diff --git a/db/.cmp.kpt b/db/.cmp.kpt index 8d7e5c6..5fd0396 100644 Binary files a/db/.cmp.kpt and b/db/.cmp.kpt differ diff --git a/db/logic_util_heursitic.dat b/db/logic_util_heursitic.dat index e1be902..3e43beb 100644 Binary files a/db/logic_util_heursitic.dat and b/db/logic_util_heursitic.dat differ diff --git a/db/prev_cmp_spectrum.qmsg b/db/prev_cmp_spectrum.qmsg index 950cfe7..65973c7 100644 --- a/db/prev_cmp_spectrum.qmsg +++ b/db/prev_cmp_spectrum.qmsg @@ -1,65 +1,65 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648828489178 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648828489179 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Apr 1 18:54:49 2022 " "Processing started: Fri Apr 1 18:54:49 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648828489179 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648828489179 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum " "Command: quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648828489179 ""} -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1648828489379 ""} -{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\".\"; expecting a direction spectrum.sv(6) " "Verilog HDL syntax error at spectrum.sv(6) near text \".\"; expecting a direction" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 6 0 0 } } } 0 10170 "Verilog HDL syntax error at %2!s! near text %1!s!" 0 0 "Quartus II" 0 -1 1648828489447 ""} -{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "spectrum spectrum.sv(1) " "Ignored design unit \"spectrum\" at spectrum.sv(1) due to previous errors" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 0 0 } } } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Quartus II" 0 -1 1648828489448 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "spectrum.sv 0 0 " "Found 0 design units, including 0 entities, in source file spectrum.sv" { } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489449 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rom0.v 1 1 " "Found 1 design units, including 1 entities, in source file rom0.v" { { "Info" "ISGN_ENTITY_NAME" "1 rom0 " "Found entity 1: rom0" { } { { "rom0.v" "" { Text "/home/benny/work/fpga/spectrum/rom0.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489454 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489454 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram16.v 1 1 " "Found 1 design units, including 1 entities, in source file ram16.v" { { "Info" "ISGN_ENTITY_NAME" "1 ram16 " "Found entity 1: ram16" { } { { "ram16.v" "" { Text "/home/benny/work/fpga/spectrum/ram16.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489455 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489455 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram32.v 1 1 " "Found 1 design units, including 1 entities, in source file ram32.v" { { "Info" "ISGN_ENTITY_NAME" "1 ram32 " "Found entity 1: ram32" { } { { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489456 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489456 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pll.v 1 1 " "Found 1 design units, including 1 entities, in source file pll.v" { { "Info" "ISGN_ENTITY_NAME" "1 pll " "Found entity 1: pll" { } { { "pll.v" "" { Text "/home/benny/work/fpga/spectrum/pll.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489457 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489457 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu " "Found entity 1: alu" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489459 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489459 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_bit_select.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_bit_select.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_bit_select " "Found entity 1: alu_bit_select" { } { { "cpu/alu/alu_bit_select.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_bit_select.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489459 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489459 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_control.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_control " "Found entity 1: alu_control" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489460 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489460 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_core.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_core.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_core " "Found entity 1: alu_core" { } { { "cpu/alu/alu_core.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_core.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489461 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489461 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_flags.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_flags.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_flags " "Found entity 1: alu_flags" { } { { "cpu/alu/alu_flags.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_flags.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489462 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489462 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_2.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_2.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_2 " "Found entity 1: alu_mux_2" { } { { "cpu/alu/alu_mux_2.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_2.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489463 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489463 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_2z.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_2z.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_2z " "Found entity 1: alu_mux_2z" { } { { "cpu/alu/alu_mux_2z.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_2z.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489464 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489464 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_3z.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_3z.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_3z " "Found entity 1: alu_mux_3z" { } { { "cpu/alu/alu_mux_3z.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_3z.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489464 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489464 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_4.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_4.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_4 " "Found entity 1: alu_mux_4" { } { { "cpu/alu/alu_mux_4.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_4.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489465 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489465 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_8.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_8.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_8 " "Found entity 1: alu_mux_8" { } { { "cpu/alu/alu_mux_8.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_8.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489466 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489466 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_prep_daa.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_prep_daa.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_prep_daa " "Found entity 1: alu_prep_daa" { } { { "cpu/alu/alu_prep_daa.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_prep_daa.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489466 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489466 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_select.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_select.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_select " "Found entity 1: alu_select" { } { { "cpu/alu/alu_select.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_select.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489467 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489467 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_shifter_core.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_shifter_core.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_shifter_core " "Found entity 1: alu_shifter_core" { } { { "cpu/alu/alu_shifter_core.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_shifter_core.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489468 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489468 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_slice.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_slice.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_slice " "Found entity 1: alu_slice" { } { { "cpu/alu/alu_slice.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_slice.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489469 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489469 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/clk_delay.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/clk_delay.v" { { "Info" "ISGN_ENTITY_NAME" "1 clk_delay " "Found entity 1: clk_delay" { } { { "cpu/control/clk_delay.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/clk_delay.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489470 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489470 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/decode_state.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/decode_state.v" { { "Info" "ISGN_ENTITY_NAME" "1 decode_state " "Found entity 1: decode_state" { } { { "cpu/control/decode_state.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/decode_state.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489471 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489471 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/execute.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/execute.v" { { "Info" "ISGN_ENTITY_NAME" "1 execute " "Found entity 1: execute" { } { { "cpu/control/execute.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/execute.v" 25 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489497 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489497 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/interrupts.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/interrupts.v" { { "Info" "ISGN_ENTITY_NAME" "1 interrupts " "Found entity 1: interrupts" { } { { "cpu/control/interrupts.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/interrupts.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489498 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489498 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/ir.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/ir.v" { { "Info" "ISGN_ENTITY_NAME" "1 ir " "Found entity 1: ir" { } { { "cpu/control/ir.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/ir.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489499 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489499 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/memory_ifc.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/memory_ifc.v" { { "Info" "ISGN_ENTITY_NAME" "1 memory_ifc " "Found entity 1: memory_ifc" { } { { "cpu/control/memory_ifc.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/memory_ifc.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489500 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489500 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/pin_control.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/pin_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 pin_control " "Found entity 1: pin_control" { } { { "cpu/control/pin_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/pin_control.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489501 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489501 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/pla_decode.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/pla_decode.v" { { "Info" "ISGN_ENTITY_NAME" "1 pla_decode " "Found entity 1: pla_decode" { } { { "cpu/control/pla_decode.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/pla_decode.v" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489502 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489502 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/resets.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/resets.v" { { "Info" "ISGN_ENTITY_NAME" "1 resets " "Found entity 1: resets" { } { { "cpu/control/resets.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/resets.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489503 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489503 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/sequencer.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/sequencer.v" { { "Info" "ISGN_ENTITY_NAME" "1 sequencer " "Found entity 1: sequencer" { } { { "cpu/control/sequencer.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/sequencer.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489504 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489504 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/address_latch.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/address_latch.v" { { "Info" "ISGN_ENTITY_NAME" "1 address_latch " "Found entity 1: address_latch" { } { { "cpu/bus/address_latch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_latch.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489505 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489505 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/address_mux.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/address_mux.v" { { "Info" "ISGN_ENTITY_NAME" "1 address_mux " "Found entity 1: address_mux" { } { { "cpu/bus/address_mux.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_mux.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489506 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489506 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/address_pins.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/address_pins.v" { { "Info" "ISGN_ENTITY_NAME" "1 address_pins " "Found entity 1: address_pins" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489506 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489506 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/bus_control.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/bus_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 bus_control " "Found entity 1: bus_control" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489507 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489507 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/bus_switch.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/bus_switch.v" { { "Info" "ISGN_ENTITY_NAME" "1 bus_switch " "Found entity 1: bus_switch" { } { { "cpu/bus/bus_switch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_switch.v" 12 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489508 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489508 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/control_pins_n.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/control_pins_n.v" { { "Info" "ISGN_ENTITY_NAME" "1 control_pins_n " "Found entity 1: control_pins_n" { } { { "cpu/bus/control_pins_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/control_pins_n.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489509 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489509 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/data_pins.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/data_pins.v" { { "Info" "ISGN_ENTITY_NAME" "1 data_pins " "Found entity 1: data_pins" { } { { "cpu/bus/data_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_pins.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489510 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489510 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/data_switch.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/data_switch.v" { { "Info" "ISGN_ENTITY_NAME" "1 data_switch " "Found entity 1: data_switch" { } { { "cpu/bus/data_switch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489510 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489510 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/data_switch_mask.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/data_switch_mask.v" { { "Info" "ISGN_ENTITY_NAME" "1 data_switch_mask " "Found entity 1: data_switch_mask" { } { { "cpu/bus/data_switch_mask.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch_mask.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489511 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489511 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/inc_dec.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/inc_dec.v" { { "Info" "ISGN_ENTITY_NAME" "1 inc_dec " "Found entity 1: inc_dec" { } { { "cpu/bus/inc_dec.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/inc_dec.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489512 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489512 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/inc_dec_2bit.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/inc_dec_2bit.v" { { "Info" "ISGN_ENTITY_NAME" "1 inc_dec_2bit " "Found entity 1: inc_dec_2bit" { } { { "cpu/bus/inc_dec_2bit.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/inc_dec_2bit.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489513 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489513 ""} -{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "nRESET nreset z80_top_direct_n.v(19) " "Verilog HDL Declaration information at z80_top_direct_n.v(19): object \"nRESET\" differs only in case from object \"nreset\" in the same scope" { } { { "cpu/toplevel/z80_top_direct_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 19 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1648828489515 ""} -{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CLK clk z80_top_direct_n.v(22) " "Verilog HDL Declaration information at z80_top_direct_n.v(22): object \"CLK\" differs only in case from object \"clk\" in the same scope" { } { { "cpu/toplevel/z80_top_direct_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1648828489515 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/toplevel/z80_top_direct_n.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/toplevel/z80_top_direct_n.v" { { "Info" "ISGN_ENTITY_NAME" "1 z80_top_direct_n " "Found entity 1: z80_top_direct_n" { } { { "cpu/toplevel/z80_top_direct_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 6 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489515 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489515 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/registers/reg_control.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/registers/reg_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 reg_control " "Found entity 1: reg_control" { } { { "cpu/registers/reg_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_control.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489516 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489516 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/registers/reg_file.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/registers/reg_file.v" { { "Info" "ISGN_ENTITY_NAME" "1 reg_file " "Found entity 1: reg_file" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489518 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489518 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/registers/reg_latch.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/registers/reg_latch.v" { { "Info" "ISGN_ENTITY_NAME" "1 reg_latch " "Found entity 1: reg_latch" { } { { "cpu/registers/reg_latch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_latch.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489519 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489519 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/clocks.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/clocks.sv" { { "Info" "ISGN_ENTITY_NAME" "1 clocks " "Found entity 1: clocks" { } { { "ula/clocks.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/clocks.sv" 26 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489519 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489519 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/zx_kbd.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/zx_kbd.sv" { { "Info" "ISGN_ENTITY_NAME" "1 zx_keyboard " "Found entity 1: zx_keyboard" { } { { "ula/zx_kbd.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/zx_kbd.sv" 38 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489520 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489520 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/video.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/video.sv" { { "Info" "ISGN_ENTITY_NAME" "1 video " "Found entity 1: video" { } { { "ula/video.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/video.sv" 26 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489521 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489521 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/ula.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/ula.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ula " "Found entity 1: ula" { } { { "ula/ula.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 20 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489522 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489522 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/ps2_kbd.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/ps2_kbd.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ps2_keyboard " "Found entity 1: ps2_keyboard" { } { { "ula/ps2_kbd.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/ps2_kbd.sv" 20 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489523 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489523 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/i2c_loader.vhd 2 1 " "Found 2 design units, including 1 entities, in source file ula/i2c_loader.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 i2c_loader-i2c_loader_arch " "Found design unit 1: i2c_loader-i2c_loader_arch" { } { { "ula/i2c_loader.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2c_loader.vhd" 64 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489823 ""} { "Info" "ISGN_ENTITY_NAME" "1 i2c_loader " "Found entity 1: i2c_loader" { } { { "ula/i2c_loader.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2c_loader.vhd" 41 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489823 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489823 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/i2s_intf.vhd 2 1 " "Found 2 design units, including 1 entities, in source file ula/i2s_intf.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 i2s_intf-i2s_intf_arch " "Found design unit 1: i2s_intf-i2s_intf_arch" { } { { "ula/i2s_intf.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2s_intf.vhd" 82 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489824 ""} { "Info" "ISGN_ENTITY_NAME" "1 i2s_intf " "Found entity 1: i2s_intf" { } { { "ula/i2s_intf.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2s_intf.vhd" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489824 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489824 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rom_scr.v 1 1 " "Found 1 design units, including 1 entities, in source file rom_scr.v" { { "Info" "ISGN_ENTITY_NAME" "1 rom_scr " "Found entity 1: rom_scr" { } { { "rom_scr.v" "" { Text "/home/benny/work/fpga/spectrum/rom_scr.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489827 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489827 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pll_video.v 1 1 " "Found 1 design units, including 1 entities, in source file pll_video.v" { { "Info" "ISGN_ENTITY_NAME" "1 pll_video " "Found entity 1: pll_video" { } { { "pll_video.v" "" { Text "/home/benny/work/fpga/spectrum/pll_video.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489828 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489828 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram_video.v 1 1 " "Found 1 design units, including 1 entities, in source file ram_video.v" { { "Info" "ISGN_ENTITY_NAME" "1 ram_video " "Found entity 1: ram_video" { } { { "ram_video.v" "" { Text "/home/benny/work/fpga/spectrum/ram_video.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828489829 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828489829 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/benny/work/fpga/spectrum/output_files/spectrum.map.smsg " "Generated suppressed messages file /home/benny/work/fpga/spectrum/output_files/spectrum.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1648828489902 ""} -{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 2 s 1 Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was unsuccessful. 2 errors, 1 warning" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "397 " "Peak virtual memory: 397 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648828489948 ""} { "Error" "EQEXE_END_BANNER_TIME" "Fri Apr 1 18:54:49 2022 " "Processing ended: Fri Apr 1 18:54:49 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648828489948 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648828489948 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648828489948 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648828489948 ""} -{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 4 s 1 " "Quartus II Full Compilation was unsuccessful. 4 errors, 1 warning" { } { } 0 293001 "Quartus II %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648828490035 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648903952061 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648903952062 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Apr 2 15:52:31 2022 " "Processing started: Sat Apr 2 15:52:31 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648903952062 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648903952062 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum " "Command: quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648903952062 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1648903952246 ""} +{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\"/\"; expecting \"end\" spectrum.sv(112) " "Verilog HDL syntax error at spectrum.sv(112) near text \"/\"; expecting \"end\"" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 112 0 0 } } } 0 10170 "Verilog HDL syntax error at %2!s! near text %1!s!" 0 0 "Quartus II" 0 -1 1648903952313 ""} +{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "spectrum spectrum.sv(1) " "Ignored design unit \"spectrum\" at spectrum.sv(1) due to previous errors" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 0 0 } } } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Quartus II" 0 -1 1648903952313 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "spectrum.sv 0 0 " "Found 0 design units, including 0 entities, in source file spectrum.sv" { } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952314 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rom0.v 1 1 " "Found 1 design units, including 1 entities, in source file rom0.v" { { "Info" "ISGN_ENTITY_NAME" "1 rom0 " "Found entity 1: rom0" { } { { "rom0.v" "" { Text "/home/benny/work/fpga/spectrum/rom0.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952316 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952316 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram16.v 1 1 " "Found 1 design units, including 1 entities, in source file ram16.v" { { "Info" "ISGN_ENTITY_NAME" "1 ram16 " "Found entity 1: ram16" { } { { "ram16.v" "" { Text "/home/benny/work/fpga/spectrum/ram16.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952317 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952317 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram32.v 1 1 " "Found 1 design units, including 1 entities, in source file ram32.v" { { "Info" "ISGN_ENTITY_NAME" "1 ram32 " "Found entity 1: ram32" { } { { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952318 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952318 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pll.v 1 1 " "Found 1 design units, including 1 entities, in source file pll.v" { { "Info" "ISGN_ENTITY_NAME" "1 pll " "Found entity 1: pll" { } { { "pll.v" "" { Text "/home/benny/work/fpga/spectrum/pll.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952319 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952319 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu " "Found entity 1: alu" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952321 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952321 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_bit_select.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_bit_select.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_bit_select " "Found entity 1: alu_bit_select" { } { { "cpu/alu/alu_bit_select.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_bit_select.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952322 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952322 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_control.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_control " "Found entity 1: alu_control" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952322 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952322 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_core.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_core.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_core " "Found entity 1: alu_core" { } { { "cpu/alu/alu_core.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_core.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952323 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952323 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_flags.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_flags.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_flags " "Found entity 1: alu_flags" { } { { "cpu/alu/alu_flags.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_flags.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952324 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952324 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_2.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_2.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_2 " "Found entity 1: alu_mux_2" { } { { "cpu/alu/alu_mux_2.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_2.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952325 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952325 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_2z.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_2z.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_2z " "Found entity 1: alu_mux_2z" { } { { "cpu/alu/alu_mux_2z.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_2z.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952326 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952326 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_3z.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_3z.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_3z " "Found entity 1: alu_mux_3z" { } { { "cpu/alu/alu_mux_3z.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_3z.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952326 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952326 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_4.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_4.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_4 " "Found entity 1: alu_mux_4" { } { { "cpu/alu/alu_mux_4.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_4.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952327 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952327 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_8.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_8.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_8 " "Found entity 1: alu_mux_8" { } { { "cpu/alu/alu_mux_8.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_8.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952328 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952328 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_prep_daa.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_prep_daa.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_prep_daa " "Found entity 1: alu_prep_daa" { } { { "cpu/alu/alu_prep_daa.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_prep_daa.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952329 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952329 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_select.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_select.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_select " "Found entity 1: alu_select" { } { { "cpu/alu/alu_select.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_select.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952329 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952329 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_shifter_core.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_shifter_core.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_shifter_core " "Found entity 1: alu_shifter_core" { } { { "cpu/alu/alu_shifter_core.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_shifter_core.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952330 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952330 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_slice.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_slice.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_slice " "Found entity 1: alu_slice" { } { { "cpu/alu/alu_slice.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_slice.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952331 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952331 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/clk_delay.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/clk_delay.v" { { "Info" "ISGN_ENTITY_NAME" "1 clk_delay " "Found entity 1: clk_delay" { } { { "cpu/control/clk_delay.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/clk_delay.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952332 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952332 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/decode_state.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/decode_state.v" { { "Info" "ISGN_ENTITY_NAME" "1 decode_state " "Found entity 1: decode_state" { } { { "cpu/control/decode_state.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/decode_state.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952333 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952333 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/execute.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/execute.v" { { "Info" "ISGN_ENTITY_NAME" "1 execute " "Found entity 1: execute" { } { { "cpu/control/execute.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/execute.v" 25 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952357 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952357 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/interrupts.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/interrupts.v" { { "Info" "ISGN_ENTITY_NAME" "1 interrupts " "Found entity 1: interrupts" { } { { "cpu/control/interrupts.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/interrupts.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952358 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952358 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/ir.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/ir.v" { { "Info" "ISGN_ENTITY_NAME" "1 ir " "Found entity 1: ir" { } { { "cpu/control/ir.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/ir.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952359 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952359 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/memory_ifc.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/memory_ifc.v" { { "Info" "ISGN_ENTITY_NAME" "1 memory_ifc " "Found entity 1: memory_ifc" { } { { "cpu/control/memory_ifc.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/memory_ifc.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952360 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952360 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/pin_control.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/pin_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 pin_control " "Found entity 1: pin_control" { } { { "cpu/control/pin_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/pin_control.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952361 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952361 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/pla_decode.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/pla_decode.v" { { "Info" "ISGN_ENTITY_NAME" "1 pla_decode " "Found entity 1: pla_decode" { } { { "cpu/control/pla_decode.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/pla_decode.v" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952363 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952363 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/resets.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/resets.v" { { "Info" "ISGN_ENTITY_NAME" "1 resets " "Found entity 1: resets" { } { { "cpu/control/resets.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/resets.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952363 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952363 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/sequencer.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/sequencer.v" { { "Info" "ISGN_ENTITY_NAME" "1 sequencer " "Found entity 1: sequencer" { } { { "cpu/control/sequencer.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/sequencer.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952364 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952364 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/address_latch.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/address_latch.v" { { "Info" "ISGN_ENTITY_NAME" "1 address_latch " "Found entity 1: address_latch" { } { { "cpu/bus/address_latch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_latch.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952365 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952365 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/address_mux.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/address_mux.v" { { "Info" "ISGN_ENTITY_NAME" "1 address_mux " "Found entity 1: address_mux" { } { { "cpu/bus/address_mux.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_mux.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952366 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952366 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/address_pins.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/address_pins.v" { { "Info" "ISGN_ENTITY_NAME" "1 address_pins " "Found entity 1: address_pins" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952367 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952367 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/bus_control.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/bus_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 bus_control " "Found entity 1: bus_control" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952367 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952367 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/bus_switch.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/bus_switch.v" { { "Info" "ISGN_ENTITY_NAME" "1 bus_switch " "Found entity 1: bus_switch" { } { { "cpu/bus/bus_switch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_switch.v" 12 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952368 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952368 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/control_pins_n.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/control_pins_n.v" { { "Info" "ISGN_ENTITY_NAME" "1 control_pins_n " "Found entity 1: control_pins_n" { } { { "cpu/bus/control_pins_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/control_pins_n.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952369 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952369 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/data_pins.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/data_pins.v" { { "Info" "ISGN_ENTITY_NAME" "1 data_pins " "Found entity 1: data_pins" { } { { "cpu/bus/data_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_pins.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952370 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952370 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/data_switch.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/data_switch.v" { { "Info" "ISGN_ENTITY_NAME" "1 data_switch " "Found entity 1: data_switch" { } { { "cpu/bus/data_switch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952371 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952371 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/data_switch_mask.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/data_switch_mask.v" { { "Info" "ISGN_ENTITY_NAME" "1 data_switch_mask " "Found entity 1: data_switch_mask" { } { { "cpu/bus/data_switch_mask.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch_mask.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952371 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952371 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/inc_dec.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/inc_dec.v" { { "Info" "ISGN_ENTITY_NAME" "1 inc_dec " "Found entity 1: inc_dec" { } { { "cpu/bus/inc_dec.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/inc_dec.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952372 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952372 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/inc_dec_2bit.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/inc_dec_2bit.v" { { "Info" "ISGN_ENTITY_NAME" "1 inc_dec_2bit " "Found entity 1: inc_dec_2bit" { } { { "cpu/bus/inc_dec_2bit.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/inc_dec_2bit.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952373 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952373 ""} +{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "nRESET nreset z80_top_direct_n.v(19) " "Verilog HDL Declaration information at z80_top_direct_n.v(19): object \"nRESET\" differs only in case from object \"nreset\" in the same scope" { } { { "cpu/toplevel/z80_top_direct_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 19 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1648903952375 ""} +{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CLK clk z80_top_direct_n.v(22) " "Verilog HDL Declaration information at z80_top_direct_n.v(22): object \"CLK\" differs only in case from object \"clk\" in the same scope" { } { { "cpu/toplevel/z80_top_direct_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1648903952375 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/toplevel/z80_top_direct_n.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/toplevel/z80_top_direct_n.v" { { "Info" "ISGN_ENTITY_NAME" "1 z80_top_direct_n " "Found entity 1: z80_top_direct_n" { } { { "cpu/toplevel/z80_top_direct_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 6 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952375 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952375 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/registers/reg_control.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/registers/reg_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 reg_control " "Found entity 1: reg_control" { } { { "cpu/registers/reg_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_control.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952376 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952376 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/registers/reg_file.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/registers/reg_file.v" { { "Info" "ISGN_ENTITY_NAME" "1 reg_file " "Found entity 1: reg_file" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952378 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952378 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/registers/reg_latch.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/registers/reg_latch.v" { { "Info" "ISGN_ENTITY_NAME" "1 reg_latch " "Found entity 1: reg_latch" { } { { "cpu/registers/reg_latch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_latch.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952379 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952379 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/clocks.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/clocks.sv" { { "Info" "ISGN_ENTITY_NAME" "1 clocks " "Found entity 1: clocks" { } { { "ula/clocks.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/clocks.sv" 26 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952379 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952379 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/zx_kbd.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/zx_kbd.sv" { { "Info" "ISGN_ENTITY_NAME" "1 zx_keyboard " "Found entity 1: zx_keyboard" { } { { "ula/zx_kbd.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/zx_kbd.sv" 38 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952380 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952380 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/video.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/video.sv" { { "Info" "ISGN_ENTITY_NAME" "1 video " "Found entity 1: video" { } { { "ula/video.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/video.sv" 26 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952382 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952382 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/ula.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/ula.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ula " "Found entity 1: ula" { } { { "ula/ula.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 20 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952382 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952382 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/ps2_kbd.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/ps2_kbd.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ps2_keyboard " "Found entity 1: ps2_keyboard" { } { { "ula/ps2_kbd.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/ps2_kbd.sv" 20 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952383 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952383 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/i2c_loader.vhd 2 1 " "Found 2 design units, including 1 entities, in source file ula/i2c_loader.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 i2c_loader-i2c_loader_arch " "Found design unit 1: i2c_loader-i2c_loader_arch" { } { { "ula/i2c_loader.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2c_loader.vhd" 64 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952676 ""} { "Info" "ISGN_ENTITY_NAME" "1 i2c_loader " "Found entity 1: i2c_loader" { } { { "ula/i2c_loader.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2c_loader.vhd" 41 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952676 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952676 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/i2s_intf.vhd 2 1 " "Found 2 design units, including 1 entities, in source file ula/i2s_intf.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 i2s_intf-i2s_intf_arch " "Found design unit 1: i2s_intf-i2s_intf_arch" { } { { "ula/i2s_intf.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2s_intf.vhd" 82 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952677 ""} { "Info" "ISGN_ENTITY_NAME" "1 i2s_intf " "Found entity 1: i2s_intf" { } { { "ula/i2s_intf.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2s_intf.vhd" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952677 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952677 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rom_scr.v 1 1 " "Found 1 design units, including 1 entities, in source file rom_scr.v" { { "Info" "ISGN_ENTITY_NAME" "1 rom_scr " "Found entity 1: rom_scr" { } { { "rom_scr.v" "" { Text "/home/benny/work/fpga/spectrum/rom_scr.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952680 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952680 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pll_video.v 1 1 " "Found 1 design units, including 1 entities, in source file pll_video.v" { { "Info" "ISGN_ENTITY_NAME" "1 pll_video " "Found entity 1: pll_video" { } { { "pll_video.v" "" { Text "/home/benny/work/fpga/spectrum/pll_video.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952681 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952681 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram_video.v 1 1 " "Found 1 design units, including 1 entities, in source file ram_video.v" { { "Info" "ISGN_ENTITY_NAME" "1 ram_video " "Found entity 1: ram_video" { } { { "ram_video.v" "" { Text "/home/benny/work/fpga/spectrum/ram_video.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903952682 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903952682 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/benny/work/fpga/spectrum/output_files/spectrum.map.smsg " "Generated suppressed messages file /home/benny/work/fpga/spectrum/output_files/spectrum.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1648903952751 ""} +{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 2 s 1 Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was unsuccessful. 2 errors, 1 warning" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "397 " "Peak virtual memory: 397 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648903952793 ""} { "Error" "EQEXE_END_BANNER_TIME" "Sat Apr 2 15:52:32 2022 " "Processing ended: Sat Apr 2 15:52:32 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648903952793 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648903952793 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648903952793 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648903952793 ""} +{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 4 s 1 " "Quartus II Full Compilation was unsuccessful. 4 errors, 1 warning" { } { } 0 293001 "Quartus II %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648903952889 ""} diff --git a/db/spectrum.(0).cnf.cdb b/db/spectrum.(0).cnf.cdb index b7d6ba3..92625b7 100644 Binary files a/db/spectrum.(0).cnf.cdb and b/db/spectrum.(0).cnf.cdb differ diff --git a/db/spectrum.(0).cnf.hdb b/db/spectrum.(0).cnf.hdb index 9fe7f0d..52a10b2 100644 Binary files a/db/spectrum.(0).cnf.hdb and b/db/spectrum.(0).cnf.hdb differ diff --git a/db/spectrum.asm.qmsg b/db/spectrum.asm.qmsg index efa6ad6..b7e81f3 100644 --- a/db/spectrum.asm.qmsg +++ b/db/spectrum.asm.qmsg @@ -1,6 +1,6 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648828541709 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648828541710 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Apr 1 18:55:41 2022 " "Processing started: Fri Apr 1 18:55:41 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648828541710 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1648828541710 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1648828541710 ""} -{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1648828542963 ""} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1648828542993 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "385 " "Peak virtual memory: 385 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648828543318 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 1 18:55:43 2022 " "Processing ended: Fri Apr 1 18:55:43 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648828543318 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648828543318 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648828543318 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1648828543318 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648904015094 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648904015094 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Apr 2 15:53:34 2022 " "Processing started: Sat Apr 2 15:53:34 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648904015094 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1648904015094 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1648904015095 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1648904016287 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1648904016316 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "385 " "Peak virtual memory: 385 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648904016628 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 2 15:53:36 2022 " "Processing ended: Sat Apr 2 15:53:36 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648904016628 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648904016628 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648904016628 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1648904016628 ""} diff --git a/db/spectrum.asm.rdb b/db/spectrum.asm.rdb index efa9242..0df0619 100644 Binary files a/db/spectrum.asm.rdb and b/db/spectrum.asm.rdb differ diff --git a/db/spectrum.asm_labs.ddb b/db/spectrum.asm_labs.ddb index 2d8a18e..f3bbe8c 100644 Binary files a/db/spectrum.asm_labs.ddb and b/db/spectrum.asm_labs.ddb differ diff --git a/db/spectrum.cmp.bpm b/db/spectrum.cmp.bpm index e4349f1..8816698 100644 Binary files a/db/spectrum.cmp.bpm and b/db/spectrum.cmp.bpm differ diff --git a/db/spectrum.cmp.cdb b/db/spectrum.cmp.cdb index decd773..9f5d19d 100644 Binary files a/db/spectrum.cmp.cdb and b/db/spectrum.cmp.cdb differ diff --git a/db/spectrum.cmp.hdb b/db/spectrum.cmp.hdb index 8694cf0..ba176e2 100644 Binary files a/db/spectrum.cmp.hdb and b/db/spectrum.cmp.hdb differ diff --git a/db/spectrum.cmp.idb b/db/spectrum.cmp.idb index 756f6f1..e5479cf 100644 Binary files a/db/spectrum.cmp.idb and b/db/spectrum.cmp.idb differ diff --git a/db/spectrum.cmp.rdb b/db/spectrum.cmp.rdb index 5f8f53f..9bc0e7f 100644 Binary files a/db/spectrum.cmp.rdb and b/db/spectrum.cmp.rdb differ diff --git a/db/spectrum.eda.qmsg b/db/spectrum.eda.qmsg index 0d8b1e0..0039b26 100644 --- a/db/spectrum.eda.qmsg +++ b/db/spectrum.eda.qmsg @@ -1,12 +1,12 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648828550447 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 32-bit " "Running Quartus II 32-bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648828550448 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Apr 1 18:55:50 2022 " "Processing started: Fri Apr 1 18:55:50 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648828550448 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648828550448 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648828550448 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_slow.vo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_slow.vo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648828551371 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_slow.vo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_slow.vo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648828551694 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_fast.vo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_fast.vo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648828552017 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum.vo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum.vo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648828552344 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_v_slow.sdo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_v_slow.sdo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648828552617 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_v_slow.sdo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_v_slow.sdo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648828552883 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_v_fast.sdo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_v_fast.sdo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648828553143 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_v.sdo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_v.sdo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648828553404 ""} -{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "380 " "Peak virtual memory: 380 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648828553503 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 1 18:55:53 2022 " "Processing ended: Fri Apr 1 18:55:53 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648828553503 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648828553503 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648828553503 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648828553503 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648904023213 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 32-bit " "Running Quartus II 32-bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648904023214 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Apr 2 15:53:43 2022 " "Processing started: Sat Apr 2 15:53:43 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648904023214 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648904023214 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648904023215 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_slow.vo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_slow.vo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648904024089 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_slow.vo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_slow.vo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648904024403 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_fast.vo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_fast.vo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648904024715 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum.vo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum.vo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648904025028 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_v_slow.sdo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_v_slow.sdo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648904025280 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_v_slow.sdo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_v_slow.sdo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648904025528 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_v_fast.sdo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_v_fast.sdo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648904025776 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_v.sdo /home/benny/work/fpga/spectrum/simulation/modelsim/ simulation " "Generated file spectrum_v.sdo in folder \"/home/benny/work/fpga/spectrum/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648904026024 ""} +{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "380 " "Peak virtual memory: 380 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648904026119 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 2 15:53:46 2022 " "Processing ended: Sat Apr 2 15:53:46 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648904026119 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648904026119 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648904026119 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648904026119 ""} diff --git a/db/spectrum.fit.qmsg b/db/spectrum.fit.qmsg index db1e7f9..d2c2e0b 100644 --- a/db/spectrum.fit.qmsg +++ b/db/spectrum.fit.qmsg @@ -1,72 +1,72 @@ -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1648828519240 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "spectrum EP4CE22F17C6 " "Selected device EP4CE22F17C6 for design \"spectrum\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1648828519256 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648828519297 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648828519298 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648828519298 ""} -{ "Info" "ICUT_CUT_PLL_COMPUTATION_SUCCESS" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 Cyclone IV E PLL " "Implemented PLL \"ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1\" as Cyclone IV E PLL type" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[0\] 141 280 0 0 " "Implementing clock multiplication of 141, clock division of 280, and phase shift of 0 degrees (0 ps) for ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[0\] port" { } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 45 -1 0 } } { "" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1221 9662 10382 0} } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Quartus II" 0 -1 1648828519365 ""} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[1\] 47 168 0 0 " "Implementing clock multiplication of 47, clock division of 168, and phase shift of 0 degrees (0 ps) for ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[1\] port" { } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 45 -1 0 } } { "" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1222 9662 10382 0} } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Quartus II" 0 -1 1648828519365 ""} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[2\] 47 98 0 0 " "Implementing clock multiplication of 47, clock division of 98, and phase shift of 0 degrees (0 ps) for ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[2\] port" { } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 45 -1 0 } } { "" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1223 9662 10382 0} } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Quartus II" 0 -1 1648828519365 ""} } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 45 -1 0 } } { "" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1221 9662 10382 0} } } } } 0 15535 "Implemented %3!s! \"%1!s!\" as %2!s! PLL type" 0 0 "Fitter" 0 -1 1648828519365 ""} -{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1648828519447 ""} -{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1648828519460 ""} -{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE10F17C6 " "Device EP4CE10F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648828519687 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE6F17C6 " "Device EP4CE6F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648828519687 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE15F17C6 " "Device EP4CE15F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648828519687 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1648828519687 ""} -{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ C1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location C1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 5274 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648828519694 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ D2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location D2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 5276 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648828519694 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ H1 " "Pin ~ALTERA_DCLK~ is reserved at location H1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 5278 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648828519694 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ H2 " "Pin ~ALTERA_DATA0~ is reserved at location H2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 5280 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648828519694 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ F16 " "Pin ~ALTERA_nCEO~ is reserved at location F16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 5282 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648828519694 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1648828519694 ""} -{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1648828519697 ""} -{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." { } { } 0 176045 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "Fitter" 0 -1 1648828519704 ""} -{ "Info" "ISTA_SDC_FOUND" "spectrum.sdc " "Reading SDC File: 'spectrum.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1648828520881 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 12 KEY1 port " "Ignored filter at spectrum.sdc(12): KEY1 could not be matched with a port" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 12 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648828520890 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "create_clock spectrum.sdc 12 Argument is an empty collection " "Ignored create_clock at spectrum.sdc(12): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "create_clock -name KEY1 -period 10.000 \[get_ports \{KEY1\}\] " "create_clock -name KEY1 -period 10.000 \[get_ports \{KEY1\}\]" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 12 -1 0 } } } 0 332050 "%1!s!" 0 0 "Quartus II" 0 -1 1648828520890 ""} } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 12 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Fitter" 0 -1 1648828520890 ""} -{ "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "Deriving PLL clocks " "Deriving PLL clocks" { { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 280 -multiply_by 141 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 280 -multiply_by 141 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648828520892 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 168 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} " "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 168 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648828520892 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 98 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} " "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 98 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648828520892 ""} } { } 0 332110 "%1!s!" 0 0 "Fitter" 0 -1 1648828520892 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 21 ula_\|clocks_\|clk_cpu\|regout pin " "Ignored filter at spectrum.sdc(21): ula_\|clocks_\|clk_cpu\|regout could not be matched with a pin" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 21 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648828520892 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "create_generated_clock spectrum.sdc 21 Argument is an empty collection " "Ignored create_generated_clock at spectrum.sdc(21): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "create_generated_clock -name clk_cpu -source \[get_pins \{ula_\|clocks_\|clk_cpu\|clk\}\] -divide_by 4 \[get_pins \{ula_\|clocks_\|clk_cpu\|regout\}\] " "create_generated_clock -name clk_cpu -source \[get_pins \{ula_\|clocks_\|clk_cpu\|clk\}\] -divide_by 4 \[get_pins \{ula_\|clocks_\|clk_cpu\|regout\}\]" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 21 -1 0 } } } 0 332050 "%1!s!" 0 0 "Quartus II" 0 -1 1648828520892 ""} } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 21 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Fitter" 0 -1 1648828520892 ""} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_CALL_IS_DELAYED" "" "Clock uncertainty is not calculated until you update the timing netlist." { } { } 0 332151 "Clock uncertainty is not calculated until you update the timing netlist." 0 0 "Fitter" 0 -1 1648828520893 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 56 clk_cpu clock " "Ignored filter at spectrum.sdc(56): clk_cpu could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 56 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648828520893 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 57 KEY1 clock " "Ignored filter at spectrum.sdc(57): KEY1 could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 57 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648828520893 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 54 ula_\|pll_\|altpll_component\|pll\|clk\[0\] clock " "Ignored filter at spectrum.sdc(54): ula_\|pll_\|altpll_component\|pll\|clk\[0\] could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 54 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648828520894 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 54 ula_\|pll_\|altpll_component\|pll\|clk\[1\] clock " "Ignored filter at spectrum.sdc(54): ula_\|pll_\|altpll_component\|pll\|clk\[1\] could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 54 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648828520894 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 54 ula_\|pll_\|altpll_component\|pll\|clk\[2\] clock " "Ignored filter at spectrum.sdc(54): ula_\|pll_\|altpll_component\|pll\|clk\[2\] could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 54 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648828520894 ""} -{ "Warning" "WSTA_SCC_LOOP" "511 " "Found combinational loop of 511 nodes" { { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~3\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~22\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~22\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~22\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~9\|datac " "Node \"z80_\|alu_control_\|db\[0\]~9\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~9\|combout " "Node \"z80_\|alu_control_\|db\[0\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~12\|dataa " "Node \"z80_\|alu_control_\|db\[0\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~12\|combout " "Node \"z80_\|alu_control_\|db\[0\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~12\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~12\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~17\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~17\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~22\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~19\|datab " "Node \"z80_\|alu_\|db\[0\]~19\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~19\|combout " "Node \"z80_\|alu_\|db\[0\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw2_\|db_up\[0\]~0\|dataa " "Node \"z80_\|sw2_\|db_up\[0\]~0\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw2_\|db_up\[0\]~0\|combout " "Node \"z80_\|sw2_\|db_up\[0\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~9\|dataa " "Node \"z80_\|alu_control_\|db\[0\]~9\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|datac " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|combout " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|datab " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|combout " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~5\|dataa " "Node \"z80_\|alu_\|db_high\[3\]~5\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~5\|combout " "Node \"z80_\|alu_\|db_high\[3\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~6\|dataa " "Node \"z80_\|alu_\|db_high\[3\]~6\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~6\|combout " "Node \"z80_\|alu_\|db_high\[3\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~7\|datac " "Node \"z80_\|alu_\|db_high\[3\]~7\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~7\|combout " "Node \"z80_\|alu_\|db_high\[3\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~8\|dataa " "Node \"z80_\|alu_\|db_high\[3\]~8\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~8\|combout " "Node \"z80_\|alu_\|db_high\[3\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~21\|datab " "Node \"z80_\|alu_\|db\[7\]~21\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~21\|combout " "Node \"z80_\|alu_\|db\[7\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~11\|dataa " "Node \"z80_\|alu_\|db_high\[2\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~11\|combout " "Node \"z80_\|alu_\|db_high\[2\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~12\|dataa " "Node \"z80_\|alu_\|db_high\[2\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~12\|combout " "Node \"z80_\|alu_\|db_high\[2\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~13\|datac " "Node \"z80_\|alu_\|db_high\[2\]~13\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~13\|combout " "Node \"z80_\|alu_\|db_high\[2\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~14\|dataa " "Node \"z80_\|alu_\|db_high\[2\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~14\|combout " "Node \"z80_\|alu_\|db_high\[2\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~23\|datab " "Node \"z80_\|alu_\|db\[6\]~23\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~23\|combout " "Node \"z80_\|alu_\|db\[6\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~12\|datab " "Node \"z80_\|alu_\|db_high\[2\]~12\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~5\|datab " "Node \"z80_\|alu_\|db_high\[3\]~5\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~20\|dataa " "Node \"z80_\|alu_control_\|db\[6\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~20\|combout " "Node \"z80_\|alu_control_\|db\[6\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~21\|datad " "Node \"z80_\|alu_control_\|db\[6\]~21\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~21\|combout " "Node \"z80_\|alu_control_\|db\[6\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~22\|datad " "Node \"z80_\|alu_control_\|db\[6\]~22\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~22\|combout " "Node \"z80_\|alu_control_\|db\[6\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~8\|datab " "Node \"z80_\|bus_control_\|db\[6\]~8\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~8\|combout " "Node \"z80_\|bus_control_\|db\[6\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~9\|dataa " "Node \"z80_\|bus_control_\|db\[6\]~9\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~9\|combout " "Node \"z80_\|bus_control_\|db\[6\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~21\|dataa " "Node \"z80_\|alu_control_\|db\[6\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~79\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~79\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~79\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~79\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~80\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~80\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~80\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~80\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~81\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~81\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~81\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~81\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~82\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~82\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~82\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~82\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~19\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~19\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~20\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~20\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~21\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~21\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~82\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~82\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~22\|dataa " "Node \"z80_\|alu_control_\|db\[6\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~22\|dataa " "Node \"z80_\|alu_\|db\[6\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~22\|combout " "Node \"z80_\|alu_\|db\[6\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~23\|dataa " "Node \"z80_\|alu_\|db\[6\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~80\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~80\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~80\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~80\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~82\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~82\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~82\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~82\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~83\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~83\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~83\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~83\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~84\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~84\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~84\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~84\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~22\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~22\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~23\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~23\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~24\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~24\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~24\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~84\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~84\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~22\|datab " "Node \"z80_\|alu_\|db\[6\]~22\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~17\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~17\|combout " "Node \"z80_\|alu_\|db_high\[1\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~18\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~18\|combout " "Node \"z80_\|alu_\|db_high\[1\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~19\|datac " "Node \"z80_\|alu_\|db_high\[1\]~19\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~19\|combout " "Node \"z80_\|alu_\|db_high\[1\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~20\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~20\|combout " "Node \"z80_\|alu_\|db_high\[1\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~25\|datab " "Node \"z80_\|alu_\|db\[5\]~25\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~25\|combout " "Node \"z80_\|alu_\|db\[5\]~25\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~11\|datab " "Node \"z80_\|alu_\|db_high\[2\]~11\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~23\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~23\|combout " "Node \"z80_\|alu_\|db_high\[0\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~24\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~24\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~24\|combout " "Node \"z80_\|alu_\|db_high\[0\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~25\|datac " "Node \"z80_\|alu_\|db_high\[0\]~25\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~25\|combout " "Node \"z80_\|alu_\|db_high\[0\]~25\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~26\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~26\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~26\|combout " "Node \"z80_\|alu_\|db_high\[0\]~26\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~17\|datab " "Node \"z80_\|alu_\|db\[4\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~17\|combout " "Node \"z80_\|alu_\|db\[4\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~7\|dataa " "Node \"z80_\|alu_\|db_low\[3\]~7\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~7\|combout " "Node \"z80_\|alu_\|db_low\[3\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~8\|dataa " "Node \"z80_\|alu_\|db_low\[3\]~8\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~8\|combout " "Node \"z80_\|alu_\|db_low\[3\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~11\|dataa " "Node \"z80_\|alu_\|db_low\[3\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~11\|combout " "Node \"z80_\|alu_\|db_low\[3\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~25\|datac " "Node \"z80_\|alu_\|db_low\[3\]~25\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~25\|combout " "Node \"z80_\|alu_\|db_low\[3\]~25\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~10\|datab " "Node \"z80_\|alu_\|db\[3\]~10\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~10\|combout " "Node \"z80_\|alu_\|db\[3\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~11\|dataa " "Node \"z80_\|alu_\|db\[3\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~11\|combout " "Node \"z80_\|alu_\|db\[3\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~8\|datab " "Node \"z80_\|alu_\|db_low\[3\]~8\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~23\|datab " "Node \"z80_\|alu_\|db_high\[0\]~23\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~44\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~44\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~44\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~44\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~46\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~46\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~46\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~46\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~47\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~47\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~47\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~47\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~48\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~48\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~48\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~48\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~10\|dataa " "Node \"z80_\|alu_\|db\[3\]~10\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~10\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~10\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~10\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~11\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~11\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~12\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~12\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~48\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~48\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~2\|dataa " "Node \"z80_\|alu_\|db_low\[2\]~2\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~2\|combout " "Node \"z80_\|alu_\|db_low\[2\]~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~3\|dataa " "Node \"z80_\|alu_\|db_low\[2\]~3\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~3\|combout " "Node \"z80_\|alu_\|db_low\[2\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~24\|dataa " "Node \"z80_\|alu_\|db_low\[2\]~24\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~24\|combout " "Node \"z80_\|alu_\|db_low\[2\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~15\|datab " "Node \"z80_\|alu_\|db\[2\]~15\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~15\|combout " "Node \"z80_\|alu_\|db\[2\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~7\|datab " "Node \"z80_\|alu_\|db_low\[3\]~7\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~27\|datac " "Node \"z80_\|alu_control_\|db\[2\]~27\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~27\|combout " "Node \"z80_\|alu_control_\|db\[2\]~27\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~29\|datac " "Node \"z80_\|alu_control_\|db\[2\]~29\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~29\|combout " "Node \"z80_\|alu_control_\|db\[2\]~29\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~12\|datab " "Node \"z80_\|bus_control_\|db\[2\]~12\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~12\|combout " "Node \"z80_\|bus_control_\|db\[2\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~13\|dataa " "Node \"z80_\|bus_control_\|db\[2\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~13\|combout " "Node \"z80_\|bus_control_\|db\[2\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~28\|dataa " "Node \"z80_\|alu_control_\|db\[2\]~28\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~28\|combout " "Node \"z80_\|alu_control_\|db\[2\]~28\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~29\|datad " "Node \"z80_\|alu_control_\|db\[2\]~29\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~39\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~39\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~39\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~39\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~40\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~40\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~40\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~40\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~41\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~41\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~41\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~41\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~42\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~42\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~42\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~42\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~7\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~7\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~7\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~8\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~8\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~8\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~9\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~9\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~9\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~42\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~42\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[2\]~2\|dataa " "Node \"z80_\|reg_file_\|db_lo_ds\[2\]~2\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[2\]~2\|combout " "Node \"z80_\|reg_file_\|db_lo_ds\[2\]~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~28\|datad " "Node \"z80_\|alu_control_\|db\[2\]~28\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~14\|dataa " "Node \"z80_\|alu_\|db\[2\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~14\|combout " "Node \"z80_\|alu_\|db\[2\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~15\|dataa " "Node \"z80_\|alu_\|db\[2\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~35\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~35\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~35\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~35\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~37\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~37\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~37\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~37\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~38\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~38\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~38\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~38\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~39\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~39\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~39\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~39\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~7\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~7\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~7\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~8\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~8\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~8\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~9\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~9\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~9\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~39\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~39\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~14\|datab " "Node \"z80_\|alu_\|db\[2\]~14\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~3\|datab " "Node \"z80_\|alu_\|db_low\[2\]~3\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~15\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~15\|combout " "Node \"z80_\|alu_\|db_low\[1\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~16\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~16\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~16\|combout " "Node \"z80_\|alu_\|db_low\[1\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~17\|datab " "Node \"z80_\|alu_\|db_low\[1\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~17\|combout " "Node \"z80_\|alu_\|db_low\[1\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~13\|datab " "Node \"z80_\|alu_\|db\[1\]~13\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~13\|combout " "Node \"z80_\|alu_\|db\[1\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~21\|dataa " "Node \"z80_\|alu_\|db_low\[0\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~21\|combout " "Node \"z80_\|alu_\|db_low\[0\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~22\|dataa " "Node \"z80_\|alu_\|db_low\[0\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~22\|combout " "Node \"z80_\|alu_\|db_low\[0\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~23\|datab " "Node \"z80_\|alu_\|db_low\[0\]~23\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~23\|combout " "Node \"z80_\|alu_\|db_low\[0\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~18\|datab " "Node \"z80_\|alu_\|db\[0\]~18\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~18\|combout " "Node \"z80_\|alu_\|db\[0\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~19\|dataa " "Node \"z80_\|alu_\|db\[0\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~12\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~12\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~14\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~14\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~14\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~15\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~15\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~15\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~21\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~21\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~12\|datab " "Node \"z80_\|alu_\|db\[1\]~12\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~12\|combout " "Node \"z80_\|alu_\|db\[1\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~13\|dataa " "Node \"z80_\|alu_\|db\[1\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~0\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~0\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~0\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~1\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~1\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~1\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~3\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~3\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~3\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~21\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~21\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~2\|datab " "Node \"z80_\|alu_\|db_low\[2\]~2\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~16\|datab " "Node \"z80_\|alu_\|db_low\[1\]~16\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~24\|datac " "Node \"z80_\|alu_control_\|db\[1\]~24\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~24\|combout " "Node \"z80_\|alu_control_\|db\[1\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~26\|datac " "Node \"z80_\|alu_control_\|db\[1\]~26\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~26\|combout " "Node \"z80_\|alu_control_\|db\[1\]~26\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~10\|datab " "Node \"z80_\|bus_control_\|db\[1\]~10\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~10\|combout " "Node \"z80_\|bus_control_\|db\[1\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~11\|dataa " "Node \"z80_\|bus_control_\|db\[1\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~11\|combout " "Node \"z80_\|bus_control_\|db\[1\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~25\|dataa " "Node \"z80_\|alu_control_\|db\[1\]~25\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~25\|combout " "Node \"z80_\|alu_control_\|db\[1\]~25\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~26\|datad " "Node \"z80_\|alu_control_\|db\[1\]~26\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~12\|dataa " "Node \"z80_\|alu_\|db\[1\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~29\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~29\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~29\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~29\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~30\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~30\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~30\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~30\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~31\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~31\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~31\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~31\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~32\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~32\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~32\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~32\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[1\]~1\|dataa " "Node \"z80_\|reg_file_\|db_lo_ds\[1\]~1\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[1\]~1\|combout " "Node \"z80_\|reg_file_\|db_lo_ds\[1\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~25\|datad " "Node \"z80_\|alu_control_\|db\[1\]~25\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~4\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~4\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~4\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~5\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~5\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~5\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~6\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~6\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~6\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~32\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~32\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~35\|datab " "Node \"z80_\|alu_control_\|db\[3\]~35\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~35\|combout " "Node \"z80_\|alu_control_\|db\[3\]~35\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~46\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~46\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~46\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~46\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~47\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~47\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~47\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~47\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~50\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~50\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~50\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~50\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~51\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~51\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~51\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~51\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~52\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~52\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~52\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~52\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~34\|datac " "Node \"z80_\|alu_control_\|db\[3\]~34\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~34\|combout " "Node \"z80_\|alu_control_\|db\[3\]~34\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~35\|dataa " "Node \"z80_\|alu_control_\|db\[3\]~35\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~10\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~10\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~10\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~11\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~11\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~12\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~12\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~52\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~52\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~11\|datab " "Node \"z80_\|alu_\|db\[3\]~11\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[3\]~21\|datab " "Node \"z80_\|bus_control_\|db\[3\]~21\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[3\]~21\|combout " "Node \"z80_\|bus_control_\|db\[3\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[3\]~1\|dataa " "Node \"z80_\|sw1_\|db_down\[3\]~1\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[3\]~1\|combout " "Node \"z80_\|sw1_\|db_down\[3\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~34\|dataa " "Node \"z80_\|alu_control_\|db\[3\]~34\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~9\|datac " "Node \"z80_\|alu_\|db_high\[2\]~9\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~9\|combout " "Node \"z80_\|alu_\|db_high\[2\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~13\|dataa " "Node \"z80_\|alu_\|db_high\[2\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~27\|datab " "Node \"z80_\|alu_\|db_high\[3\]~27\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~27\|combout " "Node \"z80_\|alu_\|db_high\[3\]~27\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~7\|dataa " "Node \"z80_\|alu_\|db_high\[3\]~7\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~21\|datac " "Node \"z80_\|alu_\|db_high\[0\]~21\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~21\|combout " "Node \"z80_\|alu_\|db_high\[0\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~25\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~25\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~18\|datac " "Node \"z80_\|alu_\|db_low\[0\]~18\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~18\|combout " "Node \"z80_\|alu_\|db_low\[0\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~20\|dataa " "Node \"z80_\|alu_\|db_low\[0\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~20\|combout " "Node \"z80_\|alu_\|db_low\[0\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~23\|dataa " "Node \"z80_\|alu_\|db_low\[0\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~12\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~12\|combout " "Node \"z80_\|alu_\|db_low\[1\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~14\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~14\|combout " "Node \"z80_\|alu_\|db_low\[1\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~17\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~15\|datab " "Node \"z80_\|alu_\|db_high\[1\]~15\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~15\|combout " "Node \"z80_\|alu_\|db_high\[1\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~19\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~4\|datac " "Node \"z80_\|alu_\|db_low\[2\]~4\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~4\|combout " "Node \"z80_\|alu_\|db_low\[2\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~6\|dataa " "Node \"z80_\|alu_\|db_low\[2\]~6\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~6\|combout " "Node \"z80_\|alu_\|db_low\[2\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~24\|datab " "Node \"z80_\|alu_\|db_low\[2\]~24\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|datab " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|combout " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~10\|datab " "Node \"z80_\|alu_\|db_low\[3\]~10\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~10\|combout " "Node \"z80_\|alu_\|db_low\[3\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~11\|datab " "Node \"z80_\|alu_\|db_low\[3\]~11\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~24\|datab " "Node \"z80_\|alu_\|db_high\[0\]~24\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~17\|datab " "Node \"z80_\|alu_\|db_high\[1\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~62\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~62\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~62\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~62\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~64\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~64\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~64\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~64\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~65\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~65\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~65\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~65\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~66\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~66\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~66\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~66\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~16\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~16\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~16\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~17\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~17\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~18\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~18\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~66\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~66\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~16\|dataa " "Node \"z80_\|alu_\|db\[4\]~16\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~16\|combout " "Node \"z80_\|alu_\|db\[4\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~17\|dataa " "Node \"z80_\|alu_\|db\[4\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~30\|dataa " "Node \"z80_\|alu_control_\|db\[4\]~30\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~30\|combout " "Node \"z80_\|alu_control_\|db\[4\]~30\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~31\|datad " "Node \"z80_\|alu_control_\|db\[4\]~31\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~31\|combout " "Node \"z80_\|alu_control_\|db\[4\]~31\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~32\|datad " "Node \"z80_\|alu_control_\|db\[4\]~32\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~32\|combout " "Node \"z80_\|alu_control_\|db\[4\]~32\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[4\]~19\|datab " "Node \"z80_\|bus_control_\|db\[4\]~19\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[4\]~19\|combout " "Node \"z80_\|bus_control_\|db\[4\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|dataa " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~9\|datab " "Node \"z80_\|alu_\|db_high\[2\]~9\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~27\|dataa " "Node \"z80_\|alu_\|db_high\[3\]~27\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~21\|datab " "Node \"z80_\|alu_\|db_high\[0\]~21\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~18\|datab " "Node \"z80_\|alu_\|db_low\[0\]~18\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~12\|datac " "Node \"z80_\|alu_\|db_low\[1\]~12\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~15\|datac " "Node \"z80_\|alu_\|db_high\[1\]~15\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~32\|dataa " "Node \"z80_\|alu_control_\|db\[4\]~32\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~4\|dataa " "Node \"z80_\|alu_\|db_low\[2\]~4\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~16\|datab " "Node \"z80_\|alu_\|db\[4\]~16\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~54\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~54\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~54\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~54\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~61\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~61\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~61\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~61\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~62\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~62\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~62\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~62\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~30\|datac " "Node \"z80_\|alu_control_\|db\[4\]~30\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~13\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~13\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~14\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~14\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~15\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~15\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~62\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~62\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~53\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~53\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~53\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~53\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~55\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~55\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~55\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~55\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~56\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~56\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~56\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~56\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~57\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~57\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~57\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~57\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~13\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~13\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~14\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~14\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~15\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~15\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~57\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~57\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~24\|dataa " "Node \"z80_\|alu_\|db\[5\]~24\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~24\|combout " "Node \"z80_\|alu_\|db\[5\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~25\|dataa " "Node \"z80_\|alu_\|db\[5\]~25\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~15\|datab " "Node \"z80_\|alu_control_\|db\[5\]~15\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~15\|combout " "Node \"z80_\|alu_control_\|db\[5\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[5\]~15\|datab " "Node \"z80_\|bus_control_\|db\[5\]~15\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[5\]~15\|combout " "Node \"z80_\|bus_control_\|db\[5\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~10\|datac " "Node \"z80_\|alu_\|db_low\[3\]~10\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~9\|dataa " "Node \"z80_\|alu_\|db_high\[2\]~9\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~27\|datac " "Node \"z80_\|alu_\|db_high\[3\]~27\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~21\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~18\|dataa " "Node \"z80_\|alu_\|db_low\[0\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~12\|datab " "Node \"z80_\|alu_\|db_low\[1\]~12\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~15\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[5\]~0\|dataa " "Node \"z80_\|sw1_\|db_down\[5\]~0\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[5\]~0\|combout " "Node \"z80_\|sw1_\|db_down\[5\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~14\|dataa " "Node \"z80_\|alu_control_\|db\[5\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~14\|combout " "Node \"z80_\|alu_control_\|db\[5\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~15\|dataa " "Node \"z80_\|alu_control_\|db\[5\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~4\|datab " "Node \"z80_\|alu_\|db_low\[2\]~4\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~66\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~66\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~66\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~66\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~67\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~67\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~67\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~67\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~70\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~70\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~70\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~70\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~71\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~71\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~71\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~71\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~72\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~72\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~72\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~72\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~16\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~16\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~16\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~17\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~17\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~18\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~18\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~72\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~72\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~14\|datac " "Node \"z80_\|alu_control_\|db\[5\]~14\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~24\|datab " "Node \"z80_\|alu_\|db\[5\]~24\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~18\|datab " "Node \"z80_\|alu_\|db_high\[1\]~18\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~71\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~71\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~71\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~71\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~73\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~73\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~73\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~73\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~74\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~74\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~74\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~74\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~75\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~75\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~75\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~75\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~19\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~19\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~20\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~20\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~21\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~21\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~75\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~75\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~20\|datab " "Node \"z80_\|alu_\|db\[7\]~20\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~20\|combout " "Node \"z80_\|alu_\|db\[7\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~21\|dataa " "Node \"z80_\|alu_\|db\[7\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|dataa " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~16\|datac " "Node \"z80_\|alu_control_\|db\[7\]~16\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~16\|combout " "Node \"z80_\|alu_control_\|db\[7\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~18\|datac " "Node \"z80_\|alu_control_\|db\[7\]~18\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~18\|combout " "Node \"z80_\|alu_control_\|db\[7\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~5\|datab " "Node \"z80_\|bus_control_\|db\[7\]~5\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~5\|combout " "Node \"z80_\|bus_control_\|db\[7\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~7\|dataa " "Node \"z80_\|bus_control_\|db\[7\]~7\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~7\|combout " "Node \"z80_\|bus_control_\|db\[7\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~17\|dataa " "Node \"z80_\|alu_control_\|db\[7\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~17\|combout " "Node \"z80_\|alu_control_\|db\[7\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~18\|datad " "Node \"z80_\|alu_control_\|db\[7\]~18\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~20\|dataa " "Node \"z80_\|alu_\|db\[7\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~89\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~89\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~89\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~89\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~90\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~90\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~90\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~90\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~91\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~91\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~91\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~91\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~92\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~92\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~92\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~92\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[7\]~0\|dataa " "Node \"z80_\|reg_file_\|db_lo_ds\[7\]~0\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[7\]~0\|combout " "Node \"z80_\|reg_file_\|db_lo_ds\[7\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~17\|datad " "Node \"z80_\|alu_control_\|db\[7\]~17\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~22\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~22\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~23\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~23\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~24\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~24\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~24\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~92\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~92\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~6\|datab " "Node \"z80_\|alu_\|db_high\[3\]~6\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~21\|datab " "Node \"z80_\|alu_\|db_low\[0\]~21\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~26\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~26\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~26\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~26\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~28\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~28\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~28\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~28\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~29\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~29\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~29\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~29\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~30\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~30\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~30\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~30\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~4\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~4\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~4\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~5\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~5\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~5\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~6\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~6\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~6\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~30\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~30\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~18\|dataa " "Node \"z80_\|alu_\|db\[0\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~15\|datab " "Node \"z80_\|alu_\|db_low\[1\]~15\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~22\|datab " "Node \"z80_\|alu_\|db_low\[0\]~22\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[0\]~17\|datab " "Node \"z80_\|bus_control_\|db\[0\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[0\]~17\|combout " "Node \"z80_\|bus_control_\|db\[0\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~8\|datab " "Node \"z80_\|alu_control_\|db\[0\]~8\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~8\|combout " "Node \"z80_\|alu_control_\|db\[0\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~9\|datab " "Node \"z80_\|alu_control_\|db\[0\]~9\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~0\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~0\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~0\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~1\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~1\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~1\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~3\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~3\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828520900 ""} } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } { "cpu/bus/data_switch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch.v" 30 -1 0 } } { "cpu/alu/alu_mux_8.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_8.v" 42 -1 0 } } { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 106 -1 0 } } { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 107 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 88 -1 0 } } { "cpu/bus/data_switch_mask.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch_mask.v" 31 -1 0 } } { "cpu/alu/alu_bit_select.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_bit_select.v" 30 -1 0 } } } 0 332125 "Found combinational loop of %1!d! nodes" 0 0 "Fitter" 0 -1 1648828520900 ""} -{ "Critical Warning" "WSTA_SCC_LOOP_TOO_BIG" "511 " "Design contains combinational loop of 511 nodes. Estimating the delays through the loop." { } { } 1 332081 "Design contains combinational loop of %1!d! nodes. Estimating the delays through the loop." 0 0 "Fitter" 0 -1 1648828520917 ""} -{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ula:ula_\|clocks:clocks_\|clk_cpu " "Node: ula:ula_\|clocks:clocks_\|clk_cpu was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1648828520949 "|spectrum|ula:ula_|clocks:clocks_|clk_cpu"} -{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "KEY\[1\] " "Node: KEY\[1\] was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1648828520949 "|spectrum|KEY[1]"} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1648828520963 ""} -{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1648828520965 ""} -{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 5 clocks " "Found 5 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648828520966 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648828520966 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 10.000 beep " " 10.000 beep" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648828520966 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 20.000 CLOCK_50 " " 20.000 CLOCK_50" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648828520966 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 39.716 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 39.716 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648828520966 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 71.489 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 71.489 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648828520966 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 41.702 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 41.702 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648828520966 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1648828520966 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CLOCK_50~input (placed in PIN R8 (CLK15, DIFFCLK_6p)) " "Automatically promoted node CLOCK_50~input (placed in PIN R8 (CLK15, DIFFCLK_6p))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G15 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G15" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648828521150 ""} } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 2 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { CLOCK_50~input } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 5262 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648828521150 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C0 of PLL_4) " "Automatically promoted node ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C0 of PLL_4)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G18 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G18" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648828521150 ""} } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 80 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1221 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648828521150 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[1\] (placed in counter C2 of PLL_4) " "Automatically promoted node ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[1\] (placed in counter C2 of PLL_4)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G17 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G17" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648828521150 ""} } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 80 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1221 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648828521150 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[2\] (placed in counter C1 of PLL_4) " "Automatically promoted node ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[2\] (placed in counter C1 of PLL_4)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G19 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G19" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648828521150 ""} } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 80 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1221 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648828521150 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "ula:ula_\|clocks:clocks_\|clk_cpu " "Automatically promoted node ula:ula_\|clocks:clocks_\|clk_cpu " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648828521150 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "ula:ula_\|clocks:clocks_\|clk_cpu~0 " "Destination node ula:ula_\|clocks:clocks_\|clk_cpu~0" { } { { "ula/clocks.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/clocks.sv" 31 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ula:ula_|clocks:clocks_|clk_cpu~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 2620 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648828521150 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1648828521150 ""} } { { "ula/clocks.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/clocks.sv" 31 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ula:ula_|clocks:clocks_|clk_cpu } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1219 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648828521150 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "reset " "Automatically promoted node reset " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648828521150 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "z80_top_direct_n:z80_\|resets:resets_\|x1~0 " "Destination node z80_top_direct_n:z80_\|resets:resets_\|x1~0" { } { { "cpu/control/resets.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/resets.v" 42 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { z80_top_direct_n:z80_|resets:resets_|x1~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 3836 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648828521150 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1648828521150 ""} } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 62 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1372 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648828521150 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "z80_top_direct_n:z80_\|resets:resets_\|SYNTHESIZED_WIRE_12 " "Automatically promoted node z80_top_direct_n:z80_\|resets:resets_\|SYNTHESIZED_WIRE_12 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648828521151 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[30\]~output " "Destination node GPIO_1\[30\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[30]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 3869 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648828521151 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[0\]~output " "Destination node GPIO_1\[0\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[0]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 3842 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648828521151 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[1\]~output " "Destination node GPIO_1\[1\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[1]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 3843 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648828521151 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[2\]~output " "Destination node GPIO_1\[2\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[2]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 3844 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648828521151 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[3\]~output " "Destination node GPIO_1\[3\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[3]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 3845 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648828521151 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[4\]~output " "Destination node GPIO_1\[4\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[4]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 3846 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648828521151 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[5\]~output " "Destination node GPIO_1\[5\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[5]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 3847 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648828521151 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[6\]~output " "Destination node GPIO_1\[6\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[6]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 3848 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648828521151 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[7\]~output " "Destination node GPIO_1\[7\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[7]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 3849 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648828521151 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[8\]~output " "Destination node GPIO_1\[8\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[8]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 3850 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648828521151 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_LIMITED_TO_SUB" "10 " "Non-global destination nodes limited to 10 nodes" { } { } 0 176358 "Non-global destination nodes limited to %1!d! nodes" 0 0 "Quartus II" 0 -1 1648828521151 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1648828521151 ""} } { { "cpu/control/resets.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/resets.v" 52 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { z80_top_direct_n:z80_|resets:resets_|SYNTHESIZED_WIRE_12 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 675 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648828521151 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "z80_top_direct_n:z80_\|fpga_reset " "Automatically promoted node z80_top_direct_n:z80_\|fpga_reset " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648828521151 ""} } { { "cpu/toplevel/core.vh" "" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/core.vh" 13 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { z80_top_direct_n:z80_|fpga_reset } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 909 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648828521151 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "z80_top_direct_n:z80_\|interrupts:interrupts_\|SYNTHESIZED_WIRE_12 " "Automatically promoted node z80_top_direct_n:z80_\|interrupts:interrupts_\|SYNTHESIZED_WIRE_12 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648828521152 ""} } { { "cpu/control/interrupts.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/interrupts.v" 76 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { z80_top_direct_n:z80_|interrupts:interrupts_|SYNTHESIZED_WIRE_12 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 747 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648828521152 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1648828521943 ""} -{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1648828521946 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1648828521947 ""} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1648828521951 ""} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1648828521956 ""} -{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1648828521959 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1648828521959 ""} -{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1648828521962 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1648828522730 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "9 I/O Output Buffer " "Packed 9 registers into blocks of type I/O Output Buffer" { } { } 1 176218 "Packed %1!d! registers into blocks of type %2!s!" 0 0 "Quartus II" 0 -1 1648828522734 ""} { "Extra Info" "IFSAC_NUM_REGISTERS_DUPLICATED" "8 " "Created 8 register duplicates" { } { } 1 176220 "Created %1!d! register duplicates" 0 0 "Quartus II" 0 -1 1648828522734 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1648828522734 ""} -{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_CS_N " "Node \"ADC_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SADDR " "Node \"ADC_SADDR\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SADDR" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SCLK " "Node \"ADC_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDAT " "Node \"ADC_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[0\] " "Node \"DRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[10\] " "Node \"DRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[11\] " "Node \"DRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[12\] " "Node \"DRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[1\] " "Node \"DRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[2\] " "Node \"DRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[3\] " "Node \"DRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[4\] " "Node \"DRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[5\] " "Node \"DRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[6\] " "Node \"DRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[7\] " "Node \"DRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[8\] " "Node \"DRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[9\] " "Node \"DRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[0\] " "Node \"DRAM_BA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[1\] " "Node \"DRAM_BA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CAS_N " "Node \"DRAM_CAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CKE " "Node \"DRAM_CKE\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CKE" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CLK " "Node \"DRAM_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CS_N " "Node \"DRAM_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[0\] " "Node \"DRAM_DQM\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[1\] " "Node \"DRAM_DQM\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[0\] " "Node \"DRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[10\] " "Node \"DRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[11\] " "Node \"DRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[12\] " "Node \"DRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[13\] " "Node \"DRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[14\] " "Node \"DRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[15\] " "Node \"DRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[1\] " "Node \"DRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[2\] " "Node \"DRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[3\] " "Node \"DRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[4\] " "Node \"DRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[5\] " "Node \"DRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[6\] " "Node \"DRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[7\] " "Node \"DRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[8\] " "Node \"DRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[9\] " "Node \"DRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_RAS_N " "Node \"DRAM_RAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_RAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_WE_N " "Node \"DRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_ASDO " "Node \"EPCS_ASDO\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_ASDO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_DATA0 " "Node \"EPCS_DATA0\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_DATA0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_DCLK " "Node \"EPCS_DCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_DCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_NCSO " "Node \"EPCS_NCSO\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_NCSO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[0\] " "Node \"GPIO_0\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[1\] " "Node \"GPIO_0\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[2\] " "Node \"GPIO_0\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[3\] " "Node \"GPIO_0\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[4\] " "Node \"GPIO_0\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[5\] " "Node \"GPIO_0\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[6\] " "Node \"GPIO_0\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[7\] " "Node \"GPIO_0\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[8\] " "Node \"GPIO_0\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[9\] " "Node \"GPIO_0\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0_IN\[0\] " "Node \"GPIO_0_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0_IN\[1\] " "Node \"GPIO_0_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1_IN\[0\] " "Node \"GPIO_1_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1_IN\[1\] " "Node \"GPIO_1_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[0\] " "Node \"GPIO_2\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[10\] " "Node \"GPIO_2\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[11\] " "Node \"GPIO_2\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[12\] " "Node \"GPIO_2\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[1\] " "Node \"GPIO_2\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[2\] " "Node \"GPIO_2\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[3\] " "Node \"GPIO_2\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[4\] " "Node \"GPIO_2\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[5\] " "Node \"GPIO_2\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[6\] " "Node \"GPIO_2\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[7\] " "Node \"GPIO_2\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[8\] " "Node \"GPIO_2\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[9\] " "Node \"GPIO_2\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[0\] " "Node \"GPIO_2_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[1\] " "Node \"GPIO_2_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[2\] " "Node \"GPIO_2_IN\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "G_SENSOR_CS_N " "Node \"G_SENSOR_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "G_SENSOR_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "G_SENSOR_INT " "Node \"G_SENSOR_INT\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "G_SENSOR_INT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648828522858 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1648828522858 ""} -{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:03 " "Fitter preparation operations ending: elapsed time is 00:00:03" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648828522862 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1648828524399 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648828525162 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1648828525183 ""} -{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1648828528419 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:03 " "Fitter placement operations ending: elapsed time is 00:00:03" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648828528419 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1648828529288 ""} -{ "Info" "IFITAPI_FITAPI_VPR_STATUS_DELAY_ADDED_FOR_HOLD" "7e+02 ns 1.5% " "7e+02 ns of routing delay (approximately 1.5% of available device routing delay) has been added to meet hold timing. For more information, refer to the Estimated Delay Added for Hold Timing section in the Fitter report." { } { } 0 170089 "%1!s! of routing delay (approximately %2!s! of available device routing delay) has been added to meet hold timing. For more information, refer to the Estimated Delay Added for Hold Timing section in the Fitter report." 0 0 "Fitter" 0 -1 1648828531514 ""} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "4 " "Router estimated average interconnect usage is 4% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "26 X32_Y11 X42_Y22 " "Router estimated peak interconnect usage is 26% of the available device resources in the region that extends from location X32_Y11 to location X42_Y22" { } { { "loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 1 { 0 "Router estimated peak interconnect usage is 26% of the available device resources in the region that extends from location X32_Y11 to location X42_Y22"} { { 11 { 0 "Router estimated peak interconnect usage is 26% of the available device resources in the region that extends from location X32_Y11 to location X42_Y22"} 32 11 11 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1648828532126 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1648828532126 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:06 " "Fitter routing operations ending: elapsed time is 00:00:06" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648828535524 ""} -{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1648828535527 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1648828535527 ""} -{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "1.92 " "Total time spent on timing analysis during the Fitter is 1.92 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1648828535674 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1648828535735 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1648828536500 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1648828536554 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1648828537249 ""} -{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:03 " "Fitter post-fit operations ending: elapsed time is 00:00:03" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648828538397 ""} -{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1648828538877 ""} -{ "Warning" "WFIOMGR_FIOMGR_REFER_APPNOTE_447_TOP_LEVEL" "41 Cyclone IV E " "41 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[0\] 3.3-V LVTTL M1 " "Pin SW\[0\] uses I/O standard 3.3-V LVTTL at M1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { SW[0] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[0\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 19 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { SW[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 141 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[3\] 3.3-V LVTTL M15 " "Pin SW\[3\] uses I/O standard 3.3-V LVTTL at M15" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { SW[3] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 19 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { SW[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 144 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[0\] 3.3-V LVTTL F13 " "Pin GPIO_1\[0\] uses I/O standard 3.3-V LVTTL at F13" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[0] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[0\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 145 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[1\] 3.3-V LVTTL T15 " "Pin GPIO_1\[1\] uses I/O standard 3.3-V LVTTL at T15" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[1] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[1\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 146 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[2\] 3.3-V LVTTL T14 " "Pin GPIO_1\[2\] uses I/O standard 3.3-V LVTTL at T14" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[2] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[2\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 147 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[3\] 3.3-V LVTTL T13 " "Pin GPIO_1\[3\] uses I/O standard 3.3-V LVTTL at T13" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[3] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[3\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 148 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[4\] 3.3-V LVTTL R13 " "Pin GPIO_1\[4\] uses I/O standard 3.3-V LVTTL at R13" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[4] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[4\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 149 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[5\] 3.3-V LVTTL T12 " "Pin GPIO_1\[5\] uses I/O standard 3.3-V LVTTL at T12" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[5] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[5\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 150 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[6\] 3.3-V LVTTL R12 " "Pin GPIO_1\[6\] uses I/O standard 3.3-V LVTTL at R12" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[6] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[6\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 151 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[7\] 3.3-V LVTTL T11 " "Pin GPIO_1\[7\] uses I/O standard 3.3-V LVTTL at T11" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[7] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[7\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 152 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[8\] 3.3-V LVTTL T10 " "Pin GPIO_1\[8\] uses I/O standard 3.3-V LVTTL at T10" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[8] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[8\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 153 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[9\] 3.3-V LVTTL R11 " "Pin GPIO_1\[9\] uses I/O standard 3.3-V LVTTL at R11" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[9] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[9\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 154 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[10\] 3.3-V LVTTL P11 " "Pin GPIO_1\[10\] uses I/O standard 3.3-V LVTTL at P11" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[10] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[10\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 155 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[11\] 3.3-V LVTTL R10 " "Pin GPIO_1\[11\] uses I/O standard 3.3-V LVTTL at R10" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[11] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[11\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 156 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[12\] 3.3-V LVTTL N12 " "Pin GPIO_1\[12\] uses I/O standard 3.3-V LVTTL at N12" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[12] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[12\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 157 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[13\] 3.3-V LVTTL P9 " "Pin GPIO_1\[13\] uses I/O standard 3.3-V LVTTL at P9" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[13] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[13\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 158 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[14\] 3.3-V LVTTL N9 " "Pin GPIO_1\[14\] uses I/O standard 3.3-V LVTTL at N9" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[14] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[14\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 159 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[15\] 3.3-V LVTTL N11 " "Pin GPIO_1\[15\] uses I/O standard 3.3-V LVTTL at N11" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[15] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[15\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 160 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[16\] 3.3-V LVTTL L16 " "Pin GPIO_1\[16\] uses I/O standard 3.3-V LVTTL at L16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[16] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[16\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[16] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 161 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[17\] 3.3-V LVTTL K16 " "Pin GPIO_1\[17\] uses I/O standard 3.3-V LVTTL at K16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[17] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[17\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[17] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 162 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[18\] 3.3-V LVTTL R16 " "Pin GPIO_1\[18\] uses I/O standard 3.3-V LVTTL at R16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[18] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[18\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[18] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 163 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[19\] 3.3-V LVTTL L15 " "Pin GPIO_1\[19\] uses I/O standard 3.3-V LVTTL at L15" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[19] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[19\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[19] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 164 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[20\] 3.3-V LVTTL P15 " "Pin GPIO_1\[20\] uses I/O standard 3.3-V LVTTL at P15" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[20] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[20\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[20] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 165 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[21\] 3.3-V LVTTL P16 " "Pin GPIO_1\[21\] uses I/O standard 3.3-V LVTTL at P16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[21] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[21\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[21] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 166 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[22\] 3.3-V LVTTL R14 " "Pin GPIO_1\[22\] uses I/O standard 3.3-V LVTTL at R14" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[22] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[22\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[22] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 167 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[23\] 3.3-V LVTTL N16 " "Pin GPIO_1\[23\] uses I/O standard 3.3-V LVTTL at N16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[23] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[23\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[23] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 168 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[27\] 3.3-V LVTTL N14 " "Pin GPIO_1\[27\] uses I/O standard 3.3-V LVTTL at N14" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[27] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[27\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[27] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 172 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[28\] 3.3-V LVTTL M10 " "Pin GPIO_1\[28\] uses I/O standard 3.3-V LVTTL at M10" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[28] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[28\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[28] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 173 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[29\] 3.3-V LVTTL L13 " "Pin GPIO_1\[29\] uses I/O standard 3.3-V LVTTL at L13" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[29] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[29\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[29] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 174 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[30\] 3.3-V LVTTL J16 " "Pin GPIO_1\[30\] uses I/O standard 3.3-V LVTTL at J16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[30] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[30\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[30] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 175 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "I2C_SCLK 3.3-V LVTTL F2 " "Pin I2C_SCLK uses I/O standard 3.3-V LVTTL at F2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { I2C_SCLK } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "I2C_SCLK" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 6 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { I2C_SCLK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 182 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "I2C_SDAT 3.3-V LVTTL F1 " "Pin I2C_SDAT uses I/O standard 3.3-V LVTTL at F1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { I2C_SDAT } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 7 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { I2C_SDAT } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 183 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[1\] 3.3-V LVTTL T8 " "Pin SW\[1\] uses I/O standard 3.3-V LVTTL at T8" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { SW[1] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 19 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { SW[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 142 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[2\] 3.3-V LVTTL B9 " "Pin SW\[2\] uses I/O standard 3.3-V LVTTL at B9" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { SW[2] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 19 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { SW[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 143 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "raw_loader_in 3.3-V LVTTL B6 " "Pin raw_loader_in uses I/O standard 3.3-V LVTTL at B6" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { raw_loader_in } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "raw_loader_in" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 23 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { raw_loader_in } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 193 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "KEY\[0\] 3.3-V LVTTL J15 " "Pin KEY\[0\] uses I/O standard 3.3-V LVTTL at J15" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { KEY[0] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "KEY\[0\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 3 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { KEY[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 127 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "CLOCK_50 3.3-V LVTTL R8 " "Pin CLOCK_50 uses I/O standard 3.3-V LVTTL at R8" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { CLOCK_50 } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 2 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 179 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "PS2_DAT 3.3-V LVTTL B7 " "Pin PS2_DAT uses I/O standard 3.3-V LVTTL at B7" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { PS2_DAT } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "PS2_DAT" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 5 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { PS2_DAT } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 181 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "KEY\[1\] 3.3-V LVTTL E1 " "Pin KEY\[1\] uses I/O standard 3.3-V LVTTL at E1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { KEY[1] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "KEY\[1\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 3 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { KEY[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 128 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "PS2_CLK 3.3-V LVTTL D6 " "Pin PS2_CLK uses I/O standard 3.3-V LVTTL at D6" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { PS2_CLK } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "PS2_CLK" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 4 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { PS2_CLK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 180 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "AUD_ADCDAT 3.3-V LVTTL D8 " "Pin AUD_ADCDAT uses I/O standard 3.3-V LVTTL at D8" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { AUD_ADCDAT } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "AUD_ADCDAT" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 13 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { AUD_ADCDAT } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 189 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648828538892 ""} } { } 0 169177 "%1!d! pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing %2!s! Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." 0 0 "Fitter" 0 -1 1648828538892 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/benny/work/fpga/spectrum/output_files/spectrum.fit.smsg " "Generated suppressed messages file /home/benny/work/fpga/spectrum/output_files/spectrum.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1648828539248 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 609 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 609 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "639 " "Peak virtual memory: 639 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648828540068 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 1 18:55:40 2022 " "Processing ended: Fri Apr 1 18:55:40 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648828540068 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:22 " "Elapsed time: 00:00:22" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648828540068 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:21 " "Total CPU time (on all processors): 00:00:21" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648828540068 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1648828540068 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1648903992363 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "spectrum EP4CE22F17C6 " "Selected device EP4CE22F17C6 for design \"spectrum\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1648903992378 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648903992417 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648903992418 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648903992418 ""} +{ "Info" "ICUT_CUT_PLL_COMPUTATION_SUCCESS" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 Cyclone IV E PLL " "Implemented PLL \"ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1\" as Cyclone IV E PLL type" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[0\] 141 280 0 0 " "Implementing clock multiplication of 141, clock division of 280, and phase shift of 0 degrees (0 ps) for ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[0\] port" { } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 45 -1 0 } } { "" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1218 9662 10382 0} } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Quartus II" 0 -1 1648903992482 ""} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[1\] 47 168 0 0 " "Implementing clock multiplication of 47, clock division of 168, and phase shift of 0 degrees (0 ps) for ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[1\] port" { } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 45 -1 0 } } { "" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1219 9662 10382 0} } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Quartus II" 0 -1 1648903992482 ""} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[2\] 47 98 0 0 " "Implementing clock multiplication of 47, clock division of 98, and phase shift of 0 degrees (0 ps) for ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[2\] port" { } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 45 -1 0 } } { "" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1220 9662 10382 0} } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Quartus II" 0 -1 1648903992482 ""} } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 45 -1 0 } } { "" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1218 9662 10382 0} } } } } 0 15535 "Implemented %3!s! \"%1!s!\" as %2!s! PLL type" 0 0 "Fitter" 0 -1 1648903992482 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1648903992557 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1648903992568 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE10F17C6 " "Device EP4CE10F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648903992784 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE6F17C6 " "Device EP4CE6F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648903992784 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE15F17C6 " "Device EP4CE15F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648903992784 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1648903992784 ""} +{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ C1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location C1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 5270 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648903992791 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ D2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location D2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 5272 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648903992791 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ H1 " "Pin ~ALTERA_DCLK~ is reserved at location H1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 5274 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648903992791 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ H2 " "Pin ~ALTERA_DATA0~ is reserved at location H2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 5276 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648903992791 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ F16 " "Pin ~ALTERA_nCEO~ is reserved at location F16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 5278 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648903992791 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1648903992791 ""} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1648903992794 ""} +{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." { } { } 0 176045 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "Fitter" 0 -1 1648903992801 ""} +{ "Info" "ISTA_SDC_FOUND" "spectrum.sdc " "Reading SDC File: 'spectrum.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1648903993934 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 12 KEY1 port " "Ignored filter at spectrum.sdc(12): KEY1 could not be matched with a port" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 12 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648903993942 ""} +{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "create_clock spectrum.sdc 12 Argument is an empty collection " "Ignored create_clock at spectrum.sdc(12): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "create_clock -name KEY1 -period 10.000 \[get_ports \{KEY1\}\] " "create_clock -name KEY1 -period 10.000 \[get_ports \{KEY1\}\]" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 12 -1 0 } } } 0 332050 "%1!s!" 0 0 "Quartus II" 0 -1 1648903993942 ""} } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 12 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Fitter" 0 -1 1648903993942 ""} +{ "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "Deriving PLL clocks " "Deriving PLL clocks" { { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 280 -multiply_by 141 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 280 -multiply_by 141 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648903993944 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 168 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} " "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 168 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648903993944 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 98 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} " "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 98 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648903993944 ""} } { } 0 332110 "%1!s!" 0 0 "Fitter" 0 -1 1648903993944 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 21 ula_\|clocks_\|clk_cpu\|regout pin " "Ignored filter at spectrum.sdc(21): ula_\|clocks_\|clk_cpu\|regout could not be matched with a pin" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 21 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648903993944 ""} +{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "create_generated_clock spectrum.sdc 21 Argument is an empty collection " "Ignored create_generated_clock at spectrum.sdc(21): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "create_generated_clock -name clk_cpu -source \[get_pins \{ula_\|clocks_\|clk_cpu\|clk\}\] -divide_by 4 \[get_pins \{ula_\|clocks_\|clk_cpu\|regout\}\] " "create_generated_clock -name clk_cpu -source \[get_pins \{ula_\|clocks_\|clk_cpu\|clk\}\] -divide_by 4 \[get_pins \{ula_\|clocks_\|clk_cpu\|regout\}\]" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 21 -1 0 } } } 0 332050 "%1!s!" 0 0 "Quartus II" 0 -1 1648903993944 ""} } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 21 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Fitter" 0 -1 1648903993944 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_CALL_IS_DELAYED" "" "Clock uncertainty is not calculated until you update the timing netlist." { } { } 0 332151 "Clock uncertainty is not calculated until you update the timing netlist." 0 0 "Fitter" 0 -1 1648903993944 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 56 clk_cpu clock " "Ignored filter at spectrum.sdc(56): clk_cpu could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 56 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648903993945 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 57 KEY1 clock " "Ignored filter at spectrum.sdc(57): KEY1 could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 57 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648903993945 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 54 ula_\|pll_\|altpll_component\|pll\|clk\[0\] clock " "Ignored filter at spectrum.sdc(54): ula_\|pll_\|altpll_component\|pll\|clk\[0\] could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 54 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648903993945 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 54 ula_\|pll_\|altpll_component\|pll\|clk\[1\] clock " "Ignored filter at spectrum.sdc(54): ula_\|pll_\|altpll_component\|pll\|clk\[1\] could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 54 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648903993945 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 54 ula_\|pll_\|altpll_component\|pll\|clk\[2\] clock " "Ignored filter at spectrum.sdc(54): ula_\|pll_\|altpll_component\|pll\|clk\[2\] could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 54 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1648903993946 ""} +{ "Warning" "WSTA_SCC_LOOP" "517 " "Found combinational loop of 517 nodes" { { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~3\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~22\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~22\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~22\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~9\|datac " "Node \"z80_\|alu_control_\|db\[0\]~9\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~9\|combout " "Node \"z80_\|alu_control_\|db\[0\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~12\|dataa " "Node \"z80_\|alu_control_\|db\[0\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~12\|combout " "Node \"z80_\|alu_control_\|db\[0\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~14\|datab " "Node \"z80_\|alu_\|db\[0\]~14\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~14\|combout " "Node \"z80_\|alu_\|db\[0\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw2_\|db_up\[0\]~0\|dataa " "Node \"z80_\|sw2_\|db_up\[0\]~0\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw2_\|db_up\[0\]~0\|combout " "Node \"z80_\|sw2_\|db_up\[0\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~9\|dataa " "Node \"z80_\|alu_control_\|db\[0\]~9\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~26\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~26\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~26\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~26\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~28\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~28\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~28\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~28\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~29\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~29\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~29\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~29\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~30\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~30\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~30\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~30\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~13\|dataa " "Node \"z80_\|alu_\|db\[0\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~13\|combout " "Node \"z80_\|alu_\|db\[0\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~14\|dataa " "Node \"z80_\|alu_\|db\[0\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~4\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~4\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~4\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~5\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~5\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~5\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~6\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~6\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~6\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~30\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~30\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|datac " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|combout " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|datab " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|combout " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~4\|dataa " "Node \"z80_\|alu_\|db_high\[3\]~4\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~4\|combout " "Node \"z80_\|alu_\|db_high\[3\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~5\|dataa " "Node \"z80_\|alu_\|db_high\[3\]~5\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~5\|combout " "Node \"z80_\|alu_\|db_high\[3\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~6\|datac " "Node \"z80_\|alu_\|db_high\[3\]~6\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~6\|combout " "Node \"z80_\|alu_\|db_high\[3\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~7\|dataa " "Node \"z80_\|alu_\|db_high\[3\]~7\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~7\|combout " "Node \"z80_\|alu_\|db_high\[3\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~12\|datab " "Node \"z80_\|alu_\|db\[7\]~12\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~12\|combout " "Node \"z80_\|alu_\|db\[7\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~5\|datab " "Node \"z80_\|alu_\|db_high\[3\]~5\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~8\|dataa " "Node \"z80_\|alu_\|db_high\[2\]~8\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~8\|combout " "Node \"z80_\|alu_\|db_high\[2\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~9\|dataa " "Node \"z80_\|alu_\|db_high\[2\]~9\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~9\|combout " "Node \"z80_\|alu_\|db_high\[2\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~12\|dataa " "Node \"z80_\|alu_\|db_high\[2\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~12\|combout " "Node \"z80_\|alu_\|db_high\[2\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~13\|dataa " "Node \"z80_\|alu_\|db_high\[2\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~13\|combout " "Node \"z80_\|alu_\|db_high\[2\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~22\|datab " "Node \"z80_\|alu_\|db\[6\]~22\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~22\|combout " "Node \"z80_\|alu_\|db\[6\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~4\|datab " "Node \"z80_\|alu_\|db_high\[3\]~4\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~9\|datab " "Node \"z80_\|alu_\|db_high\[2\]~9\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~20\|dataa " "Node \"z80_\|alu_control_\|db\[6\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~20\|combout " "Node \"z80_\|alu_control_\|db\[6\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~21\|datad " "Node \"z80_\|alu_control_\|db\[6\]~21\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~21\|combout " "Node \"z80_\|alu_control_\|db\[6\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~22\|datac " "Node \"z80_\|alu_control_\|db\[6\]~22\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~22\|combout " "Node \"z80_\|alu_control_\|db\[6\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~8\|datab " "Node \"z80_\|bus_control_\|db\[6\]~8\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~8\|combout " "Node \"z80_\|bus_control_\|db\[6\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~9\|dataa " "Node \"z80_\|bus_control_\|db\[6\]~9\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~9\|combout " "Node \"z80_\|bus_control_\|db\[6\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[6\]~1\|dataa " "Node \"z80_\|sw1_\|db_down\[6\]~1\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[6\]~1\|combout " "Node \"z80_\|sw1_\|db_down\[6\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~22\|dataa " "Node \"z80_\|alu_control_\|db\[6\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~79\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~79\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~79\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~79\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~80\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~80\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~80\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~80\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~81\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~81\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~81\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~81\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~82\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~82\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~82\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~82\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~19\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~19\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~20\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~20\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~21\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~21\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~82\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~82\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[6\]~0\|dataa " "Node \"z80_\|reg_file_\|db_lo_ds\[6\]~0\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[6\]~0\|combout " "Node \"z80_\|reg_file_\|db_lo_ds\[6\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~22\|datab " "Node \"z80_\|alu_control_\|db\[6\]~22\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~21\|dataa " "Node \"z80_\|alu_\|db\[6\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~21\|combout " "Node \"z80_\|alu_\|db\[6\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~22\|dataa " "Node \"z80_\|alu_\|db\[6\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~80\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~80\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~80\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~80\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~82\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~82\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~82\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~82\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~83\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~83\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~83\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~83\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~84\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~84\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~84\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~84\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~22\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~22\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~23\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~23\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~24\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~24\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~24\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~84\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~84\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~21\|datab " "Node \"z80_\|alu_\|db\[6\]~21\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~16\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~16\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~16\|combout " "Node \"z80_\|alu_\|db_high\[1\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~17\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~17\|combout " "Node \"z80_\|alu_\|db_high\[1\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~18\|datac " "Node \"z80_\|alu_\|db_high\[1\]~18\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~18\|combout " "Node \"z80_\|alu_\|db_high\[1\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~19\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~19\|combout " "Node \"z80_\|alu_\|db_high\[1\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~24\|datab " "Node \"z80_\|alu_\|db\[5\]~24\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~24\|combout " "Node \"z80_\|alu_\|db\[5\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~8\|datab " "Node \"z80_\|alu_\|db_high\[2\]~8\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~22\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~22\|combout " "Node \"z80_\|alu_\|db_high\[0\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~23\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~23\|combout " "Node \"z80_\|alu_\|db_high\[0\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~24\|datac " "Node \"z80_\|alu_\|db_high\[0\]~24\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~24\|combout " "Node \"z80_\|alu_\|db_high\[0\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~25\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~25\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~25\|combout " "Node \"z80_\|alu_\|db_high\[0\]~25\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~18\|datab " "Node \"z80_\|alu_\|db\[4\]~18\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~18\|combout " "Node \"z80_\|alu_\|db\[4\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~30\|dataa " "Node \"z80_\|alu_control_\|db\[4\]~30\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~30\|combout " "Node \"z80_\|alu_control_\|db\[4\]~30\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~31\|datad " "Node \"z80_\|alu_control_\|db\[4\]~31\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~31\|combout " "Node \"z80_\|alu_control_\|db\[4\]~31\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~32\|datad " "Node \"z80_\|alu_control_\|db\[4\]~32\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~32\|combout " "Node \"z80_\|alu_control_\|db\[4\]~32\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~54\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~54\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~54\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~54\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~61\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~61\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~61\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~61\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~62\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~62\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~62\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~62\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~13\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~13\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~14\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~14\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~15\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~15\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~62\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~62\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~30\|datac " "Node \"z80_\|alu_control_\|db\[4\]~30\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~17\|datab " "Node \"z80_\|alu_\|db\[4\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~17\|combout " "Node \"z80_\|alu_\|db\[4\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~18\|dataa " "Node \"z80_\|alu_\|db\[4\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[4\]~19\|datab " "Node \"z80_\|bus_control_\|db\[4\]~19\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[4\]~19\|combout " "Node \"z80_\|bus_control_\|db\[4\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~32\|dataa " "Node \"z80_\|alu_control_\|db\[4\]~32\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~2\|datab " "Node \"z80_\|alu_\|db_high\[3\]~2\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~2\|combout " "Node \"z80_\|alu_\|db_high\[3\]~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~6\|dataa " "Node \"z80_\|alu_\|db_high\[3\]~6\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~11\|datab " "Node \"z80_\|alu_\|db_high\[2\]~11\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~11\|combout " "Node \"z80_\|alu_\|db_high\[2\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~12\|datac " "Node \"z80_\|alu_\|db_high\[2\]~12\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~7\|datac " "Node \"z80_\|alu_\|db_low\[1\]~7\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~7\|combout " "Node \"z80_\|alu_\|db_low\[1\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~9\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~9\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~9\|combout " "Node \"z80_\|alu_\|db_low\[1\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~12\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~12\|combout " "Node \"z80_\|alu_\|db_low\[1\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~10\|datab " "Node \"z80_\|alu_\|db\[1\]~10\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~10\|combout " "Node \"z80_\|alu_\|db\[1\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~12\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~12\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~14\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~14\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~14\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~15\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~15\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~15\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~21\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~21\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~8\|datab " "Node \"z80_\|alu_\|db\[1\]~8\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~8\|combout " "Node \"z80_\|alu_\|db\[1\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~10\|dataa " "Node \"z80_\|alu_\|db\[1\]~10\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~0\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~0\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~0\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~1\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~1\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~1\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~3\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~3\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~3\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~21\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~21\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~2\|dataa " "Node \"z80_\|alu_\|db_low\[0\]~2\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~2\|combout " "Node \"z80_\|alu_\|db_low\[0\]~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~3\|dataa " "Node \"z80_\|alu_\|db_low\[0\]~3\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~3\|combout " "Node \"z80_\|alu_\|db_low\[0\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~24\|dataa " "Node \"z80_\|alu_\|db_low\[0\]~24\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~24\|combout " "Node \"z80_\|alu_\|db_low\[0\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~13\|datab " "Node \"z80_\|alu_\|db\[0\]~13\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~21\|datab " "Node \"z80_\|alu_\|db_low\[2\]~21\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~21\|combout " "Node \"z80_\|alu_\|db_low\[2\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~22\|dataa " "Node \"z80_\|alu_\|db_low\[2\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~22\|combout " "Node \"z80_\|alu_\|db_low\[2\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~23\|datab " "Node \"z80_\|alu_\|db_low\[2\]~23\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~23\|combout " "Node \"z80_\|alu_\|db_low\[2\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~16\|datab " "Node \"z80_\|alu_\|db\[2\]~16\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~16\|combout " "Node \"z80_\|alu_\|db\[2\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~10\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~10\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~10\|combout " "Node \"z80_\|alu_\|db_low\[1\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~11\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~11\|combout " "Node \"z80_\|alu_\|db_low\[1\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~12\|datab " "Node \"z80_\|alu_\|db_low\[1\]~12\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~35\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~35\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~35\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~35\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~37\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~37\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~37\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~37\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~38\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~38\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~38\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~38\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~39\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~39\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~39\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~39\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~7\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~7\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~7\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~8\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~8\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~8\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~9\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~9\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~9\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~39\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~39\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~15\|datab " "Node \"z80_\|alu_\|db\[2\]~15\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~15\|combout " "Node \"z80_\|alu_\|db\[2\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~16\|dataa " "Node \"z80_\|alu_\|db\[2\]~16\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~13\|datab " "Node \"z80_\|alu_\|db_low\[3\]~13\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~13\|combout " "Node \"z80_\|alu_\|db_low\[3\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~14\|dataa " "Node \"z80_\|alu_\|db_low\[3\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~14\|combout " "Node \"z80_\|alu_\|db_low\[3\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~17\|dataa " "Node \"z80_\|alu_\|db_low\[3\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~17\|combout " "Node \"z80_\|alu_\|db_low\[3\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~25\|datac " "Node \"z80_\|alu_\|db_low\[3\]~25\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~25\|combout " "Node \"z80_\|alu_\|db_low\[3\]~25\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~19\|datab " "Node \"z80_\|alu_\|db\[3\]~19\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~19\|combout " "Node \"z80_\|alu_\|db\[3\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~20\|dataa " "Node \"z80_\|alu_\|db\[3\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~20\|combout " "Node \"z80_\|alu_\|db\[3\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~22\|datab " "Node \"z80_\|alu_\|db_high\[0\]~22\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~44\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~44\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~44\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~44\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~46\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~46\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~46\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~46\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~47\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~47\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~47\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~47\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~48\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~48\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~48\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~48\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~10\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~10\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~10\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~11\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~11\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~12\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~12\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~48\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~48\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~19\|dataa " "Node \"z80_\|alu_\|db\[3\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~14\|datab " "Node \"z80_\|alu_\|db_low\[3\]~14\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~35\|datab " "Node \"z80_\|alu_control_\|db\[3\]~35\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~35\|combout " "Node \"z80_\|alu_control_\|db\[3\]~35\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[3\]~21\|datab " "Node \"z80_\|bus_control_\|db\[3\]~21\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[3\]~21\|combout " "Node \"z80_\|bus_control_\|db\[3\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~2\|datac " "Node \"z80_\|alu_\|db_high\[3\]~2\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~11\|datad " "Node \"z80_\|alu_\|db_high\[2\]~11\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~7\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~7\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~4\|datac " "Node \"z80_\|alu_\|db_low\[0\]~4\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~4\|combout " "Node \"z80_\|alu_\|db_low\[0\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~6\|dataa " "Node \"z80_\|alu_\|db_low\[0\]~6\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~6\|combout " "Node \"z80_\|alu_\|db_low\[0\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~24\|datab " "Node \"z80_\|alu_\|db_low\[0\]~24\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~20\|datac " "Node \"z80_\|alu_\|db_high\[0\]~20\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~20\|combout " "Node \"z80_\|alu_\|db_high\[0\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~24\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~24\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~14\|datab " "Node \"z80_\|alu_\|db_high\[1\]~14\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~14\|combout " "Node \"z80_\|alu_\|db_high\[1\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~18\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|datad " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|combout " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~19\|datab " "Node \"z80_\|alu_\|db_low\[2\]~19\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~19\|combout " "Node \"z80_\|alu_\|db_low\[2\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~20\|dataa " "Node \"z80_\|alu_\|db_low\[2\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~20\|combout " "Node \"z80_\|alu_\|db_low\[2\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~23\|dataa " "Node \"z80_\|alu_\|db_low\[2\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[3\]~2\|dataa " "Node \"z80_\|sw1_\|db_down\[3\]~2\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[3\]~2\|combout " "Node \"z80_\|sw1_\|db_down\[3\]~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~34\|dataa " "Node \"z80_\|alu_control_\|db\[3\]~34\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~34\|combout " "Node \"z80_\|alu_control_\|db\[3\]~34\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~35\|dataa " "Node \"z80_\|alu_control_\|db\[3\]~35\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|datab " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|combout " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~16\|datab " "Node \"z80_\|alu_\|db_low\[3\]~16\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~16\|combout " "Node \"z80_\|alu_\|db_low\[3\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~17\|datab " "Node \"z80_\|alu_\|db_low\[3\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~46\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~46\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~46\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~46\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~47\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~47\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~47\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~47\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~50\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~50\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~50\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~50\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~51\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~51\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~51\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~51\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~52\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~52\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~52\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~52\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~10\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~10\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~10\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~11\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~11\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~12\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~12\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~52\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~52\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~34\|datac " "Node \"z80_\|alu_control_\|db\[3\]~34\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~20\|datab " "Node \"z80_\|alu_\|db\[3\]~20\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~21\|dataa " "Node \"z80_\|alu_\|db_low\[2\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~22\|datab " "Node \"z80_\|alu_\|db_low\[2\]~22\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~27\|datac " "Node \"z80_\|alu_control_\|db\[2\]~27\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~27\|combout " "Node \"z80_\|alu_control_\|db\[2\]~27\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~29\|datac " "Node \"z80_\|alu_control_\|db\[2\]~29\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~29\|combout " "Node \"z80_\|alu_control_\|db\[2\]~29\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~12\|datab " "Node \"z80_\|bus_control_\|db\[2\]~12\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~12\|combout " "Node \"z80_\|bus_control_\|db\[2\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~13\|dataa " "Node \"z80_\|bus_control_\|db\[2\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~13\|combout " "Node \"z80_\|bus_control_\|db\[2\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~28\|dataa " "Node \"z80_\|alu_control_\|db\[2\]~28\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~28\|combout " "Node \"z80_\|alu_control_\|db\[2\]~28\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~29\|datad " "Node \"z80_\|alu_control_\|db\[2\]~29\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~15\|dataa " "Node \"z80_\|alu_\|db\[2\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~39\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~39\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~39\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~39\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~40\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~40\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~40\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~40\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~41\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~41\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~41\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~41\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~42\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~42\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~42\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~42\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[2\]~2\|dataa " "Node \"z80_\|reg_file_\|db_lo_ds\[2\]~2\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[2\]~2\|combout " "Node \"z80_\|reg_file_\|db_lo_ds\[2\]~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~28\|datad " "Node \"z80_\|alu_control_\|db\[2\]~28\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~7\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~7\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~7\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~8\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~8\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~8\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~9\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~9\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~9\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~42\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~42\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~11\|datab " "Node \"z80_\|alu_\|db_low\[1\]~11\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~24\|datac " "Node \"z80_\|alu_control_\|db\[1\]~24\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~24\|combout " "Node \"z80_\|alu_control_\|db\[1\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~26\|datac " "Node \"z80_\|alu_control_\|db\[1\]~26\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~26\|combout " "Node \"z80_\|alu_control_\|db\[1\]~26\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~10\|datab " "Node \"z80_\|bus_control_\|db\[1\]~10\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~10\|combout " "Node \"z80_\|bus_control_\|db\[1\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~11\|dataa " "Node \"z80_\|bus_control_\|db\[1\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~11\|combout " "Node \"z80_\|bus_control_\|db\[1\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~25\|dataa " "Node \"z80_\|alu_control_\|db\[1\]~25\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~25\|combout " "Node \"z80_\|alu_control_\|db\[1\]~25\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~26\|datad " "Node \"z80_\|alu_control_\|db\[1\]~26\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~8\|dataa " "Node \"z80_\|alu_\|db\[1\]~8\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~29\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~29\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~29\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~29\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~30\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~30\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~30\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~30\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~31\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~31\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~31\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~31\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~32\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~32\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~32\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~32\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~4\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~4\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~4\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~5\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~5\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~5\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~6\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~6\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~6\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~32\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~32\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[1\]~1\|dataa " "Node \"z80_\|reg_file_\|db_lo_ds\[1\]~1\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[1\]~1\|combout " "Node \"z80_\|reg_file_\|db_lo_ds\[1\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~25\|datad " "Node \"z80_\|alu_control_\|db\[1\]~25\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~4\|datab " "Node \"z80_\|alu_\|db_low\[0\]~4\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~20\|datab " "Node \"z80_\|alu_\|db_high\[0\]~20\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~14\|datac " "Node \"z80_\|alu_\|db_high\[1\]~14\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|dataa " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|dataa " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~62\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~62\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~62\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~62\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~64\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~64\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~64\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~64\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~65\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~65\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~65\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~65\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~66\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~66\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~66\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~66\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~16\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~16\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~16\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~17\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~17\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~18\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~18\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~66\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~66\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~17\|dataa " "Node \"z80_\|alu_\|db\[4\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~16\|datab " "Node \"z80_\|alu_\|db_high\[1\]~16\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~13\|dataa " "Node \"z80_\|alu_\|db_low\[3\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~23\|datab " "Node \"z80_\|alu_\|db_high\[0\]~23\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~15\|datab " "Node \"z80_\|alu_control_\|db\[5\]~15\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~15\|combout " "Node \"z80_\|alu_control_\|db\[5\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[5\]~15\|datab " "Node \"z80_\|bus_control_\|db\[5\]~15\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[5\]~15\|combout " "Node \"z80_\|bus_control_\|db\[5\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~2\|dataa " "Node \"z80_\|alu_\|db_high\[3\]~2\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~11\|dataa " "Node \"z80_\|alu_\|db_high\[2\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~7\|datab " "Node \"z80_\|alu_\|db_low\[1\]~7\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~4\|dataa " "Node \"z80_\|alu_\|db_low\[0\]~4\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~20\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[5\]~0\|dataa " "Node \"z80_\|sw1_\|db_down\[5\]~0\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[5\]~0\|combout " "Node \"z80_\|sw1_\|db_down\[5\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~14\|dataa " "Node \"z80_\|alu_control_\|db\[5\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~14\|combout " "Node \"z80_\|alu_control_\|db\[5\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~15\|dataa " "Node \"z80_\|alu_control_\|db\[5\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~14\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~19\|datac " "Node \"z80_\|alu_\|db_low\[2\]~19\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~16\|datac " "Node \"z80_\|alu_\|db_low\[3\]~16\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~66\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~66\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~66\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~66\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~67\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~67\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~67\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~67\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~70\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~70\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~70\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~70\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~71\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~71\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~71\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~71\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~72\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~72\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~72\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~72\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~16\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~16\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~16\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~17\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~17\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~18\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~18\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~72\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~72\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~14\|datac " "Node \"z80_\|alu_control_\|db\[5\]~14\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~23\|datab " "Node \"z80_\|alu_\|db\[5\]~23\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~23\|combout " "Node \"z80_\|alu_\|db\[5\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~24\|dataa " "Node \"z80_\|alu_\|db\[5\]~24\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~17\|datab " "Node \"z80_\|alu_\|db_high\[1\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~53\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~53\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~53\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~53\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~55\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~55\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~55\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~55\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~56\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~56\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~56\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~56\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~57\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~57\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~57\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~57\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~23\|dataa " "Node \"z80_\|alu_\|db\[5\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~13\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~13\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~14\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~14\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~15\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~15\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~57\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~57\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~16\|datac " "Node \"z80_\|alu_control_\|db\[7\]~16\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~16\|combout " "Node \"z80_\|alu_control_\|db\[7\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~17\|datad " "Node \"z80_\|alu_control_\|db\[7\]~17\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~17\|combout " "Node \"z80_\|alu_control_\|db\[7\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~18\|datad " "Node \"z80_\|alu_control_\|db\[7\]~18\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~18\|combout " "Node \"z80_\|alu_control_\|db\[7\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~19\|dataa " "Node \"z80_\|alu_control_\|db\[7\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~19\|combout " "Node \"z80_\|alu_control_\|db\[7\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~5\|datab " "Node \"z80_\|bus_control_\|db\[7\]~5\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~5\|combout " "Node \"z80_\|bus_control_\|db\[7\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~7\|dataa " "Node \"z80_\|bus_control_\|db\[7\]~7\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~7\|combout " "Node \"z80_\|bus_control_\|db\[7\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~18\|dataa " "Node \"z80_\|alu_control_\|db\[7\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~88\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~88\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~88\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~88\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~89\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~89\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~89\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~89\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~90\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~90\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~90\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~90\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~91\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~91\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~91\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~91\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~22\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~22\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~23\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~23\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~24\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~24\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~24\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~91\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~91\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~17\|datab " "Node \"z80_\|alu_control_\|db\[7\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~11\|dataa " "Node \"z80_\|alu_\|db\[7\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~11\|combout " "Node \"z80_\|alu_\|db\[7\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~12\|dataa " "Node \"z80_\|alu_\|db\[7\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~71\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~71\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~71\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~71\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~73\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~73\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~73\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~73\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~74\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~74\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~74\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~74\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~75\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~75\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~75\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~75\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~19\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~19\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~20\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~20\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~21\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~21\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~75\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~75\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~11\|datab " "Node \"z80_\|alu_\|db\[7\]~11\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|dataa " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~2\|datab " "Node \"z80_\|alu_\|db_low\[0\]~2\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~3\|datab " "Node \"z80_\|alu_\|db_low\[0\]~3\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~10\|datab " "Node \"z80_\|alu_\|db_low\[1\]~10\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~12\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~12\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~17\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~17\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~22\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[0\]~17\|datab " "Node \"z80_\|bus_control_\|db\[0\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[0\]~17\|combout " "Node \"z80_\|bus_control_\|db\[0\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~8\|datab " "Node \"z80_\|alu_control_\|db\[0\]~8\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~8\|combout " "Node \"z80_\|alu_control_\|db\[0\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~9\|datab " "Node \"z80_\|alu_control_\|db\[0\]~9\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~0\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~0\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~0\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~1\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~1\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~1\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~3\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~3\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903993952 ""} } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } { "cpu/bus/data_switch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch.v" 30 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } { "cpu/alu/alu_mux_8.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_8.v" 42 -1 0 } } { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 106 -1 0 } } { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } { "cpu/bus/data_switch_mask.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch_mask.v" 31 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 88 -1 0 } } { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 107 -1 0 } } { "cpu/alu/alu_bit_select.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_bit_select.v" 30 -1 0 } } } 0 332125 "Found combinational loop of %1!d! nodes" 0 0 "Fitter" 0 -1 1648903993952 ""} +{ "Critical Warning" "WSTA_SCC_LOOP_TOO_BIG" "517 " "Design contains combinational loop of 517 nodes. Estimating the delays through the loop." { } { } 1 332081 "Design contains combinational loop of %1!d! nodes. Estimating the delays through the loop." 0 0 "Fitter" 0 -1 1648903993969 ""} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ula:ula_\|clocks:clocks_\|clk_cpu " "Node: ula:ula_\|clocks:clocks_\|clk_cpu was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1648903994000 "|spectrum|ula:ula_|clocks:clocks_|clk_cpu"} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "KEY\[1\] " "Node: KEY\[1\] was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1648903994000 "|spectrum|KEY[1]"} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1648903994014 ""} +{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1648903994016 ""} +{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 5 clocks " "Found 5 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648903994016 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648903994016 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 10.000 beep " " 10.000 beep" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648903994016 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 20.000 CLOCK_50 " " 20.000 CLOCK_50" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648903994016 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 39.716 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 39.716 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648903994016 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 71.489 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 71.489 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648903994016 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 41.702 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 41.702 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1648903994016 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1648903994016 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CLOCK_50~input (placed in PIN R8 (CLK15, DIFFCLK_6p)) " "Automatically promoted node CLOCK_50~input (placed in PIN R8 (CLK15, DIFFCLK_6p))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G15 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G15" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648903994193 ""} } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 2 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { CLOCK_50~input } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 5258 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648903994193 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C0 of PLL_4) " "Automatically promoted node ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C0 of PLL_4)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G18 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G18" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648903994193 ""} } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 80 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1218 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648903994193 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[1\] (placed in counter C2 of PLL_4) " "Automatically promoted node ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[1\] (placed in counter C2 of PLL_4)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G17 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G17" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648903994193 ""} } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 80 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1218 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648903994193 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[2\] (placed in counter C1 of PLL_4) " "Automatically promoted node ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\|wire_pll1_clk\[2\] (placed in counter C1 of PLL_4)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G19 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G19" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648903994193 ""} } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 80 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1218 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648903994193 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "ula:ula_\|clocks:clocks_\|clk_cpu " "Automatically promoted node ula:ula_\|clocks:clocks_\|clk_cpu " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648903994193 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "ula:ula_\|clocks:clocks_\|clk_cpu~0 " "Destination node ula:ula_\|clocks:clocks_\|clk_cpu~0" { } { { "ula/clocks.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/clocks.sv" 31 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ula:ula_|clocks:clocks_|clk_cpu~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 2624 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648903994193 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1648903994193 ""} } { { "ula/clocks.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/clocks.sv" 31 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ula:ula_|clocks:clocks_|clk_cpu } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1216 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648903994193 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "reset " "Automatically promoted node reset " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648903994193 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "z80_top_direct_n:z80_\|resets:resets_\|x1~0 " "Destination node z80_top_direct_n:z80_\|resets:resets_\|x1~0" { } { { "cpu/control/resets.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/resets.v" 42 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { z80_top_direct_n:z80_|resets:resets_|x1~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 3832 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648903994193 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1648903994193 ""} } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 62 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 1373 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648903994193 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "z80_top_direct_n:z80_\|resets:resets_\|SYNTHESIZED_WIRE_12 " "Automatically promoted node z80_top_direct_n:z80_\|resets:resets_\|SYNTHESIZED_WIRE_12 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648903994194 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[30\]~output " "Destination node GPIO_1\[30\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[30]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 3865 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648903994194 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[0\]~output " "Destination node GPIO_1\[0\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[0]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 3838 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648903994194 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[1\]~output " "Destination node GPIO_1\[1\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[1]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 3839 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648903994194 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[2\]~output " "Destination node GPIO_1\[2\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[2]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 3840 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648903994194 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[3\]~output " "Destination node GPIO_1\[3\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[3]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 3841 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648903994194 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[4\]~output " "Destination node GPIO_1\[4\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[4]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 3842 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648903994194 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[5\]~output " "Destination node GPIO_1\[5\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[5]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 3843 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648903994194 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[6\]~output " "Destination node GPIO_1\[6\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[6]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 3844 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648903994194 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[7\]~output " "Destination node GPIO_1\[7\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[7]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 3845 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648903994194 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[8\]~output " "Destination node GPIO_1\[8\]~output" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[8]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 3846 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1648903994194 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_LIMITED_TO_SUB" "10 " "Non-global destination nodes limited to 10 nodes" { } { } 0 176358 "Non-global destination nodes limited to %1!d! nodes" 0 0 "Quartus II" 0 -1 1648903994194 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1648903994194 ""} } { { "cpu/control/resets.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/resets.v" 52 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { z80_top_direct_n:z80_|resets:resets_|SYNTHESIZED_WIRE_12 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 673 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648903994194 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "z80_top_direct_n:z80_\|fpga_reset " "Automatically promoted node z80_top_direct_n:z80_\|fpga_reset " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648903994194 ""} } { { "cpu/toplevel/core.vh" "" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/core.vh" 13 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { z80_top_direct_n:z80_|fpga_reset } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 906 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648903994194 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "z80_top_direct_n:z80_\|interrupts:interrupts_\|SYNTHESIZED_WIRE_12 " "Automatically promoted node z80_top_direct_n:z80_\|interrupts:interrupts_\|SYNTHESIZED_WIRE_12 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648903994195 ""} } { { "cpu/control/interrupts.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/interrupts.v" 76 -1 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { z80_top_direct_n:z80_|interrupts:interrupts_|SYNTHESIZED_WIRE_12 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 745 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648903994195 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1648903994961 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1648903994964 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1648903994965 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1648903994969 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1648903994973 ""} +{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1648903994976 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1648903994976 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1648903994979 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1648903995727 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "9 I/O Output Buffer " "Packed 9 registers into blocks of type I/O Output Buffer" { } { } 1 176218 "Packed %1!d! registers into blocks of type %2!s!" 0 0 "Quartus II" 0 -1 1648903995730 ""} { "Extra Info" "IFSAC_NUM_REGISTERS_DUPLICATED" "8 " "Created 8 register duplicates" { } { } 1 176220 "Created %1!d! register duplicates" 0 0 "Quartus II" 0 -1 1648903995730 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1648903995730 ""} +{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_CS_N " "Node \"ADC_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648903995849 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SADDR " "Node \"ADC_SADDR\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SADDR" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648903995849 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SCLK " "Node \"ADC_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648903995849 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDAT " "Node \"ADC_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648903995849 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[0\] " "Node \"DRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648903995849 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[10\] " "Node \"DRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648903995849 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[11\] " "Node \"DRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648903995849 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[12\] " "Node \"DRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648903995849 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[1\] " "Node \"DRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648903995849 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[2\] " "Node \"DRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648903995849 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[3\] " "Node \"DRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648903995849 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[4\] " "Node \"DRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648903995849 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[5\] " "Node \"DRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648903995849 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[6\] " "Node \"DRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648903995849 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[7\] " "Node \"DRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648903995849 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[8\] " "Node \"DRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648903995849 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[9\] " "Node \"DRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648903995849 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[0\] " "Node \"DRAM_BA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648903995849 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[1\] " "Node \"DRAM_BA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648903995849 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CAS_N " "Node \"DRAM_CAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648903995849 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CKE " "Node \"DRAM_CKE\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CKE" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648903995849 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CLK " "Node \"DRAM_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648903995849 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CS_N " "Node \"DRAM_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648903995849 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[0\] " "Node \"DRAM_DQM\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648903995849 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[1\] " "Node \"DRAM_DQM\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648903995849 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[0\] " "Node \"DRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648903995849 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[10\] " "Node \"DRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648903995849 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[11\] " "Node \"DRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648903995849 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[12\] " "Node \"DRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648903995849 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[13\] " "Node \"DRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648903995849 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[14\] " "Node \"DRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648903995849 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[15\] " "Node \"DRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648903995849 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[1\] " "Node \"DRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648903995849 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[2\] " "Node \"DRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648903995849 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[3\] " "Node \"DRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648903995849 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[4\] " "Node \"DRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648903995849 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[5\] " "Node \"DRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648903995849 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[6\] " "Node \"DRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648903995849 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[7\] " "Node \"DRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648903995849 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[8\] " "Node \"DRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648903995849 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[9\] " "Node \"DRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648903995849 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_RAS_N " "Node \"DRAM_RAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_RAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648903995849 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_WE_N " "Node \"DRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648903995849 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_ASDO " "Node \"EPCS_ASDO\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_ASDO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648903995849 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_DATA0 " "Node \"EPCS_DATA0\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_DATA0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648903995849 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_DCLK " "Node \"EPCS_DCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_DCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648903995849 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_NCSO " "Node \"EPCS_NCSO\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_NCSO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648903995849 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[0\] " "Node \"GPIO_0\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648903995849 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[1\] " "Node \"GPIO_0\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648903995849 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[2\] " "Node \"GPIO_0\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648903995849 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[3\] " "Node \"GPIO_0\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648903995849 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[4\] " "Node \"GPIO_0\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648903995849 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[5\] " "Node \"GPIO_0\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648903995849 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[6\] " "Node \"GPIO_0\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648903995849 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[7\] " "Node \"GPIO_0\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648903995849 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[8\] " "Node \"GPIO_0\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648903995849 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[9\] " "Node \"GPIO_0\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648903995849 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0_IN\[0\] " "Node \"GPIO_0_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648903995849 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0_IN\[1\] " "Node \"GPIO_0_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648903995849 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1_IN\[0\] " "Node \"GPIO_1_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648903995849 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1_IN\[1\] " "Node \"GPIO_1_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648903995849 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[0\] " "Node \"GPIO_2\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648903995849 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[10\] " "Node \"GPIO_2\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648903995849 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[11\] " "Node \"GPIO_2\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648903995849 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[12\] " "Node \"GPIO_2\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648903995849 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[1\] " "Node \"GPIO_2\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648903995849 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[2\] " "Node \"GPIO_2\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648903995849 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[3\] " "Node \"GPIO_2\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648903995849 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[4\] " "Node \"GPIO_2\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648903995849 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[5\] " "Node \"GPIO_2\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648903995849 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[6\] " "Node \"GPIO_2\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648903995849 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[7\] " "Node \"GPIO_2\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648903995849 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[8\] " "Node \"GPIO_2\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648903995849 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[9\] " "Node \"GPIO_2\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648903995849 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[0\] " "Node \"GPIO_2_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648903995849 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[1\] " "Node \"GPIO_2_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648903995849 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[2\] " "Node \"GPIO_2_IN\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648903995849 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "G_SENSOR_CS_N " "Node \"G_SENSOR_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "G_SENSOR_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648903995849 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "G_SENSOR_INT " "Node \"G_SENSOR_INT\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "G_SENSOR_INT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648903995849 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1648903995849 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:03 " "Fitter preparation operations ending: elapsed time is 00:00:03" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648903995853 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1648903997307 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648903998078 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1648903998099 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1648904001190 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:03 " "Fitter placement operations ending: elapsed time is 00:00:03" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648904001190 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1648904002024 ""} +{ "Info" "IFITAPI_FITAPI_VPR_STATUS_DELAY_ADDED_FOR_HOLD" "6e+02 ns 1.4% " "6e+02 ns of routing delay (approximately 1.4% of available device routing delay) has been added to meet hold timing. For more information, refer to the Estimated Delay Added for Hold Timing section in the Fitter report." { } { } 0 170089 "%1!s! of routing delay (approximately %2!s! of available device routing delay) has been added to meet hold timing. For more information, refer to the Estimated Delay Added for Hold Timing section in the Fitter report." 0 0 "Fitter" 0 -1 1648904004205 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "4 " "Router estimated average interconnect usage is 4% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "31 X21_Y11 X31_Y22 " "Router estimated peak interconnect usage is 31% of the available device resources in the region that extends from location X21_Y11 to location X31_Y22" { } { { "loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 1 { 0 "Router estimated peak interconnect usage is 31% of the available device resources in the region that extends from location X21_Y11 to location X31_Y22"} { { 11 { 0 "Router estimated peak interconnect usage is 31% of the available device resources in the region that extends from location X21_Y11 to location X31_Y22"} 21 11 11 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1648904004832 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1648904004832 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:07 " "Fitter routing operations ending: elapsed time is 00:00:07" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648904009193 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1648904009196 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1648904009196 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "1.90 " "Total time spent on timing analysis during the Fitter is 1.90 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1648904009342 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1648904009401 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1648904010137 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1648904010188 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1648904010850 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:02 " "Fitter post-fit operations ending: elapsed time is 00:00:02" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648904011944 ""} +{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1648904012406 ""} +{ "Warning" "WFIOMGR_FIOMGR_REFER_APPNOTE_447_TOP_LEVEL" "41 Cyclone IV E " "41 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[0\] 3.3-V LVTTL M1 " "Pin SW\[0\] uses I/O standard 3.3-V LVTTL at M1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { SW[0] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[0\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 19 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { SW[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 141 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648904012421 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[3\] 3.3-V LVTTL M15 " "Pin SW\[3\] uses I/O standard 3.3-V LVTTL at M15" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { SW[3] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 19 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { SW[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 144 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648904012421 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[0\] 3.3-V LVTTL F13 " "Pin GPIO_1\[0\] uses I/O standard 3.3-V LVTTL at F13" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[0] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[0\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 145 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648904012421 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[1\] 3.3-V LVTTL T15 " "Pin GPIO_1\[1\] uses I/O standard 3.3-V LVTTL at T15" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[1] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[1\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 146 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648904012421 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[2\] 3.3-V LVTTL T14 " "Pin GPIO_1\[2\] uses I/O standard 3.3-V LVTTL at T14" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[2] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[2\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 147 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648904012421 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[3\] 3.3-V LVTTL T13 " "Pin GPIO_1\[3\] uses I/O standard 3.3-V LVTTL at T13" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[3] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[3\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 148 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648904012421 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[4\] 3.3-V LVTTL R13 " "Pin GPIO_1\[4\] uses I/O standard 3.3-V LVTTL at R13" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[4] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[4\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 149 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648904012421 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[5\] 3.3-V LVTTL T12 " "Pin GPIO_1\[5\] uses I/O standard 3.3-V LVTTL at T12" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[5] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[5\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 150 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648904012421 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[6\] 3.3-V LVTTL R12 " "Pin GPIO_1\[6\] uses I/O standard 3.3-V LVTTL at R12" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[6] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[6\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 151 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648904012421 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[7\] 3.3-V LVTTL T11 " "Pin GPIO_1\[7\] uses I/O standard 3.3-V LVTTL at T11" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[7] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[7\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 152 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648904012421 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[8\] 3.3-V LVTTL T10 " "Pin GPIO_1\[8\] uses I/O standard 3.3-V LVTTL at T10" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[8] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[8\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 153 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648904012421 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[9\] 3.3-V LVTTL R11 " "Pin GPIO_1\[9\] uses I/O standard 3.3-V LVTTL at R11" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[9] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[9\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 154 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648904012421 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[10\] 3.3-V LVTTL P11 " "Pin GPIO_1\[10\] uses I/O standard 3.3-V LVTTL at P11" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[10] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[10\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 155 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648904012421 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[11\] 3.3-V LVTTL R10 " "Pin GPIO_1\[11\] uses I/O standard 3.3-V LVTTL at R10" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[11] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[11\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 156 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648904012421 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[12\] 3.3-V LVTTL N12 " "Pin GPIO_1\[12\] uses I/O standard 3.3-V LVTTL at N12" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[12] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[12\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 157 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648904012421 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[13\] 3.3-V LVTTL P9 " "Pin GPIO_1\[13\] uses I/O standard 3.3-V LVTTL at P9" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[13] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[13\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 158 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648904012421 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[14\] 3.3-V LVTTL N9 " "Pin GPIO_1\[14\] uses I/O standard 3.3-V LVTTL at N9" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[14] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[14\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 159 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648904012421 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[15\] 3.3-V LVTTL N11 " "Pin GPIO_1\[15\] uses I/O standard 3.3-V LVTTL at N11" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[15] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[15\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 160 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648904012421 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[16\] 3.3-V LVTTL L16 " "Pin GPIO_1\[16\] uses I/O standard 3.3-V LVTTL at L16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[16] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[16\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[16] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 161 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648904012421 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[17\] 3.3-V LVTTL K16 " "Pin GPIO_1\[17\] uses I/O standard 3.3-V LVTTL at K16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[17] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[17\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[17] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 162 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648904012421 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[18\] 3.3-V LVTTL R16 " "Pin GPIO_1\[18\] uses I/O standard 3.3-V LVTTL at R16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[18] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[18\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[18] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 163 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648904012421 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[19\] 3.3-V LVTTL L15 " "Pin GPIO_1\[19\] uses I/O standard 3.3-V LVTTL at L15" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[19] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[19\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[19] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 164 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648904012421 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[20\] 3.3-V LVTTL P15 " "Pin GPIO_1\[20\] uses I/O standard 3.3-V LVTTL at P15" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[20] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[20\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[20] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 165 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648904012421 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[21\] 3.3-V LVTTL P16 " "Pin GPIO_1\[21\] uses I/O standard 3.3-V LVTTL at P16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[21] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[21\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[21] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 166 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648904012421 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[22\] 3.3-V LVTTL R14 " "Pin GPIO_1\[22\] uses I/O standard 3.3-V LVTTL at R14" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[22] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[22\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[22] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 167 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648904012421 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[23\] 3.3-V LVTTL N16 " "Pin GPIO_1\[23\] uses I/O standard 3.3-V LVTTL at N16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[23] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[23\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[23] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 168 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648904012421 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[27\] 3.3-V LVTTL N14 " "Pin GPIO_1\[27\] uses I/O standard 3.3-V LVTTL at N14" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[27] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[27\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[27] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 172 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648904012421 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[28\] 3.3-V LVTTL M10 " "Pin GPIO_1\[28\] uses I/O standard 3.3-V LVTTL at M10" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[28] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[28\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[28] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 173 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648904012421 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[29\] 3.3-V LVTTL L13 " "Pin GPIO_1\[29\] uses I/O standard 3.3-V LVTTL at L13" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[29] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[29\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[29] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 174 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648904012421 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[30\] 3.3-V LVTTL J16 " "Pin GPIO_1\[30\] uses I/O standard 3.3-V LVTTL at J16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { GPIO_1[30] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[30\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { GPIO_1[30] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 175 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648904012421 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "I2C_SCLK 3.3-V LVTTL F2 " "Pin I2C_SCLK uses I/O standard 3.3-V LVTTL at F2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { I2C_SCLK } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "I2C_SCLK" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 6 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { I2C_SCLK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 182 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648904012421 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "I2C_SDAT 3.3-V LVTTL F1 " "Pin I2C_SDAT uses I/O standard 3.3-V LVTTL at F1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { I2C_SDAT } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 7 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { I2C_SDAT } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 183 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648904012421 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[1\] 3.3-V LVTTL T8 " "Pin SW\[1\] uses I/O standard 3.3-V LVTTL at T8" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { SW[1] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 19 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { SW[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 142 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648904012421 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[2\] 3.3-V LVTTL B9 " "Pin SW\[2\] uses I/O standard 3.3-V LVTTL at B9" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { SW[2] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 19 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { SW[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 143 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648904012421 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "raw_loader_in 3.3-V LVTTL B6 " "Pin raw_loader_in uses I/O standard 3.3-V LVTTL at B6" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { raw_loader_in } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "raw_loader_in" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 23 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { raw_loader_in } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 193 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648904012421 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "KEY\[0\] 3.3-V LVTTL J15 " "Pin KEY\[0\] uses I/O standard 3.3-V LVTTL at J15" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { KEY[0] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "KEY\[0\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 3 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { KEY[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 127 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648904012421 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "CLOCK_50 3.3-V LVTTL R8 " "Pin CLOCK_50 uses I/O standard 3.3-V LVTTL at R8" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { CLOCK_50 } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 2 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 179 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648904012421 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "PS2_DAT 3.3-V LVTTL B7 " "Pin PS2_DAT uses I/O standard 3.3-V LVTTL at B7" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { PS2_DAT } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "PS2_DAT" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 5 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { PS2_DAT } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 181 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648904012421 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "KEY\[1\] 3.3-V LVTTL E1 " "Pin KEY\[1\] uses I/O standard 3.3-V LVTTL at E1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { KEY[1] } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "KEY\[1\]" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 3 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { KEY[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 128 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648904012421 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "PS2_CLK 3.3-V LVTTL D6 " "Pin PS2_CLK uses I/O standard 3.3-V LVTTL at D6" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { PS2_CLK } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "PS2_CLK" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 4 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { PS2_CLK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 180 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648904012421 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "AUD_ADCDAT 3.3-V LVTTL D8 " "Pin AUD_ADCDAT uses I/O standard 3.3-V LVTTL at D8" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { AUD_ADCDAT } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "AUD_ADCDAT" } } } } { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 13 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { AUD_ADCDAT } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/spectrum/" { { 0 { 0 ""} 0 189 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648904012421 ""} } { } 0 169177 "%1!d! pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing %2!s! Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." 0 0 "Fitter" 0 -1 1648904012421 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/benny/work/fpga/spectrum/output_files/spectrum.fit.smsg " "Generated suppressed messages file /home/benny/work/fpga/spectrum/output_files/spectrum.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1648904012764 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 615 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 615 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "634 " "Peak virtual memory: 634 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648904013575 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 2 15:53:33 2022 " "Processing ended: Sat Apr 2 15:53:33 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648904013575 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:22 " "Elapsed time: 00:00:22" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648904013575 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:22 " "Total CPU time (on all processors): 00:00:22" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648904013575 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1648904013575 ""} diff --git a/db/spectrum.hier_info b/db/spectrum.hier_info index 92a74a1..e2307e9 100644 --- a/db/spectrum.hier_info +++ b/db/spectrum.hier_info @@ -1,79 +1,79 @@ |spectrum -LED[0] << SW[1].DB_MAX_OUTPUT_PORT_TYPE -LED[1] << -LED[2] << SW[2].DB_MAX_OUTPUT_PORT_TYPE -LED[3] << raw_loader_in.DB_MAX_OUTPUT_PORT_TYPE -LED[4] << -LED[5] << -LED[6] << -LED[7] << -CLOCK_50 => CLOCK_50.IN3 +LED[0] <= SW[1].DB_MAX_OUTPUT_PORT_TYPE +LED[1] <= +LED[2] <= SW[2].DB_MAX_OUTPUT_PORT_TYPE +LED[3] <= raw_loader_in.DB_MAX_OUTPUT_PORT_TYPE +LED[4] <= +LED[5] <= +LED[6] <= +LED[7] <= +CLOCK_50 => CLOCK_50.IN2 KEY[0] => reset.IN1 KEY[1] => nNMI.IN1 PS2_CLK => PS2_CLK.IN1 PS2_DAT => PS2_DAT.IN1 I2C_SCLK <> ula:ula_.I2C_SCLK I2C_SDAT <> ula:ula_.I2C_SDAT -AUD_XCK << ula:ula_.AUD_XCK -AUD_ADCLRCK << ula:ula_.AUD_ADCLRCK -AUD_DACLRCK << ula:ula_.AUD_DACLRCK -AUD_BCLK << ula:ula_.AUD_BCLK -AUD_DACDAT << ula:ula_.AUD_DACDAT +AUD_XCK <= ula:ula_.AUD_XCK +AUD_ADCLRCK <= ula:ula_.AUD_ADCLRCK +AUD_DACLRCK <= ula:ula_.AUD_DACLRCK +AUD_BCLK <= ula:ula_.AUD_BCLK +AUD_DACDAT <= ula:ula_.AUD_DACDAT AUD_ADCDAT => AUD_ADCDAT.IN1 -VGA_R[0] << ula:ula_.VGA_R -VGA_R[1] << ula:ula_.VGA_R -VGA_R[2] << ula:ula_.VGA_R -VGA_R[3] << ula:ula_.VGA_R -VGA_G[0] << ula:ula_.VGA_G -VGA_G[1] << ula:ula_.VGA_G -VGA_G[2] << ula:ula_.VGA_G -VGA_G[3] << ula:ula_.VGA_G -VGA_B[0] << ula:ula_.VGA_B -VGA_B[1] << ula:ula_.VGA_B -VGA_B[2] << ula:ula_.VGA_B -VGA_B[3] << ula:ula_.VGA_B -VGA_HS << ula:ula_.VGA_HS -VGA_VS << ula:ula_.VGA_VS +VGA_R[0] <= ula:ula_.VGA_R +VGA_R[1] <= ula:ula_.VGA_R +VGA_R[2] <= ula:ula_.VGA_R +VGA_R[3] <= ula:ula_.VGA_R +VGA_G[0] <= ula:ula_.VGA_G +VGA_G[1] <= ula:ula_.VGA_G +VGA_G[2] <= ula:ula_.VGA_G +VGA_G[3] <= ula:ula_.VGA_G +VGA_B[0] <= ula:ula_.VGA_B +VGA_B[1] <= ula:ula_.VGA_B +VGA_B[2] <= ula:ula_.VGA_B +VGA_B[3] <= ula:ula_.VGA_B +VGA_HS <= ula:ula_.VGA_HS +VGA_VS <= ula:ula_.VGA_VS SW[0] => ~NO_FANOUT~ SW[1] => LED[0].DATAIN SW[1] => comb.OUTPUTSELECT SW[2] => SW[2].IN1 SW[3] => ~NO_FANOUT~ -GPIO_1[0] << A[0].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[1] << A[1].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[2] << A[2].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[3] << A[3].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[4] << A[4].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[5] << A[5].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[6] << A[6].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[7] << A[7].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[8] << A[8].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[9] << A[9].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[10] << A[10].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[11] << A[11].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[12] << A[12].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[13] << A[13].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[14] << A[14].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[15] << A[15].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[16] << D[0].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[17] << D[1].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[18] << D[2].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[19] << D[3].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[20] << D[4].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[21] << D[5].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[22] << D[6].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[23] << D[7].DB_MAX_OUTPUT_PORT_TYPE -GPIO_1[24] << z80_top_direct_n:z80_.nBUSACK -GPIO_1[25] << z80_top_direct_n:z80_.nHALT -GPIO_1[26] << z80_top_direct_n:z80_.nRFSH -GPIO_1[27] << z80_top_direct_n:z80_.nWR -GPIO_1[28] << z80_top_direct_n:z80_.nRD -GPIO_1[29] << z80_top_direct_n:z80_.nIORQ -GPIO_1[30] << z80_top_direct_n:z80_.nMREQ -GPIO_1[31] << z80_top_direct_n:z80_.nM1 -GPIO_1[32] << -GPIO_1[33] << -buzzer_out << ula:ula_.beep +GPIO_1[0] <= A[0].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[1] <= A[1].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[2] <= A[2].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[3] <= A[3].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[4] <= A[4].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[5] <= A[5].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[6] <= A[6].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[7] <= A[7].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[8] <= A[8].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[9] <= A[9].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[10] <= A[10].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[11] <= A[11].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[12] <= A[12].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[13] <= A[13].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[14] <= A[14].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[15] <= A[15].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[16] <= D[0].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[17] <= D[1].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[18] <= D[2].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[19] <= D[3].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[20] <= D[4].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[21] <= D[5].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[22] <= D[6].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[23] <= D[7].DB_MAX_OUTPUT_PORT_TYPE +GPIO_1[24] <= z80_top_direct_n:z80_.nBUSACK +GPIO_1[25] <= z80_top_direct_n:z80_.nHALT +GPIO_1[26] <= z80_top_direct_n:z80_.nRFSH +GPIO_1[27] <= z80_top_direct_n:z80_.nWR +GPIO_1[28] <= z80_top_direct_n:z80_.nRD +GPIO_1[29] <= z80_top_direct_n:z80_.nIORQ +GPIO_1[30] <= z80_top_direct_n:z80_.nMREQ +GPIO_1[31] <= z80_top_direct_n:z80_.nM1 +GPIO_1[32] <= +GPIO_1[33] <= +buzzer_out <= ula:ula_.beep raw_loader_in => raw_loader_in.IN1 diff --git a/db/spectrum.hif b/db/spectrum.hif index 1ef198c..f48be2a 100644 Binary files a/db/spectrum.hif and b/db/spectrum.hif differ diff --git a/db/spectrum.ipinfo b/db/spectrum.ipinfo index 22d055f..0e5c4b6 100644 Binary files a/db/spectrum.ipinfo and b/db/spectrum.ipinfo differ diff --git a/db/spectrum.map.bpm b/db/spectrum.map.bpm index 2eeb07a..59002c2 100644 Binary files a/db/spectrum.map.bpm and b/db/spectrum.map.bpm differ diff --git a/db/spectrum.map.cdb b/db/spectrum.map.cdb index 0aaf4b3..348f3fd 100644 Binary files a/db/spectrum.map.cdb and b/db/spectrum.map.cdb differ diff --git a/db/spectrum.map.hdb b/db/spectrum.map.hdb index e01f3b5..1d5d555 100644 Binary files a/db/spectrum.map.hdb and b/db/spectrum.map.hdb differ diff --git a/db/spectrum.map.kpt b/db/spectrum.map.kpt index ca4b38c..0a22d52 100644 Binary files a/db/spectrum.map.kpt and b/db/spectrum.map.kpt differ diff --git a/db/spectrum.map.qmsg b/db/spectrum.map.qmsg index 5e06b04..2fd02fa 100644 --- a/db/spectrum.map.qmsg +++ b/db/spectrum.map.qmsg @@ -1,159 +1,159 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648828504365 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648828504366 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Apr 1 18:55:04 2022 " "Processing started: Fri Apr 1 18:55:04 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648828504366 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648828504366 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum " "Command: quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648828504367 ""} -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1648828504551 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "spectrum.sv 1 1 " "Found 1 design units, including 1 entities, in source file spectrum.sv" { { "Info" "ISGN_ENTITY_NAME" "1 spectrum " "Found entity 1: spectrum" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504625 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504625 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rom0.v 1 1 " "Found 1 design units, including 1 entities, in source file rom0.v" { { "Info" "ISGN_ENTITY_NAME" "1 rom0 " "Found entity 1: rom0" { } { { "rom0.v" "" { Text "/home/benny/work/fpga/spectrum/rom0.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504626 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504626 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram16.v 1 1 " "Found 1 design units, including 1 entities, in source file ram16.v" { { "Info" "ISGN_ENTITY_NAME" "1 ram16 " "Found entity 1: ram16" { } { { "ram16.v" "" { Text "/home/benny/work/fpga/spectrum/ram16.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504627 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504627 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram32.v 1 1 " "Found 1 design units, including 1 entities, in source file ram32.v" { { "Info" "ISGN_ENTITY_NAME" "1 ram32 " "Found entity 1: ram32" { } { { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504628 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504628 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pll.v 1 1 " "Found 1 design units, including 1 entities, in source file pll.v" { { "Info" "ISGN_ENTITY_NAME" "1 pll " "Found entity 1: pll" { } { { "pll.v" "" { Text "/home/benny/work/fpga/spectrum/pll.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504629 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504629 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu " "Found entity 1: alu" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504630 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504630 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_bit_select.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_bit_select.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_bit_select " "Found entity 1: alu_bit_select" { } { { "cpu/alu/alu_bit_select.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_bit_select.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504631 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504631 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_control.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_control " "Found entity 1: alu_control" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504632 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504632 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_core.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_core.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_core " "Found entity 1: alu_core" { } { { "cpu/alu/alu_core.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_core.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504633 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504633 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_flags.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_flags.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_flags " "Found entity 1: alu_flags" { } { { "cpu/alu/alu_flags.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_flags.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504634 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504634 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_2.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_2.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_2 " "Found entity 1: alu_mux_2" { } { { "cpu/alu/alu_mux_2.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_2.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504635 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504635 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_2z.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_2z.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_2z " "Found entity 1: alu_mux_2z" { } { { "cpu/alu/alu_mux_2z.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_2z.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504635 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504635 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_3z.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_3z.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_3z " "Found entity 1: alu_mux_3z" { } { { "cpu/alu/alu_mux_3z.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_3z.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504636 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504636 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_4.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_4.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_4 " "Found entity 1: alu_mux_4" { } { { "cpu/alu/alu_mux_4.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_4.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504637 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504637 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_8.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_8.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_8 " "Found entity 1: alu_mux_8" { } { { "cpu/alu/alu_mux_8.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_8.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504638 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504638 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_prep_daa.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_prep_daa.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_prep_daa " "Found entity 1: alu_prep_daa" { } { { "cpu/alu/alu_prep_daa.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_prep_daa.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504639 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504639 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_select.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_select.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_select " "Found entity 1: alu_select" { } { { "cpu/alu/alu_select.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_select.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504639 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504639 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_shifter_core.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_shifter_core.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_shifter_core " "Found entity 1: alu_shifter_core" { } { { "cpu/alu/alu_shifter_core.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_shifter_core.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504640 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504640 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_slice.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_slice.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_slice " "Found entity 1: alu_slice" { } { { "cpu/alu/alu_slice.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_slice.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504641 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504641 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/clk_delay.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/clk_delay.v" { { "Info" "ISGN_ENTITY_NAME" "1 clk_delay " "Found entity 1: clk_delay" { } { { "cpu/control/clk_delay.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/clk_delay.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504642 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504642 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/decode_state.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/decode_state.v" { { "Info" "ISGN_ENTITY_NAME" "1 decode_state " "Found entity 1: decode_state" { } { { "cpu/control/decode_state.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/decode_state.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504643 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504643 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/execute.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/execute.v" { { "Info" "ISGN_ENTITY_NAME" "1 execute " "Found entity 1: execute" { } { { "cpu/control/execute.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/execute.v" 25 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504669 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504669 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/interrupts.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/interrupts.v" { { "Info" "ISGN_ENTITY_NAME" "1 interrupts " "Found entity 1: interrupts" { } { { "cpu/control/interrupts.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/interrupts.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504670 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504670 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/ir.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/ir.v" { { "Info" "ISGN_ENTITY_NAME" "1 ir " "Found entity 1: ir" { } { { "cpu/control/ir.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/ir.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504671 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504671 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/memory_ifc.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/memory_ifc.v" { { "Info" "ISGN_ENTITY_NAME" "1 memory_ifc " "Found entity 1: memory_ifc" { } { { "cpu/control/memory_ifc.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/memory_ifc.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504672 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504672 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/pin_control.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/pin_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 pin_control " "Found entity 1: pin_control" { } { { "cpu/control/pin_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/pin_control.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504673 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504673 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/pla_decode.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/pla_decode.v" { { "Info" "ISGN_ENTITY_NAME" "1 pla_decode " "Found entity 1: pla_decode" { } { { "cpu/control/pla_decode.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/pla_decode.v" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504675 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504675 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/resets.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/resets.v" { { "Info" "ISGN_ENTITY_NAME" "1 resets " "Found entity 1: resets" { } { { "cpu/control/resets.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/resets.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504675 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504675 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/sequencer.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/sequencer.v" { { "Info" "ISGN_ENTITY_NAME" "1 sequencer " "Found entity 1: sequencer" { } { { "cpu/control/sequencer.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/sequencer.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504676 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504676 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/address_latch.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/address_latch.v" { { "Info" "ISGN_ENTITY_NAME" "1 address_latch " "Found entity 1: address_latch" { } { { "cpu/bus/address_latch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_latch.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504677 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504677 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/address_mux.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/address_mux.v" { { "Info" "ISGN_ENTITY_NAME" "1 address_mux " "Found entity 1: address_mux" { } { { "cpu/bus/address_mux.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_mux.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504678 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504678 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/address_pins.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/address_pins.v" { { "Info" "ISGN_ENTITY_NAME" "1 address_pins " "Found entity 1: address_pins" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504679 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504679 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/bus_control.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/bus_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 bus_control " "Found entity 1: bus_control" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504680 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504680 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/bus_switch.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/bus_switch.v" { { "Info" "ISGN_ENTITY_NAME" "1 bus_switch " "Found entity 1: bus_switch" { } { { "cpu/bus/bus_switch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_switch.v" 12 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504680 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504680 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/control_pins_n.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/control_pins_n.v" { { "Info" "ISGN_ENTITY_NAME" "1 control_pins_n " "Found entity 1: control_pins_n" { } { { "cpu/bus/control_pins_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/control_pins_n.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504681 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504681 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/data_pins.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/data_pins.v" { { "Info" "ISGN_ENTITY_NAME" "1 data_pins " "Found entity 1: data_pins" { } { { "cpu/bus/data_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_pins.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504682 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504682 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/data_switch.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/data_switch.v" { { "Info" "ISGN_ENTITY_NAME" "1 data_switch " "Found entity 1: data_switch" { } { { "cpu/bus/data_switch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504683 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504683 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/data_switch_mask.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/data_switch_mask.v" { { "Info" "ISGN_ENTITY_NAME" "1 data_switch_mask " "Found entity 1: data_switch_mask" { } { { "cpu/bus/data_switch_mask.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch_mask.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504684 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504684 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/inc_dec.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/inc_dec.v" { { "Info" "ISGN_ENTITY_NAME" "1 inc_dec " "Found entity 1: inc_dec" { } { { "cpu/bus/inc_dec.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/inc_dec.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504685 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504685 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/inc_dec_2bit.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/inc_dec_2bit.v" { { "Info" "ISGN_ENTITY_NAME" "1 inc_dec_2bit " "Found entity 1: inc_dec_2bit" { } { { "cpu/bus/inc_dec_2bit.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/inc_dec_2bit.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504685 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504685 ""} -{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "nRESET nreset z80_top_direct_n.v(19) " "Verilog HDL Declaration information at z80_top_direct_n.v(19): object \"nRESET\" differs only in case from object \"nreset\" in the same scope" { } { { "cpu/toplevel/z80_top_direct_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 19 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1648828504688 ""} -{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CLK clk z80_top_direct_n.v(22) " "Verilog HDL Declaration information at z80_top_direct_n.v(22): object \"CLK\" differs only in case from object \"clk\" in the same scope" { } { { "cpu/toplevel/z80_top_direct_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1648828504688 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/toplevel/z80_top_direct_n.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/toplevel/z80_top_direct_n.v" { { "Info" "ISGN_ENTITY_NAME" "1 z80_top_direct_n " "Found entity 1: z80_top_direct_n" { } { { "cpu/toplevel/z80_top_direct_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 6 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504688 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504688 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/registers/reg_control.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/registers/reg_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 reg_control " "Found entity 1: reg_control" { } { { "cpu/registers/reg_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_control.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504689 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504689 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/registers/reg_file.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/registers/reg_file.v" { { "Info" "ISGN_ENTITY_NAME" "1 reg_file " "Found entity 1: reg_file" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504691 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504691 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/registers/reg_latch.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/registers/reg_latch.v" { { "Info" "ISGN_ENTITY_NAME" "1 reg_latch " "Found entity 1: reg_latch" { } { { "cpu/registers/reg_latch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_latch.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504692 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504692 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/clocks.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/clocks.sv" { { "Info" "ISGN_ENTITY_NAME" "1 clocks " "Found entity 1: clocks" { } { { "ula/clocks.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/clocks.sv" 26 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504692 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504692 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/zx_kbd.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/zx_kbd.sv" { { "Info" "ISGN_ENTITY_NAME" "1 zx_keyboard " "Found entity 1: zx_keyboard" { } { { "ula/zx_kbd.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/zx_kbd.sv" 38 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504693 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504693 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/video.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/video.sv" { { "Info" "ISGN_ENTITY_NAME" "1 video " "Found entity 1: video" { } { { "ula/video.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/video.sv" 26 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504695 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504695 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/ula.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/ula.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ula " "Found entity 1: ula" { } { { "ula/ula.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 20 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504695 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504695 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/ps2_kbd.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/ps2_kbd.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ps2_keyboard " "Found entity 1: ps2_keyboard" { } { { "ula/ps2_kbd.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/ps2_kbd.sv" 20 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828504696 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828504696 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/i2c_loader.vhd 2 1 " "Found 2 design units, including 1 entities, in source file ula/i2c_loader.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 i2c_loader-i2c_loader_arch " "Found design unit 1: i2c_loader-i2c_loader_arch" { } { { "ula/i2c_loader.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2c_loader.vhd" 64 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828505020 ""} { "Info" "ISGN_ENTITY_NAME" "1 i2c_loader " "Found entity 1: i2c_loader" { } { { "ula/i2c_loader.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2c_loader.vhd" 41 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828505020 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828505020 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/i2s_intf.vhd 2 1 " "Found 2 design units, including 1 entities, in source file ula/i2s_intf.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 i2s_intf-i2s_intf_arch " "Found design unit 1: i2s_intf-i2s_intf_arch" { } { { "ula/i2s_intf.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2s_intf.vhd" 82 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828505021 ""} { "Info" "ISGN_ENTITY_NAME" "1 i2s_intf " "Found entity 1: i2s_intf" { } { { "ula/i2s_intf.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2s_intf.vhd" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828505021 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828505021 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rom_scr.v 1 1 " "Found 1 design units, including 1 entities, in source file rom_scr.v" { { "Info" "ISGN_ENTITY_NAME" "1 rom_scr " "Found entity 1: rom_scr" { } { { "rom_scr.v" "" { Text "/home/benny/work/fpga/spectrum/rom_scr.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828505024 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828505024 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pll_video.v 1 1 " "Found 1 design units, including 1 entities, in source file pll_video.v" { { "Info" "ISGN_ENTITY_NAME" "1 pll_video " "Found entity 1: pll_video" { } { { "pll_video.v" "" { Text "/home/benny/work/fpga/spectrum/pll_video.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828505025 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828505025 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram_video.v 1 1 " "Found 1 design units, including 1 entities, in source file ram_video.v" { { "Info" "ISGN_ENTITY_NAME" "1 ram_video " "Found entity 1: ram_video" { } { { "ram_video.v" "" { Text "/home/benny/work/fpga/spectrum/ram_video.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828505026 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828505026 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "spectrum " "Elaborating entity \"spectrum\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1648828505193 ""} -{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LED\[7..4\] spectrum.sv(1) " "Output port \"LED\[7..4\]\" at spectrum.sv(1) has no driver" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1648828505195 "|spectrum"} -{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LED\[1\] spectrum.sv(1) " "Output port \"LED\[1\]\" at spectrum.sv(1) has no driver" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1648828505195 "|spectrum"} -{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "GPIO_1\[33..32\] spectrum.sv(20) " "Output port \"GPIO_1\[33..32\]\" at spectrum.sv(20) has no driver" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1648828505195 "|spectrum"} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rom0 rom0:rom " "Elaborating entity \"rom0\" for hierarchy \"rom0:rom\"" { } { { "spectrum.sv" "rom" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 135 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505197 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram rom0:rom\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\"" { } { { "rom0.v" "altsyncram_component" { Text "/home/benny/work/fpga/spectrum/rom0.v" 81 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505251 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "rom0:rom\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"rom0:rom\|altsyncram:altsyncram_component\"" { } { { "rom0.v" "" { Text "/home/benny/work/fpga/spectrum/rom0.v" 81 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828505252 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "rom0:rom\|altsyncram:altsyncram_component " "Instantiated megafunction \"rom0:rom\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a NONE " "Parameter \"address_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505252 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a BYPASS " "Parameter \"clock_enable_input_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505252 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_a BYPASS " "Parameter \"clock_enable_output_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505252 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file ./rom/gw03.hex " "Parameter \"init_file\" = \"./rom/gw03.hex\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505252 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505252 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ENABLE_RUNTIME_MOD=NO " "Parameter \"lpm_hint\" = \"ENABLE_RUNTIME_MOD=NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505252 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505252 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 16384 " "Parameter \"numwords_a\" = \"16384\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505252 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode ROM " "Parameter \"operation_mode\" = \"ROM\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505252 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505252 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Parameter \"outdata_reg_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505252 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 14 " "Parameter \"widthad_a\" = \"14\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505252 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 8 " "Parameter \"width_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505252 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505252 ""} } { { "rom0.v" "" { Text "/home/benny/work/fpga/spectrum/rom0.v" 81 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1648828505252 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_qh91.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_qh91.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_qh91 " "Found entity 1: altsyncram_qh91" { } { { "db/altsyncram_qh91.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_qh91.tdf" 31 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828505305 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828505305 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_qh91 rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated " "Elaborating entity \"altsyncram_qh91\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505305 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_c8a.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_c8a.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_c8a " "Found entity 1: decode_c8a" { } { { "db/decode_c8a.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/decode_c8a.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828505350 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828505350 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_c8a rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|decode_c8a:rden_decode " "Elaborating entity \"decode_c8a\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|decode_c8a:rden_decode\"" { } { { "db/altsyncram_qh91.tdf" "rden_decode" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_qh91.tdf" 40 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505350 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_3nb.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mux_3nb.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_3nb " "Found entity 1: mux_3nb" { } { { "db/mux_3nb.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/mux_3nb.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828505395 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828505395 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux_3nb rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|mux_3nb:mux2 " "Elaborating entity \"mux_3nb\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|mux_3nb:mux2\"" { } { { "db/altsyncram_qh91.tdf" "mux2" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_qh91.tdf" 41 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505396 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ram16 ram16:ram0 " "Elaborating entity \"ram16\" for hierarchy \"ram16:ram0\"" { } { { "spectrum.sv" "ram0" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 157 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505400 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram ram16:ram0\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"ram16:ram0\|altsyncram:altsyncram_component\"" { } { { "ram16.v" "altsyncram_component" { Text "/home/benny/work/fpga/spectrum/ram16.v" 97 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505404 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "ram16:ram0\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"ram16:ram0\|altsyncram:altsyncram_component\"" { } { { "ram16.v" "" { Text "/home/benny/work/fpga/spectrum/ram16.v" 97 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828505405 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ram16:ram0\|altsyncram:altsyncram_component " "Instantiated megafunction \"ram16:ram0\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505406 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a BYPASS " "Parameter \"clock_enable_input_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505406 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_b BYPASS " "Parameter \"clock_enable_input_b\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505406 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_a BYPASS " "Parameter \"clock_enable_output_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505406 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_b BYPASS " "Parameter \"clock_enable_output_b\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505406 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_reg_b CLOCK0 " "Parameter \"indata_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505406 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file ula/test_scr.hex " "Parameter \"init_file\" = \"ula/test_scr.hex\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505406 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505406 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505406 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 16384 " "Parameter \"numwords_a\" = \"16384\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505406 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 16384 " "Parameter \"numwords_b\" = \"16384\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505406 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode BIDIR_DUAL_PORT " "Parameter \"operation_mode\" = \"BIDIR_DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505406 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505406 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_b NONE " "Parameter \"outdata_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505406 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Parameter \"outdata_reg_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505406 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b CLOCK0 " "Parameter \"outdata_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505406 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "power_up_uninitialized FALSE " "Parameter \"power_up_uninitialized\" = \"FALSE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505406 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505406 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_port_a NEW_DATA_NO_NBE_READ " "Parameter \"read_during_write_mode_port_a\" = \"NEW_DATA_NO_NBE_READ\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505406 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_port_b NEW_DATA_NO_NBE_READ " "Parameter \"read_during_write_mode_port_b\" = \"NEW_DATA_NO_NBE_READ\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505406 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 14 " "Parameter \"widthad_a\" = \"14\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505406 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 14 " "Parameter \"widthad_b\" = \"14\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505406 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 8 " "Parameter \"width_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505406 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 8 " "Parameter \"width_b\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505406 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505406 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_b 1 " "Parameter \"width_byteena_b\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505406 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_wraddress_reg_b CLOCK0 " "Parameter \"wrcontrol_wraddress_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505406 ""} } { { "ram16.v" "" { Text "/home/benny/work/fpga/spectrum/ram16.v" 97 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1648828505406 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_7ti2.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_7ti2.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_7ti2 " "Found entity 1: altsyncram_7ti2" { } { { "db/altsyncram_7ti2.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_7ti2.tdf" 33 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828505460 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828505460 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_7ti2 ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated " "Elaborating entity \"altsyncram_7ti2\" for hierarchy \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505460 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_jsa.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_jsa.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_jsa " "Found entity 1: decode_jsa" { } { { "db/decode_jsa.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/decode_jsa.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828505507 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828505507 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_jsa ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|decode_jsa:decode2 " "Elaborating entity \"decode_jsa\" for hierarchy \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|decode_jsa:decode2\"" { } { { "db/altsyncram_7ti2.tdf" "decode2" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_7ti2.tdf" 50 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505508 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ram32 ram32:ram1 " "Elaborating entity \"ram32\" for hierarchy \"ram32:ram1\"" { } { { "spectrum.sv" "ram1" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 170 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505514 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram ram32:ram1\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"ram32:ram1\|altsyncram:altsyncram_component\"" { } { { "ram32.v" "altsyncram_component" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505518 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "ram32:ram1\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"ram32:ram1\|altsyncram:altsyncram_component\"" { } { { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828505519 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ram32:ram1\|altsyncram:altsyncram_component " "Instantiated megafunction \"ram32:ram1\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a BYPASS " "Parameter \"clock_enable_input_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505519 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_a BYPASS " "Parameter \"clock_enable_output_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505519 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file led_patterns.mif " "Parameter \"init_file\" = \"led_patterns.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505519 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505519 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ENABLE_RUNTIME_MOD=NO " "Parameter \"lpm_hint\" = \"ENABLE_RUNTIME_MOD=NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505519 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505519 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 32768 " "Parameter \"numwords_a\" = \"32768\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505519 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode SINGLE_PORT " "Parameter \"operation_mode\" = \"SINGLE_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505519 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505519 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Parameter \"outdata_reg_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505519 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "power_up_uninitialized FALSE " "Parameter \"power_up_uninitialized\" = \"FALSE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505519 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_port_a NEW_DATA_NO_NBE_READ " "Parameter \"read_during_write_mode_port_a\" = \"NEW_DATA_NO_NBE_READ\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505519 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 15 " "Parameter \"widthad_a\" = \"15\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505519 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 8 " "Parameter \"width_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505519 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505519 ""} } { { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1648828505519 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_g9i1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_g9i1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_g9i1 " "Found entity 1: altsyncram_g9i1" { } { { "db/altsyncram_g9i1.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 33 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828505573 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828505573 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_g9i1 ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated " "Elaborating entity \"altsyncram_g9i1\" for hierarchy \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505573 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_msa.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_msa.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_msa " "Found entity 1: decode_msa" { } { { "db/decode_msa.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/decode_msa.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828505618 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828505618 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_msa ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|decode_msa:decode3 " "Elaborating entity \"decode_msa\" for hierarchy \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|decode_msa:decode3\"" { } { { "db/altsyncram_g9i1.tdf" "decode3" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 44 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505619 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_f8a.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_f8a.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_f8a " "Found entity 1: decode_f8a" { } { { "db/decode_f8a.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/decode_f8a.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828505662 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828505662 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_f8a ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|decode_f8a:rden_decode " "Elaborating entity \"decode_f8a\" for hierarchy \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|decode_f8a:rden_decode\"" { } { { "db/altsyncram_g9i1.tdf" "rden_decode" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 45 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505662 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_6nb.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mux_6nb.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_6nb " "Found entity 1: mux_6nb" { } { { "db/mux_6nb.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/mux_6nb.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828505706 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828505706 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux_6nb ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|mux_6nb:mux2 " "Elaborating entity \"mux_6nb\" for hierarchy \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|mux_6nb:mux2\"" { } { { "db/altsyncram_g9i1.tdf" "mux2" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 46 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505707 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ula ula:ula_ " "Elaborating entity \"ula\" for hierarchy \"ula:ula_\"" { } { { "spectrum.sv" "ula_" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 229 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505709 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pll ula:ula_\|pll:pll_ " "Elaborating entity \"pll\" for hierarchy \"ula:ula_\|pll:pll_\"" { } { { "ula/ula.sv" "pll_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 83 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505711 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll ula:ula_\|pll:pll_\|altpll:altpll_component " "Elaborating entity \"altpll\" for hierarchy \"ula:ula_\|pll:pll_\|altpll:altpll_component\"" { } { { "pll.v" "altpll_component" { Text "/home/benny/work/fpga/spectrum/pll.v" 102 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505739 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "ula:ula_\|pll:pll_\|altpll:altpll_component " "Elaborated megafunction instantiation \"ula:ula_\|pll:pll_\|altpll:altpll_component\"" { } { { "pll.v" "" { Text "/home/benny/work/fpga/spectrum/pll.v" 102 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ula:ula_\|pll:pll_\|altpll:altpll_component " "Instantiated megafunction \"ula:ula_\|pll:pll_\|altpll:altpll_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "bandwidth_type AUTO " "Parameter \"bandwidth_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_divide_by 2000 " "Parameter \"clk0_divide_by\" = \"2000\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_duty_cycle 50 " "Parameter \"clk0_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_multiply_by 1007 " "Parameter \"clk0_multiply_by\" = \"1007\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_phase_shift 0 " "Parameter \"clk0_phase_shift\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_divide_by 25 " "Parameter \"clk1_divide_by\" = \"25\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_duty_cycle 50 " "Parameter \"clk1_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_multiply_by 7 " "Parameter \"clk1_multiply_by\" = \"7\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_phase_shift 0 " "Parameter \"clk1_phase_shift\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_divide_by 25 " "Parameter \"clk2_divide_by\" = \"25\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_duty_cycle 50 " "Parameter \"clk2_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_multiply_by 12 " "Parameter \"clk2_multiply_by\" = \"12\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_phase_shift 0 " "Parameter \"clk2_phase_shift\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "compensate_clock CLK0 " "Parameter \"compensate_clock\" = \"CLK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "inclk0_input_frequency 20000 " "Parameter \"inclk0_input_frequency\" = \"20000\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint CBX_MODULE_PREFIX=pll " "Parameter \"lpm_hint\" = \"CBX_MODULE_PREFIX=pll\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altpll " "Parameter \"lpm_type\" = \"altpll\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode NORMAL " "Parameter \"operation_mode\" = \"NORMAL\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_type AUTO " "Parameter \"pll_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_activeclock PORT_UNUSED " "Parameter \"port_activeclock\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_areset PORT_UNUSED " "Parameter \"port_areset\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad0 PORT_UNUSED " "Parameter \"port_clkbad0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad1 PORT_UNUSED " "Parameter \"port_clkbad1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkloss PORT_UNUSED " "Parameter \"port_clkloss\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkswitch PORT_UNUSED " "Parameter \"port_clkswitch\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_configupdate PORT_UNUSED " "Parameter \"port_configupdate\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_fbin PORT_UNUSED " "Parameter \"port_fbin\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk0 PORT_USED " "Parameter \"port_inclk0\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk1 PORT_UNUSED " "Parameter \"port_inclk1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_locked PORT_USED " "Parameter \"port_locked\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pfdena PORT_UNUSED " "Parameter \"port_pfdena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasecounterselect PORT_UNUSED " "Parameter \"port_phasecounterselect\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasedone PORT_UNUSED " "Parameter \"port_phasedone\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasestep PORT_UNUSED " "Parameter \"port_phasestep\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phaseupdown PORT_UNUSED " "Parameter \"port_phaseupdown\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pllena PORT_UNUSED " "Parameter \"port_pllena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanaclr PORT_UNUSED " "Parameter \"port_scanaclr\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclk PORT_UNUSED " "Parameter \"port_scanclk\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclkena PORT_UNUSED " "Parameter \"port_scanclkena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandata PORT_UNUSED " "Parameter \"port_scandata\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandataout PORT_UNUSED " "Parameter \"port_scandataout\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandone PORT_UNUSED " "Parameter \"port_scandone\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanread PORT_UNUSED " "Parameter \"port_scanread\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanwrite PORT_UNUSED " "Parameter \"port_scanwrite\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk0 PORT_USED " "Parameter \"port_clk0\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk1 PORT_USED " "Parameter \"port_clk1\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk2 PORT_USED " "Parameter \"port_clk2\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk3 PORT_UNUSED " "Parameter \"port_clk3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk4 PORT_UNUSED " "Parameter \"port_clk4\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk5 PORT_UNUSED " "Parameter \"port_clk5\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena0 PORT_UNUSED " "Parameter \"port_clkena0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena1 PORT_UNUSED " "Parameter \"port_clkena1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena2 PORT_UNUSED " "Parameter \"port_clkena2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena3 PORT_UNUSED " "Parameter \"port_clkena3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena4 PORT_UNUSED " "Parameter \"port_clkena4\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena5 PORT_UNUSED " "Parameter \"port_clkena5\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk0 PORT_UNUSED " "Parameter \"port_extclk0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk1 PORT_UNUSED " "Parameter \"port_extclk1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk2 PORT_UNUSED " "Parameter \"port_extclk2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk3 PORT_UNUSED " "Parameter \"port_extclk3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "self_reset_on_loss_lock OFF " "Parameter \"self_reset_on_loss_lock\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_clock 5 " "Parameter \"width_clock\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505744 ""} } { { "pll.v" "" { Text "/home/benny/work/fpga/spectrum/pll.v" 102 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1648828505744 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/pll_altpll.v 1 1 " "Found 1 design units, including 1 entities, in source file db/pll_altpll.v" { { "Info" "ISGN_ENTITY_NAME" "1 pll_altpll " "Found entity 1: pll_altpll" { } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 29 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648828505797 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648828505797 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pll_altpll ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated " "Elaborating entity \"pll_altpll\" for hierarchy \"ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\"" { } { { "altpll.tdf" "auto_generated" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altpll.tdf" 897 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505798 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clocks ula:ula_\|clocks:clocks_ " "Elaborating entity \"clocks\" for hierarchy \"ula:ula_\|clocks:clocks_\"" { } { { "ula/ula.sv" "clocks_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 85 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505800 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "i2c_loader ula:ula_\|i2c_loader:i2c_loader_ " "Elaborating entity \"i2c_loader\" for hierarchy \"ula:ula_\|i2c_loader:i2c_loader_\"" { } { { "ula/ula.sv" "i2c_loader_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 124 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505801 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "i2s_intf ula:ula_\|i2s_intf:i2s_intf_ " "Elaborating entity \"i2s_intf\" for hierarchy \"ula:ula_\|i2s_intf:i2s_intf_\"" { } { { "ula/ula.sv" "i2s_intf_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 144 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505803 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "video ula:ula_\|video:video_ " "Elaborating entity \"video\" for hierarchy \"ula:ula_\|video:video_\"" { } { { "ula/ula.sv" "video_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 158 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505805 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ps2_keyboard ula:ula_\|ps2_keyboard:ps2_keyboard_ " "Elaborating entity \"ps2_keyboard\" for hierarchy \"ula:ula_\|ps2_keyboard:ps2_keyboard_\"" { } { { "ula/ula.sv" "ps2_keyboard_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 167 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505806 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "zx_keyboard ula:ula_\|zx_keyboard:zx_keyboard_ " "Elaborating entity \"zx_keyboard\" for hierarchy \"ula:ula_\|zx_keyboard:zx_keyboard_\"" { } { { "ula/ula.sv" "zx_keyboard_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 170 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505807 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "z80_top_direct_n z80_top_direct_n:z80_ " "Elaborating entity \"z80_top_direct_n\" for hierarchy \"z80_top_direct_n:z80_\"" { } { { "spectrum.sv" "z80_" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 273 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505811 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clk_delay z80_top_direct_n:z80_\|clk_delay:clk_delay_ " "Elaborating entity \"clk_delay\" for hierarchy \"z80_top_direct_n:z80_\|clk_delay:clk_delay_\"" { } { { "cpu/toplevel/coremodules.vh" "clk_delay_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 20 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505814 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_state z80_top_direct_n:z80_\|decode_state:decode_state_ " "Elaborating entity \"decode_state\" for hierarchy \"z80_top_direct_n:z80_\|decode_state:decode_state_\"" { } { { "cpu/toplevel/coremodules.vh" "decode_state_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 46 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505814 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "execute z80_top_direct_n:z80_\|execute:execute_ " "Elaborating entity \"execute\" for hierarchy \"z80_top_direct_n:z80_\|execute:execute_\"" { } { { "cpu/toplevel/coremodules.vh" "execute_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 180 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505815 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "interrupts z80_top_direct_n:z80_\|interrupts:interrupts_ " "Elaborating entity \"interrupts\" for hierarchy \"z80_top_direct_n:z80_\|interrupts:interrupts_\"" { } { { "cpu/toplevel/coremodules.vh" "interrupts_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 199 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505830 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ir z80_top_direct_n:z80_\|ir:ir_ " "Elaborating entity \"ir\" for hierarchy \"z80_top_direct_n:z80_\|ir:ir_\"" { } { { "cpu/toplevel/coremodules.vh" "ir_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 208 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505830 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pin_control z80_top_direct_n:z80_\|pin_control:pin_control_ " "Elaborating entity \"pin_control\" for hierarchy \"z80_top_direct_n:z80_\|pin_control:pin_control_\"" { } { { "cpu/toplevel/coremodules.vh" "pin_control_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 223 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505831 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pla_decode z80_top_direct_n:z80_\|pla_decode:pla_decode_ " "Elaborating entity \"pla_decode\" for hierarchy \"z80_top_direct_n:z80_\|pla_decode:pla_decode_\"" { } { { "cpu/toplevel/coremodules.vh" "pla_decode_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 229 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505832 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "resets z80_top_direct_n:z80_\|resets:resets_ " "Elaborating entity \"resets\" for hierarchy \"z80_top_direct_n:z80_\|resets:resets_\"" { } { { "cpu/toplevel/coremodules.vh" "resets_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 240 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505834 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "memory_ifc z80_top_direct_n:z80_\|memory_ifc:memory_ifc_ " "Elaborating entity \"memory_ifc\" for hierarchy \"z80_top_direct_n:z80_\|memory_ifc:memory_ifc_\"" { } { { "cpu/toplevel/coremodules.vh" "memory_ifc_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 264 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505835 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sequencer z80_top_direct_n:z80_\|sequencer:sequencer_ " "Elaborating entity \"sequencer\" for hierarchy \"z80_top_direct_n:z80_\|sequencer:sequencer_\"" { } { { "cpu/toplevel/coremodules.vh" "sequencer_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 286 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505836 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_control z80_top_direct_n:z80_\|alu_control:alu_control_ " "Elaborating entity \"alu_control\" for hierarchy \"z80_top_direct_n:z80_\|alu_control:alu_control_\"" { } { { "cpu/toplevel/coremodules.vh" "alu_control_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 326 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505836 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_mux_4 z80_top_direct_n:z80_\|alu_control:alu_control_\|alu_mux_4:b2v_inst_cond_mux " "Elaborating entity \"alu_mux_4\" for hierarchy \"z80_top_direct_n:z80_\|alu_control:alu_control_\|alu_mux_4:b2v_inst_cond_mux\"" { } { { "cpu/alu/alu_control.v" "b2v_inst_cond_mux" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 205 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505837 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_mux_8 z80_top_direct_n:z80_\|alu_control:alu_control_\|alu_mux_8:b2v_inst_shift_mux " "Elaborating entity \"alu_mux_8\" for hierarchy \"z80_top_direct_n:z80_\|alu_control:alu_control_\|alu_mux_8:b2v_inst_shift_mux\"" { } { { "cpu/alu/alu_control.v" "b2v_inst_shift_mux" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 227 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505839 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_select z80_top_direct_n:z80_\|alu_select:alu_select_ " "Elaborating entity \"alu_select\" for hierarchy \"z80_top_direct_n:z80_\|alu_select:alu_select_\"" { } { { "cpu/toplevel/coremodules.vh" "alu_select_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 363 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505839 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_flags z80_top_direct_n:z80_\|alu_flags:alu_flags_ " "Elaborating entity \"alu_flags\" for hierarchy \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\"" { } { { "cpu/toplevel/coremodules.vh" "alu_flags_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 405 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505840 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_mux_2 z80_top_direct_n:z80_\|alu_flags:alu_flags_\|alu_mux_2:b2v_inst_mux_cf " "Elaborating entity \"alu_mux_2\" for hierarchy \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|alu_mux_2:b2v_inst_mux_cf\"" { } { { "cpu/alu/alu_flags.v" "b2v_inst_mux_cf" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_flags.v" 344 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505841 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu z80_top_direct_n:z80_\|alu:alu_ " "Elaborating entity \"alu\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\"" { } { { "cpu/toplevel/coremodules.vh" "alu_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 448 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505842 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_core z80_top_direct_n:z80_\|alu:alu_\|alu_core:b2v_core " "Elaborating entity \"alu_core\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_core:b2v_core\"" { } { { "cpu/alu/alu.v" "b2v_core" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 170 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505844 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_slice z80_top_direct_n:z80_\|alu:alu_\|alu_core:b2v_core\|alu_slice:b2v_alu_slice_bit_0 " "Elaborating entity \"alu_slice\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_core:b2v_core\|alu_slice:b2v_alu_slice_bit_0\"" { } { { "cpu/alu/alu_core.v" "b2v_alu_slice_bit_0" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_core.v" 61 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505845 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_bit_select z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select " "Elaborating entity \"alu_bit_select\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\"" { } { { "cpu/alu/alu.v" "b2v_input_bit_select" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 186 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505847 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_shifter_core z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift " "Elaborating entity \"alu_shifter_core\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\"" { } { { "cpu/alu/alu.v" "b2v_input_shift" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 197 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505848 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_mux_2z z80_top_direct_n:z80_\|alu:alu_\|alu_mux_2z:b2v_op1_latch_mux_high " "Elaborating entity \"alu_mux_2z\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_2z:b2v_op1_latch_mux_high\"" { } { { "cpu/alu/alu.v" "b2v_op1_latch_mux_high" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 318 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505848 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_mux_3z z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low " "Elaborating entity \"alu_mux_3z\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\"" { } { { "cpu/alu/alu.v" "b2v_op1_latch_mux_low" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 328 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505849 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_prep_daa z80_top_direct_n:z80_\|alu:alu_\|alu_prep_daa:b2v_prep_daa " "Elaborating entity \"alu_prep_daa\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_prep_daa:b2v_prep_daa\"" { } { { "cpu/alu/alu.v" "b2v_prep_daa" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 364 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505851 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "reg_file z80_top_direct_n:z80_\|reg_file:reg_file_ " "Elaborating entity \"reg_file\" for hierarchy \"z80_top_direct_n:z80_\|reg_file:reg_file_\"" { } { { "cpu/toplevel/coremodules.vh" "reg_file_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 484 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505852 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "reg_latch z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi " "Elaborating entity \"reg_latch\" for hierarchy \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\"" { } { { "cpu/registers/reg_file.v" "b2v_latch_af2_hi" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 279 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505853 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "reg_control z80_top_direct_n:z80_\|reg_control:reg_control_ " "Elaborating entity \"reg_control\" for hierarchy \"z80_top_direct_n:z80_\|reg_control:reg_control_\"" { } { { "cpu/toplevel/coremodules.vh" "reg_control_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 531 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505866 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "address_latch z80_top_direct_n:z80_\|address_latch:address_latch_ " "Elaborating entity \"address_latch\" for hierarchy \"z80_top_direct_n:z80_\|address_latch:address_latch_\"" { } { { "cpu/toplevel/coremodules.vh" "address_latch_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 547 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505867 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "address_mux z80_top_direct_n:z80_\|address_latch:address_latch_\|address_mux:b2v_inst7 " "Elaborating entity \"address_mux\" for hierarchy \"z80_top_direct_n:z80_\|address_latch:address_latch_\|address_mux:b2v_inst7\"" { } { { "cpu/bus/address_latch.v" "b2v_inst7" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_latch.v" 106 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505869 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "inc_dec z80_top_direct_n:z80_\|address_latch:address_latch_\|inc_dec:b2v_inst_inc_dec " "Elaborating entity \"inc_dec\" for hierarchy \"z80_top_direct_n:z80_\|address_latch:address_latch_\|inc_dec:b2v_inst_inc_dec\"" { } { { "cpu/bus/address_latch.v" "b2v_inst_inc_dec" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_latch.v" 116 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505870 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "inc_dec_2bit z80_top_direct_n:z80_\|address_latch:address_latch_\|inc_dec:b2v_inst_inc_dec\|inc_dec_2bit:b2v_dual_adder_0 " "Elaborating entity \"inc_dec_2bit\" for hierarchy \"z80_top_direct_n:z80_\|address_latch:address_latch_\|inc_dec:b2v_inst_inc_dec\|inc_dec_2bit:b2v_dual_adder_0\"" { } { { "cpu/bus/inc_dec.v" "b2v_dual_adder_0" { Text "/home/benny/work/fpga/spectrum/cpu/bus/inc_dec.v" 80 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505871 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bus_control z80_top_direct_n:z80_\|bus_control:bus_control_ " "Elaborating entity \"bus_control\" for hierarchy \"z80_top_direct_n:z80_\|bus_control:bus_control_\"" { } { { "cpu/toplevel/coremodules.vh" "bus_control_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 553 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505875 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bus_switch z80_top_direct_n:z80_\|bus_switch:bus_switch_ " "Elaborating entity \"bus_switch\" for hierarchy \"z80_top_direct_n:z80_\|bus_switch:bus_switch_\"" { } { { "cpu/toplevel/coremodules.vh" "bus_switch_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 566 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505876 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "data_switch z80_top_direct_n:z80_\|data_switch:sw2_ " "Elaborating entity \"data_switch\" for hierarchy \"z80_top_direct_n:z80_\|data_switch:sw2_\"" { } { { "cpu/toplevel/core.vh" "sw2_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/core.vh" 36 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505876 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "data_switch_mask z80_top_direct_n:z80_\|data_switch_mask:sw1_ " "Elaborating entity \"data_switch_mask\" for hierarchy \"z80_top_direct_n:z80_\|data_switch_mask:sw1_\"" { } { { "cpu/toplevel/core.vh" "sw1_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/core.vh" 39 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505877 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "address_pins z80_top_direct_n:z80_\|address_pins:address_pins_ " "Elaborating entity \"address_pins\" for hierarchy \"z80_top_direct_n:z80_\|address_pins:address_pins_\"" { } { { "cpu/toplevel/z80_top_direct_n.v" "address_pins_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 41 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505878 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "data_pins z80_top_direct_n:z80_\|data_pins:data_pins_ " "Elaborating entity \"data_pins\" for hierarchy \"z80_top_direct_n:z80_\|data_pins:data_pins_\"" { } { { "cpu/toplevel/z80_top_direct_n.v" "data_pins_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 51 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505879 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "control_pins_n z80_top_direct_n:z80_\|control_pins_n:control_pins_ " "Elaborating entity \"control_pins_n\" for hierarchy \"z80_top_direct_n:z80_\|control_pins_n:control_pins_\"" { } { { "cpu/toplevel/z80_top_direct_n.v" "control_pins_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 83 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648828505880 ""} -{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "2 " "2 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Quartus II" 0 -1 1648828510554 ""} -{ "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR_HDR" "" "Tri-state node(s) do not directly drive top-level pin(s)" { { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[0\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[0\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510655 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[1\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[1\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510655 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[2\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[2\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510655 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[3\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[3\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510655 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[4\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[4\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510655 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[5\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[5\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510655 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[6\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[6\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510655 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[7\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[7\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510655 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[8\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[8\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510655 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[9\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[9\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510655 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[10\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[10\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510655 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[11\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[11\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510655 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[12\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[12\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510655 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[13\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|address_reg_a\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[13\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|address_reg_a\[0\]\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510655 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[14\] ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|address_reg_a\[1\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[14\]\" to the node \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|address_reg_a\[1\]\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510655 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[15\] ExtRamWE " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[15\]\" to the node \"ExtRamWE\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510655 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|control_pins_n:control_pins_\|pin_nWR RamWE " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|control_pins_n:control_pins_\|pin_nWR\" to the node \"RamWE\" into an OR gate" { } { { "cpu/bus/control_pins_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/control_pins_n.v" 77 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510655 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|control_pins_n:control_pins_\|pin_nRD Equal2 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|control_pins_n:control_pins_\|pin_nRD\" to the node \"Equal2\" into an OR gate" { } { { "cpu/bus/control_pins_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/control_pins_n.v" 76 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510655 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|control_pins_n:control_pins_\|pin_nIORQ Equal2 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|control_pins_n:control_pins_\|pin_nIORQ\" to the node \"Equal2\" into an OR gate" { } { { "cpu/bus/control_pins_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/control_pins_n.v" 75 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510655 ""} } { } 0 13046 "Tri-state node(s) do not directly drive top-level pin(s)" 0 0 "Quartus II" 0 -1 1648828510655 ""} -{ "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR_HDR" "" "Tri-state node(s) do not directly drive top-level pin(s)" { { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[0\] z80_top_direct_n:z80_\|ir:ir_\|opcode\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[0\]\" to the node \"z80_top_direct_n:z80_\|ir:ir_\|opcode\[0\]\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[7\] z80_top_direct_n:z80_\|ir:ir_\|opcode\[7\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[7\]\" to the node \"z80_top_direct_n:z80_\|ir:ir_\|opcode\[7\]\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[6\] z80_top_direct_n:z80_\|ir:ir_\|opcode\[6\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[6\]\" to the node \"z80_top_direct_n:z80_\|ir:ir_\|opcode\[6\]\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[5\] z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\|bs_out_high\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[5\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\|bs_out_high\[0\]\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[4\] z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[4\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[3\] z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[3\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[2\] z80_top_direct_n:z80_\|ir:ir_\|opcode\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[2\]\" to the node \"z80_top_direct_n:z80_\|ir:ir_\|opcode\[2\]\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[1\] z80_top_direct_n:z80_\|ir:ir_\|opcode\[1\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[1\]\" to the node \"z80_top_direct_n:z80_\|ir:ir_\|opcode\[1\]\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_high\[3\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_1 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_high\[3\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_1\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 106 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_high\[2\] z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_2\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_high\[2\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_2\[2\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 106 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_high\[1\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_13 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_high\[1\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_13\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 106 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_high\[0\] z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_2\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_high\[0\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_2\[0\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 106 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_low\[3\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_17 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_low\[3\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_17\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 107 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_low\[2\] z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_3\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_low\[2\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_3\[2\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 107 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_low\[1\] z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_3\[1\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_low\[1\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_3\[1\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 107 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_low\[0\] z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_3\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_low\[0\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_3\[0\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 107 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[0\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[0\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[0\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[1\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[1\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[1\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[1\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[2\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[2\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[2\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[3\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[3\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[3\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[3\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[4\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[4\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[4\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[4\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[5\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[5\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[5\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[5\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[6\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[6\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[6\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[6\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[7\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[7\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[7\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[7\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[0\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[8\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[0\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[8\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[1\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[9\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[1\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[9\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[2\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[10\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[2\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[10\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[3\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[11\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[3\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[11\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[4\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[12\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[4\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[12\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[5\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[13\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[5\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[13\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[6\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[14\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[6\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[14\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[7\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[15\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[7\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[15\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[6\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_12 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[6\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_12\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[7\] z80_top_direct_n:z80_\|alu_control:alu_control_\|alu_mux_8:b2v_inst_shift_mux\|out " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[7\]\" to the node \"z80_top_direct_n:z80_\|alu_control:alu_control_\|alu_mux_8:b2v_inst_shift_mux\|out\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[0\] z80_top_direct_n:z80_\|alu_control:alu_control_\|shift_cf_out " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[0\]\" to the node \"z80_top_direct_n:z80_\|alu_control:alu_control_\|shift_cf_out\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[0\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_22 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[0\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_22\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[7\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_10 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[7\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_10\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[5\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_14 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[5\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_14\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[4\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_16 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[4\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_16\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[3\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_18 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[3\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_18\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[2\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_20 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[2\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_20\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[1\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_2 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[1\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_2\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[6\] z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[3\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[6\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[3\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[5\] z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[5\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[2\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[4\] z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[1\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[4\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[1\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[3\] z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[3\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[0\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[2\] z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_low\[3\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[2\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_low\[3\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[1\] z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_low\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[1\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_low\[2\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[0\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[0\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[0\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[1\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[1\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[1\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[1\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[2\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[2\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[2\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[3\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[3\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[3\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[3\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[4\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[4\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[4\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[4\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[5\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[5\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[5\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[5\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[6\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[6\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[6\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[6\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[7\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[7\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[7\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[7\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[0\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[0\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[0\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[1\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[1\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[1\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[1\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[2\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[2\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[2\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[3\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[3\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[3\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[3\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[4\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[4\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[4\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[4\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[5\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[5\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[5\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[5\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[6\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[6\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[6\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[6\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[7\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[7\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[7\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[7\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[0\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"D\[0\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a0\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 76 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[1\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a1 " "Converted the fan-out from the tri-state buffer \"D\[1\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a1\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 76 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[2\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a2 " "Converted the fan-out from the tri-state buffer \"D\[2\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a2\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 76 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[3\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a3 " "Converted the fan-out from the tri-state buffer \"D\[3\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a3\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 76 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[4\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a4 " "Converted the fan-out from the tri-state buffer \"D\[4\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a4\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 76 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[5\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a5 " "Converted the fan-out from the tri-state buffer \"D\[5\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a5\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 76 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[6\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a6 " "Converted the fan-out from the tri-state buffer \"D\[6\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a6\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 76 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[7\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a7 " "Converted the fan-out from the tri-state buffer \"D\[7\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a7\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 76 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648828510661 ""} } { } 0 13046 "Tri-state node(s) do not directly drive top-level pin(s)" 0 0 "Quartus II" 0 -1 1648828510661 ""} -{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" { } { { "cpu/control/resets.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/resets.v" 52 -1 0 } } { "cpu/control/sequencer.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/sequencer.v" 127 -1 0 } } { "cpu/control/sequencer.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/sequencer.v" 201 -1 0 } } { "cpu/control/resets.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/resets.v" 42 -1 0 } } { "ula/zx_kbd.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/zx_kbd.sv" 93 -1 0 } } { "cpu/control/memory_ifc.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/memory_ifc.v" 97 -1 0 } } { "ula/i2c_loader.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2c_loader.vhd" 108 -1 0 } } { "ula/i2c_loader.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2c_loader.vhd" 109 -1 0 } } { "ula/ps2_kbd.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/ps2_kbd.sv" 33 -1 0 } } { "ula/ps2_kbd.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/ps2_kbd.sv" 59 -1 0 } } } 0 13000 "Registers with preset signals will power-up high" 0 0 "Quartus II" 0 -1 1648828510688 ""} -{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" { } { } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "Quartus II" 0 -1 1648828510688 ""} -{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "LED\[1\] GND " "Pin \"LED\[1\]\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648828513991 "|spectrum|LED[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LED\[4\] GND " "Pin \"LED\[4\]\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648828513991 "|spectrum|LED[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LED\[5\] GND " "Pin \"LED\[5\]\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648828513991 "|spectrum|LED[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LED\[6\] GND " "Pin \"LED\[6\]\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648828513991 "|spectrum|LED[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LED\[7\] GND " "Pin \"LED\[7\]\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648828513991 "|spectrum|LED[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "GPIO_1\[24\] VCC " "Pin \"GPIO_1\[24\]\" is stuck at VCC" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648828513991 "|spectrum|GPIO_1[24]"} { "Warning" "WMLS_MLS_STUCK_PIN" "GPIO_1\[32\] GND " "Pin \"GPIO_1\[32\]\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648828513991 "|spectrum|GPIO_1[32]"} { "Warning" "WMLS_MLS_STUCK_PIN" "GPIO_1\[33\] GND " "Pin \"GPIO_1\[33\]\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648828513991 "|spectrum|GPIO_1[33]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1648828513991 ""} -{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1648828514385 ""} -{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "2 " "2 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1648828517029 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/benny/work/fpga/spectrum/output_files/spectrum.map.smsg " "Generated suppressed messages file /home/benny/work/fpga/spectrum/output_files/spectrum.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1648828517124 ""} -{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "1 0 1 0 0 " "Adding 1 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1648828517378 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828517378 ""} -{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "2 " "Design contains 2 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[0\] " "No output dependent on input pin \"SW\[0\]\"" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 19 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828517630 "|spectrum|SW[0]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[3\] " "No output dependent on input pin \"SW\[3\]\"" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 19 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828517630 "|spectrum|SW[3]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Quartus II" 0 -1 1648828517630 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "2747 " "Implemented 2747 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "11 " "Implemented 11 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1648828517630 ""} { "Info" "ICUT_CUT_TM_OPINS" "62 " "Implemented 62 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1648828517630 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "2 " "Implemented 2 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1648828517630 ""} { "Info" "ICUT_CUT_TM_LCELLS" "2607 " "Implemented 2607 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1648828517630 ""} { "Info" "ICUT_CUT_TM_RAMS" "64 " "Implemented 64 RAM segments" { } { } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Quartus II" 0 -1 1648828517630 ""} { "Info" "ICUT_CUT_TM_PLLS" "1 " "Implemented 1 PLLs" { } { } 0 21065 "Implemented %1!d! PLLs" 0 0 "Quartus II" 0 -1 1648828517630 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1648828517630 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 110 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 110 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "441 " "Peak virtual memory: 441 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648828517650 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 1 18:55:17 2022 " "Processing ended: Fri Apr 1 18:55:17 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648828517650 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:13 " "Elapsed time: 00:00:13" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648828517650 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:13 " "Total CPU time (on all processors): 00:00:13" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648828517650 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648828517650 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648903978171 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648903978172 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Apr 2 15:52:58 2022 " "Processing started: Sat Apr 2 15:52:58 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648903978172 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648903978172 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum " "Command: quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648903978172 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1648903978349 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "spectrum.sv 1 1 " "Found 1 design units, including 1 entities, in source file spectrum.sv" { { "Info" "ISGN_ENTITY_NAME" "1 spectrum " "Found entity 1: spectrum" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903978416 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903978416 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rom0.v 1 1 " "Found 1 design units, including 1 entities, in source file rom0.v" { { "Info" "ISGN_ENTITY_NAME" "1 rom0 " "Found entity 1: rom0" { } { { "rom0.v" "" { Text "/home/benny/work/fpga/spectrum/rom0.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903978417 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903978417 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram16.v 1 1 " "Found 1 design units, including 1 entities, in source file ram16.v" { { "Info" "ISGN_ENTITY_NAME" "1 ram16 " "Found entity 1: ram16" { } { { "ram16.v" "" { Text "/home/benny/work/fpga/spectrum/ram16.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903978418 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903978418 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram32.v 1 1 " "Found 1 design units, including 1 entities, in source file ram32.v" { { "Info" "ISGN_ENTITY_NAME" "1 ram32 " "Found entity 1: ram32" { } { { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903978419 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903978419 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pll.v 1 1 " "Found 1 design units, including 1 entities, in source file pll.v" { { "Info" "ISGN_ENTITY_NAME" "1 pll " "Found entity 1: pll" { } { { "pll.v" "" { Text "/home/benny/work/fpga/spectrum/pll.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903978420 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903978420 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu " "Found entity 1: alu" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903978422 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903978422 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_bit_select.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_bit_select.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_bit_select " "Found entity 1: alu_bit_select" { } { { "cpu/alu/alu_bit_select.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_bit_select.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903978422 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903978422 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_control.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_control " "Found entity 1: alu_control" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903978423 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903978423 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_core.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_core.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_core " "Found entity 1: alu_core" { } { { "cpu/alu/alu_core.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_core.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903978424 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903978424 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_flags.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_flags.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_flags " "Found entity 1: alu_flags" { } { { "cpu/alu/alu_flags.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_flags.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903978425 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903978425 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_2.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_2.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_2 " "Found entity 1: alu_mux_2" { } { { "cpu/alu/alu_mux_2.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_2.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903978426 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903978426 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_2z.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_2z.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_2z " "Found entity 1: alu_mux_2z" { } { { "cpu/alu/alu_mux_2z.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_2z.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903978426 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903978426 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_3z.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_3z.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_3z " "Found entity 1: alu_mux_3z" { } { { "cpu/alu/alu_mux_3z.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_3z.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903978427 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903978427 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_4.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_4.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_4 " "Found entity 1: alu_mux_4" { } { { "cpu/alu/alu_mux_4.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_4.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903978428 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903978428 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_mux_8.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_mux_8.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_mux_8 " "Found entity 1: alu_mux_8" { } { { "cpu/alu/alu_mux_8.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_8.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903978429 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903978429 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_prep_daa.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_prep_daa.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_prep_daa " "Found entity 1: alu_prep_daa" { } { { "cpu/alu/alu_prep_daa.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_prep_daa.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903978429 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903978429 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_select.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_select.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_select " "Found entity 1: alu_select" { } { { "cpu/alu/alu_select.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_select.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903978430 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903978430 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_shifter_core.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_shifter_core.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_shifter_core " "Found entity 1: alu_shifter_core" { } { { "cpu/alu/alu_shifter_core.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_shifter_core.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903978431 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903978431 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/alu/alu_slice.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/alu/alu_slice.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_slice " "Found entity 1: alu_slice" { } { { "cpu/alu/alu_slice.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_slice.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903978432 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903978432 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/clk_delay.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/clk_delay.v" { { "Info" "ISGN_ENTITY_NAME" "1 clk_delay " "Found entity 1: clk_delay" { } { { "cpu/control/clk_delay.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/clk_delay.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903978432 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903978432 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/decode_state.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/decode_state.v" { { "Info" "ISGN_ENTITY_NAME" "1 decode_state " "Found entity 1: decode_state" { } { { "cpu/control/decode_state.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/decode_state.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903978433 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903978433 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/execute.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/execute.v" { { "Info" "ISGN_ENTITY_NAME" "1 execute " "Found entity 1: execute" { } { { "cpu/control/execute.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/execute.v" 25 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903978457 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903978457 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/interrupts.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/interrupts.v" { { "Info" "ISGN_ENTITY_NAME" "1 interrupts " "Found entity 1: interrupts" { } { { "cpu/control/interrupts.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/interrupts.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903978458 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903978458 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/ir.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/ir.v" { { "Info" "ISGN_ENTITY_NAME" "1 ir " "Found entity 1: ir" { } { { "cpu/control/ir.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/ir.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903978459 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903978459 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/memory_ifc.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/memory_ifc.v" { { "Info" "ISGN_ENTITY_NAME" "1 memory_ifc " "Found entity 1: memory_ifc" { } { { "cpu/control/memory_ifc.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/memory_ifc.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903978460 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903978460 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/pin_control.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/pin_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 pin_control " "Found entity 1: pin_control" { } { { "cpu/control/pin_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/pin_control.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903978461 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903978461 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/pla_decode.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/pla_decode.v" { { "Info" "ISGN_ENTITY_NAME" "1 pla_decode " "Found entity 1: pla_decode" { } { { "cpu/control/pla_decode.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/pla_decode.v" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903978463 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903978463 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/resets.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/resets.v" { { "Info" "ISGN_ENTITY_NAME" "1 resets " "Found entity 1: resets" { } { { "cpu/control/resets.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/resets.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903978463 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903978463 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/control/sequencer.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/control/sequencer.v" { { "Info" "ISGN_ENTITY_NAME" "1 sequencer " "Found entity 1: sequencer" { } { { "cpu/control/sequencer.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/sequencer.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903978464 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903978464 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/address_latch.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/address_latch.v" { { "Info" "ISGN_ENTITY_NAME" "1 address_latch " "Found entity 1: address_latch" { } { { "cpu/bus/address_latch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_latch.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903978465 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903978465 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/address_mux.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/address_mux.v" { { "Info" "ISGN_ENTITY_NAME" "1 address_mux " "Found entity 1: address_mux" { } { { "cpu/bus/address_mux.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_mux.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903978466 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903978466 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/address_pins.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/address_pins.v" { { "Info" "ISGN_ENTITY_NAME" "1 address_pins " "Found entity 1: address_pins" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903978467 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903978467 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/bus_control.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/bus_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 bus_control " "Found entity 1: bus_control" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903978467 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903978467 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/bus_switch.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/bus_switch.v" { { "Info" "ISGN_ENTITY_NAME" "1 bus_switch " "Found entity 1: bus_switch" { } { { "cpu/bus/bus_switch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_switch.v" 12 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903978468 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903978468 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/control_pins_n.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/control_pins_n.v" { { "Info" "ISGN_ENTITY_NAME" "1 control_pins_n " "Found entity 1: control_pins_n" { } { { "cpu/bus/control_pins_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/control_pins_n.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903978469 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903978469 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/data_pins.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/data_pins.v" { { "Info" "ISGN_ENTITY_NAME" "1 data_pins " "Found entity 1: data_pins" { } { { "cpu/bus/data_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_pins.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903978470 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903978470 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/data_switch.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/data_switch.v" { { "Info" "ISGN_ENTITY_NAME" "1 data_switch " "Found entity 1: data_switch" { } { { "cpu/bus/data_switch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903978470 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903978470 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/data_switch_mask.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/data_switch_mask.v" { { "Info" "ISGN_ENTITY_NAME" "1 data_switch_mask " "Found entity 1: data_switch_mask" { } { { "cpu/bus/data_switch_mask.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch_mask.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903978471 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903978471 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/inc_dec.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/inc_dec.v" { { "Info" "ISGN_ENTITY_NAME" "1 inc_dec " "Found entity 1: inc_dec" { } { { "cpu/bus/inc_dec.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/inc_dec.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903978472 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903978472 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/bus/inc_dec_2bit.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/bus/inc_dec_2bit.v" { { "Info" "ISGN_ENTITY_NAME" "1 inc_dec_2bit " "Found entity 1: inc_dec_2bit" { } { { "cpu/bus/inc_dec_2bit.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/inc_dec_2bit.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903978473 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903978473 ""} +{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "nRESET nreset z80_top_direct_n.v(19) " "Verilog HDL Declaration information at z80_top_direct_n.v(19): object \"nRESET\" differs only in case from object \"nreset\" in the same scope" { } { { "cpu/toplevel/z80_top_direct_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 19 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1648903978475 ""} +{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CLK clk z80_top_direct_n.v(22) " "Verilog HDL Declaration information at z80_top_direct_n.v(22): object \"CLK\" differs only in case from object \"clk\" in the same scope" { } { { "cpu/toplevel/z80_top_direct_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1648903978475 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/toplevel/z80_top_direct_n.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/toplevel/z80_top_direct_n.v" { { "Info" "ISGN_ENTITY_NAME" "1 z80_top_direct_n " "Found entity 1: z80_top_direct_n" { } { { "cpu/toplevel/z80_top_direct_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 6 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903978475 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903978475 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/registers/reg_control.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/registers/reg_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 reg_control " "Found entity 1: reg_control" { } { { "cpu/registers/reg_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_control.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903978476 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903978476 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/registers/reg_file.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/registers/reg_file.v" { { "Info" "ISGN_ENTITY_NAME" "1 reg_file " "Found entity 1: reg_file" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903978478 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903978478 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu/registers/reg_latch.v 1 1 " "Found 1 design units, including 1 entities, in source file cpu/registers/reg_latch.v" { { "Info" "ISGN_ENTITY_NAME" "1 reg_latch " "Found entity 1: reg_latch" { } { { "cpu/registers/reg_latch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_latch.v" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903978479 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903978479 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/clocks.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/clocks.sv" { { "Info" "ISGN_ENTITY_NAME" "1 clocks " "Found entity 1: clocks" { } { { "ula/clocks.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/clocks.sv" 26 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903978479 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903978479 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/zx_kbd.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/zx_kbd.sv" { { "Info" "ISGN_ENTITY_NAME" "1 zx_keyboard " "Found entity 1: zx_keyboard" { } { { "ula/zx_kbd.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/zx_kbd.sv" 38 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903978480 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903978480 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/video.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/video.sv" { { "Info" "ISGN_ENTITY_NAME" "1 video " "Found entity 1: video" { } { { "ula/video.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/video.sv" 26 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903978481 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903978481 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/ula.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/ula.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ula " "Found entity 1: ula" { } { { "ula/ula.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 20 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903978482 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903978482 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/ps2_kbd.sv 1 1 " "Found 1 design units, including 1 entities, in source file ula/ps2_kbd.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ps2_keyboard " "Found entity 1: ps2_keyboard" { } { { "ula/ps2_kbd.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/ps2_kbd.sv" 20 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903978483 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903978483 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/i2c_loader.vhd 2 1 " "Found 2 design units, including 1 entities, in source file ula/i2c_loader.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 i2c_loader-i2c_loader_arch " "Found design unit 1: i2c_loader-i2c_loader_arch" { } { { "ula/i2c_loader.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2c_loader.vhd" 64 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903978773 ""} { "Info" "ISGN_ENTITY_NAME" "1 i2c_loader " "Found entity 1: i2c_loader" { } { { "ula/i2c_loader.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2c_loader.vhd" 41 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903978773 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903978773 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ula/i2s_intf.vhd 2 1 " "Found 2 design units, including 1 entities, in source file ula/i2s_intf.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 i2s_intf-i2s_intf_arch " "Found design unit 1: i2s_intf-i2s_intf_arch" { } { { "ula/i2s_intf.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2s_intf.vhd" 82 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903978773 ""} { "Info" "ISGN_ENTITY_NAME" "1 i2s_intf " "Found entity 1: i2s_intf" { } { { "ula/i2s_intf.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2s_intf.vhd" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903978773 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903978773 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rom_scr.v 1 1 " "Found 1 design units, including 1 entities, in source file rom_scr.v" { { "Info" "ISGN_ENTITY_NAME" "1 rom_scr " "Found entity 1: rom_scr" { } { { "rom_scr.v" "" { Text "/home/benny/work/fpga/spectrum/rom_scr.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903978776 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903978776 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pll_video.v 1 1 " "Found 1 design units, including 1 entities, in source file pll_video.v" { { "Info" "ISGN_ENTITY_NAME" "1 pll_video " "Found entity 1: pll_video" { } { { "pll_video.v" "" { Text "/home/benny/work/fpga/spectrum/pll_video.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903978777 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903978777 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram_video.v 1 1 " "Found 1 design units, including 1 entities, in source file ram_video.v" { { "Info" "ISGN_ENTITY_NAME" "1 ram_video " "Found entity 1: ram_video" { } { { "ram_video.v" "" { Text "/home/benny/work/fpga/spectrum/ram_video.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903978778 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903978778 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "spectrum " "Elaborating entity \"spectrum\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1648903978931 ""} +{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LED\[7..4\] spectrum.sv(1) " "Output port \"LED\[7..4\]\" at spectrum.sv(1) has no driver" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1648903978936 "|spectrum"} +{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LED\[1\] spectrum.sv(1) " "Output port \"LED\[1\]\" at spectrum.sv(1) has no driver" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1648903978936 "|spectrum"} +{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "GPIO_1\[33..32\] spectrum.sv(20) " "Output port \"GPIO_1\[33..32\]\" at spectrum.sv(20) has no driver" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1648903978936 "|spectrum"} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rom0 rom0:rom " "Elaborating entity \"rom0\" for hierarchy \"rom0:rom\"" { } { { "spectrum.sv" "rom" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 134 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903978947 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram rom0:rom\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\"" { } { { "rom0.v" "altsyncram_component" { Text "/home/benny/work/fpga/spectrum/rom0.v" 81 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903978994 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "rom0:rom\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"rom0:rom\|altsyncram:altsyncram_component\"" { } { { "rom0.v" "" { Text "/home/benny/work/fpga/spectrum/rom0.v" 81 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903978995 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "rom0:rom\|altsyncram:altsyncram_component " "Instantiated megafunction \"rom0:rom\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a NONE " "Parameter \"address_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903978996 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a BYPASS " "Parameter \"clock_enable_input_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903978996 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_a BYPASS " "Parameter \"clock_enable_output_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903978996 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file ./rom/gw03.hex " "Parameter \"init_file\" = \"./rom/gw03.hex\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903978996 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903978996 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ENABLE_RUNTIME_MOD=NO " "Parameter \"lpm_hint\" = \"ENABLE_RUNTIME_MOD=NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903978996 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903978996 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 16384 " "Parameter \"numwords_a\" = \"16384\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903978996 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode ROM " "Parameter \"operation_mode\" = \"ROM\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903978996 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903978996 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Parameter \"outdata_reg_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903978996 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 14 " "Parameter \"widthad_a\" = \"14\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903978996 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 8 " "Parameter \"width_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903978996 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903978996 ""} } { { "rom0.v" "" { Text "/home/benny/work/fpga/spectrum/rom0.v" 81 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1648903978996 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_qh91.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_qh91.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_qh91 " "Found entity 1: altsyncram_qh91" { } { { "db/altsyncram_qh91.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_qh91.tdf" 31 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903979042 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903979042 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_qh91 rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated " "Elaborating entity \"altsyncram_qh91\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979043 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_c8a.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_c8a.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_c8a " "Found entity 1: decode_c8a" { } { { "db/decode_c8a.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/decode_c8a.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903979083 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903979083 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_c8a rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|decode_c8a:rden_decode " "Elaborating entity \"decode_c8a\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|decode_c8a:rden_decode\"" { } { { "db/altsyncram_qh91.tdf" "rden_decode" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_qh91.tdf" 40 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979084 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_3nb.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mux_3nb.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_3nb " "Found entity 1: mux_3nb" { } { { "db/mux_3nb.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/mux_3nb.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903979124 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903979124 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux_3nb rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|mux_3nb:mux2 " "Elaborating entity \"mux_3nb\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|mux_3nb:mux2\"" { } { { "db/altsyncram_qh91.tdf" "mux2" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_qh91.tdf" 41 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979125 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ram16 ram16:ram0 " "Elaborating entity \"ram16\" for hierarchy \"ram16:ram0\"" { } { { "spectrum.sv" "ram0" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 156 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979128 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram ram16:ram0\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"ram16:ram0\|altsyncram:altsyncram_component\"" { } { { "ram16.v" "altsyncram_component" { Text "/home/benny/work/fpga/spectrum/ram16.v" 97 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979132 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "ram16:ram0\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"ram16:ram0\|altsyncram:altsyncram_component\"" { } { { "ram16.v" "" { Text "/home/benny/work/fpga/spectrum/ram16.v" 97 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903979134 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ram16:ram0\|altsyncram:altsyncram_component " "Instantiated megafunction \"ram16:ram0\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979134 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a BYPASS " "Parameter \"clock_enable_input_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979134 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_b BYPASS " "Parameter \"clock_enable_input_b\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979134 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_a BYPASS " "Parameter \"clock_enable_output_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979134 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_b BYPASS " "Parameter \"clock_enable_output_b\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979134 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_reg_b CLOCK0 " "Parameter \"indata_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979134 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file ula/test_scr.hex " "Parameter \"init_file\" = \"ula/test_scr.hex\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979134 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979134 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979134 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 16384 " "Parameter \"numwords_a\" = \"16384\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979134 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 16384 " "Parameter \"numwords_b\" = \"16384\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979134 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode BIDIR_DUAL_PORT " "Parameter \"operation_mode\" = \"BIDIR_DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979134 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979134 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_b NONE " "Parameter \"outdata_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979134 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Parameter \"outdata_reg_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979134 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b CLOCK0 " "Parameter \"outdata_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979134 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "power_up_uninitialized FALSE " "Parameter \"power_up_uninitialized\" = \"FALSE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979134 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979134 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_port_a NEW_DATA_NO_NBE_READ " "Parameter \"read_during_write_mode_port_a\" = \"NEW_DATA_NO_NBE_READ\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979134 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_port_b NEW_DATA_NO_NBE_READ " "Parameter \"read_during_write_mode_port_b\" = \"NEW_DATA_NO_NBE_READ\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979134 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 14 " "Parameter \"widthad_a\" = \"14\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979134 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 14 " "Parameter \"widthad_b\" = \"14\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979134 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 8 " "Parameter \"width_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979134 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 8 " "Parameter \"width_b\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979134 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979134 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_b 1 " "Parameter \"width_byteena_b\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979134 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_wraddress_reg_b CLOCK0 " "Parameter \"wrcontrol_wraddress_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979134 ""} } { { "ram16.v" "" { Text "/home/benny/work/fpga/spectrum/ram16.v" 97 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1648903979134 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_7ti2.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_7ti2.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_7ti2 " "Found entity 1: altsyncram_7ti2" { } { { "db/altsyncram_7ti2.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_7ti2.tdf" 33 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903979181 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903979181 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_7ti2 ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated " "Elaborating entity \"altsyncram_7ti2\" for hierarchy \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979181 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_jsa.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_jsa.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_jsa " "Found entity 1: decode_jsa" { } { { "db/decode_jsa.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/decode_jsa.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903979222 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903979222 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_jsa ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|decode_jsa:decode2 " "Elaborating entity \"decode_jsa\" for hierarchy \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|decode_jsa:decode2\"" { } { { "db/altsyncram_7ti2.tdf" "decode2" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_7ti2.tdf" 50 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979222 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ram32 ram32:ram1 " "Elaborating entity \"ram32\" for hierarchy \"ram32:ram1\"" { } { { "spectrum.sv" "ram1" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 169 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979228 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram ram32:ram1\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"ram32:ram1\|altsyncram:altsyncram_component\"" { } { { "ram32.v" "altsyncram_component" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979232 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "ram32:ram1\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"ram32:ram1\|altsyncram:altsyncram_component\"" { } { { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903979233 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ram32:ram1\|altsyncram:altsyncram_component " "Instantiated megafunction \"ram32:ram1\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a BYPASS " "Parameter \"clock_enable_input_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979233 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_a BYPASS " "Parameter \"clock_enable_output_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979233 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file led_patterns.mif " "Parameter \"init_file\" = \"led_patterns.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979233 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979233 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ENABLE_RUNTIME_MOD=NO " "Parameter \"lpm_hint\" = \"ENABLE_RUNTIME_MOD=NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979233 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979233 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 32768 " "Parameter \"numwords_a\" = \"32768\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979233 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode SINGLE_PORT " "Parameter \"operation_mode\" = \"SINGLE_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979233 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979233 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Parameter \"outdata_reg_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979233 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "power_up_uninitialized FALSE " "Parameter \"power_up_uninitialized\" = \"FALSE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979233 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_port_a NEW_DATA_NO_NBE_READ " "Parameter \"read_during_write_mode_port_a\" = \"NEW_DATA_NO_NBE_READ\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979233 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 15 " "Parameter \"widthad_a\" = \"15\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979233 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 8 " "Parameter \"width_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979233 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979233 ""} } { { "ram32.v" "" { Text "/home/benny/work/fpga/spectrum/ram32.v" 85 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1648903979233 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_g9i1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_g9i1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_g9i1 " "Found entity 1: altsyncram_g9i1" { } { { "db/altsyncram_g9i1.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 33 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903979281 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903979281 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_g9i1 ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated " "Elaborating entity \"altsyncram_g9i1\" for hierarchy \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979282 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_msa.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_msa.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_msa " "Found entity 1: decode_msa" { } { { "db/decode_msa.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/decode_msa.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903979323 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903979323 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_msa ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|decode_msa:decode3 " "Elaborating entity \"decode_msa\" for hierarchy \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|decode_msa:decode3\"" { } { { "db/altsyncram_g9i1.tdf" "decode3" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 44 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979323 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_f8a.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_f8a.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_f8a " "Found entity 1: decode_f8a" { } { { "db/decode_f8a.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/decode_f8a.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903979363 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903979363 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_f8a ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|decode_f8a:rden_decode " "Elaborating entity \"decode_f8a\" for hierarchy \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|decode_f8a:rden_decode\"" { } { { "db/altsyncram_g9i1.tdf" "rden_decode" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 45 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979364 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_6nb.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mux_6nb.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_6nb " "Found entity 1: mux_6nb" { } { { "db/mux_6nb.tdf" "" { Text "/home/benny/work/fpga/spectrum/db/mux_6nb.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903979405 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903979405 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux_6nb ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|mux_6nb:mux2 " "Elaborating entity \"mux_6nb\" for hierarchy \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|mux_6nb:mux2\"" { } { { "db/altsyncram_g9i1.tdf" "mux2" { Text "/home/benny/work/fpga/spectrum/db/altsyncram_g9i1.tdf" 46 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979405 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ula ula:ula_ " "Elaborating entity \"ula\" for hierarchy \"ula:ula_\"" { } { { "spectrum.sv" "ula_" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 228 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979407 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pll ula:ula_\|pll:pll_ " "Elaborating entity \"pll\" for hierarchy \"ula:ula_\|pll:pll_\"" { } { { "ula/ula.sv" "pll_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 83 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979409 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll ula:ula_\|pll:pll_\|altpll:altpll_component " "Elaborating entity \"altpll\" for hierarchy \"ula:ula_\|pll:pll_\|altpll:altpll_component\"" { } { { "pll.v" "altpll_component" { Text "/home/benny/work/fpga/spectrum/pll.v" 102 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979436 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "ula:ula_\|pll:pll_\|altpll:altpll_component " "Elaborated megafunction instantiation \"ula:ula_\|pll:pll_\|altpll:altpll_component\"" { } { { "pll.v" "" { Text "/home/benny/work/fpga/spectrum/pll.v" 102 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903979439 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ula:ula_\|pll:pll_\|altpll:altpll_component " "Instantiated megafunction \"ula:ula_\|pll:pll_\|altpll:altpll_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "bandwidth_type AUTO " "Parameter \"bandwidth_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979440 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_divide_by 2000 " "Parameter \"clk0_divide_by\" = \"2000\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979440 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_duty_cycle 50 " "Parameter \"clk0_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979440 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_multiply_by 1007 " "Parameter \"clk0_multiply_by\" = \"1007\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979440 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_phase_shift 0 " "Parameter \"clk0_phase_shift\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979440 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_divide_by 25 " "Parameter \"clk1_divide_by\" = \"25\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979440 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_duty_cycle 50 " "Parameter \"clk1_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979440 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_multiply_by 7 " "Parameter \"clk1_multiply_by\" = \"7\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979440 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_phase_shift 0 " "Parameter \"clk1_phase_shift\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979440 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_divide_by 25 " "Parameter \"clk2_divide_by\" = \"25\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979440 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_duty_cycle 50 " "Parameter \"clk2_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979440 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_multiply_by 12 " "Parameter \"clk2_multiply_by\" = \"12\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979440 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_phase_shift 0 " "Parameter \"clk2_phase_shift\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979440 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "compensate_clock CLK0 " "Parameter \"compensate_clock\" = \"CLK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979440 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "inclk0_input_frequency 20000 " "Parameter \"inclk0_input_frequency\" = \"20000\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979440 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979440 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint CBX_MODULE_PREFIX=pll " "Parameter \"lpm_hint\" = \"CBX_MODULE_PREFIX=pll\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979440 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altpll " "Parameter \"lpm_type\" = \"altpll\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979440 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode NORMAL " "Parameter \"operation_mode\" = \"NORMAL\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979440 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_type AUTO " "Parameter \"pll_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979440 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_activeclock PORT_UNUSED " "Parameter \"port_activeclock\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979440 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_areset PORT_UNUSED " "Parameter \"port_areset\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979440 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad0 PORT_UNUSED " "Parameter \"port_clkbad0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979440 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad1 PORT_UNUSED " "Parameter \"port_clkbad1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979440 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkloss PORT_UNUSED " "Parameter \"port_clkloss\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979440 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkswitch PORT_UNUSED " "Parameter \"port_clkswitch\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979440 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_configupdate PORT_UNUSED " "Parameter \"port_configupdate\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979440 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_fbin PORT_UNUSED " "Parameter \"port_fbin\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979440 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk0 PORT_USED " "Parameter \"port_inclk0\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979440 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk1 PORT_UNUSED " "Parameter \"port_inclk1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979440 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_locked PORT_USED " "Parameter \"port_locked\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979440 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pfdena PORT_UNUSED " "Parameter \"port_pfdena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979440 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasecounterselect PORT_UNUSED " "Parameter \"port_phasecounterselect\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979440 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasedone PORT_UNUSED " "Parameter \"port_phasedone\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979440 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasestep PORT_UNUSED " "Parameter \"port_phasestep\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979440 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phaseupdown PORT_UNUSED " "Parameter \"port_phaseupdown\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979440 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pllena PORT_UNUSED " "Parameter \"port_pllena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979440 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanaclr PORT_UNUSED " "Parameter \"port_scanaclr\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979440 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclk PORT_UNUSED " "Parameter \"port_scanclk\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979440 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclkena PORT_UNUSED " "Parameter \"port_scanclkena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979440 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandata PORT_UNUSED " "Parameter \"port_scandata\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979440 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandataout PORT_UNUSED " "Parameter \"port_scandataout\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979440 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandone PORT_UNUSED " "Parameter \"port_scandone\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979440 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanread PORT_UNUSED " "Parameter \"port_scanread\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979440 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanwrite PORT_UNUSED " "Parameter \"port_scanwrite\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979440 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk0 PORT_USED " "Parameter \"port_clk0\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979440 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk1 PORT_USED " "Parameter \"port_clk1\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979440 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk2 PORT_USED " "Parameter \"port_clk2\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979440 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk3 PORT_UNUSED " "Parameter \"port_clk3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979440 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk4 PORT_UNUSED " "Parameter \"port_clk4\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979440 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk5 PORT_UNUSED " "Parameter \"port_clk5\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979440 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena0 PORT_UNUSED " "Parameter \"port_clkena0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979440 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena1 PORT_UNUSED " "Parameter \"port_clkena1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979440 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena2 PORT_UNUSED " "Parameter \"port_clkena2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979440 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena3 PORT_UNUSED " "Parameter \"port_clkena3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979440 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena4 PORT_UNUSED " "Parameter \"port_clkena4\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979440 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena5 PORT_UNUSED " "Parameter \"port_clkena5\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979440 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk0 PORT_UNUSED " "Parameter \"port_extclk0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979440 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk1 PORT_UNUSED " "Parameter \"port_extclk1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979440 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk2 PORT_UNUSED " "Parameter \"port_extclk2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979440 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk3 PORT_UNUSED " "Parameter \"port_extclk3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979440 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "self_reset_on_loss_lock OFF " "Parameter \"self_reset_on_loss_lock\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979440 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_clock 5 " "Parameter \"width_clock\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979440 ""} } { { "pll.v" "" { Text "/home/benny/work/fpga/spectrum/pll.v" 102 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1648903979440 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/pll_altpll.v 1 1 " "Found 1 design units, including 1 entities, in source file db/pll_altpll.v" { { "Info" "ISGN_ENTITY_NAME" "1 pll_altpll " "Found entity 1: pll_altpll" { } { { "db/pll_altpll.v" "" { Text "/home/benny/work/fpga/spectrum/db/pll_altpll.v" 29 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648903979488 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648903979488 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pll_altpll ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated " "Elaborating entity \"pll_altpll\" for hierarchy \"ula:ula_\|pll:pll_\|altpll:altpll_component\|pll_altpll:auto_generated\"" { } { { "altpll.tdf" "auto_generated" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altpll.tdf" 897 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979488 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clocks ula:ula_\|clocks:clocks_ " "Elaborating entity \"clocks\" for hierarchy \"ula:ula_\|clocks:clocks_\"" { } { { "ula/ula.sv" "clocks_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 85 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979490 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "i2c_loader ula:ula_\|i2c_loader:i2c_loader_ " "Elaborating entity \"i2c_loader\" for hierarchy \"ula:ula_\|i2c_loader:i2c_loader_\"" { } { { "ula/ula.sv" "i2c_loader_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 124 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979491 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "i2s_intf ula:ula_\|i2s_intf:i2s_intf_ " "Elaborating entity \"i2s_intf\" for hierarchy \"ula:ula_\|i2s_intf:i2s_intf_\"" { } { { "ula/ula.sv" "i2s_intf_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 144 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979492 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "video ula:ula_\|video:video_ " "Elaborating entity \"video\" for hierarchy \"ula:ula_\|video:video_\"" { } { { "ula/ula.sv" "video_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 158 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979494 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ps2_keyboard ula:ula_\|ps2_keyboard:ps2_keyboard_ " "Elaborating entity \"ps2_keyboard\" for hierarchy \"ula:ula_\|ps2_keyboard:ps2_keyboard_\"" { } { { "ula/ula.sv" "ps2_keyboard_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 167 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979495 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "zx_keyboard ula:ula_\|zx_keyboard:zx_keyboard_ " "Elaborating entity \"zx_keyboard\" for hierarchy \"ula:ula_\|zx_keyboard:zx_keyboard_\"" { } { { "ula/ula.sv" "zx_keyboard_" { Text "/home/benny/work/fpga/spectrum/ula/ula.sv" 170 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979496 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "z80_top_direct_n z80_top_direct_n:z80_ " "Elaborating entity \"z80_top_direct_n\" for hierarchy \"z80_top_direct_n:z80_\"" { } { { "spectrum.sv" "z80_" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 272 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979499 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clk_delay z80_top_direct_n:z80_\|clk_delay:clk_delay_ " "Elaborating entity \"clk_delay\" for hierarchy \"z80_top_direct_n:z80_\|clk_delay:clk_delay_\"" { } { { "cpu/toplevel/coremodules.vh" "clk_delay_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 20 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979502 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_state z80_top_direct_n:z80_\|decode_state:decode_state_ " "Elaborating entity \"decode_state\" for hierarchy \"z80_top_direct_n:z80_\|decode_state:decode_state_\"" { } { { "cpu/toplevel/coremodules.vh" "decode_state_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 46 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979503 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "execute z80_top_direct_n:z80_\|execute:execute_ " "Elaborating entity \"execute\" for hierarchy \"z80_top_direct_n:z80_\|execute:execute_\"" { } { { "cpu/toplevel/coremodules.vh" "execute_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 180 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979504 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "interrupts z80_top_direct_n:z80_\|interrupts:interrupts_ " "Elaborating entity \"interrupts\" for hierarchy \"z80_top_direct_n:z80_\|interrupts:interrupts_\"" { } { { "cpu/toplevel/coremodules.vh" "interrupts_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 199 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979518 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ir z80_top_direct_n:z80_\|ir:ir_ " "Elaborating entity \"ir\" for hierarchy \"z80_top_direct_n:z80_\|ir:ir_\"" { } { { "cpu/toplevel/coremodules.vh" "ir_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 208 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979518 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pin_control z80_top_direct_n:z80_\|pin_control:pin_control_ " "Elaborating entity \"pin_control\" for hierarchy \"z80_top_direct_n:z80_\|pin_control:pin_control_\"" { } { { "cpu/toplevel/coremodules.vh" "pin_control_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 223 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979519 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pla_decode z80_top_direct_n:z80_\|pla_decode:pla_decode_ " "Elaborating entity \"pla_decode\" for hierarchy \"z80_top_direct_n:z80_\|pla_decode:pla_decode_\"" { } { { "cpu/toplevel/coremodules.vh" "pla_decode_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 229 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979520 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "resets z80_top_direct_n:z80_\|resets:resets_ " "Elaborating entity \"resets\" for hierarchy \"z80_top_direct_n:z80_\|resets:resets_\"" { } { { "cpu/toplevel/coremodules.vh" "resets_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 240 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979522 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "memory_ifc z80_top_direct_n:z80_\|memory_ifc:memory_ifc_ " "Elaborating entity \"memory_ifc\" for hierarchy \"z80_top_direct_n:z80_\|memory_ifc:memory_ifc_\"" { } { { "cpu/toplevel/coremodules.vh" "memory_ifc_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 264 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979522 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sequencer z80_top_direct_n:z80_\|sequencer:sequencer_ " "Elaborating entity \"sequencer\" for hierarchy \"z80_top_direct_n:z80_\|sequencer:sequencer_\"" { } { { "cpu/toplevel/coremodules.vh" "sequencer_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 286 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979523 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_control z80_top_direct_n:z80_\|alu_control:alu_control_ " "Elaborating entity \"alu_control\" for hierarchy \"z80_top_direct_n:z80_\|alu_control:alu_control_\"" { } { { "cpu/toplevel/coremodules.vh" "alu_control_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 326 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979524 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_mux_4 z80_top_direct_n:z80_\|alu_control:alu_control_\|alu_mux_4:b2v_inst_cond_mux " "Elaborating entity \"alu_mux_4\" for hierarchy \"z80_top_direct_n:z80_\|alu_control:alu_control_\|alu_mux_4:b2v_inst_cond_mux\"" { } { { "cpu/alu/alu_control.v" "b2v_inst_cond_mux" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 205 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979525 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_mux_8 z80_top_direct_n:z80_\|alu_control:alu_control_\|alu_mux_8:b2v_inst_shift_mux " "Elaborating entity \"alu_mux_8\" for hierarchy \"z80_top_direct_n:z80_\|alu_control:alu_control_\|alu_mux_8:b2v_inst_shift_mux\"" { } { { "cpu/alu/alu_control.v" "b2v_inst_shift_mux" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 227 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979526 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_select z80_top_direct_n:z80_\|alu_select:alu_select_ " "Elaborating entity \"alu_select\" for hierarchy \"z80_top_direct_n:z80_\|alu_select:alu_select_\"" { } { { "cpu/toplevel/coremodules.vh" "alu_select_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 363 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979527 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_flags z80_top_direct_n:z80_\|alu_flags:alu_flags_ " "Elaborating entity \"alu_flags\" for hierarchy \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\"" { } { { "cpu/toplevel/coremodules.vh" "alu_flags_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 405 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979527 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_mux_2 z80_top_direct_n:z80_\|alu_flags:alu_flags_\|alu_mux_2:b2v_inst_mux_cf " "Elaborating entity \"alu_mux_2\" for hierarchy \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|alu_mux_2:b2v_inst_mux_cf\"" { } { { "cpu/alu/alu_flags.v" "b2v_inst_mux_cf" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_flags.v" 344 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979528 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu z80_top_direct_n:z80_\|alu:alu_ " "Elaborating entity \"alu\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\"" { } { { "cpu/toplevel/coremodules.vh" "alu_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 448 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979529 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_core z80_top_direct_n:z80_\|alu:alu_\|alu_core:b2v_core " "Elaborating entity \"alu_core\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_core:b2v_core\"" { } { { "cpu/alu/alu.v" "b2v_core" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 170 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979531 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_slice z80_top_direct_n:z80_\|alu:alu_\|alu_core:b2v_core\|alu_slice:b2v_alu_slice_bit_0 " "Elaborating entity \"alu_slice\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_core:b2v_core\|alu_slice:b2v_alu_slice_bit_0\"" { } { { "cpu/alu/alu_core.v" "b2v_alu_slice_bit_0" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_core.v" 61 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979532 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_bit_select z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select " "Elaborating entity \"alu_bit_select\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\"" { } { { "cpu/alu/alu.v" "b2v_input_bit_select" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 186 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979534 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_shifter_core z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift " "Elaborating entity \"alu_shifter_core\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\"" { } { { "cpu/alu/alu.v" "b2v_input_shift" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 197 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979534 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_mux_2z z80_top_direct_n:z80_\|alu:alu_\|alu_mux_2z:b2v_op1_latch_mux_high " "Elaborating entity \"alu_mux_2z\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_2z:b2v_op1_latch_mux_high\"" { } { { "cpu/alu/alu.v" "b2v_op1_latch_mux_high" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 318 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979535 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_mux_3z z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low " "Elaborating entity \"alu_mux_3z\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\"" { } { { "cpu/alu/alu.v" "b2v_op1_latch_mux_low" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 328 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979536 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_prep_daa z80_top_direct_n:z80_\|alu:alu_\|alu_prep_daa:b2v_prep_daa " "Elaborating entity \"alu_prep_daa\" for hierarchy \"z80_top_direct_n:z80_\|alu:alu_\|alu_prep_daa:b2v_prep_daa\"" { } { { "cpu/alu/alu.v" "b2v_prep_daa" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 364 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979537 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "reg_file z80_top_direct_n:z80_\|reg_file:reg_file_ " "Elaborating entity \"reg_file\" for hierarchy \"z80_top_direct_n:z80_\|reg_file:reg_file_\"" { } { { "cpu/toplevel/coremodules.vh" "reg_file_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 484 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979538 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "reg_latch z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi " "Elaborating entity \"reg_latch\" for hierarchy \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\"" { } { { "cpu/registers/reg_file.v" "b2v_latch_af2_hi" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 279 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979540 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "reg_control z80_top_direct_n:z80_\|reg_control:reg_control_ " "Elaborating entity \"reg_control\" for hierarchy \"z80_top_direct_n:z80_\|reg_control:reg_control_\"" { } { { "cpu/toplevel/coremodules.vh" "reg_control_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 531 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979552 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "address_latch z80_top_direct_n:z80_\|address_latch:address_latch_ " "Elaborating entity \"address_latch\" for hierarchy \"z80_top_direct_n:z80_\|address_latch:address_latch_\"" { } { { "cpu/toplevel/coremodules.vh" "address_latch_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 547 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979553 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "address_mux z80_top_direct_n:z80_\|address_latch:address_latch_\|address_mux:b2v_inst7 " "Elaborating entity \"address_mux\" for hierarchy \"z80_top_direct_n:z80_\|address_latch:address_latch_\|address_mux:b2v_inst7\"" { } { { "cpu/bus/address_latch.v" "b2v_inst7" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_latch.v" 106 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979554 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "inc_dec z80_top_direct_n:z80_\|address_latch:address_latch_\|inc_dec:b2v_inst_inc_dec " "Elaborating entity \"inc_dec\" for hierarchy \"z80_top_direct_n:z80_\|address_latch:address_latch_\|inc_dec:b2v_inst_inc_dec\"" { } { { "cpu/bus/address_latch.v" "b2v_inst_inc_dec" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_latch.v" 116 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979555 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "inc_dec_2bit z80_top_direct_n:z80_\|address_latch:address_latch_\|inc_dec:b2v_inst_inc_dec\|inc_dec_2bit:b2v_dual_adder_0 " "Elaborating entity \"inc_dec_2bit\" for hierarchy \"z80_top_direct_n:z80_\|address_latch:address_latch_\|inc_dec:b2v_inst_inc_dec\|inc_dec_2bit:b2v_dual_adder_0\"" { } { { "cpu/bus/inc_dec.v" "b2v_dual_adder_0" { Text "/home/benny/work/fpga/spectrum/cpu/bus/inc_dec.v" 80 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979556 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bus_control z80_top_direct_n:z80_\|bus_control:bus_control_ " "Elaborating entity \"bus_control\" for hierarchy \"z80_top_direct_n:z80_\|bus_control:bus_control_\"" { } { { "cpu/toplevel/coremodules.vh" "bus_control_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 553 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979560 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bus_switch z80_top_direct_n:z80_\|bus_switch:bus_switch_ " "Elaborating entity \"bus_switch\" for hierarchy \"z80_top_direct_n:z80_\|bus_switch:bus_switch_\"" { } { { "cpu/toplevel/coremodules.vh" "bus_switch_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh" 566 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979560 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "data_switch z80_top_direct_n:z80_\|data_switch:sw2_ " "Elaborating entity \"data_switch\" for hierarchy \"z80_top_direct_n:z80_\|data_switch:sw2_\"" { } { { "cpu/toplevel/core.vh" "sw2_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/core.vh" 36 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979561 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "data_switch_mask z80_top_direct_n:z80_\|data_switch_mask:sw1_ " "Elaborating entity \"data_switch_mask\" for hierarchy \"z80_top_direct_n:z80_\|data_switch_mask:sw1_\"" { } { { "cpu/toplevel/core.vh" "sw1_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/core.vh" 39 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979562 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "address_pins z80_top_direct_n:z80_\|address_pins:address_pins_ " "Elaborating entity \"address_pins\" for hierarchy \"z80_top_direct_n:z80_\|address_pins:address_pins_\"" { } { { "cpu/toplevel/z80_top_direct_n.v" "address_pins_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 41 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979563 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "data_pins z80_top_direct_n:z80_\|data_pins:data_pins_ " "Elaborating entity \"data_pins\" for hierarchy \"z80_top_direct_n:z80_\|data_pins:data_pins_\"" { } { { "cpu/toplevel/z80_top_direct_n.v" "data_pins_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 51 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979563 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "control_pins_n z80_top_direct_n:z80_\|control_pins_n:control_pins_ " "Elaborating entity \"control_pins_n\" for hierarchy \"z80_top_direct_n:z80_\|control_pins_n:control_pins_\"" { } { { "cpu/toplevel/z80_top_direct_n.v" "control_pins_" { Text "/home/benny/work/fpga/spectrum/cpu/toplevel/z80_top_direct_n.v" 83 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648903979564 ""} +{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "2 " "2 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Quartus II" 0 -1 1648903984007 ""} +{ "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR_HDR" "" "Tri-state node(s) do not directly drive top-level pin(s)" { { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[0\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[0\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984102 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[1\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[1\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984102 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[2\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[2\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984102 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[3\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[3\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984102 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[4\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[4\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984102 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[5\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[5\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984102 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[6\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[6\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984102 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[7\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[7\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984102 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[8\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[8\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984102 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[9\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[9\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984102 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[10\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[10\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984102 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[11\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[11\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984102 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[12\] rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[12\]\" to the node \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|ram_block1a0\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984102 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[13\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|address_reg_a\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[13\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|address_reg_a\[0\]\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984102 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[14\] ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|address_reg_a\[1\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[14\]\" to the node \"ram32:ram1\|altsyncram:altsyncram_component\|altsyncram_g9i1:auto_generated\|address_reg_a\[1\]\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984102 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[15\] ExtRamWE " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|address_pins:address_pins_\|abus\[15\]\" to the node \"ExtRamWE\" into an OR gate" { } { { "cpu/bus/address_pins.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/address_pins.v" 32 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984102 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|control_pins_n:control_pins_\|pin_nWR RamWE " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|control_pins_n:control_pins_\|pin_nWR\" to the node \"RamWE\" into an OR gate" { } { { "cpu/bus/control_pins_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/control_pins_n.v" 77 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984102 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|control_pins_n:control_pins_\|pin_nRD Equal2 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|control_pins_n:control_pins_\|pin_nRD\" to the node \"Equal2\" into an OR gate" { } { { "cpu/bus/control_pins_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/control_pins_n.v" 76 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984102 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|control_pins_n:control_pins_\|pin_nIORQ Equal2 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|control_pins_n:control_pins_\|pin_nIORQ\" to the node \"Equal2\" into an OR gate" { } { { "cpu/bus/control_pins_n.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/control_pins_n.v" 75 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984102 ""} } { } 0 13046 "Tri-state node(s) do not directly drive top-level pin(s)" 0 0 "Quartus II" 0 -1 1648903984102 ""} +{ "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR_HDR" "" "Tri-state node(s) do not directly drive top-level pin(s)" { { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[0\] z80_top_direct_n:z80_\|ir:ir_\|opcode\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[0\]\" to the node \"z80_top_direct_n:z80_\|ir:ir_\|opcode\[0\]\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984108 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[7\] z80_top_direct_n:z80_\|ir:ir_\|opcode\[7\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[7\]\" to the node \"z80_top_direct_n:z80_\|ir:ir_\|opcode\[7\]\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984108 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[6\] z80_top_direct_n:z80_\|ir:ir_\|opcode\[6\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[6\]\" to the node \"z80_top_direct_n:z80_\|ir:ir_\|opcode\[6\]\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984108 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[5\] z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\|bs_out_high\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[5\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\|bs_out_high\[0\]\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984108 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[4\] z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[4\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984108 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[3\] z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[3\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_bit_select:b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984108 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[2\] z80_top_direct_n:z80_\|ir:ir_\|opcode\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[2\]\" to the node \"z80_top_direct_n:z80_\|ir:ir_\|opcode\[2\]\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984108 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[1\] z80_top_direct_n:z80_\|ir:ir_\|opcode\[1\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|bus_control:bus_control_\|db\[1\]\" to the node \"z80_top_direct_n:z80_\|ir:ir_\|opcode\[1\]\" into an OR gate" { } { { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984108 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_high\[3\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_1 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_high\[3\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_1\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 106 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984108 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_high\[2\] z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_2\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_high\[2\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_2\[2\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 106 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984108 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_high\[1\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_13 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_high\[1\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_13\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 106 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984108 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_high\[0\] z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_2\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_high\[0\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_2\[0\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 106 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984108 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_low\[3\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_17 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_low\[3\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_17\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 107 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984108 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_low\[2\] z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_3\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_low\[2\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_3\[2\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 107 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984108 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_low\[1\] z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_3\[1\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_low\[1\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_3\[1\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 107 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984108 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db_low\[0\] z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_3\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db_low\[0\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_mux_3z:b2v_op1_latch_mux_low\|SYNTHESIZED_WIRE_3\[0\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 107 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984108 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[0\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[0\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[0\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984108 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[1\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[1\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[1\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[1\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984108 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[2\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[2\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[2\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984108 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[3\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[3\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[3\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[3\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984108 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[4\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[4\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[4\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[4\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984108 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[5\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[5\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[5\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[5\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984108 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[6\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[6\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[6\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[6\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984108 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[7\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[7\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_lo_as\[7\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[7\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984108 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[0\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[8\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[0\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[8\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984108 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[1\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[9\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[1\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[9\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984108 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[2\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[10\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[2\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[10\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984108 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[3\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[11\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[3\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[11\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984108 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[4\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[12\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[4\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[12\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984108 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[5\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[13\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[5\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[13\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984108 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[6\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[14\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[6\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[14\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984108 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[7\] z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[15\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|db_hi_as\[7\]\" to the node \"z80_top_direct_n:z80_\|address_latch:address_latch_\|abusz\[15\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984108 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[6\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_12 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[6\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_12\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984108 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[7\] z80_top_direct_n:z80_\|alu_control:alu_control_\|alu_mux_8:b2v_inst_shift_mux\|out " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[7\]\" to the node \"z80_top_direct_n:z80_\|alu_control:alu_control_\|alu_mux_8:b2v_inst_shift_mux\|out\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984108 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[0\] z80_top_direct_n:z80_\|alu_control:alu_control_\|shift_cf_out " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[0\]\" to the node \"z80_top_direct_n:z80_\|alu_control:alu_control_\|shift_cf_out\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984108 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[0\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_22 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[0\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_22\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984108 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[7\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_10 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[7\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_10\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984108 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[5\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_14 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[5\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_14\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984108 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[4\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_16 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[4\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_16\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984108 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[3\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_18 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[3\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_18\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984108 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[2\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_20 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[2\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_20\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984108 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[1\] z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_2 " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu_control:alu_control_\|db\[1\]\" to the node \"z80_top_direct_n:z80_\|alu_flags:alu_flags_\|SYNTHESIZED_WIRE_2\" into an OR gate" { } { { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984108 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[6\] z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[3\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[6\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[3\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984108 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[5\] z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[5\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[2\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984108 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[4\] z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[1\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[4\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[1\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984108 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[3\] z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[3\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_high\[0\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984108 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[2\] z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_low\[3\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[2\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_low\[3\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984108 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|alu:alu_\|db\[1\] z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_low\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|alu:alu_\|db\[1\]\" to the node \"z80_top_direct_n:z80_\|alu:alu_\|alu_shifter_core:b2v_input_shift\|out_low\[2\]\" into an OR gate" { } { { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984108 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[0\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[0\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[0\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984108 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[1\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[1\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[1\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[1\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984108 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[2\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[2\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[2\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984108 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[3\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[3\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[3\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[3\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984108 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[4\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[4\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[4\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[4\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984108 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[5\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[5\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[5\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[5\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984108 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[6\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[6\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[6\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[6\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984108 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[7\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[7\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp0\[7\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_lo\|latch\[7\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984108 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[0\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[0\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[0\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[0\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984108 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[1\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[1\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[1\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[1\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984108 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[2\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[2\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[2\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[2\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984108 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[3\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[3\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[3\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[3\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984108 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[4\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[4\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[4\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[4\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984108 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[5\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[5\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[5\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[5\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984108 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[6\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[6\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[6\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[6\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984108 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[7\] z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[7\] " "Converted the fan-out from the tri-state buffer \"z80_top_direct_n:z80_\|reg_file:reg_file_\|gdfx_temp1\[7\]\" to the node \"z80_top_direct_n:z80_\|reg_file:reg_file_\|reg_latch:b2v_latch_af2_hi\|latch\[7\]\" into an OR gate" { } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984108 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[0\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a0 " "Converted the fan-out from the tri-state buffer \"D\[0\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a0\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 76 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984108 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[1\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a1 " "Converted the fan-out from the tri-state buffer \"D\[1\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a1\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 76 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984108 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[2\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a2 " "Converted the fan-out from the tri-state buffer \"D\[2\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a2\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 76 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984108 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[3\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a3 " "Converted the fan-out from the tri-state buffer \"D\[3\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a3\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 76 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984108 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[4\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a4 " "Converted the fan-out from the tri-state buffer \"D\[4\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a4\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 76 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984108 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[5\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a5 " "Converted the fan-out from the tri-state buffer \"D\[5\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a5\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 76 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984108 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[6\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a6 " "Converted the fan-out from the tri-state buffer \"D\[6\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a6\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 76 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984108 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "D\[7\] ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a7 " "Converted the fan-out from the tri-state buffer \"D\[7\]\" to the node \"ram16:ram0\|altsyncram:altsyncram_component\|altsyncram_7ti2:auto_generated\|ram_block1a7\" into an OR gate" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 76 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1648903984108 ""} } { } 0 13046 "Tri-state node(s) do not directly drive top-level pin(s)" 0 0 "Quartus II" 0 -1 1648903984108 ""} +{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" { } { { "cpu/control/resets.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/resets.v" 52 -1 0 } } { "cpu/control/sequencer.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/sequencer.v" 127 -1 0 } } { "cpu/control/sequencer.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/sequencer.v" 201 -1 0 } } { "cpu/control/resets.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/resets.v" 42 -1 0 } } { "ula/zx_kbd.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/zx_kbd.sv" 93 -1 0 } } { "cpu/control/memory_ifc.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/control/memory_ifc.v" 97 -1 0 } } { "ula/i2c_loader.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2c_loader.vhd" 108 -1 0 } } { "ula/i2c_loader.vhd" "" { Text "/home/benny/work/fpga/spectrum/ula/i2c_loader.vhd" 109 -1 0 } } { "ula/ps2_kbd.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/ps2_kbd.sv" 33 -1 0 } } { "ula/ps2_kbd.sv" "" { Text "/home/benny/work/fpga/spectrum/ula/ps2_kbd.sv" 59 -1 0 } } } 0 13000 "Registers with preset signals will power-up high" 0 0 "Quartus II" 0 -1 1648903984132 ""} +{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" { } { } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "Quartus II" 0 -1 1648903984132 ""} +{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "LED\[1\] GND " "Pin \"LED\[1\]\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648903987256 "|spectrum|LED[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LED\[4\] GND " "Pin \"LED\[4\]\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648903987256 "|spectrum|LED[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LED\[5\] GND " "Pin \"LED\[5\]\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648903987256 "|spectrum|LED[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LED\[6\] GND " "Pin \"LED\[6\]\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648903987256 "|spectrum|LED[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LED\[7\] GND " "Pin \"LED\[7\]\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 1 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648903987256 "|spectrum|LED[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "GPIO_1\[24\] VCC " "Pin \"GPIO_1\[24\]\" is stuck at VCC" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648903987256 "|spectrum|GPIO_1[24]"} { "Warning" "WMLS_MLS_STUCK_PIN" "GPIO_1\[32\] GND " "Pin \"GPIO_1\[32\]\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648903987256 "|spectrum|GPIO_1[32]"} { "Warning" "WMLS_MLS_STUCK_PIN" "GPIO_1\[33\] GND " "Pin \"GPIO_1\[33\]\" is stuck at GND" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 20 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648903987256 "|spectrum|GPIO_1[33]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1648903987256 ""} +{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1648903987630 ""} +{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "2 " "2 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1648903990358 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/benny/work/fpga/spectrum/output_files/spectrum.map.smsg " "Generated suppressed messages file /home/benny/work/fpga/spectrum/output_files/spectrum.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1648903990445 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "1 0 1 0 0 " "Adding 1 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1648903990690 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903990690 ""} +{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "2 " "Design contains 2 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[0\] " "No output dependent on input pin \"SW\[0\]\"" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 19 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903990927 "|spectrum|SW[0]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[3\] " "No output dependent on input pin \"SW\[3\]\"" { } { { "spectrum.sv" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sv" 19 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648903990927 "|spectrum|SW[3]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Quartus II" 0 -1 1648903990927 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "2734 " "Implemented 2734 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "11 " "Implemented 11 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1648903990927 ""} { "Info" "ICUT_CUT_TM_OPINS" "62 " "Implemented 62 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1648903990927 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "2 " "Implemented 2 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1648903990927 ""} { "Info" "ICUT_CUT_TM_LCELLS" "2594 " "Implemented 2594 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1648903990927 ""} { "Info" "ICUT_CUT_TM_RAMS" "64 " "Implemented 64 RAM segments" { } { } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Quartus II" 0 -1 1648903990927 ""} { "Info" "ICUT_CUT_TM_PLLS" "1 " "Implemented 1 PLLs" { } { } 0 21065 "Implemented %1!d! PLLs" 0 0 "Quartus II" 0 -1 1648903990927 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1648903990927 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 110 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 110 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "441 " "Peak virtual memory: 441 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648903990946 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 2 15:53:10 2022 " "Processing ended: Sat Apr 2 15:53:10 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648903990946 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:12 " "Elapsed time: 00:00:12" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648903990946 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:13 " "Total CPU time (on all processors): 00:00:13" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648903990946 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648903990946 ""} diff --git a/db/spectrum.map.rdb b/db/spectrum.map.rdb index 354cdc8..df8728f 100644 Binary files a/db/spectrum.map.rdb and b/db/spectrum.map.rdb differ diff --git a/db/spectrum.map_bb.cdb b/db/spectrum.map_bb.cdb index ae2f98f..0ef5e08 100644 Binary files a/db/spectrum.map_bb.cdb and b/db/spectrum.map_bb.cdb differ diff --git a/db/spectrum.map_bb.hdb b/db/spectrum.map_bb.hdb index 49a27df..0d53777 100644 Binary files a/db/spectrum.map_bb.hdb and b/db/spectrum.map_bb.hdb differ diff --git a/db/spectrum.pplq.rdb b/db/spectrum.pplq.rdb index 9e9f17c..e82bd43 100644 Binary files a/db/spectrum.pplq.rdb and b/db/spectrum.pplq.rdb differ diff --git a/db/spectrum.pre_map.hdb b/db/spectrum.pre_map.hdb index ff19523..2d50e36 100644 Binary files a/db/spectrum.pre_map.hdb and b/db/spectrum.pre_map.hdb differ diff --git a/db/spectrum.root_partition.map.reg_db.cdb b/db/spectrum.root_partition.map.reg_db.cdb index 923edc0..26c4b1a 100644 Binary files a/db/spectrum.root_partition.map.reg_db.cdb and b/db/spectrum.root_partition.map.reg_db.cdb differ diff --git a/db/spectrum.routing.rdb b/db/spectrum.routing.rdb index c862e9f..a94c778 100644 Binary files a/db/spectrum.routing.rdb and b/db/spectrum.routing.rdb differ diff --git a/db/spectrum.rtlv.hdb b/db/spectrum.rtlv.hdb index 2740a45..a3143df 100644 Binary files a/db/spectrum.rtlv.hdb and b/db/spectrum.rtlv.hdb differ diff --git a/db/spectrum.rtlv_sg.cdb b/db/spectrum.rtlv_sg.cdb index ec5faa5..0f36795 100644 Binary files a/db/spectrum.rtlv_sg.cdb and b/db/spectrum.rtlv_sg.cdb differ diff --git a/db/spectrum.rtlv_sg_swap.cdb b/db/spectrum.rtlv_sg_swap.cdb index b2ef264..3b7bcf6 100644 Binary files a/db/spectrum.rtlv_sg_swap.cdb and b/db/spectrum.rtlv_sg_swap.cdb differ diff --git a/db/spectrum.sgdiff.cdb b/db/spectrum.sgdiff.cdb index 6061989..4d47aac 100644 Binary files a/db/spectrum.sgdiff.cdb and b/db/spectrum.sgdiff.cdb differ diff --git a/db/spectrum.sgdiff.hdb b/db/spectrum.sgdiff.hdb index 5eedc1c..fcc3eac 100644 Binary files a/db/spectrum.sgdiff.hdb and b/db/spectrum.sgdiff.hdb differ diff --git a/db/spectrum.sta.qmsg b/db/spectrum.sta.qmsg index cd2bc04..f37b4b6 100644 --- a/db/spectrum.sta.qmsg +++ b/db/spectrum.sta.qmsg @@ -1,58 +1,58 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648828544821 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648828544822 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Apr 1 18:55:44 2022 " "Processing started: Fri Apr 1 18:55:44 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648828544822 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648828544822 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta spectrum -c spectrum " "Command: quartus_sta spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648828544822 ""} -{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1648828544853 ""} -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1648828545066 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648828545068 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648828545118 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648828545118 ""} -{ "Info" "ISTA_SDC_FOUND" "spectrum.sdc " "Reading SDC File: 'spectrum.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Quartus II" 0 -1 1648828545540 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 12 KEY1 port " "Ignored filter at spectrum.sdc(12): KEY1 could not be matched with a port" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 12 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1648828545549 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "create_clock spectrum.sdc 12 Argument is an empty collection " "Ignored create_clock at spectrum.sdc(12): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "create_clock -name KEY1 -period 10.000 \[get_ports \{KEY1\}\] " "create_clock -name KEY1 -period 10.000 \[get_ports \{KEY1\}\]" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 12 -1 0 } } } 0 332050 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545549 ""} } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 12 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Quartus II" 0 -1 1648828545549 ""} -{ "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "Deriving PLL clocks " "Deriving PLL clocks" { { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 280 -multiply_by 141 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 280 -multiply_by 141 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545550 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 168 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} " "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 168 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545550 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 98 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} " "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 98 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545550 ""} } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545550 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 21 ula_\|clocks_\|clk_cpu\|regout pin " "Ignored filter at spectrum.sdc(21): ula_\|clocks_\|clk_cpu\|regout could not be matched with a pin" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 21 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1648828545550 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "create_generated_clock spectrum.sdc 21 Argument is an empty collection " "Ignored create_generated_clock at spectrum.sdc(21): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "create_generated_clock -name clk_cpu -source \[get_pins \{ula_\|clocks_\|clk_cpu\|clk\}\] -divide_by 4 \[get_pins \{ula_\|clocks_\|clk_cpu\|regout\}\] " "create_generated_clock -name clk_cpu -source \[get_pins \{ula_\|clocks_\|clk_cpu\|clk\}\] -divide_by 4 \[get_pins \{ula_\|clocks_\|clk_cpu\|regout\}\]" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 21 -1 0 } } } 0 332050 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545551 ""} } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 21 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Quartus II" 0 -1 1648828545551 ""} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_CALL_IS_DELAYED" "" "Clock uncertainty is not calculated until you update the timing netlist." { } { } 0 332151 "Clock uncertainty is not calculated until you update the timing netlist." 0 0 "Quartus II" 0 -1 1648828545551 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 56 clk_cpu clock " "Ignored filter at spectrum.sdc(56): clk_cpu could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 56 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1648828545552 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 57 KEY1 clock " "Ignored filter at spectrum.sdc(57): KEY1 could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 57 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1648828545552 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 54 ula_\|pll_\|altpll_component\|pll\|clk\[0\] clock " "Ignored filter at spectrum.sdc(54): ula_\|pll_\|altpll_component\|pll\|clk\[0\] could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 54 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1648828545552 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 54 ula_\|pll_\|altpll_component\|pll\|clk\[1\] clock " "Ignored filter at spectrum.sdc(54): ula_\|pll_\|altpll_component\|pll\|clk\[1\] could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 54 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1648828545552 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 54 ula_\|pll_\|altpll_component\|pll\|clk\[2\] clock " "Ignored filter at spectrum.sdc(54): ula_\|pll_\|altpll_component\|pll\|clk\[2\] could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 54 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1648828545552 ""} -{ "Warning" "WSTA_SCC_LOOP" "511 " "Found combinational loop of 511 nodes" { { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~3\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~22\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~22\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~22\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~9\|datab " "Node \"z80_\|alu_control_\|db\[0\]~9\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~9\|combout " "Node \"z80_\|alu_control_\|db\[0\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~12\|datac " "Node \"z80_\|alu_control_\|db\[0\]~12\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~12\|combout " "Node \"z80_\|alu_control_\|db\[0\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[0\]~17\|datab " "Node \"z80_\|bus_control_\|db\[0\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[0\]~17\|combout " "Node \"z80_\|bus_control_\|db\[0\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~8\|datac " "Node \"z80_\|alu_control_\|db\[0\]~8\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~8\|combout " "Node \"z80_\|alu_control_\|db\[0\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~9\|dataa " "Node \"z80_\|alu_control_\|db\[0\]~9\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~12\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~12\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~12\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~17\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~17\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~17\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~22\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~22\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~19\|datac " "Node \"z80_\|alu_\|db\[0\]~19\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~19\|combout " "Node \"z80_\|alu_\|db\[0\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~15\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~15\|combout " "Node \"z80_\|alu_\|db_low\[1\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~16\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~16\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~16\|combout " "Node \"z80_\|alu_\|db_low\[1\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~17\|datac " "Node \"z80_\|alu_\|db_low\[1\]~17\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~17\|combout " "Node \"z80_\|alu_\|db_low\[1\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~13\|datac " "Node \"z80_\|alu_\|db\[1\]~13\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~13\|combout " "Node \"z80_\|alu_\|db\[1\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~16\|datac " "Node \"z80_\|alu_\|db_low\[1\]~16\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~21\|datac " "Node \"z80_\|alu_\|db_low\[0\]~21\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~21\|combout " "Node \"z80_\|alu_\|db_low\[0\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~22\|datab " "Node \"z80_\|alu_\|db_low\[0\]~22\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~22\|combout " "Node \"z80_\|alu_\|db_low\[0\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~23\|dataa " "Node \"z80_\|alu_\|db_low\[0\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~23\|combout " "Node \"z80_\|alu_\|db_low\[0\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~18\|datab " "Node \"z80_\|alu_\|db\[0\]~18\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~18\|combout " "Node \"z80_\|alu_\|db\[0\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~19\|dataa " "Node \"z80_\|alu_\|db\[0\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~12\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~12\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~14\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~14\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~14\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~15\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~15\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~15\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~21\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~21\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~21\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~12\|datac " "Node \"z80_\|alu_\|db\[1\]~12\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~12\|combout " "Node \"z80_\|alu_\|db\[1\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~13\|dataa " "Node \"z80_\|alu_\|db\[1\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~0\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~0\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~0\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~1\|datac " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~1\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~1\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~3\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~3\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~3\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~21\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~21\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~2\|datac " "Node \"z80_\|alu_\|db_low\[2\]~2\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~2\|combout " "Node \"z80_\|alu_\|db_low\[2\]~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~3\|datac " "Node \"z80_\|alu_\|db_low\[2\]~3\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~3\|combout " "Node \"z80_\|alu_\|db_low\[2\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~24\|datab " "Node \"z80_\|alu_\|db_low\[2\]~24\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~24\|combout " "Node \"z80_\|alu_\|db_low\[2\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~15\|dataa " "Node \"z80_\|alu_\|db\[2\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~15\|combout " "Node \"z80_\|alu_\|db\[2\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~15\|datad " "Node \"z80_\|alu_\|db_low\[1\]~15\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~35\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~35\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~35\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~35\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~37\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~37\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~37\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~37\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~38\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~38\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~38\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~38\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~39\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~39\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~39\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~39\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~7\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~7\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~7\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~8\|datab " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~8\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~8\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~9\|datad " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~9\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~9\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~39\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~39\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~14\|datad " "Node \"z80_\|alu_\|db\[2\]~14\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~14\|combout " "Node \"z80_\|alu_\|db\[2\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~15\|datac " "Node \"z80_\|alu_\|db\[2\]~15\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~27\|datab " "Node \"z80_\|alu_control_\|db\[2\]~27\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~27\|combout " "Node \"z80_\|alu_control_\|db\[2\]~27\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~29\|datad " "Node \"z80_\|alu_control_\|db\[2\]~29\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~29\|combout " "Node \"z80_\|alu_control_\|db\[2\]~29\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~12\|datab " "Node \"z80_\|bus_control_\|db\[2\]~12\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~12\|combout " "Node \"z80_\|bus_control_\|db\[2\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~13\|datad " "Node \"z80_\|bus_control_\|db\[2\]~13\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~13\|combout " "Node \"z80_\|bus_control_\|db\[2\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~28\|dataa " "Node \"z80_\|alu_control_\|db\[2\]~28\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~28\|combout " "Node \"z80_\|alu_control_\|db\[2\]~28\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~29\|datac " "Node \"z80_\|alu_control_\|db\[2\]~29\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~14\|datac " "Node \"z80_\|alu_\|db\[2\]~14\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~39\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~39\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~39\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~39\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~40\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~40\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~40\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~40\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~41\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~41\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~41\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~41\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~42\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~42\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~42\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~42\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[2\]~2\|datad " "Node \"z80_\|reg_file_\|db_lo_ds\[2\]~2\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[2\]~2\|combout " "Node \"z80_\|reg_file_\|db_lo_ds\[2\]~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~28\|datad " "Node \"z80_\|alu_control_\|db\[2\]~28\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~7\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~7\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~7\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~8\|datad " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~8\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~8\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~9\|datac " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~9\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~9\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~42\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~42\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~3\|dataa " "Node \"z80_\|alu_\|db_low\[2\]~3\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~7\|datad " "Node \"z80_\|alu_\|db_low\[3\]~7\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~7\|combout " "Node \"z80_\|alu_\|db_low\[3\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~8\|datac " "Node \"z80_\|alu_\|db_low\[3\]~8\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~8\|combout " "Node \"z80_\|alu_\|db_low\[3\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~11\|datad " "Node \"z80_\|alu_\|db_low\[3\]~11\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~11\|combout " "Node \"z80_\|alu_\|db_low\[3\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~25\|datac " "Node \"z80_\|alu_\|db_low\[3\]~25\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~25\|combout " "Node \"z80_\|alu_\|db_low\[3\]~25\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~10\|datad " "Node \"z80_\|alu_\|db\[3\]~10\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~10\|combout " "Node \"z80_\|alu_\|db\[3\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~11\|dataa " "Node \"z80_\|alu_\|db\[3\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~11\|combout " "Node \"z80_\|alu_\|db\[3\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~35\|dataa " "Node \"z80_\|alu_control_\|db\[3\]~35\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~35\|combout " "Node \"z80_\|alu_control_\|db\[3\]~35\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~46\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~46\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~46\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~46\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~47\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~47\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~47\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~47\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~50\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~50\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~50\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~50\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~51\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~51\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~51\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~51\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~52\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~52\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~52\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~52\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~34\|dataa " "Node \"z80_\|alu_control_\|db\[3\]~34\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~34\|combout " "Node \"z80_\|alu_control_\|db\[3\]~34\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~35\|datad " "Node \"z80_\|alu_control_\|db\[3\]~35\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~10\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~10\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~10\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~11\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~11\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~12\|datad " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~12\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~12\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~52\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~52\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~11\|datac " "Node \"z80_\|alu_\|db\[3\]~11\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[3\]~21\|datad " "Node \"z80_\|bus_control_\|db\[3\]~21\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[3\]~21\|combout " "Node \"z80_\|bus_control_\|db\[3\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~12\|datad " "Node \"z80_\|alu_\|db_low\[1\]~12\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~12\|combout " "Node \"z80_\|alu_\|db_low\[1\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~14\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~14\|combout " "Node \"z80_\|alu_\|db_low\[1\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~17\|datad " "Node \"z80_\|alu_\|db_low\[1\]~17\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|datad " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|combout " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~10\|datad " "Node \"z80_\|alu_\|db_low\[3\]~10\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~10\|combout " "Node \"z80_\|alu_\|db_low\[3\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~11\|dataa " "Node \"z80_\|alu_\|db_low\[3\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~21\|datad " "Node \"z80_\|alu_\|db_high\[0\]~21\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~21\|combout " "Node \"z80_\|alu_\|db_high\[0\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~25\|datab " "Node \"z80_\|alu_\|db_high\[0\]~25\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~25\|combout " "Node \"z80_\|alu_\|db_high\[0\]~25\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~26\|datac " "Node \"z80_\|alu_\|db_high\[0\]~26\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~26\|combout " "Node \"z80_\|alu_\|db_high\[0\]~26\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~17\|datac " "Node \"z80_\|alu_\|db\[4\]~17\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~17\|combout " "Node \"z80_\|alu_\|db\[4\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~62\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~62\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~62\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~62\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~64\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~64\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~64\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~64\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~65\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~65\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~65\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~65\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~66\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~66\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~66\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~66\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~16\|datad " "Node \"z80_\|alu_\|db\[4\]~16\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~16\|combout " "Node \"z80_\|alu_\|db\[4\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~17\|dataa " "Node \"z80_\|alu_\|db\[4\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~16\|datad " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~16\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~16\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~17\|datad " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~17\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~17\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~18\|datad " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~18\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~18\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~66\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~66\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~7\|dataa " "Node \"z80_\|alu_\|db_low\[3\]~7\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~24\|datac " "Node \"z80_\|alu_\|db_high\[0\]~24\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~24\|combout " "Node \"z80_\|alu_\|db_high\[0\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~25\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~25\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~17\|datad " "Node \"z80_\|alu_\|db_high\[1\]~17\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~17\|combout " "Node \"z80_\|alu_\|db_high\[1\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~18\|datab " "Node \"z80_\|alu_\|db_high\[1\]~18\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~18\|combout " "Node \"z80_\|alu_\|db_high\[1\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~19\|datad " "Node \"z80_\|alu_\|db_high\[1\]~19\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~19\|combout " "Node \"z80_\|alu_\|db_high\[1\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~20\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~20\|combout " "Node \"z80_\|alu_\|db_high\[1\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~25\|dataa " "Node \"z80_\|alu_\|db\[5\]~25\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~25\|combout " "Node \"z80_\|alu_\|db\[5\]~25\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~15\|datab " "Node \"z80_\|alu_control_\|db\[5\]~15\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~15\|combout " "Node \"z80_\|alu_control_\|db\[5\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[5\]~15\|datac " "Node \"z80_\|bus_control_\|db\[5\]~15\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[5\]~15\|combout " "Node \"z80_\|bus_control_\|db\[5\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~12\|datac " "Node \"z80_\|alu_\|db_low\[1\]~12\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~10\|dataa " "Node \"z80_\|alu_\|db_low\[3\]~10\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[5\]~0\|datab " "Node \"z80_\|sw1_\|db_down\[5\]~0\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[5\]~0\|combout " "Node \"z80_\|sw1_\|db_down\[5\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~14\|dataa " "Node \"z80_\|alu_control_\|db\[5\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~14\|combout " "Node \"z80_\|alu_control_\|db\[5\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~15\|datad " "Node \"z80_\|alu_control_\|db\[5\]~15\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~21\|datac " "Node \"z80_\|alu_\|db_high\[0\]~21\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~18\|datac " "Node \"z80_\|alu_\|db_low\[0\]~18\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~18\|combout " "Node \"z80_\|alu_\|db_low\[0\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~20\|dataa " "Node \"z80_\|alu_\|db_low\[0\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~20\|combout " "Node \"z80_\|alu_\|db_low\[0\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~23\|datad " "Node \"z80_\|alu_\|db_low\[0\]~23\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~9\|datac " "Node \"z80_\|alu_\|db_high\[2\]~9\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~9\|combout " "Node \"z80_\|alu_\|db_high\[2\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~13\|dataa " "Node \"z80_\|alu_\|db_high\[2\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~13\|combout " "Node \"z80_\|alu_\|db_high\[2\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~14\|datad " "Node \"z80_\|alu_\|db_high\[2\]~14\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~14\|combout " "Node \"z80_\|alu_\|db_high\[2\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~23\|dataa " "Node \"z80_\|alu_\|db\[6\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~23\|combout " "Node \"z80_\|alu_\|db\[6\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~5\|datac " "Node \"z80_\|alu_\|db_high\[3\]~5\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~5\|combout " "Node \"z80_\|alu_\|db_high\[3\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~6\|datab " "Node \"z80_\|alu_\|db_high\[3\]~6\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~6\|combout " "Node \"z80_\|alu_\|db_high\[3\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~7\|dataa " "Node \"z80_\|alu_\|db_high\[3\]~7\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~7\|combout " "Node \"z80_\|alu_\|db_high\[3\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~8\|datac " "Node \"z80_\|alu_\|db_high\[3\]~8\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~8\|combout " "Node \"z80_\|alu_\|db_high\[3\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~21\|datac " "Node \"z80_\|alu_\|db\[7\]~21\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~21\|combout " "Node \"z80_\|alu_\|db\[7\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~6\|datac " "Node \"z80_\|alu_\|db_high\[3\]~6\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~71\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~71\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~71\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~71\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~73\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~73\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~73\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~73\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~74\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~74\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~74\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~74\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~75\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~75\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~75\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~75\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~19\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~19\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~20\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~20\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~21\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~21\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~75\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~75\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~20\|datac " "Node \"z80_\|alu_\|db\[7\]~20\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~20\|combout " "Node \"z80_\|alu_\|db\[7\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~21\|dataa " "Node \"z80_\|alu_\|db\[7\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|dataa " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|combout " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|dataa " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|combout " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~5\|datab " "Node \"z80_\|alu_\|db_high\[3\]~5\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~21\|datad " "Node \"z80_\|alu_\|db_low\[0\]~21\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~11\|datad " "Node \"z80_\|alu_\|db_high\[2\]~11\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~11\|combout " "Node \"z80_\|alu_\|db_high\[2\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~12\|datab " "Node \"z80_\|alu_\|db_high\[2\]~12\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~12\|combout " "Node \"z80_\|alu_\|db_high\[2\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~13\|datac " "Node \"z80_\|alu_\|db_high\[2\]~13\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~16\|datac " "Node \"z80_\|alu_control_\|db\[7\]~16\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~16\|combout " "Node \"z80_\|alu_control_\|db\[7\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~18\|datad " "Node \"z80_\|alu_control_\|db\[7\]~18\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~18\|combout " "Node \"z80_\|alu_control_\|db\[7\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~5\|datab " "Node \"z80_\|bus_control_\|db\[7\]~5\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~5\|combout " "Node \"z80_\|bus_control_\|db\[7\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~7\|datad " "Node \"z80_\|bus_control_\|db\[7\]~7\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~7\|combout " "Node \"z80_\|bus_control_\|db\[7\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~17\|datad " "Node \"z80_\|alu_control_\|db\[7\]~17\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~17\|combout " "Node \"z80_\|alu_control_\|db\[7\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~18\|dataa " "Node \"z80_\|alu_control_\|db\[7\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~20\|datad " "Node \"z80_\|alu_\|db\[7\]~20\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~89\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~89\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~89\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~89\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~90\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~90\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~90\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~90\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~91\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~91\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~91\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~91\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~92\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~92\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~92\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~92\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[7\]~0\|datac " "Node \"z80_\|reg_file_\|db_lo_ds\[7\]~0\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[7\]~0\|combout " "Node \"z80_\|reg_file_\|db_lo_ds\[7\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~17\|dataa " "Node \"z80_\|alu_control_\|db\[7\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~22\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~22\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~23\|datac " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~23\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~23\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~24\|datac " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~24\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~24\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~92\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~92\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~20\|datab " "Node \"z80_\|alu_control_\|db\[6\]~20\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~20\|combout " "Node \"z80_\|alu_control_\|db\[6\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~21\|datac " "Node \"z80_\|alu_control_\|db\[6\]~21\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~21\|combout " "Node \"z80_\|alu_control_\|db\[6\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~22\|datab " "Node \"z80_\|alu_control_\|db\[6\]~22\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~22\|combout " "Node \"z80_\|alu_control_\|db\[6\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~8\|datab " "Node \"z80_\|bus_control_\|db\[6\]~8\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~8\|combout " "Node \"z80_\|bus_control_\|db\[6\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~9\|dataa " "Node \"z80_\|bus_control_\|db\[6\]~9\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~9\|combout " "Node \"z80_\|bus_control_\|db\[6\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~21\|dataa " "Node \"z80_\|alu_control_\|db\[6\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~79\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~79\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~79\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~79\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~80\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~80\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~80\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~80\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~81\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~81\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~81\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~81\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~82\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~82\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~82\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~82\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~19\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~19\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~20\|datad " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~20\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~20\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~21\|datad " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~21\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~21\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~82\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~82\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~22\|datac " "Node \"z80_\|alu_control_\|db\[6\]~22\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~22\|datad " "Node \"z80_\|alu_\|db\[6\]~22\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~22\|combout " "Node \"z80_\|alu_\|db\[6\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~23\|datac " "Node \"z80_\|alu_\|db\[6\]~23\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~12\|datac " "Node \"z80_\|alu_\|db_high\[2\]~12\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~17\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~80\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~80\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~80\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~80\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~82\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~82\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~82\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~82\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~83\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~83\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~83\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~83\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~84\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~84\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~84\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~84\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~22\|datac " "Node \"z80_\|alu_\|db\[6\]~22\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~22\|datab " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~22\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~22\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~23\|datab " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~23\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~23\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~24\|datad " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~24\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~24\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~84\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~84\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~4\|datac " "Node \"z80_\|alu_\|db_low\[2\]~4\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~4\|combout " "Node \"z80_\|alu_\|db_low\[2\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~6\|dataa " "Node \"z80_\|alu_\|db_low\[2\]~6\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~6\|combout " "Node \"z80_\|alu_\|db_low\[2\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~24\|datac " "Node \"z80_\|alu_\|db_low\[2\]~24\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~15\|datac " "Node \"z80_\|alu_\|db_high\[1\]~15\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~15\|combout " "Node \"z80_\|alu_\|db_high\[1\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~19\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~27\|datac " "Node \"z80_\|alu_\|db_high\[3\]~27\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~27\|combout " "Node \"z80_\|alu_\|db_high\[3\]~27\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~7\|datac " "Node \"z80_\|alu_\|db_high\[3\]~7\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~24\|datab " "Node \"z80_\|alu_\|db\[5\]~24\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~24\|combout " "Node \"z80_\|alu_\|db\[5\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~25\|datac " "Node \"z80_\|alu_\|db\[5\]~25\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~66\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~66\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~66\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~66\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~67\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~67\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~67\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~67\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~70\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~70\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~70\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~70\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~71\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~71\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~71\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~71\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~72\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~72\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~72\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~72\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~14\|datac " "Node \"z80_\|alu_control_\|db\[5\]~14\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~16\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~16\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~16\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~17\|datac " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~17\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~17\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~18\|datad " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~18\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~18\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~72\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~72\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~23\|datac " "Node \"z80_\|alu_\|db_high\[0\]~23\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~23\|combout " "Node \"z80_\|alu_\|db_high\[0\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~24\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~24\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~11\|datac " "Node \"z80_\|alu_\|db_high\[2\]~11\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~53\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~53\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~53\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~53\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~55\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~55\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~55\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~55\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~56\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~56\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~56\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~56\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~57\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~57\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~57\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~57\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~13\|datab " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~13\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~13\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~14\|datab " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~14\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~14\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~15\|datad " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~15\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~15\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~57\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~57\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~24\|datac " "Node \"z80_\|alu_\|db\[5\]~24\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~18\|datac " "Node \"z80_\|alu_\|db_high\[1\]~18\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~30\|dataa " "Node \"z80_\|alu_control_\|db\[4\]~30\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~30\|combout " "Node \"z80_\|alu_control_\|db\[4\]~30\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~31\|datad " "Node \"z80_\|alu_control_\|db\[4\]~31\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~31\|combout " "Node \"z80_\|alu_control_\|db\[4\]~31\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~32\|datad " "Node \"z80_\|alu_control_\|db\[4\]~32\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~32\|combout " "Node \"z80_\|alu_control_\|db\[4\]~32\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[4\]~19\|datab " "Node \"z80_\|bus_control_\|db\[4\]~19\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[4\]~19\|combout " "Node \"z80_\|bus_control_\|db\[4\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~12\|datab " "Node \"z80_\|alu_\|db_low\[1\]~12\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|datab " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~32\|dataa " "Node \"z80_\|alu_control_\|db\[4\]~32\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~21\|datab " "Node \"z80_\|alu_\|db_high\[0\]~21\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~18\|datab " "Node \"z80_\|alu_\|db_low\[0\]~18\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~9\|datab " "Node \"z80_\|alu_\|db_high\[2\]~9\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~4\|datab " "Node \"z80_\|alu_\|db_low\[2\]~4\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~15\|datab " "Node \"z80_\|alu_\|db_high\[1\]~15\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~27\|datab " "Node \"z80_\|alu_\|db_high\[3\]~27\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~16\|datac " "Node \"z80_\|alu_\|db\[4\]~16\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~54\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~54\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~54\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~54\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~61\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~61\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~61\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~61\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~62\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~62\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~62\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~62\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~30\|datac " "Node \"z80_\|alu_control_\|db\[4\]~30\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~13\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~13\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~14\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~14\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~14\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~15\|datad " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~15\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~15\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~62\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~62\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~18\|datad " "Node \"z80_\|alu_\|db_low\[0\]~18\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~9\|datad " "Node \"z80_\|alu_\|db_high\[2\]~9\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~4\|datad " "Node \"z80_\|alu_\|db_low\[2\]~4\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~15\|datad " "Node \"z80_\|alu_\|db_high\[1\]~15\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~27\|datad " "Node \"z80_\|alu_\|db_high\[3\]~27\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[3\]~1\|datad " "Node \"z80_\|sw1_\|db_down\[3\]~1\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[3\]~1\|combout " "Node \"z80_\|sw1_\|db_down\[3\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~34\|datad " "Node \"z80_\|alu_control_\|db\[3\]~34\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~8\|dataa " "Node \"z80_\|alu_\|db_low\[3\]~8\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~23\|datab " "Node \"z80_\|alu_\|db_high\[0\]~23\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~44\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~44\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~44\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~44\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~46\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~46\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~46\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~46\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~47\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~47\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~47\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~47\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~48\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~48\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~48\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~48\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~10\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~10\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~10\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~11\|datac " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~11\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~11\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~12\|datad " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~12\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~12\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~48\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~48\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~10\|datac " "Node \"z80_\|alu_\|db\[3\]~10\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~2\|datab " "Node \"z80_\|alu_\|db_low\[2\]~2\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~24\|datad " "Node \"z80_\|alu_control_\|db\[1\]~24\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~24\|combout " "Node \"z80_\|alu_control_\|db\[1\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~26\|datad " "Node \"z80_\|alu_control_\|db\[1\]~26\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~26\|combout " "Node \"z80_\|alu_control_\|db\[1\]~26\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~10\|datab " "Node \"z80_\|bus_control_\|db\[1\]~10\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~10\|combout " "Node \"z80_\|bus_control_\|db\[1\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~11\|datac " "Node \"z80_\|bus_control_\|db\[1\]~11\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~11\|combout " "Node \"z80_\|bus_control_\|db\[1\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~25\|dataa " "Node \"z80_\|alu_control_\|db\[1\]~25\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~25\|combout " "Node \"z80_\|alu_control_\|db\[1\]~25\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~26\|dataa " "Node \"z80_\|alu_control_\|db\[1\]~26\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~12\|datab " "Node \"z80_\|alu_\|db\[1\]~12\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~29\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~29\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~29\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~29\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~30\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~30\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~30\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~30\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~31\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~31\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~31\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~31\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~32\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~32\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~32\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~32\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[1\]~1\|datac " "Node \"z80_\|reg_file_\|db_lo_ds\[1\]~1\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[1\]~1\|combout " "Node \"z80_\|reg_file_\|db_lo_ds\[1\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~25\|datab " "Node \"z80_\|alu_control_\|db\[1\]~25\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~4\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~4\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~4\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~5\|datad " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~5\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~5\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~6\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~6\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~6\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~32\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~32\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|datac " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~22\|datac " "Node \"z80_\|alu_\|db_low\[0\]~22\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~26\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~26\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~26\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~26\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~28\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~28\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~28\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~28\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~29\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~29\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~29\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~29\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~30\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~30\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~30\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~30\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~4\|datab " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~4\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~4\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~5\|datad " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~5\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~5\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~6\|datad " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~6\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~6\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~30\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~30\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~18\|datac " "Node \"z80_\|alu_\|db\[0\]~18\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw2_\|db_up\[0\]~0\|datad " "Node \"z80_\|sw2_\|db_up\[0\]~0\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw2_\|db_up\[0\]~0\|combout " "Node \"z80_\|sw2_\|db_up\[0\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~9\|datad " "Node \"z80_\|alu_control_\|db\[0\]~9\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~0\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~0\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~0\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~1\|datad " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~1\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~1\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~3\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~3\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648828545559 ""} } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 107 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 88 -1 0 } } { "cpu/alu/alu_bit_select.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_bit_select.v" 30 -1 0 } } { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 106 -1 0 } } { "cpu/bus/data_switch_mask.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch_mask.v" 31 -1 0 } } { "cpu/alu/alu_mux_8.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_8.v" 42 -1 0 } } { "cpu/bus/data_switch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch.v" 30 -1 0 } } } 0 332125 "Found combinational loop of %1!d! nodes" 0 0 "Quartus II" 0 -1 1648828545559 ""} -{ "Critical Warning" "WSTA_SCC_LOOP_TOO_BIG" "511 " "Design contains combinational loop of 511 nodes. Estimating the delays through the loop." { } { } 1 332081 "Design contains combinational loop of %1!d! nodes. Estimating the delays through the loop." 0 0 "Quartus II" 0 -1 1648828545577 ""} -{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ula:ula_\|clocks:clocks_\|clk_cpu " "Node: ula:ula_\|clocks:clocks_\|clk_cpu was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1648828545610 "|spectrum|ula:ula_|clocks:clocks_|clk_cpu"} -{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "KEY\[1\] " "Node: KEY\[1\] was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1648828545610 "|spectrum|KEY[1]"} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545745 ""} -{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1648828545747 ""} -{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1648828545777 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648828545819 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648828545819 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -18.123 " "Worst-case setup slack is -18.123" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545820 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545820 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -18.123 -549.338 CLOCK_50 " " -18.123 -549.338 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545820 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -7.533 -284.813 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " -7.533 -284.813 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545820 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.740 -42.810 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " -4.740 -42.810 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545820 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.914 -2.914 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " -2.914 -2.914 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545820 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648828545820 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.210 " "Worst-case hold slack is 0.210" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545826 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545826 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.210 0.000 CLOCK_50 " " 0.210 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545826 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.342 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 0.342 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545826 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.344 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 0.344 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545826 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.357 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.357 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545826 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648828545826 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -6.223 " "Worst-case recovery slack is -6.223" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545827 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545827 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -6.223 -459.348 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " -6.223 -459.348 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545827 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648828545827 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "removal 3.698 " "Worst-case removal slack is 3.698" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545828 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545828 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 3.698 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 3.698 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545828 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648828545828 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 9.488 " "Worst-case minimum pulse width slack is 9.488" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545829 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545829 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.488 0.000 CLOCK_50 " " 9.488 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545829 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 19.602 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 19.602 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545829 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 20.595 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 20.595 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545829 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 35.503 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 35.503 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828545829 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648828545829 ""} -{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1648828545969 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1648828546007 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1648828546952 ""} -{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ula:ula_\|clocks:clocks_\|clk_cpu " "Node: ula:ula_\|clocks:clocks_\|clk_cpu was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1648828547129 "|spectrum|ula:ula_|clocks:clocks_|clk_cpu"} -{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "KEY\[1\] " "Node: KEY\[1\] was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1648828547129 "|spectrum|KEY[1]"} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547131 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648828547148 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648828547148 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -17.311 " "Worst-case setup slack is -17.311" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547151 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547151 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -17.311 -526.609 CLOCK_50 " " -17.311 -526.609 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547151 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -6.686 -253.661 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " -6.686 -253.661 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547151 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.428 -40.009 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " -4.428 -40.009 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547151 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.785 -2.785 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " -2.785 -2.785 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547151 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648828547151 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.298 " "Worst-case hold slack is 0.298" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547159 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547159 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.298 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 0.298 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547159 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.300 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 0.300 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547159 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.304 0.000 CLOCK_50 " " 0.304 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547159 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.311 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.311 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547159 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648828547159 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -5.744 " "Worst-case recovery slack is -5.744" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547162 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547162 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -5.744 -423.582 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " -5.744 -423.582 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547162 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648828547162 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "removal 3.374 " "Worst-case removal slack is 3.374" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547165 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547165 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 3.374 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 3.374 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547165 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648828547165 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 9.489 " "Worst-case minimum pulse width slack is 9.489" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547168 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547168 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.489 0.000 CLOCK_50 " " 9.489 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547168 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 19.600 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 19.600 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547168 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 20.591 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 20.591 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547168 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 35.491 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 35.491 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547168 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648828547168 ""} -{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1648828547327 ""} -{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ula:ula_\|clocks:clocks_\|clk_cpu " "Node: ula:ula_\|clocks:clocks_\|clk_cpu was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1648828547608 "|spectrum|ula:ula_|clocks:clocks_|clk_cpu"} -{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "KEY\[1\] " "Node: KEY\[1\] was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1648828547608 "|spectrum|KEY[1]"} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547610 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648828547617 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648828547617 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -14.971 " "Worst-case setup slack is -14.971" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547622 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547622 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -14.971 -442.545 CLOCK_50 " " -14.971 -442.545 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547622 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.979 -171.124 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " -4.979 -171.124 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547622 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.775 -35.541 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " -3.775 -35.541 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547622 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.784 -2.784 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " -2.784 -2.784 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547622 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648828547622 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.053 " "Worst-case hold slack is -0.053" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547632 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547632 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.053 -0.089 CLOCK_50 " " -0.053 -0.089 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547632 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.177 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 0.177 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547632 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.178 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 0.178 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547632 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.186 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.186 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547632 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648828547632 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -4.693 " "Worst-case recovery slack is -4.693" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547637 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547637 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.693 -358.284 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " -4.693 -358.284 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547637 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648828547637 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "removal 2.518 " "Worst-case removal slack is 2.518" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547642 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547642 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 2.518 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 2.518 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547642 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648828547642 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 9.208 " "Worst-case minimum pulse width slack is 9.208" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547647 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547647 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.208 0.000 CLOCK_50 " " 9.208 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547647 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 19.609 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 19.609 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547647 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 20.600 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 20.600 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547647 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 35.535 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 35.535 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648828547647 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648828547647 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1648828548217 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1648828548217 ""} -{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 532 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 532 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "437 " "Peak virtual memory: 437 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648828548454 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 1 18:55:48 2022 " "Processing ended: Fri Apr 1 18:55:48 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648828548454 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648828548454 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648828548454 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648828548454 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648904018029 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648904018030 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Apr 2 15:53:37 2022 " "Processing started: Sat Apr 2 15:53:37 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648904018030 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648904018030 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta spectrum -c spectrum " "Command: quartus_sta spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648904018030 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1648904018057 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1648904018261 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648904018263 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648904018308 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648904018308 ""} +{ "Info" "ISTA_SDC_FOUND" "spectrum.sdc " "Reading SDC File: 'spectrum.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Quartus II" 0 -1 1648904018704 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 12 KEY1 port " "Ignored filter at spectrum.sdc(12): KEY1 could not be matched with a port" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 12 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1648904018713 ""} +{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "create_clock spectrum.sdc 12 Argument is an empty collection " "Ignored create_clock at spectrum.sdc(12): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "create_clock -name KEY1 -period 10.000 \[get_ports \{KEY1\}\] " "create_clock -name KEY1 -period 10.000 \[get_ports \{KEY1\}\]" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 12 -1 0 } } } 0 332050 "%1!s!" 0 0 "Quartus II" 0 -1 1648904018713 ""} } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 12 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Quartus II" 0 -1 1648904018713 ""} +{ "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "Deriving PLL clocks " "Deriving PLL clocks" { { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 280 -multiply_by 141 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 280 -multiply_by 141 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648904018714 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 168 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} " "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 168 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648904018714 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 98 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} " "create_generated_clock -source \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 98 -multiply_by 47 -duty_cycle 50.00 -name \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} \{ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\]\}" { } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648904018714 ""} } { } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1648904018714 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 21 ula_\|clocks_\|clk_cpu\|regout pin " "Ignored filter at spectrum.sdc(21): ula_\|clocks_\|clk_cpu\|regout could not be matched with a pin" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 21 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1648904018714 ""} +{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "create_generated_clock spectrum.sdc 21 Argument is an empty collection " "Ignored create_generated_clock at spectrum.sdc(21): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "create_generated_clock -name clk_cpu -source \[get_pins \{ula_\|clocks_\|clk_cpu\|clk\}\] -divide_by 4 \[get_pins \{ula_\|clocks_\|clk_cpu\|regout\}\] " "create_generated_clock -name clk_cpu -source \[get_pins \{ula_\|clocks_\|clk_cpu\|clk\}\] -divide_by 4 \[get_pins \{ula_\|clocks_\|clk_cpu\|regout\}\]" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 21 -1 0 } } } 0 332050 "%1!s!" 0 0 "Quartus II" 0 -1 1648904018714 ""} } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 21 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Quartus II" 0 -1 1648904018714 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_CALL_IS_DELAYED" "" "Clock uncertainty is not calculated until you update the timing netlist." { } { } 0 332151 "Clock uncertainty is not calculated until you update the timing netlist." 0 0 "Quartus II" 0 -1 1648904018715 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 56 clk_cpu clock " "Ignored filter at spectrum.sdc(56): clk_cpu could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 56 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1648904018716 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 57 KEY1 clock " "Ignored filter at spectrum.sdc(57): KEY1 could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 57 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1648904018716 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 54 ula_\|pll_\|altpll_component\|pll\|clk\[0\] clock " "Ignored filter at spectrum.sdc(54): ula_\|pll_\|altpll_component\|pll\|clk\[0\] could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 54 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1648904018716 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 54 ula_\|pll_\|altpll_component\|pll\|clk\[1\] clock " "Ignored filter at spectrum.sdc(54): ula_\|pll_\|altpll_component\|pll\|clk\[1\] could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 54 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1648904018716 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "spectrum.sdc 54 ula_\|pll_\|altpll_component\|pll\|clk\[2\] clock " "Ignored filter at spectrum.sdc(54): ula_\|pll_\|altpll_component\|pll\|clk\[2\] could not be matched with a clock" { } { { "/home/benny/work/fpga/spectrum/spectrum.sdc" "" { Text "/home/benny/work/fpga/spectrum/spectrum.sdc" 54 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1648904018716 ""} +{ "Warning" "WSTA_SCC_LOOP" "517 " "Found combinational loop of 517 nodes" { { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~3\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~22\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~22\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~22\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~0\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~0\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~0\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~1\|datac " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~1\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~1\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[0\]~3\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[0\]~3\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~9\|datac " "Node \"z80_\|alu_control_\|db\[0\]~9\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~9\|combout " "Node \"z80_\|alu_control_\|db\[0\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~12\|datac " "Node \"z80_\|alu_control_\|db\[0\]~12\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~12\|combout " "Node \"z80_\|alu_control_\|db\[0\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[0\]~17\|datab " "Node \"z80_\|bus_control_\|db\[0\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[0\]~17\|combout " "Node \"z80_\|bus_control_\|db\[0\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~8\|datad " "Node \"z80_\|alu_control_\|db\[0\]~8\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~8\|combout " "Node \"z80_\|alu_control_\|db\[0\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~9\|datab " "Node \"z80_\|alu_control_\|db\[0\]~9\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~14\|dataa " "Node \"z80_\|alu_\|db\[0\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~14\|combout " "Node \"z80_\|alu_\|db\[0\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|datad " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|combout " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|dataa " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|combout " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~2\|datab " "Node \"z80_\|alu_\|db_low\[0\]~2\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~2\|combout " "Node \"z80_\|alu_\|db_low\[0\]~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~3\|datac " "Node \"z80_\|alu_\|db_low\[0\]~3\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~3\|combout " "Node \"z80_\|alu_\|db_low\[0\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~24\|datab " "Node \"z80_\|alu_\|db_low\[0\]~24\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~24\|combout " "Node \"z80_\|alu_\|db_low\[0\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~13\|datac " "Node \"z80_\|alu_\|db\[0\]~13\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~13\|combout " "Node \"z80_\|alu_\|db\[0\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~14\|datad " "Node \"z80_\|alu_\|db\[0\]~14\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~4\|datab " "Node \"z80_\|alu_\|db_high\[3\]~4\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~4\|combout " "Node \"z80_\|alu_\|db_high\[3\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~5\|datad " "Node \"z80_\|alu_\|db_high\[3\]~5\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~5\|combout " "Node \"z80_\|alu_\|db_high\[3\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~6\|datab " "Node \"z80_\|alu_\|db_high\[3\]~6\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~6\|combout " "Node \"z80_\|alu_\|db_high\[3\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~7\|datad " "Node \"z80_\|alu_\|db_high\[3\]~7\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~7\|combout " "Node \"z80_\|alu_\|db_high\[3\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~12\|datac " "Node \"z80_\|alu_\|db\[7\]~12\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~12\|combout " "Node \"z80_\|alu_\|db\[7\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~5\|dataa " "Node \"z80_\|alu_\|db_high\[3\]~5\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|dataa " "Node \"z80_\|alu_control_\|b2v_inst_shift_mux\|out~1\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~8\|datac " "Node \"z80_\|alu_\|db_high\[2\]~8\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~8\|combout " "Node \"z80_\|alu_\|db_high\[2\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~9\|datac " "Node \"z80_\|alu_\|db_high\[2\]~9\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~9\|combout " "Node \"z80_\|alu_\|db_high\[2\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~12\|dataa " "Node \"z80_\|alu_\|db_high\[2\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~12\|combout " "Node \"z80_\|alu_\|db_high\[2\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~13\|datab " "Node \"z80_\|alu_\|db_high\[2\]~13\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~13\|combout " "Node \"z80_\|alu_\|db_high\[2\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~22\|datac " "Node \"z80_\|alu_\|db\[6\]~22\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~22\|combout " "Node \"z80_\|alu_\|db\[6\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~4\|dataa " "Node \"z80_\|alu_\|db_high\[3\]~4\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~9\|dataa " "Node \"z80_\|alu_\|db_high\[2\]~9\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~80\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~80\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~80\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~80\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~82\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~82\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~82\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~82\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~83\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~83\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~83\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~83\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~84\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~84\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~84\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~84\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~22\|datab " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~22\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~22\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~23\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~23\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~24\|datac " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~24\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[6\]~24\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[6\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[6\]~84\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[6\]~84\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~21\|datad " "Node \"z80_\|alu_\|db\[6\]~21\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~21\|combout " "Node \"z80_\|alu_\|db\[6\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~22\|datad " "Node \"z80_\|alu_\|db\[6\]~22\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~20\|dataa " "Node \"z80_\|alu_control_\|db\[6\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~20\|combout " "Node \"z80_\|alu_control_\|db\[6\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~21\|datad " "Node \"z80_\|alu_control_\|db\[6\]~21\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~21\|combout " "Node \"z80_\|alu_control_\|db\[6\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~22\|datac " "Node \"z80_\|alu_control_\|db\[6\]~22\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~22\|combout " "Node \"z80_\|alu_control_\|db\[6\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~8\|datad " "Node \"z80_\|bus_control_\|db\[6\]~8\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~8\|combout " "Node \"z80_\|bus_control_\|db\[6\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~9\|datab " "Node \"z80_\|bus_control_\|db\[6\]~9\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[6\]~9\|combout " "Node \"z80_\|bus_control_\|db\[6\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[6\]~1\|datab " "Node \"z80_\|sw1_\|db_down\[6\]~1\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[6\]~1\|combout " "Node \"z80_\|sw1_\|db_down\[6\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~22\|datab " "Node \"z80_\|alu_control_\|db\[6\]~22\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[6\]~21\|datab " "Node \"z80_\|alu_\|db\[6\]~21\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~79\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~79\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~79\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~79\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~80\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~80\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~80\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~80\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~81\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~81\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~81\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~81\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~82\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~82\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~82\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~82\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[6\]~0\|datad " "Node \"z80_\|reg_file_\|db_lo_ds\[6\]~0\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[6\]~0\|combout " "Node \"z80_\|reg_file_\|db_lo_ds\[6\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[6\]~22\|dataa " "Node \"z80_\|alu_control_\|db\[6\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~19\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~19\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~20\|datad " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~20\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~20\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~21\|datac " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~21\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[6\]~21\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[6\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[6\]~82\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[6\]~82\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~16\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~16\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~16\|combout " "Node \"z80_\|alu_\|db_high\[1\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~17\|datab " "Node \"z80_\|alu_\|db_high\[1\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~17\|combout " "Node \"z80_\|alu_\|db_high\[1\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~18\|datad " "Node \"z80_\|alu_\|db_high\[1\]~18\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~18\|combout " "Node \"z80_\|alu_\|db_high\[1\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~19\|datad " "Node \"z80_\|alu_\|db_high\[1\]~19\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~19\|combout " "Node \"z80_\|alu_\|db_high\[1\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~24\|datab " "Node \"z80_\|alu_\|db\[5\]~24\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~24\|combout " "Node \"z80_\|alu_\|db\[5\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~8\|datab " "Node \"z80_\|alu_\|db_high\[2\]~8\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~22\|datac " "Node \"z80_\|alu_\|db_high\[0\]~22\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~22\|combout " "Node \"z80_\|alu_\|db_high\[0\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~23\|datad " "Node \"z80_\|alu_\|db_high\[0\]~23\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~23\|combout " "Node \"z80_\|alu_\|db_high\[0\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~24\|datad " "Node \"z80_\|alu_\|db_high\[0\]~24\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~24\|combout " "Node \"z80_\|alu_\|db_high\[0\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~25\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~25\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~25\|combout " "Node \"z80_\|alu_\|db_high\[0\]~25\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~18\|datad " "Node \"z80_\|alu_\|db\[4\]~18\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~18\|combout " "Node \"z80_\|alu_\|db\[4\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~30\|dataa " "Node \"z80_\|alu_control_\|db\[4\]~30\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~30\|combout " "Node \"z80_\|alu_control_\|db\[4\]~30\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~31\|datad " "Node \"z80_\|alu_control_\|db\[4\]~31\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~31\|combout " "Node \"z80_\|alu_control_\|db\[4\]~31\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~32\|datab " "Node \"z80_\|alu_control_\|db\[4\]~32\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~32\|combout " "Node \"z80_\|alu_control_\|db\[4\]~32\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~54\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~54\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~54\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~54\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~61\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~61\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~61\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~61\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~62\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~62\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~62\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~62\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~30\|datab " "Node \"z80_\|alu_control_\|db\[4\]~30\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~13\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~13\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~13\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~14\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~14\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~14\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~15\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~15\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[4\]~15\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[4\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[4\]~62\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[4\]~62\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~17\|datab " "Node \"z80_\|alu_\|db\[4\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~17\|combout " "Node \"z80_\|alu_\|db\[4\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~18\|datac " "Node \"z80_\|alu_\|db\[4\]~18\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[4\]~19\|datac " "Node \"z80_\|bus_control_\|db\[4\]~19\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[4\]~19\|combout " "Node \"z80_\|bus_control_\|db\[4\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[4\]~32\|dataa " "Node \"z80_\|alu_control_\|db\[4\]~32\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|datab " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|combout " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~16\|dataa " "Node \"z80_\|alu_\|db_low\[3\]~16\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~16\|combout " "Node \"z80_\|alu_\|db_low\[3\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~17\|datab " "Node \"z80_\|alu_\|db_low\[3\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~17\|combout " "Node \"z80_\|alu_\|db_low\[3\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~25\|datad " "Node \"z80_\|alu_\|db_low\[3\]~25\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~25\|combout " "Node \"z80_\|alu_\|db_low\[3\]~25\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~19\|datab " "Node \"z80_\|alu_\|db\[3\]~19\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~19\|combout " "Node \"z80_\|alu_\|db\[3\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~20\|datad " "Node \"z80_\|alu_\|db\[3\]~20\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~20\|combout " "Node \"z80_\|alu_\|db\[3\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~22\|datab " "Node \"z80_\|alu_\|db_high\[0\]~22\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~35\|datac " "Node \"z80_\|alu_control_\|db\[3\]~35\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~35\|combout " "Node \"z80_\|alu_control_\|db\[3\]~35\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[3\]~21\|datab " "Node \"z80_\|bus_control_\|db\[3\]~21\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[3\]~21\|combout " "Node \"z80_\|bus_control_\|db\[3\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~11\|datac " "Node \"z80_\|alu_\|db_high\[2\]~11\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~11\|combout " "Node \"z80_\|alu_\|db_high\[2\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~12\|datac " "Node \"z80_\|alu_\|db_high\[2\]~12\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~20\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~20\|combout " "Node \"z80_\|alu_\|db_high\[0\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~24\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~24\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~14\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~14\|combout " "Node \"z80_\|alu_\|db_high\[1\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~18\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~18\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~4\|dataa " "Node \"z80_\|alu_\|db_low\[0\]~4\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~4\|combout " "Node \"z80_\|alu_\|db_low\[0\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~6\|datab " "Node \"z80_\|alu_\|db_low\[0\]~6\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~6\|combout " "Node \"z80_\|alu_\|db_low\[0\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~24\|dataa " "Node \"z80_\|alu_\|db_low\[0\]~24\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[3\]~2\|datad " "Node \"z80_\|sw1_\|db_down\[3\]~2\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[3\]~2\|combout " "Node \"z80_\|sw1_\|db_down\[3\]~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~34\|datad " "Node \"z80_\|alu_control_\|db\[3\]~34\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~34\|combout " "Node \"z80_\|alu_control_\|db\[3\]~34\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~35\|dataa " "Node \"z80_\|alu_control_\|db\[3\]~35\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|datac " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|combout " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~19\|dataa " "Node \"z80_\|alu_\|db_low\[2\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~19\|combout " "Node \"z80_\|alu_\|db_low\[2\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~20\|datad " "Node \"z80_\|alu_\|db_low\[2\]~20\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~20\|combout " "Node \"z80_\|alu_\|db_low\[2\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~23\|datad " "Node \"z80_\|alu_\|db_low\[2\]~23\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~23\|combout " "Node \"z80_\|alu_\|db_low\[2\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~16\|datad " "Node \"z80_\|alu_\|db\[2\]~16\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~16\|combout " "Node \"z80_\|alu_\|db\[2\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~27\|dataa " "Node \"z80_\|alu_control_\|db\[2\]~27\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~27\|combout " "Node \"z80_\|alu_control_\|db\[2\]~27\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~29\|datab " "Node \"z80_\|alu_control_\|db\[2\]~29\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~29\|combout " "Node \"z80_\|alu_control_\|db\[2\]~29\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~12\|datac " "Node \"z80_\|bus_control_\|db\[2\]~12\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~12\|combout " "Node \"z80_\|bus_control_\|db\[2\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~13\|datad " "Node \"z80_\|bus_control_\|db\[2\]~13\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[2\]~13\|combout " "Node \"z80_\|bus_control_\|db\[2\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~28\|datab " "Node \"z80_\|alu_control_\|db\[2\]~28\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~28\|combout " "Node \"z80_\|alu_control_\|db\[2\]~28\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~29\|dataa " "Node \"z80_\|alu_control_\|db\[2\]~29\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~15\|datad " "Node \"z80_\|alu_\|db\[2\]~15\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~15\|combout " "Node \"z80_\|alu_\|db\[2\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~16\|datab " "Node \"z80_\|alu_\|db\[2\]~16\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~39\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~39\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~39\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~39\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~40\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~40\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~40\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~40\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~41\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~41\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~41\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~41\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~42\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~42\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~42\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~42\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[2\]~2\|datad " "Node \"z80_\|reg_file_\|db_lo_ds\[2\]~2\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[2\]~2\|combout " "Node \"z80_\|reg_file_\|db_lo_ds\[2\]~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[2\]~28\|datad " "Node \"z80_\|alu_control_\|db\[2\]~28\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~7\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~7\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~7\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~8\|datac " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~8\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~8\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~9\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~9\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[2\]~9\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[2\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[2\]~42\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[2\]~42\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~35\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~35\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~35\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~35\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~37\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~37\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~37\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~37\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~38\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~38\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~38\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~38\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~39\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~39\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~39\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~39\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~7\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~7\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~7\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~8\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~8\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~8\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~9\|datac " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~9\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[2\]~9\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[2\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[2\]~39\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[2\]~39\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[2\]~15\|datab " "Node \"z80_\|alu_\|db\[2\]~15\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~13\|datad " "Node \"z80_\|alu_\|db_low\[3\]~13\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~13\|combout " "Node \"z80_\|alu_\|db_low\[3\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~14\|dataa " "Node \"z80_\|alu_\|db_low\[3\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~14\|combout " "Node \"z80_\|alu_\|db_low\[3\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~17\|datad " "Node \"z80_\|alu_\|db_low\[3\]~17\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~22\|datac " "Node \"z80_\|alu_\|db_low\[2\]~22\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~22\|combout " "Node \"z80_\|alu_\|db_low\[2\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~23\|dataa " "Node \"z80_\|alu_\|db_low\[2\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~10\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~10\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~10\|combout " "Node \"z80_\|alu_\|db_low\[1\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~11\|datad " "Node \"z80_\|alu_\|db_low\[1\]~11\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~11\|combout " "Node \"z80_\|alu_\|db_low\[1\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~12\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~12\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~12\|combout " "Node \"z80_\|alu_\|db_low\[1\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~10\|datac " "Node \"z80_\|alu_\|db\[1\]~10\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~10\|combout " "Node \"z80_\|alu_\|db\[1\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~24\|datab " "Node \"z80_\|alu_control_\|db\[1\]~24\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~24\|combout " "Node \"z80_\|alu_control_\|db\[1\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~26\|datab " "Node \"z80_\|alu_control_\|db\[1\]~26\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~26\|combout " "Node \"z80_\|alu_control_\|db\[1\]~26\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~10\|datad " "Node \"z80_\|bus_control_\|db\[1\]~10\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~10\|combout " "Node \"z80_\|bus_control_\|db\[1\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~11\|datab " "Node \"z80_\|bus_control_\|db\[1\]~11\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[1\]~11\|combout " "Node \"z80_\|bus_control_\|db\[1\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~25\|datab " "Node \"z80_\|alu_control_\|db\[1\]~25\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~25\|combout " "Node \"z80_\|alu_control_\|db\[1\]~25\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~26\|dataa " "Node \"z80_\|alu_control_\|db\[1\]~26\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~29\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~29\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~29\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~29\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~30\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~30\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~30\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~30\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~31\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~31\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~31\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~31\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~32\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~32\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~32\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~32\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[1\]~1\|datad " "Node \"z80_\|reg_file_\|db_lo_ds\[1\]~1\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_ds\[1\]~1\|combout " "Node \"z80_\|reg_file_\|db_lo_ds\[1\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[1\]~25\|dataa " "Node \"z80_\|alu_control_\|db\[1\]~25\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~4\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~4\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~4\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~5\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~5\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~5\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~6\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~6\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[1\]~6\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[1\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[1\]~32\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[1\]~32\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~8\|datad " "Node \"z80_\|alu_\|db\[1\]~8\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~8\|combout " "Node \"z80_\|alu_\|db\[1\]~8\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~10\|datad " "Node \"z80_\|alu_\|db\[1\]~10\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~12\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~12\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~12\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~14\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~14\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~15\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~15\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~21\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~21\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~21\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[1\]~8\|datac " "Node \"z80_\|alu_\|db\[1\]~8\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~0\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~0\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~0\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~1\|datab " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~1\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~1\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~1\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~3\|datab " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~3\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[1\]~3\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[1\]~3\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[1\]~21\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[1\]~21\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~11\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~11\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~21\|datad " "Node \"z80_\|alu_\|db_low\[2\]~21\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~21\|combout " "Node \"z80_\|alu_\|db_low\[2\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~22\|datab " "Node \"z80_\|alu_\|db_low\[2\]~22\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~2\|dataa " "Node \"z80_\|alu_\|db_low\[0\]~2\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~7\|dataa " "Node \"z80_\|alu_\|db_low\[1\]~7\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~7\|combout " "Node \"z80_\|alu_\|db_low\[1\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~9\|datab " "Node \"z80_\|alu_\|db_low\[1\]~9\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~9\|combout " "Node \"z80_\|alu_\|db_low\[1\]~9\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~12\|datad " "Node \"z80_\|alu_\|db_low\[1\]~12\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~2\|dataa " "Node \"z80_\|alu_\|db_high\[3\]~2\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~2\|combout " "Node \"z80_\|alu_\|db_high\[3\]~2\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~6\|datad " "Node \"z80_\|alu_\|db_high\[3\]~6\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|datac " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~2\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~46\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~46\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~46\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~46\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~47\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~47\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~47\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~47\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~50\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~50\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~50\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~50\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~51\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~51\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~51\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~51\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~52\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~52\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~52\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~52\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~10\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~10\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~10\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~11\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~11\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~11\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~12\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~12\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[3\]~12\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[3\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[3\]~52\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[3\]~52\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[3\]~34\|dataa " "Node \"z80_\|alu_control_\|db\[3\]~34\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~20\|dataa " "Node \"z80_\|alu_\|db\[3\]~20\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~14\|datad " "Node \"z80_\|alu_\|db_low\[3\]~14\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~44\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~44\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~44\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~44\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~46\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~46\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~46\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~46\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~47\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~47\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~47\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~47\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~48\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~48\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~48\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~48\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~10\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~10\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~10\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~10\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~11\|datad " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~11\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~11\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~12\|datac " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~12\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[3\]~12\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[3\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[3\]~48\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[3\]~48\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[3\]~19\|datac " "Node \"z80_\|alu_\|db\[3\]~19\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~21\|dataa " "Node \"z80_\|alu_\|db_low\[2\]~21\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~11\|datab " "Node \"z80_\|alu_\|db_high\[2\]~11\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~20\|datad " "Node \"z80_\|alu_\|db_high\[0\]~20\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~14\|datad " "Node \"z80_\|alu_\|db_high\[1\]~14\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~4\|datad " "Node \"z80_\|alu_\|db_low\[0\]~4\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|datab " "Node \"z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED~3\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~7\|datad " "Node \"z80_\|alu_\|db_low\[1\]~7\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~2\|datad " "Node \"z80_\|alu_\|db_high\[3\]~2\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~23\|dataa " "Node \"z80_\|alu_\|db_high\[0\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~13\|dataa " "Node \"z80_\|alu_\|db_low\[3\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~62\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~62\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~62\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~62\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~64\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~64\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~64\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~64\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~65\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~65\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~65\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~65\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~66\|datac " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~66\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~66\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~66\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~16\|datab " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~16\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~16\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~17\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~17\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~18\|datab " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~18\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[4\]~18\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[4\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[4\]~66\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[4\]~66\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[4\]~17\|datad " "Node \"z80_\|alu_\|db\[4\]~17\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~16\|datad " "Node \"z80_\|alu_\|db_high\[1\]~16\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~17\|dataa " "Node \"z80_\|alu_\|db_high\[1\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~15\|dataa " "Node \"z80_\|alu_control_\|db\[5\]~15\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~15\|combout " "Node \"z80_\|alu_control_\|db\[5\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[5\]~15\|datab " "Node \"z80_\|bus_control_\|db\[5\]~15\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[5\]~15\|combout " "Node \"z80_\|bus_control_\|db\[5\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[2\]~11\|datad " "Node \"z80_\|alu_\|db_high\[2\]~11\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[0\]~20\|datab " "Node \"z80_\|alu_\|db_high\[0\]~20\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[1\]~14\|datab " "Node \"z80_\|alu_\|db_high\[1\]~14\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[5\]~0\|datac " "Node \"z80_\|sw1_\|db_down\[5\]~0\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw1_\|db_down\[5\]~0\|combout " "Node \"z80_\|sw1_\|db_down\[5\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~14\|dataa " "Node \"z80_\|alu_control_\|db\[5\]~14\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~14\|combout " "Node \"z80_\|alu_control_\|db\[5\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~15\|datac " "Node \"z80_\|alu_control_\|db\[5\]~15\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~4\|datab " "Node \"z80_\|alu_\|db_low\[0\]~4\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[3\]~16\|datab " "Node \"z80_\|alu_\|db_low\[3\]~16\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[2\]~19\|datab " "Node \"z80_\|alu_\|db_low\[2\]~19\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~7\|datab " "Node \"z80_\|alu_\|db_low\[1\]~7\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_high\[3\]~2\|datab " "Node \"z80_\|alu_\|db_high\[3\]~2\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~66\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~66\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~66\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~66\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~67\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~67\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~67\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~67\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~70\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~70\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~70\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~70\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~71\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~71\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~71\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~71\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~72\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~72\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~72\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~72\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~16\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~16\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~16\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~17\|datad " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~17\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~17\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~18\|datac " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~18\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[5\]~18\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[5\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[5\]~72\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[5\]~72\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[5\]~14\|datac " "Node \"z80_\|alu_control_\|db\[5\]~14\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~23\|dataa " "Node \"z80_\|alu_\|db\[5\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~23\|combout " "Node \"z80_\|alu_\|db\[5\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~24\|dataa " "Node \"z80_\|alu_\|db\[5\]~24\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~53\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~53\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~53\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~53\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~55\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~55\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~55\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~55\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~56\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~56\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~56\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~56\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~57\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~57\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~57\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~57\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[5\]~23\|datab " "Node \"z80_\|alu_\|db\[5\]~23\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~13\|dataa " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~13\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~13\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~13\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~14\|datad " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~14\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~14\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~14\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~15\|datad " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~15\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[5\]~15\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[5\]~15\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[5\]~57\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[5\]~57\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~16\|datab " "Node \"z80_\|alu_control_\|db\[7\]~16\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~16\|combout " "Node \"z80_\|alu_control_\|db\[7\]~16\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~17\|datab " "Node \"z80_\|alu_control_\|db\[7\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~17\|combout " "Node \"z80_\|alu_control_\|db\[7\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~18\|datad " "Node \"z80_\|alu_control_\|db\[7\]~18\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~18\|combout " "Node \"z80_\|alu_control_\|db\[7\]~18\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~19\|dataa " "Node \"z80_\|alu_control_\|db\[7\]~19\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~19\|combout " "Node \"z80_\|alu_control_\|db\[7\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~5\|datad " "Node \"z80_\|bus_control_\|db\[7\]~5\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~5\|combout " "Node \"z80_\|bus_control_\|db\[7\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~7\|datab " "Node \"z80_\|bus_control_\|db\[7\]~7\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|bus_control_\|db\[7\]~7\|combout " "Node \"z80_\|bus_control_\|db\[7\]~7\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~18\|datab " "Node \"z80_\|alu_control_\|db\[7\]~18\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~88\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~88\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~88\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~88\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~89\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~89\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~89\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~89\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~90\|datac " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~90\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~90\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~90\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~91\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~91\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~91\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~91\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~22\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~22\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~22\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~22\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~23\|dataa " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~23\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~23\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~23\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~24\|datab " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~24\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_lo_as\[7\]~24\|combout " "Node \"z80_\|reg_file_\|db_lo_as\[7\]~24\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[7\]~91\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[7\]~91\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[7\]~17\|dataa " "Node \"z80_\|alu_control_\|db\[7\]~17\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~11\|datab " "Node \"z80_\|alu_\|db\[7\]~11\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~11\|combout " "Node \"z80_\|alu_\|db\[7\]~11\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~12\|datad " "Node \"z80_\|alu_\|db\[7\]~12\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~71\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~71\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~71\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~71\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~73\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~73\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~73\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~73\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~74\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~74\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~74\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~74\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~75\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~75\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~75\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~75\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[7\]~11\|datad " "Node \"z80_\|alu_\|db\[7\]~11\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~19\|datad " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~19\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~19\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~19\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~20\|datad " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~20\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~20\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~20\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~21\|datad " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~21\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[7\]~21\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[7\]~21\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[7\]~75\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[7\]~75\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~26\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~26\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~26\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~26\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~28\|datad " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~28\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~28\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~28\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~29\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~29\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~29\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~29\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~30\|datab " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~30\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~30\|combout " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~30\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db\[0\]~13\|datab " "Node \"z80_\|alu_\|db\[0\]~13\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~4\|datad " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~4\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~4\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~4\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~5\|datad " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~5\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~5\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~5\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~6\|datab " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~6\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|db_hi_as\[0\]~6\|combout " "Node \"z80_\|reg_file_\|db_hi_as\[0\]~6\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp1\[0\]~30\|dataa " "Node \"z80_\|reg_file_\|gdfx_temp1\[0\]~30\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[1\]~10\|datab " "Node \"z80_\|alu_\|db_low\[1\]~10\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_\|db_low\[0\]~3\|datad " "Node \"z80_\|alu_\|db_low\[0\]~3\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw2_\|db_up\[0\]~0\|datac " "Node \"z80_\|sw2_\|db_up\[0\]~0\|datac\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|sw2_\|db_up\[0\]~0\|combout " "Node \"z80_\|sw2_\|db_up\[0\]~0\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|alu_control_\|db\[0\]~9\|dataa " "Node \"z80_\|alu_control_\|db\[0\]~9\|dataa\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~12\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~12\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~12\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~12\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~17\|datab " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~17\|datab\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~17\|combout " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~17\|combout\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} { "Warning" "WSTA_SCC_NODE" "z80_\|reg_file_\|gdfx_temp0\[0\]~22\|datad " "Node \"z80_\|reg_file_\|gdfx_temp0\[0\]~22\|datad\"" { } { } 0 332126 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648904018723 ""} } { { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 87 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 90 -1 0 } } { "cpu/alu/alu_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_control.v" 96 -1 0 } } { "cpu/bus/bus_control.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/bus_control.v" 28 -1 0 } } { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 100 -1 0 } } { "cpu/alu/alu_mux_8.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_mux_8.v" 42 -1 0 } } { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 107 -1 0 } } { "cpu/alu/alu.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu.v" 106 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 91 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 85 -1 0 } } { "cpu/bus/data_switch_mask.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch_mask.v" 31 -1 0 } } { "cpu/registers/reg_file.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/registers/reg_file.v" 88 -1 0 } } { "cpu/alu/alu_bit_select.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/alu/alu_bit_select.v" 30 -1 0 } } { "cpu/bus/data_switch.v" "" { Text "/home/benny/work/fpga/spectrum/cpu/bus/data_switch.v" 30 -1 0 } } } 0 332125 "Found combinational loop of %1!d! nodes" 0 0 "Quartus II" 0 -1 1648904018723 ""} +{ "Critical Warning" "WSTA_SCC_LOOP_TOO_BIG" "517 " "Design contains combinational loop of 517 nodes. Estimating the delays through the loop." { } { } 1 332081 "Design contains combinational loop of %1!d! nodes. Estimating the delays through the loop." 0 0 "Quartus II" 0 -1 1648904018739 ""} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ula:ula_\|clocks:clocks_\|clk_cpu " "Node: ula:ula_\|clocks:clocks_\|clk_cpu was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1648904018770 "|spectrum|ula:ula_|clocks:clocks_|clk_cpu"} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "KEY\[1\] " "Node: KEY\[1\] was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1648904018771 "|spectrum|KEY[1]"} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648904018902 ""} +{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1648904018905 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1648904018933 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648904018970 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648904018970 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -18.425 " "Worst-case setup slack is -18.425" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648904018971 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648904018971 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -18.425 -546.891 CLOCK_50 " " -18.425 -546.891 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648904018971 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -6.923 -271.506 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " -6.923 -271.506 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648904018971 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.745 -42.191 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " -4.745 -42.191 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648904018971 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.915 -2.915 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " -2.915 -2.915 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648904018971 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648904018971 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.342 " "Worst-case hold slack is 0.342" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648904018976 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648904018976 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.342 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 0.342 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648904018976 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.342 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 0.342 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648904018976 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.357 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.357 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648904018976 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.517 0.000 CLOCK_50 " " 0.517 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648904018976 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648904018976 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -6.263 " "Worst-case recovery slack is -6.263" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648904018977 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648904018977 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -6.263 -464.840 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " -6.263 -464.840 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648904018977 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648904018977 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "removal 3.657 " "Worst-case removal slack is 3.657" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648904018978 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648904018978 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 3.657 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 3.657 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648904018978 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648904018978 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 9.488 " "Worst-case minimum pulse width slack is 9.488" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648904018979 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648904018979 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.488 0.000 CLOCK_50 " " 9.488 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648904018979 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 19.602 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 19.602 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648904018979 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 20.597 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 20.597 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648904018979 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 35.503 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 35.503 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648904018979 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648904018979 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1648904019104 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1648904019140 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1648904020052 ""} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ula:ula_\|clocks:clocks_\|clk_cpu " "Node: ula:ula_\|clocks:clocks_\|clk_cpu was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1648904020215 "|spectrum|ula:ula_|clocks:clocks_|clk_cpu"} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "KEY\[1\] " "Node: KEY\[1\] was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1648904020215 "|spectrum|KEY[1]"} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648904020217 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648904020233 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648904020233 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -17.572 " "Worst-case setup slack is -17.572" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648904020236 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648904020236 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -17.572 -524.603 CLOCK_50 " " -17.572 -524.603 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648904020236 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -6.192 -241.805 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " -6.192 -241.805 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648904020236 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.414 -39.436 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " -4.414 -39.436 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648904020236 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.786 -2.786 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " -2.786 -2.786 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648904020236 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648904020236 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.297 " "Worst-case hold slack is 0.297" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648904020243 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648904020243 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.297 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 0.297 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648904020243 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.298 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 0.298 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648904020243 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.311 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.311 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648904020243 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.467 0.000 CLOCK_50 " " 0.467 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648904020243 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648904020243 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -5.773 " "Worst-case recovery slack is -5.773" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648904020246 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648904020246 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -5.773 -427.930 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " -5.773 -427.930 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648904020246 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648904020246 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "removal 3.347 " "Worst-case removal slack is 3.347" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648904020249 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648904020249 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 3.347 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 3.347 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648904020249 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648904020249 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 9.489 " "Worst-case minimum pulse width slack is 9.489" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648904020252 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648904020252 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.489 0.000 CLOCK_50 " " 9.489 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648904020252 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 19.601 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 19.601 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648904020252 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 20.590 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 20.590 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648904020252 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 35.491 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 35.491 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648904020252 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648904020252 ""} +{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1648904020396 ""} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ula:ula_\|clocks:clocks_\|clk_cpu " "Node: ula:ula_\|clocks:clocks_\|clk_cpu was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1648904020671 "|spectrum|ula:ula_|clocks:clocks_|clk_cpu"} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "KEY\[1\] " "Node: KEY\[1\] was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1648904020671 "|spectrum|KEY[1]"} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648904020673 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648904020680 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648904020680 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -15.171 " "Worst-case setup slack is -15.171" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648904020685 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648904020685 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -15.171 -440.252 CLOCK_50 " " -15.171 -440.252 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648904020685 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.743 -163.399 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " -4.743 -163.399 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648904020685 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.815 -35.260 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " -3.815 -35.260 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648904020685 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.784 -2.784 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " -2.784 -2.784 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648904020685 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648904020685 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.112 " "Worst-case hold slack is 0.112" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648904020694 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648904020694 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.112 0.000 CLOCK_50 " " 0.112 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648904020694 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.177 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 0.177 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648904020694 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.178 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 0.178 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648904020694 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.186 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.186 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648904020694 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648904020694 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -4.728 " "Worst-case recovery slack is -4.728" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648904020699 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648904020699 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.728 -362.420 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " -4.728 -362.420 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648904020699 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648904020699 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "removal 2.503 " "Worst-case removal slack is 2.503" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648904020704 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648904020704 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 2.503 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 2.503 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648904020704 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648904020704 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 9.208 " "Worst-case minimum pulse width slack is 9.208" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648904020709 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648904020709 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.208 0.000 CLOCK_50 " " 9.208 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648904020709 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 19.609 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 19.609 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648904020709 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 20.600 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 20.600 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648904020709 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 35.535 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 35.535 0.000 ula_\|pll_\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648904020709 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648904020709 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1648904021256 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1648904021256 ""} +{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 538 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 538 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "440 " "Peak virtual memory: 440 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648904021493 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 2 15:53:41 2022 " "Processing ended: Sat Apr 2 15:53:41 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648904021493 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648904021493 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648904021493 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648904021493 ""} diff --git a/db/spectrum.sta.rdb b/db/spectrum.sta.rdb index 1bbdc89..6bd116e 100644 Binary files a/db/spectrum.sta.rdb and b/db/spectrum.sta.rdb differ diff --git a/db/spectrum.sta_cmp.6_slow_1200mv_85c.tdb b/db/spectrum.sta_cmp.6_slow_1200mv_85c.tdb index 2eb24bc..7c0f47b 100644 Binary files a/db/spectrum.sta_cmp.6_slow_1200mv_85c.tdb and b/db/spectrum.sta_cmp.6_slow_1200mv_85c.tdb differ diff --git a/db/spectrum.tiscmp.fast_1200mv_0c.ddb b/db/spectrum.tiscmp.fast_1200mv_0c.ddb index 964cd81..6b1516d 100644 Binary files a/db/spectrum.tiscmp.fast_1200mv_0c.ddb and b/db/spectrum.tiscmp.fast_1200mv_0c.ddb differ diff --git a/db/spectrum.tiscmp.slow_1200mv_0c.ddb b/db/spectrum.tiscmp.slow_1200mv_0c.ddb index 4eb861d..2a624a5 100644 Binary files a/db/spectrum.tiscmp.slow_1200mv_0c.ddb and b/db/spectrum.tiscmp.slow_1200mv_0c.ddb differ diff --git a/db/spectrum.tiscmp.slow_1200mv_85c.ddb b/db/spectrum.tiscmp.slow_1200mv_85c.ddb index 865cf09..3fc77fd 100644 Binary files a/db/spectrum.tiscmp.slow_1200mv_85c.ddb and b/db/spectrum.tiscmp.slow_1200mv_85c.ddb differ diff --git a/db/spectrum.vpr.ammdb b/db/spectrum.vpr.ammdb index 1f2e0e9..5cc339b 100644 Binary files a/db/spectrum.vpr.ammdb and b/db/spectrum.vpr.ammdb differ diff --git a/incremental_db/compiled_partitions/spectrum.root_partition.cmp.ammdb b/incremental_db/compiled_partitions/spectrum.root_partition.cmp.ammdb index d33caa1..0886a9b 100644 Binary files a/incremental_db/compiled_partitions/spectrum.root_partition.cmp.ammdb and b/incremental_db/compiled_partitions/spectrum.root_partition.cmp.ammdb differ diff --git a/incremental_db/compiled_partitions/spectrum.root_partition.cmp.cdb b/incremental_db/compiled_partitions/spectrum.root_partition.cmp.cdb index 11d8ad5..86f9a90 100644 Binary files a/incremental_db/compiled_partitions/spectrum.root_partition.cmp.cdb and b/incremental_db/compiled_partitions/spectrum.root_partition.cmp.cdb differ diff --git a/incremental_db/compiled_partitions/spectrum.root_partition.cmp.hdb b/incremental_db/compiled_partitions/spectrum.root_partition.cmp.hdb index 25ab810..65e166b 100644 Binary files a/incremental_db/compiled_partitions/spectrum.root_partition.cmp.hdb and b/incremental_db/compiled_partitions/spectrum.root_partition.cmp.hdb differ diff --git a/incremental_db/compiled_partitions/spectrum.root_partition.cmp.rcfdb b/incremental_db/compiled_partitions/spectrum.root_partition.cmp.rcfdb index da66c56..6fd2e14 100644 Binary files a/incremental_db/compiled_partitions/spectrum.root_partition.cmp.rcfdb and b/incremental_db/compiled_partitions/spectrum.root_partition.cmp.rcfdb differ diff --git a/incremental_db/compiled_partitions/spectrum.root_partition.map.cdb b/incremental_db/compiled_partitions/spectrum.root_partition.map.cdb index 428a347..914861f 100644 Binary files a/incremental_db/compiled_partitions/spectrum.root_partition.map.cdb and b/incremental_db/compiled_partitions/spectrum.root_partition.map.cdb differ diff --git a/incremental_db/compiled_partitions/spectrum.root_partition.map.dpi b/incremental_db/compiled_partitions/spectrum.root_partition.map.dpi index 33139a1..e5bf3ac 100644 Binary files a/incremental_db/compiled_partitions/spectrum.root_partition.map.dpi and b/incremental_db/compiled_partitions/spectrum.root_partition.map.dpi differ diff --git a/incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.cdb b/incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.cdb index 67df2f3..4bc6c57 100644 Binary files a/incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.cdb and b/incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.cdb differ diff --git a/incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.hdb b/incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.hdb index 110b4e6..5c6046d 100644 Binary files a/incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.hdb and b/incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.hdb differ diff --git a/incremental_db/compiled_partitions/spectrum.root_partition.map.hdb b/incremental_db/compiled_partitions/spectrum.root_partition.map.hdb index 9b6563d..ca759bc 100644 Binary files a/incremental_db/compiled_partitions/spectrum.root_partition.map.hdb and b/incremental_db/compiled_partitions/spectrum.root_partition.map.hdb differ diff --git a/incremental_db/compiled_partitions/spectrum.root_partition.map.kpt b/incremental_db/compiled_partitions/spectrum.root_partition.map.kpt index d4f8b41..5c1e489 100644 Binary files a/incremental_db/compiled_partitions/spectrum.root_partition.map.kpt and b/incremental_db/compiled_partitions/spectrum.root_partition.map.kpt differ diff --git a/output_files/spectrum.asm.rpt b/output_files/spectrum.asm.rpt index 0b03803..5445141 100644 --- a/output_files/spectrum.asm.rpt +++ b/output_files/spectrum.asm.rpt @@ -1,5 +1,5 @@ Assembler report for spectrum -Fri Apr 1 18:55:43 2022 +Sat Apr 2 15:53:36 2022 Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition @@ -37,7 +37,7 @@ applicable agreement for further details. +---------------------------------------------------------------+ ; Assembler Summary ; +-----------------------+---------------------------------------+ -; Assembler Status ; Successful - Fri Apr 1 18:55:43 2022 ; +; Assembler Status ; Successful - Sat Apr 2 15:53:36 2022 ; ; Revision Name ; spectrum ; ; Top-level Entity Name ; spectrum ; ; Family ; Cyclone IV E ; @@ -162,8 +162,8 @@ Default Value : On ; Option ; Setting ; +----------------+-----------------------+ ; Device ; EP4CE22F17C6 ; -; JTAG usercode ; 0x0056423F ; -; Checksum ; 0x0056423F ; +; JTAG usercode ; 0x0056105B ; +; Checksum ; 0x0056105B ; +----------------+-----------------------+ @@ -173,13 +173,13 @@ Default Value : On Info: ******************************************************************* Info: Running Quartus II 32-bit Assembler Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition - Info: Processing started: Fri Apr 1 18:55:41 2022 + Info: Processing started: Sat Apr 2 15:53:34 2022 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum Info (115031): Writing out detailed assembly data for power analysis Info (115030): Assembler is generating device programming files Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings Info: Peak virtual memory: 385 megabytes - Info: Processing ended: Fri Apr 1 18:55:43 2022 + Info: Processing ended: Sat Apr 2 15:53:36 2022 Info: Elapsed time: 00:00:02 Info: Total CPU time (on all processors): 00:00:02 diff --git a/output_files/spectrum.done b/output_files/spectrum.done index a426016..b77c984 100644 --- a/output_files/spectrum.done +++ b/output_files/spectrum.done @@ -1 +1 @@ -Fri Apr 1 18:55:53 2022 +Sat Apr 2 15:53:46 2022 diff --git a/output_files/spectrum.eda.rpt b/output_files/spectrum.eda.rpt index 32ae12e..e399dd9 100644 --- a/output_files/spectrum.eda.rpt +++ b/output_files/spectrum.eda.rpt @@ -1,5 +1,5 @@ EDA Netlist Writer report for spectrum -Fri Apr 1 18:55:53 2022 +Sat Apr 2 15:53:46 2022 Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition @@ -36,7 +36,7 @@ applicable agreement for further details. +-------------------------------------------------------------------+ ; EDA Netlist Writer Summary ; +---------------------------+---------------------------------------+ -; EDA Netlist Writer Status ; Successful - Fri Apr 1 18:55:53 2022 ; +; EDA Netlist Writer Status ; Successful - Sat Apr 2 15:53:46 2022 ; ; Revision Name ; spectrum ; ; Top-level Entity Name ; spectrum ; ; Family ; Cyclone IV E ; @@ -88,7 +88,7 @@ applicable agreement for further details. Info: ******************************************************************* Info: Running Quartus II 32-bit EDA Netlist Writer Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition - Info: Processing started: Fri Apr 1 18:55:50 2022 + Info: Processing started: Sat Apr 2 15:53:43 2022 Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum Info (204019): Generated file spectrum_6_1200mv_85c_slow.vo in folder "/home/benny/work/fpga/spectrum/simulation/modelsim/" for EDA simulation tool Info (204019): Generated file spectrum_6_1200mv_0c_slow.vo in folder "/home/benny/work/fpga/spectrum/simulation/modelsim/" for EDA simulation tool @@ -100,7 +100,7 @@ Info (204019): Generated file spectrum_min_1200mv_0c_v_fast.sdo in folder "/home Info (204019): Generated file spectrum_v.sdo in folder "/home/benny/work/fpga/spectrum/simulation/modelsim/" for EDA simulation tool Info: Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings Info: Peak virtual memory: 380 megabytes - Info: Processing ended: Fri Apr 1 18:55:53 2022 + Info: Processing ended: Sat Apr 2 15:53:46 2022 Info: Elapsed time: 00:00:03 Info: Total CPU time (on all processors): 00:00:03 diff --git a/output_files/spectrum.fit.rpt b/output_files/spectrum.fit.rpt index 21ded4a..7dfd444 100644 --- a/output_files/spectrum.fit.rpt +++ b/output_files/spectrum.fit.rpt @@ -1,5 +1,5 @@ Fitter report for spectrum -Fri Apr 1 18:55:39 2022 +Sat Apr 2 15:53:32 2022 Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition @@ -77,15 +77,15 @@ applicable agreement for further details. +---------------------------------------------------------------------------------+ ; Fitter Summary ; +------------------------------------+--------------------------------------------+ -; Fitter Status ; Successful - Fri Apr 1 18:55:39 2022 ; +; Fitter Status ; Successful - Sat Apr 2 15:53:32 2022 ; ; Quartus II 32-bit Version ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ; ; Revision Name ; spectrum ; ; Top-level Entity Name ; spectrum ; ; Family ; Cyclone IV E ; ; Device ; EP4CE22F17C6 ; ; Timing Models ; Final ; -; Total logic elements ; 2,396 / 22,320 ( 11 % ) ; -; Total combinational functions ; 2,272 / 22,320 ( 10 % ) ; +; Total logic elements ; 2,376 / 22,320 ( 11 % ) ; +; Total combinational functions ; 2,258 / 22,320 ( 10 % ) ; ; Dedicated logic registers ; 591 / 22,320 ( 3 % ) ; ; Total registers ; 600 ; ; Total pins ; 75 / 154 ( 49 % ) ; @@ -1710,14 +1710,14 @@ From Design Partitions [A] : From Rapid Recompile [B] : Type : -- Requested -Total [A + B] : 0.00 % ( 0 / 3097 ) -From Design Partitions [A] : 0.00 % ( 0 / 3097 ) -From Rapid Recompile [B] : 0.00 % ( 0 / 3097 ) +Total [A + B] : 0.00 % ( 0 / 3083 ) +From Design Partitions [A] : 0.00 % ( 0 / 3083 ) +From Rapid Recompile [B] : 0.00 % ( 0 / 3083 ) Type : -- Achieved -Total [A + B] : 0.00 % ( 0 / 3097 ) -From Design Partitions [A] : 0.00 % ( 0 / 3097 ) -From Rapid Recompile [B] : 0.00 % ( 0 / 3097 ) +Total [A + B] : 0.00 % ( 0 / 3083 ) +From Design Partitions [A] : 0.00 % ( 0 / 3083 ) +From Rapid Recompile [B] : 0.00 % ( 0 / 3083 ) Type : Total [A + B] : @@ -1768,7 +1768,7 @@ Contents : hard_block:auto_generated_inst ; Incremental Compilation Placement Preservation ; +--------------------------------------------------------------------------------+ Partition Name : Top -Preservation Achieved : 0.00 % ( 0 / 3083 ) +Preservation Achieved : 0.00 % ( 0 / 3069 ) Preservation Level Used : N/A Netlist Type Used : Source File Preservation Method : N/A @@ -1795,26 +1795,26 @@ The pin-out file can be found in /home/benny/work/fpga/spectrum/output_files/spe +---------------------------------------------+----------------------------+ ; Resource ; Usage ; +---------------------------------------------+----------------------------+ -; Total logic elements ; 2,396 / 22,320 ( 11 % ) ; -; -- Combinational with no register ; 1805 ; -; -- Register only ; 124 ; -; -- Combinational with a register ; 467 ; +; Total logic elements ; 2,376 / 22,320 ( 11 % ) ; +; -- Combinational with no register ; 1785 ; +; -- Register only ; 118 ; +; -- Combinational with a register ; 473 ; ; ; ; ; Logic element usage by number of LUT inputs ; ; -; -- 4 input functions ; 1640 ; -; -- 3 input functions ; 385 ; -; -- <=2 input functions ; 247 ; -; -- Register only ; 124 ; +; -- 4 input functions ; 1637 ; +; -- 3 input functions ; 372 ; +; -- <=2 input functions ; 249 ; +; -- Register only ; 118 ; ; ; ; ; Logic elements by mode ; ; -; -- normal mode ; 2219 ; +; -- normal mode ; 2205 ; ; -- arithmetic mode ; 53 ; ; ; ; ; Total registers* ; 600 / 23,018 ( 3 % ) ; ; -- Dedicated logic registers ; 591 / 22,320 ( 3 % ) ; ; -- I/O registers ; 9 / 698 ( 1 % ) ; ; ; ; -; Total LABs: partially or completely used ; 185 / 1,395 ( 13 % ) ; +; Total LABs: partially or completely used ; 176 / 1,395 ( 13 % ) ; ; Virtual pins ; 0 ; ; I/O pins ; 75 / 154 ( 49 % ) ; ; -- Clock pins ; 5 / 7 ( 71 % ) ; @@ -1832,10 +1832,10 @@ The pin-out file can be found in /home/benny/work/fpga/spectrum/output_files/spe ; ASMI blocks ; 0 / 1 ( 0 % ) ; ; Impedance control blocks ; 0 / 4 ( 0 % ) ; ; Average interconnect usage (total/H/V) ; 5% / 5% / 6% ; -; Peak interconnect usage (total/H/V) ; 29% / 26% / 33% ; +; Peak interconnect usage (total/H/V) ; 35% / 31% / 42% ; ; Maximum fan-out ; 435 ; ; Highest non-global fan-out ; 69 ; -; Total fan-out ; 11636 ; +; Total fan-out ; 11589 ; ; Average fan-out ; 3.66 ; +---------------------------------------------+----------------------------+ * Register count does not include registers inside RAM blocks or DSP blocks. @@ -1854,19 +1854,19 @@ Top : hard_block:auto_generated_inst : Statistic : Total logic elements -Top : 2396 / 22320 ( 11 % ) +Top : 2376 / 22320 ( 11 % ) hard_block:auto_generated_inst : 0 / 22320 ( 0 % ) Statistic : -- Combinational with no register -Top : 1805 +Top : 1785 hard_block:auto_generated_inst : 0 Statistic : -- Register only -Top : 124 +Top : 118 hard_block:auto_generated_inst : 0 Statistic : -- Combinational with a register -Top : 467 +Top : 473 hard_block:auto_generated_inst : 0 Statistic : @@ -1878,19 +1878,19 @@ Top : hard_block:auto_generated_inst : Statistic : -- 4 input functions -Top : 1640 +Top : 1637 hard_block:auto_generated_inst : 0 Statistic : -- 3 input functions -Top : 385 +Top : 372 hard_block:auto_generated_inst : 0 Statistic : -- <=2 input functions -Top : 247 +Top : 249 hard_block:auto_generated_inst : 0 Statistic : -- Register only -Top : 124 +Top : 118 hard_block:auto_generated_inst : 0 Statistic : @@ -1902,7 +1902,7 @@ Top : hard_block:auto_generated_inst : Statistic : -- normal mode -Top : 2219 +Top : 2205 hard_block:auto_generated_inst : 0 Statistic : -- arithmetic mode @@ -1930,7 +1930,7 @@ Top : hard_block:auto_generated_inst : Statistic : Total LABs: partially or completely used -Top : 185 / 1395 ( 13 % ) +Top : 176 / 1395 ( 13 % ) hard_block:auto_generated_inst : 0 / 1395 ( 0 % ) Statistic : @@ -1982,16 +1982,16 @@ Top : hard_block:auto_generated_inst : Statistic : -- Input Connections -Top : 197 +Top : 213 hard_block:auto_generated_inst : 1 Statistic : -- Registered Input Connections -Top : 194 +Top : 210 hard_block:auto_generated_inst : 0 Statistic : -- Output Connections Top : 3 -hard_block:auto_generated_inst : 195 +hard_block:auto_generated_inst : 211 Statistic : -- Registered Output Connections Top : 0 @@ -2006,8 +2006,8 @@ Top : hard_block:auto_generated_inst : Statistic : -- Total Connections -Top : 11643 -hard_block:auto_generated_inst : 205 +Top : 11596 +hard_block:auto_generated_inst : 221 Statistic : -- Registered Connections Top : 2921 @@ -2023,10 +2023,10 @@ hard_block:auto_generated_inst : Statistic : -- Top Top : 4 -hard_block:auto_generated_inst : 196 +hard_block:auto_generated_inst : 212 Statistic : -- hard_block:auto_generated_inst -Top : 196 +Top : 212 hard_block:auto_generated_inst : 0 Statistic : @@ -2135,7 +2135,7 @@ I/O Bank : 3 X coordinate : 27 Y coordinate : 0 Z coordinate : 21 -Combinational Fan-Out : 51 +Combinational Fan-Out : 35 Registered Fan-Out : 0 Global : yes Input Register : no @@ -7356,7 +7356,7 @@ SDC Pin Name : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] ; Fitter Resource Utilization by Entity ; +--------------------------------------------------------------------------------+ Compilation Hierarchy Node : |spectrum -Logic Cells : 2396 (98) +Logic Cells : 2376 (84) Dedicated Logic Registers : 591 (0) I/O Registers : 9 (9) Memory Bits : 524288 @@ -7366,9 +7366,9 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 75 Virtual Pins : 0 -LUT-Only LCs : 1805 (96) -Register-Only LCs : 124 (0) -LUT/Register LCs : 467 (2) +LUT-Only LCs : 1785 (81) +Register-Only LCs : 118 (0) +LUT/Register LCs : 473 (5) Full Hierarchy Name : |spectrum Library Name : work @@ -7441,7 +7441,7 @@ Full Hierarchy Name : |spectrum|ram16:ram0|altsyncram:altsyncram_componen Library Name : work Compilation Hierarchy Node : |ram32:ram1| -Logic Cells : 19 (0) +Logic Cells : 27 (0) Dedicated Logic Registers : 4 (0) I/O Registers : 0 (0) Memory Bits : 262144 @@ -7451,14 +7451,14 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 15 (0) -Register-Only LCs : 0 (0) -LUT/Register LCs : 4 (0) +LUT-Only LCs : 23 (0) +Register-Only LCs : 1 (0) +LUT/Register LCs : 3 (0) Full Hierarchy Name : |spectrum|ram32:ram1 Library Name : work Compilation Hierarchy Node : |altsyncram:altsyncram_component| -Logic Cells : 19 (0) +Logic Cells : 27 (0) Dedicated Logic Registers : 4 (0) I/O Registers : 0 (0) Memory Bits : 262144 @@ -7468,14 +7468,14 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 15 (0) -Register-Only LCs : 0 (0) -LUT/Register LCs : 4 (0) +LUT-Only LCs : 23 (0) +Register-Only LCs : 1 (0) +LUT/Register LCs : 3 (0) Full Hierarchy Name : |spectrum|ram32:ram1|altsyncram:altsyncram_component Library Name : work Compilation Hierarchy Node : |altsyncram_g9i1:auto_generated| -Logic Cells : 19 (4) +Logic Cells : 27 (4) Dedicated Logic Registers : 4 (4) I/O Registers : 0 (0) Memory Bits : 262144 @@ -7485,9 +7485,9 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 15 (0) -Register-Only LCs : 0 (0) -LUT/Register LCs : 4 (3) +LUT-Only LCs : 23 (0) +Register-Only LCs : 1 (1) +LUT/Register LCs : 3 (2) Full Hierarchy Name : |spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated Library Name : work @@ -7526,7 +7526,7 @@ Full Hierarchy Name : |spectrum|ram32:ram1|altsyncram:altsyncram_componen Library Name : work Compilation Hierarchy Node : |mux_6nb:mux2| -Logic Cells : 8 (8) +Logic Cells : 16 (16) Dedicated Logic Registers : 0 (0) I/O Registers : 0 (0) Memory Bits : 0 @@ -7536,7 +7536,7 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 7 (7) +LUT-Only LCs : 15 (15) Register-Only LCs : 0 (0) LUT/Register LCs : 1 (1) Full Hierarchy Name : |spectrum|ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|mux_6nb:mux2 @@ -7594,7 +7594,7 @@ Full Hierarchy Name : |spectrum|rom0:rom|altsyncram:altsyncram_component| Library Name : work Compilation Hierarchy Node : |ula:ula_| -Logic Cells : 458 (9) +Logic Cells : 461 (9) Dedicated Logic Registers : 223 (7) I/O Registers : 0 (0) Memory Bits : 0 @@ -7604,9 +7604,9 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 235 (2) -Register-Only LCs : 36 (3) -LUT/Register LCs : 187 (3) +LUT-Only LCs : 237 (1) +Register-Only LCs : 37 (2) +LUT/Register LCs : 187 (6) Full Hierarchy Name : |spectrum|ula:ula_ Library Name : work @@ -7628,7 +7628,7 @@ Full Hierarchy Name : |spectrum|ula:ula_|clocks:clocks_ Library Name : work Compilation Hierarchy Node : |i2c_loader:i2c_loader_| -Logic Cells : 82 (82) +Logic Cells : 81 (81) Dedicated Logic Registers : 34 (34) I/O Registers : 0 (0) Memory Bits : 0 @@ -7638,7 +7638,7 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 48 (48) +LUT-Only LCs : 47 (47) Register-Only LCs : 0 (0) LUT/Register LCs : 34 (34) Full Hierarchy Name : |spectrum|ula:ula_|i2c_loader:i2c_loader_ @@ -7655,9 +7655,9 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 27 (27) +LUT-Only LCs : 28 (28) Register-Only LCs : 1 (1) -LUT/Register LCs : 41 (41) +LUT/Register LCs : 40 (40) Full Hierarchy Name : |spectrum|ula:ula_|i2s_intf:i2s_intf_ Library Name : work @@ -7724,8 +7724,8 @@ DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 LUT-Only LCs : 7 (7) -Register-Only LCs : 7 (7) -LUT/Register LCs : 17 (17) +Register-Only LCs : 9 (9) +LUT/Register LCs : 15 (15) Full Hierarchy Name : |spectrum|ula:ula_|ps2_keyboard:ps2_keyboard_ Library Name : work @@ -7747,7 +7747,7 @@ Full Hierarchy Name : |spectrum|ula:ula_|video:video_ Library Name : work Compilation Hierarchy Node : |zx_keyboard:zx_keyboard_| -Logic Cells : 150 (150) +Logic Cells : 151 (151) Dedicated Logic Registers : 43 (43) I/O Registers : 0 (0) Memory Bits : 0 @@ -7757,14 +7757,14 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 99 (99) +LUT-Only LCs : 102 (102) Register-Only LCs : 0 (0) -LUT/Register LCs : 51 (51) +LUT/Register LCs : 49 (49) Full Hierarchy Name : |spectrum|ula:ula_|zx_keyboard:zx_keyboard_ Library Name : work Compilation Hierarchy Node : |z80_top_direct_n:z80_| -Logic Cells : 1822 (2) +Logic Cells : 1805 (2) Dedicated Logic Registers : 362 (1) I/O Registers : 0 (0) Memory Bits : 0 @@ -7774,14 +7774,14 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 1457 (1) -Register-Only LCs : 87 (0) -LUT/Register LCs : 278 (2) +LUT-Only LCs : 1442 (1) +Register-Only LCs : 79 (0) +LUT/Register LCs : 284 (2) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_ Library Name : work Compilation Hierarchy Node : |address_latch:address_latch_| -Logic Cells : 57 (26) +Logic Cells : 49 (19) Dedicated Logic Registers : 16 (16) I/O Registers : 0 (0) Memory Bits : 0 @@ -7791,14 +7791,14 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 41 (10) -Register-Only LCs : 7 (7) -LUT/Register LCs : 9 (8) +LUT-Only LCs : 33 (3) +Register-Only LCs : 3 (3) +LUT/Register LCs : 13 (13) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|address_latch:address_latch_ Library Name : work Compilation Hierarchy Node : |inc_dec:b2v_inst_inc_dec| -Logic Cells : 32 (14) +Logic Cells : 30 (13) Dedicated Logic Registers : 0 (0) I/O Registers : 0 (0) Memory Bits : 0 @@ -7808,14 +7808,14 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 31 (13) +LUT-Only LCs : 30 (13) Register-Only LCs : 0 (0) -LUT/Register LCs : 1 (1) +LUT/Register LCs : 0 (0) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec Library Name : work Compilation Hierarchy Node : |inc_dec_2bit:b2v_dual_adder_0| -Logic Cells : 4 (4) +Logic Cells : 3 (3) Dedicated Logic Registers : 0 (0) I/O Registers : 0 (0) Memory Bits : 0 @@ -7825,7 +7825,7 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 4 (4) +LUT-Only LCs : 3 (3) Register-Only LCs : 0 (0) LUT/Register LCs : 0 (0) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|inc_dec_2bit:b2v_dual_adder_0 @@ -7927,14 +7927,14 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 13 (13) +LUT-Only LCs : 14 (14) Register-Only LCs : 0 (0) -LUT/Register LCs : 19 (19) +LUT/Register LCs : 18 (18) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|address_pins:address_pins_ Library Name : work Compilation Hierarchy Node : |alu:alu_| -Logic Cells : 130 (95) +Logic Cells : 131 (93) Dedicated Logic Registers : 20 (20) I/O Registers : 0 (0) Memory Bits : 0 @@ -7944,9 +7944,9 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 107 (74) -Register-Only LCs : 0 (0) -LUT/Register LCs : 23 (3) +LUT-Only LCs : 107 (71) +Register-Only LCs : 1 (1) +LUT/Register LCs : 23 (5) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu:alu_ Library Name : work @@ -7968,7 +7968,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu:alu_|alu_bit_se Library Name : work Compilation Hierarchy Node : |alu_core:b2v_core| -Logic Cells : 20 (0) +Logic Cells : 21 (0) Dedicated Logic Registers : 0 (0) I/O Registers : 0 (0) Memory Bits : 0 @@ -7978,9 +7978,9 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 18 (0) +LUT-Only LCs : 21 (0) Register-Only LCs : 0 (0) -LUT/Register LCs : 2 (0) +LUT/Register LCs : 0 (0) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core Library Name : work @@ -8002,7 +8002,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu:alu_|alu_core:b Library Name : work Compilation Hierarchy Node : |alu_slice:b2v_alu_slice_bit_1| -Logic Cells : 4 (4) +Logic Cells : 5 (5) Dedicated Logic Registers : 0 (0) I/O Registers : 0 (0) Memory Bits : 0 @@ -8012,7 +8012,7 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 4 (4) +LUT-Only LCs : 5 (5) Register-Only LCs : 0 (0) LUT/Register LCs : 0 (0) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_1 @@ -8029,9 +8029,9 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 5 (5) +LUT-Only LCs : 6 (6) Register-Only LCs : 0 (0) -LUT/Register LCs : 1 (1) +LUT/Register LCs : 0 (0) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_2 Library Name : work @@ -8046,9 +8046,9 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 4 (4) +LUT-Only LCs : 5 (5) Register-Only LCs : 0 (0) -LUT/Register LCs : 1 (1) +LUT/Register LCs : 0 (0) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_3 Library Name : work @@ -8172,7 +8172,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu_control:alu_con Library Name : work Compilation Hierarchy Node : |alu_flags:alu_flags_| -Logic Cells : 63 (63) +Logic Cells : 60 (60) Dedicated Logic Registers : 10 (10) I/O Registers : 0 (0) Memory Bits : 0 @@ -8182,7 +8182,7 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 53 (53) +LUT-Only LCs : 50 (50) Register-Only LCs : 0 (0) LUT/Register LCs : 10 (10) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu_flags:alu_flags_ @@ -8199,9 +8199,9 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 14 (14) +LUT-Only LCs : 11 (11) Register-Only LCs : 0 (0) -LUT/Register LCs : 4 (4) +LUT/Register LCs : 7 (7) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|bus_control:bus_control_ Library Name : work @@ -8216,14 +8216,14 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 1 (1) +LUT-Only LCs : 0 (0) Register-Only LCs : 1 (1) -LUT/Register LCs : 1 (1) +LUT/Register LCs : 2 (2) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|clk_delay:clk_delay_ Library Name : work Compilation Hierarchy Node : |data_pins:data_pins_| -Logic Cells : 9 (9) +Logic Cells : 10 (10) Dedicated Logic Registers : 8 (8) I/O Registers : 0 (0) Memory Bits : 0 @@ -8233,7 +8233,7 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 1 (1) +LUT-Only LCs : 2 (2) Register-Only LCs : 0 (0) LUT/Register LCs : 8 (8) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|data_pins:data_pins_ @@ -8257,7 +8257,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|data_switch:sw2_ Library Name : work Compilation Hierarchy Node : |data_switch_mask:sw1_| -Logic Cells : 2 (2) +Logic Cells : 3 (3) Dedicated Logic Registers : 0 (0) I/O Registers : 0 (0) Memory Bits : 0 @@ -8267,7 +8267,7 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 2 (2) +LUT-Only LCs : 3 (3) Register-Only LCs : 0 (0) LUT/Register LCs : 0 (0) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|data_switch_mask:sw1_ @@ -8291,7 +8291,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|decode_state:decode Library Name : work Compilation Hierarchy Node : |execute:execute_| -Logic Cells : 933 (933) +Logic Cells : 926 (926) Dedicated Logic Registers : 0 (0) I/O Registers : 0 (0) Memory Bits : 0 @@ -8301,9 +8301,9 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 923 (923) +LUT-Only LCs : 920 (920) Register-Only LCs : 0 (0) -LUT/Register LCs : 10 (10) +LUT/Register LCs : 6 (6) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|execute:execute_ Library Name : work @@ -8318,8 +8318,8 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 7 (7) -Register-Only LCs : 1 (1) +LUT-Only LCs : 6 (6) +Register-Only LCs : 2 (2) LUT/Register LCs : 7 (7) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|interrupts:interrupts_ Library Name : work @@ -8336,13 +8336,13 @@ DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 LUT-Only LCs : 0 (0) -Register-Only LCs : 3 (3) -LUT/Register LCs : 5 (5) +Register-Only LCs : 0 (0) +LUT/Register LCs : 8 (8) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|ir:ir_ Library Name : work Compilation Hierarchy Node : |memory_ifc:memory_ifc_| -Logic Cells : 22 (22) +Logic Cells : 23 (23) Dedicated Logic Registers : 20 (20) I/O Registers : 0 (0) Memory Bits : 0 @@ -8352,7 +8352,7 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 2 (2) +LUT-Only LCs : 3 (3) Register-Only LCs : 6 (6) LUT/Register LCs : 14 (14) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|memory_ifc:memory_ifc_ @@ -8410,7 +8410,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_control:reg_con Library Name : work Compilation Hierarchy Node : |reg_file:reg_file_| -Logic Cells : 350 (128) +Logic Cells : 350 (125) Dedicated Logic Registers : 224 (0) I/O Registers : 0 (0) Memory Bits : 0 @@ -8420,9 +8420,9 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 126 (126) -Register-Only LCs : 68 (0) -LUT/Register LCs : 156 (147) +LUT-Only LCs : 126 (125) +Register-Only LCs : 65 (0) +LUT/Register LCs : 159 (148) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_ Library Name : work @@ -8461,7 +8461,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_| Library Name : work Compilation Hierarchy Node : |reg_latch:b2v_latch_af_hi| -Logic Cells : 8 (8) +Logic Cells : 9 (9) Dedicated Logic Registers : 8 (8) I/O Registers : 0 (0) Memory Bits : 0 @@ -8471,7 +8471,7 @@ DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 0 (0) +LUT-Only LCs : 1 (1) Register-Only LCs : 0 (0) LUT/Register LCs : 8 (8) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_af_hi @@ -8489,8 +8489,8 @@ DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 LUT-Only LCs : 0 (0) -Register-Only LCs : 6 (6) -LUT/Register LCs : 2 (2) +Register-Only LCs : 7 (7) +LUT/Register LCs : 1 (1) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_af_lo Library Name : work @@ -8557,8 +8557,8 @@ DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 LUT-Only LCs : 0 (0) -Register-Only LCs : 5 (5) -LUT/Register LCs : 3 (3) +Register-Only LCs : 6 (6) +LUT/Register LCs : 2 (2) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_bc_lo Library Name : work @@ -8625,8 +8625,8 @@ DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 LUT-Only LCs : 0 (0) -Register-Only LCs : 6 (6) -LUT/Register LCs : 2 (2) +Register-Only LCs : 7 (7) +LUT/Register LCs : 1 (1) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_de_lo Library Name : work @@ -8676,8 +8676,8 @@ DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 LUT-Only LCs : 0 (0) -Register-Only LCs : 8 (8) -LUT/Register LCs : 0 (0) +Register-Only LCs : 6 (6) +LUT/Register LCs : 2 (2) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_hl_hi Library Name : work @@ -8693,8 +8693,8 @@ DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 LUT-Only LCs : 0 (0) -Register-Only LCs : 7 (7) -LUT/Register LCs : 1 (1) +Register-Only LCs : 4 (4) +LUT/Register LCs : 4 (4) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_hl_lo Library Name : work @@ -8795,8 +8795,8 @@ DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 LUT-Only LCs : 0 (0) -Register-Only LCs : 5 (5) -LUT/Register LCs : 3 (3) +Register-Only LCs : 4 (4) +LUT/Register LCs : 4 (4) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_iy_lo Library Name : work @@ -8846,8 +8846,8 @@ DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 LUT-Only LCs : 0 (0) -Register-Only LCs : 1 (1) -LUT/Register LCs : 7 (7) +Register-Only LCs : 0 (0) +LUT/Register LCs : 8 (8) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_sp_hi Library Name : work @@ -8880,8 +8880,8 @@ DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 LUT-Only LCs : 0 (0) -Register-Only LCs : 0 (0) -LUT/Register LCs : 8 (8) +Register-Only LCs : 2 (2) +LUT/Register LCs : 6 (6) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_wz_hi Library Name : work @@ -8897,8 +8897,8 @@ DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 LUT-Only LCs : 0 (0) -Register-Only LCs : 1 (1) -LUT/Register LCs : 7 (7) +Register-Only LCs : 0 (0) +LUT/Register LCs : 8 (8) Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_|reg_latch:b2v_latch_wz_lo Library Name : work @@ -9466,7 +9466,7 @@ TCOE : -- Name : I2C_SDAT Pin Type : Bidir Pad to Core 0 : (0) 0 ps -Pad to Core 1 : -- +Pad to Core 1 : (0) 0 ps Pad to Input Register : -- TCO : (0) 0 ps TCOE : -- @@ -9489,16 +9489,16 @@ TCOE : -- Name : raw_loader_in Pin Type : Input -Pad to Core 0 : (6) 1314 ps -Pad to Core 1 : (0) 0 ps +Pad to Core 0 : (0) 0 ps +Pad to Core 1 : (6) 1314 ps Pad to Input Register : -- TCO : -- TCOE : -- Name : KEY[0] Pin Type : Input -Pad to Core 0 : (0) 0 ps -Pad to Core 1 : -- +Pad to Core 0 : -- +Pad to Core 1 : (0) 0 ps Pad to Input Register : -- TCO : -- TCOE : -- @@ -9570,11 +9570,11 @@ Pad To Core Index : 0 Setting : 0 Source Pin / Fanout : - ula:ula_|i2c_loader:i2c_loader_|nbyte[0]~1 -Pad To Core Index : 0 +Pad To Core Index : 1 Setting : 0 Source Pin / Fanout : - ula:ula_|i2c_loader:i2c_loader_|nbyte[1]~5 -Pad To Core Index : 0 +Pad To Core Index : 1 Setting : 0 Source Pin / Fanout : SW[1] @@ -9589,16 +9589,16 @@ Source Pin / Fanout : raw_loader_in Pad To Core Index : Setting : -Source Pin / Fanout : - D[6]~86 -Pad To Core Index : 1 +Source Pin / Fanout : - D[6]~69 +Pad To Core Index : 0 Setting : 0 Source Pin / Fanout : - ula:ula_|beep~0 -Pad To Core Index : 0 +Pad To Core Index : 1 Setting : 6 Source Pin / Fanout : - LED[3]~output -Pad To Core Index : 1 +Pad To Core Index : 0 Setting : 0 Source Pin / Fanout : KEY[0] @@ -9606,7 +9606,7 @@ Pad To Core Index : Setting : Source Pin / Fanout : - reset -Pad To Core Index : 0 +Pad To Core Index : 1 Setting : 0 Source Pin / Fanout : CLOCK_50 @@ -9657,7 +9657,7 @@ Setting : 0 +--------------------------------------------------------------------------------+ Name : CLOCK_50 Location : PIN_R8 -Fan-Out : 34 +Fan-Out : 18 Usage : Clock Global : yes Global Resource Used : Global Clock @@ -9673,8 +9673,8 @@ Global Resource Used : -- Global Line Name : -- Enable Signal Source Name : -- -Name : D[0]~107 -Location : LCCOMB_X31_Y12_N10 +Name : D[0]~84 +Location : LCCOMB_X29_Y11_N12 Fan-Out : 10 Usage : Output enable Global : no @@ -9691,8 +9691,8 @@ Global Resource Used : -- Global Line Name : -- Enable Signal Source Name : -- -Name : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|decode_jsa:decode2|eq_node[0]~0 -Location : LCCOMB_X32_Y14_N2 +Name : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|decode_jsa:decode2|eq_node[0]~1 +Location : LCCOMB_X29_Y11_N10 Fan-Out : 8 Usage : Write enable Global : no @@ -9700,8 +9700,8 @@ Global Resource Used : -- Global Line Name : -- Enable Signal Source Name : -- -Name : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|decode_jsa:decode2|eq_node[1]~1 -Location : LCCOMB_X32_Y14_N10 +Name : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|decode_jsa:decode2|eq_node[1]~0 +Location : LCCOMB_X29_Y11_N22 Fan-Out : 8 Usage : Write enable Global : no @@ -9710,7 +9710,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_f8a:rden_decode|w_anode284w[2]~0 -Location : LCCOMB_X32_Y14_N22 +Location : LCCOMB_X23_Y10_N10 Fan-Out : 8 Usage : Clock enable Global : no @@ -9719,7 +9719,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3|w_anode223w[2] -Location : LCCOMB_X32_Y14_N12 +Location : LCCOMB_X29_Y11_N4 Fan-Out : 8 Usage : Write enable Global : no @@ -9728,7 +9728,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3|w_anode223w[2]~0 -Location : LCCOMB_X32_Y14_N18 +Location : LCCOMB_X23_Y10_N0 Fan-Out : 8 Usage : Clock enable Global : no @@ -9737,7 +9737,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3|w_anode236w[2] -Location : LCCOMB_X32_Y14_N8 +Location : LCCOMB_X29_Y11_N0 Fan-Out : 8 Usage : Write enable Global : no @@ -9746,7 +9746,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3|w_anode244w[2] -Location : LCCOMB_X32_Y14_N24 +Location : LCCOMB_X29_Y11_N24 Fan-Out : 8 Usage : Write enable Global : no @@ -9755,7 +9755,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3|w_anode244w[2]~0 -Location : LCCOMB_X32_Y14_N26 +Location : LCCOMB_X24_Y10_N12 Fan-Out : 8 Usage : Clock enable Global : no @@ -9764,7 +9764,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3|w_anode252w[2] -Location : LCCOMB_X32_Y14_N20 +Location : LCCOMB_X29_Y11_N18 Fan-Out : 8 Usage : Write enable Global : no @@ -9773,7 +9773,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3|w_anode252w[2]~0 -Location : LCCOMB_X32_Y14_N6 +Location : LCCOMB_X24_Y10_N30 Fan-Out : 8 Usage : Clock enable Global : no @@ -9782,16 +9782,16 @@ Global Line Name : -- Enable Signal Source Name : -- Name : reset -Location : LCCOMB_X52_Y14_N4 +Location : LCCOMB_X52_Y17_N6 Fan-Out : 149 Usage : Async. clear, Async. load Global : yes Global Resource Used : Global Clock -Global Line Name : GCLK5 +Global Line Name : GCLK8 Enable Signal Source Name : -- Name : ula:ula_|always0~3 -Location : LCCOMB_X31_Y12_N20 +Location : LCCOMB_X29_Y11_N26 Fan-Out : 7 Usage : Clock enable Global : no @@ -9800,16 +9800,16 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ula:ula_|clocks:clocks_|clk_cpu -Location : FF_X25_Y33_N11 +Location : FF_X25_Y33_N5 Fan-Out : 435 Usage : Clock Global : yes Global Resource Used : Global Clock -Global Line Name : GCLK14 +Global Line Name : GCLK12 Enable Signal Source Name : -- Name : ula:ula_|i2c_loader:i2c_loader_|WideAnd0 -Location : LCCOMB_X4_Y24_N8 +Location : LCCOMB_X1_Y24_N30 Fan-Out : 17 Usage : Clock enable Global : no @@ -9818,7 +9818,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ula:ula_|i2c_loader:i2c_loader_|nbit[0]~4 -Location : LCCOMB_X1_Y24_N4 +Location : LCCOMB_X2_Y23_N0 Fan-Out : 3 Usage : Clock enable Global : no @@ -9827,7 +9827,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]~3 -Location : LCCOMB_X1_Y23_N24 +Location : LCCOMB_X2_Y23_N8 Fan-Out : 2 Usage : Clock enable Global : no @@ -9836,16 +9836,16 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ula:ula_|i2c_loader:i2c_loader_|phase[0] -Location : FF_X1_Y23_N5 -Fan-Out : 23 +Location : FF_X3_Y23_N1 +Fan-Out : 22 Usage : Sync. load Global : no Global Resource Used : -- Global Line Name : -- Enable Signal Source Name : -- -Name : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]~8 -Location : LCCOMB_X1_Y24_N10 +Name : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]~7 +Location : LCCOMB_X3_Y23_N8 Fan-Out : 2 Usage : Clock enable Global : no @@ -9853,8 +9853,8 @@ Global Resource Used : -- Global Line Name : -- Enable Signal Source Name : -- -Name : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]~11 -Location : LCCOMB_X2_Y24_N24 +Name : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]~10 +Location : LCCOMB_X3_Y23_N12 Fan-Out : 6 Usage : Clock enable Global : no @@ -9863,7 +9863,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ula:ula_|i2c_loader:i2c_loader_|state.Start -Location : FF_X1_Y24_N31 +Location : FF_X3_Y23_N27 Fan-Out : 20 Usage : Sync. clear, Sync. load Global : no @@ -9872,7 +9872,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]~18 -Location : LCCOMB_X2_Y23_N8 +Location : LCCOMB_X5_Y23_N16 Fan-Out : 5 Usage : Clock enable Global : no @@ -9881,7 +9881,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ula:ula_|i2s_intf:i2s_intf_|Equal0~2 -Location : LCCOMB_X29_Y23_N30 +Location : LCCOMB_X24_Y32_N30 Fan-Out : 37 Usage : Sync. load Global : no @@ -9890,7 +9890,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]~15 -Location : LCCOMB_X31_Y22_N28 +Location : LCCOMB_X25_Y31_N22 Fan-Out : 5 Usage : Clock enable Global : no @@ -9899,7 +9899,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]~2 -Location : LCCOMB_X31_Y22_N30 +Location : LCCOMB_X25_Y31_N28 Fan-Out : 17 Usage : Clock enable Global : no @@ -9909,7 +9909,7 @@ Enable Signal Source Name : -- Name : ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] Location : PLL_4 -Fan-Out : 110 +Fan-Out : 126 Usage : Clock Global : yes Global Resource Used : Global Clock @@ -9935,7 +9935,7 @@ Global Line Name : GCLK19 Enable Signal Source Name : -- Name : ula:ula_|ps2_keyboard:ps2_keyboard_|clk_edge -Location : FF_X20_Y26_N5 +Location : FF_X16_Y26_N29 Fan-Out : 6 Usage : Clock enable Global : no @@ -9944,7 +9944,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ula:ula_|ps2_keyboard:ps2_keyboard_|scan_code_ready -Location : FF_X26_Y21_N9 +Location : FF_X21_Y10_N5 Fan-Out : 7 Usage : Clock enable Global : no @@ -9953,7 +9953,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[0]~0 -Location : LCCOMB_X26_Y21_N6 +Location : LCCOMB_X21_Y10_N26 Fan-Out : 9 Usage : Clock enable Global : no @@ -9962,7 +9962,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ula:ula_|video:video_|Decoder0~0 -Location : LCCOMB_X34_Y31_N12 +Location : LCCOMB_X35_Y31_N2 Fan-Out : 16 Usage : Clock enable Global : no @@ -9971,7 +9971,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ula:ula_|video:video_|Decoder0~1 -Location : LCCOMB_X34_Y31_N10 +Location : LCCOMB_X35_Y31_N24 Fan-Out : 8 Usage : Clock enable Global : no @@ -9980,7 +9980,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ula:ula_|video:video_|Decoder0~2 -Location : LCCOMB_X34_Y31_N8 +Location : LCCOMB_X35_Y31_N10 Fan-Out : 8 Usage : Clock enable Global : no @@ -9989,7 +9989,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ula:ula_|video:video_|Equal3~1 -Location : LCCOMB_X37_Y33_N18 +Location : LCCOMB_X35_Y32_N10 Fan-Out : 16 Usage : Clock enable Global : no @@ -9998,7 +9998,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ula:ula_|video:video_|vram_address[9]~1 -Location : LCCOMB_X34_Y31_N14 +Location : LCCOMB_X35_Y31_N16 Fan-Out : 4 Usage : Clock enable Global : no @@ -10007,7 +10007,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : ula:ula_|video:video_|vram_address~0 -Location : LCCOMB_X34_Y31_N4 +Location : LCCOMB_X35_Y31_N26 Fan-Out : 8 Usage : Clock enable Global : no @@ -10016,7 +10016,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|address_pins:address_pins_|abus[13]~20 -Location : LCCOMB_X32_Y14_N0 +Location : LCCOMB_X23_Y10_N6 Fan-Out : 45 Usage : Clock enable Global : no @@ -10025,7 +10025,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|alu:alu_|alu_mux_2z:b2v_op1_latch_mux_high|ena~0 -Location : LCCOMB_X36_Y10_N2 +Location : LCCOMB_X32_Y17_N8 Fan-Out : 4 Usage : Clock enable Global : no @@ -10034,7 +10034,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|alu:alu_|alu_mux_3z:b2v_op1_latch_mux_low|ena -Location : LCCOMB_X36_Y10_N12 +Location : LCCOMB_X32_Y17_N30 Fan-Out : 4 Usage : Clock enable Global : no @@ -10043,7 +10043,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|alu:alu_|alu_mux_3z:b2v_op2_latch_mux_high|ena -Location : LCCOMB_X37_Y10_N16 +Location : LCCOMB_X32_Y18_N0 Fan-Out : 8 Usage : Clock enable Global : no @@ -10052,7 +10052,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|clk_delay:clk_delay_|hold_clk_iorq -Location : LCCOMB_X43_Y15_N20 +Location : LCCOMB_X30_Y12_N12 Fan-Out : 24 Usage : Clock enable Global : no @@ -10061,7 +10061,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|data_pins:data_pins_|SYNTHESIZED_WIRE_2 -Location : LCCOMB_X32_Y13_N16 +Location : LCCOMB_X30_Y13_N8 Fan-Out : 8 Usage : Clock enable Global : no @@ -10070,7 +10070,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|execute:execute_|ctl_al_we~12 -Location : LCCOMB_X41_Y18_N4 +Location : LCCOMB_X24_Y12_N0 Fan-Out : 16 Usage : Clock enable Global : no @@ -10079,8 +10079,8 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low -Location : LCCOMB_X39_Y11_N30 -Fan-Out : 17 +Location : LCCOMB_X26_Y16_N14 +Fan-Out : 15 Usage : Clock enable Global : no Global Resource Used : -- @@ -10088,7 +10088,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|execute:execute_|ctl_apin_mux2~0 -Location : LCCOMB_X31_Y16_N0 +Location : LCCOMB_X29_Y18_N8 Fan-Out : 16 Usage : Sync. load Global : no @@ -10097,7 +10097,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|execute:execute_|ctl_flags_sz_we~8 -Location : LCCOMB_X37_Y9_N22 +Location : LCCOMB_X28_Y18_N12 Fan-Out : 2 Usage : Clock enable Global : no @@ -10105,8 +10105,8 @@ Global Resource Used : -- Global Line Name : -- Enable Signal Source Name : -- -Name : z80_top_direct_n:z80_|execute:execute_|ctl_flags_xy_we~15 -Location : LCCOMB_X36_Y11_N20 +Name : z80_top_direct_n:z80_|execute:execute_|ctl_flags_xy_we~18 +Location : LCCOMB_X28_Y18_N0 Fan-Out : 2 Usage : Clock enable Global : no @@ -10115,7 +10115,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|execute:execute_|ctl_im_we -Location : LCCOMB_X35_Y13_N16 +Location : LCCOMB_X27_Y19_N14 Fan-Out : 3 Usage : Clock enable Global : no @@ -10124,7 +10124,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~13 -Location : LCCOMB_X35_Y12_N8 +Location : LCCOMB_X24_Y17_N18 Fan-Out : 8 Usage : Clock enable Global : no @@ -10133,7 +10133,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|execute:execute_|ctl_state_ixiy_we~2 -Location : LCCOMB_X37_Y15_N0 +Location : LCCOMB_X26_Y16_N0 Fan-Out : 2 Usage : Clock enable Global : no @@ -10142,7 +10142,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|execute:execute_|ctl_state_tbl_we~8 -Location : LCCOMB_X41_Y17_N2 +Location : LCCOMB_X29_Y13_N2 Fan-Out : 2 Usage : Clock enable Global : no @@ -10151,16 +10151,16 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|fpga_reset -Location : FF_X25_Y33_N1 +Location : FF_X1_Y16_N17 Fan-Out : 2 Usage : Async. clear Global : yes Global Resource Used : Global Clock -Global Line Name : GCLK12 +Global Line Name : GCLK2 Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|interrupts:interrupts_|SYNTHESIZED_WIRE_12 -Location : LCCOMB_X32_Y15_N28 +Location : LCCOMB_X27_Y11_N24 Fan-Out : 2 Usage : Async. clear Global : yes @@ -10169,7 +10169,7 @@ Global Line Name : GCLK16 Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|interrupts:interrupts_|SYNTHESIZED_WIRE_15 -Location : LCCOMB_X38_Y18_N12 +Location : LCCOMB_X28_Y13_N20 Fan-Out : 1 Usage : Async. clear Global : no @@ -10178,7 +10178,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|interrupts:interrupts_|SYNTHESIZED_WIRE_9 -Location : LCCOMB_X32_Y15_N2 +Location : LCCOMB_X27_Y13_N4 Fan-Out : 1 Usage : Async. clear Global : no @@ -10187,7 +10187,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|interrupts:interrupts_|test1~3 -Location : LCCOMB_X43_Y15_N26 +Location : LCCOMB_X27_Y13_N22 Fan-Out : 2 Usage : Clock enable Global : no @@ -10195,8 +10195,8 @@ Global Resource Used : -- Global Line Name : -- Enable Signal Source Name : -- -Name : z80_top_direct_n:z80_|pin_control:pin_control_|bus_ab_pin_we~3 -Location : LCCOMB_X31_Y16_N2 +Name : z80_top_direct_n:z80_|pin_control:pin_control_|bus_ab_pin_we~1 +Location : LCCOMB_X28_Y12_N26 Fan-Out : 16 Usage : Clock enable Global : no @@ -10205,7 +10205,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_29 -Location : LCCOMB_X28_Y11_N12 +Location : LCCOMB_X36_Y16_N18 Fan-Out : 8 Usage : Clock enable Global : no @@ -10214,7 +10214,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_31 -Location : LCCOMB_X28_Y10_N10 +Location : LCCOMB_X31_Y13_N14 Fan-Out : 8 Usage : Clock enable Global : no @@ -10223,7 +10223,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_33 -Location : LCCOMB_X28_Y14_N26 +Location : LCCOMB_X36_Y15_N2 Fan-Out : 8 Usage : Clock enable Global : no @@ -10232,7 +10232,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_35 -Location : LCCOMB_X28_Y14_N8 +Location : LCCOMB_X31_Y13_N0 Fan-Out : 8 Usage : Clock enable Global : no @@ -10241,7 +10241,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_37~0 -Location : LCCOMB_X29_Y15_N16 +Location : LCCOMB_X32_Y16_N22 Fan-Out : 8 Usage : Clock enable Global : no @@ -10250,7 +10250,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_39~0 -Location : LCCOMB_X30_Y12_N8 +Location : LCCOMB_X32_Y16_N12 Fan-Out : 8 Usage : Clock enable Global : no @@ -10259,7 +10259,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_41~0 -Location : LCCOMB_X29_Y15_N6 +Location : LCCOMB_X32_Y16_N20 Fan-Out : 8 Usage : Clock enable Global : no @@ -10268,7 +10268,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_43~0 -Location : LCCOMB_X30_Y12_N14 +Location : LCCOMB_X32_Y16_N18 Fan-Out : 8 Usage : Clock enable Global : no @@ -10277,7 +10277,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_45 -Location : LCCOMB_X26_Y13_N4 +Location : LCCOMB_X36_Y15_N20 Fan-Out : 8 Usage : Clock enable Global : no @@ -10286,7 +10286,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_47 -Location : LCCOMB_X30_Y13_N14 +Location : LCCOMB_X30_Y11_N22 Fan-Out : 8 Usage : Clock enable Global : no @@ -10295,7 +10295,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_49 -Location : LCCOMB_X26_Y13_N6 +Location : LCCOMB_X36_Y16_N24 Fan-Out : 8 Usage : Clock enable Global : no @@ -10304,7 +10304,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_51 -Location : LCCOMB_X30_Y13_N28 +Location : LCCOMB_X30_Y11_N16 Fan-Out : 8 Usage : Clock enable Global : no @@ -10313,7 +10313,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_53 -Location : LCCOMB_X26_Y13_N16 +Location : LCCOMB_X37_Y14_N2 Fan-Out : 8 Usage : Clock enable Global : no @@ -10322,7 +10322,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_55 -Location : LCCOMB_X26_Y13_N26 +Location : LCCOMB_X30_Y12_N18 Fan-Out : 8 Usage : Clock enable Global : no @@ -10331,7 +10331,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_57 -Location : LCCOMB_X26_Y13_N18 +Location : LCCOMB_X36_Y16_N26 Fan-Out : 8 Usage : Clock enable Global : no @@ -10340,7 +10340,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_59 -Location : LCCOMB_X26_Y13_N0 +Location : LCCOMB_X30_Y12_N26 Fan-Out : 8 Usage : Clock enable Global : no @@ -10349,7 +10349,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_61 -Location : LCCOMB_X28_Y15_N16 +Location : LCCOMB_X35_Y12_N20 Fan-Out : 8 Usage : Clock enable Global : no @@ -10358,7 +10358,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_63 -Location : LCCOMB_X31_Y15_N28 +Location : LCCOMB_X35_Y12_N12 Fan-Out : 8 Usage : Clock enable Global : no @@ -10367,7 +10367,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_65~0 -Location : LCCOMB_X30_Y12_N4 +Location : LCCOMB_X32_Y16_N4 Fan-Out : 8 Usage : Clock enable Global : no @@ -10376,7 +10376,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_67~0 -Location : LCCOMB_X30_Y12_N16 +Location : LCCOMB_X32_Y16_N28 Fan-Out : 8 Usage : Clock enable Global : no @@ -10385,7 +10385,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_69 -Location : LCCOMB_X27_Y12_N12 +Location : LCCOMB_X36_Y16_N8 Fan-Out : 8 Usage : Clock enable Global : no @@ -10394,7 +10394,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_71 -Location : LCCOMB_X30_Y10_N24 +Location : LCCOMB_X31_Y12_N10 Fan-Out : 8 Usage : Clock enable Global : no @@ -10403,7 +10403,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_73 -Location : LCCOMB_X28_Y15_N10 +Location : LCCOMB_X35_Y12_N22 Fan-Out : 8 Usage : Clock enable Global : no @@ -10412,7 +10412,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_75 -Location : LCCOMB_X31_Y15_N18 +Location : LCCOMB_X35_Y12_N10 Fan-Out : 8 Usage : Clock enable Global : no @@ -10421,7 +10421,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_77~0 -Location : LCCOMB_X30_Y12_N22 +Location : LCCOMB_X32_Y16_N2 Fan-Out : 8 Usage : Clock enable Global : no @@ -10430,7 +10430,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_79~0 -Location : LCCOMB_X30_Y12_N6 +Location : LCCOMB_X32_Y16_N14 Fan-Out : 8 Usage : Clock enable Global : no @@ -10439,7 +10439,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_81 -Location : LCCOMB_X28_Y15_N4 +Location : LCCOMB_X35_Y12_N30 Fan-Out : 8 Usage : Clock enable Global : no @@ -10448,7 +10448,7 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_83 -Location : LCCOMB_X31_Y15_N30 +Location : LCCOMB_X35_Y12_N0 Fan-Out : 8 Usage : Clock enable Global : no @@ -10457,8 +10457,8 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|resets:resets_|SYNTHESIZED_WIRE_12 -Location : FF_X35_Y13_N11 -Fan-Out : 67 +Location : FF_X52_Y17_N13 +Fan-Out : 68 Usage : Output enable Global : no Global Resource Used : -- @@ -10466,12 +10466,12 @@ Global Line Name : -- Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|resets:resets_|SYNTHESIZED_WIRE_12 -Location : FF_X35_Y13_N11 +Location : FF_X52_Y17_N13 Fan-Out : 72 Usage : Async. clear Global : yes Global Resource Used : Global Clock -Global Line Name : GCLK7 +Global Line Name : GCLK9 Enable Signal Source Name : -- +--------------------------------------------------------------------------------+ @@ -10482,31 +10482,31 @@ Enable Signal Source Name : -- +--------------------------------------------------------------------------------+ Name : CLOCK_50 Location : PIN_R8 -Fan-Out : 34 -Fan-Out Using Intentional Clock Skew : 1 +Fan-Out : 18 +Fan-Out Using Intentional Clock Skew : 0 Global Resource Used : Global Clock Global Line Name : GCLK15 Enable Signal Source Name : -- Name : reset -Location : LCCOMB_X52_Y14_N4 +Location : LCCOMB_X52_Y17_N6 Fan-Out : 149 Fan-Out Using Intentional Clock Skew : 0 Global Resource Used : Global Clock -Global Line Name : GCLK5 +Global Line Name : GCLK8 Enable Signal Source Name : -- Name : ula:ula_|clocks:clocks_|clk_cpu -Location : FF_X25_Y33_N11 +Location : FF_X25_Y33_N5 Fan-Out : 435 Fan-Out Using Intentional Clock Skew : 0 Global Resource Used : Global Clock -Global Line Name : GCLK14 +Global Line Name : GCLK12 Enable Signal Source Name : -- Name : ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] Location : PLL_4 -Fan-Out : 110 +Fan-Out : 126 Fan-Out Using Intentional Clock Skew : 17 Global Resource Used : Global Clock Global Line Name : GCLK18 @@ -10523,21 +10523,21 @@ Enable Signal Source Name : -- Name : ula:ula_|pll:pll_|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[2] Location : PLL_4 Fan-Out : 82 -Fan-Out Using Intentional Clock Skew : 33 +Fan-Out Using Intentional Clock Skew : 26 Global Resource Used : Global Clock Global Line Name : GCLK19 Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|fpga_reset -Location : FF_X25_Y33_N1 +Location : FF_X1_Y16_N17 Fan-Out : 2 Fan-Out Using Intentional Clock Skew : 0 Global Resource Used : Global Clock -Global Line Name : GCLK12 +Global Line Name : GCLK2 Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|interrupts:interrupts_|SYNTHESIZED_WIRE_12 -Location : LCCOMB_X32_Y15_N28 +Location : LCCOMB_X27_Y11_N24 Fan-Out : 2 Fan-Out Using Intentional Clock Skew : 0 Global Resource Used : Global Clock @@ -10545,11 +10545,11 @@ Global Line Name : GCLK16 Enable Signal Source Name : -- Name : z80_top_direct_n:z80_|resets:resets_|SYNTHESIZED_WIRE_12 -Location : FF_X35_Y13_N11 +Location : FF_X52_Y17_N13 Fan-Out : 72 Fan-Out Using Intentional Clock Skew : 0 Global Resource Used : Global Clock -Global Line Name : GCLK7 +Global Line Name : GCLK9 Enable Signal Source Name : -- +--------------------------------------------------------------------------------+ @@ -10560,15 +10560,14 @@ Enable Signal Source Name : -- +---------------------------------------------------------------------------------------------------------------------------------+---------+ ; Name ; Fan-Out ; +---------------------------------------------------------------------------------------------------------------------------------+---------+ -; z80_top_direct_n:z80_|ir:ir_|opcode[3] ; 69 ; -; z80_top_direct_n:z80_|address_pins:address_pins_|abus[8]~18 ; 69 ; -; z80_top_direct_n:z80_|address_pins:address_pins_|abus[9]~17 ; 69 ; -; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_M1_ff ; 68 ; -; z80_top_direct_n:z80_|address_pins:address_pins_|abus[10]~24 ; 68 ; -; z80_top_direct_n:z80_|address_pins:address_pins_|abus[12]~21 ; 68 ; -; z80_top_direct_n:z80_|address_pins:address_pins_|abus[11]~19 ; 68 ; -; z80_top_direct_n:z80_|address_pins:address_pins_|abus[0]~16 ; 68 ; -; z80_top_direct_n:z80_|resets:resets_|SYNTHESIZED_WIRE_12 ; 66 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|abus[12]~21 ; 69 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|abus[11]~19 ; 69 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|abus[0]~16 ; 69 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|abus[9]~17 ; 68 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|abus[10]~24 ; 67 ; +; z80_top_direct_n:z80_|ir:ir_|opcode[3] ; 67 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|abus[8]~18 ; 67 ; +; z80_top_direct_n:z80_|resets:resets_|SYNTHESIZED_WIRE_12 ; 67 ; ; z80_top_direct_n:z80_|address_pins:address_pins_|abus[7]~31 ; 64 ; ; z80_top_direct_n:z80_|address_pins:address_pins_|abus[6]~30 ; 64 ; ; z80_top_direct_n:z80_|address_pins:address_pins_|abus[5]~29 ; 64 ; @@ -10576,86 +10575,89 @@ Enable Signal Source Name : -- ; z80_top_direct_n:z80_|address_pins:address_pins_|abus[3]~27 ; 64 ; ; z80_top_direct_n:z80_|address_pins:address_pins_|abus[2]~26 ; 64 ; ; z80_top_direct_n:z80_|address_pins:address_pins_|abus[1]~25 ; 64 ; -; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T1_ff ; 59 ; -; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T2_ff ; 59 ; -; z80_top_direct_n:z80_|ir:ir_|opcode[5] ; 58 ; +; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T2_ff ; 62 ; +; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_M1_ff ; 61 ; +; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T1_ff ; 58 ; +; z80_top_direct_n:z80_|ir:ir_|opcode[5] ; 57 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_eval_cond~0 ; 54 ; ; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T3_ff ; 53 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_eval_cond~0 ; 52 ; +; z80_top_direct_n:z80_|ir:ir_|opcode[0] ; 52 ; ; z80_top_direct_n:z80_|nM1_int~2 ; 51 ; -; z80_top_direct_n:z80_|ir:ir_|opcode[0] ; 51 ; -; z80_top_direct_n:z80_|execute:execute_|ixy_d~5 ; 47 ; +; z80_top_direct_n:z80_|execute:execute_|ixy_d~5 ; 45 ; ; z80_top_direct_n:z80_|address_pins:address_pins_|abus[13]~20 ; 45 ; -; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_M2_ff ; 44 ; -; z80_top_direct_n:z80_|execute:execute_|ixy_d~7 ; 42 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_we~6 ; 41 ; -; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T4_ff ; 41 ; -; ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[2] ; 39 ; -; ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[3] ; 39 ; -; z80_top_direct_n:z80_|execute:execute_|ixy_d~6 ; 39 ; -; z80_top_direct_n:z80_|ir:ir_|opcode[4] ; 39 ; +; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T4_ff ; 44 ; +; z80_top_direct_n:z80_|execute:execute_|ixy_d~7 ; 43 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_we~8 ; 42 ; +; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_M2_ff ; 42 ; +; ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[2] ; 41 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal6~0 ; 40 ; +; z80_top_direct_n:z80_|execute:execute_|ixy_d~6 ; 40 ; +; ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[3] ; 38 ; ; ula:ula_|zx_keyboard:zx_keyboard_|released ; 38 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal6~0 ; 37 ; +; z80_top_direct_n:z80_|ir:ir_|opcode[4] ; 38 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~2 ; 38 ; +; ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[4] ; 37 ; ; ula:ula_|i2s_intf:i2s_intf_|Equal0~2 ; 37 ; -; ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[1] ; 36 ; -; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_M3_ff ; 36 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~8 ; 36 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~4 ; 36 ; -; ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[0] ; 35 ; -; ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[4] ; 35 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo_1M1T3_3 ; 35 ; -; z80_top_direct_n:z80_|ir:ir_|opcode[2] ; 35 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~22 ; 36 ; +; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_M4_ff ; 35 ; +; ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[1] ; 34 ; ; ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[6] ; 34 ; -; ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[5] ; 33 ; +; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_M3_ff ; 34 ; +; ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[0] ; 33 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo_1M1T3_3 ; 33 ; +; z80_top_direct_n:z80_|ir:ir_|opcode[2] ; 33 ; +; ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[5] ; 32 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal13~0 ; 32 ; ; z80_top_direct_n:z80_|ir:ir_|opcode[1] ; 31 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~36 ; 30 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal33~0 ; 30 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~4 ; 30 ; -; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_M4_ff ; 30 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal13~0 ; 29 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~6 ; 27 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal11~0 ; 25 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal55~0 ; 25 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mWrite~2 ; 25 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~4 ; 29 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~34 ; 28 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal33~0 ; 28 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|abus[14]~23 ; 27 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~4 ; 26 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal11~0 ; 26 ; +; z80_top_direct_n:z80_|sequencer:sequencer_|M5 ; 25 ; ; ~GND ; 24 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~43 ; 24 ; ; z80_top_direct_n:z80_|resets:resets_|SYNTHESIZED_WIRE_11 ; 24 ; ; z80_top_direct_n:z80_|clk_delay:clk_delay_|hold_clk_iorq ; 24 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal10~0 ; 24 ; -; ula:ula_|i2c_loader:i2c_loader_|phase[0] ; 23 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~46 ; 23 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal13~2 ; 23 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal55~0 ; 24 ; ; ula:ula_|i2c_loader:i2c_loader_|state.Data ; 23 ; -; z80_top_direct_n:z80_|execute:execute_|ixy_d~9 ; 22 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_shift_oe~14 ; 22 ; +; ula:ula_|i2c_loader:i2c_loader_|phase[0] ; 22 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal10~0 ; 22 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal13~2 ; 22 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal9~1 ; 22 ; +; z80_top_direct_n:z80_|ir:ir_|opcode[7] ; 22 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[1]~31 ; 21 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal21~1 ; 21 ; -; z80_top_direct_n:z80_|sequencer:sequencer_|M5 ; 21 ; +; z80_top_direct_n:z80_|execute:execute_|ixy_d~9 ; 21 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_shift_oe~14 ; 21 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~3 ; 21 ; +; z80_top_direct_n:z80_|ir:ir_|opcode[6] ; 21 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mWrite~17 ; 20 ; ; ula:ula_|i2c_loader:i2c_loader_|state.Start ; 20 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[0]~35 ; 20 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal47~0 ; 20 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~5 ; 20 ; -; z80_top_direct_n:z80_|ir:ir_|opcode[7] ; 20 ; -; z80_top_direct_n:z80_|ir:ir_|opcode[6] ; 19 ; -; z80_top_direct_n:z80_|address_pins:address_pins_|abus[14]~23 ; 19 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mWrite~16 ; 18 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal63~0 ; 20 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal33~1 ; 20 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mWrite~4 ; 20 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal47~0 ; 19 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_sw_4u~6 ; 18 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[0]~38 ; 18 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[0]~35 ; 18 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_bus_db_we~7 ; 18 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_bus_inc_oe~41 ; 18 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal63~0 ; 18 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~10 ; 18 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal3~1 ; 18 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_bus_inc_oe~43 ; 18 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~9 ; 18 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal21~1 ; 18 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~8 ; 18 ; ; Equal2~1 ; 18 ; ; ula:ula_|i2c_loader:i2c_loader_|WideAnd0 ; 17 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low ; 17 ; ; ula:ula_|video:video_|vram_address[10] ; 17 ; ; ula:ula_|zx_keyboard:zx_keyboard_|extended ; 17 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~11 ; 17 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~12 ; 17 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~11 ; 17 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal6~1 ; 17 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal33~1 ; 17 ; +; z80_top_direct_n:z80_|decode_state:decode_state_|use_ixiy ; 17 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal19~0 ; 17 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal34~0 ; 17 ; +; z80_top_direct_n:z80_|interrupts:interrupts_|in_nmi_ALTERA_SYNTHESIZED ; 17 ; ; ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]~2 ; 17 ; -; z80_top_direct_n:z80_|pin_control:pin_control_|bus_ab_pin_we~3 ; 16 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_al_we~12 ; 16 ; ; ula:ula_|video:video_|vram_address[12] ; 16 ; ; ula:ula_|video:video_|vram_address[11] ; 16 ; @@ -10669,31 +10671,29 @@ Enable Signal Source Name : -- ; ula:ula_|video:video_|vram_address[2] ; 16 ; ; ula:ula_|video:video_|vram_address[1] ; 16 ; ; ula:ula_|video:video_|vram_address[0] ; 16 ; +; z80_top_direct_n:z80_|pin_control:pin_control_|bus_ab_pin_we~1 ; 16 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_apin_mux2~0 ; 16 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_apin_mux~2 ; 16 ; ; z80_top_direct_n:z80_|resets:resets_|clrpc~0 ; 16 ; -; z80_top_direct_n:z80_|execute:execute_|setM1~52 ; 16 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~12 ; 16 ; -; z80_top_direct_n:z80_|decode_state:decode_state_|use_ixiy ; 16 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal32~0 ; 16 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal34~0 ; 16 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mWrite~3 ; 16 ; -; z80_top_direct_n:z80_|interrupts:interrupts_|in_nmi_ALTERA_SYNTHESIZED ; 16 ; -; ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] ; 16 ; +; z80_top_direct_n:z80_|execute:execute_|ixy_d~15 ; 16 ; +; z80_top_direct_n:z80_|execute:execute_|setM1~54 ; 16 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~6 ; 16 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal3~1 ; 16 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal21~0 ; 16 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal2~0 ; 16 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mWrite~5 ; 16 ; ; ula:ula_|video:video_|Decoder0~0 ; 16 ; ; ula:ula_|video:video_|Equal3~1 ; 16 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~14 ; 15 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low ; 15 ; ; z80_top_direct_n:z80_|reg_control:reg_control_|bank_exx ; 15 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal41~2 ; 15 ; -; z80_top_direct_n:z80_|pin_control:pin_control_|bus_db_pin_oe~14 ; 15 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~10 ; 15 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~7 ; 15 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~6 ; 15 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal2~0 ; 15 ; -; z80_top_direct_n:z80_|address_pins:address_pins_|abus[15]~22 ; 15 ; +; z80_top_direct_n:z80_|pin_control:pin_control_|bus_db_pin_oe~15 ; 15 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal32~0 ; 15 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal1~4 ; 15 ; ; ula:ula_|video:video_|Equal1~0 ; 15 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_cf2_sel_daa ; 14 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~15 ; 14 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp0[7]~92 ; 14 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp0[7]~91 ; 14 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp0[6]~82 ; 14 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp0[5]~72 ; 14 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp0[4]~62 ; 14 ; @@ -10709,68 +10709,69 @@ Enable Signal Source Name : -- ; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp1[0]~30 ; 14 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp1[1]~21 ; 14 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp0[0]~22 ; 14 ; -; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T5_ff ; 14 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~10 ; 14 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~9 ; 14 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~8 ; 14 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mWrite~4 ; 14 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal19~0 ; 14 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal21~0 ; 14 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~6 ; 14 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~7 ; 14 ; +; z80_top_direct_n:z80_|decode_state:decode_state_|DFFE_inst4 ; 14 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mWrite~6 ; 14 ; ; z80_top_direct_n:z80_|decode_state:decode_state_|in_halt ; 14 ; ; ula:ula_|video:video_|vga_hc[2] ; 14 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_cf2_sel_daa ; 13 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal1~7 ; 13 ; -; ula:ula_|i2c_loader:i2c_loader_|phase[1] ; 13 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_shift_oe~43 ; 13 ; -; z80_top_direct_n:z80_|execute:execute_|ixy_d~15 ; 13 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_bus~5 ; 13 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_bus~1 ; 13 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal52~1 ; 13 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal56~0 ; 13 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~9 ; 13 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~8 ; 13 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~4 ; 13 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~5 ; 13 ; -; z80_top_direct_n:z80_|decode_state:decode_state_|DFFE_inst4 ; 13 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_oe~2 ; 13 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_oe~0 ; 13 ; +; ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] ; 13 ; ; ula:ula_|video:video_|vga_hc[1] ; 13 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~14 ; 12 ; -; z80_top_direct_n:z80_|bus_control:bus_control_|db[3]~21 ; 12 ; -; z80_top_direct_n:z80_|bus_control:bus_control_|db[4]~19 ; 12 ; -; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sel_af~0 ; 12 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal69~0 ; 12 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~17 ; 12 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal52~1 ; 12 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal40~1 ; 12 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal39~0 ; 12 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~12 ; 12 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_in_hi~2 ; 12 ; +; ula:ula_|i2c_loader:i2c_loader_|phase[1] ; 12 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_shift_oe~43 ; 12 ; +; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T5_ff ; 12 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~5 ; 12 ; ; Equal2~0 ; 12 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal8~0 ; 12 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal3~0 ; 12 ; ; z80_top_direct_n:z80_|decode_state:decode_state_|DFFE_instCB ; 12 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal1~4 ; 12 ; -; ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] ; 12 ; ; ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] ; 12 ; +; z80_top_direct_n:z80_|bus_control:bus_control_|db[3]~21 ; 11 ; +; z80_top_direct_n:z80_|bus_control:bus_control_|db[4]~19 ; 11 ; ; z80_top_direct_n:z80_|bus_control:bus_control_|db[5]~15 ; 11 ; +; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sel_af~0 ; 11 ; ; z80_top_direct_n:z80_|execute:execute_|nextM~14 ; 11 ; ; ula:ula_|zx_keyboard:zx_keyboard_|shifted ; 11 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal69~0 ; 11 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~15 ; 11 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~13 ; 11 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal39~0 ; 11 ; ; z80_top_direct_n:z80_|execute:execute_|nextM~2 ; 11 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~25 ; 11 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal20~0 ; 11 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~7 ; 11 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal52~0 ; 11 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal3~0 ; 11 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_in_hi~2 ; 11 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal9~0 ; 11 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|abus[15]~22 ; 11 ; ; ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] ; 11 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_bs_oe ; 10 ; -; D[0]~107 ; 10 ; +; D[0]~84 ; 10 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op1_sel_zero ; 10 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op1_sel_bus~15 ; 10 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_flags_cf2_sel_shift~4 ; 10 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_res_oe~2 ; 10 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_res_oe~3 ; 10 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_bs_oe ; 10 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_66_oe~2 ; 10 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_sw_4d~6 ; 10 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal35~0 ; 10 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal49~0 ; 10 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal40~1 ; 10 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal24~0 ; 10 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal9~0 ; 10 ; +; z80_top_direct_n:z80_|decode_state:decode_state_|DFFE_instIY1 ; 10 ; +; z80_top_direct_n:z80_|decode_state:decode_state_|DFFE_instED ; 10 ; ; z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[15] ; 10 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_28 ; 9 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_68 ; 9 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_56 ; 9 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_52 ; 9 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_48 ; 9 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_44 ; 9 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_70 ; 9 ; @@ -10783,6 +10784,7 @@ Enable Signal Source Name : -- ; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op2_sel_zero ; 9 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op2_sel_bus~8 ; 9 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op2_sel_lq ; 9 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_oe~11 ; 9 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_sw_2d~13 ; 9 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_out_hi~7 ; 9 ; ; ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[0]~0 ; 9 ; @@ -10792,7 +10794,6 @@ Enable Signal Source Name : -- ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_64~0 ; 9 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_40~0 ; 9 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_36~0 ; 9 ; -; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_82 ; 9 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_78~0 ; 9 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_42~0 ; 9 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_66~0 ; 9 ; @@ -10804,26 +10805,22 @@ Enable Signal Source Name : -- ; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op2_oe~0 ; 9 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_flags_alu~15 ; 9 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_bus_db_oe ; 9 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[0][0]~15 ; 9 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[0][0]~13 ; 9 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_inc_dec~11 ; 9 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_72 ; 9 ; ; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sw_4d_hi~0 ; 9 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_60 ; 9 ; +; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~17 ; 9 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_62 ; 9 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_74 ; 9 ; -; D[4]~98 ; 9 ; -; D[3]~96 ; 9 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal8~0 ; 9 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal25~0 ; 9 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~14 ; 9 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mWrite~7 ; 9 ; -; z80_top_direct_n:z80_|execute:execute_|ixy_d~8 ; 9 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal20~0 ; 9 ; -; z80_top_direct_n:z80_|decode_state:decode_state_|DFFE_instIY1 ; 9 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~5 ; 9 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~4 ; 9 ; -; z80_top_direct_n:z80_|decode_state:decode_state_|DFFE_instED ; 9 ; +; D[4]~76 ; 9 ; +; D[3]~74 ; 9 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal49~0 ; 9 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~12 ; 9 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal52~0 ; 9 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~2 ; 9 ; ; z80_top_direct_n:z80_|interrupts:interrupts_|DFFE_inst44 ; 9 ; +; Selector3~0 ; 9 ; ; ula:ula_|video:video_|vga_hc[3] ; 9 ; ; ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] ; 9 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_29 ; 8 ; @@ -10840,9 +10837,7 @@ Enable Signal Source Name : -- ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_55 ; 8 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_47 ; 8 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_51 ; 8 ; -; z80_top_direct_n:z80_|alu:alu_|db[7]~26 ; 8 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_58 ; 8 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel~36 ; 8 ; ; ula:ula_|i2c_loader:i2c_loader_|Mux42~0 ; 8 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_77~0 ; 8 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_81 ; 8 ; @@ -10855,7 +10850,7 @@ Enable Signal Source Name : -- ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_43~0 ; 8 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_39~0 ; 8 ; ; z80_top_direct_n:z80_|alu:alu_|alu_mux_3z:b2v_op2_latch_mux_high|ena ; 8 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_oe~14 ; 8 ; +; z80_top_direct_n:z80_|alu:alu_|db[7]~9 ; 8 ; ; ula:ula_|video:video_|vram_address~0 ; 8 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_73 ; 8 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_61 ; 8 ; @@ -10863,73 +10858,76 @@ Enable Signal Source Name : -- ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_63 ; 8 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_75 ; 8 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|gdfx_temp0[0]~21 ; 8 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_82 ; 8 ; ; z80_top_direct_n:z80_|alu_control:alu_control_|db[6]~11 ; 8 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~12 ; 8 ; +; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sel_hl2~0 ; 8 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_flags_bus ; 8 ; ; z80_top_direct_n:z80_|data_pins:data_pins_|SYNTHESIZED_WIRE_2 ; 8 ; ; z80_top_direct_n:z80_|pin_control:pin_control_|bus_db_pin_re ; 8 ; ; z80_top_direct_n:z80_|bus_control:bus_control_|db[0]~6 ; 8 ; ; z80_top_direct_n:z80_|bus_control:bus_control_|db[0]~4 ; 8 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_66_oe~2 ; 8 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~13 ; 8 ; -; ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|decode_jsa:decode2|eq_node[1]~1 ; 8 ; -; ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|decode_jsa:decode2|eq_node[0]~0 ; 8 ; +; ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|decode_jsa:decode2|eq_node[0]~1 ; 8 ; +; ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|decode_jsa:decode2|eq_node[1]~0 ; 8 ; ; ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3|w_anode252w[2]~0 ; 8 ; ; ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3|w_anode252w[2] ; 8 ; ; ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3|w_anode223w[2]~0 ; 8 ; ; ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3|w_anode223w[2] ; 8 ; -; ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_f8a:rden_decode|w_anode284w[2]~0 ; 8 ; -; ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3|w_anode236w[2] ; 8 ; ; ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3|w_anode244w[2]~0 ; 8 ; ; ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3|w_anode244w[2] ; 8 ; +; ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_f8a:rden_decode|w_anode284w[2]~0 ; 8 ; +; ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|decode_msa:decode3|w_anode236w[2] ; 8 ; ; ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[7] ; 8 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|db_hi_as[0]~2 ; 8 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|db_lo_as[0]~2 ; 8 ; -; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~38 ; 8 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~14 ; 8 ; +; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sys_we_lo ; 8 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~28 ; 8 ; ; ula:ula_|video:video_|Decoder0~2 ; 8 ; ; ula:ula_|video:video_|Decoder0~1 ; 8 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~13 ; 8 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~27 ; 8 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal48~0 ; 8 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal25~0 ; 8 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal12~1 ; 8 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_oe~3 ; 8 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_oe~1 ; 8 ; +; z80_top_direct_n:z80_|execute:execute_|ixy_d~8 ; 8 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal37~0 ; 8 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~11 ; 8 ; -; D[0]~58 ; 8 ; -; D[2]~46 ; 8 ; -; D[1]~34 ; 8 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mWrite~5 ; 8 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~24 ; 8 ; +; D[0]~46 ; 8 ; +; D[2]~39 ; 8 ; +; D[1]~32 ; 8 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mWrite~7 ; 8 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal77~0 ; 8 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal41~0 ; 8 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~3 ; 8 ; ; ula:ula_|video:video_|vga_hc[0] ; 8 ; ; ula:ula_|video:video_|vga_hc[6] ; 8 ; ; ula:ula_|video:video_|vga_vc[5] ; 8 ; ; ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] ; 8 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_54 ; 7 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_52 ; 7 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal38~2 ; 7 ; ; ula:ula_|always0~3 ; 7 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_iorw~11 ; 7 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_iorw~10 ; 7 ; ; ula:ula_|i2c_loader:i2c_loader_|nbyte[0] ; 7 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_sw_1d~7 ; 7 ; -; z80_top_direct_n:z80_|alu_control:alu_control_|SYNTHESIZED_WIRE_2~0 ; 7 ; -; z80_top_direct_n:z80_|alu:alu_|db_high[3]~8 ; 7 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_S~8 ; 7 ; -; z80_top_direct_n:z80_|alu:alu_|db_high[3]~3 ; 7 ; -; z80_top_direct_n:z80_|alu:alu_|db_high[3]~2 ; 7 ; -; D[7]~102 ; 7 ; -; D[6]~101 ; 7 ; -; D[5]~99 ; 7 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[7][1]~23 ; 7 ; +; z80_top_direct_n:z80_|alu:alu_|db_high[3]~7 ; 7 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~41 ; 7 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel~7 ; 7 ; +; D[7]~80 ; 7 ; +; D[6]~79 ; 7 ; +; D[5]~77 ; 7 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[7][1]~21 ; 7 ; ; ula:ula_|ps2_keyboard:ps2_keyboard_|scan_code_ready ; 7 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo[1]~33 ; 7 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_bus_inc_oe~33 ; 7 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo[1]~35 ; 7 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_bus_inc_oe~42 ; 7 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_inc_dec~5 ; 7 ; -; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sys_we_lo ; 7 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo[0]~31 ; 7 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mWrite~9 ; 7 ; ; z80_top_direct_n:z80_|alu_control:alu_control_|flags_cond_true ; 7 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal13~1 ; 7 ; ; z80_top_direct_n:z80_|memory_ifc:memory_ifc_|nWR_out~0 ; 7 ; ; z80_top_direct_n:z80_|memory_ifc:memory_ifc_|nRD_out~2 ; 7 ; ; z80_top_direct_n:z80_|decode_state:decode_state_|table_xx~0 ; 7 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal41~0 ; 7 ; ; ula:ula_|video:video_|vga_hc[8] ; 7 ; ; ula:ula_|video:video_|vga_hc[7] ; 7 ; ; ula:ula_|video:video_|vga_vc[9] ; 7 ; @@ -10940,33 +10938,33 @@ Enable Signal Source Name : -- ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_in_lo~9 ; 6 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_pf_sel[0]~3 ; 6 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal61~2 ; 6 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo_pla77M1T1_3 ; 6 ; -; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~49 ; 6 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~47 ; 6 ; -; ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]~11 ; 6 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_pf_sel_pla11M1T1_11 ; 6 ; +; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~26 ; 6 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~44 ; 6 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_al_we~13 ; 6 ; +; ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]~10 ; 6 ; ; ula:ula_|i2c_loader:i2c_loader_|nbyte[1] ; 6 ; -; z80_top_direct_n:z80_|alu:alu_|db[7]~21 ; 6 ; -; z80_top_direct_n:z80_|alu:alu_|db[0]~19 ; 6 ; +; z80_top_direct_n:z80_|alu:alu_|db[0]~14 ; 6 ; +; z80_top_direct_n:z80_|alu:alu_|db[7]~12 ; 6 ; ; ula:ula_|ps2_keyboard:ps2_keyboard_|bit_count[3] ; 6 ; ; ula:ula_|ps2_keyboard:ps2_keyboard_|bit_count[1] ; 6 ; ; ula:ula_|ps2_keyboard:ps2_keyboard_|bit_count[2] ; 6 ; ; ula:ula_|ps2_keyboard:ps2_keyboard_|clk_edge ; 6 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_use_sp~6 ; 6 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_out_lo~8 ; 6 ; -; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sel_hl2~0 ; 6 ; ; z80_top_direct_n:z80_|execute:execute_|rsel3 ; 6 ; -; z80_top_direct_n:z80_|alu:alu_|db_high[1]~20 ; 6 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~27 ; 6 ; -; z80_top_direct_n:z80_|alu_flags:alu_flags_|DFFE_inst_latch_nf ; 6 ; +; z80_top_direct_n:z80_|alu:alu_|db_high[1]~19 ; 6 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_R~4 ; 6 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~11 ; 6 ; +; z80_top_direct_n:z80_|alu:alu_|db_high[3]~0 ; 6 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_pf_sel_pla82M1T1_16 ; 6 ; ; ExtRamWE~0 ; 6 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_inc_dec~10 ; 6 ; ; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sys_we_hi ; 6 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_inc_dec~6 ; 6 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo[0]~29 ; 6 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_bus_db_oe~1 ; 6 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal33~3 ; 6 ; -; z80_top_direct_n:z80_|execute:execute_|ixy_d~10 ; 6 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal44~0 ; 6 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~16 ; 6 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op1_sel_zero~4 ; 6 ; ; z80_top_direct_n:z80_|alu_flags:alu_flags_|SYNTHESIZED_WIRE_39 ; 6 ; ; z80_top_direct_n:z80_|execute:execute_|comb~0 ; 6 ; ; ula:ula_|i2s_intf:i2s_intf_|bdivider[0] ; 6 ; @@ -10983,93 +10981,83 @@ Enable Signal Source Name : -- ; ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]~18 ; 5 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo_pla89M1T2_3 ; 5 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_alu_sel_op2_high ; 5 ; +; z80_top_direct_n:z80_|alu:alu_|db_low[3]~25 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo_pla77M1T1_3 ; 5 ; ; z80_top_direct_n:z80_|execute:execute_|ixy_d~16 ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_al_we~13 ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_iorw~10 ; 5 ; ; ula:ula_|i2c_loader:i2c_loader_|nbit[0] ; 5 ; -; z80_top_direct_n:z80_|alu:alu_|db[5]~25 ; 5 ; -; z80_top_direct_n:z80_|alu:alu_|db[6]~23 ; 5 ; -; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_3|cy_out~0 ; 5 ; -; z80_top_direct_n:z80_|alu:alu_|db[4]~17 ; 5 ; +; z80_top_direct_n:z80_|alu:alu_|db[5]~24 ; 5 ; +; z80_top_direct_n:z80_|alu:alu_|db[6]~22 ; 5 ; +; z80_top_direct_n:z80_|alu:alu_|db[3]~20 ; 5 ; +; z80_top_direct_n:z80_|alu:alu_|db[4]~18 ; 5 ; +; z80_top_direct_n:z80_|alu:alu_|db[2]~16 ; 5 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op1_sel_low ; 5 ; -; z80_top_direct_n:z80_|alu:alu_|db[2]~15 ; 5 ; -; z80_top_direct_n:z80_|alu:alu_|db[1]~13 ; 5 ; -; z80_top_direct_n:z80_|alu:alu_|db[3]~11 ; 5 ; +; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_3|cy_out~0 ; 5 ; +; z80_top_direct_n:z80_|alu:alu_|db[1]~10 ; 5 ; ; z80_top_direct_n:z80_|alu_control:alu_control_|db[4]~32 ; 5 ; ; ula:ula_|ps2_keyboard:ps2_keyboard_|bit_count[0] ; 5 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_68~2 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sel_wz~18 ; 5 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_out_lo~7 ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~40 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~37 ; 5 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_sw_mask543_en~0 ; 5 ; +; z80_top_direct_n:z80_|alu_control:alu_control_|SYNTHESIZED_WIRE_2~0 ; 5 ; ; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sel_hl~0 ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~19 ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_sw_2u~5 ; 5 ; -; z80_top_direct_n:z80_|alu:alu_|db_high[0]~26 ; 5 ; -; z80_top_direct_n:z80_|alu:alu_|db_high[2]~14 ; 5 ; +; z80_top_direct_n:z80_|alu:alu_|db_high[0]~25 ; 5 ; +; z80_top_direct_n:z80_|alu:alu_|db_high[2]~13 ; 5 ; ; z80_top_direct_n:z80_|alu:alu_|op1_high[1] ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_S~9 ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_sel_op2_neg~18 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_S ; 5 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal62~2 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_sel_op2_neg~15 ; 5 ; +; z80_top_direct_n:z80_|alu_flags:alu_flags_|DFFE_inst_latch_nf ; 5 ; ; z80_top_direct_n:z80_|alu:alu_|op1_high[2] ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~23 ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~19 ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_R~4 ; 5 ; ; z80_top_direct_n:z80_|alu:alu_|op1_high[3] ; 5 ; -; z80_top_direct_n:z80_|alu:alu_|db_low[0]~23 ; 5 ; -; z80_top_direct_n:z80_|alu:alu_|db_low[1]~17 ; 5 ; -; z80_top_direct_n:z80_|alu:alu_|op1_low[1] ; 5 ; -; z80_top_direct_n:z80_|alu:alu_|op1_low[3] ; 5 ; +; z80_top_direct_n:z80_|alu:alu_|db_low[2]~23 ; 5 ; ; z80_top_direct_n:z80_|alu:alu_|op1_low[2] ; 5 ; +; z80_top_direct_n:z80_|alu:alu_|op1_low[3] ; 5 ; +; z80_top_direct_n:z80_|alu:alu_|db_low[1]~12 ; 5 ; +; z80_top_direct_n:z80_|alu:alu_|op1_low[1] ; 5 ; +; z80_top_direct_n:z80_|alu:alu_|db_high[3]~1 ; 5 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_alu_shift_oe~38 ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~15 ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~26 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|nextM~11 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~24 ; 5 ; ; z80_top_direct_n:z80_|address_latch:address_latch_|Q[13] ; 5 ; ; z80_top_direct_n:z80_|address_latch:address_latch_|Q[11] ; 5 ; ; z80_top_direct_n:z80_|address_latch:address_latch_|Q[7] ; 5 ; -; z80_top_direct_n:z80_|address_latch:address_latch_|Q[1] ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_inc_dec~10 ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_inc_dec~9 ; 5 ; +; z80_top_direct_n:z80_|address_latch:address_latch_|Q[4] ; 5 ; ; z80_top_direct_n:z80_|address_latch:address_latch_|Q[9] ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_in_hi~5 ; 5 ; -; z80_top_direct_n:z80_|address_latch:address_latch_|Q[0] ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_inc_dec~6 ; 5 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sel_ir~1 ; 5 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_out_hi~4 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo_ixy_dT5_7 ; 5 ; ; ula:ula_|i2s_intf:i2s_intf_|bitcount[4]~15 ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~18 ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~16 ; 5 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal12~0 ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~13 ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op1_sel_zero~4 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sel_wz~8 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ixy_d~10 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~14 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~11 ; 5 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_alu_shift_oe~15 ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~8 ; 5 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~7 ; 5 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal44~0 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~5 ; 5 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal40~0 ; 5 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal29~0 ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mWrite~6 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mWrite~8 ; 5 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo_pla56M3T3_6 ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|fMWrite~3 ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_sw_4u~0 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|fMWrite~1 ; 5 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_apin_mux~0 ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|fMRead~0 ; 5 ; +; z80_top_direct_n:z80_|execute:execute_|fMRead~2 ; 5 ; ; z80_top_direct_n:z80_|memory_ifc:memory_ifc_|nIORQ_out~0 ; 5 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~9 ; 5 ; ; ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]~1 ; 5 ; ; ula:ula_|i2s_intf:i2s_intf_|Equal1~0 ; 5 ; ; ula:ula_|video:video_|vga_hc[5] ; 5 ; ; ula:ula_|video:video_|vga_hc[4] ; 5 ; ; ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 ; 5 ; -; z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[0] ; 5 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal62~3 ; 4 ; ; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sel_iy~2 ; 4 ; ; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sel_de2~6 ; 4 ; ; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sel_de2~5 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~34 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~33 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_pf_sel_pla11M1T1_11 ; 4 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_flags_hf2_we ; 4 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_sw_1d~8 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_al_we~14 ; 4 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo_pla57M1T4_4 ; 4 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal68~2 ; 4 ; ; ula:ula_|i2c_loader:i2c_loader_|state.Pause ; 4 ; ; ula:ula_|i2c_loader:i2c_loader_|nbit[1] ; 4 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_69~2 ; 4 ; @@ -11077,34 +11065,38 @@ Enable Signal Source Name : -- ; ula:ula_|i2c_loader:i2c_loader_|state.Stop ; 4 ; ; z80_top_direct_n:z80_|alu:alu_|alu_mux_2z:b2v_op1_latch_mux_high|ena~0 ; 4 ; ; z80_top_direct_n:z80_|alu:alu_|alu_mux_3z:b2v_op1_latch_mux_low|ena ; 4 ; +; z80_top_direct_n:z80_|alu:alu_|db_low[0]~24 ; 4 ; ; z80_top_direct_n:z80_|alu_control:alu_control_|db[3]~35 ; 4 ; ; z80_top_direct_n:z80_|alu_control:alu_control_|db[2]~29 ; 4 ; ; z80_top_direct_n:z80_|alu_control:alu_control_|db[1]~26 ; 4 ; ; z80_top_direct_n:z80_|alu_control:alu_control_|db[6]~22 ; 4 ; -; z80_top_direct_n:z80_|alu_control:alu_control_|db[7]~18 ; 4 ; +; z80_top_direct_n:z80_|alu_control:alu_control_|db[7]~19 ; 4 ; ; z80_top_direct_n:z80_|alu_control:alu_control_|db[5]~15 ; 4 ; ; ula:ula_|video:video_|vram_address[9]~1 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sel_wz~17 ; 4 ; ; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sel_af2~0 ; 4 ; ; z80_top_direct_n:z80_|alu_control:alu_control_|db[0]~12 ; 4 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_out_lo~5 ; 4 ; ; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sel_de~0 ; 4 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_70~2 ; 4 ; ; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sel_de2~4 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_xy_we~12 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~15 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_xy_we~14 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_R~5 ; 4 ; ; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_2|cy_out~0 ; 4 ; +; z80_top_direct_n:z80_|alu:alu_|op1_high[0] ; 4 ; ; z80_top_direct_n:z80_|alu_flags:alu_flags_|flags_cf ; 4 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_pf_sel_pla66npla53M1T1_15 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~42 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~37 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~34 ; 4 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_R ; 4 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal62~2 ; 4 ; +; z80_top_direct_n:z80_|alu_flags:alu_flags_|DFFE_inst_latch_nf~4 ; 4 ; ; z80_top_direct_n:z80_|alu_flags:alu_flags_|DFFE_inst_latch_cf ; 4 ; -; z80_top_direct_n:z80_|alu:alu_|db_low[3]~11 ; 4 ; -; z80_top_direct_n:z80_|alu:alu_|db_low[2]~6 ; 4 ; -; z80_top_direct_n:z80_|alu:alu_|db_low[2]~3 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op1_sel_bus~7 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_sel_op2_neg~5 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_sz_we~4 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op1_sel_bus~8 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo_ixy_dT4_2 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_sel_op2_neg~3 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_use_sp~0 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~29 ; 4 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_pf_sel[0]~2 ; 4 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_R~1 ; 4 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|db_lo_as[7]~24 ; 4 ; @@ -11114,83 +11106,91 @@ Enable Signal Source Name : -- ; z80_top_direct_n:z80_|reg_file:reg_file_|db_lo_as[3]~12 ; 4 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|db_lo_as[2]~9 ; 4 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|db_lo_as[1]~6 ; 4 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[5][4]~62 ; 4 ; ; ula:ula_|zx_keyboard:zx_keyboard_|Equal0~2 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|nextM~11 ; 4 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[6][4]~46 ; 4 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_sw_1d~6 ; 4 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|db_hi_as[6]~24 ; 4 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|db_hi_as[7]~21 ; 4 ; ; z80_top_direct_n:z80_|address_latch:address_latch_|Q[14] ; 4 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[5][1]~36 ; 4 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[7][2]~32 ; 4 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[5][1]~34 ; 4 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[7][2]~30 ; 4 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|db_hi_as[4]~18 ; 4 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|db_hi_as[5]~15 ; 4 ; ; z80_top_direct_n:z80_|address_latch:address_latch_|Q[12] ; 4 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|db_hi_as[3]~12 ; 4 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[1][4]~25 ; 4 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[1][4]~23 ; 4 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|db_hi_as[2]~9 ; 4 ; ; z80_top_direct_n:z80_|address_latch:address_latch_|Q[10] ; 4 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[7][4]~19 ; 4 ; ; ula:ula_|zx_keyboard:zx_keyboard_|Equal0~1 ; 4 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|db_hi_as[0]~6 ; 4 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|db_hi_as[1]~3 ; 4 ; ; z80_top_direct_n:z80_|address_latch:address_latch_|Q[8] ; 4 ; ; z80_top_direct_n:z80_|address_latch:address_latch_|Q[6] ; 4 ; +; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|inc_dec_2bit:b2v_dual_adder_2|carry_borrow_out~0 ; 4 ; +; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|inc_dec_2bit:b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0 ; 4 ; +; z80_top_direct_n:z80_|address_latch:address_latch_|Q[1] ; 4 ; ; z80_top_direct_n:z80_|address_latch:address_latch_|Q[2] ; 4 ; ; z80_top_direct_n:z80_|address_latch:address_latch_|Q[3] ; 4 ; -; z80_top_direct_n:z80_|address_latch:address_latch_|Q[4] ; 4 ; ; z80_top_direct_n:z80_|address_latch:address_latch_|Q[5] ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_inc_dec~9 ; 4 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_inc_dec~7 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_in_hi~5 ; 4 ; ; z80_top_direct_n:z80_|reg_file:reg_file_|db_lo_as[0]~3 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[1]~5 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~85 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~53 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~34 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~31 ; 4 ; +; z80_top_direct_n:z80_|address_latch:address_latch_|Q[0] ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~16 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~9 ; 4 ; ; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sel_pc ; 4 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_sw_4u~1 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo~20 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sel_wz~8 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo_ixy_dT5_7 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo~21 ; 4 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_bus_db_oe~0 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|fMRead~3 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo[0]~11 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_al_we~4 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~28 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo[0]~12 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~6 ; 4 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal33~2 ; 4 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal50~0 ; 4 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal12~0 ; 4 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo_pla42M3T3_6 ; 4 ; ; z80_top_direct_n:z80_|decode_state:decode_state_|DFFE_instNonRep ; 4 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_flags_sz_we~0 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_bus~4 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_bus~0 ; 4 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal1~5 ; 4 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal2~1 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_sel_op2_neg~4 ; 4 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_sel_op2_neg~2 ; 4 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 ; 4 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo[1]~8 ; 4 ; ; z80_top_direct_n:z80_|execute:execute_|ixy_d~4 ; 4 ; ; ula:ula_|i2s_intf:i2s_intf_|Equal1~1 ; 4 ; ; z80_top_direct_n:z80_|memory_ifc:memory_ifc_|SYNTHESIZED_WIRE_16 ; 4 ; ; ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 ; 4 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[10] ; 4 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[8] ; 4 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[0] ; 4 ; ; ula:ula_|i2s_intf:i2s_intf_|bitcount[4] ; 4 ; ; PS2_DAT~input ; 3 ; ; raw_loader_in~input ; 3 ; ; I2C_SDAT~input ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~48 ; 3 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_flags_use_cf2~13 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~94 ; 3 ; -; z80_top_direct_n:z80_|alu:alu_|db_low[3]~25 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~15 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_bs_oe~14 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_66_oe ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~13 ; 3 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal72~2 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_bs_oe~12 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mWrite~18 ; 3 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_im_we ; 3 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op2_sel_bus~9 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_alu~16 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_alu~18 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_alu~17 ; 3 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel_pla10M5T1_5~2 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~50 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sel_wz~19 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~27 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_al_we~14 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sel_wz~21 ; 3 ; ; z80_top_direct_n:z80_|execute:execute_|ixy_d~17 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sel_wz~18 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_xy_we~16 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo[1]~35 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_inc_dec~12 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~82 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sel_wz~20 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_iorw~11 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|setM1~57 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~45 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_xy_we~19 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo[1]~37 ; 3 ; ; ula:ula_|i2c_loader:i2c_loader_|nbit[0]~4 ; 3 ; ; ula:ula_|i2c_loader:i2c_loader_|state~24 ; 3 ; ; ula:ula_|i2c_loader:i2c_loader_|nbit[2] ; 3 ; @@ -11201,117 +11201,112 @@ Enable Signal Source Name : -- ; z80_top_direct_n:z80_|bus_control:bus_control_|db[0]~17 ; 3 ; ; z80_top_direct_n:z80_|alu_control:alu_control_|out[6]~2 ; 3 ; ; z80_top_direct_n:z80_|reg_control:reg_control_|bank_af ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_oe~9 ; 3 ; ; z80_top_direct_n:z80_|reg_control:reg_control_|bank_hl_de1 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_sw_2u~5 ; 3 ; ; z80_top_direct_n:z80_|execute:execute_|rsel0 ; 3 ; ; z80_top_direct_n:z80_|reg_control:reg_control_|bank_hl_de2 ; 3 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[0]~30 ; 3 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_flags_oe~1 ; 3 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[1]~26 ; 3 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_flags_pf_we~4 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[0]~20 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[0]~12 ; 3 ; ; ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] ; 3 ; ; z80_top_direct_n:z80_|alu_flags:alu_flags_|DFFE_inst_latch_pf ; 3 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_flags_sz_we~6 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_xy_we~11 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_xy_we~13 ; 3 ; ; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_0|result~0 ; 3 ; ; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_1|result~0 ; 3 ; ; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_2|result~0 ; 3 ; ; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_3|result~0 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_R~5 ; 3 ; ; z80_top_direct_n:z80_|alu:alu_|alu_op2[3]~2 ; 3 ; ; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 ; 3 ; +; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 ; 3 ; ; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_0|cy_out~0 ; 3 ; ; z80_top_direct_n:z80_|alu:alu_|op2_high[0] ; 3 ; -; z80_top_direct_n:z80_|alu:alu_|alu_op1[0]~1 ; 3 ; -; z80_top_direct_n:z80_|alu:alu_|op1_high[0] ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~28 ; 3 ; -; z80_top_direct_n:z80_|alu:alu_|alu_op2[1]~1 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_hf~15 ; 3 ; +; z80_top_direct_n:z80_|alu_flags:alu_flags_|SYNTHESIZED_WIRE_0~13 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~12 ; 3 ; ; z80_top_direct_n:z80_|alu:alu_|alu_op2[2]~0 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo_ixy_dT4_2 ; 3 ; ; z80_top_direct_n:z80_|alu_flags:alu_flags_|DFFE_inst_latch_sf ; 3 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_pf_sel_nop3pla68M3T1_20 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~40 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~38 ; 3 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op1_sel_bus~10 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~20 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_sel_op2_neg~6 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~13 ; 3 ; -; z80_top_direct_n:z80_|alu_flags:alu_flags_|DFFE_inst_latch_nf~6 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~11 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~9 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~10 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_state_alu~8 ; 3 ; ; z80_top_direct_n:z80_|alu:alu_|op2_low[0] ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_S~7 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~17 ; 3 ; +; z80_top_direct_n:z80_|alu:alu_|op1_low[0] ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~31 ; 3 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op2_sel_bus~4 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_use_sp~1 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_use_sp~0 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_xy_we~9 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo_ixy_dT2_2 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_sz_we~4 ; 3 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_flags_sz_we~1 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_oe~4 ; 3 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_R~0 ; 3 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_alu_shift_oe~20 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_bus~12 ; 3 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[3][0]~78 ; 3 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[7][4]~51 ; 3 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[6][4]~47 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mWrite~10 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_bus~9 ; 3 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[3][0]~75 ; 3 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[7][4]~49 ; 3 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[6][4]~45 ; 3 ; ; z80_top_direct_n:z80_|bus_control:bus_control_|db[2]~13 ; 3 ; ; z80_top_direct_n:z80_|bus_control:bus_control_|db[1]~11 ; 3 ; ; z80_top_direct_n:z80_|bus_control:bus_control_|db[6]~9 ; 3 ; ; z80_top_direct_n:z80_|bus_control:bus_control_|db[7]~7 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~27 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~25 ; 3 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_bus_db_oe~3 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_bs_oe~9 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_bs_oe~7 ; 3 ; ; ula:ula_|zx_keyboard:zx_keyboard_|WideOr16~2 ; 3 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[6][1]~41 ; 3 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[6][1]~39 ; 3 ; ; z80_top_direct_n:z80_|address_latch:address_latch_|Q[15] ; 3 ; ; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|inc_dec_2bit:b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 ; 3 ; ; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|inc_dec_2bit:b2v_dual_adder_9|carry_borrow_out~0 ; 3 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[5][4]~24 ; 3 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[5][4]~22 ; 3 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[7][4]~17 ; 3 ; ; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|inc_dec_2bit:b2v_dual_adder_7|carry_borrow_out~0 ; 3 ; ; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 ; 3 ; -; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|inc_dec_2bit:b2v_dual_adder_2|carry_borrow_out~0 ; 3 ; -; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 ; 3 ; -; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|SYNTHESIZED_WIRE_42 ; 3 ; -; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|fMRead~35 ; 3 ; +; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|fMRead~36 ; 3 ; ; z80_top_direct_n:z80_|execute:execute_|nextM~4 ; 3 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[0]~6 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~25 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|nextM~3 ; 3 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~23 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|nextM~3 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~21 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[1]~5 ; 3 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel_pla10M5T4_2 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~77 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~43 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~45 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~36 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~35 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~30 ; 3 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal11~1 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~49 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~19 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~41 ; 3 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal45~0 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~12 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~8 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~7 ; 3 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_sw_1d~4 ; 3 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[1]~4 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|fMRead~5 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~29 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_bus_inc_oe~30 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|fMRead~7 ; 3 ; ; z80_top_direct_n:z80_|reg_control:reg_control_|reg_sys_we_lo~6 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~22 ; 3 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_al_we~5 ; 3 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_in_hi~4 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_bs_oe~8 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_bs_oe~6 ; 3 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_in_hi~3 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~42 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|fMRead~6 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~39 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~38 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|setM1~50 ; 3 ; ; z80_top_direct_n:z80_|execute:execute_|setM1~48 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|setM1~46 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|setM1~45 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~19 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|setM1~40 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|setM1~47 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~17 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|setM1~42 ; 3 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal4~0 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|setM1~36 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo[1]~10 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|setM1~29 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_bus_inc_oe~29 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~12 ; 3 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal1~5 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|fMRead~4 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_al_we~4 ; 3 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal40~2 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|setM1~30 ; 3 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal50~0 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_bus_inc_oe~31 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~10 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_sw_2u~1 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~26 ; 3 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal2~2 ; 3 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal79~0 ; 3 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal3~2 ; 3 ; @@ -11321,17 +11316,18 @@ Enable Signal Source Name : -- ; z80_top_direct_n:z80_|data_pins:data_pins_|dout[3] ; 3 ; ; z80_top_direct_n:z80_|data_pins:data_pins_|dout[0] ; 3 ; ; z80_top_direct_n:z80_|data_pins:data_pins_|dout[2] ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sel_wz~4 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo[1]~10 ; 3 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal46~0 ; 3 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_ir_we~6 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_bus_inc_oe~24 ; 3 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal19~1 ; 3 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~34 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_bus_inc_oe~26 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_sw_4u~0 ; 3 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~32 ; 3 ; ; z80_top_direct_n:z80_|data_pins:data_pins_|dout[1] ; 3 ; ; z80_top_direct_n:z80_|execute:execute_|fIOWrite~5 ; 3 ; ; z80_top_direct_n:z80_|memory_ifc:memory_ifc_|wait_mrd ; 3 ; ; z80_top_direct_n:z80_|execute:execute_|fIORead~3 ; 3 ; ; z80_top_direct_n:z80_|execute:execute_|fIOWrite~0 ; 3 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal68~2 ; 3 ; ; z80_top_direct_n:z80_|memory_ifc:memory_ifc_|iorq~0 ; 3 ; ; ula:ula_|i2s_intf:i2s_intf_|LessThan0~0 ; 3 ; ; ula:ula_|i2s_intf:i2s_intf_|lrclk_r~0 ; 3 ; @@ -11344,79 +11340,72 @@ Enable Signal Source Name : -- ; ula:ula_|video:video_|Equal2~0 ; 3 ; ; ula:ula_|video:video_|LessThan6~0 ; 3 ; ; ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 ; 3 ; -; z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[12] ; 3 ; -; z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[11] ; 3 ; -; z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[10] ; 3 ; +; z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[9] ; 3 ; ; SW[2]~input ; 2 ; ; SW[1]~input ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_state_tbl_we~8 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|pc_inc_hold~52 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_bus_inc_oe~47 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~92 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_66_oe ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~53 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~52 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_bus_inc_oe~49 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~87 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~86 ; 2 ; +; z80_top_direct_n:z80_|reg_file:reg_file_|SYNTHESIZED_WIRE_32 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~48 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~47 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_in_hi~13 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_sw_1d~9 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~49 ; 2 ; -; z80_top_direct_n:z80_|alu_flags:alu_flags_|SYNTHESIZED_WIRE_0~22 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_S~11 ; 2 ; -; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal71~2 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_sel_op2_neg~21 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~45 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_S~12 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_sel_op2_neg~18 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo_pla26M1T4_3 ; 2 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal73~2 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_alu_shift_oe~46 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_xy_we~18 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_xy_we~21 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op1_sel_bus~16 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~47 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op2_sel_bus~10 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_flags_cf_we~7 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_flags_pf_we~10 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_flags_hf_we~5 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~48 ; 2 ; -; z80_top_direct_n:z80_|alu_flags:alu_flags_|DFFE_inst_latch_nf~11 ; 2 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[3][4]~130 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_pf_sel_pla12M1T1_12~2 ; 2 ; +; z80_top_direct_n:z80_|alu_flags:alu_flags_|DFFE_inst_latch_nf~9 ; 2 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[3][4]~129 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_state_ixiy_we~2 ; 2 ; ; z80_top_direct_n:z80_|pin_control:pin_control_|bus_db_pin_re~2 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~32 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~46 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_alu_shift_oe~44 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_alu~18 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_alu~19 ; 2 ; ; z80_top_direct_n:z80_|interrupts:interrupts_|test1~3 ; 2 ; -; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4 ; 2 ; -; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4 ; 2 ; +; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|SYNTHESIZED_WIRE_42 ; 2 ; ; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_alu~17 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_bus_inc_oe~46 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_bus_inc_oe~44 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~91 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_bus_inc_oe~48 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_bus_inc_oe~45 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel_pla91pla20M2T2_3 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel_pla9M1T5_2 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sel_pc~20 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_xy_we~17 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_inc_cy~87 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel_pla12M3T1_2 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sel_pc~19 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_xy_we~20 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_out_lo~9 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|setM1~54 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~31 ; 2 ; +; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal68~3 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sys_hilo~38 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo_pla6M1T4_4 ; 2 ; -; D[6]~111 ; 2 ; -; D[4]~109 ; 2 ; -; D[3]~108 ; 2 ; -; D[0]~106 ; 2 ; -; D[2]~105 ; 2 ; -; D[2]~104 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|fMWrite~11 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_bus_inc_oe~43 ; 2 ; -; D[1]~103 ; 2 ; +; D[6]~88 ; 2 ; +; D[4]~86 ; 2 ; +; D[3]~85 ; 2 ; +; D[0]~83 ; 2 ; +; D[2]~82 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_bus_inc_oe~44 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_S~11 ; 2 ; +; D[1]~81 ; 2 ; ; ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] ; 2 ; -; ula:ula_|i2c_loader:i2c_loader_|shiftreg~14 ; 2 ; +; ula:ula_|i2c_loader:i2c_loader_|shiftreg~13 ; 2 ; ; ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] ; 2 ; ; ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] ; 2 ; ; ula:ula_|i2c_loader:i2c_loader_|Mux35~0 ; 2 ; ; ula:ula_|i2c_loader:i2c_loader_|nbyte[0]~3 ; 2 ; -; ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]~8 ; 2 ; +; ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]~7 ; 2 ; ; ula:ula_|i2c_loader:i2c_loader_|state.Done~1 ; 2 ; ; ula:ula_|i2c_loader:i2c_loader_|state.Done~0 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_xy_we~15 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_xy_we~18 ; 2 ; ; ula:ula_|ps2_keyboard:ps2_keyboard_|ps2_clk_in ; 2 ; ; ula:ula_|ps2_keyboard:ps2_keyboard_|Equal0~1 ; 2 ; ; ula:ula_|ps2_keyboard:ps2_keyboard_|clk_filter[1] ; 2 ; @@ -11430,112 +11419,119 @@ Enable Signal Source Name : -- ; ula:ula_|i2c_loader:i2c_loader_|sda_out~4 ; 2 ; ; ula:ula_|i2c_loader:i2c_loader_|sda_out~1 ; 2 ; ; ula:ula_|i2c_loader:i2c_loader_|scl_out~2 ; 2 ; -; z80_top_direct_n:z80_|alu:alu_|alu_parity_out ; 2 ; +; z80_top_direct_n:z80_|alu:alu_|alu_parity_out~1 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_flags_pf_we~9 ; 2 ; -; z80_top_direct_n:z80_|alu_flags:alu_flags_|DFFE_inst_latch_nf~8 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op1_sel_bus~14 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_flags_cf2_we~3 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_flags_hf_we~2 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op1_sel_bus~14 ; 2 ; -; z80_top_direct_n:z80_|alu:alu_|db_low[2]~24 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_oe~13 ; 2 ; ; z80_top_direct_n:z80_|alu_control:alu_control_|db[2]~23 ; 2 ; ; z80_top_direct_n:z80_|alu_flags:alu_flags_|flags_hf2 ; 2 ; ; z80_top_direct_n:z80_|alu_control:alu_control_|out[6]~0 ; 2 ; ; z80_top_direct_n:z80_|interrupts:interrupts_|iff1 ; 2 ; ; ula:ula_|ps2_keyboard:ps2_keyboard_|shiftreg[8] ; 2 ; ; ula:ula_|ps2_keyboard:ps2_keyboard_|LessThan0~0 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sel_wz~16 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_sel_wz~17 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_in_hi~10 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~39 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~36 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_out_hi~6 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_out_lo~2 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_oe~8 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_in_hi~8 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_we~5 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_we~2 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_we~7 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_we~4 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_sw_4u~3 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~37 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~35 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[0]~33 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[0]~31 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~24 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~34 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~32 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[0]~30 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[0]~28 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~20 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[0]~34 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[0]~32 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~23 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~19 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[0]~27 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_we~1 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~22 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_oe~7 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_we~3 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~18 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_oe~6 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[0]~25 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[0]~24 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[0]~22 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~16 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_sw_2u~4 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_sel[0]~14 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_use_sp~3 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~20 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~14 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 ; 2 ; ; ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 ; 2 ; ; z80_top_direct_n:z80_|alu_control:alu_control_|sel[1]~0 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_flags_sz_we~8 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_flags_sz_we~7 ; 2 ; ; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 ; 2 ; -; z80_top_direct_n:z80_|alu:alu_|alu_op1[3]~3 ; 2 ; +; z80_top_direct_n:z80_|alu:alu_|alu_op1[3]~2 ; 2 ; ; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 ; 2 ; ; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 ; 2 ; -; z80_top_direct_n:z80_|alu:alu_|alu_op1[2]~2 ; 2 ; -; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 ; 2 ; +; z80_top_direct_n:z80_|alu:alu_|alu_op1[2]~1 ; 2 ; ; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 ; 2 ; +; z80_top_direct_n:z80_|alu:alu_|alu_op1[0]~0 ; 2 ; ; z80_top_direct_n:z80_|alu_control:alu_control_|alu_core_cf_in~0 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_hf~20 ; 2 ; ; z80_top_direct_n:z80_|alu_flags:alu_flags_|flags_hf ; 2 ; ; z80_top_direct_n:z80_|alu_flags:alu_flags_|DFFE_inst_latch_hf ; 2 ; ; z80_top_direct_n:z80_|alu_flags:alu_flags_|DFFE_inst_latch_cf2 ; 2 ; ; z80_top_direct_n:z80_|pla_decode:pla_decode_|Equal64~0 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo_ixy_dT2_2 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_flags_nf_we~1 ; 2 ; ; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 ; 2 ; -; z80_top_direct_n:z80_|alu:alu_|alu_op1[1]~0 ; 2 ; +; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0 ; 2 ; +; z80_top_direct_n:z80_|alu:alu_|alu_op2[1]~1 ; 2 ; ; z80_top_direct_n:z80_|alu:alu_|op2_high[1] ; 2 ; ; z80_top_direct_n:z80_|alu:alu_|alu_core:b2v_core|alu_slice:b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_sel_op2_neg~17 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_sel_op2_neg~16 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_hf~18 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_sel_op2_neg~14 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_alu_sel_op2_neg~13 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_sel_op2_neg~12 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_sel_op2_neg~8 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_hf~12 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_sel_op2_neg~10 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_sel_op2_neg~9 ; 2 ; ; z80_top_direct_n:z80_|alu:alu_|op2_high[2] ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~26 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~24 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~22 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op1_sel_bus~8 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op_low~36 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op1_sel_bus~9 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_S~9 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_S~8 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_sel_op2_neg~4 ; 2 ; ; z80_top_direct_n:z80_|alu:alu_|op2_high[3] ; 2 ; -; z80_top_direct_n:z80_|alu_control:alu_control_|alu_mux_8:b2v_inst_shift_mux|out~2 ; 2 ; -; z80_top_direct_n:z80_|alu:alu_|op1_low[0] ; 2 ; -; z80_top_direct_n:z80_|alu:alu_|op2_low[1] ; 2 ; +; z80_top_direct_n:z80_|alu:alu_|alu_bit_select:b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 ; 2 ; +; z80_top_direct_n:z80_|alu:alu_|op2_low[2] ; 2 ; +; z80_top_direct_n:z80_|alu:alu_|db_low[3]~17 ; 2 ; ; z80_top_direct_n:z80_|alu:alu_|alu_bit_select:b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 ; 2 ; ; z80_top_direct_n:z80_|alu:alu_|op2_low[3] ; 2 ; -; z80_top_direct_n:z80_|alu:alu_|op2_low[2] ; 2 ; +; z80_top_direct_n:z80_|alu:alu_|op2_low[1] ; 2 ; +; z80_top_direct_n:z80_|alu:alu_|db_low[0]~6 ; 2 ; +; z80_top_direct_n:z80_|alu:alu_|db_low[0]~3 ; 2 ; +; z80_top_direct_n:z80_|alu_control:alu_control_|alu_mux_8:b2v_inst_shift_mux|out~2 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_S~7 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_S~6 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_S~5 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_alu_core_S~4 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_flags_pf_we~3 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_flags_cf_we~2 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_xy_we~10 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_xy_we~12 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_alu_shift_oe~41 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op1_sel_bus~5 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_bs_oe~11 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_shift_oe~31 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_op1_sel_bus~6 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_shift_oe~32 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_bs_oe~9 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_bs_oe~8 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_flags_alu~14 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo_pla25M1T1_3 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_use_sp~1 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_flags_alu~11 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_flags_alu~10 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_flags_sz_we~3 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_xy_we~11 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_xy_we~10 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_flags_sz_we~2 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_xy_we~7 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_alu_oe~5 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_flags_xy_we~6 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_xy_we~9 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_flags_xy_we~8 ; 2 ; ; z80_top_direct_n:z80_|execute:execute_|ctl_flags_pf_we~2 ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_pf_sel_pla12M1T1_12~0 ; 2 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[6][4]~126 ; 2 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[0][4]~111 ; 2 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[0][4]~97 ; 2 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[2][4]~95 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo[1]~13 ; 2 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[0][4]~109 ; 2 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[0][4]~96 ; 2 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[2][4]~94 ; 2 ; ; z80_top_direct_n:z80_|address_latch:address_latch_|abusz[7] ; 2 ; ; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|inc_dec_2bit:b2v_dual_adder_7|d0_out ; 2 ; ; z80_top_direct_n:z80_|address_latch:address_latch_|abusz[6] ; 2 ; @@ -11546,20 +11542,24 @@ Enable Signal Source Name : -- ; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|inc_dec_2bit:b2v_dual_adder_4|d0_out ; 2 ; ; z80_top_direct_n:z80_|address_latch:address_latch_|abusz[3] ; 2 ; ; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|inc_dec_2bit:b2v_dual_adder_2|d1_out ; 2 ; -; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|inc_dec_2bit:b2v_dual_adder_0|carry_borrow_out~0 ; 2 ; ; z80_top_direct_n:z80_|address_latch:address_latch_|abusz[2] ; 2 ; ; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|inc_dec_2bit:b2v_dual_adder_2|d0_out ; 2 ; ; z80_top_direct_n:z80_|address_latch:address_latch_|abusz[1] ; 2 ; ; z80_top_direct_n:z80_|address_latch:address_latch_|inc_dec:b2v_inst_inc_dec|inc_dec_2bit:b2v_dual_adder_0|d1_out ; 2 ; -; ula:ula_|zx_keyboard:zx_keyboard_|shifted~1 ; 2 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[5][0]~67 ; 2 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[5][4]~63 ; 2 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[7][2]~61 ; 2 ; +; ula:ula_|zx_keyboard:zx_keyboard_|shifted~3 ; 2 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[5][0]~66 ; 2 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[7][2]~60 ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|Selector13~0 ; 2 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[3][2]~53 ; 2 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[3][3]~48 ; 2 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[3][2]~50 ; 2 ; ; ula:ula_|clocks:clocks_|counter[0] ; 2 ; -; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~30 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mRead~28 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_mWrite~14 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_sw_2d~9 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_alu_shift_oe~16 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_bus_db_oe~7 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_bus_db_oe~2 ; 2 ; +; z80_top_direct_n:z80_|execute:execute_|ctl_sw_2u~3 ; 2 ; +---------------------------------------------------------------------------------------------------------------------------------+---------+ @@ -11586,7 +11586,7 @@ Implementation Port B Width : 8 Implementation Bits : 131072 M9Ks : 16 MIF : ula/test_scr.hex -Location : M9K_X33_Y22_N0, M9K_X33_Y24_N0, M9K_X33_Y31_N0, M9K_X33_Y28_N0, M9K_X22_Y28_N0, M9K_X22_Y27_N0, M9K_X22_Y31_N0, M9K_X22_Y23_N0, M9K_X22_Y25_N0, M9K_X22_Y22_N0, M9K_X33_Y29_N0, M9K_X22_Y26_N0, M9K_X33_Y27_N0, M9K_X33_Y25_N0, M9K_X33_Y26_N0, M9K_X22_Y24_N0 +Location : M9K_X33_Y26_N0, M9K_X33_Y30_N0, M9K_X22_Y25_N0, M9K_X22_Y27_N0, M9K_X22_Y21_N0, M9K_X22_Y28_N0, M9K_X22_Y22_N0, M9K_X22_Y30_N0, M9K_X22_Y24_N0, M9K_X33_Y27_N0, M9K_X33_Y25_N0, M9K_X33_Y28_N0, M9K_X22_Y23_N0, M9K_X22_Y26_N0, M9K_X33_Y23_N0, M9K_X33_Y24_N0 Mixed Width RDW Mode : Don't care Port A RDW Mode : Old data Port B RDW Mode : Old data @@ -11612,7 +11612,7 @@ Implementation Port B Width : -- Implementation Bits : 262144 M9Ks : 32 MIF : led_patterns.mif -Location : M9K_X33_Y19_N0, M9K_X33_Y18_N0, M9K_X33_Y15_N0, M9K_X33_Y20_N0, M9K_X33_Y12_N0, M9K_X33_Y8_N0, M9K_X22_Y12_N0, M9K_X33_Y9_N0, M9K_X22_Y13_N0, M9K_X33_Y16_N0, M9K_X33_Y13_N0, M9K_X33_Y14_N0, M9K_X22_Y11_N0, M9K_X22_Y5_N0, M9K_X22_Y15_N0, M9K_X22_Y18_N0, M9K_X22_Y8_N0, M9K_X22_Y16_N0, M9K_X22_Y3_N0, M9K_X22_Y14_N0, M9K_X22_Y6_N0, M9K_X22_Y7_N0, M9K_X22_Y9_N0, M9K_X33_Y23_N0, M9K_X33_Y11_N0, M9K_X33_Y6_N0, M9K_X33_Y10_N0, M9K_X22_Y10_N0, M9K_X33_Y5_N0, M9K_X33_Y7_N0, M9K_X33_Y4_N0, M9K_X22_Y4_N0 +Location : M9K_X33_Y12_N0, M9K_X33_Y8_N0, M9K_X33_Y10_N0, M9K_X33_Y7_N0, M9K_X22_Y6_N0, M9K_X22_Y12_N0, M9K_X22_Y9_N0, M9K_X22_Y5_N0, M9K_X22_Y18_N0, M9K_X22_Y15_N0, M9K_X22_Y19_N0, M9K_X22_Y17_N0, M9K_X22_Y16_N0, M9K_X22_Y13_N0, M9K_X22_Y14_N0, M9K_X33_Y14_N0, M9K_X33_Y6_N0, M9K_X33_Y11_N0, M9K_X33_Y9_N0, M9K_X33_Y5_N0, M9K_X33_Y15_N0, M9K_X33_Y19_N0, M9K_X33_Y22_N0, M9K_X33_Y17_N0, M9K_X22_Y7_N0, M9K_X22_Y11_N0, M9K_X22_Y10_N0, M9K_X22_Y8_N0, M9K_X33_Y16_N0, M9K_X33_Y20_N0, M9K_X33_Y21_N0, M9K_X33_Y18_N0 Mixed Width RDW Mode : Don't care Port A RDW Mode : Old data Port B RDW Mode : Old data @@ -11638,7 +11638,7 @@ Implementation Port B Width : -- Implementation Bits : 131072 M9Ks : 16 MIF : ./rom/gw03.hex -Location : M9K_X33_Y32_N0, M9K_X33_Y21_N0, M9K_X22_Y17_N0, M9K_X33_Y17_N0, M9K_X22_Y30_N0, M9K_X22_Y20_N0, M9K_X22_Y19_N0, M9K_X22_Y21_N0, M9K_X22_Y1_N0, M9K_X33_Y3_N0, M9K_X22_Y29_N0, M9K_X33_Y2_N0, M9K_X33_Y33_N0, M9K_X33_Y1_N0, M9K_X33_Y30_N0, M9K_X22_Y2_N0 +Location : M9K_X22_Y2_N0, M9K_X33_Y2_N0, M9K_X22_Y3_N0, M9K_X22_Y29_N0, M9K_X33_Y13_N0, M9K_X22_Y31_N0, M9K_X22_Y32_N0, M9K_X22_Y20_N0, M9K_X33_Y3_N0, M9K_X33_Y4_N0, M9K_X33_Y31_N0, M9K_X33_Y1_N0, M9K_X22_Y4_N0, M9K_X22_Y1_N0, M9K_X33_Y29_N0, M9K_X33_Y32_N0 Mixed Width RDW Mode : Don't care Port A RDW Mode : Old data Port B RDW Mode : Old data @@ -19869,165 +19869,165 @@ RAM content values are presented in the following format: (Binary) (Octal) (Deci +-----------------------+------------------------+ ; Routing Resource Type ; Usage ; +-----------------------+------------------------+ -; Block interconnects ; 5,027 / 71,559 ( 7 % ) ; -; C16 interconnects ; 124 / 2,597 ( 5 % ) ; -; C4 interconnects ; 2,759 / 46,848 ( 6 % ) ; -; Direct links ; 421 / 71,559 ( < 1 % ) ; +; Block interconnects ; 5,028 / 71,559 ( 7 % ) ; +; C16 interconnects ; 112 / 2,597 ( 4 % ) ; +; C4 interconnects ; 2,821 / 46,848 ( 6 % ) ; +; Direct links ; 452 / 71,559 ( < 1 % ) ; ; Global clocks ; 9 / 20 ( 45 % ) ; -; Local interconnects ; 1,200 / 24,624 ( 5 % ) ; -; R24 interconnects ; 107 / 2,496 ( 4 % ) ; -; R4 interconnects ; 2,921 / 62,424 ( 5 % ) ; +; Local interconnects ; 1,182 / 24,624 ( 5 % ) ; +; R24 interconnects ; 119 / 2,496 ( 5 % ) ; +; R4 interconnects ; 3,204 / 62,424 ( 5 % ) ; +-----------------------+------------------------+ +-----------------------------------------------------------------------------+ ; LAB Logic Elements ; +---------------------------------------------+-------------------------------+ -; Number of Logic Elements (Average = 12.95) ; Number of LABs (Total = 185) ; +; Number of Logic Elements (Average = 13.50) ; Number of LABs (Total = 176) ; +---------------------------------------------+-------------------------------+ -; 1 ; 17 ; +; 1 ; 9 ; ; 2 ; 5 ; -; 3 ; 4 ; +; 3 ; 2 ; ; 4 ; 2 ; -; 5 ; 2 ; +; 5 ; 1 ; ; 6 ; 1 ; -; 7 ; 0 ; -; 8 ; 5 ; -; 9 ; 1 ; -; 10 ; 1 ; -; 11 ; 3 ; -; 12 ; 2 ; -; 13 ; 7 ; -; 14 ; 7 ; -; 15 ; 20 ; -; 16 ; 108 ; +; 7 ; 1 ; +; 8 ; 3 ; +; 9 ; 4 ; +; 10 ; 2 ; +; 11 ; 0 ; +; 12 ; 5 ; +; 13 ; 9 ; +; 14 ; 13 ; +; 15 ; 18 ; +; 16 ; 101 ; +---------------------------------------------+-------------------------------+ +--------------------------------------------------------------------+ ; LAB-wide Signals ; +------------------------------------+-------------------------------+ -; LAB-wide Signals (Average = 1.12) ; Number of LABs (Total = 185) ; +; LAB-wide Signals (Average = 1.21) ; Number of LABs (Total = 176) ; +------------------------------------+-------------------------------+ -; 1 Async. clear ; 49 ; -; 1 Clock ; 94 ; +; 1 Async. clear ; 52 ; +; 1 Clock ; 95 ; ; 1 Clock enable ; 35 ; ; 1 Sync. clear ; 1 ; -; 1 Sync. load ; 4 ; -; 2 Async. clears ; 2 ; -; 2 Clock enables ; 19 ; -; 2 Clocks ; 3 ; +; 1 Sync. load ; 3 ; +; 2 Async. clears ; 1 ; +; 2 Clock enables ; 22 ; +; 2 Clocks ; 4 ; +------------------------------------+-------------------------------+ +------------------------------------------------------------------------------+ ; LAB Signals Sourced ; +----------------------------------------------+-------------------------------+ -; Number of Signals Sourced (Average = 15.85) ; Number of LABs (Total = 185) ; +; Number of Signals Sourced (Average = 16.58) ; Number of LABs (Total = 176) ; +----------------------------------------------+-------------------------------+ ; 0 ; 0 ; -; 1 ; 11 ; -; 2 ; 9 ; +; 1 ; 5 ; +; 2 ; 7 ; ; 3 ; 2 ; -; 4 ; 1 ; -; 5 ; 3 ; -; 6 ; 2 ; +; 4 ; 2 ; +; 5 ; 1 ; +; 6 ; 1 ; ; 7 ; 0 ; -; 8 ; 4 ; -; 9 ; 2 ; -; 10 ; 1 ; -; 11 ; 1 ; +; 8 ; 2 ; +; 9 ; 1 ; +; 10 ; 0 ; +; 11 ; 0 ; ; 12 ; 2 ; -; 13 ; 6 ; -; 14 ; 5 ; -; 15 ; 8 ; -; 16 ; 55 ; -; 17 ; 7 ; -; 18 ; 8 ; -; 19 ; 6 ; -; 20 ; 5 ; -; 21 ; 6 ; -; 22 ; 8 ; +; 13 ; 4 ; +; 14 ; 13 ; +; 15 ; 16 ; +; 16 ; 46 ; +; 17 ; 11 ; +; 18 ; 10 ; +; 19 ; 4 ; +; 20 ; 11 ; +; 21 ; 4 ; +; 22 ; 5 ; ; 23 ; 5 ; -; 24 ; 9 ; -; 25 ; 8 ; -; 26 ; 1 ; -; 27 ; 4 ; -; 28 ; 1 ; +; 24 ; 6 ; +; 25 ; 0 ; +; 26 ; 9 ; +; 27 ; 1 ; +; 28 ; 3 ; ; 29 ; 1 ; -; 30 ; 3 ; -; 31 ; 0 ; -; 32 ; 1 ; +; 30 ; 1 ; +; 31 ; 1 ; +; 32 ; 2 ; +----------------------------------------------+-------------------------------+ +---------------------------------------------------------------------------------+ ; LAB Signals Sourced Out ; +-------------------------------------------------+-------------------------------+ -; Number of Signals Sourced Out (Average = 8.41) ; Number of LABs (Total = 185) ; +; Number of Signals Sourced Out (Average = 8.75) ; Number of LABs (Total = 176) ; +-------------------------------------------------+-------------------------------+ ; 0 ; 0 ; -; 1 ; 24 ; -; 2 ; 8 ; -; 3 ; 3 ; -; 4 ; 6 ; -; 5 ; 7 ; -; 6 ; 9 ; -; 7 ; 15 ; -; 8 ; 19 ; -; 9 ; 13 ; +; 1 ; 14 ; +; 2 ; 7 ; +; 3 ; 2 ; +; 4 ; 7 ; +; 5 ; 12 ; +; 6 ; 5 ; +; 7 ; 19 ; +; 8 ; 15 ; +; 9 ; 16 ; ; 10 ; 18 ; -; 11 ; 10 ; -; 12 ; 20 ; -; 13 ; 10 ; -; 14 ; 4 ; -; 15 ; 9 ; +; 11 ; 9 ; +; 12 ; 17 ; +; 13 ; 9 ; +; 14 ; 10 ; +; 15 ; 8 ; ; 16 ; 6 ; -; 17 ; 2 ; +; 17 ; 1 ; ; 18 ; 1 ; -; 19 ; 0 ; -; 20 ; 1 ; +-------------------------------------------------+-------------------------------+ +------------------------------------------------------------------------------+ ; LAB Distinct Inputs ; +----------------------------------------------+-------------------------------+ -; Number of Distinct Inputs (Average = 19.44) ; Number of LABs (Total = 185) ; +; Number of Distinct Inputs (Average = 20.30) ; Number of LABs (Total = 176) ; +----------------------------------------------+-------------------------------+ ; 0 ; 0 ; -; 1 ; 0 ; -; 2 ; 4 ; -; 3 ; 5 ; -; 4 ; 10 ; +; 1 ; 1 ; +; 2 ; 5 ; +; 3 ; 3 ; +; 4 ; 4 ; ; 5 ; 3 ; -; 6 ; 5 ; -; 7 ; 5 ; -; 8 ; 1 ; +; 6 ; 3 ; +; 7 ; 0 ; +; 8 ; 4 ; ; 9 ; 4 ; -; 10 ; 2 ; -; 11 ; 3 ; +; 10 ; 3 ; +; 11 ; 8 ; ; 12 ; 4 ; -; 13 ; 5 ; -; 14 ; 9 ; +; 13 ; 3 ; +; 14 ; 5 ; ; 15 ; 6 ; -; 16 ; 4 ; -; 17 ; 5 ; -; 18 ; 9 ; -; 19 ; 3 ; -; 20 ; 5 ; -; 21 ; 4 ; -; 22 ; 2 ; -; 23 ; 6 ; -; 24 ; 6 ; -; 25 ; 10 ; -; 26 ; 6 ; -; 27 ; 5 ; -; 28 ; 8 ; -; 29 ; 8 ; -; 30 ; 9 ; +; 16 ; 7 ; +; 17 ; 4 ; +; 18 ; 5 ; +; 19 ; 7 ; +; 20 ; 6 ; +; 21 ; 8 ; +; 22 ; 3 ; +; 23 ; 3 ; +; 24 ; 8 ; +; 25 ; 5 ; +; 26 ; 3 ; +; 27 ; 9 ; +; 28 ; 4 ; +; 29 ; 4 ; +; 30 ; 10 ; ; 31 ; 14 ; -; 32 ; 14 ; +; 32 ; 17 ; +; 33 ; 2 ; +; 34 ; 1 ; +----------------------------------------------+-------------------------------+ @@ -22896,11 +22896,11 @@ IO_000042 : Inapplicable +--------------------------------------------------------------------------------+ Source Clock(s) : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Destination Clock(s) : CLOCK_50 -Delay Added in ns : 646.3 +Delay Added in ns : 598.8 Source Clock(s) : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Destination Clock(s) : CLOCK_50,ula_|pll_|altpll_component|auto_generated|pll1|clk[0],I/O -Delay Added in ns : 20.5 +Delay Added in ns : 25.0 +--------------------------------------------------------------------------------+ Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off. @@ -22911,404 +22911,404 @@ This will disable optimization of problematic paths and expose them for further ; Estimated Delay Added for Hold Timing Details ; +--------------------------------------------------------------------------------+ Source Register : ula:ula_|video:video_|vram_address[8] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 -Delay Added in ns : 3.927 - -Source Register : ula:ula_|video:video_|vram_address[12] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 -Delay Added in ns : 3.927 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 +Delay Added in ns : 3.746 Source Register : ula:ula_|video:video_|vram_address[9] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 -Delay Added in ns : 3.925 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 +Delay Added in ns : 3.746 Source Register : ula:ula_|video:video_|vram_address[11] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 -Delay Added in ns : 3.925 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 +Delay Added in ns : 3.746 -Source Register : ula:ula_|video:video_|vram_address[10] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 -Delay Added in ns : 3.878 - -Source Register : ula:ula_|video:video_|vram_address[5] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 -Delay Added in ns : 3.683 - -Source Register : ula:ula_|video:video_|vram_address[6] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 -Delay Added in ns : 3.680 - -Source Register : ula:ula_|video:video_|vram_address[7] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 -Delay Added in ns : 3.680 +Source Register : ula:ula_|video:video_|vram_address[12] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 +Delay Added in ns : 3.746 Source Register : ula:ula_|video:video_|vram_address[0] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 -Delay Added in ns : 3.437 - -Source Register : ula:ula_|video:video_|vram_address[2] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 -Delay Added in ns : 3.437 - -Source Register : ula:ula_|video:video_|vram_address[4] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 -Delay Added in ns : 3.437 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 +Delay Added in ns : 3.447 Source Register : ula:ula_|video:video_|vram_address[1] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 -Delay Added in ns : 3.435 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 +Delay Added in ns : 3.447 + +Source Register : ula:ula_|video:video_|vram_address[2] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 +Delay Added in ns : 3.447 Source Register : ula:ula_|video:video_|vram_address[3] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 -Delay Added in ns : 3.431 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 +Delay Added in ns : 3.447 -Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 -Delay Added in ns : 1.522 +Source Register : ula:ula_|video:video_|vram_address[4] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 +Delay Added in ns : 3.447 + +Source Register : ula:ula_|video:video_|vram_address[5] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 +Delay Added in ns : 3.430 + +Source Register : ula:ula_|video:video_|vram_address[6] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 +Delay Added in ns : 3.418 + +Source Register : ula:ula_|video:video_|vram_address[7] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 +Delay Added in ns : 3.418 + +Source Register : ula:ula_|video:video_|vram_address[10] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 +Delay Added in ns : 3.152 Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0 -Delay Added in ns : 1.458 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_datain_reg0 +Delay Added in ns : 1.790 -Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 -Delay Added in ns : 1.233 +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 +Delay Added in ns : 1.294 -Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0 +Delay Added in ns : 1.292 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 +Delay Added in ns : 1.273 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 +Delay Added in ns : 1.268 + +Source Register : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 +Delay Added in ns : 1.127 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 +Delay Added in ns : 1.093 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 Delay Added in ns : 1.069 -Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26 +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 +Delay Added in ns : 1.050 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 +Delay Added in ns : 1.047 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 +Delay Added in ns : 1.033 + +Source Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 -Delay Added in ns : 1.013 +Delay Added in ns : 0.957 + +Source Register : z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[14] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 +Delay Added in ns : 0.957 + +Source Register : z80_top_direct_n:z80_|resets:resets_|SYNTHESIZED_WIRE_12 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 +Delay Added in ns : 0.957 + +Source Register : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 +Delay Added in ns : 0.890 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0 +Delay Added in ns : 0.865 + +Source Register : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 +Delay Added in ns : 0.831 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0 +Delay Added in ns : 0.724 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0 +Delay Added in ns : 0.688 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0 +Delay Added in ns : 0.687 + +Source Register : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 +Delay Added in ns : 0.671 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0 +Delay Added in ns : 0.648 Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19 Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 -Delay Added in ns : 0.967 +Delay Added in ns : 0.646 -Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11 +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3 Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 -Delay Added in ns : 0.882 - -Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.847 - -Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.827 - -Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 -Delay Added in ns : 0.798 - -Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 -Delay Added in ns : 0.755 - -Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.743 - -Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.724 - -Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 -Delay Added in ns : 0.719 - -Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_datain_reg0 -Delay Added in ns : 0.718 - -Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0 -Delay Added in ns : 0.681 - -Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0 -Delay Added in ns : 0.671 - -Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0 -Delay Added in ns : 0.627 - -Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0 -Delay Added in ns : 0.613 +Delay Added in ns : 0.646 Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16 Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_datain_reg0 -Delay Added in ns : 0.597 +Delay Added in ns : 0.629 -Source Register : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0 +Delay Added in ns : 0.626 + +Source Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 +Delay Added in ns : 0.624 + +Source Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 +Delay Added in ns : 0.624 + +Source Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 +Delay Added in ns : 0.622 + +Source Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 +Delay Added in ns : 0.622 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_datain_reg0 +Delay Added in ns : 0.607 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11 Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 -Delay Added in ns : 0.592 +Delay Added in ns : 0.594 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0 +Delay Added in ns : 0.573 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 +Delay Added in ns : 0.534 + +Source Register : z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[15] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 +Delay Added in ns : 0.513 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 +Delay Added in ns : 0.480 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 +Delay Added in ns : 0.480 + +Source Register : z80_top_direct_n:z80_|data_pins:data_pins_|dout[5] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 +Delay Added in ns : 0.445 + +Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 +Delay Added in ns : 0.445 + +Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|DFFE_m1_ff3 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 +Delay Added in ns : 0.445 + +Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|DFFE_intr_ff3 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 +Delay Added in ns : 0.445 + +Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|wait_iorqinta +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 +Delay Added in ns : 0.445 + +Source Register : z80_top_direct_n:z80_|sequencer:sequencer_|M5 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 +Delay Added in ns : 0.445 + +Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|wait_mrd +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 +Delay Added in ns : 0.445 + +Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|DFFE_mrd_ff3 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 +Delay Added in ns : 0.445 + +Source Register : z80_top_direct_n:z80_|interrupts:interrupts_|in_nmi_ALTERA_SYNTHESIZED +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 +Delay Added in ns : 0.445 + +Source Register : z80_top_direct_n:z80_|interrupts:interrupts_|DFFE_inst44 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 +Delay Added in ns : 0.445 + +Source Register : z80_top_direct_n:z80_|decode_state:decode_state_|in_halt +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 +Delay Added in ns : 0.445 + +Source Register : z80_top_direct_n:z80_|decode_state:decode_state_|DFFE_inst4 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 +Delay Added in ns : 0.445 + +Source Register : z80_top_direct_n:z80_|decode_state:decode_state_|DFFE_instIY1 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 +Delay Added in ns : 0.445 + +Source Register : z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_M4_ff +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 +Delay Added in ns : 0.445 + +Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|mwr_wr +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 +Delay Added in ns : 0.445 + +Source Register : z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_M3_ff +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 +Delay Added in ns : 0.445 + +Source Register : z80_top_direct_n:z80_|decode_state:decode_state_|DFFE_instCB +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 +Delay Added in ns : 0.445 + +Source Register : z80_top_direct_n:z80_|decode_state:decode_state_|DFFE_instED +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 +Delay Added in ns : 0.445 + +Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|SYNTHESIZED_WIRE_15 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 +Delay Added in ns : 0.445 + +Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|wait_iorq +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 +Delay Added in ns : 0.445 + +Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|DFFE_iorq_ff4 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 +Delay Added in ns : 0.445 + +Source Register : z80_top_direct_n:z80_|ir:ir_|opcode[7] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 +Delay Added in ns : 0.445 + +Source Register : z80_top_direct_n:z80_|ir:ir_|opcode[6] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 +Delay Added in ns : 0.445 + +Source Register : z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_M2_ff +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 +Delay Added in ns : 0.445 + +Source Register : z80_top_direct_n:z80_|ir:ir_|opcode[1] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 +Delay Added in ns : 0.445 + +Source Register : z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T3_ff +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 +Delay Added in ns : 0.445 + +Source Register : z80_top_direct_n:z80_|ir:ir_|opcode[0] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 +Delay Added in ns : 0.445 + +Source Register : z80_top_direct_n:z80_|ir:ir_|opcode[2] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 +Delay Added in ns : 0.445 + +Source Register : z80_top_direct_n:z80_|ir:ir_|opcode[3] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 +Delay Added in ns : 0.445 + +Source Register : z80_top_direct_n:z80_|ir:ir_|opcode[5] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 +Delay Added in ns : 0.445 + +Source Register : z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T2_ff +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 +Delay Added in ns : 0.445 + +Source Register : z80_top_direct_n:z80_|ir:ir_|opcode[4] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 +Delay Added in ns : 0.445 + +Source Register : z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T4_ff +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 +Delay Added in ns : 0.445 + +Source Register : z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T1_ff +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 +Delay Added in ns : 0.445 + +Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 +Delay Added in ns : 0.440 + +Source Register : ula:ula_|zx_keyboard:zx_keyboard_|keys[1][3] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 +Delay Added in ns : 0.423 + +Source Register : ula:ula_|zx_keyboard:zx_keyboard_|keys[0][3] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 +Delay Added in ns : 0.423 + +Source Register : ula:ula_|zx_keyboard:zx_keyboard_|keys[2][3] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 +Delay Added in ns : 0.423 + +Source Register : ula:ula_|zx_keyboard:zx_keyboard_|keys[3][3] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 +Delay Added in ns : 0.423 + +Source Register : ula:ula_|zx_keyboard:zx_keyboard_|keys[5][3] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 +Delay Added in ns : 0.423 + +Source Register : ula:ula_|zx_keyboard:zx_keyboard_|keys[4][3] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 +Delay Added in ns : 0.423 + +Source Register : ula:ula_|zx_keyboard:zx_keyboard_|keys[7][3] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 +Delay Added in ns : 0.423 + +Source Register : ula:ula_|zx_keyboard:zx_keyboard_|keys[6][3] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 +Delay Added in ns : 0.423 Source Register : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 -Delay Added in ns : 0.592 +Delay Added in ns : 0.423 + +Source Register : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 +Delay Added in ns : 0.423 Source Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11 Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 -Delay Added in ns : 0.592 - -Source Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 -Delay Added in ns : 0.592 - -Source Register : z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[15] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 -Delay Added in ns : 0.592 - -Source Register : z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[14] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 -Delay Added in ns : 0.592 - -Source Register : z80_top_direct_n:z80_|resets:resets_|SYNTHESIZED_WIRE_12 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 -Delay Added in ns : 0.592 - -Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0 -Delay Added in ns : 0.581 +Delay Added in ns : 0.423 Source Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3 Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 -Delay Added in ns : 0.581 +Delay Added in ns : 0.423 -Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0 -Delay Added in ns : 0.573 - -Source Register : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.524 - -Source Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.524 - -Source Register : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.524 - -Source Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.524 - -Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_datain_reg0 -Delay Added in ns : 0.521 - -Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0 -Delay Added in ns : 0.518 - -Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0 -Delay Added in ns : 0.495 - -Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0 -Delay Added in ns : 0.490 - -Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0 -Delay Added in ns : 0.436 - -Source Register : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0 -Delay Added in ns : 0.433 - -Source Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0 -Delay Added in ns : 0.433 - -Source Register : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0 -Delay Added in ns : 0.433 - -Source Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0 -Delay Added in ns : 0.433 - -Source Register : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_datain_reg0 -Delay Added in ns : 0.433 - -Source Register : ula:ula_|zx_keyboard:zx_keyboard_|keys[0][1] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 - -Source Register : ula:ula_|zx_keyboard:zx_keyboard_|keys[1][1] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 - -Source Register : ula:ula_|zx_keyboard:zx_keyboard_|keys[2][1] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 - -Source Register : ula:ula_|zx_keyboard:zx_keyboard_|keys[3][1] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 - -Source Register : ula:ula_|zx_keyboard:zx_keyboard_|keys[4][1] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 - -Source Register : ula:ula_|zx_keyboard:zx_keyboard_|keys[5][1] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 - -Source Register : ula:ula_|zx_keyboard:zx_keyboard_|keys[6][1] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 - -Source Register : ula:ula_|zx_keyboard:zx_keyboard_|keys[7][1] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 - -Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 - -Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|DFFE_m1_ff3 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 +Source Register : z80_top_direct_n:z80_|data_pins:data_pins_|dout[3] +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 +Delay Added in ns : 0.423 Source Register : z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[13] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 +Delay Added in ns : 0.423 Source Register : z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[8] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 - -Source Register : z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[9] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 - -Source Register : z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[10] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 - -Source Register : z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[11] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 - -Source Register : z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[12] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 - -Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|DFFE_intr_ff3 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 - -Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|wait_iorqinta -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 - -Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|wait_mrd -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 - -Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|DFFE_mrd_ff3 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 - -Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|mwr_wr -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 - -Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|SYNTHESIZED_WIRE_15 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 - -Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|wait_iorq -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 - -Source Register : z80_top_direct_n:z80_|memory_ifc:memory_ifc_|DFFE_iorq_ff4 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 - -Source Register : z80_top_direct_n:z80_|interrupts:interrupts_|in_nmi_ALTERA_SYNTHESIZED -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 - -Source Register : z80_top_direct_n:z80_|interrupts:interrupts_|DFFE_inst44 -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 - -Source Register : z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_M3_ff -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 - -Source Register : z80_top_direct_n:z80_|ir:ir_|opcode[6] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 - -Source Register : z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T4_ff -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 - -Source Register : z80_top_direct_n:z80_|ir:ir_|opcode[0] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 - -Source Register : z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T3_ff -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 - -Source Register : z80_top_direct_n:z80_|decode_state:decode_state_|DFFE_instCB -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 - -Source Register : z80_top_direct_n:z80_|ir:ir_|opcode[1] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 - -Source Register : z80_top_direct_n:z80_|decode_state:decode_state_|DFFE_instED -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 - -Source Register : z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_M2_ff -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 - -Source Register : z80_top_direct_n:z80_|ir:ir_|opcode[2] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 - -Source Register : z80_top_direct_n:z80_|ir:ir_|opcode[7] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 - -Source Register : z80_top_direct_n:z80_|ir:ir_|opcode[5] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 - -Source Register : z80_top_direct_n:z80_|ir:ir_|opcode[4] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 - -Source Register : z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T2_ff -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 - -Source Register : z80_top_direct_n:z80_|ir:ir_|opcode[3] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 - -Source Register : z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T1_ff -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 - -Source Register : z80_top_direct_n:z80_|address_pins:address_pins_|DFFE_apin_latch[0] -Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Delay Added in ns : 0.428 +Destination Register : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 +Delay Added in ns : 0.423 +--------------------------------------------------------------------------------+ Note: This table only shows the top 100 path(s) that have the largest delay added for hold. @@ -23357,7 +23357,7 @@ Warning (332174): Ignored filter at spectrum.sdc(57): KEY1 could not be matched Warning (332174): Ignored filter at spectrum.sdc(54): ula_|pll_|altpll_component|pll|clk[0] could not be matched with a clock Warning (332174): Ignored filter at spectrum.sdc(54): ula_|pll_|altpll_component|pll|clk[1] could not be matched with a clock Warning (332174): Ignored filter at spectrum.sdc(54): ula_|pll_|altpll_component|pll|clk[2] could not be matched with a clock -Warning (332125): Found combinational loop of 511 nodes +Warning (332125): Found combinational loop of 517 nodes Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~3|combout" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~22|datab" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~22|combout" @@ -23365,58 +23365,74 @@ Warning (332125): Found combinational loop of 511 nodes Warning (332126): Node "z80_|alu_control_|db[0]~9|combout" Warning (332126): Node "z80_|alu_control_|db[0]~12|dataa" Warning (332126): Node "z80_|alu_control_|db[0]~12|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~12|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~12|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~17|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~17|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~22|dataa" - Warning (332126): Node "z80_|alu_|db[0]~19|datab" - Warning (332126): Node "z80_|alu_|db[0]~19|combout" + Warning (332126): Node "z80_|alu_|db[0]~14|datab" + Warning (332126): Node "z80_|alu_|db[0]~14|combout" Warning (332126): Node "z80_|sw2_|db_up[0]~0|dataa" Warning (332126): Node "z80_|sw2_|db_up[0]~0|combout" Warning (332126): Node "z80_|alu_control_|db[0]~9|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~26|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~26|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~28|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~28|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~29|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~29|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~30|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~30|combout" + Warning (332126): Node "z80_|alu_|db[0]~13|dataa" + Warning (332126): Node "z80_|alu_|db[0]~13|combout" + Warning (332126): Node "z80_|alu_|db[0]~14|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~4|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~4|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~5|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~5|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~6|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~6|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~30|datab" Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~1|datac" Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~1|combout" Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~2|datab" Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~2|combout" + Warning (332126): Node "z80_|alu_|db_high[3]~4|dataa" + Warning (332126): Node "z80_|alu_|db_high[3]~4|combout" Warning (332126): Node "z80_|alu_|db_high[3]~5|dataa" Warning (332126): Node "z80_|alu_|db_high[3]~5|combout" - Warning (332126): Node "z80_|alu_|db_high[3]~6|dataa" + Warning (332126): Node "z80_|alu_|db_high[3]~6|datac" Warning (332126): Node "z80_|alu_|db_high[3]~6|combout" - Warning (332126): Node "z80_|alu_|db_high[3]~7|datac" + Warning (332126): Node "z80_|alu_|db_high[3]~7|dataa" Warning (332126): Node "z80_|alu_|db_high[3]~7|combout" - Warning (332126): Node "z80_|alu_|db_high[3]~8|dataa" - Warning (332126): Node "z80_|alu_|db_high[3]~8|combout" - Warning (332126): Node "z80_|alu_|db[7]~21|datab" - Warning (332126): Node "z80_|alu_|db[7]~21|combout" - Warning (332126): Node "z80_|alu_|db_high[2]~11|dataa" - Warning (332126): Node "z80_|alu_|db_high[2]~11|combout" + Warning (332126): Node "z80_|alu_|db[7]~12|datab" + Warning (332126): Node "z80_|alu_|db[7]~12|combout" + Warning (332126): Node "z80_|alu_|db_high[3]~5|datab" + Warning (332126): Node "z80_|alu_|db_high[2]~8|dataa" + Warning (332126): Node "z80_|alu_|db_high[2]~8|combout" + Warning (332126): Node "z80_|alu_|db_high[2]~9|dataa" + Warning (332126): Node "z80_|alu_|db_high[2]~9|combout" Warning (332126): Node "z80_|alu_|db_high[2]~12|dataa" Warning (332126): Node "z80_|alu_|db_high[2]~12|combout" - Warning (332126): Node "z80_|alu_|db_high[2]~13|datac" + Warning (332126): Node "z80_|alu_|db_high[2]~13|dataa" Warning (332126): Node "z80_|alu_|db_high[2]~13|combout" - Warning (332126): Node "z80_|alu_|db_high[2]~14|dataa" - Warning (332126): Node "z80_|alu_|db_high[2]~14|combout" - Warning (332126): Node "z80_|alu_|db[6]~23|datab" - Warning (332126): Node "z80_|alu_|db[6]~23|combout" - Warning (332126): Node "z80_|alu_|db_high[2]~12|datab" - Warning (332126): Node "z80_|alu_|db_high[3]~5|datab" + Warning (332126): Node "z80_|alu_|db[6]~22|datab" + Warning (332126): Node "z80_|alu_|db[6]~22|combout" + Warning (332126): Node "z80_|alu_|db_high[3]~4|datab" + Warning (332126): Node "z80_|alu_|db_high[2]~9|datab" Warning (332126): Node "z80_|alu_control_|db[6]~20|dataa" Warning (332126): Node "z80_|alu_control_|db[6]~20|combout" Warning (332126): Node "z80_|alu_control_|db[6]~21|datad" Warning (332126): Node "z80_|alu_control_|db[6]~21|combout" - Warning (332126): Node "z80_|alu_control_|db[6]~22|datad" + Warning (332126): Node "z80_|alu_control_|db[6]~22|datac" Warning (332126): Node "z80_|alu_control_|db[6]~22|combout" Warning (332126): Node "z80_|bus_control_|db[6]~8|datab" Warning (332126): Node "z80_|bus_control_|db[6]~8|combout" Warning (332126): Node "z80_|bus_control_|db[6]~9|dataa" Warning (332126): Node "z80_|bus_control_|db[6]~9|combout" - Warning (332126): Node "z80_|alu_control_|db[6]~21|dataa" + Warning (332126): Node "z80_|sw1_|db_down[6]~1|dataa" + Warning (332126): Node "z80_|sw1_|db_down[6]~1|combout" + Warning (332126): Node "z80_|alu_control_|db[6]~22|dataa" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~79|dataa" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~79|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~80|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~80|datad" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~80|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~81|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~81|datac" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~81|combout" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~82|dataa" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~82|combout" @@ -23427,15 +23443,17 @@ Warning (332125): Found combinational loop of 511 nodes Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~21|dataa" Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~21|combout" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~82|datab" - Warning (332126): Node "z80_|alu_control_|db[6]~22|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_ds[6]~0|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_ds[6]~0|combout" + Warning (332126): Node "z80_|alu_control_|db[6]~22|datab" + Warning (332126): Node "z80_|alu_|db[6]~21|dataa" + Warning (332126): Node "z80_|alu_|db[6]~21|combout" Warning (332126): Node "z80_|alu_|db[6]~22|dataa" - Warning (332126): Node "z80_|alu_|db[6]~22|combout" - Warning (332126): Node "z80_|alu_|db[6]~23|dataa" Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~80|dataa" Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~80|combout" Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~82|datac" Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~82|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~83|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~83|datab" Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~83|combout" Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~84|dataa" Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~84|combout" @@ -23446,99 +23464,106 @@ Warning (332125): Found combinational loop of 511 nodes Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~24|dataa" Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~24|combout" Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~84|datab" - Warning (332126): Node "z80_|alu_|db[6]~22|datab" + Warning (332126): Node "z80_|alu_|db[6]~21|datab" + Warning (332126): Node "z80_|alu_|db_high[1]~16|dataa" + Warning (332126): Node "z80_|alu_|db_high[1]~16|combout" Warning (332126): Node "z80_|alu_|db_high[1]~17|dataa" Warning (332126): Node "z80_|alu_|db_high[1]~17|combout" - Warning (332126): Node "z80_|alu_|db_high[1]~18|dataa" + Warning (332126): Node "z80_|alu_|db_high[1]~18|datac" Warning (332126): Node "z80_|alu_|db_high[1]~18|combout" - Warning (332126): Node "z80_|alu_|db_high[1]~19|datac" + Warning (332126): Node "z80_|alu_|db_high[1]~19|dataa" Warning (332126): Node "z80_|alu_|db_high[1]~19|combout" - Warning (332126): Node "z80_|alu_|db_high[1]~20|dataa" - Warning (332126): Node "z80_|alu_|db_high[1]~20|combout" - Warning (332126): Node "z80_|alu_|db[5]~25|datab" - Warning (332126): Node "z80_|alu_|db[5]~25|combout" - Warning (332126): Node "z80_|alu_|db_high[2]~11|datab" + Warning (332126): Node "z80_|alu_|db[5]~24|datab" + Warning (332126): Node "z80_|alu_|db[5]~24|combout" + Warning (332126): Node "z80_|alu_|db_high[2]~8|datab" + Warning (332126): Node "z80_|alu_|db_high[0]~22|dataa" + Warning (332126): Node "z80_|alu_|db_high[0]~22|combout" Warning (332126): Node "z80_|alu_|db_high[0]~23|dataa" Warning (332126): Node "z80_|alu_|db_high[0]~23|combout" - Warning (332126): Node "z80_|alu_|db_high[0]~24|dataa" + Warning (332126): Node "z80_|alu_|db_high[0]~24|datac" Warning (332126): Node "z80_|alu_|db_high[0]~24|combout" - Warning (332126): Node "z80_|alu_|db_high[0]~25|datac" + Warning (332126): Node "z80_|alu_|db_high[0]~25|dataa" Warning (332126): Node "z80_|alu_|db_high[0]~25|combout" - Warning (332126): Node "z80_|alu_|db_high[0]~26|dataa" - Warning (332126): Node "z80_|alu_|db_high[0]~26|combout" + Warning (332126): Node "z80_|alu_|db[4]~18|datab" + Warning (332126): Node "z80_|alu_|db[4]~18|combout" + Warning (332126): Node "z80_|alu_control_|db[4]~30|dataa" + Warning (332126): Node "z80_|alu_control_|db[4]~30|combout" + Warning (332126): Node "z80_|alu_control_|db[4]~31|datad" + Warning (332126): Node "z80_|alu_control_|db[4]~31|combout" + Warning (332126): Node "z80_|alu_control_|db[4]~32|datad" + Warning (332126): Node "z80_|alu_control_|db[4]~32|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~54|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~54|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~61|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~61|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~62|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~62|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~13|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~13|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~14|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~14|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~15|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~15|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~62|datab" + Warning (332126): Node "z80_|alu_control_|db[4]~30|datac" Warning (332126): Node "z80_|alu_|db[4]~17|datab" Warning (332126): Node "z80_|alu_|db[4]~17|combout" - Warning (332126): Node "z80_|alu_|db_low[3]~7|dataa" - Warning (332126): Node "z80_|alu_|db_low[3]~7|combout" - Warning (332126): Node "z80_|alu_|db_low[3]~8|dataa" - Warning (332126): Node "z80_|alu_|db_low[3]~8|combout" - Warning (332126): Node "z80_|alu_|db_low[3]~11|dataa" - Warning (332126): Node "z80_|alu_|db_low[3]~11|combout" - Warning (332126): Node "z80_|alu_|db_low[3]~25|datac" - Warning (332126): Node "z80_|alu_|db_low[3]~25|combout" - Warning (332126): Node "z80_|alu_|db[3]~10|datab" - Warning (332126): Node "z80_|alu_|db[3]~10|combout" - Warning (332126): Node "z80_|alu_|db[3]~11|dataa" - Warning (332126): Node "z80_|alu_|db[3]~11|combout" - Warning (332126): Node "z80_|alu_|db_low[3]~8|datab" - Warning (332126): Node "z80_|alu_|db_high[0]~23|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~44|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~44|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~46|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~46|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~47|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~47|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~48|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~48|combout" - Warning (332126): Node "z80_|alu_|db[3]~10|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~10|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~10|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~11|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~11|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~12|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~12|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~48|datab" - Warning (332126): Node "z80_|alu_|db_low[2]~2|dataa" - Warning (332126): Node "z80_|alu_|db_low[2]~2|combout" - Warning (332126): Node "z80_|alu_|db_low[2]~3|dataa" - Warning (332126): Node "z80_|alu_|db_low[2]~3|combout" - Warning (332126): Node "z80_|alu_|db_low[2]~24|dataa" - Warning (332126): Node "z80_|alu_|db_low[2]~24|combout" - Warning (332126): Node "z80_|alu_|db[2]~15|datab" - Warning (332126): Node "z80_|alu_|db[2]~15|combout" - Warning (332126): Node "z80_|alu_|db_low[3]~7|datab" - Warning (332126): Node "z80_|alu_control_|db[2]~27|datac" - Warning (332126): Node "z80_|alu_control_|db[2]~27|combout" - Warning (332126): Node "z80_|alu_control_|db[2]~29|datac" - Warning (332126): Node "z80_|alu_control_|db[2]~29|combout" - Warning (332126): Node "z80_|bus_control_|db[2]~12|datab" - Warning (332126): Node "z80_|bus_control_|db[2]~12|combout" - Warning (332126): Node "z80_|bus_control_|db[2]~13|dataa" - Warning (332126): Node "z80_|bus_control_|db[2]~13|combout" - Warning (332126): Node "z80_|alu_control_|db[2]~28|dataa" - Warning (332126): Node "z80_|alu_control_|db[2]~28|combout" - Warning (332126): Node "z80_|alu_control_|db[2]~29|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~39|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~39|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~40|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~40|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~41|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~41|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~42|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~42|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~7|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~7|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~8|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~8|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~9|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~9|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~42|datab" - Warning (332126): Node "z80_|reg_file_|db_lo_ds[2]~2|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_ds[2]~2|combout" - Warning (332126): Node "z80_|alu_control_|db[2]~28|datad" - Warning (332126): Node "z80_|alu_|db[2]~14|dataa" - Warning (332126): Node "z80_|alu_|db[2]~14|combout" - Warning (332126): Node "z80_|alu_|db[2]~15|dataa" + Warning (332126): Node "z80_|alu_|db[4]~18|dataa" + Warning (332126): Node "z80_|bus_control_|db[4]~19|datab" + Warning (332126): Node "z80_|bus_control_|db[4]~19|combout" + Warning (332126): Node "z80_|alu_control_|db[4]~32|dataa" + Warning (332126): Node "z80_|alu_|db_high[3]~2|datab" + Warning (332126): Node "z80_|alu_|db_high[3]~2|combout" + Warning (332126): Node "z80_|alu_|db_high[3]~6|dataa" + Warning (332126): Node "z80_|alu_|db_high[2]~11|datab" + Warning (332126): Node "z80_|alu_|db_high[2]~11|combout" + Warning (332126): Node "z80_|alu_|db_high[2]~12|datac" + Warning (332126): Node "z80_|alu_|db_low[1]~7|datac" + Warning (332126): Node "z80_|alu_|db_low[1]~7|combout" + Warning (332126): Node "z80_|alu_|db_low[1]~9|dataa" + Warning (332126): Node "z80_|alu_|db_low[1]~9|combout" + Warning (332126): Node "z80_|alu_|db_low[1]~12|dataa" + Warning (332126): Node "z80_|alu_|db_low[1]~12|combout" + Warning (332126): Node "z80_|alu_|db[1]~10|datab" + Warning (332126): Node "z80_|alu_|db[1]~10|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~12|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~12|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~14|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~14|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~15|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~15|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~21|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~21|combout" + Warning (332126): Node "z80_|alu_|db[1]~8|datab" + Warning (332126): Node "z80_|alu_|db[1]~8|combout" + Warning (332126): Node "z80_|alu_|db[1]~10|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~0|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~0|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~1|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~1|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~3|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~3|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~21|datab" + Warning (332126): Node "z80_|alu_|db_low[0]~2|dataa" + Warning (332126): Node "z80_|alu_|db_low[0]~2|combout" + Warning (332126): Node "z80_|alu_|db_low[0]~3|dataa" + Warning (332126): Node "z80_|alu_|db_low[0]~3|combout" + Warning (332126): Node "z80_|alu_|db_low[0]~24|dataa" + Warning (332126): Node "z80_|alu_|db_low[0]~24|combout" + Warning (332126): Node "z80_|alu_|db[0]~13|datab" + Warning (332126): Node "z80_|alu_|db_low[2]~21|datab" + Warning (332126): Node "z80_|alu_|db_low[2]~21|combout" + Warning (332126): Node "z80_|alu_|db_low[2]~22|dataa" + Warning (332126): Node "z80_|alu_|db_low[2]~22|combout" + Warning (332126): Node "z80_|alu_|db_low[2]~23|datab" + Warning (332126): Node "z80_|alu_|db_low[2]~23|combout" + Warning (332126): Node "z80_|alu_|db[2]~16|datab" + Warning (332126): Node "z80_|alu_|db[2]~16|combout" + Warning (332126): Node "z80_|alu_|db_low[1]~10|dataa" + Warning (332126): Node "z80_|alu_|db_low[1]~10|combout" + Warning (332126): Node "z80_|alu_|db_low[1]~11|dataa" + Warning (332126): Node "z80_|alu_|db_low[1]~11|combout" + Warning (332126): Node "z80_|alu_|db_low[1]~12|datab" Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~35|dataa" Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~35|combout" Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~37|datac" @@ -23554,45 +23579,126 @@ Warning (332125): Found combinational loop of 511 nodes Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~9|dataa" Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~9|combout" Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~39|datab" - Warning (332126): Node "z80_|alu_|db[2]~14|datab" - Warning (332126): Node "z80_|alu_|db_low[2]~3|datab" - Warning (332126): Node "z80_|alu_|db_low[1]~15|dataa" - Warning (332126): Node "z80_|alu_|db_low[1]~15|combout" - Warning (332126): Node "z80_|alu_|db_low[1]~16|dataa" - Warning (332126): Node "z80_|alu_|db_low[1]~16|combout" - Warning (332126): Node "z80_|alu_|db_low[1]~17|datab" - Warning (332126): Node "z80_|alu_|db_low[1]~17|combout" - Warning (332126): Node "z80_|alu_|db[1]~13|datab" - Warning (332126): Node "z80_|alu_|db[1]~13|combout" - Warning (332126): Node "z80_|alu_|db_low[0]~21|dataa" - Warning (332126): Node "z80_|alu_|db_low[0]~21|combout" - Warning (332126): Node "z80_|alu_|db_low[0]~22|dataa" - Warning (332126): Node "z80_|alu_|db_low[0]~22|combout" - Warning (332126): Node "z80_|alu_|db_low[0]~23|datab" - Warning (332126): Node "z80_|alu_|db_low[0]~23|combout" - Warning (332126): Node "z80_|alu_|db[0]~18|datab" - Warning (332126): Node "z80_|alu_|db[0]~18|combout" - Warning (332126): Node "z80_|alu_|db[0]~19|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~12|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~12|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~14|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~14|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~15|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~15|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~21|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~21|combout" - Warning (332126): Node "z80_|alu_|db[1]~12|datab" - Warning (332126): Node "z80_|alu_|db[1]~12|combout" - Warning (332126): Node "z80_|alu_|db[1]~13|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~0|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~0|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~1|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~1|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~3|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~3|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~21|datab" - Warning (332126): Node "z80_|alu_|db_low[2]~2|datab" - Warning (332126): Node "z80_|alu_|db_low[1]~16|datab" + Warning (332126): Node "z80_|alu_|db[2]~15|datab" + Warning (332126): Node "z80_|alu_|db[2]~15|combout" + Warning (332126): Node "z80_|alu_|db[2]~16|dataa" + Warning (332126): Node "z80_|alu_|db_low[3]~13|datab" + Warning (332126): Node "z80_|alu_|db_low[3]~13|combout" + Warning (332126): Node "z80_|alu_|db_low[3]~14|dataa" + Warning (332126): Node "z80_|alu_|db_low[3]~14|combout" + Warning (332126): Node "z80_|alu_|db_low[3]~17|dataa" + Warning (332126): Node "z80_|alu_|db_low[3]~17|combout" + Warning (332126): Node "z80_|alu_|db_low[3]~25|datac" + Warning (332126): Node "z80_|alu_|db_low[3]~25|combout" + Warning (332126): Node "z80_|alu_|db[3]~19|datab" + Warning (332126): Node "z80_|alu_|db[3]~19|combout" + Warning (332126): Node "z80_|alu_|db[3]~20|dataa" + Warning (332126): Node "z80_|alu_|db[3]~20|combout" + Warning (332126): Node "z80_|alu_|db_high[0]~22|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~44|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~44|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~46|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~46|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~47|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~47|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~48|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~48|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~10|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~10|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~11|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~11|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~12|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~12|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~48|datab" + Warning (332126): Node "z80_|alu_|db[3]~19|dataa" + Warning (332126): Node "z80_|alu_|db_low[3]~14|datab" + Warning (332126): Node "z80_|alu_control_|db[3]~35|datab" + Warning (332126): Node "z80_|alu_control_|db[3]~35|combout" + Warning (332126): Node "z80_|bus_control_|db[3]~21|datab" + Warning (332126): Node "z80_|bus_control_|db[3]~21|combout" + Warning (332126): Node "z80_|alu_|db_high[3]~2|datac" + Warning (332126): Node "z80_|alu_|db_high[2]~11|datad" + Warning (332126): Node "z80_|alu_|db_low[1]~7|dataa" + Warning (332126): Node "z80_|alu_|db_low[0]~4|datac" + Warning (332126): Node "z80_|alu_|db_low[0]~4|combout" + Warning (332126): Node "z80_|alu_|db_low[0]~6|dataa" + Warning (332126): Node "z80_|alu_|db_low[0]~6|combout" + Warning (332126): Node "z80_|alu_|db_low[0]~24|datab" + Warning (332126): Node "z80_|alu_|db_high[0]~20|datac" + Warning (332126): Node "z80_|alu_|db_high[0]~20|combout" + Warning (332126): Node "z80_|alu_|db_high[0]~24|dataa" + Warning (332126): Node "z80_|alu_|db_high[1]~14|datab" + Warning (332126): Node "z80_|alu_|db_high[1]~14|combout" + Warning (332126): Node "z80_|alu_|db_high[1]~18|dataa" + Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3|datad" + Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3|combout" + Warning (332126): Node "z80_|alu_|db_low[2]~19|datab" + Warning (332126): Node "z80_|alu_|db_low[2]~19|combout" + Warning (332126): Node "z80_|alu_|db_low[2]~20|dataa" + Warning (332126): Node "z80_|alu_|db_low[2]~20|combout" + Warning (332126): Node "z80_|alu_|db_low[2]~23|dataa" + Warning (332126): Node "z80_|sw1_|db_down[3]~2|dataa" + Warning (332126): Node "z80_|sw1_|db_down[3]~2|combout" + Warning (332126): Node "z80_|alu_control_|db[3]~34|dataa" + Warning (332126): Node "z80_|alu_control_|db[3]~34|combout" + Warning (332126): Node "z80_|alu_control_|db[3]~35|dataa" + Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2|datab" + Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2|combout" + Warning (332126): Node "z80_|alu_|db_low[3]~16|datab" + Warning (332126): Node "z80_|alu_|db_low[3]~16|combout" + Warning (332126): Node "z80_|alu_|db_low[3]~17|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~46|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~46|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~47|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~47|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~50|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~50|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~51|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~51|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~52|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~52|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~10|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~10|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~11|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~11|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~12|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~12|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~52|datab" + Warning (332126): Node "z80_|alu_control_|db[3]~34|datac" + Warning (332126): Node "z80_|alu_|db[3]~20|datab" + Warning (332126): Node "z80_|alu_|db_low[2]~21|dataa" + Warning (332126): Node "z80_|alu_|db_low[2]~22|datab" + Warning (332126): Node "z80_|alu_control_|db[2]~27|datac" + Warning (332126): Node "z80_|alu_control_|db[2]~27|combout" + Warning (332126): Node "z80_|alu_control_|db[2]~29|datac" + Warning (332126): Node "z80_|alu_control_|db[2]~29|combout" + Warning (332126): Node "z80_|bus_control_|db[2]~12|datab" + Warning (332126): Node "z80_|bus_control_|db[2]~12|combout" + Warning (332126): Node "z80_|bus_control_|db[2]~13|dataa" + Warning (332126): Node "z80_|bus_control_|db[2]~13|combout" + Warning (332126): Node "z80_|alu_control_|db[2]~28|dataa" + Warning (332126): Node "z80_|alu_control_|db[2]~28|combout" + Warning (332126): Node "z80_|alu_control_|db[2]~29|datad" + Warning (332126): Node "z80_|alu_|db[2]~15|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~39|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~39|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~40|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~40|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~41|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~41|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~42|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~42|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_ds[2]~2|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_ds[2]~2|combout" + Warning (332126): Node "z80_|alu_control_|db[2]~28|datad" + Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~7|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~7|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~8|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~8|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~9|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~9|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~42|datab" + Warning (332126): Node "z80_|alu_|db_low[1]~11|datab" Warning (332126): Node "z80_|alu_control_|db[1]~24|datac" Warning (332126): Node "z80_|alu_control_|db[1]~24|combout" Warning (332126): Node "z80_|alu_control_|db[1]~26|datac" @@ -23604,18 +23710,15 @@ Warning (332125): Found combinational loop of 511 nodes Warning (332126): Node "z80_|alu_control_|db[1]~25|dataa" Warning (332126): Node "z80_|alu_control_|db[1]~25|combout" Warning (332126): Node "z80_|alu_control_|db[1]~26|datad" - Warning (332126): Node "z80_|alu_|db[1]~12|dataa" + Warning (332126): Node "z80_|alu_|db[1]~8|dataa" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~29|dataa" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~29|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~30|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~30|datac" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~30|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~31|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~31|datad" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~31|combout" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~32|dataa" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~32|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_ds[1]~1|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_ds[1]~1|combout" - Warning (332126): Node "z80_|alu_control_|db[1]~25|datad" Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~4|dataa" Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~4|combout" Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~5|dataa" @@ -23623,73 +23726,19 @@ Warning (332125): Found combinational loop of 511 nodes Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~6|dataa" Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~6|combout" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~32|datab" - Warning (332126): Node "z80_|alu_control_|db[3]~35|datab" - Warning (332126): Node "z80_|alu_control_|db[3]~35|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~46|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~46|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~47|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~47|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~50|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~50|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~51|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~51|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~52|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~52|combout" - Warning (332126): Node "z80_|alu_control_|db[3]~34|datac" - Warning (332126): Node "z80_|alu_control_|db[3]~34|combout" - Warning (332126): Node "z80_|alu_control_|db[3]~35|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~10|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~10|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~11|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~11|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~12|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~12|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~52|datab" - Warning (332126): Node "z80_|alu_|db[3]~11|datab" - Warning (332126): Node "z80_|bus_control_|db[3]~21|datab" - Warning (332126): Node "z80_|bus_control_|db[3]~21|combout" - Warning (332126): Node "z80_|sw1_|db_down[3]~1|dataa" - Warning (332126): Node "z80_|sw1_|db_down[3]~1|combout" - Warning (332126): Node "z80_|alu_control_|db[3]~34|dataa" - Warning (332126): Node "z80_|alu_|db_high[2]~9|datac" - Warning (332126): Node "z80_|alu_|db_high[2]~9|combout" - Warning (332126): Node "z80_|alu_|db_high[2]~13|dataa" - Warning (332126): Node "z80_|alu_|db_high[3]~27|datab" - Warning (332126): Node "z80_|alu_|db_high[3]~27|combout" - Warning (332126): Node "z80_|alu_|db_high[3]~7|dataa" - Warning (332126): Node "z80_|alu_|db_high[0]~21|datac" - Warning (332126): Node "z80_|alu_|db_high[0]~21|combout" - Warning (332126): Node "z80_|alu_|db_high[0]~25|dataa" - Warning (332126): Node "z80_|alu_|db_low[0]~18|datac" - Warning (332126): Node "z80_|alu_|db_low[0]~18|combout" - Warning (332126): Node "z80_|alu_|db_low[0]~20|dataa" - Warning (332126): Node "z80_|alu_|db_low[0]~20|combout" - Warning (332126): Node "z80_|alu_|db_low[0]~23|dataa" - Warning (332126): Node "z80_|alu_|db_low[1]~12|dataa" - Warning (332126): Node "z80_|alu_|db_low[1]~12|combout" - Warning (332126): Node "z80_|alu_|db_low[1]~14|dataa" - Warning (332126): Node "z80_|alu_|db_low[1]~14|combout" - Warning (332126): Node "z80_|alu_|db_low[1]~17|dataa" - Warning (332126): Node "z80_|alu_|db_high[1]~15|datab" - Warning (332126): Node "z80_|alu_|db_high[1]~15|combout" - Warning (332126): Node "z80_|alu_|db_high[1]~19|dataa" - Warning (332126): Node "z80_|alu_|db_low[2]~4|datac" - Warning (332126): Node "z80_|alu_|db_low[2]~4|combout" - Warning (332126): Node "z80_|alu_|db_low[2]~6|dataa" - Warning (332126): Node "z80_|alu_|db_low[2]~6|combout" - Warning (332126): Node "z80_|alu_|db_low[2]~24|datab" - Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2|datab" - Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2|combout" - Warning (332126): Node "z80_|alu_|db_low[3]~10|datab" - Warning (332126): Node "z80_|alu_|db_low[3]~10|combout" - Warning (332126): Node "z80_|alu_|db_low[3]~11|datab" - Warning (332126): Node "z80_|alu_|db_high[0]~24|datab" - Warning (332126): Node "z80_|alu_|db_high[1]~17|datab" + Warning (332126): Node "z80_|reg_file_|db_lo_ds[1]~1|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_ds[1]~1|combout" + Warning (332126): Node "z80_|alu_control_|db[1]~25|datad" + Warning (332126): Node "z80_|alu_|db_low[0]~4|datab" + Warning (332126): Node "z80_|alu_|db_high[0]~20|datab" + Warning (332126): Node "z80_|alu_|db_high[1]~14|datac" + Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3|dataa" + Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2|dataa" Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~62|dataa" Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~62|combout" Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~64|datac" Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~64|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~65|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~65|datab" Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~65|combout" Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~66|dataa" Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~66|combout" @@ -23700,76 +23749,27 @@ Warning (332125): Found combinational loop of 511 nodes Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~18|dataa" Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~18|combout" Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~66|datab" - Warning (332126): Node "z80_|alu_|db[4]~16|dataa" - Warning (332126): Node "z80_|alu_|db[4]~16|combout" Warning (332126): Node "z80_|alu_|db[4]~17|dataa" - Warning (332126): Node "z80_|alu_control_|db[4]~30|dataa" - Warning (332126): Node "z80_|alu_control_|db[4]~30|combout" - Warning (332126): Node "z80_|alu_control_|db[4]~31|datad" - Warning (332126): Node "z80_|alu_control_|db[4]~31|combout" - Warning (332126): Node "z80_|alu_control_|db[4]~32|datad" - Warning (332126): Node "z80_|alu_control_|db[4]~32|combout" - Warning (332126): Node "z80_|bus_control_|db[4]~19|datab" - Warning (332126): Node "z80_|bus_control_|db[4]~19|combout" - Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2|dataa" - Warning (332126): Node "z80_|alu_|db_high[2]~9|datab" - Warning (332126): Node "z80_|alu_|db_high[3]~27|dataa" - Warning (332126): Node "z80_|alu_|db_high[0]~21|datab" - Warning (332126): Node "z80_|alu_|db_low[0]~18|datab" - Warning (332126): Node "z80_|alu_|db_low[1]~12|datac" - Warning (332126): Node "z80_|alu_|db_high[1]~15|datac" - Warning (332126): Node "z80_|alu_control_|db[4]~32|dataa" - Warning (332126): Node "z80_|alu_|db_low[2]~4|dataa" - Warning (332126): Node "z80_|alu_|db[4]~16|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~54|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~54|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~61|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~61|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~62|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~62|combout" - Warning (332126): Node "z80_|alu_control_|db[4]~30|datac" - Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~13|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~13|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~14|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~14|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~15|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~15|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~62|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~53|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~53|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~55|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~55|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~56|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~56|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~57|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~57|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~13|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~13|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~14|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~14|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~15|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~15|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~57|datab" - Warning (332126): Node "z80_|alu_|db[5]~24|dataa" - Warning (332126): Node "z80_|alu_|db[5]~24|combout" - Warning (332126): Node "z80_|alu_|db[5]~25|dataa" + Warning (332126): Node "z80_|alu_|db_high[1]~16|datab" + Warning (332126): Node "z80_|alu_|db_low[3]~13|dataa" + Warning (332126): Node "z80_|alu_|db_high[0]~23|datab" Warning (332126): Node "z80_|alu_control_|db[5]~15|datab" Warning (332126): Node "z80_|alu_control_|db[5]~15|combout" Warning (332126): Node "z80_|bus_control_|db[5]~15|datab" Warning (332126): Node "z80_|bus_control_|db[5]~15|combout" - Warning (332126): Node "z80_|alu_|db_low[3]~10|datac" - Warning (332126): Node "z80_|alu_|db_high[2]~9|dataa" - Warning (332126): Node "z80_|alu_|db_high[3]~27|datac" - Warning (332126): Node "z80_|alu_|db_high[0]~21|dataa" - Warning (332126): Node "z80_|alu_|db_low[0]~18|dataa" - Warning (332126): Node "z80_|alu_|db_low[1]~12|datab" - Warning (332126): Node "z80_|alu_|db_high[1]~15|dataa" + Warning (332126): Node "z80_|alu_|db_high[3]~2|dataa" + Warning (332126): Node "z80_|alu_|db_high[2]~11|dataa" + Warning (332126): Node "z80_|alu_|db_low[1]~7|datab" + Warning (332126): Node "z80_|alu_|db_low[0]~4|dataa" + Warning (332126): Node "z80_|alu_|db_high[0]~20|dataa" Warning (332126): Node "z80_|sw1_|db_down[5]~0|dataa" Warning (332126): Node "z80_|sw1_|db_down[5]~0|combout" Warning (332126): Node "z80_|alu_control_|db[5]~14|dataa" Warning (332126): Node "z80_|alu_control_|db[5]~14|combout" Warning (332126): Node "z80_|alu_control_|db[5]~15|dataa" - Warning (332126): Node "z80_|alu_|db_low[2]~4|datab" + Warning (332126): Node "z80_|alu_|db_high[1]~14|dataa" + Warning (332126): Node "z80_|alu_|db_low[2]~19|datac" + Warning (332126): Node "z80_|alu_|db_low[3]~16|datac" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~66|dataa" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~66|combout" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~67|dataa" @@ -23788,8 +23788,58 @@ Warning (332125): Found combinational loop of 511 nodes Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~18|combout" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~72|datab" Warning (332126): Node "z80_|alu_control_|db[5]~14|datac" - Warning (332126): Node "z80_|alu_|db[5]~24|datab" - Warning (332126): Node "z80_|alu_|db_high[1]~18|datab" + Warning (332126): Node "z80_|alu_|db[5]~23|datab" + Warning (332126): Node "z80_|alu_|db[5]~23|combout" + Warning (332126): Node "z80_|alu_|db[5]~24|dataa" + Warning (332126): Node "z80_|alu_|db_high[1]~17|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~53|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~53|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~55|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~55|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~56|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~56|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~57|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~57|combout" + Warning (332126): Node "z80_|alu_|db[5]~23|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~13|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~13|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~14|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~14|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~15|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~15|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~57|datab" + Warning (332126): Node "z80_|alu_control_|db[7]~16|datac" + Warning (332126): Node "z80_|alu_control_|db[7]~16|combout" + Warning (332126): Node "z80_|alu_control_|db[7]~17|datad" + Warning (332126): Node "z80_|alu_control_|db[7]~17|combout" + Warning (332126): Node "z80_|alu_control_|db[7]~18|datad" + Warning (332126): Node "z80_|alu_control_|db[7]~18|combout" + Warning (332126): Node "z80_|alu_control_|db[7]~19|dataa" + Warning (332126): Node "z80_|alu_control_|db[7]~19|combout" + Warning (332126): Node "z80_|bus_control_|db[7]~5|datab" + Warning (332126): Node "z80_|bus_control_|db[7]~5|combout" + Warning (332126): Node "z80_|bus_control_|db[7]~7|dataa" + Warning (332126): Node "z80_|bus_control_|db[7]~7|combout" + Warning (332126): Node "z80_|alu_control_|db[7]~18|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~88|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~88|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~89|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~89|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~90|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~90|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~91|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~91|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~22|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~22|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~23|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~23|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~24|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~24|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~91|datab" + Warning (332126): Node "z80_|alu_control_|db[7]~17|datab" + Warning (332126): Node "z80_|alu_|db[7]~11|dataa" + Warning (332126): Node "z80_|alu_|db[7]~11|combout" + Warning (332126): Node "z80_|alu_|db[7]~12|dataa" Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~71|dataa" Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~71|combout" Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~73|datac" @@ -23805,60 +23855,16 @@ Warning (332125): Found combinational loop of 511 nodes Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~21|dataa" Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~21|combout" Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~75|datab" - Warning (332126): Node "z80_|alu_|db[7]~20|datab" - Warning (332126): Node "z80_|alu_|db[7]~20|combout" - Warning (332126): Node "z80_|alu_|db[7]~21|dataa" + Warning (332126): Node "z80_|alu_|db[7]~11|datab" Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~1|dataa" - Warning (332126): Node "z80_|alu_control_|db[7]~16|datac" - Warning (332126): Node "z80_|alu_control_|db[7]~16|combout" - Warning (332126): Node "z80_|alu_control_|db[7]~18|datac" - Warning (332126): Node "z80_|alu_control_|db[7]~18|combout" - Warning (332126): Node "z80_|bus_control_|db[7]~5|datab" - Warning (332126): Node "z80_|bus_control_|db[7]~5|combout" - Warning (332126): Node "z80_|bus_control_|db[7]~7|dataa" - Warning (332126): Node "z80_|bus_control_|db[7]~7|combout" - Warning (332126): Node "z80_|alu_control_|db[7]~17|dataa" - Warning (332126): Node "z80_|alu_control_|db[7]~17|combout" - Warning (332126): Node "z80_|alu_control_|db[7]~18|datad" - Warning (332126): Node "z80_|alu_|db[7]~20|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~89|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~89|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~90|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~90|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~91|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~91|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~92|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~92|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_ds[7]~0|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_ds[7]~0|combout" - Warning (332126): Node "z80_|alu_control_|db[7]~17|datad" - Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~22|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~22|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~23|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~23|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~24|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~24|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~92|datab" - Warning (332126): Node "z80_|alu_|db_high[3]~6|datab" - Warning (332126): Node "z80_|alu_|db_low[0]~21|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~26|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~26|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~28|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~28|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~29|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~29|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~30|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~30|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~4|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~4|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~5|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~5|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~6|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~6|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~30|datab" - Warning (332126): Node "z80_|alu_|db[0]~18|dataa" - Warning (332126): Node "z80_|alu_|db_low[1]~15|datab" - Warning (332126): Node "z80_|alu_|db_low[0]~22|datab" + Warning (332126): Node "z80_|alu_|db_low[0]~2|datab" + Warning (332126): Node "z80_|alu_|db_low[0]~3|datab" + Warning (332126): Node "z80_|alu_|db_low[1]~10|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~12|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~12|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~17|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~17|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~22|dataa" Warning (332126): Node "z80_|bus_control_|db[0]~17|datab" Warning (332126): Node "z80_|bus_control_|db[0]~17|combout" Warning (332126): Node "z80_|alu_control_|db[0]~8|datab" @@ -23869,7 +23875,7 @@ Warning (332125): Found combinational loop of 511 nodes Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~1|dataa" Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~1|combout" Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~3|dataa" -Critical Warning (332081): Design contains combinational loop of 511 nodes. Estimating the delays through the loop. +Critical Warning (332081): Design contains combinational loop of 517 nodes. Estimating the delays through the loop. Warning (332060): Node: ula:ula_|clocks:clocks_|clk_cpu was determined to be a clock but was found without an associated clock assignment. Warning (332060): Node: KEY[1] was determined to be a clock but was found without an associated clock assignment. Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. @@ -24007,18 +24013,18 @@ Info (170191): Fitter placement operations beginning Info (170137): Fitter placement was successful Info (170192): Fitter placement operations ending: elapsed time is 00:00:03 Info (170193): Fitter routing operations beginning -Info (170089): 7e+02 ns of routing delay (approximately 1.5% of available device routing delay) has been added to meet hold timing. For more information, refer to the Estimated Delay Added for Hold Timing section in the Fitter report. +Info (170089): 6e+02 ns of routing delay (approximately 1.4% of available device routing delay) has been added to meet hold timing. For more information, refer to the Estimated Delay Added for Hold Timing section in the Fitter report. Info (170195): Router estimated average interconnect usage is 4% of the available device resources - Info (170196): Router estimated peak interconnect usage is 26% of the available device resources in the region that extends from location X32_Y11 to location X42_Y22 -Info (170194): Fitter routing operations ending: elapsed time is 00:00:06 + Info (170196): Router estimated peak interconnect usage is 31% of the available device resources in the region that extends from location X21_Y11 to location X31_Y22 +Info (170194): Fitter routing operations ending: elapsed time is 00:00:07 Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. Info (170201): Optimizations that may affect the design's routability were skipped -Info (11888): Total time spent on timing analysis during the Fitter is 1.92 seconds. +Info (11888): Total time spent on timing analysis during the Fitter is 1.90 seconds. Info (334003): Started post-fitting delay annotation Info (334004): Delay annotation completed successfully Info (334003): Started post-fitting delay annotation Info (334004): Delay annotation completed successfully -Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:03 +Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:02 Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information. Warning (169177): 41 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems. Info (169178): Pin SW[0] uses I/O standard 3.3-V LVTTL at M1 @@ -24063,11 +24069,11 @@ Warning (169177): 41 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5- Info (169178): Pin PS2_CLK uses I/O standard 3.3-V LVTTL at D6 Info (169178): Pin AUD_ADCDAT uses I/O standard 3.3-V LVTTL at D8 Info (144001): Generated suppressed messages file /home/benny/work/fpga/spectrum/output_files/spectrum.fit.smsg -Info: Quartus II 32-bit Fitter was successful. 0 errors, 609 warnings - Info: Peak virtual memory: 639 megabytes - Info: Processing ended: Fri Apr 1 18:55:40 2022 +Info: Quartus II 32-bit Fitter was successful. 0 errors, 615 warnings + Info: Peak virtual memory: 634 megabytes + Info: Processing ended: Sat Apr 2 15:53:33 2022 Info: Elapsed time: 00:00:22 - Info: Total CPU time (on all processors): 00:00:21 + Info: Total CPU time (on all processors): 00:00:22 +----------------------------+ diff --git a/output_files/spectrum.fit.summary b/output_files/spectrum.fit.summary index 8b9bb67..a50ef81 100644 --- a/output_files/spectrum.fit.summary +++ b/output_files/spectrum.fit.summary @@ -1,12 +1,12 @@ -Fitter Status : Successful - Fri Apr 1 18:55:39 2022 +Fitter Status : Successful - Sat Apr 2 15:53:32 2022 Quartus II 32-bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition Revision Name : spectrum Top-level Entity Name : spectrum Family : Cyclone IV E Device : EP4CE22F17C6 Timing Models : Final -Total logic elements : 2,396 / 22,320 ( 11 % ) - Total combinational functions : 2,272 / 22,320 ( 10 % ) +Total logic elements : 2,376 / 22,320 ( 11 % ) + Total combinational functions : 2,258 / 22,320 ( 10 % ) Dedicated logic registers : 591 / 22,320 ( 3 % ) Total registers : 600 Total pins : 75 / 154 ( 49 % ) diff --git a/output_files/spectrum.flow.rpt b/output_files/spectrum.flow.rpt index da73600..e5cefb2 100644 --- a/output_files/spectrum.flow.rpt +++ b/output_files/spectrum.flow.rpt @@ -1,5 +1,5 @@ Flow report for spectrum -Fri Apr 1 18:55:53 2022 +Sat Apr 2 15:53:46 2022 Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition @@ -40,15 +40,15 @@ applicable agreement for further details. +---------------------------------------------------------------------------------+ ; Flow Summary ; +------------------------------------+--------------------------------------------+ -; Flow Status ; Successful - Fri Apr 1 18:55:53 2022 ; +; Flow Status ; Successful - Sat Apr 2 15:53:46 2022 ; ; Quartus II 32-bit Version ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ; ; Revision Name ; spectrum ; ; Top-level Entity Name ; spectrum ; ; Family ; Cyclone IV E ; ; Device ; EP4CE22F17C6 ; ; Timing Models ; Final ; -; Total logic elements ; 2,396 / 22,320 ( 11 % ) ; -; Total combinational functions ; 2,272 / 22,320 ( 10 % ) ; +; Total logic elements ; 2,376 / 22,320 ( 11 % ) ; +; Total combinational functions ; 2,258 / 22,320 ( 10 % ) ; ; Dedicated logic registers ; 591 / 22,320 ( 3 % ) ; ; Total registers ; 600 ; ; Total pins ; 75 / 154 ( 49 % ) ; @@ -64,7 +64,7 @@ applicable agreement for further details. +-------------------+---------------------+ ; Option ; Setting ; +-------------------+---------------------+ -; Start date & time ; 04/01/2022 18:55:04 ; +; Start date & time ; 04/02/2022 15:52:58 ; ; Main task ; Compilation ; ; Revision Name ; spectrum ; +-------------------+---------------------+ @@ -74,7 +74,7 @@ applicable agreement for further details. ; Flow Non-Default Global Settings ; +--------------------------------------------------------------------------------+ Assignment Name : COMPILER_SIGNATURE_ID -Value : 0.164882850457192 +Value : 0.164890397819294 Default Value : -- Entity Name : -- Section Id : -- @@ -278,15 +278,15 @@ Section Id : -- ; Flow Elapsed Time ; +--------------------------------------------------------------------------------+ Module Name : Analysis & Synthesis -Elapsed Time : 00:00:13 +Elapsed Time : 00:00:12 Average Processors Used : 1.0 Peak Virtual Memory : 441 MB -Total CPU Time (on all processors) : 00:00:13 +Total CPU Time (on all processors) : 00:00:12 Module Name : Fitter Elapsed Time : 00:00:21 Average Processors Used : 1.0 -Peak Virtual Memory : 639 MB +Peak Virtual Memory : 634 MB Total CPU Time (on all processors) : 00:00:21 Module Name : Assembler @@ -298,8 +298,8 @@ Total CPU Time (on all processors) : 00:00:02 Module Name : TimeQuest Timing Analyzer Elapsed Time : 00:00:04 Average Processors Used : 1.0 -Peak Virtual Memory : 437 MB -Total CPU Time (on all processors) : 00:00:04 +Peak Virtual Memory : 440 MB +Total CPU Time (on all processors) : 00:00:03 Module Name : EDA Netlist Writer Elapsed Time : 00:00:03 @@ -308,10 +308,10 @@ Peak Virtual Memory : 372 MB Total CPU Time (on all processors) : 00:00:03 Module Name : Total -Elapsed Time : 00:00:43 +Elapsed Time : 00:00:42 Average Processors Used : -- Peak Virtual Memory : -- -Total CPU Time (on all processors) : 00:00:43 +Total CPU Time (on all processors) : 00:00:41 +--------------------------------------------------------------------------------+ diff --git a/output_files/spectrum.jdi b/output_files/spectrum.jdi index 72b6f13..b5f84a3 100644 --- a/output_files/spectrum.jdi +++ b/output_files/spectrum.jdi @@ -1,6 +1,6 @@ - + diff --git a/output_files/spectrum.map.rpt b/output_files/spectrum.map.rpt index a963b5f..7398dc0 100644 --- a/output_files/spectrum.map.rpt +++ b/output_files/spectrum.map.rpt @@ -1,5 +1,5 @@ Analysis & Synthesis report for spectrum -Fri Apr 1 18:55:17 2022 +Sat Apr 2 15:53:10 2022 Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition @@ -70,13 +70,13 @@ applicable agreement for further details. +---------------------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +------------------------------------+--------------------------------------------+ -; Analysis & Synthesis Status ; Successful - Fri Apr 1 18:55:17 2022 ; +; Analysis & Synthesis Status ; Successful - Sat Apr 2 15:53:10 2022 ; ; Quartus II 32-bit Version ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ; ; Revision Name ; spectrum ; ; Top-level Entity Name ; spectrum ; ; Family ; Cyclone IV E ; -; Total logic elements ; 2,537 ; -; Total combinational functions ; 2,269 ; +; Total logic elements ; 2,523 ; +; Total combinational functions ; 2,255 ; ; Dedicated logic registers ; 592 ; ; Total registers ; 592 ; ; Total pins ; 75 ; @@ -935,16 +935,16 @@ Library : +---------------------------------------------+---------------------------------+ ; Resource ; Usage ; +---------------------------------------------+---------------------------------+ -; Estimated Total logic elements ; 2,537 ; +; Estimated Total logic elements ; 2,523 ; ; ; ; -; Total combinational functions ; 2269 ; +; Total combinational functions ; 2255 ; ; Logic element usage by number of LUT inputs ; ; -; -- 4 input functions ; 1640 ; -; -- 3 input functions ; 385 ; -; -- <=2 input functions ; 244 ; +; -- 4 input functions ; 1637 ; +; -- 3 input functions ; 372 ; +; -- <=2 input functions ; 246 ; ; ; ; ; Logic elements by mode ; ; -; -- normal mode ; 2216 ; +; -- normal mode ; 2202 ; ; -- arithmetic mode ; 53 ; ; ; ; ; Total registers ; 592 ; @@ -959,8 +959,8 @@ Library : ; ; ; ; Maximum fan-out node ; ula:ula_|clocks:clocks_|clk_cpu ; ; Maximum fan-out ; 436 ; -; Total fan-out ; 11524 ; -; Average fan-out ; 3.74 ; +; Total fan-out ; 11477 ; +; Average fan-out ; 3.75 ; +---------------------------------------------+---------------------------------+ @@ -968,7 +968,7 @@ Library : ; Analysis & Synthesis Resource Utilization by Entity ; +--------------------------------------------------------------------------------+ Compilation Hierarchy Node : |spectrum -LC Combinationals : 2269 (98) +LC Combinationals : 2255 (86) LC Registers : 592 (0) Memory Bits : 524288 DSP Elements : 0 @@ -1028,7 +1028,7 @@ Full Hierarchy Name : |spectrum|ram16:ram0|altsyncram:altsyncram_componen Library Name : work Compilation Hierarchy Node : |ram32:ram1| -LC Combinationals : 16 (0) +LC Combinationals : 24 (0) LC Registers : 4 (0) Memory Bits : 262144 DSP Elements : 0 @@ -1040,7 +1040,7 @@ Full Hierarchy Name : |spectrum|ram32:ram1 Library Name : work Compilation Hierarchy Node : |altsyncram:altsyncram_component| -LC Combinationals : 16 (0) +LC Combinationals : 24 (0) LC Registers : 4 (0) Memory Bits : 262144 DSP Elements : 0 @@ -1052,7 +1052,7 @@ Full Hierarchy Name : |spectrum|ram32:ram1|altsyncram:altsyncram_componen Library Name : work Compilation Hierarchy Node : |altsyncram_g9i1:auto_generated| -LC Combinationals : 16 (0) +LC Combinationals : 24 (0) LC Registers : 4 (4) Memory Bits : 262144 DSP Elements : 0 @@ -1088,7 +1088,7 @@ Full Hierarchy Name : |spectrum|ram32:ram1|altsyncram:altsyncram_componen Library Name : work Compilation Hierarchy Node : |mux_6nb:mux2| -LC Combinationals : 8 (8) +LC Combinationals : 16 (16) LC Registers : 0 (0) Memory Bits : 0 DSP Elements : 0 @@ -1160,7 +1160,7 @@ Full Hierarchy Name : |spectrum|ula:ula_|clocks:clocks_ Library Name : work Compilation Hierarchy Node : |i2c_loader:i2c_loader_| -LC Combinationals : 81 (81) +LC Combinationals : 80 (80) LC Registers : 34 (34) Memory Bits : 0 DSP Elements : 0 @@ -1244,7 +1244,7 @@ Full Hierarchy Name : |spectrum|ula:ula_|video:video_ Library Name : work Compilation Hierarchy Node : |zx_keyboard:zx_keyboard_| -LC Combinationals : 150 (150) +LC Combinationals : 151 (151) LC Registers : 43 (43) Memory Bits : 0 DSP Elements : 0 @@ -1256,7 +1256,7 @@ Full Hierarchy Name : |spectrum|ula:ula_|zx_keyboard:zx_keyboard_ Library Name : work Compilation Hierarchy Node : |z80_top_direct_n:z80_| -LC Combinationals : 1733 (2) +LC Combinationals : 1723 (2) LC Registers : 362 (1) Memory Bits : 0 DSP Elements : 0 @@ -1268,7 +1268,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_ Library Name : work Compilation Hierarchy Node : |address_latch:address_latch_| -LC Combinationals : 48 (16) +LC Combinationals : 46 (16) LC Registers : 16 (16) Memory Bits : 0 DSP Elements : 0 @@ -1280,7 +1280,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|address_latch:addre Library Name : work Compilation Hierarchy Node : |inc_dec:b2v_inst_inc_dec| -LC Combinationals : 32 (14) +LC Combinationals : 30 (13) LC Registers : 0 (0) Memory Bits : 0 DSP Elements : 0 @@ -1292,7 +1292,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|address_latch:addre Library Name : work Compilation Hierarchy Node : |inc_dec_2bit:b2v_dual_adder_0| -LC Combinationals : 4 (4) +LC Combinationals : 3 (3) LC Registers : 0 (0) Memory Bits : 0 DSP Elements : 0 @@ -1376,7 +1376,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|address_pins:addres Library Name : work Compilation Hierarchy Node : |alu:alu_| -LC Combinationals : 130 (77) +LC Combinationals : 130 (76) LC Registers : 20 (20) Memory Bits : 0 DSP Elements : 0 @@ -1400,7 +1400,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu:alu_|alu_bit_se Library Name : work Compilation Hierarchy Node : |alu_core:b2v_core| -LC Combinationals : 20 (0) +LC Combinationals : 21 (0) LC Registers : 0 (0) Memory Bits : 0 DSP Elements : 0 @@ -1424,7 +1424,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu:alu_|alu_core:b Library Name : work Compilation Hierarchy Node : |alu_slice:b2v_alu_slice_bit_1| -LC Combinationals : 4 (4) +LC Combinationals : 5 (5) LC Registers : 0 (0) Memory Bits : 0 DSP Elements : 0 @@ -1544,7 +1544,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|alu_control:alu_con Library Name : work Compilation Hierarchy Node : |alu_flags:alu_flags_| -LC Combinationals : 63 (63) +LC Combinationals : 60 (60) LC Registers : 10 (10) Memory Bits : 0 DSP Elements : 0 @@ -1604,7 +1604,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|data_switch:sw2_ Library Name : work Compilation Hierarchy Node : |data_switch_mask:sw1_| -LC Combinationals : 2 (2) +LC Combinationals : 3 (3) LC Registers : 0 (0) Memory Bits : 0 DSP Elements : 0 @@ -1628,7 +1628,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|decode_state:decode Library Name : work Compilation Hierarchy Node : |execute:execute_| -LC Combinationals : 933 (933) +LC Combinationals : 926 (926) LC Registers : 0 (0) Memory Bits : 0 DSP Elements : 0 @@ -1712,7 +1712,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_control:reg_con Library Name : work Compilation Hierarchy Node : |reg_file:reg_file_| -LC Combinationals : 282 (273) +LC Combinationals : 283 (273) LC Registers : 224 (0) Memory Bits : 0 DSP Elements : 0 @@ -1748,7 +1748,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_| Library Name : work Compilation Hierarchy Node : |reg_latch:b2v_latch_af_hi| -LC Combinationals : 8 (8) +LC Combinationals : 6 (6) LC Registers : 8 (8) Memory Bits : 0 DSP Elements : 0 @@ -1868,7 +1868,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_| Library Name : work Compilation Hierarchy Node : |reg_latch:b2v_latch_hl2_hi| -LC Combinationals : 0 (0) +LC Combinationals : 2 (2) LC Registers : 8 (8) Memory Bits : 0 DSP Elements : 0 @@ -2048,7 +2048,7 @@ Full Hierarchy Name : |spectrum|z80_top_direct_n:z80_|reg_file:reg_file_| Library Name : work Compilation Hierarchy Node : |reg_latch:b2v_latch_wz_lo| -LC Combinationals : 0 (0) +LC Combinationals : 1 (1) LC Registers : 8 (8) Memory Bits : 0 DSP Elements : 0 @@ -2241,9 +2241,9 @@ state.Idle : 1 ; z80_top_direct_n:z80_|clk_delay:clk_delay_|hold_clk_busrq_ALTERA_SYNTHESIZED ; Stuck at GND due to stuck port data_in ; ; ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|address_reg_b[0] ; Stuck at GND due to stuck port data_in ; ; ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_b[0] ; Stuck at GND due to stuck port data_in ; -; rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|out_address_reg_a[0] ; Merged with ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] ; +; rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|out_address_reg_a[0] ; Merged with ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] ; ; ula:ula_|pcm_outr[14] ; Merged with ula:ula_|pcm_outl[14] ; -; rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|address_reg_a[0] ; Merged with ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|address_reg_a[0] ; +; rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|address_reg_a[0] ; Merged with ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[0] ; ; ula:ula_|pcm_outr[13] ; Merged with ula:ula_|pcm_outl[13] ; ; ula:ula_|pcm_outr[12] ; Merged with ula:ula_|pcm_outl[12] ; ; ula:ula_|i2c_loader:i2c_loader_|retries ; Stuck at GND due to stuck port data_in ; @@ -2290,7 +2290,7 @@ Registers Removed due to This Register : ula:ula_|i2c_loader:i2c_loader_|nak +----------------------------------------------------------+---------+ ; ula:ula_|i2s_intf:i2s_intf_|bitcount[4] ; 4 ; ; ula:ula_|i2s_intf:i2s_intf_|bitcount[0] ; 2 ; -; z80_top_direct_n:z80_|resets:resets_|SYNTHESIZED_WIRE_12 ; 138 ; +; z80_top_direct_n:z80_|resets:resets_|SYNTHESIZED_WIRE_12 ; 139 ; ; ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] ; 2 ; ; ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] ; 2 ; ; ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] ; 2 ; @@ -2308,40 +2308,40 @@ Registers Removed due to This Register : ula:ula_|i2c_loader:i2c_loader_|nak ; ula:ula_|zx_keyboard:zx_keyboard_|keys[5][1] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[6][1] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[7][1] ; 2 ; -; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T1_ff ; 59 ; +; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_T1_ff ; 58 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[1][2] ; 2 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[0][2] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[3][2] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[2][2] ; 2 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[0][2] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[5][2] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[4][2] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[7][2] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[6][2] ; 2 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[1][0] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[0][0] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[3][0] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[2][0] ; 2 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[1][0] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[5][0] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[4][0] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[7][0] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[6][0] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[1][3] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[0][3] ; 2 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[3][3] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[2][3] ; 2 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[3][3] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[5][3] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[4][3] ; 2 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[6][3] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[7][3] ; 2 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[1][4] ; 2 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[6][3] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[0][4] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[3][4] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[2][4] ; 2 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[1][4] ; 2 ; +; ula:ula_|zx_keyboard:zx_keyboard_|keys[5][4] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[4][4] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[7][4] ; 2 ; ; ula:ula_|zx_keyboard:zx_keyboard_|keys[6][4] ; 2 ; -; ula:ula_|zx_keyboard:zx_keyboard_|keys[5][4] ; 2 ; -; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_M1_ff ; 68 ; +; z80_top_direct_n:z80_|sequencer:sequencer_|DFFE_M1_ff ; 61 ; ; z80_top_direct_n:z80_|resets:resets_|x1 ; 2 ; ; z80_top_direct_n:z80_|fpga_reset ; 2 ; ; z80_top_direct_n:z80_|memory_ifc:memory_ifc_|DFFE_m1_ff1 ; 1 ; @@ -4948,7 +4948,7 @@ Details : Input port expression (16 bits) is wider than the input port (14 bits Info: ******************************************************************* Info: Running Quartus II 32-bit Analysis & Synthesis Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition - Info: Processing started: Fri Apr 1 18:55:04 2022 + Info: Processing started: Sat Apr 2 15:52:58 2022 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum Warning (20028): Parallel compilation is not licensed and has been disabled Info (12021): Found 1 design units, including 1 entities, in source file spectrum.sv @@ -5389,17 +5389,17 @@ Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" Warning (21074): Design contains 2 input pin(s) that do not drive logic Warning (15610): No output dependent on input pin "SW[0]" Warning (15610): No output dependent on input pin "SW[3]" -Info (21057): Implemented 2747 device resources after synthesis - the final resource count might be different +Info (21057): Implemented 2734 device resources after synthesis - the final resource count might be different Info (21058): Implemented 11 input pins Info (21059): Implemented 62 output pins Info (21060): Implemented 2 bidirectional pins - Info (21061): Implemented 2607 logic cells + Info (21061): Implemented 2594 logic cells Info (21064): Implemented 64 RAM segments Info (21065): Implemented 1 PLLs Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 110 warnings Info: Peak virtual memory: 441 megabytes - Info: Processing ended: Fri Apr 1 18:55:17 2022 - Info: Elapsed time: 00:00:13 + Info: Processing ended: Sat Apr 2 15:53:10 2022 + Info: Elapsed time: 00:00:12 Info: Total CPU time (on all processors): 00:00:13 diff --git a/output_files/spectrum.map.summary b/output_files/spectrum.map.summary index 24e537b..0e2c4e4 100644 --- a/output_files/spectrum.map.summary +++ b/output_files/spectrum.map.summary @@ -1,10 +1,10 @@ -Analysis & Synthesis Status : Successful - Fri Apr 1 18:55:17 2022 +Analysis & Synthesis Status : Successful - Sat Apr 2 15:53:10 2022 Quartus II 32-bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition Revision Name : spectrum Top-level Entity Name : spectrum Family : Cyclone IV E -Total logic elements : 2,537 - Total combinational functions : 2,269 +Total logic elements : 2,523 + Total combinational functions : 2,255 Dedicated logic registers : 592 Total registers : 592 Total pins : 75 diff --git a/output_files/spectrum.sof b/output_files/spectrum.sof index 7a2f56c..1f28bbb 100644 Binary files a/output_files/spectrum.sof and b/output_files/spectrum.sof differ diff --git a/output_files/spectrum.sta.rpt b/output_files/spectrum.sta.rpt index a84d05a..70efcf0 100644 --- a/output_files/spectrum.sta.rpt +++ b/output_files/spectrum.sta.rpt @@ -1,5 +1,5 @@ TimeQuest Timing Analyzer report for spectrum -Fri Apr 1 18:55:48 2022 +Sat Apr 2 15:53:41 2022 Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition @@ -22,10 +22,10 @@ Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition 14. Slow 1200mV 85C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' 15. Slow 1200mV 85C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' 16. Slow 1200mV 85C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' - 17. Slow 1200mV 85C Model Hold: 'CLOCK_50' - 18. Slow 1200mV 85C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' - 19. Slow 1200mV 85C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' - 20. Slow 1200mV 85C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' + 17. Slow 1200mV 85C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' + 18. Slow 1200mV 85C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' + 19. Slow 1200mV 85C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' + 20. Slow 1200mV 85C Model Hold: 'CLOCK_50' 21. Slow 1200mV 85C Model Recovery: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' 22. Slow 1200mV 85C Model Removal: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' 23. Slow 1200mV 85C Model Minimum Pulse Width: 'CLOCK_50' @@ -49,10 +49,10 @@ Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition 41. Slow 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' 42. Slow 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' 43. Slow 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' - 44. Slow 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' - 45. Slow 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' - 46. Slow 1200mV 0C Model Hold: 'CLOCK_50' - 47. Slow 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' + 44. Slow 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' + 45. Slow 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' + 46. Slow 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' + 47. Slow 1200mV 0C Model Hold: 'CLOCK_50' 48. Slow 1200mV 0C Model Recovery: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' 49. Slow 1200mV 0C Model Removal: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' 50. Slow 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50' @@ -163,7 +163,7 @@ Parallel compilation was disabled, but you have multiple processors available. E +--------------------------------------------------------------------------------+ SDC File Path : spectrum.sdc Status : OK -Read at : Fri Apr 1 18:55:45 2022 +Read at : Sat Apr 2 15:53:38 2022 +--------------------------------------------------------------------------------+ @@ -267,22 +267,22 @@ Targets : { ula_|pll_|altpll_component|auto_generated|pll1|clk[2] } +--------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Fmax Summary ; +--------------------------------------------------------------------------------+ -Fmax : 49.07 MHz -Restricted Fmax : 49.07 MHz +Fmax : 50.46 MHz +Restricted Fmax : 50.46 MHz Clock Name : CLOCK_50 Note : -Fmax : 124.66 MHz -Restricted Fmax : 124.66 MHz +Fmax : 129.4 MHz +Restricted Fmax : 129.4 MHz Clock Name : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Note : -Fmax : 161.45 MHz -Restricted Fmax : 161.45 MHz +Fmax : 173.94 MHz +Restricted Fmax : 173.94 MHz Clock Name : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Note : -Fmax : 938.97 MHz +Fmax : 940.73 MHz Restricted Fmax : 500.0 MHz Clock Name : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Note : limit due to minimum period restriction (tmin) @@ -301,20 +301,20 @@ HTML report is unavailable in plain text report export. ; Slow 1200mV 85C Model Setup Summary ; +--------------------------------------------------------------------------------+ Clock : CLOCK_50 -Slack : -18.123 -End Point TNS : -549.338 +Slack : -18.425 +End Point TNS : -546.891 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Slack : -7.533 -End Point TNS : -284.813 +Slack : -6.923 +End Point TNS : -271.506 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Slack : -4.740 -End Point TNS : -42.810 +Slack : -4.745 +End Point TNS : -42.191 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] -Slack : -2.914 -End Point TNS : -2.914 +Slack : -2.915 +End Point TNS : -2.915 +--------------------------------------------------------------------------------+ @@ -322,21 +322,21 @@ End Point TNS : -2.914 +--------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Hold Summary ; +--------------------------------------------------------------------------------+ -Clock : CLOCK_50 -Slack : 0.210 -End Point TNS : 0.000 - Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Slack : 0.342 End Point TNS : 0.000 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Slack : 0.344 +Slack : 0.342 End Point TNS : 0.000 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Slack : 0.357 End Point TNS : 0.000 + +Clock : CLOCK_50 +Slack : 0.517 +End Point TNS : 0.000 +--------------------------------------------------------------------------------+ @@ -345,8 +345,8 @@ End Point TNS : 0.000 ; Slow 1200mV 85C Model Recovery Summary ; +--------------------------------------------------------------------------------+ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Slack : -6.223 -End Point TNS : -459.348 +Slack : -6.263 +End Point TNS : -464.840 +--------------------------------------------------------------------------------+ @@ -355,7 +355,7 @@ End Point TNS : -459.348 ; Slow 1200mV 85C Model Removal Summary ; +--------------------------------------------------------------------------------+ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Slack : 3.698 +Slack : 3.657 End Point TNS : 0.000 +--------------------------------------------------------------------------------+ @@ -373,7 +373,7 @@ Slack : 19.602 End Point TNS : 0.000 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Slack : 20.595 +Slack : 20.597 End Point TNS : 0.000 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] @@ -386,905 +386,905 @@ End Point TNS : 0.000 +--------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Setup: 'CLOCK_50' ; +--------------------------------------------------------------------------------+ -Slack : -18.123 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.243 -Data Delay : 7.954 - -Slack : -18.117 -From Node : ula:ula_|video:video_|vga_vc[3] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.243 -Data Delay : 7.948 - -Slack : -18.075 +Slack : -18.425 From Node : ula:ula_|video:video_|vga_hc[4] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.244 -Data Delay : 7.905 +Clock Skew : -0.249 +Data Delay : 8.250 -Slack : -18.071 +Slack : -18.317 From Node : ula:ula_|video:video_|vga_vc[9] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.243 -Data Delay : 7.902 +Clock Skew : -0.249 +Data Delay : 8.142 -Slack : -18.067 +Slack : -18.277 From Node : ula:ula_|video:video_|vga_hc[6] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.244 -Data Delay : 7.897 +Clock Skew : -0.249 +Data Delay : 8.102 -Slack : -18.052 -From Node : ula:ula_|video:video_|vga_vc[8] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.243 -Data Delay : 7.883 - -Slack : -18.038 +Slack : -18.178 From Node : ula:ula_|video:video_|vga_hc[2] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.244 -Data Delay : 7.868 +Clock Skew : -0.249 +Data Delay : 8.003 -Slack : -17.978 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.243 -Data Delay : 7.809 - -Slack : -17.977 -From Node : ula:ula_|video:video_|bits[5] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.248 -Data Delay : 7.803 - -Slack : -17.957 -From Node : ula:ula_|video:video_|vga_hc[1] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.248 -Data Delay : 7.783 - -Slack : -17.929 -From Node : ula:ula_|video:video_|vga_vc[6] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.243 -Data Delay : 7.760 - -Slack : -17.924 -From Node : ula:ula_|video:video_|vga_vc[4] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.243 -Data Delay : 7.755 - -Slack : -17.912 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4 -To Node : GPIO_1[20] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.514 -Data Delay : 7.472 - -Slack : -17.909 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22 -To Node : GPIO_1[22] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.509 -Data Delay : 7.474 - -Slack : -17.904 -From Node : ula:ula_|video:video_|vga_vc[7] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.243 -Data Delay : 7.735 - -Slack : -17.882 -From Node : ula:ula_|video:video_|vga_hc[5] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.244 -Data Delay : 7.712 - -Slack : -17.861 -From Node : ula:ula_|video:video_|vga_vc[0] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.243 -Data Delay : 7.692 - -Slack : -17.852 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : GPIO_1[20] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.241 -Data Delay : 7.685 - -Slack : -17.852 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : GPIO_1[22] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.242 -Data Delay : 7.684 - -Slack : -17.810 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6 -To Node : GPIO_1[22] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.518 -Data Delay : 7.366 - -Slack : -17.798 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : GPIO_1[22] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.241 -Data Delay : 7.631 - -Slack : -17.790 -From Node : ula:ula_|video:video_|vga_vc[5] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.243 -Data Delay : 7.621 - -Slack : -17.747 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1 -To Node : GPIO_1[17] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.524 -Data Delay : 7.297 - -Slack : -17.716 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9 -To Node : GPIO_1[17] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.524 -Data Delay : 7.266 - -Slack : -17.709 -From Node : ula:ula_|video:video_|bits[1] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.248 -Data Delay : 7.535 - -Slack : -17.708 -From Node : ula:ula_|video:video_|vga_hc[9] +Slack : -18.138 +From Node : ula:ula_|video:video_|vga_vc[3] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 Clock Skew : -0.247 -Data Delay : 7.535 +Data Delay : 7.965 -Slack : -17.700 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : GPIO_1[19] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.241 -Data Delay : 7.533 - -Slack : -17.676 -From Node : ula:ula_|video:video_|vga_hc[8] +Slack : -18.132 +From Node : ula:ula_|video:video_|vga_vc[2] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.244 -Data Delay : 7.506 +Clock Skew : -0.247 +Data Delay : 7.959 -Slack : -17.657 +Slack : -18.098 From Node : ula:ula_|video:video_|vga_hc[7] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.244 -Data Delay : 7.487 +Clock Skew : -0.249 +Data Delay : 7.923 -Slack : -17.622 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8 -To Node : GPIO_1[16] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.514 -Data Delay : 7.182 - -Slack : -17.617 -From Node : ula:ula_|video:video_|bits[6] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.248 -Data Delay : 7.443 - -Slack : -17.612 -From Node : ula:ula_|video:video_|frame[4] +Slack : -18.027 +From Node : ula:ula_|video:video_|vga_hc[1] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 Clock Skew : -0.249 -Data Delay : 7.437 +Data Delay : 7.852 -Slack : -17.578 -From Node : ula:ula_|video:video_|bits[7] +Slack : -17.997 +From Node : ula:ula_|video:video_|vga_hc[5] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.248 -Data Delay : 7.404 +Clock Skew : -0.249 +Data Delay : 7.822 -Slack : -17.576 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28 -To Node : GPIO_1[20] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.515 -Data Delay : 7.135 - -Slack : -17.567 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12 -To Node : GPIO_1[20] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.505 -Data Delay : 7.136 - -Slack : -17.554 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20 -To Node : GPIO_1[20] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.515 -Data Delay : 7.113 - -Slack : -17.492 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14 -To Node : GPIO_1[22] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.520 -Data Delay : 7.046 - -Slack : -17.483 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11 -To Node : GPIO_1[19] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.516 -Data Delay : 7.041 - -Slack : -17.477 -From Node : ula:ula_|video:video_|bits[2] +Slack : -17.976 +From Node : ula:ula_|video:video_|vga_vc[6] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.248 -Data Delay : 7.303 +Clock Skew : -0.249 +Data Delay : 7.801 -Slack : -17.475 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30 -To Node : GPIO_1[22] +Slack : -17.952 +From Node : ula:ula_|video:video_|vga_vc[8] +To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.518 -Data Delay : 7.031 +Clock Skew : -0.247 +Data Delay : 7.779 -Slack : -17.460 +Slack : -17.936 +From Node : ula:ula_|video:video_|vga_hc[9] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.249 +Data Delay : 7.761 + +Slack : -17.926 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] To Node : GPIO_1[21] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.241 -Data Delay : 7.293 +Clock Skew : -0.227 +Data Delay : 7.773 -Slack : -17.458 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27 -To Node : GPIO_1[19] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.511 -Data Delay : 7.021 - -Slack : -17.448 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : GPIO_1[17] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.241 -Data Delay : 7.281 - -Slack : -17.445 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : GPIO_1[17] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.242 -Data Delay : 7.277 - -Slack : -17.442 -From Node : ula:ula_|video:video_|bits[3] +Slack : -17.876 +From Node : ula:ula_|video:video_|vga_vc[1] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.248 -Data Delay : 7.268 +Clock Skew : -0.247 +Data Delay : 7.703 -Slack : -17.441 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : GPIO_1[21] +Slack : -17.849 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : GPIO_1[22] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.242 -Data Delay : 7.273 +Clock Skew : -0.227 +Data Delay : 7.696 -Slack : -17.429 +Slack : -17.838 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0 To Node : GPIO_1[16] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.523 -Data Delay : 6.980 +Clock Skew : -0.515 +Data Delay : 7.397 -Slack : -17.425 -From Node : ula:ula_|video:video_|attr[7] +Slack : -17.822 +From Node : ula:ula_|video:video_|bits[5] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.248 -Data Delay : 7.251 +Clock Skew : -0.247 +Data Delay : 7.649 -Slack : -17.393 +Slack : -17.822 +From Node : ula:ula_|video:video_|vga_vc[0] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.247 +Data Delay : 7.649 + +Slack : -17.818 +From Node : ula:ula_|video:video_|vga_vc[4] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.249 +Data Delay : 7.643 + +Slack : -17.806 +From Node : ula:ula_|video:video_|vga_vc[5] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.249 +Data Delay : 7.631 + +Slack : -17.801 +From Node : ula:ula_|video:video_|vga_vc[7] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.249 +Data Delay : 7.626 + +Slack : -17.792 +From Node : ula:ula_|video:video_|vga_hc[8] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.249 +Data Delay : 7.617 + +Slack : -17.792 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : GPIO_1[16] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.227 +Data Delay : 7.639 + +Slack : -17.769 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 +To Node : GPIO_1[19] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.526 +Data Delay : 7.317 + +Slack : -17.761 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : GPIO_1[23] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.232 +Data Delay : 7.603 + +Slack : -17.731 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : GPIO_1[16] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.232 +Data Delay : 7.573 + +Slack : -17.725 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14 +To Node : GPIO_1[22] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.511 +Data Delay : 7.288 + +Slack : -17.721 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : GPIO_1[21] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.232 +Data Delay : 7.563 + +Slack : -17.684 +From Node : ula:ula_|video:video_|bits[6] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.247 +Data Delay : 7.511 + +Slack : -17.682 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : GPIO_1[22] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.232 +Data Delay : 7.524 + +Slack : -17.673 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 +To Node : GPIO_1[16] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.526 +Data Delay : 7.221 + +Slack : -17.653 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8 +To Node : GPIO_1[16] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.515 +Data Delay : 7.212 + +Slack : -17.600 +From Node : ula:ula_|video:video_|bits[1] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.247 +Data Delay : 7.427 + +Slack : -17.586 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16 To Node : GPIO_1[16] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.524 -Data Delay : 6.943 +Clock Skew : -0.516 +Data Delay : 7.144 -Slack : -17.368 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17 -To Node : GPIO_1[17] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.524 -Data Delay : 6.918 - -Slack : -17.351 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25 -To Node : GPIO_1[17] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.523 -Data Delay : 6.902 - -Slack : -17.350 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : GPIO_1[16] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.241 -Data Delay : 7.183 - -Slack : -17.328 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19 -To Node : GPIO_1[19] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.511 -Data Delay : 6.891 - -Slack : -17.322 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3 -To Node : GPIO_1[19] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.515 -Data Delay : 6.881 - -Slack : -17.316 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5 -To Node : GPIO_1[21] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.507 -Data Delay : 6.883 - -Slack : -17.314 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : GPIO_1[18] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.241 -Data Delay : 7.147 - -Slack : -17.300 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24 -To Node : GPIO_1[16] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.524 -Data Delay : 6.850 - -Slack : -17.296 -From Node : ula:ula_|video:video_|vga_hc[3] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.248 -Data Delay : 7.122 - -Slack : -17.274 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : GPIO_1[19] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.242 -Data Delay : 7.106 - -Slack : -17.267 -From Node : ula:ula_|video:video_|bits[4] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.248 -Data Delay : 7.093 - -Slack : -17.247 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2 -To Node : GPIO_1[18] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.513 -Data Delay : 6.808 - -Slack : -17.239 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : GPIO_1[16] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.242 -Data Delay : 7.071 - -Slack : -17.229 +Slack : -17.577 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] To Node : GPIO_1[23] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.241 -Data Delay : 7.062 +Clock Skew : -0.227 +Data Delay : 7.424 -Slack : -17.199 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10 -To Node : GPIO_1[18] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.522 -Data Delay : 6.751 - -Slack : -17.188 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13 -To Node : GPIO_1[21] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.507 -Data Delay : 6.755 - -Slack : -17.162 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18 -To Node : GPIO_1[18] +Slack : -17.544 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24 +To Node : GPIO_1[16] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 Clock Skew : -0.516 -Data Delay : 6.720 +Data Delay : 7.102 -Slack : -17.128 -From Node : ula:ula_|video:video_|bits[0] +Slack : -17.512 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 +To Node : GPIO_1[16] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.523 +Data Delay : 7.063 + +Slack : -17.508 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 +To Node : GPIO_1[22] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.513 +Data Delay : 7.069 + +Slack : -17.503 +From Node : ula:ula_|video:video_|bits[2] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.248 -Data Delay : 6.954 +Clock Skew : -0.247 +Data Delay : 7.330 -Slack : -17.120 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26 +Slack : -17.499 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6 +To Node : GPIO_1[22] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.509 +Data Delay : 7.064 + +Slack : -17.477 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] To Node : GPIO_1[18] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.514 -Data Delay : 6.680 +Clock Skew : -0.227 +Data Delay : 7.324 -Slack : -17.110 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : GPIO_1[18] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.242 -Data Delay : 6.942 - -Slack : -17.095 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29 -To Node : GPIO_1[21] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.519 -Data Delay : 6.650 - -Slack : -17.083 +Slack : -17.476 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7 To Node : GPIO_1[23] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 Clock Skew : -0.522 -Data Delay : 6.635 +Data Delay : 7.028 -Slack : -17.035 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21 -To Node : GPIO_1[21] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.509 -Data Delay : 6.600 - -Slack : -16.837 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23 -To Node : GPIO_1[23] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.520 -Data Delay : 6.391 - -Slack : -16.833 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31 -To Node : GPIO_1[23] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.513 -Data Delay : 6.394 - -Slack : -16.800 -From Node : ula:ula_|video:video_|attr[0] +Slack : -17.472 +From Node : ula:ula_|video:video_|bits[7] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 Clock Skew : -0.247 -Data Delay : 6.627 +Data Delay : 7.299 -Slack : -16.774 +Slack : -17.464 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21 +To Node : GPIO_1[21] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.524 +Data Delay : 7.014 + +Slack : -17.462 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : GPIO_1[17] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.227 +Data Delay : 7.309 + +Slack : -17.457 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2 +To Node : GPIO_1[18] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.507 +Data Delay : 7.024 + +Slack : -17.455 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 +To Node : GPIO_1[22] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.515 +Data Delay : 7.014 + +Slack : -17.452 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : GPIO_1[19] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.227 +Data Delay : 7.299 + +Slack : -17.451 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30 +To Node : GPIO_1[22] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.505 +Data Delay : 7.020 + +Slack : -17.438 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : GPIO_1[17] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.232 +Data Delay : 7.280 + +Slack : -17.435 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 +To Node : GPIO_1[19] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.514 +Data Delay : 6.995 + +Slack : -17.420 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22 +To Node : GPIO_1[22] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.507 +Data Delay : 6.987 + +Slack : -17.417 +From Node : ula:ula_|video:video_|vga_hc[3] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.249 +Data Delay : 7.242 + +Slack : -17.416 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23 To Node : GPIO_1[23] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.242 -Data Delay : 6.606 +Clock Skew : -0.523 +Data Delay : 6.967 -Slack : -16.762 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : VGA_B[3] +Slack : -17.401 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10 +To Node : GPIO_1[18] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.243 -Data Delay : 6.593 +Clock Skew : -0.513 +Data Delay : 6.962 -Slack : -16.756 -From Node : ula:ula_|video:video_|vga_vc[3] -To Node : VGA_B[3] +Slack : -17.398 +From Node : ula:ula_|video:video_|frame[4] +To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.243 -Data Delay : 6.587 +Clock Skew : -0.247 +Data Delay : 7.225 -Slack : -16.714 +Slack : -17.396 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : GPIO_1[18] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.232 +Data Delay : 7.238 + +Slack : -17.385 From Node : ula:ula_|video:video_|vga_hc[4] -To Node : VGA_B[3] +To Node : VGA_R[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.244 -Data Delay : 6.544 +Clock Skew : -0.249 +Data Delay : 7.210 -Slack : -16.710 -From Node : ula:ula_|video:video_|vga_vc[9] -To Node : VGA_B[3] +Slack : -17.374 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17 +To Node : GPIO_1[17] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.243 -Data Delay : 6.541 +Clock Skew : -0.514 +Data Delay : 6.934 -Slack : -16.706 +Slack : -17.357 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13 +To Node : GPIO_1[21] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.524 +Data Delay : 6.907 + +Slack : -17.354 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : GPIO_1[20] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.227 +Data Delay : 7.201 + +Slack : -17.353 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 +To Node : GPIO_1[21] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.534 +Data Delay : 6.893 + +Slack : -17.341 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2 +To Node : GPIO_1[18] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.524 +Data Delay : 6.891 + +Slack : -17.337 +From Node : ula:ula_|video:video_|bits[3] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.247 +Data Delay : 7.164 + +Slack : -17.329 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 +To Node : GPIO_1[21] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.524 +Data Delay : 6.879 + +Slack : -17.329 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19 +To Node : GPIO_1[19] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.514 +Data Delay : 6.889 + +Slack : -17.327 +From Node : ula:ula_|video:video_|attr[7] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.247 +Data Delay : 7.154 + +Slack : -17.324 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29 +To Node : GPIO_1[21] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.524 +Data Delay : 6.874 + +Slack : -17.324 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3 +To Node : GPIO_1[19] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.515 +Data Delay : 6.883 + +Slack : -17.312 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 +To Node : GPIO_1[18] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.514 +Data Delay : 6.872 + +Slack : -17.303 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27 +To Node : GPIO_1[19] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.524 +Data Delay : 6.853 + +Slack : -17.282 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5 +To Node : GPIO_1[21] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.521 +Data Delay : 6.835 + +Slack : -17.277 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18 +To Node : GPIO_1[18] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.509 +Data Delay : 6.842 + +Slack : -17.266 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26 +To Node : GPIO_1[18] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.511 +Data Delay : 6.829 + +Slack : -17.238 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1 +To Node : GPIO_1[17] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.518 +Data Delay : 6.794 + +Slack : -17.237 From Node : ula:ula_|video:video_|vga_hc[6] -To Node : VGA_B[3] +To Node : VGA_R[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.244 -Data Delay : 6.536 +Clock Skew : -0.249 +Data Delay : 7.062 -Slack : -16.702 +Slack : -17.212 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 +To Node : GPIO_1[23] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.533 +Data Delay : 6.753 + +Slack : -17.208 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31 +To Node : GPIO_1[23] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.524 +Data Delay : 6.758 + +Slack : -17.165 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : VGA_R[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.249 +Data Delay : 6.990 + +Slack : -17.164 +From Node : ula:ula_|video:video_|bits[4] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.247 +Data Delay : 6.991 + +Slack : -17.161 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 +To Node : GPIO_1[17] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.515 +Data Delay : 6.720 + +Slack : -17.160 +From Node : ula:ula_|video:video_|vga_vc[9] +To Node : VGA_R[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.249 +Data Delay : 6.985 + +Slack : -17.141 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15 To Node : GPIO_1[23] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.516 -Data Delay : 6.260 +Clock Skew : -0.524 +Data Delay : 6.691 -Slack : -16.691 -From Node : ula:ula_|video:video_|vga_vc[8] -To Node : VGA_B[3] +Slack : -17.138 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9 +To Node : GPIO_1[17] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.243 -Data Delay : 6.522 +Clock Skew : -0.522 +Data Delay : 6.690 -Slack : -16.677 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : VGA_B[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.244 -Data Delay : 6.507 - -Slack : -16.617 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : VGA_B[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.243 -Data Delay : 6.448 - -Slack : -16.616 -From Node : ula:ula_|video:video_|bits[5] -To Node : VGA_B[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.248 -Data Delay : 6.442 - -Slack : -16.596 -From Node : ula:ula_|video:video_|vga_hc[1] -To Node : VGA_B[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.248 -Data Delay : 6.422 - -Slack : -16.590 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : VGA_R[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.243 -Data Delay : 6.421 - -Slack : -16.589 +Slack : -17.113 From Node : ula:ula_|video:video_|vga_vc[3] -To Node : VGA_R[0] +To Node : VGA_R[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.243 -Data Delay : 6.420 +Clock Skew : -0.247 +Data Delay : 6.940 -Slack : -16.568 -From Node : ula:ula_|video:video_|vga_vc[6] -To Node : VGA_B[3] +Slack : -17.113 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12 +To Node : GPIO_1[20] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.243 -Data Delay : 6.399 +Clock Skew : -0.520 +Data Delay : 6.667 -Slack : -16.567 -From Node : ula:ula_|video:video_|vga_hc[4] -To Node : VGA_R[0] +Slack : -17.107 +From Node : ula:ula_|video:video_|vga_vc[2] +To Node : VGA_R[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.244 -Data Delay : 6.397 +Clock Skew : -0.247 +Data Delay : 6.934 -Slack : -16.563 -From Node : ula:ula_|video:video_|vga_vc[4] -To Node : VGA_B[3] +Slack : -17.058 +From Node : ula:ula_|video:video_|vga_hc[7] +To Node : VGA_R[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.243 -Data Delay : 6.394 +Clock Skew : -0.249 +Data Delay : 6.883 -Slack : -16.549 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : VGA_R[0] +Slack : -17.050 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 +To Node : GPIO_1[23] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.244 -Data Delay : 6.379 +Clock Skew : -0.535 +Data Delay : 6.589 -Slack : -16.543 -From Node : ula:ula_|video:video_|vga_vc[7] -To Node : VGA_B[3] +Slack : -17.034 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : GPIO_1[20] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.243 -Data Delay : 6.374 +Clock Skew : -0.232 +Data Delay : 6.876 -Slack : -16.523 -From Node : ula:ula_|video:video_|vga_vc[9] -To Node : VGA_R[0] +Slack : -17.027 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 +To Node : GPIO_1[20] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.243 -Data Delay : 6.354 +Clock Skew : -0.522 +Data Delay : 6.579 -Slack : -16.521 -From Node : ula:ula_|video:video_|vga_hc[5] -To Node : VGA_B[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.244 -Data Delay : 6.351 - -Slack : -16.500 -From Node : ula:ula_|video:video_|vga_vc[0] -To Node : VGA_B[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.243 -Data Delay : 6.331 - -Slack : -16.495 -From Node : ula:ula_|video:video_|vga_vc[8] -To Node : VGA_R[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.243 -Data Delay : 6.326 - -Slack : -16.484 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : VGA_G[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.244 -Data Delay : 6.314 - -Slack : -16.460 -From Node : ula:ula_|video:video_|attr[3] +Slack : -17.025 +From Node : ula:ula_|video:video_|bits[0] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.248 -Data Delay : 6.286 +Clock Skew : -0.247 +Data Delay : 6.852 + +Slack : -17.025 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 +To Node : GPIO_1[17] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.524 +Data Delay : 6.575 + +Slack : -17.014 +From Node : ula:ula_|video:video_|vga_hc[1] +To Node : VGA_R[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.249 +Data Delay : 6.839 + +Slack : -16.986 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25 +To Node : GPIO_1[17] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.516 +Data Delay : 6.544 + +Slack : -16.964 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 +To Node : GPIO_1[20] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.523 +Data Delay : 6.515 + +Slack : -16.959 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : VGA_R[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.249 +Data Delay : 6.784 + +Slack : -16.957 +From Node : ula:ula_|video:video_|vga_hc[5] +To Node : VGA_R[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.249 +Data Delay : 6.782 + +Slack : -16.944 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4 +To Node : GPIO_1[20] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.516 +Data Delay : 6.502 + +Slack : -16.927 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11 +To Node : GPIO_1[19] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.515 +Data Delay : 6.486 +--------------------------------------------------------------------------------+ @@ -1292,905 +1292,905 @@ Data Delay : 6.286 +--------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' ; +--------------------------------------------------------------------------------+ -Slack : -7.533 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0 +Slack : -6.923 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -2.293 -Data Delay : 5.348 +Clock Skew : -1.984 +Data Delay : 5.047 -Slack : -7.427 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 +Slack : -6.749 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -2.284 -Data Delay : 5.251 +Clock Skew : -2.252 +Data Delay : 4.605 -Slack : -7.365 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.290 -Data Delay : 5.183 - -Slack : -7.307 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 +Slack : -6.727 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -2.284 -Data Delay : 5.131 - -Slack : -7.245 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.245 -Data Delay : 5.108 - -Slack : -7.233 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.307 -Data Delay : 5.034 - -Slack : -7.228 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 Clock Skew : -2.251 -Data Delay : 5.085 +Data Delay : 4.584 -Slack : -7.218 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.284 -Data Delay : 5.042 - -Slack : -7.217 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.283 -Data Delay : 5.042 - -Slack : -7.215 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.263 -Data Delay : 5.060 - -Slack : -7.206 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.299 -Data Delay : 5.015 - -Slack : -7.130 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.245 -Data Delay : 4.993 - -Slack : -7.122 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.282 -Data Delay : 4.948 - -Slack : -7.122 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.242 -Data Delay : 4.988 - -Slack : -7.092 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.244 -Data Delay : 4.956 - -Slack : -7.063 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.292 -Data Delay : 4.879 - -Slack : -7.057 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.297 -Data Delay : 4.868 - -Slack : -7.054 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.299 -Data Delay : 4.863 - -Slack : -7.052 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.257 -Data Delay : 4.903 - -Slack : -7.042 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.299 -Data Delay : 4.851 - -Slack : -7.025 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.249 -Data Delay : 4.884 - -Slack : -7.023 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.283 -Data Delay : 4.848 - -Slack : -7.020 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.262 -Data Delay : 4.866 - -Slack : -7.020 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.281 -Data Delay : 4.847 - -Slack : -7.017 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.260 -Data Delay : 4.865 - -Slack : -7.009 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.285 -Data Delay : 4.832 - -Slack : -7.002 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.242 -Data Delay : 4.868 - -Slack : -6.982 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.295 -Data Delay : 4.795 - -Slack : -6.955 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.287 -Data Delay : 4.776 - -Slack : -6.943 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.009 -Data Delay : 5.042 - -Slack : -6.934 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.254 -Data Delay : 4.788 - -Slack : -6.930 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.283 -Data Delay : 4.755 - -Slack : -6.927 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.274 -Data Delay : 4.761 - -Slack : -6.927 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.276 -Data Delay : 4.759 - -Slack : -6.914 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.283 -Data Delay : 4.739 - -Slack : -6.912 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.241 -Data Delay : 4.779 - -Slack : -6.876 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.247 -Data Delay : 4.737 - -Slack : -6.862 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.245 -Data Delay : 4.725 - -Slack : -6.861 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.249 -Data Delay : 4.720 - -Slack : -6.857 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.260 -Data Delay : 4.705 - -Slack : -6.837 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.000 -Data Delay : 4.945 - -Slack : -6.836 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.267 -Data Delay : 4.677 - -Slack : -6.834 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.289 -Data Delay : 4.653 - -Slack : -6.811 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.291 -Data Delay : 4.628 - -Slack : -6.810 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.271 -Data Delay : 4.647 - -Slack : -6.806 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.285 -Data Delay : 4.629 - -Slack : -6.804 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.240 -Data Delay : 4.672 - -Slack : -6.798 +Slack : -6.700 From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -2.253 -Data Delay : 4.653 +Clock Skew : -2.251 +Data Delay : 4.557 -Slack : -6.792 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.241 -Data Delay : 4.659 - -Slack : -6.791 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.287 -Data Delay : 4.612 - -Slack : -6.789 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.232 -Data Delay : 4.665 - -Slack : -6.789 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 +Slack : -6.643 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 Clock Skew : -2.234 -Data Delay : 4.663 +Data Delay : 4.517 -Slack : -6.781 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 +Slack : -6.626 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -2.253 -Data Delay : 4.636 +Clock Skew : -2.234 +Data Delay : 4.500 -Slack : -6.770 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.269 -Data Delay : 4.609 - -Slack : -6.768 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.275 -Data Delay : 4.601 - -Slack : -6.765 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.254 -Data Delay : 4.619 - -Slack : -6.761 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.286 -Data Delay : 4.583 - -Slack : -6.756 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.293 -Data Delay : 4.571 - -Slack : -6.756 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.999 -Data Delay : 4.865 - -Slack : -6.751 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.271 -Data Delay : 4.588 - -Slack : -6.748 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.257 -Data Delay : 4.599 - -Slack : -6.745 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.248 -Data Delay : 4.605 - -Slack : -6.745 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.250 -Data Delay : 4.603 - -Slack : -6.741 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.285 -Data Delay : 4.564 - -Slack : -6.739 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.012 -Data Delay : 4.835 - -Slack : -6.737 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.292 -Data Delay : 4.553 - -Slack : -6.727 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.292 -Data Delay : 4.543 - -Slack : -6.720 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.281 -Data Delay : 4.547 - -Slack : -6.717 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.000 -Data Delay : 4.825 - -Slack : -6.714 +Slack : -6.626 From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -2.244 -Data Delay : 4.578 +Clock Skew : -2.236 +Data Delay : 4.498 -Slack : -6.714 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 +Slack : -6.608 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.251 +Data Delay : 4.465 + +Slack : -6.602 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.254 +Data Delay : 4.456 + +Slack : -6.563 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.984 +Data Delay : 4.687 + +Slack : -6.553 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.257 +Data Delay : 4.404 + +Slack : -6.550 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.984 +Data Delay : 4.674 + +Slack : -6.549 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.256 +Data Delay : 4.401 + +Slack : -6.533 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.984 +Data Delay : 4.657 + +Slack : -6.525 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.248 +Data Delay : 4.385 + +Slack : -6.513 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -2.297 -Data Delay : 4.525 +Clock Skew : -2.252 +Data Delay : 4.369 -Slack : -6.693 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 +Slack : -6.509 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -2.009 -Data Delay : 4.792 +Clock Skew : -2.245 +Data Delay : 4.372 -Slack : -6.692 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0 +Slack : -6.499 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.988 +Data Delay : 4.619 + +Slack : -6.498 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.248 +Data Delay : 4.358 + +Slack : -6.485 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.254 +Data Delay : 4.339 + +Slack : -6.476 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 Clock Skew : -2.244 -Data Delay : 4.556 +Data Delay : 4.340 -Slack : -6.689 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 +Slack : -6.470 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -2.239 -Data Delay : 4.558 +Clock Skew : -2.254 +Data Delay : 4.324 -Slack : -6.683 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0 +Slack : -6.469 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -2.280 -Data Delay : 4.511 +Clock Skew : -2.264 +Data Delay : 4.313 -Slack : -6.681 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 +Slack : -6.468 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -2.302 -Data Delay : 4.487 +Clock Skew : -2.254 +Data Delay : 4.322 -Slack : -6.678 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 +Slack : -6.468 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -2.293 -Data Delay : 4.493 +Clock Skew : -2.256 +Data Delay : 4.320 -Slack : -6.678 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 +Slack : -6.454 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -2.295 -Data Delay : 4.491 +Clock Skew : -2.251 +Data Delay : 4.311 -Slack : -6.674 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0 +Slack : -6.454 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -2.295 -Data Delay : 4.487 +Clock Skew : -2.243 +Data Delay : 4.319 -Slack : -6.658 +Slack : -6.427 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.243 +Data Delay : 4.292 + +Slack : -6.425 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.252 +Data Delay : 4.281 + +Slack : -6.420 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.243 +Data Delay : 4.285 + +Slack : -6.416 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.266 +Data Delay : 4.258 + +Slack : -6.409 From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -2.261 -Data Delay : 4.505 +Clock Skew : -2.249 +Data Delay : 4.268 -Slack : -6.655 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.297 -Data Delay : 4.466 - -Slack : -6.646 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.283 -Data Delay : 4.471 - -Slack : -6.641 +Slack : -6.406 From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -2.266 -Data Delay : 4.483 +Clock Skew : -2.254 +Data Delay : 4.260 -Slack : -6.638 +Slack : -6.406 From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -2.264 -Data Delay : 4.482 +Clock Skew : -2.255 +Data Delay : 4.259 -Slack : -6.629 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 +Slack : -6.400 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.238 +Data Delay : 4.270 + +Slack : -6.390 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.257 +Data Delay : 4.241 + +Slack : -6.365 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.258 +Data Delay : 4.215 + +Slack : -6.362 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.252 +Data Delay : 4.218 + +Slack : -6.361 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.258 +Data Delay : 4.211 + +Slack : -6.329 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.003 +Data Delay : 4.434 + +Slack : -6.323 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.252 +Data Delay : 4.179 + +Slack : -6.282 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -2.280 -Data Delay : 4.457 +Clock Skew : -2.239 +Data Delay : 4.151 -Slack : -6.629 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6 +Slack : -6.279 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.246 +Data Delay : 4.141 + +Slack : -6.246 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -2.264 -Data Delay : 4.473 +Clock Skew : -2.000 +Data Delay : 4.354 -Slack : -6.627 +Slack : -6.242 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.258 +Data Delay : 4.092 + +Slack : -6.241 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.993 +Data Delay : 4.356 + +Slack : -6.234 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.984 +Data Delay : 4.358 + +Slack : -6.230 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.997 +Data Delay : 4.341 + +Slack : -6.227 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.248 +Data Delay : 4.087 + +Slack : -6.227 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.249 +Data Delay : 4.086 + +Slack : -6.224 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.252 +Data Delay : 4.080 + +Slack : -6.224 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.235 +Data Delay : 4.097 + +Slack : -6.219 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.992 +Data Delay : 4.335 + +Slack : -6.212 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.985 +Data Delay : 4.335 + +Slack : -6.205 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.243 +Data Delay : 4.070 + +Slack : -6.192 From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.999 -Data Delay : 4.736 +Clock Skew : -1.992 +Data Delay : 4.308 -Slack : -6.620 +Slack : -6.190 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.262 +Data Delay : 4.036 + +Slack : -6.183 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.246 +Data Delay : 4.045 + +Slack : -6.176 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.244 +Data Delay : 4.040 + +Slack : -6.162 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.241 +Data Delay : 4.029 + +Slack : -6.153 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.252 +Data Delay : 4.009 + +Slack : -6.152 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.244 +Data Delay : 4.016 + +Slack : -6.140 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.252 +Data Delay : 3.996 + +Slack : -6.113 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.257 +Data Delay : 3.964 + +Slack : -6.103 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.257 +Data Delay : 3.954 + +Slack : -6.089 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.256 +Data Delay : 3.941 + +Slack : -6.084 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.992 +Data Delay : 4.200 + +Slack : -6.068 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.988 +Data Delay : 4.188 + +Slack : -6.060 From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 Clock Skew : -2.243 -Data Delay : 4.485 +Data Delay : 3.925 -Slack : -6.614 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 +Slack : -6.051 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -2.272 -Data Delay : 4.450 +Clock Skew : -1.988 +Data Delay : 4.171 -Slack : -6.604 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.279 -Data Delay : 4.433 - -Slack : -6.602 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.256 -Data Delay : 4.454 - -Slack : -6.591 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 +Slack : -6.051 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -2.281 -Data Delay : 4.418 +Clock Skew : -1.990 +Data Delay : 4.169 -Slack : -6.588 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.278 -Data Delay : 4.418 - -Slack : -6.573 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.254 -Data Delay : 4.427 - -Slack : -6.572 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.244 -Data Delay : 4.436 - -Slack : -6.561 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.243 -Data Delay : 4.426 - -Slack : -6.546 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.292 -Data Delay : 4.362 - -Slack : -6.533 +Slack : -6.047 From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -2.252 -Data Delay : 4.389 +Clock Skew : -2.243 +Data Delay : 3.912 -Slack : -6.514 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 +Slack : -6.031 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -2.243 -Data Delay : 4.379 +Clock Skew : -1.994 +Data Delay : 4.145 -Slack : -6.514 +Slack : -6.000 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.998 +Data Delay : 4.110 + +Slack : -5.996 From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -2.254 -Data Delay : 4.368 +Clock Skew : -2.247 +Data Delay : 3.857 + +Slack : -5.983 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.239 +Data Delay : 3.852 + +Slack : -5.980 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.986 +Data Delay : 4.102 + +Slack : -5.961 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.240 +Data Delay : 3.829 + +Slack : -5.935 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.986 +Data Delay : 4.057 + +Slack : -5.934 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.251 +Data Delay : 3.791 + +Slack : -5.918 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.243 +Data Delay : 3.783 + +Slack : -5.917 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.993 +Data Delay : 4.032 + +Slack : -5.894 +From Node : raw_loader_in +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : 0.140 +Data Delay : 4.142 + +Slack : -5.863 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.241 +Data Delay : 3.730 + +Slack : -5.841 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.242 +Data Delay : 3.707 + +Slack : -5.825 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.992 +Data Delay : 3.941 + +Slack : -5.811 +From Node : raw_loader_in +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : 0.143 +Data Delay : 4.062 + +Slack : -5.805 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.990 +Data Delay : 3.923 + +Slack : -5.795 +From Node : raw_loader_in +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : 0.146 +Data Delay : 4.049 + +Slack : -5.716 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.985 +Data Delay : 3.839 + +Slack : -5.705 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.997 +Data Delay : 3.816 + +Slack : -5.705 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.998 +Data Delay : 3.815 + +Slack : -5.697 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.993 +Data Delay : 3.812 + +Slack : -5.684 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.241 +Data Delay : 3.551 + +Slack : -5.668 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.994 +Data Delay : 3.782 + +Slack : -5.661 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.995 +Data Delay : 3.774 + +Slack : -5.565 +From Node : raw_loader_in +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : 0.145 +Data Delay : 3.818 + +Slack : -5.564 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.243 +Data Delay : 3.429 + +Slack : -5.412 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -2.000 +Data Delay : 3.520 + +Slack : -5.410 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.993 +Data Delay : 3.525 +--------------------------------------------------------------------------------+ @@ -2198,905 +2198,905 @@ Data Delay : 4.368 +--------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ; +--------------------------------------------------------------------------------+ -Slack : -4.740 +Slack : -4.745 +From Node : I2C_SDAT +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.161 +Data Delay : 2.963 + +Slack : -4.745 +From Node : I2C_SDAT +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.161 +Data Delay : 2.963 + +Slack : -4.723 From Node : I2C_SDAT To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.193 -Data Delay : 2.831 +Data Delay : 2.814 -Slack : -4.581 -From Node : I2C_SDAT -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.161 -Data Delay : 2.799 - -Slack : -4.581 -From Node : I2C_SDAT -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.161 -Data Delay : 2.799 - -Slack : -4.362 +Slack : -4.108 From Node : I2C_SDAT To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.161 -Data Delay : 2.580 +Clock Skew : 0.190 +Data Delay : 2.677 -Slack : -4.362 +Slack : -4.108 From Node : I2C_SDAT To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.161 -Data Delay : 2.580 +Clock Skew : 0.190 +Data Delay : 2.677 -Slack : -4.362 +Slack : -4.108 From Node : I2C_SDAT To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.161 -Data Delay : 2.580 +Clock Skew : 0.190 +Data Delay : 2.677 -Slack : -4.362 +Slack : -4.108 From Node : I2C_SDAT To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.161 -Data Delay : 2.580 +Clock Skew : 0.190 +Data Delay : 2.677 -Slack : -4.362 +Slack : -4.108 From Node : I2C_SDAT To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.161 -Data Delay : 2.580 +Clock Skew : 0.190 +Data Delay : 2.677 -Slack : -3.957 +Slack : -3.938 From Node : I2C_SDAT To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.161 -Data Delay : 2.175 +Data Delay : 2.156 -Slack : -3.141 +Slack : -3.500 From Node : AUD_ADCDAT To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.170 -Data Delay : 1.690 +Clock Skew : -0.161 +Data Delay : 1.718 -Slack : 16.840 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.577 - -Slack : 16.845 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.572 - -Slack : 16.978 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.439 - -Slack : 16.978 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.439 - -Slack : 16.983 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.434 - -Slack : 16.983 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.434 - -Slack : 16.986 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.431 - -Slack : 17.051 +Slack : 16.987 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.366 +Clock Skew : -0.431 +Data Delay : 3.428 -Slack : 17.051 +Slack : 16.987 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 3.428 + +Slack : 16.987 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.366 +Clock Skew : -0.431 +Data Delay : 3.428 -Slack : 17.051 +Slack : 16.987 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.366 +Clock Skew : -0.431 +Data Delay : 3.428 -Slack : 17.051 +Slack : 16.987 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.366 +Clock Skew : -0.431 +Data Delay : 3.428 -Slack : 17.056 +Slack : 16.988 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.361 +Clock Skew : -0.431 +Data Delay : 3.427 -Slack : 17.056 +Slack : 16.988 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 3.427 + +Slack : 16.988 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.361 +Clock Skew : -0.431 +Data Delay : 3.427 -Slack : 17.056 +Slack : 16.988 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.361 +Clock Skew : -0.431 +Data Delay : 3.427 -Slack : 17.056 +Slack : 16.988 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.361 +Clock Skew : -0.431 +Data Delay : 3.427 -Slack : 17.086 +Slack : 17.088 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 3.327 + +Slack : 17.088 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 3.327 + +Slack : 17.089 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 3.326 + +Slack : 17.089 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 3.326 + +Slack : 17.132 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 3.283 + +Slack : 17.132 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 3.283 + +Slack : 17.132 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 3.283 + +Slack : 17.132 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 3.283 + +Slack : 17.132 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 3.283 + +Slack : 17.188 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.430 +Data Delay : 3.228 + +Slack : 17.189 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.430 +Data Delay : 3.227 + +Slack : 17.216 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.432 +Data Delay : 3.198 + +Slack : 17.216 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.432 +Data Delay : 3.198 + +Slack : 17.217 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.432 +Data Delay : 3.197 + +Slack : 17.217 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.432 +Data Delay : 3.197 + +Slack : 17.231 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 3.184 + +Slack : 17.231 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.331 - -Slack : 17.117 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.300 - -Slack : 17.117 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.300 - -Slack : 17.140 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.277 - -Slack : 17.140 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.277 - -Slack : 17.145 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.272 - -Slack : 17.145 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.272 - -Slack : 17.159 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 Clock Skew : -0.431 -Data Delay : 3.256 +Data Delay : 3.184 -Slack : 17.159 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.431 -Data Delay : 3.256 - -Slack : 17.164 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.431 -Data Delay : 3.251 - -Slack : 17.164 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.431 -Data Delay : 3.251 - -Slack : 17.189 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.228 - -Slack : 17.189 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.228 - -Slack : 17.189 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.228 - -Slack : 17.189 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.228 - -Slack : 17.224 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.193 - -Slack : 17.224 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.193 - -Slack : 17.256 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.161 - -Slack : 17.259 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.158 - -Slack : 17.259 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.158 - -Slack : 17.259 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.158 - -Slack : 17.259 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.158 - -Slack : 17.259 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.158 - -Slack : 17.264 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.153 - -Slack : 17.264 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.153 - -Slack : 17.264 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.153 - -Slack : 17.264 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.153 - -Slack : 17.264 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.153 - -Slack : 17.289 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.128 - -Slack : 17.289 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.128 - -Slack : 17.297 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.120 - -Slack : 17.297 +Slack : 17.231 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.120 +Clock Skew : -0.431 +Data Delay : 3.184 -Slack : 17.297 +Slack : 17.231 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.120 +Clock Skew : -0.431 +Data Delay : 3.184 -Slack : 17.297 +Slack : 17.231 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.120 - -Slack : 17.308 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 Clock Skew : -0.431 -Data Delay : 3.107 +Data Delay : 3.184 -Slack : 17.308 +Slack : 17.233 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.431 -Data Delay : 3.107 - -Slack : 17.386 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.031 - -Slack : 17.386 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.031 - -Slack : 17.394 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.023 +Clock Skew : -0.431 +Data Delay : 3.182 -Slack : 17.394 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +Slack : 17.233 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.023 +Clock Skew : -0.431 +Data Delay : 3.182 -Slack : 17.405 +Slack : 17.332 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 Clock Skew : -0.431 -Data Delay : 3.010 +Data Delay : 3.083 -Slack : 17.405 +Slack : 17.332 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 3.083 + +Slack : 17.333 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.430 +Data Delay : 3.083 + +Slack : 17.361 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.431 -Data Delay : 3.010 +Clock Skew : -0.432 +Data Delay : 3.053 -Slack : 17.408 +Slack : 17.361 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.009 +Clock Skew : -0.432 +Data Delay : 3.053 -Slack : 17.408 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Slack : 17.366 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.009 +Clock Skew : -0.430 +Data Delay : 3.050 -Slack : 17.408 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Slack : 17.366 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.009 +Clock Skew : -0.430 +Data Delay : 3.050 -Slack : 17.408 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Slack : 17.367 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.009 +Clock Skew : -0.430 +Data Delay : 3.049 -Slack : 17.408 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Slack : 17.367 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 3.009 +Clock Skew : -0.430 +Data Delay : 3.049 Slack : 17.432 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.430 +Data Delay : 2.984 + +Slack : 17.460 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.432 +Data Delay : 2.954 + +Slack : 17.460 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.432 +Data Delay : 2.954 + +Slack : 17.505 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.431 -Data Delay : 2.983 +Clock Skew : -0.079 +Data Delay : 3.262 -Slack : 17.437 +Slack : 17.505 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.079 +Data Delay : 3.262 + +Slack : 17.505 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.079 +Data Delay : 3.262 + +Slack : 17.505 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.079 +Data Delay : 3.262 + +Slack : 17.505 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.079 +Data Delay : 3.262 + +Slack : 17.506 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.431 -Data Delay : 2.978 +Clock Skew : -0.079 +Data Delay : 3.261 -Slack : 17.467 +Slack : 17.506 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.079 +Data Delay : 3.261 + +Slack : 17.506 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.079 +Data Delay : 3.261 + +Slack : 17.506 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.079 +Data Delay : 3.261 + +Slack : 17.506 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.079 +Data Delay : 3.261 + +Slack : 17.511 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.430 +Data Delay : 2.905 + +Slack : 17.511 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.430 +Data Delay : 2.905 + +Slack : 17.605 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.430 +Data Delay : 2.811 + +Slack : 17.605 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.430 +Data Delay : 2.811 + +Slack : 17.605 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.430 +Data Delay : 2.811 + +Slack : 17.605 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.430 +Data Delay : 2.811 + +Slack : 17.606 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.430 +Data Delay : 2.810 + +Slack : 17.606 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.430 +Data Delay : 2.810 + +Slack : 17.606 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.430 +Data Delay : 2.810 + +Slack : 17.606 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.430 +Data Delay : 2.810 + +Slack : 17.610 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.430 +Data Delay : 2.806 + +Slack : 17.610 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.430 +Data Delay : 2.806 + +Slack : 17.614 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.076 +Data Delay : 3.156 + +Slack : 17.615 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.076 +Data Delay : 3.155 + +Slack : 17.636 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 2.950 +Clock Skew : -0.431 +Data Delay : 2.779 -Slack : 17.467 +Slack : 17.636 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 2.779 + +Slack : 17.636 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 2.950 +Clock Skew : -0.431 +Data Delay : 2.779 -Slack : 17.467 +Slack : 17.636 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 2.950 +Clock Skew : -0.431 +Data Delay : 2.779 -Slack : 17.467 +Slack : 17.636 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 2.950 +Clock Skew : -0.431 +Data Delay : 2.779 -Slack : 17.501 +Slack : 17.650 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.079 +Data Delay : 3.117 + +Slack : 17.650 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.079 +Data Delay : 3.117 + +Slack : 17.650 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.079 +Data Delay : 3.117 + +Slack : 17.650 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.079 +Data Delay : 3.117 + +Slack : 17.650 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.079 +Data Delay : 3.117 + +Slack : 17.733 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 2.682 + +Slack : 17.733 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 2.916 - -Slack : 17.505 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 2.912 - -Slack : 17.505 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 2.912 - -Slack : 17.505 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 2.912 - -Slack : 17.505 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 2.912 - -Slack : 17.505 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 2.912 - -Slack : 17.556 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 2.861 - -Slack : 17.556 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 2.861 - -Slack : 17.563 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.076 -Data Delay : 3.207 - -Slack : 17.568 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.076 -Data Delay : 3.202 - -Slack : 17.575 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 Clock Skew : -0.431 -Data Delay : 2.840 +Data Delay : 2.682 -Slack : 17.575 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.431 -Data Delay : 2.840 - -Slack : 17.581 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.431 -Data Delay : 2.834 - -Slack : 17.639 +Slack : 17.733 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 2.682 + +Slack : 17.733 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 2.682 + +Slack : 17.733 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.431 +Data Delay : 2.682 + +Slack : 17.737 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 2.778 +Clock Skew : -0.431 +Data Delay : 2.678 -Slack : 17.639 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +Slack : 17.737 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 2.778 +Clock Skew : -0.431 +Data Delay : 2.678 -Slack : 17.675 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +Slack : 17.749 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 2.742 +Clock Skew : -0.079 +Data Delay : 3.018 -Slack : 17.675 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +Slack : 17.749 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 2.742 +Clock Skew : -0.079 +Data Delay : 3.018 -Slack : 17.675 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +Slack : 17.749 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 2.742 +Clock Skew : -0.079 +Data Delay : 3.018 -Slack : 17.675 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +Slack : 17.749 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 2.742 +Clock Skew : -0.079 +Data Delay : 3.018 -Slack : 17.675 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +Slack : 17.749 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.429 -Data Delay : 2.742 - -Slack : 17.678 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.431 -Data Delay : 2.737 - -Slack : 17.710 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.076 -Data Delay : 3.060 +Clock Skew : -0.079 +Data Delay : 3.018 +--------------------------------------------------------------------------------+ @@ -3104,23 +3104,23 @@ Data Delay : 3.060 +--------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' ; +--------------------------------------------------------------------------------+ -Slack : -2.914 +Slack : -2.915 From Node : SW[2] To Node : ula:ula_|clocks:clocks_|clk_cpu Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Relationship : 0.423 Clock Skew : 0.216 -Data Delay : 1.508 +Data Delay : 1.509 -Slack : 70.424 +Slack : 70.426 From Node : ula:ula_|clocks:clocks_|counter[0] To Node : ula:ula_|clocks:clocks_|clk_cpu Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Relationship : 71.489 Clock Skew : -0.078 -Data Delay : 0.982 +Data Delay : 0.980 Slack : 70.747 From Node : ula:ula_|clocks:clocks_|counter[0] @@ -3143,912 +3143,6 @@ Data Delay : 0.659 -+--------------------------------------------------------------------------------+ -; Slow 1200mV 85C Model Hold: 'CLOCK_50' ; -+--------------------------------------------------------------------------------+ -Slack : 0.210 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.627 -Data Delay : 3.128 - -Slack : 0.266 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.628 -Data Delay : 3.185 - -Slack : 1.266 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.574 -Data Delay : 4.131 - -Slack : 1.277 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.575 -Data Delay : 4.143 - -Slack : 1.289 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.571 -Data Delay : 4.151 - -Slack : 1.310 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.562 -Data Delay : 4.163 - -Slack : 1.311 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.562 -Data Delay : 4.164 - -Slack : 1.311 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.574 -Data Delay : 4.176 - -Slack : 1.313 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.558 -Data Delay : 4.162 - -Slack : 1.318 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.565 -Data Delay : 4.174 - -Slack : 1.328 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.575 -Data Delay : 4.194 - -Slack : 1.332 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.562 -Data Delay : 4.185 - -Slack : 1.333 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.565 -Data Delay : 4.189 - -Slack : 1.370 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.565 -Data Delay : 4.226 - -Slack : 1.390 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.560 -Data Delay : 4.241 - -Slack : 1.397 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.557 -Data Delay : 4.245 - -Slack : 1.404 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.567 -Data Delay : 4.262 - -Slack : 1.406 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.554 -Data Delay : 4.251 - -Slack : 1.412 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.549 -Data Delay : 4.252 - -Slack : 1.417 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.553 -Data Delay : 4.261 - -Slack : 1.418 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.562 -Data Delay : 4.271 - -Slack : 1.422 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.562 -Data Delay : 4.275 - -Slack : 1.426 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.551 -Data Delay : 4.268 - -Slack : 1.427 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.562 -Data Delay : 4.280 - -Slack : 1.431 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.569 -Data Delay : 4.291 - -Slack : 1.438 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.562 -Data Delay : 4.291 - -Slack : 1.443 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.551 -Data Delay : 4.285 - -Slack : 1.446 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.560 -Data Delay : 4.297 - -Slack : 1.449 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.562 -Data Delay : 4.302 - -Slack : 1.455 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.560 -Data Delay : 4.306 - -Slack : 1.456 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.558 -Data Delay : 4.305 - -Slack : 1.460 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.553 -Data Delay : 4.304 - -Slack : 1.470 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.571 -Data Delay : 4.332 - -Slack : 1.472 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.551 -Data Delay : 4.314 - -Slack : 1.474 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.549 -Data Delay : 4.314 - -Slack : 1.474 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.553 -Data Delay : 4.318 - -Slack : 1.476 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.625 -Data Delay : 4.392 - -Slack : 1.477 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.554 -Data Delay : 4.322 - -Slack : 1.479 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.649 -Data Delay : 4.419 - -Slack : 1.483 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.562 -Data Delay : 4.336 - -Slack : 1.489 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.571 -Data Delay : 4.351 - -Slack : 1.492 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.633 -Data Delay : 4.416 - -Slack : 1.496 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.553 -Data Delay : 4.340 - -Slack : 1.496 -From Node : ula:ula_|video:video_|vram_address[10] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.555 -Data Delay : 4.342 - -Slack : 1.497 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.567 -Data Delay : 4.355 - -Slack : 1.499 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.557 -Data Delay : 4.347 - -Slack : 1.502 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.378 -Data Delay : 4.171 - -Slack : 1.505 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.562 -Data Delay : 4.358 - -Slack : 1.507 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.557 -Data Delay : 4.355 - -Slack : 1.508 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.569 -Data Delay : 4.368 - -Slack : 1.509 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.554 -Data Delay : 4.354 - -Slack : 1.512 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.562 -Data Delay : 4.365 - -Slack : 1.517 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.560 -Data Delay : 4.368 - -Slack : 1.517 -From Node : ula:ula_|video:video_|vram_address[12] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.554 -Data Delay : 4.362 - -Slack : 1.519 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.569 -Data Delay : 4.379 - -Slack : 1.522 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.632 -Data Delay : 4.445 - -Slack : 1.523 -From Node : ula:ula_|video:video_|vram_address[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.551 -Data Delay : 4.365 - -Slack : 1.525 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.551 -Data Delay : 4.367 - -Slack : 1.525 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.549 -Data Delay : 4.365 - -Slack : 1.525 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.565 -Data Delay : 4.381 - -Slack : 1.527 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.562 -Data Delay : 4.380 - -Slack : 1.528 -From Node : ula:ula_|video:video_|vram_address[11] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.563 -Data Delay : 4.382 - -Slack : 1.529 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.571 -Data Delay : 4.391 - -Slack : 1.531 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.645 -Data Delay : 4.467 - -Slack : 1.531 -From Node : ula:ula_|video:video_|vram_address[11] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.552 -Data Delay : 4.374 - -Slack : 1.532 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.557 -Data Delay : 4.380 - -Slack : 1.533 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.641 -Data Delay : 4.465 - -Slack : 1.533 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.558 -Data Delay : 4.382 - -Slack : 1.534 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.551 -Data Delay : 4.376 - -Slack : 1.534 -From Node : ula:ula_|video:video_|vram_address[10] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.552 -Data Delay : 4.377 - -Slack : 1.538 -From Node : ula:ula_|video:video_|vram_address[11] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.561 -Data Delay : 4.390 - -Slack : 1.540 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.554 -Data Delay : 4.385 - -Slack : 1.542 -From Node : ula:ula_|video:video_|vram_address[10] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.568 -Data Delay : 4.401 - -Slack : 1.543 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.549 -Data Delay : 4.383 - -Slack : 1.544 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.558 -Data Delay : 4.393 - -Slack : 1.545 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.574 -Data Delay : 4.410 - -Slack : 1.547 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.569 -Data Delay : 4.407 - -Slack : 1.547 -From Node : ula:ula_|video:video_|vram_address[11] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.550 -Data Delay : 4.388 - -Slack : 1.547 -From Node : ula:ula_|video:video_|vram_address[10] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.554 -Data Delay : 4.392 - -Slack : 1.548 -From Node : ula:ula_|video:video_|vram_address[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.558 -Data Delay : 4.397 - -Slack : 1.549 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.565 -Data Delay : 4.405 - -Slack : 1.549 -From Node : ula:ula_|video:video_|vram_address[3] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.558 -Data Delay : 4.398 - -Slack : 1.551 -From Node : ula:ula_|video:video_|vram_address[12] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.563 -Data Delay : 4.405 - -Slack : 1.553 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.574 -Data Delay : 4.418 - -Slack : 1.553 -From Node : ula:ula_|video:video_|vram_address[11] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.554 -Data Delay : 4.398 - -Slack : 1.555 -From Node : ula:ula_|video:video_|vram_address[11] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.575 -Data Delay : 4.421 - -Slack : 1.555 -From Node : ula:ula_|video:video_|vram_address[11] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.563 -Data Delay : 4.409 - -Slack : 1.557 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.549 -Data Delay : 4.397 - -Slack : 1.558 -From Node : ula:ula_|video:video_|vram_address[8] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.563 -Data Delay : 4.412 - -Slack : 1.562 -From Node : ula:ula_|video:video_|vram_address[10] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.550 -Data Delay : 4.403 - -Slack : 1.563 -From Node : ula:ula_|video:video_|vram_address[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.562 -Data Delay : 4.416 - -Slack : 1.565 -From Node : ula:ula_|video:video_|vram_address[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.557 -Data Delay : 4.413 - -Slack : 1.565 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.367 -Data Delay : 4.223 - -Slack : 1.567 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.558 -Data Delay : 4.416 - -Slack : 1.569 -From Node : ula:ula_|video:video_|vram_address[3] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.562 -Data Delay : 4.422 - -Slack : 1.572 -From Node : ula:ula_|video:video_|vram_address[10] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.566 -Data Delay : 4.429 - -Slack : 1.578 -From Node : ula:ula_|video:video_|vram_address[10] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.563 -Data Delay : 4.432 - -Slack : 1.578 -From Node : ula:ula_|video:video_|vram_address[6] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.562 -Data Delay : 4.431 - -Slack : 1.579 -From Node : ula:ula_|video:video_|vram_address[11] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.558 -Data Delay : 4.428 - -Slack : 1.580 -From Node : ula:ula_|video:video_|vram_address[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.554 -Data Delay : 4.425 -+--------------------------------------------------------------------------------+ - - - +--------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' ; +--------------------------------------------------------------------------------+ @@ -4070,23 +3164,23 @@ Relationship : 0.000 Clock Skew : 0.078 Data Delay : 0.580 -Slack : 0.576 +Slack : 0.575 From Node : ula:ula_|clocks:clocks_|counter[0] To Node : ula:ula_|clocks:clocks_|clk_cpu Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Relationship : 0.000 Clock Skew : 0.078 -Data Delay : 0.811 +Data Delay : 0.810 -Slack : 1.324 +Slack : 1.322 From Node : SW[2] To Node : ula:ula_|clocks:clocks_|clk_cpu Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Relationship : -0.017 Clock Skew : 0.636 -Data Delay : 1.190 +Data Delay : 1.188 +--------------------------------------------------------------------------------+ @@ -4094,15 +3188,51 @@ Data Delay : 1.190 +--------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ; +--------------------------------------------------------------------------------+ -Slack : 0.344 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] +Slack : 0.342 +From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 +To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.076 +Clock Skew : 0.078 Data Delay : 0.577 +Slack : 0.343 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.077 +Data Delay : 0.577 + +Slack : 0.343 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.077 +Data Delay : 0.577 + +Slack : 0.345 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.078 +Data Delay : 0.580 + +Slack : 0.345 +From Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 +To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.078 +Data Delay : 0.580 + Slack : 0.345 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] @@ -4112,58 +3242,49 @@ Relationship : 0.000 Clock Skew : 0.078 Data Delay : 0.580 -Slack : 0.346 -From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Slack : 0.358 +From Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.077 -Data Delay : 0.580 +Clock Skew : 0.062 +Data Delay : 0.577 -Slack : 0.347 -From Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 -To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 +Slack : 0.358 +From Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.076 -Data Delay : 0.580 +Clock Skew : 0.062 +Data Delay : 0.577 -Slack : 0.357 +Slack : 0.358 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.577 + +Slack : 0.358 From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.063 +Clock Skew : 0.062 Data Delay : 0.577 -Slack : 0.357 +Slack : 0.358 From Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 0.577 - -Slack : 0.357 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 0.577 - -Slack : 0.357 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.063 +Clock Skew : 0.062 Data Delay : 0.577 Slack : 0.358 @@ -4184,15 +3305,6 @@ Relationship : 0.000 Clock Skew : 0.062 Data Delay : 0.577 -Slack : 0.358 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.577 - Slack : 0.358 From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] @@ -4202,6 +3314,15 @@ Relationship : 0.000 Clock Skew : 0.062 Data Delay : 0.577 +Slack : 0.358 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.577 + Slack : 0.358 From Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] @@ -4211,33 +3332,6 @@ Relationship : 0.000 Clock Skew : 0.062 Data Delay : 0.577 -Slack : 0.358 -From Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] -To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.577 - -Slack : 0.358 -From Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] -To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.577 - -Slack : 0.358 -From Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 -To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.577 - Slack : 0.361 From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] @@ -4265,131 +3359,212 @@ Relationship : 0.000 Clock Skew : 0.062 Data Delay : 0.580 -Slack : 0.362 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +Slack : 0.372 +From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.078 -Data Delay : 0.597 +Clock Skew : 0.063 +Data Delay : 0.592 -Slack : 0.374 +Slack : 0.373 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.592 + +Slack : 0.373 From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 0.593 + +Slack : 0.374 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 Clock Skew : 0.062 Data Delay : 0.593 -Slack : 0.384 -From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 -To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] +Slack : 0.374 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.062 -Data Delay : 0.603 +Data Delay : 0.593 -Slack : 0.384 -From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 -To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] +Slack : 0.374 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.062 -Data Delay : 0.603 +Data Delay : 0.593 -Slack : 0.386 +Slack : 0.374 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.593 + +Slack : 0.375 +From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 0.595 + +Slack : 0.384 From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.062 -Data Delay : 0.605 +Data Delay : 0.603 -Slack : 0.399 +Slack : 0.413 From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle -To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.062 -Data Delay : 0.618 +Data Delay : 0.632 -Slack : 0.401 +Slack : 0.424 From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.062 -Data Delay : 0.620 +Data Delay : 0.643 -Slack : 0.463 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] +Slack : 0.424 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.078 -Data Delay : 0.698 +Clock Skew : 0.062 +Data Delay : 0.643 -Slack : 0.463 +Slack : 0.431 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.432 +Data Delay : 1.020 + +Slack : 0.476 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.435 +Data Delay : 1.068 + +Slack : 0.477 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.432 +Data Delay : 1.066 + +Slack : 0.478 From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.078 -Data Delay : 0.698 +Clock Skew : 0.062 +Data Delay : 0.697 -Slack : 0.464 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] +Slack : 0.479 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.078 +Clock Skew : 0.062 +Data Delay : 0.698 + +Slack : 0.480 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 Data Delay : 0.699 -Slack : 0.464 +Slack : 0.480 From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.078 +Clock Skew : 0.062 Data Delay : 0.699 -Slack : 0.466 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.078 -Data Delay : 0.701 - -Slack : 0.513 -From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.732 - -Slack : 0.515 +Slack : 0.514 From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.060 -Data Delay : 0.732 +Clock Skew : 0.063 +Data Delay : 0.734 + +Slack : 0.530 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.749 + +Slack : 0.533 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.752 + +Slack : 0.540 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.078 +Data Delay : 0.775 Slack : 0.542 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] @@ -4400,456 +3575,474 @@ Relationship : 0.000 Clock Skew : 0.078 Data Delay : 0.777 -Slack : 0.544 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.078 -Data Delay : 0.779 - -Slack : 0.547 +Slack : 0.545 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.078 -Data Delay : 0.782 +Data Delay : 0.780 -Slack : 0.548 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.106 -Data Delay : 0.811 - -Slack : 0.554 -From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.773 - -Slack : 0.555 -From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.774 - -Slack : 0.555 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +Slack : 0.547 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.078 -Data Delay : 0.790 +Data Delay : 0.782 -Slack : 0.557 +Slack : 0.552 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.771 + +Slack : 0.553 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.078 -Data Delay : 0.792 +Data Delay : 0.788 -Slack : 0.558 -From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.777 - -Slack : 0.559 -From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.778 - -Slack : 0.559 -From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.778 - -Slack : 0.561 -From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.780 - -Slack : 0.564 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.061 -Data Delay : 0.782 - -Slack : 0.567 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 0.787 - -Slack : 0.574 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.078 -Data Delay : 0.809 - -Slack : 0.574 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.078 -Data Delay : 0.809 - -Slack : 0.575 +Slack : 0.554 From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.078 -Data Delay : 0.810 +Clock Skew : 0.062 +Data Delay : 0.773 -Slack : 0.575 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Slack : 0.554 +From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.432 -Data Delay : 1.164 +Clock Skew : 0.063 +Data Delay : 0.774 -Slack : 0.576 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.078 -Data Delay : 0.811 - -Slack : 0.576 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.078 -Data Delay : 0.811 - -Slack : 0.576 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.078 -Data Delay : 0.811 - -Slack : 0.576 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.078 -Data Delay : 0.811 - -Slack : 0.577 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.078 -Data Delay : 0.812 - -Slack : 0.577 -From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] +Slack : 0.556 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.062 -Data Delay : 0.796 +Data Delay : 0.775 -Slack : 0.580 -From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] +Slack : 0.556 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.799 +Clock Skew : 0.063 +Data Delay : 0.776 -Slack : 0.590 -From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Slack : 0.557 +From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.809 +Clock Skew : 0.063 +Data Delay : 0.777 -Slack : 0.590 +Slack : 0.558 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 0.778 + +Slack : 0.559 From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.809 +Clock Skew : 0.432 +Data Delay : 1.148 -Slack : 0.597 -From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Slack : 0.559 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.078 +Data Delay : 0.794 + +Slack : 0.567 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.062 -Data Delay : 0.816 +Data Delay : 0.786 -Slack : 0.604 +Slack : 0.573 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.792 + +Slack : 0.574 From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.823 +Clock Skew : 0.077 +Data Delay : 0.808 -Slack : 0.612 -From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Slack : 0.576 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.831 +Clock Skew : 0.063 +Data Delay : 0.796 -Slack : 0.613 +Slack : 0.578 +From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.077 +Data Delay : 0.812 + +Slack : 0.579 From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.832 +Clock Skew : 0.077 +Data Delay : 0.813 -Slack : 0.627 -From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Slack : 0.579 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.846 +Clock Skew : 0.063 +Data Delay : 0.799 -Slack : 0.636 -From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Slack : 0.581 +From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.855 +Clock Skew : 0.077 +Data Delay : 0.815 -Slack : 0.639 +Slack : 0.588 From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.062 -Data Delay : 0.858 +Data Delay : 0.807 -Slack : 0.680 -From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.899 - -Slack : 0.686 -From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.905 - -Slack : 0.703 -From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 -To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.922 - -Slack : 0.747 -From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : -0.293 -Data Delay : 0.611 - -Slack : 0.763 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start -To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.064 -Data Delay : 0.984 - -Slack : 0.764 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.064 -Data Delay : 0.985 - -Slack : 0.771 +Slack : 0.591 From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.064 -Data Delay : 0.992 +Clock Skew : 0.062 +Data Delay : 0.810 -Slack : 0.780 -From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Slack : 0.592 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.062 -Data Delay : 0.999 +Data Delay : 0.811 -Slack : 0.785 -From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] +Slack : 0.602 +From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.004 +Clock Skew : 0.077 +Data Delay : 0.836 -Slack : 0.786 +Slack : 0.631 From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.062 -Data Delay : 1.005 +Data Delay : 0.850 -Slack : 0.788 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +Slack : 0.633 +From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.852 + +Slack : 0.653 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.432 +Data Delay : 1.242 + +Slack : 0.673 +From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.892 + +Slack : 0.720 +From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.939 + +Slack : 0.725 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.944 + +Slack : 0.729 +From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.948 + +Slack : 0.734 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.063 -Data Delay : 1.008 +Data Delay : 0.954 -Slack : 0.799 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +Slack : 0.738 +From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.957 + +Slack : 0.742 +From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.961 + +Slack : 0.749 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : -0.294 +Data Delay : 0.612 + +Slack : 0.755 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.432 +Data Delay : 1.344 + +Slack : 0.790 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.428 +Data Delay : 1.375 + +Slack : 0.790 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.428 +Data Delay : 1.375 + +Slack : 0.790 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.428 +Data Delay : 1.375 + +Slack : 0.790 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.428 +Data Delay : 1.375 + +Slack : 0.790 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.428 +Data Delay : 1.375 + +Slack : 0.800 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.062 -Data Delay : 1.018 +Data Delay : 1.019 -Slack : 0.808 +Slack : 0.813 From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.028 - -Slack : 0.814 -From Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.062 -Data Delay : 1.033 +Data Delay : 1.032 -Slack : 0.817 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.078 -Data Delay : 1.052 - -Slack : 0.818 +Slack : 0.815 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.078 -Data Delay : 1.053 +Data Delay : 1.050 -Slack : 0.831 -From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] +Slack : 0.816 +From Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 +To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 1.036 + +Slack : 0.816 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.078 +Data Delay : 1.051 + +Slack : 0.817 +From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.062 +Data Delay : 1.036 + +Slack : 0.820 +From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.039 + +Slack : 0.823 +From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.042 + +Slack : 0.827 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.046 + +Slack : 0.830 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.063 Data Delay : 1.050 +Slack : 0.831 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 1.051 + Slack : 0.831 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] @@ -4860,31 +4053,13 @@ Clock Skew : 0.078 Data Delay : 1.066 Slack : 0.832 -From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.051 - -Slack : 0.832 -From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.051 - -Slack : 0.833 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : -0.291 -Data Delay : 0.699 +Clock Skew : 0.078 +Data Delay : 1.067 Slack : 0.833 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] @@ -4905,94 +4080,13 @@ Clock Skew : 0.078 Data Delay : 1.068 Slack : 0.834 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.078 -Data Delay : 1.069 - -Slack : 0.835 -From Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.077 -Data Delay : 1.069 - -Slack : 0.835 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.078 -Data Delay : 1.070 - -Slack : 0.836 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.078 -Data Delay : 1.071 - -Slack : 0.845 -From Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 -To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.062 -Data Delay : 1.064 - -Slack : 0.848 -From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.067 - -Slack : 0.850 -From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.069 - -Slack : 0.852 -From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.071 - -Slack : 0.854 -From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.073 - -Slack : 0.854 -From Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 -To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.073 +Data Delay : 1.053 +--------------------------------------------------------------------------------+ @@ -5010,8 +4104,8 @@ Clock Skew : 0.063 Data Delay : 0.577 Slack : 0.357 -From Node : ula:ula_|video:video_|vram_address[10] -To Node : ula:ula_|video:video_|vram_address[10] +From Node : ula:ula_|video:video_|vga_vc[9] +To Node : ula:ula_|video:video_|vga_vc[9] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 @@ -5019,8 +4113,35 @@ Clock Skew : 0.063 Data Delay : 0.577 Slack : 0.357 -From Node : ula:ula_|video:video_|frame[0] -To Node : ula:ula_|video:video_|frame[0] +From Node : ula:ula_|video:video_|vga_vc[4] +To Node : ula:ula_|video:video_|vga_vc[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 0.577 + +Slack : 0.357 +From Node : ula:ula_|video:video_|vga_vc[5] +To Node : ula:ula_|video:video_|vga_vc[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 0.577 + +Slack : 0.357 +From Node : ula:ula_|video:video_|vga_vc[6] +To Node : ula:ula_|video:video_|vga_vc[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 0.577 + +Slack : 0.357 +From Node : ula:ula_|video:video_|vga_vc[7] +To Node : ula:ula_|video:video_|vga_vc[7] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 @@ -5037,8 +4158,8 @@ Clock Skew : 0.062 Data Delay : 0.577 Slack : 0.358 -From Node : ula:ula_|video:video_|vga_vc[9] -To Node : ula:ula_|video:video_|vga_vc[9] +From Node : ula:ula_|video:video_|vram_address[10] +To Node : ula:ula_|video:video_|vram_address[10] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 @@ -5046,8 +4167,8 @@ Clock Skew : 0.062 Data Delay : 0.577 Slack : 0.358 -From Node : ula:ula_|video:video_|vga_vc[0] -To Node : ula:ula_|video:video_|vga_vc[0] +From Node : ula:ula_|video:video_|frame[0] +To Node : ula:ula_|video:video_|frame[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 @@ -5063,15 +4184,6 @@ Relationship : 0.000 Clock Skew : 0.062 Data Delay : 0.577 -Slack : 0.358 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : ula:ula_|video:video_|vga_vc[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.577 - Slack : 0.358 From Node : ula:ula_|video:video_|vga_vc[8] To Node : ula:ula_|video:video_|vga_vc[8] @@ -5081,41 +4193,14 @@ Relationship : 0.000 Clock Skew : 0.062 Data Delay : 0.577 -Slack : 0.358 -From Node : ula:ula_|video:video_|vga_vc[4] -To Node : ula:ula_|video:video_|vga_vc[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.577 - -Slack : 0.358 -From Node : ula:ula_|video:video_|vga_vc[6] -To Node : ula:ula_|video:video_|vga_vc[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.577 - -Slack : 0.358 -From Node : ula:ula_|video:video_|vga_vc[7] -To Node : ula:ula_|video:video_|vga_vc[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.577 - -Slack : 0.549 +Slack : 0.551 From Node : ula:ula_|video:video_|frame[2] To Node : ula:ula_|video:video_|frame[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.768 +Clock Skew : 0.063 +Data Delay : 0.771 Slack : 0.553 From Node : ula:ula_|video:video_|frame[3] @@ -5123,782 +4208,1697 @@ To Node : ula:ula_|video:video_|frame[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.772 +Clock Skew : 0.063 +Data Delay : 0.773 -Slack : 0.563 +Slack : 0.562 From Node : ula:ula_|video:video_|frame[1] To Node : ula:ula_|video:video_|frame[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.062 +Clock Skew : 0.063 Data Delay : 0.782 -Slack : 0.570 -From Node : ula:ula_|video:video_|frame[4] -To Node : ula:ula_|video:video_|frame[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.789 - -Slack : 0.657 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[1] -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.876 - -Slack : 0.728 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|vram_address[10] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 0.948 - -Slack : 0.821 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 1.047 - -Slack : 0.824 +Slack : 0.825 From Node : ula:ula_|video:video_|frame[2] To Node : ula:ula_|video:video_|frame[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.043 +Clock Skew : 0.063 +Data Delay : 1.045 Slack : 0.840 -From Node : ula:ula_|video:video_|frame[3] -To Node : ula:ula_|video:video_|frame[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.059 - -Slack : 0.841 From Node : ula:ula_|video:video_|frame[1] To Node : ula:ula_|video:video_|frame[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.062 +Clock Skew : 0.063 Data Delay : 1.060 -Slack : 0.843 +Slack : 0.842 From Node : ula:ula_|video:video_|frame[1] To Node : ula:ula_|video:video_|frame[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.062 +Clock Skew : 0.063 Data Delay : 1.062 -Slack : 0.860 -From Node : ula:ula_|video:video_|vga_hc[8] -To Node : ula:ula_|video:video_|vga_hc[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.080 - -Slack : 0.919 -From Node : ula:ula_|video:video_|frame[0] -To Node : ula:ula_|video:video_|frame[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.138 - -Slack : 0.934 -From Node : ula:ula_|video:video_|frame[2] -To Node : ula:ula_|video:video_|frame[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.153 - -Slack : 0.953 -From Node : ula:ula_|video:video_|frame[1] -To Node : ula:ula_|video:video_|frame[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.172 - -Slack : 0.967 -From Node : ula:ula_|video:video_|vga_vc[4] -To Node : ula:ula_|video:video_|vram_address[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 1.193 - -Slack : 0.980 -From Node : ula:ula_|video:video_|vga_vc[5] -To Node : ula:ula_|video:video_|vram_address[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 1.206 - -Slack : 1.030 -From Node : ula:ula_|video:video_|vga_hc[4] -To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.066 -Data Delay : 1.253 - -Slack : 1.074 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|vram_address[9] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.068 -Data Delay : 1.299 - -Slack : 1.074 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|vram_address[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.068 -Data Delay : 1.299 - -Slack : 1.077 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|vram_address[12] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.068 -Data Delay : 1.302 - -Slack : 1.078 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|vram_address[11] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.068 -Data Delay : 1.303 - -Slack : 1.111 -From Node : ula:ula_|video:video_|bits_prefetch[6] -To Node : ula:ula_|video:video_|bits[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.300 -Data Delay : 0.968 - -Slack : 1.117 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : ula:ula_|video:video_|vram_address[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 1.343 - -Slack : 1.118 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : ula:ula_|video:video_|vram_address[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 1.344 - -Slack : 1.129 -From Node : ula:ula_|video:video_|vga_hc[5] -To Node : ula:ula_|video:video_|vram_address[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 1.355 - -Slack : 1.140 -From Node : ula:ula_|video:video_|bits_prefetch[2] -To Node : ula:ula_|video:video_|bits[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.300 -Data Delay : 0.997 - -Slack : 1.143 +Slack : 0.903 From Node : ula:ula_|video:video_|bits_prefetch[1] To Node : ula:ula_|video:video_|bits[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : -0.300 -Data Delay : 1.000 +Clock Skew : -0.291 +Data Delay : 0.769 -Slack : 1.151 +Slack : 0.920 From Node : ula:ula_|video:video_|bits_prefetch[5] To Node : ula:ula_|video:video_|bits[5] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : -0.300 -Data Delay : 1.008 +Clock Skew : -0.291 +Data Delay : 0.786 -Slack : 1.159 -From Node : ula:ula_|video:video_|vga_hc[4] -To Node : ula:ula_|video:video_|vram_address[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 1.385 - -Slack : 1.193 -From Node : ula:ula_|video:video_|frame[0] -To Node : ula:ula_|video:video_|frame[2] +Slack : 0.978 +From Node : ula:ula_|video:video_|vga_hc[6] +To Node : ula:ula_|video:video_|vram_address[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.062 -Data Delay : 1.412 +Data Delay : 1.197 -Slack : 1.195 -From Node : ula:ula_|video:video_|frame[0] -To Node : ula:ula_|video:video_|frame[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.414 - -Slack : 1.201 +Slack : 0.980 From Node : ula:ula_|video:video_|vga_hc[6] To Node : ula:ula_|video:video_|vram_address[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 1.427 +Clock Skew : 0.062 +Data Delay : 1.199 -Slack : 1.241 -From Node : ula:ula_|video:video_|vga_vc[4] -To Node : ula:ula_|video:video_|vram_address[6] +Slack : 0.981 +From Node : ula:ula_|video:video_|vga_hc[6] +To Node : ula:ula_|video:video_|vram_address[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 1.467 +Clock Skew : 0.062 +Data Delay : 1.200 -Slack : 1.248 -From Node : ula:ula_|video:video_|vga_vc[6] -To Node : ula:ula_|video:video_|vram_address[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 1.474 - -Slack : 1.262 +Slack : 1.036 From Node : ula:ula_|video:video_|vga_hc[5] -To Node : ula:ula_|video:video_|vga_hc[5] +To Node : ula:ula_|video:video_|vram_address[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.482 +Clock Skew : 0.062 +Data Delay : 1.255 -Slack : 1.265 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|vram_address[12] +Slack : 1.041 +From Node : ula:ula_|video:video_|bits_prefetch[3] +To Node : ula:ula_|video:video_|bits[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.485 +Clock Skew : -0.291 +Data Delay : 0.907 -Slack : 1.265 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|vram_address[9] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.485 - -Slack : 1.265 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|vram_address[11] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.485 - -Slack : 1.265 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|vram_address[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.485 - -Slack : 1.269 -From Node : ula:ula_|video:video_|vga_vc[5] -To Node : ula:ula_|video:video_|vram_address[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 1.495 - -Slack : 1.279 -From Node : ula:ula_|video:video_|vga_vc[3] -To Node : ula:ula_|video:video_|vram_address[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 1.505 - -Slack : 1.281 -From Node : ula:ula_|video:video_|bits_prefetch[0] -To Node : ula:ula_|video:video_|bits[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.300 -Data Delay : 1.138 - -Slack : 1.281 -From Node : ula:ula_|video:video_|vga_vc[3] -To Node : ula:ula_|video:video_|vram_address[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 1.507 - -Slack : 1.291 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|vga_hc[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.511 - -Slack : 1.291 -From Node : ula:ula_|video:video_|vga_hc[1] -To Node : ula:ula_|video:video_|vram_address[10] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.064 -Data Delay : 1.512 - -Slack : 1.296 -From Node : ula:ula_|video:video_|attr_prefetch[3] -To Node : ula:ula_|video:video_|attr[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.328 -Data Delay : 1.125 - -Slack : 1.299 +Slack : 1.041 From Node : ula:ula_|video:video_|bits_prefetch[4] To Node : ula:ula_|video:video_|bits[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : -0.300 -Data Delay : 1.156 +Clock Skew : -0.291 +Data Delay : 0.907 -Slack : 1.305 -From Node : ula:ula_|video:video_|frame[0] -To Node : ula:ula_|video:video_|frame[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.524 - -Slack : 1.310 -From Node : ula:ula_|video:video_|vga_hc[9] -To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.529 - -Slack : 1.312 -From Node : ula:ula_|video:video_|vga_hc[9] -To Node : ula:ula_|video:video_|vga_hc[9] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.531 - -Slack : 1.314 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : ula:ula_|video:video_|vram_address[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 1.540 - -Slack : 1.316 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : ula:ula_|video:video_|vram_address[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 1.542 - -Slack : 1.323 -From Node : ula:ula_|video:video_|attr_prefetch[5] -To Node : ula:ula_|video:video_|attr[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.328 -Data Delay : 1.152 - -Slack : 1.339 -From Node : ula:ula_|video:video_|attr_prefetch[7] -To Node : ula:ula_|video:video_|attr[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.328 -Data Delay : 1.168 - -Slack : 1.342 -From Node : ula:ula_|video:video_|attr_prefetch[4] -To Node : ula:ula_|video:video_|attr[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.329 -Data Delay : 1.170 - -Slack : 1.351 +Slack : 1.051 From Node : ula:ula_|video:video_|vga_vc[4] -To Node : ula:ula_|video:video_|vram_address[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 1.577 - -Slack : 1.355 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : ula:ula_|video:video_|vga_hc[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.575 - -Slack : 1.360 -From Node : ula:ula_|video:video_|attr_prefetch[0] -To Node : ula:ula_|video:video_|attr[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.329 -Data Delay : 1.188 - -Slack : 1.378 -From Node : ula:ula_|video:video_|vga_vc[0] To Node : ula:ula_|video:video_|vram_address[5] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 1.604 +Clock Skew : 0.062 +Data Delay : 1.270 -Slack : 1.380 -From Node : ula:ula_|video:video_|vga_vc[0] -To Node : ula:ula_|video:video_|vram_address[6] +Slack : 1.054 +From Node : ula:ula_|video:video_|vga_hc[4] +To Node : ula:ula_|video:video_|vram_address[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 1.606 +Clock Skew : 0.062 +Data Delay : 1.273 -Slack : 1.387 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : ula:ula_|video:video_|vga_hc[9] +Slack : 1.060 +From Node : ula:ula_|video:video_|vga_hc[1] +To Node : ula:ula_|video:video_|vram_address[10] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.066 -Data Delay : 1.610 +Clock Skew : 0.062 +Data Delay : 1.279 -Slack : 1.391 -From Node : ula:ula_|video:video_|vga_vc[3] -To Node : ula:ula_|video:video_|vram_address[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 1.617 - -Slack : 1.398 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.066 -Data Delay : 1.621 - -Slack : 1.405 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|vram_address[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 1.631 - -Slack : 1.406 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|vga_hc[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.626 - -Slack : 1.407 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|vram_address[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 1.633 - -Slack : 1.426 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : ula:ula_|video:video_|vram_address[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 1.652 - -Slack : 1.450 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|attr_prefetch[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.469 -Data Delay : 2.076 - -Slack : 1.450 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|attr_prefetch[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.469 -Data Delay : 2.076 - -Slack : 1.450 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|attr_prefetch[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.469 -Data Delay : 2.076 - -Slack : 1.450 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|attr_prefetch[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.469 -Data Delay : 2.076 - -Slack : 1.450 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|attr_prefetch[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.469 -Data Delay : 2.076 - -Slack : 1.450 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|attr_prefetch[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.469 -Data Delay : 2.076 - -Slack : 1.450 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|attr_prefetch[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.469 -Data Delay : 2.076 - -Slack : 1.450 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|attr_prefetch[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.469 -Data Delay : 2.076 - -Slack : 1.479 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|bits_prefetch[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.440 -Data Delay : 2.076 - -Slack : 1.479 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|bits_prefetch[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.440 -Data Delay : 2.076 - -Slack : 1.479 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|bits_prefetch[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.440 -Data Delay : 2.076 - -Slack : 1.479 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|bits_prefetch[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.440 -Data Delay : 2.076 - -Slack : 1.479 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|bits_prefetch[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.440 -Data Delay : 2.076 - -Slack : 1.479 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|bits_prefetch[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.440 -Data Delay : 2.076 - -Slack : 1.479 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|bits_prefetch[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.440 -Data Delay : 2.076 - -Slack : 1.479 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|bits_prefetch[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.440 -Data Delay : 2.076 - -Slack : 1.490 -From Node : ula:ula_|video:video_|vga_vc[0] -To Node : ula:ula_|video:video_|vram_address[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 1.716 - -Slack : 1.500 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : ula:ula_|video:video_|vga_hc[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.720 - -Slack : 1.509 +Slack : 1.070 From Node : ula:ula_|video:video_|bits_prefetch[7] To Node : ula:ula_|video:video_|bits[7] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : -0.300 -Data Delay : 1.366 +Clock Skew : -0.291 +Data Delay : 0.936 -Slack : 1.517 -From Node : ula:ula_|video:video_|vga_hc[8] -To Node : ula:ula_|video:video_|vga_hc[9] +Slack : 1.075 +From Node : ula:ula_|video:video_|bits_prefetch[2] +To Node : ula:ula_|video:video_|bits[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.066 -Data Delay : 1.740 +Clock Skew : -0.291 +Data Delay : 0.941 + +Slack : 1.099 +From Node : ula:ula_|video:video_|attr_prefetch[7] +To Node : ula:ula_|video:video_|attr[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.319 +Data Delay : 0.937 + +Slack : 1.102 +From Node : ula:ula_|video:video_|attr_prefetch[3] +To Node : ula:ula_|video:video_|attr[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.319 +Data Delay : 0.940 + +Slack : 1.136 +From Node : ula:ula_|video:video_|frame[0] +To Node : ula:ula_|video:video_|frame[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 1.356 + +Slack : 1.144 +From Node : ula:ula_|video:video_|attr_prefetch[0] +To Node : ula:ula_|video:video_|attr[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.319 +Data Delay : 0.982 + +Slack : 1.146 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|vram_address[12] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 1.366 + +Slack : 1.146 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|vram_address[11] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 1.366 + +Slack : 1.224 +From Node : ula:ula_|video:video_|bits_prefetch[6] +To Node : ula:ula_|video:video_|bits[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.291 +Data Delay : 1.090 + +Slack : 1.224 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|vram_address[9] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 1.444 + +Slack : 1.227 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|vram_address[8] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 1.447 + +Slack : 1.230 +From Node : ula:ula_|video:video_|vga_vc[5] +To Node : ula:ula_|video:video_|vram_address[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.449 + +Slack : 1.235 +From Node : ula:ula_|video:video_|vga_hc[8] +To Node : ula:ula_|video:video_|vram_address[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 1.455 + +Slack : 1.237 +From Node : ula:ula_|video:video_|vga_vc[6] +To Node : ula:ula_|video:video_|vram_address[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.456 + +Slack : 1.238 +From Node : ula:ula_|video:video_|vga_hc[7] +To Node : ula:ula_|video:video_|vram_address[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.457 + +Slack : 1.239 +From Node : ula:ula_|video:video_|vga_hc[7] +To Node : ula:ula_|video:video_|vram_address[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.458 + +Slack : 1.280 +From Node : ula:ula_|video:video_|vga_vc[9] +To Node : ula:ula_|video:video_|frame[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.499 + +Slack : 1.285 +From Node : ula:ula_|video:video_|vga_hc[6] +To Node : ula:ula_|video:video_|vga_hc[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.504 + +Slack : 1.286 +From Node : ula:ula_|video:video_|vga_hc[7] +To Node : ula:ula_|video:video_|vga_hc[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.505 + +Slack : 1.289 +From Node : ula:ula_|video:video_|attr_prefetch[6] +To Node : ula:ula_|video:video_|attr[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.319 +Data Delay : 1.127 + +Slack : 1.301 +From Node : ula:ula_|video:video_|attr_prefetch[4] +To Node : ula:ula_|video:video_|attr[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.319 +Data Delay : 1.139 + +Slack : 1.325 +From Node : ula:ula_|video:video_|vga_vc[4] +To Node : ula:ula_|video:video_|vram_address[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.544 + +Slack : 1.329 +From Node : ula:ula_|video:video_|vga_hc[8] +To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.548 + +Slack : 1.347 +From Node : ula:ula_|video:video_|attr_prefetch[5] +To Node : ula:ula_|video:video_|attr[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.319 +Data Delay : 1.185 + +Slack : 1.379 +From Node : ula:ula_|video:video_|vga_hc[3] +To Node : ula:ula_|video:video_|vram_address[10] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.597 + +Slack : 1.389 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.608 + +Slack : 1.410 +From Node : ula:ula_|video:video_|frame[0] +To Node : ula:ula_|video:video_|frame[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 1.630 + +Slack : 1.412 +From Node : ula:ula_|video:video_|frame[0] +To Node : ula:ula_|video:video_|frame[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 1.632 + +Slack : 1.435 +From Node : ula:ula_|video:video_|vga_vc[4] +To Node : ula:ula_|video:video_|vram_address[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.654 + +Slack : 1.438 +From Node : ula:ula_|video:video_|vga_hc[6] +To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.656 + +Slack : 1.449 +From Node : ula:ula_|video:video_|frame[4] +To Node : ula:ula_|video:video_|frame[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 1.669 + +Slack : 1.470 +From Node : ula:ula_|video:video_|frame[3] +To Node : ula:ula_|video:video_|frame[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.688 + +Slack : 1.472 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|vram_address[10] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.290 +Data Delay : 1.339 + +Slack : 1.484 +From Node : ula:ula_|video:video_|vga_vc[8] +To Node : ula:ula_|video:video_|vram_address[12] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.064 +Data Delay : 1.705 + +Slack : 1.485 +From Node : ula:ula_|video:video_|vga_vc[8] +To Node : ula:ula_|video:video_|vram_address[9] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.064 +Data Delay : 1.706 + +Slack : 1.519 +From Node : ula:ula_|video:video_|vga_vc[5] +To Node : ula:ula_|video:video_|vram_address[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.738 + +Slack : 1.565 +From Node : ula:ula_|video:video_|frame[2] +To Node : ula:ula_|video:video_|frame[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.783 + +Slack : 1.576 +From Node : ula:ula_|video:video_|vga_hc[6] +To Node : ula:ula_|video:video_|vga_hc[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.795 + +Slack : 1.582 +From Node : ula:ula_|video:video_|frame[1] +To Node : ula:ula_|video:video_|frame[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.800 + +Slack : 1.610 +From Node : ula:ula_|video:video_|vga_vc[0] +To Node : ula:ula_|video:video_|vram_address[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 1.830 + +Slack : 1.612 +From Node : ula:ula_|video:video_|vga_vc[0] +To Node : ula:ula_|video:video_|vram_address[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 1.832 + +Slack : 1.623 +From Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1 +To Node : ula:ula_|video:video_|VGA_VS +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.038 +Data Delay : 1.758 + +Slack : 1.633 +From Node : ula:ula_|video:video_|vga_hc[9] +To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.851 + +Slack : 1.645 +From Node : ula:ula_|video:video_|vga_vc[2] +To Node : ula:ula_|video:video_|vram_address[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 1.865 + +Slack : 1.647 +From Node : ula:ula_|video:video_|vga_vc[2] +To Node : ula:ula_|video:video_|vram_address[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 1.867 + +Slack : 1.653 +From Node : ula:ula_|video:video_|vga_hc[3] +To Node : ula:ula_|video:video_|vga_hc[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.872 + +Slack : 1.673 +From Node : ula:ula_|video:video_|vga_vc[7] +To Node : ula:ula_|video:video_|frame[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.892 + +Slack : 1.679 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|vram_address[10] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.898 + +Slack : 1.697 +From Node : ula:ula_|video:video_|attr_prefetch[2] +To Node : ula:ula_|video:video_|attr[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.319 +Data Delay : 1.535 + +Slack : 1.712 +From Node : ula:ula_|video:video_|vga_vc[1] +To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.064 +Data Delay : 1.933 + +Slack : 1.721 +From Node : ula:ula_|video:video_|vga_hc[3] +To Node : ula:ula_|video:video_|vga_hc[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.940 + +Slack : 1.722 +From Node : ula:ula_|video:video_|vga_vc[0] +To Node : ula:ula_|video:video_|vram_address[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 1.942 + +Slack : 1.729 +From Node : ula:ula_|video:video_|bits_prefetch[0] +To Node : ula:ula_|video:video_|bits[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.291 +Data Delay : 1.595 + +Slack : 1.733 +From Node : ula:ula_|video:video_|vga_vc[3] +To Node : ula:ula_|video:video_|vram_address[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 1.953 + +Slack : 1.735 +From Node : ula:ula_|video:video_|vga_vc[3] +To Node : ula:ula_|video:video_|vram_address[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 1.955 + +Slack : 1.755 +From Node : ula:ula_|video:video_|vga_vc[9] +To Node : ula:ula_|video:video_|frame[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 1.973 + +Slack : 1.757 +From Node : ula:ula_|video:video_|vga_vc[2] +To Node : ula:ula_|video:video_|vram_address[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 1.977 + +Slack : 1.759 +From Node : ula:ula_|video:video_|vga_vc[0] +To Node : ula:ula_|video:video_|vram_address[8] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.064 +Data Delay : 1.980 + +Slack : 1.779 +From Node : ula:ula_|video:video_|vga_vc[9] +To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 1.999 + +Slack : 1.796 +From Node : ula:ula_|video:video_|vga_vc[4] +To Node : ula:ula_|video:video_|frame[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 2.015 + +Slack : 1.800 +From Node : ula:ula_|video:video_|vga_hc[8] +To Node : ula:ula_|video:video_|vga_vc[8] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 2.018 + +Slack : 1.801 +From Node : ula:ula_|video:video_|vga_hc[8] +To Node : ula:ula_|video:video_|vga_vc[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 2.019 + +Slack : 1.811 +From Node : ula:ula_|video:video_|vga_hc[8] +To Node : ula:ula_|video:video_|vga_vc[9] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 2.031 + +Slack : 1.818 +From Node : ula:ula_|video:video_|vga_vc[8] +To Node : ula:ula_|video:video_|frame[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 2.038 + +Slack : 1.824 +From Node : ula:ula_|video:video_|vga_vc[2] +To Node : ula:ula_|video:video_|vram_address[9] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.064 +Data Delay : 2.045 + +Slack : 1.829 +From Node : ula:ula_|video:video_|attr_prefetch[1] +To Node : ula:ula_|video:video_|attr[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.319 +Data Delay : 1.667 + +Slack : 1.829 +From Node : ula:ula_|video:video_|vga_hc[5] +To Node : ula:ula_|video:video_|vga_hc[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 2.048 + +Slack : 1.845 +From Node : ula:ula_|video:video_|vga_vc[3] +To Node : ula:ula_|video:video_|vram_address[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 2.065 + +Slack : 1.860 +From Node : ula:ula_|video:video_|vga_hc[5] +To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.061 +Data Delay : 2.078 + +Slack : 1.862 +From Node : ula:ula_|video:video_|vga_vc[7] +To Node : ula:ula_|video:video_|vram_address[8] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 2.082 + +Slack : 1.866 +From Node : ula:ula_|video:video_|vga_vc[7] +To Node : ula:ula_|video:video_|vram_address[11] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 2.086 + +Slack : 1.869 +From Node : ula:ula_|video:video_|vga_hc[8] +To Node : ula:ula_|video:video_|vga_vc[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 2.089 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Hold: 'CLOCK_50' ; ++--------------------------------------------------------------------------------+ +Slack : 0.517 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|address_reg_a[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.736 + +Slack : 0.518 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.651 +Data Delay : 3.460 + +Slack : 0.525 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.637 +Data Delay : 3.453 + +Slack : 1.193 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.366 +Data Delay : 3.850 + +Slack : 1.200 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.559 +Data Delay : 4.050 + +Slack : 1.200 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.352 +Data Delay : 3.843 + +Slack : 1.205 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.563 +Data Delay : 4.059 + +Slack : 1.206 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.577 +Data Delay : 4.074 + +Slack : 1.214 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.566 +Data Delay : 4.071 + +Slack : 1.220 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.562 +Data Delay : 4.073 + +Slack : 1.220 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.656 +Data Delay : 4.167 + +Slack : 1.221 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.564 +Data Delay : 4.076 + +Slack : 1.221 +From Node : ula:ula_|video:video_|vram_address[10] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.572 +Data Delay : 4.084 + +Slack : 1.224 +From Node : ula:ula_|video:video_|vram_address[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.576 +Data Delay : 4.091 + +Slack : 1.227 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.642 +Data Delay : 4.160 + +Slack : 1.228 +From Node : ula:ula_|video:video_|vram_address[9] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.558 +Data Delay : 4.077 + +Slack : 1.233 +From Node : ula:ula_|video:video_|vram_address[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.572 +Data Delay : 4.096 + +Slack : 1.241 +From Node : ula:ula_|video:video_|vram_address[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.576 +Data Delay : 4.108 + +Slack : 1.243 +From Node : ula:ula_|video:video_|vram_address[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.570 +Data Delay : 4.104 + +Slack : 1.244 +From Node : ula:ula_|video:video_|vram_address[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.570 +Data Delay : 4.105 + +Slack : 1.246 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.571 +Data Delay : 4.108 + +Slack : 1.256 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.569 +Data Delay : 4.116 + +Slack : 1.259 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.556 +Data Delay : 4.106 + +Slack : 1.265 +From Node : ula:ula_|video:video_|vram_address[10] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.576 +Data Delay : 4.132 + +Slack : 1.266 +From Node : ula:ula_|video:video_|vram_address[9] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.561 +Data Delay : 4.118 + +Slack : 1.267 +From Node : ula:ula_|video:video_|vram_address[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.566 +Data Delay : 4.124 + +Slack : 1.269 +From Node : ula:ula_|video:video_|vram_address[9] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.568 +Data Delay : 4.128 + +Slack : 1.271 +From Node : ula:ula_|video:video_|vram_address[6] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.562 +Data Delay : 4.124 + +Slack : 1.271 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.555 +Data Delay : 4.117 + +Slack : 1.272 +From Node : ula:ula_|video:video_|vram_address[9] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.563 +Data Delay : 4.126 + +Slack : 1.272 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.551 +Data Delay : 4.114 + +Slack : 1.272 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.553 +Data Delay : 4.116 + +Slack : 1.273 +From Node : ula:ula_|video:video_|vram_address[10] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.570 +Data Delay : 4.134 + +Slack : 1.275 +From Node : ula:ula_|video:video_|vram_address[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.566 +Data Delay : 4.132 + +Slack : 1.275 +From Node : ula:ula_|video:video_|vram_address[6] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.555 +Data Delay : 4.121 + +Slack : 1.276 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.570 +Data Delay : 4.137 + +Slack : 1.277 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.562 +Data Delay : 4.130 + +Slack : 1.277 +From Node : ula:ula_|video:video_|vram_address[6] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.559 +Data Delay : 4.127 + +Slack : 1.280 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.556 +Data Delay : 4.127 + +Slack : 1.281 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.363 +Data Delay : 3.935 + +Slack : 1.282 +From Node : ula:ula_|video:video_|vram_address[4] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.559 +Data Delay : 4.132 + +Slack : 1.283 +From Node : ula:ula_|video:video_|vram_address[3] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.576 +Data Delay : 4.150 + +Slack : 1.286 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.658 +Data Delay : 4.235 + +Slack : 1.286 +From Node : ula:ula_|video:video_|vram_address[10] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.566 +Data Delay : 4.143 + +Slack : 1.288 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.638 +Data Delay : 4.217 + +Slack : 1.288 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.559 +Data Delay : 4.138 + +Slack : 1.289 +From Node : ula:ula_|video:video_|vram_address[2] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.550 +Data Delay : 4.130 + +Slack : 1.290 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.643 +Data Delay : 4.224 + +Slack : 1.291 +From Node : ula:ula_|video:video_|vram_address[2] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.566 +Data Delay : 4.148 + +Slack : 1.291 +From Node : ula:ula_|video:video_|vram_address[4] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.552 +Data Delay : 4.134 + +Slack : 1.293 +From Node : ula:ula_|video:video_|vram_address[9] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.550 +Data Delay : 4.134 + +Slack : 1.293 +From Node : ula:ula_|video:video_|vram_address[9] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.552 +Data Delay : 4.136 + +Slack : 1.294 +From Node : ula:ula_|video:video_|vram_address[4] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.561 +Data Delay : 4.146 + +Slack : 1.294 +From Node : ula:ula_|video:video_|vram_address[4] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.554 +Data Delay : 4.139 + +Slack : 1.296 +From Node : ula:ula_|video:video_|vram_address[6] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.564 +Data Delay : 4.151 + +Slack : 1.296 +From Node : ula:ula_|video:video_|vram_address[6] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.556 +Data Delay : 4.143 + +Slack : 1.296 +From Node : ula:ula_|video:video_|vram_address[2] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.570 +Data Delay : 4.157 + +Slack : 1.297 +From Node : ula:ula_|video:video_|vram_address[2] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.555 +Data Delay : 4.143 + +Slack : 1.300 +From Node : ula:ula_|video:video_|vram_address[4] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.550 +Data Delay : 4.141 + +Slack : 1.300 +From Node : ula:ula_|video:video_|vram_address[2] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.563 +Data Delay : 4.154 + +Slack : 1.301 +From Node : ula:ula_|video:video_|vram_address[4] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.563 +Data Delay : 4.155 + +Slack : 1.301 +From Node : ula:ula_|video:video_|vram_address[2] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.576 +Data Delay : 4.168 + +Slack : 1.303 +From Node : ula:ula_|video:video_|vram_address[4] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.558 +Data Delay : 4.152 + +Slack : 1.304 +From Node : ula:ula_|video:video_|vram_address[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.559 +Data Delay : 4.154 + +Slack : 1.305 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.564 +Data Delay : 4.160 + +Slack : 1.306 +From Node : ula:ula_|video:video_|vram_address[9] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.555 +Data Delay : 4.152 + +Slack : 1.310 +From Node : ula:ula_|video:video_|vram_address[2] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.554 +Data Delay : 4.155 + +Slack : 1.315 +From Node : ula:ula_|video:video_|vram_address[3] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.566 +Data Delay : 4.172 + +Slack : 1.315 +From Node : ula:ula_|video:video_|vram_address[2] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.552 +Data Delay : 4.158 + +Slack : 1.318 +From Node : ula:ula_|video:video_|vram_address[9] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.554 +Data Delay : 4.163 + +Slack : 1.318 +From Node : ula:ula_|video:video_|vram_address[4] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.568 +Data Delay : 4.177 + +Slack : 1.319 +From Node : ula:ula_|video:video_|vram_address[4] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.555 +Data Delay : 4.165 + +Slack : 1.319 +From Node : ula:ula_|video:video_|vram_address[6] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.553 +Data Delay : 4.163 + +Slack : 1.320 +From Node : ula:ula_|video:video_|vram_address[6] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.551 +Data Delay : 4.162 + +Slack : 1.321 +From Node : ula:ula_|video:video_|vram_address[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.563 +Data Delay : 4.175 + +Slack : 1.328 +From Node : ula:ula_|video:video_|vram_address[4] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.561 +Data Delay : 4.180 + +Slack : 1.328 +From Node : ula:ula_|video:video_|vram_address[3] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.568 +Data Delay : 4.187 + +Slack : 1.330 +From Node : ula:ula_|video:video_|vram_address[4] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.563 +Data Delay : 4.184 + +Slack : 1.331 +From Node : ula:ula_|video:video_|vram_address[2] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.563 +Data Delay : 4.185 + +Slack : 1.333 +From Node : ula:ula_|video:video_|vram_address[9] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.555 +Data Delay : 4.179 + +Slack : 1.334 +From Node : ula:ula_|video:video_|vram_address[6] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.556 +Data Delay : 4.181 + +Slack : 1.335 +From Node : ula:ula_|video:video_|vram_address[6] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.573 +Data Delay : 4.199 + +Slack : 1.337 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.339 +Data Delay : 3.967 + +Slack : 1.338 +From Node : ula:ula_|video:video_|vram_address[2] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.555 +Data Delay : 4.184 + +Slack : 1.339 +From Node : ula:ula_|video:video_|vram_address[3] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.559 +Data Delay : 4.189 + +Slack : 1.339 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.560 +Data Delay : 4.190 + +Slack : 1.340 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.563 +Data Delay : 4.194 + +Slack : 1.341 +From Node : ula:ula_|video:video_|vram_address[3] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.570 +Data Delay : 4.202 + +Slack : 1.344 +From Node : ula:ula_|video:video_|vram_address[2] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.561 +Data Delay : 4.196 + +Slack : 1.344 +From Node : ula:ula_|video:video_|vram_address[3] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.561 +Data Delay : 4.196 + +Slack : 1.344 +From Node : ula:ula_|video:video_|vram_address[6] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.569 +Data Delay : 4.204 + +Slack : 1.346 +From Node : ula:ula_|video:video_|vram_address[2] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.558 +Data Delay : 4.195 + +Slack : 1.348 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.555 +Data Delay : 4.194 + +Slack : 1.348 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.552 +Data Delay : 4.191 + +Slack : 1.348 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.358 +Data Delay : 3.997 + +Slack : 1.350 +From Node : ula:ula_|video:video_|vram_address[2] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.572 +Data Delay : 4.213 + +Slack : 1.354 +From Node : ula:ula_|video:video_|vram_address[2] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.561 +Data Delay : 4.206 + +Slack : 1.355 +From Node : ula:ula_|video:video_|vram_address[4] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.566 +Data Delay : 4.212 + +Slack : 1.355 +From Node : ula:ula_|video:video_|vram_address[8] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.570 +Data Delay : 4.216 + +Slack : 1.356 +From Node : ula:ula_|video:video_|vram_address[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.561 +Data Delay : 4.208 +--------------------------------------------------------------------------------+ @@ -5906,743 +5906,743 @@ Data Delay : 1.740 +--------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Recovery: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ; +--------------------------------------------------------------------------------+ -Slack : -6.223 +Slack : -6.263 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[17] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.161 -Data Delay : 4.344 +Data Delay : 4.384 -Slack : -6.223 +Slack : -6.263 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.163 -Data Delay : 4.342 +Data Delay : 4.382 -Slack : -6.223 +Slack : -6.263 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_1 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.164 -Data Delay : 4.341 +Data Delay : 4.381 -Slack : -6.223 +Slack : -6.263 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.165 -Data Delay : 4.340 +Data Delay : 4.380 -Slack : -6.222 +Slack : -6.262 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.164 -Data Delay : 4.340 +Data Delay : 4.380 -Slack : -5.985 +Slack : -6.025 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.193 -Data Delay : 4.076 +Data Delay : 4.116 -Slack : -5.971 +Slack : -6.011 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.195 -Data Delay : 4.060 +Data Delay : 4.100 -Slack : -5.707 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.163 -Data Delay : 3.923 - -Slack : -5.707 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.163 -Data Delay : 3.923 - -Slack : -5.707 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.163 -Data Delay : 3.923 - -Slack : -5.707 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.163 -Data Delay : 3.923 - -Slack : -5.706 +Slack : -5.747 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.166 -Data Delay : 3.919 +Clock Skew : -0.161 +Data Delay : 3.965 -Slack : -5.706 +Slack : -5.747 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.166 -Data Delay : 3.919 +Clock Skew : -0.161 +Data Delay : 3.965 -Slack : -5.706 +Slack : -5.747 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.166 -Data Delay : 3.919 +Clock Skew : -0.161 +Data Delay : 3.965 -Slack : -5.706 +Slack : -5.747 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.166 -Data Delay : 3.919 +Clock Skew : -0.161 +Data Delay : 3.965 -Slack : -5.706 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.166 -Data Delay : 3.919 - -Slack : -5.706 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.166 -Data Delay : 3.919 - -Slack : -5.706 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.166 -Data Delay : 3.919 - -Slack : -5.706 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.166 -Data Delay : 3.919 - -Slack : -5.706 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.166 -Data Delay : 3.919 - -Slack : -5.706 +Slack : -5.747 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.166 -Data Delay : 3.919 +Clock Skew : -0.161 +Data Delay : 3.965 -Slack : -5.706 +Slack : -5.747 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.166 -Data Delay : 3.919 +Clock Skew : -0.161 +Data Delay : 3.965 -Slack : -5.706 +Slack : -5.747 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.162 +Data Delay : 3.964 + +Slack : -5.747 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.162 +Data Delay : 3.964 + +Slack : -5.747 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.162 +Data Delay : 3.964 + +Slack : -5.747 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.162 +Data Delay : 3.964 + +Slack : -5.747 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.162 +Data Delay : 3.964 + +Slack : -5.747 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.162 +Data Delay : 3.964 + +Slack : -5.747 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.162 +Data Delay : 3.964 + +Slack : -5.746 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.161 +Data Delay : 3.964 + +Slack : -5.746 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.161 +Data Delay : 3.964 + +Slack : -5.746 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.161 +Data Delay : 3.964 + +Slack : -5.746 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.161 +Data Delay : 3.964 + +Slack : -5.746 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.161 +Data Delay : 3.964 + +Slack : -5.746 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.161 +Data Delay : 3.964 + +Slack : -5.746 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.161 -Data Delay : 3.924 +Data Delay : 3.964 -Slack : -5.706 +Slack : -5.746 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.161 -Data Delay : 3.924 +Data Delay : 3.964 -Slack : -5.706 +Slack : -5.746 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.161 -Data Delay : 3.924 +Data Delay : 3.964 -Slack : -5.706 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.163 -Data Delay : 3.922 - -Slack : -5.706 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.163 -Data Delay : 3.922 - -Slack : -5.706 +Slack : -5.746 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.161 -Data Delay : 3.924 +Data Delay : 3.964 -Slack : -5.706 +Slack : -5.746 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.163 +Data Delay : 3.962 + +Slack : -5.746 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.163 +Data Delay : 3.962 + +Slack : -5.746 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.161 -Data Delay : 3.924 +Data Delay : 3.964 -Slack : -5.706 +Slack : -5.746 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.163 -Data Delay : 3.922 - -Slack : -5.706 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.161 -Data Delay : 3.924 +Data Delay : 3.964 -Slack : -5.706 +Slack : -5.746 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.161 -Data Delay : 3.924 +Data Delay : 3.964 -Slack : -5.706 +Slack : -5.746 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.161 -Data Delay : 3.924 +Data Delay : 3.964 -Slack : -5.706 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.161 -Data Delay : 3.924 - -Slack : -5.706 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.161 -Data Delay : 3.924 - -Slack : -5.706 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.161 -Data Delay : 3.924 - -Slack : -5.706 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.161 -Data Delay : 3.924 - -Slack : -5.706 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.161 -Data Delay : 3.924 - -Slack : -5.706 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.161 -Data Delay : 3.924 - -Slack : -5.706 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.161 -Data Delay : 3.924 - -Slack : -5.706 +Slack : -5.746 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.163 -Data Delay : 3.922 - -Slack : -5.706 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 Clock Skew : -0.161 -Data Delay : 3.924 +Data Delay : 3.964 -Slack : -5.706 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.161 -Data Delay : 3.924 - -Slack : -5.706 +Slack : -5.746 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.161 -Data Delay : 3.924 +Data Delay : 3.964 -Slack : -5.706 +Slack : -5.746 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.161 -Data Delay : 3.924 +Data Delay : 3.964 -Slack : -5.706 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.166 -Data Delay : 3.919 - -Slack : -5.706 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.166 -Data Delay : 3.919 - -Slack : -5.706 +Slack : -5.746 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.166 -Data Delay : 3.919 +Clock Skew : -0.161 +Data Delay : 3.964 -Slack : -5.706 +Slack : -5.746 From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.165 -Data Delay : 3.920 +Clock Skew : -0.161 +Data Delay : 3.964 -Slack : -5.375 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.170 -Data Delay : 3.924 - -Slack : -5.356 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.421 -Clock Skew : 0.190 -Data Delay : 3.922 - -Slack : -5.356 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.421 -Clock Skew : 0.190 -Data Delay : 3.922 - -Slack : -5.356 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.421 -Clock Skew : 0.190 -Data Delay : 3.922 - -Slack : -5.356 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.421 -Clock Skew : 0.190 -Data Delay : 3.922 - -Slack : -5.356 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.421 -Clock Skew : 0.190 -Data Delay : 3.922 - -Slack : -5.356 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.421 -Clock Skew : 0.190 -Data Delay : 3.922 - -Slack : -5.355 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.184 -Data Delay : 3.918 - -Slack : -5.355 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.184 -Data Delay : 3.918 - -Slack : -5.355 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.184 -Data Delay : 3.918 - -Slack : -5.355 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.184 -Data Delay : 3.918 - -Slack : -5.355 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.184 -Data Delay : 3.918 - -Slack : -5.355 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.184 -Data Delay : 3.918 - -Slack : -5.355 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.184 -Data Delay : 3.918 - -Slack : -5.355 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.184 -Data Delay : 3.918 - -Slack : -5.355 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.184 -Data Delay : 3.918 - -Slack : -5.354 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.185 -Data Delay : 3.918 - -Slack : -5.353 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.188 -Data Delay : 3.920 - -Slack : -5.351 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.192 -Data Delay : 3.922 - -Slack : -5.347 +Slack : -5.746 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.198 -Data Delay : 3.924 +Clock Skew : -0.161 +Data Delay : 3.964 -Slack : -5.347 +Slack : -5.746 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.198 -Data Delay : 3.924 +Clock Skew : -0.161 +Data Delay : 3.964 -Slack : -5.347 +Slack : -5.746 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.198 -Data Delay : 3.924 +Clock Skew : -0.161 +Data Delay : 3.964 -Slack : -5.347 +Slack : -5.746 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.198 -Data Delay : 3.924 +Clock Skew : -0.161 +Data Delay : 3.964 -Slack : -5.347 +Slack : -5.746 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.198 -Data Delay : 3.924 +Clock Skew : -0.161 +Data Delay : 3.964 -Slack : -5.347 +Slack : -5.746 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.198 -Data Delay : 3.924 +Clock Skew : -0.161 +Data Delay : 3.964 -Slack : -5.347 +Slack : -5.746 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.198 -Data Delay : 3.924 +Clock Skew : -0.161 +Data Delay : 3.964 -Slack : -5.347 +Slack : -5.746 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.198 -Data Delay : 3.924 +Clock Skew : -0.161 +Data Delay : 3.964 -Slack : -5.347 +Slack : -5.746 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.198 -Data Delay : 3.924 +Clock Skew : -0.161 +Data Delay : 3.964 -Slack : -5.347 +Slack : -5.746 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.198 -Data Delay : 3.924 +Clock Skew : -0.161 +Data Delay : 3.964 -Slack : -5.347 +Slack : -5.746 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.198 -Data Delay : 3.924 +Clock Skew : -0.161 +Data Delay : 3.964 -Slack : -5.347 +Slack : -5.746 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.198 -Data Delay : 3.924 +Clock Skew : -0.161 +Data Delay : 3.964 -Slack : -5.347 +Slack : -5.746 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.198 -Data Delay : 3.924 +Clock Skew : -0.161 +Data Delay : 3.964 -Slack : -5.347 +Slack : -5.746 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.198 -Data Delay : 3.924 +Clock Skew : -0.161 +Data Delay : 3.964 + +Slack : -5.746 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.161 +Data Delay : 3.964 + +Slack : -5.396 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.421 +Clock Skew : 0.191 +Data Delay : 3.963 + +Slack : -5.396 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.421 +Clock Skew : 0.191 +Data Delay : 3.963 + +Slack : -5.396 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.421 +Clock Skew : 0.191 +Data Delay : 3.963 + +Slack : -5.396 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.421 +Clock Skew : 0.191 +Data Delay : 3.963 + +Slack : -5.396 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.421 +Clock Skew : 0.191 +Data Delay : 3.963 + +Slack : -5.396 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.421 +Clock Skew : 0.191 +Data Delay : 3.963 + +Slack : -5.394 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.190 +Data Delay : 3.963 + +Slack : -5.394 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.190 +Data Delay : 3.963 + +Slack : -5.394 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.190 +Data Delay : 3.963 + +Slack : -5.394 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.190 +Data Delay : 3.963 + +Slack : -5.394 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.190 +Data Delay : 3.963 + +Slack : -5.391 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.194 +Data Delay : 3.964 + +Slack : -5.391 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.194 +Data Delay : 3.964 + +Slack : -5.390 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.193 +Data Delay : 3.962 + +Slack : -5.389 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.197 +Data Delay : 3.965 + +Slack : -5.370 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.216 +Data Delay : 3.965 + +Slack : -5.370 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.216 +Data Delay : 3.965 + +Slack : -5.370 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.216 +Data Delay : 3.965 + +Slack : -5.370 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.216 +Data Delay : 3.965 + +Slack : -5.370 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.215 +Data Delay : 3.964 + +Slack : -5.361 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.225 +Data Delay : 3.965 + +Slack : -5.361 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.225 +Data Delay : 3.965 + +Slack : -5.361 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.225 +Data Delay : 3.965 + +Slack : -5.361 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.225 +Data Delay : 3.965 + +Slack : -5.361 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.225 +Data Delay : 3.965 + +Slack : -5.361 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.225 +Data Delay : 3.965 +--------------------------------------------------------------------------------+ @@ -6650,743 +6650,743 @@ Data Delay : 3.924 +--------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Removal: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ; +--------------------------------------------------------------------------------+ -Slack : 3.698 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.618 -Data Delay : 3.557 - -Slack : 3.698 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.618 -Data Delay : 3.557 - -Slack : 3.698 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.618 -Data Delay : 3.557 - -Slack : 3.698 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.618 -Data Delay : 3.557 - -Slack : 3.698 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.618 -Data Delay : 3.557 - -Slack : 3.698 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.618 -Data Delay : 3.557 - -Slack : 3.698 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.618 -Data Delay : 3.557 - -Slack : 3.698 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.618 -Data Delay : 3.557 - -Slack : 3.698 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.618 -Data Delay : 3.557 - -Slack : 3.698 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.618 -Data Delay : 3.557 - -Slack : 3.698 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.618 -Data Delay : 3.557 - -Slack : 3.698 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.618 -Data Delay : 3.557 - -Slack : 3.698 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.618 -Data Delay : 3.557 - -Slack : 3.698 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.618 -Data Delay : 3.557 - -Slack : 3.703 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.003 -Clock Skew : 0.609 -Data Delay : 3.556 - -Slack : 3.703 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.003 -Clock Skew : 0.609 -Data Delay : 3.556 - -Slack : 3.703 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.003 -Clock Skew : 0.609 -Data Delay : 3.556 - -Slack : 3.703 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.003 -Clock Skew : 0.609 -Data Delay : 3.556 - -Slack : 3.703 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.003 -Clock Skew : 0.609 -Data Delay : 3.556 - -Slack : 3.703 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.003 -Clock Skew : 0.609 -Data Delay : 3.556 - -Slack : 3.705 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.611 -Data Delay : 3.557 - -Slack : 3.707 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.606 -Data Delay : 3.554 - -Slack : 3.709 +Slack : 3.657 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.603 -Data Delay : 3.553 +Clock Skew : 0.646 +Data Delay : 3.544 -Slack : 3.709 +Slack : 3.657 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.603 -Data Delay : 3.553 +Clock Skew : 0.646 +Data Delay : 3.544 -Slack : 3.709 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.603 -Data Delay : 3.553 - -Slack : 3.709 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.603 -Data Delay : 3.553 - -Slack : 3.709 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.603 -Data Delay : 3.553 - -Slack : 3.710 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.603 -Data Delay : 3.554 - -Slack : 3.710 +Slack : 3.657 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.603 -Data Delay : 3.554 +Clock Skew : 0.646 +Data Delay : 3.544 -Slack : 3.710 +Slack : 3.657 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.646 +Data Delay : 3.544 + +Slack : 3.657 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.646 +Data Delay : 3.544 + +Slack : 3.657 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.603 -Data Delay : 3.554 +Clock Skew : 0.646 +Data Delay : 3.544 -Slack : 3.710 +Slack : 3.667 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.636 +Data Delay : 3.544 + +Slack : 3.667 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.603 -Data Delay : 3.554 +Clock Skew : 0.636 +Data Delay : 3.544 -Slack : 3.710 +Slack : 3.667 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.603 -Data Delay : 3.554 +Clock Skew : 0.636 +Data Delay : 3.544 -Slack : 3.728 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.588 -Data Delay : 3.557 - -Slack : 4.074 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.238 -Data Delay : 3.553 - -Slack : 4.074 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.238 -Data Delay : 3.553 - -Slack : 4.074 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.242 -Data Delay : 3.557 - -Slack : 4.074 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.242 -Data Delay : 3.557 - -Slack : 4.074 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.242 -Data Delay : 3.557 - -Slack : 4.074 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.242 -Data Delay : 3.557 - -Slack : 4.074 +Slack : 3.667 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.238 -Data Delay : 3.553 +Clock Skew : 0.635 +Data Delay : 3.543 -Slack : 4.074 +Slack : 3.668 From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] +To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.238 -Data Delay : 3.553 +Clock Skew : 0.636 +Data Delay : 3.545 -Slack : 4.074 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.238 -Data Delay : 3.553 - -Slack : 4.074 +Slack : 3.687 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.239 -Data Delay : 3.554 +Clock Skew : 0.616 +Data Delay : 3.544 -Slack : 4.075 +Slack : 3.688 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.613 +Data Delay : 3.542 + +Slack : 3.689 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.003 +Clock Skew : 0.610 +Data Delay : 3.543 + +Slack : 3.689 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.003 +Clock Skew : 0.610 +Data Delay : 3.543 + +Slack : 3.689 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.003 +Clock Skew : 0.610 +Data Delay : 3.543 + +Slack : 3.689 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.003 +Clock Skew : 0.610 +Data Delay : 3.543 + +Slack : 3.689 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.003 +Clock Skew : 0.610 +Data Delay : 3.543 + +Slack : 3.689 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.003 +Clock Skew : 0.610 +Data Delay : 3.543 + +Slack : 3.691 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.613 +Data Delay : 3.545 + +Slack : 3.691 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.613 +Data Delay : 3.545 + +Slack : 3.694 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.609 +Data Delay : 3.544 + +Slack : 3.694 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.609 +Data Delay : 3.544 + +Slack : 3.694 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.609 +Data Delay : 3.544 + +Slack : 3.694 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.609 +Data Delay : 3.544 + +Slack : 3.694 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.609 +Data Delay : 3.544 + +Slack : 4.059 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.238 -Data Delay : 3.554 +Clock Skew : 0.244 +Data Delay : 3.544 -Slack : 4.075 +Slack : 4.059 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.238 -Data Delay : 3.554 +Clock Skew : 0.244 +Data Delay : 3.544 -Slack : 4.075 +Slack : 4.059 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.238 -Data Delay : 3.554 +Clock Skew : 0.244 +Data Delay : 3.544 -Slack : 4.075 +Slack : 4.059 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.238 -Data Delay : 3.554 +Clock Skew : 0.244 +Data Delay : 3.544 -Slack : 4.075 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.238 -Data Delay : 3.554 - -Slack : 4.075 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.238 -Data Delay : 3.554 - -Slack : 4.075 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.238 -Data Delay : 3.554 - -Slack : 4.075 +Slack : 4.059 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.238 -Data Delay : 3.554 +Clock Skew : 0.244 +Data Delay : 3.544 -Slack : 4.075 +Slack : 4.059 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.238 -Data Delay : 3.554 +Clock Skew : 0.244 +Data Delay : 3.544 -Slack : 4.075 +Slack : 4.059 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.243 +Data Delay : 3.543 + +Slack : 4.059 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.243 +Data Delay : 3.543 + +Slack : 4.059 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.243 +Data Delay : 3.543 + +Slack : 4.059 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.243 +Data Delay : 3.543 + +Slack : 4.059 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.243 +Data Delay : 3.543 + +Slack : 4.059 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.243 +Data Delay : 3.543 + +Slack : 4.059 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.243 +Data Delay : 3.543 + +Slack : 4.059 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.243 +Data Delay : 3.543 + +Slack : 4.059 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.243 +Data Delay : 3.543 + +Slack : 4.059 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.243 +Data Delay : 3.543 + +Slack : 4.059 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.243 +Data Delay : 3.543 + +Slack : 4.059 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.243 +Data Delay : 3.543 + +Slack : 4.059 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.243 +Data Delay : 3.543 + +Slack : 4.059 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.243 +Data Delay : 3.543 + +Slack : 4.059 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.243 +Data Delay : 3.543 + +Slack : 4.060 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.243 +Data Delay : 3.544 + +Slack : 4.060 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.243 +Data Delay : 3.544 + +Slack : 4.060 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.243 +Data Delay : 3.544 + +Slack : 4.060 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.243 +Data Delay : 3.544 + +Slack : 4.060 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.243 +Data Delay : 3.544 + +Slack : 4.060 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.243 +Data Delay : 3.544 + +Slack : 4.060 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.243 -Data Delay : 3.559 +Data Delay : 3.544 -Slack : 4.075 +Slack : 4.060 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.243 -Data Delay : 3.559 +Data Delay : 3.544 -Slack : 4.075 +Slack : 4.060 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.243 -Data Delay : 3.559 +Data Delay : 3.544 -Slack : 4.075 +Slack : 4.060 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.241 -Data Delay : 3.557 +Data Delay : 3.542 -Slack : 4.075 +Slack : 4.060 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.241 -Data Delay : 3.557 +Data Delay : 3.542 -Slack : 4.075 +Slack : 4.060 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.243 -Data Delay : 3.559 +Data Delay : 3.544 -Slack : 4.075 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.243 -Data Delay : 3.559 - -Slack : 4.075 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.241 -Data Delay : 3.557 - -Slack : 4.075 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.243 -Data Delay : 3.559 - -Slack : 4.075 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.243 -Data Delay : 3.559 - -Slack : 4.075 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.243 -Data Delay : 3.559 - -Slack : 4.075 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.243 -Data Delay : 3.559 - -Slack : 4.075 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.243 -Data Delay : 3.559 - -Slack : 4.075 +Slack : 4.060 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.243 -Data Delay : 3.559 +Data Delay : 3.544 -Slack : 4.075 +Slack : 4.060 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.243 -Data Delay : 3.559 +Data Delay : 3.544 -Slack : 4.075 +Slack : 4.060 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.243 -Data Delay : 3.559 +Data Delay : 3.544 -Slack : 4.075 +Slack : 4.060 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.243 -Data Delay : 3.559 +Data Delay : 3.544 -Slack : 4.075 +Slack : 4.060 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.243 -Data Delay : 3.559 +Data Delay : 3.544 -Slack : 4.075 +Slack : 4.060 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.241 -Data Delay : 3.557 +Clock Skew : 0.243 +Data Delay : 3.544 -Slack : 4.075 +Slack : 4.060 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.243 -Data Delay : 3.559 +Data Delay : 3.544 -Slack : 4.075 +Slack : 4.060 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.243 -Data Delay : 3.559 +Data Delay : 3.544 -Slack : 4.075 +Slack : 4.060 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.243 +Data Delay : 3.544 + +Slack : 4.060 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.243 +Data Delay : 3.544 + +Slack : 4.061 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.243 +Data Delay : 3.545 + +Slack : 4.061 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.243 +Data Delay : 3.545 + +Slack : 4.061 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.243 +Data Delay : 3.545 + +Slack : 4.061 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.243 +Data Delay : 3.545 + +Slack : 4.061 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.243 -Data Delay : 3.559 +Data Delay : 3.545 -Slack : 4.075 +Slack : 4.061 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.243 -Data Delay : 3.559 +Data Delay : 3.545 -Slack : 4.294 +Slack : 4.280 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.190 -Data Delay : 3.669 +Data Delay : 3.655 -Slack : 4.309 +Slack : 4.294 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.192 -Data Delay : 3.686 +Data Delay : 3.671 -Slack : 4.519 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.222 -Data Delay : 3.922 - -Slack : 4.520 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[17] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.225 -Data Delay : 3.926 - -Slack : 4.520 +Slack : 4.505 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.223 -Data Delay : 3.924 +Data Delay : 3.909 -Slack : 4.520 +Slack : 4.505 From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_1 +To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.222 -Data Delay : 3.923 +Data Delay : 3.908 -Slack : 4.520 +Slack : 4.505 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.221 -Data Delay : 3.922 +Data Delay : 3.907 + +Slack : 4.506 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[17] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.225 +Data Delay : 3.912 + +Slack : 4.506 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.222 +Data Delay : 3.909 +--------------------------------------------------------------------------------+ @@ -7400,7 +7400,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_address_reg0 Slack : 9.488 Actual Width : 9.718 @@ -7408,7 +7408,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0 Slack : 9.488 Actual Width : 9.718 @@ -7416,7 +7416,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_we_reg +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_we_reg Slack : 9.488 Actual Width : 9.718 @@ -7424,7 +7424,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_address_reg0 Slack : 9.488 Actual Width : 9.718 @@ -7432,7 +7432,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 Slack : 9.488 Actual Width : 9.718 @@ -7440,7 +7440,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_we_reg +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_we_reg Slack : 9.489 Actual Width : 9.719 @@ -7472,7 +7472,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_address_reg0 Slack : 9.489 Actual Width : 9.719 @@ -7480,7 +7480,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 Slack : 9.489 Actual Width : 9.719 @@ -7488,7 +7488,31 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_we_reg +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_we_reg + +Slack : 9.489 +Actual Width : 9.719 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_address_reg0 + +Slack : 9.489 +Actual Width : 9.719 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 + +Slack : 9.489 +Actual Width : 9.719 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_we_reg Slack : 9.489 Actual Width : 9.719 @@ -7520,7 +7544,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_address_reg0 Slack : 9.489 Actual Width : 9.719 @@ -7528,7 +7552,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 Slack : 9.489 Actual Width : 9.719 @@ -7536,7 +7560,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_we_reg +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_we_reg Slack : 9.489 Actual Width : 9.719 @@ -7544,7 +7568,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_address_reg0 Slack : 9.489 Actual Width : 9.719 @@ -7552,7 +7576,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0 Slack : 9.489 Actual Width : 9.719 @@ -7560,7 +7584,31 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_we_reg +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_we_reg + +Slack : 9.489 +Actual Width : 9.719 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_address_reg0 + +Slack : 9.489 +Actual Width : 9.719 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0 + +Slack : 9.489 +Actual Width : 9.719 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_we_reg Slack : 9.489 Actual Width : 9.719 @@ -7634,61 +7682,13 @@ Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_we_reg -Slack : 9.489 -Actual Width : 9.719 +Slack : 9.490 +Actual Width : 9.720 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0 - -Slack : 9.489 -Actual Width : 9.719 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0 - -Slack : 9.489 -Actual Width : 9.719 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0 - -Slack : 9.489 -Actual Width : 9.719 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1~porta_address_reg0 - -Slack : 9.489 -Actual Width : 9.719 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2~porta_address_reg0 - -Slack : 9.489 -Actual Width : 9.719 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 - -Slack : 9.489 -Actual Width : 9.719 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_address_reg0 Slack : 9.490 Actual Width : 9.720 @@ -7696,7 +7696,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0 Slack : 9.490 Actual Width : 9.720 @@ -7704,7 +7704,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_we_reg Slack : 9.490 Actual Width : 9.720 @@ -7712,7 +7712,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_we_reg +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_address_reg0 Slack : 9.490 Actual Width : 9.720 @@ -7720,112 +7720,40 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0 + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_we_reg + +Slack : 9.491 +Actual Width : 9.721 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_address_reg0 -Slack : 9.490 -Actual Width : 9.720 +Slack : 9.491 +Actual Width : 9.721 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Slack : 9.490 -Actual Width : 9.720 +Slack : 9.491 +Actual Width : 9.721 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_we_reg -Slack : 9.490 -Actual Width : 9.720 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_address_reg0 - -Slack : 9.490 -Actual Width : 9.720 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0 - -Slack : 9.490 -Actual Width : 9.720 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_we_reg - -Slack : 9.490 -Actual Width : 9.720 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_address_reg0 - -Slack : 9.490 -Actual Width : 9.720 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0 - -Slack : 9.490 -Actual Width : 9.720 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_we_reg - -Slack : 9.490 -Actual Width : 9.720 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0 - -Slack : 9.490 -Actual Width : 9.720 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 - -Slack : 9.490 -Actual Width : 9.720 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5~porta_address_reg0 - -Slack : 9.490 -Actual Width : 9.720 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 - -Slack : 9.490 -Actual Width : 9.720 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9~porta_address_reg0 - Slack : 9.491 Actual Width : 9.721 Required Width : 0.230 @@ -7850,189 +7778,13 @@ Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_we_reg -Slack : 9.491 -Actual Width : 9.721 +Slack : 9.498 +Actual Width : 9.728 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_address_reg0 - -Slack : 9.491 -Actual Width : 9.721 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0 - -Slack : 9.491 -Actual Width : 9.721 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_we_reg - -Slack : 9.491 -Actual Width : 9.721 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13~porta_address_reg0 - -Slack : 9.491 -Actual Width : 9.721 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 - -Slack : 9.491 -Actual Width : 9.721 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0 - -Slack : 9.491 -Actual Width : 9.721 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8~porta_address_reg0 - -Slack : 9.493 -Actual Width : 9.723 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 - -Slack : 9.493 -Actual Width : 9.723 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 - -Slack : 9.493 -Actual Width : 9.723 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 - -Slack : 9.493 -Actual Width : 9.723 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 - -Slack : 9.493 -Actual Width : 9.723 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2 - -Slack : 9.493 -Actual Width : 9.723 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 - -Slack : 9.493 -Actual Width : 9.723 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 - -Slack : 9.494 -Actual Width : 9.724 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 - -Slack : 9.494 -Actual Width : 9.724 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 - -Slack : 9.494 -Actual Width : 9.724 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 - -Slack : 9.494 -Actual Width : 9.724 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 - -Slack : 9.494 -Actual Width : 9.724 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 - -Slack : 9.495 -Actual Width : 9.725 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 - -Slack : 9.495 -Actual Width : 9.725 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 - -Slack : 9.495 -Actual Width : 9.725 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 - -Slack : 9.495 -Actual Width : 9.725 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14 Slack : 9.498 Actual Width : 9.728 @@ -8040,15 +7792,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11 - -Slack : 9.498 -Actual Width : 9.728 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4 Slack : 9.499 Actual Width : 9.729 @@ -8064,7 +7808,15 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 + +Slack : 9.499 +Actual Width : 9.729 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11 Slack : 9.499 Actual Width : 9.729 @@ -8080,7 +7832,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15 Slack : 9.499 Actual Width : 9.729 @@ -8088,7 +7840,23 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2 + +Slack : 9.499 +Actual Width : 9.729 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~PORTBDATAOUT0 + +Slack : 9.499 +Actual Width : 9.729 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6 Slack : 9.499 Actual Width : 9.729 @@ -8128,7 +7896,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 Slack : 9.500 Actual Width : 9.730 @@ -8136,7 +7904,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~PORTBDATAOUT0 Slack : 9.500 Actual Width : 9.730 @@ -8144,7 +7912,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 Slack : 9.500 Actual Width : 9.730 @@ -8152,15 +7920,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~PORTBDATAOUT0 - -Slack : 9.500 -Actual Width : 9.730 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~PORTBDATAOUT0 Slack : 9.500 Actual Width : 9.730 @@ -8176,7 +7936,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1 Slack : 9.501 Actual Width : 9.731 @@ -8184,15 +7944,255 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 + +Slack : 9.501 +Actual Width : 9.731 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3 + +Slack : 9.501 +Actual Width : 9.731 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 + +Slack : 9.501 +Actual Width : 9.731 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~PORTBDATAOUT0 + +Slack : 9.502 +Actual Width : 9.732 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 + +Slack : 9.502 +Actual Width : 9.732 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 + +Slack : 9.502 +Actual Width : 9.732 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 + +Slack : 9.502 +Actual Width : 9.732 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 + +Slack : 9.502 +Actual Width : 9.732 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 -Slack : 9.501 -Actual Width : 9.731 +Slack : 9.502 +Actual Width : 9.732 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~PORTBDATAOUT0 + +Slack : 9.502 +Actual Width : 9.732 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 + +Slack : 9.502 +Actual Width : 9.732 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~PORTBDATAOUT0 + +Slack : 9.502 +Actual Width : 9.732 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 + +Slack : 9.502 +Actual Width : 9.732 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 + +Slack : 9.502 +Actual Width : 9.732 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 + +Slack : 9.502 +Actual Width : 9.732 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 + +Slack : 9.503 +Actual Width : 9.733 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 + +Slack : 9.503 +Actual Width : 9.733 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 + +Slack : 9.504 +Actual Width : 9.734 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_datain_reg0 + +Slack : 9.504 +Actual Width : 9.734 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 + +Slack : 9.504 +Actual Width : 9.734 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 + +Slack : 9.504 +Actual Width : 9.734 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_datain_reg0 + +Slack : 9.505 +Actual Width : 9.735 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_datain_reg0 + +Slack : 9.505 +Actual Width : 9.735 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_datain_reg0 + +Slack : 9.505 +Actual Width : 9.735 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_datain_reg0 + +Slack : 9.505 +Actual Width : 9.735 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_datain_reg0 + +Slack : 9.505 +Actual Width : 9.735 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_datain_reg0 + +Slack : 9.505 +Actual Width : 9.735 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_datain_reg0 + +Slack : 9.505 +Actual Width : 9.735 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_datain_reg0 + +Slack : 9.505 +Actual Width : 9.735 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_datain_reg0 + +Slack : 9.505 +Actual Width : 9.735 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_datain_reg0 + +Slack : 9.505 +Actual Width : 9.735 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_datain_reg0 +--------------------------------------------------------------------------------+ @@ -8206,7 +8206,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_address_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_address_reg0 Slack : 19.602 Actual Width : 19.832 @@ -8214,7 +8214,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 Slack : 19.602 Actual Width : 19.832 @@ -8222,7 +8222,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_we_reg +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_we_reg Slack : 19.602 Actual Width : 19.832 @@ -8230,7 +8230,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_address_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_address_reg0 Slack : 19.602 Actual Width : 19.832 @@ -8238,7 +8238,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0 Slack : 19.602 Actual Width : 19.832 @@ -8246,7 +8246,55 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_we_reg +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_we_reg + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_address_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_we_reg + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_address_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_we_reg Slack : 19.602 Actual Width : 19.832 @@ -8272,54 +8320,6 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_we_reg -Slack : 19.602 -Actual Width : 19.832 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_address_reg0 - -Slack : 19.602 -Actual Width : 19.832 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 - -Slack : 19.602 -Actual Width : 19.832 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_we_reg - -Slack : 19.602 -Actual Width : 19.832 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_address_reg0 - -Slack : 19.602 -Actual Width : 19.832 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0 - -Slack : 19.602 -Actual Width : 19.832 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_we_reg - Slack : 19.602 Actual Width : 19.832 Required Width : 0.230 @@ -8350,7 +8350,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_address_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_address_reg0 Slack : 19.602 Actual Width : 19.832 @@ -8358,7 +8358,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 Slack : 19.602 Actual Width : 19.832 @@ -8366,31 +8366,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_we_reg - -Slack : 19.602 -Actual Width : 19.832 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_address_reg0 - -Slack : 19.602 -Actual Width : 19.832 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0 - -Slack : 19.602 -Actual Width : 19.832 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_we_reg +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_we_reg Slack : 19.602 Actual Width : 19.832 @@ -8416,6 +8392,78 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_we_reg +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_address_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_we_reg + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_we_reg + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_address_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_we_reg + Slack : 19.602 Actual Width : 19.832 Required Width : 0.230 @@ -8446,7 +8494,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_address_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_address_reg0 Slack : 19.602 Actual Width : 19.832 @@ -8454,7 +8502,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0 Slack : 19.602 Actual Width : 19.832 @@ -8462,7 +8510,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_we_reg +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_we_reg Slack : 19.602 Actual Width : 19.832 @@ -8470,7 +8518,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_address_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_address_reg0 Slack : 19.602 Actual Width : 19.832 @@ -8478,7 +8526,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 Slack : 19.602 Actual Width : 19.832 @@ -8486,7 +8534,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_we_reg +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_we_reg Slack : 19.602 Actual Width : 19.832 @@ -8518,7 +8566,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_address_reg0 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0 Slack : 19.602 Actual Width : 19.832 @@ -8526,7 +8574,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 Slack : 19.602 Actual Width : 19.832 @@ -8534,7 +8582,15 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_we_reg +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 + +Slack : 19.602 +Actual Width : 19.832 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9~porta_address_reg0 Slack : 19.603 Actual Width : 19.833 @@ -8542,7 +8598,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_address_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_address_reg0 Slack : 19.603 Actual Width : 19.833 @@ -8550,7 +8606,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0 Slack : 19.603 Actual Width : 19.833 @@ -8558,7 +8614,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_we_reg +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_we_reg Slack : 19.603 Actual Width : 19.833 @@ -8566,7 +8622,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_address_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_address_reg0 Slack : 19.603 Actual Width : 19.833 @@ -8574,7 +8630,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 Slack : 19.603 Actual Width : 19.833 @@ -8582,7 +8638,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_we_reg +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_we_reg Slack : 19.603 Actual Width : 19.833 @@ -8590,7 +8646,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_address_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_address_reg0 Slack : 19.603 Actual Width : 19.833 @@ -8598,7 +8654,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0 Slack : 19.603 Actual Width : 19.833 @@ -8606,7 +8662,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_we_reg +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_we_reg Slack : 19.603 Actual Width : 19.833 @@ -8680,30 +8736,6 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_we_reg -Slack : 19.603 -Actual Width : 19.833 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_address_reg0 - -Slack : 19.603 -Actual Width : 19.833 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0 - -Slack : 19.603 -Actual Width : 19.833 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_we_reg - Slack : 19.603 Actual Width : 19.833 Required Width : 0.230 @@ -8728,6 +8760,54 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_we_reg +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_address_reg0 + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_we_reg + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_address_reg0 + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0 + +Slack : 19.603 +Actual Width : 19.833 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_we_reg + Slack : 19.603 Actual Width : 19.833 Required Width : 0.230 @@ -8806,7 +8886,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_address_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_address_reg0 Slack : 19.603 Actual Width : 19.833 @@ -8814,7 +8894,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 Slack : 19.603 Actual Width : 19.833 @@ -8822,7 +8902,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_we_reg +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_we_reg Slack : 19.603 Actual Width : 19.833 @@ -8830,7 +8910,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_address_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_address_reg0 Slack : 19.603 Actual Width : 19.833 @@ -8838,7 +8918,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0 Slack : 19.603 Actual Width : 19.833 @@ -8846,7 +8926,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_we_reg +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_we_reg Slack : 19.603 Actual Width : 19.833 @@ -8854,7 +8934,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_address_reg0 Slack : 19.603 Actual Width : 19.833 @@ -8862,7 +8942,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 Slack : 19.603 Actual Width : 19.833 @@ -8870,7 +8950,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_we_reg +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_we_reg Slack : 19.603 Actual Width : 19.833 @@ -8878,7 +8958,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_address_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_address_reg0 Slack : 19.603 Actual Width : 19.833 @@ -8886,7 +8966,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0 Slack : 19.603 Actual Width : 19.833 @@ -8894,7 +8974,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_we_reg +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_we_reg Slack : 19.603 Actual Width : 19.833 @@ -8902,7 +8982,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_address_reg0 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0 Slack : 19.603 Actual Width : 19.833 @@ -8910,7 +8990,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0 Slack : 19.603 Actual Width : 19.833 @@ -8918,87 +8998,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_we_reg - -Slack : 19.604 -Actual Width : 19.834 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_address_reg0 - -Slack : 19.604 -Actual Width : 19.834 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0 - -Slack : 19.604 -Actual Width : 19.834 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_we_reg - -Slack : 19.604 -Actual Width : 19.834 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_address_reg0 - -Slack : 19.604 -Actual Width : 19.834 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 - -Slack : 19.604 -Actual Width : 19.834 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_we_reg - -Slack : 19.604 -Actual Width : 19.820 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|VGA_HS~_Duplicate_1 - -Slack : 19.604 -Actual Width : 19.820 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|attr[0] - -Slack : 19.604 -Actual Width : 19.820 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|attr[1] - -Slack : 19.604 -Actual Width : 19.820 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|attr[2] +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13~porta_address_reg0 +--------------------------------------------------------------------------------+ @@ -9006,29 +9006,125 @@ Target : ula:ula_|video:video_|attr[2] +--------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ; +--------------------------------------------------------------------------------+ -Slack : 20.595 -Actual Width : 20.811 +Slack : 20.597 +Actual Width : 20.813 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] -Slack : 20.598 -Actual Width : 20.814 +Slack : 20.597 +Actual Width : 20.813 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] -Slack : 20.598 -Actual Width : 20.814 +Slack : 20.597 +Actual Width : 20.813 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] + +Slack : 20.597 +Actual Width : 20.813 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] + +Slack : 20.597 +Actual Width : 20.813 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] + +Slack : 20.597 +Actual Width : 20.813 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] + +Slack : 20.597 +Actual Width : 20.813 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] + +Slack : 20.597 +Actual Width : 20.813 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] + +Slack : 20.597 +Actual Width : 20.813 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] + +Slack : 20.597 +Actual Width : 20.813 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] + +Slack : 20.597 +Actual Width : 20.813 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] + +Slack : 20.597 +Actual Width : 20.813 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] + +Slack : 20.597 +Actual Width : 20.813 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] + +Slack : 20.597 +Actual Width : 20.813 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] + +Slack : 20.597 +Actual Width : 20.813 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] Slack : 20.598 Actual Width : 20.814 @@ -9046,6 +9142,22 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] +Slack : 20.598 +Actual Width : 20.814 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 + +Slack : 20.598 +Actual Width : 20.814 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] + Slack : 20.598 Actual Width : 20.814 Required Width : 0.216 @@ -9054,6 +9166,14 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] +Slack : 20.598 +Actual Width : 20.814 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] + Slack : 20.598 Actual Width : 20.814 Required Width : 0.216 @@ -9068,7 +9188,7 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 +Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] Slack : 20.598 Actual Width : 20.814 @@ -9076,7 +9196,63 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] +Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] + +Slack : 20.598 +Actual Width : 20.814 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] + +Slack : 20.598 +Actual Width : 20.814 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] + +Slack : 20.598 +Actual Width : 20.814 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] + +Slack : 20.598 +Actual Width : 20.814 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] + +Slack : 20.598 +Actual Width : 20.814 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] + +Slack : 20.599 +Actual Width : 20.815 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|nbit[1] + +Slack : 20.599 +Actual Width : 20.815 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|nbit[2] Slack : 20.599 Actual Width : 20.815 @@ -9190,14 +9366,6 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] -Slack : 20.599 -Actual Width : 20.815 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|state.Ack - Slack : 20.599 Actual Width : 20.815 Required Width : 0.216 @@ -9230,310 +9398,70 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2c_loader:i2c_loader_|state.Start -Slack : 20.599 -Actual Width : 20.815 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|state.Stop - -Slack : 20.599 -Actual Width : 20.815 +Slack : 20.600 +Actual Width : 20.816 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] -Slack : 20.599 -Actual Width : 20.815 +Slack : 20.600 +Actual Width : 20.816 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] -Slack : 20.599 -Actual Width : 20.815 +Slack : 20.600 +Actual Width : 20.816 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] -Slack : 20.599 -Actual Width : 20.815 +Slack : 20.600 +Actual Width : 20.816 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] -Slack : 20.599 -Actual Width : 20.815 +Slack : 20.600 +Actual Width : 20.816 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] -Slack : 20.599 -Actual Width : 20.815 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 - -Slack : 20.599 -Actual Width : 20.815 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] - -Slack : 20.599 -Actual Width : 20.815 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] - -Slack : 20.599 -Actual Width : 20.815 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] - -Slack : 20.599 -Actual Width : 20.815 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] - -Slack : 20.599 -Actual Width : 20.815 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] - -Slack : 20.599 -Actual Width : 20.815 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] - -Slack : 20.599 -Actual Width : 20.815 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] - -Slack : 20.599 -Actual Width : 20.815 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] - Slack : 20.604 Actual Width : 20.820 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] -Slack : 20.607 -Actual Width : 20.823 +Slack : 20.609 +Actual Width : 20.825 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] +Target : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 -Slack : 20.607 -Actual Width : 20.823 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] - -Slack : 20.607 -Actual Width : 20.823 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] - -Slack : 20.607 -Actual Width : 20.823 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] - -Slack : 20.607 -Actual Width : 20.823 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] - -Slack : 20.607 -Actual Width : 20.823 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] - -Slack : 20.607 -Actual Width : 20.823 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] - -Slack : 20.607 -Actual Width : 20.823 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] - -Slack : 20.607 -Actual Width : 20.823 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] - -Slack : 20.607 -Actual Width : 20.823 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] - -Slack : 20.607 -Actual Width : 20.823 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] - -Slack : 20.607 -Actual Width : 20.823 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] - -Slack : 20.607 -Actual Width : 20.823 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] - -Slack : 20.607 -Actual Width : 20.823 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] - -Slack : 20.608 -Actual Width : 20.824 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] - -Slack : 20.608 -Actual Width : 20.824 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] - -Slack : 20.608 -Actual Width : 20.824 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] - -Slack : 20.608 -Actual Width : 20.824 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] - -Slack : 20.608 -Actual Width : 20.824 +Slack : 20.609 +Actual Width : 20.825 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] -Slack : 20.608 -Actual Width : 20.824 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 - -Slack : 20.609 -Actual Width : 20.825 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] - -Slack : 20.609 -Actual Width : 20.825 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] - Slack : 20.609 Actual Width : 20.825 Required Width : 0.216 @@ -9550,13 +9478,85 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] -Slack : 20.615 -Actual Width : 20.831 +Slack : 20.610 +Actual Width : 20.826 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] +Target : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 + +Slack : 20.611 +Actual Width : 20.827 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] + +Slack : 20.611 +Actual Width : 20.827 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] + +Slack : 20.611 +Actual Width : 20.827 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] + +Slack : 20.611 +Actual Width : 20.827 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] + +Slack : 20.611 +Actual Width : 20.827 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] + +Slack : 20.611 +Actual Width : 20.827 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] + +Slack : 20.613 +Actual Width : 20.829 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|nbit[0] + +Slack : 20.613 +Actual Width : 20.829 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|state.Ack + +Slack : 20.613 +Actual Width : 20.829 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|state.Stop Slack : 20.647 Actual Width : 20.863 @@ -9654,13 +9654,77 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Fall Target : ula:ula_|i2c_loader:i2c_loader_|divider[5] -Slack : 20.684 -Actual Width : 20.868 +Slack : 20.687 +Actual Width : 20.871 Required Width : 0.184 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] +Target : ula:ula_|i2c_loader:i2c_loader_|state.Ack + +Slack : 20.687 +Actual Width : 20.871 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|state.Stop + +Slack : 20.688 +Actual Width : 20.872 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|nbit[0] + +Slack : 20.690 +Actual Width : 20.874 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] + +Slack : 20.690 +Actual Width : 20.874 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] + +Slack : 20.690 +Actual Width : 20.874 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] + +Slack : 20.690 +Actual Width : 20.874 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] + +Slack : 20.690 +Actual Width : 20.874 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] + +Slack : 20.690 +Actual Width : 20.874 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] Slack : 20.691 Actual Width : 20.846 @@ -9678,6 +9742,46 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2c_loader:i2c_loader_|sda_out +Slack : 20.691 +Actual Width : 20.875 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 + +Slack : 20.691 +Actual Width : 20.875 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] + +Slack : 20.691 +Actual Width : 20.875 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8] + +Slack : 20.691 +Actual Width : 20.875 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] + +Slack : 20.691 +Actual Width : 20.875 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 + Slack : 20.692 Actual Width : 20.847 Required Width : 0.155 @@ -9694,62 +9798,6 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_1 -Slack : 20.692 -Actual Width : 20.876 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] - -Slack : 20.692 -Actual Width : 20.876 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] - -Slack : 20.692 -Actual Width : 20.876 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] - -Slack : 20.692 -Actual Width : 20.876 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] - -Slack : 20.692 -Actual Width : 20.876 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] - -Slack : 20.692 -Actual Width : 20.876 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8] - -Slack : 20.692 -Actual Width : 20.876 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] - Slack : 20.692 Actual Width : 20.847 Required Width : 0.155 @@ -9757,54 +9805,6 @@ Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|mclk_r - -Slack : 20.692 -Actual Width : 20.876 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 - -Slack : 20.692 -Actual Width : 20.847 -Required Width : 0.155 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[17] - -Slack : 20.693 -Actual Width : 20.848 -Required Width : 0.155 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrclk_r - -Slack : 20.693 -Actual Width : 20.877 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] - -Slack : 20.693 -Actual Width : 20.877 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] - -Slack : 20.694 -Actual Width : 20.878 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] +--------------------------------------------------------------------------------+ @@ -9932,43 +9932,43 @@ Target : ula:ula_|clocks:clocks_|counter[0] +--------------------------------------------------------------------------------+ Data Port : raw_loader_in Clock Port : CLOCK_50 -Rise : 1.981 -Fall : 2.458 +Rise : 1.693 +Fall : 2.046 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : raw_loader_in Clock Port : CLOCK_50 -Rise : 3.874 -Fall : 4.319 +Rise : 3.641 +Fall : 3.954 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : SW[*] Clock Port : CLOCK_50 -Rise : 1.011 -Fall : 1.277 +Rise : 1.010 +Fall : 1.278 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Data Port : SW[2] Clock Port : CLOCK_50 -Rise : 1.011 -Fall : 1.277 +Rise : 1.010 +Fall : 1.278 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Data Port : AUD_ADCDAT Clock Port : CLOCK_50 -Rise : 1.262 -Fall : 1.505 +Rise : 1.624 +Fall : 1.864 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Data Port : I2C_SDAT Clock Port : CLOCK_50 -Rise : 2.823 -Fall : 3.104 +Rise : 2.876 +Fall : 3.109 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ @@ -9980,43 +9980,43 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ Data Port : raw_loader_in Clock Port : CLOCK_50 -Rise : -1.568 -Fall : -2.042 +Rise : -1.306 +Fall : -1.657 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : raw_loader_in Clock Port : CLOCK_50 -Rise : -2.986 -Fall : -3.436 +Rise : -2.643 +Fall : -2.954 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : SW[*] Clock Port : CLOCK_50 -Rise : -0.397 -Fall : -0.660 +Rise : -0.395 +Fall : -0.661 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Data Port : SW[2] Clock Port : CLOCK_50 -Rise : -0.397 -Fall : -0.660 +Rise : -0.395 +Fall : -0.661 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Data Port : AUD_ADCDAT Clock Port : CLOCK_50 -Rise : -0.645 -Fall : -0.878 +Rise : -1.019 +Fall : -1.250 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Data Port : I2C_SDAT Clock Port : CLOCK_50 -Rise : -1.355 -Fall : -1.593 +Rise : -1.337 +Fall : -1.575 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ @@ -10028,197 +10028,197 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ Data Port : GPIO_1[*] Clock Port : CLOCK_50 -Rise : 10.359 -Fall : 10.359 +Rise : 9.798 +Fall : 9.748 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[16] Clock Port : CLOCK_50 -Rise : 10.359 -Fall : 10.359 +Rise : 9.705 +Fall : 9.748 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[17] Clock Port : CLOCK_50 -Rise : 9.229 -Fall : 9.317 +Rise : 9.555 +Fall : 9.493 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[18] Clock Port : CLOCK_50 -Rise : 10.015 -Fall : 9.971 +Rise : 9.798 +Fall : 9.738 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[19] Clock Port : CLOCK_50 -Rise : 9.628 -Fall : 9.644 +Rise : 9.757 +Fall : 9.715 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[20] Clock Port : CLOCK_50 -Rise : 9.826 -Fall : 9.843 +Rise : 9.549 +Fall : 9.489 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[21] Clock Port : CLOCK_50 -Rise : 9.397 -Fall : 9.318 +Rise : 9.522 +Fall : 9.546 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[22] Clock Port : CLOCK_50 -Rise : 9.972 -Fall : 9.975 +Rise : 9.748 +Fall : 9.728 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[23] Clock Port : CLOCK_50 -Rise : 9.201 -Fall : 9.152 +Rise : 9.098 +Fall : 9.177 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[*] Clock Port : CLOCK_50 -Rise : 7.986 -Fall : 7.983 +Rise : 7.976 +Fall : 8.000 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[16] Clock Port : CLOCK_50 -Rise : 7.696 -Fall : 7.696 +Rise : 7.875 +Fall : 7.912 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[17] Clock Port : CLOCK_50 -Rise : 7.783 -Fall : 7.821 +Rise : 7.501 +Fall : 7.536 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[18] Clock Port : CLOCK_50 -Rise : 7.371 -Fall : 7.388 +Rise : 7.551 +Fall : 7.531 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[19] Clock Port : CLOCK_50 -Rise : 7.739 -Fall : 7.774 +Rise : 7.805 +Fall : 7.843 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[20] Clock Port : CLOCK_50 -Rise : 7.986 -Fall : 7.975 +Rise : 7.428 +Fall : 7.368 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[21] Clock Port : CLOCK_50 -Rise : 7.534 -Fall : 7.528 +Rise : 7.976 +Fall : 8.000 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[22] Clock Port : CLOCK_50 -Rise : 7.914 -Fall : 7.983 +Rise : 7.923 +Fall : 7.903 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[23] Clock Port : CLOCK_50 -Rise : 7.285 -Fall : 7.303 +Rise : 7.748 +Fall : 7.835 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[*] Clock Port : CLOCK_50 -Rise : 8.197 -Fall : 7.907 +Rise : 8.499 +Fall : 8.077 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[0] Clock Port : CLOCK_50 -Rise : 8.197 -Fall : 7.907 +Rise : 8.499 +Fall : 8.077 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[1] Clock Port : CLOCK_50 -Rise : 6.071 -Fall : 5.974 +Rise : 6.645 +Fall : 6.554 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[2] Clock Port : CLOCK_50 -Rise : 6.410 -Fall : 6.400 +Rise : 6.682 +Fall : 6.538 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[3] Clock Port : CLOCK_50 -Rise : 6.836 -Fall : 6.810 +Rise : 6.778 +Fall : 6.679 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[*] Clock Port : CLOCK_50 -Rise : 6.558 -Fall : 6.425 +Rise : 6.936 +Fall : 6.847 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[0] Clock Port : CLOCK_50 -Rise : 6.558 -Fall : 6.425 +Rise : 6.658 +Fall : 6.538 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[1] Clock Port : CLOCK_50 -Rise : 6.366 -Fall : 6.305 +Rise : 6.936 +Fall : 6.847 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[2] Clock Port : CLOCK_50 -Rise : 6.429 -Fall : 6.279 +Rise : 6.905 +Fall : 6.787 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[3] Clock Port : CLOCK_50 -Rise : 6.429 -Fall : 6.279 +Rise : 6.881 +Fall : 6.765 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] @@ -10231,36 +10231,36 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[*] Clock Port : CLOCK_50 -Rise : 6.621 -Fall : 6.664 +Rise : 7.442 +Fall : 7.459 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[0] Clock Port : CLOCK_50 -Rise : 6.621 -Fall : 6.664 +Rise : 7.239 +Fall : 7.169 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[1] Clock Port : CLOCK_50 -Rise : 6.426 -Fall : 6.412 +Rise : 7.442 +Fall : 7.459 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[2] Clock Port : CLOCK_50 -Rise : 6.231 -Fall : 6.211 +Rise : 6.381 +Fall : 6.270 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[3] Clock Port : CLOCK_50 -Rise : 6.443 -Fall : 6.428 +Rise : 6.900 +Fall : 6.786 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] @@ -10328,197 +10328,197 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ Data Port : GPIO_1[*] Clock Port : CLOCK_50 -Rise : 7.669 -Fall : 7.651 +Rise : 8.372 +Fall : 8.404 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[16] Clock Port : CLOCK_50 -Rise : 8.267 -Fall : 8.296 +Rise : 8.723 +Fall : 8.730 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[17] Clock Port : CLOCK_50 -Rise : 8.307 -Fall : 8.286 +Rise : 8.620 +Fall : 8.564 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[18] Clock Port : CLOCK_50 -Rise : 7.669 -Fall : 7.651 +Rise : 8.672 +Fall : 8.618 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[19] Clock Port : CLOCK_50 -Rise : 8.069 -Fall : 8.077 +Rise : 8.614 +Fall : 8.575 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[20] Clock Port : CLOCK_50 -Rise : 8.420 -Fall : 8.430 +Rise : 8.452 +Fall : 8.404 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[21] Clock Port : CLOCK_50 -Rise : 7.905 -Fall : 7.819 +Rise : 8.677 +Fall : 8.704 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[22] Clock Port : CLOCK_50 -Rise : 7.716 -Fall : 7.719 +Rise : 9.019 +Fall : 9.006 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[23] Clock Port : CLOCK_50 -Rise : 7.805 -Fall : 7.751 +Rise : 8.372 +Fall : 8.423 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[*] Clock Port : CLOCK_50 -Rise : 5.460 -Fall : 5.452 +Rise : 5.700 +Fall : 5.689 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[16] Clock Port : CLOCK_50 -Rise : 6.523 -Fall : 6.572 +Rise : 6.735 +Fall : 6.742 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[17] Clock Port : CLOCK_50 -Rise : 6.581 -Fall : 6.660 +Rise : 6.344 +Fall : 6.354 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[18] Clock Port : CLOCK_50 -Rise : 6.318 -Fall : 6.325 +Rise : 6.577 +Fall : 6.551 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[19] Clock Port : CLOCK_50 -Rise : 6.316 -Fall : 6.388 +Rise : 5.700 +Fall : 5.689 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[20] Clock Port : CLOCK_50 -Rise : 5.460 -Fall : 5.452 +Rise : 6.064 +Fall : 6.051 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[21] Clock Port : CLOCK_50 -Rise : 6.325 -Fall : 6.358 +Rise : 6.607 +Fall : 6.635 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[22] Clock Port : CLOCK_50 -Rise : 6.708 -Fall : 6.750 +Rise : 6.771 +Fall : 6.823 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[23] Clock Port : CLOCK_50 -Rise : 6.065 -Fall : 6.060 +Rise : 6.392 +Fall : 6.494 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[*] Clock Port : CLOCK_50 -Rise : 3.938 -Fall : 3.816 +Rise : 3.816 +Fall : 3.714 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[0] Clock Port : CLOCK_50 -Rise : 5.979 -Fall : 5.590 +Rise : 5.891 +Fall : 5.507 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[1] Clock Port : CLOCK_50 -Rise : 3.938 -Fall : 3.816 +Rise : 3.816 +Fall : 3.714 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[2] Clock Port : CLOCK_50 -Rise : 4.183 -Fall : 4.073 +Rise : 4.066 +Fall : 3.959 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[3] Clock Port : CLOCK_50 -Rise : 4.592 -Fall : 4.467 +Rise : 4.158 +Fall : 4.095 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[*] Clock Port : CLOCK_50 -Rise : 4.007 -Fall : 3.940 +Rise : 3.866 +Fall : 3.768 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[0] Clock Port : CLOCK_50 -Rise : 4.406 -Fall : 4.287 +Rise : 3.879 +Fall : 3.779 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[1] Clock Port : CLOCK_50 -Rise : 4.007 -Fall : 3.940 +Rise : 3.866 +Fall : 3.768 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[2] Clock Port : CLOCK_50 -Rise : 4.282 -Fall : 4.147 +Rise : 4.116 +Fall : 4.018 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[3] Clock Port : CLOCK_50 -Rise : 4.282 -Fall : 4.147 +Rise : 4.093 +Fall : 3.996 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] @@ -10531,36 +10531,36 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[*] Clock Port : CLOCK_50 -Rise : 3.864 -Fall : 3.753 +Rise : 3.614 +Fall : 3.521 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[0] Clock Port : CLOCK_50 -Rise : 4.238 -Fall : 4.188 +Rise : 4.437 +Fall : 4.384 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[1] Clock Port : CLOCK_50 -Rise : 4.151 -Fall : 4.091 +Rise : 4.239 +Fall : 4.194 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[2] Clock Port : CLOCK_50 -Rise : 3.864 -Fall : 3.753 +Rise : 3.614 +Fall : 3.521 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[3] Clock Port : CLOCK_50 -Rise : 4.068 -Fall : 3.961 +Rise : 4.112 +Fall : 4.016 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] @@ -10628,10 +10628,10 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ Input Port : SW[1] Output Port : LED[0] -RR : 4.629 +RR : 4.640 RF : FR : -FF : 4.693 +FF : 4.702 Input Port : SW[2] Output Port : LED[2] @@ -10642,17 +10642,17 @@ FF : 4.195 Input Port : raw_loader_in Output Port : GPIO_1[22] -RR : 6.626 +RR : 6.764 RF : FR : -FF : 7.003 +FF : 7.009 Input Port : raw_loader_in Output Port : LED[3] -RR : 4.318 +RR : 4.399 RF : FR : -FF : 4.517 +FF : 4.625 +--------------------------------------------------------------------------------+ @@ -10662,10 +10662,10 @@ FF : 4.517 +--------------------------------------------------------------------------------+ Input Port : SW[1] Output Port : LED[0] -RR : 4.491 +RR : 4.502 RF : FR : -FF : 4.559 +FF : 4.568 Input Port : SW[2] Output Port : LED[2] @@ -10676,17 +10676,17 @@ FF : 4.081 Input Port : raw_loader_in Output Port : GPIO_1[22] -RR : 6.402 +RR : 6.534 RF : FR : -FF : 6.769 +FF : 6.775 Input Port : raw_loader_in Output Port : LED[3] -RR : 4.186 +RR : 4.263 RF : FR : -FF : 4.384 +FF : 4.487 +--------------------------------------------------------------------------------+ @@ -10700,22 +10700,22 @@ No synchronizer chains to report. +--------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Fmax Summary ; +--------------------------------------------------------------------------------+ -Fmax : 51.79 MHz -Restricted Fmax : 51.79 MHz +Fmax : 53.08 MHz +Restricted Fmax : 53.08 MHz Clock Name : CLOCK_50 Note : -Fmax : 138.35 MHz -Restricted Fmax : 138.35 MHz +Fmax : 143.6 MHz +Restricted Fmax : 143.6 MHz Clock Name : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Note : -Fmax : 177.12 MHz -Restricted Fmax : 177.12 MHz +Fmax : 190.48 MHz +Restricted Fmax : 190.48 MHz Clock Name : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Note : -Fmax : 1052.63 MHz +Fmax : 1054.85 MHz Restricted Fmax : 500.0 MHz Clock Name : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Note : limit due to minimum period restriction (tmin) @@ -10728,20 +10728,20 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp ; Slow 1200mV 0C Model Setup Summary ; +--------------------------------------------------------------------------------+ Clock : CLOCK_50 -Slack : -17.311 -End Point TNS : -526.609 +Slack : -17.572 +End Point TNS : -524.603 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Slack : -6.686 -End Point TNS : -253.661 +Slack : -6.192 +End Point TNS : -241.805 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Slack : -4.428 -End Point TNS : -40.009 +Slack : -4.414 +End Point TNS : -39.436 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] -Slack : -2.785 -End Point TNS : -2.785 +Slack : -2.786 +End Point TNS : -2.786 +--------------------------------------------------------------------------------+ @@ -10749,20 +10749,20 @@ End Point TNS : -2.785 +--------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Hold Summary ; +--------------------------------------------------------------------------------+ +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Slack : 0.297 +End Point TNS : 0.000 + Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Slack : 0.298 End Point TNS : 0.000 -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Slack : 0.300 +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Slack : 0.311 End Point TNS : 0.000 Clock : CLOCK_50 -Slack : 0.304 -End Point TNS : 0.000 - -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Slack : 0.311 +Slack : 0.467 End Point TNS : 0.000 +--------------------------------------------------------------------------------+ @@ -10772,8 +10772,8 @@ End Point TNS : 0.000 ; Slow 1200mV 0C Model Recovery Summary ; +--------------------------------------------------------------------------------+ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Slack : -5.744 -End Point TNS : -423.582 +Slack : -5.773 +End Point TNS : -427.930 +--------------------------------------------------------------------------------+ @@ -10782,7 +10782,7 @@ End Point TNS : -423.582 ; Slow 1200mV 0C Model Removal Summary ; +--------------------------------------------------------------------------------+ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Slack : 3.374 +Slack : 3.347 End Point TNS : 0.000 +--------------------------------------------------------------------------------+ @@ -10796,11 +10796,11 @@ Slack : 9.489 End Point TNS : 0.000 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Slack : 19.600 +Slack : 19.601 End Point TNS : 0.000 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Slack : 20.591 +Slack : 20.590 End Point TNS : 0.000 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] @@ -10813,905 +10813,905 @@ End Point TNS : 0.000 +--------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Setup: 'CLOCK_50' ; +--------------------------------------------------------------------------------+ -Slack : -17.311 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.273 -Data Delay : 7.112 - -Slack : -17.306 -From Node : ula:ula_|video:video_|vga_vc[3] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.273 -Data Delay : 7.107 - -Slack : -17.281 +Slack : -17.572 From Node : ula:ula_|video:video_|vga_hc[4] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.274 -Data Delay : 7.081 +Clock Skew : -0.279 +Data Delay : 7.367 -Slack : -17.275 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.274 -Data Delay : 7.075 - -Slack : -17.265 +Slack : -17.513 From Node : ula:ula_|video:video_|vga_vc[9] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.273 -Data Delay : 7.066 +Clock Skew : -0.279 +Data Delay : 7.308 -Slack : -17.249 -From Node : ula:ula_|video:video_|vga_vc[8] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.273 -Data Delay : 7.050 - -Slack : -17.244 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.274 -Data Delay : 7.044 - -Slack : -17.196 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4 -To Node : GPIO_1[20] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.515 -Data Delay : 6.755 - -Slack : -17.190 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.273 -Data Delay : 6.991 - -Slack : -17.182 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : GPIO_1[20] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.272 -Data Delay : 6.984 - -Slack : -17.176 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22 -To Node : GPIO_1[22] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.510 -Data Delay : 6.740 - -Slack : -17.176 -From Node : ula:ula_|video:video_|bits[5] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.277 -Data Delay : 6.973 - -Slack : -17.172 -From Node : ula:ula_|video:video_|vga_hc[1] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.277 -Data Delay : 6.969 - -Slack : -17.142 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : GPIO_1[22] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.272 -Data Delay : 6.944 - -Slack : -17.140 -From Node : ula:ula_|video:video_|vga_vc[6] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.273 -Data Delay : 6.941 - -Slack : -17.136 -From Node : ula:ula_|video:video_|vga_vc[4] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.273 -Data Delay : 6.937 - -Slack : -17.114 -From Node : ula:ula_|video:video_|vga_vc[7] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.273 -Data Delay : 6.915 - -Slack : -17.106 -From Node : ula:ula_|video:video_|vga_hc[5] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.274 -Data Delay : 6.906 - -Slack : -17.082 -From Node : ula:ula_|video:video_|vga_vc[0] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.273 -Data Delay : 6.883 - -Slack : -17.075 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6 -To Node : GPIO_1[22] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.518 -Data Delay : 6.631 - -Slack : -17.061 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : GPIO_1[22] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.272 -Data Delay : 6.863 - -Slack : -17.022 -From Node : ula:ula_|video:video_|vga_vc[5] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.273 -Data Delay : 6.823 - -Slack : -16.969 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1 -To Node : GPIO_1[17] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.524 -Data Delay : 6.519 - -Slack : -16.953 -From Node : ula:ula_|video:video_|vga_hc[9] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.277 -Data Delay : 6.750 - -Slack : -16.941 -From Node : ula:ula_|video:video_|bits[1] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.277 -Data Delay : 6.738 - -Slack : -16.939 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9 -To Node : GPIO_1[17] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.524 -Data Delay : 6.489 - -Slack : -16.921 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : GPIO_1[19] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.272 -Data Delay : 6.723 - -Slack : -16.917 -From Node : ula:ula_|video:video_|vga_hc[8] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.274 -Data Delay : 6.717 - -Slack : -16.916 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8 -To Node : GPIO_1[16] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.515 -Data Delay : 6.475 - -Slack : -16.906 -From Node : ula:ula_|video:video_|vga_hc[7] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.274 -Data Delay : 6.706 - -Slack : -16.904 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20 -To Node : GPIO_1[20] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.516 -Data Delay : 6.462 - -Slack : -16.894 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12 -To Node : GPIO_1[20] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.504 -Data Delay : 6.464 - -Slack : -16.865 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28 -To Node : GPIO_1[20] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.516 -Data Delay : 6.423 - -Slack : -16.857 -From Node : ula:ula_|video:video_|bits[6] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.277 -Data Delay : 6.654 - -Slack : -16.852 -From Node : ula:ula_|video:video_|frame[4] +Slack : -17.443 +From Node : ula:ula_|video:video_|vga_hc[6] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 Clock Skew : -0.279 -Data Delay : 6.647 +Data Delay : 7.238 -Slack : -16.821 -From Node : ula:ula_|video:video_|bits[7] +Slack : -17.346 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.279 +Data Delay : 7.141 + +Slack : -17.323 +From Node : ula:ula_|video:video_|vga_vc[3] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 Clock Skew : -0.277 -Data Delay : 6.618 +Data Delay : 7.120 -Slack : -16.820 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30 -To Node : GPIO_1[22] +Slack : -17.318 +From Node : ula:ula_|video:video_|vga_vc[2] +To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.518 -Data Delay : 6.376 +Clock Skew : -0.277 +Data Delay : 7.115 -Slack : -16.761 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14 -To Node : GPIO_1[22] +Slack : -17.290 +From Node : ula:ula_|video:video_|vga_hc[7] +To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.521 -Data Delay : 6.314 +Clock Skew : -0.279 +Data Delay : 7.085 -Slack : -16.737 +Slack : -17.219 +From Node : ula:ula_|video:video_|vga_hc[1] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.279 +Data Delay : 7.014 + +Slack : -17.194 +From Node : ula:ula_|video:video_|vga_hc[5] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.279 +Data Delay : 6.989 + +Slack : -17.188 +From Node : ula:ula_|video:video_|vga_vc[6] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.279 +Data Delay : 6.983 + +Slack : -17.164 +From Node : ula:ula_|video:video_|vga_vc[8] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.277 +Data Delay : 6.961 + +Slack : -17.151 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] To Node : GPIO_1[21] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.272 -Data Delay : 6.539 +Clock Skew : -0.257 +Data Delay : 6.968 -Slack : -16.733 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : GPIO_1[21] +Slack : -17.144 +From Node : ula:ula_|video:video_|vga_hc[9] +To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.272 -Data Delay : 6.535 +Clock Skew : -0.279 +Data Delay : 6.939 -Slack : -16.727 -From Node : ula:ula_|video:video_|bits[2] +Slack : -17.121 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : GPIO_1[22] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.257 +Data Delay : 6.938 + +Slack : -17.094 +From Node : ula:ula_|video:video_|vga_vc[1] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 Clock Skew : -0.277 -Data Delay : 6.524 +Data Delay : 6.891 -Slack : -16.721 +Slack : -17.077 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0 To Node : GPIO_1[16] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.523 -Data Delay : 6.272 +Clock Skew : -0.516 +Data Delay : 6.635 -Slack : -16.719 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27 +Slack : -17.068 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 To Node : GPIO_1[19] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 +Clock Skew : -0.527 +Data Delay : 6.615 + +Slack : -17.059 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : GPIO_1[16] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.257 +Data Delay : 6.876 + +Slack : -17.058 +From Node : ula:ula_|video:video_|vga_vc[4] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.279 +Data Delay : 6.853 + +Slack : -17.038 +From Node : ula:ula_|video:video_|vga_vc[7] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.279 +Data Delay : 6.833 + +Slack : -17.032 +From Node : ula:ula_|video:video_|vga_hc[8] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.279 +Data Delay : 6.827 + +Slack : -17.031 +From Node : ula:ula_|video:video_|bits[5] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.276 +Data Delay : 6.829 + +Slack : -17.025 +From Node : ula:ula_|video:video_|vga_vc[5] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.279 +Data Delay : 6.820 + +Slack : -17.016 +From Node : ula:ula_|video:video_|vga_vc[0] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.277 +Data Delay : 6.813 + +Slack : -16.986 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14 +To Node : GPIO_1[22] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 Clock Skew : -0.513 -Data Delay : 6.280 +Data Delay : 6.547 -Slack : -16.716 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11 -To Node : GPIO_1[19] +Slack : -16.986 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : GPIO_1[16] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.264 +Data Delay : 6.796 + +Slack : -16.978 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : GPIO_1[22] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.264 +Data Delay : 6.788 + +Slack : -16.939 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : GPIO_1[21] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.264 +Data Delay : 6.749 + +Slack : -16.938 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 +To Node : GPIO_1[16] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.526 +Data Delay : 6.486 + +Slack : -16.917 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : GPIO_1[23] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.264 +Data Delay : 6.727 + +Slack : -16.907 +From Node : ula:ula_|video:video_|bits[6] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.276 +Data Delay : 6.705 + +Slack : -16.884 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 +To Node : GPIO_1[22] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.514 +Data Delay : 6.444 + +Slack : -16.883 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8 +To Node : GPIO_1[16] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 Clock Skew : -0.516 -Data Delay : 6.274 +Data Delay : 6.441 -Slack : -16.702 -From Node : ula:ula_|video:video_|bits[3] +Slack : -16.837 +From Node : ula:ula_|video:video_|bits[1] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.277 -Data Delay : 6.499 +Clock Skew : -0.276 +Data Delay : 6.635 -Slack : -16.700 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : GPIO_1[17] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.272 -Data Delay : 6.502 - -Slack : -16.698 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : GPIO_1[17] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.272 -Data Delay : 6.500 - -Slack : -16.679 -From Node : ula:ula_|video:video_|attr[7] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.277 -Data Delay : 6.476 - -Slack : -16.665 +Slack : -16.830 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16 To Node : GPIO_1[16] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.524 -Data Delay : 6.215 +Clock Skew : -0.516 +Data Delay : 6.388 -Slack : -16.650 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5 -To Node : GPIO_1[21] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.508 -Data Delay : 6.216 - -Slack : -16.637 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25 -To Node : GPIO_1[17] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.523 -Data Delay : 6.188 - -Slack : -16.629 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +Slack : -16.809 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 To Node : GPIO_1[16] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.272 -Data Delay : 6.431 +Clock Skew : -0.523 +Data Delay : 6.360 -Slack : -16.615 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17 -To Node : GPIO_1[17] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.524 -Data Delay : 6.165 - -Slack : -16.606 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19 -To Node : GPIO_1[19] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.513 -Data Delay : 6.167 - -Slack : -16.595 +Slack : -16.791 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : GPIO_1[18] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.272 -Data Delay : 6.397 - -Slack : -16.582 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2 -To Node : GPIO_1[18] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.514 -Data Delay : 6.142 - -Slack : -16.567 -From Node : ula:ula_|video:video_|vga_hc[3] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.277 -Data Delay : 6.364 - -Slack : -16.565 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3 To Node : GPIO_1[19] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.516 -Data Delay : 6.123 +Clock Skew : -0.257 +Data Delay : 6.608 -Slack : -16.554 +Slack : -16.787 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6 +To Node : GPIO_1[22] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.510 +Data Delay : 6.351 + +Slack : -16.775 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 +To Node : GPIO_1[19] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.515 +Data Delay : 6.334 + +Slack : -16.772 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24 To Node : GPIO_1[16] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.524 -Data Delay : 6.104 +Clock Skew : -0.516 +Data Delay : 6.330 -Slack : -16.544 -From Node : ula:ula_|video:video_|bits[4] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.277 -Data Delay : 6.341 - -Slack : -16.541 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10 -To Node : GPIO_1[18] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.522 -Data Delay : 6.093 - -Slack : -16.539 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : GPIO_1[19] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.272 -Data Delay : 6.341 - -Slack : -16.529 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13 -To Node : GPIO_1[21] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.508 -Data Delay : 6.095 - -Slack : -16.512 +Slack : -16.771 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] To Node : GPIO_1[23] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.272 -Data Delay : 6.314 +Clock Skew : -0.257 +Data Delay : 6.588 -Slack : -16.511 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : GPIO_1[16] +Slack : -16.767 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2 +To Node : GPIO_1[18] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.272 -Data Delay : 6.313 +Clock Skew : -0.508 +Data Delay : 6.333 -Slack : -16.483 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18 +Slack : -16.765 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] To Node : GPIO_1[18] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 +Clock Skew : -0.257 +Data Delay : 6.582 + +Slack : -16.748 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 +To Node : GPIO_1[22] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 Clock Skew : -0.516 -Data Delay : 6.041 +Data Delay : 6.306 -Slack : -16.443 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29 +Slack : -16.748 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30 +To Node : GPIO_1[22] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.504 +Data Delay : 6.318 + +Slack : -16.744 +From Node : ula:ula_|video:video_|vga_hc[4] +To Node : VGA_R[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.279 +Data Delay : 6.539 + +Slack : -16.743 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : GPIO_1[17] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.257 +Data Delay : 6.560 + +Slack : -16.740 +From Node : ula:ula_|video:video_|bits[2] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.276 +Data Delay : 6.538 + +Slack : -16.721 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10 +To Node : GPIO_1[18] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.514 +Data Delay : 6.281 + +Slack : -16.720 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22 +To Node : GPIO_1[22] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.508 +Data Delay : 6.286 + +Slack : -16.717 +From Node : ula:ula_|video:video_|bits[7] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.276 +Data Delay : 6.515 + +Slack : -16.715 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : GPIO_1[17] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.264 +Data Delay : 6.525 + +Slack : -16.705 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21 To Node : GPIO_1[21] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.517 -Data Delay : 6.000 +Clock Skew : -0.524 +Data Delay : 6.255 -Slack : -16.425 +Slack : -16.699 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] To Node : GPIO_1[18] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.272 -Data Delay : 6.227 +Clock Skew : -0.264 +Data Delay : 6.509 -Slack : -16.422 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26 -To Node : GPIO_1[18] +Slack : -16.694 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : GPIO_1[20] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.512 -Data Delay : 5.984 +Clock Skew : -0.257 +Data Delay : 6.511 -Slack : -16.415 -From Node : ula:ula_|video:video_|bits[0] +Slack : -16.666 +From Node : ula:ula_|video:video_|vga_hc[3] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.277 -Data Delay : 6.212 +Clock Skew : -0.279 +Data Delay : 6.461 -Slack : -16.393 +Slack : -16.665 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2 +To Node : GPIO_1[18] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.523 +Data Delay : 6.216 + +Slack : -16.664 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 +To Node : GPIO_1[18] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.515 +Data Delay : 6.223 + +Slack : -16.661 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19 +To Node : GPIO_1[19] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.515 +Data Delay : 6.220 + +Slack : -16.659 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17 +To Node : GPIO_1[17] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.512 +Data Delay : 6.221 + +Slack : -16.648 +From Node : ula:ula_|video:video_|frame[4] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.276 +Data Delay : 6.446 + +Slack : -16.644 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 +To Node : GPIO_1[21] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.534 +Data Delay : 6.184 + +Slack : -16.640 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13 +To Node : GPIO_1[21] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.524 +Data Delay : 6.190 + +Slack : -16.637 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7 To Node : GPIO_1[23] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 Clock Skew : -0.522 -Data Delay : 5.945 +Data Delay : 6.189 -Slack : -16.347 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21 -To Node : GPIO_1[21] +Slack : -16.636 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27 +To Node : GPIO_1[19] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.510 -Data Delay : 5.911 +Clock Skew : -0.524 +Data Delay : 6.186 -Slack : -16.212 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31 -To Node : GPIO_1[23] +Slack : -16.626 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3 +To Node : GPIO_1[19] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.514 -Data Delay : 5.772 +Clock Skew : -0.516 +Data Delay : 6.184 -Slack : -16.157 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : VGA_B[3] +Slack : -16.615 +From Node : ula:ula_|video:video_|vga_hc[6] +To Node : VGA_R[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.273 -Data Delay : 5.958 +Clock Skew : -0.279 +Data Delay : 6.410 -Slack : -16.155 +Slack : -16.604 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26 +To Node : GPIO_1[18] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.513 +Data Delay : 6.165 + +Slack : -16.601 +From Node : ula:ula_|video:video_|bits[3] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.276 +Data Delay : 6.399 + +Slack : -16.599 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23 To Node : GPIO_1[23] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.521 -Data Delay : 5.708 +Clock Skew : -0.523 +Data Delay : 6.150 -Slack : -16.152 -From Node : ula:ula_|video:video_|vga_vc[3] -To Node : VGA_B[3] +Slack : -16.590 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29 +To Node : GPIO_1[21] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.273 -Data Delay : 5.953 +Clock Skew : -0.524 +Data Delay : 6.140 -Slack : -16.143 -From Node : ula:ula_|video:video_|attr[0] +Slack : -16.588 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18 +To Node : GPIO_1[18] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.510 +Data Delay : 6.152 + +Slack : -16.584 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5 +To Node : GPIO_1[21] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.520 +Data Delay : 6.138 + +Slack : -16.582 +From Node : ula:ula_|video:video_|attr[7] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 +Clock Skew : -0.276 +Data Delay : 6.380 + +Slack : -16.563 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 +To Node : GPIO_1[21] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.524 +Data Delay : 6.113 + +Slack : -16.543 +From Node : ula:ula_|video:video_|vga_vc[9] +To Node : VGA_R[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.279 +Data Delay : 6.338 + +Slack : -16.533 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 +To Node : GPIO_1[17] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.516 +Data Delay : 6.091 + +Slack : -16.527 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1 +To Node : GPIO_1[17] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.518 +Data Delay : 6.083 + +Slack : -16.522 +From Node : ula:ula_|video:video_|vga_vc[3] +To Node : VGA_R[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 Clock Skew : -0.277 -Data Delay : 5.940 +Data Delay : 6.319 -Slack : -16.127 -From Node : ula:ula_|video:video_|vga_hc[4] -To Node : VGA_B[3] +Slack : -16.517 +From Node : ula:ula_|video:video_|vga_vc[2] +To Node : VGA_R[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.274 -Data Delay : 5.927 +Clock Skew : -0.277 +Data Delay : 6.314 -Slack : -16.121 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : VGA_B[3] +Slack : -16.498 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9 +To Node : GPIO_1[17] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.274 -Data Delay : 5.921 +Clock Skew : -0.522 +Data Delay : 6.050 -Slack : -16.113 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +Slack : -16.497 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 To Node : GPIO_1[23] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.272 -Data Delay : 5.915 +Clock Skew : -0.531 +Data Delay : 6.040 -Slack : -16.111 -From Node : ula:ula_|video:video_|vga_vc[9] -To Node : VGA_B[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.273 -Data Delay : 5.912 - -Slack : -16.095 -From Node : ula:ula_|video:video_|vga_vc[8] -To Node : VGA_B[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.273 -Data Delay : 5.896 - -Slack : -16.090 +Slack : -16.495 From Node : ula:ula_|video:video_|vga_hc[2] -To Node : VGA_B[3] +To Node : VGA_R[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.274 -Data Delay : 5.890 +Clock Skew : -0.279 +Data Delay : 6.290 -Slack : -16.052 +Slack : -16.462 +From Node : ula:ula_|video:video_|vga_hc[7] +To Node : VGA_R[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.279 +Data Delay : 6.257 + +Slack : -16.446 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12 +To Node : GPIO_1[20] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.521 +Data Delay : 5.999 + +Slack : -16.443 +From Node : ula:ula_|video:video_|bits[4] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.276 +Data Delay : 6.241 + +Slack : -16.432 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31 +To Node : GPIO_1[23] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.524 +Data Delay : 5.982 + +Slack : -16.421 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 +To Node : GPIO_1[20] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.522 +Data Delay : 5.973 + +Slack : -16.413 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15 To Node : GPIO_1[23] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.516 -Data Delay : 5.610 +Clock Skew : -0.524 +Data Delay : 5.963 -Slack : -16.036 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : VGA_B[3] +Slack : -16.401 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 +To Node : GPIO_1[17] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.273 -Data Delay : 5.837 +Clock Skew : -0.524 +Data Delay : 5.951 -Slack : -16.022 -From Node : ula:ula_|video:video_|bits[5] -To Node : VGA_B[3] +Slack : -16.389 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : GPIO_1[20] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.277 -Data Delay : 5.819 +Clock Skew : -0.264 +Data Delay : 6.199 -Slack : -16.018 +Slack : -16.371 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 +To Node : GPIO_1[20] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.523 +Data Delay : 5.922 + +Slack : -16.368 From Node : ula:ula_|video:video_|vga_hc[1] -To Node : VGA_B[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.277 -Data Delay : 5.815 - -Slack : -15.986 -From Node : ula:ula_|video:video_|vga_vc[6] -To Node : VGA_B[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.273 -Data Delay : 5.787 - -Slack : -15.982 -From Node : ula:ula_|video:video_|vga_vc[4] -To Node : VGA_B[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.273 -Data Delay : 5.783 - -Slack : -15.961 -From Node : ula:ula_|video:video_|vga_vc[2] To Node : VGA_R[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.273 -Data Delay : 5.762 +Clock Skew : -0.279 +Data Delay : 6.163 -Slack : -15.960 -From Node : ula:ula_|video:video_|vga_vc[7] -To Node : VGA_B[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.273 -Data Delay : 5.761 - -Slack : -15.956 -From Node : ula:ula_|video:video_|vga_vc[3] -To Node : VGA_R[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.273 -Data Delay : 5.757 - -Slack : -15.952 +Slack : -16.366 From Node : ula:ula_|video:video_|vga_hc[5] -To Node : VGA_B[3] +To Node : VGA_R[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.274 -Data Delay : 5.752 +Clock Skew : -0.279 +Data Delay : 6.161 -Slack : -15.931 -From Node : ula:ula_|video:video_|vga_hc[4] -To Node : VGA_R[0] +Slack : -16.342 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25 +To Node : GPIO_1[17] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.274 -Data Delay : 5.731 +Clock Skew : -0.516 +Data Delay : 5.900 -Slack : -15.928 -From Node : ula:ula_|video:video_|vga_vc[0] -To Node : VGA_B[3] +Slack : -16.330 +From Node : ula:ula_|video:video_|vga_hc[9] +To Node : VGA_R[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.273 -Data Delay : 5.729 +Clock Skew : -0.279 +Data Delay : 6.125 -Slack : -15.925 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : VGA_R[0] +Slack : -16.316 +From Node : ula:ula_|video:video_|bits[0] +To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.274 -Data Delay : 5.725 +Clock Skew : -0.276 +Data Delay : 6.114 -Slack : -15.918 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : VGA_G[0] +Slack : -16.311 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 +To Node : GPIO_1[23] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.274 -Data Delay : 5.718 +Clock Skew : -0.535 +Data Delay : 5.850 -Slack : -15.915 -From Node : ula:ula_|video:video_|vga_vc[9] -To Node : VGA_R[0] +Slack : -16.310 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4 +To Node : GPIO_1[20] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.273 -Data Delay : 5.716 +Clock Skew : -0.516 +Data Delay : 5.868 -Slack : -15.899 -From Node : ula:ula_|video:video_|vga_vc[8] -To Node : VGA_R[0] +Slack : -16.309 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11 +To Node : GPIO_1[19] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.273 -Data Delay : 5.700 - -Slack : -15.868 -From Node : ula:ula_|video:video_|vga_vc[5] -To Node : VGA_B[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.273 -Data Delay : 5.669 +Clock Skew : -0.516 +Data Delay : 5.867 +--------------------------------------------------------------------------------+ @@ -11719,905 +11719,905 @@ Data Delay : 5.669 +--------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' ; +--------------------------------------------------------------------------------+ -Slack : -6.686 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.012 -Data Delay : 4.774 - -Slack : -6.590 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.004 -Data Delay : 4.686 - -Slack : -6.554 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.010 -Data Delay : 4.644 - -Slack : -6.499 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.983 -Data Delay : 4.616 - -Slack : -6.497 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.004 -Data Delay : 4.593 - -Slack : -6.479 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.027 -Data Delay : 4.552 - -Slack : -6.476 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.003 -Data Delay : 4.573 - -Slack : -6.457 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.019 -Data Delay : 4.538 - -Slack : -6.451 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.965 -Data Delay : 4.586 - -Slack : -6.417 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.971 -Data Delay : 4.546 - -Slack : -6.411 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.003 -Data Delay : 4.508 - -Slack : -6.338 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.963 -Data Delay : 4.475 - -Slack : -6.321 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.963 -Data Delay : 4.458 - -Slack : -6.320 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.003 -Data Delay : 4.417 - -Slack : -6.306 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.021 -Data Delay : 4.385 - -Slack : -6.299 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.964 -Data Delay : 4.435 - -Slack : -6.296 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.985 -Data Delay : 4.411 - -Slack : -6.294 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.006 -Data Delay : 4.388 - -Slack : -6.293 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.016 -Data Delay : 4.377 - -Slack : -6.292 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.978 -Data Delay : 4.414 - -Slack : -6.291 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.981 -Data Delay : 4.410 - -Slack : -6.289 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.002 -Data Delay : 4.387 - -Slack : -6.278 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.019 -Data Delay : 4.359 - -Slack : -6.270 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.970 -Data Delay : 4.400 - -Slack : -6.264 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.013 -Data Delay : 4.351 - -Slack : -6.253 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.005 -Data Delay : 4.348 - -Slack : -6.237 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.016 -Data Delay : 4.321 - -Slack : -6.215 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.008 -Data Delay : 4.307 - -Slack : -6.207 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.962 -Data Delay : 4.345 - -Slack : -6.203 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.976 -Data Delay : 4.327 - -Slack : -6.198 +Slack : -6.192 From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.759 -Data Delay : 4.539 - -Slack : -6.179 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.004 -Data Delay : 4.275 - -Slack : -6.173 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.987 -Data Delay : 4.286 - -Slack : -6.161 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.996 -Data Delay : 4.265 - -Slack : -6.145 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.997 -Data Delay : 4.248 - -Slack : -6.145 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.003 -Data Delay : 4.242 - -Slack : -6.142 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.962 -Data Delay : 4.280 - -Slack : -6.128 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.981 -Data Delay : 4.247 - -Slack : -6.124 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.963 -Data Delay : 4.261 - -Slack : -6.106 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.967 -Data Delay : 4.239 - -Slack : -6.102 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.751 -Data Delay : 4.451 - -Slack : -6.091 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.009 -Data Delay : 4.182 - -Slack : -6.091 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.989 -Data Delay : 4.202 +Clock Skew : -1.735 +Data Delay : 4.557 -Slack : -6.091 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.970 -Data Delay : 4.221 - -Slack : -6.072 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.014 -Data Delay : 4.158 - -Slack : -6.065 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.988 -Data Delay : 4.177 - -Slack : -6.064 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.975 -Data Delay : 4.189 - -Slack : -6.063 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.960 -Data Delay : 4.203 - -Slack : -6.062 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.996 -Data Delay : 4.166 - -Slack : -6.055 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.989 -Data Delay : 4.166 - -Slack : -6.051 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.975 -Data Delay : 4.176 - -Slack : -6.051 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.005 -Data Delay : 4.146 - -Slack : -6.040 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.962 -Data Delay : 4.178 - -Slack : -6.039 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.005 -Data Delay : 4.134 - -Slack : -6.036 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.008 -Data Delay : 4.128 - -Slack : -6.026 +Slack : -6.015 From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.973 -Data Delay : 4.153 +Clock Skew : -1.972 +Data Delay : 4.143 -Slack : -6.022 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 +Slack : -5.957 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.954 -Data Delay : 4.168 +Clock Skew : -1.972 +Data Delay : 4.085 -Slack : -6.019 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.977 -Data Delay : 4.142 - -Slack : -6.009 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.750 -Data Delay : 4.359 - -Slack : -6.006 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 +Slack : -5.943 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 Clock Skew : -1.955 -Data Delay : 4.151 +Data Delay : 4.088 -Slack : -6.004 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.014 -Data Delay : 4.090 - -Slack : -6.004 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.002 -Data Delay : 4.102 - -Slack : -6.004 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.761 -Data Delay : 4.343 - -Slack : -6.001 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.969 -Data Delay : 4.132 - -Slack : -6.000 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.008 -Data Delay : 4.092 - -Slack : -5.988 +Slack : -5.937 From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.964 -Data Delay : 4.124 +Clock Skew : -1.958 +Data Delay : 4.079 -Slack : -5.988 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 +Slack : -5.935 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.750 -Data Delay : 4.338 +Clock Skew : -1.972 +Data Delay : 4.063 -Slack : -5.985 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 +Slack : -5.922 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.970 -Data Delay : 4.115 +Clock Skew : -1.955 +Data Delay : 4.067 -Slack : -5.983 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0 +Slack : -5.900 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -2.013 -Data Delay : 4.070 +Clock Skew : -1.975 +Data Delay : 4.025 -Slack : -5.978 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0 +Slack : -5.889 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -2.002 -Data Delay : 4.076 +Clock Skew : -1.972 +Data Delay : 4.017 -Slack : -5.973 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.021 -Data Delay : 4.052 - -Slack : -5.972 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 +Slack : -5.875 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -2.014 -Data Delay : 4.058 +Clock Skew : -1.979 +Data Delay : 3.996 -Slack : -5.970 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 +Slack : -5.849 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.989 -Data Delay : 4.081 +Clock Skew : -1.735 +Data Delay : 4.214 -Slack : -5.965 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0 +Slack : -5.842 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.985 -Data Delay : 4.080 +Clock Skew : -1.979 +Data Delay : 3.963 -Slack : -5.963 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 +Slack : -5.841 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.736 +Data Delay : 4.205 + +Slack : -5.838 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.969 +Data Delay : 3.969 + +Slack : -5.822 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.735 +Data Delay : 4.187 + +Slack : -5.821 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -2.016 -Data Delay : 4.047 +Clock Skew : -1.973 +Data Delay : 3.948 -Slack : -5.955 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 +Slack : -5.816 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -2.013 -Data Delay : 4.042 +Clock Skew : -1.967 +Data Delay : 3.949 -Slack : -5.952 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 +Slack : -5.816 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.960 -Data Delay : 4.092 +Clock Skew : -1.965 +Data Delay : 3.951 -Slack : -5.950 +Slack : -5.804 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.973 +Data Delay : 3.931 + +Slack : -5.798 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.976 +Data Delay : 3.922 + +Slack : -5.796 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.739 +Data Delay : 4.157 + +Slack : -5.795 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.963 +Data Delay : 3.932 + +Slack : -5.790 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.984 +Data Delay : 3.906 + +Slack : -5.783 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.973 +Data Delay : 3.910 + +Slack : -5.769 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.974 +Data Delay : 3.895 + +Slack : -5.765 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.988 +Data Delay : 3.877 + +Slack : -5.758 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.965 +Data Delay : 3.893 + +Slack : -5.748 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.970 +Data Delay : 3.878 + +Slack : -5.741 From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.980 -Data Delay : 4.070 +Clock Skew : -1.968 +Data Delay : 3.873 -Slack : -5.939 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.014 -Data Delay : 4.025 - -Slack : -5.937 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.015 -Data Delay : 4.022 - -Slack : -5.933 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.759 -Data Delay : 4.274 - -Slack : -5.931 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.003 -Data Delay : 4.028 - -Slack : -5.930 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.965 -Data Delay : 4.065 - -Slack : -5.927 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.016 -Data Delay : 4.011 - -Slack : -5.923 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.750 -Data Delay : 4.273 - -Slack : -5.908 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.994 -Data Delay : 4.014 - -Slack : -5.896 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.984 -Data Delay : 4.012 - -Slack : -5.887 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.002 -Data Delay : 3.985 - -Slack : -5.884 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.000 -Data Delay : 3.984 - -Slack : -5.884 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.012 -Data Delay : 3.972 - -Slack : -5.877 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.966 -Data Delay : 4.011 - -Slack : -5.874 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.976 -Data Delay : 3.998 - -Slack : -5.870 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.000 -Data Delay : 3.970 - -Slack : -5.857 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -2.002 -Data Delay : 3.955 - -Slack : -5.836 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.963 -Data Delay : 3.973 - -Slack : -5.826 -From Node : raw_loader_in -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : 0.180 -Data Delay : 4.106 - -Slack : -5.816 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.964 -Data Delay : 3.952 - -Slack : -5.814 +Slack : -5.738 From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.974 -Data Delay : 3.940 +Clock Skew : -1.964 +Data Delay : 3.874 -Slack : -5.804 +Slack : -5.736 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.965 +Data Delay : 3.871 + +Slack : -5.728 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.978 +Data Delay : 3.850 + +Slack : -5.727 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.976 +Data Delay : 3.851 + +Slack : -5.724 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.973 +Data Delay : 3.851 + +Slack : -5.717 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.960 +Data Delay : 3.857 + +Slack : -5.704 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.972 +Data Delay : 3.832 + +Slack : -5.694 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.976 +Data Delay : 3.818 + +Slack : -5.694 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.972 +Data Delay : 3.822 + +Slack : -5.671 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.977 +Data Delay : 3.794 + +Slack : -5.655 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.755 +Data Delay : 4.000 + +Slack : -5.650 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.973 +Data Delay : 3.777 + +Slack : -5.603 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.955 +Data Delay : 3.748 + +Slack : -5.587 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.966 +Data Delay : 3.721 + +Slack : -5.582 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.750 +Data Delay : 3.932 + +Slack : -5.580 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.743 +Data Delay : 3.937 + +Slack : -5.578 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.978 +Data Delay : 3.700 + +Slack : -5.572 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.960 +Data Delay : 3.712 + +Slack : -5.557 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.735 +Data Delay : 3.922 + +Slack : -5.556 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.963 +Data Delay : 3.693 + +Slack : -5.556 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.970 +Data Delay : 3.686 + +Slack : -5.553 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.967 +Data Delay : 3.686 + +Slack : -5.553 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.746 +Data Delay : 3.907 + +Slack : -5.543 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.736 +Data Delay : 3.907 + +Slack : -5.540 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.973 +Data Delay : 3.667 + +Slack : -5.540 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.982 +Data Delay : 3.658 + +Slack : -5.533 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.964 +Data Delay : 3.669 + +Slack : -5.533 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.966 +Data Delay : 3.667 + +Slack : -5.522 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.743 +Data Delay : 3.879 + +Slack : -5.500 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.743 +Data Delay : 3.857 + +Slack : -5.495 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.965 +Data Delay : 3.630 + +Slack : -5.487 From Node : raw_loader_in To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : 0.188 -Data Delay : 4.092 +Clock Skew : 0.174 +Data Delay : 3.761 -Slack : -5.794 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 +Slack : -5.478 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.993 -Data Delay : 3.901 +Clock Skew : -1.960 +Data Delay : 3.618 + +Slack : -5.478 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.973 +Data Delay : 3.605 + +Slack : -5.470 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.974 +Data Delay : 3.596 + +Slack : -5.467 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.977 +Data Delay : 3.590 + +Slack : -5.446 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.743 +Data Delay : 3.803 + +Slack : -5.438 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.738 +Data Delay : 3.800 + +Slack : -5.432 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.741 +Data Delay : 3.791 + +Slack : -5.428 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.976 +Data Delay : 3.552 + +Slack : -5.425 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.977 +Data Delay : 3.548 + +Slack : -5.421 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.747 +Data Delay : 3.774 + +Slack : -5.417 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.738 +Data Delay : 3.779 + +Slack : -5.414 +From Node : raw_loader_in +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : 0.179 +Data Delay : 3.693 + +Slack : -5.395 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.964 +Data Delay : 3.531 + +Slack : -5.387 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.965 +Data Delay : 3.522 + +Slack : -5.384 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.737 +Data Delay : 3.747 + +Slack : -5.384 +From Node : raw_loader_in +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : 0.183 +Data Delay : 3.667 + +Slack : -5.353 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.749 +Data Delay : 3.704 + +Slack : -5.342 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.968 +Data Delay : 3.474 + +Slack : -5.307 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.960 +Data Delay : 3.447 + +Slack : -5.296 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.971 +Data Delay : 3.425 + +Slack : -5.294 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.737 +Data Delay : 3.657 + +Slack : -5.293 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.961 +Data Delay : 3.432 + +Slack : -5.290 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.963 +Data Delay : 3.427 + +Slack : -5.259 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.743 +Data Delay : 3.616 + +Slack : -5.213 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.960 +Data Delay : 3.353 + +Slack : -5.212 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.743 +Data Delay : 3.569 + +Slack : -5.199 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.961 +Data Delay : 3.338 + +Slack : -5.196 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.741 +Data Delay : 3.555 + +Slack : -5.185 +From Node : raw_loader_in +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : 0.180 +Data Delay : 3.465 + +Slack : -5.110 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.735 +Data Delay : 3.475 + +Slack : -5.091 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.749 +Data Delay : 3.442 + +Slack : -5.088 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.746 +Data Delay : 3.442 + +Slack : -5.068 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.745 +Data Delay : 3.423 + +Slack : -5.063 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.743 +Data Delay : 3.420 + +Slack : -5.044 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.962 +Data Delay : 3.182 + +Slack : -5.040 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.744 +Data Delay : 3.396 + +Slack : -4.950 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.962 +Data Delay : 3.088 + +Slack : -4.831 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.750 +Data Delay : 3.181 + +Slack : -4.797 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.743 +Data Delay : 3.154 +--------------------------------------------------------------------------------+ @@ -12625,905 +12625,905 @@ Data Delay : 3.901 +--------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ; +--------------------------------------------------------------------------------+ -Slack : -4.428 +Slack : -4.414 From Node : I2C_SDAT To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.115 -Data Delay : 2.602 +Data Delay : 2.588 -Slack : -4.267 +Slack : -4.409 From Node : I2C_SDAT To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.087 -Data Delay : 2.559 +Data Delay : 2.701 -Slack : -4.267 +Slack : -4.409 From Node : I2C_SDAT To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.087 -Data Delay : 2.559 +Data Delay : 2.701 -Slack : -4.074 +Slack : -3.844 From Node : I2C_SDAT To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.087 -Data Delay : 2.366 +Clock Skew : 0.229 +Data Delay : 2.452 -Slack : -4.074 +Slack : -3.844 From Node : I2C_SDAT To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.087 -Data Delay : 2.366 +Clock Skew : 0.229 +Data Delay : 2.452 -Slack : -4.074 +Slack : -3.844 From Node : I2C_SDAT To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.087 -Data Delay : 2.366 +Clock Skew : 0.229 +Data Delay : 2.452 -Slack : -4.074 +Slack : -3.844 From Node : I2C_SDAT To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.087 -Data Delay : 2.366 +Clock Skew : 0.229 +Data Delay : 2.452 -Slack : -4.074 +Slack : -3.844 From Node : I2C_SDAT To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.087 -Data Delay : 2.366 +Clock Skew : 0.229 +Data Delay : 2.452 -Slack : -3.711 +Slack : -3.696 From Node : I2C_SDAT To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.087 -Data Delay : 2.003 +Data Delay : 1.988 -Slack : -2.966 +Slack : -3.288 From Node : AUD_ADCDAT To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.208 -Data Delay : 1.553 +Clock Skew : -0.084 +Data Delay : 1.583 -Slack : 17.237 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 3.241 - -Slack : 17.242 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 3.236 - -Slack : 17.361 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 3.117 - -Slack : 17.361 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 3.117 - -Slack : 17.362 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 3.116 - -Slack : 17.366 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 3.112 - -Slack : 17.366 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 3.112 - -Slack : 17.421 +Slack : 17.369 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 3.057 +Clock Skew : -0.369 +Data Delay : 3.108 -Slack : 17.421 +Slack : 17.369 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 3.108 + +Slack : 17.369 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 3.057 +Clock Skew : -0.369 +Data Delay : 3.108 -Slack : 17.421 +Slack : 17.369 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 3.057 +Clock Skew : -0.369 +Data Delay : 3.108 -Slack : 17.421 +Slack : 17.369 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 3.057 +Clock Skew : -0.369 +Data Delay : 3.108 -Slack : 17.426 +Slack : 17.371 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 3.052 +Clock Skew : -0.369 +Data Delay : 3.106 -Slack : 17.426 +Slack : 17.371 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 3.106 + +Slack : 17.371 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 3.052 +Clock Skew : -0.369 +Data Delay : 3.106 -Slack : 17.426 +Slack : 17.371 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 3.052 +Clock Skew : -0.369 +Data Delay : 3.106 -Slack : 17.426 +Slack : 17.371 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 3.052 +Clock Skew : -0.369 +Data Delay : 3.106 -Slack : 17.453 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 3.025 - -Slack : 17.488 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +Slack : 17.457 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.990 +Clock Skew : -0.369 +Data Delay : 3.020 -Slack : 17.488 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +Slack : 17.457 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.990 +Clock Skew : -0.369 +Data Delay : 3.020 -Slack : 17.495 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Slack : 17.459 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.368 +Clock Skew : -0.369 +Data Delay : 3.018 + +Slack : 17.459 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 3.018 + +Slack : 17.494 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 Data Delay : 2.983 -Slack : 17.495 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.983 - -Slack : 17.500 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.978 - -Slack : 17.500 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.978 - -Slack : 17.528 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 2.949 - -Slack : 17.528 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 2.949 - -Slack : 17.533 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 2.944 - -Slack : 17.533 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 2.944 - -Slack : 17.548 +Slack : 17.494 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.930 - -Slack : 17.548 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.930 - -Slack : 17.548 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.930 - -Slack : 17.548 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.930 - -Slack : 17.577 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.901 - -Slack : 17.577 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.901 - -Slack : 17.604 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.874 - -Slack : 17.604 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.874 - -Slack : 17.604 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.874 - -Slack : 17.604 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.874 - -Slack : 17.604 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.874 - -Slack : 17.609 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.869 - -Slack : 17.609 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.869 - -Slack : 17.609 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.869 - -Slack : 17.609 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.869 - -Slack : 17.609 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.869 - -Slack : 17.618 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.860 +Clock Skew : -0.369 +Data Delay : 2.983 -Slack : 17.622 +Slack : 17.494 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.856 - -Slack : 17.622 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.856 - -Slack : 17.637 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.841 - -Slack : 17.637 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.841 +Clock Skew : -0.369 +Data Delay : 2.983 -Slack : 17.637 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +Slack : 17.494 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.841 +Clock Skew : -0.369 +Data Delay : 2.983 -Slack : 17.637 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +Slack : 17.494 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.841 - -Slack : 17.655 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 Clock Skew : -0.369 -Data Delay : 2.822 +Data Delay : 2.983 -Slack : 17.655 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 2.822 - -Slack : 17.711 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.767 - -Slack : 17.711 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.767 - -Slack : 17.731 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.747 - -Slack : 17.731 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.747 - -Slack : 17.731 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.747 - -Slack : 17.731 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.747 - -Slack : 17.731 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.747 - -Slack : 17.742 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.736 - -Slack : 17.742 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.736 - -Slack : 17.744 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 2.733 - -Slack : 17.744 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 2.733 - -Slack : 17.770 +Slack : 17.547 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 Clock Skew : -0.369 -Data Delay : 2.707 +Data Delay : 2.930 -Slack : 17.775 +Slack : 17.549 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 Clock Skew : -0.369 -Data Delay : 2.702 +Data Delay : 2.928 -Slack : 17.802 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +Slack : 17.582 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.895 + +Slack : 17.582 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.895 + +Slack : 17.585 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.676 +Clock Skew : -0.369 +Data Delay : 2.892 -Slack : 17.802 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.676 - -Slack : 17.802 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.676 - -Slack : 17.802 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.676 - -Slack : 17.820 +Slack : 17.585 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.658 - -Slack : 17.820 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.658 - -Slack : 17.820 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.658 - -Slack : 17.820 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.658 - -Slack : 17.820 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.658 - -Slack : 17.831 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.647 +Clock Skew : -0.369 +Data Delay : 2.892 -Slack : 17.876 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +Slack : 17.585 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.892 + +Slack : 17.585 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.892 + +Slack : 17.585 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.892 + +Slack : 17.586 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.370 +Data Delay : 2.890 + +Slack : 17.586 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.370 +Data Delay : 2.890 + +Slack : 17.588 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.370 +Data Delay : 2.888 + +Slack : 17.588 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.370 +Data Delay : 2.888 + +Slack : 17.672 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.805 + +Slack : 17.673 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.804 + +Slack : 17.673 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.804 + +Slack : 17.711 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.370 +Data Delay : 2.765 + +Slack : 17.711 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.370 +Data Delay : 2.765 + +Slack : 17.713 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.602 +Clock Skew : -0.369 +Data Delay : 2.764 -Slack : 17.876 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +Slack : 17.713 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.602 +Clock Skew : -0.369 +Data Delay : 2.764 -Slack : 17.890 +Slack : 17.715 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.762 + +Slack : 17.715 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.762 + +Slack : 17.763 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.714 + +Slack : 17.802 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.370 +Data Delay : 2.674 + +Slack : 17.802 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.370 +Data Delay : 2.674 + +Slack : 17.835 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.053 +Data Delay : 2.958 + +Slack : 17.835 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.053 +Data Delay : 2.958 + +Slack : 17.835 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.053 +Data Delay : 2.958 + +Slack : 17.835 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.053 +Data Delay : 2.958 + +Slack : 17.835 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.053 +Data Delay : 2.958 + +Slack : 17.837 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.053 +Data Delay : 2.956 + +Slack : 17.837 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.053 +Data Delay : 2.956 + +Slack : 17.837 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.053 +Data Delay : 2.956 + +Slack : 17.837 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.053 +Data Delay : 2.956 + +Slack : 17.837 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.053 +Data Delay : 2.956 + +Slack : 17.838 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.639 + +Slack : 17.838 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.639 + +Slack : 17.925 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.552 + +Slack : 17.925 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.552 + +Slack : 17.925 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.552 + +Slack : 17.925 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.552 + +Slack : 17.927 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.550 + +Slack : 17.927 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.550 + +Slack : 17.927 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.550 + +Slack : 17.927 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.550 + +Slack : 17.929 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.548 + +Slack : 17.929 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.548 + +Slack : 17.943 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 Clock Skew : -0.049 -Data Delay : 2.907 +Data Delay : 2.854 -Slack : 17.895 +Slack : 17.945 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 Clock Skew : -0.049 -Data Delay : 2.902 +Data Delay : 2.852 -Slack : 17.897 +Slack : 17.950 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.527 + +Slack : 17.950 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.527 + +Slack : 17.950 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.527 + +Slack : 17.950 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.527 + +Slack : 17.950 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.527 + +Slack : 17.960 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 2.580 - -Slack : 17.909 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 2.568 - -Slack : 17.909 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.369 -Data Delay : 2.568 - -Slack : 17.955 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.523 - -Slack : 17.955 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.523 - -Slack : 17.985 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.493 +Clock Skew : -0.053 +Data Delay : 2.833 -Slack : 17.985 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +Slack : 17.960 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.493 +Clock Skew : -0.053 +Data Delay : 2.833 -Slack : 17.985 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +Slack : 17.960 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.493 +Clock Skew : -0.053 +Data Delay : 2.833 -Slack : 17.985 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +Slack : 17.960 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.493 +Clock Skew : -0.053 +Data Delay : 2.833 -Slack : 17.985 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +Slack : 17.960 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.368 -Data Delay : 2.493 +Clock Skew : -0.053 +Data Delay : 2.833 -Slack : 17.986 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +Slack : 18.038 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 Clock Skew : -0.369 -Data Delay : 2.491 +Data Delay : 2.439 -Slack : 18.007 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out +Slack : 18.038 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.396 -Data Delay : 2.353 +Clock Skew : -0.369 +Data Delay : 2.439 + +Slack : 18.038 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.439 + +Slack : 18.038 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.439 + +Slack : 18.038 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.439 + +Slack : 18.038 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.439 + +Slack : 18.038 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.439 + +Slack : 18.050 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.427 + +Slack : 18.050 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.427 + +Slack : 18.050 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.427 + +Slack : 18.050 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.369 +Data Delay : 2.427 + +Slack : 18.051 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.053 +Data Delay : 2.742 +--------------------------------------------------------------------------------+ @@ -13531,23 +13531,23 @@ Data Delay : 2.353 +--------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' ; +--------------------------------------------------------------------------------+ -Slack : -2.785 +Slack : -2.786 From Node : SW[2] To Node : ula:ula_|clocks:clocks_|clk_cpu Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Relationship : 0.423 Clock Skew : 0.254 -Data Delay : 1.417 +Data Delay : 1.418 -Slack : 70.539 +Slack : 70.541 From Node : ula:ula_|clocks:clocks_|counter[0] To Node : ula:ula_|clocks:clocks_|clk_cpu Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Relationship : 71.489 Clock Skew : -0.069 -Data Delay : 0.876 +Data Delay : 0.874 Slack : 70.832 From Node : ula:ula_|clocks:clocks_|counter[0] @@ -13570,6 +13570,912 @@ Data Delay : 0.583 ++--------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ; ++--------------------------------------------------------------------------------+ +Slack : 0.297 +From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 +To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.070 +Data Delay : 0.511 + +Slack : 0.298 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 0.511 + +Slack : 0.298 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 0.511 + +Slack : 0.305 +From Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 +To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.070 +Data Delay : 0.519 + +Slack : 0.306 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 0.519 + +Slack : 0.306 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 0.519 + +Slack : 0.311 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.511 + +Slack : 0.311 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.511 + +Slack : 0.311 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.511 + +Slack : 0.311 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.511 + +Slack : 0.312 +From Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.511 + +Slack : 0.312 +From Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.511 + +Slack : 0.312 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.511 + +Slack : 0.312 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.511 + +Slack : 0.312 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.511 + +Slack : 0.312 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.511 + +Slack : 0.320 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.519 + +Slack : 0.320 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.519 + +Slack : 0.320 +From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.519 + +Slack : 0.337 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.537 + +Slack : 0.338 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.538 + +Slack : 0.339 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.539 + +Slack : 0.339 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.539 + +Slack : 0.339 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.539 + +Slack : 0.339 +From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.538 + +Slack : 0.340 +From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.539 + +Slack : 0.341 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.541 + +Slack : 0.342 +From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.541 + +Slack : 0.368 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.567 + +Slack : 0.386 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.585 + +Slack : 0.386 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.585 + +Slack : 0.393 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.389 +Data Delay : 0.926 + +Slack : 0.431 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.631 + +Slack : 0.431 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.631 + +Slack : 0.432 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.632 + +Slack : 0.432 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.632 + +Slack : 0.434 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.388 +Data Delay : 0.966 + +Slack : 0.453 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.388 +Data Delay : 0.985 + +Slack : 0.476 +From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.675 + +Slack : 0.486 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 0.699 + +Slack : 0.487 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.687 + +Slack : 0.488 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 0.701 + +Slack : 0.490 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.690 + +Slack : 0.490 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 0.703 + +Slack : 0.492 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 0.705 + +Slack : 0.495 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.695 + +Slack : 0.497 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.697 + +Slack : 0.498 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 0.711 + +Slack : 0.499 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.699 + +Slack : 0.500 +From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.699 + +Slack : 0.501 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.700 + +Slack : 0.502 +From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.701 + +Slack : 0.502 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.701 + +Slack : 0.504 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 0.717 + +Slack : 0.509 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.709 + +Slack : 0.514 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.714 + +Slack : 0.514 +From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.068 +Data Delay : 0.726 + +Slack : 0.516 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.715 + +Slack : 0.518 +From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.068 +Data Delay : 0.730 + +Slack : 0.518 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.717 + +Slack : 0.519 +From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.068 +Data Delay : 0.731 + +Slack : 0.519 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.388 +Data Delay : 1.051 + +Slack : 0.520 +From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.068 +Data Delay : 0.732 + +Slack : 0.526 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.725 + +Slack : 0.540 +From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.068 +Data Delay : 0.752 + +Slack : 0.540 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.739 + +Slack : 0.546 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.745 + +Slack : 0.561 +From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.760 + +Slack : 0.562 +From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.761 + +Slack : 0.575 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.388 +Data Delay : 1.107 + +Slack : 0.606 +From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.805 + +Slack : 0.651 +From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.850 + +Slack : 0.657 +From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.856 + +Slack : 0.662 +From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.861 + +Slack : 0.663 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.862 + +Slack : 0.664 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.863 + +Slack : 0.664 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.388 +Data Delay : 1.196 + +Slack : 0.665 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : -0.265 +Data Delay : 0.544 + +Slack : 0.666 +From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.865 + +Slack : 0.719 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.918 + +Slack : 0.719 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.384 +Data Delay : 1.247 + +Slack : 0.719 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.384 +Data Delay : 1.247 + +Slack : 0.719 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.384 +Data Delay : 1.247 + +Slack : 0.719 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.384 +Data Delay : 1.247 + +Slack : 0.719 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.384 +Data Delay : 1.247 + +Slack : 0.730 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 0.943 + +Slack : 0.733 +From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.932 + +Slack : 0.733 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 0.946 + +Slack : 0.735 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.934 + +Slack : 0.736 +From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.935 + +Slack : 0.737 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 0.950 + +Slack : 0.739 +From Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 +To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.938 + +Slack : 0.739 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 0.952 + +Slack : 0.739 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 0.952 + +Slack : 0.744 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.943 + +Slack : 0.744 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 0.957 + +Slack : 0.745 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.944 + +Slack : 0.745 +From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.944 + +Slack : 0.746 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 0.959 + +Slack : 0.746 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.069 +Data Delay : 0.959 ++--------------------------------------------------------------------------------+ + + + +--------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' ; +--------------------------------------------------------------------------------+ @@ -13591,1835 +14497,23 @@ Relationship : 0.000 Clock Skew : 0.069 Data Delay : 0.519 -Slack : 0.518 +Slack : 0.517 From Node : ula:ula_|clocks:clocks_|counter[0] To Node : ula:ula_|clocks:clocks_|clk_cpu Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Relationship : 0.000 Clock Skew : 0.069 -Data Delay : 0.731 +Data Delay : 0.730 -Slack : 1.248 +Slack : 1.246 From Node : SW[2] To Node : ula:ula_|clocks:clocks_|clk_cpu Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Relationship : -0.017 Clock Skew : 0.626 -Data Delay : 1.091 -+--------------------------------------------------------------------------------+ - - - -+--------------------------------------------------------------------------------+ -; Slow 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ; -+--------------------------------------------------------------------------------+ -Slack : 0.300 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.067 -Data Delay : 0.511 - -Slack : 0.306 -From Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 -To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 0.519 - -Slack : 0.306 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 0.519 - -Slack : 0.307 -From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.068 -Data Delay : 0.519 - -Slack : 0.311 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.511 - -Slack : 0.311 -From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.511 - -Slack : 0.311 -From Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.511 - -Slack : 0.312 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.511 - -Slack : 0.312 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.511 - -Slack : 0.312 -From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.511 - -Slack : 0.312 -From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.511 - -Slack : 0.312 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.511 - -Slack : 0.312 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.511 - -Slack : 0.312 -From Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] -To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.511 - -Slack : 0.312 -From Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] -To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.511 - -Slack : 0.312 -From Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 -To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.511 - -Slack : 0.319 -From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.519 - -Slack : 0.319 -From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.519 - -Slack : 0.320 -From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.519 - -Slack : 0.322 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 0.535 - -Slack : 0.339 -From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.538 - -Slack : 0.342 -From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 -To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.541 - -Slack : 0.342 -From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 -To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.541 - -Slack : 0.344 -From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.543 - -Slack : 0.361 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle -To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.561 - -Slack : 0.363 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle -To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.563 - -Slack : 0.418 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 0.631 - -Slack : 0.418 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 0.631 - -Slack : 0.419 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 0.632 - -Slack : 0.419 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 0.632 - -Slack : 0.421 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 0.634 - -Slack : 0.469 -From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.668 - -Slack : 0.474 -From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.673 - -Slack : 0.487 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 0.700 - -Slack : 0.490 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 0.703 - -Slack : 0.491 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.096 -Data Delay : 0.731 - -Slack : 0.492 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 0.705 - -Slack : 0.498 -From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.697 - -Slack : 0.499 -From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.698 - -Slack : 0.501 -From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.700 - -Slack : 0.501 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 0.714 - -Slack : 0.502 -From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.701 - -Slack : 0.503 -From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.702 - -Slack : 0.503 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 0.716 - -Slack : 0.507 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.706 - -Slack : 0.508 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.707 - -Slack : 0.514 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 0.727 - -Slack : 0.515 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 0.728 - -Slack : 0.516 -From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.715 - -Slack : 0.518 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 0.731 - -Slack : 0.518 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 0.731 - -Slack : 0.518 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 0.731 - -Slack : 0.518 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 0.731 - -Slack : 0.518 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 0.731 - -Slack : 0.518 -From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.717 - -Slack : 0.519 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 0.732 - -Slack : 0.520 -From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.719 - -Slack : 0.529 -From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.728 - -Slack : 0.532 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.387 -Data Delay : 1.063 - -Slack : 0.537 -From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.736 - -Slack : 0.538 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.737 - -Slack : 0.539 -From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.738 - -Slack : 0.547 -From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.746 - -Slack : 0.548 -From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.747 - -Slack : 0.561 -From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.761 - -Slack : 0.563 -From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.763 - -Slack : 0.565 -From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.764 - -Slack : 0.599 -From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.799 - -Slack : 0.605 -From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.805 - -Slack : 0.630 -From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 -To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.829 - -Slack : 0.668 -From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : -0.265 -Data Delay : 0.547 - -Slack : 0.701 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start -To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.901 - -Slack : 0.701 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.901 - -Slack : 0.706 -From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.905 - -Slack : 0.709 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.908 - -Slack : 0.709 -From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.054 -Data Delay : 0.907 - -Slack : 0.710 -From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.054 -Data Delay : 0.908 - -Slack : 0.714 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.914 - -Slack : 0.721 -From Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.921 - -Slack : 0.728 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.927 - -Slack : 0.729 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.928 - -Slack : 0.731 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 0.944 - -Slack : 0.735 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 0.948 - -Slack : 0.738 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 0.951 - -Slack : 0.740 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 0.953 - -Slack : 0.741 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 0.954 - -Slack : 0.744 -From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.943 - -Slack : 0.745 -From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.944 - -Slack : 0.745 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 0.958 - -Slack : 0.746 -From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.945 - -Slack : 0.747 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 0.960 - -Slack : 0.748 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.069 -Data Delay : 0.961 - -Slack : 0.749 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : -0.261 -Data Delay : 0.632 - -Slack : 0.750 -From Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.068 -Data Delay : 0.962 - -Slack : 0.753 -From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.952 - -Slack : 0.760 -From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.959 - -Slack : 0.764 -From Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 -To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.964 - -Slack : 0.770 -From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.969 - -Slack : 0.772 -From Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 -To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.972 - -Slack : 0.773 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.972 -+--------------------------------------------------------------------------------+ - - - -+--------------------------------------------------------------------------------+ -; Slow 1200mV 0C Model Hold: 'CLOCK_50' ; -+--------------------------------------------------------------------------------+ -Slack : 0.304 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.304 -Data Delay : 2.881 - -Slack : 0.359 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.305 -Data Delay : 2.937 - -Slack : 1.206 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.252 -Data Delay : 3.731 - -Slack : 1.215 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.251 -Data Delay : 3.739 - -Slack : 1.221 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.255 -Data Delay : 3.749 - -Slack : 1.229 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.242 -Data Delay : 3.744 - -Slack : 1.234 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.252 -Data Delay : 3.759 - -Slack : 1.240 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.245 -Data Delay : 3.758 - -Slack : 1.262 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.238 -Data Delay : 3.773 - -Slack : 1.264 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.255 -Data Delay : 3.792 - -Slack : 1.266 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.245 -Data Delay : 3.784 - -Slack : 1.278 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.242 -Data Delay : 3.793 - -Slack : 1.287 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.242 -Data Delay : 3.802 - -Slack : 1.332 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.248 -Data Delay : 3.853 - -Slack : 1.340 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.245 -Data Delay : 3.858 - -Slack : 1.351 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.240 -Data Delay : 3.864 - -Slack : 1.367 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.241 -Data Delay : 3.881 - -Slack : 1.373 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.251 -Data Delay : 3.897 - -Slack : 1.373 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.237 -Data Delay : 3.883 - -Slack : 1.378 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.247 -Data Delay : 3.898 - -Slack : 1.378 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.230 -Data Delay : 3.881 - -Slack : 1.379 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.242 -Data Delay : 3.894 - -Slack : 1.379 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.240 -Data Delay : 3.892 - -Slack : 1.383 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.230 -Data Delay : 3.886 - -Slack : 1.384 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.234 -Data Delay : 3.891 - -Slack : 1.389 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.242 -Data Delay : 3.904 - -Slack : 1.393 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.230 -Data Delay : 3.896 - -Slack : 1.394 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.242 -Data Delay : 3.909 - -Slack : 1.396 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.242 -Data Delay : 3.911 - -Slack : 1.400 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.238 -Data Delay : 3.911 - -Slack : 1.401 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.230 -Data Delay : 3.904 - -Slack : 1.402 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.233 -Data Delay : 3.908 - -Slack : 1.405 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.247 -Data Delay : 3.925 - -Slack : 1.407 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.241 -Data Delay : 3.921 - -Slack : 1.410 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.240 -Data Delay : 3.923 - -Slack : 1.410 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.241 -Data Delay : 3.924 - -Slack : 1.412 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.242 -Data Delay : 3.927 - -Slack : 1.413 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.233 -Data Delay : 3.919 - -Slack : 1.417 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.240 -Data Delay : 3.930 - -Slack : 1.417 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.230 -Data Delay : 3.920 - -Slack : 1.425 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.251 -Data Delay : 3.949 - -Slack : 1.433 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.248 -Data Delay : 3.954 - -Slack : 1.434 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.234 -Data Delay : 3.941 - -Slack : 1.435 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.230 -Data Delay : 3.938 - -Slack : 1.435 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.245 -Data Delay : 3.953 - -Slack : 1.436 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.238 -Data Delay : 3.947 - -Slack : 1.440 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.237 -Data Delay : 3.950 - -Slack : 1.442 -From Node : ula:ula_|video:video_|vram_address[8] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.243 -Data Delay : 3.958 - -Slack : 1.449 -From Node : ula:ula_|video:video_|vram_address[3] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.238 -Data Delay : 3.960 - -Slack : 1.451 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.234 -Data Delay : 3.958 - -Slack : 1.452 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.310 -Data Delay : 4.035 - -Slack : 1.452 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.237 -Data Delay : 3.962 - -Slack : 1.453 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.238 -Data Delay : 3.964 - -Slack : 1.454 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.233 -Data Delay : 3.960 - -Slack : 1.455 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.326 -Data Delay : 4.054 - -Slack : 1.455 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.090 -Data Delay : 3.818 - -Slack : 1.455 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.248 -Data Delay : 3.976 - -Slack : 1.458 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.248 -Data Delay : 3.979 - -Slack : 1.460 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.242 -Data Delay : 3.975 - -Slack : 1.460 -From Node : ula:ula_|video:video_|vram_address[11] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.243 -Data Delay : 3.976 - -Slack : 1.460 -From Node : ula:ula_|video:video_|vram_address[11] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.241 -Data Delay : 3.974 - -Slack : 1.460 -From Node : ula:ula_|video:video_|vram_address[10] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.235 -Data Delay : 3.968 - -Slack : 1.461 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.233 -Data Delay : 3.967 - -Slack : 1.465 -From Node : ula:ula_|video:video_|vram_address[11] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.253 -Data Delay : 3.991 - -Slack : 1.465 -From Node : ula:ula_|video:video_|vram_address[12] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.234 -Data Delay : 3.972 - -Slack : 1.466 -From Node : ula:ula_|video:video_|vram_address[11] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.231 -Data Delay : 3.970 - -Slack : 1.467 -From Node : ula:ula_|video:video_|vram_address[11] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.231 -Data Delay : 3.971 - -Slack : 1.471 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.252 -Data Delay : 3.996 - -Slack : 1.473 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.230 -Data Delay : 3.976 - -Slack : 1.476 -From Node : ula:ula_|video:video_|vram_address[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.238 -Data Delay : 3.987 - -Slack : 1.480 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.251 -Data Delay : 4.004 - -Slack : 1.481 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.301 -Data Delay : 4.055 - -Slack : 1.482 -From Node : ula:ula_|video:video_|vram_address[8] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.242 -Data Delay : 3.997 - -Slack : 1.485 -From Node : ula:ula_|video:video_|vram_address[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.230 -Data Delay : 3.988 - -Slack : 1.485 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.245 -Data Delay : 4.003 - -Slack : 1.487 -From Node : ula:ula_|video:video_|vram_address[11] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.234 -Data Delay : 3.994 - -Slack : 1.487 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.309 -Data Delay : 4.069 - -Slack : 1.489 -From Node : ula:ula_|video:video_|vram_address[11] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.242 -Data Delay : 4.004 - -Slack : 1.490 -From Node : ula:ula_|video:video_|vram_address[8] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.239 -Data Delay : 4.002 - -Slack : 1.492 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.230 -Data Delay : 3.995 - -Slack : 1.493 -From Node : ula:ula_|video:video_|vram_address[12] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.242 -Data Delay : 4.008 - -Slack : 1.494 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.237 -Data Delay : 4.004 - -Slack : 1.494 -From Node : ula:ula_|video:video_|vram_address[3] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.241 -Data Delay : 4.008 - -Slack : 1.496 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.234 -Data Delay : 4.003 - -Slack : 1.498 -From Node : ula:ula_|video:video_|vram_address[8] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.238 -Data Delay : 4.009 - -Slack : 1.498 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.238 -Data Delay : 4.009 - -Slack : 1.499 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.322 -Data Delay : 4.094 - -Slack : 1.502 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.230 -Data Delay : 4.005 - -Slack : 1.503 -From Node : ula:ula_|video:video_|vram_address[11] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.238 -Data Delay : 4.014 - -Slack : 1.504 -From Node : ula:ula_|video:video_|vram_address[10] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.231 -Data Delay : 4.008 - -Slack : 1.505 -From Node : ula:ula_|video:video_|vram_address[10] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.248 -Data Delay : 4.026 - -Slack : 1.507 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.252 -Data Delay : 4.032 - -Slack : 1.508 -From Node : ula:ula_|video:video_|vram_address[10] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.246 -Data Delay : 4.027 - -Slack : 1.509 -From Node : ula:ula_|video:video_|vram_address[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.242 -Data Delay : 4.024 - -Slack : 1.510 -From Node : ula:ula_|video:video_|vram_address[8] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.252 -Data Delay : 4.035 - -Slack : 1.510 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.081 -Data Delay : 3.864 - -Slack : 1.511 -From Node : ula:ula_|video:video_|vram_address[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.233 -Data Delay : 4.017 - -Slack : 1.513 -From Node : ula:ula_|video:video_|vram_address[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.237 -Data Delay : 4.023 - -Slack : 1.513 -From Node : ula:ula_|video:video_|vram_address[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.234 -Data Delay : 4.020 - -Slack : 1.520 -From Node : ula:ula_|video:video_|vram_address[10] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 2.234 -Data Delay : 4.027 +Data Delay : 1.089 +--------------------------------------------------------------------------------+ @@ -15437,8 +14531,8 @@ Clock Skew : 0.056 Data Delay : 0.511 Slack : 0.311 -From Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 -To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 +From Node : ula:ula_|video:video_|vga_vc[9] +To Node : ula:ula_|video:video_|vga_vc[9] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 @@ -15446,8 +14540,8 @@ Clock Skew : 0.056 Data Delay : 0.511 Slack : 0.311 -From Node : ula:ula_|video:video_|vram_address[10] -To Node : ula:ula_|video:video_|vram_address[10] +From Node : ula:ula_|video:video_|vga_vc[4] +To Node : ula:ula_|video:video_|vga_vc[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 @@ -15455,8 +14549,26 @@ Clock Skew : 0.056 Data Delay : 0.511 Slack : 0.311 -From Node : ula:ula_|video:video_|frame[0] -To Node : ula:ula_|video:video_|frame[0] +From Node : ula:ula_|video:video_|vga_vc[5] +To Node : ula:ula_|video:video_|vga_vc[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.511 + +Slack : 0.311 +From Node : ula:ula_|video:video_|vga_vc[6] +To Node : ula:ula_|video:video_|vga_vc[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.511 + +Slack : 0.311 +From Node : ula:ula_|video:video_|vga_vc[7] +To Node : ula:ula_|video:video_|vga_vc[7] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 @@ -15464,8 +14576,8 @@ Clock Skew : 0.056 Data Delay : 0.511 Slack : 0.312 -From Node : ula:ula_|video:video_|vga_vc[9] -To Node : ula:ula_|video:video_|vga_vc[9] +From Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 +To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 @@ -15473,8 +14585,17 @@ Clock Skew : 0.055 Data Delay : 0.511 Slack : 0.312 -From Node : ula:ula_|video:video_|vga_vc[0] -To Node : ula:ula_|video:video_|vga_vc[0] +From Node : ula:ula_|video:video_|vram_address[10] +To Node : ula:ula_|video:video_|vram_address[10] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.511 + +Slack : 0.312 +From Node : ula:ula_|video:video_|frame[0] +To Node : ula:ula_|video:video_|frame[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 @@ -15490,15 +14611,6 @@ Relationship : 0.000 Clock Skew : 0.055 Data Delay : 0.511 -Slack : 0.312 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : ula:ula_|video:video_|vga_vc[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.511 - Slack : 0.312 From Node : ula:ula_|video:video_|vga_vc[8] To Node : ula:ula_|video:video_|vga_vc[8] @@ -15508,41 +14620,14 @@ Relationship : 0.000 Clock Skew : 0.055 Data Delay : 0.511 -Slack : 0.312 -From Node : ula:ula_|video:video_|vga_vc[4] -To Node : ula:ula_|video:video_|vga_vc[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.511 - -Slack : 0.312 -From Node : ula:ula_|video:video_|vga_vc[6] -To Node : ula:ula_|video:video_|vga_vc[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.511 - -Slack : 0.312 -From Node : ula:ula_|video:video_|vga_vc[7] -To Node : ula:ula_|video:video_|vga_vc[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.511 - -Slack : 0.493 +Slack : 0.496 From Node : ula:ula_|video:video_|frame[2] To Node : ula:ula_|video:video_|frame[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.692 +Clock Skew : 0.056 +Data Delay : 0.696 Slack : 0.498 From Node : ula:ula_|video:video_|frame[3] @@ -15550,782 +14635,1697 @@ To Node : ula:ula_|video:video_|frame[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.697 +Clock Skew : 0.056 +Data Delay : 0.698 -Slack : 0.509 +Slack : 0.508 From Node : ula:ula_|video:video_|frame[1] To Node : ula:ula_|video:video_|frame[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.055 +Clock Skew : 0.056 Data Delay : 0.708 -Slack : 0.512 +Slack : 0.741 +From Node : ula:ula_|video:video_|frame[2] +To Node : ula:ula_|video:video_|frame[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.941 + +Slack : 0.747 +From Node : ula:ula_|video:video_|frame[1] +To Node : ula:ula_|video:video_|frame[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.947 + +Slack : 0.754 +From Node : ula:ula_|video:video_|frame[1] +To Node : ula:ula_|video:video_|frame[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.954 + +Slack : 0.824 +From Node : ula:ula_|video:video_|bits_prefetch[1] +To Node : ula:ula_|video:video_|bits[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.261 +Data Delay : 0.707 + +Slack : 0.837 +From Node : ula:ula_|video:video_|bits_prefetch[5] +To Node : ula:ula_|video:video_|bits[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.261 +Data Delay : 0.720 + +Slack : 0.888 +From Node : ula:ula_|video:video_|vga_hc[6] +To Node : ula:ula_|video:video_|vram_address[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 1.086 + +Slack : 0.890 +From Node : ula:ula_|video:video_|vga_hc[6] +To Node : ula:ula_|video:video_|vram_address[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 1.088 + +Slack : 0.891 +From Node : ula:ula_|video:video_|vga_hc[6] +To Node : ula:ula_|video:video_|vram_address[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 1.089 + +Slack : 0.945 +From Node : ula:ula_|video:video_|bits_prefetch[4] +To Node : ula:ula_|video:video_|bits[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.261 +Data Delay : 0.828 + +Slack : 0.946 +From Node : ula:ula_|video:video_|bits_prefetch[3] +To Node : ula:ula_|video:video_|bits[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.261 +Data Delay : 0.829 + +Slack : 0.950 +From Node : ula:ula_|video:video_|vga_hc[1] +To Node : ula:ula_|video:video_|vram_address[10] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.149 + +Slack : 0.953 +From Node : ula:ula_|video:video_|vga_hc[5] +To Node : ula:ula_|video:video_|vram_address[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 1.151 + +Slack : 0.961 +From Node : ula:ula_|video:video_|vga_vc[4] +To Node : ula:ula_|video:video_|vram_address[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 1.159 + +Slack : 0.973 +From Node : ula:ula_|video:video_|vga_hc[4] +To Node : ula:ula_|video:video_|vram_address[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 1.171 + +Slack : 0.974 +From Node : ula:ula_|video:video_|bits_prefetch[7] +To Node : ula:ula_|video:video_|bits[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.261 +Data Delay : 0.857 + +Slack : 0.986 +From Node : ula:ula_|video:video_|bits_prefetch[2] +To Node : ula:ula_|video:video_|bits[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.261 +Data Delay : 0.869 + +Slack : 1.002 +From Node : ula:ula_|video:video_|attr_prefetch[7] +To Node : ula:ula_|video:video_|attr[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.288 +Data Delay : 0.858 + +Slack : 1.004 +From Node : ula:ula_|video:video_|attr_prefetch[3] +To Node : ula:ula_|video:video_|attr[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.288 +Data Delay : 0.860 + +Slack : 1.035 +From Node : ula:ula_|video:video_|frame[0] +To Node : ula:ula_|video:video_|frame[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 1.235 + +Slack : 1.041 +From Node : ula:ula_|video:video_|attr_prefetch[0] +To Node : ula:ula_|video:video_|attr[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.288 +Data Delay : 0.897 + +Slack : 1.060 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|vram_address[12] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.259 + +Slack : 1.060 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|vram_address[11] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.259 + +Slack : 1.123 +From Node : ula:ula_|video:video_|bits_prefetch[6] +To Node : ula:ula_|video:video_|bits[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.261 +Data Delay : 1.006 + +Slack : 1.124 +From Node : ula:ula_|video:video_|vga_vc[5] +To Node : ula:ula_|video:video_|vram_address[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 1.322 + +Slack : 1.127 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|vram_address[9] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.326 + +Slack : 1.127 +From Node : ula:ula_|video:video_|vga_vc[6] +To Node : ula:ula_|video:video_|vram_address[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 1.325 + +Slack : 1.129 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|vram_address[8] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.328 + +Slack : 1.130 +From Node : ula:ula_|video:video_|vga_hc[8] +To Node : ula:ula_|video:video_|vram_address[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.329 + +Slack : 1.140 +From Node : ula:ula_|video:video_|vga_hc[7] +To Node : ula:ula_|video:video_|vram_address[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 1.338 + +Slack : 1.141 +From Node : ula:ula_|video:video_|vga_hc[7] +To Node : ula:ula_|video:video_|vram_address[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 1.339 + +Slack : 1.160 +From Node : ula:ula_|video:video_|vga_vc[9] +To Node : ula:ula_|video:video_|frame[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.359 + +Slack : 1.176 +From Node : ula:ula_|video:video_|attr_prefetch[6] +To Node : ula:ula_|video:video_|attr[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.287 +Data Delay : 1.033 + +Slack : 1.180 +From Node : ula:ula_|video:video_|vga_hc[7] +To Node : ula:ula_|video:video_|vga_hc[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.379 + +Slack : 1.182 +From Node : ula:ula_|video:video_|vga_hc[6] +To Node : ula:ula_|video:video_|vga_hc[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.381 + +Slack : 1.188 +From Node : ula:ula_|video:video_|attr_prefetch[4] +To Node : ula:ula_|video:video_|attr[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.287 +Data Delay : 1.045 + +Slack : 1.195 +From Node : ula:ula_|video:video_|vga_hc[8] +To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.394 + +Slack : 1.206 +From Node : ula:ula_|video:video_|vga_vc[4] +To Node : ula:ula_|video:video_|vram_address[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 1.404 + +Slack : 1.228 +From Node : ula:ula_|video:video_|attr_prefetch[5] +To Node : ula:ula_|video:video_|attr[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.287 +Data Delay : 1.085 + +Slack : 1.237 +From Node : ula:ula_|video:video_|vga_hc[3] +To Node : ula:ula_|video:video_|vram_address[10] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 1.435 + +Slack : 1.266 +From Node : ula:ula_|video:video_|frame[0] +To Node : ula:ula_|video:video_|frame[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 1.466 + +Slack : 1.280 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 1.478 + +Slack : 1.287 +From Node : ula:ula_|video:video_|frame[0] +To Node : ula:ula_|video:video_|frame[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 1.487 + +Slack : 1.295 +From Node : ula:ula_|video:video_|vga_vc[4] +To Node : ula:ula_|video:video_|vram_address[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 1.493 + +Slack : 1.307 +From Node : ula:ula_|video:video_|frame[3] +To Node : ula:ula_|video:video_|frame[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.053 +Data Delay : 1.504 + +Slack : 1.309 From Node : ula:ula_|video:video_|frame[4] To Node : ula:ula_|video:video_|frame[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.055 -Data Delay : 0.711 +Data Delay : 1.508 -Slack : 0.596 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[1] -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +Slack : 1.324 +From Node : ula:ula_|video:video_|vga_hc[6] +To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.795 +Clock Skew : 0.054 +Data Delay : 1.522 -Slack : 0.652 +Slack : 1.337 From Node : ula:ula_|video:video_|vga_hc[0] To Node : ula:ula_|video:video_|vram_address[10] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.852 +Clock Skew : -0.261 +Data Delay : 1.220 -Slack : 0.737 -From Node : ula:ula_|video:video_|frame[2] -To Node : ula:ula_|video:video_|frame[3] +Slack : 1.345 +From Node : ula:ula_|video:video_|vga_vc[8] +To Node : ula:ula_|video:video_|vram_address[12] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.936 +Clock Skew : 0.056 +Data Delay : 1.545 -Slack : 0.747 -From Node : ula:ula_|video:video_|frame[3] +Slack : 1.345 +From Node : ula:ula_|video:video_|vga_vc[8] +To Node : ula:ula_|video:video_|vram_address[9] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 1.545 + +Slack : 1.365 +From Node : ula:ula_|video:video_|vga_vc[5] +To Node : ula:ula_|video:video_|vram_address[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 1.563 + +Slack : 1.390 +From Node : ula:ula_|video:video_|frame[2] To Node : ula:ula_|video:video_|frame[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.946 +Clock Skew : 0.053 +Data Delay : 1.587 -Slack : 0.748 +Slack : 1.403 From Node : ula:ula_|video:video_|frame[1] -To Node : ula:ula_|video:video_|frame[2] +To Node : ula:ula_|video:video_|frame[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.053 +Data Delay : 1.600 + +Slack : 1.422 +From Node : ula:ula_|video:video_|vga_hc[6] +To Node : ula:ula_|video:video_|vga_hc[7] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.055 -Data Delay : 0.947 +Data Delay : 1.621 -Slack : 0.751 +Slack : 1.455 +From Node : ula:ula_|video:video_|vga_vc[0] +To Node : ula:ula_|video:video_|vram_address[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.654 + +Slack : 1.462 +From Node : ula:ula_|video:video_|vga_vc[0] +To Node : ula:ula_|video:video_|vram_address[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.661 + +Slack : 1.468 +From Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1 +To Node : ula:ula_|video:video_|VGA_VS +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.030 +Data Delay : 1.584 + +Slack : 1.475 +From Node : ula:ula_|video:video_|vga_hc[9] +To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 1.673 + +Slack : 1.476 +From Node : ula:ula_|video:video_|vga_vc[2] +To Node : ula:ula_|video:video_|vram_address[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.675 + +Slack : 1.495 +From Node : ula:ula_|video:video_|vga_vc[7] +To Node : ula:ula_|video:video_|frame[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.694 + +Slack : 1.498 +From Node : ula:ula_|video:video_|vga_hc[3] +To Node : ula:ula_|video:video_|vga_hc[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.697 + +Slack : 1.501 +From Node : ula:ula_|video:video_|vga_vc[2] +To Node : ula:ula_|video:video_|vram_address[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.700 + +Slack : 1.519 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|vram_address[10] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.718 + +Slack : 1.543 +From Node : ula:ula_|video:video_|vga_vc[3] +To Node : ula:ula_|video:video_|vram_address[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.742 + +Slack : 1.551 +From Node : ula:ula_|video:video_|vga_vc[0] +To Node : ula:ula_|video:video_|vram_address[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.750 + +Slack : 1.555 +From Node : ula:ula_|video:video_|attr_prefetch[2] +To Node : ula:ula_|video:video_|attr[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.287 +Data Delay : 1.412 + +Slack : 1.568 +From Node : ula:ula_|video:video_|vga_hc[3] +To Node : ula:ula_|video:video_|vga_hc[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.767 + +Slack : 1.568 From Node : ula:ula_|video:video_|vga_vc[1] To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.957 - -Slack : 0.755 -From Node : ula:ula_|video:video_|frame[1] -To Node : ula:ula_|video:video_|frame[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.954 - -Slack : 0.778 -From Node : ula:ula_|video:video_|vga_hc[8] -To Node : ula:ula_|video:video_|vga_hc[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.978 - -Slack : 0.826 -From Node : ula:ula_|video:video_|frame[2] -To Node : ula:ula_|video:video_|frame[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.025 - -Slack : 0.839 -From Node : ula:ula_|video:video_|frame[0] -To Node : ula:ula_|video:video_|frame[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.038 - -Slack : 0.844 -From Node : ula:ula_|video:video_|frame[1] -To Node : ula:ula_|video:video_|frame[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.043 - -Slack : 0.885 -From Node : ula:ula_|video:video_|vga_vc[4] -To Node : ula:ula_|video:video_|vram_address[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.091 - -Slack : 0.901 -From Node : ula:ula_|video:video_|vga_vc[5] -To Node : ula:ula_|video:video_|vram_address[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.107 - -Slack : 0.911 -From Node : ula:ula_|video:video_|vga_hc[4] -To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.059 -Data Delay : 1.114 - -Slack : 0.986 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|vram_address[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.061 -Data Delay : 1.191 - -Slack : 0.987 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|vram_address[9] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.061 -Data Delay : 1.192 - -Slack : 0.996 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|vram_address[12] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.061 -Data Delay : 1.201 - -Slack : 0.996 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|vram_address[11] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.061 -Data Delay : 1.201 - -Slack : 1.019 -From Node : ula:ula_|video:video_|bits_prefetch[6] -To Node : ula:ula_|video:video_|bits[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.271 -Data Delay : 0.892 - -Slack : 1.022 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : ula:ula_|video:video_|vram_address[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.228 - -Slack : 1.025 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : ula:ula_|video:video_|vram_address[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.231 - -Slack : 1.039 -From Node : ula:ula_|video:video_|vga_hc[5] -To Node : ula:ula_|video:video_|vram_address[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.245 - -Slack : 1.040 -From Node : ula:ula_|video:video_|bits_prefetch[2] -To Node : ula:ula_|video:video_|bits[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.271 -Data Delay : 0.913 - -Slack : 1.041 -From Node : ula:ula_|video:video_|bits_prefetch[1] -To Node : ula:ula_|video:video_|bits[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.271 -Data Delay : 0.914 - -Slack : 1.050 -From Node : ula:ula_|video:video_|bits_prefetch[5] -To Node : ula:ula_|video:video_|bits[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.271 -Data Delay : 0.923 - -Slack : 1.062 -From Node : ula:ula_|video:video_|vga_hc[4] -To Node : ula:ula_|video:video_|vram_address[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.268 - -Slack : 1.070 -From Node : ula:ula_|video:video_|frame[0] -To Node : ula:ula_|video:video_|frame[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.269 - -Slack : 1.082 -From Node : ula:ula_|video:video_|frame[0] -To Node : ula:ula_|video:video_|frame[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.281 - -Slack : 1.106 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : ula:ula_|video:video_|vram_address[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.312 - -Slack : 1.130 -From Node : ula:ula_|video:video_|vga_vc[4] -To Node : ula:ula_|video:video_|vram_address[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.336 - -Slack : 1.143 -From Node : ula:ula_|video:video_|vga_vc[6] -To Node : ula:ula_|video:video_|vram_address[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.349 - -Slack : 1.145 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|vram_address[12] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 1.345 - -Slack : 1.145 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|vram_address[9] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 1.345 - -Slack : 1.145 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|vram_address[11] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 1.345 - -Slack : 1.145 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|vram_address[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 1.345 - -Slack : 1.151 -From Node : ula:ula_|video:video_|vga_vc[5] -To Node : ula:ula_|video:video_|vram_address[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.357 - -Slack : 1.153 -From Node : ula:ula_|video:video_|vga_hc[5] -To Node : ula:ula_|video:video_|vga_hc[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 1.353 - -Slack : 1.154 -From Node : ula:ula_|video:video_|vga_vc[3] -To Node : ula:ula_|video:video_|vram_address[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.360 - -Slack : 1.166 -From Node : ula:ula_|video:video_|frame[0] -To Node : ula:ula_|video:video_|frame[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.365 - -Slack : 1.168 -From Node : ula:ula_|video:video_|vga_vc[3] -To Node : ula:ula_|video:video_|vram_address[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.374 - -Slack : 1.170 -From Node : ula:ula_|video:video_|vga_hc[1] -To Node : ula:ula_|video:video_|vram_address[10] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 Clock Skew : 0.057 -Data Delay : 1.371 +Data Delay : 1.769 -Slack : 1.172 +Slack : 1.572 +From Node : ula:ula_|video:video_|vga_vc[2] +To Node : ula:ula_|video:video_|vram_address[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.771 + +Slack : 1.580 From Node : ula:ula_|video:video_|bits_prefetch[0] To Node : ula:ula_|video:video_|bits[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : -0.271 -Data Delay : 1.045 +Clock Skew : -0.261 +Data Delay : 1.463 -Slack : 1.174 -From Node : ula:ula_|video:video_|vga_hc[9] -To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 1.374 - -Slack : 1.176 -From Node : ula:ula_|video:video_|vga_hc[9] -To Node : ula:ula_|video:video_|vga_hc[9] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 1.376 - -Slack : 1.176 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|vga_hc[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 1.376 - -Slack : 1.182 -From Node : ula:ula_|video:video_|attr_prefetch[3] -To Node : ula:ula_|video:video_|attr[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.298 -Data Delay : 1.028 - -Slack : 1.183 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : ula:ula_|video:video_|vram_address[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.389 - -Slack : 1.184 -From Node : ula:ula_|video:video_|bits_prefetch[4] -To Node : ula:ula_|video:video_|bits[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.271 -Data Delay : 1.057 - -Slack : 1.200 -From Node : ula:ula_|video:video_|vga_vc[2] +Slack : 1.580 +From Node : ula:ula_|video:video_|vga_vc[3] To Node : ula:ula_|video:video_|vram_address[6] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.406 +Clock Skew : 0.055 +Data Delay : 1.779 -Slack : 1.207 -From Node : ula:ula_|video:video_|attr_prefetch[5] -To Node : ula:ula_|video:video_|attr[5] +Slack : 1.593 +From Node : ula:ula_|video:video_|vga_vc[9] +To Node : ula:ula_|video:video_|frame[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : -0.298 -Data Delay : 1.053 +Clock Skew : 0.053 +Data Delay : 1.790 -Slack : 1.219 +Slack : 1.608 From Node : ula:ula_|video:video_|vga_vc[4] -To Node : ula:ula_|video:video_|vram_address[7] +To Node : ula:ula_|video:video_|frame[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.425 +Clock Skew : 0.055 +Data Delay : 1.807 -Slack : 1.223 -From Node : ula:ula_|video:video_|attr_prefetch[7] -To Node : ula:ula_|video:video_|attr[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.298 -Data Delay : 1.069 - -Slack : 1.225 -From Node : ula:ula_|video:video_|attr_prefetch[4] -To Node : ula:ula_|video:video_|attr[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.298 -Data Delay : 1.071 - -Slack : 1.240 -From Node : ula:ula_|video:video_|attr_prefetch[0] -To Node : ula:ula_|video:video_|attr[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.298 -Data Delay : 1.086 - -Slack : 1.242 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : ula:ula_|video:video_|vga_hc[6] +Slack : 1.616 +From Node : ula:ula_|video:video_|vga_vc[8] +To Node : ula:ula_|video:video_|frame[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.056 -Data Delay : 1.442 +Data Delay : 1.816 -Slack : 1.243 +Slack : 1.617 From Node : ula:ula_|video:video_|vga_vc[0] -To Node : ula:ula_|video:video_|vram_address[5] +To Node : ula:ula_|video:video_|vram_address[8] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.449 +Clock Skew : 0.056 +Data Delay : 1.817 -Slack : 1.250 -From Node : ula:ula_|video:video_|vga_vc[0] -To Node : ula:ula_|video:video_|vram_address[6] +Slack : 1.618 +From Node : ula:ula_|video:video_|vga_vc[9] +To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.456 +Clock Skew : 0.056 +Data Delay : 1.818 -Slack : 1.250 +Slack : 1.622 +From Node : ula:ula_|video:video_|vga_hc[8] +To Node : ula:ula_|video:video_|vga_vc[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 1.820 + +Slack : 1.623 +From Node : ula:ula_|video:video_|vga_hc[8] +To Node : ula:ula_|video:video_|vga_vc[8] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 1.821 + +Slack : 1.630 +From Node : ula:ula_|video:video_|vga_hc[8] +To Node : ula:ula_|video:video_|vga_vc[9] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 1.830 + +Slack : 1.639 From Node : ula:ula_|video:video_|vga_vc[3] To Node : ula:ula_|video:video_|vram_address[7] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.456 +Clock Skew : 0.055 +Data Delay : 1.838 -Slack : 1.257 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|vga_hc[5] +Slack : 1.673 +From Node : ula:ula_|video:video_|vga_hc[5] +To Node : ula:ula_|video:video_|vga_hc[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.872 + +Slack : 1.680 +From Node : ula:ula_|video:video_|attr_prefetch[1] +To Node : ula:ula_|video:video_|attr[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.287 +Data Delay : 1.537 + +Slack : 1.680 +From Node : ula:ula_|video:video_|vga_vc[2] +To Node : ula:ula_|video:video_|vram_address[9] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.056 -Data Delay : 1.457 +Data Delay : 1.880 -Slack : 1.261 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|vram_address[5] +Slack : 1.686 +From Node : ula:ula_|video:video_|vga_hc[8] +To Node : ula:ula_|video:video_|vga_vc[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.467 +Clock Skew : 0.056 +Data Delay : 1.886 + +Slack : 1.686 +From Node : ula:ula_|video:video_|vga_hc[8] +To Node : ula:ula_|video:video_|vga_vc[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 1.886 + +Slack : 1.686 +From Node : ula:ula_|video:video_|vga_hc[8] +To Node : ula:ula_|video:video_|vga_vc[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 1.886 + +Slack : 1.688 +From Node : ula:ula_|video:video_|vga_hc[8] +To Node : ula:ula_|video:video_|vga_vc[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 1.888 ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Hold: 'CLOCK_50' ; ++--------------------------------------------------------------------------------+ +Slack : 0.467 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|address_reg_a[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.054 +Data Delay : 0.665 + +Slack : 0.574 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.325 +Data Delay : 3.172 + +Slack : 0.580 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.312 +Data Delay : 3.165 + +Slack : 1.158 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.244 +Data Delay : 3.675 + +Slack : 1.163 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.256 +Data Delay : 3.692 + +Slack : 1.166 +From Node : ula:ula_|video:video_|vram_address[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.256 +Data Delay : 3.695 + +Slack : 1.171 +From Node : ula:ula_|video:video_|vram_address[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.253 +Data Delay : 3.697 + +Slack : 1.172 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.247 +Data Delay : 3.692 + +Slack : 1.183 +From Node : ula:ula_|video:video_|vram_address[10] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.252 +Data Delay : 3.708 + +Slack : 1.192 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.250 +Data Delay : 3.715 + +Slack : 1.194 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.239 +Data Delay : 3.706 + +Slack : 1.194 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.078 +Data Delay : 3.545 + +Slack : 1.200 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.065 +Data Delay : 3.538 + +Slack : 1.203 +From Node : ula:ula_|video:video_|vram_address[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.250 +Data Delay : 3.726 + +Slack : 1.217 +From Node : ula:ula_|video:video_|vram_address[10] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.255 +Data Delay : 3.745 + +Slack : 1.219 +From Node : ula:ula_|video:video_|vram_address[2] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.247 +Data Delay : 3.739 + +Slack : 1.219 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.240 +Data Delay : 3.732 + +Slack : 1.221 +From Node : ula:ula_|video:video_|vram_address[2] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.250 +Data Delay : 3.744 + +Slack : 1.221 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.244 +Data Delay : 3.738 + +Slack : 1.223 +From Node : ula:ula_|video:video_|vram_address[10] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.249 +Data Delay : 3.745 + +Slack : 1.225 +From Node : ula:ula_|video:video_|vram_address[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.250 +Data Delay : 3.748 + +Slack : 1.226 +From Node : ula:ula_|video:video_|vram_address[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.247 +Data Delay : 3.746 + +Slack : 1.228 +From Node : ula:ula_|video:video_|vram_address[6] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.239 +Data Delay : 3.740 + +Slack : 1.230 +From Node : ula:ula_|video:video_|vram_address[6] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.235 +Data Delay : 3.738 + +Slack : 1.231 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.331 +Data Delay : 3.835 + +Slack : 1.232 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.236 +Data Delay : 3.741 + +Slack : 1.236 +From Node : ula:ula_|video:video_|vram_address[10] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.246 +Data Delay : 3.755 + +Slack : 1.237 +From Node : ula:ula_|video:video_|vram_address[2] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.256 +Data Delay : 3.766 + +Slack : 1.237 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.318 +Data Delay : 3.828 + +Slack : 1.242 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.248 +Data Delay : 3.763 + +Slack : 1.243 +From Node : ula:ula_|video:video_|vram_address[2] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.244 +Data Delay : 3.760 + +Slack : 1.248 +From Node : ula:ula_|video:video_|vram_address[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.256 +Data Delay : 3.777 + +Slack : 1.248 +From Node : ula:ula_|video:video_|vram_address[9] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.239 +Data Delay : 3.760 + +Slack : 1.252 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.242 +Data Delay : 3.767 + +Slack : 1.252 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.232 +Data Delay : 3.757 + +Slack : 1.253 +From Node : ula:ula_|video:video_|vram_address[3] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.256 +Data Delay : 3.782 + +Slack : 1.254 +From Node : ula:ula_|video:video_|vram_address[6] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.242 +Data Delay : 3.769 + +Slack : 1.255 +From Node : ula:ula_|video:video_|vram_address[6] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.244 +Data Delay : 3.772 + +Slack : 1.256 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.235 +Data Delay : 3.764 + +Slack : 1.258 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.232 +Data Delay : 3.763 + +Slack : 1.260 +From Node : ula:ula_|video:video_|vram_address[9] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.242 +Data Delay : 3.775 Slack : 1.264 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : ula:ula_|video:video_|vga_hc[9] +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.059 -Data Delay : 1.467 +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.240 +Data Delay : 3.777 -Slack : 1.268 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|vram_address[6] +Slack : 1.265 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.474 +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.250 +Data Delay : 3.788 + +Slack : 1.267 +From Node : ula:ula_|video:video_|vram_address[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.244 +Data Delay : 3.784 + +Slack : 1.269 +From Node : ula:ula_|video:video_|vram_address[6] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.232 +Data Delay : 3.774 + +Slack : 1.271 +From Node : ula:ula_|video:video_|vram_address[6] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.237 +Data Delay : 3.781 + +Slack : 1.273 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.237 +Data Delay : 3.783 + +Slack : 1.276 +From Node : ula:ula_|video:video_|vram_address[2] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.240 +Data Delay : 3.789 Slack : 1.277 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.059 -Data Delay : 1.480 +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.077 +Data Delay : 3.627 + +Slack : 1.278 +From Node : ula:ula_|video:video_|vram_address[9] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.244 +Data Delay : 3.795 Slack : 1.279 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : ula:ula_|video:video_|vram_address[7] +From Node : ula:ula_|video:video_|vram_address[11] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.485 +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.248 +Data Delay : 3.800 + +Slack : 1.280 +From Node : ula:ula_|video:video_|vram_address[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.247 +Data Delay : 3.800 + +Slack : 1.280 +From Node : ula:ula_|video:video_|vram_address[9] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.248 +Data Delay : 3.801 + +Slack : 1.282 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.333 +Data Delay : 3.888 + +Slack : 1.283 +From Node : ula:ula_|video:video_|vram_address[11] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.239 +Data Delay : 3.795 + +Slack : 1.284 +From Node : ula:ula_|video:video_|vram_address[4] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.247 +Data Delay : 3.804 + +Slack : 1.286 +From Node : ula:ula_|video:video_|vram_address[6] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.236 +Data Delay : 3.795 + +Slack : 1.287 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.244 +Data Delay : 3.804 + +Slack : 1.287 +From Node : ula:ula_|video:video_|vram_address[3] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.250 +Data Delay : 3.810 + +Slack : 1.288 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.240 +Data Delay : 3.801 + +Slack : 1.291 +From Node : ula:ula_|video:video_|vram_address[6] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.232 +Data Delay : 3.796 + +Slack : 1.292 +From Node : ula:ula_|video:video_|vram_address[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.240 +Data Delay : 3.805 + +Slack : 1.292 +From Node : ula:ula_|video:video_|vram_address[2] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.235 +Data Delay : 3.800 + +Slack : 1.293 +From Node : ula:ula_|video:video_|vram_address[2] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.232 +Data Delay : 3.798 + +Slack : 1.294 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.319 +Data Delay : 3.886 + +Slack : 1.294 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.244 +Data Delay : 3.811 + +Slack : 1.295 +From Node : ula:ula_|video:video_|vram_address[2] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.236 +Data Delay : 3.804 + +Slack : 1.297 +From Node : ula:ula_|video:video_|vram_address[3] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.248 +Data Delay : 3.818 + +Slack : 1.300 +From Node : ula:ula_|video:video_|vram_address[8] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.250 +Data Delay : 3.823 + +Slack : 1.301 +From Node : ula:ula_|video:video_|vram_address[9] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.232 +Data Delay : 3.806 + +Slack : 1.303 +From Node : ula:ula_|video:video_|vram_address[6] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.248 +Data Delay : 3.824 + +Slack : 1.304 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.313 +Data Delay : 3.890 + +Slack : 1.305 +From Node : ula:ula_|video:video_|vram_address[3] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.247 +Data Delay : 3.825 + +Slack : 1.306 +From Node : ula:ula_|video:video_|vram_address[9] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.232 +Data Delay : 3.811 + +Slack : 1.307 +From Node : ula:ula_|video:video_|vram_address[9] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.236 +Data Delay : 3.816 + +Slack : 1.307 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.232 +Data Delay : 3.812 + +Slack : 1.308 +From Node : ula:ula_|video:video_|vram_address[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.240 +Data Delay : 3.821 + +Slack : 1.309 +From Node : ula:ula_|video:video_|vram_address[5] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.256 +Data Delay : 3.838 + +Slack : 1.310 +From Node : ula:ula_|video:video_|vram_address[8] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.247 +Data Delay : 3.830 + +Slack : 1.310 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.253 +Data Delay : 3.836 + +Slack : 1.311 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.247 +Data Delay : 3.831 + +Slack : 1.311 +From Node : ula:ula_|video:video_|vram_address[2] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.232 +Data Delay : 3.816 + +Slack : 1.311 +From Node : ula:ula_|video:video_|vram_address[3] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.240 +Data Delay : 3.824 + +Slack : 1.312 +From Node : ula:ula_|video:video_|vram_address[6] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.244 +Data Delay : 3.829 + +Slack : 1.313 +From Node : ula:ula_|video:video_|vram_address[9] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.237 +Data Delay : 3.823 + +Slack : 1.313 +From Node : ula:ula_|video:video_|vram_address[6] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.253 +Data Delay : 3.839 + +Slack : 1.313 +From Node : ula:ula_|video:video_|vram_address[3] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.240 +Data Delay : 3.826 + +Slack : 1.314 +From Node : ula:ula_|video:video_|vram_address[11] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.256 +Data Delay : 3.843 + +Slack : 1.314 +From Node : ula:ula_|video:video_|vram_address[2] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.253 +Data Delay : 3.840 + +Slack : 1.315 +From Node : ula:ula_|video:video_|vram_address[11] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.242 +Data Delay : 3.830 + +Slack : 1.315 +From Node : ula:ula_|video:video_|vram_address[4] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.232 +Data Delay : 3.820 + +Slack : 1.315 +From Node : ula:ula_|video:video_|vram_address[4] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.240 +Data Delay : 3.828 + +Slack : 1.315 +From Node : ula:ula_|video:video_|vram_address[4] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.240 +Data Delay : 3.828 + +Slack : 1.316 +From Node : ula:ula_|video:video_|vram_address[6] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.240 +Data Delay : 3.829 + +Slack : 1.317 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.052 +Data Delay : 3.642 + +Slack : 1.317 +From Node : ula:ula_|video:video_|vram_address[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.244 +Data Delay : 3.834 + +Slack : 1.317 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.232 +Data Delay : 3.822 + +Slack : 1.318 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.240 +Data Delay : 3.831 + +Slack : 1.318 +From Node : ula:ula_|video:video_|vram_address[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.248 +Data Delay : 3.839 Slack : 1.320 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|attr_prefetch[1] +From Node : ula:ula_|video:video_|vram_address[11] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.422 -Data Delay : 1.886 - -Slack : 1.320 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|attr_prefetch[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.422 -Data Delay : 1.886 - -Slack : 1.320 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|attr_prefetch[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.422 -Data Delay : 1.886 - -Slack : 1.320 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|attr_prefetch[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.422 -Data Delay : 1.886 - -Slack : 1.320 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|attr_prefetch[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.422 -Data Delay : 1.886 - -Slack : 1.320 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|attr_prefetch[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.422 -Data Delay : 1.886 - -Slack : 1.320 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|attr_prefetch[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.422 -Data Delay : 1.886 - -Slack : 1.320 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|attr_prefetch[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.422 -Data Delay : 1.886 - -Slack : 1.339 -From Node : ula:ula_|video:video_|vga_vc[0] -To Node : ula:ula_|video:video_|vram_address[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.545 - -Slack : 1.345 -From Node : ula:ula_|video:video_|vga_hc[8] -To Node : ula:ula_|video:video_|vga_hc[9] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.059 -Data Delay : 1.548 - -Slack : 1.349 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|bits_prefetch[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.394 -Data Delay : 1.887 - -Slack : 1.349 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|bits_prefetch[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.394 -Data Delay : 1.887 - -Slack : 1.349 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|bits_prefetch[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.394 -Data Delay : 1.887 - -Slack : 1.349 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|bits_prefetch[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.394 -Data Delay : 1.887 - -Slack : 1.349 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|bits_prefetch[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.394 -Data Delay : 1.887 - -Slack : 1.349 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|bits_prefetch[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.394 -Data Delay : 1.887 - -Slack : 1.349 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|bits_prefetch[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.394 -Data Delay : 1.887 - -Slack : 1.349 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|bits_prefetch[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.394 -Data Delay : 1.887 - -Slack : 1.357 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|vram_address[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.563 - -Slack : 1.362 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|vga_hc[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 1.562 +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 2.244 +Data Delay : 3.837 +--------------------------------------------------------------------------------+ @@ -16333,554 +16333,689 @@ Data Delay : 1.562 +--------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Recovery: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ; +--------------------------------------------------------------------------------+ -Slack : -5.744 +Slack : -5.773 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[17] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.088 -Data Delay : 3.943 +Data Delay : 3.972 -Slack : -5.744 +Slack : -5.773 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.090 -Data Delay : 3.941 +Data Delay : 3.970 -Slack : -5.744 +Slack : -5.773 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_1 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.091 -Data Delay : 3.940 +Data Delay : 3.969 -Slack : -5.743 +Slack : -5.772 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.091 -Data Delay : 3.939 +Data Delay : 3.968 -Slack : -5.743 +Slack : -5.772 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.092 -Data Delay : 3.938 +Data Delay : 3.967 -Slack : -5.507 +Slack : -5.536 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.115 -Data Delay : 3.681 +Data Delay : 3.710 -Slack : -5.494 +Slack : -5.523 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.116 -Data Delay : 3.667 +Data Delay : 3.696 -Slack : -5.257 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.087 -Data Delay : 3.549 - -Slack : -5.257 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.087 -Data Delay : 3.549 - -Slack : -5.257 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.087 -Data Delay : 3.549 - -Slack : -5.257 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.087 -Data Delay : 3.549 - -Slack : -5.257 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.087 -Data Delay : 3.549 - -Slack : -5.257 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.088 -Data Delay : 3.548 - -Slack : -5.257 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.088 -Data Delay : 3.548 - -Slack : -5.257 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.087 -Data Delay : 3.549 - -Slack : -5.257 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.087 -Data Delay : 3.549 - -Slack : -5.256 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.090 -Data Delay : 3.545 - -Slack : -5.256 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.090 -Data Delay : 3.545 - -Slack : -5.256 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.090 -Data Delay : 3.545 - -Slack : -5.256 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.090 -Data Delay : 3.545 - -Slack : -5.256 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.090 -Data Delay : 3.545 - -Slack : -5.256 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.091 -Data Delay : 3.544 - -Slack : -5.256 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.090 -Data Delay : 3.545 - -Slack : -5.256 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.091 -Data Delay : 3.544 - -Slack : -5.256 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.090 -Data Delay : 3.545 - -Slack : -5.256 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.090 -Data Delay : 3.545 - -Slack : -5.256 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.090 -Data Delay : 3.545 - -Slack : -5.256 +Slack : -5.286 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.088 -Data Delay : 3.547 +Data Delay : 3.577 -Slack : -5.256 +Slack : -5.286 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.088 -Data Delay : 3.547 +Data Delay : 3.577 -Slack : -5.256 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.087 -Data Delay : 3.548 - -Slack : -5.256 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.087 -Data Delay : 3.548 - -Slack : -5.256 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.087 -Data Delay : 3.548 - -Slack : -5.256 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.087 -Data Delay : 3.548 - -Slack : -5.256 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.087 -Data Delay : 3.548 - -Slack : -5.256 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.087 -Data Delay : 3.548 - -Slack : -5.256 +Slack : -5.286 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.087 -Data Delay : 3.548 +Data Delay : 3.578 -Slack : -5.256 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.087 -Data Delay : 3.548 - -Slack : -5.256 +Slack : -5.286 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.087 -Data Delay : 3.548 +Data Delay : 3.578 -Slack : -5.256 +Slack : -5.286 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.087 +Data Delay : 3.578 + +Slack : -5.286 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.087 +Data Delay : 3.578 + +Slack : -5.286 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.085 +Data Delay : 3.580 + +Slack : -5.286 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.085 +Data Delay : 3.580 + +Slack : -5.286 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.085 +Data Delay : 3.580 + +Slack : -5.286 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.085 +Data Delay : 3.580 + +Slack : -5.286 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.085 +Data Delay : 3.580 + +Slack : -5.286 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.085 +Data Delay : 3.580 + +Slack : -5.286 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.085 +Data Delay : 3.580 + +Slack : -5.286 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.085 +Data Delay : 3.580 + +Slack : -5.286 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.085 +Data Delay : 3.580 + +Slack : -5.286 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.085 +Data Delay : 3.580 + +Slack : -5.286 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.085 +Data Delay : 3.580 + +Slack : -5.286 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.085 +Data Delay : 3.580 + +Slack : -5.286 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.085 +Data Delay : 3.580 + +Slack : -5.286 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.085 +Data Delay : 3.580 + +Slack : -5.286 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.085 +Data Delay : 3.580 + +Slack : -5.285 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.084 +Data Delay : 3.580 + +Slack : -5.285 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.084 +Data Delay : 3.580 + +Slack : -5.285 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.084 +Data Delay : 3.580 + +Slack : -5.285 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.084 +Data Delay : 3.580 + +Slack : -5.285 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.084 +Data Delay : 3.580 + +Slack : -5.285 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.084 +Data Delay : 3.580 + +Slack : -5.285 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.084 +Data Delay : 3.580 + +Slack : -5.285 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.084 +Data Delay : 3.580 + +Slack : -5.285 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.084 +Data Delay : 3.580 + +Slack : -5.285 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.084 +Data Delay : 3.580 + +Slack : -5.285 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.084 +Data Delay : 3.580 + +Slack : -5.285 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.084 +Data Delay : 3.580 + +Slack : -5.285 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.087 +Data Delay : 3.577 + +Slack : -5.285 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.087 +Data Delay : 3.577 + +Slack : -5.285 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.087 +Data Delay : 3.577 + +Slack : -5.285 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.087 +Data Delay : 3.577 + +Slack : -5.285 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.087 +Data Delay : 3.577 + +Slack : -5.285 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.087 +Data Delay : 3.577 + +Slack : -5.285 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.087 -Data Delay : 3.548 +Data Delay : 3.577 -Slack : -5.256 +Slack : -5.285 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.087 -Data Delay : 3.548 +Data Delay : 3.577 -Slack : -5.256 +Slack : -5.285 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.087 -Data Delay : 3.548 +Data Delay : 3.577 -Slack : -5.256 +Slack : -5.285 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.087 -Data Delay : 3.548 +Data Delay : 3.577 -Slack : -5.256 +Slack : -5.285 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.087 -Data Delay : 3.548 +Data Delay : 3.577 -Slack : -5.256 +Slack : -5.285 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.087 +Data Delay : 3.577 + +Slack : -5.285 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.087 -Data Delay : 3.548 +Data Delay : 3.577 -Slack : -5.256 +Slack : -5.285 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.087 -Data Delay : 3.548 +Data Delay : 3.577 -Slack : -5.256 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.091 -Data Delay : 3.544 - -Slack : -5.256 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.091 -Data Delay : 3.544 - -Slack : -5.256 +Slack : -5.285 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.091 -Data Delay : 3.544 +Clock Skew : -0.084 +Data Delay : 3.580 -Slack : -5.256 +Slack : -5.285 From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.089 -Data Delay : 3.546 +Clock Skew : -0.084 +Data Delay : 3.580 -Slack : -4.963 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.208 -Data Delay : 3.550 - -Slack : -4.959 +Slack : -4.988 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.421 -Clock Skew : 0.212 -Data Delay : 3.547 +Clock Skew : 0.213 +Data Delay : 3.577 -Slack : -4.959 +Slack : -4.988 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.421 -Clock Skew : 0.212 -Data Delay : 3.547 +Clock Skew : 0.213 +Data Delay : 3.577 -Slack : -4.959 +Slack : -4.988 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.421 -Clock Skew : 0.212 -Data Delay : 3.547 +Clock Skew : 0.213 +Data Delay : 3.577 -Slack : -4.959 +Slack : -4.988 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.421 -Clock Skew : 0.212 -Data Delay : 3.547 +Clock Skew : 0.213 +Data Delay : 3.577 -Slack : -4.959 +Slack : -4.988 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.421 -Clock Skew : 0.212 -Data Delay : 3.547 +Clock Skew : 0.213 +Data Delay : 3.577 -Slack : -4.959 +Slack : -4.988 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.421 -Clock Skew : 0.212 -Data Delay : 3.547 +Clock Skew : 0.213 +Data Delay : 3.577 -Slack : -4.941 +Slack : -4.969 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.229 +Data Delay : 3.577 + +Slack : -4.969 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.229 +Data Delay : 3.577 + +Slack : -4.969 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.229 +Data Delay : 3.577 + +Slack : -4.969 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.229 +Data Delay : 3.577 + +Slack : -4.969 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.229 +Data Delay : 3.577 + +Slack : -4.967 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.234 +Data Delay : 3.580 + +Slack : -4.966 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.232 +Data Delay : 3.577 + +Slack : -4.966 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.232 +Data Delay : 3.577 + +Slack : -4.965 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.233 +Data Delay : 3.577 + +Slack : -4.949 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.223 -Data Delay : 3.543 +Clock Skew : 0.253 +Data Delay : 3.581 -Slack : -4.941 +Slack : -4.949 From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.223 -Data Delay : 3.543 +Clock Skew : 0.253 +Data Delay : 3.581 -Slack : -4.941 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.223 -Data Delay : 3.543 - -Slack : -4.941 +Slack : -4.949 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.223 -Data Delay : 3.543 +Clock Skew : 0.253 +Data Delay : 3.581 -Slack : -4.941 +Slack : -4.949 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.223 -Data Delay : 3.543 +Clock Skew : 0.253 +Data Delay : 3.581 + +Slack : -4.949 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.252 +Data Delay : 3.580 Slack : -4.940 From Node : KEY[0] @@ -16888,8 +17023,8 @@ To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.223 -Data Delay : 3.542 +Clock Skew : 0.261 +Data Delay : 3.580 Slack : -4.940 From Node : KEY[0] @@ -16897,8 +17032,17 @@ To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.223 -Data Delay : 3.542 +Clock Skew : 0.261 +Data Delay : 3.580 + +Slack : -4.940 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : 0.261 +Data Delay : 3.580 Slack : -4.940 From Node : KEY[0] @@ -16906,8 +17050,8 @@ To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.223 -Data Delay : 3.542 +Clock Skew : 0.261 +Data Delay : 3.580 Slack : -4.940 From Node : KEY[0] @@ -16915,161 +17059,17 @@ To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.223 -Data Delay : 3.542 +Clock Skew : 0.261 +Data Delay : 3.580 Slack : -4.940 From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : 0.223 -Data Delay : 3.542 - -Slack : -4.940 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.227 -Data Delay : 3.546 - -Slack : -4.936 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.232 -Data Delay : 3.547 - -Slack : -4.936 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.235 -Data Delay : 3.550 - -Slack : -4.936 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.235 -Data Delay : 3.550 - -Slack : -4.936 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.235 -Data Delay : 3.550 - -Slack : -4.936 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.235 -Data Delay : 3.550 - -Slack : -4.936 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.235 -Data Delay : 3.550 - -Slack : -4.936 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.235 -Data Delay : 3.550 - -Slack : -4.936 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.235 -Data Delay : 3.550 - -Slack : -4.936 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.235 -Data Delay : 3.550 - -Slack : -4.936 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.235 -Data Delay : 3.550 - -Slack : -4.936 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.235 -Data Delay : 3.550 - -Slack : -4.936 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.235 -Data Delay : 3.550 - -Slack : -4.936 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.235 -Data Delay : 3.550 - -Slack : -4.936 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.235 -Data Delay : 3.550 - -Slack : -4.936 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : 0.235 -Data Delay : 3.550 +Clock Skew : 0.261 +Data Delay : 3.580 +--------------------------------------------------------------------------------+ @@ -17077,455 +17077,518 @@ Data Delay : 3.550 +--------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Removal: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ; +--------------------------------------------------------------------------------+ -Slack : 3.374 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.603 -Data Delay : 3.205 - -Slack : 3.374 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.607 -Data Delay : 3.209 - -Slack : 3.374 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.607 -Data Delay : 3.209 - -Slack : 3.374 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.607 -Data Delay : 3.209 - -Slack : 3.374 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.607 -Data Delay : 3.209 - -Slack : 3.374 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.607 -Data Delay : 3.209 - -Slack : 3.374 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.607 -Data Delay : 3.209 - -Slack : 3.374 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.607 -Data Delay : 3.209 - -Slack : 3.374 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.607 -Data Delay : 3.209 - -Slack : 3.374 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.607 -Data Delay : 3.209 - -Slack : 3.374 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.607 -Data Delay : 3.209 - -Slack : 3.374 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.607 -Data Delay : 3.209 - -Slack : 3.374 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.607 -Data Delay : 3.209 - -Slack : 3.374 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.607 -Data Delay : 3.209 - -Slack : 3.374 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.607 -Data Delay : 3.209 - -Slack : 3.378 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.599 -Data Delay : 3.205 - -Slack : 3.380 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.595 -Data Delay : 3.203 - -Slack : 3.381 +Slack : 3.347 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.594 -Data Delay : 3.203 +Clock Skew : 0.634 +Data Delay : 3.209 -Slack : 3.381 +Slack : 3.347 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.594 -Data Delay : 3.203 +Clock Skew : 0.634 +Data Delay : 3.209 -Slack : 3.381 +Slack : 3.347 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.594 -Data Delay : 3.203 +Clock Skew : 0.634 +Data Delay : 3.209 -Slack : 3.381 +Slack : 3.347 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.594 -Data Delay : 3.203 +Clock Skew : 0.634 +Data Delay : 3.209 -Slack : 3.381 +Slack : 3.347 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.594 -Data Delay : 3.203 +Clock Skew : 0.634 +Data Delay : 3.209 -Slack : 3.381 +Slack : 3.347 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.594 -Data Delay : 3.203 +Clock Skew : 0.634 +Data Delay : 3.209 -Slack : 3.381 +Slack : 3.356 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.626 +Data Delay : 3.210 + +Slack : 3.356 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.594 -Data Delay : 3.203 +Clock Skew : 0.626 +Data Delay : 3.210 -Slack : 3.381 +Slack : 3.356 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.594 -Data Delay : 3.203 +Clock Skew : 0.626 +Data Delay : 3.210 -Slack : 3.381 +Slack : 3.356 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.594 -Data Delay : 3.203 +Clock Skew : 0.626 +Data Delay : 3.210 -Slack : 3.391 +Slack : 3.356 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.003 -Clock Skew : 0.583 -Data Delay : 3.205 - -Slack : 3.391 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.003 -Clock Skew : 0.583 -Data Delay : 3.205 - -Slack : 3.391 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.003 -Clock Skew : 0.583 -Data Delay : 3.205 - -Slack : 3.391 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.003 -Clock Skew : 0.583 -Data Delay : 3.205 - -Slack : 3.391 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.003 -Clock Skew : 0.583 -Data Delay : 3.205 - -Slack : 3.391 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.003 -Clock Skew : 0.583 -Data Delay : 3.205 - -Slack : 3.403 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.578 +Clock Skew : 0.625 Data Delay : 3.209 -Slack : 3.707 +Slack : 3.372 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.270 +Clock Skew : 0.605 Data Delay : 3.205 -Slack : 3.707 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.270 -Data Delay : 3.205 - -Slack : 3.707 +Slack : 3.375 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.271 -Data Delay : 3.206 +Clock Skew : 0.604 +Data Delay : 3.207 -Slack : 3.707 +Slack : 3.375 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.271 -Data Delay : 3.206 +Clock Skew : 0.604 +Data Delay : 3.207 -Slack : 3.707 +Slack : 3.375 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.606 +Data Delay : 3.209 + +Slack : 3.379 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.600 +Data Delay : 3.207 + +Slack : 3.379 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.600 +Data Delay : 3.207 + +Slack : 3.379 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.600 +Data Delay : 3.207 + +Slack : 3.379 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.600 +Data Delay : 3.207 + +Slack : 3.379 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.600 +Data Delay : 3.207 + +Slack : 3.390 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.003 +Clock Skew : 0.584 +Data Delay : 3.205 + +Slack : 3.390 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.003 +Clock Skew : 0.584 +Data Delay : 3.205 + +Slack : 3.390 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.003 +Clock Skew : 0.584 +Data Delay : 3.205 + +Slack : 3.390 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.003 +Clock Skew : 0.584 +Data Delay : 3.205 + +Slack : 3.390 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.003 +Clock Skew : 0.584 +Data Delay : 3.205 + +Slack : 3.390 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.003 +Clock Skew : 0.584 +Data Delay : 3.205 + +Slack : 3.706 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.271 -Data Delay : 3.206 +Data Delay : 3.205 -Slack : 3.707 +Slack : 3.706 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.271 -Data Delay : 3.206 +Data Delay : 3.205 Slack : 3.707 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.271 -Data Delay : 3.206 +Clock Skew : 0.274 +Data Delay : 3.209 Slack : 3.707 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.271 -Data Delay : 3.206 - -Slack : 3.708 -From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.268 -Data Delay : 3.204 +Clock Skew : 0.274 +Data Delay : 3.209 -Slack : 3.708 +Slack : 3.707 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.268 -Data Delay : 3.204 +Clock Skew : 0.274 +Data Delay : 3.209 -Slack : 3.708 +Slack : 3.707 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.268 -Data Delay : 3.204 +Clock Skew : 0.274 +Data Delay : 3.209 -Slack : 3.708 +Slack : 3.707 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.268 -Data Delay : 3.204 +Clock Skew : 0.274 +Data Delay : 3.209 -Slack : 3.708 +Slack : 3.707 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.268 -Data Delay : 3.204 +Clock Skew : 0.274 +Data Delay : 3.209 -Slack : 3.708 +Slack : 3.707 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.274 +Data Delay : 3.209 + +Slack : 3.707 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.268 -Data Delay : 3.204 +Clock Skew : 0.274 +Data Delay : 3.209 -Slack : 3.708 +Slack : 3.707 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.274 +Data Delay : 3.209 + +Slack : 3.707 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.268 -Data Delay : 3.204 +Clock Skew : 0.274 +Data Delay : 3.209 -Slack : 3.708 +Slack : 3.707 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.268 -Data Delay : 3.204 +Clock Skew : 0.274 +Data Delay : 3.209 -Slack : 3.708 +Slack : 3.707 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.268 -Data Delay : 3.204 +Clock Skew : 0.274 +Data Delay : 3.209 + +Slack : 3.707 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.274 +Data Delay : 3.209 + +Slack : 3.707 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.274 +Data Delay : 3.209 + +Slack : 3.707 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.274 +Data Delay : 3.209 + +Slack : 3.707 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.274 +Data Delay : 3.209 + +Slack : 3.707 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.274 +Data Delay : 3.209 + +Slack : 3.707 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.274 +Data Delay : 3.209 + +Slack : 3.707 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.274 +Data Delay : 3.209 + +Slack : 3.707 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.274 +Data Delay : 3.209 + +Slack : 3.707 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.274 +Data Delay : 3.209 + +Slack : 3.707 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.274 +Data Delay : 3.209 + +Slack : 3.707 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.274 +Data Delay : 3.209 + +Slack : 3.707 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.274 +Data Delay : 3.209 + +Slack : 3.707 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.274 +Data Delay : 3.209 + +Slack : 3.707 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.274 +Data Delay : 3.209 + +Slack : 3.707 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.274 +Data Delay : 3.209 + +Slack : 3.707 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.274 +Data Delay : 3.209 + +Slack : 3.707 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.274 +Data Delay : 3.209 Slack : 3.708 From Node : KEY[0] @@ -17533,8 +17596,8 @@ To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.272 -Data Delay : 3.208 +Clock Skew : 0.271 +Data Delay : 3.207 Slack : 3.708 From Node : KEY[0] @@ -17542,8 +17605,8 @@ To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.272 -Data Delay : 3.208 +Clock Skew : 0.271 +Data Delay : 3.207 Slack : 3.708 From Node : KEY[0] @@ -17551,8 +17614,8 @@ To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.272 -Data Delay : 3.208 +Clock Skew : 0.271 +Data Delay : 3.207 Slack : 3.708 From Node : KEY[0] @@ -17560,8 +17623,8 @@ To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.272 -Data Delay : 3.208 +Clock Skew : 0.271 +Data Delay : 3.207 Slack : 3.708 From Node : KEY[0] @@ -17569,9 +17632,108 @@ To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 +Clock Skew : 0.271 +Data Delay : 3.207 + +Slack : 3.708 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 Clock Skew : 0.272 Data Delay : 3.208 +Slack : 3.708 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.271 +Data Delay : 3.207 + +Slack : 3.708 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.272 +Data Delay : 3.208 + +Slack : 3.708 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.271 +Data Delay : 3.207 + +Slack : 3.708 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.271 +Data Delay : 3.207 + +Slack : 3.708 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.271 +Data Delay : 3.207 + +Slack : 3.708 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.271 +Data Delay : 3.207 + +Slack : 3.708 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.271 +Data Delay : 3.207 + +Slack : 3.708 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.271 +Data Delay : 3.207 + +Slack : 3.708 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.271 +Data Delay : 3.207 + +Slack : 3.708 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.271 +Data Delay : 3.207 + Slack : 3.708 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 @@ -17590,168 +17752,6 @@ Relationship : -0.006 Clock Skew : 0.272 Data Delay : 3.208 -Slack : 3.708 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.269 -Data Delay : 3.205 - -Slack : 3.709 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.267 -Data Delay : 3.204 - -Slack : 3.709 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.267 -Data Delay : 3.204 - -Slack : 3.709 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.271 -Data Delay : 3.208 - -Slack : 3.709 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.271 -Data Delay : 3.208 - -Slack : 3.709 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.271 -Data Delay : 3.208 - -Slack : 3.709 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.271 -Data Delay : 3.208 - -Slack : 3.709 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.271 -Data Delay : 3.208 - -Slack : 3.709 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.271 -Data Delay : 3.208 - -Slack : 3.709 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.271 -Data Delay : 3.208 - -Slack : 3.709 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.271 -Data Delay : 3.208 - -Slack : 3.709 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.271 -Data Delay : 3.208 - -Slack : 3.709 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.271 -Data Delay : 3.208 - -Slack : 3.709 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.271 -Data Delay : 3.208 - -Slack : 3.709 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.271 -Data Delay : 3.208 - -Slack : 3.709 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.267 -Data Delay : 3.204 - -Slack : 3.709 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.267 -Data Delay : 3.204 - -Slack : 3.709 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.267 -Data Delay : 3.204 - Slack : 3.895 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out @@ -17761,14 +17761,14 @@ Relationship : -0.006 Clock Skew : 0.226 Data Delay : 3.294 -Slack : 3.909 +Slack : 3.908 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.227 -Data Delay : 3.309 +Data Delay : 3.308 Slack : 4.117 From Node : KEY[0] @@ -17788,6 +17788,15 @@ Relationship : -0.006 Clock Skew : 0.252 Data Delay : 3.539 +Slack : 4.117 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.250 +Data Delay : 3.537 + Slack : 4.117 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_1 @@ -17805,15 +17814,6 @@ Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.250 Data Delay : 3.537 - -Slack : 4.118 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.250 -Data Delay : 3.538 +--------------------------------------------------------------------------------+ @@ -17859,7 +17859,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_address_reg0 Slack : 9.489 Actual Width : 9.719 @@ -17867,7 +17867,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_we_reg +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_we_reg Slack : 9.489 Actual Width : 9.719 @@ -17875,7 +17875,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_address_reg0 Slack : 9.489 Actual Width : 9.719 @@ -17883,7 +17883,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_we_reg +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_we_reg Slack : 9.489 Actual Width : 9.719 @@ -17891,7 +17891,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_address_reg0 Slack : 9.489 Actual Width : 9.719 @@ -17899,7 +17899,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_we_reg Slack : 9.490 Actual Width : 9.720 @@ -17917,6 +17917,22 @@ Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_we_reg +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_address_reg0 + +Slack : 9.490 +Actual Width : 9.720 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_we_reg + Slack : 9.490 Actual Width : 9.720 Required Width : 0.230 @@ -17939,7 +17955,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_address_reg0 Slack : 9.490 Actual Width : 9.720 @@ -17947,39 +17963,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_we_reg - -Slack : 9.490 -Actual Width : 9.720 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_address_reg0 - -Slack : 9.490 -Actual Width : 9.720 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_we_reg - -Slack : 9.490 -Actual Width : 9.720 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_address_reg0 - -Slack : 9.490 -Actual Width : 9.720 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_we_reg +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_we_reg Slack : 9.490 Actual Width : 9.720 @@ -18035,7 +18019,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_address_reg0 Slack : 9.490 Actual Width : 9.720 @@ -18043,7 +18027,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_we_reg +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_we_reg Slack : 9.490 Actual Width : 9.720 @@ -18051,7 +18035,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_address_reg0 Slack : 9.490 Actual Width : 9.720 @@ -18059,55 +18043,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0 - -Slack : 9.490 -Actual Width : 9.720 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13~porta_address_reg0 - -Slack : 9.490 -Actual Width : 9.720 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 - -Slack : 9.490 -Actual Width : 9.720 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 - -Slack : 9.490 -Actual Width : 9.720 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5~porta_address_reg0 - -Slack : 9.490 -Actual Width : 9.720 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 - -Slack : 9.490 -Actual Width : 9.720 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_we_reg Slack : 9.491 Actual Width : 9.721 @@ -18131,7 +18067,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0 Slack : 9.491 Actual Width : 9.721 @@ -18139,7 +18075,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 Slack : 9.491 Actual Width : 9.721 @@ -18147,7 +18083,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_we_reg +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_address_reg0 Slack : 9.491 Actual Width : 9.721 @@ -18155,7 +18091,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_we_reg Slack : 9.491 Actual Width : 9.721 @@ -18163,7 +18099,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_we_reg +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0 Slack : 9.491 Actual Width : 9.721 @@ -18171,7 +18107,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_datain_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_address_reg0 Slack : 9.491 Actual Width : 9.721 @@ -18179,55 +18115,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_address_reg0 - -Slack : 9.491 -Actual Width : 9.721 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_we_reg - -Slack : 9.491 -Actual Width : 9.721 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0 - -Slack : 9.491 -Actual Width : 9.721 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0 - -Slack : 9.491 -Actual Width : 9.721 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1~porta_address_reg0 - -Slack : 9.491 -Actual Width : 9.721 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2~porta_address_reg0 - -Slack : 9.491 -Actual Width : 9.721 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_we_reg Slack : 9.492 Actual Width : 9.722 @@ -18237,6 +18125,14 @@ Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 +Slack : 9.492 +Actual Width : 9.722 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0 + Slack : 9.492 Actual Width : 9.722 Required Width : 0.230 @@ -18251,23 +18147,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0 - -Slack : 9.492 -Actual Width : 9.722 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 - -Slack : 9.492 -Actual Width : 9.722 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 Slack : 9.492 Actual Width : 9.722 @@ -18299,7 +18179,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_datain_reg0 Slack : 9.492 Actual Width : 9.722 @@ -18307,30 +18187,6 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 - -Slack : 9.493 -Actual Width : 9.723 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0 - -Slack : 9.493 -Actual Width : 9.723 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 - -Slack : 9.493 -Actual Width : 9.723 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0 Slack : 9.493 @@ -18339,7 +18195,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 Slack : 9.493 Actual Width : 9.723 @@ -18347,119 +18203,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 - -Slack : 9.494 -Actual Width : 9.724 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 - -Slack : 9.494 -Actual Width : 9.724 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 - -Slack : 9.494 -Actual Width : 9.724 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 - -Slack : 9.494 -Actual Width : 9.724 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 - -Slack : 9.494 -Actual Width : 9.724 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 - -Slack : 9.494 -Actual Width : 9.724 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 - -Slack : 9.494 -Actual Width : 9.724 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 - -Slack : 9.494 -Actual Width : 9.724 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 - -Slack : 9.495 -Actual Width : 9.725 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 - -Slack : 9.495 -Actual Width : 9.725 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 - -Slack : 9.495 -Actual Width : 9.725 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 - -Slack : 9.495 -Actual Width : 9.725 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2 - -Slack : 9.495 -Actual Width : 9.725 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 - -Slack : 9.496 -Actual Width : 9.726 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0 Slack : 9.497 Actual Width : 9.727 @@ -18483,7 +18227,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14 Slack : 9.497 Actual Width : 9.727 @@ -18491,7 +18235,15 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15 + +Slack : 9.497 +Actual Width : 9.727 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2 Slack : 9.498 Actual Width : 9.728 @@ -18509,14 +18261,6 @@ Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 -Slack : 9.498 -Actual Width : 9.728 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1 - Slack : 9.498 Actual Width : 9.728 Required Width : 0.230 @@ -18539,7 +18283,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 Slack : 9.498 Actual Width : 9.728 @@ -18555,7 +18299,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 Slack : 9.498 Actual Width : 9.728 @@ -18563,7 +18307,31 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 + +Slack : 9.498 +Actual Width : 9.728 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~PORTBDATAOUT0 + +Slack : 9.498 +Actual Width : 9.728 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 + +Slack : 9.498 +Actual Width : 9.728 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3 Slack : 9.498 Actual Width : 9.728 @@ -18595,7 +18363,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 Slack : 9.498 Actual Width : 9.728 @@ -18603,7 +18371,15 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9 + +Slack : 9.499 +Actual Width : 9.729 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1 Slack : 9.499 Actual Width : 9.729 @@ -18613,6 +18389,14 @@ Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 +Slack : 9.499 +Actual Width : 9.729 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 + Slack : 9.499 Actual Width : 9.729 Required Width : 0.230 @@ -18620,6 +18404,222 @@ Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 + +Slack : 9.499 +Actual Width : 9.729 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~PORTBDATAOUT0 + +Slack : 9.499 +Actual Width : 9.729 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 + +Slack : 9.499 +Actual Width : 9.729 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~PORTBDATAOUT0 + +Slack : 9.499 +Actual Width : 9.729 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 + +Slack : 9.499 +Actual Width : 9.729 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~PORTBDATAOUT0 + +Slack : 9.499 +Actual Width : 9.729 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 + +Slack : 9.499 +Actual Width : 9.729 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~PORTBDATAOUT0 + +Slack : 9.499 +Actual Width : 9.729 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 + +Slack : 9.499 +Actual Width : 9.729 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 + +Slack : 9.499 +Actual Width : 9.729 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 + +Slack : 9.499 +Actual Width : 9.729 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 + +Slack : 9.500 +Actual Width : 9.730 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~PORTBDATAOUT0 + +Slack : 9.500 +Actual Width : 9.730 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 + +Slack : 9.500 +Actual Width : 9.730 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~PORTBDATAOUT0 + +Slack : 9.500 +Actual Width : 9.730 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 + +Slack : 9.501 +Actual Width : 9.731 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_datain_reg0 + +Slack : 9.501 +Actual Width : 9.731 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_datain_reg0 + +Slack : 9.501 +Actual Width : 9.731 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_datain_reg0 + +Slack : 9.501 +Actual Width : 9.731 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_datain_reg0 + +Slack : 9.501 +Actual Width : 9.731 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_datain_reg0 + +Slack : 9.502 +Actual Width : 9.732 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_datain_reg0 + +Slack : 9.502 +Actual Width : 9.732 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_datain_reg0 + +Slack : 9.502 +Actual Width : 9.732 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_datain_reg0 + +Slack : 9.502 +Actual Width : 9.732 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_datain_reg0 + +Slack : 9.502 +Actual Width : 9.732 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_datain_reg0 + +Slack : 9.502 +Actual Width : 9.732 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_datain_reg0 + +Slack : 9.502 +Actual Width : 9.732 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_datain_reg0 +--------------------------------------------------------------------------------+ @@ -18627,245 +18627,37 @@ Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto +--------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' ; +--------------------------------------------------------------------------------+ -Slack : 19.600 -Actual Width : 19.816 +Slack : 19.601 +Actual Width : 19.817 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : ula:ula_|video:video_|VGA_HS~_Duplicate_1 -Slack : 19.600 -Actual Width : 19.816 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|VGA_VS~_Duplicate_1 - -Slack : 19.600 -Actual Width : 19.816 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|attr[0] - -Slack : 19.600 -Actual Width : 19.816 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|attr[1] - -Slack : 19.600 -Actual Width : 19.816 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|attr[4] - -Slack : 19.600 -Actual Width : 19.816 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|bits_prefetch[0] - -Slack : 19.600 -Actual Width : 19.816 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|bits_prefetch[1] - -Slack : 19.600 -Actual Width : 19.816 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|bits_prefetch[2] - -Slack : 19.600 -Actual Width : 19.816 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|bits_prefetch[3] - -Slack : 19.600 -Actual Width : 19.816 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|bits_prefetch[4] - -Slack : 19.600 -Actual Width : 19.816 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|bits_prefetch[5] - -Slack : 19.600 -Actual Width : 19.816 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|bits_prefetch[6] - -Slack : 19.600 -Actual Width : 19.816 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|bits_prefetch[7] - -Slack : 19.600 -Actual Width : 19.816 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|frame[0] - -Slack : 19.600 -Actual Width : 19.816 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vga_hc[2] - -Slack : 19.600 -Actual Width : 19.816 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vga_hc[4] - -Slack : 19.600 -Actual Width : 19.816 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vga_hc[5] - -Slack : 19.600 -Actual Width : 19.816 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vga_hc[6] - -Slack : 19.600 -Actual Width : 19.816 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vga_hc[7] - -Slack : 19.600 -Actual Width : 19.816 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vga_hc[8] - -Slack : 19.600 -Actual Width : 19.816 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vga_hc[9] - -Slack : 19.600 -Actual Width : 19.816 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vram_address[0] - -Slack : 19.600 -Actual Width : 19.816 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vram_address[1] - -Slack : 19.600 -Actual Width : 19.816 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vram_address[2] - -Slack : 19.600 -Actual Width : 19.816 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vram_address[3] - -Slack : 19.600 -Actual Width : 19.816 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vram_address[4] - -Slack : 19.600 -Actual Width : 19.816 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vram_address[5] - -Slack : 19.600 -Actual Width : 19.816 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vram_address[6] - -Slack : 19.600 -Actual Width : 19.816 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vram_address[7] - Slack : 19.601 Actual Width : 19.817 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +Target : ula:ula_|video:video_|VGA_VS~_Duplicate_1 + +Slack : 19.601 +Actual Width : 19.817 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|attr[0] + +Slack : 19.601 +Actual Width : 19.817 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|attr[1] Slack : 19.601 Actual Width : 19.817 @@ -18883,6 +18675,14 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : ula:ula_|video:video_|attr[3] +Slack : 19.601 +Actual Width : 19.817 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|attr[4] + Slack : 19.601 Actual Width : 19.817 Required Width : 0.216 @@ -18971,6 +18771,78 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : ula:ula_|video:video_|bits[7] +Slack : 19.601 +Actual Width : 19.817 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|bits_prefetch[0] + +Slack : 19.601 +Actual Width : 19.817 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|bits_prefetch[1] + +Slack : 19.601 +Actual Width : 19.817 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|bits_prefetch[2] + +Slack : 19.601 +Actual Width : 19.817 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|bits_prefetch[3] + +Slack : 19.601 +Actual Width : 19.817 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|bits_prefetch[4] + +Slack : 19.601 +Actual Width : 19.817 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|bits_prefetch[5] + +Slack : 19.601 +Actual Width : 19.817 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|bits_prefetch[6] + +Slack : 19.601 +Actual Width : 19.817 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|bits_prefetch[7] + +Slack : 19.601 +Actual Width : 19.817 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|frame[0] + Slack : 19.601 Actual Width : 19.817 Required Width : 0.216 @@ -19003,14 +18875,6 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : ula:ula_|video:video_|frame[4] -Slack : 19.601 -Actual Width : 19.817 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|vga_hc[0] - Slack : 19.601 Actual Width : 19.817 Required Width : 0.216 @@ -19019,6 +18883,14 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : ula:ula_|video:video_|vga_hc[1] +Slack : 19.601 +Actual Width : 19.817 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|vga_hc[2] + Slack : 19.601 Actual Width : 19.817 Required Width : 0.216 @@ -19027,6 +18899,54 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : ula:ula_|video:video_|vga_hc[3] +Slack : 19.601 +Actual Width : 19.817 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|vga_hc[4] + +Slack : 19.601 +Actual Width : 19.817 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|vga_hc[5] + +Slack : 19.601 +Actual Width : 19.817 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|vga_hc[6] + +Slack : 19.601 +Actual Width : 19.817 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|vga_hc[7] + +Slack : 19.601 +Actual Width : 19.817 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|vga_hc[8] + +Slack : 19.601 +Actual Width : 19.817 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|vga_hc[9] + Slack : 19.601 Actual Width : 19.817 Required Width : 0.216 @@ -19107,6 +19027,14 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : ula:ula_|video:video_|vga_vc[9] +Slack : 19.601 +Actual Width : 19.817 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|vram_address[0] + Slack : 19.601 Actual Width : 19.817 Required Width : 0.216 @@ -19131,6 +19059,62 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : ula:ula_|video:video_|vram_address[12] +Slack : 19.601 +Actual Width : 19.817 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|vram_address[1] + +Slack : 19.601 +Actual Width : 19.817 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|vram_address[2] + +Slack : 19.601 +Actual Width : 19.817 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|vram_address[3] + +Slack : 19.601 +Actual Width : 19.817 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|vram_address[4] + +Slack : 19.601 +Actual Width : 19.817 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|vram_address[5] + +Slack : 19.601 +Actual Width : 19.817 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|vram_address[6] + +Slack : 19.601 +Actual Width : 19.817 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|vram_address[7] + Slack : 19.601 Actual Width : 19.817 Required Width : 0.216 @@ -19169,7 +19153,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_address_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0 Slack : 19.603 Actual Width : 19.833 @@ -19177,7 +19161,15 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_we_reg +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_we_reg + +Slack : 19.603 +Actual Width : 19.819 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|vga_hc[0] Slack : 19.604 Actual Width : 19.820 @@ -19188,12 +19180,12 @@ Clock Edge : Rise Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[0] Slack : 19.604 -Actual Width : 19.834 -Required Width : 0.230 -Type : Low Pulse Width +Actual Width : 19.820 +Required Width : 0.216 +Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_address_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] Slack : 19.604 Actual Width : 19.834 @@ -19201,71 +19193,15 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_we_reg +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_address_reg0 Slack : 19.604 -Actual Width : 19.820 -Required Width : 0.216 -Type : High Pulse Width +Actual Width : 19.834 +Required Width : 0.230 +Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ula:ula_|video:video_|attr_prefetch[0] - -Slack : 19.604 -Actual Width : 19.820 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|attr_prefetch[1] - -Slack : 19.604 -Actual Width : 19.820 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|attr_prefetch[2] - -Slack : 19.604 -Actual Width : 19.820 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|attr_prefetch[3] - -Slack : 19.604 -Actual Width : 19.820 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|attr_prefetch[4] - -Slack : 19.604 -Actual Width : 19.820 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|attr_prefetch[5] - -Slack : 19.604 -Actual Width : 19.820 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|attr_prefetch[6] - -Slack : 19.604 -Actual Width : 19.820 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ula:ula_|video:video_|attr_prefetch[7] +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_we_reg Slack : 19.605 Actual Width : 19.835 @@ -19273,7 +19209,63 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_address_reg0 + +Slack : 19.605 +Actual Width : 19.835 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_we_reg + +Slack : 19.605 +Actual Width : 19.835 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_address_reg0 + +Slack : 19.605 +Actual Width : 19.835 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_we_reg + +Slack : 19.605 +Actual Width : 19.835 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_address_reg0 + +Slack : 19.605 +Actual Width : 19.835 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_we_reg + +Slack : 19.605 +Actual Width : 19.835 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_address_reg0 + +Slack : 19.605 +Actual Width : 19.835 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_we_reg Slack : 19.605 Actual Width : 19.835 @@ -19297,79 +19289,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_address_reg0 - -Slack : 19.605 -Actual Width : 19.835 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_we_reg - -Slack : 19.605 -Actual Width : 19.835 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_address_reg0 - -Slack : 19.605 -Actual Width : 19.835 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_we_reg - -Slack : 19.605 -Actual Width : 19.835 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_address_reg0 - -Slack : 19.605 -Actual Width : 19.835 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_we_reg - -Slack : 19.605 -Actual Width : 19.835 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_address_reg0 - -Slack : 19.605 -Actual Width : 19.835 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_we_reg - -Slack : 19.605 -Actual Width : 19.835 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0 - -Slack : 19.605 -Actual Width : 19.835 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_we_reg +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 Slack : 19.605 Actual Width : 19.835 @@ -19387,22 +19307,6 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_we_reg -Slack : 19.605 -Actual Width : 19.835 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_address_reg0 - -Slack : 19.605 -Actual Width : 19.835 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_we_reg - Slack : 19.605 Actual Width : 19.835 Required Width : 0.230 @@ -19426,6 +19330,102 @@ Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_address_reg0 + +Slack : 19.605 +Actual Width : 19.835 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_we_reg + +Slack : 19.605 +Actual Width : 19.835 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0 + +Slack : 19.605 +Actual Width : 19.835 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 + +Slack : 19.605 +Actual Width : 19.835 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9~porta_address_reg0 + +Slack : 19.605 +Actual Width : 19.821 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|attr_prefetch[0] + +Slack : 19.605 +Actual Width : 19.821 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|attr_prefetch[1] + +Slack : 19.605 +Actual Width : 19.821 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|attr_prefetch[2] + +Slack : 19.605 +Actual Width : 19.821 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|attr_prefetch[3] + +Slack : 19.605 +Actual Width : 19.821 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|attr_prefetch[4] + +Slack : 19.605 +Actual Width : 19.821 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|attr_prefetch[5] + +Slack : 19.605 +Actual Width : 19.821 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|attr_prefetch[6] + +Slack : 19.605 +Actual Width : 19.821 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ula:ula_|video:video_|attr_prefetch[7] +--------------------------------------------------------------------------------+ @@ -19433,21 +19433,45 @@ Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto +--------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ; +--------------------------------------------------------------------------------+ -Slack : 20.591 -Actual Width : 20.807 +Slack : 20.590 +Actual Width : 20.806 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] +Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] -Slack : 20.592 -Actual Width : 20.808 +Slack : 20.590 +Actual Width : 20.806 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] + +Slack : 20.590 +Actual Width : 20.806 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] + +Slack : 20.590 +Actual Width : 20.806 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] + +Slack : 20.590 +Actual Width : 20.806 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] Slack : 20.594 Actual Width : 20.810 @@ -19471,7 +19495,7 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] Slack : 20.594 Actual Width : 20.810 @@ -19479,7 +19503,7 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|state.Ack +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] Slack : 20.594 Actual Width : 20.810 @@ -19487,7 +19511,7 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|state.Data +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] Slack : 20.594 Actual Width : 20.810 @@ -19495,7 +19519,7 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|state.Pause +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] Slack : 20.594 Actual Width : 20.810 @@ -19503,7 +19527,7 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|state.Start +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] Slack : 20.594 Actual Width : 20.810 @@ -19511,39 +19535,79 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|state.Stop +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] -Slack : 20.595 -Actual Width : 20.811 +Slack : 20.594 +Actual Width : 20.810 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] -Slack : 20.595 -Actual Width : 20.811 +Slack : 20.594 +Actual Width : 20.810 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] -Slack : 20.595 -Actual Width : 20.811 +Slack : 20.594 +Actual Width : 20.810 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|phase[0] +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] -Slack : 20.595 -Actual Width : 20.811 +Slack : 20.594 +Actual Width : 20.810 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|phase[1] +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] + +Slack : 20.594 +Actual Width : 20.810 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] + +Slack : 20.594 +Actual Width : 20.810 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] + +Slack : 20.594 +Actual Width : 20.810 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] + +Slack : 20.594 +Actual Width : 20.810 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] + +Slack : 20.594 +Actual Width : 20.810 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] Slack : 20.595 Actual Width : 20.811 @@ -19567,7 +19631,71 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|state.Idle +Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] + +Slack : 20.595 +Actual Width : 20.811 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] + +Slack : 20.595 +Actual Width : 20.811 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] + +Slack : 20.595 +Actual Width : 20.811 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] + +Slack : 20.595 +Actual Width : 20.811 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] + +Slack : 20.595 +Actual Width : 20.811 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] + +Slack : 20.595 +Actual Width : 20.811 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] + +Slack : 20.595 +Actual Width : 20.811 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|state.Data + +Slack : 20.595 +Actual Width : 20.811 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|state.Pause Slack : 20.595 Actual Width : 20.811 @@ -19679,143 +19807,79 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] -Slack : 20.595 -Actual Width : 20.811 +Slack : 20.596 +Actual Width : 20.812 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] + +Slack : 20.596 +Actual Width : 20.812 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] + +Slack : 20.596 +Actual Width : 20.812 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|phase[0] + +Slack : 20.596 +Actual Width : 20.812 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|phase[1] + +Slack : 20.596 +Actual Width : 20.812 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] + +Slack : 20.596 +Actual Width : 20.812 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|state.Idle + +Slack : 20.596 +Actual Width : 20.812 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|state.Start + +Slack : 20.596 +Actual Width : 20.812 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] -Slack : 20.596 -Actual Width : 20.812 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] - -Slack : 20.596 -Actual Width : 20.812 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] - -Slack : 20.596 -Actual Width : 20.812 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] - -Slack : 20.596 -Actual Width : 20.812 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] - -Slack : 20.596 -Actual Width : 20.812 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] - -Slack : 20.596 -Actual Width : 20.812 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] - -Slack : 20.596 -Actual Width : 20.812 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] - -Slack : 20.596 -Actual Width : 20.812 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] - -Slack : 20.596 -Actual Width : 20.812 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] - -Slack : 20.596 -Actual Width : 20.812 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] - -Slack : 20.596 -Actual Width : 20.812 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] - -Slack : 20.596 -Actual Width : 20.812 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] - Slack : 20.598 Actual Width : 20.814 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] - -Slack : 20.598 -Actual Width : 20.814 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] - -Slack : 20.598 -Actual Width : 20.814 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] - -Slack : 20.598 -Actual Width : 20.814 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] +Target : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 Slack : 20.598 Actual Width : 20.814 @@ -19825,6 +19889,22 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] +Slack : 20.598 +Actual Width : 20.814 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8] + +Slack : 20.598 +Actual Width : 20.814 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] + Slack : 20.598 Actual Width : 20.814 Required Width : 0.216 @@ -19833,6 +19913,30 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 +Slack : 20.599 +Actual Width : 20.815 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|nbit[0] + +Slack : 20.599 +Actual Width : 20.815 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] + +Slack : 20.599 +Actual Width : 20.815 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] + Slack : 20.599 Actual Width : 20.815 Required Width : 0.216 @@ -19841,6 +19945,22 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] +Slack : 20.599 +Actual Width : 20.815 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] + +Slack : 20.599 +Actual Width : 20.815 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] + Slack : 20.599 Actual Width : 20.815 Required Width : 0.216 @@ -19849,141 +19969,21 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] -Slack : 20.599 -Actual Width : 20.815 +Slack : 20.601 +Actual Width : 20.817 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8] +Target : ula:ula_|i2c_loader:i2c_loader_|state.Ack -Slack : 20.599 -Actual Width : 20.815 +Slack : 20.601 +Actual Width : 20.817 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] - -Slack : 20.599 -Actual Width : 20.815 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] - -Slack : 20.599 -Actual Width : 20.815 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] - -Slack : 20.599 -Actual Width : 20.815 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] - -Slack : 20.599 -Actual Width : 20.815 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] - -Slack : 20.599 -Actual Width : 20.815 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] - -Slack : 20.599 -Actual Width : 20.815 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] - -Slack : 20.599 -Actual Width : 20.815 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] - -Slack : 20.599 -Actual Width : 20.815 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] - -Slack : 20.599 -Actual Width : 20.815 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] - -Slack : 20.599 -Actual Width : 20.815 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] - -Slack : 20.599 -Actual Width : 20.815 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] - -Slack : 20.599 -Actual Width : 20.815 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] - -Slack : 20.599 -Actual Width : 20.815 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] - -Slack : 20.599 -Actual Width : 20.815 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] - -Slack : 20.603 -Actual Width : 20.819 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] +Target : ula:ula_|i2c_loader:i2c_loader_|state.Stop Slack : 20.633 Actual Width : 20.817 @@ -20105,14 +20105,6 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|lrclk_r -Slack : 20.697 -Actual Width : 20.881 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] - Slack : 20.698 Actual Width : 20.853 Required Width : 0.155 @@ -20193,6 +20185,30 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2c_loader:i2c_loader_|sda_out +Slack : 20.700 +Actual Width : 20.884 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|state.Ack + +Slack : 20.700 +Actual Width : 20.884 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|state.Stop + +Slack : 20.702 +Actual Width : 20.886 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|nbit[0] + Slack : 20.702 Actual Width : 20.857 Required Width : 0.155 @@ -20207,7 +20223,7 @@ Required Width : 0.184 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] +Target : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 Slack : 20.702 Actual Width : 20.886 @@ -20215,23 +20231,7 @@ Required Width : 0.184 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] - -Slack : 20.702 -Actual Width : 20.886 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] - -Slack : 20.702 -Actual Width : 20.886 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] +--------------------------------------------------------------------------------+ @@ -20359,43 +20359,43 @@ Target : ula:ula_|clocks:clocks_|counter[0] +--------------------------------------------------------------------------------+ Data Port : raw_loader_in Clock Port : CLOCK_50 -Rise : 1.911 -Fall : 2.250 +Rise : 1.644 +Fall : 1.865 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : raw_loader_in Clock Port : CLOCK_50 -Rise : 3.553 -Fall : 3.886 +Rise : 3.339 +Fall : 3.547 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : SW[*] Clock Port : CLOCK_50 -Rise : 0.869 -Fall : 1.148 +Rise : 0.868 +Fall : 1.149 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Data Port : SW[2] Clock Port : CLOCK_50 -Rise : 0.869 -Fall : 1.148 +Rise : 0.868 +Fall : 1.149 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Data Port : AUD_ADCDAT Clock Port : CLOCK_50 -Rise : 1.127 -Fall : 1.330 +Rise : 1.441 +Fall : 1.652 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Data Port : I2C_SDAT Clock Port : CLOCK_50 -Rise : 2.508 -Fall : 2.792 +Rise : 2.596 +Fall : 2.778 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ @@ -20407,43 +20407,43 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ Data Port : raw_loader_in Clock Port : CLOCK_50 -Rise : -1.524 -Fall : -1.860 +Rise : -1.287 +Fall : -1.512 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : raw_loader_in Clock Port : CLOCK_50 -Rise : -2.737 -Fall : -3.061 +Rise : -2.425 +Fall : -2.640 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : SW[*] Clock Port : CLOCK_50 -Rise : -0.321 -Fall : -0.592 +Rise : -0.319 +Fall : -0.593 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Data Port : SW[2] Clock Port : CLOCK_50 -Rise : -0.321 -Fall : -0.592 +Rise : -0.319 +Fall : -0.593 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Data Port : AUD_ADCDAT Clock Port : CLOCK_50 -Rise : -0.576 -Fall : -0.776 +Rise : -0.901 +Fall : -1.108 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Data Port : I2C_SDAT Clock Port : CLOCK_50 -Rise : -1.192 -Fall : -1.416 +Rise : -1.177 +Fall : -1.402 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ @@ -20455,197 +20455,197 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ Data Port : GPIO_1[*] Clock Port : CLOCK_50 -Rise : 9.288 -Fall : 9.190 +Rise : 8.820 +Fall : 8.719 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[16] Clock Port : CLOCK_50 -Rise : 9.288 -Fall : 9.190 +Rise : 8.712 +Fall : 8.669 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[17] Clock Port : CLOCK_50 -Rise : 8.334 -Fall : 8.266 +Rise : 8.605 +Fall : 8.449 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[18] Clock Port : CLOCK_50 -Rise : 9.015 -Fall : 8.878 +Rise : 8.820 +Fall : 8.681 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[19] Clock Port : CLOCK_50 -Rise : 8.651 -Fall : 8.566 +Rise : 8.777 +Fall : 8.626 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[20] Clock Port : CLOCK_50 -Rise : 8.878 -Fall : 8.812 +Rise : 8.613 +Fall : 8.498 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[21] Clock Port : CLOCK_50 -Rise : 8.466 -Fall : 8.329 +Rise : 8.565 +Fall : 8.494 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[22] Clock Port : CLOCK_50 -Rise : 9.024 -Fall : 8.945 +Rise : 8.794 +Fall : 8.719 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[23] Clock Port : CLOCK_50 -Rise : 8.255 -Fall : 8.139 +Rise : 8.185 +Fall : 8.164 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[*] Clock Port : CLOCK_50 -Rise : 7.270 -Fall : 7.175 +Rise : 7.225 +Fall : 7.154 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[16] Clock Port : CLOCK_50 -Rise : 6.990 -Fall : 6.892 +Rise : 7.151 +Fall : 7.121 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[17] Clock Port : CLOCK_50 -Rise : 7.043 -Fall : 6.987 +Rise : 6.817 +Fall : 6.742 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[18] Clock Port : CLOCK_50 -Rise : 6.669 -Fall : 6.593 +Rise : 6.841 +Fall : 6.753 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[19] Clock Port : CLOCK_50 -Rise : 6.995 -Fall : 6.959 +Rise : 7.142 +Fall : 7.000 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[20] Clock Port : CLOCK_50 -Rise : 7.270 -Fall : 7.174 +Rise : 6.768 +Fall : 6.653 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[21] Clock Port : CLOCK_50 -Rise : 6.811 -Fall : 6.729 +Rise : 7.225 +Fall : 7.154 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[22] Clock Port : CLOCK_50 -Rise : 7.250 -Fall : 7.175 +Rise : 7.195 +Fall : 7.120 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[23] Clock Port : CLOCK_50 -Rise : 6.586 -Fall : 6.535 +Rise : 6.991 +Fall : 6.985 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[*] Clock Port : CLOCK_50 -Rise : 7.385 -Fall : 6.991 +Rise : 7.646 +Fall : 7.177 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[0] Clock Port : CLOCK_50 -Rise : 7.385 -Fall : 6.991 +Rise : 7.646 +Fall : 7.177 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[1] Clock Port : CLOCK_50 -Rise : 5.536 -Fall : 5.411 +Rise : 6.075 +Fall : 5.914 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[2] Clock Port : CLOCK_50 -Rise : 5.836 -Fall : 5.758 +Rise : 6.071 +Fall : 5.947 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[3] Clock Port : CLOCK_50 -Rise : 6.231 -Fall : 6.124 +Rise : 6.163 +Fall : 6.057 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[*] Clock Port : CLOCK_50 -Rise : 5.992 -Fall : 5.815 +Rise : 6.346 +Fall : 6.162 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[0] Clock Port : CLOCK_50 -Rise : 5.992 -Fall : 5.815 +Rise : 6.083 +Fall : 5.897 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[1] Clock Port : CLOCK_50 -Rise : 5.802 -Fall : 5.684 +Rise : 6.346 +Fall : 6.162 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[2] Clock Port : CLOCK_50 -Rise : 5.868 -Fall : 5.672 +Rise : 6.311 +Fall : 6.111 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[3] Clock Port : CLOCK_50 -Rise : 5.868 -Fall : 5.672 +Rise : 6.287 +Fall : 6.091 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] @@ -20658,36 +20658,36 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[*] Clock Port : CLOCK_50 -Rise : 6.035 -Fall : 5.996 +Rise : 6.818 +Fall : 6.718 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[0] Clock Port : CLOCK_50 -Rise : 6.035 -Fall : 5.996 +Rise : 6.617 +Fall : 6.456 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[1] Clock Port : CLOCK_50 -Rise : 5.858 -Fall : 5.798 +Rise : 6.818 +Fall : 6.718 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[2] Clock Port : CLOCK_50 -Rise : 5.672 -Fall : 5.600 +Rise : 5.818 +Fall : 5.652 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[3] Clock Port : CLOCK_50 -Rise : 5.870 -Fall : 5.793 +Rise : 6.304 +Fall : 6.116 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] @@ -20755,197 +20755,197 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ Data Port : GPIO_1[*] Clock Port : CLOCK_50 -Rise : 6.905 -Fall : 6.797 +Rise : 7.516 +Fall : 7.474 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[16] Clock Port : CLOCK_50 -Rise : 7.457 -Fall : 7.377 +Rise : 7.855 +Fall : 7.805 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[17] Clock Port : CLOCK_50 -Rise : 7.475 -Fall : 7.384 +Rise : 7.763 +Fall : 7.613 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[18] Clock Port : CLOCK_50 -Rise : 6.905 -Fall : 6.797 +Rise : 7.799 +Fall : 7.666 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[19] Clock Port : CLOCK_50 -Rise : 7.286 -Fall : 7.208 +Rise : 7.769 +Fall : 7.624 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[20] Clock Port : CLOCK_50 -Rise : 7.618 -Fall : 7.567 +Rise : 7.603 +Fall : 7.549 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[21] Clock Port : CLOCK_50 -Rise : 7.138 -Fall : 6.996 +Rise : 7.816 +Fall : 7.752 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[22] Clock Port : CLOCK_50 -Rise : 6.984 -Fall : 6.911 +Rise : 8.138 +Fall : 8.067 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[23] Clock Port : CLOCK_50 -Rise : 7.037 -Fall : 6.924 +Rise : 7.516 +Fall : 7.474 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[*] Clock Port : CLOCK_50 -Rise : 5.004 -Fall : 4.912 +Rise : 5.188 +Fall : 5.076 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[16] Clock Port : CLOCK_50 -Rise : 5.924 -Fall : 5.881 +Rise : 6.129 +Fall : 6.073 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[17] Clock Port : CLOCK_50 -Rise : 5.978 -Fall : 5.952 +Rise : 5.781 +Fall : 5.660 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[18] Clock Port : CLOCK_50 -Rise : 5.763 -Fall : 5.676 +Rise : 5.993 +Fall : 5.893 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[19] Clock Port : CLOCK_50 -Rise : 5.765 -Fall : 5.720 +Rise : 5.188 +Fall : 5.076 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[20] Clock Port : CLOCK_50 -Rise : 5.004 -Fall : 4.912 +Rise : 5.555 +Fall : 5.507 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[21] Clock Port : CLOCK_50 -Rise : 5.746 -Fall : 5.674 +Rise : 5.982 +Fall : 5.904 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[22] Clock Port : CLOCK_50 -Rise : 6.140 -Fall : 6.075 +Rise : 6.184 +Fall : 6.158 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[23] Clock Port : CLOCK_50 -Rise : 5.512 -Fall : 5.440 +Rise : 5.809 +Fall : 5.760 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[*] Clock Port : CLOCK_50 -Rise : 3.609 -Fall : 3.472 +Rise : 3.490 +Fall : 3.375 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[0] Clock Port : CLOCK_50 -Rise : 5.390 -Fall : 4.913 +Rise : 5.302 +Fall : 4.831 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[1] Clock Port : CLOCK_50 -Rise : 3.609 -Fall : 3.472 +Rise : 3.490 +Fall : 3.375 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[2] Clock Port : CLOCK_50 -Rise : 3.832 -Fall : 3.672 +Rise : 3.719 +Fall : 3.593 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[3] Clock Port : CLOCK_50 -Rise : 4.210 -Fall : 4.023 +Rise : 3.808 +Fall : 3.699 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[*] Clock Port : CLOCK_50 -Rise : 3.660 -Fall : 3.561 +Rise : 3.542 +Fall : 3.413 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[0] Clock Port : CLOCK_50 -Rise : 4.048 -Fall : 3.884 +Rise : 3.550 +Fall : 3.419 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[1] Clock Port : CLOCK_50 -Rise : 3.660 -Fall : 3.561 +Rise : 3.542 +Fall : 3.413 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[2] Clock Port : CLOCK_50 -Rise : 3.929 -Fall : 3.746 +Rise : 3.770 +Fall : 3.624 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[3] Clock Port : CLOCK_50 -Rise : 3.929 -Fall : 3.746 +Rise : 3.747 +Fall : 3.605 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] @@ -20958,36 +20958,36 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[*] Clock Port : CLOCK_50 -Rise : 3.534 -Fall : 3.394 +Rise : 3.296 +Fall : 3.183 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[0] Clock Port : CLOCK_50 -Rise : 3.882 -Fall : 3.774 +Rise : 4.064 +Fall : 3.956 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[1] Clock Port : CLOCK_50 -Rise : 3.799 -Fall : 3.710 +Rise : 3.885 +Fall : 3.786 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[2] Clock Port : CLOCK_50 -Rise : 3.534 -Fall : 3.394 +Rise : 3.296 +Fall : 3.183 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[3] Clock Port : CLOCK_50 -Rise : 3.723 -Fall : 3.578 +Rise : 3.763 +Fall : 3.630 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] @@ -21055,10 +21055,10 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ Input Port : SW[1] Output Port : LED[0] -RR : 4.171 +RR : 4.182 RF : FR : -FF : 4.298 +FF : 4.306 Input Port : SW[2] Output Port : LED[2] @@ -21069,17 +21069,17 @@ FF : 3.830 Input Port : raw_loader_in Output Port : GPIO_1[22] -RR : 6.058 +RR : 6.181 RF : FR : -FF : 6.293 +FF : 6.311 Input Port : raw_loader_in Output Port : LED[3] -RR : 3.926 +RR : 3.999 RF : FR : -FF : 4.082 +FF : 4.176 +--------------------------------------------------------------------------------+ @@ -21089,10 +21089,10 @@ FF : 4.082 +--------------------------------------------------------------------------------+ Input Port : SW[1] Output Port : LED[0] -RR : 4.037 +RR : 4.046 RF : FR : -FF : 4.164 +FF : 4.172 Input Port : SW[2] Output Port : LED[2] @@ -21103,17 +21103,17 @@ FF : 3.715 Input Port : raw_loader_in Output Port : GPIO_1[22] -RR : 5.841 +RR : 5.960 RF : FR : -FF : 6.076 +FF : 6.095 Input Port : raw_loader_in Output Port : LED[3] -RR : 3.796 +RR : 3.866 RF : FR : -FF : 3.952 +FF : 4.043 +--------------------------------------------------------------------------------+ @@ -21128,16 +21128,16 @@ No synchronizer chains to report. ; Fast 1200mV 0C Model Setup Summary ; +--------------------------------------------------------------------------------+ Clock : CLOCK_50 -Slack : -14.971 -End Point TNS : -442.545 +Slack : -15.171 +End Point TNS : -440.252 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Slack : -4.979 -End Point TNS : -171.124 +Slack : -4.743 +End Point TNS : -163.399 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Slack : -3.775 -End Point TNS : -35.541 +Slack : -3.815 +End Point TNS : -35.260 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Slack : -2.784 @@ -21150,8 +21150,8 @@ End Point TNS : -2.784 ; Fast 1200mV 0C Model Hold Summary ; +--------------------------------------------------------------------------------+ Clock : CLOCK_50 -Slack : -0.053 -End Point TNS : -0.089 +Slack : 0.112 +End Point TNS : 0.000 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Slack : 0.177 @@ -21172,8 +21172,8 @@ End Point TNS : 0.000 ; Fast 1200mV 0C Model Recovery Summary ; +--------------------------------------------------------------------------------+ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Slack : -4.693 -End Point TNS : -358.284 +Slack : -4.728 +End Point TNS : -362.420 +--------------------------------------------------------------------------------+ @@ -21182,7 +21182,7 @@ End Point TNS : -358.284 ; Fast 1200mV 0C Model Removal Summary ; +--------------------------------------------------------------------------------+ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Slack : 2.518 +Slack : 2.503 End Point TNS : 0.000 +--------------------------------------------------------------------------------+ @@ -21213,473 +21213,554 @@ End Point TNS : 0.000 +--------------------------------------------------------------------------------+ ; Fast 1200mV 0C Model Setup: 'CLOCK_50' ; +--------------------------------------------------------------------------------+ -Slack : -14.971 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.021 -Data Delay : 5.024 - -Slack : -14.965 -From Node : ula:ula_|video:video_|vga_vc[3] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.021 -Data Delay : 5.018 - -Slack : -14.951 -From Node : ula:ula_|video:video_|vga_vc[9] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.021 -Data Delay : 5.004 - -Slack : -14.940 -From Node : ula:ula_|video:video_|vga_vc[8] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.021 -Data Delay : 4.993 - -Slack : -14.933 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.022 -Data Delay : 4.985 - -Slack : -14.932 +Slack : -15.171 From Node : ula:ula_|video:video_|vga_hc[4] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.022 -Data Delay : 4.984 +Clock Skew : -0.026 +Data Delay : 5.219 -Slack : -14.927 +Slack : -15.085 From Node : ula:ula_|video:video_|vga_hc[6] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.022 -Data Delay : 4.979 +Clock Skew : -0.026 +Data Delay : 5.133 -Slack : -14.893 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.021 -Data Delay : 4.946 - -Slack : -14.893 -From Node : ula:ula_|video:video_|bits[5] +Slack : -15.048 +From Node : ula:ula_|video:video_|vga_vc[9] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 Clock Skew : -0.025 -Data Delay : 4.942 +Data Delay : 5.097 -Slack : -14.880 +Slack : -15.012 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.025 +Data Delay : 5.061 + +Slack : -14.996 +From Node : ula:ula_|video:video_|vga_vc[3] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.024 +Data Delay : 5.046 + +Slack : -14.991 +From Node : ula:ula_|video:video_|vga_vc[2] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.024 +Data Delay : 5.041 + +Slack : -14.969 +From Node : ula:ula_|video:video_|vga_hc[7] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.026 +Data Delay : 5.017 + +Slack : -14.934 From Node : ula:ula_|video:video_|vga_hc[1] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 Clock Skew : -0.025 -Data Delay : 4.929 +Data Delay : 4.983 -Slack : -14.864 -From Node : ula:ula_|video:video_|vga_vc[7] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.021 -Data Delay : 4.917 - -Slack : -14.860 -From Node : ula:ula_|video:video_|vga_vc[6] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.021 -Data Delay : 4.913 - -Slack : -14.853 -From Node : ula:ula_|video:video_|vga_vc[4] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.021 -Data Delay : 4.906 - -Slack : -14.842 +Slack : -14.916 From Node : ula:ula_|video:video_|vga_hc[5] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.022 -Data Delay : 4.894 +Clock Skew : -0.026 +Data Delay : 4.964 -Slack : -14.824 -From Node : ula:ula_|video:video_|vga_vc[0] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.021 -Data Delay : 4.877 - -Slack : -14.800 -From Node : ula:ula_|video:video_|vga_vc[5] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.021 -Data Delay : 4.853 - -Slack : -14.761 +Slack : -14.899 From Node : ula:ula_|video:video_|vga_hc[9] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.024 -Data Delay : 4.811 +Clock Skew : -0.026 +Data Delay : 4.947 -Slack : -14.737 -From Node : ula:ula_|video:video_|bits[1] +Slack : -14.873 +From Node : ula:ula_|video:video_|vga_vc[6] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 Clock Skew : -0.025 -Data Delay : 4.786 +Data Delay : 4.922 -Slack : -14.728 +Slack : -14.862 +From Node : ula:ula_|video:video_|vga_vc[8] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.024 +Data Delay : 4.912 + +Slack : -14.846 +From Node : ula:ula_|video:video_|vga_vc[1] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.024 +Data Delay : 4.896 + +Slack : -14.846 +From Node : ula:ula_|video:video_|vga_vc[0] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.024 +Data Delay : 4.896 + +Slack : -14.797 +From Node : ula:ula_|video:video_|bits[5] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.024 +Data Delay : 4.847 + +Slack : -14.797 +From Node : ula:ula_|video:video_|vga_vc[5] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.025 +Data Delay : 4.846 + +Slack : -14.782 +From Node : ula:ula_|video:video_|vga_vc[4] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.025 +Data Delay : 4.831 + +Slack : -14.776 +From Node : ula:ula_|video:video_|vga_vc[7] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.025 +Data Delay : 4.825 + +Slack : -14.776 From Node : ula:ula_|video:video_|vga_hc[8] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.022 -Data Delay : 4.780 - -Slack : -14.718 -From Node : ula:ula_|video:video_|vga_hc[7] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.022 -Data Delay : 4.770 - -Slack : -14.694 -From Node : ula:ula_|video:video_|frame[4] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 Clock Skew : -0.025 -Data Delay : 4.743 +Data Delay : 4.825 -Slack : -14.690 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4 -To Node : GPIO_1[20] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.178 -Data Delay : 4.586 - -Slack : -14.685 +Slack : -14.736 From Node : ula:ula_|video:video_|bits[6] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.025 -Data Delay : 4.734 +Clock Skew : -0.024 +Data Delay : 4.786 -Slack : -14.667 -From Node : ula:ula_|video:video_|bits[7] +Slack : -14.677 +From Node : ula:ula_|video:video_|bits[1] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.025 -Data Delay : 4.716 +Clock Skew : -0.024 +Data Delay : 4.727 -Slack : -14.623 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22 -To Node : GPIO_1[22] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.174 -Data Delay : 4.523 - -Slack : -14.609 +Slack : -14.630 From Node : ula:ula_|video:video_|bits[2] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.025 -Data Delay : 4.658 +Clock Skew : -0.024 +Data Delay : 4.680 -Slack : -14.606 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : GPIO_1[20] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.019 -Data Delay : 4.661 - -Slack : -14.593 -From Node : ula:ula_|video:video_|bits[3] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.025 -Data Delay : 4.642 - -Slack : -14.587 -From Node : ula:ula_|video:video_|attr[7] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.025 -Data Delay : 4.636 - -Slack : -14.564 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : GPIO_1[22] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.019 -Data Delay : 4.619 - -Slack : -14.561 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : GPIO_1[22] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.020 -Data Delay : 4.615 - -Slack : -14.543 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6 -To Node : GPIO_1[22] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.179 -Data Delay : 4.438 - -Slack : -14.517 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1 -To Node : GPIO_1[17] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.185 -Data Delay : 4.406 - -Slack : -14.515 -From Node : ula:ula_|video:video_|vga_hc[3] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.025 -Data Delay : 4.564 - -Slack : -14.515 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9 -To Node : GPIO_1[17] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.184 -Data Delay : 4.405 - -Slack : -14.501 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28 -To Node : GPIO_1[20] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.179 -Data Delay : 4.396 - -Slack : -14.497 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12 -To Node : GPIO_1[20] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.169 -Data Delay : 4.402 - -Slack : -14.494 -From Node : ula:ula_|video:video_|bits[4] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.025 -Data Delay : 4.543 - -Slack : -14.474 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : GPIO_1[19] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.019 -Data Delay : 4.529 - -Slack : -14.462 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8 -To Node : GPIO_1[16] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.178 -Data Delay : 4.358 - -Slack : -14.459 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20 -To Node : GPIO_1[20] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.179 -Data Delay : 4.354 - -Slack : -14.425 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30 -To Node : GPIO_1[22] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.179 -Data Delay : 4.320 - -Slack : -14.420 -From Node : ula:ula_|video:video_|bits[0] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.025 -Data Delay : 4.469 - -Slack : -14.413 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27 -To Node : GPIO_1[19] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.176 -Data Delay : 4.311 - -Slack : -14.388 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14 -To Node : GPIO_1[22] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.181 -Data Delay : 4.281 - -Slack : -14.372 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11 -To Node : GPIO_1[19] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.178 -Data Delay : 4.268 - -Slack : -14.341 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17 -To Node : GPIO_1[17] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.183 -Data Delay : 4.232 - -Slack : -14.340 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25 -To Node : GPIO_1[17] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.183 -Data Delay : 4.231 - -Slack : -14.337 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : GPIO_1[21] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.019 -Data Delay : 4.392 - -Slack : -14.335 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : GPIO_1[21] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.020 -Data Delay : 4.389 - -Slack : -14.333 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : GPIO_1[17] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.020 -Data Delay : 4.387 - -Slack : -14.325 +Slack : -14.613 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0 To Node : GPIO_1[16] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 +Clock Skew : -0.178 +Data Delay : 4.509 + +Slack : -14.607 +From Node : ula:ula_|video:video_|bits[7] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.024 +Data Delay : 4.657 + +Slack : -14.601 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : GPIO_1[21] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.009 +Data Delay : 4.666 + +Slack : -14.600 +From Node : ula:ula_|video:video_|vga_hc[3] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.026 +Data Delay : 4.648 + +Slack : -14.593 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 +To Node : GPIO_1[19] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.188 +Data Delay : 4.479 + +Slack : -14.578 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : GPIO_1[16] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.009 +Data Delay : 4.643 + +Slack : -14.566 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : GPIO_1[22] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.014 +Data Delay : 4.626 + +Slack : -14.565 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : GPIO_1[22] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.009 +Data Delay : 4.630 + +Slack : -14.564 +From Node : ula:ula_|video:video_|frame[4] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.024 +Data Delay : 4.614 + +Slack : -14.564 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 +To Node : GPIO_1[16] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.188 +Data Delay : 4.450 + +Slack : -14.534 +From Node : ula:ula_|video:video_|bits[3] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.024 +Data Delay : 4.584 + +Slack : -14.528 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : GPIO_1[23] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.014 +Data Delay : 4.588 + +Slack : -14.528 +From Node : ula:ula_|video:video_|attr[7] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.024 +Data Delay : 4.578 + +Slack : -14.525 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : GPIO_1[16] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.014 +Data Delay : 4.585 + +Slack : -14.521 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14 +To Node : GPIO_1[22] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.176 +Data Delay : 4.419 + +Slack : -14.513 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : GPIO_1[21] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.014 +Data Delay : 4.573 + +Slack : -14.478 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8 +To Node : GPIO_1[16] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.179 +Data Delay : 4.373 + +Slack : -14.464 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16 +To Node : GPIO_1[16] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.178 +Data Delay : 4.360 + +Slack : -14.449 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 +To Node : GPIO_1[22] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.177 +Data Delay : 4.346 + +Slack : -14.436 +From Node : ula:ula_|video:video_|bits[4] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.024 +Data Delay : 4.486 + +Slack : -14.431 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24 +To Node : GPIO_1[16] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.178 +Data Delay : 4.327 + +Slack : -14.426 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 +To Node : GPIO_1[16] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 Clock Skew : -0.184 -Data Delay : 4.215 +Data Delay : 4.316 + +Slack : -14.416 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : GPIO_1[23] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.009 +Data Delay : 4.481 + +Slack : -14.406 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30 +To Node : GPIO_1[22] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.169 +Data Delay : 4.311 + +Slack : -14.401 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 +To Node : GPIO_1[22] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.179 +Data Delay : 4.296 + +Slack : -14.393 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22 +To Node : GPIO_1[22] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.171 +Data Delay : 4.296 + +Slack : -14.392 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 +To Node : GPIO_1[19] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.177 +Data Delay : 4.289 + +Slack : -14.383 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6 +To Node : GPIO_1[22] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.174 +Data Delay : 4.283 + +Slack : -14.371 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : GPIO_1[19] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.009 +Data Delay : 4.436 + +Slack : -14.361 +From Node : ula:ula_|video:video_|bits[0] +To Node : VGA_B[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.024 +Data Delay : 4.411 + +Slack : -14.360 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2 +To Node : GPIO_1[18] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.171 +Data Delay : 4.263 + +Slack : -14.340 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : GPIO_1[18] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.014 +Data Delay : 4.400 + +Slack : -14.338 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10 +To Node : GPIO_1[18] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.177 +Data Delay : 4.235 + +Slack : -14.337 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21 +To Node : GPIO_1[21] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.183 +Data Delay : 4.228 + +Slack : -14.336 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2 +To Node : GPIO_1[18] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.185 +Data Delay : 4.225 + +Slack : -14.328 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : GPIO_1[17] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.014 +Data Delay : 4.388 + +Slack : -14.321 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 +To Node : GPIO_1[21] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.193 +Data Delay : 4.202 + +Slack : -14.314 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7 +To Node : GPIO_1[23] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.182 +Data Delay : 4.206 + +Slack : -14.313 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13 +To Node : GPIO_1[21] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.185 +Data Delay : 4.202 Slack : -14.310 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] @@ -21687,431 +21768,350 @@ To Node : GPIO_1[17] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.019 -Data Delay : 4.365 +Clock Skew : -0.009 +Data Delay : 4.375 + +Slack : -14.307 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 +To Node : GPIO_1[18] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.178 +Data Delay : 4.203 + +Slack : -14.297 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23 +To Node : GPIO_1[23] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.183 +Data Delay : 4.188 + +Slack : -14.293 +From Node : ula:ula_|video:video_|vga_hc[4] +To Node : VGA_R[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.026 +Data Delay : 4.341 + +Slack : -14.292 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29 +To Node : GPIO_1[21] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.184 +Data Delay : 4.182 + +Slack : -14.291 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 +To Node : GPIO_1[21] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.185 +Data Delay : 4.180 + +Slack : -14.288 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26 +To Node : GPIO_1[18] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.176 +Data Delay : 4.186 Slack : -14.285 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17 +To Node : GPIO_1[17] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.174 +Data Delay : 4.185 + +Slack : -14.284 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] To Node : GPIO_1[18] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.019 -Data Delay : 4.340 +Clock Skew : -0.009 +Data Delay : 4.349 -Slack : -14.285 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16 -To Node : GPIO_1[16] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.184 -Data Delay : 4.175 - -Slack : -14.284 +Slack : -14.283 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19 To Node : GPIO_1[19] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.176 -Data Delay : 4.182 +Clock Skew : -0.178 +Data Delay : 4.179 -Slack : -14.281 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5 -To Node : GPIO_1[21] +Slack : -14.280 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27 +To Node : GPIO_1[19] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.171 -Data Delay : 4.184 +Clock Skew : -0.184 +Data Delay : 4.170 -Slack : -14.271 +Slack : -14.277 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18 +To Node : GPIO_1[18] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.174 +Data Delay : 4.177 + +Slack : -14.263 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 +To Node : GPIO_1[23] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.191 +Data Delay : 4.146 + +Slack : -14.256 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : GPIO_1[16] +To Node : GPIO_1[20] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.019 -Data Delay : 4.326 +Clock Skew : -0.009 +Data Delay : 4.321 -Slack : -14.259 +Slack : -14.253 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3 To Node : GPIO_1[19] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 Clock Skew : -0.179 -Data Delay : 4.154 +Data Delay : 4.148 -Slack : -14.250 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24 -To Node : GPIO_1[16] +Slack : -14.231 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5 +To Node : GPIO_1[21] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.180 +Data Delay : 4.125 + +Slack : -14.226 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31 +To Node : GPIO_1[23] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.184 +Data Delay : 4.116 + +Slack : -14.207 +From Node : ula:ula_|video:video_|vga_hc[6] +To Node : VGA_R[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.026 +Data Delay : 4.255 + +Slack : -14.203 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 +To Node : GPIO_1[17] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.179 +Data Delay : 4.098 + +Slack : -14.198 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15 +To Node : GPIO_1[23] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 Clock Skew : -0.185 -Data Delay : 4.139 +Data Delay : 4.087 -Slack : -14.247 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : GPIO_1[19] +Slack : -14.183 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1 +To Node : GPIO_1[17] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.020 -Data Delay : 4.301 +Clock Skew : -0.179 +Data Delay : 4.078 -Slack : -14.221 +Slack : -14.166 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 +To Node : GPIO_1[23] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.194 +Data Delay : 4.046 + +Slack : -14.163 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12 +To Node : GPIO_1[20] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.181 +Data Delay : 4.056 + +Slack : -14.162 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9 +To Node : GPIO_1[17] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.183 +Data Delay : 4.053 + +Slack : -14.160 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] +To Node : GPIO_1[20] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.014 +Data Delay : 4.220 + +Slack : -14.131 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 +To Node : GPIO_1[20] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.184 +Data Delay : 4.021 + +Slack : -14.125 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 +To Node : GPIO_1[20] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.183 +Data Delay : 4.016 + +Slack : -14.121 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 +To Node : GPIO_1[17] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.184 +Data Delay : 4.011 + +Slack : -14.118 +From Node : ula:ula_|video:video_|vga_vc[3] +To Node : VGA_R[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.024 +Data Delay : 4.168 + +Slack : -14.113 +From Node : ula:ula_|video:video_|vga_vc[2] +To Node : VGA_R[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.024 +Data Delay : 4.163 + +Slack : -14.107 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : VGA_R[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.025 +Data Delay : 4.156 + +Slack : -14.104 +From Node : ula:ula_|video:video_|vga_vc[9] +To Node : VGA_R[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.164 +Clock Skew : -0.025 +Data Delay : 4.153 + +Slack : -14.101 From Node : ula:ula_|video:video_|attr[0] To Node : VGA_B[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 Clock Skew : -0.024 -Data Delay : 4.271 +Data Delay : 4.151 -Slack : -14.206 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2 -To Node : GPIO_1[18] +Slack : -14.097 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25 +To Node : GPIO_1[17] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 Clock Skew : -0.177 -Data Delay : 4.103 +Data Delay : 3.994 -Slack : -14.203 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13 -To Node : GPIO_1[21] +Slack : -14.091 +From Node : ula:ula_|video:video_|vga_hc[7] +To Node : VGA_R[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.171 -Data Delay : 4.106 +Clock Skew : -0.026 +Data Delay : 4.139 -Slack : -14.195 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10 -To Node : GPIO_1[18] +Slack : -14.066 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11 +To Node : GPIO_1[19] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.183 -Data Delay : 4.086 +Clock Skew : -0.179 +Data Delay : 3.961 -Slack : -14.189 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : GPIO_1[23] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.019 -Data Delay : 4.244 - -Slack : -14.183 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : GPIO_1[16] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.020 -Data Delay : 4.237 - -Slack : -14.169 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29 -To Node : GPIO_1[21] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.178 -Data Delay : 4.065 - -Slack : -14.155 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18 -To Node : GPIO_1[18] +Slack : -14.057 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4 +To Node : GPIO_1[20] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 Clock Skew : -0.177 -Data Delay : 4.052 +Data Delay : 3.954 -Slack : -14.138 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26 -To Node : GPIO_1[18] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.174 -Data Delay : 4.038 - -Slack : -14.126 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7 -To Node : GPIO_1[23] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.183 -Data Delay : 4.017 - -Slack : -14.124 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21 -To Node : GPIO_1[21] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.174 -Data Delay : 4.024 - -Slack : -14.114 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : GPIO_1[18] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.020 -Data Delay : 4.168 - -Slack : -14.045 -From Node : ula:ula_|video:video_|attr[3] -To Node : VGA_B[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.025 -Data Delay : 4.094 - -Slack : -14.020 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31 -To Node : GPIO_1[23] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.177 -Data Delay : 3.917 - -Slack : -13.997 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23 -To Node : GPIO_1[23] +Slack : -14.054 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28 +To Node : GPIO_1[20] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 Clock Skew : -0.181 -Data Delay : 3.890 +Data Delay : 3.947 -Slack : -13.949 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : GPIO_1[23] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.020 -Data Delay : 4.003 - -Slack : -13.888 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : VGA_B[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.021 -Data Delay : 3.941 - -Slack : -13.887 -From Node : ula:ula_|video:video_|vga_vc[3] -To Node : VGA_B[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.021 -Data Delay : 3.940 - -Slack : -13.882 -From Node : ula:ula_|video:video_|vga_hc[4] -To Node : VGA_B[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.022 -Data Delay : 3.934 - -Slack : -13.881 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15 -To Node : GPIO_1[23] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.177 -Data Delay : 3.778 - -Slack : -13.868 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : VGA_B[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.022 -Data Delay : 3.920 - -Slack : -13.841 -From Node : ula:ula_|video:video_|vga_vc[9] -To Node : VGA_B[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.021 -Data Delay : 3.894 - -Slack : -13.826 -From Node : ula:ula_|video:video_|vga_vc[8] -To Node : VGA_B[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.021 -Data Delay : 3.879 - -Slack : -13.816 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : VGA_B[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.021 -Data Delay : 3.869 - -Slack : -13.812 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : VGA_R[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.021 -Data Delay : 3.865 - -Slack : -13.811 -From Node : ula:ula_|video:video_|vga_vc[3] -To Node : VGA_R[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.021 -Data Delay : 3.864 - -Slack : -13.806 -From Node : ula:ula_|video:video_|vga_hc[4] -To Node : VGA_R[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.022 -Data Delay : 3.858 - -Slack : -13.792 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : VGA_R[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.022 -Data Delay : 3.844 - -Slack : -13.784 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : VGA_B[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.022 -Data Delay : 3.836 - -Slack : -13.765 -From Node : ula:ula_|video:video_|vga_vc[9] -To Node : VGA_R[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.021 -Data Delay : 3.818 - -Slack : -13.750 -From Node : ula:ula_|video:video_|vga_vc[8] -To Node : VGA_R[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.021 -Data Delay : 3.803 - -Slack : -13.747 -From Node : ula:ula_|video:video_|vga_vc[0] -To Node : VGA_B[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.021 -Data Delay : 3.800 - -Slack : -13.744 -From Node : ula:ula_|video:video_|bits[5] -To Node : VGA_B[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.025 -Data Delay : 3.793 - -Slack : -13.742 -From Node : ula:ula_|video:video_|vga_vc[6] -To Node : VGA_B[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.021 -Data Delay : 3.795 - -Slack : -13.742 -From Node : ula:ula_|video:video_|vga_vc[4] -To Node : VGA_B[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.021 -Data Delay : 3.795 - -Slack : -13.740 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : VGA_R[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.021 -Data Delay : 3.793 - -Slack : -13.738 -From Node : ula:ula_|video:video_|vga_vc[7] -To Node : VGA_B[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.021 -Data Delay : 3.791 - -Slack : -13.731 +Slack : -14.038 From Node : ula:ula_|video:video_|vga_hc[5] -To Node : VGA_B[3] +To Node : VGA_R[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.164 -Clock Skew : -0.022 -Data Delay : 3.783 - -Slack : -13.731 -From Node : ula:ula_|video:video_|vga_hc[1] -To Node : VGA_B[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.164 -Clock Skew : -0.025 -Data Delay : 3.780 +Clock Skew : -0.026 +Data Delay : 4.086 +--------------------------------------------------------------------------------+ @@ -22119,905 +22119,905 @@ Data Delay : 3.780 +--------------------------------------------------------------------------------+ ; Fast 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' ; +--------------------------------------------------------------------------------+ -Slack : -4.979 +Slack : -4.743 +From Node : raw_loader_in +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -0.062 +Data Delay : 2.770 + +Slack : -4.695 From Node : raw_loader_in To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 +Clock Skew : -0.060 +Data Delay : 2.724 + +Slack : -4.673 +From Node : raw_loader_in +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -0.056 +Data Delay : 2.706 + +Slack : -4.529 +From Node : raw_loader_in +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 Clock Skew : -0.058 -Data Delay : 3.010 +Data Delay : 2.560 -Slack : -4.977 -From Node : raw_loader_in -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 +Slack : -4.056 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -0.052 -Data Delay : 3.014 +Clock Skew : -1.193 +Data Delay : 2.952 -Slack : -4.861 -From Node : raw_loader_in -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -0.051 -Data Delay : 2.899 - -Slack : -4.849 -From Node : raw_loader_in -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -0.052 -Data Delay : 2.886 - -Slack : -4.418 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.376 -Data Delay : 3.131 - -Slack : -4.378 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.374 -Data Delay : 3.093 - -Slack : -4.335 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 +Slack : -3.956 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.371 -Data Delay : 3.053 +Clock Skew : -1.349 +Data Delay : 2.696 -Slack : -4.297 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.340 -Data Delay : 3.046 - -Slack : -4.275 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.355 -Data Delay : 3.009 - -Slack : -4.272 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 +Slack : -3.926 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.370 -Data Delay : 2.991 +Clock Skew : -1.348 +Data Delay : 2.667 -Slack : -4.269 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.390 -Data Delay : 2.968 - -Slack : -4.267 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.384 -Data Delay : 2.972 - -Slack : -4.253 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.369 -Data Delay : 2.973 - -Slack : -4.232 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.346 -Data Delay : 2.975 - -Slack : -4.230 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.369 -Data Delay : 2.950 - -Slack : -4.220 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 +Slack : -3.908 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.370 -Data Delay : 2.939 +Clock Skew : -1.348 +Data Delay : 2.649 -Slack : -4.204 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 +Slack : -3.896 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.339 -Data Delay : 2.954 +Clock Skew : -1.347 +Data Delay : 2.638 -Slack : -4.200 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 +Slack : -3.896 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.378 -Data Delay : 2.911 +Clock Skew : -1.333 +Data Delay : 2.652 -Slack : -4.196 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 +Slack : -3.895 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.334 +Data Delay : 2.650 + +Slack : -3.889 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.383 -Data Delay : 2.902 +Clock Skew : -1.333 +Data Delay : 2.645 -Slack : -4.194 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 +Slack : -3.886 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.341 -Data Delay : 2.942 +Clock Skew : -1.350 +Data Delay : 2.625 -Slack : -4.159 +Slack : -3.869 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.352 +Data Delay : 2.606 + +Slack : -3.867 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.353 +Data Delay : 2.603 + +Slack : -3.848 From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.351 -Data Delay : 2.897 - -Slack : -4.157 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 Clock Skew : -1.345 -Data Delay : 2.901 +Data Delay : 2.592 -Slack : -4.153 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 +Slack : -3.844 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 Clock Skew : -1.358 -Data Delay : 2.884 +Data Delay : 2.575 -Slack : -4.152 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0 +Slack : -3.843 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.355 -Data Delay : 2.886 +Clock Skew : -1.349 +Data Delay : 2.583 -Slack : -4.151 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 +Slack : -3.842 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.383 -Data Delay : 2.857 +Clock Skew : -1.350 +Data Delay : 2.581 -Slack : -4.149 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.341 -Data Delay : 2.897 - -Slack : -4.139 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.384 -Data Delay : 2.844 - -Slack : -4.131 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.372 -Data Delay : 2.848 - -Slack : -4.130 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.369 -Data Delay : 2.850 - -Slack : -4.126 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.380 -Data Delay : 2.835 - -Slack : -4.124 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.374 -Data Delay : 2.839 - -Slack : -4.115 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4 +Slack : -3.836 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 Clock Skew : -1.349 -Data Delay : 2.855 +Data Delay : 2.576 -Slack : -4.109 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.371 -Data Delay : 2.827 - -Slack : -4.086 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.340 -Data Delay : 2.835 - -Slack : -4.073 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.370 -Data Delay : 2.792 - -Slack : -4.071 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.365 -Data Delay : 2.795 - -Slack : -4.071 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.359 -Data Delay : 2.801 - -Slack : -4.061 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.367 -Data Delay : 2.783 - -Slack : -4.059 +Slack : -3.828 From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.356 -Data Delay : 2.792 +Clock Skew : -1.348 +Data Delay : 2.569 -Slack : -4.056 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.210 -Data Delay : 2.935 - -Slack : -4.055 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.369 -Data Delay : 2.775 - -Slack : -4.048 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.378 -Data Delay : 2.759 - -Slack : -4.044 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.373 -Data Delay : 2.760 - -Slack : -4.041 +Slack : -3.826 From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.344 -Data Delay : 2.786 - -Slack : -4.035 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 Clock Skew : -1.341 -Data Delay : 2.783 +Data Delay : 2.574 -Slack : -4.034 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.340 -Data Delay : 2.783 - -Slack : -4.029 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.345 -Data Delay : 2.773 - -Slack : -4.022 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.348 -Data Delay : 2.763 - -Slack : -4.021 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.363 -Data Delay : 2.747 - -Slack : -4.018 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.375 -Data Delay : 2.732 - -Slack : -4.010 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.380 -Data Delay : 2.719 - -Slack : -4.008 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.373 -Data Delay : 2.724 - -Slack : -4.003 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.348 -Data Delay : 2.744 - -Slack : -4.002 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.361 -Data Delay : 2.730 - -Slack : -4.001 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.336 -Data Delay : 2.754 - -Slack : -3.999 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.331 -Data Delay : 2.757 - -Slack : -3.999 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.338 -Data Delay : 2.750 - -Slack : -3.996 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.374 -Data Delay : 2.711 - -Slack : -3.994 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.350 -Data Delay : 2.733 - -Slack : -3.993 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 +Slack : -3.826 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.379 -Data Delay : 2.703 +Clock Skew : -1.345 +Data Delay : 2.570 -Slack : -3.989 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.333 -Data Delay : 2.745 - -Slack : -3.985 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 +Slack : -3.825 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.379 -Data Delay : 2.695 +Clock Skew : -1.361 +Data Delay : 2.553 -Slack : -3.985 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.363 -Data Delay : 2.711 - -Slack : -3.982 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.350 -Data Delay : 2.721 - -Slack : -3.980 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.382 -Data Delay : 2.687 - -Slack : -3.980 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.345 -Data Delay : 2.724 - -Slack : -3.975 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.367 -Data Delay : 2.697 - -Slack : -3.973 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.383 -Data Delay : 2.679 - -Slack : -3.973 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +Slack : -3.822 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.205 -Data Delay : 2.857 +Clock Skew : -1.342 +Data Delay : 2.569 -Slack : -3.972 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.364 -Data Delay : 2.697 - -Slack : -3.971 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.378 -Data Delay : 2.682 - -Slack : -3.970 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.347 -Data Delay : 2.712 - -Slack : -3.963 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.339 -Data Delay : 2.713 - -Slack : -3.961 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.380 -Data Delay : 2.670 - -Slack : -3.961 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.380 -Data Delay : 2.670 - -Slack : -3.960 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.356 -Data Delay : 2.693 - -Slack : -3.954 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.204 -Data Delay : 2.839 - -Slack : -3.953 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.335 -Data Delay : 2.707 - -Slack : -3.950 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.371 -Data Delay : 2.668 - -Slack : -3.949 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.362 -Data Delay : 2.676 - -Slack : -3.948 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.359 -Data Delay : 2.678 - -Slack : -3.944 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.382 -Data Delay : 2.651 - -Slack : -3.936 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.343 -Data Delay : 2.682 - -Slack : -3.932 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.210 -Data Delay : 2.811 - -Slack : -3.926 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.213 -Data Delay : 2.802 - -Slack : -3.920 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.343 -Data Delay : 2.666 - -Slack : -3.916 +Slack : -3.821 From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.356 -Data Delay : 2.649 - -Slack : -3.914 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 -Clock Skew : -1.368 -Data Delay : 2.635 - -Slack : -3.914 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.120 Clock Skew : -1.350 -Data Delay : 2.653 +Data Delay : 2.560 -Slack : -3.910 +Slack : -3.817 From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.194 +Data Delay : 2.712 + +Slack : -3.816 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.193 +Data Delay : 2.712 + +Slack : -3.807 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.194 +Data Delay : 2.702 + +Slack : -3.801 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.349 +Data Delay : 2.541 + +Slack : -3.800 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.351 +Data Delay : 2.538 + +Slack : -3.799 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.346 +Data Delay : 2.542 + +Slack : -3.792 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.204 -Data Delay : 2.795 +Clock Skew : -1.341 +Data Delay : 2.540 -Slack : -3.898 +Slack : -3.784 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.353 +Data Delay : 2.520 + +Slack : -3.777 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.350 +Data Delay : 2.516 + +Slack : -3.776 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.347 +Data Delay : 2.518 + +Slack : -3.774 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.341 +Data Delay : 2.522 + +Slack : -3.772 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.345 +Data Delay : 2.516 + +Slack : -3.770 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.197 +Data Delay : 2.662 + +Slack : -3.752 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.351 +Data Delay : 2.490 + +Slack : -3.752 From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.350 -Data Delay : 2.637 +Clock Skew : -1.340 +Data Delay : 2.501 -Slack : -3.896 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 +Slack : -3.743 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.368 -Data Delay : 2.617 +Clock Skew : -1.336 +Data Delay : 2.496 -Slack : -3.896 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 +Slack : -3.736 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.347 +Data Delay : 2.478 + +Slack : -3.702 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.348 +Data Delay : 2.443 + +Slack : -3.690 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.352 +Data Delay : 2.427 + +Slack : -3.690 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.208 +Data Delay : 2.571 + +Slack : -3.682 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.343 +Data Delay : 2.428 + +Slack : -3.676 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.343 +Data Delay : 2.422 + +Slack : -3.675 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.345 +Data Delay : 2.419 + +Slack : -3.664 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.338 +Data Delay : 2.415 + +Slack : -3.660 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.356 +Data Delay : 2.393 + +Slack : -3.659 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.333 +Data Delay : 2.415 + +Slack : -3.655 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.348 +Data Delay : 2.396 + +Slack : -3.651 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.341 +Data Delay : 2.399 + +Slack : -3.642 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.206 +Data Delay : 2.525 + +Slack : -3.640 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.335 +Data Delay : 2.394 + +Slack : -3.639 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.369 -Data Delay : 2.616 +Clock Skew : -1.339 +Data Delay : 2.389 -Slack : -3.892 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 +Slack : -3.627 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.362 -Data Delay : 2.619 +Clock Skew : -1.200 +Data Delay : 2.516 -Slack : -3.879 +Slack : -3.622 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.194 +Data Delay : 2.517 + +Slack : -3.620 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.202 +Data Delay : 2.507 + +Slack : -3.609 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.353 +Data Delay : 2.345 + +Slack : -3.609 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.195 +Data Delay : 2.503 + +Slack : -3.602 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.340 +Data Delay : 2.351 + +Slack : -3.597 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.199 +Data Delay : 2.487 + +Slack : -3.589 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.349 +Data Delay : 2.329 + +Slack : -3.588 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.337 +Data Delay : 2.340 + +Slack : -3.584 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.351 +Data Delay : 2.322 + +Slack : -3.579 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.349 +Data Delay : 2.319 + +Slack : -3.579 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.199 +Data Delay : 2.469 + +Slack : -3.544 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.200 +Data Delay : 2.433 + +Slack : -3.542 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.352 +Data Delay : 2.279 + +Slack : -3.536 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.197 +Data Delay : 2.428 + +Slack : -3.535 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.198 +Data Delay : 2.426 + +Slack : -3.529 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.197 +Data Delay : 2.421 + +Slack : -3.525 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.203 +Data Delay : 2.411 + +Slack : -3.513 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.341 +Data Delay : 2.261 + +Slack : -3.503 From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.348 -Data Delay : 2.620 +Clock Skew : -1.341 +Data Delay : 2.251 -Slack : -3.878 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 +Slack : -3.484 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.366 -Data Delay : 2.601 +Clock Skew : -1.347 +Data Delay : 2.226 -Slack : -3.875 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_datain_reg0 +Slack : -3.484 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.370 -Data Delay : 2.594 +Clock Skew : -1.195 +Data Delay : 2.378 -Slack : -3.870 -From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12 -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0 +Slack : -3.476 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.338 -Data Delay : 2.621 +Clock Skew : -1.204 +Data Delay : 2.361 -Slack : -3.862 +Slack : -3.471 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.339 +Data Delay : 2.221 + +Slack : -3.466 From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13 To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.350 -Data Delay : 2.601 +Clock Skew : -1.344 +Data Delay : 2.211 -Slack : -3.860 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 +Slack : -3.446 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.336 +Data Delay : 2.199 + +Slack : -3.435 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.196 +Data Delay : 2.328 + +Slack : -3.433 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.337 +Data Delay : 2.185 + +Slack : -3.407 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.198 +Data Delay : 2.298 + +Slack : -3.394 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.338 +Data Delay : 2.145 + +Slack : -3.383 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.200 +Data Delay : 2.272 + +Slack : -3.381 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.339 +Data Delay : 2.131 + +Slack : -3.360 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.198 +Data Delay : 2.251 + +Slack : -3.314 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.120 -Clock Skew : -1.366 -Data Delay : 2.583 +Clock Skew : -1.198 +Data Delay : 2.205 + +Slack : -3.309 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.193 +Data Delay : 2.205 + +Slack : -3.305 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.202 +Data Delay : 2.192 + +Slack : -3.304 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.204 +Data Delay : 2.189 + +Slack : -3.289 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.199 +Data Delay : 2.179 + +Slack : -3.280 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.200 +Data Delay : 2.169 + +Slack : -3.259 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.338 +Data Delay : 2.010 + +Slack : -3.207 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15 +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.340 +Data Delay : 1.956 + +Slack : -3.121 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.199 +Data Delay : 2.011 + +Slack : -3.113 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.120 +Clock Skew : -1.206 +Data Delay : 1.996 +--------------------------------------------------------------------------------+ @@ -23025,905 +23025,905 @@ Data Delay : 2.583 +--------------------------------------------------------------------------------+ ; Fast 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ; +--------------------------------------------------------------------------------+ -Slack : -3.775 +Slack : -3.815 +From Node : I2C_SDAT +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.226 +Data Delay : 1.960 + +Slack : -3.815 +From Node : I2C_SDAT +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.226 +Data Delay : 1.960 + +Slack : -3.760 From Node : I2C_SDAT To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.248 -Data Delay : 1.851 +Data Delay : 1.836 -Slack : -3.717 -From Node : I2C_SDAT -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.226 -Data Delay : 1.862 - -Slack : -3.717 -From Node : I2C_SDAT -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.226 -Data Delay : 1.862 - -Slack : -3.603 +Slack : -3.475 From Node : I2C_SDAT To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.226 -Data Delay : 1.748 +Clock Skew : -0.040 +Data Delay : 1.806 -Slack : -3.603 +Slack : -3.475 From Node : I2C_SDAT To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.226 -Data Delay : 1.748 +Clock Skew : -0.040 +Data Delay : 1.806 -Slack : -3.603 +Slack : -3.475 From Node : I2C_SDAT To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.226 -Data Delay : 1.748 +Clock Skew : -0.040 +Data Delay : 1.806 -Slack : -3.603 +Slack : -3.475 From Node : I2C_SDAT To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.226 -Data Delay : 1.748 +Clock Skew : -0.040 +Data Delay : 1.806 -Slack : -3.603 +Slack : -3.475 From Node : I2C_SDAT To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.226 -Data Delay : 1.748 +Clock Skew : -0.040 +Data Delay : 1.806 -Slack : -3.360 +Slack : -3.345 From Node : I2C_SDAT To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.226 -Data Delay : 1.505 +Data Delay : 1.490 -Slack : -2.957 +Slack : -3.150 From Node : AUD_ADCDAT To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.044 -Data Delay : 1.284 +Clock Skew : -0.222 +Data Delay : 1.299 -Slack : 18.580 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.984 - -Slack : 18.583 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.981 - -Slack : 18.654 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.910 - -Slack : 18.654 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.910 - -Slack : 18.657 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.907 - -Slack : 18.657 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.907 - -Slack : 18.675 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.889 - -Slack : 18.700 +Slack : 18.672 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.864 +Clock Skew : -0.276 +Data Delay : 1.890 -Slack : 18.700 +Slack : 18.672 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.276 +Data Delay : 1.890 + +Slack : 18.672 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.864 +Clock Skew : -0.276 +Data Delay : 1.890 -Slack : 18.700 +Slack : 18.672 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.864 +Clock Skew : -0.276 +Data Delay : 1.890 -Slack : 18.700 +Slack : 18.672 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.864 +Clock Skew : -0.276 +Data Delay : 1.890 -Slack : 18.703 +Slack : 18.672 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.861 +Clock Skew : -0.276 +Data Delay : 1.890 -Slack : 18.703 +Slack : 18.672 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.276 +Data Delay : 1.890 + +Slack : 18.672 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.861 +Clock Skew : -0.276 +Data Delay : 1.890 -Slack : 18.703 +Slack : 18.672 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.861 +Clock Skew : -0.276 +Data Delay : 1.890 -Slack : 18.703 +Slack : 18.672 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.861 +Clock Skew : -0.276 +Data Delay : 1.890 -Slack : 18.725 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.839 - -Slack : 18.739 +Slack : 18.713 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.825 - -Slack : 18.739 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.825 - -Slack : 18.740 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.824 - -Slack : 18.740 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.824 - -Slack : 18.750 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.814 +Clock Skew : -0.276 +Data Delay : 1.849 -Slack : 18.750 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +Slack : 18.713 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.814 +Clock Skew : -0.276 +Data Delay : 1.849 + +Slack : 18.713 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.276 +Data Delay : 1.849 + +Slack : 18.713 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.276 +Data Delay : 1.849 + +Slack : 18.743 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.276 +Data Delay : 1.819 + +Slack : 18.743 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.276 +Data Delay : 1.819 + +Slack : 18.743 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.276 +Data Delay : 1.819 + +Slack : 18.743 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.276 +Data Delay : 1.819 + +Slack : 18.743 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.276 +Data Delay : 1.819 Slack : 18.769 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.277 -Data Delay : 1.792 +Clock Skew : -0.275 +Data Delay : 1.794 Slack : 18.769 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.277 -Data Delay : 1.792 - -Slack : 18.772 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.277 -Data Delay : 1.789 +Clock Skew : -0.275 +Data Delay : 1.794 -Slack : 18.772 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.277 -Data Delay : 1.789 - -Slack : 18.774 +Slack : 18.784 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.790 - -Slack : 18.774 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.790 - -Slack : 18.774 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.790 - -Slack : 18.774 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.790 - -Slack : 18.799 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.765 +Clock Skew : -0.276 +Data Delay : 1.778 -Slack : 18.799 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +Slack : 18.784 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.765 +Clock Skew : -0.276 +Data Delay : 1.778 -Slack : 18.803 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Slack : 18.801 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.274 +Clock Skew : -0.276 Data Delay : 1.761 -Slack : 18.811 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.753 - -Slack : 18.811 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.753 - -Slack : 18.823 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.741 - -Slack : 18.823 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.741 - -Slack : 18.823 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.741 - -Slack : 18.823 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.741 - -Slack : 18.823 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.741 - -Slack : 18.824 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.740 - -Slack : 18.824 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.740 - -Slack : 18.824 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.740 - -Slack : 18.824 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.740 - -Slack : 18.824 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.740 - -Slack : 18.831 +Slack : 18.801 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.733 - -Slack : 18.831 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.733 - -Slack : 18.831 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.733 - -Slack : 18.831 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.733 - -Slack : 18.865 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.277 -Data Delay : 1.696 - -Slack : 18.865 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.277 -Data Delay : 1.696 - -Slack : 18.868 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.696 - -Slack : 18.868 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.696 - -Slack : 18.877 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.687 - -Slack : 18.877 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.687 - -Slack : 18.895 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.669 - -Slack : 18.895 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.669 - -Slack : 18.895 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.669 - -Slack : 18.895 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.669 - -Slack : 18.895 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.669 - -Slack : 18.909 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.277 -Data Delay : 1.652 - -Slack : 18.910 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.277 -Data Delay : 1.651 - -Slack : 18.914 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.277 -Data Delay : 1.647 - -Slack : 18.914 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.277 -Data Delay : 1.647 - -Slack : 18.923 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.641 - -Slack : 18.923 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.641 - -Slack : 18.923 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.641 - -Slack : 18.923 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.641 - -Slack : 18.947 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.617 +Clock Skew : -0.276 +Data Delay : 1.761 -Slack : 18.952 +Slack : 18.801 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.612 +Clock Skew : -0.276 +Data Delay : 1.761 -Slack : 18.952 +Slack : 18.801 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.612 +Clock Skew : -0.276 +Data Delay : 1.761 -Slack : 18.952 +Slack : 18.801 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.612 +Clock Skew : -0.276 +Data Delay : 1.761 -Slack : 18.952 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Slack : 18.805 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.612 +Clock Skew : -0.278 +Data Delay : 1.755 -Slack : 18.952 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Slack : 18.805 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.612 +Clock Skew : -0.278 +Data Delay : 1.755 -Slack : 18.981 +Slack : 18.805 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.278 +Data Delay : 1.755 + +Slack : 18.805 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.278 +Data Delay : 1.755 + +Slack : 18.840 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.277 -Data Delay : 1.580 +Clock Skew : -0.275 +Data Delay : 1.723 -Slack : 18.989 +Slack : 18.842 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.276 +Data Delay : 1.720 + +Slack : 18.842 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.276 +Data Delay : 1.720 + +Slack : 18.876 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.278 +Data Delay : 1.684 + +Slack : 18.876 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.278 +Data Delay : 1.684 + +Slack : 18.885 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.275 +Data Delay : 1.678 + +Slack : 18.885 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.275 +Data Delay : 1.678 + +Slack : 18.885 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.275 +Data Delay : 1.678 + +Slack : 18.885 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.275 +Data Delay : 1.678 + +Slack : 18.898 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.275 +Data Delay : 1.665 + +Slack : 18.934 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.278 +Data Delay : 1.626 + +Slack : 18.934 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.278 +Data Delay : 1.626 + +Slack : 18.952 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.089 +Data Delay : 1.797 + +Slack : 18.952 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.089 +Data Delay : 1.797 + +Slack : 18.952 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.089 +Data Delay : 1.797 + +Slack : 18.952 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.089 +Data Delay : 1.797 + +Slack : 18.952 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.089 +Data Delay : 1.797 + +Slack : 18.952 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.089 +Data Delay : 1.797 + +Slack : 18.952 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.089 +Data Delay : 1.797 + +Slack : 18.952 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.089 +Data Delay : 1.797 + +Slack : 18.952 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.089 +Data Delay : 1.797 + +Slack : 18.952 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.089 +Data Delay : 1.797 + +Slack : 18.956 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.275 +Data Delay : 1.607 + +Slack : 18.956 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.275 +Data Delay : 1.607 + +Slack : 18.992 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.275 +Data Delay : 1.571 + +Slack : 18.992 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.275 +Data Delay : 1.571 + +Slack : 18.992 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.275 +Data Delay : 1.571 + +Slack : 18.992 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.275 +Data Delay : 1.571 + +Slack : 18.992 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.275 +Data Delay : 1.571 + +Slack : 18.992 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.275 +Data Delay : 1.571 + +Slack : 18.992 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.275 +Data Delay : 1.571 + +Slack : 18.992 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.275 +Data Delay : 1.571 + +Slack : 19.012 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 Clock Skew : -0.087 -Data Delay : 1.762 +Data Delay : 1.739 -Slack : 18.991 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.573 - -Slack : 18.991 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.573 - -Slack : 18.992 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.277 -Data Delay : 1.569 - -Slack : 18.992 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.277 -Data Delay : 1.569 - -Slack : 18.992 +Slack : 19.012 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 Clock Skew : -0.087 -Data Delay : 1.759 +Data Delay : 1.739 -Slack : 19.021 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.543 - -Slack : 19.021 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.543 - -Slack : 19.038 +Slack : 19.014 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.277 -Data Delay : 1.523 +Clock Skew : -0.275 +Data Delay : 1.549 -Slack : 19.067 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Slack : 19.014 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.497 +Clock Skew : -0.275 +Data Delay : 1.549 -Slack : 19.067 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.497 - -Slack : 19.067 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.497 - -Slack : 19.067 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.497 - -Slack : 19.074 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +Slack : 19.023 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.490 +Clock Skew : -0.089 +Data Delay : 1.726 -Slack : 19.074 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +Slack : 19.023 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 20.851 -Clock Skew : -0.274 -Data Delay : 1.490 +Clock Skew : -0.089 +Data Delay : 1.726 + +Slack : 19.023 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.089 +Data Delay : 1.726 + +Slack : 19.023 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.089 +Data Delay : 1.726 + +Slack : 19.023 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.089 +Data Delay : 1.726 + +Slack : 19.051 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.276 +Data Delay : 1.511 + +Slack : 19.051 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.276 +Data Delay : 1.511 + +Slack : 19.051 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.276 +Data Delay : 1.511 + +Slack : 19.051 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.276 +Data Delay : 1.511 + +Slack : 19.051 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.276 +Data Delay : 1.511 + +Slack : 19.063 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.275 +Data Delay : 1.500 + +Slack : 19.063 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.275 +Data Delay : 1.500 + +Slack : 19.063 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.275 +Data Delay : 1.500 + +Slack : 19.063 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.275 +Data Delay : 1.500 + +Slack : 19.081 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.089 +Data Delay : 1.668 + +Slack : 19.081 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.089 +Data Delay : 1.668 + +Slack : 19.081 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.089 +Data Delay : 1.668 + +Slack : 19.081 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.089 +Data Delay : 1.668 + +Slack : 19.081 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.089 +Data Delay : 1.668 + +Slack : 19.083 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.087 +Data Delay : 1.668 + +Slack : 19.093 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.276 +Data Delay : 1.469 + +Slack : 19.093 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 20.851 +Clock Skew : -0.276 +Data Delay : 1.469 +--------------------------------------------------------------------------------+ @@ -23940,14 +23940,14 @@ Relationship : 0.423 Clock Skew : -0.021 Data Delay : 1.133 -Slack : 70.890 +Slack : 70.891 From Node : ula:ula_|clocks:clocks_|counter[0] To Node : ula:ula_|clocks:clocks_|clk_cpu Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Relationship : 71.489 Clock Skew : -0.046 -Data Delay : 0.540 +Data Delay : 0.539 Slack : 71.071 From Node : ula:ula_|clocks:clocks_|counter[0] @@ -23973,45 +23973,261 @@ Data Delay : 0.359 +--------------------------------------------------------------------------------+ ; Fast 1200mV 0C Model Hold: 'CLOCK_50' ; +--------------------------------------------------------------------------------+ -Slack : -0.053 +Slack : 0.112 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 -Clock Skew : 1.556 -Data Delay : 1.711 +Clock Skew : 1.562 +Data Delay : 1.882 -Slack : -0.036 +Slack : 0.123 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 -Clock Skew : 1.557 -Data Delay : 1.729 +Clock Skew : 1.574 +Data Delay : 1.905 -Slack : 0.540 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 +Slack : 0.268 +From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|address_reg_a[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.388 + +Slack : 0.505 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 -Clock Skew : 1.522 -Data Delay : 2.270 +Clock Skew : 1.403 +Data Delay : 2.116 -Slack : 0.548 -From Node : ula:ula_|video:video_|vram_address[7] +Slack : 0.509 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.566 +Data Delay : 2.283 + +Slack : 0.511 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.567 +Data Delay : 2.286 + +Slack : 0.514 +From Node : ula:ula_|video:video_|vram_address[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.527 +Data Delay : 2.249 + +Slack : 0.514 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.516 +Data Delay : 2.238 + +Slack : 0.515 +From Node : ula:ula_|video:video_|vram_address[10] To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 Clock Skew : 1.524 -Data Delay : 2.280 +Data Delay : 2.247 + +Slack : 0.516 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.578 +Data Delay : 2.302 + +Slack : 0.516 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.528 +Data Delay : 2.252 + +Slack : 0.516 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.514 +Data Delay : 2.238 + +Slack : 0.516 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.415 +Data Delay : 2.139 + +Slack : 0.519 +From Node : ula:ula_|video:video_|vram_address[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.524 +Data Delay : 2.251 + +Slack : 0.520 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.578 +Data Delay : 2.306 + +Slack : 0.524 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.519 +Data Delay : 2.251 + +Slack : 0.538 +From Node : ula:ula_|video:video_|vram_address[10] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.527 +Data Delay : 2.273 + +Slack : 0.540 +From Node : ula:ula_|video:video_|vram_address[10] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.521 +Data Delay : 2.269 + +Slack : 0.540 +From Node : ula:ula_|video:video_|vram_address[9] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.513 +Data Delay : 2.261 + +Slack : 0.544 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.415 +Data Delay : 2.167 + +Slack : 0.552 +From Node : ula:ula_|video:video_|vram_address[10] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.519 +Data Delay : 2.279 + +Slack : 0.553 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.514 +Data Delay : 2.275 + +Slack : 0.554 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.522 +Data Delay : 2.284 + +Slack : 0.555 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.511 +Data Delay : 2.274 + +Slack : 0.555 +From Node : ula:ula_|video:video_|vram_address[2] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.521 +Data Delay : 2.284 + +Slack : 0.556 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.517 +Data Delay : 2.281 + +Slack : 0.556 +From Node : ula:ula_|video:video_|vram_address[6] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.514 +Data Delay : 2.278 + +Slack : 0.557 +From Node : ula:ula_|video:video_|vram_address[2] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.519 +Data Delay : 2.284 Slack : 0.558 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 +From Node : ula:ula_|video:video_|vram_address[6] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 @@ -24019,859 +24235,643 @@ Clock Skew : 1.517 Data Delay : 2.283 Slack : 0.559 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 +From Node : ula:ula_|video:video_|vram_address[3] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 -Clock Skew : 1.514 -Data Delay : 2.281 +Clock Skew : 1.527 +Data Delay : 2.294 Slack : 0.561 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.524 -Data Delay : 2.293 - -Slack : 0.564 From Node : ula:ula_|video:video_|vram_address[7] To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 -Clock Skew : 1.526 -Data Delay : 2.298 - -Slack : 0.575 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.526 -Data Delay : 2.309 - -Slack : 0.603 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.516 -Data Delay : 2.327 - -Slack : 0.606 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 Clock Skew : 1.517 -Data Delay : 2.331 +Data Delay : 2.286 -Slack : 0.606 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 +Slack : 0.561 +From Node : ula:ula_|video:video_|vram_address[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 -Clock Skew : 1.509 -Data Delay : 2.323 +Clock Skew : 1.521 +Data Delay : 2.290 -Slack : 0.610 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.514 -Data Delay : 2.332 - -Slack : 0.618 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.575 -Data Delay : 2.401 - -Slack : 0.620 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.555 -Data Delay : 2.383 - -Slack : 0.623 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.558 -Data Delay : 2.389 - -Slack : 0.626 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.517 -Data Delay : 2.351 - -Slack : 0.637 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.571 -Data Delay : 2.416 - -Slack : 0.637 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 +Slack : 0.562 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 Clock Skew : 1.522 -Data Delay : 2.367 +Data Delay : 2.292 -Slack : 0.638 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.519 -Data Delay : 2.365 - -Slack : 0.641 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.570 -Data Delay : 2.419 - -Slack : 0.646 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.513 -Data Delay : 2.367 - -Slack : 0.650 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.506 -Data Delay : 2.364 - -Slack : 0.650 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.514 -Data Delay : 2.372 - -Slack : 0.651 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 +Slack : 0.568 +From Node : ula:ula_|video:video_|vram_address[9] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 Clock Skew : 1.516 -Data Delay : 2.375 +Data Delay : 2.292 -Slack : 0.651 +Slack : 0.572 From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.516 -Data Delay : 2.375 - -Slack : 0.651 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.558 -Data Delay : 2.417 - -Slack : 0.653 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.514 -Data Delay : 2.375 - -Slack : 0.654 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.511 -Data Delay : 2.373 - -Slack : 0.655 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.513 -Data Delay : 2.376 - -Slack : 0.660 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.521 -Data Delay : 2.389 - -Slack : 0.661 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.521 -Data Delay : 2.390 - -Slack : 0.662 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.513 -Data Delay : 2.383 - -Slack : 0.665 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.514 -Data Delay : 2.387 - -Slack : 0.665 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.514 -Data Delay : 2.387 - -Slack : 0.666 -From Node : ula:ula_|video:video_|vram_address[1] To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 -Clock Skew : 1.508 -Data Delay : 2.382 - -Slack : 0.667 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.514 -Data Delay : 2.389 - -Slack : 0.669 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.426 -Data Delay : 2.303 - -Slack : 0.669 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 Clock Skew : 1.506 -Data Delay : 2.383 +Data Delay : 2.286 -Slack : 0.669 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.507 -Data Delay : 2.384 - -Slack : 0.669 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.507 -Data Delay : 2.384 - -Slack : 0.671 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.509 -Data Delay : 2.388 - -Slack : 0.675 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.516 -Data Delay : 2.399 - -Slack : 0.675 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.503 -Data Delay : 2.386 - -Slack : 0.677 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.517 -Data Delay : 2.402 - -Slack : 0.677 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10 +Slack : 0.573 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 -Clock Skew : 1.419 -Data Delay : 2.304 +Clock Skew : 1.573 +Data Delay : 2.354 -Slack : 0.681 -From Node : ula:ula_|video:video_|vram_address[4] +Slack : 0.573 +From Node : ula:ula_|video:video_|vram_address[0] To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 -Clock Skew : 1.509 -Data Delay : 2.398 +Clock Skew : 1.519 +Data Delay : 2.300 -Slack : 0.683 -From Node : ula:ula_|video:video_|vram_address[4] +Slack : 0.573 +From Node : ula:ula_|video:video_|vram_address[2] To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 -Clock Skew : 1.511 -Data Delay : 2.402 +Clock Skew : 1.516 +Data Delay : 2.297 -Slack : 0.687 +Slack : 0.574 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.403 +Data Delay : 2.185 + +Slack : 0.574 From Node : ula:ula_|video:video_|vram_address[1] To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 -Clock Skew : 1.507 -Data Delay : 2.402 +Clock Skew : 1.521 +Data Delay : 2.303 -Slack : 0.688 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.519 -Data Delay : 2.415 - -Slack : 0.688 -From Node : ula:ula_|video:video_|vram_address[1] +Slack : 0.574 +From Node : ula:ula_|video:video_|vram_address[6] To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 -Clock Skew : 1.506 -Data Delay : 2.402 +Clock Skew : 1.510 +Data Delay : 2.292 -Slack : 0.689 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 +Slack : 0.575 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 -Clock Skew : 1.519 -Data Delay : 2.416 +Clock Skew : 1.509 +Data Delay : 2.292 -Slack : 0.689 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 +Slack : 0.575 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 -Clock Skew : 1.507 -Data Delay : 2.404 +Clock Skew : 1.510 +Data Delay : 2.293 -Slack : 0.690 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 +Slack : 0.576 +From Node : ula:ula_|video:video_|vram_address[9] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 -Clock Skew : 1.514 -Data Delay : 2.412 +Clock Skew : 1.518 +Data Delay : 2.302 -Slack : 0.690 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 +Slack : 0.576 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 -Clock Skew : 1.503 -Data Delay : 2.401 +Clock Skew : 1.410 +Data Delay : 2.194 -Slack : 0.691 -From Node : ula:ula_|video:video_|vram_address[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.522 -Data Delay : 2.421 - -Slack : 0.691 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.503 -Data Delay : 2.402 - -Slack : 0.693 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.427 -Data Delay : 2.328 - -Slack : 0.695 +Slack : 0.576 From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_datain_reg0 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 Clock Skew : 1.563 -Data Delay : 2.466 +Data Delay : 2.347 -Slack : 0.695 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 +Slack : 0.577 +From Node : ula:ula_|video:video_|vram_address[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 -Clock Skew : 1.522 -Data Delay : 2.425 +Clock Skew : 1.527 +Data Delay : 2.312 -Slack : 0.695 -From Node : ula:ula_|video:video_|vram_address[11] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 +Slack : 0.578 +From Node : ula:ula_|video:video_|vram_address[2] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 -Clock Skew : 1.507 -Data Delay : 2.410 +Clock Skew : 1.527 +Data Delay : 2.313 -Slack : 0.695 -From Node : ula:ula_|video:video_|vram_address[4] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.508 -Data Delay : 2.411 - -Slack : 0.696 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.514 -Data Delay : 2.418 - -Slack : 0.696 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.415 -Data Delay : 2.319 - -Slack : 0.698 -From Node : ula:ula_|video:video_|vram_address[11] +Slack : 0.579 +From Node : ula:ula_|video:video_|vram_address[6] To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 -Clock Skew : 1.517 -Data Delay : 2.423 +Clock Skew : 1.519 +Data Delay : 2.306 -Slack : 0.698 -From Node : ula:ula_|video:video_|vram_address[11] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 +Slack : 0.579 +From Node : ula:ula_|video:video_|vram_address[9] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 -Clock Skew : 1.515 -Data Delay : 2.421 +Clock Skew : 1.521 +Data Delay : 2.308 -Slack : 0.698 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 +Slack : 0.580 +From Node : ula:ula_|video:video_|vram_address[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 -Clock Skew : 1.508 -Data Delay : 2.414 +Clock Skew : 1.518 +Data Delay : 2.306 -Slack : 0.699 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 +Slack : 0.580 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 -Clock Skew : 1.562 -Data Delay : 2.469 +Clock Skew : 1.519 +Data Delay : 2.307 -Slack : 0.699 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.506 -Data Delay : 2.413 - -Slack : 0.699 -From Node : ula:ula_|video:video_|vram_address[11] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.504 -Data Delay : 2.411 - -Slack : 0.700 +Slack : 0.581 From Node : ula:ula_|video:video_|vram_address[12] To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 -Clock Skew : 1.508 -Data Delay : 2.416 +Clock Skew : 1.521 +Data Delay : 2.310 -Slack : 0.701 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_datain_reg0 +Slack : 0.583 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 -Clock Skew : 1.565 -Data Delay : 2.474 +Clock Skew : 1.413 +Data Delay : 2.204 -Slack : 0.702 +Slack : 0.585 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.511 +Data Delay : 2.304 + +Slack : 0.585 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.402 +Data Delay : 2.195 + +Slack : 0.587 +From Node : ula:ula_|video:video_|vram_address[6] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.512 +Data Delay : 2.307 + +Slack : 0.589 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.393 +Data Delay : 2.190 + +Slack : 0.591 +From Node : ula:ula_|video:video_|vram_address[9] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.510 +Data Delay : 2.309 + +Slack : 0.591 +From Node : ula:ula_|video:video_|vram_address[11] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.521 +Data Delay : 2.320 + +Slack : 0.591 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.410 +Data Delay : 2.209 + +Slack : 0.592 +From Node : ula:ula_|video:video_|vram_address[6] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.506 +Data Delay : 2.306 + +Slack : 0.594 From Node : ula:ula_|video:video_|vram_address[3] To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 -Clock Skew : 1.509 -Data Delay : 2.419 +Clock Skew : 1.519 +Data Delay : 2.321 -Slack : 0.703 -From Node : ula:ula_|video:video_|vram_address[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 +Slack : 0.594 +From Node : ula:ula_|video:video_|vram_address[6] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 -Clock Skew : 1.506 -Data Delay : 2.417 +Clock Skew : 1.509 +Data Delay : 2.311 -Slack : 0.703 -From Node : ula:ula_|video:video_|vram_address[8] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 +Slack : 0.594 +From Node : ula:ula_|video:video_|vram_address[6] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.522 +Data Delay : 2.324 + +Slack : 0.595 +From Node : ula:ula_|video:video_|vram_address[9] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.505 +Data Delay : 2.308 + +Slack : 0.595 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.576 +Data Delay : 2.379 + +Slack : 0.596 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.570 +Data Delay : 2.374 + +Slack : 0.596 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 Clock Skew : 1.512 -Data Delay : 2.423 +Data Delay : 2.316 -Slack : 0.704 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0 +Slack : 0.596 +From Node : ula:ula_|video:video_|vram_address[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 -Clock Skew : 1.406 -Data Delay : 2.318 +Clock Skew : 1.519 +Data Delay : 2.323 -Slack : 0.705 +Slack : 0.596 +From Node : ula:ula_|video:video_|vram_address[3] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.511 +Data Delay : 2.315 + +Slack : 0.596 +From Node : ula:ula_|video:video_|vram_address[3] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.521 +Data Delay : 2.325 + +Slack : 0.598 +From Node : ula:ula_|video:video_|vram_address[6] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.511 +Data Delay : 2.317 + +Slack : 0.598 +From Node : ula:ula_|video:video_|vram_address[9] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.508 +Data Delay : 2.314 + +Slack : 0.598 From Node : ula:ula_|video:video_|vram_address[11] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.513 +Data Delay : 2.319 + +Slack : 0.599 +From Node : ula:ula_|video:video_|vram_address[2] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.524 +Data Delay : 2.331 + +Slack : 0.604 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.565 +Data Delay : 2.377 + +Slack : 0.604 +From Node : ula:ula_|video:video_|vram_address[2] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.513 +Data Delay : 2.325 + +Slack : 0.605 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.562 +Data Delay : 2.375 + +Slack : 0.605 +From Node : ula:ula_|video:video_|vram_address[7] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.520 +Data Delay : 2.333 + +Slack : 0.605 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.408 +Data Delay : 2.221 + +Slack : 0.606 +From Node : ula:ula_|video:video_|vram_address[2] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.505 +Data Delay : 2.319 + +Slack : 0.607 +From Node : ula:ula_|video:video_|vram_address[2] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.510 +Data Delay : 2.325 + +Slack : 0.607 +From Node : ula:ula_|video:video_|vram_address[3] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.521 +Data Delay : 2.336 + +Slack : 0.607 +From Node : ula:ula_|video:video_|vram_address[4] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.505 +Data Delay : 2.320 + +Slack : 0.607 +From Node : ula:ula_|video:video_|vram_address[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.521 +Data Delay : 2.336 + +Slack : 0.607 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.415 +Data Delay : 2.230 + +Slack : 0.608 +From Node : ula:ula_|video:video_|vram_address[11] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.516 +Data Delay : 2.332 + +Slack : 0.610 +From Node : ula:ula_|video:video_|vram_address[11] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.518 +Data Delay : 2.336 + +Slack : 0.610 +From Node : ula:ula_|video:video_|vram_address[12] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.513 +Data Delay : 2.331 + +Slack : 0.610 +From Node : ula:ula_|video:video_|vram_address[1] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.511 +Data Delay : 2.329 + +Slack : 0.610 +From Node : ula:ula_|video:video_|vram_address[9] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.509 +Data Delay : 2.327 + +Slack : 0.611 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5 +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.409 +Data Delay : 2.228 + +Slack : 0.611 +From Node : ula:ula_|video:video_|vram_address[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.510 +Data Delay : 2.329 + +Slack : 0.611 +From Node : ula:ula_|video:video_|vram_address[6] To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 Clock Skew : 1.525 -Data Delay : 2.438 +Data Delay : 2.344 -Slack : 0.706 +Slack : 0.612 From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.524 -Data Delay : 2.438 - -Slack : 0.706 -From Node : ula:ula_|video:video_|vram_address[10] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.509 -Data Delay : 2.423 - -Slack : 0.706 -From Node : ula:ula_|video:video_|vram_address[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.509 -Data Delay : 2.423 - -Slack : 0.707 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.509 -Data Delay : 2.424 - -Slack : 0.709 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.506 -Data Delay : 2.423 - -Slack : 0.709 -From Node : ula:ula_|video:video_|vram_address[3] To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 -Clock Skew : 1.513 -Data Delay : 2.430 +Clock Skew : 1.528 +Data Delay : 2.348 -Slack : 0.710 -From Node : ula:ula_|video:video_|vram_address[5] +Slack : 0.612 +From Node : ula:ula_|video:video_|vram_address[6] To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 -Clock Skew : 1.503 -Data Delay : 2.421 +Clock Skew : 1.514 +Data Delay : 2.334 -Slack : 0.711 -From Node : ula:ula_|video:video_|vram_address[5] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 +Slack : 0.613 +From Node : ula:ula_|video:video_|vram_address[9] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.511 +Data Delay : 2.332 + +Slack : 0.615 +From Node : ula:ula_|video:video_|vram_address[0] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : CLOCK_50 +Relationship : 0.044 +Clock Skew : 1.516 +Data Delay : 2.339 + +Slack : 0.615 +From Node : ula:ula_|video:video_|vram_address[6] +To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : CLOCK_50 Relationship : 0.044 Clock Skew : 1.517 -Data Delay : 2.436 - -Slack : 0.712 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.511 -Data Delay : 2.431 - -Slack : 0.712 -From Node : ula:ula_|video:video_|vram_address[11] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.512 -Data Delay : 2.432 - -Slack : 0.712 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.423 -Data Delay : 2.343 - -Slack : 0.713 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.511 -Data Delay : 2.432 - -Slack : 0.713 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.575 -Data Delay : 2.496 - -Slack : 0.714 -From Node : ula:ula_|video:video_|vram_address[11] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.508 -Data Delay : 2.430 - -Slack : 0.714 -From Node : ula:ula_|video:video_|vram_address[7] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.508 -Data Delay : 2.430 - -Slack : 0.715 -From Node : ula:ula_|video:video_|vram_address[8] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.515 -Data Delay : 2.438 - -Slack : 0.716 -From Node : ula:ula_|video:video_|vram_address[10] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.522 -Data Delay : 2.446 - -Slack : 0.719 -From Node : ula:ula_|video:video_|vram_address[11] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.514 -Data Delay : 2.441 - -Slack : 0.720 -From Node : ula:ula_|video:video_|vram_address[12] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.514 -Data Delay : 2.442 - -Slack : 0.724 -From Node : ula:ula_|video:video_|vram_address[2] -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.524 -Data Delay : 2.456 - -Slack : 0.724 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.424 -Data Delay : 2.356 - -Slack : 0.725 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.421 -Data Delay : 2.354 - -Slack : 0.726 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29 -To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : CLOCK_50 -Relationship : 0.044 -Clock Skew : 1.421 -Data Delay : 2.355 +Data Delay : 2.340 +--------------------------------------------------------------------------------+ @@ -24922,107 +24922,116 @@ Data Delay : 0.576 ; Fast 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ; +--------------------------------------------------------------------------------+ Slack : 0.178 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] +From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 +To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.045 Data Delay : 0.307 -Slack : 0.184 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.046 -Data Delay : 0.314 - -Slack : 0.186 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.307 - -Slack : 0.186 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.307 - -Slack : 0.186 -From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.044 -Data Delay : 0.314 - -Slack : 0.186 +Slack : 0.178 From Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.037 +Clock Skew : 0.045 Data Delay : 0.307 -Slack : 0.186 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.307 - -Slack : 0.186 +Slack : 0.178 From Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.037 +Clock Skew : 0.045 Data Delay : 0.307 -Slack : 0.186 -From Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 -To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 +Slack : 0.183 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.307 +Clock Skew : 0.047 +Data Delay : 0.314 -Slack : 0.186 +Slack : 0.185 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.045 +Data Delay : 0.314 + +Slack : 0.185 From Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.044 +Clock Skew : 0.045 Data Delay : 0.314 -Slack : 0.187 +Slack : 0.186 +From Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.307 + +Slack : 0.186 +From Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.307 + +Slack : 0.186 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.307 + +Slack : 0.186 From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.307 + +Slack : 0.186 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.307 + +Slack : 0.187 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 Clock Skew : 0.036 Data Delay : 0.307 Slack : 0.187 -From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 @@ -25038,6 +25047,15 @@ Relationship : 0.000 Clock Skew : 0.036 Data Delay : 0.307 +Slack : 0.187 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.307 + Slack : 0.187 From Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] @@ -25047,32 +25065,41 @@ Relationship : 0.000 Clock Skew : 0.036 Data Delay : 0.307 -Slack : 0.187 -From Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] -To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] +Slack : 0.192 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.307 +Clock Skew : 0.037 +Data Delay : 0.313 -Slack : 0.187 -From Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] -To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] +Slack : 0.193 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.307 +Clock Skew : 0.037 +Data Delay : 0.314 -Slack : 0.188 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +Slack : 0.193 +From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.046 -Data Delay : 0.318 +Clock Skew : 0.037 +Data Delay : 0.314 + +Slack : 0.193 +From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.314 Slack : 0.193 From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] @@ -25083,6 +25110,33 @@ Relationship : 0.000 Clock Skew : 0.037 Data Delay : 0.314 +Slack : 0.194 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.315 + +Slack : 0.194 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.315 + +Slack : 0.194 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.315 + Slack : 0.194 From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] @@ -25101,225 +25155,234 @@ Relationship : 0.000 Clock Skew : 0.036 Data Delay : 0.314 -Slack : 0.195 -From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Slack : 0.196 +From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.315 - -Slack : 0.200 -From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 -To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.320 +Clock Skew : 0.037 +Data Delay : 0.317 Slack : 0.201 -From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 -To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.321 - -Slack : 0.204 From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.324 +Clock Skew : 0.037 +Data Delay : 0.322 -Slack : 0.208 +Slack : 0.222 From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle -To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.036 -Data Delay : 0.328 +Data Delay : 0.342 -Slack : 0.210 +Slack : 0.225 From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.036 -Data Delay : 0.330 +Data Delay : 0.345 -Slack : 0.243 +Slack : 0.226 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.346 + +Slack : 0.233 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.233 +Data Delay : 0.550 + +Slack : 0.246 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.237 +Data Delay : 0.567 + +Slack : 0.252 From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.045 -Data Delay : 0.372 +Clock Skew : 0.037 +Data Delay : 0.373 -Slack : 0.244 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] +Slack : 0.253 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.045 -Data Delay : 0.373 +Clock Skew : 0.037 +Data Delay : 0.374 -Slack : 0.244 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.045 -Data Delay : 0.373 - -Slack : 0.244 +Slack : 0.253 From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.045 -Data Delay : 0.373 - -Slack : 0.245 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.045 +Clock Skew : 0.037 Data Delay : 0.374 -Slack : 0.262 -From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Slack : 0.254 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.382 +Clock Skew : 0.037 +Data Delay : 0.375 -Slack : 0.266 +Slack : 0.256 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.235 +Data Delay : 0.575 + +Slack : 0.263 From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.034 +Clock Skew : 0.037 Data Delay : 0.384 -Slack : 0.288 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +Slack : 0.273 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.046 -Data Delay : 0.418 +Clock Skew : 0.037 +Data Delay : 0.394 -Slack : 0.289 +Slack : 0.275 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.396 + +Slack : 0.286 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.046 -Data Delay : 0.419 +Clock Skew : 0.047 +Data Delay : 0.417 -Slack : 0.291 +Slack : 0.287 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.047 +Data Delay : 0.418 + +Slack : 0.289 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.046 +Clock Skew : 0.047 +Data Delay : 0.420 + +Slack : 0.290 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.047 Data Delay : 0.421 -Slack : 0.292 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] +Slack : 0.293 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.060 -Data Delay : 0.436 +Clock Skew : 0.235 +Data Delay : 0.612 -Slack : 0.292 -From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.412 - -Slack : 0.296 -From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.416 - -Slack : 0.296 +Slack : 0.293 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.046 -Data Delay : 0.426 +Clock Skew : 0.047 +Data Delay : 0.424 -Slack : 0.296 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.046 -Data Delay : 0.426 - -Slack : 0.297 -From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.417 - -Slack : 0.298 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.034 -Data Delay : 0.416 - -Slack : 0.298 -From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] +Slack : 0.294 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.037 -Data Delay : 0.419 +Data Delay : 0.415 + +Slack : 0.295 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.416 + +Slack : 0.295 +From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.416 + +Slack : 0.296 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.417 Slack : 0.298 -From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] +From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 @@ -25332,368 +25395,386 @@ To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.419 +Clock Skew : 0.036 +Data Delay : 0.418 -Slack : 0.302 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack +Slack : 0.298 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.423 - -Slack : 0.303 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.424 - -Slack : 0.305 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.234 -Data Delay : 0.623 - -Slack : 0.307 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.045 -Data Delay : 0.436 - -Slack : 0.307 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.045 -Data Delay : 0.436 - -Slack : 0.307 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.045 -Data Delay : 0.436 - -Slack : 0.307 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.045 -Data Delay : 0.436 - -Slack : 0.308 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.045 -Data Delay : 0.437 - -Slack : 0.308 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.045 -Data Delay : 0.437 - -Slack : 0.308 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.045 -Data Delay : 0.437 - -Slack : 0.308 -From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.037 +Clock Skew : 0.047 Data Delay : 0.429 -Slack : 0.309 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] +Slack : 0.299 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.045 -Data Delay : 0.438 +Clock Skew : 0.036 +Data Delay : 0.419 -Slack : 0.309 -From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] +Slack : 0.300 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.037 -Data Delay : 0.430 +Data Delay : 0.421 -Slack : 0.317 -From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Slack : 0.306 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.437 +Clock Skew : 0.037 +Data Delay : 0.427 -Slack : 0.320 -From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.440 - -Slack : 0.325 +Slack : 0.307 From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.445 +Clock Skew : 0.045 +Data Delay : 0.436 -Slack : 0.328 -From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.448 - -Slack : 0.332 -From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.452 - -Slack : 0.341 -From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.461 - -Slack : 0.341 -From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Slack : 0.307 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.036 -Data Delay : 0.461 +Data Delay : 0.427 -Slack : 0.346 +Slack : 0.310 +From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.045 +Data Delay : 0.439 + +Slack : 0.310 +From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.045 +Data Delay : 0.439 + +Slack : 0.310 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.430 + +Slack : 0.310 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.430 + +Slack : 0.312 +From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.045 +Data Delay : 0.441 + +Slack : 0.314 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.434 + +Slack : 0.315 From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.036 -Data Delay : 0.466 +Data Delay : 0.435 -Slack : 0.370 -From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 -To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 +Slack : 0.322 +From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.045 +Data Delay : 0.451 + +Slack : 0.340 +From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.461 + +Slack : 0.341 +From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.462 + +Slack : 0.357 +From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.478 + +Slack : 0.362 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.235 +Data Delay : 0.681 + +Slack : 0.376 +From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.036 -Data Delay : 0.490 +Data Delay : 0.496 -Slack : 0.371 -From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Slack : 0.378 +From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.499 + +Slack : 0.382 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.036 -Data Delay : 0.491 +Data Delay : 0.502 -Slack : 0.373 -From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.493 - -Slack : 0.397 +Slack : 0.394 From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : -0.154 -Data Delay : 0.327 +Data Delay : 0.324 Slack : 0.398 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start -To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.039 -Data Delay : 0.521 - -Slack : 0.402 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.039 -Data Delay : 0.525 - -Slack : 0.404 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.039 -Data Delay : 0.527 - -Slack : 0.409 -From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.529 - -Slack : 0.410 -From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] +From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.530 +Clock Skew : 0.037 +Data Delay : 0.519 -Slack : 0.411 -From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Slack : 0.399 +From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.520 + +Slack : 0.403 +From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.524 + +Slack : 0.414 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.231 +Data Delay : 0.729 + +Slack : 0.414 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.231 +Data Delay : 0.729 + +Slack : 0.414 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.231 +Data Delay : 0.729 + +Slack : 0.414 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.231 +Data Delay : 0.729 + +Slack : 0.414 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.231 +Data Delay : 0.729 + +Slack : 0.415 +From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.235 +Data Delay : 0.734 + +Slack : 0.427 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.036 -Data Delay : 0.531 +Data Delay : 0.547 -Slack : 0.424 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +Slack : 0.433 +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.545 +Clock Skew : 0.036 +Data Delay : 0.553 -Slack : 0.427 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +Slack : 0.433 +From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.037 -Data Delay : 0.548 +Data Delay : 0.554 -Slack : 0.430 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.551 - -Slack : 0.432 -From Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 +Slack : 0.434 +From Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 +To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.036 -Data Delay : 0.552 +Data Delay : 0.554 -Slack : 0.437 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.046 -Data Delay : 0.567 - -Slack : 0.438 +Slack : 0.435 From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.046 -Data Delay : 0.568 +Clock Skew : 0.047 +Data Delay : 0.566 + +Slack : 0.436 +From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.557 + +Slack : 0.436 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.047 +Data Delay : 0.567 + +Slack : 0.439 +From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.560 + +Slack : 0.441 +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.561 Slack : 0.443 -From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] +From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : -0.155 -Data Delay : 0.372 +Clock Skew : 0.036 +Data Delay : 0.563 Slack : 0.446 -From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] +From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.567 - -Slack : 0.446 -From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.567 +Clock Skew : 0.036 +Data Delay : 0.566 Slack : 0.446 From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] @@ -25701,125 +25782,44 @@ To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 -Clock Skew : 0.037 +Clock Skew : 0.036 +Data Delay : 0.566 + +Slack : 0.446 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.047 +Data Delay : 0.577 + +Slack : 0.447 +From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.036 Data Delay : 0.567 Slack : 0.447 +From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.000 +Clock Skew : 0.047 +Data Delay : 0.578 + +Slack : 0.448 From Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.000 Clock Skew : 0.036 -Data Delay : 0.567 - -Slack : 0.448 -From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.036 Data Delay : 0.568 - -Slack : 0.448 -From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.039 -Data Delay : 0.571 - -Slack : 0.448 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.046 -Data Delay : 0.578 - -Slack : 0.449 -From Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.044 -Data Delay : 0.577 - -Slack : 0.449 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.046 -Data Delay : 0.579 - -Slack : 0.449 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.046 -Data Delay : 0.579 - -Slack : 0.451 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.046 -Data Delay : 0.581 - -Slack : 0.452 -From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.572 - -Slack : 0.452 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.046 -Data Delay : 0.582 - -Slack : 0.452 -From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.046 -Data Delay : 0.582 - -Slack : 0.457 -From Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 -To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.577 - -Slack : 0.457 -From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.577 +--------------------------------------------------------------------------------+ @@ -25872,15 +25872,6 @@ Relationship : 0.000 Clock Skew : 0.037 Data Delay : 0.307 -Slack : 0.186 -From Node : ula:ula_|video:video_|vga_vc[0] -To Node : ula:ula_|video:video_|vga_vc[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.307 - Slack : 0.186 From Node : ula:ula_|video:video_|vga_vc[1] To Node : ula:ula_|video:video_|vga_vc[1] @@ -25890,24 +25881,6 @@ Relationship : 0.000 Clock Skew : 0.037 Data Delay : 0.307 -Slack : 0.186 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : ula:ula_|video:video_|vga_vc[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.307 - -Slack : 0.186 -From Node : ula:ula_|video:video_|vga_vc[8] -To Node : ula:ula_|video:video_|vga_vc[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.307 - Slack : 0.186 From Node : ula:ula_|video:video_|vga_vc[4] To Node : ula:ula_|video:video_|vga_vc[4] @@ -25917,6 +25890,15 @@ Relationship : 0.000 Clock Skew : 0.037 Data Delay : 0.307 +Slack : 0.186 +From Node : ula:ula_|video:video_|vga_vc[5] +To Node : ula:ula_|video:video_|vga_vc[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.307 + Slack : 0.186 From Node : ula:ula_|video:video_|vga_vc[6] To Node : ula:ula_|video:video_|vga_vc[6] @@ -25935,6 +25917,15 @@ Relationship : 0.000 Clock Skew : 0.037 Data Delay : 0.307 +Slack : 0.186 +From Node : ula:ula_|video:video_|vga_vc[8] +To Node : ula:ula_|video:video_|vga_vc[8] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.307 + Slack : 0.293 From Node : ula:ula_|video:video_|frame[2] To Node : ula:ula_|video:video_|frame[2] @@ -25944,59 +25935,23 @@ Relationship : 0.000 Clock Skew : 0.037 Data Delay : 0.414 -Slack : 0.294 +Slack : 0.295 From Node : ula:ula_|video:video_|frame[3] To Node : ula:ula_|video:video_|frame[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.037 -Data Delay : 0.415 +Data Delay : 0.416 -Slack : 0.300 +Slack : 0.299 From Node : ula:ula_|video:video_|frame[1] To Node : ula:ula_|video:video_|frame[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.037 -Data Delay : 0.421 - -Slack : 0.303 -From Node : ula:ula_|video:video_|frame[4] -To Node : ula:ula_|video:video_|frame[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.424 - -Slack : 0.336 -From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[1] -To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.457 - -Slack : 0.400 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|vram_address[10] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.521 - -Slack : 0.442 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.042 -Data Delay : 0.568 +Data Delay : 0.420 Slack : 0.442 From Node : ula:ula_|video:video_|frame[2] @@ -26008,724 +25963,769 @@ Clock Skew : 0.037 Data Delay : 0.563 Slack : 0.452 -From Node : ula:ula_|video:video_|frame[3] -To Node : ula:ula_|video:video_|frame[4] +From Node : ula:ula_|video:video_|frame[1] +To Node : ula:ula_|video:video_|frame[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.037 Data Delay : 0.573 -Slack : 0.453 -From Node : ula:ula_|video:video_|frame[1] -To Node : ula:ula_|video:video_|frame[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.574 - -Slack : 0.456 +Slack : 0.455 From Node : ula:ula_|video:video_|frame[1] To Node : ula:ula_|video:video_|frame[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.037 -Data Delay : 0.577 +Data Delay : 0.576 -Slack : 0.457 -From Node : ula:ula_|video:video_|vga_hc[8] -To Node : ula:ula_|video:video_|vga_hc[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.578 - -Slack : 0.481 -From Node : ula:ula_|video:video_|frame[0] -To Node : ula:ula_|video:video_|frame[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.601 - -Slack : 0.505 -From Node : ula:ula_|video:video_|frame[2] -To Node : ula:ula_|video:video_|frame[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.626 - -Slack : 0.519 -From Node : ula:ula_|video:video_|frame[1] -To Node : ula:ula_|video:video_|frame[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.640 - -Slack : 0.524 -From Node : ula:ula_|video:video_|vga_vc[4] -To Node : ula:ula_|video:video_|vram_address[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.042 -Data Delay : 0.650 - -Slack : 0.534 -From Node : ula:ula_|video:video_|vga_vc[5] -To Node : ula:ula_|video:video_|vram_address[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.042 -Data Delay : 0.660 - -Slack : 0.544 -From Node : ula:ula_|video:video_|vga_hc[4] -To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.039 -Data Delay : 0.667 - -Slack : 0.581 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|vram_address[12] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.040 -Data Delay : 0.705 - -Slack : 0.582 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|vram_address[9] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.040 -Data Delay : 0.706 - -Slack : 0.582 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|vram_address[11] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.040 -Data Delay : 0.706 - -Slack : 0.582 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|vram_address[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.040 -Data Delay : 0.706 - -Slack : 0.592 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : ula:ula_|video:video_|vram_address[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.041 -Data Delay : 0.717 - -Slack : 0.595 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : ula:ula_|video:video_|vram_address[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.041 -Data Delay : 0.720 - -Slack : 0.597 -From Node : ula:ula_|video:video_|vga_hc[5] -To Node : ula:ula_|video:video_|vram_address[1] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.041 -Data Delay : 0.722 - -Slack : 0.598 -From Node : ula:ula_|video:video_|bits_prefetch[6] -To Node : ula:ula_|video:video_|bits[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.160 -Data Delay : 0.522 - -Slack : 0.610 +Slack : 0.478 From Node : ula:ula_|video:video_|bits_prefetch[1] To Node : ula:ula_|video:video_|bits[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : -0.160 -Data Delay : 0.534 +Clock Skew : -0.152 +Data Delay : 0.410 -Slack : 0.611 -From Node : ula:ula_|video:video_|vga_hc[4] -To Node : ula:ula_|video:video_|vram_address[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.041 -Data Delay : 0.736 - -Slack : 0.613 -From Node : ula:ula_|video:video_|bits_prefetch[2] -To Node : ula:ula_|video:video_|bits[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.160 -Data Delay : 0.537 - -Slack : 0.619 +Slack : 0.484 From Node : ula:ula_|video:video_|bits_prefetch[5] To Node : ula:ula_|video:video_|bits[5] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : -0.160 -Data Delay : 0.543 +Clock Skew : -0.152 +Data Delay : 0.416 -Slack : 0.633 -From Node : ula:ula_|video:video_|frame[0] -To Node : ula:ula_|video:video_|frame[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.753 - -Slack : 0.636 -From Node : ula:ula_|video:video_|frame[0] -To Node : ula:ula_|video:video_|frame[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.756 - -Slack : 0.641 +Slack : 0.532 From Node : ula:ula_|video:video_|vga_hc[6] To Node : ula:ula_|video:video_|vram_address[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.041 -Data Delay : 0.766 +Clock Skew : 0.035 +Data Delay : 0.651 -Slack : 0.652 -From Node : ula:ula_|video:video_|vga_hc[5] -To Node : ula:ula_|video:video_|vga_hc[5] +Slack : 0.533 +From Node : ula:ula_|video:video_|vga_hc[6] +To Node : ula:ula_|video:video_|vram_address[2] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.773 +Clock Skew : 0.035 +Data Delay : 0.652 -Slack : 0.661 -From Node : ula:ula_|video:video_|vga_vc[6] -To Node : ula:ula_|video:video_|vram_address[7] +Slack : 0.536 +From Node : ula:ula_|video:video_|vga_hc[6] +To Node : ula:ula_|video:video_|vram_address[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.042 -Data Delay : 0.787 +Clock Skew : 0.035 +Data Delay : 0.655 -Slack : 0.673 -From Node : ula:ula_|video:video_|vga_vc[4] -To Node : ula:ula_|video:video_|vram_address[6] +Slack : 0.548 +From Node : ula:ula_|video:video_|bits_prefetch[3] +To Node : ula:ula_|video:video_|bits[3] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.042 -Data Delay : 0.799 +Clock Skew : -0.152 +Data Delay : 0.480 -Slack : 0.674 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|vga_hc[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.795 - -Slack : 0.680 -From Node : ula:ula_|video:video_|vga_vc[3] -To Node : ula:ula_|video:video_|vram_address[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.042 -Data Delay : 0.806 - -Slack : 0.683 -From Node : ula:ula_|video:video_|vga_vc[3] -To Node : ula:ula_|video:video_|vram_address[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.042 -Data Delay : 0.809 - -Slack : 0.686 -From Node : ula:ula_|video:video_|bits_prefetch[0] -To Node : ula:ula_|video:video_|bits[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.160 -Data Delay : 0.610 - -Slack : 0.691 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|vram_address[12] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.812 - -Slack : 0.691 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|vram_address[9] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.812 - -Slack : 0.691 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|vram_address[11] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.812 - -Slack : 0.691 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|vram_address[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.812 - -Slack : 0.693 -From Node : ula:ula_|video:video_|vga_vc[5] -To Node : ula:ula_|video:video_|vram_address[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.042 -Data Delay : 0.819 - -Slack : 0.694 -From Node : ula:ula_|video:video_|attr_prefetch[3] -To Node : ula:ula_|video:video_|attr[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.174 -Data Delay : 0.604 - -Slack : 0.695 +Slack : 0.548 From Node : ula:ula_|video:video_|bits_prefetch[4] To Node : ula:ula_|video:video_|bits[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : -0.160 -Data Delay : 0.619 +Clock Skew : -0.152 +Data Delay : 0.480 -Slack : 0.699 -From Node : ula:ula_|video:video_|frame[0] -To Node : ula:ula_|video:video_|frame[4] +Slack : 0.548 +From Node : ula:ula_|video:video_|vga_hc[5] +To Node : ula:ula_|video:video_|vram_address[1] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.036 -Data Delay : 0.819 +Clock Skew : 0.035 +Data Delay : 0.667 -Slack : 0.702 -From Node : ula:ula_|video:video_|attr_prefetch[5] -To Node : ula:ula_|video:video_|attr[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.174 -Data Delay : 0.612 - -Slack : 0.703 +Slack : 0.559 From Node : ula:ula_|video:video_|vga_hc[1] To Node : ula:ula_|video:video_|vram_address[10] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.824 +Clock Skew : 0.036 +Data Delay : 0.679 -Slack : 0.707 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : ula:ula_|video:video_|vga_hc[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.828 - -Slack : 0.709 -From Node : ula:ula_|video:video_|attr_prefetch[7] -To Node : ula:ula_|video:video_|attr[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.174 -Data Delay : 0.619 - -Slack : 0.709 -From Node : ula:ula_|video:video_|vga_hc[9] -To Node : ula:ula_|video:video_|vga_hc[9] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.830 - -Slack : 0.709 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : ula:ula_|video:video_|vram_address[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.042 -Data Delay : 0.835 - -Slack : 0.710 -From Node : ula:ula_|video:video_|vga_hc[9] -To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.831 - -Slack : 0.712 -From Node : ula:ula_|video:video_|attr_prefetch[4] -To Node : ula:ula_|video:video_|attr[4] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.175 -Data Delay : 0.621 - -Slack : 0.712 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : ula:ula_|video:video_|vram_address[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.042 -Data Delay : 0.838 - -Slack : 0.729 -From Node : ula:ula_|video:video_|attr_prefetch[0] -To Node : ula:ula_|video:video_|attr[0] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.175 -Data Delay : 0.638 - -Slack : 0.736 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : ula:ula_|video:video_|vga_hc[9] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.039 -Data Delay : 0.859 - -Slack : 0.736 -From Node : ula:ula_|video:video_|vga_vc[4] -To Node : ula:ula_|video:video_|vram_address[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.042 -Data Delay : 0.862 - -Slack : 0.744 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.039 -Data Delay : 0.867 - -Slack : 0.746 -From Node : ula:ula_|video:video_|vga_vc[3] -To Node : ula:ula_|video:video_|vram_address[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.042 -Data Delay : 0.872 - -Slack : 0.755 -From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|vga_hc[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.876 - -Slack : 0.755 -From Node : ula:ula_|video:video_|vga_vc[0] -To Node : ula:ula_|video:video_|vram_address[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.042 -Data Delay : 0.881 - -Slack : 0.758 -From Node : ula:ula_|video:video_|vga_vc[0] -To Node : ula:ula_|video:video_|vram_address[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.042 -Data Delay : 0.884 - -Slack : 0.771 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|vram_address[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.042 -Data Delay : 0.897 - -Slack : 0.774 -From Node : ula:ula_|video:video_|vga_vc[1] -To Node : ula:ula_|video:video_|vram_address[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.042 -Data Delay : 0.900 - -Slack : 0.775 -From Node : ula:ula_|video:video_|vga_vc[2] -To Node : ula:ula_|video:video_|vram_address[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.042 -Data Delay : 0.901 - -Slack : 0.794 -From Node : ula:ula_|video:video_|vga_hc[6] -To Node : ula:ula_|video:video_|vga_hc[8] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.915 - -Slack : 0.803 +Slack : 0.560 From Node : ula:ula_|video:video_|bits_prefetch[7] To Node : ula:ula_|video:video_|bits[7] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : -0.160 -Data Delay : 0.727 +Clock Skew : -0.152 +Data Delay : 0.492 -Slack : 0.809 +Slack : 0.562 +From Node : ula:ula_|video:video_|vga_hc[4] +To Node : ula:ula_|video:video_|vram_address[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.035 +Data Delay : 0.681 + +Slack : 0.565 +From Node : ula:ula_|video:video_|vga_vc[4] +To Node : ula:ula_|video:video_|vram_address[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.035 +Data Delay : 0.684 + +Slack : 0.569 +From Node : ula:ula_|video:video_|bits_prefetch[2] +To Node : ula:ula_|video:video_|bits[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.152 +Data Delay : 0.501 + +Slack : 0.575 +From Node : ula:ula_|video:video_|attr_prefetch[7] +To Node : ula:ula_|video:video_|attr[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.166 +Data Delay : 0.493 + +Slack : 0.576 +From Node : ula:ula_|video:video_|attr_prefetch[3] +To Node : ula:ula_|video:video_|attr[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.166 +Data Delay : 0.494 + +Slack : 0.592 +From Node : ula:ula_|video:video_|frame[0] +To Node : ula:ula_|video:video_|frame[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.038 +Data Delay : 0.714 + +Slack : 0.606 +From Node : ula:ula_|video:video_|attr_prefetch[0] +To Node : ula:ula_|video:video_|attr[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.166 +Data Delay : 0.524 + +Slack : 0.615 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|vram_address[12] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.735 + +Slack : 0.615 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|vram_address[11] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.735 + +Slack : 0.645 +From Node : ula:ula_|video:video_|bits_prefetch[6] +To Node : ula:ula_|video:video_|bits[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.152 +Data Delay : 0.577 + +Slack : 0.652 +From Node : ula:ula_|video:video_|vga_vc[5] +To Node : ula:ula_|video:video_|vram_address[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.035 +Data Delay : 0.771 + +Slack : 0.659 From Node : ula:ula_|video:video_|vga_hc[8] -To Node : ula:ula_|video:video_|vga_hc[9] +To Node : ula:ula_|video:video_|vram_address[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.039 -Data Delay : 0.932 +Clock Skew : 0.036 +Data Delay : 0.779 -Slack : 0.811 -From Node : ula:ula_|video:video_|attr_prefetch[2] -To Node : ula:ula_|video:video_|attr[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.174 -Data Delay : 0.721 - -Slack : 0.821 -From Node : ula:ula_|video:video_|vga_vc[0] -To Node : ula:ula_|video:video_|vram_address[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.042 -Data Delay : 0.947 - -Slack : 0.824 +Slack : 0.662 From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|vga_hc[8] +To Node : ula:ula_|video:video_|vram_address[9] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.945 +Clock Skew : 0.036 +Data Delay : 0.782 -Slack : 0.828 -From Node : ula:ula_|video:video_|attr_prefetch[6] -To Node : ula:ula_|video:video_|attr[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : -0.178 -Data Delay : 0.734 - -Slack : 0.832 +Slack : 0.662 From Node : ula:ula_|video:video_|vga_hc[2] -To Node : ula:ula_|video:video_|vga_hc[6] +To Node : ula:ula_|video:video_|vram_address[8] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.953 +Clock Skew : 0.036 +Data Delay : 0.782 -Slack : 0.833 -From Node : ula:ula_|video:video_|vga_hc[7] -To Node : ula:ula_|video:video_|vram_address[3] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.041 -Data Delay : 0.958 - -Slack : 0.833 +Slack : 0.663 From Node : ula:ula_|video:video_|vga_hc[7] To Node : ula:ula_|video:video_|vram_address[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.041 -Data Delay : 0.958 +Clock Skew : 0.035 +Data Delay : 0.782 -Slack : 0.834 +Slack : 0.663 +From Node : ula:ula_|video:video_|vga_hc[7] +To Node : ula:ula_|video:video_|vram_address[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.035 +Data Delay : 0.782 + +Slack : 0.664 +From Node : ula:ula_|video:video_|vga_vc[6] +To Node : ula:ula_|video:video_|vram_address[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.035 +Data Delay : 0.783 + +Slack : 0.669 +From Node : ula:ula_|video:video_|vga_hc[7] +To Node : ula:ula_|video:video_|vga_hc[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.790 + +Slack : 0.671 +From Node : ula:ula_|video:video_|vga_hc[6] +To Node : ula:ula_|video:video_|vga_hc[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.792 + +Slack : 0.678 +From Node : ula:ula_|video:video_|attr_prefetch[4] +To Node : ula:ula_|video:video_|attr[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.166 +Data Delay : 0.596 + +Slack : 0.684 +From Node : ula:ula_|video:video_|attr_prefetch[6] +To Node : ula:ula_|video:video_|attr[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.166 +Data Delay : 0.602 + +Slack : 0.687 +From Node : ula:ula_|video:video_|vga_vc[9] +To Node : ula:ula_|video:video_|frame[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.807 + +Slack : 0.709 +From Node : ula:ula_|video:video_|attr_prefetch[5] +To Node : ula:ula_|video:video_|attr[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.166 +Data Delay : 0.627 + +Slack : 0.714 +From Node : ula:ula_|video:video_|vga_vc[4] +To Node : ula:ula_|video:video_|vram_address[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.035 +Data Delay : 0.833 + +Slack : 0.728 From Node : ula:ula_|video:video_|vga_hc[8] To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.039 -Data Delay : 0.957 +Clock Skew : 0.036 +Data Delay : 0.848 + +Slack : 0.736 +From Node : ula:ula_|video:video_|vga_hc[3] +To Node : ula:ula_|video:video_|vram_address[10] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.035 +Data Delay : 0.855 + +Slack : 0.744 +From Node : ula:ula_|video:video_|frame[0] +To Node : ula:ula_|video:video_|frame[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.038 +Data Delay : 0.866 + +Slack : 0.744 +From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[0] +To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.864 + +Slack : 0.747 +From Node : ula:ula_|video:video_|frame[0] +To Node : ula:ula_|video:video_|frame[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.038 +Data Delay : 0.869 + +Slack : 0.764 +From Node : ula:ula_|video:video_|frame[4] +To Node : ula:ula_|video:video_|frame[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.885 + +Slack : 0.767 +From Node : ula:ula_|video:video_|vga_hc[6] +To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.035 +Data Delay : 0.886 + +Slack : 0.777 +From Node : ula:ula_|video:video_|vga_vc[4] +To Node : ula:ula_|video:video_|vram_address[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.035 +Data Delay : 0.896 + +Slack : 0.784 +From Node : ula:ula_|video:video_|frame[3] +To Node : ula:ula_|video:video_|frame[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.904 + +Slack : 0.790 +From Node : ula:ula_|video:video_|vga_vc[8] +To Node : ula:ula_|video:video_|vram_address[9] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.911 + +Slack : 0.791 +From Node : ula:ula_|video:video_|vga_vc[8] +To Node : ula:ula_|video:video_|vram_address[12] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.912 + +Slack : 0.804 +From Node : ula:ula_|video:video_|vga_hc[0] +To Node : ula:ula_|video:video_|vram_address[10] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.155 +Data Delay : 0.733 + +Slack : 0.811 +From Node : ula:ula_|video:video_|vga_vc[5] +To Node : ula:ula_|video:video_|vram_address[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.035 +Data Delay : 0.930 + +Slack : 0.829 +From Node : ula:ula_|video:video_|vga_hc[6] +To Node : ula:ula_|video:video_|vga_hc[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.950 Slack : 0.836 -From Node : ula:ula_|video:video_|vga_hc[2] +From Node : ula:ula_|video:video_|frame[2] +To Node : ula:ula_|video:video_|frame[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.956 + +Slack : 0.849 +From Node : ula:ula_|video:video_|frame[1] +To Node : ula:ula_|video:video_|frame[4] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.969 + +Slack : 0.863 +From Node : ula:ula_|video:video_|vga_hc[3] To Node : ula:ula_|video:video_|vga_hc[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 Clock Skew : 0.037 -Data Delay : 0.957 +Data Delay : 0.984 -Slack : 0.837 +Slack : 0.876 +From Node : ula:ula_|video:video_|vga_vc[0] +To Node : ula:ula_|video:video_|vram_address[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.996 + +Slack : 0.879 +From Node : ula:ula_|video:video_|vga_vc[0] +To Node : ula:ula_|video:video_|vram_address[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.999 + +Slack : 0.887 +From Node : ula:ula_|video:video_|vga_hc[3] +To Node : ula:ula_|video:video_|vga_hc[3] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 1.008 + +Slack : 0.888 +From Node : ula:ula_|video:video_|vga_vc[2] +To Node : ula:ula_|video:video_|vram_address[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 1.008 + +Slack : 0.891 +From Node : ula:ula_|video:video_|vga_hc[2] +To Node : ula:ula_|video:video_|vram_address[10] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 1.011 + +Slack : 0.891 +From Node : ula:ula_|video:video_|vga_vc[2] +To Node : ula:ula_|video:video_|vram_address[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 1.011 + +Slack : 0.894 +From Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1 +To Node : ula:ula_|video:video_|VGA_VS +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.020 +Data Delay : 0.970 + +Slack : 0.902 +From Node : ula:ula_|video:video_|attr_prefetch[2] +To Node : ula:ula_|video:video_|attr[2] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.166 +Data Delay : 0.820 + +Slack : 0.908 From Node : ula:ula_|video:video_|vga_vc[1] +To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.038 +Data Delay : 1.030 + +Slack : 0.909 +From Node : ula:ula_|video:video_|vga_hc[9] +To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.035 +Data Delay : 1.028 + +Slack : 0.919 +From Node : ula:ula_|video:video_|bits_prefetch[0] +To Node : ula:ula_|video:video_|bits[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.152 +Data Delay : 0.851 + +Slack : 0.927 +From Node : ula:ula_|video:video_|vga_vc[3] +To Node : ula:ula_|video:video_|vram_address[5] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 1.047 + +Slack : 0.928 +From Node : ula:ula_|video:video_|vga_vc[7] +To Node : ula:ula_|video:video_|frame[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 1.048 + +Slack : 0.930 +From Node : ula:ula_|video:video_|vga_vc[3] +To Node : ula:ula_|video:video_|vram_address[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 1.050 + +Slack : 0.939 +From Node : ula:ula_|video:video_|vga_vc[0] +To Node : ula:ula_|video:video_|vram_address[8] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 1.060 + +Slack : 0.942 +From Node : ula:ula_|video:video_|vga_vc[0] To Node : ula:ula_|video:video_|vram_address[7] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.042 -Data Delay : 0.963 +Clock Skew : 0.036 +Data Delay : 1.062 -Slack : 0.841 -From Node : ula:ula_|video:video_|vga_hc[4] -To Node : ula:ula_|video:video_|vga_hc[9] +Slack : 0.943 +From Node : ula:ula_|video:video_|vga_vc[9] +To Node : ula:ula_|video:video_|frame[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.039 -Data Delay : 0.964 +Clock Skew : 0.036 +Data Delay : 1.063 -Slack : 0.845 +Slack : 0.949 +From Node : ula:ula_|video:video_|vga_hc[5] +To Node : ula:ula_|video:video_|vga_hc[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 1.070 + +Slack : 0.954 +From Node : ula:ula_|video:video_|vga_vc[2] +To Node : ula:ula_|video:video_|vram_address[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 1.074 + +Slack : 0.962 +From Node : ula:ula_|video:video_|vga_vc[9] +To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 1.083 + +Slack : 0.968 +From Node : ula:ula_|video:video_|vga_vc[2] +To Node : ula:ula_|video:video_|vram_address[9] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 1.089 + +Slack : 0.979 +From Node : ula:ula_|video:video_|vga_hc[5] +To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1 +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.035 +Data Delay : 1.098 + +Slack : 0.987 +From Node : ula:ula_|video:video_|vga_vc[0] +To Node : ula:ula_|video:video_|vga_vc[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 1.108 + +Slack : 0.987 +From Node : ula:ula_|video:video_|vga_vc[4] +To Node : ula:ula_|video:video_|frame[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 1.107 + +Slack : 0.989 +From Node : ula:ula_|video:video_|attr_prefetch[1] +To Node : ula:ula_|video:video_|attr[1] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : -0.166 +Data Delay : 0.907 + +Slack : 0.990 +From Node : ula:ula_|video:video_|vga_vc[7] +To Node : ula:ula_|video:video_|vram_address[8] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 1.110 + +Slack : 0.992 +From Node : ula:ula_|video:video_|vga_vc[7] +To Node : ula:ula_|video:video_|vram_address[11] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 1.112 + +Slack : 0.993 +From Node : ula:ula_|video:video_|vga_vc[3] +To Node : ula:ula_|video:video_|vram_address[7] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 1.113 + +Slack : 0.996 +From Node : ula:ula_|video:video_|vga_hc[3] +To Node : ula:ula_|video:video_|vga_hc[6] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 1.117 + +Slack : 1.006 +From Node : ula:ula_|video:video_|vga_vc[8] +To Node : ula:ula_|video:video_|frame[0] +Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 1.127 + +Slack : 1.008 From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|attr_prefetch[1] +To Node : ula:ula_|video:video_|vga_hc[4] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.257 -Data Delay : 1.186 +Clock Skew : -0.153 +Data Delay : 0.939 -Slack : 0.845 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|attr_prefetch[4] +Slack : 1.012 +From Node : ula:ula_|video:video_|vga_hc[5] +To Node : ula:ula_|video:video_|vga_hc[7] Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Relationship : 0.000 -Clock Skew : 0.257 -Data Delay : 1.186 - -Slack : 0.845 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|attr_prefetch[7] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.257 -Data Delay : 1.186 - -Slack : 0.845 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|attr_prefetch[6] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.257 -Data Delay : 1.186 - -Slack : 0.845 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|attr_prefetch[2] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.257 -Data Delay : 1.186 - -Slack : 0.845 -From Node : ula:ula_|video:video_|vga_hc[0] -To Node : ula:ula_|video:video_|attr_prefetch[5] -Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Relationship : 0.000 -Clock Skew : 0.257 -Data Delay : 1.186 +Clock Skew : 0.037 +Data Delay : 1.133 +--------------------------------------------------------------------------------+ @@ -26733,743 +26733,743 @@ Data Delay : 1.186 +--------------------------------------------------------------------------------+ ; Fast 1200mV 0C Model Recovery: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ; +--------------------------------------------------------------------------------+ -Slack : -4.693 +Slack : -4.728 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[17] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.225 -Data Delay : 2.791 +Data Delay : 2.826 -Slack : -4.693 +Slack : -4.728 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_1 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.227 -Data Delay : 2.789 +Data Delay : 2.824 -Slack : -4.693 +Slack : -4.728 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.230 -Data Delay : 2.786 +Data Delay : 2.821 -Slack : -4.692 +Slack : -4.727 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.226 -Data Delay : 2.789 +Data Delay : 2.824 -Slack : -4.692 +Slack : -4.727 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.228 -Data Delay : 2.787 +Data Delay : 2.822 -Slack : -4.583 +Slack : -4.618 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.248 -Data Delay : 2.659 +Data Delay : 2.694 -Slack : -4.575 +Slack : -4.610 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.251 -Data Delay : 2.648 +Data Delay : 2.683 -Slack : -4.430 +Slack : -4.465 From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.229 -Data Delay : 2.572 +Clock Skew : -0.222 +Data Delay : 2.614 -Slack : -4.430 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.229 -Data Delay : 2.572 - -Slack : -4.430 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.229 -Data Delay : 2.572 - -Slack : -4.430 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.229 -Data Delay : 2.572 - -Slack : -4.430 +Slack : -4.465 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.229 -Data Delay : 2.572 +Clock Skew : -0.222 +Data Delay : 2.614 -Slack : -4.430 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.229 -Data Delay : 2.572 - -Slack : -4.430 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.229 -Data Delay : 2.572 - -Slack : -4.430 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.229 -Data Delay : 2.572 - -Slack : -4.430 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.229 -Data Delay : 2.572 - -Slack : -4.430 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.229 -Data Delay : 2.572 - -Slack : -4.430 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.229 -Data Delay : 2.572 - -Slack : -4.430 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.229 -Data Delay : 2.572 - -Slack : -4.430 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.229 -Data Delay : 2.572 - -Slack : -4.430 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.229 -Data Delay : 2.572 - -Slack : -4.430 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.229 -Data Delay : 2.572 - -Slack : -4.429 +Slack : -4.465 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.229 -Data Delay : 2.571 +Clock Skew : -0.222 +Data Delay : 2.614 -Slack : -4.429 +Slack : -4.465 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.222 +Data Delay : 2.614 + +Slack : -4.465 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.229 -Data Delay : 2.571 +Clock Skew : -0.222 +Data Delay : 2.614 -Slack : -4.429 +Slack : -4.465 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.226 -Data Delay : 2.574 +Clock Skew : -0.222 +Data Delay : 2.614 -Slack : -4.429 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.226 -Data Delay : 2.574 - -Slack : -4.429 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.226 -Data Delay : 2.574 - -Slack : -4.429 +Slack : -4.465 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.229 -Data Delay : 2.571 +Data Delay : 2.607 -Slack : -4.429 +Slack : -4.465 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.229 -Data Delay : 2.571 +Data Delay : 2.607 -Slack : -4.429 +Slack : -4.465 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.227 +Data Delay : 2.609 + +Slack : -4.465 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.227 +Data Delay : 2.609 + +Slack : -4.465 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.227 +Data Delay : 2.609 + +Slack : -4.465 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.227 +Data Delay : 2.609 + +Slack : -4.465 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.227 +Data Delay : 2.609 + +Slack : -4.465 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.227 +Data Delay : 2.609 + +Slack : -4.465 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.227 +Data Delay : 2.609 + +Slack : -4.465 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.222 +Data Delay : 2.614 + +Slack : -4.465 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.222 +Data Delay : 2.614 + +Slack : -4.465 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.222 +Data Delay : 2.614 + +Slack : -4.465 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.222 +Data Delay : 2.614 + +Slack : -4.465 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.222 +Data Delay : 2.614 + +Slack : -4.465 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.222 +Data Delay : 2.614 + +Slack : -4.465 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.222 +Data Delay : 2.614 + +Slack : -4.465 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.222 +Data Delay : 2.614 + +Slack : -4.465 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.222 +Data Delay : 2.614 + +Slack : -4.465 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.222 +Data Delay : 2.614 + +Slack : -4.465 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.222 +Data Delay : 2.614 + +Slack : -4.465 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.222 +Data Delay : 2.614 + +Slack : -4.465 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.222 +Data Delay : 2.614 + +Slack : -4.465 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.222 +Data Delay : 2.614 + +Slack : -4.465 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.222 +Data Delay : 2.614 + +Slack : -4.465 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.222 +Data Delay : 2.614 + +Slack : -4.465 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.222 +Data Delay : 2.614 + +Slack : -4.464 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.221 +Data Delay : 2.614 + +Slack : -4.464 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.221 +Data Delay : 2.614 + +Slack : -4.464 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.221 +Data Delay : 2.614 + +Slack : -4.464 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.221 +Data Delay : 2.614 + +Slack : -4.464 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.221 +Data Delay : 2.614 + +Slack : -4.464 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.221 +Data Delay : 2.614 + +Slack : -4.464 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.226 +Data Delay : 2.609 + +Slack : -4.464 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.226 +Data Delay : 2.609 + +Slack : -4.464 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : 0.424 +Clock Skew : -0.226 +Data Delay : 2.609 + +Slack : -4.464 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.226 -Data Delay : 2.574 +Data Delay : 2.609 -Slack : -4.429 +Slack : -4.464 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.226 -Data Delay : 2.574 +Data Delay : 2.609 -Slack : -4.429 +Slack : -4.464 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.226 -Data Delay : 2.574 +Data Delay : 2.609 -Slack : -4.429 +Slack : -4.464 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.226 -Data Delay : 2.574 +Data Delay : 2.609 -Slack : -4.429 +Slack : -4.464 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.226 -Data Delay : 2.574 +Data Delay : 2.609 -Slack : -4.429 +Slack : -4.464 From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.226 -Data Delay : 2.574 +Data Delay : 2.609 -Slack : -4.429 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.226 -Data Delay : 2.574 - -Slack : -4.429 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.226 -Data Delay : 2.574 - -Slack : -4.429 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.226 -Data Delay : 2.574 - -Slack : -4.429 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.226 -Data Delay : 2.574 - -Slack : -4.429 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.226 -Data Delay : 2.574 - -Slack : -4.429 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.226 -Data Delay : 2.574 - -Slack : -4.429 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.226 -Data Delay : 2.574 - -Slack : -4.429 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.226 -Data Delay : 2.574 - -Slack : -4.429 +Slack : -4.464 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.226 -Data Delay : 2.574 +Data Delay : 2.609 -Slack : -4.429 +Slack : -4.464 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.226 -Data Delay : 2.574 +Data Delay : 2.609 -Slack : -4.429 +Slack : -4.278 From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.229 -Data Delay : 2.571 - -Slack : -4.429 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.229 -Data Delay : 2.571 - -Slack : -4.429 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.229 -Data Delay : 2.571 - -Slack : -4.429 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.228 -Data Delay : 2.572 - -Slack : -4.251 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.044 -Data Delay : 2.578 - -Slack : -4.240 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.041 -Data Delay : 2.570 - -Slack : -4.240 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.041 -Data Delay : 2.570 - -Slack : -4.239 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.040 -Data Delay : 2.570 +Data Delay : 2.609 -Slack : -4.239 +Slack : -4.278 From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.040 -Data Delay : 2.570 +Data Delay : 2.609 -Slack : -4.239 +Slack : -4.278 From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.040 -Data Delay : 2.570 +Data Delay : 2.609 -Slack : -4.239 +Slack : -4.278 From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.040 -Data Delay : 2.570 +Data Delay : 2.609 -Slack : -4.239 +Slack : -4.278 From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] +To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 Clock Skew : -0.040 -Data Delay : 2.570 +Data Delay : 2.609 -Slack : -4.239 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.040 -Data Delay : 2.570 - -Slack : -4.239 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.040 -Data Delay : 2.570 - -Slack : -4.239 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.040 -Data Delay : 2.570 - -Slack : -4.239 +Slack : -4.274 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.039 -Data Delay : 2.571 +Clock Skew : -0.038 +Data Delay : 2.607 -Slack : -4.238 +Slack : -4.274 From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.037 -Data Delay : 2.572 +Clock Skew : -0.036 +Data Delay : 2.609 -Slack : -4.236 +Slack : -4.274 From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.029 -Data Delay : 2.578 +Clock Skew : -0.036 +Data Delay : 2.609 -Slack : -4.236 +Slack : -4.273 From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.029 -Data Delay : 2.578 +Clock Skew : -0.030 +Data Delay : 2.614 -Slack : -4.236 +Slack : -4.265 From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] +To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.029 -Data Delay : 2.578 +Clock Skew : -0.021 +Data Delay : 2.615 -Slack : -4.236 +Slack : -4.265 From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.029 -Data Delay : 2.578 +Clock Skew : -0.021 +Data Delay : 2.615 -Slack : -4.236 +Slack : -4.265 From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.029 -Data Delay : 2.578 +Clock Skew : -0.021 +Data Delay : 2.615 -Slack : -4.236 +Slack : -4.265 From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.029 -Data Delay : 2.578 +Clock Skew : -0.021 +Data Delay : 2.615 -Slack : -4.236 +Slack : -4.265 From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.029 -Data Delay : 2.578 +Clock Skew : -0.022 +Data Delay : 2.614 -Slack : -4.236 +Slack : -4.259 From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.029 -Data Delay : 2.578 +Clock Skew : -0.016 +Data Delay : 2.614 -Slack : -4.236 +Slack : -4.259 From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.029 -Data Delay : 2.578 +Clock Skew : -0.016 +Data Delay : 2.614 -Slack : -4.236 +Slack : -4.259 From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.029 -Data Delay : 2.578 +Clock Skew : -0.016 +Data Delay : 2.614 -Slack : -4.236 +Slack : -4.259 From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.029 -Data Delay : 2.578 +Clock Skew : -0.016 +Data Delay : 2.614 -Slack : -4.236 +Slack : -4.259 From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.029 -Data Delay : 2.578 +Clock Skew : -0.016 +Data Delay : 2.614 -Slack : -4.236 +Slack : -4.259 From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.424 -Clock Skew : -0.029 -Data Delay : 2.578 +Clock Skew : -0.016 +Data Delay : 2.614 -Slack : -4.236 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : 0.424 -Clock Skew : -0.029 -Data Delay : 2.578 - -Slack : -4.201 +Slack : -4.237 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.421 Clock Skew : 0.002 -Data Delay : 2.571 +Data Delay : 2.607 -Slack : -4.201 +Slack : -4.237 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.421 Clock Skew : 0.002 -Data Delay : 2.571 +Data Delay : 2.607 -Slack : -4.201 +Slack : -4.237 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.421 Clock Skew : 0.002 -Data Delay : 2.571 +Data Delay : 2.607 -Slack : -4.201 +Slack : -4.237 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.421 Clock Skew : 0.002 -Data Delay : 2.571 +Data Delay : 2.607 -Slack : -4.201 +Slack : -4.237 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.421 Clock Skew : 0.002 -Data Delay : 2.571 +Data Delay : 2.607 -Slack : -4.201 +Slack : -4.237 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : 0.421 Clock Skew : 0.002 -Data Delay : 2.571 +Data Delay : 2.607 +--------------------------------------------------------------------------------+ @@ -27477,743 +27477,743 @@ Data Delay : 2.571 +--------------------------------------------------------------------------------+ ; Fast 1200mV 0C Model Removal: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ; +--------------------------------------------------------------------------------+ -Slack : 2.518 +Slack : 2.503 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.003 -Clock Skew : 0.256 -Data Delay : 1.945 +Clock Skew : 0.257 +Data Delay : 1.931 -Slack : 2.518 +Slack : 2.503 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.003 -Clock Skew : 0.256 -Data Delay : 1.945 +Clock Skew : 0.257 +Data Delay : 1.931 -Slack : 2.518 +Slack : 2.503 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.003 -Clock Skew : 0.256 -Data Delay : 1.945 +Clock Skew : 0.257 +Data Delay : 1.931 -Slack : 2.518 +Slack : 2.503 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.003 -Clock Skew : 0.256 -Data Delay : 1.945 +Clock Skew : 0.257 +Data Delay : 1.931 -Slack : 2.518 +Slack : 2.503 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.003 -Clock Skew : 0.256 -Data Delay : 1.945 +Clock Skew : 0.257 +Data Delay : 1.931 -Slack : 2.518 +Slack : 2.503 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.003 -Clock Skew : 0.256 -Data Delay : 1.945 +Clock Skew : 0.257 +Data Delay : 1.931 -Slack : 2.559 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.224 -Data Delay : 1.951 - -Slack : 2.559 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.224 -Data Delay : 1.951 - -Slack : 2.559 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.224 -Data Delay : 1.951 - -Slack : 2.559 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.224 -Data Delay : 1.951 - -Slack : 2.559 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.224 -Data Delay : 1.951 - -Slack : 2.559 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.224 -Data Delay : 1.951 - -Slack : 2.559 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.224 -Data Delay : 1.951 - -Slack : 2.559 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.224 -Data Delay : 1.951 - -Slack : 2.559 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.224 -Data Delay : 1.951 - -Slack : 2.559 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.224 -Data Delay : 1.951 - -Slack : 2.559 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.224 -Data Delay : 1.951 - -Slack : 2.559 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.224 -Data Delay : 1.951 - -Slack : 2.559 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.224 -Data Delay : 1.951 - -Slack : 2.559 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.224 -Data Delay : 1.951 - -Slack : 2.562 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.215 -Data Delay : 1.945 - -Slack : 2.563 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.212 -Data Delay : 1.943 - -Slack : 2.563 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.212 -Data Delay : 1.943 - -Slack : 2.564 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.212 -Data Delay : 1.944 - -Slack : 2.564 +Slack : 2.532 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.212 -Data Delay : 1.944 +Clock Skew : 0.238 +Data Delay : 1.938 -Slack : 2.564 +Slack : 2.532 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.238 +Data Delay : 1.938 + +Slack : 2.532 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.212 -Data Delay : 1.944 +Clock Skew : 0.238 +Data Delay : 1.938 -Slack : 2.564 +Slack : 2.532 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.212 -Data Delay : 1.944 +Clock Skew : 0.238 +Data Delay : 1.938 -Slack : 2.564 +Slack : 2.532 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.212 -Data Delay : 1.944 +Clock Skew : 0.238 +Data Delay : 1.938 -Slack : 2.564 +Slack : 2.532 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.212 -Data Delay : 1.944 +Clock Skew : 0.238 +Data Delay : 1.938 -Slack : 2.564 +Slack : 2.538 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.232 +Data Delay : 1.938 + +Slack : 2.538 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.232 +Data Delay : 1.938 + +Slack : 2.538 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.212 -Data Delay : 1.944 +Clock Skew : 0.232 +Data Delay : 1.938 -Slack : 2.564 +Slack : 2.538 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.212 -Data Delay : 1.944 +Clock Skew : 0.232 +Data Delay : 1.938 -Slack : 2.565 +Slack : 2.538 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.231 +Data Delay : 1.937 + +Slack : 2.547 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.223 +Data Delay : 1.938 + +Slack : 2.548 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.213 -Data Delay : 1.946 +Clock Skew : 0.215 +Data Delay : 1.931 -Slack : 2.574 +Slack : 2.548 From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.209 -Data Delay : 1.951 +Clock Skew : 0.217 +Data Delay : 1.933 -Slack : 2.761 +Slack : 2.548 From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.016 -Data Delay : 1.945 +Clock Skew : 0.217 +Data Delay : 1.933 -Slack : 2.761 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.016 -Data Delay : 1.945 - -Slack : 2.761 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.016 -Data Delay : 1.945 - -Slack : 2.761 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.016 -Data Delay : 1.945 - -Slack : 2.761 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.016 -Data Delay : 1.945 - -Slack : 2.761 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.015 -Data Delay : 1.944 - -Slack : 2.761 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.016 -Data Delay : 1.945 - -Slack : 2.761 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.015 -Data Delay : 1.944 - -Slack : 2.761 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.016 -Data Delay : 1.945 - -Slack : 2.761 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.016 -Data Delay : 1.945 - -Slack : 2.761 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.016 -Data Delay : 1.945 - -Slack : 2.761 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.018 -Data Delay : 1.947 - -Slack : 2.761 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.018 -Data Delay : 1.947 - -Slack : 2.761 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.018 -Data Delay : 1.947 - -Slack : 2.761 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.018 -Data Delay : 1.947 - -Slack : 2.761 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.018 -Data Delay : 1.947 - -Slack : 2.761 +Slack : 2.551 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.018 -Data Delay : 1.947 +Clock Skew : 0.213 +Data Delay : 1.932 -Slack : 2.761 +Slack : 2.551 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.018 -Data Delay : 1.947 +Clock Skew : 0.213 +Data Delay : 1.932 -Slack : 2.761 +Slack : 2.551 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.018 -Data Delay : 1.947 +Clock Skew : 0.213 +Data Delay : 1.932 -Slack : 2.761 +Slack : 2.551 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.018 -Data Delay : 1.947 +Clock Skew : 0.213 +Data Delay : 1.932 -Slack : 2.761 +Slack : 2.551 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.018 -Data Delay : 1.947 +Clock Skew : 0.213 +Data Delay : 1.932 -Slack : 2.761 +Slack : 2.746 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.023 +Data Delay : 1.937 + +Slack : 2.746 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.023 +Data Delay : 1.937 + +Slack : 2.746 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.023 +Data Delay : 1.937 + +Slack : 2.746 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.023 +Data Delay : 1.937 + +Slack : 2.746 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.023 +Data Delay : 1.937 + +Slack : 2.746 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.023 +Data Delay : 1.937 + +Slack : 2.746 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.023 +Data Delay : 1.937 + +Slack : 2.746 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.023 +Data Delay : 1.937 + +Slack : 2.746 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.023 +Data Delay : 1.937 + +Slack : 2.746 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.023 +Data Delay : 1.937 + +Slack : 2.746 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1 +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.023 +Data Delay : 1.937 + +Slack : 2.746 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.023 +Data Delay : 1.937 + +Slack : 2.746 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.018 -Data Delay : 1.947 +Data Delay : 1.932 -Slack : 2.761 +Slack : 2.746 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.018 -Data Delay : 1.947 +Data Delay : 1.932 -Slack : 2.761 +Slack : 2.746 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.018 -Data Delay : 1.947 +Data Delay : 1.932 -Slack : 2.761 +Slack : 2.746 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.018 -Data Delay : 1.947 +Data Delay : 1.932 -Slack : 2.761 +Slack : 2.746 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.018 -Data Delay : 1.947 +Data Delay : 1.932 -Slack : 2.761 +Slack : 2.746 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.018 -Data Delay : 1.947 +Data Delay : 1.932 -Slack : 2.761 +Slack : 2.746 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.018 -Data Delay : 1.947 +Data Delay : 1.932 -Slack : 2.761 +Slack : 2.746 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.023 +Data Delay : 1.937 + +Slack : 2.746 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.023 +Data Delay : 1.937 + +Slack : 2.746 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.023 +Data Delay : 1.937 + +Slack : 2.746 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.023 +Data Delay : 1.937 + +Slack : 2.746 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.023 +Data Delay : 1.937 + +Slack : 2.746 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.023 +Data Delay : 1.937 + +Slack : 2.746 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.023 +Data Delay : 1.937 + +Slack : 2.746 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.023 +Data Delay : 1.937 + +Slack : 2.746 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.023 +Data Delay : 1.937 + +Slack : 2.746 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.023 +Data Delay : 1.937 + +Slack : 2.746 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.023 +Data Delay : 1.937 + +Slack : 2.746 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.023 +Data Delay : 1.937 + +Slack : 2.746 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.023 +Data Delay : 1.937 + +Slack : 2.746 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.023 +Data Delay : 1.937 + +Slack : 2.746 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.023 +Data Delay : 1.937 + +Slack : 2.746 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.023 +Data Delay : 1.937 + +Slack : 2.746 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.023 +Data Delay : 1.937 + +Slack : 2.747 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.018 +Data Delay : 1.933 + +Slack : 2.747 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.018 +Data Delay : 1.933 + +Slack : 2.747 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.018 +Data Delay : 1.933 + +Slack : 2.747 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.018 +Data Delay : 1.933 + +Slack : 2.747 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.016 +Data Delay : 1.931 + +Slack : 2.747 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.016 +Data Delay : 1.931 + +Slack : 2.747 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.018 +Data Delay : 1.933 + +Slack : 2.747 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.018 +Data Delay : 1.933 + +Slack : 2.747 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.018 +Data Delay : 1.933 + +Slack : 2.747 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.018 +Data Delay : 1.933 + +Slack : 2.747 +From Node : KEY[0] +To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.018 +Data Delay : 1.933 + +Slack : 2.747 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.018 -Data Delay : 1.947 +Data Delay : 1.933 -Slack : 2.761 +Slack : 2.747 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.018 -Data Delay : 1.947 +Data Delay : 1.933 -Slack : 2.761 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.015 -Data Delay : 1.944 - -Slack : 2.761 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.015 -Data Delay : 1.944 - -Slack : 2.761 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.015 -Data Delay : 1.944 - -Slack : 2.761 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.016 -Data Delay : 1.945 - -Slack : 2.762 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.016 -Data Delay : 1.946 - -Slack : 2.762 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.016 -Data Delay : 1.946 - -Slack : 2.762 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.016 -Data Delay : 1.946 - -Slack : 2.762 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.016 -Data Delay : 1.946 - -Slack : 2.762 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.016 -Data Delay : 1.946 - -Slack : 2.762 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.016 -Data Delay : 1.946 - -Slack : 2.763 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.015 -Data Delay : 1.946 - -Slack : 2.763 -From Node : KEY[0] -To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.015 -Data Delay : 1.946 - -Slack : 2.897 +Slack : 2.882 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : -0.019 -Data Delay : 2.020 +Data Delay : 2.005 -Slack : 2.902 +Slack : 2.888 From Node : KEY[0] To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : -0.016 -Data Delay : 2.028 +Data Delay : 2.014 -Slack : 3.008 +Slack : 2.993 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[17] Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.009 -Data Delay : 2.157 +Data Delay : 2.142 -Slack : 3.008 -From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r -Launch Clock : CLOCK_50 -Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Relationship : -0.006 -Clock Skew : 0.007 -Data Delay : 2.155 - -Slack : 3.008 +Slack : 2.993 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_1 Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.007 -Data Delay : 2.155 +Data Delay : 2.140 -Slack : 3.008 +Slack : 2.994 From Node : KEY[0] -To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r +To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 -Clock Skew : 0.004 -Data Delay : 2.152 +Clock Skew : 0.007 +Data Delay : 2.141 -Slack : 3.009 +Slack : 2.994 From Node : KEY[0] To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r Launch Clock : CLOCK_50 Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Relationship : -0.006 Clock Skew : 0.005 -Data Delay : 2.154 +Data Delay : 2.139 + +Slack : 2.994 +From Node : KEY[0] +To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r +Launch Clock : CLOCK_50 +Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Relationship : -0.006 +Clock Skew : 0.004 +Data Delay : 2.138 +--------------------------------------------------------------------------------+ @@ -28243,7 +28243,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_address_reg0 Slack : 9.208 Actual Width : 9.438 @@ -28251,7 +28251,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_we_reg +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_we_reg Slack : 9.208 Actual Width : 9.438 @@ -28259,7 +28259,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_address_reg0 Slack : 9.208 Actual Width : 9.438 @@ -28267,7 +28267,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_we_reg +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_we_reg Slack : 9.208 Actual Width : 9.438 @@ -28275,7 +28275,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_address_reg0 Slack : 9.208 Actual Width : 9.438 @@ -28283,7 +28283,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_we_reg +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_we_reg Slack : 9.208 Actual Width : 9.438 @@ -28291,7 +28291,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_address_reg0 Slack : 9.208 Actual Width : 9.438 @@ -28299,7 +28299,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_we_reg +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_we_reg Slack : 9.209 Actual Width : 9.439 @@ -28349,6 +28349,22 @@ Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_we_reg +Slack : 9.209 +Actual Width : 9.439 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_address_reg0 + +Slack : 9.209 +Actual Width : 9.439 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_we_reg + Slack : 9.209 Actual Width : 9.439 Required Width : 0.230 @@ -28365,6 +28381,22 @@ Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_we_reg +Slack : 9.209 +Actual Width : 9.439 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_address_reg0 + +Slack : 9.209 +Actual Width : 9.439 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_we_reg + Slack : 9.209 Actual Width : 9.439 Required Width : 0.230 @@ -28381,22 +28413,6 @@ Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_we_reg -Slack : 9.209 -Actual Width : 9.439 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_address_reg0 - -Slack : 9.209 -Actual Width : 9.439 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_we_reg - Slack : 9.209 Actual Width : 9.439 Required Width : 0.230 @@ -28419,7 +28435,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_address_reg0 Slack : 9.209 Actual Width : 9.439 @@ -28427,7 +28443,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_we_reg +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_we_reg Slack : 9.209 Actual Width : 9.439 @@ -28435,7 +28451,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_address_reg0 Slack : 9.209 Actual Width : 9.439 @@ -28443,127 +28459,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_we_reg - -Slack : 9.209 -Actual Width : 9.439 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_address_reg0 - -Slack : 9.209 -Actual Width : 9.439 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_we_reg - -Slack : 9.209 -Actual Width : 9.439 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0 - -Slack : 9.209 -Actual Width : 9.439 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0 - -Slack : 9.209 -Actual Width : 9.439 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0 - -Slack : 9.209 -Actual Width : 9.439 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13~porta_address_reg0 - -Slack : 9.209 -Actual Width : 9.439 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 - -Slack : 9.209 -Actual Width : 9.439 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0 - -Slack : 9.209 -Actual Width : 9.439 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1~porta_address_reg0 - -Slack : 9.209 -Actual Width : 9.439 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2~porta_address_reg0 - -Slack : 9.209 -Actual Width : 9.439 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 - -Slack : 9.209 -Actual Width : 9.439 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 - -Slack : 9.209 -Actual Width : 9.439 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0 - -Slack : 9.209 -Actual Width : 9.439 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8~porta_address_reg0 - -Slack : 9.209 -Actual Width : 9.439 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_we_reg Slack : 9.210 Actual Width : 9.440 @@ -28579,7 +28475,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0 Slack : 9.210 Actual Width : 9.440 @@ -28587,7 +28483,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 Slack : 9.210 Actual Width : 9.440 @@ -28595,7 +28491,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0 Slack : 9.210 Actual Width : 9.440 @@ -28603,7 +28499,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_we_reg +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0 Slack : 9.210 Actual Width : 9.440 @@ -28611,7 +28507,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_datain_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_address_reg0 Slack : 9.210 Actual Width : 9.440 @@ -28619,135 +28515,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0 - -Slack : 9.210 -Actual Width : 9.440 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0 - -Slack : 9.210 -Actual Width : 9.440 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 - -Slack : 9.210 -Actual Width : 9.440 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 - -Slack : 9.210 -Actual Width : 9.440 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 - -Slack : 9.210 -Actual Width : 9.440 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 - -Slack : 9.210 -Actual Width : 9.440 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 - -Slack : 9.210 -Actual Width : 9.440 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 - -Slack : 9.210 -Actual Width : 9.440 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 - -Slack : 9.210 -Actual Width : 9.440 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2 - -Slack : 9.210 -Actual Width : 9.440 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 - -Slack : 9.210 -Actual Width : 9.440 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 - -Slack : 9.210 -Actual Width : 9.440 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5~porta_address_reg0 - -Slack : 9.210 -Actual Width : 9.440 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 - -Slack : 9.210 -Actual Width : 9.440 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 - -Slack : 9.210 -Actual Width : 9.440 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 - -Slack : 9.210 -Actual Width : 9.440 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_we_reg Slack : 9.211 Actual Width : 9.441 @@ -28773,6 +28541,14 @@ Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0 +Slack : 9.211 +Actual Width : 9.441 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0 + Slack : 9.211 Actual Width : 9.441 Required Width : 0.230 @@ -28787,15 +28563,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15 - -Slack : 9.211 -Actual Width : 9.441 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0 Slack : 9.211 Actual Width : 9.441 @@ -28805,14 +28573,6 @@ Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0 -Slack : 9.211 -Actual Width : 9.441 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0 - Slack : 9.211 Actual Width : 9.441 Required Width : 0.230 @@ -28827,7 +28587,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4 Slack : 9.211 Actual Width : 9.441 @@ -28835,7 +28595,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~PORTBDATAOUT0 Slack : 9.211 Actual Width : 9.441 @@ -28843,7 +28603,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 Slack : 9.211 Actual Width : 9.441 @@ -28851,7 +28611,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0 Slack : 9.211 Actual Width : 9.441 @@ -28859,15 +28619,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 - -Slack : 9.211 -Actual Width : 9.441 -Required Width : 0.230 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0 Slack : 9.212 Actual Width : 9.442 @@ -28893,6 +28645,30 @@ Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0 +Slack : 9.212 +Actual Width : 9.442 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1 + +Slack : 9.212 +Actual Width : 9.442 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10 + +Slack : 9.212 +Actual Width : 9.442 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0 + Slack : 9.212 Actual Width : 9.442 Required Width : 0.230 @@ -28925,6 +28701,54 @@ Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0 +Slack : 9.212 +Actual Width : 9.442 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14 + +Slack : 9.212 +Actual Width : 9.442 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0 + +Slack : 9.212 +Actual Width : 9.442 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15 + +Slack : 9.212 +Actual Width : 9.442 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0 + +Slack : 9.212 +Actual Width : 9.442 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~PORTBDATAOUT0 + +Slack : 9.212 +Actual Width : 9.442 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0 + Slack : 9.212 Actual Width : 9.442 Required Width : 0.230 @@ -28955,7 +28779,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3 Slack : 9.212 Actual Width : 9.442 @@ -28963,7 +28787,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~PORTBDATAOUT0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~PORTBDATAOUT0 Slack : 9.212 Actual Width : 9.442 @@ -28971,7 +28795,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0 Slack : 9.212 Actual Width : 9.442 @@ -28979,7 +28803,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0 +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7 Slack : 9.212 Actual Width : 9.442 @@ -28987,39 +28811,215 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~PORTBDATAOUT0 + +Slack : 9.212 +Actual Width : 9.442 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0 + +Slack : 9.212 +Actual Width : 9.442 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_datain_reg0 + +Slack : 9.213 +Actual Width : 9.443 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13 + +Slack : 9.213 +Actual Width : 9.443 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0 + +Slack : 9.213 +Actual Width : 9.443 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_datain_reg0 + +Slack : 9.213 +Actual Width : 9.443 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5 + +Slack : 9.213 +Actual Width : 9.443 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~PORTBDATAOUT0 + +Slack : 9.213 +Actual Width : 9.443 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0 + +Slack : 9.213 +Actual Width : 9.443 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6 -Slack : 9.212 -Actual Width : 9.442 +Slack : 9.213 +Actual Width : 9.443 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~PORTBDATAOUT0 -Slack : 9.212 -Actual Width : 9.442 +Slack : 9.213 +Actual Width : 9.443 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0 -Slack : 9.212 -Actual Width : 9.442 +Slack : 9.213 +Actual Width : 9.443 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8 -Slack : 9.212 -Actual Width : 9.442 +Slack : 9.213 +Actual Width : 9.443 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0 + +Slack : 9.213 +Actual Width : 9.443 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9 + +Slack : 9.213 +Actual Width : 9.443 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0 + +Slack : 9.214 +Actual Width : 9.444 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_datain_reg0 + +Slack : 9.214 +Actual Width : 9.444 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_datain_reg0 + +Slack : 9.214 +Actual Width : 9.444 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_datain_reg0 + +Slack : 9.214 +Actual Width : 9.444 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_datain_reg0 + +Slack : 9.214 +Actual Width : 9.444 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_datain_reg0 + +Slack : 9.214 +Actual Width : 9.444 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_datain_reg0 + +Slack : 9.214 +Actual Width : 9.444 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_datain_reg0 + +Slack : 9.214 +Actual Width : 9.444 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_datain_reg0 + +Slack : 9.214 +Actual Width : 9.444 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_datain_reg0 + +Slack : 9.214 +Actual Width : 9.444 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_datain_reg0 + +Slack : 9.215 +Actual Width : 9.445 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_datain_reg0 +--------------------------------------------------------------------------------+ @@ -29049,7 +29049,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_address_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_address_reg0 Slack : 19.609 Actual Width : 19.839 @@ -29057,7 +29057,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_we_reg +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_we_reg Slack : 19.609 Actual Width : 19.839 @@ -29065,7 +29065,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_address_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_address_reg0 Slack : 19.609 Actual Width : 19.839 @@ -29073,23 +29073,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_we_reg - -Slack : 19.609 -Actual Width : 19.839 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_address_reg0 - -Slack : 19.609 -Actual Width : 19.839 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_we_reg +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_we_reg Slack : 19.609 Actual Width : 19.839 @@ -29113,7 +29097,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_address_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_address_reg0 Slack : 19.609 Actual Width : 19.839 @@ -29121,7 +29105,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_we_reg +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_we_reg Slack : 19.609 Actual Width : 19.839 @@ -29129,7 +29113,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_address_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_address_reg0 Slack : 19.609 Actual Width : 19.839 @@ -29137,7 +29121,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_we_reg +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_we_reg Slack : 19.609 Actual Width : 19.839 @@ -29145,7 +29129,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_address_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0 Slack : 19.609 Actual Width : 19.839 @@ -29153,7 +29137,31 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_we_reg +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_we_reg + +Slack : 19.609 +Actual Width : 19.839 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_address_reg0 + +Slack : 19.609 +Actual Width : 19.839 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_we_reg + +Slack : 19.609 +Actual Width : 19.839 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0 Slack : 19.610 Actual Width : 19.840 @@ -29217,7 +29225,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_address_reg0 Slack : 19.610 Actual Width : 19.840 @@ -29225,7 +29233,23 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_we_reg + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_address_reg0 + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_we_reg Slack : 19.610 Actual Width : 19.840 @@ -29249,7 +29273,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_address_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_address_reg0 Slack : 19.610 Actual Width : 19.840 @@ -29257,7 +29281,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_we_reg +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_we_reg Slack : 19.610 Actual Width : 19.840 @@ -29265,7 +29289,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_address_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17 Slack : 19.610 Actual Width : 19.840 @@ -29273,23 +29297,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_we_reg - -Slack : 19.610 -Actual Width : 19.840 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_address_reg0 - -Slack : 19.610 -Actual Width : 19.840 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_we_reg +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18 Slack : 19.610 Actual Width : 19.840 @@ -29307,6 +29315,14 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_we_reg +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2 + Slack : 19.610 Actual Width : 19.840 Required Width : 0.230 @@ -29329,7 +29345,15 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_address_reg0 + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_we_reg Slack : 19.610 Actual Width : 19.840 @@ -29339,14 +29363,6 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22 -Slack : 19.610 -Actual Width : 19.840 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23 - Slack : 19.610 Actual Width : 19.840 Required Width : 0.230 @@ -29369,7 +29385,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_address_reg0 Slack : 19.610 Actual Width : 19.840 @@ -29377,7 +29393,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_address_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_we_reg Slack : 19.610 Actual Width : 19.840 @@ -29385,7 +29401,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_we_reg +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_address_reg0 Slack : 19.610 Actual Width : 19.840 @@ -29393,7 +29409,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_address_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_we_reg Slack : 19.610 Actual Width : 19.840 @@ -29401,7 +29417,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_we_reg +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28 Slack : 19.610 Actual Width : 19.840 @@ -29425,31 +29441,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_address_reg0 - -Slack : 19.610 -Actual Width : 19.840 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_we_reg - -Slack : 19.610 -Actual Width : 19.840 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0 - -Slack : 19.610 -Actual Width : 19.840 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_we_reg +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30 Slack : 19.610 Actual Width : 19.840 @@ -29489,7 +29481,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_address_reg0 Slack : 19.610 Actual Width : 19.840 @@ -29497,7 +29489,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_address_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_we_reg Slack : 19.610 Actual Width : 19.840 @@ -29505,7 +29497,23 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_we_reg +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_address_reg0 + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_we_reg + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6 Slack : 19.610 Actual Width : 19.840 @@ -29523,6 +29531,22 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_we_reg +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_address_reg0 + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_we_reg + Slack : 19.610 Actual Width : 19.840 Required Width : 0.230 @@ -29539,6 +29563,102 @@ Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_we_reg +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0 + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0 + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13~porta_address_reg0 + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2~porta_address_reg0 + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5~porta_address_reg0 + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0 + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8~porta_address_reg0 + +Slack : 19.610 +Actual Width : 19.840 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9~porta_address_reg0 + Slack : 19.611 Actual Width : 19.841 Required Width : 0.230 @@ -29585,7 +29705,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13 Slack : 19.611 Actual Width : 19.841 @@ -29593,7 +29713,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14 Slack : 19.611 Actual Width : 19.841 @@ -29609,7 +29729,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_address_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16 Slack : 19.611 Actual Width : 19.841 @@ -29617,7 +29737,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_we_reg +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0 Slack : 19.611 Actual Width : 19.841 @@ -29625,7 +29745,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0 Slack : 19.611 Actual Width : 19.841 @@ -29633,7 +29753,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_address_reg0 Slack : 19.611 Actual Width : 19.841 @@ -29641,15 +29761,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19 - -Slack : 19.611 -Actual Width : 19.841 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_we_reg Slack : 19.611 Actual Width : 19.841 @@ -29665,7 +29777,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21 Slack : 19.611 Actual Width : 19.841 @@ -29681,7 +29793,15 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_address_reg0 + +Slack : 19.611 +Actual Width : 19.841 +Required Width : 0.230 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] +Clock Edge : Rise +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_we_reg Slack : 19.611 Actual Width : 19.841 @@ -29697,7 +29817,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_address_reg0 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25 Slack : 19.611 Actual Width : 19.841 @@ -29705,127 +29825,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_we_reg - -Slack : 19.611 -Actual Width : 19.841 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0 - -Slack : 19.611 -Actual Width : 19.841 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27 - -Slack : 19.611 -Actual Width : 19.841 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28 - -Slack : 19.611 -Actual Width : 19.841 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29 - -Slack : 19.611 -Actual Width : 19.841 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3 - -Slack : 19.611 -Actual Width : 19.841 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30 - -Slack : 19.611 -Actual Width : 19.841 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31 - -Slack : 19.611 -Actual Width : 19.841 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_address_reg0 - -Slack : 19.611 -Actual Width : 19.841 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_we_reg - -Slack : 19.611 -Actual Width : 19.841 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0 - -Slack : 19.611 -Actual Width : 19.841 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6 - -Slack : 19.611 -Actual Width : 19.841 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7 - -Slack : 19.611 -Actual Width : 19.841 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_address_reg0 - -Slack : 19.611 -Actual Width : 19.841 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_we_reg - -Slack : 19.611 -Actual Width : 19.841 -Required Width : 0.230 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Clock Edge : Rise -Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9 +Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26 +--------------------------------------------------------------------------------+ @@ -29935,7 +29935,7 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] +Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] Slack : 20.633 Actual Width : 20.849 @@ -29943,47 +29943,7 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] - -Slack : 20.633 -Actual Width : 20.849 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] - -Slack : 20.633 -Actual Width : 20.849 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] - -Slack : 20.633 -Actual Width : 20.849 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] - -Slack : 20.633 -Actual Width : 20.849 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] - -Slack : 20.633 -Actual Width : 20.849 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] +Target : ula:ula_|i2c_loader:i2c_loader_|state.Data Slack : 20.633 Actual Width : 20.849 @@ -29999,7 +29959,7 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] +Target : ula:ula_|i2c_loader:i2c_loader_|state.Pause Slack : 20.633 Actual Width : 20.849 @@ -30007,31 +29967,7 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] - -Slack : 20.633 -Actual Width : 20.849 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] - -Slack : 20.633 -Actual Width : 20.849 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] - -Slack : 20.633 -Actual Width : 20.849 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] +Target : ula:ula_|i2c_loader:i2c_loader_|state.Start Slack : 20.633 Actual Width : 20.849 @@ -30143,7 +30079,7 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] Slack : 20.633 Actual Width : 20.849 @@ -30151,7 +30087,119 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] + +Slack : 20.633 +Actual Width : 20.849 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] + +Slack : 20.633 +Actual Width : 20.849 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] + +Slack : 20.633 +Actual Width : 20.849 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] + +Slack : 20.633 +Actual Width : 20.849 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] + +Slack : 20.633 +Actual Width : 20.849 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] + +Slack : 20.633 +Actual Width : 20.849 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] + +Slack : 20.633 +Actual Width : 20.849 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] + +Slack : 20.633 +Actual Width : 20.849 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] + +Slack : 20.633 +Actual Width : 20.849 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] + +Slack : 20.633 +Actual Width : 20.849 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] + +Slack : 20.633 +Actual Width : 20.849 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] + +Slack : 20.633 +Actual Width : 20.849 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] + +Slack : 20.633 +Actual Width : 20.849 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] + +Slack : 20.633 +Actual Width : 20.849 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] Slack : 20.634 Actual Width : 20.850 @@ -30175,7 +30223,7 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5] +Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0] Slack : 20.634 Actual Width : 20.850 @@ -30183,36 +30231,116 @@ Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1] + +Slack : 20.634 +Actual Width : 20.850 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2] + +Slack : 20.634 +Actual Width : 20.850 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3] + +Slack : 20.634 +Actual Width : 20.850 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4] + +Slack : 20.634 +Actual Width : 20.850 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6] + +Slack : 20.634 +Actual Width : 20.850 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7] + +Slack : 20.637 +Actual Width : 20.821 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|nbit[0] + +Slack : 20.638 +Actual Width : 20.822 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] + +Slack : 20.638 +Actual Width : 20.822 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] + +Slack : 20.638 +Actual Width : 20.822 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] + +Slack : 20.638 +Actual Width : 20.822 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] + +Slack : 20.638 +Actual Width : 20.822 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] + +Slack : 20.638 +Actual Width : 20.822 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] + +Slack : 20.639 +Actual Width : 20.823 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise Target : ula:ula_|i2c_loader:i2c_loader_|state.Ack -Slack : 20.634 -Actual Width : 20.850 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|state.Data - -Slack : 20.634 -Actual Width : 20.850 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|state.Pause - -Slack : 20.634 -Actual Width : 20.850 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|state.Start - -Slack : 20.634 -Actual Width : 20.850 -Required Width : 0.216 -Type : High Pulse Width +Slack : 20.639 +Actual Width : 20.823 +Required Width : 0.184 +Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2c_loader:i2c_loader_|state.Stop @@ -30223,415 +30351,287 @@ Required Width : 0.184 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15] +Target : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 -Slack : 20.641 -Actual Width : 20.825 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2c_loader:i2c_loader_|nbit[0] - -Slack : 20.641 -Actual Width : 20.825 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] - -Slack : 20.641 -Actual Width : 20.825 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] - -Slack : 20.641 -Actual Width : 20.825 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] - -Slack : 20.641 -Actual Width : 20.825 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] - -Slack : 20.641 -Actual Width : 20.825 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] - -Slack : 20.641 -Actual Width : 20.825 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] - -Slack : 20.641 -Actual Width : 20.825 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] - -Slack : 20.641 -Actual Width : 20.825 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] - -Slack : 20.641 -Actual Width : 20.825 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] - -Slack : 20.641 -Actual Width : 20.825 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] - -Slack : 20.641 -Actual Width : 20.825 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] - -Slack : 20.641 -Actual Width : 20.825 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] - -Slack : 20.641 -Actual Width : 20.825 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] - -Slack : 20.641 -Actual Width : 20.825 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9] - -Slack : 20.643 -Actual Width : 20.827 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] - -Slack : 20.643 -Actual Width : 20.827 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] - -Slack : 20.643 -Actual Width : 20.827 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] - -Slack : 20.643 -Actual Width : 20.827 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] - -Slack : 20.643 -Actual Width : 20.827 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] - -Slack : 20.643 -Actual Width : 20.827 -Required Width : 0.184 -Type : Low Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] - -Slack : 20.643 -Actual Width : 20.827 +Slack : 20.639 +Actual Width : 20.823 Required Width : 0.184 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] -Slack : 20.643 -Actual Width : 20.827 +Slack : 20.639 +Actual Width : 20.823 Required Width : 0.184 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8] -Slack : 20.643 -Actual Width : 20.827 +Slack : 20.639 +Actual Width : 20.823 Required Width : 0.184 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] -Slack : 20.643 -Actual Width : 20.827 +Slack : 20.639 +Actual Width : 20.823 Required Width : 0.184 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 -Slack : 20.649 -Actual Width : 20.865 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] - -Slack : 20.651 -Actual Width : 20.835 +Slack : 20.645 +Actual Width : 20.829 Required Width : 0.184 Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0] +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] -Slack : 20.656 -Actual Width : 20.872 +Slack : 20.648 +Actual Width : 20.832 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] + +Slack : 20.648 +Actual Width : 20.832 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] + +Slack : 20.648 +Actual Width : 20.832 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] + +Slack : 20.648 +Actual Width : 20.832 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] + +Slack : 20.648 +Actual Width : 20.832 +Required Width : 0.184 +Type : Low Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] + +Slack : 20.653 +Actual Width : 20.869 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] +Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0] -Slack : 20.656 -Actual Width : 20.872 +Slack : 20.653 +Actual Width : 20.869 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] +Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1] -Slack : 20.656 -Actual Width : 20.872 +Slack : 20.653 +Actual Width : 20.869 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] +Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2] -Slack : 20.656 -Actual Width : 20.872 +Slack : 20.653 +Actual Width : 20.869 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] +Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3] -Slack : 20.656 -Actual Width : 20.872 +Slack : 20.653 +Actual Width : 20.869 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] +Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4] -Slack : 20.656 -Actual Width : 20.872 +Slack : 20.655 +Actual Width : 20.871 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8] +Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16] -Slack : 20.656 -Actual Width : 20.872 +Slack : 20.661 +Actual Width : 20.877 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] +Target : ula:ula_|i2c_loader:i2c_loader_|state.Ack -Slack : 20.656 -Actual Width : 20.872 +Slack : 20.661 +Actual Width : 20.877 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 +Target : ula:ula_|i2c_loader:i2c_loader_|state.Stop -Slack : 20.657 -Actual Width : 20.873 +Slack : 20.661 +Actual Width : 20.877 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] +Target : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2 -Slack : 20.657 -Actual Width : 20.873 +Slack : 20.661 +Actual Width : 20.877 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7] -Slack : 20.658 -Actual Width : 20.874 +Slack : 20.661 +Actual Width : 20.877 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8] + +Slack : 20.661 +Actual Width : 20.877 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9] + +Slack : 20.661 +Actual Width : 20.877 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1 + +Slack : 20.662 +Actual Width : 20.878 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1] + +Slack : 20.662 +Actual Width : 20.878 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2] + +Slack : 20.662 +Actual Width : 20.878 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3] + +Slack : 20.662 +Actual Width : 20.878 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4] + +Slack : 20.662 +Actual Width : 20.878 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5] + +Slack : 20.662 +Actual Width : 20.878 +Required Width : 0.216 +Type : High Pulse Width +Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Clock Edge : Rise +Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6] + +Slack : 20.663 +Actual Width : 20.879 Required Width : 0.216 Type : High Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise Target : ula:ula_|i2c_loader:i2c_loader_|nbit[0] -Slack : 20.659 -Actual Width : 20.875 -Required Width : 0.216 -Type : High Pulse Width +Slack : 20.667 +Actual Width : 20.851 +Required Width : 0.184 +Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10] +Target : ula:ula_|i2c_loader:i2c_loader_|nbit[1] -Slack : 20.659 -Actual Width : 20.875 -Required Width : 0.216 -Type : High Pulse Width +Slack : 20.667 +Actual Width : 20.851 +Required Width : 0.184 +Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11] +Target : ula:ula_|i2c_loader:i2c_loader_|nbit[2] -Slack : 20.659 -Actual Width : 20.875 -Required Width : 0.216 -Type : High Pulse Width +Slack : 20.667 +Actual Width : 20.851 +Required Width : 0.184 +Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12] +Target : ula:ula_|i2c_loader:i2c_loader_|nbyte[0] -Slack : 20.659 -Actual Width : 20.875 -Required Width : 0.216 -Type : High Pulse Width +Slack : 20.667 +Actual Width : 20.851 +Required Width : 0.184 +Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13] +Target : ula:ula_|i2c_loader:i2c_loader_|nbyte[1] -Slack : 20.659 -Actual Width : 20.875 -Required Width : 0.216 -Type : High Pulse Width +Slack : 20.667 +Actual Width : 20.851 +Required Width : 0.184 +Type : Low Pulse Width Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14] - -Slack : 20.659 -Actual Width : 20.875 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1] - -Slack : 20.659 -Actual Width : 20.875 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2] - -Slack : 20.659 -Actual Width : 20.875 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3] - -Slack : 20.659 -Actual Width : 20.875 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4] - -Slack : 20.659 -Actual Width : 20.875 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5] - -Slack : 20.659 -Actual Width : 20.875 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6] - -Slack : 20.659 -Actual Width : 20.875 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7] - -Slack : 20.659 -Actual Width : 20.875 -Required Width : 0.216 -Type : High Pulse Width -Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Clock Edge : Rise -Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8] +Target : ula:ula_|i2c_loader:i2c_loader_|phase[0] +--------------------------------------------------------------------------------+ @@ -30759,43 +30759,43 @@ Target : ula:ula_|clocks:clocks_|counter[0] +--------------------------------------------------------------------------------+ Data Port : raw_loader_in Clock Port : CLOCK_50 -Rise : 1.079 -Fall : 1.946 +Rise : 0.855 +Fall : 1.653 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : raw_loader_in Clock Port : CLOCK_50 -Rise : 2.221 -Fall : 3.039 +Rise : 2.034 +Fall : 2.803 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : SW[*] Clock Port : CLOCK_50 -Rise : 0.623 +Rise : 0.624 Fall : 1.147 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Data Port : SW[2] Clock Port : CLOCK_50 -Rise : 0.623 +Rise : 0.624 Fall : 1.147 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Data Port : AUD_ADCDAT Clock Port : CLOCK_50 -Rise : 0.728 -Fall : 1.321 +Rise : 0.918 +Fall : 1.514 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Data Port : I2C_SDAT Clock Port : CLOCK_50 -Rise : 1.575 -Fall : 2.139 +Rise : 1.571 +Fall : 2.179 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ @@ -30807,43 +30807,43 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ Data Port : raw_loader_in Clock Port : CLOCK_50 -Rise : -0.841 -Fall : -1.690 +Rise : -0.631 +Fall : -1.422 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : raw_loader_in Clock Port : CLOCK_50 -Rise : -1.690 -Fall : -2.493 +Rise : -1.454 +Fall : -2.187 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : SW[*] Clock Port : CLOCK_50 Rise : -0.259 -Fall : -0.787 +Fall : -0.788 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Data Port : SW[2] Clock Port : CLOCK_50 Rise : -0.259 -Fall : -0.787 +Fall : -0.788 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Data Port : AUD_ADCDAT Clock Port : CLOCK_50 -Rise : -0.368 -Fall : -0.952 +Rise : -0.566 +Fall : -1.152 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Data Port : I2C_SDAT Clock Port : CLOCK_50 -Rise : -0.742 -Fall : -1.295 +Rise : -0.730 +Fall : -1.282 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ @@ -30855,197 +30855,197 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ Data Port : GPIO_1[*] Clock Port : CLOCK_50 -Rise : 6.008 -Fall : 6.095 +Rise : 5.707 +Fall : 5.789 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[16] Clock Port : CLOCK_50 -Rise : 6.008 -Fall : 6.095 +Rise : 5.633 +Fall : 5.747 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[17] Clock Port : CLOCK_50 -Rise : 5.342 -Fall : 5.537 +Rise : 5.550 +Fall : 5.607 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[18] Clock Port : CLOCK_50 -Rise : 5.828 -Fall : 5.903 +Rise : 5.707 +Fall : 5.789 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[19] Clock Port : CLOCK_50 -Rise : 5.590 -Fall : 5.692 +Rise : 5.683 +Fall : 5.753 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[20] Clock Port : CLOCK_50 -Rise : 5.726 -Fall : 5.854 +Rise : 5.541 +Fall : 5.625 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[21] Clock Port : CLOCK_50 -Rise : 5.482 -Fall : 5.521 +Rise : 5.535 +Fall : 5.610 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[22] Clock Port : CLOCK_50 -Rise : 5.820 -Fall : 5.903 +Rise : 5.680 +Fall : 5.780 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[23] Clock Port : CLOCK_50 -Rise : 5.363 -Fall : 5.393 +Rise : 5.303 +Fall : 5.400 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[*] Clock Port : CLOCK_50 -Rise : 4.649 -Fall : 4.764 +Rise : 4.600 +Fall : 4.687 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[16] Clock Port : CLOCK_50 -Rise : 4.449 -Fall : 4.536 +Rise : 4.578 +Fall : 4.687 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[17] Clock Port : CLOCK_50 -Rise : 4.487 -Fall : 4.591 +Rise : 4.320 +Fall : 4.402 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[18] Clock Port : CLOCK_50 -Rise : 4.253 -Fall : 4.359 +Rise : 4.317 +Fall : 4.434 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[19] Clock Port : CLOCK_50 -Rise : 4.439 -Fall : 4.548 +Rise : 4.448 +Fall : 4.667 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[20] Clock Port : CLOCK_50 -Rise : 4.649 -Fall : 4.764 +Rise : 4.246 +Fall : 4.330 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[21] Clock Port : CLOCK_50 -Rise : 4.334 -Fall : 4.411 +Rise : 4.600 +Fall : 4.675 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[22] Clock Port : CLOCK_50 -Rise : 4.547 -Fall : 4.697 +Rise : 4.539 +Fall : 4.640 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[23] Clock Port : CLOCK_50 -Rise : 4.198 -Fall : 4.263 +Rise : 4.508 +Fall : 4.602 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[*] Clock Port : CLOCK_50 -Rise : 5.045 -Fall : 4.866 +Rise : 5.245 +Fall : 4.941 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[0] Clock Port : CLOCK_50 -Rise : 5.045 -Fall : 4.866 +Rise : 5.245 +Fall : 4.941 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[1] Clock Port : CLOCK_50 -Rise : 3.467 -Fall : 3.470 +Rise : 3.747 +Fall : 3.799 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[2] Clock Port : CLOCK_50 -Rise : 3.638 -Fall : 3.715 +Rise : 3.833 +Fall : 3.780 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[3] Clock Port : CLOCK_50 -Rise : 3.865 -Fall : 3.962 +Rise : 3.893 +Fall : 3.863 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[*] Clock Port : CLOCK_50 -Rise : 3.736 -Fall : 3.757 +Rise : 3.942 +Fall : 3.968 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[0] Clock Port : CLOCK_50 -Rise : 3.736 -Fall : 3.757 +Rise : 3.813 +Fall : 3.787 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[1] Clock Port : CLOCK_50 -Rise : 3.606 -Fall : 3.673 +Rise : 3.892 +Fall : 3.968 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[2] Clock Port : CLOCK_50 -Rise : 3.656 -Fall : 3.658 +Rise : 3.942 +Fall : 3.931 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[3] Clock Port : CLOCK_50 -Rise : 3.656 -Fall : 3.658 +Rise : 3.928 +Fall : 3.917 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] @@ -31058,36 +31058,36 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[*] Clock Port : CLOCK_50 -Rise : 3.764 -Fall : 3.886 +Rise : 4.204 +Fall : 4.367 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[0] Clock Port : CLOCK_50 -Rise : 3.764 -Fall : 3.886 +Rise : 4.144 +Fall : 4.181 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[1] Clock Port : CLOCK_50 -Rise : 3.693 -Fall : 3.752 +Rise : 4.204 +Fall : 4.367 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[2] Clock Port : CLOCK_50 -Rise : 3.523 -Fall : 3.590 +Rise : 3.660 +Fall : 3.615 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[3] Clock Port : CLOCK_50 -Rise : 3.653 -Fall : 3.739 +Rise : 3.950 +Fall : 3.945 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] @@ -31155,197 +31155,197 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ Data Port : GPIO_1[*] Clock Port : CLOCK_50 -Rise : 4.404 -Fall : 4.492 +Rise : 4.814 +Fall : 4.889 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[16] Clock Port : CLOCK_50 -Rise : 4.714 -Fall : 4.811 +Rise : 4.986 +Fall : 5.076 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[17] Clock Port : CLOCK_50 -Rise : 4.756 -Fall : 4.806 +Rise : 4.899 +Fall : 4.961 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[18] Clock Port : CLOCK_50 -Rise : 4.404 -Fall : 4.492 +Rise : 4.915 +Fall : 5.000 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[19] Clock Port : CLOCK_50 -Rise : 4.619 -Fall : 4.708 +Rise : 4.914 +Fall : 4.986 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[20] Clock Port : CLOCK_50 -Rise : 4.805 -Fall : 4.924 +Rise : 4.819 +Fall : 4.894 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[21] Clock Port : CLOCK_50 -Rise : 4.528 -Fall : 4.559 +Rise : 4.961 +Fall : 5.038 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[22] Clock Port : CLOCK_50 -Rise : 4.418 -Fall : 4.501 +Rise : 5.139 +Fall : 5.242 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[23] Clock Port : CLOCK_50 -Rise : 4.478 -Fall : 4.502 +Rise : 4.814 +Fall : 4.889 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[*] Clock Port : CLOCK_50 -Rise : 3.074 -Fall : 3.195 +Rise : 3.215 +Fall : 3.294 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[16] Clock Port : CLOCK_50 -Rise : 3.656 -Fall : 3.753 +Rise : 3.794 +Fall : 3.884 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[17] Clock Port : CLOCK_50 -Rise : 3.705 -Fall : 3.857 +Rise : 3.590 +Fall : 3.708 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[18] Clock Port : CLOCK_50 -Rise : 3.537 -Fall : 3.607 +Rise : 3.672 +Fall : 3.764 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[19] Clock Port : CLOCK_50 -Rise : 3.562 -Fall : 3.684 +Rise : 3.215 +Fall : 3.294 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[20] Clock Port : CLOCK_50 -Rise : 3.074 -Fall : 3.195 +Rise : 3.409 +Fall : 3.498 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[21] Clock Port : CLOCK_50 -Rise : 3.587 -Fall : 3.750 +Rise : 3.716 +Fall : 3.793 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[22] Clock Port : CLOCK_50 -Rise : 3.787 -Fall : 3.888 +Rise : 3.823 +Fall : 3.933 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[23] Clock Port : CLOCK_50 -Rise : 3.402 -Fall : 3.449 +Rise : 3.656 +Fall : 3.803 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[*] Clock Port : CLOCK_50 -Rise : 2.246 -Fall : 2.250 +Rise : 2.186 +Fall : 2.187 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[0] Clock Port : CLOCK_50 -Rise : 3.784 -Fall : 3.550 +Rise : 3.738 +Fall : 3.497 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[1] Clock Port : CLOCK_50 -Rise : 2.246 -Fall : 2.250 +Rise : 2.186 +Fall : 2.187 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[2] Clock Port : CLOCK_50 -Rise : 2.373 -Fall : 2.393 +Rise : 2.321 +Fall : 2.331 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[3] Clock Port : CLOCK_50 -Rise : 2.590 -Fall : 2.631 +Rise : 2.379 +Fall : 2.411 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[*] Clock Port : CLOCK_50 -Rise : 2.286 -Fall : 2.308 +Rise : 2.209 +Fall : 2.213 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[0] Clock Port : CLOCK_50 -Rise : 2.504 -Fall : 2.535 +Rise : 2.214 +Fall : 2.222 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[1] Clock Port : CLOCK_50 -Rise : 2.286 -Fall : 2.308 +Rise : 2.209 +Fall : 2.213 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[2] Clock Port : CLOCK_50 -Rise : 2.428 -Fall : 2.440 +Rise : 2.338 +Fall : 2.360 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[3] Clock Port : CLOCK_50 -Rise : 2.428 -Fall : 2.440 +Rise : 2.325 +Fall : 2.347 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] @@ -31358,36 +31358,36 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[*] Clock Port : CLOCK_50 -Rise : 2.190 -Fall : 2.191 +Rise : 2.066 +Fall : 2.055 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[0] Clock Port : CLOCK_50 -Rise : 2.422 -Fall : 2.474 +Rise : 2.531 +Fall : 2.598 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[1] Clock Port : CLOCK_50 -Rise : 2.385 -Fall : 2.429 +Rise : 2.429 +Fall : 2.479 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[2] Clock Port : CLOCK_50 -Rise : 2.190 -Fall : 2.191 +Rise : 2.066 +Fall : 2.055 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[3] Clock Port : CLOCK_50 -Rise : 2.315 -Fall : 2.333 +Rise : 2.345 +Fall : 2.372 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] @@ -31455,10 +31455,10 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ Input Port : SW[1] Output Port : LED[0] -RR : 2.818 +RR : 2.827 RF : FR : -FF : 3.181 +FF : 3.187 Input Port : SW[2] Output Port : LED[2] @@ -31469,17 +31469,17 @@ FF : 2.866 Input Port : raw_loader_in Output Port : GPIO_1[22] -RR : 3.838 +RR : 3.882 RF : FR : -FF : 4.613 +FF : 4.619 Input Port : raw_loader_in Output Port : LED[3] -RR : 2.537 +RR : 2.598 RF : FR : -FF : 3.123 +FF : 3.199 +--------------------------------------------------------------------------------+ @@ -31489,10 +31489,10 @@ FF : 3.123 +--------------------------------------------------------------------------------+ Input Port : SW[1] Output Port : LED[0] -RR : 2.732 +RR : 2.741 RF : FR : -FF : 3.100 +FF : 3.106 Input Port : SW[2] Output Port : LED[2] @@ -31503,17 +31503,17 @@ FF : 2.798 Input Port : raw_loader_in Output Port : GPIO_1[22] -RR : 3.707 +RR : 3.748 RF : FR : -FF : 4.473 +FF : 4.479 Input Port : raw_loader_in Output Port : LED[3] -RR : 2.459 +RR : 2.517 RF : FR : -FF : 3.040 +FF : 3.114 +--------------------------------------------------------------------------------+ @@ -31528,72 +31528,72 @@ No synchronizer chains to report. ; Multicorner Timing Analysis Summary ; +--------------------------------------------------------------------------------+ Clock : Worst-case Slack -Setup : -18.123 -Hold : -0.053 -Recovery : -6.223 -Removal : 2.518 +Setup : -18.425 +Hold : 0.112 +Recovery : -6.263 +Removal : 2.503 Minimum Pulse Width : 9.208 Clock : CLOCK_50 -Setup : -18.123 -Hold : -0.053 +Setup : -18.425 +Hold : 0.112 Recovery : N/A Removal : N/A Minimum Pulse Width : 9.208 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Setup : -7.533 +Setup : -6.923 Hold : 0.186 Recovery : N/A Removal : N/A -Minimum Pulse Width : 19.600 +Minimum Pulse Width : 19.601 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] -Setup : -2.914 +Setup : -2.915 Hold : 0.177 Recovery : N/A Removal : N/A Minimum Pulse Width : 35.491 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Setup : -4.740 +Setup : -4.745 Hold : 0.178 -Recovery : -6.223 -Removal : 2.518 -Minimum Pulse Width : 20.591 +Recovery : -6.263 +Removal : 2.503 +Minimum Pulse Width : 20.590 Clock : Design-wide TNS -Setup : -879.875 -Hold : -0.089 -Recovery : -459.348 +Setup : -863.503 +Hold : 0.0 +Recovery : -464.84 Removal : 0.0 Minimum Pulse Width : 0.0 Clock : CLOCK_50 -Setup : -549.338 -Hold : -0.089 +Setup : -546.891 +Hold : 0.000 Recovery : N/A Removal : N/A Minimum Pulse Width : 0.000 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Setup : -284.813 +Setup : -271.506 Hold : 0.000 Recovery : N/A Removal : N/A Minimum Pulse Width : 0.000 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] -Setup : -2.914 +Setup : -2.915 Hold : 0.000 Recovery : N/A Removal : N/A Minimum Pulse Width : 0.000 Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Setup : -42.810 +Setup : -42.191 Hold : 0.000 -Recovery : -459.348 +Recovery : -464.840 Removal : 0.000 Minimum Pulse Width : 0.000 +--------------------------------------------------------------------------------+ @@ -31605,43 +31605,43 @@ Minimum Pulse Width : 0.000 +--------------------------------------------------------------------------------+ Data Port : raw_loader_in Clock Port : CLOCK_50 -Rise : 1.981 -Fall : 2.458 +Rise : 1.693 +Fall : 2.046 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : raw_loader_in Clock Port : CLOCK_50 -Rise : 3.874 -Fall : 4.319 +Rise : 3.641 +Fall : 3.954 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : SW[*] Clock Port : CLOCK_50 -Rise : 1.011 -Fall : 1.277 +Rise : 1.010 +Fall : 1.278 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Data Port : SW[2] Clock Port : CLOCK_50 -Rise : 1.011 -Fall : 1.277 +Rise : 1.010 +Fall : 1.278 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Data Port : AUD_ADCDAT Clock Port : CLOCK_50 -Rise : 1.262 -Fall : 1.505 +Rise : 1.624 +Fall : 1.864 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Data Port : I2C_SDAT Clock Port : CLOCK_50 -Rise : 2.823 -Fall : 3.104 +Rise : 2.876 +Fall : 3.109 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ @@ -31653,43 +31653,43 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ Data Port : raw_loader_in Clock Port : CLOCK_50 -Rise : -0.841 -Fall : -1.690 +Rise : -0.631 +Fall : -1.422 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : raw_loader_in Clock Port : CLOCK_50 -Rise : -1.690 -Fall : -2.493 +Rise : -1.454 +Fall : -2.187 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : SW[*] Clock Port : CLOCK_50 Rise : -0.259 -Fall : -0.592 +Fall : -0.593 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Data Port : SW[2] Clock Port : CLOCK_50 Rise : -0.259 -Fall : -0.592 +Fall : -0.593 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Data Port : AUD_ADCDAT Clock Port : CLOCK_50 -Rise : -0.368 -Fall : -0.776 +Rise : -0.566 +Fall : -1.108 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Data Port : I2C_SDAT Clock Port : CLOCK_50 -Rise : -0.742 -Fall : -1.295 +Rise : -0.730 +Fall : -1.282 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ @@ -31701,197 +31701,197 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ Data Port : GPIO_1[*] Clock Port : CLOCK_50 -Rise : 10.359 -Fall : 10.359 +Rise : 9.798 +Fall : 9.748 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[16] Clock Port : CLOCK_50 -Rise : 10.359 -Fall : 10.359 +Rise : 9.705 +Fall : 9.748 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[17] Clock Port : CLOCK_50 -Rise : 9.229 -Fall : 9.317 +Rise : 9.555 +Fall : 9.493 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[18] Clock Port : CLOCK_50 -Rise : 10.015 -Fall : 9.971 +Rise : 9.798 +Fall : 9.738 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[19] Clock Port : CLOCK_50 -Rise : 9.628 -Fall : 9.644 +Rise : 9.757 +Fall : 9.715 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[20] Clock Port : CLOCK_50 -Rise : 9.826 -Fall : 9.843 +Rise : 9.549 +Fall : 9.489 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[21] Clock Port : CLOCK_50 -Rise : 9.397 -Fall : 9.318 +Rise : 9.522 +Fall : 9.546 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[22] Clock Port : CLOCK_50 -Rise : 9.972 -Fall : 9.975 +Rise : 9.748 +Fall : 9.728 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[23] Clock Port : CLOCK_50 -Rise : 9.201 -Fall : 9.152 +Rise : 9.098 +Fall : 9.177 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[*] Clock Port : CLOCK_50 -Rise : 7.986 -Fall : 7.983 +Rise : 7.976 +Fall : 8.000 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[16] Clock Port : CLOCK_50 -Rise : 7.696 -Fall : 7.696 +Rise : 7.875 +Fall : 7.912 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[17] Clock Port : CLOCK_50 -Rise : 7.783 -Fall : 7.821 +Rise : 7.501 +Fall : 7.536 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[18] Clock Port : CLOCK_50 -Rise : 7.371 -Fall : 7.388 +Rise : 7.551 +Fall : 7.531 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[19] Clock Port : CLOCK_50 -Rise : 7.739 -Fall : 7.774 +Rise : 7.805 +Fall : 7.843 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[20] Clock Port : CLOCK_50 -Rise : 7.986 -Fall : 7.975 +Rise : 7.428 +Fall : 7.368 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[21] Clock Port : CLOCK_50 -Rise : 7.534 -Fall : 7.528 +Rise : 7.976 +Fall : 8.000 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[22] Clock Port : CLOCK_50 -Rise : 7.914 -Fall : 7.983 +Rise : 7.923 +Fall : 7.903 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[23] Clock Port : CLOCK_50 -Rise : 7.285 -Fall : 7.303 +Rise : 7.748 +Fall : 7.835 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[*] Clock Port : CLOCK_50 -Rise : 8.197 -Fall : 7.907 +Rise : 8.499 +Fall : 8.077 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[0] Clock Port : CLOCK_50 -Rise : 8.197 -Fall : 7.907 +Rise : 8.499 +Fall : 8.077 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[1] Clock Port : CLOCK_50 -Rise : 6.071 -Fall : 5.974 +Rise : 6.645 +Fall : 6.554 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[2] Clock Port : CLOCK_50 -Rise : 6.410 -Fall : 6.400 +Rise : 6.682 +Fall : 6.538 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[3] Clock Port : CLOCK_50 -Rise : 6.836 -Fall : 6.810 +Rise : 6.778 +Fall : 6.679 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[*] Clock Port : CLOCK_50 -Rise : 6.558 -Fall : 6.425 +Rise : 6.936 +Fall : 6.847 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[0] Clock Port : CLOCK_50 -Rise : 6.558 -Fall : 6.425 +Rise : 6.658 +Fall : 6.538 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[1] Clock Port : CLOCK_50 -Rise : 6.366 -Fall : 6.305 +Rise : 6.936 +Fall : 6.847 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[2] Clock Port : CLOCK_50 -Rise : 6.429 -Fall : 6.279 +Rise : 6.905 +Fall : 6.787 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[3] Clock Port : CLOCK_50 -Rise : 6.429 -Fall : 6.279 +Rise : 6.881 +Fall : 6.765 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] @@ -31904,36 +31904,36 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[*] Clock Port : CLOCK_50 -Rise : 6.621 -Fall : 6.664 +Rise : 7.442 +Fall : 7.459 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[0] Clock Port : CLOCK_50 -Rise : 6.621 -Fall : 6.664 +Rise : 7.239 +Fall : 7.169 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[1] Clock Port : CLOCK_50 -Rise : 6.426 -Fall : 6.412 +Rise : 7.442 +Fall : 7.459 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[2] Clock Port : CLOCK_50 -Rise : 6.231 -Fall : 6.211 +Rise : 6.381 +Fall : 6.270 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[3] Clock Port : CLOCK_50 -Rise : 6.443 -Fall : 6.428 +Rise : 6.900 +Fall : 6.786 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] @@ -32001,197 +32001,197 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ Data Port : GPIO_1[*] Clock Port : CLOCK_50 -Rise : 4.404 -Fall : 4.492 +Rise : 4.814 +Fall : 4.889 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[16] Clock Port : CLOCK_50 -Rise : 4.714 -Fall : 4.811 +Rise : 4.986 +Fall : 5.076 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[17] Clock Port : CLOCK_50 -Rise : 4.756 -Fall : 4.806 +Rise : 4.899 +Fall : 4.961 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[18] Clock Port : CLOCK_50 -Rise : 4.404 -Fall : 4.492 +Rise : 4.915 +Fall : 5.000 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[19] Clock Port : CLOCK_50 -Rise : 4.619 -Fall : 4.708 +Rise : 4.914 +Fall : 4.986 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[20] Clock Port : CLOCK_50 -Rise : 4.805 -Fall : 4.924 +Rise : 4.819 +Fall : 4.894 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[21] Clock Port : CLOCK_50 -Rise : 4.528 -Fall : 4.559 +Rise : 4.961 +Fall : 5.038 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[22] Clock Port : CLOCK_50 -Rise : 4.418 -Fall : 4.501 +Rise : 5.139 +Fall : 5.242 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[23] Clock Port : CLOCK_50 -Rise : 4.478 -Fall : 4.502 +Rise : 4.814 +Fall : 4.889 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : GPIO_1[*] Clock Port : CLOCK_50 -Rise : 3.074 -Fall : 3.195 +Rise : 3.215 +Fall : 3.294 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[16] Clock Port : CLOCK_50 -Rise : 3.656 -Fall : 3.753 +Rise : 3.794 +Fall : 3.884 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[17] Clock Port : CLOCK_50 -Rise : 3.705 -Fall : 3.857 +Rise : 3.590 +Fall : 3.708 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[18] Clock Port : CLOCK_50 -Rise : 3.537 -Fall : 3.607 +Rise : 3.672 +Fall : 3.764 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[19] Clock Port : CLOCK_50 -Rise : 3.562 -Fall : 3.684 +Rise : 3.215 +Fall : 3.294 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[20] Clock Port : CLOCK_50 -Rise : 3.074 -Fall : 3.195 +Rise : 3.409 +Fall : 3.498 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[21] Clock Port : CLOCK_50 -Rise : 3.587 -Fall : 3.750 +Rise : 3.716 +Fall : 3.793 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[22] Clock Port : CLOCK_50 -Rise : 3.787 -Fall : 3.888 +Rise : 3.823 +Fall : 3.933 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : GPIO_1[23] Clock Port : CLOCK_50 -Rise : 3.402 -Fall : 3.449 +Rise : 3.656 +Fall : 3.803 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[*] Clock Port : CLOCK_50 -Rise : 2.246 -Fall : 2.250 +Rise : 2.186 +Fall : 2.187 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[0] Clock Port : CLOCK_50 -Rise : 3.784 -Fall : 3.550 +Rise : 3.738 +Fall : 3.497 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[1] Clock Port : CLOCK_50 -Rise : 2.246 -Fall : 2.250 +Rise : 2.186 +Fall : 2.187 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[2] Clock Port : CLOCK_50 -Rise : 2.373 -Fall : 2.393 +Rise : 2.321 +Fall : 2.331 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_B[3] Clock Port : CLOCK_50 -Rise : 2.590 -Fall : 2.631 +Rise : 2.379 +Fall : 2.411 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[*] Clock Port : CLOCK_50 -Rise : 2.286 -Fall : 2.308 +Rise : 2.209 +Fall : 2.213 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[0] Clock Port : CLOCK_50 -Rise : 2.504 -Fall : 2.535 +Rise : 2.214 +Fall : 2.222 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[1] Clock Port : CLOCK_50 -Rise : 2.286 -Fall : 2.308 +Rise : 2.209 +Fall : 2.213 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[2] Clock Port : CLOCK_50 -Rise : 2.428 -Fall : 2.440 +Rise : 2.338 +Fall : 2.360 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_G[3] Clock Port : CLOCK_50 -Rise : 2.428 -Fall : 2.440 +Rise : 2.325 +Fall : 2.347 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] @@ -32204,36 +32204,36 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[*] Clock Port : CLOCK_50 -Rise : 2.190 -Fall : 2.191 +Rise : 2.066 +Fall : 2.055 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[0] Clock Port : CLOCK_50 -Rise : 2.422 -Fall : 2.474 +Rise : 2.531 +Fall : 2.598 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[1] Clock Port : CLOCK_50 -Rise : 2.385 -Fall : 2.429 +Rise : 2.429 +Fall : 2.479 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[2] Clock Port : CLOCK_50 -Rise : 2.190 -Fall : 2.191 +Rise : 2.066 +Fall : 2.055 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] Data Port : VGA_R[3] Clock Port : CLOCK_50 -Rise : 2.315 -Fall : 2.333 +Rise : 2.345 +Fall : 2.372 Clock Edge : Rise Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] @@ -32301,10 +32301,10 @@ Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +--------------------------------------------------------------------------------+ Input Port : SW[1] Output Port : LED[0] -RR : 4.629 +RR : 4.640 RF : FR : -FF : 4.693 +FF : 4.702 Input Port : SW[2] Output Port : LED[2] @@ -32315,17 +32315,17 @@ FF : 4.195 Input Port : raw_loader_in Output Port : GPIO_1[22] -RR : 6.626 +RR : 6.764 RF : FR : -FF : 7.003 +FF : 7.009 Input Port : raw_loader_in Output Port : LED[3] -RR : 4.318 +RR : 4.399 RF : FR : -FF : 4.517 +FF : 4.625 +--------------------------------------------------------------------------------+ @@ -32335,10 +32335,10 @@ FF : 4.517 +--------------------------------------------------------------------------------+ Input Port : SW[1] Output Port : LED[0] -RR : 2.732 +RR : 2.741 RF : FR : -FF : 3.100 +FF : 3.106 Input Port : SW[2] Output Port : LED[2] @@ -32349,17 +32349,17 @@ FF : 2.798 Input Port : raw_loader_in Output Port : GPIO_1[22] -RR : 3.707 +RR : 3.748 RF : FR : -FF : 4.473 +FF : 4.479 Input Port : raw_loader_in Output Port : LED[3] -RR : 2.459 +RR : 2.517 RF : FR : -FF : 3.040 +FF : 3.114 +--------------------------------------------------------------------------------+ @@ -38961,14 +38961,14 @@ FF Paths : 0 From Clock : CLOCK_50 To Clock : CLOCK_50 -RR Paths : 227 +RR Paths : 106 FR Paths : 0 RF Paths : 0 FF Paths : 0 From Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] To Clock : CLOCK_50 -RR Paths : 1125 +RR Paths : 1188 FR Paths : 0 RF Paths : 0 FF Paths : 0 @@ -38982,14 +38982,14 @@ FF Paths : 0 From Clock : CLOCK_50 To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -RR Paths : 260 +RR Paths : 120 FR Paths : 0 RF Paths : 0 FF Paths : 0 From Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -RR Paths : 1054 +RR Paths : 1154 FR Paths : 0 RF Paths : 0 FF Paths : 0 @@ -39017,7 +39017,7 @@ FF Paths : 0 From Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -RR Paths : 1428 +RR Paths : 1424 FR Paths : 180 RF Paths : 0 FF Paths : 21 @@ -39045,14 +39045,14 @@ FF Paths : 0 From Clock : CLOCK_50 To Clock : CLOCK_50 -RR Paths : 227 +RR Paths : 106 FR Paths : 0 RF Paths : 0 FF Paths : 0 From Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] To Clock : CLOCK_50 -RR Paths : 1125 +RR Paths : 1188 FR Paths : 0 RF Paths : 0 FF Paths : 0 @@ -39066,14 +39066,14 @@ FF Paths : 0 From Clock : CLOCK_50 To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -RR Paths : 260 +RR Paths : 120 FR Paths : 0 RF Paths : 0 FF Paths : 0 From Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -RR Paths : 1054 +RR Paths : 1154 FR Paths : 0 RF Paths : 0 FF Paths : 0 @@ -39101,7 +39101,7 @@ FF Paths : 0 From Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -RR Paths : 1428 +RR Paths : 1424 FR Paths : 180 RF Paths : 0 FF Paths : 21 @@ -39186,7 +39186,7 @@ Hold : 0 Info: ******************************************************************* Info: Running Quartus II 32-bit TimeQuest Timing Analyzer Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition - Info: Processing started: Fri Apr 1 18:55:44 2022 + Info: Processing started: Sat Apr 2 15:53:37 2022 Info: Command: quartus_sta spectrum -c spectrum Info: qsta_default_script.tcl version: #1 Warning (20028): Parallel compilation is not licensed and has been disabled @@ -39210,519 +39210,525 @@ Warning (332174): Ignored filter at spectrum.sdc(57): KEY1 could not be matched Warning (332174): Ignored filter at spectrum.sdc(54): ula_|pll_|altpll_component|pll|clk[0] could not be matched with a clock Warning (332174): Ignored filter at spectrum.sdc(54): ula_|pll_|altpll_component|pll|clk[1] could not be matched with a clock Warning (332174): Ignored filter at spectrum.sdc(54): ula_|pll_|altpll_component|pll|clk[2] could not be matched with a clock -Warning (332125): Found combinational loop of 511 nodes +Warning (332125): Found combinational loop of 517 nodes Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~3|combout" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~22|datac" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~22|combout" - Warning (332126): Node "z80_|alu_control_|db[0]~9|datab" + Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~0|datab" + Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~0|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~1|datac" + Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~1|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~3|datab" + Warning (332126): Node "z80_|alu_control_|db[0]~9|datac" Warning (332126): Node "z80_|alu_control_|db[0]~9|combout" Warning (332126): Node "z80_|alu_control_|db[0]~12|datac" Warning (332126): Node "z80_|alu_control_|db[0]~12|combout" Warning (332126): Node "z80_|bus_control_|db[0]~17|datab" Warning (332126): Node "z80_|bus_control_|db[0]~17|combout" - Warning (332126): Node "z80_|alu_control_|db[0]~8|datac" + Warning (332126): Node "z80_|alu_control_|db[0]~8|datad" Warning (332126): Node "z80_|alu_control_|db[0]~8|combout" - Warning (332126): Node "z80_|alu_control_|db[0]~9|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~12|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~12|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~17|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~17|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~22|datab" - Warning (332126): Node "z80_|alu_|db[0]~19|datac" - Warning (332126): Node "z80_|alu_|db[0]~19|combout" - Warning (332126): Node "z80_|alu_|db_low[1]~15|dataa" - Warning (332126): Node "z80_|alu_|db_low[1]~15|combout" - Warning (332126): Node "z80_|alu_|db_low[1]~16|dataa" - Warning (332126): Node "z80_|alu_|db_low[1]~16|combout" - Warning (332126): Node "z80_|alu_|db_low[1]~17|datac" - Warning (332126): Node "z80_|alu_|db_low[1]~17|combout" - Warning (332126): Node "z80_|alu_|db[1]~13|datac" - Warning (332126): Node "z80_|alu_|db[1]~13|combout" - Warning (332126): Node "z80_|alu_|db_low[1]~16|datac" - Warning (332126): Node "z80_|alu_|db_low[0]~21|datac" - Warning (332126): Node "z80_|alu_|db_low[0]~21|combout" - Warning (332126): Node "z80_|alu_|db_low[0]~22|datab" - Warning (332126): Node "z80_|alu_|db_low[0]~22|combout" - Warning (332126): Node "z80_|alu_|db_low[0]~23|dataa" - Warning (332126): Node "z80_|alu_|db_low[0]~23|combout" - Warning (332126): Node "z80_|alu_|db[0]~18|datab" - Warning (332126): Node "z80_|alu_|db[0]~18|combout" - Warning (332126): Node "z80_|alu_|db[0]~19|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~12|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~12|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~14|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~14|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~15|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~15|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~21|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~21|combout" - Warning (332126): Node "z80_|alu_|db[1]~12|datac" - Warning (332126): Node "z80_|alu_|db[1]~12|combout" - Warning (332126): Node "z80_|alu_|db[1]~13|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~0|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~0|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~1|datac" - Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~1|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~3|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~3|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~21|datac" - Warning (332126): Node "z80_|alu_|db_low[2]~2|datac" - Warning (332126): Node "z80_|alu_|db_low[2]~2|combout" - Warning (332126): Node "z80_|alu_|db_low[2]~3|datac" - Warning (332126): Node "z80_|alu_|db_low[2]~3|combout" - Warning (332126): Node "z80_|alu_|db_low[2]~24|datab" - Warning (332126): Node "z80_|alu_|db_low[2]~24|combout" - Warning (332126): Node "z80_|alu_|db[2]~15|dataa" - Warning (332126): Node "z80_|alu_|db[2]~15|combout" - Warning (332126): Node "z80_|alu_|db_low[1]~15|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~35|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~35|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~37|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~37|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~38|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~38|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~39|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~39|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~7|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~7|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~8|datab" - Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~8|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~9|datad" - Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~9|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~39|datab" - Warning (332126): Node "z80_|alu_|db[2]~14|datad" - Warning (332126): Node "z80_|alu_|db[2]~14|combout" - Warning (332126): Node "z80_|alu_|db[2]~15|datac" - Warning (332126): Node "z80_|alu_control_|db[2]~27|datab" + Warning (332126): Node "z80_|alu_control_|db[0]~9|datab" + Warning (332126): Node "z80_|alu_|db[0]~14|dataa" + Warning (332126): Node "z80_|alu_|db[0]~14|combout" + Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~1|datad" + Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~1|combout" + Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~2|dataa" + Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~2|combout" + Warning (332126): Node "z80_|alu_|db_low[0]~2|datab" + Warning (332126): Node "z80_|alu_|db_low[0]~2|combout" + Warning (332126): Node "z80_|alu_|db_low[0]~3|datac" + Warning (332126): Node "z80_|alu_|db_low[0]~3|combout" + Warning (332126): Node "z80_|alu_|db_low[0]~24|datab" + Warning (332126): Node "z80_|alu_|db_low[0]~24|combout" + Warning (332126): Node "z80_|alu_|db[0]~13|datac" + Warning (332126): Node "z80_|alu_|db[0]~13|combout" + Warning (332126): Node "z80_|alu_|db[0]~14|datad" + Warning (332126): Node "z80_|alu_|db_high[3]~4|datab" + Warning (332126): Node "z80_|alu_|db_high[3]~4|combout" + Warning (332126): Node "z80_|alu_|db_high[3]~5|datad" + Warning (332126): Node "z80_|alu_|db_high[3]~5|combout" + Warning (332126): Node "z80_|alu_|db_high[3]~6|datab" + Warning (332126): Node "z80_|alu_|db_high[3]~6|combout" + Warning (332126): Node "z80_|alu_|db_high[3]~7|datad" + Warning (332126): Node "z80_|alu_|db_high[3]~7|combout" + Warning (332126): Node "z80_|alu_|db[7]~12|datac" + Warning (332126): Node "z80_|alu_|db[7]~12|combout" + Warning (332126): Node "z80_|alu_|db_high[3]~5|dataa" + Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~1|dataa" + Warning (332126): Node "z80_|alu_|db_high[2]~8|datac" + Warning (332126): Node "z80_|alu_|db_high[2]~8|combout" + Warning (332126): Node "z80_|alu_|db_high[2]~9|datac" + Warning (332126): Node "z80_|alu_|db_high[2]~9|combout" + Warning (332126): Node "z80_|alu_|db_high[2]~12|dataa" + Warning (332126): Node "z80_|alu_|db_high[2]~12|combout" + Warning (332126): Node "z80_|alu_|db_high[2]~13|datab" + Warning (332126): Node "z80_|alu_|db_high[2]~13|combout" + Warning (332126): Node "z80_|alu_|db[6]~22|datac" + Warning (332126): Node "z80_|alu_|db[6]~22|combout" + Warning (332126): Node "z80_|alu_|db_high[3]~4|dataa" + Warning (332126): Node "z80_|alu_|db_high[2]~9|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~80|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~80|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~82|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~82|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~83|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~83|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~84|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~84|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~22|datab" + Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~22|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~23|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~23|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~24|datac" + Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~24|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~84|datac" + Warning (332126): Node "z80_|alu_|db[6]~21|datad" + Warning (332126): Node "z80_|alu_|db[6]~21|combout" + Warning (332126): Node "z80_|alu_|db[6]~22|datad" + Warning (332126): Node "z80_|alu_control_|db[6]~20|dataa" + Warning (332126): Node "z80_|alu_control_|db[6]~20|combout" + Warning (332126): Node "z80_|alu_control_|db[6]~21|datad" + Warning (332126): Node "z80_|alu_control_|db[6]~21|combout" + Warning (332126): Node "z80_|alu_control_|db[6]~22|datac" + Warning (332126): Node "z80_|alu_control_|db[6]~22|combout" + Warning (332126): Node "z80_|bus_control_|db[6]~8|datad" + Warning (332126): Node "z80_|bus_control_|db[6]~8|combout" + Warning (332126): Node "z80_|bus_control_|db[6]~9|datab" + Warning (332126): Node "z80_|bus_control_|db[6]~9|combout" + Warning (332126): Node "z80_|sw1_|db_down[6]~1|datab" + Warning (332126): Node "z80_|sw1_|db_down[6]~1|combout" + Warning (332126): Node "z80_|alu_control_|db[6]~22|datab" + Warning (332126): Node "z80_|alu_|db[6]~21|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~79|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~79|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~80|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~80|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~81|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~81|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~82|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~82|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_ds[6]~0|datad" + Warning (332126): Node "z80_|reg_file_|db_lo_ds[6]~0|combout" + Warning (332126): Node "z80_|alu_control_|db[6]~22|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~19|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~19|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~20|datad" + Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~20|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~21|datac" + Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~21|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~82|datad" + Warning (332126): Node "z80_|alu_|db_high[1]~16|dataa" + Warning (332126): Node "z80_|alu_|db_high[1]~16|combout" + Warning (332126): Node "z80_|alu_|db_high[1]~17|datab" + Warning (332126): Node "z80_|alu_|db_high[1]~17|combout" + Warning (332126): Node "z80_|alu_|db_high[1]~18|datad" + Warning (332126): Node "z80_|alu_|db_high[1]~18|combout" + Warning (332126): Node "z80_|alu_|db_high[1]~19|datad" + Warning (332126): Node "z80_|alu_|db_high[1]~19|combout" + Warning (332126): Node "z80_|alu_|db[5]~24|datab" + Warning (332126): Node "z80_|alu_|db[5]~24|combout" + Warning (332126): Node "z80_|alu_|db_high[2]~8|datab" + Warning (332126): Node "z80_|alu_|db_high[0]~22|datac" + Warning (332126): Node "z80_|alu_|db_high[0]~22|combout" + Warning (332126): Node "z80_|alu_|db_high[0]~23|datad" + Warning (332126): Node "z80_|alu_|db_high[0]~23|combout" + Warning (332126): Node "z80_|alu_|db_high[0]~24|datad" + Warning (332126): Node "z80_|alu_|db_high[0]~24|combout" + Warning (332126): Node "z80_|alu_|db_high[0]~25|dataa" + Warning (332126): Node "z80_|alu_|db_high[0]~25|combout" + Warning (332126): Node "z80_|alu_|db[4]~18|datad" + Warning (332126): Node "z80_|alu_|db[4]~18|combout" + Warning (332126): Node "z80_|alu_control_|db[4]~30|dataa" + Warning (332126): Node "z80_|alu_control_|db[4]~30|combout" + Warning (332126): Node "z80_|alu_control_|db[4]~31|datad" + Warning (332126): Node "z80_|alu_control_|db[4]~31|combout" + Warning (332126): Node "z80_|alu_control_|db[4]~32|datab" + Warning (332126): Node "z80_|alu_control_|db[4]~32|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~54|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~54|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~61|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~61|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~62|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~62|combout" + Warning (332126): Node "z80_|alu_control_|db[4]~30|datab" + Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~13|datab" + Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~13|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~14|datab" + Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~14|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~15|datab" + Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~15|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~62|datad" + Warning (332126): Node "z80_|alu_|db[4]~17|datab" + Warning (332126): Node "z80_|alu_|db[4]~17|combout" + Warning (332126): Node "z80_|alu_|db[4]~18|datac" + Warning (332126): Node "z80_|bus_control_|db[4]~19|datac" + Warning (332126): Node "z80_|bus_control_|db[4]~19|combout" + Warning (332126): Node "z80_|alu_control_|db[4]~32|dataa" + Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2|datab" + Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2|combout" + Warning (332126): Node "z80_|alu_|db_low[3]~16|dataa" + Warning (332126): Node "z80_|alu_|db_low[3]~16|combout" + Warning (332126): Node "z80_|alu_|db_low[3]~17|datab" + Warning (332126): Node "z80_|alu_|db_low[3]~17|combout" + Warning (332126): Node "z80_|alu_|db_low[3]~25|datad" + Warning (332126): Node "z80_|alu_|db_low[3]~25|combout" + Warning (332126): Node "z80_|alu_|db[3]~19|datab" + Warning (332126): Node "z80_|alu_|db[3]~19|combout" + Warning (332126): Node "z80_|alu_|db[3]~20|datad" + Warning (332126): Node "z80_|alu_|db[3]~20|combout" + Warning (332126): Node "z80_|alu_|db_high[0]~22|datab" + Warning (332126): Node "z80_|alu_control_|db[3]~35|datac" + Warning (332126): Node "z80_|alu_control_|db[3]~35|combout" + Warning (332126): Node "z80_|bus_control_|db[3]~21|datab" + Warning (332126): Node "z80_|bus_control_|db[3]~21|combout" + Warning (332126): Node "z80_|alu_|db_high[2]~11|datac" + Warning (332126): Node "z80_|alu_|db_high[2]~11|combout" + Warning (332126): Node "z80_|alu_|db_high[2]~12|datac" + Warning (332126): Node "z80_|alu_|db_high[0]~20|dataa" + Warning (332126): Node "z80_|alu_|db_high[0]~20|combout" + Warning (332126): Node "z80_|alu_|db_high[0]~24|dataa" + Warning (332126): Node "z80_|alu_|db_high[1]~14|dataa" + Warning (332126): Node "z80_|alu_|db_high[1]~14|combout" + Warning (332126): Node "z80_|alu_|db_high[1]~18|dataa" + Warning (332126): Node "z80_|alu_|db_low[0]~4|dataa" + Warning (332126): Node "z80_|alu_|db_low[0]~4|combout" + Warning (332126): Node "z80_|alu_|db_low[0]~6|datab" + Warning (332126): Node "z80_|alu_|db_low[0]~6|combout" + Warning (332126): Node "z80_|alu_|db_low[0]~24|dataa" + Warning (332126): Node "z80_|sw1_|db_down[3]~2|datad" + Warning (332126): Node "z80_|sw1_|db_down[3]~2|combout" + Warning (332126): Node "z80_|alu_control_|db[3]~34|datad" + Warning (332126): Node "z80_|alu_control_|db[3]~34|combout" + Warning (332126): Node "z80_|alu_control_|db[3]~35|dataa" + Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3|datac" + Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3|combout" + Warning (332126): Node "z80_|alu_|db_low[2]~19|dataa" + Warning (332126): Node "z80_|alu_|db_low[2]~19|combout" + Warning (332126): Node "z80_|alu_|db_low[2]~20|datad" + Warning (332126): Node "z80_|alu_|db_low[2]~20|combout" + Warning (332126): Node "z80_|alu_|db_low[2]~23|datad" + Warning (332126): Node "z80_|alu_|db_low[2]~23|combout" + Warning (332126): Node "z80_|alu_|db[2]~16|datad" + Warning (332126): Node "z80_|alu_|db[2]~16|combout" + Warning (332126): Node "z80_|alu_control_|db[2]~27|dataa" Warning (332126): Node "z80_|alu_control_|db[2]~27|combout" - Warning (332126): Node "z80_|alu_control_|db[2]~29|datad" + Warning (332126): Node "z80_|alu_control_|db[2]~29|datab" Warning (332126): Node "z80_|alu_control_|db[2]~29|combout" - Warning (332126): Node "z80_|bus_control_|db[2]~12|datab" + Warning (332126): Node "z80_|bus_control_|db[2]~12|datac" Warning (332126): Node "z80_|bus_control_|db[2]~12|combout" Warning (332126): Node "z80_|bus_control_|db[2]~13|datad" Warning (332126): Node "z80_|bus_control_|db[2]~13|combout" - Warning (332126): Node "z80_|alu_control_|db[2]~28|dataa" + Warning (332126): Node "z80_|alu_control_|db[2]~28|datab" Warning (332126): Node "z80_|alu_control_|db[2]~28|combout" - Warning (332126): Node "z80_|alu_control_|db[2]~29|datac" - Warning (332126): Node "z80_|alu_|db[2]~14|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~39|dataa" + Warning (332126): Node "z80_|alu_control_|db[2]~29|dataa" + Warning (332126): Node "z80_|alu_|db[2]~15|datad" + Warning (332126): Node "z80_|alu_|db[2]~15|combout" + Warning (332126): Node "z80_|alu_|db[2]~16|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~39|datac" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~39|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~40|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~40|datac" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~40|combout" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~41|datad" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~41|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~42|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~42|datab" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~42|combout" Warning (332126): Node "z80_|reg_file_|db_lo_ds[2]~2|datad" Warning (332126): Node "z80_|reg_file_|db_lo_ds[2]~2|combout" Warning (332126): Node "z80_|alu_control_|db[2]~28|datad" - Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~7|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~7|datab" Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~7|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~8|datad" + Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~8|datac" Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~8|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~9|datac" + Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~9|dataa" Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~9|combout" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~42|datad" - Warning (332126): Node "z80_|alu_|db_low[2]~3|dataa" - Warning (332126): Node "z80_|alu_|db_low[3]~7|datad" - Warning (332126): Node "z80_|alu_|db_low[3]~7|combout" - Warning (332126): Node "z80_|alu_|db_low[3]~8|datac" - Warning (332126): Node "z80_|alu_|db_low[3]~8|combout" - Warning (332126): Node "z80_|alu_|db_low[3]~11|datad" - Warning (332126): Node "z80_|alu_|db_low[3]~11|combout" - Warning (332126): Node "z80_|alu_|db_low[3]~25|datac" - Warning (332126): Node "z80_|alu_|db_low[3]~25|combout" - Warning (332126): Node "z80_|alu_|db[3]~10|datad" - Warning (332126): Node "z80_|alu_|db[3]~10|combout" - Warning (332126): Node "z80_|alu_|db[3]~11|dataa" - Warning (332126): Node "z80_|alu_|db[3]~11|combout" - Warning (332126): Node "z80_|alu_control_|db[3]~35|dataa" - Warning (332126): Node "z80_|alu_control_|db[3]~35|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~35|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~35|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~37|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~37|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~38|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~38|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~39|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~39|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~7|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~7|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~8|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~8|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~9|datac" + Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~9|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~39|datac" + Warning (332126): Node "z80_|alu_|db[2]~15|datab" + Warning (332126): Node "z80_|alu_|db_low[3]~13|datad" + Warning (332126): Node "z80_|alu_|db_low[3]~13|combout" + Warning (332126): Node "z80_|alu_|db_low[3]~14|dataa" + Warning (332126): Node "z80_|alu_|db_low[3]~14|combout" + Warning (332126): Node "z80_|alu_|db_low[3]~17|datad" + Warning (332126): Node "z80_|alu_|db_low[2]~22|datac" + Warning (332126): Node "z80_|alu_|db_low[2]~22|combout" + Warning (332126): Node "z80_|alu_|db_low[2]~23|dataa" + Warning (332126): Node "z80_|alu_|db_low[1]~10|dataa" + Warning (332126): Node "z80_|alu_|db_low[1]~10|combout" + Warning (332126): Node "z80_|alu_|db_low[1]~11|datad" + Warning (332126): Node "z80_|alu_|db_low[1]~11|combout" + Warning (332126): Node "z80_|alu_|db_low[1]~12|dataa" + Warning (332126): Node "z80_|alu_|db_low[1]~12|combout" + Warning (332126): Node "z80_|alu_|db[1]~10|datac" + Warning (332126): Node "z80_|alu_|db[1]~10|combout" + Warning (332126): Node "z80_|alu_control_|db[1]~24|datab" + Warning (332126): Node "z80_|alu_control_|db[1]~24|combout" + Warning (332126): Node "z80_|alu_control_|db[1]~26|datab" + Warning (332126): Node "z80_|alu_control_|db[1]~26|combout" + Warning (332126): Node "z80_|bus_control_|db[1]~10|datad" + Warning (332126): Node "z80_|bus_control_|db[1]~10|combout" + Warning (332126): Node "z80_|bus_control_|db[1]~11|datab" + Warning (332126): Node "z80_|bus_control_|db[1]~11|combout" + Warning (332126): Node "z80_|alu_control_|db[1]~25|datab" + Warning (332126): Node "z80_|alu_control_|db[1]~25|combout" + Warning (332126): Node "z80_|alu_control_|db[1]~26|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~29|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~29|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~30|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~30|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~31|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~31|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~32|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~32|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_ds[1]~1|datad" + Warning (332126): Node "z80_|reg_file_|db_lo_ds[1]~1|combout" + Warning (332126): Node "z80_|alu_control_|db[1]~25|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~4|datab" + Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~4|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~5|datab" + Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~5|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~6|datab" + Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~6|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~32|datab" + Warning (332126): Node "z80_|alu_|db[1]~8|datad" + Warning (332126): Node "z80_|alu_|db[1]~8|combout" + Warning (332126): Node "z80_|alu_|db[1]~10|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~12|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~12|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~14|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~14|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~15|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~15|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~21|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~21|combout" + Warning (332126): Node "z80_|alu_|db[1]~8|datac" + Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~0|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~0|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~1|datab" + Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~1|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~3|datab" + Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~3|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~21|datac" + Warning (332126): Node "z80_|alu_|db_low[1]~11|dataa" + Warning (332126): Node "z80_|alu_|db_low[2]~21|datad" + Warning (332126): Node "z80_|alu_|db_low[2]~21|combout" + Warning (332126): Node "z80_|alu_|db_low[2]~22|datab" + Warning (332126): Node "z80_|alu_|db_low[0]~2|dataa" + Warning (332126): Node "z80_|alu_|db_low[1]~7|dataa" + Warning (332126): Node "z80_|alu_|db_low[1]~7|combout" + Warning (332126): Node "z80_|alu_|db_low[1]~9|datab" + Warning (332126): Node "z80_|alu_|db_low[1]~9|combout" + Warning (332126): Node "z80_|alu_|db_low[1]~12|datad" + Warning (332126): Node "z80_|alu_|db_high[3]~2|dataa" + Warning (332126): Node "z80_|alu_|db_high[3]~2|combout" + Warning (332126): Node "z80_|alu_|db_high[3]~6|datad" + Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2|datac" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~46|datad" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~46|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~47|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~47|datad" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~47|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~50|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~50|dataa" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~50|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~51|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~51|datad" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~51|combout" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~52|datab" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~52|combout" - Warning (332126): Node "z80_|alu_control_|db[3]~34|dataa" - Warning (332126): Node "z80_|alu_control_|db[3]~34|combout" - Warning (332126): Node "z80_|alu_control_|db[3]~35|datad" - Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~10|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~10|datab" Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~10|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~11|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~11|datab" Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~11|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~12|datad" + Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~12|datab" Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~12|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~52|dataa" - Warning (332126): Node "z80_|alu_|db[3]~11|datac" - Warning (332126): Node "z80_|bus_control_|db[3]~21|datad" - Warning (332126): Node "z80_|bus_control_|db[3]~21|combout" - Warning (332126): Node "z80_|alu_|db_low[1]~12|datad" - Warning (332126): Node "z80_|alu_|db_low[1]~12|combout" - Warning (332126): Node "z80_|alu_|db_low[1]~14|dataa" - Warning (332126): Node "z80_|alu_|db_low[1]~14|combout" - Warning (332126): Node "z80_|alu_|db_low[1]~17|datad" - Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2|datad" - Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2|combout" - Warning (332126): Node "z80_|alu_|db_low[3]~10|datad" - Warning (332126): Node "z80_|alu_|db_low[3]~10|combout" - Warning (332126): Node "z80_|alu_|db_low[3]~11|dataa" - Warning (332126): Node "z80_|alu_|db_high[0]~21|datad" - Warning (332126): Node "z80_|alu_|db_high[0]~21|combout" - Warning (332126): Node "z80_|alu_|db_high[0]~25|datab" - Warning (332126): Node "z80_|alu_|db_high[0]~25|combout" - Warning (332126): Node "z80_|alu_|db_high[0]~26|datac" - Warning (332126): Node "z80_|alu_|db_high[0]~26|combout" - Warning (332126): Node "z80_|alu_|db[4]~17|datac" - Warning (332126): Node "z80_|alu_|db[4]~17|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~62|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~52|datac" + Warning (332126): Node "z80_|alu_control_|db[3]~34|dataa" + Warning (332126): Node "z80_|alu_|db[3]~20|dataa" + Warning (332126): Node "z80_|alu_|db_low[3]~14|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~44|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~44|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~46|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~46|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~47|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~47|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~48|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~48|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~10|dataa" + Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~10|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~11|datad" + Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~11|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~12|datac" + Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~12|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~48|dataa" + Warning (332126): Node "z80_|alu_|db[3]~19|datac" + Warning (332126): Node "z80_|alu_|db_low[2]~21|dataa" + Warning (332126): Node "z80_|alu_|db_high[2]~11|datab" + Warning (332126): Node "z80_|alu_|db_high[0]~20|datad" + Warning (332126): Node "z80_|alu_|db_high[1]~14|datad" + Warning (332126): Node "z80_|alu_|db_low[0]~4|datad" + Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3|datab" + Warning (332126): Node "z80_|alu_|db_low[1]~7|datad" + Warning (332126): Node "z80_|alu_|db_high[3]~2|datad" + Warning (332126): Node "z80_|alu_|db_high[0]~23|dataa" + Warning (332126): Node "z80_|alu_|db_low[3]~13|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~62|datab" Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~62|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~64|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~64|datab" Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~64|combout" Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~65|dataa" Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~65|combout" Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~66|datac" Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~66|combout" - Warning (332126): Node "z80_|alu_|db[4]~16|datad" - Warning (332126): Node "z80_|alu_|db[4]~16|combout" - Warning (332126): Node "z80_|alu_|db[4]~17|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~16|datad" + Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~16|datab" Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~16|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~17|datad" + Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~17|dataa" Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~17|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~18|datad" + Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~18|datab" Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~18|combout" Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~66|datab" - Warning (332126): Node "z80_|alu_|db_low[3]~7|dataa" - Warning (332126): Node "z80_|alu_|db_high[0]~24|datac" - Warning (332126): Node "z80_|alu_|db_high[0]~24|combout" - Warning (332126): Node "z80_|alu_|db_high[0]~25|dataa" - Warning (332126): Node "z80_|alu_|db_high[1]~17|datad" - Warning (332126): Node "z80_|alu_|db_high[1]~17|combout" - Warning (332126): Node "z80_|alu_|db_high[1]~18|datab" - Warning (332126): Node "z80_|alu_|db_high[1]~18|combout" - Warning (332126): Node "z80_|alu_|db_high[1]~19|datad" - Warning (332126): Node "z80_|alu_|db_high[1]~19|combout" - Warning (332126): Node "z80_|alu_|db_high[1]~20|dataa" - Warning (332126): Node "z80_|alu_|db_high[1]~20|combout" - Warning (332126): Node "z80_|alu_|db[5]~25|dataa" - Warning (332126): Node "z80_|alu_|db[5]~25|combout" - Warning (332126): Node "z80_|alu_control_|db[5]~15|datab" + Warning (332126): Node "z80_|alu_|db[4]~17|datad" + Warning (332126): Node "z80_|alu_|db_high[1]~16|datad" + Warning (332126): Node "z80_|alu_|db_high[1]~17|dataa" + Warning (332126): Node "z80_|alu_control_|db[5]~15|dataa" Warning (332126): Node "z80_|alu_control_|db[5]~15|combout" - Warning (332126): Node "z80_|bus_control_|db[5]~15|datac" + Warning (332126): Node "z80_|bus_control_|db[5]~15|datab" Warning (332126): Node "z80_|bus_control_|db[5]~15|combout" - Warning (332126): Node "z80_|alu_|db_low[1]~12|datac" - Warning (332126): Node "z80_|alu_|db_low[3]~10|dataa" - Warning (332126): Node "z80_|sw1_|db_down[5]~0|datab" + Warning (332126): Node "z80_|alu_|db_high[2]~11|datad" + Warning (332126): Node "z80_|alu_|db_high[0]~20|datab" + Warning (332126): Node "z80_|alu_|db_high[1]~14|datab" + Warning (332126): Node "z80_|sw1_|db_down[5]~0|datac" Warning (332126): Node "z80_|sw1_|db_down[5]~0|combout" Warning (332126): Node "z80_|alu_control_|db[5]~14|dataa" Warning (332126): Node "z80_|alu_control_|db[5]~14|combout" - Warning (332126): Node "z80_|alu_control_|db[5]~15|datad" - Warning (332126): Node "z80_|alu_|db_high[0]~21|datac" - Warning (332126): Node "z80_|alu_|db_low[0]~18|datac" - Warning (332126): Node "z80_|alu_|db_low[0]~18|combout" - Warning (332126): Node "z80_|alu_|db_low[0]~20|dataa" - Warning (332126): Node "z80_|alu_|db_low[0]~20|combout" - Warning (332126): Node "z80_|alu_|db_low[0]~23|datad" - Warning (332126): Node "z80_|alu_|db_high[2]~9|datac" - Warning (332126): Node "z80_|alu_|db_high[2]~9|combout" - Warning (332126): Node "z80_|alu_|db_high[2]~13|dataa" - Warning (332126): Node "z80_|alu_|db_high[2]~13|combout" - Warning (332126): Node "z80_|alu_|db_high[2]~14|datad" - Warning (332126): Node "z80_|alu_|db_high[2]~14|combout" - Warning (332126): Node "z80_|alu_|db[6]~23|dataa" - Warning (332126): Node "z80_|alu_|db[6]~23|combout" - Warning (332126): Node "z80_|alu_|db_high[3]~5|datac" - Warning (332126): Node "z80_|alu_|db_high[3]~5|combout" - Warning (332126): Node "z80_|alu_|db_high[3]~6|datab" - Warning (332126): Node "z80_|alu_|db_high[3]~6|combout" - Warning (332126): Node "z80_|alu_|db_high[3]~7|dataa" - Warning (332126): Node "z80_|alu_|db_high[3]~7|combout" - Warning (332126): Node "z80_|alu_|db_high[3]~8|datac" - Warning (332126): Node "z80_|alu_|db_high[3]~8|combout" - Warning (332126): Node "z80_|alu_|db[7]~21|datac" - Warning (332126): Node "z80_|alu_|db[7]~21|combout" - Warning (332126): Node "z80_|alu_|db_high[3]~6|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~71|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~71|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~73|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~73|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~74|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~74|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~75|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~75|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~19|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~19|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~20|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~20|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~21|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~21|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~75|datac" - Warning (332126): Node "z80_|alu_|db[7]~20|datac" - Warning (332126): Node "z80_|alu_|db[7]~20|combout" - Warning (332126): Node "z80_|alu_|db[7]~21|dataa" - Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~1|dataa" - Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~1|combout" - Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~2|dataa" - Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~2|combout" - Warning (332126): Node "z80_|alu_|db_high[3]~5|datab" - Warning (332126): Node "z80_|alu_|db_low[0]~21|datad" - Warning (332126): Node "z80_|alu_|db_high[2]~11|datad" - Warning (332126): Node "z80_|alu_|db_high[2]~11|combout" - Warning (332126): Node "z80_|alu_|db_high[2]~12|datab" - Warning (332126): Node "z80_|alu_|db_high[2]~12|combout" - Warning (332126): Node "z80_|alu_|db_high[2]~13|datac" - Warning (332126): Node "z80_|alu_control_|db[7]~16|datac" - Warning (332126): Node "z80_|alu_control_|db[7]~16|combout" - Warning (332126): Node "z80_|alu_control_|db[7]~18|datad" - Warning (332126): Node "z80_|alu_control_|db[7]~18|combout" - Warning (332126): Node "z80_|bus_control_|db[7]~5|datab" - Warning (332126): Node "z80_|bus_control_|db[7]~5|combout" - Warning (332126): Node "z80_|bus_control_|db[7]~7|datad" - Warning (332126): Node "z80_|bus_control_|db[7]~7|combout" - Warning (332126): Node "z80_|alu_control_|db[7]~17|datad" - Warning (332126): Node "z80_|alu_control_|db[7]~17|combout" - Warning (332126): Node "z80_|alu_control_|db[7]~18|dataa" - Warning (332126): Node "z80_|alu_|db[7]~20|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~89|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~89|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~90|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~90|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~91|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~91|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~92|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~92|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_ds[7]~0|datac" - Warning (332126): Node "z80_|reg_file_|db_lo_ds[7]~0|combout" - Warning (332126): Node "z80_|alu_control_|db[7]~17|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~22|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~22|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~23|datac" - Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~23|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~24|datac" - Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~24|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~92|dataa" - Warning (332126): Node "z80_|alu_control_|db[6]~20|datab" - Warning (332126): Node "z80_|alu_control_|db[6]~20|combout" - Warning (332126): Node "z80_|alu_control_|db[6]~21|datac" - Warning (332126): Node "z80_|alu_control_|db[6]~21|combout" - Warning (332126): Node "z80_|alu_control_|db[6]~22|datab" - Warning (332126): Node "z80_|alu_control_|db[6]~22|combout" - Warning (332126): Node "z80_|bus_control_|db[6]~8|datab" - Warning (332126): Node "z80_|bus_control_|db[6]~8|combout" - Warning (332126): Node "z80_|bus_control_|db[6]~9|dataa" - Warning (332126): Node "z80_|bus_control_|db[6]~9|combout" - Warning (332126): Node "z80_|alu_control_|db[6]~21|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~79|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~79|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~80|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~80|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~81|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~81|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~82|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~82|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~19|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~19|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~20|datad" - Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~20|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~21|datad" - Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~21|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~82|datab" - Warning (332126): Node "z80_|alu_control_|db[6]~22|datac" - Warning (332126): Node "z80_|alu_|db[6]~22|datad" - Warning (332126): Node "z80_|alu_|db[6]~22|combout" - Warning (332126): Node "z80_|alu_|db[6]~23|datac" - Warning (332126): Node "z80_|alu_|db_high[2]~12|datac" - Warning (332126): Node "z80_|alu_|db_high[1]~17|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~80|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~80|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~82|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~82|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~83|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~83|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~84|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~84|combout" - Warning (332126): Node "z80_|alu_|db[6]~22|datac" - Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~22|datab" - Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~22|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~23|datab" - Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~23|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~24|datad" - Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~24|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~84|datac" - Warning (332126): Node "z80_|alu_|db_low[2]~4|datac" - Warning (332126): Node "z80_|alu_|db_low[2]~4|combout" - Warning (332126): Node "z80_|alu_|db_low[2]~6|dataa" - Warning (332126): Node "z80_|alu_|db_low[2]~6|combout" - Warning (332126): Node "z80_|alu_|db_low[2]~24|datac" - Warning (332126): Node "z80_|alu_|db_high[1]~15|datac" - Warning (332126): Node "z80_|alu_|db_high[1]~15|combout" - Warning (332126): Node "z80_|alu_|db_high[1]~19|dataa" - Warning (332126): Node "z80_|alu_|db_high[3]~27|datac" - Warning (332126): Node "z80_|alu_|db_high[3]~27|combout" - Warning (332126): Node "z80_|alu_|db_high[3]~7|datac" - Warning (332126): Node "z80_|alu_|db[5]~24|datab" - Warning (332126): Node "z80_|alu_|db[5]~24|combout" - Warning (332126): Node "z80_|alu_|db[5]~25|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~66|datad" + Warning (332126): Node "z80_|alu_control_|db[5]~15|datac" + Warning (332126): Node "z80_|alu_|db_low[0]~4|datab" + Warning (332126): Node "z80_|alu_|db_low[3]~16|datab" + Warning (332126): Node "z80_|alu_|db_low[2]~19|datab" + Warning (332126): Node "z80_|alu_|db_low[1]~7|datab" + Warning (332126): Node "z80_|alu_|db_high[3]~2|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~66|datab" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~66|combout" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~67|datad" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~67|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~70|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~70|datad" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~70|combout" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~71|datad" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~71|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~72|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~72|dataa" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~72|combout" - Warning (332126): Node "z80_|alu_control_|db[5]~14|datac" Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~16|dataa" Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~16|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~17|datac" + Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~17|datad" Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~17|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~18|datad" + Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~18|datac" Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~18|combout" Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~72|datab" - Warning (332126): Node "z80_|alu_|db_high[0]~23|datac" - Warning (332126): Node "z80_|alu_|db_high[0]~23|combout" - Warning (332126): Node "z80_|alu_|db_high[0]~24|dataa" - Warning (332126): Node "z80_|alu_|db_high[2]~11|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~53|dataa" + Warning (332126): Node "z80_|alu_control_|db[5]~14|datac" + Warning (332126): Node "z80_|alu_|db[5]~23|dataa" + Warning (332126): Node "z80_|alu_|db[5]~23|combout" + Warning (332126): Node "z80_|alu_|db[5]~24|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~53|datab" Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~53|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~55|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~55|dataa" Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~55|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~56|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~56|datab" Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~56|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~57|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~57|datad" Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~57|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~13|datab" + Warning (332126): Node "z80_|alu_|db[5]~23|datab" + Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~13|dataa" Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~13|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~14|datab" + Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~14|datad" Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~14|combout" Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~15|datad" Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~15|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~57|datac" - Warning (332126): Node "z80_|alu_|db[5]~24|datac" - Warning (332126): Node "z80_|alu_|db_high[1]~18|datac" - Warning (332126): Node "z80_|alu_control_|db[4]~30|dataa" - Warning (332126): Node "z80_|alu_control_|db[4]~30|combout" - Warning (332126): Node "z80_|alu_control_|db[4]~31|datad" - Warning (332126): Node "z80_|alu_control_|db[4]~31|combout" - Warning (332126): Node "z80_|alu_control_|db[4]~32|datad" - Warning (332126): Node "z80_|alu_control_|db[4]~32|combout" - Warning (332126): Node "z80_|bus_control_|db[4]~19|datab" - Warning (332126): Node "z80_|bus_control_|db[4]~19|combout" - Warning (332126): Node "z80_|alu_|db_low[1]~12|datab" - Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2|datab" - Warning (332126): Node "z80_|alu_control_|db[4]~32|dataa" - Warning (332126): Node "z80_|alu_|db_high[0]~21|datab" - Warning (332126): Node "z80_|alu_|db_low[0]~18|datab" - Warning (332126): Node "z80_|alu_|db_high[2]~9|datab" - Warning (332126): Node "z80_|alu_|db_low[2]~4|datab" - Warning (332126): Node "z80_|alu_|db_high[1]~15|datab" - Warning (332126): Node "z80_|alu_|db_high[3]~27|datab" - Warning (332126): Node "z80_|alu_|db[4]~16|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~54|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~54|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~61|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~61|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~62|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~62|combout" - Warning (332126): Node "z80_|alu_control_|db[4]~30|datac" - Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~13|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~13|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~14|datab" - Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~14|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~15|datad" - Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~15|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~62|datac" - Warning (332126): Node "z80_|alu_|db_low[0]~18|datad" - Warning (332126): Node "z80_|alu_|db_high[2]~9|datad" - Warning (332126): Node "z80_|alu_|db_low[2]~4|datad" - Warning (332126): Node "z80_|alu_|db_high[1]~15|datad" - Warning (332126): Node "z80_|alu_|db_high[3]~27|datad" - Warning (332126): Node "z80_|sw1_|db_down[3]~1|datad" - Warning (332126): Node "z80_|sw1_|db_down[3]~1|combout" - Warning (332126): Node "z80_|alu_control_|db[3]~34|datad" - Warning (332126): Node "z80_|alu_|db_low[3]~8|dataa" - Warning (332126): Node "z80_|alu_|db_high[0]~23|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~44|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~44|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~46|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~46|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~47|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~47|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~48|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~48|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~10|dataa" - Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~10|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~11|datac" - Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~11|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~12|datad" - Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~12|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~48|datac" - Warning (332126): Node "z80_|alu_|db[3]~10|datac" - Warning (332126): Node "z80_|alu_|db_low[2]~2|datab" - Warning (332126): Node "z80_|alu_control_|db[1]~24|datad" - Warning (332126): Node "z80_|alu_control_|db[1]~24|combout" - Warning (332126): Node "z80_|alu_control_|db[1]~26|datad" - Warning (332126): Node "z80_|alu_control_|db[1]~26|combout" - Warning (332126): Node "z80_|bus_control_|db[1]~10|datab" - Warning (332126): Node "z80_|bus_control_|db[1]~10|combout" - Warning (332126): Node "z80_|bus_control_|db[1]~11|datac" - Warning (332126): Node "z80_|bus_control_|db[1]~11|combout" - Warning (332126): Node "z80_|alu_control_|db[1]~25|dataa" - Warning (332126): Node "z80_|alu_control_|db[1]~25|combout" - Warning (332126): Node "z80_|alu_control_|db[1]~26|dataa" - Warning (332126): Node "z80_|alu_|db[1]~12|datab" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~29|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~29|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~30|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~30|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~31|dataa" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~31|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~32|datad" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~32|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_ds[1]~1|datac" - Warning (332126): Node "z80_|reg_file_|db_lo_ds[1]~1|combout" - Warning (332126): Node "z80_|alu_control_|db[1]~25|datab" - Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~4|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~4|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~5|datad" - Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~5|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~6|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~6|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~32|datac" - Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~1|datac" - Warning (332126): Node "z80_|alu_|db_low[0]~22|datac" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~26|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~57|dataa" + Warning (332126): Node "z80_|alu_control_|db[7]~16|datab" + Warning (332126): Node "z80_|alu_control_|db[7]~16|combout" + Warning (332126): Node "z80_|alu_control_|db[7]~17|datab" + Warning (332126): Node "z80_|alu_control_|db[7]~17|combout" + Warning (332126): Node "z80_|alu_control_|db[7]~18|datad" + Warning (332126): Node "z80_|alu_control_|db[7]~18|combout" + Warning (332126): Node "z80_|alu_control_|db[7]~19|dataa" + Warning (332126): Node "z80_|alu_control_|db[7]~19|combout" + Warning (332126): Node "z80_|bus_control_|db[7]~5|datad" + Warning (332126): Node "z80_|bus_control_|db[7]~5|combout" + Warning (332126): Node "z80_|bus_control_|db[7]~7|datab" + Warning (332126): Node "z80_|bus_control_|db[7]~7|combout" + Warning (332126): Node "z80_|alu_control_|db[7]~18|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~88|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~88|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~89|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~89|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~90|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~90|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~91|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~91|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~22|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~22|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~23|dataa" + Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~23|combout" + Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~24|datab" + Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~24|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~91|datad" + Warning (332126): Node "z80_|alu_control_|db[7]~17|dataa" + Warning (332126): Node "z80_|alu_|db[7]~11|datab" + Warning (332126): Node "z80_|alu_|db[7]~11|combout" + Warning (332126): Node "z80_|alu_|db[7]~12|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~71|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~71|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~73|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~73|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~74|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~74|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~75|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~75|combout" + Warning (332126): Node "z80_|alu_|db[7]~11|datad" + Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~19|datad" + Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~19|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~20|datad" + Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~20|combout" + Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~21|datad" + Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~21|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~75|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~26|datab" Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~26|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~28|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~28|datad" Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~28|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~29|datac" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~29|datab" Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~29|combout" - Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~30|datad" + Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~30|datab" Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~30|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~4|datab" + Warning (332126): Node "z80_|alu_|db[0]~13|datab" + Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~4|datad" Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~4|combout" Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~5|datad" Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~5|combout" - Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~6|datad" + Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~6|datab" Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~6|combout" Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~30|dataa" - Warning (332126): Node "z80_|alu_|db[0]~18|datac" - Warning (332126): Node "z80_|sw2_|db_up[0]~0|datad" + Warning (332126): Node "z80_|alu_|db_low[1]~10|datab" + Warning (332126): Node "z80_|alu_|db_low[0]~3|datad" + Warning (332126): Node "z80_|sw2_|db_up[0]~0|datac" Warning (332126): Node "z80_|sw2_|db_up[0]~0|combout" - Warning (332126): Node "z80_|alu_control_|db[0]~9|datad" - Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~0|dataa" - Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~0|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~1|datad" - Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~1|combout" - Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~3|dataa" -Critical Warning (332081): Design contains combinational loop of 511 nodes. Estimating the delays through the loop. + Warning (332126): Node "z80_|alu_control_|db[0]~9|dataa" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~12|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~12|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~17|datab" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~17|combout" + Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~22|datad" +Critical Warning (332081): Design contains combinational loop of 517 nodes. Estimating the delays through the loop. Warning (332060): Node: ula:ula_|clocks:clocks_|clk_cpu was determined to be a clock but was found without an associated clock assignment. Warning (332060): Node: KEY[1] was determined to be a clock but was found without an associated clock assignment. Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. @@ -39730,34 +39736,34 @@ Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON Info: Analyzing Slow 1200mV 85C Model Critical Warning (332148): Timing requirements not met Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer. -Info (332146): Worst-case setup slack is -18.123 +Info (332146): Worst-case setup slack is -18.425 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): -18.123 -549.338 CLOCK_50 - Info (332119): -7.533 -284.813 ula_|pll_|altpll_component|auto_generated|pll1|clk[0] - Info (332119): -4.740 -42.810 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] - Info (332119): -2.914 -2.914 ula_|pll_|altpll_component|auto_generated|pll1|clk[1] -Info (332146): Worst-case hold slack is 0.210 + Info (332119): -18.425 -546.891 CLOCK_50 + Info (332119): -6.923 -271.506 ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + Info (332119): -4.745 -42.191 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + Info (332119): -2.915 -2.915 ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Info (332146): Worst-case hold slack is 0.342 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): 0.210 0.000 CLOCK_50 Info (332119): 0.342 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[1] - Info (332119): 0.344 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + Info (332119): 0.342 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Info (332119): 0.357 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Info (332146): Worst-case recovery slack is -6.223 + Info (332119): 0.517 0.000 CLOCK_50 +Info (332146): Worst-case recovery slack is -6.263 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): -6.223 -459.348 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Info (332146): Worst-case removal slack is 3.698 + Info (332119): -6.263 -464.840 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Info (332146): Worst-case removal slack is 3.657 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): 3.698 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + Info (332119): 3.657 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Info (332146): Worst-case minimum pulse width slack is 9.488 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 9.488 0.000 CLOCK_50 Info (332119): 19.602 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[0] - Info (332119): 20.595 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + Info (332119): 20.597 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Info (332119): 35.503 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Info: Analyzing Slow 1200mV 0C Model Info (334003): Started post-fitting delay annotation @@ -39767,34 +39773,34 @@ Warning (332060): Node: KEY[1] was determined to be a clock but was found withou Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. Critical Warning (332148): Timing requirements not met Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer. -Info (332146): Worst-case setup slack is -17.311 +Info (332146): Worst-case setup slack is -17.572 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): -17.311 -526.609 CLOCK_50 - Info (332119): -6.686 -253.661 ula_|pll_|altpll_component|auto_generated|pll1|clk[0] - Info (332119): -4.428 -40.009 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] - Info (332119): -2.785 -2.785 ula_|pll_|altpll_component|auto_generated|pll1|clk[1] -Info (332146): Worst-case hold slack is 0.298 + Info (332119): -17.572 -524.603 CLOCK_50 + Info (332119): -6.192 -241.805 ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + Info (332119): -4.414 -39.436 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + Info (332119): -2.786 -2.786 ula_|pll_|altpll_component|auto_generated|pll1|clk[1] +Info (332146): Worst-case hold slack is 0.297 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== + Info (332119): 0.297 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Info (332119): 0.298 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[1] - Info (332119): 0.300 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] - Info (332119): 0.304 0.000 CLOCK_50 Info (332119): 0.311 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Info (332146): Worst-case recovery slack is -5.744 + Info (332119): 0.467 0.000 CLOCK_50 +Info (332146): Worst-case recovery slack is -5.773 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): -5.744 -423.582 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Info (332146): Worst-case removal slack is 3.374 + Info (332119): -5.773 -427.930 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Info (332146): Worst-case removal slack is 3.347 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): 3.374 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + Info (332119): 3.347 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Info (332146): Worst-case minimum pulse width slack is 9.489 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 9.489 0.000 CLOCK_50 - Info (332119): 19.600 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[0] - Info (332119): 20.591 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + Info (332119): 19.601 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 20.590 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Info (332119): 35.491 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Info: Analyzing Fast 1200mV 0C Model Warning (332060): Node: ula:ula_|clocks:clocks_|clk_cpu was determined to be a clock but was found without an associated clock assignment. @@ -39802,28 +39808,28 @@ Warning (332060): Node: KEY[1] was determined to be a clock but was found withou Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. Critical Warning (332148): Timing requirements not met Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer. -Info (332146): Worst-case setup slack is -14.971 +Info (332146): Worst-case setup slack is -15.171 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): -14.971 -442.545 CLOCK_50 - Info (332119): -4.979 -171.124 ula_|pll_|altpll_component|auto_generated|pll1|clk[0] - Info (332119): -3.775 -35.541 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + Info (332119): -15.171 -440.252 CLOCK_50 + Info (332119): -4.743 -163.399 ula_|pll_|altpll_component|auto_generated|pll1|clk[0] + Info (332119): -3.815 -35.260 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Info (332119): -2.784 -2.784 ula_|pll_|altpll_component|auto_generated|pll1|clk[1] -Info (332146): Worst-case hold slack is -0.053 +Info (332146): Worst-case hold slack is 0.112 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): -0.053 -0.089 CLOCK_50 + Info (332119): 0.112 0.000 CLOCK_50 Info (332119): 0.177 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Info (332119): 0.178 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Info (332119): 0.186 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[0] -Info (332146): Worst-case recovery slack is -4.693 +Info (332146): Worst-case recovery slack is -4.728 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): -4.693 -358.284 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] -Info (332146): Worst-case removal slack is 2.518 + Info (332119): -4.728 -362.420 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] +Info (332146): Worst-case removal slack is 2.503 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): 2.518 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] + Info (332119): 2.503 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2] Info (332146): Worst-case minimum pulse width slack is 9.208 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== @@ -39833,9 +39839,9 @@ Info (332146): Worst-case minimum pulse width slack is 9.208 Info (332119): 35.535 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[1] Info (332102): Design is not fully constrained for setup requirements Info (332102): Design is not fully constrained for hold requirements -Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 532 warnings - Info: Peak virtual memory: 437 megabytes - Info: Processing ended: Fri Apr 1 18:55:48 2022 +Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 538 warnings + Info: Peak virtual memory: 440 megabytes + Info: Processing ended: Sat Apr 2 15:53:41 2022 Info: Elapsed time: 00:00:04 Info: Total CPU time (on all processors): 00:00:04 diff --git a/output_files/spectrum.sta.summary b/output_files/spectrum.sta.summary index 337cec4..541f396 100644 --- a/output_files/spectrum.sta.summary +++ b/output_files/spectrum.sta.summary @@ -3,43 +3,43 @@ TimeQuest Timing Analyzer Summary ------------------------------------------------------------ Type : Slow 1200mV 85C Model Setup 'CLOCK_50' -Slack : -18.123 -TNS : -549.338 +Slack : -18.425 +TNS : -546.891 Type : Slow 1200mV 85C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' -Slack : -7.533 -TNS : -284.813 +Slack : -6.923 +TNS : -271.506 Type : Slow 1200mV 85C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' -Slack : -4.740 -TNS : -42.810 +Slack : -4.745 +TNS : -42.191 Type : Slow 1200mV 85C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' -Slack : -2.914 -TNS : -2.914 - -Type : Slow 1200mV 85C Model Hold 'CLOCK_50' -Slack : 0.210 -TNS : 0.000 +Slack : -2.915 +TNS : -2.915 Type : Slow 1200mV 85C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' Slack : 0.342 TNS : 0.000 Type : Slow 1200mV 85C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' -Slack : 0.344 +Slack : 0.342 TNS : 0.000 Type : Slow 1200mV 85C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' Slack : 0.357 TNS : 0.000 +Type : Slow 1200mV 85C Model Hold 'CLOCK_50' +Slack : 0.517 +TNS : 0.000 + Type : Slow 1200mV 85C Model Recovery 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' -Slack : -6.223 -TNS : -459.348 +Slack : -6.263 +TNS : -464.840 Type : Slow 1200mV 85C Model Removal 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' -Slack : 3.698 +Slack : 3.657 TNS : 0.000 Type : Slow 1200mV 85C Model Minimum Pulse Width 'CLOCK_50' @@ -51,7 +51,7 @@ Slack : 19.602 TNS : 0.000 Type : Slow 1200mV 85C Model Minimum Pulse Width 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' -Slack : 20.595 +Slack : 20.597 TNS : 0.000 Type : Slow 1200mV 85C Model Minimum Pulse Width 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' @@ -59,43 +59,43 @@ Slack : 35.503 TNS : 0.000 Type : Slow 1200mV 0C Model Setup 'CLOCK_50' -Slack : -17.311 -TNS : -526.609 +Slack : -17.572 +TNS : -524.603 Type : Slow 1200mV 0C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' -Slack : -6.686 -TNS : -253.661 +Slack : -6.192 +TNS : -241.805 Type : Slow 1200mV 0C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' -Slack : -4.428 -TNS : -40.009 +Slack : -4.414 +TNS : -39.436 Type : Slow 1200mV 0C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' -Slack : -2.785 -TNS : -2.785 +Slack : -2.786 +TNS : -2.786 + +Type : Slow 1200mV 0C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' +Slack : 0.297 +TNS : 0.000 Type : Slow 1200mV 0C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' Slack : 0.298 TNS : 0.000 -Type : Slow 1200mV 0C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' -Slack : 0.300 -TNS : 0.000 - -Type : Slow 1200mV 0C Model Hold 'CLOCK_50' -Slack : 0.304 -TNS : 0.000 - Type : Slow 1200mV 0C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' Slack : 0.311 TNS : 0.000 +Type : Slow 1200mV 0C Model Hold 'CLOCK_50' +Slack : 0.467 +TNS : 0.000 + Type : Slow 1200mV 0C Model Recovery 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' -Slack : -5.744 -TNS : -423.582 +Slack : -5.773 +TNS : -427.930 Type : Slow 1200mV 0C Model Removal 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' -Slack : 3.374 +Slack : 3.347 TNS : 0.000 Type : Slow 1200mV 0C Model Minimum Pulse Width 'CLOCK_50' @@ -103,11 +103,11 @@ Slack : 9.489 TNS : 0.000 Type : Slow 1200mV 0C Model Minimum Pulse Width 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' -Slack : 19.600 +Slack : 19.601 TNS : 0.000 Type : Slow 1200mV 0C Model Minimum Pulse Width 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' -Slack : 20.591 +Slack : 20.590 TNS : 0.000 Type : Slow 1200mV 0C Model Minimum Pulse Width 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' @@ -115,24 +115,24 @@ Slack : 35.491 TNS : 0.000 Type : Fast 1200mV 0C Model Setup 'CLOCK_50' -Slack : -14.971 -TNS : -442.545 +Slack : -15.171 +TNS : -440.252 Type : Fast 1200mV 0C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' -Slack : -4.979 -TNS : -171.124 +Slack : -4.743 +TNS : -163.399 Type : Fast 1200mV 0C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' -Slack : -3.775 -TNS : -35.541 +Slack : -3.815 +TNS : -35.260 Type : Fast 1200mV 0C Model Setup 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' Slack : -2.784 TNS : -2.784 Type : Fast 1200mV 0C Model Hold 'CLOCK_50' -Slack : -0.053 -TNS : -0.089 +Slack : 0.112 +TNS : 0.000 Type : Fast 1200mV 0C Model Hold 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' Slack : 0.177 @@ -147,11 +147,11 @@ Slack : 0.186 TNS : 0.000 Type : Fast 1200mV 0C Model Recovery 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' -Slack : -4.693 -TNS : -358.284 +Slack : -4.728 +TNS : -362.420 Type : Fast 1200mV 0C Model Removal 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' -Slack : 2.518 +Slack : 2.503 TNS : 0.000 Type : Fast 1200mV 0C Model Minimum Pulse Width 'CLOCK_50' diff --git a/simulation/modelsim/spectrum.vo b/simulation/modelsim/spectrum.vo index c5a510e..423ba37 100644 --- a/simulation/modelsim/spectrum.vo +++ b/simulation/modelsim/spectrum.vo @@ -16,7 +16,7 @@ // PROGRAM "Quartus II 32-bit" // VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" -// DATE "04/01/2022 18:55:52" +// DATE "04/02/2022 15:53:44" // // Device: Altera EP4CE22F17C6 Package FBGA256 @@ -56,8 +56,8 @@ input CLOCK_50; input [1:0] KEY; input PS2_CLK; input PS2_DAT; -output I2C_SCLK; -output I2C_SDAT; +inout I2C_SCLK; +inout I2C_SDAT; output AUD_XCK; output AUD_ADCLRCK; output AUD_DACLRCK; @@ -178,786 +178,67 @@ wire \SW[2]~input_o ; wire \ula_|clocks_|clk_cpu~0_combout ; wire \ula_|clocks_|clk_cpu~q ; wire \ula_|clocks_|clk_cpu~clkctrl_outclk ; -wire \z80_|sequencer_|DFFE_M1_ff~0_combout ; -wire \z80_|sequencer_|ena_M~combout ; +wire \z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ; +wire \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ; wire \KEY[1]~input_o ; wire \z80_|interrupts_|nmi_armed~feeder_combout ; wire \z80_|interrupts_|SYNTHESIZED_WIRE_9~combout ; wire \z80_|interrupts_|nmi_armed~q ; wire \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder_combout ; -wire \z80_|execute_|ctl_eval_cond~0_combout ; -wire \z80_|execute_|ixy_d~4_combout ; +wire \z80_|sequencer_|DFFE_M2_ff~0_combout ; +wire \z80_|sequencer_|DFFE_M2_ff~q ; wire \z80_|sequencer_|DFFE_M3_ff~0_combout ; wire \z80_|sequencer_|DFFE_M3_ff~q ; -wire \z80_|execute_|fIOWrite~1_combout ; wire \z80_|sequencer_|DFFE_M4_ff~0_combout ; wire \z80_|sequencer_|DFFE_M4_ff~q ; -wire \z80_|pla_decode_|Equal32~0_combout ; -wire \z80_|resets_|SYNTHESIZED_WIRE_11~combout ; -wire \z80_|decode_state_|table_xx~0_combout ; -wire \z80_|pla_decode_|Equal1~7_combout ; -wire \z80_|pla_decode_|Equal2~0_combout ; -wire \z80_|pla_decode_|Equal36~0_combout ; -wire \z80_|execute_|ctl_state_tbl_cb_set~combout ; -wire \z80_|execute_|ctl_state_tbl_we~8_combout ; -wire \z80_|decode_state_|DFFE_instCB~q ; -wire \z80_|pla_decode_|Equal52~0_combout ; -wire \z80_|pla_decode_|Equal2~1_combout ; -wire \z80_|execute_|ctl_state_tbl_ed_set~combout ; -wire \z80_|decode_state_|DFFE_instED~q ; -wire \z80_|pla_decode_|Equal13~0_combout ; -wire \z80_|pla_decode_|Equal33~0_combout ; -wire \z80_|execute_|ctl_im_we~combout ; -wire \z80_|pla_decode_|Equal49~0_combout ; -wire \z80_|pla_decode_|Equal33~1_combout ; -wire \z80_|pla_decode_|Equal6~0_combout ; -wire \z80_|execute_|ctl_mRead~14_combout ; -wire \z80_|pla_decode_|Equal12~0_combout ; -wire \z80_|execute_|ctl_sw_1d~8_combout ; -wire \z80_|nM1_int~2_combout ; -wire \z80_|execute_|ctl_sw_1d~5_combout ; -wire \z80_|pla_decode_|Equal3~0_combout ; -wire \z80_|execute_|ctl_mRead~4_combout ; -wire \z80_|execute_|ixy_d~7_combout ; -wire \z80_|execute_|ctl_state_alu~4_combout ; -wire \z80_|execute_|ctl_sw_1d~4_combout ; -wire \z80_|pla_decode_|Equal40~1_combout ; -wire \z80_|pla_decode_|Equal39~0_combout ; -wire \z80_|execute_|ctl_bus_db_oe~1_combout ; -wire \z80_|pla_decode_|Equal13~1_combout ; -wire \z80_|pla_decode_|Equal13~2_combout ; -wire \z80_|pla_decode_|Equal3~2_combout ; -wire \z80_|execute_|ctl_state_iy_set~2_combout ; -wire \z80_|execute_|ixy_d~8_combout ; -wire \z80_|execute_|ixy_d~6_combout ; -wire \z80_|execute_|ixy_d~9_combout ; -wire \z80_|execute_|ixy_d~12_combout ; -wire \z80_|execute_|ixy_d~10_combout ; -wire \z80_|pla_decode_|Equal44~0_combout ; -wire \z80_|execute_|ixy_d~16_combout ; -wire \z80_|execute_|ixy_d~13_combout ; -wire \z80_|pla_decode_|Equal50~0_combout ; -wire \z80_|pla_decode_|Equal33~2_combout ; -wire \z80_|execute_|ixy_d~17_combout ; -wire \z80_|execute_|ixy_d~5_combout ; -wire \z80_|execute_|ixy_d~14_combout ; -wire \z80_|execute_|ixy_d~11_combout ; -wire \z80_|execute_|ixy_d~15_combout ; -wire \z80_|execute_|ctl_state_ixiy_we~2_combout ; -wire \z80_|decode_state_|DFFE_instIY1~q ; -wire \z80_|execute_|ctl_ir_we~5_combout ; -wire \z80_|execute_|ctl_ir_we~14_combout ; -wire \z80_|execute_|ctl_mWrite~2_combout ; -wire \z80_|execute_|ctl_mWrite~16_combout ; -wire \z80_|execute_|ctl_flags_alu~18_combout ; -wire \z80_|execute_|ctl_mRead~26_combout ; -wire \z80_|execute_|ctl_mRead~27_combout ; -wire \z80_|execute_|ctl_bus_db_oe~7_combout ; -wire \z80_|execute_|ctl_sw_2d~5_combout ; -wire \z80_|execute_|ctl_mRead~18_combout ; -wire \z80_|pla_decode_|Equal55~0_combout ; -wire \z80_|execute_|comb~1_combout ; -wire \z80_|execute_|ctl_mRead~15_combout ; -wire \z80_|execute_|ctl_mRead~17_combout ; -wire \z80_|execute_|ctl_reg_in_hi~5_combout ; -wire \z80_|execute_|ctl_mRead~9_combout ; -wire \z80_|pla_decode_|Equal9~0_combout ; -wire \z80_|execute_|ctl_mRead~10_combout ; -wire \z80_|execute_|ctl_mRead~8_combout ; -wire \z80_|execute_|ctl_mRead~20_combout ; -wire \z80_|pla_decode_|Equal12~1_combout ; -wire \z80_|pla_decode_|Equal9~1_combout ; -wire \z80_|pla_decode_|Equal25~0_combout ; -wire \z80_|execute_|ctl_mRead~21_combout ; -wire \z80_|execute_|ctl_state_alu~6_combout ; -wire \z80_|pla_decode_|Equal19~0_combout ; -wire \z80_|pla_decode_|Equal1~4_combout ; -wire \z80_|pla_decode_|Equal29~0_combout ; -wire \z80_|pla_decode_|Equal24~1_combout ; -wire \z80_|pla_decode_|Equal34~0_combout ; -wire \z80_|pla_decode_|Equal37~0_combout ; -wire \z80_|pla_decode_|Equal35~0_combout ; -wire \z80_|pla_decode_|Equal38~2_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~2_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~3_combout ; -wire \z80_|execute_|comb~0_combout ; -wire \z80_|pla_decode_|Equal47~0_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~4_combout ; -wire \z80_|execute_|ctl_mRead~22_combout ; -wire \z80_|execute_|ctl_mRead~24_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ; -wire \z80_|execute_|ctl_reg_in_hi~6_combout ; -wire \z80_|pla_decode_|Equal6~1_combout ; -wire \z80_|execute_|ctl_mRead~16_combout ; wire \z80_|sequencer_|M5~0_combout ; wire \z80_|sequencer_|M5~q ; -wire \z80_|execute_|ctl_reg_in_hi~2_combout ; -wire \z80_|execute_|setM1~29_combout ; -wire \z80_|execute_|ctl_mRead~25_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~6_combout ; -wire \z80_|execute_|ctl_ir_we~7_combout ; -wire \z80_|pla_decode_|Equal52~1_combout ; -wire \z80_|execute_|ctl_state_alu~14_combout ; -wire \z80_|execute_|ctl_state_alu~8_combout ; -wire \z80_|pla_decode_|Equal24~0_combout ; -wire \z80_|reg_control_|reg_sel_pc~0_combout ; -wire \z80_|reg_control_|reg_sel_pc~1_combout ; -wire \z80_|reg_control_|reg_sel_pc~2_combout ; -wire \z80_|execute_|fMRead~17_combout ; -wire \z80_|execute_|ctl_mRead~6_combout ; -wire \z80_|pla_decode_|Equal11~0_combout ; -wire \z80_|pla_decode_|Equal10~0_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~9_combout ; -wire \z80_|execute_|ctl_sw_2d~4_combout ; -wire \z80_|execute_|ctl_ir_we~15_combout ; -wire \z80_|execute_|fMRead~16_combout ; -wire \z80_|execute_|ctl_ir_we~9_combout ; -wire \z80_|pla_decode_|Equal46~0_combout ; -wire \z80_|execute_|ctl_ir_we~10_combout ; -wire \z80_|execute_|ctl_flags_alu~17_combout ; -wire \z80_|execute_|ctl_flags_alu~6_combout ; -wire \z80_|execute_|ctl_ir_we~6_combout ; -wire \z80_|execute_|ctl_ir_we~8_combout ; -wire \z80_|execute_|ctl_flags_alu~16_combout ; -wire \z80_|execute_|ctl_reg_in_hi~3_combout ; -wire \z80_|execute_|ctl_mWrite~8_combout ; -wire \z80_|execute_|fMRead~18_combout ; -wire \z80_|execute_|fMRead~19_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~16_combout ; -wire \z80_|execute_|ctl_mRead~36_combout ; -wire \z80_|execute_|ctl_alu_op_low~9_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~44_combout ; -wire \z80_|execute_|ctl_mRead~11_combout ; -wire \z80_|execute_|ctl_sw_2d~6_combout ; -wire \z80_|execute_|ctl_sw_2d~7_combout ; -wire \z80_|execute_|ctl_mWrite~7_combout ; -wire \z80_|execute_|ctl_ir_we~11_combout ; -wire \z80_|execute_|ctl_ir_we~12_combout ; -wire \z80_|execute_|ctl_flags_sz_we~0_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ; -wire \z80_|execute_|ctl_sw_2d~8_combout ; -wire \z80_|execute_|ctl_sw_2d~9_combout ; -wire \z80_|execute_|ctl_sw_1d~6_combout ; -wire \z80_|execute_|ctl_sw_1d~7_combout ; -wire \z80_|execute_|ctl_alu_op_low~8_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ; -wire \z80_|execute_|ctl_reg_out_hi~4_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~15_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~38_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_zero~combout ; -wire \z80_|alu_|db_low[2]~4_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~14_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ; -wire \z80_|execute_|ctl_sw_4u~1_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~5_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~30_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~29_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~31_combout ; -wire \z80_|pla_decode_|Equal69~0_combout ; -wire \z80_|pla_decode_|Equal1~5_combout ; -wire \z80_|execute_|ctl_alu_op_low~14_combout ; -wire \z80_|execute_|ctl_alu_op_low~12_combout ; -wire \z80_|pla_decode_|Equal56~0_combout ; -wire \z80_|execute_|ctl_alu_op_low~11_combout ; -wire \z80_|execute_|nextM~2_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~16_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~4_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~5_combout ; -wire \z80_|execute_|ctl_alu_oe~3_combout ; -wire \z80_|execute_|ctl_alu_op_low~15_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~8_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~9_combout ; -wire \z80_|execute_|ctl_alu_core_R~3_combout ; -wire \z80_|execute_|ctl_alu_core_R~4_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~10_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~11_combout ; -wire \z80_|pla_decode_|Equal48~0_combout ; -wire \z80_|execute_|ctl_flags_hf2_we~combout ; -wire \z80_|execute_|ctl_alu_shift_oe~41_combout ; -wire \z80_|execute_|ctl_flags_xy_we~18_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~17_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~19_combout ; -wire \z80_|execute_|ctl_iorw~10_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~18_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~20_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~13_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~9_combout ; -wire \z80_|execute_|ctl_bus_db_oe~3_combout ; -wire \z80_|pla_decode_|Equal20~0_combout ; -wire \z80_|pla_decode_|Equal68~2_combout ; -wire \z80_|execute_|ctl_flags_bus~14_combout ; -wire \z80_|execute_|ctl_alu_op_low~13_combout ; -wire \z80_|execute_|ctl_flags_bus~15_combout ; -wire \z80_|execute_|ctl_flags_bus~11_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~11_combout ; -wire \z80_|execute_|ctl_flags_bus~10_combout ; -wire \z80_|execute_|ctl_flags_bus~8_combout ; -wire \z80_|execute_|ctl_flags_bus~9_combout ; -wire \z80_|execute_|ctl_flags_bus~12_combout ; -wire \z80_|execute_|ctl_flags_xy_we~11_combout ; -wire \z80_|execute_|ctl_flags_xy_we~12_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~6_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~7_combout ; -wire \z80_|execute_|ctl_ir_we~4_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~8_combout ; -wire \z80_|execute_|ctl_bus_db_oe~0_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~12_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~13_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~14_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~15_combout ; -wire \z80_|execute_|ctl_66_oe~2_combout ; -wire \z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ; -wire \z80_|execute_|ctl_alu_op1_sel_zero~5_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_zero~4_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_zero~combout ; -wire \z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_lq~combout ; -wire \z80_|execute_|ctl_alu_op_low~10_combout ; -wire \z80_|execute_|fMWrite~11_combout ; -wire \z80_|execute_|ctl_alu_op_low~21_combout ; +wire \z80_|execute_|ixy_d~5_combout ; wire \z80_|execute_|ctl_alu_op_low~22_combout ; -wire \z80_|execute_|ctl_alu_op_low~16_combout ; -wire \z80_|execute_|ctl_alu_op_low~17_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ; -wire \z80_|execute_|ctl_reg_gp_sel~36_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~4_combout ; -wire \z80_|execute_|ctl_state_alu~5_combout ; -wire \z80_|execute_|ctl_alu_op_low~18_combout ; -wire \z80_|execute_|ctl_alu_op_low~19_combout ; -wire \z80_|execute_|ctl_alu_op_low~33_combout ; -wire \z80_|execute_|ctl_alu_op_low~20_combout ; -wire \z80_|execute_|ctl_alu_op_low~23_combout ; -wire \z80_|execute_|ctl_alu_op_low~24_combout ; -wire \z80_|execute_|ctl_alu_op_low~25_combout ; -wire \z80_|execute_|ctl_alu_op_low~34_combout ; -wire \z80_|execute_|ctl_alu_op_low~combout ; -wire \z80_|execute_|ctl_alu_shift_oe~40_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~37_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~39_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~46_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~42_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~21_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~45_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~22_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~23_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~24_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~25_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~14_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~26_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~27_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~28_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~10_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~11_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~32_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~33_combout ; -wire \z80_|execute_|ctl_reg_use_sp~0_combout ; -wire \z80_|execute_|ctl_reg_use_sp~1_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~12_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~47_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~34_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~35_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~36_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~43_combout ; -wire \z80_|execute_|ctl_reg_in_lo~9_combout ; -wire \z80_|execute_|ctl_alu_op1_oe~0_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ; -wire \z80_|execute_|ctl_alu_op1_oe~1_combout ; -wire \z80_|execute_|ctl_flags_xy_we~8_combout ; -wire \z80_|execute_|ctl_flags_xy_we~9_combout ; -wire \z80_|pla_decode_|Equal8~0_combout ; -wire \z80_|execute_|ctl_flags_alu~9_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~4_combout ; -wire \z80_|execute_|ctl_flags_sz_we~3_combout ; -wire \z80_|pla_decode_|Equal11~1_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ; -wire \z80_|execute_|ctl_flags_alu~10_combout ; -wire \z80_|execute_|ctl_flags_alu~11_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ; -wire \z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ; -wire \z80_|execute_|ctl_flags_use_cf2~13_combout ; -wire \z80_|execute_|ctl_flags_cf_we~7_combout ; -wire \z80_|execute_|ctl_pf_sel[0]~2_combout ; -wire \z80_|execute_|ctl_alu_oe~2_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~25_combout ; -wire \z80_|execute_|ctl_flags_hf_we~5_combout ; -wire \z80_|execute_|ctl_flags_pf_we~10_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ; -wire \z80_|execute_|ctl_flags_pf_we~2_combout ; -wire \z80_|execute_|ctl_flags_pf_we~3_combout ; -wire \z80_|execute_|ctl_flags_xy_we~17_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~5_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~6_combout ; -wire \z80_|execute_|ctl_flags_xy_we~10_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ; -wire \z80_|execute_|ctl_state_alu~7_combout ; -wire \z80_|execute_|ctl_flags_sz_we~1_combout ; -wire \z80_|execute_|ctl_flags_cf_we~2_combout ; -wire \z80_|execute_|ctl_alu_core_S~6_combout ; -wire \z80_|execute_|ctl_alu_core_S~7_combout ; -wire \z80_|execute_|ctl_alu_core_S~4_combout ; -wire \z80_|execute_|ctl_alu_core_S~5_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ; -wire \z80_|execute_|ctl_alu_res_oe~0_combout ; -wire \z80_|execute_|ctl_alu_oe~15_combout ; -wire \z80_|execute_|ctl_alu_res_oe~1_combout ; -wire \z80_|execute_|ctl_alu_res_oe~2_combout ; -wire \z80_|execute_|ctl_alu_op2_oe~0_combout ; -wire \z80_|alu_|db_high[3]~2_combout ; -wire \z80_|alu_|db_high[3]~3_combout ; -wire \z80_|alu_|db_low[2]~24_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~7_combout ; -wire \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ; -wire \z80_|execute_|ctl_reg_in_hi~8_combout ; -wire \z80_|execute_|ctl_alu_oe~8_combout ; -wire \z80_|execute_|ctl_alu_oe~4_combout ; -wire \z80_|execute_|ctl_mWrite~9_combout ; -wire \z80_|execute_|ctl_alu_core_S~10_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~43_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~26_combout ; -wire \z80_|execute_|ctl_bus_db_we~5_combout ; -wire \z80_|execute_|ctl_alu_oe~9_combout ; -wire \z80_|execute_|ctl_alu_oe~11_combout ; -wire \z80_|execute_|ctl_alu_oe~5_combout ; -wire \z80_|execute_|ctl_alu_core_S~11_combout ; -wire \z80_|execute_|ctl_alu_oe~6_combout ; -wire \z80_|execute_|ctl_alu_oe~7_combout ; -wire \z80_|execute_|ctl_alu_oe~12_combout ; -wire \z80_|execute_|ctl_alu_oe~13_combout ; -wire \z80_|execute_|ctl_alu_oe~14_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~24_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~27_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ; -wire \z80_|execute_|ctl_reg_out_hi~8_combout ; -wire \z80_|execute_|setM1~54_combout ; -wire \z80_|execute_|ctl_sw_2u~1_combout ; -wire \z80_|execute_|ctl_sw_2u~4_combout ; -wire \z80_|execute_|ctl_sw_2u~5_combout ; -wire \z80_|execute_|ctl_sw_2u~6_combout ; -wire \z80_|execute_|ctl_inc_cy~35_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ; -wire \z80_|execute_|ctl_mWrite~6_combout ; -wire \z80_|execute_|ctl_sw_2u~2_combout ; -wire \z80_|execute_|ctl_sw_2u~0_combout ; -wire \z80_|execute_|ctl_sw_2u~3_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ; -wire \z80_|execute_|ctl_reg_out_lo~2_combout ; -wire \z80_|execute_|rsel3~combout ; -wire \z80_|execute_|ctl_reg_out_hi~5_combout ; -wire \z80_|execute_|ctl_reg_out_hi~6_combout ; -wire \z80_|execute_|ctl_reg_out_hi~7_combout ; -wire \z80_|execute_|rsel0~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ; -wire \z80_|execute_|ctl_reg_out_lo~6_combout ; -wire \z80_|execute_|ctl_reg_out_lo~7_combout ; -wire \z80_|execute_|ctl_iorw~11_combout ; -wire \z80_|execute_|ctl_sw_2d~10_combout ; -wire \z80_|execute_|ctl_sw_2d~14_combout ; -wire \z80_|execute_|ctl_sw_2d~11_combout ; -wire \z80_|execute_|ctl_sw_2d~12_combout ; -wire \z80_|execute_|ctl_sw_2d~13_combout ; -wire \z80_|execute_|ctl_66_oe~combout ; -wire \z80_|execute_|ctl_inc_cy~34_combout ; -wire \z80_|execute_|ctl_apin_mux~0_combout ; -wire \z80_|execute_|ctl_sw_4u~5_combout ; -wire \z80_|execute_|ctl_inc_cy~75_combout ; -wire \z80_|execute_|ctl_inc_cy~76_combout ; -wire \z80_|pla_decode_|Equal4~0_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~48_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~46_combout ; -wire \z80_|execute_|ctl_inc_cy~53_combout ; -wire \z80_|execute_|ctl_inc_cy~92_combout ; -wire \z80_|pla_decode_|Equal19~1_combout ; -wire \z80_|execute_|ctl_sw_4u~0_combout ; -wire \z80_|execute_|ctl_inc_cy~38_combout ; -wire \z80_|execute_|ctl_inc_cy~93_combout ; -wire \z80_|execute_|ctl_inc_cy~39_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~24_combout ; -wire \z80_|execute_|ctl_reg_gp_we~1_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ; -wire \z80_|execute_|ctl_bus_inc_oe~44_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~5_combout ; -wire \z80_|execute_|ctl_reg_gp_we~0_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ; -wire \z80_|execute_|ctl_sw_4u~2_combout ; -wire \z80_|execute_|ctl_sw_4u~3_combout ; -wire \z80_|execute_|fMRead~3_combout ; -wire \z80_|execute_|ctl_sw_4u~4_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ; -wire \z80_|execute_|ctl_reg_sel_wz~15_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ; -wire \z80_|execute_|ctl_inc_cy~94_combout ; -wire \z80_|execute_|ctl_inc_cy~87_combout ; -wire \z80_|execute_|ctl_inc_cy~42_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~16_combout ; -wire \z80_|execute_|ctl_sw_4u~6_combout ; -wire \z80_|pla_decode_|Equal2~2_combout ; -wire \z80_|pla_decode_|Equal1~6_combout ; -wire \z80_|reg_control_|bank_exx~2_combout ; -wire \z80_|reg_control_|bank_exx~q ; -wire \z80_|reg_control_|bank_hl_de1~0_combout ; -wire \z80_|reg_control_|bank_hl_de1~q ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~10_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~11_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~12_combout ; -wire \z80_|execute_|ctl_mRead~7_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~9_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~37_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~13_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ; -wire \z80_|execute_|fMWrite~3_combout ; -wire \z80_|execute_|ctl_flags_bus~5_combout ; -wire \z80_|execute_|fMRead~2_combout ; -wire \z80_|execute_|ctl_mRead~19_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~7_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~8_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~14_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~16_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~15_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~17_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~19_combout ; -wire \z80_|execute_|ctl_reg_use_sp~2_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~47_combout ; -wire \z80_|execute_|ctl_reg_use_sp~3_combout ; -wire \z80_|execute_|ctl_sw_1d~9_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~21_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~20_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~22_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~18_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~23_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~28_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ; -wire \z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ; -wire \z80_|execute_|ctl_flags_hf_cpl~14_combout ; -wire \z80_|execute_|ctl_flags_hf_cpl~10_combout ; -wire \z80_|execute_|setM1~47_combout ; -wire \z80_|execute_|setM1~48_combout ; -wire \z80_|execute_|ctl_al_we~13_combout ; -wire \z80_|execute_|ctl_flags_oe~0_combout ; -wire \z80_|execute_|ctl_flags_oe~1_combout ; -wire \z80_|execute_|ctl_reg_in_hi~13_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~29_combout ; -wire \z80_|execute_|ctl_inc_cy~40_combout ; -wire \z80_|execute_|ctl_inc_dec~2_combout ; -wire \z80_|execute_|ctl_inc_dec~12_combout ; -wire \z80_|execute_|ctl_inc_cy~43_combout ; -wire \z80_|execute_|ctl_inc_dec~5_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~4_combout ; -wire \z80_|execute_|fMRead~6_combout ; -wire \z80_|execute_|fMRead~7_combout ; -wire \z80_|execute_|fMRead~8_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~26_combout ; -wire \z80_|execute_|ctl_state_alu~13_combout ; -wire \z80_|execute_|ctl_state_alu~10_combout ; -wire \z80_|execute_|ctl_state_alu~11_combout ; -wire \z80_|execute_|ctl_state_alu~9_combout ; -wire \z80_|pla_decode_|Equal62~2_combout ; -wire \z80_|execute_|ctl_flags_pf_we~4_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ; -wire \z80_|pla_decode_|Equal64~0_combout ; -wire \z80_|execute_|ctl_pf_sel[0]~3_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ; -wire \z80_|execute_|ctl_state_alu~15_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~25_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~30_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~31_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~33_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~34_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo~20_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~32_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ; -wire \z80_|reg_control_|reg_sel_de2~5_combout ; -wire \z80_|reg_control_|reg_sel_de2~6_combout ; -wire \z80_|reg_control_|reg_sel_hl~0_combout ; -wire \z80_|reg_control_|bank_hl_de2~0_combout ; -wire \z80_|reg_control_|bank_hl_de2~q ; -wire \z80_|reg_control_|reg_sel_hl2~0_combout ; -wire \z80_|execute_|ctl_reg_in_hi~7_combout ; -wire \z80_|execute_|ctl_reg_gp_we~4_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ; -wire \z80_|execute_|ctl_reg_gp_we~3_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~13_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5~combout ; -wire \z80_|execute_|ctl_reg_gp_we~2_combout ; -wire \z80_|execute_|ctl_reg_gp_we~5_combout ; -wire \z80_|execute_|ctl_reg_gp_we~6_combout ; -wire \z80_|execute_|ctl_al_we~14_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~32_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ; -wire \z80_|execute_|setM1~40_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~93_combout ; -wire \z80_|reg_control_|reg_sel_de~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ; -wire \z80_|execute_|ctl_reg_in_hi~9_combout ; -wire \z80_|execute_|ctl_reg_in_hi~10_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~19_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ; -wire \z80_|execute_|ctl_reg_in_lo~8_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~19_combout ; -wire \z80_|execute_|ctl_reg_use_sp~4_combout ; -wire \z80_|execute_|ctl_reg_use_sp~5_combout ; -wire \z80_|execute_|ctl_reg_use_sp~6_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ; -wire \z80_|pla_decode_|Equal21~2_combout ; -wire \z80_|reg_control_|bank_af~0_combout ; -wire \z80_|reg_control_|bank_af~q ; -wire \z80_|reg_control_|reg_sel_af~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ; -wire \z80_|reg_control_|reg_sel_af2~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ; -wire \z80_|execute_|ctl_reg_sel_wz~12_combout ; -wire \z80_|execute_|ctl_flags_bus~4_combout ; -wire \z80_|execute_|ctl_flags_bus~6_combout ; -wire \z80_|execute_|ctl_flags_bus~7_combout ; -wire \z80_|execute_|fMRead~24_combout ; -wire \z80_|execute_|ctl_flags_bus~13_combout ; -wire \z80_|execute_|ctl_flags_bus~combout ; -wire \z80_|execute_|ctl_inc_dec~3_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~2_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~3_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~6_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~5_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~4_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~7_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~8_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~9_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~10_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~29_combout ; -wire \z80_|execute_|ctl_mRead~13_combout ; -wire \z80_|execute_|pc_inc_hold~49_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~9_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ; -wire \z80_|execute_|pc_inc_hold~28_combout ; -wire \z80_|execute_|setM1~35_combout ; -wire \z80_|execute_|setM1~36_combout ; -wire \z80_|execute_|fMRead~5_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~31_combout ; -wire \z80_|execute_|pc_inc_hold~29_combout ; -wire \z80_|execute_|ctl_reg_sys_we~1_combout ; -wire \z80_|execute_|ctl_reg_sys_we~2_combout ; -wire \z80_|pla_decode_|Equal33~3_combout ; -wire \z80_|execute_|ctl_reg_sys_we~0_combout ; -wire \z80_|execute_|ctl_reg_sys_we~3_combout ; -wire \z80_|execute_|ctl_reg_sys_we_lo~2_combout ; -wire \z80_|execute_|ctl_reg_sys_we_lo~3_combout ; -wire \z80_|execute_|ctl_reg_sys_we_lo~4_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~combout ; -wire \z80_|execute_|ctl_reg_sel_ir~0_combout ; -wire \z80_|execute_|ctl_reg_sel_ir~1_combout ; -wire \z80_|execute_|ctl_reg_out_lo~9_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~36_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ; -wire \z80_|execute_|ctl_reg_in_hi~4_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~4_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ; -wire \z80_|execute_|ctl_reg_sel_wz~5_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~6_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~7_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo~16_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~11_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~12_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~13_combout ; -wire \z80_|execute_|ctl_al_we~4_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~38_combout ; -wire \z80_|execute_|fMRead~0_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ; -wire \z80_|execute_|ctl_inc_dec~4_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~9_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~8_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ; -wire \z80_|execute_|ctl_al_we~5_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~18_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[0]~37_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ; -wire \z80_|execute_|ctl_bus_inc_oe~38_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~39_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~30_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~45_combout ; -wire \z80_|execute_|fMRead~1_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~36_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~27_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~28_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~37_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~40_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~35_combout ; -wire \z80_|execute_|ctl_inc_cy~77_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~32_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~33_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~34_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~41_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~10_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~11_combout ; -wire \z80_|execute_|ctl_sw_4d~3_combout ; -wire \z80_|execute_|ctl_sw_4d~4_combout ; -wire \z80_|execute_|ctl_sw_4d~2_combout ; -wire \z80_|execute_|ctl_sw_4d~5_combout ; -wire \z80_|execute_|setM1~45_combout ; -wire \z80_|execute_|setM1~46_combout ; -wire \z80_|execute_|ctl_sw_4d~1_combout ; -wire \z80_|execute_|ctl_sw_4d~0_combout ; -wire \z80_|execute_|ctl_sw_4d~6_combout ; -wire \z80_|execute_|fMRead~4_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~16_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~14_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~20_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~15_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~17_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~18_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~19_combout ; -wire \z80_|reg_control_|reg_sel_pc~3_combout ; -wire \z80_|reg_control_|reg_sel_pc~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ; -wire \z80_|reg_file_|db_lo_as[0]~2_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ; -wire \z80_|reg_file_|db_lo_as[7]~22_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ; -wire \z80_|reg_file_|db_lo_as[7]~23_combout ; -wire \z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ; -wire \z80_|resets_|SYNTHESIZED_WIRE_10~q ; -wire \z80_|resets_|SYNTHESIZED_WIRE_9~q ; -wire \z80_|resets_|DFFE_intr_ff3~q ; -wire \ula_|pll_|altpll_component|auto_generated|wire_pll1_locked ; -wire \KEY[0]~input_o ; -wire \reset~combout ; -wire \z80_|resets_|x1~0_combout ; -wire \z80_|fpga_reset~feeder_combout ; -wire \z80_|fpga_reset~q ; -wire \z80_|fpga_reset~clkctrl_outclk ; -wire \z80_|resets_|x1~q ; -wire \z80_|resets_|clrpc_int~0_combout ; -wire \z80_|resets_|clrpc_int~q ; -wire \z80_|resets_|clrpc~0_combout ; -wire \z80_|execute_|ctl_apin_mux~1_combout ; -wire \z80_|execute_|ctl_al_we~6_combout ; -wire \z80_|execute_|ctl_al_we~7_combout ; -wire \z80_|execute_|ctl_al_we~8_combout ; -wire \z80_|execute_|ctl_alu_oe~10_combout ; -wire \z80_|execute_|ctl_al_we~9_combout ; -wire \z80_|execute_|ctl_al_we~10_combout ; -wire \z80_|execute_|ctl_al_we~11_combout ; -wire \z80_|execute_|ctl_al_we~12_combout ; -wire \z80_|execute_|ctl_inc_dec~6_combout ; -wire \z80_|execute_|fIOWrite~0_combout ; -wire \z80_|execute_|ctl_inc_dec~8_combout ; -wire \z80_|execute_|ctl_inc_dec~9_combout ; -wire \z80_|execute_|ctl_inc_dec~10_combout ; -wire \z80_|execute_|ctl_inc_dec~7_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~34_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ; -wire \z80_|reg_control_|reg_sel_de2~4_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~33_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~36_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~37_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~39_combout ; -wire \z80_|reg_control_|reg_sel_iy~2_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~38_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ; -wire \z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~35_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~40_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~41_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~42_combout ; -wire \z80_|reg_file_|db_lo_as[2]~7_combout ; -wire \z80_|reg_file_|db_lo_as[2]~8_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~10_combout ; -wire \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~11_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~15_combout ; -wire \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~14_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~16_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~12_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~13_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~17_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~22_combout ; -wire \z80_|reg_file_|db_lo_as[0]~0_combout ; -wire \z80_|reg_file_|db_lo_as[0]~1_combout ; -wire \z80_|execute_|ctl_inc_cy~72_combout ; +wire \z80_|resets_|SYNTHESIZED_WIRE_11~combout ; +wire \z80_|execute_|ctl_ir_we~4_combout ; +wire \z80_|execute_|ctl_state_iy_set~2_combout ; +wire \z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ; +wire \z80_|sequencer_|DFFE_T5_ff~q ; +wire \z80_|execute_|ctl_state_ixiy_we~2_combout ; +wire \z80_|decode_state_|DFFE_instIY1~q ; +wire \z80_|decode_state_|use_ixiy~combout ; +wire \z80_|execute_|ixy_d~4_combout ; +wire \z80_|execute_|ixy_d~11_combout ; +wire \z80_|execute_|ixy_d~9_combout ; +wire \z80_|execute_|ixy_d~7_combout ; +wire \z80_|execute_|ixy_d~6_combout ; +wire \z80_|execute_|ixy_d~8_combout ; +wire \z80_|execute_|ixy_d~12_combout ; +wire \z80_|pla_decode_|Equal33~0_combout ; +wire \z80_|pla_decode_|Equal33~1_combout ; +wire \z80_|pla_decode_|Equal33~2_combout ; +wire \z80_|pla_decode_|Equal21~0_combout ; +wire \z80_|pla_decode_|Equal77~0_combout ; +wire \z80_|pla_decode_|Equal77~1_combout ; +wire \z80_|pla_decode_|Equal1~7_combout ; +wire \z80_|pla_decode_|Equal79~0_combout ; +wire \z80_|interrupts_|iff1~0_combout ; +wire \z80_|interrupts_|DFFE_instIFF2~0_combout ; +wire \z80_|interrupts_|SYNTHESIZED_WIRE_12~combout ; +wire \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl_outclk ; +wire \z80_|interrupts_|DFFE_instIFF2~q ; +wire \z80_|pla_decode_|Equal13~0_combout ; +wire \z80_|pla_decode_|Equal38~2_combout ; +wire \z80_|interrupts_|iff1~1_combout ; +wire \z80_|interrupts_|SYNTHESIZED_WIRE_15~combout ; +wire \z80_|interrupts_|iff1~q ; wire \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ; -wire \ula_|video_|Add0~15 ; -wire \ula_|video_|Add0~16_combout ; -wire \ula_|video_|vga_hc~2_combout ; -wire \ula_|video_|Add0~17 ; -wire \ula_|video_|Add0~18_combout ; -wire \ula_|video_|vga_hc~1_combout ; wire \ula_|video_|Add0~0_combout ; wire \ula_|video_|vga_hc~3_combout ; wire \ula_|video_|Add0~1 ; wire \ula_|video_|Add0~2_combout ; -wire \ula_|video_|vga_hc[1]~feeder_combout ; wire \ula_|video_|Add0~3 ; wire \ula_|video_|Add0~4_combout ; wire \ula_|video_|Add0~5 ; wire \ula_|video_|Add0~6_combout ; -wire \ula_|video_|vga_hc[3]~feeder_combout ; wire \ula_|video_|Add0~7 ; wire \ula_|video_|Add0~8_combout ; -wire \ula_|video_|Equal0~0_combout ; -wire \ula_|video_|Equal0~1_combout ; -wire \ula_|video_|Equal1~0_combout ; wire \ula_|video_|Add0~9 ; wire \ula_|video_|Add0~10_combout ; wire \ula_|video_|vga_hc~0_combout ; @@ -965,10 +246,24 @@ wire \ula_|video_|Add0~11 ; wire \ula_|video_|Add0~12_combout ; wire \ula_|video_|Add0~13 ; wire \ula_|video_|Add0~14_combout ; +wire \ula_|video_|Add0~15 ; +wire \ula_|video_|Add0~16_combout ; +wire \ula_|video_|vga_hc~2_combout ; +wire \ula_|video_|Add0~17 ; +wire \ula_|video_|Add0~18_combout ; +wire \ula_|video_|vga_hc~1_combout ; +wire \ula_|video_|Equal0~0_combout ; +wire \ula_|video_|Equal0~1_combout ; +wire \ula_|video_|Equal1~0_combout ; wire \ula_|video_|Add1~0_combout ; +wire \ula_|video_|vga_vc[0]~0_combout ; +wire \ula_|video_|Add1~1 ; +wire \ula_|video_|Add1~2_combout ; +wire \ula_|video_|vga_vc[1]~1_combout ; wire \ula_|video_|Add1~3 ; wire \ula_|video_|Add1~4_combout ; wire \ula_|video_|vga_vc[2]~2_combout ; +wire \ula_|video_|vga_vc[2]~feeder_combout ; wire \ula_|video_|Add1~5 ; wire \ula_|video_|Add1~6_combout ; wire \ula_|video_|vga_vc[3]~3_combout ; @@ -976,8 +271,6 @@ wire \ula_|video_|Add1~7 ; wire \ula_|video_|Add1~8_combout ; wire \ula_|video_|vga_vc[4]~5_combout ; wire \ula_|video_|Add1~9 ; -wire \ula_|video_|Add1~10_combout ; -wire \ula_|video_|vga_vc[5]~8_combout ; wire \ula_|video_|Add1~11 ; wire \ula_|video_|Add1~12_combout ; wire \ula_|video_|vga_vc[6]~4_combout ; @@ -990,359 +283,1298 @@ wire \ula_|video_|vga_vc[8]~7_combout ; wire \ula_|video_|Add1~17 ; wire \ula_|video_|Add1~18_combout ; wire \ula_|video_|vga_vc[9]~9_combout ; -wire \ula_|video_|Equal2~0_combout ; wire \ula_|video_|Equal3~0_combout ; +wire \ula_|video_|Equal2~0_combout ; wire \ula_|video_|Equal3~1_combout ; -wire \ula_|video_|vga_vc[0]~0_combout ; -wire \ula_|video_|Add1~1 ; -wire \ula_|video_|Add1~2_combout ; -wire \ula_|video_|vga_vc[1]~1_combout ; -wire \SW[1]~input_o ; -wire \z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout ; -wire \z80_|pla_decode_|Equal79~0_combout ; -wire \z80_|interrupts_|DFFE_instIFF2~0_combout ; -wire \z80_|interrupts_|SYNTHESIZED_WIRE_12~combout ; -wire \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl_outclk ; -wire \z80_|interrupts_|DFFE_instIFF2~q ; -wire \z80_|interrupts_|iff1~0_combout ; -wire \z80_|interrupts_|iff1~1_combout ; -wire \z80_|interrupts_|SYNTHESIZED_WIRE_15~combout ; -wire \z80_|interrupts_|iff1~q ; +wire \ula_|video_|Add1~10_combout ; +wire \ula_|video_|vga_vc[5]~8_combout ; wire \ula_|video_|Equal2~1_combout ; wire \ula_|video_|Equal2~2_combout ; +wire \SW[1]~input_o ; +wire \z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout ; wire \z80_|interrupts_|SYNTHESIZED_WIRE_13~combout ; wire \z80_|interrupts_|int_armed~q ; +wire \z80_|interrupts_|DFFE_inst44~feeder_combout ; wire \z80_|interrupts_|DFFE_inst44~q ; -wire \z80_|execute_|pc_inc_hold~38_combout ; -wire \z80_|execute_|ctl_inc_cy~91_combout ; -wire \z80_|execute_|pc_inc_hold~45_combout ; -wire \z80_|execute_|pc_inc_hold~44_combout ; -wire \z80_|execute_|pc_inc_hold~46_combout ; -wire \z80_|execute_|pc_inc_hold~37_combout ; -wire \z80_|execute_|pc_inc_hold~50_combout ; -wire \z80_|execute_|pc_inc_hold~33_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ; -wire \z80_|execute_|pc_inc_hold~31_combout ; -wire \z80_|execute_|pc_inc_hold~32_combout ; -wire \z80_|execute_|pc_inc_hold~34_combout ; -wire \z80_|execute_|pc_inc_hold~51_combout ; -wire \z80_|execute_|pc_inc_hold~30_combout ; -wire \z80_|execute_|pc_inc_hold~52_combout ; -wire \z80_|execute_|pc_inc_hold~35_combout ; -wire \z80_|execute_|pc_inc_hold~36_combout ; -wire \z80_|execute_|ctl_inc_cy~44_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ; -wire \z80_|execute_|ctl_inc_cy~45_combout ; -wire \z80_|execute_|pc_inc_hold~43_combout ; -wire \z80_|execute_|ctl_inc_cy~71_combout ; -wire \z80_|execute_|ctl_inc_cy~73_combout ; -wire \z80_|execute_|ctl_inc_cy~46_combout ; -wire \z80_|execute_|pc_inc_hold~53_combout ; -wire \z80_|execute_|pc_inc_hold~39_combout ; -wire \z80_|execute_|pc_inc_hold~47_combout ; -wire \z80_|execute_|ctl_inc_cy~74_combout ; +wire \z80_|decode_state_|in_halt~0_combout ; +wire \z80_|decode_state_|in_halt~1_combout ; +wire \z80_|decode_state_|in_halt~q ; +wire \z80_|pla_decode_|Equal50~0_combout ; +wire \z80_|execute_|ixy_d~17_combout ; +wire \z80_|pla_decode_|Equal44~0_combout ; +wire \z80_|execute_|ixy_d~16_combout ; +wire \z80_|pla_decode_|Equal3~1_combout ; +wire \z80_|execute_|ixy_d~10_combout ; +wire \z80_|execute_|ixy_d~13_combout ; +wire \z80_|execute_|ixy_d~14_combout ; +wire \z80_|pla_decode_|Equal49~0_combout ; +wire \z80_|execute_|ixy_d~15_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ; +wire \z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout ; +wire \z80_|decode_state_|DFFE_inst4~q ; +wire \z80_|execute_|ctl_ir_we~5_combout ; +wire \z80_|execute_|ctl_ir_we~13_combout ; +wire \z80_|pla_decode_|Equal8~0_combout ; +wire \z80_|execute_|ctl_mRead~6_combout ; +wire \z80_|pla_decode_|Equal9~0_combout ; +wire \z80_|pla_decode_|Equal9~1_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ; +wire \z80_|pla_decode_|Equal13~1_combout ; +wire \z80_|pla_decode_|Equal69~0_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ; +wire \z80_|execute_|ctl_alu_op_low~27_combout ; +wire \z80_|execute_|ctl_reg_out_lo~2_combout ; +wire \z80_|execute_|rsel3~combout ; +wire \z80_|execute_|ctl_ir_we~12_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ; +wire \z80_|pla_decode_|Equal56~0_combout ; +wire \z80_|execute_|ctl_alu_op_low~24_combout ; +wire \z80_|execute_|ctl_alu_op_low~25_combout ; +wire \z80_|execute_|nextM~2_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~16_combout ; +wire \z80_|execute_|ctl_reg_out_lo~3_combout ; +wire \z80_|pla_decode_|Equal40~0_combout ; +wire \z80_|pla_decode_|Equal40~1_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ; +wire \z80_|pla_decode_|Equal3~0_combout ; +wire \z80_|pla_decode_|Equal39~0_combout ; +wire \z80_|execute_|ctl_reg_out_lo~4_combout ; +wire \z80_|execute_|ctl_alu_oe~0_combout ; +wire \z80_|execute_|comb~0_combout ; +wire \z80_|pla_decode_|Equal41~0_combout ; +wire \z80_|pla_decode_|Equal47~0_combout ; +wire \z80_|execute_|ctl_inc_cy~32_combout ; +wire \z80_|pla_decode_|Equal19~0_combout ; +wire \z80_|execute_|ctl_reg_out_lo~9_combout ; +wire \z80_|execute_|ctl_reg_out_lo~5_combout ; +wire \z80_|execute_|ctl_mWrite~4_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ; +wire \z80_|execute_|ctl_mRead~34_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ; +wire \z80_|execute_|ctl_mWrite~5_combout ; +wire \z80_|execute_|nextM~11_combout ; +wire \z80_|pla_decode_|Equal20~0_combout ; +wire \z80_|pla_decode_|Equal13~2_combout ; +wire \z80_|execute_|ctl_mRead~24_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~27_combout ; +wire \z80_|pla_decode_|Equal48~0_combout ; +wire \z80_|pla_decode_|Equal10~0_combout ; +wire \z80_|pla_decode_|Equal11~0_combout ; +wire \z80_|pla_decode_|Equal63~0_combout ; +wire \z80_|execute_|ctl_flags_hf2_we~combout ; +wire \z80_|execute_|ctl_alu_shift_oe~41_combout ; +wire \z80_|pla_decode_|Equal68~3_combout ; +wire \z80_|execute_|ctl_flags_bus~7_combout ; +wire \z80_|execute_|ctl_flags_bus~8_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~9_combout ; +wire \z80_|execute_|ctl_ir_we~6_combout ; +wire \z80_|execute_|ctl_ir_we~8_combout ; +wire \z80_|execute_|ctl_ir_we~14_combout ; +wire \z80_|execute_|ctl_flags_bus~4_combout ; +wire \z80_|execute_|ctl_flags_bus~5_combout ; +wire \z80_|execute_|ctl_mRead~4_combout ; +wire \z80_|execute_|ctl_flags_bus~6_combout ; +wire \z80_|execute_|ctl_flags_bus~9_combout ; +wire \z80_|execute_|ctl_iorw~11_combout ; +wire \z80_|execute_|ctl_mWrite~17_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~18_combout ; +wire \z80_|pla_decode_|Equal37~0_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~19_combout ; +wire \z80_|pla_decode_|Equal35~0_combout ; +wire \z80_|pla_decode_|Equal21~1_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~17_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~20_combout ; +wire \z80_|execute_|ctl_ir_we~9_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~11_combout ; +wire \z80_|execute_|ctl_ir_we~15_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~7_combout ; +wire \z80_|execute_|ctl_ir_we~7_combout ; +wire \z80_|pla_decode_|Equal46~0_combout ; +wire \z80_|execute_|ctl_ir_we~11_combout ; +wire \z80_|execute_|ctl_bus_db_oe~3_combout ; +wire \z80_|pla_decode_|Equal52~1_combout ; +wire \z80_|execute_|ctl_flags_xy_we~21_combout ; +wire \z80_|execute_|ctl_flags_xy_we~13_combout ; +wire \z80_|execute_|ctl_state_alu~6_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~14_combout ; +wire \z80_|execute_|ctl_flags_xy_we~14_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~24_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ; +wire \z80_|execute_|ctl_reg_gp_sel~7_combout ; +wire \z80_|execute_|rsel0~combout ; +wire \z80_|execute_|ctl_state_alu~3_combout ; +wire \z80_|execute_|ctl_reg_use_sp~0_combout ; +wire \z80_|execute_|ctl_state_alu~2_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ; +wire \z80_|execute_|ctl_reg_out_lo~6_combout ; +wire \z80_|execute_|ctl_state_alu~5_combout ; +wire \z80_|execute_|ctl_sw_2u~1_combout ; +wire \z80_|execute_|ctl_alu_oe~1_combout ; +wire \z80_|execute_|ctl_mWrite~7_combout ; +wire \z80_|execute_|ctl_sw_2u~4_combout ; +wire \z80_|execute_|setM1~57_combout ; +wire \z80_|execute_|ctl_sw_2u~5_combout ; +wire \z80_|execute_|ctl_reg_out_lo~7_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~0_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~41_combout ; +wire \z80_|execute_|ctl_inc_cy~86_combout ; +wire \z80_|execute_|ctl_inc_cy~88_combout ; +wire \z80_|execute_|ctl_inc_cy~36_combout ; +wire \z80_|execute_|ctl_inc_cy~87_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~26_combout ; +wire \z80_|execute_|ctl_mWrite~9_combout ; +wire \z80_|execute_|ctl_reg_sys_we~1_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~42_combout ; +wire \z80_|pla_decode_|Equal40~2_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~14_combout ; +wire \z80_|pla_decode_|Equal55~0_combout ; +wire \z80_|execute_|ctl_mRead~11_combout ; +wire \z80_|pla_decode_|Equal6~1_combout ; +wire \z80_|execute_|setM1~36_combout ; +wire \z80_|execute_|comb~1_combout ; +wire \z80_|execute_|ctl_mRead~13_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~11_combout ; +wire \z80_|pla_decode_|Equal24~0_combout ; +wire \z80_|execute_|pc_inc_hold~26_combout ; +wire \z80_|execute_|setM1~37_combout ; +wire \z80_|execute_|pc_inc_hold~6_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo~38_combout ; +wire \z80_|execute_|fMRead~7_combout ; +wire \z80_|execute_|ctl_mRead~12_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~31_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ; +wire \z80_|nM1_int~2_combout ; +wire \z80_|execute_|ctl_sw_4u~0_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ; +wire \z80_|execute_|fMRead~6_combout ; +wire \z80_|execute_|ctl_inc_dec~12_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ; +wire \z80_|pla_decode_|Equal25~0_combout ; +wire \z80_|pla_decode_|Equal12~1_combout ; +wire \z80_|execute_|ctl_inc_cy~38_combout ; +wire \z80_|execute_|ctl_inc_cy~82_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~16_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~32_combout ; +wire \z80_|execute_|ctl_inc_cy~77_combout ; +wire \z80_|pla_decode_|Equal29~0_combout ; wire \z80_|execute_|ctl_inc_cy~78_combout ; wire \z80_|execute_|ctl_inc_cy~79_combout ; -wire \z80_|execute_|ctl_inc_cy~80_combout ; -wire \z80_|execute_|ctl_inc_cy~81_combout ; -wire \z80_|execute_|ctl_inc_cy~82_combout ; -wire \z80_|execute_|ctl_inc_cy~83_combout ; -wire \z80_|execute_|ctl_inc_cy~84_combout ; -wire \z80_|execute_|pc_inc_hold~42_combout ; -wire \z80_|execute_|ctl_inc_cy~90_combout ; -wire \z80_|execute_|pc_inc_hold~41_combout ; -wire \z80_|execute_|ctl_inc_cy~66_combout ; -wire \z80_|execute_|ctl_inc_cy~67_combout ; -wire \z80_|execute_|ctl_inc_cy~68_combout ; -wire \z80_|execute_|ctl_inc_cy~64_combout ; -wire \z80_|execute_|ctl_inc_cy~63_combout ; -wire \z80_|execute_|ctl_inc_cy~65_combout ; -wire \z80_|execute_|ctl_inc_cy~69_combout ; +wire \z80_|execute_|ctl_mRead~14_combout ; wire \z80_|execute_|ctl_inc_cy~49_combout ; -wire \z80_|execute_|ctl_inc_cy~50_combout ; -wire \z80_|execute_|ctl_inc_cy~51_combout ; -wire \z80_|execute_|ctl_inc_cy~52_combout ; -wire \z80_|execute_|ctl_inc_cy~36_combout ; -wire \z80_|execute_|ctl_inc_cy~37_combout ; -wire \z80_|execute_|ctl_inc_cy~54_combout ; -wire \z80_|execute_|ctl_inc_cy~41_combout ; -wire \z80_|execute_|ctl_inc_cy~58_combout ; -wire \z80_|execute_|ctl_inc_cy~55_combout ; -wire \z80_|execute_|ctl_inc_cy~56_combout ; -wire \z80_|execute_|ctl_inc_cy~89_combout ; -wire \z80_|execute_|ctl_inc_cy~57_combout ; -wire \z80_|execute_|ctl_inc_cy~59_combout ; -wire \z80_|execute_|ctl_inc_cy~60_combout ; -wire \z80_|execute_|ctl_inc_cy~47_combout ; -wire \z80_|execute_|ctl_inc_cy~88_combout ; -wire \z80_|execute_|ctl_inc_cy~48_combout ; -wire \z80_|execute_|pc_inc_hold~40_combout ; -wire \z80_|execute_|ctl_inc_cy~61_combout ; -wire \z80_|execute_|ctl_inc_cy~62_combout ; -wire \z80_|execute_|ctl_inc_cy~70_combout ; -wire \z80_|execute_|ctl_inc_cy~85_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ; -wire \z80_|reg_file_|db_lo_as[0]~3_combout ; -wire \z80_|address_latch_|Q[0]~feeder_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ; -wire \z80_|reg_file_|db_lo_as[1]~4_combout ; -wire \z80_|reg_file_|db_lo_as[1]~5_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ; -wire \z80_|reg_file_|db_lo_as[1]~6_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ; -wire \z80_|reg_file_|db_lo_as[2]~9_combout ; -wire \z80_|address_latch_|Q[2]~feeder_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ; -wire \z80_|execute_|ctl_inc_cy~86_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ; -wire \z80_|execute_|ctl_inc_dec~11_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~45_combout ; -wire \z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~48_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~49_combout ; -wire \z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~5_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~40_combout ; +wire \z80_|execute_|ctl_mRead~5_combout ; wire \z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~40_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~41_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[3]~18_combout ; -wire \z80_|execute_|ctl_reg_in_hi~11_combout ; -wire \z80_|execute_|ctl_reg_in_hi~12_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~44_combout ; -wire \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~43_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ; -wire \z80_|reg_control_|reg_sys_we_hi~0_combout ; -wire \z80_|reg_control_|reg_sys_we_hi~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~45_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~42_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~46_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~47_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~17_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~18_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~19_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~16_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~20_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~8_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[1]~15_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~13_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~12_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~10_combout ; -wire \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~11_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~14_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~9_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~15_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~21_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ; -wire \z80_|reg_control_|reg_sw_4d_hi~0_combout ; -wire \z80_|reg_file_|db_hi_as[1]~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ; -wire \z80_|reg_file_|db_hi_as[1]~1_combout ; -wire \z80_|reg_file_|db_hi_as[0]~2_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~23_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~22_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~24_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~26_combout ; -wire \z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~25_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~27_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~28_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[0]~16_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~29_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~30_combout ; -wire \z80_|reg_file_|db_hi_as[0]~4_combout ; -wire \z80_|reg_file_|db_hi_as[0]~5_combout ; -wire \z80_|reg_file_|db_hi_as[0]~6_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ; -wire \z80_|reg_file_|db_hi_as[1]~3_combout ; -wire \z80_|address_latch_|Q[9]~feeder_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~32_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~35_combout ; -wire \z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~34_combout ; -wire \z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~33_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~36_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~37_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~31_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[2]~17_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~38_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~39_combout ; -wire \z80_|reg_file_|db_hi_as[2]~7_combout ; -wire \z80_|reg_file_|db_hi_as[2]~8_combout ; -wire \z80_|reg_file_|db_hi_as[2]~9_combout ; -wire \z80_|address_latch_|Q[10]~feeder_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ; -wire \z80_|reg_file_|db_hi_as[3]~10_combout ; -wire \z80_|reg_file_|db_hi_as[3]~11_combout ; -wire \z80_|reg_file_|db_hi_as[3]~12_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~48_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_low~combout ; -wire \z80_|alu_|alu_op1[3]~3_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~6_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~10_combout ; -wire \z80_|execute_|ctl_alu_core_R~0_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~5_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~7_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~8_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|ena~combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~6_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~20_combout ; -wire \z80_|execute_|ctl_state_alu~12_combout ; -wire \z80_|execute_|ctl_alu_core_hf~18_combout ; -wire \z80_|pla_decode_|Equal61~2_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~16_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~17_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~21_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~15_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~12_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~22_combout ; -wire \z80_|execute_|ctl_alu_core_hf~20_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~36_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~35_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~46_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~33_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~47_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ; +wire \z80_|execute_|ctl_bus_inc_oe~45_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~34_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ; +wire \z80_|execute_|ctl_mWrite~6_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~50_combout ; +wire \z80_|pla_decode_|Equal4~0_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~48_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~49_combout ; +wire \z80_|execute_|ctl_mRead~7_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~29_combout ; +wire \z80_|execute_|ctl_alu_core_S~11_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~27_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~44_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~28_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~30_combout ; +wire \z80_|execute_|ctl_mRead~3_combout ; +wire \z80_|execute_|fMRead~3_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~37_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~38_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~39_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~43_combout ; +wire \z80_|execute_|ctl_alu_oe~3_combout ; +wire \z80_|execute_|fMWrite~1_combout ; +wire \z80_|execute_|ctl_flags_bus~1_combout ; +wire \z80_|execute_|fMRead~5_combout ; +wire \z80_|execute_|ctl_mRead~17_combout ; +wire \z80_|execute_|ctl_iorw~10_combout ; +wire \z80_|execute_|setM1~47_combout ; +wire \z80_|execute_|ctl_mWrite~8_combout ; +wire \z80_|execute_|ctl_al_we~13_combout ; +wire \z80_|execute_|setM1~48_combout ; +wire \z80_|execute_|ctl_sw_4d~0_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ; +wire \z80_|execute_|ctl_mRead~9_combout ; +wire \z80_|execute_|ctl_flags_sz_we~3_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ; +wire \z80_|execute_|ctl_flags_alu~9_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~2_combout ; +wire \z80_|execute_|ctl_flags_alu~10_combout ; +wire \z80_|execute_|ctl_flags_xy_we~10_combout ; +wire \z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ; +wire \z80_|execute_|ctl_flags_xy_we~11_combout ; +wire \z80_|execute_|ctl_flags_alu~11_combout ; +wire \z80_|execute_|ctl_reg_use_sp~1_combout ; +wire \z80_|execute_|ctl_state_alu~4_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~9_combout ; +wire \z80_|execute_|ctl_sw_2d~4_combout ; +wire \z80_|execute_|ctl_flags_sz_we~0_combout ; wire \z80_|execute_|ctl_flags_sz_we~4_combout ; -wire \z80_|pla_decode_|Equal71~2_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ; +wire \z80_|execute_|ctl_alu_op_low~47_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~3_combout ; +wire \z80_|execute_|ctl_flags_alu~12_combout ; +wire \z80_|execute_|ctl_alu_op_low~23_combout ; +wire \z80_|execute_|ctl_flags_xy_we~19_combout ; +wire \z80_|execute_|ctl_flags_alu~13_combout ; +wire \z80_|execute_|ctl_reg_out_hi~4_combout ; +wire \z80_|execute_|ctl_sw_4u~1_combout ; +wire \z80_|execute_|ctl_alu_op_low~29_combout ; +wire \z80_|execute_|ctl_flags_alu~14_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ; +wire \z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ; +wire \z80_|execute_|ctl_flags_use_cf2~13_combout ; +wire \z80_|execute_|ctl_flags_cf_we~7_combout ; +wire \z80_|execute_|ctl_pf_sel[0]~2_combout ; +wire \z80_|execute_|ctl_flags_hf_we~5_combout ; +wire \z80_|execute_|ctl_flags_pf_we~10_combout ; +wire \z80_|pla_decode_|Equal68~2_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~13_combout ; +wire \z80_|execute_|ctl_flags_pf_we~2_combout ; +wire \z80_|execute_|ctl_alu_oe~4_combout ; +wire \z80_|execute_|ctl_flags_xy_we~8_combout ; +wire \z80_|execute_|ctl_flags_xy_we~20_combout ; +wire \z80_|execute_|ctl_flags_xy_we~9_combout ; +wire \z80_|execute_|ctl_flags_sz_we~1_combout ; +wire \z80_|execute_|ctl_bus_db_oe~1_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~10_combout ; +wire \z80_|execute_|ctl_flags_sz_we~2_combout ; +wire \z80_|execute_|ctl_flags_alu~17_combout ; +wire \z80_|execute_|ctl_flags_alu~18_combout ; +wire \z80_|execute_|ctl_flags_alu~6_combout ; +wire \z80_|execute_|ctl_flags_alu~19_combout ; +wire \z80_|pla_decode_|Equal1~5_combout ; +wire \z80_|execute_|ctl_alu_core_R~0_combout ; +wire \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ; +wire \z80_|execute_|ctl_alu_core_R~1_combout ; +wire \z80_|execute_|ctl_flags_alu~7_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~5_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~8_combout ; +wire \z80_|execute_|ctl_flags_alu~8_combout ; +wire \z80_|execute_|ctl_flags_alu~15_combout ; +wire \z80_|execute_|ctl_state_alu~7_combout ; +wire \z80_|execute_|ctl_state_alu~12_combout ; +wire \z80_|execute_|ctl_state_alu~9_combout ; +wire \z80_|execute_|ctl_state_alu~10_combout ; +wire \z80_|execute_|ctl_state_alu~8_combout ; +wire \z80_|pla_decode_|Equal64~0_combout ; +wire \z80_|execute_|ctl_pf_sel[0]~3_combout ; +wire \z80_|pla_decode_|Equal62~2_combout ; +wire \z80_|execute_|ctl_flags_pf_we~4_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~46_combout ; +wire \z80_|execute_|ctl_flags_pf_we~6_combout ; +wire \z80_|execute_|ctl_flags_pf_we~7_combout ; +wire \z80_|execute_|ctl_state_alu~11_combout ; +wire \z80_|pla_decode_|Equal62~3_combout ; +wire \z80_|execute_|ctl_flags_pf_we~5_combout ; +wire \z80_|execute_|ctl_flags_pf_we~3_combout ; +wire \z80_|execute_|ctl_flags_pf_we~8_combout ; +wire \z80_|execute_|ctl_flags_pf_we~9_combout ; +wire \z80_|execute_|ctl_alu_core_S~6_combout ; +wire \z80_|execute_|ctl_alu_core_S~7_combout ; +wire \z80_|execute_|ctl_alu_res_oe~1_combout ; +wire \z80_|execute_|ctl_alu_res_oe~0_combout ; +wire \z80_|execute_|ctl_alu_core_S~4_combout ; +wire \z80_|execute_|ctl_alu_core_S~5_combout ; +wire \z80_|execute_|ctl_alu_res_oe~2_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ; +wire \z80_|reg_control_|reg_sys_we_lo~6_combout ; +wire \z80_|execute_|ctl_flags_xy_we~12_combout ; +wire \z80_|execute_|ctl_flags_cf_we~2_combout ; +wire \z80_|execute_|ctl_alu_res_oe~3_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_high~combout ; +wire \z80_|execute_|ctl_alu_op1_sel_zero~4_combout ; +wire \z80_|execute_|ctl_alu_core_hf~12_combout ; +wire \z80_|pla_decode_|Equal61~2_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~4_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~13_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~14_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~18_combout ; +wire \z80_|execute_|ctl_flags_bus~10_combout ; +wire \z80_|execute_|ctl_flags_bus~2_combout ; +wire \z80_|execute_|ctl_flags_bus~0_combout ; +wire \z80_|execute_|ctl_flags_bus~3_combout ; +wire \z80_|execute_|fMRead~26_combout ; +wire \z80_|execute_|ctl_flags_bus~combout ; +wire \z80_|execute_|ctl_reg_in_lo~9_combout ; +wire \z80_|execute_|ctl_alu_op1_oe~0_combout ; +wire \z80_|execute_|ctl_alu_op1_oe~1_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~6_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~12_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~8_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~9_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~combout ; +wire \z80_|execute_|ctl_alu_op2_oe~0_combout ; +wire \z80_|alu_|db_high[3]~0_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla83M1T3_2~combout ; +wire \z80_|execute_|ctl_alu_shift_oe~15_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~38_combout ; +wire \z80_|execute_|ctl_alu_op_low~28_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~6_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~37_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~39_combout ; +wire \z80_|execute_|ctl_flags_cf2_sel_daa~combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~7_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~8_combout ; +wire \z80_|execute_|ctl_alu_op_low~30_combout ; wire \z80_|execute_|ctl_alu_op_low~31_combout ; +wire \z80_|execute_|ctl_mRead~25_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~40_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~42_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~4_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~47_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~34_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~35_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~36_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~28_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~44_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~29_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~16_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~27_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~10_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~31_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~30_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~32_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~33_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~21_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~45_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~22_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~23_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~24_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~25_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~26_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~43_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_low~combout ; +wire \z80_|execute_|ctl_alu_op1_sel_zero~5_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_zero~combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~13_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~17_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~14_combout ; +wire \z80_|execute_|ctl_alu_core_R~3_combout ; +wire \z80_|execute_|ctl_alu_core_R~4_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~9_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~10_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~11_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~12_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~15_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~6_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|ena~combout ; +wire \z80_|alu_|db_low[3]~15_combout ; +wire \z80_|alu_|db_low[3]~16_combout ; +wire \z80_|execute_|ctl_alu_op_low~33_combout ; +wire \z80_|execute_|ctl_alu_op_low~34_combout ; +wire \z80_|execute_|ctl_alu_op_low~48_combout ; +wire \z80_|execute_|ctl_alu_op_low~35_combout ; +wire \z80_|execute_|ctl_alu_op_low~36_combout ; +wire \z80_|execute_|ctl_alu_op_low~37_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ; +wire \z80_|execute_|ctl_alu_op_low~38_combout ; +wire \z80_|execute_|ctl_alu_op_low~39_combout ; +wire \z80_|execute_|ctl_alu_op_low~40_combout ; +wire \z80_|execute_|ctl_alu_op_low~41_combout ; +wire \z80_|execute_|ctl_alu_op_low~combout ; +wire \z80_|execute_|ctl_alu_oe~5_combout ; +wire \z80_|execute_|ctl_alu_oe~6_combout ; +wire \z80_|execute_|ctl_alu_oe~9_combout ; +wire \z80_|execute_|ctl_alu_core_S~12_combout ; +wire \z80_|execute_|ctl_alu_oe~10_combout ; +wire \z80_|execute_|ctl_alu_oe~2_combout ; +wire \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~15_combout ; +wire \z80_|execute_|ctl_reg_in_hi~8_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~7_combout ; +wire \z80_|execute_|ctl_alu_oe~7_combout ; +wire \z80_|execute_|ctl_mWrite~11_combout ; +wire \z80_|execute_|ctl_bus_db_we~5_combout ; +wire \z80_|execute_|ctl_alu_oe~8_combout ; +wire \z80_|execute_|ctl_flags_alu~16_combout ; +wire \z80_|execute_|ctl_alu_oe~11_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ; +wire \z80_|execute_|ctl_reg_out_hi~8_combout ; +wire \z80_|execute_|ctl_reg_out_hi~5_combout ; +wire \z80_|execute_|ctl_sw_2u~2_combout ; +wire \z80_|execute_|ctl_sw_2u~0_combout ; +wire \z80_|execute_|ctl_sw_2u~3_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ; +wire \z80_|execute_|ctl_inc_cy~33_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~37_combout ; +wire \z80_|execute_|ctl_sw_2u~6_combout ; +wire \z80_|execute_|ctl_reg_out_hi~6_combout ; +wire \z80_|execute_|ctl_reg_out_hi~7_combout ; +wire \z80_|execute_|ctl_mRead~2_combout ; +wire \z80_|execute_|ctl_sw_2d~6_combout ; +wire \z80_|execute_|ctl_sw_2d~7_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ; +wire \z80_|execute_|ctl_sw_2d~8_combout ; +wire \z80_|execute_|ctl_bus_db_oe~7_combout ; +wire \z80_|execute_|ctl_sw_2d~5_combout ; +wire \z80_|execute_|ctl_mRead~19_combout ; +wire \z80_|execute_|ctl_mRead~18_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~2_combout ; +wire \z80_|pla_decode_|Equal24~1_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~3_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~4_combout ; +wire \z80_|execute_|ctl_mRead~20_combout ; +wire \z80_|execute_|ctl_reg_in_hi~5_combout ; +wire \z80_|execute_|ctl_mRead~22_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ; +wire \z80_|execute_|ctl_reg_in_hi~6_combout ; +wire \z80_|execute_|ctl_reg_in_hi~2_combout ; +wire \z80_|execute_|setM1~30_combout ; +wire \z80_|execute_|ctl_mRead~23_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~6_combout ; +wire \z80_|execute_|ctl_reg_in_hi~3_combout ; +wire \z80_|execute_|ctl_mWrite~10_combout ; +wire \z80_|execute_|fMRead~18_combout ; +wire \z80_|reg_control_|reg_sel_pc~0_combout ; +wire \z80_|reg_control_|reg_sel_pc~1_combout ; +wire \z80_|reg_control_|reg_sel_pc~2_combout ; +wire \z80_|execute_|fMRead~19_combout ; +wire \z80_|execute_|fMRead~20_combout ; +wire \z80_|execute_|fMRead~21_combout ; +wire \z80_|execute_|ctl_sw_2d~9_combout ; +wire \z80_|execute_|ctl_sw_2d~14_combout ; +wire \z80_|execute_|ctl_sw_1d~8_combout ; +wire \z80_|execute_|ctl_sw_2d~10_combout ; +wire \z80_|execute_|ctl_sw_2d~11_combout ; +wire \z80_|execute_|ctl_sw_2d~12_combout ; +wire \z80_|execute_|ctl_sw_2d~13_combout ; +wire \z80_|alu_|db[7]~9_combout ; +wire \z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ; +wire \z80_|execute_|ctl_alu_op_low~32_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~2_combout ; +wire \z80_|execute_|ctl_flags_xy_we~22_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~3_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ; wire \z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ; +wire \z80_|execute_|ctl_alu_core_hf~15_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ; -wire \z80_|pla_decode_|Equal72~2_combout ; -wire \z80_|pla_decode_|Equal73~2_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~7_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~17_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ; +wire \z80_|execute_|ctl_flags_nf_we~3_combout ; wire \z80_|execute_|ctl_flags_nf_we~0_combout ; +wire \z80_|pla_decode_|Equal73~2_combout ; +wire \z80_|pla_decode_|Equal72~2_combout ; wire \z80_|execute_|ctl_flags_nf_we~1_combout ; wire \z80_|execute_|ctl_flags_nf_we~2_combout ; -wire \z80_|execute_|ctl_flags_nf_we~3_combout ; wire \z80_|execute_|ctl_flags_sz_we~5_combout ; wire \z80_|execute_|ctl_flags_sz_we~6_combout ; wire \z80_|execute_|ctl_flags_nf_we~4_combout ; -wire \z80_|execute_|setM1~15_combout ; -wire \z80_|execute_|setM1~16_combout ; -wire \z80_|execute_|ctl_flags_xy_we~6_combout ; -wire \z80_|execute_|ctl_flags_xy_we~7_combout ; -wire \z80_|execute_|ctl_flags_sz_we~2_combout ; -wire \z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ; -wire \z80_|execute_|ctl_alu_core_R~1_combout ; -wire \z80_|execute_|ctl_flags_alu~7_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~8_combout ; -wire \z80_|execute_|ctl_flags_alu~8_combout ; -wire \z80_|execute_|ctl_flags_xy_we~16_combout ; -wire \z80_|execute_|ctl_flags_alu~12_combout ; -wire \z80_|execute_|ctl_flags_alu~13_combout ; -wire \z80_|execute_|ctl_flags_alu~14_combout ; -wire \z80_|execute_|ctl_flags_alu~15_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~19_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~7_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~9_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~10_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_nf~q ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~7_combout ; -wire \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ; +wire \z80_|execute_|ctl_flags_hf_cpl~14_combout ; +wire \z80_|execute_|ctl_flags_hf_cpl~10_combout ; +wire \z80_|pla_decode_|Equal45~0_combout ; +wire \z80_|execute_|ctl_flags_hf_cpl~11_combout ; +wire \z80_|execute_|ctl_flags_hf_cpl~12_combout ; +wire \z80_|execute_|ctl_flags_hf_cpl~13_combout ; +wire \z80_|execute_|ctl_alu_core_S~8_combout ; +wire \z80_|execute_|ctl_alu_core_S~9_combout ; +wire \z80_|execute_|ctl_alu_core_S~10_combout ; +wire \z80_|execute_|ctl_alu_core_S~combout ; +wire \z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ; +wire \z80_|alu_|alu_op1[3]~2_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ; +wire \z80_|execute_|ctl_reg_sys_we_lo~2_combout ; +wire \z80_|execute_|ctl_reg_sys_we_lo~3_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~14_combout ; +wire \z80_|reg_control_|reg_sys_we_hi~0_combout ; +wire \z80_|pla_decode_|Equal33~3_combout ; +wire \z80_|execute_|ctl_reg_sys_we~0_combout ; +wire \z80_|execute_|ctl_reg_sys_we~2_combout ; +wire \z80_|execute_|ctl_reg_sys_we~3_combout ; +wire \z80_|execute_|ctl_reg_in_hi~4_combout ; +wire \z80_|reg_control_|reg_sys_we_hi~combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo~17_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~11_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~12_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~13_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ; +wire \z80_|execute_|ctl_reg_sel_wz~6_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~7_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~9_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~8_combout ; +wire \z80_|execute_|ctl_al_we~5_combout ; +wire \z80_|execute_|ctl_al_we~4_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~41_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~10_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo~21_combout ; +wire \z80_|execute_|ctl_inc_dec~3_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ; +wire \z80_|execute_|fMRead~2_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~20_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~29_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~13_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ; +wire \z80_|execute_|ctl_reg_sel_ir~0_combout ; +wire \z80_|execute_|ctl_reg_sel_ir~1_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ; +wire \z80_|execute_|ctl_reg_sys_we_lo~4_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~combout ; +wire \z80_|reg_control_|reg_sw_4d_hi~0_combout ; +wire \z80_|reg_file_|db_hi_as[3]~10_combout ; +wire \z80_|reg_file_|db_hi_as[3]~11_combout ; +wire \z80_|execute_|ctl_apin_mux~1_combout ; +wire \z80_|execute_|ctl_inc_cy~37_combout ; +wire \z80_|execute_|ctl_inc_dec~2_combout ; +wire \z80_|execute_|ctl_inc_cy~40_combout ; +wire \z80_|execute_|ctl_inc_dec~4_combout ; +wire \z80_|execute_|ctl_inc_dec~5_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~4_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ; +wire \z80_|execute_|setM1~42_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~12_combout ; +wire \z80_|execute_|ctl_sw_1d~4_combout ; +wire \z80_|execute_|ctl_sw_4d~3_combout ; +wire \z80_|execute_|fMRead~9_combout ; +wire \z80_|execute_|fMRead~10_combout ; +wire \z80_|execute_|fMRead~8_combout ; +wire \z80_|execute_|ctl_sw_4d~2_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~11_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~12_combout ; +wire \z80_|execute_|ctl_sw_4d~4_combout ; +wire \z80_|execute_|ctl_sw_4d~5_combout ; +wire \z80_|execute_|ctl_al_we~14_combout ; +wire \z80_|execute_|ctl_al_we~10_combout ; +wire \z80_|execute_|ctl_al_we~6_combout ; +wire \z80_|execute_|ctl_al_we~7_combout ; +wire \z80_|execute_|ctl_al_we~8_combout ; +wire \z80_|execute_|ctl_al_we~9_combout ; +wire \z80_|execute_|ctl_al_we~11_combout ; +wire \z80_|execute_|ctl_al_we~12_combout ; +wire \z80_|execute_|fIOWrite~0_combout ; +wire \z80_|execute_|ctl_inc_dec~8_combout ; +wire \z80_|execute_|ctl_reg_gp_we~2_combout ; +wire \z80_|execute_|ctl_inc_dec~9_combout ; +wire \z80_|execute_|ctl_apin_mux~0_combout ; +wire \z80_|execute_|ctl_inc_dec~6_combout ; +wire \z80_|execute_|ctl_inc_dec~7_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~21_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[0]~40_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~39_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[0]~13_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[0]~31_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ; +wire \z80_|execute_|setM1~49_combout ; +wire \z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ; +wire \z80_|execute_|setM1~50_combout ; +wire \z80_|execute_|ctl_flags_oe~0_combout ; +wire \z80_|execute_|ctl_flags_oe~1_combout ; +wire \z80_|execute_|ctl_reg_in_hi~13_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~12_combout ; +wire \z80_|execute_|ctl_reg_in_hi~7_combout ; +wire \z80_|execute_|ctl_state_alu~13_combout ; +wire \z80_|execute_|ctl_reg_gp_we~6_combout ; +wire \z80_|execute_|ctl_reg_gp_we~5_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~17_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ; wire \z80_|execute_|ctl_alu_sel_op2_neg~10_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~8_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~9_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~11_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~14_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~18_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_high~combout ; +wire \z80_|execute_|ctl_sw_1d~9_combout ; +wire \z80_|execute_|ctl_reg_gp_we~9_combout ; +wire \z80_|execute_|ctl_reg_gp_we~4_combout ; +wire \z80_|execute_|ctl_reg_gp_we~7_combout ; +wire \z80_|execute_|ctl_reg_gp_we~3_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~32_combout ; +wire \z80_|execute_|ctl_sw_4u~2_combout ; +wire \z80_|execute_|ctl_sw_4u~3_combout ; +wire \z80_|execute_|ctl_reg_gp_we~8_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~14_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~24_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~46_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~22_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~23_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~26_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~34_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~25_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~21_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ; +wire \z80_|pla_decode_|Equal2~2_combout ; +wire \z80_|pla_decode_|Equal1~6_combout ; +wire \z80_|reg_control_|bank_exx~2_combout ; +wire \z80_|reg_control_|bank_exx~q ; +wire \z80_|reg_control_|bank_hl_de1~0_combout ; +wire \z80_|reg_control_|bank_hl_de1~q ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~28_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~29_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~30_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~13_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ; +wire \z80_|execute_|ctl_reg_use_sp~2_combout ; +wire \z80_|execute_|ctl_reg_use_sp~3_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~14_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~32_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~33_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~16_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~34_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~20_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~21_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~22_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~18_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~37_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~19_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~23_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~16_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~17_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~11_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~36_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~8_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~9_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~10_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~15_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~31_combout ; +wire \z80_|reg_control_|reg_sel_de2~5_combout ; +wire \z80_|reg_control_|reg_sel_de2~6_combout ; +wire \z80_|reg_control_|reg_sel_de~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ; +wire \z80_|reg_control_|bank_hl_de2~0_combout ; +wire \z80_|reg_control_|bank_hl_de2~q ; +wire \z80_|reg_control_|reg_sel_de2~4_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~33_combout ; +wire \z80_|reg_control_|reg_sel_hl~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ; +wire \z80_|reg_control_|reg_sel_hl2~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~34_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~36_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~15_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~18_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~37_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ; +wire \z80_|reg_control_|reg_sel_iy~2_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~38_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ; +wire \z80_|execute_|ctl_reg_in_hi~9_combout ; +wire \z80_|execute_|ctl_reg_in_hi~10_combout ; +wire \z80_|execute_|ctl_reg_in_lo~8_combout ; +wire \z80_|reg_file_|b2v_latch_sp_lo|latch[2]~feeder_combout ; +wire \z80_|execute_|ctl_reg_use_sp~4_combout ; +wire \z80_|execute_|ctl_reg_use_sp~5_combout ; +wire \z80_|execute_|ctl_reg_use_sp~6_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ; +wire \z80_|execute_|ctl_sw_1d~5_combout ; +wire \z80_|execute_|ctl_im_we~combout ; +wire \z80_|execute_|ctl_sw_1d~6_combout ; +wire \z80_|execute_|ctl_sw_1d~7_combout ; +wire \z80_|reg_file_|db_lo_ds[2]~2_combout ; +wire \z80_|alu_control_|db[2]~28_combout ; +wire \z80_|execute_|ctl_reg_in_hi~11_combout ; +wire \z80_|execute_|ctl_reg_in_hi~12_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~18_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ; +wire \z80_|pla_decode_|Equal21~2_combout ; +wire \z80_|reg_control_|bank_af~0_combout ; +wire \z80_|reg_control_|bank_af~q ; +wire \z80_|reg_control_|reg_sel_af~0_combout ; +wire \z80_|reg_control_|reg_sel_af2~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~17_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~19_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~16_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~20_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~34_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~36_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~35_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~33_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~37_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ; +wire \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~31_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[2]~12_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~32_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~38_combout ; +wire \z80_|execute_|ctl_inc_dec~11_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ; +wire \z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ; +wire \z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ; +wire \z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~4_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~5_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~16_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~6_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~7_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~10_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~8_combout ; +wire \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ; +wire \z80_|execute_|ctl_alu_op_low~42_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~9_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ; +wire \z80_|execute_|ctl_mWrite~18_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~2_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ; +wire \z80_|execute_|ctl_flags_cf2_we~4_combout ; +wire \z80_|execute_|ctl_flags_cf2_we~2_combout ; +wire \z80_|execute_|ctl_flags_cf2_we~3_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_32~combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~81_combout ; +wire \z80_|alu_|db_high[2]~8_combout ; +wire \z80_|alu_|db_high[2]~9_combout ; +wire \z80_|alu_|db_high[2]~11_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_lq~combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~5_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~6_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~7_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~8_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_zero~combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|ena~combout ; +wire \z80_|alu_|db_high[2]~10_combout ; +wire \z80_|alu_|db_high[2]~12_combout ; +wire \z80_|alu_|db_high[3]~1_combout ; +wire \z80_|alu_|db_high[2]~13_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~78_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~79_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ; +wire \z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~75_combout ; +wire \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~76_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~77_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~80_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~74_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~73_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~81_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~19_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~18_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~20_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~92_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~21_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ; +wire \z80_|reg_file_|db_lo_as[0]~2_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~55_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~56_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~57_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~59_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~58_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~60_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~53_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~54_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~61_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~62_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ; +wire \z80_|reg_file_|db_lo_as[4]~13_combout ; +wire \z80_|reg_file_|db_lo_as[4]~14_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ; +wire \z80_|reg_file_|db_lo_as[4]~15_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~64_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~63_combout ; +wire \z80_|reg_file_|b2v_latch_af_lo|latch[5]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~65_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~69_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~68_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~66_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~67_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~70_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~71_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~72_combout ; +wire \z80_|reg_file_|db_lo_as[5]~16_combout ; +wire \z80_|reg_file_|db_lo_as[5]~17_combout ; +wire \z80_|reg_file_|db_lo_as[5]~18_combout ; +wire \z80_|execute_|ctl_inc_dec~10_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ; +wire \z80_|reg_file_|db_lo_as[6]~19_combout ; +wire \z80_|reg_file_|db_lo_as[6]~20_combout ; +wire \z80_|reg_file_|db_lo_as[6]~21_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~82_combout ; +wire \z80_|reg_file_|db_lo_ds[6]~0_combout ; +wire \z80_|sw1_|db_down[6]~1_combout ; +wire \z80_|execute_|ctl_66_oe~combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~4_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~2_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~3_combout ; wire \z80_|alu_|alu_op2[1]~1_combout ; wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ; -wire \z80_|execute_|ctl_alu_core_S~9_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8_combout ; -wire \z80_|alu_|alu_op2[0]~3_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~12_combout ; -wire \z80_|execute_|ctl_alu_core_S~8_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ; -wire \z80_|execute_|ctl_alu_core_hf~21_combout ; -wire \z80_|execute_|ctl_alu_core_hf~22_combout ; -wire \z80_|execute_|ctl_alu_core_hf~19_combout ; -wire \z80_|execute_|ctl_alu_op_low~27_combout ; -wire \z80_|execute_|ctl_alu_op_low~29_combout ; -wire \z80_|execute_|ctl_alu_core_hf~23_combout ; -wire \z80_|execute_|ctl_alu_core_hf~37_combout ; -wire \z80_|execute_|ctl_alu_core_hf~38_combout ; -wire \z80_|execute_|ctl_alu_core_hf~24_combout ; -wire \z80_|execute_|ctl_alu_core_hf~25_combout ; -wire \z80_|execute_|ctl_alu_core_hf~26_combout ; -wire \z80_|execute_|ctl_alu_core_hf~27_combout ; -wire \z80_|execute_|ctl_alu_core_hf~28_combout ; -wire \z80_|execute_|ctl_alu_op_low~30_combout ; -wire \z80_|execute_|ctl_alu_core_hf~34_combout ; -wire \z80_|execute_|ctl_alu_core_hf~32_combout ; -wire \z80_|execute_|ctl_alu_core_hf~43_combout ; -wire \z80_|execute_|ctl_alu_core_hf~33_combout ; -wire \z80_|execute_|ctl_alu_core_hf~42_combout ; -wire \z80_|execute_|ctl_alu_core_hf~35_combout ; -wire \z80_|execute_|ctl_alu_core_hf~41_combout ; -wire \z80_|execute_|ctl_alu_core_hf~30_combout ; -wire \z80_|execute_|ctl_mWrite~10_combout ; -wire \z80_|execute_|ctl_alu_core_hf~31_combout ; -wire \z80_|execute_|ctl_alu_core_hf~44_combout ; -wire \z80_|execute_|ctl_alu_core_hf~29_combout ; -wire \z80_|execute_|ctl_alu_core_hf~36_combout ; -wire \z80_|execute_|ctl_alu_core_hf~39_combout ; -wire \z80_|execute_|ctl_alu_core_hf~40_combout ; -wire \z80_|execute_|ctl_flags_hf_we~2_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ; +wire \z80_|execute_|ctl_alu_core_R~5_combout ; wire \z80_|execute_|ctl_alu_core_R~2_combout ; wire \z80_|execute_|ctl_alu_core_R~combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3_combout ; -wire \z80_|alu_|alu_op2[3]~2_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ; +wire \z80_|alu_|db_high[0]~20_combout ; +wire \z80_|alu_|db_high[0]~21_combout ; +wire \z80_|alu_|db_high[0]~22_combout ; +wire \z80_|alu_|db_high[0]~23_combout ; +wire \z80_|alu_|db_high[0]~24_combout ; +wire \z80_|alu_|db_low[0]~4_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~2_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~3_combout ; +wire \z80_|alu_|db_low[0]~5_combout ; +wire \z80_|alu_|db_low[0]~6_combout ; +wire \z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ; +wire \z80_|execute_|ctl_flags_hf_we~2_combout ; +wire \z80_|execute_|ctl_flags_cf_we~3_combout ; +wire \z80_|execute_|ctl_flags_cf_we~4_combout ; +wire \z80_|execute_|ctl_flags_cf_we~5_combout ; +wire \z80_|execute_|ctl_flags_cf_we~6_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf~q ; +wire \z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ; +wire \z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ; +wire \z80_|alu_|db_low[0]~2_combout ; +wire \z80_|alu_|db_low[0]~3_combout ; +wire \z80_|alu_|db_low[0]~24_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~0_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~1_combout ; +wire \z80_|alu_|alu_op2[0]~3_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla26M3T5_8~combout ; +wire \z80_|execute_|ctl_alu_core_hf~14_combout ; +wire \z80_|execute_|ctl_alu_core_hf~16_combout ; +wire \z80_|execute_|ctl_alu_core_hf~13_combout ; +wire \z80_|execute_|ctl_alu_core_hf~17_combout ; +wire \z80_|execute_|ctl_alu_op_low~44_combout ; +wire \z80_|execute_|ctl_alu_core_hf~20_combout ; +wire \z80_|execute_|ctl_alu_core_hf~21_combout ; +wire \z80_|execute_|ctl_alu_core_hf~18_combout ; +wire \z80_|execute_|ctl_alu_core_hf~19_combout ; +wire \z80_|execute_|ctl_alu_core_hf~22_combout ; +wire \z80_|execute_|ctl_alu_op_low~43_combout ; +wire \z80_|execute_|ctl_alu_core_hf~24_combout ; +wire \z80_|execute_|ctl_alu_core_hf~25_combout ; +wire \z80_|execute_|ctl_alu_core_hf~35_combout ; +wire \z80_|execute_|ctl_alu_core_hf~23_combout ; +wire \z80_|execute_|ctl_alu_core_hf~26_combout ; +wire \z80_|execute_|ctl_alu_core_hf~34_combout ; +wire \z80_|execute_|ctl_alu_core_hf~27_combout ; +wire \z80_|execute_|ctl_alu_core_hf~28_combout ; +wire \z80_|execute_|ctl_alu_core_hf~29_combout ; +wire \z80_|execute_|ctl_alu_core_hf~30_combout ; +wire \z80_|execute_|ctl_alu_core_hf~31_combout ; +wire \z80_|execute_|ctl_alu_core_hf~36_combout ; +wire \z80_|execute_|ctl_alu_core_hf~37_combout ; +wire \z80_|execute_|ctl_alu_core_hf~32_combout ; +wire \z80_|execute_|ctl_alu_core_hf~33_combout ; +wire \z80_|alu_control_|alu_core_cf_in~0_combout ; +wire \z80_|alu_|alu_op1[0]~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ; +wire \z80_|alu_|db_high[0]~25_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~6_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ; +wire \z80_|alu_|db_high[1]~14_combout ; +wire \z80_|alu_|db_high[1]~15_combout ; +wire \z80_|alu_|db_high[1]~16_combout ; +wire \z80_|alu_|db_high[1]~17_combout ; +wire \z80_|alu_|db_high[1]~18_combout ; +wire \z80_|alu_|db_high[1]~19_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ; +wire \z80_|alu_control_|out[6]~0_combout ; +wire \z80_|alu_control_|out[6]~1_combout ; +wire \z80_|alu_control_|out[6]~2_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ; +wire \z80_|execute_|ctl_flags_sz_we~7_combout ; +wire \z80_|execute_|ctl_flags_sz_we~8_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ; +wire \z80_|execute_|setM1~51_combout ; +wire \z80_|execute_|ctl_flags_oe~2_combout ; +wire \z80_|execute_|ctl_sw_2u~7_combout ; +wire \z80_|alu_control_|db[6]~20_combout ; +wire \z80_|alu_control_|db[6]~21_combout ; +wire \z80_|execute_|ctl_reg_out_lo~8_combout ; +wire \z80_|alu_control_|db[6]~10_combout ; +wire \z80_|alu_control_|db[6]~11_combout ; +wire \z80_|alu_control_|db[6]~22_combout ; +wire \z80_|alu_|db[6]~21_combout ; +wire \z80_|alu_|db[6]~22_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~80_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~79_combout ; +wire \z80_|reg_file_|b2v_latch_bc_hi|latch[6]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~78_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~82_combout ; +wire \z80_|reg_file_|b2v_latch_hl2_hi|db[6]~5_combout ; +wire \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~76_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~77_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~83_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~84_combout ; +wire \z80_|reg_file_|db_hi_as[6]~22_combout ; +wire \z80_|reg_file_|db_hi_as[6]~23_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~61_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~62_combout ; +wire \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~60_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~63_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~64_combout ; +wire \z80_|reg_file_|b2v_latch_hl2_hi|db[4]~4_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~58_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~59_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~65_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~66_combout ; +wire \z80_|reg_file_|db_hi_as[4]~16_combout ; +wire \z80_|reg_file_|db_hi_as[4]~17_combout ; +wire \z80_|reg_file_|db_hi_as[4]~18_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ; +wire \z80_|reg_file_|db_hi_as[6]~24_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|address[15]~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|address[15]~1_combout ; +wire \z80_|reg_file_|db_hi_as[7]~19_combout ; +wire \z80_|reg_file_|db_hi_as[7]~20_combout ; +wire \z80_|reg_file_|db_hi_as[7]~21_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[7]~15_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~72_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~71_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~70_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~69_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~73_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~68_combout ; +wire \z80_|reg_file_|b2v_latch_de_hi|latch[7]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~67_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~74_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~75_combout ; +wire \z80_|alu_|db[7]~11_combout ; +wire \z80_|alu_|db[7]~12_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf2~q ; +wire \z80_|execute_|ctl_flags_use_cf2~8_combout ; +wire \z80_|execute_|ctl_flags_use_cf2~9_combout ; +wire \z80_|execute_|ctl_flags_use_cf2~10_combout ; +wire \z80_|execute_|ctl_flags_use_cf2~11_combout ; +wire \z80_|execute_|ctl_flags_use_cf2~12_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ; +wire \z80_|execute_|ctl_alu_op_low~46_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~9_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~3_combout ; +wire \z80_|alu_flags_|flags_cf~combout ; +wire \z80_|sw2_|db_up[0]~0_combout ; +wire \z80_|alu_control_|db[0]~8_combout ; +wire \z80_|reg_file_|db_lo_as[0]~0_combout ; +wire \z80_|reg_file_|db_lo_as[0]~1_combout ; +wire \z80_|execute_|ctl_inc_cy~70_combout ; +wire \z80_|execute_|pc_inc_hold~28_combout ; +wire \z80_|execute_|pc_inc_hold~15_combout ; +wire \z80_|execute_|pc_inc_hold~27_combout ; +wire \z80_|execute_|pc_inc_hold~10_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ; +wire \z80_|execute_|pc_inc_hold~11_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ; +wire \z80_|execute_|pc_inc_hold~9_combout ; +wire \z80_|execute_|pc_inc_hold~12_combout ; +wire \z80_|execute_|pc_inc_hold~7_combout ; +wire \z80_|execute_|pc_inc_hold~8_combout ; +wire \z80_|execute_|pc_inc_hold~13_combout ; +wire \z80_|execute_|pc_inc_hold~14_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ; +wire \z80_|execute_|pc_inc_hold~16_combout ; +wire \z80_|execute_|pc_inc_hold~22_combout ; +wire \z80_|execute_|pc_inc_hold~23_combout ; +wire \z80_|execute_|pc_inc_hold~24_combout ; +wire \z80_|execute_|ctl_inc_cy~41_combout ; +wire \z80_|execute_|pc_inc_hold~21_combout ; +wire \z80_|execute_|pc_inc_hold~25_combout ; +wire \z80_|execute_|ctl_inc_cy~69_combout ; +wire \z80_|execute_|pc_inc_hold~17_combout ; +wire \z80_|execute_|ctl_inc_cy~71_combout ; +wire \z80_|execute_|ctl_inc_cy~44_combout ; +wire \z80_|execute_|ctl_inc_cy~42_combout ; +wire \z80_|execute_|ctl_inc_cy~43_combout ; +wire \z80_|execute_|ctl_inc_cy~57_combout ; +wire \z80_|execute_|ctl_inc_cy~54_combout ; +wire \z80_|execute_|ctl_inc_cy~58_combout ; +wire \z80_|execute_|pc_inc_hold~18_combout ; +wire \z80_|execute_|pc_inc_hold~19_combout ; +wire \z80_|execute_|ctl_inc_cy~45_combout ; +wire \z80_|execute_|ctl_inc_cy~34_combout ; +wire \z80_|execute_|ctl_inc_cy~35_combout ; +wire \z80_|execute_|ctl_inc_cy~46_combout ; +wire \z80_|execute_|ctl_inc_cy~47_combout ; +wire \z80_|execute_|ctl_inc_cy~48_combout ; +wire \z80_|execute_|ctl_inc_cy~50_combout ; +wire \z80_|execute_|ctl_inc_cy~51_combout ; +wire \z80_|execute_|ctl_inc_cy~85_combout ; +wire \z80_|execute_|ctl_inc_cy~63_combout ; +wire \z80_|execute_|ctl_inc_cy~64_combout ; +wire \z80_|execute_|ctl_inc_cy~65_combout ; +wire \z80_|execute_|ctl_inc_cy~59_combout ; +wire \z80_|execute_|ctl_inc_cy~60_combout ; +wire \z80_|execute_|ctl_inc_cy~61_combout ; +wire \z80_|execute_|ctl_inc_cy~62_combout ; +wire \z80_|execute_|ctl_inc_cy~66_combout ; +wire \z80_|execute_|ctl_inc_cy~53_combout ; +wire \z80_|execute_|ctl_inc_cy~52_combout ; +wire \z80_|execute_|ctl_inc_cy~84_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ; +wire \z80_|execute_|ctl_inc_cy~55_combout ; +wire \z80_|execute_|ctl_inc_cy~56_combout ; +wire \z80_|execute_|ctl_inc_cy~67_combout ; +wire \z80_|execute_|pc_inc_hold~20_combout ; +wire \z80_|execute_|ctl_inc_cy~83_combout ; +wire \z80_|execute_|ctl_inc_cy~68_combout ; +wire \z80_|address_latch_|Q[0]~feeder_combout ; +wire \z80_|execute_|ctl_inc_cy~72_combout ; +wire \z80_|execute_|ctl_inc_cy~73_combout ; +wire \z80_|execute_|ctl_inc_cy~74_combout ; +wire \z80_|execute_|ctl_inc_cy~75_combout ; +wire \z80_|execute_|ctl_inc_cy~76_combout ; +wire \z80_|execute_|ctl_inc_cy~80_combout ; +wire \z80_|execute_|ctl_inc_cy~81_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ; +wire \z80_|reg_file_|db_lo_as[0]~3_combout ; +wire \z80_|reg_file_|b2v_latch_af_lo|latch[0]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~13_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~12_combout ; +wire \z80_|reg_file_|b2v_latch_de_lo|latch[0]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~10_combout ; +wire \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~11_combout ; +wire \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~14_combout ; +wire \z80_|reg_file_|b2v_latch_sp_lo|latch[0]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~15_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~16_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~17_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~22_combout ; +wire \z80_|alu_control_|db[0]~9_combout ; +wire \z80_|alu_control_|db[0]~12_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~84_combout ; +wire \z80_|reg_file_|b2v_latch_de_lo|latch[7]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~83_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~88_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~86_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~87_combout ; +wire \z80_|reg_file_|b2v_latch_wz_lo|db[7]~0_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~89_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~85_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~90_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~91_combout ; +wire \z80_|reg_file_|db_lo_as[7]~22_combout ; +wire \z80_|reg_file_|db_lo_as[7]~23_combout ; +wire \z80_|reg_file_|db_lo_as[7]~24_combout ; +wire \z80_|address_latch_|Q[7]~feeder_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ; +wire \z80_|reg_file_|db_hi_as[0]~4_combout ; +wire \z80_|reg_file_|db_hi_as[0]~5_combout ; +wire \z80_|reg_file_|db_hi_as[0]~6_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~23_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~25_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~27_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~24_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~26_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~28_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[0]~11_combout ; +wire \z80_|reg_file_|b2v_latch_de_hi|latch[0]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~22_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~29_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~30_combout ; +wire \z80_|alu_|db[0]~13_combout ; +wire \z80_|alu_|db[0]~14_combout ; +wire \z80_|alu_|db_low[1]~10_combout ; +wire \z80_|alu_|db_low[1]~11_combout ; +wire \z80_|alu_|db_low[1]~8_combout ; +wire \z80_|alu_|db_low[1]~7_combout ; +wire \z80_|alu_|result_lo[1]~feeder_combout ; +wire \z80_|alu_|db_low[1]~9_combout ; +wire \z80_|alu_|db_low[1]~12_combout ; +wire \z80_|alu_|db[1]~8_combout ; +wire \z80_|alu_|db[1]~10_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~12_combout ; +wire \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~11_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~10_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~13_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~14_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[1]~10_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~9_combout ; +wire \z80_|reg_file_|b2v_latch_de_hi|latch[1]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~8_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~15_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~21_combout ; +wire \z80_|reg_file_|db_hi_as[1]~0_combout ; +wire \z80_|reg_file_|db_hi_as[1]~1_combout ; +wire \z80_|reg_file_|db_hi_as[1]~3_combout ; +wire \z80_|address_latch_|Q[9]~feeder_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ; +wire \z80_|reg_file_|db_hi_as[2]~7_combout ; +wire \z80_|reg_file_|db_hi_as[2]~8_combout ; +wire \z80_|reg_file_|db_hi_as[2]~9_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~39_combout ; +wire \z80_|alu_|db[2]~15_combout ; +wire \z80_|alu_|db[2]~16_combout ; +wire \z80_|alu_control_|db[2]~27_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ; +wire \z80_|alu_flags_|flags_hf2~0_combout ; +wire \z80_|alu_flags_|flags_hf2~q ; +wire \z80_|alu_control_|db[2]~23_combout ; +wire \z80_|alu_control_|db[2]~29_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~39_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~35_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~40_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~41_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~42_combout ; +wire \z80_|reg_file_|db_lo_as[2]~7_combout ; +wire \z80_|reg_file_|db_lo_as[2]~8_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ; +wire \z80_|reg_file_|db_lo_as[2]~9_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ; +wire \z80_|reg_file_|db_lo_as[3]~10_combout ; +wire \z80_|reg_file_|db_lo_as[3]~11_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ; +wire \z80_|reg_file_|db_lo_as[3]~12_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ; +wire \z80_|reg_file_|db_hi_as[3]~12_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~41_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~45_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~44_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~43_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~42_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~46_combout ; +wire \z80_|reg_file_|b2v_latch_de_hi|latch[3]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~40_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[3]~13_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~47_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~48_combout ; +wire \z80_|alu_|db[3]~19_combout ; +wire \z80_|alu_|db[3]~20_combout ; +wire \z80_|alu_|db_low[2]~21_combout ; +wire \z80_|alu_|db_low[2]~22_combout ; +wire \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~6_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~7_combout ; +wire \z80_|alu_|db_low[2]~18_combout ; +wire \z80_|alu_|db_low[2]~19_combout ; +wire \z80_|alu_|db_low[2]~20_combout ; +wire \z80_|alu_|db_low[2]~23_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~7_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~8_combout ; +wire \z80_|alu_|alu_op1[2]~1_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ; wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ; wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ; @@ -1350,449 +1582,292 @@ wire \z80_|execute_|ctl_flags_hf_we~3_combout ; wire \z80_|execute_|ctl_flags_hf_we~4_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_hf~q ; -wire \z80_|execute_|ctl_flags_hf_cpl~11_combout ; -wire \z80_|execute_|ctl_flags_hf_cpl~12_combout ; -wire \z80_|execute_|ctl_flags_hf_cpl~13_combout ; wire \z80_|alu_flags_|flags_hf~combout ; -wire \z80_|alu_control_|alu_core_cf_in~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ; -wire \z80_|alu_|db_high[0]~23_combout ; -wire \z80_|address_latch_|Q[12]~feeder_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ; -wire \z80_|reg_file_|db_hi_as[4]~16_combout ; -wire \z80_|reg_file_|db_hi_as[4]~17_combout ; -wire \z80_|reg_file_|db_hi_as[4]~18_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~62_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~63_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~61_combout ; -wire \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~60_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~64_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~59_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~58_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[4]~19_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~65_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~66_combout ; -wire \z80_|alu_|db[4]~16_combout ; -wire \z80_|alu_|db[7]~26_combout ; +wire \z80_|alu_control_|db[4]~30_combout ; +wire \z80_|alu_control_|db[4]~31_combout ; +wire \z80_|alu_control_|db[4]~32_combout ; wire \z80_|alu_|db[4]~17_combout ; -wire \z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ; -wire \z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ; -wire \z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ; -wire \z80_|alu_|db_high[0]~24_combout ; -wire \z80_|alu_|db_high[0]~21_combout ; -wire \z80_|alu_|db_high[0]~22_combout ; -wire \z80_|alu_|db_high[0]~25_combout ; -wire \z80_|alu_|db_high[0]~26_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|ena~combout ; -wire \z80_|alu_|alu_op1[0]~1_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ; -wire \z80_|alu_|alu_op1[1]~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ; -wire \z80_|alu_|alu_op1[2]~2_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ; -wire \z80_|execute_|ctl_alu_core_R~5_combout ; +wire \z80_|alu_|db[4]~18_combout ; +wire \z80_|alu_|db_low[3]~13_combout ; +wire \z80_|alu_|db_low[3]~14_combout ; +wire \z80_|alu_|db_low[3]~17_combout ; +wire \z80_|alu_|db_low[3]~25_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~4_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~5_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1_combout ; +wire \z80_|alu_|alu_op2[3]~2_combout ; wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout ; wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ; -wire \z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~69_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~70_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~72_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~71_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~73_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~67_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[7]~20_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~68_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~74_combout ; -wire \z80_|reg_file_|db_hi_as[7]~19_combout ; -wire \z80_|reg_file_|db_hi_as[7]~20_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~54_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~53_combout ; -wire \z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~51_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~52_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~55_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~49_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~50_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[5]~14_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~56_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~57_combout ; -wire \z80_|reg_file_|db_hi_as[5]~13_combout ; -wire \z80_|reg_file_|db_hi_as[5]~14_combout ; -wire \z80_|reg_file_|db_hi_as[5]~15_combout ; -wire \z80_|address_latch_|Q[13]~feeder_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~76_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~80_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~79_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~78_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~81_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~82_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~77_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[6]~21_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~83_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~84_combout ; -wire \z80_|reg_file_|db_hi_as[6]~22_combout ; -wire \z80_|reg_file_|db_hi_as[6]~23_combout ; -wire \z80_|reg_file_|db_hi_as[6]~24_combout ; -wire \z80_|address_latch_|Q[14]~feeder_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout ; -wire \z80_|reg_file_|db_hi_as[7]~21_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~75_combout ; -wire \z80_|alu_|db[7]~20_combout ; -wire \z80_|alu_|db[7]~21_combout ; -wire \z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ; -wire \z80_|execute_|ctl_flags_cf_we~4_combout ; -wire \z80_|execute_|ctl_flags_cf_we~5_combout ; -wire \z80_|execute_|ctl_flags_cf_we~3_combout ; -wire \z80_|execute_|ctl_flags_cf_we~6_combout ; -wire \z80_|execute_|ctl_flags_cf2_we~2_combout ; -wire \z80_|execute_|ctl_flags_cf2_we~4_combout ; -wire \z80_|execute_|ctl_flags_cf2_we~3_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf~q ; -wire \z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ; -wire \z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ; -wire \z80_|alu_|db_high[3]~5_combout ; -wire \z80_|alu_|db_high[3]~6_combout ; +wire \z80_|alu_|db_high[3]~3_combout ; wire \z80_|alu_|db_high[3]~4_combout ; -wire \z80_|alu_|db_high[3]~27_combout ; +wire \z80_|alu_|db_high[3]~5_combout ; +wire \z80_|alu_|db_high[3]~2_combout ; +wire \z80_|alu_|db_high[3]~6_combout ; wire \z80_|alu_|db_high[3]~7_combout ; -wire \z80_|alu_|db_high[3]~8_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4_combout ; -wire \z80_|alu_|db_low[3]~9_combout ; -wire \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ; -wire \z80_|alu_|db_low[3]~10_combout ; -wire \z80_|alu_|db_low[3]~7_combout ; -wire \z80_|alu_|db_low[3]~8_combout ; -wire \z80_|alu_|db_low[3]~11_combout ; -wire \z80_|alu_|db_low[3]~25_combout ; -wire \z80_|alu_|db[3]~10_combout ; -wire \z80_|alu_|db[3]~11_combout ; -wire \z80_|execute_|ctl_sw_2u~7_combout ; -wire \z80_|execute_|setM1~49_combout ; -wire \z80_|execute_|ctl_flags_oe~2_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ; -wire \z80_|execute_|ctl_flags_sz_we~7_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ; -wire \z80_|execute_|ctl_flags_xy_we~13_combout ; -wire \z80_|execute_|ctl_flags_xy_we~14_combout ; -wire \z80_|execute_|ctl_flags_xy_we~15_combout ; -wire \z80_|alu_flags_|flags_xf~q ; -wire \z80_|alu_control_|db[3]~33_combout ; -wire \z80_|execute_|ctl_reg_out_lo~3_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ; -wire \z80_|execute_|ctl_reg_out_lo~4_combout ; -wire \z80_|execute_|ctl_reg_out_lo~5_combout ; -wire \z80_|execute_|ctl_reg_out_lo~8_combout ; -wire \z80_|sw1_|db_down[3]~1_combout ; -wire \z80_|alu_control_|db[3]~34_combout ; -wire \z80_|alu_control_|db[3]~35_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~46_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~47_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~50_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~44_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~43_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~51_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~52_combout ; -wire \z80_|reg_file_|db_lo_as[3]~10_combout ; -wire \z80_|reg_file_|db_lo_as[3]~11_combout ; -wire \z80_|reg_file_|db_lo_as[3]~12_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~53_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~54_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~58_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~59_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~60_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~57_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~55_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~56_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~61_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~62_combout ; -wire \z80_|reg_file_|db_lo_as[4]~13_combout ; -wire \z80_|reg_file_|db_lo_as[4]~14_combout ; -wire \z80_|reg_file_|db_lo_as[4]~15_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~64_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~63_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~66_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~67_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~65_combout ; -wire \z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~69_combout ; -wire \z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~68_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~70_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~71_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~72_combout ; -wire \z80_|reg_file_|db_lo_as[5]~16_combout ; -wire \z80_|reg_file_|db_lo_as[5]~17_combout ; -wire \z80_|reg_file_|db_lo_as[5]~18_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout ; -wire \z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~74_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~73_combout ; -wire \z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~78_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~79_combout ; -wire \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~76_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~77_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~80_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~75_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~81_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~82_combout ; -wire \z80_|reg_file_|db_lo_as[6]~19_combout ; -wire \z80_|reg_file_|db_lo_as[6]~20_combout ; -wire \z80_|reg_file_|db_lo_as[6]~21_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ; -wire \z80_|reg_file_|db_lo_as[7]~24_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~83_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~84_combout ; -wire \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~88_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~86_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~87_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~85_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~89_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~90_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~91_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~92_combout ; -wire \z80_|reg_file_|db_lo_ds[7]~0_combout ; -wire \z80_|interrupts_|im2~q ; -wire \z80_|execute_|ctl_mRead~12_combout ; -wire \z80_|execute_|ctl_sw_mask543_en~0_combout ; -wire \z80_|alu_control_|db[7]~17_combout ; -wire \z80_|alu_control_|db[7]~16_combout ; -wire \z80_|alu_control_|db[7]~18_combout ; wire \z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ; -wire \z80_|execute_|ctl_flags_sz_we~8_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_sf~q ; -wire \z80_|pla_decode_|Equal62~3_combout ; -wire \z80_|execute_|ctl_flags_pf_we~5_combout ; -wire \z80_|execute_|ctl_flags_pf_we~6_combout ; -wire \z80_|execute_|ctl_flags_pf_we~7_combout ; -wire \z80_|execute_|ctl_flags_pf_we~8_combout ; -wire \z80_|execute_|ctl_flags_pf_we~9_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~5_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~7_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~6_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~8_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~11_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~12_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~15_combout ; +wire \z80_|alu_|alu_op2[2]~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ; +wire \z80_|alu_control_|DFFE_latch_pf_tmp~q ; +wire \z80_|alu_|alu_parity_out~0_combout ; +wire \z80_|alu_|alu_parity_out~1_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ; -wire \z80_|decode_state_|DFFE_instNonRep~0_combout ; -wire \z80_|decode_state_|DFFE_instNonRep~3_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~1_combout ; wire \z80_|decode_state_|DFFE_instNonRep~2_combout ; wire \z80_|decode_state_|DFFE_instNonRep~1_combout ; +wire \z80_|decode_state_|DFFE_instNonRep~3_combout ; +wire \z80_|decode_state_|DFFE_instNonRep~0_combout ; wire \z80_|decode_state_|DFFE_instNonRep~4_combout ; wire \z80_|decode_state_|DFFE_instNonRep~5_combout ; wire \z80_|decode_state_|DFFE_instNonRep~q ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~1_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ; -wire \z80_|alu_control_|DFFE_latch_pf_tmp~q ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ; -wire \z80_|alu_|alu_parity_out~0_combout ; -wire \z80_|alu_|alu_parity_out~combout ; wire \z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_pf~10_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_pf~q ; wire \z80_|alu_control_|sel[1]~0_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ; wire \z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ; wire \z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ; wire \z80_|alu_control_|flags_cond_true~0_combout ; wire \z80_|alu_control_|flags_cond_true~q ; -wire \z80_|execute_|ctl_reg_sel_wz~13_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~14_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~17_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~18_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~20_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~21_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~20_combout ; +wire \z80_|execute_|ctl_sw_4d~1_combout ; +wire \z80_|execute_|ctl_sw_4d~6_combout ; +wire \z80_|reg_file_|db_lo_as[1]~4_combout ; +wire \z80_|reg_file_|db_lo_as[1]~5_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ; +wire \z80_|reg_file_|db_lo_as[1]~6_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~29_combout ; wire \z80_|reg_file_|gdfx_temp0[1]~28_combout ; wire \z80_|reg_file_|gdfx_temp0[1]~26_combout ; wire \z80_|reg_file_|gdfx_temp0[1]~27_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~29_combout ; -wire \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~25_combout ; wire \z80_|reg_file_|gdfx_temp0[1]~30_combout ; -wire \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder_combout ; wire \z80_|reg_file_|gdfx_temp0[1]~24_combout ; wire \z80_|reg_file_|gdfx_temp0[1]~23_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~25_combout ; wire \z80_|reg_file_|gdfx_temp0[1]~31_combout ; wire \z80_|reg_file_|gdfx_temp0[1]~32_combout ; wire \z80_|reg_file_|db_lo_ds[1]~1_combout ; wire \z80_|alu_control_|db[1]~25_combout ; wire \z80_|alu_control_|db[1]~24_combout ; wire \z80_|alu_control_|db[1]~26_combout ; -wire \z80_|alu_|db[1]~12_combout ; -wire \z80_|alu_|db[1]~13_combout ; -wire \z80_|alu_|db_low[0]~21_combout ; -wire \z80_|alu_|db_low[0]~22_combout ; -wire \z80_|alu_|db_low[0]~18_combout ; -wire \z80_|alu_|db_low[0]~19_combout ; -wire \z80_|alu_|db_low[0]~20_combout ; -wire \z80_|alu_|db_low[0]~23_combout ; -wire \z80_|alu_|db[0]~18_combout ; -wire \z80_|alu_|db[0]~19_combout ; -wire \z80_|alu_|db_low[1]~15_combout ; -wire \z80_|alu_|db_low[1]~16_combout ; -wire \z80_|alu_|db_low[1]~12_combout ; -wire \z80_|alu_|db_low[1]~13_combout ; -wire \z80_|alu_|db_low[1]~14_combout ; -wire \z80_|alu_|db_low[1]~17_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6_combout ; -wire \z80_|alu_control_|out[6]~0_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ; -wire \z80_|alu_flags_|flags_hf2~0_combout ; -wire \z80_|alu_flags_|flags_hf2~q ; -wire \z80_|alu_control_|db[2]~23_combout ; -wire \z80_|reg_file_|db_lo_ds[2]~2_combout ; -wire \z80_|alu_control_|db[2]~28_combout ; -wire \z80_|alu_control_|db[2]~27_combout ; -wire \z80_|alu_control_|db[2]~29_combout ; -wire \z80_|alu_|db[2]~14_combout ; -wire \z80_|alu_|db[2]~15_combout ; -wire \z80_|alu_|db_low[2]~2_combout ; -wire \z80_|alu_|db_low[2]~3_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1_combout ; -wire \z80_|alu_|db_low[2]~5_combout ; -wire \z80_|alu_|db_low[2]~6_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4_combout ; -wire \z80_|alu_|alu_op2[2]~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ; -wire \z80_|alu_|db_high[2]~9_combout ; -wire \z80_|alu_|db_high[2]~11_combout ; -wire \z80_|alu_|db_high[2]~12_combout ; -wire \z80_|alu_|db_high[2]~10_combout ; -wire \z80_|alu_|db_high[2]~13_combout ; -wire \z80_|alu_|db_high[2]~14_combout ; -wire \z80_|alu_|db[6]~22_combout ; -wire \z80_|alu_|db[6]~23_combout ; -wire \z80_|alu_control_|out[6]~1_combout ; -wire \z80_|alu_control_|out[6]~2_combout ; -wire \z80_|alu_control_|db[6]~19_combout ; -wire \z80_|alu_control_|db[6]~20_combout ; -wire \z80_|alu_control_|db[6]~21_combout ; -wire \z80_|alu_control_|db[6]~22_combout ; -wire \z80_|execute_|ctl_bus_zero_oe~0_combout ; -wire \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ; -wire \z80_|interrupts_|im1~q ; -wire \z80_|execute_|ctl_bus_ff_oe~0_combout ; -wire \z80_|execute_|ctl_bus_ff_oe~1_combout ; -wire \z80_|bus_control_|db[0]~4_combout ; -wire \z80_|bus_control_|db[6]~8_combout ; -wire \z80_|execute_|ctl_mRead~37_combout ; -wire \z80_|execute_|ctl_mRead~28_combout ; -wire \z80_|execute_|ctl_mRead~29_combout ; -wire \z80_|execute_|ctl_mRead~30_combout ; -wire \z80_|execute_|setM1~37_combout ; -wire \z80_|execute_|setM1~55_combout ; -wire \z80_|execute_|setM1~38_combout ; -wire \z80_|execute_|ctl_mRead~34_combout ; -wire \z80_|execute_|nextM~3_combout ; -wire \z80_|execute_|ctl_mRead~31_combout ; -wire \z80_|execute_|ctl_mRead~32_combout ; -wire \z80_|execute_|ctl_mRead~33_combout ; -wire \z80_|execute_|ctl_mRead~35_combout ; -wire \z80_|memory_ifc_|DFFE_mrd_ff1~q ; -wire \z80_|memory_ifc_|wait_mrd~feeder_combout ; -wire \z80_|memory_ifc_|wait_mrd~q ; -wire \z80_|memory_ifc_|DFFE_mrd_ff3~q ; -wire \z80_|memory_ifc_|nRD_out~1_combout ; +wire \z80_|bus_control_|db[1]~10_combout ; wire \z80_|execute_|nextM~4_combout ; wire \z80_|execute_|ctl_iorw~12_combout ; wire \z80_|execute_|ctl_iorw~8_combout ; wire \z80_|execute_|ctl_iorw~9_combout ; wire \z80_|memory_ifc_|DFFE_iorq_ff1~q ; -wire \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder_combout ; wire \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ; +wire \z80_|memory_ifc_|wait_iorq~feeder_combout ; wire \z80_|memory_ifc_|wait_iorq~q ; wire \z80_|memory_ifc_|DFFE_iorq_ff4~q ; wire \z80_|memory_ifc_|iorq~0_combout ; -wire \z80_|execute_|fIORead~1_combout ; -wire \z80_|execute_|fIORead~2_combout ; -wire \z80_|execute_|fIORead~0_combout ; -wire \z80_|execute_|fIORead~3_combout ; wire \z80_|memory_ifc_|DFFE_m1_ff1~q ; wire \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout ; wire \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ; wire \z80_|memory_ifc_|DFFE_m1_ff3~q ; wire \z80_|memory_ifc_|nRD_out~0_combout ; +wire \z80_|execute_|fIORead~0_combout ; +wire \z80_|execute_|fIORead~1_combout ; +wire \z80_|execute_|fIORead~2_combout ; +wire \z80_|execute_|fIOWrite~1_combout ; +wire \z80_|execute_|fIORead~3_combout ; +wire \z80_|execute_|ctl_mRead~30_combout ; +wire \z80_|execute_|ctl_mRead~31_combout ; +wire \z80_|execute_|nextM~3_combout ; +wire \z80_|execute_|ctl_mRead~29_combout ; +wire \z80_|execute_|setM1~58_combout ; +wire \z80_|execute_|setM1~38_combout ; +wire \z80_|execute_|fMRead~4_combout ; +wire \z80_|execute_|setM1~39_combout ; +wire \z80_|execute_|setM1~40_combout ; +wire \z80_|execute_|ctl_mRead~32_combout ; +wire \z80_|execute_|ctl_mRead~33_combout ; +wire \z80_|memory_ifc_|DFFE_mrd_ff1~q ; +wire \z80_|memory_ifc_|wait_mrd~feeder_combout ; +wire \z80_|memory_ifc_|wait_mrd~q ; +wire \z80_|memory_ifc_|DFFE_mrd_ff3~q ; +wire \z80_|memory_ifc_|nRD_out~1_combout ; wire \z80_|memory_ifc_|nRD_out~2_combout ; +wire \z80_|execute_|fIOWrite~3_combout ; +wire \z80_|execute_|fIOWrite~4_combout ; +wire \z80_|execute_|fIOWrite~2_combout ; +wire \z80_|execute_|fIOWrite~5_combout ; +wire \z80_|execute_|ctl_mWrite~15_combout ; +wire \z80_|execute_|ctl_mWrite~12_combout ; +wire \z80_|execute_|ctl_mWrite~13_combout ; +wire \z80_|execute_|ctl_mWrite~14_combout ; +wire \z80_|execute_|ctl_mWrite~16_combout ; +wire \z80_|memory_ifc_|DFFE_mwr_ff1~q ; +wire \z80_|memory_ifc_|wait_mwr~feeder_combout ; +wire \z80_|memory_ifc_|wait_mwr~q ; +wire \z80_|memory_ifc_|mwr_wr~q ; +wire \z80_|memory_ifc_|nWR_out~0_combout ; wire \Equal2~1_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~0_combout ; -wire \z80_|execute_|fMWrite~5_combout ; -wire \z80_|execute_|fMWrite~6_combout ; -wire \z80_|execute_|fMWrite~2_combout ; +wire \z80_|execute_|fMWrite~3_combout ; wire \z80_|execute_|fMWrite~4_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~1_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~2_combout ; +wire \z80_|execute_|fMWrite~0_combout ; +wire \z80_|execute_|fMWrite~2_combout ; wire \z80_|pin_control_|bus_db_pin_oe~3_combout ; -wire \z80_|execute_|fMWrite~7_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~4_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~7_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~6_combout ; -wire \z80_|execute_|fMWrite~9_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~8_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~9_combout ; wire \z80_|execute_|fMWrite~8_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~5_combout ; +wire \z80_|execute_|fMWrite~7_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~16_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~8_combout ; +wire \z80_|execute_|fMWrite~6_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~9_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~7_combout ; wire \z80_|pin_control_|bus_db_pin_oe~10_combout ; -wire \z80_|execute_|fMWrite~10_combout ; wire \z80_|pin_control_|bus_db_pin_oe~11_combout ; +wire \z80_|execute_|fMWrite~5_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~6_combout ; wire \z80_|pin_control_|bus_db_pin_oe~12_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~4_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~5_combout ; wire \z80_|pin_control_|bus_db_pin_oe~13_combout ; wire \z80_|pin_control_|bus_db_pin_oe~14_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~2_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~15_combout ; wire \z80_|clk_delay_|DFF_inst5~feeder_combout ; wire \z80_|clk_delay_|DFF_inst5~q ; -wire \z80_|memory_ifc_|wait_iorqinta~feeder_combout ; wire \z80_|memory_ifc_|wait_iorqinta~q ; wire \z80_|memory_ifc_|DFFE_intr_ff3~q ; wire \z80_|memory_ifc_|nIORQ_out~0_combout ; wire \Equal2~0_combout ; -wire \ExtRamWE~0_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[13]~13_combout ; +wire \z80_|execute_|ctl_apin_mux~2_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[10]~10_combout ; wire \z80_|execute_|ctl_apin_mux2~0_combout ; -wire \z80_|pin_control_|bus_ab_pin_we~2_combout ; -wire \z80_|pin_control_|bus_ab_pin_we~3_combout ; +wire \z80_|pin_control_|bus_ab_pin_we~0_combout ; +wire \z80_|pin_control_|bus_ab_pin_we~1_combout ; +wire \PS2_DAT~input_o ; +wire \ula_|pll_|altpll_component|auto_generated|wire_pll1_locked ; +wire \KEY[0]~input_o ; +wire \reset~combout ; +wire \reset~clkctrl_outclk ; +wire \ula_|ps2_keyboard_|bit_count~3_combout ; +wire \PS2_CLK~input_o ; +wire \ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ; +wire \ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ; +wire \ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ; +wire \ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ; +wire \ula_|ps2_keyboard_|clk_filter[3]~feeder_combout ; +wire \ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ; +wire \ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ; +wire \ula_|ps2_keyboard_|Equal0~0_combout ; +wire \ula_|ps2_keyboard_|Equal0~1_combout ; +wire \ula_|ps2_keyboard_|clk_filter[0]~0_combout ; +wire \ula_|ps2_keyboard_|ps2_clk_in~0_combout ; +wire \ula_|ps2_keyboard_|ps2_clk_in~q ; +wire \ula_|ps2_keyboard_|clk_edge~0_combout ; +wire \ula_|ps2_keyboard_|clk_edge~q ; +wire \ula_|ps2_keyboard_|bit_count~1_combout ; +wire \ula_|ps2_keyboard_|bit_count~2_combout ; +wire \ula_|ps2_keyboard_|bit_count~0_combout ; +wire \ula_|ps2_keyboard_|always1~0_combout ; +wire \ula_|ps2_keyboard_|LessThan0~0_combout ; +wire \ula_|ps2_keyboard_|shiftreg[0]~0_combout ; +wire \ula_|ps2_keyboard_|shiftreg[7]~feeder_combout ; +wire \ula_|ps2_keyboard_|shiftreg[0]~feeder_combout ; +wire \ula_|ps2_keyboard_|WideXor0~0_combout ; +wire \ula_|ps2_keyboard_|WideXor0~1_combout ; +wire \ula_|ps2_keyboard_|WideXor0~2_combout ; +wire \ula_|ps2_keyboard_|scan_code_ready~0_combout ; +wire \ula_|ps2_keyboard_|scan_code_ready~q ; +wire \ula_|zx_keyboard_|Equal0~0_combout ; +wire \ula_|zx_keyboard_|Equal0~1_combout ; +wire \ula_|zx_keyboard_|released~0_combout ; +wire \ula_|zx_keyboard_|released~q ; +wire \ula_|zx_keyboard_|extended~0_combout ; +wire \ula_|zx_keyboard_|extended~q ; +wire \ula_|zx_keyboard_|keys[7][1]~21_combout ; +wire \ula_|zx_keyboard_|keys[5][4]~22_combout ; +wire \ula_|zx_keyboard_|keys[1][4]~23_combout ; +wire \ula_|zx_keyboard_|keys[2][1]~24_combout ; +wire \ula_|zx_keyboard_|keys[2][1]~25_combout ; +wire \ula_|zx_keyboard_|keys[2][1]~q ; +wire \ula_|zx_keyboard_|key_row~0_combout ; +wire \ula_|zx_keyboard_|keys[3][1]~26_combout ; +wire \ula_|zx_keyboard_|keys[3][1]~27_combout ; +wire \ula_|zx_keyboard_|keys[3][1]~28_combout ; +wire \ula_|zx_keyboard_|keys[3][1]~q ; +wire \z80_|address_pins_|DFFE_apin_latch[11]~11_combout ; +wire \z80_|address_pins_|abus[11]~19_combout ; +wire \ula_|zx_keyboard_|keys[7][4]~17_combout ; +wire \ula_|zx_keyboard_|keys[6][4]~18_combout ; +wire \ula_|zx_keyboard_|keys[1][1]~19_combout ; +wire \ula_|zx_keyboard_|keys[1][1]~20_combout ; +wire \ula_|zx_keyboard_|keys[1][1]~q ; +wire \z80_|address_pins_|DFFE_apin_latch[9]~9_combout ; +wire \z80_|address_pins_|abus[9]~17_combout ; +wire \ula_|zx_keyboard_|keys[0][0]~13_combout ; +wire \ula_|zx_keyboard_|shifted~2_combout ; +wire \ula_|zx_keyboard_|keys[0][1]~14_combout ; +wire \ula_|zx_keyboard_|keys[0][1]~15_combout ; +wire \ula_|zx_keyboard_|WideOr17~0_combout ; +wire \ula_|zx_keyboard_|shifted~5_combout ; +wire \ula_|zx_keyboard_|shifted~4_combout ; +wire \ula_|zx_keyboard_|shifted~q ; +wire \ula_|zx_keyboard_|keys[0][1]~12_combout ; +wire \ula_|zx_keyboard_|keys[0][1]~16_combout ; +wire \ula_|zx_keyboard_|keys[0][1]~q ; +wire \z80_|address_pins_|DFFE_apin_latch[8]~8_combout ; +wire \z80_|address_pins_|abus[8]~18_combout ; +wire \D[1]~26_combout ; +wire \D[1]~27_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[12]~12_combout ; +wire \z80_|address_pins_|abus[12]~21_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ; +wire \z80_|address_pins_|DFFE_apin_latch[13]~13_combout ; wire \z80_|address_pins_|abus[13]~20_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~36_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~34_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~35_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~33_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~37_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~q ; +wire \ula_|zx_keyboard_|keys[4][1]~29_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~30_combout ; +wire \ula_|zx_keyboard_|keys[5][2]~31_combout ; +wire \ula_|zx_keyboard_|keys[4][1]~32_combout ; +wire \ula_|zx_keyboard_|keys[4][1]~q ; +wire \D[1]~28_combout ; +wire \z80_|address_pins_|abus[0]~16_combout ; wire \z80_|address_pins_|DFFE_apin_latch[14]~14_combout ; wire \z80_|address_pins_|abus[14]~23_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~40_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~41_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~39_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~38_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~42_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~q ; +wire \ula_|zx_keyboard_|WideOr16~4_combout ; +wire \ula_|zx_keyboard_|WideOr16~2_combout ; +wire \ula_|zx_keyboard_|WideOr16~7_combout ; +wire \ula_|zx_keyboard_|WideOr16~5_combout ; +wire \ula_|zx_keyboard_|WideOr16~6_combout ; +wire \ula_|zx_keyboard_|keys[7][1]~43_combout ; +wire \ula_|zx_keyboard_|keys[7][1]~44_combout ; +wire \ula_|zx_keyboard_|keys[7][1]~q ; wire \z80_|address_pins_|DFFE_apin_latch[15]~15_combout ; wire \z80_|address_pins_|abus[15]~22_combout ; +wire \D[1]~29_combout ; +wire \D[1]~30_combout ; +wire \ExtRamWE~0_combout ; wire \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ; -wire \z80_|address_pins_|abus[0]~16_combout ; wire \z80_|address_pins_|DFFE_apin_latch[1]~1_combout ; wire \z80_|address_pins_|abus[1]~25_combout ; wire \z80_|address_pins_|DFFE_apin_latch[2]~2_combout ; @@ -1807,30 +1882,27 @@ wire \z80_|address_pins_|DFFE_apin_latch[6]~6_combout ; wire \z80_|address_pins_|abus[6]~30_combout ; wire \z80_|address_pins_|DFFE_apin_latch[7]~7_combout ; wire \z80_|address_pins_|abus[7]~31_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[8]~8_combout ; -wire \z80_|address_pins_|abus[8]~18_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[9]~9_combout ; -wire \z80_|address_pins_|abus[9]~17_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[10]~10_combout ; wire \z80_|address_pins_|abus[10]~24_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[11]~11_combout ; -wire \z80_|address_pins_|abus[11]~19_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[12]~12_combout ; -wire \z80_|address_pins_|abus[12]~21_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ; wire \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ; +wire \ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ; wire \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ; -wire \D[6]~90_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout ; wire \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ; -wire \D[6]~91_combout ; -wire \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ; wire \CLOCK_50~inputclkctrl_outclk ; +wire \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ; +wire \Selector3~0_combout ; +wire \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ; wire \~GND~combout ; wire \ula_|video_|vram_address[0]~feeder_combout ; wire \ula_|video_|vram_address~0_combout ; +wire \ula_|video_|vram_address[1]~feeder_combout ; wire \ula_|video_|vram_address[2]~4_combout ; wire \ula_|video_|Add3~0_combout ; wire \ula_|video_|Add3~1_combout ; @@ -1842,483 +1914,369 @@ wire \ula_|video_|Add4~7 ; wire \ula_|video_|Add4~8_combout ; wire \ula_|video_|Add4~9 ; wire \ula_|video_|Add4~10_combout ; +wire \ula_|video_|Add4~0_combout ; wire \ula_|video_|Add4~11 ; wire \ula_|video_|Add4~12_combout ; -wire \ula_|video_|Add4~0_combout ; wire \ula_|video_|Selector6~0_combout ; wire \ula_|video_|vram_address[9]~1_combout ; +wire \ula_|video_|Add4~2_combout ; wire \ula_|video_|Add4~13 ; wire \ula_|video_|Add4~14_combout ; -wire \ula_|video_|Add4~2_combout ; wire \ula_|video_|Selector5~0_combout ; wire \ula_|video_|Add4~4_combout ; wire \ula_|video_|vram_address[10]~2_combout ; wire \ula_|video_|vram_address[10]~3_combout ; wire \ula_|video_|Selector3~0_combout ; wire \ula_|video_|Selector2~0_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ; -wire \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ; -wire \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ; -wire \D[6]~87_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ; -wire \D[6]~88_combout ; -wire \D[6]~89_combout ; -wire \D[6]~111_combout ; -wire \raw_loader_in~input_o ; -wire \D[6]~86_combout ; -wire \D[6]~100_combout ; -wire \D[6]~101_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout ; +wire \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ; +wire \Selector1~0_combout ; +wire \Selector1~1_combout ; +wire \D[1]~81_combout ; +wire \D[1]~31_combout ; +wire \D[1]~32_combout ; wire \z80_|pin_control_|bus_db_pin_re~2_combout ; wire \z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ; -wire \z80_|bus_control_|db[6]~9_combout ; -wire \z80_|ir_|opcode[6]~feeder_combout ; -wire \z80_|execute_|ctl_ir_we~13_combout ; -wire \z80_|pla_decode_|Equal41~0_combout ; +wire \z80_|bus_control_|db[1]~11_combout ; +wire \z80_|pla_decode_|Equal2~0_combout ; +wire \z80_|execute_|ctl_mRead~15_combout ; +wire \z80_|execute_|ctl_inc_cy~39_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~36_combout ; +wire \z80_|execute_|ctl_sw_4u~4_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~16_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~17_combout ; +wire \z80_|execute_|ctl_sw_4u~5_combout ; +wire \z80_|execute_|ctl_sw_4u~6_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~44_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~43_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~46_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~47_combout ; +wire \z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~49_combout ; +wire \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~45_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~48_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~50_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~51_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~52_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ; +wire \z80_|execute_|ctl_flags_xy_we~15_combout ; +wire \z80_|execute_|ctl_flags_xy_we~16_combout ; +wire \z80_|execute_|ctl_flags_xy_we~17_combout ; +wire \z80_|execute_|ctl_flags_xy_we~18_combout ; +wire \z80_|alu_flags_|flags_xf~q ; +wire \z80_|alu_control_|db[3]~33_combout ; +wire \z80_|sw1_|db_down[3]~2_combout ; +wire \z80_|alu_control_|db[3]~34_combout ; +wire \z80_|alu_control_|db[3]~35_combout ; +wire \ula_|zx_keyboard_|keys[3][0]~75_combout ; +wire \ula_|zx_keyboard_|Selector5~0_combout ; +wire \ula_|zx_keyboard_|Selector5~1_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~132_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~106_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~107_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~133_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~108_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~q ; +wire \ula_|zx_keyboard_|keys[5][3]~104_combout ; +wire \ula_|zx_keyboard_|keys[5][3]~105_combout ; +wire \ula_|zx_keyboard_|keys[5][3]~q ; +wire \D[3]~55_combout ; +wire \ula_|zx_keyboard_|keys[6][4]~46_combout ; +wire \ula_|zx_keyboard_|keys[5][4]~62_combout ; +wire \ula_|zx_keyboard_|keys[3][3]~102_combout ; +wire \ula_|zx_keyboard_|keys[3][3]~103_combout ; +wire \ula_|zx_keyboard_|keys[3][3]~q ; +wire \ula_|zx_keyboard_|keys[0][4]~96_combout ; +wire \ula_|zx_keyboard_|keys[2][4]~94_combout ; +wire \ula_|zx_keyboard_|keys[0][3]~95_combout ; +wire \ula_|zx_keyboard_|keys[0][3]~97_combout ; +wire \ula_|zx_keyboard_|keys[0][3]~q ; +wire \ula_|zx_keyboard_|keys[6][4]~45_combout ; +wire \ula_|zx_keyboard_|keys[1][3]~92_combout ; +wire \ula_|zx_keyboard_|keys[1][3]~93_combout ; +wire \ula_|zx_keyboard_|keys[1][3]~q ; +wire \D[3]~53_combout ; +wire \ula_|zx_keyboard_|keys[2][3]~99_combout ; +wire \ula_|zx_keyboard_|keys[2][3]~100_combout ; +wire \ula_|zx_keyboard_|keys[2][3]~98_combout ; +wire \ula_|zx_keyboard_|keys[2][3]~101_combout ; +wire \ula_|zx_keyboard_|keys[2][3]~q ; +wire \ula_|zx_keyboard_|key_row~3_combout ; +wire \D[3]~54_combout ; +wire \ula_|zx_keyboard_|keys[0][4]~109_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~60_combout ; +wire \ula_|zx_keyboard_|keys[7][3]~110_combout ; +wire \ula_|zx_keyboard_|keys[7][3]~111_combout ; +wire \ula_|zx_keyboard_|keys[7][3]~112_combout ; +wire \ula_|zx_keyboard_|keys[7][3]~q ; +wire \ula_|zx_keyboard_|Selector13~0_combout ; +wire \ula_|zx_keyboard_|keys[6][3]~113_combout ; +wire \ula_|zx_keyboard_|keys[6][3]~114_combout ; +wire \ula_|zx_keyboard_|keys[6][3]~135_combout ; +wire \ula_|zx_keyboard_|keys[6][3]~136_combout ; +wire \ula_|zx_keyboard_|keys[6][3]~q ; +wire \D[3]~56_combout ; +wire \D[3]~57_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ; +wire \Selector3~1_combout ; +wire \Selector3~2_combout ; +wire \D[3]~85_combout ; +wire \D[3]~73_combout ; +wire \D[3]~74_combout ; +wire \z80_|bus_control_|db[3]~20_combout ; +wire \z80_|bus_control_|db[3]~21_combout ; +wire \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ; +wire \z80_|interrupts_|im2~q ; +wire \z80_|execute_|ctl_mRead~10_combout ; +wire \z80_|execute_|ctl_sw_mask543_en~0_combout ; +wire \z80_|alu_control_|db[7]~16_combout ; +wire \z80_|alu_control_|db[7]~17_combout ; +wire \z80_|alu_control_|db[7]~18_combout ; +wire \z80_|alu_control_|db[7]~19_combout ; +wire \z80_|bus_control_|db[7]~5_combout ; +wire \D[5]~67_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout ; +wire \Mux0~0_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ; +wire \Mux0~1_combout ; +wire \D[7]~89_combout ; +wire \D[7]~72_combout ; +wire \D[0]~84_combout ; +wire \D[7]~80_combout ; +wire \z80_|bus_control_|db[7]~7_combout ; +wire \z80_|pla_decode_|Equal6~0_combout ; +wire \z80_|pla_decode_|Equal12~0_combout ; +wire \z80_|execute_|ctl_mRead~16_combout ; +wire \z80_|execute_|fMRead~24_combout ; +wire \z80_|execute_|fMRead~25_combout ; +wire \z80_|execute_|ctl_mRead~21_combout ; +wire \z80_|execute_|fMRead~16_combout ; +wire \z80_|execute_|fMRead~14_combout ; +wire \z80_|execute_|fMRead~15_combout ; +wire \z80_|execute_|fMRead~12_combout ; +wire \z80_|execute_|fMRead~11_combout ; +wire \z80_|execute_|fMRead~13_combout ; +wire \z80_|execute_|fMRead~17_combout ; +wire \z80_|execute_|fMRead~22_combout ; +wire \z80_|execute_|fMRead~27_combout ; +wire \z80_|execute_|fMRead~37_combout ; +wire \z80_|execute_|fMRead~31_combout ; +wire \z80_|execute_|fMRead~29_combout ; +wire \z80_|execute_|fMRead~30_combout ; +wire \z80_|execute_|fMRead~28_combout ; +wire \z80_|execute_|fMRead~32_combout ; +wire \z80_|execute_|fMRead~33_combout ; +wire \z80_|execute_|fMRead~23_combout ; +wire \z80_|execute_|fMRead~34_combout ; +wire \z80_|execute_|fMRead~35_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~19_combout ; +wire \z80_|execute_|fMRead~36_combout ; +wire \z80_|pin_control_|bus_db_pin_re~combout ; +wire \ula_|zx_keyboard_|keys[2][4]~118_combout ; +wire \ula_|zx_keyboard_|keys[2][4]~119_combout ; +wire \ula_|zx_keyboard_|keys[2][4]~120_combout ; +wire \ula_|zx_keyboard_|keys[2][4]~q ; +wire \ula_|zx_keyboard_|keys[3][4]~129_combout ; +wire \ula_|zx_keyboard_|keys[3][4]~116_combout ; +wire \ula_|zx_keyboard_|keys[3][4]~134_combout ; +wire \ula_|zx_keyboard_|keys[3][4]~117_combout ; +wire \ula_|zx_keyboard_|keys[3][4]~q ; +wire \D[4]~60_combout ; +wire \ula_|zx_keyboard_|Equal0~2_combout ; +wire \ula_|zx_keyboard_|keys[1][4]~121_combout ; +wire \ula_|zx_keyboard_|keys[1][4]~q ; +wire \ula_|zx_keyboard_|keys[0][4]~115_combout ; +wire \ula_|zx_keyboard_|keys[0][4]~q ; +wire \ula_|zx_keyboard_|key_row~4_combout ; +wire \D[4]~61_combout ; +wire \ula_|zx_keyboard_|keys[4][4]~124_combout ; +wire \ula_|zx_keyboard_|keys[4][4]~125_combout ; +wire \ula_|zx_keyboard_|keys[4][4]~126_combout ; +wire \ula_|zx_keyboard_|keys[4][4]~q ; +wire \ula_|zx_keyboard_|keys[5][4]~122_combout ; +wire \ula_|zx_keyboard_|keys[5][4]~123_combout ; +wire \ula_|zx_keyboard_|keys[5][4]~q ; +wire \D[4]~62_combout ; +wire \ula_|zx_keyboard_|keys[7][4]~49_combout ; +wire \ula_|zx_keyboard_|shifted~3_combout ; +wire \ula_|zx_keyboard_|keys[7][4]~127_combout ; +wire \ula_|zx_keyboard_|keys[7][4]~q ; +wire \ula_|zx_keyboard_|keys[6][4]~128_combout ; +wire \ula_|zx_keyboard_|keys[6][4]~q ; +wire \D[4]~63_combout ; +wire \D[4]~64_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ; +wire \Selector4~0_combout ; +wire \Selector4~1_combout ; +wire \D[4]~86_combout ; +wire \D[4]~75_combout ; +wire \D[4]~76_combout ; +wire \z80_|bus_control_|db[4]~18_combout ; +wire \z80_|bus_control_|db[4]~19_combout ; +wire \z80_|pla_decode_|Equal32~0_combout ; wire \z80_|pla_decode_|Equal41~1_combout ; wire \z80_|pla_decode_|Equal41~2_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~combout ; -wire \z80_|alu_|db_high[1]~15_combout ; -wire \z80_|alu_|db_high[1]~16_combout ; -wire \z80_|alu_|db_high[1]~17_combout ; -wire \z80_|alu_|db_high[1]~18_combout ; -wire \z80_|alu_|db_high[1]~19_combout ; -wire \z80_|alu_|db_high[1]~20_combout ; +wire \z80_|pla_decode_|Equal36~0_combout ; +wire \z80_|execute_|ctl_state_tbl_cb_set~combout ; +wire \z80_|execute_|ctl_state_tbl_we~8_combout ; +wire \z80_|decode_state_|DFFE_instCB~q ; +wire \z80_|pla_decode_|Equal52~0_combout ; +wire \z80_|pla_decode_|Equal2~1_combout ; +wire \z80_|execute_|ctl_state_tbl_ed_set~combout ; +wire \z80_|decode_state_|DFFE_instED~q ; +wire \z80_|decode_state_|table_xx~0_combout ; +wire \z80_|pla_decode_|Equal34~0_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~6_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~5_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~4_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~2_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~3_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~7_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~8_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~9_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~10_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~16_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~17_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~15_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~18_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~19_combout ; +wire \z80_|reg_control_|reg_sel_pc~3_combout ; +wire \z80_|reg_control_|reg_sel_pc~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ; +wire \z80_|reg_file_|db_hi_as[0]~2_combout ; +wire \z80_|reg_file_|db_hi_as[5]~13_combout ; +wire \z80_|reg_file_|db_hi_as[5]~14_combout ; +wire \z80_|reg_file_|db_hi_as[5]~15_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~50_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~53_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~54_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~52_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~51_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~55_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[5]~14_combout ; +wire \z80_|reg_file_|b2v_latch_de_hi|latch[5]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~49_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~56_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~57_combout ; +wire \z80_|alu_|db[5]~23_combout ; wire \z80_|alu_|db[5]~24_combout ; -wire \z80_|alu_|db[5]~25_combout ; wire \z80_|sw1_|db_down[5]~0_combout ; wire \z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout ; wire \z80_|alu_flags_|flags_yf~q ; wire \z80_|alu_control_|db[5]~13_combout ; wire \z80_|alu_control_|db[5]~14_combout ; wire \z80_|alu_control_|db[5]~15_combout ; -wire \D[0]~107_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ; wire \ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ; wire \ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout ; wire \rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ; wire \rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout ; wire \Mux2~0_combout ; wire \Mux2~1_combout ; -wire \D[5]~110_combout ; -wire \D[5]~85_combout ; -wire \D[5]~99_combout ; +wire \D[5]~87_combout ; +wire \D[5]~68_combout ; +wire \D[5]~77_combout ; wire \z80_|bus_control_|db[5]~14_combout ; wire \z80_|bus_control_|db[5]~15_combout ; -wire \z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout ; -wire \z80_|decode_state_|DFFE_inst4~q ; -wire \z80_|decode_state_|use_ixiy~combout ; -wire \z80_|execute_|ctl_mRead~23_combout ; -wire \z80_|execute_|fMRead~34_combout ; -wire \z80_|execute_|fMRead~31_combout ; -wire \z80_|execute_|fMRead~29_combout ; -wire \z80_|execute_|fMRead~30_combout ; -wire \z80_|execute_|fMRead~28_combout ; -wire \z80_|execute_|fMRead~32_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~42_combout ; -wire \z80_|execute_|fMRead~14_combout ; -wire \z80_|execute_|fMRead~10_combout ; -wire \z80_|execute_|fMRead~9_combout ; -wire \z80_|execute_|fMRead~11_combout ; -wire \z80_|execute_|fMRead~12_combout ; -wire \z80_|execute_|fMRead~13_combout ; -wire \z80_|execute_|fMRead~15_combout ; -wire \z80_|execute_|fMRead~20_combout ; -wire \z80_|execute_|pc_inc_hold~48_combout ; -wire \z80_|execute_|fMRead~22_combout ; -wire \z80_|execute_|fMRead~21_combout ; -wire \z80_|execute_|fMRead~23_combout ; -wire \z80_|execute_|fMRead~26_combout ; -wire \z80_|execute_|fMRead~25_combout ; -wire \z80_|execute_|fMRead~27_combout ; -wire \z80_|execute_|fMRead~33_combout ; -wire \z80_|execute_|fMRead~35_combout ; -wire \z80_|pin_control_|bus_db_pin_re~combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ; -wire \Selector1~0_combout ; -wire \Selector1~1_combout ; -wire \D[1]~103_combout ; -wire \PS2_DAT~input_o ; -wire \reset~clkctrl_outclk ; -wire \ula_|ps2_keyboard_|bit_count~0_combout ; -wire \PS2_CLK~input_o ; -wire \ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ; -wire \ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ; -wire \ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ; -wire \ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ; -wire \ula_|ps2_keyboard_|Equal0~0_combout ; -wire \ula_|ps2_keyboard_|clk_filter[3]~feeder_combout ; -wire \ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ; -wire \ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ; -wire \ula_|ps2_keyboard_|Equal0~1_combout ; -wire \ula_|ps2_keyboard_|clk_filter[0]~0_combout ; -wire \ula_|ps2_keyboard_|ps2_clk_in~0_combout ; -wire \ula_|ps2_keyboard_|ps2_clk_in~q ; -wire \ula_|ps2_keyboard_|clk_edge~0_combout ; -wire \ula_|ps2_keyboard_|clk_edge~q ; -wire \ula_|ps2_keyboard_|bit_count~1_combout ; -wire \ula_|ps2_keyboard_|bit_count~3_combout ; -wire \ula_|ps2_keyboard_|bit_count~2_combout ; -wire \ula_|ps2_keyboard_|always1~0_combout ; -wire \ula_|ps2_keyboard_|LessThan0~0_combout ; -wire \ula_|ps2_keyboard_|shiftreg[0]~0_combout ; -wire \ula_|zx_keyboard_|Equal0~0_combout ; -wire \ula_|zx_keyboard_|Equal0~1_combout ; -wire \ula_|zx_keyboard_|extended~0_combout ; -wire \ula_|ps2_keyboard_|WideXor0~1_combout ; -wire \ula_|ps2_keyboard_|WideXor0~0_combout ; -wire \ula_|ps2_keyboard_|WideXor0~2_combout ; -wire \ula_|ps2_keyboard_|scan_code_ready~0_combout ; -wire \ula_|ps2_keyboard_|scan_code_ready~q ; -wire \ula_|zx_keyboard_|extended~q ; -wire \ula_|zx_keyboard_|keys[0][0]~15_combout ; -wire \ula_|zx_keyboard_|keys[5][1]~36_combout ; -wire \ula_|zx_keyboard_|keys[5][1]~37_combout ; -wire \ula_|zx_keyboard_|shifted~0_combout ; -wire \ula_|zx_keyboard_|released~0_combout ; -wire \ula_|zx_keyboard_|released~q ; -wire \ula_|zx_keyboard_|WideOr17~0_combout ; -wire \ula_|zx_keyboard_|shifted~2_combout ; -wire \ula_|zx_keyboard_|shifted~3_combout ; -wire \ula_|zx_keyboard_|shifted~q ; -wire \ula_|zx_keyboard_|keys[5][1]~35_combout ; -wire \ula_|zx_keyboard_|keys[5][1]~38_combout ; -wire \ula_|zx_keyboard_|keys[5][1]~39_combout ; -wire \ula_|zx_keyboard_|keys[5][1]~q ; -wire \ula_|zx_keyboard_|keys[4][1]~31_combout ; -wire \ula_|zx_keyboard_|keys[7][1]~23_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~32_combout ; -wire \ula_|zx_keyboard_|keys[5][2]~33_combout ; -wire \ula_|zx_keyboard_|keys[4][1]~34_combout ; -wire \ula_|zx_keyboard_|keys[4][1]~q ; -wire \D[1]~30_combout ; -wire \ula_|zx_keyboard_|keys[5][4]~24_combout ; -wire \ula_|zx_keyboard_|keys[3][1]~28_combout ; -wire \ula_|zx_keyboard_|keys[3][1]~29_combout ; -wire \ula_|zx_keyboard_|keys[3][1]~30_combout ; -wire \ula_|zx_keyboard_|keys[3][1]~q ; -wire \ula_|zx_keyboard_|keys[1][4]~25_combout ; -wire \ula_|zx_keyboard_|keys[2][1]~26_combout ; -wire \ula_|zx_keyboard_|keys[2][1]~27_combout ; -wire \ula_|zx_keyboard_|keys[2][1]~q ; -wire \ula_|zx_keyboard_|key_row~0_combout ; -wire \ula_|zx_keyboard_|keys[0][1]~14_combout ; -wire \ula_|zx_keyboard_|keys[0][1]~16_combout ; -wire \ula_|zx_keyboard_|keys[0][1]~17_combout ; -wire \ula_|zx_keyboard_|keys[0][1]~18_combout ; -wire \ula_|zx_keyboard_|keys[0][1]~q ; -wire \ula_|zx_keyboard_|keys[7][4]~19_combout ; -wire \ula_|zx_keyboard_|keys[6][4]~20_combout ; -wire \ula_|zx_keyboard_|keys[1][1]~21_combout ; -wire \ula_|zx_keyboard_|keys[1][1]~22_combout ; -wire \ula_|zx_keyboard_|keys[1][1]~q ; -wire \D[1]~28_combout ; -wire \D[1]~29_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~41_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~42_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~43_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~40_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~44_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~q ; -wire \ula_|zx_keyboard_|keys[7][1]~45_combout ; -wire \ula_|zx_keyboard_|WideOr16~5_combout ; -wire \ula_|zx_keyboard_|WideOr16~2_combout ; -wire \ula_|zx_keyboard_|WideOr16~4_combout ; -wire \ula_|zx_keyboard_|WideOr16~7_combout ; -wire \ula_|zx_keyboard_|WideOr16~6_combout ; -wire \ula_|zx_keyboard_|keys[7][1]~46_combout ; -wire \ula_|zx_keyboard_|keys[7][1]~q ; -wire \D[1]~31_combout ; -wire \D[1]~32_combout ; -wire \D[1]~33_combout ; -wire \D[1]~34_combout ; -wire \z80_|bus_control_|db[1]~10_combout ; -wire \z80_|bus_control_|db[1]~11_combout ; -wire \z80_|ir_|opcode[1]~feeder_combout ; -wire \z80_|pla_decode_|Equal40~0_combout ; -wire \z80_|pla_decode_|Equal21~1_combout ; -wire \z80_|execute_|ctl_alu_op_low~26_combout ; -wire \z80_|execute_|ctl_alu_op_low~28_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~3_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~2_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~21_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ; -wire \z80_|execute_|ctl_alu_op_low~32_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~19_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf2~q ; -wire \z80_|execute_|ctl_flags_use_cf2~10_combout ; -wire \z80_|execute_|ctl_flags_use_cf2~11_combout ; -wire \z80_|execute_|ctl_flags_use_cf2~8_combout ; -wire \z80_|execute_|ctl_flags_use_cf2~9_combout ; -wire \z80_|execute_|ctl_flags_use_cf2~12_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~20_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~10_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~8_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~5_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~6_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~7_combout ; -wire \z80_|execute_|ctl_flags_cf_set~0_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~4_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~9_combout ; -wire \z80_|alu_flags_|flags_cf~combout ; -wire \z80_|alu_control_|db[0]~8_combout ; -wire \z80_|sw2_|db_up[0]~0_combout ; -wire \z80_|alu_control_|db[0]~9_combout ; -wire \z80_|alu_control_|db[0]~12_combout ; -wire \ula_|zx_keyboard_|keys[5][0]~67_combout ; -wire \ula_|zx_keyboard_|keys[5][0]~81_combout ; -wire \ula_|zx_keyboard_|keys[5][0]~82_combout ; -wire \ula_|zx_keyboard_|keys[5][0]~83_combout ; -wire \ula_|zx_keyboard_|keys[5][0]~q ; -wire \ula_|zx_keyboard_|keys[4][0]~84_combout ; -wire \ula_|zx_keyboard_|keys[4][0]~85_combout ; -wire \ula_|zx_keyboard_|keys[4][0]~86_combout ; -wire \ula_|zx_keyboard_|keys[4][0]~q ; -wire \D[0]~49_combout ; -wire \ula_|zx_keyboard_|WideOr4~0_combout ; -wire \ula_|zx_keyboard_|keys~76_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~73_combout ; -wire \ula_|zx_keyboard_|keys[6][4]~47_combout ; -wire \ula_|zx_keyboard_|WideOr0~0_combout ; -wire \ula_|zx_keyboard_|keys~74_combout ; -wire \ula_|zx_keyboard_|keys[0][0]~75_combout ; -wire \ula_|zx_keyboard_|keys[0][0]~77_combout ; -wire \ula_|zx_keyboard_|keys[0][0]~q ; -wire \ula_|zx_keyboard_|keys[1][0]~71_combout ; -wire \ula_|zx_keyboard_|keys[1][0]~72_combout ; -wire \ula_|zx_keyboard_|keys[1][0]~q ; -wire \D[0]~47_combout ; -wire \ula_|zx_keyboard_|keys[2][0]~80_combout ; -wire \ula_|zx_keyboard_|keys[2][0]~q ; -wire \ula_|zx_keyboard_|keys[3][0]~78_combout ; -wire \ula_|zx_keyboard_|keys[3][0]~79_combout ; -wire \ula_|zx_keyboard_|keys[3][0]~q ; -wire \ula_|zx_keyboard_|key_row~1_combout ; -wire \D[0]~48_combout ; -wire \ula_|zx_keyboard_|shifted~1_combout ; -wire \ula_|zx_keyboard_|keys[6][0]~90_combout ; -wire \ula_|zx_keyboard_|keys[6][0]~91_combout ; -wire \ula_|zx_keyboard_|keys[6][0]~92_combout ; -wire \ula_|zx_keyboard_|keys[6][0]~q ; -wire \ula_|zx_keyboard_|keys[5][4]~63_combout ; -wire \ula_|zx_keyboard_|WideOr16~3_combout ; -wire \ula_|zx_keyboard_|keys[7][0]~87_combout ; -wire \ula_|zx_keyboard_|keys[7][0]~132_combout ; -wire \ula_|zx_keyboard_|keys[7][0]~88_combout ; -wire \ula_|zx_keyboard_|keys[7][0]~89_combout ; -wire \ula_|zx_keyboard_|keys[7][0]~q ; -wire \D[0]~50_combout ; -wire \D[0]~51_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ; -wire \D[0]~55_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ; -wire \D[0]~56_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ; -wire \D[0]~52_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ; -wire \D[0]~53_combout ; -wire \D[0]~54_combout ; -wire \D[0]~106_combout ; -wire \D[0]~57_combout ; -wire \D[0]~58_combout ; -wire \z80_|bus_control_|db[0]~16_combout ; -wire \z80_|bus_control_|db[0]~17_combout ; -wire \z80_|pla_decode_|Equal63~0_combout ; -wire \z80_|execute_|ctl_flags_cf2_sel_daa~combout ; -wire \z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ; -wire \z80_|alu_control_|db[6]~10_combout ; -wire \z80_|alu_control_|db[6]~11_combout ; -wire \z80_|alu_control_|db[4]~30_combout ; -wire \z80_|alu_control_|db[4]~31_combout ; -wire \z80_|alu_control_|db[4]~32_combout ; -wire \ula_|zx_keyboard_|keys[2][4]~119_combout ; -wire \ula_|zx_keyboard_|keys[2][4]~120_combout ; -wire \ula_|zx_keyboard_|keys[2][4]~95_combout ; -wire \ula_|zx_keyboard_|keys[2][4]~121_combout ; -wire \ula_|zx_keyboard_|keys[2][4]~q ; -wire \ula_|zx_keyboard_|keys[3][4]~117_combout ; -wire \ula_|zx_keyboard_|keys[3][4]~136_combout ; -wire \ula_|zx_keyboard_|keys[3][4]~130_combout ; -wire \ula_|zx_keyboard_|keys[3][4]~118_combout ; -wire \ula_|zx_keyboard_|keys[3][4]~q ; -wire \D[4]~78_combout ; -wire \ula_|zx_keyboard_|keys[6][4]~126_combout ; -wire \ula_|zx_keyboard_|keys[5][4]~128_combout ; -wire \ula_|zx_keyboard_|keys[5][4]~129_combout ; -wire \ula_|zx_keyboard_|keys[5][4]~q ; -wire \ula_|zx_keyboard_|keys[6][4]~127_combout ; -wire \ula_|zx_keyboard_|keys[6][4]~q ; -wire \ula_|zx_keyboard_|Equal0~2_combout ; -wire \ula_|zx_keyboard_|keys[7][4]~51_combout ; -wire \ula_|zx_keyboard_|keys[7][4]~125_combout ; -wire \ula_|zx_keyboard_|keys[7][4]~q ; -wire \D[4]~79_combout ; -wire \ula_|zx_keyboard_|keys[4][4]~122_combout ; -wire \ula_|zx_keyboard_|keys[4][4]~123_combout ; -wire \ula_|zx_keyboard_|keys[4][4]~124_combout ; -wire \ula_|zx_keyboard_|keys[4][4]~q ; -wire \ula_|zx_keyboard_|key_row~3_combout ; -wire \D[4]~80_combout ; -wire \ula_|zx_keyboard_|keys[0][4]~111_combout ; -wire \ula_|zx_keyboard_|keys[0][4]~97_combout ; -wire \ula_|zx_keyboard_|keys[0][4]~116_combout ; -wire \ula_|zx_keyboard_|keys[0][4]~q ; -wire \ula_|zx_keyboard_|keys[1][4]~115_combout ; -wire \ula_|zx_keyboard_|keys[1][4]~q ; -wire \D[4]~77_combout ; -wire \D[4]~81_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout ; -wire \Selector4~0_combout ; -wire \Selector4~1_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2_combout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3_combout ; -wire \D[4]~109_combout ; -wire \D[4]~97_combout ; -wire \D[4]~98_combout ; -wire \z80_|bus_control_|db[4]~18_combout ; -wire \z80_|bus_control_|db[4]~19_combout ; -wire \z80_|pla_decode_|Equal21~0_combout ; -wire \z80_|execute_|ctl_mRead~5_combout ; -wire \z80_|execute_|fIOWrite~2_combout ; -wire \z80_|execute_|fIOWrite~3_combout ; -wire \z80_|execute_|fIOWrite~4_combout ; -wire \z80_|execute_|fIOWrite~5_combout ; -wire \z80_|execute_|ctl_mWrite~11_combout ; -wire \z80_|execute_|ctl_mWrite~12_combout ; -wire \z80_|execute_|ctl_mWrite~13_combout ; -wire \z80_|execute_|ctl_mWrite~14_combout ; -wire \z80_|execute_|ctl_mWrite~15_combout ; -wire \z80_|memory_ifc_|DFFE_mwr_ff1~q ; -wire \z80_|memory_ifc_|wait_mwr~feeder_combout ; -wire \z80_|memory_ifc_|wait_mwr~q ; -wire \z80_|memory_ifc_|mwr_wr~q ; -wire \z80_|memory_ifc_|nWR_out~0_combout ; -wire \D[5]~84_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout ; -wire \Mux0~0_combout ; -wire \Mux0~1_combout ; -wire \D[7]~112_combout ; -wire \D[7]~94_combout ; -wire \D[7]~102_combout ; -wire \z80_|bus_control_|db[7]~5_combout ; -wire \z80_|bus_control_|db[7]~7_combout ; -wire \z80_|pla_decode_|Equal77~0_combout ; -wire \z80_|execute_|ctl_mWrite~5_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ; -wire \z80_|execute_|ctl_bus_db_we~3_combout ; +wire \z80_|execute_|ctl_mRead~8_combout ; wire \z80_|execute_|ctl_bus_db_we~8_combout ; -wire \z80_|execute_|ctl_bus_db_we~2_combout ; wire \z80_|execute_|ctl_bus_db_we~4_combout ; wire \z80_|execute_|ctl_bus_db_we~6_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ; +wire \z80_|execute_|ctl_bus_db_we~3_combout ; +wire \z80_|execute_|ctl_bus_db_we~2_combout ; wire \z80_|execute_|ctl_bus_db_we~7_combout ; -wire \ula_|zx_keyboard_|keys[0][2]~50_combout ; -wire \ula_|zx_keyboard_|keys[0][2]~52_combout ; -wire \ula_|zx_keyboard_|keys[0][2]~q ; -wire \ula_|zx_keyboard_|keys[3][3]~48_combout ; -wire \ula_|zx_keyboard_|keys[1][2]~49_combout ; -wire \ula_|zx_keyboard_|keys[1][2]~q ; -wire \D[2]~35_combout ; -wire \ula_|zx_keyboard_|keys[5][2]~57_combout ; -wire \ula_|zx_keyboard_|keys[5][2]~58_combout ; -wire \ula_|zx_keyboard_|keys[5][2]~q ; -wire \ula_|zx_keyboard_|keys[4][2]~59_combout ; -wire \ula_|zx_keyboard_|keys[4][2]~131_combout ; -wire \ula_|zx_keyboard_|keys[4][2]~60_combout ; -wire \ula_|zx_keyboard_|keys[4][2]~q ; -wire \D[2]~37_combout ; -wire \ula_|zx_keyboard_|keys[3][2]~53_combout ; -wire \ula_|zx_keyboard_|keys[2][2]~55_combout ; -wire \ula_|zx_keyboard_|keys[2][2]~56_combout ; -wire \ula_|zx_keyboard_|keys[2][2]~q ; -wire \ula_|zx_keyboard_|keys[3][2]~54_combout ; -wire \ula_|zx_keyboard_|keys[3][2]~q ; -wire \D[2]~36_combout ; -wire \ula_|zx_keyboard_|keys[6][2]~68_combout ; -wire \ula_|zx_keyboard_|keys[6][2]~69_combout ; -wire \ula_|zx_keyboard_|keys[6][2]~70_combout ; -wire \ula_|zx_keyboard_|keys[6][2]~q ; -wire \ula_|zx_keyboard_|keys[7][2]~61_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~62_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~64_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~65_combout ; -wire \ula_|zx_keyboard_|Selector13~0_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~66_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~q ; -wire \D[2]~38_combout ; -wire \D[2]~39_combout ; -wire \D[2]~104_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ; -wire \D[2]~43_combout ; -wire \D[2]~44_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout ; -wire \D[2]~40_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ; -wire \D[2]~41_combout ; -wire \D[2]~42_combout ; -wire \D[2]~105_combout ; -wire \D[2]~45_combout ; -wire \D[2]~46_combout ; -wire \z80_|bus_control_|db[2]~12_combout ; -wire \z80_|bus_control_|db[2]~13_combout ; -wire \z80_|pla_decode_|Equal3~1_combout ; +wire \ula_|zx_keyboard_|keys[5][0]~66_combout ; +wire \ula_|zx_keyboard_|keys[5][0]~80_combout ; +wire \ula_|zx_keyboard_|keys[5][0]~81_combout ; +wire \ula_|zx_keyboard_|keys[5][0]~82_combout ; +wire \ula_|zx_keyboard_|keys[5][0]~q ; +wire \ula_|zx_keyboard_|keys[4][0]~84_combout ; +wire \ula_|zx_keyboard_|keys[4][0]~83_combout ; +wire \ula_|zx_keyboard_|keys[4][0]~85_combout ; +wire \ula_|zx_keyboard_|keys[4][0]~q ; +wire \D[0]~42_combout ; +wire \ula_|zx_keyboard_|keys[1][0]~78_combout ; +wire \ula_|zx_keyboard_|keys[1][0]~79_combout ; +wire \ula_|zx_keyboard_|keys[1][0]~q ; +wire \ula_|zx_keyboard_|keys[3][0]~76_combout ; +wire \ula_|zx_keyboard_|keys[3][0]~q ; +wire \ula_|zx_keyboard_|keys[2][0]~77_combout ; +wire \ula_|zx_keyboard_|keys[2][0]~q ; +wire \D[0]~40_combout ; +wire \ula_|zx_keyboard_|WideOr0~0_combout ; +wire \ula_|zx_keyboard_|keys~71_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~70_combout ; +wire \ula_|zx_keyboard_|keys[0][0]~72_combout ; +wire \ula_|zx_keyboard_|WideOr4~0_combout ; +wire \ula_|zx_keyboard_|keys~73_combout ; +wire \ula_|zx_keyboard_|keys[0][0]~74_combout ; +wire \ula_|zx_keyboard_|keys[0][0]~q ; +wire \ula_|zx_keyboard_|key_row~2_combout ; +wire \D[0]~41_combout ; +wire \ula_|zx_keyboard_|keys[6][0]~89_combout ; +wire \ula_|zx_keyboard_|keys[6][0]~90_combout ; +wire \ula_|zx_keyboard_|keys[6][0]~91_combout ; +wire \ula_|zx_keyboard_|keys[6][0]~q ; +wire \ula_|zx_keyboard_|keys[7][0]~131_combout ; +wire \ula_|zx_keyboard_|WideOr16~3_combout ; +wire \ula_|zx_keyboard_|keys[7][0]~86_combout ; +wire \ula_|zx_keyboard_|keys[7][0]~87_combout ; +wire \ula_|zx_keyboard_|keys[7][0]~88_combout ; +wire \ula_|zx_keyboard_|keys[7][0]~q ; +wire \D[0]~43_combout ; +wire \D[0]~44_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4_combout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~5_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ; +wire \Selector2~0_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ; +wire \Selector2~1_combout ; +wire \D[0]~83_combout ; +wire \D[0]~45_combout ; +wire \D[0]~46_combout ; +wire \z80_|bus_control_|db[0]~16_combout ; +wire \z80_|bus_control_|db[0]~17_combout ; +wire \z80_|pla_decode_|Equal3~2_combout ; wire \z80_|pla_decode_|Equal43~0_combout ; wire \z80_|interrupts_|test1~2_combout ; wire \z80_|interrupts_|test1~3_combout ; @@ -2326,154 +2284,184 @@ wire \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ; wire \z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout ; wire \z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ; wire \z80_|clk_delay_|hold_clk_iorq~combout ; -wire \z80_|sequencer_|DFFE_T1_ff~q ; -wire \z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ; -wire \z80_|sequencer_|DFFE_T2_ff~q ; -wire \z80_|resets_|x3~combout ; -wire \z80_|resets_|SYNTHESIZED_WIRE_12~q ; -wire \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ; -wire \z80_|sequencer_|DFFE_M1_ff~q ; -wire \z80_|sequencer_|DFFE_M2_ff~0_combout ; -wire \z80_|sequencer_|DFFE_M2_ff~q ; -wire \z80_|execute_|ctl_mWrite~3_combout ; -wire \z80_|execute_|nextM~11_combout ; +wire \z80_|sequencer_|DFFE_T4_ff~q ; +wire \z80_|execute_|ctl_eval_cond~0_combout ; +wire \z80_|execute_|ctl_mRead~27_combout ; +wire \z80_|execute_|ctl_mRead~26_combout ; +wire \z80_|execute_|ctl_mRead~28_combout ; +wire \z80_|execute_|nextM~6_combout ; +wire \z80_|execute_|nextM~7_combout ; wire \z80_|execute_|nextM~8_combout ; wire \z80_|execute_|nextM~9_combout ; wire \z80_|execute_|nextM~10_combout ; wire \z80_|execute_|nextM~12_combout ; wire \z80_|execute_|nextM~15_combout ; -wire \z80_|execute_|nextM~6_combout ; -wire \z80_|execute_|nextM~7_combout ; wire \z80_|execute_|nextM~13_combout ; -wire \z80_|execute_|setM1~39_combout ; +wire \z80_|execute_|setM1~41_combout ; wire \z80_|execute_|nextM~5_combout ; wire \z80_|execute_|nextM~14_combout ; -wire \z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ; -wire \z80_|sequencer_|DFFE_T4_ff~q ; -wire \z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ; -wire \z80_|sequencer_|DFFE_T5_ff~q ; -wire \z80_|sequencer_|SYNTHESIZED_WIRE_17~combout ; -wire \z80_|sequencer_|T6~q ; -wire \z80_|execute_|setM1~13_combout ; -wire \z80_|pla_decode_|Equal77~1_combout ; -wire \z80_|execute_|setM1~12_combout ; -wire \z80_|execute_|setM1~14_combout ; -wire \z80_|execute_|setM1~41_combout ; -wire \z80_|execute_|setM1~42_combout ; -wire \z80_|execute_|setM1~43_combout ; -wire \z80_|execute_|setM1~44_combout ; -wire \z80_|execute_|setM1~50_combout ; -wire \z80_|execute_|setM1~51_combout ; -wire \z80_|execute_|setM1~6_combout ; -wire \z80_|execute_|setM1~7_combout ; -wire \z80_|execute_|setM1~8_combout ; -wire \z80_|execute_|setM1~9_combout ; -wire \z80_|execute_|setM1~10_combout ; -wire \z80_|execute_|setM1~11_combout ; -wire \z80_|execute_|setM1~17_combout ; -wire \z80_|execute_|setM1~31_combout ; -wire \z80_|execute_|setM1~28_combout ; -wire \z80_|execute_|setM1~30_combout ; -wire \z80_|execute_|setM1~32_combout ; -wire \z80_|execute_|setM1~33_combout ; -wire \z80_|execute_|setM1~25_combout ; -wire \z80_|execute_|setM1~26_combout ; -wire \z80_|execute_|setM1~24_combout ; -wire \z80_|execute_|setM1~27_combout ; -wire \z80_|execute_|setM1~22_combout ; -wire \z80_|execute_|setM1~21_combout ; -wire \z80_|execute_|setM1~53_combout ; -wire \z80_|execute_|setM1~23_combout ; -wire \z80_|execute_|setM1~18_combout ; -wire \z80_|execute_|setM1~19_combout ; -wire \z80_|execute_|setM1~20_combout ; -wire \z80_|execute_|setM1~34_combout ; -wire \z80_|execute_|setM1~52_combout ; +wire \z80_|sequencer_|ena_M~combout ; +wire \z80_|sequencer_|DFFE_T1_ff~q ; +wire \z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ; +wire \z80_|sequencer_|DFFE_T2_ff~q ; wire \z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ; wire \z80_|sequencer_|DFFE_T3_ff~q ; wire \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ; -wire \z80_|decode_state_|in_halt~0_combout ; -wire \z80_|decode_state_|in_halt~1_combout ; -wire \z80_|decode_state_|in_halt~q ; +wire \z80_|execute_|ctl_66_oe~2_combout ; +wire \z80_|interrupts_|im1~q ; +wire \z80_|execute_|ctl_bus_ff_oe~0_combout ; +wire \z80_|execute_|ctl_bus_ff_oe~1_combout ; +wire \z80_|execute_|ctl_bus_zero_oe~0_combout ; +wire \z80_|bus_control_|db[0]~4_combout ; +wire \z80_|bus_control_|db[6]~8_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ; +wire \Selector6~0_combout ; +wire \Selector6~1_combout ; +wire \D[6]~88_combout ; +wire \raw_loader_in~input_o ; +wire \D[6]~69_combout ; +wire \D[6]~78_combout ; +wire \D[6]~79_combout ; +wire \z80_|bus_control_|db[6]~9_combout ; +wire \z80_|execute_|ctl_ir_we~10_combout ; +wire \z80_|execute_|ctl_bus_db_oe~0_combout ; +wire \z80_|execute_|ctl_bus_db_oe~4_combout ; wire \z80_|execute_|ctl_bus_db_oe~2_combout ; wire \z80_|execute_|ctl_bus_db_oe~5_combout ; wire \z80_|execute_|ctl_bus_db_oe~6_combout ; -wire \z80_|execute_|ctl_bus_db_oe~4_combout ; wire \z80_|execute_|ctl_bus_db_oe~combout ; wire \z80_|bus_control_|db[0]~6_combout ; -wire \ula_|zx_keyboard_|keys[1][3]~93_combout ; -wire \ula_|zx_keyboard_|keys[1][3]~94_combout ; -wire \ula_|zx_keyboard_|keys[1][3]~q ; -wire \ula_|zx_keyboard_|keys[0][3]~96_combout ; -wire \ula_|zx_keyboard_|keys[0][3]~98_combout ; -wire \ula_|zx_keyboard_|keys[0][3]~q ; -wire \D[3]~65_combout ; -wire \ula_|zx_keyboard_|keys[3][3]~99_combout ; -wire \ula_|zx_keyboard_|keys[3][3]~100_combout ; -wire \ula_|zx_keyboard_|keys[3][3]~q ; -wire \ula_|zx_keyboard_|keys[2][3]~101_combout ; -wire \ula_|zx_keyboard_|keys[2][3]~102_combout ; -wire \ula_|zx_keyboard_|keys[2][3]~133_combout ; -wire \ula_|zx_keyboard_|keys[2][3]~103_combout ; -wire \ula_|zx_keyboard_|keys[2][3]~q ; -wire \D[3]~66_combout ; -wire \ula_|zx_keyboard_|keys[5][3]~104_combout ; -wire \ula_|zx_keyboard_|keys[5][3]~105_combout ; -wire \ula_|zx_keyboard_|keys[5][3]~q ; -wire \ula_|zx_keyboard_|keys[4][3]~106_combout ; -wire \ula_|zx_keyboard_|Selector5~1_combout ; -wire \ula_|zx_keyboard_|Selector5~0_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~134_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~107_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~135_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~108_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~q ; -wire \D[3]~67_combout ; -wire \ula_|zx_keyboard_|keys[7][3]~112_combout ; -wire \ula_|zx_keyboard_|keys[7][3]~113_combout ; -wire \ula_|zx_keyboard_|keys[7][3]~114_combout ; -wire \ula_|zx_keyboard_|keys[7][3]~q ; -wire \ula_|zx_keyboard_|keys[6][3]~109_combout ; -wire \ula_|zx_keyboard_|keys[6][3]~110_combout ; -wire \ula_|zx_keyboard_|keys[6][3]~137_combout ; -wire \ula_|zx_keyboard_|keys[6][3]~138_combout ; -wire \ula_|zx_keyboard_|keys[6][3]~q ; -wire \ula_|zx_keyboard_|key_row~2_combout ; -wire \D[3]~68_combout ; -wire \D[3]~69_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ; -wire \D[3]~73_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ; -wire \D[3]~74_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ; -wire \D[3]~70_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ; -wire \D[3]~71_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ; -wire \D[3]~72_combout ; -wire \D[3]~108_combout ; -wire \D[3]~95_combout ; -wire \D[3]~96_combout ; -wire \z80_|bus_control_|db[3]~20_combout ; -wire \z80_|bus_control_|db[3]~21_combout ; -wire \z80_|execute_|ctl_mWrite~4_combout ; -wire \z80_|execute_|ctl_apin_mux~2_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~61_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~63_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~64_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~65_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~q ; +wire \ula_|zx_keyboard_|keys[6][2]~67_combout ; +wire \ula_|zx_keyboard_|keys[6][2]~68_combout ; +wire \ula_|zx_keyboard_|keys[6][2]~69_combout ; +wire \ula_|zx_keyboard_|keys[6][2]~q ; +wire \D[2]~36_combout ; +wire \ula_|zx_keyboard_|keys[4][2]~58_combout ; +wire \ula_|zx_keyboard_|keys[4][2]~130_combout ; +wire \ula_|zx_keyboard_|keys[4][2]~59_combout ; +wire \ula_|zx_keyboard_|keys[4][2]~q ; +wire \ula_|zx_keyboard_|keys[5][2]~56_combout ; +wire \ula_|zx_keyboard_|keys[5][2]~57_combout ; +wire \ula_|zx_keyboard_|keys[5][2]~q ; +wire \D[2]~35_combout ; +wire \ula_|zx_keyboard_|keys[0][2]~54_combout ; +wire \ula_|zx_keyboard_|keys[0][2]~55_combout ; +wire \ula_|zx_keyboard_|keys[0][2]~q ; +wire \ula_|zx_keyboard_|keys[3][2]~50_combout ; +wire \ula_|zx_keyboard_|keys[3][2]~51_combout ; +wire \ula_|zx_keyboard_|keys[3][2]~q ; +wire \ula_|zx_keyboard_|keys[2][2]~52_combout ; +wire \ula_|zx_keyboard_|keys[2][2]~53_combout ; +wire \ula_|zx_keyboard_|keys[2][2]~q ; +wire \D[2]~33_combout ; +wire \ula_|zx_keyboard_|keys[1][2]~47_combout ; +wire \ula_|zx_keyboard_|keys[1][2]~48_combout ; +wire \ula_|zx_keyboard_|keys[1][2]~q ; +wire \ula_|zx_keyboard_|key_row~1_combout ; +wire \D[2]~34_combout ; +wire \D[2]~37_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~3_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ; +wire \Selector0~0_combout ; +wire \Selector0~1_combout ; +wire \D[2]~82_combout ; +wire \D[2]~38_combout ; +wire \D[2]~39_combout ; +wire \z80_|bus_control_|db[2]~12_combout ; +wire \z80_|bus_control_|db[2]~13_combout ; +wire \z80_|pla_decode_|Equal1~4_combout ; +wire \z80_|execute_|ctl_alu_op_low~26_combout ; +wire \z80_|execute_|ctl_alu_op_low~45_combout ; +wire \z80_|execute_|setM1~17_combout ; +wire \z80_|execute_|setM1~18_combout ; +wire \z80_|execute_|setM1~11_combout ; +wire \z80_|execute_|setM1~10_combout ; +wire \z80_|execute_|setM1~12_combout ; +wire \z80_|execute_|setM1~8_combout ; +wire \z80_|execute_|setM1~9_combout ; +wire \z80_|execute_|setM1~13_combout ; +wire \z80_|execute_|setM1~15_combout ; +wire \z80_|execute_|setM1~14_combout ; +wire \z80_|execute_|setM1~16_combout ; +wire \z80_|execute_|setM1~19_combout ; +wire \z80_|execute_|setM1~23_combout ; +wire \z80_|execute_|setM1~22_combout ; +wire \z80_|execute_|setM1~56_combout ; +wire \z80_|execute_|setM1~24_combout ; +wire \z80_|execute_|setM1~25_combout ; +wire \z80_|execute_|setM1~26_combout ; +wire \z80_|execute_|setM1~27_combout ; +wire \z80_|execute_|setM1~28_combout ; +wire \z80_|execute_|setM1~55_combout ; +wire \z80_|execute_|setM1~29_combout ; +wire \z80_|execute_|setM1~31_combout ; +wire \z80_|execute_|setM1~33_combout ; +wire \z80_|execute_|setM1~32_combout ; +wire \z80_|execute_|setM1~34_combout ; +wire \z80_|execute_|setM1~20_combout ; +wire \z80_|execute_|setM1~21_combout ; +wire \z80_|execute_|setM1~35_combout ; +wire \z80_|execute_|setM1~43_combout ; +wire \z80_|execute_|setM1~44_combout ; +wire \z80_|execute_|setM1~45_combout ; +wire \z80_|execute_|setM1~46_combout ; +wire \z80_|execute_|setM1~52_combout ; +wire \z80_|sequencer_|SYNTHESIZED_WIRE_17~combout ; +wire \z80_|sequencer_|T6~q ; +wire \z80_|execute_|setM1~53_combout ; +wire \z80_|execute_|setM1~54_combout ; +wire \z80_|sequencer_|DFFE_M1_ff~0_combout ; +wire \z80_|sequencer_|DFFE_M1_ff~q ; +wire \z80_|resets_|x1~0_combout ; +wire \z80_|fpga_reset~feeder_combout ; +wire \z80_|fpga_reset~q ; +wire \z80_|fpga_reset~clkctrl_outclk ; +wire \z80_|resets_|x1~q ; +wire \z80_|resets_|x3~combout ; +wire \z80_|resets_|SYNTHESIZED_WIRE_12~q ; +wire \z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ; +wire \z80_|resets_|SYNTHESIZED_WIRE_10~q ; +wire \z80_|resets_|SYNTHESIZED_WIRE_9~feeder_combout ; +wire \z80_|resets_|SYNTHESIZED_WIRE_9~q ; +wire \z80_|resets_|DFFE_intr_ff3~q ; +wire \z80_|resets_|clrpc_int~0_combout ; +wire \z80_|resets_|clrpc_int~q ; +wire \z80_|resets_|clrpc~0_combout ; wire \z80_|address_pins_|DFFE_apin_latch[0]~0_combout ; -wire \D[0]~59_combout ; -wire \D[0]~60_combout ; -wire \D[1]~61_combout ; -wire \D[1]~62_combout ; -wire \D[2]~63_combout ; -wire \D[2]~64_combout ; -wire \D[3]~75_combout ; -wire \D[3]~76_combout ; -wire \D[4]~82_combout ; -wire \D[4]~83_combout ; -wire \D[6]~92_combout ; -wire \D[6]~93_combout ; +wire \D[0]~47_combout ; +wire \D[0]~48_combout ; +wire \D[1]~49_combout ; +wire \D[1]~50_combout ; +wire \D[2]~51_combout ; +wire \D[2]~52_combout ; +wire \D[3]~58_combout ; +wire \D[3]~59_combout ; +wire \D[4]~65_combout ; +wire \D[4]~66_combout ; +wire \D[6]~70_combout ; +wire \D[6]~71_combout ; wire \z80_|nM1_int~3_combout ; wire \z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q ; wire \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder_combout ; @@ -2489,33 +2477,43 @@ wire \ula_|i2c_loader_|divider[1]~6 ; wire \ula_|i2c_loader_|divider[2]~7_combout ; wire \ula_|i2c_loader_|divider[2]~8 ; wire \ula_|i2c_loader_|divider[3]~9_combout ; +wire \ula_|i2c_loader_|WideAnd0~0_combout ; wire \ula_|i2c_loader_|divider[3]~10 ; wire \ula_|i2c_loader_|divider[4]~11_combout ; wire \ula_|i2c_loader_|divider[4]~12 ; wire \ula_|i2c_loader_|divider[5]~13_combout ; -wire \ula_|i2c_loader_|WideAnd0~0_combout ; wire \ula_|i2c_loader_|WideAnd0~combout ; wire \ula_|i2c_loader_|state.Idle~q ; wire \ula_|i2c_loader_|phase~0_combout ; wire \ula_|i2c_loader_|phase~1_combout ; wire \ula_|i2c_loader_|nbit~5_combout ; -wire \ula_|i2c_loader_|thisbyte[0]~8_combout ; +wire \ula_|i2c_loader_|state.Idle~0_combout ; wire \ula_|i2c_loader_|Mux42~0_combout ; +wire \ula_|i2c_loader_|nbit~6_combout ; +wire \ula_|i2c_loader_|state.Done~0_combout ; +wire \ula_|i2c_loader_|state.Ack~0_combout ; +wire \ula_|i2c_loader_|state.Ack~1_combout ; +wire \ula_|i2c_loader_|state.Ack~q ; +wire \ula_|i2c_loader_|nbit[0]~2_combout ; wire \ula_|i2c_loader_|nbyte~4_combout ; wire \ula_|i2c_loader_|thisbyte[0]~7_combout ; wire \I2C_SDAT~input_o ; wire \ula_|i2c_loader_|nbyte[0]~1_combout ; wire \ula_|i2c_loader_|nbyte[0]~2_combout ; wire \ula_|i2c_loader_|nbyte[0]~3_combout ; -wire \ula_|i2c_loader_|state.Stop~0_combout ; -wire \ula_|i2c_loader_|state.Stop~1_combout ; -wire \ula_|i2c_loader_|state.Stop~q ; -wire \ula_|i2c_loader_|state.Idle~0_combout ; +wire \ula_|i2c_loader_|nbit[0]~1_combout ; +wire \ula_|i2c_loader_|nbit[0]~3_combout ; +wire \ula_|i2c_loader_|nbit[0]~4_combout ; wire \ula_|i2c_loader_|nbit~0_combout ; -wire \ula_|i2c_loader_|state.Done~0_combout ; -wire \ula_|i2c_loader_|state.Ack~0_combout ; -wire \ula_|i2c_loader_|state.Ack~1_combout ; -wire \ula_|i2c_loader_|state.Ack~q ; +wire \ula_|i2c_loader_|state.Done~1_combout ; +wire \ula_|i2c_loader_|state~27_combout ; +wire \ula_|i2c_loader_|state~24_combout ; +wire \ula_|i2c_loader_|state~26_combout ; +wire \ula_|i2c_loader_|state.Data~0_combout ; +wire \ula_|i2c_loader_|state.Data~q ; +wire \ula_|i2c_loader_|state.Done~2_combout ; +wire \ula_|i2c_loader_|state.Pause~1_combout ; +wire \ula_|i2c_loader_|thisbyte[0]~8_combout ; wire \ula_|i2c_loader_|nbyte[1]~5_combout ; wire \ula_|i2c_loader_|thisbyte[0]~18_combout ; wire \ula_|i2c_loader_|thisbyte[0]~9 ; @@ -2525,28 +2523,18 @@ wire \ula_|i2c_loader_|thisbyte[2]~12_combout ; wire \ula_|i2c_loader_|thisbyte[2]~13 ; wire \ula_|i2c_loader_|thisbyte[3]~14_combout ; wire \ula_|i2c_loader_|Equal2~0_combout ; -wire \ula_|i2c_loader_|state.Pause~0_combout ; wire \ula_|i2c_loader_|thisbyte[3]~15 ; wire \ula_|i2c_loader_|thisbyte[4]~16_combout ; -wire \ula_|i2c_loader_|state.Pause~1_combout ; -wire \ula_|i2c_loader_|state.Done~2_combout ; +wire \ula_|i2c_loader_|Equal2~1_combout ; +wire \ula_|i2c_loader_|state.Pause~0_combout ; wire \ula_|i2c_loader_|state.Pause~2_combout ; -wire \ula_|i2c_loader_|state.Pause~3_combout ; wire \ula_|i2c_loader_|state.Pause~q ; wire \ula_|i2c_loader_|state~25_combout ; wire \ula_|i2c_loader_|state.Start~q ; wire \ula_|i2c_loader_|nbyte~0_combout ; -wire \ula_|i2c_loader_|nbit[0]~1_combout ; -wire \ula_|i2c_loader_|nbit[0]~2_combout ; -wire \ula_|i2c_loader_|nbit[0]~3_combout ; -wire \ula_|i2c_loader_|nbit[0]~4_combout ; -wire \ula_|i2c_loader_|nbit~6_combout ; -wire \ula_|i2c_loader_|state.Done~1_combout ; -wire \ula_|i2c_loader_|state~27_combout ; -wire \ula_|i2c_loader_|state~24_combout ; -wire \ula_|i2c_loader_|state~26_combout ; -wire \ula_|i2c_loader_|state.Data~0_combout ; -wire \ula_|i2c_loader_|state.Data~q ; +wire \ula_|i2c_loader_|state.Stop~0_combout ; +wire \ula_|i2c_loader_|state.Stop~1_combout ; +wire \ula_|i2c_loader_|state.Stop~q ; wire \ula_|i2c_loader_|scl_out~0_combout ; wire \ula_|i2c_loader_|scl_out~_Duplicate_1_q ; wire \ula_|i2c_loader_|scl_out~1_combout ; @@ -2556,26 +2544,25 @@ wire \ula_|i2c_loader_|sda_out~_Duplicate_1_q ; wire \ula_|i2c_loader_|shiftreg~4_combout ; wire \ula_|i2c_loader_|Mux35~0_combout ; wire \ula_|i2c_loader_|shiftreg~13_combout ; -wire \ula_|i2c_loader_|shiftreg~14_combout ; wire \ula_|i2c_loader_|shiftreg~15_combout ; -wire \ula_|i2c_loader_|shiftreg[0]~24_combout ; -wire \ula_|i2c_loader_|shiftreg[0]~6_combout ; -wire \ula_|i2c_loader_|shiftreg[0]~7_combout ; -wire \ula_|i2c_loader_|shiftreg[0]~8_combout ; -wire \ula_|i2c_loader_|shiftreg~21_combout ; -wire \ula_|i2c_loader_|shiftreg~22_combout ; -wire \ula_|i2c_loader_|shiftreg~23_combout ; -wire \ula_|i2c_loader_|shiftreg[6]~10_combout ; -wire \ula_|i2c_loader_|shiftreg[6]~11_combout ; -wire \ula_|i2c_loader_|shiftreg~18_combout ; -wire \ula_|i2c_loader_|shiftreg~19_combout ; -wire \ula_|i2c_loader_|shiftreg~20_combout ; wire \ula_|i2c_loader_|shiftreg~16_combout ; wire \ula_|i2c_loader_|shiftreg~17_combout ; -wire \ula_|i2c_loader_|shiftreg~26_combout ; +wire \ula_|i2c_loader_|shiftreg~18_combout ; +wire \ula_|i2c_loader_|shiftreg~20_combout ; +wire \ula_|i2c_loader_|shiftreg~21_combout ; +wire \ula_|i2c_loader_|shiftreg[0]~23_combout ; +wire \ula_|i2c_loader_|shiftreg[0]~6_combout ; +wire \ula_|i2c_loader_|shiftreg[0]~7_combout ; +wire \ula_|i2c_loader_|shiftreg~22_combout ; +wire \ula_|i2c_loader_|shiftreg[6]~9_combout ; +wire \ula_|i2c_loader_|shiftreg[6]~10_combout ; +wire \ula_|i2c_loader_|shiftreg~19_combout ; wire \ula_|i2c_loader_|shiftreg~25_combout ; wire \ula_|i2c_loader_|shiftreg~12_combout ; -wire \ula_|i2c_loader_|shiftreg~9_combout ; +wire \ula_|i2c_loader_|shiftreg~14_combout ; +wire \ula_|i2c_loader_|shiftreg~24_combout ; +wire \ula_|i2c_loader_|shiftreg~11_combout ; +wire \ula_|i2c_loader_|shiftreg~8_combout ; wire \ula_|i2c_loader_|shiftreg[7]~5_combout ; wire \ula_|i2c_loader_|sda_out~0_combout ; wire \ula_|i2c_loader_|sda_out~1_combout ; @@ -2616,12 +2603,12 @@ wire \ula_|i2s_intf_|Add0~18_combout ; wire \ula_|i2s_intf_|lrdivider[9]~3_combout ; wire \ula_|i2s_intf_|Equal0~0_combout ; wire \ula_|i2s_intf_|Equal0~2_combout ; -wire \ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder_combout ; wire \ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ; wire \ula_|i2s_intf_|lrclk_r~0_combout ; wire \ula_|i2s_intf_|lrclk_r~q ; wire \ula_|i2s_intf_|lrclk_r~_Duplicate_1_q ; wire \ula_|i2s_intf_|bitcount[0]~5_combout ; +wire \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder_combout ; wire \ula_|i2s_intf_|bclk_r~_Duplicate_1_q ; wire \ula_|i2s_intf_|bitcount[4]~15_combout ; wire \ula_|i2s_intf_|bitcount[0]~6 ; @@ -2630,9 +2617,11 @@ wire \ula_|i2s_intf_|bitcount[1]~8 ; wire \ula_|i2s_intf_|bitcount[2]~9_combout ; wire \ula_|i2s_intf_|bitcount[2]~10 ; wire \ula_|i2s_intf_|bitcount[3]~11_combout ; -wire \ula_|i2s_intf_|LessThan0~0_combout ; wire \ula_|i2s_intf_|bitcount[3]~12 ; wire \ula_|i2s_intf_|bitcount[4]~13_combout ; +wire \ula_|i2s_intf_|LessThan0~0_combout ; +wire \ula_|i2s_intf_|shiftreg[4]~1_combout ; +wire \ula_|i2s_intf_|Add2~18_combout ; wire \ula_|i2s_intf_|Add2~7_cout ; wire \ula_|i2s_intf_|Add2~8_combout ; wire \ula_|i2s_intf_|Add2~20_combout ; @@ -2646,13 +2635,10 @@ wire \ula_|i2s_intf_|Add2~13 ; wire \ula_|i2s_intf_|Add2~14_combout ; wire \ula_|i2s_intf_|Add2~16_combout ; wire \ula_|i2s_intf_|Equal1~0_combout ; -wire \ula_|i2s_intf_|shiftreg[4]~1_combout ; -wire \ula_|i2s_intf_|Add2~18_combout ; wire \ula_|i2s_intf_|Equal1~1_combout ; wire \ula_|i2s_intf_|bclk_r~0_combout ; wire \ula_|i2s_intf_|bclk_r~1_combout ; wire \ula_|i2s_intf_|bclk_r~q ; -wire \ula_|pcm_outl[13]~feeder_combout ; wire \ula_|always0~2_combout ; wire \ula_|always0~3_combout ; wire \ula_|i2s_intf_|shiftreg[0]~19_combout ; @@ -2671,33 +2657,30 @@ wire \ula_|i2s_intf_|shiftreg~10_combout ; wire \ula_|i2s_intf_|shiftreg~9_combout ; wire \ula_|i2s_intf_|shiftreg~8_combout ; wire \ula_|i2s_intf_|shiftreg~7_combout ; -wire \ula_|i2s_intf_|PCM_INR[14]~0_combout ; wire \ula_|i2s_intf_|PCM_INL[14]~0_combout ; +wire \ula_|i2s_intf_|PCM_INR[14]~0_combout ; wire \ula_|pcm_outr~0_combout ; wire \ula_|i2s_intf_|shiftreg~6_combout ; wire \ula_|i2s_intf_|shiftreg~5_combout ; wire \ula_|i2s_intf_|shiftreg~4_combout ; wire \ula_|i2s_intf_|shiftreg~3_combout ; wire \ula_|i2s_intf_|shiftreg~0_combout ; -wire \ula_|video_|LessThan2~0_combout ; +wire \ula_|border[1]~feeder_combout ; +wire \ula_|video_|LessThan4~0_combout ; +wire \ula_|video_|screen_en~0_combout ; wire \ula_|video_|LessThan6~0_combout ; +wire \ula_|video_|LessThan6~1_combout ; +wire \ula_|video_|screen_en~1_combout ; +wire \ula_|video_|LessThan2~0_combout ; wire \ula_|video_|LessThan2~1_combout ; wire \ula_|video_|LessThan3~0_combout ; wire \ula_|video_|LessThan0~0_combout ; wire \ula_|video_|disp_enable~0_combout ; wire \ula_|video_|disp_enable~1_combout ; -wire \ula_|video_|LessThan6~1_combout ; -wire \ula_|video_|LessThan4~0_combout ; -wire \ula_|video_|screen_en~0_combout ; -wire \ula_|video_|screen_en~1_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 ; -wire \ula_|video_|attr_prefetch[1]~feeder_combout ; -wire \ula_|video_|Decoder0~1_combout ; -wire \ula_|video_|Decoder0~0_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 ; -wire \ula_|video_|attr_prefetch[4]~feeder_combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 ; wire \ula_|video_|attr_prefetch[7]~feeder_combout ; +wire \ula_|video_|Decoder0~1_combout ; +wire \ula_|video_|Decoder0~0_combout ; wire \ula_|video_|frame[0]~12_combout ; wire \ula_|video_|frame[1]~4_combout ; wire \ula_|video_|frame[1]~5 ; @@ -2706,11 +2689,12 @@ wire \ula_|video_|frame[2]~7 ; wire \ula_|video_|frame[3]~8_combout ; wire \ula_|video_|frame[3]~9 ; wire \ula_|video_|frame[4]~10_combout ; +wire \ula_|video_|frame[4]~feeder_combout ; wire \ula_|video_|inverted~combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 ; wire \ula_|video_|bits_prefetch[6]~feeder_combout ; wire \ula_|video_|Decoder0~2_combout ; -wire \ula_|video_|bits[6]~feeder_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 ; wire \ula_|video_|bits_prefetch[4]~feeder_combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 ; wire \ula_|video_|bits_prefetch[5]~feeder_combout ; @@ -2723,6 +2707,7 @@ wire \ula_|video_|bits_prefetch[2]~feeder_combout ; wire \ula_|video_|bits[2]~feeder_combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 ; wire \ula_|video_|bits_prefetch[0]~feeder_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 ; wire \ula_|video_|bits_prefetch[1]~feeder_combout ; wire \ula_|video_|bits[1]~feeder_combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 ; @@ -2730,13 +2715,15 @@ wire \ula_|video_|bits_prefetch[3]~feeder_combout ; wire \ula_|video_|Mux0~2_combout ; wire \ula_|video_|Mux0~3_combout ; wire \ula_|video_|cindex[1]~0_combout ; +wire \ula_|video_|attr_prefetch[4]~feeder_combout ; +wire \ula_|video_|attr_prefetch[1]~feeder_combout ; wire \ula_|video_|cindex[1]~1_combout ; wire \ula_|video_|VGA_R[0]~0_combout ; wire \ula_|video_|attr_prefetch[6]~feeder_combout ; wire \ula_|video_|VGA_B[1]~0_combout ; wire \ula_|video_|VGA_R[1]~1_combout ; -wire \ula_|video_|attr_prefetch[2]~feeder_combout ; wire \ula_|video_|attr_prefetch[5]~feeder_combout ; +wire \ula_|video_|attr_prefetch[2]~feeder_combout ; wire \ula_|video_|cindex[2]~2_combout ; wire \ula_|video_|VGA_G[0]~0_combout ; wire \ula_|video_|VGA_G[1]~1_combout ; @@ -2761,42 +2748,24 @@ wire \z80_|memory_ifc_|nM1_out~combout ; wire \ula_|beep~0_combout ; wire \ula_|beep~q ; wire [0:0] \ram0|altsyncram_component|auto_generated|address_reg_a ; -wire [1:0] \ram1|altsyncram_component|auto_generated|address_reg_a ; wire [2:0] \ram1|altsyncram_component|auto_generated|decode3|w_anode244w ; -wire [2:0] \ram1|altsyncram_component|auto_generated|decode3|w_anode223w ; wire [2:0] \ula_|border ; wire [0:0] \ula_|clocks_|counter ; -wire [7:0] \ula_|i2c_loader_|shiftreg ; wire [1:0] \ula_|i2c_loader_|nbyte ; -wire [5:0] \ula_|i2c_loader_|divider ; -wire [17:0] \ula_|i2s_intf_|shiftreg ; wire [4:0] \ula_|i2s_intf_|bitcount ; -wire [15:0] \ula_|i2s_intf_|PCM_INR ; -wire [9:0] \ula_|video_|vga_vc ; wire [4:0] \ula_|video_|frame ; -wire [7:0] \ula_|video_|bits_prefetch ; wire [7:0] \ula_|video_|attr_prefetch ; -wire [7:0] \ula_|ps2_keyboard_|clk_filter ; -wire [7:0] \z80_|reg_file_|b2v_latch_af_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_bc2_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_bc_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_de2_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_de_lo|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_af_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_bc2_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_de2_hi|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_hl2_lo|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_hl_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_ir_lo|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_ix_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_iy_lo|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_pc_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_sp_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_wz_lo|latch ; -wire [3:0] \z80_|alu_|op2_low ; wire [3:0] \z80_|alu_|op1_low ; -wire [15:0] \z80_|address_latch_|Q ; -wire [15:0] \z80_|address_latch_|b2v_inst_inc_dec|address ; -wire [15:0] \z80_|address_pins_|DFFE_apin_latch ; -wire [7:0] \z80_|data_pins_|dout ; -wire [7:0] \z80_|ir_|opcode ; +wire [7:0] \z80_|reg_file_|b2v_latch_af2_hi|latch ; +wire [15:0] \z80_|address_latch_|abusz ; +wire [7:0] \z80_|data_pins_|SYNTHESIZED_WIRE_0 ; wire [0:0] \ram0|altsyncram_component|auto_generated|out_address_reg_a ; wire [1:0] \ram1|altsyncram_component|auto_generated|out_address_reg_a ; wire [2:0] \ram1|altsyncram_component|auto_generated|decode3|w_anode252w ; @@ -2815,13 +2784,11 @@ wire [7:0] \ula_|video_|bits ; wire [7:0] \ula_|video_|attr ; wire [8:0] \ula_|ps2_keyboard_|shiftreg ; wire [3:0] \ula_|ps2_keyboard_|bit_count ; -wire [7:0] \z80_|reg_file_|b2v_latch_af2_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_af_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_bc2_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_bc_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_de2_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_de_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_hl2_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_af_lo|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_bc2_lo|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_bc_lo|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_de2_lo|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_de_lo|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_hl_hi|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_ir_hi|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_ix_hi|latch ; @@ -2829,53 +2796,73 @@ wire [7:0] \z80_|reg_file_|b2v_latch_iy_hi|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_pc_hi|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_sp_hi|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_wz_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_wz_lo|latch ; wire [3:0] \z80_|alu_|result_lo ; wire [3:0] \z80_|alu_|op2_high ; wire [3:0] \z80_|alu_|op1_high ; wire [3:0] \z80_|alu_|b2v_op1_latch_mux_high|Q ; -wire [7:0] \z80_|reg_file_|b2v_latch_af2_hi|latch ; -wire [15:0] \z80_|address_latch_|abusz ; -wire [7:0] \z80_|data_pins_|SYNTHESIZED_WIRE_0 ; +wire [15:0] \z80_|address_latch_|Q ; +wire [15:0] \z80_|address_latch_|b2v_inst_inc_dec|address ; +wire [15:0] \z80_|address_pins_|DFFE_apin_latch ; +wire [7:0] \z80_|data_pins_|dout ; +wire [7:0] \z80_|ir_|opcode ; +wire [1:0] \ram1|altsyncram_component|auto_generated|address_reg_a ; +wire [2:0] \ram1|altsyncram_component|auto_generated|decode3|w_anode223w ; +wire [7:0] \ula_|i2c_loader_|shiftreg ; +wire [5:0] \ula_|i2c_loader_|divider ; +wire [17:0] \ula_|i2s_intf_|shiftreg ; +wire [15:0] \ula_|i2s_intf_|PCM_INR ; +wire [9:0] \ula_|video_|vga_vc ; +wire [7:0] \ula_|video_|bits_prefetch ; +wire [7:0] \ula_|ps2_keyboard_|clk_filter ; +wire [7:0] \z80_|reg_file_|b2v_latch_af2_lo|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_bc_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_de_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_hl2_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_ir_lo|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_iy_lo|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_sp_lo|latch ; +wire [3:0] \z80_|alu_|op2_low ; wire [4:0] \ula_|pll_|altpll_component|auto_generated|pll1_CLK_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a25_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ; -wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ; -wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; -wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; -wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; -wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a28_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ; @@ -2883,33 +2870,33 @@ wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_b wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a4_PORTBDATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ; -wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ; -wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a5_PORTBDATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a5_PORTBDATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ; -wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a31_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ; -wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ; -wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus ; assign \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk [0] = \ula_|pll_|altpll_component|auto_generated|pll1_CLK_bus [0]; assign \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk [1] = \ula_|pll_|altpll_component|auto_generated|pll1_CLK_bus [1]; @@ -2917,82 +2904,82 @@ assign \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk [2] = \ula_|pll_ assign \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk [3] = \ula_|pll_|altpll_component|auto_generated|pll1_CLK_bus [3]; assign \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk [4] = \ula_|pll_|altpll_component|auto_generated|pll1_CLK_bus [4]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus [0]; - assign \ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus [0]; + assign \ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0]; assign \ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a25_PORTADATAOUT_bus [0]; assign \rom|altsyncram_component|auto_generated|ram_block1a9~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a1~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [0]; + assign \ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a1~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus [0]; -assign \ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a10~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a10~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus [0]; -assign \ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a8~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus [0]; +assign \ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a8~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; -assign \ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus [0]; +assign \ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; - -assign \ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus [0]; - -assign \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus [0]; assign \ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus [0]; - assign \ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus [0]; assign \ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a28_PORTADATAOUT_bus [0]; @@ -3007,60 +2994,60 @@ assign \rom|altsyncram_component|auto_generated|ram_block1a4~portadataout = \ro assign \ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus [0]; - assign \ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus [0]; + assign \ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus [0]; assign \ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus [0]; assign \rom|altsyncram_component|auto_generated|ram_block1a13~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a5~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus [0]; + assign \ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a5_PORTBDATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a5~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus [0]; -assign \ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a14~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a6~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a14~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus [0]; - -assign \ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus [0]; - -assign \rom|altsyncram_component|auto_generated|ram_block1a6~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus [0]; assign \ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus [0]; - assign \ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus [0]; assign \ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a31_PORTADATAOUT_bus [0]; assign \rom|altsyncram_component|auto_generated|ram_block1a15~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus [0]; -assign \ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus [0]; - -assign \ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus [0]; - assign \rom|altsyncram_component|auto_generated|ram_block1a7~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus [0]; +assign \ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus [0]; + // Location: IOOBUF_X53_Y21_N23 cycloneive_io_obuf \GPIO_1[0]~output ( .i(\z80_|address_pins_|DFFE_apin_latch [0]), @@ -3271,8 +3258,8 @@ defparam \GPIO_1[15]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y11_N9 cycloneive_io_obuf \GPIO_1[16]~output ( - .i(\D[0]~60_combout ), - .oe(\D[0]~107_combout ), + .i(\D[0]~48_combout ), + .oe(\D[0]~84_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[16]), @@ -3284,8 +3271,8 @@ defparam \GPIO_1[16]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y12_N2 cycloneive_io_obuf \GPIO_1[17]~output ( - .i(\D[1]~62_combout ), - .oe(\D[0]~107_combout ), + .i(\D[1]~50_combout ), + .oe(\D[0]~84_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[17]), @@ -3297,8 +3284,8 @@ defparam \GPIO_1[17]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y8_N23 cycloneive_io_obuf \GPIO_1[18]~output ( - .i(\D[2]~64_combout ), - .oe(\D[0]~107_combout ), + .i(\D[2]~52_combout ), + .oe(\D[0]~84_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[18]), @@ -3310,8 +3297,8 @@ defparam \GPIO_1[18]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y11_N2 cycloneive_io_obuf \GPIO_1[19]~output ( - .i(\D[3]~76_combout ), - .oe(\D[0]~107_combout ), + .i(\D[3]~59_combout ), + .oe(\D[0]~84_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[19]), @@ -3323,8 +3310,8 @@ defparam \GPIO_1[19]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y6_N16 cycloneive_io_obuf \GPIO_1[20]~output ( - .i(\D[4]~83_combout ), - .oe(\D[0]~107_combout ), + .i(\D[4]~66_combout ), + .oe(\D[0]~84_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[20]), @@ -3336,8 +3323,8 @@ defparam \GPIO_1[20]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y7_N9 cycloneive_io_obuf \GPIO_1[21]~output ( - .i(\D[5]~85_combout ), - .oe(\D[0]~107_combout ), + .i(\D[5]~68_combout ), + .oe(\D[0]~84_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[21]), @@ -3349,8 +3336,8 @@ defparam \GPIO_1[21]~output .open_drain_output = "false"; // Location: IOOBUF_X49_Y0_N2 cycloneive_io_obuf \GPIO_1[22]~output ( - .i(\D[6]~93_combout ), - .oe(\D[0]~107_combout ), + .i(\D[6]~71_combout ), + .oe(\D[0]~84_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[22]), @@ -3362,8 +3349,8 @@ defparam \GPIO_1[22]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y9_N23 cycloneive_io_obuf \GPIO_1[23]~output ( - .i(\D[7]~94_combout ), - .oe(\D[0]~107_combout ), + .i(\D[7]~72_combout ), + .oe(\D[0]~84_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[23]), @@ -4024,7 +4011,7 @@ defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl .cl defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: LCCOMB_X25_Y33_N4 +// Location: LCCOMB_X25_Y33_N0 cycloneive_lcell_comb \ula_|clocks_|counter[0]~0 ( // Equation(s): // \ula_|clocks_|counter[0]~0_combout = !\ula_|clocks_|counter [0] @@ -4041,7 +4028,7 @@ defparam \ula_|clocks_|counter[0]~0 .lut_mask = 16'h0F0F; defparam \ula_|clocks_|counter[0]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X25_Y33_N5 +// Location: FF_X25_Y33_N1 dffeas \ula_|clocks_|counter[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), .d(\ula_|clocks_|counter[0]~0_combout ), @@ -4070,7 +4057,7 @@ defparam \SW[2]~input .bus_hold = "false"; defparam \SW[2]~input .simulate_z_as = "z"; // synopsys translate_on -// Location: LCCOMB_X25_Y33_N10 +// Location: LCCOMB_X25_Y33_N4 cycloneive_lcell_comb \ula_|clocks_|clk_cpu~0 ( // Equation(s): // \ula_|clocks_|clk_cpu~0_combout = \ula_|clocks_|clk_cpu~q $ (((\SW[2]~input_o ) # (!\ula_|clocks_|counter [0]))) @@ -4087,7 +4074,7 @@ defparam \ula_|clocks_|clk_cpu~0 .lut_mask = 16'h0FC3; defparam \ula_|clocks_|clk_cpu~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X25_Y33_N11 +// Location: FF_X25_Y33_N5 dffeas \ula_|clocks_|clk_cpu ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), .d(\ula_|clocks_|clk_cpu~0_combout ), @@ -4106,7 +4093,7 @@ defparam \ula_|clocks_|clk_cpu .is_wysiwyg = "true"; defparam \ula_|clocks_|clk_cpu .power_up = "low"; // synopsys translate_on -// Location: CLKCTRL_G14 +// Location: CLKCTRL_G12 cycloneive_clkctrl \ula_|clocks_|clk_cpu~clkctrl ( .ena(vcc), .inclk({vcc,vcc,vcc,\ula_|clocks_|clk_cpu~q }), @@ -4119,38 +4106,34 @@ defparam \ula_|clocks_|clk_cpu~clkctrl .clock_type = "global clock"; defparam \ula_|clocks_|clk_cpu~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: LCCOMB_X32_Y17_N20 -cycloneive_lcell_comb \z80_|sequencer_|DFFE_M1_ff~0 ( +// Location: LCCOMB_X26_Y13_N30 +cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_15 ( // Equation(s): -// \z80_|sequencer_|DFFE_M1_ff~0_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # (\z80_|execute_|nextM~14_combout ))) - - .dataa(\z80_|execute_|setM1~52_combout ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|DFFE_M1_ff~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_M1_ff~0 .lut_mask = 16'hAAA0; -defparam \z80_|sequencer_|DFFE_M1_ff~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N12 -cycloneive_lcell_comb \z80_|sequencer_|ena_M ( -// Equation(s): -// \z80_|sequencer_|ena_M~combout = (\z80_|execute_|setM1~52_combout & !\z80_|execute_|nextM~14_combout ) +// \z80_|sequencer_|SYNTHESIZED_WIRE_15~combout = (\z80_|execute_|setM1~54_combout & (\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|execute_|nextM~14_combout )) .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|setM1~52_combout ), + .datab(\z80_|execute_|setM1~54_combout ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), .datad(\z80_|execute_|nextM~14_combout ), .cin(gnd), - .combout(\z80_|sequencer_|ena_M~combout ), + .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ), .cout()); // synopsys translate_off -defparam \z80_|sequencer_|ena_M .lut_mask = 16'h00F0; -defparam \z80_|sequencer_|ena_M .sum_lutc_input = "datac"; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_15 .lut_mask = 16'h00C0; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: CLKCTRL_G9 +cycloneive_clkctrl \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\z80_|resets_|SYNTHESIZED_WIRE_12~q }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk )); +// synopsys translate_off +defparam \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl .clock_type = "global clock"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl .ena_register_mode = "none"; // synopsys translate_on // Location: IOIBUF_X0_Y16_N8 @@ -4163,7 +4146,7 @@ defparam \KEY[1]~input .bus_hold = "false"; defparam \KEY[1]~input .simulate_z_as = "z"; // synopsys translate_on -// Location: LCCOMB_X24_Y15_N6 +// Location: LCCOMB_X27_Y13_N8 cycloneive_lcell_comb \z80_|interrupts_|nmi_armed~feeder ( // Equation(s): // \z80_|interrupts_|nmi_armed~feeder_combout = VCC @@ -4180,24 +4163,24 @@ defparam \z80_|interrupts_|nmi_armed~feeder .lut_mask = 16'hFFFF; defparam \z80_|interrupts_|nmi_armed~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y15_N2 +// Location: LCCOMB_X27_Y13_N4 cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_9 ( // Equation(s): // \z80_|interrupts_|SYNTHESIZED_WIRE_9~combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .dataa(gnd), .datab(gnd), - .datac(gnd), + .datac(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .cin(gnd), .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_9~combout ), .cout()); // synopsys translate_off -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_9 .lut_mask = 16'hAAFF; +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_9 .lut_mask = 16'hF0FF; defparam \z80_|interrupts_|SYNTHESIZED_WIRE_9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y15_N7 +// Location: FF_X27_Y13_N9 dffeas \z80_|interrupts_|nmi_armed ( .clk(!\KEY[1]~input_o ), .d(\z80_|interrupts_|nmi_armed~feeder_combout ), @@ -4216,7 +4199,7 @@ defparam \z80_|interrupts_|nmi_armed .is_wysiwyg = "true"; defparam \z80_|interrupts_|nmi_armed .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y15_N12 +// Location: LCCOMB_X28_Y13_N0 cycloneive_lcell_comb \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder ( // Equation(s): // \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder_combout = \z80_|interrupts_|nmi_armed~q @@ -4233,58 +4216,60 @@ defparam \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder .lut_mask = 16'hFF00 defparam \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_eval_cond~0 ( +// Location: LCCOMB_X26_Y13_N22 +cycloneive_lcell_comb \z80_|sequencer_|DFFE_M2_ff~0 ( // Equation(s): -// \z80_|execute_|ctl_eval_cond~0_combout = (\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) +// \z80_|sequencer_|DFFE_M2_ff~0_combout = (\z80_|execute_|setM1~54_combout & ((\z80_|execute_|nextM~14_combout & (!\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|DFFE_M2_ff~q ))))) - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|execute_|setM1~54_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|execute_|nextM~14_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_eval_cond~0_combout ), + .combout(\z80_|sequencer_|DFFE_M2_ff~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_eval_cond~0 .lut_mask = 16'h00F0; -defparam \z80_|execute_|ctl_eval_cond~0 .sum_lutc_input = "datac"; +defparam \z80_|sequencer_|DFFE_M2_ff~0 .lut_mask = 16'h44C0; +defparam \z80_|sequencer_|DFFE_M2_ff~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X41_Y18_N0 -cycloneive_lcell_comb \z80_|execute_|ixy_d~4 ( -// Equation(s): -// \z80_|execute_|ixy_d~4_combout = (!\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~4_combout ), - .cout()); +// Location: FF_X26_Y13_N23 +dffeas \z80_|sequencer_|DFFE_M2_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|DFFE_M2_ff~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_M2_ff~q ), + .prn(vcc)); // synopsys translate_off -defparam \z80_|execute_|ixy_d~4 .lut_mask = 16'h1100; -defparam \z80_|execute_|ixy_d~4 .sum_lutc_input = "datac"; +defparam \z80_|sequencer_|DFFE_M2_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_M2_ff .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y17_N30 +// Location: LCCOMB_X26_Y13_N6 cycloneive_lcell_comb \z80_|sequencer_|DFFE_M3_ff~0 ( // Equation(s): -// \z80_|sequencer_|DFFE_M3_ff~0_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|DFFE_M3_ff~q ))))) +// \z80_|sequencer_|DFFE_M3_ff~0_combout = (\z80_|execute_|setM1~54_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|DFFE_M3_ff~q ))))) - .dataa(\z80_|execute_|setM1~52_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|execute_|setM1~54_combout ), .datac(\z80_|sequencer_|DFFE_M3_ff~q ), .datad(\z80_|execute_|nextM~14_combout ), .cin(gnd), .combout(\z80_|sequencer_|DFFE_M3_ff~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|sequencer_|DFFE_M3_ff~0 .lut_mask = 16'h88A0; +defparam \z80_|sequencer_|DFFE_M3_ff~0 .lut_mask = 16'h88C0; defparam \z80_|sequencer_|DFFE_M3_ff~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y17_N31 +// Location: FF_X26_Y13_N7 dffeas \z80_|sequencer_|DFFE_M3_ff ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|sequencer_|DFFE_M3_ff~0_combout ), @@ -4303,41 +4288,24 @@ defparam \z80_|sequencer_|DFFE_M3_ff .is_wysiwyg = "true"; defparam \z80_|sequencer_|DFFE_M3_ff .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X37_Y18_N12 -cycloneive_lcell_comb \z80_|execute_|fIOWrite~1 ( -// Equation(s): -// \z80_|execute_|fIOWrite~1_combout = (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|execute_|ixy_d~4_combout ))) - - .dataa(\z80_|execute_|ixy_d~4_combout ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|fIOWrite~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIOWrite~1 .lut_mask = 16'hD0D0; -defparam \z80_|execute_|fIOWrite~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N2 +// Location: LCCOMB_X26_Y13_N10 cycloneive_lcell_comb \z80_|sequencer_|DFFE_M4_ff~0 ( // Equation(s): -// \z80_|sequencer_|DFFE_M4_ff~0_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|DFFE_M4_ff~q ))))) +// \z80_|sequencer_|DFFE_M4_ff~0_combout = (\z80_|execute_|setM1~54_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|DFFE_M4_ff~q ))))) - .dataa(\z80_|execute_|setM1~52_combout ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|execute_|setM1~54_combout ), .datac(\z80_|sequencer_|DFFE_M4_ff~q ), .datad(\z80_|execute_|nextM~14_combout ), .cin(gnd), .combout(\z80_|sequencer_|DFFE_M4_ff~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|sequencer_|DFFE_M4_ff~0 .lut_mask = 16'h88A0; +defparam \z80_|sequencer_|DFFE_M4_ff~0 .lut_mask = 16'h88C0; defparam \z80_|sequencer_|DFFE_M4_ff~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y17_N3 +// Location: FF_X26_Y13_N11 dffeas \z80_|sequencer_|DFFE_M4_ff ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|sequencer_|DFFE_M4_ff~0_combout ), @@ -4356,1685 +4324,24 @@ defparam \z80_|sequencer_|DFFE_M4_ff .is_wysiwyg = "true"; defparam \z80_|sequencer_|DFFE_M4_ff .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y11_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal32~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal32~0_combout = (\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4]) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [3]), - .datac(gnd), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal32~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal32~0 .lut_mask = 16'h00CC; -defparam \z80_|pla_decode_|Equal32~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N14 -cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_11 ( -// Equation(s): -// \z80_|resets_|SYNTHESIZED_WIRE_11~combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_11 .lut_mask = 16'hFF33; -defparam \z80_|resets_|SYNTHESIZED_WIRE_11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N10 -cycloneive_lcell_comb \z80_|decode_state_|table_xx~0 ( -// Equation(s): -// \z80_|decode_state_|table_xx~0_combout = (\z80_|decode_state_|DFFE_instED~q ) # (\z80_|decode_state_|DFFE_instCB~q ) - - .dataa(\z80_|decode_state_|DFFE_instED~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|decode_state_|DFFE_instCB~q ), - .cin(gnd), - .combout(\z80_|decode_state_|table_xx~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|table_xx~0 .lut_mask = 16'hFFAA; -defparam \z80_|decode_state_|table_xx~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N10 -cycloneive_lcell_comb \z80_|pla_decode_|Equal1~7 ( -// Equation(s): -// \z80_|pla_decode_|Equal1~7_combout = (\z80_|ir_|opcode [7] & (!\z80_|decode_state_|table_xx~0_combout & (\z80_|ir_|opcode [0] & \z80_|ir_|opcode [6]))) - - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|decode_state_|table_xx~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|ir_|opcode [6]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal1~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal1~7 .lut_mask = 16'h2000; -defparam \z80_|pla_decode_|Equal1~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N20 -cycloneive_lcell_comb \z80_|pla_decode_|Equal2~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal2~0_combout = (!\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal2~0 .lut_mask = 16'h0F00; -defparam \z80_|pla_decode_|Equal2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N12 -cycloneive_lcell_comb \z80_|pla_decode_|Equal36~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal36~0_combout = (\z80_|pla_decode_|Equal1~7_combout & (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal32~0_combout & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~7_combout ), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|pla_decode_|Equal32~0_combout ), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal36~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal36~0 .lut_mask = 16'h2000; -defparam \z80_|pla_decode_|Equal36~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_cb_set ( -// Equation(s): -// \z80_|execute_|ctl_state_tbl_cb_set~combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|pla_decode_|Equal41~2_combout ) # ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal36~0_combout )))) # -// (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|pla_decode_|Equal36~0_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|pla_decode_|Equal41~2_combout ), - .datad(\z80_|pla_decode_|Equal36~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_tbl_cb_set~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_tbl_cb_set .lut_mask = 16'hB3A0; -defparam \z80_|execute_|ctl_state_tbl_cb_set .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_state_tbl_we~8_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # ((\z80_|sequencer_|DFFE_T3_ff~q & \z80_|pla_decode_|Equal41~2_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|pla_decode_|Equal41~2_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_tbl_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_tbl_we~8 .lut_mask = 16'h00EA; -defparam \z80_|execute_|ctl_state_tbl_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X41_Y17_N29 -dffeas \z80_|decode_state_|DFFE_instCB ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_state_tbl_cb_set~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_state_tbl_we~8_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|decode_state_|DFFE_instCB~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instCB .is_wysiwyg = "true"; -defparam \z80_|decode_state_|DFFE_instCB .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal52~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal52~0_combout = (\z80_|ir_|opcode [7] & (!\z80_|decode_state_|DFFE_instCB~q & (\z80_|ir_|opcode [6] & !\z80_|decode_state_|DFFE_instED~q ))) - - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|decode_state_|DFFE_instCB~q ), - .datac(\z80_|ir_|opcode [6]), - .datad(\z80_|decode_state_|DFFE_instED~q ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal52~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal52~0 .lut_mask = 16'h0020; -defparam \z80_|pla_decode_|Equal52~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal2~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal2~1_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal32~0_combout & \z80_|pla_decode_|Equal52~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|pla_decode_|Equal32~0_combout ), - .datad(\z80_|pla_decode_|Equal52~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal2~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal2~1 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal2~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_ed_set ( -// Equation(s): -// \z80_|execute_|ctl_state_tbl_ed_set~combout = (\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal2~1_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & !\z80_|ir_|opcode [1]))) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|pla_decode_|Equal2~1_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_tbl_ed_set~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_tbl_ed_set .lut_mask = 16'h0008; -defparam \z80_|execute_|ctl_state_tbl_ed_set .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X41_Y17_N17 -dffeas \z80_|decode_state_|DFFE_instED ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_state_tbl_ed_set~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_state_tbl_we~8_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|decode_state_|DFFE_instED~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instED .is_wysiwyg = "true"; -defparam \z80_|decode_state_|DFFE_instED .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal13~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal13~0_combout = (!\z80_|ir_|opcode [7] & (\z80_|ir_|opcode [6] & \z80_|decode_state_|DFFE_instED~q )) - - .dataa(\z80_|ir_|opcode [7]), - .datab(gnd), - .datac(\z80_|ir_|opcode [6]), - .datad(\z80_|decode_state_|DFFE_instED~q ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal13~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal13~0 .lut_mask = 16'h5000; -defparam \z80_|pla_decode_|Equal13~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal33~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal33~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1])) - - .dataa(\z80_|ir_|opcode [0]), - .datab(gnd), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal33~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal33~0 .lut_mask = 16'h5000; -defparam \z80_|pla_decode_|Equal33~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_im_we ( -// Equation(s): -// \z80_|execute_|ctl_im_we~combout = (\z80_|pla_decode_|Equal13~0_combout & (\z80_|sequencer_|DFFE_T3_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|pla_decode_|Equal33~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_im_we~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_im_we .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_im_we .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N18 -cycloneive_lcell_comb \z80_|pla_decode_|Equal49~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal49~0_combout = (!\z80_|decode_state_|in_halt~q & (\z80_|pla_decode_|Equal77~0_combout & \z80_|pla_decode_|Equal33~0_combout )) - - .dataa(gnd), - .datab(\z80_|decode_state_|in_halt~q ), - .datac(\z80_|pla_decode_|Equal77~0_combout ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal49~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal49~0 .lut_mask = 16'h3000; -defparam \z80_|pla_decode_|Equal49~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N2 -cycloneive_lcell_comb \z80_|pla_decode_|Equal33~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal33~1_combout = (\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [5] & !\z80_|ir_|opcode [3])) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|ir_|opcode [3]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal33~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal33~1 .lut_mask = 16'h0808; -defparam \z80_|pla_decode_|Equal33~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N30 -cycloneive_lcell_comb \z80_|pla_decode_|Equal6~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal6~0_combout = (!\z80_|ir_|opcode [7] & (!\z80_|decode_state_|DFFE_instCB~q & (!\z80_|ir_|opcode [6] & !\z80_|decode_state_|DFFE_instED~q ))) - - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|decode_state_|DFFE_instCB~q ), - .datac(\z80_|ir_|opcode [6]), - .datad(\z80_|decode_state_|DFFE_instED~q ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal6~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal6~0 .lut_mask = 16'h0001; -defparam \z80_|pla_decode_|Equal6~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~14 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~14_combout = (!\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal6~0_combout )) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~14 .lut_mask = 16'h4400; -defparam \z80_|execute_|ctl_mRead~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N18 -cycloneive_lcell_comb \z80_|pla_decode_|Equal12~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal12~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2]))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal12~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal12~0 .lut_mask = 16'h0040; -defparam \z80_|pla_decode_|Equal12~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~8 ( -// Equation(s): -// \z80_|execute_|ctl_sw_1d~8_combout = (((!\z80_|ir_|opcode [4] & \z80_|ir_|opcode [5])) # (!\z80_|pla_decode_|Equal12~0_combout )) # (!\z80_|ir_|opcode [3]) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal12~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~8 .lut_mask = 16'h4FFF; -defparam \z80_|execute_|ctl_sw_1d~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N12 -cycloneive_lcell_comb \z80_|nM1_int~2 ( -// Equation(s): -// \z80_|nM1_int~2_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|nM1_int~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|nM1_int~2 .lut_mask = 16'h0055; -defparam \z80_|nM1_int~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~5 ( -// Equation(s): -// \z80_|execute_|ctl_sw_1d~5_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal49~0_combout ) # ((\z80_|execute_|ctl_mRead~14_combout ) # (!\z80_|execute_|ctl_sw_1d~8_combout )))) - - .dataa(\z80_|pla_decode_|Equal49~0_combout ), - .datab(\z80_|execute_|ctl_mRead~14_combout ), - .datac(\z80_|execute_|ctl_sw_1d~8_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~5 .lut_mask = 16'hEF00; -defparam \z80_|execute_|ctl_sw_1d~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal3~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal3~0_combout = (\z80_|ir_|opcode [3] & \z80_|ir_|opcode [4]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal3~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal3~0 .lut_mask = 16'hF000; -defparam \z80_|pla_decode_|Equal3~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~4 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~4_combout = (\z80_|pla_decode_|Equal1~7_combout & (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal3~0_combout & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~7_combout ), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|pla_decode_|Equal3~0_combout ), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~4 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_mRead~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|ixy_d~7 ( -// Equation(s): -// \z80_|execute_|ixy_d~7_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M3_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~7 .lut_mask = 16'h0F00; -defparam \z80_|execute_|ixy_d~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~4 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~4_combout = (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~4 .lut_mask = 16'hA0A0; -defparam \z80_|execute_|ctl_state_alu~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~4 ( -// Equation(s): -// \z80_|execute_|ctl_sw_1d~4_combout = (\z80_|execute_|ctl_mRead~5_combout & (!\z80_|execute_|ctl_state_alu~4_combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|execute_|ctl_mRead~4_combout )))) # (!\z80_|execute_|ctl_mRead~5_combout & -// (((!\z80_|execute_|ixy_d~7_combout )) # (!\z80_|execute_|ctl_mRead~4_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~5_combout ), - .datab(\z80_|execute_|ctl_mRead~4_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~4 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_sw_1d~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N10 -cycloneive_lcell_comb \z80_|pla_decode_|Equal40~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal40~1_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal40~0_combout & \z80_|ir_|opcode [5])) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal40~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal40~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal40~1 .lut_mask = 16'h8080; -defparam \z80_|pla_decode_|Equal40~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal39~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal39~0_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal40~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal3~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal40~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal3~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal39~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal39~0 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal39~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~1 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~1_combout = (!\z80_|pla_decode_|Equal40~1_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal39~0_combout )) - - .dataa(\z80_|pla_decode_|Equal40~1_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~1 .lut_mask = 16'h0005; -defparam \z80_|execute_|ctl_bus_db_oe~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N26 -cycloneive_lcell_comb \z80_|pla_decode_|Equal13~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal13~1_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1])) - - .dataa(\z80_|ir_|opcode [0]), - .datab(gnd), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal13~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal13~1 .lut_mask = 16'hA000; -defparam \z80_|pla_decode_|Equal13~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal13~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal13~2_combout = (\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|pla_decode_|Equal13~1_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal13~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal13~2 .lut_mask = 16'h2000; -defparam \z80_|pla_decode_|Equal13~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal3~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal3~2_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal3~0_combout & \z80_|pla_decode_|Equal52~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|pla_decode_|Equal3~0_combout ), - .datad(\z80_|pla_decode_|Equal52~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal3~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal3~2 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal3~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_state_iy_set~2 ( -// Equation(s): -// \z80_|execute_|ctl_state_iy_set~2_combout = (\z80_|ir_|opcode [5] & (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal3~2_combout & \z80_|sequencer_|DFFE_T2_ff~q ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|pla_decode_|Equal3~2_combout ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_iy_set~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_iy_set~2 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_state_iy_set~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N26 -cycloneive_lcell_comb \z80_|execute_|ixy_d~8 ( -// Equation(s): -// \z80_|execute_|ixy_d~8_combout = (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T5_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|sequencer_|DFFE_T5_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~8 .lut_mask = 16'hC0C0; -defparam \z80_|execute_|ixy_d~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ixy_d~6 ( -// Equation(s): -// \z80_|execute_|ixy_d~6_combout = (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~6 .lut_mask = 16'hF000; -defparam \z80_|execute_|ixy_d~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N6 -cycloneive_lcell_comb \z80_|execute_|ixy_d~9 ( -// Equation(s): -// \z80_|execute_|ixy_d~9_combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_M3_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~9 .lut_mask = 16'hF000; -defparam \z80_|execute_|ixy_d~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N8 -cycloneive_lcell_comb \z80_|execute_|ixy_d~12 ( -// Equation(s): -// \z80_|execute_|ixy_d~12_combout = (!\z80_|execute_|ixy_d~7_combout & (!\z80_|execute_|ixy_d~8_combout & (!\z80_|execute_|ixy_d~6_combout & !\z80_|execute_|ixy_d~9_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ixy_d~8_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|execute_|ixy_d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~12 .lut_mask = 16'h0001; -defparam \z80_|execute_|ixy_d~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N22 -cycloneive_lcell_comb \z80_|execute_|ixy_d~10 ( -// Equation(s): -// \z80_|execute_|ixy_d~10_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|pla_decode_|Equal3~1_combout ), - .datac(\z80_|decode_state_|use_ixiy~combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~10 .lut_mask = 16'h8000; -defparam \z80_|execute_|ixy_d~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal44~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal44~0_combout = (\z80_|ir_|opcode [7] & (!\z80_|decode_state_|DFFE_instCB~q & (!\z80_|ir_|opcode [6] & !\z80_|decode_state_|DFFE_instED~q ))) - - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|decode_state_|DFFE_instCB~q ), - .datac(\z80_|ir_|opcode [6]), - .datad(\z80_|decode_state_|DFFE_instED~q ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal44~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal44~0 .lut_mask = 16'h0002; -defparam \z80_|pla_decode_|Equal44~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N0 -cycloneive_lcell_comb \z80_|execute_|ixy_d~16 ( -// Equation(s): -// \z80_|execute_|ixy_d~16_combout = (\z80_|pla_decode_|Equal44~0_combout & (\z80_|pla_decode_|Equal33~0_combout & ((\z80_|decode_state_|DFFE_inst4~q ) # (\z80_|decode_state_|DFFE_instIY1~q )))) - - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(\z80_|pla_decode_|Equal44~0_combout ), - .datac(\z80_|decode_state_|DFFE_instIY1~q ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~16 .lut_mask = 16'hC800; -defparam \z80_|execute_|ixy_d~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N28 -cycloneive_lcell_comb \z80_|execute_|ixy_d~13 ( -// Equation(s): -// \z80_|execute_|ixy_d~13_combout = (\z80_|pla_decode_|Equal41~2_combout ) # ((\z80_|execute_|ixy_d~10_combout ) # (\z80_|execute_|ixy_d~16_combout )) - - .dataa(gnd), - .datab(\z80_|pla_decode_|Equal41~2_combout ), - .datac(\z80_|execute_|ixy_d~10_combout ), - .datad(\z80_|execute_|ixy_d~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~13 .lut_mask = 16'hFFFC; -defparam \z80_|execute_|ixy_d~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal50~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal50~0_combout = (!\z80_|decode_state_|in_halt~q & (\z80_|pla_decode_|Equal77~0_combout & \z80_|pla_decode_|Equal33~1_combout )) - - .dataa(gnd), - .datab(\z80_|decode_state_|in_halt~q ), - .datac(\z80_|pla_decode_|Equal77~0_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal50~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal50~0 .lut_mask = 16'h3000; -defparam \z80_|pla_decode_|Equal50~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal33~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal33~2_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal6~0_combout )) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal33~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal33~2 .lut_mask = 16'h8800; -defparam \z80_|pla_decode_|Equal33~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N30 -cycloneive_lcell_comb \z80_|execute_|ixy_d~17 ( -// Equation(s): -// \z80_|execute_|ixy_d~17_combout = (\z80_|decode_state_|DFFE_inst4~q & (!\z80_|pla_decode_|Equal50~0_combout & ((!\z80_|pla_decode_|Equal33~2_combout )))) # (!\z80_|decode_state_|DFFE_inst4~q & (((!\z80_|pla_decode_|Equal50~0_combout & -// !\z80_|pla_decode_|Equal33~2_combout )) # (!\z80_|decode_state_|DFFE_instIY1~q ))) - - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(\z80_|pla_decode_|Equal50~0_combout ), - .datac(\z80_|decode_state_|DFFE_instIY1~q ), - .datad(\z80_|pla_decode_|Equal33~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~17 .lut_mask = 16'h0537; -defparam \z80_|execute_|ixy_d~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N16 -cycloneive_lcell_comb \z80_|execute_|ixy_d~5 ( -// Equation(s): -// \z80_|execute_|ixy_d~5_combout = (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_M3_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~5 .lut_mask = 16'hF000; -defparam \z80_|execute_|ixy_d~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N22 -cycloneive_lcell_comb \z80_|execute_|ixy_d~14 ( -// Equation(s): -// \z80_|execute_|ixy_d~14_combout = (\z80_|execute_|ixy_d~12_combout & (((!\z80_|execute_|ixy_d~13_combout & \z80_|execute_|ixy_d~17_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) # (!\z80_|execute_|ixy_d~12_combout & -// (!\z80_|execute_|ixy_d~13_combout & (\z80_|execute_|ixy_d~17_combout ))) - - .dataa(\z80_|execute_|ixy_d~12_combout ), - .datab(\z80_|execute_|ixy_d~13_combout ), - .datac(\z80_|execute_|ixy_d~17_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~14 .lut_mask = 16'h30BA; -defparam \z80_|execute_|ixy_d~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N18 -cycloneive_lcell_comb \z80_|execute_|ixy_d~11 ( -// Equation(s): -// \z80_|execute_|ixy_d~11_combout = (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T5_ff~q ) # ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|execute_|ixy_d~4_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|execute_|ixy_d~4_combout ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~11 .lut_mask = 16'hCC8C; -defparam \z80_|execute_|ixy_d~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N12 -cycloneive_lcell_comb \z80_|execute_|ixy_d~15 ( -// Equation(s): -// \z80_|execute_|ixy_d~15_combout = ((\z80_|pla_decode_|Equal49~0_combout & (\z80_|decode_state_|use_ixiy~combout & \z80_|execute_|ixy_d~11_combout ))) # (!\z80_|execute_|ixy_d~14_combout ) - - .dataa(\z80_|pla_decode_|Equal49~0_combout ), - .datab(\z80_|decode_state_|use_ixiy~combout ), - .datac(\z80_|execute_|ixy_d~14_combout ), - .datad(\z80_|execute_|ixy_d~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~15 .lut_mask = 16'h8F0F; -defparam \z80_|execute_|ixy_d~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_state_ixiy_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_state_ixiy_we~2_combout = (\z80_|sequencer_|DFFE_T5_ff~q & ((\z80_|execute_|ixy_d~15_combout ) # ((\z80_|sequencer_|DFFE_T2_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )))) # (!\z80_|sequencer_|DFFE_T5_ff~q & -// (\z80_|sequencer_|DFFE_T2_ff~q & ((!\z80_|sequencer_|DFFE_M1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|execute_|ixy_d~15_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_ixiy_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_ixiy_we~2 .lut_mask = 16'hA0EC; -defparam \z80_|execute_|ctl_state_ixiy_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y15_N23 -dffeas \z80_|decode_state_|DFFE_instIY1 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_state_iy_set~2_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_state_ixiy_we~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|decode_state_|DFFE_instIY1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instIY1 .is_wysiwyg = "true"; -defparam \z80_|decode_state_|DFFE_instIY1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~5_combout = (!\z80_|decode_state_|DFFE_inst4~q & (!\z80_|decode_state_|DFFE_instIY1~q & \z80_|decode_state_|DFFE_instCB~q )) - - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(gnd), - .datac(\z80_|decode_state_|DFFE_instIY1~q ), - .datad(\z80_|decode_state_|DFFE_instCB~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~5 .lut_mask = 16'h0500; -defparam \z80_|execute_|ctl_ir_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~14 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~14_combout = (!\z80_|ir_|opcode [6] & (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) - - .dataa(\z80_|ir_|opcode [6]), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|execute_|ctl_ir_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~14 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_ir_we~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~2 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~2_combout = (\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [6] & (\z80_|ir_|opcode [7] & \z80_|decode_state_|DFFE_instED~q ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|ir_|opcode [6]), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|decode_state_|DFFE_instED~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~2 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_mWrite~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~16 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~16_combout = (\z80_|ir_|opcode [1] & (\z80_|execute_|ctl_mWrite~2_combout & (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [0]))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~16 .lut_mask = 16'h0008; -defparam \z80_|execute_|ctl_mWrite~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~18 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~18_combout = (((!\z80_|execute_|ctl_ir_we~14_combout & !\z80_|execute_|ctl_mWrite~16_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|sequencer_|DFFE_T4_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|execute_|ctl_ir_we~14_combout ), - .datad(\z80_|execute_|ctl_mWrite~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~18 .lut_mask = 16'h777F; -defparam \z80_|execute_|ctl_flags_alu~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~26 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~26_combout = (\z80_|pla_decode_|Equal13~2_combout & !\z80_|ir_|opcode [3]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~26 .lut_mask = 16'h00F0; -defparam \z80_|execute_|ctl_mRead~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~27 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~27_combout = (\z80_|pla_decode_|Equal13~2_combout & \z80_|ir_|opcode [3]) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(gnd), - .datac(\z80_|ir_|opcode [3]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~27 .lut_mask = 16'hA0A0; -defparam \z80_|execute_|ctl_mRead~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~7 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~7_combout = (\z80_|execute_|ctl_flags_alu~18_combout & (((!\z80_|execute_|ctl_mRead~26_combout & !\z80_|execute_|ctl_mRead~27_combout )) # (!\z80_|execute_|ixy_d~9_combout ))) - - .dataa(\z80_|execute_|ctl_flags_alu~18_combout ), - .datab(\z80_|execute_|ctl_mRead~26_combout ), - .datac(\z80_|execute_|ctl_mRead~27_combout ), - .datad(\z80_|execute_|ixy_d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~7 .lut_mask = 16'h02AA; -defparam \z80_|execute_|ctl_bus_db_oe~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~5 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~5_combout = (\z80_|execute_|ctl_bus_db_oe~7_combout & (((\z80_|execute_|ctl_bus_db_oe~1_combout & !\z80_|pla_decode_|Equal13~2_combout )) # (!\z80_|execute_|ixy_d~7_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~5 .lut_mask = 16'h5D00; -defparam \z80_|execute_|ctl_sw_2d~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~18 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~18_combout = (!\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal12~0_combout ))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal12~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~18 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_mRead~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N12 -cycloneive_lcell_comb \z80_|pla_decode_|Equal55~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal55~0_combout = (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1])) - - .dataa(\z80_|ir_|opcode [0]), - .datab(gnd), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal55~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal55~0 .lut_mask = 16'h0500; -defparam \z80_|pla_decode_|Equal55~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|comb~1 ( -// Equation(s): -// \z80_|execute_|comb~1_combout = (\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4]) - - .dataa(\z80_|ir_|opcode [5]), - .datab(gnd), - .datac(\z80_|ir_|opcode [4]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|comb~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|comb~1 .lut_mask = 16'hA0A0; -defparam \z80_|execute_|comb~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~15 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~15_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [3] & \z80_|execute_|comb~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|execute_|comb~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~15 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_mRead~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~17 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~17_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~17 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_mRead~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~5_combout = ((!\z80_|execute_|ctl_mRead~18_combout & (!\z80_|execute_|ctl_mRead~15_combout & !\z80_|execute_|ctl_mRead~17_combout ))) # (!\z80_|execute_|ixy_d~6_combout ) - - .dataa(\z80_|execute_|ctl_mRead~18_combout ), - .datab(\z80_|execute_|ctl_mRead~15_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|execute_|ctl_mRead~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~5 .lut_mask = 16'h0F1F; -defparam \z80_|execute_|ctl_reg_in_hi~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~9 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~9_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal55~0_combout & \z80_|pla_decode_|Equal33~1_combout )) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~9 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_mRead~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal9~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal9~0_combout = (!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal9~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal9~0 .lut_mask = 16'h000F; -defparam \z80_|pla_decode_|Equal9~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~10 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~10_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal55~0_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal9~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal9~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~10 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_mRead~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~8 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~8_combout = (\z80_|pla_decode_|Equal13~0_combout & (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~8 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_mRead~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~20 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~20_combout = (\z80_|execute_|ctl_mRead~9_combout ) # ((\z80_|execute_|ctl_mRead~15_combout ) # ((\z80_|execute_|ctl_mRead~10_combout ) # (\z80_|execute_|ctl_mRead~8_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~9_combout ), - .datab(\z80_|execute_|ctl_mRead~15_combout ), - .datac(\z80_|execute_|ctl_mRead~10_combout ), - .datad(\z80_|execute_|ctl_mRead~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~20 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_mRead~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal12~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal12~1_combout = (\z80_|pla_decode_|Equal55~0_combout & (!\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal6~0_combout )) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal12~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal12~1 .lut_mask = 16'h2200; -defparam \z80_|pla_decode_|Equal12~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N10 -cycloneive_lcell_comb \z80_|pla_decode_|Equal9~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal9~1_combout = (\z80_|pla_decode_|Equal9~0_combout & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal1~7_combout ))) - - .dataa(\z80_|pla_decode_|Equal9~0_combout ), - .datab(\z80_|pla_decode_|Equal2~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal1~7_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal9~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal9~1 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal9~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal25~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal25~0_combout = (\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal55~0_combout & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal25~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal25~0 .lut_mask = 16'h2000; -defparam \z80_|pla_decode_|Equal25~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~21 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~21_combout = (\z80_|pla_decode_|Equal9~1_combout ) # ((\z80_|execute_|ctl_mRead~17_combout ) # ((!\z80_|pla_decode_|Equal12~1_combout & \z80_|pla_decode_|Equal25~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal12~1_combout ), - .datab(\z80_|pla_decode_|Equal9~1_combout ), - .datac(\z80_|execute_|ctl_mRead~17_combout ), - .datad(\z80_|pla_decode_|Equal25~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~21 .lut_mask = 16'hFDFC; -defparam \z80_|execute_|ctl_mRead~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~6 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~6_combout = (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_M4_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~6 .lut_mask = 16'hA0A0; -defparam \z80_|execute_|ctl_state_alu~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal19~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal19~0_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal32~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal1~7_combout ))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|pla_decode_|Equal32~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal1~7_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal19~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal19~0 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal19~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N30 -cycloneive_lcell_comb \z80_|pla_decode_|Equal1~4 ( -// Equation(s): -// \z80_|pla_decode_|Equal1~4_combout = (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [1]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal1~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal1~4 .lut_mask = 16'h000F; -defparam \z80_|pla_decode_|Equal1~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N2 -cycloneive_lcell_comb \z80_|pla_decode_|Equal29~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal29~0_combout = (\z80_|pla_decode_|Equal1~7_combout & (\z80_|pla_decode_|Equal1~4_combout & (\z80_|pla_decode_|Equal32~0_combout & !\z80_|ir_|opcode [5]))) - - .dataa(\z80_|pla_decode_|Equal1~7_combout ), - .datab(\z80_|pla_decode_|Equal1~4_combout ), - .datac(\z80_|pla_decode_|Equal32~0_combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal29~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal29~0 .lut_mask = 16'h0080; -defparam \z80_|pla_decode_|Equal29~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N20 -cycloneive_lcell_comb \z80_|pla_decode_|Equal24~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal24~1_combout = (\z80_|pla_decode_|Equal9~0_combout & (\z80_|pla_decode_|Equal2~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal1~7_combout ))) - - .dataa(\z80_|pla_decode_|Equal9~0_combout ), - .datab(\z80_|pla_decode_|Equal2~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal1~7_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal24~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal24~1 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal24~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N18 -cycloneive_lcell_comb \z80_|pla_decode_|Equal34~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal34~0_combout = (!\z80_|ir_|opcode [0] & (!\z80_|decode_state_|table_xx~0_combout & (\z80_|pla_decode_|Equal3~1_combout & \z80_|pla_decode_|Equal41~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|decode_state_|table_xx~0_combout ), - .datac(\z80_|pla_decode_|Equal3~1_combout ), - .datad(\z80_|pla_decode_|Equal41~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal34~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal34~0 .lut_mask = 16'h1000; -defparam \z80_|pla_decode_|Equal34~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal37~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal37~0_combout = (\z80_|pla_decode_|Equal41~0_combout & (!\z80_|decode_state_|table_xx~0_combout & (!\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal1~4_combout ))) - - .dataa(\z80_|pla_decode_|Equal41~0_combout ), - .datab(\z80_|decode_state_|table_xx~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal1~4_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal37~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal37~0 .lut_mask = 16'h0200; -defparam \z80_|pla_decode_|Equal37~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N12 -cycloneive_lcell_comb \z80_|pla_decode_|Equal35~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal35~0_combout = (\z80_|pla_decode_|Equal41~0_combout & (!\z80_|decode_state_|table_xx~0_combout & (!\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal41~0_combout ), - .datab(\z80_|decode_state_|table_xx~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal35~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal35~0 .lut_mask = 16'h0200; -defparam \z80_|pla_decode_|Equal35~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N14 -cycloneive_lcell_comb \z80_|pla_decode_|Equal38~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal38~2_combout = (!\z80_|ir_|opcode [1] & (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [2] & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal38~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal38~2 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal38~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N14 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~2 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~2_combout = (\z80_|pla_decode_|Equal34~0_combout ) # ((\z80_|pla_decode_|Equal37~0_combout ) # ((\z80_|pla_decode_|Equal35~0_combout ) # (\z80_|pla_decode_|Equal38~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal34~0_combout ), - .datab(\z80_|pla_decode_|Equal37~0_combout ), - .datac(\z80_|pla_decode_|Equal35~0_combout ), - .datad(\z80_|pla_decode_|Equal38~2_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~2 .lut_mask = 16'hFFFE; -defparam \z80_|reg_control_|reg_sys_we_lo~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N22 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~3 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~3_combout = (\z80_|pla_decode_|Equal19~0_combout ) # ((\z80_|pla_decode_|Equal29~0_combout ) # ((\z80_|pla_decode_|Equal24~1_combout ) # (\z80_|reg_control_|reg_sys_we_lo~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal19~0_combout ), - .datab(\z80_|pla_decode_|Equal29~0_combout ), - .datac(\z80_|pla_decode_|Equal24~1_combout ), - .datad(\z80_|reg_control_|reg_sys_we_lo~2_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~3 .lut_mask = 16'hFFFE; -defparam \z80_|reg_control_|reg_sys_we_lo~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N4 -cycloneive_lcell_comb \z80_|execute_|comb~0 ( -// Equation(s): -// \z80_|execute_|comb~0_combout = (\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1]) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [2]), - .datac(\z80_|ir_|opcode [1]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|comb~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|comb~0 .lut_mask = 16'hC0C0; -defparam \z80_|execute_|comb~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N30 -cycloneive_lcell_comb \z80_|pla_decode_|Equal47~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal47~0_combout = (\z80_|pla_decode_|Equal41~0_combout & (!\z80_|decode_state_|table_xx~0_combout & (\z80_|ir_|opcode [0] & \z80_|execute_|comb~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal41~0_combout ), - .datab(\z80_|decode_state_|table_xx~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|execute_|comb~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal47~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal47~0 .lut_mask = 16'h2000; -defparam \z80_|pla_decode_|Equal47~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N8 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~4 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~4_combout = (\z80_|execute_|ctl_state_alu~6_combout & (!\z80_|pla_decode_|Equal47~0_combout & ((!\z80_|reg_control_|reg_sys_we_lo~3_combout ) # (!\z80_|execute_|ctl_state_alu~4_combout )))) # -// (!\z80_|execute_|ctl_state_alu~6_combout & (((!\z80_|reg_control_|reg_sys_we_lo~3_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~6_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|reg_control_|reg_sys_we_lo~3_combout ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~4 .lut_mask = 16'h153F; -defparam \z80_|reg_control_|reg_sys_we_lo~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~22 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~22_combout = (\z80_|reg_control_|reg_sys_we_lo~4_combout & (((!\z80_|execute_|ctl_mRead~20_combout & !\z80_|execute_|ctl_mRead~21_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~20_combout ), - .datab(\z80_|execute_|ctl_mRead~21_combout ), - .datac(\z80_|reg_control_|reg_sys_we_lo~4_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~22 .lut_mask = 16'h10F0; -defparam \z80_|execute_|ctl_mRead~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~24 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~24_combout = (\z80_|execute_|ctl_reg_in_hi~5_combout & (\z80_|execute_|ctl_mRead~22_combout & ((!\z80_|execute_|ctl_state_alu~6_combout ) # (!\z80_|execute_|ctl_mRead~18_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~18_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~5_combout ), - .datac(\z80_|execute_|ctl_mRead~22_combout ), - .datad(\z80_|execute_|ctl_state_alu~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~24 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_mRead~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout = (\z80_|pla_decode_|Equal52~0_combout & (!\z80_|ir_|opcode [0] & (\z80_|execute_|ixy_d~6_combout & \z80_|pla_decode_|Equal3~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal52~0_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|pla_decode_|Equal3~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~6_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & (((!\z80_|pla_decode_|Equal19~0_combout & !\z80_|pla_decode_|Equal35~0_combout )) # (!\z80_|execute_|ixy_d~6_combout ))) - - .dataa(\z80_|pla_decode_|Equal19~0_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|pla_decode_|Equal35~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~6 .lut_mask = 16'h0313; -defparam \z80_|execute_|ctl_reg_in_hi~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N20 -cycloneive_lcell_comb \z80_|pla_decode_|Equal6~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal6~1_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal1~4_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal1~4_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal6~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal6~1 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal6~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~16 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~16_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal1~4_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal52~0_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal1~4_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal52~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~16 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_mRead~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N16 +// Location: LCCOMB_X26_Y13_N0 cycloneive_lcell_comb \z80_|sequencer_|M5~0 ( // Equation(s): -// \z80_|sequencer_|M5~0_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|M5~q ))))) +// \z80_|sequencer_|M5~0_combout = (\z80_|execute_|setM1~54_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|M5~q ))))) - .dataa(\z80_|execute_|setM1~52_combout ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|execute_|setM1~54_combout ), .datac(\z80_|sequencer_|M5~q ), .datad(\z80_|execute_|nextM~14_combout ), .cin(gnd), .combout(\z80_|sequencer_|M5~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|sequencer_|M5~0 .lut_mask = 16'h88A0; +defparam \z80_|sequencer_|M5~0 .lut_mask = 16'h88C0; defparam \z80_|sequencer_|M5~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y17_N17 +// Location: FF_X26_Y13_N1 dffeas \z80_|sequencer_|M5 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|sequencer_|M5~0_combout ), @@ -6053,12847 +4360,427 @@ defparam \z80_|sequencer_|M5 .is_wysiwyg = "true"; defparam \z80_|sequencer_|M5 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X38_Y17_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~2 ( +// Location: LCCOMB_X24_Y11_N10 +cycloneive_lcell_comb \z80_|execute_|ixy_d~5 ( // Equation(s): -// \z80_|execute_|ctl_reg_in_hi~2_combout = (\z80_|sequencer_|M5~q & \z80_|sequencer_|DFFE_T3_ff~q ) +// \z80_|execute_|ixy_d~5_combout = (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ) .dataa(gnd), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), .datad(gnd), .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .combout(\z80_|execute_|ixy_d~5_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~2 .lut_mask = 16'hC0C0; -defparam \z80_|execute_|ctl_reg_in_hi~2 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ixy_d~5 .lut_mask = 16'hC0C0; +defparam \z80_|execute_|ixy_d~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|setM1~29 ( -// Equation(s): -// \z80_|execute_|setM1~29_combout = (\z80_|execute_|ctl_mRead~16_combout & (!\z80_|execute_|ixy_d~6_combout & ((!\z80_|execute_|ctl_mRead~17_combout ) # (!\z80_|execute_|ctl_reg_in_hi~2_combout )))) # (!\z80_|execute_|ctl_mRead~16_combout & -// (((!\z80_|execute_|ctl_mRead~17_combout ) # (!\z80_|execute_|ctl_reg_in_hi~2_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~16_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datad(\z80_|execute_|ctl_mRead~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~29 .lut_mask = 16'h0777; -defparam \z80_|execute_|setM1~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~25 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~25_combout = (\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|execute_|ctl_mRead~16_combout & ((!\z80_|execute_|ctl_state_alu~6_combout ) # (!\z80_|execute_|ctl_mRead~17_combout )))) # (!\z80_|execute_|ctl_state_alu~4_combout -// & (((!\z80_|execute_|ctl_state_alu~6_combout )) # (!\z80_|execute_|ctl_mRead~17_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_mRead~17_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_mRead~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~25 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_mRead~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~6_combout = (\z80_|execute_|setM1~29_combout & (\z80_|execute_|ctl_mRead~25_combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|pla_decode_|Equal6~1_combout )))) - - .dataa(\z80_|pla_decode_|Equal6~1_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|execute_|setM1~29_combout ), - .datad(\z80_|execute_|ctl_mRead~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~6 .lut_mask = 16'h7000; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~7_combout = (!\z80_|ir_|opcode [6] & (\z80_|pla_decode_|Equal33~0_combout & (\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) - - .dataa(\z80_|ir_|opcode [6]), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|execute_|ctl_ir_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~7 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_ir_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N2 -cycloneive_lcell_comb \z80_|pla_decode_|Equal52~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal52~1_combout = (!\z80_|decode_state_|DFFE_instED~q & (\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal41~0_combout & !\z80_|decode_state_|DFFE_instCB~q ))) - - .dataa(\z80_|decode_state_|DFFE_instED~q ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|pla_decode_|Equal41~0_combout ), - .datad(\z80_|decode_state_|DFFE_instCB~q ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal52~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal52~1 .lut_mask = 16'h0040; -defparam \z80_|pla_decode_|Equal52~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~14 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~14_combout = (!\z80_|decode_state_|DFFE_inst4~q & (\z80_|pla_decode_|Equal44~0_combout & (!\z80_|decode_state_|DFFE_instIY1~q & \z80_|pla_decode_|Equal33~0_combout ))) - - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(\z80_|pla_decode_|Equal44~0_combout ), - .datac(\z80_|decode_state_|DFFE_instIY1~q ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~14 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_state_alu~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~8 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~8_combout = (\z80_|execute_|ctl_state_alu~4_combout & (((!\z80_|pla_decode_|Equal52~1_combout & !\z80_|execute_|ctl_state_alu~14_combout )))) # (!\z80_|execute_|ctl_state_alu~4_combout & -// (((!\z80_|execute_|ctl_state_alu~14_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_state_alu~6_combout ), - .datac(\z80_|pla_decode_|Equal52~1_combout ), - .datad(\z80_|execute_|ctl_state_alu~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~8 .lut_mask = 16'h115F; -defparam \z80_|execute_|ctl_state_alu~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N20 -cycloneive_lcell_comb \z80_|pla_decode_|Equal24~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal24~0_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|pla_decode_|Equal52~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal24~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal24~0 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal24~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N0 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_pc~0_combout = ((!\z80_|pla_decode_|Equal37~0_combout & ((!\z80_|pla_decode_|Equal9~0_combout ) # (!\z80_|pla_decode_|Equal24~0_combout )))) # (!\z80_|execute_|ixy_d~6_combout ) - - .dataa(\z80_|pla_decode_|Equal24~0_combout ), - .datab(\z80_|pla_decode_|Equal37~0_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|pla_decode_|Equal9~0_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_pc~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_pc~0 .lut_mask = 16'h1F3F; -defparam \z80_|reg_control_|reg_sel_pc~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N26 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~1 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_pc~1_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ctl_reg_in_hi~2_combout & ((!\z80_|pla_decode_|Equal29~0_combout ) # (!\z80_|execute_|ixy_d~6_combout )))) # (!\z80_|pla_decode_|Equal47~0_combout & -// (((!\z80_|pla_decode_|Equal29~0_combout )) # (!\z80_|execute_|ixy_d~6_combout ))) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datad(\z80_|pla_decode_|Equal29~0_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_pc~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_pc~1 .lut_mask = 16'h135F; -defparam \z80_|reg_control_|reg_sel_pc~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N12 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~2 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_pc~2_combout = (\z80_|reg_control_|reg_sel_pc~0_combout & (\z80_|reg_control_|reg_sel_pc~1_combout & ((!\z80_|pla_decode_|Equal38~2_combout ) # (!\z80_|execute_|ixy_d~6_combout )))) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|reg_control_|reg_sel_pc~0_combout ), - .datac(\z80_|reg_control_|reg_sel_pc~1_combout ), - .datad(\z80_|pla_decode_|Equal38~2_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_pc~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_pc~2 .lut_mask = 16'h40C0; -defparam \z80_|reg_control_|reg_sel_pc~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|fMRead~17 ( -// Equation(s): -// \z80_|execute_|fMRead~17_combout = (\z80_|execute_|ctl_state_alu~8_combout & (\z80_|reg_control_|reg_sel_pc~2_combout & ((!\z80_|execute_|ctl_ir_we~7_combout ) # (!\z80_|execute_|ctl_state_alu~4_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_ir_we~7_combout ), - .datac(\z80_|execute_|ctl_state_alu~8_combout ), - .datad(\z80_|reg_control_|reg_sel_pc~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~17 .lut_mask = 16'h7000; -defparam \z80_|execute_|fMRead~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~6 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~6_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal3~1_combout & (!\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|pla_decode_|Equal3~1_combout ), - .datac(\z80_|decode_state_|use_ixiy~combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~6 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_mRead~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal11~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal11~0_combout = (!\z80_|ir_|opcode [1] & (\z80_|execute_|ctl_mWrite~2_combout & (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [0]))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal11~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal11~0 .lut_mask = 16'h0004; -defparam \z80_|pla_decode_|Equal11~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal10~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal10~0_combout = (!\z80_|ir_|opcode [1] & (\z80_|execute_|ctl_mWrite~2_combout & (!\z80_|ir_|opcode [2] & \z80_|ir_|opcode [0]))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal10~0 .lut_mask = 16'h0400; -defparam \z80_|pla_decode_|Equal10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~9_combout = (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|pla_decode_|Equal10~0_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(\z80_|pla_decode_|Equal11~0_combout ), - .datab(\z80_|pla_decode_|Equal10~0_combout ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~9 .lut_mask = 16'h1FFF; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~4 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~4_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & (((!\z80_|execute_|ctl_state_alu~4_combout & !\z80_|execute_|ctl_state_alu~6_combout )) # (!\z80_|execute_|ctl_mRead~6_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_state_alu~6_combout ), - .datac(\z80_|execute_|ctl_mRead~6_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~4 .lut_mask = 16'h1F00; -defparam \z80_|execute_|ctl_sw_2d~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~15 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~15_combout = (\z80_|ir_|opcode [6] & (\z80_|pla_decode_|Equal33~0_combout & (\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) - - .dataa(\z80_|ir_|opcode [6]), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|execute_|ctl_ir_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~15 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_ir_we~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|fMRead~16 ( -// Equation(s): -// \z80_|execute_|fMRead~16_combout = (\z80_|execute_|ctl_reg_in_hi~2_combout & (!\z80_|execute_|ctl_mRead~18_combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_ir_we~15_combout )))) # (!\z80_|execute_|ctl_reg_in_hi~2_combout & -// (((!\z80_|execute_|ctl_state_alu~4_combout )) # (!\z80_|execute_|ctl_ir_we~15_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_mRead~18_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~16 .lut_mask = 16'h135F; -defparam \z80_|execute_|fMRead~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~9 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~9_combout = (\z80_|execute_|ctl_ir_we~5_combout & (\z80_|pla_decode_|Equal41~0_combout & ((!\z80_|decode_state_|DFFE_instCB~q ) # (!\z80_|pla_decode_|Equal33~0_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~5_combout ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|pla_decode_|Equal41~0_combout ), - .datad(\z80_|decode_state_|DFFE_instCB~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~9 .lut_mask = 16'h20A0; -defparam \z80_|execute_|ctl_ir_we~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N22 -cycloneive_lcell_comb \z80_|pla_decode_|Equal46~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal46~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [1] & (\z80_|ir_|opcode [2] & \z80_|decode_state_|DFFE_instCB~q ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [1]), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|decode_state_|DFFE_instCB~q ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal46~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal46~0 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal46~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~10 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~10_combout = (!\z80_|ir_|opcode [6] & (!\z80_|pla_decode_|Equal46~0_combout & (\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) - - .dataa(\z80_|ir_|opcode [6]), - .datab(\z80_|pla_decode_|Equal46~0_combout ), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|execute_|ctl_ir_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~10 .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_ir_we~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~17 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~17_combout = (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|execute_|ctl_ir_we~7_combout ), - .datad(\z80_|execute_|ctl_ir_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~17 .lut_mask = 16'h777F; -defparam \z80_|execute_|ctl_flags_alu~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~6_combout = (\z80_|execute_|ctl_flags_alu~17_combout & (((!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~9_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~15_combout ), - .datab(\z80_|execute_|ctl_ir_we~9_combout ), - .datac(\z80_|execute_|ctl_flags_alu~17_combout ), - .datad(\z80_|execute_|ctl_state_alu~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~6 .lut_mask = 16'h10F0; -defparam \z80_|execute_|ctl_flags_alu~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~6_combout = (!\z80_|ir_|opcode [6] & !\z80_|ir_|opcode [7]) - - .dataa(\z80_|ir_|opcode [6]), - .datab(gnd), - .datac(\z80_|ir_|opcode [7]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~6 .lut_mask = 16'h0505; -defparam \z80_|execute_|ctl_ir_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~8_combout = (\z80_|execute_|ctl_ir_we~5_combout & (\z80_|execute_|ctl_ir_we~6_combout & ((!\z80_|decode_state_|DFFE_instCB~q ) # (!\z80_|pla_decode_|Equal33~0_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~5_combout ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|execute_|ctl_ir_we~6_combout ), - .datad(\z80_|decode_state_|DFFE_instCB~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~8 .lut_mask = 16'h20A0; -defparam \z80_|execute_|ctl_ir_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~16 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~16_combout = (((!\z80_|execute_|ctl_ir_we~8_combout & !\z80_|execute_|ctl_ir_we~14_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M4_ff~q ) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|execute_|ctl_ir_we~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~16 .lut_mask = 16'h3F7F; -defparam \z80_|execute_|ctl_flags_alu~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~3_combout = ((!\z80_|execute_|ctl_mRead~8_combout & (!\z80_|execute_|ctl_mRead~10_combout & !\z80_|execute_|ctl_mRead~9_combout ))) # (!\z80_|execute_|ixy_d~6_combout ) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|execute_|ctl_mRead~8_combout ), - .datac(\z80_|execute_|ctl_mRead~10_combout ), - .datad(\z80_|execute_|ctl_mRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~3 .lut_mask = 16'h5557; -defparam \z80_|execute_|ctl_reg_in_hi~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~8 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~8_combout = (\z80_|execute_|ctl_flags_alu~6_combout & (\z80_|execute_|ctl_flags_alu~16_combout & \z80_|execute_|ctl_reg_in_hi~3_combout )) - - .dataa(\z80_|execute_|ctl_flags_alu~6_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_flags_alu~16_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~8 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_mWrite~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|fMRead~18 ( -// Equation(s): -// \z80_|execute_|fMRead~18_combout = (\z80_|execute_|fMRead~17_combout & (\z80_|execute_|ctl_sw_2d~4_combout & (\z80_|execute_|fMRead~16_combout & \z80_|execute_|ctl_mWrite~8_combout ))) - - .dataa(\z80_|execute_|fMRead~17_combout ), - .datab(\z80_|execute_|ctl_sw_2d~4_combout ), - .datac(\z80_|execute_|fMRead~16_combout ), - .datad(\z80_|execute_|ctl_mWrite~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~18 .lut_mask = 16'h8000; -defparam \z80_|execute_|fMRead~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N26 -cycloneive_lcell_comb \z80_|execute_|fMRead~19 ( -// Equation(s): -// \z80_|execute_|fMRead~19_combout = (\z80_|execute_|ctl_mRead~24_combout & (\z80_|execute_|ctl_reg_in_hi~6_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~6_combout & \z80_|execute_|fMRead~18_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~24_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~6_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), - .datad(\z80_|execute_|fMRead~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~19 .lut_mask = 16'h8000; -defparam \z80_|execute_|fMRead~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~16 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~16_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|execute_|ixy_d~15_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~16 .lut_mask = 16'h0F00; -defparam \z80_|execute_|ctl_alu_shift_oe~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~36 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~36_combout = (\z80_|ir_|opcode [1] & (\z80_|execute_|ctl_mWrite~2_combout & (!\z80_|ir_|opcode [2] & \z80_|ir_|opcode [0]))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~36 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_mRead~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~9_combout = (\z80_|pla_decode_|Equal1~4_combout & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [0] & \z80_|execute_|ctl_mWrite~3_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~4_combout ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|execute_|ctl_mWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~9 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_alu_op_low~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~44 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~44_combout = (!\z80_|execute_|ctl_alu_op_low~9_combout & (((!\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|execute_|ctl_mRead~36_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|execute_|ctl_mRead~36_combout ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|execute_|ctl_alu_op_low~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~44 .lut_mask = 16'h007F; -defparam \z80_|execute_|ctl_alu_shift_oe~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~11 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~11_combout = (\z80_|sequencer_|DFFE_T5_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~11 .lut_mask = 16'h00AA; -defparam \z80_|execute_|ctl_mRead~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~6 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~6_combout = (\z80_|execute_|ixy_d~6_combout & (!\z80_|pla_decode_|Equal9~1_combout & ((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_mRead~11_combout )))) # (!\z80_|execute_|ixy_d~6_combout & -// (((!\z80_|pla_decode_|Equal47~0_combout )) # (!\z80_|execute_|ctl_mRead~11_combout ))) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|execute_|ctl_mRead~11_combout ), - .datac(\z80_|pla_decode_|Equal47~0_combout ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~6 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_sw_2d~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~7 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~7_combout = (\z80_|execute_|ctl_sw_2d~6_combout & (((!\z80_|execute_|ctl_mRead~4_combout & !\z80_|pla_decode_|Equal6~1_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_sw_2d~6_combout ), - .datab(\z80_|execute_|ctl_mRead~4_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal6~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~7 .lut_mask = 16'h0A2A; -defparam \z80_|execute_|ctl_sw_2d~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~7 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~7_combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_M4_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|sequencer_|DFFE_M4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~7 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_mWrite~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~11 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~11_combout = (\z80_|ir_|opcode [6] & (!\z80_|pla_decode_|Equal46~0_combout & (!\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) - - .dataa(\z80_|ir_|opcode [6]), - .datab(\z80_|pla_decode_|Equal46~0_combout ), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|execute_|ctl_ir_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~11 .lut_mask = 16'h0200; -defparam \z80_|execute_|ctl_ir_we~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~12 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~12_combout = (\z80_|ir_|opcode [6] & (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) - - .dataa(\z80_|ir_|opcode [6]), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|execute_|ctl_ir_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~12 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_ir_we~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~0 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~0_combout = (\z80_|execute_|ctl_mWrite~7_combout & (!\z80_|execute_|ctl_ir_we~11_combout & ((!\z80_|execute_|ctl_ir_we~12_combout )))) # (!\z80_|execute_|ctl_mWrite~7_combout & (((!\z80_|execute_|ctl_ir_we~12_combout ) # -// (!\z80_|execute_|ctl_mWrite~3_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~7_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_mWrite~3_combout ), - .datad(\z80_|execute_|ctl_ir_we~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~0 .lut_mask = 16'h0577; -defparam \z80_|execute_|ctl_flags_sz_we~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout = (\z80_|pla_decode_|Equal1~4_combout & (!\z80_|ir_|opcode [0] & (\z80_|nM1_int~2_combout & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~4_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~8 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~8_combout = (\z80_|execute_|ctl_alu_shift_oe~44_combout & (\z80_|execute_|ctl_sw_2d~7_combout & (\z80_|execute_|ctl_flags_sz_we~0_combout & !\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~44_combout ), - .datab(\z80_|execute_|ctl_sw_2d~7_combout ), - .datac(\z80_|execute_|ctl_flags_sz_we~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~8 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_sw_2d~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~9 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~9_combout = (\z80_|execute_|ctl_sw_2d~5_combout & (\z80_|execute_|fMRead~19_combout & (!\z80_|execute_|ctl_alu_shift_oe~16_combout & \z80_|execute_|ctl_sw_2d~8_combout ))) - - .dataa(\z80_|execute_|ctl_sw_2d~5_combout ), - .datab(\z80_|execute_|fMRead~19_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~16_combout ), - .datad(\z80_|execute_|ctl_sw_2d~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~9 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_sw_2d~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~6 ( -// Equation(s): -// \z80_|execute_|ctl_sw_1d~6_combout = (!\z80_|execute_|ctl_im_we~combout & (!\z80_|execute_|ctl_sw_1d~5_combout & (\z80_|execute_|ctl_sw_1d~4_combout & \z80_|execute_|ctl_sw_2d~9_combout ))) - - .dataa(\z80_|execute_|ctl_im_we~combout ), - .datab(\z80_|execute_|ctl_sw_1d~5_combout ), - .datac(\z80_|execute_|ctl_sw_1d~4_combout ), - .datad(\z80_|execute_|ctl_sw_2d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~6 .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_sw_1d~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~7 ( -// Equation(s): -// \z80_|execute_|ctl_sw_1d~7_combout = ((!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & \z80_|pla_decode_|Equal47~0_combout ))) # (!\z80_|execute_|ctl_sw_1d~6_combout ) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|execute_|ctl_sw_1d~6_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~7 .lut_mask = 16'h7333; -defparam \z80_|execute_|ctl_sw_1d~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y18_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~8_combout = (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~8 .lut_mask = 16'hC0C0; -defparam \z80_|execute_|ctl_alu_op_low~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y18_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout = (\z80_|execute_|ctl_mWrite~2_combout & (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal2~0_combout & \z80_|execute_|ctl_alu_op_low~8_combout ))) - - .dataa(\z80_|execute_|ctl_mWrite~2_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|pla_decode_|Equal2~0_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|execute_|ixy_d~15_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~39 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~39_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout & (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & ((!\z80_|execute_|ctl_mRead~36_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_mRead~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~39 .lut_mask = 16'h0111; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|pla_decode_|Equal21~1_combout & !\z80_|sequencer_|DFFE_M1_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|pla_decode_|Equal21~1_combout ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 .lut_mask = 16'h0088; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_hi~4_combout = ((!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal40~1_combout & !\z80_|pla_decode_|Equal39~0_combout ))) # (!\z80_|execute_|ixy_d~9_combout ) - - .dataa(\z80_|execute_|ixy_d~9_combout ), - .datab(\z80_|pla_decode_|Equal21~1_combout ), - .datac(\z80_|pla_decode_|Equal40~1_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_hi~4 .lut_mask = 16'h5557; -defparam \z80_|execute_|ctl_reg_out_hi~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~15 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~15_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal6~0_combout & (!\z80_|pla_decode_|Equal33~1_combout & \z80_|pla_decode_|Equal3~1_combout ))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|pla_decode_|Equal33~1_combout ), - .datad(\z80_|pla_decode_|Equal3~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~15 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_alu_shift_oe~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~38 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~38_combout = (!\z80_|execute_|ctl_alu_shift_oe~15_combout & (((!\z80_|execute_|ctl_state_alu~4_combout & !\z80_|execute_|ctl_state_alu~6_combout )) # (!\z80_|execute_|ctl_mRead~6_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~38 .lut_mask = 16'h0037; -defparam \z80_|execute_|ctl_alu_shift_oe~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_zero ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_zero~combout = ((\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~38_combout ) # (!\z80_|execute_|ctl_reg_out_hi~4_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), - .datac(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_zero .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_alu_op2_sel_zero .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N14 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~4 ( -// Equation(s): -// \z80_|alu_|db_low[2]~4_combout = ((\z80_|bus_control_|db[4]~19_combout & (!\z80_|bus_control_|db[5]~15_combout & !\z80_|bus_control_|db[3]~21_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datab(\z80_|bus_control_|db[4]~19_combout ), - .datac(\z80_|bus_control_|db[5]~15_combout ), - .datad(\z80_|bus_control_|db[3]~21_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~4 .lut_mask = 16'h555D; -defparam \z80_|alu_|db_low[2]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~14_combout = (\z80_|sequencer_|DFFE_M4_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~14 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_alu_shift_oe~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~11 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[0]~11_combout = ((!\z80_|pla_decode_|Equal40~1_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal39~0_combout ))) # (!\z80_|execute_|ixy_d~5_combout ) - - .dataa(\z80_|pla_decode_|Equal40~1_combout ), - .datab(\z80_|pla_decode_|Equal21~1_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~11 .lut_mask = 16'h0F1F; -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~1 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~1_combout = (\z80_|execute_|ctl_reg_out_hi~4_combout & \z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~1 .lut_mask = 16'hCC00; -defparam \z80_|execute_|ctl_sw_4u~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~5_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout & (((!\z80_|pla_decode_|Equal21~1_combout & !\z80_|execute_|ctl_mRead~36_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), - .datab(\z80_|pla_decode_|Equal21~1_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_mRead~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~5 .lut_mask = 16'h0515; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~30 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~30_combout = (\z80_|execute_|ctl_sw_4u~1_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~5_combout & ((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|execute_|ctl_sw_4u~1_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~30 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_alu_shift_oe~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~29 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~29_combout = (\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|execute_|ctl_mRead~36_combout & ((!\z80_|execute_|ctl_mWrite~3_combout ) # (!\z80_|execute_|ctl_mWrite~16_combout )))) # -// (!\z80_|execute_|ctl_state_alu~4_combout & (((!\z80_|execute_|ctl_mWrite~3_combout )) # (!\z80_|execute_|ctl_mWrite~16_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_mWrite~16_combout ), - .datac(\z80_|execute_|ctl_mRead~36_combout ), - .datad(\z80_|execute_|ctl_mWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~29 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_alu_shift_oe~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~31 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~31_combout = (\z80_|execute_|ctl_alu_shift_oe~30_combout & (\z80_|execute_|ctl_alu_shift_oe~29_combout & ((!\z80_|execute_|ctl_mRead~11_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~30_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~29_combout ), - .datad(\z80_|execute_|ctl_mRead~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~31 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_alu_shift_oe~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal69~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal69~0_combout = (!\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|pla_decode_|Equal13~1_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal69~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal69~0 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal69~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N24 -cycloneive_lcell_comb \z80_|pla_decode_|Equal1~5 ( -// Equation(s): -// \z80_|pla_decode_|Equal1~5_combout = (\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [5]) - - .dataa(\z80_|ir_|opcode [4]), - .datab(gnd), - .datac(gnd), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal1~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal1~5 .lut_mask = 16'h00AA; -defparam \z80_|pla_decode_|Equal1~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~14_combout = (\z80_|pla_decode_|Equal1~5_combout & (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~5_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|pla_decode_|Equal13~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~14 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_op_low~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~12 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~12_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal2~0_combout & (!\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal2~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~12 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_alu_op_low~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal56~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal56~0_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal1~4_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal1~4_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal56~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal56~0 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal56~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~11_combout = (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~11 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_alu_op_low~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|nextM~2 ( -// Equation(s): -// \z80_|execute_|nextM~2_combout = (!\z80_|execute_|ctl_alu_op_low~12_combout & (!\z80_|pla_decode_|Equal56~0_combout & !\z80_|execute_|ctl_alu_op_low~11_combout )) - - .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_alu_op_low~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~2 .lut_mask = 16'h0011; -defparam \z80_|execute_|nextM~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~16 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~16_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # ((\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T3_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|execute_|nextM~2_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~16 .lut_mask = 16'h0F08; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~4_combout = (!\z80_|execute_|ctl_alu_op_low~14_combout & (!\z80_|execute_|ctl_alu_op1_sel_bus~16_combout & ((!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # (!\z80_|pla_decode_|Equal69~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal69~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~4 .lut_mask = 16'h0103; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~5_combout = (\z80_|execute_|ctl_alu_shift_oe~38_combout & \z80_|execute_|ctl_alu_op1_sel_bus~4_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~5 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~3 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~3_combout = (\z80_|pla_decode_|Equal77~0_combout & ((\z80_|decode_state_|in_halt~q ) # ((!\z80_|pla_decode_|Equal33~1_combout & !\z80_|pla_decode_|Equal33~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|decode_state_|in_halt~q ), - .datac(\z80_|pla_decode_|Equal77~0_combout ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~3 .lut_mask = 16'hC0D0; -defparam \z80_|execute_|ctl_alu_oe~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~15 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~15_combout = ((!\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|execute_|ixy_d~15_combout ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|execute_|ixy_d~15_combout ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~15 .lut_mask = 16'h0F3F; -defparam \z80_|execute_|ctl_alu_op_low~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~8_combout = (\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|execute_|ctl_ir_we~7_combout & ((!\z80_|execute_|ctl_ir_we~10_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) # -// (!\z80_|execute_|ctl_state_alu~4_combout & (((!\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_ir_we~7_combout ), - .datad(\z80_|execute_|ctl_ir_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~8 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~9_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~8_combout & (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_ir_we~10_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~9 .lut_mask = 16'h1F00; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~3 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~3_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|execute_|ctl_ir_we~9_combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_ir_we~15_combout )))) # -// (!\z80_|execute_|ctl_eval_cond~0_combout & (((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_ir_we~15_combout )))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|ctl_ir_we~9_combout ), - .datac(\z80_|execute_|ctl_ir_we~15_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~3 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_alu_core_R~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~4_combout = (\z80_|execute_|ctl_alu_core_R~3_combout & (((!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~9_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~15_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~3_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_ir_we~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~4 .lut_mask = 16'h0C4C; -defparam \z80_|execute_|ctl_alu_core_R~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|execute_|ctl_ir_we~11_combout )) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|execute_|ctl_ir_we~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 .lut_mask = 16'h3000; -defparam \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~10_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~9_combout & (\z80_|execute_|ctl_flags_sz_we~0_combout & (\z80_|execute_|ctl_alu_core_R~4_combout & !\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout -// ))) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~0_combout ), - .datac(\z80_|execute_|ctl_alu_core_R~4_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~10 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~11_combout = (((\z80_|execute_|ctl_alu_oe~3_combout & \z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~10_combout )) # (!\z80_|execute_|ctl_alu_op_low~15_combout ) - - .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~15_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~11 .lut_mask = 16'h8FFF; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal48~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal48~0_combout = (!\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|pla_decode_|Equal13~1_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal48~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal48~0 .lut_mask = 16'h1000; -defparam \z80_|pla_decode_|Equal48~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf2_we ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf2_we~combout = (\z80_|pla_decode_|Equal63~0_combout & (!\z80_|ir_|opcode [4] & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & !\z80_|ir_|opcode [3]))) - - .dataa(\z80_|pla_decode_|Equal63~0_combout ), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf2_we~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf2_we .lut_mask = 16'h0020; -defparam \z80_|execute_|ctl_flags_hf2_we .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~41 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~41_combout = (!\z80_|execute_|ctl_flags_hf2_we~combout & (((!\z80_|pla_decode_|Equal10~0_combout & !\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|execute_|ctl_flags_hf2_we~combout ), - .datad(\z80_|pla_decode_|Equal11~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~41 .lut_mask = 16'h0307; -defparam \z80_|execute_|ctl_alu_shift_oe~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~18 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~18_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|pla_decode_|Equal44~0_combout & !\z80_|pla_decode_|Equal52~1_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|pla_decode_|Equal44~0_combout ), - .datad(\z80_|pla_decode_|Equal52~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~18 .lut_mask = 16'hBBBF; -defparam \z80_|execute_|ctl_flags_xy_we~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~17 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~17_combout = ((!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal35~0_combout & !\z80_|pla_decode_|Equal39~0_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|pla_decode_|Equal21~1_combout ), - .datac(\z80_|pla_decode_|Equal35~0_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~17 .lut_mask = 16'h5557; -defparam \z80_|execute_|ctl_alu_shift_oe~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~19 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~19_combout = (\z80_|pla_decode_|Equal40~1_combout ) # ((\z80_|pla_decode_|Equal37~0_combout ) # ((\z80_|pla_decode_|Equal41~2_combout ) # (\z80_|pla_decode_|Equal34~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal40~1_combout ), - .datab(\z80_|pla_decode_|Equal37~0_combout ), - .datac(\z80_|pla_decode_|Equal41~2_combout ), - .datad(\z80_|pla_decode_|Equal34~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~19 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_alu_shift_oe~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_iorw~10 ( -// Equation(s): -// \z80_|execute_|ctl_iorw~10_combout = (!\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [2] & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_iorw~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_iorw~10 .lut_mask = 16'h0100; -defparam \z80_|execute_|ctl_iorw~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~18 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~18_combout = ((!\z80_|execute_|ctl_mWrite~16_combout & (!\z80_|execute_|ctl_mRead~36_combout & !\z80_|execute_|ctl_iorw~10_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) - - .dataa(\z80_|execute_|ctl_mWrite~16_combout ), - .datab(\z80_|execute_|ctl_mRead~36_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_iorw~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~18 .lut_mask = 16'h0F1F; -defparam \z80_|execute_|ctl_alu_shift_oe~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~20 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~20_combout = (\z80_|execute_|ctl_alu_shift_oe~17_combout & (\z80_|execute_|ctl_alu_shift_oe~18_combout & ((!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # (!\z80_|execute_|ctl_alu_shift_oe~19_combout )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~17_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~19_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~20 .lut_mask = 16'h2A00; -defparam \z80_|execute_|ctl_alu_shift_oe~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~13 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~13_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~12_combout ))) # (!\z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|execute_|ctl_ir_we~9_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|ctl_ir_we~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~13 .lut_mask = 16'hF5F7; -defparam \z80_|execute_|ctl_alu_bs_oe~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~9_combout = (\z80_|execute_|ctl_alu_bs_oe~13_combout & (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|execute_|ctl_alu_bs_oe~13_combout ), - .datac(\z80_|execute_|ctl_ir_we~10_combout ), - .datad(\z80_|execute_|ctl_ir_we~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~9 .lut_mask = 16'h444C; -defparam \z80_|execute_|ctl_alu_bs_oe~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~3 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~3_combout = (\z80_|execute_|ctl_alu_bs_oe~9_combout & (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~11_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~9_combout ), - .datad(\z80_|execute_|ctl_ir_we~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~3 .lut_mask = 16'h3070; -defparam \z80_|execute_|ctl_bus_db_oe~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N26 -cycloneive_lcell_comb \z80_|pla_decode_|Equal20~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal20~0_combout = (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [5] & (\z80_|execute_|comb~0_combout & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|execute_|comb~0_combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal20~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal20~0 .lut_mask = 16'h2000; -defparam \z80_|pla_decode_|Equal20~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal68~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal68~2_combout = (!\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [2] & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal68~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal68~2 .lut_mask = 16'h1000; -defparam \z80_|pla_decode_|Equal68~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~14 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~14_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal20~0_combout & !\z80_|pla_decode_|Equal68~2_combout ))) # (!\z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|pla_decode_|Equal20~0_combout ), - .datab(\z80_|pla_decode_|Equal68~2_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~14 .lut_mask = 16'hFF1F; -defparam \z80_|execute_|ctl_flags_bus~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~13 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~13_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal3~1_combout & ((!\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal21~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal21~0_combout ), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|pla_decode_|Equal3~1_combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~13 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_alu_op_low~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~15 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~15_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|execute_|ctl_alu_op_low~13_combout & !\z80_|execute_|ctl_alu_op_low~12_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|execute_|ctl_alu_op_low~13_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~15 .lut_mask = 16'hBBBF; -defparam \z80_|execute_|ctl_flags_bus~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~11_combout = (\z80_|execute_|ctl_flags_bus~15_combout & (((!\z80_|execute_|ctl_ir_we~14_combout & !\z80_|execute_|ctl_ir_we~8_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|execute_|ctl_ir_we~14_combout ), - .datac(\z80_|execute_|ctl_ir_we~8_combout ), - .datad(\z80_|execute_|ctl_flags_bus~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~11 .lut_mask = 16'h5700; -defparam \z80_|execute_|ctl_flags_bus~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N20 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~11 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~11_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|pla_decode_|Equal56~0_combout & !\z80_|execute_|ctl_alu_op_low~11_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|execute_|ctl_alu_op_low~11_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~11 .lut_mask = 16'hAFBF; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~10_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~11_combout & (((!\z80_|pla_decode_|Equal21~0_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )) # (!\z80_|pla_decode_|Equal63~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal63~0_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~11_combout ), - .datad(\z80_|pla_decode_|Equal21~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~10 .lut_mask = 16'h70F0; -defparam \z80_|execute_|ctl_flags_bus~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~8_combout = (\z80_|execute_|ixy_d~10_combout ) # ((\z80_|pla_decode_|Equal63~0_combout & ((\z80_|pla_decode_|Equal3~0_combout ) # (\z80_|pla_decode_|Equal32~0_combout )))) - - .dataa(\z80_|execute_|ixy_d~10_combout ), - .datab(\z80_|pla_decode_|Equal63~0_combout ), - .datac(\z80_|pla_decode_|Equal3~0_combout ), - .datad(\z80_|pla_decode_|Equal32~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~8 .lut_mask = 16'hEEEA; -defparam \z80_|execute_|ctl_flags_bus~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~9_combout = ((!\z80_|pla_decode_|Equal13~2_combout & (!\z80_|execute_|ctl_mRead~6_combout & !\z80_|execute_|ctl_flags_bus~8_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|execute_|ctl_mRead~6_combout ), - .datad(\z80_|execute_|ctl_flags_bus~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~9 .lut_mask = 16'h3337; -defparam \z80_|execute_|ctl_flags_bus~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~12 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~12_combout = (\z80_|execute_|ctl_flags_bus~14_combout & (\z80_|execute_|ctl_flags_bus~11_combout & (\z80_|execute_|ctl_flags_bus~10_combout & \z80_|execute_|ctl_flags_bus~9_combout ))) - - .dataa(\z80_|execute_|ctl_flags_bus~14_combout ), - .datab(\z80_|execute_|ctl_flags_bus~11_combout ), - .datac(\z80_|execute_|ctl_flags_bus~10_combout ), - .datad(\z80_|execute_|ctl_flags_bus~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~12 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_bus~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~11_combout = (\z80_|execute_|ctl_flags_xy_we~18_combout & (\z80_|execute_|ctl_alu_shift_oe~20_combout & (\z80_|execute_|ctl_bus_db_oe~3_combout & \z80_|execute_|ctl_flags_bus~12_combout ))) - - .dataa(\z80_|execute_|ctl_flags_xy_we~18_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~20_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~3_combout ), - .datad(\z80_|execute_|ctl_flags_bus~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~11 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_xy_we~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~12 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~12_combout = (\z80_|execute_|ctl_alu_shift_oe~41_combout & (\z80_|execute_|ctl_flags_xy_we~11_combout & ((!\z80_|execute_|ctl_state_alu~14_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~41_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~11_combout ), - .datad(\z80_|execute_|ctl_state_alu~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~12 .lut_mask = 16'h20A0; -defparam \z80_|execute_|ctl_flags_xy_we~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~6_combout = (\z80_|execute_|ctl_mWrite~3_combout & (!\z80_|execute_|ctl_ir_we~14_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|execute_|ctl_ir_we~8_combout )))) # -// (!\z80_|execute_|ctl_mWrite~3_combout & (((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|execute_|ctl_ir_we~8_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~3_combout ), - .datab(\z80_|execute_|ctl_ir_we~14_combout ), - .datac(\z80_|execute_|ctl_ir_we~8_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~6 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~7 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~7_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~6_combout & (\z80_|execute_|ctl_flags_alu~16_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal20~0_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ), - .datac(\z80_|execute_|ctl_flags_alu~16_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~7 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~4_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M4_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~4 .lut_mask = 16'h3030; -defparam \z80_|execute_|ctl_ir_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~8_combout = ((!\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~9_combout ))) # (!\z80_|execute_|ctl_ir_we~4_combout ) - - .dataa(\z80_|execute_|ctl_ir_we~12_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_ir_we~9_combout ), - .datad(\z80_|execute_|ctl_ir_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~8 .lut_mask = 16'h01FF; -defparam \z80_|execute_|ctl_alu_bs_oe~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~0_combout = (\z80_|execute_|ctl_alu_bs_oe~8_combout & (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_ir_we~10_combout ), - .datad(\z80_|execute_|ctl_alu_bs_oe~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~0 .lut_mask = 16'h3700; -defparam \z80_|execute_|ctl_bus_db_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~12 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~12_combout = (!\z80_|execute_|ctl_alu_op_low~9_combout & (((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|pla_decode_|Equal41~2_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~9_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|pla_decode_|Equal41~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~12 .lut_mask = 16'h0515; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~13 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~13_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~7_combout & (\z80_|execute_|ctl_bus_db_oe~0_combout & \z80_|execute_|ctl_alu_op1_sel_bus~12_combout )) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_bus_db_oe~0_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~13 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~14_combout = (\z80_|execute_|ctl_flags_xy_we~12_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~13_combout & ((!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # (!\z80_|pla_decode_|Equal48~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal48~0_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~12_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~14 .lut_mask = 16'h4C00; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~15 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~15_combout = (((\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ) # (!\z80_|execute_|ctl_alu_op1_sel_bus~14_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~5_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~31_combout ) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~31_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~5_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~15 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_66_oe~2 ( -// Equation(s): -// \z80_|execute_|ctl_66_oe~2_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|execute_|comb~0_combout & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal52~0_combout ), - .datac(\z80_|execute_|comb~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_66_oe~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_66_oe~2 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_66_oe~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla11M1T1_11 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|pla_decode_|Equal10~0_combout )) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal10~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel_pla11M1T1_11 .lut_mask = 16'h1100; -defparam \z80_|execute_|ctl_pf_sel_pla11M1T1_11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_zero~5_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal63~0_combout & (\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4]))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|pla_decode_|Equal63~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_zero~5 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_alu_op1_sel_zero~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_zero~4_combout = (\z80_|pla_decode_|Equal3~1_combout & (!\z80_|ir_|opcode [0] & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_zero~4 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_alu_op1_sel_zero~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_zero~combout = (\z80_|execute_|ctl_66_oe~2_combout ) # ((\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ) # (\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ))) - - .dataa(\z80_|execute_|ctl_66_oe~2_combout ), - .datab(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_zero .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_alu_op1_sel_zero .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N16 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[2] ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_high|Q [2] = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & (\z80_|alu_|db_high[2]~14_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .datac(\z80_|alu_|db_high[2]~14_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [2]), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[2] .lut_mask = 16'h00C0; -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N2 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|ena~0 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ) # (\z80_|execute_|ctl_alu_op1_sel_zero~combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_high|ena~0 .lut_mask = 16'hFFF0; -defparam \z80_|alu_|b2v_op1_latch_mux_high|ena~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y10_N17 -dffeas \z80_|alu_|op1_high[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [2]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_high [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_high[2] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_high[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_lq ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_lq~combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ixy_d~7_combout ) # ((\z80_|execute_|ixy_d~6_combout & !\z80_|ir_|opcode [3])))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|pla_decode_|Equal13~2_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_lq .lut_mask = 16'h88C8; -defparam \z80_|execute_|ctl_alu_op2_sel_lq .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~10_combout = (((!\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [3])) # (!\z80_|pla_decode_|Equal63~0_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal63~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~10 .lut_mask = 16'h1FFF; -defparam \z80_|execute_|ctl_alu_op_low~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N28 -cycloneive_lcell_comb \z80_|execute_|fMWrite~11 ( -// Equation(s): -// \z80_|execute_|fMWrite~11_combout = ((!\z80_|pla_decode_|Equal13~2_combout ) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|pla_decode_|Equal13~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~11 .lut_mask = 16'h5FFF; -defparam \z80_|execute_|fMWrite~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~21 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~21_combout = ((\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # (\z80_|execute_|ctl_alu_op_low~9_combout ))) # (!\z80_|execute_|fMWrite~11_combout ) - - .dataa(\z80_|execute_|fMWrite~11_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~21 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_alu_op_low~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N4 +// Location: LCCOMB_X21_Y12_N24 cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~22 ( // Equation(s): -// \z80_|execute_|ctl_alu_op_low~22_combout = ((\z80_|execute_|ctl_alu_op_low~21_combout ) # (!\z80_|execute_|ctl_alu_op1_sel_bus~10_combout )) # (!\z80_|execute_|ctl_alu_op_low~10_combout ) +// \z80_|execute_|ctl_alu_op_low~22_combout = (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ) - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op_low~10_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~21_combout ), + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), .cin(gnd), .combout(\z80_|execute_|ctl_alu_op_low~22_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~22 .lut_mask = 16'hFF3F; +defparam \z80_|execute_|ctl_alu_op_low~22 .lut_mask = 16'hAA00; defparam \z80_|execute_|ctl_alu_op_low~22 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y14_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~16 ( +// Location: LCCOMB_X26_Y16_N30 +cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_11 ( // Equation(s): -// \z80_|execute_|ctl_alu_op_low~16_combout = ((!\z80_|execute_|ixy_d~7_combout & ((\z80_|ir_|opcode [3]) # (!\z80_|execute_|ixy_d~6_combout )))) # (!\z80_|pla_decode_|Equal13~2_combout ) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|pla_decode_|Equal13~2_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~16 .lut_mask = 16'h7737; -defparam \z80_|execute_|ctl_alu_op_low~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~17 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~17_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~7_combout & (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & \z80_|execute_|ctl_alu_op_low~16_combout )) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), - .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_alu_op_low~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~17 .lut_mask = 16'h2200; -defparam \z80_|execute_|ctl_alu_op_low~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout = (!\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal44~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T4_ff~q ))) - - .dataa(\z80_|pla_decode_|Equal33~0_combout ), - .datab(\z80_|pla_decode_|Equal44~0_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel~36 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel~36_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|sequencer_|DFFE_T4_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|pla_decode_|Equal52~0_combout ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel~36 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_gp_sel~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~4_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout & (\z80_|execute_|ctl_state_alu~8_combout & (!\z80_|execute_|ctl_reg_gp_sel~36_combout & \z80_|execute_|ctl_alu_op2_sel_bus~9_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), - .datab(\z80_|execute_|ctl_state_alu~8_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel~36_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~4 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~5 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~5_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ) +// \z80_|resets_|SYNTHESIZED_WIRE_11~combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T2_ff~q ) .dataa(gnd), .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~5 .lut_mask = 16'h0F00; -defparam \z80_|execute_|ctl_state_alu~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~18 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~18_combout = (\z80_|execute_|ctl_mWrite~3_combout & ((\z80_|pla_decode_|Equal56~0_combout ) # ((\z80_|execute_|ctl_alu_op_low~11_combout )))) # (!\z80_|execute_|ctl_mWrite~3_combout & -// (\z80_|execute_|ctl_state_alu~5_combout & ((\z80_|pla_decode_|Equal56~0_combout ) # (\z80_|execute_|ctl_alu_op_low~11_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~3_combout ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|execute_|ctl_state_alu~5_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~18 .lut_mask = 16'hFAC8; -defparam \z80_|execute_|ctl_alu_op_low~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~19 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~19_combout = ((\z80_|execute_|ctl_alu_op_low~14_combout ) # ((\z80_|execute_|ctl_alu_op_low~18_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~38_combout ))) # (!\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~19 .lut_mask = 16'hFFDF; -defparam \z80_|execute_|ctl_alu_op_low~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~33 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~33_combout = (((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|execute_|ctl_alu_op_low~12_combout ) - - .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~33 .lut_mask = 16'h77F7; -defparam \z80_|execute_|ctl_alu_op_low~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~20 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~20_combout = (\z80_|execute_|ctl_alu_op_low~19_combout ) # (!\z80_|execute_|ctl_alu_op_low~33_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_op_low~19_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~33_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~20 .lut_mask = 16'hF0FF; -defparam \z80_|execute_|ctl_alu_op_low~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~23 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~23_combout = (\z80_|execute_|ctl_mRead~36_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout )))) # (!\z80_|execute_|ctl_mRead~36_combout & (\z80_|execute_|ixy_d~5_combout & -// ((\z80_|pla_decode_|Equal39~0_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~36_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~23 .lut_mask = 16'hECA8; -defparam \z80_|execute_|ctl_alu_op_low~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~24 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~24_combout = (\z80_|execute_|ctl_alu_op_low~22_combout ) # (((\z80_|execute_|ctl_alu_op_low~20_combout ) # (\z80_|execute_|ctl_alu_op_low~23_combout )) # (!\z80_|execute_|ctl_alu_op_low~17_combout )) - - .dataa(\z80_|execute_|ctl_alu_op_low~22_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~20_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~23_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~24 .lut_mask = 16'hFFFB; -defparam \z80_|execute_|ctl_alu_op_low~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~25 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~25_combout = (\z80_|execute_|ixy_d~9_combout & (((\z80_|pla_decode_|Equal40~1_combout ) # (\z80_|pla_decode_|Equal39~0_combout )))) # (!\z80_|execute_|ixy_d~9_combout & (\z80_|execute_|ixy_d~5_combout & -// (\z80_|pla_decode_|Equal40~1_combout ))) - - .dataa(\z80_|execute_|ixy_d~9_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|pla_decode_|Equal40~1_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~25 .lut_mask = 16'hEAE0; -defparam \z80_|execute_|ctl_alu_op_low~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~34 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~34_combout = (\z80_|execute_|ctl_alu_op_low~25_combout ) # ((\z80_|pla_decode_|Equal21~1_combout & (\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ))) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|ctl_alu_op_low~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~34 .lut_mask = 16'hFF08; -defparam \z80_|execute_|ctl_alu_op_low~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~combout = ((\z80_|execute_|ctl_alu_op_low~24_combout ) # ((\z80_|execute_|ctl_alu_op_low~34_combout ) # (\z80_|execute_|ctl_alu_op_low~26_combout ))) # (!\z80_|execute_|ctl_alu_op_low~15_combout ) - - .dataa(\z80_|execute_|ctl_alu_op_low~15_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~24_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~34_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~26_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_alu_op_low .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~40 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~40_combout = ((\z80_|execute_|ixy_d~9_combout & ((\z80_|execute_|ctl_mRead~26_combout ) # (\z80_|execute_|ctl_mRead~27_combout )))) # (!\z80_|execute_|ctl_flags_xy_we~18_combout ) - - .dataa(\z80_|execute_|ctl_mRead~26_combout ), - .datab(\z80_|execute_|ctl_mRead~27_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~18_combout ), - .datad(\z80_|execute_|ixy_d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~40 .lut_mask = 16'hEF0F; -defparam \z80_|execute_|ctl_alu_shift_oe~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~37 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~37_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_alu_oe~3_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) - - .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~37 .lut_mask = 16'hAE00; -defparam \z80_|execute_|ctl_alu_shift_oe~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~39 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~39_combout = (\z80_|execute_|ctl_alu_shift_oe~37_combout ) # (((\z80_|execute_|ctl_state_alu~14_combout & \z80_|execute_|ctl_alu_shift_oe~14_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~5_combout )) - - .dataa(\z80_|execute_|ctl_state_alu~14_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~37_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~39 .lut_mask = 16'hECFF; -defparam \z80_|execute_|ctl_alu_shift_oe~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~46 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~46_combout = (\z80_|execute_|ctl_alu_shift_oe~41_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|pla_decode_|Equal48~0_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~41_combout ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|pla_decode_|Equal48~0_combout ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), .datad(\z80_|sequencer_|DFFE_M1_ff~q ), .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~46_combout ), + .combout(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~46 .lut_mask = 16'hAA2A; -defparam \z80_|execute_|ctl_alu_shift_oe~46 .sum_lutc_input = "datac"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_11 .lut_mask = 16'hFF0F; +defparam \z80_|resets_|SYNTHESIZED_WIRE_11 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X40_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~42 ( +// Location: LCCOMB_X31_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~4 ( // Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~42_combout = (\z80_|execute_|ctl_alu_shift_oe~40_combout ) # (((\z80_|execute_|ctl_alu_shift_oe~39_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~46_combout )) # (!\z80_|execute_|ctl_alu_op_low~17_combout )) +// \z80_|execute_|ctl_ir_we~4_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M4_ff~q ) - .dataa(\z80_|execute_|ctl_alu_shift_oe~40_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~39_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~46_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~42 .lut_mask = 16'hFBFF; -defparam \z80_|execute_|ctl_alu_shift_oe~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~21 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~21_combout = (\z80_|execute_|ctl_ir_we~15_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # ((\z80_|execute_|ctl_state_alu~6_combout & !\z80_|execute_|ctl_ir_we~4_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~6_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_ir_we~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~21 .lut_mask = 16'hF200; -defparam \z80_|execute_|ctl_alu_shift_oe~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~45 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~45_combout = (\z80_|execute_|ctl_alu_shift_oe~21_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|execute_|ctl_alu_shift_oe~21_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|ctl_ir_we~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~45 .lut_mask = 16'hC4CC; -defparam \z80_|execute_|ctl_alu_shift_oe~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~22 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~22_combout = (\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_state_alu~6_combout ) # (\z80_|execute_|ctl_alu_shift_oe~45_combout )))) # -// (!\z80_|execute_|ctl_ir_we~9_combout & (((\z80_|execute_|ctl_alu_shift_oe~45_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~6_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_ir_we~9_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~45_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~22 .lut_mask = 16'h3F20; -defparam \z80_|execute_|ctl_alu_shift_oe~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~23 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~23_combout = (\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # (\z80_|execute_|ctl_alu_shift_oe~22_combout )))) # -// (!\z80_|execute_|ctl_ir_we~9_combout & (((\z80_|execute_|ctl_alu_shift_oe~22_combout )))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~22_combout ), - .datac(\z80_|execute_|ctl_ir_we~9_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~23 .lut_mask = 16'h0CEC; -defparam \z80_|execute_|ctl_alu_shift_oe~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~24 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~24_combout = (\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_mWrite~7_combout ) # (\z80_|execute_|ctl_alu_shift_oe~23_combout )))) # -// (!\z80_|execute_|ctl_ir_we~12_combout & (((\z80_|execute_|ctl_alu_shift_oe~23_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~7_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~23_combout ), - .datad(\z80_|execute_|ctl_ir_we~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~24 .lut_mask = 16'h32F0; -defparam \z80_|execute_|ctl_alu_shift_oe~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~25 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~25_combout = (\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|execute_|ctl_alu_shift_oe~24_combout ) # (\z80_|execute_|ctl_mWrite~3_combout )))) # -// (!\z80_|execute_|ctl_ir_we~12_combout & (\z80_|execute_|ctl_alu_shift_oe~24_combout )) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~24_combout ), - .datab(\z80_|execute_|ctl_ir_we~12_combout ), - .datac(\z80_|execute_|ctl_mWrite~3_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~25 .lut_mask = 16'h22EA; -defparam \z80_|execute_|ctl_alu_shift_oe~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~14_combout = (\z80_|execute_|ctl_ir_we~11_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # ((\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~14 .lut_mask = 16'hC0C8; -defparam \z80_|execute_|ctl_alu_bs_oe~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~26 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~26_combout = (!\z80_|execute_|ctl_alu_bs_oe~14_combout & ((\z80_|execute_|ctl_alu_shift_oe~25_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout & \z80_|execute_|ctl_mWrite~7_combout )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~25_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_mWrite~7_combout ), - .datad(\z80_|execute_|ctl_alu_bs_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~26 .lut_mask = 16'h00EA; -defparam \z80_|execute_|ctl_alu_shift_oe~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~27 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~27_combout = (\z80_|execute_|ctl_ir_we~7_combout & ((\z80_|execute_|ctl_state_alu~6_combout ) # ((\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ctl_bus_db_oe~1_combout )))) # (!\z80_|execute_|ctl_ir_we~7_combout & -// (\z80_|execute_|ixy_d~7_combout & ((!\z80_|execute_|ctl_bus_db_oe~1_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~27 .lut_mask = 16'hA0EC; -defparam \z80_|execute_|ctl_alu_shift_oe~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~28 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~28_combout = ((\z80_|execute_|ctl_alu_shift_oe~27_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~20_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~44_combout ) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~44_combout ), + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), .datab(gnd), - .datac(\z80_|execute_|ctl_alu_shift_oe~20_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~27_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~28 .lut_mask = 16'hFF5F; -defparam \z80_|execute_|ctl_alu_shift_oe~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~10_combout = (\z80_|execute_|ctl_ir_we~7_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) # (!\z80_|execute_|ctl_ir_we~7_combout & (\z80_|execute_|ctl_ir_we~4_combout -// & (\z80_|execute_|ctl_ir_we~10_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_ir_we~10_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~10 .lut_mask = 16'hEAC8; -defparam \z80_|execute_|ctl_alu_bs_oe~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~11_combout = (\z80_|execute_|ctl_alu_bs_oe~10_combout ) # ((\z80_|execute_|ctl_alu_bs_oe~14_combout ) # ((!\z80_|execute_|ctl_alu_bs_oe~8_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~9_combout ))) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~10_combout ), - .datab(\z80_|execute_|ctl_alu_bs_oe~14_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~9_combout ), - .datad(\z80_|execute_|ctl_alu_bs_oe~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~11 .lut_mask = 16'hEFFF; -defparam \z80_|execute_|ctl_alu_bs_oe~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~32 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~32_combout = (!\z80_|execute_|ctl_alu_bs_oe~11_combout & ((\z80_|execute_|ctl_alu_shift_oe~28_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~31_combout ))) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_shift_oe~28_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~31_combout ), - .datad(\z80_|execute_|ctl_alu_bs_oe~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~32 .lut_mask = 16'h00CF; -defparam \z80_|execute_|ctl_alu_shift_oe~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~33 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~33_combout = (\z80_|execute_|ctl_alu_shift_oe~32_combout ) # ((!\z80_|execute_|ctl_alu_bs_oe~combout & ((\z80_|execute_|ctl_alu_shift_oe~16_combout ) # (!\z80_|execute_|ctl_alu_op_low~15_combout )))) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datab(\z80_|execute_|ctl_alu_op_low~15_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~16_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~33 .lut_mask = 16'hFF51; -defparam \z80_|execute_|ctl_alu_shift_oe~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~0_combout = ((!\z80_|execute_|ctl_alu_op_low~12_combout & (!\z80_|execute_|ctl_alu_op_low~11_combout & !\z80_|pla_decode_|Equal56~0_combout ))) # (!\z80_|execute_|ctl_state_alu~5_combout ) - - .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~11_combout ), - .datac(\z80_|execute_|ctl_state_alu~5_combout ), - .datad(\z80_|pla_decode_|Equal56~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~0 .lut_mask = 16'h0F1F; -defparam \z80_|execute_|ctl_reg_use_sp~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~1 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~1_combout = (\z80_|execute_|ctl_reg_use_sp~0_combout & \z80_|execute_|nextM~11_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_use_sp~0_combout ), .datac(gnd), - .datad(\z80_|execute_|nextM~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~1 .lut_mask = 16'hCC00; -defparam \z80_|execute_|ctl_reg_use_sp~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~12 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~12_combout = (\z80_|execute_|ctl_alu_bs_oe~14_combout ) # ((!\z80_|execute_|ctl_alu_bs_oe~8_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~9_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_bs_oe~14_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~9_combout ), - .datad(\z80_|execute_|ctl_alu_bs_oe~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~12 .lut_mask = 16'hCFFF; -defparam \z80_|execute_|ctl_alu_bs_oe~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~47 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~47_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|sequencer_|DFFE_M1_ff~q & \z80_|execute_|ctl_ir_we~7_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|ctl_ir_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~47 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_shift_oe~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~34 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~34_combout = (\z80_|execute_|ctl_ir_we~10_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_state_alu~6_combout ) # (\z80_|execute_|ctl_alu_shift_oe~47_combout )))) # -// (!\z80_|execute_|ctl_ir_we~10_combout & (((\z80_|execute_|ctl_alu_shift_oe~47_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~6_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_ir_we~10_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~47_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~34 .lut_mask = 16'h3F20; -defparam \z80_|execute_|ctl_alu_shift_oe~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~35 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~35_combout = (!\z80_|execute_|ctl_alu_bs_oe~12_combout & ((\z80_|execute_|ctl_alu_shift_oe~34_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & \z80_|execute_|ctl_ir_we~10_combout )))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|ctl_ir_we~10_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~12_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~34_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~35 .lut_mask = 16'h0F08; -defparam \z80_|execute_|ctl_alu_shift_oe~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~36 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~36_combout = (((\z80_|execute_|ctl_alu_shift_oe~35_combout ) # (!\z80_|execute_|ctl_reg_use_sp~1_combout )) # (!\z80_|execute_|ctl_flags_bus~12_combout )) # (!\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ), - .datab(\z80_|execute_|ctl_flags_bus~12_combout ), - .datac(\z80_|execute_|ctl_reg_use_sp~1_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~35_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~36 .lut_mask = 16'hFF7F; -defparam \z80_|execute_|ctl_alu_shift_oe~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~43 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~43_combout = (\z80_|execute_|ctl_alu_shift_oe~42_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~26_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~33_combout ) # (\z80_|execute_|ctl_alu_shift_oe~36_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~42_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~26_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~33_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~43 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_alu_shift_oe~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_lo~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_lo~9_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q ))) # (!\z80_|pla_decode_|Equal47~0_combout ) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|M5~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_lo~9 .lut_mask = 16'hF5F7; -defparam \z80_|execute_|ctl_reg_in_lo~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_oe~0_combout = ((\z80_|execute_|ctl_66_oe~2_combout ) # ((\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_alu_shift_oe~14_combout ))) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ) - - .dataa(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datab(\z80_|execute_|ctl_66_oe~2_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_oe~0 .lut_mask = 16'hFDDD; -defparam \z80_|execute_|ctl_alu_op1_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout = (\z80_|pla_decode_|Equal48~0_combout & (\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )) - - .dataa(\z80_|pla_decode_|Equal48~0_combout ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 .lut_mask = 16'h0088; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_oe~1 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_oe~1_combout = (\z80_|execute_|ctl_alu_op1_oe~0_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ) # ((\z80_|execute_|ctl_alu_oe~3_combout & \z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_alu_op1_oe~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_oe~1 .lut_mask = 16'hFFF8; -defparam \z80_|execute_|ctl_alu_op1_oe~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~8_combout = (((!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4])) # (!\z80_|pla_decode_|Equal63~0_combout )) # (!\z80_|nM1_int~2_combout ) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal63~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~8 .lut_mask = 16'h777F; -defparam \z80_|execute_|ctl_flags_xy_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~9_combout = (!\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout & (\z80_|execute_|ctl_flags_xy_we~8_combout & ((!\z80_|sequencer_|DFFE_T5_ff~q ) # (!\z80_|execute_|ixy_d~15_combout )))) - - .dataa(\z80_|execute_|ixy_d~15_combout ), - .datab(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .datac(\z80_|sequencer_|DFFE_T5_ff~q ), - .datad(\z80_|execute_|ctl_flags_xy_we~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~9 .lut_mask = 16'h1300; -defparam \z80_|execute_|ctl_flags_xy_we~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N18 -cycloneive_lcell_comb \z80_|pla_decode_|Equal8~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal8~0_combout = (\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [2] & \z80_|ir_|opcode [0])) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [1]), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal8~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal8~0 .lut_mask = 16'h0C00; -defparam \z80_|pla_decode_|Equal8~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~9_combout = (((!\z80_|nM1_int~2_combout & !\z80_|execute_|ixy_d~6_combout )) # (!\z80_|execute_|ctl_mWrite~2_combout )) # (!\z80_|pla_decode_|Equal8~0_combout ) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal8~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~2_combout ), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~9 .lut_mask = 16'h3F7F; -defparam \z80_|execute_|ctl_flags_alu~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~4_combout = ((!\z80_|pla_decode_|Equal40~1_combout & (!\z80_|pla_decode_|Equal39~0_combout & !\z80_|pla_decode_|Equal21~1_combout ))) # (!\z80_|execute_|ixy_d~8_combout ) - - .dataa(\z80_|pla_decode_|Equal40~1_combout ), - .datab(\z80_|pla_decode_|Equal39~0_combout ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|execute_|ixy_d~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~4 .lut_mask = 16'h01FF; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~3_combout = (\z80_|pla_decode_|Equal21~1_combout & (!\z80_|execute_|ctl_mRead~11_combout & ((!\z80_|pla_decode_|Equal10~0_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) # (!\z80_|pla_decode_|Equal21~1_combout & -// (((!\z80_|pla_decode_|Equal10~0_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|execute_|ctl_mRead~11_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|pla_decode_|Equal10~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~3 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_flags_sz_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal11~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal11~1_combout = (!\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [0]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal11~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal11~1 .lut_mask = 16'h000F; -defparam \z80_|pla_decode_|Equal11~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout = (\z80_|execute_|ixy_d~7_combout & (\z80_|execute_|ctl_mWrite~2_combout & (!\z80_|ir_|opcode [2] & \z80_|pla_decode_|Equal11~1_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|pla_decode_|Equal11~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~10_combout = (\z80_|execute_|ctl_flags_alu~9_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~4_combout & (\z80_|execute_|ctl_flags_sz_we~3_combout & !\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ))) - - .dataa(\z80_|execute_|ctl_flags_alu~9_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), - .datac(\z80_|execute_|ctl_flags_sz_we~3_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~10 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_flags_alu~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~11_combout = (\z80_|execute_|ctl_flags_xy_we~9_combout & (\z80_|execute_|ctl_flags_alu~10_combout & ((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|execute_|ixy_d~15_combout )))) - - .dataa(\z80_|execute_|ixy_d~15_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~9_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|execute_|ctl_flags_alu~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~11 .lut_mask = 16'h4C00; -defparam \z80_|execute_|ctl_flags_alu~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout = (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal63~0_combout & (!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4]))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal63~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 .lut_mask = 16'h0008; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla82M1T1_16 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout = (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [0] & (\z80_|nM1_int~2_combout & \z80_|pla_decode_|Equal3~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal3~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel_pla82M1T1_16 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_pf_sel_pla82M1T1_16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~13 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~13_combout = (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|execute_|ctl_mRead~6_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|execute_|ctl_mRead~6_combout ), .datad(\z80_|sequencer_|DFFE_M4_ff~q ), .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~13_combout ), + .combout(\z80_|execute_|ctl_ir_we~4_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~13 .lut_mask = 16'h3F7F; -defparam \z80_|execute_|ctl_flags_use_cf2~13 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_ir_we~4 .lut_mask = 16'h5500; +defparam \z80_|execute_|ctl_ir_we~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~7 ( +// Location: LCCOMB_X26_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_state_iy_set~2 ( // Equation(s): -// \z80_|execute_|ctl_flags_cf_we~7_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # (((!\z80_|pla_decode_|Equal55~0_combout ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|pla_decode_|Equal13~0_combout )) +// \z80_|execute_|ctl_state_iy_set~2_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal3~2_combout ))) - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|pla_decode_|Equal55~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~7 .lut_mask = 16'hBFFF; -defparam \z80_|execute_|ctl_flags_cf_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel[0]~2 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel[0]~2_combout = (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (\z80_|execute_|ctl_flags_use_cf2~13_combout & \z80_|execute_|ctl_flags_cf_we~7_combout )) - - .dataa(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .datab(\z80_|execute_|ctl_flags_use_cf2~13_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_flags_cf_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel[0]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel[0]~2 .lut_mask = 16'h4400; -defparam \z80_|execute_|ctl_pf_sel[0]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~2 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~2_combout = (\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_T1_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~2 .lut_mask = 16'h00F0; -defparam \z80_|execute_|ctl_alu_oe~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~25 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~25_combout = (\z80_|execute_|ctl_ir_we~14_combout & (!\z80_|execute_|ixy_d~7_combout & ((!\z80_|execute_|ctl_alu_oe~2_combout )))) # (!\z80_|execute_|ctl_ir_we~14_combout & (((!\z80_|execute_|ctl_alu_oe~2_combout ) # -// (!\z80_|execute_|ctl_ir_we~8_combout )))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_ir_we~14_combout ), - .datac(\z80_|execute_|ctl_ir_we~8_combout ), - .datad(\z80_|execute_|ctl_alu_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~25 .lut_mask = 16'h0377; -defparam \z80_|execute_|ctl_bus_inc_oe~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_we~5_combout = (\z80_|execute_|ctl_bus_inc_oe~25_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|execute_|ctl_ir_we~8_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|execute_|ctl_bus_inc_oe~25_combout ), - .datac(\z80_|execute_|ctl_ir_we~8_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_we~5 .lut_mask = 16'hCC8C; -defparam \z80_|execute_|ctl_flags_hf_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~10_combout = (\z80_|execute_|ctl_flags_hf_we~5_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|pla_decode_|Equal13~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(\z80_|execute_|ctl_flags_hf_we~5_combout ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~10 .lut_mask = 16'hCCC4; -defparam \z80_|execute_|ctl_flags_pf_we~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~48 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~48_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|execute_|ctl_alu_op_low~13_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~13_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~48 .lut_mask = 16'h3331; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~2_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout & (\z80_|execute_|ctl_pf_sel[0]~2_combout & (\z80_|execute_|ctl_flags_pf_we~10_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .datab(\z80_|execute_|ctl_pf_sel[0]~2_combout ), - .datac(\z80_|execute_|ctl_flags_pf_we~10_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~2 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_flags_pf_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~3_combout = (\z80_|execute_|ctl_flags_pf_we~2_combout & (((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_ir_we~12_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_flags_pf_we~2_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_ir_we~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~3 .lut_mask = 16'h0A2A; -defparam \z80_|execute_|ctl_flags_pf_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y19_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~17 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~17_combout = (((!\z80_|pla_decode_|Equal13~0_combout ) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|pla_decode_|Equal55~0_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~17 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_flags_xy_we~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N6 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~5 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~5_combout = ((!\z80_|pla_decode_|Equal40~1_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal39~0_combout ))) # (!\z80_|execute_|ixy_d~6_combout ) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|pla_decode_|Equal40~1_combout ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~5 .lut_mask = 16'h5557; -defparam \z80_|reg_control_|reg_sys_we_lo~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N26 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~6 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~6_combout = (\z80_|execute_|ctl_flags_xy_we~17_combout & (\z80_|reg_control_|reg_sys_we_lo~5_combout & ((!\z80_|execute_|ctl_alu_op_low~8_combout ) # (!\z80_|pla_decode_|Equal56~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal56~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~17_combout ), - .datad(\z80_|reg_control_|reg_sys_we_lo~5_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~6 .lut_mask = 16'h7000; -defparam \z80_|reg_control_|reg_sys_we_lo~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~10_combout = (\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ixy_d~7_combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) # (!\z80_|pla_decode_|Equal56~0_combout & -// (((!\z80_|nM1_int~2_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal56~0_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|pla_decode_|Equal20~0_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~10 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_flags_xy_we~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout = (\z80_|execute_|ctl_mWrite~2_combout & (\z80_|execute_|ctl_state_alu~4_combout & (\z80_|pla_decode_|Equal2~0_combout & !\z80_|ir_|opcode [0]))) - - .dataa(\z80_|execute_|ctl_mWrite~2_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|pla_decode_|Equal2~0_combout ), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~7 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~7_combout = (\z80_|ir_|opcode [7] & (!\z80_|pla_decode_|Equal33~0_combout & (!\z80_|ir_|opcode [6] & !\z80_|decode_state_|table_xx~0_combout ))) - - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|ir_|opcode [6]), - .datad(\z80_|decode_state_|table_xx~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~7 .lut_mask = 16'h0002; -defparam \z80_|execute_|ctl_state_alu~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~1 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~1_combout = ((!\z80_|execute_|ctl_state_alu~14_combout & (!\z80_|execute_|ctl_state_alu~7_combout & !\z80_|pla_decode_|Equal52~1_combout ))) # (!\z80_|nM1_int~2_combout ) - - .dataa(\z80_|execute_|ctl_state_alu~14_combout ), - .datab(\z80_|execute_|ctl_state_alu~7_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal52~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~1 .lut_mask = 16'h0F1F; -defparam \z80_|execute_|ctl_flags_sz_we~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~2_combout = (\z80_|reg_control_|reg_sys_we_lo~6_combout & (\z80_|execute_|ctl_flags_xy_we~10_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout & \z80_|execute_|ctl_flags_sz_we~1_combout ))) - - .dataa(\z80_|reg_control_|reg_sys_we_lo~6_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~10_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), - .datad(\z80_|execute_|ctl_flags_sz_we~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~2 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_flags_cf_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~6_combout = (\z80_|nM1_int~2_combout & (!\z80_|execute_|ctl_ir_we~9_combout & ((!\z80_|execute_|ctl_mWrite~3_combout ) # (!\z80_|execute_|ctl_ir_we~15_combout )))) # (!\z80_|nM1_int~2_combout & -// (((!\z80_|execute_|ctl_mWrite~3_combout )) # (!\z80_|execute_|ctl_ir_we~15_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_ir_we~9_combout ), - .datad(\z80_|execute_|ctl_mWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~6 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_alu_core_S~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~7 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~7_combout = (\z80_|execute_|ctl_alu_core_S~6_combout & (((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_alu_oe~2_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~9_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_alu_core_S~6_combout ), - .datad(\z80_|execute_|ctl_alu_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~7 .lut_mask = 16'h10F0; -defparam \z80_|execute_|ctl_alu_core_S~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~4_combout = (\z80_|execute_|ctl_ir_we~7_combout & (!\z80_|execute_|ctl_mWrite~3_combout & ((!\z80_|execute_|ctl_ir_we~10_combout ) # (!\z80_|nM1_int~2_combout )))) # (!\z80_|execute_|ctl_ir_we~7_combout & -// (((!\z80_|execute_|ctl_ir_we~10_combout ) # (!\z80_|nM1_int~2_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_mWrite~3_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_ir_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~4 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_alu_core_S~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~5_combout = (\z80_|execute_|ctl_alu_core_S~4_combout & (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~7_combout )) # (!\z80_|execute_|ctl_alu_oe~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_S~4_combout ), - .datab(\z80_|execute_|ctl_ir_we~10_combout ), - .datac(\z80_|execute_|ctl_ir_we~7_combout ), - .datad(\z80_|execute_|ctl_alu_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~5 .lut_mask = 16'h02AA; -defparam \z80_|execute_|ctl_alu_core_S~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout = (\z80_|execute_|ctl_mWrite~2_combout & (\z80_|pla_decode_|Equal8~0_combout & (\z80_|sequencer_|DFFE_T5_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ))) - - .dataa(\z80_|execute_|ctl_mWrite~2_combout ), - .datab(\z80_|pla_decode_|Equal8~0_combout ), - .datac(\z80_|sequencer_|DFFE_T5_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_alu_res_oe~0_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout & (((!\z80_|pla_decode_|Equal69~0_combout & !\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal69~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_res_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_res_oe~0 .lut_mask = 16'h0133; -defparam \z80_|execute_|ctl_alu_res_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~15 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~15_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_mWrite~2_combout & !\z80_|sequencer_|DFFE_M1_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~2_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~15 .lut_mask = 16'h0040; -defparam \z80_|execute_|ctl_alu_oe~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~1 ( -// Equation(s): -// \z80_|execute_|ctl_alu_res_oe~1_combout = (\z80_|execute_|ctl_alu_core_S~7_combout & (\z80_|execute_|ctl_alu_core_S~5_combout & (\z80_|execute_|ctl_alu_res_oe~0_combout & !\z80_|execute_|ctl_alu_oe~15_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_S~7_combout ), - .datab(\z80_|execute_|ctl_alu_core_S~5_combout ), - .datac(\z80_|execute_|ctl_alu_res_oe~0_combout ), - .datad(\z80_|execute_|ctl_alu_oe~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_res_oe~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_res_oe~1 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_alu_res_oe~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~2 ( -// Equation(s): -// \z80_|execute_|ctl_alu_res_oe~2_combout = (\z80_|execute_|ctl_flags_alu~11_combout & (\z80_|execute_|ctl_flags_pf_we~3_combout & (\z80_|execute_|ctl_flags_cf_we~2_combout & \z80_|execute_|ctl_alu_res_oe~1_combout ))) - - .dataa(\z80_|execute_|ctl_flags_alu~11_combout ), - .datab(\z80_|execute_|ctl_flags_pf_we~3_combout ), - .datac(\z80_|execute_|ctl_flags_cf_we~2_combout ), - .datad(\z80_|execute_|ctl_alu_res_oe~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_res_oe~2 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_res_oe~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_oe~0_combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # ((!\z80_|ir_|opcode [3] & \z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|pla_decode_|Equal13~2_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_oe~0 .lut_mask = 16'h8C88; -defparam \z80_|execute_|ctl_alu_op2_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N4 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~2 ( -// Equation(s): -// \z80_|alu_|db_high[3]~2_combout = (\z80_|execute_|ctl_alu_bs_oe~combout ) # ((\z80_|execute_|ctl_alu_op1_oe~1_combout ) # ((\z80_|execute_|ctl_alu_op2_oe~0_combout ) # (!\z80_|execute_|ctl_alu_res_oe~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~2 .lut_mask = 16'hFFEF; -defparam \z80_|alu_|db_high[3]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N0 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~3 ( -// Equation(s): -// \z80_|alu_|db_high[3]~3_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout ) # (\z80_|alu_|db_high[3]~2_combout ) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datab(gnd), - .datac(\z80_|alu_|db_high[3]~2_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~3 .lut_mask = 16'hFAFA; -defparam \z80_|alu_|db_high[3]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N20 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~24 ( -// Equation(s): -// \z80_|alu_|db_low[2]~24_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout & (\z80_|alu_|db_low[2]~3_combout & (\z80_|alu_|db_low[2]~6_combout ))) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout & (((\z80_|alu_|db_low[2]~3_combout & -// \z80_|alu_|db_low[2]~6_combout )) # (!\z80_|alu_|db_high[3]~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datab(\z80_|alu_|db_low[2]~3_combout ), - .datac(\z80_|alu_|db_low[2]~6_combout ), - .datad(\z80_|alu_|db_high[3]~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~24 .lut_mask = 16'hC0D5; -defparam \z80_|alu_|db_low[2]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N24 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~7 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~7_combout = (\z80_|reg_control_|reg_sys_we_lo~6_combout & ((!\z80_|execute_|ixy_d~15_combout ) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(\z80_|reg_control_|reg_sys_we_lo~6_combout ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~7 .lut_mask = 16'h0AAA; -defparam \z80_|reg_control_|reg_sys_we_lo~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout = (!\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|nM1_int~2_combout & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|pla_decode_|Equal3~1_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~19 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout = ((!\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_ir_we~8_combout & !\z80_|execute_|ctl_ir_we~10_combout ))) # (!\z80_|nM1_int~2_combout ) - - .dataa(\z80_|execute_|ctl_ir_we~9_combout ), - .datab(\z80_|execute_|ctl_ir_we~8_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_ir_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~19 .lut_mask = 16'h0F1F; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~8_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout & (\z80_|execute_|ctl_flags_sz_we~1_combout & (!\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout & \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~1_combout ), - .datac(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~8 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_reg_in_hi~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~8_combout = (\z80_|reg_control_|reg_sys_we_lo~7_combout & (\z80_|execute_|ctl_reg_in_hi~8_combout & ((!\z80_|execute_|ctl_ir_we~4_combout ) # (!\z80_|pla_decode_|Equal13~2_combout )))) - - .dataa(\z80_|reg_control_|reg_sys_we_lo~7_combout ), - .datab(\z80_|pla_decode_|Equal13~2_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~8 .lut_mask = 16'h2A00; -defparam \z80_|execute_|ctl_alu_oe~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~4_combout = ((!\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_alu_op_low~12_combout & !\z80_|execute_|ctl_alu_op_low~11_combout ))) # (!\z80_|execute_|ixy_d~7_combout ) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~12_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~4 .lut_mask = 16'h5557; -defparam \z80_|execute_|ctl_alu_oe~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~9 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~9_combout = (\z80_|execute_|ctl_flags_use_cf2~13_combout & (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_mWrite~3_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_flags_use_cf2~13_combout ), - .datad(\z80_|execute_|ctl_mWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~9 .lut_mask = 16'h10F0; -defparam \z80_|execute_|ctl_mWrite~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~10_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~9_combout ))) # (!\z80_|sequencer_|M5~q ) - - .dataa(\z80_|sequencer_|M5~q ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_ir_we~9_combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~10 .lut_mask = 16'hFF57; -defparam \z80_|execute_|ctl_alu_core_S~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~43 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~43_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~7_combout ))) # (!\z80_|sequencer_|M5~q ) - - .dataa(\z80_|sequencer_|M5~q ), - .datab(\z80_|execute_|ctl_ir_we~10_combout ), - .datac(\z80_|execute_|ctl_ir_we~7_combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~43 .lut_mask = 16'hFF57; -defparam \z80_|execute_|ctl_bus_inc_oe~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~26 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~26_combout = (\z80_|execute_|ctl_alu_core_S~10_combout & (\z80_|execute_|ctl_bus_inc_oe~43_combout & \z80_|execute_|ctl_bus_inc_oe~25_combout )) - - .dataa(\z80_|execute_|ctl_alu_core_S~10_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~26 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_bus_inc_oe~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_we~5_combout = (\z80_|execute_|ctl_mWrite~9_combout & (\z80_|execute_|ctl_bus_inc_oe~26_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|execute_|ctl_mRead~26_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~9_combout ), - .datab(\z80_|execute_|ctl_mRead~26_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~26_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~5 .lut_mask = 16'h20A0; -defparam \z80_|execute_|ctl_bus_db_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~9_combout = (\z80_|execute_|ctl_alu_oe~8_combout & (\z80_|execute_|ctl_alu_oe~4_combout & (\z80_|execute_|ctl_reg_in_lo~9_combout & \z80_|execute_|ctl_bus_db_we~5_combout ))) - - .dataa(\z80_|execute_|ctl_alu_oe~8_combout ), - .datab(\z80_|execute_|ctl_alu_oe~4_combout ), - .datac(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datad(\z80_|execute_|ctl_bus_db_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~9 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_oe~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~11_combout = (\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_alu_oe~3_combout ) # ((\z80_|pla_decode_|Equal69~0_combout ) # (\z80_|execute_|ctl_mWrite~16_combout )))) - - .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), - .datab(\z80_|pla_decode_|Equal69~0_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_mWrite~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~11 .lut_mask = 16'hF0E0; -defparam \z80_|execute_|ctl_alu_oe~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~5_combout = (\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|execute_|ctl_mWrite~16_combout & ((!\z80_|execute_|ctl_mRead~11_combout ) # (!\z80_|execute_|ctl_mRead~36_combout )))) # (!\z80_|execute_|ctl_state_alu~4_combout & -// (((!\z80_|execute_|ctl_mRead~11_combout ) # (!\z80_|execute_|ctl_mRead~36_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_mWrite~16_combout ), - .datac(\z80_|execute_|ctl_mRead~36_combout ), - .datad(\z80_|execute_|ctl_mRead~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~5 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_alu_oe~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~11_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_ir_we~12_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~11_combout ), - .datab(\z80_|execute_|ctl_ir_we~12_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~11 .lut_mask = 16'hFFF1; -defparam \z80_|execute_|ctl_alu_core_S~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~6_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout & (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal20~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~6 .lut_mask = 16'h0013; -defparam \z80_|execute_|ctl_alu_oe~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~7 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~7_combout = (\z80_|execute_|ctl_alu_oe~6_combout & (((!\z80_|execute_|ctl_mRead~27_combout & !\z80_|execute_|ctl_mRead~26_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_mRead~27_combout ), - .datac(\z80_|execute_|ctl_mRead~26_combout ), - .datad(\z80_|execute_|ctl_alu_oe~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~7 .lut_mask = 16'h5700; -defparam \z80_|execute_|ctl_alu_oe~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~12 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~12_combout = (\z80_|execute_|ctl_alu_oe~11_combout ) # (((!\z80_|execute_|ctl_alu_oe~7_combout ) # (!\z80_|execute_|ctl_alu_core_S~11_combout )) # (!\z80_|execute_|ctl_alu_oe~5_combout )) - - .dataa(\z80_|execute_|ctl_alu_oe~11_combout ), - .datab(\z80_|execute_|ctl_alu_oe~5_combout ), - .datac(\z80_|execute_|ctl_alu_core_S~11_combout ), - .datad(\z80_|execute_|ctl_alu_oe~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~12 .lut_mask = 16'hBFFF; -defparam \z80_|execute_|ctl_alu_oe~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~13 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~13_combout = (\z80_|execute_|ctl_alu_oe~12_combout ) # (((\z80_|execute_|ctl_66_oe~2_combout ) # (!\z80_|execute_|ctl_flags_alu~10_combout )) # (!\z80_|execute_|ctl_flags_xy_we~9_combout )) - - .dataa(\z80_|execute_|ctl_alu_oe~12_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~9_combout ), - .datac(\z80_|execute_|ctl_66_oe~2_combout ), - .datad(\z80_|execute_|ctl_flags_alu~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~13 .lut_mask = 16'hFBFF; -defparam \z80_|execute_|ctl_alu_oe~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~14_combout = (\z80_|execute_|ctl_alu_oe~13_combout ) # (!\z80_|execute_|ctl_alu_oe~9_combout ) - - .dataa(\z80_|execute_|ctl_alu_oe~9_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_oe~13_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~14 .lut_mask = 16'hF5F5; -defparam \z80_|execute_|ctl_alu_oe~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~24 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~24_combout = (\z80_|execute_|ctl_flags_xy_we~12_combout & (((!\z80_|pla_decode_|Equal48~0_combout & !\z80_|pla_decode_|Equal69~0_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|pla_decode_|Equal48~0_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~12_combout ), - .datad(\z80_|pla_decode_|Equal69~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~24 .lut_mask = 16'h3070; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~27 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~27_combout = (\z80_|pla_decode_|Equal20~0_combout & (!\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ixy_d~6_combout ) # (!\z80_|execute_|ctl_mRead~26_combout )))) # (!\z80_|pla_decode_|Equal20~0_combout & -// (((!\z80_|execute_|ixy_d~6_combout )) # (!\z80_|execute_|ctl_mRead~26_combout ))) - - .dataa(\z80_|pla_decode_|Equal20~0_combout ), - .datab(\z80_|execute_|ctl_mRead~26_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~27 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~40 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~40_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~24_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~27_combout & \z80_|execute_|nextM~11_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~27_combout ), - .datad(\z80_|execute_|nextM~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~40 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~53 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~53_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal21~1_combout ) # (!\z80_|sequencer_|DFFE_T4_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), - .datad(\z80_|pla_decode_|Equal21~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~53 .lut_mask = 16'hB0F0; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_hi~8_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & ((\z80_|execute_|ctl_ir_we~12_combout ) # (!\z80_|execute_|nextM~2_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~12_combout ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|execute_|nextM~2_combout ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_hi~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_hi~8 .lut_mask = 16'h8C00; -defparam \z80_|execute_|ctl_reg_out_hi~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|setM1~54 ( -// Equation(s): -// \z80_|execute_|setM1~54_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|execute_|ctl_ir_we~9_combout ), - .datac(\z80_|execute_|ctl_ir_we~10_combout ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~54_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~54 .lut_mask = 16'hABFF; -defparam \z80_|execute_|setM1~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~1 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~1_combout = ((!\z80_|execute_|ctl_ir_we~8_combout & (!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_state_alu~7_combout ))) # (!\z80_|execute_|ctl_eval_cond~0_combout ) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_state_alu~7_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~1 .lut_mask = 16'h01FF; -defparam \z80_|execute_|ctl_sw_2u~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~4 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~4_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|execute_|ctl_mWrite~5_combout & ((!\z80_|execute_|ctl_alu_oe~3_combout )))) # (!\z80_|execute_|ctl_eval_cond~0_combout & (((!\z80_|execute_|ctl_ir_we~4_combout )) # -// (!\z80_|execute_|ctl_mWrite~5_combout ))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|ctl_mWrite~5_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|execute_|ctl_alu_oe~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~4 .lut_mask = 16'h1537; -defparam \z80_|execute_|ctl_sw_2u~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~5 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~5_combout = (\z80_|execute_|setM1~54_combout & (\z80_|execute_|ctl_sw_2u~1_combout & \z80_|execute_|ctl_sw_2u~4_combout )) - - .dataa(\z80_|execute_|setM1~54_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_sw_2u~1_combout ), - .datad(\z80_|execute_|ctl_sw_2u~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~5 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_sw_2u~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~6 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~6_combout = (\z80_|execute_|ctl_reg_gp_sel~36_combout & (\z80_|execute_|comb~0_combout $ ((!\z80_|ir_|opcode [0])))) # (!\z80_|execute_|ctl_reg_gp_sel~36_combout & (!\z80_|execute_|ctl_sw_2u~5_combout & -// (\z80_|execute_|comb~0_combout $ (!\z80_|ir_|opcode [0])))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel~36_combout ), - .datab(\z80_|execute_|comb~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|execute_|ctl_sw_2u~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~6 .lut_mask = 16'h82C3; -defparam \z80_|execute_|ctl_sw_2u~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~35 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~35_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ctl_state_alu~5_combout & ((!\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|pla_decode_|Equal47~0_combout & -// (((!\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|pla_decode_|Equal34~0_combout ), - .datad(\z80_|execute_|ctl_state_alu~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~35 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_inc_cy~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~35 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~35_combout = (\z80_|execute_|ctl_inc_cy~35_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|sequencer_|DFFE_M4_ff~q ) # (!\z80_|pla_decode_|Equal19~0_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|pla_decode_|Equal19~0_combout ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|execute_|ctl_inc_cy~35_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~35 .lut_mask = 16'hBF00; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~6 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~6_combout = (\z80_|pla_decode_|Equal55~0_combout & (!\z80_|ir_|opcode [3] & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~6 .lut_mask = 16'h0200; -defparam \z80_|execute_|ctl_mWrite~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~2 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~2_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|execute_|ctl_mWrite~6_combout & ((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|execute_|ctl_eval_cond~0_combout & -// (((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|ctl_mWrite~6_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|execute_|ctl_mRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~2 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_sw_2u~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~0 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~0_combout = (\z80_|pla_decode_|Equal9~1_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((!\z80_|execute_|ctl_mWrite~4_combout ) # (!\z80_|execute_|ctl_state_alu~5_combout )))) # (!\z80_|pla_decode_|Equal9~1_combout & -// (((!\z80_|execute_|ctl_mWrite~4_combout ) # (!\z80_|execute_|ctl_state_alu~5_combout )))) - - .dataa(\z80_|pla_decode_|Equal9~1_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_state_alu~5_combout ), - .datad(\z80_|execute_|ctl_mWrite~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~0 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_sw_2u~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~3 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~3_combout = (\z80_|execute_|ctl_sw_2u~2_combout & (\z80_|execute_|ctl_sw_2u~0_combout & ((!\z80_|execute_|ctl_alu_oe~2_combout ) # (!\z80_|execute_|ctl_mRead~8_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~8_combout ), - .datab(\z80_|execute_|ctl_sw_2u~2_combout ), - .datac(\z80_|execute_|ctl_sw_2u~0_combout ), - .datad(\z80_|execute_|ctl_alu_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~3 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_sw_2u~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~52 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~52_combout = (\z80_|execute_|ctl_sw_2u~3_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|sequencer_|M5~q )) # (!\z80_|execute_|ctl_mRead~10_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|execute_|ctl_sw_2u~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~52 .lut_mask = 16'hDF00; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout = (\z80_|pla_decode_|Equal1~4_combout & (\z80_|ir_|opcode [0] & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~4_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~2_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|pla_decode_|Equal69~0_combout ) # (\z80_|execute_|ctl_alu_op_low~13_combout )))) - - .dataa(\z80_|pla_decode_|Equal69~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~13_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~2 .lut_mask = 16'hFEF0; -defparam \z80_|execute_|ctl_reg_out_lo~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N18 -cycloneive_lcell_comb \z80_|execute_|rsel3 ( -// Equation(s): -// \z80_|execute_|rsel3~combout = \z80_|ir_|opcode [3] $ (((\z80_|ir_|opcode [4] & \z80_|ir_|opcode [5]))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|ir_|opcode [3]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|rsel3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|rsel3 .lut_mask = 16'h7878; -defparam \z80_|execute_|rsel3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_hi~5_combout = (\z80_|execute_|ctl_mRead~5_combout & (!\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|rsel3~combout ) # (!\z80_|execute_|ctl_reg_out_lo~2_combout )))) # (!\z80_|execute_|ctl_mRead~5_combout & -// (((\z80_|execute_|rsel3~combout ) # (!\z80_|execute_|ctl_reg_out_lo~2_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~5_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|execute_|ctl_reg_out_lo~2_combout ), - .datad(\z80_|execute_|rsel3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_hi~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_hi~5 .lut_mask = 16'h7707; -defparam \z80_|execute_|ctl_reg_out_hi~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_hi~6_combout = (!\z80_|execute_|ctl_sw_2u~6_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout & \z80_|execute_|ctl_reg_out_hi~5_combout ))) - - .dataa(\z80_|execute_|ctl_sw_2u~6_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ), - .datad(\z80_|execute_|ctl_reg_out_hi~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_hi~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_hi~6 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_out_hi~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_hi~7_combout = ((\z80_|execute_|ctl_reg_out_hi~8_combout ) # ((!\z80_|execute_|ctl_reg_out_hi~6_combout ) # (!\z80_|execute_|ctl_reg_out_hi~4_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ), - .datab(\z80_|execute_|ctl_reg_out_hi~8_combout ), - .datac(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .datad(\z80_|execute_|ctl_reg_out_hi~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_hi~7 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_reg_out_hi~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N28 -cycloneive_lcell_comb \z80_|execute_|rsel0 ( -// Equation(s): -// \z80_|execute_|rsel0~combout = \z80_|ir_|opcode [0] $ (((\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1]))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(gnd), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|execute_|rsel0~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|rsel0 .lut_mask = 16'h5AAA; -defparam \z80_|execute_|rsel0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout = (\z80_|execute_|ixy_d~15_combout & \z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(gnd), - .datab(\z80_|execute_|ixy_d~15_combout ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 .lut_mask = 16'hC0C0; -defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~33 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~33_combout = (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout & (\z80_|execute_|ctl_reg_use_sp~0_combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_mRead~36_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), - .datab(\z80_|execute_|ctl_reg_use_sp~0_combout ), - .datac(\z80_|execute_|ctl_mRead~36_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~33 .lut_mask = 16'h0444; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~6_combout = (\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout & ((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~6 .lut_mask = 16'h0888; -defparam \z80_|execute_|ctl_reg_out_lo~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~7_combout = (\z80_|execute_|ctl_reg_out_lo~6_combout & (((!\z80_|execute_|ctl_reg_gp_sel~36_combout & \z80_|execute_|ctl_sw_2u~5_combout )) # (!\z80_|execute_|rsel0~combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel~36_combout ), - .datab(\z80_|execute_|rsel0~combout ), - .datac(\z80_|execute_|ctl_reg_out_lo~6_combout ), - .datad(\z80_|execute_|ctl_sw_2u~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~7 .lut_mask = 16'h7030; -defparam \z80_|execute_|ctl_reg_out_lo~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_iorw~11 ( -// Equation(s): -// \z80_|execute_|ctl_iorw~11_combout = (!\z80_|ir_|opcode [1] & (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [2] & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_iorw~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_iorw~11 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_iorw~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~10 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~10_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (((\z80_|execute_|rsel3~combout & \z80_|execute_|ctl_iorw~11_combout )) # (!\z80_|execute_|nextM~2_combout ))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|rsel3~combout ), - .datac(\z80_|execute_|nextM~2_combout ), - .datad(\z80_|execute_|ctl_iorw~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~10 .lut_mask = 16'h8A0A; -defparam \z80_|execute_|ctl_sw_2d~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~14 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~14_combout = (!\z80_|execute_|ctl_mRead~14_combout & (((\z80_|decode_state_|in_halt~q ) # (!\z80_|pla_decode_|Equal33~0_combout )) # (!\z80_|pla_decode_|Equal77~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal77~0_combout ), - .datab(\z80_|decode_state_|in_halt~q ), - .datac(\z80_|execute_|ctl_mRead~14_combout ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~14 .lut_mask = 16'h0D0F; -defparam \z80_|execute_|ctl_sw_2d~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~11 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~11_combout = (\z80_|execute_|ctl_sw_2d~10_combout ) # ((\z80_|nM1_int~2_combout & ((!\z80_|execute_|ctl_sw_1d~8_combout ) # (!\z80_|execute_|ctl_sw_2d~14_combout )))) - - .dataa(\z80_|execute_|ctl_sw_2d~10_combout ), - .datab(\z80_|execute_|ctl_sw_2d~14_combout ), - .datac(\z80_|execute_|ctl_sw_1d~8_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~11 .lut_mask = 16'hBFAA; -defparam \z80_|execute_|ctl_sw_2d~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~12 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~12_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|execute_|rsel3~combout & ((\z80_|execute_|ctl_alu_op_low~14_combout ) # (\z80_|execute_|ctl_alu_shift_oe~15_combout )))) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .datad(\z80_|execute_|rsel3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~12 .lut_mask = 16'hFEAA; -defparam \z80_|execute_|ctl_sw_2d~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~13 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~13_combout = ((\z80_|execute_|ctl_sw_2d~11_combout ) # ((\z80_|execute_|ctl_sw_2d~12_combout ) # (!\z80_|execute_|ctl_sw_2d~9_combout ))) # (!\z80_|execute_|ctl_reg_out_lo~7_combout ) - - .dataa(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .datab(\z80_|execute_|ctl_sw_2d~11_combout ), - .datac(\z80_|execute_|ctl_sw_2d~12_combout ), - .datad(\z80_|execute_|ctl_sw_2d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~13 .lut_mask = 16'hFDFF; -defparam \z80_|execute_|ctl_sw_2d~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_66_oe ( -// Equation(s): -// \z80_|execute_|ctl_66_oe~combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|sequencer_|DFFE_T3_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|pla_decode_|Equal47~0_combout ))) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_66_oe~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_66_oe .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_66_oe .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~34 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~34_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|pla_decode_|Equal47~0_combout & ((!\z80_|execute_|ctl_alu_oe~2_combout ) # (!\z80_|pla_decode_|Equal34~0_combout )))) # (!\z80_|execute_|ixy_d~7_combout & -// (((!\z80_|execute_|ctl_alu_oe~2_combout )) # (!\z80_|pla_decode_|Equal34~0_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|pla_decode_|Equal34~0_combout ), - .datac(\z80_|pla_decode_|Equal47~0_combout ), - .datad(\z80_|execute_|ctl_alu_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~34 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_inc_cy~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~0 ( -// Equation(s): -// \z80_|execute_|ctl_apin_mux~0_combout = (\z80_|execute_|ctl_inc_cy~34_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout & ((!\z80_|execute_|ctl_alu_oe~2_combout ) # (!\z80_|pla_decode_|Equal19~0_combout )))) - - .dataa(\z80_|execute_|ctl_inc_cy~34_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), - .datac(\z80_|pla_decode_|Equal19~0_combout ), - .datad(\z80_|execute_|ctl_alu_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_apin_mux~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_apin_mux~0 .lut_mask = 16'h0888; -defparam \z80_|execute_|ctl_apin_mux~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~5 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~5_combout = (\z80_|execute_|ctl_alu_op_low~14_combout ) # (((\z80_|execute_|ctl_alu_shift_oe~14_combout & \z80_|pla_decode_|Equal47~0_combout )) # (!\z80_|execute_|ctl_sw_4u~1_combout )) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ctl_sw_4u~1_combout ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~5 .lut_mask = 16'hEFCF; -defparam \z80_|execute_|ctl_sw_4u~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~75 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~75_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & (!\z80_|pla_decode_|Equal38~2_combout & ((!\z80_|pla_decode_|Equal37~0_combout )))) # (!\z80_|execute_|ctl_alu_op_low~8_combout & (((!\z80_|pla_decode_|Equal38~2_combout -// & !\z80_|pla_decode_|Equal37~0_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datab(\z80_|pla_decode_|Equal38~2_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|pla_decode_|Equal37~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~75_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~75 .lut_mask = 16'h0537; -defparam \z80_|execute_|ctl_inc_cy~75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~76 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~76_combout = (\z80_|execute_|ctl_inc_cy~75_combout & (((!\z80_|execute_|ctl_alu_op_low~8_combout & !\z80_|execute_|ixy_d~5_combout )) # (!\z80_|pla_decode_|Equal29~0_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~75_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|pla_decode_|Equal29~0_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~76_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~76 .lut_mask = 16'h0A2A; -defparam \z80_|execute_|ctl_inc_cy~76 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal4~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal4~0_combout = (\z80_|execute_|comb~1_combout & (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal1~7_combout & \z80_|pla_decode_|Equal1~4_combout ))) - - .dataa(\z80_|execute_|comb~1_combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|pla_decode_|Equal1~7_combout ), - .datad(\z80_|pla_decode_|Equal1~4_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal4~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal4~0 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y19_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~48 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~48_combout = (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|execute_|ctl_mWrite~4_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|execute_|ctl_mWrite~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~48 .lut_mask = 16'h1FFF; -defparam \z80_|execute_|ctl_bus_inc_oe~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~46 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~46_combout = (\z80_|execute_|ctl_bus_inc_oe~48_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T5_ff~q )) # (!\z80_|pla_decode_|Equal4~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal4~0_combout ), + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|execute_|ctl_bus_inc_oe~48_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal3~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_iy_set~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_iy_set~2 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_state_iy_set~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N18 +cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_16 ( +// Equation(s): +// \z80_|sequencer_|SYNTHESIZED_WIRE_16~combout = (\z80_|execute_|setM1~54_combout & (\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|execute_|nextM~14_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|setM1~54_combout ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_16 .lut_mask = 16'h00C0; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y13_N19 +dffeas \z80_|sequencer_|DFFE_T5_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_T5_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_T5_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_T5_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_state_ixiy_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_state_ixiy_we~2_combout = (\z80_|execute_|ixy_d~15_combout & ((\z80_|sequencer_|DFFE_T5_ff~q ) # ((!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T2_ff~q )))) # (!\z80_|execute_|ixy_d~15_combout & +// (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|execute_|ixy_d~15_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), .datad(\z80_|sequencer_|DFFE_T5_ff~q ), .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~46_combout ), + .combout(\z80_|execute_|ctl_state_ixiy_we~2_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~46 .lut_mask = 16'hD0F0; -defparam \z80_|execute_|ctl_bus_inc_oe~46 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_state_ixiy_we~2 .lut_mask = 16'hBA30; +defparam \z80_|execute_|ctl_state_ixiy_we~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y18_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~53 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~53_combout = (\z80_|execute_|ctl_mRead~16_combout & (!\z80_|execute_|ctl_alu_op_low~8_combout & ((!\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|execute_|ctl_mRead~16_combout & (((!\z80_|execute_|ctl_alu_op_low~8_combout & -// !\z80_|execute_|ixy_d~5_combout )) # (!\z80_|pla_decode_|Equal9~1_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~16_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~53_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~53 .lut_mask = 16'h0537; -defparam \z80_|execute_|ctl_inc_cy~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~92 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~92_combout = (((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|pla_decode_|Equal9~1_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|sequencer_|DFFE_M4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~92_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~92 .lut_mask = 16'h5F7F; -defparam \z80_|execute_|ctl_inc_cy~92 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal19~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal19~1_combout = (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal32~0_combout & \z80_|pla_decode_|Equal52~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|pla_decode_|Equal32~0_combout ), - .datad(\z80_|pla_decode_|Equal52~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal19~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal19~1 .lut_mask = 16'h2000; -defparam \z80_|pla_decode_|Equal19~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~0 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~0_combout = (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|M5~q ) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|sequencer_|M5~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~0 .lut_mask = 16'hAA00; -defparam \z80_|execute_|ctl_sw_4u~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~38 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~38_combout = (((!\z80_|execute_|ctl_alu_shift_oe~14_combout & !\z80_|execute_|ctl_sw_4u~0_combout )) # (!\z80_|pla_decode_|Equal3~1_combout )) # (!\z80_|pla_decode_|Equal19~1_combout ) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|pla_decode_|Equal19~1_combout ), - .datac(\z80_|execute_|ctl_sw_4u~0_combout ), - .datad(\z80_|pla_decode_|Equal3~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~38 .lut_mask = 16'h37FF; -defparam \z80_|execute_|ctl_inc_cy~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~93 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~93_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|pla_decode_|Equal34~0_combout ) - - .dataa(\z80_|pla_decode_|Equal34~0_combout ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~93_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~93 .lut_mask = 16'h57FF; -defparam \z80_|execute_|ctl_inc_cy~93 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~39 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~39_combout = (\z80_|execute_|ctl_inc_cy~93_combout & (((!\z80_|execute_|ctl_alu_op_low~8_combout & !\z80_|execute_|ixy_d~5_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|execute_|ctl_inc_cy~93_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~39 .lut_mask = 16'h444C; -defparam \z80_|execute_|ctl_inc_cy~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~24 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~24_combout = (\z80_|execute_|ctl_inc_cy~92_combout & (\z80_|execute_|ctl_inc_cy~38_combout & \z80_|execute_|ctl_inc_cy~39_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_inc_cy~92_combout ), - .datac(\z80_|execute_|ctl_inc_cy~38_combout ), - .datad(\z80_|execute_|ctl_inc_cy~39_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~24 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_bus_inc_oe~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~1 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~1_combout = (\z80_|execute_|ctl_inc_cy~76_combout & (\z80_|execute_|ctl_bus_inc_oe~46_combout & (\z80_|execute_|ctl_inc_cy~53_combout & \z80_|execute_|ctl_bus_inc_oe~24_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~76_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~46_combout ), - .datac(\z80_|execute_|ctl_inc_cy~53_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~1 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_we~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T5_ff~q & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal8~0_combout ))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T5_ff~q ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|pla_decode_|Equal8~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~44 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~44_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout & (((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|pla_decode_|Equal11~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal11~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~44 .lut_mask = 16'h1333; -defparam \z80_|execute_|ctl_bus_inc_oe~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~5_combout = ((!\z80_|pla_decode_|Equal10~0_combout & (!\z80_|pla_decode_|Equal11~0_combout & !\z80_|execute_|ctl_mRead~36_combout ))) # (!\z80_|execute_|ctl_alu_op_low~8_combout ) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|execute_|ctl_mRead~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~5 .lut_mask = 16'h3337; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~0_combout = (\z80_|execute_|ctl_bus_inc_oe~44_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~5_combout & ((!\z80_|execute_|ctl_mWrite~16_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_mWrite~16_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~0 .lut_mask = 16'h2A00; -defparam \z80_|execute_|ctl_reg_gp_we~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|sequencer_|M5~q & \z80_|pla_decode_|Equal9~1_combout )) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~35 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~35_combout = (\z80_|execute_|ctl_reg_gp_we~0_combout & (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout & ((!\z80_|pla_decode_|Equal10~0_combout ) # (!\z80_|execute_|ixy_d~9_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_we~0_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), - .datad(\z80_|pla_decode_|Equal10~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~35 .lut_mask = 16'h020A; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~2 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~2_combout = (\z80_|execute_|ixy_d~5_combout & (\z80_|execute_|nextM~2_combout & ((!\z80_|execute_|ixy_d~9_combout ) # (!\z80_|pla_decode_|Equal11~0_combout )))) # (!\z80_|execute_|ixy_d~5_combout & -// (((!\z80_|execute_|ixy_d~9_combout )) # (!\z80_|pla_decode_|Equal11~0_combout ))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|execute_|nextM~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~2 .lut_mask = 16'h3F15; -defparam \z80_|execute_|ctl_sw_4u~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~3 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~3_combout = (\z80_|execute_|ctl_reg_gp_we~1_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout & \z80_|execute_|ctl_sw_4u~2_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~1_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ), - .datad(\z80_|execute_|ctl_sw_4u~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~3 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_sw_4u~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N0 -cycloneive_lcell_comb \z80_|execute_|fMRead~3 ( -// Equation(s): -// \z80_|execute_|fMRead~3_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & (!\z80_|execute_|ctl_state_alu~14_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_mRead~15_combout )))) # -// (!\z80_|execute_|ctl_alu_op_low~8_combout & (((!\z80_|execute_|ctl_alu_shift_oe~14_combout )) # (!\z80_|execute_|ctl_mRead~15_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datab(\z80_|execute_|ctl_mRead~15_combout ), - .datac(\z80_|execute_|ctl_state_alu~14_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~3 .lut_mask = 16'h135F; -defparam \z80_|execute_|fMRead~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~4 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~4_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal55~0_combout & (!\z80_|ir_|opcode [5] & \z80_|execute_|ctl_alu_op_low~8_combout ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~4 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_sw_4u~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout = (\z80_|execute_|ctl_alu_shift_oe~14_combout & (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~15 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~15_combout = (!\z80_|execute_|ctl_sw_4u~4_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_ir_we~12_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~12_combout ), - .datab(\z80_|execute_|ctl_sw_4u~4_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~15 .lut_mask = 16'h0013; -defparam \z80_|execute_|ctl_reg_sel_wz~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~8_combout = (\z80_|execute_|ctl_mRead~10_combout & (!\z80_|execute_|ctl_alu_shift_oe~14_combout & ((!\z80_|execute_|ctl_sw_4u~0_combout )))) # (!\z80_|execute_|ctl_mRead~10_combout & -// (((!\z80_|execute_|ctl_alu_shift_oe~14_combout & !\z80_|execute_|ctl_sw_4u~0_combout )) # (!\z80_|execute_|ctl_mRead~8_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datac(\z80_|execute_|ctl_mRead~8_combout ), - .datad(\z80_|execute_|ctl_sw_4u~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~8 .lut_mask = 16'h0537; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~94 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~94_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|execute_|ctl_mRead~17_combout ) - - .dataa(\z80_|execute_|ctl_mRead~17_combout ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~94_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~94 .lut_mask = 16'h57FF; -defparam \z80_|execute_|ctl_inc_cy~94 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~87 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~87_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|pla_decode_|Equal13~2_combout ) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~87_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~87 .lut_mask = 16'h5FFF; -defparam \z80_|execute_|ctl_inc_cy~87 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~42 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~42_combout = (\z80_|pla_decode_|Equal12~1_combout ) # (((!\z80_|execute_|ctl_sw_4u~0_combout & !\z80_|execute_|ctl_alu_shift_oe~14_combout )) # (!\z80_|pla_decode_|Equal25~0_combout )) - - .dataa(\z80_|execute_|ctl_sw_4u~0_combout ), - .datab(\z80_|pla_decode_|Equal12~1_combout ), - .datac(\z80_|pla_decode_|Equal25~0_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~42 .lut_mask = 16'hCFDF; -defparam \z80_|execute_|ctl_inc_cy~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~34 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~34_combout = (\z80_|execute_|ctl_inc_cy~94_combout & (\z80_|execute_|ctl_inc_cy~87_combout & \z80_|execute_|ctl_inc_cy~42_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_inc_cy~94_combout ), - .datac(\z80_|execute_|ctl_inc_cy~87_combout ), - .datad(\z80_|execute_|ctl_inc_cy~42_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~34 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~16 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~16_combout = (\z80_|execute_|fMRead~3_combout & (\z80_|execute_|ctl_reg_sel_wz~15_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ))) - - .dataa(\z80_|execute_|fMRead~3_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~15_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~16 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sel_wz~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~6 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~6_combout = ((\z80_|execute_|ctl_sw_4u~5_combout ) # ((!\z80_|execute_|ctl_reg_sel_wz~16_combout ) # (!\z80_|execute_|ctl_sw_4u~3_combout ))) # (!\z80_|execute_|ctl_apin_mux~0_combout ) - - .dataa(\z80_|execute_|ctl_apin_mux~0_combout ), - .datab(\z80_|execute_|ctl_sw_4u~5_combout ), - .datac(\z80_|execute_|ctl_sw_4u~3_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~6 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_sw_4u~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N22 -cycloneive_lcell_comb \z80_|pla_decode_|Equal2~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal2~2_combout = (\z80_|pla_decode_|Equal1~7_combout & (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal32~0_combout & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~7_combout ), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|pla_decode_|Equal32~0_combout ), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal2~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal2~2 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal2~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal1~6 ( -// Equation(s): -// \z80_|pla_decode_|Equal1~6_combout = (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal1~5_combout & (\z80_|pla_decode_|Equal1~7_combout & \z80_|pla_decode_|Equal1~4_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal1~5_combout ), - .datac(\z80_|pla_decode_|Equal1~7_combout ), - .datad(\z80_|pla_decode_|Equal1~4_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal1~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal1~6 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal1~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N22 -cycloneive_lcell_comb \z80_|reg_control_|bank_exx~2 ( -// Equation(s): -// \z80_|reg_control_|bank_exx~2_combout = \z80_|reg_control_|bank_exx~q $ (((!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal1~6_combout & \z80_|sequencer_|DFFE_T2_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|pla_decode_|Equal1~6_combout ), - .datac(\z80_|reg_control_|bank_exx~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|reg_control_|bank_exx~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|bank_exx~2 .lut_mask = 16'hB4F0; -defparam \z80_|reg_control_|bank_exx~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y13_N23 -dffeas \z80_|reg_control_|bank_exx ( +// Location: FF_X26_Y16_N7 +dffeas \z80_|decode_state_|DFFE_instIY1 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_control_|bank_exx~2_combout ), + .d(\z80_|execute_|ctl_state_iy_set~2_combout ), .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(vcc), + .ena(\z80_|execute_|ctl_state_ixiy_we~2_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|reg_control_|bank_exx~q ), + .q(\z80_|decode_state_|DFFE_instIY1~q ), .prn(vcc)); // synopsys translate_off -defparam \z80_|reg_control_|bank_exx .is_wysiwyg = "true"; -defparam \z80_|reg_control_|bank_exx .power_up = "low"; +defparam \z80_|decode_state_|DFFE_instIY1 .is_wysiwyg = "true"; +defparam \z80_|decode_state_|DFFE_instIY1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y15_N26 -cycloneive_lcell_comb \z80_|reg_control_|bank_hl_de1~0 ( +// Location: LCCOMB_X25_Y16_N10 +cycloneive_lcell_comb \z80_|decode_state_|use_ixiy ( // Equation(s): -// \z80_|reg_control_|bank_hl_de1~0_combout = \z80_|reg_control_|bank_hl_de1~q $ (((\z80_|pla_decode_|Equal2~2_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & !\z80_|reg_control_|bank_exx~q )))) - - .dataa(\z80_|pla_decode_|Equal2~2_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|reg_control_|bank_hl_de1~q ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_control_|bank_hl_de1~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|bank_hl_de1~0 .lut_mask = 16'hF0D2; -defparam \z80_|reg_control_|bank_hl_de1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y15_N27 -dffeas \z80_|reg_control_|bank_hl_de1 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_control_|bank_hl_de1~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_control_|bank_hl_de1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_control_|bank_hl_de1 .is_wysiwyg = "true"; -defparam \z80_|reg_control_|bank_hl_de1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~10 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~10_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|pla_decode_|Equal4~0_combout ) # ((\z80_|pla_decode_|Equal2~1_combout & \z80_|pla_decode_|Equal1~4_combout )))) - - .dataa(\z80_|pla_decode_|Equal4~0_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|pla_decode_|Equal2~1_combout ), - .datad(\z80_|pla_decode_|Equal1~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~10 .lut_mask = 16'hC888; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~11 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~11_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout ) # (\z80_|execute_|ctl_state_alu~4_combout )))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|nextM~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~11 .lut_mask = 16'h00FE; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~12 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~12_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ) # ((\z80_|execute_|ctl_state_alu~4_combout & \z80_|execute_|ctl_mRead~36_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_mRead~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~12 .lut_mask = 16'hFEEE; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~7 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~7_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|decode_state_|use_ixiy~combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~7 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_mRead~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~9_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mRead~5_combout ) # ((\z80_|execute_|ctl_mRead~7_combout ) # (\z80_|execute_|ctl_mWrite~16_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~5_combout ), - .datab(\z80_|execute_|ctl_mRead~7_combout ), - .datac(\z80_|execute_|ctl_mWrite~16_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~9 .lut_mask = 16'hFE00; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~37 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~37_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~5_combout & (((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|execute_|ctl_mWrite~16_combout ))) - - .dataa(\z80_|execute_|ctl_mWrite~16_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~37 .lut_mask = 16'h4CCC; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~13 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~13_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~12_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~9_combout ) # ((\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ) # (!\z80_|execute_|ctl_reg_gp_sel[1]~37_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~12_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~9_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~37_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~13 .lut_mask = 16'hFFEF; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~47 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~47_combout = (\z80_|decode_state_|DFFE_inst4~q ) # ((\z80_|decode_state_|DFFE_instIY1~q ) # ((!\z80_|pla_decode_|Equal50~0_combout & !\z80_|pla_decode_|Equal49~0_combout ))) - - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(\z80_|decode_state_|DFFE_instIY1~q ), - .datac(\z80_|pla_decode_|Equal50~0_combout ), - .datad(\z80_|pla_decode_|Equal49~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~47 .lut_mask = 16'hEEEF; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|fMWrite~3 ( -// Equation(s): -// \z80_|execute_|fMWrite~3_combout = (!\z80_|execute_|ctl_ir_we~15_combout & (!\z80_|execute_|ctl_ir_we~14_combout & (!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_mRead~6_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~15_combout ), - .datab(\z80_|execute_|ctl_ir_we~14_combout ), - .datac(\z80_|execute_|ctl_ir_we~7_combout ), - .datad(\z80_|execute_|ctl_mRead~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~3 .lut_mask = 16'h0001; -defparam \z80_|execute_|fMWrite~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~5_combout = (\z80_|ir_|opcode [2]) # ((\z80_|ir_|opcode [1]) # (!\z80_|execute_|ctl_mWrite~2_combout )) - - .dataa(\z80_|ir_|opcode [2]), - .datab(gnd), - .datac(\z80_|execute_|ctl_mWrite~2_combout ), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~5 .lut_mask = 16'hFFAF; -defparam \z80_|execute_|ctl_flags_bus~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N26 -cycloneive_lcell_comb \z80_|execute_|fMRead~2 ( -// Equation(s): -// \z80_|execute_|fMRead~2_combout = (!\z80_|pla_decode_|Equal13~2_combout & (!\z80_|execute_|ctl_state_alu~14_combout & \z80_|execute_|ctl_flags_bus~5_combout )) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(\z80_|execute_|ctl_state_alu~14_combout ), - .datac(\z80_|execute_|ctl_flags_bus~5_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|fMRead~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~2 .lut_mask = 16'h1010; -defparam \z80_|execute_|fMRead~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~19 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~19_combout = (\z80_|execute_|fMWrite~3_combout & (\z80_|execute_|fMRead~2_combout & !\z80_|execute_|ctl_ir_we~12_combout )) +// \z80_|decode_state_|use_ixiy~combout = (\z80_|decode_state_|DFFE_inst4~q ) # (\z80_|decode_state_|DFFE_instIY1~q ) .dataa(gnd), - .datab(\z80_|execute_|fMWrite~3_combout ), - .datac(\z80_|execute_|fMRead~2_combout ), - .datad(\z80_|execute_|ctl_ir_we~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~19 .lut_mask = 16'h00C0; -defparam \z80_|execute_|ctl_mRead~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~7_combout = (\z80_|execute_|ctl_state_alu~5_combout & (((\z80_|execute_|ctl_mRead~36_combout ) # (!\z80_|execute_|ctl_mRead~19_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), - .datab(\z80_|execute_|ctl_state_alu~5_combout ), - .datac(\z80_|execute_|ctl_mRead~36_combout ), - .datad(\z80_|execute_|ctl_mRead~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~7 .lut_mask = 16'hC4CC; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~8_combout = (\z80_|ir_|opcode [2] & ((!\z80_|execute_|ctl_sw_2u~5_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), - .datab(gnd), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|execute_|ctl_sw_2u~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~8 .lut_mask = 16'h50F0; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~14 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~14_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~13_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~7_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~8_combout ) # (!\z80_|execute_|ctl_alu_op_low~15_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~13_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~7_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~15_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~14 .lut_mask = 16'hFFEF; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~16 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~16_combout = (\z80_|ir_|opcode [3] & (((\z80_|sequencer_|DFFE_T3_ff~q )))) # (!\z80_|ir_|opcode [3] & (((\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|pla_decode_|Equal12~0_combout )) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal12~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~16 .lut_mask = 16'hC5CD; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~15 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~15_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|ir_|opcode [3] & (\z80_|ir_|opcode [7] & \z80_|ir_|opcode [6]))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|ir_|opcode [6]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~15 .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~17 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~17_combout = (\z80_|ir_|opcode [0] & (((\z80_|execute_|ctl_reg_gp_sel[1]~15_combout )))) # (!\z80_|ir_|opcode [0] & (\z80_|execute_|ctl_reg_gp_sel[1]~16_combout & ((\z80_|execute_|ctl_ir_we~6_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~16_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|execute_|ctl_ir_we~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~17 .lut_mask = 16'hCAC0; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~19 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~19_combout = (!\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2])) - - .dataa(\z80_|ir_|opcode [4]), - .datab(gnd), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~19 .lut_mask = 16'h0050; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~2_combout = (((!\z80_|execute_|ctl_mRead~11_combout & !\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal8~0_combout )) # (!\z80_|pla_decode_|Equal6~0_combout ) - - .dataa(\z80_|execute_|ctl_mRead~11_combout ), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal8~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~2 .lut_mask = 16'h37FF; -defparam \z80_|execute_|ctl_reg_use_sp~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~47 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~47_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q ))) # (!\z80_|execute_|ctl_mRead~8_combout ) - - .dataa(\z80_|sequencer_|M5~q ), - .datab(\z80_|execute_|ctl_mRead~8_combout ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~47 .lut_mask = 16'hFF37; -defparam \z80_|execute_|ctl_bus_inc_oe~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~3_combout = (\z80_|execute_|ctl_reg_use_sp~2_combout & (\z80_|execute_|ctl_reg_use_sp~0_combout & (\z80_|execute_|ctl_bus_inc_oe~47_combout & \z80_|execute_|nextM~11_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~2_combout ), - .datab(\z80_|execute_|ctl_reg_use_sp~0_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~47_combout ), - .datad(\z80_|execute_|nextM~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~3 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_use_sp~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~9 ( -// Equation(s): -// \z80_|execute_|ctl_sw_1d~9_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal6~1_combout & !\z80_|sequencer_|DFFE_M1_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal6~1_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~9 .lut_mask = 16'h0050; -defparam \z80_|execute_|ctl_sw_1d~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~21 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~21_combout = (!\z80_|execute_|ctl_sw_1d~9_combout & (((!\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ctl_state_alu~5_combout )) # (!\z80_|execute_|ctl_mWrite~4_combout ))) - - .dataa(\z80_|execute_|ctl_mWrite~4_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|execute_|ctl_state_alu~5_combout ), - .datad(\z80_|execute_|ctl_sw_1d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~21 .lut_mask = 16'h0057; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~20 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~20_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout & ((\z80_|pla_decode_|Equal33~1_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~15_combout & -// !\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~20 .lut_mask = 16'hAB00; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~20 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~20_combout = (!\z80_|execute_|ctl_alu_oe~3_combout & (!\z80_|execute_|ctl_mRead~14_combout & !\z80_|pla_decode_|Equal49~0_combout )) - - .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), - .datab(\z80_|execute_|ctl_mRead~14_combout ), - .datac(\z80_|pla_decode_|Equal49~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~20 .lut_mask = 16'h0101; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~49 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~49_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((\z80_|execute_|ctl_reg_gp_sel[0]~20_combout ) # (\z80_|sequencer_|DFFE_M1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~20_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~49 .lut_mask = 16'hCCC8; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~22 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~22_combout = (\z80_|execute_|ctl_reg_use_sp~3_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~21_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~6_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~3_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[0]~21_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~22 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~18 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~18_combout = (!\z80_|decode_state_|DFFE_instED~q & (!\z80_|decode_state_|DFFE_instCB~q & ((\z80_|sequencer_|M5~q ) # (\z80_|sequencer_|DFFE_M4_ff~q )))) - - .dataa(\z80_|sequencer_|M5~q ), - .datab(\z80_|decode_state_|DFFE_instED~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|decode_state_|DFFE_instCB~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~18 .lut_mask = 16'h0032; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~23 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~23_combout = ((\z80_|execute_|ctl_reg_gp_sel[1]~17_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~19_combout & \z80_|execute_|ctl_reg_gp_sel[1]~18_combout ))) # (!\z80_|execute_|ctl_reg_gp_sel[0]~22_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~17_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~22_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~23 .lut_mask = 16'h8F0F; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~28 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~28_combout = (\z80_|execute_|ctl_sw_2u~2_combout & !\z80_|execute_|ctl_reg_gp_sel~36_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_sw_2u~2_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_gp_sel~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~28 .lut_mask = 16'h00CC; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~23 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~23_combout = (\z80_|execute_|ctl_sw_1d~4_combout & (((!\z80_|pla_decode_|Equal69~0_combout & \z80_|execute_|ctl_sw_1d~8_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_sw_1d~4_combout ), - .datab(\z80_|pla_decode_|Equal69~0_combout ), - .datac(\z80_|execute_|ctl_sw_1d~8_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~23 .lut_mask = 16'h20AA; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_sel_shift~2_combout = (!\z80_|execute_|ctl_ir_we~8_combout & !\z80_|pla_decode_|Equal20~0_combout ) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal20~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~2 .lut_mask = 16'h0505; -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~14 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_cpl~14_combout = (\z80_|ir_|opcode [4]) # (!\z80_|pla_decode_|Equal63~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|pla_decode_|Equal63~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_cpl~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_cpl~14 .lut_mask = 16'hF0FF; -defparam \z80_|execute_|ctl_flags_hf_cpl~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_cpl~10_combout = (!\z80_|pla_decode_|Equal68~2_combout & (!\z80_|execute_|ctl_state_alu~7_combout & (\z80_|execute_|ctl_flags_hf_cpl~14_combout & !\z80_|execute_|ctl_alu_op_low~13_combout ))) - - .dataa(\z80_|pla_decode_|Equal68~2_combout ), - .datab(\z80_|execute_|ctl_state_alu~7_combout ), - .datac(\z80_|execute_|ctl_flags_hf_cpl~14_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_cpl~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_cpl~10 .lut_mask = 16'h0010; -defparam \z80_|execute_|ctl_flags_hf_cpl~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N22 -cycloneive_lcell_comb \z80_|execute_|setM1~47 ( -// Equation(s): -// \z80_|execute_|setM1~47_combout = (!\z80_|execute_|ctl_ir_we~11_combout & (!\z80_|pla_decode_|Equal69~0_combout & ((!\z80_|pla_decode_|Equal21~0_combout ) # (!\z80_|pla_decode_|Equal63~0_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~11_combout ), - .datab(\z80_|pla_decode_|Equal63~0_combout ), - .datac(\z80_|pla_decode_|Equal21~0_combout ), - .datad(\z80_|pla_decode_|Equal69~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~47 .lut_mask = 16'h0015; -defparam \z80_|execute_|setM1~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|setM1~48 ( -// Equation(s): -// \z80_|execute_|setM1~48_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & (\z80_|execute_|ctl_flags_hf_cpl~10_combout & (\z80_|execute_|setM1~47_combout & \z80_|execute_|nextM~2_combout ))) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), - .datab(\z80_|execute_|ctl_flags_hf_cpl~10_combout ), - .datac(\z80_|execute_|setM1~47_combout ), - .datad(\z80_|execute_|nextM~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~48 .lut_mask = 16'h8000; -defparam \z80_|execute_|setM1~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~13 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~13_combout = (\z80_|ir_|opcode [2]) # ((!\z80_|ir_|opcode [1]) # (!\z80_|execute_|ctl_mWrite~2_combout )) - - .dataa(\z80_|ir_|opcode [2]), - .datab(gnd), - .datac(\z80_|execute_|ctl_mWrite~2_combout ), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~13 .lut_mask = 16'hAFFF; -defparam \z80_|execute_|ctl_al_we~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_flags_oe~0_combout = (!\z80_|execute_|ctl_ir_we~14_combout & (!\z80_|execute_|ctl_mRead~6_combout & (!\z80_|execute_|ctl_ir_we~12_combout & !\z80_|execute_|ctl_iorw~10_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~14_combout ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|execute_|ctl_iorw~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_oe~0 .lut_mask = 16'h0001; -defparam \z80_|execute_|ctl_flags_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~1 ( -// Equation(s): -// \z80_|execute_|ctl_flags_oe~1_combout = (\z80_|execute_|ctl_al_we~13_combout & (\z80_|execute_|ctl_flags_bus~5_combout & (!\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_flags_oe~0_combout ))) - - .dataa(\z80_|execute_|ctl_al_we~13_combout ), - .datab(\z80_|execute_|ctl_flags_bus~5_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|ctl_flags_oe~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_oe~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_oe~1 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_flags_oe~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~13 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~13_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & ((!\z80_|execute_|ctl_flags_oe~1_combout ) # (!\z80_|execute_|setM1~48_combout )))) - - .dataa(\z80_|execute_|setM1~48_combout ), - .datab(\z80_|execute_|ctl_flags_oe~1_combout ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~13 .lut_mask = 16'h0070; -defparam \z80_|execute_|ctl_reg_in_hi~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~29 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~29_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~28_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~27_combout & !\z80_|execute_|ctl_reg_in_hi~13_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~28_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~27_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~29 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~40 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~40_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ctl_state_alu~4_combout & ((!\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ctl_state_alu~6_combout )))) # (!\z80_|pla_decode_|Equal47~0_combout & -// (((!\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|execute_|ctl_state_alu~6_combout ), - .datac(\z80_|pla_decode_|Equal34~0_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~40 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_inc_cy~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~2 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~2_combout = (\z80_|execute_|ctl_inc_cy~40_combout & (((!\z80_|pla_decode_|Equal19~0_combout & !\z80_|pla_decode_|Equal9~1_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~40_combout ), - .datab(\z80_|pla_decode_|Equal19~0_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~2 .lut_mask = 16'h0A2A; -defparam \z80_|execute_|ctl_inc_dec~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~12 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~12_combout = (\z80_|execute_|ctl_inc_dec~2_combout & (((!\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|pla_decode_|Equal9~1_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|execute_|ctl_inc_dec~2_combout ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~12 .lut_mask = 16'h4CCC; -defparam \z80_|execute_|ctl_inc_dec~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~43 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~43_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ctl_mRead~11_combout & ((!\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ixy_d~9_combout )))) # (!\z80_|pla_decode_|Equal47~0_combout & -// (((!\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|execute_|ixy_d~9_combout ))) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|pla_decode_|Equal34~0_combout ), - .datad(\z80_|execute_|ctl_mRead~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~43 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_inc_cy~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~5 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~5_combout = (\z80_|execute_|ctl_inc_dec~12_combout & (\z80_|execute_|ctl_inc_cy~43_combout & ((!\z80_|execute_|ixy_d~9_combout ) # (!\z80_|pla_decode_|Equal19~0_combout )))) - - .dataa(\z80_|execute_|ctl_inc_dec~12_combout ), - .datab(\z80_|pla_decode_|Equal19~0_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|execute_|ctl_inc_cy~43_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~5 .lut_mask = 16'h2A00; -defparam \z80_|execute_|ctl_inc_dec~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~4_combout = (\z80_|execute_|ctl_inc_dec~5_combout & (((!\z80_|execute_|ctl_mRead~11_combout & !\z80_|execute_|ctl_state_alu~4_combout )) # (!\z80_|execute_|ctl_mWrite~4_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~11_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_inc_dec~5_combout ), - .datad(\z80_|execute_|ctl_mWrite~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~4 .lut_mask = 16'h10F0; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|fMRead~6 ( -// Equation(s): -// \z80_|execute_|fMRead~6_combout = (\z80_|pla_decode_|Equal29~0_combout & (!\z80_|execute_|ctl_state_alu~5_combout & (!\z80_|execute_|ixy_d~7_combout ))) # (!\z80_|pla_decode_|Equal29~0_combout & (((!\z80_|execute_|ctl_state_alu~5_combout & -// !\z80_|execute_|ixy_d~7_combout )) # (!\z80_|pla_decode_|Equal9~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal29~0_combout ), - .datab(\z80_|execute_|ctl_state_alu~5_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~6 .lut_mask = 16'h0357; -defparam \z80_|execute_|fMRead~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|fMRead~7 ( -// Equation(s): -// \z80_|execute_|fMRead~7_combout = (\z80_|execute_|ctl_state_alu~5_combout & (((!\z80_|pla_decode_|Equal37~0_combout & !\z80_|execute_|ctl_mRead~16_combout )))) # (!\z80_|execute_|ctl_state_alu~5_combout & (((!\z80_|pla_decode_|Equal37~0_combout & -// !\z80_|execute_|ctl_mRead~16_combout )) # (!\z80_|execute_|ixy_d~7_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~5_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|pla_decode_|Equal37~0_combout ), - .datad(\z80_|execute_|ctl_mRead~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~7 .lut_mask = 16'h111F; -defparam \z80_|execute_|fMRead~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N26 -cycloneive_lcell_comb \z80_|execute_|fMRead~8 ( -// Equation(s): -// \z80_|execute_|fMRead~8_combout = (\z80_|execute_|fMRead~7_combout & (((!\z80_|execute_|ctl_state_alu~5_combout & !\z80_|execute_|ixy_d~7_combout )) # (!\z80_|pla_decode_|Equal38~2_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~5_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|execute_|fMRead~7_combout ), - .datad(\z80_|pla_decode_|Equal38~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~8 .lut_mask = 16'h10F0; -defparam \z80_|execute_|fMRead~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~26 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~26_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~4_combout & (\z80_|execute_|ctl_reg_gp_we~1_combout & (\z80_|execute_|fMRead~6_combout & \z80_|execute_|fMRead~8_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~1_combout ), - .datac(\z80_|execute_|fMRead~6_combout ), - .datad(\z80_|execute_|fMRead~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~26 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~13 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~13_combout = (\z80_|execute_|ctl_state_alu~8_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|pla_decode_|Equal52~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal52~1_combout ), - .datab(\z80_|execute_|ctl_state_alu~8_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~13 .lut_mask = 16'hC4CC; -defparam \z80_|execute_|ctl_state_alu~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~10 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~10_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~10 .lut_mask = 16'h3331; -defparam \z80_|execute_|ctl_state_alu~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~11 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~11_combout = (\z80_|execute_|ctl_state_alu~5_combout & ((\z80_|pla_decode_|Equal52~1_combout ) # ((\z80_|execute_|ctl_state_alu~10_combout & \z80_|execute_|ctl_state_alu~7_combout )))) # -// (!\z80_|execute_|ctl_state_alu~5_combout & (((\z80_|execute_|ctl_state_alu~10_combout & \z80_|execute_|ctl_state_alu~7_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~5_combout ), - .datab(\z80_|pla_decode_|Equal52~1_combout ), - .datac(\z80_|execute_|ctl_state_alu~10_combout ), - .datad(\z80_|execute_|ctl_state_alu~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~11 .lut_mask = 16'hF888; -defparam \z80_|execute_|ctl_state_alu~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~9 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~9_combout = (\z80_|execute_|ctl_state_alu~14_combout & (((\z80_|nM1_int~2_combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) # (!\z80_|execute_|ctl_state_alu~14_combout & (\z80_|pla_decode_|Equal52~1_combout & -// ((\z80_|nM1_int~2_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~14_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal52~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~9 .lut_mask = 16'hF3A2; -defparam \z80_|execute_|ctl_state_alu~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N14 -cycloneive_lcell_comb \z80_|pla_decode_|Equal62~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal62~2_combout = (\z80_|ir_|opcode [5] & (((\z80_|execute_|ctl_state_alu~11_combout ) # (\z80_|execute_|ctl_state_alu~9_combout )) # (!\z80_|execute_|ctl_state_alu~13_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~13_combout ), - .datab(\z80_|execute_|ctl_state_alu~11_combout ), - .datac(\z80_|execute_|ctl_state_alu~9_combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal62~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal62~2 .lut_mask = 16'hFD00; -defparam \z80_|pla_decode_|Equal62~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~4_combout = (((\z80_|ir_|opcode [3] & \z80_|ir_|opcode [4])) # (!\z80_|nM1_int~2_combout )) # (!\z80_|pla_decode_|Equal62~2_combout ) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|pla_decode_|Equal62~2_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~4 .lut_mask = 16'h8FFF; -defparam \z80_|execute_|ctl_flags_pf_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~21 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~21_combout = ((!\z80_|execute_|ctl_mRead~4_combout & ((!\z80_|pla_decode_|Equal63~0_combout ) # (!\z80_|pla_decode_|Equal32~0_combout )))) # (!\z80_|nM1_int~2_combout ) - - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_mRead~4_combout ), - .datad(\z80_|pla_decode_|Equal63~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~21 .lut_mask = 16'h373F; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal64~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal64~0_combout = (!\z80_|ir_|opcode [5] & (((\z80_|execute_|ctl_state_alu~11_combout ) # (\z80_|execute_|ctl_state_alu~9_combout )) # (!\z80_|execute_|ctl_state_alu~13_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~13_combout ), - .datab(\z80_|execute_|ctl_state_alu~11_combout ), - .datac(\z80_|execute_|ctl_state_alu~9_combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal64~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal64~0 .lut_mask = 16'h00FD; -defparam \z80_|pla_decode_|Equal64~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel[0]~3 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel[0]~3_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # ((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|pla_decode_|Equal64~0_combout )) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal64~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel[0]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel[0]~3 .lut_mask = 16'hEEFF; -defparam \z80_|execute_|ctl_pf_sel[0]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~22 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~22_combout = (\z80_|execute_|ctl_flags_pf_we~4_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout & (\z80_|execute_|ctl_alu_oe~7_combout & \z80_|execute_|ctl_pf_sel[0]~3_combout ))) - - .dataa(\z80_|execute_|ctl_flags_pf_we~4_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ), - .datac(\z80_|execute_|ctl_alu_oe~7_combout ), - .datad(\z80_|execute_|ctl_pf_sel[0]~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~22 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~15 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~15_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|execute_|ctl_state_alu~14_combout & !\z80_|pla_decode_|Equal52~1_combout ))) # (!\z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(\z80_|execute_|ctl_state_alu~14_combout ), - .datab(\z80_|pla_decode_|Equal52~1_combout ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~15 .lut_mask = 16'hFF1F; -defparam \z80_|execute_|ctl_state_alu~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout = (\z80_|ir_|opcode [4] & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal63~0_combout ))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal63~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~25 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~25_combout = (\z80_|execute_|ctl_state_alu~15_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~24_combout & !\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout )) - - .dataa(\z80_|execute_|ctl_state_alu~15_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~25 .lut_mask = 16'h00A0; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~30 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~30_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~29_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~26_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout & \z80_|execute_|ctl_reg_gp_sel[0]~25_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~29_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~30 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~31 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~31_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~14_combout ) # (((\z80_|execute_|ctl_reg_gp_sel[1]~23_combout & \z80_|ir_|opcode [5])) # (!\z80_|execute_|ctl_reg_gp_sel[0]~30_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~14_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~31 .lut_mask = 16'hEFAF; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~33 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~33_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|pla_decode_|Equal11~0_combout ) # ((\z80_|execute_|ctl_mRead~5_combout )))) # (!\z80_|execute_|ixy_d~7_combout & (\z80_|pla_decode_|Equal11~0_combout & -// ((\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ctl_mRead~5_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~33 .lut_mask = 16'hECA8; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~34 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~34_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ) # ((\z80_|ir_|opcode [1] & ((!\z80_|execute_|ctl_sw_2u~5_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), - .datab(\z80_|execute_|ctl_sw_2u~5_combout ), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~34 .lut_mask = 16'hFF70; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo~20 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo~20_combout = ((\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal55~0_combout )) # (!\z80_|pla_decode_|Equal6~0_combout ) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo~20 .lut_mask = 16'hF7F7; -defparam \z80_|execute_|ctl_reg_sys_hilo~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~32 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~32_combout = (\z80_|ir_|opcode [4] & (((\z80_|execute_|ctl_state_alu~5_combout & !\z80_|execute_|ctl_reg_sys_hilo~20_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~22_combout ))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|execute_|ctl_reg_gp_sel[0]~22_combout ), - .datac(\z80_|execute_|ctl_state_alu~5_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~32 .lut_mask = 16'h22A2; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~35 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~35_combout = ((\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ) # (\z80_|execute_|ctl_reg_gp_sel[0]~32_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~35 .lut_mask = 16'hFFF3; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N18 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~5 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_de2~5_combout = (!\z80_|decode_state_|DFFE_instIY1~q & (!\z80_|decode_state_|DFFE_inst4~q & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|decode_state_|DFFE_instIY1~q ), .datab(\z80_|decode_state_|DFFE_inst4~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_de2~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_de2~5 .lut_mask = 16'h0010; -defparam \z80_|reg_control_|reg_sel_de2~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N24 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~6 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_de2~6_combout = (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & ((\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[0]~30_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_de2~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_de2~6 .lut_mask = 16'h0F0B; -defparam \z80_|reg_control_|reg_sel_de2~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N0 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_hl~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_hl~0_combout = (!\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de1~q & ((\z80_|reg_control_|reg_sel_de2~6_combout ))) # (!\z80_|reg_control_|bank_hl_de1~q & (\z80_|reg_control_|reg_sel_de2~5_combout )))) - - .dataa(\z80_|reg_control_|bank_hl_de1~q ), - .datab(\z80_|reg_control_|reg_sel_de2~5_combout ), - .datac(\z80_|reg_control_|reg_sel_de2~6_combout ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_hl~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_hl~0 .lut_mask = 16'h00E4; -defparam \z80_|reg_control_|reg_sel_hl~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N14 -cycloneive_lcell_comb \z80_|reg_control_|bank_hl_de2~0 ( -// Equation(s): -// \z80_|reg_control_|bank_hl_de2~0_combout = \z80_|reg_control_|bank_hl_de2~q $ (((\z80_|pla_decode_|Equal2~2_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|reg_control_|bank_exx~q )))) - - .dataa(\z80_|pla_decode_|Equal2~2_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|reg_control_|bank_hl_de2~q ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_control_|bank_hl_de2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|bank_hl_de2~0 .lut_mask = 16'hD2F0; -defparam \z80_|reg_control_|bank_hl_de2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y15_N15 -dffeas \z80_|reg_control_|bank_hl_de2 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_control_|bank_hl_de2~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_control_|bank_hl_de2~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_control_|bank_hl_de2 .is_wysiwyg = "true"; -defparam \z80_|reg_control_|bank_hl_de2 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N30 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_hl2~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_hl2~0_combout = (\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de2~q & (\z80_|reg_control_|reg_sel_de2~6_combout )) # (!\z80_|reg_control_|bank_hl_de2~q & ((\z80_|reg_control_|reg_sel_de2~5_combout ))))) - - .dataa(\z80_|reg_control_|reg_sel_de2~6_combout ), - .datab(\z80_|reg_control_|reg_sel_de2~5_combout ), - .datac(\z80_|reg_control_|bank_hl_de2~q ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_hl2~0 .lut_mask = 16'hAC00; -defparam \z80_|reg_control_|reg_sel_hl2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~7_combout = (\z80_|nM1_int~2_combout & (((\z80_|pla_decode_|Equal69~0_combout ) # (!\z80_|execute_|ctl_sw_1d~8_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~20_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~20_combout ), - .datab(\z80_|pla_decode_|Equal69~0_combout ), - .datac(\z80_|execute_|ctl_sw_1d~8_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~7 .lut_mask = 16'hDF00; -defparam \z80_|execute_|ctl_reg_in_hi~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~4_combout = (!\z80_|execute_|ctl_reg_in_hi~7_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout & \z80_|execute_|ctl_state_alu~15_combout )) - - .dataa(\z80_|execute_|ctl_reg_in_hi~7_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), .datac(gnd), - .datad(\z80_|execute_|ctl_state_alu~15_combout ), + .datad(\z80_|decode_state_|DFFE_instIY1~q ), .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~4_combout ), + .combout(\z80_|decode_state_|use_ixiy~combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~4 .lut_mask = 16'h1100; -defparam \z80_|execute_|ctl_reg_gp_we~4 .sum_lutc_input = "datac"; +defparam \z80_|decode_state_|use_ixiy .lut_mask = 16'hFFCC; +defparam \z80_|decode_state_|use_ixiy .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 ( +// Location: LCCOMB_X28_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ixy_d~4 ( // Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M4_ff~q & (\z80_|pla_decode_|Equal25~0_combout & !\z80_|pla_decode_|Equal12~1_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|pla_decode_|Equal25~0_combout ), - .datad(\z80_|pla_decode_|Equal12~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~3_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~6_combout & (!\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout & ((!\z80_|execute_|ctl_iorw~10_combout ) # (!\z80_|nM1_int~2_combout )))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), - .datac(\z80_|execute_|ctl_iorw~10_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~3 .lut_mask = 16'h004C; -defparam \z80_|execute_|ctl_reg_gp_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~13 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~13_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout & ((!\z80_|pla_decode_|Equal21~1_combout ) # (!\z80_|execute_|ctl_mRead~11_combout -// )))) - - .dataa(\z80_|execute_|ctl_mRead~11_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~13 .lut_mask = 16'h0013; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5~combout = (\z80_|execute_|ctl_reg_in_hi~2_combout & (\z80_|pla_decode_|Equal25~0_combout & ((\z80_|ir_|opcode [3]) # (!\z80_|pla_decode_|Equal12~0_combout )))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datab(\z80_|pla_decode_|Equal12~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal25~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5 .lut_mask = 16'hA200; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~2_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~13_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5~combout & !\z80_|execute_|ctl_sw_1d~9_combout ))) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5~combout ), - .datad(\z80_|execute_|ctl_sw_1d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~2 .lut_mask = 16'h0008; -defparam \z80_|execute_|ctl_reg_gp_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~5_combout = (!\z80_|execute_|ctl_reg_in_hi~13_combout & (\z80_|execute_|ctl_reg_gp_we~4_combout & (\z80_|execute_|ctl_reg_gp_we~3_combout & \z80_|execute_|ctl_reg_gp_we~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~13_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~4_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~3_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~5 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_gp_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~6_combout = (((\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout )) # (!\z80_|execute_|ctl_sw_4u~3_combout )) # (!\z80_|execute_|ctl_reg_gp_we~5_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_we~5_combout ), - .datab(\z80_|execute_|ctl_sw_4u~3_combout ), - .datac(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~6 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|ctl_reg_gp_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~14 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~14_combout = (!\z80_|execute_|ctl_mRead~7_combout & (((\z80_|ir_|opcode [2]) # (!\z80_|execute_|ctl_mWrite~2_combout )) # (!\z80_|ir_|opcode [1]))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|execute_|ctl_mRead~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~14 .lut_mask = 16'h00F7; -defparam \z80_|execute_|ctl_al_we~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~50 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~50_combout = (!\z80_|execute_|ctl_flags_oe~1_combout & (((!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|execute_|ctl_flags_oe~1_combout ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~50 .lut_mask = 16'h1033; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~26 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~26_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ) # ((\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mWrite~4_combout ) # (!\z80_|execute_|ctl_al_we~14_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~4_combout ), - .datab(\z80_|execute_|ctl_al_we~14_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~26 .lut_mask = 16'hFBF0; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~27 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~27_combout = (\z80_|execute_|rsel3~combout & (((!\z80_|execute_|ctl_reg_gp_sel[0]~20_combout & \z80_|nM1_int~2_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~20_combout ), - .datab(\z80_|execute_|rsel3~combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~27 .lut_mask = 16'h40CC; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~28 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~28_combout = (((\z80_|execute_|ctl_ir_we~7_combout ) # (\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo~20_combout ) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), - .datac(\z80_|execute_|ctl_ir_we~7_combout ), - .datad(\z80_|execute_|ctl_ir_we~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~28 .lut_mask = 16'hFFF7; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~29 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~29_combout = (\z80_|execute_|ctl_state_alu~5_combout & ((\z80_|execute_|ctl_iorw~11_combout ) # ((\z80_|execute_|ctl_state_alu~14_combout ) # (\z80_|execute_|ctl_reg_gp_hilo[0]~28_combout )))) - - .dataa(\z80_|execute_|ctl_iorw~11_combout ), - .datab(\z80_|execute_|ctl_state_alu~5_combout ), - .datac(\z80_|execute_|ctl_state_alu~14_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~29 .lut_mask = 16'hCCC8; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal9~1_combout & \z80_|sequencer_|M5~q )) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|pla_decode_|Equal9~1_combout ), - .datac(gnd), - .datad(\z80_|sequencer_|M5~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 .lut_mask = 16'h4400; -defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~31 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~31_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout & (((!\z80_|execute_|ctl_mRead~8_combout & !\z80_|execute_|ctl_mRead~10_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~8_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), - .datad(\z80_|execute_|ctl_mRead~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~31 .lut_mask = 16'h0307; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~51 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~51_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # ((\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T2_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|execute_|nextM~2_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~51 .lut_mask = 16'h0F08; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~30 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~30_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ) # (((\z80_|pla_decode_|Equal6~1_combout & \z80_|execute_|ixy_d~7_combout )) # (!\z80_|execute_|ctl_mRead~25_combout )) - - .dataa(\z80_|pla_decode_|Equal6~1_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_mRead~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~30 .lut_mask = 16'hECFF; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~32 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~32_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ) # ((\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ) # -// (!\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~32 .lut_mask = 16'hFFEF; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~34 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~34_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ) # (((\z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ) # (\z80_|execute_|ctl_reg_gp_hilo[0]~32_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~34 .lut_mask = 16'hFFFB; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~24 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout = ((\z80_|execute_|ctl_reg_gp_sel~36_combout ) # (!\z80_|execute_|ctl_sw_2u~5_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_sel~36_combout ), - .datad(\z80_|execute_|ctl_sw_2u~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~24 .lut_mask = 16'hF5FF; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~25 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~25_combout = (\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|execute_|rsel0~combout & ((\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout )))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & -// (((\z80_|execute_|rsel0~combout & \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout )) # (!\z80_|execute_|setM1~48_combout ))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|execute_|rsel0~combout ), - .datac(\z80_|execute_|setM1~48_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~25 .lut_mask = 16'hCD05; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~36 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~36_combout = (\z80_|pla_decode_|Equal11~0_combout & (!\z80_|execute_|ixy_d~6_combout & (!\z80_|execute_|ixy_d~9_combout ))) # (!\z80_|pla_decode_|Equal11~0_combout & (((!\z80_|pla_decode_|Equal10~0_combout )) # -// (!\z80_|execute_|ixy_d~6_combout ))) - - .dataa(\z80_|pla_decode_|Equal11~0_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|pla_decode_|Equal10~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~36 .lut_mask = 16'h1357; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout = (!\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal2~1_combout & (\z80_|execute_|ctl_eval_cond~0_combout & !\z80_|ir_|opcode [1]))) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|pla_decode_|Equal2~1_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 .lut_mask = 16'h0040; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N4 -cycloneive_lcell_comb \z80_|execute_|setM1~40 ( -// Equation(s): -// \z80_|execute_|setM1~40_combout = (!\z80_|pla_decode_|Equal4~0_combout & ((!\z80_|pla_decode_|Equal8~0_combout ) # (!\z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal4~0_combout ), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal8~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~40 .lut_mask = 16'h1155; -defparam \z80_|execute_|setM1~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~18 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout & (!\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout & ((\z80_|execute_|setM1~40_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|setM1~40_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~18 .lut_mask = 16'h1101; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~37 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~37_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout & \z80_|execute_|ctl_reg_gp_sel[1]~26_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~37 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~38 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ) # ((!\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~38 .lut_mask = 16'hEFFF; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~93 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~93_combout = (!\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & ((\z80_|reg_control_|reg_sel_hl~0_combout ) # (\z80_|reg_control_|reg_sel_hl2~0_combout )))) - - .dataa(\z80_|reg_control_|reg_sel_hl~0_combout ), - .datab(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~93_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~93 .lut_mask = 16'h0E00; -defparam \z80_|reg_file_|gdfx_temp0[0]~93 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N28 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_de~0_combout = (!\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de1~q & (\z80_|reg_control_|reg_sel_de2~5_combout )) # (!\z80_|reg_control_|bank_hl_de1~q & ((\z80_|reg_control_|reg_sel_de2~6_combout ))))) - - .dataa(\z80_|reg_control_|bank_hl_de1~q ), - .datab(\z80_|reg_control_|reg_sel_de2~5_combout ), - .datac(\z80_|reg_control_|reg_sel_de2~6_combout ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_de~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_de~0 .lut_mask = 16'h00D8; -defparam \z80_|reg_control_|reg_sel_de~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N0 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_50 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_50~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_de~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_de~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_50 .lut_mask = 16'h0C00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N0 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout = (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 .lut_mask = 16'h0F00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N18 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout = (\z80_|decode_state_|DFFE_inst4~q & (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 .lut_mask = 16'h0080; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N30 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|reg_control_|bank_exx~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 .lut_mask = 16'h0400; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N12 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|reg_control_|bank_exx~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 .lut_mask = 16'h0100; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~9_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|execute_|ctl_mRead~4_combout )))) # (!\z80_|pla_decode_|Equal47~0_combout -// & (((!\z80_|execute_|ixy_d~7_combout )) # (!\z80_|execute_|ctl_mRead~4_combout ))) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|execute_|ctl_mRead~4_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~9 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_reg_in_hi~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~10 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~10_combout = (\z80_|execute_|ctl_reg_in_hi~9_combout & (\z80_|execute_|ctl_reg_in_hi~8_combout & \z80_|execute_|ctl_reg_gp_we~5_combout )) - - .dataa(\z80_|execute_|ctl_reg_in_hi~9_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~8_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_gp_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~10 .lut_mask = 16'h8800; -defparam \z80_|execute_|ctl_reg_in_hi~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~19 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~19_combout = (\z80_|execute_|ctl_mRead~22_combout & (\z80_|reg_control_|reg_sys_we_lo~6_combout & ((!\z80_|execute_|ixy_d~15_combout ) # (!\z80_|sequencer_|DFFE_T3_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|execute_|ctl_mRead~22_combout ), - .datac(\z80_|reg_control_|reg_sys_we_lo~6_combout ), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~19 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_reg_sel_wz~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout = (\z80_|pla_decode_|Equal24~0_combout & (\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|ir_|opcode [3] & \z80_|ir_|opcode [4]))) - - .dataa(\z80_|pla_decode_|Equal24~0_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_lo~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_lo~8_combout = (((\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ) # (!\z80_|execute_|ctl_reg_sel_wz~19_combout )) # (!\z80_|execute_|ctl_reg_in_hi~10_combout )) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ) - - .dataa(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~10_combout ), - .datac(\z80_|execute_|ctl_reg_sel_wz~19_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_lo~8 .lut_mask = 16'hFF7F; -defparam \z80_|execute_|ctl_reg_in_lo~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y12_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~19 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~19_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ) # ((\z80_|execute_|ctl_sw_4u~6_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ) # (\z80_|execute_|ctl_reg_in_lo~8_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|execute_|ctl_sw_4u~6_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .datad(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~19 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp0[0]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~4_combout = (\z80_|pla_decode_|Equal6~1_combout & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_M1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|pla_decode_|Equal6~1_combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~4 .lut_mask = 16'h00B0; -defparam \z80_|execute_|ctl_reg_use_sp~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~5_combout = (\z80_|execute_|ctl_reg_use_sp~4_combout ) # ((\z80_|execute_|ctl_mRead~17_combout & ((\z80_|execute_|ctl_reg_in_hi~2_combout ) # (\z80_|execute_|ctl_state_alu~6_combout )))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datab(\z80_|execute_|ctl_reg_use_sp~4_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_mRead~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~5 .lut_mask = 16'hFECC; -defparam \z80_|execute_|ctl_reg_use_sp~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~6_combout = (\z80_|execute_|ctl_reg_use_sp~5_combout ) # ((!\z80_|execute_|ctl_reg_use_sp~3_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[1]~26_combout )) - - .dataa(\z80_|execute_|ctl_reg_use_sp~5_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), - .datad(\z80_|execute_|ctl_reg_use_sp~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~6 .lut_mask = 16'hAFFF; -defparam \z80_|execute_|ctl_reg_use_sp~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N2 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout = (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal21~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal21~2_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal40~0_combout & !\z80_|ir_|opcode [5])) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal40~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal21~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal21~2 .lut_mask = 16'h0808; -defparam \z80_|pla_decode_|Equal21~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N20 -cycloneive_lcell_comb \z80_|reg_control_|bank_af~0 ( -// Equation(s): -// \z80_|reg_control_|bank_af~0_combout = \z80_|reg_control_|bank_af~q $ (((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|pla_decode_|Equal21~2_combout & \z80_|pla_decode_|Equal32~0_combout )))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|pla_decode_|Equal21~2_combout ), - .datac(\z80_|reg_control_|bank_af~q ), - .datad(\z80_|pla_decode_|Equal32~0_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|bank_af~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|bank_af~0 .lut_mask = 16'hB4F0; -defparam \z80_|reg_control_|bank_af~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y12_N21 -dffeas \z80_|reg_control_|bank_af ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_control_|bank_af~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_control_|bank_af~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_control_|bank_af .is_wysiwyg = "true"; -defparam \z80_|reg_control_|bank_af .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N28 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_af~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_af~0_combout = (!\z80_|execute_|ctl_reg_use_sp~6_combout & (!\z80_|reg_control_|bank_af~q & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datab(\z80_|reg_control_|bank_af~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_af~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_af~0 .lut_mask = 16'h1000; -defparam \z80_|reg_control_|reg_sel_af~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N4 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_34 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_34~combout = (\z80_|reg_control_|reg_sel_af~0_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & !\z80_|execute_|ctl_reg_gp_we~6_combout )) - - .dataa(\z80_|reg_control_|reg_sel_af~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_34 .lut_mask = 16'h0088; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N10 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_af2~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_af2~0_combout = (!\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|reg_control_|bank_af~q & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datab(\z80_|reg_control_|bank_af~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_af2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_af2~0 .lut_mask = 16'h4000; -defparam \z80_|reg_control_|reg_sel_af2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N18 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_30 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_30~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_af2~0_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datac(gnd), - .datad(\z80_|reg_control_|reg_sel_af2~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_30 .lut_mask = 16'h2200; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~12 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~12_combout = (\z80_|execute_|ixy_d~6_combout & (!\z80_|pla_decode_|Equal19~0_combout & ((!\z80_|pla_decode_|Equal9~1_combout )))) # (!\z80_|execute_|ixy_d~6_combout & (((!\z80_|pla_decode_|Equal9~1_combout ) # -// (!\z80_|execute_|ctl_reg_in_hi~2_combout )))) - - .dataa(\z80_|pla_decode_|Equal19~0_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~12 .lut_mask = 16'h035F; -defparam \z80_|execute_|ctl_reg_sel_wz~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~4_combout = (\z80_|ir_|opcode [5]) # ((!\z80_|pla_decode_|Equal13~1_combout ) # (!\z80_|pla_decode_|Equal13~0_combout )) - - .dataa(\z80_|ir_|opcode [5]), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|pla_decode_|Equal13~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~4 .lut_mask = 16'hAFFF; -defparam \z80_|execute_|ctl_flags_bus~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~6_combout = (\z80_|pla_decode_|Equal44~0_combout ) # ((\z80_|pla_decode_|Equal52~0_combout & \z80_|pla_decode_|Equal33~0_combout )) - - .dataa(\z80_|pla_decode_|Equal52~0_combout ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|pla_decode_|Equal44~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~6 .lut_mask = 16'hF8F8; -defparam \z80_|execute_|ctl_flags_bus~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~7_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (((\z80_|execute_|ctl_flags_bus~6_combout ) # (!\z80_|execute_|ctl_flags_bus~5_combout )) # (!\z80_|execute_|ctl_flags_bus~4_combout ))) - - .dataa(\z80_|execute_|ctl_flags_bus~4_combout ), - .datab(\z80_|execute_|ctl_flags_bus~5_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_flags_bus~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~7 .lut_mask = 16'hF070; -defparam \z80_|execute_|ctl_flags_bus~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N22 -cycloneive_lcell_comb \z80_|execute_|fMRead~24 ( -// Equation(s): -// \z80_|execute_|fMRead~24_combout = (\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_state_alu~4_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_state_alu~14_combout )))) # -// (!\z80_|execute_|ctl_ir_we~12_combout & (((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_state_alu~14_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~12_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_state_alu~14_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~24 .lut_mask = 16'h0777; -defparam \z80_|execute_|fMRead~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~13 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~13_combout = (\z80_|execute_|ctl_alu_shift_oe~20_combout & (\z80_|execute_|ctl_bus_db_oe~3_combout & \z80_|execute_|ctl_flags_bus~12_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_shift_oe~20_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~3_combout ), - .datad(\z80_|execute_|ctl_flags_bus~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~13 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_flags_bus~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~combout = (\z80_|execute_|ctl_flags_bus~7_combout ) # (((\z80_|execute_|ctl_flags_hf2_we~combout ) # (!\z80_|execute_|ctl_flags_bus~13_combout )) # (!\z80_|execute_|fMRead~24_combout )) - - .dataa(\z80_|execute_|ctl_flags_bus~7_combout ), - .datab(\z80_|execute_|fMRead~24_combout ), - .datac(\z80_|execute_|ctl_flags_hf2_we~combout ), - .datad(\z80_|execute_|ctl_flags_bus~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus .lut_mask = 16'hFBFF; -defparam \z80_|execute_|ctl_flags_bus .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~3 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~3_combout = ((!\z80_|pla_decode_|Equal11~0_combout & ((!\z80_|execute_|ctl_mWrite~2_combout ) # (!\z80_|pla_decode_|Equal55~0_combout )))) # (!\z80_|execute_|ctl_mWrite~7_combout ) - - .dataa(\z80_|pla_decode_|Equal11~0_combout ), - .datab(\z80_|execute_|ctl_mWrite~7_combout ), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|execute_|ctl_mWrite~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~3 .lut_mask = 16'h3777; -defparam \z80_|execute_|ctl_inc_dec~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~14 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~14_combout = (\z80_|execute_|ctl_inc_dec~3_combout & (!\z80_|nM1_int~2_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout & \z80_|execute_|fMRead~3_combout ))) - - .dataa(\z80_|execute_|ctl_inc_dec~3_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), - .datad(\z80_|execute_|fMRead~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~14 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~2_combout = ((!\z80_|execute_|ctl_mRead~15_combout & ((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout )))) # (!\z80_|execute_|ixy_d~5_combout ) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|ctl_mRead~15_combout ), - .datac(\z80_|pla_decode_|Equal25~0_combout ), - .datad(\z80_|pla_decode_|Equal12~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~2 .lut_mask = 16'h7757; -defparam \z80_|execute_|ctl_reg_sel_pc~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~3_combout = (\z80_|execute_|ctl_reg_sel_pc~2_combout & (((!\z80_|execute_|ctl_mRead~10_combout & !\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~2_combout ), - .datac(\z80_|pla_decode_|Equal19~0_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~3 .lut_mask = 16'h04CC; -defparam \z80_|execute_|ctl_reg_sel_pc~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~6_combout = (\z80_|pla_decode_|Equal34~0_combout & (!\z80_|execute_|ixy_d~5_combout & ((!\z80_|execute_|ctl_alu_op_low~8_combout ) # (!\z80_|execute_|ixy_d~16_combout )))) # (!\z80_|pla_decode_|Equal34~0_combout & -// (((!\z80_|execute_|ctl_alu_op_low~8_combout )) # (!\z80_|execute_|ixy_d~16_combout ))) - - .dataa(\z80_|pla_decode_|Equal34~0_combout ), - .datab(\z80_|execute_|ixy_d~16_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~6 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_reg_sel_pc~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~5_combout = ((!\z80_|execute_|ctl_mRead~8_combout & (!\z80_|execute_|ctl_mRead~17_combout & !\z80_|execute_|ctl_mRead~9_combout ))) # (!\z80_|execute_|ixy_d~5_combout ) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|ctl_mRead~8_combout ), - .datac(\z80_|execute_|ctl_mRead~17_combout ), - .datad(\z80_|execute_|ctl_mRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~5 .lut_mask = 16'h5557; -defparam \z80_|execute_|ctl_reg_sel_pc~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~4_combout = ((!\z80_|execute_|ixy_d~10_combout & ((!\z80_|pla_decode_|Equal21~0_combout ) # (!\z80_|pla_decode_|Equal24~0_combout )))) # (!\z80_|execute_|ctl_alu_op_low~8_combout ) - - .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datab(\z80_|pla_decode_|Equal24~0_combout ), - .datac(\z80_|pla_decode_|Equal21~0_combout ), - .datad(\z80_|execute_|ixy_d~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~4 .lut_mask = 16'h557F; -defparam \z80_|execute_|ctl_reg_sel_pc~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~7_combout = (\z80_|execute_|ctl_reg_sel_pc~3_combout & (\z80_|execute_|ctl_reg_sel_pc~6_combout & (\z80_|execute_|ctl_reg_sel_pc~5_combout & \z80_|execute_|ctl_reg_sel_pc~4_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~3_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~6_combout ), - .datac(\z80_|execute_|ctl_reg_sel_pc~5_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~7 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sel_pc~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~8_combout = (\z80_|pla_decode_|Equal3~0_combout & ((\z80_|pla_decode_|Equal24~0_combout ) # ((\z80_|pla_decode_|Equal25~0_combout & !\z80_|pla_decode_|Equal12~1_combout )))) # (!\z80_|pla_decode_|Equal3~0_combout & -// (((\z80_|pla_decode_|Equal25~0_combout & !\z80_|pla_decode_|Equal12~1_combout )))) - - .dataa(\z80_|pla_decode_|Equal3~0_combout ), - .datab(\z80_|pla_decode_|Equal24~0_combout ), - .datac(\z80_|pla_decode_|Equal25~0_combout ), - .datad(\z80_|pla_decode_|Equal12~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~8 .lut_mask = 16'h88F8; -defparam \z80_|execute_|ctl_reg_sel_pc~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~9_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & ((\z80_|pla_decode_|Equal34~0_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~8_combout ) # (\z80_|execute_|ctl_mRead~17_combout )))) - - .dataa(\z80_|pla_decode_|Equal34~0_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~8_combout ), - .datac(\z80_|execute_|ctl_mRead~17_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~9 .lut_mask = 16'hFE00; -defparam \z80_|execute_|ctl_reg_sel_pc~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~10 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~10_combout = (\z80_|execute_|ctl_reg_sel_pc~7_combout & (!\z80_|execute_|ctl_reg_sel_pc~9_combout & ((!\z80_|pla_decode_|Equal41~2_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~7_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~9_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|pla_decode_|Equal41~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~10 .lut_mask = 16'h0222; -defparam \z80_|execute_|ctl_reg_sel_pc~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~13 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~13_combout = (\z80_|execute_|ctl_reg_sel_pc~10_combout & (\z80_|execute_|ctl_inc_cy~94_combout & (\z80_|execute_|ctl_inc_cy~87_combout & \z80_|execute_|ctl_inc_cy~42_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~10_combout ), - .datab(\z80_|execute_|ctl_inc_cy~94_combout ), - .datac(\z80_|execute_|ctl_inc_cy~87_combout ), - .datad(\z80_|execute_|ctl_inc_cy~42_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~13 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~15 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~15_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout & -// !\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~15 .lut_mask = 16'h0020; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~29 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~29_combout = (!\z80_|execute_|ctl_mRead~14_combout & ((\z80_|ir_|opcode [5]) # ((\z80_|ir_|opcode [3]) # (!\z80_|pla_decode_|Equal12~0_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~14_combout ), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal12~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~29 .lut_mask = 16'h5455; -defparam \z80_|execute_|ctl_bus_inc_oe~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~13 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~13_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|ir_|opcode [3] & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~13 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_mRead~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N8 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~49 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~49_combout = (!\z80_|pla_decode_|Equal35~0_combout & (((\z80_|ir_|opcode [3]) # (\z80_|ir_|opcode [4])) # (!\z80_|pla_decode_|Equal24~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal24~0_combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|pla_decode_|Equal35~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~49 .lut_mask = 16'h00FD; -defparam \z80_|execute_|pc_inc_hold~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~9_combout = (!\z80_|execute_|ctl_mRead~10_combout & (!\z80_|execute_|ctl_mRead~15_combout & (!\z80_|pla_decode_|Equal41~2_combout & !\z80_|execute_|ctl_mRead~8_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|execute_|ctl_mRead~15_combout ), - .datac(\z80_|pla_decode_|Equal41~2_combout ), - .datad(\z80_|execute_|ctl_mRead~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~9 .lut_mask = 16'h0001; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~10 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~10_combout = (\z80_|execute_|pc_inc_hold~49_combout & (!\z80_|pla_decode_|Equal19~0_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~9_combout )) - - .dataa(\z80_|execute_|pc_inc_hold~49_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal19~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~10 .lut_mask = 16'h0A00; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~28 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~28_combout = (!\z80_|pla_decode_|Equal33~2_combout & (((!\z80_|pla_decode_|Equal49~0_combout & !\z80_|pla_decode_|Equal50~0_combout )) # (!\z80_|decode_state_|use_ixiy~combout ))) - - .dataa(\z80_|pla_decode_|Equal33~2_combout ), - .datab(\z80_|pla_decode_|Equal49~0_combout ), - .datac(\z80_|decode_state_|use_ixiy~combout ), - .datad(\z80_|pla_decode_|Equal50~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~28 .lut_mask = 16'h0515; -defparam \z80_|execute_|pc_inc_hold~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|setM1~35 ( -// Equation(s): -// \z80_|execute_|setM1~35_combout = (!\z80_|pla_decode_|Equal6~1_combout & (!\z80_|pla_decode_|Equal39~0_combout & !\z80_|pla_decode_|Equal40~1_combout )) - - .dataa(gnd), - .datab(\z80_|pla_decode_|Equal6~1_combout ), - .datac(\z80_|pla_decode_|Equal39~0_combout ), - .datad(\z80_|pla_decode_|Equal40~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~35 .lut_mask = 16'h0003; -defparam \z80_|execute_|setM1~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N16 -cycloneive_lcell_comb \z80_|execute_|setM1~36 ( -// Equation(s): -// \z80_|execute_|setM1~36_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout & (!\z80_|execute_|ctl_mRead~9_combout & (\z80_|execute_|pc_inc_hold~28_combout & \z80_|execute_|setM1~35_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), - .datab(\z80_|execute_|ctl_mRead~9_combout ), - .datac(\z80_|execute_|pc_inc_hold~28_combout ), - .datad(\z80_|execute_|setM1~35_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~36 .lut_mask = 16'h2000; -defparam \z80_|execute_|setM1~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y18_N2 -cycloneive_lcell_comb \z80_|execute_|fMRead~5 ( -// Equation(s): -// \z80_|execute_|fMRead~5_combout = (!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|execute_|ctl_mRead~13_combout & (!\z80_|pla_decode_|Equal52~1_combout & \z80_|execute_|setM1~36_combout ))) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|execute_|ctl_mRead~13_combout ), - .datac(\z80_|pla_decode_|Equal52~1_combout ), - .datad(\z80_|execute_|setM1~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~5 .lut_mask = 16'h0100; -defparam \z80_|execute_|fMRead~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y18_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~31 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~31_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout & (((\z80_|execute_|ctl_bus_inc_oe~29_combout & \z80_|execute_|fMRead~5_combout )) # (!\z80_|execute_|ctl_alu_op_low~8_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~29_combout ), - .datad(\z80_|execute_|fMRead~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~31 .lut_mask = 16'hA222; -defparam \z80_|execute_|ctl_bus_inc_oe~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N20 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~29 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~29_combout = (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T4_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~29 .lut_mask = 16'hC8C8; -defparam \z80_|execute_|pc_inc_hold~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~1 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we~1_combout = (\z80_|execute_|pc_inc_hold~29_combout & ((\z80_|pla_decode_|Equal10~0_combout ) # (\z80_|execute_|ctl_mRead~36_combout ))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|execute_|ctl_mRead~36_combout ), - .datac(gnd), - .datad(\z80_|execute_|pc_inc_hold~29_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we~1 .lut_mask = 16'hEE00; -defparam \z80_|execute_|ctl_reg_sys_we~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we~2_combout = (!\z80_|execute_|ctl_reg_sys_we~1_combout & (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|execute_|ctl_mWrite~16_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|execute_|ctl_reg_sys_we~1_combout ), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|execute_|ctl_mWrite~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we~2 .lut_mask = 16'h1113; -defparam \z80_|execute_|ctl_reg_sys_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N14 -cycloneive_lcell_comb \z80_|pla_decode_|Equal33~3 ( -// Equation(s): -// \z80_|pla_decode_|Equal33~3_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal33~0_combout & (\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|decode_state_|use_ixiy~combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal33~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal33~3 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal33~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we~0_combout = (\z80_|execute_|ixy_d~5_combout & ((\z80_|pla_decode_|Equal33~3_combout ) # ((\z80_|pla_decode_|Equal6~1_combout ) # (!\z80_|execute_|pc_inc_hold~49_combout )))) - - .dataa(\z80_|pla_decode_|Equal33~3_combout ), - .datab(\z80_|execute_|pc_inc_hold~49_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|pla_decode_|Equal6~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we~0 .lut_mask = 16'hF0B0; -defparam \z80_|execute_|ctl_reg_sys_we~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we~3_combout = (((\z80_|execute_|ctl_reg_sys_we~0_combout ) # (\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout )) # (!\z80_|execute_|ctl_reg_sys_we~2_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~31_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~31_combout ), - .datab(\z80_|execute_|ctl_reg_sys_we~2_combout ), - .datac(\z80_|execute_|ctl_reg_sys_we~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we~3 .lut_mask = 16'hFFF7; -defparam \z80_|execute_|ctl_reg_sys_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we_lo~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we_lo~2_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal55~0_combout & \z80_|pla_decode_|Equal6~0_combout )) - - .dataa(\z80_|ir_|opcode [5]), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we_lo~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we_lo~2 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_reg_sys_we_lo~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we_lo~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we_lo~3_combout = (\z80_|execute_|ctl_reg_sys_we_lo~2_combout ) # ((\z80_|pla_decode_|Equal9~1_combout ) # ((\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal8~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|pla_decode_|Equal8~0_combout ), - .datac(\z80_|execute_|ctl_reg_sys_we_lo~2_combout ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we_lo~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we_lo~3 .lut_mask = 16'hFFF8; -defparam \z80_|execute_|ctl_reg_sys_we_lo~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we_lo~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we_lo~4_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|execute_|ctl_reg_sys_we_lo~3_combout & \z80_|sequencer_|DFFE_M2_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|execute_|ctl_reg_sys_we_lo~3_combout ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we_lo~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we_lo~4 .lut_mask = 16'h8080; -defparam \z80_|execute_|ctl_reg_sys_we_lo~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N20 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~combout = (\z80_|execute_|ctl_reg_sys_we~3_combout ) # ((\z80_|execute_|ctl_reg_sys_we_lo~4_combout ) # ((!\z80_|reg_control_|reg_sys_we_lo~7_combout ) # (!\z80_|reg_control_|reg_sys_we_lo~4_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_we~3_combout ), - .datab(\z80_|execute_|ctl_reg_sys_we_lo~4_combout ), - .datac(\z80_|reg_control_|reg_sys_we_lo~4_combout ), - .datad(\z80_|reg_control_|reg_sys_we_lo~7_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo .lut_mask = 16'hEFFF; -defparam \z80_|reg_control_|reg_sys_we_lo .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_ir~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_ir~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_ir~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_ir~0 .lut_mask = 16'h3330; -defparam \z80_|execute_|ctl_reg_sel_ir~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_ir~1 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_ir~1_combout = ((\z80_|execute_|ctl_reg_sel_ir~0_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & !\z80_|execute_|ctl_flags_bus~4_combout ))) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ) - - .dataa(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_flags_bus~4_combout ), - .datad(\z80_|execute_|ctl_reg_sel_ir~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_ir~1 .lut_mask = 16'hFF5D; -defparam \z80_|execute_|ctl_reg_sel_ir~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~9_combout = (\z80_|execute_|ctl_inc_cy~34_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|sequencer_|M5~q ) # (!\z80_|pla_decode_|Equal19~0_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|execute_|ctl_inc_cy~34_combout ), - .datac(\z80_|pla_decode_|Equal19~0_combout ), - .datad(\z80_|sequencer_|M5~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~9 .lut_mask = 16'h8CCC; -defparam \z80_|execute_|ctl_reg_out_lo~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~36 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~36_combout = (\z80_|execute_|ctl_alu_op_low~14_combout ) # ((\z80_|sequencer_|DFFE_T4_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|pla_decode_|Equal48~0_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|pla_decode_|Equal48~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~36 .lut_mask = 16'hF2F0; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~12 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[0]~12_combout = (((\z80_|ir_|opcode [3] & \z80_|execute_|ctl_reg_sys_hilo[1]~36_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout )) # (!\z80_|execute_|ctl_reg_out_lo~9_combout ) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|execute_|ctl_reg_out_lo~9_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~12 .lut_mask = 16'hBF3F; -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout = (\z80_|sequencer_|DFFE_T5_ff~q & \z80_|execute_|ixy_d~15_combout ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T5_ff~q ), - .datac(gnd), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 .lut_mask = 16'hCC00; -defparam \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~4_combout = (\z80_|reg_control_|reg_sel_pc~2_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~4_combout & (\z80_|execute_|ctl_alu_oe~4_combout & !\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ))) - - .dataa(\z80_|reg_control_|reg_sel_pc~2_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), - .datac(\z80_|execute_|ctl_alu_oe~4_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~4 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_in_hi~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~4_combout = ((!\z80_|pla_decode_|Equal34~0_combout & ((!\z80_|pla_decode_|Equal3~1_combout ) # (!\z80_|pla_decode_|Equal19~1_combout )))) # (!\z80_|execute_|ctl_reg_in_hi~2_combout ) - - .dataa(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datab(\z80_|pla_decode_|Equal34~0_combout ), - .datac(\z80_|pla_decode_|Equal19~1_combout ), - .datad(\z80_|pla_decode_|Equal3~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~4 .lut_mask = 16'h5777; -defparam \z80_|execute_|ctl_reg_sel_wz~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|execute_|comb~0_combout & \z80_|execute_|ixy_d~6_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal52~0_combout ), - .datac(\z80_|execute_|comb~0_combout ), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~5_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & (((!\z80_|execute_|ctl_mRead~10_combout & !\z80_|execute_|ctl_mRead~8_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|execute_|ctl_mRead~8_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~5 .lut_mask = 16'h001F; -defparam \z80_|execute_|ctl_reg_sel_wz~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~6_combout = (\z80_|execute_|ctl_reg_sel_wz~4_combout & \z80_|execute_|ctl_reg_sel_wz~5_combout ) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~4_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_sel_wz~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~6 .lut_mask = 16'hAA00; -defparam \z80_|execute_|ctl_reg_sel_wz~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~7_combout = (\z80_|execute_|ctl_bus_db_oe~0_combout & (\z80_|execute_|ctl_reg_in_hi~4_combout & (\z80_|execute_|ctl_reg_in_hi~3_combout & \z80_|execute_|ctl_reg_sel_wz~6_combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_oe~0_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~4_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~3_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~7 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sel_wz~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo~16 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo~16_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|execute_|ctl_mRead~14_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|execute_|ctl_mRead~14_combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo~16 .lut_mask = 16'h80C0; -defparam \z80_|execute_|ctl_reg_sys_hilo~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~11 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~11_combout = (!\z80_|execute_|ctl_reg_sys_hilo~16_combout & (((!\z80_|execute_|ctl_mRead~36_combout & !\z80_|pla_decode_|Equal10~0_combout )) # (!\z80_|execute_|ctl_mWrite~7_combout ))) - - .dataa(\z80_|execute_|ctl_mWrite~7_combout ), - .datab(\z80_|execute_|ctl_mRead~36_combout ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~11 .lut_mask = 16'h0057; -defparam \z80_|execute_|ctl_reg_sel_pc~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~17 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~17_combout = (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~17 .lut_mask = 16'hE0F0; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~12 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~12_combout = (\z80_|execute_|ctl_reg_sel_pc~11_combout & (((\z80_|execute_|ctl_flags_bus~5_combout & \z80_|execute_|ctl_al_we~13_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~11_combout ), - .datab(\z80_|execute_|ctl_flags_bus~5_combout ), - .datac(\z80_|execute_|ctl_al_we~13_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~12 .lut_mask = 16'h80AA; -defparam \z80_|execute_|ctl_reg_sel_pc~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~13 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~13_combout = (\z80_|execute_|ctl_reg_sel_pc~12_combout & (\z80_|execute_|setM1~52_combout & ((!\z80_|pla_decode_|Equal6~1_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~12_combout ), - .datac(\z80_|execute_|setM1~52_combout ), - .datad(\z80_|pla_decode_|Equal6~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~13 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_reg_sel_pc~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~4_combout = (!\z80_|execute_|ctl_mRead~4_combout & (!\z80_|execute_|ixy_d~16_combout & (!\z80_|execute_|ixy_d~10_combout & !\z80_|execute_|ctl_mRead~5_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~4_combout ), - .datab(\z80_|execute_|ixy_d~16_combout ), - .datac(\z80_|execute_|ixy_d~10_combout ), - .datad(\z80_|execute_|ctl_mRead~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~4 .lut_mask = 16'h0001; -defparam \z80_|execute_|ctl_al_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~38 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~38_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ctl_al_we~4_combout )))) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|pla_decode_|Equal34~0_combout ), - .datad(\z80_|execute_|ctl_al_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~38 .lut_mask = 16'h2022; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y18_N24 -cycloneive_lcell_comb \z80_|execute_|fMRead~0 ( -// Equation(s): -// \z80_|execute_|fMRead~0_combout = ((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|fMRead~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~0 .lut_mask = 16'h5D5D; -defparam \z80_|execute_|fMRead~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~24 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~24_combout = (!\z80_|pla_decode_|Equal6~1_combout & (\z80_|execute_|ctl_bus_db_oe~1_combout & !\z80_|pla_decode_|Equal52~1_combout )) - - .dataa(gnd), - .datab(\z80_|pla_decode_|Equal6~1_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .datad(\z80_|pla_decode_|Equal52~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~24 .lut_mask = 16'h0030; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~25 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~25_combout = (!\z80_|execute_|fMRead~0_combout & ((!\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), - .datab(gnd), - .datac(\z80_|execute_|fMRead~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~25 .lut_mask = 16'h050F; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~4 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~4_combout = ((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~4 .lut_mask = 16'h0FAF; -defparam \z80_|execute_|ctl_inc_dec~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~21 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~21_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & (\z80_|execute_|ctl_reg_sys_hilo~20_combout & ((\z80_|execute_|ctl_inc_dec~4_combout ) # (!\z80_|pla_decode_|Equal33~3_combout )))) # -// (!\z80_|execute_|ctl_alu_op_low~8_combout & (((\z80_|execute_|ctl_inc_dec~4_combout ) # (!\z80_|pla_decode_|Equal33~3_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), - .datac(\z80_|execute_|ctl_inc_dec~4_combout ), - .datad(\z80_|pla_decode_|Equal33~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~21 .lut_mask = 16'hD0DD; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~9_combout = (!\z80_|execute_|ctl_ir_we~8_combout & (!\z80_|execute_|ctl_mRead~15_combout & !\z80_|execute_|ctl_ir_we~14_combout )) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_mRead~15_combout ), - .datad(\z80_|execute_|ctl_ir_we~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~9 .lut_mask = 16'h0005; -defparam \z80_|execute_|ctl_reg_sel_wz~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|execute_|ctl_ir_we~12_combout & \z80_|sequencer_|DFFE_M2_ff~q )) +// \z80_|execute_|ixy_d~4_combout = (!\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) .dataa(gnd), .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~22 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~22_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~21_combout & (!\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout & ((\z80_|execute_|ctl_reg_sel_wz~9_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout -// )))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ), - .datac(\z80_|execute_|ctl_reg_sel_wz~9_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~22 .lut_mask = 16'h00C4; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~23 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~23_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout & (((\z80_|execute_|pc_inc_hold~49_combout & !\z80_|pla_decode_|Equal6~1_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~49_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ), - .datac(\z80_|pla_decode_|Equal6~1_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~23 .lut_mask = 16'h08CC; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~8_combout = (!\z80_|execute_|ctl_mRead~17_combout & ((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~17_combout ), - .datab(\z80_|pla_decode_|Equal12~1_combout ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal25~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~8 .lut_mask = 16'h4455; -defparam \z80_|execute_|ctl_reg_sel_wz~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~18 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~18_combout = (!\z80_|execute_|ctl_reg_sel_wz~8_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # ((\z80_|execute_|ctl_state_alu~5_combout ) # (\z80_|execute_|ctl_alu_oe~2_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~8_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_state_alu~5_combout ), - .datad(\z80_|execute_|ctl_alu_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~18 .lut_mask = 16'h5554; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~19 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~19_combout = (!\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout & ((\z80_|execute_|fMRead~0_combout ) # ((!\z80_|execute_|ctl_mRead~9_combout & \z80_|execute_|pc_inc_hold~28_combout )))) - - .dataa(\z80_|execute_|fMRead~0_combout ), - .datab(\z80_|execute_|ctl_mRead~9_combout ), - .datac(\z80_|execute_|pc_inc_hold~28_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~19 .lut_mask = 16'h00BA; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~26 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~26_combout = (!\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout & (\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~26 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~5_combout = (\z80_|execute_|ctl_reg_sel_wz~8_combout & (!\z80_|pla_decode_|Equal34~0_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout & !\z80_|execute_|ctl_mRead~9_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~8_combout ), - .datab(\z80_|pla_decode_|Equal34~0_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), - .datad(\z80_|execute_|ctl_mRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~5 .lut_mask = 16'h0020; -defparam \z80_|execute_|ctl_al_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~27 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~27_combout = (!\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout & ((\z80_|execute_|ctl_al_we~5_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_al_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~27 .lut_mask = 16'h4404; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~28 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~28_combout = (\z80_|execute_|ctl_reg_sel_wz~7_combout & (\z80_|execute_|ctl_reg_sel_pc~13_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~7_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~13_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~28 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~18 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~18_combout = (\z80_|alu_control_|flags_cond_true~q & (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|pla_decode_|Equal35~0_combout ))) - - .dataa(\z80_|alu_control_|flags_cond_true~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|pla_decode_|Equal35~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~18 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sel_wz~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~37 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[0]~37_combout = (\z80_|execute_|ctl_reg_sel_wz~18_combout ) # ((\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|M5~q & \z80_|pla_decode_|Equal9~1_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~37 .lut_mask = 16'hFF80; -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~29 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[0]~29_combout = (\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ) # (((\z80_|execute_|ctl_reg_sys_hilo[0]~37_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~19_combout )) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~19_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~37_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~29 .lut_mask = 16'hFFBF; -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N12 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_62 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_62~combout = (!\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|execute_|ctl_reg_sel_ir~1_combout & \z80_|execute_|ctl_reg_sys_hilo[0]~29_combout )) - - .dataa(gnd), - .datab(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datac(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_62 .lut_mask = 16'h3000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_62 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~38 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~38_combout = ((\z80_|execute_|ctl_ir_we~11_combout ) # ((\z80_|execute_|ctl_mRead~6_combout ) # (\z80_|execute_|ctl_mRead~7_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_mRead~6_combout ), - .datad(\z80_|execute_|ctl_mRead~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~38 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_bus_inc_oe~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~39 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~39_combout = (\z80_|execute_|ctl_mRead~10_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~38_combout ) # ((\z80_|pla_decode_|Equal13~2_combout ) # (\z80_|execute_|ctl_state_alu~14_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~38_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|ctl_state_alu~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~39 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_bus_inc_oe~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~30 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~30_combout = (\z80_|execute_|pc_inc_hold~49_combout & (!\z80_|pla_decode_|Equal6~1_combout & ((!\z80_|pla_decode_|Equal33~2_combout ) # (!\z80_|decode_state_|use_ixiy~combout )))) - - .dataa(\z80_|execute_|pc_inc_hold~49_combout ), - .datab(\z80_|pla_decode_|Equal6~1_combout ), - .datac(\z80_|decode_state_|use_ixiy~combout ), - .datad(\z80_|pla_decode_|Equal33~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~30 .lut_mask = 16'h0222; -defparam \z80_|execute_|ctl_bus_inc_oe~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~45 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~45_combout = (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & ((!\z80_|execute_|nextM~2_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~30_combout )))) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~30_combout ), - .datab(\z80_|execute_|nextM~2_combout ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~45 .lut_mask = 16'h7000; -defparam \z80_|execute_|ctl_bus_inc_oe~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N12 -cycloneive_lcell_comb \z80_|execute_|fMRead~1 ( -// Equation(s): -// \z80_|execute_|fMRead~1_combout = ((!\z80_|pla_decode_|Equal33~0_combout ) # (!\z80_|ir_|opcode [7])) # (!\z80_|execute_|ctl_ir_we~5_combout ) - - .dataa(\z80_|execute_|ctl_ir_we~5_combout ), - .datab(gnd), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~1 .lut_mask = 16'h5FFF; -defparam \z80_|execute_|fMRead~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~36 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~36_combout = (\z80_|execute_|ixy_d~7_combout & (((\z80_|execute_|ctl_mRead~6_combout ) # (\z80_|execute_|ctl_mRead~5_combout )) # (!\z80_|execute_|fMRead~1_combout ))) - - .dataa(\z80_|execute_|fMRead~1_combout ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_mRead~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~36 .lut_mask = 16'hF0D0; -defparam \z80_|execute_|ctl_bus_inc_oe~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~27 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~27_combout = (\z80_|execute_|ctl_ir_we~4_combout & (!\z80_|execute_|ctl_mRead~9_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|execute_|ctl_mWrite~16_combout )))) # (!\z80_|execute_|ctl_ir_we~4_combout & -// (((!\z80_|execute_|ixy_d~5_combout )) # (!\z80_|execute_|ctl_mWrite~16_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ctl_mWrite~16_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|execute_|ctl_mRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~27 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_bus_inc_oe~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~28 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~28_combout = (\z80_|execute_|ctl_bus_inc_oe~47_combout & (\z80_|execute_|ctl_bus_inc_oe~26_combout & \z80_|execute_|ctl_bus_inc_oe~27_combout )) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~47_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_bus_inc_oe~26_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~27_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~28 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_bus_inc_oe~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~37 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~37_combout = (\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ) # ((\z80_|execute_|ctl_bus_inc_oe~36_combout ) # ((!\z80_|execute_|ctl_bus_inc_oe~28_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~46_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~36_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~46_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~28_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~37 .lut_mask = 16'hEFFF; -defparam \z80_|execute_|ctl_bus_inc_oe~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~40 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~40_combout = (\z80_|execute_|ctl_bus_inc_oe~45_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~37_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~39_combout & \z80_|execute_|ctl_ir_we~4_combout ))) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~39_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~45_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~37_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~40 .lut_mask = 16'hFFEC; -defparam \z80_|execute_|ctl_bus_inc_oe~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~35 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~35_combout = ((\z80_|execute_|ctl_alu_oe~2_combout & ((\z80_|execute_|ctl_mRead~6_combout ) # (\z80_|execute_|ctl_mRead~10_combout )))) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout ) - - .dataa(\z80_|execute_|ctl_mRead~6_combout ), - .datab(\z80_|execute_|ctl_alu_oe~2_combout ), - .datac(\z80_|execute_|ctl_mRead~10_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~35 .lut_mask = 16'hC8FF; -defparam \z80_|execute_|ctl_bus_inc_oe~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~77 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~77_combout = (\z80_|execute_|ctl_inc_cy~76_combout & (((!\z80_|execute_|ctl_alu_shift_oe~14_combout & !\z80_|execute_|ctl_sw_4u~0_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|execute_|ctl_sw_4u~0_combout ), - .datac(\z80_|execute_|ctl_inc_cy~76_combout ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~77_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~77 .lut_mask = 16'h10F0; -defparam \z80_|execute_|ctl_inc_cy~77 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~32 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~32_combout = (\z80_|execute_|ixy_d~9_combout & (!\z80_|pla_decode_|Equal11~0_combout & ((!\z80_|pla_decode_|Equal10~0_combout )))) # (!\z80_|execute_|ixy_d~9_combout & (((!\z80_|execute_|ctl_alu_shift_oe~14_combout )) # -// (!\z80_|pla_decode_|Equal11~0_combout ))) - - .dataa(\z80_|execute_|ixy_d~9_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datad(\z80_|pla_decode_|Equal10~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~32 .lut_mask = 16'h1537; -defparam \z80_|execute_|ctl_bus_inc_oe~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M4_ff~q & (\z80_|execute_|ctl_mWrite~2_combout & \z80_|pla_decode_|Equal55~0_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|execute_|ctl_mWrite~2_combout ), - .datad(\z80_|pla_decode_|Equal55~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~33 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~33_combout = (!\z80_|execute_|ctl_reg_sys_we~1_combout & (\z80_|execute_|ctl_bus_inc_oe~32_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout & \z80_|execute_|ctl_bus_inc_oe~24_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_we~1_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~32_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~33 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_bus_inc_oe~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~34 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~34_combout = (((!\z80_|execute_|ctl_bus_inc_oe~33_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[1]~5_combout )) # (!\z80_|execute_|ctl_inc_cy~77_combout )) # (!\z80_|execute_|ctl_inc_cy~53_combout ) - - .dataa(\z80_|execute_|ctl_inc_cy~53_combout ), - .datab(\z80_|execute_|ctl_inc_cy~77_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~34 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_bus_inc_oe~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~41 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~41_combout = (\z80_|execute_|ctl_bus_inc_oe~40_combout ) # (((\z80_|execute_|ctl_bus_inc_oe~35_combout ) # (\z80_|execute_|ctl_bus_inc_oe~34_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~31_combout )) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~40_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~31_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~35_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~34_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~41 .lut_mask = 16'hFFFB; -defparam \z80_|execute_|ctl_bus_inc_oe~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~10 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~10_combout = (\z80_|execute_|ctl_reg_sel_wz~8_combout & ((\z80_|execute_|ctl_reg_sel_wz~9_combout ) # ((!\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|execute_|ctl_reg_sel_wz~8_combout & -// (((!\z80_|execute_|ctl_alu_oe~2_combout & !\z80_|execute_|ctl_ir_we~4_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~9_combout ), - .datab(\z80_|execute_|ctl_alu_oe~2_combout ), - .datac(\z80_|execute_|ctl_reg_sel_wz~8_combout ), - .datad(\z80_|execute_|ctl_ir_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~10 .lut_mask = 16'hA0F3; -defparam \z80_|execute_|ctl_reg_sel_wz~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~11 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~11_combout = (\z80_|execute_|ctl_reg_sel_wz~7_combout & \z80_|execute_|ctl_reg_sel_wz~10_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_sel_wz~7_combout ), - .datac(\z80_|execute_|ctl_reg_sel_wz~10_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~11 .lut_mask = 16'hC0C0; -defparam \z80_|execute_|ctl_reg_sel_wz~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~3 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~3_combout = (\z80_|execute_|ctl_sw_1d~4_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~4_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout )) - - .dataa(\z80_|execute_|ctl_sw_1d~4_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~3 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_sw_4d~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~4 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~4_combout = (\z80_|execute_|ctl_flags_bus~5_combout & (((!\z80_|execute_|ctl_reg_in_hi~2_combout )) # (!\z80_|pla_decode_|Equal9~1_combout ))) # (!\z80_|execute_|ctl_flags_bus~5_combout & (!\z80_|execute_|ixy_d~6_combout & -// ((!\z80_|execute_|ctl_reg_in_hi~2_combout ) # (!\z80_|pla_decode_|Equal9~1_combout )))) - - .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), - .datab(\z80_|pla_decode_|Equal9~1_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~4 .lut_mask = 16'h2A3F; -defparam \z80_|execute_|ctl_sw_4d~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~2 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~2_combout = (\z80_|execute_|ctl_reg_in_lo~9_combout & (\z80_|execute_|fMRead~6_combout & \z80_|execute_|fMRead~8_combout )) - - .dataa(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datab(gnd), - .datac(\z80_|execute_|fMRead~6_combout ), - .datad(\z80_|execute_|fMRead~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~2 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_sw_4d~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~5 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~5_combout = (\z80_|execute_|ctl_reg_sel_wz~11_combout & (\z80_|execute_|ctl_sw_4d~3_combout & (\z80_|execute_|ctl_sw_4d~4_combout & \z80_|execute_|ctl_sw_4d~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~11_combout ), - .datab(\z80_|execute_|ctl_sw_4d~3_combout ), - .datac(\z80_|execute_|ctl_sw_4d~4_combout ), - .datad(\z80_|execute_|ctl_sw_4d~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~5 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_sw_4d~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|setM1~45 ( -// Equation(s): -// \z80_|execute_|setM1~45_combout = (!\z80_|execute_|ctl_iorw~11_combout & (\z80_|execute_|ctl_mRead~19_combout & (!\z80_|execute_|ctl_mRead~13_combout & !\z80_|execute_|ctl_iorw~10_combout ))) - - .dataa(\z80_|execute_|ctl_iorw~11_combout ), - .datab(\z80_|execute_|ctl_mRead~19_combout ), - .datac(\z80_|execute_|ctl_mRead~13_combout ), - .datad(\z80_|execute_|ctl_iorw~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~45 .lut_mask = 16'h0004; -defparam \z80_|execute_|setM1~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N12 -cycloneive_lcell_comb \z80_|execute_|setM1~46 ( -// Equation(s): -// \z80_|execute_|setM1~46_combout = (\z80_|execute_|ctl_al_we~13_combout & (\z80_|execute_|setM1~45_combout & !\z80_|execute_|ctl_mWrite~6_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_al_we~13_combout ), - .datac(\z80_|execute_|setM1~45_combout ), - .datad(\z80_|execute_|ctl_mWrite~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~46 .lut_mask = 16'h00C0; -defparam \z80_|execute_|setM1~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~1 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~1_combout = ((!\z80_|decode_state_|use_ixiy~combout & ((\z80_|pla_decode_|Equal50~0_combout ) # (\z80_|pla_decode_|Equal49~0_combout )))) # (!\z80_|execute_|setM1~46_combout ) - - .dataa(\z80_|pla_decode_|Equal50~0_combout ), - .datab(\z80_|decode_state_|use_ixiy~combout ), - .datac(\z80_|pla_decode_|Equal49~0_combout ), - .datad(\z80_|execute_|setM1~46_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~1 .lut_mask = 16'h32FF; -defparam \z80_|execute_|ctl_sw_4d~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~0 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~0_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ) # ((\z80_|execute_|ctl_reg_sel_wz~18_combout ) # ((\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ctl_al_we~14_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|execute_|ctl_al_we~14_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~0 .lut_mask = 16'hFFAE; -defparam \z80_|execute_|ctl_sw_4d~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~6 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~6_combout = ((\z80_|execute_|ctl_sw_4d~0_combout ) # ((\z80_|execute_|ctl_sw_4d~1_combout & \z80_|execute_|ctl_state_alu~5_combout ))) # (!\z80_|execute_|ctl_sw_4d~5_combout ) - - .dataa(\z80_|execute_|ctl_sw_4d~5_combout ), - .datab(\z80_|execute_|ctl_sw_4d~1_combout ), - .datac(\z80_|execute_|ctl_state_alu~5_combout ), - .datad(\z80_|execute_|ctl_sw_4d~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~6 .lut_mask = 16'hFFD5; -defparam \z80_|execute_|ctl_sw_4d~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N18 -cycloneive_lcell_comb \z80_|execute_|fMRead~4 ( -// Equation(s): -// \z80_|execute_|fMRead~4_combout = (\z80_|execute_|ctl_reg_sel_wz~8_combout & (!\z80_|pla_decode_|Equal34~0_combout & \z80_|execute_|ctl_al_we~4_combout )) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~8_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal34~0_combout ), - .datad(\z80_|execute_|ctl_al_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~4 .lut_mask = 16'h0A00; -defparam \z80_|execute_|fMRead~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~16 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~16_combout = (((\z80_|execute_|ctl_state_alu~5_combout & !\z80_|execute_|fMRead~4_combout )) # (!\z80_|execute_|ctl_reg_sel_pc~10_combout )) # (!\z80_|execute_|ctl_apin_mux~0_combout ) - - .dataa(\z80_|execute_|ctl_apin_mux~0_combout ), - .datab(\z80_|execute_|ctl_state_alu~5_combout ), - .datac(\z80_|execute_|fMRead~4_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~16 .lut_mask = 16'h5DFF; -defparam \z80_|execute_|ctl_reg_sel_pc~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~14 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~14_combout = (!\z80_|pla_decode_|Equal21~1_combout & (((\z80_|decode_state_|table_xx~0_combout ) # (!\z80_|pla_decode_|Equal33~0_combout )) # (!\z80_|pla_decode_|Equal41~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal41~0_combout ), - .datab(\z80_|decode_state_|table_xx~0_combout ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|pla_decode_|Equal21~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~14 .lut_mask = 16'h00DF; -defparam \z80_|execute_|ctl_reg_sel_pc~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~20 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~20_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|pla_decode_|Equal33~3_combout ) # (!\z80_|execute_|ctl_al_we~5_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|execute_|ctl_al_we~5_combout ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|pla_decode_|Equal33~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~20 .lut_mask = 16'h5010; -defparam \z80_|execute_|ctl_reg_sel_pc~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y18_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~15 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~15_combout = (\z80_|execute_|ctl_reg_sel_pc~20_combout ) # ((!\z80_|execute_|fMRead~0_combout & ((!\z80_|execute_|setM1~36_combout ) # (!\z80_|execute_|ctl_reg_sel_pc~14_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~14_combout ), - .datab(\z80_|execute_|setM1~36_combout ), - .datac(\z80_|execute_|ctl_reg_sel_pc~20_combout ), - .datad(\z80_|execute_|fMRead~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~15 .lut_mask = 16'hF0F7; -defparam \z80_|execute_|ctl_reg_sel_pc~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~17 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~17_combout = (!\z80_|nM1_int~2_combout & (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|execute_|ctl_mWrite~16_combout )) # (!\z80_|execute_|ctl_mWrite~7_combout ))) - - .dataa(\z80_|pla_decode_|Equal11~0_combout ), - .datab(\z80_|execute_|ctl_mWrite~7_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_mWrite~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~17 .lut_mask = 16'h0307; -defparam \z80_|execute_|ctl_reg_sel_pc~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~18 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~18_combout = (((!\z80_|execute_|ctl_bus_inc_oe~30_combout & \z80_|execute_|ixy_d~5_combout )) # (!\z80_|execute_|ctl_reg_sel_pc~17_combout )) # (!\z80_|execute_|ctl_sw_4u~1_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~30_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_sw_4u~1_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~18 .lut_mask = 16'h4FFF; -defparam \z80_|execute_|ctl_reg_sel_pc~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~19 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~19_combout = ((\z80_|execute_|ctl_reg_sel_pc~16_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~15_combout ) # (\z80_|execute_|ctl_reg_sel_pc~18_combout ))) # (!\z80_|execute_|ctl_reg_sel_pc~13_combout ) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~13_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~16_combout ), - .datac(\z80_|execute_|ctl_reg_sel_pc~15_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~19 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_reg_sel_pc~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N24 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~3 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_pc~3_combout = (\z80_|reg_control_|reg_sel_pc~2_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~4_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout & \z80_|execute_|ctl_reg_sel_wz~4_combout ))) - - .dataa(\z80_|reg_control_|reg_sel_pc~2_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~4_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_pc~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_pc~3 .lut_mask = 16'h0800; -defparam \z80_|reg_control_|reg_sel_pc~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N18 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc ( -// Equation(s): -// \z80_|reg_control_|reg_sel_pc~combout = (!\z80_|execute_|ctl_reg_sel_wz~18_combout & (\z80_|execute_|ctl_reg_sel_pc~19_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & \z80_|reg_control_|reg_sel_pc~3_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~18_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~19_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .datad(\z80_|reg_control_|reg_sel_pc~3_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_pc~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_pc .lut_mask = 16'h0400; -defparam \z80_|reg_control_|reg_sel_pc .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N8 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_74 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_74~combout = (\z80_|reg_control_|reg_sel_pc~combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout & !\z80_|reg_control_|reg_sys_we_lo~combout )) - - .dataa(gnd), - .datab(\z80_|reg_control_|reg_sel_pc~combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .datad(\z80_|reg_control_|reg_sys_we_lo~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_74 .lut_mask = 16'h00C0; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N22 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~2 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[0]~2_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ) # ((\z80_|execute_|ctl_bus_inc_oe~41_combout ) # ((\z80_|execute_|ctl_sw_4d~6_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|execute_|ctl_sw_4d~6_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[0]~2 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|db_lo_as[0]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N18 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_75 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_75~combout = (\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout & (\z80_|reg_control_|reg_sel_pc~combout & \z80_|reg_control_|reg_sys_we_lo~combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .datac(\z80_|reg_control_|reg_sel_pc~combout ), - .datad(\z80_|reg_control_|reg_sys_we_lo~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_75 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N3 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[7]~24_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N2 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~22 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[7]~22_combout = (\z80_|reg_file_|gdfx_temp0[7]~92_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) # (!\z80_|reg_file_|gdfx_temp0[7]~92_combout & -// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [7]), - .datad(\z80_|execute_|ctl_sw_4d~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[7]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[7]~22 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_lo_as[7]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N28 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_63 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_63~combout = (\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|execute_|ctl_reg_sel_ir~1_combout & \z80_|execute_|ctl_reg_sys_hilo[0]~29_combout )) - - .dataa(gnd), - .datab(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datac(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_63 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y17_N25 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[7]~24_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N14 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~23 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[7]~23_combout = (\z80_|reg_file_|db_lo_as[7]~22_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datac(\z80_|reg_file_|db_lo_as[7]~22_combout ), - .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[7]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[7]~23 .lut_mask = 16'hF030; -defparam \z80_|reg_file_|db_lo_as[7]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N26 -cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_10~0 ( -// Equation(s): -// \z80_|resets_|SYNTHESIZED_WIRE_10~0_combout = !\z80_|resets_|SYNTHESIZED_WIRE_12~q - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h0F0F; -defparam \z80_|resets_|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y17_N27 -dffeas \z80_|resets_|SYNTHESIZED_WIRE_10 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_10 .is_wysiwyg = "true"; -defparam \z80_|resets_|SYNTHESIZED_WIRE_10 .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y17_N9 -dffeas \z80_|resets_|SYNTHESIZED_WIRE_9 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_9 .is_wysiwyg = "true"; -defparam \z80_|resets_|SYNTHESIZED_WIRE_9 .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y17_N29 -dffeas \z80_|resets_|DFFE_intr_ff3 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|resets_|DFFE_intr_ff3~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|resets_|DFFE_intr_ff3 .is_wysiwyg = "true"; -defparam \z80_|resets_|DFFE_intr_ff3 .power_up = "low"; -// synopsys translate_on - -// Location: IOIBUF_X53_Y14_N1 -cycloneive_io_ibuf \KEY[0]~input ( - .i(KEY[0]), - .ibar(gnd), - .o(\KEY[0]~input_o )); -// synopsys translate_off -defparam \KEY[0]~input .bus_hold = "false"; -defparam \KEY[0]~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: LCCOMB_X52_Y14_N4 -cycloneive_lcell_comb reset( -// Equation(s): -// \reset~combout = (!\KEY[0]~input_o ) # (!\ula_|pll_|altpll_component|auto_generated|wire_pll1_locked ) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|pll_|altpll_component|auto_generated|wire_pll1_locked ), - .datad(\KEY[0]~input_o ), - .cin(gnd), - .combout(\reset~combout ), - .cout()); -// synopsys translate_off -defparam reset.lut_mask = 16'h0FFF; -defparam reset.sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N26 -cycloneive_lcell_comb \z80_|resets_|x1~0 ( -// Equation(s): -// \z80_|resets_|x1~0_combout = !\reset~combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\reset~combout ), - .cin(gnd), - .combout(\z80_|resets_|x1~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|resets_|x1~0 .lut_mask = 16'h00FF; -defparam \z80_|resets_|x1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y33_N0 -cycloneive_lcell_comb \z80_|fpga_reset~feeder ( -// Equation(s): -// \z80_|fpga_reset~feeder_combout = VCC - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(gnd), - .cin(gnd), - .combout(\z80_|fpga_reset~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|fpga_reset~feeder .lut_mask = 16'hFFFF; -defparam \z80_|fpga_reset~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y33_N1 -dffeas \z80_|fpga_reset ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|fpga_reset~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|fpga_reset~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|fpga_reset .is_wysiwyg = "true"; -defparam \z80_|fpga_reset .power_up = "low"; -// synopsys translate_on - -// Location: CLKCTRL_G12 -cycloneive_clkctrl \z80_|fpga_reset~clkctrl ( - .ena(vcc), - .inclk({vcc,vcc,vcc,\z80_|fpga_reset~q }), - .clkselect(2'b00), - .devclrn(devclrn), - .devpor(devpor), - .outclk(\z80_|fpga_reset~clkctrl_outclk )); -// synopsys translate_off -defparam \z80_|fpga_reset~clkctrl .clock_type = "global clock"; -defparam \z80_|fpga_reset~clkctrl .ena_register_mode = "none"; -// synopsys translate_on - -// Location: FF_X35_Y13_N27 -dffeas \z80_|resets_|x1 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|resets_|x1~0_combout ), - .asdata(vcc), - .clrn(\z80_|fpga_reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|resets_|x1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|resets_|x1 .is_wysiwyg = "true"; -defparam \z80_|resets_|x1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N18 -cycloneive_lcell_comb \z80_|resets_|clrpc_int~0 ( -// Equation(s): -// \z80_|resets_|clrpc_int~0_combout = (\z80_|sequencer_|DFFE_M1_ff~q & (((\z80_|resets_|clrpc_int~q )))) # (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|resets_|clrpc_int~q & !\z80_|resets_|x1~q )) # -// (!\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|resets_|clrpc_int~q )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|resets_|clrpc_int~q ), - .datad(\z80_|resets_|x1~q ), - .cin(gnd), - .combout(\z80_|resets_|clrpc_int~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|resets_|clrpc_int~0 .lut_mask = 16'hB0B4; -defparam \z80_|resets_|clrpc_int~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y17_N19 -dffeas \z80_|resets_|clrpc_int ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|resets_|clrpc_int~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|resets_|clrpc_int~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|resets_|clrpc_int .is_wysiwyg = "true"; -defparam \z80_|resets_|clrpc_int .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N28 -cycloneive_lcell_comb \z80_|resets_|clrpc~0 ( -// Equation(s): -// \z80_|resets_|clrpc~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_10~q ) # ((\z80_|resets_|SYNTHESIZED_WIRE_9~q ) # ((\z80_|resets_|DFFE_intr_ff3~q ) # (\z80_|resets_|clrpc_int~q ))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), - .datac(\z80_|resets_|DFFE_intr_ff3~q ), - .datad(\z80_|resets_|clrpc_int~q ), - .cin(gnd), - .combout(\z80_|resets_|clrpc~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|resets_|clrpc~0 .lut_mask = 16'hFFFE; -defparam \z80_|resets_|clrpc~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N4 -cycloneive_lcell_comb \z80_|address_latch_|abusz[7] ( -// Equation(s): -// \z80_|address_latch_|abusz [7] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[7]~24_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(\z80_|reg_file_|db_lo_as[7]~24_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [7]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[7] .lut_mask = 16'h0F00; -defparam \z80_|address_latch_|abusz[7] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~1 ( -// Equation(s): -// \z80_|execute_|ctl_apin_mux~1_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (\z80_|sequencer_|DFFE_M2_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_apin_mux~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_apin_mux~1 .lut_mask = 16'h5550; -defparam \z80_|execute_|ctl_apin_mux~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~6_combout = (\z80_|execute_|ctl_apin_mux~1_combout & (((\z80_|pla_decode_|Equal33~3_combout ) # (!\z80_|execute_|ctl_al_we~14_combout )) # (!\z80_|execute_|ctl_al_we~5_combout ))) - - .dataa(\z80_|execute_|ctl_apin_mux~1_combout ), - .datab(\z80_|execute_|ctl_al_we~5_combout ), - .datac(\z80_|execute_|ctl_al_we~14_combout ), - .datad(\z80_|pla_decode_|Equal33~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~6 .lut_mask = 16'hAA2A; -defparam \z80_|execute_|ctl_al_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~7_combout = (\z80_|execute_|ctl_state_alu~6_combout & (((!\z80_|execute_|ctl_flags_bus~5_combout ) # (!\z80_|execute_|ctl_al_we~13_combout )))) # (!\z80_|execute_|ctl_state_alu~6_combout & (\z80_|execute_|ctl_ir_we~4_combout & -// ((!\z80_|execute_|ctl_flags_bus~5_combout ) # (!\z80_|execute_|ctl_al_we~13_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~6_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_al_we~13_combout ), - .datad(\z80_|execute_|ctl_flags_bus~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~7 .lut_mask = 16'h0EEE; -defparam \z80_|execute_|ctl_al_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~8_combout = ((\z80_|execute_|ctl_al_we~7_combout ) # ((\z80_|execute_|ixy_d~6_combout & \z80_|pla_decode_|Equal35~0_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|execute_|ctl_al_we~7_combout ), - .datad(\z80_|pla_decode_|Equal35~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~8 .lut_mask = 16'hFBF3; -defparam \z80_|execute_|ctl_al_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~10_combout = (\z80_|decode_state_|in_halt~q ) # (((!\z80_|pla_decode_|Equal33~1_combout & !\z80_|pla_decode_|Equal33~0_combout )) # (!\z80_|pla_decode_|Equal77~0_combout )) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|decode_state_|in_halt~q ), - .datac(\z80_|pla_decode_|Equal77~0_combout ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~10 .lut_mask = 16'hCFDF; -defparam \z80_|execute_|ctl_alu_oe~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~9 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~9_combout = (((!\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~29_combout )) # (!\z80_|execute_|ctl_al_we~4_combout )) # (!\z80_|execute_|ctl_alu_oe~10_combout ) - - .dataa(\z80_|execute_|ctl_alu_oe~10_combout ), - .datab(\z80_|execute_|ctl_al_we~4_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~29_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~9 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_al_we~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~10 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~10_combout = (\z80_|execute_|ctl_al_we~8_combout ) # ((\z80_|execute_|ctl_state_alu~5_combout & ((\z80_|execute_|ctl_al_we~9_combout ) # (!\z80_|execute_|setM1~45_combout )))) - - .dataa(\z80_|execute_|ctl_al_we~8_combout ), - .datab(\z80_|execute_|ctl_state_alu~5_combout ), - .datac(\z80_|execute_|setM1~45_combout ), - .datad(\z80_|execute_|ctl_al_we~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~10 .lut_mask = 16'hEEAE; -defparam \z80_|execute_|ctl_al_we~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~11 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~11_combout = (\z80_|execute_|ctl_al_we~6_combout ) # ((\z80_|execute_|ctl_al_we~10_combout ) # (!\z80_|execute_|ctl_sw_4d~5_combout )) - - .dataa(\z80_|execute_|ctl_al_we~6_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_sw_4d~5_combout ), - .datad(\z80_|execute_|ctl_al_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~11 .lut_mask = 16'hFFAF; -defparam \z80_|execute_|ctl_al_we~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~12 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~12_combout = (\z80_|execute_|ctl_al_we~11_combout ) # (((\z80_|execute_|ixy_d~7_combout & \z80_|pla_decode_|Equal6~1_combout )) # (!\z80_|execute_|setM1~52_combout )) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_al_we~11_combout ), - .datac(\z80_|execute_|setM1~52_combout ), - .datad(\z80_|pla_decode_|Equal6~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~12 .lut_mask = 16'hEFCF; -defparam \z80_|execute_|ctl_al_we~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y16_N5 -dffeas \z80_|address_latch_|Q[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [7]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[7] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~6 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~6_combout = (\z80_|execute_|ctl_apin_mux~0_combout & (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout & ((!\z80_|execute_|ctl_ir_we~4_combout ) # (!\z80_|pla_decode_|Equal9~1_combout )))) - - .dataa(\z80_|execute_|ctl_apin_mux~0_combout ), - .datab(\z80_|pla_decode_|Equal9~1_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), - .datad(\z80_|execute_|ctl_ir_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~6 .lut_mask = 16'h020A; -defparam \z80_|execute_|ctl_inc_dec~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N24 -cycloneive_lcell_comb \z80_|execute_|fIOWrite~0 ( -// Equation(s): -// \z80_|execute_|fIOWrite~0_combout = ((!\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q ))) # (!\z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), .datac(\z80_|sequencer_|DFFE_T1_ff~q ), .datad(\z80_|sequencer_|DFFE_T2_ff~q ), .cin(gnd), - .combout(\z80_|execute_|fIOWrite~0_combout ), + .combout(\z80_|execute_|ixy_d~4_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fIOWrite~0 .lut_mask = 16'h3373; -defparam \z80_|execute_|fIOWrite~0 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ixy_d~4 .lut_mask = 16'h0030; +defparam \z80_|execute_|ixy_d~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y18_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~8 ( +// Location: LCCOMB_X21_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|ixy_d~11 ( // Equation(s): -// \z80_|execute_|ctl_inc_dec~8_combout = (\z80_|execute_|ctl_mWrite~4_combout & (((\z80_|execute_|ctl_mRead~11_combout ) # (!\z80_|execute_|fIOWrite~0_combout )) # (!\z80_|execute_|ctl_inc_dec~4_combout ))) +// \z80_|execute_|ixy_d~11_combout = (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # ((\z80_|sequencer_|DFFE_T5_ff~q ) # (!\z80_|execute_|ixy_d~4_combout )))) - .dataa(\z80_|execute_|ctl_inc_dec~4_combout ), - .datab(\z80_|execute_|fIOWrite~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|execute_|ctl_mRead~11_combout ), + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T5_ff~q ), + .datad(\z80_|execute_|ixy_d~4_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~8_combout ), + .combout(\z80_|execute_|ixy_d~11_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~8 .lut_mask = 16'hF070; -defparam \z80_|execute_|ctl_inc_dec~8 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ixy_d~11 .lut_mask = 16'hC8CC; +defparam \z80_|execute_|ixy_d~11 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y18_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~9 ( +// Location: LCCOMB_X21_Y14_N6 +cycloneive_lcell_comb \z80_|execute_|ixy_d~9 ( // Equation(s): -// \z80_|execute_|ctl_inc_dec~9_combout = ((\z80_|execute_|ctl_inc_dec~8_combout ) # ((!\z80_|execute_|ctl_reg_gp_we~0_combout & \z80_|ir_|opcode [3]))) # (!\z80_|execute_|ctl_inc_dec~3_combout ) +// \z80_|execute_|ixy_d~9_combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_M3_ff~q ) - .dataa(\z80_|execute_|ctl_reg_gp_we~0_combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|execute_|ctl_inc_dec~3_combout ), - .datad(\z80_|execute_|ctl_inc_dec~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~9 .lut_mask = 16'hFF4F; -defparam \z80_|execute_|ctl_inc_dec~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~10 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~10_combout = (\z80_|execute_|ctl_inc_dec~9_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_inc_dec~6_combout ), - .datac(\z80_|execute_|ctl_inc_dec~9_combout ), + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), .datad(gnd), .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~10_combout ), + .combout(\z80_|execute_|ixy_d~9_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~10 .lut_mask = 16'hF3F3; -defparam \z80_|execute_|ctl_inc_dec~10 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ixy_d~9 .lut_mask = 16'hA0A0; +defparam \z80_|execute_|ixy_d~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y17_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~7 ( +// Location: LCCOMB_X26_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|ixy_d~7 ( // Equation(s): -// \z80_|execute_|ctl_inc_dec~7_combout = (!\z80_|execute_|ctl_bus_inc_oe~33_combout ) # (!\z80_|execute_|ctl_inc_dec~5_combout ) +// \z80_|execute_|ixy_d~7_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M3_ff~q ) - .dataa(\z80_|execute_|ctl_inc_dec~5_combout ), + .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~7_combout ), + .combout(\z80_|execute_|ixy_d~7_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~7 .lut_mask = 16'h55FF; -defparam \z80_|execute_|ctl_inc_dec~7 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ixy_d~7 .lut_mask = 16'h0F00; +defparam \z80_|execute_|ixy_d~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y17_N17 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[2]~9_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [2]), - .prn(vcc)); +// Location: LCCOMB_X24_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|ixy_d~6 ( +// Equation(s): +// \z80_|execute_|ixy_d~6_combout = (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_M3_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~6_combout ), + .cout()); // synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[2] .power_up = "low"; +defparam \z80_|execute_|ixy_d~6 .lut_mask = 16'hA0A0; +defparam \z80_|execute_|ixy_d~6 .sum_lutc_input = "datac"; // synopsys translate_on // Location: LCCOMB_X26_Y13_N8 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_54 ( +cycloneive_lcell_comb \z80_|execute_|ixy_d~8 ( // Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_54~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl2~0_combout )) +// \z80_|execute_|ixy_d~8_combout = (\z80_|sequencer_|DFFE_T5_ff~q & \z80_|sequencer_|DFFE_M3_ff~q ) .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_54 .lut_mask = 16'h0C00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N22 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_58 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_58~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_58 .lut_mask = 16'h0C00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N26 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_55 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_55~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl2~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_55 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y9_N1 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N0 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_59 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_59~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_59 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_59 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y9_N3 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~34 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~34_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (\z80_|reg_file_|b2v_latch_hl2_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (((\z80_|reg_file_|b2v_latch_hl_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]), - .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [2]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~34 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[2]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N28 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_51 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_51~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_de~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_de~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_51 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y13_N11 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N12 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~4 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_de2~4_combout = (\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de2~q & ((\z80_|reg_control_|reg_sel_de2~5_combout ))) # (!\z80_|reg_control_|bank_hl_de2~q & (\z80_|reg_control_|reg_sel_de2~6_combout )))) - - .dataa(\z80_|reg_control_|reg_sel_de2~6_combout ), - .datab(\z80_|reg_control_|reg_sel_de2~5_combout ), - .datac(\z80_|reg_control_|bank_hl_de2~q ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_de2~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_de2~4 .lut_mask = 16'hCA00; -defparam \z80_|reg_control_|reg_sel_de2~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N2 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_46 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_46~combout = (!\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|reg_control_|reg_sel_de2~4_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datac(\z80_|reg_control_|reg_sel_de2~4_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_46 .lut_mask = 16'h3000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N14 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_47 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_47~combout = (\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|reg_control_|reg_sel_de2~4_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datac(\z80_|reg_control_|reg_sel_de2~4_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_47 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y13_N17 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~33 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~33_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [2] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [2] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [2]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~33 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[2]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N26 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 .lut_mask = 16'hF000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N14 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & !\z80_|reg_control_|bank_exx~q ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 .lut_mask = 16'h0010; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y11_N15 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N8 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & \z80_|reg_control_|bank_exx~q ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 .lut_mask = 16'h1000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y11_N25 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~36 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~36_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [2]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [2]), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~36 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[2]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N30 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_83 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_83~combout = (\z80_|execute_|ctl_reg_sel_wz~17_combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout & \z80_|reg_control_|reg_sys_we_lo~combout )) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~17_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), + .datab(\z80_|sequencer_|DFFE_T5_ff~q ), .datac(gnd), - .datad(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .combout(\z80_|execute_|ixy_d~8_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_83 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_83 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ixy_d~8 .lut_mask = 16'hCC00; +defparam \z80_|execute_|ixy_d~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y10_N13 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~37 ( +// Location: LCCOMB_X27_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|ixy_d~12 ( // Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~37_combout = (\z80_|reg_file_|gdfx_temp0[2]~36_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) +// \z80_|execute_|ixy_d~12_combout = (!\z80_|execute_|ixy_d~9_combout & (!\z80_|execute_|ixy_d~7_combout & (!\z80_|execute_|ixy_d~6_combout & !\z80_|execute_|ixy_d~8_combout ))) - .dataa(\z80_|reg_file_|gdfx_temp0[2]~36_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [2]), - .datad(gnd), + .dataa(\z80_|execute_|ixy_d~9_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ixy_d~8_combout ), .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~37_combout ), + .combout(\z80_|execute_|ixy_d~12_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~37 .lut_mask = 16'hA2A2; -defparam \z80_|reg_file_|gdfx_temp0[2]~37 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ixy_d~12 .lut_mask = 16'h0001; +defparam \z80_|execute_|ixy_d~12 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y12_N6 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 ( +// Location: LCCOMB_X29_Y13_N24 +cycloneive_lcell_comb \z80_|pla_decode_|Equal33~0 ( // Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout = (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) +// \z80_|pla_decode_|Equal33~0_combout = (\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [0] & \z80_|ir_|opcode [1])) - .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|ir_|opcode [0]), + .datac(gnd), + .datad(\z80_|ir_|opcode [1]), .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .combout(\z80_|pla_decode_|Equal33~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal33~0 .lut_mask = 16'h2200; +defparam \z80_|pla_decode_|Equal33~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y10_N25 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~39 ( +// Location: LCCOMB_X20_Y17_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal33~1 ( // Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~39_combout = (\z80_|alu_control_|db[2]~29_combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [2]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) # (!\z80_|alu_control_|db[2]~29_combout & -// (!\z80_|execute_|ctl_reg_in_lo~8_combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) +// \z80_|pla_decode_|Equal33~1_combout = (\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [3])) - .dataa(\z80_|alu_control_|db[2]~29_combout ), - .datab(\z80_|reg_file_|b2v_latch_sp_lo|latch [2]), - .datac(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|ir_|opcode [4]), + .datac(gnd), + .datad(\z80_|ir_|opcode [3]), .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~39_combout ), + .combout(\z80_|pla_decode_|Equal33~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~39 .lut_mask = 16'h8CAF; -defparam \z80_|reg_file_|gdfx_temp0[2]~39 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal33~1 .lut_mask = 16'h0088; +defparam \z80_|pla_decode_|Equal33~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y15_N22 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_iy~2 ( +// Location: LCCOMB_X24_Y15_N24 +cycloneive_lcell_comb \z80_|pla_decode_|Equal33~2 ( // Equation(s): -// \z80_|reg_control_|reg_sel_iy~2_combout = (\z80_|decode_state_|DFFE_instIY1~q & (!\z80_|decode_state_|DFFE_inst4~q & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) +// \z80_|pla_decode_|Equal33~2_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal33~1_combout )) - .dataa(\z80_|decode_state_|DFFE_instIY1~q ), - .datab(\z80_|decode_state_|DFFE_inst4~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal33~1_combout ), .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_iy~2_combout ), + .combout(\z80_|pla_decode_|Equal33~2_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_control_|reg_sel_iy~2 .lut_mask = 16'h0020; -defparam \z80_|reg_control_|reg_sel_iy~2 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal33~2 .lut_mask = 16'h8800; +defparam \z80_|pla_decode_|Equal33~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y10_N26 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_70 ( +// Location: LCCOMB_X28_Y19_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal21~0 ( // Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_70~combout = (!\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & \z80_|reg_control_|reg_sel_iy~2_combout )) +// \z80_|pla_decode_|Equal21~0_combout = (\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [3]) .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datad(\z80_|reg_control_|reg_sel_iy~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70 .lut_mask = 16'h3000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N16 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout = (\z80_|decode_state_|DFFE_inst4~q & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 .lut_mask = 16'h0080; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y10_N31 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N24 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_71 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_71~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (\z80_|reg_control_|reg_sel_iy~2_combout & \z80_|execute_|ctl_reg_gp_we~6_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datab(\z80_|reg_control_|reg_sel_iy~2_combout ), + .datab(\z80_|ir_|opcode [4]), .datac(gnd), - .datad(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datad(\z80_|ir_|opcode [3]), .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .combout(\z80_|pla_decode_|Equal21~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal21~0 .lut_mask = 16'h00CC; +defparam \z80_|pla_decode_|Equal21~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y10_N15 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~38 ( +// Location: LCCOMB_X25_Y16_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal77~0 ( // Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~38_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) +// \z80_|pla_decode_|Equal77~0_combout = (!\z80_|decode_state_|DFFE_instCB~q & (!\z80_|decode_state_|DFFE_instED~q & (!\z80_|ir_|opcode [7] & \z80_|ir_|opcode [6]))) - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [2]), - .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [2]), + .dataa(\z80_|decode_state_|DFFE_instCB~q ), + .datab(\z80_|decode_state_|DFFE_instED~q ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|ir_|opcode [6]), .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~38_combout ), + .combout(\z80_|pla_decode_|Equal77~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~38 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[2]~38 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal77~0 .lut_mask = 16'h0100; +defparam \z80_|pla_decode_|Equal77~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y10_N10 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_31 ( +// Location: LCCOMB_X28_Y16_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal77~1 ( // Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_31~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_af2~0_combout )) +// \z80_|pla_decode_|Equal77~1_combout = (\z80_|pla_decode_|Equal21~0_combout & (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal77~0_combout ))) - .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datac(gnd), - .datad(\z80_|reg_control_|reg_sel_af2~0_combout ), + .dataa(\z80_|pla_decode_|Equal21~0_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|pla_decode_|Equal77~0_combout ), .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .combout(\z80_|pla_decode_|Equal77~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_31 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_31 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal77~1 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal77~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y10_N23 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N28 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder ( +// Location: LCCOMB_X28_Y13_N26 +cycloneive_lcell_comb \z80_|pla_decode_|Equal1~7 ( // Equation(s): -// \z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp0[2]~42_combout +// \z80_|pla_decode_|Equal1~7_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [6] & (!\z80_|decode_state_|table_xx~0_combout & \z80_|ir_|opcode [7]))) - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [6]), + .datac(\z80_|decode_state_|table_xx~0_combout ), + .datad(\z80_|ir_|opcode [7]), .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder_combout ), + .combout(\z80_|pla_decode_|Equal1~7_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal1~7 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal1~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y14_N8 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_35 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_35~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_af~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_af~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_35 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N29 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~35 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~35_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [2]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [2]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~35 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[2]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~40 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~40_combout = (\z80_|reg_file_|gdfx_temp0[2]~37_combout & (\z80_|reg_file_|gdfx_temp0[2]~39_combout & (\z80_|reg_file_|gdfx_temp0[2]~38_combout & \z80_|reg_file_|gdfx_temp0[2]~35_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[2]~37_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[2]~39_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[2]~38_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[2]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~40 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[2]~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~41 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~41_combout = (\z80_|reg_file_|gdfx_temp0[2]~34_combout & (\z80_|reg_file_|gdfx_temp0[2]~33_combout & \z80_|reg_file_|gdfx_temp0[2]~40_combout )) - - .dataa(\z80_|reg_file_|gdfx_temp0[2]~34_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[2]~33_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[2]~40_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~41 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|gdfx_temp0[2]~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~42 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~42_combout = ((\z80_|reg_file_|gdfx_temp0[2]~41_combout & ((\z80_|reg_file_|db_lo_as[2]~9_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .datac(\z80_|execute_|ctl_sw_4u~6_combout ), - .datad(\z80_|reg_file_|db_lo_as[2]~9_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~42 .lut_mask = 16'hBB3B; -defparam \z80_|reg_file_|gdfx_temp0[2]~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N21 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[2]~9_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N20 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~7 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[2]~7_combout = (\z80_|reg_file_|gdfx_temp0[2]~42_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # (!\z80_|reg_file_|gdfx_temp0[2]~42_combout & -// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .datab(\z80_|execute_|ctl_sw_4d~6_combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[2]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[2]~7 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|db_lo_as[2]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N26 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~8 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[2]~8_combout = (\z80_|reg_file_|db_lo_as[2]~7_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_lo|latch [2]), - .datad(\z80_|reg_file_|db_lo_as[2]~7_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[2]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[2]~8 .lut_mask = 16'hF300; -defparam \z80_|reg_file_|db_lo_as[2]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y17_N9 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[0]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y13_N13 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y13_N19 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~10 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~10_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [0] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [0] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [0]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~10 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[0]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y13_N29 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N28 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]) # (!\z80_|reg_control_|reg_sel_hl2~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]), - .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y9_N9 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~11 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~11_combout = (\z80_|reg_file_|gdfx_temp0[0]~10_combout & (\z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0_combout & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[0]~10_combout ), - .datab(\z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_hl_lo|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~11 .lut_mask = 16'h8088; -defparam \z80_|reg_file_|gdfx_temp0[0]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y10_N21 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y10_N19 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~15 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~15_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_sp_lo|latch [0]), - .datac(\z80_|reg_file_|b2v_latch_iy_lo|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~15 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp0[0]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y11_N19 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N30 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder_combout = \z80_|reg_file_|gdfx_temp0[0]~22_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y11_N31 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y11_N1 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~14 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~14_combout = (\z80_|reg_file_|b2v_latch_bc_lo|latch [0] & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # (!\z80_|reg_file_|b2v_latch_bc_lo|latch [0] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc_lo|latch [0]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~14 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[0]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~16 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~16_combout = (\z80_|reg_file_|gdfx_temp0[0]~15_combout & (\z80_|reg_file_|gdfx_temp0[0]~14_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[0]~15_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [0]), - .datad(\z80_|reg_file_|gdfx_temp0[0]~14_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~16 .lut_mask = 16'hA200; -defparam \z80_|reg_file_|gdfx_temp0[0]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y11_N1 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~12 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~12_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [0] & ((\z80_|alu_control_|db[0]~12_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (((\z80_|alu_control_|db[0]~12_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [0]), - .datad(\z80_|alu_control_|db[0]~12_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~12 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[0]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N7 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y10_N13 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~13 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~13_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [0]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [0]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~13 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[0]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~17 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~17_combout = (\z80_|reg_file_|gdfx_temp0[0]~11_combout & (\z80_|reg_file_|gdfx_temp0[0]~16_combout & (\z80_|reg_file_|gdfx_temp0[0]~12_combout & \z80_|reg_file_|gdfx_temp0[0]~13_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[0]~11_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~16_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[0]~12_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[0]~13_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~17 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[0]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~22 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~22_combout = ((\z80_|reg_file_|gdfx_temp0[0]~17_combout & ((\z80_|reg_file_|db_lo_as[0]~3_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~17_combout ), - .datac(\z80_|reg_file_|db_lo_as[0]~3_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~22 .lut_mask = 16'hC4FF; -defparam \z80_|reg_file_|gdfx_temp0[0]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N25 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[0]~3_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N24 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~0 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[0]~0_combout = (\z80_|reg_file_|gdfx_temp0[0]~22_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) # (!\z80_|reg_file_|gdfx_temp0[0]~22_combout & -// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [0]), - .datad(\z80_|execute_|ctl_sw_4d~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[0]~0 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_lo_as[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N22 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~1 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[0]~1_combout = (\z80_|reg_file_|db_lo_as[0]~0_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|b2v_latch_ir_lo|latch [0]), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datad(\z80_|reg_file_|db_lo_as[0]~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[0]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[0]~1 .lut_mask = 16'hCF00; -defparam \z80_|reg_file_|db_lo_as[0]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~72 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~72_combout = (!\z80_|nM1_int~2_combout & (((!\z80_|execute_|ctl_alu_op_low~8_combout & !\z80_|execute_|ixy_d~5_combout )) # (!\z80_|pla_decode_|Equal41~2_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|pla_decode_|Equal41~2_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~72_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~72 .lut_mask = 16'h0515; -defparam \z80_|execute_|ctl_inc_cy~72 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: CLKCTRL_G18 -cycloneive_clkctrl \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl ( - .ena(vcc), - .inclk({vcc,vcc,vcc,\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk [0]}), - .clkselect(2'b00), - .devclrn(devclrn), - .devpor(devpor), - .outclk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk )); -// synopsys translate_off -defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .clock_type = "global clock"; -defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .ena_register_mode = "none"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N16 -cycloneive_lcell_comb \ula_|video_|Add0~14 ( -// Equation(s): -// \ula_|video_|Add0~14_combout = (\ula_|video_|vga_hc [7] & (!\ula_|video_|Add0~13 )) # (!\ula_|video_|vga_hc [7] & ((\ula_|video_|Add0~13 ) # (GND))) -// \ula_|video_|Add0~15 = CARRY((!\ula_|video_|Add0~13 ) # (!\ula_|video_|vga_hc [7])) - - .dataa(gnd), - .datab(\ula_|video_|vga_hc [7]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add0~13 ), - .combout(\ula_|video_|Add0~14_combout ), - .cout(\ula_|video_|Add0~15 )); -// synopsys translate_off -defparam \ula_|video_|Add0~14 .lut_mask = 16'h3C3F; -defparam \ula_|video_|Add0~14 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N18 -cycloneive_lcell_comb \ula_|video_|Add0~16 ( -// Equation(s): -// \ula_|video_|Add0~16_combout = (\ula_|video_|vga_hc [8] & (\ula_|video_|Add0~15 $ (GND))) # (!\ula_|video_|vga_hc [8] & (!\ula_|video_|Add0~15 & VCC)) -// \ula_|video_|Add0~17 = CARRY((\ula_|video_|vga_hc [8] & !\ula_|video_|Add0~15 )) - - .dataa(\ula_|video_|vga_hc [8]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add0~15 ), - .combout(\ula_|video_|Add0~16_combout ), - .cout(\ula_|video_|Add0~17 )); -// synopsys translate_off -defparam \ula_|video_|Add0~16 .lut_mask = 16'hA50A; -defparam \ula_|video_|Add0~16 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N26 -cycloneive_lcell_comb \ula_|video_|vga_hc~2 ( -// Equation(s): -// \ula_|video_|vga_hc~2_combout = (\ula_|video_|Equal1~0_combout & \ula_|video_|Add0~16_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|video_|Equal1~0_combout ), - .datad(\ula_|video_|Add0~16_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_hc~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_hc~2 .lut_mask = 16'hF000; -defparam \ula_|video_|vga_hc~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y33_N27 -dffeas \ula_|video_|vga_hc[8] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_hc~2_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_hc [8]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_hc[8] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_hc[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N20 -cycloneive_lcell_comb \ula_|video_|Add0~18 ( -// Equation(s): -// \ula_|video_|Add0~18_combout = \ula_|video_|Add0~17 $ (\ula_|video_|vga_hc [9]) - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|vga_hc [9]), - .cin(\ula_|video_|Add0~17 ), - .combout(\ula_|video_|Add0~18_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Add0~18 .lut_mask = 16'h0FF0; -defparam \ula_|video_|Add0~18 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y33_N20 -cycloneive_lcell_comb \ula_|video_|vga_hc~1 ( -// Equation(s): -// \ula_|video_|vga_hc~1_combout = (\ula_|video_|Equal1~0_combout & \ula_|video_|Add0~18_combout ) - - .dataa(gnd), - .datab(\ula_|video_|Equal1~0_combout ), - .datac(gnd), - .datad(\ula_|video_|Add0~18_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_hc~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_hc~1 .lut_mask = 16'hCC00; -defparam \ula_|video_|vga_hc~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y33_N21 -dffeas \ula_|video_|vga_hc[9] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_hc~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_hc [9]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_hc[9] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_hc[9] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N2 -cycloneive_lcell_comb \ula_|video_|Add0~0 ( -// Equation(s): -// \ula_|video_|Add0~0_combout = \ula_|video_|vga_hc [0] $ (VCC) -// \ula_|video_|Add0~1 = CARRY(\ula_|video_|vga_hc [0]) - - .dataa(gnd), - .datab(\ula_|video_|vga_hc [0]), - .datac(gnd), - .datad(vcc), - .cin(gnd), - .combout(\ula_|video_|Add0~0_combout ), - .cout(\ula_|video_|Add0~1 )); -// synopsys translate_off -defparam \ula_|video_|Add0~0 .lut_mask = 16'h33CC; -defparam \ula_|video_|Add0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N0 -cycloneive_lcell_comb \ula_|video_|vga_hc~3 ( -// Equation(s): -// \ula_|video_|vga_hc~3_combout = (\ula_|video_|Add0~0_combout & \ula_|video_|Equal1~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|video_|Add0~0_combout ), - .datad(\ula_|video_|Equal1~0_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_hc~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_hc~3 .lut_mask = 16'hF000; -defparam \ula_|video_|vga_hc~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y31_N1 -dffeas \ula_|video_|vga_hc[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_hc~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_hc [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_hc[0] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_hc[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N4 -cycloneive_lcell_comb \ula_|video_|Add0~2 ( -// Equation(s): -// \ula_|video_|Add0~2_combout = (\ula_|video_|vga_hc [1] & (!\ula_|video_|Add0~1 )) # (!\ula_|video_|vga_hc [1] & ((\ula_|video_|Add0~1 ) # (GND))) -// \ula_|video_|Add0~3 = CARRY((!\ula_|video_|Add0~1 ) # (!\ula_|video_|vga_hc [1])) - - .dataa(gnd), - .datab(\ula_|video_|vga_hc [1]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add0~1 ), - .combout(\ula_|video_|Add0~2_combout ), - .cout(\ula_|video_|Add0~3 )); -// synopsys translate_off -defparam \ula_|video_|Add0~2 .lut_mask = 16'h3C3F; -defparam \ula_|video_|Add0~2 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y33_N16 -cycloneive_lcell_comb \ula_|video_|vga_hc[1]~feeder ( -// Equation(s): -// \ula_|video_|vga_hc[1]~feeder_combout = \ula_|video_|Add0~2_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|Add0~2_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_hc[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_hc[1]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|vga_hc[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y33_N17 -dffeas \ula_|video_|vga_hc[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_hc[1]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_hc [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_hc[1] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_hc[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N6 -cycloneive_lcell_comb \ula_|video_|Add0~4 ( -// Equation(s): -// \ula_|video_|Add0~4_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|Add0~3 $ (GND))) # (!\ula_|video_|vga_hc [2] & (!\ula_|video_|Add0~3 & VCC)) -// \ula_|video_|Add0~5 = CARRY((\ula_|video_|vga_hc [2] & !\ula_|video_|Add0~3 )) - - .dataa(gnd), - .datab(\ula_|video_|vga_hc [2]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add0~3 ), - .combout(\ula_|video_|Add0~4_combout ), - .cout(\ula_|video_|Add0~5 )); -// synopsys translate_off -defparam \ula_|video_|Add0~4 .lut_mask = 16'hC30C; -defparam \ula_|video_|Add0~4 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y33_N23 -dffeas \ula_|video_|vga_hc[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|Add0~4_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_hc [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_hc[2] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_hc[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N8 -cycloneive_lcell_comb \ula_|video_|Add0~6 ( -// Equation(s): -// \ula_|video_|Add0~6_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|Add0~5 )) # (!\ula_|video_|vga_hc [3] & ((\ula_|video_|Add0~5 ) # (GND))) -// \ula_|video_|Add0~7 = CARRY((!\ula_|video_|Add0~5 ) # (!\ula_|video_|vga_hc [3])) - - .dataa(gnd), - .datab(\ula_|video_|vga_hc [3]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add0~5 ), - .combout(\ula_|video_|Add0~6_combout ), - .cout(\ula_|video_|Add0~7 )); -// synopsys translate_off -defparam \ula_|video_|Add0~6 .lut_mask = 16'h3C3F; -defparam \ula_|video_|Add0~6 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y33_N8 -cycloneive_lcell_comb \ula_|video_|vga_hc[3]~feeder ( -// Equation(s): -// \ula_|video_|vga_hc[3]~feeder_combout = \ula_|video_|Add0~6_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|Add0~6_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_hc[3]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_hc[3]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|vga_hc[3]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y33_N9 -dffeas \ula_|video_|vga_hc[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_hc[3]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_hc [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_hc[3] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_hc[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N10 -cycloneive_lcell_comb \ula_|video_|Add0~8 ( -// Equation(s): -// \ula_|video_|Add0~8_combout = (\ula_|video_|vga_hc [4] & (\ula_|video_|Add0~7 $ (GND))) # (!\ula_|video_|vga_hc [4] & (!\ula_|video_|Add0~7 & VCC)) -// \ula_|video_|Add0~9 = CARRY((\ula_|video_|vga_hc [4] & !\ula_|video_|Add0~7 )) - - .dataa(\ula_|video_|vga_hc [4]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add0~7 ), - .combout(\ula_|video_|Add0~8_combout ), - .cout(\ula_|video_|Add0~9 )); -// synopsys translate_off -defparam \ula_|video_|Add0~8 .lut_mask = 16'hA50A; -defparam \ula_|video_|Add0~8 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y33_N31 -dffeas \ula_|video_|vga_hc[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|Add0~8_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_hc [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_hc[4] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_hc[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N18 -cycloneive_lcell_comb \ula_|video_|Equal0~0 ( -// Equation(s): -// \ula_|video_|Equal0~0_combout = (!\ula_|video_|vga_hc [2] & (!\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [1] & !\ula_|video_|vga_hc [0]))) - - .dataa(\ula_|video_|vga_hc [2]), - .datab(\ula_|video_|vga_hc [3]), - .datac(\ula_|video_|vga_hc [1]), - .datad(\ula_|video_|vga_hc [0]), - .cin(gnd), - .combout(\ula_|video_|Equal0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Equal0~0 .lut_mask = 16'h0001; -defparam \ula_|video_|Equal0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N30 -cycloneive_lcell_comb \ula_|video_|Equal0~1 ( -// Equation(s): -// \ula_|video_|Equal0~1_combout = (\ula_|video_|vga_hc [5] & (!\ula_|video_|vga_hc [7] & (!\ula_|video_|vga_hc [4] & \ula_|video_|Equal0~0_combout ))) - - .dataa(\ula_|video_|vga_hc [5]), - .datab(\ula_|video_|vga_hc [7]), - .datac(\ula_|video_|vga_hc [4]), - .datad(\ula_|video_|Equal0~0_combout ), - .cin(gnd), - .combout(\ula_|video_|Equal0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Equal0~1 .lut_mask = 16'h0200; -defparam \ula_|video_|Equal0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y33_N16 -cycloneive_lcell_comb \ula_|video_|Equal1~0 ( -// Equation(s): -// \ula_|video_|Equal1~0_combout = (((\ula_|video_|vga_hc [6]) # (!\ula_|video_|Equal0~1_combout )) # (!\ula_|video_|vga_hc [8])) # (!\ula_|video_|vga_hc [9]) - - .dataa(\ula_|video_|vga_hc [9]), - .datab(\ula_|video_|vga_hc [8]), - .datac(\ula_|video_|vga_hc [6]), - .datad(\ula_|video_|Equal0~1_combout ), - .cin(gnd), - .combout(\ula_|video_|Equal1~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Equal1~0 .lut_mask = 16'hF7FF; -defparam \ula_|video_|Equal1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N12 -cycloneive_lcell_comb \ula_|video_|Add0~10 ( -// Equation(s): -// \ula_|video_|Add0~10_combout = (\ula_|video_|vga_hc [5] & (!\ula_|video_|Add0~9 )) # (!\ula_|video_|vga_hc [5] & ((\ula_|video_|Add0~9 ) # (GND))) -// \ula_|video_|Add0~11 = CARRY((!\ula_|video_|Add0~9 ) # (!\ula_|video_|vga_hc [5])) - - .dataa(\ula_|video_|vga_hc [5]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add0~9 ), - .combout(\ula_|video_|Add0~10_combout ), - .cout(\ula_|video_|Add0~11 )); -// synopsys translate_off -defparam \ula_|video_|Add0~10 .lut_mask = 16'h5A5F; -defparam \ula_|video_|Add0~10 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N0 -cycloneive_lcell_comb \ula_|video_|vga_hc~0 ( -// Equation(s): -// \ula_|video_|vga_hc~0_combout = (\ula_|video_|Equal1~0_combout & \ula_|video_|Add0~10_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|video_|Equal1~0_combout ), - .datad(\ula_|video_|Add0~10_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_hc~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_hc~0 .lut_mask = 16'hF000; -defparam \ula_|video_|vga_hc~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y33_N1 -dffeas \ula_|video_|vga_hc[5] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_hc~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_hc [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_hc[5] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_hc[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N14 -cycloneive_lcell_comb \ula_|video_|Add0~12 ( -// Equation(s): -// \ula_|video_|Add0~12_combout = (\ula_|video_|vga_hc [6] & (\ula_|video_|Add0~11 $ (GND))) # (!\ula_|video_|vga_hc [6] & (!\ula_|video_|Add0~11 & VCC)) -// \ula_|video_|Add0~13 = CARRY((\ula_|video_|vga_hc [6] & !\ula_|video_|Add0~11 )) - - .dataa(\ula_|video_|vga_hc [6]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add0~11 ), - .combout(\ula_|video_|Add0~12_combout ), - .cout(\ula_|video_|Add0~13 )); -// synopsys translate_off -defparam \ula_|video_|Add0~12 .lut_mask = 16'hA50A; -defparam \ula_|video_|Add0~12 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y33_N29 -dffeas \ula_|video_|vga_hc[6] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|Add0~12_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_hc [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_hc[6] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_hc[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X39_Y33_N25 -dffeas \ula_|video_|vga_hc[7] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|Add0~14_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_hc [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_hc[7] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_hc[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y33_N0 -cycloneive_lcell_comb \ula_|video_|Add1~0 ( -// Equation(s): -// \ula_|video_|Add1~0_combout = \ula_|video_|vga_vc [0] $ (VCC) -// \ula_|video_|Add1~1 = CARRY(\ula_|video_|vga_vc [0]) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [0]), - .datac(gnd), - .datad(vcc), - .cin(gnd), - .combout(\ula_|video_|Add1~0_combout ), - .cout(\ula_|video_|Add1~1 )); -// synopsys translate_off -defparam \ula_|video_|Add1~0 .lut_mask = 16'h33CC; -defparam \ula_|video_|Add1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y33_N2 -cycloneive_lcell_comb \ula_|video_|Add1~2 ( -// Equation(s): -// \ula_|video_|Add1~2_combout = (\ula_|video_|vga_vc [1] & (!\ula_|video_|Add1~1 )) # (!\ula_|video_|vga_vc [1] & ((\ula_|video_|Add1~1 ) # (GND))) -// \ula_|video_|Add1~3 = CARRY((!\ula_|video_|Add1~1 ) # (!\ula_|video_|vga_vc [1])) - - .dataa(\ula_|video_|vga_vc [1]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add1~1 ), - .combout(\ula_|video_|Add1~2_combout ), - .cout(\ula_|video_|Add1~3 )); -// synopsys translate_off -defparam \ula_|video_|Add1~2 .lut_mask = 16'h5A5F; -defparam \ula_|video_|Add1~2 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y33_N4 -cycloneive_lcell_comb \ula_|video_|Add1~4 ( -// Equation(s): -// \ula_|video_|Add1~4_combout = (\ula_|video_|vga_vc [2] & (\ula_|video_|Add1~3 $ (GND))) # (!\ula_|video_|vga_vc [2] & (!\ula_|video_|Add1~3 & VCC)) -// \ula_|video_|Add1~5 = CARRY((\ula_|video_|vga_vc [2] & !\ula_|video_|Add1~3 )) - - .dataa(\ula_|video_|vga_vc [2]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add1~3 ), - .combout(\ula_|video_|Add1~4_combout ), - .cout(\ula_|video_|Add1~5 )); -// synopsys translate_off -defparam \ula_|video_|Add1~4 .lut_mask = 16'hA50A; -defparam \ula_|video_|Add1~4 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N12 -cycloneive_lcell_comb \ula_|video_|vga_vc[2]~2 ( -// Equation(s): -// \ula_|video_|vga_vc[2]~2_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [2]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~4_combout )))) - - .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Add1~4_combout ), - .datac(\ula_|video_|vga_vc [2]), - .datad(\ula_|video_|Equal3~1_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[2]~2 .lut_mask = 16'h00E4; -defparam \ula_|video_|vga_vc[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y33_N13 -dffeas \ula_|video_|vga_vc[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[2]~2_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[2] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y33_N6 -cycloneive_lcell_comb \ula_|video_|Add1~6 ( -// Equation(s): -// \ula_|video_|Add1~6_combout = (\ula_|video_|vga_vc [3] & (!\ula_|video_|Add1~5 )) # (!\ula_|video_|vga_vc [3] & ((\ula_|video_|Add1~5 ) # (GND))) -// \ula_|video_|Add1~7 = CARRY((!\ula_|video_|Add1~5 ) # (!\ula_|video_|vga_vc [3])) - - .dataa(\ula_|video_|vga_vc [3]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add1~5 ), - .combout(\ula_|video_|Add1~6_combout ), - .cout(\ula_|video_|Add1~7 )); -// synopsys translate_off -defparam \ula_|video_|Add1~6 .lut_mask = 16'h5A5F; -defparam \ula_|video_|Add1~6 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y33_N20 -cycloneive_lcell_comb \ula_|video_|vga_vc[3]~3 ( -// Equation(s): -// \ula_|video_|vga_vc[3]~3_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [3])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~6_combout ))))) - - .dataa(\ula_|video_|Equal3~1_combout ), - .datab(\ula_|video_|Equal1~0_combout ), - .datac(\ula_|video_|vga_vc [3]), - .datad(\ula_|video_|Add1~6_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[3]~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[3]~3 .lut_mask = 16'h5140; -defparam \ula_|video_|vga_vc[3]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y33_N3 -dffeas \ula_|video_|vga_vc[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|vga_vc[3]~3_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[3] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y33_N8 -cycloneive_lcell_comb \ula_|video_|Add1~8 ( -// Equation(s): -// \ula_|video_|Add1~8_combout = (\ula_|video_|vga_vc [4] & (\ula_|video_|Add1~7 $ (GND))) # (!\ula_|video_|vga_vc [4] & (!\ula_|video_|Add1~7 & VCC)) -// \ula_|video_|Add1~9 = CARRY((\ula_|video_|vga_vc [4] & !\ula_|video_|Add1~7 )) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [4]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add1~7 ), - .combout(\ula_|video_|Add1~8_combout ), - .cout(\ula_|video_|Add1~9 )); -// synopsys translate_off -defparam \ula_|video_|Add1~8 .lut_mask = 16'hC30C; -defparam \ula_|video_|Add1~8 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N20 -cycloneive_lcell_comb \ula_|video_|vga_vc[4]~5 ( -// Equation(s): -// \ula_|video_|vga_vc[4]~5_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [4]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~8_combout )))) - - .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Add1~8_combout ), - .datac(\ula_|video_|vga_vc [4]), - .datad(\ula_|video_|Equal3~1_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[4]~5_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[4]~5 .lut_mask = 16'h00E4; -defparam \ula_|video_|vga_vc[4]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y33_N21 -dffeas \ula_|video_|vga_vc[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[4]~5_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[4] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y33_N10 -cycloneive_lcell_comb \ula_|video_|Add1~10 ( -// Equation(s): -// \ula_|video_|Add1~10_combout = (\ula_|video_|vga_vc [5] & (!\ula_|video_|Add1~9 )) # (!\ula_|video_|vga_vc [5] & ((\ula_|video_|Add1~9 ) # (GND))) -// \ula_|video_|Add1~11 = CARRY((!\ula_|video_|Add1~9 ) # (!\ula_|video_|vga_vc [5])) - - .dataa(\ula_|video_|vga_vc [5]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add1~9 ), - .combout(\ula_|video_|Add1~10_combout ), - .cout(\ula_|video_|Add1~11 )); -// synopsys translate_off -defparam \ula_|video_|Add1~10 .lut_mask = 16'h5A5F; -defparam \ula_|video_|Add1~10 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y33_N22 -cycloneive_lcell_comb \ula_|video_|vga_vc[5]~8 ( -// Equation(s): -// \ula_|video_|vga_vc[5]~8_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [5])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~10_combout ))))) - - .dataa(\ula_|video_|Equal3~1_combout ), - .datab(\ula_|video_|Equal1~0_combout ), - .datac(\ula_|video_|vga_vc [5]), - .datad(\ula_|video_|Add1~10_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[5]~8_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[5]~8 .lut_mask = 16'h5140; -defparam \ula_|video_|vga_vc[5]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y33_N17 -dffeas \ula_|video_|vga_vc[5] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|vga_vc[5]~8_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[5] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y33_N12 -cycloneive_lcell_comb \ula_|video_|Add1~12 ( -// Equation(s): -// \ula_|video_|Add1~12_combout = (\ula_|video_|vga_vc [6] & (\ula_|video_|Add1~11 $ (GND))) # (!\ula_|video_|vga_vc [6] & (!\ula_|video_|Add1~11 & VCC)) -// \ula_|video_|Add1~13 = CARRY((\ula_|video_|vga_vc [6] & !\ula_|video_|Add1~11 )) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [6]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add1~11 ), - .combout(\ula_|video_|Add1~12_combout ), - .cout(\ula_|video_|Add1~13 )); -// synopsys translate_off -defparam \ula_|video_|Add1~12 .lut_mask = 16'hC30C; -defparam \ula_|video_|Add1~12 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N6 -cycloneive_lcell_comb \ula_|video_|vga_vc[6]~4 ( -// Equation(s): -// \ula_|video_|vga_vc[6]~4_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [6]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~12_combout )))) - - .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Add1~12_combout ), - .datac(\ula_|video_|vga_vc [6]), - .datad(\ula_|video_|Equal3~1_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[6]~4_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[6]~4 .lut_mask = 16'h00E4; -defparam \ula_|video_|vga_vc[6]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y33_N7 -dffeas \ula_|video_|vga_vc[6] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[6]~4_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[6] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y33_N14 -cycloneive_lcell_comb \ula_|video_|Add1~14 ( -// Equation(s): -// \ula_|video_|Add1~14_combout = (\ula_|video_|vga_vc [7] & (!\ula_|video_|Add1~13 )) # (!\ula_|video_|vga_vc [7] & ((\ula_|video_|Add1~13 ) # (GND))) -// \ula_|video_|Add1~15 = CARRY((!\ula_|video_|Add1~13 ) # (!\ula_|video_|vga_vc [7])) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [7]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add1~13 ), - .combout(\ula_|video_|Add1~14_combout ), - .cout(\ula_|video_|Add1~15 )); -// synopsys translate_off -defparam \ula_|video_|Add1~14 .lut_mask = 16'h3C3F; -defparam \ula_|video_|Add1~14 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N14 -cycloneive_lcell_comb \ula_|video_|vga_vc[7]~6 ( -// Equation(s): -// \ula_|video_|vga_vc[7]~6_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [7]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~14_combout )))) - - .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Add1~14_combout ), - .datac(\ula_|video_|vga_vc [7]), - .datad(\ula_|video_|Equal3~1_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[7]~6_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[7]~6 .lut_mask = 16'h00E4; -defparam \ula_|video_|vga_vc[7]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y33_N15 -dffeas \ula_|video_|vga_vc[7] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[7]~6_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[7] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y33_N16 -cycloneive_lcell_comb \ula_|video_|Add1~16 ( -// Equation(s): -// \ula_|video_|Add1~16_combout = (\ula_|video_|vga_vc [8] & (\ula_|video_|Add1~15 $ (GND))) # (!\ula_|video_|vga_vc [8] & (!\ula_|video_|Add1~15 & VCC)) -// \ula_|video_|Add1~17 = CARRY((\ula_|video_|vga_vc [8] & !\ula_|video_|Add1~15 )) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [8]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add1~15 ), - .combout(\ula_|video_|Add1~16_combout ), - .cout(\ula_|video_|Add1~17 )); -// synopsys translate_off -defparam \ula_|video_|Add1~16 .lut_mask = 16'hC30C; -defparam \ula_|video_|Add1~16 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N24 -cycloneive_lcell_comb \ula_|video_|vga_vc[8]~7 ( -// Equation(s): -// \ula_|video_|vga_vc[8]~7_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [8]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~16_combout )))) - - .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Add1~16_combout ), - .datac(\ula_|video_|vga_vc [8]), - .datad(\ula_|video_|Equal3~1_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[8]~7_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[8]~7 .lut_mask = 16'h00E4; -defparam \ula_|video_|vga_vc[8]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y33_N25 -dffeas \ula_|video_|vga_vc[8] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[8]~7_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [8]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[8] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y33_N18 -cycloneive_lcell_comb \ula_|video_|Add1~18 ( -// Equation(s): -// \ula_|video_|Add1~18_combout = \ula_|video_|Add1~17 $ (\ula_|video_|vga_vc [9]) - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|vga_vc [9]), - .cin(\ula_|video_|Add1~17 ), - .combout(\ula_|video_|Add1~18_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Add1~18 .lut_mask = 16'h0FF0; -defparam \ula_|video_|Add1~18 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N10 -cycloneive_lcell_comb \ula_|video_|vga_vc[9]~9 ( -// Equation(s): -// \ula_|video_|vga_vc[9]~9_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [9]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~18_combout )))) - - .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Add1~18_combout ), - .datac(\ula_|video_|vga_vc [9]), - .datad(\ula_|video_|Equal3~1_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[9]~9_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[9]~9 .lut_mask = 16'h00E4; -defparam \ula_|video_|vga_vc[9]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y33_N11 -dffeas \ula_|video_|vga_vc[9] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[9]~9_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [9]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[9] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[9] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N18 -cycloneive_lcell_comb \ula_|video_|Equal2~0 ( -// Equation(s): -// \ula_|video_|Equal2~0_combout = (!\ula_|video_|vga_vc [6] & (!\ula_|video_|vga_vc [4] & (!\ula_|video_|vga_vc [7] & !\ula_|video_|vga_vc [8]))) - - .dataa(\ula_|video_|vga_vc [6]), - .datab(\ula_|video_|vga_vc [4]), - .datac(\ula_|video_|vga_vc [7]), - .datad(\ula_|video_|vga_vc [8]), - .cin(gnd), - .combout(\ula_|video_|Equal2~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Equal2~0 .lut_mask = 16'h0001; -defparam \ula_|video_|Equal2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y33_N30 -cycloneive_lcell_comb \ula_|video_|Equal3~0 ( -// Equation(s): -// \ula_|video_|Equal3~0_combout = (\ula_|video_|vga_vc [3] & (\ula_|video_|vga_vc [2] & (!\ula_|video_|vga_vc [1] & \ula_|video_|vga_vc [0]))) - - .dataa(\ula_|video_|vga_vc [3]), - .datab(\ula_|video_|vga_vc [2]), - .datac(\ula_|video_|vga_vc [1]), - .datad(\ula_|video_|vga_vc [0]), - .cin(gnd), - .combout(\ula_|video_|Equal3~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Equal3~0 .lut_mask = 16'h0800; -defparam \ula_|video_|Equal3~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y33_N18 -cycloneive_lcell_comb \ula_|video_|Equal3~1 ( -// Equation(s): -// \ula_|video_|Equal3~1_combout = (!\ula_|video_|vga_vc [5] & (\ula_|video_|vga_vc [9] & (\ula_|video_|Equal2~0_combout & \ula_|video_|Equal3~0_combout ))) - - .dataa(\ula_|video_|vga_vc [5]), - .datab(\ula_|video_|vga_vc [9]), - .datac(\ula_|video_|Equal2~0_combout ), - .datad(\ula_|video_|Equal3~0_combout ), - .cin(gnd), - .combout(\ula_|video_|Equal3~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Equal3~1 .lut_mask = 16'h4000; -defparam \ula_|video_|Equal3~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N28 -cycloneive_lcell_comb \ula_|video_|vga_vc[0]~0 ( -// Equation(s): -// \ula_|video_|vga_vc[0]~0_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [0]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~0_combout )))) - - .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Add1~0_combout ), - .datac(\ula_|video_|vga_vc [0]), - .datad(\ula_|video_|Equal3~1_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[0]~0 .lut_mask = 16'h00E4; -defparam \ula_|video_|vga_vc[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y33_N29 -dffeas \ula_|video_|vga_vc[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[0]~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[0] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N22 -cycloneive_lcell_comb \ula_|video_|vga_vc[1]~1 ( -// Equation(s): -// \ula_|video_|vga_vc[1]~1_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [1]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~2_combout )))) - - .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Add1~2_combout ), - .datac(\ula_|video_|vga_vc [1]), - .datad(\ula_|video_|Equal3~1_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[1]~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[1]~1 .lut_mask = 16'h00E4; -defparam \ula_|video_|vga_vc[1]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y33_N23 -dffeas \ula_|video_|vga_vc[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[1]~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[1] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[1] .power_up = "low"; -// synopsys translate_on - -// Location: IOIBUF_X27_Y0_N15 -cycloneive_io_ibuf \SW[1]~input ( - .i(SW[1]), - .ibar(gnd), - .o(\SW[1]~input_o )); -// synopsys translate_off -defparam \SW[1]~input .bus_hold = "false"; -defparam \SW[1]~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N30 -cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_13~0 ( -// Equation(s): -// \z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout = (!\ula_|video_|vga_hc [8] & (!\ula_|video_|vga_vc [1] & (!\SW[1]~input_o & !\ula_|video_|vga_hc [9]))) - - .dataa(\ula_|video_|vga_hc [8]), - .datab(\ula_|video_|vga_vc [1]), - .datac(\SW[1]~input_o ), - .datad(\ula_|video_|vga_hc [9]), - .cin(gnd), - .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13~0 .lut_mask = 16'h0001; -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N30 +// Location: LCCOMB_X29_Y17_N26 cycloneive_lcell_comb \z80_|pla_decode_|Equal79~0 ( // Equation(s): -// \z80_|pla_decode_|Equal79~0_combout = (\z80_|pla_decode_|Equal1~7_combout & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4]))) +// \z80_|pla_decode_|Equal79~0_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal1~7_combout & \z80_|ir_|opcode [4]))) - .dataa(\z80_|pla_decode_|Equal1~7_combout ), + .dataa(\z80_|ir_|opcode [5]), .datab(\z80_|pla_decode_|Equal2~0_combout ), - .datac(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal1~7_combout ), .datad(\z80_|ir_|opcode [4]), .cin(gnd), .combout(\z80_|pla_decode_|Equal79~0_combout ), @@ -18903,38 +4790,56 @@ defparam \z80_|pla_decode_|Equal79~0 .lut_mask = 16'h8000; defparam \z80_|pla_decode_|Equal79~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y17_N16 +// Location: LCCOMB_X29_Y17_N12 +cycloneive_lcell_comb \z80_|interrupts_|iff1~0 ( +// Equation(s): +// \z80_|interrupts_|iff1~0_combout = (\z80_|pla_decode_|Equal79~0_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|ir_|opcode [3]))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|interrupts_|iff1~q )))) # +// (!\z80_|pla_decode_|Equal79~0_combout & (((\z80_|interrupts_|iff1~q )))) + + .dataa(\z80_|pla_decode_|Equal79~0_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|interrupts_|iff1~q ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|interrupts_|iff1~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|iff1~0 .lut_mask = 16'hF870; +defparam \z80_|interrupts_|iff1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N30 cycloneive_lcell_comb \z80_|interrupts_|DFFE_instIFF2~0 ( // Equation(s): -// \z80_|interrupts_|DFFE_instIFF2~0_combout = (\z80_|pla_decode_|Equal79~0_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|ir_|opcode [3])) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|interrupts_|DFFE_instIFF2~q -// ))))) # (!\z80_|pla_decode_|Equal79~0_combout & (((\z80_|interrupts_|DFFE_instIFF2~q )))) +// \z80_|interrupts_|DFFE_instIFF2~0_combout = (\z80_|pla_decode_|Equal79~0_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|ir_|opcode [3]))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|interrupts_|DFFE_instIFF2~q +// )))) # (!\z80_|pla_decode_|Equal79~0_combout & (((\z80_|interrupts_|DFFE_instIFF2~q )))) - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal79~0_combout ), + .dataa(\z80_|pla_decode_|Equal79~0_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), .datac(\z80_|interrupts_|DFFE_instIFF2~q ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|ir_|opcode [3]), .cin(gnd), .combout(\z80_|interrupts_|DFFE_instIFF2~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|interrupts_|DFFE_instIFF2~0 .lut_mask = 16'hB8F0; +defparam \z80_|interrupts_|DFFE_instIFF2~0 .lut_mask = 16'hF870; defparam \z80_|interrupts_|DFFE_instIFF2~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y15_N28 +// Location: LCCOMB_X27_Y11_N24 cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_12 ( // Equation(s): -// \z80_|interrupts_|SYNTHESIZED_WIRE_12~combout = ((!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & \z80_|interrupts_|DFFE_inst44~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) +// \z80_|interrupts_|SYNTHESIZED_WIRE_12~combout = ((\z80_|interrupts_|DFFE_inst44~q & !\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|interrupts_|DFFE_inst44~q ), .datac(gnd), - .datad(\z80_|interrupts_|DFFE_inst44~q ), + .datad(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), .cin(gnd), .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_12~combout ), .cout()); // synopsys translate_off -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12 .lut_mask = 16'h7733; +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12 .lut_mask = 16'h55DD; defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12 .sum_lutc_input = "datac"; // synopsys translate_on @@ -18951,7 +4856,7 @@ defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl .clock_type = "global clo defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: FF_X35_Y17_N17 +// Location: FF_X29_Y17_N31 dffeas \z80_|interrupts_|DFFE_instIFF2 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|interrupts_|DFFE_instIFF2~0_combout ), @@ -18970,60 +4875,76 @@ defparam \z80_|interrupts_|DFFE_instIFF2 .is_wysiwyg = "true"; defparam \z80_|interrupts_|DFFE_instIFF2 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X35_Y17_N2 -cycloneive_lcell_comb \z80_|interrupts_|iff1~0 ( +// Location: LCCOMB_X29_Y13_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal13~0 ( // Equation(s): -// \z80_|interrupts_|iff1~0_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|pla_decode_|Equal79~0_combout & ((\z80_|ir_|opcode [3]))) # (!\z80_|pla_decode_|Equal79~0_combout & (\z80_|interrupts_|iff1~q )))) # -// (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|interrupts_|iff1~q )) +// \z80_|pla_decode_|Equal13~0_combout = (\z80_|decode_state_|DFFE_instED~q & (!\z80_|ir_|opcode [7] & \z80_|ir_|opcode [6])) - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|interrupts_|iff1~q ), - .datac(\z80_|pla_decode_|Equal79~0_combout ), - .datad(\z80_|ir_|opcode [3]), + .dataa(\z80_|decode_state_|DFFE_instED~q ), + .datab(gnd), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|ir_|opcode [6]), .cin(gnd), - .combout(\z80_|interrupts_|iff1~0_combout ), + .combout(\z80_|pla_decode_|Equal13~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|interrupts_|iff1~0 .lut_mask = 16'hEC4C; -defparam \z80_|interrupts_|iff1~0 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal13~0 .lut_mask = 16'h0A00; +defparam \z80_|pla_decode_|Equal13~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y17_N18 +// Location: LCCOMB_X21_Y16_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal38~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal38~2_combout = (\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [1] & \z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal38~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal38~2 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal38~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N0 cycloneive_lcell_comb \z80_|interrupts_|iff1~1 ( // Equation(s): -// \z80_|interrupts_|iff1~1_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|pla_decode_|Equal38~2_combout & (\z80_|interrupts_|DFFE_instIFF2~q )) # (!\z80_|pla_decode_|Equal38~2_combout & ((\z80_|interrupts_|iff1~0_combout ))))) # -// (!\z80_|execute_|ctl_eval_cond~0_combout & (((\z80_|interrupts_|iff1~0_combout )))) +// \z80_|interrupts_|iff1~1_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|pla_decode_|Equal38~2_combout & ((\z80_|interrupts_|DFFE_instIFF2~q ))) # (!\z80_|pla_decode_|Equal38~2_combout & (\z80_|interrupts_|iff1~0_combout )))) # +// (!\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|interrupts_|iff1~0_combout )) - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|interrupts_|DFFE_instIFF2~q ), - .datac(\z80_|pla_decode_|Equal38~2_combout ), - .datad(\z80_|interrupts_|iff1~0_combout ), + .dataa(\z80_|interrupts_|iff1~0_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|interrupts_|DFFE_instIFF2~q ), + .datad(\z80_|pla_decode_|Equal38~2_combout ), .cin(gnd), .combout(\z80_|interrupts_|iff1~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|interrupts_|iff1~1 .lut_mask = 16'hDF80; +defparam \z80_|interrupts_|iff1~1 .lut_mask = 16'hE2AA; defparam \z80_|interrupts_|iff1~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y18_N12 +// Location: LCCOMB_X28_Y13_N20 cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_15 ( // Equation(s): -// \z80_|interrupts_|SYNTHESIZED_WIRE_15~combout = ((\z80_|interrupts_|DFFE_inst44~q ) # (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) +// \z80_|interrupts_|SYNTHESIZED_WIRE_15~combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # ((\z80_|interrupts_|DFFE_inst44~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(gnd), .datac(\z80_|interrupts_|DFFE_inst44~q ), - .datad(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .cin(gnd), .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_15~combout ), .cout()); // synopsys translate_off -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_15 .lut_mask = 16'hFFF3; +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_15 .lut_mask = 16'hFAFF; defparam \z80_|interrupts_|SYNTHESIZED_WIRE_15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X35_Y17_N19 +// Location: FF_X29_Y17_N1 dffeas \z80_|interrupts_|iff1 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|interrupts_|iff1~1_combout ), @@ -19042,14 +4963,1122 @@ defparam \z80_|interrupts_|iff1 .is_wysiwyg = "true"; defparam \z80_|interrupts_|iff1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X37_Y33_N4 -cycloneive_lcell_comb \ula_|video_|Equal2~1 ( +// Location: CLKCTRL_G18 +cycloneive_clkctrl \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk [0]}), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk )); +// synopsys translate_off +defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .clock_type = "global clock"; +defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y32_N6 +cycloneive_lcell_comb \ula_|video_|Add0~0 ( // Equation(s): -// \ula_|video_|Equal2~1_combout = (!\ula_|video_|vga_vc [3] & (!\ula_|video_|vga_vc [2] & (!\ula_|video_|vga_vc [9] & !\ula_|video_|vga_vc [0]))) +// \ula_|video_|Add0~0_combout = \ula_|video_|vga_hc [0] $ (VCC) +// \ula_|video_|Add0~1 = CARRY(\ula_|video_|vga_hc [0]) + + .dataa(gnd), + .datab(\ula_|video_|vga_hc [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\ula_|video_|Add0~0_combout ), + .cout(\ula_|video_|Add0~1 )); +// synopsys translate_off +defparam \ula_|video_|Add0~0 .lut_mask = 16'h33CC; +defparam \ula_|video_|Add0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y32_N28 +cycloneive_lcell_comb \ula_|video_|vga_hc~3 ( +// Equation(s): +// \ula_|video_|vga_hc~3_combout = (\ula_|video_|Add0~0_combout & \ula_|video_|Equal1~0_combout ) + + .dataa(gnd), + .datab(\ula_|video_|Add0~0_combout ), + .datac(gnd), + .datad(\ula_|video_|Equal1~0_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_hc~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_hc~3 .lut_mask = 16'hCC00; +defparam \ula_|video_|vga_hc~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y32_N13 +dffeas \ula_|video_|vga_hc[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|vga_hc~3_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_hc [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_hc[0] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_hc[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y32_N8 +cycloneive_lcell_comb \ula_|video_|Add0~2 ( +// Equation(s): +// \ula_|video_|Add0~2_combout = (\ula_|video_|vga_hc [1] & (!\ula_|video_|Add0~1 )) # (!\ula_|video_|vga_hc [1] & ((\ula_|video_|Add0~1 ) # (GND))) +// \ula_|video_|Add0~3 = CARRY((!\ula_|video_|Add0~1 ) # (!\ula_|video_|vga_hc [1])) + + .dataa(gnd), + .datab(\ula_|video_|vga_hc [1]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add0~1 ), + .combout(\ula_|video_|Add0~2_combout ), + .cout(\ula_|video_|Add0~3 )); +// synopsys translate_off +defparam \ula_|video_|Add0~2 .lut_mask = 16'h3C3F; +defparam \ula_|video_|Add0~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X35_Y32_N25 +dffeas \ula_|video_|vga_hc[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|Add0~2_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_hc [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_hc[1] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_hc[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y32_N10 +cycloneive_lcell_comb \ula_|video_|Add0~4 ( +// Equation(s): +// \ula_|video_|Add0~4_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|Add0~3 $ (GND))) # (!\ula_|video_|vga_hc [2] & (!\ula_|video_|Add0~3 & VCC)) +// \ula_|video_|Add0~5 = CARRY((\ula_|video_|vga_hc [2] & !\ula_|video_|Add0~3 )) + + .dataa(gnd), + .datab(\ula_|video_|vga_hc [2]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add0~3 ), + .combout(\ula_|video_|Add0~4_combout ), + .cout(\ula_|video_|Add0~5 )); +// synopsys translate_off +defparam \ula_|video_|Add0~4 .lut_mask = 16'hC30C; +defparam \ula_|video_|Add0~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X35_Y32_N3 +dffeas \ula_|video_|vga_hc[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|Add0~4_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_hc [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_hc[2] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_hc[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y32_N12 +cycloneive_lcell_comb \ula_|video_|Add0~6 ( +// Equation(s): +// \ula_|video_|Add0~6_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|Add0~5 )) # (!\ula_|video_|vga_hc [3] & ((\ula_|video_|Add0~5 ) # (GND))) +// \ula_|video_|Add0~7 = CARRY((!\ula_|video_|Add0~5 ) # (!\ula_|video_|vga_hc [3])) + + .dataa(\ula_|video_|vga_hc [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add0~5 ), + .combout(\ula_|video_|Add0~6_combout ), + .cout(\ula_|video_|Add0~7 )); +// synopsys translate_off +defparam \ula_|video_|Add0~6 .lut_mask = 16'h5A5F; +defparam \ula_|video_|Add0~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X34_Y32_N21 +dffeas \ula_|video_|vga_hc[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|Add0~6_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_hc [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_hc[3] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_hc[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y32_N14 +cycloneive_lcell_comb \ula_|video_|Add0~8 ( +// Equation(s): +// \ula_|video_|Add0~8_combout = (\ula_|video_|vga_hc [4] & (\ula_|video_|Add0~7 $ (GND))) # (!\ula_|video_|vga_hc [4] & (!\ula_|video_|Add0~7 & VCC)) +// \ula_|video_|Add0~9 = CARRY((\ula_|video_|vga_hc [4] & !\ula_|video_|Add0~7 )) + + .dataa(\ula_|video_|vga_hc [4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add0~7 ), + .combout(\ula_|video_|Add0~8_combout ), + .cout(\ula_|video_|Add0~9 )); +// synopsys translate_off +defparam \ula_|video_|Add0~8 .lut_mask = 16'hA50A; +defparam \ula_|video_|Add0~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X34_Y32_N3 +dffeas \ula_|video_|vga_hc[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|Add0~8_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_hc [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_hc[4] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_hc[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y32_N16 +cycloneive_lcell_comb \ula_|video_|Add0~10 ( +// Equation(s): +// \ula_|video_|Add0~10_combout = (\ula_|video_|vga_hc [5] & (!\ula_|video_|Add0~9 )) # (!\ula_|video_|vga_hc [5] & ((\ula_|video_|Add0~9 ) # (GND))) +// \ula_|video_|Add0~11 = CARRY((!\ula_|video_|Add0~9 ) # (!\ula_|video_|vga_hc [5])) + + .dataa(gnd), + .datab(\ula_|video_|vga_hc [5]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add0~9 ), + .combout(\ula_|video_|Add0~10_combout ), + .cout(\ula_|video_|Add0~11 )); +// synopsys translate_off +defparam \ula_|video_|Add0~10 .lut_mask = 16'h3C3F; +defparam \ula_|video_|Add0~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y32_N26 +cycloneive_lcell_comb \ula_|video_|vga_hc~0 ( +// Equation(s): +// \ula_|video_|vga_hc~0_combout = (\ula_|video_|Add0~10_combout & \ula_|video_|Equal1~0_combout ) + + .dataa(gnd), + .datab(\ula_|video_|Add0~10_combout ), + .datac(gnd), + .datad(\ula_|video_|Equal1~0_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_hc~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_hc~0 .lut_mask = 16'hCC00; +defparam \ula_|video_|vga_hc~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y32_N29 +dffeas \ula_|video_|vga_hc[5] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|vga_hc~0_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_hc [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_hc[5] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_hc[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y32_N18 +cycloneive_lcell_comb \ula_|video_|Add0~12 ( +// Equation(s): +// \ula_|video_|Add0~12_combout = (\ula_|video_|vga_hc [6] & (\ula_|video_|Add0~11 $ (GND))) # (!\ula_|video_|vga_hc [6] & (!\ula_|video_|Add0~11 & VCC)) +// \ula_|video_|Add0~13 = CARRY((\ula_|video_|vga_hc [6] & !\ula_|video_|Add0~11 )) + + .dataa(\ula_|video_|vga_hc [6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add0~11 ), + .combout(\ula_|video_|Add0~12_combout ), + .cout(\ula_|video_|Add0~13 )); +// synopsys translate_off +defparam \ula_|video_|Add0~12 .lut_mask = 16'hA50A; +defparam \ula_|video_|Add0~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X34_Y32_N5 +dffeas \ula_|video_|vga_hc[6] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|Add0~12_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_hc [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_hc[6] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_hc[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y32_N20 +cycloneive_lcell_comb \ula_|video_|Add0~14 ( +// Equation(s): +// \ula_|video_|Add0~14_combout = (\ula_|video_|vga_hc [7] & (!\ula_|video_|Add0~13 )) # (!\ula_|video_|vga_hc [7] & ((\ula_|video_|Add0~13 ) # (GND))) +// \ula_|video_|Add0~15 = CARRY((!\ula_|video_|Add0~13 ) # (!\ula_|video_|vga_hc [7])) + + .dataa(gnd), + .datab(\ula_|video_|vga_hc [7]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add0~13 ), + .combout(\ula_|video_|Add0~14_combout ), + .cout(\ula_|video_|Add0~15 )); +// synopsys translate_off +defparam \ula_|video_|Add0~14 .lut_mask = 16'h3C3F; +defparam \ula_|video_|Add0~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X34_Y32_N27 +dffeas \ula_|video_|vga_hc[7] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|Add0~14_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_hc [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_hc[7] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_hc[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y32_N22 +cycloneive_lcell_comb \ula_|video_|Add0~16 ( +// Equation(s): +// \ula_|video_|Add0~16_combout = (\ula_|video_|vga_hc [8] & (\ula_|video_|Add0~15 $ (GND))) # (!\ula_|video_|vga_hc [8] & (!\ula_|video_|Add0~15 & VCC)) +// \ula_|video_|Add0~17 = CARRY((\ula_|video_|vga_hc [8] & !\ula_|video_|Add0~15 )) + + .dataa(gnd), + .datab(\ula_|video_|vga_hc [8]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add0~15 ), + .combout(\ula_|video_|Add0~16_combout ), + .cout(\ula_|video_|Add0~17 )); +// synopsys translate_off +defparam \ula_|video_|Add0~16 .lut_mask = 16'hC30C; +defparam \ula_|video_|Add0~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y32_N2 +cycloneive_lcell_comb \ula_|video_|vga_hc~2 ( +// Equation(s): +// \ula_|video_|vga_hc~2_combout = (\ula_|video_|Add0~16_combout & \ula_|video_|Equal1~0_combout ) + + .dataa(gnd), + .datab(\ula_|video_|Add0~16_combout ), + .datac(gnd), + .datad(\ula_|video_|Equal1~0_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_hc~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_hc~2 .lut_mask = 16'hCC00; +defparam \ula_|video_|vga_hc~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y32_N27 +dffeas \ula_|video_|vga_hc[8] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|vga_hc~2_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_hc [8]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_hc[8] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_hc[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y32_N24 +cycloneive_lcell_comb \ula_|video_|Add0~18 ( +// Equation(s): +// \ula_|video_|Add0~18_combout = \ula_|video_|Add0~17 $ (\ula_|video_|vga_hc [9]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|vga_hc [9]), + .cin(\ula_|video_|Add0~17 ), + .combout(\ula_|video_|Add0~18_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Add0~18 .lut_mask = 16'h0FF0; +defparam \ula_|video_|Add0~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y32_N4 +cycloneive_lcell_comb \ula_|video_|vga_hc~1 ( +// Equation(s): +// \ula_|video_|vga_hc~1_combout = (\ula_|video_|Add0~18_combout & \ula_|video_|Equal1~0_combout ) + + .dataa(\ula_|video_|Add0~18_combout ), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|Equal1~0_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_hc~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_hc~1 .lut_mask = 16'hAA00; +defparam \ula_|video_|vga_hc~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y32_N1 +dffeas \ula_|video_|vga_hc[9] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|vga_hc~1_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_hc [9]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_hc[9] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_hc[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y31_N14 +cycloneive_lcell_comb \ula_|video_|Equal0~0 ( +// Equation(s): +// \ula_|video_|Equal0~0_combout = (!\ula_|video_|vga_hc [1] & (!\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [2] & !\ula_|video_|vga_hc [0]))) + + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|vga_hc [3]), + .datac(\ula_|video_|vga_hc [2]), + .datad(\ula_|video_|vga_hc [0]), + .cin(gnd), + .combout(\ula_|video_|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Equal0~0 .lut_mask = 16'h0001; +defparam \ula_|video_|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y31_N24 +cycloneive_lcell_comb \ula_|video_|Equal0~1 ( +// Equation(s): +// \ula_|video_|Equal0~1_combout = (!\ula_|video_|vga_hc [4] & (!\ula_|video_|vga_hc [7] & (\ula_|video_|Equal0~0_combout & \ula_|video_|vga_hc [5]))) + + .dataa(\ula_|video_|vga_hc [4]), + .datab(\ula_|video_|vga_hc [7]), + .datac(\ula_|video_|Equal0~0_combout ), + .datad(\ula_|video_|vga_hc [5]), + .cin(gnd), + .combout(\ula_|video_|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Equal0~1 .lut_mask = 16'h1000; +defparam \ula_|video_|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y31_N8 +cycloneive_lcell_comb \ula_|video_|Equal1~0 ( +// Equation(s): +// \ula_|video_|Equal1~0_combout = ((\ula_|video_|vga_hc [6]) # ((!\ula_|video_|Equal0~1_combout ) # (!\ula_|video_|vga_hc [8]))) # (!\ula_|video_|vga_hc [9]) + + .dataa(\ula_|video_|vga_hc [9]), + .datab(\ula_|video_|vga_hc [6]), + .datac(\ula_|video_|vga_hc [8]), + .datad(\ula_|video_|Equal0~1_combout ), + .cin(gnd), + .combout(\ula_|video_|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Equal1~0 .lut_mask = 16'hDFFF; +defparam \ula_|video_|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y31_N2 +cycloneive_lcell_comb \ula_|video_|Add1~0 ( +// Equation(s): +// \ula_|video_|Add1~0_combout = \ula_|video_|vga_vc [0] $ (VCC) +// \ula_|video_|Add1~1 = CARRY(\ula_|video_|vga_vc [0]) + + .dataa(\ula_|video_|vga_vc [0]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\ula_|video_|Add1~0_combout ), + .cout(\ula_|video_|Add1~1 )); +// synopsys translate_off +defparam \ula_|video_|Add1~0 .lut_mask = 16'h55AA; +defparam \ula_|video_|Add1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y31_N28 +cycloneive_lcell_comb \ula_|video_|vga_vc[0]~0 ( +// Equation(s): +// \ula_|video_|vga_vc[0]~0_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [0]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~0_combout )))) + + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Equal3~1_combout ), + .datac(\ula_|video_|Add1~0_combout ), + .datad(\ula_|video_|vga_vc [0]), + .cin(gnd), + .combout(\ula_|video_|vga_vc[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[0]~0 .lut_mask = 16'h3210; +defparam \ula_|video_|vga_vc[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y32_N29 +dffeas \ula_|video_|vga_vc[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|vga_vc[0]~0_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[0] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y31_N4 +cycloneive_lcell_comb \ula_|video_|Add1~2 ( +// Equation(s): +// \ula_|video_|Add1~2_combout = (\ula_|video_|vga_vc [1] & (!\ula_|video_|Add1~1 )) # (!\ula_|video_|vga_vc [1] & ((\ula_|video_|Add1~1 ) # (GND))) +// \ula_|video_|Add1~3 = CARRY((!\ula_|video_|Add1~1 ) # (!\ula_|video_|vga_vc [1])) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [1]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add1~1 ), + .combout(\ula_|video_|Add1~2_combout ), + .cout(\ula_|video_|Add1~3 )); +// synopsys translate_off +defparam \ula_|video_|Add1~2 .lut_mask = 16'h3C3F; +defparam \ula_|video_|Add1~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y32_N10 +cycloneive_lcell_comb \ula_|video_|vga_vc[1]~1 ( +// Equation(s): +// \ula_|video_|vga_vc[1]~1_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [1]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~2_combout )))) + + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Add1~2_combout ), + .datac(\ula_|video_|vga_vc [1]), + .datad(\ula_|video_|Equal3~1_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[1]~1 .lut_mask = 16'h00E4; +defparam \ula_|video_|vga_vc[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y32_N11 +dffeas \ula_|video_|vga_vc[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[1]~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[1] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y31_N6 +cycloneive_lcell_comb \ula_|video_|Add1~4 ( +// Equation(s): +// \ula_|video_|Add1~4_combout = (\ula_|video_|vga_vc [2] & (\ula_|video_|Add1~3 $ (GND))) # (!\ula_|video_|vga_vc [2] & (!\ula_|video_|Add1~3 & VCC)) +// \ula_|video_|Add1~5 = CARRY((\ula_|video_|vga_vc [2] & !\ula_|video_|Add1~3 )) + + .dataa(\ula_|video_|vga_vc [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add1~3 ), + .combout(\ula_|video_|Add1~4_combout ), + .cout(\ula_|video_|Add1~5 )); +// synopsys translate_off +defparam \ula_|video_|Add1~4 .lut_mask = 16'hA50A; +defparam \ula_|video_|Add1~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y31_N22 +cycloneive_lcell_comb \ula_|video_|vga_vc[2]~2 ( +// Equation(s): +// \ula_|video_|vga_vc[2]~2_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [2])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~4_combout ))))) + + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Equal3~1_combout ), + .datac(\ula_|video_|vga_vc [2]), + .datad(\ula_|video_|Add1~4_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[2]~2 .lut_mask = 16'h3120; +defparam \ula_|video_|vga_vc[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y32_N24 +cycloneive_lcell_comb \ula_|video_|vga_vc[2]~feeder ( +// Equation(s): +// \ula_|video_|vga_vc[2]~feeder_combout = \ula_|video_|vga_vc[2]~2_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|vga_vc[2]~2_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[2]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|vga_vc[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y32_N25 +dffeas \ula_|video_|vga_vc[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[2] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y31_N8 +cycloneive_lcell_comb \ula_|video_|Add1~6 ( +// Equation(s): +// \ula_|video_|Add1~6_combout = (\ula_|video_|vga_vc [3] & (!\ula_|video_|Add1~5 )) # (!\ula_|video_|vga_vc [3] & ((\ula_|video_|Add1~5 ) # (GND))) +// \ula_|video_|Add1~7 = CARRY((!\ula_|video_|Add1~5 ) # (!\ula_|video_|vga_vc [3])) .dataa(\ula_|video_|vga_vc [3]), - .datab(\ula_|video_|vga_vc [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add1~5 ), + .combout(\ula_|video_|Add1~6_combout ), + .cout(\ula_|video_|Add1~7 )); +// synopsys translate_off +defparam \ula_|video_|Add1~6 .lut_mask = 16'h5A5F; +defparam \ula_|video_|Add1~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y31_N24 +cycloneive_lcell_comb \ula_|video_|vga_vc[3]~3 ( +// Equation(s): +// \ula_|video_|vga_vc[3]~3_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [3])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~6_combout ))))) + + .dataa(\ula_|video_|vga_vc [3]), + .datab(\ula_|video_|Equal3~1_combout ), + .datac(\ula_|video_|Add1~6_combout ), + .datad(\ula_|video_|Equal1~0_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[3]~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[3]~3 .lut_mask = 16'h2230; +defparam \ula_|video_|vga_vc[3]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y32_N31 +dffeas \ula_|video_|vga_vc[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|vga_vc[3]~3_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[3] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y31_N10 +cycloneive_lcell_comb \ula_|video_|Add1~8 ( +// Equation(s): +// \ula_|video_|Add1~8_combout = (\ula_|video_|vga_vc [4] & (\ula_|video_|Add1~7 $ (GND))) # (!\ula_|video_|vga_vc [4] & (!\ula_|video_|Add1~7 & VCC)) +// \ula_|video_|Add1~9 = CARRY((\ula_|video_|vga_vc [4] & !\ula_|video_|Add1~7 )) + + .dataa(\ula_|video_|vga_vc [4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add1~7 ), + .combout(\ula_|video_|Add1~8_combout ), + .cout(\ula_|video_|Add1~9 )); +// synopsys translate_off +defparam \ula_|video_|Add1~8 .lut_mask = 16'hA50A; +defparam \ula_|video_|Add1~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y32_N6 +cycloneive_lcell_comb \ula_|video_|vga_vc[4]~5 ( +// Equation(s): +// \ula_|video_|vga_vc[4]~5_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [4]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~8_combout )))) + + .dataa(\ula_|video_|Equal3~1_combout ), + .datab(\ula_|video_|Add1~8_combout ), + .datac(\ula_|video_|vga_vc [4]), + .datad(\ula_|video_|Equal1~0_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[4]~5_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[4]~5 .lut_mask = 16'h5044; +defparam \ula_|video_|vga_vc[4]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y32_N7 +dffeas \ula_|video_|vga_vc[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[4]~5_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[4] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y31_N12 +cycloneive_lcell_comb \ula_|video_|Add1~10 ( +// Equation(s): +// \ula_|video_|Add1~10_combout = (\ula_|video_|vga_vc [5] & (!\ula_|video_|Add1~9 )) # (!\ula_|video_|vga_vc [5] & ((\ula_|video_|Add1~9 ) # (GND))) +// \ula_|video_|Add1~11 = CARRY((!\ula_|video_|Add1~9 ) # (!\ula_|video_|vga_vc [5])) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [5]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add1~9 ), + .combout(\ula_|video_|Add1~10_combout ), + .cout(\ula_|video_|Add1~11 )); +// synopsys translate_off +defparam \ula_|video_|Add1~10 .lut_mask = 16'h3C3F; +defparam \ula_|video_|Add1~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y31_N14 +cycloneive_lcell_comb \ula_|video_|Add1~12 ( +// Equation(s): +// \ula_|video_|Add1~12_combout = (\ula_|video_|vga_vc [6] & (\ula_|video_|Add1~11 $ (GND))) # (!\ula_|video_|vga_vc [6] & (!\ula_|video_|Add1~11 & VCC)) +// \ula_|video_|Add1~13 = CARRY((\ula_|video_|vga_vc [6] & !\ula_|video_|Add1~11 )) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [6]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add1~11 ), + .combout(\ula_|video_|Add1~12_combout ), + .cout(\ula_|video_|Add1~13 )); +// synopsys translate_off +defparam \ula_|video_|Add1~12 .lut_mask = 16'hC30C; +defparam \ula_|video_|Add1~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y32_N0 +cycloneive_lcell_comb \ula_|video_|vga_vc[6]~4 ( +// Equation(s): +// \ula_|video_|vga_vc[6]~4_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [6]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~12_combout )))) + + .dataa(\ula_|video_|Equal3~1_combout ), + .datab(\ula_|video_|Add1~12_combout ), + .datac(\ula_|video_|vga_vc [6]), + .datad(\ula_|video_|Equal1~0_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[6]~4_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[6]~4 .lut_mask = 16'h5044; +defparam \ula_|video_|vga_vc[6]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y32_N1 +dffeas \ula_|video_|vga_vc[6] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[6]~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[6] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y31_N16 +cycloneive_lcell_comb \ula_|video_|Add1~14 ( +// Equation(s): +// \ula_|video_|Add1~14_combout = (\ula_|video_|vga_vc [7] & (!\ula_|video_|Add1~13 )) # (!\ula_|video_|vga_vc [7] & ((\ula_|video_|Add1~13 ) # (GND))) +// \ula_|video_|Add1~15 = CARRY((!\ula_|video_|Add1~13 ) # (!\ula_|video_|vga_vc [7])) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [7]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add1~13 ), + .combout(\ula_|video_|Add1~14_combout ), + .cout(\ula_|video_|Add1~15 )); +// synopsys translate_off +defparam \ula_|video_|Add1~14 .lut_mask = 16'h3C3F; +defparam \ula_|video_|Add1~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y32_N8 +cycloneive_lcell_comb \ula_|video_|vga_vc[7]~6 ( +// Equation(s): +// \ula_|video_|vga_vc[7]~6_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [7]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~14_combout )))) + + .dataa(\ula_|video_|Equal3~1_combout ), + .datab(\ula_|video_|Add1~14_combout ), + .datac(\ula_|video_|vga_vc [7]), + .datad(\ula_|video_|Equal1~0_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[7]~6_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[7]~6 .lut_mask = 16'h5044; +defparam \ula_|video_|vga_vc[7]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y32_N9 +dffeas \ula_|video_|vga_vc[7] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[7]~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[7] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y31_N18 +cycloneive_lcell_comb \ula_|video_|Add1~16 ( +// Equation(s): +// \ula_|video_|Add1~16_combout = (\ula_|video_|vga_vc [8] & (\ula_|video_|Add1~15 $ (GND))) # (!\ula_|video_|vga_vc [8] & (!\ula_|video_|Add1~15 & VCC)) +// \ula_|video_|Add1~17 = CARRY((\ula_|video_|vga_vc [8] & !\ula_|video_|Add1~15 )) + + .dataa(\ula_|video_|vga_vc [8]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add1~15 ), + .combout(\ula_|video_|Add1~16_combout ), + .cout(\ula_|video_|Add1~17 )); +// synopsys translate_off +defparam \ula_|video_|Add1~16 .lut_mask = 16'hA50A; +defparam \ula_|video_|Add1~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y32_N0 +cycloneive_lcell_comb \ula_|video_|vga_vc[8]~7 ( +// Equation(s): +// \ula_|video_|vga_vc[8]~7_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [8]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~16_combout )))) + + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Add1~16_combout ), + .datac(\ula_|video_|vga_vc [8]), + .datad(\ula_|video_|Equal3~1_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[8]~7_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[8]~7 .lut_mask = 16'h00E4; +defparam \ula_|video_|vga_vc[8]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y32_N1 +dffeas \ula_|video_|vga_vc[8] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[8]~7_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [8]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[8] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y31_N20 +cycloneive_lcell_comb \ula_|video_|Add1~18 ( +// Equation(s): +// \ula_|video_|Add1~18_combout = \ula_|video_|Add1~17 $ (\ula_|video_|vga_vc [9]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|vga_vc [9]), + .cin(\ula_|video_|Add1~17 ), + .combout(\ula_|video_|Add1~18_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Add1~18 .lut_mask = 16'h0FF0; +defparam \ula_|video_|Add1~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y32_N28 +cycloneive_lcell_comb \ula_|video_|vga_vc[9]~9 ( +// Equation(s): +// \ula_|video_|vga_vc[9]~9_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [9]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~18_combout )))) + + .dataa(\ula_|video_|Add1~18_combout ), + .datab(\ula_|video_|Equal1~0_combout ), .datac(\ula_|video_|vga_vc [9]), + .datad(\ula_|video_|Equal3~1_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[9]~9_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[9]~9 .lut_mask = 16'h00E2; +defparam \ula_|video_|vga_vc[9]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y32_N29 +dffeas \ula_|video_|vga_vc[9] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[9]~9_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [9]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[9] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y30_N0 +cycloneive_lcell_comb \ula_|video_|Equal3~0 ( +// Equation(s): +// \ula_|video_|Equal3~0_combout = (\ula_|video_|vga_vc [0] & (\ula_|video_|vga_vc [3] & (\ula_|video_|vga_vc [2] & !\ula_|video_|vga_vc [1]))) + + .dataa(\ula_|video_|vga_vc [0]), + .datab(\ula_|video_|vga_vc [3]), + .datac(\ula_|video_|vga_vc [2]), + .datad(\ula_|video_|vga_vc [1]), + .cin(gnd), + .combout(\ula_|video_|Equal3~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Equal3~0 .lut_mask = 16'h0080; +defparam \ula_|video_|Equal3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y32_N2 +cycloneive_lcell_comb \ula_|video_|Equal2~0 ( +// Equation(s): +// \ula_|video_|Equal2~0_combout = (!\ula_|video_|vga_vc [6] & (!\ula_|video_|vga_vc [8] & (!\ula_|video_|vga_vc [4] & !\ula_|video_|vga_vc [7]))) + + .dataa(\ula_|video_|vga_vc [6]), + .datab(\ula_|video_|vga_vc [8]), + .datac(\ula_|video_|vga_vc [4]), + .datad(\ula_|video_|vga_vc [7]), + .cin(gnd), + .combout(\ula_|video_|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Equal2~0 .lut_mask = 16'h0001; +defparam \ula_|video_|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y32_N10 +cycloneive_lcell_comb \ula_|video_|Equal3~1 ( +// Equation(s): +// \ula_|video_|Equal3~1_combout = (!\ula_|video_|vga_vc [5] & (\ula_|video_|vga_vc [9] & (\ula_|video_|Equal3~0_combout & \ula_|video_|Equal2~0_combout ))) + + .dataa(\ula_|video_|vga_vc [5]), + .datab(\ula_|video_|vga_vc [9]), + .datac(\ula_|video_|Equal3~0_combout ), + .datad(\ula_|video_|Equal2~0_combout ), + .cin(gnd), + .combout(\ula_|video_|Equal3~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Equal3~1 .lut_mask = 16'h4000; +defparam \ula_|video_|Equal3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y32_N30 +cycloneive_lcell_comb \ula_|video_|vga_vc[5]~8 ( +// Equation(s): +// \ula_|video_|vga_vc[5]~8_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [5]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~10_combout )))) + + .dataa(\ula_|video_|Equal3~1_combout ), + .datab(\ula_|video_|Add1~10_combout ), + .datac(\ula_|video_|vga_vc [5]), + .datad(\ula_|video_|Equal1~0_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[5]~8_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[5]~8 .lut_mask = 16'h5044; +defparam \ula_|video_|vga_vc[5]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y32_N31 +dffeas \ula_|video_|vga_vc[5] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[5]~8_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[5] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y31_N26 +cycloneive_lcell_comb \ula_|video_|Equal2~1 ( +// Equation(s): +// \ula_|video_|Equal2~1_combout = (!\ula_|video_|vga_vc [2] & (!\ula_|video_|vga_vc [9] & (!\ula_|video_|vga_vc [3] & !\ula_|video_|vga_vc [0]))) + + .dataa(\ula_|video_|vga_vc [2]), + .datab(\ula_|video_|vga_vc [9]), + .datac(\ula_|video_|vga_vc [3]), .datad(\ula_|video_|vga_vc [0]), .cin(gnd), .combout(\ula_|video_|Equal2~1_combout ), @@ -19059,41 +6088,68 @@ defparam \ula_|video_|Equal2~1 .lut_mask = 16'h0001; defparam \ula_|video_|Equal2~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y33_N14 +// Location: LCCOMB_X35_Y32_N24 cycloneive_lcell_comb \ula_|video_|Equal2~2 ( // Equation(s): -// \ula_|video_|Equal2~2_combout = (\ula_|video_|Equal2~1_combout & (\ula_|video_|Equal2~0_combout & !\ula_|video_|vga_vc [5])) +// \ula_|video_|Equal2~2_combout = (!\ula_|video_|vga_vc [5] & (\ula_|video_|Equal2~1_combout & \ula_|video_|Equal2~0_combout )) - .dataa(gnd), + .dataa(\ula_|video_|vga_vc [5]), .datab(\ula_|video_|Equal2~1_combout ), - .datac(\ula_|video_|Equal2~0_combout ), - .datad(\ula_|video_|vga_vc [5]), + .datac(gnd), + .datad(\ula_|video_|Equal2~0_combout ), .cin(gnd), .combout(\ula_|video_|Equal2~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Equal2~2 .lut_mask = 16'h00C0; +defparam \ula_|video_|Equal2~2 .lut_mask = 16'h4400; defparam \ula_|video_|Equal2~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y31_N28 +// Location: IOIBUF_X27_Y0_N15 +cycloneive_io_ibuf \SW[1]~input ( + .i(SW[1]), + .ibar(gnd), + .o(\SW[1]~input_o )); +// synopsys translate_off +defparam \SW[1]~input .bus_hold = "false"; +defparam \SW[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y33_N2 +cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_13~0 ( +// Equation(s): +// \z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout = (!\ula_|video_|vga_vc [1] & (!\ula_|video_|vga_hc [8] & (!\ula_|video_|vga_hc [9] & !\SW[1]~input_o ))) + + .dataa(\ula_|video_|vga_vc [1]), + .datab(\ula_|video_|vga_hc [8]), + .datac(\ula_|video_|vga_hc [9]), + .datad(\SW[1]~input_o ), + .cin(gnd), + .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13~0 .lut_mask = 16'h0001; +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y33_N20 cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_13 ( // Equation(s): -// \z80_|interrupts_|SYNTHESIZED_WIRE_13~combout = (!\ula_|video_|vga_hc [7] & (\z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout & (\z80_|interrupts_|iff1~q & \ula_|video_|Equal2~2_combout ))) +// \z80_|interrupts_|SYNTHESIZED_WIRE_13~combout = (\z80_|interrupts_|iff1~q & (\ula_|video_|Equal2~2_combout & (!\ula_|video_|vga_hc [7] & \z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout ))) - .dataa(\ula_|video_|vga_hc [7]), - .datab(\z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout ), - .datac(\z80_|interrupts_|iff1~q ), - .datad(\ula_|video_|Equal2~2_combout ), + .dataa(\z80_|interrupts_|iff1~q ), + .datab(\ula_|video_|Equal2~2_combout ), + .datac(\ula_|video_|vga_hc [7]), + .datad(\z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout ), .cin(gnd), .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_13~combout ), .cout()); // synopsys translate_off -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13 .lut_mask = 16'h4000; +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13 .lut_mask = 16'h0800; defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X35_Y31_N29 +// Location: FF_X35_Y33_N21 dffeas \z80_|interrupts_|int_armed ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|interrupts_|SYNTHESIZED_WIRE_13~combout ), @@ -19112,15 +6168,32 @@ defparam \z80_|interrupts_|int_armed .is_wysiwyg = "true"; defparam \z80_|interrupts_|int_armed .power_up = "low"; // synopsys translate_on -// Location: FF_X32_Y15_N11 +// Location: LCCOMB_X28_Y13_N30 +cycloneive_lcell_comb \z80_|interrupts_|DFFE_inst44~feeder ( +// Equation(s): +// \z80_|interrupts_|DFFE_inst44~feeder_combout = \z80_|interrupts_|int_armed~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|interrupts_|int_armed~q ), + .cin(gnd), + .combout(\z80_|interrupts_|DFFE_inst44~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|DFFE_inst44~feeder .lut_mask = 16'hFF00; +defparam \z80_|interrupts_|DFFE_inst44~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y13_N31 dffeas \z80_|interrupts_|DFFE_inst44 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|interrupts_|int_armed~q ), + .d(\z80_|interrupts_|DFFE_inst44~feeder_combout ), + .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), - .sload(vcc), + .sload(gnd), .ena(\z80_|interrupts_|test1~3_combout ), .devclrn(devclrn), .devpor(devpor), @@ -19131,14509 +6204,44 @@ defparam \z80_|interrupts_|DFFE_inst44 .is_wysiwyg = "true"; defparam \z80_|interrupts_|DFFE_inst44 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~38 ( +// Location: LCCOMB_X28_Y13_N4 +cycloneive_lcell_comb \z80_|decode_state_|in_halt~0 ( // Equation(s): -// \z80_|execute_|pc_inc_hold~38_combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # ((\z80_|decode_state_|in_halt~q ) # (\z80_|interrupts_|DFFE_inst44~q )) +// \z80_|decode_state_|in_halt~0_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (!\z80_|interrupts_|DFFE_inst44~q & \z80_|decode_state_|in_halt~q )) .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), .datab(gnd), - .datac(\z80_|decode_state_|in_halt~q ), - .datad(\z80_|interrupts_|DFFE_inst44~q ), + .datac(\z80_|interrupts_|DFFE_inst44~q ), + .datad(\z80_|decode_state_|in_halt~q ), .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~38_combout ), + .combout(\z80_|decode_state_|in_halt~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~38 .lut_mask = 16'hFFFA; -defparam \z80_|execute_|pc_inc_hold~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~91 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~91_combout = (((!\z80_|sequencer_|DFFE_M3_ff~q & !\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|pla_decode_|Equal34~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~91_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~91 .lut_mask = 16'h57FF; -defparam \z80_|execute_|ctl_inc_cy~91 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~45 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~45_combout = (\z80_|pla_decode_|Equal19~0_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ctl_mRead~36_combout & \z80_|execute_|pc_inc_hold~29_combout )))) # (!\z80_|pla_decode_|Equal19~0_combout & -// (((\z80_|execute_|ctl_mRead~36_combout & \z80_|execute_|pc_inc_hold~29_combout )))) - - .dataa(\z80_|pla_decode_|Equal19~0_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_mRead~36_combout ), - .datad(\z80_|execute_|pc_inc_hold~29_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~45 .lut_mask = 16'hF888; -defparam \z80_|execute_|pc_inc_hold~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~44 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~44_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & ((\z80_|pla_decode_|Equal19~0_combout ) # ((!\z80_|execute_|pc_inc_hold~49_combout ) # (!\z80_|execute_|ctl_bus_db_oe~1_combout )))) - - .dataa(\z80_|pla_decode_|Equal19~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .datad(\z80_|execute_|pc_inc_hold~49_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~44 .lut_mask = 16'h8CCC; -defparam \z80_|execute_|pc_inc_hold~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N2 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~46 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~46_combout = (\z80_|execute_|pc_inc_hold~45_combout ) # ((\z80_|execute_|pc_inc_hold~44_combout ) # ((\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|pc_inc_hold~49_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~45_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|pc_inc_hold~44_combout ), - .datad(\z80_|execute_|pc_inc_hold~49_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~46 .lut_mask = 16'hFAFE; -defparam \z80_|execute_|pc_inc_hold~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N18 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~37 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~37_combout = (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|execute_|pc_inc_hold~29_combout ) # ((\z80_|pla_decode_|Equal52~1_combout & \z80_|execute_|ctl_alu_op_low~8_combout )))) # (!\z80_|pla_decode_|Equal10~0_combout & -// (\z80_|pla_decode_|Equal52~1_combout & (\z80_|execute_|ctl_alu_op_low~8_combout ))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|pla_decode_|Equal52~1_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datad(\z80_|execute_|pc_inc_hold~29_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~37 .lut_mask = 16'hEAC0; -defparam \z80_|execute_|pc_inc_hold~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N12 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~50 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~50_combout = (\z80_|execute_|pc_inc_hold~37_combout ) # ((\z80_|execute_|ixy_d~16_combout & (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ))) - - .dataa(\z80_|execute_|ixy_d~16_combout ), - .datab(\z80_|execute_|pc_inc_hold~37_combout ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~50 .lut_mask = 16'hECCC; -defparam \z80_|execute_|pc_inc_hold~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N22 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~33 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~33_combout = (\z80_|execute_|ctl_mRead~10_combout & (((\z80_|execute_|ctl_alu_op_low~8_combout ) # (\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|execute_|ctl_mRead~10_combout & (\z80_|pla_decode_|Equal6~1_combout & -// ((\z80_|execute_|ctl_alu_op_low~8_combout ) # (\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|pla_decode_|Equal6~1_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~33 .lut_mask = 16'hEEE0; -defparam \z80_|execute_|pc_inc_hold~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|execute_|ixy_d~5_combout & (\z80_|pla_decode_|Equal55~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal33~2_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|decode_state_|use_ixiy~combout ), - .datad(\z80_|pla_decode_|Equal33~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N26 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~31 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~31_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ) # ((\z80_|execute_|ctl_alu_op_low~8_combout & ((\z80_|execute_|ctl_mRead~14_combout ) # (!\z80_|execute_|pc_inc_hold~28_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ), - .datac(\z80_|execute_|ctl_mRead~14_combout ), - .datad(\z80_|execute_|pc_inc_hold~28_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~31 .lut_mask = 16'hECEE; -defparam \z80_|execute_|pc_inc_hold~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N12 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~32 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~32_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & (((\z80_|execute_|ctl_mRead~9_combout ) # (\z80_|execute_|ctl_mRead~15_combout )))) # (!\z80_|execute_|ctl_alu_op_low~8_combout & (\z80_|execute_|ixy_d~5_combout & -// ((\z80_|execute_|ctl_mRead~15_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_mRead~9_combout ), - .datad(\z80_|execute_|ctl_mRead~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~32 .lut_mask = 16'hEEA0; -defparam \z80_|execute_|pc_inc_hold~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N16 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~34 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~34_combout = (\z80_|execute_|pc_inc_hold~33_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ) # ((\z80_|execute_|pc_inc_hold~31_combout ) # (\z80_|execute_|pc_inc_hold~32_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~33_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ), - .datac(\z80_|execute_|pc_inc_hold~31_combout ), - .datad(\z80_|execute_|pc_inc_hold~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~34 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|pc_inc_hold~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N28 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~51 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~51_combout = (((!\z80_|sequencer_|DFFE_M3_ff~q & !\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|execute_|ctl_mRead~17_combout ) - - .dataa(\z80_|execute_|ctl_mRead~17_combout ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~51_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~51 .lut_mask = 16'h57FF; -defparam \z80_|execute_|pc_inc_hold~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N22 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~30 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~30_combout = (\z80_|pla_decode_|Equal12~1_combout ) # (((!\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ctl_alu_op_low~8_combout )) # (!\z80_|pla_decode_|Equal25~0_combout )) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|pla_decode_|Equal12~1_combout ), - .datac(\z80_|pla_decode_|Equal25~0_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~30 .lut_mask = 16'hCFDF; -defparam \z80_|execute_|pc_inc_hold~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N6 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~52 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~52_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|execute_|ctl_mRead~8_combout & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (\z80_|sequencer_|DFFE_M2_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|execute_|ctl_mRead~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~52_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~52 .lut_mask = 16'hA800; -defparam \z80_|execute_|pc_inc_hold~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N8 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~35 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~35_combout = (!\z80_|execute_|pc_inc_hold~34_combout & (\z80_|execute_|pc_inc_hold~51_combout & (\z80_|execute_|pc_inc_hold~30_combout & !\z80_|execute_|pc_inc_hold~52_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~34_combout ), - .datab(\z80_|execute_|pc_inc_hold~51_combout ), - .datac(\z80_|execute_|pc_inc_hold~30_combout ), - .datad(\z80_|execute_|pc_inc_hold~52_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~35 .lut_mask = 16'h0040; -defparam \z80_|execute_|pc_inc_hold~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N4 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~36 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~36_combout = ((\z80_|pla_decode_|Equal11~0_combout & ((\z80_|execute_|ctl_mWrite~7_combout ) # (\z80_|execute_|ctl_alu_shift_oe~14_combout )))) # (!\z80_|execute_|pc_inc_hold~35_combout ) - - .dataa(\z80_|execute_|ctl_mWrite~7_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|pc_inc_hold~35_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~36 .lut_mask = 16'hCF8F; -defparam \z80_|execute_|pc_inc_hold~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~44 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~44_combout = (((!\z80_|pla_decode_|Equal21~0_combout & !\z80_|pla_decode_|Equal3~0_combout )) # (!\z80_|pla_decode_|Equal24~0_combout )) # (!\z80_|execute_|ctl_alu_op_low~8_combout ) - - .dataa(\z80_|pla_decode_|Equal21~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|pla_decode_|Equal3~0_combout ), - .datad(\z80_|pla_decode_|Equal24~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~44 .lut_mask = 16'h37FF; -defparam \z80_|execute_|ctl_inc_cy~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|execute_|ixy_d~10_combout )) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(gnd), - .datad(\z80_|execute_|ixy_d~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 .lut_mask = 16'h8800; -defparam \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~45 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~45_combout = (!\z80_|execute_|pc_inc_hold~50_combout & (!\z80_|execute_|pc_inc_hold~36_combout & (\z80_|execute_|ctl_inc_cy~44_combout & !\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~50_combout ), - .datab(\z80_|execute_|pc_inc_hold~36_combout ), - .datac(\z80_|execute_|ctl_inc_cy~44_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~45 .lut_mask = 16'h0010; -defparam \z80_|execute_|ctl_inc_cy~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~43 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~43_combout = (\z80_|execute_|ctl_mWrite~2_combout & (\z80_|pla_decode_|Equal55~0_combout & ((\z80_|execute_|ctl_mWrite~7_combout ) # (\z80_|execute_|ctl_alu_shift_oe~14_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~7_combout ), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~43 .lut_mask = 16'hC080; -defparam \z80_|execute_|pc_inc_hold~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~71 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~71_combout = (\z80_|execute_|ctl_inc_cy~91_combout & (!\z80_|execute_|pc_inc_hold~46_combout & (\z80_|execute_|ctl_inc_cy~45_combout & !\z80_|execute_|pc_inc_hold~43_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~91_combout ), - .datab(\z80_|execute_|pc_inc_hold~46_combout ), - .datac(\z80_|execute_|ctl_inc_cy~45_combout ), - .datad(\z80_|execute_|pc_inc_hold~43_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~71_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~71 .lut_mask = 16'h0020; -defparam \z80_|execute_|ctl_inc_cy~71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~73 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~73_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (((\z80_|execute_|ctl_inc_cy~72_combout & \z80_|execute_|ctl_inc_cy~71_combout )) # (!\z80_|execute_|pc_inc_hold~38_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|execute_|ctl_inc_cy~72_combout ), - .datac(\z80_|execute_|pc_inc_hold~38_combout ), - .datad(\z80_|execute_|ctl_inc_cy~71_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~73_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~73 .lut_mask = 16'h8A0A; -defparam \z80_|execute_|ctl_inc_cy~73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~46 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~46_combout = (\z80_|execute_|ixy_d~5_combout & (\z80_|execute_|ctl_mWrite~16_combout & ((\z80_|execute_|ctl_inc_cy~45_combout ) # (!\z80_|execute_|pc_inc_hold~38_combout )))) - - .dataa(\z80_|execute_|ctl_inc_cy~45_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|pc_inc_hold~38_combout ), - .datad(\z80_|execute_|ctl_mWrite~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~46 .lut_mask = 16'h8C00; -defparam \z80_|execute_|ctl_inc_cy~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N24 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~53 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~53_combout = (\z80_|pla_decode_|Equal11~0_combout & (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T4_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|sequencer_|DFFE_M4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~53_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~53 .lut_mask = 16'hE000; -defparam \z80_|execute_|pc_inc_hold~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N0 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~39 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~39_combout = (!\z80_|execute_|pc_inc_hold~50_combout & (!\z80_|execute_|pc_inc_hold~53_combout & (\z80_|execute_|pc_inc_hold~35_combout & !\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~50_combout ), - .datab(\z80_|execute_|pc_inc_hold~53_combout ), - .datac(\z80_|execute_|pc_inc_hold~35_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~39 .lut_mask = 16'h0010; -defparam \z80_|execute_|pc_inc_hold~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N10 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~47 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~47_combout = (\z80_|execute_|pc_inc_hold~46_combout ) # ((\z80_|execute_|pc_inc_hold~43_combout ) # ((!\z80_|execute_|ctl_inc_cy~44_combout ) # (!\z80_|execute_|pc_inc_hold~39_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~46_combout ), - .datab(\z80_|execute_|pc_inc_hold~43_combout ), - .datac(\z80_|execute_|pc_inc_hold~39_combout ), - .datad(\z80_|execute_|ctl_inc_cy~44_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~47 .lut_mask = 16'hEFFF; -defparam \z80_|execute_|pc_inc_hold~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~74 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~74_combout = (((!\z80_|execute_|ctl_inc_cy~40_combout ) # (!\z80_|execute_|ctl_inc_cy~34_combout )) # (!\z80_|execute_|ctl_inc_cy~35_combout )) # (!\z80_|execute_|ctl_inc_cy~43_combout ) - - .dataa(\z80_|execute_|ctl_inc_cy~43_combout ), - .datab(\z80_|execute_|ctl_inc_cy~35_combout ), - .datac(\z80_|execute_|ctl_inc_cy~34_combout ), - .datad(\z80_|execute_|ctl_inc_cy~40_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~74_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~74 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_inc_cy~74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~78 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~78_combout = ((\z80_|execute_|ctl_inc_cy~74_combout ) # (!\z80_|execute_|ctl_inc_cy~77_combout )) # (!\z80_|execute_|ctl_inc_cy~39_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_inc_cy~39_combout ), - .datac(\z80_|execute_|ctl_inc_cy~77_combout ), - .datad(\z80_|execute_|ctl_inc_cy~74_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~78_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~78 .lut_mask = 16'hFF3F; -defparam \z80_|execute_|ctl_inc_cy~78 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~79 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~79_combout = (\z80_|execute_|ctl_inc_cy~78_combout & (((!\z80_|execute_|pc_inc_hold~47_combout & \z80_|execute_|ctl_inc_cy~91_combout )) # (!\z80_|execute_|pc_inc_hold~38_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~47_combout ), - .datab(\z80_|execute_|ctl_inc_cy~78_combout ), - .datac(\z80_|execute_|pc_inc_hold~38_combout ), - .datad(\z80_|execute_|ctl_inc_cy~91_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~79_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~79 .lut_mask = 16'h4C0C; -defparam \z80_|execute_|ctl_inc_cy~79 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~80 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~80_combout = (\z80_|execute_|ctl_inc_cy~45_combout & (\z80_|execute_|ctl_alu_op_low~8_combout & (\z80_|execute_|ctl_mRead~36_combout & !\z80_|execute_|pc_inc_hold~43_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~45_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|execute_|ctl_mRead~36_combout ), - .datad(\z80_|execute_|pc_inc_hold~43_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~80_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~80 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_inc_cy~80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~81 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~81_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal19~1_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # (\z80_|execute_|ixy_d~9_combout )))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|pla_decode_|Equal19~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~81_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~81 .lut_mask = 16'hA800; -defparam \z80_|execute_|ctl_inc_cy~81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~82 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~82_combout = (\z80_|execute_|ctl_inc_cy~81_combout ) # ((\z80_|pla_decode_|Equal19~0_combout & ((\z80_|execute_|ctl_state_alu~6_combout ) # (\z80_|execute_|ctl_alu_oe~2_combout )))) - - .dataa(\z80_|execute_|ctl_inc_cy~81_combout ), - .datab(\z80_|pla_decode_|Equal19~0_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_alu_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~82_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~82 .lut_mask = 16'hEEEA; -defparam \z80_|execute_|ctl_inc_cy~82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~83 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~83_combout = (\z80_|execute_|pc_inc_hold~47_combout & (!\z80_|execute_|pc_inc_hold~38_combout & ((\z80_|execute_|ctl_inc_cy~82_combout ) # (!\z80_|execute_|ctl_inc_cy~38_combout )))) # (!\z80_|execute_|pc_inc_hold~47_combout -// & ((\z80_|execute_|ctl_inc_cy~82_combout ) # ((!\z80_|execute_|ctl_inc_cy~38_combout )))) - - .dataa(\z80_|execute_|pc_inc_hold~47_combout ), - .datab(\z80_|execute_|ctl_inc_cy~82_combout ), - .datac(\z80_|execute_|pc_inc_hold~38_combout ), - .datad(\z80_|execute_|ctl_inc_cy~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~83_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~83 .lut_mask = 16'h4C5F; -defparam \z80_|execute_|ctl_inc_cy~83 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~84 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~84_combout = (\z80_|execute_|ctl_inc_cy~79_combout ) # ((\z80_|execute_|ctl_inc_cy~80_combout ) # (\z80_|execute_|ctl_inc_cy~83_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_inc_cy~79_combout ), - .datac(\z80_|execute_|ctl_inc_cy~80_combout ), - .datad(\z80_|execute_|ctl_inc_cy~83_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~84_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~84 .lut_mask = 16'hFFFC; -defparam \z80_|execute_|ctl_inc_cy~84 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N10 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~42 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~42_combout = ((\z80_|execute_|pc_inc_hold~34_combout ) # (\z80_|execute_|pc_inc_hold~52_combout )) # (!\z80_|execute_|pc_inc_hold~30_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|pc_inc_hold~30_combout ), - .datac(\z80_|execute_|pc_inc_hold~34_combout ), - .datad(\z80_|execute_|pc_inc_hold~52_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~42 .lut_mask = 16'hFFF3; -defparam \z80_|execute_|pc_inc_hold~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~90 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~90_combout = (((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|execute_|ctl_mRead~8_combout ) - - .dataa(\z80_|sequencer_|M5~q ), - .datab(\z80_|execute_|ctl_mRead~8_combout ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~90_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~90 .lut_mask = 16'h37FF; -defparam \z80_|execute_|ctl_inc_cy~90 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N2 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~41 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~41_combout = (\z80_|execute_|pc_inc_hold~31_combout ) # ((\z80_|execute_|pc_inc_hold~32_combout ) # ((\z80_|execute_|ixy_d~5_combout & \z80_|execute_|ctl_mRead~9_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~31_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_mRead~9_combout ), - .datad(\z80_|execute_|pc_inc_hold~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~41 .lut_mask = 16'hFFEA; -defparam \z80_|execute_|pc_inc_hold~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~66 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~66_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|execute_|ctl_mRead~14_combout & (!\z80_|decode_state_|in_halt~q & !\z80_|interrupts_|DFFE_inst44~q ))) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|execute_|ctl_mRead~14_combout ), - .datac(\z80_|decode_state_|in_halt~q ), - .datad(\z80_|interrupts_|DFFE_inst44~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~66_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~66 .lut_mask = 16'h0004; -defparam \z80_|execute_|ctl_inc_cy~66 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~67 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~67_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & ((\z80_|execute_|ctl_inc_cy~66_combout ) # ((!\z80_|execute_|ctl_reg_sys_hilo~20_combout & !\z80_|execute_|pc_inc_hold~31_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), - .datac(\z80_|execute_|pc_inc_hold~31_combout ), - .datad(\z80_|execute_|ctl_inc_cy~66_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~67_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~67 .lut_mask = 16'hAA02; -defparam \z80_|execute_|ctl_inc_cy~67 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~68 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~68_combout = (\z80_|execute_|ctl_inc_cy~67_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~14_combout & (!\z80_|execute_|pc_inc_hold~41_combout & \z80_|execute_|ctl_mRead~15_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|execute_|pc_inc_hold~41_combout ), - .datac(\z80_|execute_|ctl_inc_cy~67_combout ), - .datad(\z80_|execute_|ctl_mRead~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~68_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~68 .lut_mask = 16'hF2F0; -defparam \z80_|execute_|ctl_inc_cy~68 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~64 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~64_combout = (!\z80_|execute_|pc_inc_hold~31_combout & (((!\z80_|execute_|ctl_alu_op_low~8_combout & !\z80_|execute_|ixy_d~5_combout )) # (!\z80_|execute_|ctl_mRead~9_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datab(\z80_|execute_|ctl_mRead~9_combout ), - .datac(\z80_|execute_|pc_inc_hold~31_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~64_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~64 .lut_mask = 16'h0307; -defparam \z80_|execute_|ctl_inc_cy~64 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~63 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~63_combout = (\z80_|execute_|ctl_mRead~10_combout & (!\z80_|execute_|pc_inc_hold~34_combout & ((\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (\z80_|execute_|ctl_sw_4u~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|execute_|ctl_mRead~10_combout ), - .datac(\z80_|execute_|pc_inc_hold~34_combout ), - .datad(\z80_|execute_|ctl_sw_4u~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~63_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~63 .lut_mask = 16'h0C08; -defparam \z80_|execute_|ctl_inc_cy~63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~65 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~65_combout = (\z80_|execute_|ctl_inc_cy~63_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & ((\z80_|execute_|ctl_inc_cy~64_combout ) # (!\z80_|execute_|pc_inc_hold~38_combout )))) - - .dataa(\z80_|execute_|pc_inc_hold~38_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), - .datac(\z80_|execute_|ctl_inc_cy~64_combout ), - .datad(\z80_|execute_|ctl_inc_cy~63_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~65_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~65 .lut_mask = 16'hFFC4; -defparam \z80_|execute_|ctl_inc_cy~65 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~69 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~69_combout = (\z80_|execute_|ctl_inc_cy~68_combout ) # ((\z80_|execute_|ctl_inc_cy~65_combout ) # ((!\z80_|execute_|pc_inc_hold~42_combout & !\z80_|execute_|ctl_inc_cy~90_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~42_combout ), - .datab(\z80_|execute_|ctl_inc_cy~90_combout ), - .datac(\z80_|execute_|ctl_inc_cy~68_combout ), - .datad(\z80_|execute_|ctl_inc_cy~65_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~69_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~69 .lut_mask = 16'hFFF1; -defparam \z80_|execute_|ctl_inc_cy~69 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~49 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~49_combout = ((\z80_|pla_decode_|Equal9~1_combout & ((\z80_|execute_|ixy_d~9_combout ) # (\z80_|execute_|ctl_state_alu~6_combout )))) # (!\z80_|execute_|ctl_inc_cy~92_combout ) - - .dataa(\z80_|execute_|ixy_d~9_combout ), - .datab(\z80_|execute_|ctl_state_alu~6_combout ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|execute_|ctl_inc_cy~92_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~49 .lut_mask = 16'hE0FF; -defparam \z80_|execute_|ctl_inc_cy~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~50 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~50_combout = (\z80_|execute_|ixy_d~9_combout & ((\z80_|pla_decode_|Equal11~0_combout ) # ((\z80_|execute_|ctl_mWrite~4_combout & \z80_|execute_|ixy_d~7_combout )))) # (!\z80_|execute_|ixy_d~9_combout & -// (((\z80_|execute_|ctl_mWrite~4_combout & \z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|execute_|ixy_d~9_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~50 .lut_mask = 16'hF888; -defparam \z80_|execute_|ctl_inc_cy~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~51 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~51_combout = (\z80_|execute_|ctl_inc_cy~50_combout ) # (((\z80_|execute_|ctl_mWrite~4_combout & \z80_|execute_|ctl_mRead~11_combout )) # (!\z80_|execute_|ctl_inc_cy~94_combout )) - - .dataa(\z80_|execute_|ctl_inc_cy~50_combout ), - .datab(\z80_|execute_|ctl_mWrite~4_combout ), - .datac(\z80_|execute_|ctl_inc_cy~94_combout ), - .datad(\z80_|execute_|ctl_mRead~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~51_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~51 .lut_mask = 16'hEFAF; -defparam \z80_|execute_|ctl_inc_cy~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~52 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~52_combout = (\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ) # ((\z80_|execute_|ctl_inc_cy~51_combout ) # ((\z80_|execute_|ctl_alu_op_low~8_combout & \z80_|pla_decode_|Equal11~0_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|execute_|ctl_inc_cy~51_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~52_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~52 .lut_mask = 16'hFFEA; -defparam \z80_|execute_|ctl_inc_cy~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~36 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~36_combout = ((!\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|execute_|ctl_alu_op_low~8_combout & !\z80_|execute_|ixy_d~5_combout ))) # (!\z80_|execute_|ctl_mWrite~4_combout ) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|execute_|ctl_mWrite~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~36 .lut_mask = 16'h01FF; -defparam \z80_|execute_|ctl_inc_cy~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~37 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~37_combout = (\z80_|execute_|ctl_sw_2u~0_combout & (\z80_|execute_|ctl_inc_cy~36_combout & ((!\z80_|pla_decode_|Equal11~0_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ctl_sw_2u~0_combout ), - .datad(\z80_|execute_|ctl_inc_cy~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~37 .lut_mask = 16'h7000; -defparam \z80_|execute_|ctl_inc_cy~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~54 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~54_combout = ((\z80_|execute_|ctl_inc_cy~49_combout ) # ((\z80_|execute_|ctl_inc_cy~52_combout ) # (!\z80_|execute_|ctl_inc_cy~37_combout ))) # (!\z80_|execute_|ctl_inc_cy~53_combout ) - - .dataa(\z80_|execute_|ctl_inc_cy~53_combout ), - .datab(\z80_|execute_|ctl_inc_cy~49_combout ), - .datac(\z80_|execute_|ctl_inc_cy~52_combout ), - .datad(\z80_|execute_|ctl_inc_cy~37_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~54_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~54 .lut_mask = 16'hFDFF; -defparam \z80_|execute_|ctl_inc_cy~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~41 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~41_combout = (!\z80_|execute_|ctl_mRead~17_combout & (!\z80_|pla_decode_|Equal34~0_combout & ((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~17_combout ), - .datab(\z80_|pla_decode_|Equal12~1_combout ), - .datac(\z80_|pla_decode_|Equal25~0_combout ), - .datad(\z80_|pla_decode_|Equal34~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~41 .lut_mask = 16'h0045; -defparam \z80_|execute_|ctl_inc_cy~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~58 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~58_combout = (\z80_|execute_|ctl_mRead~4_combout ) # ((\z80_|execute_|ctl_mWrite~6_combout ) # (!\z80_|execute_|ctl_inc_cy~41_combout )) - - .dataa(\z80_|execute_|ctl_mRead~4_combout ), - .datab(\z80_|execute_|ctl_mWrite~6_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_inc_cy~41_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~58_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~58 .lut_mask = 16'hEEFF; -defparam \z80_|execute_|ctl_inc_cy~58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~55 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~55_combout = (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|execute_|ctl_alu_op_low~8_combout ) # ((\z80_|execute_|ixy_d~9_combout )))) # (!\z80_|pla_decode_|Equal10~0_combout & (\z80_|execute_|ctl_alu_op_low~8_combout & -// ((\z80_|execute_|ctl_mRead~36_combout )))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|execute_|ctl_mRead~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~55_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~55 .lut_mask = 16'hECA8; -defparam \z80_|execute_|ctl_inc_cy~55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~56 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~56_combout = (((!\z80_|execute_|ctl_reg_sys_we~2_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout )) # (!\z80_|execute_|ctl_reg_sel_pc~17_combout )) # (!\z80_|execute_|fMRead~3_combout ) - - .dataa(\z80_|execute_|fMRead~3_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~17_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), - .datad(\z80_|execute_|ctl_reg_sys_we~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~56_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~56 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_inc_cy~56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~89 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~89_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|pla_decode_|Equal41~2_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~30_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|execute_|ctl_bus_inc_oe~30_combout ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|pla_decode_|Equal41~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~89_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~89 .lut_mask = 16'hA020; -defparam \z80_|execute_|ctl_inc_cy~89 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~57 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~57_combout = ((\z80_|execute_|ctl_inc_cy~55_combout ) # ((\z80_|execute_|ctl_inc_cy~56_combout ) # (\z80_|execute_|ctl_inc_cy~89_combout ))) # (!\z80_|execute_|ctl_reg_sel_pc~7_combout ) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~7_combout ), - .datab(\z80_|execute_|ctl_inc_cy~55_combout ), - .datac(\z80_|execute_|ctl_inc_cy~56_combout ), - .datad(\z80_|execute_|ctl_inc_cy~89_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~57_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~57 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_inc_cy~57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~59 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~59_combout = (\z80_|execute_|ctl_inc_cy~57_combout ) # ((\z80_|execute_|ctl_alu_op_low~8_combout & ((\z80_|execute_|ctl_inc_cy~58_combout ) # (!\z80_|execute_|fMRead~5_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datab(\z80_|execute_|ctl_inc_cy~58_combout ), - .datac(\z80_|execute_|fMRead~5_combout ), - .datad(\z80_|execute_|ctl_inc_cy~57_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~59_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~59 .lut_mask = 16'hFF8A; -defparam \z80_|execute_|ctl_inc_cy~59 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~60 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~60_combout = (\z80_|execute_|pc_inc_hold~38_combout & (\z80_|execute_|pc_inc_hold~35_combout & (\z80_|execute_|ctl_inc_cy~54_combout ))) # (!\z80_|execute_|pc_inc_hold~38_combout & (((\z80_|execute_|ctl_inc_cy~54_combout ) # -// (\z80_|execute_|ctl_inc_cy~59_combout )))) - - .dataa(\z80_|execute_|pc_inc_hold~38_combout ), - .datab(\z80_|execute_|pc_inc_hold~35_combout ), - .datac(\z80_|execute_|ctl_inc_cy~54_combout ), - .datad(\z80_|execute_|ctl_inc_cy~59_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~60_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~60 .lut_mask = 16'hD5D0; -defparam \z80_|execute_|ctl_inc_cy~60 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~47 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~47_combout = (\z80_|execute_|ctl_state_alu~14_combout & (!\z80_|execute_|pc_inc_hold~36_combout & (\z80_|execute_|ctl_alu_op_low~8_combout & !\z80_|execute_|pc_inc_hold~50_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~14_combout ), - .datab(\z80_|execute_|pc_inc_hold~36_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datad(\z80_|execute_|pc_inc_hold~50_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~47 .lut_mask = 16'h0020; -defparam \z80_|execute_|ctl_inc_cy~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~88 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~88_combout = (\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ) # ((\z80_|pla_decode_|Equal13~2_combout & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ))) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~88_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~88 .lut_mask = 16'hECCC; -defparam \z80_|execute_|ctl_inc_cy~88 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~48 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~48_combout = (\z80_|execute_|ctl_inc_cy~47_combout ) # ((\z80_|execute_|ctl_inc_cy~88_combout & ((\z80_|execute_|pc_inc_hold~39_combout ) # (!\z80_|execute_|pc_inc_hold~38_combout )))) - - .dataa(\z80_|execute_|pc_inc_hold~39_combout ), - .datab(\z80_|execute_|ctl_inc_cy~47_combout ), - .datac(\z80_|execute_|ctl_inc_cy~88_combout ), - .datad(\z80_|execute_|pc_inc_hold~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~48 .lut_mask = 16'hECFC; -defparam \z80_|execute_|ctl_inc_cy~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N18 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~40 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~40_combout = (\z80_|execute_|pc_inc_hold~30_combout & !\z80_|execute_|pc_inc_hold~34_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|pc_inc_hold~30_combout ), - .datac(\z80_|execute_|pc_inc_hold~34_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~40 .lut_mask = 16'h0C0C; -defparam \z80_|execute_|pc_inc_hold~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~61 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~61_combout = (!\z80_|execute_|pc_inc_hold~36_combout & (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|execute_|ixy_d~9_combout ) # (\z80_|execute_|ctl_alu_op_low~8_combout )))) - - .dataa(\z80_|execute_|ixy_d~9_combout ), - .datab(\z80_|execute_|pc_inc_hold~36_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datad(\z80_|pla_decode_|Equal10~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~61_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~61 .lut_mask = 16'h3200; -defparam \z80_|execute_|ctl_inc_cy~61 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~62 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~62_combout = (\z80_|execute_|ctl_inc_cy~61_combout ) # ((!\z80_|execute_|ctl_inc_cy~42_combout & ((\z80_|execute_|pc_inc_hold~40_combout ) # (!\z80_|execute_|pc_inc_hold~38_combout )))) - - .dataa(\z80_|execute_|pc_inc_hold~38_combout ), - .datab(\z80_|execute_|pc_inc_hold~40_combout ), - .datac(\z80_|execute_|ctl_inc_cy~61_combout ), - .datad(\z80_|execute_|ctl_inc_cy~42_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~62_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~62 .lut_mask = 16'hF0FD; -defparam \z80_|execute_|ctl_inc_cy~62 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~70 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~70_combout = (\z80_|execute_|ctl_inc_cy~69_combout ) # ((\z80_|execute_|ctl_inc_cy~60_combout ) # ((\z80_|execute_|ctl_inc_cy~48_combout ) # (\z80_|execute_|ctl_inc_cy~62_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~69_combout ), - .datab(\z80_|execute_|ctl_inc_cy~60_combout ), - .datac(\z80_|execute_|ctl_inc_cy~48_combout ), - .datad(\z80_|execute_|ctl_inc_cy~62_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~70_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~70 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_inc_cy~70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~85 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~85_combout = (\z80_|execute_|ctl_inc_cy~73_combout ) # ((\z80_|execute_|ctl_inc_cy~46_combout ) # ((\z80_|execute_|ctl_inc_cy~84_combout ) # (\z80_|execute_|ctl_inc_cy~70_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~73_combout ), - .datab(\z80_|execute_|ctl_inc_cy~46_combout ), - .datac(\z80_|execute_|ctl_inc_cy~84_combout ), - .datad(\z80_|execute_|ctl_inc_cy~70_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~85_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~85 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_inc_cy~85 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N28 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout = \z80_|address_latch_|Q [0] $ (\z80_|execute_|ctl_inc_cy~85_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|address_latch_|Q [0]), - .datad(\z80_|execute_|ctl_inc_cy~85_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out .lut_mask = 16'h0FF0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N8 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~3 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[0]~3_combout = ((\z80_|reg_file_|db_lo_as[0]~1_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[0]~1_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[0]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[0]~3 .lut_mask = 16'hAF2F; -defparam \z80_|reg_file_|db_lo_as[0]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N28 -cycloneive_lcell_comb \z80_|address_latch_|abusz[0] ( -// Equation(s): -// \z80_|address_latch_|abusz [0] = (\z80_|reg_file_|db_lo_as[0]~3_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|reg_file_|db_lo_as[0]~3_combout ), - .datad(\z80_|resets_|clrpc~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [0]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[0] .lut_mask = 16'h00F0; -defparam \z80_|address_latch_|abusz[0] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N22 -cycloneive_lcell_comb \z80_|address_latch_|Q[0]~feeder ( -// Equation(s): -// \z80_|address_latch_|Q[0]~feeder_combout = \z80_|address_latch_|abusz [0] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [0]), - .cin(gnd), - .combout(\z80_|address_latch_|Q[0]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|Q[0]~feeder .lut_mask = 16'hFF00; -defparam \z80_|address_latch_|Q[0]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N23 -dffeas \z80_|address_latch_|Q[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|Q[0]~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[0] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N4 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout = \z80_|address_latch_|Q [0] $ (((\z80_|execute_|ctl_inc_dec~9_combout ) # ((\z80_|execute_|ctl_inc_dec~7_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout )))) - - .dataa(\z80_|execute_|ctl_inc_dec~9_combout ), - .datab(\z80_|execute_|ctl_inc_dec~6_combout ), - .datac(\z80_|address_latch_|Q [0]), - .datad(\z80_|execute_|ctl_inc_dec~7_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 .lut_mask = 16'h0F4B; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y17_N5 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[1]~6_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X31_Y13_N23 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[1]~6_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N22 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~4 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[1]~4_combout = (\z80_|reg_file_|gdfx_temp0[1]~32_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) # (!\z80_|reg_file_|gdfx_temp0[1]~32_combout & -// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [1]), - .datad(\z80_|execute_|ctl_sw_4d~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[1]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[1]~4 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_lo_as[1]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N26 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~5 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[1]~5_combout = (\z80_|reg_file_|db_lo_as[1]~4_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_lo|latch [1]), - .datad(\z80_|reg_file_|db_lo_as[1]~4_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[1]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[1]~5 .lut_mask = 16'hF300; -defparam \z80_|reg_file_|db_lo_as[1]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N24 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout = \z80_|address_latch_|Q [1] $ (((\z80_|execute_|ctl_inc_cy~85_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ))) - - .dataa(\z80_|address_latch_|Q [1]), - .datab(\z80_|execute_|ctl_inc_cy~85_combout ), - .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out .lut_mask = 16'h6A6A; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N4 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~6 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[1]~6_combout = ((\z80_|reg_file_|db_lo_as[1]~5_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[1]~5_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[1]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[1]~6 .lut_mask = 16'hAF2F; -defparam \z80_|reg_file_|db_lo_as[1]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N14 -cycloneive_lcell_comb \z80_|address_latch_|abusz[1] ( -// Equation(s): -// \z80_|address_latch_|abusz [1] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[1]~6_combout ) - - .dataa(gnd), - .datab(\z80_|resets_|clrpc~0_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|db_lo_as[1]~6_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [1]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[1] .lut_mask = 16'h3300; -defparam \z80_|address_latch_|abusz[1] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y17_N19 -dffeas \z80_|address_latch_|Q[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|address_latch_|abusz [1]), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[1] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N6 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout = \z80_|address_latch_|Q [1] $ ((((\z80_|execute_|ctl_inc_dec~10_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )) # (!\z80_|execute_|ctl_inc_dec~5_combout ))) - - .dataa(\z80_|execute_|ctl_inc_dec~5_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .datac(\z80_|address_latch_|Q [1]), - .datad(\z80_|execute_|ctl_inc_dec~10_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4 .lut_mask = 16'h0F87; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N22 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout = \z80_|address_latch_|Q [2] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout & (\z80_|execute_|ctl_inc_cy~85_combout & -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout )))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), - .datab(\z80_|execute_|ctl_inc_cy~85_combout ), - .datac(\z80_|address_latch_|Q [2]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out .lut_mask = 16'h78F0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N16 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~9 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[2]~9_combout = ((\z80_|reg_file_|db_lo_as[2]~8_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|reg_file_|db_lo_as[2]~8_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[2]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[2]~9 .lut_mask = 16'hF575; -defparam \z80_|reg_file_|db_lo_as[2]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N12 -cycloneive_lcell_comb \z80_|address_latch_|abusz[2] ( -// Equation(s): -// \z80_|address_latch_|abusz [2] = (\z80_|reg_file_|db_lo_as[2]~9_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[2]~9_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|resets_|clrpc~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [2]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[2] .lut_mask = 16'h00AA; -defparam \z80_|address_latch_|abusz[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N14 -cycloneive_lcell_comb \z80_|address_latch_|Q[2]~feeder ( -// Equation(s): -// \z80_|address_latch_|Q[2]~feeder_combout = \z80_|address_latch_|abusz [2] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [2]), - .cin(gnd), - .combout(\z80_|address_latch_|Q[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|Q[2]~feeder .lut_mask = 16'hFF00; -defparam \z80_|address_latch_|Q[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y17_N15 -dffeas \z80_|address_latch_|Q[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|Q[2]~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[2] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N2 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout = \z80_|address_latch_|Q [2] $ (((\z80_|execute_|ctl_inc_dec~10_combout ) # ((!\z80_|execute_|ctl_inc_dec~5_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) - - .dataa(\z80_|execute_|ctl_inc_dec~10_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .datac(\z80_|execute_|ctl_inc_dec~5_combout ), - .datad(\z80_|address_latch_|Q [2]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42 .lut_mask = 16'h40BF; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~86 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~86_combout = (\z80_|execute_|ctl_inc_cy~73_combout ) # ((\z80_|execute_|ctl_inc_cy~79_combout ) # ((\z80_|execute_|ctl_inc_cy~80_combout ) # (\z80_|execute_|ctl_inc_cy~83_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~73_combout ), - .datab(\z80_|execute_|ctl_inc_cy~79_combout ), - .datac(\z80_|execute_|ctl_inc_cy~80_combout ), - .datad(\z80_|execute_|ctl_inc_cy~83_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~86_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~86 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_inc_cy~86 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N0 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout & ((\z80_|execute_|ctl_inc_cy~46_combout ) # ((\z80_|execute_|ctl_inc_cy~86_combout ) # -// (\z80_|execute_|ctl_inc_cy~70_combout )))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), - .datab(\z80_|execute_|ctl_inc_cy~46_combout ), - .datac(\z80_|execute_|ctl_inc_cy~86_combout ), - .datad(\z80_|execute_|ctl_inc_cy~70_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'hAAA8; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~11 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~11_combout = (\z80_|execute_|ctl_inc_dec~9_combout ) # (((!\z80_|execute_|ctl_bus_inc_oe~33_combout ) # (!\z80_|execute_|ctl_inc_dec~5_combout )) # (!\z80_|execute_|ctl_inc_dec~6_combout )) - - .dataa(\z80_|execute_|ctl_inc_dec~9_combout ), - .datab(\z80_|execute_|ctl_inc_dec~6_combout ), - .datac(\z80_|execute_|ctl_inc_dec~5_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~11 .lut_mask = 16'hBFFF; -defparam \z80_|execute_|ctl_inc_dec~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N0 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout = (\z80_|execute_|ctl_inc_cy~85_combout & ((\z80_|address_latch_|Q [1] & (!\z80_|execute_|ctl_inc_dec~11_combout & \z80_|address_latch_|Q [0])) # (!\z80_|address_latch_|Q -// [1] & (\z80_|execute_|ctl_inc_dec~11_combout & !\z80_|address_latch_|Q [0])))) - - .dataa(\z80_|address_latch_|Q [1]), - .datab(\z80_|execute_|ctl_inc_dec~11_combout ), - .datac(\z80_|address_latch_|Q [0]), - .datad(\z80_|execute_|ctl_inc_cy~85_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0 .lut_mask = 16'h2400; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N10 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout = \z80_|address_latch_|Q [3] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout -// ))) - - .dataa(gnd), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ), - .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ), - .datad(\z80_|address_latch_|Q [3]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out .lut_mask = 16'h3FC0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N15 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y10_N21 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~45 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~45_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [3]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [3]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~45 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[3]~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N26 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp0[3]~52_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y11_N27 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y11_N11 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~48 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~48_combout = (\z80_|reg_file_|b2v_latch_ix_lo|latch [3] & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # (!\z80_|reg_file_|b2v_latch_ix_lo|latch [3] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_ix_lo|latch [3]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc_lo|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~48 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[3]~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y10_N5 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y10_N11 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~49 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~49_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [3]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_iy_lo|latch [3]), - .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~49 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[3]~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N12 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp0[3]~52_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y11_N13 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y11_N27 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~41 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~41_combout = ((!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ), - .datac(\z80_|execute_|nextM~2_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~41 .lut_mask = 16'h3F3B; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~42 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~42_combout = ((\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mRead~5_combout ) # (!\z80_|execute_|ctl_al_we~14_combout )))) # (!\z80_|execute_|setM1~29_combout ) - - .dataa(\z80_|execute_|ctl_mRead~5_combout ), - .datab(\z80_|execute_|setM1~29_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_al_we~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~42 .lut_mask = 16'hB3F3; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~43 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~43_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ) # ((!\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout & !\z80_|execute_|rsel3~combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ), - .datab(\z80_|execute_|rsel3~combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~43 .lut_mask = 16'hFFF1; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~44 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~44_combout = ((\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ) # ((!\z80_|execute_|rsel0~combout & \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ), - .datab(\z80_|execute_|rsel0~combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~44 .lut_mask = 16'hF7F5; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~45 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~45_combout = ((\z80_|execute_|ctl_state_alu~5_combout & ((!\z80_|execute_|setM1~46_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout )))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), - .datab(\z80_|execute_|ctl_state_alu~5_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), - .datad(\z80_|execute_|setM1~46_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~45 .lut_mask = 16'h5DDD; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~46 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout = ((\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ) # (!\z80_|execute_|ctl_reg_gp_we~2_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~46 .lut_mask = 16'hFDFF; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N14 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_48 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_48~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_de~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_de~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_48 .lut_mask = 16'h0C00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N20 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_44 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_44~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_de2~4_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_de2~4_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_44 .lut_mask = 16'h0C00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N4 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_45 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_45~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_de2~4_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_de2~4_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_45 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y13_N15 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N6 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_49 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_49~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_de~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_de~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_49 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y13_N1 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~40 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~40_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [3]), - .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [3]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~40 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[3]~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N12 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_52 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_52~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl2~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_52 .lut_mask = 16'h0C00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N18 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_57 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_57~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_57 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N9 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N16 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_53 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_53~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl2~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_53 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N19 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N30 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_56 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_56~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_56 .lut_mask = 16'h0C00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~41 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~41_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [3]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [3]), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~41 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp1[3]~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N26 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_33 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_33~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_af~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_af~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_33 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y14_N5 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N4 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[3]~18 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[3]~18_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [3]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [3]), - .datad(\z80_|reg_control_|reg_sel_af~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[3]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[3]~18 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[3]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~11 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~11_combout = (((\z80_|pla_decode_|Equal9~1_combout & \z80_|execute_|ixy_d~6_combout )) # (!\z80_|execute_|ctl_reg_in_hi~5_combout )) # (!\z80_|execute_|ctl_reg_in_hi~6_combout ) - - .dataa(\z80_|pla_decode_|Equal9~1_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~6_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~11 .lut_mask = 16'hB3FF; -defparam \z80_|execute_|ctl_reg_in_hi~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~12 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~12_combout = (\z80_|execute_|ctl_reg_in_hi~11_combout ) # (((!\z80_|execute_|ctl_reg_in_hi~4_combout ) # (!\z80_|execute_|ctl_reg_in_hi~3_combout )) # (!\z80_|execute_|ctl_reg_in_hi~10_combout )) - - .dataa(\z80_|execute_|ctl_reg_in_hi~11_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~10_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~3_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~12 .lut_mask = 16'hBFFF; -defparam \z80_|execute_|ctl_reg_in_hi~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N12 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_29 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_29~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_af2~0_combout & \z80_|execute_|ctl_reg_gp_we~6_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datab(gnd), - .datac(\z80_|reg_control_|reg_sel_af2~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_29 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y11_N19 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N2 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_28 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_28~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_af2~0_combout & !\z80_|execute_|ctl_reg_gp_we~6_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datab(gnd), - .datac(\z80_|reg_control_|reg_sel_af2~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_28 .lut_mask = 16'h00A0; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~44 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~44_combout = (\z80_|alu_|db[3]~11_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[3]~11_combout & (!\z80_|execute_|ctl_reg_in_hi~12_combout & -// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|alu_|db[3]~11_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~44 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[3]~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N8 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp1[3]~48_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N12 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_69 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_69~combout = (\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & \z80_|reg_control_|reg_sel_iy~2_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datad(\z80_|reg_control_|reg_sel_iy~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y12_N9 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N24 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout = (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(gnd), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 .lut_mask = 16'h4444; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N2 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|decode_state_|DFFE_inst4~q & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|decode_state_|DFFE_inst4~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 .lut_mask = 16'h4000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N8 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & \z80_|execute_|ctl_reg_gp_we~6_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 .lut_mask = 16'hF000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N4 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout = (\z80_|decode_state_|DFFE_inst4~q & (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 .lut_mask = 16'h0080; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y12_N29 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N14 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_68 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_68~combout = (!\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & \z80_|reg_control_|reg_sel_iy~2_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datad(\z80_|reg_control_|reg_sel_iy~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68 .lut_mask = 16'h3000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~43 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~43_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [3] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [3] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [3]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~43 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[3]~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N20 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N22 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout = (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y15_N23 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~31 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~31_combout = (!\z80_|ir_|opcode [3] & ((\z80_|execute_|ctl_alu_op_low~14_combout ) # ((\z80_|pla_decode_|Equal48~0_combout & \z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal48~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~31 .lut_mask = 16'h5450; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~30 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~30_combout = ((\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ) # ((\z80_|pla_decode_|Equal35~0_combout & \z80_|execute_|ixy_d~6_combout ))) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ) - - .dataa(\z80_|pla_decode_|Equal35~0_combout ), - .datab(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~30 .lut_mask = 16'hFFB3; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~32 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~32_combout = (((\z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ) # (\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout )) # (!\z80_|execute_|ctl_reg_out_hi~4_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), - .datab(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~32 .lut_mask = 16'hFFF7; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~33 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~33_combout = ((\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ) # ((!\z80_|execute_|ctl_reg_in_hi~5_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ))) # (!\z80_|execute_|ctl_reg_sel_wz~12_combout ) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~12_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~33 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N30 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_hi~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_hi~0_combout = ((\z80_|execute_|ixy_d~6_combout & ((\z80_|pla_decode_|Equal19~0_combout ) # (\z80_|execute_|ctl_reg_sys_we_lo~3_combout )))) # (!\z80_|execute_|ctl_reg_sel_wz~13_combout ) - - .dataa(\z80_|pla_decode_|Equal19~0_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~13_combout ), - .datac(\z80_|execute_|ctl_reg_sys_we_lo~3_combout ), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_hi~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_hi~0 .lut_mask = 16'hFB33; -defparam \z80_|reg_control_|reg_sys_we_hi~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N14 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_hi ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_hi~combout = ((\z80_|reg_control_|reg_sys_we_hi~0_combout ) # (\z80_|execute_|ctl_reg_sys_we~3_combout )) # (!\z80_|execute_|ctl_reg_in_hi~4_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_in_hi~4_combout ), - .datac(\z80_|reg_control_|reg_sys_we_hi~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_we~3_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_hi~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_hi .lut_mask = 16'hFFF3; -defparam \z80_|reg_control_|reg_sys_we_hi .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N4 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_81 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_81~combout = (\z80_|execute_|ctl_reg_sel_wz~17_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & \z80_|reg_control_|reg_sys_we_hi~combout )) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~17_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_81 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y12_N27 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N22 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_80 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_80~combout = (\z80_|execute_|ctl_reg_sel_wz~17_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & !\z80_|reg_control_|reg_sys_we_hi~combout )) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~17_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_80 .lut_mask = 16'h00A0; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~45 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~45_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [3]), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~45 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[3]~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N6 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & (!\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), - .datab(\z80_|reg_control_|bank_exx~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 .lut_mask = 16'h0002; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y13_N1 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N10 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|reg_control_|bank_exx~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 .lut_mask = 16'h0400; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N16 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & (\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), - .datab(\z80_|reg_control_|bank_exx~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 .lut_mask = 16'h0008; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y13_N3 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N4 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|reg_control_|bank_exx~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 .lut_mask = 16'h0100; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~42 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~42_combout = (\z80_|reg_file_|b2v_latch_bc_hi|latch [3] & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_hi|latch [3] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc_hi|latch [3]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~42 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[3]~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~46 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~46_combout = (\z80_|reg_file_|gdfx_temp1[3]~44_combout & (\z80_|reg_file_|gdfx_temp1[3]~43_combout & (\z80_|reg_file_|gdfx_temp1[3]~45_combout & \z80_|reg_file_|gdfx_temp1[3]~42_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[3]~44_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[3]~43_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[3]~45_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[3]~42_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~46 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[3]~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~47 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~47_combout = (\z80_|reg_file_|gdfx_temp1[3]~40_combout & (\z80_|reg_file_|gdfx_temp1[3]~41_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[3]~18_combout & \z80_|reg_file_|gdfx_temp1[3]~46_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[3]~40_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[3]~41_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|db[3]~18_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[3]~46_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~47 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[3]~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~17 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~17_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ) # ((\z80_|reg_control_|reg_sel_af~0_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) - - .dataa(\z80_|reg_control_|reg_sel_af~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~17 .lut_mask = 16'hFFF8; -defparam \z80_|reg_file_|gdfx_temp1[0]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~18 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~18_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~18 .lut_mask = 16'hFEFE; -defparam \z80_|reg_file_|gdfx_temp1[0]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~19 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~19_combout = (\z80_|reg_file_|gdfx_temp1[0]~17_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ) # ((\z80_|reg_file_|gdfx_temp1[0]~18_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~17_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[0]~18_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~19 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp1[0]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~16 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~16_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~16 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp1[0]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~20 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~20_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout ) # ((\z80_|reg_file_|gdfx_temp1[0]~19_combout ) # ((\z80_|execute_|ctl_sw_4u~6_combout ) # (\z80_|reg_file_|gdfx_temp1[0]~16_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~19_combout ), - .datac(\z80_|execute_|ctl_sw_4u~6_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[0]~16_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~20 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp1[0]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N10 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_73 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_73~combout = (\z80_|reg_control_|reg_sel_pc~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & \z80_|reg_control_|reg_sys_we_hi~combout )) - - .dataa(\z80_|reg_control_|reg_sel_pc~combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_73 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N13 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[1]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y13_N19 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y13_N25 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~8 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~8_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [1]), - .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [1]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~8 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[1]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y14_N3 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N2 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[1]~15 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[1]~15_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [1]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [1]), - .datad(\z80_|reg_control_|reg_sel_af~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[1]~15 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y15_N9 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y12_N11 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~13 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~13_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [1]), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~13 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[1]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y11_N21 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~12 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~12_combout = (\z80_|alu_|db[1]~13_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[1]~13_combout & (!\z80_|execute_|ctl_reg_in_hi~12_combout & -// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|alu_|db[1]~13_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~12 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[1]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y13_N5 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y13_N31 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~10 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~10_combout = (\z80_|reg_file_|b2v_latch_bc_hi|latch [1] & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_hi|latch [1] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc_hi|latch [1]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~10 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[1]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y12_N21 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N28 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder_combout = \z80_|reg_file_|gdfx_temp1[1]~21_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y12_N29 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~11 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~11_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [1]), - .datad(\z80_|reg_file_|b2v_latch_iy_hi|latch [1]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~11 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[1]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~14 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~14_combout = (\z80_|reg_file_|gdfx_temp1[1]~13_combout & (\z80_|reg_file_|gdfx_temp1[1]~12_combout & (\z80_|reg_file_|gdfx_temp1[1]~10_combout & \z80_|reg_file_|gdfx_temp1[1]~11_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[1]~13_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[1]~12_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[1]~10_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[1]~11_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~14 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[1]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N15 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y14_N17 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~9 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~9_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [1]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [1]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~9 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[1]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~15 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~15_combout = (\z80_|reg_file_|gdfx_temp1[1]~8_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[1]~15_combout & (\z80_|reg_file_|gdfx_temp1[1]~14_combout & \z80_|reg_file_|gdfx_temp1[1]~9_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[1]~8_combout ), - .datab(\z80_|reg_file_|b2v_latch_af_hi|db[1]~15_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[1]~14_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[1]~9_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~15 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~21 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~21_combout = ((\z80_|reg_file_|gdfx_temp1[1]~15_combout & ((\z80_|reg_file_|db_hi_as[1]~3_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[1]~15_combout ), - .datac(\z80_|reg_file_|db_hi_as[1]~3_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~21 .lut_mask = 16'hD5DD; -defparam \z80_|reg_file_|gdfx_temp1[1]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N28 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_60 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_60~combout = (!\z80_|reg_control_|reg_sys_we_hi~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & \z80_|execute_|ctl_reg_sel_ir~1_combout )) - - .dataa(\z80_|reg_control_|reg_sys_we_hi~combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datad(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_60 .lut_mask = 16'h5000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_60 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N16 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_61 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_61~combout = (\z80_|reg_control_|reg_sys_we_hi~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & \z80_|execute_|ctl_reg_sel_ir~1_combout )) - - .dataa(\z80_|reg_control_|reg_sys_we_hi~combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datad(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_61 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_61 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y15_N17 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[1]~3_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N6 -cycloneive_lcell_comb \z80_|reg_control_|reg_sw_4d_hi~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sw_4d_hi~0_combout = (\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_control_|reg_sys_we_lo~combout ) # ((!\z80_|execute_|ctl_reg_sel_ir~1_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout )))) - - .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), - .datab(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datad(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sw_4d_hi~0 .lut_mask = 16'h8AAA; -defparam \z80_|reg_control_|reg_sw_4d_hi~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N16 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~0 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[1]~0_combout = (\z80_|reg_file_|gdfx_temp1[1]~21_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) # (!\z80_|reg_file_|gdfx_temp1[1]~21_combout & -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [1]), - .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[1]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[1]~0 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_hi_as[1]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N12 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_72 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_72~combout = (\z80_|reg_control_|reg_sel_pc~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & !\z80_|reg_control_|reg_sys_we_hi~combout )) - - .dataa(\z80_|reg_control_|reg_sel_pc~combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_72 .lut_mask = 16'h00A0; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_72 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N10 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~1 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[1]~1_combout = (\z80_|reg_file_|db_hi_as[1]~0_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|b2v_latch_pc_hi|latch [1]), - .datab(gnd), - .datac(\z80_|reg_file_|db_hi_as[1]~0_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[1]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[1]~1 .lut_mask = 16'hA0F0; -defparam \z80_|reg_file_|db_hi_as[1]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N30 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~2 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[0]~2_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ) # ((\z80_|execute_|ctl_bus_inc_oe~41_combout ) # (\z80_|reg_control_|reg_sw_4d_hi~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[0]~2 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|db_hi_as[0]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N2 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout = \z80_|address_latch_|Q [8] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout & (\z80_|address_latch_|Q [7] $ (\z80_|execute_|ctl_inc_dec~11_combout ))))) - - .dataa(\z80_|address_latch_|Q [7]), - .datab(\z80_|address_latch_|Q [8]), - .datac(\z80_|execute_|ctl_inc_dec~11_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out .lut_mask = 16'h96CC; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y15_N27 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[0]~6_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y14_N3 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y14_N1 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~23 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~23_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [0]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [0]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~23 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[0]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y13_N7 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y13_N29 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~22 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~22_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [0]), - .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [0]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~22 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[0]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y13_N21 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y13_N7 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~24 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~24_combout = (\z80_|reg_file_|b2v_latch_bc2_hi|latch [0] & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # (!\z80_|reg_file_|b2v_latch_bc2_hi|latch [0] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc_hi|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~24 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[0]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y11_N15 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~26 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~26_combout = (\z80_|alu_|db[0]~19_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[0]~19_combout & (!\z80_|execute_|ctl_reg_in_hi~12_combout & -// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|alu_|db[0]~19_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~26 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[0]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N26 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder_combout = \z80_|reg_file_|gdfx_temp1[0]~30_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y12_N27 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y12_N5 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~25 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~25_combout = (\z80_|reg_file_|b2v_latch_ix_hi|latch [0] & (((\z80_|reg_file_|b2v_latch_iy_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ))) # (!\z80_|reg_file_|b2v_latch_ix_hi|latch [0] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & ((\z80_|reg_file_|b2v_latch_iy_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_ix_hi|latch [0]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datac(\z80_|reg_file_|b2v_latch_iy_hi|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~25 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[0]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y14_N13 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X26_Y14_N7 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~27 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~27_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (\z80_|reg_file_|b2v_latch_wz_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (((\z80_|reg_file_|b2v_latch_sp_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_sp_hi|latch [0]), - .datad(\z80_|reg_file_|b2v_latch_wz_hi|latch [0]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~27 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[0]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~28 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~28_combout = (\z80_|reg_file_|gdfx_temp1[0]~24_combout & (\z80_|reg_file_|gdfx_temp1[0]~26_combout & (\z80_|reg_file_|gdfx_temp1[0]~25_combout & \z80_|reg_file_|gdfx_temp1[0]~27_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~24_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~26_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[0]~25_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[0]~27_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~28 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[0]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y14_N29 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N28 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[0]~16 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[0]~16_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [0]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [0]), - .datad(\z80_|reg_control_|reg_sel_af~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[0]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[0]~16 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[0]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~29 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~29_combout = (\z80_|reg_file_|gdfx_temp1[0]~23_combout & (\z80_|reg_file_|gdfx_temp1[0]~22_combout & (\z80_|reg_file_|gdfx_temp1[0]~28_combout & \z80_|reg_file_|b2v_latch_af_hi|db[0]~16_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~23_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~22_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[0]~28_combout ), - .datad(\z80_|reg_file_|b2v_latch_af_hi|db[0]~16_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~29 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[0]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~30 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~30_combout = ((\z80_|reg_file_|gdfx_temp1[0]~29_combout & ((\z80_|reg_file_|db_hi_as[0]~6_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|db_hi_as[0]~6_combout ), - .datab(\z80_|execute_|ctl_sw_4u~6_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[0]~29_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~30 .lut_mask = 16'hBF0F; -defparam \z80_|reg_file_|gdfx_temp1[0]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y15_N21 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[0]~6_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N20 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~4 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[0]~4_combout = (\z80_|reg_control_|reg_sw_4d_hi~0_combout & (\z80_|reg_file_|gdfx_temp1[0]~30_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) - - .dataa(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[0]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[0]~4 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|db_hi_as[0]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N24 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~5 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[0]~5_combout = (\z80_|reg_file_|db_hi_as[0]~4_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datab(gnd), - .datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [0]), - .datad(\z80_|reg_file_|db_hi_as[0]~4_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[0]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[0]~5 .lut_mask = 16'hF500; -defparam \z80_|reg_file_|db_hi_as[0]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N26 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~6 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[0]~6_combout = ((\z80_|reg_file_|db_hi_as[0]~5_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), - .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datad(\z80_|reg_file_|db_hi_as[0]~5_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[0]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[0]~6 .lut_mask = 16'hDF0F; -defparam \z80_|reg_file_|db_hi_as[0]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N8 -cycloneive_lcell_comb \z80_|address_latch_|abusz[8] ( -// Equation(s): -// \z80_|address_latch_|abusz [8] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[0]~6_combout ) - - .dataa(\z80_|resets_|clrpc~0_combout ), - .datab(gnd), - .datac(\z80_|reg_file_|db_hi_as[0]~6_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [8]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[8] .lut_mask = 16'h5050; -defparam \z80_|address_latch_|abusz[8] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y16_N9 -dffeas \z80_|address_latch_|Q[8] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [8]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [8]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[8] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N18 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout & ((\z80_|address_latch_|Q [7] & (\z80_|address_latch_|Q [8] & !\z80_|execute_|ctl_inc_dec~11_combout -// )) # (!\z80_|address_latch_|Q [7] & (!\z80_|address_latch_|Q [8] & \z80_|execute_|ctl_inc_dec~11_combout )))) - - .dataa(\z80_|address_latch_|Q [7]), - .datab(\z80_|address_latch_|Q [8]), - .datac(\z80_|execute_|ctl_inc_dec~11_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 .lut_mask = 16'h1800; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N20 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout = \z80_|address_latch_|Q [9] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|address_latch_|Q [9]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out .lut_mask = 16'h0FF0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N12 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~3 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[1]~3_combout = ((\z80_|reg_file_|db_hi_as[1]~1_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_hi_as[1]~1_combout ), - .datab(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[1]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[1]~3 .lut_mask = 16'hBB3B; -defparam \z80_|reg_file_|db_hi_as[1]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N24 -cycloneive_lcell_comb \z80_|address_latch_|abusz[9] ( -// Equation(s): -// \z80_|address_latch_|abusz [9] = (\z80_|reg_file_|db_hi_as[1]~3_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(gnd), - .datab(\z80_|reg_file_|db_hi_as[1]~3_combout ), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [9]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[9] .lut_mask = 16'h0C0C; -defparam \z80_|address_latch_|abusz[9] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N4 -cycloneive_lcell_comb \z80_|address_latch_|Q[9]~feeder ( -// Equation(s): -// \z80_|address_latch_|Q[9]~feeder_combout = \z80_|address_latch_|abusz [9] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [9]), - .cin(gnd), - .combout(\z80_|address_latch_|Q[9]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|Q[9]~feeder .lut_mask = 16'hFF00; -defparam \z80_|address_latch_|Q[9]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N5 -dffeas \z80_|address_latch_|Q[9] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|Q[9]~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [9]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[9] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[9] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N30 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout = \z80_|address_latch_|Q [10] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout & (\z80_|address_latch_|Q [9] $ -// (\z80_|execute_|ctl_inc_dec~11_combout ))))) - - .dataa(\z80_|address_latch_|Q [10]), - .datab(\z80_|address_latch_|Q [9]), - .datac(\z80_|execute_|ctl_inc_dec~11_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out .lut_mask = 16'h96AA; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N7 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y14_N13 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~32 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~32_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [2]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [2]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~32 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[2]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y11_N25 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~35 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~35_combout = (\z80_|alu_|db[2]~15_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[2]~15_combout & (!\z80_|execute_|ctl_reg_in_hi~12_combout & -// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|alu_|db[2]~15_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~35 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[2]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y12_N19 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N18 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp1[2]~39_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y12_N19 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~34 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~34_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [2]), - .datad(\z80_|reg_file_|b2v_latch_iy_hi|latch [2]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~34 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[2]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N16 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp1[2]~39_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y13_N17 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y13_N15 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~33 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~33_combout = (\z80_|reg_file_|b2v_latch_bc_hi|latch [2] & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_hi|latch [2] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc_hi|latch [2]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~33 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[2]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y15_N21 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y12_N1 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~36 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~36_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [2]), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~36 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[2]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~37 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~37_combout = (\z80_|reg_file_|gdfx_temp1[2]~35_combout & (\z80_|reg_file_|gdfx_temp1[2]~34_combout & (\z80_|reg_file_|gdfx_temp1[2]~33_combout & \z80_|reg_file_|gdfx_temp1[2]~36_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[2]~35_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[2]~34_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[2]~33_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[2]~36_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~37 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[2]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y13_N5 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y13_N31 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~31 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~31_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datab(\z80_|reg_file_|b2v_latch_de_hi|latch [2]), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~31 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[2]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y14_N23 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N22 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[2]~17 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[2]~17_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [2]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [2]), - .datad(\z80_|reg_control_|reg_sel_af~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[2]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[2]~17 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[2]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y12_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~38 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~38_combout = (\z80_|reg_file_|gdfx_temp1[2]~32_combout & (\z80_|reg_file_|gdfx_temp1[2]~37_combout & (\z80_|reg_file_|gdfx_temp1[2]~31_combout & \z80_|reg_file_|b2v_latch_af_hi|db[2]~17_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[2]~32_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[2]~37_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[2]~31_combout ), - .datad(\z80_|reg_file_|b2v_latch_af_hi|db[2]~17_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~38 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[2]~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~39 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~39_combout = ((\z80_|reg_file_|gdfx_temp1[2]~38_combout & ((\z80_|reg_file_|db_hi_as[2]~9_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[2]~38_combout ), - .datab(\z80_|reg_file_|db_hi_as[2]~9_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~39 .lut_mask = 16'h8FAF; -defparam \z80_|reg_file_|gdfx_temp1[2]~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y15_N19 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[2]~9_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N18 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~7 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[2]~7_combout = (\z80_|reg_file_|gdfx_temp1[2]~39_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) # (!\z80_|reg_file_|gdfx_temp1[2]~39_combout & -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [2]), - .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[2]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[2]~7 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_hi_as[2]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y15_N9 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[2]~9_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N2 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~8 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[2]~8_combout = (\z80_|reg_file_|db_hi_as[2]~7_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datab(\z80_|reg_file_|db_hi_as[2]~7_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|b2v_latch_pc_hi|latch [2]), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[2]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[2]~8 .lut_mask = 16'hCC44; -defparam \z80_|reg_file_|db_hi_as[2]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N8 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~9 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[2]~9_combout = ((\z80_|reg_file_|db_hi_as[2]~8_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), - .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datad(\z80_|reg_file_|db_hi_as[2]~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[2]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[2]~9 .lut_mask = 16'hDF0F; -defparam \z80_|reg_file_|db_hi_as[2]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N0 -cycloneive_lcell_comb \z80_|address_latch_|abusz[10] ( -// Equation(s): -// \z80_|address_latch_|abusz [10] = (\z80_|reg_file_|db_hi_as[2]~9_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|reg_file_|db_hi_as[2]~9_combout ), - .datad(\z80_|resets_|clrpc~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [10]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[10] .lut_mask = 16'h00F0; -defparam \z80_|address_latch_|abusz[10] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N26 -cycloneive_lcell_comb \z80_|address_latch_|Q[10]~feeder ( -// Equation(s): -// \z80_|address_latch_|Q[10]~feeder_combout = \z80_|address_latch_|abusz [10] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [10]), - .cin(gnd), - .combout(\z80_|address_latch_|Q[10]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|Q[10]~feeder .lut_mask = 16'hFF00; -defparam \z80_|address_latch_|Q[10]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N27 -dffeas \z80_|address_latch_|Q[10] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|Q[10]~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [10]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[10] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[10] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N10 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout & ((\z80_|address_latch_|Q [10] & (\z80_|address_latch_|Q [9] & -// !\z80_|execute_|ctl_inc_dec~11_combout )) # (!\z80_|address_latch_|Q [10] & (!\z80_|address_latch_|Q [9] & \z80_|execute_|ctl_inc_dec~11_combout )))) - - .dataa(\z80_|address_latch_|Q [10]), - .datab(\z80_|address_latch_|Q [9]), - .datac(\z80_|execute_|ctl_inc_dec~11_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 .lut_mask = 16'h1800; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N14 -cycloneive_lcell_comb \z80_|address_latch_|abusz[11] ( -// Equation(s): -// \z80_|address_latch_|abusz [11] = (\z80_|reg_file_|db_hi_as[3]~12_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(gnd), - .datab(\z80_|reg_file_|db_hi_as[3]~12_combout ), - .datac(gnd), - .datad(\z80_|resets_|clrpc~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [11]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[11] .lut_mask = 16'h00CC; -defparam \z80_|address_latch_|abusz[11] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N15 -dffeas \z80_|address_latch_|Q[11] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [11]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [11]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[11] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[11] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N12 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[11] ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|address [11] = \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout $ (\z80_|address_latch_|Q [11]) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), - .datab(gnd), - .datac(\z80_|address_latch_|Q [11]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[11] .lut_mask = 16'h5A5A; -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[11] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N31 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[3]~12_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y15_N31 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[3]~12_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N30 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~10 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[3]~10_combout = (\z80_|reg_file_|gdfx_temp1[3]~48_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) # (!\z80_|reg_file_|gdfx_temp1[3]~48_combout & -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [3]), - .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[3]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[3]~10 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_hi_as[3]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N0 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~11 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[3]~11_combout = (\z80_|reg_file_|db_hi_as[3]~10_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|b2v_latch_pc_hi|latch [3]), - .datab(gnd), - .datac(\z80_|reg_file_|db_hi_as[3]~10_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[3]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[3]~11 .lut_mask = 16'hA0F0; -defparam \z80_|reg_file_|db_hi_as[3]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N30 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~12 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[3]~12_combout = ((\z80_|reg_file_|db_hi_as[3]~11_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [11]) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datad(\z80_|reg_file_|db_hi_as[3]~11_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[3]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[3]~12 .lut_mask = 16'hBF0F; -defparam \z80_|reg_file_|db_hi_as[3]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~48 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~48_combout = ((\z80_|reg_file_|gdfx_temp1[3]~47_combout & ((\z80_|reg_file_|db_hi_as[3]~12_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[3]~47_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datac(\z80_|reg_file_|db_hi_as[3]~12_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~48 .lut_mask = 16'hB3BB; -defparam \z80_|reg_file_|gdfx_temp1[3]~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N16 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & ((\z80_|alu_|db_low[3]~11_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~43_combout & !\z80_|alu_|db_high[3]~2_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .datab(\z80_|alu_|db_low[3]~11_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datad(\z80_|alu_|db_high[3]~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9 .lut_mask = 16'h888A; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_low ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_low~combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ixy_d~9_combout ) # ((\z80_|execute_|ixy_d~7_combout & !\z80_|ir_|opcode [3])))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_low .lut_mask = 16'hC0E0; -defparam \z80_|execute_|ctl_alu_op1_sel_low .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N6 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[3] ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_high|Q [3] = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & (\z80_|alu_|db_high[3]~8_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .datac(\z80_|alu_|db_high[3]~8_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [3]), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[3] .lut_mask = 16'h00C0; -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[3] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y10_N7 -dffeas \z80_|alu_|op1_high[3] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [3]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_high [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_high[3] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_high[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N10 -cycloneive_lcell_comb \z80_|alu_|alu_op1[3]~3 ( -// Equation(s): -// \z80_|alu_|alu_op1[3]~3_combout = (\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [3]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [3])) - - .dataa(gnd), - .datab(\z80_|alu_|op1_high [3]), - .datac(\z80_|alu_|op1_low [3]), - .datad(\z80_|execute_|ctl_alu_op_low~combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_op1[3]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op1[3]~3 .lut_mask = 16'hF0CC; -defparam \z80_|alu_|alu_op1[3]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N16 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout = (!\z80_|alu_|alu_op2[2]~0_combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_low [2]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_high -// [2])))) - - .dataa(\z80_|alu_|op1_high [2]), - .datab(\z80_|alu_|op1_low [2]), - .datac(\z80_|alu_|alu_op2[2]~0_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h0305; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~6_combout = ((\z80_|pla_decode_|Equal8~0_combout & (\z80_|execute_|ixy_d~5_combout & \z80_|execute_|ctl_mWrite~2_combout ))) # (!\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ) - - .dataa(\z80_|pla_decode_|Equal8~0_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ), - .datad(\z80_|execute_|ctl_mWrite~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~6 .lut_mask = 16'h8F0F; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~10_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ixy_d~15_combout & ((\z80_|execute_|ctl_bus_db_oe~1_combout ) # (!\z80_|sequencer_|DFFE_M3_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~10 .lut_mask = 16'hAAFB; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~0 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~0_combout = (\z80_|pla_decode_|Equal1~5_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~5_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|pla_decode_|Equal13~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~0 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_alu_core_R~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~5_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|execute_|ctl_alu_core_R~0_combout & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T3_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datad(\z80_|execute_|ctl_alu_core_R~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~5 .lut_mask = 16'hFEF0; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~7 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~7_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ) # (((\z80_|execute_|ctl_alu_op2_sel_bus~5_combout ) # (!\z80_|execute_|ctl_reg_use_sp~1_combout )) # (!\z80_|execute_|ctl_alu_op2_sel_bus~10_combout )) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), - .datab(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), - .datac(\z80_|execute_|ctl_reg_use_sp~1_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~7 .lut_mask = 16'hFFBF; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~8_combout = ((\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ) # ((\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_alu_shift_oe~14_combout ))) # (!\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~8 .lut_mask = 16'hFF8F; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N4 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout = (\z80_|alu_|db_low[1]~17_combout & ((\z80_|execute_|ctl_alu_op2_sel_lq~combout ) # ((\z80_|alu_|db_high[1]~20_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) # -// (!\z80_|alu_|db_low[1]~17_combout & (((\z80_|alu_|db_high[1]~20_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) - - .dataa(\z80_|alu_|db_low[1]~17_combout ), - .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datac(\z80_|alu_|db_high[1]~20_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5 .lut_mask = 16'hF888; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N0 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout ) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datab(gnd), - .datac(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6 .lut_mask = 16'h5050; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N16 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|ena ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|ena~combout = (\z80_|execute_|ctl_alu_op2_sel_zero~combout ) # ((\z80_|execute_|ctl_alu_op2_sel_lq~combout ) # (\z80_|execute_|ctl_alu_op2_sel_bus~8_combout )) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|ena .lut_mask = 16'hFFFA; -defparam \z80_|alu_|b2v_op2_latch_mux_high|ena .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y10_N1 -dffeas \z80_|alu_|op2_high[1] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_high [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_high[1] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_high[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N22 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[1] ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_high|Q [1] = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & (\z80_|alu_|db_high[1]~20_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .datac(\z80_|alu_|db_high[1]~20_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [1]), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[1] .lut_mask = 16'h00C0; -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[1] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y10_N23 -dffeas \z80_|alu_|op1_high[1] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [1]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_high [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_high[1] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_high[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N28 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [1])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [1]))))) - - .dataa(\z80_|alu_|op1_low [1]), - .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datac(\z80_|execute_|ctl_alu_op_low~combout ), - .datad(\z80_|alu_|op1_high [1]), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 .lut_mask = 16'h8C80; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N20 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ) # ((\z80_|alu_|db_low[1]~17_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datab(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ), - .datac(\z80_|alu_|db_low[1]~17_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 .lut_mask = 16'h5444; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y10_N21 -dffeas \z80_|alu_|op2_low[1] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_low [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_low[1] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_low[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~6_combout = (((!\z80_|nM1_int~2_combout & !\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal63~0_combout )) # (!\z80_|pla_decode_|Equal32~0_combout ) - - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal63~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~6 .lut_mask = 16'h57FF; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~20 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~20_combout = (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|pla_decode_|Equal68~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal68~2_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~20 .lut_mask = 16'h0D0F; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~12 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~12_combout = (\z80_|execute_|ctl_state_alu~9_combout ) # ((\z80_|execute_|ctl_reg_gp_sel~36_combout ) # ((\z80_|execute_|ctl_state_alu~11_combout ) # (!\z80_|execute_|ctl_state_alu~8_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~9_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel~36_combout ), - .datac(\z80_|execute_|ctl_state_alu~11_combout ), - .datad(\z80_|execute_|ctl_state_alu~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~12 .lut_mask = 16'hFEFF; -defparam \z80_|execute_|ctl_state_alu~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~18 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~18_combout = ((!\z80_|pla_decode_|Equal3~0_combout & ((\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal21~0_combout )))) # (!\z80_|execute_|ctl_state_alu~12_combout ) - - .dataa(\z80_|execute_|ctl_state_alu~12_combout ), - .datab(\z80_|pla_decode_|Equal3~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal21~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~18 .lut_mask = 16'h7577; -defparam \z80_|execute_|ctl_alu_core_hf~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N0 -cycloneive_lcell_comb \z80_|pla_decode_|Equal61~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal61~2_combout = (\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal6~0_combout & (!\z80_|ir_|opcode [1] & \z80_|ir_|opcode [0]))) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal61~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal61~2 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal61~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~16 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~16_combout = (\z80_|pla_decode_|Equal61~2_combout & ((\z80_|sequencer_|DFFE_M2_ff~q ) # (\z80_|sequencer_|DFFE_M4_ff~q ))) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|pla_decode_|Equal61~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~16 .lut_mask = 16'hFC00; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~17 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~17_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~6_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~20_combout & (\z80_|execute_|ctl_alu_core_hf~18_combout & !\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ))) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~20_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~18_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~17 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~21 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~21_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~17_combout & (((!\z80_|execute_|ctl_mWrite~16_combout ) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|execute_|ctl_mWrite~16_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~21 .lut_mask = 16'h7F00; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~15 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~15_combout = (((\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ) # (\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout )) # (!\z80_|execute_|ctl_alu_sel_op2_neg~4_combout )) # (!\z80_|execute_|ctl_reg_out_hi~4_combout -// ) - - .dataa(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~15 .lut_mask = 16'hFFF7; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~12 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~12_combout = (\z80_|execute_|ctl_flags_alu~17_combout & (\z80_|execute_|ctl_bus_inc_oe~43_combout & (\z80_|execute_|ctl_alu_core_S~4_combout & \z80_|execute_|ctl_alu_op1_sel_bus~8_combout ))) - - .dataa(\z80_|execute_|ctl_flags_alu~17_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .datac(\z80_|execute_|ctl_alu_core_S~4_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~12 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N6 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~22 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~22_combout = (\z80_|execute_|ctl_alu_shift_oe~38_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|execute_|ctl_ir_we~11_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~11_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~22 .lut_mask = 16'hC4CC; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~20 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~20_combout = ((\z80_|ir_|opcode [5]) # ((!\z80_|pla_decode_|Equal32~0_combout & !\z80_|pla_decode_|Equal9~0_combout ))) # (!\z80_|execute_|ctl_state_alu~12_combout ) - - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|pla_decode_|Equal9~0_combout ), - .datac(\z80_|execute_|ctl_state_alu~12_combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~20 .lut_mask = 16'hFF1F; -defparam \z80_|execute_|ctl_alu_core_hf~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~4_combout = (\z80_|execute_|ctl_flags_sz_we~0_combout & (((!\z80_|execute_|ctl_ir_we~12_combout & !\z80_|execute_|ctl_ir_we~11_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_flags_sz_we~0_combout ), - .datab(\z80_|execute_|ctl_ir_we~12_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_ir_we~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~4 .lut_mask = 16'h0A2A; -defparam \z80_|execute_|ctl_flags_sz_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N2 -cycloneive_lcell_comb \z80_|pla_decode_|Equal71~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal71~2_combout = (!\z80_|ir_|opcode [3] & (!\z80_|ir_|opcode [4] & (\z80_|execute_|ctl_state_alu~12_combout & \z80_|ir_|opcode [5]))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|execute_|ctl_state_alu~12_combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal71~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal71~2 .lut_mask = 16'h1000; -defparam \z80_|pla_decode_|Equal71~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N18 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~8 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~8_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~22_combout & (\z80_|execute_|ctl_alu_core_hf~20_combout & (\z80_|execute_|ctl_flags_sz_we~4_combout & !\z80_|pla_decode_|Equal71~2_combout ))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~22_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~20_combout ), - .datac(\z80_|execute_|ctl_flags_sz_we~4_combout ), - .datad(\z80_|pla_decode_|Equal71~2_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~8 .lut_mask = 16'h0080; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~31 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~31_combout = (!\z80_|execute_|ctl_alu_op_low~9_combout & (((!\z80_|sequencer_|DFFE_M4_ff~q ) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|pla_decode_|Equal13~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~9_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_M4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~31 .lut_mask = 16'h1333; -defparam \z80_|execute_|ctl_alu_op_low~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N22 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~4 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~4_combout = (\z80_|pla_decode_|Equal21~0_combout & ((\z80_|nM1_int~2_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout )))) # (!\z80_|pla_decode_|Equal21~0_combout & (\z80_|pla_decode_|Equal3~0_combout & -// ((\z80_|nM1_int~2_combout ) # (\z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal21~0_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal3~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~4 .lut_mask = 16'hFCA8; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout = (\z80_|pla_decode_|Equal13~1_combout & (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal6~0_combout & !\z80_|ir_|opcode [5]))) - - .dataa(\z80_|pla_decode_|Equal13~1_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N16 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~5 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~5_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout & \z80_|pla_decode_|Equal63~0_combout -// ))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), - .datac(\z80_|pla_decode_|Equal63~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~5 .lut_mask = 16'hFFEC; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N26 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~6 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~6_combout = (\z80_|execute_|ctl_alu_op_low~31_combout & (\z80_|execute_|ctl_flags_pf_we~10_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~7_combout & !\z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~31_combout ), - .datab(\z80_|execute_|ctl_flags_pf_we~10_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~6 .lut_mask = 16'h0080; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal72~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal72~2_combout = (\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [3] & \z80_|execute_|ctl_state_alu~12_combout ))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|execute_|ctl_state_alu~12_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal72~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal72~2 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal72~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y9_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal73~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal73~2_combout = (\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [3] & (!\z80_|ir_|opcode [4] & \z80_|execute_|ctl_state_alu~12_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|execute_|ctl_state_alu~12_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal73~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal73~2 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal73~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~0 ( -// Equation(s): -// \z80_|execute_|ctl_flags_nf_we~0_combout = (\z80_|pla_decode_|Equal61~2_combout & (!\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|execute_|ctl_mRead~36_combout )))) # (!\z80_|pla_decode_|Equal61~2_combout & -// (((!\z80_|execute_|ixy_d~5_combout )) # (!\z80_|execute_|ctl_mRead~36_combout ))) - - .dataa(\z80_|pla_decode_|Equal61~2_combout ), - .datab(\z80_|execute_|ctl_mRead~36_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_nf_we~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_nf_we~0 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_flags_nf_we~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~1 ( -// Equation(s): -// \z80_|execute_|ctl_flags_nf_we~1_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout & (!\z80_|pla_decode_|Equal72~2_combout & (!\z80_|pla_decode_|Equal73~2_combout & \z80_|execute_|ctl_flags_nf_we~0_combout ))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ), - .datab(\z80_|pla_decode_|Equal72~2_combout ), - .datac(\z80_|pla_decode_|Equal73~2_combout ), - .datad(\z80_|execute_|ctl_flags_nf_we~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_nf_we~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_nf_we~1 .lut_mask = 16'h0200; -defparam \z80_|execute_|ctl_flags_nf_we~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_nf_we~2_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal10~0_combout ) # ((\z80_|pla_decode_|Equal11~0_combout ) # (\z80_|pla_decode_|Equal61~2_combout )))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal61~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_nf_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_nf_we~2 .lut_mask = 16'hF0E0; -defparam \z80_|execute_|ctl_flags_nf_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_nf_we~3_combout = ((\z80_|execute_|ctl_flags_nf_we~2_combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~21_combout )) # (!\z80_|execute_|ctl_flags_nf_we~1_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_flags_nf_we~1_combout ), - .datac(\z80_|execute_|ctl_flags_nf_we~2_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~21_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_nf_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_nf_we~3 .lut_mask = 16'hF3FF; -defparam \z80_|execute_|ctl_flags_nf_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~5_combout = (\z80_|sequencer_|DFFE_T4_ff~q ) # ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~5 .lut_mask = 16'hFAFF; -defparam \z80_|execute_|ctl_flags_sz_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~6_combout = (\z80_|pla_decode_|Equal48~0_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # ((\z80_|execute_|ctl_flags_sz_we~5_combout & \z80_|execute_|ctl_alu_core_R~0_combout )))) # -// (!\z80_|pla_decode_|Equal48~0_combout & (\z80_|execute_|ctl_flags_sz_we~5_combout & ((\z80_|execute_|ctl_alu_core_R~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal48~0_combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~5_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_alu_core_R~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~6 .lut_mask = 16'hECA0; -defparam \z80_|execute_|ctl_flags_sz_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_nf_we~4_combout = (((\z80_|execute_|ctl_flags_nf_we~3_combout ) # (\z80_|execute_|ctl_flags_sz_we~6_combout )) # (!\z80_|execute_|ctl_flags_xy_we~12_combout )) # (!\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~12_combout ), - .datac(\z80_|execute_|ctl_flags_nf_we~3_combout ), - .datad(\z80_|execute_|ctl_flags_sz_we~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_nf_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_nf_we~4 .lut_mask = 16'hFFF7; -defparam \z80_|execute_|ctl_flags_nf_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y9_N12 -cycloneive_lcell_comb \z80_|execute_|setM1~15 ( -// Equation(s): -// \z80_|execute_|setM1~15_combout = (!\z80_|execute_|ctl_alu_shift_oe~15_combout & (\z80_|execute_|ctl_sw_2u~1_combout & \z80_|execute_|ctl_state_alu~8_combout )) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_sw_2u~1_combout ), - .datad(\z80_|execute_|ctl_state_alu~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~15 .lut_mask = 16'h5000; -defparam \z80_|execute_|setM1~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|setM1~16 ( -// Equation(s): -// \z80_|execute_|setM1~16_combout = (\z80_|execute_|setM1~15_combout & (!\z80_|execute_|ctl_alu_op1_sel_zero~4_combout & (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & \z80_|execute_|ctl_alu_op_low~31_combout ))) - - .dataa(\z80_|execute_|setM1~15_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datad(\z80_|execute_|ctl_alu_op_low~31_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~16 .lut_mask = 16'h0200; -defparam \z80_|execute_|setM1~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~6_combout = (!\z80_|execute_|ctl_reg_gp_sel~36_combout & \z80_|execute_|setM1~16_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_sel~36_combout ), - .datad(\z80_|execute_|setM1~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~6 .lut_mask = 16'h0F00; -defparam \z80_|execute_|ctl_flags_xy_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~7_combout = (\z80_|execute_|ctl_flags_pf_we~2_combout & (\z80_|execute_|ctl_flags_xy_we~17_combout & (\z80_|execute_|ctl_flags_xy_we~6_combout & \z80_|execute_|ctl_alu_oe~5_combout ))) - - .dataa(\z80_|execute_|ctl_flags_pf_we~2_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~17_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~6_combout ), - .datad(\z80_|execute_|ctl_alu_oe~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~7 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_xy_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~2_combout = (\z80_|execute_|ctl_flags_sz_we~1_combout & (\z80_|execute_|ctl_flags_xy_we~7_combout & \z80_|execute_|ctl_alu_op2_sel_bus~10_combout )) - - .dataa(\z80_|execute_|ctl_flags_sz_we~1_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~7_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~2 .lut_mask = 16'h8800; -defparam \z80_|execute_|ctl_flags_sz_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla12M1T1_12~0 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout = (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal11~1_combout & (!\z80_|ir_|opcode [2] & \z80_|execute_|ctl_mWrite~2_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal11~1_combout ), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|execute_|ctl_mWrite~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel_pla12M1T1_12~0 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_pf_sel_pla12M1T1_12~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~1 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~1_combout = (\z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ) # ((\z80_|execute_|ctl_alu_core_R~0_combout & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|execute_|ctl_alu_core_R~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~1 .lut_mask = 16'hFBAA; -defparam \z80_|execute_|ctl_alu_core_R~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~7_combout = (\z80_|execute_|ctl_alu_core_R~1_combout ) # (((\z80_|execute_|ixy_d~7_combout & \z80_|pla_decode_|Equal56~0_combout )) # (!\z80_|execute_|ctl_flags_alu~18_combout )) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~1_combout ), - .datac(\z80_|pla_decode_|Equal56~0_combout ), - .datad(\z80_|execute_|ctl_flags_alu~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~7 .lut_mask = 16'hECFF; -defparam \z80_|execute_|ctl_flags_alu~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N24 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~8 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~8_combout = (\z80_|reg_control_|reg_sys_we_lo~5_combout & (((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|pla_decode_|Equal56~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal56~0_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|reg_control_|reg_sys_we_lo~5_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~8 .lut_mask = 16'h7F00; -defparam \z80_|reg_control_|reg_sys_we_lo~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~8_combout = ((\z80_|execute_|ctl_flags_alu~7_combout ) # ((!\z80_|reg_control_|reg_sys_we_lo~8_combout ) # (!\z80_|execute_|ctl_flags_alu~16_combout ))) # (!\z80_|execute_|ctl_flags_alu~6_combout ) - - .dataa(\z80_|execute_|ctl_flags_alu~6_combout ), - .datab(\z80_|execute_|ctl_flags_alu~7_combout ), - .datac(\z80_|execute_|ctl_flags_alu~16_combout ), - .datad(\z80_|reg_control_|reg_sys_we_lo~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~8 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_flags_alu~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~16 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~16_combout = (\z80_|execute_|ctl_alu_op_low~10_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|pla_decode_|Equal20~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal20~0_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|execute_|ctl_alu_op_low~10_combout ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~16 .lut_mask = 16'hD0F0; -defparam \z80_|execute_|ctl_flags_xy_we~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~12 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~12_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~5_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout & ((!\z80_|execute_|ctl_mRead~36_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|ctl_mRead~36_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~12 .lut_mask = 16'h0070; -defparam \z80_|execute_|ctl_flags_alu~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~13 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~13_combout = (\z80_|execute_|ctl_flags_sz_we~4_combout & (\z80_|execute_|ctl_flags_xy_we~16_combout & (\z80_|execute_|ctl_sw_2d~4_combout & \z80_|execute_|ctl_flags_alu~12_combout ))) - - .dataa(\z80_|execute_|ctl_flags_sz_we~4_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~16_combout ), - .datac(\z80_|execute_|ctl_sw_2d~4_combout ), - .datad(\z80_|execute_|ctl_flags_alu~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~13 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_alu~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~14 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~14_combout = (\z80_|execute_|ctl_reg_use_sp~1_combout & (\z80_|execute_|ctl_alu_op_low~15_combout & (\z80_|execute_|ctl_sw_4u~1_combout & \z80_|execute_|ctl_flags_alu~13_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~1_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~15_combout ), - .datac(\z80_|execute_|ctl_sw_4u~1_combout ), - .datad(\z80_|execute_|ctl_flags_alu~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~14 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_alu~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~15 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~15_combout = ((\z80_|execute_|ctl_flags_alu~8_combout ) # ((!\z80_|execute_|ctl_flags_alu~11_combout ) # (!\z80_|execute_|ctl_flags_alu~14_combout ))) # (!\z80_|execute_|ctl_flags_sz_we~2_combout ) - - .dataa(\z80_|execute_|ctl_flags_sz_we~2_combout ), - .datab(\z80_|execute_|ctl_flags_alu~8_combout ), - .datac(\z80_|execute_|ctl_flags_alu~14_combout ), - .datad(\z80_|execute_|ctl_flags_alu~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~15 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_flags_alu~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [3] & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N12 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout = (\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ) # ((\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal10~0_combout ) # (\z80_|pla_decode_|Equal61~2_combout )))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal61~2_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 .lut_mask = 16'hFCEC; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~19 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~19_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal3~1_combout ))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal3~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~19 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N30 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ) # ((\z80_|execute_|ctl_alu_sel_op2_neg~19_combout ) # ((\z80_|alu_control_|db[1]~26_combout & \z80_|execute_|ctl_flags_bus~combout ))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~19_combout ), - .datac(\z80_|alu_control_|db[1]~26_combout ), - .datad(\z80_|execute_|ctl_flags_bus~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 .lut_mask = 16'hFEEE; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N20 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout = ((\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ) # ((\z80_|execute_|ctl_flags_alu~15_combout & \z80_|alu_|db_high[3]~8_combout ))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ) - - .dataa(\z80_|execute_|ctl_flags_alu~15_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), - .datac(\z80_|alu_|db_high[3]~8_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 .lut_mask = 16'hFFB3; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N20 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~7 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~7_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout & (((!\z80_|pla_decode_|Equal32~0_combout & !\z80_|pla_decode_|Equal21~0_combout )) # (!\z80_|pla_decode_|Equal62~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|pla_decode_|Equal62~2_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ), - .datad(\z80_|pla_decode_|Equal21~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~7 .lut_mask = 16'h3070; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N6 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~9 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~9_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~7_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~11_combout & (!\z80_|execute_|ctl_alu_core_R~1_combout & \z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~7_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~11_combout ), - .datac(\z80_|execute_|ctl_alu_core_R~1_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~9 .lut_mask = 16'h0800; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N26 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~10 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~10_combout = (\z80_|execute_|ctl_flags_nf_we~4_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout & ((\z80_|alu_flags_|DFFE_inst_latch_nf~9_combout )))) # (!\z80_|execute_|ctl_flags_nf_we~4_combout & -// (((\z80_|alu_flags_|DFFE_inst_latch_nf~q )))) - - .dataa(\z80_|execute_|ctl_flags_nf_we~4_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~9_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~10 .lut_mask = 16'hD850; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y9_N27 -dffeas \z80_|alu_flags_|DFFE_inst_latch_nf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|DFFE_inst_latch_nf~10_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~7 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~7_combout = ((\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # (\z80_|execute_|ctl_flags_cf2_sel_daa~combout )))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~7 .lut_mask = 16'hE0FF; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [3] & \z80_|execute_|ixy_d~7_combout ))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~10_combout = (\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ) # ((\z80_|pla_decode_|Equal61~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # (\z80_|nM1_int~2_combout )))) - - .dataa(\z80_|pla_decode_|Equal61~2_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~10 .lut_mask = 16'hFFA8; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~8_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (!\z80_|sequencer_|DFFE_T3_ff~q & ((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|sequencer_|DFFE_M3_ff~q )))) # (!\z80_|sequencer_|DFFE_M2_ff~q & -// (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|sequencer_|DFFE_M3_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~8 .lut_mask = 16'h7707; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~9_combout = ((\z80_|pla_decode_|Equal10~0_combout & ((\z80_|nM1_int~2_combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~8_combout )))) # (!\z80_|execute_|ctl_alu_op_low~33_combout ) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~33_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~9 .lut_mask = 16'hB3BB; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~11_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ) # ((\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ) # ((\z80_|execute_|ctl_alu_op_low~8_combout & \z80_|execute_|ctl_alu_op_low~12_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~12_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~11 .lut_mask = 16'hFFEC; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~14_combout = (((\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ) # (\z80_|execute_|ctl_alu_sel_op2_neg~11_combout )) # (!\z80_|execute_|ctl_alu_sel_op2_neg~12_combout )) # (!\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~14 .lut_mask = 16'hFFF7; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~18 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~18_combout = ((\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ) # ((\z80_|execute_|ctl_alu_sel_op2_neg~15_combout & \z80_|alu_flags_|DFFE_inst_latch_sf~q ))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~21_combout ) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~21_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~18 .lut_mask = 16'hFDF5; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_high ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_high~combout = ((\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|pla_decode_|Equal13~2_combout & \z80_|sequencer_|DFFE_M3_ff~q ))) # (!\z80_|execute_|ctl_alu_res_oe~2_combout ) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|pla_decode_|Equal13~2_combout ), - .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_high .lut_mask = 16'h8F0F; -defparam \z80_|execute_|ctl_alu_sel_op2_high .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N6 -cycloneive_lcell_comb \z80_|alu_|alu_op2[1]~1 ( -// Equation(s): -// \z80_|alu_|alu_op2[1]~1_combout = \z80_|execute_|ctl_alu_sel_op2_neg~18_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_high [1])) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_low [1]))))) - - .dataa(\z80_|alu_|op2_high [1]), - .datab(\z80_|alu_|op2_low [1]), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_op2[1]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op2[1]~1 .lut_mask = 16'h5A3C; -defparam \z80_|alu_|alu_op2[1]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N30 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout = (!\z80_|alu_|alu_op2[1]~1_combout & ((\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_low [1])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_high -// [1]))))) - - .dataa(\z80_|alu_|alu_op2[1]~1_combout ), - .datab(\z80_|alu_|op1_low [1]), - .datac(\z80_|execute_|ctl_alu_op_low~combout ), - .datad(\z80_|alu_|op1_high [1]), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'h1015; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~9_combout = (((\z80_|pla_decode_|Equal71~2_combout ) # (!\z80_|execute_|ctl_alu_core_S~11_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~10_combout )) # (!\z80_|execute_|ctl_alu_core_S~5_combout ) - - .dataa(\z80_|execute_|ctl_alu_core_S~5_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), - .datac(\z80_|execute_|ctl_alu_core_S~11_combout ), - .datad(\z80_|pla_decode_|Equal71~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~9 .lut_mask = 16'hFF7F; -defparam \z80_|execute_|ctl_alu_core_S~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N22 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout = (\z80_|alu_|db_high[0]~26_combout & ((\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ) # ((\z80_|alu_|db_low[0]~23_combout & \z80_|execute_|ctl_alu_op2_sel_lq~combout )))) # -// (!\z80_|alu_|db_high[0]~26_combout & (\z80_|alu_|db_low[0]~23_combout & (\z80_|execute_|ctl_alu_op2_sel_lq~combout ))) - - .dataa(\z80_|alu_|db_high[0]~26_combout ), - .datab(\z80_|alu_|db_low[0]~23_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7 .lut_mask = 16'hEAC0; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N6 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8_combout = (\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout & !\z80_|execute_|ctl_alu_op2_sel_zero~combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8 .lut_mask = 16'h00F0; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y10_N7 -dffeas \z80_|alu_|op2_high[0] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_high [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_high[0] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_high[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N2 -cycloneive_lcell_comb \z80_|alu_|alu_op2[0]~3 ( -// Equation(s): -// \z80_|alu_|alu_op2[0]~3_combout = \z80_|execute_|ctl_alu_sel_op2_neg~18_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [0]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [0])))) - - .dataa(\z80_|alu_|op2_low [0]), - .datab(\z80_|alu_|op2_high [0]), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_op2[0]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op2[0]~3 .lut_mask = 16'h3C5A; -defparam \z80_|alu_|alu_op2[0]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N0 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~12 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~12_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout & ((\z80_|ir_|opcode [3]) # ((!\z80_|ir_|opcode [4]) # (!\z80_|pla_decode_|Equal62~2_combout )))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal62~2_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~12 .lut_mask = 16'hB0F0; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~8_combout = (!\z80_|execute_|ctl_alu_core_R~1_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~6_combout & \z80_|execute_|ctl_alu_core_S~7_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_R~1_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~8 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_alu_core_S~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N2 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout = (((!\z80_|execute_|ctl_alu_core_S~9_combout & !\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout )) # (!\z80_|execute_|ctl_alu_core_S~8_combout )) # -// (!\z80_|execute_|ctl_alu_core_R~4_combout ) - - .dataa(\z80_|execute_|ctl_alu_core_S~9_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~4_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 .lut_mask = 16'h37FF; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~21 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~21_combout = (\z80_|execute_|ctl_alu_core_hf~20_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # ((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|execute_|ixy_d~15_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|execute_|ixy_d~15_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~20_combout ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~21 .lut_mask = 16'hB0F0; -defparam \z80_|execute_|ctl_alu_core_hf~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~22 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~22_combout = (((\z80_|execute_|ixy_d~8_combout & \z80_|pla_decode_|Equal21~1_combout )) # (!\z80_|execute_|ctl_alu_core_hf~21_combout )) # (!\z80_|execute_|ctl_alu_core_hf~18_combout ) - - .dataa(\z80_|execute_|ctl_alu_core_hf~18_combout ), - .datab(\z80_|execute_|ixy_d~8_combout ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~21_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~22 .lut_mask = 16'hD5FF; -defparam \z80_|execute_|ctl_alu_core_hf~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~19 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~19_combout = (\z80_|pla_decode_|Equal21~1_combout & ((\z80_|execute_|ctl_mRead~11_combout ) # ((\z80_|execute_|ixy_d~6_combout & !\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~11_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~19 .lut_mask = 16'hA0E0; -defparam \z80_|execute_|ctl_alu_core_hf~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~27 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~27_combout = (\z80_|execute_|ctl_alu_op_low~19_combout ) # (((\z80_|execute_|ctl_alu_op_low~22_combout ) # (!\z80_|execute_|ctl_alu_op_low~33_combout )) # (!\z80_|execute_|ctl_alu_op_low~17_combout )) - - .dataa(\z80_|execute_|ctl_alu_op_low~19_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~22_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~33_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~27 .lut_mask = 16'hFBFF; -defparam \z80_|execute_|ctl_alu_op_low~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~29 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~29_combout = (\z80_|execute_|ctl_alu_op_low~23_combout ) # ((\z80_|execute_|ctl_alu_op_low~34_combout ) # (\z80_|execute_|ctl_alu_op_low~27_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op_low~23_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~34_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~29 .lut_mask = 16'hFFFC; -defparam \z80_|execute_|ctl_alu_op_low~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~23 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~23_combout = (\z80_|execute_|ctl_alu_core_hf~22_combout & (((\z80_|execute_|ctl_alu_core_hf~19_combout & !\z80_|execute_|ctl_alu_op_low~29_combout )) # (!\z80_|execute_|ctl_alu_op_low~28_combout ))) # -// (!\z80_|execute_|ctl_alu_core_hf~22_combout & (\z80_|execute_|ctl_alu_core_hf~19_combout & (!\z80_|execute_|ctl_alu_op_low~29_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~22_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~19_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~29_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~28_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~23 .lut_mask = 16'h0CAE; -defparam \z80_|execute_|ctl_alu_core_hf~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~37 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~37_combout = (\z80_|pla_decode_|Equal39~0_combout ) # ((!\z80_|execute_|ixy_d~5_combout & \z80_|pla_decode_|Equal40~1_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|pla_decode_|Equal40~1_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~37 .lut_mask = 16'hFF30; -defparam \z80_|execute_|ctl_alu_core_hf~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~38 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~38_combout = (\z80_|execute_|ctl_alu_core_hf~37_combout & ((\z80_|execute_|ixy_d~6_combout ) # ((\z80_|execute_|ixy_d~8_combout & !\z80_|execute_|ixy_d~9_combout )))) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|execute_|ixy_d~8_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~37_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~38 .lut_mask = 16'hAE00; -defparam \z80_|execute_|ctl_alu_core_hf~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~24 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~24_combout = (\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (((!\z80_|pla_decode_|Equal32~0_combout ) # (!\z80_|pla_decode_|Equal63~0_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|pla_decode_|Equal63~0_combout ), - .datac(\z80_|pla_decode_|Equal32~0_combout ), - .datad(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~24 .lut_mask = 16'h7F00; -defparam \z80_|execute_|ctl_alu_core_hf~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~25 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~25_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # ((\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ) # ((!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & \z80_|execute_|ctl_alu_core_hf~24_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .datab(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~25 .lut_mask = 16'hEFEE; -defparam \z80_|execute_|ctl_alu_core_hf~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~26 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~26_combout = (\z80_|execute_|ctl_mRead~36_combout & ((\z80_|execute_|ctl_mRead~11_combout ) # ((\z80_|execute_|ixy_d~6_combout & !\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~36_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|execute_|ctl_mRead~11_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~26 .lut_mask = 16'hA0A8; -defparam \z80_|execute_|ctl_alu_core_hf~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~27 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~27_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ) # ((\z80_|execute_|ctl_alu_core_hf~26_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|execute_|ctl_mRead~36_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~36_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~26_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~27 .lut_mask = 16'hDFCC; -defparam \z80_|execute_|ctl_alu_core_hf~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~28 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~28_combout = (\z80_|execute_|ctl_alu_core_hf~25_combout & (((\z80_|execute_|ctl_alu_core_hf~27_combout & !\z80_|execute_|ctl_alu_op_low~27_combout )) # (!\z80_|execute_|ctl_alu_op_low~20_combout ))) # -// (!\z80_|execute_|ctl_alu_core_hf~25_combout & (((\z80_|execute_|ctl_alu_core_hf~27_combout & !\z80_|execute_|ctl_alu_op_low~27_combout )))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~25_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~20_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~27_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~28 .lut_mask = 16'h22F2; -defparam \z80_|execute_|ctl_alu_core_hf~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~30 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~30_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ) # (((\z80_|execute_|ctl_alu_op_low~14_combout ) # (!\z80_|execute_|ctl_alu_op2_sel_bus~9_combout )) # (!\z80_|execute_|ctl_state_alu~13_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), - .datab(\z80_|execute_|ctl_state_alu~13_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~30 .lut_mask = 16'hFBFF; -defparam \z80_|execute_|ctl_alu_op_low~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~34 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~34_combout = (\z80_|execute_|ctl_mRead~6_combout & ((\z80_|execute_|ctl_mWrite~3_combout ) # ((\z80_|execute_|ctl_mWrite~7_combout & !\z80_|execute_|ctl_state_alu~6_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~3_combout ), - .datab(\z80_|execute_|ctl_mWrite~7_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_mRead~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~34 .lut_mask = 16'hAE00; -defparam \z80_|execute_|ctl_alu_core_hf~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~32 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~32_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & (((\z80_|execute_|ctl_alu_op_low~11_combout )))) # (!\z80_|execute_|ctl_alu_op_low~8_combout & (\z80_|execute_|ixy_d~7_combout & -// ((!\z80_|execute_|ctl_mWrite~3_combout )))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~11_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datad(\z80_|execute_|ctl_mWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~32 .lut_mask = 16'hC0CA; -defparam \z80_|execute_|ctl_alu_core_hf~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~43 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~43_combout = (\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|execute_|ctl_mRead~6_combout & (\z80_|execute_|ctl_state_alu~6_combout ))) # (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M2_ff~q ) # -// ((\z80_|execute_|ctl_mRead~6_combout & \z80_|execute_|ctl_state_alu~6_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~43 .lut_mask = 16'hD5C0; -defparam \z80_|execute_|ctl_alu_core_hf~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~33 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~33_combout = (!\z80_|execute_|ctl_alu_core_hf~43_combout & ((\z80_|execute_|ctl_alu_core_hf~32_combout & ((\z80_|pla_decode_|Equal56~0_combout ) # (\z80_|execute_|ctl_alu_op_low~8_combout ))) # -// (!\z80_|execute_|ctl_alu_core_hf~32_combout & (\z80_|pla_decode_|Equal56~0_combout & \z80_|execute_|ctl_alu_op_low~8_combout )))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~32_combout ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~43_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~33 .lut_mask = 16'h00E8; -defparam \z80_|execute_|ctl_alu_core_hf~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~42 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~42_combout = (!\z80_|execute_|ctl_alu_shift_oe~15_combout & (((!\z80_|sequencer_|DFFE_M2_ff~q ) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|execute_|ctl_mRead~6_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~42 .lut_mask = 16'h1555; -defparam \z80_|execute_|ctl_alu_core_hf~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~35 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~35_combout = (\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # ((\z80_|execute_|ctl_alu_core_hf~42_combout & ((\z80_|execute_|ctl_alu_core_hf~34_combout ) # (\z80_|execute_|ctl_alu_core_hf~33_combout )))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~34_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~33_combout ), - .datac(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~42_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~35 .lut_mask = 16'hFEF0; -defparam \z80_|execute_|ctl_alu_core_hf~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~41 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~41_combout = (!\z80_|execute_|ctl_state_alu~4_combout & (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|pla_decode_|Equal10~0_combout & !\z80_|sequencer_|DFFE_T1_ff~q ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~41 .lut_mask = 16'h0040; -defparam \z80_|execute_|ctl_alu_core_hf~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~30 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~30_combout = (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|nM1_int~2_combout ) # ((\z80_|pla_decode_|Equal11~0_combout & !\z80_|execute_|ctl_alu_sel_op2_neg~8_combout )))) # (!\z80_|pla_decode_|Equal10~0_combout & -// (\z80_|pla_decode_|Equal11~0_combout & ((!\z80_|execute_|ctl_alu_sel_op2_neg~8_combout )))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~30 .lut_mask = 16'hA0EC; -defparam \z80_|execute_|ctl_alu_core_hf~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~10 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~10_combout = (!\z80_|ir_|opcode [2] & (\z80_|execute_|ctl_state_alu~4_combout & (\z80_|pla_decode_|Equal11~1_combout & \z80_|execute_|ctl_mWrite~2_combout ))) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|pla_decode_|Equal11~1_combout ), - .datad(\z80_|execute_|ctl_mWrite~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~10 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_mWrite~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~31 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~31_combout = (!\z80_|execute_|ctl_alu_op_low~14_combout & (!\z80_|execute_|ctl_mWrite~10_combout & ((\z80_|execute_|ctl_alu_core_hf~41_combout ) # (\z80_|execute_|ctl_alu_core_hf~30_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~41_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~30_combout ), - .datad(\z80_|execute_|ctl_mWrite~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~31 .lut_mask = 16'h0054; -defparam \z80_|execute_|ctl_alu_core_hf~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~44 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~44_combout = (\z80_|execute_|ctl_alu_op_low~12_combout & (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~44 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_core_hf~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~29 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~29_combout = (!\z80_|execute_|ctl_alu_op_low~19_combout & ((\z80_|execute_|ctl_alu_core_hf~44_combout ) # ((\z80_|execute_|ctl_alu_op_low~11_combout & \z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~44_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~11_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~19_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~29 .lut_mask = 16'h0E0A; -defparam \z80_|execute_|ctl_alu_core_hf~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~36 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~36_combout = (\z80_|execute_|ctl_alu_core_hf~31_combout ) # ((\z80_|execute_|ctl_alu_core_hf~29_combout ) # ((!\z80_|execute_|ctl_alu_op_low~30_combout & \z80_|execute_|ctl_alu_core_hf~35_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~30_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~35_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~31_combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~29_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~36 .lut_mask = 16'hFFF4; -defparam \z80_|execute_|ctl_alu_core_hf~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~39 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~39_combout = (\z80_|execute_|ctl_alu_core_hf~28_combout ) # ((\z80_|execute_|ctl_alu_core_hf~36_combout ) # ((\z80_|execute_|ctl_alu_core_hf~38_combout & !\z80_|execute_|ctl_alu_op_low~24_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~38_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~28_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~36_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~39 .lut_mask = 16'hFCFE; -defparam \z80_|execute_|ctl_alu_core_hf~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~40 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~40_combout = (\z80_|execute_|ctl_alu_core_hf~23_combout ) # ((\z80_|execute_|ctl_alu_core_hf~39_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout & !\z80_|execute_|ctl_alu_op_low~combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~23_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), - .datac(\z80_|execute_|ctl_alu_op_low~combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~39_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~40 .lut_mask = 16'hFFAE; -defparam \z80_|execute_|ctl_alu_core_hf~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_we~2_combout = (\z80_|execute_|ctl_flags_xy_we~11_combout & (\z80_|execute_|ctl_flags_hf_we~5_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_state_alu~14_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~14_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~11_combout ), - .datad(\z80_|execute_|ctl_flags_hf_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_we~2 .lut_mask = 16'h7000; -defparam \z80_|execute_|ctl_flags_hf_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~2 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~2_combout = (\z80_|nM1_int~2_combout & (\z80_|execute_|ctl_mWrite~2_combout & ((\z80_|pla_decode_|Equal55~0_combout ) # (\z80_|pla_decode_|Equal8~0_combout )))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~2_combout ), - .datad(\z80_|pla_decode_|Equal8~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~2 .lut_mask = 16'hA080; -defparam \z80_|execute_|ctl_alu_core_R~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~combout = (\z80_|execute_|ctl_alu_core_R~2_combout ) # (((\z80_|pla_decode_|Equal73~2_combout ) # (!\z80_|execute_|ctl_alu_core_S~8_combout )) # (!\z80_|execute_|ctl_alu_core_R~4_combout )) - - .dataa(\z80_|execute_|ctl_alu_core_R~2_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~4_combout ), - .datac(\z80_|pla_decode_|Equal73~2_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R .lut_mask = 16'hFBFF; -defparam \z80_|execute_|ctl_alu_core_R .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N2 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|alu_|db_low[3]~11_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~43_combout & !\z80_|alu_|db_high[3]~2_combout )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datab(\z80_|alu_|db_low[3]~11_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datad(\z80_|alu_|db_high[3]~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9 .lut_mask = 16'hC0D0; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N8 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~8_combout & \z80_|alu_|db_high[3]~8_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datab(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .datac(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9_combout ), - .datad(\z80_|alu_|db_high[3]~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2 .lut_mask = 16'h5450; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y10_N9 -dffeas \z80_|alu_|op2_high[3] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_high [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_high[3] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_high[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N2 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [3]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [3])))) - - .dataa(\z80_|alu_|op1_high [3]), - .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datac(\z80_|execute_|ctl_alu_op_low~combout ), - .datad(\z80_|alu_|op1_low [3]), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2 .lut_mask = 16'hC808; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N18 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2_combout ) # ((\z80_|alu_|db_low[3]~25_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datab(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2_combout ), - .datac(\z80_|alu_|db_low[3]~25_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3 .lut_mask = 16'h5444; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y10_N19 -dffeas \z80_|alu_|op2_low[3] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_low [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_low[3] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_low[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N26 -cycloneive_lcell_comb \z80_|alu_|alu_op2[3]~2 ( -// Equation(s): -// \z80_|alu_|alu_op2[3]~2_combout = \z80_|execute_|ctl_alu_sel_op2_neg~18_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_high [3])) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_low [3]))))) - - .dataa(\z80_|alu_|op2_high [3]), - .datab(\z80_|alu_|op2_low [3]), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_op2[3]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op2[3]~2 .lut_mask = 16'h5A3C; -defparam \z80_|alu_|alu_op2[3]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N4 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout = (\z80_|execute_|ctl_alu_core_S~9_combout ) # (((\z80_|alu_|alu_op1[3]~3_combout & \z80_|alu_|alu_op2[3]~2_combout )) # (!\z80_|execute_|ctl_alu_core_S~8_combout )) - - .dataa(\z80_|alu_|alu_op1[3]~3_combout ), - .datab(\z80_|execute_|ctl_alu_core_S~9_combout ), - .datac(\z80_|alu_|alu_op2[3]~2_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hECFF; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N16 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout = (!\z80_|alu_|alu_op2[3]~2_combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_low [3]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_high -// [3])))) - - .dataa(\z80_|alu_|alu_op2[3]~2_combout ), - .datab(\z80_|alu_|op1_high [3]), - .datac(\z80_|alu_|op1_low [3]), - .datad(\z80_|execute_|ctl_alu_op_low~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h0511; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N30 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ) # -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_core_R~combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0 .lut_mask = 16'hAFAE; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N2 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_hf~0 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_hf~0_combout = (\z80_|execute_|ctl_flags_bus~combout & ((\z80_|alu_control_|db[4]~32_combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & \z80_|execute_|ctl_flags_alu~15_combout )))) # -// (!\z80_|execute_|ctl_flags_bus~combout & (((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & \z80_|execute_|ctl_flags_alu~15_combout )))) - - .dataa(\z80_|execute_|ctl_flags_bus~combout ), - .datab(\z80_|alu_control_|db[4]~32_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), - .datad(\z80_|execute_|ctl_flags_alu~15_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_hf~0 .lut_mask = 16'h8F88; -defparam \z80_|alu_flags_|DFFE_inst_latch_hf~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_we~3_combout = (\z80_|pla_decode_|Equal11~0_combout & ((\z80_|nM1_int~2_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) # (!\z80_|pla_decode_|Equal11~0_combout & (((\z80_|pla_decode_|Equal10~0_combout & -// \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_we~3 .lut_mask = 16'hFC88; -defparam \z80_|execute_|ctl_flags_hf_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_we~4_combout = ((\z80_|execute_|ctl_flags_sz_we~6_combout ) # ((\z80_|execute_|ctl_flags_hf_we~3_combout ) # (!\z80_|execute_|ctl_flags_xy_we~6_combout ))) # (!\z80_|execute_|ctl_flags_alu~14_combout ) - - .dataa(\z80_|execute_|ctl_flags_alu~14_combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~6_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~6_combout ), - .datad(\z80_|execute_|ctl_flags_hf_we~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_we~4 .lut_mask = 16'hFFDF; -defparam \z80_|execute_|ctl_flags_hf_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N6 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_hf~1 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_hf~1_combout = (\z80_|execute_|ctl_flags_hf_we~2_combout & ((\z80_|execute_|ctl_flags_hf_we~4_combout & (\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout )) # (!\z80_|execute_|ctl_flags_hf_we~4_combout & -// ((\z80_|alu_flags_|DFFE_inst_latch_hf~q ))))) # (!\z80_|execute_|ctl_flags_hf_we~2_combout & (\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout )) - - .dataa(\z80_|execute_|ctl_flags_hf_we~2_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), - .datad(\z80_|execute_|ctl_flags_hf_we~4_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_hf~1 .lut_mask = 16'hCCE4; -defparam \z80_|alu_flags_|DFFE_inst_latch_hf~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y11_N7 -dffeas \z80_|alu_flags_|DFFE_inst_latch_hf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_hf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_hf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_cpl~11_combout = (\z80_|execute_|ctl_mRead~6_combout ) # ((\z80_|pla_decode_|Equal52~1_combout ) # (\z80_|execute_|ctl_state_alu~14_combout )) - - .dataa(\z80_|execute_|ctl_mRead~6_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal52~1_combout ), - .datad(\z80_|execute_|ctl_state_alu~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_cpl~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_cpl~11 .lut_mask = 16'hFFFA; -defparam \z80_|execute_|ctl_flags_hf_cpl~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~12 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_cpl~12_combout = ((\z80_|execute_|ctl_flags_hf_cpl~11_combout ) # ((\z80_|pla_decode_|Equal10~0_combout ) # (\z80_|execute_|ctl_alu_op_low~12_combout ))) # (!\z80_|execute_|ctl_flags_hf_cpl~10_combout ) - - .dataa(\z80_|execute_|ctl_flags_hf_cpl~10_combout ), - .datab(\z80_|execute_|ctl_flags_hf_cpl~11_combout ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_cpl~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_cpl~12 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_flags_hf_cpl~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~13 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_cpl~13_combout = (\z80_|execute_|ctl_flags_hf_cpl~12_combout & (\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|alu_flags_|DFFE_inst_latch_nf~q ))) - - .dataa(\z80_|execute_|ctl_flags_hf_cpl~12_combout ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_cpl~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_cpl~13 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_flags_hf_cpl~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N8 -cycloneive_lcell_comb \z80_|alu_flags_|flags_hf ( -// Equation(s): -// \z80_|alu_flags_|flags_hf~combout = \z80_|alu_flags_|DFFE_inst_latch_hf~q $ (((\z80_|execute_|ctl_flags_hf_cpl~13_combout ) # ((!\z80_|alu_flags_|flags_cf~combout & \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout )))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), - .datab(\z80_|alu_flags_|flags_cf~combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .datad(\z80_|execute_|ctl_flags_hf_cpl~13_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|flags_hf~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_hf .lut_mask = 16'h559A; -defparam \z80_|alu_flags_|flags_hf .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N30 -cycloneive_lcell_comb \z80_|alu_control_|alu_core_cf_in~0 ( -// Equation(s): -// \z80_|alu_control_|alu_core_cf_in~0_combout = (\z80_|execute_|ctl_alu_core_hf~40_combout & ((\z80_|alu_flags_|flags_hf~combout ))) # (!\z80_|execute_|ctl_alu_core_hf~40_combout & (\z80_|alu_flags_|flags_cf~combout )) - - .dataa(\z80_|execute_|ctl_alu_core_hf~40_combout ), - .datab(\z80_|alu_flags_|flags_cf~combout ), - .datac(gnd), - .datad(\z80_|alu_flags_|flags_hf~combout ), - .cin(gnd), - .combout(\z80_|alu_control_|alu_core_cf_in~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|alu_core_cf_in~0 .lut_mask = 16'hEE44; -defparam \z80_|alu_control_|alu_core_cf_in~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N20 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout = (\z80_|alu_|alu_op2[0]~3_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ) # ((\z80_|alu_control_|alu_core_cf_in~0_combout & \z80_|alu_|alu_op1[0]~1_combout )))) -// # (!\z80_|alu_|alu_op2[0]~3_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_control_|alu_core_cf_in~0_combout ) # (\z80_|alu_|alu_op1[0]~1_combout )))) - - .dataa(\z80_|alu_|alu_op2[0]~3_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ), - .datac(\z80_|alu_control_|alu_core_cf_in~0_combout ), - .datad(\z80_|alu_|alu_op1[0]~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 .lut_mask = 16'hECC8; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N12 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~23 ( -// Equation(s): -// \z80_|alu_|db_high[0]~23_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[5]~25_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[3]~11_combout )) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|alu_|db[3]~11_combout ), - .datac(\z80_|alu_|db[5]~25_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~23 .lut_mask = 16'hE4E4; -defparam \z80_|alu_|db_high[0]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N8 -cycloneive_lcell_comb \z80_|address_latch_|abusz[12] ( -// Equation(s): -// \z80_|address_latch_|abusz [12] = (\z80_|reg_file_|db_hi_as[4]~18_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(gnd), - .datab(\z80_|reg_file_|db_hi_as[4]~18_combout ), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [12]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[12] .lut_mask = 16'h0C0C; -defparam \z80_|address_latch_|abusz[12] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N14 -cycloneive_lcell_comb \z80_|address_latch_|Q[12]~feeder ( -// Equation(s): -// \z80_|address_latch_|Q[12]~feeder_combout = \z80_|address_latch_|abusz [12] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [12]), - .cin(gnd), - .combout(\z80_|address_latch_|Q[12]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|Q[12]~feeder .lut_mask = 16'hFF00; -defparam \z80_|address_latch_|Q[12]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N15 -dffeas \z80_|address_latch_|Q[12] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|Q[12]~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [12]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[12] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[12] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N30 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout = \z80_|address_latch_|Q [12] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout & (\z80_|execute_|ctl_inc_dec~11_combout $ -// (\z80_|address_latch_|Q [11]))))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), - .datab(\z80_|execute_|ctl_inc_dec~11_combout ), - .datac(\z80_|address_latch_|Q [12]), - .datad(\z80_|address_latch_|Q [11]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out .lut_mask = 16'hD278; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N5 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[4]~18_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y15_N7 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[4]~18_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N6 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~16 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[4]~16_combout = (\z80_|reg_control_|reg_sw_4d_hi~0_combout & (\z80_|reg_file_|gdfx_temp1[4]~66_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) - - .dataa(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [4]), - .datad(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[4]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[4]~16 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|db_hi_as[4]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N18 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~17 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[4]~17_combout = (\z80_|reg_file_|db_hi_as[4]~16_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datab(gnd), - .datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [4]), - .datad(\z80_|reg_file_|db_hi_as[4]~16_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[4]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[4]~17 .lut_mask = 16'hF500; -defparam \z80_|reg_file_|db_hi_as[4]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N4 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~18 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[4]~18_combout = ((\z80_|reg_file_|db_hi_as[4]~17_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datad(\z80_|reg_file_|db_hi_as[4]~17_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[4]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[4]~18 .lut_mask = 16'hBF0F; -defparam \z80_|reg_file_|db_hi_as[4]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y11_N11 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~62 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~62_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (\z80_|reg_file_|b2v_latch_af2_hi|latch [4] & ((\z80_|alu_|db[4]~17_combout ) # (!\z80_|execute_|ctl_reg_in_hi~12_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (((\z80_|alu_|db[4]~17_combout )) # (!\z80_|execute_|ctl_reg_in_hi~12_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [4]), - .datad(\z80_|alu_|db[4]~17_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~62_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~62 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[4]~62 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y15_N13 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y11_N29 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~63 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~63_combout = (\z80_|reg_file_|b2v_latch_sp_hi|latch [4] & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ))) # (!\z80_|reg_file_|b2v_latch_sp_hi|latch [4] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_sp_hi|latch [4]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~63_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~63 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[4]~63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y12_N23 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y12_N21 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~61 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~61_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (\z80_|reg_file_|b2v_latch_ix_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_iy_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (((\z80_|reg_file_|b2v_latch_iy_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_iy_hi|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~61_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~61 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[4]~61 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N24 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder_combout = \z80_|reg_file_|gdfx_temp1[4]~66_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y13_N25 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y13_N23 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~60 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~60_combout = (\z80_|reg_file_|b2v_latch_bc_hi|latch [4] & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_hi|latch [4] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc_hi|latch [4]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~60_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~60 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[4]~60 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~64 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~64_combout = (\z80_|reg_file_|gdfx_temp1[4]~62_combout & (\z80_|reg_file_|gdfx_temp1[4]~63_combout & (\z80_|reg_file_|gdfx_temp1[4]~61_combout & \z80_|reg_file_|gdfx_temp1[4]~60_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[4]~62_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[4]~63_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[4]~61_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[4]~60_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~64_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~64 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[4]~64 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N31 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y14_N29 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~59 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~59_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~59_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~59 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[4]~59 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y13_N23 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y13_N13 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~58 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~58_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~58_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~58 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[4]~58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y14_N19 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N18 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[4]~19 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[4]~19_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [4]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [4]), - .datad(\z80_|reg_control_|reg_sel_af~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[4]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[4]~19 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[4]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~65 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~65_combout = (\z80_|reg_file_|gdfx_temp1[4]~64_combout & (\z80_|reg_file_|gdfx_temp1[4]~59_combout & (\z80_|reg_file_|gdfx_temp1[4]~58_combout & \z80_|reg_file_|b2v_latch_af_hi|db[4]~19_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[4]~64_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[4]~59_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[4]~58_combout ), - .datad(\z80_|reg_file_|b2v_latch_af_hi|db[4]~19_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~65_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~65 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[4]~65 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~66 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~66_combout = ((\z80_|reg_file_|gdfx_temp1[4]~65_combout & ((\z80_|reg_file_|db_hi_as[4]~18_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datab(\z80_|reg_file_|db_hi_as[4]~18_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[4]~65_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~66 .lut_mask = 16'hD5F5; -defparam \z80_|reg_file_|gdfx_temp1[4]~66 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N26 -cycloneive_lcell_comb \z80_|alu_|db[4]~16 ( -// Equation(s): -// \z80_|alu_|db[4]~16_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[4]~66_combout & ((\z80_|alu_control_|db[4]~32_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & -// (((\z80_|alu_control_|db[4]~32_combout )) # (!\z80_|execute_|ctl_sw_2d~13_combout ))) - - .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datab(\z80_|execute_|ctl_sw_2d~13_combout ), - .datac(\z80_|alu_control_|db[4]~32_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[4]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[4]~16 .lut_mask = 16'hF351; -defparam \z80_|alu_|db[4]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N2 -cycloneive_lcell_comb \z80_|alu_|db[7]~26 ( -// Equation(s): -// \z80_|alu_|db[7]~26_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout ) # ((\z80_|execute_|ctl_alu_oe~13_combout ) # ((\z80_|execute_|ctl_sw_2d~13_combout ) # (!\z80_|execute_|ctl_alu_oe~9_combout ))) - - .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datab(\z80_|execute_|ctl_alu_oe~13_combout ), - .datac(\z80_|execute_|ctl_alu_oe~9_combout ), - .datad(\z80_|execute_|ctl_sw_2d~13_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[7]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[7]~26 .lut_mask = 16'hFFEF; -defparam \z80_|alu_|db[7]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N0 -cycloneive_lcell_comb \z80_|alu_|db[4]~17 ( -// Equation(s): -// \z80_|alu_|db[4]~17_combout = ((\z80_|alu_|db[4]~16_combout & ((\z80_|alu_|db_high[0]~26_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~26_combout ) - - .dataa(\z80_|alu_|db[4]~16_combout ), - .datab(\z80_|alu_|db[7]~26_combout ), - .datac(\z80_|alu_|db_high[0]~26_combout ), - .datad(\z80_|execute_|ctl_alu_oe~14_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[4]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[4]~17 .lut_mask = 16'hB3BB; -defparam \z80_|alu_|db[4]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_sel_shift~3_combout = (\z80_|execute_|ctl_state_alu~6_combout ) # ((\z80_|pla_decode_|Equal33~0_combout & (\z80_|execute_|ctl_mWrite~3_combout & \z80_|decode_state_|DFFE_instCB~q ))) - - .dataa(\z80_|execute_|ctl_state_alu~6_combout ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~3_combout ), - .datad(\z80_|decode_state_|DFFE_instCB~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~3 .lut_mask = 16'hEAAA; -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_sel_shift~5_combout = (\z80_|sequencer_|DFFE_T4_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|execute_|ctl_ir_we~8_combout ) # (\z80_|pla_decode_|Equal20~0_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|pla_decode_|Equal20~0_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~5 .lut_mask = 16'h00C8; -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_sel_shift~4_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ) # ((\z80_|execute_|ctl_ir_we~6_combout & (\z80_|execute_|ctl_flags_cf2_sel_shift~3_combout & \z80_|execute_|ctl_ir_we~5_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~6_combout ), - .datab(\z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ), - .datac(\z80_|execute_|ctl_ir_we~5_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~4 .lut_mask = 16'hFF80; -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N10 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~24 ( -// Equation(s): -// \z80_|alu_|db_high[0]~24_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_high[0]~23_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[4]~17_combout ))) - - .dataa(\z80_|alu_|db_high[0]~23_combout ), - .datab(gnd), - .datac(\z80_|alu_|db[4]~17_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~24 .lut_mask = 16'hAAF0; -defparam \z80_|alu_|db_high[0]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N4 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~21 ( -// Equation(s): -// \z80_|alu_|db_high[0]~21_combout = ((!\z80_|bus_control_|db[4]~19_combout & (\z80_|bus_control_|db[5]~15_combout & !\z80_|bus_control_|db[3]~21_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datab(\z80_|bus_control_|db[4]~19_combout ), - .datac(\z80_|bus_control_|db[5]~15_combout ), - .datad(\z80_|bus_control_|db[3]~21_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~21 .lut_mask = 16'h5575; -defparam \z80_|alu_|db_high[0]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N20 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[0] ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_high|Q [0] = (\z80_|alu_|db_high[0]~26_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) - - .dataa(gnd), - .datab(\z80_|alu_|db_high[0]~26_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [0]), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[0] .lut_mask = 16'h00C0; -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[0] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y10_N21 -dffeas \z80_|alu_|op1_high[0] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [0]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_high [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_high[0] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_high[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N8 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~22 ( -// Equation(s): -// \z80_|alu_|db_high[0]~22_combout = (\z80_|alu_|op1_high [0] & (((\z80_|alu_|op2_high [0]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|alu_|op1_high [0] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_high [0]) # -// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) - - .dataa(\z80_|alu_|op1_high [0]), - .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datac(\z80_|alu_|op2_high [0]), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~22 .lut_mask = 16'hB0BB; -defparam \z80_|alu_|db_high[0]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N4 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~25 ( -// Equation(s): -// \z80_|alu_|db_high[0]~25_combout = (\z80_|alu_|db_high[0]~21_combout & (\z80_|alu_|db_high[0]~22_combout & ((\z80_|alu_|db_high[0]~24_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) - - .dataa(\z80_|alu_|db_high[0]~24_combout ), - .datab(\z80_|alu_|db_high[0]~21_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datad(\z80_|alu_|db_high[0]~22_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~25 .lut_mask = 16'h8C00; -defparam \z80_|alu_|db_high[0]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N22 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~26 ( -// Equation(s): -// \z80_|alu_|db_high[0]~26_combout = ((\z80_|alu_|db_high[0]~25_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) # (!\z80_|alu_|db_high[3]~3_combout ) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), - .datab(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datac(\z80_|alu_|db_high[0]~25_combout ), - .datad(\z80_|alu_|db_high[3]~3_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~26 .lut_mask = 16'hE0FF; -defparam \z80_|alu_|db_high[0]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N4 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout = (\z80_|alu_|db_low[0]~23_combout & ((\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_low~combout & \z80_|alu_|db_high[0]~26_combout )))) # -// (!\z80_|alu_|db_low[0]~23_combout & (((\z80_|execute_|ctl_alu_op1_sel_low~combout & \z80_|alu_|db_high[0]~26_combout )))) - - .dataa(\z80_|alu_|db_low[0]~23_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .datad(\z80_|alu_|db_high[0]~26_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 .lut_mask = 16'hF888; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N30 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8_combout = (\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8 .lut_mask = 16'h00F0; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N12 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|ena ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|ena~combout = (\z80_|execute_|ctl_alu_op1_sel_low~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~combout ) # (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout )) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|ena .lut_mask = 16'hFEFE; -defparam \z80_|alu_|b2v_op1_latch_mux_low|ena .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y10_N31 -dffeas \z80_|alu_|op1_low[0] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_low [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_low[0] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_low[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N12 -cycloneive_lcell_comb \z80_|alu_|alu_op1[0]~1 ( -// Equation(s): -// \z80_|alu_|alu_op1[0]~1_combout = (\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [0])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [0]))) - - .dataa(\z80_|execute_|ctl_alu_op_low~combout ), - .datab(\z80_|alu_|op1_low [0]), - .datac(\z80_|alu_|op1_high [0]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|alu_op1[0]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op1[0]~1 .lut_mask = 16'hD8D8; -defparam \z80_|alu_|alu_op1[0]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N30 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout = (\z80_|alu_|alu_op1[0]~1_combout & ((\z80_|execute_|ctl_alu_op2_sel_lq~combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~8_combout & \z80_|alu_|db_low[0]~23_combout )))) # -// (!\z80_|alu_|alu_op1[0]~1_combout & (\z80_|execute_|ctl_alu_op2_sel_bus~8_combout & ((\z80_|alu_|db_low[0]~23_combout )))) - - .dataa(\z80_|alu_|alu_op1[0]~1_combout ), - .datab(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datad(\z80_|alu_|db_low[0]~23_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 .lut_mask = 16'hECA0; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N14 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datab(gnd), - .datac(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 .lut_mask = 16'h5050; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y10_N15 -dffeas \z80_|alu_|op2_low[0] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_low [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_low[0] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_low[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N12 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout = (\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [0]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [0])) - - .dataa(\z80_|alu_|op2_low [0]), - .datab(gnd), - .datac(\z80_|alu_|op2_high [0]), - .datad(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'hF0AA; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N14 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout = (\z80_|alu_control_|alu_core_cf_in~0_combout & ((\z80_|alu_|alu_op1[0]~1_combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout $ -// (\z80_|execute_|ctl_alu_sel_op2_neg~18_combout )))) # (!\z80_|alu_control_|alu_core_cf_in~0_combout & (\z80_|alu_|alu_op1[0]~1_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout $ -// (\z80_|execute_|ctl_alu_sel_op2_neg~18_combout )))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), - .datac(\z80_|alu_control_|alu_core_cf_in~0_combout ), - .datad(\z80_|alu_|alu_op1[0]~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hF660; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N28 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|execute_|ctl_alu_core_S~9_combout & (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout & -// \z80_|execute_|ctl_alu_core_S~8_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_S~9_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), - .datac(\z80_|execute_|ctl_alu_core_R~combout ), - .datad(\z80_|execute_|ctl_alu_core_S~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 .lut_mask = 16'hF1F0; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N26 -cycloneive_lcell_comb \z80_|alu_|alu_op1[1]~0 ( -// Equation(s): -// \z80_|alu_|alu_op1[1]~0_combout = (\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [1])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [1]))) - - .dataa(\z80_|execute_|ctl_alu_op_low~combout ), - .datab(\z80_|alu_|op1_low [1]), - .datac(gnd), - .datad(\z80_|alu_|op1_high [1]), - .cin(gnd), - .combout(\z80_|alu_|alu_op1[1]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op1[1]~0 .lut_mask = 16'hDD88; -defparam \z80_|alu_|alu_op1[1]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N0 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout = (\z80_|execute_|ctl_alu_core_S~9_combout ) # (((\z80_|alu_|alu_op1[1]~0_combout & \z80_|alu_|alu_op2[1]~1_combout )) # (!\z80_|execute_|ctl_alu_core_S~8_combout )) - - .dataa(\z80_|execute_|ctl_alu_core_S~9_combout ), - .datab(\z80_|execute_|ctl_alu_core_S~8_combout ), - .datac(\z80_|alu_|alu_op1[1]~0_combout ), - .datad(\z80_|alu_|alu_op2[1]~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'hFBBB; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N24 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout = (!\z80_|execute_|ctl_alu_core_R~combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ) # -// ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout & !\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout )))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), - .datac(\z80_|execute_|ctl_alu_core_R~combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 .lut_mask = 16'h0F01; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N26 -cycloneive_lcell_comb \z80_|alu_|alu_op1[2]~2 ( -// Equation(s): -// \z80_|alu_|alu_op1[2]~2_combout = (\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [2]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [2])) - - .dataa(\z80_|alu_|op1_high [2]), - .datab(\z80_|execute_|ctl_alu_op_low~combout ), - .datac(gnd), - .datad(\z80_|alu_|op1_low [2]), - .cin(gnd), - .combout(\z80_|alu_|alu_op1[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op1[2]~2 .lut_mask = 16'hEE22; -defparam \z80_|alu_|alu_op1[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N8 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout = (\z80_|execute_|ctl_alu_core_S~9_combout ) # (((\z80_|alu_|alu_op2[2]~0_combout & \z80_|alu_|alu_op1[2]~2_combout )) # (!\z80_|execute_|ctl_alu_core_S~8_combout )) - - .dataa(\z80_|alu_|alu_op2[2]~0_combout ), - .datab(\z80_|execute_|ctl_alu_core_S~9_combout ), - .datac(\z80_|alu_|alu_op1[2]~2_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hECFF; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N2 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ) # -// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), - .datad(\z80_|execute_|ctl_alu_core_R~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 .lut_mask = 16'hFF0B; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~5_combout = (\z80_|execute_|ctl_alu_core_R~4_combout & \z80_|execute_|ctl_alu_core_S~8_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_core_R~4_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~5 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_alu_core_R~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N6 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ) # -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout )))) # (!\z80_|execute_|ctl_alu_core_R~5_combout ) - - .dataa(\z80_|execute_|ctl_alu_core_R~5_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1 .lut_mask = 16'h5F5D; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N14 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout = (\z80_|alu_|alu_op1[3]~3_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout & -// \z80_|alu_|alu_op2[3]~2_combout )))) # (!\z80_|alu_|alu_op1[3]~3_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_|alu_op2[3]~2_combout ) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout )))) - - .dataa(\z80_|alu_|alu_op1[3]~3_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), - .datac(\z80_|alu_|alu_op2[3]~2_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 .lut_mask = 16'hFB20; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N12 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder_combout = \z80_|reg_file_|gdfx_temp1[7]~75_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y13_N13 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y13_N19 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~69 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~69_combout = (\z80_|reg_file_|b2v_latch_bc_hi|latch [7] & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_hi|latch [7] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc_hi|latch [7]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~69_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~69 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[7]~69 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y12_N3 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y12_N25 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~70 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~70_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (\z80_|reg_file_|b2v_latch_ix_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_iy_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (((\z80_|reg_file_|b2v_latch_iy_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_iy_hi|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~70_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~70 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[7]~70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y15_N11 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y11_N27 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~72 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~72_combout = (\z80_|reg_file_|b2v_latch_sp_hi|latch [7] & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ))) # (!\z80_|reg_file_|b2v_latch_sp_hi|latch [7] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_sp_hi|latch [7]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~72_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~72 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[7]~72 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y11_N17 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~71 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~71_combout = (\z80_|alu_|db[7]~21_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[7]~21_combout & (!\z80_|execute_|ctl_reg_in_hi~12_combout & -// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|alu_|db[7]~21_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~71_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~71 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[7]~71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~73 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~73_combout = (\z80_|reg_file_|gdfx_temp1[7]~69_combout & (\z80_|reg_file_|gdfx_temp1[7]~70_combout & (\z80_|reg_file_|gdfx_temp1[7]~72_combout & \z80_|reg_file_|gdfx_temp1[7]~71_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[7]~69_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[7]~70_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[7]~72_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[7]~71_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~73_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~73 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[7]~73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y13_N27 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y13_N17 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~67 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~67_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~67_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~67 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[7]~67 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y14_N15 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N14 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[7]~20 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[7]~20_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [7]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [7]), - .datad(\z80_|reg_control_|reg_sel_af~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[7]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[7]~20 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[7]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N11 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y14_N21 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~68 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~68_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~68_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~68 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[7]~68 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y11_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~74 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~74_combout = (\z80_|reg_file_|gdfx_temp1[7]~73_combout & (\z80_|reg_file_|gdfx_temp1[7]~67_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[7]~20_combout & \z80_|reg_file_|gdfx_temp1[7]~68_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[7]~73_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[7]~67_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|db[7]~20_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[7]~68_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~74_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~74 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[7]~74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y15_N29 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[7]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N28 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~19 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[7]~19_combout = (\z80_|reg_file_|gdfx_temp1[7]~75_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) # (!\z80_|reg_file_|gdfx_temp1[7]~75_combout & -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [7]), - .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[7]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[7]~19 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_hi_as[7]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N27 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[7]~21_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N28 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~20 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[7]~20_combout = (\z80_|reg_file_|db_hi_as[7]~19_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|db_hi_as[7]~19_combout ), - .datab(gnd), - .datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[7]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[7]~20 .lut_mask = 16'hA0AA; -defparam \z80_|reg_file_|db_hi_as[7]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N2 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout & ((\z80_|execute_|ctl_inc_dec~11_combout & (!\z80_|address_latch_|Q [12] & -// !\z80_|address_latch_|Q [11])) # (!\z80_|execute_|ctl_inc_dec~11_combout & (\z80_|address_latch_|Q [12] & \z80_|address_latch_|Q [11])))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), - .datab(\z80_|execute_|ctl_inc_dec~11_combout ), - .datac(\z80_|address_latch_|Q [12]), - .datad(\z80_|address_latch_|Q [11]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'h2008; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N8 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout = \z80_|address_latch_|Q [13] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|address_latch_|Q [13]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out .lut_mask = 16'h0FF0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y12_N13 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y15_N5 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~54 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~54_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [5]), - .datad(\z80_|reg_file_|b2v_latch_sp_hi|latch [5]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~54_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~54 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[5]~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y11_N1 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~53 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~53_combout = (\z80_|alu_|db[5]~25_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[5]~25_combout & (!\z80_|execute_|ctl_reg_in_hi~12_combout & -// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|alu_|db[5]~25_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~53_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~53 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[5]~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N8 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder_combout = \z80_|reg_file_|gdfx_temp1[5]~57_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y13_N9 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y13_N11 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~51 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~51_combout = (\z80_|reg_file_|b2v_latch_bc_hi|latch [5] & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_hi|latch [5] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc_hi|latch [5]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~51_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~51 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[5]~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y12_N11 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y12_N3 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~52 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~52_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [5] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [5] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [5]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~52_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~52 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[5]~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~55 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~55_combout = (\z80_|reg_file_|gdfx_temp1[5]~54_combout & (\z80_|reg_file_|gdfx_temp1[5]~53_combout & (\z80_|reg_file_|gdfx_temp1[5]~51_combout & \z80_|reg_file_|gdfx_temp1[5]~52_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[5]~54_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[5]~53_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[5]~51_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[5]~52_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~55_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~55 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[5]~55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y13_N9 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y13_N3 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~49 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~49_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datab(\z80_|reg_file_|b2v_latch_de_hi|latch [5]), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~49 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[5]~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N5 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y14_N27 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~50 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~50_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [5]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [5]), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~50 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp1[5]~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y14_N21 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N20 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[5]~14 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[5]~14_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [5]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [5]), - .datad(\z80_|reg_control_|reg_sel_af~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[5]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[5]~14 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[5]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~56 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~56_combout = (\z80_|reg_file_|gdfx_temp1[5]~55_combout & (\z80_|reg_file_|gdfx_temp1[5]~49_combout & (\z80_|reg_file_|gdfx_temp1[5]~50_combout & \z80_|reg_file_|b2v_latch_af_hi|db[5]~14_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[5]~55_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[5]~49_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[5]~50_combout ), - .datad(\z80_|reg_file_|b2v_latch_af_hi|db[5]~14_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~56_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~56 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[5]~56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~57 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~57_combout = ((\z80_|reg_file_|gdfx_temp1[5]~56_combout & ((\z80_|reg_file_|db_hi_as[5]~15_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[5]~56_combout ), - .datac(\z80_|reg_file_|db_hi_as[5]~15_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~57 .lut_mask = 16'hD5DD; -defparam \z80_|reg_file_|gdfx_temp1[5]~57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y15_N1 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[5]~15_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N0 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~13 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[5]~13_combout = (\z80_|reg_control_|reg_sw_4d_hi~0_combout & (\z80_|reg_file_|gdfx_temp1[5]~57_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) - - .dataa(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[5]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[5]~13 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|db_hi_as[5]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N23 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[5]~15_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N16 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~14 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[5]~14_combout = (\z80_|reg_file_|db_hi_as[5]~13_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datab(\z80_|reg_file_|db_hi_as[5]~13_combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [5]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[5]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[5]~14 .lut_mask = 16'hC4C4; -defparam \z80_|reg_file_|db_hi_as[5]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N22 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~15 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[5]~15_combout = ((\z80_|reg_file_|db_hi_as[5]~14_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datad(\z80_|reg_file_|db_hi_as[5]~14_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[5]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[5]~15 .lut_mask = 16'hBF0F; -defparam \z80_|reg_file_|db_hi_as[5]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N2 -cycloneive_lcell_comb \z80_|address_latch_|abusz[13] ( -// Equation(s): -// \z80_|address_latch_|abusz [13] = (\z80_|reg_file_|db_hi_as[5]~15_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(gnd), - .datab(\z80_|reg_file_|db_hi_as[5]~15_combout ), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [13]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[13] .lut_mask = 16'h0C0C; -defparam \z80_|address_latch_|abusz[13] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N22 -cycloneive_lcell_comb \z80_|address_latch_|Q[13]~feeder ( -// Equation(s): -// \z80_|address_latch_|Q[13]~feeder_combout = \z80_|address_latch_|abusz [13] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [13]), - .cin(gnd), - .combout(\z80_|address_latch_|Q[13]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|Q[13]~feeder .lut_mask = 16'hFF00; -defparam \z80_|address_latch_|Q[13]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N23 -dffeas \z80_|address_latch_|Q[13] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|Q[13]~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [13]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[13] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[13] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N6 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout = \z80_|address_latch_|Q [13] $ (\z80_|execute_|ctl_inc_dec~11_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|address_latch_|Q [13]), - .datad(\z80_|execute_|ctl_inc_dec~11_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 .lut_mask = 16'h0FF0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N26 -cycloneive_lcell_comb \z80_|address_latch_|abusz[15] ( -// Equation(s): -// \z80_|address_latch_|abusz [15] = (\z80_|reg_file_|db_hi_as[7]~21_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|reg_file_|db_hi_as[7]~21_combout ), - .datad(\z80_|resets_|clrpc~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [15]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[15] .lut_mask = 16'h00F0; -defparam \z80_|address_latch_|abusz[15] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N27 -dffeas \z80_|address_latch_|Q[15] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [15]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [15]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[15] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[15] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N20 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[14] ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|address [14] = \z80_|address_latch_|Q [14] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout & (\z80_|address_latch_|Q [13] $ (\z80_|execute_|ctl_inc_dec~11_combout ))))) - - .dataa(\z80_|address_latch_|Q [13]), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), - .datac(\z80_|address_latch_|Q [14]), - .datad(\z80_|execute_|ctl_inc_dec~11_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[14] .lut_mask = 16'hB478; -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[14] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N7 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[6]~24_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y13_N11 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y13_N21 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~76 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~76_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~76_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~76 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[6]~76 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y11_N23 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~80 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~80_combout = (\z80_|alu_|db[6]~23_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[6]~23_combout & (!\z80_|execute_|ctl_reg_in_hi~12_combout & -// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|alu_|db[6]~23_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~80_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~80 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[6]~80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y12_N17 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y12_N9 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~79 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~79_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [6] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [6] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [6]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~79_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~79 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[6]~79 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y13_N27 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y13_N29 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~78 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~78_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (\z80_|reg_file_|b2v_latch_bc2_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_bc_hi|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~78_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~78 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[6]~78 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y15_N25 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y12_N7 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~81 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~81_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [6]), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~81_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~81 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[6]~81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~82 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~82_combout = (\z80_|reg_file_|gdfx_temp1[6]~80_combout & (\z80_|reg_file_|gdfx_temp1[6]~79_combout & (\z80_|reg_file_|gdfx_temp1[6]~78_combout & \z80_|reg_file_|gdfx_temp1[6]~81_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[6]~80_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[6]~79_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[6]~78_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[6]~81_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~82_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~82 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[6]~82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N23 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y14_N25 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~77 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~77_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~77_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~77 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[6]~77 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y14_N13 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N12 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[6]~21 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[6]~21_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [6]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [6]), - .datad(\z80_|reg_control_|reg_sel_af~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[6]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[6]~21 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[6]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~83 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~83_combout = (\z80_|reg_file_|gdfx_temp1[6]~76_combout & (\z80_|reg_file_|gdfx_temp1[6]~82_combout & (\z80_|reg_file_|gdfx_temp1[6]~77_combout & \z80_|reg_file_|b2v_latch_af_hi|db[6]~21_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[6]~76_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[6]~82_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[6]~77_combout ), - .datad(\z80_|reg_file_|b2v_latch_af_hi|db[6]~21_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~83_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~83 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[6]~83 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~84 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~84_combout = ((\z80_|reg_file_|gdfx_temp1[6]~83_combout & ((\z80_|reg_file_|db_hi_as[6]~24_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[6]~83_combout ), - .datac(\z80_|reg_file_|db_hi_as[6]~24_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~84 .lut_mask = 16'hD5DD; -defparam \z80_|reg_file_|gdfx_temp1[6]~84 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y15_N19 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[6]~24_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N18 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~22 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[6]~22_combout = (\z80_|reg_control_|reg_sw_4d_hi~0_combout & (\z80_|reg_file_|gdfx_temp1[6]~84_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) - - .dataa(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[6]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[6]~22 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|db_hi_as[6]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N20 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~23 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[6]~23_combout = (\z80_|reg_file_|db_hi_as[6]~22_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|b2v_latch_pc_hi|latch [6]), - .datab(\z80_|reg_file_|db_hi_as[6]~22_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[6]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[6]~23 .lut_mask = 16'h88CC; -defparam \z80_|reg_file_|db_hi_as[6]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N6 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~24 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[6]~24_combout = ((\z80_|reg_file_|db_hi_as[6]~23_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [14]) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), - .datab(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datad(\z80_|reg_file_|db_hi_as[6]~23_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[6]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[6]~24 .lut_mask = 16'hBF33; -defparam \z80_|reg_file_|db_hi_as[6]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N14 -cycloneive_lcell_comb \z80_|address_latch_|abusz[14] ( -// Equation(s): -// \z80_|address_latch_|abusz [14] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[6]~24_combout ) - - .dataa(\z80_|resets_|clrpc~0_combout ), - .datab(gnd), - .datac(\z80_|reg_file_|db_hi_as[6]~24_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [14]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[14] .lut_mask = 16'h5050; -defparam \z80_|address_latch_|abusz[14] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N4 -cycloneive_lcell_comb \z80_|address_latch_|Q[14]~feeder ( -// Equation(s): -// \z80_|address_latch_|Q[14]~feeder_combout = \z80_|address_latch_|abusz [14] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [14]), - .cin(gnd), - .combout(\z80_|address_latch_|Q[14]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|Q[14]~feeder .lut_mask = 16'hFF00; -defparam \z80_|address_latch_|Q[14]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N5 -dffeas \z80_|address_latch_|Q[14] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|Q[14]~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [14]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[14] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[14] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y16_N4 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout = \z80_|address_latch_|Q [14] $ (((\z80_|execute_|ctl_inc_dec~9_combout ) # ((\z80_|execute_|ctl_inc_dec~7_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout )))) - - .dataa(\z80_|execute_|ctl_inc_dec~9_combout ), - .datab(\z80_|address_latch_|Q [14]), - .datac(\z80_|execute_|ctl_inc_dec~6_combout ), - .datad(\z80_|execute_|ctl_inc_dec~7_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16 .lut_mask = 16'h3363; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N12 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[15] ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|address [15] = \z80_|address_latch_|Q [15] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout & -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout )))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), - .datac(\z80_|address_latch_|Q [15]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [15]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[15] .lut_mask = 16'h78F0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[15] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N26 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~21 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[7]~21_combout = ((\z80_|reg_file_|db_hi_as[7]~20_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [15]) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_hi_as[7]~20_combout ), - .datab(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|address [15]), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[7]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[7]~21 .lut_mask = 16'hBB3B; -defparam \z80_|reg_file_|db_hi_as[7]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~75 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~75_combout = ((\z80_|reg_file_|gdfx_temp1[7]~74_combout & ((\z80_|reg_file_|db_hi_as[7]~21_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[7]~74_combout ), - .datac(\z80_|reg_file_|db_hi_as[7]~21_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~75 .lut_mask = 16'hD5DD; -defparam \z80_|reg_file_|gdfx_temp1[7]~75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N6 -cycloneive_lcell_comb \z80_|alu_|db[7]~20 ( -// Equation(s): -// \z80_|alu_|db[7]~20_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[7]~75_combout & ((\z80_|alu_control_|db[7]~18_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & -// (((\z80_|alu_control_|db[7]~18_combout )) # (!\z80_|execute_|ctl_sw_2d~13_combout ))) - - .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datab(\z80_|execute_|ctl_sw_2d~13_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .datad(\z80_|alu_control_|db[7]~18_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[7]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[7]~20 .lut_mask = 16'hF531; -defparam \z80_|alu_|db[7]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N24 -cycloneive_lcell_comb \z80_|alu_|db[7]~21 ( -// Equation(s): -// \z80_|alu_|db[7]~21_combout = ((\z80_|alu_|db[7]~20_combout & ((\z80_|alu_|db_high[3]~8_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~26_combout ) - - .dataa(\z80_|alu_|db[7]~20_combout ), - .datab(\z80_|alu_|db[7]~26_combout ), - .datac(\z80_|alu_|db_high[3]~8_combout ), - .datad(\z80_|execute_|ctl_alu_oe~14_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[7]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[7]~21 .lut_mask = 16'hB3BB; -defparam \z80_|alu_|db[7]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N22 -cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~1 ( -// Equation(s): -// \z80_|alu_control_|b2v_inst_shift_mux|out~1_combout = (\z80_|ir_|opcode [5] & (\z80_|alu_|db[7]~21_combout & ((\z80_|ir_|opcode [3])))) # (!\z80_|ir_|opcode [5] & ((\z80_|ir_|opcode [3] & ((\z80_|alu_|db[0]~19_combout ))) # (!\z80_|ir_|opcode [3] & -// (\z80_|alu_|db[7]~21_combout )))) - - .dataa(\z80_|alu_|db[7]~21_combout ), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|alu_|db[0]~19_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~1 .lut_mask = 16'hB822; -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N4 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~0 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf~0_combout = (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & (\z80_|alu_control_|db[0]~12_combout & (\z80_|execute_|ctl_flags_bus~combout ))) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & -// ((\z80_|execute_|ctl_flags_alu~15_combout ) # ((\z80_|alu_control_|db[0]~12_combout & \z80_|execute_|ctl_flags_bus~combout )))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), - .datab(\z80_|alu_control_|db[0]~12_combout ), - .datac(\z80_|execute_|ctl_flags_bus~combout ), - .datad(\z80_|execute_|ctl_flags_alu~15_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~0 .lut_mask = 16'hD5C0; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~4_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # ((\z80_|execute_|ixy_d~6_combout & \z80_|execute_|ctl_mRead~36_combout ))) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|execute_|ctl_mRead~36_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~4 .lut_mask = 16'hFFF8; -defparam \z80_|execute_|ctl_flags_cf_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~5_combout = ((\z80_|execute_|ctl_flags_cf_we~4_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # (\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ))) # (!\z80_|execute_|ctl_flags_cf_we~7_combout ) - - .dataa(\z80_|execute_|ctl_flags_cf_we~7_combout ), - .datab(\z80_|execute_|ctl_flags_cf_we~4_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .datad(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~5 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_flags_cf_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~3_combout = (\z80_|execute_|ctl_flags_hf2_we~combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((!\z80_|execute_|ctl_flags_bus~5_combout ) # (!\z80_|execute_|ctl_flags_bus~4_combout )))) - - .dataa(\z80_|execute_|ctl_flags_bus~4_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|execute_|ctl_flags_hf2_we~combout ), - .datad(\z80_|execute_|ctl_flags_bus~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~3 .lut_mask = 16'hF4FC; -defparam \z80_|execute_|ctl_flags_cf_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~6_combout = ((\z80_|execute_|ctl_flags_cf_we~5_combout ) # ((\z80_|execute_|ctl_flags_cf_we~3_combout ) # (!\z80_|execute_|ctl_flags_cf_we~2_combout ))) # (!\z80_|execute_|ctl_flags_hf_we~2_combout ) - - .dataa(\z80_|execute_|ctl_flags_hf_we~2_combout ), - .datab(\z80_|execute_|ctl_flags_cf_we~5_combout ), - .datac(\z80_|execute_|ctl_flags_cf_we~3_combout ), - .datad(\z80_|execute_|ctl_flags_cf_we~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~6 .lut_mask = 16'hFDFF; -defparam \z80_|execute_|ctl_flags_cf_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_we~2_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~38_combout ) # (!\z80_|execute_|ctl_alu_op1_sel_bus~7_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_we~2 .lut_mask = 16'hCFFF; -defparam \z80_|execute_|ctl_flags_cf2_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_we~4_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & ((\z80_|pla_decode_|Equal11~0_combout ) # (\z80_|pla_decode_|Equal10~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal11~0_combout ), - .datab(\z80_|pla_decode_|Equal10~0_combout ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_we~4 .lut_mask = 16'hE000; -defparam \z80_|execute_|ctl_flags_cf2_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_we~3_combout = (\z80_|execute_|ctl_flags_cf2_we~2_combout ) # ((\z80_|execute_|ctl_flags_cf2_we~4_combout ) # ((\z80_|sequencer_|DFFE_T3_ff~q & \z80_|execute_|ixy_d~15_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|execute_|ctl_flags_cf2_we~2_combout ), - .datac(\z80_|execute_|ixy_d~15_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_we~3 .lut_mask = 16'hFFEC; -defparam \z80_|execute_|ctl_flags_cf2_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N2 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~1 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf~1_combout = (\z80_|execute_|ctl_flags_cf_we~6_combout & ((\z80_|execute_|ctl_flags_cf2_we~3_combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf~q ))) # (!\z80_|execute_|ctl_flags_cf2_we~3_combout & -// (\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout )))) # (!\z80_|execute_|ctl_flags_cf_we~6_combout & (((\z80_|alu_flags_|DFFE_inst_latch_cf~q )))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ), - .datab(\z80_|execute_|ctl_flags_cf_we~6_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), - .datad(\z80_|execute_|ctl_flags_cf2_we~3_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~1 .lut_mask = 16'hF0B8; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y9_N3 -dffeas \z80_|alu_flags_|DFFE_inst_latch_cf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N0 -cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~0 ( -// Equation(s): -// \z80_|alu_control_|b2v_inst_shift_mux|out~0_combout = (\z80_|ir_|opcode [4] & ((\z80_|ir_|opcode [5] & ((!\z80_|ir_|opcode [3]))) # (!\z80_|ir_|opcode [5] & (\z80_|alu_flags_|DFFE_inst_latch_cf~q )))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~0 .lut_mask = 16'h0A88; -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N4 -cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~2 ( -// Equation(s): -// \z80_|alu_control_|b2v_inst_shift_mux|out~2_combout = (\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ) # ((\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout & !\z80_|ir_|opcode [4])) - - .dataa(\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ), - .datab(\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ), - .datac(gnd), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~2 .lut_mask = 16'hCCEE; -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N14 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~5 ( -// Equation(s): -// \z80_|alu_|db_high[3]~5_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[6]~23_combout ))) - - .dataa(gnd), - .datab(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), - .datac(\z80_|alu_|db[6]~23_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~5 .lut_mask = 16'hCCF0; -defparam \z80_|alu_|db_high[3]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N20 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~6 ( -// Equation(s): -// \z80_|alu_|db_high[3]~6_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_high[3]~5_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[7]~21_combout ))) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .datab(\z80_|alu_|db_high[3]~5_combout ), - .datac(\z80_|alu_|db[7]~21_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~6 .lut_mask = 16'hD8D8; -defparam \z80_|alu_|db_high[3]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N28 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~4 ( -// Equation(s): -// \z80_|alu_|db_high[3]~4_combout = (\z80_|alu_|op2_high [3] & (((\z80_|alu_|op1_high [3])) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout ))) # (!\z80_|alu_|op2_high [3] & (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_high [3]) # -// (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) - - .dataa(\z80_|alu_|op2_high [3]), - .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datac(\z80_|alu_|op1_high [3]), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~4 .lut_mask = 16'hA2F3; -defparam \z80_|alu_|db_high[3]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N30 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~27 ( -// Equation(s): -// \z80_|alu_|db_high[3]~27_combout = ((\z80_|bus_control_|db[4]~19_combout & (\z80_|bus_control_|db[5]~15_combout & \z80_|bus_control_|db[3]~21_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datab(\z80_|bus_control_|db[4]~19_combout ), - .datac(\z80_|bus_control_|db[5]~15_combout ), - .datad(\z80_|bus_control_|db[3]~21_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~27 .lut_mask = 16'hD555; -defparam \z80_|alu_|db_high[3]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N6 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~7 ( -// Equation(s): -// \z80_|alu_|db_high[3]~7_combout = (\z80_|alu_|db_high[3]~4_combout & (\z80_|alu_|db_high[3]~27_combout & ((\z80_|alu_|db_high[3]~6_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) - - .dataa(\z80_|alu_|db_high[3]~6_combout ), - .datab(\z80_|alu_|db_high[3]~4_combout ), - .datac(\z80_|alu_|db_high[3]~27_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~7 .lut_mask = 16'h80C0; -defparam \z80_|alu_|db_high[3]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N28 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~8 ( -// Equation(s): -// \z80_|alu_|db_high[3]~8_combout = ((\z80_|alu_|db_high[3]~7_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) # (!\z80_|alu_|db_high[3]~3_combout ) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), - .datab(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datac(\z80_|alu_|db_high[3]~7_combout ), - .datad(\z80_|alu_|db_high[3]~3_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~8 .lut_mask = 16'hE0FF; -defparam \z80_|alu_|db_high[3]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N14 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & ((\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_low~combout & \z80_|alu_|db_high[3]~8_combout )))) - - .dataa(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .datac(\z80_|alu_|db_high[3]~8_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4 .lut_mask = 16'h00EA; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y10_N15 -dffeas \z80_|alu_|op1_low[3] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_low [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_low[3] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_low[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N0 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~9 ( -// Equation(s): -// \z80_|alu_|db_low[3]~9_combout = (\z80_|alu_|op1_low [3] & (((\z80_|alu_|op2_low [3]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|alu_|op1_low [3] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_low [3]) # -// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) - - .dataa(\z80_|alu_|op1_low [3]), - .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datac(\z80_|alu_|op2_low [3]), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~9 .lut_mask = 16'hB0BB; -defparam \z80_|alu_|db_low[3]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N10 -cycloneive_lcell_comb \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 ( -// Equation(s): -// \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout = (\z80_|bus_control_|db[4]~19_combout & \z80_|bus_control_|db[3]~21_combout ) - - .dataa(gnd), - .datab(\z80_|bus_control_|db[4]~19_combout ), - .datac(gnd), - .datad(\z80_|bus_control_|db[3]~21_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 .lut_mask = 16'hCC00; -defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N24 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~10 ( -// Equation(s): -// \z80_|alu_|db_low[3]~10_combout = (\z80_|alu_|db_low[3]~9_combout & (((!\z80_|bus_control_|db[5]~15_combout & \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout )) # (!\z80_|execute_|ctl_alu_bs_oe~combout ))) - - .dataa(\z80_|bus_control_|db[5]~15_combout ), - .datab(\z80_|alu_|db_low[3]~9_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datad(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~10 .lut_mask = 16'h4C0C; -defparam \z80_|alu_|db_low[3]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y10_N15 -dffeas \z80_|alu_|result_lo[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_alu_op_low~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|result_lo [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|result_lo[3] .is_wysiwyg = "true"; -defparam \z80_|alu_|result_lo[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N14 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~7 ( -// Equation(s): -// \z80_|alu_|db_low[3]~7_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[4]~17_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[2]~15_combout ))) - - .dataa(\z80_|alu_|db[4]~17_combout ), - .datab(gnd), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|alu_|db[2]~15_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~7 .lut_mask = 16'hAFA0; -defparam \z80_|alu_|db_low[3]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N28 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~8 ( -// Equation(s): -// \z80_|alu_|db_low[3]~8_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_low[3]~7_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[3]~11_combout ))) # -// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) - - .dataa(\z80_|alu_|db[3]~11_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datac(\z80_|alu_|db_low[3]~7_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~8 .lut_mask = 16'hF3BB; -defparam \z80_|alu_|db_low[3]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N8 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~11 ( -// Equation(s): -// \z80_|alu_|db_low[3]~11_combout = (\z80_|alu_|db_low[3]~10_combout & (\z80_|alu_|db_low[3]~8_combout & ((\z80_|alu_|result_lo [3]) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) - - .dataa(\z80_|alu_|db_low[3]~10_combout ), - .datab(\z80_|alu_|result_lo [3]), - .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datad(\z80_|alu_|db_low[3]~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~11 .lut_mask = 16'hA800; -defparam \z80_|alu_|db_low[3]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N6 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~25 ( -// Equation(s): -// \z80_|alu_|db_low[3]~25_combout = (\z80_|alu_|db_low[3]~11_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~43_combout & !\z80_|alu_|db_high[3]~2_combout )) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datab(\z80_|alu_|db_high[3]~2_combout ), - .datac(\z80_|alu_|db_low[3]~11_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~25 .lut_mask = 16'hF1F1; -defparam \z80_|alu_|db_low[3]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N12 -cycloneive_lcell_comb \z80_|alu_|db[3]~10 ( -// Equation(s): -// \z80_|alu_|db[3]~10_combout = (\z80_|execute_|ctl_alu_oe~14_combout & (\z80_|alu_|db_low[3]~25_combout & ((\z80_|reg_file_|gdfx_temp1[3]~48_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) # (!\z80_|execute_|ctl_alu_oe~14_combout & -// (((\z80_|reg_file_|gdfx_temp1[3]~48_combout )) # (!\z80_|execute_|ctl_reg_out_hi~7_combout ))) - - .dataa(\z80_|execute_|ctl_alu_oe~14_combout ), - .datab(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .datad(\z80_|alu_|db_low[3]~25_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[3]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[3]~10 .lut_mask = 16'hF351; -defparam \z80_|alu_|db[3]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N12 -cycloneive_lcell_comb \z80_|alu_|db[3]~11 ( -// Equation(s): -// \z80_|alu_|db[3]~11_combout = ((\z80_|alu_|db[3]~10_combout & ((\z80_|alu_control_|db[3]~35_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|alu_|db[7]~26_combout ) - - .dataa(\z80_|alu_|db[3]~10_combout ), - .datab(\z80_|execute_|ctl_sw_2d~13_combout ), - .datac(\z80_|alu_control_|db[3]~35_combout ), - .datad(\z80_|alu_|db[7]~26_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[3]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[3]~11 .lut_mask = 16'hA2FF; -defparam \z80_|alu_|db[3]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~7 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~7_combout = (((\z80_|nM1_int~2_combout & \z80_|execute_|ctl_alu_oe~3_combout )) # (!\z80_|execute_|ctl_reg_out_hi~6_combout )) # (!\z80_|execute_|ctl_alu_oe~9_combout ) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_alu_oe~3_combout ), - .datac(\z80_|execute_|ctl_alu_oe~9_combout ), - .datad(\z80_|execute_|ctl_reg_out_hi~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~7 .lut_mask = 16'h8FFF; -defparam \z80_|execute_|ctl_sw_2u~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|setM1~49 ( -// Equation(s): -// \z80_|execute_|setM1~49_combout = (\z80_|execute_|setM1~48_combout & (!\z80_|pla_decode_|Equal52~1_combout & ((!\z80_|pla_decode_|Equal63~0_combout ) # (!\z80_|pla_decode_|Equal3~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal3~0_combout ), - .datab(\z80_|pla_decode_|Equal63~0_combout ), - .datac(\z80_|execute_|setM1~48_combout ), - .datad(\z80_|pla_decode_|Equal52~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~49 .lut_mask = 16'h0070; -defparam \z80_|execute_|setM1~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_oe~2_combout = (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_state_alu~14_combout ) # ((!\z80_|execute_|ctl_flags_oe~1_combout ) # (!\z80_|execute_|setM1~49_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~14_combout ), - .datab(\z80_|execute_|setM1~49_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|execute_|ctl_flags_oe~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_oe~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_oe~2 .lut_mask = 16'h0B0F; -defparam \z80_|execute_|ctl_flags_oe~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N30 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_35 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout = (\z80_|alu_|db_low[3]~25_combout & ((\z80_|execute_|ctl_flags_alu~15_combout ) # ((\z80_|alu_control_|db[3]~35_combout & \z80_|execute_|ctl_flags_bus~combout )))) # (!\z80_|alu_|db_low[3]~25_combout & -// (\z80_|alu_control_|db[3]~35_combout & (\z80_|execute_|ctl_flags_bus~combout ))) - - .dataa(\z80_|alu_|db_low[3]~25_combout ), - .datab(\z80_|alu_control_|db[3]~35_combout ), - .datac(\z80_|execute_|ctl_flags_bus~combout ), - .datad(\z80_|execute_|ctl_flags_alu~15_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_35 .lut_mask = 16'hEAC0; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~7_combout = (\z80_|execute_|ctl_flags_xy_we~12_combout & !\z80_|execute_|ctl_flags_sz_we~6_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_flags_xy_we~12_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_flags_sz_we~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~7 .lut_mask = 16'h00CC; -defparam \z80_|execute_|ctl_flags_sz_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout = (\z80_|pla_decode_|Equal56~0_combout & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T2_ff~q )) - - .dataa(\z80_|pla_decode_|Equal56~0_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3 .lut_mask = 16'h8080; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~13 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~13_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ) # ((\z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ) # -// (!\z80_|execute_|ctl_flags_xy_we~10_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ), - .datab(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), - .datad(\z80_|execute_|ctl_flags_xy_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~13 .lut_mask = 16'hFEFF; -defparam \z80_|execute_|ctl_flags_xy_we~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~14 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~14_combout = (((\z80_|execute_|ctl_flags_xy_we~13_combout ) # (!\z80_|execute_|ctl_flags_xy_we~7_combout )) # (!\z80_|execute_|ctl_flags_xy_we~9_combout )) # (!\z80_|execute_|ctl_flags_xy_we~16_combout ) - - .dataa(\z80_|execute_|ctl_flags_xy_we~16_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~9_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~13_combout ), - .datad(\z80_|execute_|ctl_flags_xy_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~14 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|ctl_flags_xy_we~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~15 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~15_combout = (((\z80_|execute_|ctl_flags_xy_we~14_combout ) # (!\z80_|execute_|ctl_flags_pf_we~4_combout )) # (!\z80_|execute_|ctl_flags_sz_we~7_combout )) # (!\z80_|execute_|ctl_pf_sel[0]~3_combout ) - - .dataa(\z80_|execute_|ctl_pf_sel[0]~3_combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~7_combout ), - .datac(\z80_|execute_|ctl_flags_pf_we~4_combout ), - .datad(\z80_|execute_|ctl_flags_xy_we~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~15 .lut_mask = 16'hFF7F; -defparam \z80_|execute_|ctl_flags_xy_we~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y11_N31 -dffeas \z80_|alu_flags_|flags_xf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_flags_xy_we~15_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|flags_xf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_xf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|flags_xf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N8 -cycloneive_lcell_comb \z80_|alu_control_|db[3]~33 ( -// Equation(s): -// \z80_|alu_control_|db[3]~33_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & ((\z80_|alu_flags_|flags_xf~q ) # (!\z80_|execute_|ctl_flags_oe~2_combout ))) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_flags_oe~2_combout ), - .datac(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .datad(\z80_|alu_flags_|flags_xf~q ), - .cin(gnd), - .combout(\z80_|alu_control_|db[3]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[3]~33 .lut_mask = 16'hF030; -defparam \z80_|alu_control_|db[3]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~3_combout = (\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ) # ((\z80_|execute_|ctl_reg_out_lo~2_combout & \z80_|execute_|rsel3~combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), - .datab(\z80_|execute_|ctl_reg_out_lo~2_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), - .datad(\z80_|execute_|rsel3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~3 .lut_mask = 16'hFEFA; -defparam \z80_|execute_|ctl_reg_out_lo~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout = (\z80_|pla_decode_|Equal1~7_combout & (\z80_|execute_|ixy_d~7_combout & (!\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal3~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~7_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal3~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~4_combout = (\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ) # ((\z80_|execute_|ixy_d~9_combout & ((\z80_|pla_decode_|Equal40~1_combout ) # (\z80_|pla_decode_|Equal39~0_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ), - .datab(\z80_|pla_decode_|Equal40~1_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~4 .lut_mask = 16'hFAEA; -defparam \z80_|execute_|ctl_reg_out_lo~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~5_combout = (\z80_|execute_|ctl_reg_out_lo~3_combout ) # (((\z80_|execute_|ctl_reg_out_lo~4_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout )) # (!\z80_|execute_|ctl_reg_out_lo~9_combout )) - - .dataa(\z80_|execute_|ctl_reg_out_lo~3_combout ), - .datab(\z80_|execute_|ctl_reg_out_lo~9_combout ), - .datac(\z80_|execute_|ctl_reg_out_lo~4_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~5 .lut_mask = 16'hFBFF; -defparam \z80_|execute_|ctl_reg_out_lo~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~8_combout = ((\z80_|execute_|ctl_reg_out_lo~5_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout )) # (!\z80_|execute_|ctl_reg_out_lo~7_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), - .datad(\z80_|execute_|ctl_reg_out_lo~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~8 .lut_mask = 16'hFF3F; -defparam \z80_|execute_|ctl_reg_out_lo~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N16 -cycloneive_lcell_comb \z80_|sw1_|db_down[3]~1 ( -// Equation(s): -// \z80_|sw1_|db_down[3]~1_combout = (\z80_|bus_control_|db[3]~21_combout ) # ((\z80_|execute_|ctl_sw_1d~6_combout & ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|execute_|ctl_66_oe~2_combout )))) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|execute_|ctl_sw_1d~6_combout ), - .datac(\z80_|execute_|ctl_66_oe~2_combout ), - .datad(\z80_|bus_control_|db[3]~21_combout ), - .cin(gnd), - .combout(\z80_|sw1_|db_down[3]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sw1_|db_down[3]~1 .lut_mask = 16'hFF8C; -defparam \z80_|sw1_|db_down[3]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N10 -cycloneive_lcell_comb \z80_|alu_control_|db[3]~34 ( -// Equation(s): -// \z80_|alu_control_|db[3]~34_combout = (\z80_|alu_control_|db[3]~33_combout & (\z80_|sw1_|db_down[3]~1_combout & ((\z80_|reg_file_|gdfx_temp0[3]~52_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .datab(\z80_|alu_control_|db[3]~33_combout ), - .datac(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datad(\z80_|sw1_|db_down[3]~1_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[3]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[3]~34 .lut_mask = 16'h8C00; -defparam \z80_|alu_control_|db[3]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N0 -cycloneive_lcell_comb \z80_|alu_control_|db[3]~35 ( -// Equation(s): -// \z80_|alu_control_|db[3]~35_combout = ((\z80_|alu_control_|db[3]~34_combout & ((\z80_|alu_|db[3]~11_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|alu_|db[3]~11_combout ), - .datab(\z80_|alu_control_|db[6]~11_combout ), - .datac(\z80_|execute_|ctl_sw_2u~7_combout ), - .datad(\z80_|alu_control_|db[3]~34_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[3]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[3]~35 .lut_mask = 16'hBF33; -defparam \z80_|alu_control_|db[3]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~46 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~46_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [3] & ((\z80_|alu_control_|db[3]~35_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (((\z80_|alu_control_|db[3]~35_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [3]), - .datad(\z80_|alu_control_|db[3]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~46 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[3]~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~47 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~47_combout = (\z80_|reg_file_|gdfx_temp0[3]~46_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(\z80_|reg_file_|b2v_latch_wz_lo|latch [3]), - .datab(gnd), - .datac(\z80_|reg_file_|gdfx_temp0[3]~46_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~47 .lut_mask = 16'hA0F0; -defparam \z80_|reg_file_|gdfx_temp0[3]~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~50 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~50_combout = (\z80_|reg_file_|gdfx_temp0[3]~48_combout & (\z80_|reg_file_|gdfx_temp0[3]~49_combout & \z80_|reg_file_|gdfx_temp0[3]~47_combout )) - - .dataa(gnd), - .datab(\z80_|reg_file_|gdfx_temp0[3]~48_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[3]~49_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[3]~47_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~50 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|gdfx_temp0[3]~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y9_N31 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y9_N5 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~44 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~44_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [3] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [3] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [3]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~44 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[3]~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y13_N7 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y13_N5 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~43 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~43_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [3] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [3] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [3]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~43 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[3]~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~51 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~51_combout = (\z80_|reg_file_|gdfx_temp0[3]~45_combout & (\z80_|reg_file_|gdfx_temp0[3]~50_combout & (\z80_|reg_file_|gdfx_temp0[3]~44_combout & \z80_|reg_file_|gdfx_temp0[3]~43_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[3]~45_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[3]~50_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[3]~44_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[3]~43_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~51 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[3]~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~52 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~52_combout = ((\z80_|reg_file_|gdfx_temp0[3]~51_combout & ((\z80_|reg_file_|db_lo_as[3]~12_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[3]~12_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~52 .lut_mask = 16'h8FCF; -defparam \z80_|reg_file_|gdfx_temp0[3]~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N13 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[3]~12_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N12 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~10 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[3]~10_combout = (\z80_|reg_file_|gdfx_temp0[3]~52_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) # (!\z80_|reg_file_|gdfx_temp0[3]~52_combout & -// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [3]), - .datad(\z80_|execute_|ctl_sw_4d~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[3]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[3]~10 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_lo_as[3]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y17_N3 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[3]~12_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N20 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~11 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[3]~11_combout = (\z80_|reg_file_|db_lo_as[3]~10_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(\z80_|reg_file_|db_lo_as[3]~10_combout ), - .datab(gnd), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [3]), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[3]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[3]~11 .lut_mask = 16'hAA0A; -defparam \z80_|reg_file_|db_lo_as[3]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N2 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~12 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[3]~12_combout = ((\z80_|reg_file_|db_lo_as[3]~11_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datad(\z80_|reg_file_|db_lo_as[3]~11_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[3]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[3]~12 .lut_mask = 16'hBF0F; -defparam \z80_|reg_file_|db_lo_as[3]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N2 -cycloneive_lcell_comb \z80_|address_latch_|abusz[3] ( -// Equation(s): -// \z80_|address_latch_|abusz [3] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[3]~12_combout ) - - .dataa(gnd), - .datab(\z80_|resets_|clrpc~0_combout ), - .datac(\z80_|reg_file_|db_lo_as[3]~12_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [3]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[3] .lut_mask = 16'h3030; -defparam \z80_|address_latch_|abusz[3] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y17_N17 -dffeas \z80_|address_latch_|Q[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|address_latch_|abusz [3]), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[3] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N20 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout = \z80_|address_latch_|Q [3] $ (((\z80_|execute_|ctl_inc_dec~10_combout ) # ((!\z80_|execute_|ctl_inc_dec~5_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) - - .dataa(\z80_|execute_|ctl_inc_dec~10_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .datac(\z80_|execute_|ctl_inc_dec~5_combout ), - .datad(\z80_|address_latch_|Q [3]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4 .lut_mask = 16'h40BF; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N6 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout & -// (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout ))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ), - .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 .lut_mask = 16'h8000; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N12 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout = \z80_|address_latch_|Q [4] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout & -// (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout )))) - - .dataa(\z80_|address_latch_|Q [4]), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ), - .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out .lut_mask = 16'h6AAA; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y13_N27 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y13_N9 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~53 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~53_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [4] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [4] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [4]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~53_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~53 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[4]~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~54 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~54_combout = (\z80_|reg_file_|gdfx_temp0[4]~53_combout & ((\z80_|alu_control_|db[4]~32_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) - - .dataa(\z80_|alu_control_|db[4]~32_combout ), - .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[4]~53_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~54_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~54 .lut_mask = 16'hBB00; -defparam \z80_|reg_file_|gdfx_temp0[4]~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N27 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y10_N1 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~58 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~58_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~58_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~58 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[4]~58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y11_N31 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y11_N23 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y11_N21 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~59 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~59_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_bc_lo|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~59_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~59 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[4]~59 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~60 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~60_combout = (\z80_|reg_file_|gdfx_temp0[4]~58_combout & (\z80_|reg_file_|gdfx_temp0[4]~59_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[4]~58_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [4]), - .datad(\z80_|reg_file_|gdfx_temp0[4]~59_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~60_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~60 .lut_mask = 16'hA200; -defparam \z80_|reg_file_|gdfx_temp0[4]~60 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y9_N21 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y9_N11 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~57 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~57_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (\z80_|reg_file_|b2v_latch_hl2_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (((\z80_|reg_file_|b2v_latch_hl_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~57_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~57 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[4]~57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y10_N1 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y10_N7 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~55 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~55_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datac(\z80_|reg_file_|b2v_latch_iy_lo|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_sp_lo|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~55_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~55 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[4]~55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y11_N21 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~56 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~56_combout = (\z80_|reg_file_|gdfx_temp0[4]~55_combout & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[4]~55_combout ), - .datab(gnd), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~56_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~56 .lut_mask = 16'hA0AA; -defparam \z80_|reg_file_|gdfx_temp0[4]~56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~61 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~61_combout = (\z80_|reg_file_|gdfx_temp0[4]~54_combout & (\z80_|reg_file_|gdfx_temp0[4]~60_combout & (\z80_|reg_file_|gdfx_temp0[4]~57_combout & \z80_|reg_file_|gdfx_temp0[4]~56_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[4]~54_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[4]~60_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[4]~57_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[4]~56_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~61 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[4]~61 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~62 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~62_combout = ((\z80_|reg_file_|gdfx_temp0[4]~61_combout & ((\z80_|reg_file_|db_lo_as[4]~15_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .datac(\z80_|reg_file_|db_lo_as[4]~15_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~62 .lut_mask = 16'hB3BB; -defparam \z80_|reg_file_|gdfx_temp0[4]~62 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N7 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[4]~15_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N6 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~13 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[4]~13_combout = (\z80_|reg_file_|gdfx_temp0[4]~62_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # (!\z80_|reg_file_|gdfx_temp0[4]~62_combout & -// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .datab(\z80_|execute_|ctl_sw_4d~6_combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[4]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[4]~13 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|db_lo_as[4]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y17_N7 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[4]~15_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N12 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~14 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[4]~14_combout = (\z80_|reg_file_|db_lo_as[4]~13_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|db_lo_as[4]~13_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[4]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[4]~14 .lut_mask = 16'hCC0C; -defparam \z80_|reg_file_|db_lo_as[4]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N6 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~15 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[4]~15_combout = ((\z80_|reg_file_|db_lo_as[4]~14_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datad(\z80_|reg_file_|db_lo_as[4]~14_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[4]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[4]~15 .lut_mask = 16'hBF0F; -defparam \z80_|reg_file_|db_lo_as[4]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N16 -cycloneive_lcell_comb \z80_|address_latch_|abusz[4] ( -// Equation(s): -// \z80_|address_latch_|abusz [4] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[4]~15_combout ) - - .dataa(gnd), - .datab(\z80_|resets_|clrpc~0_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|db_lo_as[4]~15_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [4]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[4] .lut_mask = 16'h3300; -defparam \z80_|address_latch_|abusz[4] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y17_N23 -dffeas \z80_|address_latch_|Q[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|address_latch_|abusz [4]), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[4] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N22 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout = \z80_|address_latch_|Q [4] $ (((\z80_|execute_|ctl_inc_dec~9_combout ) # ((\z80_|execute_|ctl_inc_dec~7_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout )))) - - .dataa(\z80_|execute_|ctl_inc_dec~9_combout ), - .datab(\z80_|execute_|ctl_inc_dec~6_combout ), - .datac(\z80_|address_latch_|Q [4]), - .datad(\z80_|execute_|ctl_inc_dec~7_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 .lut_mask = 16'h0F4B; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N28 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout = \z80_|address_latch_|Q [5] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout & \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout -// ))) - - .dataa(\z80_|address_latch_|Q [5]), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out .lut_mask = 16'h6A6A; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y9_N23 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y9_N13 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~64 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~64_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [5] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [5] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [5]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~64_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~64 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[5]~64 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y9_N21 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y9_N23 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~63 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~63_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (\z80_|reg_file_|b2v_latch_de2_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_de_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & ((\z80_|reg_file_|b2v_latch_de_lo|latch [5]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datab(\z80_|reg_file_|b2v_latch_de_lo|latch [5]), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~63_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~63 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[5]~63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y11_N9 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y11_N5 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~66 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~66_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [5] & ((\z80_|alu_control_|db[5]~15_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (((\z80_|alu_control_|db[5]~15_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [5]), - .datad(\z80_|alu_control_|db[5]~15_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~66_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~66 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[5]~66 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~67 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~67_combout = (\z80_|reg_file_|gdfx_temp0[5]~66_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [5]), - .datad(\z80_|reg_file_|gdfx_temp0[5]~66_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~67_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~67 .lut_mask = 16'hF300; -defparam \z80_|reg_file_|gdfx_temp0[5]~67 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N31 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y10_N17 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~65 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~65_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [5]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [5]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~65_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~65 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[5]~65 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y10_N31 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N28 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder_combout = \z80_|reg_file_|gdfx_temp0[5]~72_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y10_N29 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~69 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~69_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [5]), - .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [5]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~69_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~69 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[5]~69 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N6 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder_combout = \z80_|reg_file_|gdfx_temp0[5]~72_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y11_N7 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y11_N3 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~68 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~68_combout = (\z80_|reg_file_|b2v_latch_ix_lo|latch [5] & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # (!\z80_|reg_file_|b2v_latch_ix_lo|latch [5] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_ix_lo|latch [5]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc_lo|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~68_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~68 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[5]~68 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~70 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~70_combout = (\z80_|reg_file_|gdfx_temp0[5]~67_combout & (\z80_|reg_file_|gdfx_temp0[5]~65_combout & (\z80_|reg_file_|gdfx_temp0[5]~69_combout & \z80_|reg_file_|gdfx_temp0[5]~68_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[5]~67_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[5]~65_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[5]~69_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[5]~68_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~70_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~70 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[5]~70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~71 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~71_combout = (\z80_|reg_file_|gdfx_temp0[5]~64_combout & (\z80_|reg_file_|gdfx_temp0[5]~63_combout & \z80_|reg_file_|gdfx_temp0[5]~70_combout )) - - .dataa(\z80_|reg_file_|gdfx_temp0[5]~64_combout ), - .datab(gnd), - .datac(\z80_|reg_file_|gdfx_temp0[5]~63_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[5]~70_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~71 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|gdfx_temp0[5]~71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~72 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~72_combout = ((\z80_|reg_file_|gdfx_temp0[5]~71_combout & ((\z80_|reg_file_|db_lo_as[5]~18_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .datab(\z80_|reg_file_|db_lo_as[5]~18_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~72 .lut_mask = 16'hD5F5; -defparam \z80_|reg_file_|gdfx_temp0[5]~72 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N5 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[5]~18_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N4 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~16 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[5]~16_combout = (\z80_|reg_file_|gdfx_temp0[5]~72_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # (!\z80_|reg_file_|gdfx_temp0[5]~72_combout & -// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .datab(\z80_|execute_|ctl_sw_4d~6_combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[5]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[5]~16 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|db_lo_as[5]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y15_N25 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[5]~18_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N2 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~17 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[5]~17_combout = (\z80_|reg_file_|db_lo_as[5]~16_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datab(gnd), - .datac(\z80_|reg_file_|db_lo_as[5]~16_combout ), - .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [5]), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[5]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[5]~17 .lut_mask = 16'hF050; -defparam \z80_|reg_file_|db_lo_as[5]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N24 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~18 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[5]~18_combout = ((\z80_|reg_file_|db_lo_as[5]~17_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datad(\z80_|reg_file_|db_lo_as[5]~17_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[5]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[5]~18 .lut_mask = 16'hBF0F; -defparam \z80_|reg_file_|db_lo_as[5]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N26 -cycloneive_lcell_comb \z80_|address_latch_|abusz[5] ( -// Equation(s): -// \z80_|address_latch_|abusz [5] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[5]~18_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(\z80_|reg_file_|db_lo_as[5]~18_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [5]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[5] .lut_mask = 16'h0F00; -defparam \z80_|address_latch_|abusz[5] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y16_N27 -dffeas \z80_|address_latch_|Q[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [5]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[5] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N26 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout = \z80_|address_latch_|Q [5] $ ((((\z80_|execute_|ctl_inc_dec~10_combout ) # (!\z80_|execute_|ctl_inc_dec~5_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout ))) - - .dataa(\z80_|address_latch_|Q [5]), - .datab(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .datac(\z80_|execute_|ctl_inc_dec~5_combout ), - .datad(\z80_|execute_|ctl_inc_dec~10_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4 .lut_mask = 16'h5595; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N16 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[6] ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|address [6] = \z80_|address_latch_|Q [6] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout & -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout )))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|address_latch_|Q [6]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[6] .lut_mask = 16'h78F0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[6] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y17_N11 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[6]~21_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y9_N17 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N6 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder_combout = \z80_|reg_file_|gdfx_temp0[6]~82_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y9_N7 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~74 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~74_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (\z80_|reg_file_|b2v_latch_hl2_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (((\z80_|reg_file_|b2v_latch_hl_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~74_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~74 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[6]~74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y9_N19 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y9_N5 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~73 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~73_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (\z80_|reg_file_|b2v_latch_de2_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_de_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & ((\z80_|reg_file_|b2v_latch_de_lo|latch [6]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datab(\z80_|reg_file_|b2v_latch_de_lo|latch [6]), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~73_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~73 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[6]~73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y10_N19 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N2 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder_combout = \z80_|reg_file_|gdfx_temp0[6]~82_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y10_N3 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~78 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~78_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~78_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~78 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[6]~78 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N29 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~79 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~79_combout = (\z80_|reg_file_|b2v_latch_sp_lo|latch [6] & (((\z80_|alu_control_|db[6]~22_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) # (!\z80_|reg_file_|b2v_latch_sp_lo|latch [6] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|alu_control_|db[6]~22_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_sp_lo|latch [6]), - .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datac(\z80_|alu_control_|db[6]~22_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~79_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~79 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[6]~79 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y10_N17 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N16 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder_combout = \z80_|reg_file_|gdfx_temp0[6]~82_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y11_N17 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y11_N19 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~76 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~76_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [6]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [6]), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~76_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~76 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[6]~76 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~77 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~77_combout = (\z80_|reg_file_|gdfx_temp0[6]~76_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [6]), - .datad(\z80_|reg_file_|gdfx_temp0[6]~76_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~77_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~77 .lut_mask = 16'hF300; -defparam \z80_|reg_file_|gdfx_temp0[6]~77 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~80 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~80_combout = (\z80_|reg_file_|gdfx_temp0[6]~78_combout & (\z80_|reg_file_|gdfx_temp0[6]~79_combout & \z80_|reg_file_|gdfx_temp0[6]~77_combout )) - - .dataa(gnd), - .datab(\z80_|reg_file_|gdfx_temp0[6]~78_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[6]~79_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[6]~77_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~80 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|gdfx_temp0[6]~80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N5 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y14_N25 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~75 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~75_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~75_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~75 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[6]~75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~81 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~81_combout = (\z80_|reg_file_|gdfx_temp0[6]~74_combout & (\z80_|reg_file_|gdfx_temp0[6]~73_combout & (\z80_|reg_file_|gdfx_temp0[6]~80_combout & \z80_|reg_file_|gdfx_temp0[6]~75_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[6]~74_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[6]~73_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[6]~75_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~81_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~81 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[6]~81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~82 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~82_combout = ((\z80_|reg_file_|gdfx_temp0[6]~81_combout & ((\z80_|reg_file_|db_lo_as[6]~21_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp0[6]~81_combout ), - .datab(\z80_|reg_file_|db_lo_as[6]~21_combout ), - .datac(\z80_|execute_|ctl_sw_4u~6_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~82 .lut_mask = 16'h8AFF; -defparam \z80_|reg_file_|gdfx_temp0[6]~82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N19 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[6]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N18 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~19 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[6]~19_combout = (\z80_|reg_file_|gdfx_temp0[6]~82_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # (!\z80_|reg_file_|gdfx_temp0[6]~82_combout & -// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .datab(\z80_|execute_|ctl_sw_4d~6_combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[6]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[6]~19 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|db_lo_as[6]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N16 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~20 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[6]~20_combout = (\z80_|reg_file_|db_lo_as[6]~19_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_lo|latch [6]), - .datad(\z80_|reg_file_|db_lo_as[6]~19_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[6]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[6]~20 .lut_mask = 16'hF300; -defparam \z80_|reg_file_|db_lo_as[6]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N10 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~21 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[6]~21_combout = ((\z80_|reg_file_|db_lo_as[6]~20_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [6]) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), - .datac(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datad(\z80_|reg_file_|db_lo_as[6]~20_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[6]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[6]~21 .lut_mask = 16'hDF55; -defparam \z80_|reg_file_|db_lo_as[6]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N22 -cycloneive_lcell_comb \z80_|address_latch_|abusz[6] ( -// Equation(s): -// \z80_|address_latch_|abusz [6] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[6]~21_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(\z80_|reg_file_|db_lo_as[6]~21_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [6]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[6] .lut_mask = 16'h0F00; -defparam \z80_|address_latch_|abusz[6] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y16_N23 -dffeas \z80_|address_latch_|Q[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [6]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[6] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N6 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout = (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|address_latch_|Q [6] $ (((\z80_|execute_|ctl_inc_dec~10_combout ) # (\z80_|execute_|ctl_inc_dec~7_combout ))))) - - .dataa(\z80_|execute_|ctl_inc_dec~10_combout ), - .datab(\z80_|execute_|ctl_inc_dec~7_combout ), - .datac(\z80_|address_latch_|Q [6]), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 .lut_mask = 16'h001E; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N0 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout & -// (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout ))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 .lut_mask = 16'h8000; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N24 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout = \z80_|address_latch_|Q [7] $ (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ) - - .dataa(\z80_|address_latch_|Q [7]), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out .lut_mask = 16'h55AA; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N24 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~24 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[7]~24_combout = ((\z80_|reg_file_|db_lo_as[7]~23_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|reg_file_|db_lo_as[7]~23_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[7]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[7]~24 .lut_mask = 16'hF575; -defparam \z80_|reg_file_|db_lo_as[7]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y9_N25 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y9_N11 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~83 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~83_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (\z80_|reg_file_|b2v_latch_de2_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_de_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & ((\z80_|reg_file_|b2v_latch_de_lo|latch [7]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datab(\z80_|reg_file_|b2v_latch_de_lo|latch [7]), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~83_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~83 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[7]~83 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y9_N29 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y9_N19 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~84 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~84_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (\z80_|reg_file_|b2v_latch_hl2_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (((\z80_|reg_file_|b2v_latch_hl_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~84_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~84 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[7]~84 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y10_N11 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N12 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder_combout = \z80_|reg_file_|gdfx_temp0[7]~92_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y10_N13 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~88 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~88_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~88_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~88 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[7]~88 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y10_N21 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y11_N9 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y11_N7 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~86 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~86_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [7]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [7]), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~86_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~86 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[7]~86 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~87 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~87_combout = (\z80_|reg_file_|gdfx_temp0[7]~86_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [7]), - .datad(\z80_|reg_file_|gdfx_temp0[7]~86_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~87_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~87 .lut_mask = 16'hF300; -defparam \z80_|reg_file_|gdfx_temp0[7]~87 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N25 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y10_N19 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~85 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~85_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~85_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~85 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[7]~85 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N15 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~89 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~89_combout = (\z80_|reg_file_|b2v_latch_sp_lo|latch [7] & (((\z80_|alu_control_|db[7]~18_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) # (!\z80_|reg_file_|b2v_latch_sp_lo|latch [7] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|alu_control_|db[7]~18_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_sp_lo|latch [7]), - .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datac(\z80_|alu_control_|db[7]~18_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~89_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~89 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[7]~89 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~90 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~90_combout = (\z80_|reg_file_|gdfx_temp0[7]~88_combout & (\z80_|reg_file_|gdfx_temp0[7]~87_combout & (\z80_|reg_file_|gdfx_temp0[7]~85_combout & \z80_|reg_file_|gdfx_temp0[7]~89_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[7]~88_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[7]~87_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[7]~85_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[7]~89_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~90 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[7]~90 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~91 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~91_combout = (\z80_|reg_file_|gdfx_temp0[7]~83_combout & (\z80_|reg_file_|gdfx_temp0[7]~84_combout & \z80_|reg_file_|gdfx_temp0[7]~90_combout )) - - .dataa(\z80_|reg_file_|gdfx_temp0[7]~83_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[7]~84_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~91 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|gdfx_temp0[7]~91 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~92 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~92_combout = ((\z80_|reg_file_|gdfx_temp0[7]~91_combout & ((\z80_|reg_file_|db_lo_as[7]~24_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[7]~24_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), - .datac(\z80_|execute_|ctl_sw_4u~6_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~92 .lut_mask = 16'h8CFF; -defparam \z80_|reg_file_|gdfx_temp0[7]~92 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N6 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[7]~0 ( -// Equation(s): -// \z80_|reg_file_|db_lo_ds[7]~0_combout = (\z80_|reg_file_|gdfx_temp0[7]~92_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout & (\z80_|execute_|ctl_reg_out_lo~7_combout & !\z80_|execute_|ctl_reg_out_lo~5_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), - .datab(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .datad(\z80_|execute_|ctl_reg_out_lo~5_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_ds[7]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_ds[7]~0 .lut_mask = 16'hF0F8; -defparam \z80_|reg_file_|db_lo_ds[7]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y10_N11 -dffeas \z80_|interrupts_|im2 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_im_we~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|interrupts_|im2~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|interrupts_|im2 .is_wysiwyg = "true"; -defparam \z80_|interrupts_|im2 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~12 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~12_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|interrupts_|im2~q & \z80_|interrupts_|DFFE_inst44~q )) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(gnd), - .datac(\z80_|interrupts_|im2~q ), - .datad(\z80_|interrupts_|DFFE_inst44~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~12 .lut_mask = 16'h5000; -defparam \z80_|execute_|ctl_mRead~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_mask543_en~0 ( -// Equation(s): -// \z80_|execute_|ctl_sw_mask543_en~0_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (!\z80_|execute_|ctl_mRead~12_combout & \z80_|pla_decode_|Equal47~0_combout ))) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|execute_|ctl_mRead~12_combout ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_mask543_en~0 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_sw_mask543_en~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N12 -cycloneive_lcell_comb \z80_|alu_control_|db[7]~17 ( -// Equation(s): -// \z80_|alu_control_|db[7]~17_combout = (\z80_|reg_file_|db_lo_ds[7]~0_combout & (((!\z80_|execute_|ctl_sw_mask543_en~0_combout & \z80_|bus_control_|db[7]~7_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) - - .dataa(\z80_|reg_file_|db_lo_ds[7]~0_combout ), - .datab(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .datac(\z80_|execute_|ctl_sw_1d~7_combout ), - .datad(\z80_|bus_control_|db[7]~7_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[7]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[7]~17 .lut_mask = 16'h2A0A; -defparam \z80_|alu_control_|db[7]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N16 -cycloneive_lcell_comb \z80_|alu_control_|db[7]~16 ( -// Equation(s): -// \z80_|alu_control_|db[7]~16_combout = (\z80_|execute_|ctl_flags_oe~2_combout & (((\z80_|execute_|ctl_sw_2u~7_combout & !\z80_|alu_|db[7]~21_combout )) # (!\z80_|alu_flags_|DFFE_inst_latch_sf~q ))) # (!\z80_|execute_|ctl_flags_oe~2_combout & -// (\z80_|execute_|ctl_sw_2u~7_combout & (!\z80_|alu_|db[7]~21_combout ))) - - .dataa(\z80_|execute_|ctl_flags_oe~2_combout ), - .datab(\z80_|execute_|ctl_sw_2u~7_combout ), - .datac(\z80_|alu_|db[7]~21_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), - .cin(gnd), - .combout(\z80_|alu_control_|db[7]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[7]~16 .lut_mask = 16'h0CAE; -defparam \z80_|alu_control_|db[7]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N14 -cycloneive_lcell_comb \z80_|alu_control_|db[7]~18 ( -// Equation(s): -// \z80_|alu_control_|db[7]~18_combout = ((\z80_|alu_control_|db[7]~17_combout & (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & !\z80_|alu_control_|db[7]~16_combout ))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|alu_control_|db[7]~17_combout ), - .datab(\z80_|alu_control_|db[6]~11_combout ), - .datac(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .datad(\z80_|alu_control_|db[7]~16_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[7]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[7]~18 .lut_mask = 16'h33B3; -defparam \z80_|alu_control_|db[7]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N8 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_34 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout = (\z80_|execute_|ctl_flags_bus~combout & ((\z80_|alu_control_|db[7]~18_combout ) # ((\z80_|alu_|db_high[3]~8_combout & \z80_|execute_|ctl_flags_alu~15_combout )))) # (!\z80_|execute_|ctl_flags_bus~combout -// & (((\z80_|alu_|db_high[3]~8_combout & \z80_|execute_|ctl_flags_alu~15_combout )))) - - .dataa(\z80_|execute_|ctl_flags_bus~combout ), - .datab(\z80_|alu_control_|db[7]~18_combout ), - .datac(\z80_|alu_|db_high[3]~8_combout ), - .datad(\z80_|execute_|ctl_flags_alu~15_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_34 .lut_mask = 16'hF888; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~8_combout = (((!\z80_|execute_|ctl_flags_sz_we~7_combout ) # (!\z80_|execute_|ctl_flags_sz_we~2_combout )) # (!\z80_|execute_|ctl_flags_sz_we~4_combout )) # (!\z80_|execute_|ctl_flags_sz_we~3_combout ) - - .dataa(\z80_|execute_|ctl_flags_sz_we~3_combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~4_combout ), - .datac(\z80_|execute_|ctl_flags_sz_we~2_combout ), - .datad(\z80_|execute_|ctl_flags_sz_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~8 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_flags_sz_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y9_N9 -dffeas \z80_|alu_flags_|DFFE_inst_latch_sf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_flags_sz_we~8_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_sf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_sf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N26 -cycloneive_lcell_comb \z80_|pla_decode_|Equal62~3 ( -// Equation(s): -// \z80_|pla_decode_|Equal62~3_combout = (\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [3] & \z80_|execute_|ctl_state_alu~12_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|execute_|ctl_state_alu~12_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal62~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal62~3 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal62~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~5_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal62~3_combout ) # ((\z80_|execute_|ctl_mWrite~16_combout ) # (\z80_|pla_decode_|Equal11~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal62~3_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_mWrite~16_combout ), - .datad(\z80_|pla_decode_|Equal11~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~5 .lut_mask = 16'hCCC8; -defparam \z80_|execute_|ctl_flags_pf_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~6_combout = (\z80_|pla_decode_|Equal69~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|pla_decode_|Equal69~0_combout ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~6 .lut_mask = 16'h008C; -defparam \z80_|execute_|ctl_flags_pf_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~7_combout = (\z80_|execute_|ctl_flags_pf_we~6_combout ) # ((\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # ((\z80_|nM1_int~2_combout & \z80_|execute_|ctl_mRead~36_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_mRead~36_combout ), - .datac(\z80_|execute_|ctl_flags_pf_we~6_combout ), - .datad(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~7 .lut_mask = 16'hFFF8; -defparam \z80_|execute_|ctl_flags_pf_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~8_combout = (((\z80_|execute_|ctl_flags_pf_we~5_combout ) # (\z80_|execute_|ctl_flags_pf_we~7_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~46_combout )) # (!\z80_|execute_|ctl_flags_pf_we~3_combout ) - - .dataa(\z80_|execute_|ctl_flags_pf_we~3_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~46_combout ), - .datac(\z80_|execute_|ctl_flags_pf_we~5_combout ), - .datad(\z80_|execute_|ctl_flags_pf_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~8 .lut_mask = 16'hFFF7; -defparam \z80_|execute_|ctl_flags_pf_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~9_combout = ((\z80_|execute_|ctl_flags_pf_we~8_combout ) # ((!\z80_|execute_|ctl_pf_sel[0]~3_combout ) # (!\z80_|execute_|ctl_flags_pf_we~4_combout ))) # (!\z80_|execute_|ctl_flags_xy_we~11_combout ) - - .dataa(\z80_|execute_|ctl_flags_xy_we~11_combout ), - .datab(\z80_|execute_|ctl_flags_pf_we~8_combout ), - .datac(\z80_|execute_|ctl_flags_pf_we~4_combout ), - .datad(\z80_|execute_|ctl_pf_sel[0]~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~9 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_flags_pf_we~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N10 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~0 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~0_combout = (\z80_|execute_|ctl_flags_pf_we~9_combout & (\z80_|execute_|ctl_flags_bus~combout & (\z80_|alu_control_|db[2]~29_combout ))) # (!\z80_|execute_|ctl_flags_pf_we~9_combout & -// (((\z80_|alu_flags_|DFFE_inst_latch_pf~q )))) - - .dataa(\z80_|execute_|ctl_flags_bus~combout ), - .datab(\z80_|alu_control_|db[2]~29_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), - .datad(\z80_|execute_|ctl_flags_pf_we~9_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~0 .lut_mask = 16'h88F0; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N22 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~4 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~4_combout = (\z80_|execute_|ctl_pf_sel[0]~2_combout & (((!\z80_|pla_decode_|Equal62~3_combout & !\z80_|execute_|ctl_alu_op_low~13_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal62~3_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_pf_sel[0]~2_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~13_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~4 .lut_mask = 16'h3070; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N28 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~5 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~5_combout = (\z80_|execute_|ctl_pf_sel[0]~3_combout & (!\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout $ -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout )))) # (!\z80_|execute_|ctl_pf_sel[0]~3_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout $ (((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ))))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), - .datab(\z80_|execute_|ctl_pf_sel[0]~3_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~5 .lut_mask = 16'h152A; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N26 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~6 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~6_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout & (((\z80_|execute_|ctl_flags_bus~5_combout & !\z80_|pla_decode_|Equal69~0_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|pla_decode_|Equal69~0_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~6 .lut_mask = 16'h3B00; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~6 .sum_lutc_input = "datac"; +defparam \z80_|decode_state_|in_halt~0 .lut_mask = 16'h0500; +defparam \z80_|decode_state_|in_halt~0 .sum_lutc_input = "datac"; // synopsys translate_on // Location: LCCOMB_X28_Y16_N24 -cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~0 ( +cycloneive_lcell_comb \z80_|decode_state_|in_halt~1 ( // Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~0_combout = (!\z80_|address_latch_|Q [14] & (!\z80_|address_latch_|Q [12] & (!\z80_|address_latch_|Q [15] & !\z80_|address_latch_|Q [13]))) +// \z80_|decode_state_|in_halt~1_combout = (\z80_|decode_state_|in_halt~0_combout ) # ((\z80_|pla_decode_|Equal77~1_combout & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & !\z80_|decode_state_|in_halt~q ))) - .dataa(\z80_|address_latch_|Q [14]), - .datab(\z80_|address_latch_|Q [12]), - .datac(\z80_|address_latch_|Q [15]), - .datad(\z80_|address_latch_|Q [13]), + .dataa(\z80_|pla_decode_|Equal77~1_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|decode_state_|in_halt~q ), + .datad(\z80_|decode_state_|in_halt~0_combout ), .cin(gnd), - .combout(\z80_|decode_state_|DFFE_instNonRep~0_combout ), + .combout(\z80_|decode_state_|in_halt~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep~0 .lut_mask = 16'h0001; -defparam \z80_|decode_state_|DFFE_instNonRep~0 .sum_lutc_input = "datac"; +defparam \z80_|decode_state_|in_halt~1 .lut_mask = 16'hFF08; +defparam \z80_|decode_state_|in_halt~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y17_N16 -cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~3 ( -// Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~3_combout = (!\z80_|address_latch_|Q [1] & (\z80_|address_latch_|Q [0] & (!\z80_|address_latch_|Q [3] & !\z80_|address_latch_|Q [2]))) - - .dataa(\z80_|address_latch_|Q [1]), - .datab(\z80_|address_latch_|Q [0]), - .datac(\z80_|address_latch_|Q [3]), - .datad(\z80_|address_latch_|Q [2]), - .cin(gnd), - .combout(\z80_|decode_state_|DFFE_instNonRep~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep~3 .lut_mask = 16'h0004; -defparam \z80_|decode_state_|DFFE_instNonRep~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N14 -cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~2 ( -// Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~2_combout = (!\z80_|address_latch_|Q [7] & (!\z80_|address_latch_|Q [6] & (!\z80_|address_latch_|Q [5] & !\z80_|address_latch_|Q [4]))) - - .dataa(\z80_|address_latch_|Q [7]), - .datab(\z80_|address_latch_|Q [6]), - .datac(\z80_|address_latch_|Q [5]), - .datad(\z80_|address_latch_|Q [4]), - .cin(gnd), - .combout(\z80_|decode_state_|DFFE_instNonRep~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep~2 .lut_mask = 16'h0001; -defparam \z80_|decode_state_|DFFE_instNonRep~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N8 -cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~1 ( -// Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~1_combout = (!\z80_|address_latch_|Q [10] & (!\z80_|address_latch_|Q [11] & (!\z80_|address_latch_|Q [9] & !\z80_|address_latch_|Q [8]))) - - .dataa(\z80_|address_latch_|Q [10]), - .datab(\z80_|address_latch_|Q [11]), - .datac(\z80_|address_latch_|Q [9]), - .datad(\z80_|address_latch_|Q [8]), - .cin(gnd), - .combout(\z80_|decode_state_|DFFE_instNonRep~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep~1 .lut_mask = 16'h0001; -defparam \z80_|decode_state_|DFFE_instNonRep~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N18 -cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~4 ( -// Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~4_combout = (\z80_|decode_state_|DFFE_instNonRep~0_combout & (\z80_|decode_state_|DFFE_instNonRep~3_combout & (\z80_|decode_state_|DFFE_instNonRep~2_combout & \z80_|decode_state_|DFFE_instNonRep~1_combout ))) - - .dataa(\z80_|decode_state_|DFFE_instNonRep~0_combout ), - .datab(\z80_|decode_state_|DFFE_instNonRep~3_combout ), - .datac(\z80_|decode_state_|DFFE_instNonRep~2_combout ), - .datad(\z80_|decode_state_|DFFE_instNonRep~1_combout ), - .cin(gnd), - .combout(\z80_|decode_state_|DFFE_instNonRep~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep~4 .lut_mask = 16'h8000; -defparam \z80_|decode_state_|DFFE_instNonRep~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N16 -cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~5 ( -// Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~5_combout = (\z80_|execute_|ctl_flags_bus~5_combout & (((\z80_|decode_state_|DFFE_instNonRep~q )))) # (!\z80_|execute_|ctl_flags_bus~5_combout & ((\z80_|execute_|ixy_d~9_combout & -// ((\z80_|decode_state_|DFFE_instNonRep~4_combout ))) # (!\z80_|execute_|ixy_d~9_combout & (\z80_|decode_state_|DFFE_instNonRep~q )))) - - .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|decode_state_|DFFE_instNonRep~q ), - .datad(\z80_|decode_state_|DFFE_instNonRep~4_combout ), - .cin(gnd), - .combout(\z80_|decode_state_|DFFE_instNonRep~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep~5 .lut_mask = 16'hF4B0; -defparam \z80_|decode_state_|DFFE_instNonRep~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y16_N17 -dffeas \z80_|decode_state_|DFFE_instNonRep ( +// Location: FF_X28_Y16_N25 +dffeas \z80_|decode_state_|in_halt ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|decode_state_|DFFE_instNonRep~5_combout ), + .d(\z80_|decode_state_|in_halt~1_combout ), .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), @@ -33642,7153 +6250,203 @@ dffeas \z80_|decode_state_|DFFE_instNonRep ( .ena(vcc), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|decode_state_|DFFE_instNonRep~q ), + .q(\z80_|decode_state_|in_halt~q ), .prn(vcc)); // synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep .is_wysiwyg = "true"; -defparam \z80_|decode_state_|DFFE_instNonRep .power_up = "low"; +defparam \z80_|decode_state_|in_halt .is_wysiwyg = "true"; +defparam \z80_|decode_state_|in_halt .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y16_N12 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~1 ( +// Location: LCCOMB_X28_Y16_N8 +cycloneive_lcell_comb \z80_|pla_decode_|Equal50~0 ( // Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~1_combout = (!\z80_|pla_decode_|Equal62~3_combout & (\z80_|execute_|ctl_pf_sel[0]~3_combout & (\z80_|execute_|ctl_pf_sel[0]~2_combout & !\z80_|execute_|ctl_alu_op_low~13_combout ))) - - .dataa(\z80_|pla_decode_|Equal62~3_combout ), - .datab(\z80_|execute_|ctl_pf_sel[0]~3_combout ), - .datac(\z80_|execute_|ctl_pf_sel[0]~2_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~13_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~1 .lut_mask = 16'h0040; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N10 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~2 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~2_combout = (\z80_|pla_decode_|Equal69~0_combout & ((\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout & (\z80_|interrupts_|DFFE_instIFF2~q )) # (!\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout & -// ((!\z80_|decode_state_|DFFE_instNonRep~q ))))) - - .dataa(\z80_|interrupts_|DFFE_instIFF2~q ), - .datab(\z80_|decode_state_|DFFE_instNonRep~q ), - .datac(\z80_|pla_decode_|Equal69~0_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~2 .lut_mask = 16'hA030; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N24 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~3 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~3_combout = (\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_flags_bus~5_combout & (\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout )) # (!\z80_|execute_|ctl_flags_bus~5_combout & -// ((!\z80_|decode_state_|DFFE_instNonRep~q ))))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_flags_bus~5_combout ), - .datad(\z80_|decode_state_|DFFE_instNonRep~q ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~3 .lut_mask = 16'h808C; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y10_N23 -dffeas \z80_|alu_control_|DFFE_latch_pf_tmp ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|alu_parity_out~combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_alu_op_low~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_control_|DFFE_latch_pf_tmp~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_control_|DFFE_latch_pf_tmp .is_wysiwyg = "true"; -defparam \z80_|alu_control_|DFFE_latch_pf_tmp .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N16 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ) # -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout )))) # (!\z80_|execute_|ctl_alu_core_R~5_combout ) - - .dataa(\z80_|execute_|ctl_alu_core_R~5_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 .lut_mask = 16'h55FD; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N22 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout = (\z80_|alu_|alu_op2[1]~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout & -// \z80_|alu_|alu_op1[1]~0_combout )))) # (!\z80_|alu_|alu_op2[1]~1_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_|alu_op1[1]~0_combout ) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout )))) - - .dataa(\z80_|alu_|alu_op2[1]~1_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), - .datac(\z80_|alu_|alu_op1[1]~0_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 .lut_mask = 16'hFB20; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N28 -cycloneive_lcell_comb \z80_|alu_|alu_parity_out~0 ( -// Equation(s): -// \z80_|alu_|alu_parity_out~0_combout = \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout $ (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout $ (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout )) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), - .datab(gnd), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_parity_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_parity_out~0 .lut_mask = 16'hA55A; -defparam \z80_|alu_|alu_parity_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N22 -cycloneive_lcell_comb \z80_|alu_|alu_parity_out ( -// Equation(s): -// \z80_|alu_|alu_parity_out~combout = \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout $ (\z80_|alu_|alu_parity_out~0_combout $ (((\z80_|execute_|ctl_alu_op_low~combout ) # (\z80_|alu_control_|DFFE_latch_pf_tmp~q )))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~combout ), - .datac(\z80_|alu_control_|DFFE_latch_pf_tmp~q ), - .datad(\z80_|alu_|alu_parity_out~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_parity_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_parity_out .lut_mask = 16'hA956; -defparam \z80_|alu_|alu_parity_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N20 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~7 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~7_combout = (\z80_|pla_decode_|Equal62~3_combout ) # ((\z80_|pla_decode_|Equal69~0_combout ) # ((\z80_|execute_|ctl_alu_op_low~13_combout ) # (!\z80_|execute_|ctl_flags_bus~5_combout ))) - - .dataa(\z80_|pla_decode_|Equal62~3_combout ), - .datab(\z80_|pla_decode_|Equal69~0_combout ), - .datac(\z80_|execute_|ctl_flags_bus~5_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~13_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~7 .lut_mask = 16'hFFEF; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N2 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~8 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~8_combout = (\z80_|execute_|ctl_pf_sel[0]~2_combout & (\z80_|execute_|ctl_pf_sel[0]~3_combout & ((!\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ) # (!\z80_|nM1_int~2_combout )))) - - .dataa(\z80_|execute_|ctl_pf_sel[0]~2_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_pf_sel[0]~3_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~8 .lut_mask = 16'h20A0; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N4 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~9 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~9_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ) # ((\z80_|alu_|alu_parity_out~combout & \z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ), - .datac(\z80_|alu_|alu_parity_out~combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~9 .lut_mask = 16'hFEEE; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N14 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~10 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~10_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ) # ((\z80_|execute_|ctl_flags_pf_we~9_combout & (\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout & \z80_|execute_|ctl_flags_alu~15_combout ))) - - .dataa(\z80_|execute_|ctl_flags_pf_we~9_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ), - .datad(\z80_|execute_|ctl_flags_alu~15_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~10 .lut_mask = 16'hECCC; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y11_N15 -dffeas \z80_|alu_flags_|DFFE_inst_latch_pf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|DFFE_inst_latch_pf~10_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N14 -cycloneive_lcell_comb \z80_|alu_control_|sel[1]~0 ( -// Equation(s): -// \z80_|alu_control_|sel[1]~0_combout = (\z80_|ir_|opcode [5] & (((!\z80_|pla_decode_|Equal40~0_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal40~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|sel[1]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|sel[1]~0 .lut_mask = 16'h70F0; -defparam \z80_|alu_control_|sel[1]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N18 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout = (!\z80_|alu_|db_high[1]~20_combout & (!\z80_|alu_|db_high[3]~8_combout & (!\z80_|alu_|db_high[2]~14_combout & !\z80_|alu_|db_high[0]~26_combout ))) - - .dataa(\z80_|alu_|db_high[1]~20_combout ), - .datab(\z80_|alu_|db_high[3]~8_combout ), - .datac(\z80_|alu_|db_high[2]~14_combout ), - .datad(\z80_|alu_|db_high[0]~26_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2 .lut_mask = 16'h0001; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N4 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_12 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout = (\z80_|alu_control_|db[6]~22_combout & \z80_|execute_|ctl_flags_bus~combout ) - - .dataa(\z80_|alu_control_|db[6]~22_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|execute_|ctl_flags_bus~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_12 .lut_mask = 16'hAA00; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N14 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout = (!\z80_|alu_|db_low[3]~11_combout & (\z80_|alu_|db_high[3]~3_combout & ((!\z80_|alu_|db_low[2]~3_combout ) # (!\z80_|alu_|db_low[2]~6_combout )))) - - .dataa(\z80_|alu_|db_low[2]~6_combout ), - .datab(\z80_|alu_|db_low[3]~11_combout ), - .datac(\z80_|alu_|db_low[2]~3_combout ), - .datad(\z80_|alu_|db_high[3]~3_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 .lut_mask = 16'h1300; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N8 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout = (!\z80_|alu_|db_low[1]~17_combout & (\z80_|execute_|ctl_flags_alu~15_combout & (!\z80_|alu_|db_low[0]~23_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ))) - - .dataa(\z80_|alu_|db_low[1]~17_combout ), - .datab(\z80_|execute_|ctl_flags_alu~15_combout ), - .datac(\z80_|alu_|db_low[0]~23_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 .lut_mask = 16'h0400; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N2 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout = (((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ) # (!\z80_|execute_|ixy_d~7_combout )) # (!\z80_|pla_decode_|Equal13~0_combout )) # (!\z80_|pla_decode_|Equal55~0_combout ) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 .lut_mask = 16'hF7FF; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N26 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout & ((\z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout )))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 .lut_mask = 16'hEC00; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y13_N27 -dffeas \z80_|alu_flags_|SYNTHESIZED_WIRE_39 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_flags_sz_we~8_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_39 .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_39 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N28 -cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_cond_mux|out~0 ( -// Equation(s): -// \z80_|alu_control_|b2v_inst_cond_mux|out~0_combout = (\z80_|alu_control_|sel[1]~0_combout & (((\z80_|ir_|opcode [4])))) # (!\z80_|alu_control_|sel[1]~0_combout & ((\z80_|ir_|opcode [4] & ((\z80_|alu_flags_|flags_cf~combout ))) # (!\z80_|ir_|opcode [4] -// & (\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q )))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .datab(\z80_|alu_flags_|flags_cf~combout ), - .datac(\z80_|alu_control_|sel[1]~0_combout ), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|b2v_inst_cond_mux|out~0 .lut_mask = 16'hFC0A; -defparam \z80_|alu_control_|b2v_inst_cond_mux|out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N18 -cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_cond_mux|out~1 ( -// Equation(s): -// \z80_|alu_control_|b2v_inst_cond_mux|out~1_combout = (\z80_|alu_control_|sel[1]~0_combout & ((\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout & (\z80_|alu_flags_|DFFE_inst_latch_sf~q )) # (!\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout & -// ((\z80_|alu_flags_|DFFE_inst_latch_pf~q ))))) # (!\z80_|alu_control_|sel[1]~0_combout & (((\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout )))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), - .datac(\z80_|alu_control_|sel[1]~0_combout ), - .datad(\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|b2v_inst_cond_mux|out~1 .lut_mask = 16'hAFC0; -defparam \z80_|alu_control_|b2v_inst_cond_mux|out~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N20 -cycloneive_lcell_comb \z80_|alu_control_|flags_cond_true~0 ( -// Equation(s): -// \z80_|alu_control_|flags_cond_true~0_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|ir_|opcode [3] $ (((!\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ))))) # (!\z80_|execute_|ctl_eval_cond~0_combout & -// (((\z80_|alu_control_|flags_cond_true~q )))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|alu_control_|flags_cond_true~q ), - .datad(\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|flags_cond_true~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|flags_cond_true~0 .lut_mask = 16'hB874; -defparam \z80_|alu_control_|flags_cond_true~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y11_N21 -dffeas \z80_|alu_control_|flags_cond_true ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_control_|flags_cond_true~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_control_|flags_cond_true~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_control_|flags_cond_true .is_wysiwyg = "true"; -defparam \z80_|alu_control_|flags_cond_true .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~13 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~13_combout = (((!\z80_|pla_decode_|Equal35~0_combout & !\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|execute_|ixy_d~6_combout )) # (!\z80_|alu_control_|flags_cond_true~q ) - - .dataa(\z80_|pla_decode_|Equal35~0_combout ), - .datab(\z80_|alu_control_|flags_cond_true~q ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|pla_decode_|Equal34~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~13 .lut_mask = 16'h3F7F; -defparam \z80_|execute_|ctl_reg_sel_wz~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~14 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~14_combout = (((\z80_|execute_|ctl_66_oe~2_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~13_combout )) # (!\z80_|execute_|ctl_reg_in_hi~5_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~12_combout ) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~12_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~5_combout ), - .datac(\z80_|execute_|ctl_66_oe~2_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~14 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|ctl_reg_sel_wz~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~17 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~17_combout = (\z80_|execute_|ctl_reg_sel_wz~14_combout ) # (((!\z80_|execute_|ctl_reg_sel_wz~16_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~19_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~11_combout )) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~14_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~11_combout ), - .datac(\z80_|execute_|ctl_reg_sel_wz~19_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~17 .lut_mask = 16'hBFFF; -defparam \z80_|execute_|ctl_reg_sel_wz~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N16 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_82 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_82~combout = (\z80_|execute_|ctl_reg_sel_wz~17_combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout & !\z80_|reg_control_|reg_sys_we_lo~combout )) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~17_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .datac(gnd), - .datad(\z80_|reg_control_|reg_sys_we_lo~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_82 .lut_mask = 16'h0088; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~18 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~18_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~18 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp0[0]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y12_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~20 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~20_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ) # ((\z80_|reg_file_|gdfx_temp0[0]~19_combout ) # ((\z80_|reg_file_|gdfx_temp0[0]~18_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~19_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[0]~18_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~20 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp0[0]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~21 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~21_combout = (\z80_|reg_file_|gdfx_temp0[0]~93_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ) # ((\z80_|reg_file_|gdfx_temp0[0]~20_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[0]~93_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .datac(\z80_|reg_file_|gdfx_temp0[0]~20_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~21 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp0[0]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y10_N23 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X31_Y10_N27 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~28 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~28_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datab(\z80_|reg_file_|b2v_latch_iy_lo|latch [1]), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~28 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp0[1]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y10_N25 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y11_N13 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y12_N25 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~26 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~26_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [1]), - .datad(\z80_|reg_file_|b2v_latch_bc_lo|latch [1]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~26 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[1]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~27 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~27_combout = (\z80_|reg_file_|gdfx_temp0[1]~26_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) +// \z80_|pla_decode_|Equal50~0_combout = (!\z80_|decode_state_|in_halt~q & (\z80_|pla_decode_|Equal33~1_combout & \z80_|pla_decode_|Equal77~0_combout )) .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [1]), - .datad(\z80_|reg_file_|gdfx_temp0[1]~26_combout ), + .datab(\z80_|decode_state_|in_halt~q ), + .datac(\z80_|pla_decode_|Equal33~1_combout ), + .datad(\z80_|pla_decode_|Equal77~0_combout ), .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~27_combout ), + .combout(\z80_|pla_decode_|Equal50~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~27 .lut_mask = 16'hF300; -defparam \z80_|reg_file_|gdfx_temp0[1]~27 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal50~0 .lut_mask = 16'h3000; +defparam \z80_|pla_decode_|Equal50~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y10_N17 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~29 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~29_combout = (\z80_|reg_file_|b2v_latch_sp_lo|latch [1] & (((\z80_|alu_control_|db[1]~26_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) # (!\z80_|reg_file_|b2v_latch_sp_lo|latch [1] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|alu_control_|db[1]~26_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_sp_lo|latch [1]), - .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datac(\z80_|alu_control_|db[1]~26_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~29 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[1]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N3 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N8 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout = \z80_|reg_file_|gdfx_temp0[1]~32_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N9 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~25 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~25_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [1]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [1]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~25 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[1]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~30 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~30_combout = (\z80_|reg_file_|gdfx_temp0[1]~28_combout & (\z80_|reg_file_|gdfx_temp0[1]~27_combout & (\z80_|reg_file_|gdfx_temp0[1]~29_combout & \z80_|reg_file_|gdfx_temp0[1]~25_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[1]~28_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[1]~27_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[1]~29_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[1]~25_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~30 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[1]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N26 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder_combout = \z80_|reg_file_|gdfx_temp0[1]~32_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y9_N27 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y9_N25 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~24 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~24_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [1] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [1] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [1]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~24 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[1]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y13_N23 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y13_N25 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~23 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~23_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [1] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [1] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [1]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~23 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[1]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~31 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~31_combout = (\z80_|reg_file_|gdfx_temp0[1]~30_combout & (\z80_|reg_file_|gdfx_temp0[1]~24_combout & \z80_|reg_file_|gdfx_temp0[1]~23_combout )) - - .dataa(\z80_|reg_file_|gdfx_temp0[1]~30_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[1]~24_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[1]~23_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~31 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|gdfx_temp0[1]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~32 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~32_combout = ((\z80_|reg_file_|gdfx_temp0[1]~31_combout & ((\z80_|reg_file_|db_lo_as[1]~6_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .datac(\z80_|reg_file_|db_lo_as[1]~6_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[1]~31_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~32 .lut_mask = 16'hF733; -defparam \z80_|reg_file_|gdfx_temp0[1]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N12 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[1]~1 ( -// Equation(s): -// \z80_|reg_file_|db_lo_ds[1]~1_combout = (\z80_|reg_file_|gdfx_temp0[1]~32_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout & (\z80_|execute_|ctl_reg_out_lo~7_combout & !\z80_|execute_|ctl_reg_out_lo~5_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), - .datab(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .datad(\z80_|execute_|ctl_reg_out_lo~5_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_ds[1]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_ds[1]~1 .lut_mask = 16'hF0F8; -defparam \z80_|reg_file_|db_lo_ds[1]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N30 -cycloneive_lcell_comb \z80_|alu_control_|db[1]~25 ( -// Equation(s): -// \z80_|alu_control_|db[1]~25_combout = (\z80_|reg_file_|db_lo_ds[1]~1_combout & (((\z80_|bus_control_|db[1]~11_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) - - .dataa(\z80_|bus_control_|db[1]~11_combout ), - .datab(\z80_|reg_file_|db_lo_ds[1]~1_combout ), - .datac(\z80_|execute_|ctl_sw_1d~7_combout ), - .datad(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[1]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[1]~25 .lut_mask = 16'h0C8C; -defparam \z80_|alu_control_|db[1]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N28 -cycloneive_lcell_comb \z80_|alu_control_|db[1]~24 ( -// Equation(s): -// \z80_|alu_control_|db[1]~24_combout = (\z80_|execute_|ctl_flags_oe~2_combout & (((\z80_|execute_|ctl_sw_2u~7_combout & !\z80_|alu_|db[1]~13_combout )) # (!\z80_|alu_flags_|DFFE_inst_latch_nf~q ))) # (!\z80_|execute_|ctl_flags_oe~2_combout & -// (\z80_|execute_|ctl_sw_2u~7_combout & ((!\z80_|alu_|db[1]~13_combout )))) - - .dataa(\z80_|execute_|ctl_flags_oe~2_combout ), - .datab(\z80_|execute_|ctl_sw_2u~7_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .datad(\z80_|alu_|db[1]~13_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[1]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[1]~24 .lut_mask = 16'h0ACE; -defparam \z80_|alu_control_|db[1]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N20 -cycloneive_lcell_comb \z80_|alu_control_|db[1]~26 ( -// Equation(s): -// \z80_|alu_control_|db[1]~26_combout = ((\z80_|alu_control_|db[1]~25_combout & (\z80_|alu_control_|db[2]~23_combout & !\z80_|alu_control_|db[1]~24_combout ))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|alu_control_|db[1]~25_combout ), - .datab(\z80_|alu_control_|db[2]~23_combout ), - .datac(\z80_|alu_control_|db[6]~11_combout ), - .datad(\z80_|alu_control_|db[1]~24_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[1]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[1]~26 .lut_mask = 16'h0F8F; -defparam \z80_|alu_control_|db[1]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N22 -cycloneive_lcell_comb \z80_|alu_|db[1]~12 ( -// Equation(s): -// \z80_|alu_|db[1]~12_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[1]~21_combout & ((\z80_|alu_control_|db[1]~26_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & -// ((\z80_|alu_control_|db[1]~26_combout ) # ((!\z80_|execute_|ctl_sw_2d~13_combout )))) - - .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datab(\z80_|alu_control_|db[1]~26_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .datad(\z80_|execute_|ctl_sw_2d~13_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[1]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[1]~12 .lut_mask = 16'hC4F5; -defparam \z80_|alu_|db[1]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N8 -cycloneive_lcell_comb \z80_|alu_|db[1]~13 ( -// Equation(s): -// \z80_|alu_|db[1]~13_combout = ((\z80_|alu_|db[1]~12_combout & ((\z80_|alu_|db_low[1]~17_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~26_combout ) - - .dataa(\z80_|alu_|db[1]~12_combout ), - .datab(\z80_|execute_|ctl_alu_oe~14_combout ), - .datac(\z80_|alu_|db_low[1]~17_combout ), - .datad(\z80_|alu_|db[7]~26_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[1]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[1]~13 .lut_mask = 16'hA2FF; -defparam \z80_|alu_|db[1]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N18 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~21 ( -// Equation(s): -// \z80_|alu_|db_low[0]~21_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[1]~13_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(gnd), - .datac(\z80_|alu_|db[1]~13_combout ), - .datad(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~21 .lut_mask = 16'hF5A0; -defparam \z80_|alu_|db_low[0]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N0 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~22 ( -// Equation(s): -// \z80_|alu_|db_low[0]~22_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_low[0]~21_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[0]~19_combout ))) - - .dataa(gnd), - .datab(\z80_|alu_|db_low[0]~21_combout ), - .datac(\z80_|alu_|db[0]~19_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~22 .lut_mask = 16'hCCF0; -defparam \z80_|alu_|db_low[0]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N16 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~18 ( -// Equation(s): -// \z80_|alu_|db_low[0]~18_combout = ((!\z80_|bus_control_|db[4]~19_combout & (!\z80_|bus_control_|db[5]~15_combout & !\z80_|bus_control_|db[3]~21_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datab(\z80_|bus_control_|db[4]~19_combout ), - .datac(\z80_|bus_control_|db[5]~15_combout ), - .datad(\z80_|bus_control_|db[3]~21_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~18 .lut_mask = 16'h5557; -defparam \z80_|alu_|db_low[0]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N20 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~19 ( -// Equation(s): -// \z80_|alu_|db_low[0]~19_combout = (\z80_|alu_|op2_low [0] & (((\z80_|alu_|op1_low [0])) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout ))) # (!\z80_|alu_|op2_low [0] & (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_low [0]) # -// (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) - - .dataa(\z80_|alu_|op2_low [0]), - .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datac(\z80_|alu_|op1_low [0]), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~19 .lut_mask = 16'hA2F3; -defparam \z80_|alu_|db_low[0]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y10_N25 -dffeas \z80_|alu_|result_lo[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_alu_op_low~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|result_lo [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|result_lo[0] .is_wysiwyg = "true"; -defparam \z80_|alu_|result_lo[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N24 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~20 ( -// Equation(s): -// \z80_|alu_|db_low[0]~20_combout = (\z80_|alu_|db_low[0]~18_combout & (\z80_|alu_|db_low[0]~19_combout & ((\z80_|alu_|result_lo [0]) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) - - .dataa(\z80_|alu_|db_low[0]~18_combout ), - .datab(\z80_|alu_|db_low[0]~19_combout ), - .datac(\z80_|alu_|result_lo [0]), - .datad(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~20 .lut_mask = 16'h8880; -defparam \z80_|alu_|db_low[0]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N22 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~23 ( -// Equation(s): -// \z80_|alu_|db_low[0]~23_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout & (\z80_|alu_|db_low[0]~22_combout & ((\z80_|alu_|db_low[0]~20_combout )))) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout & (((\z80_|alu_|db_low[0]~20_combout ) # -// (!\z80_|alu_|db_high[3]~2_combout )))) - - .dataa(\z80_|alu_|db_low[0]~22_combout ), - .datab(\z80_|alu_|db_high[3]~2_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datad(\z80_|alu_|db_low[0]~20_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~23 .lut_mask = 16'hAF03; -defparam \z80_|alu_|db_low[0]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N10 -cycloneive_lcell_comb \z80_|alu_|db[0]~18 ( -// Equation(s): -// \z80_|alu_|db[0]~18_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[0]~30_combout & ((\z80_|alu_|db_low[0]~23_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & -// ((\z80_|alu_|db_low[0]~23_combout ) # ((!\z80_|execute_|ctl_alu_oe~14_combout )))) - - .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datab(\z80_|alu_|db_low[0]~23_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .datad(\z80_|execute_|ctl_alu_oe~14_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[0]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[0]~18 .lut_mask = 16'hC4F5; -defparam \z80_|alu_|db[0]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N16 -cycloneive_lcell_comb \z80_|alu_|db[0]~19 ( -// Equation(s): -// \z80_|alu_|db[0]~19_combout = ((\z80_|alu_|db[0]~18_combout & ((\z80_|alu_control_|db[0]~12_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|alu_|db[7]~26_combout ) - - .dataa(\z80_|alu_|db[0]~18_combout ), - .datab(\z80_|execute_|ctl_sw_2d~13_combout ), - .datac(\z80_|alu_control_|db[0]~12_combout ), - .datad(\z80_|alu_|db[7]~26_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[0]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[0]~19 .lut_mask = 16'hA2FF; -defparam \z80_|alu_|db[0]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N30 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~15 ( -// Equation(s): -// \z80_|alu_|db_low[1]~15_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[2]~15_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[0]~19_combout )) - - .dataa(\z80_|alu_|db[0]~19_combout ), - .datab(gnd), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|alu_|db[2]~15_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~15 .lut_mask = 16'hFA0A; -defparam \z80_|alu_|db_low[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N16 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~16 ( -// Equation(s): -// \z80_|alu_|db_low[1]~16_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_low[1]~15_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[1]~13_combout ))) - - .dataa(\z80_|alu_|db_low[1]~15_combout ), - .datab(gnd), - .datac(\z80_|alu_|db[1]~13_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~16 .lut_mask = 16'hAAF0; -defparam \z80_|alu_|db_low[1]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N6 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~12 ( -// Equation(s): -// \z80_|alu_|db_low[1]~12_combout = ((!\z80_|bus_control_|db[4]~19_combout & (!\z80_|bus_control_|db[5]~15_combout & \z80_|bus_control_|db[3]~21_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datab(\z80_|bus_control_|db[4]~19_combout ), - .datac(\z80_|bus_control_|db[5]~15_combout ), - .datad(\z80_|bus_control_|db[3]~21_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~12 .lut_mask = 16'h5755; -defparam \z80_|alu_|db_low[1]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N18 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~13 ( -// Equation(s): -// \z80_|alu_|db_low[1]~13_combout = (\z80_|alu_|op2_low [1] & (((\z80_|alu_|op1_low [1])) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout ))) # (!\z80_|alu_|op2_low [1] & (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_low [1]) # -// (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) - - .dataa(\z80_|alu_|op2_low [1]), - .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datac(\z80_|alu_|op1_low [1]), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~13 .lut_mask = 16'hA2F3; -defparam \z80_|alu_|db_low[1]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y10_N21 -dffeas \z80_|alu_|result_lo[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_alu_op_low~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|result_lo [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|result_lo[1] .is_wysiwyg = "true"; -defparam \z80_|alu_|result_lo[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N20 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~14 ( -// Equation(s): -// \z80_|alu_|db_low[1]~14_combout = (\z80_|alu_|db_low[1]~12_combout & (\z80_|alu_|db_low[1]~13_combout & ((\z80_|alu_|result_lo [1]) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) - - .dataa(\z80_|alu_|db_low[1]~12_combout ), - .datab(\z80_|alu_|db_low[1]~13_combout ), - .datac(\z80_|alu_|result_lo [1]), - .datad(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~14 .lut_mask = 16'h8880; -defparam \z80_|alu_|db_low[1]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N18 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~17 ( -// Equation(s): -// \z80_|alu_|db_low[1]~17_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout & (((\z80_|alu_|db_low[1]~16_combout & \z80_|alu_|db_low[1]~14_combout )))) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout & (((\z80_|alu_|db_low[1]~14_combout )) # -// (!\z80_|alu_|db_high[3]~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datab(\z80_|alu_|db_high[3]~2_combout ), - .datac(\z80_|alu_|db_low[1]~16_combout ), - .datad(\z80_|alu_|db_low[1]~14_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~17 .lut_mask = 16'hF511; -defparam \z80_|alu_|db_low[1]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N26 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout = (\z80_|alu_|db_low[1]~17_combout & ((\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ) # ((\z80_|alu_|db_high[1]~20_combout & \z80_|execute_|ctl_alu_op1_sel_low~combout )))) # -// (!\z80_|alu_|db_low[1]~17_combout & (((\z80_|alu_|db_high[1]~20_combout & \z80_|execute_|ctl_alu_op1_sel_low~combout )))) - - .dataa(\z80_|alu_|db_low[1]~17_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .datac(\z80_|alu_|db_high[1]~20_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 .lut_mask = 16'hF888; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N0 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6_combout = (\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6 .lut_mask = 16'h00F0; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y10_N1 -dffeas \z80_|alu_|op1_low[1] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_low [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_low[1] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_low[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N28 -cycloneive_lcell_comb \z80_|alu_control_|out[6]~0 ( -// Equation(s): -// \z80_|alu_control_|out[6]~0_combout = (\z80_|alu_|op1_low [3] & ((\z80_|alu_|op1_low [1]) # (\z80_|alu_|op1_low [2]))) - - .dataa(gnd), - .datab(\z80_|alu_|op1_low [1]), - .datac(\z80_|alu_|op1_low [3]), - .datad(\z80_|alu_|op1_low [2]), - .cin(gnd), - .combout(\z80_|alu_control_|out[6]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|out[6]~0 .lut_mask = 16'hF0C0; -defparam \z80_|alu_control_|out[6]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N18 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~2 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf~2_combout = (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & \z80_|execute_|ctl_flags_alu~15_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), - .datad(\z80_|execute_|ctl_flags_alu~15_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~2 .lut_mask = 16'h0F00; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N8 -cycloneive_lcell_comb \z80_|alu_flags_|flags_hf2~0 ( -// Equation(s): -// \z80_|alu_flags_|flags_hf2~0_combout = (\z80_|execute_|ctl_flags_hf2_we~combout & ((\z80_|alu_control_|db[4]~32_combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout )))) # (!\z80_|execute_|ctl_flags_hf2_we~combout & -// (((\z80_|alu_flags_|flags_hf2~q )))) - - .dataa(\z80_|alu_control_|db[4]~32_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ), - .datac(\z80_|alu_flags_|flags_hf2~q ), - .datad(\z80_|execute_|ctl_flags_hf2_we~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|flags_hf2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_hf2~0 .lut_mask = 16'hEEF0; -defparam \z80_|alu_flags_|flags_hf2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y11_N9 -dffeas \z80_|alu_flags_|flags_hf2 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|flags_hf2~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|flags_hf2~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_hf2 .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|flags_hf2 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N12 -cycloneive_lcell_comb \z80_|alu_control_|db[2]~23 ( -// Equation(s): -// \z80_|alu_control_|db[2]~23_combout = (\z80_|execute_|ctl_66_oe~combout ) # ((\z80_|alu_control_|out[6]~0_combout ) # ((\z80_|alu_flags_|flags_hf2~q ) # (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout ))) - - .dataa(\z80_|execute_|ctl_66_oe~combout ), - .datab(\z80_|alu_control_|out[6]~0_combout ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datad(\z80_|alu_flags_|flags_hf2~q ), - .cin(gnd), - .combout(\z80_|alu_control_|db[2]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[2]~23 .lut_mask = 16'hFFEF; -defparam \z80_|alu_control_|db[2]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N26 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[2]~2 ( -// Equation(s): -// \z80_|reg_file_|db_lo_ds[2]~2_combout = (\z80_|reg_file_|gdfx_temp0[2]~42_combout ) # ((!\z80_|execute_|ctl_reg_out_lo~5_combout & (\z80_|execute_|ctl_reg_out_lo~7_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ))) - - .dataa(\z80_|execute_|ctl_reg_out_lo~5_combout ), - .datab(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_ds[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_ds[2]~2 .lut_mask = 16'hFF40; -defparam \z80_|reg_file_|db_lo_ds[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N16 -cycloneive_lcell_comb \z80_|alu_control_|db[2]~28 ( -// Equation(s): -// \z80_|alu_control_|db[2]~28_combout = (\z80_|reg_file_|db_lo_ds[2]~2_combout & (((\z80_|bus_control_|db[2]~13_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) - - .dataa(\z80_|bus_control_|db[2]~13_combout ), - .datab(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .datac(\z80_|execute_|ctl_sw_1d~7_combout ), - .datad(\z80_|reg_file_|db_lo_ds[2]~2_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[2]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[2]~28 .lut_mask = 16'h2F00; -defparam \z80_|alu_control_|db[2]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N28 -cycloneive_lcell_comb \z80_|alu_control_|db[2]~27 ( -// Equation(s): -// \z80_|alu_control_|db[2]~27_combout = (\z80_|execute_|ctl_flags_oe~2_combout & (((!\z80_|alu_|db[2]~15_combout & \z80_|execute_|ctl_sw_2u~7_combout )) # (!\z80_|alu_flags_|DFFE_inst_latch_pf~q ))) # (!\z80_|execute_|ctl_flags_oe~2_combout & -// (!\z80_|alu_|db[2]~15_combout & ((\z80_|execute_|ctl_sw_2u~7_combout )))) - - .dataa(\z80_|execute_|ctl_flags_oe~2_combout ), - .datab(\z80_|alu_|db[2]~15_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), - .datad(\z80_|execute_|ctl_sw_2u~7_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[2]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[2]~27 .lut_mask = 16'h3B0A; -defparam \z80_|alu_control_|db[2]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N22 -cycloneive_lcell_comb \z80_|alu_control_|db[2]~29 ( -// Equation(s): -// \z80_|alu_control_|db[2]~29_combout = ((\z80_|alu_control_|db[2]~23_combout & (\z80_|alu_control_|db[2]~28_combout & !\z80_|alu_control_|db[2]~27_combout ))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|alu_control_|db[6]~11_combout ), - .datab(\z80_|alu_control_|db[2]~23_combout ), - .datac(\z80_|alu_control_|db[2]~28_combout ), - .datad(\z80_|alu_control_|db[2]~27_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[2]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[2]~29 .lut_mask = 16'h55D5; -defparam \z80_|alu_control_|db[2]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N30 -cycloneive_lcell_comb \z80_|alu_|db[2]~14 ( -// Equation(s): -// \z80_|alu_|db[2]~14_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[2]~39_combout & ((\z80_|alu_control_|db[2]~29_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & -// (((\z80_|alu_control_|db[2]~29_combout )) # (!\z80_|execute_|ctl_sw_2d~13_combout ))) - - .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datab(\z80_|execute_|ctl_sw_2d~13_combout ), - .datac(\z80_|alu_control_|db[2]~29_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[2]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[2]~14 .lut_mask = 16'hF351; -defparam \z80_|alu_|db[2]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N4 -cycloneive_lcell_comb \z80_|alu_|db[2]~15 ( -// Equation(s): -// \z80_|alu_|db[2]~15_combout = ((\z80_|alu_|db[2]~14_combout & ((\z80_|alu_|db_low[2]~24_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~26_combout ) - - .dataa(\z80_|alu_|db_low[2]~24_combout ), - .datab(\z80_|execute_|ctl_alu_oe~14_combout ), - .datac(\z80_|alu_|db[2]~14_combout ), - .datad(\z80_|alu_|db[7]~26_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[2]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[2]~15 .lut_mask = 16'hB0FF; -defparam \z80_|alu_|db[2]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N4 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~2 ( -// Equation(s): -// \z80_|alu_|db_low[2]~2_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[3]~11_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[1]~13_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|alu_|db[3]~11_combout ), - .datac(\z80_|alu_|db[1]~13_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~2 .lut_mask = 16'hD8D8; -defparam \z80_|alu_|db_low[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N8 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~3 ( -// Equation(s): -// \z80_|alu_|db_low[2]~3_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_low[2]~2_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[2]~15_combout ))) # -// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) - - .dataa(\z80_|alu_|db[2]~15_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datac(\z80_|alu_|db_low[2]~2_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~3 .lut_mask = 16'hF3BB; -defparam \z80_|alu_|db_low[2]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N18 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & (((\z80_|alu_|db_low[2]~6_combout & \z80_|alu_|db_low[2]~3_combout )) # (!\z80_|alu_|db_high[3]~3_combout ))) - - .dataa(\z80_|alu_|db_low[2]~6_combout ), - .datab(\z80_|alu_|db_high[3]~3_combout ), - .datac(\z80_|alu_|db_low[2]~3_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2 .lut_mask = 16'hB300; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N24 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & ((\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout ) # ((\z80_|alu_|db_high[2]~14_combout & \z80_|execute_|ctl_alu_op1_sel_low~combout )))) - - .dataa(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .datac(\z80_|alu_|db_high[2]~14_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 .lut_mask = 16'h3222; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y10_N25 -dffeas \z80_|alu_|op1_low[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_low [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_low[2] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_low[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N24 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [2]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [2])))) - - .dataa(\z80_|alu_|op1_high [2]), - .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datac(\z80_|execute_|ctl_alu_op_low~combout ), - .datad(\z80_|alu_|op1_low [2]), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0 .lut_mask = 16'hC808; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N12 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0_combout ) # ((\z80_|alu_|db_low[2]~24_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datab(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0_combout ), - .datac(\z80_|alu_|db_low[2]~24_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1 .lut_mask = 16'h5444; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y10_N13 -dffeas \z80_|alu_|op2_low[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_low [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_low[2] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_low[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N30 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~5 ( -// Equation(s): -// \z80_|alu_|db_low[2]~5_combout = (\z80_|alu_|op2_low [2] & ((\z80_|alu_|op1_low [2]) # ((!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) # (!\z80_|alu_|op2_low [2] & (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_low [2]) # -// (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) - - .dataa(\z80_|alu_|op2_low [2]), - .datab(\z80_|alu_|op1_low [2]), - .datac(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~5 .lut_mask = 16'h8ACF; -defparam \z80_|alu_|db_low[2]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y10_N13 -dffeas \z80_|alu_|result_lo[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_alu_op_low~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|result_lo [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|result_lo[2] .is_wysiwyg = "true"; -defparam \z80_|alu_|result_lo[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N30 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~6 ( -// Equation(s): -// \z80_|alu_|db_low[2]~6_combout = (\z80_|alu_|db_low[2]~4_combout & (\z80_|alu_|db_low[2]~5_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|result_lo [2])))) - - .dataa(\z80_|alu_|db_low[2]~4_combout ), - .datab(\z80_|alu_|db_low[2]~5_combout ), - .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datad(\z80_|alu_|result_lo [2]), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~6 .lut_mask = 16'h8880; -defparam \z80_|alu_|db_low[2]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N24 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & (((\z80_|alu_|db_low[2]~6_combout & \z80_|alu_|db_low[2]~3_combout )) # (!\z80_|alu_|db_high[3]~3_combout ))) - - .dataa(\z80_|alu_|db_low[2]~6_combout ), - .datab(\z80_|alu_|db_low[2]~3_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datad(\z80_|alu_|db_high[3]~3_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 .lut_mask = 16'h80F0; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N26 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ) # ((\z80_|alu_|db_high[2]~14_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datab(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ), - .datac(\z80_|alu_|db_high[2]~14_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4 .lut_mask = 16'h5444; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y10_N27 -dffeas \z80_|alu_|op2_high[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_high [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_high[2] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_high[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N14 -cycloneive_lcell_comb \z80_|alu_|alu_op2[2]~0 ( -// Equation(s): -// \z80_|alu_|alu_op2[2]~0_combout = \z80_|execute_|ctl_alu_sel_op2_neg~18_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_high [2])) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_low [2]))))) - - .dataa(\z80_|alu_|op2_high [2]), - .datab(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), - .datad(\z80_|alu_|op2_low [2]), - .cin(gnd), - .combout(\z80_|alu_|alu_op2[2]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op2[2]~0 .lut_mask = 16'h4B78; -defparam \z80_|alu_|alu_op2[2]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N0 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ) # -// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) # (!\z80_|execute_|ctl_alu_core_R~5_combout ) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), - .datad(\z80_|execute_|ctl_alu_core_R~5_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 .lut_mask = 16'h0BFF; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N12 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout = (\z80_|alu_|alu_op2[2]~0_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ) # ((\z80_|alu_|alu_op1[2]~2_combout & -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) # (!\z80_|alu_|alu_op2[2]~0_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_|alu_op1[2]~2_combout ) # -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) - - .dataa(\z80_|alu_|alu_op2[2]~0_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ), - .datac(\z80_|alu_|alu_op1[2]~2_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 .lut_mask = 16'hECC8; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N26 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~9 ( -// Equation(s): -// \z80_|alu_|db_high[2]~9_combout = ((\z80_|bus_control_|db[4]~19_combout & (\z80_|bus_control_|db[5]~15_combout & !\z80_|bus_control_|db[3]~21_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datab(\z80_|bus_control_|db[4]~19_combout ), - .datac(\z80_|bus_control_|db[5]~15_combout ), - .datad(\z80_|bus_control_|db[3]~21_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~9 .lut_mask = 16'h55D5; -defparam \z80_|alu_|db_high[2]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N24 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~11 ( -// Equation(s): -// \z80_|alu_|db_high[2]~11_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[7]~21_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[5]~25_combout )) - - .dataa(\z80_|ir_|opcode [3]), - .datab(gnd), - .datac(\z80_|alu_|db[5]~25_combout ), - .datad(\z80_|alu_|db[7]~21_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~11 .lut_mask = 16'hFA50; -defparam \z80_|alu_|db_high[2]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N22 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~12 ( -// Equation(s): -// \z80_|alu_|db_high[2]~12_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_high[2]~11_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[6]~23_combout ))) - - .dataa(gnd), - .datab(\z80_|alu_|db_high[2]~11_combout ), - .datac(\z80_|alu_|db[6]~23_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~12 .lut_mask = 16'hCCF0; -defparam \z80_|alu_|db_high[2]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N24 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~10 ( -// Equation(s): -// \z80_|alu_|db_high[2]~10_combout = (\z80_|alu_|op1_high [2] & (((\z80_|alu_|op2_high [2]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|alu_|op1_high [2] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_high [2]) # -// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) - - .dataa(\z80_|alu_|op1_high [2]), - .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datac(\z80_|alu_|op2_high [2]), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~10 .lut_mask = 16'hB0BB; -defparam \z80_|alu_|db_high[2]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N20 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~13 ( -// Equation(s): -// \z80_|alu_|db_high[2]~13_combout = (\z80_|alu_|db_high[2]~9_combout & (\z80_|alu_|db_high[2]~10_combout & ((\z80_|alu_|db_high[2]~12_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) - - .dataa(\z80_|alu_|db_high[2]~9_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datac(\z80_|alu_|db_high[2]~12_combout ), - .datad(\z80_|alu_|db_high[2]~10_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~13 .lut_mask = 16'hA200; -defparam \z80_|alu_|db_high[2]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N10 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~14 ( -// Equation(s): -// \z80_|alu_|db_high[2]~14_combout = ((\z80_|alu_|db_high[2]~13_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) # (!\z80_|alu_|db_high[3]~3_combout ) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), - .datab(\z80_|alu_|db_high[3]~3_combout ), - .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datad(\z80_|alu_|db_high[2]~13_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~14 .lut_mask = 16'hFB33; -defparam \z80_|alu_|db_high[2]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N18 -cycloneive_lcell_comb \z80_|alu_|db[6]~22 ( -// Equation(s): -// \z80_|alu_|db[6]~22_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[6]~84_combout & ((\z80_|alu_control_|db[6]~22_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & -// (((\z80_|alu_control_|db[6]~22_combout )) # (!\z80_|execute_|ctl_sw_2d~13_combout ))) - - .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datab(\z80_|execute_|ctl_sw_2d~13_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .datad(\z80_|alu_control_|db[6]~22_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[6]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[6]~22 .lut_mask = 16'hF531; -defparam \z80_|alu_|db[6]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N20 -cycloneive_lcell_comb \z80_|alu_|db[6]~23 ( -// Equation(s): -// \z80_|alu_|db[6]~23_combout = ((\z80_|alu_|db[6]~22_combout & ((\z80_|alu_|db_high[2]~14_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~26_combout ) - - .dataa(\z80_|alu_|db_high[2]~14_combout ), - .datab(\z80_|execute_|ctl_alu_oe~14_combout ), - .datac(\z80_|alu_|db[6]~22_combout ), - .datad(\z80_|alu_|db[7]~26_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[6]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[6]~23 .lut_mask = 16'hB0FF; -defparam \z80_|alu_|db[6]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N10 -cycloneive_lcell_comb \z80_|alu_control_|out[6]~1 ( -// Equation(s): -// \z80_|alu_control_|out[6]~1_combout = (\z80_|alu_|op1_high [2]) # ((\z80_|alu_|op1_high [1]) # ((\z80_|alu_|op1_high [0] & \z80_|alu_control_|out[6]~0_combout ))) - - .dataa(\z80_|alu_|op1_high [2]), - .datab(\z80_|alu_|op1_high [0]), - .datac(\z80_|alu_|op1_high [1]), - .datad(\z80_|alu_control_|out[6]~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|out[6]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|out[6]~1 .lut_mask = 16'hFEFA; -defparam \z80_|alu_control_|out[6]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N26 -cycloneive_lcell_comb \z80_|alu_control_|out[6]~2 ( -// Equation(s): -// \z80_|alu_control_|out[6]~2_combout = (\z80_|execute_|ctl_66_oe~combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_cf~q ) # ((\z80_|alu_control_|out[6]~1_combout & \z80_|alu_|op1_high [3]))) - - .dataa(\z80_|execute_|ctl_66_oe~combout ), - .datab(\z80_|alu_control_|out[6]~1_combout ), - .datac(\z80_|alu_|op1_high [3]), - .datad(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), - .cin(gnd), - .combout(\z80_|alu_control_|out[6]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|out[6]~2 .lut_mask = 16'hFFEA; -defparam \z80_|alu_control_|out[6]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N12 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~19 ( -// Equation(s): -// \z80_|alu_control_|db[6]~19_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & ((\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ) # ((\z80_|alu_control_|out[6]~2_combout )))) # (!\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & -// (!\z80_|execute_|ctl_flags_oe~2_combout & ((\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ) # (\z80_|alu_control_|out[6]~2_combout )))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .datab(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .datac(\z80_|execute_|ctl_flags_oe~2_combout ), - .datad(\z80_|alu_control_|out[6]~2_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~19 .lut_mask = 16'hAF8C; -defparam \z80_|alu_control_|db[6]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N26 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~20 ( -// Equation(s): -// \z80_|alu_control_|db[6]~20_combout = (\z80_|alu_control_|db[6]~19_combout & ((\z80_|alu_|db[6]~23_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout ))) - - .dataa(gnd), - .datab(\z80_|alu_|db[6]~23_combout ), - .datac(\z80_|execute_|ctl_sw_2u~7_combout ), - .datad(\z80_|alu_control_|db[6]~19_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~20 .lut_mask = 16'hCF00; -defparam \z80_|alu_control_|db[6]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N24 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~21 ( -// Equation(s): -// \z80_|alu_control_|db[6]~21_combout = (\z80_|alu_control_|db[6]~20_combout & (((\z80_|bus_control_|db[6]~9_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) - - .dataa(\z80_|bus_control_|db[6]~9_combout ), - .datab(\z80_|execute_|ctl_sw_1d~7_combout ), - .datac(\z80_|alu_control_|db[6]~20_combout ), - .datad(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~21 .lut_mask = 16'h30B0; -defparam \z80_|alu_control_|db[6]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N6 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~22 ( -// Equation(s): -// \z80_|alu_control_|db[6]~22_combout = ((\z80_|alu_control_|db[6]~21_combout & ((\z80_|reg_file_|gdfx_temp0[6]~82_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|alu_control_|db[6]~11_combout ), - .datab(\z80_|alu_control_|db[6]~21_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .datad(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~22 .lut_mask = 16'hD5DD; -defparam \z80_|alu_control_|db[6]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_zero_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_bus_zero_oe~0_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal33~1_combout & ((\z80_|execute_|ctl_alu_op_low~13_combout ) # (\z80_|execute_|ctl_iorw~11_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~13_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_iorw~11_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_zero_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_zero_oe~0 .lut_mask = 16'hC800; -defparam \z80_|execute_|ctl_bus_zero_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N8 -cycloneive_lcell_comb \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 ( -// Equation(s): -// \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout = (\z80_|bus_control_|db[4]~19_combout & !\z80_|bus_control_|db[3]~21_combout ) - - .dataa(gnd), - .datab(\z80_|bus_control_|db[4]~19_combout ), - .datac(gnd), - .datad(\z80_|bus_control_|db[3]~21_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 .lut_mask = 16'h00CC; -defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y10_N9 -dffeas \z80_|interrupts_|im1 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_im_we~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|interrupts_|im1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|interrupts_|im1 .is_wysiwyg = "true"; -defparam \z80_|interrupts_|im1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_ff_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_bus_ff_oe~0_combout = (\z80_|interrupts_|DFFE_inst44~q & ((\z80_|interrupts_|im1~q ) # ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|interrupts_|im2~q )))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|interrupts_|im1~q ), - .datac(\z80_|interrupts_|im2~q ), - .datad(\z80_|interrupts_|DFFE_inst44~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_ff_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_ff_oe~0 .lut_mask = 16'hDC00; -defparam \z80_|execute_|ctl_bus_ff_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_ff_oe~1 ( -// Equation(s): -// \z80_|execute_|ctl_bus_ff_oe~1_combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) # (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|execute_|ctl_bus_ff_oe~0_combout & -// ((\z80_|execute_|ctl_66_oe~2_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|execute_|ctl_bus_ff_oe~0_combout ), - .datac(\z80_|execute_|ctl_66_oe~2_combout ), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_ff_oe~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_ff_oe~1 .lut_mask = 16'h40EE; -defparam \z80_|execute_|ctl_bus_ff_oe~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N0 -cycloneive_lcell_comb \z80_|bus_control_|db[0]~4 ( -// Equation(s): -// \z80_|bus_control_|db[0]~4_combout = (\z80_|execute_|ctl_bus_ff_oe~1_combout ) # ((!\z80_|execute_|ctl_bus_zero_oe~0_combout & ((\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) # (!\z80_|decode_state_|in_halt~q )))) - - .dataa(\z80_|decode_state_|in_halt~q ), - .datab(\z80_|execute_|ctl_bus_zero_oe~0_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|execute_|ctl_bus_ff_oe~1_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[0]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[0]~4 .lut_mask = 16'hFF31; -defparam \z80_|bus_control_|db[0]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N6 -cycloneive_lcell_comb \z80_|bus_control_|db[6]~8 ( -// Equation(s): -// \z80_|bus_control_|db[6]~8_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[6]~22_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) - - .dataa(gnd), - .datab(\z80_|alu_control_|db[6]~22_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|bus_control_|db[0]~4_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[6]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[6]~8 .lut_mask = 16'hCF00; -defparam \z80_|bus_control_|db[6]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~37 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~37_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal37~0_combout & !\z80_|execute_|ctl_mRead~36_combout ))) # (!\z80_|sequencer_|DFFE_T5_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|pla_decode_|Equal37~0_combout ), - .datad(\z80_|execute_|ctl_mRead~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~37 .lut_mask = 16'hDDDF; -defparam \z80_|execute_|ctl_mRead~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~28 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~28_combout = (\z80_|execute_|ctl_mRead~37_combout & (!\z80_|execute_|ctl_reg_gp_sel~36_combout & ((!\z80_|pla_decode_|Equal38~2_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~37_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel~36_combout ), - .datad(\z80_|pla_decode_|Equal38~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~28 .lut_mask = 16'h020A; -defparam \z80_|execute_|ctl_mRead~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~29 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~29_combout = (\z80_|execute_|ctl_mRead~28_combout & (\z80_|execute_|ctl_mRead~25_combout & ((!\z80_|pla_decode_|Equal21~1_combout ) # (!\z80_|execute_|ctl_mRead~11_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~28_combout ), - .datab(\z80_|execute_|ctl_mRead~11_combout ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|execute_|ctl_mRead~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~29 .lut_mask = 16'h2A00; -defparam \z80_|execute_|ctl_mRead~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~30 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~30_combout = (\z80_|execute_|ctl_mRead~29_combout & (\z80_|execute_|ctl_reg_in_hi~5_combout & (\z80_|execute_|ctl_mRead~22_combout & !\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ))) - - .dataa(\z80_|execute_|ctl_mRead~29_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~5_combout ), - .datac(\z80_|execute_|ctl_mRead~22_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~30 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_mRead~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y18_N0 -cycloneive_lcell_comb \z80_|execute_|setM1~37 ( -// Equation(s): -// \z80_|execute_|setM1~37_combout = (!\z80_|pla_decode_|Equal9~1_combout & (!\z80_|pla_decode_|Equal29~0_combout & (\z80_|execute_|ctl_al_we~4_combout & \z80_|execute_|ctl_inc_cy~41_combout ))) - - .dataa(\z80_|pla_decode_|Equal9~1_combout ), - .datab(\z80_|pla_decode_|Equal29~0_combout ), - .datac(\z80_|execute_|ctl_al_we~4_combout ), - .datad(\z80_|execute_|ctl_inc_cy~41_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~37 .lut_mask = 16'h1000; -defparam \z80_|execute_|setM1~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N10 -cycloneive_lcell_comb \z80_|execute_|setM1~55 ( +// Location: LCCOMB_X25_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|ixy_d~17 ( // Equation(s): -// \z80_|execute_|setM1~55_combout = (!\z80_|execute_|ctl_mRead~14_combout & ((\z80_|decode_state_|DFFE_instIY1~q ) # ((\z80_|decode_state_|DFFE_inst4~q ) # (!\z80_|pla_decode_|Equal49~0_combout )))) +// \z80_|execute_|ixy_d~17_combout = (\z80_|decode_state_|DFFE_instIY1~q & (((!\z80_|pla_decode_|Equal33~2_combout & !\z80_|pla_decode_|Equal50~0_combout )))) # (!\z80_|decode_state_|DFFE_instIY1~q & (((!\z80_|pla_decode_|Equal33~2_combout & +// !\z80_|pla_decode_|Equal50~0_combout )) # (!\z80_|decode_state_|DFFE_inst4~q ))) .dataa(\z80_|decode_state_|DFFE_instIY1~q ), - .datab(\z80_|execute_|ctl_mRead~14_combout ), - .datac(\z80_|decode_state_|DFFE_inst4~q ), - .datad(\z80_|pla_decode_|Equal49~0_combout ), + .datab(\z80_|decode_state_|DFFE_inst4~q ), + .datac(\z80_|pla_decode_|Equal33~2_combout ), + .datad(\z80_|pla_decode_|Equal50~0_combout ), .cin(gnd), - .combout(\z80_|execute_|setM1~55_combout ), + .combout(\z80_|execute_|ixy_d~17_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|setM1~55 .lut_mask = 16'h3233; -defparam \z80_|execute_|setM1~55 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ixy_d~17 .lut_mask = 16'h111F; +defparam \z80_|execute_|ixy_d~17 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y18_N30 -cycloneive_lcell_comb \z80_|execute_|setM1~38 ( +// Location: LCCOMB_X25_Y16_N0 +cycloneive_lcell_comb \z80_|pla_decode_|Equal44~0 ( // Equation(s): -// \z80_|execute_|setM1~38_combout = (!\z80_|execute_|ctl_mRead~16_combout & (\z80_|execute_|setM1~37_combout & (\z80_|execute_|setM1~55_combout & \z80_|execute_|setM1~36_combout ))) +// \z80_|pla_decode_|Equal44~0_combout = (!\z80_|decode_state_|DFFE_instCB~q & (!\z80_|decode_state_|DFFE_instED~q & (\z80_|ir_|opcode [7] & !\z80_|ir_|opcode [6]))) - .dataa(\z80_|execute_|ctl_mRead~16_combout ), - .datab(\z80_|execute_|setM1~37_combout ), - .datac(\z80_|execute_|setM1~55_combout ), - .datad(\z80_|execute_|setM1~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~38 .lut_mask = 16'h4000; -defparam \z80_|execute_|setM1~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~34 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~34_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (((\z80_|execute_|ctl_mRead~13_combout ) # (!\z80_|execute_|ctl_mRead~19_combout )) # (!\z80_|execute_|setM1~38_combout ))) - - .dataa(\z80_|execute_|setM1~38_combout ), - .datab(\z80_|execute_|ctl_mRead~13_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_mRead~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~34 .lut_mask = 16'hD0F0; -defparam \z80_|execute_|ctl_mRead~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N2 -cycloneive_lcell_comb \z80_|execute_|nextM~3 ( -// Equation(s): -// \z80_|execute_|nextM~3_combout = (!\z80_|pla_decode_|Equal41~2_combout & (!\z80_|execute_|ixy_d~10_combout & !\z80_|execute_|ixy_d~16_combout )) - - .dataa(gnd), - .datab(\z80_|pla_decode_|Equal41~2_combout ), - .datac(\z80_|execute_|ixy_d~10_combout ), - .datad(\z80_|execute_|ixy_d~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~3 .lut_mask = 16'h0003; -defparam \z80_|execute_|nextM~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~31 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~31_combout = (\z80_|execute_|ixy_d~8_combout & (((\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal49~0_combout )) # (!\z80_|execute_|nextM~3_combout ))) - - .dataa(\z80_|execute_|ixy_d~8_combout ), - .datab(\z80_|decode_state_|use_ixiy~combout ), - .datac(\z80_|execute_|nextM~3_combout ), - .datad(\z80_|pla_decode_|Equal49~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~31 .lut_mask = 16'h8A0A; -defparam \z80_|execute_|ctl_mRead~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~32 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~32_combout = (\z80_|execute_|ctl_state_alu~4_combout & ((\z80_|pla_decode_|Equal33~3_combout ) # ((\z80_|pla_decode_|Equal6~1_combout ) # (\z80_|pla_decode_|Equal41~2_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|pla_decode_|Equal33~3_combout ), - .datac(\z80_|pla_decode_|Equal6~1_combout ), - .datad(\z80_|pla_decode_|Equal41~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~32 .lut_mask = 16'hAAA8; -defparam \z80_|execute_|ctl_mRead~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~33 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~33_combout = (\z80_|execute_|ctl_mRead~32_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & \z80_|execute_|ctl_mRead~12_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .datac(\z80_|execute_|ctl_mRead~12_combout ), - .datad(\z80_|execute_|ctl_mRead~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~33 .lut_mask = 16'hFFC0; -defparam \z80_|execute_|ctl_mRead~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~35 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~35_combout = ((\z80_|execute_|ctl_mRead~34_combout ) # ((\z80_|execute_|ctl_mRead~31_combout ) # (\z80_|execute_|ctl_mRead~33_combout ))) # (!\z80_|execute_|ctl_mRead~30_combout ) - - .dataa(\z80_|execute_|ctl_mRead~30_combout ), - .datab(\z80_|execute_|ctl_mRead~34_combout ), - .datac(\z80_|execute_|ctl_mRead~31_combout ), - .datad(\z80_|execute_|ctl_mRead~33_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~35 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_mRead~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X43_Y17_N23 -dffeas \z80_|memory_ifc_|DFFE_mrd_ff1 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_mRead~35_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_mrd_ff1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_mrd_ff1 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_mrd_ff1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y15_N24 -cycloneive_lcell_comb \z80_|memory_ifc_|wait_mrd~feeder ( -// Equation(s): -// \z80_|memory_ifc_|wait_mrd~feeder_combout = \z80_|memory_ifc_|DFFE_mrd_ff1~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|memory_ifc_|DFFE_mrd_ff1~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|wait_mrd~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_mrd~feeder .lut_mask = 16'hFF00; -defparam \z80_|memory_ifc_|wait_mrd~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X46_Y15_N25 -dffeas \z80_|memory_ifc_|wait_mrd ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|memory_ifc_|wait_mrd~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|wait_mrd~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_mrd .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|wait_mrd .power_up = "low"; -// synopsys translate_on - -// Location: FF_X43_Y17_N3 -dffeas \z80_|memory_ifc_|DFFE_mrd_ff3 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|memory_ifc_|wait_mrd~q ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_mrd_ff3~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_mrd_ff3 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_mrd_ff3 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N8 -cycloneive_lcell_comb \z80_|memory_ifc_|nRD_out~1 ( -// Equation(s): -// \z80_|memory_ifc_|nRD_out~1_combout = (!\z80_|memory_ifc_|wait_mrd~q & !\z80_|memory_ifc_|DFFE_mrd_ff3~q ) - - .dataa(\z80_|memory_ifc_|wait_mrd~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|memory_ifc_|DFFE_mrd_ff3~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|nRD_out~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|nRD_out~1 .lut_mask = 16'h0055; -defparam \z80_|memory_ifc_|nRD_out~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N30 -cycloneive_lcell_comb \z80_|execute_|nextM~4 ( -// Equation(s): -// \z80_|execute_|nextM~4_combout = ((!\z80_|execute_|ctl_mRead~36_combout & ((!\z80_|pla_decode_|Equal24~0_combout ) # (!\z80_|pla_decode_|Equal21~0_combout )))) # (!\z80_|execute_|ctl_state_alu~4_combout ) - - .dataa(\z80_|pla_decode_|Equal21~0_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_mRead~36_combout ), - .datad(\z80_|pla_decode_|Equal24~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~4 .lut_mask = 16'h373F; -defparam \z80_|execute_|nextM~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_iorw~12 ( -// Equation(s): -// \z80_|execute_|ctl_iorw~12_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2]))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|execute_|ctl_iorw~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_iorw~12 .lut_mask = 16'h0008; -defparam \z80_|execute_|ctl_iorw~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_iorw~8 ( -// Equation(s): -// \z80_|execute_|ctl_iorw~8_combout = (\z80_|execute_|ctl_iorw~12_combout ) # ((\z80_|pla_decode_|Equal24~0_combout & (\z80_|pla_decode_|Equal3~0_combout & \z80_|execute_|ctl_state_alu~4_combout ))) - - .dataa(\z80_|pla_decode_|Equal24~0_combout ), - .datab(\z80_|execute_|ctl_iorw~12_combout ), - .datac(\z80_|pla_decode_|Equal3~0_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_iorw~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_iorw~8 .lut_mask = 16'hECCC; -defparam \z80_|execute_|ctl_iorw~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_iorw~9 ( -// Equation(s): -// \z80_|execute_|ctl_iorw~9_combout = ((\z80_|execute_|ctl_iorw~8_combout ) # ((\z80_|execute_|ctl_mRead~11_combout & \z80_|execute_|ctl_mWrite~16_combout ))) # (!\z80_|execute_|nextM~4_combout ) - - .dataa(\z80_|execute_|nextM~4_combout ), - .datab(\z80_|execute_|ctl_mRead~11_combout ), - .datac(\z80_|execute_|ctl_mWrite~16_combout ), - .datad(\z80_|execute_|ctl_iorw~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_iorw~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_iorw~9 .lut_mask = 16'hFFD5; -defparam \z80_|execute_|ctl_iorw~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X43_Y17_N7 -dffeas \z80_|memory_ifc_|DFFE_iorq_ff1 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_iorw~9_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_iorq_ff1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_iorq_ff1 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_iorq_ff1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N26 -cycloneive_lcell_comb \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder ( -// Equation(s): -// \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder_combout = \z80_|memory_ifc_|DFFE_iorq_ff1~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|memory_ifc_|DFFE_iorq_ff1~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder .lut_mask = 16'hFF00; -defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X43_Y17_N27 -dffeas \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 .power_up = "low"; -// synopsys translate_on - -// Location: FF_X43_Y17_N9 -dffeas \z80_|memory_ifc_|wait_iorq ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|wait_iorq~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_iorq .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|wait_iorq .power_up = "low"; -// synopsys translate_on - -// Location: FF_X43_Y17_N13 -dffeas \z80_|memory_ifc_|DFFE_iorq_ff4 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|memory_ifc_|wait_iorq~q ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_iorq_ff4~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_iorq_ff4 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_iorq_ff4 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N12 -cycloneive_lcell_comb \z80_|memory_ifc_|iorq~0 ( -// Equation(s): -// \z80_|memory_ifc_|iorq~0_combout = (\z80_|memory_ifc_|wait_iorq~q ) # ((\z80_|memory_ifc_|DFFE_iorq_ff4~q ) # (\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q )) - - .dataa(gnd), - .datab(\z80_|memory_ifc_|wait_iorq~q ), - .datac(\z80_|memory_ifc_|DFFE_iorq_ff4~q ), - .datad(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|iorq~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|iorq~0 .lut_mask = 16'hFFFC; -defparam \z80_|memory_ifc_|iorq~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|fIORead~1 ( -// Equation(s): -// \z80_|execute_|fIORead~1_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_mWrite~2_combout & ((\z80_|execute_|ctl_state_alu~5_combout ) # (\z80_|execute_|ctl_mWrite~3_combout )))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|execute_|ctl_state_alu~5_combout ), - .datac(\z80_|execute_|ctl_mWrite~3_combout ), - .datad(\z80_|execute_|ctl_mWrite~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIORead~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIORead~1 .lut_mask = 16'hA800; -defparam \z80_|execute_|fIORead~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N18 -cycloneive_lcell_comb \z80_|execute_|fIORead~2 ( -// Equation(s): -// \z80_|execute_|fIORead~2_combout = (\z80_|execute_|fIORead~1_combout ) # ((\z80_|execute_|ctl_alu_op_low~9_combout ) # ((\z80_|execute_|ctl_iorw~10_combout & !\z80_|execute_|fIOWrite~0_combout ))) - - .dataa(\z80_|execute_|ctl_iorw~10_combout ), - .datab(\z80_|execute_|fIOWrite~0_combout ), - .datac(\z80_|execute_|fIORead~1_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIORead~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIORead~2 .lut_mask = 16'hFFF2; -defparam \z80_|execute_|fIORead~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y18_N6 -cycloneive_lcell_comb \z80_|execute_|fIORead~0 ( -// Equation(s): -// \z80_|execute_|fIORead~0_combout = (\z80_|execute_|ctl_mWrite~2_combout & (\z80_|pla_decode_|Equal55~0_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ctl_alu_op_low~8_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~2_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIORead~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIORead~0 .lut_mask = 16'hA080; -defparam \z80_|execute_|fIORead~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N6 -cycloneive_lcell_comb \z80_|execute_|fIORead~3 ( -// Equation(s): -// \z80_|execute_|fIORead~3_combout = (\z80_|execute_|fIORead~2_combout ) # ((\z80_|execute_|fIORead~0_combout ) # ((\z80_|execute_|fIOWrite~1_combout & \z80_|execute_|ctl_mRead~4_combout ))) - - .dataa(\z80_|execute_|fIOWrite~1_combout ), - .datab(\z80_|execute_|fIORead~2_combout ), - .datac(\z80_|execute_|ctl_mRead~4_combout ), - .datad(\z80_|execute_|fIORead~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIORead~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIORead~3 .lut_mask = 16'hFFEC; -defparam \z80_|execute_|fIORead~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X41_Y17_N25 -dffeas \z80_|memory_ifc_|DFFE_m1_ff1 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|setM1~52_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_m1_ff1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_m1_ff1 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_m1_ff1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N14 -cycloneive_lcell_comb \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0 ( -// Equation(s): -// \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout = !\z80_|memory_ifc_|DFFE_m1_ff1~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|memory_ifc_|DFFE_m1_ff1~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0 .lut_mask = 16'h00FF; -defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X43_Y17_N15 -dffeas \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 .power_up = "low"; -// synopsys translate_on - -// Location: FF_X43_Y17_N21 -dffeas \z80_|memory_ifc_|DFFE_m1_ff3 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_m1_ff3~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_m1_ff3 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_m1_ff3 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N20 -cycloneive_lcell_comb \z80_|memory_ifc_|nRD_out~0 ( -// Equation(s): -// \z80_|memory_ifc_|nRD_out~0_combout = (\z80_|interrupts_|DFFE_inst44~q & (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & ((\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ) # (\z80_|memory_ifc_|DFFE_m1_ff3~q )))) # (!\z80_|interrupts_|DFFE_inst44~q & -// ((\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ) # ((\z80_|memory_ifc_|DFFE_m1_ff3~q )))) - - .dataa(\z80_|interrupts_|DFFE_inst44~q ), - .datab(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ), - .datac(\z80_|memory_ifc_|DFFE_m1_ff3~q ), - .datad(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|nRD_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|nRD_out~0 .lut_mask = 16'hFC54; -defparam \z80_|memory_ifc_|nRD_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N18 -cycloneive_lcell_comb \z80_|memory_ifc_|nRD_out~2 ( -// Equation(s): -// \z80_|memory_ifc_|nRD_out~2_combout = ((\z80_|memory_ifc_|nRD_out~0_combout ) # ((\z80_|memory_ifc_|iorq~0_combout & \z80_|execute_|fIORead~3_combout ))) # (!\z80_|memory_ifc_|nRD_out~1_combout ) - - .dataa(\z80_|memory_ifc_|nRD_out~1_combout ), - .datab(\z80_|memory_ifc_|iorq~0_combout ), - .datac(\z80_|execute_|fIORead~3_combout ), - .datad(\z80_|memory_ifc_|nRD_out~0_combout ), - .cin(gnd), - .combout(\z80_|memory_ifc_|nRD_out~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|nRD_out~2 .lut_mask = 16'hFFD5; -defparam \z80_|memory_ifc_|nRD_out~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N24 -cycloneive_lcell_comb \Equal2~1 ( -// Equation(s): -// \Equal2~1_combout = (!\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|memory_ifc_|nRD_out~2_combout & \z80_|resets_|SYNTHESIZED_WIRE_12~q )) - - .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), - .datab(\z80_|memory_ifc_|nRD_out~2_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(gnd), - .cin(gnd), - .combout(\Equal2~1_combout ), - .cout()); -// synopsys translate_off -defparam \Equal2~1 .lut_mask = 16'h4040; -defparam \Equal2~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N30 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~0 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~0_combout = (\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~0 .lut_mask = 16'hFFAA; -defparam \z80_|pin_control_|bus_db_pin_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y18_N10 -cycloneive_lcell_comb \z80_|execute_|fMWrite~5 ( -// Equation(s): -// \z80_|execute_|fMWrite~5_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|sequencer_|DFFE_M4_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~5 .lut_mask = 16'h3F33; -defparam \z80_|execute_|fMWrite~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N8 -cycloneive_lcell_comb \z80_|execute_|fMWrite~6 ( -// Equation(s): -// \z80_|execute_|fMWrite~6_combout = (!\z80_|execute_|fMWrite~5_combout & ((\z80_|execute_|ctl_mRead~7_combout ) # ((\z80_|pla_decode_|Equal13~2_combout ) # (\z80_|execute_|ctl_mWrite~5_combout )))) - - .dataa(\z80_|execute_|fMWrite~5_combout ), - .datab(\z80_|execute_|ctl_mRead~7_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|ctl_mWrite~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~6 .lut_mask = 16'h5554; -defparam \z80_|execute_|fMWrite~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N30 -cycloneive_lcell_comb \z80_|execute_|fMWrite~2 ( -// Equation(s): -// \z80_|execute_|fMWrite~2_combout = ((!\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|M5~q ) - - .dataa(\z80_|sequencer_|M5~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~2 .lut_mask = 16'h555F; -defparam \z80_|execute_|fMWrite~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N2 -cycloneive_lcell_comb \z80_|execute_|fMWrite~4 ( -// Equation(s): -// \z80_|execute_|fMWrite~4_combout = (!\z80_|execute_|fMWrite~3_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ixy_d~6_combout ) # (!\z80_|execute_|fMWrite~2_combout )))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|execute_|fMWrite~2_combout ), - .datad(\z80_|execute_|fMWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~4 .lut_mask = 16'h00EF; -defparam \z80_|execute_|fMWrite~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N20 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~1 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~1_combout = (\z80_|execute_|ctl_bus_inc_oe~24_combout & (!\z80_|execute_|fIOWrite~5_combout & (!\z80_|execute_|fMWrite~6_combout & !\z80_|execute_|fMWrite~4_combout ))) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~24_combout ), - .datab(\z80_|execute_|fIOWrite~5_combout ), - .datac(\z80_|execute_|fMWrite~6_combout ), - .datad(\z80_|execute_|fMWrite~4_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~1 .lut_mask = 16'h0002; -defparam \z80_|pin_control_|bus_db_pin_oe~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N30 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~2 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~2_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|pla_decode_|Equal11~0_combout & ((!\z80_|execute_|ctl_mRead~8_combout ) # (!\z80_|execute_|ctl_reg_in_hi~2_combout )))) # (!\z80_|execute_|ixy_d~7_combout & -// (((!\z80_|execute_|ctl_mRead~8_combout )) # (!\z80_|execute_|ctl_reg_in_hi~2_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|execute_|ctl_mRead~8_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~2 .lut_mask = 16'h135F; -defparam \z80_|pin_control_|bus_db_pin_oe~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N24 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~3 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~3_combout = (\z80_|pin_control_|bus_db_pin_oe~2_combout & (((\z80_|execute_|ixy_d~4_combout ) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|execute_|ctl_mWrite~5_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~2_combout ), - .datab(\z80_|execute_|ctl_mWrite~5_combout ), - .datac(\z80_|execute_|ixy_d~4_combout ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~3 .lut_mask = 16'hA2AA; -defparam \z80_|pin_control_|bus_db_pin_oe~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N8 -cycloneive_lcell_comb \z80_|execute_|fMWrite~7 ( -// Equation(s): -// \z80_|execute_|fMWrite~7_combout = (!\z80_|execute_|ctl_mWrite~16_combout & (!\z80_|execute_|ctl_mWrite~4_combout & !\z80_|execute_|ctl_mRead~7_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_mWrite~16_combout ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|execute_|ctl_mRead~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~7 .lut_mask = 16'h0003; -defparam \z80_|execute_|fMWrite~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N30 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~4 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~4_combout = (\z80_|execute_|ctl_inc_dec~2_combout & ((\z80_|execute_|fMWrite~7_combout ) # ((!\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ixy_d~6_combout )))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|fMWrite~7_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|execute_|ctl_inc_dec~2_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~4 .lut_mask = 16'hCD00; -defparam \z80_|pin_control_|bus_db_pin_oe~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N10 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~7 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~7_combout = (\z80_|execute_|ctl_ir_we~4_combout & (!\z80_|execute_|ctl_mRead~10_combout & ((!\z80_|execute_|ctl_mRead~7_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|execute_|ctl_ir_we~4_combout & -// (((!\z80_|execute_|ctl_mRead~7_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ctl_mRead~10_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|execute_|ctl_mRead~7_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~7 .lut_mask = 16'h0777; -defparam \z80_|pin_control_|bus_db_pin_oe~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N4 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~6 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~6_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|execute_|ctl_mRead~6_combout & ((\z80_|execute_|fMRead~1_combout )))) # (!\z80_|execute_|ixy_d~7_combout & (((!\z80_|execute_|ctl_alu_oe~2_combout )) # -// (!\z80_|execute_|ctl_mRead~6_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|execute_|ctl_alu_oe~2_combout ), - .datad(\z80_|execute_|fMRead~1_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~6 .lut_mask = 16'h3715; -defparam \z80_|pin_control_|bus_db_pin_oe~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|fMWrite~9 ( -// Equation(s): -// \z80_|execute_|fMWrite~9_combout = (\z80_|pla_decode_|Equal46~0_combout ) # (((\z80_|ir_|opcode [6] & !\z80_|ir_|opcode [7])) # (!\z80_|execute_|ctl_ir_we~5_combout )) - - .dataa(\z80_|ir_|opcode [6]), - .datab(\z80_|pla_decode_|Equal46~0_combout ), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|execute_|ctl_ir_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~9 .lut_mask = 16'hCEFF; -defparam \z80_|execute_|fMWrite~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N22 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~8 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~8_combout = (\z80_|execute_|ctl_mWrite~6_combout & (\z80_|execute_|fIOWrite~0_combout & ((\z80_|execute_|fMWrite~2_combout ) # (\z80_|execute_|fMWrite~9_combout )))) # (!\z80_|execute_|ctl_mWrite~6_combout & -// (((\z80_|execute_|fMWrite~2_combout ) # (\z80_|execute_|fMWrite~9_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~6_combout ), - .datab(\z80_|execute_|fIOWrite~0_combout ), - .datac(\z80_|execute_|fMWrite~2_combout ), - .datad(\z80_|execute_|fMWrite~9_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~8 .lut_mask = 16'hDDD0; -defparam \z80_|pin_control_|bus_db_pin_oe~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N0 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~9 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~9_combout = (\z80_|pin_control_|bus_db_pin_oe~8_combout & (\z80_|execute_|fMWrite~11_combout & !\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout )) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~8_combout ), - .datab(\z80_|execute_|fMWrite~11_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~9 .lut_mask = 16'h0808; -defparam \z80_|pin_control_|bus_db_pin_oe~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N26 -cycloneive_lcell_comb \z80_|execute_|fMWrite~8 ( -// Equation(s): -// \z80_|execute_|fMWrite~8_combout = (\z80_|execute_|ctl_state_alu~6_combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # ((\z80_|execute_|ctl_mRead~7_combout ) # (\z80_|execute_|ctl_mRead~9_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~5_combout ), - .datab(\z80_|execute_|ctl_mRead~7_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_mRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~8 .lut_mask = 16'hF0E0; -defparam \z80_|execute_|fMWrite~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N26 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~5 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~5_combout = (\z80_|execute_|ctl_reg_sel_wz~4_combout & (\z80_|execute_|ctl_reg_sel_wz~5_combout & (!\z80_|execute_|fMWrite~8_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~4_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~5_combout ), - .datac(\z80_|execute_|fMWrite~8_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~5 .lut_mask = 16'h0800; -defparam \z80_|pin_control_|bus_db_pin_oe~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N20 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~10 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~10_combout = (\z80_|pin_control_|bus_db_pin_oe~7_combout & (\z80_|pin_control_|bus_db_pin_oe~6_combout & (\z80_|pin_control_|bus_db_pin_oe~9_combout & \z80_|pin_control_|bus_db_pin_oe~5_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~7_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~6_combout ), - .datac(\z80_|pin_control_|bus_db_pin_oe~9_combout ), - .datad(\z80_|pin_control_|bus_db_pin_oe~5_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~10 .lut_mask = 16'h8000; -defparam \z80_|pin_control_|bus_db_pin_oe~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N22 -cycloneive_lcell_comb \z80_|execute_|fMWrite~10 ( -// Equation(s): -// \z80_|execute_|fMWrite~10_combout = (\z80_|execute_|ctl_reg_in_hi~2_combout & ((\z80_|pla_decode_|Equal9~1_combout ) # ((\z80_|execute_|ctl_mRead~10_combout )))) # (!\z80_|execute_|ctl_reg_in_hi~2_combout & (\z80_|execute_|ctl_alu_oe~2_combout & -// ((\z80_|pla_decode_|Equal9~1_combout ) # (\z80_|execute_|ctl_mRead~10_combout )))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datab(\z80_|pla_decode_|Equal9~1_combout ), - .datac(\z80_|execute_|ctl_alu_oe~2_combout ), - .datad(\z80_|execute_|ctl_mRead~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~10 .lut_mask = 16'hFAC8; -defparam \z80_|execute_|fMWrite~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N0 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~11 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~11_combout = (\z80_|pin_control_|bus_db_pin_oe~4_combout & (\z80_|pin_control_|bus_db_pin_oe~10_combout & (!\z80_|execute_|fMWrite~10_combout & \z80_|execute_|ctl_bus_inc_oe~28_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~4_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~10_combout ), - .datac(\z80_|execute_|fMWrite~10_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~28_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~11 .lut_mask = 16'h0800; -defparam \z80_|pin_control_|bus_db_pin_oe~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N26 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~12 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~12_combout = (\z80_|pin_control_|bus_db_pin_oe~3_combout & (\z80_|pin_control_|bus_db_pin_oe~11_combout & ((!\z80_|execute_|ixy_d~6_combout ) # (!\z80_|pla_decode_|Equal11~0_combout )))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~3_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|pin_control_|bus_db_pin_oe~11_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~12 .lut_mask = 16'h2A00; -defparam \z80_|pin_control_|bus_db_pin_oe~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N22 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~13 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~13_combout = (\z80_|execute_|ctl_apin_mux~0_combout & (\z80_|pin_control_|bus_db_pin_oe~1_combout & (\z80_|pin_control_|bus_db_pin_oe~12_combout & \z80_|execute_|ctl_inc_cy~37_combout ))) - - .dataa(\z80_|execute_|ctl_apin_mux~0_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~1_combout ), - .datac(\z80_|pin_control_|bus_db_pin_oe~12_combout ), - .datad(\z80_|execute_|ctl_inc_cy~37_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~13 .lut_mask = 16'h8000; -defparam \z80_|pin_control_|bus_db_pin_oe~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N28 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~14 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~14_combout = (\z80_|pin_control_|bus_db_pin_oe~0_combout & (((\z80_|sequencer_|DFFE_T4_ff~q & \z80_|execute_|fIOWrite~5_combout )) # (!\z80_|pin_control_|bus_db_pin_oe~13_combout ))) # -// (!\z80_|pin_control_|bus_db_pin_oe~0_combout & (((\z80_|sequencer_|DFFE_T4_ff~q & \z80_|execute_|fIOWrite~5_combout )))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~0_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~13_combout ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|execute_|fIOWrite~5_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~14 .lut_mask = 16'hF222; -defparam \z80_|pin_control_|bus_db_pin_oe~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N0 -cycloneive_lcell_comb \z80_|clk_delay_|DFF_inst5~feeder ( -// Equation(s): -// \z80_|clk_delay_|DFF_inst5~feeder_combout = \z80_|clk_delay_|SYNTHESIZED_WIRE_7~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ), - .cin(gnd), - .combout(\z80_|clk_delay_|DFF_inst5~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|clk_delay_|DFF_inst5~feeder .lut_mask = 16'hFF00; -defparam \z80_|clk_delay_|DFF_inst5~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X43_Y15_N1 -dffeas \z80_|clk_delay_|DFF_inst5 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|clk_delay_|DFF_inst5~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|clk_delay_|DFF_inst5~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|clk_delay_|DFF_inst5 .is_wysiwyg = "true"; -defparam \z80_|clk_delay_|DFF_inst5 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N22 -cycloneive_lcell_comb \z80_|memory_ifc_|wait_iorqinta~feeder ( -// Equation(s): -// \z80_|memory_ifc_|wait_iorqinta~feeder_combout = \z80_|clk_delay_|DFF_inst5~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|clk_delay_|DFF_inst5~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|wait_iorqinta~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_iorqinta~feeder .lut_mask = 16'hFF00; -defparam \z80_|memory_ifc_|wait_iorqinta~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X43_Y15_N23 -dffeas \z80_|memory_ifc_|wait_iorqinta ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|memory_ifc_|wait_iorqinta~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|wait_iorqinta~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_iorqinta .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|wait_iorqinta .power_up = "low"; -// synopsys translate_on - -// Location: FF_X43_Y15_N13 -dffeas \z80_|memory_ifc_|DFFE_intr_ff3 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|memory_ifc_|wait_iorqinta~q ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_intr_ff3~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_intr_ff3 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_intr_ff3 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N12 -cycloneive_lcell_comb \z80_|memory_ifc_|nIORQ_out~0 ( -// Equation(s): -// \z80_|memory_ifc_|nIORQ_out~0_combout = (\z80_|memory_ifc_|wait_iorqinta~q ) # ((\z80_|memory_ifc_|DFFE_intr_ff3~q ) # (\z80_|memory_ifc_|iorq~0_combout )) - - .dataa(\z80_|memory_ifc_|wait_iorqinta~q ), - .datab(gnd), - .datac(\z80_|memory_ifc_|DFFE_intr_ff3~q ), - .datad(\z80_|memory_ifc_|iorq~0_combout ), - .cin(gnd), - .combout(\z80_|memory_ifc_|nIORQ_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|nIORQ_out~0 .lut_mask = 16'hFFFA; -defparam \z80_|memory_ifc_|nIORQ_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N18 -cycloneive_lcell_comb \Equal2~0 ( -// Equation(s): -// \Equal2~0_combout = (!\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|memory_ifc_|nRD_out~2_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \z80_|memory_ifc_|nIORQ_out~0_combout ))) - - .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), - .datab(\z80_|memory_ifc_|nRD_out~2_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|memory_ifc_|nIORQ_out~0_combout ), - .cin(gnd), - .combout(\Equal2~0_combout ), - .cout()); -// synopsys translate_off -defparam \Equal2~0 .lut_mask = 16'h4000; -defparam \Equal2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N22 -cycloneive_lcell_comb \ExtRamWE~0 ( -// Equation(s): -// \ExtRamWE~0_combout = (\z80_|memory_ifc_|nWR_out~0_combout & (!\z80_|memory_ifc_|nRD_out~2_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|memory_ifc_|nIORQ_out~0_combout ))) - - .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), - .datab(\z80_|memory_ifc_|nRD_out~2_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|memory_ifc_|nIORQ_out~0_combout ), - .cin(gnd), - .combout(\ExtRamWE~0_combout ), - .cout()); -// synopsys translate_off -defparam \ExtRamWE~0 .lut_mask = 16'h0020; -defparam \ExtRamWE~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N18 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[13]~13 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[13]~13_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [13]))) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [13]), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[13]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[13]~13 .lut_mask = 16'hDD88; -defparam \z80_|address_pins_|DFFE_apin_latch[13]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux2~0 ( -// Equation(s): -// \z80_|execute_|ctl_apin_mux2~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_apin_mux2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_apin_mux2~0 .lut_mask = 16'h0B0B; -defparam \z80_|execute_|ctl_apin_mux2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N28 -cycloneive_lcell_comb \z80_|pin_control_|bus_ab_pin_we~2 ( -// Equation(s): -// \z80_|pin_control_|bus_ab_pin_we~2_combout = (((\z80_|execute_|fMRead~35_combout ) # (\z80_|execute_|fIORead~3_combout )) # (!\z80_|pin_control_|bus_db_pin_oe~13_combout )) # (!\z80_|sequencer_|DFFE_M1_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|pin_control_|bus_db_pin_oe~13_combout ), - .datac(\z80_|execute_|fMRead~35_combout ), - .datad(\z80_|execute_|fIORead~3_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_ab_pin_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_ab_pin_we~2 .lut_mask = 16'hFFF7; -defparam \z80_|pin_control_|bus_ab_pin_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N2 -cycloneive_lcell_comb \z80_|pin_control_|bus_ab_pin_we~3 ( -// Equation(s): -// \z80_|pin_control_|bus_ab_pin_we~3_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (((!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|pin_control_|bus_ab_pin_we~2_combout )) # (!\z80_|sequencer_|DFFE_M1_ff~q ))) # (!\z80_|sequencer_|DFFE_T3_ff~q & -// (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|pin_control_|bus_ab_pin_we~2_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|pin_control_|bus_ab_pin_we~2_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_ab_pin_we~3 .lut_mask = 16'h3B0A; -defparam \z80_|pin_control_|bus_ab_pin_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N19 -dffeas \z80_|address_pins_|DFFE_apin_latch[13] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[13]~13_combout ), - .asdata(\z80_|address_latch_|Q [13]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [13]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[13] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[13] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N0 -cycloneive_lcell_comb \z80_|address_pins_|abus[13]~20 ( -// Equation(s): -// \z80_|address_pins_|abus[13]~20_combout = (\z80_|address_pins_|DFFE_apin_latch [13]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [13]), - .datab(gnd), - .datac(gnd), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\z80_|address_pins_|abus[13]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[13]~20 .lut_mask = 16'hAAFF; -defparam \z80_|address_pins_|abus[13]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N28 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[14]~14 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[14]~14_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|address [14])) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [14]))) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [14]), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[14]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[14]~14 .lut_mask = 16'hDD88; -defparam \z80_|address_pins_|DFFE_apin_latch[14]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N29 -dffeas \z80_|address_pins_|DFFE_apin_latch[14] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[14]~14_combout ), - .asdata(\z80_|address_latch_|Q [14]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [14]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[14] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[14] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N4 -cycloneive_lcell_comb \z80_|address_pins_|abus[14]~23 ( -// Equation(s): -// \z80_|address_pins_|abus[14]~23_combout = (\z80_|address_pins_|DFFE_apin_latch [14]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(gnd), - .datad(\z80_|address_pins_|DFFE_apin_latch [14]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[14]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[14]~23 .lut_mask = 16'hFF33; -defparam \z80_|address_pins_|abus[14]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N10 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[15]~15 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[15]~15_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [15]))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [15])) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|abusz [15]), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|address [15]), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[15]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[15]~15 .lut_mask = 16'hEE44; -defparam \z80_|address_pins_|DFFE_apin_latch[15]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N11 -dffeas \z80_|address_pins_|DFFE_apin_latch[15] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[15]~15_combout ), - .asdata(\z80_|address_latch_|Q [15]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [15]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[15] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[15] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y15_N12 -cycloneive_lcell_comb \z80_|address_pins_|abus[15]~22 ( -// Equation(s): -// \z80_|address_pins_|abus[15]~22_combout = (\z80_|address_pins_|DFFE_apin_latch [15]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [15]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_pins_|abus[15]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[15]~22 .lut_mask = 16'hF3F3; -defparam \z80_|address_pins_|abus[15]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N8 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2] = (\ExtRamWE~0_combout & (\z80_|address_pins_|abus[13]~20_combout & (!\z80_|address_pins_|abus[14]~23_combout & \z80_|address_pins_|abus[15]~22_combout ))) - - .dataa(\ExtRamWE~0_combout ), - .datab(\z80_|address_pins_|abus[13]~20_combout ), - .datac(\z80_|address_pins_|abus[14]~23_combout ), - .datad(\z80_|address_pins_|abus[15]~22_combout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] .lut_mask = 16'h0800; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N22 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\z80_|address_pins_|DFFE_apin_latch [13] & !\z80_|address_pins_|DFFE_apin_latch [14])) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [13]), - .datad(\z80_|address_pins_|DFFE_apin_latch [14]), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 .lut_mask = 16'h00C0; -defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N0 -cycloneive_lcell_comb \z80_|address_pins_|abus[0]~16 ( -// Equation(s): -// \z80_|address_pins_|abus[0]~16_combout = (\z80_|address_pins_|DFFE_apin_latch [0]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [0]), - .datab(gnd), - .datac(gnd), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\z80_|address_pins_|abus[0]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[0]~16 .lut_mask = 16'hAAFF; -defparam \z80_|address_pins_|abus[0]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N28 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[1]~1 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[1]~1_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [1]))) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [1]), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[1]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[1]~1 .lut_mask = 16'hDD88; -defparam \z80_|address_pins_|DFFE_apin_latch[1]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y17_N29 -dffeas \z80_|address_pins_|DFFE_apin_latch[1] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[1]~1_combout ), - .asdata(\z80_|address_latch_|Q [1]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[1] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y18_N20 -cycloneive_lcell_comb \z80_|address_pins_|abus[1]~25 ( -// Equation(s): -// \z80_|address_pins_|abus[1]~25_combout = (\z80_|address_pins_|DFFE_apin_latch [1]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_pins_|DFFE_apin_latch [1]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[1]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[1]~25 .lut_mask = 16'hFF55; -defparam \z80_|address_pins_|abus[1]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N18 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[2]~2 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[2]~2_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [2])) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|abusz [2]), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[2]~2 .lut_mask = 16'hEE44; -defparam \z80_|address_pins_|DFFE_apin_latch[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y17_N19 -dffeas \z80_|address_pins_|DFFE_apin_latch[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[2]~2_combout ), - .asdata(\z80_|address_latch_|Q [2]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[2] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y18_N26 -cycloneive_lcell_comb \z80_|address_pins_|abus[2]~26 ( -// Equation(s): -// \z80_|address_pins_|abus[2]~26_combout = (\z80_|address_pins_|DFFE_apin_latch [2]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|address_pins_|DFFE_apin_latch [2]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[2]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[2]~26 .lut_mask = 16'hFF0F; -defparam \z80_|address_pins_|abus[2]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N0 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[3]~3 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[3]~3_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [3])) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|abusz [3]), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[3]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[3]~3 .lut_mask = 16'hEE44; -defparam \z80_|address_pins_|DFFE_apin_latch[3]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y17_N1 -dffeas \z80_|address_pins_|DFFE_apin_latch[3] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[3]~3_combout ), - .asdata(\z80_|address_latch_|Q [3]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[3] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y18_N12 -cycloneive_lcell_comb \z80_|address_pins_|abus[3]~27 ( -// Equation(s): -// \z80_|address_pins_|abus[3]~27_combout = (\z80_|address_pins_|DFFE_apin_latch [3]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|address_pins_|DFFE_apin_latch [3]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[3]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[3]~27 .lut_mask = 16'hFF0F; -defparam \z80_|address_pins_|abus[3]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N30 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[4]~4 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[4]~4_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [4])) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|abusz [4]), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[4]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[4]~4 .lut_mask = 16'hEE44; -defparam \z80_|address_pins_|DFFE_apin_latch[4]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y17_N31 -dffeas \z80_|address_pins_|DFFE_apin_latch[4] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[4]~4_combout ), - .asdata(\z80_|address_latch_|Q [4]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[4] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y18_N2 -cycloneive_lcell_comb \z80_|address_pins_|abus[4]~28 ( -// Equation(s): -// \z80_|address_pins_|abus[4]~28_combout = (\z80_|address_pins_|DFFE_apin_latch [4]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|address_pins_|DFFE_apin_latch [4]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[4]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[4]~28 .lut_mask = 16'hFF0F; -defparam \z80_|address_pins_|abus[4]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N12 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[5]~5 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[5]~5_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [5])) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|abusz [5]), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[5]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[5]~5 .lut_mask = 16'hEE44; -defparam \z80_|address_pins_|DFFE_apin_latch[5]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y16_N13 -dffeas \z80_|address_pins_|DFFE_apin_latch[5] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[5]~5_combout ), - .asdata(\z80_|address_latch_|Q [5]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[5] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N20 -cycloneive_lcell_comb \z80_|address_pins_|abus[5]~29 ( -// Equation(s): -// \z80_|address_pins_|abus[5]~29_combout = (\z80_|address_pins_|DFFE_apin_latch [5]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [5]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_pins_|abus[5]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[5]~29 .lut_mask = 16'hF3F3; -defparam \z80_|address_pins_|abus[5]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N10 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[6]~6 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[6]~6_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [6]))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [6])) - - .dataa(\z80_|address_latch_|abusz [6]), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), - .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[6]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[6]~6 .lut_mask = 16'hCCAA; -defparam \z80_|address_pins_|DFFE_apin_latch[6]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y16_N11 -dffeas \z80_|address_pins_|DFFE_apin_latch[6] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[6]~6_combout ), - .asdata(\z80_|address_latch_|Q [6]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[6] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y18_N28 -cycloneive_lcell_comb \z80_|address_pins_|abus[6]~30 ( -// Equation(s): -// \z80_|address_pins_|abus[6]~30_combout = (\z80_|address_pins_|DFFE_apin_latch [6]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|address_pins_|DFFE_apin_latch [6]), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_pins_|abus[6]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[6]~30 .lut_mask = 16'hCFCF; -defparam \z80_|address_pins_|abus[6]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N30 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[7]~7 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[7]~7_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [7])) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|abusz [7]), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[7]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[7]~7 .lut_mask = 16'hEE44; -defparam \z80_|address_pins_|DFFE_apin_latch[7]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y16_N31 -dffeas \z80_|address_pins_|DFFE_apin_latch[7] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[7]~7_combout ), - .asdata(\z80_|address_latch_|Q [7]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[7] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y18_N22 -cycloneive_lcell_comb \z80_|address_pins_|abus[7]~31 ( -// Equation(s): -// \z80_|address_pins_|abus[7]~31_combout = (\z80_|address_pins_|DFFE_apin_latch [7]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|address_pins_|DFFE_apin_latch [7]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[7]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[7]~31 .lut_mask = 16'hFF0F; -defparam \z80_|address_pins_|abus[7]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N20 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[8]~8 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[8]~8_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [8])) - - .dataa(\z80_|address_latch_|abusz [8]), - .datab(\z80_|execute_|ctl_apin_mux~2_combout ), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[8]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[8]~8 .lut_mask = 16'hEE22; -defparam \z80_|address_pins_|DFFE_apin_latch[8]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y16_N21 -dffeas \z80_|address_pins_|DFFE_apin_latch[8] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[8]~8_combout ), - .asdata(\z80_|address_latch_|Q [8]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [8]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[8] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N30 -cycloneive_lcell_comb \z80_|address_pins_|abus[8]~18 ( -// Equation(s): -// \z80_|address_pins_|abus[8]~18_combout = (\z80_|address_pins_|DFFE_apin_latch [8]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|address_pins_|DFFE_apin_latch [8]), - .datac(gnd), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\z80_|address_pins_|abus[8]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[8]~18 .lut_mask = 16'hCCFF; -defparam \z80_|address_pins_|abus[8]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N16 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[9]~9 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[9]~9_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [9]))) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [9]), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[9]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[9]~9 .lut_mask = 16'hDD88; -defparam \z80_|address_pins_|DFFE_apin_latch[9]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N17 -dffeas \z80_|address_pins_|DFFE_apin_latch[9] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[9]~9_combout ), - .asdata(\z80_|address_latch_|Q [9]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [9]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[9] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[9] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y18_N4 -cycloneive_lcell_comb \z80_|address_pins_|abus[9]~17 ( -// Equation(s): -// \z80_|address_pins_|abus[9]~17_combout = (\z80_|address_pins_|DFFE_apin_latch [9]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|address_pins_|DFFE_apin_latch [9]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[9]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[9]~17 .lut_mask = 16'hFF0F; -defparam \z80_|address_pins_|abus[9]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N24 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[10]~10 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[10]~10_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [10]))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), - .datab(\z80_|address_latch_|abusz [10]), - .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[10]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[10]~10 .lut_mask = 16'hAACC; -defparam \z80_|address_pins_|DFFE_apin_latch[10]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N25 -dffeas \z80_|address_pins_|DFFE_apin_latch[10] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[10]~10_combout ), - .asdata(\z80_|address_latch_|Q [10]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [10]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[10] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[10] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N24 -cycloneive_lcell_comb \z80_|address_pins_|abus[10]~24 ( -// Equation(s): -// \z80_|address_pins_|abus[10]~24_combout = (\z80_|address_pins_|DFFE_apin_latch [10]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|address_pins_|DFFE_apin_latch [10]), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\z80_|address_pins_|abus[10]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[10]~24 .lut_mask = 16'hF0FF; -defparam \z80_|address_pins_|abus[10]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N6 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[11]~11 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[11]~11_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|address [11])) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [11]))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), - .datab(\z80_|address_latch_|abusz [11]), - .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[11]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[11]~11 .lut_mask = 16'hAACC; -defparam \z80_|address_pins_|DFFE_apin_latch[11]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N7 -dffeas \z80_|address_pins_|DFFE_apin_latch[11] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[11]~11_combout ), - .asdata(\z80_|address_latch_|Q [11]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [11]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[11] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[11] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N8 -cycloneive_lcell_comb \z80_|address_pins_|abus[11]~19 ( -// Equation(s): -// \z80_|address_pins_|abus[11]~19_combout = (\z80_|address_pins_|DFFE_apin_latch [11]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [11]), - .datab(gnd), - .datac(gnd), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\z80_|address_pins_|abus[11]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[11]~19 .lut_mask = 16'hAAFF; -defparam \z80_|address_pins_|abus[11]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N16 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[12]~12 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[12]~12_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [12])) - - .dataa(\z80_|address_latch_|abusz [12]), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[12]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[12]~12 .lut_mask = 16'hCCAA; -defparam \z80_|address_pins_|DFFE_apin_latch[12]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N17 -dffeas \z80_|address_pins_|DFFE_apin_latch[12] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[12]~12_combout ), - .asdata(\z80_|address_latch_|Q [12]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [12]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[12] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[12] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y18_N30 -cycloneive_lcell_comb \z80_|address_pins_|abus[12]~21 ( -// Equation(s): -// \z80_|address_pins_|abus[12]~21_combout = (\z80_|address_pins_|DFFE_apin_latch [12]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_pins_|DFFE_apin_latch [12]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[12]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[12]~21 .lut_mask = 16'hFF55; -defparam \z80_|address_pins_|abus[12]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y11_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a14 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~101_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: FF_X32_Y14_N31 -dffeas \ram1|altsyncram_component|auto_generated|address_reg_a[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|address_pins_|abus[13]~20_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram1|altsyncram_component|auto_generated|address_reg_a [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true"; -defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X32_Y14_N1 -dffeas \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ram1|altsyncram_component|auto_generated|address_reg_a [0]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true"; -defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N12 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2] = (\ExtRamWE~0_combout & (!\z80_|address_pins_|abus[13]~20_combout & (!\z80_|address_pins_|abus[14]~23_combout & \z80_|address_pins_|abus[15]~22_combout ))) - - .dataa(\ExtRamWE~0_combout ), - .datab(\z80_|address_pins_|abus[13]~20_combout ), - .datac(\z80_|address_pins_|abus[14]~23_combout ), - .datad(\z80_|address_pins_|abus[15]~22_combout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] .lut_mask = 16'h0200; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N18 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (!\z80_|address_pins_|DFFE_apin_latch [13] & !\z80_|address_pins_|DFFE_apin_latch [14])) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [13]), - .datad(\z80_|address_pins_|DFFE_apin_latch [14]), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 .lut_mask = 16'h000C; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y10_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a6 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~101_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; -// synopsys translate_on - -// Location: FF_X29_Y14_N5 -dffeas \ram1|altsyncram_component|auto_generated|address_reg_a[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|address_pins_|abus[14]~23_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram1|altsyncram_component|auto_generated|address_reg_a [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1] .is_wysiwyg = "true"; -defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y14_N21 -dffeas \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ram1|altsyncram_component|auto_generated|address_reg_a [1]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] .is_wysiwyg = "true"; -defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N24 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2] = (\ExtRamWE~0_combout & (!\z80_|address_pins_|abus[13]~20_combout & (\z80_|address_pins_|abus[14]~23_combout & \z80_|address_pins_|abus[15]~22_combout ))) - - .dataa(\ExtRamWE~0_combout ), - .datab(\z80_|address_pins_|abus[13]~20_combout ), - .datac(\z80_|address_pins_|abus[14]~23_combout ), - .datad(\z80_|address_pins_|abus[15]~22_combout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] .lut_mask = 16'h2000; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N26 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (!\z80_|address_pins_|DFFE_apin_latch [13] & \z80_|address_pins_|DFFE_apin_latch [14])) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [13]), - .datad(\z80_|address_pins_|DFFE_apin_latch [14]), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 .lut_mask = 16'h0C00; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y10_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a22 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~101_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_first_bit_number = 6; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N10 -cycloneive_lcell_comb \D[6]~90 ( -// Equation(s): -// \D[6]~90_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ) # (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout & ((!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ), - .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .cin(gnd), - .combout(\D[6]~90_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~90 .lut_mask = 16'hCCE2; -defparam \D[6]~90 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N20 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2] = (\ExtRamWE~0_combout & (\z80_|address_pins_|abus[13]~20_combout & (\z80_|address_pins_|abus[14]~23_combout & \z80_|address_pins_|abus[15]~22_combout ))) - - .dataa(\ExtRamWE~0_combout ), - .datab(\z80_|address_pins_|abus[13]~20_combout ), - .datac(\z80_|address_pins_|abus[14]~23_combout ), - .datad(\z80_|address_pins_|abus[15]~22_combout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] .lut_mask = 16'h8000; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N6 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout = ((\z80_|address_pins_|DFFE_apin_latch [13] & \z80_|address_pins_|DFFE_apin_latch [14])) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [13]), - .datad(\z80_|address_pins_|DFFE_apin_latch [14]), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 .lut_mask = 16'hF333; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y6_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a30 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~101_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_first_bit_number = 6; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N16 -cycloneive_lcell_comb \D[6]~91 ( -// Equation(s): -// \D[6]~91_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[6]~90_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ))) # (!\D[6]~90_combout & -// (\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[6]~90_combout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\D[6]~90_combout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ), - .cin(gnd), - .combout(\D[6]~91_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~91 .lut_mask = 16'hF838; -defparam \D[6]~91 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N2 -cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0 ( -// Equation(s): -// \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout = (\ExtRamWE~0_combout & (!\z80_|address_pins_|abus[13]~20_combout & (\z80_|address_pins_|abus[14]~23_combout & !\z80_|address_pins_|abus[15]~22_combout ))) - - .dataa(\ExtRamWE~0_combout ), - .datab(\z80_|address_pins_|abus[13]~20_combout ), - .datac(\z80_|address_pins_|abus[14]~23_combout ), - .datad(\z80_|address_pins_|abus[15]~22_combout ), - .cin(gnd), - .combout(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0 .lut_mask = 16'h0020; -defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: CLKCTRL_G15 -cycloneive_clkctrl \CLOCK_50~inputclkctrl ( - .ena(vcc), - .inclk({vcc,vcc,vcc,\CLOCK_50~input_o }), - .clkselect(2'b00), - .devclrn(devclrn), - .devpor(devpor), - .outclk(\CLOCK_50~inputclkctrl_outclk )); -// synopsys translate_off -defparam \CLOCK_50~inputclkctrl .clock_type = "global clock"; -defparam \CLOCK_50~inputclkctrl .ena_register_mode = "none"; -// synopsys translate_on - -// Location: LCCOMB_X5_Y24_N16 -cycloneive_lcell_comb \~GND ( -// Equation(s): -// \~GND~combout = GND - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(gnd), - .cin(gnd), - .combout(\~GND~combout ), - .cout()); -// synopsys translate_off -defparam \~GND .lut_mask = 16'h0000; -defparam \~GND .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N20 -cycloneive_lcell_comb \ula_|video_|vram_address[0]~feeder ( -// Equation(s): -// \ula_|video_|vram_address[0]~feeder_combout = \ula_|video_|vga_hc [4] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|vga_hc [4]), - .cin(gnd), - .combout(\ula_|video_|vram_address[0]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address[0]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|vram_address[0]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N4 -cycloneive_lcell_comb \ula_|video_|vram_address~0 ( -// Equation(s): -// \ula_|video_|vram_address~0_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [2] $ (\ula_|video_|vga_hc [1])))) - - .dataa(\ula_|video_|vga_hc [2]), - .datab(\ula_|video_|vga_hc [3]), - .datac(\ula_|video_|vga_hc [1]), - .datad(\ula_|video_|vga_hc [0]), - .cin(gnd), - .combout(\ula_|video_|vram_address~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address~0 .lut_mask = 16'h0048; -defparam \ula_|video_|vram_address~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y33_N21 -dffeas \ula_|video_|vram_address[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vram_address[0]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[0] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X34_Y33_N19 -dffeas \ula_|video_|vram_address[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|vga_hc [5]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[1] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N0 -cycloneive_lcell_comb \ula_|video_|vram_address[2]~4 ( -// Equation(s): -// \ula_|video_|vram_address[2]~4_combout = !\ula_|video_|vga_hc [6] - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|video_|vga_hc [6]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|video_|vram_address[2]~4_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address[2]~4 .lut_mask = 16'h0F0F; -defparam \ula_|video_|vram_address[2]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y33_N1 -dffeas \ula_|video_|vram_address[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vram_address[2]~4_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[2] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N26 -cycloneive_lcell_comb \ula_|video_|Add3~0 ( -// Equation(s): -// \ula_|video_|Add3~0_combout = \ula_|video_|vga_hc [6] $ (\ula_|video_|vga_hc [7]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|video_|vga_hc [6]), - .datad(\ula_|video_|vga_hc [7]), - .cin(gnd), - .combout(\ula_|video_|Add3~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Add3~0 .lut_mask = 16'h0FF0; -defparam \ula_|video_|Add3~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y33_N27 -dffeas \ula_|video_|vram_address[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Add3~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[3] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N28 -cycloneive_lcell_comb \ula_|video_|Add3~1 ( -// Equation(s): -// \ula_|video_|Add3~1_combout = \ula_|video_|vga_hc [8] $ (((!\ula_|video_|vga_hc [7]) # (!\ula_|video_|vga_hc [6]))) - - .dataa(\ula_|video_|vga_hc [6]), - .datab(gnd), - .datac(\ula_|video_|vga_hc [8]), - .datad(\ula_|video_|vga_hc [7]), - .cin(gnd), - .combout(\ula_|video_|Add3~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Add3~1 .lut_mask = 16'hA50F; -defparam \ula_|video_|Add3~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y33_N29 -dffeas \ula_|video_|vram_address[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Add3~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[4] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N2 -cycloneive_lcell_comb \ula_|video_|Add4~0 ( -// Equation(s): -// \ula_|video_|Add4~0_combout = (\ula_|video_|vga_vc [0] & (\ula_|video_|vga_vc [1] $ (VCC))) # (!\ula_|video_|vga_vc [0] & (\ula_|video_|vga_vc [1] & VCC)) -// \ula_|video_|Add4~1 = CARRY((\ula_|video_|vga_vc [0] & \ula_|video_|vga_vc [1])) - - .dataa(\ula_|video_|vga_vc [0]), - .datab(\ula_|video_|vga_vc [1]), - .datac(gnd), - .datad(vcc), - .cin(gnd), - .combout(\ula_|video_|Add4~0_combout ), - .cout(\ula_|video_|Add4~1 )); -// synopsys translate_off -defparam \ula_|video_|Add4~0 .lut_mask = 16'h6688; -defparam \ula_|video_|Add4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N4 -cycloneive_lcell_comb \ula_|video_|Add4~2 ( -// Equation(s): -// \ula_|video_|Add4~2_combout = (\ula_|video_|vga_vc [2] & (\ula_|video_|Add4~1 & VCC)) # (!\ula_|video_|vga_vc [2] & (!\ula_|video_|Add4~1 )) -// \ula_|video_|Add4~3 = CARRY((!\ula_|video_|vga_vc [2] & !\ula_|video_|Add4~1 )) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [2]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~1 ), - .combout(\ula_|video_|Add4~2_combout ), - .cout(\ula_|video_|Add4~3 )); -// synopsys translate_off -defparam \ula_|video_|Add4~2 .lut_mask = 16'hC303; -defparam \ula_|video_|Add4~2 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N6 -cycloneive_lcell_comb \ula_|video_|Add4~4 ( -// Equation(s): -// \ula_|video_|Add4~4_combout = (\ula_|video_|vga_vc [3] & ((GND) # (!\ula_|video_|Add4~3 ))) # (!\ula_|video_|vga_vc [3] & (\ula_|video_|Add4~3 $ (GND))) -// \ula_|video_|Add4~5 = CARRY((\ula_|video_|vga_vc [3]) # (!\ula_|video_|Add4~3 )) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [3]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~3 ), - .combout(\ula_|video_|Add4~4_combout ), - .cout(\ula_|video_|Add4~5 )); -// synopsys translate_off -defparam \ula_|video_|Add4~4 .lut_mask = 16'h3CCF; -defparam \ula_|video_|Add4~4 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N8 -cycloneive_lcell_comb \ula_|video_|Add4~6 ( -// Equation(s): -// \ula_|video_|Add4~6_combout = (\ula_|video_|vga_vc [4] & (!\ula_|video_|Add4~5 )) # (!\ula_|video_|vga_vc [4] & ((\ula_|video_|Add4~5 ) # (GND))) -// \ula_|video_|Add4~7 = CARRY((!\ula_|video_|Add4~5 ) # (!\ula_|video_|vga_vc [4])) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [4]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~5 ), - .combout(\ula_|video_|Add4~6_combout ), - .cout(\ula_|video_|Add4~7 )); -// synopsys translate_off -defparam \ula_|video_|Add4~6 .lut_mask = 16'h3C3F; -defparam \ula_|video_|Add4~6 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X34_Y33_N9 -dffeas \ula_|video_|vram_address[5] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Add4~6_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[5] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N10 -cycloneive_lcell_comb \ula_|video_|Add4~8 ( -// Equation(s): -// \ula_|video_|Add4~8_combout = (\ula_|video_|vga_vc [5] & ((GND) # (!\ula_|video_|Add4~7 ))) # (!\ula_|video_|vga_vc [5] & (\ula_|video_|Add4~7 $ (GND))) -// \ula_|video_|Add4~9 = CARRY((\ula_|video_|vga_vc [5]) # (!\ula_|video_|Add4~7 )) - - .dataa(\ula_|video_|vga_vc [5]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~7 ), - .combout(\ula_|video_|Add4~8_combout ), - .cout(\ula_|video_|Add4~9 )); -// synopsys translate_off -defparam \ula_|video_|Add4~8 .lut_mask = 16'h5AAF; -defparam \ula_|video_|Add4~8 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X34_Y33_N11 -dffeas \ula_|video_|vram_address[6] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Add4~8_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[6] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N12 -cycloneive_lcell_comb \ula_|video_|Add4~10 ( -// Equation(s): -// \ula_|video_|Add4~10_combout = (\ula_|video_|vga_vc [6] & (!\ula_|video_|Add4~9 )) # (!\ula_|video_|vga_vc [6] & ((\ula_|video_|Add4~9 ) # (GND))) -// \ula_|video_|Add4~11 = CARRY((!\ula_|video_|Add4~9 ) # (!\ula_|video_|vga_vc [6])) - - .dataa(\ula_|video_|vga_vc [6]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~9 ), - .combout(\ula_|video_|Add4~10_combout ), - .cout(\ula_|video_|Add4~11 )); -// synopsys translate_off -defparam \ula_|video_|Add4~10 .lut_mask = 16'h5A5F; -defparam \ula_|video_|Add4~10 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X34_Y33_N13 -dffeas \ula_|video_|vram_address[7] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Add4~10_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[7] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N14 -cycloneive_lcell_comb \ula_|video_|Add4~12 ( -// Equation(s): -// \ula_|video_|Add4~12_combout = (\ula_|video_|vga_vc [7] & ((GND) # (!\ula_|video_|Add4~11 ))) # (!\ula_|video_|vga_vc [7] & (\ula_|video_|Add4~11 $ (GND))) -// \ula_|video_|Add4~13 = CARRY((\ula_|video_|vga_vc [7]) # (!\ula_|video_|Add4~11 )) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [7]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~11 ), - .combout(\ula_|video_|Add4~12_combout ), - .cout(\ula_|video_|Add4~13 )); -// synopsys translate_off -defparam \ula_|video_|Add4~12 .lut_mask = 16'h3CCF; -defparam \ula_|video_|Add4~12 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N22 -cycloneive_lcell_comb \ula_|video_|Selector6~0 ( -// Equation(s): -// \ula_|video_|Selector6~0_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|Add4~12_combout )) # (!\ula_|video_|vga_hc [2] & ((\ula_|video_|Add4~0_combout ))) - - .dataa(gnd), - .datab(\ula_|video_|Add4~12_combout ), - .datac(\ula_|video_|Add4~0_combout ), - .datad(\ula_|video_|vga_hc [2]), - .cin(gnd), - .combout(\ula_|video_|Selector6~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Selector6~0 .lut_mask = 16'hCCF0; -defparam \ula_|video_|Selector6~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N14 -cycloneive_lcell_comb \ula_|video_|vram_address[9]~1 ( -// Equation(s): -// \ula_|video_|vram_address[9]~1_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [2] $ (\ula_|video_|vga_hc [1])))) - - .dataa(\ula_|video_|vga_hc [2]), - .datab(\ula_|video_|vga_hc [3]), - .datac(\ula_|video_|vga_hc [1]), - .datad(\ula_|video_|vga_hc [0]), - .cin(gnd), - .combout(\ula_|video_|vram_address[9]~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address[9]~1 .lut_mask = 16'h0048; -defparam \ula_|video_|vram_address[9]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y31_N23 -dffeas \ula_|video_|vram_address[8] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Selector6~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address[9]~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [8]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[8] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N16 -cycloneive_lcell_comb \ula_|video_|Add4~14 ( -// Equation(s): -// \ula_|video_|Add4~14_combout = \ula_|video_|Add4~13 $ (!\ula_|video_|vga_vc [8]) - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|vga_vc [8]), - .cin(\ula_|video_|Add4~13 ), - .combout(\ula_|video_|Add4~14_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Add4~14 .lut_mask = 16'hF00F; -defparam \ula_|video_|Add4~14 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N20 -cycloneive_lcell_comb \ula_|video_|Selector5~0 ( -// Equation(s): -// \ula_|video_|Selector5~0_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|Add4~14_combout )) # (!\ula_|video_|vga_hc [2] & ((\ula_|video_|Add4~2_combout ))) - - .dataa(\ula_|video_|Add4~14_combout ), - .datab(gnd), - .datac(\ula_|video_|Add4~2_combout ), - .datad(\ula_|video_|vga_hc [2]), - .cin(gnd), - .combout(\ula_|video_|Selector5~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Selector5~0 .lut_mask = 16'hAAF0; -defparam \ula_|video_|Selector5~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y31_N21 -dffeas \ula_|video_|vram_address[9] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Selector5~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address[9]~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [9]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[9] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[9] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N28 -cycloneive_lcell_comb \ula_|video_|vram_address[10]~2 ( -// Equation(s): -// \ula_|video_|vram_address[10]~2_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [2] $ (\ula_|video_|vga_hc [1])))) - - .dataa(\ula_|video_|vga_hc [2]), - .datab(\ula_|video_|vga_hc [3]), - .datac(\ula_|video_|vga_hc [1]), - .datad(\ula_|video_|vga_hc [0]), - .cin(gnd), - .combout(\ula_|video_|vram_address[10]~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address[10]~2 .lut_mask = 16'h0048; -defparam \ula_|video_|vram_address[10]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N30 -cycloneive_lcell_comb \ula_|video_|vram_address[10]~3 ( -// Equation(s): -// \ula_|video_|vram_address[10]~3_combout = (\ula_|video_|vram_address[10]~2_combout & (\ula_|video_|Add4~4_combout & (\ula_|video_|vga_hc [1]))) # (!\ula_|video_|vram_address[10]~2_combout & (((\ula_|video_|vram_address [10])))) - - .dataa(\ula_|video_|Add4~4_combout ), - .datab(\ula_|video_|vga_hc [1]), - .datac(\ula_|video_|vram_address [10]), - .datad(\ula_|video_|vram_address[10]~2_combout ), - .cin(gnd), - .combout(\ula_|video_|vram_address[10]~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address[10]~3 .lut_mask = 16'h88F0; -defparam \ula_|video_|vram_address[10]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y31_N31 -dffeas \ula_|video_|vram_address[10] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vram_address[10]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [10]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[10] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[10] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N16 -cycloneive_lcell_comb \ula_|video_|Selector3~0 ( -// Equation(s): -// \ula_|video_|Selector3~0_combout = (\ula_|video_|Add4~12_combout ) # (\ula_|video_|vga_hc [2]) - - .dataa(gnd), - .datab(\ula_|video_|Add4~12_combout ), - .datac(gnd), - .datad(\ula_|video_|vga_hc [2]), - .cin(gnd), - .combout(\ula_|video_|Selector3~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Selector3~0 .lut_mask = 16'hFFCC; -defparam \ula_|video_|Selector3~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y31_N17 -dffeas \ula_|video_|vram_address[11] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Selector3~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address[9]~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [11]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[11] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[11] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N26 -cycloneive_lcell_comb \ula_|video_|Selector2~0 ( -// Equation(s): -// \ula_|video_|Selector2~0_combout = (\ula_|video_|Add4~14_combout ) # (\ula_|video_|vga_hc [2]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|video_|Add4~14_combout ), - .datad(\ula_|video_|vga_hc [2]), - .cin(gnd), - .combout(\ula_|video_|Selector2~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Selector2~0 .lut_mask = 16'hFFF0; -defparam \ula_|video_|Selector2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y31_N27 -dffeas \ula_|video_|vram_address[12] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Selector2~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address[9]~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [12]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[12] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[12] .power_up = "low"; -// synopsys translate_on - -// Location: M9K_X33_Y27_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a6 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~101_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_first_bit_number = 6; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFFFFFEBFFFFFFFFFFFFFFFFFFFFFFFBFFFFFFFFFFFFFFFFFDFFFFFFFFFFFFFBFFFFFFFFFEFFFFFFFDFFFFFFFFFFFFFEFFFFFFFDF8FFFFFFF9FFFFFFFFFFFFFFFF3FFFFFFE7FFFFFFFFFFFFFFFF; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000380001887600094C977486989000000000000000000000000FFFFFFFFC0810205C00018C36DC09CF97749EDCD00000000000000000000000000000001FFFFFFFDC004000B6D028BF17749ED8100000000000000000000000000000001BF7EFDF9400404A96D8289B57549FFC10000000000000000000000003F7EFDF90000000140041EB16D8298357DC9F7410000000000000000000000007FFFFFFD8000000340043AB160021E757DC9134100000000000000000000000040810207BFFFFFFF5FE430497702760D60099349000000000000000000000000408102073FFFFFFD5FE40E49774240C96009735D; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h5FE8334948F827C15FF88F8169A80ECB609EAD417A698FC178F33E8171F72A915FE836E948F807C95FF88F81E9A80FC7639E1FC17B2BBEC170730F8D70F7B0C1400826E548B807C95FF88F95E8280FCB63C6BCC17B3B3FC171AB3E81708734C1400826ED58F8258159F88B8168280FC161629DC17A3B3F41738B3F8150AF16E9400826ED581805C151D88A8160682FC1422297C17A2A39C162FB378550CF10A1400826ED58182581D1580B8761EC2FC14232B7C179AA39C5627B7781D0CF10D3400826E158182D81F0488A4B61EC0DC143789FC17BBB39C1610B7F81D45F11D34008A7E958080D01F0088A4160B42DD143689FC17B9B398561837F81D41702B1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h50DF086350368F0151C688016801460157EDE81148F310013FFFFFFF40810103D2D70D4B50168F0141D6C8116C01462153EDA90148F31D01BFFFFFFF40810107D2D7296354D68501403EC0016C01482173FDA08148F11F01800000037FFFFFFD4297893154DE81054022D2116C014D6153FCA00148D10F01000000013F7EFEF9429F810150CEC10143E042016C014C09537DA00148D11F01BF7EFEF900000001469F833150168D0543E04A116F014DA15379B181C8511F03FFFFFFFD00000001449AAB2155368D01482046016F416CA15079B001C8513E03C0810105FFFFFFFF403A8B0155C685014800461167476CA15039B08180413E0500000007FFFFFFFF; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N22 -cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder ( -// Equation(s): -// \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout = \z80_|address_pins_|abus[13]~20_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_pins_|abus[13]~20_combout ), - .cin(gnd), - .combout(\ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder .lut_mask = 16'hFF00; -defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y14_N23 -dffeas \ram0|altsyncram_component|auto_generated|address_reg_a[0] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram0|altsyncram_component|auto_generated|address_reg_a [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true"; -defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y14_N1 -dffeas \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(gnd), - .asdata(\ram0|altsyncram_component|auto_generated|address_reg_a [0]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true"; -defparam \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N10 -cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1 ( -// Equation(s): -// \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout = (\ExtRamWE~0_combout & (\z80_|address_pins_|abus[13]~20_combout & (\z80_|address_pins_|abus[14]~23_combout & !\z80_|address_pins_|abus[15]~22_combout ))) - - .dataa(\ExtRamWE~0_combout ), - .datab(\z80_|address_pins_|abus[13]~20_combout ), - .datac(\z80_|address_pins_|abus[14]~23_combout ), - .datad(\z80_|address_pins_|abus[15]~22_combout ), - .cin(gnd), - .combout(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .cout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1 .lut_mask = 16'h0080; -defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y25_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a14 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(gnd), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~101_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_first_bit_number = 6; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y33_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a14 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h4200420000441C443C0C3C00480018FC387C7C000000007E180038300000204880084204004204423E1E3E02247E3C7E3C7E7E7E7E30007E3C7E7E7E3C7E7C3C0400000000000C34023C2E302464003C00000000000000000020460024000000FF991E65536D2D8D9C9B4DB081C83A5A881B0DFDE2D72DF0FA08FCD6F664173D989098D02025E0F6043B4B9080F4923880C3A3B02D269E730C3DCC423386DCB98B4AD0C5C8D6119602E5121008325B7457090E914F4876EC8A18C664210A4C2392C7658400073421047C75FBE7BE73FDFFF05FEE07BF8AEF7F1378B359E8C61F8F692C2218C98A4A8748531986E7C770D984E0000C02060C000C0DF50F68A580; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h0100046606572583002086010800054C0F2DE8371AC0000A9003E024840C7C0806F6612D770080980A40D293FEC069F16CB2164CA033C539F69B37741AEF1CE3662FF5DF9CB107BB23A39EF7B95E7372200448DBDC18F9C0DE0EF379BF49480657781E91788044213E091339886F337D0612CA646CD48FC58EE77EDD7ECEC466C744FD00E1A7F9E9FBFE4777FD50ABD11F0E57FF4808802282200888A20AA88000000008800AC11D556264251ECFA68C056FBCCB040C614A6850222300D2F6FF59F878FCF5689FCFEF34BFD52FA2422A56A3C113409F7813007F8D6B5F80FE9D7FB1E62675F7C2CBE01032DCA16BADC570C1CBF7ECBC4E7E6C54A5D4550BE1A8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'hE33CB578DEBFAFAEDFD530DE8FA1992072F31B116644B18C72F9F44116C79ADF2F3982C7BE09AD4A32196807648A2495ADF98FD2B16CC096A5E25F5BC811C953CEC3000F432029B3FE3F211712944CA54D1940F193204C199C9F49666CC11B38C23B9D130CA49818913D3A2C1FBF71C5B0C774336F903C677D976189D98CA127AAAD6B6AF36195DA637C6EFA3E36E8FE97FA02EC26EB46198AD8DAD8C11260AF499D7BD86619EE5574CD27C80D39F71E653FDCF1B366737233CBB98D1E7B330F7DCCFC5939C4EC79CF0E1CD43BA7AFC716900A21BDB9DD0FCC7ECE1063238407C7E1B221EA10E38F64EF31CEBF3368E1C712BB1B33781134CFE54C2123349A6E; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h5F9CB25A3631964C20007FF5754FC631A97D4F93986C30CF24394625658DE9A7C228A2050470925E29A35D8D06242712CD25C9241898204D85A710947C802013E1265727652C8F0C422BA8C28A0FBB893B0881E00403DDD8843B2D8EB929D0D8CB76E03779E019E2C4E4028219C38C202C9384E0D24E569C2E4D4D60B670CE37414D536A41D144B6C4624A2B00366D8CF6734A4A2DC465B308462CCBD1BF9CB863FC93EDB2CA5DC61B01639318985C88F01680E307C42311C0124700B28BF9B4FF7CCCEFE1996DE3ED6D8CFBF1871BD98EE7646242664EB2E338BD009838637124C921BB3332DC66D9C1706B6C48C3129639A3BA4088EDB496EDBBBFC2CC40B6; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N2 -cycloneive_lcell_comb \D[6]~87 ( -// Equation(s): -// \D[6]~87_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))) # (!\z80_|address_pins_|abus[14]~23_combout -// & (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout )))) - - .dataa(\z80_|address_pins_|abus[14]~23_combout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout ), - .datad(\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ), - .cin(gnd), - .combout(\D[6]~87_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~87 .lut_mask = 16'hE6A2; -defparam \D[6]~87 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y1_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a6 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h3C766E63DB6481CB39BC8C68831C724633186CC1BAE9D608A5DEF0FF219C28C1EFF4FDE394D0E19B6FD89186C23CF071E6F1CC8F7FC4F1E48756B0DCD8ED6D0C3DA139003D7A86B2F878DD99DAFB70DE1A19F3FB7DB3B8EF2633007664CB19992E43664448EFF06072648DBA32EDB76E26439BCCEF2DFBF664594B04FBAE72A84A3E508B49DC6BEAAB4F3F0CCCF6D8F568F2DA00EB384A7F53249323198000100408002024010408824080002008011482ED5615E40012EE630C3B2CDB2C13A736DB5B7BD2850018CF936621C6863095A73F7BE7442CB13110B9C0BBB96EEF16CE618EEDCFB393738178C476C367909F71307F6803F677575763DB2D8C3118E4; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h881331ED7AC4EFD38DFACDBB236790005719AEA2FAECCF0D126A30A27222D61BBA428334561F4EDB60C6BF8DB6E267BC56CB69BBCE636CCCB3B2B4B103CC46D5CEEC06DAECB0001569589D5F267AFE086C8FED5DE41DFEFF027DFDFF7FFBFBFDFFDFFF6FFFBDFFDFFF57FF7F7FB7FBBDFBDFFDBFF78FFDBFFEDDFFFDFFFEFF6FF7F7FDDFFEDFF6FF7FFEEFFEFEFC4E51EC0888848E1F2044B47B66608D8A3B3919B9466E6D60D27565964244B218B48AD83430D996068EC908D9E112096996041D77401A0C0CCF5DEEE561F7F7E68CBE72E48E570B047C772CBACC33753080E32EB0B348C0B62337739B1BC73192392592C84E37B7AC141CFE65EE76D83C9083; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h1C5CF062CA6F13854A59BDEEEA07E3C6559EBB3618111895CBBACCBCD512B5F07D361CCE72B925658DBE1F7C4707E195C5C665B8118C3C31B196C261DA85A5E11889D25CB816ACC6627802052C61A4099B7B0EC923971DB3B9F9204BDBCCFA457EE296E8986E64C6DC99E59436641567648CB84DEB7D7937F974F038D838274F3D3CF1BE8C84DDB000565880A776E5C0E13166E49F47119A4CA1311CF97B965E7CBBCB2CB384BD0D92ED105D0617856E80441124B31DE58B8C001607FEE668899693E3EFF8FBF1FCEEFBCF7CF9BA6C37640DDF7FFE6187B19ACF089D4C038F6607B78D38001FE67E56CCE399DE36D7DDBD699D5CFC5B6D7A1421CE06FE40DB6E; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h0776C62C316FF94B0BC3A0288DE6A62B14D6C1A2DADF9BDF85B2CCB02CE1DB2D96632C3232C3974CDC1172E1779D8C6738251819975DB8146067301E0C0277B6B657485DCD62AC0662C8C005DDE7494C9CA13AAE3234BB0EE1B708A23A2F48AC4C3838641E940620F9CDDCCA14BCC07104C112BCC9032C48E925594CB886A604C9F7627EB100872A52FB5141D65111E6C8DA0ADB6CEC6004461D0E366B20DCCDB607E624499300E4DF6D95CB62F62FB75403E400EFBC3BD34080FC9CDCFCFCFFFFFFFFFFFFFFFFFFFFF7BFFFFFFFFFFFFFFFFFFFFFFFFFFFCF9FFFFFEFFFF81FFDDFFFFFFFFFFFFFF7FFBFFFBFDC0A6DBE6F8BE5BB7FE7A39B3DA3F3BE13B679; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N6 -cycloneive_lcell_comb \D[6]~88 ( -// Equation(s): -// \D[6]~88_combout = (\z80_|address_pins_|abus[15]~22_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout $ (((\D[6]~87_combout ))))) # (!\z80_|address_pins_|abus[15]~22_combout & -// (((\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout & !\D[6]~87_combout )))) - - .dataa(\z80_|address_pins_|abus[15]~22_combout ), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ), - .datad(\D[6]~87_combout ), - .cin(gnd), - .combout(\D[6]~88_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~88 .lut_mask = 16'h22D8; -defparam \D[6]~88 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N20 -cycloneive_lcell_comb \D[6]~89 ( -// Equation(s): -// \D[6]~89_combout = (\D[6]~87_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout & !\D[6]~88_combout )))) # (!\D[6]~87_combout & -// (((!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & \D[6]~88_combout )))) - - .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ), - .datab(\D[6]~87_combout ), - .datac(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datad(\D[6]~88_combout ), - .cin(gnd), - .combout(\D[6]~89_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~89 .lut_mask = 16'hC3C8; -defparam \D[6]~89 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N14 -cycloneive_lcell_comb \D[6]~111 ( -// Equation(s): -// \D[6]~111_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [15] & (\D[6]~91_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\D[6]~89_combout ))))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & -// (\D[6]~91_combout )) - - .dataa(\D[6]~91_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [15]), - .datad(\D[6]~89_combout ), - .cin(gnd), - .combout(\D[6]~111_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~111 .lut_mask = 16'hAEA2; -defparam \D[6]~111 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: IOIBUF_X16_Y34_N8 -cycloneive_io_ibuf \raw_loader_in~input ( - .i(raw_loader_in), - .ibar(gnd), - .o(\raw_loader_in~input_o )); -// synopsys translate_off -defparam \raw_loader_in~input .bus_hold = "false"; -defparam \raw_loader_in~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N18 -cycloneive_lcell_comb \D[6]~86 ( -// Equation(s): -// \D[6]~86_combout = (\z80_|address_pins_|DFFE_apin_latch [0]) # ((\raw_loader_in~input_o ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [0]), - .datab(gnd), - .datac(\raw_loader_in~input_o ), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\D[6]~86_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~86 .lut_mask = 16'hFAFF; -defparam \D[6]~86 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N28 -cycloneive_lcell_comb \D[6]~100 ( -// Equation(s): -// \D[6]~100_combout = ((\Equal2~0_combout & ((\D[6]~86_combout ))) # (!\Equal2~0_combout & (\D[6]~111_combout ))) # (!\Equal2~1_combout ) - - .dataa(\Equal2~1_combout ), - .datab(\Equal2~0_combout ), - .datac(\D[6]~111_combout ), - .datad(\D[6]~86_combout ), - .cin(gnd), - .combout(\D[6]~100_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~100 .lut_mask = 16'hFD75; -defparam \D[6]~100 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N4 -cycloneive_lcell_comb \D[6]~101 ( -// Equation(s): -// \D[6]~101_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\z80_|data_pins_|dout [6] & \D[6]~100_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\D[6]~100_combout )) # (!\Equal2~1_combout ))) - - .dataa(\Equal2~1_combout ), - .datab(\z80_|data_pins_|dout [6]), - .datac(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datad(\D[6]~100_combout ), - .cin(gnd), - .combout(\D[6]~101_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~101 .lut_mask = 16'hCF05; -defparam \D[6]~101 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N12 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [6] = (\z80_|pin_control_|bus_db_pin_re~combout & ((\D[6]~101_combout ) # ((\z80_|execute_|ctl_bus_db_we~7_combout & \z80_|bus_control_|db[6]~9_combout )))) # (!\z80_|pin_control_|bus_db_pin_re~combout & -// (((\z80_|execute_|ctl_bus_db_we~7_combout & \z80_|bus_control_|db[6]~9_combout )))) - - .dataa(\z80_|pin_control_|bus_db_pin_re~combout ), - .datab(\D[6]~101_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|bus_control_|db[6]~9_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [6]), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] .lut_mask = 16'hF888; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N10 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_re~2 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_re~2_combout = (\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & ((\z80_|execute_|fIORead~3_combout )))) # (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # -// ((\z80_|sequencer_|DFFE_T3_ff~q & \z80_|execute_|fIORead~3_combout )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|execute_|fIORead~3_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_re~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_re~2 .lut_mask = 16'hDC50; -defparam \z80_|pin_control_|bus_db_pin_re~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N16 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_2 ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_2~combout = (\z80_|execute_|ctl_bus_db_we~7_combout ) # ((\z80_|pin_control_|bus_db_pin_re~2_combout ) # ((\z80_|execute_|fMRead~35_combout & \z80_|sequencer_|DFFE_T2_ff~q ))) - - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(\z80_|execute_|fMRead~35_combout ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|pin_control_|bus_db_pin_re~2_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_2 .lut_mask = 16'hFFEA; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y13_N13 -dffeas \z80_|data_pins_|dout[6] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [6]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|data_pins_|dout [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|data_pins_|dout[6] .is_wysiwyg = "true"; -defparam \z80_|data_pins_|dout[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N16 -cycloneive_lcell_comb \z80_|bus_control_|db[6]~9 ( -// Equation(s): -// \z80_|bus_control_|db[6]~9_combout = ((\z80_|bus_control_|db[6]~8_combout & ((\z80_|data_pins_|dout [6]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - - .dataa(\z80_|bus_control_|db[6]~8_combout ), - .datab(\z80_|data_pins_|dout [6]), - .datac(\z80_|execute_|ctl_bus_db_oe~combout ), - .datad(\z80_|bus_control_|db[0]~6_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[6]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[6]~9 .lut_mask = 16'h8AFF; -defparam \z80_|bus_control_|db[6]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N8 -cycloneive_lcell_comb \z80_|ir_|opcode[6]~feeder ( -// Equation(s): -// \z80_|ir_|opcode[6]~feeder_combout = \z80_|bus_control_|db[6]~9_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|bus_control_|db[6]~9_combout ), - .cin(gnd), - .combout(\z80_|ir_|opcode[6]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|ir_|opcode[6]~feeder .lut_mask = 16'hFF00; -defparam \z80_|ir_|opcode[6]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~13 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~13_combout = ((\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_ir_we~5_combout ) # (\z80_|pla_decode_|Equal41~2_combout )))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) - - .dataa(\z80_|execute_|ctl_ir_we~5_combout ), - .datab(\z80_|pla_decode_|Equal41~2_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~13 .lut_mask = 16'hE0FF; -defparam \z80_|execute_|ctl_ir_we~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y12_N9 -dffeas \z80_|ir_|opcode[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|ir_|opcode[6]~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|ir_|opcode [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|ir_|opcode[6] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal41~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal41~0_combout = (\z80_|ir_|opcode [7] & \z80_|ir_|opcode [6]) - - .dataa(gnd), - .datab(gnd), + .dataa(\z80_|decode_state_|DFFE_instCB~q ), + .datab(\z80_|decode_state_|DFFE_instED~q ), .datac(\z80_|ir_|opcode [7]), .datad(\z80_|ir_|opcode [6]), .cin(gnd), - .combout(\z80_|pla_decode_|Equal41~0_combout ), + .combout(\z80_|pla_decode_|Equal44~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal41~0 .lut_mask = 16'hF000; -defparam \z80_|pla_decode_|Equal41~0 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal44~0 .lut_mask = 16'h0010; +defparam \z80_|pla_decode_|Equal44~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y16_N22 -cycloneive_lcell_comb \z80_|pla_decode_|Equal41~1 ( +// Location: LCCOMB_X25_Y16_N20 +cycloneive_lcell_comb \z80_|execute_|ixy_d~16 ( // Equation(s): -// \z80_|pla_decode_|Equal41~1_combout = (!\z80_|ir_|opcode [2] & (\z80_|ir_|opcode [1] & (\z80_|ir_|opcode [0] & !\z80_|ir_|opcode [5]))) +// \z80_|execute_|ixy_d~16_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal44~0_combout & ((\z80_|decode_state_|DFFE_instIY1~q ) # (\z80_|decode_state_|DFFE_inst4~q )))) - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|ir_|opcode [1]), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|ir_|opcode [5]), + .dataa(\z80_|decode_state_|DFFE_instIY1~q ), + .datab(\z80_|decode_state_|DFFE_inst4~q ), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|pla_decode_|Equal44~0_combout ), .cin(gnd), - .combout(\z80_|pla_decode_|Equal41~1_combout ), + .combout(\z80_|execute_|ixy_d~16_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal41~1 .lut_mask = 16'h0040; -defparam \z80_|pla_decode_|Equal41~1 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ixy_d~16 .lut_mask = 16'hE000; +defparam \z80_|execute_|ixy_d~16 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y16_N24 -cycloneive_lcell_comb \z80_|pla_decode_|Equal41~2 ( +// Location: LCCOMB_X23_Y13_N24 +cycloneive_lcell_comb \z80_|pla_decode_|Equal3~1 ( // Equation(s): -// \z80_|pla_decode_|Equal41~2_combout = (\z80_|pla_decode_|Equal41~0_combout & (\z80_|pla_decode_|Equal32~0_combout & (\z80_|pla_decode_|Equal41~1_combout & \z80_|decode_state_|use_ixiy~combout ))) - - .dataa(\z80_|pla_decode_|Equal41~0_combout ), - .datab(\z80_|pla_decode_|Equal32~0_combout ), - .datac(\z80_|pla_decode_|Equal41~1_combout ), - .datad(\z80_|decode_state_|use_ixiy~combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal41~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal41~2 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal41~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~combout = (\z80_|execute_|ctl_alu_bs_oe~11_combout ) # ((\z80_|sequencer_|DFFE_M4_ff~q & (\z80_|pla_decode_|Equal41~2_combout & !\z80_|sequencer_|DFFE_T1_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|pla_decode_|Equal41~2_combout ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|execute_|ctl_alu_bs_oe~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe .lut_mask = 16'hFF08; -defparam \z80_|execute_|ctl_alu_bs_oe .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N2 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~15 ( -// Equation(s): -// \z80_|alu_|db_high[1]~15_combout = ((!\z80_|bus_control_|db[4]~19_combout & (\z80_|bus_control_|db[5]~15_combout & \z80_|bus_control_|db[3]~21_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datab(\z80_|bus_control_|db[4]~19_combout ), - .datac(\z80_|bus_control_|db[5]~15_combout ), - .datad(\z80_|bus_control_|db[3]~21_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~15 .lut_mask = 16'h7555; -defparam \z80_|alu_|db_high[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N10 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~16 ( -// Equation(s): -// \z80_|alu_|db_high[1]~16_combout = (\z80_|alu_|op1_high [1] & (((\z80_|alu_|op2_high [1]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|alu_|op1_high [1] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_high [1]) # -// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) - - .dataa(\z80_|alu_|op1_high [1]), - .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datac(\z80_|alu_|op2_high [1]), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~16 .lut_mask = 16'hB0BB; -defparam \z80_|alu_|db_high[1]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N20 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~17 ( -// Equation(s): -// \z80_|alu_|db_high[1]~17_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[6]~23_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[4]~17_combout ))) - - .dataa(\z80_|alu_|db[6]~23_combout ), - .datab(gnd), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|alu_|db[4]~17_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~17 .lut_mask = 16'hAFA0; -defparam \z80_|alu_|db_high[1]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N26 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~18 ( -// Equation(s): -// \z80_|alu_|db_high[1]~18_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_high[1]~17_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[5]~25_combout ))) +// \z80_|pla_decode_|Equal3~1_combout = (\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [1]) .dataa(gnd), - .datab(\z80_|alu_|db_high[1]~17_combout ), - .datac(\z80_|alu_|db[5]~25_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~18 .lut_mask = 16'hCCF0; -defparam \z80_|alu_|db_high[1]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N12 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~19 ( -// Equation(s): -// \z80_|alu_|db_high[1]~19_combout = (\z80_|alu_|db_high[1]~15_combout & (\z80_|alu_|db_high[1]~16_combout & ((\z80_|alu_|db_high[1]~18_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) - - .dataa(\z80_|alu_|db_high[1]~15_combout ), - .datab(\z80_|alu_|db_high[1]~16_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datad(\z80_|alu_|db_high[1]~18_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~19 .lut_mask = 16'h8808; -defparam \z80_|alu_|db_high[1]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N26 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~20 ( -// Equation(s): -// \z80_|alu_|db_high[1]~20_combout = ((\z80_|alu_|db_high[1]~19_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout )))) # (!\z80_|alu_|db_high[3]~3_combout ) - - .dataa(\z80_|alu_|db_high[1]~19_combout ), - .datab(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), - .datad(\z80_|alu_|db_high[3]~3_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~20 .lut_mask = 16'hA8FF; -defparam \z80_|alu_|db_high[1]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N14 -cycloneive_lcell_comb \z80_|alu_|db[5]~24 ( -// Equation(s): -// \z80_|alu_|db[5]~24_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[5]~57_combout & ((\z80_|alu_control_|db[5]~15_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & -// ((\z80_|alu_control_|db[5]~15_combout ) # ((!\z80_|execute_|ctl_sw_2d~13_combout )))) - - .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datab(\z80_|alu_control_|db[5]~15_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .datad(\z80_|execute_|ctl_sw_2d~13_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[5]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[5]~24 .lut_mask = 16'hC4F5; -defparam \z80_|alu_|db[5]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N28 -cycloneive_lcell_comb \z80_|alu_|db[5]~25 ( -// Equation(s): -// \z80_|alu_|db[5]~25_combout = ((\z80_|alu_|db[5]~24_combout & ((\z80_|alu_|db_high[1]~20_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~26_combout ) - - .dataa(\z80_|alu_|db_high[1]~20_combout ), - .datab(\z80_|alu_|db[7]~26_combout ), - .datac(\z80_|alu_|db[5]~24_combout ), - .datad(\z80_|execute_|ctl_alu_oe~14_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[5]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[5]~25 .lut_mask = 16'hB3F3; -defparam \z80_|alu_|db[5]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N14 -cycloneive_lcell_comb \z80_|sw1_|db_down[5]~0 ( -// Equation(s): -// \z80_|sw1_|db_down[5]~0_combout = (\z80_|bus_control_|db[5]~15_combout ) # ((\z80_|execute_|ctl_sw_1d~6_combout & ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|execute_|ctl_66_oe~2_combout )))) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|bus_control_|db[5]~15_combout ), - .datac(\z80_|execute_|ctl_66_oe~2_combout ), - .datad(\z80_|execute_|ctl_sw_1d~6_combout ), - .cin(gnd), - .combout(\z80_|sw1_|db_down[5]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sw1_|db_down[5]~0 .lut_mask = 16'hEFCC; -defparam \z80_|sw1_|db_down[5]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N22 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_36 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout = (\z80_|alu_control_|db[5]~15_combout & ((\z80_|execute_|ctl_flags_bus~combout ) # ((\z80_|alu_|db_high[1]~20_combout & \z80_|execute_|ctl_flags_alu~15_combout )))) # (!\z80_|alu_control_|db[5]~15_combout -// & (\z80_|alu_|db_high[1]~20_combout & ((\z80_|execute_|ctl_flags_alu~15_combout )))) - - .dataa(\z80_|alu_control_|db[5]~15_combout ), - .datab(\z80_|alu_|db_high[1]~20_combout ), - .datac(\z80_|execute_|ctl_flags_bus~combout ), - .datad(\z80_|execute_|ctl_flags_alu~15_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_36 .lut_mask = 16'hECA0; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y11_N23 -dffeas \z80_|alu_flags_|flags_yf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_flags_xy_we~15_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|flags_yf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_yf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|flags_yf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N2 -cycloneive_lcell_comb \z80_|alu_control_|db[5]~13 ( -// Equation(s): -// \z80_|alu_control_|db[5]~13_combout = (\z80_|alu_flags_|flags_yf~q & ((\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ) # ((\z80_|alu_control_|out[6]~2_combout )))) # (!\z80_|alu_flags_|flags_yf~q & (!\z80_|execute_|ctl_flags_oe~2_combout & -// ((\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ) # (\z80_|alu_control_|out[6]~2_combout )))) - - .dataa(\z80_|alu_flags_|flags_yf~q ), - .datab(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .datac(\z80_|execute_|ctl_flags_oe~2_combout ), - .datad(\z80_|alu_control_|out[6]~2_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[5]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[5]~13 .lut_mask = 16'hAF8C; -defparam \z80_|alu_control_|db[5]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N0 -cycloneive_lcell_comb \z80_|alu_control_|db[5]~14 ( -// Equation(s): -// \z80_|alu_control_|db[5]~14_combout = (\z80_|sw1_|db_down[5]~0_combout & (\z80_|alu_control_|db[5]~13_combout & ((\z80_|reg_file_|gdfx_temp0[5]~72_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) - - .dataa(\z80_|sw1_|db_down[5]~0_combout ), - .datab(\z80_|alu_control_|db[5]~13_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .datad(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[5]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[5]~14 .lut_mask = 16'h8088; -defparam \z80_|alu_control_|db[5]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N10 -cycloneive_lcell_comb \z80_|alu_control_|db[5]~15 ( -// Equation(s): -// \z80_|alu_control_|db[5]~15_combout = ((\z80_|alu_control_|db[5]~14_combout & ((\z80_|alu_|db[5]~25_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|alu_control_|db[6]~11_combout ), - .datab(\z80_|alu_|db[5]~25_combout ), - .datac(\z80_|execute_|ctl_sw_2u~7_combout ), - .datad(\z80_|alu_control_|db[5]~14_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[5]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[5]~15 .lut_mask = 16'hDF55; -defparam \z80_|alu_control_|db[5]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N10 -cycloneive_lcell_comb \D[0]~107 ( -// Equation(s): -// \D[0]~107_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout ) # ((!\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \z80_|memory_ifc_|nRD_out~2_combout ))) - - .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|memory_ifc_|nRD_out~2_combout ), - .datad(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .cin(gnd), - .combout(\D[0]~107_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~107 .lut_mask = 16'hFF40; -defparam \D[0]~107 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y6_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a21 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[5]~99_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_first_bit_number = 5; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y9_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a5 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[5]~99_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_bit_number = 5; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024; -// synopsys translate_on - -// Location: M9K_X22_Y7_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a13 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[5]~99_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_bit_number = 5; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N8 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4 .lut_mask = 16'hDC98; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y23_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a29 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[5]~99_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_first_bit_number = 5; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N6 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4_combout & -// ((\ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout )))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4_combout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4_combout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5 .lut_mask = 16'hF838; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y26_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a13 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(gnd), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[5]~99_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_bit_number = 5; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_first_bit_number = 5; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y29_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a13 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_bit_number = 5; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init3 = 2048'h990442000864A0284030400454782424440404007E404808A4005448387E547C8004420800620824402040024A1242124204044008404208420A4A42424A1242020028008000524A024A4A284252446240001000101042000054265C7E0600007FAF5CA001C181BE0C02418447B1D88BAA85409896BC7C0E5FAC2529CB69A4038E2564731F88FE730045956C357C5ECF7EF8591DF2A8ACFFBFEEF268CD9B51238594AF691A9B8640983B7F76AAB97209EA6257389992FFE684926E0B19FA338B8489D73811171D5C9FF3DCFFFFFF8002000780101F3F4035A0CDED99F79A4775854F179F7D7DBBCF81B2F6421FF684CA6AF85894D29B9D3ACCBA3F27D9DC9911; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init2 = 2048'h5B438D714D4E3DD115E8BD1286EAB5FA1D71BD8F4508BD4BDC8838F9D27B552259BCEFFBB68A6FF529B3B0D92970010BBB6C7D872421210E190E1CCC47A485EAD2F8735647315839EF6F683C64773FC73464D5FE354936D50823A5DAEBEBDBCC6CAFF2622B8D518F63C6030424188FD357718970D25A30CD0731E532DB23002D02C12B12378356DE2C52041CA7A320C51E0D7CA9F5D575775D57FD75DDFDF75FFFDFFFD75F145247F03A0AE7F1E1EB2D5A99D2444108C6A5979B7CC26ABCC241EA4C912568003BB493CE04FF086C188980052BF6ABAAA2FD5D658000011277EB924C10EFAF3CB9B62486512344C61ADE6F15AB67F335A52513FF05AFAEEE8400; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 2048'h0C840083AD485153ACD3C035591630199B8C096CE4DC557D6D55FCCD738573D6E0948817C496E9DE8EA1F88F627B7460106691CC452DB9799E59A5D003733C4EA1BCE33AD2D8BE40A4E5BB7D7BBEC2CEADBBC8B6F87A4A56FBE0B891DE57E4C64EF9AD87727C49CFE7C5DE942B72AC7F6D97DE18920777FDDEE9EB11122A4E18F5569FDE08906765428FB9E6F89FBF0DEAA6064637BCA63FD02E273E5557F0548662C97BC2E8D3FFDB26D23E87BFD97E635A6560CFD93F8EED26E30C70DE8633D6B97C86DF7D9BEDFB99E36B6658F16C6DEFBDD5DF728D6209C852C37FE67CFF32EE4CCCECC64F7E6225FC99EC64C3B6DD7DED0FD7CCEA3BF09A006ECDD1009E; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'hA9C9CE3AECF7BE27C000000A8ABA95251B309A60B9DDC19EC3E391458CBB53CA00A85E3C5AAE2C49DDC2F6C7B013DACB319A769818A1081A7389F711D76A09BCBED23D9A99FF9B77183697955D76BF0E0008822742DA45B883C9193DAF09424501859565800698515E10A8189EE9B323E35CE7388D73C6E7A50D0DE6739C73AC538D134115D860ADA57B5B868E54393B1E31E762062577697D57E8464340420E9434CCA34CC9A1CB1FAACC56168071EAC113F5265D5F6A45A098D604A820508C4EA47F9A7E46083716911B0D585CE937B530218E8D2AD3777EE7D3B4BC56C29ADB46809D15D185F8809229B150C29C8081174CA6173B99703DA466629005C604; -// synopsys translate_on - -// Location: M9K_X33_Y2_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a5 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_bit_number = 5; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init3 = 2048'hE10F8B8C100323720BEBBDEBB81DF13FF97B252E2CB4F27BA091FBD0002D1A611E1EDBBC716D44D2912B80041C44558060CFCF15955C0D780DD5E71393920844F25E16C87C5D0308EEC52C011514BBC13AFA1028924D0C7CE738105BD47A10AA5B5C1D9D4193E4339F492B0E1A64E13AE35BE6B67AC8057BDACC155F14E906A017A1841358335450D4B26CD2A21B3D8F2211080B81EC040D7FA0B51CD48008112508062020A02490900092D2040259108806A328F4006D2AA514B42FB006ECCCCB9A360865678449975A8AE72B5C0F7BA800C1B5DC55D7D6FE2EF4EED85D00AB111821321BA426A4FE4956B43595832C271E83E060341AE5F2023FC808177383; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init2 = 2048'h1A2955372D510AC266A5445146E27000020C320FAE1557E37154040A13202DC6F40B840FB9A59B6DBB296562CB6220EFBE99D2776A202044D9101006FD221D305519198C859000004012AFF4FB060307C92BB732203BFDFEFFFFFFDFFF87FCFFFBFFEFF03FFE0FFFBFAFE0FF80787FFF7FFF83F7F87003FFBFFFFBFFFBFF0FFC0FF81FFF7FFBFFDFFFBFFFE1FF0086F3141AAB6005810A0621595A893F9D85983B9254954341968BAC8C141C90938C05B2C9CD267E11650407375FEDD6A2FEB346AAF6CFDC0791AA97B741995A3B3981E06D1A44D3711955197BB9910FCA20744915C84D6C24BAF53929814CA8A4697E8F4201145AE7415DC122A5F010436107; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048'h02E84F969E3C800AC610D276182020227809001A50DDDBA3487BB6AE802BA06509312DA0E620656EAF24D57C08FFB14D289613DC32083803B84DC6415FD5EDC000300A8D128FA20030ACCBAFA237B7024504D36A4BA26081137F059E78991154FE2AC2A884A8CC7FBBB21C851CC92B12E15593C0C020FFEE066558590E882D5B67459F1A8C3240FE4E6A8D028C0C088FCF471D400A19B38211004DD122212288B111114514CB11840E04828849C621392041163C00808C67223422F00110201DD18FCFFFF3FFE7F9FFFFFFF82C0B422D214711E08904524A069491774E663F48F665955B4E2C63DAC0078652D10120900298F7EE380092442AFD400BEC43C003; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'hB5D49EA9D7036A45AA9E870B8E8016720C7C3102AE925262492C84584942D209042216E0216C85B8912250B7157D5955AD406CB685BBF071B47D5193363C1CECAFE59E91BF11498940A0944996D47EE8D7E3A4EAE611AE19A965D01BA86B55E9C52A6A379A382C6C265FB0DA01396D0800C0046405C06F466DD18C4DD7655CD4E7622EC485808C841D64B737041FF68813B149A41531A0A692FB14AE2E5B49D49CDCADCF90E7BD88125BCE706BF6D04AABFC1C001163DC6EFF7FD3230303030000000000000000000008400000000000000000000000000030600000100007E00220000000000000080040004023AD496997B8C0077B886EEF161CF2298A091B; -// synopsys translate_on - -// Location: M9K_X33_Y29_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a5 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[5]~99_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a5_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_bit_number = 5; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_first_bit_number = 5; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init3 = 2048'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF80000001C000000160F000FF70C0007F78C00000F05001007870010010000000000800000038000000F000000070000000300000006000000000000040000000F00000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000000001D108000BEDA9FA9698A000000000000000000000000FFFFFFFF408102048004188297E014DA9FA9E9CA00000000000000000000000000000000FFFFFFFC800400CA972208DA9FA9CD8E00000000000000000000000000000000FFFFFFFC8004046A97A289FA9FA9CDC20000000000000000000000007FFFFFFC8000000280040E2A97A2997A9DA9CFC20000000000000000000000007FFFFFFE8000000280042EB28002BE369DA9274200000000000000000000000040810206BFFFFFFE9FE430A29D82AC3E8009E34A000000000000000000000000000000023FFFFFFC9FE4B1829FA2800E8009436A; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048'h9FE8334E88F827C697F88D1600A80A44809E8FC2B86999C2B85B3A82B1D32A869FE8336A88F807CA97F88F96A0A80EC2838E8D42B9E98FC2B86B3B82B0D7B2D2800832E288F827CA97F88B82A0080EC683869542B939B8C2B1AB0F8290B730C2800826EA8878078297F88AD2A0280EC283E694C2B83A3BC2A3AB3E8291A316AA800826EE881807C69DE8ABD6A0280BC282209CD2BA2A3D42A2737F82918314E2800806E6981805C69D48AED6A1E80BCA82709FC2BB223DC2A07B7F8295DF11C2800886E6980805869848AAC6A1E42DC281789DC2BBAA3DC6A02B7582955F00928008A6EE98082D9618088AC8A0F40FC289E89DC2BBCA3DC2A18B7782154F02F0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'h174F0870801C870281E2C982A801460297E5AC0288F318023FFFFFFC0000000297DF094A8094870281D6C082AC01460293FDA89288D31902BFFFFFFE40810106879F8D228C8685028016C082AC014642B3FCA80288D10F02800000027FFFFFFE879F893284DEC9028000408AAC014C02937DA00288D10F02800000027FFFFFFC841FA902804E81068BC04292AC0145E29379B00288D11F02FFFFFFFC0000000084FE89328166C1028BE05282AE4144829179B20288511F02FFFFFFFC0000000084F283328516850A88204602874364829179B08280513E0240810104FFFFFFFF843A8302853685828800560287476C928039B00200413E0000000000FFFFFFFF; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N0 -cycloneive_lcell_comb \Mux2~0 ( -// Equation(s): -// \Mux2~0_combout = (\z80_|address_pins_|abus[14]~23_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout )))) # (!\z80_|address_pins_|abus[14]~23_combout & -// (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ))) - - .dataa(\z80_|address_pins_|abus[14]~23_combout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout ), - .cin(gnd), - .combout(\Mux2~0_combout ), - .cout()); -// synopsys translate_off -defparam \Mux2~0 .lut_mask = 16'hBA98; -defparam \Mux2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N2 -cycloneive_lcell_comb \Mux2~1 ( -// Equation(s): -// \Mux2~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Mux2~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout )) # (!\Mux2~0_combout & -// ((\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Mux2~0_combout )))) - - .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ), - .datad(\Mux2~0_combout ), - .cin(gnd), - .combout(\Mux2~1_combout ), - .cout()); -// synopsys translate_off -defparam \Mux2~1 .lut_mask = 16'hBBC0; -defparam \Mux2~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N20 -cycloneive_lcell_comb \D[5]~110 ( -// Equation(s): -// \D[5]~110_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [15] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\Mux2~1_combout ))))) # -// (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout )) - - .dataa(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [15]), - .datad(\Mux2~1_combout ), - .cin(gnd), - .combout(\D[5]~110_combout ), - .cout()); -// synopsys translate_off -defparam \D[5]~110 .lut_mask = 16'hAEA2; -defparam \D[5]~110 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N28 -cycloneive_lcell_comb \D[5]~85 ( -// Equation(s): -// \D[5]~85_combout = (\D[5]~84_combout & (\D[5]~110_combout & ((\z80_|data_pins_|dout [5]) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) # (!\D[5]~84_combout & (((\z80_|data_pins_|dout [5])) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout ))) - - .dataa(\D[5]~84_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datac(\z80_|data_pins_|dout [5]), - .datad(\D[5]~110_combout ), - .cin(gnd), - .combout(\D[5]~85_combout ), - .cout()); -// synopsys translate_off -defparam \D[5]~85 .lut_mask = 16'hF351; -defparam \D[5]~85 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N24 -cycloneive_lcell_comb \D[5]~99 ( -// Equation(s): -// \D[5]~99_combout = (\D[5]~85_combout ) # (!\D[0]~107_combout ) - - .dataa(\D[0]~107_combout ), .datab(gnd), - .datac(gnd), - .datad(\D[5]~85_combout ), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [1]), .cin(gnd), - .combout(\D[5]~99_combout ), + .combout(\z80_|pla_decode_|Equal3~1_combout ), .cout()); // synopsys translate_off -defparam \D[5]~99 .lut_mask = 16'hFF55; -defparam \D[5]~99 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal3~1 .lut_mask = 16'h00F0; +defparam \z80_|pla_decode_|Equal3~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y13_N14 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[5] ( +// Location: LCCOMB_X24_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|ixy_d~10 ( // Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [5] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[5]~15_combout ) # ((\D[5]~99_combout & \z80_|pin_control_|bus_db_pin_re~combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & -// (\D[5]~99_combout & (\z80_|pin_control_|bus_db_pin_re~combout ))) +// \z80_|execute_|ixy_d~10_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal6~0_combout ))) - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(\D[5]~99_combout ), - .datac(\z80_|pin_control_|bus_db_pin_re~combout ), - .datad(\z80_|bus_control_|db[5]~15_combout ), + .dataa(\z80_|pla_decode_|Equal33~1_combout ), + .datab(\z80_|pla_decode_|Equal3~1_combout ), + .datac(\z80_|decode_state_|use_ixiy~combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [5]), + .combout(\z80_|execute_|ixy_d~10_combout ), .cout()); // synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[5] .lut_mask = 16'hEAC0; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[5] .sum_lutc_input = "datac"; +defparam \z80_|execute_|ixy_d~10 .lut_mask = 16'h8000; +defparam \z80_|execute_|ixy_d~10 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y13_N15 -dffeas \z80_|data_pins_|dout[5] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [5]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|data_pins_|dout [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|data_pins_|dout[5] .is_wysiwyg = "true"; -defparam \z80_|data_pins_|dout[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N22 -cycloneive_lcell_comb \z80_|bus_control_|db[5]~14 ( +// Location: LCCOMB_X24_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|ixy_d~13 ( // Equation(s): -// \z80_|bus_control_|db[5]~14_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [5]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) +// \z80_|execute_|ixy_d~13_combout = (\z80_|execute_|ixy_d~16_combout ) # ((\z80_|execute_|ixy_d~10_combout ) # (\z80_|pla_decode_|Equal41~2_combout )) + + .dataa(\z80_|execute_|ixy_d~16_combout ), + .datab(\z80_|execute_|ixy_d~10_combout ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~13 .lut_mask = 16'hFEFE; +defparam \z80_|execute_|ixy_d~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|ixy_d~14 ( +// Equation(s): +// \z80_|execute_|ixy_d~14_combout = (\z80_|execute_|ixy_d~12_combout & (((\z80_|execute_|ixy_d~17_combout & !\z80_|execute_|ixy_d~13_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) # (!\z80_|execute_|ixy_d~12_combout & +// (((\z80_|execute_|ixy_d~17_combout & !\z80_|execute_|ixy_d~13_combout )))) + + .dataa(\z80_|execute_|ixy_d~12_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ixy_d~17_combout ), + .datad(\z80_|execute_|ixy_d~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~14 .lut_mask = 16'h22F2; +defparam \z80_|execute_|ixy_d~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N10 +cycloneive_lcell_comb \z80_|pla_decode_|Equal49~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal49~0_combout = (!\z80_|decode_state_|in_halt~q & (\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal77~0_combout )) .dataa(gnd), - .datab(\z80_|execute_|ctl_bus_db_oe~combout ), - .datac(\z80_|data_pins_|dout [5]), - .datad(\z80_|bus_control_|db[0]~4_combout ), + .datab(\z80_|decode_state_|in_halt~q ), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|pla_decode_|Equal77~0_combout ), .cin(gnd), - .combout(\z80_|bus_control_|db[5]~14_combout ), + .combout(\z80_|pla_decode_|Equal49~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[5]~14 .lut_mask = 16'hF300; -defparam \z80_|bus_control_|db[5]~14 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal49~0 .lut_mask = 16'h3000; +defparam \z80_|pla_decode_|Equal49~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y10_N22 -cycloneive_lcell_comb \z80_|bus_control_|db[5]~15 ( +// Location: LCCOMB_X24_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ixy_d~15 ( // Equation(s): -// \z80_|bus_control_|db[5]~15_combout = ((\z80_|bus_control_|db[5]~14_combout & ((\z80_|alu_control_|db[5]~15_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) +// \z80_|execute_|ixy_d~15_combout = ((\z80_|decode_state_|use_ixiy~combout & (\z80_|execute_|ixy_d~11_combout & \z80_|pla_decode_|Equal49~0_combout ))) # (!\z80_|execute_|ixy_d~14_combout ) - .dataa(\z80_|bus_control_|db[0]~6_combout ), - .datab(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datac(\z80_|alu_control_|db[5]~15_combout ), - .datad(\z80_|bus_control_|db[5]~14_combout ), + .dataa(\z80_|decode_state_|use_ixiy~combout ), + .datab(\z80_|execute_|ixy_d~11_combout ), + .datac(\z80_|execute_|ixy_d~14_combout ), + .datad(\z80_|pla_decode_|Equal49~0_combout ), .cin(gnd), - .combout(\z80_|bus_control_|db[5]~15_combout ), + .combout(\z80_|execute_|ixy_d~15_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[5]~15 .lut_mask = 16'hF755; -defparam \z80_|bus_control_|db[5]~15 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ixy_d~15 .lut_mask = 16'h8F0F; +defparam \z80_|execute_|ixy_d~15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X34_Y10_N13 -dffeas \z80_|ir_|opcode[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|bus_control_|db[5]~15_combout ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|ir_|opcode [5]), - .prn(vcc)); +// Location: LCCOMB_X28_Y18_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout = (\z80_|execute_|ixy_d~15_combout & \z80_|sequencer_|DFFE_T5_ff~q ) + + .dataa(gnd), + .datab(\z80_|execute_|ixy_d~15_combout ), + .datac(\z80_|sequencer_|DFFE_T5_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), + .cout()); // synopsys translate_off -defparam \z80_|ir_|opcode[5] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[5] .power_up = "low"; +defparam \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 .lut_mask = 16'hC0C0; +defparam \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y15_N20 +// Location: LCCOMB_X26_Y16_N28 cycloneive_lcell_comb \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 ( // Equation(s): // \z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (((!\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout )))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (!\z80_|ir_|opcode [5] & @@ -40796,17 +6454,17 @@ cycloneive_lcell_comb \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 ( .dataa(\z80_|ir_|opcode [5]), .datab(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), - .datac(\z80_|pla_decode_|Equal3~2_combout ), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|pla_decode_|Equal3~2_combout ), .cin(gnd), .combout(\z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'h3350; +defparam \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'h3530; defparam \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X37_Y15_N21 +// Location: FF_X26_Y16_N29 dffeas \z80_|decode_state_|DFFE_inst4 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout ), @@ -40825,525 +6483,32592 @@ defparam \z80_|decode_state_|DFFE_inst4 .is_wysiwyg = "true"; defparam \z80_|decode_state_|DFFE_inst4 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X40_Y18_N4 -cycloneive_lcell_comb \z80_|decode_state_|use_ixiy ( +// Location: LCCOMB_X25_Y16_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~5 ( // Equation(s): -// \z80_|decode_state_|use_ixiy~combout = (\z80_|decode_state_|DFFE_inst4~q ) # (\z80_|decode_state_|DFFE_instIY1~q ) +// \z80_|execute_|ctl_ir_we~5_combout = (\z80_|decode_state_|DFFE_instCB~q & (!\z80_|decode_state_|DFFE_inst4~q & !\z80_|decode_state_|DFFE_instIY1~q )) - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(gnd), - .datac(\z80_|decode_state_|DFFE_instIY1~q ), - .datad(gnd), + .dataa(\z80_|decode_state_|DFFE_instCB~q ), + .datab(\z80_|decode_state_|DFFE_inst4~q ), + .datac(gnd), + .datad(\z80_|decode_state_|DFFE_instIY1~q ), .cin(gnd), - .combout(\z80_|decode_state_|use_ixiy~combout ), + .combout(\z80_|execute_|ctl_ir_we~5_combout ), .cout()); // synopsys translate_off -defparam \z80_|decode_state_|use_ixiy .lut_mask = 16'hFAFA; -defparam \z80_|decode_state_|use_ixiy .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_ir_we~5 .lut_mask = 16'h0022; +defparam \z80_|execute_|ctl_ir_we~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y17_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~23 ( +// Location: LCCOMB_X24_Y17_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~13 ( // Equation(s): -// \z80_|execute_|ctl_mRead~23_combout = (!\z80_|decode_state_|use_ixiy~combout & (!\z80_|decode_state_|in_halt~q & (\z80_|pla_decode_|Equal77~0_combout & \z80_|pla_decode_|Equal33~0_combout ))) +// \z80_|execute_|ctl_ir_we~13_combout = ((\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|pla_decode_|Equal41~2_combout ) # (\z80_|execute_|ctl_ir_we~5_combout )))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) - .dataa(\z80_|decode_state_|use_ixiy~combout ), - .datab(\z80_|decode_state_|in_halt~q ), - .datac(\z80_|pla_decode_|Equal77~0_combout ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~23 .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_mRead~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N16 -cycloneive_lcell_comb \z80_|execute_|fMRead~34 ( -// Equation(s): -// \z80_|execute_|fMRead~34_combout = (\z80_|execute_|ctl_mRead~23_combout ) # (((\z80_|execute_|ctl_ir_we~12_combout ) # (!\z80_|execute_|fMRead~5_combout )) # (!\z80_|execute_|fMWrite~3_combout )) - - .dataa(\z80_|execute_|ctl_mRead~23_combout ), - .datab(\z80_|execute_|fMWrite~3_combout ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|execute_|fMRead~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~34 .lut_mask = 16'hFBFF; -defparam \z80_|execute_|fMRead~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N14 -cycloneive_lcell_comb \z80_|execute_|fMRead~31 ( -// Equation(s): -// \z80_|execute_|fMRead~31_combout = (\z80_|execute_|ixy_d~6_combout & ((\z80_|pla_decode_|Equal33~3_combout ) # ((\z80_|pla_decode_|Equal6~1_combout )))) # (!\z80_|execute_|ixy_d~6_combout & (\z80_|execute_|ixy_d~5_combout & -// ((\z80_|pla_decode_|Equal33~3_combout ) # (\z80_|pla_decode_|Equal6~1_combout )))) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|pla_decode_|Equal33~3_combout ), - .datac(\z80_|pla_decode_|Equal6~1_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~31 .lut_mask = 16'hFCA8; -defparam \z80_|execute_|fMRead~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|fMRead~29 ( -// Equation(s): -// \z80_|execute_|fMRead~29_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|execute_|ctl_ir_we~5_combout & ((\z80_|ir_|opcode [6]) # (\z80_|ir_|opcode [7])))) - - .dataa(\z80_|ir_|opcode [6]), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|ir_|opcode [7]), + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|pla_decode_|Equal41~2_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), .datad(\z80_|execute_|ctl_ir_we~5_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~29_combout ), + .combout(\z80_|execute_|ctl_ir_we~13_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~29 .lut_mask = 16'hC800; -defparam \z80_|execute_|fMRead~29 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_ir_we~13 .lut_mask = 16'hF5D5; +defparam \z80_|execute_|ctl_ir_we~13 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y16_N14 -cycloneive_lcell_comb \z80_|execute_|fMRead~30 ( +// Location: FF_X30_Y17_N31 +dffeas \z80_|ir_|opcode[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|bus_control_|db[3]~21_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|ir_|opcode [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|ir_|opcode[3] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y16_N26 +cycloneive_lcell_comb \z80_|pla_decode_|Equal8~0 ( // Equation(s): -// \z80_|execute_|fMRead~30_combout = (\z80_|execute_|ctl_alu_shift_oe~14_combout & ((\z80_|execute_|ctl_ir_we~9_combout ) # ((\z80_|execute_|fMRead~29_combout ) # (\z80_|execute_|ctl_ir_we~10_combout )))) +// \z80_|pla_decode_|Equal8~0_combout = (!\z80_|ir_|opcode [2] & (\z80_|ir_|opcode [1] & \z80_|ir_|opcode [0])) + + .dataa(\z80_|ir_|opcode [2]), + .datab(gnd), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal8~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal8~0 .lut_mask = 16'h5000; +defparam \z80_|pla_decode_|Equal8~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~6 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~6_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal8~0_combout & \z80_|pla_decode_|Equal13~0_combout )) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|pla_decode_|Equal8~0_combout ), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~6 .lut_mask = 16'h3000; +defparam \z80_|execute_|ctl_mRead~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N10 +cycloneive_lcell_comb \z80_|pla_decode_|Equal9~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal9~0_combout = (!\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [3]) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [4]), + .datac(gnd), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal9~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal9~0 .lut_mask = 16'h0033; +defparam \z80_|pla_decode_|Equal9~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal9~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal9~1_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal1~7_combout & \z80_|pla_decode_|Equal9~0_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal2~0_combout ), + .datac(\z80_|pla_decode_|Equal1~7_combout ), + .datad(\z80_|pla_decode_|Equal9~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal9~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal9~1 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal9~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal9~1_combout & \z80_|sequencer_|M5~q )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|pla_decode_|Equal9~1_combout ), + .datad(\z80_|sequencer_|M5~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 .lut_mask = 16'h3000; +defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~28 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~28_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout & (((!\z80_|execute_|ctl_mRead~8_combout & !\z80_|execute_|ctl_mRead~6_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|execute_|ctl_mRead~8_combout ), + .datac(\z80_|execute_|ctl_mRead~6_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~28 .lut_mask = 16'h0057; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y16_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal13~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal13~1_combout = (\z80_|ir_|opcode [2] & (\z80_|ir_|opcode [1] & \z80_|ir_|opcode [0])) + + .dataa(\z80_|ir_|opcode [2]), + .datab(gnd), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal13~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal13~1 .lut_mask = 16'hA000; +defparam \z80_|pla_decode_|Equal13~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y17_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal69~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal69~0_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|ir_|opcode [4] & \z80_|pla_decode_|Equal13~1_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|pla_decode_|Equal13~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal69~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal69~0 .lut_mask = 16'h4000; +defparam \z80_|pla_decode_|Equal69~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout = (\z80_|pla_decode_|Equal1~4_combout & (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal13~0_combout & \z80_|ir_|opcode [0]))) + + .dataa(\z80_|pla_decode_|Equal1~4_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~27 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~27_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal6~0_combout & ((!\z80_|pla_decode_|Equal21~0_combout ) # (!\z80_|ir_|opcode [5])))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal3~1_combout ), + .datac(\z80_|pla_decode_|Equal21~0_combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~27 .lut_mask = 16'h4C00; +defparam \z80_|execute_|ctl_alu_op_low~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~2_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|pla_decode_|Equal69~0_combout ) # (\z80_|execute_|ctl_alu_op_low~27_combout )))) + + .dataa(\z80_|pla_decode_|Equal69~0_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~2 .lut_mask = 16'hFCF8; +defparam \z80_|execute_|ctl_reg_out_lo~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|rsel3 ( +// Equation(s): +// \z80_|execute_|rsel3~combout = \z80_|ir_|opcode [3] $ (((\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4]))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(gnd), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|rsel3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|rsel3 .lut_mask = 16'h5FA0; +defparam \z80_|execute_|rsel3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~12 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~12_combout = (\z80_|execute_|ctl_ir_we~5_combout & (!\z80_|ir_|opcode [7] & (\z80_|pla_decode_|Equal33~0_combout & \z80_|ir_|opcode [6]))) + + .dataa(\z80_|execute_|ctl_ir_we~5_combout ), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~12 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_ir_we~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|execute_|ctl_ir_we~12_combout & \z80_|sequencer_|DFFE_T3_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(gnd), + .datac(\z80_|execute_|ctl_ir_we~12_combout ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal56~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal56~0_combout = (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal1~4_combout & \z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|pla_decode_|Equal1~4_combout ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal56~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal56~0 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal56~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~24 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~24_combout = (\z80_|pla_decode_|Equal2~0_combout & (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|ir_|opcode [3]))) + + .dataa(\z80_|pla_decode_|Equal2~0_combout ), + .datab(\z80_|ir_|opcode [0]), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~24 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_alu_op_low~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~25 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~25_combout = (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|ir_|opcode [3]))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal2~0_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~25 .lut_mask = 16'h0040; +defparam \z80_|execute_|ctl_alu_op_low~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N16 +cycloneive_lcell_comb \z80_|execute_|nextM~2 ( +// Equation(s): +// \z80_|execute_|nextM~2_combout = (!\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_alu_op_low~24_combout & !\z80_|execute_|ctl_alu_op_low~25_combout )) + + .dataa(\z80_|pla_decode_|Equal56~0_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op_low~24_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~2 .lut_mask = 16'h0005; +defparam \z80_|execute_|nextM~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~16 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~16_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # ((\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T3_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|execute_|nextM~2_combout ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~16 .lut_mask = 16'h3320; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~3_combout = (\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ) # ((\z80_|execute_|ctl_reg_out_lo~2_combout & \z80_|execute_|rsel3~combout ))) + + .dataa(\z80_|execute_|ctl_reg_out_lo~2_combout ), + .datab(\z80_|execute_|rsel3~combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~3 .lut_mask = 16'hFFF8; +defparam \z80_|execute_|ctl_reg_out_lo~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y13_N22 +cycloneive_lcell_comb \z80_|pla_decode_|Equal40~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal40~0_combout = (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [1])) + + .dataa(\z80_|ir_|opcode [0]), + .datab(gnd), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal40~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal40~0 .lut_mask = 16'h0005; +defparam \z80_|pla_decode_|Equal40~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y13_N18 +cycloneive_lcell_comb \z80_|pla_decode_|Equal40~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal40~1_combout = (\z80_|pla_decode_|Equal40~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|ir_|opcode [5])) + + .dataa(\z80_|pla_decode_|Equal40~0_combout ), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(gnd), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal40~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal40~1 .lut_mask = 16'h8800; +defparam \z80_|pla_decode_|Equal40~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|execute_|ixy_d~7_combout & \z80_|pla_decode_|Equal1~7_combout ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal3~1_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|pla_decode_|Equal1~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y17_N24 +cycloneive_lcell_comb \z80_|pla_decode_|Equal3~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal3~0_combout = (\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3]) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [4]), + .datac(gnd), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal3~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal3~0 .lut_mask = 16'hCC00; +defparam \z80_|pla_decode_|Equal3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y13_N20 +cycloneive_lcell_comb \z80_|pla_decode_|Equal39~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal39~0_combout = (\z80_|pla_decode_|Equal40~0_combout & (\z80_|pla_decode_|Equal6~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal3~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal40~0_combout ), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal3~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal39~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal39~0 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal39~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~4_combout = (\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ) # ((\z80_|execute_|ixy_d~9_combout & ((\z80_|pla_decode_|Equal40~1_combout ) # (\z80_|pla_decode_|Equal39~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal40~1_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ), + .datac(\z80_|pla_decode_|Equal39~0_combout ), + .datad(\z80_|execute_|ixy_d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~4 .lut_mask = 16'hFECC; +defparam \z80_|execute_|ctl_reg_out_lo~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y18_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~0_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|M5~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|M5~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~0 .lut_mask = 16'h0F00; +defparam \z80_|execute_|ctl_alu_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|comb~0 ( +// Equation(s): +// \z80_|execute_|comb~0_combout = (\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|execute_|comb~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|comb~0 .lut_mask = 16'hF000; +defparam \z80_|execute_|comb~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N28 +cycloneive_lcell_comb \z80_|pla_decode_|Equal41~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal41~0_combout = (\z80_|ir_|opcode [6] & \z80_|ir_|opcode [7]) + + .dataa(\z80_|ir_|opcode [6]), + .datab(gnd), + .datac(gnd), + .datad(\z80_|ir_|opcode [7]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal41~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal41~0 .lut_mask = 16'hAA00; +defparam \z80_|pla_decode_|Equal41~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N30 +cycloneive_lcell_comb \z80_|pla_decode_|Equal47~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal47~0_combout = (\z80_|ir_|opcode [0] & (!\z80_|decode_state_|table_xx~0_combout & (\z80_|execute_|comb~0_combout & \z80_|pla_decode_|Equal41~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|decode_state_|table_xx~0_combout ), + .datac(\z80_|execute_|comb~0_combout ), + .datad(\z80_|pla_decode_|Equal41~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal47~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal47~0 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal47~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y18_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~32 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~32_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|pla_decode_|Equal47~0_combout & ((!\z80_|execute_|ctl_alu_oe~0_combout ) # (!\z80_|pla_decode_|Equal34~0_combout )))) # (!\z80_|execute_|ixy_d~7_combout & +// (((!\z80_|execute_|ctl_alu_oe~0_combout )) # (!\z80_|pla_decode_|Equal34~0_combout ))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|pla_decode_|Equal34~0_combout ), + .datac(\z80_|execute_|ctl_alu_oe~0_combout ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~32 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_inc_cy~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N22 +cycloneive_lcell_comb \z80_|pla_decode_|Equal19~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal19~0_combout = (\z80_|pla_decode_|Equal1~7_combout & (\z80_|pla_decode_|Equal32~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal3~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal1~7_combout ), + .datab(\z80_|pla_decode_|Equal32~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal3~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal19~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal19~0 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal19~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~9_combout = (\z80_|execute_|ctl_inc_cy~32_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|sequencer_|M5~q )) # (!\z80_|pla_decode_|Equal19~0_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~32_combout ), + .datab(\z80_|pla_decode_|Equal19~0_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|M5~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~9 .lut_mask = 16'hA2AA; +defparam \z80_|execute_|ctl_reg_out_lo~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~5_combout = ((\z80_|execute_|ctl_reg_out_lo~3_combout ) # ((\z80_|execute_|ctl_reg_out_lo~4_combout ) # (!\z80_|execute_|ctl_reg_out_lo~9_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~3_combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~4_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~5 .lut_mask = 16'hFDFF; +defparam \z80_|execute_|ctl_reg_out_lo~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~4 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~4_combout = (\z80_|decode_state_|DFFE_instED~q & (\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [7] & !\z80_|ir_|opcode [6]))) + + .dataa(\z80_|decode_state_|DFFE_instED~q ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~4 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_mWrite~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout = (\z80_|pla_decode_|Equal2~0_combout & (\z80_|execute_|ctl_mWrite~4_combout & (!\z80_|ir_|opcode [0] & \z80_|execute_|ctl_alu_op_low~22_combout ))) + + .dataa(\z80_|pla_decode_|Equal2~0_combout ), + .datab(\z80_|execute_|ctl_mWrite~4_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|execute_|ctl_alu_op_low~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~34 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~34_combout = (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [2] & (\z80_|ir_|opcode [1] & \z80_|execute_|ctl_mWrite~4_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|execute_|ctl_mWrite~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~34 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_mRead~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|execute_|ixy_d~15_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|execute_|ixy_d~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y17_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~36 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~36_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout & (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|execute_|ctl_mRead~34_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~36 .lut_mask = 16'h0015; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~5 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~5_combout = (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T4_ff~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~5 .lut_mask = 16'hC0C0; +defparam \z80_|execute_|ctl_mWrite~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N6 +cycloneive_lcell_comb \z80_|execute_|nextM~11 ( +// Equation(s): +// \z80_|execute_|nextM~11_combout = ((!\z80_|execute_|ctl_alu_op_low~25_combout & (!\z80_|execute_|ctl_alu_op_low~24_combout & !\z80_|pla_decode_|Equal56~0_combout ))) # (!\z80_|execute_|ctl_mWrite~5_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~25_combout ), + .datab(\z80_|execute_|ctl_mWrite~5_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~24_combout ), + .datad(\z80_|pla_decode_|Equal56~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~11 .lut_mask = 16'h3337; +defparam \z80_|execute_|nextM~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N26 +cycloneive_lcell_comb \z80_|pla_decode_|Equal20~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal20~0_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|execute_|comb~0_combout & !\z80_|ir_|opcode [5]))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|execute_|comb~0_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal20~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal20~0 .lut_mask = 16'h0080; +defparam \z80_|pla_decode_|Equal20~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y17_N10 +cycloneive_lcell_comb \z80_|pla_decode_|Equal13~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal13~2_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [4] & \z80_|pla_decode_|Equal13~1_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|pla_decode_|Equal13~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal13~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal13~2 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal13~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~24 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~24_combout = (\z80_|pla_decode_|Equal13~2_combout & !\z80_|ir_|opcode [3]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~24 .lut_mask = 16'h00F0; +defparam \z80_|execute_|ctl_mRead~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~27 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~27_combout = (\z80_|pla_decode_|Equal20~0_combout & (!\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ctl_mRead~24_combout ) # (!\z80_|execute_|ixy_d~6_combout )))) # (!\z80_|pla_decode_|Equal20~0_combout & +// (((!\z80_|execute_|ctl_mRead~24_combout ) # (!\z80_|execute_|ixy_d~6_combout )))) + + .dataa(\z80_|pla_decode_|Equal20~0_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ctl_mRead~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~27 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y17_N20 +cycloneive_lcell_comb \z80_|pla_decode_|Equal48~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal48~0_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [4] & \z80_|pla_decode_|Equal13~1_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|pla_decode_|Equal13~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal48~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal48~0 .lut_mask = 16'h0400; +defparam \z80_|pla_decode_|Equal48~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y16_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal10~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal10~0_combout = (!\z80_|ir_|opcode [1] & (\z80_|execute_|ctl_mWrite~4_combout & (!\z80_|ir_|opcode [2] & \z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [1]), + .datab(\z80_|execute_|ctl_mWrite~4_combout ), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal10~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal10~0 .lut_mask = 16'h0400; +defparam \z80_|pla_decode_|Equal10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y16_N0 +cycloneive_lcell_comb \z80_|pla_decode_|Equal11~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal11~0_combout = (!\z80_|ir_|opcode [1] & (\z80_|execute_|ctl_mWrite~4_combout & (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [1]), + .datab(\z80_|execute_|ctl_mWrite~4_combout ), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal11~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal11~0 .lut_mask = 16'h0004; +defparam \z80_|pla_decode_|Equal11~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N24 +cycloneive_lcell_comb \z80_|pla_decode_|Equal63~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal63~0_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|execute_|comb~0_combout & \z80_|ir_|opcode [5]))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|execute_|comb~0_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal63~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal63~0 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal63~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf2_we ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf2_we~combout = (\z80_|pla_decode_|Equal63~0_combout & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (!\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [3]))) + + .dataa(\z80_|pla_decode_|Equal63~0_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf2_we~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf2_we .lut_mask = 16'h0008; +defparam \z80_|execute_|ctl_flags_hf2_we .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~41 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~41_combout = (!\z80_|execute_|ctl_flags_hf2_we~combout & (((!\z80_|pla_decode_|Equal10~0_combout & !\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|execute_|ctl_flags_hf2_we~combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~41 .lut_mask = 16'h010F; +defparam \z80_|execute_|ctl_alu_shift_oe~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y13_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal68~3 ( +// Equation(s): +// \z80_|pla_decode_|Equal68~3_combout = (\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [1] & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal68~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal68~3 .lut_mask = 16'h0020; +defparam \z80_|pla_decode_|Equal68~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~7_combout = (\z80_|execute_|ctl_alu_op_low~27_combout ) # ((\z80_|pla_decode_|Equal68~3_combout ) # ((\z80_|pla_decode_|Equal21~0_combout & \z80_|pla_decode_|Equal63~0_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~27_combout ), + .datab(\z80_|pla_decode_|Equal68~3_combout ), + .datac(\z80_|pla_decode_|Equal21~0_combout ), + .datad(\z80_|pla_decode_|Equal63~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~7 .lut_mask = 16'hFEEE; +defparam \z80_|execute_|ctl_flags_bus~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~8_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|execute_|ctl_alu_op_low~25_combout ) # ((\z80_|execute_|ctl_flags_bus~7_combout ) # (\z80_|pla_decode_|Equal20~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~25_combout ), + .datab(\z80_|execute_|ctl_flags_bus~7_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|pla_decode_|Equal20~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~8 .lut_mask = 16'hF0E0; +defparam \z80_|execute_|ctl_flags_bus~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N18 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~9 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~9_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|execute_|ctl_alu_op_low~24_combout & !\z80_|pla_decode_|Equal56~0_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) + + .dataa(\z80_|execute_|ctl_alu_op_low~24_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|pla_decode_|Equal56~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~9 .lut_mask = 16'hCFDF; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~6_combout = (!\z80_|ir_|opcode [6] & !\z80_|ir_|opcode [7]) + + .dataa(\z80_|ir_|opcode [6]), + .datab(gnd), + .datac(gnd), + .datad(\z80_|ir_|opcode [7]), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~6 .lut_mask = 16'h0055; +defparam \z80_|execute_|ctl_ir_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~8_combout = (\z80_|execute_|ctl_ir_we~5_combout & (\z80_|execute_|ctl_ir_we~6_combout & ((!\z80_|decode_state_|DFFE_instCB~q ) # (!\z80_|pla_decode_|Equal33~0_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~5_combout ), + .datab(\z80_|execute_|ctl_ir_we~6_combout ), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|decode_state_|DFFE_instCB~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~8 .lut_mask = 16'h0888; +defparam \z80_|execute_|ctl_ir_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~14 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~14_combout = (\z80_|execute_|ctl_ir_we~5_combout & (!\z80_|ir_|opcode [7] & (\z80_|pla_decode_|Equal33~0_combout & !\z80_|ir_|opcode [6]))) + + .dataa(\z80_|execute_|ctl_ir_we~5_combout ), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~14 .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_ir_we~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~4_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~8_combout & !\z80_|execute_|ctl_ir_we~14_combout ))) # (!\z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|execute_|ctl_ir_we~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~4 .lut_mask = 16'hF3F7; +defparam \z80_|execute_|ctl_flags_bus~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~5_combout = (\z80_|execute_|ixy_d~10_combout ) # ((\z80_|pla_decode_|Equal63~0_combout & ((\z80_|pla_decode_|Equal32~0_combout ) # (\z80_|pla_decode_|Equal3~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal32~0_combout ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|execute_|ixy_d~10_combout ), + .datad(\z80_|pla_decode_|Equal3~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~5 .lut_mask = 16'hFCF8; +defparam \z80_|execute_|ctl_flags_bus~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~4 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~4_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal3~1_combout & (!\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~1_combout ), + .datab(\z80_|pla_decode_|Equal3~1_combout ), + .datac(\z80_|decode_state_|use_ixiy~combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~4 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_mRead~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~6_combout = ((!\z80_|execute_|ctl_flags_bus~5_combout & (!\z80_|pla_decode_|Equal13~2_combout & !\z80_|execute_|ctl_mRead~4_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) + + .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), + .datab(\z80_|pla_decode_|Equal13~2_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|execute_|ctl_mRead~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~6 .lut_mask = 16'h0F1F; +defparam \z80_|execute_|ctl_flags_bus~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~9 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~9_combout = (!\z80_|execute_|ctl_flags_bus~8_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~9_combout & (\z80_|execute_|ctl_flags_bus~4_combout & \z80_|execute_|ctl_flags_bus~6_combout ))) + + .dataa(\z80_|execute_|ctl_flags_bus~8_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~9_combout ), + .datac(\z80_|execute_|ctl_flags_bus~4_combout ), + .datad(\z80_|execute_|ctl_flags_bus~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~9 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_flags_bus~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_iorw~11 ( +// Equation(s): +// \z80_|execute_|ctl_iorw~11_combout = (!\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_iorw~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_iorw~11 .lut_mask = 16'h0004; +defparam \z80_|execute_|ctl_iorw~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y16_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~17 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~17_combout = (\z80_|ir_|opcode [1] & (\z80_|execute_|ctl_mWrite~4_combout & (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [1]), + .datab(\z80_|execute_|ctl_mWrite~4_combout ), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~17 .lut_mask = 16'h0008; +defparam \z80_|execute_|ctl_mWrite~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y14_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~18 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~18_combout = ((!\z80_|execute_|ctl_iorw~11_combout & (!\z80_|execute_|ctl_mWrite~17_combout & !\z80_|execute_|ctl_mRead~34_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) + + .dataa(\z80_|execute_|ctl_iorw~11_combout ), + .datab(\z80_|execute_|ctl_mWrite~17_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~18 .lut_mask = 16'h01FF; +defparam \z80_|execute_|ctl_alu_shift_oe~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N14 +cycloneive_lcell_comb \z80_|pla_decode_|Equal37~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal37~0_combout = (!\z80_|ir_|opcode [0] & (!\z80_|decode_state_|table_xx~0_combout & (\z80_|pla_decode_|Equal1~4_combout & \z80_|pla_decode_|Equal41~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|decode_state_|table_xx~0_combout ), + .datac(\z80_|pla_decode_|Equal1~4_combout ), + .datad(\z80_|pla_decode_|Equal41~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal37~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal37~0 .lut_mask = 16'h1000; +defparam \z80_|pla_decode_|Equal37~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~19 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~19_combout = (\z80_|pla_decode_|Equal41~2_combout ) # ((\z80_|pla_decode_|Equal37~0_combout ) # ((\z80_|pla_decode_|Equal40~1_combout ) # (\z80_|pla_decode_|Equal34~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal41~2_combout ), + .datab(\z80_|pla_decode_|Equal37~0_combout ), + .datac(\z80_|pla_decode_|Equal40~1_combout ), + .datad(\z80_|pla_decode_|Equal34~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~19 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_alu_shift_oe~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N0 +cycloneive_lcell_comb \z80_|pla_decode_|Equal35~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal35~0_combout = (!\z80_|ir_|opcode [0] & (!\z80_|decode_state_|table_xx~0_combout & (\z80_|pla_decode_|Equal2~0_combout & \z80_|pla_decode_|Equal41~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|decode_state_|table_xx~0_combout ), + .datac(\z80_|pla_decode_|Equal2~0_combout ), + .datad(\z80_|pla_decode_|Equal41~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal35~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal35~0 .lut_mask = 16'h1000; +defparam \z80_|pla_decode_|Equal35~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y13_N0 +cycloneive_lcell_comb \z80_|pla_decode_|Equal21~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal21~1_combout = (\z80_|pla_decode_|Equal40~0_combout & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal21~0_combout & !\z80_|ir_|opcode [5]))) + + .dataa(\z80_|pla_decode_|Equal40~0_combout ), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|pla_decode_|Equal21~0_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal21~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal21~1 .lut_mask = 16'h0080; +defparam \z80_|pla_decode_|Equal21~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~17 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~17_combout = ((!\z80_|pla_decode_|Equal39~0_combout & (!\z80_|pla_decode_|Equal35~0_combout & !\z80_|pla_decode_|Equal21~1_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) + + .dataa(\z80_|pla_decode_|Equal39~0_combout ), + .datab(\z80_|pla_decode_|Equal35~0_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|pla_decode_|Equal21~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~17 .lut_mask = 16'h0F1F; +defparam \z80_|execute_|ctl_alu_shift_oe~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~20 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~20_combout = (\z80_|execute_|ctl_alu_shift_oe~18_combout & (\z80_|execute_|ctl_alu_shift_oe~17_combout & ((!\z80_|execute_|ctl_alu_shift_oe~19_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~19_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~20 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_alu_shift_oe~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~9 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~9_combout = (\z80_|pla_decode_|Equal41~0_combout & (\z80_|execute_|ctl_ir_we~5_combout & ((!\z80_|decode_state_|DFFE_instCB~q ) # (!\z80_|pla_decode_|Equal33~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|pla_decode_|Equal41~0_combout ), + .datac(\z80_|execute_|ctl_ir_we~5_combout ), + .datad(\z80_|decode_state_|DFFE_instCB~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~9 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_ir_we~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y20_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~11_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|execute_|ctl_ir_we~12_combout & !\z80_|execute_|ctl_ir_we~9_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) + + .dataa(\z80_|execute_|ctl_ir_we~12_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|execute_|ctl_ir_we~9_combout ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~11 .lut_mask = 16'hCDFF; +defparam \z80_|execute_|ctl_alu_bs_oe~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~15 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~15_combout = (\z80_|execute_|ctl_ir_we~5_combout & (\z80_|ir_|opcode [7] & (\z80_|pla_decode_|Equal33~0_combout & \z80_|ir_|opcode [6]))) + + .dataa(\z80_|execute_|ctl_ir_we~5_combout ), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~15 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_ir_we~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y20_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~7_combout = (\z80_|execute_|ctl_alu_bs_oe~11_combout & (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|execute_|ctl_ir_we~10_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~11_combout ), + .datad(\z80_|execute_|ctl_ir_we~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~7 .lut_mask = 16'h5070; +defparam \z80_|execute_|ctl_alu_bs_oe~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~7_combout = (\z80_|execute_|ctl_ir_we~5_combout & (\z80_|ir_|opcode [7] & (\z80_|pla_decode_|Equal33~0_combout & !\z80_|ir_|opcode [6]))) + + .dataa(\z80_|execute_|ctl_ir_we~5_combout ), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~7 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_ir_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N4 +cycloneive_lcell_comb \z80_|pla_decode_|Equal46~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal46~0_combout = (\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [0] & (\z80_|decode_state_|DFFE_instCB~q & \z80_|ir_|opcode [1]))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|ir_|opcode [0]), + .datac(\z80_|decode_state_|DFFE_instCB~q ), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal46~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal46~0 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal46~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~11 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~11_combout = (\z80_|ir_|opcode [6] & (!\z80_|ir_|opcode [7] & (\z80_|execute_|ctl_ir_we~5_combout & !\z80_|pla_decode_|Equal46~0_combout ))) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|execute_|ctl_ir_we~5_combout ), + .datad(\z80_|pla_decode_|Equal46~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~11 .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_ir_we~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~3 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~3_combout = (\z80_|execute_|ctl_alu_bs_oe~7_combout & (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~11_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~7_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_ir_we~7_combout ), + .datad(\z80_|execute_|ctl_ir_we~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~3 .lut_mask = 16'h222A; +defparam \z80_|execute_|ctl_bus_db_oe~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal52~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal52~1_combout = (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|decode_state_|DFFE_instED~q & (\z80_|pla_decode_|Equal41~0_combout & !\z80_|decode_state_|DFFE_instCB~q ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|decode_state_|DFFE_instED~q ), + .datac(\z80_|pla_decode_|Equal41~0_combout ), + .datad(\z80_|decode_state_|DFFE_instCB~q ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal52~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal52~1 .lut_mask = 16'h0020; +defparam \z80_|pla_decode_|Equal52~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~21 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~21_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal44~0_combout & !\z80_|pla_decode_|Equal52~1_combout ))) # (!\z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|pla_decode_|Equal44~0_combout ), + .datad(\z80_|pla_decode_|Equal52~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~21 .lut_mask = 16'hDDDF; +defparam \z80_|execute_|ctl_flags_xy_we~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~13 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~13_combout = (\z80_|execute_|ctl_flags_bus~9_combout & (\z80_|execute_|ctl_alu_shift_oe~20_combout & (\z80_|execute_|ctl_bus_db_oe~3_combout & \z80_|execute_|ctl_flags_xy_we~21_combout ))) + + .dataa(\z80_|execute_|ctl_flags_bus~9_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~20_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~3_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~13 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_flags_xy_we~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~6 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~6_combout = (!\z80_|decode_state_|DFFE_instIY1~q & (!\z80_|decode_state_|DFFE_inst4~q & (\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal44~0_combout ))) + + .dataa(\z80_|decode_state_|DFFE_instIY1~q ), + .datab(\z80_|decode_state_|DFFE_inst4~q ), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|pla_decode_|Equal44~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~6 .lut_mask = 16'h1000; +defparam \z80_|execute_|ctl_state_alu~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~14 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~14_combout = (\z80_|sequencer_|DFFE_M4_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~14 .lut_mask = 16'hA0A0; +defparam \z80_|execute_|ctl_alu_shift_oe~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~14 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~14_combout = (\z80_|execute_|ctl_alu_shift_oe~41_combout & (\z80_|execute_|ctl_flags_xy_we~13_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_state_alu~6_combout )))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~41_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~13_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~14 .lut_mask = 16'h0888; +defparam \z80_|execute_|ctl_flags_xy_we~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y19_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~24 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~24_combout = (\z80_|execute_|ctl_flags_xy_we~14_combout & (((!\z80_|pla_decode_|Equal48~0_combout & !\z80_|pla_decode_|Equal69~0_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|pla_decode_|Equal48~0_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|pla_decode_|Equal69~0_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~24 .lut_mask = 16'h3700; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y19_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~37 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~37_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout & (\z80_|execute_|nextM~11_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~27_combout & \z80_|execute_|ctl_reg_gp_sel[0]~24_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ), + .datab(\z80_|execute_|nextM~11_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~27_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~37 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel~7_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|decode_state_|table_xx~0_combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal41~0_combout ))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|decode_state_|table_xx~0_combout ), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|pla_decode_|Equal41~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel~7 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_reg_gp_sel~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|rsel0 ( +// Equation(s): +// \z80_|execute_|rsel0~combout = \z80_|ir_|opcode [0] $ (((\z80_|ir_|opcode [1] & \z80_|ir_|opcode [2]))) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|rsel0~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|rsel0 .lut_mask = 16'h3FC0; +defparam \z80_|execute_|rsel0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~3 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~3_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~3 .lut_mask = 16'h5050; +defparam \z80_|execute_|ctl_state_alu~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~0_combout = ((!\z80_|execute_|ctl_alu_op_low~24_combout & (!\z80_|execute_|ctl_alu_op_low~25_combout & !\z80_|pla_decode_|Equal56~0_combout ))) # (!\z80_|execute_|ctl_state_alu~3_combout ) + + .dataa(\z80_|execute_|ctl_state_alu~3_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~24_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~25_combout ), + .datad(\z80_|pla_decode_|Equal56~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~0 .lut_mask = 16'h5557; +defparam \z80_|execute_|ctl_reg_use_sp~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~2 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~2_combout = (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~2 .lut_mask = 16'hCC00; +defparam \z80_|execute_|ctl_state_alu~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout = (\z80_|execute_|ixy_d~15_combout & \z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|execute_|ixy_d~15_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 .lut_mask = 16'hAA00; +defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~30 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~30_combout = (\z80_|execute_|ctl_reg_use_sp~0_combout & (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout & ((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|ctl_mRead~34_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~34_combout ), + .datab(\z80_|execute_|ctl_reg_use_sp~0_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~30 .lut_mask = 16'h004C; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~12 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[0]~12_combout = ((!\z80_|pla_decode_|Equal39~0_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal40~1_combout ))) # (!\z80_|execute_|ixy_d~5_combout ) + + .dataa(\z80_|pla_decode_|Equal39~0_combout ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|pla_decode_|Equal40~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~12 .lut_mask = 16'h0F1F; +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~6_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~30_combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ), + .datab(\z80_|pla_decode_|Equal47~0_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~6 .lut_mask = 16'h20A0; +defparam \z80_|execute_|ctl_reg_out_lo~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~5 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~5_combout = (!\z80_|decode_state_|table_xx~0_combout & (!\z80_|pla_decode_|Equal33~0_combout & (\z80_|ir_|opcode [7] & !\z80_|ir_|opcode [6]))) + + .dataa(\z80_|decode_state_|table_xx~0_combout ), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~5 .lut_mask = 16'h0010; +defparam \z80_|execute_|ctl_state_alu~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~1 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~1_combout = ((!\z80_|execute_|ctl_ir_we~8_combout & (!\z80_|execute_|ctl_state_alu~5_combout & !\z80_|execute_|ctl_ir_we~11_combout ))) # (!\z80_|execute_|ctl_eval_cond~0_combout ) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_state_alu~5_combout ), + .datad(\z80_|execute_|ctl_ir_we~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~1 .lut_mask = 16'h3337; +defparam \z80_|execute_|ctl_sw_2u~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~1 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~1_combout = (\z80_|pla_decode_|Equal77~0_combout & ((\z80_|decode_state_|in_halt~q ) # ((!\z80_|pla_decode_|Equal33~0_combout & !\z80_|pla_decode_|Equal33~1_combout )))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|decode_state_|in_halt~q ), + .datac(\z80_|pla_decode_|Equal33~1_combout ), + .datad(\z80_|pla_decode_|Equal77~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~1 .lut_mask = 16'hCD00; +defparam \z80_|execute_|ctl_alu_oe~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~7 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~7_combout = (\z80_|pla_decode_|Equal77~0_combout & (\z80_|pla_decode_|Equal33~1_combout & (!\z80_|decode_state_|use_ixiy~combout & !\z80_|decode_state_|in_halt~q ))) + + .dataa(\z80_|pla_decode_|Equal77~0_combout ), + .datab(\z80_|pla_decode_|Equal33~1_combout ), + .datac(\z80_|decode_state_|use_ixiy~combout ), + .datad(\z80_|decode_state_|in_halt~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~7 .lut_mask = 16'h0008; +defparam \z80_|execute_|ctl_mWrite~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~4 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~4_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|execute_|ctl_alu_oe~1_combout & (!\z80_|execute_|ctl_mWrite~7_combout ))) # (!\z80_|execute_|ctl_eval_cond~0_combout & (((!\z80_|execute_|ctl_ir_we~4_combout ) # +// (!\z80_|execute_|ctl_mWrite~7_combout )))) + + .dataa(\z80_|execute_|ctl_alu_oe~1_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~7_combout ), + .datad(\z80_|execute_|ctl_ir_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~4 .lut_mask = 16'h0737; +defparam \z80_|execute_|ctl_sw_2u~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|setM1~57 ( +// Equation(s): +// \z80_|execute_|setM1~57_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~10_combout ))) # (!\z80_|sequencer_|DFFE_T4_ff~q ) .dataa(\z80_|execute_|ctl_ir_we~9_combout ), - .datab(\z80_|execute_|fMRead~29_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datad(\z80_|execute_|ctl_ir_we~10_combout ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|execute_|ctl_ir_we~10_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), .cin(gnd), - .combout(\z80_|execute_|fMRead~30_combout ), + .combout(\z80_|execute_|setM1~57_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~30 .lut_mask = 16'hF0E0; -defparam \z80_|execute_|fMRead~30 .sum_lutc_input = "datac"; +defparam \z80_|execute_|setM1~57 .lut_mask = 16'hFF37; +defparam \z80_|execute_|setM1~57 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X41_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|fMRead~28 ( +// Location: LCCOMB_X29_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~5 ( // Equation(s): -// \z80_|execute_|fMRead~28_combout = ((\z80_|execute_|ixy_d~6_combout & ((\z80_|pla_decode_|Equal41~2_combout ) # (\z80_|pla_decode_|Equal9~1_combout )))) # (!\z80_|execute_|nextM~4_combout ) +// \z80_|execute_|ctl_sw_2u~5_combout = (\z80_|execute_|ctl_sw_2u~1_combout & (\z80_|execute_|ctl_sw_2u~4_combout & \z80_|execute_|setM1~57_combout )) - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|pla_decode_|Equal41~2_combout ), + .dataa(gnd), + .datab(\z80_|execute_|ctl_sw_2u~1_combout ), + .datac(\z80_|execute_|ctl_sw_2u~4_combout ), + .datad(\z80_|execute_|setM1~57_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~5 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_sw_2u~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~7_combout = (\z80_|execute_|ctl_reg_out_lo~6_combout & (((!\z80_|execute_|ctl_reg_gp_sel~7_combout & \z80_|execute_|ctl_sw_2u~5_combout )) # (!\z80_|execute_|rsel0~combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel~7_combout ), + .datab(\z80_|execute_|rsel0~combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~6_combout ), + .datad(\z80_|execute_|ctl_sw_2u~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~7 .lut_mask = 16'h7030; +defparam \z80_|execute_|ctl_reg_out_lo~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~0_combout = (\z80_|execute_|ctl_alu_shift_oe~14_combout & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|execute_|ctl_mWrite~4_combout & !\z80_|ir_|opcode [0]))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datab(\z80_|pla_decode_|Equal2~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~0 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~41 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~41_combout = (\z80_|execute_|ixy_d~9_combout & (((!\z80_|pla_decode_|Equal10~0_combout & !\z80_|pla_decode_|Equal11~0_combout )))) # (!\z80_|execute_|ixy_d~9_combout & (((!\z80_|pla_decode_|Equal11~0_combout )) # +// (!\z80_|execute_|ctl_alu_shift_oe~14_combout ))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datab(\z80_|execute_|ixy_d~9_combout ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|pla_decode_|Equal11~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~41 .lut_mask = 16'h113F; +defparam \z80_|execute_|ctl_bus_inc_oe~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~86 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~86_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|pla_decode_|Equal19~0_combout ) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|pla_decode_|Equal19~0_combout ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|sequencer_|M5~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~86_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~86 .lut_mask = 16'h3F7F; +defparam \z80_|execute_|ctl_inc_cy~86 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y18_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~88 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~88_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|pla_decode_|Equal34~0_combout ) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|pla_decode_|Equal34~0_combout ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~88_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~88 .lut_mask = 16'h37FF; +defparam \z80_|execute_|ctl_inc_cy~88 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~36 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~36_combout = (\z80_|execute_|ctl_inc_cy~88_combout & (((!\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ctl_alu_op_low~22_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|pla_decode_|Equal47~0_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datad(\z80_|execute_|ctl_inc_cy~88_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~36 .lut_mask = 16'h3700; +defparam \z80_|execute_|ctl_inc_cy~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~87 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~87_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|pla_decode_|Equal9~1_combout ) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|sequencer_|M5~q ), .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|execute_|nextM~4_combout ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), .cin(gnd), - .combout(\z80_|execute_|fMRead~28_combout ), + .combout(\z80_|execute_|ctl_inc_cy~87_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~28 .lut_mask = 16'hA8FF; -defparam \z80_|execute_|fMRead~28 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~87 .lut_mask = 16'h1FFF; +defparam \z80_|execute_|ctl_inc_cy~87 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X41_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|fMRead~32 ( +// Location: LCCOMB_X20_Y18_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~26 ( // Equation(s): -// \z80_|execute_|fMRead~32_combout = ((\z80_|execute_|fMRead~31_combout ) # ((\z80_|execute_|fMRead~30_combout ) # (\z80_|execute_|fMRead~28_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ) +// \z80_|execute_|ctl_bus_inc_oe~26_combout = (\z80_|execute_|ctl_inc_cy~86_combout & (\z80_|execute_|ctl_inc_cy~36_combout & \z80_|execute_|ctl_inc_cy~87_combout )) - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ), - .datab(\z80_|execute_|fMRead~31_combout ), - .datac(\z80_|execute_|fMRead~30_combout ), - .datad(\z80_|execute_|fMRead~28_combout ), + .dataa(\z80_|execute_|ctl_inc_cy~86_combout ), + .datab(\z80_|execute_|ctl_inc_cy~36_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_inc_cy~87_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~32_combout ), + .combout(\z80_|execute_|ctl_bus_inc_oe~26_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~32 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|fMRead~32 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_inc_oe~26 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_bus_inc_oe~26 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y18_N30 +// Location: LCCOMB_X30_Y19_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~9 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~9_combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_M4_ff~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~9 .lut_mask = 16'hC0C0; +defparam \z80_|execute_|ctl_mWrite~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y18_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~1 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we~1_combout = (\z80_|pla_decode_|Equal10~0_combout & (((\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (\z80_|execute_|ctl_mWrite~9_combout )))) # (!\z80_|pla_decode_|Equal10~0_combout & (\z80_|execute_|ctl_mRead~34_combout +// & ((\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (\z80_|execute_|ctl_mWrite~9_combout )))) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datad(\z80_|execute_|ctl_mWrite~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we~1 .lut_mask = 16'hEEE0; +defparam \z80_|execute_|ctl_reg_sys_we~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y18_N20 cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~42 ( // Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~42_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~5_combout & (\z80_|execute_|ctl_inc_cy~77_combout & \z80_|execute_|ctl_inc_cy~53_combout )) +// \z80_|execute_|ctl_bus_inc_oe~42_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~0_combout & (\z80_|execute_|ctl_bus_inc_oe~41_combout & (\z80_|execute_|ctl_bus_inc_oe~26_combout & !\z80_|execute_|ctl_reg_sys_we~1_combout ))) - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), - .datab(\z80_|execute_|ctl_inc_cy~77_combout ), - .datac(\z80_|execute_|ctl_inc_cy~53_combout ), - .datad(gnd), + .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~0_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~26_combout ), + .datad(\z80_|execute_|ctl_reg_sys_we~1_combout ), .cin(gnd), .combout(\z80_|execute_|ctl_bus_inc_oe~42_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~42 .lut_mask = 16'h8080; +defparam \z80_|execute_|ctl_bus_inc_oe~42 .lut_mask = 16'h0040; defparam \z80_|execute_|ctl_bus_inc_oe~42 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y18_N12 -cycloneive_lcell_comb \z80_|execute_|fMRead~14 ( +// Location: LCCOMB_X21_Y16_N22 +cycloneive_lcell_comb \z80_|pla_decode_|Equal40~2 ( // Equation(s): -// \z80_|execute_|fMRead~14_combout = (\z80_|execute_|ctl_mRead~23_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout ) # ((\z80_|execute_|ctl_mRead~15_combout ) # (\z80_|execute_|ctl_ir_we~12_combout ))) +// \z80_|pla_decode_|Equal40~2_combout = (!\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal6~0_combout & (!\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [0]))) - .dataa(\z80_|execute_|ctl_mRead~23_combout ), + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal40~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal40~2 .lut_mask = 16'h0004; +defparam \z80_|pla_decode_|Equal40~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~14 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~14_combout = (!\z80_|pla_decode_|Equal52~1_combout & (((\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal40~2_combout )) # (!\z80_|pla_decode_|Equal21~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal52~1_combout ), + .datab(\z80_|pla_decode_|Equal21~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal40~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~14 .lut_mask = 16'h5155; +defparam \z80_|execute_|ctl_reg_sel_pc~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y16_N28 +cycloneive_lcell_comb \z80_|pla_decode_|Equal55~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal55~0_combout = (!\z80_|ir_|opcode [2] & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [0])) + + .dataa(\z80_|ir_|opcode [2]), + .datab(gnd), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal55~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal55~0 .lut_mask = 16'h0050; +defparam \z80_|pla_decode_|Equal55~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~11 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~11_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal55~0_combout & \z80_|ir_|opcode [3]))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~11 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_mRead~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N4 +cycloneive_lcell_comb \z80_|pla_decode_|Equal6~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal6~1_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal1~4_combout & \z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|pla_decode_|Equal1~4_combout ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal6~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal6~1 .lut_mask = 16'h4000; +defparam \z80_|pla_decode_|Equal6~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|setM1~36 ( +// Equation(s): +// \z80_|execute_|setM1~36_combout = (!\z80_|pla_decode_|Equal6~1_combout & (((!\z80_|ir_|opcode [5] & !\z80_|pla_decode_|Equal3~0_combout )) # (!\z80_|pla_decode_|Equal40~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal6~1_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal3~0_combout ), + .datad(\z80_|pla_decode_|Equal40~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~36 .lut_mask = 16'h0155; +defparam \z80_|execute_|setM1~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|comb~1 ( +// Equation(s): +// \z80_|execute_|comb~1_combout = (\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4]) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [5]), + .datac(gnd), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|comb~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|comb~1 .lut_mask = 16'hCC00; +defparam \z80_|execute_|comb~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~13 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~13_combout = (\z80_|execute_|comb~1_combout & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal55~0_combout ))) + + .dataa(\z80_|execute_|comb~1_combout ), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~13 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_mRead~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~11 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~11_combout = (!\z80_|pla_decode_|Equal41~2_combout & (!\z80_|execute_|ctl_mRead~13_combout & (!\z80_|execute_|ctl_mRead~8_combout & !\z80_|execute_|ctl_mRead~6_combout ))) + + .dataa(\z80_|pla_decode_|Equal41~2_combout ), + .datab(\z80_|execute_|ctl_mRead~13_combout ), + .datac(\z80_|execute_|ctl_mRead~8_combout ), + .datad(\z80_|execute_|ctl_mRead~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~11 .lut_mask = 16'h0001; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N28 +cycloneive_lcell_comb \z80_|pla_decode_|Equal24~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal24~0_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|pla_decode_|Equal2~0_combout & !\z80_|ir_|opcode [5]))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal52~0_combout ), + .datac(\z80_|pla_decode_|Equal2~0_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal24~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal24~0 .lut_mask = 16'h0080; +defparam \z80_|pla_decode_|Equal24~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N12 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~26 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~26_combout = (!\z80_|pla_decode_|Equal35~0_combout & ((\z80_|ir_|opcode [4]) # ((\z80_|ir_|opcode [3]) # (!\z80_|pla_decode_|Equal24~0_combout )))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|pla_decode_|Equal35~0_combout ), + .datad(\z80_|pla_decode_|Equal24~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~26 .lut_mask = 16'h0E0F; +defparam \z80_|execute_|pc_inc_hold~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|setM1~37 ( +// Equation(s): +// \z80_|execute_|setM1~37_combout = (!\z80_|pla_decode_|Equal19~0_combout & (\z80_|execute_|setM1~36_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~11_combout & \z80_|execute_|pc_inc_hold~26_combout ))) + + .dataa(\z80_|pla_decode_|Equal19~0_combout ), + .datab(\z80_|execute_|setM1~36_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~11_combout ), + .datad(\z80_|execute_|pc_inc_hold~26_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~37 .lut_mask = 16'h4000; +defparam \z80_|execute_|setM1~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~6 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~6_combout = (!\z80_|pla_decode_|Equal33~2_combout & (((!\z80_|pla_decode_|Equal50~0_combout & !\z80_|pla_decode_|Equal49~0_combout )) # (!\z80_|decode_state_|use_ixiy~combout ))) + + .dataa(\z80_|decode_state_|use_ixiy~combout ), + .datab(\z80_|pla_decode_|Equal50~0_combout ), + .datac(\z80_|pla_decode_|Equal33~2_combout ), + .datad(\z80_|pla_decode_|Equal49~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~6 .lut_mask = 16'h0507; +defparam \z80_|execute_|pc_inc_hold~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo~38 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo~38_combout = (\z80_|execute_|pc_inc_hold~6_combout & (((!\z80_|pla_decode_|Equal33~1_combout ) # (!\z80_|pla_decode_|Equal6~0_combout )) # (!\z80_|pla_decode_|Equal55~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|pla_decode_|Equal33~1_combout ), + .datad(\z80_|execute_|pc_inc_hold~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo~38 .lut_mask = 16'h7F00; +defparam \z80_|execute_|ctl_reg_sys_hilo~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|fMRead~7 ( +// Equation(s): +// \z80_|execute_|fMRead~7_combout = (\z80_|execute_|ctl_reg_sel_pc~14_combout & (!\z80_|execute_|ctl_mRead~11_combout & (\z80_|execute_|setM1~37_combout & \z80_|execute_|ctl_reg_sys_hilo~38_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~14_combout ), + .datab(\z80_|execute_|ctl_mRead~11_combout ), + .datac(\z80_|execute_|setM1~37_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo~38_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~7 .lut_mask = 16'h2000; +defparam \z80_|execute_|fMRead~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~12 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~12_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal6~0_combout & !\z80_|pla_decode_|Equal33~1_combout )) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~12 .lut_mask = 16'h0088; +defparam \z80_|execute_|ctl_mRead~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~31 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~31_combout = (!\z80_|execute_|ctl_mRead~12_combout & ((\z80_|ir_|opcode [3]) # ((\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal12~0_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~12_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|pla_decode_|Equal12~0_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~31 .lut_mask = 16'h5545; +defparam \z80_|execute_|ctl_bus_inc_oe~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_alu_shift_oe~14_combout & \z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~1_combout ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N12 +cycloneive_lcell_comb \z80_|nM1_int~2 ( +// Equation(s): +// \z80_|nM1_int~2_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|nM1_int~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|nM1_int~2 .lut_mask = 16'h000F; +defparam \z80_|nM1_int~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~0 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~0_combout = (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|M5~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(gnd), + .datad(\z80_|sequencer_|M5~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~0 .lut_mask = 16'hCC00; +defparam \z80_|execute_|ctl_sw_4u~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~10 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~10_combout = (\z80_|execute_|ctl_mRead~8_combout & (!\z80_|execute_|ctl_alu_shift_oe~14_combout & (!\z80_|execute_|ctl_sw_4u~0_combout ))) # (!\z80_|execute_|ctl_mRead~8_combout & +// (((!\z80_|execute_|ctl_alu_shift_oe~14_combout & !\z80_|execute_|ctl_sw_4u~0_combout )) # (!\z80_|execute_|ctl_mRead~6_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~8_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datac(\z80_|execute_|ctl_sw_4u~0_combout ), + .datad(\z80_|execute_|ctl_mRead~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~10 .lut_mask = 16'h0357; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|fMRead~6 ( +// Equation(s): +// \z80_|execute_|fMRead~6_combout = (\z80_|execute_|ctl_mRead~13_combout & (!\z80_|execute_|ctl_alu_shift_oe~14_combout & ((!\z80_|execute_|ctl_alu_op_low~22_combout ) # (!\z80_|execute_|ctl_state_alu~6_combout )))) # +// (!\z80_|execute_|ctl_mRead~13_combout & (((!\z80_|execute_|ctl_alu_op_low~22_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~13_combout ), + .datab(\z80_|execute_|ctl_state_alu~6_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~6 .lut_mask = 16'h153F; +defparam \z80_|execute_|fMRead~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~12 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~12_combout = (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|execute_|ctl_mWrite~17_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|sequencer_|DFFE_M4_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|execute_|ctl_mWrite~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~12 .lut_mask = 16'h5F7F; +defparam \z80_|execute_|ctl_inc_dec~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~15 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~15_combout = (!\z80_|nM1_int~2_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout & (\z80_|execute_|fMRead~6_combout & \z80_|execute_|ctl_inc_dec~12_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), + .datac(\z80_|execute_|fMRead~6_combout ), + .datad(\z80_|execute_|ctl_inc_dec~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~15 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N28 +cycloneive_lcell_comb \z80_|pla_decode_|Equal25~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal25~0_combout = (!\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal55~0_combout ))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal25~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal25~0 .lut_mask = 16'h4000; +defparam \z80_|pla_decode_|Equal25~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal12~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal12~1_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal2~0_combout & !\z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|pla_decode_|Equal2~0_combout ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal12~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal12~1 .lut_mask = 16'h0040; +defparam \z80_|pla_decode_|Equal12~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~38 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~38_combout = ((\z80_|pla_decode_|Equal12~1_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~14_combout & !\z80_|execute_|ctl_sw_4u~0_combout ))) # (!\z80_|pla_decode_|Equal25~0_combout ) + + .dataa(\z80_|pla_decode_|Equal25~0_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datac(\z80_|pla_decode_|Equal12~1_combout ), + .datad(\z80_|execute_|ctl_sw_4u~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~38 .lut_mask = 16'hF5F7; +defparam \z80_|execute_|ctl_inc_cy~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~82 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~82_combout = ((!\z80_|sequencer_|DFFE_M2_ff~q ) # (!\z80_|pla_decode_|Equal13~2_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|pla_decode_|Equal13~2_combout ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~82_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~82 .lut_mask = 16'h77FF; +defparam \z80_|execute_|ctl_inc_cy~82 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~14 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~14_combout = (\z80_|execute_|ctl_inc_cy~38_combout & (\z80_|execute_|ctl_inc_cy~39_combout & (\z80_|execute_|ctl_reg_sel_pc~10_combout & \z80_|execute_|ctl_inc_cy~82_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~38_combout ), + .datab(\z80_|execute_|ctl_inc_cy~39_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~10_combout ), + .datad(\z80_|execute_|ctl_inc_cy~82_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~14 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~16 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~16_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout & +// \z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~16 .lut_mask = 16'h1000; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~32 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~32_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~16_combout & (((\z80_|execute_|fMRead~7_combout & \z80_|execute_|ctl_bus_inc_oe~31_combout )) # (!\z80_|execute_|ctl_alu_op_low~22_combout ))) + + .dataa(\z80_|execute_|fMRead~7_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~31_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~32 .lut_mask = 16'hB300; +defparam \z80_|execute_|ctl_bus_inc_oe~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~77 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~77_combout = (\z80_|execute_|ixy_d~5_combout & (((!\z80_|pla_decode_|Equal37~0_combout & !\z80_|pla_decode_|Equal38~2_combout )))) # (!\z80_|execute_|ixy_d~5_combout & (((!\z80_|pla_decode_|Equal37~0_combout & +// !\z80_|pla_decode_|Equal38~2_combout )) # (!\z80_|execute_|ctl_alu_op_low~22_combout ))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datac(\z80_|pla_decode_|Equal37~0_combout ), + .datad(\z80_|pla_decode_|Equal38~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~77_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~77 .lut_mask = 16'h111F; +defparam \z80_|execute_|ctl_inc_cy~77 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N4 +cycloneive_lcell_comb \z80_|pla_decode_|Equal29~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal29~0_combout = (\z80_|pla_decode_|Equal1~7_combout & (\z80_|pla_decode_|Equal32~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal1~4_combout ))) + + .dataa(\z80_|pla_decode_|Equal1~7_combout ), + .datab(\z80_|pla_decode_|Equal32~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal1~4_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal29~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal29~0 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal29~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~78 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~78_combout = (\z80_|execute_|ctl_inc_cy~77_combout & (((!\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ctl_alu_op_low~22_combout )) # (!\z80_|pla_decode_|Equal29~0_combout ))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datac(\z80_|execute_|ctl_inc_cy~77_combout ), + .datad(\z80_|pla_decode_|Equal29~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~78_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~78 .lut_mask = 16'h10F0; +defparam \z80_|execute_|ctl_inc_cy~78 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~79 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~79_combout = (\z80_|execute_|ctl_inc_cy~78_combout & (((!\z80_|execute_|ctl_sw_4u~0_combout & !\z80_|execute_|ctl_alu_shift_oe~14_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) + + .dataa(\z80_|execute_|ctl_sw_4u~0_combout ), + .datab(\z80_|pla_decode_|Equal47~0_combout ), + .datac(\z80_|execute_|ctl_inc_cy~78_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~79_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~79 .lut_mask = 16'h3070; +defparam \z80_|execute_|ctl_inc_cy~79 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~14 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~14_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal1~4_combout ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal52~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal1~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~14 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_mRead~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y18_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~49 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~49_combout = (\z80_|execute_|ixy_d~5_combout & (!\z80_|pla_decode_|Equal9~1_combout & (!\z80_|execute_|ctl_mRead~14_combout ))) # (!\z80_|execute_|ixy_d~5_combout & (((!\z80_|pla_decode_|Equal9~1_combout & +// !\z80_|execute_|ctl_mRead~14_combout )) # (!\z80_|execute_|ctl_alu_op_low~22_combout ))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|pla_decode_|Equal9~1_combout ), + .datac(\z80_|execute_|ctl_mRead~14_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~49_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~49 .lut_mask = 16'h0357; +defparam \z80_|execute_|ctl_inc_cy~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y18_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~5_combout = ((!\z80_|pla_decode_|Equal11~0_combout & (!\z80_|execute_|ctl_mRead~34_combout & !\z80_|pla_decode_|Equal10~0_combout ))) # (!\z80_|execute_|ctl_alu_op_low~22_combout ) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~5 .lut_mask = 16'h01FF; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y18_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~40 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~40_combout = (\z80_|execute_|ctl_inc_cy~79_combout & (\z80_|execute_|ctl_inc_cy~49_combout & \z80_|execute_|ctl_reg_gp_sel[1]~5_combout )) + + .dataa(\z80_|execute_|ctl_inc_cy~79_combout ), + .datab(\z80_|execute_|ctl_inc_cy~49_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~40 .lut_mask = 16'h8080; +defparam \z80_|execute_|ctl_bus_inc_oe~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~5 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~5_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal33~1_combout & (!\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|pla_decode_|Equal33~1_combout ), + .datac(\z80_|decode_state_|use_ixiy~combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~5 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_mRead~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~44 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~44_combout = (\z80_|decode_state_|DFFE_inst4~q ) # ((\z80_|decode_state_|DFFE_instIY1~q ) # ((!\z80_|pla_decode_|Equal49~0_combout & !\z80_|pla_decode_|Equal50~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal49~0_combout ), + .datab(\z80_|decode_state_|DFFE_inst4~q ), + .datac(\z80_|pla_decode_|Equal50~0_combout ), + .datad(\z80_|decode_state_|DFFE_instIY1~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~44 .lut_mask = 16'hFFCD; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~36 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~36_combout = (\z80_|execute_|ctl_mRead~5_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout ) # ((\z80_|execute_|ctl_mRead~4_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~5_combout ), .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_mRead~15_combout ), - .datad(\z80_|execute_|ctl_ir_we~12_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ), + .datad(\z80_|execute_|ctl_mRead~4_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~14_combout ), + .combout(\z80_|execute_|ctl_bus_inc_oe~36_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~14 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|fMRead~14 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_inc_oe~36 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|ctl_bus_inc_oe~36 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y18_N18 -cycloneive_lcell_comb \z80_|execute_|fMRead~10 ( +// Location: LCCOMB_X21_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~35 ( // Equation(s): -// \z80_|execute_|fMRead~10_combout = (!\z80_|execute_|ctl_mRead~4_combout & (!\z80_|pla_decode_|Equal6~1_combout & (!\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_bus_db_oe~1_combout ))) +// \z80_|execute_|ctl_bus_inc_oe~35_combout = (\z80_|execute_|ctl_state_alu~6_combout ) # ((\z80_|pla_decode_|Equal13~2_combout ) # (\z80_|execute_|ctl_mRead~8_combout )) - .dataa(\z80_|execute_|ctl_mRead~4_combout ), - .datab(\z80_|pla_decode_|Equal6~1_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .dataa(\z80_|execute_|ctl_state_alu~6_combout ), + .datab(\z80_|pla_decode_|Equal13~2_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_mRead~8_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~10_combout ), + .combout(\z80_|execute_|ctl_bus_inc_oe~35_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~10 .lut_mask = 16'h0100; -defparam \z80_|execute_|fMRead~10 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_inc_oe~35 .lut_mask = 16'hFFEE; +defparam \z80_|execute_|ctl_bus_inc_oe~35 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y18_N28 -cycloneive_lcell_comb \z80_|execute_|fMRead~9 ( +// Location: LCCOMB_X21_Y17_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~46 ( // Equation(s): -// \z80_|execute_|fMRead~9_combout = (\z80_|execute_|ctl_mRead~23_combout ) # (((\z80_|execute_|ctl_mRead~13_combout ) # (!\z80_|execute_|nextM~3_combout )) # (!\z80_|execute_|pc_inc_hold~28_combout )) +// \z80_|execute_|ctl_bus_inc_oe~46_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|execute_|ctl_bus_inc_oe~36_combout ) # (\z80_|execute_|ctl_bus_inc_oe~35_combout )))) - .dataa(\z80_|execute_|ctl_mRead~23_combout ), - .datab(\z80_|execute_|pc_inc_hold~28_combout ), - .datac(\z80_|execute_|ctl_mRead~13_combout ), - .datad(\z80_|execute_|nextM~3_combout ), + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|execute_|ctl_bus_inc_oe~36_combout ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|execute_|ctl_bus_inc_oe~35_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~9_combout ), + .combout(\z80_|execute_|ctl_bus_inc_oe~46_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~9 .lut_mask = 16'hFBFF; -defparam \z80_|execute_|fMRead~9 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_inc_oe~46 .lut_mask = 16'h5040; +defparam \z80_|execute_|ctl_bus_inc_oe~46 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y18_N24 -cycloneive_lcell_comb \z80_|execute_|fMRead~11 ( +// Location: LCCOMB_X24_Y11_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~33 ( // Equation(s): -// \z80_|execute_|fMRead~11_combout = (\z80_|execute_|ctl_state_alu~4_combout & (((\z80_|execute_|ctl_ir_we~14_combout ) # (\z80_|execute_|fMRead~9_combout )) # (!\z80_|execute_|fMRead~10_combout ))) +// \z80_|execute_|ctl_bus_inc_oe~33_combout = (\z80_|execute_|pc_inc_hold~26_combout & (!\z80_|pla_decode_|Equal6~1_combout & ((!\z80_|pla_decode_|Equal33~2_combout ) # (!\z80_|decode_state_|use_ixiy~combout )))) - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|fMRead~10_combout ), - .datac(\z80_|execute_|ctl_ir_we~14_combout ), - .datad(\z80_|execute_|fMRead~9_combout ), + .dataa(\z80_|decode_state_|use_ixiy~combout ), + .datab(\z80_|execute_|pc_inc_hold~26_combout ), + .datac(\z80_|pla_decode_|Equal6~1_combout ), + .datad(\z80_|pla_decode_|Equal33~2_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~11_combout ), + .combout(\z80_|execute_|ctl_bus_inc_oe~33_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~11 .lut_mask = 16'hAAA2; -defparam \z80_|execute_|fMRead~11 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_inc_oe~33 .lut_mask = 16'h040C; +defparam \z80_|execute_|ctl_bus_inc_oe~33 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|fMRead~12 ( +// Location: LCCOMB_X21_Y17_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~47 ( // Equation(s): -// \z80_|execute_|fMRead~12_combout = (\z80_|execute_|ctl_ir_we~8_combout ) # ((\z80_|execute_|ctl_ir_we~14_combout ) # ((\z80_|pla_decode_|Equal49~0_combout & !\z80_|decode_state_|use_ixiy~combout ))) +// \z80_|execute_|ctl_bus_inc_oe~47_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & ((!\z80_|execute_|ctl_bus_inc_oe~33_combout ) # (!\z80_|execute_|nextM~2_combout )))) - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|execute_|nextM~2_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~47 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_bus_inc_oe~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal8~0_combout & (\z80_|sequencer_|DFFE_T5_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ))) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|pla_decode_|Equal8~0_combout ), + .datac(\z80_|sequencer_|DFFE_T5_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~45 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~45_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout & (((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|pla_decode_|Equal11~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~45 .lut_mask = 16'h070F; +defparam \z80_|execute_|ctl_bus_inc_oe~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~34 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~34_combout = ((\z80_|execute_|ctl_alu_oe~0_combout & ((\z80_|execute_|ctl_mRead~4_combout ) # (\z80_|execute_|ctl_mRead~8_combout )))) # (!\z80_|execute_|ctl_bus_inc_oe~45_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~45_combout ), + .datab(\z80_|execute_|ctl_mRead~4_combout ), + .datac(\z80_|execute_|ctl_alu_oe~0_combout ), + .datad(\z80_|execute_|ctl_mRead~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~34 .lut_mask = 16'hF5D5; +defparam \z80_|execute_|ctl_bus_inc_oe~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout = (\z80_|pla_decode_|Equal9~1_combout & (\z80_|sequencer_|M5~q & \z80_|sequencer_|DFFE_T4_ff~q )) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(gnd), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~6 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~6_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal52~0_combout & \z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal3~1_combout ), + .datac(\z80_|pla_decode_|Equal52~0_combout ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~6 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_mWrite~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~50 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~50_combout = (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|execute_|ctl_mWrite~6_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|execute_|ctl_mWrite~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~50_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~50 .lut_mask = 16'h37FF; +defparam \z80_|execute_|ctl_bus_inc_oe~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal4~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal4~0_combout = (\z80_|pla_decode_|Equal1~4_combout & (\z80_|pla_decode_|Equal1~7_combout & (\z80_|ir_|opcode [3] & \z80_|execute_|comb~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal1~4_combout ), + .datab(\z80_|pla_decode_|Equal1~7_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|execute_|comb~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal4~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal4~0 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~48 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~48_combout = (\z80_|execute_|ctl_bus_inc_oe~50_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|pla_decode_|Equal4~0_combout )) # (!\z80_|sequencer_|DFFE_T5_ff~q ))) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~50_combout ), + .datab(\z80_|sequencer_|DFFE_T5_ff~q ), + .datac(\z80_|pla_decode_|Equal4~0_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~48 .lut_mask = 16'hAA2A; +defparam \z80_|execute_|ctl_bus_inc_oe~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~49 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~49_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q ))) # (!\z80_|execute_|ctl_mRead~6_combout ) + + .dataa(\z80_|sequencer_|M5~q ), + .datab(\z80_|execute_|ctl_mRead~6_combout ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~49_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~49 .lut_mask = 16'hFF37; +defparam \z80_|execute_|ctl_bus_inc_oe~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~7 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~7_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal55~0_combout & \z80_|pla_decode_|Equal6~0_combout )) + + .dataa(\z80_|pla_decode_|Equal33~1_combout ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~7 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_mRead~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~29 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~29_combout = (\z80_|execute_|ixy_d~5_combout & (!\z80_|execute_|ctl_mWrite~17_combout & ((!\z80_|execute_|ctl_ir_we~4_combout ) # (!\z80_|execute_|ctl_mRead~7_combout )))) # (!\z80_|execute_|ixy_d~5_combout & +// (((!\z80_|execute_|ctl_ir_we~4_combout )) # (!\z80_|execute_|ctl_mRead~7_combout ))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_mRead~7_combout ), + .datac(\z80_|execute_|ctl_mWrite~17_combout ), + .datad(\z80_|execute_|ctl_ir_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~29 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_bus_inc_oe~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~11_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # (((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|sequencer_|M5~q )) + + .dataa(\z80_|execute_|ctl_ir_we~9_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|M5~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~11 .lut_mask = 16'hF1FF; +defparam \z80_|execute_|ctl_alu_core_S~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y17_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~27 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~27_combout = (\z80_|execute_|ctl_alu_oe~0_combout & (!\z80_|execute_|ctl_ir_we~14_combout & ((!\z80_|execute_|ctl_ir_we~8_combout )))) # (!\z80_|execute_|ctl_alu_oe~0_combout & (((!\z80_|execute_|ixy_d~7_combout )) # +// (!\z80_|execute_|ctl_ir_we~14_combout ))) + + .dataa(\z80_|execute_|ctl_alu_oe~0_combout ), .datab(\z80_|execute_|ctl_ir_we~14_combout ), - .datac(\z80_|pla_decode_|Equal49~0_combout ), - .datad(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ctl_ir_we~8_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~12_combout ), + .combout(\z80_|execute_|ctl_bus_inc_oe~27_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~12 .lut_mask = 16'hEEFE; -defparam \z80_|execute_|fMRead~12 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_inc_oe~27 .lut_mask = 16'h1537; +defparam \z80_|execute_|ctl_bus_inc_oe~27 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y18_N14 -cycloneive_lcell_comb \z80_|execute_|fMRead~13 ( +// Location: LCCOMB_X23_Y19_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~44 ( // Equation(s): -// \z80_|execute_|fMRead~13_combout = (!\z80_|execute_|fMWrite~5_combout & ((\z80_|execute_|fMRead~12_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout ) # (\z80_|execute_|ctl_mRead~6_combout )))) +// \z80_|execute_|ctl_bus_inc_oe~44_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~7_combout )) # (!\z80_|sequencer_|M5~q )) - .dataa(\z80_|execute_|fMRead~12_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_mRead~6_combout ), - .datad(\z80_|execute_|fMWrite~5_combout ), + .dataa(\z80_|execute_|ctl_ir_we~10_combout ), + .datab(\z80_|execute_|ctl_ir_we~7_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|M5~q ), .cin(gnd), - .combout(\z80_|execute_|fMRead~13_combout ), + .combout(\z80_|execute_|ctl_bus_inc_oe~44_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~13 .lut_mask = 16'h00FE; -defparam \z80_|execute_|fMRead~13 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_inc_oe~44 .lut_mask = 16'hF1FF; +defparam \z80_|execute_|ctl_bus_inc_oe~44 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y18_N30 -cycloneive_lcell_comb \z80_|execute_|fMRead~15 ( +// Location: LCCOMB_X25_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~28 ( // Equation(s): -// \z80_|execute_|fMRead~15_combout = (\z80_|execute_|fMRead~11_combout ) # ((\z80_|execute_|fMRead~13_combout ) # ((\z80_|execute_|fMRead~14_combout & \z80_|execute_|ctl_state_alu~6_combout ))) +// \z80_|execute_|ctl_bus_inc_oe~28_combout = (\z80_|execute_|ctl_alu_core_S~11_combout & (\z80_|execute_|ctl_bus_inc_oe~27_combout & \z80_|execute_|ctl_bus_inc_oe~44_combout )) - .dataa(\z80_|execute_|fMRead~14_combout ), - .datab(\z80_|execute_|fMRead~11_combout ), - .datac(\z80_|execute_|fMRead~13_combout ), - .datad(\z80_|execute_|ctl_state_alu~6_combout ), + .dataa(\z80_|execute_|ctl_alu_core_S~11_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~27_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_bus_inc_oe~44_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~15_combout ), + .combout(\z80_|execute_|ctl_bus_inc_oe~28_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~15 .lut_mask = 16'hFEFC; -defparam \z80_|execute_|fMRead~15 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_inc_oe~28 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_bus_inc_oe~28 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y17_N2 -cycloneive_lcell_comb \z80_|execute_|fMRead~20 ( +// Location: LCCOMB_X23_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~30 ( // Equation(s): -// \z80_|execute_|fMRead~20_combout = (((\z80_|execute_|fMRead~15_combout ) # (!\z80_|execute_|ctl_sw_4d~2_combout )) # (!\z80_|execute_|fMRead~19_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~42_combout ) +// \z80_|execute_|ctl_bus_inc_oe~30_combout = (\z80_|execute_|ctl_bus_inc_oe~49_combout & (\z80_|execute_|ctl_bus_inc_oe~29_combout & \z80_|execute_|ctl_bus_inc_oe~28_combout )) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~49_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~29_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_bus_inc_oe~28_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~30 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_bus_inc_oe~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~3 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~3_combout = (\z80_|pla_decode_|Equal1~7_combout & (\z80_|pla_decode_|Equal2~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal21~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal1~7_combout ), + .datab(\z80_|pla_decode_|Equal2~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal21~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~3 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_mRead~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|fMRead~3 ( +// Equation(s): +// \z80_|execute_|fMRead~3_combout = ((!\z80_|pla_decode_|Equal33~0_combout ) # (!\z80_|ir_|opcode [7])) # (!\z80_|execute_|ctl_ir_we~5_combout ) + + .dataa(\z80_|execute_|ctl_ir_we~5_combout ), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|fMRead~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~3 .lut_mask = 16'h7F7F; +defparam \z80_|execute_|fMRead~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~37 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~37_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mRead~3_combout ) # ((\z80_|execute_|ctl_mRead~4_combout ) # (!\z80_|execute_|fMRead~3_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~3_combout ), + .datab(\z80_|execute_|ctl_mRead~4_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|fMRead~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~37 .lut_mask = 16'hE0F0; +defparam \z80_|execute_|ctl_bus_inc_oe~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~38 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~38_combout = (\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ) # (((\z80_|execute_|ctl_bus_inc_oe~37_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~30_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~48_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~48_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~30_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~37_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~38 .lut_mask = 16'hFFBF; +defparam \z80_|execute_|ctl_bus_inc_oe~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~39 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~39_combout = (\z80_|execute_|ctl_bus_inc_oe~46_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~47_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~34_combout ) # (\z80_|execute_|ctl_bus_inc_oe~38_combout ))) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~46_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~47_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~34_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~38_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~39 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_bus_inc_oe~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~43 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~43_combout = (((\z80_|execute_|ctl_bus_inc_oe~39_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~40_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~32_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~42_combout ) .dataa(\z80_|execute_|ctl_bus_inc_oe~42_combout ), - .datab(\z80_|execute_|fMRead~19_combout ), - .datac(\z80_|execute_|fMRead~15_combout ), - .datad(\z80_|execute_|ctl_sw_4d~2_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~32_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~40_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~39_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~20_combout ), + .combout(\z80_|execute_|ctl_bus_inc_oe~43_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~20 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|fMRead~20 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_inc_oe~43 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_bus_inc_oe~43 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~48 ( +// Location: LCCOMB_X28_Y16_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~3 ( // Equation(s): -// \z80_|execute_|pc_inc_hold~48_combout = (\z80_|execute_|ixy_d~5_combout & ((\z80_|pla_decode_|Equal35~0_combout ) # ((\z80_|pla_decode_|Equal24~0_combout & \z80_|pla_decode_|Equal9~0_combout )))) +// \z80_|execute_|ctl_alu_oe~3_combout = (\z80_|decode_state_|in_halt~q ) # (((!\z80_|pla_decode_|Equal33~0_combout & !\z80_|pla_decode_|Equal33~1_combout )) # (!\z80_|pla_decode_|Equal77~0_combout )) - .dataa(\z80_|pla_decode_|Equal24~0_combout ), - .datab(\z80_|pla_decode_|Equal35~0_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|pla_decode_|Equal9~0_combout ), + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|decode_state_|in_halt~q ), + .datac(\z80_|pla_decode_|Equal33~1_combout ), + .datad(\z80_|pla_decode_|Equal77~0_combout ), .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~48_combout ), + .combout(\z80_|execute_|ctl_alu_oe~3_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~48 .lut_mask = 16'hE0C0; -defparam \z80_|execute_|pc_inc_hold~48 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_alu_oe~3 .lut_mask = 16'hCDFF; +defparam \z80_|execute_|ctl_alu_oe~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X41_Y16_N30 -cycloneive_lcell_comb \z80_|execute_|fMRead~22 ( +// Location: LCCOMB_X25_Y14_N8 +cycloneive_lcell_comb \z80_|execute_|fMWrite~1 ( // Equation(s): -// \z80_|execute_|fMRead~22_combout = (\z80_|execute_|ctl_mRead~17_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # ((\z80_|execute_|ctl_alu_oe~2_combout )))) # (!\z80_|execute_|ctl_mRead~17_combout & (\z80_|execute_|ctl_mRead~18_combout & -// ((\z80_|execute_|ctl_ir_we~4_combout ) # (\z80_|execute_|ctl_alu_oe~2_combout )))) +// \z80_|execute_|fMWrite~1_combout = (!\z80_|execute_|ctl_ir_we~15_combout & (!\z80_|execute_|ctl_mRead~4_combout & (!\z80_|execute_|ctl_ir_we~14_combout & !\z80_|execute_|ctl_ir_we~7_combout ))) - .dataa(\z80_|execute_|ctl_mRead~17_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_mRead~18_combout ), - .datad(\z80_|execute_|ctl_alu_oe~2_combout ), + .dataa(\z80_|execute_|ctl_ir_we~15_combout ), + .datab(\z80_|execute_|ctl_mRead~4_combout ), + .datac(\z80_|execute_|ctl_ir_we~14_combout ), + .datad(\z80_|execute_|ctl_ir_we~7_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~22_combout ), + .combout(\z80_|execute_|fMWrite~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~22 .lut_mask = 16'hFAC8; -defparam \z80_|execute_|fMRead~22 .sum_lutc_input = "datac"; +defparam \z80_|execute_|fMWrite~1 .lut_mask = 16'h0001; +defparam \z80_|execute_|fMWrite~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y15_N2 -cycloneive_lcell_comb \z80_|execute_|fMRead~21 ( +// Location: LCCOMB_X24_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~1 ( // Equation(s): -// \z80_|execute_|fMRead~21_combout = (\z80_|execute_|ctl_state_alu~5_combout & (((\z80_|execute_|ctl_mRead~36_combout ) # (!\z80_|execute_|fMRead~4_combout )) # (!\z80_|execute_|fMRead~2_combout ))) +// \z80_|execute_|ctl_flags_bus~1_combout = ((\z80_|ir_|opcode [2]) # (\z80_|ir_|opcode [1])) # (!\z80_|execute_|ctl_mWrite~4_combout ) - .dataa(\z80_|execute_|fMRead~2_combout ), - .datab(\z80_|execute_|ctl_mRead~36_combout ), - .datac(\z80_|execute_|ctl_state_alu~5_combout ), - .datad(\z80_|execute_|fMRead~4_combout ), + .dataa(gnd), + .datab(\z80_|execute_|ctl_mWrite~4_combout ), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [1]), .cin(gnd), - .combout(\z80_|execute_|fMRead~21_combout ), + .combout(\z80_|execute_|ctl_flags_bus~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~21 .lut_mask = 16'hD0F0; -defparam \z80_|execute_|fMRead~21 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_flags_bus~1 .lut_mask = 16'hFFF3; +defparam \z80_|execute_|ctl_flags_bus~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y15_N10 -cycloneive_lcell_comb \z80_|execute_|fMRead~23 ( +// Location: LCCOMB_X25_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|fMRead~5 ( // Equation(s): -// \z80_|execute_|fMRead~23_combout = ((\z80_|execute_|pc_inc_hold~48_combout ) # ((\z80_|execute_|fMRead~22_combout ) # (\z80_|execute_|fMRead~21_combout ))) # (!\z80_|execute_|ctl_bus_db_oe~0_combout ) +// \z80_|execute_|fMRead~5_combout = (!\z80_|pla_decode_|Equal13~2_combout & (\z80_|execute_|ctl_flags_bus~1_combout & !\z80_|execute_|ctl_state_alu~6_combout )) - .dataa(\z80_|execute_|ctl_bus_db_oe~0_combout ), - .datab(\z80_|execute_|pc_inc_hold~48_combout ), - .datac(\z80_|execute_|fMRead~22_combout ), - .datad(\z80_|execute_|fMRead~21_combout ), + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(\z80_|execute_|ctl_flags_bus~1_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(gnd), .cin(gnd), - .combout(\z80_|execute_|fMRead~23_combout ), + .combout(\z80_|execute_|fMRead~5_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~23 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|fMRead~23 .sum_lutc_input = "datac"; +defparam \z80_|execute_|fMRead~5 .lut_mask = 16'h0404; +defparam \z80_|execute_|fMRead~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y12_N8 +// Location: LCCOMB_X25_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~17 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~17_combout = (\z80_|execute_|fMWrite~1_combout & (!\z80_|execute_|ctl_ir_we~12_combout & \z80_|execute_|fMRead~5_combout )) + + .dataa(\z80_|execute_|fMWrite~1_combout ), + .datab(\z80_|execute_|ctl_ir_we~12_combout ), + .datac(gnd), + .datad(\z80_|execute_|fMRead~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~17 .lut_mask = 16'h2200; +defparam \z80_|execute_|ctl_mRead~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_iorw~10 ( +// Equation(s): +// \z80_|execute_|ctl_iorw~10_combout = (!\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [1] & \z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_iorw~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_iorw~10 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_iorw~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|setM1~47 ( +// Equation(s): +// \z80_|execute_|setM1~47_combout = (!\z80_|execute_|ctl_iorw~11_combout & (!\z80_|execute_|ctl_mRead~11_combout & (\z80_|execute_|ctl_mRead~17_combout & !\z80_|execute_|ctl_iorw~10_combout ))) + + .dataa(\z80_|execute_|ctl_iorw~11_combout ), + .datab(\z80_|execute_|ctl_mRead~11_combout ), + .datac(\z80_|execute_|ctl_mRead~17_combout ), + .datad(\z80_|execute_|ctl_iorw~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~47 .lut_mask = 16'h0010; +defparam \z80_|execute_|setM1~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~8 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~8_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal6~0_combout & (!\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal55~0_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~8 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_mWrite~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~13 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~13_combout = ((\z80_|ir_|opcode [2]) # (!\z80_|ir_|opcode [1])) # (!\z80_|execute_|ctl_mWrite~4_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_mWrite~4_combout ), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~13 .lut_mask = 16'hF3FF; +defparam \z80_|execute_|ctl_al_we~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|setM1~48 ( +// Equation(s): +// \z80_|execute_|setM1~48_combout = (\z80_|execute_|setM1~47_combout & (!\z80_|execute_|ctl_mWrite~8_combout & \z80_|execute_|ctl_al_we~13_combout )) + + .dataa(\z80_|execute_|setM1~47_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_mWrite~8_combout ), + .datad(\z80_|execute_|ctl_al_we~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~48 .lut_mask = 16'h0A00; +defparam \z80_|execute_|setM1~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~0 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~0_combout = (\z80_|execute_|ctl_state_alu~3_combout & (((!\z80_|decode_state_|use_ixiy~combout & !\z80_|execute_|ctl_alu_oe~3_combout )) # (!\z80_|execute_|setM1~48_combout ))) + + .dataa(\z80_|decode_state_|use_ixiy~combout ), + .datab(\z80_|execute_|ctl_state_alu~3_combout ), + .datac(\z80_|execute_|ctl_alu_oe~3_combout ), + .datad(\z80_|execute_|setM1~48_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~0 .lut_mask = 16'h04CC; +defparam \z80_|execute_|ctl_sw_4d~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|pla_decode_|Equal48~0_combout & !\z80_|sequencer_|DFFE_M1_ff~q )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|pla_decode_|Equal48~0_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 .lut_mask = 16'h00C0; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~9 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~9_combout = (\z80_|sequencer_|DFFE_T5_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T5_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~9 .lut_mask = 16'h00F0; +defparam \z80_|execute_|ctl_mRead~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~3_combout = (\z80_|pla_decode_|Equal10~0_combout & (!\z80_|execute_|ixy_d~7_combout & ((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|pla_decode_|Equal21~1_combout )))) # (!\z80_|pla_decode_|Equal10~0_combout & +// (((!\z80_|execute_|ctl_mRead~9_combout )) # (!\z80_|pla_decode_|Equal21~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|execute_|ctl_mRead~9_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~3 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_flags_sz_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout = (\z80_|pla_decode_|Equal11~0_combout & (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M3_ff~q )) + + .dataa(gnd), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 .lut_mask = 16'h0C00; +defparam \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~9 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~9_combout = (((!\z80_|execute_|ixy_d~6_combout & !\z80_|nM1_int~2_combout )) # (!\z80_|execute_|ctl_mWrite~4_combout )) # (!\z80_|pla_decode_|Equal8~0_combout ) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|pla_decode_|Equal8~0_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_mWrite~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~9 .lut_mask = 16'h37FF; +defparam \z80_|execute_|ctl_flags_alu~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~2 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~2_combout = ((!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal39~0_combout & !\z80_|pla_decode_|Equal40~1_combout ))) # (!\z80_|execute_|ixy_d~8_combout ) + + .dataa(\z80_|execute_|ixy_d~8_combout ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|pla_decode_|Equal39~0_combout ), + .datad(\z80_|pla_decode_|Equal40~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~2 .lut_mask = 16'h5557; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~10_combout = (\z80_|execute_|ctl_flags_sz_we~3_combout & (!\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout & (\z80_|execute_|ctl_flags_alu~9_combout & \z80_|execute_|ctl_alu_sel_op2_neg~2_combout ))) + + .dataa(\z80_|execute_|ctl_flags_sz_we~3_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), + .datac(\z80_|execute_|ctl_flags_alu~9_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~10 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_flags_alu~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~10_combout = (((!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4])) # (!\z80_|nM1_int~2_combout )) # (!\z80_|pla_decode_|Equal63~0_combout ) + + .dataa(\z80_|pla_decode_|Equal63~0_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~10 .lut_mask = 16'h777F; +defparam \z80_|execute_|ctl_flags_xy_we~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla11M1T1_11 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|pla_decode_|Equal10~0_combout )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|pla_decode_|Equal10~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel_pla11M1T1_11 .lut_mask = 16'h0300; +defparam \z80_|execute_|ctl_pf_sel_pla11M1T1_11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~11 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~11_combout = (\z80_|execute_|ctl_flags_xy_we~10_combout & (!\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout & ((!\z80_|sequencer_|DFFE_T5_ff~q ) # (!\z80_|execute_|ixy_d~15_combout )))) + + .dataa(\z80_|execute_|ctl_flags_xy_we~10_combout ), + .datab(\z80_|execute_|ixy_d~15_combout ), + .datac(\z80_|sequencer_|DFFE_T5_ff~q ), + .datad(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~11 .lut_mask = 16'h002A; +defparam \z80_|execute_|ctl_flags_xy_we~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~11 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~11_combout = (\z80_|execute_|ctl_flags_alu~10_combout & (\z80_|execute_|ctl_flags_xy_we~11_combout & ((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|execute_|ixy_d~15_combout )))) + + .dataa(\z80_|execute_|ctl_flags_alu~10_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~11_combout ), + .datac(\z80_|execute_|ixy_d~15_combout ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~11 .lut_mask = 16'h0888; +defparam \z80_|execute_|ctl_flags_alu~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~1 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~1_combout = (\z80_|execute_|ctl_reg_use_sp~0_combout & \z80_|execute_|nextM~11_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_use_sp~0_combout ), + .datad(\z80_|execute_|nextM~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~1 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_reg_use_sp~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~4 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~4_combout = (\z80_|sequencer_|DFFE_M4_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~4 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_state_alu~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~9_combout = (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|pla_decode_|Equal10~0_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|pla_decode_|Equal10~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~9 .lut_mask = 16'h777F; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~4 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~4_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & (((!\z80_|execute_|ctl_state_alu~4_combout & !\z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|execute_|ctl_mRead~4_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|ctl_mRead~4_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~4 .lut_mask = 16'h3700; +defparam \z80_|execute_|ctl_sw_2d~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~0 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~0_combout = (\z80_|execute_|ctl_mWrite~9_combout & (((!\z80_|execute_|ctl_ir_we~12_combout & !\z80_|execute_|ctl_ir_we~11_combout )))) # (!\z80_|execute_|ctl_mWrite~9_combout & (((!\z80_|execute_|ctl_ir_we~12_combout )) +// # (!\z80_|execute_|ctl_mWrite~5_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~5_combout ), + .datab(\z80_|execute_|ctl_mWrite~9_combout ), + .datac(\z80_|execute_|ctl_ir_we~12_combout ), + .datad(\z80_|execute_|ctl_ir_we~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~0 .lut_mask = 16'h131F; +defparam \z80_|execute_|ctl_flags_sz_we~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~4_combout = (\z80_|execute_|ctl_flags_sz_we~0_combout & (((!\z80_|execute_|ctl_ir_we~12_combout & !\z80_|execute_|ctl_ir_we~11_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .datab(\z80_|execute_|ctl_ir_we~12_combout ), + .datac(\z80_|execute_|ctl_ir_we~11_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~4 .lut_mask = 16'h02AA; +defparam \z80_|execute_|ctl_flags_sz_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y16_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~47 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~47_combout = (\z80_|pla_decode_|Equal8~0_combout & (\z80_|execute_|ctl_mWrite~4_combout & (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_M3_ff~q ))) + + .dataa(\z80_|pla_decode_|Equal8~0_combout ), + .datab(\z80_|execute_|ctl_mWrite~4_combout ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~47 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_op_low~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~3 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~3_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout & (((!\z80_|pla_decode_|Equal21~1_combout & !\z80_|execute_|ctl_mRead~34_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal21~1_combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~3 .lut_mask = 16'h001F; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~12 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~12_combout = (!\z80_|execute_|ctl_alu_op_low~47_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~3_combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~47_combout ), + .datab(\z80_|pla_decode_|Equal20~0_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~12 .lut_mask = 16'h1050; +defparam \z80_|execute_|ctl_flags_alu~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~23 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~23_combout = (((!\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [3])) # (!\z80_|pla_decode_|Equal63~0_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|pla_decode_|Equal63~0_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~23 .lut_mask = 16'h5F7F; +defparam \z80_|execute_|ctl_alu_op_low~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~19 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~19_combout = (\z80_|execute_|ctl_alu_op_low~23_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|pla_decode_|Equal20~0_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|execute_|ctl_alu_op_low~23_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|pla_decode_|Equal20~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~19 .lut_mask = 16'hC4CC; +defparam \z80_|execute_|ctl_flags_xy_we~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~13 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~13_combout = (\z80_|execute_|ctl_sw_2d~4_combout & (\z80_|execute_|ctl_flags_sz_we~4_combout & (\z80_|execute_|ctl_flags_alu~12_combout & \z80_|execute_|ctl_flags_xy_we~19_combout ))) + + .dataa(\z80_|execute_|ctl_sw_2d~4_combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~4_combout ), + .datac(\z80_|execute_|ctl_flags_alu~12_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~13 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_flags_alu~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_hi~4_combout = ((!\z80_|pla_decode_|Equal40~1_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal39~0_combout ))) # (!\z80_|execute_|ixy_d~9_combout ) + + .dataa(\z80_|pla_decode_|Equal40~1_combout ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|pla_decode_|Equal39~0_combout ), + .datad(\z80_|execute_|ixy_d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_hi~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_hi~4 .lut_mask = 16'h01FF; +defparam \z80_|execute_|ctl_reg_out_hi~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~1 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~1_combout = (\z80_|execute_|ctl_reg_out_hi~4_combout & \z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_out_hi~4_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~1 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_sw_4u~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~29 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~29_combout = ((!\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|execute_|ixy_d~15_combout ) + + .dataa(\z80_|execute_|ixy_d~15_combout ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~29 .lut_mask = 16'h555F; +defparam \z80_|execute_|ctl_alu_op_low~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~14 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~14_combout = (\z80_|execute_|ctl_reg_use_sp~1_combout & (\z80_|execute_|ctl_flags_alu~13_combout & (\z80_|execute_|ctl_sw_4u~1_combout & \z80_|execute_|ctl_alu_op_low~29_combout ))) + + .dataa(\z80_|execute_|ctl_reg_use_sp~1_combout ), + .datab(\z80_|execute_|ctl_flags_alu~13_combout ), + .datac(\z80_|execute_|ctl_sw_4u~1_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~29_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~14 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_flags_alu~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout = (\z80_|pla_decode_|Equal63~0_combout & (\z80_|nM1_int~2_combout & (!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4]))) + + .dataa(\z80_|pla_decode_|Equal63~0_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 .lut_mask = 16'h0008; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla82M1T1_16 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout = (!\z80_|ir_|opcode [0] & (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal3~1_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|pla_decode_|Equal3~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel_pla82M1T1_16 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_pf_sel_pla82M1T1_16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~13 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~13_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|execute_|ctl_mRead~4_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|execute_|ctl_mRead~4_combout ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~13 .lut_mask = 16'h777F; +defparam \z80_|execute_|ctl_flags_use_cf2~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~7_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|pla_decode_|Equal13~0_combout ) # (!\z80_|pla_decode_|Equal55~0_combout ))) # (!\z80_|sequencer_|DFFE_M3_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~7 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_flags_cf_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel[0]~2 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel[0]~2_combout = (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (\z80_|execute_|ctl_flags_use_cf2~13_combout & \z80_|execute_|ctl_flags_cf_we~7_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .datac(\z80_|execute_|ctl_flags_use_cf2~13_combout ), + .datad(\z80_|execute_|ctl_flags_cf_we~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel[0]~2 .lut_mask = 16'h3000; +defparam \z80_|execute_|ctl_pf_sel[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_we~5_combout = (\z80_|execute_|ctl_bus_inc_oe~27_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|execute_|ctl_ir_we~8_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|execute_|ctl_bus_inc_oe~27_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_we~5 .lut_mask = 16'hFD00; +defparam \z80_|execute_|ctl_flags_hf_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~10_combout = (\z80_|execute_|ctl_flags_hf_we~5_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|pla_decode_|Equal13~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|execute_|ctl_flags_hf_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~10 .lut_mask = 16'hFD00; +defparam \z80_|execute_|ctl_flags_pf_we~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N8 +cycloneive_lcell_comb \z80_|pla_decode_|Equal68~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal68~2_combout = (\z80_|ir_|opcode [6] & (\z80_|decode_state_|DFFE_instED~q & (!\z80_|ir_|opcode [7] & !\z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|decode_state_|DFFE_instED~q ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal68~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal68~2 .lut_mask = 16'h0008; +defparam \z80_|pla_decode_|Equal68~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~13 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~13_combout = ((!\z80_|execute_|ctl_alu_op_low~27_combout & ((!\z80_|pla_decode_|Equal68~2_combout ) # (!\z80_|pla_decode_|Equal1~4_combout )))) # (!\z80_|nM1_int~2_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~27_combout ), + .datab(\z80_|pla_decode_|Equal1~4_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal68~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~13 .lut_mask = 16'h1F5F; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~2_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout & (\z80_|execute_|ctl_pf_sel[0]~2_combout & (\z80_|execute_|ctl_flags_pf_we~10_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~13_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .datab(\z80_|execute_|ctl_pf_sel[0]~2_combout ), + .datac(\z80_|execute_|ctl_flags_pf_we~10_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~2 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_flags_pf_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~4_combout = (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|execute_|ctl_mWrite~17_combout & ((!\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|ctl_mRead~9_combout )))) # (!\z80_|execute_|ctl_state_alu~2_combout & +// (((!\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|ctl_mRead~9_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ctl_mWrite~17_combout ), + .datac(\z80_|execute_|ctl_mRead~9_combout ), + .datad(\z80_|execute_|ctl_mRead~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~4 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_alu_oe~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y18_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~8_combout = (!\z80_|execute_|ctl_reg_gp_sel~7_combout & \z80_|execute_|setM1~18_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_sel~7_combout ), + .datab(gnd), + .datac(\z80_|execute_|setM1~18_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~8 .lut_mask = 16'h5050; +defparam \z80_|execute_|ctl_flags_xy_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y19_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~20 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~20_combout = (((!\z80_|pla_decode_|Equal13~0_combout ) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|pla_decode_|Equal55~0_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~20 .lut_mask = 16'h7FFF; +defparam \z80_|execute_|ctl_flags_xy_we~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~9 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~9_combout = (\z80_|execute_|ctl_flags_pf_we~2_combout & (\z80_|execute_|ctl_alu_oe~4_combout & (\z80_|execute_|ctl_flags_xy_we~8_combout & \z80_|execute_|ctl_flags_xy_we~20_combout ))) + + .dataa(\z80_|execute_|ctl_flags_pf_we~2_combout ), + .datab(\z80_|execute_|ctl_alu_oe~4_combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~8_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~9 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_flags_xy_we~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~1 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~1_combout = ((!\z80_|execute_|ctl_state_alu~5_combout & (!\z80_|execute_|ctl_state_alu~6_combout & !\z80_|pla_decode_|Equal52~1_combout ))) # (!\z80_|nM1_int~2_combout ) + + .dataa(\z80_|execute_|ctl_state_alu~5_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|pla_decode_|Equal52~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~1 .lut_mask = 16'h3337; +defparam \z80_|execute_|ctl_flags_sz_we~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~1 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~1_combout = (!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal39~0_combout & !\z80_|pla_decode_|Equal40~1_combout )) + + .dataa(gnd), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|pla_decode_|Equal39~0_combout ), + .datad(\z80_|pla_decode_|Equal40~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~1 .lut_mask = 16'h0003; +defparam \z80_|execute_|ctl_bus_db_oe~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~10_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ixy_d~15_combout & ((\z80_|execute_|ctl_bus_db_oe~1_combout ) # (!\z80_|sequencer_|DFFE_M3_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|execute_|ixy_d~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~10 .lut_mask = 16'hF0FD; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~2_combout = (\z80_|execute_|ctl_flags_xy_we~9_combout & (\z80_|execute_|ctl_flags_sz_we~1_combout & \z80_|execute_|ctl_alu_op2_sel_bus~10_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_flags_xy_we~9_combout ), + .datac(\z80_|execute_|ctl_flags_sz_we~1_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~2 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_flags_sz_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y17_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~17 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~17_combout = (((!\z80_|execute_|ctl_ir_we~14_combout & !\z80_|execute_|ctl_ir_we~8_combout )) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|execute_|ctl_ir_we~14_combout ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|execute_|ctl_ir_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~17 .lut_mask = 16'h5F7F; +defparam \z80_|execute_|ctl_flags_alu~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~18 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~18_combout = (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|execute_|ctl_ir_we~7_combout ), + .datad(\z80_|execute_|ctl_ir_we~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~18 .lut_mask = 16'h777F; +defparam \z80_|execute_|ctl_flags_alu~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~6_combout = (\z80_|execute_|ctl_flags_alu~18_combout & (((!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~9_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~15_combout ), + .datab(\z80_|execute_|ctl_flags_alu~18_combout ), + .datac(\z80_|execute_|ctl_ir_we~9_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~6 .lut_mask = 16'h04CC; +defparam \z80_|execute_|ctl_flags_alu~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~19 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~19_combout = (((!\z80_|execute_|ctl_ir_we~14_combout & !\z80_|execute_|ctl_mWrite~17_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|sequencer_|DFFE_T4_ff~q ) + + .dataa(\z80_|execute_|ctl_ir_we~14_combout ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|execute_|ctl_mWrite~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~19 .lut_mask = 16'h3F7F; +defparam \z80_|execute_|ctl_flags_alu~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N24 +cycloneive_lcell_comb \z80_|pla_decode_|Equal1~5 ( +// Equation(s): +// \z80_|pla_decode_|Equal1~5_combout = (!\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal1~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal1~5 .lut_mask = 16'h0F00; +defparam \z80_|pla_decode_|Equal1~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y19_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~0 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~0_combout = (\z80_|pla_decode_|Equal1~5_combout & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|pla_decode_|Equal13~1_combout & !\z80_|sequencer_|DFFE_M1_ff~q ))) + + .dataa(\z80_|pla_decode_|Equal1~5_combout ), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|pla_decode_|Equal13~1_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~0 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_alu_core_R~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|pla_decode_|Equal11~0_combout )) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2 .lut_mask = 16'h1010; +defparam \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~1 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~1_combout = (\z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ) # ((\z80_|execute_|ctl_alu_core_R~0_combout & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|execute_|ctl_alu_core_R~0_combout ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~1 .lut_mask = 16'hFAF2; +defparam \z80_|execute_|ctl_alu_core_R~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~7_combout = ((\z80_|execute_|ctl_alu_core_R~1_combout ) # ((\z80_|pla_decode_|Equal56~0_combout & \z80_|execute_|ixy_d~7_combout ))) # (!\z80_|execute_|ctl_flags_alu~19_combout ) + + .dataa(\z80_|execute_|ctl_flags_alu~19_combout ), + .datab(\z80_|pla_decode_|Equal56~0_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ctl_alu_core_R~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~7 .lut_mask = 16'hFFD5; +defparam \z80_|execute_|ctl_flags_alu~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N12 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~5 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~5_combout = ((!\z80_|pla_decode_|Equal39~0_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal40~1_combout ))) # (!\z80_|execute_|ixy_d~6_combout ) + + .dataa(\z80_|pla_decode_|Equal39~0_combout ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|pla_decode_|Equal40~1_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~5 .lut_mask = 16'h0F1F; +defparam \z80_|reg_control_|reg_sys_we_lo~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N28 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~8 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~8_combout = (\z80_|reg_control_|reg_sys_we_lo~5_combout & (((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|pla_decode_|Equal56~0_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|pla_decode_|Equal56~0_combout ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|reg_control_|reg_sys_we_lo~5_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~8 .lut_mask = 16'h7F00; +defparam \z80_|reg_control_|reg_sys_we_lo~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~8_combout = (((\z80_|execute_|ctl_flags_alu~7_combout ) # (!\z80_|reg_control_|reg_sys_we_lo~8_combout )) # (!\z80_|execute_|ctl_flags_alu~6_combout )) # (!\z80_|execute_|ctl_flags_alu~17_combout ) + + .dataa(\z80_|execute_|ctl_flags_alu~17_combout ), + .datab(\z80_|execute_|ctl_flags_alu~6_combout ), + .datac(\z80_|execute_|ctl_flags_alu~7_combout ), + .datad(\z80_|reg_control_|reg_sys_we_lo~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~8 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|ctl_flags_alu~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~15 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~15_combout = (((\z80_|execute_|ctl_flags_alu~8_combout ) # (!\z80_|execute_|ctl_flags_sz_we~2_combout )) # (!\z80_|execute_|ctl_flags_alu~14_combout )) # (!\z80_|execute_|ctl_flags_alu~11_combout ) + + .dataa(\z80_|execute_|ctl_flags_alu~11_combout ), + .datab(\z80_|execute_|ctl_flags_alu~14_combout ), + .datac(\z80_|execute_|ctl_flags_sz_we~2_combout ), + .datad(\z80_|execute_|ctl_flags_alu~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~15 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_flags_alu~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~7 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~7_combout = (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|execute_|ctl_state_alu~6_combout & ((!\z80_|pla_decode_|Equal52~1_combout )))) # (!\z80_|execute_|ctl_state_alu~2_combout & +// (((!\z80_|execute_|ctl_state_alu~4_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ctl_state_alu~6_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|pla_decode_|Equal52~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~7 .lut_mask = 16'h1537; +defparam \z80_|execute_|ctl_state_alu~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~12 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~12_combout = (\z80_|execute_|ctl_state_alu~7_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|pla_decode_|Equal52~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal52~1_combout ), + .datab(\z80_|execute_|ctl_state_alu~7_combout ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~12 .lut_mask = 16'hCC4C; +defparam \z80_|execute_|ctl_state_alu~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~9 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~9_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # ((\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~9 .lut_mask = 16'h00EF; +defparam \z80_|execute_|ctl_state_alu~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~10 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~10_combout = (\z80_|execute_|ctl_state_alu~9_combout & ((\z80_|execute_|ctl_state_alu~5_combout ) # ((\z80_|pla_decode_|Equal52~1_combout & \z80_|execute_|ctl_state_alu~3_combout )))) # +// (!\z80_|execute_|ctl_state_alu~9_combout & (((\z80_|pla_decode_|Equal52~1_combout & \z80_|execute_|ctl_state_alu~3_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~9_combout ), + .datab(\z80_|execute_|ctl_state_alu~5_combout ), + .datac(\z80_|pla_decode_|Equal52~1_combout ), + .datad(\z80_|execute_|ctl_state_alu~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~10 .lut_mask = 16'hF888; +defparam \z80_|execute_|ctl_state_alu~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~8 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~8_combout = (\z80_|pla_decode_|Equal52~1_combout & (((\z80_|nM1_int~2_combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) # (!\z80_|pla_decode_|Equal52~1_combout & (\z80_|execute_|ctl_state_alu~6_combout & +// ((\z80_|nM1_int~2_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) + + .dataa(\z80_|pla_decode_|Equal52~1_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~8 .lut_mask = 16'hFA32; +defparam \z80_|execute_|ctl_state_alu~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal64~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal64~0_combout = (!\z80_|ir_|opcode [5] & (((\z80_|execute_|ctl_state_alu~10_combout ) # (\z80_|execute_|ctl_state_alu~8_combout )) # (!\z80_|execute_|ctl_state_alu~12_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|execute_|ctl_state_alu~12_combout ), + .datac(\z80_|execute_|ctl_state_alu~10_combout ), + .datad(\z80_|execute_|ctl_state_alu~8_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal64~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal64~0 .lut_mask = 16'h5551; +defparam \z80_|pla_decode_|Equal64~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel[0]~3 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel[0]~3_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # (\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|pla_decode_|Equal64~0_combout ) + + .dataa(\z80_|pla_decode_|Equal64~0_combout ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel[0]~3 .lut_mask = 16'hFDFD; +defparam \z80_|execute_|ctl_pf_sel[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N22 +cycloneive_lcell_comb \z80_|pla_decode_|Equal62~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal62~2_combout = (\z80_|ir_|opcode [5] & (((\z80_|execute_|ctl_state_alu~10_combout ) # (\z80_|execute_|ctl_state_alu~8_combout )) # (!\z80_|execute_|ctl_state_alu~12_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|execute_|ctl_state_alu~12_combout ), + .datac(\z80_|execute_|ctl_state_alu~10_combout ), + .datad(\z80_|execute_|ctl_state_alu~8_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal62~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal62~2 .lut_mask = 16'hAAA2; +defparam \z80_|pla_decode_|Equal62~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~4_combout = (((\z80_|ir_|opcode [3] & \z80_|ir_|opcode [4])) # (!\z80_|nM1_int~2_combout )) # (!\z80_|pla_decode_|Equal62~2_combout ) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|pla_decode_|Equal62~2_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~4 .lut_mask = 16'h8FFF; +defparam \z80_|execute_|ctl_flags_pf_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~46 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~46_combout = (\z80_|execute_|ctl_alu_shift_oe~41_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|pla_decode_|Equal48~0_combout )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|pla_decode_|Equal48~0_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~41_combout ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~46 .lut_mask = 16'hB0F0; +defparam \z80_|execute_|ctl_alu_shift_oe~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~6_combout = (\z80_|pla_decode_|Equal69~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|pla_decode_|Equal69~0_combout ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~6 .lut_mask = 16'h080A; +defparam \z80_|execute_|ctl_flags_pf_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~7_combout = (\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # ((\z80_|execute_|ctl_flags_pf_we~6_combout ) # ((\z80_|execute_|ctl_mRead~34_combout & \z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~34_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .datad(\z80_|execute_|ctl_flags_pf_we~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~7 .lut_mask = 16'hFFF8; +defparam \z80_|execute_|ctl_flags_pf_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~11 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~11_combout = ((\z80_|execute_|ctl_state_alu~10_combout ) # ((\z80_|execute_|ctl_reg_gp_sel~7_combout ) # (\z80_|execute_|ctl_state_alu~8_combout ))) # (!\z80_|execute_|ctl_state_alu~7_combout ) + + .dataa(\z80_|execute_|ctl_state_alu~7_combout ), + .datab(\z80_|execute_|ctl_state_alu~10_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel~7_combout ), + .datad(\z80_|execute_|ctl_state_alu~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~11 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_state_alu~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y17_N26 +cycloneive_lcell_comb \z80_|pla_decode_|Equal62~3 ( +// Equation(s): +// \z80_|pla_decode_|Equal62~3_combout = (\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [4] & (\z80_|execute_|ctl_state_alu~11_combout & \z80_|ir_|opcode [3]))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|execute_|ctl_state_alu~11_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal62~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal62~3 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal62~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~5_combout = (\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_mWrite~17_combout ) # ((\z80_|pla_decode_|Equal11~0_combout ) # (\z80_|pla_decode_|Equal62~3_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~17_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|pla_decode_|Equal62~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~5 .lut_mask = 16'hCCC8; +defparam \z80_|execute_|ctl_flags_pf_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~3_combout = (\z80_|execute_|ctl_flags_pf_we~2_combout & (((!\z80_|execute_|ctl_ir_we~12_combout & !\z80_|execute_|ctl_ir_we~11_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_ir_we~12_combout ), + .datac(\z80_|execute_|ctl_flags_pf_we~2_combout ), + .datad(\z80_|execute_|ctl_ir_we~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~3 .lut_mask = 16'h5070; +defparam \z80_|execute_|ctl_flags_pf_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~8_combout = ((\z80_|execute_|ctl_flags_pf_we~7_combout ) # ((\z80_|execute_|ctl_flags_pf_we~5_combout ) # (!\z80_|execute_|ctl_flags_pf_we~3_combout ))) # (!\z80_|execute_|ctl_alu_shift_oe~46_combout ) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~46_combout ), + .datab(\z80_|execute_|ctl_flags_pf_we~7_combout ), + .datac(\z80_|execute_|ctl_flags_pf_we~5_combout ), + .datad(\z80_|execute_|ctl_flags_pf_we~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~8 .lut_mask = 16'hFDFF; +defparam \z80_|execute_|ctl_flags_pf_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~9 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~9_combout = (((\z80_|execute_|ctl_flags_pf_we~8_combout ) # (!\z80_|execute_|ctl_flags_pf_we~4_combout )) # (!\z80_|execute_|ctl_pf_sel[0]~3_combout )) # (!\z80_|execute_|ctl_flags_xy_we~13_combout ) + + .dataa(\z80_|execute_|ctl_flags_xy_we~13_combout ), + .datab(\z80_|execute_|ctl_pf_sel[0]~3_combout ), + .datac(\z80_|execute_|ctl_flags_pf_we~4_combout ), + .datad(\z80_|execute_|ctl_flags_pf_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~9 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_flags_pf_we~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y20_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~6_combout = (\z80_|execute_|ctl_ir_we~15_combout & (!\z80_|execute_|ctl_mWrite~5_combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|execute_|ctl_ir_we~9_combout )))) # (!\z80_|execute_|ctl_ir_we~15_combout & +// (((!\z80_|nM1_int~2_combout ) # (!\z80_|execute_|ctl_ir_we~9_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~15_combout ), + .datab(\z80_|execute_|ctl_mWrite~5_combout ), + .datac(\z80_|execute_|ctl_ir_we~9_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~6 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_alu_core_S~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y20_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~7_combout = (\z80_|execute_|ctl_alu_core_S~6_combout & (((!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~9_combout )) # (!\z80_|execute_|ctl_alu_oe~0_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~15_combout ), + .datab(\z80_|execute_|ctl_alu_oe~0_combout ), + .datac(\z80_|execute_|ctl_ir_we~9_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~7 .lut_mask = 16'h3700; +defparam \z80_|execute_|ctl_alu_core_S~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~1 ( +// Equation(s): +// \z80_|execute_|ctl_alu_res_oe~1_combout = (\z80_|execute_|ctl_alu_core_S~7_combout & (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|pla_decode_|Equal69~0_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|pla_decode_|Equal69~0_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_res_oe~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_res_oe~1 .lut_mask = 16'h5700; +defparam \z80_|execute_|ctl_alu_res_oe~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_alu_res_oe~0_combout = (\z80_|pla_decode_|Equal8~0_combout & ((\z80_|execute_|ctl_mRead~9_combout ) # ((\z80_|nM1_int~2_combout & \z80_|pla_decode_|Equal55~0_combout )))) # (!\z80_|pla_decode_|Equal8~0_combout & +// (((\z80_|nM1_int~2_combout & \z80_|pla_decode_|Equal55~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal8~0_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_res_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_res_oe~0 .lut_mask = 16'hF888; +defparam \z80_|execute_|ctl_alu_res_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y20_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~4_combout = (\z80_|execute_|ctl_ir_we~7_combout & (!\z80_|execute_|ctl_mWrite~5_combout & ((!\z80_|execute_|ctl_ir_we~10_combout ) # (!\z80_|nM1_int~2_combout )))) # (!\z80_|execute_|ctl_ir_we~7_combout & +// (((!\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~7_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|execute_|ctl_mWrite~5_combout ), + .datad(\z80_|execute_|ctl_ir_we~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~4 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_alu_core_S~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y20_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~5_combout = (\z80_|execute_|ctl_alu_core_S~4_combout & (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|execute_|ctl_alu_oe~0_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~7_combout ), + .datab(\z80_|execute_|ctl_ir_we~10_combout ), + .datac(\z80_|execute_|ctl_alu_oe~0_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~5 .lut_mask = 16'h1F00; +defparam \z80_|execute_|ctl_alu_core_S~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~2 ( +// Equation(s): +// \z80_|execute_|ctl_alu_res_oe~2_combout = (\z80_|execute_|ctl_alu_res_oe~1_combout & (\z80_|execute_|ctl_alu_core_S~5_combout & ((!\z80_|execute_|ctl_mWrite~4_combout ) # (!\z80_|execute_|ctl_alu_res_oe~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_res_oe~1_combout ), + .datab(\z80_|execute_|ctl_alu_res_oe~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_res_oe~2 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_alu_res_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y17_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout = (\z80_|pla_decode_|Equal2~0_combout & (\z80_|execute_|ctl_mWrite~4_combout & (!\z80_|ir_|opcode [0] & \z80_|execute_|ctl_state_alu~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal2~0_combout ), + .datab(\z80_|execute_|ctl_mWrite~4_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|execute_|ctl_state_alu~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N18 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~6 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~6_combout = (\z80_|reg_control_|reg_sys_we_lo~5_combout & (\z80_|execute_|ctl_flags_xy_we~20_combout & ((!\z80_|pla_decode_|Equal56~0_combout ) # (!\z80_|execute_|ctl_alu_op_low~22_combout )))) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~5_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datac(\z80_|pla_decode_|Equal56~0_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~20_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~6 .lut_mask = 16'h2A00; +defparam \z80_|reg_control_|reg_sys_we_lo~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~12 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~12_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|pla_decode_|Equal56~0_combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) # (!\z80_|execute_|ixy_d~7_combout & +// (((!\z80_|nM1_int~2_combout )) # (!\z80_|pla_decode_|Equal20~0_combout ))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|pla_decode_|Equal20~0_combout ), + .datac(\z80_|pla_decode_|Equal56~0_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~12 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_flags_xy_we~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~2_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout & (\z80_|reg_control_|reg_sys_we_lo~6_combout & (\z80_|execute_|ctl_flags_sz_we~1_combout & \z80_|execute_|ctl_flags_xy_we~12_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), + .datab(\z80_|reg_control_|reg_sys_we_lo~6_combout ), + .datac(\z80_|execute_|ctl_flags_sz_we~1_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~2 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_flags_cf_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~3 ( +// Equation(s): +// \z80_|execute_|ctl_alu_res_oe~3_combout = (\z80_|execute_|ctl_flags_alu~11_combout & (\z80_|execute_|ctl_alu_res_oe~2_combout & (\z80_|execute_|ctl_flags_cf_we~2_combout & \z80_|execute_|ctl_flags_pf_we~3_combout ))) + + .dataa(\z80_|execute_|ctl_flags_alu~11_combout ), + .datab(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datac(\z80_|execute_|ctl_flags_cf_we~2_combout ), + .datad(\z80_|execute_|ctl_flags_pf_we~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_res_oe~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_res_oe~3 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_res_oe~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_high ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_high~combout = ((\z80_|pla_decode_|Equal13~2_combout & (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_M3_ff~q ))) # (!\z80_|execute_|ctl_alu_res_oe~3_combout ) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|execute_|ctl_alu_res_oe~3_combout ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_high .lut_mask = 16'h8F0F; +defparam \z80_|execute_|ctl_alu_sel_op2_high .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_zero~4_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|ir_|opcode [0]))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|pla_decode_|Equal3~1_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_zero~4 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_alu_op1_sel_zero~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~12_combout = ((!\z80_|pla_decode_|Equal3~0_combout & ((\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal21~0_combout )))) # (!\z80_|execute_|ctl_state_alu~11_combout ) + + .dataa(\z80_|pla_decode_|Equal3~0_combout ), + .datab(\z80_|pla_decode_|Equal21~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|execute_|ctl_state_alu~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~12 .lut_mask = 16'h51FF; +defparam \z80_|execute_|ctl_alu_core_hf~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y16_N10 +cycloneive_lcell_comb \z80_|pla_decode_|Equal61~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal61~2_combout = (\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal6~0_combout & (!\z80_|ir_|opcode [1] & \z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal61~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal61~2 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal61~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~4_combout = (((!\z80_|execute_|ctl_eval_cond~0_combout & !\z80_|nM1_int~2_combout )) # (!\z80_|pla_decode_|Equal32~0_combout )) # (!\z80_|pla_decode_|Equal63~0_combout ) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|pla_decode_|Equal63~0_combout ), + .datad(\z80_|pla_decode_|Equal32~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~4 .lut_mask = 16'h1FFF; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~13 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~13_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~4_combout & (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|pla_decode_|Equal61~2_combout ))) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|pla_decode_|Equal61~2_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~13 .lut_mask = 16'h3070; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y20_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~14 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~14_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~4_combout & (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (\z80_|execute_|ctl_alu_core_hf~12_combout & \z80_|execute_|ctl_alu_sel_op2_neg~13_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .datab(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~12_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~14 .lut_mask = 16'h1000; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~18 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~18_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~14_combout & (((!\z80_|execute_|ctl_mWrite~17_combout ) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|execute_|ctl_mWrite~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~18 .lut_mask = 16'h2AAA; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~10_combout = (\z80_|execute_|ctl_flags_bus~9_combout & (\z80_|execute_|ctl_alu_shift_oe~20_combout & \z80_|execute_|ctl_bus_db_oe~3_combout )) + + .dataa(\z80_|execute_|ctl_flags_bus~9_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~20_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~3_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~10 .lut_mask = 16'h8080; +defparam \z80_|execute_|ctl_flags_bus~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~2_combout = (\z80_|pla_decode_|Equal44~0_combout ) # ((\z80_|pla_decode_|Equal52~0_combout & \z80_|pla_decode_|Equal33~0_combout )) + + .dataa(gnd), + .datab(\z80_|pla_decode_|Equal44~0_combout ), + .datac(\z80_|pla_decode_|Equal52~0_combout ), + .datad(\z80_|pla_decode_|Equal33~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~2 .lut_mask = 16'hFCCC; +defparam \z80_|execute_|ctl_flags_bus~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y17_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~0 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~0_combout = (\z80_|ir_|opcode [5]) # ((!\z80_|pla_decode_|Equal13~1_combout ) # (!\z80_|pla_decode_|Equal13~0_combout )) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal13~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~0 .lut_mask = 16'hBBFF; +defparam \z80_|execute_|ctl_flags_bus~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~3_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|execute_|ctl_flags_bus~2_combout ) # ((!\z80_|execute_|ctl_flags_bus~0_combout ) # (!\z80_|execute_|ctl_flags_bus~1_combout )))) + + .dataa(\z80_|execute_|ctl_flags_bus~2_combout ), + .datab(\z80_|execute_|ctl_flags_bus~1_combout ), + .datac(\z80_|execute_|ctl_flags_bus~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~3 .lut_mask = 16'hBF00; +defparam \z80_|execute_|ctl_flags_bus~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N10 cycloneive_lcell_comb \z80_|execute_|fMRead~26 ( // Equation(s): -// \z80_|execute_|fMRead~26_combout = (\z80_|execute_|ctl_mRead~15_combout ) # ((\z80_|pla_decode_|Equal44~0_combout & (\z80_|pla_decode_|Equal33~0_combout & !\z80_|decode_state_|use_ixiy~combout ))) +// \z80_|execute_|fMRead~26_combout = (\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_state_alu~2_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_state_alu~6_combout )))) # (!\z80_|execute_|ctl_ir_we~12_combout +// & (((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_state_alu~6_combout )))) - .dataa(\z80_|pla_decode_|Equal44~0_combout ), - .datab(\z80_|execute_|ctl_mRead~15_combout ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|decode_state_|use_ixiy~combout ), + .dataa(\z80_|execute_|ctl_ir_we~12_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), .cin(gnd), .combout(\z80_|execute_|fMRead~26_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~26 .lut_mask = 16'hCCEC; +defparam \z80_|execute_|fMRead~26 .lut_mask = 16'h0777; defparam \z80_|execute_|fMRead~26 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y19_N20 -cycloneive_lcell_comb \z80_|execute_|fMRead~25 ( +// Location: LCCOMB_X29_Y19_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus ( // Equation(s): -// \z80_|execute_|fMRead~25_combout = ((\z80_|sequencer_|DFFE_M2_ff~q & (!\z80_|execute_|ixy_d~4_combout & \z80_|execute_|ctl_mRead~14_combout ))) # (!\z80_|execute_|fMRead~24_combout ) +// \z80_|execute_|ctl_flags_bus~combout = ((\z80_|execute_|ctl_flags_bus~3_combout ) # ((\z80_|execute_|ctl_flags_hf2_we~combout ) # (!\z80_|execute_|fMRead~26_combout ))) # (!\z80_|execute_|ctl_flags_bus~10_combout ) - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|execute_|ixy_d~4_combout ), - .datac(\z80_|execute_|fMRead~24_combout ), - .datad(\z80_|execute_|ctl_mRead~14_combout ), + .dataa(\z80_|execute_|ctl_flags_bus~10_combout ), + .datab(\z80_|execute_|ctl_flags_bus~3_combout ), + .datac(\z80_|execute_|ctl_flags_hf2_we~combout ), + .datad(\z80_|execute_|fMRead~26_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~25_combout ), + .combout(\z80_|execute_|ctl_flags_bus~combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~25 .lut_mask = 16'h2F0F; -defparam \z80_|execute_|fMRead~25 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_flags_bus .lut_mask = 16'hFDFF; +defparam \z80_|execute_|ctl_flags_bus .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|fMRead~27 ( +// Location: LCCOMB_X26_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_lo~9 ( // Equation(s): -// \z80_|execute_|fMRead~27_combout = ((\z80_|execute_|fMRead~25_combout ) # ((\z80_|execute_|fMRead~26_combout & \z80_|execute_|ctl_ir_we~4_combout ))) # (!\z80_|execute_|fMRead~3_combout ) +// \z80_|execute_|ctl_reg_in_lo~9_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q ))) # (!\z80_|pla_decode_|Equal47~0_combout ) - .dataa(\z80_|execute_|fMRead~26_combout ), - .datab(\z80_|execute_|fMRead~3_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|execute_|fMRead~25_combout ), + .dataa(\z80_|pla_decode_|Equal47~0_combout ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|M5~q ), .cin(gnd), - .combout(\z80_|execute_|fMRead~27_combout ), + .combout(\z80_|execute_|ctl_reg_in_lo~9_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~27 .lut_mask = 16'hFFB3; -defparam \z80_|execute_|fMRead~27 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_reg_in_lo~9 .lut_mask = 16'hF5F7; +defparam \z80_|execute_|ctl_reg_in_lo~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y17_N18 -cycloneive_lcell_comb \z80_|execute_|fMRead~33 ( +// Location: LCCOMB_X30_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_oe~0 ( // Equation(s): -// \z80_|execute_|fMRead~33_combout = (\z80_|execute_|fMRead~32_combout ) # ((\z80_|execute_|fMRead~20_combout ) # ((\z80_|execute_|fMRead~23_combout ) # (\z80_|execute_|fMRead~27_combout ))) +// \z80_|execute_|ctl_alu_op1_oe~0_combout = ((\z80_|execute_|ctl_66_oe~2_combout ) # ((\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_alu_shift_oe~14_combout ))) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ) - .dataa(\z80_|execute_|fMRead~32_combout ), - .datab(\z80_|execute_|fMRead~20_combout ), - .datac(\z80_|execute_|fMRead~23_combout ), - .datad(\z80_|execute_|fMRead~27_combout ), + .dataa(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .datab(\z80_|execute_|ctl_66_oe~2_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~33_combout ), + .combout(\z80_|execute_|ctl_alu_op1_oe~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~33 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|fMRead~33 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_alu_op1_oe~0 .lut_mask = 16'hFDDD; +defparam \z80_|execute_|ctl_alu_op1_oe~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y17_N8 -cycloneive_lcell_comb \z80_|execute_|fMRead~35 ( +// Location: LCCOMB_X30_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_oe~1 ( // Equation(s): -// \z80_|execute_|fMRead~35_combout = (\z80_|execute_|fMRead~33_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~20_combout ) # ((\z80_|execute_|fMRead~34_combout & !\z80_|execute_|fMRead~0_combout ))) +// \z80_|execute_|ctl_alu_op1_oe~1_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ) # ((\z80_|execute_|ctl_alu_op1_oe~0_combout ) # ((\z80_|nM1_int~2_combout & \z80_|execute_|ctl_alu_oe~1_combout ))) - .dataa(\z80_|execute_|fMRead~34_combout ), - .datab(\z80_|execute_|fMRead~33_combout ), - .datac(\z80_|execute_|fMRead~0_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~20_combout ), + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_alu_oe~1_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), + .datad(\z80_|execute_|ctl_alu_op1_oe~0_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~35_combout ), + .combout(\z80_|execute_|ctl_alu_op1_oe~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~35 .lut_mask = 16'hFFCE; -defparam \z80_|execute_|fMRead~35 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_alu_op1_oe~1 .lut_mask = 16'hFFF8; +defparam \z80_|execute_|ctl_alu_op1_oe~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y13_N30 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_re ( +// Location: LCCOMB_X23_Y19_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~6 ( // Equation(s): -// \z80_|pin_control_|bus_db_pin_re~combout = (\z80_|pin_control_|bus_db_pin_re~2_combout ) # ((\z80_|execute_|fMRead~35_combout & \z80_|sequencer_|DFFE_T2_ff~q )) +// \z80_|execute_|ctl_alu_bs_oe~6_combout = ((!\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~15_combout ))) # (!\z80_|execute_|ctl_ir_we~4_combout ) + + .dataa(\z80_|execute_|ctl_ir_we~12_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ctl_ir_we~9_combout ), + .datad(\z80_|execute_|ctl_ir_we~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~6 .lut_mask = 16'h3337; +defparam \z80_|execute_|ctl_alu_bs_oe~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~12_combout = (\z80_|execute_|ctl_ir_we~11_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # ((!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M4_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|execute_|ctl_ir_we~11_combout ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~12 .lut_mask = 16'hCC40; +defparam \z80_|execute_|ctl_alu_bs_oe~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~8_combout = ((\z80_|execute_|ctl_alu_bs_oe~12_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~7_combout )) # (!\z80_|execute_|ctl_alu_bs_oe~6_combout ) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~6_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_bs_oe~12_combout ), + .datad(\z80_|execute_|ctl_alu_bs_oe~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~8 .lut_mask = 16'hF5FF; +defparam \z80_|execute_|ctl_alu_bs_oe~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~9_combout = (\z80_|execute_|ctl_ir_we~7_combout & (((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # (\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|execute_|ctl_ir_we~7_combout & (\z80_|execute_|ctl_ir_we~10_combout +// & ((\z80_|execute_|ctl_ir_we~4_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~10_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_ir_we~7_combout ), + .datad(\z80_|execute_|ctl_ir_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~9 .lut_mask = 16'hFAC0; +defparam \z80_|execute_|ctl_alu_bs_oe~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~combout = (\z80_|execute_|ctl_alu_bs_oe~8_combout ) # ((\z80_|execute_|ctl_alu_bs_oe~9_combout ) # ((\z80_|execute_|ctl_ir_we~4_combout & \z80_|pla_decode_|Equal41~2_combout ))) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~8_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(\z80_|execute_|ctl_alu_bs_oe~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe .lut_mask = 16'hFFEA; +defparam \z80_|execute_|ctl_alu_bs_oe .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_oe~0_combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # ((!\z80_|ir_|opcode [3] & \z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_oe~0 .lut_mask = 16'hB0A0; +defparam \z80_|execute_|ctl_alu_op2_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N12 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~0 ( +// Equation(s): +// \z80_|alu_|db_high[3]~0_combout = (\z80_|execute_|ctl_alu_op1_oe~1_combout ) # ((\z80_|execute_|ctl_alu_bs_oe~combout ) # ((\z80_|execute_|ctl_alu_op2_oe~0_combout ) # (!\z80_|execute_|ctl_alu_res_oe~3_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datab(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datac(\z80_|execute_|ctl_alu_res_oe~3_combout ), + .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~0 .lut_mask = 16'hFFEF; +defparam \z80_|alu_|db_high[3]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y19_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla83M1T3_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla83M1T3_2~combout = (\z80_|pla_decode_|Equal1~5_combout & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|pla_decode_|Equal13~1_combout & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal1~5_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|pla_decode_|Equal13~1_combout ), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla83M1T3_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla83M1T3_2 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla83M1T3_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~15 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~15_combout = (!\z80_|pla_decode_|Equal33~1_combout & (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal3~1_combout & \z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~1_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|pla_decode_|Equal3~1_combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~15 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_alu_shift_oe~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~38 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~38_combout = (!\z80_|execute_|ctl_alu_shift_oe~15_combout & (((!\z80_|execute_|ctl_state_alu~4_combout & !\z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|execute_|ctl_mRead~4_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|ctl_mRead~4_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~38 .lut_mask = 16'h0037; +defparam \z80_|execute_|ctl_alu_shift_oe~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y19_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~28 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~28_combout = (\z80_|pla_decode_|Equal1~5_combout & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|pla_decode_|Equal13~1_combout & \z80_|execute_|ctl_eval_cond~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal1~5_combout ), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|pla_decode_|Equal13~1_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~28 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_op_low~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y19_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~6_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla83M1T3_2~combout & (!\z80_|execute_|ctl_alu_op1_sel_bus~16_combout & (\z80_|execute_|ctl_alu_shift_oe~38_combout & !\z80_|execute_|ctl_alu_op_low~28_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla83M1T3_2~combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~38_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~28_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~6 .lut_mask = 16'h0010; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~37 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~37_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_alu_oe~1_combout ) # ((!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & \z80_|execute_|ctl_ir_we~11_combout )))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_ir_we~11_combout ), + .datad(\z80_|execute_|ctl_alu_oe~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~37 .lut_mask = 16'hAA20; +defparam \z80_|execute_|ctl_alu_shift_oe~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~39 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~39_combout = ((\z80_|execute_|ctl_alu_shift_oe~37_combout ) # ((\z80_|execute_|ctl_state_alu~6_combout & \z80_|execute_|ctl_alu_shift_oe~14_combout ))) # (!\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ) + + .dataa(\z80_|execute_|ctl_state_alu~6_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~37_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~39 .lut_mask = 16'hFBF3; +defparam \z80_|execute_|ctl_alu_shift_oe~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_daa ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_sel_daa~combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal63~0_combout & (!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4]))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_sel_daa .lut_mask = 16'h0008; +defparam \z80_|execute_|ctl_flags_cf2_sel_daa .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y17_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~7_combout = (\z80_|execute_|ctl_ir_we~8_combout & (!\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ctl_mWrite~5_combout ) # (!\z80_|execute_|ctl_ir_we~14_combout )))) # (!\z80_|execute_|ctl_ir_we~8_combout +// & (((!\z80_|execute_|ctl_mWrite~5_combout )) # (!\z80_|execute_|ctl_ir_we~14_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|execute_|ctl_ir_we~14_combout ), + .datac(\z80_|execute_|ctl_mWrite~5_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~7 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y17_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~8_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~7_combout & (\z80_|execute_|ctl_flags_alu~17_combout & ((!\z80_|pla_decode_|Equal20~0_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|pla_decode_|Equal20~0_combout ), + .datad(\z80_|execute_|ctl_flags_alu~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~8 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~30 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~30_combout = ((!\z80_|execute_|ixy_d~7_combout & ((\z80_|ir_|opcode [3]) # (!\z80_|execute_|ixy_d~6_combout )))) # (!\z80_|pla_decode_|Equal13~2_combout ) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~30 .lut_mask = 16'h7757; +defparam \z80_|execute_|ctl_alu_op_low~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y18_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~31 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~31_combout = (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (\z80_|execute_|ctl_alu_op1_sel_bus~8_combout & \z80_|execute_|ctl_alu_op_low~30_combout )) .dataa(gnd), - .datab(\z80_|execute_|fMRead~35_combout ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|pin_control_|bus_db_pin_re~2_combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~30_combout ), .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_re~combout ), + .combout(\z80_|execute_|ctl_alu_op_low~31_combout ), .cout()); // synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_re .lut_mask = 16'hFFC0; -defparam \z80_|pin_control_|bus_db_pin_re .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_alu_op_low~31 .lut_mask = 16'h3000; +defparam \z80_|execute_|ctl_alu_op_low~31 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X33_Y15_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a1 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[1]~34_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), +// Location: LCCOMB_X27_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~25 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~25_combout = (\z80_|pla_decode_|Equal13~2_combout & \z80_|ir_|opcode [3]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~25 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_mRead~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~40 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~40_combout = ((\z80_|execute_|ixy_d~9_combout & ((\z80_|execute_|ctl_mRead~25_combout ) # (\z80_|execute_|ctl_mRead~24_combout )))) # (!\z80_|execute_|ctl_flags_xy_we~21_combout ) + + .dataa(\z80_|execute_|ctl_mRead~25_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~21_combout ), + .datac(\z80_|execute_|ixy_d~9_combout ), + .datad(\z80_|execute_|ctl_mRead~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~40 .lut_mask = 16'hF3B3; +defparam \z80_|execute_|ctl_alu_shift_oe~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~42 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~42_combout = ((\z80_|execute_|ctl_alu_shift_oe~39_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~40_combout ) # (!\z80_|execute_|ctl_alu_op_low~31_combout ))) # (!\z80_|execute_|ctl_alu_shift_oe~46_combout ) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~46_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~39_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~31_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~40_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~42 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|ctl_alu_shift_oe~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout = (!\z80_|pla_decode_|Equal33~0_combout & (\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|pla_decode_|Equal44~0_combout & !\z80_|sequencer_|DFFE_M1_ff~q ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|pla_decode_|Equal44~0_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 .lut_mask = 16'h0040; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y18_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~4_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & (\z80_|execute_|ctl_state_alu~7_combout & (!\z80_|execute_|ctl_reg_gp_sel~7_combout & !\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ))) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), + .datab(\z80_|execute_|ctl_state_alu~7_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel~7_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~4 .lut_mask = 16'h0008; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~47 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~47_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|execute_|ctl_ir_we~7_combout & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_M1_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|execute_|ctl_ir_we~7_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~47 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_shift_oe~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~34 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~34_combout = (\z80_|execute_|ctl_ir_we~10_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ctl_alu_shift_oe~47_combout )))) # +// (!\z80_|execute_|ctl_ir_we~10_combout & (((\z80_|execute_|ctl_alu_shift_oe~47_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~10_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~47_combout ), + .datad(\z80_|execute_|ctl_ir_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~34 .lut_mask = 16'h50F8; +defparam \z80_|execute_|ctl_alu_shift_oe~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~35 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~35_combout = (!\z80_|execute_|ctl_alu_bs_oe~8_combout & ((\z80_|execute_|ctl_alu_shift_oe~34_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & \z80_|execute_|ctl_ir_we~10_combout )))) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~8_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~34_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_ir_we~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~35 .lut_mask = 16'h5444; +defparam \z80_|execute_|ctl_alu_shift_oe~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~36 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~36_combout = (((\z80_|execute_|ctl_alu_shift_oe~35_combout ) # (!\z80_|execute_|ctl_flags_bus~9_combout )) # (!\z80_|execute_|ctl_reg_use_sp~1_combout )) # (!\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ), + .datab(\z80_|execute_|ctl_reg_use_sp~1_combout ), + .datac(\z80_|execute_|ctl_flags_bus~9_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~35_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~36 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_alu_shift_oe~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~28 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~28_combout = (\z80_|execute_|ctl_state_alu~4_combout & ((\z80_|execute_|ctl_ir_we~7_combout ) # ((\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ctl_bus_db_oe~1_combout )))) # (!\z80_|execute_|ctl_state_alu~4_combout +// & (\z80_|execute_|ixy_d~7_combout & ((!\z80_|execute_|ctl_bus_db_oe~1_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|execute_|ctl_ir_we~7_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~28 .lut_mask = 16'hA0EC; +defparam \z80_|execute_|ctl_alu_shift_oe~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~44 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~44_combout = (!\z80_|execute_|ctl_alu_op_low~26_combout & (((!\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~26_combout ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|execute_|ctl_mRead~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~44 .lut_mask = 16'h1555; +defparam \z80_|execute_|ctl_alu_shift_oe~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~29 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~29_combout = (\z80_|execute_|ctl_alu_shift_oe~28_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~44_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~20_combout )) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~28_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_shift_oe~20_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~44_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~29 .lut_mask = 16'hAFFF; +defparam \z80_|execute_|ctl_alu_shift_oe~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~16 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~16_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|execute_|ixy_d~15_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|execute_|ixy_d~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~16 .lut_mask = 16'h0F00; +defparam \z80_|execute_|ctl_alu_shift_oe~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~27 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~27_combout = (!\z80_|execute_|ctl_alu_bs_oe~combout & ((\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ) # (\z80_|execute_|ctl_alu_shift_oe~16_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), + .datab(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~27 .lut_mask = 16'h3332; +defparam \z80_|execute_|ctl_alu_shift_oe~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~10_combout = ((\z80_|execute_|ctl_alu_bs_oe~9_combout ) # ((\z80_|execute_|ctl_alu_bs_oe~12_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~7_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~6_combout ) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~6_combout ), + .datab(\z80_|execute_|ctl_alu_bs_oe~9_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~12_combout ), + .datad(\z80_|execute_|ctl_alu_bs_oe~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~10 .lut_mask = 16'hFDFF; +defparam \z80_|execute_|ctl_alu_bs_oe~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~31 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~31_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~3_combout & (\z80_|execute_|ctl_sw_4u~1_combout & ((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout )))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datab(\z80_|pla_decode_|Equal47~0_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), + .datad(\z80_|execute_|ctl_sw_4u~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~31 .lut_mask = 16'h7000; +defparam \z80_|execute_|ctl_alu_shift_oe~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~30 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~30_combout = (\z80_|execute_|ctl_mWrite~5_combout & (!\z80_|execute_|ctl_mWrite~17_combout & ((!\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|ctl_state_alu~2_combout )))) # +// (!\z80_|execute_|ctl_mWrite~5_combout & (((!\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|ctl_state_alu~2_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~5_combout ), + .datab(\z80_|execute_|ctl_mWrite~17_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_mRead~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~30 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_alu_shift_oe~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~32 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~32_combout = (\z80_|execute_|ctl_alu_shift_oe~31_combout & (\z80_|execute_|ctl_alu_shift_oe~30_combout & ((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_mRead~9_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~9_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~31_combout ), + .datac(\z80_|pla_decode_|Equal47~0_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~30_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~32 .lut_mask = 16'h4C00; +defparam \z80_|execute_|ctl_alu_shift_oe~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~33 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~33_combout = (\z80_|execute_|ctl_alu_shift_oe~27_combout ) # ((!\z80_|execute_|ctl_alu_bs_oe~10_combout & ((\z80_|execute_|ctl_alu_shift_oe~29_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~32_combout )))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~29_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~27_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~10_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~32_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~33 .lut_mask = 16'hCECF; +defparam \z80_|execute_|ctl_alu_shift_oe~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y20_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~21 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~21_combout = (\z80_|execute_|ctl_ir_we~15_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # ((!\z80_|execute_|ctl_ir_we~4_combout & \z80_|execute_|ctl_state_alu~4_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~15_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|ctl_state_alu~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~21 .lut_mask = 16'hAA20; +defparam \z80_|execute_|ctl_alu_shift_oe~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y20_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~45 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~45_combout = (\z80_|execute_|ctl_alu_shift_oe~21_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|execute_|ctl_alu_shift_oe~21_combout ), + .datad(\z80_|execute_|ctl_ir_we~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~45 .lut_mask = 16'hD0F0; +defparam \z80_|execute_|ctl_alu_shift_oe~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y20_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~22 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~22_combout = (\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_alu_shift_oe~45_combout ) # (\z80_|execute_|ctl_state_alu~4_combout )))) # +// (!\z80_|execute_|ctl_ir_we~9_combout & (\z80_|execute_|ctl_alu_shift_oe~45_combout )) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~45_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ctl_ir_we~9_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~22 .lut_mask = 16'h3A2A; +defparam \z80_|execute_|ctl_alu_shift_oe~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y20_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~23 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~23_combout = (\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|execute_|ctl_alu_shift_oe~22_combout ) # (\z80_|execute_|ctl_eval_cond~0_combout )))) # +// (!\z80_|execute_|ctl_ir_we~9_combout & (\z80_|execute_|ctl_alu_shift_oe~22_combout )) + + .dataa(\z80_|execute_|ctl_ir_we~9_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~22_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~23 .lut_mask = 16'h44EC; +defparam \z80_|execute_|ctl_alu_shift_oe~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y20_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~24 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~24_combout = (\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_mWrite~9_combout ) # (\z80_|execute_|ctl_alu_shift_oe~23_combout )))) # +// (!\z80_|execute_|ctl_ir_we~12_combout & (((\z80_|execute_|ctl_alu_shift_oe~23_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~12_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ctl_mWrite~9_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~23_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~24 .lut_mask = 16'h7720; +defparam \z80_|execute_|ctl_alu_shift_oe~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y20_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~25 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~25_combout = (\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # (\z80_|execute_|ctl_alu_shift_oe~24_combout )))) # +// (!\z80_|execute_|ctl_ir_we~12_combout & (((\z80_|execute_|ctl_alu_shift_oe~24_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|execute_|ctl_mWrite~5_combout ), + .datac(\z80_|execute_|ctl_ir_we~12_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~25 .lut_mask = 16'h5F40; +defparam \z80_|execute_|ctl_alu_shift_oe~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~26 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~26_combout = (!\z80_|execute_|ctl_alu_bs_oe~12_combout & ((\z80_|execute_|ctl_alu_shift_oe~25_combout ) # ((\z80_|execute_|ctl_mWrite~9_combout & \z80_|execute_|ctl_ir_we~11_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~9_combout ), + .datab(\z80_|execute_|ctl_ir_we~11_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~25_combout ), + .datad(\z80_|execute_|ctl_alu_bs_oe~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~26 .lut_mask = 16'h00F8; +defparam \z80_|execute_|ctl_alu_shift_oe~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~43 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~43_combout = (\z80_|execute_|ctl_alu_shift_oe~42_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~36_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~33_combout ) # (\z80_|execute_|ctl_alu_shift_oe~26_combout ))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~42_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~36_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~33_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~26_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~43 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_alu_shift_oe~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_low ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_low~combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ixy_d~9_combout ) # ((\z80_|execute_|ixy_d~7_combout & !\z80_|ir_|opcode [3])))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ixy_d~9_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_low .lut_mask = 16'hC0E0; +defparam \z80_|execute_|ctl_alu_op1_sel_low .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_zero~5_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal63~0_combout & !\z80_|ir_|opcode [4]))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|pla_decode_|Equal63~0_combout ), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_zero~5 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_alu_op1_sel_zero~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y17_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_zero~combout = (\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # ((\z80_|execute_|ctl_66_oe~2_combout ) # ((\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # (\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .datab(\z80_|execute_|ctl_66_oe~2_combout ), + .datac(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_zero .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_alu_op1_sel_zero .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y17_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~13 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~13_combout = (!\z80_|execute_|ctl_alu_op_low~26_combout & (((!\z80_|pla_decode_|Equal41~2_combout & !\z80_|execute_|ctl_ir_we~11_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~26_combout ), + .datab(\z80_|pla_decode_|Equal41~2_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|execute_|ctl_ir_we~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~13 .lut_mask = 16'h0515; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y19_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~17 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~17_combout = (\z80_|execute_|ctl_flags_xy_we~14_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|pla_decode_|Equal48~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal48~0_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~14_combout ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~17 .lut_mask = 16'hCC4C; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y19_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~14 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~14_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~13_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~17_combout & (\z80_|execute_|ctl_bus_db_oe~0_combout & \z80_|execute_|ctl_alu_op1_sel_bus~8_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~13_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~17_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~0_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~14 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y20_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~3 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~3_combout = (\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ctl_ir_we~15_combout ) # (!\z80_|execute_|ctl_state_alu~2_combout )))) # (!\z80_|execute_|ctl_ir_we~9_combout +// & (((!\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_state_alu~2_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~9_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_ir_we~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~3 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_alu_core_R~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y20_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~4_combout = (\z80_|execute_|ctl_alu_core_R~3_combout & (((!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~9_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~15_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_ir_we~9_combout ), + .datad(\z80_|execute_|ctl_alu_core_R~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~4 .lut_mask = 16'h3700; +defparam \z80_|execute_|ctl_alu_core_R~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|execute_|ctl_ir_we~11_combout & \z80_|sequencer_|DFFE_T4_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|execute_|ctl_ir_we~11_combout ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 .lut_mask = 16'h4400; +defparam \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y20_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~9_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|execute_|ctl_ir_we~10_combout & ((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|ctl_ir_we~7_combout )))) # +// (!\z80_|execute_|ctl_eval_cond~0_combout & (((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|ctl_ir_we~7_combout )))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|ctl_ir_we~10_combout ), + .datac(\z80_|execute_|ctl_ir_we~7_combout ), + .datad(\z80_|execute_|ctl_state_alu~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~9 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~10_combout = (!\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout & (\z80_|execute_|ctl_flags_sz_we~0_combout & (\z80_|execute_|ctl_flags_alu~18_combout & \z80_|execute_|ctl_alu_op1_sel_bus~9_combout +// ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .datac(\z80_|execute_|ctl_flags_alu~18_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~10 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~11_combout = (((\z80_|execute_|ctl_alu_oe~1_combout & \z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~10_combout )) # (!\z80_|execute_|ctl_alu_core_R~4_combout ) + + .dataa(\z80_|execute_|ctl_alu_oe~1_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_alu_core_R~4_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~11 .lut_mask = 16'h8FFF; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~12_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ) # ((\z80_|execute_|ixy_d~15_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T4_ff~q )))) + + .dataa(\z80_|execute_|ixy_d~15_combout ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~12 .lut_mask = 16'hFFA8; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~15 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~15_combout = ((\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~32_combout ) # (!\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ))) # (!\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~32_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~15 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N6 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & ((\z80_|alu_|db_low[3]~17_combout ) # ((!\z80_|alu_|db_high[3]~0_combout & !\z80_|execute_|ctl_alu_shift_oe~43_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datab(\z80_|alu_|db_high[3]~0_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datad(\z80_|alu_|db_low[3]~17_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9 .lut_mask = 16'hAA02; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N4 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~6 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~6_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & ((\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ) # ((\z80_|alu_|db_high[3]~7_combout & \z80_|execute_|ctl_alu_op1_sel_low~combout )))) + + .dataa(\z80_|alu_|db_high[3]~7_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .datad(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~6 .lut_mask = 16'h0F08; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N30 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|ena ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|ena~combout = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~combout ) # (\z80_|execute_|ctl_alu_op1_sel_low~combout )) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|ena .lut_mask = 16'hFFFA; +defparam \z80_|alu_|b2v_op1_latch_mux_low|ena .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y17_N5 +dffeas \z80_|alu_|op1_low[3] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), .devclrn(devclrn), .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), - .portbdataout()); + .q(\z80_|alu_|op1_low [3]), + .prn(vcc)); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; +defparam \z80_|alu_|op1_low[3] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_low[3] .power_up = "low"; // synopsys translate_on -// Location: M9K_X33_Y18_N0 +// Location: LCCOMB_X31_Y17_N4 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~15 ( +// Equation(s): +// \z80_|alu_|db_low[3]~15_combout = (\z80_|execute_|ctl_alu_op2_oe~0_combout & (\z80_|alu_|op2_low [3] & ((\z80_|alu_|op1_low [3]) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout & (((\z80_|alu_|op1_low [3])) +// # (!\z80_|execute_|ctl_alu_op1_oe~1_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datac(\z80_|alu_|op2_low [3]), + .datad(\z80_|alu_|op1_low [3]), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~15 .lut_mask = 16'hF531; +defparam \z80_|alu_|db_low[3]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N24 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~16 ( +// Equation(s): +// \z80_|alu_|db_low[3]~16_combout = (\z80_|alu_|db_low[3]~15_combout & (((\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout & !\z80_|bus_control_|db[5]~15_combout )) # (!\z80_|execute_|ctl_alu_bs_oe~combout ))) + + .dataa(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), + .datab(\z80_|bus_control_|db[5]~15_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datad(\z80_|alu_|db_low[3]~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~16 .lut_mask = 16'h2F00; +defparam \z80_|alu_|db_low[3]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~33 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~33_combout = (\z80_|execute_|ctl_state_alu~3_combout & (((\z80_|execute_|ctl_alu_op_low~24_combout ) # (\z80_|pla_decode_|Equal56~0_combout )))) # (!\z80_|execute_|ctl_state_alu~3_combout & +// (\z80_|execute_|ctl_mWrite~5_combout & ((\z80_|execute_|ctl_alu_op_low~24_combout ) # (\z80_|pla_decode_|Equal56~0_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~3_combout ), + .datab(\z80_|execute_|ctl_mWrite~5_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~24_combout ), + .datad(\z80_|pla_decode_|Equal56~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~33 .lut_mask = 16'hEEE0; +defparam \z80_|execute_|ctl_alu_op_low~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y20_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~34 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~34_combout = (\z80_|execute_|ctl_alu_op_low~33_combout ) # (((\z80_|execute_|ctl_alu_op_low~28_combout ) # (!\z80_|execute_|ctl_alu_op2_sel_bus~4_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~38_combout )) + + .dataa(\z80_|execute_|ctl_alu_op_low~33_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~38_combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~28_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~34 .lut_mask = 16'hFFBF; +defparam \z80_|execute_|ctl_alu_op_low~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~48 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~48_combout = (((!\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|execute_|ctl_alu_op_low~25_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|execute_|ctl_alu_op_low~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~48 .lut_mask = 16'h73FF; +defparam \z80_|execute_|ctl_alu_op_low~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~35 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~35_combout = (\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # (((\z80_|execute_|ctl_alu_op_low~22_combout & \z80_|execute_|ctl_mWrite~17_combout )) # (!\z80_|execute_|ctl_alu_op_low~45_combout )) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~45_combout ), + .datad(\z80_|execute_|ctl_mWrite~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~35 .lut_mask = 16'hEFAF; +defparam \z80_|execute_|ctl_alu_op_low~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~36 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~36_combout = (((\z80_|execute_|ctl_alu_op_low~35_combout ) # (!\z80_|execute_|ctl_alu_core_R~4_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~10_combout )) # (!\z80_|execute_|ctl_alu_op_low~23_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~23_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), + .datac(\z80_|execute_|ctl_alu_core_R~4_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~35_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~36 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_alu_op_low~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y20_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~37 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~37_combout = (\z80_|execute_|ctl_alu_op_low~34_combout ) # (((\z80_|execute_|ctl_alu_op_low~36_combout ) # (!\z80_|execute_|ctl_alu_op_low~48_combout )) # (!\z80_|execute_|ctl_alu_op_low~31_combout )) + + .dataa(\z80_|execute_|ctl_alu_op_low~34_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~31_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~48_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~36_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~37 .lut_mask = 16'hFFBF; +defparam \z80_|execute_|ctl_alu_op_low~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|pla_decode_|Equal21~1_combout & !\z80_|sequencer_|DFFE_M1_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 .lut_mask = 16'h0088; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y20_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~38 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~38_combout = (\z80_|execute_|ixy_d~5_combout & (((\z80_|execute_|ctl_mRead~34_combout ) # (\z80_|pla_decode_|Equal39~0_combout )))) # (!\z80_|execute_|ixy_d~5_combout & (\z80_|execute_|ctl_eval_cond~0_combout & +// (\z80_|execute_|ctl_mRead~34_combout ))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|pla_decode_|Equal39~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~38 .lut_mask = 16'hECE0; +defparam \z80_|execute_|ctl_alu_op_low~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~39 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~39_combout = (\z80_|execute_|ixy_d~9_combout & ((\z80_|pla_decode_|Equal39~0_combout ) # ((\z80_|pla_decode_|Equal40~1_combout )))) # (!\z80_|execute_|ixy_d~9_combout & (((\z80_|execute_|ixy_d~5_combout & +// \z80_|pla_decode_|Equal40~1_combout )))) + + .dataa(\z80_|pla_decode_|Equal39~0_combout ), + .datab(\z80_|execute_|ixy_d~9_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|pla_decode_|Equal40~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~39 .lut_mask = 16'hFC88; +defparam \z80_|execute_|ctl_alu_op_low~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y20_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~40 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~40_combout = (\z80_|execute_|ctl_alu_op_low~37_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ) # ((\z80_|execute_|ctl_alu_op_low~38_combout ) # (\z80_|execute_|ctl_alu_op_low~39_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~37_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), + .datac(\z80_|execute_|ctl_alu_op_low~38_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~39_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~40 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_alu_op_low~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~41 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~41_combout = (\z80_|execute_|ctl_alu_op_low~40_combout ) # ((\z80_|pla_decode_|Equal21~1_combout & ((\z80_|execute_|ixy_d~5_combout ) # (\z80_|execute_|ixy_d~9_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|execute_|ixy_d~9_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~40_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~41 .lut_mask = 16'hFFC8; +defparam \z80_|execute_|ctl_alu_op_low~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~combout = (\z80_|execute_|ctl_alu_op_low~41_combout ) # ((\z80_|execute_|ixy_d~15_combout & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|execute_|ctl_alu_op_low~41_combout ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|execute_|ixy_d~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low .lut_mask = 16'hFECC; +defparam \z80_|execute_|ctl_alu_op_low .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y16_N25 +dffeas \z80_|alu_|result_lo[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_alu_op_low~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|result_lo [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|result_lo[3] .is_wysiwyg = "true"; +defparam \z80_|alu_|result_lo[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~5_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout & (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal20~0_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .datac(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~5 .lut_mask = 16'h0103; +defparam \z80_|execute_|ctl_alu_oe~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~6_combout = (\z80_|execute_|ctl_alu_oe~5_combout & (((!\z80_|execute_|ctl_mRead~24_combout & !\z80_|execute_|ctl_mRead~25_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~24_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|execute_|ctl_alu_oe~5_combout ), + .datad(\z80_|execute_|ctl_mRead~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~6 .lut_mask = 16'h3070; +defparam \z80_|execute_|ctl_alu_oe~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~9_combout = (\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_mWrite~17_combout ) # ((\z80_|execute_|ctl_alu_oe~1_combout ) # (\z80_|pla_decode_|Equal69~0_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~17_combout ), + .datab(\z80_|execute_|ctl_alu_oe~1_combout ), + .datac(\z80_|pla_decode_|Equal69~0_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~9 .lut_mask = 16'hFE00; +defparam \z80_|execute_|ctl_alu_oe~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~12_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~12_combout & !\z80_|execute_|ctl_ir_we~11_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~12_combout ), + .datab(\z80_|execute_|ctl_ir_we~11_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~12 .lut_mask = 16'hFFF1; +defparam \z80_|execute_|ctl_alu_core_S~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~10_combout = ((\z80_|execute_|ctl_alu_oe~9_combout ) # ((!\z80_|execute_|ctl_alu_core_S~12_combout ) # (!\z80_|execute_|ctl_alu_oe~4_combout ))) # (!\z80_|execute_|ctl_alu_oe~6_combout ) + + .dataa(\z80_|execute_|ctl_alu_oe~6_combout ), + .datab(\z80_|execute_|ctl_alu_oe~9_combout ), + .datac(\z80_|execute_|ctl_alu_oe~4_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~10 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_alu_oe~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~2 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~2_combout = ((!\z80_|execute_|ctl_alu_op_low~25_combout & (!\z80_|execute_|ctl_alu_op_low~24_combout & !\z80_|pla_decode_|Equal56~0_combout ))) # (!\z80_|execute_|ixy_d~7_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~25_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~24_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|pla_decode_|Equal56~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~2 .lut_mask = 16'h0F1F; +defparam \z80_|execute_|ctl_alu_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout = (!\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|nM1_int~2_combout & \z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~1_combout ), + .datab(\z80_|pla_decode_|Equal3~1_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~15 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~15_combout = ((!\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_ir_we~8_combout & !\z80_|execute_|ctl_ir_we~10_combout ))) # (!\z80_|nM1_int~2_combout ) + + .dataa(\z80_|execute_|ctl_ir_we~9_combout ), + .datab(\z80_|execute_|ctl_ir_we~8_combout ), + .datac(\z80_|execute_|ctl_ir_we~10_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~15 .lut_mask = 16'h01FF; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~8_combout = (!\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~15_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout & \z80_|execute_|ctl_flags_sz_we~1_combout ))) + + .dataa(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~15_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), + .datad(\z80_|execute_|ctl_flags_sz_we~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~8 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_reg_in_hi~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N6 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~7 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~7_combout = (\z80_|reg_control_|reg_sys_we_lo~6_combout & ((!\z80_|execute_|ixy_d~15_combout ) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|reg_control_|reg_sys_we_lo~6_combout ), + .datac(\z80_|execute_|ixy_d~15_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~7 .lut_mask = 16'h4C4C; +defparam \z80_|reg_control_|reg_sys_we_lo~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~7_combout = (\z80_|execute_|ctl_reg_in_hi~8_combout & (\z80_|reg_control_|reg_sys_we_lo~7_combout & ((!\z80_|pla_decode_|Equal13~2_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~8_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|reg_control_|reg_sys_we_lo~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~7 .lut_mask = 16'h4C00; +defparam \z80_|execute_|ctl_alu_oe~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y17_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~11 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~11_combout = (\z80_|execute_|ctl_flags_use_cf2~13_combout & (((!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~7_combout )) # (!\z80_|execute_|ctl_mWrite~5_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~5_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|execute_|ctl_ir_we~7_combout ), + .datad(\z80_|execute_|ctl_flags_use_cf2~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~11 .lut_mask = 16'h5700; +defparam \z80_|execute_|ctl_mWrite~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_we~5_combout = (\z80_|execute_|ctl_bus_inc_oe~28_combout & (\z80_|execute_|ctl_mWrite~11_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|execute_|ctl_mRead~24_combout )))) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~28_combout ), + .datab(\z80_|execute_|ctl_mRead~24_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|execute_|ctl_mWrite~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_we~5 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_bus_db_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~8_combout = (\z80_|execute_|ctl_reg_in_lo~9_combout & (\z80_|execute_|ctl_alu_oe~2_combout & (\z80_|execute_|ctl_alu_oe~7_combout & \z80_|execute_|ctl_bus_db_we~5_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .datab(\z80_|execute_|ctl_alu_oe~2_combout ), + .datac(\z80_|execute_|ctl_alu_oe~7_combout ), + .datad(\z80_|execute_|ctl_bus_db_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~8 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_oe~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~16 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~16_combout = (\z80_|execute_|ctl_flags_alu~10_combout & (!\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout & (\z80_|execute_|ctl_flags_xy_we~10_combout & !\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ))) + + .dataa(\z80_|execute_|ctl_flags_alu~10_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~10_combout ), + .datad(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~16 .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_flags_alu~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~11_combout = (\z80_|execute_|ctl_alu_oe~10_combout ) # (((\z80_|execute_|ctl_66_oe~2_combout ) # (!\z80_|execute_|ctl_flags_alu~16_combout )) # (!\z80_|execute_|ctl_alu_oe~8_combout )) + + .dataa(\z80_|execute_|ctl_alu_oe~10_combout ), + .datab(\z80_|execute_|ctl_alu_oe~8_combout ), + .datac(\z80_|execute_|ctl_flags_alu~16_combout ), + .datad(\z80_|execute_|ctl_66_oe~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~11 .lut_mask = 16'hFFBF; +defparam \z80_|execute_|ctl_alu_oe~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y19_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~48 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~48_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|pla_decode_|Equal21~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal21~1_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~48 .lut_mask = 16'hD0F0; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_hi~8_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & ((\z80_|execute_|ctl_ir_we~12_combout ) # (!\z80_|execute_|nextM~2_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|execute_|nextM~2_combout ), + .datac(\z80_|execute_|ctl_ir_we~12_combout ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_hi~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_hi~8 .lut_mask = 16'hA200; +defparam \z80_|execute_|ctl_reg_out_hi~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_hi~5_combout = (\z80_|execute_|ctl_reg_out_lo~2_combout & (\z80_|execute_|rsel3~combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|execute_|ctl_mRead~3_combout )))) # (!\z80_|execute_|ctl_reg_out_lo~2_combout & +// (((!\z80_|execute_|ixy_d~7_combout )) # (!\z80_|execute_|ctl_mRead~3_combout ))) + + .dataa(\z80_|execute_|ctl_reg_out_lo~2_combout ), + .datab(\z80_|execute_|ctl_mRead~3_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|rsel3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_hi~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_hi~5 .lut_mask = 16'h3F15; +defparam \z80_|execute_|ctl_reg_out_hi~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~2 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~2_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|execute_|ctl_mWrite~8_combout & ((!\z80_|execute_|ctl_mRead~7_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|execute_|ctl_eval_cond~0_combout & +// (((!\z80_|execute_|ctl_mRead~7_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|ctl_mWrite~8_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|execute_|ctl_mRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~2 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_sw_2u~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~0 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~0_combout = (\z80_|execute_|ctl_state_alu~3_combout & (!\z80_|execute_|ctl_mWrite~6_combout & ((!\z80_|pla_decode_|Equal9~1_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|execute_|ctl_state_alu~3_combout & +// (((!\z80_|pla_decode_|Equal9~1_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~3_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|pla_decode_|Equal9~1_combout ), + .datad(\z80_|execute_|ctl_mWrite~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~0 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_sw_2u~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~3 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~3_combout = (\z80_|execute_|ctl_sw_2u~2_combout & (\z80_|execute_|ctl_sw_2u~0_combout & ((!\z80_|execute_|ctl_mRead~6_combout ) # (!\z80_|execute_|ctl_alu_oe~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_oe~0_combout ), + .datab(\z80_|execute_|ctl_mRead~6_combout ), + .datac(\z80_|execute_|ctl_sw_2u~2_combout ), + .datad(\z80_|execute_|ctl_sw_2u~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~3 .lut_mask = 16'h7000; +defparam \z80_|execute_|ctl_sw_2u~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y15_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~47 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~47_combout = (\z80_|execute_|ctl_sw_2u~3_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|execute_|ctl_mRead~8_combout )) # (!\z80_|sequencer_|M5~q ))) + + .dataa(\z80_|sequencer_|M5~q ), + .datab(\z80_|execute_|ctl_sw_2u~3_combout ), + .datac(\z80_|execute_|ctl_mRead~8_combout ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~47 .lut_mask = 16'hCC4C; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y18_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~33 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~33_combout = (\z80_|execute_|ctl_state_alu~3_combout & (!\z80_|pla_decode_|Equal47~0_combout & ((!\z80_|execute_|ctl_ir_we~4_combout ) # (!\z80_|pla_decode_|Equal34~0_combout )))) # (!\z80_|execute_|ctl_state_alu~3_combout & +// (((!\z80_|execute_|ctl_ir_we~4_combout )) # (!\z80_|pla_decode_|Equal34~0_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~3_combout ), + .datab(\z80_|pla_decode_|Equal34~0_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~33 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_inc_cy~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~37 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~37_combout = (\z80_|execute_|ctl_inc_cy~33_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|sequencer_|DFFE_M4_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|pla_decode_|Equal19~0_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|execute_|ctl_inc_cy~33_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~37 .lut_mask = 16'hF700; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~6 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~6_combout = (\z80_|execute_|ctl_reg_gp_sel~7_combout & (\z80_|ir_|opcode [0] $ ((!\z80_|execute_|comb~0_combout )))) # (!\z80_|execute_|ctl_reg_gp_sel~7_combout & (!\z80_|execute_|ctl_sw_2u~5_combout & (\z80_|ir_|opcode [0] $ +// (!\z80_|execute_|comb~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel~7_combout ), + .datab(\z80_|ir_|opcode [0]), + .datac(\z80_|execute_|comb~0_combout ), + .datad(\z80_|execute_|ctl_sw_2u~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~6 .lut_mask = 16'h82C3; +defparam \z80_|execute_|ctl_sw_2u~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_hi~6_combout = (\z80_|execute_|ctl_reg_out_hi~5_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~37_combout & !\z80_|execute_|ctl_sw_2u~6_combout ))) + + .dataa(\z80_|execute_|ctl_reg_out_hi~5_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~37_combout ), + .datad(\z80_|execute_|ctl_sw_2u~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_hi~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_hi~6 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_out_hi~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_hi~7_combout = (((\z80_|execute_|ctl_reg_out_hi~8_combout ) # (!\z80_|execute_|ctl_reg_out_hi~6_combout )) # (!\z80_|execute_|ctl_reg_out_hi~4_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), + .datab(\z80_|execute_|ctl_reg_out_hi~4_combout ), + .datac(\z80_|execute_|ctl_reg_out_hi~8_combout ), + .datad(\z80_|execute_|ctl_reg_out_hi~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_hi~7 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|ctl_reg_out_hi~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~2 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~2_combout = (\z80_|pla_decode_|Equal3~0_combout & (\z80_|pla_decode_|Equal1~7_combout & (\z80_|pla_decode_|Equal2~0_combout & !\z80_|ir_|opcode [5]))) + + .dataa(\z80_|pla_decode_|Equal3~0_combout ), + .datab(\z80_|pla_decode_|Equal1~7_combout ), + .datac(\z80_|pla_decode_|Equal2~0_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~2 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_mRead~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~6 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~6_combout = (\z80_|pla_decode_|Equal9~1_combout & (!\z80_|execute_|ixy_d~6_combout & ((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) # (!\z80_|pla_decode_|Equal9~1_combout & +// (((!\z80_|execute_|ctl_mRead~9_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|pla_decode_|Equal47~0_combout ), + .datac(\z80_|execute_|ctl_mRead~9_combout ), + .datad(\z80_|execute_|ixy_d~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~6 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_sw_2d~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~7 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~7_combout = (\z80_|execute_|ctl_sw_2d~6_combout & (((!\z80_|execute_|ctl_mRead~2_combout & !\z80_|pla_decode_|Equal6~1_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_mRead~2_combout ), + .datac(\z80_|pla_decode_|Equal6~1_combout ), + .datad(\z80_|execute_|ctl_sw_2d~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~7 .lut_mask = 16'h5700; +defparam \z80_|execute_|ctl_sw_2d~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout = (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal1~4_combout & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|ir_|opcode [0]))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|pla_decode_|Equal1~4_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~8 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~8_combout = (\z80_|execute_|ctl_flags_sz_we~0_combout & (\z80_|execute_|ctl_sw_2d~7_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout & \z80_|execute_|ctl_alu_shift_oe~44_combout ))) + + .dataa(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .datab(\z80_|execute_|ctl_sw_2d~7_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~44_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~8 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_sw_2d~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~7 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~7_combout = (\z80_|execute_|ctl_flags_alu~19_combout & (((!\z80_|execute_|ctl_mRead~25_combout & !\z80_|execute_|ctl_mRead~24_combout )) # (!\z80_|execute_|ixy_d~9_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~25_combout ), + .datab(\z80_|execute_|ctl_flags_alu~19_combout ), + .datac(\z80_|execute_|ixy_d~9_combout ), + .datad(\z80_|execute_|ctl_mRead~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~7 .lut_mask = 16'h0C4C; +defparam \z80_|execute_|ctl_bus_db_oe~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~5 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~5_combout = (\z80_|execute_|ctl_bus_db_oe~7_combout & (((!\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_bus_db_oe~1_combout )) # (!\z80_|execute_|ixy_d~7_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(\z80_|execute_|ctl_bus_db_oe~7_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~5 .lut_mask = 16'h4C0C; +defparam \z80_|execute_|ctl_sw_2d~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~19 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~19_combout = (\z80_|execute_|ctl_mRead~15_combout ) # ((\z80_|pla_decode_|Equal9~1_combout ) # ((!\z80_|pla_decode_|Equal12~1_combout & \z80_|pla_decode_|Equal25~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal12~1_combout ), + .datab(\z80_|execute_|ctl_mRead~15_combout ), + .datac(\z80_|pla_decode_|Equal9~1_combout ), + .datad(\z80_|pla_decode_|Equal25~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~19 .lut_mask = 16'hFDFC; +defparam \z80_|execute_|ctl_mRead~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~18 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~18_combout = (\z80_|execute_|ctl_mRead~8_combout ) # ((\z80_|execute_|ctl_mRead~13_combout ) # ((\z80_|execute_|ctl_mRead~7_combout ) # (\z80_|execute_|ctl_mRead~6_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~8_combout ), + .datab(\z80_|execute_|ctl_mRead~13_combout ), + .datac(\z80_|execute_|ctl_mRead~7_combout ), + .datad(\z80_|execute_|ctl_mRead~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~18 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_mRead~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N26 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~2 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~2_combout = (\z80_|pla_decode_|Equal35~0_combout ) # ((\z80_|pla_decode_|Equal34~0_combout ) # ((\z80_|pla_decode_|Equal37~0_combout ) # (\z80_|pla_decode_|Equal38~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal35~0_combout ), + .datab(\z80_|pla_decode_|Equal34~0_combout ), + .datac(\z80_|pla_decode_|Equal37~0_combout ), + .datad(\z80_|pla_decode_|Equal38~2_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~2 .lut_mask = 16'hFFFE; +defparam \z80_|reg_control_|reg_sys_we_lo~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal24~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal24~1_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal1~7_combout & \z80_|pla_decode_|Equal9~0_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal2~0_combout ), + .datac(\z80_|pla_decode_|Equal1~7_combout ), + .datad(\z80_|pla_decode_|Equal9~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal24~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal24~1 .lut_mask = 16'h4000; +defparam \z80_|pla_decode_|Equal24~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N12 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~3 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~3_combout = (\z80_|pla_decode_|Equal29~0_combout ) # ((\z80_|pla_decode_|Equal19~0_combout ) # ((\z80_|reg_control_|reg_sys_we_lo~2_combout ) # (\z80_|pla_decode_|Equal24~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal29~0_combout ), + .datab(\z80_|pla_decode_|Equal19~0_combout ), + .datac(\z80_|reg_control_|reg_sys_we_lo~2_combout ), + .datad(\z80_|pla_decode_|Equal24~1_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~3 .lut_mask = 16'hFFFE; +defparam \z80_|reg_control_|reg_sys_we_lo~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N2 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~4 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~4_combout = (\z80_|reg_control_|reg_sys_we_lo~3_combout & (!\z80_|execute_|ctl_state_alu~2_combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) # +// (!\z80_|reg_control_|reg_sys_we_lo~3_combout & (((!\z80_|execute_|ctl_state_alu~4_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~3_combout ), + .datab(\z80_|pla_decode_|Equal47~0_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~4 .lut_mask = 16'h135F; +defparam \z80_|reg_control_|reg_sys_we_lo~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~20 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~20_combout = (\z80_|reg_control_|reg_sys_we_lo~4_combout & (((!\z80_|execute_|ctl_mRead~19_combout & !\z80_|execute_|ctl_mRead~18_combout )) # (!\z80_|execute_|ctl_state_alu~2_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~19_combout ), + .datab(\z80_|execute_|ctl_mRead~18_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|reg_control_|reg_sys_we_lo~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~20 .lut_mask = 16'h1F00; +defparam \z80_|execute_|ctl_mRead~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~5_combout = ((!\z80_|execute_|ctl_mRead~13_combout & (!\z80_|execute_|ctl_mRead~15_combout & !\z80_|execute_|ctl_mRead~16_combout ))) # (!\z80_|execute_|ixy_d~6_combout ) + + .dataa(\z80_|execute_|ctl_mRead~13_combout ), + .datab(\z80_|execute_|ctl_mRead~15_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ctl_mRead~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~5 .lut_mask = 16'h0F1F; +defparam \z80_|execute_|ctl_reg_in_hi~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y17_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~22 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~22_combout = (\z80_|execute_|ctl_mRead~20_combout & (\z80_|execute_|ctl_reg_in_hi~5_combout & ((!\z80_|execute_|ctl_mRead~16_combout ) # (!\z80_|execute_|ctl_state_alu~4_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|ctl_mRead~20_combout ), + .datac(\z80_|execute_|ctl_mRead~16_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~22 .lut_mask = 16'h4C00; +defparam \z80_|execute_|ctl_mRead~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout = (\z80_|execute_|ixy_d~6_combout & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal52~0_combout & !\z80_|ir_|opcode [0]))) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|pla_decode_|Equal3~1_combout ), + .datac(\z80_|pla_decode_|Equal52~0_combout ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~6_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & (((!\z80_|pla_decode_|Equal35~0_combout & !\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|execute_|ixy_d~6_combout ))) + + .dataa(\z80_|pla_decode_|Equal35~0_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~6 .lut_mask = 16'h0037; +defparam \z80_|execute_|ctl_reg_in_hi~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~2_combout = (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|M5~q ) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|sequencer_|M5~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~2 .lut_mask = 16'hAA00; +defparam \z80_|execute_|ctl_reg_in_hi~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|setM1~30 ( +// Equation(s): +// \z80_|execute_|setM1~30_combout = (\z80_|execute_|ixy_d~6_combout & (!\z80_|execute_|ctl_mRead~14_combout & ((!\z80_|execute_|ctl_mRead~15_combout ) # (!\z80_|execute_|ctl_reg_in_hi~2_combout )))) # (!\z80_|execute_|ixy_d~6_combout & +// (((!\z80_|execute_|ctl_mRead~15_combout )) # (!\z80_|execute_|ctl_reg_in_hi~2_combout ))) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datac(\z80_|execute_|ctl_mRead~14_combout ), + .datad(\z80_|execute_|ctl_mRead~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~30 .lut_mask = 16'h135F; +defparam \z80_|execute_|setM1~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~23 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~23_combout = (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|execute_|ctl_mRead~14_combout & ((!\z80_|execute_|ctl_mRead~15_combout ) # (!\z80_|execute_|ctl_state_alu~4_combout )))) # (!\z80_|execute_|ctl_state_alu~2_combout +// & (((!\z80_|execute_|ctl_mRead~15_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_mRead~14_combout ), + .datad(\z80_|execute_|ctl_mRead~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~23 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_mRead~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~6_combout = (\z80_|execute_|setM1~30_combout & (\z80_|execute_|ctl_mRead~23_combout & ((!\z80_|pla_decode_|Equal6~1_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) + + .dataa(\z80_|execute_|setM1~30_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|execute_|ctl_mRead~23_combout ), + .datad(\z80_|pla_decode_|Equal6~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~6 .lut_mask = 16'h20A0; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~3_combout = ((!\z80_|execute_|ctl_mRead~7_combout & (!\z80_|execute_|ctl_mRead~8_combout & !\z80_|execute_|ctl_mRead~6_combout ))) # (!\z80_|execute_|ixy_d~6_combout ) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|execute_|ctl_mRead~7_combout ), + .datac(\z80_|execute_|ctl_mRead~8_combout ), + .datad(\z80_|execute_|ctl_mRead~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~3 .lut_mask = 16'h5557; +defparam \z80_|execute_|ctl_reg_in_hi~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~10 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~10_combout = (\z80_|execute_|ctl_flags_alu~17_combout & (\z80_|execute_|ctl_flags_alu~6_combout & \z80_|execute_|ctl_reg_in_hi~3_combout )) + + .dataa(\z80_|execute_|ctl_flags_alu~17_combout ), + .datab(\z80_|execute_|ctl_flags_alu~6_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_in_hi~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~10 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_mWrite~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y18_N26 +cycloneive_lcell_comb \z80_|execute_|fMRead~18 ( +// Equation(s): +// \z80_|execute_|fMRead~18_combout = (\z80_|execute_|ctl_ir_we~15_combout & (!\z80_|execute_|ctl_state_alu~2_combout & ((!\z80_|execute_|ctl_mRead~16_combout ) # (!\z80_|execute_|ctl_reg_in_hi~2_combout )))) # (!\z80_|execute_|ctl_ir_we~15_combout & +// (((!\z80_|execute_|ctl_mRead~16_combout )) # (!\z80_|execute_|ctl_reg_in_hi~2_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~15_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_mRead~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~18 .lut_mask = 16'h135F; +defparam \z80_|execute_|fMRead~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N14 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_pc~0_combout = ((!\z80_|pla_decode_|Equal37~0_combout & ((!\z80_|pla_decode_|Equal24~0_combout ) # (!\z80_|pla_decode_|Equal9~0_combout )))) # (!\z80_|execute_|ixy_d~6_combout ) + + .dataa(\z80_|pla_decode_|Equal37~0_combout ), + .datab(\z80_|pla_decode_|Equal9~0_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|pla_decode_|Equal24~0_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_pc~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_pc~0 .lut_mask = 16'h1F5F; +defparam \z80_|reg_control_|reg_sel_pc~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N8 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~1 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_pc~1_combout = (\z80_|pla_decode_|Equal29~0_combout & (!\z80_|execute_|ixy_d~6_combout & ((!\z80_|execute_|ctl_reg_in_hi~2_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) # (!\z80_|pla_decode_|Equal29~0_combout & +// (((!\z80_|execute_|ctl_reg_in_hi~2_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal29~0_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|pla_decode_|Equal47~0_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_pc~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_pc~1 .lut_mask = 16'h0777; +defparam \z80_|reg_control_|reg_sel_pc~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N18 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~2 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_pc~2_combout = (\z80_|reg_control_|reg_sel_pc~0_combout & (\z80_|reg_control_|reg_sel_pc~1_combout & ((!\z80_|pla_decode_|Equal38~2_combout ) # (!\z80_|execute_|ixy_d~6_combout )))) + + .dataa(\z80_|reg_control_|reg_sel_pc~0_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|reg_control_|reg_sel_pc~1_combout ), + .datad(\z80_|pla_decode_|Equal38~2_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_pc~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_pc~2 .lut_mask = 16'h20A0; +defparam \z80_|reg_control_|reg_sel_pc~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y18_N18 +cycloneive_lcell_comb \z80_|execute_|fMRead~19 ( +// Equation(s): +// \z80_|execute_|fMRead~19_combout = (\z80_|reg_control_|reg_sel_pc~2_combout & (\z80_|execute_|ctl_state_alu~7_combout & ((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|ctl_ir_we~7_combout )))) + + .dataa(\z80_|reg_control_|reg_sel_pc~2_combout ), + .datab(\z80_|execute_|ctl_ir_we~7_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_state_alu~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~19 .lut_mask = 16'h2A00; +defparam \z80_|execute_|fMRead~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|fMRead~20 ( +// Equation(s): +// \z80_|execute_|fMRead~20_combout = (\z80_|execute_|ctl_mWrite~10_combout & (\z80_|execute_|ctl_sw_2d~4_combout & (\z80_|execute_|fMRead~18_combout & \z80_|execute_|fMRead~19_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~10_combout ), + .datab(\z80_|execute_|ctl_sw_2d~4_combout ), + .datac(\z80_|execute_|fMRead~18_combout ), + .datad(\z80_|execute_|fMRead~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~20 .lut_mask = 16'h8000; +defparam \z80_|execute_|fMRead~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|fMRead~21 ( +// Equation(s): +// \z80_|execute_|fMRead~21_combout = (\z80_|execute_|ctl_mRead~22_combout & (\z80_|execute_|ctl_reg_in_hi~6_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~6_combout & \z80_|execute_|fMRead~20_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~22_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~6_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), + .datad(\z80_|execute_|fMRead~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~21 .lut_mask = 16'h8000; +defparam \z80_|execute_|fMRead~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~9 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~9_combout = (\z80_|execute_|ctl_sw_2d~8_combout & (\z80_|execute_|ctl_sw_2d~5_combout & (!\z80_|execute_|ctl_alu_shift_oe~16_combout & \z80_|execute_|fMRead~21_combout ))) + + .dataa(\z80_|execute_|ctl_sw_2d~8_combout ), + .datab(\z80_|execute_|ctl_sw_2d~5_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~16_combout ), + .datad(\z80_|execute_|fMRead~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~9 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_sw_2d~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~14 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~14_combout = (!\z80_|execute_|ctl_mRead~12_combout & (((\z80_|decode_state_|in_halt~q ) # (!\z80_|pla_decode_|Equal77~0_combout )) # (!\z80_|pla_decode_|Equal33~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|decode_state_|in_halt~q ), + .datac(\z80_|execute_|ctl_mRead~12_combout ), + .datad(\z80_|pla_decode_|Equal77~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~14 .lut_mask = 16'h0D0F; +defparam \z80_|execute_|ctl_sw_2d~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~8 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~8_combout = (((\z80_|ir_|opcode [5] & !\z80_|ir_|opcode [4])) # (!\z80_|ir_|opcode [3])) # (!\z80_|pla_decode_|Equal12~0_combout ) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|pla_decode_|Equal12~0_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~8 .lut_mask = 16'h2FFF; +defparam \z80_|execute_|ctl_sw_1d~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~10 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~10_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (((\z80_|execute_|rsel3~combout & \z80_|execute_|ctl_iorw~10_combout )) # (!\z80_|execute_|nextM~2_combout ))) + + .dataa(\z80_|execute_|rsel3~combout ), + .datab(\z80_|execute_|ctl_iorw~10_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|nextM~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~10 .lut_mask = 16'h80F0; +defparam \z80_|execute_|ctl_sw_2d~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~11 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~11_combout = (\z80_|execute_|ctl_sw_2d~10_combout ) # ((\z80_|nM1_int~2_combout & ((!\z80_|execute_|ctl_sw_1d~8_combout ) # (!\z80_|execute_|ctl_sw_2d~14_combout )))) + + .dataa(\z80_|execute_|ctl_sw_2d~14_combout ), + .datab(\z80_|execute_|ctl_sw_1d~8_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_sw_2d~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~11 .lut_mask = 16'hFF70; +defparam \z80_|execute_|ctl_sw_2d~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~12 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~12_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|execute_|rsel3~combout & ((\z80_|execute_|ctl_alu_shift_oe~15_combout ) # (\z80_|execute_|ctl_alu_op_low~28_combout )))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~15_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~28_combout ), + .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datad(\z80_|execute_|rsel3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~12 .lut_mask = 16'hFEF0; +defparam \z80_|execute_|ctl_sw_2d~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~13 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~13_combout = ((\z80_|execute_|ctl_sw_2d~11_combout ) # ((\z80_|execute_|ctl_sw_2d~12_combout ) # (!\z80_|execute_|ctl_reg_out_lo~7_combout ))) # (!\z80_|execute_|ctl_sw_2d~9_combout ) + + .dataa(\z80_|execute_|ctl_sw_2d~9_combout ), + .datab(\z80_|execute_|ctl_sw_2d~11_combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .datad(\z80_|execute_|ctl_sw_2d~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~13 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|ctl_sw_2d~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N8 +cycloneive_lcell_comb \z80_|alu_|db[7]~9 ( +// Equation(s): +// \z80_|alu_|db[7]~9_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout ) # ((\z80_|execute_|ctl_sw_2d~13_combout ) # (\z80_|execute_|ctl_alu_oe~11_combout )) + + .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_sw_2d~13_combout ), + .datad(\z80_|execute_|ctl_alu_oe~11_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[7]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[7]~9 .lut_mask = 16'hFFFA; +defparam \z80_|alu_|db[7]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N0 +cycloneive_lcell_comb \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 ( +// Equation(s): +// \z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout = (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )) # (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ))) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 .lut_mask = 16'h1333; +defparam \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout = (\z80_|ir_|opcode [3] & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|pla_decode_|Equal63~0_combout & \z80_|ir_|opcode [4]))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|pla_decode_|Equal63~0_combout ), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~32 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~32_combout = (((!\z80_|pla_decode_|Equal3~0_combout & !\z80_|pla_decode_|Equal21~0_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal63~0_combout ) + + .dataa(\z80_|pla_decode_|Equal63~0_combout ), + .datab(\z80_|pla_decode_|Equal3~0_combout ), + .datac(\z80_|pla_decode_|Equal21~0_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~32 .lut_mask = 16'h57FF; +defparam \z80_|execute_|ctl_alu_op_low~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N2 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~2 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~2_combout = ((!\z80_|pla_decode_|Equal20~0_combout & ((!\z80_|pla_decode_|Equal68~2_combout ) # (!\z80_|pla_decode_|Equal1~4_combout )))) # (!\z80_|nM1_int~2_combout ) + + .dataa(\z80_|pla_decode_|Equal20~0_combout ), + .datab(\z80_|pla_decode_|Equal1~4_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal68~2_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~2 .lut_mask = 16'h1F5F; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~22 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~22_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|ir_|opcode [4])) # (!\z80_|pla_decode_|Equal63~0_combout )) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~22 .lut_mask = 16'hFBFF; +defparam \z80_|execute_|ctl_flags_xy_we~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N28 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~3 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~3_combout = (\z80_|execute_|ctl_alu_op_low~32_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~2_combout & \z80_|execute_|ctl_flags_xy_we~22_combout )) + + .dataa(\z80_|execute_|ctl_alu_op_low~32_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~2_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_flags_xy_we~22_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~3 .lut_mask = 16'h8800; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y18_N2 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~4 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~4_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~3_combout & (\z80_|execute_|ctl_flags_pf_we~10_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~8_combout & \z80_|execute_|ctl_alu_op_low~45_combout ))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~3_combout ), + .datab(\z80_|execute_|ctl_flags_pf_we~10_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~45_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~4 .lut_mask = 16'h8000; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N16 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~5 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~5_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout & (((!\z80_|pla_decode_|Equal21~0_combout & !\z80_|pla_decode_|Equal32~0_combout )) # (!\z80_|pla_decode_|Equal62~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal21~0_combout ), + .datab(\z80_|pla_decode_|Equal32~0_combout ), + .datac(\z80_|pla_decode_|Equal62~2_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~5 .lut_mask = 16'h1F00; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N8 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout = (\z80_|execute_|ctl_alu_shift_oe~38_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|execute_|ctl_ir_we~11_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|execute_|ctl_alu_shift_oe~38_combout ), + .datac(\z80_|execute_|ctl_ir_we~11_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 .lut_mask = 16'hCC4C; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N2 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout & (\z80_|execute_|ctl_flags_sz_we~4_combout & ((!\z80_|pla_decode_|Equal62~2_combout ) # (!\z80_|pla_decode_|Equal9~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal9~0_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ), + .datac(\z80_|pla_decode_|Equal62~2_combout ), + .datad(\z80_|execute_|ctl_flags_sz_we~4_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 .lut_mask = 16'h4C00; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~15 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~15_combout = (\z80_|ir_|opcode [5]) # (((!\z80_|pla_decode_|Equal32~0_combout & !\z80_|pla_decode_|Equal9~0_combout )) # (!\z80_|execute_|ctl_state_alu~11_combout )) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|execute_|ctl_state_alu~11_combout ), + .datac(\z80_|pla_decode_|Equal32~0_combout ), + .datad(\z80_|pla_decode_|Equal9~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~15 .lut_mask = 16'hBBBF; +defparam \z80_|execute_|ctl_alu_core_hf~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N8 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~6 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~6_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout & \z80_|execute_|ctl_alu_core_hf~15_combout ) + + .dataa(gnd), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~15_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~6 .lut_mask = 16'hC0C0; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N10 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~7 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~7_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~5_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~9_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout & !\z80_|execute_|ctl_alu_core_R~1_combout ))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~9_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ), + .datad(\z80_|execute_|ctl_alu_core_R~1_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~7 .lut_mask = 16'h0080; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|ir_|opcode [3]))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N20 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout = (\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ) # ((\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal10~0_combout ) # (\z80_|pla_decode_|Equal61~2_combout )))) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal61~2_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 .lut_mask = 16'hFCEC; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~17 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~17_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal3~1_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~17 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N18 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ) # ((\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ) # ((\z80_|alu_control_|db[1]~26_combout & \z80_|execute_|ctl_flags_bus~combout ))) + + .dataa(\z80_|alu_control_|db[1]~26_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ), + .datac(\z80_|execute_|ctl_flags_bus~combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 .lut_mask = 16'hFFEC; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N4 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout = ((\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ) # ((\z80_|alu_|db_high[3]~7_combout & \z80_|execute_|ctl_flags_alu~15_combout ))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ) + + .dataa(\z80_|alu_|db_high[3]~7_combout ), + .datab(\z80_|execute_|ctl_flags_alu~15_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 .lut_mask = 16'hFF8F; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_nf_we~3_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal10~0_combout ) # ((\z80_|pla_decode_|Equal11~0_combout ) # (\z80_|pla_decode_|Equal61~2_combout )))) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal61~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_nf_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_nf_we~3 .lut_mask = 16'hF0E0; +defparam \z80_|execute_|ctl_flags_nf_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y20_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~0 ( +// Equation(s): +// \z80_|execute_|ctl_flags_nf_we~0_combout = (\z80_|pla_decode_|Equal61~2_combout & (!\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|execute_|ctl_mRead~34_combout )))) # (!\z80_|pla_decode_|Equal61~2_combout & +// (((!\z80_|execute_|ixy_d~5_combout )) # (!\z80_|execute_|ctl_mRead~34_combout ))) + + .dataa(\z80_|pla_decode_|Equal61~2_combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_nf_we~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_nf_we~0 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_flags_nf_we~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y17_N0 +cycloneive_lcell_comb \z80_|pla_decode_|Equal73~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal73~2_combout = (\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [4] & (\z80_|execute_|ctl_state_alu~11_combout & \z80_|ir_|opcode [3]))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|execute_|ctl_state_alu~11_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal73~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal73~2 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal73~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N26 +cycloneive_lcell_comb \z80_|pla_decode_|Equal72~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal72~2_combout = (\z80_|ir_|opcode [5] & (\z80_|execute_|ctl_state_alu~11_combout & (\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [3]))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|execute_|ctl_state_alu~11_combout ), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal72~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal72~2 .lut_mask = 16'h0080; +defparam \z80_|pla_decode_|Equal72~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y20_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~1 ( +// Equation(s): +// \z80_|execute_|ctl_flags_nf_we~1_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout & (\z80_|execute_|ctl_flags_nf_we~0_combout & (!\z80_|pla_decode_|Equal73~2_combout & !\z80_|pla_decode_|Equal72~2_combout ))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ), + .datab(\z80_|execute_|ctl_flags_nf_we~0_combout ), + .datac(\z80_|pla_decode_|Equal73~2_combout ), + .datad(\z80_|pla_decode_|Equal72~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_nf_we~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_nf_we~1 .lut_mask = 16'h0008; +defparam \z80_|execute_|ctl_flags_nf_we~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_nf_we~2_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~18_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout & (\z80_|execute_|ctl_alu_core_hf~15_combout & \z80_|execute_|ctl_flags_nf_we~1_combout ))) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~15_combout ), + .datad(\z80_|execute_|ctl_flags_nf_we~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_nf_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_nf_we~2 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_flags_nf_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~5_combout = (\z80_|sequencer_|DFFE_T4_ff~q ) # ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~5 .lut_mask = 16'hFFBB; +defparam \z80_|execute_|ctl_flags_sz_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~6_combout = (\z80_|execute_|ctl_flags_sz_we~5_combout & ((\z80_|execute_|ctl_alu_core_R~0_combout ) # ((\z80_|pla_decode_|Equal48~0_combout & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) # +// (!\z80_|execute_|ctl_flags_sz_we~5_combout & (((\z80_|pla_decode_|Equal48~0_combout & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) + + .dataa(\z80_|execute_|ctl_flags_sz_we~5_combout ), + .datab(\z80_|execute_|ctl_alu_core_R~0_combout ), + .datac(\z80_|pla_decode_|Equal48~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~6 .lut_mask = 16'hF888; +defparam \z80_|execute_|ctl_flags_sz_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_nf_we~4_combout = (\z80_|execute_|ctl_flags_nf_we~3_combout ) # (((\z80_|execute_|ctl_flags_sz_we~6_combout ) # (!\z80_|execute_|ctl_flags_xy_we~14_combout )) # (!\z80_|execute_|ctl_flags_nf_we~2_combout )) + + .dataa(\z80_|execute_|ctl_flags_nf_we~3_combout ), + .datab(\z80_|execute_|ctl_flags_nf_we~2_combout ), + .datac(\z80_|execute_|ctl_flags_sz_we~6_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_nf_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_nf_we~4 .lut_mask = 16'hFBFF; +defparam \z80_|execute_|ctl_flags_nf_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N24 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~8 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~8_combout = (\z80_|execute_|ctl_flags_nf_we~4_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~7_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ))) # (!\z80_|execute_|ctl_flags_nf_we~4_combout & +// (((\z80_|alu_flags_|DFFE_inst_latch_nf~q )))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~7_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .datad(\z80_|execute_|ctl_flags_nf_we~4_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~8 .lut_mask = 16'h88F0; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y19_N25 +dffeas \z80_|alu_flags_|DFFE_inst_latch_nf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~14 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_cpl~14_combout = (\z80_|ir_|opcode [4]) # (!\z80_|pla_decode_|Equal63~0_combout ) + + .dataa(gnd), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(gnd), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_cpl~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_cpl~14 .lut_mask = 16'hFF33; +defparam \z80_|execute_|ctl_flags_hf_cpl~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_cpl~10_combout = (\z80_|execute_|ctl_flags_hf_cpl~14_combout & (!\z80_|execute_|ctl_alu_op_low~27_combout & (!\z80_|execute_|ctl_state_alu~5_combout & !\z80_|pla_decode_|Equal68~3_combout ))) + + .dataa(\z80_|execute_|ctl_flags_hf_cpl~14_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~27_combout ), + .datac(\z80_|execute_|ctl_state_alu~5_combout ), + .datad(\z80_|pla_decode_|Equal68~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_cpl~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_cpl~10 .lut_mask = 16'h0002; +defparam \z80_|execute_|ctl_flags_hf_cpl~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal45~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal45~0_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [1] & \z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~1_combout ), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal45~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal45~0 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal45~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~11 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_cpl~11_combout = (\z80_|execute_|ctl_state_alu~6_combout ) # ((\z80_|pla_decode_|Equal52~1_combout ) # ((\z80_|pla_decode_|Equal45~0_combout & !\z80_|decode_state_|use_ixiy~combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~6_combout ), + .datab(\z80_|pla_decode_|Equal45~0_combout ), + .datac(\z80_|decode_state_|use_ixiy~combout ), + .datad(\z80_|pla_decode_|Equal52~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_cpl~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_cpl~11 .lut_mask = 16'hFFAE; +defparam \z80_|execute_|ctl_flags_hf_cpl~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~12 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_cpl~12_combout = ((\z80_|execute_|ctl_alu_op_low~25_combout ) # ((\z80_|pla_decode_|Equal10~0_combout ) # (\z80_|execute_|ctl_flags_hf_cpl~11_combout ))) # (!\z80_|execute_|ctl_flags_hf_cpl~10_combout ) + + .dataa(\z80_|execute_|ctl_flags_hf_cpl~10_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~25_combout ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|execute_|ctl_flags_hf_cpl~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_cpl~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_cpl~12 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_flags_hf_cpl~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~13 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_cpl~13_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~q & (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|execute_|ctl_flags_hf_cpl~12_combout & \z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|execute_|ctl_flags_hf_cpl~12_combout ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_cpl~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_cpl~13 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_flags_hf_cpl~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y17_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~8_combout = (\z80_|execute_|ctl_alu_core_S~6_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~4_combout & (\z80_|execute_|ctl_alu_core_S~11_combout & !\z80_|execute_|ctl_alu_core_R~1_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_S~6_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), + .datac(\z80_|execute_|ctl_alu_core_S~11_combout ), + .datad(\z80_|execute_|ctl_alu_core_R~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~8 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_alu_core_S~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y20_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~9_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout & (\z80_|execute_|ctl_alu_core_S~8_combout & !\z80_|pla_decode_|Equal72~2_combout )) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_core_S~8_combout ), + .datad(\z80_|pla_decode_|Equal72~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~9 .lut_mask = 16'h00A0; +defparam \z80_|execute_|ctl_alu_core_S~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~10_combout = (((!\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ) # (!\z80_|execute_|ctl_alu_core_S~12_combout )) # (!\z80_|execute_|ctl_alu_core_R~4_combout )) # (!\z80_|execute_|ctl_alu_core_S~5_combout ) + + .dataa(\z80_|execute_|ctl_alu_core_S~5_combout ), + .datab(\z80_|execute_|ctl_alu_core_R~4_combout ), + .datac(\z80_|execute_|ctl_alu_core_S~12_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~10 .lut_mask = 16'h7FFF; +defparam \z80_|execute_|ctl_alu_core_S~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y20_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~combout = ((\z80_|execute_|ctl_alu_core_S~10_combout ) # ((\z80_|pla_decode_|Equal9~0_combout & \z80_|pla_decode_|Equal62~2_combout ))) # (!\z80_|execute_|ctl_alu_core_S~9_combout ) + + .dataa(\z80_|pla_decode_|Equal9~0_combout ), + .datab(\z80_|execute_|ctl_alu_core_S~9_combout ), + .datac(\z80_|execute_|ctl_alu_core_S~10_combout ), + .datad(\z80_|pla_decode_|Equal62~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S .lut_mask = 16'hFBF3; +defparam \z80_|execute_|ctl_alu_core_S .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N12 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[3] ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_high|Q [3] = (\z80_|alu_|db_high[3]~7_combout & (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & \z80_|execute_|ctl_alu_op1_sel_bus~15_combout )) + + .dataa(\z80_|alu_|db_high[3]~7_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [3]), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[3] .lut_mask = 16'h0A00; +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[3] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N8 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|ena~0 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ) # (\z80_|execute_|ctl_alu_op1_sel_zero~combout ) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_high|ena~0 .lut_mask = 16'hFAFA; +defparam \z80_|alu_|b2v_op1_latch_mux_high|ena~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y17_N13 +dffeas \z80_|alu_|op1_high[3] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [3]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_high [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_high[3] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_high[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N14 +cycloneive_lcell_comb \z80_|alu_|alu_op1[3]~2 ( +// Equation(s): +// \z80_|alu_|alu_op1[3]~2_combout = (\z80_|execute_|ctl_alu_op_low~41_combout & (((\z80_|alu_|op1_low [3])))) # (!\z80_|execute_|ctl_alu_op_low~41_combout & ((\z80_|execute_|ctl_alu_op_low~29_combout & (\z80_|alu_|op1_high [3])) # +// (!\z80_|execute_|ctl_alu_op_low~29_combout & ((\z80_|alu_|op1_low [3]))))) + + .dataa(\z80_|execute_|ctl_alu_op_low~41_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~29_combout ), + .datac(\z80_|alu_|op1_high [3]), + .datad(\z80_|alu_|op1_low [3]), + .cin(gnd), + .combout(\z80_|alu_|alu_op1[3]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op1[3]~2 .lut_mask = 16'hFB40; +defparam \z80_|alu_|alu_op1[3]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N12 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout = (\z80_|execute_|ctl_alu_core_S~combout ) # ((\z80_|alu_|alu_op1[3]~2_combout & \z80_|alu_|alu_op2[3]~2_combout )) + + .dataa(\z80_|execute_|ctl_alu_core_S~combout ), + .datab(gnd), + .datac(\z80_|alu_|alu_op1[3]~2_combout ), + .datad(\z80_|alu_|alu_op2[3]~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hFAAA; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we_lo~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we_lo~2_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|ir_|opcode [5])) + + .dataa(gnd), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we_lo~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we_lo~2 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_reg_sys_we_lo~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we_lo~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we_lo~3_combout = (\z80_|pla_decode_|Equal9~1_combout ) # ((\z80_|execute_|ctl_reg_sys_we_lo~2_combout ) # ((\z80_|pla_decode_|Equal8~0_combout & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal8~0_combout ), + .datab(\z80_|pla_decode_|Equal9~1_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_we_lo~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we_lo~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we_lo~3 .lut_mask = 16'hFFEC; +defparam \z80_|execute_|ctl_reg_sys_we_lo~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~14 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~14_combout = (((!\z80_|pla_decode_|Equal35~0_combout & !\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|alu_control_|flags_cond_true~q )) # (!\z80_|execute_|ixy_d~6_combout ) + + .dataa(\z80_|pla_decode_|Equal35~0_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|pla_decode_|Equal34~0_combout ), + .datad(\z80_|alu_control_|flags_cond_true~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~14 .lut_mask = 16'h37FF; +defparam \z80_|execute_|ctl_reg_sel_wz~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N8 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_hi~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_hi~0_combout = ((\z80_|execute_|ixy_d~6_combout & ((\z80_|execute_|ctl_reg_sys_we_lo~3_combout ) # (\z80_|pla_decode_|Equal19~0_combout )))) # (!\z80_|execute_|ctl_reg_sel_wz~14_combout ) + + .dataa(\z80_|execute_|ctl_reg_sys_we_lo~3_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~14_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_hi~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_hi~0 .lut_mask = 16'hC8FF; +defparam \z80_|reg_control_|reg_sys_we_hi~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N20 +cycloneive_lcell_comb \z80_|pla_decode_|Equal33~3 ( +// Equation(s): +// \z80_|pla_decode_|Equal33~3_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal33~1_combout & (\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|pla_decode_|Equal33~1_combout ), + .datac(\z80_|decode_state_|use_ixiy~combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal33~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal33~3 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal33~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we~0_combout = (\z80_|execute_|ixy_d~5_combout & ((\z80_|pla_decode_|Equal33~3_combout ) # ((\z80_|pla_decode_|Equal6~1_combout ) # (!\z80_|execute_|pc_inc_hold~26_combout )))) + + .dataa(\z80_|pla_decode_|Equal33~3_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|pla_decode_|Equal6~1_combout ), + .datad(\z80_|execute_|pc_inc_hold~26_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we~0 .lut_mask = 16'hC8CC; +defparam \z80_|execute_|ctl_reg_sys_we~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we~2_combout = (!\z80_|execute_|ctl_reg_sys_we~1_combout & (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|execute_|ctl_mWrite~17_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout ))) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|execute_|ctl_reg_sys_we~1_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datad(\z80_|execute_|ctl_mWrite~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we~2 .lut_mask = 16'h0313; +defparam \z80_|execute_|ctl_reg_sys_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we~3_combout = (\z80_|execute_|ctl_reg_sys_we~0_combout ) # (((\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ) # (!\z80_|execute_|ctl_reg_sys_we~2_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~32_combout )) + + .dataa(\z80_|execute_|ctl_reg_sys_we~0_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~32_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), + .datad(\z80_|execute_|ctl_reg_sys_we~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we~3 .lut_mask = 16'hFBFF; +defparam \z80_|execute_|ctl_reg_sys_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~4_combout = (\z80_|reg_control_|reg_sel_pc~2_combout & (\z80_|execute_|ctl_alu_oe~2_combout & (!\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout & \z80_|execute_|ctl_alu_sel_op2_neg~2_combout ))) + + .dataa(\z80_|reg_control_|reg_sel_pc~2_combout ), + .datab(\z80_|execute_|ctl_alu_oe~2_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~4 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_in_hi~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N4 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_hi ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_hi~combout = (\z80_|reg_control_|reg_sys_we_hi~0_combout ) # ((\z80_|execute_|ctl_reg_sys_we~3_combout ) # (!\z80_|execute_|ctl_reg_in_hi~4_combout )) + + .dataa(\z80_|reg_control_|reg_sys_we_hi~0_combout ), + .datab(\z80_|execute_|ctl_reg_sys_we~3_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_in_hi~4_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_hi~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_hi .lut_mask = 16'hEEFF; +defparam \z80_|reg_control_|reg_sys_we_hi .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~18 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~18_combout = (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # ((\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~18 .lut_mask = 16'hF0B0; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo~17 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo~17_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|execute_|ctl_mRead~12_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|execute_|ctl_mRead~12_combout ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo~17 .lut_mask = 16'h80C0; +defparam \z80_|execute_|ctl_reg_sys_hilo~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~11 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~11_combout = (!\z80_|execute_|ctl_reg_sys_hilo~17_combout & (((!\z80_|execute_|ctl_mRead~34_combout & !\z80_|pla_decode_|Equal10~0_combout )) # (!\z80_|execute_|ctl_mWrite~9_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~9_combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~11 .lut_mask = 16'h0057; +defparam \z80_|execute_|ctl_reg_sel_pc~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~12 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~12_combout = (\z80_|execute_|ctl_reg_sel_pc~11_combout & (((\z80_|execute_|ctl_flags_bus~1_combout & \z80_|execute_|ctl_al_we~13_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ), + .datab(\z80_|execute_|ctl_flags_bus~1_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~11_combout ), + .datad(\z80_|execute_|ctl_al_we~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~12 .lut_mask = 16'hD050; +defparam \z80_|execute_|ctl_reg_sel_pc~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~13 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~13_combout = (\z80_|execute_|setM1~54_combout & (\z80_|execute_|ctl_reg_sel_pc~12_combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|pla_decode_|Equal6~1_combout )))) + + .dataa(\z80_|execute_|setM1~54_combout ), + .datab(\z80_|pla_decode_|Equal6~1_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~12_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~13 .lut_mask = 16'h20A0; +defparam \z80_|execute_|ctl_reg_sel_pc~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout = (\z80_|execute_|ixy_d~6_combout & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|execute_|comb~0_combout & \z80_|ir_|opcode [0]))) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|pla_decode_|Equal52~0_combout ), + .datac(\z80_|execute_|comb~0_combout ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~6_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & (((!\z80_|execute_|ctl_mRead~8_combout & !\z80_|execute_|ctl_mRead~6_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~8_combout ), + .datab(\z80_|execute_|ctl_mRead~6_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~6 .lut_mask = 16'h010F; +defparam \z80_|execute_|ctl_reg_sel_wz~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~7_combout = (\z80_|execute_|ctl_reg_sel_wz~6_combout & (((!\z80_|pla_decode_|Equal34~0_combout & !\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|execute_|ctl_reg_in_hi~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal34~0_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~7 .lut_mask = 16'h3700; +defparam \z80_|execute_|ctl_reg_sel_wz~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~9_combout = (\z80_|execute_|ctl_bus_db_oe~0_combout & (\z80_|execute_|ctl_reg_in_hi~3_combout & (\z80_|execute_|ctl_reg_sel_wz~7_combout & \z80_|execute_|ctl_reg_in_hi~4_combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_oe~0_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~3_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~7_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~9 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sel_wz~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~25 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~25_combout = (!\z80_|pla_decode_|Equal35~0_combout & (!\z80_|pla_decode_|Equal24~1_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~11_combout & !\z80_|pla_decode_|Equal19~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal35~0_combout ), + .datab(\z80_|pla_decode_|Equal24~1_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~11_combout ), + .datad(\z80_|pla_decode_|Equal19~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~25 .lut_mask = 16'h0010; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~8_combout = (!\z80_|execute_|ctl_mRead~15_combout & ((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~15_combout ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal12~1_combout ), + .datad(\z80_|pla_decode_|Equal25~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~8 .lut_mask = 16'h5055; +defparam \z80_|execute_|ctl_reg_sel_wz~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~5_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout & (!\z80_|pla_decode_|Equal34~0_combout & (\z80_|execute_|ctl_reg_sel_wz~8_combout & !\z80_|execute_|ctl_mRead~7_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ), + .datab(\z80_|pla_decode_|Equal34~0_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~8_combout ), + .datad(\z80_|execute_|ctl_mRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~5 .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_al_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~4_combout = (!\z80_|execute_|ctl_mRead~2_combout & (!\z80_|execute_|ixy_d~10_combout & (!\z80_|execute_|ixy_d~16_combout & !\z80_|execute_|ctl_mRead~3_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~2_combout ), + .datab(\z80_|execute_|ixy_d~10_combout ), + .datac(\z80_|execute_|ixy_d~16_combout ), + .datad(\z80_|execute_|ctl_mRead~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~4 .lut_mask = 16'h0001; +defparam \z80_|execute_|ctl_al_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~41 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~41_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ctl_al_we~4_combout )))) + + .dataa(\z80_|pla_decode_|Equal34~0_combout ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|execute_|ctl_al_we~4_combout ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~41 .lut_mask = 16'h008C; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~10 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~10_combout = (!\z80_|execute_|ctl_ir_we~8_combout & (!\z80_|execute_|ctl_mRead~13_combout & !\z80_|execute_|ctl_ir_we~14_combout )) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_mRead~13_combout ), + .datad(\z80_|execute_|ctl_ir_we~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~10 .lut_mask = 16'h0005; +defparam \z80_|execute_|ctl_reg_sel_wz~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo~21 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo~21_combout = (\z80_|ir_|opcode [5]) # ((!\z80_|pla_decode_|Equal6~0_combout ) # (!\z80_|pla_decode_|Equal55~0_combout )) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo~21 .lut_mask = 16'hBBFF; +defparam \z80_|execute_|ctl_reg_sys_hilo~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~3 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~3_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~3 .lut_mask = 16'h7755; +defparam \z80_|execute_|ctl_inc_dec~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~22 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~22_combout = (\z80_|execute_|ctl_reg_sys_hilo~21_combout & (((\z80_|execute_|ctl_inc_dec~3_combout ) # (!\z80_|pla_decode_|Equal33~3_combout )))) # (!\z80_|execute_|ctl_reg_sys_hilo~21_combout & +// (!\z80_|execute_|ctl_alu_op_low~22_combout & ((\z80_|execute_|ctl_inc_dec~3_combout ) # (!\z80_|pla_decode_|Equal33~3_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo~21_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datac(\z80_|pla_decode_|Equal33~3_combout ), + .datad(\z80_|execute_|ctl_inc_dec~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~22 .lut_mask = 16'hBB0B; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~23 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~23_combout = (!\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout & ((\z80_|execute_|ctl_reg_sel_wz~10_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout +// )))) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~10_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~23 .lut_mask = 16'h2300; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~24 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~24_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout & (((!\z80_|pla_decode_|Equal6~1_combout & \z80_|execute_|pc_inc_hold~26_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) + + .dataa(\z80_|pla_decode_|Equal6~1_combout ), + .datab(\z80_|execute_|pc_inc_hold~26_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~24 .lut_mask = 16'h4F00; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~19 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~19_combout = (!\z80_|execute_|ctl_reg_sel_wz~8_combout & ((\z80_|execute_|ctl_state_alu~3_combout ) # ((\z80_|execute_|ctl_alu_oe~0_combout ) # (\z80_|execute_|ctl_ir_we~4_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~3_combout ), + .datab(\z80_|execute_|ctl_alu_oe~0_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~19 .lut_mask = 16'h00FE; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N28 +cycloneive_lcell_comb \z80_|execute_|fMRead~2 ( +// Equation(s): +// \z80_|execute_|fMRead~2_combout = ((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~2 .lut_mask = 16'h0AFF; +defparam \z80_|execute_|fMRead~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~20 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~20_combout = (!\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout & ((\z80_|execute_|fMRead~2_combout ) # ((\z80_|execute_|pc_inc_hold~6_combout & !\z80_|execute_|ctl_mRead~7_combout )))) + + .dataa(\z80_|execute_|pc_inc_hold~6_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ), + .datac(\z80_|execute_|ctl_mRead~7_combout ), + .datad(\z80_|execute_|fMRead~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~20 .lut_mask = 16'h3302; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~26 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~26_combout = (!\z80_|pla_decode_|Equal52~1_combout & (!\z80_|pla_decode_|Equal6~1_combout & \z80_|execute_|ctl_bus_db_oe~1_combout )) + + .dataa(\z80_|pla_decode_|Equal52~1_combout ), + .datab(\z80_|pla_decode_|Equal6~1_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~26 .lut_mask = 16'h1100; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~27 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~27_combout = (!\z80_|execute_|fMRead~2_combout & ((!\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ), + .datab(\z80_|execute_|fMRead~2_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~27 .lut_mask = 16'h1133; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~28 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~28_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~20_combout & (!\z80_|execute_|ctl_reg_sys_hilo[1]~27_combout & \z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~20_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~28 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~29 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~29_combout = (!\z80_|execute_|ctl_reg_sys_hilo[1]~41_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout & ((\z80_|execute_|ctl_al_we~5_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) + + .dataa(\z80_|execute_|ctl_al_we~5_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~41_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~29 .lut_mask = 16'h2300; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~30 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~30_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~16_combout & (\z80_|execute_|ctl_reg_sel_pc~13_combout & (\z80_|execute_|ctl_reg_sel_wz~9_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~29_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~16_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~13_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~9_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~29_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~30 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~13 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~13_combout = (\z80_|pla_decode_|Equal9~1_combout & (!\z80_|execute_|ixy_d~6_combout & ((!\z80_|execute_|ctl_reg_in_hi~2_combout )))) # (!\z80_|pla_decode_|Equal9~1_combout & (((!\z80_|pla_decode_|Equal19~0_combout )) # +// (!\z80_|execute_|ixy_d~6_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~13 .lut_mask = 16'h1537; +defparam \z80_|execute_|ctl_reg_sel_wz~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~32 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~32_combout = ((\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ) # ((\z80_|pla_decode_|Equal35~0_combout & \z80_|execute_|ixy_d~6_combout ))) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ) + + .dataa(\z80_|pla_decode_|Equal35~0_combout ), + .datab(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~32 .lut_mask = 16'hFFB3; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y19_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~33 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~33_combout = (!\z80_|ir_|opcode [3] & ((\z80_|execute_|ctl_alu_op_low~28_combout ) # ((\z80_|pla_decode_|Equal48~0_combout & \z80_|execute_|ctl_eval_cond~0_combout )))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|execute_|ctl_alu_op_low~28_combout ), + .datac(\z80_|pla_decode_|Equal48~0_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~33 .lut_mask = 16'h5444; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y19_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~34 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~34_combout = (((\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ) # (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout )) # (!\z80_|execute_|ctl_reg_out_hi~4_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~37_combout ) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~37_combout ), + .datab(\z80_|execute_|ctl_reg_out_hi~4_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~34 .lut_mask = 16'hFFF7; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~35 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~35_combout = (((\z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~13_combout )) # (!\z80_|execute_|ctl_reg_in_hi~5_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~5_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~13_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~35 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N22 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_73 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_73~combout = (\z80_|reg_control_|reg_sel_pc~combout & (\z80_|reg_control_|reg_sys_we_hi~combout & \z80_|execute_|ctl_reg_sys_hilo[1]~35_combout )) + + .dataa(\z80_|reg_control_|reg_sel_pc~combout ), + .datab(gnd), + .datac(\z80_|reg_control_|reg_sys_we_hi~combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_73 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_73 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y14_N5 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[3]~12_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_ir~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_ir~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_ir~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_ir~0 .lut_mask = 16'h0F0C; +defparam \z80_|execute_|ctl_reg_sel_ir~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_ir~1 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_ir~1_combout = (\z80_|execute_|ctl_reg_sel_ir~0_combout ) # (((\z80_|execute_|ctl_eval_cond~0_combout & !\z80_|execute_|ctl_flags_bus~0_combout )) # (!\z80_|execute_|ctl_reg_in_lo~9_combout )) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|ctl_flags_bus~0_combout ), + .datac(\z80_|execute_|ctl_reg_sel_ir~0_combout ), + .datad(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_ir~1 .lut_mask = 16'hF2FF; +defparam \z80_|execute_|ctl_reg_sel_ir~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N16 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_60 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_60~combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout & (!\z80_|reg_control_|reg_sys_we_hi~combout & \z80_|execute_|ctl_reg_sel_ir~1_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), + .datac(\z80_|reg_control_|reg_sys_we_hi~combout ), + .datad(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_60 .lut_mask = 16'h0C00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_60 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N20 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_61 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_61~combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout & (\z80_|reg_control_|reg_sys_we_hi~combout & \z80_|execute_|ctl_reg_sel_ir~1_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), + .datac(\z80_|reg_control_|reg_sys_we_hi~combout ), + .datad(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_61 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_61 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y14_N15 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[3]~12_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we_lo~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we_lo~4_combout = (\z80_|execute_|ctl_reg_sys_we_lo~3_combout & (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_M2_ff~q )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_sys_we_lo~3_combout ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we_lo~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we_lo~4 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_reg_sys_we_lo~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N22 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~combout = ((\z80_|execute_|ctl_reg_sys_we_lo~4_combout ) # ((\z80_|execute_|ctl_reg_sys_we~3_combout ) # (!\z80_|reg_control_|reg_sys_we_lo~4_combout ))) # (!\z80_|reg_control_|reg_sys_we_lo~7_combout ) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~7_combout ), + .datab(\z80_|execute_|ctl_reg_sys_we_lo~4_combout ), + .datac(\z80_|reg_control_|reg_sys_we_lo~4_combout ), + .datad(\z80_|execute_|ctl_reg_sys_we~3_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo .lut_mask = 16'hFFDF; +defparam \z80_|reg_control_|reg_sys_we_lo .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N2 +cycloneive_lcell_comb \z80_|reg_control_|reg_sw_4d_hi~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sw_4d_hi~0_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_control_|reg_sys_we_lo~combout ) # (!\z80_|execute_|ctl_reg_sel_ir~1_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ))) + + .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), + .datac(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datad(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sw_4d_hi~0 .lut_mask = 16'hA2AA; +defparam \z80_|reg_control_|reg_sw_4d_hi~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N14 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~10 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[3]~10_combout = (\z80_|reg_file_|gdfx_temp1[3]~48_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) # (!\z80_|reg_file_|gdfx_temp1[3]~48_combout & +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [3]), + .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[3]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[3]~10 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|db_hi_as[3]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N26 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~11 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[3]~11_combout = (\z80_|reg_file_|db_hi_as[3]~10_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [3]), + .datad(\z80_|reg_file_|db_hi_as[3]~10_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[3]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[3]~11 .lut_mask = 16'hF300; +defparam \z80_|reg_file_|db_hi_as[3]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N14 +cycloneive_lcell_comb \z80_|address_latch_|abusz[11] ( +// Equation(s): +// \z80_|address_latch_|abusz [11] = (\z80_|reg_file_|db_hi_as[3]~12_combout & !\z80_|resets_|clrpc~0_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[3]~12_combout ), + .datab(gnd), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [11]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[11] .lut_mask = 16'h0A0A; +defparam \z80_|address_latch_|abusz[11] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~1 ( +// Equation(s): +// \z80_|execute_|ctl_apin_mux~1_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (\z80_|sequencer_|DFFE_M2_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_apin_mux~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_apin_mux~1 .lut_mask = 16'h3232; +defparam \z80_|execute_|ctl_apin_mux~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~37 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~37_combout = (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|pla_decode_|Equal47~0_combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|pla_decode_|Equal34~0_combout )))) # (!\z80_|execute_|ctl_state_alu~2_combout +// & (((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|pla_decode_|Equal34~0_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|pla_decode_|Equal47~0_combout ), + .datac(\z80_|pla_decode_|Equal34~0_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~37 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_inc_cy~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~2 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~2_combout = (\z80_|execute_|ctl_inc_cy~37_combout & (((!\z80_|pla_decode_|Equal9~1_combout & !\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|execute_|ctl_inc_cy~37_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~2 .lut_mask = 16'h3700; +defparam \z80_|execute_|ctl_inc_dec~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~40 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~40_combout = (\z80_|pla_decode_|Equal34~0_combout & (!\z80_|execute_|ixy_d~9_combout & ((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) # (!\z80_|pla_decode_|Equal34~0_combout & +// (((!\z80_|execute_|ctl_mRead~9_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal34~0_combout ), + .datab(\z80_|pla_decode_|Equal47~0_combout ), + .datac(\z80_|execute_|ctl_mRead~9_combout ), + .datad(\z80_|execute_|ixy_d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~40 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_inc_cy~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~4 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~4_combout = (\z80_|execute_|ctl_inc_cy~40_combout & (((!\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|sequencer_|DFFE_M3_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|execute_|ctl_inc_cy~40_combout ), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~4 .lut_mask = 16'h4CCC; +defparam \z80_|execute_|ctl_inc_dec~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~5 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~5_combout = (\z80_|execute_|ctl_inc_dec~2_combout & (\z80_|execute_|ctl_inc_dec~4_combout & ((!\z80_|execute_|ixy_d~9_combout ) # (!\z80_|pla_decode_|Equal9~1_combout )))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ctl_inc_dec~2_combout ), + .datac(\z80_|execute_|ctl_inc_dec~4_combout ), + .datad(\z80_|execute_|ixy_d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~5 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_inc_dec~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~4_combout = (\z80_|execute_|ctl_inc_dec~5_combout & (((!\z80_|execute_|ctl_state_alu~2_combout & !\z80_|execute_|ctl_mRead~9_combout )) # (!\z80_|execute_|ctl_mWrite~6_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datac(\z80_|execute_|ctl_inc_dec~5_combout ), + .datad(\z80_|execute_|ctl_mRead~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~4 .lut_mask = 16'h3070; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal2~1_combout & (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [1]))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|pla_decode_|Equal2~1_combout ), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 .lut_mask = 16'h0008; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|setM1~42 ( +// Equation(s): +// \z80_|execute_|setM1~42_combout = (!\z80_|pla_decode_|Equal4~0_combout & ((!\z80_|pla_decode_|Equal8~0_combout ) # (!\z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal4~0_combout ), + .datad(\z80_|pla_decode_|Equal8~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~42 .lut_mask = 16'h050F; +defparam \z80_|execute_|setM1~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~12 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~12_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout & (!\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout & ((\z80_|execute_|setM1~42_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ), + .datab(\z80_|execute_|setM1~42_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~12 .lut_mask = 16'h0405; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~4 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~4_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|execute_|ctl_mRead~2_combout & ((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|ctl_mRead~3_combout )))) # (!\z80_|execute_|ixy_d~7_combout & +// (((!\z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|execute_|ctl_mRead~3_combout ))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ctl_mRead~3_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_mRead~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~4 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_sw_1d~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~3 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~3_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~4_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~12_combout & \z80_|execute_|ctl_sw_1d~4_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~12_combout ), + .datad(\z80_|execute_|ctl_sw_1d~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~3 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_sw_4d~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N8 +cycloneive_lcell_comb \z80_|execute_|fMRead~9 ( +// Equation(s): +// \z80_|execute_|fMRead~9_combout = (\z80_|execute_|ctl_mRead~14_combout & (((!\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ctl_state_alu~3_combout )))) # (!\z80_|execute_|ctl_mRead~14_combout & (((!\z80_|execute_|ixy_d~7_combout & +// !\z80_|execute_|ctl_state_alu~3_combout )) # (!\z80_|pla_decode_|Equal37~0_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~14_combout ), + .datab(\z80_|pla_decode_|Equal37~0_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ctl_state_alu~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~9 .lut_mask = 16'h111F; +defparam \z80_|execute_|fMRead~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N2 +cycloneive_lcell_comb \z80_|execute_|fMRead~10 ( +// Equation(s): +// \z80_|execute_|fMRead~10_combout = (\z80_|execute_|fMRead~9_combout & (((!\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ctl_state_alu~3_combout )) # (!\z80_|pla_decode_|Equal38~2_combout ))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|fMRead~9_combout ), + .datac(\z80_|pla_decode_|Equal38~2_combout ), + .datad(\z80_|execute_|ctl_state_alu~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~10 .lut_mask = 16'h0C4C; +defparam \z80_|execute_|fMRead~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|fMRead~8 ( +// Equation(s): +// \z80_|execute_|fMRead~8_combout = (\z80_|pla_decode_|Equal9~1_combout & (!\z80_|execute_|ctl_state_alu~3_combout & (!\z80_|execute_|ixy_d~7_combout ))) # (!\z80_|pla_decode_|Equal9~1_combout & (((!\z80_|execute_|ctl_state_alu~3_combout & +// !\z80_|execute_|ixy_d~7_combout )) # (!\z80_|pla_decode_|Equal29~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ctl_state_alu~3_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|pla_decode_|Equal29~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~8 .lut_mask = 16'h0357; +defparam \z80_|execute_|fMRead~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~2 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~2_combout = (\z80_|execute_|fMRead~10_combout & (\z80_|execute_|fMRead~8_combout & \z80_|execute_|ctl_reg_in_lo~9_combout )) + + .dataa(\z80_|execute_|fMRead~10_combout ), + .datab(\z80_|execute_|fMRead~8_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~2 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_sw_4d~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~11 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~11_combout = (\z80_|execute_|ctl_reg_sel_wz~8_combout & (((\z80_|execute_|ctl_reg_sel_wz~10_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|execute_|ctl_reg_sel_wz~8_combout & +// (!\z80_|execute_|ctl_alu_oe~0_combout & (!\z80_|execute_|ctl_ir_we~4_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~8_combout ), + .datab(\z80_|execute_|ctl_alu_oe~0_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~11 .lut_mask = 16'hAB0B; +defparam \z80_|execute_|ctl_reg_sel_wz~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~12 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~12_combout = (\z80_|execute_|ctl_reg_sel_wz~9_combout & \z80_|execute_|ctl_reg_sel_wz~11_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_sel_wz~9_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~12 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_reg_sel_wz~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~4 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~4_combout = (\z80_|pla_decode_|Equal9~1_combout & (!\z80_|execute_|ctl_reg_in_hi~2_combout & ((\z80_|execute_|ctl_flags_bus~1_combout ) # (!\z80_|execute_|ixy_d~6_combout )))) # (!\z80_|pla_decode_|Equal9~1_combout & +// (((\z80_|execute_|ctl_flags_bus~1_combout )) # (!\z80_|execute_|ixy_d~6_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|execute_|ctl_flags_bus~1_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~4 .lut_mask = 16'h51F3; +defparam \z80_|execute_|ctl_sw_4d~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~5 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~5_combout = (\z80_|execute_|ctl_sw_4d~3_combout & (\z80_|execute_|ctl_sw_4d~2_combout & (\z80_|execute_|ctl_reg_sel_wz~12_combout & \z80_|execute_|ctl_sw_4d~4_combout ))) + + .dataa(\z80_|execute_|ctl_sw_4d~3_combout ), + .datab(\z80_|execute_|ctl_sw_4d~2_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~12_combout ), + .datad(\z80_|execute_|ctl_sw_4d~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~5 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_sw_4d~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~14 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~14_combout = (!\z80_|execute_|ctl_mRead~5_combout & ((\z80_|ir_|opcode [2]) # ((!\z80_|ir_|opcode [1]) # (!\z80_|execute_|ctl_mWrite~4_combout )))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|execute_|ctl_mWrite~4_combout ), + .datac(\z80_|execute_|ctl_mRead~5_combout ), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~14 .lut_mask = 16'h0B0F; +defparam \z80_|execute_|ctl_al_we~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~10 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~10_combout = ((\z80_|pla_decode_|Equal33~3_combout ) # (!\z80_|execute_|ctl_al_we~5_combout )) # (!\z80_|execute_|ctl_al_we~14_combout ) + + .dataa(\z80_|execute_|ctl_al_we~14_combout ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal33~3_combout ), + .datad(\z80_|execute_|ctl_al_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~10 .lut_mask = 16'hF5FF; +defparam \z80_|execute_|ctl_al_we~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~6_combout = (\z80_|execute_|ctl_ir_we~4_combout & (((!\z80_|execute_|ctl_al_we~13_combout )) # (!\z80_|execute_|ctl_flags_bus~1_combout ))) # (!\z80_|execute_|ctl_ir_we~4_combout & (\z80_|execute_|ctl_state_alu~4_combout & +// ((!\z80_|execute_|ctl_al_we~13_combout ) # (!\z80_|execute_|ctl_flags_bus~1_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|execute_|ctl_flags_bus~1_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|ctl_al_we~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~6 .lut_mask = 16'h32FA; +defparam \z80_|execute_|ctl_al_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~7_combout = ((\z80_|execute_|ctl_al_we~6_combout ) # ((\z80_|pla_decode_|Equal35~0_combout & \z80_|execute_|ixy_d~6_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|execute_|ctl_al_we~6_combout ), + .datac(\z80_|pla_decode_|Equal35~0_combout ), + .datad(\z80_|execute_|ixy_d~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~7 .lut_mask = 16'hFDDD; +defparam \z80_|execute_|ctl_al_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~8_combout = (((!\z80_|execute_|ctl_al_we~4_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~31_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout )) # (!\z80_|execute_|ctl_alu_oe~3_combout ) + + .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~31_combout ), + .datad(\z80_|execute_|ctl_al_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~8 .lut_mask = 16'h7FFF; +defparam \z80_|execute_|ctl_al_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~9 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~9_combout = (\z80_|execute_|ctl_al_we~7_combout ) # ((\z80_|execute_|ctl_state_alu~3_combout & ((\z80_|execute_|ctl_al_we~8_combout ) # (!\z80_|execute_|setM1~47_combout )))) + + .dataa(\z80_|execute_|ctl_al_we~7_combout ), + .datab(\z80_|execute_|ctl_state_alu~3_combout ), + .datac(\z80_|execute_|setM1~47_combout ), + .datad(\z80_|execute_|ctl_al_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~9 .lut_mask = 16'hEEAE; +defparam \z80_|execute_|ctl_al_we~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~11 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~11_combout = ((\z80_|execute_|ctl_al_we~9_combout ) # ((\z80_|execute_|ctl_apin_mux~1_combout & \z80_|execute_|ctl_al_we~10_combout ))) # (!\z80_|execute_|ctl_sw_4d~5_combout ) + + .dataa(\z80_|execute_|ctl_apin_mux~1_combout ), + .datab(\z80_|execute_|ctl_sw_4d~5_combout ), + .datac(\z80_|execute_|ctl_al_we~10_combout ), + .datad(\z80_|execute_|ctl_al_we~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~11 .lut_mask = 16'hFFB3; +defparam \z80_|execute_|ctl_al_we~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~12 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~12_combout = ((\z80_|execute_|ctl_al_we~11_combout ) # ((\z80_|pla_decode_|Equal6~1_combout & \z80_|execute_|ixy_d~7_combout ))) # (!\z80_|execute_|setM1~54_combout ) + + .dataa(\z80_|execute_|setM1~54_combout ), + .datab(\z80_|pla_decode_|Equal6~1_combout ), + .datac(\z80_|execute_|ctl_al_we~11_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~12 .lut_mask = 16'hFDF5; +defparam \z80_|execute_|ctl_al_we~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y13_N15 +dffeas \z80_|address_latch_|Q[11] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [11]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [11]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[11] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N24 +cycloneive_lcell_comb \z80_|execute_|fIOWrite~0 ( +// Equation(s): +// \z80_|execute_|fIOWrite~0_combout = ((\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q ))) # (!\z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|fIOWrite~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIOWrite~0 .lut_mask = 16'h0F2F; +defparam \z80_|execute_|fIOWrite~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~8 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~8_combout = (\z80_|execute_|ctl_mWrite~6_combout & ((\z80_|execute_|ctl_mRead~9_combout ) # ((!\z80_|execute_|ctl_inc_dec~3_combout ) # (!\z80_|execute_|fIOWrite~0_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~9_combout ), + .datab(\z80_|execute_|fIOWrite~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~6_combout ), + .datad(\z80_|execute_|ctl_inc_dec~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~8 .lut_mask = 16'hB0F0; +defparam \z80_|execute_|ctl_inc_dec~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y18_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~2_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~5_combout & (\z80_|execute_|ctl_bus_inc_oe~45_combout & ((!\z80_|execute_|ctl_mWrite~17_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~45_combout ), + .datad(\z80_|execute_|ctl_mWrite~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~2 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_reg_gp_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~9 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~9_combout = ((\z80_|execute_|ctl_inc_dec~8_combout ) # ((!\z80_|execute_|ctl_reg_gp_we~2_combout & \z80_|ir_|opcode [3]))) # (!\z80_|execute_|ctl_inc_dec~12_combout ) + + .dataa(\z80_|execute_|ctl_inc_dec~12_combout ), + .datab(\z80_|execute_|ctl_inc_dec~8_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~2_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~9 .lut_mask = 16'hDFDD; +defparam \z80_|execute_|ctl_inc_dec~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N22 +cycloneive_lcell_comb \z80_|address_latch_|abusz[1] ( +// Equation(s): +// \z80_|address_latch_|abusz [1] = (\z80_|reg_file_|db_lo_as[1]~6_combout & !\z80_|resets_|clrpc~0_combout ) + + .dataa(\z80_|reg_file_|db_lo_as[1]~6_combout ), + .datab(gnd), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [1]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[1] .lut_mask = 16'h0A0A; +defparam \z80_|address_latch_|abusz[1] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y11_N23 +dffeas \z80_|address_latch_|Q[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [1]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[1] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~0 ( +// Equation(s): +// \z80_|execute_|ctl_apin_mux~0_combout = (\z80_|execute_|ctl_inc_cy~32_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~37_combout & ((!\z80_|pla_decode_|Equal19~0_combout ) # (!\z80_|execute_|ctl_alu_oe~0_combout )))) + + .dataa(\z80_|execute_|ctl_inc_cy~32_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~37_combout ), + .datac(\z80_|execute_|ctl_alu_oe~0_combout ), + .datad(\z80_|pla_decode_|Equal19~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_apin_mux~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_apin_mux~0 .lut_mask = 16'h0888; +defparam \z80_|execute_|ctl_apin_mux~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~6 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~6_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout & (\z80_|execute_|ctl_apin_mux~0_combout & ((!\z80_|pla_decode_|Equal9~1_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|pla_decode_|Equal9~1_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), + .datad(\z80_|execute_|ctl_apin_mux~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~6 .lut_mask = 16'h0700; +defparam \z80_|execute_|ctl_inc_dec~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~7 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~7_combout = (!\z80_|execute_|ctl_bus_inc_oe~42_combout ) # (!\z80_|execute_|ctl_inc_dec~5_combout ) + + .dataa(\z80_|execute_|ctl_inc_dec~5_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_bus_inc_oe~42_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~7 .lut_mask = 16'h5F5F; +defparam \z80_|execute_|ctl_inc_dec~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N6 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout = \z80_|address_latch_|Q [1] $ (((\z80_|execute_|ctl_inc_dec~9_combout ) # ((\z80_|execute_|ctl_inc_dec~7_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout )))) + + .dataa(\z80_|execute_|ctl_inc_dec~9_combout ), + .datab(\z80_|address_latch_|Q [1]), + .datac(\z80_|execute_|ctl_inc_dec~6_combout ), + .datad(\z80_|execute_|ctl_inc_dec~7_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0 .lut_mask = 16'h3363; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~21 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~21_combout = (\z80_|reg_control_|reg_sys_we_lo~6_combout & (\z80_|execute_|ctl_mRead~20_combout & ((!\z80_|execute_|ixy_d~15_combout ) # (!\z80_|sequencer_|DFFE_T3_ff~q )))) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~6_combout ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|execute_|ixy_d~15_combout ), + .datad(\z80_|execute_|ctl_mRead~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~21 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_reg_sel_wz~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~40 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[0]~40_combout = (\z80_|execute_|ctl_reg_sel_wz~20_combout ) # ((\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|M5~q & \z80_|pla_decode_|Equal9~1_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|M5~q ), + .datac(\z80_|execute_|ctl_reg_sel_wz~20_combout ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~40 .lut_mask = 16'hF8F0; +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y19_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~39 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~39_combout = (\z80_|execute_|ctl_alu_op_low~28_combout ) # ((\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|pla_decode_|Equal48~0_combout & !\z80_|sequencer_|DFFE_M1_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|execute_|ctl_alu_op_low~28_combout ), + .datac(\z80_|pla_decode_|Equal48~0_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~39 .lut_mask = 16'hCCEC; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y19_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~13 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[0]~13_combout = (((\z80_|execute_|ctl_reg_sys_hilo[1]~39_combout & \z80_|ir_|opcode [3])) # (!\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout )) # (!\z80_|execute_|ctl_reg_out_lo~9_combout ) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~39_combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~9_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~13 .lut_mask = 16'hBF3F; +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~31 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[0]~31_combout = (((\z80_|execute_|ctl_reg_sys_hilo[0]~40_combout ) # (\z80_|execute_|ctl_reg_sys_hilo[0]~13_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~21_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~21_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[0]~40_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~31 .lut_mask = 16'hFFF7; +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N12 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_63 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_63~combout = (\z80_|execute_|ctl_reg_sys_hilo[0]~31_combout & (\z80_|reg_control_|reg_sys_we_lo~combout & \z80_|execute_|ctl_reg_sel_ir~1_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~31_combout ), + .datac(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datad(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_63 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y12_N9 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[2]~9_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|setM1~49 ( +// Equation(s): +// \z80_|execute_|setM1~49_combout = (!\z80_|execute_|ctl_ir_we~11_combout & (!\z80_|pla_decode_|Equal69~0_combout & ((!\z80_|pla_decode_|Equal63~0_combout ) # (!\z80_|pla_decode_|Equal21~0_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~11_combout ), + .datab(\z80_|pla_decode_|Equal21~0_combout ), + .datac(\z80_|pla_decode_|Equal69~0_combout ), + .datad(\z80_|pla_decode_|Equal63~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~49_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~49 .lut_mask = 16'h0105; +defparam \z80_|execute_|setM1~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_sel_shift~2_combout = (!\z80_|pla_decode_|Equal20~0_combout & !\z80_|execute_|ctl_ir_we~8_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal20~0_combout ), + .datad(\z80_|execute_|ctl_ir_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~2 .lut_mask = 16'h000F; +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|setM1~50 ( +// Equation(s): +// \z80_|execute_|setM1~50_combout = (\z80_|execute_|ctl_flags_hf_cpl~10_combout & (\z80_|execute_|nextM~2_combout & (\z80_|execute_|setM1~49_combout & \z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ))) + + .dataa(\z80_|execute_|ctl_flags_hf_cpl~10_combout ), + .datab(\z80_|execute_|nextM~2_combout ), + .datac(\z80_|execute_|setM1~49_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~50_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~50 .lut_mask = 16'h8000; +defparam \z80_|execute_|setM1~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_flags_oe~0_combout = (!\z80_|execute_|ctl_iorw~11_combout & (!\z80_|execute_|ctl_mRead~4_combout & (!\z80_|execute_|ctl_ir_we~14_combout & !\z80_|execute_|ctl_ir_we~12_combout ))) + + .dataa(\z80_|execute_|ctl_iorw~11_combout ), + .datab(\z80_|execute_|ctl_mRead~4_combout ), + .datac(\z80_|execute_|ctl_ir_we~14_combout ), + .datad(\z80_|execute_|ctl_ir_we~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_oe~0 .lut_mask = 16'h0001; +defparam \z80_|execute_|ctl_flags_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~1 ( +// Equation(s): +// \z80_|execute_|ctl_flags_oe~1_combout = (\z80_|execute_|ctl_al_we~13_combout & (\z80_|execute_|ctl_flags_bus~1_combout & (\z80_|execute_|ctl_flags_oe~0_combout & !\z80_|pla_decode_|Equal13~2_combout ))) + + .dataa(\z80_|execute_|ctl_al_we~13_combout ), + .datab(\z80_|execute_|ctl_flags_bus~1_combout ), + .datac(\z80_|execute_|ctl_flags_oe~0_combout ), + .datad(\z80_|pla_decode_|Equal13~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_oe~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_oe~1 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_flags_oe~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~13 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~13_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & ((!\z80_|execute_|ctl_flags_oe~1_combout ) # (!\z80_|execute_|setM1~50_combout )))) + + .dataa(\z80_|execute_|setM1~50_combout ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|execute_|ctl_flags_oe~1_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~13 .lut_mask = 16'h004C; +defparam \z80_|execute_|ctl_reg_in_hi~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~12 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~12_combout = (!\z80_|execute_|ctl_mRead~12_combout & (!\z80_|execute_|ctl_alu_oe~1_combout & !\z80_|pla_decode_|Equal49~0_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_mRead~12_combout ), + .datac(\z80_|execute_|ctl_alu_oe~1_combout ), + .datad(\z80_|pla_decode_|Equal49~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~12 .lut_mask = 16'h0003; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~7_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal69~0_combout ) # ((!\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ) # (!\z80_|execute_|ctl_sw_1d~8_combout )))) + + .dataa(\z80_|pla_decode_|Equal69~0_combout ), + .datab(\z80_|execute_|ctl_sw_1d~8_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~7 .lut_mask = 16'hBF00; +defparam \z80_|execute_|ctl_reg_in_hi~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~13 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~13_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|execute_|ctl_state_alu~6_combout & !\z80_|pla_decode_|Equal52~1_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|pla_decode_|Equal52~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~13 .lut_mask = 16'hBBBF; +defparam \z80_|execute_|ctl_state_alu~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~6_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout & (!\z80_|execute_|ctl_reg_in_hi~13_combout & (!\z80_|execute_|ctl_reg_in_hi~7_combout & \z80_|execute_|ctl_state_alu~13_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~13_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~7_combout ), + .datad(\z80_|execute_|ctl_state_alu~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~6 .lut_mask = 16'h0100; +defparam \z80_|execute_|ctl_reg_gp_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~5_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout & (((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|pla_decode_|Equal12~1_combout ), + .datad(\z80_|pla_decode_|Equal25~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~5 .lut_mask = 16'h5155; +defparam \z80_|execute_|ctl_reg_gp_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~17 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~17_combout = ((!\z80_|execute_|ctl_mRead~2_combout & ((!\z80_|pla_decode_|Equal32~0_combout ) # (!\z80_|pla_decode_|Equal63~0_combout )))) # (!\z80_|nM1_int~2_combout ) + + .dataa(\z80_|pla_decode_|Equal63~0_combout ), + .datab(\z80_|execute_|ctl_mRead~2_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal32~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~17 .lut_mask = 16'h1F3F; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~18 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~17_combout & (\z80_|execute_|ctl_pf_sel[0]~3_combout & (\z80_|execute_|ctl_flags_pf_we~4_combout & \z80_|execute_|ctl_alu_oe~6_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~17_combout ), + .datab(\z80_|execute_|ctl_pf_sel[0]~3_combout ), + .datac(\z80_|execute_|ctl_flags_pf_we~4_combout ), + .datad(\z80_|execute_|ctl_alu_oe~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~18 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y17_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~10_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout & (((!\z80_|execute_|ctl_mRead~34_combout & !\z80_|pla_decode_|Equal21~1_combout )) # (!\z80_|execute_|ctl_mRead~9_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|execute_|ctl_mRead~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~10 .lut_mask = 16'h0155; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~9 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~9_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|pla_decode_|Equal6~1_combout )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|pla_decode_|Equal6~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~9 .lut_mask = 16'h0300; +defparam \z80_|execute_|ctl_sw_1d~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~9_combout = (!\z80_|execute_|ctl_sw_1d~9_combout & (((!\z80_|execute_|ctl_mRead~16_combout ) # (!\z80_|sequencer_|M5~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|M5~q ), + .datac(\z80_|execute_|ctl_sw_1d~9_combout ), + .datad(\z80_|execute_|ctl_mRead~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~9 .lut_mask = 16'h070F; +defparam \z80_|execute_|ctl_reg_gp_we~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~4_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~10_combout & \z80_|execute_|ctl_reg_gp_we~9_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_gp_we~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~4 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_reg_gp_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~7_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~6_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|execute_|ctl_reg_gp_we~5_combout & \z80_|execute_|ctl_reg_gp_we~4_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~5_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~7 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~3_combout = (\z80_|execute_|ctl_inc_cy~78_combout & (\z80_|execute_|ctl_bus_inc_oe~48_combout & (\z80_|execute_|ctl_bus_inc_oe~26_combout & \z80_|execute_|ctl_inc_cy~49_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~78_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~48_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~26_combout ), + .datad(\z80_|execute_|ctl_inc_cy~49_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~3 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~32 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~32_combout = (\z80_|execute_|ctl_reg_gp_we~2_combout & (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout & ((!\z80_|execute_|ixy_d~9_combout ) # (!\z80_|pla_decode_|Equal10~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~2_combout ), + .datac(\z80_|execute_|ixy_d~9_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~32 .lut_mask = 16'h004C; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~2 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~2_combout = (\z80_|execute_|nextM~2_combout & (((!\z80_|execute_|ixy_d~9_combout )) # (!\z80_|pla_decode_|Equal11~0_combout ))) # (!\z80_|execute_|nextM~2_combout & (!\z80_|execute_|ixy_d~5_combout & +// ((!\z80_|execute_|ixy_d~9_combout ) # (!\z80_|pla_decode_|Equal11~0_combout )))) + + .dataa(\z80_|execute_|nextM~2_combout ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|execute_|ixy_d~9_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~2 .lut_mask = 16'h2A3F; +defparam \z80_|execute_|ctl_sw_4u~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~3 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~3_combout = (\z80_|execute_|ctl_reg_gp_we~3_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout & \z80_|execute_|ctl_sw_4u~2_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~3_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout ), + .datac(\z80_|execute_|ctl_sw_4u~2_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~3 .lut_mask = 16'h8080; +defparam \z80_|execute_|ctl_sw_4u~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~8_combout = (\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # (((!\z80_|execute_|ctl_reg_gp_hilo[1]~15_combout ) # (!\z80_|execute_|ctl_sw_4u~3_combout )) # (!\z80_|execute_|ctl_reg_gp_we~7_combout )) + + .dataa(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datac(\z80_|execute_|ctl_sw_4u~3_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~8 .lut_mask = 16'hBFFF; +defparam \z80_|execute_|ctl_reg_gp_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~14 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~14_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~13_combout & ((\z80_|pla_decode_|Equal33~1_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~15_combout & +// !\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~13_combout ), + .datab(\z80_|pla_decode_|Equal33~1_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~15_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~14 .lut_mask = 16'h888A; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~24 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~24_combout = (\z80_|execute_|rsel3~combout & (((\z80_|nM1_int~2_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~12_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~14_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~14_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ), + .datad(\z80_|execute_|rsel3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~24 .lut_mask = 16'h5D00; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout = (\z80_|sequencer_|DFFE_M4_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & (!\z80_|pla_decode_|Equal12~1_combout & \z80_|pla_decode_|Equal25~0_combout ))) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|pla_decode_|Equal12~1_combout ), + .datad(\z80_|pla_decode_|Equal25~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~25 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~25_combout = (\z80_|execute_|ctl_ir_we~7_combout ) # ((\z80_|execute_|ctl_ir_we~15_combout ) # ((!\z80_|execute_|ctl_reg_sys_hilo~21_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~7_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~25 .lut_mask = 16'hEFFF; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~26 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~26_combout = (\z80_|execute_|ctl_state_alu~3_combout & ((\z80_|execute_|ctl_iorw~10_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ) # (\z80_|execute_|ctl_state_alu~6_combout )))) + + .dataa(\z80_|execute_|ctl_iorw~10_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|ctl_state_alu~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~26 .lut_mask = 16'hFE00; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~46 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~46_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # ((\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T2_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|nextM~2_combout ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~46 .lut_mask = 16'h0E0C; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~27 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~27_combout = ((\z80_|execute_|ctl_reg_gp_hilo[0]~46_combout ) # ((\z80_|pla_decode_|Equal6~1_combout & \z80_|execute_|ixy_d~7_combout ))) # (!\z80_|execute_|ctl_mRead~23_combout ) + + .dataa(\z80_|execute_|ctl_mRead~23_combout ), + .datab(\z80_|pla_decode_|Equal6~1_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~46_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~27 .lut_mask = 16'hFDF5; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~29 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~29_combout = (\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ) # +// (!\z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~29 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~22 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~22_combout = (\z80_|execute_|ixy_d~7_combout & (((\z80_|execute_|ctl_mWrite~6_combout ) # (\z80_|execute_|ctl_mRead~5_combout )) # (!\z80_|execute_|ctl_al_we~13_combout ))) + + .dataa(\z80_|execute_|ctl_al_we~13_combout ), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datac(\z80_|execute_|ctl_mRead~5_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~22 .lut_mask = 16'hFD00; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~23 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~23_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~22_combout ) # ((!\z80_|execute_|ctl_flags_oe~1_combout & ((\z80_|execute_|ctl_state_alu~3_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~3_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|execute_|ctl_flags_oe~1_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~23 .lut_mask = 16'hFF0B; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~31 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~31_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~24_combout ) # (((\z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ) # (\z80_|execute_|ctl_reg_gp_hilo[0]~23_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~30_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~24_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~23_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~31 .lut_mask = 16'hFFFB; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~33 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~33_combout = (\z80_|execute_|ixy_d~6_combout & (((!\z80_|pla_decode_|Equal10~0_combout & !\z80_|pla_decode_|Equal11~0_combout )))) # (!\z80_|execute_|ixy_d~6_combout & (((!\z80_|pla_decode_|Equal11~0_combout )) # +// (!\z80_|execute_|ixy_d~9_combout ))) + + .dataa(\z80_|execute_|ixy_d~9_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|pla_decode_|Equal11~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~33 .lut_mask = 16'h113F; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~26 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~26_combout = (\z80_|execute_|ctl_reg_gp_we~3_combout & (\z80_|execute_|fMRead~8_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~4_combout & \z80_|execute_|fMRead~10_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_we~3_combout ), + .datab(\z80_|execute_|fMRead~8_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), + .datad(\z80_|execute_|fMRead~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~26 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~34 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~34_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~12_combout & \z80_|execute_|ctl_reg_gp_sel[1]~26_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~12_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~34 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~25 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~25_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout & (\z80_|execute_|ctl_state_alu~13_combout & \z80_|execute_|ctl_reg_gp_sel[0]~24_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .datab(\z80_|execute_|ctl_state_alu~13_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~25 .lut_mask = 16'h4040; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~20 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~20_combout = (\z80_|execute_|ctl_reg_gp_sel~7_combout ) # ((!\z80_|execute_|ctl_reg_gp_hilo[1]~15_combout ) # (!\z80_|execute_|ctl_sw_2u~5_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_sel~7_combout ), + .datab(\z80_|execute_|ctl_sw_2u~5_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~20 .lut_mask = 16'hBBFF; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~21 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~21_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout & ((\z80_|execute_|rsel0~combout ) # ((!\z80_|execute_|setM1~50_combout & !\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) # +// (!\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout & (((!\z80_|execute_|setM1~50_combout & !\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), + .datab(\z80_|execute_|rsel0~combout ), + .datac(\z80_|execute_|setM1~50_combout ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~21 .lut_mask = 16'h888F; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~35 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~35_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ) # (((\z80_|execute_|ctl_reg_gp_hilo[0]~21_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[0]~25_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~34_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~34_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~35 .lut_mask = 16'hFFBF; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N14 +cycloneive_lcell_comb \z80_|pla_decode_|Equal2~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal2~2_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal1~7_combout & \z80_|pla_decode_|Equal32~0_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal2~0_combout ), + .datac(\z80_|pla_decode_|Equal1~7_combout ), + .datad(\z80_|pla_decode_|Equal32~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal2~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal2~2 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N14 +cycloneive_lcell_comb \z80_|pla_decode_|Equal1~6 ( +// Equation(s): +// \z80_|pla_decode_|Equal1~6_combout = (\z80_|pla_decode_|Equal1~4_combout & (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal1~5_combout & \z80_|pla_decode_|Equal1~7_combout ))) + + .dataa(\z80_|pla_decode_|Equal1~4_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|pla_decode_|Equal1~5_combout ), + .datad(\z80_|pla_decode_|Equal1~7_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal1~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal1~6 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal1~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N20 +cycloneive_lcell_comb \z80_|reg_control_|bank_exx~2 ( +// Equation(s): +// \z80_|reg_control_|bank_exx~2_combout = \z80_|reg_control_|bank_exx~q $ (((\z80_|pla_decode_|Equal1~6_combout & (\z80_|sequencer_|DFFE_T2_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )))) + + .dataa(\z80_|pla_decode_|Equal1~6_combout ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|reg_control_|bank_exx~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|reg_control_|bank_exx~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|bank_exx~2 .lut_mask = 16'hF078; +defparam \z80_|reg_control_|bank_exx~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y15_N21 +dffeas \z80_|reg_control_|bank_exx ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_control_|bank_exx~2_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_control_|bank_exx~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_control_|bank_exx .is_wysiwyg = "true"; +defparam \z80_|reg_control_|bank_exx .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N6 +cycloneive_lcell_comb \z80_|reg_control_|bank_hl_de1~0 ( +// Equation(s): +// \z80_|reg_control_|bank_hl_de1~0_combout = \z80_|reg_control_|bank_hl_de1~q $ (((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|pla_decode_|Equal2~2_combout & !\z80_|reg_control_|bank_exx~q )))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|pla_decode_|Equal2~2_combout ), + .datac(\z80_|reg_control_|bank_hl_de1~q ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_control_|bank_hl_de1~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|bank_hl_de1~0 .lut_mask = 16'hF0B4; +defparam \z80_|reg_control_|bank_hl_de1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y15_N7 +dffeas \z80_|reg_control_|bank_hl_de1 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_control_|bank_hl_de1~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_control_|bank_hl_de1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_control_|bank_hl_de1 .is_wysiwyg = "true"; +defparam \z80_|reg_control_|bank_hl_de1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~19 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout = (\z80_|execute_|ctl_sw_1d~4_combout & (((\z80_|execute_|ctl_sw_1d~8_combout & !\z80_|pla_decode_|Equal69~0_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_sw_1d~4_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|execute_|ctl_sw_1d~8_combout ), + .datad(\z80_|pla_decode_|Equal69~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~19 .lut_mask = 16'h22A2; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~28 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~28_combout = (!\z80_|execute_|ctl_reg_gp_sel~7_combout & \z80_|execute_|ctl_sw_2u~2_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_sel~7_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_sw_2u~2_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~28 .lut_mask = 16'h5050; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~29 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~29_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~28_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~27_combout & !\z80_|execute_|ctl_reg_in_hi~13_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~28_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~27_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~29 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~30 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~30_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~25_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~29_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~26_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~29_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~30 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y15_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~13 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~13_combout = (!\z80_|execute_|ctl_sw_1d~9_combout & (((!\z80_|execute_|ctl_state_alu~3_combout & !\z80_|execute_|ixy_d~7_combout )) # (!\z80_|execute_|ctl_mWrite~6_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~3_combout ), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ctl_sw_1d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~13 .lut_mask = 16'h0037; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~45 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~45_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~14_combout & ((\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ) # ((\z80_|sequencer_|DFFE_M1_ff~q ) # (\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~14_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~45 .lut_mask = 16'hAAA8; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~2_combout = (((!\z80_|execute_|ctl_mRead~9_combout & !\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal6~0_combout )) # (!\z80_|pla_decode_|Equal8~0_combout ) + + .dataa(\z80_|execute_|ctl_mRead~9_combout ), + .datab(\z80_|pla_decode_|Equal8~0_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~2 .lut_mask = 16'h3F7F; +defparam \z80_|execute_|ctl_reg_use_sp~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~3_combout = (\z80_|execute_|nextM~11_combout & (\z80_|execute_|ctl_bus_inc_oe~49_combout & (\z80_|execute_|ctl_reg_use_sp~0_combout & \z80_|execute_|ctl_reg_use_sp~2_combout ))) + + .dataa(\z80_|execute_|nextM~11_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~49_combout ), + .datac(\z80_|execute_|ctl_reg_use_sp~0_combout ), + .datad(\z80_|execute_|ctl_reg_use_sp~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~3 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_use_sp~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~14 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~14_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~13_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~45_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~6_combout & \z80_|execute_|ctl_reg_use_sp~3_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~13_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), + .datad(\z80_|execute_|ctl_reg_use_sp~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~14 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~32 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~32_combout = (\z80_|ir_|opcode [4] & (((!\z80_|execute_|ctl_reg_sys_hilo~21_combout & \z80_|execute_|ctl_state_alu~3_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|execute_|ctl_reg_sys_hilo~21_combout ), + .datad(\z80_|execute_|ctl_state_alu~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~32 .lut_mask = 16'h4C44; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~33 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~33_combout = (\z80_|execute_|ixy_d~7_combout & (((\z80_|execute_|ctl_mRead~3_combout ) # (\z80_|pla_decode_|Equal11~0_combout )))) # (!\z80_|execute_|ixy_d~7_combout & (\z80_|execute_|ixy_d~5_combout & +// ((\z80_|pla_decode_|Equal11~0_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_mRead~3_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|pla_decode_|Equal11~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~33 .lut_mask = 16'hFAC0; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~16 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~16_combout = (\z80_|execute_|setM1~57_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~15_combout & (\z80_|execute_|ctl_sw_2u~4_combout & \z80_|execute_|ctl_sw_2u~1_combout ))) + + .dataa(\z80_|execute_|setM1~57_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~15_combout ), + .datac(\z80_|execute_|ctl_sw_2u~4_combout ), + .datad(\z80_|execute_|ctl_sw_2u~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~16 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~34 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~34_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ) # ((!\z80_|execute_|ctl_reg_gp_hilo[1]~16_combout & \z80_|ir_|opcode [1])) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~16_combout ), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~34 .lut_mask = 16'hCFCC; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~35 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~35_combout = ((\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ) # (\z80_|execute_|ctl_reg_gp_sel[0]~34_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~35 .lut_mask = 16'hFFF5; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~20 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~20_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|pla_decode_|Equal4~0_combout ) # ((\z80_|pla_decode_|Equal1~4_combout & \z80_|pla_decode_|Equal2~1_combout )))) + + .dataa(\z80_|pla_decode_|Equal4~0_combout ), + .datab(\z80_|pla_decode_|Equal1~4_combout ), + .datac(\z80_|pla_decode_|Equal2~1_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~20 .lut_mask = 16'hEA00; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~21 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~21_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout ) # (\z80_|execute_|ctl_state_alu~2_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|nextM~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~21 .lut_mask = 16'h00FE; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~22 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~22_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~20_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~21_combout ) # ((\z80_|execute_|ctl_mRead~34_combout & \z80_|execute_|ctl_state_alu~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~20_combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~22 .lut_mask = 16'hFFEA; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~18 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~18_combout = (\z80_|execute_|ctl_mWrite~17_combout ) # ((\z80_|execute_|ctl_mRead~5_combout ) # ((\z80_|pla_decode_|Equal21~0_combout & \z80_|pla_decode_|Equal24~0_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~17_combout ), + .datab(\z80_|pla_decode_|Equal21~0_combout ), + .datac(\z80_|execute_|ctl_mRead~5_combout ), + .datad(\z80_|pla_decode_|Equal24~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~18 .lut_mask = 16'hFEFA; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~37 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~37_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~5_combout & (((!\z80_|execute_|ctl_mWrite~17_combout ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), + .datad(\z80_|execute_|ctl_mWrite~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~37 .lut_mask = 16'h70F0; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~19 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~19_combout = ((\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~18_combout & \z80_|execute_|ixy_d~7_combout ))) # (!\z80_|execute_|ctl_reg_gp_sel[1]~37_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~18_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~37_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~19 .lut_mask = 16'hFF8F; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~23 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~23_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~22_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ) # ((!\z80_|execute_|ctl_reg_gp_hilo[1]~16_combout & \z80_|ir_|opcode [2]))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~22_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~16_combout ), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~23 .lut_mask = 16'hEFEE; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y14_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~16 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~16_combout = (\z80_|execute_|ctl_state_alu~3_combout & (((\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout )) # (!\z80_|execute_|ctl_mRead~17_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~17_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|ctl_state_alu~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~16 .lut_mask = 16'hF700; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~17 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~17_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~16_combout ) # ((\z80_|execute_|ixy_d~15_combout & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~16_combout ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|execute_|ixy_d~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~17 .lut_mask = 16'hFECC; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~11 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~11_combout = (!\z80_|decode_state_|DFFE_instCB~q & (!\z80_|decode_state_|DFFE_instED~q & ((\z80_|sequencer_|DFFE_M4_ff~q ) # (\z80_|sequencer_|M5~q )))) + + .dataa(\z80_|decode_state_|DFFE_instCB~q ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|decode_state_|DFFE_instED~q ), + .datad(\z80_|sequencer_|M5~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~11 .lut_mask = 16'h0504; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~36 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~36_combout = (\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [2] & (\z80_|execute_|ctl_reg_gp_sel[1]~11_combout & !\z80_|ir_|opcode [4]))) + + .dataa(\z80_|ir_|opcode [1]), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~36 .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~8_combout = (\z80_|ir_|opcode [7] & (!\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|ir_|opcode [3] & \z80_|ir_|opcode [6]))) + + .dataa(\z80_|ir_|opcode [7]), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~8 .lut_mask = 16'h0200; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~9_combout = (\z80_|ir_|opcode [3] & (((\z80_|sequencer_|DFFE_T3_ff~q )))) # (!\z80_|ir_|opcode [3] & (((!\z80_|pla_decode_|Equal12~0_combout & \z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal12~0_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~9 .lut_mask = 16'hBF05; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~10 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~10_combout = (\z80_|ir_|opcode [0] & (\z80_|execute_|ctl_reg_gp_sel[1]~8_combout )) # (!\z80_|ir_|opcode [0] & (((\z80_|execute_|ctl_reg_gp_sel[1]~9_combout & \z80_|execute_|ctl_ir_we~6_combout )))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~8_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~9_combout ), + .datad(\z80_|execute_|ctl_ir_we~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~10 .lut_mask = 16'hD888; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~15 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~15_combout = (\z80_|ir_|opcode [5] & (((\z80_|execute_|ctl_reg_gp_sel[1]~36_combout & \z80_|execute_|ctl_reg_gp_sel[1]~10_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~15 .lut_mask = 16'hA222; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~31 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~31_combout = ((\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~17_combout ) # (\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ))) # (!\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~17_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~31 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N24 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~5 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_de2~5_combout = (!\z80_|decode_state_|DFFE_instIY1~q & (!\z80_|decode_state_|DFFE_inst4~q & (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & \z80_|execute_|ctl_reg_gp_sel[1]~31_combout ))) + + .dataa(\z80_|decode_state_|DFFE_instIY1~q ), + .datab(\z80_|decode_state_|DFFE_inst4~q ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_de2~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_de2~5 .lut_mask = 16'h0100; +defparam \z80_|reg_control_|reg_sel_de2~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N28 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~6 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_de2~6_combout = (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (((\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ) # (\z80_|execute_|ctl_reg_gp_sel[0]~32_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_de2~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_de2~6 .lut_mask = 16'h00FD; +defparam \z80_|reg_control_|reg_sel_de2~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N24 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_de~0_combout = (!\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de1~q & (\z80_|reg_control_|reg_sel_de2~5_combout )) # (!\z80_|reg_control_|bank_hl_de1~q & ((\z80_|reg_control_|reg_sel_de2~6_combout ))))) + + .dataa(\z80_|reg_control_|bank_hl_de1~q ), + .datab(\z80_|reg_control_|bank_exx~q ), + .datac(\z80_|reg_control_|reg_sel_de2~5_combout ), + .datad(\z80_|reg_control_|reg_sel_de2~6_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_de~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_de~0 .lut_mask = 16'h3120; +defparam \z80_|reg_control_|reg_sel_de~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N14 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_50 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_50~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout & \z80_|reg_control_|reg_sel_de~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .datad(\z80_|reg_control_|reg_sel_de~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_50 .lut_mask = 16'h5000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N22 +cycloneive_lcell_comb \z80_|reg_control_|bank_hl_de2~0 ( +// Equation(s): +// \z80_|reg_control_|bank_hl_de2~0_combout = \z80_|reg_control_|bank_hl_de2~q $ (((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|pla_decode_|Equal2~2_combout & \z80_|reg_control_|bank_exx~q )))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|pla_decode_|Equal2~2_combout ), + .datac(\z80_|reg_control_|bank_hl_de2~q ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_control_|bank_hl_de2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|bank_hl_de2~0 .lut_mask = 16'hB4F0; +defparam \z80_|reg_control_|bank_hl_de2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y15_N23 +dffeas \z80_|reg_control_|bank_hl_de2 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_control_|bank_hl_de2~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_control_|bank_hl_de2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_control_|bank_hl_de2 .is_wysiwyg = "true"; +defparam \z80_|reg_control_|bank_hl_de2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N16 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~4 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_de2~4_combout = (\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de2~q & (\z80_|reg_control_|reg_sel_de2~5_combout )) # (!\z80_|reg_control_|bank_hl_de2~q & ((\z80_|reg_control_|reg_sel_de2~6_combout ))))) + + .dataa(\z80_|reg_control_|bank_hl_de2~q ), + .datab(\z80_|reg_control_|bank_exx~q ), + .datac(\z80_|reg_control_|reg_sel_de2~5_combout ), + .datad(\z80_|reg_control_|reg_sel_de2~6_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_de2~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_de2~4 .lut_mask = 16'hC480; +defparam \z80_|reg_control_|reg_sel_de2~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N24 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_46 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_46~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout & \z80_|reg_control_|reg_sel_de2~4_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .datad(\z80_|reg_control_|reg_sel_de2~4_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_46 .lut_mask = 16'h5000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N22 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_47 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_47~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout & \z80_|reg_control_|reg_sel_de2~4_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .datad(\z80_|reg_control_|reg_sel_de2~4_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_47 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y11_N1 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N16 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_51 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_51~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout & \z80_|reg_control_|reg_sel_de~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .datad(\z80_|reg_control_|reg_sel_de~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_51 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y11_N7 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~33 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~33_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [2]), + .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~33 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[2]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N8 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_hl~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_hl~0_combout = (!\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de1~q & ((\z80_|reg_control_|reg_sel_de2~6_combout ))) # (!\z80_|reg_control_|bank_hl_de1~q & (\z80_|reg_control_|reg_sel_de2~5_combout )))) + + .dataa(\z80_|reg_control_|bank_hl_de1~q ), + .datab(\z80_|reg_control_|bank_exx~q ), + .datac(\z80_|reg_control_|reg_sel_de2~5_combout ), + .datad(\z80_|reg_control_|reg_sel_de2~6_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_hl~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_hl~0 .lut_mask = 16'h3210; +defparam \z80_|reg_control_|reg_sel_hl~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N26 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_59 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_59~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout & (\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|reg_control_|reg_sel_hl~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_59 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y12_N31 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N30 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_hl2~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_hl2~0_combout = (\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de2~q & ((\z80_|reg_control_|reg_sel_de2~6_combout ))) # (!\z80_|reg_control_|bank_hl_de2~q & (\z80_|reg_control_|reg_sel_de2~5_combout )))) + + .dataa(\z80_|reg_control_|bank_hl_de2~q ), + .datab(\z80_|reg_control_|bank_exx~q ), + .datac(\z80_|reg_control_|reg_sel_de2~5_combout ), + .datad(\z80_|reg_control_|reg_sel_de2~6_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_hl2~0 .lut_mask = 16'hC840; +defparam \z80_|reg_control_|reg_sel_hl2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N4 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_54 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_54~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout & (!\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|reg_control_|reg_sel_hl2~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_54 .lut_mask = 16'h2200; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N18 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_55 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_55~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout & (\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|reg_control_|reg_sel_hl2~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_55 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y12_N25 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N20 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_58 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_58~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout & (!\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|reg_control_|reg_sel_hl~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_58 .lut_mask = 16'h0A00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~34 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~34_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [2] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [2] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [2]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~34 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp0[2]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N2 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout & !\z80_|execute_|ctl_reg_gp_we~8_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 .lut_mask = 16'h0C0C; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N0 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout = (\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & !\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ))) + + .dataa(\z80_|reg_control_|bank_exx~q ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 .lut_mask = 16'h0020; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N22 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout & \z80_|execute_|ctl_reg_gp_we~8_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 .lut_mask = 16'hC0C0; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N18 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout = (!\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & !\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ))) + + .dataa(\z80_|reg_control_|bank_exx~q ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 .lut_mask = 16'h0010; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y14_N29 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N12 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout = (\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & !\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ))) + + .dataa(\z80_|reg_control_|bank_exx~q ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 .lut_mask = 16'h0020; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y14_N7 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N16 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout = (!\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & !\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ))) + + .dataa(\z80_|reg_control_|bank_exx~q ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 .lut_mask = 16'h0010; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~36 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~36_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [2]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [2]), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~36 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[2]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~15 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~15_combout = (((\z80_|execute_|ctl_66_oe~2_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~14_combout )) # (!\z80_|execute_|ctl_reg_in_hi~5_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~13_combout ) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~13_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~5_combout ), + .datac(\z80_|execute_|ctl_66_oe~2_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~15 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|ctl_reg_sel_wz~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~18 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~18_combout = (((\z80_|execute_|ctl_reg_sel_wz~15_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~12_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~21_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~17_combout ) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~17_combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~21_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~12_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~18 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_reg_sel_wz~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N0 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_83 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_83~combout = (\z80_|execute_|ctl_reg_sel_wz~18_combout & (\z80_|reg_control_|reg_sys_we_lo~combout & \z80_|execute_|ctl_reg_sys_hilo[0]~31_combout )) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~18_combout ), + .datab(gnd), + .datac(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_83 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_83 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y13_N5 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N8 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_82 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_82~combout = (\z80_|execute_|ctl_reg_sel_wz~18_combout & (!\z80_|reg_control_|reg_sys_we_lo~combout & \z80_|execute_|ctl_reg_sys_hilo[0]~31_combout )) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~18_combout ), + .datab(gnd), + .datac(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_82 .lut_mask = 16'h0A00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_82 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~37 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~37_combout = (\z80_|reg_file_|gdfx_temp0[2]~36_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|gdfx_temp0[2]~36_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~37 .lut_mask = 16'hC0CC; +defparam \z80_|reg_file_|gdfx_temp0[2]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N6 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & (\z80_|decode_state_|DFFE_inst4~q & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), + .datab(\z80_|decode_state_|DFFE_inst4~q ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 .lut_mask = 16'h0080; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N14 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_iy~2 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_iy~2_combout = (\z80_|decode_state_|DFFE_instIY1~q & (!\z80_|decode_state_|DFFE_inst4~q & (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & \z80_|execute_|ctl_reg_gp_sel[1]~31_combout ))) + + .dataa(\z80_|decode_state_|DFFE_instIY1~q ), + .datab(\z80_|decode_state_|DFFE_inst4~q ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_iy~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_iy~2 .lut_mask = 16'h0200; +defparam \z80_|reg_control_|reg_sel_iy~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N10 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_71 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_71~combout = (\z80_|reg_control_|reg_sel_iy~2_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout & \z80_|execute_|ctl_reg_gp_we~8_combout )) + + .dataa(gnd), + .datab(\z80_|reg_control_|reg_sel_iy~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y12_N3 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N28 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|decode_state_|DFFE_inst4~q ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|decode_state_|DFFE_inst4~q ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 .lut_mask = 16'h2000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y12_N1 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N12 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_70 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_70~combout = (\z80_|reg_control_|reg_sel_iy~2_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout & !\z80_|execute_|ctl_reg_gp_we~8_combout )) + + .dataa(gnd), + .datab(\z80_|reg_control_|reg_sel_iy~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70 .lut_mask = 16'h00C0; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~38 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~38_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (\z80_|reg_file_|b2v_latch_ix_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [2]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_iy_lo|latch [2]), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~38 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[2]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout = (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|ir_|opcode [3] & (\z80_|ir_|opcode [4] & \z80_|pla_decode_|Equal24~0_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|pla_decode_|Equal24~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~9_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|execute_|ctl_mRead~2_combout )))) # (!\z80_|pla_decode_|Equal47~0_combout +// & (((!\z80_|execute_|ixy_d~7_combout )) # (!\z80_|execute_|ctl_mRead~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal47~0_combout ), + .datab(\z80_|execute_|ctl_mRead~2_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~9 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_reg_in_hi~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~10 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~10_combout = (\z80_|execute_|ctl_reg_gp_we~7_combout & (\z80_|execute_|ctl_reg_in_hi~8_combout & \z80_|execute_|ctl_reg_in_hi~9_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_in_hi~8_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~10 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_reg_in_hi~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_lo~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_lo~8_combout = (\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ) # (((!\z80_|execute_|ctl_reg_in_hi~10_combout ) # (!\z80_|execute_|ctl_reg_in_lo~9_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~21_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~21_combout ), + .datac(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_lo~8 .lut_mask = 16'hBFFF; +defparam \z80_|execute_|ctl_reg_in_lo~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N0 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_sp_lo|latch[2]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_sp_lo|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp0[2]~42_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_sp_lo|latch[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[2]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~4_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal6~1_combout & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_M1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|pla_decode_|Equal6~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~4 .lut_mask = 16'h0D00; +defparam \z80_|execute_|ctl_reg_use_sp~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~5_combout = (\z80_|execute_|ctl_reg_use_sp~4_combout ) # ((\z80_|execute_|ctl_mRead~15_combout & ((\z80_|execute_|ctl_reg_in_hi~2_combout ) # (\z80_|execute_|ctl_state_alu~4_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~15_combout ), + .datab(\z80_|execute_|ctl_reg_use_sp~4_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~5 .lut_mask = 16'hEEEC; +defparam \z80_|execute_|ctl_reg_use_sp~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~6_combout = (\z80_|execute_|ctl_reg_use_sp~5_combout ) # ((!\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ) # (!\z80_|execute_|ctl_reg_use_sp~3_combout )) + + .dataa(\z80_|execute_|ctl_reg_use_sp~5_combout ), + .datab(\z80_|execute_|ctl_reg_use_sp~3_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~6 .lut_mask = 16'hBFBF; +defparam \z80_|execute_|ctl_reg_use_sp~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N14 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout = (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & \z80_|execute_|ctl_reg_gp_sel[1]~31_combout ))) + + .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y12_N1 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_sp_lo|latch[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~5 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~5_combout = (\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_mRead~12_combout ) # ((\z80_|pla_decode_|Equal49~0_combout ) # (!\z80_|execute_|ctl_sw_1d~8_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~12_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|execute_|ctl_sw_1d~8_combout ), + .datad(\z80_|pla_decode_|Equal49~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~5 .lut_mask = 16'hCC8C; +defparam \z80_|execute_|ctl_sw_1d~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y19_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_im_we ( +// Equation(s): +// \z80_|execute_|ctl_im_we~combout = (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_im_we~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_im_we .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_im_we .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~6 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~6_combout = (\z80_|execute_|ctl_sw_1d~4_combout & (!\z80_|execute_|ctl_sw_1d~5_combout & (\z80_|execute_|ctl_sw_2d~9_combout & !\z80_|execute_|ctl_im_we~combout ))) + + .dataa(\z80_|execute_|ctl_sw_1d~4_combout ), + .datab(\z80_|execute_|ctl_sw_1d~5_combout ), + .datac(\z80_|execute_|ctl_sw_2d~9_combout ), + .datad(\z80_|execute_|ctl_im_we~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~6 .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_sw_1d~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~7 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~7_combout = ((\z80_|execute_|ctl_66_oe~2_combout & !\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q )) # (!\z80_|execute_|ctl_sw_1d~6_combout ) + + .dataa(\z80_|execute_|ctl_66_oe~2_combout ), + .datab(\z80_|execute_|ctl_sw_1d~6_combout ), + .datac(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~7 .lut_mask = 16'h3B3B; +defparam \z80_|execute_|ctl_sw_1d~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N18 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[2]~2 ( +// Equation(s): +// \z80_|reg_file_|db_lo_ds[2]~2_combout = (\z80_|reg_file_|gdfx_temp0[2]~42_combout ) # ((!\z80_|execute_|ctl_reg_out_lo~5_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout & \z80_|execute_|ctl_reg_out_lo~7_combout ))) + + .dataa(\z80_|execute_|ctl_reg_out_lo~5_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_ds[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_ds[2]~2 .lut_mask = 16'hFF40; +defparam \z80_|reg_file_|db_lo_ds[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N8 +cycloneive_lcell_comb \z80_|alu_control_|db[2]~28 ( +// Equation(s): +// \z80_|alu_control_|db[2]~28_combout = (\z80_|reg_file_|db_lo_ds[2]~2_combout & (((!\z80_|execute_|ctl_sw_mask543_en~0_combout & \z80_|bus_control_|db[2]~13_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) + + .dataa(\z80_|execute_|ctl_sw_mask543_en~0_combout ), + .datab(\z80_|bus_control_|db[2]~13_combout ), + .datac(\z80_|execute_|ctl_sw_1d~7_combout ), + .datad(\z80_|reg_file_|db_lo_ds[2]~2_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[2]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[2]~28 .lut_mask = 16'h4F00; +defparam \z80_|alu_control_|db[2]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~11 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~11_combout = (((\z80_|execute_|ixy_d~6_combout & \z80_|pla_decode_|Equal9~1_combout )) # (!\z80_|execute_|ctl_reg_in_hi~5_combout )) # (!\z80_|execute_|ctl_reg_in_hi~6_combout ) + + .dataa(\z80_|execute_|ctl_reg_in_hi~6_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~5_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~11 .lut_mask = 16'hF777; +defparam \z80_|execute_|ctl_reg_in_hi~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~12 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~12_combout = (((\z80_|execute_|ctl_reg_in_hi~11_combout ) # (!\z80_|execute_|ctl_reg_in_hi~4_combout )) # (!\z80_|execute_|ctl_reg_in_hi~3_combout )) # (!\z80_|execute_|ctl_reg_in_hi~10_combout ) + + .dataa(\z80_|execute_|ctl_reg_in_hi~10_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~3_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~11_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~12 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|ctl_reg_in_hi~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~42 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~42_combout = ((\z80_|execute_|ctl_state_alu~3_combout & ((!\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ) # (!\z80_|execute_|setM1~48_combout )))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~34_combout ) + + .dataa(\z80_|execute_|setM1~48_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ), + .datac(\z80_|execute_|ctl_state_alu~3_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~42 .lut_mask = 16'h70FF; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~39 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~39_combout = ((\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mRead~3_combout ) # (!\z80_|execute_|ctl_al_we~14_combout )))) # (!\z80_|execute_|setM1~30_combout ) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|setM1~30_combout ), + .datac(\z80_|execute_|ctl_mRead~3_combout ), + .datad(\z80_|execute_|ctl_al_we~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~39 .lut_mask = 16'hB3BB; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~38 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~38_combout = ((!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ixy_d~5_combout ) # (\z80_|execute_|ctl_state_alu~2_combout )))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), + .datad(\z80_|execute_|nextM~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~38 .lut_mask = 16'h0FEF; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~40 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~40_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ) # ((!\z80_|execute_|rsel3~combout & !\z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ), + .datab(\z80_|execute_|rsel3~combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~40 .lut_mask = 16'hFAFB; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~41 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~41_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ) # (((!\z80_|execute_|rsel0~combout & \z80_|execute_|ctl_reg_gp_hilo[1]~20_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), + .datab(\z80_|execute_|rsel0~combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~41 .lut_mask = 16'hBFAF; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~43 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~43_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ) # (((\z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ) # (!\z80_|execute_|ctl_reg_gp_we~4_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~43 .lut_mask = 16'hFBFF; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N12 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout & !\z80_|execute_|ctl_reg_gp_we~8_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 .lut_mask = 16'h00F0; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N14 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout & (\z80_|decode_state_|DFFE_inst4~q & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .datac(\z80_|decode_state_|DFFE_inst4~q ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 .lut_mask = 16'h0080; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N30 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|execute_|ctl_reg_use_sp~6_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datac(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N14 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_68 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_68~combout = (\z80_|reg_control_|reg_sel_iy~2_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout & !\z80_|execute_|ctl_reg_gp_we~8_combout )) + + .dataa(gnd), + .datab(\z80_|reg_control_|reg_sel_iy~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68 .lut_mask = 16'h00C0; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N0 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout = (!\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) + + .dataa(\z80_|reg_control_|bank_exx~q ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 .lut_mask = 16'h0010; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N8 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout = (\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) + + .dataa(\z80_|reg_control_|bank_exx~q ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 .lut_mask = 16'h0200; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~18 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~18_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~18 .lut_mask = 16'hFEFE; +defparam \z80_|reg_file_|gdfx_temp1[0]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N26 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_80 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_80~combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout & (!\z80_|reg_control_|reg_sys_we_hi~combout & \z80_|execute_|ctl_reg_sel_wz~18_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), + .datac(\z80_|reg_control_|reg_sys_we_hi~combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~18_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_80 .lut_mask = 16'h0C00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y13_N14 +cycloneive_lcell_comb \z80_|pla_decode_|Equal21~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal21~2_combout = (\z80_|pla_decode_|Equal40~0_combout & (\z80_|pla_decode_|Equal6~0_combout & !\z80_|ir_|opcode [5])) + + .dataa(\z80_|pla_decode_|Equal40~0_combout ), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(gnd), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal21~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal21~2 .lut_mask = 16'h0088; +defparam \z80_|pla_decode_|Equal21~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N4 +cycloneive_lcell_comb \z80_|reg_control_|bank_af~0 ( +// Equation(s): +// \z80_|reg_control_|bank_af~0_combout = \z80_|reg_control_|bank_af~q $ (((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|pla_decode_|Equal32~0_combout & \z80_|pla_decode_|Equal21~2_combout )))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|pla_decode_|Equal32~0_combout ), + .datac(\z80_|reg_control_|bank_af~q ), + .datad(\z80_|pla_decode_|Equal21~2_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|bank_af~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|bank_af~0 .lut_mask = 16'hB4F0; +defparam \z80_|reg_control_|bank_af~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y13_N5 +dffeas \z80_|reg_control_|bank_af ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_control_|bank_af~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_control_|bank_af~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_control_|bank_af .is_wysiwyg = "true"; +defparam \z80_|reg_control_|bank_af .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N24 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_af~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_af~0_combout = (!\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (!\z80_|reg_control_|bank_af~q & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) + + .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datac(\z80_|reg_control_|bank_af~q ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_af~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_af~0 .lut_mask = 16'h0400; +defparam \z80_|reg_control_|reg_sel_af~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N10 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_af2~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_af2~0_combout = (!\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_control_|bank_af~q & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) + + .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datac(\z80_|reg_control_|bank_af~q ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_af2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_af2~0 .lut_mask = 16'h4000; +defparam \z80_|reg_control_|reg_sel_af2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N4 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_28 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_28~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout & (\z80_|reg_control_|reg_sel_af2~0_combout & !\z80_|execute_|ctl_reg_gp_we~8_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datab(gnd), + .datac(\z80_|reg_control_|reg_sel_af2~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_28 .lut_mask = 16'h00A0; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~17 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~17_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout & \z80_|reg_control_|reg_sel_af~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .datac(\z80_|reg_control_|reg_sel_af~0_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~17 .lut_mask = 16'hFFEA; +defparam \z80_|reg_file_|gdfx_temp1[0]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~19 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~19_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ) # ((\z80_|reg_file_|gdfx_temp1[0]~18_combout ) # (\z80_|reg_file_|gdfx_temp1[0]~17_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~18_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[0]~17_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~19 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp1[0]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N0 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_52 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_52~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout & (!\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|reg_control_|reg_sel_hl2~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_52 .lut_mask = 16'h0A00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N28 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_44 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_44~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout & \z80_|reg_control_|reg_sel_de2~4_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datad(\z80_|reg_control_|reg_sel_de2~4_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_44 .lut_mask = 16'h5000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N30 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_48 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_48~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout & \z80_|reg_control_|reg_sel_de~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datad(\z80_|reg_control_|reg_sel_de~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_48 .lut_mask = 16'h5000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N20 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_56 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_56~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout & \z80_|reg_control_|reg_sel_hl~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_56 .lut_mask = 16'h5000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~16 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~16_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~16 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp1[0]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~20 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~20_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout ) # ((\z80_|reg_file_|gdfx_temp1[0]~19_combout ) # ((\z80_|reg_file_|gdfx_temp1[0]~16_combout ) # (\z80_|execute_|ctl_sw_4u~6_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[0]~19_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~16_combout ), + .datad(\z80_|execute_|ctl_sw_4u~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~20 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp1[0]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N6 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout & \z80_|execute_|ctl_reg_gp_we~8_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 .lut_mask = 16'hF000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N4 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & (\z80_|decode_state_|DFFE_inst4~q & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), + .datab(\z80_|decode_state_|DFFE_inst4~q ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 .lut_mask = 16'h0080; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y16_N7 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N8 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_69 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_69~combout = (\z80_|reg_control_|reg_sel_iy~2_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout & \z80_|execute_|ctl_reg_gp_we~8_combout )) + + .dataa(gnd), + .datab(\z80_|reg_control_|reg_sel_iy~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y16_N25 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~34 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~34_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [2]), + .datad(\z80_|reg_file_|b2v_latch_iy_hi|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~34 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[2]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N2 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|execute_|ctl_reg_use_sp~6_combout & \z80_|execute_|ctl_reg_gp_sel[1]~31_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datac(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y15_N15 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N30 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_81 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_81~combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout & (\z80_|reg_control_|reg_sys_we_hi~combout & \z80_|execute_|ctl_reg_sel_wz~18_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), + .datac(\z80_|reg_control_|reg_sys_we_hi~combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~18_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_81 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_81 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y15_N9 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~36 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~36_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (\z80_|reg_file_|b2v_latch_wz_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [2]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [2]), + .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~36 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp1[2]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N18 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_29 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_29~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout & (\z80_|reg_control_|reg_sel_af2~0_combout & \z80_|execute_|ctl_reg_gp_we~8_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datab(gnd), + .datac(\z80_|reg_control_|reg_sel_af2~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_29 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y16_N25 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~35 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~35_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout & (\z80_|alu_|db[2]~16_combout & ((\z80_|reg_file_|b2v_latch_af2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # +// (!\z80_|execute_|ctl_reg_in_hi~12_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .datab(\z80_|alu_|db[2]~16_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~35 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[2]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N22 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout = (\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ))) + + .dataa(\z80_|reg_control_|bank_exx~q ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 .lut_mask = 16'h0200; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y16_N31 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N20 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout = (!\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ))) + + .dataa(\z80_|reg_control_|bank_exx~q ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 .lut_mask = 16'h0100; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y16_N13 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~33 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~33_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (\z80_|reg_file_|b2v_latch_bc2_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]), + .datad(\z80_|reg_file_|b2v_latch_bc_hi|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~33 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[2]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~37 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~37_combout = (\z80_|reg_file_|gdfx_temp1[2]~34_combout & (\z80_|reg_file_|gdfx_temp1[2]~36_combout & (\z80_|reg_file_|gdfx_temp1[2]~35_combout & \z80_|reg_file_|gdfx_temp1[2]~33_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[2]~34_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[2]~36_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[2]~35_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[2]~33_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~37 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[2]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N20 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_45 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_45~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout & \z80_|reg_control_|reg_sel_de2~4_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sel_de2~4_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_45 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y15_N31 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N12 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp1[2]~39_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N24 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_49 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_49~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout & \z80_|reg_control_|reg_sel_de~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datad(\z80_|reg_control_|reg_sel_de~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_49 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y15_N13 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~31 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~31_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [2]), + .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~31 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[2]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N2 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_33 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_33~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout & \z80_|reg_control_|reg_sel_af~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_33 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y15_N31 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N30 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[2]~12 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[2]~12_combout = (\z80_|execute_|ctl_reg_gp_we~8_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [2]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [2]), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[2]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[2]~12 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[2]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N26 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_57 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_57~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout & \z80_|reg_control_|reg_sel_hl~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_57 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y14_N21 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N2 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_53 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_53~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout & (\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|reg_control_|reg_sel_hl2~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_53 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y14_N7 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~32 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~32_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (\z80_|reg_file_|b2v_latch_hl_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_hl2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (((\z80_|reg_file_|b2v_latch_hl2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [2]), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~32 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[2]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~38 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~38_combout = (\z80_|reg_file_|gdfx_temp1[2]~37_combout & (\z80_|reg_file_|gdfx_temp1[2]~31_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[2]~12_combout & \z80_|reg_file_|gdfx_temp1[2]~32_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[2]~37_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[2]~31_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|db[2]~12_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[2]~32_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~38 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[2]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~11 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~11_combout = (((\z80_|execute_|ctl_inc_dec~9_combout ) # (!\z80_|execute_|ctl_inc_dec~5_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~42_combout )) # (!\z80_|execute_|ctl_inc_dec~6_combout ) + + .dataa(\z80_|execute_|ctl_inc_dec~6_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~42_combout ), + .datac(\z80_|execute_|ctl_inc_dec~5_combout ), + .datad(\z80_|execute_|ctl_inc_dec~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~11 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_inc_dec~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N8 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout = \z80_|address_latch_|Q [9] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ) + + .dataa(\z80_|address_latch_|Q [9]), + .datab(gnd), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out .lut_mask = 16'h5A5A; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y14_N31 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[1]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y17_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_sel_shift~5_combout = (\z80_|sequencer_|DFFE_T4_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|pla_decode_|Equal20~0_combout ) # (\z80_|execute_|ctl_ir_we~8_combout )))) + + .dataa(\z80_|pla_decode_|Equal20~0_combout ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|execute_|ctl_ir_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~5 .lut_mask = 16'h0C08; +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_sel_shift~3_combout = (\z80_|execute_|ctl_state_alu~4_combout ) # ((\z80_|decode_state_|DFFE_instCB~q & (\z80_|pla_decode_|Equal33~0_combout & \z80_|execute_|ctl_mWrite~5_combout ))) + + .dataa(\z80_|decode_state_|DFFE_instCB~q ), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~5_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~3 .lut_mask = 16'hFF80; +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_sel_shift~4_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ) # ((\z80_|execute_|ctl_ir_we~6_combout & (\z80_|execute_|ctl_ir_we~5_combout & \z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ))) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ), + .datab(\z80_|execute_|ctl_ir_we~6_combout ), + .datac(\z80_|execute_|ctl_ir_we~5_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~4 .lut_mask = 16'hEAAA; +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~4_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [0] & !\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) + + .dataa(\z80_|pla_decode_|Equal3~1_combout ), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~4 .lut_mask = 16'h0008; +defparam \z80_|execute_|ctl_flags_cf_cpl~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~5_combout = ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_state_alu~5_combout ) # (\z80_|execute_|ctl_alu_op_low~25_combout )))) # (!\z80_|execute_|ctl_state_alu~13_combout ) + + .dataa(\z80_|execute_|ctl_state_alu~5_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|execute_|ctl_alu_op_low~25_combout ), + .datad(\z80_|execute_|ctl_state_alu~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~5 .lut_mask = 16'h32FF; +defparam \z80_|execute_|ctl_flags_cf_cpl~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~16 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~16_combout = (\z80_|pla_decode_|Equal9~0_combout & (\z80_|pla_decode_|Equal63~0_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # (\z80_|nM1_int~2_combout )))) + + .dataa(\z80_|pla_decode_|Equal9~0_combout ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~16 .lut_mask = 16'h8880; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~6_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_flags_cf_cpl~4_combout ) # ((\z80_|execute_|ctl_flags_cf_cpl~5_combout )))) # (!\z80_|alu_flags_|DFFE_inst_latch_nf~q & +// (((\z80_|execute_|ctl_alu_sel_op2_neg~16_combout )))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .datab(\z80_|execute_|ctl_flags_cf_cpl~4_combout ), + .datac(\z80_|execute_|ctl_flags_cf_cpl~5_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~6 .lut_mask = 16'hFDA8; +defparam \z80_|execute_|ctl_flags_cf_cpl~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~7_combout = (\z80_|execute_|ctl_flags_cf_cpl~6_combout ) # ((\z80_|pla_decode_|Equal9~0_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal62~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~0_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|pla_decode_|Equal62~2_combout ), + .datad(\z80_|execute_|ctl_flags_cf_cpl~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~7 .lut_mask = 16'hFF20; +defparam \z80_|execute_|ctl_flags_cf_cpl~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y20_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~10_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ) # ((!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|execute_|ctl_alu_op_low~25_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|execute_|ctl_alu_op_low~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~10 .lut_mask = 16'hDCCC; +defparam \z80_|execute_|ctl_flags_cf_cpl~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y20_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~8_combout = (\z80_|execute_|ctl_flags_cf_cpl~10_combout ) # ((\z80_|execute_|ctl_alu_op_low~34_combout & (\z80_|execute_|ctl_alu_op_low~25_combout & \z80_|execute_|ctl_alu_op_low~22_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~34_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~25_combout ), + .datac(\z80_|execute_|ctl_flags_cf_cpl~10_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~8 .lut_mask = 16'hF8F0; +defparam \z80_|execute_|ctl_flags_cf_cpl~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ixy_d~7_combout & (!\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y20_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~42 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~42_combout = (\z80_|execute_|ctl_alu_op_low~34_combout ) # (!\z80_|execute_|ctl_alu_op_low~48_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op_low~48_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~42 .lut_mask = 16'hFF0F; +defparam \z80_|execute_|ctl_alu_op_low~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y20_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~9 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~9_combout = (\z80_|execute_|ctl_flags_cf_cpl~7_combout ) # ((\z80_|execute_|ctl_flags_cf_cpl~8_combout ) # ((\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout & \z80_|execute_|ctl_alu_op_low~42_combout ))) + + .dataa(\z80_|execute_|ctl_flags_cf_cpl~7_combout ), + .datab(\z80_|execute_|ctl_flags_cf_cpl~8_combout ), + .datac(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), + .datad(\z80_|execute_|ctl_alu_op_low~42_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~9 .lut_mask = 16'hFEEE; +defparam \z80_|execute_|ctl_flags_cf_cpl~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y17_N12 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout = (\z80_|execute_|ctl_alu_op_low~40_combout & (\z80_|pla_decode_|Equal21~1_combout & ((\z80_|execute_|ixy_d~6_combout ) # (\z80_|execute_|ctl_mRead~9_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~40_combout ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ctl_mRead~9_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 .lut_mask = 16'h8880; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y20_N24 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout = ((!\z80_|pla_decode_|Equal39~0_combout & ((!\z80_|pla_decode_|Equal40~2_combout ) # (!\z80_|ir_|opcode [5])))) # (!\z80_|execute_|ixy_d~6_combout ) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal40~2_combout ), + .datad(\z80_|pla_decode_|Equal39~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 .lut_mask = 16'h557F; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y20_N22 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout = (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout & ((\z80_|execute_|ctl_alu_op_low~37_combout ) # (\z80_|execute_|ctl_alu_op_low~38_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~37_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~38_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 .lut_mask = 16'h3232; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~18 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~18_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|pla_decode_|Equal11~0_combout & \z80_|sequencer_|DFFE_T3_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~18 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_mWrite~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N14 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1_combout = (!\z80_|execute_|ctl_mWrite~18_combout & (((!\z80_|execute_|ctl_mWrite~17_combout & !\z80_|pla_decode_|Equal61~2_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~17_combout ), + .datab(\z80_|pla_decode_|Equal61~2_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_mWrite~18_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1 .lut_mask = 16'h001F; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y20_N16 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2_combout = (\z80_|nM1_int~2_combout & (!\z80_|execute_|ctl_mRead~34_combout & ((!\z80_|pla_decode_|Equal56~0_combout ) # (!\z80_|execute_|ctl_state_alu~3_combout )))) # (!\z80_|nM1_int~2_combout & +// (((!\z80_|pla_decode_|Equal56~0_combout ) # (!\z80_|execute_|ctl_state_alu~3_combout )))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|execute_|ctl_state_alu~3_combout ), + .datad(\z80_|pla_decode_|Equal56~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2 .lut_mask = 16'h0777; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y20_N10 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3_combout = (\z80_|execute_|ctl_alu_core_R~4_combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~1_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_R~4_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~1_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~2_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3 .lut_mask = 16'h8000; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y20_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~2_combout = (\z80_|execute_|ctl_alu_op_low~37_combout & (((\z80_|execute_|ctl_mRead~34_combout & \z80_|execute_|ixy_d~6_combout )) # (!\z80_|execute_|ctl_alu_oe~4_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~37_combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ctl_alu_oe~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~2 .lut_mask = 16'h80AA; +defparam \z80_|execute_|ctl_flags_cf_cpl~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y20_N2 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~3_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~13_combout & (\z80_|execute_|ctl_alu_core_S~7_combout & !\z80_|execute_|ctl_alu_core_R~1_combout ))) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), + .datac(\z80_|execute_|ctl_alu_core_S~7_combout ), + .datad(\z80_|execute_|ctl_alu_core_R~1_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'h0080; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y20_N6 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~3_combout & (!\z80_|execute_|ctl_flags_cf_cpl~2_combout & (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0_combout ))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~3_combout ), + .datab(\z80_|execute_|ctl_flags_cf_cpl~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 .lut_mask = 16'h0200; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y20_N12 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout = (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout & (\z80_|execute_|ctl_flags_nf_we~1_combout & (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ), + .datab(\z80_|execute_|ctl_flags_nf_we~1_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 .lut_mask = 16'h0400; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_we~4_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & ((\z80_|pla_decode_|Equal11~0_combout ) # (\z80_|pla_decode_|Equal10~0_combout )))) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|pla_decode_|Equal10~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_we~4 .lut_mask = 16'h8880; +defparam \z80_|execute_|ctl_flags_cf2_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y18_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_we~2_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~38_combout ) # (!\z80_|execute_|ctl_alu_op1_sel_bus~8_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~38_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_we~2 .lut_mask = 16'hCFFF; +defparam \z80_|execute_|ctl_flags_cf2_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_we~3_combout = (\z80_|execute_|ctl_flags_cf2_we~4_combout ) # ((\z80_|execute_|ctl_flags_cf2_we~2_combout ) # ((\z80_|execute_|ixy_d~15_combout & \z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(\z80_|execute_|ctl_flags_cf2_we~4_combout ), + .datab(\z80_|execute_|ixy_d~15_combout ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|execute_|ctl_flags_cf2_we~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_we~3 .lut_mask = 16'hFFEA; +defparam \z80_|execute_|ctl_flags_cf2_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y15_N13 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N8 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_32 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_32~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout & \z80_|reg_control_|reg_sel_af~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_32~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_32 .lut_mask = 16'h4400; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y15_N21 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X35_Y15_N27 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~81 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~81_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (\z80_|reg_file_|b2v_latch_wz_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (((\z80_|reg_file_|b2v_latch_sp_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .datab(\z80_|reg_file_|b2v_latch_wz_hi|latch [6]), + .datac(\z80_|reg_file_|b2v_latch_sp_hi|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~81_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~81 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[6]~81 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N22 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~8 ( +// Equation(s): +// \z80_|alu_|db_high[2]~8_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[7]~12_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[5]~24_combout )) + + .dataa(gnd), + .datab(\z80_|alu_|db[5]~24_combout ), + .datac(\z80_|alu_|db[7]~12_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|alu_|db_high[2]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[2]~8 .lut_mask = 16'hF0CC; +defparam \z80_|alu_|db_high[2]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N28 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~9 ( +// Equation(s): +// \z80_|alu_|db_high[2]~9_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_high[2]~8_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[6]~22_combout ))) # +// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) + + .dataa(\z80_|alu_|db[6]~22_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datac(\z80_|alu_|db_high[2]~8_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[2]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[2]~9 .lut_mask = 16'hF3BB; +defparam \z80_|alu_|db_high[2]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N14 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~11 ( +// Equation(s): +// \z80_|alu_|db_high[2]~11_combout = (\z80_|bus_control_|db[4]~19_combout & (!\z80_|bus_control_|db[3]~21_combout & \z80_|bus_control_|db[5]~15_combout )) + + .dataa(gnd), + .datab(\z80_|bus_control_|db[4]~19_combout ), + .datac(\z80_|bus_control_|db[3]~21_combout ), + .datad(\z80_|bus_control_|db[5]~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[2]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[2]~11 .lut_mask = 16'h0C00; +defparam \z80_|alu_|db_high[2]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N18 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[2] ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_high|Q [2] = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & (\z80_|alu_|db_high[2]~13_combout & \z80_|execute_|ctl_alu_op1_sel_bus~15_combout )) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .datab(gnd), + .datac(\z80_|alu_|db_high[2]~13_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [2]), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[2] .lut_mask = 16'h5000; +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y17_N19 +dffeas \z80_|alu_|op1_high[2] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [2]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_high [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_high[2] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_high[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_lq ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_lq~combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ixy_d~7_combout ) # ((\z80_|execute_|ixy_d~6_combout & !\z80_|ir_|opcode [3])))) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_lq .lut_mask = 16'h88A8; +defparam \z80_|execute_|ctl_alu_op2_sel_lq .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N6 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & \z80_|alu_|db_low[2]~23_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datad(\z80_|alu_|db_low[2]~23_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2 .lut_mask = 16'hF000; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~5_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|execute_|ctl_alu_core_R~0_combout & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T3_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datad(\z80_|execute_|ctl_alu_core_R~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~5 .lut_mask = 16'hFEF0; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~6_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~5_combout ) # ((\z80_|execute_|ctl_alu_op_low~47_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~14_combout & \z80_|pla_decode_|Equal13~2_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~5_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~47_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~6 .lut_mask = 16'hFFEA; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~7_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~4_combout & (\z80_|execute_|ctl_reg_use_sp~0_combout & \z80_|execute_|nextM~11_combout )) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_use_sp~0_combout ), + .datad(\z80_|execute_|nextM~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~7 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~8_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ) # (((!\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ) # (!\z80_|execute_|ctl_alu_op1_sel_bus~14_combout )) # (!\z80_|execute_|ctl_alu_op2_sel_bus~10_combout )) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~8 .lut_mask = 16'hBFFF; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y19_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_zero ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_zero~combout = (((\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ) # (!\z80_|execute_|ctl_alu_shift_oe~38_combout )) # (!\z80_|execute_|ctl_reg_out_hi~4_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ), + .datab(\z80_|execute_|ctl_reg_out_hi~4_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~38_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_zero .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_alu_op2_sel_zero .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N10 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2_combout ) # ((\z80_|alu_|db_high[2]~13_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) + + .dataa(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2_combout ), + .datab(\z80_|alu_|db_high[2]~13_combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 .lut_mask = 16'h00EA; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N0 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|ena ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|ena~combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout ) # ((\z80_|execute_|ctl_alu_op2_sel_zero~combout ) # (\z80_|execute_|ctl_alu_op2_sel_bus~8_combout )) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|ena .lut_mask = 16'hFEFE; +defparam \z80_|alu_|b2v_op2_latch_mux_high|ena .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y18_N11 +dffeas \z80_|alu_|op2_high[2] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_high [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_high[2] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_high[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N28 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~10 ( +// Equation(s): +// \z80_|alu_|db_high[2]~10_combout = (\z80_|alu_|op1_high [2] & (((\z80_|alu_|op2_high [2]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|alu_|op1_high [2] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_high [2]) # +// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) + + .dataa(\z80_|alu_|op1_high [2]), + .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datac(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datad(\z80_|alu_|op2_high [2]), + .cin(gnd), + .combout(\z80_|alu_|db_high[2]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[2]~10 .lut_mask = 16'hBB0B; +defparam \z80_|alu_|db_high[2]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N16 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~12 ( +// Equation(s): +// \z80_|alu_|db_high[2]~12_combout = (\z80_|alu_|db_high[2]~9_combout & (\z80_|alu_|db_high[2]~10_combout & ((\z80_|alu_|db_high[2]~11_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~combout )))) + + .dataa(\z80_|alu_|db_high[2]~9_combout ), + .datab(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datac(\z80_|alu_|db_high[2]~11_combout ), + .datad(\z80_|alu_|db_high[2]~10_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[2]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[2]~12 .lut_mask = 16'hA200; +defparam \z80_|alu_|db_high[2]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N6 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~1 ( +// Equation(s): +// \z80_|alu_|db_high[3]~1_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout ) # (\z80_|alu_|db_high[3]~0_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datac(gnd), + .datad(\z80_|alu_|db_high[3]~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~1 .lut_mask = 16'hFFCC; +defparam \z80_|alu_|db_high[3]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N0 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~13 ( +// Equation(s): +// \z80_|alu_|db_high[2]~13_combout = ((\z80_|alu_|db_high[2]~12_combout & ((\z80_|execute_|ctl_alu_res_oe~3_combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout )))) # (!\z80_|alu_|db_high[3]~1_combout ) + + .dataa(\z80_|execute_|ctl_alu_res_oe~3_combout ), + .datab(\z80_|alu_|db_high[2]~12_combout ), + .datac(\z80_|alu_|db_high[3]~1_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[2]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[2]~13 .lut_mask = 16'hCF8F; +defparam \z80_|alu_|db_high[2]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y12_N29 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X31_Y12_N19 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~78 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~78_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (\z80_|reg_file_|b2v_latch_ix_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [6]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_iy_lo|latch [6]), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~78_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~78 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[6]~78 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N26 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout = (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & \z80_|execute_|ctl_reg_gp_sel[1]~31_combout ))) + + .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y12_N5 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~79 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~79_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [6] & ((\z80_|alu_control_|db[6]~22_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|alu_control_|db[6]~22_combout ) # ((!\z80_|execute_|ctl_reg_in_lo~8_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datab(\z80_|alu_control_|db[6]~22_combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [6]), + .datad(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~79_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~79 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[6]~79 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N10 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_34 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_34~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_af~0_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~35_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(gnd), + .datac(\z80_|reg_control_|reg_sel_af~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_34 .lut_mask = 16'h5000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N18 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder_combout = \z80_|reg_file_|gdfx_temp0[6]~82_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N0 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_35 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_35~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_af~0_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~35_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(gnd), + .datac(\z80_|reg_control_|reg_sel_af~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_35 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y13_N19 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N14 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_31 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_31~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout & \z80_|reg_control_|reg_sel_af2~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .datac(\z80_|reg_control_|reg_sel_af2~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_31 .lut_mask = 16'h8080; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y13_N21 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N28 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_30 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_30~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout & \z80_|reg_control_|reg_sel_af2~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .datac(\z80_|reg_control_|reg_sel_af2~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_30 .lut_mask = 16'h4040; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~75 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~75_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (\z80_|reg_file_|b2v_latch_af_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_af2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (((\z80_|reg_file_|b2v_latch_af2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datab(\z80_|reg_file_|b2v_latch_af_lo|latch [6]), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~75_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~75 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp0[6]~75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N20 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder_combout = \z80_|reg_file_|gdfx_temp0[6]~82_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y14_N21 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X32_Y14_N31 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~76 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~76_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [6]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [6]), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~76_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~76 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[6]~76 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y13_N21 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~77 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~77_combout = (\z80_|reg_file_|gdfx_temp0[6]~76_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[6]~76_combout ), + .datab(gnd), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~77_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~77 .lut_mask = 16'hA0AA; +defparam \z80_|reg_file_|gdfx_temp0[6]~77 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~80 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~80_combout = (\z80_|reg_file_|gdfx_temp0[6]~78_combout & (\z80_|reg_file_|gdfx_temp0[6]~79_combout & (\z80_|reg_file_|gdfx_temp0[6]~75_combout & \z80_|reg_file_|gdfx_temp0[6]~77_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[6]~78_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[6]~79_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[6]~75_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[6]~77_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~80 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[6]~80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y12_N1 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y12_N3 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~74 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~74_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (\z80_|reg_file_|b2v_latch_hl_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl_lo|latch [6]), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~74_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~74 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp0[6]~74 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y11_N13 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y11_N11 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~73 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~73_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [6] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [6] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [6]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~73_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~73 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp0[6]~73 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~81 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~81_combout = (\z80_|reg_file_|gdfx_temp0[6]~80_combout & (\z80_|reg_file_|gdfx_temp0[6]~74_combout & \z80_|reg_file_|gdfx_temp0[6]~73_combout )) + + .dataa(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[6]~74_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[6]~73_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~81_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~81 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|gdfx_temp0[6]~81 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~19 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~19_combout = (\z80_|execute_|ctl_sw_4u~6_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ) # (\z80_|execute_|ctl_reg_in_lo~8_combout ))) + + .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datad(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~19 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp0[0]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~18 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~18_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~18 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp0[0]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~20 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~20_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ) # ((\z80_|reg_file_|gdfx_temp0[0]~19_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ) # (\z80_|reg_file_|gdfx_temp0[0]~18_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~19_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~18_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~20 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp0[0]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~92 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~92_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout & (!\z80_|execute_|ctl_reg_gp_we~8_combout & ((\z80_|reg_control_|reg_sel_hl2~0_combout ) # (\z80_|reg_control_|reg_sel_hl~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .datab(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~92_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~92 .lut_mask = 16'h0A08; +defparam \z80_|reg_file_|gdfx_temp0[0]~92 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~21 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~21_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ) # ((\z80_|reg_file_|gdfx_temp0[0]~20_combout ) # (\z80_|reg_file_|gdfx_temp0[0]~92_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datac(\z80_|reg_file_|gdfx_temp0[0]~20_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~92_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~21 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp0[0]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N4 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_74 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_74~combout = (\z80_|reg_control_|reg_sel_pc~combout & (!\z80_|reg_control_|reg_sys_we_lo~combout & \z80_|execute_|ctl_reg_sys_hilo[0]~31_combout )) + + .dataa(\z80_|reg_control_|reg_sel_pc~combout ), + .datab(gnd), + .datac(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_74 .lut_mask = 16'h0A00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_74 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N6 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_62 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_62~combout = (\z80_|execute_|ctl_reg_sys_hilo[0]~31_combout & (!\z80_|reg_control_|reg_sys_we_lo~combout & \z80_|execute_|ctl_reg_sel_ir~1_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~31_combout ), + .datac(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datad(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_62 .lut_mask = 16'h0C00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N26 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~2 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[0]~2_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ) # ((\z80_|execute_|ctl_sw_4d~6_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~43_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .datab(\z80_|execute_|ctl_sw_4d~6_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[0]~2 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|db_lo_as[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y12_N13 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[4]~15_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X31_Y12_N9 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X32_Y12_N3 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~55 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~55_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_sp_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_iy_lo|latch [4]), + .datad(\z80_|reg_file_|b2v_latch_sp_lo|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~55_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~55 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[4]~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y12_N23 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~56 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~56_combout = (\z80_|reg_file_|gdfx_temp0[4]~55_combout & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|gdfx_temp0[4]~55_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~56_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~56 .lut_mask = 16'hC0CC; +defparam \z80_|reg_file_|gdfx_temp0[4]~56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y12_N13 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y12_N23 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~57 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~57_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [4] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [4] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [4]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~57_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~57 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp0[4]~57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y14_N5 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X32_Y14_N11 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~59 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~59_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [4]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [4]), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~59_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~59 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[4]~59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y13_N17 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X31_Y13_N31 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~58 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~58_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (\z80_|reg_file_|b2v_latch_af_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_af2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (((\z80_|reg_file_|b2v_latch_af2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datab(\z80_|reg_file_|b2v_latch_af_lo|latch [4]), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~58_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~58 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp0[4]~58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y13_N1 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~60 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~60_combout = (\z80_|reg_file_|gdfx_temp0[4]~59_combout & (\z80_|reg_file_|gdfx_temp0[4]~58_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp0[4]~59_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[4]~58_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~60_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~60 .lut_mask = 16'h8088; +defparam \z80_|reg_file_|gdfx_temp0[4]~60 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y11_N23 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X31_Y11_N17 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~53 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~53_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [4]), + .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~53_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~53 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[4]~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~54 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~54_combout = (\z80_|reg_file_|gdfx_temp0[4]~53_combout & ((\z80_|alu_control_|db[4]~32_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datab(gnd), + .datac(\z80_|alu_control_|db[4]~32_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[4]~53_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~54_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~54 .lut_mask = 16'hF500; +defparam \z80_|reg_file_|gdfx_temp0[4]~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~61 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~61_combout = (\z80_|reg_file_|gdfx_temp0[4]~56_combout & (\z80_|reg_file_|gdfx_temp0[4]~57_combout & (\z80_|reg_file_|gdfx_temp0[4]~60_combout & \z80_|reg_file_|gdfx_temp0[4]~54_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[4]~56_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[4]~57_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[4]~60_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[4]~54_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~61 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[4]~61 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~62 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~62_combout = ((\z80_|reg_file_|gdfx_temp0[4]~61_combout & ((\z80_|reg_file_|db_lo_as[4]~15_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .datac(\z80_|execute_|ctl_sw_4u~6_combout ), + .datad(\z80_|reg_file_|db_lo_as[4]~15_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~62 .lut_mask = 16'hBB3B; +defparam \z80_|reg_file_|gdfx_temp0[4]~62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N10 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_75 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_75~combout = (\z80_|reg_control_|reg_sel_pc~combout & (\z80_|reg_control_|reg_sys_we_lo~combout & \z80_|execute_|ctl_reg_sys_hilo[0]~31_combout )) + + .dataa(\z80_|reg_control_|reg_sel_pc~combout ), + .datab(gnd), + .datac(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_75 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y12_N3 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[4]~15_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N2 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~13 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[4]~13_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[4]~62_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # +// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[4]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[4]~13 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_lo_as[4]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N18 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~14 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[4]~14_combout = (\z80_|reg_file_|db_lo_as[4]~13_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_ir_lo|latch [4]), + .datab(\z80_|reg_file_|db_lo_as[4]~13_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[4]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[4]~14 .lut_mask = 16'h88CC; +defparam \z80_|reg_file_|db_lo_as[4]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N16 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout = \z80_|address_latch_|Q [4] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|address_latch_|Q [4]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out .lut_mask = 16'h0FF0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N12 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~15 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[4]~15_combout = ((\z80_|reg_file_|db_lo_as[4]~14_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .datab(\z80_|reg_file_|db_lo_as[4]~14_combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), + .datad(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[4]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[4]~15 .lut_mask = 16'hC4FF; +defparam \z80_|reg_file_|db_lo_as[4]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N12 +cycloneive_lcell_comb \z80_|address_latch_|abusz[4] ( +// Equation(s): +// \z80_|address_latch_|abusz [4] = (\z80_|reg_file_|db_lo_as[4]~15_combout & !\z80_|resets_|clrpc~0_combout ) + + .dataa(gnd), + .datab(\z80_|reg_file_|db_lo_as[4]~15_combout ), + .datac(gnd), + .datad(\z80_|resets_|clrpc~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [4]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[4] .lut_mask = 16'h00CC; +defparam \z80_|address_latch_|abusz[4] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y10_N13 +dffeas \z80_|address_latch_|Q[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [4]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[4] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N20 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout = \z80_|address_latch_|Q [5] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout & (\z80_|execute_|ctl_inc_dec~11_combout $ (\z80_|address_latch_|Q +// [4]))))) + + .dataa(\z80_|execute_|ctl_inc_dec~11_combout ), + .datab(\z80_|address_latch_|Q [4]), + .datac(\z80_|address_latch_|Q [5]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out .lut_mask = 16'h96F0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y12_N29 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[5]~18_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y12_N17 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y12_N15 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~64 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~64_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [5] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [5] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [5]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~64_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~64 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp0[5]~64 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y11_N27 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X31_Y11_N25 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~63 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~63_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [5]), + .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [5]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~63_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~63 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[5]~63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y11_N17 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N18 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[5]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_lo|latch[5]~feeder_combout = \z80_|reg_file_|gdfx_temp0[5]~72_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[5]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y11_N19 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_af_lo|latch[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~65 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~65_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [5]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [5]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~65_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~65 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[5]~65 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y12_N21 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X32_Y12_N23 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~69 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~69_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [5]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_iy_lo|latch [5]), + .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~69_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~69 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[5]~69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y13_N29 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X32_Y14_N27 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~68 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~68_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (\z80_|reg_file_|b2v_latch_ix_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_ix_lo|latch [5]), + .datac(\z80_|reg_file_|b2v_latch_bc_lo|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~68_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~68 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp0[5]~68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y13_N3 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X32_Y14_N17 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~66 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~66_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [5] & ((\z80_|alu_control_|db[5]~15_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|alu_control_|db[5]~15_combout ) # ((!\z80_|execute_|ctl_reg_in_lo~8_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datab(\z80_|alu_control_|db[5]~15_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [5]), + .datad(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~66_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~66 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[5]~66 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~67 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~67_combout = (\z80_|reg_file_|gdfx_temp0[5]~66_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [5]), + .datad(\z80_|reg_file_|gdfx_temp0[5]~66_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~67_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~67 .lut_mask = 16'hF300; +defparam \z80_|reg_file_|gdfx_temp0[5]~67 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~70 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~70_combout = (\z80_|reg_file_|gdfx_temp0[5]~65_combout & (\z80_|reg_file_|gdfx_temp0[5]~69_combout & (\z80_|reg_file_|gdfx_temp0[5]~68_combout & \z80_|reg_file_|gdfx_temp0[5]~67_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[5]~65_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[5]~69_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[5]~68_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[5]~67_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~70_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~70 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[5]~70 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~71 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~71_combout = (\z80_|reg_file_|gdfx_temp0[5]~64_combout & (\z80_|reg_file_|gdfx_temp0[5]~63_combout & \z80_|reg_file_|gdfx_temp0[5]~70_combout )) + + .dataa(\z80_|reg_file_|gdfx_temp0[5]~64_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[5]~63_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[5]~70_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~71 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|gdfx_temp0[5]~71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~72 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~72_combout = ((\z80_|reg_file_|gdfx_temp0[5]~71_combout & ((\z80_|reg_file_|db_lo_as[5]~18_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), + .datab(\z80_|reg_file_|db_lo_as[5]~18_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .datad(\z80_|execute_|ctl_sw_4u~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~72 .lut_mask = 16'h8FAF; +defparam \z80_|reg_file_|gdfx_temp0[5]~72 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y12_N7 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[5]~18_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N6 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~16 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[5]~16_combout = (\z80_|reg_file_|gdfx_temp0[5]~72_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # (!\z80_|reg_file_|gdfx_temp0[5]~72_combout & +// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .datab(\z80_|execute_|ctl_sw_4d~6_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[5]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[5]~16 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|db_lo_as[5]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N14 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~17 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[5]~17_combout = (\z80_|reg_file_|db_lo_as[5]~16_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|b2v_latch_ir_lo|latch [5]), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .datad(\z80_|reg_file_|db_lo_as[5]~16_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[5]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[5]~17 .lut_mask = 16'hCF00; +defparam \z80_|reg_file_|db_lo_as[5]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N28 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~18 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[5]~18_combout = ((\z80_|reg_file_|db_lo_as[5]~17_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), + .datac(\z80_|reg_file_|db_lo_as[5]~17_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[5]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[5]~18 .lut_mask = 16'hD5F5; +defparam \z80_|reg_file_|db_lo_as[5]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N8 +cycloneive_lcell_comb \z80_|address_latch_|abusz[5] ( +// Equation(s): +// \z80_|address_latch_|abusz [5] = (\z80_|reg_file_|db_lo_as[5]~18_combout & !\z80_|resets_|clrpc~0_combout ) + + .dataa(gnd), + .datab(\z80_|reg_file_|db_lo_as[5]~18_combout ), + .datac(gnd), + .datad(\z80_|resets_|clrpc~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [5]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[5] .lut_mask = 16'h00CC; +defparam \z80_|address_latch_|abusz[5] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y10_N9 +dffeas \z80_|address_latch_|Q[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [5]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[5] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~10 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~10_combout = (\z80_|execute_|ctl_inc_dec~9_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_inc_dec~6_combout ), + .datad(\z80_|execute_|ctl_inc_dec~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~10 .lut_mask = 16'hFF0F; +defparam \z80_|execute_|ctl_inc_dec~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N30 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout = \z80_|address_latch_|Q [5] $ ((((\z80_|execute_|ctl_inc_dec~10_combout ) # (!\z80_|execute_|ctl_inc_dec~5_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~42_combout ))) + + .dataa(\z80_|address_latch_|Q [5]), + .datab(\z80_|execute_|ctl_bus_inc_oe~42_combout ), + .datac(\z80_|execute_|ctl_inc_dec~10_combout ), + .datad(\z80_|execute_|ctl_inc_dec~5_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4 .lut_mask = 16'h5955; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N8 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout = \z80_|address_latch_|Q [4] $ ((((\z80_|execute_|ctl_inc_dec~10_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~42_combout )) # (!\z80_|execute_|ctl_inc_dec~5_combout ))) + + .dataa(\z80_|execute_|ctl_inc_dec~5_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~42_combout ), + .datac(\z80_|execute_|ctl_inc_dec~10_combout ), + .datad(\z80_|address_latch_|Q [4]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 .lut_mask = 16'h08F7; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N20 +cycloneive_lcell_comb \z80_|address_latch_|abusz[6] ( +// Equation(s): +// \z80_|address_latch_|abusz [6] = (\z80_|reg_file_|db_lo_as[6]~21_combout & !\z80_|resets_|clrpc~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|reg_file_|db_lo_as[6]~21_combout ), + .datad(\z80_|resets_|clrpc~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [6]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[6] .lut_mask = 16'h00F0; +defparam \z80_|address_latch_|abusz[6] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y10_N21 +dffeas \z80_|address_latch_|Q[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [6]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[6] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N20 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[6] ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|address [6] = \z80_|address_latch_|Q [6] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout & +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout )))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), + .datac(\z80_|address_latch_|Q [6]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[6] .lut_mask = 16'h78F0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[6] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y12_N25 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[6]~21_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X36_Y12_N11 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[6]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N10 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~19 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[6]~19_combout = (\z80_|reg_file_|gdfx_temp0[6]~82_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # (!\z80_|reg_file_|gdfx_temp0[6]~82_combout & +// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .datab(\z80_|execute_|ctl_sw_4d~6_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[6]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[6]~19 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|db_lo_as[6]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N22 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~20 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[6]~20_combout = (\z80_|reg_file_|db_lo_as[6]~19_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|b2v_latch_ir_lo|latch [6]), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .datad(\z80_|reg_file_|db_lo_as[6]~19_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[6]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[6]~20 .lut_mask = 16'hCF00; +defparam \z80_|reg_file_|db_lo_as[6]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N24 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~21 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[6]~21_combout = ((\z80_|reg_file_|db_lo_as[6]~20_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [6]) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), + .datac(\z80_|reg_file_|db_lo_as[6]~20_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[6]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[6]~21 .lut_mask = 16'hD5F5; +defparam \z80_|reg_file_|db_lo_as[6]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~82 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~82_combout = ((\z80_|reg_file_|gdfx_temp0[6]~81_combout & ((\z80_|reg_file_|db_lo_as[6]~21_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[6]~81_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .datad(\z80_|reg_file_|db_lo_as[6]~21_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~82 .lut_mask = 16'hCF4F; +defparam \z80_|reg_file_|gdfx_temp0[6]~82 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N10 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[6]~0 ( +// Equation(s): +// \z80_|reg_file_|db_lo_ds[6]~0_combout = (\z80_|reg_file_|gdfx_temp0[6]~82_combout ) # ((!\z80_|execute_|ctl_reg_out_lo~5_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout & \z80_|execute_|ctl_reg_out_lo~7_combout ))) + + .dataa(\z80_|execute_|ctl_reg_out_lo~5_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_ds[6]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_ds[6]~0 .lut_mask = 16'hFF40; +defparam \z80_|reg_file_|db_lo_ds[6]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N28 +cycloneive_lcell_comb \z80_|sw1_|db_down[6]~1 ( +// Equation(s): +// \z80_|sw1_|db_down[6]~1_combout = ((\z80_|bus_control_|db[6]~9_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ) + + .dataa(gnd), + .datab(\z80_|bus_control_|db[6]~9_combout ), + .datac(\z80_|execute_|ctl_sw_1d~7_combout ), + .datad(\z80_|execute_|ctl_sw_mask543_en~0_combout ), + .cin(gnd), + .combout(\z80_|sw1_|db_down[6]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sw1_|db_down[6]~1 .lut_mask = 16'h0FCF; +defparam \z80_|sw1_|db_down[6]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_66_oe ( +// Equation(s): +// \z80_|execute_|ctl_66_oe~combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & \z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(\z80_|pla_decode_|Equal47~0_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_66_oe~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_66_oe .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_66_oe .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N24 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[1] ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_high|Q [1] = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & \z80_|alu_|db_high[1]~19_combout )) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .datad(\z80_|alu_|db_high[1]~19_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [1]), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[1] .lut_mask = 16'h0A00; +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[1] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y17_N25 +dffeas \z80_|alu_|op1_high[1] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [1]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_high [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_high[1] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_high[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N8 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~4 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~4_combout = (\z80_|alu_|db_low[1]~12_combout & \z80_|execute_|ctl_alu_op2_sel_lq~combout ) + + .dataa(gnd), + .datab(\z80_|alu_|db_low[1]~12_combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~4 .lut_mask = 16'hC0C0; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N16 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~4_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~8_combout & \z80_|alu_|db_high[1]~19_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .datab(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~4_combout ), + .datac(\z80_|alu_|db_high[1]~19_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5 .lut_mask = 16'h00EC; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y18_N17 +dffeas \z80_|alu_|op2_high[1] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_high [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_high[1] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_high[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N18 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~2 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~2_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [1]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [1])))) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datab(\z80_|alu_|op1_high [1]), + .datac(\z80_|execute_|ctl_alu_op_low~combout ), + .datad(\z80_|alu_|op1_low [1]), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~2 .lut_mask = 16'hA808; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N14 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~3 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~3_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~2_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~8_combout & \z80_|alu_|db_low[1]~12_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datac(\z80_|alu_|db_low[1]~12_combout ), + .datad(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~3 .lut_mask = 16'h3320; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y18_N15 +dffeas \z80_|alu_|op2_low[1] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_low [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_low[1] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_low[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N16 +cycloneive_lcell_comb \z80_|alu_|alu_op2[1]~1 ( +// Equation(s): +// \z80_|alu_|alu_op2[1]~1_combout = \z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_high [1])) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_low [1]))))) + + .dataa(\z80_|alu_|op2_high [1]), + .datab(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), + .datad(\z80_|alu_|op2_low [1]), + .cin(gnd), + .combout(\z80_|alu_|alu_op2[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op2[1]~1 .lut_mask = 16'h4B78; +defparam \z80_|alu_|alu_op2[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N0 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout = (!\z80_|alu_|alu_op2[1]~1_combout & ((\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_low [1])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_high +// [1]))))) + + .dataa(\z80_|alu_|op1_low [1]), + .datab(\z80_|alu_|op1_high [1]), + .datac(\z80_|execute_|ctl_alu_op_low~combout ), + .datad(\z80_|alu_|alu_op2[1]~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'h0053; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N30 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout = (\z80_|alu_|alu_op2[1]~1_combout & ((\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [1])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [1]))))) + + .dataa(\z80_|alu_|op1_low [1]), + .datab(\z80_|alu_|op1_high [1]), + .datac(\z80_|execute_|ctl_alu_op_low~combout ), + .datad(\z80_|alu_|alu_op2[1]~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0 .lut_mask = 16'hAC00; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N14 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout = (\z80_|execute_|ctl_alu_core_S~combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_core_S~combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'hFFF0; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y20_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~5_combout = (\z80_|execute_|ctl_alu_core_S~8_combout & (\z80_|execute_|ctl_alu_core_R~4_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout & !\z80_|pla_decode_|Equal72~2_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_S~8_combout ), + .datab(\z80_|execute_|ctl_alu_core_R~4_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ), + .datad(\z80_|pla_decode_|Equal72~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~5 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_alu_core_R~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~2 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~2_combout = (\z80_|execute_|ctl_mWrite~4_combout & (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal8~0_combout ) # (\z80_|pla_decode_|Equal55~0_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~4_combout ), + .datab(\z80_|pla_decode_|Equal8~0_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~2 .lut_mask = 16'hA080; +defparam \z80_|execute_|ctl_alu_core_R~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y20_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~combout = (((\z80_|pla_decode_|Equal73~2_combout ) # (\z80_|execute_|ctl_alu_core_R~2_combout )) # (!\z80_|execute_|ctl_alu_core_S~9_combout )) # (!\z80_|execute_|ctl_alu_core_R~4_combout ) + + .dataa(\z80_|execute_|ctl_alu_core_R~4_combout ), + .datab(\z80_|execute_|ctl_alu_core_S~9_combout ), + .datac(\z80_|pla_decode_|Equal73~2_combout ), + .datad(\z80_|execute_|ctl_alu_core_R~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R .lut_mask = 16'hFFF7; +defparam \z80_|execute_|ctl_alu_core_R .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N8 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~20 ( +// Equation(s): +// \z80_|alu_|db_high[0]~20_combout = ((!\z80_|bus_control_|db[3]~21_combout & (\z80_|bus_control_|db[5]~15_combout & !\z80_|bus_control_|db[4]~19_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) + + .dataa(\z80_|bus_control_|db[3]~21_combout ), + .datab(\z80_|bus_control_|db[5]~15_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datad(\z80_|bus_control_|db[4]~19_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~20 .lut_mask = 16'h0F4F; +defparam \z80_|alu_|db_high[0]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N26 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[0] ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_high|Q [0] = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & \z80_|alu_|db_high[0]~25_combout )) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .datad(\z80_|alu_|db_high[0]~25_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [0]), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[0] .lut_mask = 16'h0A00; +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[0] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y17_N27 +dffeas \z80_|alu_|op1_high[0] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [0]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_high [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_high[0] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_high[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N30 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~21 ( +// Equation(s): +// \z80_|alu_|db_high[0]~21_combout = (\z80_|execute_|ctl_alu_op1_oe~1_combout & (\z80_|alu_|op1_high [0] & ((\z80_|alu_|op2_high [0]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout & (((\z80_|alu_|op2_high +// [0]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datab(\z80_|alu_|op1_high [0]), + .datac(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datad(\z80_|alu_|op2_high [0]), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~21 .lut_mask = 16'hDD0D; +defparam \z80_|alu_|db_high[0]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N2 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~22 ( +// Equation(s): +// \z80_|alu_|db_high[0]~22_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[5]~24_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[3]~20_combout )) + + .dataa(gnd), + .datab(\z80_|alu_|db[3]~20_combout ), + .datac(\z80_|alu_|db[5]~24_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~22 .lut_mask = 16'hF0CC; +defparam \z80_|alu_|db_high[0]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N20 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~23 ( +// Equation(s): +// \z80_|alu_|db_high[0]~23_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_high[0]~22_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[4]~18_combout )) + + .dataa(\z80_|alu_|db[4]~18_combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .datac(gnd), + .datad(\z80_|alu_|db_high[0]~22_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~23 .lut_mask = 16'hEE22; +defparam \z80_|alu_|db_high[0]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N26 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~24 ( +// Equation(s): +// \z80_|alu_|db_high[0]~24_combout = (\z80_|alu_|db_high[0]~20_combout & (\z80_|alu_|db_high[0]~21_combout & ((\z80_|alu_|db_high[0]~23_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) + + .dataa(\z80_|alu_|db_high[0]~20_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datac(\z80_|alu_|db_high[0]~21_combout ), + .datad(\z80_|alu_|db_high[0]~23_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~24 .lut_mask = 16'hA020; +defparam \z80_|alu_|db_high[0]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N4 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~4 ( +// Equation(s): +// \z80_|alu_|db_low[0]~4_combout = ((!\z80_|bus_control_|db[3]~21_combout & (!\z80_|bus_control_|db[5]~15_combout & !\z80_|bus_control_|db[4]~19_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) + + .dataa(\z80_|bus_control_|db[3]~21_combout ), + .datab(\z80_|bus_control_|db[5]~15_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datad(\z80_|bus_control_|db[4]~19_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~4 .lut_mask = 16'h0F1F; +defparam \z80_|alu_|db_low[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y18_N27 +dffeas \z80_|alu_|result_lo[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_alu_op_low~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|result_lo [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|result_lo[0] .is_wysiwyg = "true"; +defparam \z80_|alu_|result_lo[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N20 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~2 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~2_combout = (\z80_|alu_|db_low[0]~24_combout & ((\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ) # ((\z80_|alu_|db_high[0]~25_combout & \z80_|execute_|ctl_alu_op1_sel_low~combout )))) # +// (!\z80_|alu_|db_low[0]~24_combout & (\z80_|alu_|db_high[0]~25_combout & ((\z80_|execute_|ctl_alu_op1_sel_low~combout )))) + + .dataa(\z80_|alu_|db_low[0]~24_combout ), + .datab(\z80_|alu_|db_high[0]~25_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~2 .lut_mask = 16'hECA0; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N0 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~3 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~3_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .datad(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~3 .lut_mask = 16'h0F00; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y17_N1 +dffeas \z80_|alu_|op1_low[0] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_low [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_low[0] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_low[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N24 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~5 ( +// Equation(s): +// \z80_|alu_|db_low[0]~5_combout = (\z80_|execute_|ctl_alu_op1_oe~1_combout & (\z80_|alu_|op1_low [0] & ((\z80_|alu_|op2_low [0]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout & (((\z80_|alu_|op2_low [0]) # +// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datab(\z80_|alu_|op1_low [0]), + .datac(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datad(\z80_|alu_|op2_low [0]), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~5 .lut_mask = 16'hDD0D; +defparam \z80_|alu_|db_low[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N26 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~6 ( +// Equation(s): +// \z80_|alu_|db_low[0]~6_combout = (\z80_|alu_|db_low[0]~4_combout & (\z80_|alu_|db_low[0]~5_combout & ((\z80_|execute_|ctl_alu_res_oe~3_combout ) # (\z80_|alu_|result_lo [0])))) + + .dataa(\z80_|execute_|ctl_alu_res_oe~3_combout ), + .datab(\z80_|alu_|db_low[0]~4_combout ), + .datac(\z80_|alu_|result_lo [0]), + .datad(\z80_|alu_|db_low[0]~5_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~6 .lut_mask = 16'hC800; +defparam \z80_|alu_|db_low[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N30 +cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~1 ( +// Equation(s): +// \z80_|alu_control_|b2v_inst_shift_mux|out~1_combout = (\z80_|ir_|opcode [5] & (\z80_|alu_|db[7]~12_combout & (\z80_|ir_|opcode [3]))) # (!\z80_|ir_|opcode [5] & ((\z80_|ir_|opcode [3] & ((\z80_|alu_|db[0]~14_combout ))) # (!\z80_|ir_|opcode [3] & +// (\z80_|alu_|db[7]~12_combout )))) + + .dataa(\z80_|alu_|db[7]~12_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|alu_|db[0]~14_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~1 .lut_mask = 16'hB282; +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_we~2_combout = (\z80_|execute_|ctl_flags_hf_we~5_combout & (\z80_|execute_|ctl_flags_xy_we~13_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_state_alu~6_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~6_combout ), + .datab(\z80_|execute_|ctl_flags_hf_we~5_combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~13_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_we~2 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_flags_hf_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~3_combout = (\z80_|execute_|ctl_flags_hf2_we~combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((!\z80_|execute_|ctl_flags_bus~1_combout ) # (!\z80_|execute_|ctl_flags_bus~0_combout )))) + + .dataa(\z80_|execute_|ctl_flags_bus~0_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_flags_hf2_we~combout ), + .datad(\z80_|execute_|ctl_flags_bus~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~3 .lut_mask = 16'hF4FC; +defparam \z80_|execute_|ctl_flags_cf_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~4_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # ((\z80_|execute_|ixy_d~6_combout & \z80_|execute_|ctl_mRead~34_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~4 .lut_mask = 16'hFFEA; +defparam \z80_|execute_|ctl_flags_cf_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~5_combout = ((\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # (\z80_|execute_|ctl_flags_cf_we~4_combout ))) # (!\z80_|execute_|ctl_flags_cf_we~7_combout ) + + .dataa(\z80_|execute_|ctl_flags_cf_we~7_combout ), + .datab(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .datad(\z80_|execute_|ctl_flags_cf_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~5 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_flags_cf_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~6_combout = (((\z80_|execute_|ctl_flags_cf_we~3_combout ) # (\z80_|execute_|ctl_flags_cf_we~5_combout )) # (!\z80_|execute_|ctl_flags_hf_we~2_combout )) # (!\z80_|execute_|ctl_flags_cf_we~2_combout ) + + .dataa(\z80_|execute_|ctl_flags_cf_we~2_combout ), + .datab(\z80_|execute_|ctl_flags_hf_we~2_combout ), + .datac(\z80_|execute_|ctl_flags_cf_we~3_combout ), + .datad(\z80_|execute_|ctl_flags_cf_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~6 .lut_mask = 16'hFFF7; +defparam \z80_|execute_|ctl_flags_cf_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N16 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~0 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf~0_combout = (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & (\z80_|execute_|ctl_flags_bus~combout & ((\z80_|alu_control_|db[0]~12_combout )))) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout +// & ((\z80_|execute_|ctl_flags_alu~15_combout ) # ((\z80_|execute_|ctl_flags_bus~combout & \z80_|alu_control_|db[0]~12_combout )))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), + .datab(\z80_|execute_|ctl_flags_bus~combout ), + .datac(\z80_|execute_|ctl_flags_alu~15_combout ), + .datad(\z80_|alu_control_|db[0]~12_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~0 .lut_mask = 16'hDC50; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N18 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~1 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf~1_combout = (\z80_|execute_|ctl_flags_cf_we~6_combout & ((\z80_|execute_|ctl_flags_cf2_we~3_combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf~q ))) # (!\z80_|execute_|ctl_flags_cf2_we~3_combout & +// (\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout )))) # (!\z80_|execute_|ctl_flags_cf_we~6_combout & (((\z80_|alu_flags_|DFFE_inst_latch_cf~q )))) + + .dataa(\z80_|execute_|ctl_flags_cf_we~6_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), + .datad(\z80_|execute_|ctl_flags_cf2_we~3_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~1 .lut_mask = 16'hF0D8; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y18_N19 +dffeas \z80_|alu_flags_|DFFE_inst_latch_cf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N4 +cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~0 ( +// Equation(s): +// \z80_|alu_control_|b2v_inst_shift_mux|out~0_combout = (\z80_|ir_|opcode [4] & ((\z80_|ir_|opcode [5] & ((!\z80_|ir_|opcode [3]))) # (!\z80_|ir_|opcode [5] & (\z80_|alu_flags_|DFFE_inst_latch_cf~q )))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~0 .lut_mask = 16'h20A8; +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N8 +cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~2 ( +// Equation(s): +// \z80_|alu_control_|b2v_inst_shift_mux|out~2_combout = (\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ) # ((\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout & !\z80_|ir_|opcode [4])) + + .dataa(\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ), + .datab(\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ), + .datac(\z80_|ir_|opcode [4]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~2 .lut_mask = 16'hCECE; +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N14 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~2 ( +// Equation(s): +// \z80_|alu_|db_low[0]~2_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[1]~10_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ))) + + .dataa(\z80_|alu_|db[1]~10_combout ), + .datab(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), + .datac(gnd), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~2 .lut_mask = 16'hAACC; +defparam \z80_|alu_|db_low[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N20 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~3 ( +// Equation(s): +// \z80_|alu_|db_low[0]~3_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_low[0]~2_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[0]~14_combout )))) # +// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .datac(\z80_|alu_|db_low[0]~2_combout ), + .datad(\z80_|alu_|db[0]~14_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~3 .lut_mask = 16'hF7D5; +defparam \z80_|alu_|db_low[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N16 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~24 ( +// Equation(s): +// \z80_|alu_|db_low[0]~24_combout = (\z80_|alu_|db_low[0]~6_combout & ((\z80_|alu_|db_low[0]~3_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~43_combout & !\z80_|alu_|db_high[3]~0_combout )))) # (!\z80_|alu_|db_low[0]~6_combout & +// (((!\z80_|execute_|ctl_alu_shift_oe~43_combout & !\z80_|alu_|db_high[3]~0_combout )))) + + .dataa(\z80_|alu_|db_low[0]~6_combout ), + .datab(\z80_|alu_|db_low[0]~3_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datad(\z80_|alu_|db_high[3]~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~24 .lut_mask = 16'h888F; +defparam \z80_|alu_|db_low[0]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N2 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~0 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~0_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [0]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [0])))) + + .dataa(\z80_|execute_|ctl_alu_op_low~combout ), + .datab(\z80_|alu_|op1_high [0]), + .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datad(\z80_|alu_|op1_low [0]), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~0 .lut_mask = 16'hE040; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N4 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~1 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~1_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~0_combout ) # ((\z80_|alu_|db_low[0]~24_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) + + .dataa(\z80_|alu_|db_low[0]~24_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .datad(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~1 .lut_mask = 16'h3320; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y18_N5 +dffeas \z80_|alu_|op2_low[0] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_low [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_low[0] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_low[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N6 +cycloneive_lcell_comb \z80_|alu_|alu_op2[0]~3 ( +// Equation(s): +// \z80_|alu_|alu_op2[0]~3_combout = \z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_high [0])) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_low [0]))))) + + .dataa(\z80_|alu_|op2_high [0]), + .datab(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), + .datad(\z80_|alu_|op2_low [0]), + .cin(gnd), + .combout(\z80_|alu_|alu_op2[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op2[0]~3 .lut_mask = 16'h4B78; +defparam \z80_|alu_|alu_op2[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N0 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout = ((!\z80_|execute_|ctl_alu_core_S~combout & !\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout )) # (!\z80_|execute_|ctl_alu_core_R~5_combout ) + + .dataa(\z80_|execute_|ctl_alu_core_S~combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_core_R~5_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 .lut_mask = 16'h0F5F; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla26M3T5_8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla26M3T5_8~combout = (\z80_|sequencer_|DFFE_T5_ff~q & (\z80_|pla_decode_|Equal21~1_combout & \z80_|sequencer_|DFFE_M3_ff~q )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T5_ff~q ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla26M3T5_8~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla26M3T5_8 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla26M3T5_8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~14 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~14_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla26M3T5_8~combout ) # ((\z80_|sequencer_|DFFE_T3_ff~q & (!\z80_|sequencer_|DFFE_T2_ff~q & \z80_|execute_|ixy_d~15_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla26M3T5_8~combout ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|execute_|ixy_d~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~14 .lut_mask = 16'hCECC; +defparam \z80_|execute_|ctl_alu_core_hf~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~16 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~16_combout = ((\z80_|execute_|ctl_alu_core_hf~14_combout ) # (!\z80_|execute_|ctl_alu_core_hf~15_combout )) # (!\z80_|execute_|ctl_alu_core_hf~12_combout ) + + .dataa(\z80_|execute_|ctl_alu_core_hf~12_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_core_hf~15_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~16 .lut_mask = 16'hFF5F; +defparam \z80_|execute_|ctl_alu_core_hf~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~13 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~13_combout = (\z80_|pla_decode_|Equal21~1_combout & ((\z80_|execute_|ctl_mRead~9_combout ) # ((!\z80_|execute_|ixy_d~5_combout & \z80_|execute_|ixy_d~6_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ctl_mRead~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~13 .lut_mask = 16'hCC40; +defparam \z80_|execute_|ctl_alu_core_hf~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~17 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~17_combout = (\z80_|execute_|ctl_alu_core_hf~16_combout & (((\z80_|execute_|ctl_alu_core_hf~13_combout & !\z80_|execute_|ctl_alu_op_low~40_combout )) # (!\z80_|execute_|ctl_alu_op_low~41_combout ))) # +// (!\z80_|execute_|ctl_alu_core_hf~16_combout & (\z80_|execute_|ctl_alu_core_hf~13_combout & ((!\z80_|execute_|ctl_alu_op_low~40_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~16_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~13_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~41_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~40_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~17 .lut_mask = 16'h0ACE; +defparam \z80_|execute_|ctl_alu_core_hf~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y20_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~44 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~44_combout = (\z80_|execute_|ctl_alu_op_low~38_combout ) # ((\z80_|execute_|ctl_alu_op_low~42_combout ) # ((\z80_|execute_|ctl_alu_op_low~36_combout ) # (!\z80_|execute_|ctl_alu_op_low~31_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~38_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~42_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~31_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~36_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~44 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|ctl_alu_op_low~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~20 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~20_combout = (\z80_|execute_|ctl_mRead~34_combout & ((\z80_|execute_|ctl_mRead~9_combout ) # ((!\z80_|execute_|ixy_d~5_combout & \z80_|execute_|ixy_d~6_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ctl_mRead~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~20 .lut_mask = 16'hCC40; +defparam \z80_|execute_|ctl_alu_core_hf~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y17_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~21 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~21_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ) # ((\z80_|execute_|ctl_alu_core_hf~20_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|execute_|ctl_mRead~34_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~21 .lut_mask = 16'hBFAA; +defparam \z80_|execute_|ctl_alu_core_hf~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~18 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~18_combout = (\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (((!\z80_|pla_decode_|Equal32~0_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal63~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal63~0_combout ), + .datab(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|pla_decode_|Equal32~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~18 .lut_mask = 16'h4CCC; +defparam \z80_|execute_|ctl_alu_core_hf~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~19 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~19_combout = (\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # ((\z80_|execute_|ctl_alu_core_hf~18_combout & !\z80_|execute_|ctl_flags_cf2_sel_daa~combout ))) + + .dataa(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~18_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~19 .lut_mask = 16'hEEFE; +defparam \z80_|execute_|ctl_alu_core_hf~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y20_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~22 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~22_combout = (\z80_|execute_|ctl_alu_op_low~37_combout & (!\z80_|execute_|ctl_alu_op_low~42_combout & ((\z80_|execute_|ctl_alu_core_hf~19_combout )))) # (!\z80_|execute_|ctl_alu_op_low~37_combout & +// ((\z80_|execute_|ctl_alu_core_hf~21_combout ) # ((!\z80_|execute_|ctl_alu_op_low~42_combout & \z80_|execute_|ctl_alu_core_hf~19_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~37_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~42_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~21_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~22 .lut_mask = 16'h7350; +defparam \z80_|execute_|ctl_alu_core_hf~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~43 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~43_combout = ((\z80_|execute_|ctl_alu_op_low~28_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ) # (!\z80_|execute_|ctl_state_alu~12_combout ))) # (!\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~28_combout ), + .datac(\z80_|execute_|ctl_state_alu~12_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~43 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|ctl_alu_op_low~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y20_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~24 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~24_combout = (\z80_|execute_|ctl_state_alu~2_combout & (\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|execute_|ctl_state_alu~2_combout & (\z80_|execute_|ixy_d~7_combout & ((\z80_|pla_decode_|Equal11~0_combout ) # +// (\z80_|pla_decode_|Equal10~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|execute_|ctl_state_alu~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~24 .lut_mask = 16'hAAC8; +defparam \z80_|execute_|ctl_alu_core_hf~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y20_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~25 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~25_combout = (!\z80_|execute_|ctl_alu_op_low~28_combout & (!\z80_|execute_|ctl_mWrite~18_combout & ((\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # (\z80_|execute_|ctl_alu_core_hf~24_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~28_combout ), + .datab(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .datac(\z80_|execute_|ctl_mWrite~18_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~25 .lut_mask = 16'h0504; +defparam \z80_|execute_|ctl_alu_core_hf~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~35 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~35_combout = (\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|execute_|ctl_alu_op_low~25_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|execute_|ctl_alu_op_low~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~35 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_core_hf~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y20_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~23 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~23_combout = (!\z80_|execute_|ctl_alu_op_low~34_combout & ((\z80_|execute_|ctl_alu_core_hf~35_combout ) # ((\z80_|execute_|ixy_d~7_combout & \z80_|execute_|ctl_alu_op_low~24_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~34_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~35_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~23 .lut_mask = 16'h5450; +defparam \z80_|execute_|ctl_alu_core_hf~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~26 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~26_combout = (!\z80_|execute_|ctl_alu_shift_oe~15_combout & (((\z80_|decode_state_|use_ixiy~combout ) # (!\z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|pla_decode_|Equal45~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal45~0_combout ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~26 .lut_mask = 16'h00DF; +defparam \z80_|execute_|ctl_alu_core_hf~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~34 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~34_combout = (\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|execute_|ctl_mRead~4_combout & ((\z80_|execute_|ctl_state_alu~4_combout )))) # (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M2_ff~q ) # +// ((\z80_|execute_|ctl_mRead~4_combout & \z80_|execute_|ctl_state_alu~4_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|execute_|ctl_mRead~4_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~34 .lut_mask = 16'hDC50; +defparam \z80_|execute_|ctl_alu_core_hf~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~27 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~27_combout = (\z80_|execute_|ctl_alu_op_low~22_combout & (((\z80_|execute_|ctl_alu_op_low~24_combout )))) # (!\z80_|execute_|ctl_alu_op_low~22_combout & (\z80_|execute_|ixy_d~7_combout & +// (!\z80_|execute_|ctl_mWrite~5_combout ))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ctl_mWrite~5_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~24_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~27 .lut_mask = 16'hF022; +defparam \z80_|execute_|ctl_alu_core_hf~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~28 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~28_combout = (!\z80_|execute_|ctl_alu_core_hf~34_combout & ((\z80_|pla_decode_|Equal56~0_combout & ((\z80_|execute_|ctl_alu_core_hf~27_combout ) # (\z80_|execute_|ctl_alu_op_low~22_combout ))) # +// (!\z80_|pla_decode_|Equal56~0_combout & (\z80_|execute_|ctl_alu_core_hf~27_combout & \z80_|execute_|ctl_alu_op_low~22_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~34_combout ), + .datab(\z80_|pla_decode_|Equal56~0_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~27_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~28 .lut_mask = 16'h5440; +defparam \z80_|execute_|ctl_alu_core_hf~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~29 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~29_combout = (\z80_|execute_|ctl_mRead~4_combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # ((!\z80_|execute_|ctl_state_alu~4_combout & \z80_|execute_|ctl_mWrite~9_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|ctl_mWrite~9_combout ), + .datac(\z80_|execute_|ctl_mRead~4_combout ), + .datad(\z80_|execute_|ctl_mWrite~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~29 .lut_mask = 16'hF040; +defparam \z80_|execute_|ctl_alu_core_hf~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~30 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~30_combout = (\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # ((\z80_|execute_|ctl_alu_core_hf~26_combout & ((\z80_|execute_|ctl_alu_core_hf~28_combout ) # (\z80_|execute_|ctl_alu_core_hf~29_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~26_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~28_combout ), + .datac(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~29_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~30 .lut_mask = 16'hFAF8; +defparam \z80_|execute_|ctl_alu_core_hf~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y20_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~31 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~31_combout = (\z80_|execute_|ctl_alu_core_hf~25_combout ) # ((\z80_|execute_|ctl_alu_core_hf~23_combout ) # ((!\z80_|execute_|ctl_alu_op_low~43_combout & \z80_|execute_|ctl_alu_core_hf~30_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~43_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~25_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~23_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~30_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~31 .lut_mask = 16'hFDFC; +defparam \z80_|execute_|ctl_alu_core_hf~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~36 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~36_combout = (\z80_|execute_|ixy_d~6_combout ) # ((\z80_|execute_|ixy_d~8_combout & !\z80_|execute_|ixy_d~9_combout )) + + .dataa(\z80_|execute_|ixy_d~8_combout ), + .datab(gnd), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ixy_d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~36 .lut_mask = 16'hF0FA; +defparam \z80_|execute_|ctl_alu_core_hf~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~37 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~37_combout = (\z80_|execute_|ctl_alu_core_hf~36_combout & ((\z80_|pla_decode_|Equal39~0_combout ) # ((!\z80_|execute_|ixy_d~5_combout & \z80_|pla_decode_|Equal40~1_combout )))) + + .dataa(\z80_|pla_decode_|Equal39~0_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~36_combout ), + .datad(\z80_|pla_decode_|Equal40~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~37 .lut_mask = 16'hB0A0; +defparam \z80_|execute_|ctl_alu_core_hf~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y20_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~32 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~32_combout = (\z80_|execute_|ctl_alu_core_hf~22_combout ) # ((\z80_|execute_|ctl_alu_core_hf~31_combout ) # ((!\z80_|execute_|ctl_alu_op_low~44_combout & \z80_|execute_|ctl_alu_core_hf~37_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~44_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~22_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~31_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~37_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~32 .lut_mask = 16'hFDFC; +defparam \z80_|execute_|ctl_alu_core_hf~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~33 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~33_combout = (\z80_|execute_|ctl_alu_core_hf~17_combout ) # ((\z80_|execute_|ctl_alu_core_hf~32_combout ) # ((!\z80_|execute_|ctl_alu_op_low~combout & \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~17_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~32_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~33 .lut_mask = 16'hFFF4; +defparam \z80_|execute_|ctl_alu_core_hf~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y14_N22 +cycloneive_lcell_comb \z80_|alu_control_|alu_core_cf_in~0 ( +// Equation(s): +// \z80_|alu_control_|alu_core_cf_in~0_combout = (\z80_|execute_|ctl_alu_core_hf~33_combout & (\z80_|alu_flags_|flags_hf~combout )) # (!\z80_|execute_|ctl_alu_core_hf~33_combout & ((\z80_|alu_flags_|flags_cf~combout ))) + + .dataa(\z80_|alu_flags_|flags_hf~combout ), + .datab(\z80_|alu_flags_|flags_cf~combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~33_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_control_|alu_core_cf_in~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|alu_core_cf_in~0 .lut_mask = 16'hACAC; +defparam \z80_|alu_control_|alu_core_cf_in~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N12 +cycloneive_lcell_comb \z80_|alu_|alu_op1[0]~0 ( +// Equation(s): +// \z80_|alu_|alu_op1[0]~0_combout = (\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [0]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [0])) + + .dataa(\z80_|execute_|ctl_alu_op_low~combout ), + .datab(\z80_|alu_|op1_high [0]), + .datac(gnd), + .datad(\z80_|alu_|op1_low [0]), + .cin(gnd), + .combout(\z80_|alu_|alu_op1[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op1[0]~0 .lut_mask = 16'hEE44; +defparam \z80_|alu_|alu_op1[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N8 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout = (\z80_|alu_|alu_op2[0]~3_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ) # ((\z80_|alu_control_|alu_core_cf_in~0_combout & \z80_|alu_|alu_op1[0]~0_combout )))) +// # (!\z80_|alu_|alu_op2[0]~3_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_control_|alu_core_cf_in~0_combout ) # (\z80_|alu_|alu_op1[0]~0_combout )))) + + .dataa(\z80_|alu_|alu_op2[0]~3_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ), + .datac(\z80_|alu_control_|alu_core_cf_in~0_combout ), + .datad(\z80_|alu_|alu_op1[0]~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 .lut_mask = 16'hECC8; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N30 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~25 ( +// Equation(s): +// \z80_|alu_|db_high[0]~25_combout = ((\z80_|alu_|db_high[0]~24_combout & ((\z80_|execute_|ctl_alu_res_oe~3_combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout )))) # (!\z80_|alu_|db_high[3]~1_combout ) + + .dataa(\z80_|alu_|db_high[0]~24_combout ), + .datab(\z80_|alu_|db_high[3]~1_combout ), + .datac(\z80_|execute_|ctl_alu_res_oe~3_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~25 .lut_mask = 16'hBBB3; +defparam \z80_|alu_|db_high[0]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N26 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~6 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~6_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|alu_|db_low[0]~24_combout ) # ((\z80_|alu_|db_high[0]~25_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) # +// (!\z80_|execute_|ctl_alu_op2_sel_lq~combout & (\z80_|alu_|db_high[0]~25_combout & (\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datab(\z80_|alu_|db_high[0]~25_combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .datad(\z80_|alu_|db_low[0]~24_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~6 .lut_mask = 16'hEAC0; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N2 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~6_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datac(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~6_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7 .lut_mask = 16'h3030; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y18_N3 +dffeas \z80_|alu_|op2_high[0] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_high [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_high[0] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_high[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N18 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout = (\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_high [0])) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_low [0]))) + + .dataa(\z80_|alu_|op2_high [0]), + .datab(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .datac(gnd), + .datad(\z80_|alu_|op2_low [0]), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'hBB88; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N16 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout = (\z80_|alu_control_|alu_core_cf_in~0_combout & ((\z80_|alu_|alu_op1[0]~0_combout ) # (\z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout )))) # (!\z80_|alu_control_|alu_core_cf_in~0_combout & (\z80_|alu_|alu_op1[0]~0_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ), + .datac(\z80_|alu_control_|alu_core_cf_in~0_combout ), + .datad(\z80_|alu_|alu_op1[0]~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hF660; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N10 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|execute_|ctl_alu_core_S~combout & !\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_core_R~combout ), + .datac(\z80_|execute_|ctl_alu_core_S~combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 .lut_mask = 16'hCCCF; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N22 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ) # +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout )))) # (!\z80_|execute_|ctl_alu_core_R~5_combout ) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), + .datac(\z80_|execute_|ctl_alu_core_R~5_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 .lut_mask = 16'h3F2F; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N28 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout = (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout & (((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout )) # +// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ))) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout & (((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout & +// !\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout )))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 .lut_mask = 16'h50FC; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N6 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~14 ( +// Equation(s): +// \z80_|alu_|db_high[1]~14_combout = ((\z80_|bus_control_|db[3]~21_combout & (\z80_|bus_control_|db[5]~15_combout & !\z80_|bus_control_|db[4]~19_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) + + .dataa(\z80_|bus_control_|db[3]~21_combout ), + .datab(\z80_|bus_control_|db[5]~15_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datad(\z80_|bus_control_|db[4]~19_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~14 .lut_mask = 16'h0F8F; +defparam \z80_|alu_|db_high[1]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N18 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~15 ( +// Equation(s): +// \z80_|alu_|db_high[1]~15_combout = (\z80_|execute_|ctl_alu_op2_oe~0_combout & (\z80_|alu_|op2_high [1] & ((\z80_|alu_|op1_high [1]) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_high +// [1]) # ((!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datab(\z80_|alu_|op1_high [1]), + .datac(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datad(\z80_|alu_|op2_high [1]), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~15 .lut_mask = 16'hCF45; +defparam \z80_|alu_|db_high[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N18 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~16 ( +// Equation(s): +// \z80_|alu_|db_high[1]~16_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[6]~22_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[4]~18_combout ))) + + .dataa(\z80_|alu_|db[6]~22_combout ), + .datab(gnd), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|alu_|db[4]~18_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~16 .lut_mask = 16'hAFA0; +defparam \z80_|alu_|db_high[1]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N12 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~17 ( +// Equation(s): +// \z80_|alu_|db_high[1]~17_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_high[1]~16_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[5]~24_combout )) + + .dataa(\z80_|alu_|db[5]~24_combout ), + .datab(\z80_|alu_|db_high[1]~16_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~17 .lut_mask = 16'hCCAA; +defparam \z80_|alu_|db_high[1]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N6 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~18 ( +// Equation(s): +// \z80_|alu_|db_high[1]~18_combout = (\z80_|alu_|db_high[1]~14_combout & (\z80_|alu_|db_high[1]~15_combout & ((\z80_|alu_|db_high[1]~17_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) + + .dataa(\z80_|alu_|db_high[1]~14_combout ), + .datab(\z80_|alu_|db_high[1]~15_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datad(\z80_|alu_|db_high[1]~17_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~18 .lut_mask = 16'h8808; +defparam \z80_|alu_|db_high[1]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N8 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~19 ( +// Equation(s): +// \z80_|alu_|db_high[1]~19_combout = ((\z80_|alu_|db_high[1]~18_combout & ((\z80_|execute_|ctl_alu_res_oe~3_combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout )))) # (!\z80_|alu_|db_high[3]~1_combout ) + + .dataa(\z80_|execute_|ctl_alu_res_oe~3_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), + .datac(\z80_|alu_|db_high[3]~1_combout ), + .datad(\z80_|alu_|db_high[1]~18_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~19 .lut_mask = 16'hEF0F; +defparam \z80_|alu_|db_high[1]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N16 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & ((\z80_|alu_|db_low[1]~12_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_low~combout & \z80_|alu_|db_high[1]~19_combout )))) # +// (!\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & (\z80_|execute_|ctl_alu_op1_sel_low~combout & ((\z80_|alu_|db_high[1]~19_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .datac(\z80_|alu_|db_low[1]~12_combout ), + .datad(\z80_|alu_|db_high[1]~19_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4 .lut_mask = 16'hECA0; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N22 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .datad(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 .lut_mask = 16'h0F00; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y17_N23 +dffeas \z80_|alu_|op1_low[1] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_low [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_low[1] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_low[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N14 +cycloneive_lcell_comb \z80_|alu_control_|out[6]~0 ( +// Equation(s): +// \z80_|alu_control_|out[6]~0_combout = (\z80_|alu_|op1_low [3] & ((\z80_|alu_|op1_low [1]) # (\z80_|alu_|op1_low [2]))) + + .dataa(\z80_|alu_|op1_low [1]), + .datab(gnd), + .datac(\z80_|alu_|op1_low [3]), + .datad(\z80_|alu_|op1_low [2]), + .cin(gnd), + .combout(\z80_|alu_control_|out[6]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|out[6]~0 .lut_mask = 16'hF0A0; +defparam \z80_|alu_control_|out[6]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N22 +cycloneive_lcell_comb \z80_|alu_control_|out[6]~1 ( +// Equation(s): +// \z80_|alu_control_|out[6]~1_combout = (\z80_|alu_|op1_high [2]) # ((\z80_|alu_|op1_high [1]) # ((\z80_|alu_control_|out[6]~0_combout & \z80_|alu_|op1_high [0]))) + + .dataa(\z80_|alu_|op1_high [2]), + .datab(\z80_|alu_control_|out[6]~0_combout ), + .datac(\z80_|alu_|op1_high [0]), + .datad(\z80_|alu_|op1_high [1]), + .cin(gnd), + .combout(\z80_|alu_control_|out[6]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|out[6]~1 .lut_mask = 16'hFFEA; +defparam \z80_|alu_control_|out[6]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N4 +cycloneive_lcell_comb \z80_|alu_control_|out[6]~2 ( +// Equation(s): +// \z80_|alu_control_|out[6]~2_combout = (\z80_|execute_|ctl_66_oe~combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_cf~q ) # ((\z80_|alu_control_|out[6]~1_combout & \z80_|alu_|op1_high [3]))) + + .dataa(\z80_|alu_control_|out[6]~1_combout ), + .datab(\z80_|execute_|ctl_66_oe~combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), + .datad(\z80_|alu_|op1_high [3]), + .cin(gnd), + .combout(\z80_|alu_control_|out[6]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|out[6]~2 .lut_mask = 16'hFEFC; +defparam \z80_|alu_control_|out[6]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N6 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_12 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout = (\z80_|alu_control_|db[6]~22_combout & \z80_|execute_|ctl_flags_bus~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|alu_control_|db[6]~22_combout ), + .datad(\z80_|execute_|ctl_flags_bus~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_12 .lut_mask = 16'hF000; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N0 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ) # (((!\z80_|pla_decode_|Equal13~0_combout ) # (!\z80_|execute_|ixy_d~7_combout )) # (!\z80_|pla_decode_|Equal55~0_combout )) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 .lut_mask = 16'hBFFF; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N28 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout = (!\z80_|alu_|db_high[3]~7_combout & (!\z80_|alu_|db_high[0]~25_combout & (!\z80_|alu_|db_high[2]~13_combout & !\z80_|alu_|db_high[1]~19_combout ))) + + .dataa(\z80_|alu_|db_high[3]~7_combout ), + .datab(\z80_|alu_|db_high[0]~25_combout ), + .datac(\z80_|alu_|db_high[2]~13_combout ), + .datad(\z80_|alu_|db_high[1]~19_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2 .lut_mask = 16'h0001; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N4 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout = (\z80_|alu_|db_high[3]~1_combout & (!\z80_|alu_|db_low[1]~12_combout & ((!\z80_|alu_|db_low[0]~3_combout ) # (!\z80_|alu_|db_low[0]~6_combout )))) + + .dataa(\z80_|alu_|db_low[0]~6_combout ), + .datab(\z80_|alu_|db_high[3]~1_combout ), + .datac(\z80_|alu_|db_low[1]~12_combout ), + .datad(\z80_|alu_|db_low[0]~3_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 .lut_mask = 16'h040C; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N24 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout = (!\z80_|alu_|db_low[2]~23_combout & (\z80_|execute_|ctl_flags_alu~15_combout & (!\z80_|alu_|db_low[3]~25_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ))) + + .dataa(\z80_|alu_|db_low[2]~23_combout ), + .datab(\z80_|execute_|ctl_flags_alu~15_combout ), + .datac(\z80_|alu_|db_low[3]~25_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 .lut_mask = 16'h0400; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N12 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout & ((\z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout )))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 .lut_mask = 16'hC888; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~7_combout = (!\z80_|execute_|ctl_flags_sz_we~6_combout & \z80_|execute_|ctl_flags_xy_we~14_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_flags_sz_we~6_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~7 .lut_mask = 16'h0F00; +defparam \z80_|execute_|ctl_flags_sz_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~8_combout = (((!\z80_|execute_|ctl_flags_sz_we~3_combout ) # (!\z80_|execute_|ctl_flags_sz_we~2_combout )) # (!\z80_|execute_|ctl_flags_sz_we~4_combout )) # (!\z80_|execute_|ctl_flags_sz_we~7_combout ) + + .dataa(\z80_|execute_|ctl_flags_sz_we~7_combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~4_combout ), + .datac(\z80_|execute_|ctl_flags_sz_we~2_combout ), + .datad(\z80_|execute_|ctl_flags_sz_we~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~8 .lut_mask = 16'h7FFF; +defparam \z80_|execute_|ctl_flags_sz_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y16_N13 +dffeas \z80_|alu_flags_|SYNTHESIZED_WIRE_39 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_flags_sz_we~8_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_39 .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_39 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N20 +cycloneive_lcell_comb \z80_|execute_|setM1~51 ( +// Equation(s): +// \z80_|execute_|setM1~51_combout = (\z80_|execute_|setM1~50_combout & (!\z80_|pla_decode_|Equal52~1_combout & ((!\z80_|pla_decode_|Equal63~0_combout ) # (!\z80_|pla_decode_|Equal3~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal3~0_combout ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|execute_|setM1~50_combout ), + .datad(\z80_|pla_decode_|Equal52~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~51_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~51 .lut_mask = 16'h0070; +defparam \z80_|execute_|setM1~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_oe~2_combout = (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (((\z80_|execute_|ctl_state_alu~6_combout ) # (!\z80_|execute_|ctl_flags_oe~1_combout )) # (!\z80_|execute_|setM1~51_combout ))) + + .dataa(\z80_|execute_|setM1~51_combout ), + .datab(\z80_|execute_|ctl_flags_oe~1_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_oe~2 .lut_mask = 16'h00F7; +defparam \z80_|execute_|ctl_flags_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~7 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~7_combout = (((\z80_|execute_|ctl_alu_oe~1_combout & \z80_|nM1_int~2_combout )) # (!\z80_|execute_|ctl_alu_oe~8_combout )) # (!\z80_|execute_|ctl_reg_out_hi~6_combout ) + + .dataa(\z80_|execute_|ctl_alu_oe~1_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|execute_|ctl_reg_out_hi~6_combout ), + .datad(\z80_|execute_|ctl_alu_oe~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~7 .lut_mask = 16'h8FFF; +defparam \z80_|execute_|ctl_sw_2u~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N10 +cycloneive_lcell_comb \z80_|alu_control_|db[6]~20 ( +// Equation(s): +// \z80_|alu_control_|db[6]~20_combout = (\z80_|alu_|db[6]~22_combout & (!\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & (\z80_|execute_|ctl_flags_oe~2_combout ))) # (!\z80_|alu_|db[6]~22_combout & ((\z80_|execute_|ctl_sw_2u~7_combout ) # +// ((!\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & \z80_|execute_|ctl_flags_oe~2_combout )))) + + .dataa(\z80_|alu_|db[6]~22_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datac(\z80_|execute_|ctl_flags_oe~2_combout ), + .datad(\z80_|execute_|ctl_sw_2u~7_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[6]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[6]~20 .lut_mask = 16'h7530; +defparam \z80_|alu_control_|db[6]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N16 +cycloneive_lcell_comb \z80_|alu_control_|db[6]~21 ( +// Equation(s): +// \z80_|alu_control_|db[6]~21_combout = (!\z80_|alu_control_|db[6]~20_combout & ((\z80_|alu_control_|out[6]~2_combout ) # ((!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & !\z80_|execute_|ctl_66_oe~combout )))) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datab(\z80_|execute_|ctl_66_oe~combout ), + .datac(\z80_|alu_control_|out[6]~2_combout ), + .datad(\z80_|alu_control_|db[6]~20_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[6]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[6]~21 .lut_mask = 16'h00F1; +defparam \z80_|alu_control_|db[6]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~8_combout = (\z80_|execute_|ctl_reg_out_lo~5_combout ) # ((!\z80_|execute_|ctl_reg_out_lo~7_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout )) + + .dataa(\z80_|execute_|ctl_reg_out_lo~5_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~8 .lut_mask = 16'hBFBF; +defparam \z80_|execute_|ctl_reg_out_lo~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N2 +cycloneive_lcell_comb \z80_|alu_control_|db[6]~10 ( +// Equation(s): +// \z80_|alu_control_|db[6]~10_combout = (\z80_|execute_|ctl_flags_oe~2_combout ) # ((\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|execute_|ctl_66_oe~2_combout & \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ))) + + .dataa(\z80_|execute_|ctl_66_oe~2_combout ), + .datab(\z80_|execute_|ctl_flags_oe~2_combout ), + .datac(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[6]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[6]~10 .lut_mask = 16'hFFEC; +defparam \z80_|alu_control_|db[6]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N28 +cycloneive_lcell_comb \z80_|alu_control_|db[6]~11 ( +// Equation(s): +// \z80_|alu_control_|db[6]~11_combout = (\z80_|execute_|ctl_sw_1d~7_combout ) # ((\z80_|execute_|ctl_reg_out_lo~8_combout ) # ((\z80_|execute_|ctl_sw_2u~7_combout ) # (\z80_|alu_control_|db[6]~10_combout ))) + + .dataa(\z80_|execute_|ctl_sw_1d~7_combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .datac(\z80_|execute_|ctl_sw_2u~7_combout ), + .datad(\z80_|alu_control_|db[6]~10_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[6]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[6]~11 .lut_mask = 16'hFFFE; +defparam \z80_|alu_control_|db[6]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N20 +cycloneive_lcell_comb \z80_|alu_control_|db[6]~22 ( +// Equation(s): +// \z80_|alu_control_|db[6]~22_combout = ((\z80_|reg_file_|db_lo_ds[6]~0_combout & (\z80_|sw1_|db_down[6]~1_combout & \z80_|alu_control_|db[6]~21_combout ))) # (!\z80_|alu_control_|db[6]~11_combout ) + + .dataa(\z80_|reg_file_|db_lo_ds[6]~0_combout ), + .datab(\z80_|sw1_|db_down[6]~1_combout ), + .datac(\z80_|alu_control_|db[6]~21_combout ), + .datad(\z80_|alu_control_|db[6]~11_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[6]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[6]~22 .lut_mask = 16'h80FF; +defparam \z80_|alu_control_|db[6]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N10 +cycloneive_lcell_comb \z80_|alu_|db[6]~21 ( +// Equation(s): +// \z80_|alu_|db[6]~21_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[6]~84_combout & ((\z80_|alu_control_|db[6]~22_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & +// ((\z80_|alu_control_|db[6]~22_combout ) # ((!\z80_|execute_|ctl_sw_2d~13_combout )))) + + .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .datab(\z80_|alu_control_|db[6]~22_combout ), + .datac(\z80_|execute_|ctl_sw_2d~13_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[6]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[6]~21 .lut_mask = 16'hCF45; +defparam \z80_|alu_|db[6]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N24 +cycloneive_lcell_comb \z80_|alu_|db[6]~22 ( +// Equation(s): +// \z80_|alu_|db[6]~22_combout = ((\z80_|alu_|db[6]~21_combout & ((\z80_|alu_|db_high[2]~13_combout ) # (!\z80_|execute_|ctl_alu_oe~11_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|execute_|ctl_alu_oe~11_combout ), + .datab(\z80_|alu_|db[7]~9_combout ), + .datac(\z80_|alu_|db_high[2]~13_combout ), + .datad(\z80_|alu_|db[6]~21_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[6]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[6]~22 .lut_mask = 16'hF733; +defparam \z80_|alu_|db[6]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y16_N3 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~80 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~80_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout & (\z80_|alu_|db[6]~22_combout & ((\z80_|reg_file_|b2v_latch_af2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # +// (!\z80_|execute_|ctl_reg_in_hi~12_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .datab(\z80_|alu_|db[6]~22_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~80_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~80 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[6]~80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y16_N23 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y16_N1 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~79 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~79_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [6]), + .datad(\z80_|reg_file_|b2v_latch_iy_hi|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~79_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~79 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[6]~79 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y16_N23 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N20 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_hi|latch[6]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_bc_hi|latch[6]~feeder_combout = \z80_|reg_file_|gdfx_temp1[6]~84_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_bc_hi|latch[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[6]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y16_N21 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_bc_hi|latch[6]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~78 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~78_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (\z80_|reg_file_|b2v_latch_bc2_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]), + .datad(\z80_|reg_file_|b2v_latch_bc_hi|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~78_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~78 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[6]~78 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y16_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~82 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~82_combout = (\z80_|reg_file_|gdfx_temp1[6]~81_combout & (\z80_|reg_file_|gdfx_temp1[6]~80_combout & (\z80_|reg_file_|gdfx_temp1[6]~79_combout & \z80_|reg_file_|gdfx_temp1[6]~78_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[6]~81_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[6]~80_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[6]~79_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[6]~78_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~82_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~82 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[6]~82 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y14_N19 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N18 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl2_hi|db[6]~5 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_hl2_hi|db[6]~5_combout = (\z80_|execute_|ctl_reg_gp_we~8_combout ) # (((\z80_|reg_file_|b2v_latch_hl2_hi|latch [6]) # (!\z80_|reg_control_|reg_sel_hl2~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [6]), + .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_hl2_hi|db[6]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|db[6]~5 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|db[6]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y15_N7 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X37_Y15_N19 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N24 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder_combout = \z80_|reg_file_|gdfx_temp1[6]~84_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y15_N25 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~76 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~76_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [6]), + .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~76_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~76 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[6]~76 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~77 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~77_combout = (\z80_|reg_file_|b2v_latch_hl2_hi|db[6]~5_combout & (\z80_|reg_file_|gdfx_temp1[6]~76_combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl2_hi|db[6]~5_combout ), + .datac(\z80_|reg_file_|b2v_latch_hl_hi|latch [6]), + .datad(\z80_|reg_file_|gdfx_temp1[6]~76_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~77_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~77 .lut_mask = 16'hC400; +defparam \z80_|reg_file_|gdfx_temp1[6]~77 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~83 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~83_combout = (\z80_|reg_file_|gdfx_temp1[6]~82_combout & (\z80_|reg_file_|gdfx_temp1[6]~77_combout & ((\z80_|reg_file_|b2v_latch_af_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_32~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_af_hi|latch [6]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_32~combout ), + .datac(\z80_|reg_file_|gdfx_temp1[6]~82_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[6]~77_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~83_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~83 .lut_mask = 16'hB000; +defparam \z80_|reg_file_|gdfx_temp1[6]~83 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~84 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~84_combout = ((\z80_|reg_file_|gdfx_temp1[6]~83_combout & ((\z80_|reg_file_|db_hi_as[6]~24_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[6]~83_combout ), + .datac(\z80_|reg_file_|db_hi_as[6]~24_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~84 .lut_mask = 16'hC4FF; +defparam \z80_|reg_file_|gdfx_temp1[6]~84 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y14_N19 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[6]~24_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N18 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~22 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[6]~22_combout = (\z80_|reg_control_|reg_sw_4d_hi~0_combout & (\z80_|reg_file_|gdfx_temp1[6]~84_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[6]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[6]~22 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_hi_as[6]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y14_N17 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[6]~24_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N26 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~23 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[6]~23_combout = (\z80_|reg_file_|db_hi_as[6]~22_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|db_hi_as[6]~22_combout ), + .datab(\z80_|reg_file_|b2v_latch_pc_hi|latch [6]), + .datac(gnd), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[6]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[6]~23 .lut_mask = 16'h88AA; +defparam \z80_|reg_file_|db_hi_as[6]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N14 +cycloneive_lcell_comb \z80_|address_latch_|abusz[13] ( +// Equation(s): +// \z80_|address_latch_|abusz [13] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[5]~15_combout ) + + .dataa(\z80_|resets_|clrpc~0_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|db_hi_as[5]~15_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [13]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[13] .lut_mask = 16'h5500; +defparam \z80_|address_latch_|abusz[13] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y13_N15 +dffeas \z80_|address_latch_|Q[13] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [13]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [13]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[13] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N18 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout = \z80_|address_latch_|Q [12] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout & (\z80_|address_latch_|Q [11] $ +// (\z80_|execute_|ctl_inc_dec~11_combout ))))) + + .dataa(\z80_|address_latch_|Q [11]), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), + .datac(\z80_|execute_|ctl_inc_dec~11_combout ), + .datad(\z80_|address_latch_|Q [12]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out .lut_mask = 16'hB748; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y16_N31 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y16_N29 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~61 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~61_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [4]), + .datad(\z80_|reg_file_|b2v_latch_iy_hi|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~61_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~61 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[4]~61 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y16_N15 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~62 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~62_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout & (\z80_|alu_|db[4]~18_combout & ((\z80_|reg_file_|b2v_latch_af2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # +// (!\z80_|execute_|ctl_reg_in_hi~12_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .datab(\z80_|alu_|db[4]~18_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~62_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~62 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[4]~62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y16_N3 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N0 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder_combout = \z80_|reg_file_|gdfx_temp1[4]~66_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y16_N1 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~60 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~60_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (\z80_|reg_file_|b2v_latch_bc2_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]), + .datad(\z80_|reg_file_|b2v_latch_bc_hi|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~60_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~60 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[4]~60 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y15_N29 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X35_Y15_N23 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~63 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~63_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (\z80_|reg_file_|b2v_latch_wz_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (((\z80_|reg_file_|b2v_latch_sp_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .datab(\z80_|reg_file_|b2v_latch_wz_hi|latch [4]), + .datac(\z80_|reg_file_|b2v_latch_sp_hi|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~63_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~63 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[4]~63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~64 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~64_combout = (\z80_|reg_file_|gdfx_temp1[4]~61_combout & (\z80_|reg_file_|gdfx_temp1[4]~62_combout & (\z80_|reg_file_|gdfx_temp1[4]~60_combout & \z80_|reg_file_|gdfx_temp1[4]~63_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[4]~61_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[4]~62_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[4]~60_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[4]~63_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~64_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~64 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[4]~64 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y15_N5 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X37_Y14_N5 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N4 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl2_hi|db[4]~4 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_hl2_hi|db[4]~4_combout = (\z80_|execute_|ctl_reg_gp_we~8_combout ) # (((\z80_|reg_file_|b2v_latch_hl2_hi|latch [4]) # (!\z80_|reg_control_|reg_sel_hl2~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [4]), + .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_hl2_hi|db[4]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|db[4]~4 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|db[4]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y15_N1 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X37_Y15_N5 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X37_Y15_N23 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~58 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~58_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datab(\z80_|reg_file_|b2v_latch_de_hi|latch [4]), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~58_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~58 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[4]~58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~59 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~59_combout = (\z80_|reg_file_|b2v_latch_hl2_hi|db[4]~4_combout & (\z80_|reg_file_|gdfx_temp1[4]~58_combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl2_hi|db[4]~4_combout ), + .datac(\z80_|reg_file_|b2v_latch_hl_hi|latch [4]), + .datad(\z80_|reg_file_|gdfx_temp1[4]~58_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~59_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~59 .lut_mask = 16'hC400; +defparam \z80_|reg_file_|gdfx_temp1[4]~59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~65 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~65_combout = (\z80_|reg_file_|gdfx_temp1[4]~64_combout & (\z80_|reg_file_|gdfx_temp1[4]~59_combout & ((\z80_|reg_file_|b2v_latch_af_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_32~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[4]~64_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_32~combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [4]), + .datad(\z80_|reg_file_|gdfx_temp1[4]~59_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~65_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~65 .lut_mask = 16'hA200; +defparam \z80_|reg_file_|gdfx_temp1[4]~65 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~66 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~66_combout = ((\z80_|reg_file_|gdfx_temp1[4]~65_combout & ((\z80_|reg_file_|db_hi_as[4]~18_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), + .datab(\z80_|reg_file_|db_hi_as[4]~18_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[4]~65_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~66 .lut_mask = 16'hD0FF; +defparam \z80_|reg_file_|gdfx_temp1[4]~66 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y14_N11 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[4]~18_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N10 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~16 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[4]~16_combout = (\z80_|reg_control_|reg_sw_4d_hi~0_combout & (\z80_|reg_file_|gdfx_temp1[4]~66_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[4]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[4]~16 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_hi_as[4]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y14_N25 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[4]~18_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N2 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~17 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[4]~17_combout = (\z80_|reg_file_|db_hi_as[4]~16_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|db_hi_as[4]~16_combout ), + .datab(\z80_|reg_file_|b2v_latch_pc_hi|latch [4]), + .datac(gnd), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[4]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[4]~17 .lut_mask = 16'h88AA; +defparam \z80_|reg_file_|db_hi_as[4]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N24 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~18 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[4]~18_combout = ((\z80_|reg_file_|db_hi_as[4]~17_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), + .datab(\z80_|reg_file_|db_hi_as[4]~17_combout ), + .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[4]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[4]~18 .lut_mask = 16'h8FCF; +defparam \z80_|reg_file_|db_hi_as[4]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N22 +cycloneive_lcell_comb \z80_|address_latch_|abusz[12] ( +// Equation(s): +// \z80_|address_latch_|abusz [12] = (\z80_|reg_file_|db_hi_as[4]~18_combout & !\z80_|resets_|clrpc~0_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[4]~18_combout ), + .datab(gnd), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [12]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[12] .lut_mask = 16'h0A0A; +defparam \z80_|address_latch_|abusz[12] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y13_N23 +dffeas \z80_|address_latch_|Q[12] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [12]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [12]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[12] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N20 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout & ((\z80_|address_latch_|Q [11] & (!\z80_|execute_|ctl_inc_dec~11_combout & +// \z80_|address_latch_|Q [12])) # (!\z80_|address_latch_|Q [11] & (\z80_|execute_|ctl_inc_dec~11_combout & !\z80_|address_latch_|Q [12])))) + + .dataa(\z80_|address_latch_|Q [11]), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), + .datac(\z80_|execute_|ctl_inc_dec~11_combout ), + .datad(\z80_|address_latch_|Q [12]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'h0840; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N24 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[14] ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|address [14] = \z80_|address_latch_|Q [14] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout & (\z80_|address_latch_|Q [13] $ (\z80_|execute_|ctl_inc_dec~11_combout ))))) + + .dataa(\z80_|address_latch_|Q [13]), + .datab(\z80_|execute_|ctl_inc_dec~11_combout ), + .datac(\z80_|address_latch_|Q [14]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[14] .lut_mask = 16'h96F0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[14] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N16 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~24 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[6]~24_combout = ((\z80_|reg_file_|db_hi_as[6]~23_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [14]) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .datab(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datac(\z80_|reg_file_|db_hi_as[6]~23_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[6]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[6]~24 .lut_mask = 16'hF373; +defparam \z80_|reg_file_|db_hi_as[6]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N30 +cycloneive_lcell_comb \z80_|address_latch_|abusz[14] ( +// Equation(s): +// \z80_|address_latch_|abusz [14] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[6]~24_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(\z80_|reg_file_|db_hi_as[6]~24_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [14]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[14] .lut_mask = 16'h0F00; +defparam \z80_|address_latch_|abusz[14] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y13_N31 +dffeas \z80_|address_latch_|Q[14] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [14]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [14]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[14] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N4 +cycloneive_lcell_comb \z80_|address_latch_|abusz[15] ( +// Equation(s): +// \z80_|address_latch_|abusz [15] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[7]~21_combout ) + + .dataa(\z80_|resets_|clrpc~0_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|db_hi_as[7]~21_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [15]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[15] .lut_mask = 16'h5500; +defparam \z80_|address_latch_|abusz[15] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y13_N5 +dffeas \z80_|address_latch_|Q[15] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [15]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [15]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[15] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N2 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[15]~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|address[15]~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout & (\z80_|address_latch_|Q [13] $ (((\z80_|execute_|ctl_inc_dec~10_combout ) # +// (\z80_|execute_|ctl_inc_dec~7_combout ))))) + + .dataa(\z80_|execute_|ctl_inc_dec~10_combout ), + .datab(\z80_|execute_|ctl_inc_dec~7_combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), + .datad(\z80_|address_latch_|Q [13]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|address[15]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[15]~0 .lut_mask = 16'h10E0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[15]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N0 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[15]~1 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|address[15]~1_combout = \z80_|address_latch_|Q [15] $ (((\z80_|address_latch_|b2v_inst_inc_dec|address[15]~0_combout & (\z80_|address_latch_|Q [14] $ (\z80_|execute_|ctl_inc_dec~11_combout ))))) + + .dataa(\z80_|address_latch_|Q [14]), + .datab(\z80_|execute_|ctl_inc_dec~11_combout ), + .datac(\z80_|address_latch_|Q [15]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|address[15]~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|address[15]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[15]~1 .lut_mask = 16'h96F0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[15]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y14_N7 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[7]~21_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X35_Y14_N21 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[7]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N20 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~19 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[7]~19_combout = (\z80_|reg_control_|reg_sw_4d_hi~0_combout & (\z80_|reg_file_|gdfx_temp1[7]~75_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) + + .dataa(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [7]), + .datad(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[7]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[7]~19 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|db_hi_as[7]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N12 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~20 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[7]~20_combout = (\z80_|reg_file_|db_hi_as[7]~19_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_pc_hi|latch [7]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datac(gnd), + .datad(\z80_|reg_file_|db_hi_as[7]~19_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[7]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[7]~20 .lut_mask = 16'hBB00; +defparam \z80_|reg_file_|db_hi_as[7]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N6 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~21 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[7]~21_combout = ((\z80_|reg_file_|db_hi_as[7]~20_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address[15]~1_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|address[15]~1_combout ), + .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datad(\z80_|reg_file_|db_hi_as[7]~20_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[7]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[7]~21 .lut_mask = 16'hDF0F; +defparam \z80_|reg_file_|db_hi_as[7]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y15_N29 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N28 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[7]~15 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[7]~15_combout = (\z80_|execute_|ctl_reg_gp_we~8_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [7]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [7]), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[7]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[7]~15 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[7]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y15_N31 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X35_Y15_N25 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~72 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~72_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (\z80_|reg_file_|b2v_latch_wz_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [7]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [7]), + .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~72_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~72 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp1[7]~72 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y16_N17 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~71 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~71_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout & (\z80_|alu_|db[7]~12_combout & ((\z80_|reg_file_|b2v_latch_af2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # +// (!\z80_|execute_|ctl_reg_in_hi~12_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .datab(\z80_|alu_|db[7]~12_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~71_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~71 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[7]~71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y16_N11 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y16_N13 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~70 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~70_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [7]), + .datad(\z80_|reg_file_|b2v_latch_iy_hi|latch [7]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~70_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~70 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[7]~70 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y16_N15 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X37_Y16_N29 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~69 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~69_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (\z80_|reg_file_|b2v_latch_bc2_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]), + .datad(\z80_|reg_file_|b2v_latch_bc_hi|latch [7]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~69_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~69 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[7]~69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y16_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~73 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~73_combout = (\z80_|reg_file_|gdfx_temp1[7]~72_combout & (\z80_|reg_file_|gdfx_temp1[7]~71_combout & (\z80_|reg_file_|gdfx_temp1[7]~70_combout & \z80_|reg_file_|gdfx_temp1[7]~69_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[7]~72_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[7]~71_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[7]~70_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[7]~69_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~73_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~73 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[7]~73 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y14_N15 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X37_Y14_N25 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~68 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~68_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (\z80_|reg_file_|b2v_latch_hl_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_hl2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (((\z80_|reg_file_|b2v_latch_hl2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [7]), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~68_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~68 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[7]~68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y15_N3 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N0 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_hi|latch[7]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_de_hi|latch[7]~feeder_combout = \z80_|reg_file_|gdfx_temp1[7]~75_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_de_hi|latch[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[7]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y15_N1 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_de_hi|latch[7]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~67 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~67_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [7]), + .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [7]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~67_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~67 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[7]~67 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y15_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~74 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~74_combout = (\z80_|reg_file_|b2v_latch_af_hi|db[7]~15_combout & (\z80_|reg_file_|gdfx_temp1[7]~73_combout & (\z80_|reg_file_|gdfx_temp1[7]~68_combout & \z80_|reg_file_|gdfx_temp1[7]~67_combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_af_hi|db[7]~15_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[7]~73_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[7]~68_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[7]~67_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~74_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~74 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[7]~74 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~75 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~75_combout = ((\z80_|reg_file_|gdfx_temp1[7]~74_combout & ((\z80_|reg_file_|db_hi_as[7]~21_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[7]~21_combout ), + .datab(\z80_|execute_|ctl_sw_4u~6_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[7]~74_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~75 .lut_mask = 16'hBF0F; +defparam \z80_|reg_file_|gdfx_temp1[7]~75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N0 +cycloneive_lcell_comb \z80_|alu_|db[7]~11 ( +// Equation(s): +// \z80_|alu_|db[7]~11_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[7]~75_combout & ((\z80_|alu_control_|db[7]~19_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & +// ((\z80_|alu_control_|db[7]~19_combout ) # ((!\z80_|execute_|ctl_sw_2d~13_combout )))) + + .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .datab(\z80_|alu_control_|db[7]~19_combout ), + .datac(\z80_|execute_|ctl_sw_2d~13_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[7]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[7]~11 .lut_mask = 16'hCF45; +defparam \z80_|alu_|db[7]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N30 +cycloneive_lcell_comb \z80_|alu_|db[7]~12 ( +// Equation(s): +// \z80_|alu_|db[7]~12_combout = ((\z80_|alu_|db[7]~11_combout & ((\z80_|alu_|db_high[3]~7_combout ) # (!\z80_|execute_|ctl_alu_oe~11_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|execute_|ctl_alu_oe~11_combout ), + .datab(\z80_|alu_|db[7]~9_combout ), + .datac(\z80_|alu_|db_high[3]~7_combout ), + .datad(\z80_|alu_|db[7]~11_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[7]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[7]~12 .lut_mask = 16'hF733; +defparam \z80_|alu_|db[7]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N28 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~0 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[0]~14_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[7]~12_combout ))) + + .dataa(\z80_|alu_|db[0]~14_combout ), + .datab(gnd), + .datac(\z80_|alu_|db[7]~12_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~0 .lut_mask = 16'hAAF0; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N2 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~1 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_control_|out[6]~2_combout ))) + + .dataa(gnd), + .datab(\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ), + .datac(\z80_|alu_control_|out[6]~2_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~1 .lut_mask = 16'hCCF0; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N20 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~2 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (((\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout & !\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout )))) # (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout +// & ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((!\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout )))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ), + .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~2 .lut_mask = 16'h03CA; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N8 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~3 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout = (\z80_|execute_|ctl_flags_cf2_we~3_combout & (\z80_|execute_|ctl_flags_cf2_sel_daa~combout $ (((!\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ))))) # (!\z80_|execute_|ctl_flags_cf2_we~3_combout & +// ((\z80_|alu_flags_|DFFE_inst_latch_cf2~q ) # ((\z80_|execute_|ctl_flags_cf2_sel_daa~combout & \z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout )))) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datab(\z80_|execute_|ctl_flags_cf2_we~3_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~3 .lut_mask = 16'hBA74; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y14_N9 +dffeas \z80_|alu_flags_|DFFE_inst_latch_cf2 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2 .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~8_combout = (\z80_|pla_decode_|Equal20~0_combout ) # ((\z80_|execute_|ctl_ir_we~14_combout ) # (\z80_|execute_|ctl_ir_we~8_combout )) + + .dataa(\z80_|pla_decode_|Equal20~0_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_ir_we~14_combout ), + .datad(\z80_|execute_|ctl_ir_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~8 .lut_mask = 16'hFFFA; +defparam \z80_|execute_|ctl_flags_use_cf2~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~9 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~9_combout = (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_flags_use_cf2~8_combout ) # ((\z80_|pla_decode_|Equal63~0_combout & \z80_|pla_decode_|Equal9~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal63~0_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|execute_|ctl_flags_use_cf2~8_combout ), + .datad(\z80_|pla_decode_|Equal9~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~9 .lut_mask = 16'h3230; +defparam \z80_|execute_|ctl_flags_use_cf2~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~10_combout = (\z80_|pla_decode_|Equal11~0_combout & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_M1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~10 .lut_mask = 16'h0C04; +defparam \z80_|execute_|ctl_flags_use_cf2~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~11 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~11_combout = (\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # ((\z80_|execute_|ctl_flags_use_cf2~10_combout ) # ((\z80_|execute_|ixy_d~7_combout & \z80_|pla_decode_|Equal10~0_combout ))) + + .dataa(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|execute_|ctl_flags_use_cf2~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~11 .lut_mask = 16'hFFEA; +defparam \z80_|execute_|ctl_flags_use_cf2~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~12 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~12_combout = ((\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # ((\z80_|execute_|ctl_flags_use_cf2~9_combout ) # (\z80_|execute_|ctl_flags_use_cf2~11_combout ))) # (!\z80_|execute_|ctl_flags_use_cf2~13_combout ) + + .dataa(\z80_|execute_|ctl_flags_use_cf2~13_combout ), + .datab(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .datac(\z80_|execute_|ctl_flags_use_cf2~9_combout ), + .datad(\z80_|execute_|ctl_flags_use_cf2~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~12 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_flags_use_cf2~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N28 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout = (\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & (\z80_|alu_flags_|DFFE_inst_latch_cf2~q )) # (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & ((\z80_|execute_|ctl_flags_use_cf2~12_combout & +// (\z80_|alu_flags_|DFFE_inst_latch_cf2~q )) # (!\z80_|execute_|ctl_flags_use_cf2~12_combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf~q ))))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), + .datac(\z80_|execute_|ctl_flags_use_cf2~12_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 .lut_mask = 16'hABA8; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~46 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~46_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|pla_decode_|Equal10~0_combout & \z80_|sequencer_|DFFE_T3_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|pla_decode_|Equal10~0_combout ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~46 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_alu_op_low~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~9_combout = (\z80_|execute_|ctl_alu_core_S~4_combout & (\z80_|execute_|ctl_bus_inc_oe~44_combout & (\z80_|execute_|ctl_flags_alu~18_combout & \z80_|execute_|ctl_alu_op1_sel_bus~9_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_S~4_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .datac(\z80_|execute_|ctl_flags_alu~18_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~9 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N28 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|pla_decode_|Equal63~0_combout & (\z80_|pla_decode_|Equal21~0_combout & !\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) + + .dataa(\z80_|pla_decode_|Equal63~0_combout ), + .datab(\z80_|pla_decode_|Equal21~0_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 .lut_mask = 16'hFF08; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N10 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout = (\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # ((\z80_|execute_|ctl_alu_op_low~46_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~46_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 .lut_mask = 16'hFFEF; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N16 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout = ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ) # ((\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & \z80_|execute_|ctl_alu_op_low~42_combout ))) # (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ) + + .dataa(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~42_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 .lut_mask = 16'hFBF3; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y17_N16 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout = (\z80_|execute_|ctl_state_alu~11_combout & ((\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3])) # (!\z80_|ir_|opcode [5] & ((!\z80_|ir_|opcode [3]))))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|execute_|ctl_state_alu~11_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 .lut_mask = 16'h8050; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N22 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ) # ((\z80_|execute_|ctl_alu_op_low~41_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~41_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 .lut_mask = 16'hFEFA; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~3_combout = (\z80_|execute_|ctl_alu_op_low~41_combout & (\z80_|pla_decode_|Equal64~0_combout & ((\z80_|pla_decode_|Equal9~0_combout ) # (\z80_|pla_decode_|Equal3~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~41_combout ), + .datab(\z80_|pla_decode_|Equal9~0_combout ), + .datac(\z80_|pla_decode_|Equal64~0_combout ), + .datad(\z80_|pla_decode_|Equal3~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~3 .lut_mask = 16'hA080; +defparam \z80_|execute_|ctl_flags_cf_cpl~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N20 +cycloneive_lcell_comb \z80_|alu_flags_|flags_cf ( +// Equation(s): +// \z80_|alu_flags_|flags_cf~combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout $ (((\z80_|execute_|ctl_flags_cf_cpl~9_combout ) # (\z80_|execute_|ctl_flags_cf_cpl~3_combout ))))) + + .dataa(\z80_|execute_|ctl_flags_cf_cpl~9_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ), + .datad(\z80_|execute_|ctl_flags_cf_cpl~3_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|flags_cf~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|flags_cf .lut_mask = 16'h0C48; +defparam \z80_|alu_flags_|flags_cf .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N14 +cycloneive_lcell_comb \z80_|sw2_|db_up[0]~0 ( +// Equation(s): +// \z80_|sw2_|db_up[0]~0_combout = (\z80_|alu_|db[0]~14_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|alu_|db[0]~14_combout ), + .datad(\z80_|execute_|ctl_sw_2u~7_combout ), + .cin(gnd), + .combout(\z80_|sw2_|db_up[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sw2_|db_up[0]~0 .lut_mask = 16'hF0FF; +defparam \z80_|sw2_|db_up[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N14 +cycloneive_lcell_comb \z80_|alu_control_|db[0]~8 ( +// Equation(s): +// \z80_|alu_control_|db[0]~8_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & (((!\z80_|execute_|ctl_sw_mask543_en~0_combout & \z80_|bus_control_|db[0]~17_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) + + .dataa(\z80_|execute_|ctl_sw_mask543_en~0_combout ), + .datab(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .datac(\z80_|execute_|ctl_sw_1d~7_combout ), + .datad(\z80_|bus_control_|db[0]~17_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[0]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[0]~8 .lut_mask = 16'h4C0C; +defparam \z80_|alu_control_|db[0]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y12_N11 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[0]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y12_N5 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[0]~3_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N4 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~0 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[0]~0_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[0]~22_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # +// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[0]~0 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_lo_as[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N0 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~1 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[0]~1_combout = (\z80_|reg_file_|db_lo_as[0]~0_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_ir_lo|latch [0]), + .datab(gnd), + .datac(\z80_|reg_file_|db_lo_as[0]~0_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[0]~1 .lut_mask = 16'hA0F0; +defparam \z80_|reg_file_|db_lo_as[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~70 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~70_combout = (!\z80_|nM1_int~2_combout & (((!\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ctl_alu_op_low~22_combout )) # (!\z80_|pla_decode_|Equal41~2_combout ))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|pla_decode_|Equal41~2_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~70_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~70 .lut_mask = 16'h0307; +defparam \z80_|execute_|ctl_inc_cy~70 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N8 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~28 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~28_combout = (\z80_|pla_decode_|Equal10~0_combout & (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|pla_decode_|Equal10~0_combout ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~28 .lut_mask = 16'hC080; +defparam \z80_|execute_|pc_inc_hold~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N10 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~15 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~15_combout = (\z80_|execute_|pc_inc_hold~28_combout ) # ((\z80_|execute_|ctl_alu_op_low~22_combout & ((\z80_|pla_decode_|Equal52~1_combout ) # (\z80_|execute_|ixy_d~16_combout )))) + + .dataa(\z80_|pla_decode_|Equal52~1_combout ), + .datab(\z80_|execute_|ixy_d~16_combout ), + .datac(\z80_|execute_|pc_inc_hold~28_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~15 .lut_mask = 16'hFEF0; +defparam \z80_|execute_|pc_inc_hold~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N18 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~27 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~27_combout = (\z80_|pla_decode_|Equal11~0_combout & (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~27 .lut_mask = 16'hC080; +defparam \z80_|execute_|pc_inc_hold~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~10 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~10_combout = (\z80_|execute_|ctl_alu_op_low~22_combout & (((\z80_|execute_|ctl_mRead~7_combout ) # (\z80_|execute_|ctl_mRead~13_combout )))) # (!\z80_|execute_|ctl_alu_op_low~22_combout & (\z80_|execute_|ixy_d~5_combout & +// ((\z80_|execute_|ctl_mRead~13_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_mRead~7_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datad(\z80_|execute_|ctl_mRead~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~10 .lut_mask = 16'hFAC0; +defparam \z80_|execute_|pc_inc_hold~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout = (\z80_|execute_|ixy_d~5_combout & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal55~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~11 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~11_combout = (\z80_|execute_|ctl_alu_op_low~22_combout & ((\z80_|pla_decode_|Equal6~1_combout ) # ((\z80_|execute_|ctl_mRead~8_combout )))) # (!\z80_|execute_|ctl_alu_op_low~22_combout & (\z80_|execute_|ixy_d~5_combout & +// ((\z80_|pla_decode_|Equal6~1_combout ) # (\z80_|execute_|ctl_mRead~8_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datab(\z80_|pla_decode_|Equal6~1_combout ), + .datac(\z80_|execute_|ctl_mRead~8_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~11 .lut_mask = 16'hFCA8; +defparam \z80_|execute_|pc_inc_hold~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout = (\z80_|decode_state_|use_ixiy~combout & (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|pla_decode_|Equal33~2_combout ))) + + .dataa(\z80_|decode_state_|use_ixiy~combout ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|pla_decode_|Equal33~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~9 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~9_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ) # ((\z80_|execute_|ctl_alu_op_low~22_combout & ((\z80_|execute_|ctl_mRead~12_combout ) # (!\z80_|execute_|pc_inc_hold~6_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datac(\z80_|execute_|ctl_mRead~12_combout ), + .datad(\z80_|execute_|pc_inc_hold~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~9 .lut_mask = 16'hEAEE; +defparam \z80_|execute_|pc_inc_hold~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~12 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~12_combout = (\z80_|execute_|pc_inc_hold~10_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ) # ((\z80_|execute_|pc_inc_hold~11_combout ) # (\z80_|execute_|pc_inc_hold~9_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~10_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ), + .datac(\z80_|execute_|pc_inc_hold~11_combout ), + .datad(\z80_|execute_|pc_inc_hold~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~12 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|pc_inc_hold~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~7 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~7_combout = ((\z80_|pla_decode_|Equal12~1_combout ) # ((!\z80_|execute_|ctl_alu_op_low~22_combout & !\z80_|execute_|ixy_d~5_combout ))) # (!\z80_|pla_decode_|Equal25~0_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datab(\z80_|pla_decode_|Equal25~0_combout ), + .datac(\z80_|pla_decode_|Equal12~1_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~7 .lut_mask = 16'hF3F7; +defparam \z80_|execute_|pc_inc_hold~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y14_N8 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~8 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~8_combout = (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|execute_|ctl_mRead~15_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|execute_|ctl_mRead~15_combout ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~8 .lut_mask = 16'h5F7F; +defparam \z80_|execute_|pc_inc_hold~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~13 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~13_combout = (\z80_|execute_|ctl_mRead~6_combout & (\z80_|sequencer_|DFFE_T2_ff~q & ((\z80_|sequencer_|DFFE_M2_ff~q ) # (\z80_|sequencer_|DFFE_M3_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|execute_|ctl_mRead~6_combout ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~13 .lut_mask = 16'hE000; +defparam \z80_|execute_|pc_inc_hold~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y14_N14 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~14 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~14_combout = (!\z80_|execute_|pc_inc_hold~12_combout & (\z80_|execute_|pc_inc_hold~7_combout & (\z80_|execute_|pc_inc_hold~8_combout & !\z80_|execute_|pc_inc_hold~13_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~12_combout ), + .datab(\z80_|execute_|pc_inc_hold~7_combout ), + .datac(\z80_|execute_|pc_inc_hold~8_combout ), + .datad(\z80_|execute_|pc_inc_hold~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~14 .lut_mask = 16'h0040; +defparam \z80_|execute_|pc_inc_hold~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal45~0_combout & \z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|pla_decode_|Equal45~0_combout ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y14_N16 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~16 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~16_combout = (!\z80_|execute_|pc_inc_hold~15_combout & (!\z80_|execute_|pc_inc_hold~27_combout & (\z80_|execute_|pc_inc_hold~14_combout & !\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~15_combout ), + .datab(\z80_|execute_|pc_inc_hold~27_combout ), + .datac(\z80_|execute_|pc_inc_hold~14_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~16 .lut_mask = 16'h0010; +defparam \z80_|execute_|pc_inc_hold~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N8 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~22 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~22_combout = (\z80_|execute_|ctl_mRead~34_combout & (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q )))) + + .dataa(\z80_|execute_|ctl_mRead~34_combout ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~22 .lut_mask = 16'h8880; +defparam \z80_|execute_|pc_inc_hold~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~23 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~23_combout = (\z80_|execute_|pc_inc_hold~26_combout & (!\z80_|pla_decode_|Equal19~0_combout & ((\z80_|execute_|ctl_bus_db_oe~1_combout ) # (!\z80_|execute_|ctl_alu_op_low~22_combout )))) + + .dataa(\z80_|execute_|pc_inc_hold~26_combout ), + .datab(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~23 .lut_mask = 16'h080A; +defparam \z80_|execute_|pc_inc_hold~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~24 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~24_combout = (\z80_|execute_|pc_inc_hold~22_combout ) # ((!\z80_|execute_|pc_inc_hold~23_combout & ((\z80_|execute_|ixy_d~5_combout ) # (\z80_|execute_|ctl_alu_op_low~22_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|pc_inc_hold~22_combout ), + .datac(\z80_|execute_|pc_inc_hold~23_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~24 .lut_mask = 16'hCFCE; +defparam \z80_|execute_|pc_inc_hold~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~41 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~41_combout = (((!\z80_|pla_decode_|Equal3~0_combout & !\z80_|pla_decode_|Equal21~0_combout )) # (!\z80_|pla_decode_|Equal24~0_combout )) # (!\z80_|execute_|ctl_alu_op_low~22_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datab(\z80_|pla_decode_|Equal3~0_combout ), + .datac(\z80_|pla_decode_|Equal21~0_combout ), + .datad(\z80_|pla_decode_|Equal24~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~41 .lut_mask = 16'h57FF; +defparam \z80_|execute_|ctl_inc_cy~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~21 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~21_combout = (\z80_|execute_|ctl_mWrite~4_combout & (\z80_|pla_decode_|Equal55~0_combout & ((\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (\z80_|execute_|ctl_mWrite~9_combout )))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datab(\z80_|execute_|ctl_mWrite~4_combout ), + .datac(\z80_|execute_|ctl_mWrite~9_combout ), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~21 .lut_mask = 16'hC800; +defparam \z80_|execute_|pc_inc_hold~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y15_N8 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~25 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~25_combout = ((\z80_|execute_|pc_inc_hold~24_combout ) # ((\z80_|execute_|pc_inc_hold~21_combout ) # (!\z80_|execute_|ctl_inc_cy~41_combout ))) # (!\z80_|execute_|pc_inc_hold~16_combout ) + + .dataa(\z80_|execute_|pc_inc_hold~16_combout ), + .datab(\z80_|execute_|pc_inc_hold~24_combout ), + .datac(\z80_|execute_|ctl_inc_cy~41_combout ), + .datad(\z80_|execute_|pc_inc_hold~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~25 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|pc_inc_hold~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~69 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~69_combout = (!\z80_|execute_|pc_inc_hold~25_combout & (((!\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ctl_alu_op_low~22_combout )) # (!\z80_|pla_decode_|Equal34~0_combout ))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datac(\z80_|execute_|pc_inc_hold~25_combout ), + .datad(\z80_|pla_decode_|Equal34~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~69_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~69 .lut_mask = 16'h010F; +defparam \z80_|execute_|ctl_inc_cy~69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~17 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~17_combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # ((\z80_|interrupts_|DFFE_inst44~q ) # (\z80_|decode_state_|in_halt~q )) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(gnd), + .datac(\z80_|interrupts_|DFFE_inst44~q ), + .datad(\z80_|decode_state_|in_halt~q ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~17 .lut_mask = 16'hFFFA; +defparam \z80_|execute_|pc_inc_hold~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~71 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~71_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (((\z80_|execute_|ctl_inc_cy~70_combout & \z80_|execute_|ctl_inc_cy~69_combout )) # (!\z80_|execute_|pc_inc_hold~17_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|execute_|ctl_inc_cy~70_combout ), + .datac(\z80_|execute_|ctl_inc_cy~69_combout ), + .datad(\z80_|execute_|pc_inc_hold~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~71_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~71 .lut_mask = 16'h80AA; +defparam \z80_|execute_|ctl_inc_cy~71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~44 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~44_combout = (\z80_|execute_|ctl_inc_cy~82_combout & (\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout & ((\z80_|execute_|pc_inc_hold~16_combout ) # (!\z80_|execute_|pc_inc_hold~17_combout )))) # +// (!\z80_|execute_|ctl_inc_cy~82_combout & (((\z80_|execute_|pc_inc_hold~16_combout ) # (!\z80_|execute_|pc_inc_hold~17_combout )))) + + .dataa(\z80_|execute_|ctl_inc_cy~82_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), + .datac(\z80_|execute_|pc_inc_hold~16_combout ), + .datad(\z80_|execute_|pc_inc_hold~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~44 .lut_mask = 16'hD0DD; +defparam \z80_|execute_|ctl_inc_cy~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~42 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~42_combout = (\z80_|execute_|pc_inc_hold~16_combout & \z80_|execute_|ctl_inc_cy~41_combout ) + + .dataa(\z80_|execute_|pc_inc_hold~16_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_inc_cy~41_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~42 .lut_mask = 16'hA0A0; +defparam \z80_|execute_|ctl_inc_cy~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~43 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~43_combout = (\z80_|execute_|ctl_mWrite~17_combout & (\z80_|execute_|ixy_d~5_combout & ((\z80_|execute_|ctl_inc_cy~42_combout ) # (!\z80_|execute_|pc_inc_hold~17_combout )))) + + .dataa(\z80_|execute_|pc_inc_hold~17_combout ), + .datab(\z80_|execute_|ctl_inc_cy~42_combout ), + .datac(\z80_|execute_|ctl_mWrite~17_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~43 .lut_mask = 16'hD000; +defparam \z80_|execute_|ctl_inc_cy~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~57 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~57_combout = (\z80_|execute_|ctl_inc_cy~38_combout ) # ((\z80_|execute_|pc_inc_hold~17_combout & ((\z80_|execute_|pc_inc_hold~12_combout ) # (!\z80_|execute_|pc_inc_hold~7_combout )))) + + .dataa(\z80_|execute_|ctl_inc_cy~38_combout ), + .datab(\z80_|execute_|pc_inc_hold~17_combout ), + .datac(\z80_|execute_|pc_inc_hold~7_combout ), + .datad(\z80_|execute_|pc_inc_hold~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~57_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~57 .lut_mask = 16'hEEAE; +defparam \z80_|execute_|ctl_inc_cy~57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~54 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~54_combout = ((!\z80_|execute_|ctl_alu_op_low~22_combout & ((!\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_T4_ff~q )))) # (!\z80_|pla_decode_|Equal10~0_combout ) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~54_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~54 .lut_mask = 16'h0F7F; +defparam \z80_|execute_|ctl_inc_cy~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~58 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~58_combout = ((!\z80_|execute_|pc_inc_hold~27_combout & (\z80_|execute_|pc_inc_hold~14_combout & !\z80_|execute_|ctl_inc_cy~54_combout ))) # (!\z80_|execute_|ctl_inc_cy~57_combout ) + + .dataa(\z80_|execute_|ctl_inc_cy~57_combout ), + .datab(\z80_|execute_|pc_inc_hold~27_combout ), + .datac(\z80_|execute_|pc_inc_hold~14_combout ), + .datad(\z80_|execute_|ctl_inc_cy~54_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~58_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~58 .lut_mask = 16'h5575; +defparam \z80_|execute_|ctl_inc_cy~58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~18 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~18_combout = (\z80_|execute_|pc_inc_hold~10_combout ) # ((\z80_|execute_|pc_inc_hold~9_combout ) # ((\z80_|execute_|ixy_d~5_combout & \z80_|execute_|ctl_mRead~7_combout ))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_mRead~7_combout ), + .datac(\z80_|execute_|pc_inc_hold~10_combout ), + .datad(\z80_|execute_|pc_inc_hold~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~18 .lut_mask = 16'hFFF8; +defparam \z80_|execute_|pc_inc_hold~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y14_N30 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~19 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~19_combout = (\z80_|execute_|pc_inc_hold~18_combout ) # ((\z80_|execute_|pc_inc_hold~13_combout ) # ((\z80_|execute_|pc_inc_hold~11_combout ) # (!\z80_|execute_|pc_inc_hold~7_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~18_combout ), + .datab(\z80_|execute_|pc_inc_hold~13_combout ), + .datac(\z80_|execute_|pc_inc_hold~7_combout ), + .datad(\z80_|execute_|pc_inc_hold~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~19 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|pc_inc_hold~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~45 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~45_combout = ((\z80_|pla_decode_|Equal9~1_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ixy_d~9_combout )))) # (!\z80_|execute_|ctl_inc_cy~87_combout ) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_inc_cy~87_combout ), + .datad(\z80_|execute_|ixy_d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~45 .lut_mask = 16'hAF8F; +defparam \z80_|execute_|ctl_inc_cy~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~34 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~34_combout = ((!\z80_|execute_|ctl_alu_op_low~22_combout & (!\z80_|execute_|ctl_state_alu~2_combout & !\z80_|execute_|ixy_d~5_combout ))) # (!\z80_|execute_|ctl_mWrite~6_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~34 .lut_mask = 16'h3337; +defparam \z80_|execute_|ctl_inc_cy~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~35 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~35_combout = (\z80_|execute_|ctl_sw_2u~0_combout & (\z80_|execute_|ctl_inc_cy~34_combout & ((!\z80_|pla_decode_|Equal11~0_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_sw_2u~0_combout ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|execute_|ctl_inc_cy~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~35 .lut_mask = 16'h4C00; +defparam \z80_|execute_|ctl_inc_cy~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~46 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~46_combout = (\z80_|pla_decode_|Equal11~0_combout & ((\z80_|execute_|ixy_d~9_combout ) # ((\z80_|execute_|ctl_mWrite~6_combout & \z80_|execute_|ixy_d~7_combout )))) # (!\z80_|pla_decode_|Equal11~0_combout & +// (\z80_|execute_|ctl_mWrite~6_combout & (\z80_|execute_|ixy_d~7_combout ))) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ixy_d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~46 .lut_mask = 16'hEAC0; +defparam \z80_|execute_|ctl_inc_cy~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~47 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~47_combout = ((\z80_|execute_|ctl_inc_cy~46_combout ) # ((\z80_|execute_|ctl_mWrite~6_combout & \z80_|execute_|ctl_mRead~9_combout ))) # (!\z80_|execute_|ctl_inc_cy~39_combout ) + + .dataa(\z80_|execute_|ctl_inc_cy~39_combout ), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datac(\z80_|execute_|ctl_mRead~9_combout ), + .datad(\z80_|execute_|ctl_inc_cy~46_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~47 .lut_mask = 16'hFFD5; +defparam \z80_|execute_|ctl_inc_cy~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~48 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~48_combout = (\z80_|execute_|ctl_inc_cy~47_combout ) # ((\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ) # ((\z80_|pla_decode_|Equal11~0_combout & \z80_|execute_|ctl_alu_op_low~22_combout ))) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datac(\z80_|execute_|ctl_inc_cy~47_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~48 .lut_mask = 16'hFFF8; +defparam \z80_|execute_|ctl_inc_cy~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y18_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~50 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~50_combout = (\z80_|execute_|ctl_inc_cy~45_combout ) # (((\z80_|execute_|ctl_inc_cy~48_combout ) # (!\z80_|execute_|ctl_inc_cy~35_combout )) # (!\z80_|execute_|ctl_inc_cy~49_combout )) + + .dataa(\z80_|execute_|ctl_inc_cy~45_combout ), + .datab(\z80_|execute_|ctl_inc_cy~49_combout ), + .datac(\z80_|execute_|ctl_inc_cy~35_combout ), + .datad(\z80_|execute_|ctl_inc_cy~48_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~50_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~50 .lut_mask = 16'hFFBF; +defparam \z80_|execute_|ctl_inc_cy~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y14_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~51 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~51_combout = (\z80_|execute_|ctl_inc_cy~50_combout & (((!\z80_|execute_|pc_inc_hold~19_combout & \z80_|execute_|pc_inc_hold~8_combout )) # (!\z80_|execute_|pc_inc_hold~17_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~19_combout ), + .datab(\z80_|execute_|pc_inc_hold~17_combout ), + .datac(\z80_|execute_|pc_inc_hold~8_combout ), + .datad(\z80_|execute_|ctl_inc_cy~50_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~51_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~51 .lut_mask = 16'h7300; +defparam \z80_|execute_|ctl_inc_cy~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y14_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~85 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~85_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|execute_|ctl_mRead~6_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|execute_|ctl_mRead~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~85_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~85 .lut_mask = 16'h57FF; +defparam \z80_|execute_|ctl_inc_cy~85 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~63 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~63_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (!\z80_|interrupts_|DFFE_inst44~q & (\z80_|execute_|ctl_mRead~12_combout & !\z80_|decode_state_|in_halt~q ))) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|interrupts_|DFFE_inst44~q ), + .datac(\z80_|execute_|ctl_mRead~12_combout ), + .datad(\z80_|decode_state_|in_halt~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~63_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~63 .lut_mask = 16'h0010; +defparam \z80_|execute_|ctl_inc_cy~63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~64 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~64_combout = (\z80_|execute_|ctl_alu_op_low~22_combout & ((\z80_|execute_|ctl_inc_cy~63_combout ) # ((!\z80_|execute_|ctl_reg_sys_hilo~21_combout & !\z80_|execute_|pc_inc_hold~9_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo~21_combout ), + .datab(\z80_|execute_|ctl_inc_cy~63_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datad(\z80_|execute_|pc_inc_hold~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~64_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~64 .lut_mask = 16'hC0D0; +defparam \z80_|execute_|ctl_inc_cy~64 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~65 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~65_combout = (\z80_|execute_|ctl_inc_cy~64_combout ) # ((\z80_|execute_|ctl_mRead~13_combout & (\z80_|execute_|ctl_alu_shift_oe~14_combout & !\z80_|execute_|pc_inc_hold~18_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~13_combout ), + .datab(\z80_|execute_|ctl_inc_cy~64_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datad(\z80_|execute_|pc_inc_hold~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~65_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~65 .lut_mask = 16'hCCEC; +defparam \z80_|execute_|ctl_inc_cy~65 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~59 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~59_combout = (((!\z80_|pla_decode_|Equal55~0_combout ) # (!\z80_|execute_|ctl_alu_op_low~22_combout )) # (!\z80_|pla_decode_|Equal6~0_combout )) # (!\z80_|pla_decode_|Equal33~1_combout ) + + .dataa(\z80_|pla_decode_|Equal33~1_combout ), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~59_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~59 .lut_mask = 16'h7FFF; +defparam \z80_|execute_|ctl_inc_cy~59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~60 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~60_combout = ((\z80_|execute_|ctl_inc_cy~59_combout & (!\z80_|execute_|pc_inc_hold~9_combout & !\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ))) # (!\z80_|execute_|pc_inc_hold~17_combout ) + + .dataa(\z80_|execute_|ctl_inc_cy~59_combout ), + .datab(\z80_|execute_|pc_inc_hold~9_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ), + .datad(\z80_|execute_|pc_inc_hold~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~60_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~60 .lut_mask = 16'h02FF; +defparam \z80_|execute_|ctl_inc_cy~60 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~61 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~61_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|execute_|ctl_mRead~8_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|execute_|ctl_mRead~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~61_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~61 .lut_mask = 16'h57FF; +defparam \z80_|execute_|ctl_inc_cy~61 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y14_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~62 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~62_combout = (\z80_|execute_|pc_inc_hold~12_combout & (\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & (\z80_|execute_|ctl_inc_cy~60_combout ))) # (!\z80_|execute_|pc_inc_hold~12_combout & +// (((\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & \z80_|execute_|ctl_inc_cy~60_combout )) # (!\z80_|execute_|ctl_inc_cy~61_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~12_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), + .datac(\z80_|execute_|ctl_inc_cy~60_combout ), + .datad(\z80_|execute_|ctl_inc_cy~61_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~62_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~62 .lut_mask = 16'hC0D5; +defparam \z80_|execute_|ctl_inc_cy~62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y14_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~66 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~66_combout = (\z80_|execute_|ctl_inc_cy~65_combout ) # ((\z80_|execute_|ctl_inc_cy~62_combout ) # ((!\z80_|execute_|ctl_inc_cy~85_combout & !\z80_|execute_|pc_inc_hold~19_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~85_combout ), + .datab(\z80_|execute_|ctl_inc_cy~65_combout ), + .datac(\z80_|execute_|pc_inc_hold~19_combout ), + .datad(\z80_|execute_|ctl_inc_cy~62_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~66_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~66 .lut_mask = 16'hFFCD; +defparam \z80_|execute_|ctl_inc_cy~66 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~53 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~53_combout = ((\z80_|execute_|ixy_d~5_combout & ((\z80_|pla_decode_|Equal41~2_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) # (!\z80_|execute_|ctl_reg_sel_pc~7_combout ) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~7_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datad(\z80_|pla_decode_|Equal41~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~53_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~53 .lut_mask = 16'hBB3B; +defparam \z80_|execute_|ctl_inc_cy~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~52 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~52_combout = (\z80_|execute_|ctl_mRead~2_combout ) # ((\z80_|execute_|ctl_mWrite~8_combout ) # ((\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~8_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~2_combout ), + .datab(\z80_|execute_|ctl_mWrite~8_combout ), + .datac(\z80_|pla_decode_|Equal34~0_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~52_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~52 .lut_mask = 16'hFEFF; +defparam \z80_|execute_|ctl_inc_cy~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~84 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~84_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & ((\z80_|execute_|ctl_inc_cy~52_combout ) # (!\z80_|execute_|fMRead~7_combout )))) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|execute_|ctl_inc_cy~52_combout ), + .datac(\z80_|execute_|fMRead~7_combout ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~84_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~84 .lut_mask = 16'h8A00; +defparam \z80_|execute_|ctl_inc_cy~84 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|pla_decode_|Equal8~0_combout & \z80_|execute_|ctl_mWrite~4_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|pla_decode_|Equal8~0_combout ), + .datad(\z80_|execute_|ctl_mWrite~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~55 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~55_combout = ((\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ) # ((!\z80_|execute_|ctl_inc_cy~54_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ))) # (!\z80_|execute_|ctl_reg_sys_we~2_combout ) + + .dataa(\z80_|execute_|ctl_reg_sys_we~2_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), + .datad(\z80_|execute_|ctl_inc_cy~54_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~55_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~55 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_inc_cy~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y14_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~56 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~56_combout = (!\z80_|execute_|pc_inc_hold~17_combout & ((\z80_|execute_|ctl_inc_cy~53_combout ) # ((\z80_|execute_|ctl_inc_cy~84_combout ) # (\z80_|execute_|ctl_inc_cy~55_combout )))) + + .dataa(\z80_|execute_|ctl_inc_cy~53_combout ), + .datab(\z80_|execute_|ctl_inc_cy~84_combout ), + .datac(\z80_|execute_|pc_inc_hold~17_combout ), + .datad(\z80_|execute_|ctl_inc_cy~55_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~56_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~56 .lut_mask = 16'h0F0E; +defparam \z80_|execute_|ctl_inc_cy~56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~67 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~67_combout = (\z80_|execute_|ctl_inc_cy~58_combout ) # ((\z80_|execute_|ctl_inc_cy~51_combout ) # ((\z80_|execute_|ctl_inc_cy~66_combout ) # (\z80_|execute_|ctl_inc_cy~56_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~58_combout ), + .datab(\z80_|execute_|ctl_inc_cy~51_combout ), + .datac(\z80_|execute_|ctl_inc_cy~66_combout ), + .datad(\z80_|execute_|ctl_inc_cy~56_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~67_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~67 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_inc_cy~67 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y14_N20 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~20 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~20_combout = (\z80_|execute_|pc_inc_hold~19_combout ) # ((\z80_|execute_|pc_inc_hold~27_combout ) # ((\z80_|execute_|pc_inc_hold~15_combout ) # (!\z80_|execute_|pc_inc_hold~8_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~19_combout ), + .datab(\z80_|execute_|pc_inc_hold~27_combout ), + .datac(\z80_|execute_|pc_inc_hold~8_combout ), + .datad(\z80_|execute_|pc_inc_hold~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~20 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|pc_inc_hold~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y15_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~83 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~83_combout = (\z80_|execute_|ctl_state_alu~6_combout & (\z80_|sequencer_|DFFE_M2_ff~q & (!\z80_|execute_|pc_inc_hold~20_combout & \z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|execute_|ctl_state_alu~6_combout ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|execute_|pc_inc_hold~20_combout ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~83_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~83 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_inc_cy~83 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~68 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~68_combout = (\z80_|execute_|ctl_inc_cy~44_combout ) # ((\z80_|execute_|ctl_inc_cy~43_combout ) # ((\z80_|execute_|ctl_inc_cy~67_combout ) # (\z80_|execute_|ctl_inc_cy~83_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~44_combout ), + .datab(\z80_|execute_|ctl_inc_cy~43_combout ), + .datac(\z80_|execute_|ctl_inc_cy~67_combout ), + .datad(\z80_|execute_|ctl_inc_cy~83_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~68_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~68 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_inc_cy~68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N30 +cycloneive_lcell_comb \z80_|address_latch_|Q[0]~feeder ( +// Equation(s): +// \z80_|address_latch_|Q[0]~feeder_combout = \z80_|address_latch_|abusz [0] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [0]), + .cin(gnd), + .combout(\z80_|address_latch_|Q[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|Q[0]~feeder .lut_mask = 16'hFF00; +defparam \z80_|address_latch_|Q[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y11_N31 +dffeas \z80_|address_latch_|Q[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|Q[0]~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[0] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~72 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~72_combout = (\z80_|execute_|pc_inc_hold~16_combout & (\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout & (\z80_|execute_|ctl_inc_cy~41_combout & !\z80_|execute_|pc_inc_hold~21_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~16_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ), + .datac(\z80_|execute_|ctl_inc_cy~41_combout ), + .datad(\z80_|execute_|pc_inc_hold~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~72_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~72 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_inc_cy~72 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y18_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~73 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~73_combout = (\z80_|execute_|ixy_d~9_combout ) # ((\z80_|execute_|ctl_alu_oe~0_combout ) # ((\z80_|sequencer_|DFFE_M4_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|execute_|ixy_d~9_combout ), + .datac(\z80_|execute_|ctl_alu_oe~0_combout ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~73_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~73 .lut_mask = 16'hFEFC; +defparam \z80_|execute_|ctl_inc_cy~73 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y18_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~74 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~74_combout = ((\z80_|pla_decode_|Equal19~0_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # (\z80_|execute_|ctl_inc_cy~73_combout )))) # (!\z80_|execute_|ctl_inc_cy~86_combout ) + + .dataa(\z80_|execute_|ctl_inc_cy~86_combout ), + .datab(\z80_|pla_decode_|Equal19~0_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|execute_|ctl_inc_cy~73_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~74_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~74 .lut_mask = 16'hDDD5; +defparam \z80_|execute_|ctl_inc_cy~74 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~75 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~75_combout = (\z80_|execute_|ctl_inc_cy~72_combout ) # ((\z80_|execute_|ctl_inc_cy~74_combout & ((!\z80_|execute_|pc_inc_hold~17_combout ) # (!\z80_|execute_|pc_inc_hold~25_combout )))) + + .dataa(\z80_|execute_|ctl_inc_cy~72_combout ), + .datab(\z80_|execute_|pc_inc_hold~25_combout ), + .datac(\z80_|execute_|ctl_inc_cy~74_combout ), + .datad(\z80_|execute_|pc_inc_hold~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~75_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~75 .lut_mask = 16'hBAFA; +defparam \z80_|execute_|ctl_inc_cy~75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~76 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~76_combout = (((!\z80_|execute_|ctl_inc_cy~40_combout ) # (!\z80_|execute_|ctl_inc_cy~37_combout )) # (!\z80_|execute_|ctl_inc_cy~33_combout )) # (!\z80_|execute_|ctl_inc_cy~32_combout ) + + .dataa(\z80_|execute_|ctl_inc_cy~32_combout ), + .datab(\z80_|execute_|ctl_inc_cy~33_combout ), + .datac(\z80_|execute_|ctl_inc_cy~37_combout ), + .datad(\z80_|execute_|ctl_inc_cy~40_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~76_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~76 .lut_mask = 16'h7FFF; +defparam \z80_|execute_|ctl_inc_cy~76 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y18_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~80 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~80_combout = (\z80_|execute_|ctl_inc_cy~76_combout ) # ((!\z80_|execute_|ctl_inc_cy~36_combout ) # (!\z80_|execute_|ctl_inc_cy~79_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_inc_cy~76_combout ), + .datac(\z80_|execute_|ctl_inc_cy~79_combout ), + .datad(\z80_|execute_|ctl_inc_cy~36_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~80_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~80 .lut_mask = 16'hCFFF; +defparam \z80_|execute_|ctl_inc_cy~80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~81 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~81_combout = (\z80_|execute_|ctl_inc_cy~75_combout ) # ((\z80_|execute_|ctl_inc_cy~80_combout & ((\z80_|execute_|ctl_inc_cy~69_combout ) # (!\z80_|execute_|pc_inc_hold~17_combout )))) + + .dataa(\z80_|execute_|pc_inc_hold~17_combout ), + .datab(\z80_|execute_|ctl_inc_cy~69_combout ), + .datac(\z80_|execute_|ctl_inc_cy~75_combout ), + .datad(\z80_|execute_|ctl_inc_cy~80_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~81_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~81 .lut_mask = 16'hFDF0; +defparam \z80_|execute_|ctl_inc_cy~81 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N20 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout = \z80_|address_latch_|Q [0] $ (((\z80_|execute_|ctl_inc_cy~71_combout ) # ((\z80_|execute_|ctl_inc_cy~68_combout ) # (\z80_|execute_|ctl_inc_cy~81_combout )))) + + .dataa(\z80_|execute_|ctl_inc_cy~71_combout ), + .datab(\z80_|execute_|ctl_inc_cy~68_combout ), + .datac(\z80_|address_latch_|Q [0]), + .datad(\z80_|execute_|ctl_inc_cy~81_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out .lut_mask = 16'h0F1E; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N10 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~3 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[0]~3_combout = ((\z80_|reg_file_|db_lo_as[0]~1_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .datab(\z80_|reg_file_|db_lo_as[0]~1_combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), + .datad(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[0]~3 .lut_mask = 16'hC4FF; +defparam \z80_|reg_file_|db_lo_as[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y11_N1 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N10 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[0]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_lo|latch[0]~feeder_combout = \z80_|reg_file_|gdfx_temp0[0]~22_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[0]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y11_N11 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_af_lo|latch[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~13 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~13_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [0]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~13 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[0]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y14_N9 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~12 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~12_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [0] & ((\z80_|alu_control_|db[0]~12_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|alu_control_|db[0]~12_combout ) # ((!\z80_|execute_|ctl_reg_in_lo~8_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datab(\z80_|alu_control_|db[0]~12_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [0]), + .datad(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~12 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[0]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N8 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_lo|latch[0]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_de_lo|latch[0]~feeder_combout = \z80_|reg_file_|gdfx_temp0[0]~22_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_de_lo|latch[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[0]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y11_N9 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_de_lo|latch[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y11_N27 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~10 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~10_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [0] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [0] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [0]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~10 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp0[0]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y12_N3 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N2 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0_combout = ((\z80_|execute_|ctl_reg_gp_we~8_combout ) # ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]) # (!\z80_|reg_control_|reg_sel_hl2~0_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]), + .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0 .lut_mask = 16'hFDFF; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y12_N9 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~11 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~11_combout = (\z80_|reg_file_|gdfx_temp0[0]~10_combout & (\z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0_combout & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp0[0]~10_combout ), + .datab(\z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_hl_lo|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~11 .lut_mask = 16'h8088; +defparam \z80_|reg_file_|gdfx_temp0[0]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N2 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder_combout = \z80_|reg_file_|gdfx_temp0[0]~22_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y14_N3 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X32_Y13_N13 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~14 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~14_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (\z80_|reg_file_|b2v_latch_ix_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [0]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [0]), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~14 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[0]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y13_N11 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N20 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_sp_lo|latch[0]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_sp_lo|latch[0]~feeder_combout = \z80_|reg_file_|gdfx_temp0[0]~22_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_sp_lo|latch[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[0]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y12_N21 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_sp_lo|latch[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X31_Y12_N17 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~15 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~15_combout = (\z80_|reg_file_|b2v_latch_sp_lo|latch [0] & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # (!\z80_|reg_file_|b2v_latch_sp_lo|latch [0] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_sp_lo|latch [0]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_iy_lo|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~15 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp0[0]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~16 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~16_combout = (\z80_|reg_file_|gdfx_temp0[0]~14_combout & (\z80_|reg_file_|gdfx_temp0[0]~15_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp0[0]~14_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [0]), + .datad(\z80_|reg_file_|gdfx_temp0[0]~15_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~16 .lut_mask = 16'hA200; +defparam \z80_|reg_file_|gdfx_temp0[0]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~17 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~17_combout = (\z80_|reg_file_|gdfx_temp0[0]~13_combout & (\z80_|reg_file_|gdfx_temp0[0]~12_combout & (\z80_|reg_file_|gdfx_temp0[0]~11_combout & \z80_|reg_file_|gdfx_temp0[0]~16_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[0]~13_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~12_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[0]~11_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~16_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~17 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[0]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~22 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~22_combout = ((\z80_|reg_file_|gdfx_temp0[0]~17_combout & ((\z80_|reg_file_|db_lo_as[0]~3_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .datac(\z80_|reg_file_|db_lo_as[0]~3_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~17_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~22 .lut_mask = 16'hF733; +defparam \z80_|reg_file_|gdfx_temp0[0]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N22 +cycloneive_lcell_comb \z80_|alu_control_|db[0]~9 ( +// Equation(s): +// \z80_|alu_control_|db[0]~9_combout = (\z80_|sw2_|db_up[0]~0_combout & (\z80_|alu_control_|db[0]~8_combout & ((\z80_|reg_file_|gdfx_temp0[0]~22_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) + + .dataa(\z80_|sw2_|db_up[0]~0_combout ), + .datab(\z80_|alu_control_|db[0]~8_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[0]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[0]~9 .lut_mask = 16'h8088; +defparam \z80_|alu_control_|db[0]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N0 +cycloneive_lcell_comb \z80_|alu_control_|db[0]~12 ( +// Equation(s): +// \z80_|alu_control_|db[0]~12_combout = ((\z80_|alu_control_|db[0]~9_combout & ((\z80_|alu_flags_|flags_cf~combout ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) + + .dataa(\z80_|alu_flags_|flags_cf~combout ), + .datab(\z80_|execute_|ctl_flags_oe~2_combout ), + .datac(\z80_|alu_control_|db[0]~9_combout ), + .datad(\z80_|alu_control_|db[6]~11_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[0]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[0]~12 .lut_mask = 16'hB0FF; +defparam \z80_|alu_control_|db[0]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N2 +cycloneive_lcell_comb \z80_|address_latch_|abusz[8] ( +// Equation(s): +// \z80_|address_latch_|abusz [8] = (\z80_|reg_file_|db_hi_as[0]~6_combout & !\z80_|resets_|clrpc~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|reg_file_|db_hi_as[0]~6_combout ), + .datad(\z80_|resets_|clrpc~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [8]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[8] .lut_mask = 16'h00F0; +defparam \z80_|address_latch_|abusz[8] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y10_N3 +dffeas \z80_|address_latch_|Q[8] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [8]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [8]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[8] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N4 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout = \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout $ (\z80_|address_latch_|Q [7]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), + .datad(\z80_|address_latch_|Q [7]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out .lut_mask = 16'h0FF0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y12_N21 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y12_N11 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~84 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~84_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (\z80_|reg_file_|b2v_latch_hl_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl_lo|latch [7]), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~84_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~84 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp0[7]~84 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N20 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_lo|latch[7]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_de_lo|latch[7]~feeder_combout = \z80_|reg_file_|gdfx_temp0[7]~91_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_de_lo|latch[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[7]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y11_N21 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_de_lo|latch[7]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y11_N7 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~83 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~83_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [7] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [7] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [7]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~83_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~83 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp0[7]~83 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y12_N29 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~88 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~88_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [7] & ((\z80_|alu_control_|db[7]~19_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|alu_control_|db[7]~19_combout ) # ((!\z80_|execute_|ctl_reg_in_lo~8_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datab(\z80_|alu_control_|db[7]~19_combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [7]), + .datad(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~88_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~88 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[7]~88 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y14_N25 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X32_Y14_N23 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~86 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~86_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [7]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [7]), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~86_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~86 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[7]~86 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y12_N25 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X31_Y12_N27 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~87 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~87_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (\z80_|reg_file_|b2v_latch_ix_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [7]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_iy_lo|latch [7]), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~87_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~87 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[7]~87 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y12_N29 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N28 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_wz_lo|db[7]~0 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_wz_lo|db[7]~0_combout = (\z80_|reg_control_|reg_sys_we_lo~combout ) # (((\z80_|reg_file_|b2v_latch_wz_lo|latch [7]) # (!\z80_|execute_|ctl_reg_sel_wz~18_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[0]~31_combout )) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~31_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [7]), + .datad(\z80_|execute_|ctl_reg_sel_wz~18_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_wz_lo|db[7]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|db[7]~0 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_wz_lo|db[7]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~89 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~89_combout = (\z80_|reg_file_|gdfx_temp0[7]~88_combout & (\z80_|reg_file_|gdfx_temp0[7]~86_combout & (\z80_|reg_file_|gdfx_temp0[7]~87_combout & \z80_|reg_file_|b2v_latch_wz_lo|db[7]~0_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[7]~88_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[7]~86_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[7]~87_combout ), + .datad(\z80_|reg_file_|b2v_latch_wz_lo|db[7]~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~89_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~89 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[7]~89 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y11_N29 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X32_Y11_N7 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~85 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~85_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [7]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [7]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~85_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~85 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[7]~85 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~90 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~90_combout = (\z80_|reg_file_|gdfx_temp0[7]~84_combout & (\z80_|reg_file_|gdfx_temp0[7]~83_combout & (\z80_|reg_file_|gdfx_temp0[7]~89_combout & \z80_|reg_file_|gdfx_temp0[7]~85_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[7]~84_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[7]~83_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[7]~89_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[7]~85_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~90 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[7]~90 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~91 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~91_combout = ((\z80_|reg_file_|gdfx_temp0[7]~90_combout & ((\z80_|reg_file_|db_lo_as[7]~24_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .datac(\z80_|execute_|ctl_sw_4u~6_combout ), + .datad(\z80_|reg_file_|db_lo_as[7]~24_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~91 .lut_mask = 16'hBB3B; +defparam \z80_|reg_file_|gdfx_temp0[7]~91 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y12_N15 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[7]~24_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N14 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~22 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[7]~22_combout = (\z80_|reg_file_|gdfx_temp0[7]~91_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) # (!\z80_|reg_file_|gdfx_temp0[7]~91_combout & +// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [7]), + .datad(\z80_|execute_|ctl_sw_4d~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[7]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[7]~22 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|db_lo_as[7]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y12_N13 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[7]~24_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N18 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~23 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[7]~23_combout = (\z80_|reg_file_|db_lo_as[7]~22_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(\z80_|reg_file_|db_lo_as[7]~22_combout ), + .datab(gnd), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [7]), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[7]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[7]~23 .lut_mask = 16'hAA0A; +defparam \z80_|reg_file_|db_lo_as[7]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N12 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~24 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[7]~24_combout = ((\z80_|reg_file_|db_lo_as[7]~23_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), + .datab(\z80_|reg_file_|db_lo_as[7]~23_combout ), + .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[7]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[7]~24 .lut_mask = 16'h8FCF; +defparam \z80_|reg_file_|db_lo_as[7]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N6 +cycloneive_lcell_comb \z80_|address_latch_|abusz[7] ( +// Equation(s): +// \z80_|address_latch_|abusz [7] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[7]~24_combout ) + + .dataa(\z80_|resets_|clrpc~0_combout ), + .datab(gnd), + .datac(\z80_|reg_file_|db_lo_as[7]~24_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [7]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[7] .lut_mask = 16'h5050; +defparam \z80_|address_latch_|abusz[7] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N16 +cycloneive_lcell_comb \z80_|address_latch_|Q[7]~feeder ( +// Equation(s): +// \z80_|address_latch_|Q[7]~feeder_combout = \z80_|address_latch_|abusz [7] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [7]), + .cin(gnd), + .combout(\z80_|address_latch_|Q[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|Q[7]~feeder .lut_mask = 16'hFF00; +defparam \z80_|address_latch_|Q[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y13_N17 +dffeas \z80_|address_latch_|Q[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|Q[7]~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[7] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N10 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout = \z80_|address_latch_|Q [8] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout & (\z80_|execute_|ctl_inc_dec~11_combout $ (\z80_|address_latch_|Q [7]))))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), + .datab(\z80_|address_latch_|Q [8]), + .datac(\z80_|execute_|ctl_inc_dec~11_combout ), + .datad(\z80_|address_latch_|Q [7]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out .lut_mask = 16'hC66C; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y14_N23 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[0]~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X35_Y14_N29 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[0]~6_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N28 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~4 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[0]~4_combout = (\z80_|reg_control_|reg_sw_4d_hi~0_combout & (\z80_|reg_file_|gdfx_temp1[0]~30_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) + + .dataa(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [0]), + .datad(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[0]~4 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|db_hi_as[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N0 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~5 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[0]~5_combout = (\z80_|reg_file_|db_hi_as[0]~4_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [0]), + .datad(\z80_|reg_file_|db_hi_as[0]~4_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[0]~5 .lut_mask = 16'hF300; +defparam \z80_|reg_file_|db_hi_as[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N22 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~6 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[0]~6_combout = ((\z80_|reg_file_|db_hi_as[0]~5_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), + .datab(\z80_|reg_file_|db_hi_as[0]~5_combout ), + .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[0]~6 .lut_mask = 16'h8FCF; +defparam \z80_|reg_file_|db_hi_as[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y14_N27 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X37_Y14_N13 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~23 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~23_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (\z80_|reg_file_|b2v_latch_hl_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_hl2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (((\z80_|reg_file_|b2v_latch_hl2_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [0]), + .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~23 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[0]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y16_N27 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X35_Y16_N5 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~25 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~25_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_iy_hi|latch [0]), + .datad(\z80_|reg_file_|b2v_latch_ix_hi|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~25 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[0]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y15_N11 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X35_Y15_N13 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~27 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~27_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (\z80_|reg_file_|b2v_latch_wz_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (((\z80_|reg_file_|b2v_latch_sp_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .datab(\z80_|reg_file_|b2v_latch_wz_hi|latch [0]), + .datac(\z80_|reg_file_|b2v_latch_sp_hi|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~27 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[0]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y16_N27 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X37_Y16_N25 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~24 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~24_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (\z80_|reg_file_|b2v_latch_bc2_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc_hi|latch [0]), + .datad(\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~24 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[0]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y16_N27 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~26 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~26_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout & (\z80_|alu_|db[0]~14_combout & ((\z80_|reg_file_|b2v_latch_af2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # +// (!\z80_|execute_|ctl_reg_in_hi~12_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .datab(\z80_|alu_|db[0]~14_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~26 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[0]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~28 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~28_combout = (\z80_|reg_file_|gdfx_temp1[0]~25_combout & (\z80_|reg_file_|gdfx_temp1[0]~27_combout & (\z80_|reg_file_|gdfx_temp1[0]~24_combout & \z80_|reg_file_|gdfx_temp1[0]~26_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~25_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[0]~27_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~24_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[0]~26_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~28 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[0]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y15_N17 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N16 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[0]~11 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[0]~11_combout = (\z80_|execute_|ctl_reg_gp_we~8_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [0]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [0]), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[0]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[0]~11 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[0]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y15_N11 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N16 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_hi|latch[0]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_de_hi|latch[0]~feeder_combout = \z80_|reg_file_|gdfx_temp1[0]~30_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_de_hi|latch[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[0]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y15_N17 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_de_hi|latch[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~22 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~22_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [0]), + .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~22 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[0]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~29 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~29_combout = (\z80_|reg_file_|gdfx_temp1[0]~23_combout & (\z80_|reg_file_|gdfx_temp1[0]~28_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[0]~11_combout & \z80_|reg_file_|gdfx_temp1[0]~22_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~23_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[0]~28_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|db[0]~11_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[0]~22_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~29 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[0]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~30 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~30_combout = ((\z80_|reg_file_|gdfx_temp1[0]~29_combout & ((\z80_|reg_file_|db_hi_as[0]~6_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[0]~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[0]~29_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datad(\z80_|execute_|ctl_sw_4u~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~30 .lut_mask = 16'h8FCF; +defparam \z80_|reg_file_|gdfx_temp1[0]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N12 +cycloneive_lcell_comb \z80_|alu_|db[0]~13 ( +// Equation(s): +// \z80_|alu_|db[0]~13_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[0]~30_combout & ((\z80_|alu_|db_low[0]~24_combout ) # (!\z80_|execute_|ctl_alu_oe~11_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & +// (((\z80_|alu_|db_low[0]~24_combout ) # (!\z80_|execute_|ctl_alu_oe~11_combout )))) + + .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .datac(\z80_|alu_|db_low[0]~24_combout ), + .datad(\z80_|execute_|ctl_alu_oe~11_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[0]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[0]~13 .lut_mask = 16'hD0DD; +defparam \z80_|alu_|db[0]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N22 +cycloneive_lcell_comb \z80_|alu_|db[0]~14 ( +// Equation(s): +// \z80_|alu_|db[0]~14_combout = ((\z80_|alu_|db[0]~13_combout & ((\z80_|alu_control_|db[0]~12_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|alu_control_|db[0]~12_combout ), + .datab(\z80_|alu_|db[7]~9_combout ), + .datac(\z80_|execute_|ctl_sw_2d~13_combout ), + .datad(\z80_|alu_|db[0]~13_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[0]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[0]~14 .lut_mask = 16'hBF33; +defparam \z80_|alu_|db[0]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N12 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~10 ( +// Equation(s): +// \z80_|alu_|db_low[1]~10_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[2]~16_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[0]~14_combout ))) + + .dataa(\z80_|alu_|db[2]~16_combout ), + .datab(\z80_|alu_|db[0]~14_combout ), + .datac(gnd), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~10 .lut_mask = 16'hAACC; +defparam \z80_|alu_|db_low[1]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N10 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~11 ( +// Equation(s): +// \z80_|alu_|db_low[1]~11_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_low[1]~10_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[1]~10_combout )) + + .dataa(\z80_|alu_|db[1]~10_combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .datac(gnd), + .datad(\z80_|alu_|db_low[1]~10_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~11 .lut_mask = 16'hEE22; +defparam \z80_|alu_|db_low[1]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N22 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~8 ( +// Equation(s): +// \z80_|alu_|db_low[1]~8_combout = (\z80_|execute_|ctl_alu_op2_oe~0_combout & (\z80_|alu_|op2_low [1] & ((\z80_|alu_|op1_low [1]) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout & (((\z80_|alu_|op1_low [1]) # +// (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datab(\z80_|alu_|op2_low [1]), + .datac(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datad(\z80_|alu_|op1_low [1]), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~8 .lut_mask = 16'hDD0D; +defparam \z80_|alu_|db_low[1]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N2 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~7 ( +// Equation(s): +// \z80_|alu_|db_low[1]~7_combout = ((\z80_|bus_control_|db[3]~21_combout & (!\z80_|bus_control_|db[5]~15_combout & !\z80_|bus_control_|db[4]~19_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) + + .dataa(\z80_|bus_control_|db[3]~21_combout ), + .datab(\z80_|bus_control_|db[5]~15_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datad(\z80_|bus_control_|db[4]~19_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~7 .lut_mask = 16'h0F2F; +defparam \z80_|alu_|db_low[1]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N4 +cycloneive_lcell_comb \z80_|alu_|result_lo[1]~feeder ( +// Equation(s): +// \z80_|alu_|result_lo[1]~feeder_combout = \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|result_lo[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|result_lo[1]~feeder .lut_mask = 16'hFF00; +defparam \z80_|alu_|result_lo[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y18_N5 +dffeas \z80_|alu_|result_lo[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|result_lo[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_alu_op_low~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|result_lo [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|result_lo[1] .is_wysiwyg = "true"; +defparam \z80_|alu_|result_lo[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N4 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~9 ( +// Equation(s): +// \z80_|alu_|db_low[1]~9_combout = (\z80_|alu_|db_low[1]~8_combout & (\z80_|alu_|db_low[1]~7_combout & ((\z80_|execute_|ctl_alu_res_oe~3_combout ) # (\z80_|alu_|result_lo [1])))) + + .dataa(\z80_|alu_|db_low[1]~8_combout ), + .datab(\z80_|alu_|db_low[1]~7_combout ), + .datac(\z80_|execute_|ctl_alu_res_oe~3_combout ), + .datad(\z80_|alu_|result_lo [1]), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~9 .lut_mask = 16'h8880; +defparam \z80_|alu_|db_low[1]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N26 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~12 ( +// Equation(s): +// \z80_|alu_|db_low[1]~12_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout & (\z80_|alu_|db_low[1]~11_combout & ((\z80_|alu_|db_low[1]~9_combout )))) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout & (((\z80_|alu_|db_low[1]~9_combout ) # +// (!\z80_|alu_|db_high[3]~0_combout )))) + + .dataa(\z80_|alu_|db_low[1]~11_combout ), + .datab(\z80_|alu_|db_high[3]~0_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datad(\z80_|alu_|db_low[1]~9_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~12 .lut_mask = 16'hAF03; +defparam \z80_|alu_|db_low[1]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N2 +cycloneive_lcell_comb \z80_|alu_|db[1]~8 ( +// Equation(s): +// \z80_|alu_|db[1]~8_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[1]~21_combout & ((\z80_|alu_control_|db[1]~26_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & +// (((\z80_|alu_control_|db[1]~26_combout )) # (!\z80_|execute_|ctl_sw_2d~13_combout ))) + + .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .datab(\z80_|execute_|ctl_sw_2d~13_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .datad(\z80_|alu_control_|db[1]~26_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[1]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[1]~8 .lut_mask = 16'hF531; +defparam \z80_|alu_|db[1]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N18 +cycloneive_lcell_comb \z80_|alu_|db[1]~10 ( +// Equation(s): +// \z80_|alu_|db[1]~10_combout = ((\z80_|alu_|db[1]~8_combout & ((\z80_|alu_|db_low[1]~12_combout ) # (!\z80_|execute_|ctl_alu_oe~11_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|execute_|ctl_alu_oe~11_combout ), + .datab(\z80_|alu_|db[7]~9_combout ), + .datac(\z80_|alu_|db_low[1]~12_combout ), + .datad(\z80_|alu_|db[1]~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[1]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[1]~10 .lut_mask = 16'hF733; +defparam \z80_|alu_|db[1]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y16_N11 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~12 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~12_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout & (\z80_|alu_|db[1]~10_combout & ((\z80_|reg_file_|b2v_latch_af2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # +// (!\z80_|execute_|ctl_reg_in_hi~12_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .datab(\z80_|alu_|db[1]~10_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~12 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[1]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N4 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder_combout = \z80_|reg_file_|gdfx_temp1[1]~21_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y16_N5 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X35_Y16_N1 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~11 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~11_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datab(\z80_|reg_file_|b2v_latch_iy_hi|latch [1]), + .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~11 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[1]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y16_N11 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X37_Y16_N17 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~10 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~10_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (\z80_|reg_file_|b2v_latch_bc2_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]), + .datad(\z80_|reg_file_|b2v_latch_bc_hi|latch [1]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~10 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[1]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y15_N3 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X35_Y15_N1 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~13 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~13_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (\z80_|reg_file_|b2v_latch_wz_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [1]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [1]), + .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~13 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp1[1]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~14 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~14_combout = (\z80_|reg_file_|gdfx_temp1[1]~12_combout & (\z80_|reg_file_|gdfx_temp1[1]~11_combout & (\z80_|reg_file_|gdfx_temp1[1]~10_combout & \z80_|reg_file_|gdfx_temp1[1]~13_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[1]~12_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[1]~11_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[1]~10_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[1]~13_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~14 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[1]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y15_N25 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N24 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[1]~10 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[1]~10_combout = (\z80_|execute_|ctl_reg_gp_we~8_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [1]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [1]), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[1]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[1]~10 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[1]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y14_N29 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X37_Y14_N11 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~9 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~9_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (\z80_|reg_file_|b2v_latch_hl_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_hl2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (((\z80_|reg_file_|b2v_latch_hl2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [1]), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~9 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[1]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y15_N7 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N20 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_hi|latch[1]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_de_hi|latch[1]~feeder_combout = \z80_|reg_file_|gdfx_temp1[1]~21_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_de_hi|latch[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[1]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y15_N21 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_de_hi|latch[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~8 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~8_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [1]), + .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [1]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~8 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[1]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~15 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~15_combout = (\z80_|reg_file_|gdfx_temp1[1]~14_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[1]~10_combout & (\z80_|reg_file_|gdfx_temp1[1]~9_combout & \z80_|reg_file_|gdfx_temp1[1]~8_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[1]~14_combout ), + .datab(\z80_|reg_file_|b2v_latch_af_hi|db[1]~10_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[1]~9_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[1]~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~15 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~21 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~21_combout = ((\z80_|reg_file_|gdfx_temp1[1]~15_combout & ((\z80_|reg_file_|db_hi_as[1]~3_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[1]~15_combout ), + .datac(\z80_|reg_file_|db_hi_as[1]~3_combout ), + .datad(\z80_|execute_|ctl_sw_4u~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~21 .lut_mask = 16'hD5DD; +defparam \z80_|reg_file_|gdfx_temp1[1]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y14_N25 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[1]~3_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N24 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~0 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[1]~0_combout = (\z80_|reg_file_|gdfx_temp1[1]~21_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # (!\z80_|reg_file_|gdfx_temp1[1]~21_combout & +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[1]~0 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|db_hi_as[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N20 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~1 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[1]~1_combout = (\z80_|reg_file_|db_hi_as[1]~0_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_pc_hi|latch [1]), + .datab(\z80_|reg_file_|db_hi_as[1]~0_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[1]~1 .lut_mask = 16'h88CC; +defparam \z80_|reg_file_|db_hi_as[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N30 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~3 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[1]~3_combout = ((\z80_|reg_file_|db_hi_as[1]~1_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), + .datab(\z80_|reg_file_|db_hi_as[1]~1_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .datad(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[1]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[1]~3 .lut_mask = 16'h8CFF; +defparam \z80_|reg_file_|db_hi_as[1]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N24 +cycloneive_lcell_comb \z80_|address_latch_|abusz[9] ( +// Equation(s): +// \z80_|address_latch_|abusz [9] = (\z80_|reg_file_|db_hi_as[1]~3_combout & !\z80_|resets_|clrpc~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|reg_file_|db_hi_as[1]~3_combout ), + .datad(\z80_|resets_|clrpc~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [9]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[9] .lut_mask = 16'h00F0; +defparam \z80_|address_latch_|abusz[9] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N22 +cycloneive_lcell_comb \z80_|address_latch_|Q[9]~feeder ( +// Equation(s): +// \z80_|address_latch_|Q[9]~feeder_combout = \z80_|address_latch_|abusz [9] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [9]), + .cin(gnd), + .combout(\z80_|address_latch_|Q[9]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|Q[9]~feeder .lut_mask = 16'hFF00; +defparam \z80_|address_latch_|Q[9]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y10_N23 +dffeas \z80_|address_latch_|Q[9] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|Q[9]~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [9]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[9] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N26 +cycloneive_lcell_comb \z80_|address_latch_|abusz[10] ( +// Equation(s): +// \z80_|address_latch_|abusz [10] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[2]~9_combout ) + + .dataa(\z80_|resets_|clrpc~0_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|db_hi_as[2]~9_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [10]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[10] .lut_mask = 16'h5500; +defparam \z80_|address_latch_|abusz[10] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y13_N27 +dffeas \z80_|address_latch_|Q[10] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [10]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [10]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[10] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N12 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout = \z80_|address_latch_|Q [10] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout & (\z80_|execute_|ctl_inc_dec~11_combout $ +// (\z80_|address_latch_|Q [9]))))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), + .datab(\z80_|execute_|ctl_inc_dec~11_combout ), + .datac(\z80_|address_latch_|Q [9]), + .datad(\z80_|address_latch_|Q [10]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out .lut_mask = 16'hD728; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y14_N13 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[2]~9_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N12 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~7 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[2]~7_combout = (\z80_|reg_file_|gdfx_temp1[2]~39_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # (!\z80_|reg_file_|gdfx_temp1[2]~39_combout & +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[2]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[2]~7 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|db_hi_as[2]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y14_N19 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[2]~9_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N8 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~8 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[2]~8_combout = (\z80_|reg_file_|db_hi_as[2]~7_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|db_hi_as[2]~7_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datac(gnd), + .datad(\z80_|reg_file_|b2v_latch_pc_hi|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[2]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[2]~8 .lut_mask = 16'hAA22; +defparam \z80_|reg_file_|db_hi_as[2]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N18 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~9 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[2]~9_combout = ((\z80_|reg_file_|db_hi_as[2]~8_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .datac(\z80_|reg_file_|db_hi_as[2]~8_combout ), + .datad(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[2]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[2]~9 .lut_mask = 16'hB0FF; +defparam \z80_|reg_file_|db_hi_as[2]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~39 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~39_combout = ((\z80_|reg_file_|gdfx_temp1[2]~38_combout & ((\z80_|reg_file_|db_hi_as[2]~9_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[2]~38_combout ), + .datac(\z80_|reg_file_|db_hi_as[2]~9_combout ), + .datad(\z80_|execute_|ctl_sw_4u~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~39 .lut_mask = 16'hD5DD; +defparam \z80_|reg_file_|gdfx_temp1[2]~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N24 +cycloneive_lcell_comb \z80_|alu_|db[2]~15 ( +// Equation(s): +// \z80_|alu_|db[2]~15_combout = (\z80_|execute_|ctl_sw_2d~13_combout & (\z80_|alu_control_|db[2]~29_combout & ((\z80_|reg_file_|gdfx_temp1[2]~39_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) # (!\z80_|execute_|ctl_sw_2d~13_combout & +// ((\z80_|reg_file_|gdfx_temp1[2]~39_combout ) # ((!\z80_|execute_|ctl_reg_out_hi~7_combout )))) + + .dataa(\z80_|execute_|ctl_sw_2d~13_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .datac(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .datad(\z80_|alu_control_|db[2]~29_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[2]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[2]~15 .lut_mask = 16'hCF45; +defparam \z80_|alu_|db[2]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N4 +cycloneive_lcell_comb \z80_|alu_|db[2]~16 ( +// Equation(s): +// \z80_|alu_|db[2]~16_combout = ((\z80_|alu_|db[2]~15_combout & ((\z80_|alu_|db_low[2]~23_combout ) # (!\z80_|execute_|ctl_alu_oe~11_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|execute_|ctl_alu_oe~11_combout ), + .datab(\z80_|alu_|db[2]~15_combout ), + .datac(\z80_|alu_|db[7]~9_combout ), + .datad(\z80_|alu_|db_low[2]~23_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[2]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[2]~16 .lut_mask = 16'hCF4F; +defparam \z80_|alu_|db[2]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N24 +cycloneive_lcell_comb \z80_|alu_control_|db[2]~27 ( +// Equation(s): +// \z80_|alu_control_|db[2]~27_combout = (\z80_|alu_|db[2]~16_combout & (!\z80_|alu_flags_|DFFE_inst_latch_pf~q & ((\z80_|execute_|ctl_flags_oe~2_combout )))) # (!\z80_|alu_|db[2]~16_combout & ((\z80_|execute_|ctl_sw_2u~7_combout ) # +// ((!\z80_|alu_flags_|DFFE_inst_latch_pf~q & \z80_|execute_|ctl_flags_oe~2_combout )))) + + .dataa(\z80_|alu_|db[2]~16_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), + .datac(\z80_|execute_|ctl_sw_2u~7_combout ), + .datad(\z80_|execute_|ctl_flags_oe~2_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[2]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[2]~27 .lut_mask = 16'h7350; +defparam \z80_|alu_control_|db[2]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N0 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~2 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf~2_combout = (\z80_|execute_|ctl_flags_alu~15_combout & !\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_flags_alu~15_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~2 .lut_mask = 16'h0C0C; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N26 +cycloneive_lcell_comb \z80_|alu_flags_|flags_hf2~0 ( +// Equation(s): +// \z80_|alu_flags_|flags_hf2~0_combout = (\z80_|execute_|ctl_flags_hf2_we~combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ) # ((\z80_|alu_control_|db[4]~32_combout )))) # (!\z80_|execute_|ctl_flags_hf2_we~combout & +// (((\z80_|alu_flags_|flags_hf2~q )))) + + .dataa(\z80_|execute_|ctl_flags_hf2_we~combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ), + .datac(\z80_|alu_flags_|flags_hf2~q ), + .datad(\z80_|alu_control_|db[4]~32_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|flags_hf2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|flags_hf2~0 .lut_mask = 16'hFAD8; +defparam \z80_|alu_flags_|flags_hf2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y18_N27 +dffeas \z80_|alu_flags_|flags_hf2 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|flags_hf2~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|flags_hf2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|flags_hf2 .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|flags_hf2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N30 +cycloneive_lcell_comb \z80_|alu_control_|db[2]~23 ( +// Equation(s): +// \z80_|alu_control_|db[2]~23_combout = ((\z80_|alu_flags_|flags_hf2~q ) # ((\z80_|alu_control_|out[6]~0_combout ) # (\z80_|execute_|ctl_66_oe~combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datab(\z80_|alu_flags_|flags_hf2~q ), + .datac(\z80_|alu_control_|out[6]~0_combout ), + .datad(\z80_|execute_|ctl_66_oe~combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[2]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[2]~23 .lut_mask = 16'hFFFD; +defparam \z80_|alu_control_|db[2]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N30 +cycloneive_lcell_comb \z80_|alu_control_|db[2]~29 ( +// Equation(s): +// \z80_|alu_control_|db[2]~29_combout = ((\z80_|alu_control_|db[2]~28_combout & (!\z80_|alu_control_|db[2]~27_combout & \z80_|alu_control_|db[2]~23_combout ))) # (!\z80_|alu_control_|db[6]~11_combout ) + + .dataa(\z80_|alu_control_|db[2]~28_combout ), + .datab(\z80_|alu_control_|db[2]~27_combout ), + .datac(\z80_|alu_control_|db[2]~23_combout ), + .datad(\z80_|alu_control_|db[6]~11_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[2]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[2]~29 .lut_mask = 16'h20FF; +defparam \z80_|alu_control_|db[2]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~39 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~39_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout & (\z80_|alu_control_|db[2]~29_combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) # +// (!\z80_|execute_|ctl_reg_in_lo~8_combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [2]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datab(\z80_|reg_file_|b2v_latch_sp_lo|latch [2]), + .datac(\z80_|alu_control_|db[2]~29_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~39 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[2]~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y11_N3 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X32_Y11_N21 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~35 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~35_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [2]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~35 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[2]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~40 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~40_combout = (\z80_|reg_file_|gdfx_temp0[2]~37_combout & (\z80_|reg_file_|gdfx_temp0[2]~38_combout & (\z80_|reg_file_|gdfx_temp0[2]~39_combout & \z80_|reg_file_|gdfx_temp0[2]~35_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[2]~37_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[2]~38_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[2]~39_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[2]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~40 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[2]~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~41 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~41_combout = (\z80_|reg_file_|gdfx_temp0[2]~33_combout & (\z80_|reg_file_|gdfx_temp0[2]~34_combout & \z80_|reg_file_|gdfx_temp0[2]~40_combout )) + + .dataa(\z80_|reg_file_|gdfx_temp0[2]~33_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[2]~34_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[2]~40_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~41 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|gdfx_temp0[2]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~42 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~42_combout = ((\z80_|reg_file_|gdfx_temp0[2]~41_combout & ((\z80_|reg_file_|db_lo_as[2]~9_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .datad(\z80_|reg_file_|db_lo_as[2]~9_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~42 .lut_mask = 16'hCF4F; +defparam \z80_|reg_file_|gdfx_temp0[2]~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y12_N15 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[2]~9_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N14 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~7 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[2]~7_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[2]~42_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # +// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[2]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[2]~7 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_lo_as[2]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N6 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~8 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[2]~8_combout = (\z80_|reg_file_|db_lo_as[2]~7_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_ir_lo|latch [2]), + .datab(gnd), + .datac(\z80_|reg_file_|db_lo_as[2]~7_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[2]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[2]~8 .lut_mask = 16'hA0F0; +defparam \z80_|reg_file_|db_lo_as[2]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N4 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout = \z80_|address_latch_|Q [0] $ (((\z80_|execute_|ctl_inc_dec~9_combout ) # ((\z80_|execute_|ctl_inc_dec~7_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout )))) + + .dataa(\z80_|execute_|ctl_inc_dec~9_combout ), + .datab(\z80_|address_latch_|Q [0]), + .datac(\z80_|execute_|ctl_inc_dec~6_combout ), + .datad(\z80_|execute_|ctl_inc_dec~7_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 .lut_mask = 16'h3363; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N26 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout & ((\z80_|execute_|ctl_inc_cy~71_combout ) # ((\z80_|execute_|ctl_inc_cy~81_combout ) # +// (\z80_|execute_|ctl_inc_cy~68_combout )))) + + .dataa(\z80_|execute_|ctl_inc_cy~71_combout ), + .datab(\z80_|execute_|ctl_inc_cy~81_combout ), + .datac(\z80_|execute_|ctl_inc_cy~68_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'hFE00; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N0 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout = \z80_|address_latch_|Q [2] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout & +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout ))) + + .dataa(\z80_|address_latch_|Q [2]), + .datab(gnd), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out .lut_mask = 16'h5AAA; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N8 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~9 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[2]~9_combout = ((\z80_|reg_file_|db_lo_as[2]~8_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|reg_file_|db_lo_as[2]~8_combout ), + .datab(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[2]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[2]~9 .lut_mask = 16'hBB3B; +defparam \z80_|reg_file_|db_lo_as[2]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N8 +cycloneive_lcell_comb \z80_|address_latch_|abusz[2] ( +// Equation(s): +// \z80_|address_latch_|abusz [2] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[2]~9_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(\z80_|reg_file_|db_lo_as[2]~9_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [2]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[2] .lut_mask = 16'h0F00; +defparam \z80_|address_latch_|abusz[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y11_N9 +dffeas \z80_|address_latch_|Q[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [2]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[2] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N18 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout = \z80_|address_latch_|Q [2] $ ((((\z80_|execute_|ctl_inc_dec~10_combout ) # (!\z80_|execute_|ctl_inc_dec~5_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~42_combout ))) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~42_combout ), + .datab(\z80_|address_latch_|Q [2]), + .datac(\z80_|execute_|ctl_inc_dec~10_combout ), + .datad(\z80_|execute_|ctl_inc_dec~5_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42 .lut_mask = 16'h3933; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y12_N25 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[3]~12_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N24 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~10 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[3]~10_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[3]~52_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # +// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[3]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[3]~10 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_lo_as[3]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y12_N31 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[3]~12_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N28 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~11 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[3]~11_combout = (\z80_|reg_file_|db_lo_as[3]~10_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .datab(\z80_|reg_file_|db_lo_as[3]~10_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [3]), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[3]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[3]~11 .lut_mask = 16'hCC44; +defparam \z80_|reg_file_|db_lo_as[3]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N26 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout = \z80_|address_latch_|Q [3] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout & +// (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout )))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout ), + .datab(\z80_|address_latch_|Q [3]), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out .lut_mask = 16'h6CCC; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N30 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~12 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[3]~12_combout = ((\z80_|reg_file_|db_lo_as[3]~11_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .datab(\z80_|reg_file_|db_lo_as[3]~11_combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), + .datad(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[3]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[3]~12 .lut_mask = 16'hC4FF; +defparam \z80_|reg_file_|db_lo_as[3]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N14 +cycloneive_lcell_comb \z80_|address_latch_|abusz[3] ( +// Equation(s): +// \z80_|address_latch_|abusz [3] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[3]~12_combout ) + + .dataa(gnd), + .datab(\z80_|resets_|clrpc~0_combout ), + .datac(\z80_|reg_file_|db_lo_as[3]~12_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [3]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[3] .lut_mask = 16'h3030; +defparam \z80_|address_latch_|abusz[3] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y11_N15 +dffeas \z80_|address_latch_|Q[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [3]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[3] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N24 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout = \z80_|address_latch_|Q [3] $ ((((\z80_|execute_|ctl_inc_dec~10_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~42_combout )) # (!\z80_|execute_|ctl_inc_dec~5_combout ))) + + .dataa(\z80_|execute_|ctl_inc_dec~5_combout ), + .datab(\z80_|address_latch_|Q [3]), + .datac(\z80_|execute_|ctl_inc_dec~10_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~42_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4 .lut_mask = 16'h3933; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N10 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout & +// (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout ))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 .lut_mask = 16'h8000; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N16 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout = (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|address_latch_|Q [6] $ (((\z80_|execute_|ctl_inc_dec~7_combout ) # (\z80_|execute_|ctl_inc_dec~10_combout ))))) + + .dataa(\z80_|address_latch_|Q [6]), + .datab(\z80_|execute_|ctl_inc_dec~7_combout ), + .datac(\z80_|execute_|ctl_inc_dec~10_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 .lut_mask = 16'h0056; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N14 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout & +// (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 .lut_mask = 16'h8000; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N22 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout & ((\z80_|address_latch_|Q [8] & (!\z80_|execute_|ctl_inc_dec~11_combout & \z80_|address_latch_|Q +// [7])) # (!\z80_|address_latch_|Q [8] & (\z80_|execute_|ctl_inc_dec~11_combout & !\z80_|address_latch_|Q [7])))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), + .datab(\z80_|address_latch_|Q [8]), + .datac(\z80_|execute_|ctl_inc_dec~11_combout ), + .datad(\z80_|address_latch_|Q [7]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 .lut_mask = 16'h0820; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N28 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout & ((\z80_|execute_|ctl_inc_dec~11_combout & (!\z80_|address_latch_|Q [9] & +// !\z80_|address_latch_|Q [10])) # (!\z80_|execute_|ctl_inc_dec~11_combout & (\z80_|address_latch_|Q [9] & \z80_|address_latch_|Q [10])))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), + .datab(\z80_|execute_|ctl_inc_dec~11_combout ), + .datac(\z80_|address_latch_|Q [9]), + .datad(\z80_|address_latch_|Q [10]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 .lut_mask = 16'h2008; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N26 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[11] ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|address [11] = \z80_|address_latch_|Q [11] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|address_latch_|Q [11]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[11] .lut_mask = 16'h0FF0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[11] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N4 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~12 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[3]~12_combout = ((\z80_|reg_file_|db_hi_as[3]~11_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [11]) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .datac(\z80_|reg_file_|db_hi_as[3]~11_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[3]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[3]~12 .lut_mask = 16'hF575; +defparam \z80_|reg_file_|db_hi_as[3]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y14_N17 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X37_Y14_N31 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~41 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~41_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (\z80_|reg_file_|b2v_latch_hl_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_hl2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (((\z80_|reg_file_|b2v_latch_hl2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [3]), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~41 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[3]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y15_N5 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X35_Y15_N7 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~45 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~45_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (\z80_|reg_file_|b2v_latch_wz_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (((\z80_|reg_file_|b2v_latch_sp_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [3]), + .datad(\z80_|reg_file_|b2v_latch_sp_hi|latch [3]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~45 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[3]~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y16_N23 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~44 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~44_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout & (\z80_|alu_|db[3]~20_combout & ((\z80_|reg_file_|b2v_latch_af2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # +// (!\z80_|execute_|ctl_reg_in_hi~12_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .datab(\z80_|alu_|db[3]~20_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~44 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[3]~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y16_N19 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y16_N9 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~43 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~43_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [3]), + .datad(\z80_|reg_file_|b2v_latch_iy_hi|latch [3]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~43 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[3]~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y16_N9 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X37_Y16_N7 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~42 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~42_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (\z80_|reg_file_|b2v_latch_bc2_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [3]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_bc_hi|latch [3]), + .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~42 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp1[3]~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~46 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~46_combout = (\z80_|reg_file_|gdfx_temp1[3]~45_combout & (\z80_|reg_file_|gdfx_temp1[3]~44_combout & (\z80_|reg_file_|gdfx_temp1[3]~43_combout & \z80_|reg_file_|gdfx_temp1[3]~42_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[3]~45_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[3]~44_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[3]~43_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[3]~42_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~46 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[3]~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N8 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_hi|latch[3]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_de_hi|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp1[3]~48_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_de_hi|latch[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[3]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y15_N9 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_de_hi|latch[3]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X37_Y15_N27 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~40 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~40_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datab(\z80_|reg_file_|b2v_latch_de_hi|latch [3]), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~40 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[3]~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y15_N21 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N10 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[3]~13 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[3]~13_combout = (\z80_|execute_|ctl_reg_gp_we~8_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [3]) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout )) # (!\z80_|reg_control_|reg_sel_af~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(\z80_|reg_control_|reg_sel_af~0_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datad(\z80_|reg_file_|b2v_latch_af_hi|latch [3]), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[3]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[3]~13 .lut_mask = 16'hFFBF; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[3]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~47 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~47_combout = (\z80_|reg_file_|gdfx_temp1[3]~41_combout & (\z80_|reg_file_|gdfx_temp1[3]~46_combout & (\z80_|reg_file_|gdfx_temp1[3]~40_combout & \z80_|reg_file_|b2v_latch_af_hi|db[3]~13_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[3]~41_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[3]~46_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[3]~40_combout ), + .datad(\z80_|reg_file_|b2v_latch_af_hi|db[3]~13_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~47 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[3]~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~48 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~48_combout = ((\z80_|reg_file_|gdfx_temp1[3]~47_combout & ((\z80_|reg_file_|db_hi_as[3]~12_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[3]~12_combout ), + .datab(\z80_|execute_|ctl_sw_4u~6_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[3]~47_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~48 .lut_mask = 16'hBF0F; +defparam \z80_|reg_file_|gdfx_temp1[3]~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N6 +cycloneive_lcell_comb \z80_|alu_|db[3]~19 ( +// Equation(s): +// \z80_|alu_|db[3]~19_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[3]~48_combout & ((\z80_|alu_|db_low[3]~25_combout ) # (!\z80_|execute_|ctl_alu_oe~11_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & +// ((\z80_|alu_|db_low[3]~25_combout ) # ((!\z80_|execute_|ctl_alu_oe~11_combout )))) + + .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .datab(\z80_|alu_|db_low[3]~25_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .datad(\z80_|execute_|ctl_alu_oe~11_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[3]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[3]~19 .lut_mask = 16'hC4F5; +defparam \z80_|alu_|db[3]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N28 +cycloneive_lcell_comb \z80_|alu_|db[3]~20 ( +// Equation(s): +// \z80_|alu_|db[3]~20_combout = ((\z80_|alu_|db[3]~19_combout & ((\z80_|alu_control_|db[3]~35_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|alu_control_|db[3]~35_combout ), + .datab(\z80_|alu_|db[7]~9_combout ), + .datac(\z80_|execute_|ctl_sw_2d~13_combout ), + .datad(\z80_|alu_|db[3]~19_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[3]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[3]~20 .lut_mask = 16'hBF33; +defparam \z80_|alu_|db[3]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N18 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~21 ( +// Equation(s): +// \z80_|alu_|db_low[2]~21_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[3]~20_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[1]~10_combout ))) + + .dataa(\z80_|alu_|db[3]~20_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(gnd), + .datad(\z80_|alu_|db[1]~10_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[2]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[2]~21 .lut_mask = 16'hBB88; +defparam \z80_|alu_|db_low[2]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N12 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~22 ( +// Equation(s): +// \z80_|alu_|db_low[2]~22_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_low[2]~21_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[2]~16_combout ))) + + .dataa(gnd), + .datab(\z80_|alu_|db_low[2]~21_combout ), + .datac(\z80_|alu_|db[2]~16_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[2]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[2]~22 .lut_mask = 16'hCCF0; +defparam \z80_|alu_|db_low[2]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y17_N1 +dffeas \z80_|alu_|result_lo[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_alu_op_low~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|result_lo [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|result_lo[2] .is_wysiwyg = "true"; +defparam \z80_|alu_|result_lo[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N10 +cycloneive_lcell_comb \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 ( +// Equation(s): +// \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout = (\z80_|bus_control_|db[4]~19_combout & !\z80_|bus_control_|db[3]~21_combout ) + + .dataa(gnd), + .datab(\z80_|bus_control_|db[4]~19_combout ), + .datac(\z80_|bus_control_|db[3]~21_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 .lut_mask = 16'h0C0C; +defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N22 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~6 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~6_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [2])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [2]))))) + + .dataa(\z80_|alu_|op1_low [2]), + .datab(\z80_|execute_|ctl_alu_op_low~combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datad(\z80_|alu_|op1_high [2]), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~6 .lut_mask = 16'hB080; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N30 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~7 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~7_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~6_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~8_combout & \z80_|alu_|db_low[2]~23_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datac(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~6_combout ), + .datad(\z80_|alu_|db_low[2]~23_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~7 .lut_mask = 16'h3230; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y18_N31 +dffeas \z80_|alu_|op2_low[2] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~7_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_low [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_low[2] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_low[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N6 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~18 ( +// Equation(s): +// \z80_|alu_|db_low[2]~18_combout = (\z80_|execute_|ctl_alu_op2_oe~0_combout & (\z80_|alu_|op2_low [2] & ((\z80_|alu_|op1_low [2]) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_low [2]) # +// ((!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datab(\z80_|alu_|op1_low [2]), + .datac(\z80_|alu_|op2_low [2]), + .datad(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[2]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[2]~18 .lut_mask = 16'hC4F5; +defparam \z80_|alu_|db_low[2]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N22 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~19 ( +// Equation(s): +// \z80_|alu_|db_low[2]~19_combout = (\z80_|alu_|db_low[2]~18_combout & (((\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout & !\z80_|bus_control_|db[5]~15_combout )) # (!\z80_|execute_|ctl_alu_bs_oe~combout ))) + + .dataa(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), + .datab(\z80_|bus_control_|db[5]~15_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datad(\z80_|alu_|db_low[2]~18_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[2]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[2]~19 .lut_mask = 16'h2F00; +defparam \z80_|alu_|db_low[2]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N0 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~20 ( +// Equation(s): +// \z80_|alu_|db_low[2]~20_combout = (\z80_|alu_|db_low[2]~19_combout & ((\z80_|execute_|ctl_alu_res_oe~3_combout ) # (\z80_|alu_|result_lo [2]))) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_res_oe~3_combout ), + .datac(\z80_|alu_|result_lo [2]), + .datad(\z80_|alu_|db_low[2]~19_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[2]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[2]~20 .lut_mask = 16'hFC00; +defparam \z80_|alu_|db_low[2]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N2 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~23 ( +// Equation(s): +// \z80_|alu_|db_low[2]~23_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout & (\z80_|alu_|db_low[2]~22_combout & ((\z80_|alu_|db_low[2]~20_combout )))) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout & (((\z80_|alu_|db_low[2]~20_combout ) # +// (!\z80_|alu_|db_high[3]~0_combout )))) + + .dataa(\z80_|alu_|db_low[2]~22_combout ), + .datab(\z80_|alu_|db_high[3]~0_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datad(\z80_|alu_|db_low[2]~20_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[2]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[2]~23 .lut_mask = 16'hAF03; +defparam \z80_|alu_|db_low[2]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N2 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~7 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~7_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & ((\z80_|alu_|db_low[2]~23_combout ) # ((\z80_|alu_|db_high[2]~13_combout & \z80_|execute_|ctl_alu_op1_sel_low~combout )))) # +// (!\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & (((\z80_|alu_|db_high[2]~13_combout & \z80_|execute_|ctl_alu_op1_sel_low~combout )))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datab(\z80_|alu_|db_low[2]~23_combout ), + .datac(\z80_|alu_|db_high[2]~13_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~7 .lut_mask = 16'hF888; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N10 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~8 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~8_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~7_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .datad(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~7_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~8 .lut_mask = 16'h0F00; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y17_N11 +dffeas \z80_|alu_|op1_low[2] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~8_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_low [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_low[2] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_low[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N26 +cycloneive_lcell_comb \z80_|alu_|alu_op1[2]~1 ( +// Equation(s): +// \z80_|alu_|alu_op1[2]~1_combout = (\z80_|execute_|ctl_alu_op_low~41_combout & (\z80_|alu_|op1_low [2])) # (!\z80_|execute_|ctl_alu_op_low~41_combout & ((\z80_|execute_|ctl_alu_op_low~29_combout & ((\z80_|alu_|op1_high [2]))) # +// (!\z80_|execute_|ctl_alu_op_low~29_combout & (\z80_|alu_|op1_low [2])))) + + .dataa(\z80_|alu_|op1_low [2]), + .datab(\z80_|execute_|ctl_alu_op_low~41_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~29_combout ), + .datad(\z80_|alu_|op1_high [2]), + .cin(gnd), + .combout(\z80_|alu_|alu_op1[2]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op1[2]~1 .lut_mask = 16'hBA8A; +defparam \z80_|alu_|alu_op1[2]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N30 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout = (\z80_|execute_|ctl_alu_core_S~combout ) # ((\z80_|alu_|alu_op1[2]~1_combout & \z80_|alu_|alu_op2[2]~0_combout )) + + .dataa(\z80_|alu_|alu_op1[2]~1_combout ), + .datab(gnd), + .datac(\z80_|alu_|alu_op2[2]~0_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hFFA0; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N8 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout = (!\z80_|alu_|alu_op2[2]~0_combout & ((\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_low [2])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_high +// [2]))))) + + .dataa(\z80_|alu_|alu_op2[2]~0_combout ), + .datab(\z80_|alu_|op1_low [2]), + .datac(\z80_|alu_|op1_high [2]), + .datad(\z80_|execute_|ctl_alu_op_low~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h1105; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N20 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout = (!\z80_|execute_|ctl_alu_core_R~combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ) # +// ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout & !\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout )))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), + .datab(\z80_|execute_|ctl_alu_core_R~combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 .lut_mask = 16'h3031; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N16 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ) # +// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), + .datab(\z80_|execute_|ctl_alu_core_R~combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 .lut_mask = 16'hDCDD; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N20 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout = (!\z80_|alu_|alu_op2[3]~2_combout & ((\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_low [3])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_high +// [3]))))) + + .dataa(\z80_|alu_|op1_low [3]), + .datab(\z80_|alu_|alu_op2[3]~2_combout ), + .datac(\z80_|alu_|op1_high [3]), + .datad(\z80_|execute_|ctl_alu_op_low~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h1103; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N10 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ) # +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout )))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .datac(\z80_|execute_|ctl_alu_core_R~combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0 .lut_mask = 16'hF5F4; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N6 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_hf~0 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_hf~0_combout = (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & (\z80_|execute_|ctl_flags_bus~combout & ((\z80_|alu_control_|db[4]~32_combout )))) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout +// & ((\z80_|execute_|ctl_flags_alu~15_combout ) # ((\z80_|execute_|ctl_flags_bus~combout & \z80_|alu_control_|db[4]~32_combout )))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), + .datab(\z80_|execute_|ctl_flags_bus~combout ), + .datac(\z80_|execute_|ctl_flags_alu~15_combout ), + .datad(\z80_|alu_control_|db[4]~32_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_hf~0 .lut_mask = 16'hDC50; +defparam \z80_|alu_flags_|DFFE_inst_latch_hf~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_we~3_combout = (\z80_|pla_decode_|Equal11~0_combout & (((\z80_|nM1_int~2_combout ) # (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) # (!\z80_|pla_decode_|Equal11~0_combout & (\z80_|pla_decode_|Equal10~0_combout & +// ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_we~3 .lut_mask = 16'hEEC0; +defparam \z80_|execute_|ctl_flags_hf_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_we~4_combout = ((\z80_|execute_|ctl_flags_sz_we~6_combout ) # ((\z80_|execute_|ctl_flags_hf_we~3_combout ) # (!\z80_|execute_|ctl_flags_alu~14_combout ))) # (!\z80_|execute_|ctl_flags_xy_we~8_combout ) + + .dataa(\z80_|execute_|ctl_flags_xy_we~8_combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~6_combout ), + .datac(\z80_|execute_|ctl_flags_alu~14_combout ), + .datad(\z80_|execute_|ctl_flags_hf_we~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_we~4 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|ctl_flags_hf_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N28 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_hf~1 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_hf~1_combout = (\z80_|execute_|ctl_flags_hf_we~2_combout & ((\z80_|execute_|ctl_flags_hf_we~4_combout & (\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout )) # (!\z80_|execute_|ctl_flags_hf_we~4_combout & +// ((\z80_|alu_flags_|DFFE_inst_latch_hf~q ))))) # (!\z80_|execute_|ctl_flags_hf_we~2_combout & (\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout )) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ), + .datab(\z80_|execute_|ctl_flags_hf_we~2_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), + .datad(\z80_|execute_|ctl_flags_hf_we~4_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_hf~1 .lut_mask = 16'hAAE2; +defparam \z80_|alu_flags_|DFFE_inst_latch_hf~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y18_N29 +dffeas \z80_|alu_flags_|DFFE_inst_latch_hf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_hf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_hf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N16 +cycloneive_lcell_comb \z80_|alu_flags_|flags_hf ( +// Equation(s): +// \z80_|alu_flags_|flags_hf~combout = \z80_|alu_flags_|DFFE_inst_latch_hf~q $ (((\z80_|execute_|ctl_flags_hf_cpl~13_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout & !\z80_|alu_flags_|flags_cf~combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .datab(\z80_|execute_|ctl_flags_hf_cpl~13_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), + .datad(\z80_|alu_flags_|flags_cf~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|flags_hf~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|flags_hf .lut_mask = 16'h3C1E; +defparam \z80_|alu_flags_|flags_hf .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N16 +cycloneive_lcell_comb \z80_|alu_control_|db[4]~30 ( +// Equation(s): +// \z80_|alu_control_|db[4]~30_combout = (\z80_|alu_|db[4]~18_combout & (!\z80_|reg_file_|gdfx_temp0[4]~62_combout & ((\z80_|execute_|ctl_reg_out_lo~8_combout )))) # (!\z80_|alu_|db[4]~18_combout & ((\z80_|execute_|ctl_sw_2u~7_combout ) # +// ((!\z80_|reg_file_|gdfx_temp0[4]~62_combout & \z80_|execute_|ctl_reg_out_lo~8_combout )))) + + .dataa(\z80_|alu_|db[4]~18_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .datac(\z80_|execute_|ctl_sw_2u~7_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[4]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[4]~30 .lut_mask = 16'h7350; +defparam \z80_|alu_control_|db[4]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N10 +cycloneive_lcell_comb \z80_|alu_control_|db[4]~31 ( +// Equation(s): +// \z80_|alu_control_|db[4]~31_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & (!\z80_|alu_control_|db[4]~30_combout & ((\z80_|alu_flags_|flags_hf~combout ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) + + .dataa(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .datab(\z80_|alu_flags_|flags_hf~combout ), + .datac(\z80_|execute_|ctl_flags_oe~2_combout ), + .datad(\z80_|alu_control_|db[4]~30_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[4]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[4]~31 .lut_mask = 16'h008A; +defparam \z80_|alu_control_|db[4]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N2 +cycloneive_lcell_comb \z80_|alu_control_|db[4]~32 ( +// Equation(s): +// \z80_|alu_control_|db[4]~32_combout = ((\z80_|alu_control_|db[4]~31_combout & ((\z80_|bus_control_|db[4]~19_combout ) # (!\z80_|execute_|ctl_sw_1d~7_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) + + .dataa(\z80_|bus_control_|db[4]~19_combout ), + .datab(\z80_|alu_control_|db[4]~31_combout ), + .datac(\z80_|execute_|ctl_sw_1d~7_combout ), + .datad(\z80_|alu_control_|db[6]~11_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[4]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[4]~32 .lut_mask = 16'h8CFF; +defparam \z80_|alu_control_|db[4]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N26 +cycloneive_lcell_comb \z80_|alu_|db[4]~17 ( +// Equation(s): +// \z80_|alu_|db[4]~17_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[4]~66_combout & ((\z80_|alu_control_|db[4]~32_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & +// ((\z80_|alu_control_|db[4]~32_combout ) # ((!\z80_|execute_|ctl_sw_2d~13_combout )))) + + .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .datab(\z80_|alu_control_|db[4]~32_combout ), + .datac(\z80_|execute_|ctl_sw_2d~13_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[4]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[4]~17 .lut_mask = 16'hCF45; +defparam \z80_|alu_|db[4]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N16 +cycloneive_lcell_comb \z80_|alu_|db[4]~18 ( +// Equation(s): +// \z80_|alu_|db[4]~18_combout = ((\z80_|alu_|db[4]~17_combout & ((\z80_|alu_|db_high[0]~25_combout ) # (!\z80_|execute_|ctl_alu_oe~11_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|execute_|ctl_alu_oe~11_combout ), + .datab(\z80_|alu_|db[7]~9_combout ), + .datac(\z80_|alu_|db[4]~17_combout ), + .datad(\z80_|alu_|db_high[0]~25_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[4]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[4]~18 .lut_mask = 16'hF373; +defparam \z80_|alu_|db[4]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N16 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~13 ( +// Equation(s): +// \z80_|alu_|db_low[3]~13_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[4]~18_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[2]~16_combout ))) + + .dataa(\z80_|alu_|db[4]~18_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(gnd), + .datad(\z80_|alu_|db[2]~16_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~13 .lut_mask = 16'hBB88; +defparam \z80_|alu_|db_low[3]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N10 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~14 ( +// Equation(s): +// \z80_|alu_|db_low[3]~14_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_low[3]~13_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[3]~20_combout )))) # +// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) + + .dataa(\z80_|alu_|db_low[3]~13_combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datad(\z80_|alu_|db[3]~20_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~14 .lut_mask = 16'hBF8F; +defparam \z80_|alu_|db_low[3]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N24 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~17 ( +// Equation(s): +// \z80_|alu_|db_low[3]~17_combout = (\z80_|alu_|db_low[3]~16_combout & (\z80_|alu_|db_low[3]~14_combout & ((\z80_|execute_|ctl_alu_res_oe~3_combout ) # (\z80_|alu_|result_lo [3])))) + + .dataa(\z80_|execute_|ctl_alu_res_oe~3_combout ), + .datab(\z80_|alu_|db_low[3]~16_combout ), + .datac(\z80_|alu_|result_lo [3]), + .datad(\z80_|alu_|db_low[3]~14_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~17 .lut_mask = 16'hC800; +defparam \z80_|alu_|db_low[3]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N14 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~25 ( +// Equation(s): +// \z80_|alu_|db_low[3]~25_combout = (\z80_|alu_|db_low[3]~17_combout ) # ((!\z80_|alu_|db_high[3]~0_combout & !\z80_|execute_|ctl_alu_shift_oe~43_combout )) + + .dataa(gnd), + .datab(\z80_|alu_|db_high[3]~0_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datad(\z80_|alu_|db_low[3]~17_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~25 .lut_mask = 16'hFF03; +defparam \z80_|alu_|db_low[3]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N24 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~4 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~4_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [3]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [3])))) + + .dataa(\z80_|alu_|op1_high [3]), + .datab(\z80_|execute_|ctl_alu_op_low~combout ), + .datac(\z80_|alu_|op1_low [3]), + .datad(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~4 .lut_mask = 16'hE200; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N28 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~5 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~5_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~4_combout ) # ((\z80_|alu_|db_low[3]~25_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) + + .dataa(\z80_|alu_|db_low[3]~25_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .datad(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~4_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~5 .lut_mask = 16'h3320; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y18_N29 +dffeas \z80_|alu_|op2_low[3] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~5_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_low [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_low[3] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_low[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N12 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~8_combout & ((\z80_|alu_|db_high[3]~7_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_lq~combout & \z80_|alu_|db_low[3]~25_combout )))) # +// (!\z80_|execute_|ctl_alu_op2_sel_bus~8_combout & (\z80_|execute_|ctl_alu_op2_sel_lq~combout & (\z80_|alu_|db_low[3]~25_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datac(\z80_|alu_|db_low[3]~25_combout ), + .datad(\z80_|alu_|db_high[3]~7_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0 .lut_mask = 16'hEAC0; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N20 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datac(gnd), + .datad(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1 .lut_mask = 16'h3300; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y18_N21 +dffeas \z80_|alu_|op2_high[3] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_high [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_high[3] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_high[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N2 +cycloneive_lcell_comb \z80_|alu_|alu_op2[3]~2 ( +// Equation(s): +// \z80_|alu_|alu_op2[3]~2_combout = \z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [3]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [3])))) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .datab(\z80_|alu_|op2_low [3]), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), + .datad(\z80_|alu_|op2_high [3]), + .cin(gnd), + .combout(\z80_|alu_|alu_op2[3]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op2[3]~2 .lut_mask = 16'h1EB4; +defparam \z80_|alu_|alu_op2[3]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N22 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ) # +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout )))) # (!\z80_|execute_|ctl_alu_core_R~5_combout ) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), + .datac(\z80_|execute_|ctl_alu_core_R~5_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1 .lut_mask = 16'h5F4F; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N20 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout = (\z80_|alu_|alu_op2[3]~2_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout ) # ((\z80_|alu_|alu_op1[3]~2_combout & +// !\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout )))) # (!\z80_|alu_|alu_op2[3]~2_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_|alu_op1[3]~2_combout ) # +// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout )))) + + .dataa(\z80_|alu_|alu_op2[3]~2_combout ), + .datab(\z80_|alu_|alu_op1[3]~2_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 .lut_mask = 16'hEF08; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N14 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~3 ( +// Equation(s): +// \z80_|alu_|db_high[3]~3_combout = (\z80_|execute_|ctl_alu_op2_oe~0_combout & (\z80_|alu_|op2_high [3] & ((\z80_|alu_|op1_high [3]) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout & (((\z80_|alu_|op1_high +// [3]) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datab(\z80_|alu_|op2_high [3]), + .datac(\z80_|alu_|op1_high [3]), + .datad(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~3 .lut_mask = 16'hD0DD; +defparam \z80_|alu_|db_high[3]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N18 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~4 ( +// Equation(s): +// \z80_|alu_|db_high[3]~4_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[6]~22_combout )) + + .dataa(\z80_|alu_|db[6]~22_combout ), + .datab(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), + .datac(gnd), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~4 .lut_mask = 16'hCCAA; +defparam \z80_|alu_|db_high[3]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N28 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~5 ( +// Equation(s): +// \z80_|alu_|db_high[3]~5_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_high[3]~4_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[7]~12_combout )) + + .dataa(\z80_|alu_|db[7]~12_combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .datac(gnd), + .datad(\z80_|alu_|db_high[3]~4_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~5 .lut_mask = 16'hEE22; +defparam \z80_|alu_|db_high[3]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N28 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~2 ( +// Equation(s): +// \z80_|alu_|db_high[3]~2_combout = ((\z80_|bus_control_|db[3]~21_combout & (\z80_|bus_control_|db[5]~15_combout & \z80_|bus_control_|db[4]~19_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) + + .dataa(\z80_|bus_control_|db[3]~21_combout ), + .datab(\z80_|bus_control_|db[5]~15_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datad(\z80_|bus_control_|db[4]~19_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~2 .lut_mask = 16'h8F0F; +defparam \z80_|alu_|db_high[3]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N0 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~6 ( +// Equation(s): +// \z80_|alu_|db_high[3]~6_combout = (\z80_|alu_|db_high[3]~3_combout & (\z80_|alu_|db_high[3]~2_combout & ((\z80_|alu_|db_high[3]~5_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) + + .dataa(\z80_|alu_|db_high[3]~3_combout ), + .datab(\z80_|alu_|db_high[3]~5_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datad(\z80_|alu_|db_high[3]~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~6 .lut_mask = 16'h8A00; +defparam \z80_|alu_|db_high[3]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N22 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~7 ( +// Equation(s): +// \z80_|alu_|db_high[3]~7_combout = ((\z80_|alu_|db_high[3]~6_combout & ((\z80_|execute_|ctl_alu_res_oe~3_combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout )))) # (!\z80_|alu_|db_high[3]~1_combout ) + + .dataa(\z80_|execute_|ctl_alu_res_oe~3_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), + .datac(\z80_|alu_|db_high[3]~1_combout ), + .datad(\z80_|alu_|db_high[3]~6_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~7 .lut_mask = 16'hEF0F; +defparam \z80_|alu_|db_high[3]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N24 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_34 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout = (\z80_|execute_|ctl_flags_bus~combout & ((\z80_|alu_control_|db[7]~19_combout ) # ((\z80_|alu_|db_high[3]~7_combout & \z80_|execute_|ctl_flags_alu~15_combout )))) # (!\z80_|execute_|ctl_flags_bus~combout +// & (((\z80_|alu_|db_high[3]~7_combout & \z80_|execute_|ctl_flags_alu~15_combout )))) + + .dataa(\z80_|execute_|ctl_flags_bus~combout ), + .datab(\z80_|alu_control_|db[7]~19_combout ), + .datac(\z80_|alu_|db_high[3]~7_combout ), + .datad(\z80_|execute_|ctl_flags_alu~15_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_34 .lut_mask = 16'hF888; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y16_N25 +dffeas \z80_|alu_flags_|DFFE_inst_latch_sf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_flags_sz_we~8_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_sf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_sf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~5_combout = ((\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # (\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout )))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~5 .lut_mask = 16'hEF0F; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~7_combout = (\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ) # ((\z80_|pla_decode_|Equal61~2_combout & ((\z80_|nM1_int~2_combout ) # (\z80_|execute_|ctl_eval_cond~0_combout )))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), + .datac(\z80_|pla_decode_|Equal61~2_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~7 .lut_mask = 16'hFCEC; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout = (\z80_|pla_decode_|Equal13~0_combout & (\z80_|execute_|ctl_alu_op_low~22_combout & (\z80_|pla_decode_|Equal55~0_combout & !\z80_|ir_|opcode [3]))) + + .dataa(\z80_|pla_decode_|Equal13~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~6_combout = (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # ((\z80_|execute_|ixy_d~7_combout ) # (\z80_|nM1_int~2_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~6 .lut_mask = 16'hF0E0; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~8_combout = ((\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ) # (\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ))) # (!\z80_|execute_|ctl_alu_op_low~48_combout +// ) + + .dataa(\z80_|execute_|ctl_alu_op_low~48_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~8 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~11_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ) # (((\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~10_combout )) # (!\z80_|execute_|ctl_alu_sel_op2_neg~9_combout )) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~11 .lut_mask = 16'hFFBF; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~12_combout = (((\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ) # (\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout )) # (!\z80_|execute_|ctl_alu_sel_op2_neg~2_combout )) # (!\z80_|execute_|ctl_reg_out_hi~4_combout +// ) + + .dataa(\z80_|execute_|ctl_reg_out_hi~4_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~12 .lut_mask = 16'hFFF7; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~15 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~15_combout = ((\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_sf~q & \z80_|execute_|ctl_alu_sel_op2_neg~12_combout ))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~15 .lut_mask = 16'hFDF5; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N26 +cycloneive_lcell_comb \z80_|alu_|alu_op2[2]~0 ( +// Equation(s): +// \z80_|alu_|alu_op2[2]~0_combout = \z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [2]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [2])))) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), + .datac(\z80_|alu_|op2_low [2]), + .datad(\z80_|alu_|op2_high [2]), + .cin(gnd), + .combout(\z80_|alu_|alu_op2[2]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op2[2]~0 .lut_mask = 16'h369C; +defparam \z80_|alu_|alu_op2[2]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N18 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ) # +// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) # (!\z80_|execute_|ctl_alu_core_R~5_combout ) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), + .datac(\z80_|execute_|ctl_alu_core_R~5_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 .lut_mask = 16'h4F5F; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N24 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout = (\z80_|alu_|alu_op2[2]~0_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ) # ((\z80_|alu_|alu_op1[2]~1_combout & +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) # (!\z80_|alu_|alu_op2[2]~0_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_|alu_op1[2]~1_combout ) # +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) + + .dataa(\z80_|alu_|alu_op2[2]~0_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ), + .datac(\z80_|alu_|alu_op1[2]~1_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 .lut_mask = 16'hECC8; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y17_N11 +dffeas \z80_|alu_control_|DFFE_latch_pf_tmp ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|alu_parity_out~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_alu_op_low~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_control_|DFFE_latch_pf_tmp~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_control_|DFFE_latch_pf_tmp .is_wysiwyg = "true"; +defparam \z80_|alu_control_|DFFE_latch_pf_tmp .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N8 +cycloneive_lcell_comb \z80_|alu_|alu_parity_out~0 ( +// Equation(s): +// \z80_|alu_|alu_parity_out~0_combout = \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout $ (((\z80_|execute_|ctl_alu_op_low~29_combout & (!\z80_|alu_control_|DFFE_latch_pf_tmp~q & !\z80_|execute_|ctl_alu_op_low~41_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~29_combout ), + .datab(\z80_|alu_control_|DFFE_latch_pf_tmp~q ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~41_combout ), + .cin(gnd), + .combout(\z80_|alu_|alu_parity_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_parity_out~0 .lut_mask = 16'hF0D2; +defparam \z80_|alu_|alu_parity_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N10 +cycloneive_lcell_comb \z80_|alu_|alu_parity_out~1 ( +// Equation(s): +// \z80_|alu_|alu_parity_out~1_combout = \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout $ (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout $ (\z80_|alu_|alu_parity_out~0_combout $ +// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), + .datac(\z80_|alu_|alu_parity_out~0_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|alu_parity_out~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_parity_out~1 .lut_mask = 16'h9669; +defparam \z80_|alu_|alu_parity_out~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N24 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~4 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~4_combout = (\z80_|execute_|ctl_pf_sel[0]~2_combout & (((!\z80_|pla_decode_|Equal62~3_combout & !\z80_|execute_|ctl_alu_op_low~27_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_pf_sel[0]~2_combout ), + .datab(\z80_|pla_decode_|Equal62~3_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~4 .lut_mask = 16'h0A2A; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N18 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~5 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~5_combout = (\z80_|execute_|ctl_pf_sel[0]~3_combout & (!\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout $ +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout )))) # (!\z80_|execute_|ctl_pf_sel[0]~3_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout $ ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout )))) + + .dataa(\z80_|execute_|ctl_pf_sel[0]~3_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~5 .lut_mask = 16'h143C; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N16 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~6 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~6_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout & (((!\z80_|pla_decode_|Equal69~0_combout & \z80_|execute_|ctl_flags_bus~1_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal69~0_combout ), + .datab(\z80_|execute_|ctl_flags_bus~1_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~6 .lut_mask = 16'h4F00; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N6 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~1 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~1_combout = (\z80_|execute_|ctl_pf_sel[0]~3_combout & (!\z80_|execute_|ctl_alu_op_low~27_combout & (\z80_|execute_|ctl_pf_sel[0]~2_combout & !\z80_|pla_decode_|Equal62~3_combout ))) + + .dataa(\z80_|execute_|ctl_pf_sel[0]~3_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~27_combout ), + .datac(\z80_|execute_|ctl_pf_sel[0]~2_combout ), + .datad(\z80_|pla_decode_|Equal62~3_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~1 .lut_mask = 16'h0020; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N30 +cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~2 ( +// Equation(s): +// \z80_|decode_state_|DFFE_instNonRep~2_combout = (!\z80_|address_latch_|Q [6] & (!\z80_|address_latch_|Q [5] & (!\z80_|address_latch_|Q [4] & !\z80_|address_latch_|Q [7]))) + + .dataa(\z80_|address_latch_|Q [6]), + .datab(\z80_|address_latch_|Q [5]), + .datac(\z80_|address_latch_|Q [4]), + .datad(\z80_|address_latch_|Q [7]), + .cin(gnd), + .combout(\z80_|decode_state_|DFFE_instNonRep~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep~2 .lut_mask = 16'h0001; +defparam \z80_|decode_state_|DFFE_instNonRep~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N0 +cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~1 ( +// Equation(s): +// \z80_|decode_state_|DFFE_instNonRep~1_combout = (!\z80_|address_latch_|Q [9] & (!\z80_|address_latch_|Q [8] & (!\z80_|address_latch_|Q [11] & !\z80_|address_latch_|Q [10]))) + + .dataa(\z80_|address_latch_|Q [9]), + .datab(\z80_|address_latch_|Q [8]), + .datac(\z80_|address_latch_|Q [11]), + .datad(\z80_|address_latch_|Q [10]), + .cin(gnd), + .combout(\z80_|decode_state_|DFFE_instNonRep~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep~1 .lut_mask = 16'h0001; +defparam \z80_|decode_state_|DFFE_instNonRep~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N4 +cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~3 ( +// Equation(s): +// \z80_|decode_state_|DFFE_instNonRep~3_combout = (\z80_|address_latch_|Q [0] & (!\z80_|address_latch_|Q [2] & (!\z80_|address_latch_|Q [3] & !\z80_|address_latch_|Q [1]))) + + .dataa(\z80_|address_latch_|Q [0]), + .datab(\z80_|address_latch_|Q [2]), + .datac(\z80_|address_latch_|Q [3]), + .datad(\z80_|address_latch_|Q [1]), + .cin(gnd), + .combout(\z80_|decode_state_|DFFE_instNonRep~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep~3 .lut_mask = 16'h0002; +defparam \z80_|decode_state_|DFFE_instNonRep~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N28 +cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~0 ( +// Equation(s): +// \z80_|decode_state_|DFFE_instNonRep~0_combout = (!\z80_|address_latch_|Q [14] & (!\z80_|address_latch_|Q [15] & (!\z80_|address_latch_|Q [12] & !\z80_|address_latch_|Q [13]))) + + .dataa(\z80_|address_latch_|Q [14]), + .datab(\z80_|address_latch_|Q [15]), + .datac(\z80_|address_latch_|Q [12]), + .datad(\z80_|address_latch_|Q [13]), + .cin(gnd), + .combout(\z80_|decode_state_|DFFE_instNonRep~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep~0 .lut_mask = 16'h0001; +defparam \z80_|decode_state_|DFFE_instNonRep~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N24 +cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~4 ( +// Equation(s): +// \z80_|decode_state_|DFFE_instNonRep~4_combout = (\z80_|decode_state_|DFFE_instNonRep~2_combout & (\z80_|decode_state_|DFFE_instNonRep~1_combout & (\z80_|decode_state_|DFFE_instNonRep~3_combout & \z80_|decode_state_|DFFE_instNonRep~0_combout ))) + + .dataa(\z80_|decode_state_|DFFE_instNonRep~2_combout ), + .datab(\z80_|decode_state_|DFFE_instNonRep~1_combout ), + .datac(\z80_|decode_state_|DFFE_instNonRep~3_combout ), + .datad(\z80_|decode_state_|DFFE_instNonRep~0_combout ), + .cin(gnd), + .combout(\z80_|decode_state_|DFFE_instNonRep~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep~4 .lut_mask = 16'h8000; +defparam \z80_|decode_state_|DFFE_instNonRep~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N20 +cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~5 ( +// Equation(s): +// \z80_|decode_state_|DFFE_instNonRep~5_combout = (\z80_|execute_|ctl_flags_bus~1_combout & (((\z80_|decode_state_|DFFE_instNonRep~q )))) # (!\z80_|execute_|ctl_flags_bus~1_combout & ((\z80_|execute_|ixy_d~9_combout & +// (\z80_|decode_state_|DFFE_instNonRep~4_combout )) # (!\z80_|execute_|ixy_d~9_combout & ((\z80_|decode_state_|DFFE_instNonRep~q ))))) + + .dataa(\z80_|decode_state_|DFFE_instNonRep~4_combout ), + .datab(\z80_|execute_|ctl_flags_bus~1_combout ), + .datac(\z80_|decode_state_|DFFE_instNonRep~q ), + .datad(\z80_|execute_|ixy_d~9_combout ), + .cin(gnd), + .combout(\z80_|decode_state_|DFFE_instNonRep~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep~5 .lut_mask = 16'hE2F0; +defparam \z80_|decode_state_|DFFE_instNonRep~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y15_N21 +dffeas \z80_|decode_state_|DFFE_instNonRep ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|decode_state_|DFFE_instNonRep~5_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|decode_state_|DFFE_instNonRep~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep .is_wysiwyg = "true"; +defparam \z80_|decode_state_|DFFE_instNonRep .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N12 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~2 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~2_combout = (\z80_|pla_decode_|Equal69~0_combout & ((\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout & ((\z80_|interrupts_|DFFE_instIFF2~q ))) # (!\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout & +// (!\z80_|decode_state_|DFFE_instNonRep~q )))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout ), + .datab(\z80_|decode_state_|DFFE_instNonRep~q ), + .datac(\z80_|interrupts_|DFFE_instIFF2~q ), + .datad(\z80_|pla_decode_|Equal69~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~2 .lut_mask = 16'hB100; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N14 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~3 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~3_combout = (\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_flags_bus~1_combout & (\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout )) # (!\z80_|execute_|ctl_flags_bus~1_combout & +// ((!\z80_|decode_state_|DFFE_instNonRep~q ))))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|decode_state_|DFFE_instNonRep~q ), + .datad(\z80_|execute_|ctl_flags_bus~1_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~3 .lut_mask = 16'h880C; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N2 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~7 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~7_combout = (\z80_|pla_decode_|Equal69~0_combout ) # (((\z80_|pla_decode_|Equal62~3_combout ) # (\z80_|execute_|ctl_alu_op_low~27_combout )) # (!\z80_|execute_|ctl_flags_bus~1_combout )) + + .dataa(\z80_|pla_decode_|Equal69~0_combout ), + .datab(\z80_|execute_|ctl_flags_bus~1_combout ), + .datac(\z80_|pla_decode_|Equal62~3_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~7 .lut_mask = 16'hFFFB; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N0 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~8 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~8_combout = (\z80_|execute_|ctl_pf_sel[0]~2_combout & (\z80_|execute_|ctl_pf_sel[0]~3_combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout )))) + + .dataa(\z80_|execute_|ctl_pf_sel[0]~2_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_pf_sel[0]~3_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~8 .lut_mask = 16'h2A00; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N26 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~9 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~9_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ) # ((\z80_|alu_|alu_parity_out~1_combout & \z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ))) + + .dataa(\z80_|alu_|alu_parity_out~1_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~9 .lut_mask = 16'hFEFC; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N0 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~0 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~0_combout = (\z80_|execute_|ctl_flags_pf_we~9_combout & (\z80_|execute_|ctl_flags_bus~combout & ((\z80_|alu_control_|db[2]~29_combout )))) # (!\z80_|execute_|ctl_flags_pf_we~9_combout & +// (((\z80_|alu_flags_|DFFE_inst_latch_pf~q )))) + + .dataa(\z80_|execute_|ctl_flags_bus~combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), + .datac(\z80_|execute_|ctl_flags_pf_we~9_combout ), + .datad(\z80_|alu_control_|db[2]~29_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~0 .lut_mask = 16'hAC0C; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N16 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~10 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~10_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ) # ((\z80_|execute_|ctl_flags_alu~15_combout & (\z80_|execute_|ctl_flags_pf_we~9_combout & \z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ))) + + .dataa(\z80_|execute_|ctl_flags_alu~15_combout ), + .datab(\z80_|execute_|ctl_flags_pf_we~9_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~10 .lut_mask = 16'hFF80; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y15_N17 +dffeas \z80_|alu_flags_|DFFE_inst_latch_pf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|DFFE_inst_latch_pf~10_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y13_N6 +cycloneive_lcell_comb \z80_|alu_control_|sel[1]~0 ( +// Equation(s): +// \z80_|alu_control_|sel[1]~0_combout = (\z80_|ir_|opcode [5] & (((!\z80_|pla_decode_|Equal6~0_combout ) # (!\z80_|pla_decode_|Equal40~0_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal40~0_combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|sel[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|sel[1]~0 .lut_mask = 16'h4CCC; +defparam \z80_|alu_control_|sel[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N18 +cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_cond_mux|out~0 ( +// Equation(s): +// \z80_|alu_control_|b2v_inst_cond_mux|out~0_combout = (\z80_|alu_control_|sel[1]~0_combout & (((\z80_|ir_|opcode [4])))) # (!\z80_|alu_control_|sel[1]~0_combout & ((\z80_|ir_|opcode [4] & ((\z80_|alu_flags_|flags_cf~combout ))) # (!\z80_|ir_|opcode [4] +// & (\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q )))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datab(\z80_|alu_flags_|flags_cf~combout ), + .datac(\z80_|alu_control_|sel[1]~0_combout ), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|b2v_inst_cond_mux|out~0 .lut_mask = 16'hFC0A; +defparam \z80_|alu_control_|b2v_inst_cond_mux|out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N16 +cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_cond_mux|out~1 ( +// Equation(s): +// \z80_|alu_control_|b2v_inst_cond_mux|out~1_combout = (\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout & (((\z80_|alu_flags_|DFFE_inst_latch_sf~q ) # (!\z80_|alu_control_|sel[1]~0_combout )))) # (!\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout & +// (\z80_|alu_flags_|DFFE_inst_latch_pf~q & (\z80_|alu_control_|sel[1]~0_combout ))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), + .datab(\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ), + .datac(\z80_|alu_control_|sel[1]~0_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), + .cin(gnd), + .combout(\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|b2v_inst_cond_mux|out~1 .lut_mask = 16'hEC2C; +defparam \z80_|alu_control_|b2v_inst_cond_mux|out~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N26 +cycloneive_lcell_comb \z80_|alu_control_|flags_cond_true~0 ( +// Equation(s): +// \z80_|alu_control_|flags_cond_true~0_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|ir_|opcode [3] $ (((!\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ))))) # (!\z80_|execute_|ctl_eval_cond~0_combout & +// (((\z80_|alu_control_|flags_cond_true~q )))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|alu_control_|flags_cond_true~q ), + .datad(\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|flags_cond_true~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|flags_cond_true~0 .lut_mask = 16'hD872; +defparam \z80_|alu_control_|flags_cond_true~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y16_N27 +dffeas \z80_|alu_control_|flags_cond_true ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_control_|flags_cond_true~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_control_|flags_cond_true~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_control_|flags_cond_true .is_wysiwyg = "true"; +defparam \z80_|alu_control_|flags_cond_true .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~20 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~20_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|pla_decode_|Equal35~0_combout & \z80_|alu_control_|flags_cond_true~q ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|pla_decode_|Equal35~0_combout ), + .datad(\z80_|alu_control_|flags_cond_true~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~20 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sel_wz~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~1 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~1_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ) # ((\z80_|execute_|ctl_reg_sel_wz~20_combout ) # ((\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ctl_al_we~14_combout ))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~20_combout ), + .datad(\z80_|execute_|ctl_al_we~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~1 .lut_mask = 16'hFCFE; +defparam \z80_|execute_|ctl_sw_4d~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~6 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~6_combout = (\z80_|execute_|ctl_sw_4d~0_combout ) # ((\z80_|execute_|ctl_sw_4d~1_combout ) # (!\z80_|execute_|ctl_sw_4d~5_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_sw_4d~0_combout ), + .datac(\z80_|execute_|ctl_sw_4d~1_combout ), + .datad(\z80_|execute_|ctl_sw_4d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~6 .lut_mask = 16'hFCFF; +defparam \z80_|execute_|ctl_sw_4d~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y12_N17 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[1]~6_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N16 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~4 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[1]~4_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[1]~32_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # +// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[1]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[1]~4 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_lo_as[1]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y12_N23 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[1]~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N20 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~5 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[1]~5_combout = (\z80_|reg_file_|db_lo_as[1]~4_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|db_lo_as[1]~4_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_lo|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[1]~5 .lut_mask = 16'hC0CC; +defparam \z80_|reg_file_|db_lo_as[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N18 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout = \z80_|address_latch_|Q [1] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ) + + .dataa(\z80_|address_latch_|Q [1]), + .datab(gnd), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out .lut_mask = 16'h5A5A; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N22 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~6 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[1]~6_combout = ((\z80_|reg_file_|db_lo_as[1]~5_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .datab(\z80_|reg_file_|db_lo_as[1]~5_combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), + .datad(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[1]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[1]~6 .lut_mask = 16'hC4FF; +defparam \z80_|reg_file_|db_lo_as[1]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y12_N7 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~29 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~29_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [1] & ((\z80_|alu_control_|db[1]~26_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (((\z80_|alu_control_|db[1]~26_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [1]), + .datad(\z80_|alu_control_|db[1]~26_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~29 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[1]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y12_N15 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X31_Y12_N5 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~28 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~28_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datab(\z80_|reg_file_|b2v_latch_iy_lo|latch [1]), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~28 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp0[1]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y14_N1 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X32_Y14_N19 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~26 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~26_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [1]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [1]), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~26 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[1]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y13_N19 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~27 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~27_combout = (\z80_|reg_file_|gdfx_temp0[1]~26_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|gdfx_temp0[1]~26_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~27 .lut_mask = 16'hC0CC; +defparam \z80_|reg_file_|gdfx_temp0[1]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~30 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~30_combout = (\z80_|reg_file_|gdfx_temp0[1]~29_combout & (\z80_|reg_file_|gdfx_temp0[1]~28_combout & \z80_|reg_file_|gdfx_temp0[1]~27_combout )) + + .dataa(\z80_|reg_file_|gdfx_temp0[1]~29_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[1]~28_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[1]~27_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~30 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|gdfx_temp0[1]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y12_N7 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y12_N1 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~24 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~24_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [1] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [1] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [1]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~24 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp0[1]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y11_N5 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X31_Y11_N19 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~23 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~23_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [1]), + .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [1]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~23 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[1]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y11_N23 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X32_Y11_N25 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~25 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~25_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [1]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [1]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~25 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[1]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~31 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~31_combout = (\z80_|reg_file_|gdfx_temp0[1]~30_combout & (\z80_|reg_file_|gdfx_temp0[1]~24_combout & (\z80_|reg_file_|gdfx_temp0[1]~23_combout & \z80_|reg_file_|gdfx_temp0[1]~25_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[1]~30_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[1]~24_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[1]~23_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[1]~25_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~31 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[1]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~32 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~32_combout = ((\z80_|reg_file_|gdfx_temp0[1]~31_combout & ((\z80_|reg_file_|db_lo_as[1]~6_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), + .datab(\z80_|reg_file_|db_lo_as[1]~6_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[1]~31_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~32 .lut_mask = 16'hD0FF; +defparam \z80_|reg_file_|gdfx_temp0[1]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N30 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[1]~1 ( +// Equation(s): +// \z80_|reg_file_|db_lo_ds[1]~1_combout = (\z80_|reg_file_|gdfx_temp0[1]~32_combout ) # ((!\z80_|execute_|ctl_reg_out_lo~5_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout & \z80_|execute_|ctl_reg_out_lo~7_combout ))) + + .dataa(\z80_|execute_|ctl_reg_out_lo~5_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_ds[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_ds[1]~1 .lut_mask = 16'hFF40; +defparam \z80_|reg_file_|db_lo_ds[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N16 +cycloneive_lcell_comb \z80_|alu_control_|db[1]~25 ( +// Equation(s): +// \z80_|alu_control_|db[1]~25_combout = (\z80_|reg_file_|db_lo_ds[1]~1_combout & (((\z80_|bus_control_|db[1]~11_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) + + .dataa(\z80_|reg_file_|db_lo_ds[1]~1_combout ), + .datab(\z80_|bus_control_|db[1]~11_combout ), + .datac(\z80_|execute_|ctl_sw_1d~7_combout ), + .datad(\z80_|execute_|ctl_sw_mask543_en~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[1]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[1]~25 .lut_mask = 16'h0A8A; +defparam \z80_|alu_control_|db[1]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N4 +cycloneive_lcell_comb \z80_|alu_control_|db[1]~24 ( +// Equation(s): +// \z80_|alu_control_|db[1]~24_combout = (\z80_|execute_|ctl_flags_oe~2_combout & (((!\z80_|alu_|db[1]~10_combout & \z80_|execute_|ctl_sw_2u~7_combout )) # (!\z80_|alu_flags_|DFFE_inst_latch_nf~q ))) # (!\z80_|execute_|ctl_flags_oe~2_combout & +// (!\z80_|alu_|db[1]~10_combout & (\z80_|execute_|ctl_sw_2u~7_combout ))) + + .dataa(\z80_|execute_|ctl_flags_oe~2_combout ), + .datab(\z80_|alu_|db[1]~10_combout ), + .datac(\z80_|execute_|ctl_sw_2u~7_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .cin(gnd), + .combout(\z80_|alu_control_|db[1]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[1]~24 .lut_mask = 16'h30BA; +defparam \z80_|alu_control_|db[1]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N18 +cycloneive_lcell_comb \z80_|alu_control_|db[1]~26 ( +// Equation(s): +// \z80_|alu_control_|db[1]~26_combout = ((\z80_|alu_control_|db[1]~25_combout & (!\z80_|alu_control_|db[1]~24_combout & \z80_|alu_control_|db[2]~23_combout ))) # (!\z80_|alu_control_|db[6]~11_combout ) + + .dataa(\z80_|alu_control_|db[1]~25_combout ), + .datab(\z80_|alu_control_|db[1]~24_combout ), + .datac(\z80_|alu_control_|db[2]~23_combout ), + .datad(\z80_|alu_control_|db[6]~11_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[1]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[1]~26 .lut_mask = 16'h20FF; +defparam \z80_|alu_control_|db[1]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N2 +cycloneive_lcell_comb \z80_|bus_control_|db[1]~10 ( +// Equation(s): +// \z80_|bus_control_|db[1]~10_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[1]~26_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) + + .dataa(\z80_|bus_control_|db[0]~4_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datad(\z80_|alu_control_|db[1]~26_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[1]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[1]~10 .lut_mask = 16'hAA0A; +defparam \z80_|bus_control_|db[1]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|nextM~4 ( +// Equation(s): +// \z80_|execute_|nextM~4_combout = ((!\z80_|execute_|ctl_mRead~34_combout & ((!\z80_|pla_decode_|Equal24~0_combout ) # (!\z80_|pla_decode_|Equal21~0_combout )))) # (!\z80_|execute_|ctl_state_alu~2_combout ) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|pla_decode_|Equal21~0_combout ), + .datad(\z80_|pla_decode_|Equal24~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~4 .lut_mask = 16'h5777; +defparam \z80_|execute_|nextM~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_iorw~12 ( +// Equation(s): +// \z80_|execute_|ctl_iorw~12_combout = (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [2] & \z80_|execute_|ctl_eval_cond~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~0_combout ), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_iorw~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_iorw~12 .lut_mask = 16'h0200; +defparam \z80_|execute_|ctl_iorw~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_iorw~8 ( +// Equation(s): +// \z80_|execute_|ctl_iorw~8_combout = (\z80_|execute_|ctl_iorw~12_combout ) # ((\z80_|execute_|ctl_state_alu~2_combout & (\z80_|pla_decode_|Equal3~0_combout & \z80_|pla_decode_|Equal24~0_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ctl_iorw~12_combout ), + .datac(\z80_|pla_decode_|Equal3~0_combout ), + .datad(\z80_|pla_decode_|Equal24~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_iorw~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_iorw~8 .lut_mask = 16'hECCC; +defparam \z80_|execute_|ctl_iorw~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_iorw~9 ( +// Equation(s): +// \z80_|execute_|ctl_iorw~9_combout = ((\z80_|execute_|ctl_iorw~8_combout ) # ((\z80_|execute_|ctl_mWrite~17_combout & \z80_|execute_|ctl_mRead~9_combout ))) # (!\z80_|execute_|nextM~4_combout ) + + .dataa(\z80_|execute_|ctl_mWrite~17_combout ), + .datab(\z80_|execute_|nextM~4_combout ), + .datac(\z80_|execute_|ctl_mRead~9_combout ), + .datad(\z80_|execute_|ctl_iorw~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_iorw~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_iorw~9 .lut_mask = 16'hFFB3; +defparam \z80_|execute_|ctl_iorw~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y11_N29 +dffeas \z80_|memory_ifc_|DFFE_iorq_ff1 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|execute_|ctl_iorw~9_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_iorq_ff1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_iorq_ff1 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_iorq_ff1 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y11_N25 +dffeas \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|memory_ifc_|DFFE_iorq_ff1~q ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N14 +cycloneive_lcell_comb \z80_|memory_ifc_|wait_iorq~feeder ( +// Equation(s): +// \z80_|memory_ifc_|wait_iorq~feeder_combout = \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|wait_iorq~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_iorq~feeder .lut_mask = 16'hFF00; +defparam \z80_|memory_ifc_|wait_iorq~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y11_N15 +dffeas \z80_|memory_ifc_|wait_iorq ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|memory_ifc_|wait_iorq~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|wait_iorq~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_iorq .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|wait_iorq .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y11_N9 +dffeas \z80_|memory_ifc_|DFFE_iorq_ff4 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|memory_ifc_|wait_iorq~q ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_iorq_ff4~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_iorq_ff4 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_iorq_ff4 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N8 +cycloneive_lcell_comb \z80_|memory_ifc_|iorq~0 ( +// Equation(s): +// \z80_|memory_ifc_|iorq~0_combout = (\z80_|memory_ifc_|wait_iorq~q ) # ((\z80_|memory_ifc_|DFFE_iorq_ff4~q ) # (\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q )) + + .dataa(gnd), + .datab(\z80_|memory_ifc_|wait_iorq~q ), + .datac(\z80_|memory_ifc_|DFFE_iorq_ff4~q ), + .datad(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|iorq~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|iorq~0 .lut_mask = 16'hFFFC; +defparam \z80_|memory_ifc_|iorq~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y11_N3 +dffeas \z80_|memory_ifc_|DFFE_m1_ff1 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|execute_|setM1~54_combout ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_m1_ff1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_m1_ff1 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_m1_ff1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N26 +cycloneive_lcell_comb \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0 ( +// Equation(s): +// \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout = !\z80_|memory_ifc_|DFFE_m1_ff1~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|memory_ifc_|DFFE_m1_ff1~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0 .lut_mask = 16'h00FF; +defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y11_N27 +dffeas \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y11_N19 +dffeas \z80_|memory_ifc_|DFFE_m1_ff3 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_m1_ff3~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_m1_ff3 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_m1_ff3 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N18 +cycloneive_lcell_comb \z80_|memory_ifc_|nRD_out~0 ( +// Equation(s): +// \z80_|memory_ifc_|nRD_out~0_combout = (\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q & (((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q )) # (!\z80_|interrupts_|DFFE_inst44~q ))) # (!\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q & +// (\z80_|memory_ifc_|DFFE_m1_ff3~q & ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|interrupts_|DFFE_inst44~q )))) + + .dataa(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ), + .datab(\z80_|interrupts_|DFFE_inst44~q ), + .datac(\z80_|memory_ifc_|DFFE_m1_ff3~q ), + .datad(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|nRD_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|nRD_out~0 .lut_mask = 16'hFA32; +defparam \z80_|memory_ifc_|nRD_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|fIORead~0 ( +// Equation(s): +// \z80_|execute_|fIORead~0_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_mWrite~4_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # (\z80_|execute_|ctl_alu_op_low~22_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIORead~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIORead~0 .lut_mask = 16'hC080; +defparam \z80_|execute_|fIORead~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N22 +cycloneive_lcell_comb \z80_|execute_|fIORead~1 ( +// Equation(s): +// \z80_|execute_|fIORead~1_combout = (\z80_|pla_decode_|Equal68~2_combout & (\z80_|pla_decode_|Equal1~4_combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # (!\z80_|execute_|fIOWrite~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal68~2_combout ), + .datab(\z80_|pla_decode_|Equal1~4_combout ), + .datac(\z80_|execute_|ctl_mWrite~5_combout ), + .datad(\z80_|execute_|fIOWrite~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIORead~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIORead~1 .lut_mask = 16'h8088; +defparam \z80_|execute_|fIORead~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N30 +cycloneive_lcell_comb \z80_|execute_|fIORead~2 ( +// Equation(s): +// \z80_|execute_|fIORead~2_combout = (\z80_|execute_|fIORead~1_combout ) # ((\z80_|execute_|ctl_mWrite~17_combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # (\z80_|execute_|ctl_state_alu~3_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~5_combout ), + .datab(\z80_|execute_|ctl_state_alu~3_combout ), + .datac(\z80_|execute_|fIORead~1_combout ), + .datad(\z80_|execute_|ctl_mWrite~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIORead~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIORead~2 .lut_mask = 16'hFEF0; +defparam \z80_|execute_|fIORead~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|fIOWrite~1 ( +// Equation(s): +// \z80_|execute_|fIOWrite~1_combout = (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|execute_|ixy_d~4_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|execute_|ixy_d~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIOWrite~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIOWrite~1 .lut_mask = 16'hA0F0; +defparam \z80_|execute_|fIOWrite~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|fIORead~3 ( +// Equation(s): +// \z80_|execute_|fIORead~3_combout = (\z80_|execute_|fIORead~0_combout ) # ((\z80_|execute_|fIORead~2_combout ) # ((\z80_|execute_|ctl_mRead~2_combout & \z80_|execute_|fIOWrite~1_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~2_combout ), + .datab(\z80_|execute_|fIORead~0_combout ), + .datac(\z80_|execute_|fIORead~2_combout ), + .datad(\z80_|execute_|fIOWrite~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIORead~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIORead~3 .lut_mask = 16'hFEFC; +defparam \z80_|execute_|fIORead~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~30 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~30_combout = (\z80_|execute_|ctl_state_alu~2_combout & ((\z80_|pla_decode_|Equal33~3_combout ) # ((\z80_|pla_decode_|Equal41~2_combout ) # (\z80_|pla_decode_|Equal6~1_combout )))) + + .dataa(\z80_|pla_decode_|Equal33~3_combout ), + .datab(\z80_|pla_decode_|Equal41~2_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|pla_decode_|Equal6~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~30 .lut_mask = 16'hF0E0; +defparam \z80_|execute_|ctl_mRead~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~31 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~31_combout = (\z80_|execute_|ctl_mRead~30_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & \z80_|execute_|ctl_mRead~10_combout )) + + .dataa(\z80_|execute_|ctl_mRead~30_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .datad(\z80_|execute_|ctl_mRead~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~31 .lut_mask = 16'hFAAA; +defparam \z80_|execute_|ctl_mRead~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|nextM~3 ( +// Equation(s): +// \z80_|execute_|nextM~3_combout = (!\z80_|execute_|ixy_d~16_combout & (!\z80_|execute_|ixy_d~10_combout & !\z80_|pla_decode_|Equal41~2_combout )) + + .dataa(\z80_|execute_|ixy_d~16_combout ), + .datab(\z80_|execute_|ixy_d~10_combout ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|nextM~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~3 .lut_mask = 16'h0101; +defparam \z80_|execute_|nextM~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~29 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~29_combout = (\z80_|execute_|ixy_d~8_combout & (((\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal49~0_combout )) # (!\z80_|execute_|nextM~3_combout ))) + + .dataa(\z80_|execute_|nextM~3_combout ), + .datab(\z80_|execute_|ixy_d~8_combout ), + .datac(\z80_|decode_state_|use_ixiy~combout ), + .datad(\z80_|pla_decode_|Equal49~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~29 .lut_mask = 16'hC444; +defparam \z80_|execute_|ctl_mRead~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N26 +cycloneive_lcell_comb \z80_|execute_|setM1~58 ( +// Equation(s): +// \z80_|execute_|setM1~58_combout = (!\z80_|execute_|ctl_mRead~12_combout & ((\z80_|decode_state_|DFFE_instIY1~q ) # ((\z80_|decode_state_|DFFE_inst4~q ) # (!\z80_|pla_decode_|Equal49~0_combout )))) + + .dataa(\z80_|decode_state_|DFFE_instIY1~q ), + .datab(\z80_|decode_state_|DFFE_inst4~q ), + .datac(\z80_|pla_decode_|Equal49~0_combout ), + .datad(\z80_|execute_|ctl_mRead~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~58_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~58 .lut_mask = 16'h00EF; +defparam \z80_|execute_|setM1~58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|setM1~38 ( +// Equation(s): +// \z80_|execute_|setM1~38_combout = (\z80_|execute_|setM1~37_combout & \z80_|execute_|ctl_reg_sys_hilo~38_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|setM1~37_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo~38_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~38 .lut_mask = 16'hF000; +defparam \z80_|execute_|setM1~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|fMRead~4 ( +// Equation(s): +// \z80_|execute_|fMRead~4_combout = (\z80_|execute_|ctl_al_we~4_combout & (\z80_|execute_|ctl_reg_sel_wz~8_combout & !\z80_|pla_decode_|Equal34~0_combout )) + + .dataa(\z80_|execute_|ctl_al_we~4_combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~8_combout ), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal34~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~4 .lut_mask = 16'h0088; +defparam \z80_|execute_|fMRead~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N14 +cycloneive_lcell_comb \z80_|execute_|setM1~39 ( +// Equation(s): +// \z80_|execute_|setM1~39_combout = (!\z80_|pla_decode_|Equal29~0_combout & (\z80_|execute_|fMRead~4_combout & !\z80_|pla_decode_|Equal9~1_combout )) + + .dataa(\z80_|pla_decode_|Equal29~0_combout ), + .datab(gnd), + .datac(\z80_|execute_|fMRead~4_combout ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~39 .lut_mask = 16'h0050; +defparam \z80_|execute_|setM1~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N4 +cycloneive_lcell_comb \z80_|execute_|setM1~40 ( +// Equation(s): +// \z80_|execute_|setM1~40_combout = (\z80_|execute_|setM1~58_combout & (\z80_|execute_|setM1~38_combout & (\z80_|execute_|setM1~39_combout & !\z80_|execute_|ctl_mRead~14_combout ))) + + .dataa(\z80_|execute_|setM1~58_combout ), + .datab(\z80_|execute_|setM1~38_combout ), + .datac(\z80_|execute_|setM1~39_combout ), + .datad(\z80_|execute_|ctl_mRead~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~40 .lut_mask = 16'h0080; +defparam \z80_|execute_|setM1~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y14_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~32 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~32_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (((\z80_|execute_|ctl_mRead~11_combout ) # (!\z80_|execute_|setM1~40_combout )) # (!\z80_|execute_|ctl_mRead~17_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~17_combout ), + .datab(\z80_|execute_|ctl_mRead~11_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|setM1~40_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~32 .lut_mask = 16'hD0F0; +defparam \z80_|execute_|ctl_mRead~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y14_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~33 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~33_combout = (\z80_|execute_|ctl_mRead~31_combout ) # (((\z80_|execute_|ctl_mRead~29_combout ) # (\z80_|execute_|ctl_mRead~32_combout )) # (!\z80_|execute_|ctl_mRead~28_combout )) + + .dataa(\z80_|execute_|ctl_mRead~31_combout ), + .datab(\z80_|execute_|ctl_mRead~28_combout ), + .datac(\z80_|execute_|ctl_mRead~29_combout ), + .datad(\z80_|execute_|ctl_mRead~32_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~33 .lut_mask = 16'hFFFB; +defparam \z80_|execute_|ctl_mRead~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y14_N17 +dffeas \z80_|memory_ifc_|DFFE_mrd_ff1 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|execute_|ctl_mRead~33_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_mrd_ff1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_mrd_ff1 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_mrd_ff1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N30 +cycloneive_lcell_comb \z80_|memory_ifc_|wait_mrd~feeder ( +// Equation(s): +// \z80_|memory_ifc_|wait_mrd~feeder_combout = \z80_|memory_ifc_|DFFE_mrd_ff1~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|memory_ifc_|DFFE_mrd_ff1~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|wait_mrd~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_mrd~feeder .lut_mask = 16'hFF00; +defparam \z80_|memory_ifc_|wait_mrd~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y11_N31 +dffeas \z80_|memory_ifc_|wait_mrd ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|memory_ifc_|wait_mrd~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|wait_mrd~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_mrd .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|wait_mrd .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y11_N17 +dffeas \z80_|memory_ifc_|DFFE_mrd_ff3 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|memory_ifc_|wait_mrd~q ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_mrd_ff3~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_mrd_ff3 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_mrd_ff3 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N12 +cycloneive_lcell_comb \z80_|memory_ifc_|nRD_out~1 ( +// Equation(s): +// \z80_|memory_ifc_|nRD_out~1_combout = (!\z80_|memory_ifc_|wait_mrd~q & !\z80_|memory_ifc_|DFFE_mrd_ff3~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|memory_ifc_|wait_mrd~q ), + .datad(\z80_|memory_ifc_|DFFE_mrd_ff3~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|nRD_out~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|nRD_out~1 .lut_mask = 16'h000F; +defparam \z80_|memory_ifc_|nRD_out~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N20 +cycloneive_lcell_comb \z80_|memory_ifc_|nRD_out~2 ( +// Equation(s): +// \z80_|memory_ifc_|nRD_out~2_combout = (\z80_|memory_ifc_|nRD_out~0_combout ) # (((\z80_|memory_ifc_|iorq~0_combout & \z80_|execute_|fIORead~3_combout )) # (!\z80_|memory_ifc_|nRD_out~1_combout )) + + .dataa(\z80_|memory_ifc_|iorq~0_combout ), + .datab(\z80_|memory_ifc_|nRD_out~0_combout ), + .datac(\z80_|execute_|fIORead~3_combout ), + .datad(\z80_|memory_ifc_|nRD_out~1_combout ), + .cin(gnd), + .combout(\z80_|memory_ifc_|nRD_out~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|nRD_out~2 .lut_mask = 16'hECFF; +defparam \z80_|memory_ifc_|nRD_out~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|fIOWrite~3 ( +// Equation(s): +// \z80_|execute_|fIOWrite~3_combout = ((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|fIOWrite~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIOWrite~3 .lut_mask = 16'h0FCF; +defparam \z80_|execute_|fIOWrite~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|fIOWrite~4 ( +// Equation(s): +// \z80_|execute_|fIOWrite~4_combout = (\z80_|execute_|ctl_mRead~34_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ixy_d~6_combout ) # (!\z80_|execute_|fIOWrite~3_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|execute_|fIOWrite~3_combout ), + .datad(\z80_|execute_|ixy_d~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIOWrite~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIOWrite~4 .lut_mask = 16'hCC8C; +defparam \z80_|execute_|fIOWrite~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N22 +cycloneive_lcell_comb \z80_|execute_|fIOWrite~2 ( +// Equation(s): +// \z80_|execute_|fIOWrite~2_combout = (\z80_|execute_|ctl_iorw~10_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # ((\z80_|execute_|ctl_mWrite~5_combout ) # (!\z80_|execute_|fMRead~2_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ctl_iorw~10_combout ), + .datac(\z80_|execute_|ctl_mWrite~5_combout ), + .datad(\z80_|execute_|fMRead~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIOWrite~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIOWrite~2 .lut_mask = 16'hC8CC; +defparam \z80_|execute_|fIOWrite~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|fIOWrite~5 ( +// Equation(s): +// \z80_|execute_|fIOWrite~5_combout = (\z80_|execute_|fIOWrite~4_combout ) # ((\z80_|execute_|fIOWrite~2_combout ) # ((\z80_|execute_|ctl_mRead~3_combout & \z80_|execute_|fIOWrite~1_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~3_combout ), + .datab(\z80_|execute_|fIOWrite~4_combout ), + .datac(\z80_|execute_|fIOWrite~2_combout ), + .datad(\z80_|execute_|fIOWrite~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIOWrite~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIOWrite~5 .lut_mask = 16'hFEFC; +defparam \z80_|execute_|fIOWrite~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~15 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~15_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_mWrite~7_combout ) # ((\z80_|execute_|ctl_state_alu~2_combout & \z80_|execute_|ctl_mRead~5_combout )))) # (!\z80_|execute_|ctl_eval_cond~0_combout & +// (((\z80_|execute_|ctl_state_alu~2_combout & \z80_|execute_|ctl_mRead~5_combout )))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|ctl_mWrite~7_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_mRead~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~15 .lut_mask = 16'hF888; +defparam \z80_|execute_|ctl_mWrite~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~12 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~12_combout = (!\z80_|execute_|ctl_mWrite~18_combout & (((!\z80_|execute_|ctl_mRead~6_combout & !\z80_|execute_|ctl_mRead~8_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|ctl_mWrite~18_combout ), + .datac(\z80_|execute_|ctl_mRead~6_combout ), + .datad(\z80_|execute_|ctl_mRead~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~12 .lut_mask = 16'h1113; +defparam \z80_|execute_|ctl_mWrite~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~13 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~13_combout = (\z80_|execute_|ctl_mWrite~12_combout & (\z80_|execute_|ctl_mWrite~10_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|execute_|ctl_mWrite~8_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~8_combout ), + .datab(\z80_|execute_|ctl_mWrite~12_combout ), + .datac(\z80_|execute_|ctl_mWrite~10_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~13 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_mWrite~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~14 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~14_combout = (\z80_|execute_|ctl_mWrite~11_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~4_combout & (\z80_|execute_|ctl_mWrite~13_combout & \z80_|execute_|ctl_bus_db_oe~7_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~11_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), + .datac(\z80_|execute_|ctl_mWrite~13_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~14 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_mWrite~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~16 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~16_combout = (\z80_|execute_|ctl_mWrite~15_combout ) # (((\z80_|execute_|ixy_d~8_combout & !\z80_|execute_|ixy_d~17_combout )) # (!\z80_|execute_|ctl_mWrite~14_combout )) + + .dataa(\z80_|execute_|ctl_mWrite~15_combout ), + .datab(\z80_|execute_|ixy_d~8_combout ), + .datac(\z80_|execute_|ixy_d~17_combout ), + .datad(\z80_|execute_|ctl_mWrite~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~16 .lut_mask = 16'hAEFF; +defparam \z80_|execute_|ctl_mWrite~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y11_N7 +dffeas \z80_|memory_ifc_|DFFE_mwr_ff1 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|execute_|ctl_mWrite~16_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_mwr_ff1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_mwr_ff1 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_mwr_ff1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N22 +cycloneive_lcell_comb \z80_|memory_ifc_|wait_mwr~feeder ( +// Equation(s): +// \z80_|memory_ifc_|wait_mwr~feeder_combout = \z80_|memory_ifc_|DFFE_mwr_ff1~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|memory_ifc_|DFFE_mwr_ff1~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|wait_mwr~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_mwr~feeder .lut_mask = 16'hFF00; +defparam \z80_|memory_ifc_|wait_mwr~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y11_N23 +dffeas \z80_|memory_ifc_|wait_mwr ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|memory_ifc_|wait_mwr~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|wait_mwr~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_mwr .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|wait_mwr .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y11_N21 +dffeas \z80_|memory_ifc_|mwr_wr ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|memory_ifc_|wait_mwr~q ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|mwr_wr~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|mwr_wr .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|mwr_wr .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N20 +cycloneive_lcell_comb \z80_|memory_ifc_|nWR_out~0 ( +// Equation(s): +// \z80_|memory_ifc_|nWR_out~0_combout = (\z80_|memory_ifc_|mwr_wr~q ) # ((\z80_|execute_|fIOWrite~5_combout & \z80_|memory_ifc_|iorq~0_combout )) + + .dataa(\z80_|execute_|fIOWrite~5_combout ), + .datab(\z80_|memory_ifc_|iorq~0_combout ), + .datac(\z80_|memory_ifc_|mwr_wr~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|memory_ifc_|nWR_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|nWR_out~0 .lut_mask = 16'hF8F8; +defparam \z80_|memory_ifc_|nWR_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N16 +cycloneive_lcell_comb \Equal2~1 ( +// Equation(s): +// \Equal2~1_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\z80_|memory_ifc_|nRD_out~2_combout & !\z80_|memory_ifc_|nWR_out~0_combout )) + + .dataa(gnd), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|memory_ifc_|nRD_out~2_combout ), + .datad(\z80_|memory_ifc_|nWR_out~0_combout ), + .cin(gnd), + .combout(\Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \Equal2~1 .lut_mask = 16'h00C0; +defparam \Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|fMWrite~3 ( +// Equation(s): +// \z80_|execute_|fMWrite~3_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|sequencer_|DFFE_M4_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~3 .lut_mask = 16'h7373; +defparam \z80_|execute_|fMWrite~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|fMWrite~4 ( +// Equation(s): +// \z80_|execute_|fMWrite~4_combout = (!\z80_|execute_|fMWrite~3_combout & ((\z80_|execute_|ctl_mWrite~7_combout ) # ((\z80_|pla_decode_|Equal13~2_combout ) # (\z80_|execute_|ctl_mRead~5_combout )))) + + .dataa(\z80_|execute_|fMWrite~3_combout ), + .datab(\z80_|execute_|ctl_mWrite~7_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|execute_|ctl_mRead~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~4 .lut_mask = 16'h5554; +defparam \z80_|execute_|fMWrite~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N24 +cycloneive_lcell_comb \z80_|execute_|fMWrite~0 ( +// Equation(s): +// \z80_|execute_|fMWrite~0_combout = ((!\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|M5~q ) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~0 .lut_mask = 16'h0F5F; +defparam \z80_|execute_|fMWrite~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|fMWrite~2 ( +// Equation(s): +// \z80_|execute_|fMWrite~2_combout = (!\z80_|execute_|fMWrite~1_combout & (((\z80_|execute_|ixy_d~6_combout ) # (\z80_|execute_|ixy_d~5_combout )) # (!\z80_|execute_|fMWrite~0_combout ))) + + .dataa(\z80_|execute_|fMWrite~1_combout ), + .datab(\z80_|execute_|fMWrite~0_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~2 .lut_mask = 16'h5551; +defparam \z80_|execute_|fMWrite~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N8 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~3 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~3_combout = (\z80_|execute_|ctl_bus_inc_oe~26_combout & (!\z80_|execute_|fMWrite~4_combout & (!\z80_|execute_|fMWrite~2_combout & !\z80_|execute_|fIOWrite~5_combout ))) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~26_combout ), + .datab(\z80_|execute_|fMWrite~4_combout ), + .datac(\z80_|execute_|fMWrite~2_combout ), + .datad(\z80_|execute_|fIOWrite~5_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~3 .lut_mask = 16'h0002; +defparam \z80_|pin_control_|bus_db_pin_oe~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|fMWrite~8 ( +// Equation(s): +// \z80_|execute_|fMWrite~8_combout = (\z80_|pla_decode_|Equal9~1_combout & (((\z80_|execute_|ctl_alu_oe~0_combout ) # (\z80_|execute_|ctl_reg_in_hi~2_combout )))) # (!\z80_|pla_decode_|Equal9~1_combout & (\z80_|execute_|ctl_mRead~8_combout & +// ((\z80_|execute_|ctl_alu_oe~0_combout ) # (\z80_|execute_|ctl_reg_in_hi~2_combout )))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ctl_mRead~8_combout ), + .datac(\z80_|execute_|ctl_alu_oe~0_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~8 .lut_mask = 16'hEEE0; +defparam \z80_|execute_|fMWrite~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|fMWrite~7 ( +// Equation(s): +// \z80_|execute_|fMWrite~7_combout = (\z80_|execute_|ctl_state_alu~4_combout & ((\z80_|execute_|ctl_mRead~5_combout ) # ((\z80_|execute_|ctl_mWrite~7_combout ) # (\z80_|execute_|ctl_mRead~7_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~5_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_mWrite~7_combout ), + .datad(\z80_|execute_|ctl_mRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~7 .lut_mask = 16'hCCC8; +defparam \z80_|execute_|fMWrite~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N26 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~16 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~16_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & (((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|pla_decode_|Equal13~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), + .datab(\z80_|pla_decode_|Equal13~2_combout ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~16 .lut_mask = 16'h1555; +defparam \z80_|pin_control_|bus_db_pin_oe~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N14 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~8 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~8_combout = (\z80_|execute_|ixy_d~5_combout & (!\z80_|execute_|ctl_mRead~5_combout & ((!\z80_|execute_|ctl_ir_we~4_combout ) # (!\z80_|execute_|ctl_mRead~8_combout )))) # (!\z80_|execute_|ixy_d~5_combout & +// (((!\z80_|execute_|ctl_ir_we~4_combout )) # (!\z80_|execute_|ctl_mRead~8_combout ))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_mRead~8_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|execute_|ctl_mRead~5_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~8 .lut_mask = 16'h153F; +defparam \z80_|pin_control_|bus_db_pin_oe~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|fMWrite~6 ( +// Equation(s): +// \z80_|execute_|fMWrite~6_combout = ((\z80_|pla_decode_|Equal46~0_combout ) # ((\z80_|ir_|opcode [6] & !\z80_|ir_|opcode [7]))) # (!\z80_|execute_|ctl_ir_we~5_combout ) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|execute_|ctl_ir_we~5_combout ), + .datad(\z80_|pla_decode_|Equal46~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~6 .lut_mask = 16'hFF2F; +defparam \z80_|execute_|fMWrite~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N8 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~9 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~9_combout = (\z80_|execute_|fMWrite~6_combout & (((\z80_|execute_|fIOWrite~0_combout )) # (!\z80_|execute_|ctl_mWrite~8_combout ))) # (!\z80_|execute_|fMWrite~6_combout & (\z80_|execute_|fMWrite~0_combout & +// ((\z80_|execute_|fIOWrite~0_combout ) # (!\z80_|execute_|ctl_mWrite~8_combout )))) + + .dataa(\z80_|execute_|fMWrite~6_combout ), + .datab(\z80_|execute_|ctl_mWrite~8_combout ), + .datac(\z80_|execute_|fIOWrite~0_combout ), + .datad(\z80_|execute_|fMWrite~0_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~9 .lut_mask = 16'hF3A2; +defparam \z80_|pin_control_|bus_db_pin_oe~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N28 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~7 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~7_combout = (\z80_|execute_|ixy_d~7_combout & (((\z80_|execute_|fMRead~3_combout & !\z80_|execute_|ctl_mRead~4_combout )))) # (!\z80_|execute_|ixy_d~7_combout & (((!\z80_|execute_|ctl_mRead~4_combout )) # +// (!\z80_|execute_|ctl_alu_oe~0_combout ))) + + .dataa(\z80_|execute_|ctl_alu_oe~0_combout ), + .datab(\z80_|execute_|fMRead~3_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ctl_mRead~4_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~7 .lut_mask = 16'h05CF; +defparam \z80_|pin_control_|bus_db_pin_oe~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N10 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~10 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~10_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (\z80_|pin_control_|bus_db_pin_oe~8_combout & (\z80_|pin_control_|bus_db_pin_oe~9_combout & \z80_|pin_control_|bus_db_pin_oe~7_combout ))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~8_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~9_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~7_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~10 .lut_mask = 16'h8000; +defparam \z80_|pin_control_|bus_db_pin_oe~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N20 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~11 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~11_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout & (!\z80_|execute_|fMWrite~7_combout & (\z80_|execute_|ctl_reg_sel_wz~7_combout & \z80_|pin_control_|bus_db_pin_oe~10_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), + .datab(\z80_|execute_|fMWrite~7_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~7_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~10_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~11 .lut_mask = 16'h2000; +defparam \z80_|pin_control_|bus_db_pin_oe~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N6 +cycloneive_lcell_comb \z80_|execute_|fMWrite~5 ( +// Equation(s): +// \z80_|execute_|fMWrite~5_combout = (!\z80_|execute_|ctl_mWrite~17_combout & (!\z80_|execute_|ctl_mWrite~6_combout & !\z80_|execute_|ctl_mRead~5_combout )) + + .dataa(\z80_|execute_|ctl_mWrite~17_combout ), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datac(\z80_|execute_|ctl_mRead~5_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~5 .lut_mask = 16'h0101; +defparam \z80_|execute_|fMWrite~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N28 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~6 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~6_combout = (\z80_|execute_|ctl_inc_dec~2_combout & ((\z80_|execute_|fMWrite~5_combout ) # ((!\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ixy_d~6_combout )))) + + .dataa(\z80_|execute_|fMWrite~5_combout ), + .datab(\z80_|execute_|ctl_inc_dec~2_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ixy_d~6_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~6 .lut_mask = 16'h888C; +defparam \z80_|pin_control_|bus_db_pin_oe~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N26 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~12 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~12_combout = (!\z80_|execute_|fMWrite~8_combout & (\z80_|pin_control_|bus_db_pin_oe~11_combout & (\z80_|execute_|ctl_bus_inc_oe~30_combout & \z80_|pin_control_|bus_db_pin_oe~6_combout ))) + + .dataa(\z80_|execute_|fMWrite~8_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~11_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~30_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~6_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~12 .lut_mask = 16'h4000; +defparam \z80_|pin_control_|bus_db_pin_oe~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y16_N20 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~4 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~4_combout = (\z80_|pla_decode_|Equal11~0_combout & (!\z80_|execute_|ixy_d~7_combout & ((!\z80_|execute_|ctl_mRead~6_combout ) # (!\z80_|execute_|ctl_reg_in_hi~2_combout )))) # (!\z80_|pla_decode_|Equal11~0_combout & +// (((!\z80_|execute_|ctl_mRead~6_combout )) # (!\z80_|execute_|ctl_reg_in_hi~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datac(\z80_|execute_|ctl_mRead~6_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~4 .lut_mask = 16'h153F; +defparam \z80_|pin_control_|bus_db_pin_oe~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N30 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~5 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~5_combout = (\z80_|pin_control_|bus_db_pin_oe~4_combout & (((\z80_|execute_|ixy_d~4_combout ) # (!\z80_|execute_|ctl_mWrite~7_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|execute_|ctl_mWrite~7_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~4_combout ), + .datad(\z80_|execute_|ixy_d~4_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~5 .lut_mask = 16'hF070; +defparam \z80_|pin_control_|bus_db_pin_oe~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N24 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~13 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~13_combout = (\z80_|pin_control_|bus_db_pin_oe~12_combout & (\z80_|pin_control_|bus_db_pin_oe~5_combout & ((!\z80_|execute_|ixy_d~6_combout ) # (!\z80_|pla_decode_|Equal11~0_combout )))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~12_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~5_combout ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|execute_|ixy_d~6_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~13 .lut_mask = 16'h0888; +defparam \z80_|pin_control_|bus_db_pin_oe~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y18_N12 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~14 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~14_combout = (\z80_|pin_control_|bus_db_pin_oe~3_combout & (\z80_|execute_|ctl_inc_cy~35_combout & (\z80_|execute_|ctl_apin_mux~0_combout & \z80_|pin_control_|bus_db_pin_oe~13_combout ))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~3_combout ), + .datab(\z80_|execute_|ctl_inc_cy~35_combout ), + .datac(\z80_|execute_|ctl_apin_mux~0_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~13_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~14 .lut_mask = 16'h8000; +defparam \z80_|pin_control_|bus_db_pin_oe~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N4 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~2 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~2_combout = (\z80_|sequencer_|DFFE_T3_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~2 .lut_mask = 16'hFFCC; +defparam \z80_|pin_control_|bus_db_pin_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N14 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~15 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~15_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout & (\z80_|execute_|fIOWrite~5_combout & ((\z80_|sequencer_|DFFE_T4_ff~q )))) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout & +// ((\z80_|pin_control_|bus_db_pin_oe~2_combout ) # ((\z80_|execute_|fIOWrite~5_combout & \z80_|sequencer_|DFFE_T4_ff~q )))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .datab(\z80_|execute_|fIOWrite~5_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~2_combout ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~15 .lut_mask = 16'hDC50; +defparam \z80_|pin_control_|bus_db_pin_oe~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N12 +cycloneive_lcell_comb \z80_|clk_delay_|DFF_inst5~feeder ( +// Equation(s): +// \z80_|clk_delay_|DFF_inst5~feeder_combout = \z80_|clk_delay_|SYNTHESIZED_WIRE_7~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ), + .cin(gnd), + .combout(\z80_|clk_delay_|DFF_inst5~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|clk_delay_|DFF_inst5~feeder .lut_mask = 16'hFF00; +defparam \z80_|clk_delay_|DFF_inst5~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X38_Y11_N13 +dffeas \z80_|clk_delay_|DFF_inst5 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|clk_delay_|DFF_inst5~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|clk_delay_|DFF_inst5~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|clk_delay_|DFF_inst5 .is_wysiwyg = "true"; +defparam \z80_|clk_delay_|DFF_inst5 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y11_N15 +dffeas \z80_|memory_ifc_|wait_iorqinta ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|clk_delay_|DFF_inst5~q ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|wait_iorqinta~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_iorqinta .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|wait_iorqinta .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y11_N31 +dffeas \z80_|memory_ifc_|DFFE_intr_ff3 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|memory_ifc_|wait_iorqinta~q ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_intr_ff3~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_intr_ff3 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_intr_ff3 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N30 +cycloneive_lcell_comb \z80_|memory_ifc_|nIORQ_out~0 ( +// Equation(s): +// \z80_|memory_ifc_|nIORQ_out~0_combout = (\z80_|memory_ifc_|iorq~0_combout ) # ((\z80_|memory_ifc_|wait_iorqinta~q ) # (\z80_|memory_ifc_|DFFE_intr_ff3~q )) + + .dataa(\z80_|memory_ifc_|iorq~0_combout ), + .datab(\z80_|memory_ifc_|wait_iorqinta~q ), + .datac(\z80_|memory_ifc_|DFFE_intr_ff3~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|memory_ifc_|nIORQ_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|nIORQ_out~0 .lut_mask = 16'hFEFE; +defparam \z80_|memory_ifc_|nIORQ_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N28 +cycloneive_lcell_comb \Equal2~0 ( +// Equation(s): +// \Equal2~0_combout = (\z80_|memory_ifc_|nIORQ_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\z80_|memory_ifc_|nRD_out~2_combout & !\z80_|memory_ifc_|nWR_out~0_combout ))) + + .dataa(\z80_|memory_ifc_|nIORQ_out~0_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|memory_ifc_|nRD_out~2_combout ), + .datad(\z80_|memory_ifc_|nWR_out~0_combout ), + .cin(gnd), + .combout(\Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \Equal2~0 .lut_mask = 16'h0080; +defparam \Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~2 ( +// Equation(s): +// \z80_|execute_|ctl_apin_mux~2_combout = ((\z80_|execute_|ctl_apin_mux~1_combout & \z80_|execute_|ctl_mWrite~6_combout )) # (!\z80_|execute_|ctl_inc_dec~6_combout ) + + .dataa(\z80_|execute_|ctl_apin_mux~1_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_inc_dec~6_combout ), + .datad(\z80_|execute_|ctl_mWrite~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_apin_mux~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_apin_mux~2 .lut_mask = 16'hAF0F; +defparam \z80_|execute_|ctl_apin_mux~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N8 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[10]~10 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[10]~10_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [10]))) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [10]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[10]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[10]~10 .lut_mask = 16'hDD88; +defparam \z80_|address_pins_|DFFE_apin_latch[10]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux2~0 ( +// Equation(s): +// \z80_|execute_|ctl_apin_mux2~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_apin_mux2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_apin_mux2~0 .lut_mask = 16'h4545; +defparam \z80_|execute_|ctl_apin_mux2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N24 +cycloneive_lcell_comb \z80_|pin_control_|bus_ab_pin_we~0 ( +// Equation(s): +// \z80_|pin_control_|bus_ab_pin_we~0_combout = ((\z80_|execute_|fIORead~3_combout ) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout )) # (!\z80_|sequencer_|DFFE_M1_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|execute_|fIORead~3_combout ), + .datac(gnd), + .datad(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_ab_pin_we~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_ab_pin_we~0 .lut_mask = 16'hDDFF; +defparam \z80_|pin_control_|bus_ab_pin_we~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N26 +cycloneive_lcell_comb \z80_|pin_control_|bus_ab_pin_we~1 ( +// Equation(s): +// \z80_|pin_control_|bus_ab_pin_we~1_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # ((!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|execute_|fMRead~36_combout ) # (\z80_|pin_control_|bus_ab_pin_we~0_combout )))) + + .dataa(\z80_|execute_|fMRead~36_combout ), + .datab(\z80_|pin_control_|bus_ab_pin_we~0_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_ab_pin_we~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_ab_pin_we~1 .lut_mask = 16'hFF0E; +defparam \z80_|pin_control_|bus_ab_pin_we~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y13_N9 +dffeas \z80_|address_pins_|DFFE_apin_latch[10] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[10]~10_combout ), + .asdata(\z80_|address_latch_|Q [10]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [10]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[10] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[10] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X18_Y34_N1 +cycloneive_io_ibuf \PS2_DAT~input ( + .i(PS2_DAT), + .ibar(gnd), + .o(\PS2_DAT~input_o )); +// synopsys translate_off +defparam \PS2_DAT~input .bus_hold = "false"; +defparam \PS2_DAT~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X53_Y14_N1 +cycloneive_io_ibuf \KEY[0]~input ( + .i(KEY[0]), + .ibar(gnd), + .o(\KEY[0]~input_o )); +// synopsys translate_off +defparam \KEY[0]~input .bus_hold = "false"; +defparam \KEY[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X52_Y17_N6 +cycloneive_lcell_comb reset( +// Equation(s): +// \reset~combout = (!\KEY[0]~input_o ) # (!\ula_|pll_|altpll_component|auto_generated|wire_pll1_locked ) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|pll_|altpll_component|auto_generated|wire_pll1_locked ), + .datad(\KEY[0]~input_o ), + .cin(gnd), + .combout(\reset~combout ), + .cout()); +// synopsys translate_off +defparam reset.lut_mask = 16'h0FFF; +defparam reset.sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: CLKCTRL_G8 +cycloneive_clkctrl \reset~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\reset~combout }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\reset~clkctrl_outclk )); +// synopsys translate_off +defparam \reset~clkctrl .clock_type = "global clock"; +defparam \reset~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y10_N0 +cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~3 ( +// Equation(s): +// \ula_|ps2_keyboard_|bit_count~3_combout = (\ula_|ps2_keyboard_|bit_count [2] & (\ula_|ps2_keyboard_|bit_count [0] & (!\ula_|ps2_keyboard_|bit_count [3] & \ula_|ps2_keyboard_|bit_count [1]))) # (!\ula_|ps2_keyboard_|bit_count [2] & +// (((\ula_|ps2_keyboard_|bit_count [3] & !\ula_|ps2_keyboard_|bit_count [1])))) + + .dataa(\ula_|ps2_keyboard_|bit_count [0]), + .datab(\ula_|ps2_keyboard_|bit_count [2]), + .datac(\ula_|ps2_keyboard_|bit_count [3]), + .datad(\ula_|ps2_keyboard_|bit_count [1]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|bit_count~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count~3 .lut_mask = 16'h0830; +defparam \ula_|ps2_keyboard_|bit_count~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X9_Y34_N8 +cycloneive_io_ibuf \PS2_CLK~input ( + .i(PS2_CLK), + .ibar(gnd), + .o(\PS2_CLK~input_o )); +// synopsys translate_off +defparam \PS2_CLK~input .bus_hold = "false"; +defparam \PS2_CLK~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y26_N20 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[7]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[7]~feeder_combout = \PS2_CLK~input_o + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\PS2_CLK~input_o ), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[7]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y26_N21 +dffeas \ula_|ps2_keyboard_|clk_filter[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[7] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y26_N18 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[6]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[6]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [7] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [7]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[6]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y26_N19 +dffeas \ula_|ps2_keyboard_|clk_filter[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[6] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y26_N0 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[5]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[5]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [6] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [6]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[5]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y26_N1 +dffeas \ula_|ps2_keyboard_|clk_filter[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[5] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y26_N6 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[4]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[4]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [5]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[4]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y26_N7 +dffeas \ula_|ps2_keyboard_|clk_filter[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[4] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y26_N10 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[3]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[3]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [4] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [4]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[3]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y26_N11 +dffeas \ula_|ps2_keyboard_|clk_filter[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[3]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[3] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y26_N24 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[2]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[2]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [3] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [3]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[2]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y26_N25 +dffeas \ula_|ps2_keyboard_|clk_filter[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[2] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y26_N26 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[1]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[1]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [2]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[1]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y26_N27 +dffeas \ula_|ps2_keyboard_|clk_filter[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[1] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y26_N16 +cycloneive_lcell_comb \ula_|ps2_keyboard_|Equal0~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|Equal0~0_combout = (!\ula_|ps2_keyboard_|clk_filter [4] & (!\ula_|ps2_keyboard_|clk_filter [7] & (!\ula_|ps2_keyboard_|clk_filter [6] & !\ula_|ps2_keyboard_|clk_filter [5]))) + + .dataa(\ula_|ps2_keyboard_|clk_filter [4]), + .datab(\ula_|ps2_keyboard_|clk_filter [7]), + .datac(\ula_|ps2_keyboard_|clk_filter [6]), + .datad(\ula_|ps2_keyboard_|clk_filter [5]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|Equal0~0 .lut_mask = 16'h0001; +defparam \ula_|ps2_keyboard_|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y26_N12 +cycloneive_lcell_comb \ula_|ps2_keyboard_|Equal0~1 ( +// Equation(s): +// \ula_|ps2_keyboard_|Equal0~1_combout = (!\ula_|ps2_keyboard_|clk_filter [3] & (!\ula_|ps2_keyboard_|clk_filter [2] & (!\ula_|ps2_keyboard_|clk_filter [1] & \ula_|ps2_keyboard_|Equal0~0_combout ))) + + .dataa(\ula_|ps2_keyboard_|clk_filter [3]), + .datab(\ula_|ps2_keyboard_|clk_filter [2]), + .datac(\ula_|ps2_keyboard_|clk_filter [1]), + .datad(\ula_|ps2_keyboard_|Equal0~0_combout ), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|Equal0~1 .lut_mask = 16'h0100; +defparam \ula_|ps2_keyboard_|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y26_N2 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[0]~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[0]~0_combout = !\ula_|ps2_keyboard_|clk_filter [1] + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|clk_filter [1]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[0]~0 .lut_mask = 16'h0F0F; +defparam \ula_|ps2_keyboard_|clk_filter[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y26_N3 +dffeas \ula_|ps2_keyboard_|clk_filter[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[0]~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[0] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y26_N22 +cycloneive_lcell_comb \ula_|ps2_keyboard_|ps2_clk_in~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|ps2_clk_in~0_combout = (\ula_|ps2_keyboard_|Equal0~1_combout & ((\ula_|ps2_keyboard_|clk_filter [0]))) # (!\ula_|ps2_keyboard_|Equal0~1_combout & (\ula_|ps2_keyboard_|ps2_clk_in~q )) + + .dataa(\ula_|ps2_keyboard_|Equal0~1_combout ), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|ps2_clk_in~q ), + .datad(\ula_|ps2_keyboard_|clk_filter [0]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|ps2_clk_in~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|ps2_clk_in~0 .lut_mask = 16'hFA50; +defparam \ula_|ps2_keyboard_|ps2_clk_in~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y26_N23 +dffeas \ula_|ps2_keyboard_|ps2_clk_in ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|ps2_clk_in~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|ps2_clk_in~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|ps2_clk_in .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|ps2_clk_in .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y26_N28 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_edge~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_edge~0_combout = (\ula_|ps2_keyboard_|Equal0~1_combout & (!\ula_|ps2_keyboard_|ps2_clk_in~q & \ula_|ps2_keyboard_|clk_filter [0])) + + .dataa(\ula_|ps2_keyboard_|Equal0~1_combout ), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|ps2_clk_in~q ), + .datad(\ula_|ps2_keyboard_|clk_filter [0]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_edge~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_edge~0 .lut_mask = 16'h0A00; +defparam \ula_|ps2_keyboard_|clk_edge~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y26_N29 +dffeas \ula_|ps2_keyboard_|clk_edge ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_edge~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_edge~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_edge .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_edge .power_up = "low"; +// synopsys translate_on + +// Location: FF_X21_Y10_N1 +dffeas \ula_|ps2_keyboard_|bit_count[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|bit_count~3_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|clk_edge~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|bit_count [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count[3] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|bit_count[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y10_N28 +cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~1 ( +// Equation(s): +// \ula_|ps2_keyboard_|bit_count~1_combout = (!\ula_|ps2_keyboard_|bit_count [3] & (\ula_|ps2_keyboard_|bit_count [2] $ (((\ula_|ps2_keyboard_|bit_count [0] & \ula_|ps2_keyboard_|bit_count [1]))))) + + .dataa(\ula_|ps2_keyboard_|bit_count [0]), + .datab(\ula_|ps2_keyboard_|bit_count [3]), + .datac(\ula_|ps2_keyboard_|bit_count [2]), + .datad(\ula_|ps2_keyboard_|bit_count [1]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|bit_count~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count~1 .lut_mask = 16'h1230; +defparam \ula_|ps2_keyboard_|bit_count~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y10_N29 +dffeas \ula_|ps2_keyboard_|bit_count[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|bit_count~1_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|clk_edge~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|bit_count [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count[2] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|bit_count[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y10_N10 +cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~2 ( +// Equation(s): +// \ula_|ps2_keyboard_|bit_count~2_combout = (\ula_|ps2_keyboard_|bit_count [0] & (!\ula_|ps2_keyboard_|bit_count [1] & ((!\ula_|ps2_keyboard_|bit_count [3]) # (!\ula_|ps2_keyboard_|bit_count [2])))) # (!\ula_|ps2_keyboard_|bit_count [0] & +// (((\ula_|ps2_keyboard_|bit_count [1] & !\ula_|ps2_keyboard_|bit_count [3])))) + + .dataa(\ula_|ps2_keyboard_|bit_count [0]), + .datab(\ula_|ps2_keyboard_|bit_count [2]), + .datac(\ula_|ps2_keyboard_|bit_count [1]), + .datad(\ula_|ps2_keyboard_|bit_count [3]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|bit_count~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count~2 .lut_mask = 16'h025A; +defparam \ula_|ps2_keyboard_|bit_count~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y10_N11 +dffeas \ula_|ps2_keyboard_|bit_count[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|bit_count~2_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|clk_edge~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|bit_count [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count[1] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|bit_count[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y10_N22 +cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|bit_count~0_combout = (!\ula_|ps2_keyboard_|bit_count [0] & (((!\ula_|ps2_keyboard_|bit_count [1] & !\ula_|ps2_keyboard_|bit_count [2])) # (!\ula_|ps2_keyboard_|bit_count [3]))) + + .dataa(\ula_|ps2_keyboard_|bit_count [1]), + .datab(\ula_|ps2_keyboard_|bit_count [2]), + .datac(\ula_|ps2_keyboard_|bit_count [0]), + .datad(\ula_|ps2_keyboard_|bit_count [3]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|bit_count~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count~0 .lut_mask = 16'h010F; +defparam \ula_|ps2_keyboard_|bit_count~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y10_N23 +dffeas \ula_|ps2_keyboard_|bit_count[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|bit_count~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|clk_edge~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|bit_count [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count[0] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|bit_count[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y10_N2 +cycloneive_lcell_comb \ula_|ps2_keyboard_|always1~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|always1~0_combout = (!\ula_|ps2_keyboard_|bit_count [1] & (!\ula_|ps2_keyboard_|bit_count [2] & (!\PS2_DAT~input_o & !\ula_|ps2_keyboard_|bit_count [3]))) + + .dataa(\ula_|ps2_keyboard_|bit_count [1]), + .datab(\ula_|ps2_keyboard_|bit_count [2]), + .datac(\PS2_DAT~input_o ), + .datad(\ula_|ps2_keyboard_|bit_count [3]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|always1~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|always1~0 .lut_mask = 16'h0001; +defparam \ula_|ps2_keyboard_|always1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y10_N12 +cycloneive_lcell_comb \ula_|ps2_keyboard_|LessThan0~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|LessThan0~0_combout = (\ula_|ps2_keyboard_|bit_count [3] & ((\ula_|ps2_keyboard_|bit_count [1]) # (\ula_|ps2_keyboard_|bit_count [2]))) + + .dataa(\ula_|ps2_keyboard_|bit_count [1]), + .datab(\ula_|ps2_keyboard_|bit_count [2]), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|bit_count [3]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|LessThan0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|LessThan0~0 .lut_mask = 16'hEE00; +defparam \ula_|ps2_keyboard_|LessThan0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y10_N26 +cycloneive_lcell_comb \ula_|ps2_keyboard_|shiftreg[0]~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|shiftreg[0]~0_combout = (\ula_|ps2_keyboard_|clk_edge~q & (!\ula_|ps2_keyboard_|LessThan0~0_combout & ((\ula_|ps2_keyboard_|bit_count [0]) # (!\ula_|ps2_keyboard_|always1~0_combout )))) + + .dataa(\ula_|ps2_keyboard_|bit_count [0]), + .datab(\ula_|ps2_keyboard_|always1~0_combout ), + .datac(\ula_|ps2_keyboard_|clk_edge~q ), + .datad(\ula_|ps2_keyboard_|LessThan0~0_combout ), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[0]~0 .lut_mask = 16'h00B0; +defparam \ula_|ps2_keyboard_|shiftreg[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y8_N17 +dffeas \ula_|ps2_keyboard_|shiftreg[8] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\PS2_DAT~input_o ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [8]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[8] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N14 +cycloneive_lcell_comb \ula_|ps2_keyboard_|shiftreg[7]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|shiftreg[7]~feeder_combout = \ula_|ps2_keyboard_|shiftreg [8] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [8]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|shiftreg[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[7]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|shiftreg[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y8_N15 +dffeas \ula_|ps2_keyboard_|shiftreg[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|shiftreg[7]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[7] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y8_N9 +dffeas \ula_|ps2_keyboard_|shiftreg[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [7]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[6] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y8_N5 +dffeas \ula_|ps2_keyboard_|shiftreg[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [6]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[5] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y8_N23 +dffeas \ula_|ps2_keyboard_|shiftreg[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [5]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[4] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y9_N17 +dffeas \ula_|ps2_keyboard_|shiftreg[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [4]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[3] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y8_N23 +dffeas \ula_|ps2_keyboard_|shiftreg[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [3]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[2] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y8_N21 +dffeas \ula_|ps2_keyboard_|shiftreg[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [2]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[1] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N18 +cycloneive_lcell_comb \ula_|ps2_keyboard_|shiftreg[0]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|shiftreg[0]~feeder_combout = \ula_|ps2_keyboard_|shiftreg [1] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|shiftreg[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[0]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|shiftreg[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y10_N19 +dffeas \ula_|ps2_keyboard_|shiftreg[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|shiftreg[0]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[0] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N4 +cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|WideXor0~0_combout = \ula_|ps2_keyboard_|shiftreg [1] $ (\ula_|ps2_keyboard_|shiftreg [0] $ (\ula_|ps2_keyboard_|shiftreg [3] $ (\ula_|ps2_keyboard_|shiftreg [2]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|WideXor0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|WideXor0~0 .lut_mask = 16'h6996; +defparam \ula_|ps2_keyboard_|WideXor0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N16 +cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~1 ( +// Equation(s): +// \ula_|ps2_keyboard_|WideXor0~1_combout = \ula_|ps2_keyboard_|shiftreg [6] $ (\ula_|ps2_keyboard_|shiftreg [5] $ (\ula_|ps2_keyboard_|shiftreg [8] $ (\ula_|ps2_keyboard_|shiftreg [7]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|ps2_keyboard_|shiftreg [8]), + .datad(\ula_|ps2_keyboard_|shiftreg [7]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|WideXor0~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|WideXor0~1 .lut_mask = 16'h6996; +defparam \ula_|ps2_keyboard_|WideXor0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N22 +cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~2 ( +// Equation(s): +// \ula_|ps2_keyboard_|WideXor0~2_combout = \ula_|ps2_keyboard_|shiftreg [4] $ (\ula_|ps2_keyboard_|WideXor0~0_combout $ (\ula_|ps2_keyboard_|WideXor0~1_combout )) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|WideXor0~0_combout ), + .datad(\ula_|ps2_keyboard_|WideXor0~1_combout ), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|WideXor0~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|WideXor0~2 .lut_mask = 16'hA55A; +defparam \ula_|ps2_keyboard_|WideXor0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y10_N4 +cycloneive_lcell_comb \ula_|ps2_keyboard_|scan_code_ready~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|scan_code_ready~0_combout = (\PS2_DAT~input_o & (\ula_|ps2_keyboard_|clk_edge~q & (\ula_|ps2_keyboard_|WideXor0~2_combout & \ula_|ps2_keyboard_|LessThan0~0_combout ))) + + .dataa(\PS2_DAT~input_o ), + .datab(\ula_|ps2_keyboard_|clk_edge~q ), + .datac(\ula_|ps2_keyboard_|WideXor0~2_combout ), + .datad(\ula_|ps2_keyboard_|LessThan0~0_combout ), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|scan_code_ready~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|scan_code_ready~0 .lut_mask = 16'h8000; +defparam \ula_|ps2_keyboard_|scan_code_ready~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y10_N5 +dffeas \ula_|ps2_keyboard_|scan_code_ready ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|scan_code_ready~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|scan_code_ready~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|scan_code_ready .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|scan_code_ready .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~0 ( +// Equation(s): +// \ula_|zx_keyboard_|Equal0~0_combout = (\ula_|ps2_keyboard_|shiftreg [7] & (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [7]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|Equal0~0 .lut_mask = 16'h0200; +defparam \ula_|zx_keyboard_|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~1 ( +// Equation(s): +// \ula_|zx_keyboard_|Equal0~1_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|Equal0~0_combout & !\ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|zx_keyboard_|Equal0~0_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|Equal0~1 .lut_mask = 16'h0020; +defparam \ula_|zx_keyboard_|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|released~0 ( +// Equation(s): +// \ula_|zx_keyboard_|released~0_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (\ula_|zx_keyboard_|Equal0~1_combout & ((\ula_|ps2_keyboard_|shiftreg [4]) # (\ula_|zx_keyboard_|released~q )))) # (!\ula_|ps2_keyboard_|scan_code_ready~q & +// (((\ula_|zx_keyboard_|released~q )))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|scan_code_ready~q ), + .datac(\ula_|zx_keyboard_|released~q ), + .datad(\ula_|zx_keyboard_|Equal0~1_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|released~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|released~0 .lut_mask = 16'hF830; +defparam \ula_|zx_keyboard_|released~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y8_N25 +dffeas \ula_|zx_keyboard_|released ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|released~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|released~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|released .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|released .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|extended~0 ( +// Equation(s): +// \ula_|zx_keyboard_|extended~0_combout = (\ula_|zx_keyboard_|Equal0~1_combout & ((\ula_|zx_keyboard_|extended~q ) # (!\ula_|ps2_keyboard_|shiftreg [4]))) + + .dataa(\ula_|zx_keyboard_|Equal0~1_combout ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|extended~q ), + .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|extended~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|extended~0 .lut_mask = 16'hA0AA; +defparam \ula_|zx_keyboard_|extended~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y8_N31 +dffeas \ula_|zx_keyboard_|extended ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|extended~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|scan_code_ready~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|extended~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|extended .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|extended .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~21 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][1]~21_combout = (!\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [7] & \ula_|ps2_keyboard_|scan_code_ready~q )) + + .dataa(\ula_|zx_keyboard_|extended~q ), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [7]), + .datad(\ula_|ps2_keyboard_|scan_code_ready~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][1]~21_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][1]~21 .lut_mask = 16'h0500; +defparam \ula_|zx_keyboard_|keys[7][1]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~22 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][4]~22_combout = (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [4]) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][4]~22_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][4]~22 .lut_mask = 16'hA0A0; +defparam \ula_|zx_keyboard_|keys[5][4]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][4]~23 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][4]~23_combout = (\ula_|zx_keyboard_|keys[7][1]~21_combout & (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[5][4]~22_combout & !\ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|zx_keyboard_|keys[7][1]~21_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|zx_keyboard_|keys[5][4]~22_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][4]~23_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][4]~23 .lut_mask = 16'h0020; +defparam \ula_|zx_keyboard_|keys[1][4]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][1]~24 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][1]~24_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[1][4]~23_combout )) + + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(gnd), + .datad(\ula_|zx_keyboard_|keys[1][4]~23_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][1]~24_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][1]~24 .lut_mask = 16'h2200; +defparam \ula_|zx_keyboard_|keys[2][1]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][1]~25 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][1]~25_combout = (\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[2][1]~24_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[2][1]~24_combout & ((\ula_|zx_keyboard_|keys[2][1]~q ))))) # +// (!\ula_|ps2_keyboard_|shiftreg [3] & (((\ula_|zx_keyboard_|keys[2][1]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|zx_keyboard_|keys[2][1]~q ), + .datad(\ula_|zx_keyboard_|keys[2][1]~24_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][1]~25_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][1]~25 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[2][1]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y9_N21 +dffeas \ula_|zx_keyboard_|keys[2][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[2][1]~25_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[2][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[2][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~0 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row~0_combout = ((\z80_|address_pins_|DFFE_apin_latch [10]) # (!\ula_|zx_keyboard_|keys[2][1]~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [10]), + .datad(\ula_|zx_keyboard_|keys[2][1]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row~0 .lut_mask = 16'hF3FF; +defparam \ula_|zx_keyboard_|key_row~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~26 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][1]~26_combout = (\ula_|zx_keyboard_|keys[7][1]~21_combout & (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[5][4]~22_combout & !\ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|zx_keyboard_|keys[7][1]~21_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|zx_keyboard_|keys[5][4]~22_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][1]~26_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][1]~26 .lut_mask = 16'h0020; +defparam \ula_|zx_keyboard_|keys[3][1]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~27 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][1]~27_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [3])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][1]~27_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][1]~27 .lut_mask = 16'h2200; +defparam \ula_|zx_keyboard_|keys[3][1]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~28 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][1]~28_combout = (\ula_|zx_keyboard_|keys[3][1]~26_combout & ((\ula_|zx_keyboard_|keys[3][1]~27_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][1]~27_combout & ((\ula_|zx_keyboard_|keys[3][1]~q +// ))))) # (!\ula_|zx_keyboard_|keys[3][1]~26_combout & (((\ula_|zx_keyboard_|keys[3][1]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[3][1]~26_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[3][1]~q ), + .datad(\ula_|zx_keyboard_|keys[3][1]~27_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][1]~28_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][1]~28 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[3][1]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y9_N29 +dffeas \ula_|zx_keyboard_|keys[3][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[3][1]~28_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[3][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[3][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N12 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[11]~11 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[11]~11_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|address [11])) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [11]))) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [11]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[11]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[11]~11 .lut_mask = 16'hDD88; +defparam \z80_|address_pins_|DFFE_apin_latch[11]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y13_N13 +dffeas \z80_|address_pins_|DFFE_apin_latch[11] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[11]~11_combout ), + .asdata(\z80_|address_latch_|Q [11]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [11]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[11] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y6_N16 +cycloneive_lcell_comb \z80_|address_pins_|abus[11]~19 ( +// Equation(s): +// \z80_|address_pins_|abus[11]~19_combout = (\z80_|address_pins_|DFFE_apin_latch [11]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [11]), + .cin(gnd), + .combout(\z80_|address_pins_|abus[11]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[11]~19 .lut_mask = 16'hFF0F; +defparam \z80_|address_pins_|abus[11]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~17 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][4]~17_combout = (!\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [7] & \ula_|ps2_keyboard_|scan_code_ready~q ))) + + .dataa(\ula_|zx_keyboard_|extended~q ), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [7]), + .datad(\ula_|ps2_keyboard_|scan_code_ready~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][4]~17_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][4]~17 .lut_mask = 16'h0100; +defparam \ula_|zx_keyboard_|keys[7][4]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~18 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][4]~18_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][4]~18_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][4]~18 .lut_mask = 16'h4000; +defparam \ula_|zx_keyboard_|keys[6][4]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][1]~19 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][1]~19_combout = (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[7][4]~17_combout & \ula_|zx_keyboard_|keys[6][4]~18_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|zx_keyboard_|keys[7][4]~17_combout ), + .datad(\ula_|zx_keyboard_|keys[6][4]~18_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][1]~19_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][1]~19 .lut_mask = 16'h4000; +defparam \ula_|zx_keyboard_|keys[1][1]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][1]~20 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][1]~20_combout = (\ula_|zx_keyboard_|keys[1][1]~19_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[1][1]~19_combout & ((\ula_|zx_keyboard_|keys[1][1]~q ))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[1][1]~q ), + .datad(\ula_|zx_keyboard_|keys[1][1]~19_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][1]~20_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][1]~20 .lut_mask = 16'h55F0; +defparam \ula_|zx_keyboard_|keys[1][1]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y7_N17 +dffeas \ula_|zx_keyboard_|keys[1][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[1][1]~20_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[1][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[1][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N4 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[9]~9 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[9]~9_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [9]))) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [9]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[9]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[9]~9 .lut_mask = 16'hDD88; +defparam \z80_|address_pins_|DFFE_apin_latch[9]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y10_N5 +dffeas \z80_|address_pins_|DFFE_apin_latch[9] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[9]~9_combout ), + .asdata(\z80_|address_latch_|Q [9]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [9]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[9] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N10 +cycloneive_lcell_comb \z80_|address_pins_|abus[9]~17 ( +// Equation(s): +// \z80_|address_pins_|abus[9]~17_combout = (\z80_|address_pins_|DFFE_apin_latch [9]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [9]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_pins_|abus[9]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[9]~17 .lut_mask = 16'hCFCF; +defparam \z80_|address_pins_|abus[9]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~13 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][0]~13_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (!\ula_|ps2_keyboard_|shiftreg [7] & !\ula_|zx_keyboard_|Equal0~1_combout )) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|scan_code_ready~q ), + .datac(\ula_|ps2_keyboard_|shiftreg [7]), + .datad(\ula_|zx_keyboard_|Equal0~1_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][0]~13_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][0]~13 .lut_mask = 16'h000C; +defparam \ula_|zx_keyboard_|keys[0][0]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~2 ( +// Equation(s): +// \ula_|zx_keyboard_|shifted~2_combout = (!\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|zx_keyboard_|extended~q & \ula_|zx_keyboard_|keys[0][0]~13_combout )) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|zx_keyboard_|extended~q ), + .datad(\ula_|zx_keyboard_|keys[0][0]~13_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|shifted~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|shifted~2 .lut_mask = 16'h0300; +defparam \ula_|zx_keyboard_|shifted~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~14 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][1]~14_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [4] $ (\ula_|ps2_keyboard_|shiftreg [2])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][1]~14_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][1]~14 .lut_mask = 16'h1020; +defparam \ula_|zx_keyboard_|keys[0][1]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~15 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][1]~15_combout = (\ula_|zx_keyboard_|keys[0][1]~14_combout & ((\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [1])) # (!\ula_|ps2_keyboard_|shiftreg [4] & +// (\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [1])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|zx_keyboard_|keys[0][1]~14_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][1]~15 .lut_mask = 16'h0840; +defparam \ula_|zx_keyboard_|keys[0][1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr17~0 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr17~0_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [3]))) # (!\ula_|ps2_keyboard_|shiftreg [1] & +// (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [3]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr17~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr17~0 .lut_mask = 16'h4002; +defparam \ula_|zx_keyboard_|WideOr17~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~5 ( +// Equation(s): +// \ula_|zx_keyboard_|shifted~5_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|zx_keyboard_|WideOr17~0_combout )) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|zx_keyboard_|WideOr17~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|shifted~5_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|shifted~5 .lut_mask = 16'h2020; +defparam \ula_|zx_keyboard_|shifted~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~4 ( +// Equation(s): +// \ula_|zx_keyboard_|shifted~4_combout = (\ula_|zx_keyboard_|shifted~5_combout & ((\ula_|zx_keyboard_|shifted~2_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|shifted~2_combout & ((\ula_|zx_keyboard_|shifted~q ))))) # +// (!\ula_|zx_keyboard_|shifted~5_combout & (((\ula_|zx_keyboard_|shifted~q )))) + + .dataa(\ula_|zx_keyboard_|shifted~5_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|shifted~q ), + .datad(\ula_|zx_keyboard_|shifted~2_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|shifted~4_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|shifted~4 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|shifted~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y10_N27 +dffeas \ula_|zx_keyboard_|shifted ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|shifted~4_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|shifted~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|shifted .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|shifted .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~12 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][1]~12_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & !\ula_|ps2_keyboard_|shiftreg [4])) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|shifted~q ), + .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][1]~12_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][1]~12 .lut_mask = 16'hCCCF; +defparam \ula_|zx_keyboard_|keys[0][1]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~16 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][1]~16_combout = (\ula_|zx_keyboard_|shifted~2_combout & ((\ula_|zx_keyboard_|keys[0][1]~15_combout & ((!\ula_|zx_keyboard_|keys[0][1]~12_combout ))) # (!\ula_|zx_keyboard_|keys[0][1]~15_combout & +// (\ula_|zx_keyboard_|keys[0][1]~q )))) # (!\ula_|zx_keyboard_|shifted~2_combout & (((\ula_|zx_keyboard_|keys[0][1]~q )))) + + .dataa(\ula_|zx_keyboard_|shifted~2_combout ), + .datab(\ula_|zx_keyboard_|keys[0][1]~15_combout ), + .datac(\ula_|zx_keyboard_|keys[0][1]~q ), + .datad(\ula_|zx_keyboard_|keys[0][1]~12_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][1]~16_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][1]~16 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[0][1]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y10_N21 +dffeas \ula_|zx_keyboard_|keys[0][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[0][1]~16_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[0][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[0][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N0 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[8]~8 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[8]~8_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [8]))) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [8]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[8]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[8]~8 .lut_mask = 16'hDD88; +defparam \z80_|address_pins_|DFFE_apin_latch[8]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y10_N1 +dffeas \z80_|address_pins_|DFFE_apin_latch[8] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[8]~8_combout ), + .asdata(\z80_|address_latch_|Q [8]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [8]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[8] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N24 +cycloneive_lcell_comb \z80_|address_pins_|abus[8]~18 ( +// Equation(s): +// \z80_|address_pins_|abus[8]~18_combout = (\z80_|address_pins_|DFFE_apin_latch [8]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [8]), + .cin(gnd), + .combout(\z80_|address_pins_|abus[8]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[8]~18 .lut_mask = 16'hFF0F; +defparam \z80_|address_pins_|abus[8]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N2 +cycloneive_lcell_comb \D[1]~26 ( +// Equation(s): +// \D[1]~26_combout = (\ula_|zx_keyboard_|keys[1][1]~q & (\z80_|address_pins_|abus[9]~17_combout & ((\z80_|address_pins_|abus[8]~18_combout ) # (!\ula_|zx_keyboard_|keys[0][1]~q )))) # (!\ula_|zx_keyboard_|keys[1][1]~q & +// (((\z80_|address_pins_|abus[8]~18_combout ) # (!\ula_|zx_keyboard_|keys[0][1]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[1][1]~q ), + .datab(\z80_|address_pins_|abus[9]~17_combout ), + .datac(\ula_|zx_keyboard_|keys[0][1]~q ), + .datad(\z80_|address_pins_|abus[8]~18_combout ), + .cin(gnd), + .combout(\D[1]~26_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~26 .lut_mask = 16'hDD0D; +defparam \D[1]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N4 +cycloneive_lcell_comb \D[1]~27 ( +// Equation(s): +// \D[1]~27_combout = (\ula_|zx_keyboard_|key_row~0_combout & (\D[1]~26_combout & ((\z80_|address_pins_|abus[11]~19_combout ) # (!\ula_|zx_keyboard_|keys[3][1]~q )))) + + .dataa(\ula_|zx_keyboard_|key_row~0_combout ), + .datab(\ula_|zx_keyboard_|keys[3][1]~q ), + .datac(\z80_|address_pins_|abus[11]~19_combout ), + .datad(\D[1]~26_combout ), + .cin(gnd), + .combout(\D[1]~27_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~27 .lut_mask = 16'hA200; +defparam \D[1]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N16 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[12]~12 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[12]~12_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [12]))) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [12]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[12]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[12]~12 .lut_mask = 16'hDD88; +defparam \z80_|address_pins_|DFFE_apin_latch[12]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y13_N17 +dffeas \z80_|address_pins_|DFFE_apin_latch[12] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[12]~12_combout ), + .asdata(\z80_|address_latch_|Q [12]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [12]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[12] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N28 +cycloneive_lcell_comb \z80_|address_pins_|abus[12]~21 ( +// Equation(s): +// \z80_|address_pins_|abus[12]~21_combout = (\z80_|address_pins_|DFFE_apin_latch [12]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [12]), + .cin(gnd), + .combout(\z80_|address_pins_|abus[12]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[12]~21 .lut_mask = 16'hFF0F; +defparam \z80_|address_pins_|abus[12]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N2 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout = \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout $ (\z80_|address_latch_|Q [13]) + + .dataa(gnd), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), + .datac(gnd), + .datad(\z80_|address_latch_|Q [13]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out .lut_mask = 16'h33CC; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N6 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[13]~13 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[13]~13_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [13])) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|abusz [13]), + .datac(gnd), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[13]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[13]~13 .lut_mask = 16'hEE44; +defparam \z80_|address_pins_|DFFE_apin_latch[13]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y13_N7 +dffeas \z80_|address_pins_|DFFE_apin_latch[13] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[13]~13_combout ), + .asdata(\z80_|address_latch_|Q [13]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [13]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[13] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N6 +cycloneive_lcell_comb \z80_|address_pins_|abus[13]~20 ( +// Equation(s): +// \z80_|address_pins_|abus[13]~20_combout = (\z80_|address_pins_|DFFE_apin_latch [13]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(gnd), + .datad(\z80_|address_pins_|DFFE_apin_latch [13]), + .cin(gnd), + .combout(\z80_|address_pins_|abus[13]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[13]~20 .lut_mask = 16'hFF33; +defparam \z80_|address_pins_|abus[13]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~36 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][1]~36_combout = (!\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [5])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][1]~36_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1]~36 .lut_mask = 16'h0005; +defparam \ula_|zx_keyboard_|keys[5][1]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~34 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][1]~34_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|zx_keyboard_|extended~q & \ula_|zx_keyboard_|keys[0][0]~13_combout )) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|zx_keyboard_|extended~q ), + .datad(\ula_|zx_keyboard_|keys[0][0]~13_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][1]~34_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1]~34 .lut_mask = 16'h0300; +defparam \ula_|zx_keyboard_|keys[5][1]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~35 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][1]~35_combout = (\ula_|zx_keyboard_|keys[5][1]~34_combout & (\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [2])) + + .dataa(\ula_|zx_keyboard_|keys[5][1]~34_combout ), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][1]~35_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1]~35 .lut_mask = 16'hA000; +defparam \ula_|zx_keyboard_|keys[5][1]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~33 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][1]~33_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [3] & \ula_|zx_keyboard_|shifted~q )) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|zx_keyboard_|shifted~q ), + .datac(gnd), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][1]~33_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1]~33 .lut_mask = 16'hFF88; +defparam \ula_|zx_keyboard_|keys[5][1]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~37 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][1]~37_combout = (\ula_|zx_keyboard_|keys[5][1]~36_combout & ((\ula_|zx_keyboard_|keys[5][1]~35_combout & ((!\ula_|zx_keyboard_|keys[5][1]~33_combout ))) # (!\ula_|zx_keyboard_|keys[5][1]~35_combout & +// (\ula_|zx_keyboard_|keys[5][1]~q )))) # (!\ula_|zx_keyboard_|keys[5][1]~36_combout & (((\ula_|zx_keyboard_|keys[5][1]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][1]~36_combout ), + .datab(\ula_|zx_keyboard_|keys[5][1]~35_combout ), + .datac(\ula_|zx_keyboard_|keys[5][1]~q ), + .datad(\ula_|zx_keyboard_|keys[5][1]~33_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][1]~37_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1]~37 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[5][1]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y10_N23 +dffeas \ula_|zx_keyboard_|keys[5][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[5][1]~37_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[5][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[5][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][1]~29 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][1]~29_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [2]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][1]~29_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][1]~29 .lut_mask = 16'h0F00; +defparam \ula_|zx_keyboard_|keys[4][1]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~30 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][2]~30_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [5])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][2]~30_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2]~30 .lut_mask = 16'h0202; +defparam \ula_|zx_keyboard_|keys[7][2]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~31 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][2]~31_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[7][1]~21_combout & (\ula_|zx_keyboard_|keys[7][2]~30_combout & \ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|zx_keyboard_|keys[7][1]~21_combout ), + .datac(\ula_|zx_keyboard_|keys[7][2]~30_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][2]~31_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][2]~31 .lut_mask = 16'h4000; +defparam \ula_|zx_keyboard_|keys[5][2]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][1]~32 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][1]~32_combout = (\ula_|zx_keyboard_|keys[4][1]~29_combout & ((\ula_|zx_keyboard_|keys[5][2]~31_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[5][2]~31_combout & ((\ula_|zx_keyboard_|keys[4][1]~q +// ))))) # (!\ula_|zx_keyboard_|keys[4][1]~29_combout & (((\ula_|zx_keyboard_|keys[4][1]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[4][1]~29_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[4][1]~q ), + .datad(\ula_|zx_keyboard_|keys[5][2]~31_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][1]~32_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][1]~32 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[4][1]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y10_N25 +dffeas \ula_|zx_keyboard_|keys[4][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[4][1]~32_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[4][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[4][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N28 +cycloneive_lcell_comb \D[1]~28 ( +// Equation(s): +// \D[1]~28_combout = (\z80_|address_pins_|abus[12]~21_combout & ((\z80_|address_pins_|abus[13]~20_combout ) # ((!\ula_|zx_keyboard_|keys[5][1]~q )))) # (!\z80_|address_pins_|abus[12]~21_combout & (!\ula_|zx_keyboard_|keys[4][1]~q & +// ((\z80_|address_pins_|abus[13]~20_combout ) # (!\ula_|zx_keyboard_|keys[5][1]~q )))) + + .dataa(\z80_|address_pins_|abus[12]~21_combout ), + .datab(\z80_|address_pins_|abus[13]~20_combout ), + .datac(\ula_|zx_keyboard_|keys[5][1]~q ), + .datad(\ula_|zx_keyboard_|keys[4][1]~q ), + .cin(gnd), + .combout(\D[1]~28_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~28 .lut_mask = 16'h8ACF; +defparam \D[1]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N6 +cycloneive_lcell_comb \z80_|address_pins_|abus[0]~16 ( +// Equation(s): +// \z80_|address_pins_|abus[0]~16_combout = (\z80_|address_pins_|DFFE_apin_latch [0]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [0]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_pins_|abus[0]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[0]~16 .lut_mask = 16'hCFCF; +defparam \z80_|address_pins_|abus[0]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N18 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[14]~14 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[14]~14_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|address [14])) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [14]))) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [14]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[14]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[14]~14 .lut_mask = 16'hDD88; +defparam \z80_|address_pins_|DFFE_apin_latch[14]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y13_N19 +dffeas \z80_|address_pins_|DFFE_apin_latch[14] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[14]~14_combout ), + .asdata(\z80_|address_latch_|Q [14]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [14]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[14] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N20 +cycloneive_lcell_comb \z80_|address_pins_|abus[14]~23 ( +// Equation(s): +// \z80_|address_pins_|abus[14]~23_combout = (\z80_|address_pins_|DFFE_apin_latch [14]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [14]), + .cin(gnd), + .combout(\z80_|address_pins_|abus[14]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[14]~23 .lut_mask = 16'hFF0F; +defparam \z80_|address_pins_|abus[14]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~40 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][1]~40_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [1])) # (!\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [4] & +// \ula_|ps2_keyboard_|shiftreg [1])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][1]~40_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1]~40 .lut_mask = 16'h1188; +defparam \ula_|zx_keyboard_|keys[6][1]~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~41 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][1]~41_combout = (\ula_|zx_keyboard_|keys[6][1]~40_combout & (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [2] $ (\ula_|ps2_keyboard_|shiftreg [3])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|zx_keyboard_|keys[6][1]~40_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][1]~41_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1]~41 .lut_mask = 16'h6000; +defparam \ula_|zx_keyboard_|keys[6][1]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~39 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][1]~39_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|zx_keyboard_|keys[0][0]~13_combout & !\ula_|zx_keyboard_|extended~q ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|zx_keyboard_|keys[0][0]~13_combout ), + .datad(\ula_|zx_keyboard_|extended~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][1]~39_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1]~39 .lut_mask = 16'h0020; +defparam \ula_|zx_keyboard_|keys[6][1]~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~38 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][1]~38_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [2])) + + .dataa(\ula_|zx_keyboard_|shifted~q ), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][1]~38_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1]~38 .lut_mask = 16'hFFA0; +defparam \ula_|zx_keyboard_|keys[6][1]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~42 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][1]~42_combout = (\ula_|zx_keyboard_|keys[6][1]~41_combout & ((\ula_|zx_keyboard_|keys[6][1]~39_combout & ((!\ula_|zx_keyboard_|keys[6][1]~38_combout ))) # (!\ula_|zx_keyboard_|keys[6][1]~39_combout & +// (\ula_|zx_keyboard_|keys[6][1]~q )))) # (!\ula_|zx_keyboard_|keys[6][1]~41_combout & (((\ula_|zx_keyboard_|keys[6][1]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[6][1]~41_combout ), + .datab(\ula_|zx_keyboard_|keys[6][1]~39_combout ), + .datac(\ula_|zx_keyboard_|keys[6][1]~q ), + .datad(\ula_|zx_keyboard_|keys[6][1]~38_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][1]~42_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1]~42 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[6][1]~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y9_N23 +dffeas \ula_|zx_keyboard_|keys[6][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[6][1]~42_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[6][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[6][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~4 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~4_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [2])) # (!\ula_|ps2_keyboard_|shiftreg [1] & +// (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [2])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~4_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~4 .lut_mask = 16'h0402; +defparam \ula_|zx_keyboard_|WideOr16~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~2 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~2_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [1])) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~2 .lut_mask = 16'h000C; +defparam \ula_|zx_keyboard_|WideOr16~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~7 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~7_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|WideOr16~4_combout )) # (!\ula_|ps2_keyboard_|shiftreg [6] & (((\ula_|zx_keyboard_|WideOr16~2_combout & !\ula_|ps2_keyboard_|shiftreg [2])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|zx_keyboard_|WideOr16~4_combout ), + .datac(\ula_|zx_keyboard_|WideOr16~2_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~7_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~7 .lut_mask = 16'h88D8; +defparam \ula_|zx_keyboard_|WideOr16~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~5 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~5_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [1] & ((!\ula_|ps2_keyboard_|shiftreg [2])))) # (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & +// ((\ula_|ps2_keyboard_|shiftreg [1]) # (\ula_|ps2_keyboard_|shiftreg [2])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~5_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~5 .lut_mask = 16'h3064; +defparam \ula_|zx_keyboard_|WideOr16~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~6 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~6_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|zx_keyboard_|WideOr16~7_combout )) # (!\ula_|ps2_keyboard_|shiftreg [4] & (((\ula_|ps2_keyboard_|shiftreg [6] & \ula_|zx_keyboard_|WideOr16~5_combout )))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|zx_keyboard_|WideOr16~7_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(\ula_|zx_keyboard_|WideOr16~5_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~6_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~6 .lut_mask = 16'hD888; +defparam \ula_|zx_keyboard_|WideOr16~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~43 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][1]~43_combout = (!\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [7] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|scan_code_ready~q ))) + + .dataa(\ula_|zx_keyboard_|extended~q ), + .datab(\ula_|ps2_keyboard_|shiftreg [7]), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|ps2_keyboard_|scan_code_ready~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][1]~43_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][1]~43 .lut_mask = 16'h0100; +defparam \ula_|zx_keyboard_|keys[7][1]~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~44 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][1]~44_combout = (\ula_|zx_keyboard_|WideOr16~6_combout & ((\ula_|zx_keyboard_|keys[7][1]~43_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[7][1]~43_combout & (\ula_|zx_keyboard_|keys[7][1]~q )))) +// # (!\ula_|zx_keyboard_|WideOr16~6_combout & (((\ula_|zx_keyboard_|keys[7][1]~q )))) + + .dataa(\ula_|zx_keyboard_|WideOr16~6_combout ), + .datab(\ula_|zx_keyboard_|keys[7][1]~43_combout ), + .datac(\ula_|zx_keyboard_|keys[7][1]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][1]~44_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][1]~44 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[7][1]~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y10_N25 +dffeas \ula_|zx_keyboard_|keys[7][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[7][1]~44_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[7][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[7][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N10 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[15]~15 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[15]~15_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address[15]~1_combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [15])) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|abusz [15]), + .datac(gnd), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|address[15]~1_combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[15]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[15]~15 .lut_mask = 16'hEE44; +defparam \z80_|address_pins_|DFFE_apin_latch[15]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y13_N11 +dffeas \z80_|address_pins_|DFFE_apin_latch[15] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[15]~15_combout ), + .asdata(\z80_|address_latch_|Q [15]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [15]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[15] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N8 +cycloneive_lcell_comb \z80_|address_pins_|abus[15]~22 ( +// Equation(s): +// \z80_|address_pins_|abus[15]~22_combout = (\z80_|address_pins_|DFFE_apin_latch [15]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [15]), + .cin(gnd), + .combout(\z80_|address_pins_|abus[15]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[15]~22 .lut_mask = 16'hFF0F; +defparam \z80_|address_pins_|abus[15]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N16 +cycloneive_lcell_comb \D[1]~29 ( +// Equation(s): +// \D[1]~29_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\z80_|address_pins_|abus[15]~22_combout ) # (!\ula_|zx_keyboard_|keys[7][1]~q )))) # (!\z80_|address_pins_|abus[14]~23_combout & (!\ula_|zx_keyboard_|keys[6][1]~q & +// ((\z80_|address_pins_|abus[15]~22_combout ) # (!\ula_|zx_keyboard_|keys[7][1]~q )))) + + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\ula_|zx_keyboard_|keys[6][1]~q ), + .datac(\ula_|zx_keyboard_|keys[7][1]~q ), + .datad(\z80_|address_pins_|abus[15]~22_combout ), + .cin(gnd), + .combout(\D[1]~29_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~29 .lut_mask = 16'hBB0B; +defparam \D[1]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N26 +cycloneive_lcell_comb \D[1]~30 ( +// Equation(s): +// \D[1]~30_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[1]~27_combout & (\D[1]~28_combout & \D[1]~29_combout ))) + + .dataa(\D[1]~27_combout ), + .datab(\D[1]~28_combout ), + .datac(\z80_|address_pins_|abus[0]~16_combout ), + .datad(\D[1]~29_combout ), + .cin(gnd), + .combout(\D[1]~30_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~30 .lut_mask = 16'hF8F0; +defparam \D[1]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N20 +cycloneive_lcell_comb \ExtRamWE~0 ( +// Equation(s): +// \ExtRamWE~0_combout = (!\z80_|memory_ifc_|nIORQ_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (!\z80_|memory_ifc_|nRD_out~2_combout & \z80_|memory_ifc_|nWR_out~0_combout ))) + + .dataa(\z80_|memory_ifc_|nIORQ_out~0_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|memory_ifc_|nRD_out~2_combout ), + .datad(\z80_|memory_ifc_|nWR_out~0_combout ), + .cin(gnd), + .combout(\ExtRamWE~0_combout ), + .cout()); +// synopsys translate_off +defparam \ExtRamWE~0 .lut_mask = 16'h0400; +defparam \ExtRamWE~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N0 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2] = (!\z80_|address_pins_|abus[14]~23_combout & (\ExtRamWE~0_combout & (\z80_|address_pins_|abus[15]~22_combout & \z80_|address_pins_|abus[13]~20_combout ))) + + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\ExtRamWE~0_combout ), + .datac(\z80_|address_pins_|abus[15]~22_combout ), + .datad(\z80_|address_pins_|abus[13]~20_combout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] .lut_mask = 16'h4000; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N10 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout = (!\z80_|address_pins_|DFFE_apin_latch [14] & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \z80_|address_pins_|DFFE_apin_latch [13])) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [14]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [13]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 .lut_mask = 16'h3000; +defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N6 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[1]~1 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[1]~1_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [1])) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|abusz [1]), + .datac(gnd), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[1]~1 .lut_mask = 16'hEE44; +defparam \z80_|address_pins_|DFFE_apin_latch[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y11_N7 +dffeas \z80_|address_pins_|DFFE_apin_latch[1] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[1]~1_combout ), + .asdata(\z80_|address_latch_|Q [1]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[1] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N10 +cycloneive_lcell_comb \z80_|address_pins_|abus[1]~25 ( +// Equation(s): +// \z80_|address_pins_|abus[1]~25_combout = (\z80_|address_pins_|DFFE_apin_latch [1]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [1]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_pins_|abus[1]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[1]~25 .lut_mask = 16'hCFCF; +defparam \z80_|address_pins_|abus[1]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N12 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[2]~2 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[2]~2_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [2]))) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [2]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[2]~2 .lut_mask = 16'hDD88; +defparam \z80_|address_pins_|DFFE_apin_latch[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y11_N13 +dffeas \z80_|address_pins_|DFFE_apin_latch[2] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[2]~2_combout ), + .asdata(\z80_|address_latch_|Q [2]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[2] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N16 +cycloneive_lcell_comb \z80_|address_pins_|abus[2]~26 ( +// Equation(s): +// \z80_|address_pins_|abus[2]~26_combout = (\z80_|address_pins_|DFFE_apin_latch [2]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [2]), + .cin(gnd), + .combout(\z80_|address_pins_|abus[2]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[2]~26 .lut_mask = 16'hFF0F; +defparam \z80_|address_pins_|abus[2]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N28 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[3]~3 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[3]~3_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [3])) + + .dataa(\z80_|address_latch_|abusz [3]), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_apin_mux~2_combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[3]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[3]~3 .lut_mask = 16'hCCAA; +defparam \z80_|address_pins_|DFFE_apin_latch[3]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y11_N29 +dffeas \z80_|address_pins_|DFFE_apin_latch[3] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[3]~3_combout ), + .asdata(\z80_|address_latch_|Q [3]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[3] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N0 +cycloneive_lcell_comb \z80_|address_pins_|abus[3]~27 ( +// Equation(s): +// \z80_|address_pins_|abus[3]~27_combout = (\z80_|address_pins_|DFFE_apin_latch [3]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [3]), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_pins_|abus[3]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[3]~27 .lut_mask = 16'hAFAF; +defparam \z80_|address_pins_|abus[3]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N16 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[4]~4 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[4]~4_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [4]))) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [4]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[4]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[4]~4 .lut_mask = 16'hDD88; +defparam \z80_|address_pins_|DFFE_apin_latch[4]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y10_N17 +dffeas \z80_|address_pins_|DFFE_apin_latch[4] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[4]~4_combout ), + .asdata(\z80_|address_latch_|Q [4]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[4] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N6 +cycloneive_lcell_comb \z80_|address_pins_|abus[4]~28 ( +// Equation(s): +// \z80_|address_pins_|abus[4]~28_combout = (\z80_|address_pins_|DFFE_apin_latch [4]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [4]), + .cin(gnd), + .combout(\z80_|address_pins_|abus[4]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[4]~28 .lut_mask = 16'hFF0F; +defparam \z80_|address_pins_|abus[4]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N18 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[5]~5 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[5]~5_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [5]))) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [5]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[5]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[5]~5 .lut_mask = 16'hDD88; +defparam \z80_|address_pins_|DFFE_apin_latch[5]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y10_N19 +dffeas \z80_|address_pins_|DFFE_apin_latch[5] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[5]~5_combout ), + .asdata(\z80_|address_latch_|Q [5]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[5] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N30 +cycloneive_lcell_comb \z80_|address_pins_|abus[5]~29 ( +// Equation(s): +// \z80_|address_pins_|abus[5]~29_combout = (\z80_|address_pins_|DFFE_apin_latch [5]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [5]), + .cin(gnd), + .combout(\z80_|address_pins_|abus[5]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[5]~29 .lut_mask = 16'hFF0F; +defparam \z80_|address_pins_|abus[5]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N14 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[6]~6 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[6]~6_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|address [6])) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [6]))) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [6]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[6]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[6]~6 .lut_mask = 16'hDD88; +defparam \z80_|address_pins_|DFFE_apin_latch[6]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y10_N15 +dffeas \z80_|address_pins_|DFFE_apin_latch[6] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[6]~6_combout ), + .asdata(\z80_|address_latch_|Q [6]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[6] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N26 +cycloneive_lcell_comb \z80_|address_pins_|abus[6]~30 ( +// Equation(s): +// \z80_|address_pins_|abus[6]~30_combout = (\z80_|address_pins_|DFFE_apin_latch [6]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [6]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_pins_|abus[6]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[6]~30 .lut_mask = 16'hCFCF; +defparam \z80_|address_pins_|abus[6]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N20 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[7]~7 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[7]~7_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [7])) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|abusz [7]), + .datac(gnd), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[7]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[7]~7 .lut_mask = 16'hEE44; +defparam \z80_|address_pins_|DFFE_apin_latch[7]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y13_N21 +dffeas \z80_|address_pins_|DFFE_apin_latch[7] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[7]~7_combout ), + .asdata(\z80_|address_latch_|Q [7]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[7] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N24 +cycloneive_lcell_comb \z80_|address_pins_|abus[7]~31 ( +// Equation(s): +// \z80_|address_pins_|abus[7]~31_combout = (\z80_|address_pins_|DFFE_apin_latch [7]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_pins_|DFFE_apin_latch [7]), + .cin(gnd), + .combout(\z80_|address_pins_|abus[7]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[7]~31 .lut_mask = 16'hFF55; +defparam \z80_|address_pins_|abus[7]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N0 +cycloneive_lcell_comb \z80_|address_pins_|abus[10]~24 ( +// Equation(s): +// \z80_|address_pins_|abus[10]~24_combout = (\z80_|address_pins_|DFFE_apin_latch [10]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_pins_|DFFE_apin_latch [10]), + .cin(gnd), + .combout(\z80_|address_pins_|abus[10]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[10]~24 .lut_mask = 16'hFF55; +defparam \z80_|address_pins_|abus[10]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y12_N0 cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a9 ( .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), .portare(vcc), @@ -41359,7 +39084,7 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a9 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[1]~34_combout }), + .portadatain({\D[1]~32_combout }), .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , \z80_|address_pins_|abus[0]~16_combout }), @@ -41400,26 +39125,187 @@ defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 204 defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: LCCOMB_X32_Y14_N28 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0 ( +// Location: LCCOMB_X29_Y11_N4 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] ( // Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout )))) +// \ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2] = (!\z80_|address_pins_|abus[14]~23_combout & (\ExtRamWE~0_combout & (\z80_|address_pins_|abus[15]~22_combout & !\z80_|address_pins_|abus[13]~20_combout ))) - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ), + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\ExtRamWE~0_combout ), + .datac(\z80_|address_pins_|abus[15]~22_combout ), + .datad(\z80_|address_pins_|abus[13]~20_combout ), .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout ), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), .cout()); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0 .lut_mask = 16'hDC98; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0 .sum_lutc_input = "datac"; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] .lut_mask = 16'h0040; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X33_Y19_N0 +// Location: LCCOMB_X23_Y10_N0 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout = (!\z80_|address_pins_|DFFE_apin_latch [14] & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|address_pins_|DFFE_apin_latch [13])) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [14]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [13]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 .lut_mask = 16'h0030; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y10_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a1 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[1]~32_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N22 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout = \z80_|address_pins_|abus[13]~20_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_pins_|abus[13]~20_combout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder .lut_mask = 16'hFF00; +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y10_N23 +dffeas \ram1|altsyncram_component|auto_generated|address_reg_a[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram1|altsyncram_component|auto_generated|address_reg_a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true"; +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X23_Y10_N7 +dffeas \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ram1|altsyncram_component|auto_generated|address_reg_a [0]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true"; +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N24 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2] = (\z80_|address_pins_|abus[14]~23_combout & (\ExtRamWE~0_combout & (\z80_|address_pins_|abus[15]~22_combout & !\z80_|address_pins_|abus[13]~20_combout ))) + + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\ExtRamWE~0_combout ), + .datac(\z80_|address_pins_|abus[15]~22_combout ), + .datad(\z80_|address_pins_|abus[13]~20_combout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] .lut_mask = 16'h0080; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y10_N12 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout = (!\z80_|address_pins_|DFFE_apin_latch [13] & (\z80_|address_pins_|DFFE_apin_latch [14] & \z80_|resets_|SYNTHESIZED_WIRE_12~q )) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [13]), + .datac(\z80_|address_pins_|DFFE_apin_latch [14]), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 .lut_mask = 16'h3000; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y8_N0 cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a17 ( .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), .portare(vcc), @@ -41435,7 +39321,7 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a17 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[1]~34_combout }), + .portadatain({\D[1]~32_combout }), .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , \z80_|address_pins_|abus[0]~16_combout }), @@ -41476,7 +39362,98 @@ defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init1 = 20 defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: M9K_X33_Y20_N0 +// Location: FF_X23_Y14_N5 +dffeas \ram1|altsyncram_component|auto_generated|address_reg_a[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|address_pins_|abus[14]~23_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram1|altsyncram_component|auto_generated|address_reg_a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1] .is_wysiwyg = "true"; +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X23_Y14_N27 +dffeas \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ram1|altsyncram_component|auto_generated|address_reg_a [1]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] .is_wysiwyg = "true"; +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N8 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0 .lut_mask = 16'hFC22; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N18 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2] = (\z80_|address_pins_|abus[14]~23_combout & (\ExtRamWE~0_combout & (\z80_|address_pins_|abus[15]~22_combout & \z80_|address_pins_|abus[13]~20_combout ))) + + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\ExtRamWE~0_combout ), + .datac(\z80_|address_pins_|abus[15]~22_combout ), + .datad(\z80_|address_pins_|abus[13]~20_combout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] .lut_mask = 16'h8000; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y10_N30 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout = ((\z80_|address_pins_|DFFE_apin_latch [13] & \z80_|address_pins_|DFFE_apin_latch [14])) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [13]), + .datac(\z80_|address_pins_|DFFE_apin_latch [14]), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 .lut_mask = 16'hC0FF; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y7_N0 cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a25 ( .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), .portare(vcc), @@ -41492,7 +39469,7 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a25 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[1]~34_combout }), + .portadatain({\D[1]~32_combout }), .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , \z80_|address_pins_|abus[0]~16_combout }), @@ -41533,28 +39510,875 @@ defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init1 = 20 defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: LCCOMB_X32_Y14_N16 +// Location: LCCOMB_X31_Y10_N6 cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1 ( // Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout & -// ((\ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout )))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout )) +// \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout = (\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout & (((\ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout & +// (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]))) - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ), .datab(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout ), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), .datad(\ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ), .cin(gnd), .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ), .cout()); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1 .lut_mask = 16'hEC64; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1 .lut_mask = 16'hEC2C; defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X33_Y24_N0 +// Location: M9K_X33_Y2_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a1 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h35C65240B61076066A23CE4CFC5E76063A1C2AE07DF555007338BDC080EA0C23082C891C76A4845096304A0D8502080C1198911998821D09C29CA830C337499236E0548D65FF9125A765F0220F6EB9D1B318244CC6CA2CBC9CEC6979C14EB28DE2E0440C6CBD61341FC178649A852D4A2A0627C688D905B882524E191E7951EAEF30312A73337CBAD4838F42A3293859CD169240D8E652F6D72D8D19D56DD7675939FC47C933E1B0AEF12A484454C247B00A6BEC5402AA08B5106E3065602454C80CEC08A7F5F85CE65326632B4C4F3920019A35AE2AEB321131046EE45B81D4EFD5995634050D4CFEC166B032B6415553AF0358304080D9DD0A2E5948593830; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h376E511217E00B624A46BA2E4CC10B729C326F710F24CFE78C5E63F3024B17CC5E1380C938A0A16C9B696272DE7A2948BE8AFE81310146B8AAE5E549FA27EFBE27929938B8E10530250877A4998D0DF0004852125C20CA8D4279881E41208B14198817644F293AC1946061117122A39D8841818C1389D51BDAC549181902516571163594CEC5863F0F56625E221D6B8180848C6B2BE24AA0AEEE5D187201CAAE6AA394A8644314895565192AE415630A42894D6EF21343903B348EED8642F2310644C9567C0BF9911B870B989C59330089AA4C8065AB1B11132213EE0FD830817DE6C2ED45D76325CA2A8E198859334553AB02945CAB1F17C142288008073004; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h20721F982534A8179F13E2C6328CDE7D2A73087D3A9314419022103DFF7677769FE2D1F27443253D58403577C801AE23371F00290A17E1C4A40258BFD204230EE9969472A81B83113144528F831AA6C3221E137C1E9C670E26809A894013828D9E2DBCBF62498A769893D7218899245CD18AE49F0146517422EE475D520029ED39BCEF6BF4D23532957455F1C80115524179D59C4C4534DF7296991146CE24508366123AA809AB30B47977571C5D70397A93C723106D0A2C254714359DC7C9E13AE624C94932927924D20024CD638A05C8620023319662D80E05805625BC4A4006C78011F78D8B82E59F0CD4B32D6801669BE3EB0B96960DFF152005EC7C16CB; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h9C8CA06AA05B63C89A59A3E4E80807B27A70B0006624C4AC4A0595CCD8CA20824CA272352720BCD900A6D79BFD9D0595EC0D044ABC8CC28E9AE946E3D2000A4EFA4F91915C6AC9D8570C292F10848189906127BCBE06FFE92DAFB4AAFB240D88DDBB7B207EFA1709B05E1C4801BD45625A36BB62220506E171891964A31BED2215408676F600F490FAA59B488C7998CC8CCC28922AC62644EEBB432EEECB51B16CDEE7468681D6C31E4991CA3736E9ACB7531EC6D8BBCD453718101EA25D79278C6AC955A8A6140421573E413CF5A80AA1436D8B4C31A2AB26D2A61CE834248BAD5751BD429B4F61318427560CE39D49299002165212181064E24FF0093B997B; +// synopsys translate_on + +// Location: M9K_X22_Y2_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a9 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h420000004200000000000000000080000000000000000000000000000030004480000000424202423E1E3E02304C3C0C3C7E7E40403E427E3402421824347C1C0400280000003C3406303220344C403C0400100010100000005062742400000091991809FB3BD9084A1241F5015988B3C506031934089E0E1FA8043DDAF2CC07D94A6F2B1D133C211222B22C787D430E45D4C53282288077DFC0F704AAD55127A2BEAEA114958D2817AB1213183A4E1A15E3690A08A33B429284A202011A1243D49CACA1C0A441405A720D21A0921294045F746229E287B95E956AA3DE0CA3B7A019C8039C4DDA6BC99371248CC6008A54CB84503442C4F91309238ECB252072; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h81F3167814687CBD683E54D44555E6C95B5F2A72C0C193C6110C0221A448D0C9A0D8E36A84D5C61285128845215F8F8821C308E368283D8E2B42989C04A8B51354E09A38775020189010680840800297C31282442326D008D1F2351A89FFD7C16087F8B130F04418C0A1C082FC005843F5B42CADD9455ADBD328C13219110DE100D988737BBB44C414210118C673B0C1BDF76C499226F78FF41A0AF7AFD3308AAA0AAA22B1C70003F542A66FD1F1CF9D4578315F8C1C6FEC3EDB9B322CB204821A94A248414CE030020F207BF040A06A3DF993DEA3823423F405294A52014565100E0A7211342DF02958046899EEBE6E491299A09312778193FEBD7FFABA8000; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h2C05EF54A3C0F7F5F017E03F5800377CCF6E493C84E8F56441831087370A084801DEC1A54696B9912E8B0705C8587D4F7D36C8638947A620554CC77819B55B7A12D552A8A0496EFE3AAC6F34739A94E798101823148D811212E9A349CC219049527CCD419525AD29AB7D372C0B56AA0A065F8BDC905346478059EC82801920687FF29C990C9E66273CC78041192D03081CC62A8A0D8CB4D9CF2F2558131A78B8A807C3A1110211AFCA2A142F0BA928156D142250438143D339E4E2079F298493C08C4847914664518E27EF7EB9C870A226AFC35BEDB651840466400D4B3C0F877740114D6B08228BCC693FB12CECCCD2461586069445ACFC910B1241434622B6; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h5FFE6AD3343986C4103935236B6E6E11B940EF46A8FC06E6872A6929D50DCDB75621E625522D34519BF2C353F8AA030B9109C2F9686AD3AF57AF3016D9160354C0BED5FBD379F904A41BAFB6BE4EE9F208058229DD0C354F034A6C4D8B6C16A29F0120108829220B230F44550832C1022530CC13C4C30D8254ECA5200A1941266EE48A1CA6430860DE613153615CAF4C8D191004CE9C6105D8C6795B6484467D21D9DC46029B8376E97F2C7BF8C3A218EE79DDBCF886B2BBDE702F71B38AEC6914E5DCCAFE50CC13922A5B149C598A621F80C24D215291228844E7F33F9763C6639303AE5376F664C7125632C1A280CECD5740C77849D937472B202579964F60; +// synopsys translate_on + +// Location: CLKCTRL_G15 +cycloneive_clkctrl \CLOCK_50~inputclkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\CLOCK_50~input_o }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\CLOCK_50~inputclkctrl_outclk )); +// synopsys translate_off +defparam \CLOCK_50~inputclkctrl .clock_type = "global clock"; +defparam \CLOCK_50~inputclkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N4 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout = \z80_|address_pins_|abus[13]~20_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_pins_|abus[13]~20_combout ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder .lut_mask = 16'hFF00; +defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y10_N5 +dffeas \ram0|altsyncram_component|auto_generated|address_reg_a[0] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram0|altsyncram_component|auto_generated|address_reg_a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true"; +defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X23_Y10_N15 +dffeas \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(gnd), + .asdata(\ram0|altsyncram_component|auto_generated|address_reg_a [0]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true"; +defparam \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N14 +cycloneive_lcell_comb \Selector3~0 ( +// Equation(s): +// \Selector3~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [14] & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))) # (!\z80_|address_pins_|DFFE_apin_latch [14] & +// (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0])))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\z80_|address_pins_|DFFE_apin_latch [14]), + .cin(gnd), + .combout(\Selector3~0_combout ), + .cout()); +// synopsys translate_off +defparam \Selector3~0 .lut_mask = 16'hF0B8; +defparam \Selector3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N22 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout = (\z80_|address_pins_|abus[14]~23_combout & (\ExtRamWE~0_combout & (!\z80_|address_pins_|abus[15]~22_combout & \z80_|address_pins_|abus[13]~20_combout ))) + + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\ExtRamWE~0_combout ), + .datac(\z80_|address_pins_|abus[15]~22_combout ), + .datad(\z80_|address_pins_|abus[13]~20_combout ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0 .lut_mask = 16'h0800; +defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y31_N14 +cycloneive_lcell_comb \~GND ( +// Equation(s): +// \~GND~combout = GND + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\~GND~combout ), + .cout()); +// synopsys translate_off +defparam \~GND .lut_mask = 16'h0000; +defparam \~GND .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y30_N24 +cycloneive_lcell_comb \ula_|video_|vram_address[0]~feeder ( +// Equation(s): +// \ula_|video_|vram_address[0]~feeder_combout = \ula_|video_|vga_hc [4] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|vga_hc [4]), + .cin(gnd), + .combout(\ula_|video_|vram_address[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address[0]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|vram_address[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y31_N26 +cycloneive_lcell_comb \ula_|video_|vram_address~0 ( +// Equation(s): +// \ula_|video_|vram_address~0_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [1] $ (\ula_|video_|vga_hc [2])))) + + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|vga_hc [3]), + .datac(\ula_|video_|vga_hc [2]), + .datad(\ula_|video_|vga_hc [0]), + .cin(gnd), + .combout(\ula_|video_|vram_address~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address~0 .lut_mask = 16'h0048; +defparam \ula_|video_|vram_address~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y30_N25 +dffeas \ula_|video_|vram_address[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vram_address[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[0] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y30_N22 +cycloneive_lcell_comb \ula_|video_|vram_address[1]~feeder ( +// Equation(s): +// \ula_|video_|vram_address[1]~feeder_combout = \ula_|video_|vga_hc [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|vga_hc [5]), + .cin(gnd), + .combout(\ula_|video_|vram_address[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address[1]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|vram_address[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y30_N23 +dffeas \ula_|video_|vram_address[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vram_address[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[1] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y30_N20 +cycloneive_lcell_comb \ula_|video_|vram_address[2]~4 ( +// Equation(s): +// \ula_|video_|vram_address[2]~4_combout = !\ula_|video_|vga_hc [6] + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|video_|vga_hc [6]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|video_|vram_address[2]~4_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address[2]~4 .lut_mask = 16'h0F0F; +defparam \ula_|video_|vram_address[2]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y30_N21 +dffeas \ula_|video_|vram_address[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vram_address[2]~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[2] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y30_N30 +cycloneive_lcell_comb \ula_|video_|Add3~0 ( +// Equation(s): +// \ula_|video_|Add3~0_combout = \ula_|video_|vga_hc [6] $ (\ula_|video_|vga_hc [7]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|video_|vga_hc [6]), + .datad(\ula_|video_|vga_hc [7]), + .cin(gnd), + .combout(\ula_|video_|Add3~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Add3~0 .lut_mask = 16'h0FF0; +defparam \ula_|video_|Add3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y30_N31 +dffeas \ula_|video_|vram_address[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Add3~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[3] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y30_N16 +cycloneive_lcell_comb \ula_|video_|Add3~1 ( +// Equation(s): +// \ula_|video_|Add3~1_combout = \ula_|video_|vga_hc [8] $ (((!\ula_|video_|vga_hc [7]) # (!\ula_|video_|vga_hc [6]))) + + .dataa(\ula_|video_|vga_hc [8]), + .datab(gnd), + .datac(\ula_|video_|vga_hc [6]), + .datad(\ula_|video_|vga_hc [7]), + .cin(gnd), + .combout(\ula_|video_|Add3~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Add3~1 .lut_mask = 16'hA555; +defparam \ula_|video_|Add3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y30_N17 +dffeas \ula_|video_|vram_address[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Add3~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[4] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y30_N10 +cycloneive_lcell_comb \ula_|video_|Add4~0 ( +// Equation(s): +// \ula_|video_|Add4~0_combout = (\ula_|video_|vga_vc [0] & (\ula_|video_|vga_vc [1] $ (VCC))) # (!\ula_|video_|vga_vc [0] & (\ula_|video_|vga_vc [1] & VCC)) +// \ula_|video_|Add4~1 = CARRY((\ula_|video_|vga_vc [0] & \ula_|video_|vga_vc [1])) + + .dataa(\ula_|video_|vga_vc [0]), + .datab(\ula_|video_|vga_vc [1]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\ula_|video_|Add4~0_combout ), + .cout(\ula_|video_|Add4~1 )); +// synopsys translate_off +defparam \ula_|video_|Add4~0 .lut_mask = 16'h6688; +defparam \ula_|video_|Add4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y30_N12 +cycloneive_lcell_comb \ula_|video_|Add4~2 ( +// Equation(s): +// \ula_|video_|Add4~2_combout = (\ula_|video_|vga_vc [2] & (\ula_|video_|Add4~1 & VCC)) # (!\ula_|video_|vga_vc [2] & (!\ula_|video_|Add4~1 )) +// \ula_|video_|Add4~3 = CARRY((!\ula_|video_|vga_vc [2] & !\ula_|video_|Add4~1 )) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [2]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~1 ), + .combout(\ula_|video_|Add4~2_combout ), + .cout(\ula_|video_|Add4~3 )); +// synopsys translate_off +defparam \ula_|video_|Add4~2 .lut_mask = 16'hC303; +defparam \ula_|video_|Add4~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y30_N14 +cycloneive_lcell_comb \ula_|video_|Add4~4 ( +// Equation(s): +// \ula_|video_|Add4~4_combout = (\ula_|video_|vga_vc [3] & ((GND) # (!\ula_|video_|Add4~3 ))) # (!\ula_|video_|vga_vc [3] & (\ula_|video_|Add4~3 $ (GND))) +// \ula_|video_|Add4~5 = CARRY((\ula_|video_|vga_vc [3]) # (!\ula_|video_|Add4~3 )) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [3]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~3 ), + .combout(\ula_|video_|Add4~4_combout ), + .cout(\ula_|video_|Add4~5 )); +// synopsys translate_off +defparam \ula_|video_|Add4~4 .lut_mask = 16'h3CCF; +defparam \ula_|video_|Add4~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y30_N16 +cycloneive_lcell_comb \ula_|video_|Add4~6 ( +// Equation(s): +// \ula_|video_|Add4~6_combout = (\ula_|video_|vga_vc [4] & (!\ula_|video_|Add4~5 )) # (!\ula_|video_|vga_vc [4] & ((\ula_|video_|Add4~5 ) # (GND))) +// \ula_|video_|Add4~7 = CARRY((!\ula_|video_|Add4~5 ) # (!\ula_|video_|vga_vc [4])) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [4]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~5 ), + .combout(\ula_|video_|Add4~6_combout ), + .cout(\ula_|video_|Add4~7 )); +// synopsys translate_off +defparam \ula_|video_|Add4~6 .lut_mask = 16'h3C3F; +defparam \ula_|video_|Add4~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X35_Y30_N17 +dffeas \ula_|video_|vram_address[5] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Add4~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[5] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y30_N18 +cycloneive_lcell_comb \ula_|video_|Add4~8 ( +// Equation(s): +// \ula_|video_|Add4~8_combout = (\ula_|video_|vga_vc [5] & ((GND) # (!\ula_|video_|Add4~7 ))) # (!\ula_|video_|vga_vc [5] & (\ula_|video_|Add4~7 $ (GND))) +// \ula_|video_|Add4~9 = CARRY((\ula_|video_|vga_vc [5]) # (!\ula_|video_|Add4~7 )) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [5]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~7 ), + .combout(\ula_|video_|Add4~8_combout ), + .cout(\ula_|video_|Add4~9 )); +// synopsys translate_off +defparam \ula_|video_|Add4~8 .lut_mask = 16'h3CCF; +defparam \ula_|video_|Add4~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X35_Y30_N19 +dffeas \ula_|video_|vram_address[6] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Add4~8_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[6] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y30_N20 +cycloneive_lcell_comb \ula_|video_|Add4~10 ( +// Equation(s): +// \ula_|video_|Add4~10_combout = (\ula_|video_|vga_vc [6] & (!\ula_|video_|Add4~9 )) # (!\ula_|video_|vga_vc [6] & ((\ula_|video_|Add4~9 ) # (GND))) +// \ula_|video_|Add4~11 = CARRY((!\ula_|video_|Add4~9 ) # (!\ula_|video_|vga_vc [6])) + + .dataa(\ula_|video_|vga_vc [6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~9 ), + .combout(\ula_|video_|Add4~10_combout ), + .cout(\ula_|video_|Add4~11 )); +// synopsys translate_off +defparam \ula_|video_|Add4~10 .lut_mask = 16'h5A5F; +defparam \ula_|video_|Add4~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X35_Y30_N21 +dffeas \ula_|video_|vram_address[7] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Add4~10_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[7] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y30_N22 +cycloneive_lcell_comb \ula_|video_|Add4~12 ( +// Equation(s): +// \ula_|video_|Add4~12_combout = (\ula_|video_|vga_vc [7] & ((GND) # (!\ula_|video_|Add4~11 ))) # (!\ula_|video_|vga_vc [7] & (\ula_|video_|Add4~11 $ (GND))) +// \ula_|video_|Add4~13 = CARRY((\ula_|video_|vga_vc [7]) # (!\ula_|video_|Add4~11 )) + + .dataa(\ula_|video_|vga_vc [7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~11 ), + .combout(\ula_|video_|Add4~12_combout ), + .cout(\ula_|video_|Add4~13 )); +// synopsys translate_off +defparam \ula_|video_|Add4~12 .lut_mask = 16'h5AAF; +defparam \ula_|video_|Add4~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y30_N26 +cycloneive_lcell_comb \ula_|video_|Selector6~0 ( +// Equation(s): +// \ula_|video_|Selector6~0_combout = (\ula_|video_|vga_hc [2] & ((\ula_|video_|Add4~12_combout ))) # (!\ula_|video_|vga_hc [2] & (\ula_|video_|Add4~0_combout )) + + .dataa(gnd), + .datab(\ula_|video_|vga_hc [2]), + .datac(\ula_|video_|Add4~0_combout ), + .datad(\ula_|video_|Add4~12_combout ), + .cin(gnd), + .combout(\ula_|video_|Selector6~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Selector6~0 .lut_mask = 16'hFC30; +defparam \ula_|video_|Selector6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y31_N16 +cycloneive_lcell_comb \ula_|video_|vram_address[9]~1 ( +// Equation(s): +// \ula_|video_|vram_address[9]~1_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [1] $ (\ula_|video_|vga_hc [2])))) + + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|vga_hc [3]), + .datac(\ula_|video_|vga_hc [2]), + .datad(\ula_|video_|vga_hc [0]), + .cin(gnd), + .combout(\ula_|video_|vram_address[9]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address[9]~1 .lut_mask = 16'h0048; +defparam \ula_|video_|vram_address[9]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y30_N27 +dffeas \ula_|video_|vram_address[8] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Selector6~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address[9]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [8]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[8] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y30_N24 +cycloneive_lcell_comb \ula_|video_|Add4~14 ( +// Equation(s): +// \ula_|video_|Add4~14_combout = \ula_|video_|Add4~13 $ (!\ula_|video_|vga_vc [8]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|vga_vc [8]), + .cin(\ula_|video_|Add4~13 ), + .combout(\ula_|video_|Add4~14_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Add4~14 .lut_mask = 16'hF00F; +defparam \ula_|video_|Add4~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y30_N12 +cycloneive_lcell_comb \ula_|video_|Selector5~0 ( +// Equation(s): +// \ula_|video_|Selector5~0_combout = (\ula_|video_|vga_hc [2] & ((\ula_|video_|Add4~14_combout ))) # (!\ula_|video_|vga_hc [2] & (\ula_|video_|Add4~2_combout )) + + .dataa(gnd), + .datab(\ula_|video_|vga_hc [2]), + .datac(\ula_|video_|Add4~2_combout ), + .datad(\ula_|video_|Add4~14_combout ), + .cin(gnd), + .combout(\ula_|video_|Selector5~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Selector5~0 .lut_mask = 16'hFC30; +defparam \ula_|video_|Selector5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y30_N13 +dffeas \ula_|video_|vram_address[9] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Selector5~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address[9]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [9]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[9] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y31_N6 +cycloneive_lcell_comb \ula_|video_|vram_address[10]~2 ( +// Equation(s): +// \ula_|video_|vram_address[10]~2_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [1] $ (\ula_|video_|vga_hc [2])))) + + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|vga_hc [3]), + .datac(\ula_|video_|vga_hc [2]), + .datad(\ula_|video_|vga_hc [0]), + .cin(gnd), + .combout(\ula_|video_|vram_address[10]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address[10]~2 .lut_mask = 16'h0048; +defparam \ula_|video_|vram_address[10]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y31_N28 +cycloneive_lcell_comb \ula_|video_|vram_address[10]~3 ( +// Equation(s): +// \ula_|video_|vram_address[10]~3_combout = (\ula_|video_|vram_address[10]~2_combout & (\ula_|video_|vga_hc [1] & (\ula_|video_|Add4~4_combout ))) # (!\ula_|video_|vram_address[10]~2_combout & (((\ula_|video_|vram_address [10])))) + + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|Add4~4_combout ), + .datac(\ula_|video_|vram_address [10]), + .datad(\ula_|video_|vram_address[10]~2_combout ), + .cin(gnd), + .combout(\ula_|video_|vram_address[10]~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address[10]~3 .lut_mask = 16'h88F0; +defparam \ula_|video_|vram_address[10]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y31_N29 +dffeas \ula_|video_|vram_address[10] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vram_address[10]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [10]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[10] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y30_N6 +cycloneive_lcell_comb \ula_|video_|Selector3~0 ( +// Equation(s): +// \ula_|video_|Selector3~0_combout = (\ula_|video_|vga_hc [2]) # (\ula_|video_|Add4~12_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|video_|vga_hc [2]), + .datad(\ula_|video_|Add4~12_combout ), + .cin(gnd), + .combout(\ula_|video_|Selector3~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Selector3~0 .lut_mask = 16'hFFF0; +defparam \ula_|video_|Selector3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y30_N7 +dffeas \ula_|video_|vram_address[11] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Selector3~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address[9]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [11]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[11] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y30_N8 +cycloneive_lcell_comb \ula_|video_|Selector2~0 ( +// Equation(s): +// \ula_|video_|Selector2~0_combout = (\ula_|video_|vga_hc [2]) # (\ula_|video_|Add4~14_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|video_|vga_hc [2]), + .datad(\ula_|video_|Add4~14_combout ), + .cin(gnd), + .combout(\ula_|video_|Selector2~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Selector2~0 .lut_mask = 16'hFFF0; +defparam \ula_|video_|Selector2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y30_N9 +dffeas \ula_|video_|vram_address[12] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Selector2~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address[9]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [12]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[12] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[12] .power_up = "low"; +// synopsys translate_on + +// Location: M9K_X33_Y26_N0 cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a9 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), @@ -41568,7 +40392,7 @@ cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a9 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[1]~34_combout }), + .portadatain({\D[1]~32_combout }), .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , \z80_|address_pins_|abus[0]~16_combout }), @@ -41625,125 +40449,26 @@ defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 204 defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: M9K_X33_Y32_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a9 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), - .portbdataout()); +// Location: LCCOMB_X29_Y11_N10 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout = (\z80_|address_pins_|abus[14]~23_combout & (\ExtRamWE~0_combout & (!\z80_|address_pins_|abus[15]~22_combout & !\z80_|address_pins_|abus[13]~20_combout ))) + + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\ExtRamWE~0_combout ), + .datac(\z80_|address_pins_|abus[15]~22_combout ), + .datad(\z80_|address_pins_|abus[13]~20_combout ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ), + .cout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h420000004200000000000000000080000000000000000000000000000030004480000000424202423E1E3E02304C3C0C3C7E7E40403E427E3402421824347C1C0400280000003C3406303220344C403C0400100010100000005062742400000091991809FB3BD9084A1241F5015988B3C506031934089E0E1FA8043DDAF2CC07D94A6F2B1D133C211222B22C787D430E45D4C53282288077DFC0F704AAD55127A2BEAEA114958D2817AB1213183A4E1A15E3690A08A33B429284A202011A1243D49CACA1C0A441405A720D21A0921294045F746229E287B95E956AA3DE0CA3B7A019C8039C4DDA6BC99371248CC6008A54CB84503442C4F91309238ECB252072; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h81F3167814687CBD683E54D44555E6C95B5F2A72C0C193C6110C0221A448D0C9A0D8E36A84D5C61285128845215F8F8821C308E368283D8E2B42989C04A8B51354E09A38775020189010680840800297C31282442326D008D1F2351A89FFD7C16087F8B130F04418C0A1C082FC005843F5B42CADD9455ADBD328C13219110DE100D988737BBB44C414210118C673B0C1BDF76C499226F78FF41A0AF7AFD3308AAA0AAA22B1C70003F542A66FD1F1CF9D4578315F8C1C6FEC3EDB9B322CB204821A94A248414CE030020F207BF040A06A3DF993DEA3823423F405294A52014565100E0A7211342DF02958046899EEBE6E491299A09312778193FEBD7FFABA8000; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h2C05EF54A3C0F7F5F017E03F5800377CCF6E493C84E8F56441831087370A084801DEC1A54696B9912E8B0705C8587D4F7D36C8638947A620554CC77819B55B7A12D552A8A0496EFE3AAC6F34739A94E798101823148D811212E9A349CC219049527CCD419525AD29AB7D372C0B56AA0A065F8BDC905346478059EC82801920687FF29C990C9E66273CC78041192D03081CC62A8A0D8CB4D9CF2F2558131A78B8A807C3A1110211AFCA2A142F0BA928156D142250438143D339E4E2079F298493C08C4847914664518E27EF7EB9C870A226AFC35BEDB651840466400D4B3C0F877740114D6B08228BCC693FB12CECCCD2461586069445ACFC910B1241434622B6; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h5FFE6AD3343986C4103935236B6E6E11B940EF46A8FC06E6872A6929D50DCDB75621E625522D34519BF2C353F8AA030B9109C2F9686AD3AF57AF3016D9160354C0BED5FBD379F904A41BAFB6BE4EE9F208058229DD0C354F034A6C4D8B6C16A29F0120108829220B230F44550832C1022530CC13C4C30D8254ECA5200A1941266EE48A1CA6430860DE613153615CAF4C8D191004CE9C6105D8C6795B6484467D21D9DC46029B8376E97F2C7BF8C3A218EE79DDBCF886B2BBDE702F71B38AEC6914E5DCCAFE50CC13922A5B149C598A621F80C24D215291228844E7F33F9763C6639303AE5376F664C7125632C1A280CECD5740C77849D937472B202579964F60; +defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1 .lut_mask = 16'h0008; +defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X33_Y21_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a1 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h35C65240B61076066A23CE4CFC5E76063A1C2AE07DF555007338BDC080EA0C23082C891C76A4845096304A0D8502080C1198911998821D09C29CA830C337499236E0548D65FF9125A765F0220F6EB9D1B318244CC6CA2CBC9CEC6979C14EB28DE2E0440C6CBD61341FC178649A852D4A2A0627C688D905B882524E191E7951EAEF30312A73337CBAD4838F42A3293859CD169240D8E652F6D72D8D19D56DD7675939FC47C933E1B0AEF12A484454C247B00A6BEC5402AA08B5106E3065602454C80CEC08A7F5F85CE65326632B4C4F3920019A35AE2AEB321131046EE45B81D4EFD5995634050D4CFEC166B032B6415553AF0358304080D9DD0A2E5948593830; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h376E511217E00B624A46BA2E4CC10B729C326F710F24CFE78C5E63F3024B17CC5E1380C938A0A16C9B696272DE7A2948BE8AFE81310146B8AAE5E549FA27EFBE27929938B8E10530250877A4998D0DF0004852125C20CA8D4279881E41208B14198817644F293AC1946061117122A39D8841818C1389D51BDAC549181902516571163594CEC5863F0F56625E221D6B8180848C6B2BE24AA0AEEE5D187201CAAE6AA394A8644314895565192AE415630A42894D6EF21343903B348EED8642F2310644C9567C0BF9911B870B989C59330089AA4C8065AB1B11132213EE0FD830817DE6C2ED45D76325CA2A8E198859334553AB02945CAB1F17C142288008073004; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h20721F982534A8179F13E2C6328CDE7D2A73087D3A9314419022103DFF7677769FE2D1F27443253D58403577C801AE23371F00290A17E1C4A40258BFD204230EE9969472A81B83113144528F831AA6C3221E137C1E9C670E26809A894013828D9E2DBCBF62498A769893D7218899245CD18AE49F0146517422EE475D520029ED39BCEF6BF4D23532957455F1C80115524179D59C4C4534DF7296991146CE24508366123AA809AB30B47977571C5D70397A93C723106D0A2C254714359DC7C9E13AE624C94932927924D20024CD638A05C8620023319662D80E05805625BC4A4006C78011F78D8B82E59F0CD4B32D6801669BE3EB0B96960DFF152005EC7C16CB; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h9C8CA06AA05B63C89A59A3E4E80807B27A70B0006624C4AC4A0595CCD8CA20824CA272352720BCD900A6D79BFD9D0595EC0D044ABC8CC28E9AE946E3D2000A4EFA4F91915C6AC9D8570C292F10848189906127BCBE06FFE92DAFB4AAFB240D88DDBB7B207EFA1709B05E1C4801BD45625A36BB62220506E171891964A31BED2215408676F600F490FAA59B488C7998CC8CCC28922AC62644EEBB432EEECB51B16CDEE7468681D6C31E4991CA3736E9ACB7531EC6D8BBCD453718101EA25D79278C6AC955A8A6140421573E413CF5A80AA1436D8B4C31A2AB26D2A61CE834248BAD5751BD429B4F61318427560CE39D49299002165212181064E24FF0093B997B; -// synopsys translate_on - -// Location: M9K_X33_Y22_N0 +// Location: M9K_X33_Y30_N0 cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a1 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), @@ -41757,7 +40482,7 @@ cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a1 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[1]~34_combout }), + .portadatain({\D[1]~32_combout }), .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , \z80_|address_pins_|abus[0]~16_combout }), @@ -41813,2095 +40538,104 @@ defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 204 defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'hCB9C84F288C855028DE04086AC0122869175A48288D30882FFFFFFFCC0000002CB9C80B78DD447828DE440828C0126829175840280D10B82FFFFFFFDE0408082C8D480838FD45582881C4482840160028179800280510B82C0000001BFFFFFFE8AD480BA8F844182880860828601660A8179900280510B02800000009FBF7F7C8B90A1328C8401828BE0608A86836E1281791012805107029FBF7F7D800000008B9883228C9405828BE0728286832E0281799042C0500F43BFFFFFFF80000000889081128FD400828A0066828782288281199002C0401F03A0408083FFFFFFFF888881128FE440828800268287D22CE280199022A0003F00E0408080FFFFFFFF; // synopsys translate_on -// Location: LCCOMB_X32_Y18_N0 +// Location: LCCOMB_X30_Y10_N20 cycloneive_lcell_comb \Selector1~0 ( // Equation(s): -// \Selector1~0_combout = (\z80_|address_pins_|abus[14]~23_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout )))) # (!\z80_|address_pins_|abus[14]~23_combout -// & (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ))) +// \Selector1~0_combout = (\z80_|address_pins_|abus[14]~23_combout & ((\Selector3~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout )) # (!\Selector3~0_combout & +// ((\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ))))) # (!\z80_|address_pins_|abus[14]~23_combout & (\Selector3~0_combout )) .dataa(\z80_|address_pins_|abus[14]~23_combout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ), + .datab(\Selector3~0_combout ), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout ), .datad(\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ), .cin(gnd), .combout(\Selector1~0_combout ), .cout()); // synopsys translate_off -defparam \Selector1~0 .lut_mask = 16'hBA98; +defparam \Selector1~0 .lut_mask = 16'hE6C4; defparam \Selector1~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y18_N2 +// Location: LCCOMB_X30_Y10_N22 cycloneive_lcell_comb \Selector1~1 ( // Equation(s): -// \Selector1~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Selector1~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout )) # (!\Selector1~0_combout & -// ((\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Selector1~0_combout )))) +// \Selector1~1_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\Selector1~0_combout )))) # (!\z80_|address_pins_|abus[14]~23_combout & ((\Selector1~0_combout & ((\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ))) # +// (!\Selector1~0_combout & (\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout )))) - .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ), .datac(\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ), .datad(\Selector1~0_combout ), .cin(gnd), .combout(\Selector1~1_combout ), .cout()); // synopsys translate_off -defparam \Selector1~1 .lut_mask = 16'hBBC0; +defparam \Selector1~1 .lut_mask = 16'hFA44; defparam \Selector1~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y18_N12 -cycloneive_lcell_comb \D[1]~103 ( +// Location: LCCOMB_X31_Y10_N28 +cycloneive_lcell_comb \D[1]~81 ( // Equation(s): -// \D[1]~103_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [15] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\Selector1~1_combout -// ))))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout )))) +// \D[1]~81_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\Selector1~1_combout ))) +// # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout )))) - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .dataa(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ), .datab(\z80_|address_pins_|DFFE_apin_latch [15]), - .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .datad(\Selector1~1_combout ), .cin(gnd), - .combout(\D[1]~103_combout ), + .combout(\D[1]~81_combout ), .cout()); // synopsys translate_off -defparam \D[1]~103 .lut_mask = 16'hF2D0; -defparam \D[1]~103 .sum_lutc_input = "datac"; +defparam \D[1]~81 .lut_mask = 16'hBA8A; +defparam \D[1]~81 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: IOIBUF_X18_Y34_N1 -cycloneive_io_ibuf \PS2_DAT~input ( - .i(PS2_DAT), - .ibar(gnd), - .o(\PS2_DAT~input_o )); -// synopsys translate_off -defparam \PS2_DAT~input .bus_hold = "false"; -defparam \PS2_DAT~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: CLKCTRL_G5 -cycloneive_clkctrl \reset~clkctrl ( - .ena(vcc), - .inclk({vcc,vcc,vcc,\reset~combout }), - .clkselect(2'b00), - .devclrn(devclrn), - .devpor(devpor), - .outclk(\reset~clkctrl_outclk )); -// synopsys translate_off -defparam \reset~clkctrl .clock_type = "global clock"; -defparam \reset~clkctrl .ena_register_mode = "none"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y21_N2 -cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|bit_count~0_combout = (!\ula_|ps2_keyboard_|bit_count [0] & (((!\ula_|ps2_keyboard_|bit_count [1] & !\ula_|ps2_keyboard_|bit_count [2])) # (!\ula_|ps2_keyboard_|bit_count [3]))) - - .dataa(\ula_|ps2_keyboard_|bit_count [1]), - .datab(\ula_|ps2_keyboard_|bit_count [3]), - .datac(\ula_|ps2_keyboard_|bit_count [0]), - .datad(\ula_|ps2_keyboard_|bit_count [2]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|bit_count~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count~0 .lut_mask = 16'h0307; -defparam \ula_|ps2_keyboard_|bit_count~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: IOIBUF_X9_Y34_N8 -cycloneive_io_ibuf \PS2_CLK~input ( - .i(PS2_CLK), - .ibar(gnd), - .o(\PS2_CLK~input_o )); -// synopsys translate_off -defparam \PS2_CLK~input .bus_hold = "false"; -defparam \PS2_CLK~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N0 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[7]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[7]~feeder_combout = \PS2_CLK~input_o - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\PS2_CLK~input_o ), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[7]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[7]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y26_N1 -dffeas \ula_|ps2_keyboard_|clk_filter[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[7] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N6 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[6]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[6]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [7] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [7]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[6]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[6]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y26_N7 -dffeas \ula_|ps2_keyboard_|clk_filter[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[6] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N20 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[5]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[5]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [6] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [6]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[5]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[5]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y26_N21 -dffeas \ula_|ps2_keyboard_|clk_filter[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[5] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N18 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[4]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[4]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [5] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [5]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[4]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[4]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y26_N19 -dffeas \ula_|ps2_keyboard_|clk_filter[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[4] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N12 -cycloneive_lcell_comb \ula_|ps2_keyboard_|Equal0~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|Equal0~0_combout = (!\ula_|ps2_keyboard_|clk_filter [6] & (!\ula_|ps2_keyboard_|clk_filter [7] & (!\ula_|ps2_keyboard_|clk_filter [5] & !\ula_|ps2_keyboard_|clk_filter [4]))) - - .dataa(\ula_|ps2_keyboard_|clk_filter [6]), - .datab(\ula_|ps2_keyboard_|clk_filter [7]), - .datac(\ula_|ps2_keyboard_|clk_filter [5]), - .datad(\ula_|ps2_keyboard_|clk_filter [4]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|Equal0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|Equal0~0 .lut_mask = 16'h0001; -defparam \ula_|ps2_keyboard_|Equal0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N2 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[3]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[3]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [4] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [4]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[3]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[3]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[3]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y26_N3 -dffeas \ula_|ps2_keyboard_|clk_filter[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[3]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[3] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N28 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[2]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[2]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [3] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [3]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[2]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y26_N29 -dffeas \ula_|ps2_keyboard_|clk_filter[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[2] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N22 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[1]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[1]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [2] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [2]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[1]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y26_N23 -dffeas \ula_|ps2_keyboard_|clk_filter[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[1] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N16 -cycloneive_lcell_comb \ula_|ps2_keyboard_|Equal0~1 ( -// Equation(s): -// \ula_|ps2_keyboard_|Equal0~1_combout = (\ula_|ps2_keyboard_|Equal0~0_combout & (!\ula_|ps2_keyboard_|clk_filter [2] & (!\ula_|ps2_keyboard_|clk_filter [1] & !\ula_|ps2_keyboard_|clk_filter [3]))) - - .dataa(\ula_|ps2_keyboard_|Equal0~0_combout ), - .datab(\ula_|ps2_keyboard_|clk_filter [2]), - .datac(\ula_|ps2_keyboard_|clk_filter [1]), - .datad(\ula_|ps2_keyboard_|clk_filter [3]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|Equal0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|Equal0~1 .lut_mask = 16'h0002; -defparam \ula_|ps2_keyboard_|Equal0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N10 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[0]~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[0]~0_combout = !\ula_|ps2_keyboard_|clk_filter [1] - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|clk_filter [1]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[0]~0 .lut_mask = 16'h0F0F; -defparam \ula_|ps2_keyboard_|clk_filter[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y26_N11 -dffeas \ula_|ps2_keyboard_|clk_filter[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[0]~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[0] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N26 -cycloneive_lcell_comb \ula_|ps2_keyboard_|ps2_clk_in~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|ps2_clk_in~0_combout = (\ula_|ps2_keyboard_|Equal0~1_combout & ((\ula_|ps2_keyboard_|clk_filter [0]))) # (!\ula_|ps2_keyboard_|Equal0~1_combout & (\ula_|ps2_keyboard_|ps2_clk_in~q )) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|Equal0~1_combout ), - .datac(\ula_|ps2_keyboard_|ps2_clk_in~q ), - .datad(\ula_|ps2_keyboard_|clk_filter [0]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|ps2_clk_in~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|ps2_clk_in~0 .lut_mask = 16'hFC30; -defparam \ula_|ps2_keyboard_|ps2_clk_in~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y26_N27 -dffeas \ula_|ps2_keyboard_|ps2_clk_in ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|ps2_clk_in~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|ps2_clk_in~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|ps2_clk_in .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|ps2_clk_in .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N4 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_edge~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_edge~0_combout = (\ula_|ps2_keyboard_|Equal0~1_combout & (!\ula_|ps2_keyboard_|ps2_clk_in~q & \ula_|ps2_keyboard_|clk_filter [0])) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|Equal0~1_combout ), - .datac(\ula_|ps2_keyboard_|ps2_clk_in~q ), - .datad(\ula_|ps2_keyboard_|clk_filter [0]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_edge~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_edge~0 .lut_mask = 16'h0C00; -defparam \ula_|ps2_keyboard_|clk_edge~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y26_N5 -dffeas \ula_|ps2_keyboard_|clk_edge ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_edge~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_edge~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_edge .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_edge .power_up = "low"; -// synopsys translate_on - -// Location: FF_X26_Y21_N3 -dffeas \ula_|ps2_keyboard_|bit_count[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|bit_count~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|ps2_keyboard_|clk_edge~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|bit_count [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count[0] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|bit_count[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y21_N0 -cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~1 ( -// Equation(s): -// \ula_|ps2_keyboard_|bit_count~1_combout = (!\ula_|ps2_keyboard_|bit_count [3] & (\ula_|ps2_keyboard_|bit_count [2] $ (((\ula_|ps2_keyboard_|bit_count [1] & \ula_|ps2_keyboard_|bit_count [0]))))) - - .dataa(\ula_|ps2_keyboard_|bit_count [1]), - .datab(\ula_|ps2_keyboard_|bit_count [3]), - .datac(\ula_|ps2_keyboard_|bit_count [2]), - .datad(\ula_|ps2_keyboard_|bit_count [0]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|bit_count~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count~1 .lut_mask = 16'h1230; -defparam \ula_|ps2_keyboard_|bit_count~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y21_N1 -dffeas \ula_|ps2_keyboard_|bit_count[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|bit_count~1_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|ps2_keyboard_|clk_edge~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|bit_count [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count[2] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|bit_count[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y21_N16 -cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~3 ( -// Equation(s): -// \ula_|ps2_keyboard_|bit_count~3_combout = (\ula_|ps2_keyboard_|bit_count [1] & (\ula_|ps2_keyboard_|bit_count [2] & (!\ula_|ps2_keyboard_|bit_count [3] & \ula_|ps2_keyboard_|bit_count [0]))) # (!\ula_|ps2_keyboard_|bit_count [1] & -// (!\ula_|ps2_keyboard_|bit_count [2] & (\ula_|ps2_keyboard_|bit_count [3]))) - - .dataa(\ula_|ps2_keyboard_|bit_count [1]), - .datab(\ula_|ps2_keyboard_|bit_count [2]), - .datac(\ula_|ps2_keyboard_|bit_count [3]), - .datad(\ula_|ps2_keyboard_|bit_count [0]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|bit_count~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count~3 .lut_mask = 16'h1810; -defparam \ula_|ps2_keyboard_|bit_count~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y21_N17 -dffeas \ula_|ps2_keyboard_|bit_count[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|bit_count~3_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|ps2_keyboard_|clk_edge~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|bit_count [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count[3] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|bit_count[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y21_N26 -cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~2 ( -// Equation(s): -// \ula_|ps2_keyboard_|bit_count~2_combout = (\ula_|ps2_keyboard_|bit_count [3] & (!\ula_|ps2_keyboard_|bit_count [2] & (!\ula_|ps2_keyboard_|bit_count [1] & \ula_|ps2_keyboard_|bit_count [0]))) # (!\ula_|ps2_keyboard_|bit_count [3] & -// ((\ula_|ps2_keyboard_|bit_count [1] $ (\ula_|ps2_keyboard_|bit_count [0])))) - - .dataa(\ula_|ps2_keyboard_|bit_count [3]), - .datab(\ula_|ps2_keyboard_|bit_count [2]), - .datac(\ula_|ps2_keyboard_|bit_count [1]), - .datad(\ula_|ps2_keyboard_|bit_count [0]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|bit_count~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count~2 .lut_mask = 16'h0750; -defparam \ula_|ps2_keyboard_|bit_count~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y21_N27 -dffeas \ula_|ps2_keyboard_|bit_count[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|bit_count~2_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|ps2_keyboard_|clk_edge~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|bit_count [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count[1] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|bit_count[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y21_N22 -cycloneive_lcell_comb \ula_|ps2_keyboard_|always1~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|always1~0_combout = (!\ula_|ps2_keyboard_|bit_count [1] & (!\ula_|ps2_keyboard_|bit_count [3] & (!\PS2_DAT~input_o & !\ula_|ps2_keyboard_|bit_count [2]))) - - .dataa(\ula_|ps2_keyboard_|bit_count [1]), - .datab(\ula_|ps2_keyboard_|bit_count [3]), - .datac(\PS2_DAT~input_o ), - .datad(\ula_|ps2_keyboard_|bit_count [2]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|always1~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|always1~0 .lut_mask = 16'h0001; -defparam \ula_|ps2_keyboard_|always1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y21_N12 -cycloneive_lcell_comb \ula_|ps2_keyboard_|LessThan0~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|LessThan0~0_combout = (\ula_|ps2_keyboard_|bit_count [3] & ((\ula_|ps2_keyboard_|bit_count [1]) # (\ula_|ps2_keyboard_|bit_count [2]))) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|bit_count [3]), - .datac(\ula_|ps2_keyboard_|bit_count [1]), - .datad(\ula_|ps2_keyboard_|bit_count [2]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|LessThan0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|LessThan0~0 .lut_mask = 16'hCCC0; -defparam \ula_|ps2_keyboard_|LessThan0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y21_N6 -cycloneive_lcell_comb \ula_|ps2_keyboard_|shiftreg[0]~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|shiftreg[0]~0_combout = (\ula_|ps2_keyboard_|clk_edge~q & (!\ula_|ps2_keyboard_|LessThan0~0_combout & ((\ula_|ps2_keyboard_|bit_count [0]) # (!\ula_|ps2_keyboard_|always1~0_combout )))) - - .dataa(\ula_|ps2_keyboard_|always1~0_combout ), - .datab(\ula_|ps2_keyboard_|bit_count [0]), - .datac(\ula_|ps2_keyboard_|clk_edge~q ), - .datad(\ula_|ps2_keyboard_|LessThan0~0_combout ), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[0]~0 .lut_mask = 16'h00D0; -defparam \ula_|ps2_keyboard_|shiftreg[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y21_N9 -dffeas \ula_|ps2_keyboard_|shiftreg[8] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\PS2_DAT~input_o ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [8]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[8] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[8] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y21_N15 -dffeas \ula_|ps2_keyboard_|shiftreg[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [8]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[7] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y21_N5 -dffeas \ula_|ps2_keyboard_|shiftreg[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [7]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[6] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y21_N11 -dffeas \ula_|ps2_keyboard_|shiftreg[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [6]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[5] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y21_N11 -dffeas \ula_|ps2_keyboard_|shiftreg[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [5]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[4] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y21_N25 -dffeas \ula_|ps2_keyboard_|shiftreg[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [4]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[3] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y21_N29 -dffeas \ula_|ps2_keyboard_|shiftreg[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [3]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[2] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y21_N1 -dffeas \ula_|ps2_keyboard_|shiftreg[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [2]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[1] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y21_N17 -dffeas \ula_|ps2_keyboard_|shiftreg[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [1]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[0] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~0 ( -// Equation(s): -// \ula_|zx_keyboard_|Equal0~0_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [7] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [5]), - .datab(\ula_|ps2_keyboard_|shiftreg [7]), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|Equal0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|Equal0~0 .lut_mask = 16'h0008; -defparam \ula_|zx_keyboard_|Equal0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~1 ( -// Equation(s): -// \ula_|zx_keyboard_|Equal0~1_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|Equal0~0_combout & !\ula_|ps2_keyboard_|shiftreg [1]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|zx_keyboard_|Equal0~0_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|Equal0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|Equal0~1 .lut_mask = 16'h0020; -defparam \ula_|zx_keyboard_|Equal0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|extended~0 ( -// Equation(s): -// \ula_|zx_keyboard_|extended~0_combout = (\ula_|zx_keyboard_|Equal0~1_combout & ((\ula_|zx_keyboard_|extended~q ) # (!\ula_|ps2_keyboard_|shiftreg [4]))) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [4]), - .datac(\ula_|zx_keyboard_|extended~q ), - .datad(\ula_|zx_keyboard_|Equal0~1_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|extended~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|extended~0 .lut_mask = 16'hF300; -defparam \ula_|zx_keyboard_|extended~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y21_N8 -cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~1 ( -// Equation(s): -// \ula_|ps2_keyboard_|WideXor0~1_combout = \ula_|ps2_keyboard_|shiftreg [6] $ (\ula_|ps2_keyboard_|shiftreg [7] $ (\ula_|ps2_keyboard_|shiftreg [8] $ (\ula_|ps2_keyboard_|shiftreg [5]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|ps2_keyboard_|shiftreg [7]), - .datac(\ula_|ps2_keyboard_|shiftreg [8]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|WideXor0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|WideXor0~1 .lut_mask = 16'h6996; -defparam \ula_|ps2_keyboard_|WideXor0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y21_N0 -cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|WideXor0~0_combout = \ula_|ps2_keyboard_|shiftreg [2] $ (\ula_|ps2_keyboard_|shiftreg [0] $ (\ula_|ps2_keyboard_|shiftreg [1] $ (\ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|WideXor0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|WideXor0~0 .lut_mask = 16'h6996; -defparam \ula_|ps2_keyboard_|WideXor0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y21_N6 -cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~2 ( -// Equation(s): -// \ula_|ps2_keyboard_|WideXor0~2_combout = \ula_|ps2_keyboard_|shiftreg [4] $ (\ula_|ps2_keyboard_|WideXor0~1_combout $ (\ula_|ps2_keyboard_|WideXor0~0_combout )) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [4]), - .datac(\ula_|ps2_keyboard_|WideXor0~1_combout ), - .datad(\ula_|ps2_keyboard_|WideXor0~0_combout ), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|WideXor0~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|WideXor0~2 .lut_mask = 16'hC33C; -defparam \ula_|ps2_keyboard_|WideXor0~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y21_N8 -cycloneive_lcell_comb \ula_|ps2_keyboard_|scan_code_ready~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|scan_code_ready~0_combout = (\ula_|ps2_keyboard_|LessThan0~0_combout & (\PS2_DAT~input_o & (\ula_|ps2_keyboard_|clk_edge~q & \ula_|ps2_keyboard_|WideXor0~2_combout ))) - - .dataa(\ula_|ps2_keyboard_|LessThan0~0_combout ), - .datab(\PS2_DAT~input_o ), - .datac(\ula_|ps2_keyboard_|clk_edge~q ), - .datad(\ula_|ps2_keyboard_|WideXor0~2_combout ), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|scan_code_ready~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|scan_code_ready~0 .lut_mask = 16'h8000; -defparam \ula_|ps2_keyboard_|scan_code_ready~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y21_N9 -dffeas \ula_|ps2_keyboard_|scan_code_ready ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|scan_code_ready~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|scan_code_ready~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|scan_code_ready .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|scan_code_ready .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y20_N1 -dffeas \ula_|zx_keyboard_|extended ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|extended~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|ps2_keyboard_|scan_code_ready~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|extended~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|extended .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|extended .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y21_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~15 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][0]~15_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (!\ula_|zx_keyboard_|Equal0~1_combout & !\ula_|ps2_keyboard_|shiftreg [7])) - - .dataa(\ula_|ps2_keyboard_|scan_code_ready~q ), - .datab(\ula_|zx_keyboard_|Equal0~1_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [7]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][0]~15 .lut_mask = 16'h0202; -defparam \ula_|zx_keyboard_|keys[0][0]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~36 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][1]~36_combout = (!\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[0][0]~15_combout )) - - .dataa(\ula_|zx_keyboard_|extended~q ), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][1]~36_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1]~36 .lut_mask = 16'h0500; -defparam \ula_|zx_keyboard_|keys[5][1]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~37 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][1]~37_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[5][1]~36_combout & \ula_|ps2_keyboard_|shiftreg [2])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[5][1]~36_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][1]~37_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1]~37 .lut_mask = 16'hA000; -defparam \ula_|zx_keyboard_|keys[5][1]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~0 ( -// Equation(s): -// \ula_|zx_keyboard_|shifted~0_combout = (\ula_|zx_keyboard_|keys[0][0]~15_combout & (!\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|zx_keyboard_|extended~q )) - - .dataa(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|zx_keyboard_|extended~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|shifted~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|shifted~0 .lut_mask = 16'h000A; -defparam \ula_|zx_keyboard_|shifted~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y21_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|released~0 ( -// Equation(s): -// \ula_|zx_keyboard_|released~0_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (\ula_|zx_keyboard_|Equal0~1_combout & ((\ula_|ps2_keyboard_|shiftreg [4]) # (\ula_|zx_keyboard_|released~q )))) # (!\ula_|ps2_keyboard_|scan_code_ready~q & -// (((\ula_|zx_keyboard_|released~q )))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|zx_keyboard_|Equal0~1_combout ), - .datac(\ula_|zx_keyboard_|released~q ), - .datad(\ula_|ps2_keyboard_|scan_code_ready~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|released~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|released~0 .lut_mask = 16'hC8F0; -defparam \ula_|zx_keyboard_|released~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y21_N19 -dffeas \ula_|zx_keyboard_|released ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|released~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|released~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|released .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|released .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr17~0 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr17~0_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [0]))) # (!\ula_|ps2_keyboard_|shiftreg [1] & -// (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [0]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr17~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr17~0 .lut_mask = 16'h4002; -defparam \ula_|zx_keyboard_|WideOr17~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~2 ( -// Equation(s): -// \ula_|zx_keyboard_|shifted~2_combout = (\ula_|zx_keyboard_|WideOr17~0_combout & (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [4])) - - .dataa(\ula_|zx_keyboard_|WideOr17~0_combout ), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|shifted~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|shifted~2 .lut_mask = 16'h0A00; -defparam \ula_|zx_keyboard_|shifted~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~3 ( -// Equation(s): -// \ula_|zx_keyboard_|shifted~3_combout = (\ula_|zx_keyboard_|shifted~0_combout & ((\ula_|zx_keyboard_|shifted~2_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|shifted~2_combout & ((\ula_|zx_keyboard_|shifted~q ))))) # -// (!\ula_|zx_keyboard_|shifted~0_combout & (((\ula_|zx_keyboard_|shifted~q )))) - - .dataa(\ula_|zx_keyboard_|shifted~0_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|shifted~q ), - .datad(\ula_|zx_keyboard_|shifted~2_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|shifted~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|shifted~3 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|shifted~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y21_N3 -dffeas \ula_|zx_keyboard_|shifted ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|shifted~3_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|shifted~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|shifted .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|shifted .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~35 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][1]~35_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [3])) - - .dataa(\ula_|zx_keyboard_|shifted~q ), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(gnd), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][1]~35_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1]~35 .lut_mask = 16'hFF88; -defparam \ula_|zx_keyboard_|keys[5][1]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~38 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][1]~38_combout = (!\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [0])) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][1]~38_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1]~38 .lut_mask = 16'h0003; -defparam \ula_|zx_keyboard_|keys[5][1]~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~39 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][1]~39_combout = (\ula_|zx_keyboard_|keys[5][1]~37_combout & ((\ula_|zx_keyboard_|keys[5][1]~38_combout & (!\ula_|zx_keyboard_|keys[5][1]~35_combout )) # (!\ula_|zx_keyboard_|keys[5][1]~38_combout & -// ((\ula_|zx_keyboard_|keys[5][1]~q ))))) # (!\ula_|zx_keyboard_|keys[5][1]~37_combout & (((\ula_|zx_keyboard_|keys[5][1]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[5][1]~37_combout ), - .datab(\ula_|zx_keyboard_|keys[5][1]~35_combout ), - .datac(\ula_|zx_keyboard_|keys[5][1]~q ), - .datad(\ula_|zx_keyboard_|keys[5][1]~38_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][1]~39_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1]~39 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[5][1]~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y18_N19 -dffeas \ula_|zx_keyboard_|keys[5][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[5][1]~39_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[5][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[5][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][1]~31 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][1]~31_combout = (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [0]) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][1]~31_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][1]~31 .lut_mask = 16'h00CC; -defparam \ula_|zx_keyboard_|keys[4][1]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y21_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~23 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][1]~23_combout = (!\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [7] & \ula_|ps2_keyboard_|scan_code_ready~q )) - - .dataa(\ula_|zx_keyboard_|extended~q ), - .datab(\ula_|ps2_keyboard_|shiftreg [7]), - .datac(\ula_|ps2_keyboard_|scan_code_ready~q ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][1]~23_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][1]~23 .lut_mask = 16'h1010; -defparam \ula_|zx_keyboard_|keys[7][1]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y21_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~32 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~32_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [4])) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~32_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~32 .lut_mask = 16'h000C; -defparam \ula_|zx_keyboard_|keys[7][2]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y21_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~33 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][2]~33_combout = (\ula_|zx_keyboard_|keys[7][1]~23_combout & (\ula_|zx_keyboard_|keys[7][2]~32_combout & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|zx_keyboard_|keys[7][1]~23_combout ), - .datab(\ula_|zx_keyboard_|keys[7][2]~32_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][2]~33_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][2]~33 .lut_mask = 16'h0080; -defparam \ula_|zx_keyboard_|keys[5][2]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][1]~34 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][1]~34_combout = (\ula_|zx_keyboard_|keys[4][1]~31_combout & ((\ula_|zx_keyboard_|keys[5][2]~33_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[5][2]~33_combout & (\ula_|zx_keyboard_|keys[4][1]~q -// )))) # (!\ula_|zx_keyboard_|keys[4][1]~31_combout & (((\ula_|zx_keyboard_|keys[4][1]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[4][1]~31_combout ), - .datab(\ula_|zx_keyboard_|keys[5][2]~33_combout ), - .datac(\ula_|zx_keyboard_|keys[4][1]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][1]~34_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][1]~34 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[4][1]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y18_N9 -dffeas \ula_|zx_keyboard_|keys[4][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[4][1]~34_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[4][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[4][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N24 -cycloneive_lcell_comb \D[1]~30 ( -// Equation(s): -// \D[1]~30_combout = (\z80_|address_pins_|abus[13]~20_combout & (((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][1]~q )))) # (!\z80_|address_pins_|abus[13]~20_combout & (!\ula_|zx_keyboard_|keys[5][1]~q & -// ((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][1]~q )))) - - .dataa(\z80_|address_pins_|abus[13]~20_combout ), - .datab(\ula_|zx_keyboard_|keys[5][1]~q ), - .datac(\ula_|zx_keyboard_|keys[4][1]~q ), - .datad(\z80_|address_pins_|abus[12]~21_combout ), - .cin(gnd), - .combout(\D[1]~30_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~30 .lut_mask = 16'hBB0B; -defparam \D[1]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~24 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][4]~24_combout = (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [2]) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][4]~24_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][4]~24 .lut_mask = 16'hA0A0; -defparam \ula_|zx_keyboard_|keys[5][4]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~28 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][1]~28_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[7][1]~23_combout & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[5][4]~24_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|zx_keyboard_|keys[7][1]~23_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|zx_keyboard_|keys[5][4]~24_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][1]~28_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][1]~28 .lut_mask = 16'h0400; -defparam \ula_|zx_keyboard_|keys[3][1]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~29 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][1]~29_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [0])) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][1]~29_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][1]~29 .lut_mask = 16'h00C0; -defparam \ula_|zx_keyboard_|keys[3][1]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~30 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][1]~30_combout = (\ula_|zx_keyboard_|keys[3][1]~28_combout & ((\ula_|zx_keyboard_|keys[3][1]~29_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][1]~29_combout & ((\ula_|zx_keyboard_|keys[3][1]~q -// ))))) # (!\ula_|zx_keyboard_|keys[3][1]~28_combout & (((\ula_|zx_keyboard_|keys[3][1]~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[3][1]~28_combout ), - .datac(\ula_|zx_keyboard_|keys[3][1]~q ), - .datad(\ula_|zx_keyboard_|keys[3][1]~29_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][1]~30_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][1]~30 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[3][1]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y18_N17 -dffeas \ula_|zx_keyboard_|keys[3][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[3][1]~30_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[3][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[3][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][4]~25 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][4]~25_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[5][4]~24_combout & (\ula_|zx_keyboard_|keys[7][1]~23_combout & !\ula_|ps2_keyboard_|shiftreg [1]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|zx_keyboard_|keys[5][4]~24_combout ), - .datac(\ula_|zx_keyboard_|keys[7][1]~23_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][4]~25_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][4]~25 .lut_mask = 16'h0040; -defparam \ula_|zx_keyboard_|keys[1][4]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][1]~26 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][1]~26_combout = (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|zx_keyboard_|keys[1][4]~25_combout & \ula_|ps2_keyboard_|shiftreg [0])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [5]), - .datab(\ula_|zx_keyboard_|keys[1][4]~25_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][1]~26_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][1]~26 .lut_mask = 16'h4040; -defparam \ula_|zx_keyboard_|keys[2][1]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][1]~27 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][1]~27_combout = (\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[2][1]~26_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[2][1]~26_combout & ((\ula_|zx_keyboard_|keys[2][1]~q ))))) # -// (!\ula_|ps2_keyboard_|shiftreg [3] & (((\ula_|zx_keyboard_|keys[2][1]~q )))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[2][1]~q ), - .datad(\ula_|zx_keyboard_|keys[2][1]~26_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][1]~27_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][1]~27 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[2][1]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y20_N17 -dffeas \ula_|zx_keyboard_|keys[2][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[2][1]~27_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[2][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[2][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~0 ( -// Equation(s): -// \ula_|zx_keyboard_|key_row~0_combout = ((\z80_|address_pins_|DFFE_apin_latch [10]) # (!\ula_|zx_keyboard_|keys[2][1]~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [10]), - .datad(\ula_|zx_keyboard_|keys[2][1]~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|key_row~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|key_row~0 .lut_mask = 16'hF3FF; -defparam \ula_|zx_keyboard_|key_row~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~14 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][1]~14_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & !\ula_|ps2_keyboard_|shiftreg [4])) - - .dataa(gnd), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|shifted~q ), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][1]~14_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][1]~14 .lut_mask = 16'hCCCF; -defparam \ula_|zx_keyboard_|keys[0][1]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~16 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][1]~16_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [4] $ (\ula_|ps2_keyboard_|shiftreg [2])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][1]~16_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][1]~16 .lut_mask = 16'h0060; -defparam \ula_|zx_keyboard_|keys[0][1]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~17 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][1]~17_combout = (\ula_|zx_keyboard_|keys[0][1]~16_combout & ((\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [4])) # (!\ula_|ps2_keyboard_|shiftreg [1] & -// (\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [4])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|zx_keyboard_|keys[0][1]~16_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][1]~17_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][1]~17 .lut_mask = 16'h2040; -defparam \ula_|zx_keyboard_|keys[0][1]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~18 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][1]~18_combout = (\ula_|zx_keyboard_|shifted~0_combout & ((\ula_|zx_keyboard_|keys[0][1]~17_combout & (!\ula_|zx_keyboard_|keys[0][1]~14_combout )) # (!\ula_|zx_keyboard_|keys[0][1]~17_combout & -// ((\ula_|zx_keyboard_|keys[0][1]~q ))))) # (!\ula_|zx_keyboard_|shifted~0_combout & (((\ula_|zx_keyboard_|keys[0][1]~q )))) - - .dataa(\ula_|zx_keyboard_|shifted~0_combout ), - .datab(\ula_|zx_keyboard_|keys[0][1]~14_combout ), - .datac(\ula_|zx_keyboard_|keys[0][1]~q ), - .datad(\ula_|zx_keyboard_|keys[0][1]~17_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][1]~18_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][1]~18 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[0][1]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y21_N7 -dffeas \ula_|zx_keyboard_|keys[0][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[0][1]~18_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[0][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[0][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~19 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][4]~19_combout = (!\ula_|ps2_keyboard_|shiftreg [7] & (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|zx_keyboard_|extended~q & \ula_|ps2_keyboard_|scan_code_ready~q ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [7]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|zx_keyboard_|extended~q ), - .datad(\ula_|ps2_keyboard_|scan_code_ready~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][4]~19_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][4]~19 .lut_mask = 16'h0100; -defparam \ula_|zx_keyboard_|keys[7][4]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~20 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][4]~20_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [2]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [0]), - .datab(\ula_|ps2_keyboard_|shiftreg [4]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][4]~20_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][4]~20 .lut_mask = 16'h0080; -defparam \ula_|zx_keyboard_|keys[6][4]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][1]~21 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][1]~21_combout = (\ula_|zx_keyboard_|keys[7][4]~19_combout & (\ula_|zx_keyboard_|keys[6][4]~20_combout & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|zx_keyboard_|keys[7][4]~19_combout ), - .datab(\ula_|zx_keyboard_|keys[6][4]~20_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][1]~21_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][1]~21 .lut_mask = 16'h0800; -defparam \ula_|zx_keyboard_|keys[1][1]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][1]~22 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][1]~22_combout = (\ula_|zx_keyboard_|keys[1][1]~21_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[1][1]~21_combout & (\ula_|zx_keyboard_|keys[1][1]~q )) - - .dataa(gnd), - .datab(\ula_|zx_keyboard_|keys[1][1]~21_combout ), - .datac(\ula_|zx_keyboard_|keys[1][1]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][1]~22_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][1]~22 .lut_mask = 16'h30FC; -defparam \ula_|zx_keyboard_|keys[1][1]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y20_N13 -dffeas \ula_|zx_keyboard_|keys[1][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[1][1]~22_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[1][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[1][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N2 -cycloneive_lcell_comb \D[1]~28 ( -// Equation(s): -// \D[1]~28_combout = (\ula_|zx_keyboard_|keys[0][1]~q & (\z80_|address_pins_|abus[8]~18_combout & ((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][1]~q )))) # (!\ula_|zx_keyboard_|keys[0][1]~q & -// (((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][1]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[0][1]~q ), - .datab(\z80_|address_pins_|abus[8]~18_combout ), - .datac(\z80_|address_pins_|abus[9]~17_combout ), - .datad(\ula_|zx_keyboard_|keys[1][1]~q ), - .cin(gnd), - .combout(\D[1]~28_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~28 .lut_mask = 16'hD0DD; -defparam \D[1]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N26 -cycloneive_lcell_comb \D[1]~29 ( -// Equation(s): -// \D[1]~29_combout = (\ula_|zx_keyboard_|key_row~0_combout & (\D[1]~28_combout & ((\z80_|address_pins_|abus[11]~19_combout ) # (!\ula_|zx_keyboard_|keys[3][1]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[3][1]~q ), - .datab(\ula_|zx_keyboard_|key_row~0_combout ), - .datac(\z80_|address_pins_|abus[11]~19_combout ), - .datad(\D[1]~28_combout ), - .cin(gnd), - .combout(\D[1]~29_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~29 .lut_mask = 16'hC400; -defparam \D[1]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~41 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][1]~41_combout = (!\ula_|zx_keyboard_|extended~q & (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[0][0]~15_combout ))) - - .dataa(\ula_|zx_keyboard_|extended~q ), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][1]~41_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1]~41 .lut_mask = 16'h0400; -defparam \ula_|zx_keyboard_|keys[6][1]~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~42 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][1]~42_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [3]))) # (!\ula_|ps2_keyboard_|shiftreg [1] & -// (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][1]~42_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1]~42 .lut_mask = 16'h0240; -defparam \ula_|zx_keyboard_|keys[6][1]~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~43 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][1]~43_combout = (\ula_|zx_keyboard_|keys[6][1]~41_combout & (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|zx_keyboard_|keys[6][1]~42_combout )) - - .dataa(\ula_|zx_keyboard_|keys[6][1]~41_combout ), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|zx_keyboard_|keys[6][1]~42_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][1]~43_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1]~43 .lut_mask = 16'hA000; -defparam \ula_|zx_keyboard_|keys[6][1]~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~40 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][1]~40_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [2] & \ula_|zx_keyboard_|shifted~q )) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|zx_keyboard_|shifted~q ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][1]~40_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1]~40 .lut_mask = 16'hEAEA; -defparam \ula_|zx_keyboard_|keys[6][1]~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~44 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][1]~44_combout = (\ula_|zx_keyboard_|keys[6][1]~43_combout & ((!\ula_|zx_keyboard_|keys[6][1]~40_combout ))) # (!\ula_|zx_keyboard_|keys[6][1]~43_combout & (\ula_|zx_keyboard_|keys[6][1]~q )) - - .dataa(\ula_|zx_keyboard_|keys[6][1]~43_combout ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[6][1]~q ), - .datad(\ula_|zx_keyboard_|keys[6][1]~40_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][1]~44_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1]~44 .lut_mask = 16'h50FA; -defparam \ula_|zx_keyboard_|keys[6][1]~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y20_N25 -dffeas \ula_|zx_keyboard_|keys[6][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[6][1]~44_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[6][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[6][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y21_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~45 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][1]~45_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (!\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [7]))) - - .dataa(\ula_|ps2_keyboard_|scan_code_ready~q ), - .datab(\ula_|zx_keyboard_|extended~q ), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|ps2_keyboard_|shiftreg [7]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][1]~45_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][1]~45 .lut_mask = 16'h0002; -defparam \ula_|zx_keyboard_|keys[7][1]~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~5 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~5_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (((!\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [1])))) # (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & -// ((\ula_|ps2_keyboard_|shiftreg [2]) # (\ula_|ps2_keyboard_|shiftreg [1])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~5_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~5 .lut_mask = 16'h0A38; -defparam \ula_|zx_keyboard_|WideOr16~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~2 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~2_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~2 .lut_mask = 16'h0044; -defparam \ula_|zx_keyboard_|WideOr16~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~4 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~4_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1])) # (!\ula_|ps2_keyboard_|shiftreg [2] & -// (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [1])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~4_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~4 .lut_mask = 16'h0140; -defparam \ula_|zx_keyboard_|WideOr16~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~7 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~7_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (((\ula_|zx_keyboard_|WideOr16~4_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|WideOr16~2_combout & (!\ula_|ps2_keyboard_|shiftreg [2]))) - - .dataa(\ula_|zx_keyboard_|WideOr16~2_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|zx_keyboard_|WideOr16~4_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~7_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~7 .lut_mask = 16'hF022; -defparam \ula_|zx_keyboard_|WideOr16~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~6 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~6_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (((\ula_|zx_keyboard_|WideOr16~7_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|WideOr16~5_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|zx_keyboard_|WideOr16~5_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|WideOr16~7_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~6_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~6 .lut_mask = 16'hF808; -defparam \ula_|zx_keyboard_|WideOr16~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y21_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~46 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][1]~46_combout = (\ula_|zx_keyboard_|keys[7][1]~45_combout & ((\ula_|zx_keyboard_|WideOr16~6_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|WideOr16~6_combout & ((\ula_|zx_keyboard_|keys[7][1]~q ))))) # -// (!\ula_|zx_keyboard_|keys[7][1]~45_combout & (((\ula_|zx_keyboard_|keys[7][1]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[7][1]~45_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[7][1]~q ), - .datad(\ula_|zx_keyboard_|WideOr16~6_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][1]~46_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][1]~46 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[7][1]~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y21_N31 -dffeas \ula_|zx_keyboard_|keys[7][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[7][1]~46_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[7][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[7][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N20 +// Location: LCCOMB_X31_Y10_N20 cycloneive_lcell_comb \D[1]~31 ( // Equation(s): -// \D[1]~31_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\z80_|address_pins_|abus[15]~22_combout ) # (!\ula_|zx_keyboard_|keys[7][1]~q )))) # (!\z80_|address_pins_|abus[14]~23_combout & (!\ula_|zx_keyboard_|keys[6][1]~q & -// ((\z80_|address_pins_|abus[15]~22_combout ) # (!\ula_|zx_keyboard_|keys[7][1]~q )))) +// \D[1]~31_combout = ((\Equal2~0_combout & (\D[1]~30_combout )) # (!\Equal2~0_combout & ((\D[1]~81_combout )))) # (!\Equal2~1_combout ) - .dataa(\z80_|address_pins_|abus[14]~23_combout ), - .datab(\ula_|zx_keyboard_|keys[6][1]~q ), - .datac(\z80_|address_pins_|abus[15]~22_combout ), - .datad(\ula_|zx_keyboard_|keys[7][1]~q ), + .dataa(\Equal2~1_combout ), + .datab(\Equal2~0_combout ), + .datac(\D[1]~30_combout ), + .datad(\D[1]~81_combout ), .cin(gnd), .combout(\D[1]~31_combout ), .cout()); // synopsys translate_off -defparam \D[1]~31 .lut_mask = 16'hB0BB; +defparam \D[1]~31 .lut_mask = 16'hF7D5; defparam \D[1]~31 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y20_N18 +// Location: LCCOMB_X31_Y10_N2 cycloneive_lcell_comb \D[1]~32 ( // Equation(s): -// \D[1]~32_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[1]~30_combout & (\D[1]~29_combout & \D[1]~31_combout ))) +// \D[1]~32_combout = (\z80_|pin_control_|bus_db_pin_oe~15_combout & (((\z80_|data_pins_|dout [1] & \D[1]~31_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout & (((\D[1]~31_combout )) # (!\Equal2~1_combout ))) - .dataa(\D[1]~30_combout ), - .datab(\z80_|address_pins_|abus[0]~16_combout ), - .datac(\D[1]~29_combout ), + .dataa(\Equal2~1_combout ), + .datab(\z80_|data_pins_|dout [1]), + .datac(\z80_|pin_control_|bus_db_pin_oe~15_combout ), .datad(\D[1]~31_combout ), .cin(gnd), .combout(\D[1]~32_combout ), .cout()); // synopsys translate_off -defparam \D[1]~32 .lut_mask = 16'hECCC; +defparam \D[1]~32 .lut_mask = 16'hCF05; defparam \D[1]~32 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y22_N4 -cycloneive_lcell_comb \D[1]~33 ( -// Equation(s): -// \D[1]~33_combout = ((\Equal2~0_combout & ((\D[1]~32_combout ))) # (!\Equal2~0_combout & (\D[1]~103_combout ))) # (!\Equal2~1_combout ) - - .dataa(\Equal2~0_combout ), - .datab(\Equal2~1_combout ), - .datac(\D[1]~103_combout ), - .datad(\D[1]~32_combout ), - .cin(gnd), - .combout(\D[1]~33_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~33 .lut_mask = 16'hFB73; -defparam \D[1]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y22_N8 -cycloneive_lcell_comb \D[1]~34 ( -// Equation(s): -// \D[1]~34_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\D[1]~33_combout & \z80_|data_pins_|dout [1])))) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\D[1]~33_combout )) # (!\Equal2~1_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datab(\Equal2~1_combout ), - .datac(\D[1]~33_combout ), - .datad(\z80_|data_pins_|dout [1]), - .cin(gnd), - .combout(\D[1]~34_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~34 .lut_mask = 16'hF151; -defparam \D[1]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N18 +// Location: LCCOMB_X30_Y13_N14 cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] ( // Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [1] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[1]~11_combout ) # ((\z80_|pin_control_|bus_db_pin_re~combout & \D[1]~34_combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & -// (((\z80_|pin_control_|bus_db_pin_re~combout & \D[1]~34_combout )))) +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [1] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[1]~11_combout ) # ((\D[1]~32_combout & \z80_|pin_control_|bus_db_pin_re~combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & +// (((\D[1]~32_combout & \z80_|pin_control_|bus_db_pin_re~combout )))) .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), .datab(\z80_|bus_control_|db[1]~11_combout ), - .datac(\z80_|pin_control_|bus_db_pin_re~combout ), - .datad(\D[1]~34_combout ), + .datac(\D[1]~32_combout ), + .datad(\z80_|pin_control_|bus_db_pin_re~combout ), .cin(gnd), .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [1]), .cout()); @@ -43910,7 +40644,42 @@ defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] .lut_mask = 16'hF888; defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y13_N19 +// Location: LCCOMB_X28_Y12_N16 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_re~2 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_re~2_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (((\z80_|execute_|fIORead~3_combout & \z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M1_ff~q ))) # (!\z80_|sequencer_|DFFE_T2_ff~q & +// (\z80_|execute_|fIORead~3_combout & ((\z80_|sequencer_|DFFE_T3_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|execute_|fIORead~3_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_re~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_re~2 .lut_mask = 16'hCE0A; +defparam \z80_|pin_control_|bus_db_pin_re~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N8 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_2 ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_2~combout = (\z80_|execute_|ctl_bus_db_we~7_combout ) # ((\z80_|pin_control_|bus_db_pin_re~2_combout ) # ((\z80_|execute_|fMRead~36_combout & \z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datab(\z80_|execute_|fMRead~36_combout ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|pin_control_|bus_db_pin_re~2_combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_2 .lut_mask = 16'hFFEA; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y13_N15 dffeas \z80_|data_pins_|dout[1] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [1]), @@ -43929,61 +40698,27 @@ defparam \z80_|data_pins_|dout[1] .is_wysiwyg = "true"; defparam \z80_|data_pins_|dout[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N30 -cycloneive_lcell_comb \z80_|bus_control_|db[1]~10 ( -// Equation(s): -// \z80_|bus_control_|db[1]~10_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[1]~26_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) - - .dataa(gnd), - .datab(\z80_|alu_control_|db[1]~26_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|bus_control_|db[0]~4_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[1]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[1]~10 .lut_mask = 16'hCF00; -defparam \z80_|bus_control_|db[1]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N24 +// Location: LCCOMB_X30_Y13_N28 cycloneive_lcell_comb \z80_|bus_control_|db[1]~11 ( // Equation(s): // \z80_|bus_control_|db[1]~11_combout = ((\z80_|bus_control_|db[1]~10_combout & ((\z80_|data_pins_|dout [1]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - .dataa(\z80_|execute_|ctl_bus_db_oe~combout ), - .datab(\z80_|data_pins_|dout [1]), - .datac(\z80_|bus_control_|db[1]~10_combout ), - .datad(\z80_|bus_control_|db[0]~6_combout ), + .dataa(\z80_|bus_control_|db[0]~6_combout ), + .datab(\z80_|bus_control_|db[1]~10_combout ), + .datac(\z80_|data_pins_|dout [1]), + .datad(\z80_|execute_|ctl_bus_db_oe~combout ), .cin(gnd), .combout(\z80_|bus_control_|db[1]~11_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[1]~11 .lut_mask = 16'hD0FF; +defparam \z80_|bus_control_|db[1]~11 .lut_mask = 16'hD5DD; defparam \z80_|bus_control_|db[1]~11 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N14 -cycloneive_lcell_comb \z80_|ir_|opcode[1]~feeder ( -// Equation(s): -// \z80_|ir_|opcode[1]~feeder_combout = \z80_|bus_control_|db[1]~11_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|bus_control_|db[1]~11_combout ), - .cin(gnd), - .combout(\z80_|ir_|opcode[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|ir_|opcode[1]~feeder .lut_mask = 16'hFF00; -defparam \z80_|ir_|opcode[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y12_N15 +// Location: FF_X30_Y13_N29 dffeas \z80_|ir_|opcode[1] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|ir_|opcode[1]~feeder_combout ), + .d(\z80_|bus_control_|db[1]~11_combout ), .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), @@ -43999,8110 +40734,848 @@ defparam \z80_|ir_|opcode[1] .is_wysiwyg = "true"; defparam \z80_|ir_|opcode[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y13_N18 -cycloneive_lcell_comb \z80_|pla_decode_|Equal40~0 ( +// Location: LCCOMB_X27_Y13_N0 +cycloneive_lcell_comb \z80_|pla_decode_|Equal2~0 ( // Equation(s): -// \z80_|pla_decode_|Equal40~0_combout = (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [1])) +// \z80_|pla_decode_|Equal2~0_combout = (!\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1]) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|ir_|opcode [1]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal2~0 .lut_mask = 16'h3030; +defparam \z80_|pla_decode_|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~15 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~15_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal13~0_combout & \z80_|ir_|opcode [3]))) .dataa(\z80_|ir_|opcode [0]), - .datab(gnd), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal40~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal40~0 .lut_mask = 16'h0005; -defparam \z80_|pla_decode_|Equal40~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N24 -cycloneive_lcell_comb \z80_|pla_decode_|Equal21~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal21~1_combout = (\z80_|pla_decode_|Equal21~0_combout & (\z80_|pla_decode_|Equal40~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal21~0_combout ), - .datab(\z80_|pla_decode_|Equal40~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal21~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal21~1 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal21~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~26 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~26_combout = (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|pla_decode_|Equal21~1_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T4_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~26 .lut_mask = 16'hC080; -defparam \z80_|execute_|ctl_alu_op_low~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~28 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~28_combout = (\z80_|execute_|ctl_alu_op_low~26_combout ) # ((\z80_|execute_|ctl_alu_op_low~23_combout ) # ((\z80_|execute_|ctl_alu_op_low~34_combout ) # (\z80_|execute_|ctl_alu_op_low~27_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~26_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~23_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~34_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~28 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_alu_op_low~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~3_combout = (\z80_|execute_|ctl_alu_op_low~28_combout & (\z80_|pla_decode_|Equal64~0_combout & ((\z80_|pla_decode_|Equal9~0_combout ) # (\z80_|pla_decode_|Equal3~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~28_combout ), - .datab(\z80_|pla_decode_|Equal9~0_combout ), - .datac(\z80_|pla_decode_|Equal64~0_combout ), - .datad(\z80_|pla_decode_|Equal3~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~3 .lut_mask = 16'hA080; -defparam \z80_|execute_|ctl_flags_cf_cpl~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~2_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ) # ((\z80_|execute_|ctl_mRead~36_combout & ((\z80_|execute_|ixy_d~6_combout ) # (\z80_|execute_|ctl_mRead~11_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~36_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|execute_|ctl_mRead~11_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~2 .lut_mask = 16'hFFA8; -defparam \z80_|execute_|ctl_flags_cf_cpl~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N20 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout = (!\z80_|execute_|ctl_mWrite~10_combout & (((!\z80_|pla_decode_|Equal61~2_combout & !\z80_|execute_|ctl_mWrite~16_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal61~2_combout ), - .datab(\z80_|execute_|ctl_mWrite~16_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_mWrite~10_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 .lut_mask = 16'h001F; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N2 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout = (\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_state_alu~5_combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|execute_|ctl_mRead~36_combout )))) # (!\z80_|pla_decode_|Equal56~0_combout & -// (((!\z80_|nM1_int~2_combout )) # (!\z80_|execute_|ctl_mRead~36_combout ))) - - .dataa(\z80_|pla_decode_|Equal56~0_combout ), - .datab(\z80_|execute_|ctl_mRead~36_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_state_alu~5_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 .lut_mask = 16'h153F; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N28 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout = (\z80_|execute_|ctl_alu_core_R~4_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_R~4_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 .lut_mask = 16'h8000; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N16 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~6_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~5_combout & !\z80_|execute_|ctl_alu_sel_op2_neg~16_combout )) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 .lut_mask = 16'h0088; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N22 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout = (!\z80_|execute_|ctl_alu_core_R~1_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout & (\z80_|execute_|ctl_alu_core_S~7_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_R~1_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ), - .datac(\z80_|execute_|ctl_alu_core_S~7_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 .lut_mask = 16'h4000; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N18 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout & (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout & ((!\z80_|execute_|ctl_alu_op_low~27_combout ) # (!\z80_|execute_|ctl_flags_cf_cpl~2_combout )))) - - .dataa(\z80_|execute_|ctl_flags_cf_cpl~2_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), - .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 .lut_mask = 16'h040C; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N30 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~21 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~21_combout = (((!\z80_|pla_decode_|Equal40~1_combout & !\z80_|pla_decode_|Equal39~0_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|pla_decode_|Equal40~1_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~21 .lut_mask = 16'h777F; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N26 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout = (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~21_combout & ((\z80_|execute_|ctl_alu_op_low~23_combout ) # (\z80_|execute_|ctl_alu_op_low~27_combout ))) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op_low~23_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~21_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 .lut_mask = 16'h0F0C; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N4 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout = (\z80_|pla_decode_|Equal21~1_combout & ((\z80_|execute_|ixy_d~6_combout ) # ((\z80_|sequencer_|DFFE_T5_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 .lut_mask = 16'hC0E0; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N28 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout & ((\z80_|execute_|ctl_alu_op_low~23_combout ) # ((\z80_|execute_|ctl_alu_op_low~34_combout ) # (\z80_|execute_|ctl_alu_op_low~27_combout )))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~23_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~34_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 .lut_mask = 16'hAAA8; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N0 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout = (\z80_|execute_|ctl_flags_nf_we~1_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout & (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout & !\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ))) - - .dataa(\z80_|execute_|ctl_flags_nf_we~1_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 .lut_mask = 16'h0008; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N22 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~22_combout & (\z80_|execute_|ctl_flags_sz_we~4_combout & ((!\z80_|pla_decode_|Equal9~0_combout ) # (!\z80_|pla_decode_|Equal62~2_combout )))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~22_combout ), - .datab(\z80_|pla_decode_|Equal62~2_combout ), - .datac(\z80_|execute_|ctl_flags_sz_we~4_combout ), - .datad(\z80_|pla_decode_|Equal9~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17 .lut_mask = 16'h20A0; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~32 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~32_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|pla_decode_|Equal10~0_combout )) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal10~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~32 .lut_mask = 16'h8800; -defparam \z80_|execute_|ctl_alu_op_low~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N18 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|pla_decode_|Equal21~0_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal63~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal21~0_combout ), - .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|pla_decode_|Equal63~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 .lut_mask = 16'hCECC; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N20 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout = (\z80_|execute_|ctl_alu_op_low~32_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~32_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 .lut_mask = 16'hFFEF; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N24 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout = ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ) # ((\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & \z80_|execute_|ctl_alu_op_low~20_combout ))) # (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ) - - .dataa(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~20_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18 .lut_mask = 16'hFFB3; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N0 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~19 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~19_combout = (\z80_|execute_|ctl_state_alu~12_combout & ((\z80_|ir_|opcode [3] & (\z80_|ir_|opcode [4] & \z80_|ir_|opcode [5])) # (!\z80_|ir_|opcode [3] & ((!\z80_|ir_|opcode [5]))))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|execute_|ctl_state_alu~12_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~19 .lut_mask = 16'h8500; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N10 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~0 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[0]~19_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[7]~21_combout )) - - .dataa(\z80_|alu_|db[7]~21_combout ), - .datab(gnd), - .datac(\z80_|alu_|db[0]~19_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~0 .lut_mask = 16'hF0AA; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N28 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~1 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_control_|out[6]~2_combout )) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .datab(gnd), - .datac(\z80_|alu_control_|out[6]~2_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~1 .lut_mask = 16'hFA50; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N18 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~2 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout & ((!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout )))) # (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout -// & ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (!\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ))))) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~2 .lut_mask = 16'h11D8; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N30 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~3 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout = (\z80_|execute_|ctl_flags_cf2_we~3_combout & (\z80_|execute_|ctl_flags_cf2_sel_daa~combout $ ((!\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout )))) # (!\z80_|execute_|ctl_flags_cf2_we~3_combout & -// ((\z80_|alu_flags_|DFFE_inst_latch_cf2~q ) # ((\z80_|execute_|ctl_flags_cf2_sel_daa~combout & \z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout )))) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), - .datad(\z80_|execute_|ctl_flags_cf2_we~3_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~3 .lut_mask = 16'h99F8; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y9_N31 -dffeas \z80_|alu_flags_|DFFE_inst_latch_cf2 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2 .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~10_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal11~0_combout & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_M1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|pla_decode_|Equal11~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~10 .lut_mask = 16'h0B00; -defparam \z80_|execute_|ctl_flags_use_cf2~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~11_combout = (\z80_|execute_|ctl_flags_use_cf2~10_combout ) # ((\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # ((\z80_|pla_decode_|Equal10~0_combout & \z80_|execute_|ixy_d~7_combout ))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|execute_|ctl_flags_use_cf2~10_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~11 .lut_mask = 16'hFFEC; -defparam \z80_|execute_|ctl_flags_use_cf2~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~8_combout = (\z80_|execute_|ctl_ir_we~8_combout ) # ((\z80_|pla_decode_|Equal20~0_combout ) # (\z80_|execute_|ctl_ir_we~14_combout )) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal20~0_combout ), - .datad(\z80_|execute_|ctl_ir_we~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~8 .lut_mask = 16'hFFFA; -defparam \z80_|execute_|ctl_flags_use_cf2~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~9_combout = (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_flags_use_cf2~8_combout ) # ((\z80_|pla_decode_|Equal9~0_combout & \z80_|pla_decode_|Equal63~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal9~0_combout ), - .datab(\z80_|pla_decode_|Equal63~0_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|execute_|ctl_flags_use_cf2~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~9 .lut_mask = 16'h0F08; -defparam \z80_|execute_|ctl_flags_use_cf2~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~12 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~12_combout = (\z80_|execute_|ctl_flags_use_cf2~11_combout ) # (((\z80_|execute_|ctl_flags_use_cf2~9_combout ) # (\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout )) # (!\z80_|execute_|ctl_flags_use_cf2~13_combout )) - - .dataa(\z80_|execute_|ctl_flags_use_cf2~11_combout ), - .datab(\z80_|execute_|ctl_flags_use_cf2~13_combout ), - .datac(\z80_|execute_|ctl_flags_use_cf2~9_combout ), - .datad(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~12 .lut_mask = 16'hFFFB; -defparam \z80_|execute_|ctl_flags_use_cf2~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N16 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout = (\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & (((\z80_|alu_flags_|DFFE_inst_latch_cf2~q )))) # (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & ((\z80_|execute_|ctl_flags_use_cf2~12_combout & -// ((\z80_|alu_flags_|DFFE_inst_latch_cf2~q ))) # (!\z80_|execute_|ctl_flags_use_cf2~12_combout & (\z80_|alu_flags_|DFFE_inst_latch_cf~q )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), - .datad(\z80_|execute_|ctl_flags_use_cf2~12_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 .lut_mask = 16'hF0E4; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N22 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~20 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~20_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~19_combout & \z80_|execute_|ctl_alu_op_low~28_combout ))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~19_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~28_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~20 .lut_mask = 16'hFEFA; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~10_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ) # ((!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|execute_|ctl_alu_op_low~12_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|execute_|ctl_alu_op_low~12_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~10 .lut_mask = 16'hFF40; -defparam \z80_|execute_|ctl_flags_cf_cpl~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~8_combout = (\z80_|execute_|ctl_flags_cf_cpl~10_combout ) # ((\z80_|execute_|ctl_alu_op_low~12_combout & (\z80_|execute_|ctl_alu_op_low~8_combout & \z80_|execute_|ctl_alu_op_low~19_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), - .datab(\z80_|execute_|ctl_flags_cf_cpl~10_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~8 .lut_mask = 16'hECCC; -defparam \z80_|execute_|ctl_flags_cf_cpl~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~5_combout = ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_alu_op_low~12_combout ) # (\z80_|execute_|ctl_state_alu~7_combout )))) # (!\z80_|execute_|ctl_state_alu~15_combout ) - - .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), - .datab(\z80_|execute_|ctl_state_alu~15_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|execute_|ctl_state_alu~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~5 .lut_mask = 16'h3F3B; -defparam \z80_|execute_|ctl_flags_cf_cpl~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~6_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_flags_cf_cpl~5_combout ) # ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal68~2_combout )))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|pla_decode_|Equal68~2_combout ), - .datad(\z80_|execute_|ctl_flags_cf_cpl~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~6 .lut_mask = 16'hAA20; -defparam \z80_|execute_|ctl_flags_cf_cpl~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~7_combout = (\z80_|execute_|ctl_flags_cf_cpl~6_combout ) # ((!\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # (\z80_|execute_|ctl_flags_cf2_sel_daa~combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datad(\z80_|execute_|ctl_flags_cf_cpl~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~7 .lut_mask = 16'hFF32; -defparam \z80_|execute_|ctl_flags_cf_cpl~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_set~0 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_set~0_combout = (\z80_|execute_|ctl_state_alu~12_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal9~0_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~12_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal9~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_set~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_set~0 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_flags_cf_set~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~4_combout = (\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout & ((\z80_|execute_|ctl_alu_op_low~19_combout ) # (!\z80_|execute_|ctl_alu_op_low~33_combout ))) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), - .datac(\z80_|execute_|ctl_alu_op_low~19_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~33_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~4 .lut_mask = 16'hC0CC; -defparam \z80_|execute_|ctl_flags_cf_cpl~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~9_combout = (\z80_|execute_|ctl_flags_cf_cpl~8_combout ) # ((\z80_|execute_|ctl_flags_cf_cpl~7_combout ) # ((\z80_|execute_|ctl_flags_cf_set~0_combout ) # (\z80_|execute_|ctl_flags_cf_cpl~4_combout ))) - - .dataa(\z80_|execute_|ctl_flags_cf_cpl~8_combout ), - .datab(\z80_|execute_|ctl_flags_cf_cpl~7_combout ), - .datac(\z80_|execute_|ctl_flags_cf_set~0_combout ), - .datad(\z80_|execute_|ctl_flags_cf_cpl~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~9 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_flags_cf_cpl~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N4 -cycloneive_lcell_comb \z80_|alu_flags_|flags_cf ( -// Equation(s): -// \z80_|alu_flags_|flags_cf~combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~20_combout $ (((\z80_|execute_|ctl_flags_cf_cpl~3_combout ) # (\z80_|execute_|ctl_flags_cf_cpl~9_combout ))))) - - .dataa(\z80_|execute_|ctl_flags_cf_cpl~3_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~20_combout ), - .datad(\z80_|execute_|ctl_flags_cf_cpl~9_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|flags_cf~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_cf .lut_mask = 16'h0C48; -defparam \z80_|alu_flags_|flags_cf .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N2 -cycloneive_lcell_comb \z80_|alu_control_|db[0]~8 ( -// Equation(s): -// \z80_|alu_control_|db[0]~8_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & (((\z80_|bus_control_|db[0]~17_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) - - .dataa(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .datab(\z80_|execute_|ctl_sw_1d~7_combout ), - .datac(\z80_|bus_control_|db[0]~17_combout ), - .datad(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[0]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[0]~8 .lut_mask = 16'h22A2; -defparam \z80_|alu_control_|db[0]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N20 -cycloneive_lcell_comb \z80_|sw2_|db_up[0]~0 ( -// Equation(s): -// \z80_|sw2_|db_up[0]~0_combout = (\z80_|alu_|db[0]~19_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_sw_2u~7_combout ), - .datad(\z80_|alu_|db[0]~19_combout ), - .cin(gnd), - .combout(\z80_|sw2_|db_up[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sw2_|db_up[0]~0 .lut_mask = 16'hFF0F; -defparam \z80_|sw2_|db_up[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N4 -cycloneive_lcell_comb \z80_|alu_control_|db[0]~9 ( -// Equation(s): -// \z80_|alu_control_|db[0]~9_combout = (\z80_|alu_control_|db[0]~8_combout & (\z80_|sw2_|db_up[0]~0_combout & ((\z80_|reg_file_|gdfx_temp0[0]~22_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) - - .dataa(\z80_|alu_control_|db[0]~8_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .datac(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datad(\z80_|sw2_|db_up[0]~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[0]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[0]~9 .lut_mask = 16'h8A00; -defparam \z80_|alu_control_|db[0]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N26 -cycloneive_lcell_comb \z80_|alu_control_|db[0]~12 ( -// Equation(s): -// \z80_|alu_control_|db[0]~12_combout = ((\z80_|alu_control_|db[0]~9_combout & ((\z80_|alu_flags_|flags_cf~combout ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|alu_flags_|flags_cf~combout ), - .datab(\z80_|execute_|ctl_flags_oe~2_combout ), - .datac(\z80_|alu_control_|db[0]~9_combout ), - .datad(\z80_|alu_control_|db[6]~11_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[0]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[0]~12 .lut_mask = 16'hB0FF; -defparam \z80_|alu_control_|db[0]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~67 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][0]~67_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [4])) - - .dataa(\ula_|zx_keyboard_|shifted~q ), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][0]~67_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][0]~67 .lut_mask = 16'hFF50; -defparam \ula_|zx_keyboard_|keys[5][0]~67 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~81 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][0]~81_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [3]))) # (!\ula_|ps2_keyboard_|shiftreg [1] & -// (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][0]~81_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][0]~81 .lut_mask = 16'h0420; -defparam \ula_|zx_keyboard_|keys[5][0]~81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~82 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][0]~82_combout = (\ula_|zx_keyboard_|keys[5][0]~81_combout & (\ula_|zx_keyboard_|keys[6][1]~41_combout & (\ula_|ps2_keyboard_|shiftreg [2] $ (\ula_|ps2_keyboard_|shiftreg [4])))) - - .dataa(\ula_|zx_keyboard_|keys[5][0]~81_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|keys[6][1]~41_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][0]~82_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][0]~82 .lut_mask = 16'h2800; -defparam \ula_|zx_keyboard_|keys[5][0]~82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~83 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][0]~83_combout = (\ula_|zx_keyboard_|keys[5][0]~82_combout & (!\ula_|zx_keyboard_|keys[5][0]~67_combout )) # (!\ula_|zx_keyboard_|keys[5][0]~82_combout & ((\ula_|zx_keyboard_|keys[5][0]~q ))) - - .dataa(\ula_|zx_keyboard_|keys[5][0]~67_combout ), - .datab(\ula_|zx_keyboard_|keys[5][0]~82_combout ), - .datac(\ula_|zx_keyboard_|keys[5][0]~q ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][0]~83_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][0]~83 .lut_mask = 16'h7474; -defparam \ula_|zx_keyboard_|keys[5][0]~83 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y20_N11 -dffeas \ula_|zx_keyboard_|keys[5][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[5][0]~83_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[5][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[5][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~84 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][0]~84_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [5] $ (\ula_|ps2_keyboard_|shiftreg [3])))) # (!\ula_|ps2_keyboard_|shiftreg [1] & -// (!\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [0]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [5]), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][0]~84_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][0]~84 .lut_mask = 16'h0160; -defparam \ula_|zx_keyboard_|keys[4][0]~84 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~85 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][0]~85_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [3])) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|shifted~q ), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][0]~85_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][0]~85 .lut_mask = 16'hBABA; -defparam \ula_|zx_keyboard_|keys[4][0]~85 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~86 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][0]~86_combout = (\ula_|zx_keyboard_|keys[5][1]~37_combout & ((\ula_|zx_keyboard_|keys[4][0]~84_combout & ((!\ula_|zx_keyboard_|keys[4][0]~85_combout ))) # (!\ula_|zx_keyboard_|keys[4][0]~84_combout & -// (\ula_|zx_keyboard_|keys[4][0]~q )))) # (!\ula_|zx_keyboard_|keys[5][1]~37_combout & (((\ula_|zx_keyboard_|keys[4][0]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[5][1]~37_combout ), - .datab(\ula_|zx_keyboard_|keys[4][0]~84_combout ), - .datac(\ula_|zx_keyboard_|keys[4][0]~q ), - .datad(\ula_|zx_keyboard_|keys[4][0]~85_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][0]~86_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][0]~86 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[4][0]~86 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y18_N27 -dffeas \ula_|zx_keyboard_|keys[4][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[4][0]~86_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[4][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[4][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N20 -cycloneive_lcell_comb \D[0]~49 ( -// Equation(s): -// \D[0]~49_combout = (\z80_|address_pins_|abus[13]~20_combout & (((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][0]~q )))) # (!\z80_|address_pins_|abus[13]~20_combout & (!\ula_|zx_keyboard_|keys[5][0]~q & -// ((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][0]~q )))) - - .dataa(\z80_|address_pins_|abus[13]~20_combout ), - .datab(\ula_|zx_keyboard_|keys[5][0]~q ), - .datac(\ula_|zx_keyboard_|keys[4][0]~q ), - .datad(\z80_|address_pins_|abus[12]~21_combout ), - .cin(gnd), - .combout(\D[0]~49_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~49 .lut_mask = 16'hBB0B; -defparam \D[0]~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr4~0 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr4~0_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [5] & ((\ula_|ps2_keyboard_|shiftreg [6])))) # (!\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [5] & -// (\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [6]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr4~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr4~0 .lut_mask = 16'h8810; -defparam \ula_|zx_keyboard_|WideOr4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys~76 ( -// Equation(s): -// \ula_|zx_keyboard_|keys~76_combout = (!\ula_|zx_keyboard_|extended~q & (((\ula_|ps2_keyboard_|shiftreg [3]) # (!\ula_|zx_keyboard_|keys[4][1]~31_combout )) # (!\ula_|zx_keyboard_|WideOr4~0_combout ))) - - .dataa(\ula_|zx_keyboard_|WideOr4~0_combout ), - .datab(\ula_|zx_keyboard_|extended~q ), - .datac(\ula_|zx_keyboard_|keys[4][1]~31_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys~76_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys~76 .lut_mask = 16'h3313; -defparam \ula_|zx_keyboard_|keys~76 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~73 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~73_combout = (\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [6]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][3]~73_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~73 .lut_mask = 16'hF000; -defparam \ula_|zx_keyboard_|keys[4][3]~73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~47 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][4]~47_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [2])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][4]~47_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][4]~47 .lut_mask = 16'h0808; -defparam \ula_|zx_keyboard_|keys[6][4]~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr0~0 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr0~0_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [2])) # (!\ula_|ps2_keyboard_|shiftreg [1] & -// ((\ula_|ps2_keyboard_|shiftreg [2]))))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [0]), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr0~0 .lut_mask = 16'h0310; -defparam \ula_|zx_keyboard_|WideOr0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys~74 ( -// Equation(s): -// \ula_|zx_keyboard_|keys~74_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (((!\ula_|zx_keyboard_|WideOr0~0_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [4] & (((!\ula_|ps2_keyboard_|shiftreg [3])) # (!\ula_|zx_keyboard_|keys[6][4]~47_combout ))) - - .dataa(\ula_|zx_keyboard_|keys[6][4]~47_combout ), - .datab(\ula_|zx_keyboard_|WideOr0~0_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys~74_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys~74 .lut_mask = 16'h353F; -defparam \ula_|zx_keyboard_|keys~74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~75 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][0]~75_combout = (\ula_|zx_keyboard_|keys[0][0]~15_combout & (((\ula_|zx_keyboard_|keys[4][3]~73_combout & !\ula_|zx_keyboard_|keys~74_combout )) # (!\ula_|zx_keyboard_|extended~q ))) - - .dataa(\ula_|zx_keyboard_|keys[4][3]~73_combout ), - .datab(\ula_|zx_keyboard_|keys~74_combout ), - .datac(\ula_|zx_keyboard_|extended~q ), - .datad(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][0]~75_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][0]~75 .lut_mask = 16'h2F00; -defparam \ula_|zx_keyboard_|keys[0][0]~75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~77 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][0]~77_combout = (\ula_|zx_keyboard_|keys~76_combout & (((\ula_|zx_keyboard_|keys[0][0]~q )))) # (!\ula_|zx_keyboard_|keys~76_combout & ((\ula_|zx_keyboard_|keys[0][0]~75_combout & ((!\ula_|zx_keyboard_|released~q ))) # -// (!\ula_|zx_keyboard_|keys[0][0]~75_combout & (\ula_|zx_keyboard_|keys[0][0]~q )))) - - .dataa(\ula_|zx_keyboard_|keys~76_combout ), - .datab(\ula_|zx_keyboard_|keys[0][0]~75_combout ), - .datac(\ula_|zx_keyboard_|keys[0][0]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][0]~77_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][0]~77 .lut_mask = 16'hB0F4; -defparam \ula_|zx_keyboard_|keys[0][0]~77 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y20_N15 -dffeas \ula_|zx_keyboard_|keys[0][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[0][0]~77_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[0][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[0][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][0]~71 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][0]~71_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[1][4]~25_combout & !\ula_|ps2_keyboard_|shiftreg [5]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [0]), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|zx_keyboard_|keys[1][4]~25_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][0]~71_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][0]~71 .lut_mask = 16'h0040; -defparam \ula_|zx_keyboard_|keys[1][0]~71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][0]~72 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][0]~72_combout = (\ula_|zx_keyboard_|keys[1][0]~71_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[1][0]~71_combout & (\ula_|zx_keyboard_|keys[1][0]~q )) - - .dataa(gnd), - .datab(\ula_|zx_keyboard_|keys[1][0]~71_combout ), - .datac(\ula_|zx_keyboard_|keys[1][0]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][0]~72_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][0]~72 .lut_mask = 16'h30FC; -defparam \ula_|zx_keyboard_|keys[1][0]~72 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y19_N17 -dffeas \ula_|zx_keyboard_|keys[1][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[1][0]~72_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[1][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[1][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N30 -cycloneive_lcell_comb \D[0]~47 ( -// Equation(s): -// \D[0]~47_combout = (\ula_|zx_keyboard_|keys[0][0]~q & (\z80_|address_pins_|abus[8]~18_combout & ((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][0]~q )))) # (!\ula_|zx_keyboard_|keys[0][0]~q & -// (((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][0]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[0][0]~q ), - .datab(\z80_|address_pins_|abus[8]~18_combout ), - .datac(\z80_|address_pins_|abus[9]~17_combout ), - .datad(\ula_|zx_keyboard_|keys[1][0]~q ), - .cin(gnd), - .combout(\D[0]~47_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~47 .lut_mask = 16'hD0DD; -defparam \D[0]~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][0]~80 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][0]~80_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (((\ula_|zx_keyboard_|keys[2][0]~q )))) # (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[2][1]~26_combout & (!\ula_|zx_keyboard_|released~q )) # -// (!\ula_|zx_keyboard_|keys[2][1]~26_combout & ((\ula_|zx_keyboard_|keys[2][0]~q ))))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[2][0]~q ), - .datad(\ula_|zx_keyboard_|keys[2][1]~26_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][0]~80_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][0]~80 .lut_mask = 16'hB1F0; -defparam \ula_|zx_keyboard_|keys[2][0]~80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y20_N23 -dffeas \ula_|zx_keyboard_|keys[2][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[2][0]~80_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[2][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[2][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][0]~78 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][0]~78_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [0])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][0]~78_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][0]~78 .lut_mask = 16'h000A; -defparam \ula_|zx_keyboard_|keys[3][0]~78 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][0]~79 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][0]~79_combout = (\ula_|zx_keyboard_|keys[3][0]~78_combout & ((\ula_|zx_keyboard_|keys[3][1]~28_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[3][1]~28_combout & (\ula_|zx_keyboard_|keys[3][0]~q -// )))) # (!\ula_|zx_keyboard_|keys[3][0]~78_combout & (((\ula_|zx_keyboard_|keys[3][0]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[3][0]~78_combout ), - .datab(\ula_|zx_keyboard_|keys[3][1]~28_combout ), - .datac(\ula_|zx_keyboard_|keys[3][0]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][0]~79_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][0]~79 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[3][0]~79 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y20_N5 -dffeas \ula_|zx_keyboard_|keys[3][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[3][0]~79_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[3][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[3][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~1 ( -// Equation(s): -// \ula_|zx_keyboard_|key_row~1_combout = ((\z80_|address_pins_|DFFE_apin_latch [11]) # (!\ula_|zx_keyboard_|keys[3][0]~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\ula_|zx_keyboard_|keys[3][0]~q ), - .datad(\z80_|address_pins_|DFFE_apin_latch [11]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|key_row~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|key_row~1 .lut_mask = 16'hFF3F; -defparam \ula_|zx_keyboard_|key_row~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N4 -cycloneive_lcell_comb \D[0]~48 ( -// Equation(s): -// \D[0]~48_combout = (\D[0]~47_combout & (\ula_|zx_keyboard_|key_row~1_combout & ((\z80_|address_pins_|abus[10]~24_combout ) # (!\ula_|zx_keyboard_|keys[2][0]~q )))) - - .dataa(\D[0]~47_combout ), - .datab(\z80_|address_pins_|abus[10]~24_combout ), - .datac(\ula_|zx_keyboard_|keys[2][0]~q ), - .datad(\ula_|zx_keyboard_|key_row~1_combout ), - .cin(gnd), - .combout(\D[0]~48_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~48 .lut_mask = 16'h8A00; -defparam \D[0]~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~1 ( -// Equation(s): -// \ula_|zx_keyboard_|shifted~1_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [4]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|shifted~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|shifted~1 .lut_mask = 16'h0F00; -defparam \ula_|zx_keyboard_|shifted~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~90 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][0]~90_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][0]~90_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][0]~90 .lut_mask = 16'h0200; -defparam \ula_|zx_keyboard_|keys[6][0]~90 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~91 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][0]~91_combout = (\ula_|zx_keyboard_|shifted~1_combout & (\ula_|zx_keyboard_|keys[7][1]~23_combout & (\ula_|zx_keyboard_|keys[6][0]~90_combout & \ula_|ps2_keyboard_|shiftreg [1]))) - - .dataa(\ula_|zx_keyboard_|shifted~1_combout ), - .datab(\ula_|zx_keyboard_|keys[7][1]~23_combout ), - .datac(\ula_|zx_keyboard_|keys[6][0]~90_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][0]~91_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][0]~91 .lut_mask = 16'h8000; -defparam \ula_|zx_keyboard_|keys[6][0]~91 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~92 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][0]~92_combout = (\ula_|zx_keyboard_|keys[6][0]~91_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[6][0]~91_combout & ((\ula_|zx_keyboard_|keys[6][0]~q ))) - - .dataa(gnd), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[6][0]~q ), - .datad(\ula_|zx_keyboard_|keys[6][0]~91_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][0]~92_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][0]~92 .lut_mask = 16'h33F0; -defparam \ula_|zx_keyboard_|keys[6][0]~92 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y20_N21 -dffeas \ula_|zx_keyboard_|keys[6][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[6][0]~92_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[6][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[6][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y21_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~63 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][4]~63_combout = (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [0]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][4]~63_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][4]~63 .lut_mask = 16'h0F00; -defparam \ula_|zx_keyboard_|keys[5][4]~63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y21_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~3 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~3_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [2]) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~3 .lut_mask = 16'h0303; -defparam \ula_|zx_keyboard_|WideOr16~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y21_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~87 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][0]~87_combout = (\ula_|zx_keyboard_|keys[5][4]~63_combout & (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|WideOr16~3_combout ))) - - .dataa(\ula_|zx_keyboard_|keys[5][4]~63_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|WideOr16~3_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][0]~87_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][0]~87 .lut_mask = 16'h0800; -defparam \ula_|zx_keyboard_|keys[7][0]~87 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~132 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][0]~132_combout = (\ula_|zx_keyboard_|keys[3][0]~78_combout & (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [4]))) - - .dataa(\ula_|zx_keyboard_|keys[3][0]~78_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][0]~132_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][0]~132 .lut_mask = 16'h8000; -defparam \ula_|zx_keyboard_|keys[7][0]~132 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y21_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~88 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][0]~88_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|zx_keyboard_|keys[7][1]~23_combout & ((\ula_|zx_keyboard_|keys[7][0]~87_combout ) # (\ula_|zx_keyboard_|keys[7][0]~132_combout )))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [5]), - .datab(\ula_|zx_keyboard_|keys[7][1]~23_combout ), - .datac(\ula_|zx_keyboard_|keys[7][0]~87_combout ), - .datad(\ula_|zx_keyboard_|keys[7][0]~132_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][0]~88_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][0]~88 .lut_mask = 16'h8880; -defparam \ula_|zx_keyboard_|keys[7][0]~88 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~89 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][0]~89_combout = (\ula_|zx_keyboard_|keys[7][0]~88_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[7][0]~88_combout & (\ula_|zx_keyboard_|keys[7][0]~q )) - - .dataa(\ula_|zx_keyboard_|keys[7][0]~88_combout ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[7][0]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][0]~89_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][0]~89 .lut_mask = 16'h50FA; -defparam \ula_|zx_keyboard_|keys[7][0]~89 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y20_N7 -dffeas \ula_|zx_keyboard_|keys[7][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[7][0]~89_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[7][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[7][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N28 -cycloneive_lcell_comb \D[0]~50 ( -// Equation(s): -// \D[0]~50_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\z80_|address_pins_|abus[15]~22_combout ) # (!\ula_|zx_keyboard_|keys[7][0]~q )))) # (!\z80_|address_pins_|abus[14]~23_combout & (!\ula_|zx_keyboard_|keys[6][0]~q & -// ((\z80_|address_pins_|abus[15]~22_combout ) # (!\ula_|zx_keyboard_|keys[7][0]~q )))) - - .dataa(\z80_|address_pins_|abus[14]~23_combout ), - .datab(\ula_|zx_keyboard_|keys[6][0]~q ), - .datac(\z80_|address_pins_|abus[15]~22_combout ), - .datad(\ula_|zx_keyboard_|keys[7][0]~q ), - .cin(gnd), - .combout(\D[0]~50_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~50 .lut_mask = 16'hB0BB; -defparam \D[0]~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N10 -cycloneive_lcell_comb \D[0]~51 ( -// Equation(s): -// \D[0]~51_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[0]~49_combout & (\D[0]~48_combout & \D[0]~50_combout ))) - - .dataa(\D[0]~49_combout ), - .datab(\z80_|address_pins_|abus[0]~16_combout ), - .datac(\D[0]~48_combout ), - .datad(\D[0]~50_combout ), - .cin(gnd), - .combout(\D[0]~51_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~51 .lut_mask = 16'hECCC; -defparam \D[0]~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y16_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a24 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[0]~58_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_first_bit_number = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y14_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a16 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[0]~58_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_first_bit_number = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y13_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a0 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[0]~58_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N14 -cycloneive_lcell_comb \D[0]~55 ( -// Equation(s): -// \D[0]~55_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & -// ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout )) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & -// ((\ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ))))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ), - .cin(gnd), - .combout(\D[0]~55_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~55 .lut_mask = 16'hE3E0; -defparam \D[0]~55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y13_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a8 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[0]~58_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N22 -cycloneive_lcell_comb \D[0]~56 ( -// Equation(s): -// \D[0]~56_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[0]~55_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout )) # (!\D[0]~55_combout & -// ((\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ))))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[0]~55_combout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\D[0]~55_combout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ), - .cin(gnd), - .combout(\D[0]~56_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~56 .lut_mask = 16'hBCB0; -defparam \D[0]~56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y28_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a0 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[0]~58_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_bit_number = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF0000000000000000000000003FF03FFC20107FFC3FF00B9C3FF007FC18000FFC3FF03FD42FF43FFC2FFC3FE01FFE7FE81FFE3FDC07FE3FFC07FE2FFC07FE0F0807FE1F18207F0F3030FD8C30383300600000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h000000000000000000000000FFFFFFFFE0408103E004044390120EAA803920C6000000000000000000000000FFFFFFFFE0408103A004005A84723CEA813930C2000000000000000000000000800000009FBF7EFD8004027A8572358A813950EA000000000000000000000000800000009FBF7EFC8005157A85733F0A8139518E0000000000000000000000009FBF7EFC800000008006113A8C73330A813919EA0000000000000000000000009FBF7EFC8000000080060022801333A2813973EA00000000000000000000000080000000DFFFFFFD9FF6022A84730366801913FE000000000000000000000000E0408102FFFFFFFD9FF60ABA84730426901913EE; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h9FF81326887812F28FF0D7C2CC6856E3894C8B62980099E28988BFC2B9EC79829FE81362887842E68FF0C7C2CCE056E2896C89E2888098E28AA8BBC299FC1AC280081372887842E69EE0C7CA8CE046E289E089E289C899E28AA8BEC2993C1AE28008837E882852C69EE0874288E046E2886099E289689FCE8AD8BFC2999C09F680088376880846C69CA88382880042A289D08DE289F098C28AF8BFC289FC88F280088376880857C29CA893C2888043A289508DE288F0D9428BF0AFC289F4888A800883F2880857829C2891C3889047F2898885E2899081428990AF8289FC8BE3800893F6880847C2DC0894E389944F62888899668918914289803582CB8C8AF3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'hCBAC80F38DA845828DF44582840124029375A4A288D108A2FFFFFFFDE0408082CAEC80968DF855828CE4408284012006917194C280510B82DFFFFFFC8000000288EC84A28FFC4586880C648A860124128179900280510F82800000009FBF7F7C8BA080BA8FEC40828808618286012C028179901280510702800000009FBF7F7C8BB081BA8CAC408289E0618286812C1281791002805007029FBF7F7C8000000089B881828CB440828BE07782868322028139909280400F029FBF7F7D8000000089A4C3928FF444828A00260A8792227281199022A0001F03E0408081FFFFFFFF89A0C1928FD440828800260687B720C280199002E0001F03E0408083FFFFFFFF; -// synopsys translate_on - -// Location: M9K_X22_Y30_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a8 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h3C00000000000000000000000000000000000000000000000000000000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005DB824E17CAAE881C1908A79F24B7D1B4857A981A6AF39DFF5A2FEE9141EB33592D8E9B82471FDDA6791810A1C29D415CC1A8FA03444DF0083F83506BA93E8D1A1856A768D73A08418BFB25A40001DD4833DAF33BD311BB45F39667627407EF59ED569C483EB3BE1B10551B1428A6169579293ED063CAA9C6ADB0433CFC15C33AFF04C710408C20AC28B5909A229CD7D1DB4EB9A44CE0EEDBBBD391D3128AAA3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'hDDE6FC8EBE3F9F3C3DFC6E8F07BFD31D50660B1E0B2506A533CE0E340C7C745CAEC4837C2A5FECBB94C1C969FFDDFF79BFFAAFDCA8D748399ABF75558ADD02F56F6DFFF29CB70FFD25A59DFFFED7B3F7E8B4CE6FFF3EF9CEC6BAE57ABFFFCEE647B2AFF5B87AA26AFFDD317DEDCFBDFFE1A0CAD3B58877DD2F647F7DF748E7CF4693FD3C1238FFAFBD7FDF567FA8FEF024F33AFD3AABC6B105EA80272D64895FFF9FFF6E3881C81AFDCF2257FD4F8ED5257D0E9B800726B6564D2B05012F76DF636CDEB4BDFCAEEFC61DFFEFB7E26262DEF2CB9F71565824FEBF3F7BDDEABB593F1BF746FBFFC353E37263FF38A796EF39E3FD7DFEBA7FFEFFBD97ABAF09E909; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'hE629BDF93D7F5B5BAF92FBAB477E9B315DB5A310CFACC7408DF9A544B1E57AF6EFEF92C2FA4D8D4E4AC86C277338FA37BCDD9D47782DB75EFF80781BCD23D0AFCAE30B9FE6AA29FFF6F72DA73DFE4F7ACD39687B9E69C5359E9B991F0246EFFBC5595561AC64787878F5CE14C664CF9EB0CDAFFBABEF1E83358371B9ED96E5069555AFBBD3AEBFCABFBBED7A5C5FE9BD0E6A91C6E7610042695EEB08D8881B1D735AF87DAE59FABBD7DEAF8717F2B72F428F5E37E5D6E13157B99CBD2D73B9C73C563C8B02C8CC39C64DDCEA1BEEB5E7353F93786145598FE634EF1000179B345725EA43CE18F187A1DE4DAABEA97963E3A7A96B8B7CBC095BEB7CE46274D9AF; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h4ED4AE2B1650D21EAFE01E7099EFCA3094FD4D705CF6B84AE21583E13385F8650004406BD60A023AB063D4E5966EA41AA997F5A49BFCB0657A9732D28EB8217E65F627A15E1057ADEE7B9E27122A58FB2B98B1EA560390C7E87715861814E04DCB76FAB179E9619BC7E7E9C9FD801CF87DBA1EA496E829D4E62861E1AF436A7585287860729C77B6C68CAEA3033A6E84D67249B594C407B39C68B4C1C97FDEFC6BAD12FDBB525EF4F87F4A23EC13CBC0262D8899A3A290F04F41C1324045B9FCEEC890579E95D5A0A546CCCDD48577558ABE7CA36EF67A70F6A8758BDA052D5B95DE707778B17C2379847A23AE5D4BB01F36F3F44A8162566D9FB15DE7CC83F7; -// synopsys translate_on - -// Location: M9K_X22_Y27_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a8 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(gnd), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[0]~58_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_first_bit_number = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N4 -cycloneive_lcell_comb \D[0]~52 ( -// Equation(s): -// \D[0]~52_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\z80_|address_pins_|abus[14]~23_combout & ((\ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ))) # (!\z80_|address_pins_|abus[14]~23_combout & -// (\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\z80_|address_pins_|abus[14]~23_combout )))) - - .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ), - .datac(\z80_|address_pins_|abus[14]~23_combout ), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ), - .cin(gnd), - .combout(\D[0]~52_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~52 .lut_mask = 16'hF858; -defparam \D[0]~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y20_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a0 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h1EEA3633EFEA856D05BA968C1B3C30CA1788DD95D16B8F914DDDFC3EE5C69945DF7D7BF31C6072BFA7993996AB7DD2F3EE4009844CC9D6CF9E583AEC48A52F2904B57D8E0D755851232838F9B5348838530D7AF95411555D263B8CA86A5D29D7CE4B65409D6F04C5709A56C241C3BCEF07459A416EB4E8F3D73CC714F4333AFE605D53A5C955D5D1412F8361617A54446971FD187442A60FB04457857BECC3120A01FDC7FE2CBF038A61DEE5FCE2D10C8F35FBF80C05ABFF4B6935287B125E8D56F9FDFE7D64C1F4E1F5641845CD17E836B97780400C702523FA8E7C7BBD6F0666591A35ADD26B6B7E33CA56E9AB329EFA7E68F98AE7CE9507755C74C430286A; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h88537A811D4EF6CD9668CCD3E2E7A8041788DCA5F7E08AF52AF5276078304DEB75B74BB9AC3C1A492952F7EEAA0E7CF9FBEDD0FB47EEFDCC3734B816F355C913CD2E1AF14C30545297A91BED3AEAEFF8F696B5F4FC80BC6B1A2559492E9198E4A5875745B625C6CA7A7292332492D139728A689DA1AE78B6B44CE4F4A4EA5A22F331598B364EF27516CC49A4662C5E5C92ED140D96373678F833AE434698237599716B8CBAE2D3D061F2C3D6337AB435B5C2144AB6FA2F8BB51357801066B6589467DA6C480E6D19CEEA8451CEFA88FD70E7925B0302F877F87FA833FBD147E937309C08305A10187707E3D57DDE4931F1D9E97A8F378981ABBF8D7B6B7539C3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h763DD7AA7EED3F4AD4EA7491ADE6F14E6DBADD0F090A8DF34D7BAD35DD2275F0BCCF19EEF299751C919C9C13C6FB9ED711AC4DA7D947CC79E9B6323EF6CE62638CEBCB187AE5D44ECA689C9BD4E5AE544DEA7E90D186B9F335F3323877AAD54196CE81973CB555904419599375501366EC343561BCF83357F8823671393B278C1C387A7970C7F3E688673CF5975EE3E5FF105CFCCFAB725D698FB088B063063C7833830C7B2C7AFB8A8D203C312306DA0E72641FFB93D59B5EC84F44AD55F4B884735325ACC969B2EAE10A1478D866F667DDEF7BBF75E6958B6D02DC6D0F807660A229B98541E6FE734DE2280A9B57FCD5A9BEFEF7CDA5ABEB44FD73D2794D56; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'hD0734B461A36980411EB2A6C1BE76029258777EF227A8F6E84F74C4436098F67BA611013110188547995B108BB2DAE76F423A0D98845F9248BDFA45E10CA403A5E2B1A3E16869E1D37BCE906B82F401CBD467617DB34D9E0C80B5E6E10063EC4BD52921D249E377D95CFAAA309EEDAA57DA85F55DBB7048A69A4C801013948B617F7F5724D40707E6FF30002982023020449B4680C45D1CE6D8EB30A061DB8FEDD6E630C15271E48CA801988654FB501D5393392EE765C1EC95C1E4D86F18A965372B72B484E2F2664B735B69A5AB532B086BA4C62AD6D56EECBDB6984B251454845BD5B243DAED2B2489B313A35C50252AFD3E0B76FEF342335C7F1321D92FF; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N28 -cycloneive_lcell_comb \D[0]~53 ( -// Equation(s): -// \D[0]~53_combout = (\z80_|address_pins_|abus[15]~22_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout $ ((\D[0]~52_combout )))) # (!\z80_|address_pins_|abus[15]~22_combout & (((!\D[0]~52_combout & -// \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ), - .datab(\z80_|address_pins_|abus[15]~22_combout ), - .datac(\D[0]~52_combout ), - .datad(\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ), - .cin(gnd), - .combout(\D[0]~53_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~53 .lut_mask = 16'h4B48; -defparam \D[0]~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N16 -cycloneive_lcell_comb \D[0]~54 ( -// Equation(s): -// \D[0]~54_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[0]~52_combout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[0]~52_combout & -// (\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout & !\D[0]~53_combout )) # (!\D[0]~52_combout & ((\D[0]~53_combout ))))) - - .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\D[0]~52_combout ), - .datad(\D[0]~53_combout ), - .cin(gnd), - .combout(\D[0]~54_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~54 .lut_mask = 16'hC3E0; -defparam \D[0]~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N8 -cycloneive_lcell_comb \D[0]~106 ( -// Equation(s): -// \D[0]~106_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\D[0]~56_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\D[0]~54_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & -// (\D[0]~56_combout )))) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\D[0]~56_combout ), - .datad(\D[0]~54_combout ), - .cin(gnd), - .combout(\D[0]~106_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~106 .lut_mask = 16'hF4B0; -defparam \D[0]~106 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N14 -cycloneive_lcell_comb \D[0]~57 ( -// Equation(s): -// \D[0]~57_combout = ((\Equal2~0_combout & (\D[0]~51_combout )) # (!\Equal2~0_combout & ((\D[0]~106_combout )))) # (!\Equal2~1_combout ) - - .dataa(\Equal2~1_combout ), - .datab(\D[0]~51_combout ), - .datac(\D[0]~106_combout ), - .datad(\Equal2~0_combout ), - .cin(gnd), - .combout(\D[0]~57_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~57 .lut_mask = 16'hDDF5; -defparam \D[0]~57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N0 -cycloneive_lcell_comb \D[0]~58 ( -// Equation(s): -// \D[0]~58_combout = (\D[0]~57_combout & (((\z80_|data_pins_|dout [0]) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) # (!\D[0]~57_combout & (!\Equal2~1_combout & ((!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) - - .dataa(\Equal2~1_combout ), - .datab(\z80_|data_pins_|dout [0]), - .datac(\D[0]~57_combout ), - .datad(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .cin(gnd), - .combout(\D[0]~58_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~58 .lut_mask = 16'hC0F5; -defparam \D[0]~58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N0 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [0] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[0]~17_combout ) # ((\z80_|pin_control_|bus_db_pin_re~combout & \D[0]~58_combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & -// (((\z80_|pin_control_|bus_db_pin_re~combout & \D[0]~58_combout )))) - - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(\z80_|bus_control_|db[0]~17_combout ), - .datac(\z80_|pin_control_|bus_db_pin_re~combout ), - .datad(\D[0]~58_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [0]), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] .lut_mask = 16'hF888; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y13_N1 -dffeas \z80_|data_pins_|dout[0] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [0]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|data_pins_|dout [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|data_pins_|dout[0] .is_wysiwyg = "true"; -defparam \z80_|data_pins_|dout[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N4 -cycloneive_lcell_comb \z80_|bus_control_|db[0]~16 ( -// Equation(s): -// \z80_|bus_control_|db[0]~16_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [0]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) - - .dataa(gnd), - .datab(\z80_|bus_control_|db[0]~4_combout ), - .datac(\z80_|data_pins_|dout [0]), - .datad(\z80_|execute_|ctl_bus_db_oe~combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[0]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[0]~16 .lut_mask = 16'hC0CC; -defparam \z80_|bus_control_|db[0]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N28 -cycloneive_lcell_comb \z80_|bus_control_|db[0]~17 ( -// Equation(s): -// \z80_|bus_control_|db[0]~17_combout = ((\z80_|bus_control_|db[0]~16_combout & ((\z80_|alu_control_|db[0]~12_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - - .dataa(\z80_|bus_control_|db[0]~6_combout ), - .datab(\z80_|alu_control_|db[0]~12_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|bus_control_|db[0]~16_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[0]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[0]~17 .lut_mask = 16'hDF55; -defparam \z80_|bus_control_|db[0]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y13_N27 -dffeas \z80_|ir_|opcode[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|bus_control_|db[0]~17_combout ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|ir_|opcode [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|ir_|opcode[0] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal63~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal63~0_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [5] & (\z80_|execute_|comb~0_combout & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|execute_|comb~0_combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal63~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal63~0 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal63~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_daa ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_sel_daa~combout = (!\z80_|ir_|opcode [4] & (!\z80_|ir_|opcode [3] & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal63~0_combout ))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal63~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_sel_daa .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_flags_cf2_sel_daa .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N20 -cycloneive_lcell_comb \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 ( -// Equation(s): -// \z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout = (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )) # (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ))) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 .lut_mask = 16'h070F; -defparam \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N22 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~10 ( -// Equation(s): -// \z80_|alu_control_|db[6]~10_combout = ((\z80_|execute_|ctl_sw_2u~7_combout ) # (\z80_|execute_|ctl_flags_oe~2_combout )) # (!\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ) - - .dataa(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_sw_2u~7_combout ), - .datad(\z80_|execute_|ctl_flags_oe~2_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~10 .lut_mask = 16'hFFF5; -defparam \z80_|alu_control_|db[6]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N28 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~11 ( -// Equation(s): -// \z80_|alu_control_|db[6]~11_combout = (\z80_|alu_control_|db[6]~10_combout ) # ((\z80_|execute_|ctl_sw_1d~7_combout ) # (\z80_|execute_|ctl_reg_out_lo~8_combout )) - - .dataa(\z80_|alu_control_|db[6]~10_combout ), - .datab(\z80_|execute_|ctl_sw_1d~7_combout ), - .datac(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~11 .lut_mask = 16'hFEFE; -defparam \z80_|alu_control_|db[6]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N18 -cycloneive_lcell_comb \z80_|alu_control_|db[4]~30 ( -// Equation(s): -// \z80_|alu_control_|db[4]~30_combout = (\z80_|alu_|db[4]~17_combout & (\z80_|execute_|ctl_reg_out_lo~8_combout & (!\z80_|reg_file_|gdfx_temp0[4]~62_combout ))) # (!\z80_|alu_|db[4]~17_combout & ((\z80_|execute_|ctl_sw_2u~7_combout ) # -// ((\z80_|execute_|ctl_reg_out_lo~8_combout & !\z80_|reg_file_|gdfx_temp0[4]~62_combout )))) - - .dataa(\z80_|alu_|db[4]~17_combout ), - .datab(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .datad(\z80_|execute_|ctl_sw_2u~7_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[4]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[4]~30 .lut_mask = 16'h5D0C; -defparam \z80_|alu_control_|db[4]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N24 -cycloneive_lcell_comb \z80_|alu_control_|db[4]~31 ( -// Equation(s): -// \z80_|alu_control_|db[4]~31_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & (!\z80_|alu_control_|db[4]~30_combout & ((\z80_|alu_flags_|flags_hf~combout ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) - - .dataa(\z80_|alu_flags_|flags_hf~combout ), - .datab(\z80_|execute_|ctl_flags_oe~2_combout ), - .datac(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .datad(\z80_|alu_control_|db[4]~30_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[4]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[4]~31 .lut_mask = 16'h00B0; -defparam \z80_|alu_control_|db[4]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N6 -cycloneive_lcell_comb \z80_|alu_control_|db[4]~32 ( -// Equation(s): -// \z80_|alu_control_|db[4]~32_combout = ((\z80_|alu_control_|db[4]~31_combout & ((\z80_|bus_control_|db[4]~19_combout ) # (!\z80_|execute_|ctl_sw_1d~7_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|bus_control_|db[4]~19_combout ), - .datab(\z80_|alu_control_|db[6]~11_combout ), - .datac(\z80_|execute_|ctl_sw_1d~7_combout ), - .datad(\z80_|alu_control_|db[4]~31_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[4]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[4]~32 .lut_mask = 16'hBF33; -defparam \z80_|alu_control_|db[4]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~119 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][4]~119_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [2]))) # (!\ula_|ps2_keyboard_|shiftreg [0] & -// (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [2]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [0]), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][4]~119_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][4]~119 .lut_mask = 16'h0420; -defparam \ula_|zx_keyboard_|keys[2][4]~119 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~120 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][4]~120_combout = (\ula_|zx_keyboard_|keys[5][1]~36_combout & (\ula_|zx_keyboard_|keys[2][4]~119_combout & (\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [1]))) - - .dataa(\ula_|zx_keyboard_|keys[5][1]~36_combout ), - .datab(\ula_|zx_keyboard_|keys[2][4]~119_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][4]~120_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][4]~120 .lut_mask = 16'h0080; -defparam \ula_|zx_keyboard_|keys[2][4]~120 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~95 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][4]~95_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [6])) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|shifted~q ), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][4]~95_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][4]~95 .lut_mask = 16'hAFAA; -defparam \ula_|zx_keyboard_|keys[2][4]~95 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~121 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][4]~121_combout = (\ula_|zx_keyboard_|keys[2][4]~120_combout & ((!\ula_|zx_keyboard_|keys[2][4]~95_combout ))) # (!\ula_|zx_keyboard_|keys[2][4]~120_combout & (\ula_|zx_keyboard_|keys[2][4]~q )) - - .dataa(\ula_|zx_keyboard_|keys[2][4]~120_combout ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[2][4]~q ), - .datad(\ula_|zx_keyboard_|keys[2][4]~95_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][4]~121_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][4]~121 .lut_mask = 16'h50FA; -defparam \ula_|zx_keyboard_|keys[2][4]~121 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y18_N23 -dffeas \ula_|zx_keyboard_|keys[2][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[2][4]~121_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[2][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[2][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~117 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][4]~117_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|zx_keyboard_|extended~q ))) # (!\ula_|ps2_keyboard_|shiftreg [2] & -// (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|zx_keyboard_|extended~q ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|zx_keyboard_|extended~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][4]~117_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][4]~117 .lut_mask = 16'h4002; -defparam \ula_|zx_keyboard_|keys[3][4]~117 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~136 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][4]~136_combout = (\ula_|zx_keyboard_|keys[3][4]~117_combout & (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [4]))) - - .dataa(\ula_|zx_keyboard_|keys[3][4]~117_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][4]~136_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][4]~136 .lut_mask = 16'h0080; -defparam \ula_|zx_keyboard_|keys[3][4]~136 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y21_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~130 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][4]~130_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (!\ula_|zx_keyboard_|Equal0~1_combout & (!\ula_|ps2_keyboard_|shiftreg [7] & \ula_|ps2_keyboard_|shiftreg [5]))) - - .dataa(\ula_|ps2_keyboard_|scan_code_ready~q ), - .datab(\ula_|zx_keyboard_|Equal0~1_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [7]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][4]~130_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][4]~130 .lut_mask = 16'h0200; -defparam \ula_|zx_keyboard_|keys[3][4]~130 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~118 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][4]~118_combout = (\ula_|zx_keyboard_|keys[3][4]~136_combout & ((\ula_|zx_keyboard_|keys[3][4]~130_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][4]~130_combout & ((\ula_|zx_keyboard_|keys[3][4]~q -// ))))) # (!\ula_|zx_keyboard_|keys[3][4]~136_combout & (((\ula_|zx_keyboard_|keys[3][4]~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[3][4]~136_combout ), - .datac(\ula_|zx_keyboard_|keys[3][4]~q ), - .datad(\ula_|zx_keyboard_|keys[3][4]~130_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][4]~118_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][4]~118 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[3][4]~118 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y18_N9 -dffeas \ula_|zx_keyboard_|keys[3][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[3][4]~118_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[3][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[3][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N18 -cycloneive_lcell_comb \D[4]~78 ( -// Equation(s): -// \D[4]~78_combout = (\z80_|address_pins_|abus[11]~19_combout & ((\z80_|address_pins_|abus[10]~24_combout ) # ((!\ula_|zx_keyboard_|keys[2][4]~q )))) # (!\z80_|address_pins_|abus[11]~19_combout & (!\ula_|zx_keyboard_|keys[3][4]~q & -// ((\z80_|address_pins_|abus[10]~24_combout ) # (!\ula_|zx_keyboard_|keys[2][4]~q )))) - - .dataa(\z80_|address_pins_|abus[11]~19_combout ), - .datab(\z80_|address_pins_|abus[10]~24_combout ), - .datac(\ula_|zx_keyboard_|keys[2][4]~q ), - .datad(\ula_|zx_keyboard_|keys[3][4]~q ), - .cin(gnd), - .combout(\D[4]~78_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~78 .lut_mask = 16'h8ACF; -defparam \D[4]~78 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~126 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][4]~126_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[7][1]~23_combout & (\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [6]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|zx_keyboard_|keys[7][1]~23_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][4]~126_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][4]~126 .lut_mask = 16'h0040; -defparam \ula_|zx_keyboard_|keys[6][4]~126 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~128 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][4]~128_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [1]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][4]~128_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][4]~128 .lut_mask = 16'h0080; -defparam \ula_|zx_keyboard_|keys[5][4]~128 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~129 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][4]~129_combout = (\ula_|zx_keyboard_|keys[6][4]~126_combout & ((\ula_|zx_keyboard_|keys[5][4]~128_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[5][4]~128_combout & -// (\ula_|zx_keyboard_|keys[5][4]~q )))) # (!\ula_|zx_keyboard_|keys[6][4]~126_combout & (((\ula_|zx_keyboard_|keys[5][4]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[6][4]~126_combout ), - .datab(\ula_|zx_keyboard_|keys[5][4]~128_combout ), - .datac(\ula_|zx_keyboard_|keys[5][4]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][4]~129_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][4]~129 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[5][4]~129 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y19_N9 -dffeas \ula_|zx_keyboard_|keys[5][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[5][4]~129_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[5][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[5][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~127 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][4]~127_combout = (\ula_|zx_keyboard_|keys[6][4]~126_combout & ((\ula_|zx_keyboard_|keys[6][4]~20_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[6][4]~20_combout & ((\ula_|zx_keyboard_|keys[6][4]~q -// ))))) # (!\ula_|zx_keyboard_|keys[6][4]~126_combout & (((\ula_|zx_keyboard_|keys[6][4]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[6][4]~126_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[6][4]~q ), - .datad(\ula_|zx_keyboard_|keys[6][4]~20_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][4]~127_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][4]~127 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[6][4]~127 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y20_N5 -dffeas \ula_|zx_keyboard_|keys[6][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[6][4]~127_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[6][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[6][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~2 ( -// Equation(s): -// \ula_|zx_keyboard_|Equal0~2_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [0])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|Equal0~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|Equal0~2 .lut_mask = 16'h0050; -defparam \ula_|zx_keyboard_|Equal0~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~51 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][4]~51_combout = (\ula_|zx_keyboard_|keys[7][1]~23_combout & (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [1] & \ula_|zx_keyboard_|Equal0~2_combout ))) - - .dataa(\ula_|zx_keyboard_|keys[7][1]~23_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|zx_keyboard_|Equal0~2_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][4]~51_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][4]~51 .lut_mask = 16'h2000; -defparam \ula_|zx_keyboard_|keys[7][4]~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~125 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][4]~125_combout = (\ula_|zx_keyboard_|shifted~1_combout & ((\ula_|zx_keyboard_|keys[7][4]~51_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[7][4]~51_combout & ((\ula_|zx_keyboard_|keys[7][4]~q ))))) -// # (!\ula_|zx_keyboard_|shifted~1_combout & (((\ula_|zx_keyboard_|keys[7][4]~q )))) - - .dataa(\ula_|zx_keyboard_|shifted~1_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[7][4]~q ), - .datad(\ula_|zx_keyboard_|keys[7][4]~51_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][4]~125_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][4]~125 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[7][4]~125 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y20_N11 -dffeas \ula_|zx_keyboard_|keys[7][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[7][4]~125_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[7][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[7][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N30 -cycloneive_lcell_comb \D[4]~79 ( -// Equation(s): -// \D[4]~79_combout = (\z80_|address_pins_|abus[15]~22_combout & ((\z80_|address_pins_|abus[14]~23_combout ) # ((!\ula_|zx_keyboard_|keys[6][4]~q )))) # (!\z80_|address_pins_|abus[15]~22_combout & (!\ula_|zx_keyboard_|keys[7][4]~q & -// ((\z80_|address_pins_|abus[14]~23_combout ) # (!\ula_|zx_keyboard_|keys[6][4]~q )))) - - .dataa(\z80_|address_pins_|abus[15]~22_combout ), - .datab(\z80_|address_pins_|abus[14]~23_combout ), - .datac(\ula_|zx_keyboard_|keys[6][4]~q ), - .datad(\ula_|zx_keyboard_|keys[7][4]~q ), - .cin(gnd), - .combout(\D[4]~79_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~79 .lut_mask = 16'h8ACF; -defparam \D[4]~79 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~122 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][4]~122_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|zx_keyboard_|extended~q )) # (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [6] & -// \ula_|zx_keyboard_|extended~q )) - - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(gnd), - .datad(\ula_|zx_keyboard_|extended~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][4]~122_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][4]~122 .lut_mask = 16'h4422; -defparam \ula_|zx_keyboard_|keys[4][4]~122 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~123 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][4]~123_combout = (\ula_|zx_keyboard_|Equal0~2_combout & (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[4][4]~122_combout ))) - - .dataa(\ula_|zx_keyboard_|Equal0~2_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|keys[4][4]~122_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][4]~123_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][4]~123 .lut_mask = 16'h8000; -defparam \ula_|zx_keyboard_|keys[4][4]~123 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~124 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][4]~124_combout = (\ula_|zx_keyboard_|keys[0][0]~15_combout & ((\ula_|zx_keyboard_|keys[4][4]~123_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[4][4]~123_combout & ((\ula_|zx_keyboard_|keys[4][4]~q -// ))))) # (!\ula_|zx_keyboard_|keys[0][0]~15_combout & (((\ula_|zx_keyboard_|keys[4][4]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[4][4]~q ), - .datad(\ula_|zx_keyboard_|keys[4][4]~123_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][4]~124_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][4]~124 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[4][4]~124 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y19_N25 -dffeas \ula_|zx_keyboard_|keys[4][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[4][4]~124_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[4][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[4][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~3 ( -// Equation(s): -// \ula_|zx_keyboard_|key_row~3_combout = ((\z80_|address_pins_|DFFE_apin_latch [12]) # (!\ula_|zx_keyboard_|keys[4][4]~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [12]), - .datad(\ula_|zx_keyboard_|keys[4][4]~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|key_row~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|key_row~3 .lut_mask = 16'hF3FF; -defparam \ula_|zx_keyboard_|key_row~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N8 -cycloneive_lcell_comb \D[4]~80 ( -// Equation(s): -// \D[4]~80_combout = (\D[4]~79_combout & (\ula_|zx_keyboard_|key_row~3_combout & ((\z80_|address_pins_|abus[13]~20_combout ) # (!\ula_|zx_keyboard_|keys[5][4]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[5][4]~q ), - .datab(\D[4]~79_combout ), - .datac(\z80_|address_pins_|abus[13]~20_combout ), - .datad(\ula_|zx_keyboard_|key_row~3_combout ), - .cin(gnd), - .combout(\D[4]~80_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~80 .lut_mask = 16'hC400; -defparam \D[4]~80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~111 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][4]~111_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [6])) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|shifted~q ), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][4]~111_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][4]~111 .lut_mask = 16'hFAAA; -defparam \ula_|zx_keyboard_|keys[0][4]~111 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~97 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][4]~97_combout = (\ula_|zx_keyboard_|keys[5][1]~36_combout & (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [6] $ (\ula_|ps2_keyboard_|shiftreg [5])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|zx_keyboard_|keys[5][1]~36_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][4]~97_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][4]~97 .lut_mask = 16'h0060; -defparam \ula_|zx_keyboard_|keys[0][4]~97 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~116 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][4]~116_combout = (\ula_|zx_keyboard_|keys[3][1]~29_combout & ((\ula_|zx_keyboard_|keys[0][4]~97_combout & (!\ula_|zx_keyboard_|keys[0][4]~111_combout )) # (!\ula_|zx_keyboard_|keys[0][4]~97_combout & -// ((\ula_|zx_keyboard_|keys[0][4]~q ))))) # (!\ula_|zx_keyboard_|keys[3][1]~29_combout & (((\ula_|zx_keyboard_|keys[0][4]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[3][1]~29_combout ), - .datab(\ula_|zx_keyboard_|keys[0][4]~111_combout ), - .datac(\ula_|zx_keyboard_|keys[0][4]~q ), - .datad(\ula_|zx_keyboard_|keys[0][4]~97_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][4]~116_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][4]~116 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[0][4]~116 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y18_N11 -dffeas \ula_|zx_keyboard_|keys[0][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[0][4]~116_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[0][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[0][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][4]~115 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][4]~115_combout = (\ula_|zx_keyboard_|Equal0~2_combout & ((\ula_|zx_keyboard_|keys[1][4]~25_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[1][4]~25_combout & (\ula_|zx_keyboard_|keys[1][4]~q )))) # -// (!\ula_|zx_keyboard_|Equal0~2_combout & (((\ula_|zx_keyboard_|keys[1][4]~q )))) - - .dataa(\ula_|zx_keyboard_|Equal0~2_combout ), - .datab(\ula_|zx_keyboard_|keys[1][4]~25_combout ), - .datac(\ula_|zx_keyboard_|keys[1][4]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][4]~115_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][4]~115 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[1][4]~115 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y19_N7 -dffeas \ula_|zx_keyboard_|keys[1][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[1][4]~115_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[1][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[1][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N28 -cycloneive_lcell_comb \D[4]~77 ( -// Equation(s): -// \D[4]~77_combout = (\z80_|address_pins_|abus[9]~17_combout & ((\z80_|address_pins_|abus[8]~18_combout ) # ((!\ula_|zx_keyboard_|keys[0][4]~q )))) # (!\z80_|address_pins_|abus[9]~17_combout & (!\ula_|zx_keyboard_|keys[1][4]~q & -// ((\z80_|address_pins_|abus[8]~18_combout ) # (!\ula_|zx_keyboard_|keys[0][4]~q )))) - - .dataa(\z80_|address_pins_|abus[9]~17_combout ), - .datab(\z80_|address_pins_|abus[8]~18_combout ), - .datac(\ula_|zx_keyboard_|keys[0][4]~q ), - .datad(\ula_|zx_keyboard_|keys[1][4]~q ), - .cin(gnd), - .combout(\D[4]~77_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~77 .lut_mask = 16'h8ACF; -defparam \D[4]~77 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N26 -cycloneive_lcell_comb \D[4]~81 ( -// Equation(s): -// \D[4]~81_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[4]~78_combout & (\D[4]~80_combout & \D[4]~77_combout ))) - - .dataa(\z80_|address_pins_|abus[0]~16_combout ), - .datab(\D[4]~78_combout ), - .datac(\D[4]~80_combout ), - .datad(\D[4]~77_combout ), - .cin(gnd), - .combout(\D[4]~81_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~81 .lut_mask = 16'hEAAA; -defparam \D[4]~81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y1_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a12 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'hA50276000854A0103840403E540424244404783E18807A08A47C54484448544A807E7E10005270182040407E4A1252124208084008404208420A4A42424A125A024428106448524A624A4A24425242522060108010543C00044A105424005E0031ED1E0529E507AE2F6FF1CD51D4C772A648E65F6532C28022061303F06C36CDBD319B55CB8E626C20E46C93C1463A0B1CE594F0ED3B62330C104DECE46CA6CD966B1386612C7B43980349408F36FB64C14342DAE26CE4D8D5E791388729D743B09A27AB81D71A14AB3D24E385B602248476D00249239514B58D3098504ACD119B99E9021B650A69494C22600667473128DA5010D2195982823226DED0ADFCB8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h5861917919344A4685CC0990862A11324792E761B6D41C0FCC0838C1C27211A2453FDC2219C225E421B320085A8FBFD0C42135B16448DFC226E09B3438A740C352979565817114DE46462844A57F7958873FC4B255C8AE549BDD1A87415D5018F88D5002628FFD13203066C850F10649F21319109208387641120B362124803F0678522BA2812C1454A502ED1A59CBD76A034756F5765DF7555F57575F7F57FFFF7FFF7D5712524D4A30723514B2B3064A84B4742D48415281863DDFAA9D9B7E7BB16DDB96B7845371C30B55DB96C8F6EB4B453242FF6A4DF84A76B5AEDC88A68DC6A06905054C8C36E4199E74638E6532965218A965909BA456000451343351; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'hE2975A2686A7AE0288F140141B698E2A82A835F478453A1D722CFCED12859FD735188757AC5A42DEB501FE010586249AC1EA60D08F74CFA5086EC78FC9190C056059E332C311521E6522901852D484B423A98816C9B26A08C92368E9FF05524502288A804612A2A0A102A418CBDFBA554499541660F8124640110101263142892A086B442661015380041594608092D9CB919250100A37DDA3919A1427F660963C251301FB2CA45562245308885131119115C652B2493252340201101942D26000CC60799124A8520C08050122171281808058018C38A645D07931896B39ED259A22242CB58413089465B246231330D806105010035100B08761A08506094160; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h1228D91C352915424000000AA0088F63153A8AD81B945C8789F01C86548D12CEAB6AA38578BD55CEC9AA28082C285B8C0201104838AD502AC160C13C70620B818249144AB52CED94200A0202A885100E0D938A30A34512C0CEC98F08A98900F2093E11673256B3169C12284980E92A034141E0782507800F8100009C403C07867000000030082004A17800828F090A0C318CE120012172286317922341A2A12840B6C18040682080125C75401AEC44E8C01A8D40D1412B25A09F7600B0C6FEC65BFE5CE861A20F71E8032916A78F29CC546518461522E4E14998DD54BC0E40B64B710C9DC948F06010DF01D880E2044BE8854062D10DD93F30A62AA7FD227C4C; -// synopsys translate_on - -// Location: M9K_X22_Y22_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a12 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(gnd), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[4]~98_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_first_bit_number = 4; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y3_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a4 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h35861A00A6112A1481AF1A50A6004A05291627227FF08229B87389E08119A28A7888672DC999B7046A61E60810A7434450E3D33E330F321A18E8A120D1EDC8623DA2C64840C2CCE811522B42008095E5A456C98F4B25EAEA410610545024640CF10410AC463BF9349074917E9A74A12830EFA280EBD3131E484A255D0191C6852730A263DBCCAAA88712242B3BE49AA5338990229B391158C726BC7EB4ECC32308980020680249882691A680488292310B4313CE87FFCD5329A64B708CAC8533316412C4900F646A36630261DA093053D98F19D2C5B653165D4A71AA5682B29B89B6054CC727D292805705A93268676A31111371390B240EC3CC85D331813EB1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h1AA1C248D293110CB951445117D9B6AA500F65068B8CC508BD00184F8705B010A0CC46CC9302649242CE08191634113154562B149100204551178DE805D98EC8A2E5A64B241400267194CD524499BC01D31058CD18684A817A5800B65143281C1310B00A49902C0104004C654E0582040001103654011012021912281216B000C653A0510A1B00C36AC88058CAC126E14E198DFB07E81C3F41510BB08F8F851C3B9AF0147BC1F730B4E91D9D11C3A8F1B82DF19988ACC44072FDB17B4D81882E9DD952B29003D7767BA581A68BC41C2B16AD6EB57F1D048CD4E464190D25ADF2C194E3598360AFB031A1690F4625BB628363B4C90A400E3A04DAA70DA0CC4776; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'hC82B30671933680037A65978674DDEC2D30EEEDA78F5F2A1DEE660FFEA11B175DCB42E9277212A58842051A078007109A0D820166B881042600284403143048295D23A0E191EBC2134B833D53D37E42B05018289A10300A188E315CE98640F548A370D60A0AA3E7288A0B0869FA5E703D1AE17C0EC276B2AFB747B550A8B41021620D1A60A901095D12A0973B95E20838001330138951361967847D42901910A3488480610A91A851E84FF08783F81AEA52D2FDC2200BD2FE81C0357FBEC1D875686C6CA41B2224C88D8456C1DBF20D820A6649774CB11B69933246E9739C998470542C2E3C783A4C24767084C52DC209D60E95DBC096D9A0171A12D5AB99BAB; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h17A24D2C636ED2478B5AE1C99D40761B1E7AA6A89DDD1BBD8DBD223E70531BCDE90C8E38C8E0478AD8B388F94891C9673A50BC32478E083074657E8E0EA53BEE861F8BC1993560946D92D1C0C7F046A245B5849CB751FF15B97FCD50BC7B8524C13E7C640F3645082248D1CC14296E30DEA3057B35C641762CD00D40DABC27472251A60725008AAA056591C4000BB48C0BC29B8034A03400027B84769B520D9196968460CA3388A03ECB45F2C4B70F1829221000FFFC7FEC346F079F13079798EC2A08157331C6CC0E30884244916A0DE26D4D22454091290404A492016887E2111F830F9851184101370588A06D3BF9AE621A5F4E632A6799C83EFAAE06769D; -// synopsys translate_on - -// Location: M9K_X22_Y25_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a4 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[4]~98_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a4_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_first_bit_number = 4; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFFF0000003E0000003E0000C83F0000D83F0000F03F0000303E0000303E0000003F0010003F0010203F0010F03F0010703F0018303F001C603D800C003CFE26003C7F0F803FFFFFFFFFFFFFFFF; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF00000000000008108000BDF288E9688E000000000000000000000000FFFFFFFF0000000000041D989EA296D29EE969CA000000000000000000000000000000007FFFFFFC8004198A9AA298929EE9498A00000000000000000000000000000000FFFFFFFE800400CA9AA2AADA8AE949CE0000000000000000000000007FFFFFFEC00000028004046A9F22BA5A9EE90FC20000000000000000000000007FFFFFFE8000000280040FEA8002AA7A9EE12742000000000000000000000000000000023FFFFFFC9FE42BA298E2293A80096742000000000000000000000000000000003FFFFFFC9FE4B19298E3181E8009436A; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'h9FE8234A88F836EE9FF8BD4208282BC080DE87C2B84199C2B85E37C2B05B3A829FE8236688F837CE9FF8898208A82A44808A87CAB9C19DC2B80E3AC2927F2AC2800833E288F837C69FE8AB9688882E4283248DC2B9D188C2ABAE2F8291371092800832EA887807C69FE8AB8688080AC283E49D42B914BFC2A3BF1E82910712EA800802EA883807869DE88E8688080AC68BC4BDC2BB1439C2A27F5F82910314E2800886E6880807C69CC89A8681800BC289549CC2AB0C3942A04B7F82953315E2800886EE900805C61C089FC081E415C289D89DC2AB4E3142A1233D8217330090800086EE900805821C08BEC080D407C289C89DC2AADE3142A13B7F82176300F0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h076B0A5083288F028370C182A801468297E5AC1288D308023FFFFFFC00000000072BA9608BA08D028BF4D182AC015682937CA80288D308023FFFFFFC00000002872B892A8FA08F028A14509AAC0166B2B37DA80288D10D02800000027FFFFFFE852BAD128E388D028A004082AC0166C2937DA00288D10F02C00000027FFFFFFE846289368968C90289E0528A8C016CA29379B20280510F02FFFFFFFE0000000085E2A922816089828BE0428286416C829179B00280511F027FFFFFFC0000000087EA8B32872089828800569287436CA28179B20200513F0000000000FFFFFFFF8768A3028610858288004682874364828019900200403E0000000000FFFFFFFF; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N2 -cycloneive_lcell_comb \Selector4~0 ( -// Equation(s): -// \Selector4~0_combout = (\z80_|address_pins_|abus[14]~23_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout )))) # (!\z80_|address_pins_|abus[14]~23_combout -// & (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ))) - - .dataa(\z80_|address_pins_|abus[14]~23_combout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout ), - .cin(gnd), - .combout(\Selector4~0_combout ), - .cout()); -// synopsys translate_off -defparam \Selector4~0 .lut_mask = 16'hBA98; -defparam \Selector4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N26 -cycloneive_lcell_comb \Selector4~1 ( -// Equation(s): -// \Selector4~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Selector4~0_combout & ((\ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ))) # (!\Selector4~0_combout & -// (\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Selector4~0_combout )))) - - .dataa(\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ), - .datad(\Selector4~0_combout ), - .cin(gnd), - .combout(\Selector4~1_combout ), - .cout()); -// synopsys translate_off -defparam \Selector4~1 .lut_mask = 16'hF388; -defparam \Selector4~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y14_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a28 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[4]~98_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a28_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_first_bit_number = 4; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y8_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a12 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[4]~98_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y16_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a20 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[4]~98_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_first_bit_number = 4; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y3_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a4 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[4]~98_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N20 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout )) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ))))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout ), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2 .lut_mask = 16'hE5E0; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N10 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2_combout & -// (\ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout )) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ))))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2_combout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2_combout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3 .lut_mask = 16'hAFC0; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N6 -cycloneive_lcell_comb \D[4]~109 ( -// Equation(s): -// \D[4]~109_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\Selector4~1_combout -// )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3_combout ))))) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\Selector4~1_combout ), - .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3_combout ), - .cin(gnd), - .combout(\D[4]~109_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~109 .lut_mask = 16'hFB40; -defparam \D[4]~109 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N18 -cycloneive_lcell_comb \D[4]~97 ( -// Equation(s): -// \D[4]~97_combout = ((\Equal2~0_combout & (\D[4]~81_combout )) # (!\Equal2~0_combout & ((\D[4]~109_combout )))) # (!\Equal2~1_combout ) - - .dataa(\Equal2~0_combout ), - .datab(\D[4]~81_combout ), - .datac(\Equal2~1_combout ), - .datad(\D[4]~109_combout ), - .cin(gnd), - .combout(\D[4]~97_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~97 .lut_mask = 16'hDF8F; -defparam \D[4]~97 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N30 -cycloneive_lcell_comb \D[4]~98 ( -// Equation(s): -// \D[4]~98_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout & (\z80_|data_pins_|dout [4] & ((\D[4]~97_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\D[4]~97_combout ) # (!\Equal2~1_combout )))) - - .dataa(\z80_|data_pins_|dout [4]), - .datab(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datac(\Equal2~1_combout ), - .datad(\D[4]~97_combout ), - .cin(gnd), - .combout(\D[4]~98_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~98 .lut_mask = 16'hBB03; -defparam \D[4]~98 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N24 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[4] ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [4] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[4]~19_combout ) # ((\D[4]~98_combout & \z80_|pin_control_|bus_db_pin_re~combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & -// (\D[4]~98_combout & (\z80_|pin_control_|bus_db_pin_re~combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(\D[4]~98_combout ), - .datac(\z80_|pin_control_|bus_db_pin_re~combout ), - .datad(\z80_|bus_control_|db[4]~19_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [4]), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[4] .lut_mask = 16'hEAC0; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[4] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y13_N25 -dffeas \z80_|data_pins_|dout[4] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [4]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|data_pins_|dout [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|data_pins_|dout[4] .is_wysiwyg = "true"; -defparam \z80_|data_pins_|dout[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N20 -cycloneive_lcell_comb \z80_|bus_control_|db[4]~18 ( -// Equation(s): -// \z80_|bus_control_|db[4]~18_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [4]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) - - .dataa(\z80_|data_pins_|dout [4]), - .datab(\z80_|bus_control_|db[0]~4_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_bus_db_oe~combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[4]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[4]~18 .lut_mask = 16'h88CC; -defparam \z80_|bus_control_|db[4]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N18 -cycloneive_lcell_comb \z80_|bus_control_|db[4]~19 ( -// Equation(s): -// \z80_|bus_control_|db[4]~19_combout = ((\z80_|bus_control_|db[4]~18_combout & ((\z80_|alu_control_|db[4]~32_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - - .dataa(\z80_|bus_control_|db[0]~6_combout ), - .datab(\z80_|alu_control_|db[4]~32_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|bus_control_|db[4]~18_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[4]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[4]~19 .lut_mask = 16'hDF55; -defparam \z80_|bus_control_|db[4]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y10_N19 -dffeas \z80_|ir_|opcode[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|bus_control_|db[4]~19_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|ir_|opcode [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|ir_|opcode[4] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal21~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal21~0_combout = (!\z80_|ir_|opcode [3] & \z80_|ir_|opcode [4]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal21~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal21~0 .lut_mask = 16'h0F00; -defparam \z80_|pla_decode_|Equal21~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~5 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~5_combout = (\z80_|pla_decode_|Equal21~0_combout & (\z80_|pla_decode_|Equal2~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal1~7_combout ))) - - .dataa(\z80_|pla_decode_|Equal21~0_combout ), .datab(\z80_|pla_decode_|Equal2~0_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~15 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_mRead~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~39 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~39_combout = (((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|execute_|ctl_mRead~15_combout ) + + .dataa(\z80_|sequencer_|M5~q ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|execute_|ctl_mRead~15_combout ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~39 .lut_mask = 16'h1FFF; +defparam \z80_|execute_|ctl_inc_cy~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~36 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~36_combout = (\z80_|execute_|ctl_inc_cy~39_combout & (\z80_|execute_|ctl_inc_cy~38_combout & \z80_|execute_|ctl_inc_cy~82_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_inc_cy~39_combout ), + .datac(\z80_|execute_|ctl_inc_cy~38_combout ), + .datad(\z80_|execute_|ctl_inc_cy~82_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~36 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~4 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~4_combout = (\z80_|execute_|ctl_alu_op_low~22_combout & (\z80_|pla_decode_|Equal55~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal1~7_combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~5_combout ), + .combout(\z80_|execute_|ctl_sw_4u~4_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mRead~5 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_mRead~5 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_sw_4u~4 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_sw_4u~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y18_N22 -cycloneive_lcell_comb \z80_|execute_|fIOWrite~2 ( +// Location: LCCOMB_X21_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~16 ( // Equation(s): -// \z80_|execute_|fIOWrite~2_combout = (\z80_|execute_|ctl_iorw~11_combout & ((\z80_|execute_|ctl_mWrite~3_combout ) # ((\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|fMRead~0_combout )))) +// \z80_|execute_|ctl_reg_sel_wz~16_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & (!\z80_|execute_|ctl_sw_4u~4_combout & ((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|ctl_ir_we~12_combout )))) - .dataa(\z80_|execute_|ctl_mWrite~3_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_iorw~11_combout ), - .datad(\z80_|execute_|fMRead~0_combout ), + .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), + .datab(\z80_|execute_|ctl_ir_we~12_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_sw_4u~4_combout ), .cin(gnd), - .combout(\z80_|execute_|fIOWrite~2_combout ), + .combout(\z80_|execute_|ctl_reg_sel_wz~16_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fIOWrite~2 .lut_mask = 16'hE0F0; -defparam \z80_|execute_|fIOWrite~2 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_reg_sel_wz~16 .lut_mask = 16'h0015; +defparam \z80_|execute_|ctl_reg_sel_wz~16 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y18_N16 -cycloneive_lcell_comb \z80_|execute_|fIOWrite~3 ( +// Location: LCCOMB_X21_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~17 ( // Equation(s): -// \z80_|execute_|fIOWrite~3_combout = ((!\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ) +// \z80_|execute_|ctl_reg_sel_wz~17_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~36_combout & (\z80_|execute_|fMRead~6_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout & \z80_|execute_|ctl_reg_sel_wz~16_combout ))) - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~36_combout ), + .datab(\z80_|execute_|fMRead~6_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~16_combout ), .cin(gnd), - .combout(\z80_|execute_|fIOWrite~3_combout ), + .combout(\z80_|execute_|ctl_reg_sel_wz~17_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fIOWrite~3 .lut_mask = 16'h3F0F; -defparam \z80_|execute_|fIOWrite~3 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_reg_sel_wz~17 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sel_wz~17 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y18_N2 -cycloneive_lcell_comb \z80_|execute_|fIOWrite~4 ( +// Location: LCCOMB_X27_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~5 ( // Equation(s): -// \z80_|execute_|fIOWrite~4_combout = (\z80_|execute_|ctl_mRead~36_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ixy_d~6_combout ) # (!\z80_|execute_|fIOWrite~3_combout )))) +// \z80_|execute_|ctl_sw_4u~5_combout = (\z80_|execute_|ctl_alu_op_low~28_combout ) # (((\z80_|execute_|ctl_alu_shift_oe~14_combout & \z80_|pla_decode_|Equal47~0_combout )) # (!\z80_|execute_|ctl_sw_4u~1_combout )) - .dataa(\z80_|execute_|ctl_mRead~36_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|execute_|fIOWrite~3_combout ), + .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datab(\z80_|pla_decode_|Equal47~0_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~28_combout ), + .datad(\z80_|execute_|ctl_sw_4u~1_combout ), .cin(gnd), - .combout(\z80_|execute_|fIOWrite~4_combout ), + .combout(\z80_|execute_|ctl_sw_4u~5_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fIOWrite~4 .lut_mask = 16'hA8AA; -defparam \z80_|execute_|fIOWrite~4 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_sw_4u~5 .lut_mask = 16'hF8FF; +defparam \z80_|execute_|ctl_sw_4u~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y18_N4 -cycloneive_lcell_comb \z80_|execute_|fIOWrite~5 ( +// Location: LCCOMB_X29_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~6 ( // Equation(s): -// \z80_|execute_|fIOWrite~5_combout = (\z80_|execute_|fIOWrite~2_combout ) # ((\z80_|execute_|fIOWrite~4_combout ) # ((\z80_|execute_|fIOWrite~1_combout & \z80_|execute_|ctl_mRead~5_combout ))) +// \z80_|execute_|ctl_sw_4u~6_combout = (((\z80_|execute_|ctl_sw_4u~5_combout ) # (!\z80_|execute_|ctl_sw_4u~3_combout )) # (!\z80_|execute_|ctl_apin_mux~0_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~17_combout ) - .dataa(\z80_|execute_|fIOWrite~1_combout ), - .datab(\z80_|execute_|ctl_mRead~5_combout ), - .datac(\z80_|execute_|fIOWrite~2_combout ), - .datad(\z80_|execute_|fIOWrite~4_combout ), + .dataa(\z80_|execute_|ctl_reg_sel_wz~17_combout ), + .datab(\z80_|execute_|ctl_apin_mux~0_combout ), + .datac(\z80_|execute_|ctl_sw_4u~3_combout ), + .datad(\z80_|execute_|ctl_sw_4u~5_combout ), .cin(gnd), - .combout(\z80_|execute_|fIOWrite~5_combout ), + .combout(\z80_|execute_|ctl_sw_4u~6_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fIOWrite~5 .lut_mask = 16'hFFF8; -defparam \z80_|execute_|fIOWrite~5 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_sw_4u~6 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_sw_4u~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y17_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~11 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~11_combout = (!\z80_|execute_|ctl_mWrite~10_combout & (((!\z80_|execute_|ctl_mRead~10_combout & !\z80_|execute_|ctl_mRead~8_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|execute_|ctl_mWrite~10_combout ), - .datac(\z80_|execute_|ctl_mRead~8_combout ), - .datad(\z80_|execute_|ctl_state_alu~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~11 .lut_mask = 16'h0133; -defparam \z80_|execute_|ctl_mWrite~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~12 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~12_combout = (\z80_|execute_|ctl_mWrite~8_combout & (\z80_|execute_|ctl_mWrite~11_combout & ((!\z80_|execute_|ctl_mWrite~6_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|ctl_mWrite~8_combout ), - .datac(\z80_|execute_|ctl_mWrite~6_combout ), - .datad(\z80_|execute_|ctl_mWrite~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~12 .lut_mask = 16'h4C00; -defparam \z80_|execute_|ctl_mWrite~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~13 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~13_combout = (\z80_|execute_|ctl_mWrite~12_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~4_combout & (\z80_|execute_|ctl_mWrite~9_combout & \z80_|execute_|ctl_bus_db_oe~7_combout ))) - - .dataa(\z80_|execute_|ctl_mWrite~12_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), - .datac(\z80_|execute_|ctl_mWrite~9_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~13 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_mWrite~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~14 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~14_combout = (\z80_|execute_|ctl_state_alu~4_combout & ((\z80_|execute_|ctl_mRead~7_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & \z80_|execute_|ctl_mWrite~5_combout )))) # (!\z80_|execute_|ctl_state_alu~4_combout & -// (((\z80_|execute_|ctl_eval_cond~0_combout & \z80_|execute_|ctl_mWrite~5_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_mRead~7_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_mWrite~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~14 .lut_mask = 16'hF888; -defparam \z80_|execute_|ctl_mWrite~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~15 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~15_combout = ((\z80_|execute_|ctl_mWrite~14_combout ) # ((!\z80_|execute_|ixy_d~17_combout & \z80_|execute_|ixy_d~8_combout ))) # (!\z80_|execute_|ctl_mWrite~13_combout ) - - .dataa(\z80_|execute_|ixy_d~17_combout ), - .datab(\z80_|execute_|ctl_mWrite~13_combout ), - .datac(\z80_|execute_|ctl_mWrite~14_combout ), - .datad(\z80_|execute_|ixy_d~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~15 .lut_mask = 16'hF7F3; -defparam \z80_|execute_|ctl_mWrite~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X43_Y17_N29 -dffeas \z80_|memory_ifc_|DFFE_mwr_ff1 ( +// Location: FF_X30_Y12_N27 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[3] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_mWrite~15_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_mwr_ff1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_mwr_ff1 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_mwr_ff1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N4 -cycloneive_lcell_comb \z80_|memory_ifc_|wait_mwr~feeder ( -// Equation(s): -// \z80_|memory_ifc_|wait_mwr~feeder_combout = \z80_|memory_ifc_|DFFE_mwr_ff1~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|memory_ifc_|DFFE_mwr_ff1~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|wait_mwr~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_mwr~feeder .lut_mask = 16'hFF00; -defparam \z80_|memory_ifc_|wait_mwr~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X43_Y17_N5 -dffeas \z80_|memory_ifc_|wait_mwr ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|memory_ifc_|wait_mwr~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|wait_mwr~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_mwr .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|wait_mwr .power_up = "low"; -// synopsys translate_on - -// Location: FF_X43_Y17_N17 -dffeas \z80_|memory_ifc_|mwr_wr ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), - .asdata(\z80_|memory_ifc_|wait_mwr~q ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|mwr_wr~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|mwr_wr .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|mwr_wr .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N16 -cycloneive_lcell_comb \z80_|memory_ifc_|nWR_out~0 ( -// Equation(s): -// \z80_|memory_ifc_|nWR_out~0_combout = (\z80_|memory_ifc_|mwr_wr~q ) # ((\z80_|execute_|fIOWrite~5_combout & \z80_|memory_ifc_|iorq~0_combout )) - - .dataa(\z80_|execute_|fIOWrite~5_combout ), - .datab(\z80_|memory_ifc_|iorq~0_combout ), - .datac(\z80_|memory_ifc_|mwr_wr~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|memory_ifc_|nWR_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|nWR_out~0 .lut_mask = 16'hF8F8; -defparam \z80_|memory_ifc_|nWR_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N4 -cycloneive_lcell_comb \D[5]~84 ( -// Equation(s): -// \D[5]~84_combout = (!\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|memory_ifc_|nRD_out~2_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|memory_ifc_|nIORQ_out~0_combout ))) - - .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), - .datab(\z80_|memory_ifc_|nRD_out~2_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|memory_ifc_|nIORQ_out~0_combout ), - .cin(gnd), - .combout(\D[5]~84_combout ), - .cout()); -// synopsys translate_off -defparam \D[5]~84 .lut_mask = 16'h0040; -defparam \D[5]~84 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y5_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a23 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[7]~102_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_first_bit_number = 7; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y4_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a7 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[7]~102_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081; -// synopsys translate_on - -// Location: M9K_X33_Y7_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a15 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[7]~102_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N14 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]) # -// ((\ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & -// (\ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6 .lut_mask = 16'hBA98; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y4_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a31 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[7]~102_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a31_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_first_bit_number = 7; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N4 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6_combout & -// ((\ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout )))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6_combout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout ), - .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6_combout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7 .lut_mask = 16'hF858; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y24_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a15 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(gnd), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[7]~102_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_first_bit_number = 7; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y30_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a15 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h3C0000000000000000000000000000000000000000000000000000000000000080000000000002000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFB91060128E2D09899B4D10A148392808351AD282E76190E029FDC286449331D89080802222C0D04D1121484041D21084C223B0A12EBE72083D81421B93CA9589A04864A853089602E536320C2A5944831907110C246020089C76EE701A4E23964C6586008731635460418000008202040C300110000FCE7E12403749F8C6AB8F69167210EF8A4B8228710884C5C47A9986E8840C02862C088C36E19CF1D315; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h03020CCE064769B15020A6030880234C64E9BEF8E98A81489083A026140D648906E5AD6C882882990A40D293FED064710CB226CDA0330D7B189B344442EC35E3763C75FA1DB107B865E5B8F7B95E77F222244C6BDC1879C0562EF779BE0009465775469089F04C623E19317B486F653C1C22CA642CD685C10EE47EDD66C8C226C7C57F084106FB3B8B1E47463C0088D11104F23C180222A0AA22A22882A202A00000000288964258156302504F5F660C054DEDCA20CC201A4074192601E376C9596CD8B4B568A4DFEF3DBF8027A3422A56A2C003E514582104BF8D6B5D80BB397FBBEC46E8B3CAEBE0100275A1092081D0C1E5716DF09CFEEC00AD800529E1A8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h873CB568FC3F09080F4400DAC600092017210911A6081DCC4979244124815884AE6302C4BE6BA8C22A084803225A0855ABBBC528B1CA2456A4951A53C1209153CFC3000F43632B49C39723270C604B184D1940F1B2A04459BEB088666843BB38C23A8D170CED981891256A2C1D9B31C0F040202103900E6765976089DB8DE16E0001022EC10015E263787F7E581EF83F062200C626EC4E19021840D9C112400C4B987A78AE1BF80005EF370C0739371E0D3E5CF1E3677332370BB98D1831B30F7D8CDC0131C444798F040DC0116E2C4336B0166109A15D1FCC7EDE31EB23862203C11245EE31E38E6DEF2188BE2068F3C716E10317783020D8EF5C256774BA0E; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h1B9CE2DA363196DC20007FF5554FC631286DC716B048384C26510685218DF9E6C629E6050C619658692170C1022C2232C965C92C189020C705873084858910322166D72DC524870C422BBFFD4808A7032B088DE3000B853800736C8E9968C19A4B72C08871D2413188E4829219C38C2025920480D64856902E4D4D60B640C833C14D536A45D144B244C24A290076E58CC2E64E4A2DC4C5939C4C2DDBD1B918B231248625B2C0DD0F07A27A111CB80A48808C7C21C205029100010400228BB3BDFF7DCCEF40196C8381658D8840043B119B86A46247665810E2203000141023C366CB633B3376DC625DA8A0856C484392B779E1BA4088EDB4A6CDB9BD46DCC0B2; -// synopsys translate_on - -// Location: M9K_X22_Y2_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a7 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h7C762E21DB2481CB6BB88C68811C76C63B18ECC1BACDC6110DCC70BC20940800C71478E35468600B01A93082C63DD073AE4181844449C08D8D56B0DCC881251C202139803D3000B2E0209DB9101160989A5916381001B0446631006064DB1B996E436E644CF6C8606F124DA230E9B66E2F46BB466E2CE068661B4B05F02F7D00CB3E518948104042F84F1840401018406877D800A00000F5122597005DA4411000800020249004081008924124080114000000020BFFFFEC638C31207B6C321407D901787004001C459326210CCE00C6AF707B84440C313110B8C4D13B2C6E06C4C088B1A9B24BEB0178C4D6C18230DF72B07A28063647CC4721026D8C711864; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h881B30810845E6D18622EC9B6236A000030986A4F0644601226000A2F220D40310438334E51C28000400B18422CA60FC42C9C03F066366ECBBB010B00B004807CC0E00DAEC3000194A52B80C606262092D84A1102410000001400010002000800200080020000800200008000800400040002004000040002000020002000801000010004002001000200008000AEE708008880C86112251B45B36C0048833B319B4C2CE6660D2C0619246C4B208BC0AD00202001E104FC30911410804201E92102B400E8004C40AD6E4614466308ABC7165AA57060A3A736A188ABB300200A10BB04344008422327B1393C43396A931B8C8C87227A6141C0E2DCC76D830B082; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h101CC0024A6C32005CCB31908842211604D8B326101118B54B188CB4D502F5F02DA65C2472B824F109BC594C2401209C01A0E59830002C73B396C6015B85A163184B56183004204267600220A061A004893E1D609106BDBB553920A011AA5AE581E08228382D54C2989BC59535528176240438C9AA757917F95C7428981A26470D1C3E528444D9B00E561C40973AE1806031C464834F03D34A11233A34B34A1D1A55A50C3384B549B64C381920140D4008004020B119D5834C10064000006001169808000200040100000002F8986E37654DDFF88E20860382DC089D4C239F6E4C3C8D784218667F524CE209881213DC91099C14744901620044C802DA414966; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h84724A241226DB4809C9A1100DE6A63984D651A2624A09420496DDC12CC10964B6E370363701B41848117683379C8422106D001BB41FB8248067301E1002C636A276585D5273AC87206840415DA74B4E9D213CAE3234B308E19608AA38250844883838649E1442A0D983F4A9094A5AD4A52D56C5D80CAC58D9645944A230091549F30426B100842A12B25160D6D991E6C8C81AFB4C644004C2140A342020D84C9001624489A10045D16C944B02763FF55405E400BADFE5BFFFFFF00000000011042250089108884888410924041204444209102084241104204108824114455292225124929249248894408541300A6DB00791E5B12FEF24037181F1901B007B; -// synopsys translate_on - -// Location: M9K_X33_Y26_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a7 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[7]~102_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_first_bit_number = 7; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h000000000000000000000000FFFFFFFFC0810207C0001A176020155177486D89000000000000000000000000FFFFFFFF80000003C0000217724019F17748EDC900000000000000000000000000000001BF7EFDF9400406B17A400BF57748AD81000000000000000000000000000000013F7EFDF940041EB1724218157749A7910000000000000000000000003F7EFDF90000000140042AF97B426C157DC9B7590000000000000000000000003F7EFDF90000000140042069600246057DC95351000000000000000000000000408102053FFFFFF95FE4084175C246896009F35100000000000000000000000040810207BFFFFFFF7FE4147177C2004960291759; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h7FE8374958F827C15FF88F91E9A80DC3629A9FC172033EC170FB0E8173F792815FE826E158F805C95FF8AF8169A80DC3629A1EC17B033BC1706B3E8173FFB0C1400826E558F805C15DF8AF9169A82DD163C21BC17B133BC1716B3781723F14C1400826E958D825815DD8AF8168482DC161229BC17A133FC171AB3781723F16E9400826E95818058179582F9160480FC162229FC17ACA39C172FB3F8152CF10A1400826E958180D8179580F05614C0DC162329BC171EB398173537F8152E310D1400826E158180D81F8580FD1612C0F41631293C173BB398D63037F81D22313D1400827E958080F01F8188FCB60A40F41435083C1723B198161834F01D67300E3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'hD4FB0D2352268F0151E680016803440977EDE98148F31101BFFFFFFF4081010750FB094B52728F0151FEC0016C034C0153EDA90148F31F013FFFFFFB4081010152F3096156DA8901503ED2016C03480173FDA00148F11F01000000013F7EFEF952E3017156DA85015022C2016C034C0153FCA00148F10F01000000013F7EFEF956B3A9115052850543C2C2116C014D2153FDA12148D11F013F7EFEF900000001469F8B3150728D0143C05A016D014C81537DA00148D11E01BF7EFEF900000001528F8F2156628D0140004E016F054481513DA181C8513E0580000007FFFFFFFF528E8B2156E28C0148024E0167676C415139B041C8513E07C0810107FFFFFFFF; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N18 -cycloneive_lcell_comb \Mux0~0 ( -// Equation(s): -// \Mux0~0_combout = (\z80_|address_pins_|abus[14]~23_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout )))) # (!\z80_|address_pins_|abus[14]~23_combout & -// (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ))) - - .dataa(\z80_|address_pins_|abus[14]~23_combout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout ), - .cin(gnd), - .combout(\Mux0~0_combout ), - .cout()); -// synopsys translate_off -defparam \Mux0~0 .lut_mask = 16'hBA98; -defparam \Mux0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N12 -cycloneive_lcell_comb \Mux0~1 ( -// Equation(s): -// \Mux0~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Mux0~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout )) # (!\Mux0~0_combout & -// ((\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Mux0~0_combout )))) - - .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ), - .datad(\Mux0~0_combout ), - .cin(gnd), - .combout(\Mux0~1_combout ), - .cout()); -// synopsys translate_off -defparam \Mux0~1 .lut_mask = 16'hBBC0; -defparam \Mux0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N22 -cycloneive_lcell_comb \D[7]~112 ( -// Equation(s): -// \D[7]~112_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\Mux0~1_combout ))) -// # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout )))) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout ), - .datad(\Mux0~1_combout ), - .cin(gnd), - .combout(\D[7]~112_combout ), - .cout()); -// synopsys translate_off -defparam \D[7]~112 .lut_mask = 16'hF4B0; -defparam \D[7]~112 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N30 -cycloneive_lcell_comb \D[7]~94 ( -// Equation(s): -// \D[7]~94_combout = (\D[5]~84_combout & (\D[7]~112_combout & ((\z80_|data_pins_|dout [7]) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) # (!\D[5]~84_combout & ((\z80_|data_pins_|dout [7]) # ((!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) - - .dataa(\D[5]~84_combout ), - .datab(\z80_|data_pins_|dout [7]), - .datac(\D[7]~112_combout ), - .datad(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .cin(gnd), - .combout(\D[7]~94_combout ), - .cout()); -// synopsys translate_off -defparam \D[7]~94 .lut_mask = 16'hC4F5; -defparam \D[7]~94 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N26 -cycloneive_lcell_comb \D[7]~102 ( -// Equation(s): -// \D[7]~102_combout = (\D[7]~94_combout ) # (!\D[0]~107_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\D[7]~94_combout ), - .datad(\D[0]~107_combout ), - .cin(gnd), - .combout(\D[7]~102_combout ), - .cout()); -// synopsys translate_off -defparam \D[7]~102 .lut_mask = 16'hF0FF; -defparam \D[7]~102 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N26 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [7] = (\D[7]~102_combout & ((\z80_|pin_control_|bus_db_pin_re~combout ) # ((\z80_|bus_control_|db[7]~7_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\D[7]~102_combout & (\z80_|bus_control_|db[7]~7_combout -// & ((\z80_|execute_|ctl_bus_db_we~7_combout )))) - - .dataa(\D[7]~102_combout ), - .datab(\z80_|bus_control_|db[7]~7_combout ), - .datac(\z80_|pin_control_|bus_db_pin_re~combout ), - .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [7]), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] .lut_mask = 16'hECA0; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y13_N27 -dffeas \z80_|data_pins_|dout[7] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [7]), - .asdata(vcc), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), - .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|data_pins_|dout [7]), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [3]), .prn(vcc)); // synopsys translate_off -defparam \z80_|data_pins_|dout[7] .is_wysiwyg = "true"; -defparam \z80_|data_pins_|dout[7] .power_up = "low"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y13_N2 -cycloneive_lcell_comb \z80_|bus_control_|db[7]~5 ( -// Equation(s): -// \z80_|bus_control_|db[7]~5_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[7]~18_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) - - .dataa(gnd), - .datab(\z80_|alu_control_|db[7]~18_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|bus_control_|db[0]~4_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[7]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[7]~5 .lut_mask = 16'hCF00; -defparam \z80_|bus_control_|db[7]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N8 -cycloneive_lcell_comb \z80_|bus_control_|db[7]~7 ( -// Equation(s): -// \z80_|bus_control_|db[7]~7_combout = ((\z80_|bus_control_|db[7]~5_combout & ((\z80_|data_pins_|dout [7]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - - .dataa(\z80_|data_pins_|dout [7]), - .datab(\z80_|execute_|ctl_bus_db_oe~combout ), - .datac(\z80_|bus_control_|db[0]~6_combout ), - .datad(\z80_|bus_control_|db[7]~5_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[7]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[7]~7 .lut_mask = 16'hBF0F; -defparam \z80_|bus_control_|db[7]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y13_N21 -dffeas \z80_|ir_|opcode[7] ( +// Location: FF_X30_Y12_N29 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), - .asdata(\z80_|bus_control_|db[7]~7_combout ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(vcc), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|ir_|opcode [7]), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]), .prn(vcc)); // synopsys translate_off -defparam \z80_|ir_|opcode[7] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[7] .power_up = "low"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y13_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal77~0 ( +// Location: LCCOMB_X30_Y12_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~44 ( // Equation(s): -// \z80_|pla_decode_|Equal77~0_combout = (!\z80_|ir_|opcode [7] & (!\z80_|decode_state_|DFFE_instCB~q & (\z80_|ir_|opcode [6] & !\z80_|decode_state_|DFFE_instED~q ))) +// \z80_|reg_file_|gdfx_temp0[3]~44_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [3] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [3] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|decode_state_|DFFE_instCB~q ), - .datac(\z80_|ir_|opcode [6]), - .datad(\z80_|decode_state_|DFFE_instED~q ), + .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [3]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), .cin(gnd), - .combout(\z80_|pla_decode_|Equal77~0_combout ), + .combout(\z80_|reg_file_|gdfx_temp0[3]~44_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal77~0 .lut_mask = 16'h0010; -defparam \z80_|pla_decode_|Equal77~0 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|gdfx_temp0[3]~44 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp0[3]~44 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~5 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~5_combout = (\z80_|pla_decode_|Equal77~0_combout & (!\z80_|decode_state_|in_halt~q & (!\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal33~1_combout ))) +// Location: FF_X31_Y11_N21 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[3] .power_up = "low"; +// synopsys translate_on - .dataa(\z80_|pla_decode_|Equal77~0_combout ), - .datab(\z80_|decode_state_|in_halt~q ), - .datac(\z80_|decode_state_|use_ixiy~combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), +// Location: FF_X31_Y11_N11 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~43 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~43_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [3]), + .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [3]), .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~5_combout ), + .combout(\z80_|reg_file_|gdfx_temp0[3]~43_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~5 .lut_mask = 16'h0200; -defparam \z80_|execute_|ctl_mWrite~5 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|gdfx_temp0[3]~43 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[3]~43 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout = (\z80_|pla_decode_|Equal13~0_combout & (\z80_|execute_|ctl_ir_we~4_combout & (\z80_|pla_decode_|Equal8~0_combout & !\z80_|ir_|opcode [3]))) +// Location: FF_X32_Y13_N7 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3] .power_up = "low"; +// synopsys translate_on - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|pla_decode_|Equal8~0_combout ), - .datad(\z80_|ir_|opcode [3]), +// Location: FF_X32_Y14_N13 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~46 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~46_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [3] & ((\z80_|alu_control_|db[3]~35_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (((\z80_|alu_control_|db[3]~35_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [3]), + .datad(\z80_|alu_control_|db[3]~35_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ), + .combout(\z80_|reg_file_|gdfx_temp0[3]~46_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|gdfx_temp0[3]~46 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[3]~46 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y16_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~3 ( +// Location: LCCOMB_X32_Y13_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~47 ( // Equation(s): -// \z80_|execute_|ctl_bus_db_we~3_combout = (\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # (\z80_|execute_|ctl_iorw~11_combout )))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|ctl_mWrite~5_combout ), - .datac(\z80_|execute_|ctl_iorw~11_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~3 .lut_mask = 16'hFFA8; -defparam \z80_|execute_|ctl_bus_db_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_we~8_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|M5~q & ((\z80_|execute_|ctl_mRead~10_combout ) # (\z80_|pla_decode_|Equal9~1_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~8 .lut_mask = 16'h3020; -defparam \z80_|execute_|ctl_bus_db_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_we~2_combout = (\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_mRead~10_combout ) # ((\z80_|pla_decode_|Equal13~2_combout ) # (\z80_|execute_|ctl_mWrite~5_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|ctl_mWrite~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~2 .lut_mask = 16'hCCC8; -defparam \z80_|execute_|ctl_bus_db_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_we~4_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mWrite~4_combout ) # ((\z80_|pla_decode_|Equal21~0_combout & \z80_|pla_decode_|Equal24~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal21~0_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|pla_decode_|Equal24~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~4 .lut_mask = 16'hC8C0; -defparam \z80_|execute_|ctl_bus_db_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_we~6_combout = (((\z80_|execute_|ctl_bus_db_we~4_combout ) # (!\z80_|execute_|ctl_sw_2u~3_combout )) # (!\z80_|execute_|ctl_bus_db_we~5_combout )) # (!\z80_|execute_|ctl_apin_mux~0_combout ) - - .dataa(\z80_|execute_|ctl_apin_mux~0_combout ), - .datab(\z80_|execute_|ctl_bus_db_we~5_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~4_combout ), - .datad(\z80_|execute_|ctl_sw_2u~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~6 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|ctl_bus_db_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_we~7_combout = (\z80_|execute_|ctl_bus_db_we~3_combout ) # ((\z80_|execute_|ctl_bus_db_we~8_combout ) # ((\z80_|execute_|ctl_bus_db_we~2_combout ) # (\z80_|execute_|ctl_bus_db_we~6_combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_we~3_combout ), - .datab(\z80_|execute_|ctl_bus_db_we~8_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~2_combout ), - .datad(\z80_|execute_|ctl_bus_db_we~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~7 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_bus_db_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][2]~50 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][2]~50_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [4]) +// \z80_|reg_file_|gdfx_temp0[3]~47_combout = (\z80_|reg_file_|gdfx_temp0[3]~46_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) .dataa(gnd), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [3]), + .datad(\z80_|reg_file_|gdfx_temp0[3]~46_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][2]~50_combout ), + .combout(\z80_|reg_file_|gdfx_temp0[3]~47_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][2]~50 .lut_mask = 16'h000F; -defparam \ula_|zx_keyboard_|keys[0][2]~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][2]~52 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][2]~52_combout = (\ula_|zx_keyboard_|keys[7][4]~51_combout & ((\ula_|zx_keyboard_|keys[0][2]~50_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[0][2]~50_combout & ((\ula_|zx_keyboard_|keys[0][2]~q -// ))))) # (!\ula_|zx_keyboard_|keys[7][4]~51_combout & (((\ula_|zx_keyboard_|keys[0][2]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[7][4]~51_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[0][2]~q ), - .datad(\ula_|zx_keyboard_|keys[0][2]~50_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][2]~52_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][2]~52 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[0][2]~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y20_N17 -dffeas \ula_|zx_keyboard_|keys[0][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[0][2]~52_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[0][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[0][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][3]~48 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][3]~48_combout = (\ula_|zx_keyboard_|keys[7][4]~19_combout & (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|zx_keyboard_|keys[7][4]~19_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][3]~48_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][3]~48 .lut_mask = 16'h0008; -defparam \ula_|zx_keyboard_|keys[3][3]~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][2]~49 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][2]~49_combout = (\ula_|zx_keyboard_|keys[3][3]~48_combout & ((\ula_|zx_keyboard_|keys[6][4]~47_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[6][4]~47_combout & (\ula_|zx_keyboard_|keys[1][2]~q -// )))) # (!\ula_|zx_keyboard_|keys[3][3]~48_combout & (((\ula_|zx_keyboard_|keys[1][2]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[3][3]~48_combout ), - .datab(\ula_|zx_keyboard_|keys[6][4]~47_combout ), - .datac(\ula_|zx_keyboard_|keys[1][2]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][2]~49_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][2]~49 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[1][2]~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y20_N23 -dffeas \ula_|zx_keyboard_|keys[1][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[1][2]~49_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[1][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[1][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N22 -cycloneive_lcell_comb \D[2]~35 ( -// Equation(s): -// \D[2]~35_combout = (\z80_|address_pins_|abus[8]~18_combout & (((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][2]~q )))) # (!\z80_|address_pins_|abus[8]~18_combout & (!\ula_|zx_keyboard_|keys[0][2]~q & -// ((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][2]~q )))) - - .dataa(\z80_|address_pins_|abus[8]~18_combout ), - .datab(\ula_|zx_keyboard_|keys[0][2]~q ), - .datac(\ula_|zx_keyboard_|keys[1][2]~q ), - .datad(\z80_|address_pins_|abus[9]~17_combout ), - .cin(gnd), - .combout(\D[2]~35_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~35 .lut_mask = 16'hBB0B; -defparam \D[2]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~57 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][2]~57_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [0]) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][2]~57_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][2]~57 .lut_mask = 16'h3300; -defparam \ula_|zx_keyboard_|keys[5][2]~57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~58 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][2]~58_combout = (\ula_|zx_keyboard_|keys[5][2]~57_combout & ((\ula_|zx_keyboard_|keys[5][2]~33_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[5][2]~33_combout & (\ula_|zx_keyboard_|keys[5][2]~q -// )))) # (!\ula_|zx_keyboard_|keys[5][2]~57_combout & (((\ula_|zx_keyboard_|keys[5][2]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[5][2]~57_combout ), - .datab(\ula_|zx_keyboard_|keys[5][2]~33_combout ), - .datac(\ula_|zx_keyboard_|keys[5][2]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][2]~58_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][2]~58 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[5][2]~58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y18_N15 -dffeas \ula_|zx_keyboard_|keys[5][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[5][2]~58_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[5][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[5][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~59 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][2]~59_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|zx_keyboard_|extended~q ))) # (!\ula_|ps2_keyboard_|shiftreg [1] & -// (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|zx_keyboard_|extended~q ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|zx_keyboard_|extended~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][2]~59_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][2]~59 .lut_mask = 16'h0420; -defparam \ula_|zx_keyboard_|keys[4][2]~59 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~131 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][2]~131_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|keys[4][2]~59_combout & (\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [0]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|zx_keyboard_|keys[4][2]~59_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][2]~131_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][2]~131 .lut_mask = 16'h0080; -defparam \ula_|zx_keyboard_|keys[4][2]~131 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~60 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][2]~60_combout = (\ula_|zx_keyboard_|keys[4][2]~131_combout & ((\ula_|zx_keyboard_|keys[3][4]~130_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][4]~130_combout & ((\ula_|zx_keyboard_|keys[4][2]~q -// ))))) # (!\ula_|zx_keyboard_|keys[4][2]~131_combout & (((\ula_|zx_keyboard_|keys[4][2]~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[4][2]~131_combout ), - .datac(\ula_|zx_keyboard_|keys[4][2]~q ), - .datad(\ula_|zx_keyboard_|keys[3][4]~130_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][2]~60_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][2]~60 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[4][2]~60 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y18_N15 -dffeas \ula_|zx_keyboard_|keys[4][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[4][2]~60_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[4][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[4][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N4 -cycloneive_lcell_comb \D[2]~37 ( -// Equation(s): -// \D[2]~37_combout = (\z80_|address_pins_|abus[13]~20_combout & (((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][2]~q )))) # (!\z80_|address_pins_|abus[13]~20_combout & (!\ula_|zx_keyboard_|keys[5][2]~q & -// ((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][2]~q )))) - - .dataa(\z80_|address_pins_|abus[13]~20_combout ), - .datab(\ula_|zx_keyboard_|keys[5][2]~q ), - .datac(\ula_|zx_keyboard_|keys[4][2]~q ), - .datad(\z80_|address_pins_|abus[12]~21_combout ), - .cin(gnd), - .combout(\D[2]~37_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~37 .lut_mask = 16'hBB0B; -defparam \D[2]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][2]~53 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][2]~53_combout = (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [4]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][2]~53_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][2]~53 .lut_mask = 16'h00F0; -defparam \ula_|zx_keyboard_|keys[3][2]~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][2]~55 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][2]~55_combout = (\ula_|zx_keyboard_|keys[7][4]~19_combout & (\ula_|zx_keyboard_|keys[3][2]~53_combout & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|zx_keyboard_|Equal0~2_combout ))) - - .dataa(\ula_|zx_keyboard_|keys[7][4]~19_combout ), - .datab(\ula_|zx_keyboard_|keys[3][2]~53_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|zx_keyboard_|Equal0~2_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][2]~55_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][2]~55 .lut_mask = 16'h0800; -defparam \ula_|zx_keyboard_|keys[2][2]~55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][2]~56 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][2]~56_combout = (\ula_|zx_keyboard_|keys[2][2]~55_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[2][2]~55_combout & ((\ula_|zx_keyboard_|keys[2][2]~q ))) - - .dataa(gnd), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[2][2]~q ), - .datad(\ula_|zx_keyboard_|keys[2][2]~55_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][2]~56_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][2]~56 .lut_mask = 16'h33F0; -defparam \ula_|zx_keyboard_|keys[2][2]~56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y20_N27 -dffeas \ula_|zx_keyboard_|keys[2][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[2][2]~56_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[2][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[2][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][2]~54 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][2]~54_combout = (\ula_|zx_keyboard_|keys[7][4]~51_combout & ((\ula_|zx_keyboard_|keys[3][2]~53_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][2]~53_combout & ((\ula_|zx_keyboard_|keys[3][2]~q -// ))))) # (!\ula_|zx_keyboard_|keys[7][4]~51_combout & (((\ula_|zx_keyboard_|keys[3][2]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[7][4]~51_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[3][2]~q ), - .datad(\ula_|zx_keyboard_|keys[3][2]~53_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][2]~54_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][2]~54 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[3][2]~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y20_N29 -dffeas \ula_|zx_keyboard_|keys[3][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[3][2]~54_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[3][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[3][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N8 -cycloneive_lcell_comb \D[2]~36 ( -// Equation(s): -// \D[2]~36_combout = (\ula_|zx_keyboard_|keys[2][2]~q & (\z80_|address_pins_|abus[10]~24_combout & ((\z80_|address_pins_|abus[11]~19_combout ) # (!\ula_|zx_keyboard_|keys[3][2]~q )))) # (!\ula_|zx_keyboard_|keys[2][2]~q & -// (((\z80_|address_pins_|abus[11]~19_combout )) # (!\ula_|zx_keyboard_|keys[3][2]~q ))) - - .dataa(\ula_|zx_keyboard_|keys[2][2]~q ), - .datab(\ula_|zx_keyboard_|keys[3][2]~q ), - .datac(\z80_|address_pins_|abus[10]~24_combout ), - .datad(\z80_|address_pins_|abus[11]~19_combout ), - .cin(gnd), - .combout(\D[2]~36_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~36 .lut_mask = 16'hF531; -defparam \D[2]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~68 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][2]~68_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [1]))) # (!\ula_|ps2_keyboard_|shiftreg [4] & -// (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [1]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][2]~68_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][2]~68 .lut_mask = 16'h0180; -defparam \ula_|zx_keyboard_|keys[6][2]~68 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~69 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][2]~69_combout = (\ula_|zx_keyboard_|keys[6][1]~41_combout & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|zx_keyboard_|keys[6][2]~68_combout )) - - .dataa(\ula_|zx_keyboard_|keys[6][1]~41_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(gnd), - .datad(\ula_|zx_keyboard_|keys[6][2]~68_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][2]~69_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][2]~69 .lut_mask = 16'h2200; -defparam \ula_|zx_keyboard_|keys[6][2]~69 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~70 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][2]~70_combout = (\ula_|zx_keyboard_|keys[6][2]~69_combout & (!\ula_|zx_keyboard_|keys[5][0]~67_combout )) # (!\ula_|zx_keyboard_|keys[6][2]~69_combout & ((\ula_|zx_keyboard_|keys[6][2]~q ))) - - .dataa(\ula_|zx_keyboard_|keys[5][0]~67_combout ), - .datab(\ula_|zx_keyboard_|keys[6][2]~69_combout ), - .datac(\ula_|zx_keyboard_|keys[6][2]~q ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][2]~70_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][2]~70 .lut_mask = 16'h7474; -defparam \ula_|zx_keyboard_|keys[6][2]~70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y20_N1 -dffeas \ula_|zx_keyboard_|keys[6][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[6][2]~70_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[6][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[6][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y21_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~61 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~61_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [5]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~61_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~61 .lut_mask = 16'h0F00; -defparam \ula_|zx_keyboard_|keys[7][2]~61 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y21_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~62 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~62_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|zx_keyboard_|keys[7][2]~61_combout & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [0]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|zx_keyboard_|keys[7][2]~61_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~62_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~62 .lut_mask = 16'h0080; -defparam \ula_|zx_keyboard_|keys[7][2]~62 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y21_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~64 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~64_combout = (\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[7][2]~62_combout ) # ((\ula_|zx_keyboard_|keys[5][4]~63_combout & \ula_|zx_keyboard_|keys[7][2]~32_combout )))) - - .dataa(\ula_|zx_keyboard_|keys[5][4]~63_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|zx_keyboard_|keys[7][2]~62_combout ), - .datad(\ula_|zx_keyboard_|keys[7][2]~32_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~64_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~64 .lut_mask = 16'hC8C0; -defparam \ula_|zx_keyboard_|keys[7][2]~64 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y21_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~65 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~65_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|zx_keyboard_|extended~q & (\ula_|zx_keyboard_|keys[0][0]~15_combout & \ula_|zx_keyboard_|keys[7][2]~64_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|zx_keyboard_|extended~q ), - .datac(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .datad(\ula_|zx_keyboard_|keys[7][2]~64_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~65_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~65 .lut_mask = 16'h1000; -defparam \ula_|zx_keyboard_|keys[7][2]~65 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|Selector13~0 ( -// Equation(s): -// \ula_|zx_keyboard_|Selector13~0_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & !\ula_|ps2_keyboard_|shiftreg [5])) - - .dataa(\ula_|zx_keyboard_|shifted~q ), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(gnd), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|Selector13~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|Selector13~0 .lut_mask = 16'hFF22; -defparam \ula_|zx_keyboard_|Selector13~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y21_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~66 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~66_combout = (\ula_|zx_keyboard_|keys[7][2]~65_combout & ((!\ula_|zx_keyboard_|Selector13~0_combout ))) # (!\ula_|zx_keyboard_|keys[7][2]~65_combout & (\ula_|zx_keyboard_|keys[7][2]~q )) - - .dataa(\ula_|zx_keyboard_|keys[7][2]~65_combout ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[7][2]~q ), - .datad(\ula_|zx_keyboard_|Selector13~0_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~66_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~66 .lut_mask = 16'h50FA; -defparam \ula_|zx_keyboard_|keys[7][2]~66 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y21_N13 -dffeas \ula_|zx_keyboard_|keys[7][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[7][2]~66_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[7][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[7][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y21_N0 -cycloneive_lcell_comb \D[2]~38 ( -// Equation(s): -// \D[2]~38_combout = (\z80_|address_pins_|abus[15]~22_combout & (((\z80_|address_pins_|abus[14]~23_combout )) # (!\ula_|zx_keyboard_|keys[6][2]~q ))) # (!\z80_|address_pins_|abus[15]~22_combout & (!\ula_|zx_keyboard_|keys[7][2]~q & -// ((\z80_|address_pins_|abus[14]~23_combout ) # (!\ula_|zx_keyboard_|keys[6][2]~q )))) - - .dataa(\z80_|address_pins_|abus[15]~22_combout ), - .datab(\ula_|zx_keyboard_|keys[6][2]~q ), - .datac(\z80_|address_pins_|abus[14]~23_combout ), - .datad(\ula_|zx_keyboard_|keys[7][2]~q ), - .cin(gnd), - .combout(\D[2]~38_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~38 .lut_mask = 16'hA2F3; -defparam \D[2]~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N14 -cycloneive_lcell_comb \D[2]~39 ( -// Equation(s): -// \D[2]~39_combout = (\D[2]~35_combout & (\D[2]~37_combout & (\D[2]~36_combout & \D[2]~38_combout ))) - - .dataa(\D[2]~35_combout ), - .datab(\D[2]~37_combout ), - .datac(\D[2]~36_combout ), - .datad(\D[2]~38_combout ), - .cin(gnd), - .combout(\D[2]~39_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~39 .lut_mask = 16'h8000; -defparam \D[2]~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N14 -cycloneive_lcell_comb \D[2]~104 ( -// Equation(s): -// \D[2]~104_combout = ((\z80_|address_pins_|DFFE_apin_latch [0]) # (\D[2]~39_combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [0]), - .datad(\D[2]~39_combout ), - .cin(gnd), - .combout(\D[2]~104_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~104 .lut_mask = 16'hFFF3; -defparam \D[2]~104 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y8_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a26 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[2]~46_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_first_bit_number = 2; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y12_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a10 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[2]~46_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y9_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a18 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[2]~46_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_first_bit_number = 2; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y12_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a2 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[2]~46_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N8 -cycloneive_lcell_comb \D[2]~43 ( -// Equation(s): -// \D[2]~43_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout )))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ), - .cin(gnd), - .combout(\D[2]~43_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~43 .lut_mask = 16'hB9A8; -defparam \D[2]~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N6 -cycloneive_lcell_comb \D[2]~44 ( -// Equation(s): -// \D[2]~44_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[2]~43_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout )) # (!\D[2]~43_combout & -// ((\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ))))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[2]~43_combout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ), - .datad(\D[2]~43_combout ), - .cin(gnd), - .combout(\D[2]~44_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~44 .lut_mask = 16'hBBC0; -defparam \D[2]~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y17_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a10 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h8102080042447C443C0C3C402004FC1838787840407A00707C02487E444878428008004042460424402040024A3242124220044022404208520A4A24424A125A0A1028440000524A0A4A4A204A5240460800100010540042002064547E0600001FA9BE02B828694B8A82CB8C8158226808198E9EC6B021F07A2098D5E0ECB639D2B1908129B6A2D646516192D87593189D8B2B26CD6E16234C1CC90AD9831EBD89EAD271ECC39A80507716BB49626B743DFFCF99576C3FAC889860E46618ACB79EC30EEDE42EB1E31F3976CA23243179FAA96DCD66D51535351770D410DC8531866136E6184518410368288C446EC63A4FEE425019C244097049C2B2DC8D93C4; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'hA111466C9493A2A7CA2204102414CC798BF0EEC2995A4814580BD07585585ED92E5172E82E845070000A846100500E84EA1803B8B07B99E1DC75BE6419674597B38F54EB9091AE3320201EE395AD63902282A031CE3E87CC902954AA515D5D6B6A855EC94CFEC4E0172C59A7D054F8F9F4356C312C204E40B05E2059407C8DC84683814663FB910969D1D631A952B381B7F635A33FD38D5CF15DF47D057F7FF555B555C2278100000A24804D7D98EB98602733818A12094F281287422CB40002464C92242004E0AE8518E001D124A7628010115D23C30462FC00A014A12133582A191E00538FC8A5004036A959ACB7A463D23E419EA06B744005385455A71250; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h6C60009CA281AEACDC1762945981B869F93D683EAF4AC7EE52412E85B60B91CD03AD0025F0D509F63202D877ECD8BF8005451F7BD346CF9E17B36F1850A7D80A8CF14A288EAE3BFE00FB2DB45080D4A50C58263A3B398DD51AB9CB554ECAA7B2E73D9D6D2C265859DB844C2C1952AD10241100174FE0444E6707D80A098D8585AAAC4802B74190FB007C0C0206186AFC1B3A2A46864F26118ED1D03ACB1062B7315502751655F60070E6B2C50609369611365AD1E3352327320331A51818030C7D8C4C59396600DC0C420495A0D987501490002BAD38012E20620D556A230B1796450B74E95A860FF3E434C65F1308F16F92395816B914F0CE870C1323347A4E; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h7FC8531A7A319F3EBFC1383FFCDB0E09BD288288B078B4AD220B6FA934CF6187D972662C0D31E34E63B31CFC6EB4B35A69B67D85489E62EA99899A94F6800FDBA5D31B86A0288D29CE2EAAFF86A6A9F7000082293E6BB54F06E98ECCB199973EDA00FADB1D3A630BA18050635DE7DCB13B9B86E0CE6E08DC46331A352F716E3C441A0CC068A0823F8668A00621B779DE35FEC004050469F34866AEE766743D8C00FDF3B9F8DE7B76E97F8D32F0F39E4CAC68D9BBB68EA3915F6225F932CAAFDAD6E60DC661155EC9E80F8CEE659F19CC554B2C67C33EDCDA63BAD91B7D1842A7177AF49DF118FE47ACE3344964EBCADCFBB543F7729CCB340866D1157B6CCDDB; -// synopsys translate_on - -// Location: M9K_X33_Y28_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a10 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(gnd), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[2]~46_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_first_bit_number = 2; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N12 -cycloneive_lcell_comb \D[2]~40 ( -// Equation(s): -// \D[2]~40_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))) # (!\z80_|address_pins_|abus[14]~23_combout -// & (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ))) - - .dataa(\z80_|address_pins_|abus[14]~23_combout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout ), - .cin(gnd), - .combout(\D[2]~40_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~40 .lut_mask = 16'hEA62; -defparam \D[2]~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y31_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a2 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[2]~46_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_bit_number = 2; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF00000000FFFFFFFFFFFFFFFFFFF68003FFF38003FFF9F403FFF8B003D8F87003FFF8F01BEDFC701FEBFEA01FDBFDC00FDBFDC01FC7FDC0FFC7FDE87FC7FCDC8FC7FCF89FC07071FFC0F873F3E0303FE7FFFFFFFFFFFFFFFF; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000000040078400234B1474928D1000000000000000000000000FFFFFFFF204081024004027153423DA5474928DD000000000000000000000000000000003FFFFFFF40041CB14162378547495999000000000000000000000000000000003FFFFFFF4004189141623485474959F90000000000000000000000003FFFFFFE40000001400400815B6223C15FC913DD0000000000000000000000007FFFFFFE40000001400402E9400333715FC973E5000000000000000000000000604081027FFFFFFD5FE60AE95763353540091361000000000000000000000000400000003FFFFFFC5FE60AE95763081D40011361; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h5FE0236948F816F55FE897C10C28028041DC8DE178059BC16900BB4173E47AC15FE8236148E806F55FE891054CA80E8148288DE179E597C169903AC153F13A8140080365486806D55FE891D548080A8148608FE159E493C16BB03FD152BD1AE14008037D482017D15FE881C548A00AC148E08FE159FC9AC16AA02FC15AAF18F1400083F1482007C15EE882C148E00A4148B08FE148F88D4168E436915ABB01E9400092F9480007815C2882C148E00B6149B49F614868FD41436476814AFA42A1400892FD480807C15C0883C149800FE149DC9FE14A60BD41431C3F914AEA01C1400882F1480817C11C0883C041940FE549CC9EE54860BDC143BC7D8108D2C4D0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h0B928870484885014DE84481680162815375AC0148D308813FFFFFFC400000004B9288314DC0970149FC44856C0166815375AC8140D108817FFFFFFD6040808249D0A2094F908581481C40814C016099417DA88140D10B01400000017FFFFFFE48D083394B9085814A085081440166814179900140510F01400000013FFFFFFE4A508335498001814BE0608146016E8941799041405107413FFFFFFF000000004B98812149C005814BE0628146836E814179100140510F013FFFFFFF000000004B98A1114BE801814A00668147832C814119904140401F4120408082FFFFFFFF48D881154EA801854800768147C22CC14019900100003E0000000000FFFFFFFF; -// synopsys translate_on - -// Location: M9K_X33_Y17_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a2 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h77A47C739FF6A22B8B5CDC49E748E9C739BDE6756DB4D22437E74183E12400CBF7D3C6CC8C7841AB49CC538E8A72F2E73C64D3DF3662B19C07D7D299CBEDEF3E7DA5F4A8458A9451315B681ADA9AB0D63218DFB77D3353C32837E954604B9D98144A4566F47B71715BE6CDB8BA64D536762E9224D70F9A5C374B4D1CAB8DF527027170C5DBCC2B6AD72B8E4CCC94DAA139D8BA64E3384337426E7F274CC88A373AB1F9007B8A7F2936D16274F9BF8B6BABD48FCE74047C1E738C5B303E815BA720C76D6362915156A7671331CE657011862E594E46A6D99392E2D640D766869389A4D43867379AB880C1ACE279E451CB3A9063A0B320F65E536B8EEF9CBB9C76; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h9A2921ED6AA0CC8387B267B9E7A182720833CEE061E6450C8E4A72E3C043F21A0AD007E832124E92429C091D167806C10041AF32DDE13A669990457D098CC2FE3AC884B1E69101135CD080022451F20884CCB9CD203C141402A5AD293C3BABA95ADFAF6726384795A7656B753D2369B9EB5595BAA722012DF8DCFBF15BF46D6EB755D1CBF0DCF6FD40BEEC16EAB4A6D16839C98CBE9DBB437C69FB709F8E79993B9DDFE4F823D6E124B75BCE9B29F799F926619184B6C1178389F07349210436293A130C900FBA4EA70D2BA25B343C5B026D8E8766A4E4267CDAEC99E830D2307D94E6ED80D6722F3989B91E31C63B64C363DCE71A861C14382E270FC02868C7; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h386BA04E797A3F8551DAD9D24A8D259A03ECFF5AB81B1C31DFDAE10100544F8CF1A8CCFC0C7A15BD9E7C2557CB00BF2584E16AAD13D7EDB525A85ABF90C0136DD195D748900C29DF7F381280A9738CDC3BF5BBF937D3A4D99CE2BCCD97CEF2C7F00030AFDB7F22E68CBAA4D9BE7633D3B53E90E4B124422A2A4454BACA5A8DC9352CD1DAFC910CC504334DF9E6F1F4F30161A36293CC5CCF1CA13994ED29D34A5699692496359B8E67A7E74D9A0FC504C8465638CF74A0AF9185921A7D2629893091900604017933442359491FBAB63F346F0C5EC8E3A531984B09E605A30A0627271C28420E47B8DEC74738FC3EDF9FBD40EC09FC7B4D3A1475BE433705FB5F; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h973FED2E9BEDBA474B70B121A8D60F3B4EE3F1A238FB3B730EDEEE74EC632DB4D7779D7B79D1C75DF87378E98719C1AF38B1B801C71D180CE86370AE9C2BF38CF84DBBB9878C55457324E92D3DAE91D729AC76BBAD4C6EECA74DAB5EE9A175EE34ABEB9DFAA48538A57E3E5C158947081CA41402E8E65478737F73BB629AAE2EE51D405CAF70F622DD4599602D7910DCAC8214B2A42025110593202C8B164C8DF6369572C3BB8AA1984A8D12F776E224ECEEB21F97FCD6C0CF17A044EC2BBF0571A553CCDD8ABA79BD27B7AF735ED2D34F1EF3A81A160C9ECB1B1FAE6EDEEFF99E28CC30C7C2553DED3378D655AD194B2E6C1BCBED700F6713D960F33E4C361A; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N16 -cycloneive_lcell_comb \D[2]~41 ( -// Equation(s): -// \D[2]~41_combout = (\z80_|address_pins_|abus[15]~22_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout $ (\D[2]~40_combout )))) # (!\z80_|address_pins_|abus[15]~22_combout & -// (\rom|altsyncram_component|auto_generated|ram_block1a2~portadataout & ((!\D[2]~40_combout )))) - - .dataa(\z80_|address_pins_|abus[15]~22_combout ), - .datab(\rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ), - .datad(\D[2]~40_combout ), - .cin(gnd), - .combout(\D[2]~41_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~41 .lut_mask = 16'h0AE4; -defparam \D[2]~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N30 -cycloneive_lcell_comb \D[2]~42 ( -// Equation(s): -// \D[2]~42_combout = (\D[2]~40_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout & !\D[2]~41_combout )))) # (!\D[2]~40_combout & -// (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[2]~41_combout )))) - - .dataa(\D[2]~40_combout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ), - .datad(\D[2]~41_combout ), - .cin(gnd), - .combout(\D[2]~42_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~42 .lut_mask = 16'h99A8; -defparam \D[2]~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N0 -cycloneive_lcell_comb \D[2]~105 ( -// Equation(s): -// \D[2]~105_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (\D[2]~44_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\D[2]~42_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & -// (\D[2]~44_combout )))) - - .dataa(\D[2]~44_combout ), - .datab(\z80_|address_pins_|DFFE_apin_latch [15]), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\D[2]~42_combout ), - .cin(gnd), - .combout(\D[2]~105_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~105 .lut_mask = 16'hBA8A; -defparam \D[2]~105 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N28 -cycloneive_lcell_comb \D[2]~45 ( -// Equation(s): -// \D[2]~45_combout = ((\Equal2~0_combout & (\D[2]~104_combout )) # (!\Equal2~0_combout & ((\D[2]~105_combout )))) # (!\Equal2~1_combout ) - - .dataa(\Equal2~0_combout ), - .datab(\Equal2~1_combout ), - .datac(\D[2]~104_combout ), - .datad(\D[2]~105_combout ), - .cin(gnd), - .combout(\D[2]~45_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~45 .lut_mask = 16'hF7B3; -defparam \D[2]~45 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|gdfx_temp0[3]~47 .lut_mask = 16'hF300; +defparam \z80_|reg_file_|gdfx_temp0[3]~47 .sum_lutc_input = "datac"; // synopsys translate_on // Location: LCCOMB_X31_Y12_N30 -cycloneive_lcell_comb \D[2]~46 ( +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder ( // Equation(s): -// \D[2]~46_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout & (\z80_|data_pins_|dout [2] & ((\D[2]~45_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\D[2]~45_combout ) # (!\Equal2~1_combout )))) +// \z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp0[3]~52_combout - .dataa(\z80_|data_pins_|dout [2]), - .datab(\Equal2~1_combout ), - .datac(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datad(\D[2]~45_combout ), + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), .cin(gnd), - .combout(\D[2]~46_combout ), + .combout(\z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder_combout ), .cout()); // synopsys translate_off -defparam \D[2]~46 .lut_mask = 16'hAF03; -defparam \D[2]~46 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N2 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [2] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[2]~13_combout ) # ((\z80_|pin_control_|bus_db_pin_re~combout & \D[2]~46_combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & -// (\z80_|pin_control_|bus_db_pin_re~combout & (\D[2]~46_combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(\z80_|pin_control_|bus_db_pin_re~combout ), - .datac(\D[2]~46_combout ), - .datad(\z80_|bus_control_|db[2]~13_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [2]), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] .lut_mask = 16'hEAC0; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y12_N3 -dffeas \z80_|data_pins_|dout[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [2]), +// Location: FF_X31_Y12_N31 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|data_pins_|dout [2]), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [3]), .prn(vcc)); // synopsys translate_off -defparam \z80_|data_pins_|dout[2] .is_wysiwyg = "true"; -defparam \z80_|data_pins_|dout[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N18 -cycloneive_lcell_comb \z80_|bus_control_|db[2]~12 ( -// Equation(s): -// \z80_|bus_control_|db[2]~12_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[2]~29_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) - - .dataa(gnd), - .datab(\z80_|alu_control_|db[2]~29_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|bus_control_|db[0]~4_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[2]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[2]~12 .lut_mask = 16'hCF00; -defparam \z80_|bus_control_|db[2]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N12 -cycloneive_lcell_comb \z80_|bus_control_|db[2]~13 ( -// Equation(s): -// \z80_|bus_control_|db[2]~13_combout = ((\z80_|bus_control_|db[2]~12_combout & ((\z80_|data_pins_|dout [2]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - - .dataa(\z80_|data_pins_|dout [2]), - .datab(\z80_|bus_control_|db[0]~6_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~combout ), - .datad(\z80_|bus_control_|db[2]~12_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[2]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[2]~13 .lut_mask = 16'hBF33; -defparam \z80_|bus_control_|db[2]~13 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[3] .power_up = "low"; // synopsys translate_on // Location: FF_X32_Y12_N13 -dffeas \z80_|ir_|opcode[2] ( +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[3] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|bus_control_|db[2]~13_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|ir_|opcode [2]), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [3]), .prn(vcc)); // synopsys translate_off -defparam \z80_|ir_|opcode[2] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[2] .power_up = "low"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X38_Y16_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal3~1 ( +// Location: LCCOMB_X32_Y12_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~49 ( // Equation(s): -// \z80_|pla_decode_|Equal3~1_combout = (\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [1]) +// \z80_|reg_file_|gdfx_temp0[3]~49_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [3]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_iy_lo|latch [3]), + .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~49_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~49 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[3]~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y11_N27 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N12 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp0[3]~52_combout .dataa(gnd), .datab(gnd), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal3~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal3~1 .lut_mask = 16'h00F0; -defparam \z80_|pla_decode_|Equal3~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N26 -cycloneive_lcell_comb \z80_|pla_decode_|Equal43~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal43~0_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal32~0_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal1~7_combout ))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|pla_decode_|Equal32~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal1~7_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal43~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal43~0 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal43~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N24 -cycloneive_lcell_comb \z80_|interrupts_|test1~2 ( -// Equation(s): -// \z80_|interrupts_|test1~2_combout = (!\z80_|pla_decode_|Equal43~0_combout & (!\z80_|pla_decode_|Equal3~2_combout & (!\z80_|pla_decode_|Equal79~0_combout & !\z80_|pla_decode_|Equal36~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal43~0_combout ), - .datab(\z80_|pla_decode_|Equal3~2_combout ), - .datac(\z80_|pla_decode_|Equal79~0_combout ), - .datad(\z80_|pla_decode_|Equal36~0_combout ), - .cin(gnd), - .combout(\z80_|interrupts_|test1~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|interrupts_|test1~2 .lut_mask = 16'h0001; -defparam \z80_|interrupts_|test1~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N26 -cycloneive_lcell_comb \z80_|interrupts_|test1~3 ( -// Equation(s): -// \z80_|interrupts_|test1~3_combout = (!\z80_|execute_|setM1~52_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((\z80_|interrupts_|test1~2_combout ) # (!\z80_|sequencer_|DFFE_T4_ff~q )))) - - .dataa(\z80_|execute_|setM1~52_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|interrupts_|test1~2_combout ), - .cin(gnd), - .combout(\z80_|interrupts_|test1~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|interrupts_|test1~3 .lut_mask = 16'h5545; -defparam \z80_|interrupts_|test1~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y15_N13 -dffeas \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|interrupts_|test1~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED .is_wysiwyg = "true"; -defparam \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N2 -cycloneive_lcell_comb \z80_|clk_delay_|SYNTHESIZED_WIRE_4 ( -// Equation(s): -// \z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (!\z80_|sequencer_|DFFE_M1_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|interrupts_|DFFE_inst44~q ))) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|interrupts_|DFFE_inst44~q ), - .cin(gnd), - .combout(\z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_4 .lut_mask = 16'h0100; -defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X43_Y15_N3 -dffeas \z80_|clk_delay_|SYNTHESIZED_WIRE_7 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_7 .is_wysiwyg = "true"; -defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_7 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N20 -cycloneive_lcell_comb \z80_|clk_delay_|hold_clk_iorq ( -// Equation(s): -// \z80_|clk_delay_|hold_clk_iorq~combout = (!\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q & !\z80_|clk_delay_|DFF_inst5~q ) - - .dataa(gnd), - .datab(\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ), .datac(gnd), - .datad(\z80_|clk_delay_|DFF_inst5~q ), + .datad(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), .cin(gnd), - .combout(\z80_|clk_delay_|hold_clk_iorq~combout ), + .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder_combout ), .cout()); // synopsys translate_off -defparam \z80_|clk_delay_|hold_clk_iorq .lut_mask = 16'h0033; -defparam \z80_|clk_delay_|hold_clk_iorq .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y17_N13 -dffeas \z80_|sequencer_|DFFE_T1_ff ( +// Location: FF_X32_Y11_N13 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[3] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|ena_M~combout ), + .d(\z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder_combout ), .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|sequencer_|DFFE_T1_ff~q ), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [3]), .prn(vcc)); // synopsys translate_off -defparam \z80_|sequencer_|DFFE_T1_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_T1_ff .power_up = "low"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y17_N4 -cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_13 ( +// Location: LCCOMB_X32_Y11_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~45 ( // Equation(s): -// \z80_|sequencer_|SYNTHESIZED_WIRE_13~combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|execute_|setM1~52_combout & !\z80_|execute_|nextM~14_combout )) +// \z80_|reg_file_|gdfx_temp0[3]~45_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(gnd), - .datac(\z80_|execute_|setM1~52_combout ), - .datad(\z80_|execute_|nextM~14_combout ), + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [3]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [3]), .cin(gnd), - .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ), + .combout(\z80_|reg_file_|gdfx_temp0[3]~45_combout ), .cout()); // synopsys translate_off -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_13 .lut_mask = 16'h0050; -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_13 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|gdfx_temp0[3]~45 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[3]~45 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y17_N5 -dffeas \z80_|sequencer_|DFFE_T2_ff ( +// Location: FF_X32_Y13_N17 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[3] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|sequencer_|DFFE_T2_ff~q ), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [3]), .prn(vcc)); // synopsys translate_off -defparam \z80_|sequencer_|DFFE_T2_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_T2_ff .power_up = "low"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X35_Y13_N10 -cycloneive_lcell_comb \z80_|resets_|x3 ( -// Equation(s): -// \z80_|resets_|x3~combout = (\z80_|resets_|x1~q ) # ((\z80_|sequencer_|DFFE_T2_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )) +// Location: FF_X32_Y14_N15 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[3] .power_up = "low"; +// synopsys translate_on - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(gnd), - .datac(\z80_|resets_|x1~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), +// Location: LCCOMB_X32_Y14_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~48 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~48_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (\z80_|reg_file_|b2v_latch_ix_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_ix_lo|latch [3]), + .datac(\z80_|reg_file_|b2v_latch_bc_lo|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), .cin(gnd), - .combout(\z80_|resets_|x3~combout ), + .combout(\z80_|reg_file_|gdfx_temp0[3]~48_combout ), .cout()); // synopsys translate_off -defparam \z80_|resets_|x3 .lut_mask = 16'hF0FA; -defparam \z80_|resets_|x3 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|gdfx_temp0[3]~48 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp0[3]~48 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X35_Y13_N11 -dffeas \z80_|resets_|SYNTHESIZED_WIRE_12 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|resets_|x3~combout ), - .asdata(vcc), - .clrn(\z80_|fpga_reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_12 .is_wysiwyg = "true"; -defparam \z80_|resets_|SYNTHESIZED_WIRE_12 .power_up = "low"; -// synopsys translate_on - -// Location: CLKCTRL_G7 -cycloneive_clkctrl \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl ( - .ena(vcc), - .inclk({vcc,vcc,vcc,\z80_|resets_|SYNTHESIZED_WIRE_12~q }), - .clkselect(2'b00), - .devclrn(devclrn), - .devpor(devpor), - .outclk(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk )); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl .clock_type = "global clock"; -defparam \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl .ena_register_mode = "none"; -// synopsys translate_on - -// Location: FF_X32_Y17_N21 -dffeas \z80_|sequencer_|DFFE_M1_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|DFFE_M1_ff~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|DFFE_M1_ff~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_M1_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_M1_ff .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N10 -cycloneive_lcell_comb \z80_|sequencer_|DFFE_M2_ff~0 ( +// Location: LCCOMB_X32_Y11_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~50 ( // Equation(s): -// \z80_|sequencer_|DFFE_M2_ff~0_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|execute_|nextM~14_combout & (!\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|DFFE_M2_ff~q ))))) +// \z80_|reg_file_|gdfx_temp0[3]~50_combout = (\z80_|reg_file_|gdfx_temp0[3]~47_combout & (\z80_|reg_file_|gdfx_temp0[3]~49_combout & (\z80_|reg_file_|gdfx_temp0[3]~45_combout & \z80_|reg_file_|gdfx_temp0[3]~48_combout ))) - .dataa(\z80_|execute_|setM1~52_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|execute_|nextM~14_combout ), + .dataa(\z80_|reg_file_|gdfx_temp0[3]~47_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[3]~49_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[3]~45_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[3]~48_combout ), .cin(gnd), - .combout(\z80_|sequencer_|DFFE_M2_ff~0_combout ), + .combout(\z80_|reg_file_|gdfx_temp0[3]~50_combout ), .cout()); // synopsys translate_off -defparam \z80_|sequencer_|DFFE_M2_ff~0 .lut_mask = 16'h22A0; -defparam \z80_|sequencer_|DFFE_M2_ff~0 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|gdfx_temp0[3]~50 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[3]~50 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y17_N11 -dffeas \z80_|sequencer_|DFFE_M2_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|DFFE_M2_ff~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|DFFE_M2_ff~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_M2_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_M2_ff .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~3 ( +// Location: LCCOMB_X31_Y11_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~51 ( // Equation(s): -// \z80_|execute_|ctl_mWrite~3_combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ) +// \z80_|reg_file_|gdfx_temp0[3]~51_combout = (\z80_|reg_file_|gdfx_temp0[3]~44_combout & (\z80_|reg_file_|gdfx_temp0[3]~43_combout & \z80_|reg_file_|gdfx_temp0[3]~50_combout )) + + .dataa(\z80_|reg_file_|gdfx_temp0[3]~44_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[3]~43_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[3]~50_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~51 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|gdfx_temp0[3]~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~52 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~52_combout = ((\z80_|reg_file_|gdfx_temp0[3]~51_combout & ((\z80_|reg_file_|db_lo_as[3]~12_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), + .datac(\z80_|reg_file_|db_lo_as[3]~12_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~52 .lut_mask = 16'hC4FF; +defparam \z80_|reg_file_|gdfx_temp0[3]~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N20 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_35 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout = (\z80_|execute_|ctl_flags_bus~combout & ((\z80_|alu_control_|db[3]~35_combout ) # ((\z80_|execute_|ctl_flags_alu~15_combout & \z80_|alu_|db_low[3]~25_combout )))) # (!\z80_|execute_|ctl_flags_bus~combout +// & (((\z80_|execute_|ctl_flags_alu~15_combout & \z80_|alu_|db_low[3]~25_combout )))) + + .dataa(\z80_|execute_|ctl_flags_bus~combout ), + .datab(\z80_|alu_control_|db[3]~35_combout ), + .datac(\z80_|execute_|ctl_flags_alu~15_combout ), + .datad(\z80_|alu_|db_low[3]~25_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_35 .lut_mask = 16'hF888; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~15 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~15_combout = (\z80_|execute_|ctl_state_alu~2_combout & ((\z80_|execute_|ctl_ir_we~12_combout ) # ((\z80_|execute_|ctl_alu_op_low~22_combout & \z80_|pla_decode_|Equal56~0_combout )))) # +// (!\z80_|execute_|ctl_state_alu~2_combout & (\z80_|execute_|ctl_alu_op_low~22_combout & (\z80_|pla_decode_|Equal56~0_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datac(\z80_|pla_decode_|Equal56~0_combout ), + .datad(\z80_|execute_|ctl_ir_we~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~15 .lut_mask = 16'hEAC0; +defparam \z80_|execute_|ctl_flags_xy_we~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~16 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~16_combout = (\z80_|execute_|ctl_flags_xy_we~15_combout ) # ((\z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ) # (!\z80_|execute_|ctl_flags_xy_we~12_combout )) .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|execute_|ctl_flags_xy_we~15_combout ), + .datac(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~12_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~3_combout ), + .combout(\z80_|execute_|ctl_flags_xy_we~16_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~3 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_mWrite~3 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_flags_xy_we~16 .lut_mask = 16'hFCFF; +defparam \z80_|execute_|ctl_flags_xy_we~16 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X41_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|nextM~11 ( +// Location: LCCOMB_X28_Y18_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~17 ( // Equation(s): -// \z80_|execute_|nextM~11_combout = ((!\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_alu_op_low~12_combout & !\z80_|execute_|ctl_alu_op_low~11_combout ))) # (!\z80_|execute_|ctl_mWrite~3_combout ) +// \z80_|execute_|ctl_flags_xy_we~17_combout = (\z80_|execute_|ctl_flags_xy_we~16_combout ) # (((!\z80_|execute_|ctl_flags_xy_we~19_combout ) # (!\z80_|execute_|ctl_flags_xy_we~9_combout )) # (!\z80_|execute_|ctl_flags_xy_we~11_combout )) - .dataa(\z80_|execute_|ctl_mWrite~3_combout ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~12_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~11_combout ), + .dataa(\z80_|execute_|ctl_flags_xy_we~16_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~11_combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~9_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~19_combout ), .cin(gnd), - .combout(\z80_|execute_|nextM~11_combout ), + .combout(\z80_|execute_|ctl_flags_xy_we~17_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|nextM~11 .lut_mask = 16'h5557; -defparam \z80_|execute_|nextM~11 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_flags_xy_we~17 .lut_mask = 16'hBFFF; +defparam \z80_|execute_|ctl_flags_xy_we~17 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X40_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|nextM~8 ( +// Location: LCCOMB_X28_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~18 ( // Equation(s): -// \z80_|execute_|nextM~8_combout = (\z80_|alu_control_|flags_cond_true~q & (((\z80_|execute_|ixy_d~8_combout & !\z80_|execute_|ctl_flags_bus~5_combout )))) # (!\z80_|alu_control_|flags_cond_true~q & ((\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout -// ) # ((\z80_|execute_|ixy_d~8_combout & !\z80_|execute_|ctl_flags_bus~5_combout )))) +// \z80_|execute_|ctl_flags_xy_we~18_combout = ((\z80_|execute_|ctl_flags_xy_we~17_combout ) # ((!\z80_|execute_|ctl_flags_pf_we~4_combout ) # (!\z80_|execute_|ctl_pf_sel[0]~3_combout ))) # (!\z80_|execute_|ctl_flags_sz_we~7_combout ) - .dataa(\z80_|alu_control_|flags_cond_true~q ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), - .datac(\z80_|execute_|ixy_d~8_combout ), - .datad(\z80_|execute_|ctl_flags_bus~5_combout ), + .dataa(\z80_|execute_|ctl_flags_sz_we~7_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~17_combout ), + .datac(\z80_|execute_|ctl_pf_sel[0]~3_combout ), + .datad(\z80_|execute_|ctl_flags_pf_we~4_combout ), .cin(gnd), - .combout(\z80_|execute_|nextM~8_combout ), + .combout(\z80_|execute_|ctl_flags_xy_we~18_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|nextM~8 .lut_mask = 16'h44F4; -defparam \z80_|execute_|nextM~8 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_flags_xy_we~18 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_flags_xy_we~18 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|nextM~9 ( -// Equation(s): -// \z80_|execute_|nextM~9_combout = (\z80_|execute_|ctl_mWrite~2_combout & (\z80_|pla_decode_|Equal55~0_combout & ((\z80_|execute_|ctl_mRead~11_combout ) # (\z80_|execute_|ixy_d~6_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~2_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|execute_|ctl_mRead~11_combout ), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~9 .lut_mask = 16'h8880; -defparam \z80_|execute_|nextM~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|nextM~10 ( -// Equation(s): -// \z80_|execute_|nextM~10_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ) # ((\z80_|execute_|nextM~9_combout ) # ((\z80_|execute_|ctl_mRead~36_combout & \z80_|execute_|ixy_d~9_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .datab(\z80_|execute_|nextM~9_combout ), - .datac(\z80_|execute_|ctl_mRead~36_combout ), - .datad(\z80_|execute_|ixy_d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~10 .lut_mask = 16'hFEEE; -defparam \z80_|execute_|nextM~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|nextM~12 ( -// Equation(s): -// \z80_|execute_|nextM~12_combout = ((\z80_|execute_|nextM~8_combout ) # ((\z80_|execute_|nextM~10_combout ) # (\z80_|execute_|ctl_alu_op_low~32_combout ))) # (!\z80_|execute_|nextM~11_combout ) - - .dataa(\z80_|execute_|nextM~11_combout ), - .datab(\z80_|execute_|nextM~8_combout ), - .datac(\z80_|execute_|nextM~10_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~12 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|nextM~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N22 -cycloneive_lcell_comb \z80_|execute_|nextM~15 ( -// Equation(s): -// \z80_|execute_|nextM~15_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & ((\z80_|execute_|ctl_mRead~7_combout ) # (!\z80_|execute_|fMRead~10_combout )))) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|execute_|ctl_mRead~7_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|execute_|fMRead~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~15 .lut_mask = 16'h80A0; -defparam \z80_|execute_|nextM~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N8 -cycloneive_lcell_comb \z80_|execute_|nextM~6 ( -// Equation(s): -// \z80_|execute_|nextM~6_combout = (((\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal49~0_combout )) # (!\z80_|execute_|nextM~3_combout )) # (!\z80_|execute_|ixy_d~17_combout ) - - .dataa(\z80_|execute_|ixy_d~17_combout ), - .datab(\z80_|decode_state_|use_ixiy~combout ), - .datac(\z80_|execute_|nextM~3_combout ), - .datad(\z80_|pla_decode_|Equal49~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~6 .lut_mask = 16'hDF5F; -defparam \z80_|execute_|nextM~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N6 -cycloneive_lcell_comb \z80_|execute_|nextM~7 ( -// Equation(s): -// \z80_|execute_|nextM~7_combout = ((\z80_|execute_|nextM~6_combout & ((\z80_|execute_|ixy_d~8_combout ) # (\z80_|execute_|ctl_state_alu~4_combout )))) # (!\z80_|execute_|nextM~4_combout ) - - .dataa(\z80_|execute_|ixy_d~8_combout ), - .datab(\z80_|execute_|nextM~6_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|nextM~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~7 .lut_mask = 16'hC8FF; -defparam \z80_|execute_|nextM~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N6 -cycloneive_lcell_comb \z80_|execute_|nextM~13 ( -// Equation(s): -// \z80_|execute_|nextM~13_combout = (\z80_|execute_|nextM~12_combout ) # ((\z80_|execute_|nextM~15_combout ) # (\z80_|execute_|nextM~7_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|nextM~12_combout ), - .datac(\z80_|execute_|nextM~15_combout ), - .datad(\z80_|execute_|nextM~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~13 .lut_mask = 16'hFFFC; -defparam \z80_|execute_|nextM~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N12 -cycloneive_lcell_comb \z80_|execute_|setM1~39 ( -// Equation(s): -// \z80_|execute_|setM1~39_combout = (!\z80_|execute_|ctl_mWrite~5_combout & \z80_|execute_|setM1~38_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_mWrite~5_combout ), - .datad(\z80_|execute_|setM1~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~39 .lut_mask = 16'h0F00; -defparam \z80_|execute_|setM1~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N6 -cycloneive_lcell_comb \z80_|execute_|nextM~5 ( -// Equation(s): -// \z80_|execute_|nextM~5_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (((!\z80_|execute_|setM1~45_combout ) # (!\z80_|execute_|nextM~2_combout )) # (!\z80_|execute_|setM1~39_combout ))) - - .dataa(\z80_|execute_|setM1~39_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|nextM~2_combout ), - .datad(\z80_|execute_|setM1~45_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~5 .lut_mask = 16'h4CCC; -defparam \z80_|execute_|nextM~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|nextM~14 ( -// Equation(s): -// \z80_|execute_|nextM~14_combout = (\z80_|execute_|nextM~13_combout ) # (((\z80_|execute_|nextM~5_combout ) # (!\z80_|execute_|ctl_mRead~30_combout )) # (!\z80_|execute_|ctl_mWrite~13_combout )) - - .dataa(\z80_|execute_|nextM~13_combout ), - .datab(\z80_|execute_|ctl_mWrite~13_combout ), - .datac(\z80_|execute_|ctl_mRead~30_combout ), - .datad(\z80_|execute_|nextM~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~14 .lut_mask = 16'hFFBF; -defparam \z80_|execute_|nextM~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N14 -cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_15 ( -// Equation(s): -// \z80_|sequencer_|SYNTHESIZED_WIRE_15~combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|execute_|setM1~52_combout & !\z80_|execute_|nextM~14_combout )) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|execute_|setM1~52_combout ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_15 .lut_mask = 16'h00C0; -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y17_N15 -dffeas \z80_|sequencer_|DFFE_T4_ff ( +// Location: FF_X31_Y15_N21 +dffeas \z80_|alu_flags_|flags_xf ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ), + .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ), .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .ena(\z80_|execute_|ctl_flags_xy_we~18_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|sequencer_|DFFE_T4_ff~q ), + .q(\z80_|alu_flags_|flags_xf~q ), .prn(vcc)); // synopsys translate_off -defparam \z80_|sequencer_|DFFE_T4_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_T4_ff .power_up = "low"; +defparam \z80_|alu_flags_|flags_xf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|flags_xf .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y17_N18 -cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_16 ( +// Location: LCCOMB_X31_Y15_N30 +cycloneive_lcell_comb \z80_|alu_control_|db[3]~33 ( // Equation(s): -// \z80_|sequencer_|SYNTHESIZED_WIRE_16~combout = (\z80_|execute_|setM1~52_combout & (\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|execute_|nextM~14_combout )) - - .dataa(\z80_|execute_|setM1~52_combout ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_16 .lut_mask = 16'h00A0; -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y17_N19 -dffeas \z80_|sequencer_|DFFE_T5_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|DFFE_T5_ff~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_T5_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_T5_ff .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N26 -cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_17 ( -// Equation(s): -// \z80_|sequencer_|SYNTHESIZED_WIRE_17~combout = (\z80_|sequencer_|DFFE_T5_ff~q & (\z80_|execute_|setM1~52_combout & !\z80_|execute_|nextM~14_combout )) +// \z80_|alu_control_|db[3]~33_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & ((\z80_|alu_flags_|flags_xf~q ) # (!\z80_|execute_|ctl_flags_oe~2_combout ))) .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T5_ff~q ), - .datac(\z80_|execute_|setM1~52_combout ), - .datad(\z80_|execute_|nextM~14_combout ), + .datab(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .datac(\z80_|execute_|ctl_flags_oe~2_combout ), + .datad(\z80_|alu_flags_|flags_xf~q ), .cin(gnd), - .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_17~combout ), + .combout(\z80_|alu_control_|db[3]~33_combout ), .cout()); // synopsys translate_off -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_17 .lut_mask = 16'h00C0; -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_17 .sum_lutc_input = "datac"; +defparam \z80_|alu_control_|db[3]~33 .lut_mask = 16'hCC0C; +defparam \z80_|alu_control_|db[3]~33 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y17_N27 -dffeas \z80_|sequencer_|T6 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|SYNTHESIZED_WIRE_17~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|T6~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|T6 .is_wysiwyg = "true"; -defparam \z80_|sequencer_|T6 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|setM1~13 ( +// Location: LCCOMB_X31_Y14_N20 +cycloneive_lcell_comb \z80_|sw1_|db_down[3]~2 ( // Equation(s): -// \z80_|execute_|setM1~13_combout = (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|pla_decode_|Equal33~0_combout & ((!\z80_|pla_decode_|Equal32~0_combout ) # (!\z80_|pla_decode_|Equal21~2_combout )))) # (!\z80_|pla_decode_|Equal13~0_combout & -// (((!\z80_|pla_decode_|Equal32~0_combout )) # (!\z80_|pla_decode_|Equal21~2_combout ))) +// \z80_|sw1_|db_down[3]~2_combout = (\z80_|bus_control_|db[3]~21_combout ) # ((\z80_|execute_|ctl_sw_1d~6_combout & ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|execute_|ctl_66_oe~2_combout )))) - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|pla_decode_|Equal21~2_combout ), - .datac(\z80_|pla_decode_|Equal32~0_combout ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~13 .lut_mask = 16'h153F; -defparam \z80_|execute_|setM1~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal77~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal77~1_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal21~0_combout & (\z80_|pla_decode_|Equal77~0_combout & \z80_|pla_decode_|Equal33~0_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|pla_decode_|Equal21~0_combout ), - .datac(\z80_|pla_decode_|Equal77~0_combout ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal77~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal77~1 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal77~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|setM1~12 ( -// Equation(s): -// \z80_|execute_|setM1~12_combout = (!\z80_|pla_decode_|Equal77~1_combout & (!\z80_|execute_|ctl_alu_oe~3_combout & (!\z80_|pla_decode_|Equal1~6_combout & !\z80_|pla_decode_|Equal2~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal77~1_combout ), - .datab(\z80_|execute_|ctl_alu_oe~3_combout ), - .datac(\z80_|pla_decode_|Equal1~6_combout ), - .datad(\z80_|pla_decode_|Equal2~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~12 .lut_mask = 16'h0001; -defparam \z80_|execute_|setM1~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|setM1~14 ( -// Equation(s): -// \z80_|execute_|setM1~14_combout = (\z80_|execute_|setM1~13_combout & (\z80_|interrupts_|test1~2_combout & \z80_|execute_|setM1~12_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|setM1~13_combout ), - .datac(\z80_|interrupts_|test1~2_combout ), - .datad(\z80_|execute_|setM1~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~14 .lut_mask = 16'hC000; -defparam \z80_|execute_|setM1~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|setM1~41 ( -// Equation(s): -// \z80_|execute_|setM1~41_combout = (!\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_mWrite~4_combout & !\z80_|execute_|ctl_ir_we~10_combout )) - - .dataa(\z80_|execute_|ctl_ir_we~9_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|execute_|ctl_ir_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~41 .lut_mask = 16'h0005; -defparam \z80_|execute_|setM1~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|setM1~42 ( -// Equation(s): -// \z80_|execute_|setM1~42_combout = (!\z80_|pla_decode_|Equal38~2_combout & (!\z80_|pla_decode_|Equal37~0_combout & (!\z80_|pla_decode_|Equal47~0_combout & \z80_|sequencer_|DFFE_T4_ff~q ))) - - .dataa(\z80_|pla_decode_|Equal38~2_combout ), - .datab(\z80_|pla_decode_|Equal37~0_combout ), - .datac(\z80_|pla_decode_|Equal47~0_combout ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~42 .lut_mask = 16'h0100; -defparam \z80_|execute_|setM1~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|setM1~43 ( -// Equation(s): -// \z80_|execute_|setM1~43_combout = (!\z80_|pla_decode_|Equal21~1_combout & (\z80_|execute_|setM1~41_combout & (!\z80_|pla_decode_|Equal48~0_combout & \z80_|execute_|setM1~42_combout ))) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|execute_|setM1~41_combout ), - .datac(\z80_|pla_decode_|Equal48~0_combout ), - .datad(\z80_|execute_|setM1~42_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~43 .lut_mask = 16'h0400; -defparam \z80_|execute_|setM1~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N26 -cycloneive_lcell_comb \z80_|execute_|setM1~44 ( -// Equation(s): -// \z80_|execute_|setM1~44_combout = (\z80_|execute_|setM1~43_combout & (\z80_|execute_|setM1~40_combout & ((!\z80_|pla_decode_|Equal2~1_combout ) # (!\z80_|pla_decode_|Equal1~4_combout )))) - - .dataa(\z80_|execute_|setM1~43_combout ), - .datab(\z80_|pla_decode_|Equal1~4_combout ), - .datac(\z80_|execute_|setM1~40_combout ), - .datad(\z80_|pla_decode_|Equal2~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~44 .lut_mask = 16'h20A0; -defparam \z80_|execute_|setM1~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N20 -cycloneive_lcell_comb \z80_|execute_|setM1~50 ( -// Equation(s): -// \z80_|execute_|setM1~50_combout = (\z80_|execute_|setM1~46_combout & (\z80_|execute_|setM1~14_combout & (\z80_|execute_|setM1~44_combout & \z80_|execute_|setM1~49_combout ))) - - .dataa(\z80_|execute_|setM1~46_combout ), - .datab(\z80_|execute_|setM1~14_combout ), - .datac(\z80_|execute_|setM1~44_combout ), - .datad(\z80_|execute_|setM1~49_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~50 .lut_mask = 16'h8000; -defparam \z80_|execute_|setM1~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|setM1~51 ( -// Equation(s): -// \z80_|execute_|setM1~51_combout = (\z80_|sequencer_|T6~q & (((\z80_|execute_|setM1~50_combout & \z80_|execute_|setM1~39_combout )) # (!\z80_|execute_|setM1~40_combout ))) # (!\z80_|sequencer_|T6~q & (\z80_|execute_|setM1~50_combout & -// ((\z80_|execute_|setM1~39_combout )))) - - .dataa(\z80_|sequencer_|T6~q ), - .datab(\z80_|execute_|setM1~50_combout ), - .datac(\z80_|execute_|setM1~40_combout ), - .datad(\z80_|execute_|setM1~39_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~51_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~51 .lut_mask = 16'hCE0A; -defparam \z80_|execute_|setM1~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N2 -cycloneive_lcell_comb \z80_|execute_|setM1~6 ( -// Equation(s): -// \z80_|execute_|setM1~6_combout = (\z80_|execute_|ctl_al_we~13_combout & (\z80_|sequencer_|M5~q & (\z80_|pla_decode_|Equal9~1_combout ))) # (!\z80_|execute_|ctl_al_we~13_combout & ((\z80_|sequencer_|DFFE_M4_ff~q ) # ((\z80_|sequencer_|M5~q & -// \z80_|pla_decode_|Equal9~1_combout )))) - - .dataa(\z80_|execute_|ctl_al_we~13_combout ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|sequencer_|DFFE_M4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~6 .lut_mask = 16'hD5C0; -defparam \z80_|execute_|setM1~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N12 -cycloneive_lcell_comb \z80_|execute_|setM1~7 ( -// Equation(s): -// \z80_|execute_|setM1~7_combout = ((\z80_|sequencer_|DFFE_T5_ff~q & \z80_|execute_|setM1~6_combout )) # (!\z80_|execute_|ctl_flags_xy_we~16_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_flags_xy_we~16_combout ), - .datac(\z80_|sequencer_|DFFE_T5_ff~q ), - .datad(\z80_|execute_|setM1~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~7 .lut_mask = 16'hF333; -defparam \z80_|execute_|setM1~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N0 -cycloneive_lcell_comb \z80_|execute_|setM1~8 ( -// Equation(s): -// \z80_|execute_|setM1~8_combout = (\z80_|execute_|ctl_mWrite~4_combout ) # ((\z80_|execute_|ctl_mRead~7_combout ) # ((\z80_|pla_decode_|Equal6~1_combout ) # (!\z80_|execute_|fMWrite~3_combout ))) - - .dataa(\z80_|execute_|ctl_mWrite~4_combout ), - .datab(\z80_|execute_|ctl_mRead~7_combout ), - .datac(\z80_|pla_decode_|Equal6~1_combout ), - .datad(\z80_|execute_|fMWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~8 .lut_mask = 16'hFEFF; -defparam \z80_|execute_|setM1~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N10 -cycloneive_lcell_comb \z80_|execute_|setM1~9 ( -// Equation(s): -// \z80_|execute_|setM1~9_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ) # ((!\z80_|ir_|opcode [4] & (!\z80_|ir_|opcode [2] & \z80_|execute_|ctl_mWrite~2_combout ))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [2]), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .datad(\z80_|execute_|ctl_mWrite~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~9 .lut_mask = 16'hF1F0; -defparam \z80_|execute_|setM1~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N10 -cycloneive_lcell_comb \z80_|execute_|setM1~10 ( -// Equation(s): -// \z80_|execute_|setM1~10_combout = ((\z80_|execute_|setM1~8_combout ) # ((\z80_|execute_|ctl_mWrite~16_combout & \z80_|execute_|setM1~9_combout ))) # (!\z80_|execute_|nextM~2_combout ) - - .dataa(\z80_|execute_|ctl_mWrite~16_combout ), - .datab(\z80_|execute_|nextM~2_combout ), - .datac(\z80_|execute_|setM1~8_combout ), - .datad(\z80_|execute_|setM1~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~10 .lut_mask = 16'hFBF3; -defparam \z80_|execute_|setM1~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N26 -cycloneive_lcell_comb \z80_|execute_|setM1~11 ( -// Equation(s): -// \z80_|execute_|setM1~11_combout = (\z80_|execute_|setM1~7_combout ) # (((\z80_|execute_|ixy_d~6_combout & \z80_|execute_|setM1~10_combout )) # (!\z80_|reg_control_|reg_sel_pc~3_combout )) - - .dataa(\z80_|execute_|setM1~7_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|execute_|setM1~10_combout ), - .datad(\z80_|reg_control_|reg_sel_pc~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~11 .lut_mask = 16'hEAFF; -defparam \z80_|execute_|setM1~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|setM1~17 ( -// Equation(s): -// \z80_|execute_|setM1~17_combout = ((\z80_|execute_|setM1~11_combout ) # ((!\z80_|execute_|setM1~14_combout & \z80_|execute_|ctl_eval_cond~0_combout ))) # (!\z80_|execute_|setM1~16_combout ) - - .dataa(\z80_|execute_|setM1~16_combout ), - .datab(\z80_|execute_|setM1~14_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|setM1~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~17 .lut_mask = 16'hFF75; -defparam \z80_|execute_|setM1~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N16 -cycloneive_lcell_comb \z80_|execute_|setM1~31 ( -// Equation(s): -// \z80_|execute_|setM1~31_combout = (\z80_|pla_decode_|Equal35~0_combout & ((\z80_|execute_|ixy_d~6_combout ) # ((\z80_|execute_|ctl_reg_in_hi~2_combout & \z80_|execute_|ctl_mRead~18_combout )))) # (!\z80_|pla_decode_|Equal35~0_combout & -// (\z80_|execute_|ctl_reg_in_hi~2_combout & ((\z80_|execute_|ctl_mRead~18_combout )))) - - .dataa(\z80_|pla_decode_|Equal35~0_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|execute_|ctl_mRead~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~31 .lut_mask = 16'hECA0; -defparam \z80_|execute_|setM1~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N2 -cycloneive_lcell_comb \z80_|execute_|setM1~28 ( -// Equation(s): -// \z80_|execute_|setM1~28_combout = ((\z80_|execute_|ctl_mRead~9_combout ) # ((\z80_|execute_|ctl_mRead~15_combout ) # (\z80_|execute_|ctl_mRead~7_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), - .datab(\z80_|execute_|ctl_mRead~9_combout ), - .datac(\z80_|execute_|ctl_mRead~15_combout ), - .datad(\z80_|execute_|ctl_mRead~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~28 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|setM1~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|setM1~30 ( -// Equation(s): -// \z80_|execute_|setM1~30_combout = (((\z80_|execute_|ctl_state_alu~6_combout & \z80_|execute_|setM1~28_combout )) # (!\z80_|execute_|setM1~29_combout )) # (!\z80_|execute_|setM1~54_combout ) - - .dataa(\z80_|execute_|setM1~54_combout ), - .datab(\z80_|execute_|setM1~29_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|setM1~28_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~30 .lut_mask = 16'hF777; -defparam \z80_|execute_|setM1~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N10 -cycloneive_lcell_comb \z80_|execute_|setM1~32 ( -// Equation(s): -// \z80_|execute_|setM1~32_combout = (\z80_|execute_|ctl_mRead~5_combout ) # ((\z80_|execute_|ctl_mRead~4_combout ) # ((\z80_|execute_|setM1~9_combout & \z80_|execute_|ctl_mRead~36_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~5_combout ), - .datab(\z80_|execute_|setM1~9_combout ), - .datac(\z80_|execute_|ctl_mRead~36_combout ), - .datad(\z80_|execute_|ctl_mRead~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~32 .lut_mask = 16'hFFEA; -defparam \z80_|execute_|setM1~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N8 -cycloneive_lcell_comb \z80_|execute_|setM1~33 ( -// Equation(s): -// \z80_|execute_|setM1~33_combout = (\z80_|execute_|setM1~31_combout ) # ((\z80_|execute_|setM1~30_combout ) # ((\z80_|execute_|ixy_d~9_combout & \z80_|execute_|setM1~32_combout ))) - - .dataa(\z80_|execute_|setM1~31_combout ), - .datab(\z80_|execute_|setM1~30_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|execute_|setM1~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~33 .lut_mask = 16'hFEEE; -defparam \z80_|execute_|setM1~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|setM1~25 ( -// Equation(s): -// \z80_|execute_|setM1~25_combout = ((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & \z80_|pla_decode_|Equal21~1_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), - .datad(\z80_|pla_decode_|Equal21~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~25 .lut_mask = 16'hAF0F; -defparam \z80_|execute_|setM1~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|setM1~26 ( -// Equation(s): -// \z80_|execute_|setM1~26_combout = ((\z80_|execute_|ctl_mRead~13_combout ) # ((!\z80_|alu_control_|flags_cond_true~q & \z80_|pla_decode_|Equal40~1_combout ))) # (!\z80_|execute_|ctl_bus_inc_oe~29_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~29_combout ), - .datab(\z80_|alu_control_|flags_cond_true~q ), - .datac(\z80_|execute_|ctl_mRead~13_combout ), - .datad(\z80_|pla_decode_|Equal40~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~26 .lut_mask = 16'hF7F5; -defparam \z80_|execute_|setM1~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|setM1~24 ( -// Equation(s): -// \z80_|execute_|setM1~24_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & (((\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & !\z80_|alu_control_|flags_cond_true~q )) # (!\z80_|execute_|ctl_mRead~12_combout ))) # -// (!\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & (\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & ((!\z80_|alu_control_|flags_cond_true~q )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), - .datac(\z80_|execute_|ctl_mRead~12_combout ), - .datad(\z80_|alu_control_|flags_cond_true~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~24 .lut_mask = 16'h0ACE; -defparam \z80_|execute_|setM1~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N18 -cycloneive_lcell_comb \z80_|execute_|setM1~27 ( -// Equation(s): -// \z80_|execute_|setM1~27_combout = (\z80_|execute_|setM1~24_combout ) # ((\z80_|execute_|ctl_state_alu~4_combout & ((\z80_|execute_|setM1~25_combout ) # (\z80_|execute_|setM1~26_combout )))) - - .dataa(\z80_|execute_|setM1~25_combout ), - .datab(\z80_|execute_|setM1~26_combout ), - .datac(\z80_|execute_|setM1~24_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~27 .lut_mask = 16'hFEF0; -defparam \z80_|execute_|setM1~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N6 -cycloneive_lcell_comb \z80_|execute_|setM1~22 ( -// Equation(s): -// \z80_|execute_|setM1~22_combout = (!\z80_|execute_|ctl_mRead~10_combout & (\z80_|execute_|fMWrite~9_combout & (!\z80_|execute_|ctl_mRead~8_combout & \z80_|execute_|fMWrite~3_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|execute_|fMWrite~9_combout ), - .datac(\z80_|execute_|ctl_mRead~8_combout ), - .datad(\z80_|execute_|fMWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~22 .lut_mask = 16'h0400; -defparam \z80_|execute_|setM1~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N26 -cycloneive_lcell_comb \z80_|execute_|setM1~21 ( -// Equation(s): -// \z80_|execute_|setM1~21_combout = (\z80_|decode_state_|DFFE_instNonRep~q ) # ((!\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [4] & \z80_|execute_|ctl_mWrite~2_combout ))) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|decode_state_|DFFE_instNonRep~q ), - .datad(\z80_|execute_|ctl_mWrite~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~21 .lut_mask = 16'hF1F0; -defparam \z80_|execute_|setM1~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N2 -cycloneive_lcell_comb \z80_|execute_|setM1~53 ( -// Equation(s): -// \z80_|execute_|setM1~53_combout = (\z80_|sequencer_|DFFE_T5_ff~q & ((\z80_|sequencer_|DFFE_M4_ff~q ) # ((\z80_|execute_|setM1~21_combout & \z80_|sequencer_|DFFE_M3_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|sequencer_|DFFE_T5_ff~q ), - .datac(\z80_|execute_|setM1~21_combout ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~53_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~53 .lut_mask = 16'hC888; -defparam \z80_|execute_|setM1~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N4 -cycloneive_lcell_comb \z80_|execute_|setM1~23 ( -// Equation(s): -// \z80_|execute_|setM1~23_combout = (\z80_|execute_|setM1~22_combout & (((!\z80_|execute_|ctl_flags_bus~5_combout & \z80_|execute_|setM1~53_combout )))) # (!\z80_|execute_|setM1~22_combout & ((\z80_|execute_|ctl_reg_in_hi~2_combout ) # -// ((!\z80_|execute_|ctl_flags_bus~5_combout & \z80_|execute_|setM1~53_combout )))) - - .dataa(\z80_|execute_|setM1~22_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datac(\z80_|execute_|ctl_flags_bus~5_combout ), - .datad(\z80_|execute_|setM1~53_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~23 .lut_mask = 16'h4F44; -defparam \z80_|execute_|setM1~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N6 -cycloneive_lcell_comb \z80_|execute_|setM1~18 ( -// Equation(s): -// \z80_|execute_|setM1~18_combout = (\z80_|execute_|ctl_mRead~11_combout & (((\z80_|pla_decode_|Equal37~0_combout & !\z80_|alu_control_|flags_cond_true~q )) # (!\z80_|execute_|ctl_flags_bus~4_combout ))) - - .dataa(\z80_|pla_decode_|Equal37~0_combout ), - .datab(\z80_|execute_|ctl_mRead~11_combout ), - .datac(\z80_|alu_control_|flags_cond_true~q ), - .datad(\z80_|execute_|ctl_flags_bus~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~18 .lut_mask = 16'h08CC; -defparam \z80_|execute_|setM1~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|setM1~19 ( -// Equation(s): -// \z80_|execute_|setM1~19_combout = (\z80_|execute_|setM1~18_combout ) # ((\z80_|execute_|ixy_d~8_combout & (\z80_|pla_decode_|Equal10~0_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ))) - - .dataa(\z80_|execute_|setM1~18_combout ), - .datab(\z80_|execute_|ixy_d~8_combout ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~19 .lut_mask = 16'hEAAA; -defparam \z80_|execute_|setM1~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|setM1~20 ( -// Equation(s): -// \z80_|execute_|setM1~20_combout = ((\z80_|execute_|setM1~19_combout ) # ((\z80_|execute_|ctl_iorw~11_combout & \z80_|execute_|ctl_mWrite~3_combout ))) # (!\z80_|execute_|ctl_flags_sz_we~0_combout ) - - .dataa(\z80_|execute_|ctl_iorw~11_combout ), - .datab(\z80_|execute_|ctl_mWrite~3_combout ), - .datac(\z80_|execute_|ctl_flags_sz_we~0_combout ), - .datad(\z80_|execute_|setM1~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~20 .lut_mask = 16'hFF8F; -defparam \z80_|execute_|setM1~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N16 -cycloneive_lcell_comb \z80_|execute_|setM1~34 ( -// Equation(s): -// \z80_|execute_|setM1~34_combout = (\z80_|execute_|setM1~33_combout ) # ((\z80_|execute_|setM1~27_combout ) # ((\z80_|execute_|setM1~23_combout ) # (\z80_|execute_|setM1~20_combout ))) - - .dataa(\z80_|execute_|setM1~33_combout ), - .datab(\z80_|execute_|setM1~27_combout ), - .datac(\z80_|execute_|setM1~23_combout ), - .datad(\z80_|execute_|setM1~20_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~34 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|setM1~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|setM1~52 ( -// Equation(s): -// \z80_|execute_|setM1~52_combout = (!\z80_|execute_|setM1~17_combout & (!\z80_|execute_|setM1~34_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|execute_|setM1~51_combout )))) - - .dataa(\z80_|execute_|setM1~51_combout ), - .datab(\z80_|execute_|setM1~17_combout ), - .datac(\z80_|execute_|setM1~34_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~52_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~52 .lut_mask = 16'h0301; -defparam \z80_|execute_|setM1~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N24 -cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_14 ( -// Equation(s): -// \z80_|sequencer_|SYNTHESIZED_WIRE_14~combout = (\z80_|execute_|setM1~52_combout & (\z80_|sequencer_|DFFE_T2_ff~q & !\z80_|execute_|nextM~14_combout )) - - .dataa(\z80_|execute_|setM1~52_combout ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_14 .lut_mask = 16'h00A0; -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y17_N25 -dffeas \z80_|sequencer_|DFFE_T3_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|DFFE_T3_ff~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_T3_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_T3_ff .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout = (\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 .lut_mask = 16'h00F0; -defparam \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N24 -cycloneive_lcell_comb \z80_|decode_state_|in_halt~0 ( -// Equation(s): -// \z80_|decode_state_|in_halt~0_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|decode_state_|in_halt~q & !\z80_|interrupts_|DFFE_inst44~q )) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(gnd), - .datac(\z80_|decode_state_|in_halt~q ), - .datad(\z80_|interrupts_|DFFE_inst44~q ), - .cin(gnd), - .combout(\z80_|decode_state_|in_halt~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|in_halt~0 .lut_mask = 16'h0050; -defparam \z80_|decode_state_|in_halt~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N24 -cycloneive_lcell_comb \z80_|decode_state_|in_halt~1 ( -// Equation(s): -// \z80_|decode_state_|in_halt~1_combout = (\z80_|decode_state_|in_halt~0_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (!\z80_|decode_state_|in_halt~q & \z80_|pla_decode_|Equal77~1_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|decode_state_|in_halt~0_combout ), - .datac(\z80_|decode_state_|in_halt~q ), - .datad(\z80_|pla_decode_|Equal77~1_combout ), - .cin(gnd), - .combout(\z80_|decode_state_|in_halt~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|in_halt~1 .lut_mask = 16'hCECC; -defparam \z80_|decode_state_|in_halt~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y13_N25 -dffeas \z80_|decode_state_|in_halt ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|decode_state_|in_halt~1_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|decode_state_|in_halt~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|decode_state_|in_halt .is_wysiwyg = "true"; -defparam \z80_|decode_state_|in_halt .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~2 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~2_combout = (!\z80_|execute_|ctl_bus_zero_oe~0_combout & (!\z80_|execute_|ctl_bus_ff_oe~1_combout & ((\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) # (!\z80_|decode_state_|in_halt~q )))) - - .dataa(\z80_|decode_state_|in_halt~q ), - .datab(\z80_|execute_|ctl_bus_zero_oe~0_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|execute_|ctl_bus_ff_oe~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~2 .lut_mask = 16'h0031; -defparam \z80_|execute_|ctl_bus_db_oe~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~5 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~5_combout = (\z80_|execute_|ctl_ir_we~8_combout ) # ((\z80_|execute_|ctl_ir_we~14_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout ) # (\z80_|pla_decode_|Equal41~2_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(\z80_|execute_|ctl_ir_we~14_combout ), - .datac(\z80_|execute_|ctl_ir_we~11_combout ), - .datad(\z80_|pla_decode_|Equal41~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~5 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_bus_db_oe~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~6 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~6_combout = ((\z80_|execute_|ctl_66_oe~2_combout ) # ((\z80_|execute_|ctl_ir_we~4_combout & \z80_|execute_|ctl_bus_db_oe~5_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_66_oe~2_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~6 .lut_mask = 16'hFDF5; -defparam \z80_|execute_|ctl_bus_db_oe~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~4 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~4_combout = (!\z80_|execute_|ctl_bus_db_oe~3_combout ) # (!\z80_|execute_|ctl_bus_db_oe~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_bus_db_oe~0_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~4 .lut_mask = 16'h0FFF; -defparam \z80_|execute_|ctl_bus_db_oe~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~combout = (\z80_|execute_|ctl_bus_db_oe~2_combout & (((\z80_|execute_|ctl_bus_db_oe~6_combout ) # (\z80_|execute_|ctl_bus_db_oe~4_combout )) # (!\z80_|execute_|ctl_sw_1d~6_combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_oe~2_combout ), + .dataa(\z80_|execute_|ctl_66_oe~2_combout ), .datab(\z80_|execute_|ctl_sw_1d~6_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~6_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~4_combout ), + .datac(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datad(\z80_|bus_control_|db[3]~21_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~combout ), + .combout(\z80_|sw1_|db_down[3]~2_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe .lut_mask = 16'hAAA2; -defparam \z80_|execute_|ctl_bus_db_oe .sum_lutc_input = "datac"; +defparam \z80_|sw1_|db_down[3]~2 .lut_mask = 16'hFFC4; +defparam \z80_|sw1_|db_down[3]~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N28 -cycloneive_lcell_comb \z80_|bus_control_|db[0]~6 ( +// Location: LCCOMB_X31_Y14_N6 +cycloneive_lcell_comb \z80_|alu_control_|db[3]~34 ( // Equation(s): -// \z80_|bus_control_|db[0]~6_combout = (\z80_|execute_|ctl_bus_db_oe~combout ) # ((\z80_|execute_|ctl_bus_db_we~7_combout ) # (!\z80_|execute_|ctl_bus_db_oe~2_combout )) +// \z80_|alu_control_|db[3]~34_combout = (\z80_|alu_control_|db[3]~33_combout & (\z80_|sw1_|db_down[3]~2_combout & ((\z80_|reg_file_|gdfx_temp0[3]~52_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) - .dataa(\z80_|execute_|ctl_bus_db_oe~combout ), + .dataa(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .datac(\z80_|alu_control_|db[3]~33_combout ), + .datad(\z80_|sw1_|db_down[3]~2_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[3]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[3]~34 .lut_mask = 16'hB000; +defparam \z80_|alu_control_|db[3]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N0 +cycloneive_lcell_comb \z80_|alu_control_|db[3]~35 ( +// Equation(s): +// \z80_|alu_control_|db[3]~35_combout = ((\z80_|alu_control_|db[3]~34_combout & ((\z80_|alu_|db[3]~20_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) + + .dataa(\z80_|alu_control_|db[3]~34_combout ), + .datab(\z80_|execute_|ctl_sw_2u~7_combout ), + .datac(\z80_|alu_|db[3]~20_combout ), + .datad(\z80_|alu_control_|db[6]~11_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[3]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[3]~35 .lut_mask = 16'hA2FF; +defparam \z80_|alu_control_|db[3]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][0]~75 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][0]~75_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [1])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), .datab(gnd), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~2_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[0]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[0]~6 .lut_mask = 16'hFAFF; -defparam \z80_|bus_control_|db[0]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][3]~93 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][3]~93_combout = (\ula_|zx_keyboard_|keys[7][4]~19_combout & (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[6][4]~47_combout ))) - - .dataa(\ula_|zx_keyboard_|keys[7][4]~19_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|keys[6][4]~47_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][3]~93_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][3]~93 .lut_mask = 16'h0800; -defparam \ula_|zx_keyboard_|keys[1][3]~93 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][3]~94 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][3]~94_combout = (\ula_|zx_keyboard_|keys[1][3]~93_combout & ((\ula_|ps2_keyboard_|shiftreg [3] & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[1][3]~q )))) # -// (!\ula_|zx_keyboard_|keys[1][3]~93_combout & (((\ula_|zx_keyboard_|keys[1][3]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[1][3]~93_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|zx_keyboard_|keys[1][3]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][3]~94_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][3]~94 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[1][3]~94 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y19_N31 -dffeas \ula_|zx_keyboard_|keys[1][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[1][3]~94_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[1][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[1][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][3]~96 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][3]~96_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [1]))) # (!\ula_|ps2_keyboard_|shiftreg [3] & -// (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), .datad(\ula_|ps2_keyboard_|shiftreg [1]), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][3]~96_combout ), + .combout(\ula_|zx_keyboard_|keys[3][0]~75_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][3]~96 .lut_mask = 16'h0810; -defparam \ula_|zx_keyboard_|keys[0][3]~96 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[3][0]~75 .lut_mask = 16'h0500; +defparam \ula_|zx_keyboard_|keys[3][0]~75 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y18_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][3]~98 ( +// Location: LCCOMB_X27_Y8_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|Selector5~0 ( // Equation(s): -// \ula_|zx_keyboard_|keys[0][3]~98_combout = (\ula_|zx_keyboard_|keys[0][3]~96_combout & ((\ula_|zx_keyboard_|keys[0][4]~97_combout & ((!\ula_|zx_keyboard_|keys[2][4]~95_combout ))) # (!\ula_|zx_keyboard_|keys[0][4]~97_combout & -// (\ula_|zx_keyboard_|keys[0][3]~q )))) # (!\ula_|zx_keyboard_|keys[0][3]~96_combout & (((\ula_|zx_keyboard_|keys[0][3]~q )))) +// \ula_|zx_keyboard_|Selector5~0_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|keys[3][0]~75_combout & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [6]))) - .dataa(\ula_|zx_keyboard_|keys[0][3]~96_combout ), - .datab(\ula_|zx_keyboard_|keys[0][4]~97_combout ), - .datac(\ula_|zx_keyboard_|keys[0][3]~q ), - .datad(\ula_|zx_keyboard_|keys[2][4]~95_combout ), + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|zx_keyboard_|keys[3][0]~75_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][3]~98_combout ), + .combout(\ula_|zx_keyboard_|Selector5~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][3]~98 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[0][3]~98 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|Selector5~0 .lut_mask = 16'h0400; +defparam \ula_|zx_keyboard_|Selector5~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X29_Y18_N1 -dffeas \ula_|zx_keyboard_|keys[0][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[0][3]~98_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[0][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[0][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N4 -cycloneive_lcell_comb \D[3]~65 ( +// Location: LCCOMB_X26_Y10_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|Selector5~1 ( // Equation(s): -// \D[3]~65_combout = (\z80_|address_pins_|abus[9]~17_combout & ((\z80_|address_pins_|abus[8]~18_combout ) # ((!\ula_|zx_keyboard_|keys[0][3]~q )))) # (!\z80_|address_pins_|abus[9]~17_combout & (!\ula_|zx_keyboard_|keys[1][3]~q & -// ((\z80_|address_pins_|abus[8]~18_combout ) # (!\ula_|zx_keyboard_|keys[0][3]~q )))) - - .dataa(\z80_|address_pins_|abus[9]~17_combout ), - .datab(\z80_|address_pins_|abus[8]~18_combout ), - .datac(\ula_|zx_keyboard_|keys[1][3]~q ), - .datad(\ula_|zx_keyboard_|keys[0][3]~q ), - .cin(gnd), - .combout(\D[3]~65_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~65 .lut_mask = 16'h8CAF; -defparam \D[3]~65 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][3]~99 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][3]~99_combout = (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [2])) +// \ula_|zx_keyboard_|Selector5~1_combout = (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [2]))) .dataa(\ula_|ps2_keyboard_|shiftreg [1]), .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][3]~99_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][3]~99 .lut_mask = 16'h4040; -defparam \ula_|zx_keyboard_|keys[3][3]~99 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][3]~100 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][3]~100_combout = (\ula_|zx_keyboard_|keys[3][3]~48_combout & ((\ula_|zx_keyboard_|keys[3][3]~99_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[3][3]~99_combout & (\ula_|zx_keyboard_|keys[3][3]~q -// )))) # (!\ula_|zx_keyboard_|keys[3][3]~48_combout & (((\ula_|zx_keyboard_|keys[3][3]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[3][3]~48_combout ), - .datab(\ula_|zx_keyboard_|keys[3][3]~99_combout ), - .datac(\ula_|zx_keyboard_|keys[3][3]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][3]~100_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][3]~100 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[3][3]~100 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y20_N9 -dffeas \ula_|zx_keyboard_|keys[3][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[3][3]~100_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[3][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[3][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~101 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][3]~101_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & !\ula_|ps2_keyboard_|shiftreg [2])) - - .dataa(\ula_|zx_keyboard_|shifted~q ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), .datad(\ula_|ps2_keyboard_|shiftreg [2]), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][3]~101_combout ), + .combout(\ula_|zx_keyboard_|Selector5~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][3]~101 .lut_mask = 16'hCCDD; -defparam \ula_|zx_keyboard_|keys[2][3]~101 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|Selector5~1 .lut_mask = 16'h4000; +defparam \ula_|zx_keyboard_|Selector5~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y18_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~102 ( +// Location: LCCOMB_X27_Y8_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~132 ( // Equation(s): -// \ula_|zx_keyboard_|keys[2][3]~102_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [2]))) # (!\ula_|ps2_keyboard_|shiftreg [3] & -// (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [2]))) +// \ula_|zx_keyboard_|keys[4][3]~132_combout = (\ula_|zx_keyboard_|Selector5~0_combout ) # ((\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|zx_keyboard_|Selector5~1_combout ))) - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .dataa(\ula_|zx_keyboard_|Selector5~0_combout ), .datab(\ula_|ps2_keyboard_|shiftreg [5]), .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|zx_keyboard_|Selector5~1_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][3]~102_combout ), + .combout(\ula_|zx_keyboard_|keys[4][3]~132_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][3]~102 .lut_mask = 16'h0810; -defparam \ula_|zx_keyboard_|keys[2][3]~102 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[4][3]~132 .lut_mask = 16'hAEAA; +defparam \ula_|zx_keyboard_|keys[4][3]~132 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y18_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~133 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][3]~133_combout = (\ula_|zx_keyboard_|keys[5][1]~36_combout & (\ula_|zx_keyboard_|keys[2][3]~102_combout & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1]))) - - .dataa(\ula_|zx_keyboard_|keys[5][1]~36_combout ), - .datab(\ula_|zx_keyboard_|keys[2][3]~102_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][3]~133_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][3]~133 .lut_mask = 16'h0080; -defparam \ula_|zx_keyboard_|keys[2][3]~133 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~103 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][3]~103_combout = (\ula_|zx_keyboard_|keys[2][3]~133_combout & (!\ula_|zx_keyboard_|keys[2][3]~101_combout )) # (!\ula_|zx_keyboard_|keys[2][3]~133_combout & ((\ula_|zx_keyboard_|keys[2][3]~q ))) - - .dataa(\ula_|zx_keyboard_|keys[2][3]~101_combout ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[2][3]~q ), - .datad(\ula_|zx_keyboard_|keys[2][3]~133_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][3]~103_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][3]~103 .lut_mask = 16'h55F0; -defparam \ula_|zx_keyboard_|keys[2][3]~103 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y18_N3 -dffeas \ula_|zx_keyboard_|keys[2][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[2][3]~103_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[2][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[2][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N28 -cycloneive_lcell_comb \D[3]~66 ( -// Equation(s): -// \D[3]~66_combout = (\z80_|address_pins_|abus[11]~19_combout & (((\z80_|address_pins_|abus[10]~24_combout ) # (!\ula_|zx_keyboard_|keys[2][3]~q )))) # (!\z80_|address_pins_|abus[11]~19_combout & (!\ula_|zx_keyboard_|keys[3][3]~q & -// ((\z80_|address_pins_|abus[10]~24_combout ) # (!\ula_|zx_keyboard_|keys[2][3]~q )))) - - .dataa(\z80_|address_pins_|abus[11]~19_combout ), - .datab(\ula_|zx_keyboard_|keys[3][3]~q ), - .datac(\z80_|address_pins_|abus[10]~24_combout ), - .datad(\ula_|zx_keyboard_|keys[2][3]~q ), - .cin(gnd), - .combout(\D[3]~66_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~66 .lut_mask = 16'hB0BB; -defparam \D[3]~66 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][3]~104 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][3]~104_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [0])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [5]), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][3]~104_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][3]~104 .lut_mask = 16'h0808; -defparam \ula_|zx_keyboard_|keys[5][3]~104 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][3]~105 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][3]~105_combout = (\ula_|zx_keyboard_|keys[5][3]~104_combout & ((\ula_|zx_keyboard_|keys[1][4]~25_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[1][4]~25_combout & (\ula_|zx_keyboard_|keys[5][3]~q -// )))) # (!\ula_|zx_keyboard_|keys[5][3]~104_combout & (((\ula_|zx_keyboard_|keys[5][3]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[5][3]~104_combout ), - .datab(\ula_|zx_keyboard_|keys[1][4]~25_combout ), - .datac(\ula_|zx_keyboard_|keys[5][3]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][3]~105_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][3]~105 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[5][3]~105 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y19_N23 -dffeas \ula_|zx_keyboard_|keys[5][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[5][3]~105_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[5][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[5][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N16 +// Location: LCCOMB_X27_Y8_N10 cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~106 ( // Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~106_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[5][4]~24_combout & (\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|WideOr16~2_combout ))) +// \ula_|zx_keyboard_|keys[4][3]~106_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|WideOr16~2_combout & (\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[5][4]~22_combout ))) .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|zx_keyboard_|keys[5][4]~24_combout ), + .datab(\ula_|zx_keyboard_|WideOr16~2_combout ), .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|zx_keyboard_|WideOr16~2_combout ), + .datad(\ula_|zx_keyboard_|keys[5][4]~22_combout ), .cin(gnd), .combout(\ula_|zx_keyboard_|keys[4][3]~106_combout ), .cout()); @@ -52111,110 +41584,59 @@ defparam \ula_|zx_keyboard_|keys[4][3]~106 .lut_mask = 16'h8000; defparam \ula_|zx_keyboard_|keys[4][3]~106 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X27_Y21_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|Selector5~1 ( -// Equation(s): -// \ula_|zx_keyboard_|Selector5~1_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|Selector5~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|Selector5~1 .lut_mask = 16'h0800; -defparam \ula_|zx_keyboard_|Selector5~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|Selector5~0 ( -// Equation(s): -// \ula_|zx_keyboard_|Selector5~0_combout = (\ula_|zx_keyboard_|keys[3][0]~78_combout & (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [5]))) - - .dataa(\ula_|zx_keyboard_|keys[3][0]~78_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|Selector5~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|Selector5~0 .lut_mask = 16'h0020; -defparam \ula_|zx_keyboard_|Selector5~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y21_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~134 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~134_combout = (\ula_|zx_keyboard_|Selector5~0_combout ) # ((\ula_|zx_keyboard_|Selector5~1_combout & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [5]))) - - .dataa(\ula_|zx_keyboard_|Selector5~1_combout ), - .datab(\ula_|zx_keyboard_|Selector5~0_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][3]~134_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~134 .lut_mask = 16'hCECC; -defparam \ula_|zx_keyboard_|keys[4][3]~134 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y21_N6 +// Location: LCCOMB_X27_Y8_N26 cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~107 ( // Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~107_combout = (\ula_|zx_keyboard_|extended~q & (\ula_|zx_keyboard_|keys[4][3]~106_combout )) # (!\ula_|zx_keyboard_|extended~q & (((\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[4][3]~134_combout )))) +// \ula_|zx_keyboard_|keys[4][3]~107_combout = (\ula_|zx_keyboard_|extended~q & (((\ula_|zx_keyboard_|keys[4][3]~106_combout )))) # (!\ula_|zx_keyboard_|extended~q & (\ula_|zx_keyboard_|keys[4][3]~132_combout & (\ula_|ps2_keyboard_|shiftreg [4]))) .dataa(\ula_|zx_keyboard_|extended~q ), - .datab(\ula_|zx_keyboard_|keys[4][3]~106_combout ), + .datab(\ula_|zx_keyboard_|keys[4][3]~132_combout ), .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|keys[4][3]~134_combout ), + .datad(\ula_|zx_keyboard_|keys[4][3]~106_combout ), .cin(gnd), .combout(\ula_|zx_keyboard_|keys[4][3]~107_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~107 .lut_mask = 16'hD888; +defparam \ula_|zx_keyboard_|keys[4][3]~107 .lut_mask = 16'hEA40; defparam \ula_|zx_keyboard_|keys[4][3]~107 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y21_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~135 ( +// Location: LCCOMB_X27_Y8_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~133 ( // Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~135_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|shifted~q ))) +// \ula_|zx_keyboard_|keys[4][3]~133_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|shifted~q ))) .dataa(\ula_|zx_keyboard_|extended~q ), .datab(\ula_|zx_keyboard_|released~q ), .datac(\ula_|ps2_keyboard_|shiftreg [5]), .datad(\ula_|zx_keyboard_|shifted~q ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][3]~135_combout ), + .combout(\ula_|zx_keyboard_|keys[4][3]~133_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~135 .lut_mask = 16'hCDCC; -defparam \ula_|zx_keyboard_|keys[4][3]~135 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[4][3]~133 .lut_mask = 16'hCDCC; +defparam \ula_|zx_keyboard_|keys[4][3]~133 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y21_N22 +// Location: LCCOMB_X27_Y8_N6 cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~108 ( // Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~108_combout = (\ula_|zx_keyboard_|keys[4][3]~107_combout & ((\ula_|zx_keyboard_|keys[0][0]~15_combout & ((!\ula_|zx_keyboard_|keys[4][3]~135_combout ))) # (!\ula_|zx_keyboard_|keys[0][0]~15_combout & -// (\ula_|zx_keyboard_|keys[4][3]~q )))) # (!\ula_|zx_keyboard_|keys[4][3]~107_combout & (((\ula_|zx_keyboard_|keys[4][3]~q )))) +// \ula_|zx_keyboard_|keys[4][3]~108_combout = (\ula_|zx_keyboard_|keys[4][3]~107_combout & ((\ula_|zx_keyboard_|keys[0][0]~13_combout & (!\ula_|zx_keyboard_|keys[4][3]~133_combout )) # (!\ula_|zx_keyboard_|keys[0][0]~13_combout & +// ((\ula_|zx_keyboard_|keys[4][3]~q ))))) # (!\ula_|zx_keyboard_|keys[4][3]~107_combout & (((\ula_|zx_keyboard_|keys[4][3]~q )))) .dataa(\ula_|zx_keyboard_|keys[4][3]~107_combout ), - .datab(\ula_|zx_keyboard_|keys[0][0]~15_combout ), + .datab(\ula_|zx_keyboard_|keys[4][3]~133_combout ), .datac(\ula_|zx_keyboard_|keys[4][3]~q ), - .datad(\ula_|zx_keyboard_|keys[4][3]~135_combout ), + .datad(\ula_|zx_keyboard_|keys[0][0]~13_combout ), .cin(gnd), .combout(\ula_|zx_keyboard_|keys[4][3]~108_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~108 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[4][3]~108 .lut_mask = 16'h72F0; defparam \ula_|zx_keyboard_|keys[4][3]~108 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y21_N23 +// Location: FF_X27_Y8_N7 dffeas \ula_|zx_keyboard_|keys[4][3] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\ula_|zx_keyboard_|keys[4][3]~108_combout ), @@ -52233,79 +41655,555 @@ defparam \ula_|zx_keyboard_|keys[4][3] .is_wysiwyg = "true"; defparam \ula_|zx_keyboard_|keys[4][3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y19_N20 -cycloneive_lcell_comb \D[3]~67 ( +// Location: LCCOMB_X28_Y7_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][3]~104 ( // Equation(s): -// \D[3]~67_combout = (\ula_|zx_keyboard_|keys[5][3]~q & (\z80_|address_pins_|abus[13]~20_combout & ((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][3]~q )))) # (!\ula_|zx_keyboard_|keys[5][3]~q & -// (((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][3]~q )))) +// \ula_|zx_keyboard_|keys[5][3]~104_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [5])) - .dataa(\ula_|zx_keyboard_|keys[5][3]~q ), - .datab(\z80_|address_pins_|abus[13]~20_combout ), - .datac(\ula_|zx_keyboard_|keys[4][3]~q ), - .datad(\z80_|address_pins_|abus[12]~21_combout ), + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), .cin(gnd), - .combout(\D[3]~67_combout ), + .combout(\ula_|zx_keyboard_|keys[5][3]~104_combout ), .cout()); // synopsys translate_off -defparam \D[3]~67 .lut_mask = 16'hDD0D; -defparam \D[3]~67 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[5][3]~104 .lut_mask = 16'h0A00; +defparam \ula_|zx_keyboard_|keys[5][3]~104 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X27_Y21_N4 +// Location: LCCOMB_X28_Y7_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][3]~105 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][3]~105_combout = (\ula_|zx_keyboard_|keys[1][4]~23_combout & ((\ula_|zx_keyboard_|keys[5][3]~104_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[5][3]~104_combout & ((\ula_|zx_keyboard_|keys[5][3]~q +// ))))) # (!\ula_|zx_keyboard_|keys[1][4]~23_combout & (((\ula_|zx_keyboard_|keys[5][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[1][4]~23_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[5][3]~q ), + .datad(\ula_|zx_keyboard_|keys[5][3]~104_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][3]~105_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][3]~105 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[5][3]~105 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y7_N23 +dffeas \ula_|zx_keyboard_|keys[5][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[5][3]~105_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[5][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[5][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N12 +cycloneive_lcell_comb \D[3]~55 ( +// Equation(s): +// \D[3]~55_combout = (\z80_|address_pins_|abus[12]~21_combout & (((\z80_|address_pins_|abus[13]~20_combout ) # (!\ula_|zx_keyboard_|keys[5][3]~q )))) # (!\z80_|address_pins_|abus[12]~21_combout & (!\ula_|zx_keyboard_|keys[4][3]~q & +// ((\z80_|address_pins_|abus[13]~20_combout ) # (!\ula_|zx_keyboard_|keys[5][3]~q )))) + + .dataa(\z80_|address_pins_|abus[12]~21_combout ), + .datab(\ula_|zx_keyboard_|keys[4][3]~q ), + .datac(\ula_|zx_keyboard_|keys[5][3]~q ), + .datad(\z80_|address_pins_|abus[13]~20_combout ), + .cin(gnd), + .combout(\D[3]~55_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~55 .lut_mask = 16'hBB0B; +defparam \D[3]~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~46 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][4]~46_combout = (\ula_|zx_keyboard_|keys[7][1]~21_combout & (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|zx_keyboard_|keys[7][1]~21_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][4]~46_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][4]~46 .lut_mask = 16'h0200; +defparam \ula_|zx_keyboard_|keys[6][4]~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~62 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][4]~62_combout = (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][4]~62_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][4]~62 .lut_mask = 16'h00F0; +defparam \ula_|zx_keyboard_|keys[5][4]~62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][3]~102 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][3]~102_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|zx_keyboard_|keys[6][4]~46_combout & (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|zx_keyboard_|keys[5][4]~62_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|zx_keyboard_|keys[6][4]~46_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|zx_keyboard_|keys[5][4]~62_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][3]~102_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][3]~102 .lut_mask = 16'h4000; +defparam \ula_|zx_keyboard_|keys[3][3]~102 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][3]~103 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][3]~103_combout = (\ula_|zx_keyboard_|keys[3][3]~102_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][3]~102_combout & ((\ula_|zx_keyboard_|keys[3][3]~q ))) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[3][3]~q ), + .datad(\ula_|zx_keyboard_|keys[3][3]~102_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][3]~103_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][3]~103 .lut_mask = 16'h33F0; +defparam \ula_|zx_keyboard_|keys[3][3]~103 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y7_N11 +dffeas \ula_|zx_keyboard_|keys[3][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[3][3]~103_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[3][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[3][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~96 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][4]~96_combout = (\ula_|zx_keyboard_|keys[5][1]~34_combout & (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [5] $ (\ula_|ps2_keyboard_|shiftreg [6])))) + + .dataa(\ula_|zx_keyboard_|keys[5][1]~34_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][4]~96_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][4]~96 .lut_mask = 16'h0208; +defparam \ula_|zx_keyboard_|keys[0][4]~96 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~94 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][4]~94_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [6])) + + .dataa(\ula_|zx_keyboard_|shifted~q ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][4]~94_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][4]~94 .lut_mask = 16'hDDCC; +defparam \ula_|zx_keyboard_|keys[2][4]~94 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][3]~95 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][3]~95_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [6]))) # (!\ula_|ps2_keyboard_|shiftreg [1] & +// (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [6]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][3]~95_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][3]~95 .lut_mask = 16'h0810; +defparam \ula_|zx_keyboard_|keys[0][3]~95 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][3]~97 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][3]~97_combout = (\ula_|zx_keyboard_|keys[0][4]~96_combout & ((\ula_|zx_keyboard_|keys[0][3]~95_combout & (!\ula_|zx_keyboard_|keys[2][4]~94_combout )) # (!\ula_|zx_keyboard_|keys[0][3]~95_combout & +// ((\ula_|zx_keyboard_|keys[0][3]~q ))))) # (!\ula_|zx_keyboard_|keys[0][4]~96_combout & (((\ula_|zx_keyboard_|keys[0][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[0][4]~96_combout ), + .datab(\ula_|zx_keyboard_|keys[2][4]~94_combout ), + .datac(\ula_|zx_keyboard_|keys[0][3]~q ), + .datad(\ula_|zx_keyboard_|keys[0][3]~95_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][3]~97_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][3]~97 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[0][3]~97 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y9_N19 +dffeas \ula_|zx_keyboard_|keys[0][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[0][3]~97_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[0][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[0][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~45 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][4]~45_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [1])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][4]~45_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][4]~45 .lut_mask = 16'h5000; +defparam \ula_|zx_keyboard_|keys[6][4]~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][3]~92 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][3]~92_combout = (\ula_|zx_keyboard_|keys[6][4]~45_combout & (\ula_|zx_keyboard_|keys[7][4]~17_combout & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|zx_keyboard_|keys[6][4]~45_combout ), + .datab(\ula_|zx_keyboard_|keys[7][4]~17_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][3]~92_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][3]~92 .lut_mask = 16'h0800; +defparam \ula_|zx_keyboard_|keys[1][3]~92 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][3]~93 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][3]~93_combout = (\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[1][3]~92_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[1][3]~92_combout & ((\ula_|zx_keyboard_|keys[1][3]~q ))))) # +// (!\ula_|ps2_keyboard_|shiftreg [3] & (((\ula_|zx_keyboard_|keys[1][3]~q )))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[1][3]~q ), + .datad(\ula_|zx_keyboard_|keys[1][3]~92_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][3]~93_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][3]~93 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[1][3]~93 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y7_N15 +dffeas \ula_|zx_keyboard_|keys[1][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[1][3]~93_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[1][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[1][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N0 +cycloneive_lcell_comb \D[3]~53 ( +// Equation(s): +// \D[3]~53_combout = (\ula_|zx_keyboard_|keys[0][3]~q & (\z80_|address_pins_|abus[8]~18_combout & ((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][3]~q )))) # (!\ula_|zx_keyboard_|keys[0][3]~q & +// (((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[0][3]~q ), + .datab(\z80_|address_pins_|abus[8]~18_combout ), + .datac(\ula_|zx_keyboard_|keys[1][3]~q ), + .datad(\z80_|address_pins_|abus[9]~17_combout ), + .cin(gnd), + .combout(\D[3]~53_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~53 .lut_mask = 16'hDD0D; +defparam \D[3]~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~99 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][3]~99_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [6])) # (!\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [2] & +// \ula_|ps2_keyboard_|shiftreg [6])) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][3]~99_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][3]~99 .lut_mask = 16'h03C0; +defparam \ula_|zx_keyboard_|keys[2][3]~99 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~100 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][3]~100_combout = (\ula_|zx_keyboard_|keys[2][3]~99_combout & (\ula_|zx_keyboard_|keys[5][4]~62_combout & (\ula_|ps2_keyboard_|shiftreg [2] $ (!\ula_|ps2_keyboard_|shiftreg [3])))) + + .dataa(\ula_|zx_keyboard_|keys[2][3]~99_combout ), + .datab(\ula_|zx_keyboard_|keys[5][4]~62_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][3]~100_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][3]~100 .lut_mask = 16'h8008; +defparam \ula_|zx_keyboard_|keys[2][3]~100 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~98 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][3]~98_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & !\ula_|ps2_keyboard_|shiftreg [2])) + + .dataa(\ula_|zx_keyboard_|shifted~q ), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][3]~98_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][3]~98 .lut_mask = 16'hFF05; +defparam \ula_|zx_keyboard_|keys[2][3]~98 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~101 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][3]~101_combout = (\ula_|zx_keyboard_|keys[5][1]~34_combout & ((\ula_|zx_keyboard_|keys[2][3]~100_combout & ((!\ula_|zx_keyboard_|keys[2][3]~98_combout ))) # (!\ula_|zx_keyboard_|keys[2][3]~100_combout & +// (\ula_|zx_keyboard_|keys[2][3]~q )))) # (!\ula_|zx_keyboard_|keys[5][1]~34_combout & (((\ula_|zx_keyboard_|keys[2][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][1]~34_combout ), + .datab(\ula_|zx_keyboard_|keys[2][3]~100_combout ), + .datac(\ula_|zx_keyboard_|keys[2][3]~q ), + .datad(\ula_|zx_keyboard_|keys[2][3]~98_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][3]~101_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][3]~101 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[2][3]~101 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y9_N9 +dffeas \ula_|zx_keyboard_|keys[2][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[2][3]~101_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[2][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[2][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~3 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row~3_combout = ((\z80_|address_pins_|DFFE_apin_latch [10]) # (!\ula_|zx_keyboard_|keys[2][3]~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|address_pins_|DFFE_apin_latch [10]), + .datac(gnd), + .datad(\ula_|zx_keyboard_|keys[2][3]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row~3 .lut_mask = 16'hDDFF; +defparam \ula_|zx_keyboard_|key_row~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N20 +cycloneive_lcell_comb \D[3]~54 ( +// Equation(s): +// \D[3]~54_combout = (\D[3]~53_combout & (\ula_|zx_keyboard_|key_row~3_combout & ((\z80_|address_pins_|abus[11]~19_combout ) # (!\ula_|zx_keyboard_|keys[3][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[3][3]~q ), + .datab(\D[3]~53_combout ), + .datac(\z80_|address_pins_|abus[11]~19_combout ), + .datad(\ula_|zx_keyboard_|key_row~3_combout ), + .cin(gnd), + .combout(\D[3]~54_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~54 .lut_mask = 16'hC400; +defparam \D[3]~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~109 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][4]~109_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [6])) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|shifted~q ), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][4]~109_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][4]~109 .lut_mask = 16'hFFC0; +defparam \ula_|zx_keyboard_|keys[0][4]~109 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~60 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][2]~60_combout = (\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [6]) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][2]~60_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2]~60 .lut_mask = 16'h0C0C; +defparam \ula_|zx_keyboard_|keys[7][2]~60 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][3]~110 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][3]~110_combout = (\ula_|zx_keyboard_|WideOr16~2_combout & ((\ula_|zx_keyboard_|keys[7][2]~30_combout ) # ((\ula_|zx_keyboard_|keys[7][2]~60_combout & \ula_|ps2_keyboard_|shiftreg [4])))) + + .dataa(\ula_|zx_keyboard_|keys[7][2]~60_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|zx_keyboard_|WideOr16~2_combout ), + .datad(\ula_|zx_keyboard_|keys[7][2]~30_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][3]~110_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][3]~110 .lut_mask = 16'hF080; +defparam \ula_|zx_keyboard_|keys[7][3]~110 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][3]~111 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][3]~111_combout = (\ula_|zx_keyboard_|keys[0][0]~13_combout & (!\ula_|zx_keyboard_|extended~q & (\ula_|zx_keyboard_|keys[7][3]~110_combout & !\ula_|ps2_keyboard_|shiftreg [2]))) + + .dataa(\ula_|zx_keyboard_|keys[0][0]~13_combout ), + .datab(\ula_|zx_keyboard_|extended~q ), + .datac(\ula_|zx_keyboard_|keys[7][3]~110_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][3]~111_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][3]~111 .lut_mask = 16'h0020; +defparam \ula_|zx_keyboard_|keys[7][3]~111 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N14 cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][3]~112 ( // Equation(s): -// \ula_|zx_keyboard_|keys[7][3]~112_combout = (\ula_|zx_keyboard_|WideOr16~2_combout & ((\ula_|zx_keyboard_|keys[7][2]~32_combout ) # ((\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[7][2]~61_combout )))) +// \ula_|zx_keyboard_|keys[7][3]~112_combout = (\ula_|zx_keyboard_|keys[7][3]~111_combout & (!\ula_|zx_keyboard_|keys[0][4]~109_combout )) # (!\ula_|zx_keyboard_|keys[7][3]~111_combout & ((\ula_|zx_keyboard_|keys[7][3]~q ))) - .dataa(\ula_|zx_keyboard_|WideOr16~2_combout ), - .datab(\ula_|zx_keyboard_|keys[7][2]~32_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|keys[7][2]~61_combout ), + .dataa(\ula_|zx_keyboard_|keys[0][4]~109_combout ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[7][3]~q ), + .datad(\ula_|zx_keyboard_|keys[7][3]~111_combout ), .cin(gnd), .combout(\ula_|zx_keyboard_|keys[7][3]~112_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][3]~112 .lut_mask = 16'hA888; +defparam \ula_|zx_keyboard_|keys[7][3]~112 .lut_mask = 16'h55F0; defparam \ula_|zx_keyboard_|keys[7][3]~112 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X27_Y21_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][3]~113 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][3]~113_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|keys[7][3]~112_combout & (\ula_|zx_keyboard_|keys[0][0]~15_combout & !\ula_|zx_keyboard_|extended~q ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|zx_keyboard_|keys[7][3]~112_combout ), - .datac(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .datad(\ula_|zx_keyboard_|extended~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][3]~113_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][3]~113 .lut_mask = 16'h0040; -defparam \ula_|zx_keyboard_|keys[7][3]~113 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y20_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][3]~114 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][3]~114_combout = (\ula_|zx_keyboard_|keys[7][3]~113_combout & ((!\ula_|zx_keyboard_|keys[0][4]~111_combout ))) # (!\ula_|zx_keyboard_|keys[7][3]~113_combout & (\ula_|zx_keyboard_|keys[7][3]~q )) - - .dataa(gnd), - .datab(\ula_|zx_keyboard_|keys[7][3]~113_combout ), - .datac(\ula_|zx_keyboard_|keys[7][3]~q ), - .datad(\ula_|zx_keyboard_|keys[0][4]~111_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][3]~114_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][3]~114 .lut_mask = 16'h30FC; -defparam \ula_|zx_keyboard_|keys[7][3]~114 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y20_N9 +// Location: FF_X29_Y9_N15 dffeas \ula_|zx_keyboard_|keys[7][3] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[7][3]~114_combout ), + .d(\ula_|zx_keyboard_|keys[7][3]~112_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -52321,79 +42219,96 @@ defparam \ula_|zx_keyboard_|keys[7][3] .is_wysiwyg = "true"; defparam \ula_|zx_keyboard_|keys[7][3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X27_Y21_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~109 ( +// Location: LCCOMB_X28_Y9_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|Selector13~0 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][3]~109_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [5]))) +// \ula_|zx_keyboard_|Selector13~0_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|shifted~q )) - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), + .datab(\ula_|zx_keyboard_|shifted~q ), + .datac(gnd), + .datad(\ula_|zx_keyboard_|released~q ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][3]~109_combout ), + .combout(\ula_|zx_keyboard_|Selector13~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][3]~109 .lut_mask = 16'h1000; -defparam \ula_|zx_keyboard_|keys[6][3]~109 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|Selector13~0 .lut_mask = 16'hFF44; +defparam \ula_|zx_keyboard_|Selector13~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X27_Y21_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~110 ( +// Location: LCCOMB_X29_Y9_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~113 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][3]~110_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (((\ula_|zx_keyboard_|keys[6][3]~109_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|keys[7][2]~32_combout ))) +// \ula_|zx_keyboard_|keys[6][3]~113_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [2]))) - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|zx_keyboard_|keys[7][2]~32_combout ), - .datac(\ula_|zx_keyboard_|keys[6][3]~109_combout ), + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][3]~113_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][3]~113 .lut_mask = 16'h0040; +defparam \ula_|zx_keyboard_|keys[6][3]~113 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~114 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][3]~114_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|zx_keyboard_|keys[6][3]~113_combout )) # (!\ula_|ps2_keyboard_|shiftreg [0] & (((\ula_|ps2_keyboard_|shiftreg [2] & \ula_|zx_keyboard_|keys[7][2]~30_combout )))) + + .dataa(\ula_|zx_keyboard_|keys[6][3]~113_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|zx_keyboard_|keys[7][2]~30_combout ), .datad(\ula_|ps2_keyboard_|shiftreg [0]), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][3]~110_combout ), + .combout(\ula_|zx_keyboard_|keys[6][3]~114_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][3]~110 .lut_mask = 16'hF088; -defparam \ula_|zx_keyboard_|keys[6][3]~110 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[6][3]~114 .lut_mask = 16'hAAC0; +defparam \ula_|zx_keyboard_|keys[6][3]~114 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y21_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~137 ( +// Location: LCCOMB_X29_Y9_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~135 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][3]~137_combout = (\ula_|zx_keyboard_|extended~q ) # (((!\ula_|zx_keyboard_|keys[0][0]~15_combout ) # (!\ula_|ps2_keyboard_|shiftreg [3])) # (!\ula_|zx_keyboard_|keys[6][3]~110_combout )) +// \ula_|zx_keyboard_|keys[6][3]~135_combout = ((\ula_|zx_keyboard_|extended~q ) # ((!\ula_|zx_keyboard_|keys[6][3]~114_combout ) # (!\ula_|ps2_keyboard_|shiftreg [3]))) # (!\ula_|zx_keyboard_|keys[0][0]~13_combout ) - .dataa(\ula_|zx_keyboard_|extended~q ), - .datab(\ula_|zx_keyboard_|keys[6][3]~110_combout ), + .dataa(\ula_|zx_keyboard_|keys[0][0]~13_combout ), + .datab(\ula_|zx_keyboard_|extended~q ), .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|zx_keyboard_|keys[0][0]~15_combout ), + .datad(\ula_|zx_keyboard_|keys[6][3]~114_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][3]~137_combout ), + .combout(\ula_|zx_keyboard_|keys[6][3]~135_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][3]~137 .lut_mask = 16'hBFFF; -defparam \ula_|zx_keyboard_|keys[6][3]~137 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[6][3]~135 .lut_mask = 16'hDFFF; +defparam \ula_|zx_keyboard_|keys[6][3]~135 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y21_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~138 ( +// Location: LCCOMB_X29_Y9_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~136 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][3]~138_combout = (\ula_|ps2_keyboard_|shiftreg [1] & ((\ula_|zx_keyboard_|keys[6][3]~137_combout & ((\ula_|zx_keyboard_|keys[6][3]~q ))) # (!\ula_|zx_keyboard_|keys[6][3]~137_combout & -// (!\ula_|zx_keyboard_|Selector13~0_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [1] & (((\ula_|zx_keyboard_|keys[6][3]~q )))) +// \ula_|zx_keyboard_|keys[6][3]~136_combout = (\ula_|zx_keyboard_|keys[6][3]~135_combout & (((\ula_|zx_keyboard_|keys[6][3]~q )))) # (!\ula_|zx_keyboard_|keys[6][3]~135_combout & ((\ula_|ps2_keyboard_|shiftreg [1] & +// (!\ula_|zx_keyboard_|Selector13~0_combout )) # (!\ula_|ps2_keyboard_|shiftreg [1] & ((\ula_|zx_keyboard_|keys[6][3]~q ))))) - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|zx_keyboard_|Selector13~0_combout ), + .dataa(\ula_|zx_keyboard_|Selector13~0_combout ), + .datab(\ula_|zx_keyboard_|keys[6][3]~135_combout ), .datac(\ula_|zx_keyboard_|keys[6][3]~q ), - .datad(\ula_|zx_keyboard_|keys[6][3]~137_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][3]~138_combout ), + .combout(\ula_|zx_keyboard_|keys[6][3]~136_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][3]~138 .lut_mask = 16'hF072; -defparam \ula_|zx_keyboard_|keys[6][3]~138 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[6][3]~136 .lut_mask = 16'hD1F0; +defparam \ula_|zx_keyboard_|keys[6][3]~136 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y21_N29 +// Location: FF_X29_Y9_N9 dffeas \ula_|zx_keyboard_|keys[6][3] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[6][3]~138_combout ), + .d(\ula_|zx_keyboard_|keys[6][3]~136_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -52409,247 +42324,42 @@ defparam \ula_|zx_keyboard_|keys[6][3] .is_wysiwyg = "true"; defparam \ula_|zx_keyboard_|keys[6][3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~2 ( +// Location: LCCOMB_X29_Y9_N30 +cycloneive_lcell_comb \D[3]~56 ( // Equation(s): -// \ula_|zx_keyboard_|key_row~2_combout = (\z80_|address_pins_|DFFE_apin_latch [14]) # ((!\ula_|zx_keyboard_|keys[6][3]~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) +// \D[3]~56_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\z80_|address_pins_|abus[15]~22_combout )) # (!\ula_|zx_keyboard_|keys[7][3]~q ))) # (!\z80_|address_pins_|abus[14]~23_combout & (!\ula_|zx_keyboard_|keys[6][3]~q & +// ((\z80_|address_pins_|abus[15]~22_combout ) # (!\ula_|zx_keyboard_|keys[7][3]~q )))) - .dataa(gnd), - .datab(\z80_|address_pins_|DFFE_apin_latch [14]), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\ula_|zx_keyboard_|keys[6][3]~q ), + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\ula_|zx_keyboard_|keys[7][3]~q ), + .datac(\ula_|zx_keyboard_|keys[6][3]~q ), + .datad(\z80_|address_pins_|abus[15]~22_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|key_row~2_combout ), + .combout(\D[3]~56_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|key_row~2 .lut_mask = 16'hCFFF; -defparam \ula_|zx_keyboard_|key_row~2 .sum_lutc_input = "datac"; +defparam \D[3]~56 .lut_mask = 16'hAF23; +defparam \D[3]~56 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N8 -cycloneive_lcell_comb \D[3]~68 ( +// Location: LCCOMB_X28_Y7_N30 +cycloneive_lcell_comb \D[3]~57 ( // Equation(s): -// \D[3]~68_combout = (\D[3]~67_combout & (\ula_|zx_keyboard_|key_row~2_combout & ((\z80_|address_pins_|abus[15]~22_combout ) # (!\ula_|zx_keyboard_|keys[7][3]~q )))) +// \D[3]~57_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[3]~55_combout & (\D[3]~54_combout & \D[3]~56_combout ))) - .dataa(\z80_|address_pins_|abus[15]~22_combout ), - .datab(\D[3]~67_combout ), - .datac(\ula_|zx_keyboard_|keys[7][3]~q ), - .datad(\ula_|zx_keyboard_|key_row~2_combout ), + .dataa(\D[3]~55_combout ), + .datab(\D[3]~54_combout ), + .datac(\z80_|address_pins_|abus[0]~16_combout ), + .datad(\D[3]~56_combout ), .cin(gnd), - .combout(\D[3]~68_combout ), + .combout(\D[3]~57_combout ), .cout()); // synopsys translate_off -defparam \D[3]~68 .lut_mask = 16'h8C00; -defparam \D[3]~68 .sum_lutc_input = "datac"; +defparam \D[3]~57 .lut_mask = 16'hF8F0; +defparam \D[3]~57 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N30 -cycloneive_lcell_comb \D[3]~69 ( -// Equation(s): -// \D[3]~69_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[3]~65_combout & (\D[3]~66_combout & \D[3]~68_combout ))) - - .dataa(\D[3]~65_combout ), - .datab(\z80_|address_pins_|abus[0]~16_combout ), - .datac(\D[3]~66_combout ), - .datad(\D[3]~68_combout ), - .cin(gnd), - .combout(\D[3]~69_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~69 .lut_mask = 16'hECCC; -defparam \D[3]~69 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y11_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a19 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[3]~96_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_first_bit_number = 3; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y15_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a3 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[3]~96_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; -// synopsys translate_on - -// Location: M9K_X22_Y18_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a11 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[3]~96_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X23_Y15_N14 -cycloneive_lcell_comb \D[3]~73 ( -// Equation(s): -// \D[3]~73_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ) # (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout & ((!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ), - .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .cin(gnd), - .combout(\D[3]~73_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~73 .lut_mask = 16'hCCE2; -defparam \D[3]~73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y5_N0 +// Location: M9K_X33_Y14_N0 cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a27 ( .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), .portare(vcc), @@ -52665,7 +42375,7 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a27 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[3]~96_combout }), + .portadatain({\D[3]~74_combout }), .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , \z80_|address_pins_|abus[0]~16_combout }), @@ -52706,25 +42416,274 @@ defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init1 = 20 defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N16 -cycloneive_lcell_comb \D[3]~74 ( -// Equation(s): -// \D[3]~74_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\D[3]~73_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ))) # (!\D[3]~73_combout & -// (\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\D[3]~73_combout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ), - .datac(\D[3]~73_combout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ), - .cin(gnd), - .combout(\D[3]~74_combout ), - .cout()); +// Location: M9K_X22_Y14_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a3 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[3]~74_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), + .portbdataout()); // synopsys translate_off -defparam \D[3]~74 .lut_mask = 16'hF858; -defparam \D[3]~74 .sum_lutc_input = "datac"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; // synopsys translate_on -// Location: M9K_X22_Y19_N0 +// Location: M9K_X22_Y13_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a19 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[3]~74_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_first_bit_number = 3; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X23_Y14_N26 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6 .lut_mask = 16'hF4A4; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y16_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a11 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[3]~74_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X23_Y14_N22 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout & +// (\ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout )) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ))))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7 .lut_mask = 16'hDAD0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y20_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a3 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h7BBD7F79FFE0AB8FC33758D1C1145DDD6311CF69FFFDF62EDD236FC6A0358FA2B4B15EB89456517DFF58F68BDADB95B5F764CAE7E7C7E7D70CADB8FFD8F9A72BFBB9EB400590D7F939FF5A70A29817DC2CC29B679B2D7146BD21D47EF06F7D5EAF72F66DC666B0726D66FD941AD9BC6D758D5EC24DFEBA64871D6B86D37DF1DFBFF05FBD6AD8CA62C6CBE43BDBFD99E9EB6DD724D235FBEA9FE7D6767D811C40681A00AF8D864D8BB6D2A0916C8A93250A76B8A977F82E8FDFBE68F8E0F8DF237CA976FE488D1069D687A6F1D68A70F37CAAA367A74CBB75D3A6FFB4B1E8D4B7F7F22D2FE1509BDF80E6DD7B717D7E9C6531C3A86BE9F1D7A6AFD5BFB7A37A60; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h8AB3B7FDEE7B9CC735FCCE93E3AC1AAAA691AD6350E57F1F5773302B6F36F63D130E0574D6BB44B2C0D7A907702A748D0BA50F8FA5437ACD3B343C35039F44D19CD4E55E6CB00410842B02A7FD105706DF9E2A1FA025005632A0CC080400D280CCCA0665222D038CC873351A21B23939A98CC08803282189C8440D40CD40462421A40982C046D22C10146484345CAF7BC828BFE79DFBE3C631CBF660C487EBB759BD7F8DE9E0F27A65DE5245BEB8F7829C36F0D136168F97C2BD77D649A39EB4DDB3A42AC80797FDEF4DE3EEF7ED8C7307E4CE6A6317F7BF25D077BBF03AEA3363B065F7D671322D6BFB2B8759433929CEC27E3FD7741292A4A5AF02703CC4E3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'hFD5CB07B6C729B510A78BEC5F7C7A1E7809F1976D0DD3615C1D27D2DF596BFE7A8BCDC2E6655185CC45008B39EFD1FA6E9F5E816114F93E1E7A2A27C72C7349F3497229CB9044B6E7A7861A04A712AAF29EFBD393727F1F3FC2AA1E6CF571457F0A09C47F23F20FE2AABF5FD3ABE6167E5FD36E1D9735BBD5375C1F79BD0424ECF133BF47B9D3DA46DD6DBF3A8ADCDD3DF1176D2FE23447DFC65E1DD7BF3BE5E1C9DCD8EBB9D36AF570CF25CDD16F645D1DE9F9EE575E3A2B91D5659FC131CE3DCD4560015805B13AC0290001EF8261B7E4EB867C828D9777FFF47B6903008DDD7D77EF5E2C6D7220BE64B3C6E9EF22AFDFCC8005C2FFFFA3AB9AD1ADFC0AFE7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h06ABC52D5DBEF57EEB3311A9D85D253B44E250E1566BED57C6DBEB2ABFD1ADF6FF4DEBFBDEB376DF68D5EEDB5EB4D5AB5B79745D76CD8ADC59CB30C8AA33E1551D2FCA8DCB43C5356BAE638588C302868CE1161CACADFEF7696F8C3AA82EC16F47A8EA413A2DCF09B996582318DBF3C4711871B3BC0404EC45252A485234A663C1FFFB3487617BE24FD79501DE05F1A341B89EC82FD5702497FD866639C0DE08B383E6E7C3B310E1F7FF595C5DF6F0E9A9FFFBE16D3FFBE82C1E0051F1E060D500812F408CC6501331852531B04480021D9220D4903A41404312032840153FE9CC8070206B8245AC240020752EBC2BEF3E74AB288F360C239C4AFAE93F68775A; +// synopsys translate_on + +// Location: M9K_X22_Y32_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a11 ( .portawe(vcc), .portare(vcc), @@ -52732,7 +42691,7 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a11 ( .portbwe(gnd), .portbre(vcc), .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .clk1(gnd), .ena0(\z80_|address_pins_|abus[13]~20_combout ), .ena1(vcc), @@ -52782,9 +42741,9 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 204 defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h420539B476E305B8200E47DFAAE8D5D1D0724DCC3FD72C4F8DE54622A1DD1BA78CA3CE9F24BEFA9E2BB9D89B423C327C8E050114401A62FDCD2054E166C0005F7941B61372AC884EE60A372057B59CFF30A6020B875C06E7C5FBDF9A91F8F0588ED67F67AA66B0674CD240410F613700B8DFE7F8837F88FF4520002E4BFD7FA2768008002000002624793100811F43BC315A6004052671392B47FEB7F5DC90E62175C7B8FC48FCC916D46F9315DFDECBE43E5F03D7D27F97E09E4700AA694552A1FF3BE5E159FFDDEB2FBECAEB87BBCC5FCF6E23D77E4DD4C9DEBC93C10F636326FAFE3BE30DFAF7B9E7A5FFE44BF314DAA1C1529CDBFFE9D94EB11A9F68D4DF; // synopsys translate_on -// Location: M9K_X22_Y23_N0 +// Location: M9K_X22_Y22_N0 cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a11 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), @@ -52798,7 +42757,7 @@ cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a11 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[3]~96_combout }), + .portadatain({\D[3]~74_combout }), .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , \z80_|address_pins_|abus[0]~16_combout }), @@ -52855,103 +42814,9 @@ defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 20 defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N24 -cycloneive_lcell_comb \D[3]~70 ( -// Equation(s): -// \D[3]~70_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\z80_|address_pins_|abus[14]~23_combout & ((\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ))) # (!\z80_|address_pins_|abus[14]~23_combout & -// (\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\z80_|address_pins_|abus[14]~23_combout )) - - .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\z80_|address_pins_|abus[14]~23_combout ), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ), - .cin(gnd), - .combout(\D[3]~70_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~70 .lut_mask = 16'hEC64; -defparam \D[3]~70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y21_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a3 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h7BBD7F79FFE0AB8FC33758D1C1145DDD6311CF69FFFDF62EDD236FC6A0358FA2B4B15EB89456517DFF58F68BDADB95B5F764CAE7E7C7E7D70CADB8FFD8F9A72BFBB9EB400590D7F939FF5A70A29817DC2CC29B679B2D7146BD21D47EF06F7D5EAF72F66DC666B0726D66FD941AD9BC6D758D5EC24DFEBA64871D6B86D37DF1DFBFF05FBD6AD8CA62C6CBE43BDBFD99E9EB6DD724D235FBEA9FE7D6767D811C40681A00AF8D864D8BB6D2A0916C8A93250A76B8A977F82E8FDFBE68F8E0F8DF237CA976FE488D1069D687A6F1D68A70F37CAAA367A74CBB75D3A6FFB4B1E8D4B7F7F22D2FE1509BDF80E6DD7B717D7E9C6531C3A86BE9F1D7A6AFD5BFB7A37A60; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h8AB3B7FDEE7B9CC735FCCE93E3AC1AAAA691AD6350E57F1F5773302B6F36F63D130E0574D6BB44B2C0D7A907702A748D0BA50F8FA5437ACD3B343C35039F44D19CD4E55E6CB00410842B02A7FD105706DF9E2A1FA025005632A0CC080400D280CCCA0665222D038CC873351A21B23939A98CC08803282189C8440D40CD40462421A40982C046D22C10146484345CAF7BC828BFE79DFBE3C631CBF660C487EBB759BD7F8DE9E0F27A65DE5245BEB8F7829C36F0D136168F97C2BD77D649A39EB4DDB3A42AC80797FDEF4DE3EEF7ED8C7307E4CE6A6317F7BF25D077BBF03AEA3363B065F7D671322D6BFB2B8759433929CEC27E3FD7741292A4A5AF02703CC4E3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'hFD5CB07B6C729B510A78BEC5F7C7A1E7809F1976D0DD3615C1D27D2DF596BFE7A8BCDC2E6655185CC45008B39EFD1FA6E9F5E816114F93E1E7A2A27C72C7349F3497229CB9044B6E7A7861A04A712AAF29EFBD393727F1F3FC2AA1E6CF571457F0A09C47F23F20FE2AABF5FD3ABE6167E5FD36E1D9735BBD5375C1F79BD0424ECF133BF47B9D3DA46DD6DBF3A8ADCDD3DF1176D2FE23447DFC65E1DD7BF3BE5E1C9DCD8EBB9D36AF570CF25CDD16F645D1DE9F9EE575E3A2B91D5659FC131CE3DCD4560015805B13AC0290001EF8261B7E4EB867C828D9777FFF47B6903008DDD7D77EF5E2C6D7220BE64B3C6E9EF22AFDFCC8005C2FFFFA3AB9AD1ADFC0AFE7; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h06ABC52D5DBEF57EEB3311A9D85D253B44E250E1566BED57C6DBEB2ABFD1ADF6FF4DEBFBDEB376DF68D5EEDB5EB4D5AB5B79745D76CD8ADC59CB30C8AA33E1551D2FCA8DCB43C5356BAE638588C302868CE1161CACADFEF7696F8C3AA82EC16F47A8EA413A2DCF09B996582318DBF3C4711871B3BC0404EC45252A485234A663C1FFFB3487617BE24FD79501DE05F1A341B89EC82FD5702497FD866639C0DE08B383E6E7C3B310E1F7FF595C5DF6F0E9A9FFFBE16D3FFBE82C1E0051F1E060D500812F408CC6501331852531B04480021D9220D4903A41404312032840153FE9CC8070206B8245AC240020752EBC2BEF3E74AB288F360C239C4AFAE93F68775A; -// synopsys translate_on - -// Location: LCCOMB_X23_Y15_N22 -cycloneive_lcell_comb \D[3]~71 ( -// Equation(s): -// \D[3]~71_combout = (\z80_|address_pins_|abus[15]~22_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout $ (((\D[3]~70_combout ))))) # (!\z80_|address_pins_|abus[15]~22_combout & -// (((\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout & !\D[3]~70_combout )))) - - .dataa(\z80_|address_pins_|abus[15]~22_combout ), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ), - .datad(\D[3]~70_combout ), - .cin(gnd), - .combout(\D[3]~71_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~71 .lut_mask = 16'h22D8; -defparam \D[3]~71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y31_N0 +// Location: M9K_X22_Y30_N0 cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a3 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), @@ -52965,7 +42830,7 @@ cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a3 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[3]~96_combout }), + .portadatain({\D[3]~74_combout }), .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , \z80_|address_pins_|abus[0]~16_combout }), @@ -53021,95 +42886,113 @@ defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 204 defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h022388704B6887014BD84185680166815764AC0148D308813FFFFFFC0000000003228A304BA085014BFC40816C0166915375AC0140D308013FFFFFFC40000000432289294EB08F014A1C40816C016681537DA80140D10E01400000017FFFFFFE406281154FB08D014A0040894C016299437DB00140D10F01400000037FFFFFFE4062A13149A88D814BE0429146016EA14179B001405107017FFFFFFF0000000043E0812549C889814BE0528146016C814179924140511F413FFFFFFE0000000043E881314EE881814A00468147436C814159100100513F0000000000FFFFFFFF4B6883014EA881814800668147C22C814019900100003E0000000000FFFFFFFF; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N20 -cycloneive_lcell_comb \D[3]~72 ( +// Location: LCCOMB_X23_Y14_N24 +cycloneive_lcell_comb \Selector3~1 ( // Equation(s): -// \D[3]~72_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\D[3]~70_combout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[3]~70_combout & (!\D[3]~71_combout & -// \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout )) # (!\D[3]~70_combout & (\D[3]~71_combout )))) +// \Selector3~1_combout = (\Selector3~0_combout & (((\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout )) # (!\z80_|address_pins_|abus[14]~23_combout ))) # (!\Selector3~0_combout & (\z80_|address_pins_|abus[14]~23_combout & +// ((\ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout )))) - .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\D[3]~70_combout ), - .datac(\D[3]~71_combout ), + .dataa(\Selector3~0_combout ), + .datab(\z80_|address_pins_|abus[14]~23_combout ), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ), .datad(\ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ), .cin(gnd), - .combout(\D[3]~72_combout ), + .combout(\Selector3~1_combout ), .cout()); // synopsys translate_off -defparam \D[3]~72 .lut_mask = 16'h9C98; -defparam \D[3]~72 .sum_lutc_input = "datac"; +defparam \Selector3~1 .lut_mask = 16'hE6A2; +defparam \Selector3~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N28 -cycloneive_lcell_comb \D[3]~108 ( +// Location: LCCOMB_X23_Y14_N16 +cycloneive_lcell_comb \Selector3~2 ( // Equation(s): -// \D[3]~108_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (\D[3]~74_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\D[3]~72_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & -// (\D[3]~74_combout )))) +// \Selector3~2_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\Selector3~1_combout )))) # (!\z80_|address_pins_|abus[14]~23_combout & ((\Selector3~1_combout & ((\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ))) # +// (!\Selector3~1_combout & (\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout )))) + + .dataa(\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ), + .datab(\z80_|address_pins_|abus[14]~23_combout ), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ), + .datad(\Selector3~1_combout ), + .cin(gnd), + .combout(\Selector3~2_combout ), + .cout()); +// synopsys translate_off +defparam \Selector3~2 .lut_mask = 16'hFC22; +defparam \Selector3~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y14_N10 +cycloneive_lcell_comb \D[3]~85 ( +// Equation(s): +// \D[3]~85_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\Selector3~2_combout +// ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout )))) .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), - .datab(\D[3]~74_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\D[3]~72_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout ), + .datad(\Selector3~2_combout ), .cin(gnd), - .combout(\D[3]~108_combout ), + .combout(\D[3]~85_combout ), .cout()); // synopsys translate_off -defparam \D[3]~108 .lut_mask = 16'hDC8C; -defparam \D[3]~108 .sum_lutc_input = "datac"; +defparam \D[3]~85 .lut_mask = 16'hF4B0; +defparam \D[3]~85 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N4 -cycloneive_lcell_comb \D[3]~95 ( +// Location: LCCOMB_X23_Y14_N2 +cycloneive_lcell_comb \D[3]~73 ( // Equation(s): -// \D[3]~95_combout = ((\Equal2~0_combout & (\D[3]~69_combout )) # (!\Equal2~0_combout & ((\D[3]~108_combout )))) # (!\Equal2~1_combout ) +// \D[3]~73_combout = ((\Equal2~0_combout & (\D[3]~57_combout )) # (!\Equal2~0_combout & ((\D[3]~85_combout )))) # (!\Equal2~1_combout ) - .dataa(\D[3]~69_combout ), + .dataa(\D[3]~57_combout ), .datab(\Equal2~1_combout ), .datac(\Equal2~0_combout ), - .datad(\D[3]~108_combout ), + .datad(\D[3]~85_combout ), .cin(gnd), - .combout(\D[3]~95_combout ), + .combout(\D[3]~73_combout ), .cout()); // synopsys translate_off -defparam \D[3]~95 .lut_mask = 16'hBFB3; -defparam \D[3]~95 .sum_lutc_input = "datac"; +defparam \D[3]~73 .lut_mask = 16'hBFB3; +defparam \D[3]~73 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N26 -cycloneive_lcell_comb \D[3]~96 ( +// Location: LCCOMB_X23_Y14_N8 +cycloneive_lcell_comb \D[3]~74 ( // Equation(s): -// \D[3]~96_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\z80_|data_pins_|dout [3] & \D[3]~95_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\D[3]~95_combout )) # (!\Equal2~1_combout ))) +// \D[3]~74_combout = (\z80_|pin_control_|bus_db_pin_oe~15_combout & (\z80_|data_pins_|dout [3] & ((\D[3]~73_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout & (((\D[3]~73_combout ) # (!\Equal2~1_combout )))) - .dataa(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .dataa(\z80_|data_pins_|dout [3]), .datab(\Equal2~1_combout ), - .datac(\z80_|data_pins_|dout [3]), - .datad(\D[3]~95_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .datad(\D[3]~73_combout ), .cin(gnd), - .combout(\D[3]~96_combout ), + .combout(\D[3]~74_combout ), .cout()); // synopsys translate_off -defparam \D[3]~96 .lut_mask = 16'hF511; -defparam \D[3]~96 .sum_lutc_input = "datac"; +defparam \D[3]~74 .lut_mask = 16'hAF03; +defparam \D[3]~74 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y13_N6 +// Location: LCCOMB_X30_Y13_N16 cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] ( // Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [3] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[3]~21_combout ) # ((\D[3]~96_combout & \z80_|pin_control_|bus_db_pin_re~combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & -// (\D[3]~96_combout & (\z80_|pin_control_|bus_db_pin_re~combout ))) +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [3] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[3]~21_combout ) # ((\z80_|pin_control_|bus_db_pin_re~combout & \D[3]~74_combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & +// (\z80_|pin_control_|bus_db_pin_re~combout & ((\D[3]~74_combout )))) .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(\D[3]~96_combout ), - .datac(\z80_|pin_control_|bus_db_pin_re~combout ), - .datad(\z80_|bus_control_|db[3]~21_combout ), + .datab(\z80_|pin_control_|bus_db_pin_re~combout ), + .datac(\z80_|bus_control_|db[3]~21_combout ), + .datad(\D[3]~74_combout ), .cin(gnd), .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [3]), .cout()); // synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] .lut_mask = 16'hEAC0; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] .lut_mask = 16'hECA0; defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y13_N7 +// Location: FF_X30_Y13_N17 dffeas \z80_|data_pins_|dout[3] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [3]), @@ -53128,44 +43011,903 @@ defparam \z80_|data_pins_|dout[3] .is_wysiwyg = "true"; defparam \z80_|data_pins_|dout[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N4 +// Location: LCCOMB_X29_Y13_N20 cycloneive_lcell_comb \z80_|bus_control_|db[3]~20 ( // Equation(s): // \z80_|bus_control_|db[3]~20_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [3]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) - .dataa(\z80_|execute_|ctl_bus_db_oe~combout ), - .datab(\z80_|data_pins_|dout [3]), - .datac(gnd), - .datad(\z80_|bus_control_|db[0]~4_combout ), + .dataa(gnd), + .datab(\z80_|bus_control_|db[0]~4_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~combout ), + .datad(\z80_|data_pins_|dout [3]), .cin(gnd), .combout(\z80_|bus_control_|db[3]~20_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[3]~20 .lut_mask = 16'hDD00; +defparam \z80_|bus_control_|db[3]~20 .lut_mask = 16'hCC0C; defparam \z80_|bus_control_|db[3]~20 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y10_N0 +// Location: LCCOMB_X30_Y17_N30 cycloneive_lcell_comb \z80_|bus_control_|db[3]~21 ( // Equation(s): // \z80_|bus_control_|db[3]~21_combout = ((\z80_|bus_control_|db[3]~20_combout & ((\z80_|alu_control_|db[3]~35_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) .dataa(\z80_|bus_control_|db[0]~6_combout ), - .datab(\z80_|bus_control_|db[3]~20_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|alu_control_|db[3]~35_combout ), + .datab(\z80_|alu_control_|db[3]~35_combout ), + .datac(\z80_|bus_control_|db[3]~20_combout ), + .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), .cin(gnd), .combout(\z80_|bus_control_|db[3]~21_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[3]~21 .lut_mask = 16'hDD5D; +defparam \z80_|bus_control_|db[3]~21 .lut_mask = 16'hD5F5; defparam \z80_|bus_control_|db[3]~21 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X34_Y10_N1 -dffeas \z80_|ir_|opcode[3] ( +// Location: LCCOMB_X30_Y17_N12 +cycloneive_lcell_comb \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 ( +// Equation(s): +// \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout = (\z80_|bus_control_|db[4]~19_combout & \z80_|bus_control_|db[3]~21_combout ) + + .dataa(gnd), + .datab(\z80_|bus_control_|db[4]~19_combout ), + .datac(\z80_|bus_control_|db[3]~21_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 .lut_mask = 16'hC0C0; +defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y17_N13 +dffeas \z80_|interrupts_|im2 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|bus_control_|db[3]~21_combout ), + .d(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_im_we~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|interrupts_|im2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|interrupts_|im2 .is_wysiwyg = "true"; +defparam \z80_|interrupts_|im2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~10 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~10_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|interrupts_|im2~q & \z80_|interrupts_|DFFE_inst44~q )) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|interrupts_|im2~q ), + .datac(\z80_|interrupts_|DFFE_inst44~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~10 .lut_mask = 16'h4040; +defparam \z80_|execute_|ctl_mRead~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_mask543_en~0 ( +// Equation(s): +// \z80_|execute_|ctl_sw_mask543_en~0_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (!\z80_|execute_|ctl_mRead~10_combout & (\z80_|pla_decode_|Equal47~0_combout & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|execute_|ctl_mRead~10_combout ), + .datac(\z80_|pla_decode_|Equal47~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_mask543_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_mask543_en~0 .lut_mask = 16'h1000; +defparam \z80_|execute_|ctl_sw_mask543_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N24 +cycloneive_lcell_comb \z80_|alu_control_|db[7]~16 ( +// Equation(s): +// \z80_|alu_control_|db[7]~16_combout = (\z80_|alu_flags_|DFFE_inst_latch_sf~q & (!\z80_|alu_|db[7]~12_combout & ((\z80_|execute_|ctl_sw_2u~7_combout )))) # (!\z80_|alu_flags_|DFFE_inst_latch_sf~q & ((\z80_|execute_|ctl_flags_oe~2_combout ) # +// ((!\z80_|alu_|db[7]~12_combout & \z80_|execute_|ctl_sw_2u~7_combout )))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), + .datab(\z80_|alu_|db[7]~12_combout ), + .datac(\z80_|execute_|ctl_flags_oe~2_combout ), + .datad(\z80_|execute_|ctl_sw_2u~7_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[7]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[7]~16 .lut_mask = 16'h7350; +defparam \z80_|alu_control_|db[7]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N6 +cycloneive_lcell_comb \z80_|alu_control_|db[7]~17 ( +// Equation(s): +// \z80_|alu_control_|db[7]~17_combout = (!\z80_|alu_control_|db[7]~16_combout & (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & ((\z80_|reg_file_|gdfx_temp0[7]~91_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), + .datab(\z80_|alu_control_|db[7]~16_combout ), + .datac(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[7]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[7]~17 .lut_mask = 16'h2030; +defparam \z80_|alu_control_|db[7]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N12 +cycloneive_lcell_comb \z80_|alu_control_|db[7]~18 ( +// Equation(s): +// \z80_|alu_control_|db[7]~18_combout = (\z80_|alu_control_|db[7]~17_combout & (((!\z80_|execute_|ctl_sw_mask543_en~0_combout & \z80_|bus_control_|db[7]~7_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) + + .dataa(\z80_|execute_|ctl_sw_mask543_en~0_combout ), + .datab(\z80_|bus_control_|db[7]~7_combout ), + .datac(\z80_|execute_|ctl_sw_1d~7_combout ), + .datad(\z80_|alu_control_|db[7]~17_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[7]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[7]~18 .lut_mask = 16'h4F00; +defparam \z80_|alu_control_|db[7]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N26 +cycloneive_lcell_comb \z80_|alu_control_|db[7]~19 ( +// Equation(s): +// \z80_|alu_control_|db[7]~19_combout = (\z80_|alu_control_|db[7]~18_combout ) # (!\z80_|alu_control_|db[6]~11_combout ) + + .dataa(\z80_|alu_control_|db[7]~18_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|alu_control_|db[6]~11_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[7]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[7]~19 .lut_mask = 16'hAAFF; +defparam \z80_|alu_control_|db[7]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N28 +cycloneive_lcell_comb \z80_|bus_control_|db[7]~5 ( +// Equation(s): +// \z80_|bus_control_|db[7]~5_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[7]~19_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datab(\z80_|bus_control_|db[0]~4_combout ), + .datac(gnd), + .datad(\z80_|alu_control_|db[7]~19_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[7]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[7]~5 .lut_mask = 16'hCC44; +defparam \z80_|bus_control_|db[7]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N2 +cycloneive_lcell_comb \D[5]~67 ( +// Equation(s): +// \D[5]~67_combout = (!\z80_|memory_ifc_|nIORQ_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\z80_|memory_ifc_|nRD_out~2_combout & !\z80_|memory_ifc_|nWR_out~0_combout ))) + + .dataa(\z80_|memory_ifc_|nIORQ_out~0_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|memory_ifc_|nRD_out~2_combout ), + .datad(\z80_|memory_ifc_|nWR_out~0_combout ), + .cin(gnd), + .combout(\D[5]~67_combout ), + .cout()); +// synopsys translate_off +defparam \D[5]~67 .lut_mask = 16'h0040; +defparam \D[5]~67 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y21_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a7 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[7]~80_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081; +// synopsys translate_on + +// Location: M9K_X33_Y20_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a23 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[7]~80_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_first_bit_number = 7; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N10 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout ) # +// (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout & +// ((!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14 .lut_mask = 16'hCCE2; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y18_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a31 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[7]~80_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a31_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_first_bit_number = 7; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y16_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a15 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[7]~80_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N24 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15_combout = (\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ) # +// ((!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14_combout & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & +// \ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14_combout ), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15 .lut_mask = 16'hDA8A; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y29_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a15 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h3C0000000000000000000000000000000000000000000000000000000000000080000000000002000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFB91060128E2D09899B4D10A148392808351AD282E76190E029FDC286449331D89080802222C0D04D1121484041D21084C223B0A12EBE72083D81421B93CA9589A04864A853089602E536320C2A5944831907110C246020089C76EE701A4E23964C6586008731635460418000008202040C300110000FCE7E12403749F8C6AB8F69167210EF8A4B8228710884C5C47A9986E8840C02862C088C36E19CF1D315; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h03020CCE064769B15020A6030880234C64E9BEF8E98A81489083A026140D648906E5AD6C882882990A40D293FED064710CB226CDA0330D7B189B344442EC35E3763C75FA1DB107B865E5B8F7B95E77F222244C6BDC1879C0562EF779BE0009465775469089F04C623E19317B486F653C1C22CA642CD685C10EE47EDD66C8C226C7C57F084106FB3B8B1E47463C0088D11104F23C180222A0AA22A22882A202A00000000288964258156302504F5F660C054DEDCA20CC201A4074192601E376C9596CD8B4B568A4DFEF3DBF8027A3422A56A2C003E514582104BF8D6B5D80BB397FBBEC46E8B3CAEBE0100275A1092081D0C1E5716DF09CFEEC00AD800529E1A8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h873CB568FC3F09080F4400DAC600092017210911A6081DCC4979244124815884AE6302C4BE6BA8C22A084803225A0855ABBBC528B1CA2456A4951A53C1209153CFC3000F43632B49C39723270C604B184D1940F1B2A04459BEB088666843BB38C23A8D170CED981891256A2C1D9B31C0F040202103900E6765976089DB8DE16E0001022EC10015E263787F7E581EF83F062200C626EC4E19021840D9C112400C4B987A78AE1BF80005EF370C0739371E0D3E5CF1E3677332370BB98D1831B30F7D8CDC0131C444798F040DC0116E2C4336B0166109A15D1FCC7EDE31EB23862203C11245EE31E38E6DEF2188BE2068F3C716E10317783020D8EF5C256774BA0E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h1B9CE2DA363196DC20007FF5554FC631286DC716B048384C26510685218DF9E6C629E6050C619658692170C1022C2232C965C92C189020C705873084858910322166D72DC524870C422BBFFD4808A7032B088DE3000B853800736C8E9968C19A4B72C08871D2413188E4829219C38C2025920480D64856902E4D4D60B640C833C14D536A45D144B244C24A290076E58CC2E64E4A2DC4C5939C4C2DDBD1B918B231248625B2C0DD0F07A27A111CB80A48808C7C21C205029100010400228BB3BDFF7DCCEF40196C8381658D8840043B119B86A46247665810E2203000141023C366CB633B3376DC625DA8A0856C484392B779E1BA4088EDB4A6CDB9BD46DCC0B2; +// synopsys translate_on + +// Location: M9K_X33_Y23_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a15 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(gnd), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[7]~80_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_first_bit_number = 7; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y24_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a7 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[7]~80_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_first_bit_number = 7; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h000000000000000000000000FFFFFFFFC0810207C0001A176020155177486D89000000000000000000000000FFFFFFFF80000003C0000217724019F17748EDC900000000000000000000000000000001BF7EFDF9400406B17A400BF57748AD81000000000000000000000000000000013F7EFDF940041EB1724218157749A7910000000000000000000000003F7EFDF90000000140042AF97B426C157DC9B7590000000000000000000000003F7EFDF90000000140042069600246057DC95351000000000000000000000000408102053FFFFFF95FE4084175C246896009F35100000000000000000000000040810207BFFFFFFF7FE4147177C2004960291759; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h7FE8374958F827C15FF88F91E9A80DC3629A9FC172033EC170FB0E8173F792815FE826E158F805C95FF8AF8169A80DC3629A1EC17B033BC1706B3E8173FFB0C1400826E558F805C15DF8AF9169A82DD163C21BC17B133BC1716B3781723F14C1400826E958D825815DD8AF8168482DC161229BC17A133FC171AB3781723F16E9400826E95818058179582F9160480FC162229FC17ACA39C172FB3F8152CF10A1400826E958180D8179580F05614C0DC162329BC171EB398173537F8152E310D1400826E158180D81F8580FD1612C0F41631293C173BB398D63037F81D22313D1400827E958080F01F8188FCB60A40F41435083C1723B198161834F01D67300E3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'hD4FB0D2352268F0151E680016803440977EDE98148F31101BFFFFFFF4081010750FB094B52728F0151FEC0016C034C0153EDA90148F31F013FFFFFFB4081010152F3096156DA8901503ED2016C03480173FDA00148F11F01000000013F7EFEF952E3017156DA85015022C2016C034C0153FCA00148F10F01000000013F7EFEF956B3A9115052850543C2C2116C014D2153FDA12148D11F013F7EFEF900000001469F8B3150728D0143C05A016D014C81537DA00148D11E01BF7EFEF900000001528F8F2156628D0140004E016F054481513DA181C8513E0580000007FFFFFFFF528E8B2156E28C0148024E0167676C415139B041C8513E07C0810107FFFFFFFF; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N14 +cycloneive_lcell_comb \Mux0~0 ( +// Equation(s): +// \Mux0~0_combout = (\z80_|address_pins_|abus[14]~23_combout & ((\Selector3~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout )) # (!\Selector3~0_combout & +// ((\ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout ))))) # (!\z80_|address_pins_|abus[14]~23_combout & (((\Selector3~0_combout )))) + + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout ), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout ), + .datad(\Selector3~0_combout ), + .cin(gnd), + .combout(\Mux0~0_combout ), + .cout()); +// synopsys translate_off +defparam \Mux0~0 .lut_mask = 16'hDDA0; +defparam \Mux0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y32_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a7 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h7C762E21DB2481CB6BB88C68811C76C63B18ECC1BACDC6110DCC70BC20940800C71478E35468600B01A93082C63DD073AE4181844449C08D8D56B0DCC881251C202139803D3000B2E0209DB9101160989A5916381001B0446631006064DB1B996E436E644CF6C8606F124DA230E9B66E2F46BB466E2CE068661B4B05F02F7D00CB3E518948104042F84F1840401018406877D800A00000F5122597005DA4411000800020249004081008924124080114000000020BFFFFEC638C31207B6C321407D901787004001C459326210CCE00C6AF707B84440C313110B8C4D13B2C6E06C4C088B1A9B24BEB0178C4D6C18230DF72B07A28063647CC4721026D8C711864; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h881B30810845E6D18622EC9B6236A000030986A4F0644601226000A2F220D40310438334E51C28000400B18422CA60FC42C9C03F066366ECBBB010B00B004807CC0E00DAEC3000194A52B80C606262092D84A1102410000001400010002000800200080020000800200008000800400040002004000040002000020002000801000010004002001000200008000AEE708008880C86112251B45B36C0048833B319B4C2CE6660D2C0619246C4B208BC0AD00202001E104FC30911410804201E92102B400E8004C40AD6E4614466308ABC7165AA57060A3A736A188ABB300200A10BB04344008422327B1393C43396A931B8C8C87227A6141C0E2DCC76D830B082; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h101CC0024A6C32005CCB31908842211604D8B326101118B54B188CB4D502F5F02DA65C2472B824F109BC594C2401209C01A0E59830002C73B396C6015B85A163184B56183004204267600220A061A004893E1D609106BDBB553920A011AA5AE581E08228382D54C2989BC59535528176240438C9AA757917F95C7428981A26470D1C3E528444D9B00E561C40973AE1806031C464834F03D34A11233A34B34A1D1A55A50C3384B549B64C381920140D4008004020B119D5834C10064000006001169808000200040100000002F8986E37654DDFF88E20860382DC089D4C239F6E4C3C8D784218667F524CE209881213DC91099C14744901620044C802DA414966; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h84724A241226DB4809C9A1100DE6A63984D651A2624A09420496DDC12CC10964B6E370363701B41848117683379C8422106D001BB41FB8248067301E1002C636A276585D5273AC87206840415DA74B4E9D213CAE3234B308E19608AA38250844883838649E1442A0D983F4A9094A5AD4A52D56C5D80CAC58D9645944A230091549F30426B100842A12B25160D6D991E6C8C81AFB4C644004C2140A342020D84C9001624489A10045D16C944B02763FF55405E400BADFE5BFFFFFF00000000011042250089108884888410924041204444209102084241104204108824114455292225124929249248894408541300A6DB00791E5B12FEF24037181F1901B007B; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N16 +cycloneive_lcell_comb \Mux0~1 ( +// Equation(s): +// \Mux0~1_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\Mux0~0_combout )))) # (!\z80_|address_pins_|abus[14]~23_combout & ((\Mux0~0_combout & (\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout )) # (!\Mux0~0_combout & +// ((\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ))))) + + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ), + .datac(\Mux0~0_combout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ), + .cin(gnd), + .combout(\Mux0~1_combout ), + .cout()); +// synopsys translate_off +defparam \Mux0~1 .lut_mask = 16'hE5E0; +defparam \Mux0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N22 +cycloneive_lcell_comb \D[7]~89 ( +// Equation(s): +// \D[7]~89_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [15] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\Mux0~1_combout ))))) # +// (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15_combout )) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15_combout ), + .datac(\z80_|address_pins_|DFFE_apin_latch [15]), + .datad(\Mux0~1_combout ), + .cin(gnd), + .combout(\D[7]~89_combout ), + .cout()); +// synopsys translate_off +defparam \D[7]~89 .lut_mask = 16'hCEC4; +defparam \D[7]~89 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N30 +cycloneive_lcell_comb \D[7]~72 ( +// Equation(s): +// \D[7]~72_combout = (\D[5]~67_combout & (\D[7]~89_combout & ((\z80_|data_pins_|dout [7]) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout )))) # (!\D[5]~67_combout & ((\z80_|data_pins_|dout [7]) # ((!\z80_|pin_control_|bus_db_pin_oe~15_combout )))) + + .dataa(\D[5]~67_combout ), + .datab(\z80_|data_pins_|dout [7]), + .datac(\D[7]~89_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .cin(gnd), + .combout(\D[7]~72_combout ), + .cout()); +// synopsys translate_off +defparam \D[7]~72 .lut_mask = 16'hC4F5; +defparam \D[7]~72 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N12 +cycloneive_lcell_comb \D[0]~84 ( +// Equation(s): +// \D[0]~84_combout = (\z80_|pin_control_|bus_db_pin_oe~15_combout ) # ((\z80_|memory_ifc_|nRD_out~2_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|memory_ifc_|nWR_out~0_combout ))) + + .dataa(\z80_|memory_ifc_|nRD_out~2_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .datad(\z80_|memory_ifc_|nWR_out~0_combout ), + .cin(gnd), + .combout(\D[0]~84_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~84 .lut_mask = 16'hF0F8; +defparam \D[0]~84 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N6 +cycloneive_lcell_comb \D[7]~80 ( +// Equation(s): +// \D[7]~80_combout = (\D[7]~72_combout ) # (!\D[0]~84_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\D[7]~72_combout ), + .datad(\D[0]~84_combout ), + .cin(gnd), + .combout(\D[7]~80_combout ), + .cout()); +// synopsys translate_off +defparam \D[7]~80 .lut_mask = 16'hF0FF; +defparam \D[7]~80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N12 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [7] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[7]~7_combout ) # ((\D[7]~80_combout & \z80_|pin_control_|bus_db_pin_re~combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & +// (((\D[7]~80_combout & \z80_|pin_control_|bus_db_pin_re~combout )))) + + .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datab(\z80_|bus_control_|db[7]~7_combout ), + .datac(\D[7]~80_combout ), + .datad(\z80_|pin_control_|bus_db_pin_re~combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [7]), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] .lut_mask = 16'hF888; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y13_N13 +dffeas \z80_|data_pins_|dout[7] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [7]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|data_pins_|dout [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|data_pins_|dout[7] .is_wysiwyg = "true"; +defparam \z80_|data_pins_|dout[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N20 +cycloneive_lcell_comb \z80_|bus_control_|db[7]~7 ( +// Equation(s): +// \z80_|bus_control_|db[7]~7_combout = ((\z80_|bus_control_|db[7]~5_combout & ((\z80_|data_pins_|dout [7]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) + + .dataa(\z80_|bus_control_|db[0]~6_combout ), + .datab(\z80_|bus_control_|db[7]~5_combout ), + .datac(\z80_|data_pins_|dout [7]), + .datad(\z80_|execute_|ctl_bus_db_oe~combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[7]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[7]~7 .lut_mask = 16'hD5DD; +defparam \z80_|bus_control_|db[7]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y13_N21 +dffeas \z80_|ir_|opcode[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|bus_control_|db[7]~7_combout ), .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), @@ -53174,65 +43916,9090 @@ dffeas \z80_|ir_|opcode[3] ( .ena(\z80_|execute_|ctl_ir_we~13_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|ir_|opcode [3]), + .q(\z80_|ir_|opcode [7]), .prn(vcc)); // synopsys translate_off -defparam \z80_|ir_|opcode[3] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[3] .power_up = "low"; +defparam \z80_|ir_|opcode[7] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X40_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~4 ( +// Location: LCCOMB_X29_Y13_N30 +cycloneive_lcell_comb \z80_|pla_decode_|Equal6~0 ( // Equation(s): -// \z80_|execute_|ctl_mWrite~4_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal52~0_combout ))) +// \z80_|pla_decode_|Equal6~0_combout = (!\z80_|decode_state_|DFFE_instED~q & (!\z80_|decode_state_|DFFE_instCB~q & (!\z80_|ir_|opcode [7] & !\z80_|ir_|opcode [6]))) - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal3~1_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal52~0_combout ), + .dataa(\z80_|decode_state_|DFFE_instED~q ), + .datab(\z80_|decode_state_|DFFE_instCB~q ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|ir_|opcode [6]), .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~4_combout ), + .combout(\z80_|pla_decode_|Equal6~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~4 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_mWrite~4 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal6~0 .lut_mask = 16'h0001; +defparam \z80_|pla_decode_|Equal6~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y17_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~2 ( +// Location: LCCOMB_X21_Y16_N4 +cycloneive_lcell_comb \z80_|pla_decode_|Equal12~0 ( // Equation(s): -// \z80_|execute_|ctl_apin_mux~2_combout = ((\z80_|execute_|ctl_mWrite~4_combout & \z80_|execute_|ctl_apin_mux~1_combout )) # (!\z80_|execute_|ctl_inc_dec~6_combout ) +// \z80_|pla_decode_|Equal12~0_combout = (!\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [0]))) - .dataa(\z80_|execute_|ctl_mWrite~4_combout ), - .datab(\z80_|execute_|ctl_apin_mux~1_combout ), - .datac(\z80_|execute_|ctl_inc_dec~6_combout ), + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal12~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal12~0 .lut_mask = 16'h0040; +defparam \z80_|pla_decode_|Equal12~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~16 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~16_combout = (\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal12~0_combout & \z80_|ir_|opcode [3]))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|pla_decode_|Equal12~0_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~16 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_mRead~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|fMRead~24 ( +// Equation(s): +// \z80_|execute_|fMRead~24_combout = (\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_mRead~16_combout ) # ((\z80_|execute_|ctl_mRead~15_combout )))) # (!\z80_|execute_|ctl_ir_we~4_combout & (\z80_|execute_|ctl_alu_oe~0_combout & +// ((\z80_|execute_|ctl_mRead~16_combout ) # (\z80_|execute_|ctl_mRead~15_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|execute_|ctl_mRead~16_combout ), + .datac(\z80_|execute_|ctl_mRead~15_combout ), + .datad(\z80_|execute_|ctl_alu_oe~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~24 .lut_mask = 16'hFCA8; +defparam \z80_|execute_|fMRead~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N12 +cycloneive_lcell_comb \z80_|execute_|fMRead~25 ( +// Equation(s): +// \z80_|execute_|fMRead~25_combout = ((\z80_|execute_|fMRead~24_combout ) # ((\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|pc_inc_hold~26_combout ))) # (!\z80_|execute_|ctl_bus_db_oe~0_combout ) + + .dataa(\z80_|execute_|ctl_bus_db_oe~0_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|fMRead~24_combout ), + .datad(\z80_|execute_|pc_inc_hold~26_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~25 .lut_mask = 16'hF5FD; +defparam \z80_|execute_|fMRead~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~21 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~21_combout = (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|decode_state_|in_halt~q & (!\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal77~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|decode_state_|in_halt~q ), + .datac(\z80_|decode_state_|use_ixiy~combout ), + .datad(\z80_|pla_decode_|Equal77~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~21 .lut_mask = 16'h0200; +defparam \z80_|execute_|ctl_mRead~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|fMRead~16 ( +// Equation(s): +// \z80_|execute_|fMRead~16_combout = (\z80_|execute_|ctl_ir_we~11_combout ) # ((\z80_|execute_|ctl_ir_we~12_combout ) # ((\z80_|execute_|ctl_mRead~13_combout ) # (\z80_|execute_|ctl_mRead~21_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~11_combout ), + .datab(\z80_|execute_|ctl_ir_we~12_combout ), + .datac(\z80_|execute_|ctl_mRead~13_combout ), + .datad(\z80_|execute_|ctl_mRead~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~16 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|fMRead~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|fMRead~14 ( +// Equation(s): +// \z80_|execute_|fMRead~14_combout = (\z80_|execute_|ctl_ir_we~14_combout ) # ((\z80_|execute_|ctl_ir_we~8_combout ) # ((!\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal49~0_combout ))) + + .dataa(\z80_|decode_state_|use_ixiy~combout ), + .datab(\z80_|pla_decode_|Equal49~0_combout ), + .datac(\z80_|execute_|ctl_ir_we~14_combout ), + .datad(\z80_|execute_|ctl_ir_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~14 .lut_mask = 16'hFFF4; +defparam \z80_|execute_|fMRead~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y14_N2 +cycloneive_lcell_comb \z80_|execute_|fMRead~15 ( +// Equation(s): +// \z80_|execute_|fMRead~15_combout = (!\z80_|execute_|fMWrite~3_combout & ((\z80_|execute_|ctl_ir_we~11_combout ) # ((\z80_|execute_|ctl_mRead~4_combout ) # (\z80_|execute_|fMRead~14_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~11_combout ), + .datab(\z80_|execute_|ctl_mRead~4_combout ), + .datac(\z80_|execute_|fMRead~14_combout ), + .datad(\z80_|execute_|fMWrite~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~15 .lut_mask = 16'h00FE; +defparam \z80_|execute_|fMRead~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|fMRead~12 ( +// Equation(s): +// \z80_|execute_|fMRead~12_combout = (!\z80_|pla_decode_|Equal13~2_combout & (!\z80_|execute_|ctl_mRead~2_combout & (!\z80_|pla_decode_|Equal6~1_combout & \z80_|execute_|ctl_bus_db_oe~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(\z80_|execute_|ctl_mRead~2_combout ), + .datac(\z80_|pla_decode_|Equal6~1_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~12 .lut_mask = 16'h0100; +defparam \z80_|execute_|fMRead~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y14_N18 +cycloneive_lcell_comb \z80_|execute_|fMRead~11 ( +// Equation(s): +// \z80_|execute_|fMRead~11_combout = (((\z80_|execute_|ctl_mRead~11_combout ) # (\z80_|execute_|ctl_mRead~21_combout )) # (!\z80_|execute_|pc_inc_hold~6_combout )) # (!\z80_|execute_|nextM~3_combout ) + + .dataa(\z80_|execute_|nextM~3_combout ), + .datab(\z80_|execute_|pc_inc_hold~6_combout ), + .datac(\z80_|execute_|ctl_mRead~11_combout ), + .datad(\z80_|execute_|ctl_mRead~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~11 .lut_mask = 16'hFFF7; +defparam \z80_|execute_|fMRead~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|fMRead~13 ( +// Equation(s): +// \z80_|execute_|fMRead~13_combout = (\z80_|execute_|ctl_state_alu~2_combout & (((\z80_|execute_|ctl_ir_we~14_combout ) # (\z80_|execute_|fMRead~11_combout )) # (!\z80_|execute_|fMRead~12_combout ))) + + .dataa(\z80_|execute_|fMRead~12_combout ), + .datab(\z80_|execute_|ctl_ir_we~14_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|fMRead~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~13 .lut_mask = 16'hF0D0; +defparam \z80_|execute_|fMRead~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y14_N6 +cycloneive_lcell_comb \z80_|execute_|fMRead~17 ( +// Equation(s): +// \z80_|execute_|fMRead~17_combout = (\z80_|execute_|fMRead~15_combout ) # ((\z80_|execute_|fMRead~13_combout ) # ((\z80_|execute_|fMRead~16_combout & \z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|execute_|fMRead~16_combout ), + .datab(\z80_|execute_|fMRead~15_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|fMRead~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~17 .lut_mask = 16'hFFEC; +defparam \z80_|execute_|fMRead~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|fMRead~22 ( +// Equation(s): +// \z80_|execute_|fMRead~22_combout = (\z80_|execute_|fMRead~17_combout ) # (((!\z80_|execute_|fMRead~21_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~40_combout )) # (!\z80_|execute_|ctl_sw_4d~2_combout )) + + .dataa(\z80_|execute_|fMRead~17_combout ), + .datab(\z80_|execute_|ctl_sw_4d~2_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~40_combout ), + .datad(\z80_|execute_|fMRead~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~22 .lut_mask = 16'hBFFF; +defparam \z80_|execute_|fMRead~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|fMRead~27 ( +// Equation(s): +// \z80_|execute_|fMRead~27_combout = ((\z80_|sequencer_|DFFE_M2_ff~q & (!\z80_|execute_|ixy_d~4_combout & \z80_|execute_|ctl_mRead~12_combout ))) # (!\z80_|execute_|fMRead~26_combout ) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|execute_|fMRead~26_combout ), + .datac(\z80_|execute_|ixy_d~4_combout ), + .datad(\z80_|execute_|ctl_mRead~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~27 .lut_mask = 16'h3B33; +defparam \z80_|execute_|fMRead~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|fMRead~37 ( +// Equation(s): +// \z80_|execute_|fMRead~37_combout = (\z80_|sequencer_|DFFE_M4_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|execute_|ctl_mRead~13_combout ) # (\z80_|execute_|ctl_state_alu~6_combout )))) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|execute_|ctl_mRead~13_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|execute_|ctl_state_alu~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~37 .lut_mask = 16'h0A08; +defparam \z80_|execute_|fMRead~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|fMRead~31 ( +// Equation(s): +// \z80_|execute_|fMRead~31_combout = (\z80_|pla_decode_|Equal33~3_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ixy_d~6_combout )))) # (!\z80_|pla_decode_|Equal33~3_combout & (\z80_|pla_decode_|Equal6~1_combout & +// ((\z80_|execute_|ixy_d~5_combout ) # (\z80_|execute_|ixy_d~6_combout )))) + + .dataa(\z80_|pla_decode_|Equal33~3_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|pla_decode_|Equal6~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~31 .lut_mask = 16'hFCA8; +defparam \z80_|execute_|fMRead~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N14 +cycloneive_lcell_comb \z80_|execute_|fMRead~29 ( +// Equation(s): +// \z80_|execute_|fMRead~29_combout = (\z80_|execute_|ctl_ir_we~5_combout & (\z80_|pla_decode_|Equal33~0_combout & ((\z80_|ir_|opcode [7]) # (\z80_|ir_|opcode [6])))) + + .dataa(\z80_|execute_|ctl_ir_we~5_combout ), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|execute_|fMRead~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~29 .lut_mask = 16'hA080; +defparam \z80_|execute_|fMRead~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|fMRead~30 ( +// Equation(s): +// \z80_|execute_|fMRead~30_combout = (\z80_|execute_|ctl_alu_shift_oe~14_combout & ((\z80_|execute_|ctl_ir_we~9_combout ) # ((\z80_|execute_|fMRead~29_combout ) # (\z80_|execute_|ctl_ir_we~10_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~9_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datac(\z80_|execute_|fMRead~29_combout ), + .datad(\z80_|execute_|ctl_ir_we~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~30 .lut_mask = 16'hCCC8; +defparam \z80_|execute_|fMRead~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|fMRead~28 ( +// Equation(s): +// \z80_|execute_|fMRead~28_combout = ((\z80_|execute_|ixy_d~6_combout & ((\z80_|pla_decode_|Equal41~2_combout ) # (\z80_|pla_decode_|Equal9~1_combout )))) # (!\z80_|execute_|nextM~4_combout ) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|execute_|nextM~4_combout ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~28 .lut_mask = 16'hBBB3; +defparam \z80_|execute_|fMRead~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|fMRead~32 ( +// Equation(s): +// \z80_|execute_|fMRead~32_combout = ((\z80_|execute_|fMRead~31_combout ) # ((\z80_|execute_|fMRead~30_combout ) # (\z80_|execute_|fMRead~28_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ), + .datab(\z80_|execute_|fMRead~31_combout ), + .datac(\z80_|execute_|fMRead~30_combout ), + .datad(\z80_|execute_|fMRead~28_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~32 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|fMRead~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|fMRead~33 ( +// Equation(s): +// \z80_|execute_|fMRead~33_combout = (\z80_|execute_|fMRead~27_combout ) # (((\z80_|execute_|fMRead~37_combout ) # (\z80_|execute_|fMRead~32_combout )) # (!\z80_|execute_|fMRead~6_combout )) + + .dataa(\z80_|execute_|fMRead~27_combout ), + .datab(\z80_|execute_|fMRead~6_combout ), + .datac(\z80_|execute_|fMRead~37_combout ), + .datad(\z80_|execute_|fMRead~32_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~33 .lut_mask = 16'hFFFB; +defparam \z80_|execute_|fMRead~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|fMRead~23 ( +// Equation(s): +// \z80_|execute_|fMRead~23_combout = (\z80_|execute_|ctl_state_alu~3_combout & (((\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|fMRead~5_combout )) # (!\z80_|execute_|fMRead~4_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~3_combout ), + .datab(\z80_|execute_|fMRead~4_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|fMRead~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~23 .lut_mask = 16'hA2AA; +defparam \z80_|execute_|fMRead~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N26 +cycloneive_lcell_comb \z80_|execute_|fMRead~34 ( +// Equation(s): +// \z80_|execute_|fMRead~34_combout = (\z80_|execute_|fMRead~25_combout ) # ((\z80_|execute_|fMRead~22_combout ) # ((\z80_|execute_|fMRead~33_combout ) # (\z80_|execute_|fMRead~23_combout ))) + + .dataa(\z80_|execute_|fMRead~25_combout ), + .datab(\z80_|execute_|fMRead~22_combout ), + .datac(\z80_|execute_|fMRead~33_combout ), + .datad(\z80_|execute_|fMRead~23_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~34 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|fMRead~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y14_N14 +cycloneive_lcell_comb \z80_|execute_|fMRead~35 ( +// Equation(s): +// \z80_|execute_|fMRead~35_combout = ((\z80_|execute_|ctl_ir_we~12_combout ) # ((\z80_|execute_|ctl_mRead~21_combout ) # (!\z80_|execute_|fMRead~7_combout ))) # (!\z80_|execute_|fMWrite~1_combout ) + + .dataa(\z80_|execute_|fMWrite~1_combout ), + .datab(\z80_|execute_|ctl_ir_we~12_combout ), + .datac(\z80_|execute_|fMRead~7_combout ), + .datad(\z80_|execute_|ctl_mRead~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~35 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|fMRead~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~19 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~19_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|pla_decode_|Equal33~3_combout ) # (!\z80_|execute_|ctl_al_we~5_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|pla_decode_|Equal33~3_combout ), + .datad(\z80_|execute_|ctl_al_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~19 .lut_mask = 16'h4044; +defparam \z80_|execute_|ctl_reg_sel_pc~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N16 +cycloneive_lcell_comb \z80_|execute_|fMRead~36 ( +// Equation(s): +// \z80_|execute_|fMRead~36_combout = (\z80_|execute_|fMRead~34_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~19_combout ) # ((!\z80_|execute_|fMRead~2_combout & \z80_|execute_|fMRead~35_combout ))) + + .dataa(\z80_|execute_|fMRead~34_combout ), + .datab(\z80_|execute_|fMRead~2_combout ), + .datac(\z80_|execute_|fMRead~35_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~36 .lut_mask = 16'hFFBA; +defparam \z80_|execute_|fMRead~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N22 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_re ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_re~combout = (\z80_|pin_control_|bus_db_pin_re~2_combout ) # ((\z80_|sequencer_|DFFE_T2_ff~q & \z80_|execute_|fMRead~36_combout )) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(gnd), + .datac(\z80_|execute_|fMRead~36_combout ), + .datad(\z80_|pin_control_|bus_db_pin_re~2_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_re~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_re .lut_mask = 16'hFFA0; +defparam \z80_|pin_control_|bus_db_pin_re .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~118 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][4]~118_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [6]))) # (!\ula_|ps2_keyboard_|shiftreg [2] & +// (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [6]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][4]~118_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][4]~118 .lut_mask = 16'h1008; +defparam \ula_|zx_keyboard_|keys[2][4]~118 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~119 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][4]~119_combout = (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[2][4]~118_combout & \ula_|zx_keyboard_|keys[5][1]~34_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|zx_keyboard_|keys[2][4]~118_combout ), + .datad(\ula_|zx_keyboard_|keys[5][1]~34_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][4]~119_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][4]~119 .lut_mask = 16'h4000; +defparam \ula_|zx_keyboard_|keys[2][4]~119 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~120 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][4]~120_combout = (\ula_|zx_keyboard_|keys[2][4]~119_combout & ((!\ula_|zx_keyboard_|keys[2][4]~94_combout ))) # (!\ula_|zx_keyboard_|keys[2][4]~119_combout & (\ula_|zx_keyboard_|keys[2][4]~q )) + + .dataa(\ula_|zx_keyboard_|keys[2][4]~119_combout ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[2][4]~q ), + .datad(\ula_|zx_keyboard_|keys[2][4]~94_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][4]~120_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][4]~120 .lut_mask = 16'h50FA; +defparam \ula_|zx_keyboard_|keys[2][4]~120 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y9_N1 +dffeas \ula_|zx_keyboard_|keys[2][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[2][4]~120_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[2][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[2][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~129 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][4]~129_combout = (!\ula_|ps2_keyboard_|shiftreg [7] & (\ula_|ps2_keyboard_|scan_code_ready~q & (!\ula_|zx_keyboard_|Equal0~1_combout & \ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [7]), + .datab(\ula_|ps2_keyboard_|scan_code_ready~q ), + .datac(\ula_|zx_keyboard_|Equal0~1_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][4]~129_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][4]~129 .lut_mask = 16'h0400; +defparam \ula_|zx_keyboard_|keys[3][4]~129 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~116 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][4]~116_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [0]))) # (!\ula_|ps2_keyboard_|shiftreg [6] & +// (!\ula_|zx_keyboard_|extended~q & (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [0]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|zx_keyboard_|extended~q ), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][4]~116_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][4]~116 .lut_mask = 16'h0810; +defparam \ula_|zx_keyboard_|keys[3][4]~116 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~134 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][4]~134_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [1] & \ula_|zx_keyboard_|keys[3][4]~116_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|zx_keyboard_|keys[3][4]~116_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][4]~134_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][4]~134 .lut_mask = 16'h4000; +defparam \ula_|zx_keyboard_|keys[3][4]~134 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~117 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][4]~117_combout = (\ula_|zx_keyboard_|keys[3][4]~129_combout & ((\ula_|zx_keyboard_|keys[3][4]~134_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][4]~134_combout & ((\ula_|zx_keyboard_|keys[3][4]~q +// ))))) # (!\ula_|zx_keyboard_|keys[3][4]~129_combout & (((\ula_|zx_keyboard_|keys[3][4]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[3][4]~129_combout ), + .datac(\ula_|zx_keyboard_|keys[3][4]~q ), + .datad(\ula_|zx_keyboard_|keys[3][4]~134_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][4]~117_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][4]~117 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[3][4]~117 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y8_N19 +dffeas \ula_|zx_keyboard_|keys[3][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[3][4]~117_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[3][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[3][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N6 +cycloneive_lcell_comb \D[4]~60 ( +// Equation(s): +// \D[4]~60_combout = (\z80_|address_pins_|abus[11]~19_combout & ((\z80_|address_pins_|abus[10]~24_combout ) # ((!\ula_|zx_keyboard_|keys[2][4]~q )))) # (!\z80_|address_pins_|abus[11]~19_combout & (!\ula_|zx_keyboard_|keys[3][4]~q & +// ((\z80_|address_pins_|abus[10]~24_combout ) # (!\ula_|zx_keyboard_|keys[2][4]~q )))) + + .dataa(\z80_|address_pins_|abus[11]~19_combout ), + .datab(\z80_|address_pins_|abus[10]~24_combout ), + .datac(\ula_|zx_keyboard_|keys[2][4]~q ), + .datad(\ula_|zx_keyboard_|keys[3][4]~q ), + .cin(gnd), + .combout(\D[4]~60_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~60 .lut_mask = 16'h8ACF; +defparam \D[4]~60 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~2 ( +// Equation(s): +// \ula_|zx_keyboard_|Equal0~2_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [3])) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|Equal0~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|Equal0~2 .lut_mask = 16'h000C; +defparam \ula_|zx_keyboard_|Equal0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][4]~121 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][4]~121_combout = (\ula_|zx_keyboard_|keys[1][4]~23_combout & ((\ula_|zx_keyboard_|Equal0~2_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|Equal0~2_combout & ((\ula_|zx_keyboard_|keys[1][4]~q ))))) # +// (!\ula_|zx_keyboard_|keys[1][4]~23_combout & (((\ula_|zx_keyboard_|keys[1][4]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[1][4]~23_combout ), + .datac(\ula_|zx_keyboard_|keys[1][4]~q ), + .datad(\ula_|zx_keyboard_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][4]~121_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][4]~121 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[1][4]~121 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y9_N9 +dffeas \ula_|zx_keyboard_|keys[1][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[1][4]~121_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[1][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[1][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~115 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][4]~115_combout = (\ula_|zx_keyboard_|keys[3][1]~27_combout & ((\ula_|zx_keyboard_|keys[0][4]~96_combout & ((!\ula_|zx_keyboard_|keys[0][4]~109_combout ))) # (!\ula_|zx_keyboard_|keys[0][4]~96_combout & +// (\ula_|zx_keyboard_|keys[0][4]~q )))) # (!\ula_|zx_keyboard_|keys[3][1]~27_combout & (((\ula_|zx_keyboard_|keys[0][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[3][1]~27_combout ), + .datab(\ula_|zx_keyboard_|keys[0][4]~96_combout ), + .datac(\ula_|zx_keyboard_|keys[0][4]~q ), + .datad(\ula_|zx_keyboard_|keys[0][4]~109_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][4]~115_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][4]~115 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[0][4]~115 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y9_N31 +dffeas \ula_|zx_keyboard_|keys[0][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[0][4]~115_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[0][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[0][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~4 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row~4_combout = ((\z80_|address_pins_|DFFE_apin_latch [8]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) # (!\ula_|zx_keyboard_|keys[0][4]~q ) + + .dataa(\ula_|zx_keyboard_|keys[0][4]~q ), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [8]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row~4_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row~4 .lut_mask = 16'hFF5F; +defparam \ula_|zx_keyboard_|key_row~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N22 +cycloneive_lcell_comb \D[4]~61 ( +// Equation(s): +// \D[4]~61_combout = (\D[4]~60_combout & (\ula_|zx_keyboard_|key_row~4_combout & ((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][4]~q )))) + + .dataa(\D[4]~60_combout ), + .datab(\z80_|address_pins_|abus[9]~17_combout ), + .datac(\ula_|zx_keyboard_|keys[1][4]~q ), + .datad(\ula_|zx_keyboard_|key_row~4_combout ), + .cin(gnd), + .combout(\D[4]~61_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~61 .lut_mask = 16'h8A00; +defparam \D[4]~61 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~124 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][4]~124_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|extended~q & !\ula_|ps2_keyboard_|shiftreg [2])) # (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|zx_keyboard_|extended~q & \ula_|ps2_keyboard_|shiftreg +// [2])) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|zx_keyboard_|extended~q ), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][4]~124_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][4]~124 .lut_mask = 16'h03C0; +defparam \ula_|zx_keyboard_|keys[4][4]~124 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~125 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][4]~125_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|zx_keyboard_|keys[4][4]~124_combout & (\ula_|zx_keyboard_|Equal0~2_combout & \ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|zx_keyboard_|keys[4][4]~124_combout ), + .datac(\ula_|zx_keyboard_|Equal0~2_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][4]~125_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][4]~125 .lut_mask = 16'h8000; +defparam \ula_|zx_keyboard_|keys[4][4]~125 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~126 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][4]~126_combout = (\ula_|zx_keyboard_|keys[0][0]~13_combout & ((\ula_|zx_keyboard_|keys[4][4]~125_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[4][4]~125_combout & ((\ula_|zx_keyboard_|keys[4][4]~q +// ))))) # (!\ula_|zx_keyboard_|keys[0][0]~13_combout & (((\ula_|zx_keyboard_|keys[4][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[0][0]~13_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[4][4]~q ), + .datad(\ula_|zx_keyboard_|keys[4][4]~125_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][4]~126_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][4]~126 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[4][4]~126 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y8_N7 +dffeas \ula_|zx_keyboard_|keys[4][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[4][4]~126_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[4][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[4][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~122 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][4]~122_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [2]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][4]~122_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][4]~122 .lut_mask = 16'h2000; +defparam \ula_|zx_keyboard_|keys[5][4]~122 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~123 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][4]~123_combout = (\ula_|zx_keyboard_|keys[6][4]~46_combout & ((\ula_|zx_keyboard_|keys[5][4]~122_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[5][4]~122_combout & (\ula_|zx_keyboard_|keys[5][4]~q +// )))) # (!\ula_|zx_keyboard_|keys[6][4]~46_combout & (((\ula_|zx_keyboard_|keys[5][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[6][4]~46_combout ), + .datab(\ula_|zx_keyboard_|keys[5][4]~122_combout ), + .datac(\ula_|zx_keyboard_|keys[5][4]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][4]~123_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][4]~123 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[5][4]~123 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y8_N1 +dffeas \ula_|zx_keyboard_|keys[5][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[5][4]~123_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[5][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[5][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N8 +cycloneive_lcell_comb \D[4]~62 ( +// Equation(s): +// \D[4]~62_combout = (\ula_|zx_keyboard_|keys[4][4]~q & (\z80_|address_pins_|abus[12]~21_combout & ((\z80_|address_pins_|abus[13]~20_combout ) # (!\ula_|zx_keyboard_|keys[5][4]~q )))) # (!\ula_|zx_keyboard_|keys[4][4]~q & +// ((\z80_|address_pins_|abus[13]~20_combout ) # ((!\ula_|zx_keyboard_|keys[5][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[4][4]~q ), + .datab(\z80_|address_pins_|abus[13]~20_combout ), + .datac(\z80_|address_pins_|abus[12]~21_combout ), + .datad(\ula_|zx_keyboard_|keys[5][4]~q ), + .cin(gnd), + .combout(\D[4]~62_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~62 .lut_mask = 16'hC4F5; +defparam \D[4]~62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~49 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][4]~49_combout = (\ula_|zx_keyboard_|keys[7][1]~21_combout & (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|zx_keyboard_|Equal0~2_combout & !\ula_|ps2_keyboard_|shiftreg [6]))) + + .dataa(\ula_|zx_keyboard_|keys[7][1]~21_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\ula_|zx_keyboard_|Equal0~2_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][4]~49_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][4]~49 .lut_mask = 16'h0080; +defparam \ula_|zx_keyboard_|keys[7][4]~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~3 ( +// Equation(s): +// \ula_|zx_keyboard_|shifted~3_combout = (\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [2]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|shifted~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|shifted~3 .lut_mask = 16'h00F0; +defparam \ula_|zx_keyboard_|shifted~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~127 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][4]~127_combout = (\ula_|zx_keyboard_|keys[7][4]~49_combout & ((\ula_|zx_keyboard_|shifted~3_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|shifted~3_combout & ((\ula_|zx_keyboard_|keys[7][4]~q ))))) # +// (!\ula_|zx_keyboard_|keys[7][4]~49_combout & (((\ula_|zx_keyboard_|keys[7][4]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[7][4]~49_combout ), + .datac(\ula_|zx_keyboard_|keys[7][4]~q ), + .datad(\ula_|zx_keyboard_|shifted~3_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][4]~127_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][4]~127 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[7][4]~127 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y7_N23 +dffeas \ula_|zx_keyboard_|keys[7][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[7][4]~127_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[7][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[7][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~128 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][4]~128_combout = (\ula_|zx_keyboard_|keys[6][4]~46_combout & ((\ula_|zx_keyboard_|keys[6][4]~18_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[6][4]~18_combout & ((\ula_|zx_keyboard_|keys[6][4]~q +// ))))) # (!\ula_|zx_keyboard_|keys[6][4]~46_combout & (((\ula_|zx_keyboard_|keys[6][4]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[6][4]~46_combout ), + .datac(\ula_|zx_keyboard_|keys[6][4]~q ), + .datad(\ula_|zx_keyboard_|keys[6][4]~18_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][4]~128_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][4]~128 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[6][4]~128 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y7_N9 +dffeas \ula_|zx_keyboard_|keys[6][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[6][4]~128_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[6][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[6][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N28 +cycloneive_lcell_comb \D[4]~63 ( +// Equation(s): +// \D[4]~63_combout = (\ula_|zx_keyboard_|keys[7][4]~q & (\z80_|address_pins_|abus[15]~22_combout & ((\z80_|address_pins_|abus[14]~23_combout ) # (!\ula_|zx_keyboard_|keys[6][4]~q )))) # (!\ula_|zx_keyboard_|keys[7][4]~q & +// (((\z80_|address_pins_|abus[14]~23_combout ) # (!\ula_|zx_keyboard_|keys[6][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[7][4]~q ), + .datab(\z80_|address_pins_|abus[15]~22_combout ), + .datac(\ula_|zx_keyboard_|keys[6][4]~q ), + .datad(\z80_|address_pins_|abus[14]~23_combout ), + .cin(gnd), + .combout(\D[4]~63_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~63 .lut_mask = 16'hDD0D; +defparam \D[4]~63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N6 +cycloneive_lcell_comb \D[4]~64 ( +// Equation(s): +// \D[4]~64_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[4]~61_combout & (\D[4]~62_combout & \D[4]~63_combout ))) + + .dataa(\D[4]~61_combout ), + .datab(\D[4]~62_combout ), + .datac(\z80_|address_pins_|abus[0]~16_combout ), + .datad(\D[4]~63_combout ), + .cin(gnd), + .combout(\D[4]~64_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~64 .lut_mask = 16'hF8F0; +defparam \D[4]~64 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y5_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a28 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[4]~76_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a28_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_first_bit_number = 4; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y6_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a20 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[4]~76_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_first_bit_number = 4; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y11_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a12 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[4]~76_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y9_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a4 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[4]~76_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N4 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ) # +// ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout & +// !\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8 .lut_mask = 16'hAAD8; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N14 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout = (\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ) # +// ((!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout & (((\ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout & +// \ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout ), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9 .lut_mask = 16'hACF0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y3_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a12 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'hA50276000854A0103840403E540424244404783E18807A08A47C54484448544A807E7E10005270182040407E4A1252124208084008404208420A4A42424A125A024428106448524A624A4A24425242522060108010543C00044A105424005E0031ED1E0529E507AE2F6FF1CD51D4C772A648E65F6532C28022061303F06C36CDBD319B55CB8E626C20E46C93C1463A0B1CE594F0ED3B62330C104DECE46CA6CD966B1386612C7B43980349408F36FB64C14342DAE26CE4D8D5E791388729D743B09A27AB81D71A14AB3D24E385B602248476D00249239514B58D3098504ACD119B99E9021B650A69494C22600667473128DA5010D2195982823226DED0ADFCB8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h5861917919344A4685CC0990862A11324792E761B6D41C0FCC0838C1C27211A2453FDC2219C225E421B320085A8FBFD0C42135B16448DFC226E09B3438A740C352979565817114DE46462844A57F7958873FC4B255C8AE549BDD1A87415D5018F88D5002628FFD13203066C850F10649F21319109208387641120B362124803F0678522BA2812C1454A502ED1A59CBD76A034756F5765DF7555F57575F7F57FFFF7FFF7D5712524D4A30723514B2B3064A84B4742D48415281863DDFAA9D9B7E7BB16DDB96B7845371C30B55DB96C8F6EB4B453242FF6A4DF84A76B5AEDC88A68DC6A06905054C8C36E4199E74638E6532965218A965909BA456000451343351; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'hE2975A2686A7AE0288F140141B698E2A82A835F478453A1D722CFCED12859FD735188757AC5A42DEB501FE010586249AC1EA60D08F74CFA5086EC78FC9190C056059E332C311521E6522901852D484B423A98816C9B26A08C92368E9FF05524502288A804612A2A0A102A418CBDFBA554499541660F8124640110101263142892A086B442661015380041594608092D9CB919250100A37DDA3919A1427F660963C251301FB2CA45562245308885131119115C652B2493252340201101942D26000CC60799124A8520C08050122171281808058018C38A645D07931896B39ED259A22242CB58413089465B246231330D806105010035100B08761A08506094160; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h1228D91C352915424000000AA0088F63153A8AD81B945C8789F01C86548D12CEAB6AA38578BD55CEC9AA28082C285B8C0201104838AD502AC160C13C70620B818249144AB52CED94200A0202A885100E0D938A30A34512C0CEC98F08A98900F2093E11673256B3169C12284980E92A034141E0782507800F8100009C403C07867000000030082004A17800828F090A0C318CE120012172286317922341A2A12840B6C18040682080125C75401AEC44E8C01A8D40D1412B25A09F7600B0C6FEC65BFE5CE861A20F71E8032916A78F29CC546518461522E4E14998DD54BC0E40B64B710C9DC948F06010DF01D880E2044BE8854062D10DD93F30A62AA7FD227C4C; +// synopsys translate_on + +// Location: M9K_X33_Y27_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a12 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(gnd), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[4]~76_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_first_bit_number = 4; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y24_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a4 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[4]~76_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a4_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_first_bit_number = 4; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFFF0000003E0000003E0000C83F0000D83F0000F03F0000303E0000303E0000003F0010003F0010203F0010F03F0010703F0018303F001C603D800C003CFE26003C7F0F803FFFFFFFFFFFFFFFF; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF00000000000008108000BDF288E9688E000000000000000000000000FFFFFFFF0000000000041D989EA296D29EE969CA000000000000000000000000000000007FFFFFFC8004198A9AA298929EE9498A00000000000000000000000000000000FFFFFFFE800400CA9AA2AADA8AE949CE0000000000000000000000007FFFFFFEC00000028004046A9F22BA5A9EE90FC20000000000000000000000007FFFFFFE8000000280040FEA8002AA7A9EE12742000000000000000000000000000000023FFFFFFC9FE42BA298E2293A80096742000000000000000000000000000000003FFFFFFC9FE4B19298E3181E8009436A; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'h9FE8234A88F836EE9FF8BD4208282BC080DE87C2B84199C2B85E37C2B05B3A829FE8236688F837CE9FF8898208A82A44808A87CAB9C19DC2B80E3AC2927F2AC2800833E288F837C69FE8AB9688882E4283248DC2B9D188C2ABAE2F8291371092800832EA887807C69FE8AB8688080AC283E49D42B914BFC2A3BF1E82910712EA800802EA883807869DE88E8688080AC68BC4BDC2BB1439C2A27F5F82910314E2800886E6880807C69CC89A8681800BC289549CC2AB0C3942A04B7F82953315E2800886EE900805C61C089FC081E415C289D89DC2AB4E3142A1233D8217330090800086EE900805821C08BEC080D407C289C89DC2AADE3142A13B7F82176300F0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h076B0A5083288F028370C182A801468297E5AC1288D308023FFFFFFC00000000072BA9608BA08D028BF4D182AC015682937CA80288D308023FFFFFFC00000002872B892A8FA08F028A14509AAC0166B2B37DA80288D10D02800000027FFFFFFE852BAD128E388D028A004082AC0166C2937DA00288D10F02C00000027FFFFFFE846289368968C90289E0528A8C016CA29379B20280510F02FFFFFFFE0000000085E2A922816089828BE0428286416C829179B00280511F027FFFFFFC0000000087EA8B32872089828800569287436CA28179B20200513F0000000000FFFFFFFF8768A3028610858288004682874364828019900200403E0000000000FFFFFFFF; +// synopsys translate_on + +// Location: M9K_X33_Y4_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a4 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h35861A00A6112A1481AF1A50A6004A05291627227FF08229B87389E08119A28A7888672DC999B7046A61E60810A7434450E3D33E330F321A18E8A120D1EDC8623DA2C64840C2CCE811522B42008095E5A456C98F4B25EAEA410610545024640CF10410AC463BF9349074917E9A74A12830EFA280EBD3131E484A255D0191C6852730A263DBCCAAA88712242B3BE49AA5338990229B391158C726BC7EB4ECC32308980020680249882691A680488292310B4313CE87FFCD5329A64B708CAC8533316412C4900F646A36630261DA093053D98F19D2C5B653165D4A71AA5682B29B89B6054CC727D292805705A93268676A31111371390B240EC3CC85D331813EB1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h1AA1C248D293110CB951445117D9B6AA500F65068B8CC508BD00184F8705B010A0CC46CC9302649242CE08191634113154562B149100204551178DE805D98EC8A2E5A64B241400267194CD524499BC01D31058CD18684A817A5800B65143281C1310B00A49902C0104004C654E0582040001103654011012021912281216B000C653A0510A1B00C36AC88058CAC126E14E198DFB07E81C3F41510BB08F8F851C3B9AF0147BC1F730B4E91D9D11C3A8F1B82DF19988ACC44072FDB17B4D81882E9DD952B29003D7767BA581A68BC41C2B16AD6EB57F1D048CD4E464190D25ADF2C194E3598360AFB031A1690F4625BB628363B4C90A400E3A04DAA70DA0CC4776; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'hC82B30671933680037A65978674DDEC2D30EEEDA78F5F2A1DEE660FFEA11B175DCB42E9277212A58842051A078007109A0D820166B881042600284403143048295D23A0E191EBC2134B833D53D37E42B05018289A10300A188E315CE98640F548A370D60A0AA3E7288A0B0869FA5E703D1AE17C0EC276B2AFB747B550A8B41021620D1A60A901095D12A0973B95E20838001330138951361967847D42901910A3488480610A91A851E84FF08783F81AEA52D2FDC2200BD2FE81C0357FBEC1D875686C6CA41B2224C88D8456C1DBF20D820A6649774CB11B69933246E9739C998470542C2E3C783A4C24767084C52DC209D60E95DBC096D9A0171A12D5AB99BAB; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h17A24D2C636ED2478B5AE1C99D40761B1E7AA6A89DDD1BBD8DBD223E70531BCDE90C8E38C8E0478AD8B388F94891C9673A50BC32478E083074657E8E0EA53BEE861F8BC1993560946D92D1C0C7F046A245B5849CB751FF15B97FCD50BC7B8524C13E7C640F3645082248D1CC14296E30DEA3057B35C641762CD00D40DABC27472251A60725008AAA056591C4000BB48C0BC29B8034A03400027B84769B520D9196968460CA3388A03ECB45F2C4B70F1829221000FFFC7FEC346F079F13079798EC2A08157331C6CC0E30884244916A0DE26D4D22454091290404A492016887E2111F830F9851184101370588A06D3BF9AE621A5F4E632A6799C83EFAAE06769D; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N24 +cycloneive_lcell_comb \Selector4~0 ( +// Equation(s): +// \Selector4~0_combout = (\z80_|address_pins_|abus[14]~23_combout & ((\Selector3~0_combout ) # ((\ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout )))) # (!\z80_|address_pins_|abus[14]~23_combout & (!\Selector3~0_combout & +// ((\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout )))) + + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\Selector3~0_combout ), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ), + .cin(gnd), + .combout(\Selector4~0_combout ), + .cout()); +// synopsys translate_off +defparam \Selector4~0 .lut_mask = 16'hB9A8; +defparam \Selector4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N14 +cycloneive_lcell_comb \Selector4~1 ( +// Equation(s): +// \Selector4~1_combout = (\Selector3~0_combout & ((\Selector4~0_combout & ((\ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ))) # (!\Selector4~0_combout & (\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout )))) # +// (!\Selector3~0_combout & (((\Selector4~0_combout )))) + + .dataa(\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ), + .datab(\Selector3~0_combout ), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ), + .datad(\Selector4~0_combout ), + .cin(gnd), + .combout(\Selector4~1_combout ), + .cout()); +// synopsys translate_off +defparam \Selector4~1 .lut_mask = 16'hF388; +defparam \Selector4~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N10 +cycloneive_lcell_comb \D[4]~86 ( +// Equation(s): +// \D[4]~86_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [15] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\Selector4~1_combout +// ))))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout )))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|address_pins_|DFFE_apin_latch [15]), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout ), + .datad(\Selector4~1_combout ), + .cin(gnd), + .combout(\D[4]~86_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~86 .lut_mask = 16'hF2D0; +defparam \D[4]~86 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N16 +cycloneive_lcell_comb \D[4]~75 ( +// Equation(s): +// \D[4]~75_combout = ((\Equal2~0_combout & (\D[4]~64_combout )) # (!\Equal2~0_combout & ((\D[4]~86_combout )))) # (!\Equal2~1_combout ) + + .dataa(\Equal2~1_combout ), + .datab(\D[4]~64_combout ), + .datac(\Equal2~0_combout ), + .datad(\D[4]~86_combout ), + .cin(gnd), + .combout(\D[4]~75_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~75 .lut_mask = 16'hDFD5; +defparam \D[4]~75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N30 +cycloneive_lcell_comb \D[4]~76 ( +// Equation(s): +// \D[4]~76_combout = (\z80_|pin_control_|bus_db_pin_oe~15_combout & (((\z80_|data_pins_|dout [4] & \D[4]~75_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout & (((\D[4]~75_combout )) # (!\Equal2~1_combout ))) + + .dataa(\Equal2~1_combout ), + .datab(\z80_|data_pins_|dout [4]), + .datac(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .datad(\D[4]~75_combout ), + .cin(gnd), + .combout(\D[4]~76_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~76 .lut_mask = 16'hCF05; +defparam \D[4]~76 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N30 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[4] ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [4] = (\z80_|bus_control_|db[4]~19_combout & ((\z80_|execute_|ctl_bus_db_we~7_combout ) # ((\z80_|pin_control_|bus_db_pin_re~combout & \D[4]~76_combout )))) # (!\z80_|bus_control_|db[4]~19_combout & +// (\z80_|pin_control_|bus_db_pin_re~combout & ((\D[4]~76_combout )))) + + .dataa(\z80_|bus_control_|db[4]~19_combout ), + .datab(\z80_|pin_control_|bus_db_pin_re~combout ), + .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datad(\D[4]~76_combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [4]), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[4] .lut_mask = 16'hECA0; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[4] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y13_N31 +dffeas \z80_|data_pins_|dout[4] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [4]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|data_pins_|dout [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|data_pins_|dout[4] .is_wysiwyg = "true"; +defparam \z80_|data_pins_|dout[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N24 +cycloneive_lcell_comb \z80_|bus_control_|db[4]~18 ( +// Equation(s): +// \z80_|bus_control_|db[4]~18_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [4]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) + + .dataa(\z80_|bus_control_|db[0]~4_combout ), + .datab(\z80_|data_pins_|dout [4]), + .datac(gnd), + .datad(\z80_|execute_|ctl_bus_db_oe~combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[4]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[4]~18 .lut_mask = 16'h88AA; +defparam \z80_|bus_control_|db[4]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N0 +cycloneive_lcell_comb \z80_|bus_control_|db[4]~19 ( +// Equation(s): +// \z80_|bus_control_|db[4]~19_combout = ((\z80_|bus_control_|db[4]~18_combout & ((\z80_|alu_control_|db[4]~32_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) + + .dataa(\z80_|bus_control_|db[0]~6_combout ), + .datab(\z80_|bus_control_|db[4]~18_combout ), + .datac(\z80_|alu_control_|db[4]~32_combout ), + .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[4]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[4]~19 .lut_mask = 16'hD5DD; +defparam \z80_|bus_control_|db[4]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y17_N1 +dffeas \z80_|ir_|opcode[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|bus_control_|db[4]~19_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|ir_|opcode [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|ir_|opcode[4] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y17_N18 +cycloneive_lcell_comb \z80_|pla_decode_|Equal32~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal32~0_combout = (!\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3]) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [4]), + .datac(gnd), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal32~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal32~0 .lut_mask = 16'h3300; +defparam \z80_|pla_decode_|Equal32~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N18 +cycloneive_lcell_comb \z80_|pla_decode_|Equal41~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal41~1_combout = (\z80_|ir_|opcode [7] & (\z80_|ir_|opcode [6] & ((\z80_|decode_state_|DFFE_instIY1~q ) # (\z80_|decode_state_|DFFE_inst4~q )))) + + .dataa(\z80_|decode_state_|DFFE_instIY1~q ), + .datab(\z80_|decode_state_|DFFE_inst4~q ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal41~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal41~1 .lut_mask = 16'hE000; +defparam \z80_|pla_decode_|Equal41~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal41~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal41~2_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal32~0_combout & (\z80_|pla_decode_|Equal41~1_combout & \z80_|pla_decode_|Equal8~0_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal32~0_combout ), + .datac(\z80_|pla_decode_|Equal41~1_combout ), + .datad(\z80_|pla_decode_|Equal8~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal41~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal41~2 .lut_mask = 16'h4000; +defparam \z80_|pla_decode_|Equal41~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal36~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal36~0_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal1~7_combout & \z80_|pla_decode_|Equal32~0_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal2~0_combout ), + .datac(\z80_|pla_decode_|Equal1~7_combout ), + .datad(\z80_|pla_decode_|Equal32~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal36~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal36~0 .lut_mask = 16'h4000; +defparam \z80_|pla_decode_|Equal36~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_cb_set ( +// Equation(s): +// \z80_|execute_|ctl_state_tbl_cb_set~combout = (\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|pla_decode_|Equal41~2_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & +// ((\z80_|pla_decode_|Equal36~0_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & \z80_|pla_decode_|Equal41~2_combout )))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(\z80_|pla_decode_|Equal36~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_tbl_cb_set~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_tbl_cb_set .lut_mask = 16'hD5C0; +defparam \z80_|execute_|ctl_state_tbl_cb_set .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_state_tbl_we~8_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # ((\z80_|sequencer_|DFFE_T3_ff~q & \z80_|pla_decode_|Equal41~2_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_tbl_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_tbl_we~8 .lut_mask = 16'h00EC; +defparam \z80_|execute_|ctl_state_tbl_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y13_N9 +dffeas \z80_|decode_state_|DFFE_instCB ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|execute_|ctl_state_tbl_cb_set~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_state_tbl_we~8_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|decode_state_|DFFE_instCB~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instCB .is_wysiwyg = "true"; +defparam \z80_|decode_state_|DFFE_instCB .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal52~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal52~0_combout = (!\z80_|decode_state_|DFFE_instCB~q & (!\z80_|decode_state_|DFFE_instED~q & (\z80_|ir_|opcode [7] & \z80_|ir_|opcode [6]))) + + .dataa(\z80_|decode_state_|DFFE_instCB~q ), + .datab(\z80_|decode_state_|DFFE_instED~q ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal52~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal52~0 .lut_mask = 16'h1000; +defparam \z80_|pla_decode_|Equal52~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal2~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal2~1_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal32~0_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal52~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal32~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal2~1 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_ed_set ( +// Equation(s): +// \z80_|execute_|ctl_state_tbl_ed_set~combout = (\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal2~1_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & !\z80_|ir_|opcode [1]))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|pla_decode_|Equal2~1_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_tbl_ed_set~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_tbl_ed_set .lut_mask = 16'h0008; +defparam \z80_|execute_|ctl_state_tbl_ed_set .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y13_N13 +dffeas \z80_|decode_state_|DFFE_instED ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|execute_|ctl_state_tbl_ed_set~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_state_tbl_we~8_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|decode_state_|DFFE_instED~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instED .is_wysiwyg = "true"; +defparam \z80_|decode_state_|DFFE_instED .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N26 +cycloneive_lcell_comb \z80_|decode_state_|table_xx~0 ( +// Equation(s): +// \z80_|decode_state_|table_xx~0_combout = (\z80_|decode_state_|DFFE_instED~q ) # (\z80_|decode_state_|DFFE_instCB~q ) + + .dataa(\z80_|decode_state_|DFFE_instED~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|decode_state_|DFFE_instCB~q ), + .cin(gnd), + .combout(\z80_|decode_state_|table_xx~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|table_xx~0 .lut_mask = 16'hFFAA; +defparam \z80_|decode_state_|table_xx~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N24 +cycloneive_lcell_comb \z80_|pla_decode_|Equal34~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal34~0_combout = (!\z80_|ir_|opcode [0] & (!\z80_|decode_state_|table_xx~0_combout & (\z80_|pla_decode_|Equal3~1_combout & \z80_|pla_decode_|Equal41~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|decode_state_|table_xx~0_combout ), + .datac(\z80_|pla_decode_|Equal3~1_combout ), + .datad(\z80_|pla_decode_|Equal41~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal34~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal34~0 .lut_mask = 16'h1000; +defparam \z80_|pla_decode_|Equal34~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~6_combout = (\z80_|execute_|ctl_alu_op_low~22_combout & (!\z80_|execute_|ixy_d~16_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|pla_decode_|Equal34~0_combout )))) # (!\z80_|execute_|ctl_alu_op_low~22_combout & +// (((!\z80_|execute_|ixy_d~5_combout )) # (!\z80_|pla_decode_|Equal34~0_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datab(\z80_|pla_decode_|Equal34~0_combout ), + .datac(\z80_|execute_|ixy_d~16_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~6 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_reg_sel_pc~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~5_combout = ((!\z80_|execute_|ctl_mRead~6_combout & (!\z80_|execute_|ctl_mRead~7_combout & !\z80_|execute_|ctl_mRead~15_combout ))) # (!\z80_|execute_|ixy_d~5_combout ) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_mRead~6_combout ), + .datac(\z80_|execute_|ctl_mRead~7_combout ), + .datad(\z80_|execute_|ctl_mRead~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~5 .lut_mask = 16'h5557; +defparam \z80_|execute_|ctl_reg_sel_pc~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~4_combout = ((!\z80_|execute_|ixy_d~10_combout & ((!\z80_|pla_decode_|Equal24~0_combout ) # (!\z80_|pla_decode_|Equal21~0_combout )))) # (!\z80_|execute_|ctl_alu_op_low~22_combout ) + + .dataa(\z80_|execute_|ixy_d~10_combout ), + .datab(\z80_|pla_decode_|Equal21~0_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datad(\z80_|pla_decode_|Equal24~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~4 .lut_mask = 16'h1F5F; +defparam \z80_|execute_|ctl_reg_sel_pc~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~2_combout = ((!\z80_|execute_|ctl_mRead~13_combout & ((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout )))) # (!\z80_|execute_|ixy_d~5_combout ) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_mRead~13_combout ), + .datac(\z80_|pla_decode_|Equal12~1_combout ), + .datad(\z80_|pla_decode_|Equal25~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~2 .lut_mask = 16'h7577; +defparam \z80_|execute_|ctl_reg_sel_pc~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~3_combout = (\z80_|execute_|ctl_reg_sel_pc~2_combout & (((!\z80_|pla_decode_|Equal19~0_combout & !\z80_|execute_|ctl_mRead~8_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) + + .dataa(\z80_|pla_decode_|Equal19~0_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~2_combout ), + .datac(\z80_|execute_|ctl_mRead~8_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~3 .lut_mask = 16'h04CC; +defparam \z80_|execute_|ctl_reg_sel_pc~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~7_combout = (\z80_|execute_|ctl_reg_sel_pc~6_combout & (\z80_|execute_|ctl_reg_sel_pc~5_combout & (\z80_|execute_|ctl_reg_sel_pc~4_combout & \z80_|execute_|ctl_reg_sel_pc~3_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~6_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~5_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~4_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~7 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sel_pc~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~8_combout = (\z80_|pla_decode_|Equal12~1_combout & (((\z80_|pla_decode_|Equal3~0_combout & \z80_|pla_decode_|Equal24~0_combout )))) # (!\z80_|pla_decode_|Equal12~1_combout & ((\z80_|pla_decode_|Equal25~0_combout ) # +// ((\z80_|pla_decode_|Equal3~0_combout & \z80_|pla_decode_|Equal24~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal12~1_combout ), + .datab(\z80_|pla_decode_|Equal25~0_combout ), + .datac(\z80_|pla_decode_|Equal3~0_combout ), + .datad(\z80_|pla_decode_|Equal24~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~8 .lut_mask = 16'hF444; +defparam \z80_|execute_|ctl_reg_sel_pc~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~9_combout = (\z80_|execute_|ctl_alu_op_low~22_combout & ((\z80_|execute_|ctl_mRead~15_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~8_combout ) # (\z80_|pla_decode_|Equal34~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datab(\z80_|execute_|ctl_mRead~15_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~8_combout ), + .datad(\z80_|pla_decode_|Equal34~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~9 .lut_mask = 16'hAAA8; +defparam \z80_|execute_|ctl_reg_sel_pc~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~10 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~10_combout = (\z80_|execute_|ctl_reg_sel_pc~7_combout & (!\z80_|execute_|ctl_reg_sel_pc~9_combout & ((!\z80_|pla_decode_|Equal41~2_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~7_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~9_combout ), + .datad(\z80_|pla_decode_|Equal41~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~10 .lut_mask = 16'h040C; +defparam \z80_|execute_|ctl_reg_sel_pc~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~16 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~16_combout = (((\z80_|execute_|ctl_state_alu~3_combout & !\z80_|execute_|fMRead~4_combout )) # (!\z80_|execute_|ctl_apin_mux~0_combout )) # (!\z80_|execute_|ctl_reg_sel_pc~10_combout ) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~10_combout ), + .datab(\z80_|execute_|ctl_apin_mux~0_combout ), + .datac(\z80_|execute_|ctl_state_alu~3_combout ), + .datad(\z80_|execute_|fMRead~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~16 .lut_mask = 16'h77F7; +defparam \z80_|execute_|ctl_reg_sel_pc~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~17 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~17_combout = (\z80_|nM1_int~2_combout ) # ((\z80_|execute_|ctl_reg_sys_we~0_combout ) # ((!\z80_|execute_|ctl_sw_4u~1_combout ) # (!\z80_|execute_|ctl_inc_dec~12_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_reg_sys_we~0_combout ), + .datac(\z80_|execute_|ctl_inc_dec~12_combout ), + .datad(\z80_|execute_|ctl_sw_4u~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~17 .lut_mask = 16'hEFFF; +defparam \z80_|execute_|ctl_reg_sel_pc~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~15 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~15_combout = (\z80_|execute_|ctl_reg_sel_pc~19_combout ) # ((!\z80_|execute_|fMRead~2_combout & ((!\z80_|execute_|ctl_reg_sel_pc~14_combout ) # (!\z80_|execute_|setM1~38_combout )))) + + .dataa(\z80_|execute_|setM1~38_combout ), + .datab(\z80_|execute_|fMRead~2_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~14_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~15 .lut_mask = 16'hFF13; +defparam \z80_|execute_|ctl_reg_sel_pc~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~18 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~18_combout = (\z80_|execute_|ctl_reg_sel_pc~16_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~17_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~15_combout ) # (!\z80_|execute_|ctl_reg_sel_pc~13_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~16_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~17_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~13_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~18 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|ctl_reg_sel_pc~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~19 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~19_combout = (((!\z80_|pla_decode_|Equal19~0_combout & !\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|sequencer_|M5~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|pla_decode_|Equal19~0_combout ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|pla_decode_|Equal34~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~19 .lut_mask = 16'h5F7F; +defparam \z80_|execute_|ctl_reg_sel_wz~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N20 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~3 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_pc~3_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout & (\z80_|execute_|ctl_reg_sel_wz~19_combout & (\z80_|reg_control_|reg_sel_pc~2_combout & \z80_|execute_|ctl_alu_sel_op2_neg~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~19_combout ), + .datac(\z80_|reg_control_|reg_sel_pc~2_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_pc~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_pc~3 .lut_mask = 16'h4000; +defparam \z80_|reg_control_|reg_sel_pc~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N24 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc ( +// Equation(s): +// \z80_|reg_control_|reg_sel_pc~combout = (\z80_|execute_|ctl_reg_sel_pc~18_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & (!\z80_|execute_|ctl_reg_sel_wz~20_combout & \z80_|reg_control_|reg_sel_pc~3_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~18_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~20_combout ), + .datad(\z80_|reg_control_|reg_sel_pc~3_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_pc~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_pc .lut_mask = 16'h0200; +defparam \z80_|reg_control_|reg_sel_pc .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N24 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_72 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_72~combout = (\z80_|reg_control_|reg_sel_pc~combout & (!\z80_|reg_control_|reg_sys_we_hi~combout & \z80_|execute_|ctl_reg_sys_hilo[1]~35_combout )) + + .dataa(\z80_|reg_control_|reg_sel_pc~combout ), + .datab(gnd), + .datac(\z80_|reg_control_|reg_sys_we_hi~combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_72 .lut_mask = 16'h0A00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_72 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N10 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~2 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[0]~2_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ) # ((\z80_|reg_control_|reg_sw_4d_hi~0_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~43_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[0]~2 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|db_hi_as[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y14_N23 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[5]~15_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y14_N17 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[5]~15_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N16 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~13 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[5]~13_combout = (\z80_|reg_file_|gdfx_temp1[5]~57_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # (!\z80_|reg_file_|gdfx_temp1[5]~57_combout & +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[5]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[5]~13 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|db_hi_as[5]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N28 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~14 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[5]~14_combout = (\z80_|reg_file_|db_hi_as[5]~13_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datab(\z80_|reg_file_|b2v_latch_pc_hi|latch [5]), + .datac(gnd), + .datad(\z80_|reg_file_|db_hi_as[5]~13_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[5]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[5]~14 .lut_mask = 16'hDD00; +defparam \z80_|reg_file_|db_hi_as[5]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N22 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~15 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[5]~15_combout = ((\z80_|reg_file_|db_hi_as[5]~14_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .datad(\z80_|reg_file_|db_hi_as[5]~14_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[5]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[5]~15 .lut_mask = 16'hDF55; +defparam \z80_|reg_file_|db_hi_as[5]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y14_N9 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X37_Y14_N23 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~50 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~50_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (\z80_|reg_file_|b2v_latch_hl_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_hl2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (((\z80_|reg_file_|b2v_latch_hl2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [5]), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~50_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~50 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[5]~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y16_N13 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~53 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~53_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout & (\z80_|alu_|db[5]~24_combout & ((\z80_|reg_file_|b2v_latch_af2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # +// (!\z80_|execute_|ctl_reg_in_hi~12_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .datab(\z80_|alu_|db[5]~24_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~53_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~53 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[5]~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y15_N19 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X35_Y15_N17 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~54 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~54_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (\z80_|reg_file_|b2v_latch_wz_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [5]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [5]), + .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~54_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~54 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp1[5]~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y16_N3 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y16_N21 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~52 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~52_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [5]), + .datad(\z80_|reg_file_|b2v_latch_iy_hi|latch [5]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~52_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~52 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[5]~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y16_N5 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X37_Y16_N19 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~51 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~51_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (\z80_|reg_file_|b2v_latch_bc2_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [5]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_bc_hi|latch [5]), + .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~51_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~51 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp1[5]~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~55 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~55_combout = (\z80_|reg_file_|gdfx_temp1[5]~53_combout & (\z80_|reg_file_|gdfx_temp1[5]~54_combout & (\z80_|reg_file_|gdfx_temp1[5]~52_combout & \z80_|reg_file_|gdfx_temp1[5]~51_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[5]~53_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[5]~54_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[5]~52_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[5]~51_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~55_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~55 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[5]~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y15_N27 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N26 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[5]~14 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[5]~14_combout = (\z80_|execute_|ctl_reg_gp_we~8_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [5]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [5]), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[5]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[5]~14 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[5]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y15_N15 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N28 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_hi|latch[5]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_de_hi|latch[5]~feeder_combout = \z80_|reg_file_|gdfx_temp1[5]~57_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_de_hi|latch[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[5]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y15_N29 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_de_hi|latch[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~49 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~49_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [5]), + .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [5]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~49_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~49 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[5]~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y15_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~56 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~56_combout = (\z80_|reg_file_|gdfx_temp1[5]~50_combout & (\z80_|reg_file_|gdfx_temp1[5]~55_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[5]~14_combout & \z80_|reg_file_|gdfx_temp1[5]~49_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[5]~50_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[5]~55_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|db[5]~14_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[5]~49_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~56_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~56 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[5]~56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~57 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~57_combout = ((\z80_|reg_file_|gdfx_temp1[5]~56_combout & ((\z80_|reg_file_|db_hi_as[5]~15_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[5]~15_combout ), + .datab(\z80_|execute_|ctl_sw_4u~6_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[5]~56_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~57 .lut_mask = 16'hBF0F; +defparam \z80_|reg_file_|gdfx_temp1[5]~57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N14 +cycloneive_lcell_comb \z80_|alu_|db[5]~23 ( +// Equation(s): +// \z80_|alu_|db[5]~23_combout = (\z80_|alu_control_|db[5]~15_combout & ((\z80_|reg_file_|gdfx_temp1[5]~57_combout ) # ((!\z80_|execute_|ctl_reg_out_hi~7_combout )))) # (!\z80_|alu_control_|db[5]~15_combout & (!\z80_|execute_|ctl_sw_2d~13_combout & +// ((\z80_|reg_file_|gdfx_temp1[5]~57_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) + + .dataa(\z80_|alu_control_|db[5]~15_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .datac(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .datad(\z80_|execute_|ctl_sw_2d~13_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[5]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[5]~23 .lut_mask = 16'h8ACF; +defparam \z80_|alu_|db[5]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N14 +cycloneive_lcell_comb \z80_|alu_|db[5]~24 ( +// Equation(s): +// \z80_|alu_|db[5]~24_combout = ((\z80_|alu_|db[5]~23_combout & ((\z80_|alu_|db_high[1]~19_combout ) # (!\z80_|execute_|ctl_alu_oe~11_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|alu_|db[5]~23_combout ), + .datab(\z80_|alu_|db_high[1]~19_combout ), + .datac(\z80_|alu_|db[7]~9_combout ), + .datad(\z80_|execute_|ctl_alu_oe~11_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[5]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[5]~24 .lut_mask = 16'h8FAF; +defparam \z80_|alu_|db[5]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N26 +cycloneive_lcell_comb \z80_|sw1_|db_down[5]~0 ( +// Equation(s): +// \z80_|sw1_|db_down[5]~0_combout = (\z80_|bus_control_|db[5]~15_combout ) # ((\z80_|execute_|ctl_sw_1d~6_combout & ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|execute_|ctl_66_oe~2_combout )))) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|execute_|ctl_sw_1d~6_combout ), + .datac(\z80_|bus_control_|db[5]~15_combout ), + .datad(\z80_|execute_|ctl_66_oe~2_combout ), + .cin(gnd), + .combout(\z80_|sw1_|db_down[5]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sw1_|db_down[5]~0 .lut_mask = 16'hF8FC; +defparam \z80_|sw1_|db_down[5]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N22 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_36 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout = (\z80_|execute_|ctl_flags_bus~combout & ((\z80_|alu_control_|db[5]~15_combout ) # ((\z80_|alu_|db_high[1]~19_combout & \z80_|execute_|ctl_flags_alu~15_combout )))) # (!\z80_|execute_|ctl_flags_bus~combout +// & (\z80_|alu_|db_high[1]~19_combout & (\z80_|execute_|ctl_flags_alu~15_combout ))) + + .dataa(\z80_|execute_|ctl_flags_bus~combout ), + .datab(\z80_|alu_|db_high[1]~19_combout ), + .datac(\z80_|execute_|ctl_flags_alu~15_combout ), + .datad(\z80_|alu_control_|db[5]~15_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_36 .lut_mask = 16'hEAC0; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y15_N23 +dffeas \z80_|alu_flags_|flags_yf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_flags_xy_we~18_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|flags_yf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|flags_yf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|flags_yf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N26 +cycloneive_lcell_comb \z80_|alu_control_|db[5]~13 ( +// Equation(s): +// \z80_|alu_control_|db[5]~13_combout = (\z80_|execute_|ctl_flags_oe~2_combout & (\z80_|alu_flags_|flags_yf~q & ((\z80_|alu_control_|out[6]~2_combout ) # (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout )))) # (!\z80_|execute_|ctl_flags_oe~2_combout & +// ((\z80_|alu_control_|out[6]~2_combout ) # ((\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout )))) + + .dataa(\z80_|execute_|ctl_flags_oe~2_combout ), + .datab(\z80_|alu_control_|out[6]~2_combout ), + .datac(\z80_|alu_flags_|flags_yf~q ), + .datad(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[5]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[5]~13 .lut_mask = 16'hF5C4; +defparam \z80_|alu_control_|db[5]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N8 +cycloneive_lcell_comb \z80_|alu_control_|db[5]~14 ( +// Equation(s): +// \z80_|alu_control_|db[5]~14_combout = (\z80_|sw1_|db_down[5]~0_combout & (\z80_|alu_control_|db[5]~13_combout & ((\z80_|reg_file_|gdfx_temp0[5]~72_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) + + .dataa(\z80_|sw1_|db_down[5]~0_combout ), + .datab(\z80_|alu_control_|db[5]~13_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[5]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[5]~14 .lut_mask = 16'h8088; +defparam \z80_|alu_control_|db[5]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N14 +cycloneive_lcell_comb \z80_|alu_control_|db[5]~15 ( +// Equation(s): +// \z80_|alu_control_|db[5]~15_combout = ((\z80_|alu_control_|db[5]~14_combout & ((\z80_|alu_|db[5]~24_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) + + .dataa(\z80_|alu_|db[5]~24_combout ), + .datab(\z80_|execute_|ctl_sw_2u~7_combout ), + .datac(\z80_|alu_control_|db[5]~14_combout ), + .datad(\z80_|alu_control_|db[6]~11_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[5]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[5]~15 .lut_mask = 16'hB0FF; +defparam \z80_|alu_control_|db[5]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y17_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a29 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[5]~77_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_first_bit_number = 5; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y15_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a13 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[5]~77_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_bit_number = 5; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y19_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a21 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[5]~77_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_first_bit_number = 5; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y22_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a5 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[5]~77_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_bit_number = 5; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N28 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ) # +// ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout & +// !\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10 .lut_mask = 16'hCCB8; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N18 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout & +// (\ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout )) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ))))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11 .lut_mask = 16'hAFC0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y31_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a13 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_bit_number = 5; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init3 = 2048'h990442000864A0284030400454782424440404007E404808A4005448387E547C8004420800620824402040024A1242124204044008404208420A4A42424A1242020028008000524A024A4A284252446240001000101042000054265C7E0600007FAF5CA001C181BE0C02418447B1D88BAA85409896BC7C0E5FAC2529CB69A4038E2564731F88FE730045956C357C5ECF7EF8591DF2A8ACFFBFEEF268CD9B51238594AF691A9B8640983B7F76AAB97209EA6257389992FFE684926E0B19FA338B8489D73811171D5C9FF3DCFFFFFF8002000780101F3F4035A0CDED99F79A4775854F179F7D7DBBCF81B2F6421FF684CA6AF85894D29B9D3ACCBA3F27D9DC9911; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init2 = 2048'h5B438D714D4E3DD115E8BD1286EAB5FA1D71BD8F4508BD4BDC8838F9D27B552259BCEFFBB68A6FF529B3B0D92970010BBB6C7D872421210E190E1CCC47A485EAD2F8735647315839EF6F683C64773FC73464D5FE354936D50823A5DAEBEBDBCC6CAFF2622B8D518F63C6030424188FD357718970D25A30CD0731E532DB23002D02C12B12378356DE2C52041CA7A320C51E0D7CA9F5D575775D57FD75DDFDF75FFFDFFFD75F145247F03A0AE7F1E1EB2D5A99D2444108C6A5979B7CC26ABCC241EA4C912568003BB493CE04FF086C188980052BF6ABAAA2FD5D658000011277EB924C10EFAF3CB9B62486512344C61ADE6F15AB67F335A52513FF05AFAEEE8400; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 2048'h0C840083AD485153ACD3C035591630199B8C096CE4DC557D6D55FCCD738573D6E0948817C496E9DE8EA1F88F627B7460106691CC452DB9799E59A5D003733C4EA1BCE33AD2D8BE40A4E5BB7D7BBEC2CEADBBC8B6F87A4A56FBE0B891DE57E4C64EF9AD87727C49CFE7C5DE942B72AC7F6D97DE18920777FDDEE9EB11122A4E18F5569FDE08906765428FB9E6F89FBF0DEAA6064637BCA63FD02E273E5557F0548662C97BC2E8D3FFDB26D23E87BFD97E635A6560CFD93F8EED26E30C70DE8633D6B97C86DF7D9BEDFB99E36B6658F16C6DEFBDD5DF728D6209C852C37FE67CFF32EE4CCCECC64F7E6225FC99EC64C3B6DD7DED0FD7CCEA3BF09A006ECDD1009E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'hA9C9CE3AECF7BE27C000000A8ABA95251B309A60B9DDC19EC3E391458CBB53CA00A85E3C5AAE2C49DDC2F6C7B013DACB319A769818A1081A7389F711D76A09BCBED23D9A99FF9B77183697955D76BF0E0008822742DA45B883C9193DAF09424501859565800698515E10A8189EE9B323E35CE7388D73C6E7A50D0DE6739C73AC538D134115D860ADA57B5B868E54393B1E31E762062577697D57E8464340420E9434CCA34CC9A1CB1FAACC56168071EAC113F5265D5F6A45A098D604A820508C4EA47F9A7E46083716911B0D585CE937B530218E8D2AD3777EE7D3B4BC56C29ADB46809D15D185F8809229B150C29C8081174CA6173B99703DA466629005C604; +// synopsys translate_on + +// Location: M9K_X33_Y1_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a5 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_bit_number = 5; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init3 = 2048'hE10F8B8C100323720BEBBDEBB81DF13FF97B252E2CB4F27BA091FBD0002D1A611E1EDBBC716D44D2912B80041C44558060CFCF15955C0D780DD5E71393920844F25E16C87C5D0308EEC52C011514BBC13AFA1028924D0C7CE738105BD47A10AA5B5C1D9D4193E4339F492B0E1A64E13AE35BE6B67AC8057BDACC155F14E906A017A1841358335450D4B26CD2A21B3D8F2211080B81EC040D7FA0B51CD48008112508062020A02490900092D2040259108806A328F4006D2AA514B42FB006ECCCCB9A360865678449975A8AE72B5C0F7BA800C1B5DC55D7D6FE2EF4EED85D00AB111821321BA426A4FE4956B43595832C271E83E060341AE5F2023FC808177383; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init2 = 2048'h1A2955372D510AC266A5445146E27000020C320FAE1557E37154040A13202DC6F40B840FB9A59B6DBB296562CB6220EFBE99D2776A202044D9101006FD221D305519198C859000004012AFF4FB060307C92BB732203BFDFEFFFFFFDFFF87FCFFFBFFEFF03FFE0FFFBFAFE0FF80787FFF7FFF83F7F87003FFBFFFFBFFFBFF0FFC0FF81FFF7FFBFFDFFFBFFFE1FF0086F3141AAB6005810A0621595A893F9D85983B9254954341968BAC8C141C90938C05B2C9CD267E11650407375FEDD6A2FEB346AAF6CFDC0791AA97B741995A3B3981E06D1A44D3711955197BB9910FCA20744915C84D6C24BAF53929814CA8A4697E8F4201145AE7415DC122A5F010436107; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048'h02E84F969E3C800AC610D276182020227809001A50DDDBA3487BB6AE802BA06509312DA0E620656EAF24D57C08FFB14D289613DC32083803B84DC6415FD5EDC000300A8D128FA20030ACCBAFA237B7024504D36A4BA26081137F059E78991154FE2AC2A884A8CC7FBBB21C851CC92B12E15593C0C020FFEE066558590E882D5B67459F1A8C3240FE4E6A8D028C0C088FCF471D400A19B38211004DD122212288B111114514CB11840E04828849C621392041163C00808C67223422F00110201DD18FCFFFF3FFE7F9FFFFFFF82C0B422D214711E08904524A069491774E663F48F665955B4E2C63DAC0078652D10120900298F7EE380092442AFD400BEC43C003; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'hB5D49EA9D7036A45AA9E870B8E8016720C7C3102AE925262492C84584942D209042216E0216C85B8912250B7157D5955AD406CB685BBF071B47D5193363C1CECAFE59E91BF11498940A0944996D47EE8D7E3A4EAE611AE19A965D01BA86B55E9C52A6A379A382C6C265FB0DA01396D0800C0046405C06F466DD18C4DD7655CD4E7622EC485808C841D64B737041FF68813B149A41531A0A692FB14AE2E5B49D49CDCADCF90E7BD88125BCE706BF6D04AABFC1C001163DC6EFF7FD3230303030000000000000000000008400000000000000000000000000030600000100007E00220000000000000080040004023AD496997B8C0077B886EEF161CF2298A091B; +// synopsys translate_on + +// Location: M9K_X33_Y25_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a13 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(gnd), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[5]~77_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_bit_number = 5; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_first_bit_number = 5; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y28_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a5 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[5]~77_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a5_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_bit_number = 5; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_first_bit_number = 5; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init3 = 2048'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF80000001C000000160F000FF70C0007F78C00000F05001007870010010000000000800000038000000F000000070000000300000006000000000000040000000F00000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000000001D108000BEDA9FA9698A000000000000000000000000FFFFFFFF408102048004188297E014DA9FA9E9CA00000000000000000000000000000000FFFFFFFC800400CA972208DA9FA9CD8E00000000000000000000000000000000FFFFFFFC8004046A97A289FA9FA9CDC20000000000000000000000007FFFFFFC8000000280040E2A97A2997A9DA9CFC20000000000000000000000007FFFFFFE8000000280042EB28002BE369DA9274200000000000000000000000040810206BFFFFFFE9FE430A29D82AC3E8009E34A000000000000000000000000000000023FFFFFFC9FE4B1829FA2800E8009436A; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048'h9FE8334E88F827C697F88D1600A80A44809E8FC2B86999C2B85B3A82B1D32A869FE8336A88F807CA97F88F96A0A80EC2838E8D42B9E98FC2B86B3B82B0D7B2D2800832E288F827CA97F88B82A0080EC683869542B939B8C2B1AB0F8290B730C2800826EA8878078297F88AD2A0280EC283E694C2B83A3BC2A3AB3E8291A316AA800826EE881807C69DE8ABD6A0280BC282209CD2BA2A3D42A2737F82918314E2800806E6981805C69D48AED6A1E80BCA82709FC2BB223DC2A07B7F8295DF11C2800886E6980805869848AAC6A1E42DC281789DC2BBAA3DC6A02B7582955F00928008A6EE98082D9618088AC8A0F40FC289E89DC2BBCA3DC2A18B7782154F02F0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'h174F0870801C870281E2C982A801460297E5AC0288F318023FFFFFFC0000000297DF094A8094870281D6C082AC01460293FDA89288D31902BFFFFFFE40810106879F8D228C8685028016C082AC014642B3FCA80288D10F02800000027FFFFFFE879F893284DEC9028000408AAC014C02937DA00288D10F02800000027FFFFFFC841FA902804E81068BC04292AC0145E29379B00288D11F02FFFFFFFC0000000084FE89328166C1028BE05282AE4144829179B20288511F02FFFFFFFC0000000084F283328516850A88204602874364829179B08280513E0240810104FFFFFFFF843A8302853685828800560287476C928039B00200413E0000000000FFFFFFFF; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N20 +cycloneive_lcell_comb \Mux2~0 ( +// Equation(s): +// \Mux2~0_combout = (\Selector3~0_combout & (((\ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout )) # (!\z80_|address_pins_|abus[14]~23_combout ))) # (!\Selector3~0_combout & (\z80_|address_pins_|abus[14]~23_combout & +// ((\ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout )))) + + .dataa(\Selector3~0_combout ), + .datab(\z80_|address_pins_|abus[14]~23_combout ), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout ), + .cin(gnd), + .combout(\Mux2~0_combout ), + .cout()); +// synopsys translate_off +defparam \Mux2~0 .lut_mask = 16'hE6A2; +defparam \Mux2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N26 +cycloneive_lcell_comb \Mux2~1 ( +// Equation(s): +// \Mux2~1_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\Mux2~0_combout )))) # (!\z80_|address_pins_|abus[14]~23_combout & ((\Mux2~0_combout & (\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout )) # (!\Mux2~0_combout & +// ((\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ))))) + + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ), + .datad(\Mux2~0_combout ), + .cin(gnd), + .combout(\Mux2~1_combout ), + .cout()); +// synopsys translate_off +defparam \Mux2~1 .lut_mask = 16'hEE50; +defparam \Mux2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N8 +cycloneive_lcell_comb \D[5]~87 ( +// Equation(s): +// \D[5]~87_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [15] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\Mux2~1_combout ))))) # +// (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout )) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout ), + .datac(\Mux2~1_combout ), + .datad(\z80_|address_pins_|DFFE_apin_latch [15]), + .cin(gnd), + .combout(\D[5]~87_combout ), + .cout()); +// synopsys translate_off +defparam \D[5]~87 .lut_mask = 16'hCCE4; +defparam \D[5]~87 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N4 +cycloneive_lcell_comb \D[5]~68 ( +// Equation(s): +// \D[5]~68_combout = (\D[5]~67_combout & (\D[5]~87_combout & ((\z80_|data_pins_|dout [5]) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout )))) # (!\D[5]~67_combout & ((\z80_|data_pins_|dout [5]) # ((!\z80_|pin_control_|bus_db_pin_oe~15_combout )))) + + .dataa(\D[5]~67_combout ), + .datab(\z80_|data_pins_|dout [5]), + .datac(\D[5]~87_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .cin(gnd), + .combout(\D[5]~68_combout ), + .cout()); +// synopsys translate_off +defparam \D[5]~68 .lut_mask = 16'hC4F5; +defparam \D[5]~68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N12 +cycloneive_lcell_comb \D[5]~77 ( +// Equation(s): +// \D[5]~77_combout = (\D[5]~68_combout ) # (!\D[0]~84_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\D[5]~68_combout ), + .datad(\D[0]~84_combout ), + .cin(gnd), + .combout(\D[5]~77_combout ), + .cout()); +// synopsys translate_off +defparam \D[5]~77 .lut_mask = 16'hF0FF; +defparam \D[5]~77 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N16 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[5] ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [5] = (\D[5]~77_combout & ((\z80_|pin_control_|bus_db_pin_re~combout ) # ((\z80_|execute_|ctl_bus_db_we~7_combout & \z80_|bus_control_|db[5]~15_combout )))) # (!\D[5]~77_combout & +// (((\z80_|execute_|ctl_bus_db_we~7_combout & \z80_|bus_control_|db[5]~15_combout )))) + + .dataa(\D[5]~77_combout ), + .datab(\z80_|pin_control_|bus_db_pin_re~combout ), + .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datad(\z80_|bus_control_|db[5]~15_combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [5]), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[5] .lut_mask = 16'hF888; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[5] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y13_N25 +dffeas \z80_|data_pins_|dout[5] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [5]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|data_pins_|dout [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|data_pins_|dout[5] .is_wysiwyg = "true"; +defparam \z80_|data_pins_|dout[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N10 +cycloneive_lcell_comb \z80_|bus_control_|db[5]~14 ( +// Equation(s): +// \z80_|bus_control_|db[5]~14_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [5]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_bus_db_oe~combout ), + .datac(\z80_|bus_control_|db[0]~4_combout ), + .datad(\z80_|data_pins_|dout [5]), + .cin(gnd), + .combout(\z80_|bus_control_|db[5]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[5]~14 .lut_mask = 16'hF030; +defparam \z80_|bus_control_|db[5]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N18 +cycloneive_lcell_comb \z80_|bus_control_|db[5]~15 ( +// Equation(s): +// \z80_|bus_control_|db[5]~15_combout = ((\z80_|bus_control_|db[5]~14_combout & ((\z80_|alu_control_|db[5]~15_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) + + .dataa(\z80_|bus_control_|db[0]~6_combout ), + .datab(\z80_|alu_control_|db[5]~15_combout ), + .datac(\z80_|bus_control_|db[5]~14_combout ), + .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[5]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[5]~15 .lut_mask = 16'hD5F5; +defparam \z80_|bus_control_|db[5]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y16_N17 +dffeas \z80_|ir_|opcode[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|bus_control_|db[5]~15_combout ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|ir_|opcode [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|ir_|opcode[5] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~8 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~8_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal9~0_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal9~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~8 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_mRead~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_we~8_combout = (\z80_|sequencer_|M5~q & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|execute_|ctl_mRead~8_combout ) # (\z80_|pla_decode_|Equal9~1_combout )))) + + .dataa(\z80_|sequencer_|M5~q ), + .datab(\z80_|execute_|ctl_mRead~8_combout ), + .datac(\z80_|pla_decode_|Equal9~1_combout ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_we~8 .lut_mask = 16'h00A8; +defparam \z80_|execute_|ctl_bus_db_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y15_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_we~4_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mWrite~6_combout ) # ((\z80_|pla_decode_|Equal21~0_combout & \z80_|pla_decode_|Equal24~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal21~0_combout ), + .datab(\z80_|pla_decode_|Equal24~0_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ctl_mWrite~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_we~4 .lut_mask = 16'hF080; +defparam \z80_|execute_|ctl_bus_db_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_we~6_combout = (\z80_|execute_|ctl_bus_db_we~4_combout ) # (((!\z80_|execute_|ctl_apin_mux~0_combout ) # (!\z80_|execute_|ctl_sw_2u~3_combout )) # (!\z80_|execute_|ctl_bus_db_we~5_combout )) + + .dataa(\z80_|execute_|ctl_bus_db_we~4_combout ), + .datab(\z80_|execute_|ctl_bus_db_we~5_combout ), + .datac(\z80_|execute_|ctl_sw_2u~3_combout ), + .datad(\z80_|execute_|ctl_apin_mux~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_we~6 .lut_mask = 16'hBFFF; +defparam \z80_|execute_|ctl_bus_db_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout = (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal8~0_combout & \z80_|execute_|ctl_ir_we~4_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~0_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|pla_decode_|Equal8~0_combout ), + .datad(\z80_|execute_|ctl_ir_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_we~3_combout = (\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_iorw~10_combout ) # (\z80_|execute_|ctl_mWrite~7_combout )))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ), + .datac(\z80_|execute_|ctl_iorw~10_combout ), + .datad(\z80_|execute_|ctl_mWrite~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_we~3 .lut_mask = 16'hEEEC; +defparam \z80_|execute_|ctl_bus_db_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_we~2_combout = (\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|pla_decode_|Equal13~2_combout ) # ((\z80_|execute_|ctl_mRead~8_combout ) # (\z80_|execute_|ctl_mWrite~7_combout )))) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ctl_mRead~8_combout ), + .datad(\z80_|execute_|ctl_mWrite~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_we~2 .lut_mask = 16'hCCC8; +defparam \z80_|execute_|ctl_bus_db_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_we~7_combout = (\z80_|execute_|ctl_bus_db_we~8_combout ) # ((\z80_|execute_|ctl_bus_db_we~6_combout ) # ((\z80_|execute_|ctl_bus_db_we~3_combout ) # (\z80_|execute_|ctl_bus_db_we~2_combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_we~8_combout ), + .datab(\z80_|execute_|ctl_bus_db_we~6_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~3_combout ), + .datad(\z80_|execute_|ctl_bus_db_we~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_we~7 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_bus_db_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~66 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][0]~66_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|zx_keyboard_|shifted~q )) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|shifted~q ), .datad(gnd), .cin(gnd), - .combout(\z80_|execute_|ctl_apin_mux~2_combout ), + .combout(\ula_|zx_keyboard_|keys[5][0]~66_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_apin_mux~2 .lut_mask = 16'h8F8F; -defparam \z80_|execute_|ctl_apin_mux~2 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[5][0]~66 .lut_mask = 16'hCECE; +defparam \ula_|zx_keyboard_|keys[5][0]~66 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y16_N18 +// Location: LCCOMB_X29_Y8_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~80 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][0]~80_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [0]))) # (!\ula_|ps2_keyboard_|shiftreg [4] & +// (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [0]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][0]~80_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][0]~80 .lut_mask = 16'h1008; +defparam \ula_|zx_keyboard_|keys[5][0]~80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~81 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][0]~81_combout = (\ula_|zx_keyboard_|keys[5][0]~80_combout & (\ula_|ps2_keyboard_|shiftreg [2] $ (\ula_|ps2_keyboard_|shiftreg [4]))) + + .dataa(\ula_|zx_keyboard_|keys[5][0]~80_combout ), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][0]~81_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][0]~81 .lut_mask = 16'h0AA0; +defparam \ula_|zx_keyboard_|keys[5][0]~81 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~82 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][0]~82_combout = (\ula_|zx_keyboard_|keys[6][1]~39_combout & ((\ula_|zx_keyboard_|keys[5][0]~81_combout & (!\ula_|zx_keyboard_|keys[5][0]~66_combout )) # (!\ula_|zx_keyboard_|keys[5][0]~81_combout & +// ((\ula_|zx_keyboard_|keys[5][0]~q ))))) # (!\ula_|zx_keyboard_|keys[6][1]~39_combout & (((\ula_|zx_keyboard_|keys[5][0]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][0]~66_combout ), + .datab(\ula_|zx_keyboard_|keys[6][1]~39_combout ), + .datac(\ula_|zx_keyboard_|keys[5][0]~q ), + .datad(\ula_|zx_keyboard_|keys[5][0]~81_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][0]~82_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][0]~82 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[5][0]~82 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y8_N5 +dffeas \ula_|zx_keyboard_|keys[5][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[5][0]~82_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[5][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[5][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~84 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][0]~84_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|zx_keyboard_|shifted~q )) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|zx_keyboard_|shifted~q ), + .datac(gnd), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][0]~84_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][0]~84 .lut_mask = 16'hFF22; +defparam \ula_|zx_keyboard_|keys[4][0]~84 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~83 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][0]~83_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [5] $ (\ula_|ps2_keyboard_|shiftreg [3])))) # (!\ula_|ps2_keyboard_|shiftreg [1] & +// (!\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [0]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][0]~83_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][0]~83 .lut_mask = 16'h0148; +defparam \ula_|zx_keyboard_|keys[4][0]~83 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~85 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][0]~85_combout = (\ula_|zx_keyboard_|keys[4][0]~83_combout & ((\ula_|zx_keyboard_|keys[5][1]~35_combout & (!\ula_|zx_keyboard_|keys[4][0]~84_combout )) # (!\ula_|zx_keyboard_|keys[5][1]~35_combout & +// ((\ula_|zx_keyboard_|keys[4][0]~q ))))) # (!\ula_|zx_keyboard_|keys[4][0]~83_combout & (((\ula_|zx_keyboard_|keys[4][0]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[4][0]~84_combout ), + .datab(\ula_|zx_keyboard_|keys[4][0]~83_combout ), + .datac(\ula_|zx_keyboard_|keys[4][0]~q ), + .datad(\ula_|zx_keyboard_|keys[5][1]~35_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][0]~85_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][0]~85 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[4][0]~85 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y10_N21 +dffeas \ula_|zx_keyboard_|keys[4][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[4][0]~85_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[4][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[4][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N14 +cycloneive_lcell_comb \D[0]~42 ( +// Equation(s): +// \D[0]~42_combout = (\z80_|address_pins_|abus[12]~21_combout & (((\z80_|address_pins_|abus[13]~20_combout )) # (!\ula_|zx_keyboard_|keys[5][0]~q ))) # (!\z80_|address_pins_|abus[12]~21_combout & (!\ula_|zx_keyboard_|keys[4][0]~q & +// ((\z80_|address_pins_|abus[13]~20_combout ) # (!\ula_|zx_keyboard_|keys[5][0]~q )))) + + .dataa(\z80_|address_pins_|abus[12]~21_combout ), + .datab(\ula_|zx_keyboard_|keys[5][0]~q ), + .datac(\z80_|address_pins_|abus[13]~20_combout ), + .datad(\ula_|zx_keyboard_|keys[4][0]~q ), + .cin(gnd), + .combout(\D[0]~42_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~42 .lut_mask = 16'hA2F3; +defparam \D[0]~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][0]~78 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][0]~78_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|zx_keyboard_|keys[1][4]~23_combout & \ula_|ps2_keyboard_|shiftreg [3]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|zx_keyboard_|keys[1][4]~23_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][0]~78_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][0]~78 .lut_mask = 16'h1000; +defparam \ula_|zx_keyboard_|keys[1][0]~78 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][0]~79 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][0]~79_combout = (\ula_|zx_keyboard_|keys[1][0]~78_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[1][0]~78_combout & ((\ula_|zx_keyboard_|keys[1][0]~q ))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[1][0]~q ), + .datad(\ula_|zx_keyboard_|keys[1][0]~78_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][0]~79_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][0]~79 .lut_mask = 16'h55F0; +defparam \ula_|zx_keyboard_|keys[1][0]~79 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y9_N27 +dffeas \ula_|zx_keyboard_|keys[1][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[1][0]~79_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[1][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[1][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][0]~76 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][0]~76_combout = (\ula_|zx_keyboard_|keys[3][1]~26_combout & ((\ula_|zx_keyboard_|keys[3][0]~75_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][0]~75_combout & ((\ula_|zx_keyboard_|keys[3][0]~q +// ))))) # (!\ula_|zx_keyboard_|keys[3][1]~26_combout & (((\ula_|zx_keyboard_|keys[3][0]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[3][1]~26_combout ), + .datac(\ula_|zx_keyboard_|keys[3][0]~q ), + .datad(\ula_|zx_keyboard_|keys[3][0]~75_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][0]~76_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][0]~76 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[3][0]~76 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y9_N13 +dffeas \ula_|zx_keyboard_|keys[3][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[3][0]~76_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[3][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[3][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][0]~77 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][0]~77_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (((\ula_|zx_keyboard_|keys[2][0]~q )))) # (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[2][1]~24_combout & (!\ula_|zx_keyboard_|released~q )) # +// (!\ula_|zx_keyboard_|keys[2][1]~24_combout & ((\ula_|zx_keyboard_|keys[2][0]~q ))))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|zx_keyboard_|keys[2][0]~q ), + .datad(\ula_|zx_keyboard_|keys[2][1]~24_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][0]~77_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][0]~77 .lut_mask = 16'hD1F0; +defparam \ula_|zx_keyboard_|keys[2][0]~77 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y9_N11 +dffeas \ula_|zx_keyboard_|keys[2][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[2][0]~77_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[2][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[2][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N28 +cycloneive_lcell_comb \D[0]~40 ( +// Equation(s): +// \D[0]~40_combout = (\ula_|zx_keyboard_|keys[3][0]~q & (\z80_|address_pins_|abus[11]~19_combout & ((\z80_|address_pins_|abus[10]~24_combout ) # (!\ula_|zx_keyboard_|keys[2][0]~q )))) # (!\ula_|zx_keyboard_|keys[3][0]~q & +// ((\z80_|address_pins_|abus[10]~24_combout ) # ((!\ula_|zx_keyboard_|keys[2][0]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[3][0]~q ), + .datab(\z80_|address_pins_|abus[10]~24_combout ), + .datac(\z80_|address_pins_|abus[11]~19_combout ), + .datad(\ula_|zx_keyboard_|keys[2][0]~q ), + .cin(gnd), + .combout(\D[0]~40_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~40 .lut_mask = 16'hC4F5; +defparam \D[0]~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr0~0 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr0~0_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [0])) # (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg +// [2])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr0~0 .lut_mask = 16'h1012; +defparam \ula_|zx_keyboard_|WideOr0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys~71 ( +// Equation(s): +// \ula_|zx_keyboard_|keys~71_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (((!\ula_|zx_keyboard_|WideOr0~0_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [4] & (((!\ula_|ps2_keyboard_|shiftreg [3])) # (!\ula_|zx_keyboard_|keys[6][4]~45_combout ))) + + .dataa(\ula_|zx_keyboard_|keys[6][4]~45_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|zx_keyboard_|WideOr0~0_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys~71_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys~71 .lut_mask = 16'h13DF; +defparam \ula_|zx_keyboard_|keys~71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~70 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][3]~70_combout = (\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [6]) + + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][3]~70_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][3]~70 .lut_mask = 16'hAA00; +defparam \ula_|zx_keyboard_|keys[4][3]~70 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~72 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][0]~72_combout = (\ula_|zx_keyboard_|keys[0][0]~13_combout & (((!\ula_|zx_keyboard_|keys~71_combout & \ula_|zx_keyboard_|keys[4][3]~70_combout )) # (!\ula_|zx_keyboard_|extended~q ))) + + .dataa(\ula_|zx_keyboard_|extended~q ), + .datab(\ula_|zx_keyboard_|keys~71_combout ), + .datac(\ula_|zx_keyboard_|keys[0][0]~13_combout ), + .datad(\ula_|zx_keyboard_|keys[4][3]~70_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][0]~72_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][0]~72 .lut_mask = 16'h7050; +defparam \ula_|zx_keyboard_|keys[0][0]~72 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr4~0 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr4~0_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (((\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [1])))) # (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [4] & +// (!\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr4~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr4~0 .lut_mask = 16'hA004; +defparam \ula_|zx_keyboard_|WideOr4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys~73 ( +// Equation(s): +// \ula_|zx_keyboard_|keys~73_combout = (!\ula_|zx_keyboard_|extended~q & (((\ula_|ps2_keyboard_|shiftreg [3]) # (!\ula_|zx_keyboard_|WideOr4~0_combout )) # (!\ula_|zx_keyboard_|keys[4][1]~29_combout ))) + + .dataa(\ula_|zx_keyboard_|extended~q ), + .datab(\ula_|zx_keyboard_|keys[4][1]~29_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|zx_keyboard_|WideOr4~0_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys~73_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys~73 .lut_mask = 16'h5155; +defparam \ula_|zx_keyboard_|keys~73 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~74 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][0]~74_combout = (\ula_|zx_keyboard_|keys[0][0]~72_combout & ((\ula_|zx_keyboard_|keys~73_combout & (\ula_|zx_keyboard_|keys[0][0]~q )) # (!\ula_|zx_keyboard_|keys~73_combout & ((!\ula_|zx_keyboard_|released~q ))))) # +// (!\ula_|zx_keyboard_|keys[0][0]~72_combout & (((\ula_|zx_keyboard_|keys[0][0]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[0][0]~72_combout ), + .datab(\ula_|zx_keyboard_|keys~73_combout ), + .datac(\ula_|zx_keyboard_|keys[0][0]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][0]~74_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][0]~74 .lut_mask = 16'hD0F2; +defparam \ula_|zx_keyboard_|keys[0][0]~74 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y8_N11 +dffeas \ula_|zx_keyboard_|keys[0][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[0][0]~74_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[0][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[0][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~2 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row~2_combout = ((\z80_|address_pins_|DFFE_apin_latch [8]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) # (!\ula_|zx_keyboard_|keys[0][0]~q ) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|keys[0][0]~q ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [8]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row~2 .lut_mask = 16'hFF3F; +defparam \ula_|zx_keyboard_|key_row~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N16 +cycloneive_lcell_comb \D[0]~41 ( +// Equation(s): +// \D[0]~41_combout = (\D[0]~40_combout & (\ula_|zx_keyboard_|key_row~2_combout & ((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][0]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[1][0]~q ), + .datab(\D[0]~40_combout ), + .datac(\ula_|zx_keyboard_|key_row~2_combout ), + .datad(\z80_|address_pins_|abus[9]~17_combout ), + .cin(gnd), + .combout(\D[0]~41_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~41 .lut_mask = 16'hC040; +defparam \D[0]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~89 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][0]~89_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][0]~89_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][0]~89 .lut_mask = 16'h0008; +defparam \ula_|zx_keyboard_|keys[6][0]~89 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~90 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][0]~90_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|zx_keyboard_|keys[6][0]~89_combout & (\ula_|zx_keyboard_|shifted~3_combout & \ula_|zx_keyboard_|keys[7][1]~21_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|zx_keyboard_|keys[6][0]~89_combout ), + .datac(\ula_|zx_keyboard_|shifted~3_combout ), + .datad(\ula_|zx_keyboard_|keys[7][1]~21_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][0]~90_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][0]~90 .lut_mask = 16'h8000; +defparam \ula_|zx_keyboard_|keys[6][0]~90 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~91 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][0]~91_combout = (\ula_|zx_keyboard_|keys[6][0]~90_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[6][0]~90_combout & (\ula_|zx_keyboard_|keys[6][0]~q )) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|keys[6][0]~90_combout ), + .datac(\ula_|zx_keyboard_|keys[6][0]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][0]~91_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][0]~91 .lut_mask = 16'h30FC; +defparam \ula_|zx_keyboard_|keys[6][0]~91 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y10_N19 +dffeas \ula_|zx_keyboard_|keys[6][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[6][0]~91_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[6][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[6][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~131 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][0]~131_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|keys[3][0]~75_combout & (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [6]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|zx_keyboard_|keys[3][0]~75_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][0]~131_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][0]~131 .lut_mask = 16'h8000; +defparam \ula_|zx_keyboard_|keys[7][0]~131 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~3 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~3_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [6]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~3 .lut_mask = 16'h000F; +defparam \ula_|zx_keyboard_|WideOr16~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~86 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][0]~86_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|zx_keyboard_|keys[5][4]~62_combout & (\ula_|zx_keyboard_|WideOr16~3_combout & \ula_|ps2_keyboard_|shiftreg [3]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|zx_keyboard_|keys[5][4]~62_combout ), + .datac(\ula_|zx_keyboard_|WideOr16~3_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][0]~86_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][0]~86 .lut_mask = 16'h4000; +defparam \ula_|zx_keyboard_|keys[7][0]~86 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~87 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][0]~87_combout = (\ula_|zx_keyboard_|keys[7][1]~21_combout & (\ula_|ps2_keyboard_|shiftreg [5] & ((\ula_|zx_keyboard_|keys[7][0]~131_combout ) # (\ula_|zx_keyboard_|keys[7][0]~86_combout )))) + + .dataa(\ula_|zx_keyboard_|keys[7][1]~21_combout ), + .datab(\ula_|zx_keyboard_|keys[7][0]~131_combout ), + .datac(\ula_|zx_keyboard_|keys[7][0]~86_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][0]~87_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][0]~87 .lut_mask = 16'hA800; +defparam \ula_|zx_keyboard_|keys[7][0]~87 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~88 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][0]~88_combout = (\ula_|zx_keyboard_|keys[7][0]~87_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[7][0]~87_combout & (\ula_|zx_keyboard_|keys[7][0]~q )) + + .dataa(\ula_|zx_keyboard_|keys[7][0]~87_combout ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[7][0]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][0]~88_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][0]~88 .lut_mask = 16'h50FA; +defparam \ula_|zx_keyboard_|keys[7][0]~88 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y10_N5 +dffeas \ula_|zx_keyboard_|keys[7][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[7][0]~88_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[7][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[7][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N12 +cycloneive_lcell_comb \D[0]~43 ( +// Equation(s): +// \D[0]~43_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\z80_|address_pins_|abus[15]~22_combout ) # (!\ula_|zx_keyboard_|keys[7][0]~q )))) # (!\z80_|address_pins_|abus[14]~23_combout & (!\ula_|zx_keyboard_|keys[6][0]~q & +// ((\z80_|address_pins_|abus[15]~22_combout ) # (!\ula_|zx_keyboard_|keys[7][0]~q )))) + + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\ula_|zx_keyboard_|keys[6][0]~q ), + .datac(\ula_|zx_keyboard_|keys[7][0]~q ), + .datad(\z80_|address_pins_|abus[15]~22_combout ), + .cin(gnd), + .combout(\D[0]~43_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~43 .lut_mask = 16'hBB0B; +defparam \D[0]~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N10 +cycloneive_lcell_comb \D[0]~44 ( +// Equation(s): +// \D[0]~44_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[0]~42_combout & (\D[0]~41_combout & \D[0]~43_combout ))) + + .dataa(\D[0]~42_combout ), + .datab(\D[0]~41_combout ), + .datac(\z80_|address_pins_|abus[0]~16_combout ), + .datad(\D[0]~43_combout ), + .cin(gnd), + .combout(\D[0]~44_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~44 .lut_mask = 16'hF8F0; +defparam \D[0]~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y17_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a24 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[0]~46_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_first_bit_number = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y18_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a16 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[0]~46_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_first_bit_number = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y15_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a8 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[0]~46_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y19_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a0 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[0]~46_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081; +// synopsys translate_on + +// Location: LCCOMB_X23_Y14_N12 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout )) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ))))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4 .lut_mask = 16'hE3E0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y14_N6 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~5 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~5_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4_combout & +// (\ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout )) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout ))))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4_combout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~5 .lut_mask = 16'hAFC0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y13_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a8 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h3C00000000000000000000000000000000000000000000000000000000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005DB824E17CAAE881C1908A79F24B7D1B4857A981A6AF39DFF5A2FEE9141EB33592D8E9B82471FDDA6791810A1C29D415CC1A8FA03444DF0083F83506BA93E8D1A1856A768D73A08418BFB25A40001DD4833DAF33BD311BB45F39667627407EF59ED569C483EB3BE1B10551B1428A6169579293ED063CAA9C6ADB0433CFC15C33AFF04C710408C20AC28B5909A229CD7D1DB4EB9A44CE0EEDBBBD391D3128AAA3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'hDDE6FC8EBE3F9F3C3DFC6E8F07BFD31D50660B1E0B2506A533CE0E340C7C745CAEC4837C2A5FECBB94C1C969FFDDFF79BFFAAFDCA8D748399ABF75558ADD02F56F6DFFF29CB70FFD25A59DFFFED7B3F7E8B4CE6FFF3EF9CEC6BAE57ABFFFCEE647B2AFF5B87AA26AFFDD317DEDCFBDFFE1A0CAD3B58877DD2F647F7DF748E7CF4693FD3C1238FFAFBD7FDF567FA8FEF024F33AFD3AABC6B105EA80272D64895FFF9FFF6E3881C81AFDCF2257FD4F8ED5257D0E9B800726B6564D2B05012F76DF636CDEB4BDFCAEEFC61DFFEFB7E26262DEF2CB9F71565824FEBF3F7BDDEABB593F1BF746FBFFC353E37263FF38A796EF39E3FD7DFEBA7FFEFFBD97ABAF09E909; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'hE629BDF93D7F5B5BAF92FBAB477E9B315DB5A310CFACC7408DF9A544B1E57AF6EFEF92C2FA4D8D4E4AC86C277338FA37BCDD9D47782DB75EFF80781BCD23D0AFCAE30B9FE6AA29FFF6F72DA73DFE4F7ACD39687B9E69C5359E9B991F0246EFFBC5595561AC64787878F5CE14C664CF9EB0CDAFFBABEF1E83358371B9ED96E5069555AFBBD3AEBFCABFBBED7A5C5FE9BD0E6A91C6E7610042695EEB08D8881B1D735AF87DAE59FABBD7DEAF8717F2B72F428F5E37E5D6E13157B99CBD2D73B9C73C563C8B02C8CC39C64DDCEA1BEEB5E7353F93786145598FE634EF1000179B345725EA43CE18F187A1DE4DAABEA97963E3A7A96B8B7CBC095BEB7CE46274D9AF; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h4ED4AE2B1650D21EAFE01E7099EFCA3094FD4D705CF6B84AE21583E13385F8650004406BD60A023AB063D4E5966EA41AA997F5A49BFCB0657A9732D28EB8217E65F627A15E1057ADEE7B9E27122A58FB2B98B1EA560390C7E87715861814E04DCB76FAB179E9619BC7E7E9C9FD801CF87DBA1EA496E829D4E62861E1AF436A7585287860729C77B6C68CAEA3033A6E84D67249B594C407B39C68B4C1C97FDEFC6BAD12FDBB525EF4F87F4A23EC13CBC0262D8899A3A290F04F41C1324045B9FCEEC890579E95D5A0A546CCCDD48577558ABE7CA36EF67A70F6A8758BDA052D5B95DE707778B17C2379847A23AE5D4BB01F36F3F44A8162566D9FB15DE7CC83F7; +// synopsys translate_on + +// Location: M9K_X22_Y28_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a0 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[0]~46_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_bit_number = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF0000000000000000000000003FF03FFC20107FFC3FF00B9C3FF007FC18000FFC3FF03FD42FF43FFC2FFC3FE01FFE7FE81FFE3FDC07FE3FFC07FE2FFC07FE0F0807FE1F18207F0F3030FD8C30383300600000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h000000000000000000000000FFFFFFFFE0408103E004044390120EAA803920C6000000000000000000000000FFFFFFFFE0408103A004005A84723CEA813930C2000000000000000000000000800000009FBF7EFD8004027A8572358A813950EA000000000000000000000000800000009FBF7EFC8005157A85733F0A8139518E0000000000000000000000009FBF7EFC800000008006113A8C73330A813919EA0000000000000000000000009FBF7EFC8000000080060022801333A2813973EA00000000000000000000000080000000DFFFFFFD9FF6022A84730366801913FE000000000000000000000000E0408102FFFFFFFD9FF60ABA84730426901913EE; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h9FF81326887812F28FF0D7C2CC6856E3894C8B62980099E28988BFC2B9EC79829FE81362887842E68FF0C7C2CCE056E2896C89E2888098E28AA8BBC299FC1AC280081372887842E69EE0C7CA8CE046E289E089E289C899E28AA8BEC2993C1AE28008837E882852C69EE0874288E046E2886099E289689FCE8AD8BFC2999C09F680088376880846C69CA88382880042A289D08DE289F098C28AF8BFC289FC88F280088376880857C29CA893C2888043A289508DE288F0D9428BF0AFC289F4888A800883F2880857829C2891C3889047F2898885E2899081428990AF8289FC8BE3800893F6880847C2DC0894E389944F62888899668918914289803582CB8C8AF3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'hCBAC80F38DA845828DF44582840124029375A4A288D108A2FFFFFFFDE0408082CAEC80968DF855828CE4408284012006917194C280510B82DFFFFFFC8000000288EC84A28FFC4586880C648A860124128179900280510F82800000009FBF7F7C8BA080BA8FEC40828808618286012C028179901280510702800000009FBF7F7C8BB081BA8CAC408289E0618286812C1281791002805007029FBF7F7C8000000089B881828CB440828BE07782868322028139909280400F029FBF7F7D8000000089A4C3928FF444828A00260A8792227281199022A0001F03E0408081FFFFFFFF89A0C1928FD440828800260687B720C280199002E0001F03E0408083FFFFFFFF; +// synopsys translate_on + +// Location: M9K_X22_Y21_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a8 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(gnd), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[0]~46_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_first_bit_number = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X23_Y14_N4 +cycloneive_lcell_comb \Selector2~0 ( +// Equation(s): +// \Selector2~0_combout = (\Selector3~0_combout & (((\ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ) # (!\z80_|address_pins_|abus[14]~23_combout )))) # (!\Selector3~0_combout & +// (\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout & (\z80_|address_pins_|abus[14]~23_combout ))) + + .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ), + .datab(\Selector3~0_combout ), + .datac(\z80_|address_pins_|abus[14]~23_combout ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ), + .cin(gnd), + .combout(\Selector2~0_combout ), + .cout()); +// synopsys translate_off +defparam \Selector2~0 .lut_mask = 16'hEC2C; +defparam \Selector2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y31_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a0 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h1EEA3633EFEA856D05BA968C1B3C30CA1788DD95D16B8F914DDDFC3EE5C69945DF7D7BF31C6072BFA7993996AB7DD2F3EE4009844CC9D6CF9E583AEC48A52F2904B57D8E0D755851232838F9B5348838530D7AF95411555D263B8CA86A5D29D7CE4B65409D6F04C5709A56C241C3BCEF07459A416EB4E8F3D73CC714F4333AFE605D53A5C955D5D1412F8361617A54446971FD187442A60FB04457857BECC3120A01FDC7FE2CBF038A61DEE5FCE2D10C8F35FBF80C05ABFF4B6935287B125E8D56F9FDFE7D64C1F4E1F5641845CD17E836B97780400C702523FA8E7C7BBD6F0666591A35ADD26B6B7E33CA56E9AB329EFA7E68F98AE7CE9507755C74C430286A; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h88537A811D4EF6CD9668CCD3E2E7A8041788DCA5F7E08AF52AF5276078304DEB75B74BB9AC3C1A492952F7EEAA0E7CF9FBEDD0FB47EEFDCC3734B816F355C913CD2E1AF14C30545297A91BED3AEAEFF8F696B5F4FC80BC6B1A2559492E9198E4A5875745B625C6CA7A7292332492D139728A689DA1AE78B6B44CE4F4A4EA5A22F331598B364EF27516CC49A4662C5E5C92ED140D96373678F833AE434698237599716B8CBAE2D3D061F2C3D6337AB435B5C2144AB6FA2F8BB51357801066B6589467DA6C480E6D19CEEA8451CEFA88FD70E7925B0302F877F87FA833FBD147E937309C08305A10187707E3D57DDE4931F1D9E97A8F378981ABBF8D7B6B7539C3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h763DD7AA7EED3F4AD4EA7491ADE6F14E6DBADD0F090A8DF34D7BAD35DD2275F0BCCF19EEF299751C919C9C13C6FB9ED711AC4DA7D947CC79E9B6323EF6CE62638CEBCB187AE5D44ECA689C9BD4E5AE544DEA7E90D186B9F335F3323877AAD54196CE81973CB555904419599375501366EC343561BCF83357F8823671393B278C1C387A7970C7F3E688673CF5975EE3E5FF105CFCCFAB725D698FB088B063063C7833830C7B2C7AFB8A8D203C312306DA0E72641FFB93D59B5EC84F44AD55F4B884735325ACC969B2EAE10A1478D866F667DDEF7BBF75E6958B6D02DC6D0F807660A229B98541E6FE734DE2280A9B57FCD5A9BEFEF7CDA5ABEB44FD73D2794D56; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'hD0734B461A36980411EB2A6C1BE76029258777EF227A8F6E84F74C4436098F67BA611013110188547995B108BB2DAE76F423A0D98845F9248BDFA45E10CA403A5E2B1A3E16869E1D37BCE906B82F401CBD467617DB34D9E0C80B5E6E10063EC4BD52921D249E377D95CFAAA309EEDAA57DA85F55DBB7048A69A4C801013948B617F7F5724D40707E6FF30002982023020449B4680C45D1CE6D8EB30A061DB8FEDD6E630C15271E48CA801988654FB501D5393392EE765C1EC95C1E4D86F18A965372B72B484E2F2664B735B69A5AB532B086BA4C62AD6D56EECBDB6984B251454845BD5B243DAED2B2489B313A35C50252AFD3E0B76FEF342335C7F1321D92FF; +// synopsys translate_on + +// Location: LCCOMB_X23_Y14_N28 +cycloneive_lcell_comb \Selector2~1 ( +// Equation(s): +// \Selector2~1_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\Selector2~0_combout )))) # (!\z80_|address_pins_|abus[14]~23_combout & ((\Selector2~0_combout & (\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout )) # +// (!\Selector2~0_combout & ((\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ))))) + + .dataa(\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ), + .datab(\z80_|address_pins_|abus[14]~23_combout ), + .datac(\Selector2~0_combout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ), + .cin(gnd), + .combout(\Selector2~1_combout ), + .cout()); +// synopsys translate_off +defparam \Selector2~1 .lut_mask = 16'hE3E0; +defparam \Selector2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y14_N30 +cycloneive_lcell_comb \D[0]~83 ( +// Equation(s): +// \D[0]~83_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [15] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~5_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\Selector2~1_combout +// ))))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~5_combout )) + + .dataa(\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~5_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [15]), + .datad(\Selector2~1_combout ), + .cin(gnd), + .combout(\D[0]~83_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~83 .lut_mask = 16'hAEA2; +defparam \D[0]~83 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y14_N14 +cycloneive_lcell_comb \D[0]~45 ( +// Equation(s): +// \D[0]~45_combout = ((\Equal2~0_combout & (\D[0]~44_combout )) # (!\Equal2~0_combout & ((\D[0]~83_combout )))) # (!\Equal2~1_combout ) + + .dataa(\Equal2~0_combout ), + .datab(\D[0]~44_combout ), + .datac(\D[0]~83_combout ), + .datad(\Equal2~1_combout ), + .cin(gnd), + .combout(\D[0]~45_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~45 .lut_mask = 16'hD8FF; +defparam \D[0]~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y14_N0 +cycloneive_lcell_comb \D[0]~46 ( +// Equation(s): +// \D[0]~46_combout = (\z80_|pin_control_|bus_db_pin_oe~15_combout & (((\D[0]~45_combout & \z80_|data_pins_|dout [0])))) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout & (((\D[0]~45_combout )) # (!\Equal2~1_combout ))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .datab(\Equal2~1_combout ), + .datac(\D[0]~45_combout ), + .datad(\z80_|data_pins_|dout [0]), + .cin(gnd), + .combout(\D[0]~46_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~46 .lut_mask = 16'hF151; +defparam \D[0]~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N26 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [0] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[0]~17_combout ) # ((\D[0]~46_combout & \z80_|pin_control_|bus_db_pin_re~combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & +// (\D[0]~46_combout & ((\z80_|pin_control_|bus_db_pin_re~combout )))) + + .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datab(\D[0]~46_combout ), + .datac(\z80_|bus_control_|db[0]~17_combout ), + .datad(\z80_|pin_control_|bus_db_pin_re~combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [0]), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] .lut_mask = 16'hECA0; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y13_N27 +dffeas \z80_|data_pins_|dout[0] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [0]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|data_pins_|dout [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|data_pins_|dout[0] .is_wysiwyg = "true"; +defparam \z80_|data_pins_|dout[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N10 +cycloneive_lcell_comb \z80_|bus_control_|db[0]~16 ( +// Equation(s): +// \z80_|bus_control_|db[0]~16_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [0]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) + + .dataa(\z80_|data_pins_|dout [0]), + .datab(\z80_|bus_control_|db[0]~4_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|bus_control_|db[0]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[0]~16 .lut_mask = 16'h8C8C; +defparam \z80_|bus_control_|db[0]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N0 +cycloneive_lcell_comb \z80_|bus_control_|db[0]~17 ( +// Equation(s): +// \z80_|bus_control_|db[0]~17_combout = ((\z80_|bus_control_|db[0]~16_combout & ((\z80_|alu_control_|db[0]~12_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) + + .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datab(\z80_|alu_control_|db[0]~12_combout ), + .datac(\z80_|bus_control_|db[0]~6_combout ), + .datad(\z80_|bus_control_|db[0]~16_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[0]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[0]~17 .lut_mask = 16'hDF0F; +defparam \z80_|bus_control_|db[0]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y13_N1 +dffeas \z80_|ir_|opcode[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|bus_control_|db[0]~17_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|ir_|opcode [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|ir_|opcode[0] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal3~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal3~2_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal52~0_combout & \z80_|pla_decode_|Equal3~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal3~1_combout ), + .datac(\z80_|pla_decode_|Equal52~0_combout ), + .datad(\z80_|pla_decode_|Equal3~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal3~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal3~2 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal3~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal43~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal43~0_combout = (\z80_|pla_decode_|Equal1~7_combout & (\z80_|pla_decode_|Equal32~0_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal3~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal1~7_combout ), + .datab(\z80_|pla_decode_|Equal32~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal3~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal43~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal43~0 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal43~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N24 +cycloneive_lcell_comb \z80_|interrupts_|test1~2 ( +// Equation(s): +// \z80_|interrupts_|test1~2_combout = (!\z80_|pla_decode_|Equal3~2_combout & (!\z80_|pla_decode_|Equal43~0_combout & (!\z80_|pla_decode_|Equal79~0_combout & !\z80_|pla_decode_|Equal36~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal3~2_combout ), + .datab(\z80_|pla_decode_|Equal43~0_combout ), + .datac(\z80_|pla_decode_|Equal79~0_combout ), + .datad(\z80_|pla_decode_|Equal36~0_combout ), + .cin(gnd), + .combout(\z80_|interrupts_|test1~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|test1~2 .lut_mask = 16'h0001; +defparam \z80_|interrupts_|test1~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N22 +cycloneive_lcell_comb \z80_|interrupts_|test1~3 ( +// Equation(s): +// \z80_|interrupts_|test1~3_combout = (!\z80_|execute_|setM1~54_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (\z80_|interrupts_|test1~2_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|execute_|setM1~54_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|interrupts_|test1~2_combout ), + .cin(gnd), + .combout(\z80_|interrupts_|test1~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|test1~3 .lut_mask = 16'h3331; +defparam \z80_|interrupts_|test1~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y13_N1 +dffeas \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|interrupts_|test1~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED .is_wysiwyg = "true"; +defparam \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N6 +cycloneive_lcell_comb \z80_|clk_delay_|SYNTHESIZED_WIRE_4 ( +// Equation(s): +// \z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (!\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|interrupts_|DFFE_inst44~q ))) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|interrupts_|DFFE_inst44~q ), + .cin(gnd), + .combout(\z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_4 .lut_mask = 16'h0100; +defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y14_N7 +dffeas \z80_|clk_delay_|SYNTHESIZED_WIRE_7 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_7 .is_wysiwyg = "true"; +defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_7 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N12 +cycloneive_lcell_comb \z80_|clk_delay_|hold_clk_iorq ( +// Equation(s): +// \z80_|clk_delay_|hold_clk_iorq~combout = (!\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q & !\z80_|clk_delay_|DFF_inst5~q ) + + .dataa(\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ), + .datab(\z80_|clk_delay_|DFF_inst5~q ), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\z80_|clk_delay_|hold_clk_iorq~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|clk_delay_|hold_clk_iorq .lut_mask = 16'h1111; +defparam \z80_|clk_delay_|hold_clk_iorq .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y13_N31 +dffeas \z80_|sequencer_|DFFE_T4_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_T4_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_T4_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_T4_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_eval_cond~0 ( +// Equation(s): +// \z80_|execute_|ctl_eval_cond~0_combout = (\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_eval_cond~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_eval_cond~0 .lut_mask = 16'h00F0; +defparam \z80_|execute_|ctl_eval_cond~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~27 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~27_combout = (\z80_|execute_|ctl_mRead~23_combout & (((!\z80_|pla_decode_|Equal38~2_combout & !\z80_|pla_decode_|Equal52~1_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|pla_decode_|Equal38~2_combout ), + .datac(\z80_|execute_|ctl_mRead~23_combout ), + .datad(\z80_|pla_decode_|Equal52~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~27 .lut_mask = 16'h5070; +defparam \z80_|execute_|ctl_mRead~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~26 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~26_combout = (\z80_|execute_|ctl_mRead~34_combout ) # ((\z80_|pla_decode_|Equal21~1_combout ) # (\z80_|pla_decode_|Equal37~0_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|pla_decode_|Equal37~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~26 .lut_mask = 16'hFFFC; +defparam \z80_|execute_|ctl_mRead~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y17_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~28 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~28_combout = (\z80_|execute_|ctl_mRead~27_combout & (\z80_|execute_|ctl_mRead~22_combout & ((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|execute_|ctl_mRead~26_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~27_combout ), + .datab(\z80_|execute_|ctl_mRead~26_combout ), + .datac(\z80_|execute_|ctl_mRead~22_combout ), + .datad(\z80_|execute_|ctl_mRead~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~28 .lut_mask = 16'h20A0; +defparam \z80_|execute_|ctl_mRead~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|nextM~6 ( +// Equation(s): +// \z80_|execute_|nextM~6_combout = (((\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal49~0_combout )) # (!\z80_|execute_|nextM~3_combout )) # (!\z80_|execute_|ixy_d~17_combout ) + + .dataa(\z80_|decode_state_|use_ixiy~combout ), + .datab(\z80_|execute_|ixy_d~17_combout ), + .datac(\z80_|execute_|nextM~3_combout ), + .datad(\z80_|pla_decode_|Equal49~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~6 .lut_mask = 16'hBF3F; +defparam \z80_|execute_|nextM~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N10 +cycloneive_lcell_comb \z80_|execute_|nextM~7 ( +// Equation(s): +// \z80_|execute_|nextM~7_combout = ((\z80_|execute_|nextM~6_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # (\z80_|execute_|ixy_d~8_combout )))) # (!\z80_|execute_|nextM~4_combout ) + + .dataa(\z80_|execute_|nextM~6_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|execute_|ixy_d~8_combout ), + .datad(\z80_|execute_|nextM~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~7 .lut_mask = 16'hA8FF; +defparam \z80_|execute_|nextM~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|nextM~8 ( +// Equation(s): +// \z80_|execute_|nextM~8_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & (((\z80_|execute_|ixy_d~8_combout & !\z80_|execute_|ctl_flags_bus~1_combout )) # (!\z80_|alu_control_|flags_cond_true~q ))) # +// (!\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & (\z80_|execute_|ixy_d~8_combout & ((!\z80_|execute_|ctl_flags_bus~1_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), + .datab(\z80_|execute_|ixy_d~8_combout ), + .datac(\z80_|alu_control_|flags_cond_true~q ), + .datad(\z80_|execute_|ctl_flags_bus~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~8 .lut_mask = 16'h0ACE; +defparam \z80_|execute_|nextM~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|nextM~9 ( +// Equation(s): +// \z80_|execute_|nextM~9_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_mWrite~4_combout & ((\z80_|execute_|ctl_mRead~9_combout ) # (\z80_|execute_|ixy_d~6_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~9_combout ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ctl_mWrite~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~9 .lut_mask = 16'hC800; +defparam \z80_|execute_|nextM~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|nextM~10 ( +// Equation(s): +// \z80_|execute_|nextM~10_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ) # ((\z80_|execute_|nextM~9_combout ) # ((\z80_|execute_|ctl_mRead~34_combout & \z80_|execute_|ixy_d~9_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|execute_|nextM~9_combout ), + .datad(\z80_|execute_|ixy_d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~10 .lut_mask = 16'hFEFA; +defparam \z80_|execute_|nextM~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N20 +cycloneive_lcell_comb \z80_|execute_|nextM~12 ( +// Equation(s): +// \z80_|execute_|nextM~12_combout = (\z80_|execute_|nextM~8_combout ) # ((\z80_|execute_|ctl_alu_op_low~46_combout ) # ((\z80_|execute_|nextM~10_combout ) # (!\z80_|execute_|nextM~11_combout ))) + + .dataa(\z80_|execute_|nextM~8_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~46_combout ), + .datac(\z80_|execute_|nextM~10_combout ), + .datad(\z80_|execute_|nextM~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~12 .lut_mask = 16'hFEFF; +defparam \z80_|execute_|nextM~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|nextM~15 ( +// Equation(s): +// \z80_|execute_|nextM~15_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & ((\z80_|execute_|ctl_mRead~5_combout ) # (!\z80_|execute_|fMRead~12_combout )))) + + .dataa(\z80_|execute_|fMRead~12_combout ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|execute_|ctl_mRead~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~15 .lut_mask = 16'hC040; +defparam \z80_|execute_|nextM~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|nextM~13 ( +// Equation(s): +// \z80_|execute_|nextM~13_combout = (\z80_|execute_|nextM~7_combout ) # ((\z80_|execute_|nextM~12_combout ) # (\z80_|execute_|nextM~15_combout )) + + .dataa(\z80_|execute_|nextM~7_combout ), + .datab(\z80_|execute_|nextM~12_combout ), + .datac(gnd), + .datad(\z80_|execute_|nextM~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~13 .lut_mask = 16'hFFEE; +defparam \z80_|execute_|nextM~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N6 +cycloneive_lcell_comb \z80_|execute_|setM1~41 ( +// Equation(s): +// \z80_|execute_|setM1~41_combout = (\z80_|execute_|setM1~40_combout & !\z80_|execute_|ctl_mWrite~7_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|setM1~40_combout ), + .datac(\z80_|execute_|ctl_mWrite~7_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|setM1~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~41 .lut_mask = 16'h0C0C; +defparam \z80_|execute_|setM1~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|nextM~5 ( +// Equation(s): +// \z80_|execute_|nextM~5_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (((!\z80_|execute_|setM1~41_combout ) # (!\z80_|execute_|setM1~47_combout )) # (!\z80_|execute_|nextM~2_combout ))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|nextM~2_combout ), + .datac(\z80_|execute_|setM1~47_combout ), + .datad(\z80_|execute_|setM1~41_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~5 .lut_mask = 16'h2AAA; +defparam \z80_|execute_|nextM~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N0 +cycloneive_lcell_comb \z80_|execute_|nextM~14 ( +// Equation(s): +// \z80_|execute_|nextM~14_combout = (((\z80_|execute_|nextM~13_combout ) # (\z80_|execute_|nextM~5_combout )) # (!\z80_|execute_|ctl_mWrite~14_combout )) # (!\z80_|execute_|ctl_mRead~28_combout ) + + .dataa(\z80_|execute_|ctl_mRead~28_combout ), + .datab(\z80_|execute_|ctl_mWrite~14_combout ), + .datac(\z80_|execute_|nextM~13_combout ), + .datad(\z80_|execute_|nextM~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~14 .lut_mask = 16'hFFF7; +defparam \z80_|execute_|nextM~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N24 +cycloneive_lcell_comb \z80_|sequencer_|ena_M ( +// Equation(s): +// \z80_|sequencer_|ena_M~combout = (\z80_|execute_|setM1~54_combout & !\z80_|execute_|nextM~14_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|setM1~54_combout ), + .datac(gnd), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|ena_M~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|ena_M .lut_mask = 16'h00CC; +defparam \z80_|sequencer_|ena_M .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y13_N25 +dffeas \z80_|sequencer_|DFFE_T1_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|ena_M~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_T1_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_T1_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_T1_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N20 +cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_13 ( +// Equation(s): +// \z80_|sequencer_|SYNTHESIZED_WIRE_13~combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|execute_|setM1~54_combout & !\z80_|execute_|nextM~14_combout )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|execute_|setM1~54_combout ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_13 .lut_mask = 16'h0030; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y13_N21 +dffeas \z80_|sequencer_|DFFE_T2_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_T2_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_T2_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_T2_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N16 +cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_14 ( +// Equation(s): +// \z80_|sequencer_|SYNTHESIZED_WIRE_14~combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|execute_|setM1~54_combout & !\z80_|execute_|nextM~14_combout )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|execute_|setM1~54_combout ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_14 .lut_mask = 16'h00C0; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y13_N17 +dffeas \z80_|sequencer_|DFFE_T3_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_T3_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_T3_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_T3_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout = (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 .lut_mask = 16'h0F00; +defparam \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_66_oe~2 ( +// Equation(s): +// \z80_|execute_|ctl_66_oe~2_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|execute_|comb~0_combout & \z80_|ir_|opcode [0]))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|pla_decode_|Equal52~0_combout ), + .datac(\z80_|execute_|comb~0_combout ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_66_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_66_oe~2 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_66_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y17_N11 +dffeas \z80_|interrupts_|im1 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_im_we~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|interrupts_|im1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|interrupts_|im1 .is_wysiwyg = "true"; +defparam \z80_|interrupts_|im1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_ff_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_bus_ff_oe~0_combout = (\z80_|interrupts_|DFFE_inst44~q & ((\z80_|interrupts_|im1~q ) # ((\z80_|interrupts_|im2~q & !\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) + + .dataa(\z80_|interrupts_|DFFE_inst44~q ), + .datab(\z80_|interrupts_|im2~q ), + .datac(\z80_|interrupts_|im1~q ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_ff_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_ff_oe~0 .lut_mask = 16'hA0A8; +defparam \z80_|execute_|ctl_bus_ff_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_ff_oe~1 ( +// Equation(s): +// \z80_|execute_|ctl_bus_ff_oe~1_combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) # (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|execute_|ctl_bus_ff_oe~0_combout & +// ((\z80_|execute_|ctl_66_oe~2_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) + + .dataa(\z80_|execute_|ctl_66_oe~2_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datad(\z80_|execute_|ctl_bus_ff_oe~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_ff_oe~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_ff_oe~1 .lut_mask = 16'h3B30; +defparam \z80_|execute_|ctl_bus_ff_oe~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_zero_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_bus_zero_oe~0_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_iorw~10_combout ) # (\z80_|execute_|ctl_alu_op_low~27_combout )))) + + .dataa(\z80_|pla_decode_|Equal33~1_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_iorw~10_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_zero_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_zero_oe~0 .lut_mask = 16'h8880; +defparam \z80_|execute_|ctl_bus_zero_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N18 +cycloneive_lcell_comb \z80_|bus_control_|db[0]~4 ( +// Equation(s): +// \z80_|bus_control_|db[0]~4_combout = (\z80_|execute_|ctl_bus_ff_oe~1_combout ) # ((!\z80_|execute_|ctl_bus_zero_oe~0_combout & ((\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) # (!\z80_|decode_state_|in_halt~q )))) + + .dataa(\z80_|execute_|ctl_bus_ff_oe~1_combout ), + .datab(\z80_|execute_|ctl_bus_zero_oe~0_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|decode_state_|in_halt~q ), + .cin(gnd), + .combout(\z80_|bus_control_|db[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[0]~4 .lut_mask = 16'hBABB; +defparam \z80_|bus_control_|db[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N24 +cycloneive_lcell_comb \z80_|bus_control_|db[6]~8 ( +// Equation(s): +// \z80_|bus_control_|db[6]~8_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[6]~22_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) + + .dataa(\z80_|bus_control_|db[0]~4_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datad(\z80_|alu_control_|db[6]~22_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[6]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[6]~8 .lut_mask = 16'hAA0A; +defparam \z80_|bus_control_|db[6]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y7_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a22 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~79_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_first_bit_number = 6; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y8_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a30 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~79_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_first_bit_number = 6; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y11_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a14 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~79_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y10_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a6 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~79_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N16 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ) # +// ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout & +// !\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12 .lut_mask = 16'hF0AC; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y10_N22 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13_combout = (\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout & (((\ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout & +// ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout ), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13 .lut_mask = 16'hCAF0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y1_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a6 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h3C766E63DB6481CB39BC8C68831C724633186CC1BAE9D608A5DEF0FF219C28C1EFF4FDE394D0E19B6FD89186C23CF071E6F1CC8F7FC4F1E48756B0DCD8ED6D0C3DA139003D7A86B2F878DD99DAFB70DE1A19F3FB7DB3B8EF2633007664CB19992E43664448EFF06072648DBA32EDB76E26439BCCEF2DFBF664594B04FBAE72A84A3E508B49DC6BEAAB4F3F0CCCF6D8F568F2DA00EB384A7F53249323198000100408002024010408824080002008011482ED5615E40012EE630C3B2CDB2C13A736DB5B7BD2850018CF936621C6863095A73F7BE7442CB13110B9C0BBB96EEF16CE618EEDCFB393738178C476C367909F71307F6803F677575763DB2D8C3118E4; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h881331ED7AC4EFD38DFACDBB236790005719AEA2FAECCF0D126A30A27222D61BBA428334561F4EDB60C6BF8DB6E267BC56CB69BBCE636CCCB3B2B4B103CC46D5CEEC06DAECB0001569589D5F267AFE086C8FED5DE41DFEFF027DFDFF7FFBFBFDFFDFFF6FFFBDFFDFFF57FF7F7FB7FBBDFBDFFDBFF78FFDBFFEDDFFFDFFFEFF6FF7F7FDDFFEDFF6FF7FFEEFFEFEFC4E51EC0888848E1F2044B47B66608D8A3B3919B9466E6D60D27565964244B218B48AD83430D996068EC908D9E112096996041D77401A0C0CCF5DEEE561F7F7E68CBE72E48E570B047C772CBACC33753080E32EB0B348C0B62337739B1BC73192392592C84E37B7AC141CFE65EE76D83C9083; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h1C5CF062CA6F13854A59BDEEEA07E3C6559EBB3618111895CBBACCBCD512B5F07D361CCE72B925658DBE1F7C4707E195C5C665B8118C3C31B196C261DA85A5E11889D25CB816ACC6627802052C61A4099B7B0EC923971DB3B9F9204BDBCCFA457EE296E8986E64C6DC99E59436641567648CB84DEB7D7937F974F038D838274F3D3CF1BE8C84DDB000565880A776E5C0E13166E49F47119A4CA1311CF97B965E7CBBCB2CB384BD0D92ED105D0617856E80441124B31DE58B8C001607FEE668899693E3EFF8FBF1FCEEFBCF7CF9BA6C37640DDF7FFE6187B19ACF089D4C038F6607B78D38001FE67E56CCE399DE36D7DDBD699D5CFC5B6D7A1421CE06FE40DB6E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h0776C62C316FF94B0BC3A0288DE6A62B14D6C1A2DADF9BDF85B2CCB02CE1DB2D96632C3232C3974CDC1172E1779D8C6738251819975DB8146067301E0C0277B6B657485DCD62AC0662C8C005DDE7494C9CA13AAE3234BB0EE1B708A23A2F48AC4C3838641E940620F9CDDCCA14BCC07104C112BCC9032C48E925594CB886A604C9F7627EB100872A52FB5141D65111E6C8DA0ADB6CEC6004461D0E366B20DCCDB607E624499300E4DF6D95CB62F62FB75403E400EFBC3BD34080FC9CDCFCFCFFFFFFFFFFFFFFFFFFFFF7BFFFFFFFFFFFFFFFFFFFFFFFFFFFCF9FFFFFEFFFF81FFDDFFFFFFFFFFFFFF7FFBFFFBFDC0A6DBE6F8BE5BB7FE7A39B3DA3F3BE13B679; +// synopsys translate_on + +// Location: M9K_X22_Y4_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a14 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h4200420000441C443C0C3C00480018FC387C7C000000007E180038300000204880084204004204423E1E3E02247E3C7E3C7E7E7E7E30007E3C7E7E7E3C7E7C3C0400000000000C34023C2E302464003C00000000000000000020460024000000FF991E65536D2D8D9C9B4DB081C83A5A881B0DFDE2D72DF0FA08FCD6F664173D989098D02025E0F6043B4B9080F4923880C3A3B02D269E730C3DCC423386DCB98B4AD0C5C8D6119602E5121008325B7457090E914F4876EC8A18C664210A4C2392C7658400073421047C75FBE7BE73FDFFF05FEE07BF8AEF7F1378B359E8C61F8F692C2218C98A4A8748531986E7C770D984E0000C02060C000C0DF50F68A580; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h0100046606572583002086010800054C0F2DE8371AC0000A9003E024840C7C0806F6612D770080980A40D293FEC069F16CB2164CA033C539F69B37741AEF1CE3662FF5DF9CB107BB23A39EF7B95E7372200448DBDC18F9C0DE0EF379BF49480657781E91788044213E091339886F337D0612CA646CD48FC58EE77EDD7ECEC466C744FD00E1A7F9E9FBFE4777FD50ABD11F0E57FF4808802282200888A20AA88000000008800AC11D556264251ECFA68C056FBCCB040C614A6850222300D2F6FF59F878FCF5689FCFEF34BFD52FA2422A56A3C113409F7813007F8D6B5F80FE9D7FB1E62675F7C2CBE01032DCA16BADC570C1CBF7ECBC4E7E6C54A5D4550BE1A8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'hE33CB578DEBFAFAEDFD530DE8FA1992072F31B116644B18C72F9F44116C79ADF2F3982C7BE09AD4A32196807648A2495ADF98FD2B16CC096A5E25F5BC811C953CEC3000F432029B3FE3F211712944CA54D1940F193204C199C9F49666CC11B38C23B9D130CA49818913D3A2C1FBF71C5B0C774336F903C677D976189D98CA127AAAD6B6AF36195DA637C6EFA3E36E8FE97FA02EC26EB46198AD8DAD8C11260AF499D7BD86619EE5574CD27C80D39F71E653FDCF1B366737233CBB98D1E7B330F7DCCFC5939C4EC79CF0E1CD43BA7AFC716900A21BDB9DD0FCC7ECE1063238407C7E1B221EA10E38F64EF31CEBF3368E1C712BB1B33781134CFE54C2123349A6E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h5F9CB25A3631964C20007FF5754FC631A97D4F93986C30CF24394625658DE9A7C228A2050470925E29A35D8D06242712CD25C9241898204D85A710947C802013E1265727652C8F0C422BA8C28A0FBB893B0881E00403DDD8843B2D8EB929D0D8CB76E03779E019E2C4E4028219C38C202C9384E0D24E569C2E4D4D60B670CE37414D536A41D144B6C4624A2B00366D8CF6734A4A2DC465B308462CCBD1BF9CB863FC93EDB2CA5DC61B01639318985C88F01680E307C42311C0124700B28BF9B4FF7CCCEFE1996DE3ED6D8CFBF1871BD98EE7646242664EB2E338BD009838637124C921BB3332DC66D9C1706B6C48C3129639A3BA4088EDB496EDBBBFC2CC40B6; +// synopsys translate_on + +// Location: M9K_X22_Y23_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a14 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(gnd), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~79_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_first_bit_number = 6; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y26_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a6 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~79_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_first_bit_number = 6; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFFFFFEBFFFFFFFFFFFFFFFFFFFFFFFBFFFFFFFFFFFFFFFFFDFFFFFFFFFFFFFBFFFFFFFFFEFFFFFFFDFFFFFFFFFFFFFEFFFFFFFDF8FFFFFFF9FFFFFFFFFFFFFFFF3FFFFFFE7FFFFFFFFFFFFFFFF; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000380001887600094C977486989000000000000000000000000FFFFFFFFC0810205C00018C36DC09CF97749EDCD00000000000000000000000000000001FFFFFFFDC004000B6D028BF17749ED8100000000000000000000000000000001BF7EFDF9400404A96D8289B57549FFC10000000000000000000000003F7EFDF90000000140041EB16D8298357DC9F7410000000000000000000000007FFFFFFD8000000340043AB160021E757DC9134100000000000000000000000040810207BFFFFFFF5FE430497702760D60099349000000000000000000000000408102073FFFFFFD5FE40E49774240C96009735D; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h5FE8334948F827C15FF88F8169A80ECB609EAD417A698FC178F33E8171F72A915FE836E948F807C95FF88F81E9A80FC7639E1FC17B2BBEC170730F8D70F7B0C1400826E548B807C95FF88F95E8280FCB63C6BCC17B3B3FC171AB3E81708734C1400826ED58F8258159F88B8168280FC161629DC17A3B3F41738B3F8150AF16E9400826ED581805C151D88A8160682FC1422297C17A2A39C162FB378550CF10A1400826ED58182581D1580B8761EC2FC14232B7C179AA39C5627B7781D0CF10D3400826E158182D81F0488A4B61EC0DC143789FC17BBB39C1610B7F81D45F11D34008A7E958080D01F0088A4160B42DD143689FC17B9B398561837F81D41702B1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h50DF086350368F0151C688016801460157EDE81148F310013FFFFFFF40810103D2D70D4B50168F0141D6C8116C01462153EDA90148F31D01BFFFFFFF40810107D2D7296354D68501403EC0016C01482173FDA08148F11F01800000037FFFFFFD4297893154DE81054022D2116C014D6153FCA00148D10F01000000013F7EFEF9429F810150CEC10143E042016C014C09537DA00148D11F01BF7EFEF900000001469F833150168D0543E04A116F014DA15379B181C8511F03FFFFFFFD00000001449AAB2155368D01482046016F416CA15079B001C8513E03C0810105FFFFFFFF403A8B0155C685014800461167476CA15039B08180413E0500000007FFFFFFFF; +// synopsys translate_on + +// Location: LCCOMB_X24_Y10_N16 +cycloneive_lcell_comb \Selector6~0 ( +// Equation(s): +// \Selector6~0_combout = (\z80_|address_pins_|abus[14]~23_combout & ((\Selector3~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout )) # (!\Selector3~0_combout & +// ((\ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ))))) # (!\z80_|address_pins_|abus[14]~23_combout & (\Selector3~0_combout )) + + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\Selector3~0_combout ), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ), + .cin(gnd), + .combout(\Selector6~0_combout ), + .cout()); +// synopsys translate_off +defparam \Selector6~0 .lut_mask = 16'hE6C4; +defparam \Selector6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y10_N18 +cycloneive_lcell_comb \Selector6~1 ( +// Equation(s): +// \Selector6~1_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\Selector6~0_combout )))) # (!\z80_|address_pins_|abus[14]~23_combout & ((\Selector6~0_combout & ((\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ))) # +// (!\Selector6~0_combout & (\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout )))) + + .dataa(\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ), + .datab(\z80_|address_pins_|abus[14]~23_combout ), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .datad(\Selector6~0_combout ), + .cin(gnd), + .combout(\Selector6~1_combout ), + .cout()); +// synopsys translate_off +defparam \Selector6~1 .lut_mask = 16'hFC22; +defparam \Selector6~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y10_N4 +cycloneive_lcell_comb \D[6]~88 ( +// Equation(s): +// \D[6]~88_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\Selector6~1_combout +// ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13_combout )))) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13_combout ), + .datad(\Selector6~1_combout ), + .cin(gnd), + .combout(\D[6]~88_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~88 .lut_mask = 16'hF4B0; +defparam \D[6]~88 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X16_Y34_N8 +cycloneive_io_ibuf \raw_loader_in~input ( + .i(raw_loader_in), + .ibar(gnd), + .o(\raw_loader_in~input_o )); +// synopsys translate_off +defparam \raw_loader_in~input .bus_hold = "false"; +defparam \raw_loader_in~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y10_N24 +cycloneive_lcell_comb \D[6]~69 ( +// Equation(s): +// \D[6]~69_combout = ((\z80_|address_pins_|DFFE_apin_latch [0]) # (\raw_loader_in~input_o )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [0]), + .datad(\raw_loader_in~input_o ), + .cin(gnd), + .combout(\D[6]~69_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~69 .lut_mask = 16'hFFF3; +defparam \D[6]~69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y10_N0 +cycloneive_lcell_comb \D[6]~78 ( +// Equation(s): +// \D[6]~78_combout = ((\Equal2~0_combout & ((\D[6]~69_combout ))) # (!\Equal2~0_combout & (\D[6]~88_combout ))) # (!\Equal2~1_combout ) + + .dataa(\Equal2~0_combout ), + .datab(\Equal2~1_combout ), + .datac(\D[6]~88_combout ), + .datad(\D[6]~69_combout ), + .cin(gnd), + .combout(\D[6]~78_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~78 .lut_mask = 16'hFB73; +defparam \D[6]~78 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y10_N6 +cycloneive_lcell_comb \D[6]~79 ( +// Equation(s): +// \D[6]~79_combout = (\z80_|pin_control_|bus_db_pin_oe~15_combout & (\z80_|data_pins_|dout [6] & ((\D[6]~78_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout & (((\D[6]~78_combout ) # (!\Equal2~1_combout )))) + + .dataa(\z80_|data_pins_|dout [6]), + .datab(\Equal2~1_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .datad(\D[6]~78_combout ), + .cin(gnd), + .combout(\D[6]~79_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~79 .lut_mask = 16'hAF03; +defparam \D[6]~79 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N18 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [6] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[6]~9_combout ) # ((\z80_|pin_control_|bus_db_pin_re~combout & \D[6]~79_combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & +// (\z80_|pin_control_|bus_db_pin_re~combout & (\D[6]~79_combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datab(\z80_|pin_control_|bus_db_pin_re~combout ), + .datac(\D[6]~79_combout ), + .datad(\z80_|bus_control_|db[6]~9_combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [6]), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] .lut_mask = 16'hEAC0; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y13_N19 +dffeas \z80_|data_pins_|dout[6] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [6]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|data_pins_|dout [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|data_pins_|dout[6] .is_wysiwyg = "true"; +defparam \z80_|data_pins_|dout[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N6 +cycloneive_lcell_comb \z80_|bus_control_|db[6]~9 ( +// Equation(s): +// \z80_|bus_control_|db[6]~9_combout = ((\z80_|bus_control_|db[6]~8_combout & ((\z80_|data_pins_|dout [6]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) + + .dataa(\z80_|bus_control_|db[0]~6_combout ), + .datab(\z80_|bus_control_|db[6]~8_combout ), + .datac(\z80_|data_pins_|dout [6]), + .datad(\z80_|execute_|ctl_bus_db_oe~combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[6]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[6]~9 .lut_mask = 16'hD5DD; +defparam \z80_|bus_control_|db[6]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y13_N7 +dffeas \z80_|ir_|opcode[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|bus_control_|db[6]~9_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|ir_|opcode [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|ir_|opcode[6] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~10 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~10_combout = (!\z80_|ir_|opcode [6] & (\z80_|ir_|opcode [7] & (\z80_|execute_|ctl_ir_we~5_combout & !\z80_|pla_decode_|Equal46~0_combout ))) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|execute_|ctl_ir_we~5_combout ), + .datad(\z80_|pla_decode_|Equal46~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~10 .lut_mask = 16'h0040; +defparam \z80_|execute_|ctl_ir_we~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~0_combout = (\z80_|execute_|ctl_alu_bs_oe~6_combout & (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~7_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~10_combout ), + .datab(\z80_|execute_|ctl_ir_we~7_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~6_combout ), + .datad(\z80_|execute_|ctl_ir_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~0 .lut_mask = 16'h10F0; +defparam \z80_|execute_|ctl_bus_db_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~4 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~4_combout = (!\z80_|execute_|ctl_bus_db_oe~3_combout ) # (!\z80_|execute_|ctl_bus_db_oe~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_bus_db_oe~0_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~4 .lut_mask = 16'h0FFF; +defparam \z80_|execute_|ctl_bus_db_oe~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~2 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~2_combout = (!\z80_|execute_|ctl_bus_ff_oe~1_combout & (!\z80_|execute_|ctl_bus_zero_oe~0_combout & ((\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) # (!\z80_|decode_state_|in_halt~q )))) + + .dataa(\z80_|execute_|ctl_bus_ff_oe~1_combout ), + .datab(\z80_|execute_|ctl_bus_zero_oe~0_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|decode_state_|in_halt~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~2 .lut_mask = 16'h1011; +defparam \z80_|execute_|ctl_bus_db_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y17_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~5 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~5_combout = (\z80_|execute_|ctl_ir_we~8_combout ) # ((\z80_|pla_decode_|Equal41~2_combout ) # ((\z80_|execute_|ctl_ir_we~14_combout ) # (\z80_|execute_|ctl_ir_we~11_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|pla_decode_|Equal41~2_combout ), + .datac(\z80_|execute_|ctl_ir_we~14_combout ), + .datad(\z80_|execute_|ctl_ir_we~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~5 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_bus_db_oe~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~6 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~6_combout = ((\z80_|execute_|ctl_66_oe~2_combout ) # ((\z80_|execute_|ctl_bus_db_oe~5_combout & \z80_|execute_|ctl_ir_we~4_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|execute_|ctl_bus_db_oe~5_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|execute_|ctl_66_oe~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~6 .lut_mask = 16'hFFD5; +defparam \z80_|execute_|ctl_bus_db_oe~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~combout = (\z80_|execute_|ctl_bus_db_oe~2_combout & ((\z80_|execute_|ctl_bus_db_oe~4_combout ) # ((\z80_|execute_|ctl_bus_db_oe~6_combout ) # (!\z80_|execute_|ctl_sw_1d~6_combout )))) + + .dataa(\z80_|execute_|ctl_bus_db_oe~4_combout ), + .datab(\z80_|execute_|ctl_bus_db_oe~2_combout ), + .datac(\z80_|execute_|ctl_sw_1d~6_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe .lut_mask = 16'hCC8C; +defparam \z80_|execute_|ctl_bus_db_oe .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N14 +cycloneive_lcell_comb \z80_|bus_control_|db[0]~6 ( +// Equation(s): +// \z80_|bus_control_|db[0]~6_combout = (\z80_|execute_|ctl_bus_db_oe~combout ) # ((\z80_|execute_|ctl_bus_db_we~7_combout ) # (!\z80_|execute_|ctl_bus_db_oe~2_combout )) + + .dataa(\z80_|execute_|ctl_bus_db_oe~combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~2_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[0]~6 .lut_mask = 16'hFAFF; +defparam \z80_|bus_control_|db[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~61 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][2]~61_combout = (\ula_|zx_keyboard_|keys[7][2]~60_combout & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|zx_keyboard_|keys[7][2]~60_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][2]~61_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2]~61 .lut_mask = 16'h2000; +defparam \ula_|zx_keyboard_|keys[7][2]~61 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~63 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][2]~63_combout = (\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[7][2]~61_combout ) # ((\ula_|zx_keyboard_|keys[5][4]~62_combout & \ula_|zx_keyboard_|keys[7][2]~30_combout )))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|zx_keyboard_|keys[7][2]~61_combout ), + .datac(\ula_|zx_keyboard_|keys[5][4]~62_combout ), + .datad(\ula_|zx_keyboard_|keys[7][2]~30_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][2]~63_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2]~63 .lut_mask = 16'hA888; +defparam \ula_|zx_keyboard_|keys[7][2]~63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~64 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][2]~64_combout = (\ula_|zx_keyboard_|keys[0][0]~13_combout & (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|keys[7][2]~63_combout & !\ula_|zx_keyboard_|extended~q ))) + + .dataa(\ula_|zx_keyboard_|keys[0][0]~13_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|zx_keyboard_|keys[7][2]~63_combout ), + .datad(\ula_|zx_keyboard_|extended~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][2]~64_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2]~64 .lut_mask = 16'h0020; +defparam \ula_|zx_keyboard_|keys[7][2]~64 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~65 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][2]~65_combout = (\ula_|zx_keyboard_|keys[7][2]~64_combout & (!\ula_|zx_keyboard_|Selector13~0_combout )) # (!\ula_|zx_keyboard_|keys[7][2]~64_combout & ((\ula_|zx_keyboard_|keys[7][2]~q ))) + + .dataa(\ula_|zx_keyboard_|Selector13~0_combout ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[7][2]~q ), + .datad(\ula_|zx_keyboard_|keys[7][2]~64_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][2]~65_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2]~65 .lut_mask = 16'h55F0; +defparam \ula_|zx_keyboard_|keys[7][2]~65 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y9_N5 +dffeas \ula_|zx_keyboard_|keys[7][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[7][2]~65_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[7][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[7][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~67 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][2]~67_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [4])) # (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [1] & +// !\ula_|ps2_keyboard_|shiftreg [4])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][2]~67_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][2]~67 .lut_mask = 16'h2244; +defparam \ula_|zx_keyboard_|keys[6][2]~67 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~68 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][2]~68_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[6][2]~67_combout & (\ula_|ps2_keyboard_|shiftreg [4] $ (!\ula_|ps2_keyboard_|shiftreg [2])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|zx_keyboard_|keys[6][2]~67_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][2]~68_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][2]~68 .lut_mask = 16'h2100; +defparam \ula_|zx_keyboard_|keys[6][2]~68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~69 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][2]~69_combout = (\ula_|zx_keyboard_|keys[6][1]~39_combout & ((\ula_|zx_keyboard_|keys[6][2]~68_combout & (!\ula_|zx_keyboard_|keys[5][0]~66_combout )) # (!\ula_|zx_keyboard_|keys[6][2]~68_combout & +// ((\ula_|zx_keyboard_|keys[6][2]~q ))))) # (!\ula_|zx_keyboard_|keys[6][1]~39_combout & (((\ula_|zx_keyboard_|keys[6][2]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][0]~66_combout ), + .datab(\ula_|zx_keyboard_|keys[6][1]~39_combout ), + .datac(\ula_|zx_keyboard_|keys[6][2]~q ), + .datad(\ula_|zx_keyboard_|keys[6][2]~68_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][2]~69_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][2]~69 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[6][2]~69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y8_N11 +dffeas \ula_|zx_keyboard_|keys[6][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[6][2]~69_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[6][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[6][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N12 +cycloneive_lcell_comb \D[2]~36 ( +// Equation(s): +// \D[2]~36_combout = (\ula_|zx_keyboard_|keys[7][2]~q & (\z80_|address_pins_|abus[15]~22_combout & ((\z80_|address_pins_|abus[14]~23_combout ) # (!\ula_|zx_keyboard_|keys[6][2]~q )))) # (!\ula_|zx_keyboard_|keys[7][2]~q & +// (((\z80_|address_pins_|abus[14]~23_combout )) # (!\ula_|zx_keyboard_|keys[6][2]~q ))) + + .dataa(\ula_|zx_keyboard_|keys[7][2]~q ), + .datab(\ula_|zx_keyboard_|keys[6][2]~q ), + .datac(\z80_|address_pins_|abus[14]~23_combout ), + .datad(\z80_|address_pins_|abus[15]~22_combout ), + .cin(gnd), + .combout(\D[2]~36_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~36 .lut_mask = 16'hF351; +defparam \D[2]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~58 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][2]~58_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [1]))) # (!\ula_|ps2_keyboard_|shiftreg [6] & +// (!\ula_|zx_keyboard_|extended~q & (\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|zx_keyboard_|extended~q ), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][2]~58_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][2]~58 .lut_mask = 16'h1008; +defparam \ula_|zx_keyboard_|keys[4][2]~58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~130 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][2]~130_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|zx_keyboard_|keys[4][2]~58_combout & (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [0]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|zx_keyboard_|keys[4][2]~58_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][2]~130_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][2]~130 .lut_mask = 16'h0080; +defparam \ula_|zx_keyboard_|keys[4][2]~130 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~59 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][2]~59_combout = (\ula_|zx_keyboard_|keys[3][4]~129_combout & ((\ula_|zx_keyboard_|keys[4][2]~130_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[4][2]~130_combout & ((\ula_|zx_keyboard_|keys[4][2]~q +// ))))) # (!\ula_|zx_keyboard_|keys[3][4]~129_combout & (((\ula_|zx_keyboard_|keys[4][2]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[3][4]~129_combout ), + .datac(\ula_|zx_keyboard_|keys[4][2]~q ), + .datad(\ula_|zx_keyboard_|keys[4][2]~130_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][2]~59_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][2]~59 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[4][2]~59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y8_N25 +dffeas \ula_|zx_keyboard_|keys[4][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[4][2]~59_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[4][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[4][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~56 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][2]~56_combout = (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [2]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][2]~56_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][2]~56 .lut_mask = 16'h00F0; +defparam \ula_|zx_keyboard_|keys[5][2]~56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~57 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][2]~57_combout = (\ula_|zx_keyboard_|keys[5][2]~56_combout & ((\ula_|zx_keyboard_|keys[5][2]~31_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[5][2]~31_combout & ((\ula_|zx_keyboard_|keys[5][2]~q +// ))))) # (!\ula_|zx_keyboard_|keys[5][2]~56_combout & (((\ula_|zx_keyboard_|keys[5][2]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][2]~56_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[5][2]~q ), + .datad(\ula_|zx_keyboard_|keys[5][2]~31_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][2]~57_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][2]~57 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[5][2]~57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y10_N19 +dffeas \ula_|zx_keyboard_|keys[5][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[5][2]~57_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[5][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[5][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N24 +cycloneive_lcell_comb \D[2]~35 ( +// Equation(s): +// \D[2]~35_combout = (\z80_|address_pins_|abus[13]~20_combout & (((\z80_|address_pins_|abus[12]~21_combout )) # (!\ula_|zx_keyboard_|keys[4][2]~q ))) # (!\z80_|address_pins_|abus[13]~20_combout & (!\ula_|zx_keyboard_|keys[5][2]~q & +// ((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][2]~q )))) + + .dataa(\z80_|address_pins_|abus[13]~20_combout ), + .datab(\ula_|zx_keyboard_|keys[4][2]~q ), + .datac(\z80_|address_pins_|abus[12]~21_combout ), + .datad(\ula_|zx_keyboard_|keys[5][2]~q ), + .cin(gnd), + .combout(\D[2]~35_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~35 .lut_mask = 16'hA2F3; +defparam \D[2]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][2]~54 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][2]~54_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [2]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][2]~54_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][2]~54 .lut_mask = 16'h000F; +defparam \ula_|zx_keyboard_|keys[0][2]~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][2]~55 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][2]~55_combout = (\ula_|zx_keyboard_|keys[7][4]~49_combout & ((\ula_|zx_keyboard_|keys[0][2]~54_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[0][2]~54_combout & ((\ula_|zx_keyboard_|keys[0][2]~q +// ))))) # (!\ula_|zx_keyboard_|keys[7][4]~49_combout & (((\ula_|zx_keyboard_|keys[0][2]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[7][4]~49_combout ), + .datac(\ula_|zx_keyboard_|keys[0][2]~q ), + .datad(\ula_|zx_keyboard_|keys[0][2]~54_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][2]~55_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][2]~55 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[0][2]~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y7_N19 +dffeas \ula_|zx_keyboard_|keys[0][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[0][2]~55_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[0][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[0][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][2]~50 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][2]~50_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [2]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][2]~50_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][2]~50 .lut_mask = 16'h0F00; +defparam \ula_|zx_keyboard_|keys[3][2]~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][2]~51 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][2]~51_combout = (\ula_|zx_keyboard_|keys[3][2]~50_combout & ((\ula_|zx_keyboard_|keys[7][4]~49_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[7][4]~49_combout & (\ula_|zx_keyboard_|keys[3][2]~q +// )))) # (!\ula_|zx_keyboard_|keys[3][2]~50_combout & (((\ula_|zx_keyboard_|keys[3][2]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[3][2]~50_combout ), + .datab(\ula_|zx_keyboard_|keys[7][4]~49_combout ), + .datac(\ula_|zx_keyboard_|keys[3][2]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][2]~51_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][2]~51 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[3][2]~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y7_N15 +dffeas \ula_|zx_keyboard_|keys[3][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[3][2]~51_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[3][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[3][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][2]~52 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][2]~52_combout = (\ula_|zx_keyboard_|Equal0~2_combout & (\ula_|zx_keyboard_|keys[7][4]~17_combout & (\ula_|zx_keyboard_|keys[3][2]~50_combout & !\ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|zx_keyboard_|Equal0~2_combout ), + .datab(\ula_|zx_keyboard_|keys[7][4]~17_combout ), + .datac(\ula_|zx_keyboard_|keys[3][2]~50_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][2]~52_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][2]~52 .lut_mask = 16'h0080; +defparam \ula_|zx_keyboard_|keys[2][2]~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][2]~53 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][2]~53_combout = (\ula_|zx_keyboard_|keys[2][2]~52_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[2][2]~52_combout & ((\ula_|zx_keyboard_|keys[2][2]~q ))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[2][2]~q ), + .datad(\ula_|zx_keyboard_|keys[2][2]~52_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][2]~53_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][2]~53 .lut_mask = 16'h55F0; +defparam \ula_|zx_keyboard_|keys[2][2]~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y7_N25 +dffeas \ula_|zx_keyboard_|keys[2][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[2][2]~53_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[2][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[2][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N8 +cycloneive_lcell_comb \D[2]~33 ( +// Equation(s): +// \D[2]~33_combout = (\ula_|zx_keyboard_|keys[3][2]~q & (\z80_|address_pins_|abus[11]~19_combout & ((\z80_|address_pins_|abus[10]~24_combout ) # (!\ula_|zx_keyboard_|keys[2][2]~q )))) # (!\ula_|zx_keyboard_|keys[3][2]~q & +// (((\z80_|address_pins_|abus[10]~24_combout )) # (!\ula_|zx_keyboard_|keys[2][2]~q ))) + + .dataa(\ula_|zx_keyboard_|keys[3][2]~q ), + .datab(\ula_|zx_keyboard_|keys[2][2]~q ), + .datac(\z80_|address_pins_|abus[11]~19_combout ), + .datad(\z80_|address_pins_|abus[10]~24_combout ), + .cin(gnd), + .combout(\D[2]~33_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~33 .lut_mask = 16'hF531; +defparam \D[2]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][2]~47 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][2]~47_combout = (\ula_|zx_keyboard_|keys[6][4]~45_combout & (\ula_|zx_keyboard_|keys[6][4]~46_combout & !\ula_|ps2_keyboard_|shiftreg [4])) + + .dataa(\ula_|zx_keyboard_|keys[6][4]~45_combout ), + .datab(\ula_|zx_keyboard_|keys[6][4]~46_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][2]~47_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][2]~47 .lut_mask = 16'h0808; +defparam \ula_|zx_keyboard_|keys[1][2]~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][2]~48 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][2]~48_combout = (\ula_|zx_keyboard_|keys[1][2]~47_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[1][2]~47_combout & (\ula_|zx_keyboard_|keys[1][2]~q )) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|keys[1][2]~47_combout ), + .datac(\ula_|zx_keyboard_|keys[1][2]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][2]~48_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][2]~48 .lut_mask = 16'h30FC; +defparam \ula_|zx_keyboard_|keys[1][2]~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y7_N7 +dffeas \ula_|zx_keyboard_|keys[1][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[1][2]~48_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[1][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[1][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~1 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row~1_combout = (\z80_|address_pins_|DFFE_apin_latch [9]) # ((!\ula_|zx_keyboard_|keys[1][2]~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [9]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\ula_|zx_keyboard_|keys[1][2]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row~1 .lut_mask = 16'hCFFF; +defparam \ula_|zx_keyboard_|key_row~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N4 +cycloneive_lcell_comb \D[2]~34 ( +// Equation(s): +// \D[2]~34_combout = (\D[2]~33_combout & (\ula_|zx_keyboard_|key_row~1_combout & ((\z80_|address_pins_|abus[8]~18_combout ) # (!\ula_|zx_keyboard_|keys[0][2]~q )))) + + .dataa(\z80_|address_pins_|abus[8]~18_combout ), + .datab(\ula_|zx_keyboard_|keys[0][2]~q ), + .datac(\D[2]~33_combout ), + .datad(\ula_|zx_keyboard_|key_row~1_combout ), + .cin(gnd), + .combout(\D[2]~34_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~34 .lut_mask = 16'hB000; +defparam \D[2]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N28 +cycloneive_lcell_comb \D[2]~37 ( +// Equation(s): +// \D[2]~37_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[2]~36_combout & (\D[2]~35_combout & \D[2]~34_combout ))) + + .dataa(\D[2]~36_combout ), + .datab(\D[2]~35_combout ), + .datac(\D[2]~34_combout ), + .datad(\z80_|address_pins_|abus[0]~16_combout ), + .cin(gnd), + .combout(\D[2]~37_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~37 .lut_mask = 16'hFF80; +defparam \D[2]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y6_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a18 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[2]~39_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_first_bit_number = 2; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y9_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a2 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[2]~39_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024; +// synopsys translate_on + +// Location: M9K_X22_Y12_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a10 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[2]~39_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N26 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2 .lut_mask = 16'hDC98; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y5_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a26 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[2]~39_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_first_bit_number = 2; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N8 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~3 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~3_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout & +// ((\ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout )))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~3_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~3 .lut_mask = 16'hF838; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y3_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a10 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h8102080042447C443C0C3C402004FC1838787840407A00707C02487E444878428008004042460424402040024A3242124220044022404208520A4A24424A125A0A1028440000524A0A4A4A204A5240460800100010540042002064547E0600001FA9BE02B828694B8A82CB8C8158226808198E9EC6B021F07A2098D5E0ECB639D2B1908129B6A2D646516192D87593189D8B2B26CD6E16234C1CC90AD9831EBD89EAD271ECC39A80507716BB49626B743DFFCF99576C3FAC889860E46618ACB79EC30EEDE42EB1E31F3976CA23243179FAA96DCD66D51535351770D410DC8531866136E6184518410368288C446EC63A4FEE425019C244097049C2B2DC8D93C4; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'hA111466C9493A2A7CA2204102414CC798BF0EEC2995A4814580BD07585585ED92E5172E82E845070000A846100500E84EA1803B8B07B99E1DC75BE6419674597B38F54EB9091AE3320201EE395AD63902282A031CE3E87CC902954AA515D5D6B6A855EC94CFEC4E0172C59A7D054F8F9F4356C312C204E40B05E2059407C8DC84683814663FB910969D1D631A952B381B7F635A33FD38D5CF15DF47D057F7FF555B555C2278100000A24804D7D98EB98602733818A12094F281287422CB40002464C92242004E0AE8518E001D124A7628010115D23C30462FC00A014A12133582A191E00538FC8A5004036A959ACB7A463D23E419EA06B744005385455A71250; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h6C60009CA281AEACDC1762945981B869F93D683EAF4AC7EE52412E85B60B91CD03AD0025F0D509F63202D877ECD8BF8005451F7BD346CF9E17B36F1850A7D80A8CF14A288EAE3BFE00FB2DB45080D4A50C58263A3B398DD51AB9CB554ECAA7B2E73D9D6D2C265859DB844C2C1952AD10241100174FE0444E6707D80A098D8585AAAC4802B74190FB007C0C0206186AFC1B3A2A46864F26118ED1D03ACB1062B7315502751655F60070E6B2C50609369611365AD1E3352327320331A51818030C7D8C4C59396600DC0C420495A0D987501490002BAD38012E20620D556A230B1796450B74E95A860FF3E434C65F1308F16F92395816B914F0CE870C1323347A4E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h7FC8531A7A319F3EBFC1383FFCDB0E09BD288288B078B4AD220B6FA934CF6187D972662C0D31E34E63B31CFC6EB4B35A69B67D85489E62EA99899A94F6800FDBA5D31B86A0288D29CE2EAAFF86A6A9F7000082293E6BB54F06E98ECCB199973EDA00FADB1D3A630BA18050635DE7DCB13B9B86E0CE6E08DC46331A352F716E3C441A0CC068A0823F8668A00621B779DE35FEC004050469F34866AEE766743D8C00FDF3B9F8DE7B76E97F8D32F0F39E4CAC68D9BBB68EA3915F6225F932CAAFDAD6E60DC661155EC9E80F8CEE659F19CC554B2C67C33EDCDA63BAD91B7D1842A7177AF49DF118FE47ACE3344964EBCADCFBB543F7729CCB340866D1157B6CCDDB; +// synopsys translate_on + +// Location: M9K_X22_Y29_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a2 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h77A47C739FF6A22B8B5CDC49E748E9C739BDE6756DB4D22437E74183E12400CBF7D3C6CC8C7841AB49CC538E8A72F2E73C64D3DF3662B19C07D7D299CBEDEF3E7DA5F4A8458A9451315B681ADA9AB0D63218DFB77D3353C32837E954604B9D98144A4566F47B71715BE6CDB8BA64D536762E9224D70F9A5C374B4D1CAB8DF527027170C5DBCC2B6AD72B8E4CCC94DAA139D8BA64E3384337426E7F274CC88A373AB1F9007B8A7F2936D16274F9BF8B6BABD48FCE74047C1E738C5B303E815BA720C76D6362915156A7671331CE657011862E594E46A6D99392E2D640D766869389A4D43867379AB880C1ACE279E451CB3A9063A0B320F65E536B8EEF9CBB9C76; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h9A2921ED6AA0CC8387B267B9E7A182720833CEE061E6450C8E4A72E3C043F21A0AD007E832124E92429C091D167806C10041AF32DDE13A669990457D098CC2FE3AC884B1E69101135CD080022451F20884CCB9CD203C141402A5AD293C3BABA95ADFAF6726384795A7656B753D2369B9EB5595BAA722012DF8DCFBF15BF46D6EB755D1CBF0DCF6FD40BEEC16EAB4A6D16839C98CBE9DBB437C69FB709F8E79993B9DDFE4F823D6E124B75BCE9B29F799F926619184B6C1178389F07349210436293A130C900FBA4EA70D2BA25B343C5B026D8E8766A4E4267CDAEC99E830D2307D94E6ED80D6722F3989B91E31C63B64C363DCE71A861C14382E270FC02868C7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h386BA04E797A3F8551DAD9D24A8D259A03ECFF5AB81B1C31DFDAE10100544F8CF1A8CCFC0C7A15BD9E7C2557CB00BF2584E16AAD13D7EDB525A85ABF90C0136DD195D748900C29DF7F381280A9738CDC3BF5BBF937D3A4D99CE2BCCD97CEF2C7F00030AFDB7F22E68CBAA4D9BE7633D3B53E90E4B124422A2A4454BACA5A8DC9352CD1DAFC910CC504334DF9E6F1F4F30161A36293CC5CCF1CA13994ED29D34A5699692496359B8E67A7E74D9A0FC504C8465638CF74A0AF9185921A7D2629893091900604017933442359491FBAB63F346F0C5EC8E3A531984B09E605A30A0627271C28420E47B8DEC74738FC3EDF9FBD40EC09FC7B4D3A1475BE433705FB5F; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h973FED2E9BEDBA474B70B121A8D60F3B4EE3F1A238FB3B730EDEEE74EC632DB4D7779D7B79D1C75DF87378E98719C1AF38B1B801C71D180CE86370AE9C2BF38CF84DBBB9878C55457324E92D3DAE91D729AC76BBAD4C6EECA74DAB5EE9A175EE34ABEB9DFAA48538A57E3E5C158947081CA41402E8E65478737F73BB629AAE2EE51D405CAF70F622DD4599602D7910DCAC8214B2A42025110593202C8B164C8DF6369572C3BB8AA1984A8D12F776E224ECEEB21F97FCD6C0CF17A044EC2BBF0571A553CCDD8ABA79BD27B7AF735ED2D34F1EF3A81A160C9ECB1B1FAE6EDEEFF99E28CC30C7C2553DED3378D655AD194B2E6C1BCBED700F6713D960F33E4C361A; +// synopsys translate_on + +// Location: M9K_X22_Y25_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a10 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(gnd), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[2]~39_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_first_bit_number = 2; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y27_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a2 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[2]~39_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_bit_number = 2; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF00000000FFFFFFFFFFFFFFFFFFF68003FFF38003FFF9F403FFF8B003D8F87003FFF8F01BEDFC701FEBFEA01FDBFDC00FDBFDC01FC7FDC0FFC7FDE87FC7FCDC8FC7FCF89FC07071FFC0F873F3E0303FE7FFFFFFFFFFFFFFFF; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000000040078400234B1474928D1000000000000000000000000FFFFFFFF204081024004027153423DA5474928DD000000000000000000000000000000003FFFFFFF40041CB14162378547495999000000000000000000000000000000003FFFFFFF4004189141623485474959F90000000000000000000000003FFFFFFE40000001400400815B6223C15FC913DD0000000000000000000000007FFFFFFE40000001400402E9400333715FC973E5000000000000000000000000604081027FFFFFFD5FE60AE95763353540091361000000000000000000000000400000003FFFFFFC5FE60AE95763081D40011361; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h5FE0236948F816F55FE897C10C28028041DC8DE178059BC16900BB4173E47AC15FE8236148E806F55FE891054CA80E8148288DE179E597C169903AC153F13A8140080365486806D55FE891D548080A8148608FE159E493C16BB03FD152BD1AE14008037D482017D15FE881C548A00AC148E08FE159FC9AC16AA02FC15AAF18F1400083F1482007C15EE882C148E00A4148B08FE148F88D4168E436915ABB01E9400092F9480007815C2882C148E00B6149B49F614868FD41436476814AFA42A1400892FD480807C15C0883C149800FE149DC9FE14A60BD41431C3F914AEA01C1400882F1480817C11C0883C041940FE549CC9EE54860BDC143BC7D8108D2C4D0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h0B928870484885014DE84481680162815375AC0148D308813FFFFFFC400000004B9288314DC0970149FC44856C0166815375AC8140D108817FFFFFFD6040808249D0A2094F908581481C40814C016099417DA88140D10B01400000017FFFFFFE48D083394B9085814A085081440166814179900140510F01400000013FFFFFFE4A508335498001814BE0608146016E8941799041405107413FFFFFFF000000004B98812149C005814BE0628146836E814179100140510F013FFFFFFF000000004B98A1114BE801814A00668147832C814119904140401F4120408082FFFFFFFF48D881154EA801854800768147C22CC14019900100003E0000000000FFFFFFFF; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N24 +cycloneive_lcell_comb \Selector0~0 ( +// Equation(s): +// \Selector0~0_combout = (\Selector3~0_combout & (((\ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout )) # (!\z80_|address_pins_|abus[14]~23_combout ))) # (!\Selector3~0_combout & (\z80_|address_pins_|abus[14]~23_combout & +// ((\ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout )))) + + .dataa(\Selector3~0_combout ), + .datab(\z80_|address_pins_|abus[14]~23_combout ), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ), + .cin(gnd), + .combout(\Selector0~0_combout ), + .cout()); +// synopsys translate_off +defparam \Selector0~0 .lut_mask = 16'hE6A2; +defparam \Selector0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N18 +cycloneive_lcell_comb \Selector0~1 ( +// Equation(s): +// \Selector0~1_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\Selector0~0_combout )))) # (!\z80_|address_pins_|abus[14]~23_combout & ((\Selector0~0_combout & (\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout )) # +// (!\Selector0~0_combout & ((\rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ))))) + + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ), + .datad(\Selector0~0_combout ), + .cin(gnd), + .combout(\Selector0~1_combout ), + .cout()); +// synopsys translate_off +defparam \Selector0~1 .lut_mask = 16'hEE50; +defparam \Selector0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N28 +cycloneive_lcell_comb \D[2]~82 ( +// Equation(s): +// \D[2]~82_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~3_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\Selector0~1_combout +// ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~3_combout )))) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~3_combout ), + .datad(\Selector0~1_combout ), + .cin(gnd), + .combout(\D[2]~82_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~82 .lut_mask = 16'hF4B0; +defparam \D[2]~82 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N12 +cycloneive_lcell_comb \D[2]~38 ( +// Equation(s): +// \D[2]~38_combout = ((\Equal2~0_combout & (\D[2]~37_combout )) # (!\Equal2~0_combout & ((\D[2]~82_combout )))) # (!\Equal2~1_combout ) + + .dataa(\Equal2~1_combout ), + .datab(\Equal2~0_combout ), + .datac(\D[2]~37_combout ), + .datad(\D[2]~82_combout ), + .cin(gnd), + .combout(\D[2]~38_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~38 .lut_mask = 16'hF7D5; +defparam \D[2]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N30 +cycloneive_lcell_comb \D[2]~39 ( +// Equation(s): +// \D[2]~39_combout = (\z80_|pin_control_|bus_db_pin_oe~15_combout & (((\z80_|data_pins_|dout [2] & \D[2]~38_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout & (((\D[2]~38_combout )) # (!\Equal2~1_combout ))) + + .dataa(\Equal2~1_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .datac(\z80_|data_pins_|dout [2]), + .datad(\D[2]~38_combout ), + .cin(gnd), + .combout(\D[2]~39_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~39 .lut_mask = 16'hF311; +defparam \D[2]~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N4 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [2] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[2]~13_combout ) # ((\D[2]~39_combout & \z80_|pin_control_|bus_db_pin_re~combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & +// (((\D[2]~39_combout & \z80_|pin_control_|bus_db_pin_re~combout )))) + + .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datab(\z80_|bus_control_|db[2]~13_combout ), + .datac(\D[2]~39_combout ), + .datad(\z80_|pin_control_|bus_db_pin_re~combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [2]), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] .lut_mask = 16'hF888; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y13_N5 +dffeas \z80_|data_pins_|dout[2] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [2]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|data_pins_|dout [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|data_pins_|dout[2] .is_wysiwyg = "true"; +defparam \z80_|data_pins_|dout[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N6 +cycloneive_lcell_comb \z80_|bus_control_|db[2]~12 ( +// Equation(s): +// \z80_|bus_control_|db[2]~12_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[2]~29_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) + + .dataa(\z80_|bus_control_|db[0]~4_combout ), + .datab(gnd), + .datac(\z80_|alu_control_|db[2]~29_combout ), + .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[2]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[2]~12 .lut_mask = 16'hA0AA; +defparam \z80_|bus_control_|db[2]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N0 +cycloneive_lcell_comb \z80_|bus_control_|db[2]~13 ( +// Equation(s): +// \z80_|bus_control_|db[2]~13_combout = ((\z80_|bus_control_|db[2]~12_combout & ((\z80_|data_pins_|dout [2]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) + + .dataa(\z80_|bus_control_|db[0]~6_combout ), + .datab(\z80_|execute_|ctl_bus_db_oe~combout ), + .datac(\z80_|data_pins_|dout [2]), + .datad(\z80_|bus_control_|db[2]~12_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[2]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[2]~13 .lut_mask = 16'hF755; +defparam \z80_|bus_control_|db[2]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y13_N27 +dffeas \z80_|ir_|opcode[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|bus_control_|db[2]~13_combout ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|ir_|opcode [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|ir_|opcode[2] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N18 +cycloneive_lcell_comb \z80_|pla_decode_|Equal1~4 ( +// Equation(s): +// \z80_|pla_decode_|Equal1~4_combout = (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [1]) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|ir_|opcode [1]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal1~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal1~4 .lut_mask = 16'h0303; +defparam \z80_|pla_decode_|Equal1~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~26 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~26_combout = (\z80_|pla_decode_|Equal1~4_combout & (\z80_|execute_|ctl_mWrite~5_combout & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|ir_|opcode [0]))) + + .dataa(\z80_|pla_decode_|Equal1~4_combout ), + .datab(\z80_|execute_|ctl_mWrite~5_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~26 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_alu_op_low~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~45 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~45_combout = (!\z80_|execute_|ctl_alu_op_low~26_combout & (((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|pla_decode_|Equal13~2_combout )) # (!\z80_|sequencer_|DFFE_M4_ff~q ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~26_combout ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~45 .lut_mask = 16'h1555; +defparam \z80_|execute_|ctl_alu_op_low~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|setM1~17 ( +// Equation(s): +// \z80_|execute_|setM1~17_combout = (!\z80_|execute_|ctl_alu_shift_oe~15_combout & (\z80_|execute_|ctl_sw_2u~1_combout & \z80_|execute_|ctl_state_alu~7_combout )) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~15_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_sw_2u~1_combout ), + .datad(\z80_|execute_|ctl_state_alu~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~17 .lut_mask = 16'h5000; +defparam \z80_|execute_|setM1~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|setM1~18 ( +// Equation(s): +// \z80_|execute_|setM1~18_combout = (\z80_|execute_|ctl_alu_op_low~45_combout & (\z80_|execute_|setM1~17_combout & (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & !\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~45_combout ), + .datab(\z80_|execute_|setM1~17_combout ), + .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~18 .lut_mask = 16'h0008; +defparam \z80_|execute_|setM1~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|setM1~11 ( +// Equation(s): +// \z80_|execute_|setM1~11_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ) # ((!\z80_|ir_|opcode [2] & (\z80_|execute_|ctl_mWrite~4_combout & !\z80_|ir_|opcode [4]))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|setM1~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~11 .lut_mask = 16'hAABA; +defparam \z80_|execute_|setM1~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|setM1~10 ( +// Equation(s): +// \z80_|execute_|setM1~10_combout = (\z80_|execute_|ctl_mRead~5_combout ) # (((\z80_|execute_|ctl_mWrite~6_combout ) # (\z80_|pla_decode_|Equal6~1_combout )) # (!\z80_|execute_|fMWrite~1_combout )) + + .dataa(\z80_|execute_|ctl_mRead~5_combout ), + .datab(\z80_|execute_|fMWrite~1_combout ), + .datac(\z80_|execute_|ctl_mWrite~6_combout ), + .datad(\z80_|pla_decode_|Equal6~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~10 .lut_mask = 16'hFFFB; +defparam \z80_|execute_|setM1~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|setM1~12 ( +// Equation(s): +// \z80_|execute_|setM1~12_combout = ((\z80_|execute_|setM1~10_combout ) # ((\z80_|execute_|setM1~11_combout & \z80_|execute_|ctl_mWrite~17_combout ))) # (!\z80_|execute_|nextM~2_combout ) + + .dataa(\z80_|execute_|nextM~2_combout ), + .datab(\z80_|execute_|setM1~11_combout ), + .datac(\z80_|execute_|ctl_mWrite~17_combout ), + .datad(\z80_|execute_|setM1~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~12 .lut_mask = 16'hFFD5; +defparam \z80_|execute_|setM1~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|setM1~8 ( +// Equation(s): +// \z80_|execute_|setM1~8_combout = (\z80_|execute_|ctl_al_we~13_combout & (\z80_|sequencer_|M5~q & ((\z80_|pla_decode_|Equal9~1_combout )))) # (!\z80_|execute_|ctl_al_we~13_combout & ((\z80_|sequencer_|DFFE_M4_ff~q ) # ((\z80_|sequencer_|M5~q & +// \z80_|pla_decode_|Equal9~1_combout )))) + + .dataa(\z80_|execute_|ctl_al_we~13_combout ), + .datab(\z80_|sequencer_|M5~q ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~8 .lut_mask = 16'hDC50; +defparam \z80_|execute_|setM1~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|setM1~9 ( +// Equation(s): +// \z80_|execute_|setM1~9_combout = ((\z80_|sequencer_|DFFE_T5_ff~q & \z80_|execute_|setM1~8_combout )) # (!\z80_|execute_|ctl_flags_xy_we~19_combout ) + + .dataa(\z80_|execute_|ctl_flags_xy_we~19_combout ), + .datab(\z80_|sequencer_|DFFE_T5_ff~q ), + .datac(gnd), + .datad(\z80_|execute_|setM1~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~9 .lut_mask = 16'hDD55; +defparam \z80_|execute_|setM1~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|setM1~13 ( +// Equation(s): +// \z80_|execute_|setM1~13_combout = ((\z80_|execute_|setM1~9_combout ) # ((\z80_|execute_|setM1~12_combout & \z80_|execute_|ixy_d~6_combout ))) # (!\z80_|reg_control_|reg_sel_pc~3_combout ) + + .dataa(\z80_|reg_control_|reg_sel_pc~3_combout ), + .datab(\z80_|execute_|setM1~12_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|setM1~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~13 .lut_mask = 16'hFFD5; +defparam \z80_|execute_|setM1~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|setM1~15 ( +// Equation(s): +// \z80_|execute_|setM1~15_combout = (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|pla_decode_|Equal13~0_combout & ((!\z80_|pla_decode_|Equal21~2_combout ) # (!\z80_|pla_decode_|Equal32~0_combout )))) # (!\z80_|pla_decode_|Equal33~0_combout & +// (((!\z80_|pla_decode_|Equal21~2_combout )) # (!\z80_|pla_decode_|Equal32~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|pla_decode_|Equal32~0_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|pla_decode_|Equal21~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~15 .lut_mask = 16'h135F; +defparam \z80_|execute_|setM1~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|setM1~14 ( +// Equation(s): +// \z80_|execute_|setM1~14_combout = (!\z80_|execute_|ctl_alu_oe~1_combout & (!\z80_|pla_decode_|Equal77~1_combout & (!\z80_|pla_decode_|Equal1~6_combout & !\z80_|pla_decode_|Equal2~2_combout ))) + + .dataa(\z80_|execute_|ctl_alu_oe~1_combout ), + .datab(\z80_|pla_decode_|Equal77~1_combout ), + .datac(\z80_|pla_decode_|Equal1~6_combout ), + .datad(\z80_|pla_decode_|Equal2~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~14 .lut_mask = 16'h0001; +defparam \z80_|execute_|setM1~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|setM1~16 ( +// Equation(s): +// \z80_|execute_|setM1~16_combout = (\z80_|interrupts_|test1~2_combout & (\z80_|execute_|setM1~15_combout & \z80_|execute_|setM1~14_combout )) + + .dataa(gnd), + .datab(\z80_|interrupts_|test1~2_combout ), + .datac(\z80_|execute_|setM1~15_combout ), + .datad(\z80_|execute_|setM1~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~16 .lut_mask = 16'hC000; +defparam \z80_|execute_|setM1~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|setM1~19 ( +// Equation(s): +// \z80_|execute_|setM1~19_combout = ((\z80_|execute_|setM1~13_combout ) # ((!\z80_|execute_|setM1~16_combout & \z80_|execute_|ctl_eval_cond~0_combout ))) # (!\z80_|execute_|setM1~18_combout ) + + .dataa(\z80_|execute_|setM1~18_combout ), + .datab(\z80_|execute_|setM1~13_combout ), + .datac(\z80_|execute_|setM1~16_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~19 .lut_mask = 16'hDFDD; +defparam \z80_|execute_|setM1~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N16 +cycloneive_lcell_comb \z80_|execute_|setM1~23 ( +// Equation(s): +// \z80_|execute_|setM1~23_combout = (\z80_|execute_|fMWrite~1_combout & (!\z80_|execute_|ctl_mRead~8_combout & (!\z80_|execute_|ctl_mRead~6_combout & \z80_|execute_|fMWrite~6_combout ))) + + .dataa(\z80_|execute_|fMWrite~1_combout ), + .datab(\z80_|execute_|ctl_mRead~8_combout ), + .datac(\z80_|execute_|ctl_mRead~6_combout ), + .datad(\z80_|execute_|fMWrite~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~23 .lut_mask = 16'h0200; +defparam \z80_|execute_|setM1~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|setM1~22 ( +// Equation(s): +// \z80_|execute_|setM1~22_combout = (\z80_|decode_state_|DFFE_instNonRep~q ) # ((!\z80_|ir_|opcode [2] & (\z80_|execute_|ctl_mWrite~4_combout & !\z80_|ir_|opcode [4]))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|execute_|ctl_mWrite~4_combout ), + .datac(\z80_|decode_state_|DFFE_instNonRep~q ), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|setM1~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~22 .lut_mask = 16'hF0F4; +defparam \z80_|execute_|setM1~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|setM1~56 ( +// Equation(s): +// \z80_|execute_|setM1~56_combout = (\z80_|sequencer_|DFFE_T5_ff~q & ((\z80_|sequencer_|DFFE_M4_ff~q ) # ((\z80_|sequencer_|DFFE_M3_ff~q & \z80_|execute_|setM1~22_combout )))) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|sequencer_|DFFE_T5_ff~q ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|execute_|setM1~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~56_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~56 .lut_mask = 16'hC8C0; +defparam \z80_|execute_|setM1~56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|setM1~24 ( +// Equation(s): +// \z80_|execute_|setM1~24_combout = (\z80_|execute_|setM1~23_combout & (!\z80_|execute_|ctl_flags_bus~1_combout & ((\z80_|execute_|setM1~56_combout )))) # (!\z80_|execute_|setM1~23_combout & ((\z80_|execute_|ctl_reg_in_hi~2_combout ) # +// ((!\z80_|execute_|ctl_flags_bus~1_combout & \z80_|execute_|setM1~56_combout )))) + + .dataa(\z80_|execute_|setM1~23_combout ), + .datab(\z80_|execute_|ctl_flags_bus~1_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datad(\z80_|execute_|setM1~56_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~24 .lut_mask = 16'h7350; +defparam \z80_|execute_|setM1~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|setM1~25 ( +// Equation(s): +// \z80_|execute_|setM1~25_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & (((\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & !\z80_|execute_|ctl_mRead~10_combout )) # (!\z80_|alu_control_|flags_cond_true~q ))) # +// (!\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & (((\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & !\z80_|execute_|ctl_mRead~10_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), + .datab(\z80_|alu_control_|flags_cond_true~q ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .datad(\z80_|execute_|ctl_mRead~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~25 .lut_mask = 16'h22F2; +defparam \z80_|execute_|setM1~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|setM1~26 ( +// Equation(s): +// \z80_|execute_|setM1~26_combout = ((\z80_|execute_|ctl_mRead~11_combout ) # ((!\z80_|alu_control_|flags_cond_true~q & \z80_|pla_decode_|Equal40~1_combout ))) # (!\z80_|execute_|ctl_bus_inc_oe~31_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~31_combout ), + .datab(\z80_|alu_control_|flags_cond_true~q ), + .datac(\z80_|pla_decode_|Equal40~1_combout ), + .datad(\z80_|execute_|ctl_mRead~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~26 .lut_mask = 16'hFF75; +defparam \z80_|execute_|setM1~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|setM1~27 ( +// Equation(s): +// \z80_|execute_|setM1~27_combout = (\z80_|execute_|setM1~26_combout ) # (((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & \z80_|pla_decode_|Equal21~1_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout )) + + .dataa(\z80_|execute_|setM1~26_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ), + .datad(\z80_|pla_decode_|Equal21~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~27 .lut_mask = 16'hEFAF; +defparam \z80_|execute_|setM1~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|setM1~28 ( +// Equation(s): +// \z80_|execute_|setM1~28_combout = (\z80_|execute_|setM1~24_combout ) # ((\z80_|execute_|setM1~25_combout ) # ((\z80_|execute_|ctl_state_alu~2_combout & \z80_|execute_|setM1~27_combout ))) + + .dataa(\z80_|execute_|setM1~24_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|execute_|setM1~25_combout ), + .datad(\z80_|execute_|setM1~27_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~28 .lut_mask = 16'hFEFA; +defparam \z80_|execute_|setM1~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|setM1~55 ( +// Equation(s): +// \z80_|execute_|setM1~55_combout = ((\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|execute_|ctl_iorw~10_combout ))) # (!\z80_|execute_|ctl_flags_sz_we~0_combout ) + + .dataa(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|execute_|ctl_iorw~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~55_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~55 .lut_mask = 16'hD555; +defparam \z80_|execute_|setM1~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|setM1~29 ( +// Equation(s): +// \z80_|execute_|setM1~29_combout = (\z80_|execute_|ctl_mRead~13_combout ) # ((\z80_|execute_|ctl_mRead~5_combout ) # ((\z80_|execute_|ctl_mRead~7_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~13_combout ), + .datab(\z80_|execute_|ctl_mRead~5_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ), + .datad(\z80_|execute_|ctl_mRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~29 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|setM1~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|setM1~31 ( +// Equation(s): +// \z80_|execute_|setM1~31_combout = (((\z80_|execute_|ctl_state_alu~4_combout & \z80_|execute_|setM1~29_combout )) # (!\z80_|execute_|setM1~57_combout )) # (!\z80_|execute_|setM1~30_combout ) + + .dataa(\z80_|execute_|setM1~30_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|setM1~29_combout ), + .datad(\z80_|execute_|setM1~57_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~31 .lut_mask = 16'hD5FF; +defparam \z80_|execute_|setM1~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|setM1~33 ( +// Equation(s): +// \z80_|execute_|setM1~33_combout = (\z80_|execute_|ctl_mRead~2_combout ) # ((\z80_|execute_|ctl_mRead~3_combout ) # ((\z80_|execute_|ctl_mRead~34_combout & \z80_|execute_|setM1~11_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~2_combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|execute_|setM1~11_combout ), + .datad(\z80_|execute_|ctl_mRead~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~33 .lut_mask = 16'hFFEA; +defparam \z80_|execute_|setM1~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|setM1~32 ( +// Equation(s): +// \z80_|execute_|setM1~32_combout = (\z80_|pla_decode_|Equal35~0_combout & ((\z80_|execute_|ixy_d~6_combout ) # ((\z80_|execute_|ctl_reg_in_hi~2_combout & \z80_|execute_|ctl_mRead~16_combout )))) # (!\z80_|pla_decode_|Equal35~0_combout & +// (\z80_|execute_|ctl_reg_in_hi~2_combout & ((\z80_|execute_|ctl_mRead~16_combout )))) + + .dataa(\z80_|pla_decode_|Equal35~0_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ctl_mRead~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~32 .lut_mask = 16'hECA0; +defparam \z80_|execute_|setM1~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|setM1~34 ( +// Equation(s): +// \z80_|execute_|setM1~34_combout = (\z80_|execute_|setM1~31_combout ) # ((\z80_|execute_|setM1~32_combout ) # ((\z80_|execute_|setM1~33_combout & \z80_|execute_|ixy_d~9_combout ))) + + .dataa(\z80_|execute_|setM1~31_combout ), + .datab(\z80_|execute_|setM1~33_combout ), + .datac(\z80_|execute_|ixy_d~9_combout ), + .datad(\z80_|execute_|setM1~32_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~34 .lut_mask = 16'hFFEA; +defparam \z80_|execute_|setM1~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|setM1~20 ( +// Equation(s): +// \z80_|execute_|setM1~20_combout = (\z80_|execute_|ctl_mRead~9_combout & (((\z80_|pla_decode_|Equal37~0_combout & !\z80_|alu_control_|flags_cond_true~q )) # (!\z80_|execute_|ctl_flags_bus~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal37~0_combout ), + .datab(\z80_|alu_control_|flags_cond_true~q ), + .datac(\z80_|execute_|ctl_mRead~9_combout ), + .datad(\z80_|execute_|ctl_flags_bus~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~20 .lut_mask = 16'h20F0; +defparam \z80_|execute_|setM1~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|setM1~21 ( +// Equation(s): +// \z80_|execute_|setM1~21_combout = (\z80_|execute_|setM1~20_combout ) # ((\z80_|execute_|ixy_d~8_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & \z80_|pla_decode_|Equal10~0_combout ))) + + .dataa(\z80_|execute_|ixy_d~8_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|execute_|setM1~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~21 .lut_mask = 16'hFF80; +defparam \z80_|execute_|setM1~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|setM1~35 ( +// Equation(s): +// \z80_|execute_|setM1~35_combout = (\z80_|execute_|setM1~28_combout ) # ((\z80_|execute_|setM1~55_combout ) # ((\z80_|execute_|setM1~34_combout ) # (\z80_|execute_|setM1~21_combout ))) + + .dataa(\z80_|execute_|setM1~28_combout ), + .datab(\z80_|execute_|setM1~55_combout ), + .datac(\z80_|execute_|setM1~34_combout ), + .datad(\z80_|execute_|setM1~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~35 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|setM1~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|setM1~43 ( +// Equation(s): +// \z80_|execute_|setM1~43_combout = (!\z80_|execute_|ctl_mWrite~6_combout & (!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~9_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datac(\z80_|execute_|ctl_ir_we~10_combout ), + .datad(\z80_|execute_|ctl_ir_we~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~43 .lut_mask = 16'h0003; +defparam \z80_|execute_|setM1~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N6 +cycloneive_lcell_comb \z80_|execute_|setM1~44 ( +// Equation(s): +// \z80_|execute_|setM1~44_combout = (!\z80_|pla_decode_|Equal47~0_combout & (!\z80_|pla_decode_|Equal37~0_combout & (!\z80_|pla_decode_|Equal38~2_combout & \z80_|sequencer_|DFFE_T4_ff~q ))) + + .dataa(\z80_|pla_decode_|Equal47~0_combout ), + .datab(\z80_|pla_decode_|Equal37~0_combout ), + .datac(\z80_|pla_decode_|Equal38~2_combout ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|setM1~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~44 .lut_mask = 16'h0100; +defparam \z80_|execute_|setM1~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N18 +cycloneive_lcell_comb \z80_|execute_|setM1~45 ( +// Equation(s): +// \z80_|execute_|setM1~45_combout = (!\z80_|pla_decode_|Equal21~1_combout & (\z80_|execute_|setM1~43_combout & (!\z80_|pla_decode_|Equal48~0_combout & \z80_|execute_|setM1~44_combout ))) + + .dataa(\z80_|pla_decode_|Equal21~1_combout ), + .datab(\z80_|execute_|setM1~43_combout ), + .datac(\z80_|pla_decode_|Equal48~0_combout ), + .datad(\z80_|execute_|setM1~44_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~45 .lut_mask = 16'h0400; +defparam \z80_|execute_|setM1~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|setM1~46 ( +// Equation(s): +// \z80_|execute_|setM1~46_combout = (\z80_|execute_|setM1~45_combout & (\z80_|execute_|setM1~42_combout & ((!\z80_|pla_decode_|Equal1~4_combout ) # (!\z80_|pla_decode_|Equal2~1_combout )))) + + .dataa(\z80_|execute_|setM1~45_combout ), + .datab(\z80_|pla_decode_|Equal2~1_combout ), + .datac(\z80_|pla_decode_|Equal1~4_combout ), + .datad(\z80_|execute_|setM1~42_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~46 .lut_mask = 16'h2A00; +defparam \z80_|execute_|setM1~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|setM1~52 ( +// Equation(s): +// \z80_|execute_|setM1~52_combout = (\z80_|execute_|setM1~48_combout & (\z80_|execute_|setM1~46_combout & (\z80_|execute_|setM1~16_combout & \z80_|execute_|setM1~51_combout ))) + + .dataa(\z80_|execute_|setM1~48_combout ), + .datab(\z80_|execute_|setM1~46_combout ), + .datac(\z80_|execute_|setM1~16_combout ), + .datad(\z80_|execute_|setM1~51_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~52_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~52 .lut_mask = 16'h8000; +defparam \z80_|execute_|setM1~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N4 +cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_17 ( +// Equation(s): +// \z80_|sequencer_|SYNTHESIZED_WIRE_17~combout = (\z80_|execute_|setM1~54_combout & (\z80_|sequencer_|DFFE_T5_ff~q & !\z80_|execute_|nextM~14_combout )) + + .dataa(\z80_|execute_|setM1~54_combout ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T5_ff~q ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_17~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_17 .lut_mask = 16'h00A0; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y12_N5 +dffeas \z80_|sequencer_|T6 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|SYNTHESIZED_WIRE_17~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|T6~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|T6 .is_wysiwyg = "true"; +defparam \z80_|sequencer_|T6 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|setM1~53 ( +// Equation(s): +// \z80_|execute_|setM1~53_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|execute_|setM1~41_combout ) # ((\z80_|sequencer_|T6~q & !\z80_|execute_|setM1~42_combout )))) # (!\z80_|execute_|setM1~52_combout & (((\z80_|sequencer_|T6~q & +// !\z80_|execute_|setM1~42_combout )))) + + .dataa(\z80_|execute_|setM1~52_combout ), + .datab(\z80_|execute_|setM1~41_combout ), + .datac(\z80_|sequencer_|T6~q ), + .datad(\z80_|execute_|setM1~42_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~53_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~53 .lut_mask = 16'h88F8; +defparam \z80_|execute_|setM1~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|setM1~54 ( +// Equation(s): +// \z80_|execute_|setM1~54_combout = (!\z80_|execute_|setM1~19_combout & (!\z80_|execute_|setM1~35_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|execute_|setM1~53_combout )))) + + .dataa(\z80_|execute_|setM1~19_combout ), + .datab(\z80_|execute_|setM1~35_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|execute_|setM1~53_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~54_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~54 .lut_mask = 16'h1011; +defparam \z80_|execute_|setM1~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N28 +cycloneive_lcell_comb \z80_|sequencer_|DFFE_M1_ff~0 ( +// Equation(s): +// \z80_|sequencer_|DFFE_M1_ff~0_combout = (\z80_|execute_|setM1~54_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # (\z80_|execute_|nextM~14_combout ))) + + .dataa(gnd), + .datab(\z80_|execute_|setM1~54_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|DFFE_M1_ff~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_M1_ff~0 .lut_mask = 16'hCCC0; +defparam \z80_|sequencer_|DFFE_M1_ff~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y13_N29 +dffeas \z80_|sequencer_|DFFE_M1_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|DFFE_M1_ff~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_M1_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_M1_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_M1_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X52_Y17_N4 +cycloneive_lcell_comb \z80_|resets_|x1~0 ( +// Equation(s): +// \z80_|resets_|x1~0_combout = !\reset~combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\reset~combout ), + .cin(gnd), + .combout(\z80_|resets_|x1~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|resets_|x1~0 .lut_mask = 16'h00FF; +defparam \z80_|resets_|x1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y16_N16 +cycloneive_lcell_comb \z80_|fpga_reset~feeder ( +// Equation(s): +// \z80_|fpga_reset~feeder_combout = VCC + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\z80_|fpga_reset~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|fpga_reset~feeder .lut_mask = 16'hFFFF; +defparam \z80_|fpga_reset~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X1_Y16_N17 +dffeas \z80_|fpga_reset ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|fpga_reset~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|fpga_reset~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|fpga_reset .is_wysiwyg = "true"; +defparam \z80_|fpga_reset .power_up = "low"; +// synopsys translate_on + +// Location: CLKCTRL_G2 +cycloneive_clkctrl \z80_|fpga_reset~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\z80_|fpga_reset~q }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\z80_|fpga_reset~clkctrl_outclk )); +// synopsys translate_off +defparam \z80_|fpga_reset~clkctrl .clock_type = "global clock"; +defparam \z80_|fpga_reset~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: FF_X52_Y17_N5 +dffeas \z80_|resets_|x1 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|resets_|x1~0_combout ), + .asdata(vcc), + .clrn(\z80_|fpga_reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|resets_|x1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|resets_|x1 .is_wysiwyg = "true"; +defparam \z80_|resets_|x1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X52_Y17_N12 +cycloneive_lcell_comb \z80_|resets_|x3 ( +// Equation(s): +// \z80_|resets_|x3~combout = (\z80_|resets_|x1~q ) # ((!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T2_ff~q )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|resets_|x1~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|resets_|x3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|resets_|x3 .lut_mask = 16'hF3F0; +defparam \z80_|resets_|x3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X52_Y17_N13 +dffeas \z80_|resets_|SYNTHESIZED_WIRE_12 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|resets_|x3~combout ), + .asdata(vcc), + .clrn(\z80_|fpga_reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|resets_|SYNTHESIZED_WIRE_12 .is_wysiwyg = "true"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_12 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N28 +cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_10~0 ( +// Equation(s): +// \z80_|resets_|SYNTHESIZED_WIRE_10~0_combout = !\z80_|resets_|SYNTHESIZED_WIRE_12~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .cin(gnd), + .combout(\z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|resets_|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h00FF; +defparam \z80_|resets_|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y13_N29 +dffeas \z80_|resets_|SYNTHESIZED_WIRE_10 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|resets_|SYNTHESIZED_WIRE_10 .is_wysiwyg = "true"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_10 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N22 +cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_9~feeder ( +// Equation(s): +// \z80_|resets_|SYNTHESIZED_WIRE_9~feeder_combout = \z80_|resets_|SYNTHESIZED_WIRE_10~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), + .cin(gnd), + .combout(\z80_|resets_|SYNTHESIZED_WIRE_9~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|resets_|SYNTHESIZED_WIRE_9~feeder .lut_mask = 16'hFF00; +defparam \z80_|resets_|SYNTHESIZED_WIRE_9~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y13_N23 +dffeas \z80_|resets_|SYNTHESIZED_WIRE_9 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|resets_|SYNTHESIZED_WIRE_9~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|resets_|SYNTHESIZED_WIRE_9 .is_wysiwyg = "true"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_9 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X36_Y13_N19 +dffeas \z80_|resets_|DFFE_intr_ff3 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|resets_|DFFE_intr_ff3~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|resets_|DFFE_intr_ff3 .is_wysiwyg = "true"; +defparam \z80_|resets_|DFFE_intr_ff3 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N0 +cycloneive_lcell_comb \z80_|resets_|clrpc_int~0 ( +// Equation(s): +// \z80_|resets_|clrpc_int~0_combout = (\z80_|sequencer_|DFFE_M1_ff~q & (((\z80_|resets_|clrpc_int~q )))) # (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|resets_|clrpc_int~q & !\z80_|resets_|x1~q )) # +// (!\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|resets_|clrpc_int~q )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|resets_|clrpc_int~q ), + .datad(\z80_|resets_|x1~q ), + .cin(gnd), + .combout(\z80_|resets_|clrpc_int~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|resets_|clrpc_int~0 .lut_mask = 16'hB0B4; +defparam \z80_|resets_|clrpc_int~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y13_N1 +dffeas \z80_|resets_|clrpc_int ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|resets_|clrpc_int~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|resets_|clrpc_int~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|resets_|clrpc_int .is_wysiwyg = "true"; +defparam \z80_|resets_|clrpc_int .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N18 +cycloneive_lcell_comb \z80_|resets_|clrpc~0 ( +// Equation(s): +// \z80_|resets_|clrpc~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_9~q ) # ((\z80_|resets_|SYNTHESIZED_WIRE_10~q ) # ((\z80_|resets_|DFFE_intr_ff3~q ) # (\z80_|resets_|clrpc_int~q ))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), + .datac(\z80_|resets_|DFFE_intr_ff3~q ), + .datad(\z80_|resets_|clrpc_int~q ), + .cin(gnd), + .combout(\z80_|resets_|clrpc~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|resets_|clrpc~0 .lut_mask = 16'hFFFE; +defparam \z80_|resets_|clrpc~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N2 +cycloneive_lcell_comb \z80_|address_latch_|abusz[0] ( +// Equation(s): +// \z80_|address_latch_|abusz [0] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[0]~3_combout ) + + .dataa(gnd), + .datab(\z80_|resets_|clrpc~0_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|db_lo_as[0]~3_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [0]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[0] .lut_mask = 16'h3300; +defparam \z80_|address_latch_|abusz[0] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N24 cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[0]~0 ( // Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[0]~0_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [0]))) +// \z80_|address_pins_|DFFE_apin_latch[0]~0_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [0])) - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), + .dataa(\z80_|address_latch_|abusz [0]), + .datab(\z80_|execute_|ctl_apin_mux~2_combout ), .datac(gnd), - .datad(\z80_|address_latch_|abusz [0]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), .cin(gnd), .combout(\z80_|address_pins_|DFFE_apin_latch[0]~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[0]~0 .lut_mask = 16'hDD88; +defparam \z80_|address_pins_|DFFE_apin_latch[0]~0 .lut_mask = 16'hEE22; defparam \z80_|address_pins_|DFFE_apin_latch[0]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y16_N19 +// Location: FF_X34_Y11_N25 dffeas \z80_|address_pins_|DFFE_apin_latch[0] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|address_pins_|DFFE_apin_latch[0]~0_combout ), @@ -53241,7 +53008,7 @@ dffeas \z80_|address_pins_|DFFE_apin_latch[0] ( .aload(gnd), .sclr(gnd), .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~1_combout ), .devclrn(devclrn), .devpor(devpor), .q(\z80_|address_pins_|DFFE_apin_latch [0]), @@ -53251,228 +53018,228 @@ defparam \z80_|address_pins_|DFFE_apin_latch[0] .is_wysiwyg = "true"; defparam \z80_|address_pins_|DFFE_apin_latch[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y14_N12 -cycloneive_lcell_comb \D[0]~59 ( +// Location: LCCOMB_X23_Y14_N20 +cycloneive_lcell_comb \D[0]~47 ( // Equation(s): -// \D[0]~59_combout = (\Equal2~0_combout & (\D[0]~51_combout )) # (!\Equal2~0_combout & ((\D[0]~106_combout ))) +// \D[0]~47_combout = (\Equal2~0_combout & (\D[0]~44_combout )) # (!\Equal2~0_combout & ((\D[0]~83_combout ))) .dataa(\Equal2~0_combout ), - .datab(\D[0]~51_combout ), - .datac(\D[0]~106_combout ), + .datab(\D[0]~44_combout ), + .datac(\D[0]~83_combout ), .datad(gnd), .cin(gnd), - .combout(\D[0]~59_combout ), + .combout(\D[0]~47_combout ), .cout()); // synopsys translate_off -defparam \D[0]~59 .lut_mask = 16'hD8D8; -defparam \D[0]~59 .sum_lutc_input = "datac"; +defparam \D[0]~47 .lut_mask = 16'hD8D8; +defparam \D[0]~47 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N8 -cycloneive_lcell_comb \D[0]~60 ( +// Location: LCCOMB_X24_Y14_N24 +cycloneive_lcell_comb \D[0]~48 ( // Equation(s): -// \D[0]~60_combout = (\Equal2~1_combout & (\D[0]~59_combout & ((\z80_|data_pins_|dout [0]) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) # (!\Equal2~1_combout & ((\z80_|data_pins_|dout [0]) # ((!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) +// \D[0]~48_combout = (\z80_|data_pins_|dout [0] & (((\D[0]~47_combout ) # (!\Equal2~1_combout )))) # (!\z80_|data_pins_|dout [0] & (!\z80_|pin_control_|bus_db_pin_oe~15_combout & ((\D[0]~47_combout ) # (!\Equal2~1_combout )))) + + .dataa(\z80_|data_pins_|dout [0]), + .datab(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .datac(\Equal2~1_combout ), + .datad(\D[0]~47_combout ), + .cin(gnd), + .combout(\D[0]~48_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~48 .lut_mask = 16'hBB0B; +defparam \D[0]~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N12 +cycloneive_lcell_comb \D[1]~49 ( +// Equation(s): +// \D[1]~49_combout = (\Equal2~0_combout & (\D[1]~30_combout )) # (!\Equal2~0_combout & ((\D[1]~81_combout ))) + + .dataa(\D[1]~30_combout ), + .datab(gnd), + .datac(\Equal2~0_combout ), + .datad(\D[1]~81_combout ), + .cin(gnd), + .combout(\D[1]~49_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~49 .lut_mask = 16'hAFA0; +defparam \D[1]~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N18 +cycloneive_lcell_comb \D[1]~50 ( +// Equation(s): +// \D[1]~50_combout = (\Equal2~1_combout & (\D[1]~49_combout & ((\z80_|data_pins_|dout [1]) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout )))) # (!\Equal2~1_combout & ((\z80_|data_pins_|dout [1]) # ((!\z80_|pin_control_|bus_db_pin_oe~15_combout )))) .dataa(\Equal2~1_combout ), - .datab(\z80_|data_pins_|dout [0]), - .datac(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datad(\D[0]~59_combout ), + .datab(\z80_|data_pins_|dout [1]), + .datac(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .datad(\D[1]~49_combout ), .cin(gnd), - .combout(\D[0]~60_combout ), + .combout(\D[1]~50_combout ), .cout()); // synopsys translate_off -defparam \D[0]~60 .lut_mask = 16'hCF45; -defparam \D[0]~60 .sum_lutc_input = "datac"; +defparam \D[1]~50 .lut_mask = 16'hCF45; +defparam \D[1]~50 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y18_N20 -cycloneive_lcell_comb \D[1]~61 ( +// Location: LCCOMB_X23_Y10_N2 +cycloneive_lcell_comb \D[2]~51 ( // Equation(s): -// \D[1]~61_combout = (\Equal2~0_combout & (\D[1]~32_combout )) # (!\Equal2~0_combout & ((\D[1]~103_combout ))) +// \D[2]~51_combout = (\Equal2~0_combout & (\D[2]~37_combout )) # (!\Equal2~0_combout & ((\D[2]~82_combout ))) - .dataa(\Equal2~0_combout ), + .dataa(\D[2]~37_combout ), .datab(gnd), - .datac(\D[1]~32_combout ), - .datad(\D[1]~103_combout ), + .datac(\Equal2~0_combout ), + .datad(\D[2]~82_combout ), .cin(gnd), - .combout(\D[1]~61_combout ), + .combout(\D[2]~51_combout ), .cout()); // synopsys translate_off -defparam \D[1]~61 .lut_mask = 16'hF5A0; -defparam \D[1]~61 .sum_lutc_input = "datac"; +defparam \D[2]~51 .lut_mask = 16'hAFA0; +defparam \D[2]~51 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y18_N22 -cycloneive_lcell_comb \D[1]~62 ( +// Location: LCCOMB_X24_Y10_N2 +cycloneive_lcell_comb \D[2]~52 ( // Equation(s): -// \D[1]~62_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout & (\z80_|data_pins_|dout [1] & ((\D[1]~61_combout ) # (!\Equal2~1_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\D[1]~61_combout )) # (!\Equal2~1_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datab(\Equal2~1_combout ), - .datac(\z80_|data_pins_|dout [1]), - .datad(\D[1]~61_combout ), - .cin(gnd), - .combout(\D[1]~62_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~62 .lut_mask = 16'hF531; -defparam \D[1]~62 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N12 -cycloneive_lcell_comb \D[2]~63 ( -// Equation(s): -// \D[2]~63_combout = (\Equal2~0_combout & (\D[2]~104_combout )) # (!\Equal2~0_combout & ((\D[2]~105_combout ))) - - .dataa(\Equal2~0_combout ), - .datab(gnd), - .datac(\D[2]~104_combout ), - .datad(\D[2]~105_combout ), - .cin(gnd), - .combout(\D[2]~63_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~63 .lut_mask = 16'hF5A0; -defparam \D[2]~63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N26 -cycloneive_lcell_comb \D[2]~64 ( -// Equation(s): -// \D[2]~64_combout = (\z80_|data_pins_|dout [2] & (((\D[2]~63_combout )) # (!\Equal2~1_combout ))) # (!\z80_|data_pins_|dout [2] & (!\z80_|pin_control_|bus_db_pin_oe~14_combout & ((\D[2]~63_combout ) # (!\Equal2~1_combout )))) +// \D[2]~52_combout = (\z80_|data_pins_|dout [2] & (((\D[2]~51_combout )) # (!\Equal2~1_combout ))) # (!\z80_|data_pins_|dout [2] & (!\z80_|pin_control_|bus_db_pin_oe~15_combout & ((\D[2]~51_combout ) # (!\Equal2~1_combout )))) .dataa(\z80_|data_pins_|dout [2]), .datab(\Equal2~1_combout ), - .datac(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datad(\D[2]~63_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .datad(\D[2]~51_combout ), .cin(gnd), - .combout(\D[2]~64_combout ), + .combout(\D[2]~52_combout ), .cout()); // synopsys translate_off -defparam \D[2]~64 .lut_mask = 16'hAF23; -defparam \D[2]~64 .sum_lutc_input = "datac"; +defparam \D[2]~52 .lut_mask = 16'hAF23; +defparam \D[2]~52 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N2 -cycloneive_lcell_comb \D[3]~75 ( +// Location: LCCOMB_X23_Y14_N18 +cycloneive_lcell_comb \D[3]~58 ( // Equation(s): -// \D[3]~75_combout = (\Equal2~0_combout & (\D[3]~69_combout )) # (!\Equal2~0_combout & ((\D[3]~108_combout ))) - - .dataa(\D[3]~69_combout ), - .datab(gnd), - .datac(\Equal2~0_combout ), - .datad(\D[3]~108_combout ), - .cin(gnd), - .combout(\D[3]~75_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~75 .lut_mask = 16'hAFA0; -defparam \D[3]~75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y15_N20 -cycloneive_lcell_comb \D[3]~76 ( -// Equation(s): -// \D[3]~76_combout = (\z80_|data_pins_|dout [3] & (((\D[3]~75_combout )) # (!\Equal2~1_combout ))) # (!\z80_|data_pins_|dout [3] & (!\z80_|pin_control_|bus_db_pin_oe~14_combout & ((\D[3]~75_combout ) # (!\Equal2~1_combout )))) - - .dataa(\z80_|data_pins_|dout [3]), - .datab(\Equal2~1_combout ), - .datac(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datad(\D[3]~75_combout ), - .cin(gnd), - .combout(\D[3]~76_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~76 .lut_mask = 16'hAF23; -defparam \D[3]~76 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N24 -cycloneive_lcell_comb \D[4]~82 ( -// Equation(s): -// \D[4]~82_combout = (\Equal2~0_combout & (\D[4]~81_combout )) # (!\Equal2~0_combout & ((\D[4]~109_combout ))) +// \D[3]~58_combout = (\Equal2~0_combout & (\D[3]~57_combout )) # (!\Equal2~0_combout & ((\D[3]~85_combout ))) .dataa(\Equal2~0_combout ), - .datab(\D[4]~81_combout ), + .datab(\D[3]~57_combout ), .datac(gnd), - .datad(\D[4]~109_combout ), + .datad(\D[3]~85_combout ), .cin(gnd), - .combout(\D[4]~82_combout ), + .combout(\D[3]~58_combout ), .cout()); // synopsys translate_off -defparam \D[4]~82 .lut_mask = 16'hDD88; -defparam \D[4]~82 .sum_lutc_input = "datac"; +defparam \D[3]~58 .lut_mask = 16'hDD88; +defparam \D[3]~58 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N26 -cycloneive_lcell_comb \D[4]~83 ( +// Location: LCCOMB_X24_Y14_N18 +cycloneive_lcell_comb \D[3]~59 ( // Equation(s): -// \D[4]~83_combout = (\Equal2~1_combout & (\D[4]~82_combout & ((\z80_|data_pins_|dout [4]) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) # (!\Equal2~1_combout & ((\z80_|data_pins_|dout [4]) # ((!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) +// \D[3]~59_combout = (\z80_|data_pins_|dout [3] & (((\D[3]~58_combout ) # (!\Equal2~1_combout )))) # (!\z80_|data_pins_|dout [3] & (!\z80_|pin_control_|bus_db_pin_oe~15_combout & ((\D[3]~58_combout ) # (!\Equal2~1_combout )))) + + .dataa(\z80_|data_pins_|dout [3]), + .datab(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .datac(\Equal2~1_combout ), + .datad(\D[3]~58_combout ), + .cin(gnd), + .combout(\D[3]~59_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~59 .lut_mask = 16'hBB0B; +defparam \D[3]~59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N0 +cycloneive_lcell_comb \D[4]~65 ( +// Equation(s): +// \D[4]~65_combout = (\Equal2~0_combout & (\D[4]~64_combout )) # (!\Equal2~0_combout & ((\D[4]~86_combout ))) + + .dataa(gnd), + .datab(\D[4]~64_combout ), + .datac(\Equal2~0_combout ), + .datad(\D[4]~86_combout ), + .cin(gnd), + .combout(\D[4]~65_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~65 .lut_mask = 16'hCFC0; +defparam \D[4]~65 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N22 +cycloneive_lcell_comb \D[4]~66 ( +// Equation(s): +// \D[4]~66_combout = (\Equal2~1_combout & (\D[4]~65_combout & ((\z80_|data_pins_|dout [4]) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout )))) # (!\Equal2~1_combout & ((\z80_|data_pins_|dout [4]) # ((!\z80_|pin_control_|bus_db_pin_oe~15_combout )))) .dataa(\Equal2~1_combout ), .datab(\z80_|data_pins_|dout [4]), - .datac(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datad(\D[4]~82_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .datad(\D[4]~65_combout ), .cin(gnd), - .combout(\D[4]~83_combout ), + .combout(\D[4]~66_combout ), .cout()); // synopsys translate_off -defparam \D[4]~83 .lut_mask = 16'hCF45; -defparam \D[4]~83 .sum_lutc_input = "datac"; +defparam \D[4]~66 .lut_mask = 16'hCF45; +defparam \D[4]~66 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N24 -cycloneive_lcell_comb \D[6]~92 ( +// Location: LCCOMB_X24_Y10_N20 +cycloneive_lcell_comb \D[6]~70 ( // Equation(s): -// \D[6]~92_combout = (\Equal2~0_combout & ((\D[6]~86_combout ))) # (!\Equal2~0_combout & (\D[6]~111_combout )) +// \D[6]~70_combout = (\Equal2~0_combout & ((\D[6]~69_combout ))) # (!\Equal2~0_combout & (\D[6]~88_combout )) - .dataa(gnd), - .datab(\Equal2~0_combout ), - .datac(\D[6]~111_combout ), - .datad(\D[6]~86_combout ), + .dataa(\Equal2~0_combout ), + .datab(gnd), + .datac(\D[6]~88_combout ), + .datad(\D[6]~69_combout ), .cin(gnd), - .combout(\D[6]~92_combout ), + .combout(\D[6]~70_combout ), .cout()); // synopsys translate_off -defparam \D[6]~92 .lut_mask = 16'hFC30; -defparam \D[6]~92 .sum_lutc_input = "datac"; +defparam \D[6]~70 .lut_mask = 16'hFA50; +defparam \D[6]~70 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N10 -cycloneive_lcell_comb \D[6]~93 ( +// Location: LCCOMB_X24_Y10_N10 +cycloneive_lcell_comb \D[6]~71 ( // Equation(s): -// \D[6]~93_combout = (\Equal2~1_combout & (\D[6]~92_combout & ((\z80_|data_pins_|dout [6]) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) # (!\Equal2~1_combout & ((\z80_|data_pins_|dout [6]) # ((!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) +// \D[6]~71_combout = (\z80_|data_pins_|dout [6] & (((\D[6]~70_combout )) # (!\Equal2~1_combout ))) # (!\z80_|data_pins_|dout [6] & (!\z80_|pin_control_|bus_db_pin_oe~15_combout & ((\D[6]~70_combout ) # (!\Equal2~1_combout )))) - .dataa(\Equal2~1_combout ), - .datab(\z80_|data_pins_|dout [6]), - .datac(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datad(\D[6]~92_combout ), + .dataa(\z80_|data_pins_|dout [6]), + .datab(\Equal2~1_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .datad(\D[6]~70_combout ), .cin(gnd), - .combout(\D[6]~93_combout ), + .combout(\D[6]~71_combout ), .cout()); // synopsys translate_off -defparam \D[6]~93 .lut_mask = 16'hCF45; -defparam \D[6]~93 .sum_lutc_input = "datac"; +defparam \D[6]~71 .lut_mask = 16'hAF23; +defparam \D[6]~71 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X43_Y17_N0 +// Location: LCCOMB_X27_Y13_N28 cycloneive_lcell_comb \z80_|nM1_int~3 ( // Equation(s): -// \z80_|nM1_int~3_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # (\z80_|sequencer_|DFFE_M1_ff~q ))) +// \z80_|nM1_int~3_combout = (\z80_|execute_|setM1~54_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # (\z80_|sequencer_|DFFE_M1_ff~q ))) - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|setM1~52_combout ), + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|execute_|setM1~54_combout ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), .cin(gnd), .combout(\z80_|nM1_int~3_combout ), .cout()); // synopsys translate_off -defparam \z80_|nM1_int~3 .lut_mask = 16'hFC00; +defparam \z80_|nM1_int~3 .lut_mask = 16'hCC88; defparam \z80_|nM1_int~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X43_Y17_N1 +// Location: FF_X27_Y13_N29 dffeas \z80_|memory_ifc_|SYNTHESIZED_WIRE_16 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|nM1_int~3_combout ), @@ -53491,7 +53258,7 @@ defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_16 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_16 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X43_Y17_N30 +// Location: LCCOMB_X27_Y11_N4 cycloneive_lcell_comb \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder ( // Equation(s): // \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder_combout = \z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q @@ -53508,7 +53275,7 @@ defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder .lut_mask = 16'hFF00; defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X43_Y17_N31 +// Location: FF_X27_Y11_N5 dffeas \z80_|memory_ifc_|SYNTHESIZED_WIRE_17 ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder_combout ), @@ -53527,7 +53294,7 @@ defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_17 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_17 .power_up = "low"; // synopsys translate_on -// Location: FF_X43_Y17_N25 +// Location: FF_X27_Y11_N11 dffeas \z80_|memory_ifc_|DFFE_mreq_ff2 ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), @@ -53546,32 +53313,32 @@ defparam \z80_|memory_ifc_|DFFE_mreq_ff2 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|DFFE_mreq_ff2 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X43_Y17_N24 +// Location: LCCOMB_X27_Y11_N10 cycloneive_lcell_comb \z80_|memory_ifc_|nMREQ_out~0 ( // Equation(s): // \z80_|memory_ifc_|nMREQ_out~0_combout = (\z80_|memory_ifc_|wait_mwr~q ) # ((\z80_|memory_ifc_|mwr_wr~q ) # ((\z80_|memory_ifc_|SYNTHESIZED_WIRE_17~q & !\z80_|memory_ifc_|DFFE_mreq_ff2~q ))) - .dataa(\z80_|memory_ifc_|SYNTHESIZED_WIRE_17~q ), - .datab(\z80_|memory_ifc_|wait_mwr~q ), + .dataa(\z80_|memory_ifc_|wait_mwr~q ), + .datab(\z80_|memory_ifc_|SYNTHESIZED_WIRE_17~q ), .datac(\z80_|memory_ifc_|DFFE_mreq_ff2~q ), .datad(\z80_|memory_ifc_|mwr_wr~q ), .cin(gnd), .combout(\z80_|memory_ifc_|nMREQ_out~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|memory_ifc_|nMREQ_out~0 .lut_mask = 16'hFFCE; +defparam \z80_|memory_ifc_|nMREQ_out~0 .lut_mask = 16'hFFAE; defparam \z80_|memory_ifc_|nMREQ_out~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X43_Y17_N2 +// Location: LCCOMB_X27_Y11_N16 cycloneive_lcell_comb \z80_|memory_ifc_|nMREQ_out~1 ( // Equation(s): -// \z80_|memory_ifc_|nMREQ_out~1_combout = (!\z80_|memory_ifc_|wait_mrd~q & (!\z80_|memory_ifc_|nMREQ_out~0_combout & (!\z80_|memory_ifc_|DFFE_mrd_ff3~q & !\z80_|memory_ifc_|nRD_out~0_combout ))) +// \z80_|memory_ifc_|nMREQ_out~1_combout = (!\z80_|memory_ifc_|wait_mrd~q & (!\z80_|memory_ifc_|nRD_out~0_combout & (!\z80_|memory_ifc_|DFFE_mrd_ff3~q & !\z80_|memory_ifc_|nMREQ_out~0_combout ))) .dataa(\z80_|memory_ifc_|wait_mrd~q ), - .datab(\z80_|memory_ifc_|nMREQ_out~0_combout ), + .datab(\z80_|memory_ifc_|nRD_out~0_combout ), .datac(\z80_|memory_ifc_|DFFE_mrd_ff3~q ), - .datad(\z80_|memory_ifc_|nRD_out~0_combout ), + .datad(\z80_|memory_ifc_|nMREQ_out~0_combout ), .cin(gnd), .combout(\z80_|memory_ifc_|nMREQ_out~1_combout ), .cout()); @@ -53593,7 +53360,7 @@ defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl .cl defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N0 +// Location: LCCOMB_X3_Y23_N28 cycloneive_lcell_comb \ula_|i2c_loader_|state.Idle~feeder ( // Equation(s): // \ula_|i2c_loader_|state.Idle~feeder_combout = VCC @@ -53610,7 +53377,7 @@ defparam \ula_|i2c_loader_|state.Idle~feeder .lut_mask = 16'hFFFF; defparam \ula_|i2c_loader_|state.Idle~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X4_Y24_N0 +// Location: LCCOMB_X1_Y24_N22 cycloneive_lcell_comb \ula_|i2c_loader_|divider[0]~15 ( // Equation(s): // \ula_|i2c_loader_|divider[0]~15_combout = !\ula_|i2c_loader_|divider [0] @@ -53627,7 +53394,7 @@ defparam \ula_|i2c_loader_|divider[0]~15 .lut_mask = 16'h0F0F; defparam \ula_|i2c_loader_|divider[0]~15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X4_Y24_N1 +// Location: FF_X1_Y24_N23 dffeas \ula_|i2c_loader_|divider[0] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[0]~15_combout ), @@ -53646,14 +53413,14 @@ defparam \ula_|i2c_loader_|divider[0] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X4_Y24_N10 +// Location: LCCOMB_X1_Y24_N0 cycloneive_lcell_comb \ula_|i2c_loader_|divider[1]~5 ( // Equation(s): -// \ula_|i2c_loader_|divider[1]~5_combout = (\ula_|i2c_loader_|divider [1] & (\ula_|i2c_loader_|divider [0] $ (VCC))) # (!\ula_|i2c_loader_|divider [1] & (\ula_|i2c_loader_|divider [0] & VCC)) -// \ula_|i2c_loader_|divider[1]~6 = CARRY((\ula_|i2c_loader_|divider [1] & \ula_|i2c_loader_|divider [0])) +// \ula_|i2c_loader_|divider[1]~5_combout = (\ula_|i2c_loader_|divider [0] & (\ula_|i2c_loader_|divider [1] $ (VCC))) # (!\ula_|i2c_loader_|divider [0] & (\ula_|i2c_loader_|divider [1] & VCC)) +// \ula_|i2c_loader_|divider[1]~6 = CARRY((\ula_|i2c_loader_|divider [0] & \ula_|i2c_loader_|divider [1])) - .dataa(\ula_|i2c_loader_|divider [1]), - .datab(\ula_|i2c_loader_|divider [0]), + .dataa(\ula_|i2c_loader_|divider [0]), + .datab(\ula_|i2c_loader_|divider [1]), .datac(gnd), .datad(vcc), .cin(gnd), @@ -53664,7 +53431,7 @@ defparam \ula_|i2c_loader_|divider[1]~5 .lut_mask = 16'h6688; defparam \ula_|i2c_loader_|divider[1]~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X4_Y24_N11 +// Location: FF_X1_Y24_N1 dffeas \ula_|i2c_loader_|divider[1] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[1]~5_combout ), @@ -53683,25 +53450,25 @@ defparam \ula_|i2c_loader_|divider[1] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X4_Y24_N12 +// Location: LCCOMB_X1_Y24_N2 cycloneive_lcell_comb \ula_|i2c_loader_|divider[2]~7 ( // Equation(s): // \ula_|i2c_loader_|divider[2]~7_combout = (\ula_|i2c_loader_|divider [2] & (!\ula_|i2c_loader_|divider[1]~6 )) # (!\ula_|i2c_loader_|divider [2] & ((\ula_|i2c_loader_|divider[1]~6 ) # (GND))) // \ula_|i2c_loader_|divider[2]~8 = CARRY((!\ula_|i2c_loader_|divider[1]~6 ) # (!\ula_|i2c_loader_|divider [2])) - .dataa(\ula_|i2c_loader_|divider [2]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|i2c_loader_|divider [2]), .datac(gnd), .datad(vcc), .cin(\ula_|i2c_loader_|divider[1]~6 ), .combout(\ula_|i2c_loader_|divider[2]~7_combout ), .cout(\ula_|i2c_loader_|divider[2]~8 )); // synopsys translate_off -defparam \ula_|i2c_loader_|divider[2]~7 .lut_mask = 16'h5A5F; +defparam \ula_|i2c_loader_|divider[2]~7 .lut_mask = 16'h3C3F; defparam \ula_|i2c_loader_|divider[2]~7 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X4_Y24_N13 +// Location: FF_X1_Y24_N3 dffeas \ula_|i2c_loader_|divider[2] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[2]~7_combout ), @@ -53720,7 +53487,7 @@ defparam \ula_|i2c_loader_|divider[2] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X4_Y24_N14 +// Location: LCCOMB_X1_Y24_N4 cycloneive_lcell_comb \ula_|i2c_loader_|divider[3]~9 ( // Equation(s): // \ula_|i2c_loader_|divider[3]~9_combout = (\ula_|i2c_loader_|divider [3] & (\ula_|i2c_loader_|divider[2]~8 $ (GND))) # (!\ula_|i2c_loader_|divider [3] & (!\ula_|i2c_loader_|divider[2]~8 & VCC)) @@ -53738,7 +53505,7 @@ defparam \ula_|i2c_loader_|divider[3]~9 .lut_mask = 16'hC30C; defparam \ula_|i2c_loader_|divider[3]~9 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X4_Y24_N15 +// Location: FF_X1_Y24_N5 dffeas \ula_|i2c_loader_|divider[3] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[3]~9_combout ), @@ -53757,25 +53524,42 @@ defparam \ula_|i2c_loader_|divider[3] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X4_Y24_N16 +// Location: LCCOMB_X1_Y24_N12 +cycloneive_lcell_comb \ula_|i2c_loader_|WideAnd0~0 ( +// Equation(s): +// \ula_|i2c_loader_|WideAnd0~0_combout = (((!\ula_|i2c_loader_|divider [2]) # (!\ula_|i2c_loader_|divider [3])) # (!\ula_|i2c_loader_|divider [1])) # (!\ula_|i2c_loader_|divider [0]) + + .dataa(\ula_|i2c_loader_|divider [0]), + .datab(\ula_|i2c_loader_|divider [1]), + .datac(\ula_|i2c_loader_|divider [3]), + .datad(\ula_|i2c_loader_|divider [2]), + .cin(gnd), + .combout(\ula_|i2c_loader_|WideAnd0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|WideAnd0~0 .lut_mask = 16'h7FFF; +defparam \ula_|i2c_loader_|WideAnd0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y24_N6 cycloneive_lcell_comb \ula_|i2c_loader_|divider[4]~11 ( // Equation(s): // \ula_|i2c_loader_|divider[4]~11_combout = (\ula_|i2c_loader_|divider [4] & (!\ula_|i2c_loader_|divider[3]~10 )) # (!\ula_|i2c_loader_|divider [4] & ((\ula_|i2c_loader_|divider[3]~10 ) # (GND))) // \ula_|i2c_loader_|divider[4]~12 = CARRY((!\ula_|i2c_loader_|divider[3]~10 ) # (!\ula_|i2c_loader_|divider [4])) - .dataa(gnd), - .datab(\ula_|i2c_loader_|divider [4]), + .dataa(\ula_|i2c_loader_|divider [4]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\ula_|i2c_loader_|divider[3]~10 ), .combout(\ula_|i2c_loader_|divider[4]~11_combout ), .cout(\ula_|i2c_loader_|divider[4]~12 )); // synopsys translate_off -defparam \ula_|i2c_loader_|divider[4]~11 .lut_mask = 16'h3C3F; +defparam \ula_|i2c_loader_|divider[4]~11 .lut_mask = 16'h5A5F; defparam \ula_|i2c_loader_|divider[4]~11 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X4_Y24_N17 +// Location: FF_X1_Y24_N7 dffeas \ula_|i2c_loader_|divider[4] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[4]~11_combout ), @@ -53794,24 +53578,24 @@ defparam \ula_|i2c_loader_|divider[4] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X4_Y24_N18 +// Location: LCCOMB_X1_Y24_N8 cycloneive_lcell_comb \ula_|i2c_loader_|divider[5]~13 ( // Equation(s): -// \ula_|i2c_loader_|divider[5]~13_combout = \ula_|i2c_loader_|divider[4]~12 $ (!\ula_|i2c_loader_|divider [5]) +// \ula_|i2c_loader_|divider[5]~13_combout = \ula_|i2c_loader_|divider [5] $ (!\ula_|i2c_loader_|divider[4]~12 ) .dataa(gnd), - .datab(gnd), + .datab(\ula_|i2c_loader_|divider [5]), .datac(gnd), - .datad(\ula_|i2c_loader_|divider [5]), + .datad(gnd), .cin(\ula_|i2c_loader_|divider[4]~12 ), .combout(\ula_|i2c_loader_|divider[5]~13_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|divider[5]~13 .lut_mask = 16'hF00F; +defparam \ula_|i2c_loader_|divider[5]~13 .lut_mask = 16'hC3C3; defparam \ula_|i2c_loader_|divider[5]~13 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X4_Y24_N19 +// Location: FF_X1_Y24_N9 dffeas \ula_|i2c_loader_|divider[5] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[5]~13_combout ), @@ -53830,41 +53614,24 @@ defparam \ula_|i2c_loader_|divider[5] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X4_Y24_N22 -cycloneive_lcell_comb \ula_|i2c_loader_|WideAnd0~0 ( -// Equation(s): -// \ula_|i2c_loader_|WideAnd0~0_combout = (((!\ula_|i2c_loader_|divider [2]) # (!\ula_|i2c_loader_|divider [3])) # (!\ula_|i2c_loader_|divider [0])) # (!\ula_|i2c_loader_|divider [1]) - - .dataa(\ula_|i2c_loader_|divider [1]), - .datab(\ula_|i2c_loader_|divider [0]), - .datac(\ula_|i2c_loader_|divider [3]), - .datad(\ula_|i2c_loader_|divider [2]), - .cin(gnd), - .combout(\ula_|i2c_loader_|WideAnd0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|WideAnd0~0 .lut_mask = 16'h7FFF; -defparam \ula_|i2c_loader_|WideAnd0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y24_N8 +// Location: LCCOMB_X1_Y24_N30 cycloneive_lcell_comb \ula_|i2c_loader_|WideAnd0 ( // Equation(s): -// \ula_|i2c_loader_|WideAnd0~combout = ((\ula_|i2c_loader_|WideAnd0~0_combout ) # (!\ula_|i2c_loader_|divider [4])) # (!\ula_|i2c_loader_|divider [5]) +// \ula_|i2c_loader_|WideAnd0~combout = (\ula_|i2c_loader_|WideAnd0~0_combout ) # ((!\ula_|i2c_loader_|divider [4]) # (!\ula_|i2c_loader_|divider [5])) - .dataa(gnd), - .datab(\ula_|i2c_loader_|divider [5]), - .datac(\ula_|i2c_loader_|WideAnd0~0_combout ), + .dataa(\ula_|i2c_loader_|WideAnd0~0_combout ), + .datab(gnd), + .datac(\ula_|i2c_loader_|divider [5]), .datad(\ula_|i2c_loader_|divider [4]), .cin(gnd), .combout(\ula_|i2c_loader_|WideAnd0~combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|WideAnd0 .lut_mask = 16'hF3FF; +defparam \ula_|i2c_loader_|WideAnd0 .lut_mask = 16'hAFFF; defparam \ula_|i2c_loader_|WideAnd0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X1_Y23_N1 +// Location: FF_X3_Y23_N29 dffeas \ula_|i2c_loader_|state.Idle ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|state.Idle~feeder_combout ), @@ -53883,7 +53650,7 @@ defparam \ula_|i2c_loader_|state.Idle .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|state.Idle .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N4 +// Location: LCCOMB_X3_Y23_N0 cycloneive_lcell_comb \ula_|i2c_loader_|phase~0 ( // Equation(s): // \ula_|i2c_loader_|phase~0_combout = (!\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|state.Idle~q ) @@ -53900,7 +53667,7 @@ defparam \ula_|i2c_loader_|phase~0 .lut_mask = 16'h0F00; defparam \ula_|i2c_loader_|phase~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X1_Y23_N5 +// Location: FF_X3_Y23_N1 dffeas \ula_|i2c_loader_|phase[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|phase~0_combout ), @@ -53919,7 +53686,7 @@ defparam \ula_|i2c_loader_|phase[0] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|phase[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N14 +// Location: LCCOMB_X3_Y23_N2 cycloneive_lcell_comb \ula_|i2c_loader_|phase~1 ( // Equation(s): // \ula_|i2c_loader_|phase~1_combout = (\ula_|i2c_loader_|state.Idle~q & (\ula_|i2c_loader_|phase [0] $ (\ula_|i2c_loader_|phase [1]))) @@ -53936,7 +53703,7 @@ defparam \ula_|i2c_loader_|phase~1 .lut_mask = 16'h3C00; defparam \ula_|i2c_loader_|phase~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X1_Y23_N15 +// Location: FF_X3_Y23_N3 dffeas \ula_|i2c_loader_|phase[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|phase~1_combout ), @@ -53955,59 +53722,182 @@ defparam \ula_|i2c_loader_|phase[1] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|phase[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y24_N2 +// Location: LCCOMB_X2_Y24_N2 cycloneive_lcell_comb \ula_|i2c_loader_|nbit~5 ( // Equation(s): -// \ula_|i2c_loader_|nbit~5_combout = (!\ula_|i2c_loader_|nbit [0]) # (!\ula_|i2c_loader_|state.Data~q ) +// \ula_|i2c_loader_|nbit~5_combout = (!\ula_|i2c_loader_|state.Data~q ) # (!\ula_|i2c_loader_|nbit [0]) - .dataa(\ula_|i2c_loader_|state.Data~q ), + .dataa(gnd), .datab(gnd), .datac(\ula_|i2c_loader_|nbit [0]), - .datad(gnd), + .datad(\ula_|i2c_loader_|state.Data~q ), .cin(gnd), .combout(\ula_|i2c_loader_|nbit~5_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|nbit~5 .lut_mask = 16'h5F5F; +defparam \ula_|i2c_loader_|nbit~5 .lut_mask = 16'h0FFF; defparam \ula_|i2c_loader_|nbit~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N14 -cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[0]~8 ( +// Location: LCCOMB_X2_Y23_N16 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Idle~0 ( // Equation(s): -// \ula_|i2c_loader_|thisbyte[0]~8_combout = \ula_|i2c_loader_|thisbyte [0] $ (VCC) -// \ula_|i2c_loader_|thisbyte[0]~9 = CARRY(\ula_|i2c_loader_|thisbyte [0]) +// \ula_|i2c_loader_|state.Idle~0_combout = (!\ula_|i2c_loader_|state.Stop~q & (!\ula_|i2c_loader_|state.Ack~q & (!\ula_|i2c_loader_|state.Start~q & !\ula_|i2c_loader_|state.Pause~q ))) - .dataa(gnd), - .datab(\ula_|i2c_loader_|thisbyte [0]), - .datac(gnd), - .datad(vcc), + .dataa(\ula_|i2c_loader_|state.Stop~q ), + .datab(\ula_|i2c_loader_|state.Ack~q ), + .datac(\ula_|i2c_loader_|state.Start~q ), + .datad(\ula_|i2c_loader_|state.Pause~q ), .cin(gnd), - .combout(\ula_|i2c_loader_|thisbyte[0]~8_combout ), - .cout(\ula_|i2c_loader_|thisbyte[0]~9 )); + .combout(\ula_|i2c_loader_|state.Idle~0_combout ), + .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[0]~8 .lut_mask = 16'h33CC; -defparam \ula_|i2c_loader_|thisbyte[0]~8 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|state.Idle~0 .lut_mask = 16'h0001; +defparam \ula_|i2c_loader_|state.Idle~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N8 +// Location: LCCOMB_X1_Y23_N30 cycloneive_lcell_comb \ula_|i2c_loader_|Mux42~0 ( // Equation(s): -// \ula_|i2c_loader_|Mux42~0_combout = (\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|phase [1]) +// \ula_|i2c_loader_|Mux42~0_combout = (\ula_|i2c_loader_|phase [1] & \ula_|i2c_loader_|phase [0]) .dataa(gnd), - .datab(gnd), + .datab(\ula_|i2c_loader_|phase [1]), .datac(\ula_|i2c_loader_|phase [0]), - .datad(\ula_|i2c_loader_|phase [1]), + .datad(gnd), .cin(gnd), .combout(\ula_|i2c_loader_|Mux42~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|Mux42~0 .lut_mask = 16'hF000; +defparam \ula_|i2c_loader_|Mux42~0 .lut_mask = 16'hC0C0; defparam \ula_|i2c_loader_|Mux42~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N28 +// Location: LCCOMB_X2_Y24_N0 +cycloneive_lcell_comb \ula_|i2c_loader_|nbit~6 ( +// Equation(s): +// \ula_|i2c_loader_|nbit~6_combout = (\ula_|i2c_loader_|nbit [1] $ (!\ula_|i2c_loader_|nbit [0])) # (!\ula_|i2c_loader_|state.Data~q ) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|state.Data~q ), + .datac(\ula_|i2c_loader_|nbit [1]), + .datad(\ula_|i2c_loader_|nbit [0]), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbit~6_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit~6 .lut_mask = 16'hF33F; +defparam \ula_|i2c_loader_|nbit~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y24_N1 +dffeas \ula_|i2c_loader_|nbit[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|nbit~6_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2c_loader_|nbit[0]~4_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|nbit [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit[1] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|nbit[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y24_N30 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Done~0 ( +// Equation(s): +// \ula_|i2c_loader_|state.Done~0_combout = (!\ula_|i2c_loader_|nbit [2] & (!\ula_|i2c_loader_|nbit [0] & (\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|nbit [1]))) + + .dataa(\ula_|i2c_loader_|nbit [2]), + .datab(\ula_|i2c_loader_|nbit [0]), + .datac(\ula_|i2c_loader_|state.Data~q ), + .datad(\ula_|i2c_loader_|nbit [1]), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Done~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Done~0 .lut_mask = 16'h0010; +defparam \ula_|i2c_loader_|state.Done~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N18 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Ack~0 ( +// Equation(s): +// \ula_|i2c_loader_|state.Ack~0_combout = ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Done~0_combout ) # (!\ula_|i2c_loader_|state.Idle~0_combout )))) # (!\ula_|i2c_loader_|state.Idle~q ) + + .dataa(\ula_|i2c_loader_|state.Idle~0_combout ), + .datab(\ula_|i2c_loader_|Mux42~0_combout ), + .datac(\ula_|i2c_loader_|state.Done~0_combout ), + .datad(\ula_|i2c_loader_|state.Idle~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Ack~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Ack~0 .lut_mask = 16'hC4FF; +defparam \ula_|i2c_loader_|state.Ack~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N24 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Ack~1 ( +// Equation(s): +// \ula_|i2c_loader_|state.Ack~1_combout = (\ula_|i2c_loader_|WideAnd0~combout & (((\ula_|i2c_loader_|state.Ack~q )))) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|state.Ack~0_combout & (\ula_|i2c_loader_|state.Data~q )) # +// (!\ula_|i2c_loader_|state.Ack~0_combout & ((\ula_|i2c_loader_|state.Ack~q ))))) + + .dataa(\ula_|i2c_loader_|WideAnd0~combout ), + .datab(\ula_|i2c_loader_|state.Data~q ), + .datac(\ula_|i2c_loader_|state.Ack~q ), + .datad(\ula_|i2c_loader_|state.Ack~0_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Ack~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Ack~1 .lut_mask = 16'hE4F0; +defparam \ula_|i2c_loader_|state.Ack~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y23_N25 +dffeas \ula_|i2c_loader_|state.Ack ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|state.Ack~1_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|state.Ack~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Ack .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|state.Ack .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N2 +cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~2 ( +// Equation(s): +// \ula_|i2c_loader_|nbit[0]~2_combout = (\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|phase [0])) # (!\ula_|i2c_loader_|phase [1]))) # (!\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|state.Ack~q )))) + + .dataa(\ula_|i2c_loader_|phase [1]), + .datab(\ula_|i2c_loader_|state.Ack~q ), + .datac(\ula_|i2c_loader_|phase [0]), + .datad(\ula_|i2c_loader_|state.Data~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbit[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit[0]~2 .lut_mask = 16'h5F33; +defparam \ula_|i2c_loader_|nbit[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N26 cycloneive_lcell_comb \ula_|i2c_loader_|nbyte~4 ( // Equation(s): // \ula_|i2c_loader_|nbyte~4_combout = (\ula_|i2c_loader_|state.Start~q ) # ((\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|nbyte [0] $ (!\ula_|i2c_loader_|nbyte [1])))) @@ -54024,14 +53914,14 @@ defparam \ula_|i2c_loader_|nbyte~4 .lut_mask = 16'hFF84; defparam \ula_|i2c_loader_|nbyte~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N26 +// Location: LCCOMB_X1_Y23_N4 cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[0]~7 ( // Equation(s): -// \ula_|i2c_loader_|thisbyte[0]~7_combout = (\ula_|i2c_loader_|phase [1] & \ula_|i2c_loader_|state.Ack~q ) +// \ula_|i2c_loader_|thisbyte[0]~7_combout = (\ula_|i2c_loader_|state.Ack~q & \ula_|i2c_loader_|phase [1]) .dataa(gnd), - .datab(\ula_|i2c_loader_|phase [1]), - .datac(\ula_|i2c_loader_|state.Ack~q ), + .datab(\ula_|i2c_loader_|state.Ack~q ), + .datac(\ula_|i2c_loader_|phase [1]), .datad(gnd), .cin(gnd), .combout(\ula_|i2c_loader_|thisbyte[0]~7_combout ), @@ -54051,13 +53941,13 @@ defparam \I2C_SDAT~input .bus_hold = "false"; defparam \I2C_SDAT~input .simulate_z_as = "z"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N20 +// Location: LCCOMB_X2_Y23_N20 cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~1 ( // Equation(s): -// \ula_|i2c_loader_|nbyte[0]~1_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|nbyte [0]) # ((\ula_|i2c_loader_|nbyte [1])))) # (!\ula_|i2c_loader_|phase [0] & (((\I2C_SDAT~input_o )))) +// \ula_|i2c_loader_|nbyte[0]~1_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|nbyte [1]) # ((\ula_|i2c_loader_|nbyte [0])))) # (!\ula_|i2c_loader_|phase [0] & (((\I2C_SDAT~input_o )))) - .dataa(\ula_|i2c_loader_|nbyte [0]), - .datab(\ula_|i2c_loader_|nbyte [1]), + .dataa(\ula_|i2c_loader_|nbyte [1]), + .datab(\ula_|i2c_loader_|nbyte [0]), .datac(\ula_|i2c_loader_|phase [0]), .datad(\I2C_SDAT~input_o ), .cin(gnd), @@ -54068,7 +53958,7 @@ defparam \ula_|i2c_loader_|nbyte[0]~1 .lut_mask = 16'hEFE0; defparam \ula_|i2c_loader_|nbyte[0]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N18 +// Location: LCCOMB_X2_Y23_N10 cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~2 ( // Equation(s): // \ula_|i2c_loader_|nbyte[0]~2_combout = (\ula_|i2c_loader_|state.Start~q & (\ula_|i2c_loader_|Mux42~0_combout )) # (!\ula_|i2c_loader_|state.Start~q & (((\ula_|i2c_loader_|thisbyte[0]~7_combout & \ula_|i2c_loader_|nbyte[0]~1_combout )))) @@ -54085,24 +53975,24 @@ defparam \ula_|i2c_loader_|nbyte[0]~2 .lut_mask = 16'hD888; defparam \ula_|i2c_loader_|nbyte[0]~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N24 +// Location: LCCOMB_X2_Y23_N8 cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~3 ( // Equation(s): -// \ula_|i2c_loader_|nbyte[0]~3_combout = (!\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|state.Idle~q & \ula_|i2c_loader_|nbyte[0]~2_combout )) +// \ula_|i2c_loader_|nbyte[0]~3_combout = (\ula_|i2c_loader_|state.Idle~q & (!\ula_|i2c_loader_|WideAnd0~combout & \ula_|i2c_loader_|nbyte[0]~2_combout )) .dataa(gnd), - .datab(\ula_|i2c_loader_|WideAnd0~combout ), - .datac(\ula_|i2c_loader_|state.Idle~q ), + .datab(\ula_|i2c_loader_|state.Idle~q ), + .datac(\ula_|i2c_loader_|WideAnd0~combout ), .datad(\ula_|i2c_loader_|nbyte[0]~2_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|nbyte[0]~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|nbyte[0]~3 .lut_mask = 16'h3000; +defparam \ula_|i2c_loader_|nbyte[0]~3 .lut_mask = 16'h0C00; defparam \ula_|i2c_loader_|nbyte[0]~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X1_Y23_N29 +// Location: FF_X2_Y23_N27 dffeas \ula_|i2c_loader_|nbyte[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|nbyte~4_combout ), @@ -54121,632 +54011,41 @@ defparam \ula_|i2c_loader_|nbyte[1] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|nbyte[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N18 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Stop~0 ( -// Equation(s): -// \ula_|i2c_loader_|state.Stop~0_combout = (!\ula_|i2c_loader_|nbyte [0] & (!\ula_|i2c_loader_|nbyte [1] & \ula_|i2c_loader_|state.Ack~q )) - - .dataa(\ula_|i2c_loader_|nbyte [0]), - .datab(\ula_|i2c_loader_|nbyte [1]), - .datac(\ula_|i2c_loader_|state.Ack~q ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Stop~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Stop~0 .lut_mask = 16'h1010; -defparam \ula_|i2c_loader_|state.Stop~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y24_N2 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Stop~1 ( -// Equation(s): -// \ula_|i2c_loader_|state.Stop~1_combout = (\ula_|i2c_loader_|WideAnd0~combout & (((\ula_|i2c_loader_|state.Stop~q )))) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Stop~0_combout ))) # -// (!\ula_|i2c_loader_|Mux42~0_combout & (\ula_|i2c_loader_|state.Stop~q )))) - - .dataa(\ula_|i2c_loader_|WideAnd0~combout ), - .datab(\ula_|i2c_loader_|Mux42~0_combout ), - .datac(\ula_|i2c_loader_|state.Stop~q ), - .datad(\ula_|i2c_loader_|state.Stop~0_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Stop~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Stop~1 .lut_mask = 16'hF4B0; -defparam \ula_|i2c_loader_|state.Stop~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X1_Y24_N3 -dffeas \ula_|i2c_loader_|state.Stop ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|state.Stop~1_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|state.Stop~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Stop .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|state.Stop .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y24_N20 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Idle~0 ( -// Equation(s): -// \ula_|i2c_loader_|state.Idle~0_combout = (!\ula_|i2c_loader_|state.Start~q & (!\ula_|i2c_loader_|state.Stop~q & (!\ula_|i2c_loader_|state.Pause~q & !\ula_|i2c_loader_|state.Ack~q ))) - - .dataa(\ula_|i2c_loader_|state.Start~q ), - .datab(\ula_|i2c_loader_|state.Stop~q ), - .datac(\ula_|i2c_loader_|state.Pause~q ), - .datad(\ula_|i2c_loader_|state.Ack~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Idle~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Idle~0 .lut_mask = 16'h0001; -defparam \ula_|i2c_loader_|state.Idle~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y24_N0 -cycloneive_lcell_comb \ula_|i2c_loader_|nbit~0 ( -// Equation(s): -// \ula_|i2c_loader_|nbit~0_combout = (\ula_|i2c_loader_|nbit [2] $ (((!\ula_|i2c_loader_|nbit [0] & !\ula_|i2c_loader_|nbit [1])))) # (!\ula_|i2c_loader_|state.Data~q ) - - .dataa(\ula_|i2c_loader_|state.Data~q ), - .datab(\ula_|i2c_loader_|nbit [0]), - .datac(\ula_|i2c_loader_|nbit [2]), - .datad(\ula_|i2c_loader_|nbit [1]), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbit~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit~0 .lut_mask = 16'hF5D7; -defparam \ula_|i2c_loader_|nbit~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X3_Y24_N1 -dffeas \ula_|i2c_loader_|nbit[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|nbit~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2c_loader_|nbit[0]~4_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|nbit [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit[2] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|nbit[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y24_N6 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Done~0 ( -// Equation(s): -// \ula_|i2c_loader_|state.Done~0_combout = (!\ula_|i2c_loader_|nbit [1] & (!\ula_|i2c_loader_|nbit [2] & (\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|nbit [0]))) - - .dataa(\ula_|i2c_loader_|nbit [1]), - .datab(\ula_|i2c_loader_|nbit [2]), - .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|nbit [0]), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Done~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Done~0 .lut_mask = 16'h0010; -defparam \ula_|i2c_loader_|state.Done~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N12 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Ack~0 ( -// Equation(s): -// \ula_|i2c_loader_|state.Ack~0_combout = ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Done~0_combout ) # (!\ula_|i2c_loader_|state.Idle~0_combout )))) # (!\ula_|i2c_loader_|state.Idle~q ) - - .dataa(\ula_|i2c_loader_|Mux42~0_combout ), - .datab(\ula_|i2c_loader_|state.Idle~0_combout ), - .datac(\ula_|i2c_loader_|state.Idle~q ), - .datad(\ula_|i2c_loader_|state.Done~0_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Ack~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Ack~0 .lut_mask = 16'hAF2F; -defparam \ula_|i2c_loader_|state.Ack~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N30 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Ack~1 ( -// Equation(s): -// \ula_|i2c_loader_|state.Ack~1_combout = (\ula_|i2c_loader_|state.Ack~0_combout & ((\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|state.Ack~q )) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|state.Data~q ))))) # -// (!\ula_|i2c_loader_|state.Ack~0_combout & (((\ula_|i2c_loader_|state.Ack~q )))) - - .dataa(\ula_|i2c_loader_|state.Ack~0_combout ), - .datab(\ula_|i2c_loader_|WideAnd0~combout ), - .datac(\ula_|i2c_loader_|state.Ack~q ), - .datad(\ula_|i2c_loader_|state.Data~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Ack~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Ack~1 .lut_mask = 16'hF2D0; -defparam \ula_|i2c_loader_|state.Ack~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X2_Y24_N31 -dffeas \ula_|i2c_loader_|state.Ack ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|state.Ack~1_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|state.Ack~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Ack .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|state.Ack .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N30 -cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[1]~5 ( -// Equation(s): -// \ula_|i2c_loader_|nbyte[1]~5_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|nbyte [0]) # ((\ula_|i2c_loader_|nbyte [1])))) # (!\ula_|i2c_loader_|phase [0] & (((\I2C_SDAT~input_o )))) - - .dataa(\ula_|i2c_loader_|nbyte [0]), - .datab(\ula_|i2c_loader_|nbyte [1]), - .datac(\ula_|i2c_loader_|phase [0]), - .datad(\I2C_SDAT~input_o ), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbyte[1]~5_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbyte[1]~5 .lut_mask = 16'hEFE0; -defparam \ula_|i2c_loader_|nbyte[1]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N8 -cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[0]~18 ( -// Equation(s): -// \ula_|i2c_loader_|thisbyte[0]~18_combout = (\ula_|i2c_loader_|phase [1] & (\ula_|i2c_loader_|state.Ack~q & (!\ula_|i2c_loader_|WideAnd0~combout & \ula_|i2c_loader_|nbyte[1]~5_combout ))) - - .dataa(\ula_|i2c_loader_|phase [1]), - .datab(\ula_|i2c_loader_|state.Ack~q ), - .datac(\ula_|i2c_loader_|WideAnd0~combout ), - .datad(\ula_|i2c_loader_|nbyte[1]~5_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|thisbyte[0]~18_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[0]~18 .lut_mask = 16'h0800; -defparam \ula_|i2c_loader_|thisbyte[0]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X2_Y23_N15 -dffeas \ula_|i2c_loader_|thisbyte[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|thisbyte[0]~8_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(!\ula_|i2c_loader_|phase [0]), - .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|thisbyte [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[0] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|thisbyte[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N16 -cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[1]~10 ( -// Equation(s): -// \ula_|i2c_loader_|thisbyte[1]~10_combout = (\ula_|i2c_loader_|thisbyte [1] & (!\ula_|i2c_loader_|thisbyte[0]~9 )) # (!\ula_|i2c_loader_|thisbyte [1] & ((\ula_|i2c_loader_|thisbyte[0]~9 ) # (GND))) -// \ula_|i2c_loader_|thisbyte[1]~11 = CARRY((!\ula_|i2c_loader_|thisbyte[0]~9 ) # (!\ula_|i2c_loader_|thisbyte [1])) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|thisbyte [1]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2c_loader_|thisbyte[0]~9 ), - .combout(\ula_|i2c_loader_|thisbyte[1]~10_combout ), - .cout(\ula_|i2c_loader_|thisbyte[1]~11 )); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[1]~10 .lut_mask = 16'h3C3F; -defparam \ula_|i2c_loader_|thisbyte[1]~10 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X2_Y23_N17 -dffeas \ula_|i2c_loader_|thisbyte[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|thisbyte[1]~10_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(!\ula_|i2c_loader_|phase [0]), - .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|thisbyte [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[1] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|thisbyte[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N18 -cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[2]~12 ( -// Equation(s): -// \ula_|i2c_loader_|thisbyte[2]~12_combout = (\ula_|i2c_loader_|thisbyte [2] & (\ula_|i2c_loader_|thisbyte[1]~11 $ (GND))) # (!\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte[1]~11 & VCC)) -// \ula_|i2c_loader_|thisbyte[2]~13 = CARRY((\ula_|i2c_loader_|thisbyte [2] & !\ula_|i2c_loader_|thisbyte[1]~11 )) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|thisbyte [2]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2c_loader_|thisbyte[1]~11 ), - .combout(\ula_|i2c_loader_|thisbyte[2]~12_combout ), - .cout(\ula_|i2c_loader_|thisbyte[2]~13 )); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[2]~12 .lut_mask = 16'hC30C; -defparam \ula_|i2c_loader_|thisbyte[2]~12 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X2_Y23_N19 -dffeas \ula_|i2c_loader_|thisbyte[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|thisbyte[2]~12_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(!\ula_|i2c_loader_|phase [0]), - .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|thisbyte [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[2] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|thisbyte[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N20 -cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[3]~14 ( -// Equation(s): -// \ula_|i2c_loader_|thisbyte[3]~14_combout = (\ula_|i2c_loader_|thisbyte [3] & (!\ula_|i2c_loader_|thisbyte[2]~13 )) # (!\ula_|i2c_loader_|thisbyte [3] & ((\ula_|i2c_loader_|thisbyte[2]~13 ) # (GND))) -// \ula_|i2c_loader_|thisbyte[3]~15 = CARRY((!\ula_|i2c_loader_|thisbyte[2]~13 ) # (!\ula_|i2c_loader_|thisbyte [3])) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|thisbyte [3]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2c_loader_|thisbyte[2]~13 ), - .combout(\ula_|i2c_loader_|thisbyte[3]~14_combout ), - .cout(\ula_|i2c_loader_|thisbyte[3]~15 )); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[3]~14 .lut_mask = 16'h3C3F; -defparam \ula_|i2c_loader_|thisbyte[3]~14 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X2_Y23_N21 -dffeas \ula_|i2c_loader_|thisbyte[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|thisbyte[3]~14_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(!\ula_|i2c_loader_|phase [0]), - .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|thisbyte [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[3] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|thisbyte[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N2 -cycloneive_lcell_comb \ula_|i2c_loader_|Equal2~0 ( -// Equation(s): -// \ula_|i2c_loader_|Equal2~0_combout = (\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte [1] & (!\ula_|i2c_loader_|thisbyte [0] & !\ula_|i2c_loader_|thisbyte [3]))) - - .dataa(\ula_|i2c_loader_|thisbyte [2]), - .datab(\ula_|i2c_loader_|thisbyte [1]), - .datac(\ula_|i2c_loader_|thisbyte [0]), - .datad(\ula_|i2c_loader_|thisbyte [3]), - .cin(gnd), - .combout(\ula_|i2c_loader_|Equal2~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|Equal2~0 .lut_mask = 16'h0002; -defparam \ula_|i2c_loader_|Equal2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y24_N26 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~0 ( -// Equation(s): -// \ula_|i2c_loader_|state.Pause~0_combout = (\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|phase [0])) # (!\ula_|i2c_loader_|phase [1]))) # (!\ula_|i2c_loader_|state.Data~q & (((\ula_|i2c_loader_|state.Stop~q )))) - - .dataa(\ula_|i2c_loader_|phase [1]), - .datab(\ula_|i2c_loader_|state.Stop~q ), - .datac(\ula_|i2c_loader_|phase [0]), - .datad(\ula_|i2c_loader_|state.Data~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Pause~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Pause~0 .lut_mask = 16'h5FCC; -defparam \ula_|i2c_loader_|state.Pause~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N22 -cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[4]~16 ( -// Equation(s): -// \ula_|i2c_loader_|thisbyte[4]~16_combout = \ula_|i2c_loader_|thisbyte [4] $ (!\ula_|i2c_loader_|thisbyte[3]~15 ) - - .dataa(\ula_|i2c_loader_|thisbyte [4]), - .datab(gnd), - .datac(gnd), - .datad(gnd), - .cin(\ula_|i2c_loader_|thisbyte[3]~15 ), - .combout(\ula_|i2c_loader_|thisbyte[4]~16_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[4]~16 .lut_mask = 16'hA5A5; -defparam \ula_|i2c_loader_|thisbyte[4]~16 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X2_Y23_N23 -dffeas \ula_|i2c_loader_|thisbyte[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|thisbyte[4]~16_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(!\ula_|i2c_loader_|phase [0]), - .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|thisbyte [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[4] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|thisbyte[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N20 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~1 ( -// Equation(s): -// \ula_|i2c_loader_|state.Pause~1_combout = (\ula_|i2c_loader_|state.Pause~0_combout & ((!\ula_|i2c_loader_|thisbyte [4]) # (!\ula_|i2c_loader_|Equal2~0_combout ))) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|Equal2~0_combout ), - .datac(\ula_|i2c_loader_|state.Pause~0_combout ), - .datad(\ula_|i2c_loader_|thisbyte [4]), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Pause~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Pause~1 .lut_mask = 16'h30F0; -defparam \ula_|i2c_loader_|state.Pause~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y24_N24 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Done~2 ( -// Equation(s): -// \ula_|i2c_loader_|state.Done~2_combout = (\ula_|i2c_loader_|scl_out~0_combout & (((\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|state.Done~1_combout )) # (!\ula_|i2c_loader_|state.Pause~q ))) # (!\ula_|i2c_loader_|scl_out~0_combout & -// (\ula_|i2c_loader_|state.Data~q & ((!\ula_|i2c_loader_|state.Done~1_combout )))) - - .dataa(\ula_|i2c_loader_|scl_out~0_combout ), - .datab(\ula_|i2c_loader_|state.Data~q ), - .datac(\ula_|i2c_loader_|state.Pause~q ), - .datad(\ula_|i2c_loader_|state.Done~1_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Done~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Done~2 .lut_mask = 16'h0ACE; -defparam \ula_|i2c_loader_|state.Done~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y24_N18 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~2 ( -// Equation(s): -// \ula_|i2c_loader_|state.Pause~2_combout = ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Start~q ) # (!\ula_|i2c_loader_|state.Done~2_combout )))) # (!\ula_|i2c_loader_|state.Idle~q ) - - .dataa(\ula_|i2c_loader_|state.Done~2_combout ), - .datab(\ula_|i2c_loader_|Mux42~0_combout ), - .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|state.Idle~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Pause~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Pause~2 .lut_mask = 16'hC4FF; -defparam \ula_|i2c_loader_|state.Pause~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y24_N22 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~3 ( -// Equation(s): -// \ula_|i2c_loader_|state.Pause~3_combout = (\ula_|i2c_loader_|WideAnd0~combout & (((\ula_|i2c_loader_|state.Pause~q )))) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|state.Pause~2_combout & (\ula_|i2c_loader_|state.Pause~1_combout )) # -// (!\ula_|i2c_loader_|state.Pause~2_combout & ((\ula_|i2c_loader_|state.Pause~q ))))) - - .dataa(\ula_|i2c_loader_|state.Pause~1_combout ), - .datab(\ula_|i2c_loader_|WideAnd0~combout ), - .datac(\ula_|i2c_loader_|state.Pause~q ), - .datad(\ula_|i2c_loader_|state.Pause~2_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Pause~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Pause~3 .lut_mask = 16'hE2F0; -defparam \ula_|i2c_loader_|state.Pause~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X1_Y24_N23 -dffeas \ula_|i2c_loader_|state.Pause ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|state.Pause~3_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|state.Pause~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Pause .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|state.Pause .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y24_N30 -cycloneive_lcell_comb \ula_|i2c_loader_|state~25 ( -// Equation(s): -// \ula_|i2c_loader_|state~25_combout = ((\ula_|i2c_loader_|Mux42~0_combout & (\ula_|i2c_loader_|state.Pause~q & !\ula_|i2c_loader_|state.Start~q )) # (!\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Start~q )))) # -// (!\ula_|i2c_loader_|state.Idle~q ) - - .dataa(\ula_|i2c_loader_|state.Pause~q ), - .datab(\ula_|i2c_loader_|Mux42~0_combout ), - .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|state.Idle~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state~25_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state~25 .lut_mask = 16'h38FF; -defparam \ula_|i2c_loader_|state~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X1_Y24_N31 -dffeas \ula_|i2c_loader_|state.Start ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|state~25_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(!\ula_|i2c_loader_|WideAnd0~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|state.Start~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Start .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|state.Start .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N10 -cycloneive_lcell_comb \ula_|i2c_loader_|nbyte~0 ( -// Equation(s): -// \ula_|i2c_loader_|nbyte~0_combout = (\ula_|i2c_loader_|phase [0] & (!\ula_|i2c_loader_|nbyte [0] & !\ula_|i2c_loader_|state.Start~q )) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|phase [0]), - .datac(\ula_|i2c_loader_|nbyte [0]), - .datad(\ula_|i2c_loader_|state.Start~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbyte~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbyte~0 .lut_mask = 16'h000C; -defparam \ula_|i2c_loader_|nbyte~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X1_Y23_N11 -dffeas \ula_|i2c_loader_|nbyte[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|nbyte~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2c_loader_|nbyte[0]~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|nbyte [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbyte[0] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|nbyte[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N22 +// Location: LCCOMB_X2_Y23_N28 cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~1 ( // Equation(s): -// \ula_|i2c_loader_|nbit[0]~1_combout = (!\ula_|i2c_loader_|nbyte [0] & (!\ula_|i2c_loader_|nbyte [1] & !\ula_|i2c_loader_|state.Data~q )) +// \ula_|i2c_loader_|nbit[0]~1_combout = (!\ula_|i2c_loader_|nbyte [1] & (!\ula_|i2c_loader_|nbyte [0] & !\ula_|i2c_loader_|state.Data~q )) - .dataa(\ula_|i2c_loader_|nbyte [0]), - .datab(gnd), - .datac(\ula_|i2c_loader_|nbyte [1]), - .datad(\ula_|i2c_loader_|state.Data~q ), + .dataa(\ula_|i2c_loader_|nbyte [1]), + .datab(\ula_|i2c_loader_|nbyte [0]), + .datac(\ula_|i2c_loader_|state.Data~q ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2c_loader_|nbit[0]~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|nbit[0]~1 .lut_mask = 16'h0005; +defparam \ula_|i2c_loader_|nbit[0]~1 .lut_mask = 16'h0101; defparam \ula_|i2c_loader_|nbit[0]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N0 -cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~2 ( -// Equation(s): -// \ula_|i2c_loader_|nbit[0]~2_combout = (\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|phase [1])) # (!\ula_|i2c_loader_|phase [0]))) # (!\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|state.Ack~q )))) - - .dataa(\ula_|i2c_loader_|phase [0]), - .datab(\ula_|i2c_loader_|state.Data~q ), - .datac(\ula_|i2c_loader_|state.Ack~q ), - .datad(\ula_|i2c_loader_|phase [1]), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbit[0]~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit[0]~2 .lut_mask = 16'h47CF; -defparam \ula_|i2c_loader_|nbit[0]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N6 +// Location: LCCOMB_X2_Y23_N30 cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~3 ( // Equation(s): -// \ula_|i2c_loader_|nbit[0]~3_combout = (!\ula_|i2c_loader_|state.Start~q & ((\ula_|i2c_loader_|nbit[0]~1_combout ) # ((\ula_|i2c_loader_|nbit[0]~2_combout ) # (\ula_|i2c_loader_|state.Done~0_combout )))) +// \ula_|i2c_loader_|nbit[0]~3_combout = (!\ula_|i2c_loader_|state.Start~q & ((\ula_|i2c_loader_|nbit[0]~2_combout ) # ((\ula_|i2c_loader_|nbit[0]~1_combout ) # (\ula_|i2c_loader_|state.Done~0_combout )))) - .dataa(\ula_|i2c_loader_|nbit[0]~1_combout ), - .datab(\ula_|i2c_loader_|nbit[0]~2_combout ), - .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|state.Done~0_combout ), + .dataa(\ula_|i2c_loader_|nbit[0]~2_combout ), + .datab(\ula_|i2c_loader_|nbit[0]~1_combout ), + .datac(\ula_|i2c_loader_|state.Done~0_combout ), + .datad(\ula_|i2c_loader_|state.Start~q ), .cin(gnd), .combout(\ula_|i2c_loader_|nbit[0]~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|nbit[0]~3 .lut_mask = 16'h0F0E; +defparam \ula_|i2c_loader_|nbit[0]~3 .lut_mask = 16'h00FE; defparam \ula_|i2c_loader_|nbit[0]~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N4 +// Location: LCCOMB_X2_Y23_N0 cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~4 ( // Equation(s): // \ula_|i2c_loader_|nbit[0]~4_combout = (!\ula_|i2c_loader_|nbit[0]~3_combout & (\ula_|i2c_loader_|Mux42~0_combout & (!\ula_|i2c_loader_|WideAnd0~combout & \ula_|i2c_loader_|state.Idle~q ))) @@ -54763,7 +54062,7 @@ defparam \ula_|i2c_loader_|nbit[0]~4 .lut_mask = 16'h0400; defparam \ula_|i2c_loader_|nbit[0]~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y24_N3 +// Location: FF_X2_Y24_N3 dffeas \ula_|i2c_loader_|nbit[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|nbit~5_combout ), @@ -54782,27 +54081,27 @@ defparam \ula_|i2c_loader_|nbit[0] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|nbit[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y24_N12 -cycloneive_lcell_comb \ula_|i2c_loader_|nbit~6 ( +// Location: LCCOMB_X2_Y24_N12 +cycloneive_lcell_comb \ula_|i2c_loader_|nbit~0 ( // Equation(s): -// \ula_|i2c_loader_|nbit~6_combout = (\ula_|i2c_loader_|nbit [1] $ (!\ula_|i2c_loader_|nbit [0])) # (!\ula_|i2c_loader_|state.Data~q ) +// \ula_|i2c_loader_|nbit~0_combout = (\ula_|i2c_loader_|nbit [2] $ (((!\ula_|i2c_loader_|nbit [0] & !\ula_|i2c_loader_|nbit [1])))) # (!\ula_|i2c_loader_|state.Data~q ) .dataa(\ula_|i2c_loader_|state.Data~q ), - .datab(gnd), - .datac(\ula_|i2c_loader_|nbit [1]), - .datad(\ula_|i2c_loader_|nbit [0]), + .datab(\ula_|i2c_loader_|nbit [0]), + .datac(\ula_|i2c_loader_|nbit [2]), + .datad(\ula_|i2c_loader_|nbit [1]), .cin(gnd), - .combout(\ula_|i2c_loader_|nbit~6_combout ), + .combout(\ula_|i2c_loader_|nbit~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|nbit~6 .lut_mask = 16'hF55F; -defparam \ula_|i2c_loader_|nbit~6 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|nbit~0 .lut_mask = 16'hF5D7; +defparam \ula_|i2c_loader_|nbit~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y24_N13 -dffeas \ula_|i2c_loader_|nbit[1] ( +// Location: FF_X2_Y24_N13 +dffeas \ula_|i2c_loader_|nbit[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|nbit~6_combout ), + .d(\ula_|i2c_loader_|nbit~0_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -54811,22 +54110,22 @@ dffeas \ula_|i2c_loader_|nbit[1] ( .ena(\ula_|i2c_loader_|nbit[0]~4_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\ula_|i2c_loader_|nbit [1]), + .q(\ula_|i2c_loader_|nbit [2]), .prn(vcc)); // synopsys translate_off -defparam \ula_|i2c_loader_|nbit[1] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|nbit[1] .power_up = "low"; +defparam \ula_|i2c_loader_|nbit[2] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|nbit[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y24_N16 +// Location: LCCOMB_X2_Y24_N28 cycloneive_lcell_comb \ula_|i2c_loader_|state.Done~1 ( // Equation(s): -// \ula_|i2c_loader_|state.Done~1_combout = (!\ula_|i2c_loader_|nbit [1] & (!\ula_|i2c_loader_|nbit [2] & !\ula_|i2c_loader_|nbit [0])) +// \ula_|i2c_loader_|state.Done~1_combout = (!\ula_|i2c_loader_|nbit [2] & (!\ula_|i2c_loader_|nbit [0] & !\ula_|i2c_loader_|nbit [1])) - .dataa(\ula_|i2c_loader_|nbit [1]), - .datab(\ula_|i2c_loader_|nbit [2]), + .dataa(\ula_|i2c_loader_|nbit [2]), + .datab(\ula_|i2c_loader_|nbit [0]), .datac(gnd), - .datad(\ula_|i2c_loader_|nbit [0]), + .datad(\ula_|i2c_loader_|nbit [1]), .cin(gnd), .combout(\ula_|i2c_loader_|state.Done~1_combout ), .cout()); @@ -54835,75 +54134,75 @@ defparam \ula_|i2c_loader_|state.Done~1 .lut_mask = 16'h0011; defparam \ula_|i2c_loader_|state.Done~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N6 +// Location: LCCOMB_X1_Y23_N18 cycloneive_lcell_comb \ula_|i2c_loader_|state~27 ( // Equation(s): // \ula_|i2c_loader_|state~27_combout = ((!\ula_|i2c_loader_|state.Done~1_combout ) # (!\ula_|i2c_loader_|phase [0])) # (!\ula_|i2c_loader_|phase [1]) .dataa(\ula_|i2c_loader_|phase [1]), - .datab(gnd), - .datac(\ula_|i2c_loader_|phase [0]), - .datad(\ula_|i2c_loader_|state.Done~1_combout ), + .datab(\ula_|i2c_loader_|phase [0]), + .datac(\ula_|i2c_loader_|state.Done~1_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2c_loader_|state~27_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|state~27 .lut_mask = 16'h5FFF; +defparam \ula_|i2c_loader_|state~27 .lut_mask = 16'h7F7F; defparam \ula_|i2c_loader_|state~27 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N28 +// Location: LCCOMB_X2_Y23_N14 cycloneive_lcell_comb \ula_|i2c_loader_|state~24 ( // Equation(s): // \ula_|i2c_loader_|state~24_combout = (\ula_|i2c_loader_|state.Ack~q & ((\ula_|i2c_loader_|nbyte [0]) # (\ula_|i2c_loader_|nbyte [1]))) - .dataa(\ula_|i2c_loader_|nbyte [0]), - .datab(\ula_|i2c_loader_|nbyte [1]), - .datac(\ula_|i2c_loader_|state.Ack~q ), - .datad(gnd), + .dataa(gnd), + .datab(\ula_|i2c_loader_|nbyte [0]), + .datac(\ula_|i2c_loader_|nbyte [1]), + .datad(\ula_|i2c_loader_|state.Ack~q ), .cin(gnd), .combout(\ula_|i2c_loader_|state~24_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|state~24 .lut_mask = 16'hE0E0; +defparam \ula_|i2c_loader_|state~24 .lut_mask = 16'hFC00; defparam \ula_|i2c_loader_|state~24 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N16 +// Location: LCCOMB_X2_Y23_N2 cycloneive_lcell_comb \ula_|i2c_loader_|state~26 ( // Equation(s): -// \ula_|i2c_loader_|state~26_combout = (\ula_|i2c_loader_|phase [1] & (\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|state~24_combout )) +// \ula_|i2c_loader_|state~26_combout = (\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|state~24_combout & \ula_|i2c_loader_|phase [1])) - .dataa(\ula_|i2c_loader_|phase [1]), - .datab(gnd), - .datac(\ula_|i2c_loader_|phase [0]), - .datad(\ula_|i2c_loader_|state~24_combout ), + .dataa(gnd), + .datab(\ula_|i2c_loader_|phase [0]), + .datac(\ula_|i2c_loader_|state~24_combout ), + .datad(\ula_|i2c_loader_|phase [1]), .cin(gnd), .combout(\ula_|i2c_loader_|state~26_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|state~26 .lut_mask = 16'hA000; +defparam \ula_|i2c_loader_|state~26 .lut_mask = 16'hC000; defparam \ula_|i2c_loader_|state~26 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N28 +// Location: LCCOMB_X1_Y23_N0 cycloneive_lcell_comb \ula_|i2c_loader_|state.Data~0 ( // Equation(s): // \ula_|i2c_loader_|state.Data~0_combout = (\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|state~27_combout )) # (!\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|state~26_combout ))) - .dataa(\ula_|i2c_loader_|state~27_combout ), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|i2c_loader_|state~27_combout ), .datac(\ula_|i2c_loader_|state.Data~q ), .datad(\ula_|i2c_loader_|state~26_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|state.Data~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|state.Data~0 .lut_mask = 16'hAFA0; +defparam \ula_|i2c_loader_|state.Data~0 .lut_mask = 16'hCFC0; defparam \ula_|i2c_loader_|state.Data~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X1_Y24_N29 +// Location: FF_X1_Y23_N1 dffeas \ula_|i2c_loader_|state.Data ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|state.Data~0_combout ), @@ -54922,24 +54221,492 @@ defparam \ula_|i2c_loader_|state.Data .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|state.Data .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N12 -cycloneive_lcell_comb \ula_|i2c_loader_|scl_out~0 ( +// Location: LCCOMB_X1_Y23_N16 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Done~2 ( // Equation(s): -// \ula_|i2c_loader_|scl_out~0_combout = (!\ula_|i2c_loader_|state.Data~q & (!\ula_|i2c_loader_|state.Ack~q & !\ula_|i2c_loader_|state.Stop~q )) +// \ula_|i2c_loader_|state.Done~2_combout = (\ula_|i2c_loader_|scl_out~0_combout & (((\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|state.Done~1_combout )) # (!\ula_|i2c_loader_|state.Pause~q ))) # (!\ula_|i2c_loader_|scl_out~0_combout & +// (\ula_|i2c_loader_|state.Data~q & (!\ula_|i2c_loader_|state.Done~1_combout ))) + + .dataa(\ula_|i2c_loader_|scl_out~0_combout ), + .datab(\ula_|i2c_loader_|state.Data~q ), + .datac(\ula_|i2c_loader_|state.Done~1_combout ), + .datad(\ula_|i2c_loader_|state.Pause~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Done~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Done~2 .lut_mask = 16'h0CAE; +defparam \ula_|i2c_loader_|state.Done~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N10 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~1 ( +// Equation(s): +// \ula_|i2c_loader_|state.Pause~1_combout = ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Start~q ) # (!\ula_|i2c_loader_|state.Done~2_combout )))) # (!\ula_|i2c_loader_|state.Idle~q ) + + .dataa(\ula_|i2c_loader_|state.Start~q ), + .datab(\ula_|i2c_loader_|state.Done~2_combout ), + .datac(\ula_|i2c_loader_|Mux42~0_combout ), + .datad(\ula_|i2c_loader_|state.Idle~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Pause~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Pause~1 .lut_mask = 16'hB0FF; +defparam \ula_|i2c_loader_|state.Pause~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X5_Y23_N18 +cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[0]~8 ( +// Equation(s): +// \ula_|i2c_loader_|thisbyte[0]~8_combout = \ula_|i2c_loader_|thisbyte [0] $ (VCC) +// \ula_|i2c_loader_|thisbyte[0]~9 = CARRY(\ula_|i2c_loader_|thisbyte [0]) .dataa(gnd), + .datab(\ula_|i2c_loader_|thisbyte [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\ula_|i2c_loader_|thisbyte[0]~8_combout ), + .cout(\ula_|i2c_loader_|thisbyte[0]~9 )); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[0]~8 .lut_mask = 16'h33CC; +defparam \ula_|i2c_loader_|thisbyte[0]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X5_Y23_N28 +cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[1]~5 ( +// Equation(s): +// \ula_|i2c_loader_|nbyte[1]~5_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|nbyte [0]) # ((\ula_|i2c_loader_|nbyte [1])))) # (!\ula_|i2c_loader_|phase [0] & (((\I2C_SDAT~input_o )))) + + .dataa(\ula_|i2c_loader_|phase [0]), + .datab(\ula_|i2c_loader_|nbyte [0]), + .datac(\ula_|i2c_loader_|nbyte [1]), + .datad(\I2C_SDAT~input_o ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbyte[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbyte[1]~5 .lut_mask = 16'hFDA8; +defparam \ula_|i2c_loader_|nbyte[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X5_Y23_N16 +cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[0]~18 ( +// Equation(s): +// \ula_|i2c_loader_|thisbyte[0]~18_combout = (\ula_|i2c_loader_|state.Ack~q & (\ula_|i2c_loader_|phase [1] & (!\ula_|i2c_loader_|WideAnd0~combout & \ula_|i2c_loader_|nbyte[1]~5_combout ))) + + .dataa(\ula_|i2c_loader_|state.Ack~q ), + .datab(\ula_|i2c_loader_|phase [1]), + .datac(\ula_|i2c_loader_|WideAnd0~combout ), + .datad(\ula_|i2c_loader_|nbyte[1]~5_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|thisbyte[0]~18_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[0]~18 .lut_mask = 16'h0800; +defparam \ula_|i2c_loader_|thisbyte[0]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X5_Y23_N19 +dffeas \ula_|i2c_loader_|thisbyte[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|thisbyte[0]~8_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\ula_|i2c_loader_|phase [0]), + .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|thisbyte [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[0] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|thisbyte[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X5_Y23_N20 +cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[1]~10 ( +// Equation(s): +// \ula_|i2c_loader_|thisbyte[1]~10_combout = (\ula_|i2c_loader_|thisbyte [1] & (!\ula_|i2c_loader_|thisbyte[0]~9 )) # (!\ula_|i2c_loader_|thisbyte [1] & ((\ula_|i2c_loader_|thisbyte[0]~9 ) # (GND))) +// \ula_|i2c_loader_|thisbyte[1]~11 = CARRY((!\ula_|i2c_loader_|thisbyte[0]~9 ) # (!\ula_|i2c_loader_|thisbyte [1])) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|thisbyte [1]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2c_loader_|thisbyte[0]~9 ), + .combout(\ula_|i2c_loader_|thisbyte[1]~10_combout ), + .cout(\ula_|i2c_loader_|thisbyte[1]~11 )); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[1]~10 .lut_mask = 16'h3C3F; +defparam \ula_|i2c_loader_|thisbyte[1]~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X5_Y23_N21 +dffeas \ula_|i2c_loader_|thisbyte[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|thisbyte[1]~10_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\ula_|i2c_loader_|phase [0]), + .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|thisbyte [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[1] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|thisbyte[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X5_Y23_N22 +cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[2]~12 ( +// Equation(s): +// \ula_|i2c_loader_|thisbyte[2]~12_combout = (\ula_|i2c_loader_|thisbyte [2] & (\ula_|i2c_loader_|thisbyte[1]~11 $ (GND))) # (!\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte[1]~11 & VCC)) +// \ula_|i2c_loader_|thisbyte[2]~13 = CARRY((\ula_|i2c_loader_|thisbyte [2] & !\ula_|i2c_loader_|thisbyte[1]~11 )) + + .dataa(\ula_|i2c_loader_|thisbyte [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2c_loader_|thisbyte[1]~11 ), + .combout(\ula_|i2c_loader_|thisbyte[2]~12_combout ), + .cout(\ula_|i2c_loader_|thisbyte[2]~13 )); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[2]~12 .lut_mask = 16'hA50A; +defparam \ula_|i2c_loader_|thisbyte[2]~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X5_Y23_N23 +dffeas \ula_|i2c_loader_|thisbyte[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|thisbyte[2]~12_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\ula_|i2c_loader_|phase [0]), + .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|thisbyte [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[2] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|thisbyte[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X5_Y23_N24 +cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[3]~14 ( +// Equation(s): +// \ula_|i2c_loader_|thisbyte[3]~14_combout = (\ula_|i2c_loader_|thisbyte [3] & (!\ula_|i2c_loader_|thisbyte[2]~13 )) # (!\ula_|i2c_loader_|thisbyte [3] & ((\ula_|i2c_loader_|thisbyte[2]~13 ) # (GND))) +// \ula_|i2c_loader_|thisbyte[3]~15 = CARRY((!\ula_|i2c_loader_|thisbyte[2]~13 ) # (!\ula_|i2c_loader_|thisbyte [3])) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|thisbyte [3]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2c_loader_|thisbyte[2]~13 ), + .combout(\ula_|i2c_loader_|thisbyte[3]~14_combout ), + .cout(\ula_|i2c_loader_|thisbyte[3]~15 )); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[3]~14 .lut_mask = 16'h3C3F; +defparam \ula_|i2c_loader_|thisbyte[3]~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X5_Y23_N25 +dffeas \ula_|i2c_loader_|thisbyte[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|thisbyte[3]~14_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\ula_|i2c_loader_|phase [0]), + .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|thisbyte [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[3] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|thisbyte[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y23_N4 +cycloneive_lcell_comb \ula_|i2c_loader_|Equal2~0 ( +// Equation(s): +// \ula_|i2c_loader_|Equal2~0_combout = (\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte [3] & (!\ula_|i2c_loader_|thisbyte [1] & !\ula_|i2c_loader_|thisbyte [0]))) + + .dataa(\ula_|i2c_loader_|thisbyte [2]), + .datab(\ula_|i2c_loader_|thisbyte [3]), + .datac(\ula_|i2c_loader_|thisbyte [1]), + .datad(\ula_|i2c_loader_|thisbyte [0]), + .cin(gnd), + .combout(\ula_|i2c_loader_|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|Equal2~0 .lut_mask = 16'h0002; +defparam \ula_|i2c_loader_|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X5_Y23_N26 +cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[4]~16 ( +// Equation(s): +// \ula_|i2c_loader_|thisbyte[4]~16_combout = \ula_|i2c_loader_|thisbyte [4] $ (!\ula_|i2c_loader_|thisbyte[3]~15 ) + + .dataa(\ula_|i2c_loader_|thisbyte [4]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\ula_|i2c_loader_|thisbyte[3]~15 ), + .combout(\ula_|i2c_loader_|thisbyte[4]~16_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[4]~16 .lut_mask = 16'hA5A5; +defparam \ula_|i2c_loader_|thisbyte[4]~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X5_Y23_N27 +dffeas \ula_|i2c_loader_|thisbyte[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|thisbyte[4]~16_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\ula_|i2c_loader_|phase [0]), + .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|thisbyte [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[4] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|thisbyte[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y23_N30 +cycloneive_lcell_comb \ula_|i2c_loader_|Equal2~1 ( +// Equation(s): +// \ula_|i2c_loader_|Equal2~1_combout = (\ula_|i2c_loader_|Equal2~0_combout & \ula_|i2c_loader_|thisbyte [4]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|i2c_loader_|Equal2~0_combout ), + .datad(\ula_|i2c_loader_|thisbyte [4]), + .cin(gnd), + .combout(\ula_|i2c_loader_|Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|Equal2~1 .lut_mask = 16'hF000; +defparam \ula_|i2c_loader_|Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N22 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~0 ( +// Equation(s): +// \ula_|i2c_loader_|state.Pause~0_combout = (!\ula_|i2c_loader_|Equal2~1_combout & ((\ula_|i2c_loader_|state.Data~q & ((!\ula_|i2c_loader_|Mux42~0_combout ))) # (!\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|state.Stop~q )))) + + .dataa(\ula_|i2c_loader_|state.Stop~q ), + .datab(\ula_|i2c_loader_|Mux42~0_combout ), + .datac(\ula_|i2c_loader_|state.Data~q ), + .datad(\ula_|i2c_loader_|Equal2~1_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Pause~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Pause~0 .lut_mask = 16'h003A; +defparam \ula_|i2c_loader_|state.Pause~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N24 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~2 ( +// Equation(s): +// \ula_|i2c_loader_|state.Pause~2_combout = (\ula_|i2c_loader_|state.Pause~1_combout & ((\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|state.Pause~q )) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|state.Pause~0_combout ))))) # +// (!\ula_|i2c_loader_|state.Pause~1_combout & (((\ula_|i2c_loader_|state.Pause~q )))) + + .dataa(\ula_|i2c_loader_|state.Pause~1_combout ), + .datab(\ula_|i2c_loader_|WideAnd0~combout ), + .datac(\ula_|i2c_loader_|state.Pause~q ), + .datad(\ula_|i2c_loader_|state.Pause~0_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Pause~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Pause~2 .lut_mask = 16'hF2D0; +defparam \ula_|i2c_loader_|state.Pause~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X1_Y23_N25 +dffeas \ula_|i2c_loader_|state.Pause ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|state.Pause~2_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|state.Pause~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Pause .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|state.Pause .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y23_N26 +cycloneive_lcell_comb \ula_|i2c_loader_|state~25 ( +// Equation(s): +// \ula_|i2c_loader_|state~25_combout = ((\ula_|i2c_loader_|Mux42~0_combout & (\ula_|i2c_loader_|state.Pause~q & !\ula_|i2c_loader_|state.Start~q )) # (!\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Start~q )))) # +// (!\ula_|i2c_loader_|state.Idle~q ) + + .dataa(\ula_|i2c_loader_|state.Pause~q ), + .datab(\ula_|i2c_loader_|Mux42~0_combout ), + .datac(\ula_|i2c_loader_|state.Start~q ), + .datad(\ula_|i2c_loader_|state.Idle~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state~25_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state~25 .lut_mask = 16'h38FF; +defparam \ula_|i2c_loader_|state~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X3_Y23_N27 +dffeas \ula_|i2c_loader_|state.Start ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|state~25_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(!\ula_|i2c_loader_|WideAnd0~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|state.Start~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Start .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|state.Start .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N4 +cycloneive_lcell_comb \ula_|i2c_loader_|nbyte~0 ( +// Equation(s): +// \ula_|i2c_loader_|nbyte~0_combout = (\ula_|i2c_loader_|phase [0] & (!\ula_|i2c_loader_|nbyte [0] & !\ula_|i2c_loader_|state.Start~q )) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|phase [0]), + .datac(\ula_|i2c_loader_|nbyte [0]), + .datad(\ula_|i2c_loader_|state.Start~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbyte~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbyte~0 .lut_mask = 16'h000C; +defparam \ula_|i2c_loader_|nbyte~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y23_N5 +dffeas \ula_|i2c_loader_|nbyte[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|nbyte~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2c_loader_|nbyte[0]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|nbyte [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbyte[0] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|nbyte[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N12 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Stop~0 ( +// Equation(s): +// \ula_|i2c_loader_|state.Stop~0_combout = (!\ula_|i2c_loader_|nbyte [0] & (!\ula_|i2c_loader_|nbyte [1] & \ula_|i2c_loader_|state.Ack~q )) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|nbyte [0]), + .datac(\ula_|i2c_loader_|nbyte [1]), + .datad(\ula_|i2c_loader_|state.Ack~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Stop~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Stop~0 .lut_mask = 16'h0300; +defparam \ula_|i2c_loader_|state.Stop~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N6 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Stop~1 ( +// Equation(s): +// \ula_|i2c_loader_|state.Stop~1_combout = (\ula_|i2c_loader_|WideAnd0~combout & (((\ula_|i2c_loader_|state.Stop~q )))) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|Mux42~0_combout & (\ula_|i2c_loader_|state.Stop~0_combout )) # +// (!\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Stop~q ))))) + + .dataa(\ula_|i2c_loader_|state.Stop~0_combout ), + .datab(\ula_|i2c_loader_|WideAnd0~combout ), + .datac(\ula_|i2c_loader_|state.Stop~q ), + .datad(\ula_|i2c_loader_|Mux42~0_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Stop~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Stop~1 .lut_mask = 16'hE2F0; +defparam \ula_|i2c_loader_|state.Stop~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y23_N7 +dffeas \ula_|i2c_loader_|state.Stop ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|state.Stop~1_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|state.Stop~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Stop .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|state.Stop .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N22 +cycloneive_lcell_comb \ula_|i2c_loader_|scl_out~0 ( +// Equation(s): +// \ula_|i2c_loader_|scl_out~0_combout = (!\ula_|i2c_loader_|state.Stop~q & (!\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|state.Ack~q )) + + .dataa(\ula_|i2c_loader_|state.Stop~q ), .datab(\ula_|i2c_loader_|state.Data~q ), - .datac(\ula_|i2c_loader_|state.Ack~q ), - .datad(\ula_|i2c_loader_|state.Stop~q ), + .datac(gnd), + .datad(\ula_|i2c_loader_|state.Ack~q ), .cin(gnd), .combout(\ula_|i2c_loader_|scl_out~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|scl_out~0 .lut_mask = 16'h0003; +defparam \ula_|i2c_loader_|scl_out~0 .lut_mask = 16'h0011; defparam \ula_|i2c_loader_|scl_out~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X1_Y23_N13 +// Location: FF_X1_Y23_N7 dffeas \ula_|i2c_loader_|scl_out~_Duplicate_1 ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|scl_out~2_combout ), @@ -54958,7 +54725,7 @@ defparam \ula_|i2c_loader_|scl_out~_Duplicate_1 .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|scl_out~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N16 +// Location: LCCOMB_X1_Y23_N8 cycloneive_lcell_comb \ula_|i2c_loader_|scl_out~1 ( // Equation(s): // \ula_|i2c_loader_|scl_out~1_combout = (\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|state.Start~q $ (((!\ula_|i2c_loader_|scl_out~_Duplicate_1_q ))))) # (!\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|phase [1]) # @@ -54976,20 +54743,20 @@ defparam \ula_|i2c_loader_|scl_out~1 .lut_mask = 16'hBA74; defparam \ula_|i2c_loader_|scl_out~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N12 +// Location: LCCOMB_X1_Y23_N6 cycloneive_lcell_comb \ula_|i2c_loader_|scl_out~2 ( // Equation(s): // \ula_|i2c_loader_|scl_out~2_combout = (\ula_|i2c_loader_|scl_out~1_combout & ((\ula_|i2c_loader_|state.Start~q ))) # (!\ula_|i2c_loader_|scl_out~1_combout & (!\ula_|i2c_loader_|scl_out~0_combout & !\ula_|i2c_loader_|state.Start~q )) .dataa(\ula_|i2c_loader_|scl_out~0_combout ), .datab(\ula_|i2c_loader_|scl_out~1_combout ), - .datac(gnd), - .datad(\ula_|i2c_loader_|state.Start~q ), + .datac(\ula_|i2c_loader_|state.Start~q ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2c_loader_|scl_out~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|scl_out~2 .lut_mask = 16'hCC11; +defparam \ula_|i2c_loader_|scl_out~2 .lut_mask = 16'hC1C1; defparam \ula_|i2c_loader_|scl_out~2 .sum_lutc_input = "datac"; // synopsys translate_on @@ -55012,7 +54779,7 @@ defparam \ula_|i2c_loader_|scl_out .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|scl_out .power_up = "high"; // synopsys translate_on -// Location: FF_X1_Y23_N23 +// Location: FF_X1_Y23_N13 dffeas \ula_|i2c_loader_|sda_out~_Duplicate_1 ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|sda_out~4_combout ), @@ -55031,32 +54798,32 @@ defparam \ula_|i2c_loader_|sda_out~_Duplicate_1 .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|sda_out~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N10 +// Location: LCCOMB_X4_Y23_N10 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~4 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~4_combout = (!\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|state.Start~q ) +// \ula_|i2c_loader_|shiftreg~4_combout = (!\ula_|i2c_loader_|state.Start~q & !\ula_|i2c_loader_|state.Data~q ) - .dataa(gnd), + .dataa(\ula_|i2c_loader_|state.Start~q ), .datab(gnd), .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|state.Start~q ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg~4_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~4 .lut_mask = 16'h000F; +defparam \ula_|i2c_loader_|shiftreg~4 .lut_mask = 16'h0505; defparam \ula_|i2c_loader_|shiftreg~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N0 +// Location: LCCOMB_X4_Y23_N20 cycloneive_lcell_comb \ula_|i2c_loader_|Mux35~0 ( // Equation(s): -// \ula_|i2c_loader_|Mux35~0_combout = (\ula_|i2c_loader_|thisbyte [0] & (\ula_|i2c_loader_|thisbyte [2] & ((!\ula_|i2c_loader_|thisbyte [1]) # (!\ula_|i2c_loader_|thisbyte [3])))) +// \ula_|i2c_loader_|Mux35~0_combout = (\ula_|i2c_loader_|thisbyte [2] & (\ula_|i2c_loader_|thisbyte [0] & ((!\ula_|i2c_loader_|thisbyte [1]) # (!\ula_|i2c_loader_|thisbyte [3])))) - .dataa(\ula_|i2c_loader_|thisbyte [0]), + .dataa(\ula_|i2c_loader_|thisbyte [2]), .datab(\ula_|i2c_loader_|thisbyte [3]), .datac(\ula_|i2c_loader_|thisbyte [1]), - .datad(\ula_|i2c_loader_|thisbyte [2]), + .datad(\ula_|i2c_loader_|thisbyte [0]), .cin(gnd), .combout(\ula_|i2c_loader_|Mux35~0_combout ), .cout()); @@ -55065,135 +54832,186 @@ defparam \ula_|i2c_loader_|Mux35~0 .lut_mask = 16'h2A00; defparam \ula_|i2c_loader_|Mux35~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N30 +// Location: LCCOMB_X5_Y23_N12 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~13 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~13_combout = (!\ula_|i2c_loader_|thisbyte [2] & ((\ula_|i2c_loader_|thisbyte [4] & ((!\ula_|i2c_loader_|thisbyte [0]))) # (!\ula_|i2c_loader_|thisbyte [4] & (!\ula_|i2c_loader_|thisbyte [1] & \ula_|i2c_loader_|thisbyte [0])))) +// \ula_|i2c_loader_|shiftreg~13_combout = (!\ula_|i2c_loader_|thisbyte [2] & \ula_|i2c_loader_|thisbyte [4]) - .dataa(\ula_|i2c_loader_|thisbyte [4]), - .datab(\ula_|i2c_loader_|thisbyte [1]), - .datac(\ula_|i2c_loader_|thisbyte [0]), - .datad(\ula_|i2c_loader_|thisbyte [2]), + .dataa(\ula_|i2c_loader_|thisbyte [2]), + .datab(gnd), + .datac(\ula_|i2c_loader_|thisbyte [4]), + .datad(gnd), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg~13_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~13 .lut_mask = 16'h001A; +defparam \ula_|i2c_loader_|shiftreg~13 .lut_mask = 16'h5050; defparam \ula_|i2c_loader_|shiftreg~13 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N24 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~14 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~14_combout = (\ula_|i2c_loader_|thisbyte [4] & !\ula_|i2c_loader_|thisbyte [2]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2c_loader_|thisbyte [4]), - .datad(\ula_|i2c_loader_|thisbyte [2]), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~14_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~14 .lut_mask = 16'h00F0; -defparam \ula_|i2c_loader_|shiftreg~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N10 +// Location: LCCOMB_X5_Y23_N4 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~15 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~15_combout = (\ula_|i2c_loader_|shiftreg~13_combout ) # ((!\ula_|i2c_loader_|thisbyte [3] & (\ula_|i2c_loader_|thisbyte [0] & !\ula_|i2c_loader_|shiftreg~14_combout ))) +// \ula_|i2c_loader_|shiftreg~15_combout = (\ula_|i2c_loader_|thisbyte [2] & (((!\ula_|i2c_loader_|thisbyte [3])))) # (!\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte [1] & (\ula_|i2c_loader_|thisbyte [4]))) - .dataa(\ula_|i2c_loader_|shiftreg~13_combout ), - .datab(\ula_|i2c_loader_|thisbyte [3]), - .datac(\ula_|i2c_loader_|thisbyte [0]), - .datad(\ula_|i2c_loader_|shiftreg~14_combout ), + .dataa(\ula_|i2c_loader_|thisbyte [2]), + .datab(\ula_|i2c_loader_|thisbyte [1]), + .datac(\ula_|i2c_loader_|thisbyte [4]), + .datad(\ula_|i2c_loader_|thisbyte [3]), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg~15_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~15 .lut_mask = 16'hAABA; +defparam \ula_|i2c_loader_|shiftreg~15 .lut_mask = 16'h10BA; defparam \ula_|i2c_loader_|shiftreg~15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N12 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~24 ( +// Location: LCCOMB_X5_Y23_N10 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~16 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg[0]~24_combout = (!\ula_|i2c_loader_|thisbyte [3] & (!\ula_|i2c_loader_|state.Data~q & \ula_|i2c_loader_|thisbyte [0])) +// \ula_|i2c_loader_|shiftreg~16_combout = (\ula_|i2c_loader_|thisbyte [0] & (((\ula_|i2c_loader_|shiftreg~15_combout )))) # (!\ula_|i2c_loader_|thisbyte [0] & (!\ula_|i2c_loader_|shiftreg~13_combout & (\ula_|i2c_loader_|thisbyte [3]))) + + .dataa(\ula_|i2c_loader_|shiftreg~13_combout ), + .datab(\ula_|i2c_loader_|thisbyte [3]), + .datac(\ula_|i2c_loader_|shiftreg~15_combout ), + .datad(\ula_|i2c_loader_|thisbyte [0]), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~16_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~16 .lut_mask = 16'hF044; +defparam \ula_|i2c_loader_|shiftreg~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y23_N12 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~17 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~17_combout = (\ula_|i2c_loader_|thisbyte [0] & ((\ula_|i2c_loader_|thisbyte [4] & (!\ula_|i2c_loader_|thisbyte [1])) # (!\ula_|i2c_loader_|thisbyte [4] & ((!\ula_|i2c_loader_|thisbyte [3]))))) + + .dataa(\ula_|i2c_loader_|thisbyte [4]), + .datab(\ula_|i2c_loader_|thisbyte [0]), + .datac(\ula_|i2c_loader_|thisbyte [1]), + .datad(\ula_|i2c_loader_|thisbyte [3]), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~17_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~17 .lut_mask = 16'h084C; +defparam \ula_|i2c_loader_|shiftreg~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y23_N22 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~18 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~18_combout = ((\ula_|i2c_loader_|thisbyte [2] & ((!\ula_|i2c_loader_|thisbyte [0]))) # (!\ula_|i2c_loader_|thisbyte [2] & (\ula_|i2c_loader_|shiftreg~17_combout ))) # (!\ula_|i2c_loader_|shiftreg~4_combout ) + + .dataa(\ula_|i2c_loader_|shiftreg~17_combout ), + .datab(\ula_|i2c_loader_|thisbyte [2]), + .datac(\ula_|i2c_loader_|shiftreg~4_combout ), + .datad(\ula_|i2c_loader_|thisbyte [0]), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~18_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~18 .lut_mask = 16'h2FEF; +defparam \ula_|i2c_loader_|shiftreg~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y23_N14 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~20 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~20_combout = (\ula_|i2c_loader_|thisbyte [0] & ((\ula_|i2c_loader_|thisbyte [3] & (\ula_|i2c_loader_|thisbyte [2])) # (!\ula_|i2c_loader_|thisbyte [3] & (!\ula_|i2c_loader_|thisbyte [2] & !\ula_|i2c_loader_|thisbyte [4])))) + + .dataa(\ula_|i2c_loader_|thisbyte [0]), + .datab(\ula_|i2c_loader_|thisbyte [3]), + .datac(\ula_|i2c_loader_|thisbyte [2]), + .datad(\ula_|i2c_loader_|thisbyte [4]), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~20_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~20 .lut_mask = 16'h8082; +defparam \ula_|i2c_loader_|shiftreg~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y23_N24 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~21 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~21_combout = (\ula_|i2c_loader_|shiftreg~4_combout & ((\ula_|i2c_loader_|shiftreg~20_combout ) # ((\ula_|i2c_loader_|thisbyte [1] & !\ula_|i2c_loader_|thisbyte [0])))) + + .dataa(\ula_|i2c_loader_|shiftreg~4_combout ), + .datab(\ula_|i2c_loader_|shiftreg~20_combout ), + .datac(\ula_|i2c_loader_|thisbyte [1]), + .datad(\ula_|i2c_loader_|thisbyte [0]), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~21_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~21 .lut_mask = 16'h88A8; +defparam \ula_|i2c_loader_|shiftreg~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y23_N0 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~23 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg[0]~23_combout = (!\ula_|i2c_loader_|thisbyte [3] & (!\ula_|i2c_loader_|state.Data~q & \ula_|i2c_loader_|thisbyte [0])) .dataa(gnd), .datab(\ula_|i2c_loader_|thisbyte [3]), .datac(\ula_|i2c_loader_|state.Data~q ), .datad(\ula_|i2c_loader_|thisbyte [0]), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg[0]~24_combout ), + .combout(\ula_|i2c_loader_|shiftreg[0]~23_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[0]~24 .lut_mask = 16'h0300; -defparam \ula_|i2c_loader_|shiftreg[0]~24 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg[0]~23 .lut_mask = 16'h0300; +defparam \ula_|i2c_loader_|shiftreg[0]~23 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N14 +// Location: LCCOMB_X3_Y23_N30 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~6 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg[0]~6_combout = (!\ula_|i2c_loader_|phase [1] & (\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|state.Data~q )) +// \ula_|i2c_loader_|shiftreg[0]~6_combout = (\ula_|i2c_loader_|phase [1] & ((\ula_|i2c_loader_|state~24_combout ) # ((\ula_|i2c_loader_|state.Start~q )))) # (!\ula_|i2c_loader_|phase [1] & (((\ula_|i2c_loader_|state.Data~q )))) - .dataa(\ula_|i2c_loader_|phase [1]), - .datab(gnd), - .datac(\ula_|i2c_loader_|phase [0]), - .datad(\ula_|i2c_loader_|state.Data~q ), + .dataa(\ula_|i2c_loader_|state~24_combout ), + .datab(\ula_|i2c_loader_|state.Data~q ), + .datac(\ula_|i2c_loader_|state.Start~q ), + .datad(\ula_|i2c_loader_|phase [1]), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg[0]~6_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[0]~6 .lut_mask = 16'h5000; +defparam \ula_|i2c_loader_|shiftreg[0]~6 .lut_mask = 16'hFACC; defparam \ula_|i2c_loader_|shiftreg[0]~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N0 +// Location: LCCOMB_X3_Y23_N8 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~7 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg[0]~7_combout = (\ula_|i2c_loader_|shiftreg[0]~6_combout ) # ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Start~q ) # (\ula_|i2c_loader_|state~24_combout )))) +// \ula_|i2c_loader_|shiftreg[0]~7_combout = (\ula_|i2c_loader_|shiftreg[0]~6_combout & (\ula_|i2c_loader_|phase [0] & (!\ula_|i2c_loader_|WideAnd0~combout & \ula_|i2c_loader_|state.Idle~q ))) - .dataa(\ula_|i2c_loader_|state.Start~q ), - .datab(\ula_|i2c_loader_|Mux42~0_combout ), - .datac(\ula_|i2c_loader_|shiftreg[0]~6_combout ), - .datad(\ula_|i2c_loader_|state~24_combout ), + .dataa(\ula_|i2c_loader_|shiftreg[0]~6_combout ), + .datab(\ula_|i2c_loader_|phase [0]), + .datac(\ula_|i2c_loader_|WideAnd0~combout ), + .datad(\ula_|i2c_loader_|state.Idle~q ), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg[0]~7_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[0]~7 .lut_mask = 16'hFCF8; +defparam \ula_|i2c_loader_|shiftreg[0]~7 .lut_mask = 16'h0800; defparam \ula_|i2c_loader_|shiftreg[0]~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N10 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~8 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg[0]~8_combout = (\ula_|i2c_loader_|state.Idle~q & (!\ula_|i2c_loader_|WideAnd0~combout & \ula_|i2c_loader_|shiftreg[0]~7_combout )) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|state.Idle~q ), - .datac(\ula_|i2c_loader_|WideAnd0~combout ), - .datad(\ula_|i2c_loader_|shiftreg[0]~7_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg[0]~8_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[0]~8 .lut_mask = 16'h0C00; -defparam \ula_|i2c_loader_|shiftreg[0]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X3_Y23_N13 +// Location: FF_X4_Y23_N1 dffeas \ula_|i2c_loader_|shiftreg[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|shiftreg[0]~24_combout ), + .d(\ula_|i2c_loader_|shiftreg[0]~23_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(\ula_|i2c_loader_|state.Start~q ), .sload(gnd), - .ena(\ula_|i2c_loader_|shiftreg[0]~8_combout ), + .ena(\ula_|i2c_loader_|shiftreg[0]~7_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [0]), @@ -55203,102 +55021,68 @@ defparam \ula_|i2c_loader_|shiftreg[0] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N26 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~21 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~21_combout = (\ula_|i2c_loader_|thisbyte [0] & ((\ula_|i2c_loader_|thisbyte [3] & ((\ula_|i2c_loader_|thisbyte [2]))) # (!\ula_|i2c_loader_|thisbyte [3] & (!\ula_|i2c_loader_|thisbyte [4] & !\ula_|i2c_loader_|thisbyte [2])))) - - .dataa(\ula_|i2c_loader_|thisbyte [4]), - .datab(\ula_|i2c_loader_|thisbyte [3]), - .datac(\ula_|i2c_loader_|thisbyte [0]), - .datad(\ula_|i2c_loader_|thisbyte [2]), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~21_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~21 .lut_mask = 16'hC010; -defparam \ula_|i2c_loader_|shiftreg~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y23_N28 +// Location: LCCOMB_X4_Y23_N28 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~22 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~22_combout = (\ula_|i2c_loader_|shiftreg~4_combout & ((\ula_|i2c_loader_|shiftreg~21_combout ) # ((\ula_|i2c_loader_|thisbyte [1] & !\ula_|i2c_loader_|thisbyte [0])))) +// \ula_|i2c_loader_|shiftreg~22_combout = (\ula_|i2c_loader_|shiftreg~21_combout ) # ((\ula_|i2c_loader_|state.Data~q & \ula_|i2c_loader_|shiftreg [0])) - .dataa(\ula_|i2c_loader_|shiftreg~21_combout ), - .datab(\ula_|i2c_loader_|shiftreg~4_combout ), - .datac(\ula_|i2c_loader_|thisbyte [1]), - .datad(\ula_|i2c_loader_|thisbyte [0]), + .dataa(gnd), + .datab(\ula_|i2c_loader_|shiftreg~21_combout ), + .datac(\ula_|i2c_loader_|state.Data~q ), + .datad(\ula_|i2c_loader_|shiftreg [0]), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg~22_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~22 .lut_mask = 16'h88C8; +defparam \ula_|i2c_loader_|shiftreg~22 .lut_mask = 16'hFCCC; defparam \ula_|i2c_loader_|shiftreg~22 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N22 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~23 ( +// Location: LCCOMB_X3_Y23_N10 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[6]~9 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~23_combout = (\ula_|i2c_loader_|shiftreg~22_combout ) # ((\ula_|i2c_loader_|shiftreg [0] & \ula_|i2c_loader_|state.Data~q )) +// \ula_|i2c_loader_|shiftreg[6]~9_combout = (\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|state.Start~q $ (!\ula_|i2c_loader_|phase [1])))) # (!\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|phase [1] & ((\ula_|i2c_loader_|state~24_combout +// ) # (\ula_|i2c_loader_|state.Start~q )))) - .dataa(\ula_|i2c_loader_|shiftreg [0]), - .datab(gnd), - .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|shiftreg~22_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~23_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~23 .lut_mask = 16'hFFA0; -defparam \ula_|i2c_loader_|shiftreg~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N10 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[6]~10 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg[6]~10_combout = (\ula_|i2c_loader_|phase [1] & ((\ula_|i2c_loader_|state.Start~q ) # ((!\ula_|i2c_loader_|state.Data~q & \ula_|i2c_loader_|state~24_combout )))) # (!\ula_|i2c_loader_|phase [1] & (\ula_|i2c_loader_|state.Data~q -// & (!\ula_|i2c_loader_|state.Start~q ))) - - .dataa(\ula_|i2c_loader_|phase [1]), + .dataa(\ula_|i2c_loader_|state~24_combout ), .datab(\ula_|i2c_loader_|state.Data~q ), .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|state~24_combout ), + .datad(\ula_|i2c_loader_|phase [1]), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg[6]~9_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg[6]~9 .lut_mask = 16'hF20C; +defparam \ula_|i2c_loader_|shiftreg[6]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y23_N12 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[6]~10 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg[6]~10_combout = (\ula_|i2c_loader_|shiftreg[6]~9_combout & (\ula_|i2c_loader_|phase [0] & (!\ula_|i2c_loader_|WideAnd0~combout & \ula_|i2c_loader_|state.Idle~q ))) + + .dataa(\ula_|i2c_loader_|shiftreg[6]~9_combout ), + .datab(\ula_|i2c_loader_|phase [0]), + .datac(\ula_|i2c_loader_|WideAnd0~combout ), + .datad(\ula_|i2c_loader_|state.Idle~q ), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg[6]~10_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[6]~10 .lut_mask = 16'hA6A4; +defparam \ula_|i2c_loader_|shiftreg[6]~10 .lut_mask = 16'h0800; defparam \ula_|i2c_loader_|shiftreg[6]~10 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N24 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[6]~11 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg[6]~11_combout = (\ula_|i2c_loader_|phase [0] & (!\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|state.Idle~q & \ula_|i2c_loader_|shiftreg[6]~10_combout ))) - - .dataa(\ula_|i2c_loader_|phase [0]), - .datab(\ula_|i2c_loader_|WideAnd0~combout ), - .datac(\ula_|i2c_loader_|state.Idle~q ), - .datad(\ula_|i2c_loader_|shiftreg[6]~10_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg[6]~11_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[6]~11 .lut_mask = 16'h2000; -defparam \ula_|i2c_loader_|shiftreg[6]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X3_Y23_N23 +// Location: FF_X4_Y23_N29 dffeas \ula_|i2c_loader_|shiftreg[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|shiftreg~23_combout ), + .d(\ula_|i2c_loader_|shiftreg~22_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2c_loader_|shiftreg[6]~11_combout ), + .ena(\ula_|i2c_loader_|shiftreg[6]~10_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [1]), @@ -55308,67 +55092,33 @@ defparam \ula_|i2c_loader_|shiftreg[1] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N4 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~18 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~18_combout = (\ula_|i2c_loader_|thisbyte [0] & ((\ula_|i2c_loader_|thisbyte [4] & ((!\ula_|i2c_loader_|thisbyte [1]))) # (!\ula_|i2c_loader_|thisbyte [4] & (!\ula_|i2c_loader_|thisbyte [3])))) - - .dataa(\ula_|i2c_loader_|thisbyte [4]), - .datab(\ula_|i2c_loader_|thisbyte [3]), - .datac(\ula_|i2c_loader_|thisbyte [0]), - .datad(\ula_|i2c_loader_|thisbyte [1]), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~18_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~18 .lut_mask = 16'h10B0; -defparam \ula_|i2c_loader_|shiftreg~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y23_N24 +// Location: LCCOMB_X4_Y23_N2 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~19 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~19_combout = ((\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte [0])) # (!\ula_|i2c_loader_|thisbyte [2] & ((\ula_|i2c_loader_|shiftreg~18_combout )))) # (!\ula_|i2c_loader_|shiftreg~4_combout ) +// \ula_|i2c_loader_|shiftreg~19_combout = (\ula_|i2c_loader_|shiftreg~18_combout & ((\ula_|i2c_loader_|shiftreg [1]) # (!\ula_|i2c_loader_|state.Data~q ))) - .dataa(\ula_|i2c_loader_|thisbyte [0]), - .datab(\ula_|i2c_loader_|thisbyte [2]), - .datac(\ula_|i2c_loader_|shiftreg~18_combout ), - .datad(\ula_|i2c_loader_|shiftreg~4_combout ), + .dataa(\ula_|i2c_loader_|shiftreg~18_combout ), + .datab(\ula_|i2c_loader_|shiftreg [1]), + .datac(\ula_|i2c_loader_|state.Data~q ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg~19_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~19 .lut_mask = 16'h74FF; +defparam \ula_|i2c_loader_|shiftreg~19 .lut_mask = 16'h8A8A; defparam \ula_|i2c_loader_|shiftreg~19 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N2 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~20 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~20_combout = (\ula_|i2c_loader_|shiftreg~19_combout & ((\ula_|i2c_loader_|shiftreg [1]) # (!\ula_|i2c_loader_|state.Data~q ))) - - .dataa(\ula_|i2c_loader_|shiftreg [1]), - .datab(gnd), - .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|shiftreg~19_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~20_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~20 .lut_mask = 16'hAF00; -defparam \ula_|i2c_loader_|shiftreg~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X3_Y23_N3 +// Location: FF_X4_Y23_N3 dffeas \ula_|i2c_loader_|shiftreg[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|shiftreg~20_combout ), + .d(\ula_|i2c_loader_|shiftreg~19_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2c_loader_|shiftreg[6]~11_combout ), + .ena(\ula_|i2c_loader_|shiftreg[6]~10_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [2]), @@ -55378,67 +55128,33 @@ defparam \ula_|i2c_loader_|shiftreg[2] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N28 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~16 ( +// Location: LCCOMB_X4_Y23_N8 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~25 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~16_combout = (\ula_|i2c_loader_|thisbyte [2] & (((!\ula_|i2c_loader_|thisbyte [3])))) # (!\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte [1] & (\ula_|i2c_loader_|thisbyte [4]))) - - .dataa(\ula_|i2c_loader_|thisbyte [2]), - .datab(\ula_|i2c_loader_|thisbyte [1]), - .datac(\ula_|i2c_loader_|thisbyte [4]), - .datad(\ula_|i2c_loader_|thisbyte [3]), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~16_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~16 .lut_mask = 16'h10BA; -defparam \ula_|i2c_loader_|shiftreg~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y23_N20 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~17 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~17_combout = (\ula_|i2c_loader_|thisbyte [0] & (((\ula_|i2c_loader_|shiftreg~16_combout )))) # (!\ula_|i2c_loader_|thisbyte [0] & (\ula_|i2c_loader_|thisbyte [3] & ((!\ula_|i2c_loader_|shiftreg~14_combout )))) - - .dataa(\ula_|i2c_loader_|thisbyte [0]), - .datab(\ula_|i2c_loader_|thisbyte [3]), - .datac(\ula_|i2c_loader_|shiftreg~16_combout ), - .datad(\ula_|i2c_loader_|shiftreg~14_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~17_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~17 .lut_mask = 16'hA0E4; -defparam \ula_|i2c_loader_|shiftreg~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y23_N6 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~26 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~26_combout = (\ula_|i2c_loader_|state.Data~q & (((\ula_|i2c_loader_|shiftreg [2])))) # (!\ula_|i2c_loader_|state.Data~q & (!\ula_|i2c_loader_|state.Start~q & ((\ula_|i2c_loader_|shiftreg~17_combout )))) +// \ula_|i2c_loader_|shiftreg~25_combout = (\ula_|i2c_loader_|state.Data~q & (((\ula_|i2c_loader_|shiftreg [2])))) # (!\ula_|i2c_loader_|state.Data~q & (!\ula_|i2c_loader_|state.Start~q & (\ula_|i2c_loader_|shiftreg~16_combout ))) .dataa(\ula_|i2c_loader_|state.Start~q ), - .datab(\ula_|i2c_loader_|shiftreg [2]), - .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|shiftreg~17_combout ), + .datab(\ula_|i2c_loader_|state.Data~q ), + .datac(\ula_|i2c_loader_|shiftreg~16_combout ), + .datad(\ula_|i2c_loader_|shiftreg [2]), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~26_combout ), + .combout(\ula_|i2c_loader_|shiftreg~25_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~26 .lut_mask = 16'hC5C0; -defparam \ula_|i2c_loader_|shiftreg~26 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg~25 .lut_mask = 16'hDC10; +defparam \ula_|i2c_loader_|shiftreg~25 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y23_N7 +// Location: FF_X4_Y23_N9 dffeas \ula_|i2c_loader_|shiftreg[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|shiftreg~26_combout ), + .d(\ula_|i2c_loader_|shiftreg~25_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2c_loader_|shiftreg[6]~11_combout ), + .ena(\ula_|i2c_loader_|shiftreg[6]~10_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [3]), @@ -55448,33 +55164,67 @@ defparam \ula_|i2c_loader_|shiftreg[3] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N0 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~25 ( +// Location: LCCOMB_X5_Y23_N14 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~12 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~25_combout = (\ula_|i2c_loader_|state.Data~q & (((\ula_|i2c_loader_|shiftreg [3])))) # (!\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|shiftreg~15_combout ) # ((\ula_|i2c_loader_|state.Start~q )))) +// \ula_|i2c_loader_|shiftreg~12_combout = (!\ula_|i2c_loader_|thisbyte [2] & ((\ula_|i2c_loader_|thisbyte [4] & ((!\ula_|i2c_loader_|thisbyte [0]))) # (!\ula_|i2c_loader_|thisbyte [4] & (!\ula_|i2c_loader_|thisbyte [1] & \ula_|i2c_loader_|thisbyte [0])))) - .dataa(\ula_|i2c_loader_|shiftreg~15_combout ), - .datab(\ula_|i2c_loader_|state.Data~q ), - .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|shiftreg [3]), + .dataa(\ula_|i2c_loader_|thisbyte [2]), + .datab(\ula_|i2c_loader_|thisbyte [1]), + .datac(\ula_|i2c_loader_|thisbyte [4]), + .datad(\ula_|i2c_loader_|thisbyte [0]), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~25_combout ), + .combout(\ula_|i2c_loader_|shiftreg~12_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~25 .lut_mask = 16'hFE32; -defparam \ula_|i2c_loader_|shiftreg~25 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg~12 .lut_mask = 16'h0150; +defparam \ula_|i2c_loader_|shiftreg~12 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X2_Y23_N1 +// Location: LCCOMB_X5_Y23_N6 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~14 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~14_combout = (\ula_|i2c_loader_|shiftreg~12_combout ) # ((!\ula_|i2c_loader_|shiftreg~13_combout & (!\ula_|i2c_loader_|thisbyte [3] & \ula_|i2c_loader_|thisbyte [0]))) + + .dataa(\ula_|i2c_loader_|shiftreg~13_combout ), + .datab(\ula_|i2c_loader_|thisbyte [3]), + .datac(\ula_|i2c_loader_|shiftreg~12_combout ), + .datad(\ula_|i2c_loader_|thisbyte [0]), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~14_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~14 .lut_mask = 16'hF1F0; +defparam \ula_|i2c_loader_|shiftreg~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y23_N6 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~24 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~24_combout = (\ula_|i2c_loader_|state.Data~q & (((\ula_|i2c_loader_|shiftreg [3])))) # (!\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|state.Start~q ) # ((\ula_|i2c_loader_|shiftreg~14_combout )))) + + .dataa(\ula_|i2c_loader_|state.Start~q ), + .datab(\ula_|i2c_loader_|shiftreg [3]), + .datac(\ula_|i2c_loader_|state.Data~q ), + .datad(\ula_|i2c_loader_|shiftreg~14_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~24_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~24 .lut_mask = 16'hCFCA; +defparam \ula_|i2c_loader_|shiftreg~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X4_Y23_N7 dffeas \ula_|i2c_loader_|shiftreg[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|shiftreg~25_combout ), + .d(\ula_|i2c_loader_|shiftreg~24_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2c_loader_|shiftreg[6]~11_combout ), + .ena(\ula_|i2c_loader_|shiftreg[6]~10_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [4]), @@ -55484,33 +55234,33 @@ defparam \ula_|i2c_loader_|shiftreg[4] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N4 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~12 ( +// Location: LCCOMB_X3_Y23_N24 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~11 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~12_combout = (\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|shiftreg [4]))) # (!\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|Mux35~0_combout )) +// \ula_|i2c_loader_|shiftreg~11_combout = (\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|shiftreg [4]))) # (!\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|Mux35~0_combout )) .dataa(\ula_|i2c_loader_|Mux35~0_combout ), .datab(\ula_|i2c_loader_|state.Data~q ), .datac(gnd), .datad(\ula_|i2c_loader_|shiftreg [4]), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~12_combout ), + .combout(\ula_|i2c_loader_|shiftreg~11_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~12 .lut_mask = 16'hEE22; -defparam \ula_|i2c_loader_|shiftreg~12 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg~11 .lut_mask = 16'hEE22; +defparam \ula_|i2c_loader_|shiftreg~11 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X2_Y24_N5 +// Location: FF_X3_Y23_N25 dffeas \ula_|i2c_loader_|shiftreg[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|shiftreg~12_combout ), + .d(\ula_|i2c_loader_|shiftreg~11_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(\ula_|i2c_loader_|state.Start~q ), - .ena(\ula_|i2c_loader_|shiftreg[6]~11_combout ), + .ena(\ula_|i2c_loader_|shiftreg[6]~10_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [5]), @@ -55520,33 +55270,33 @@ defparam \ula_|i2c_loader_|shiftreg[5] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N18 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~9 ( +// Location: LCCOMB_X4_Y23_N18 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~8 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~9_combout = (\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|shiftreg [5])) # (!\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|Mux35~0_combout ))) +// \ula_|i2c_loader_|shiftreg~8_combout = (\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|shiftreg [5])) # (!\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|Mux35~0_combout ))) .dataa(gnd), .datab(\ula_|i2c_loader_|shiftreg [5]), .datac(\ula_|i2c_loader_|state.Data~q ), .datad(\ula_|i2c_loader_|Mux35~0_combout ), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~9_combout ), + .combout(\ula_|i2c_loader_|shiftreg~8_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~9 .lut_mask = 16'hCFC0; -defparam \ula_|i2c_loader_|shiftreg~9 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg~8 .lut_mask = 16'hCFC0; +defparam \ula_|i2c_loader_|shiftreg~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y23_N19 +// Location: FF_X4_Y23_N19 dffeas \ula_|i2c_loader_|shiftreg[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|shiftreg~9_combout ), + .d(\ula_|i2c_loader_|shiftreg~8_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(\ula_|i2c_loader_|state.Start~q ), .sload(gnd), - .ena(\ula_|i2c_loader_|shiftreg[6]~11_combout ), + .ena(\ula_|i2c_loader_|shiftreg[6]~10_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [6]), @@ -55556,7 +55306,7 @@ defparam \ula_|i2c_loader_|shiftreg[6] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N4 +// Location: LCCOMB_X4_Y23_N16 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[7]~5 ( // Equation(s): // \ula_|i2c_loader_|shiftreg[7]~5_combout = (\ula_|i2c_loader_|state.Data~q & \ula_|i2c_loader_|shiftreg [6]) @@ -55573,7 +55323,7 @@ defparam \ula_|i2c_loader_|shiftreg[7]~5 .lut_mask = 16'hF000; defparam \ula_|i2c_loader_|shiftreg[7]~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y23_N5 +// Location: FF_X4_Y23_N17 dffeas \ula_|i2c_loader_|shiftreg[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|shiftreg[7]~5_combout ), @@ -55582,7 +55332,7 @@ dffeas \ula_|i2c_loader_|shiftreg[7] ( .aload(gnd), .sclr(\ula_|i2c_loader_|state.Start~q ), .sload(gnd), - .ena(\ula_|i2c_loader_|shiftreg[0]~8_combout ), + .ena(\ula_|i2c_loader_|shiftreg[0]~7_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [7]), @@ -55592,25 +55342,25 @@ defparam \ula_|i2c_loader_|shiftreg[7] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N12 +// Location: LCCOMB_X1_Y23_N26 cycloneive_lcell_comb \ula_|i2c_loader_|sda_out~0 ( // Equation(s): -// \ula_|i2c_loader_|sda_out~0_combout = (\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|shiftreg [7]))) # (!\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|state.Ack~q )))) # (!\ula_|i2c_loader_|state.Data~q & +// \ula_|i2c_loader_|sda_out~0_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|shiftreg [7])) # (!\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|state.Ack~q ))))) # (!\ula_|i2c_loader_|phase [0] & // (((\ula_|i2c_loader_|state.Ack~q )))) - .dataa(\ula_|i2c_loader_|state.Data~q ), - .datab(\ula_|i2c_loader_|phase [0]), - .datac(\ula_|i2c_loader_|state.Ack~q ), - .datad(\ula_|i2c_loader_|shiftreg [7]), + .dataa(\ula_|i2c_loader_|shiftreg [7]), + .datab(\ula_|i2c_loader_|state.Ack~q ), + .datac(\ula_|i2c_loader_|phase [0]), + .datad(\ula_|i2c_loader_|state.Data~q ), .cin(gnd), .combout(\ula_|i2c_loader_|sda_out~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|sda_out~0 .lut_mask = 16'hF870; +defparam \ula_|i2c_loader_|sda_out~0 .lut_mask = 16'hACCC; defparam \ula_|i2c_loader_|sda_out~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N6 +// Location: LCCOMB_X1_Y23_N20 cycloneive_lcell_comb \ula_|i2c_loader_|sda_out~1 ( // Equation(s): // \ula_|i2c_loader_|sda_out~1_combout = (\ula_|i2c_loader_|sda_out~0_combout & ((\ula_|i2c_loader_|phase [0]) # ((\ula_|i2c_loader_|shiftreg~4_combout & !\I2C_SDAT~input_o )))) @@ -55627,55 +55377,55 @@ defparam \ula_|i2c_loader_|sda_out~1 .lut_mask = 16'hC0E0; defparam \ula_|i2c_loader_|sda_out~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N8 +// Location: LCCOMB_X1_Y23_N14 cycloneive_lcell_comb \ula_|i2c_loader_|sda_out~2 ( // Equation(s): // \ula_|i2c_loader_|sda_out~2_combout = (!\ula_|i2c_loader_|sda_out~_Duplicate_1_q & ((\ula_|i2c_loader_|phase [0]) # ((\ula_|i2c_loader_|phase [1] & !\ula_|i2c_loader_|sda_out~1_combout )))) .dataa(\ula_|i2c_loader_|sda_out~_Duplicate_1_q ), - .datab(\ula_|i2c_loader_|phase [0]), - .datac(\ula_|i2c_loader_|phase [1]), + .datab(\ula_|i2c_loader_|phase [1]), + .datac(\ula_|i2c_loader_|phase [0]), .datad(\ula_|i2c_loader_|sda_out~1_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|sda_out~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|sda_out~2 .lut_mask = 16'h4454; +defparam \ula_|i2c_loader_|sda_out~2 .lut_mask = 16'h5054; defparam \ula_|i2c_loader_|sda_out~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N2 +// Location: LCCOMB_X1_Y23_N28 cycloneive_lcell_comb \ula_|i2c_loader_|sda_out~3 ( // Equation(s): -// \ula_|i2c_loader_|sda_out~3_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|phase [1] & (\ula_|i2c_loader_|sda_out~_Duplicate_1_q )) # (!\ula_|i2c_loader_|phase [1] & ((!\ula_|i2c_loader_|sda_out~1_combout ))))) # (!\ula_|i2c_loader_|phase -// [0] & ((\ula_|i2c_loader_|sda_out~_Duplicate_1_q ) # ((\ula_|i2c_loader_|phase [1] & \ula_|i2c_loader_|sda_out~1_combout )))) +// \ula_|i2c_loader_|sda_out~3_combout = (\ula_|i2c_loader_|phase [1] & ((\ula_|i2c_loader_|sda_out~_Duplicate_1_q ) # ((!\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|sda_out~1_combout )))) # (!\ula_|i2c_loader_|phase [1] & ((\ula_|i2c_loader_|phase [0] +// & ((!\ula_|i2c_loader_|sda_out~1_combout ))) # (!\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|sda_out~_Duplicate_1_q )))) .dataa(\ula_|i2c_loader_|sda_out~_Duplicate_1_q ), - .datab(\ula_|i2c_loader_|phase [0]), - .datac(\ula_|i2c_loader_|phase [1]), + .datab(\ula_|i2c_loader_|phase [1]), + .datac(\ula_|i2c_loader_|phase [0]), .datad(\ula_|i2c_loader_|sda_out~1_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|sda_out~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|sda_out~3 .lut_mask = 16'hB2AE; +defparam \ula_|i2c_loader_|sda_out~3 .lut_mask = 16'h8EBA; defparam \ula_|i2c_loader_|sda_out~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N22 +// Location: LCCOMB_X1_Y23_N12 cycloneive_lcell_comb \ula_|i2c_loader_|sda_out~4 ( // Equation(s): // \ula_|i2c_loader_|sda_out~4_combout = (\ula_|i2c_loader_|state.Start~q & (((!\ula_|i2c_loader_|sda_out~2_combout )))) # (!\ula_|i2c_loader_|state.Start~q & (!\ula_|i2c_loader_|scl_out~0_combout & ((\ula_|i2c_loader_|sda_out~3_combout )))) - .dataa(\ula_|i2c_loader_|state.Start~q ), - .datab(\ula_|i2c_loader_|scl_out~0_combout ), + .dataa(\ula_|i2c_loader_|scl_out~0_combout ), + .datab(\ula_|i2c_loader_|state.Start~q ), .datac(\ula_|i2c_loader_|sda_out~2_combout ), .datad(\ula_|i2c_loader_|sda_out~3_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|sda_out~4_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|sda_out~4 .lut_mask = 16'h1B0A; +defparam \ula_|i2c_loader_|sda_out~4 .lut_mask = 16'h1D0C; defparam \ula_|i2c_loader_|sda_out~4 .sum_lutc_input = "datac"; // synopsys translate_on @@ -55698,7 +55448,7 @@ defparam \ula_|i2c_loader_|sda_out .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|sda_out .power_up = "high"; // synopsys translate_on -// Location: LCCOMB_X27_Y23_N16 +// Location: LCCOMB_X25_Y32_N20 cycloneive_lcell_comb \ula_|i2s_intf_|mclk_r~0 ( // Equation(s): // \ula_|i2s_intf_|mclk_r~0_combout = !\ula_|i2s_intf_|mclk_r~_Duplicate_1_q @@ -55715,7 +55465,7 @@ defparam \ula_|i2s_intf_|mclk_r~0 .lut_mask = 16'h0F0F; defparam \ula_|i2s_intf_|mclk_r~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X27_Y23_N17 +// Location: FF_X25_Y32_N21 dffeas \ula_|i2s_intf_|mclk_r~_Duplicate_1 ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|mclk_r~0_combout ), @@ -55753,7 +55503,7 @@ defparam \ula_|i2s_intf_|mclk_r .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|mclk_r .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N6 +// Location: LCCOMB_X24_Y32_N8 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~1 ( // Equation(s): // \ula_|i2s_intf_|Add0~1_cout = CARRY(!\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ) @@ -55770,25 +55520,25 @@ defparam \ula_|i2s_intf_|Add0~1 .lut_mask = 16'h0055; defparam \ula_|i2s_intf_|Add0~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N8 +// Location: LCCOMB_X24_Y32_N10 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~2 ( // Equation(s): // \ula_|i2s_intf_|Add0~2_combout = (\ula_|i2s_intf_|lrdivider [1] & (\ula_|i2s_intf_|Add0~1_cout & VCC)) # (!\ula_|i2s_intf_|lrdivider [1] & (!\ula_|i2s_intf_|Add0~1_cout )) // \ula_|i2s_intf_|Add0~3 = CARRY((!\ula_|i2s_intf_|lrdivider [1] & !\ula_|i2s_intf_|Add0~1_cout )) - .dataa(gnd), - .datab(\ula_|i2s_intf_|lrdivider [1]), + .dataa(\ula_|i2s_intf_|lrdivider [1]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\ula_|i2s_intf_|Add0~1_cout ), .combout(\ula_|i2s_intf_|Add0~2_combout ), .cout(\ula_|i2s_intf_|Add0~3 )); // synopsys translate_off -defparam \ula_|i2s_intf_|Add0~2 .lut_mask = 16'hC303; +defparam \ula_|i2s_intf_|Add0~2 .lut_mask = 16'hA505; defparam \ula_|i2s_intf_|Add0~2 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N28 +// Location: LCCOMB_X23_Y32_N10 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider~2 ( // Equation(s): // \ula_|i2s_intf_|lrdivider~2_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|Add0~2_combout ) @@ -55805,7 +55555,7 @@ defparam \ula_|i2s_intf_|lrdivider~2 .lut_mask = 16'h5050; defparam \ula_|i2s_intf_|lrdivider~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X29_Y23_N29 +// Location: FF_X23_Y32_N11 dffeas \ula_|i2s_intf_|lrdivider[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider~2_combout ), @@ -55824,42 +55574,42 @@ defparam \ula_|i2s_intf_|lrdivider[1] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N10 +// Location: LCCOMB_X24_Y32_N12 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~4 ( // Equation(s): // \ula_|i2s_intf_|Add0~4_combout = (\ula_|i2s_intf_|lrdivider [2] & (\ula_|i2s_intf_|Add0~3 $ (GND))) # (!\ula_|i2s_intf_|lrdivider [2] & ((GND) # (!\ula_|i2s_intf_|Add0~3 ))) // \ula_|i2s_intf_|Add0~5 = CARRY((!\ula_|i2s_intf_|Add0~3 ) # (!\ula_|i2s_intf_|lrdivider [2])) - .dataa(\ula_|i2s_intf_|lrdivider [2]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|i2s_intf_|lrdivider [2]), .datac(gnd), .datad(vcc), .cin(\ula_|i2s_intf_|Add0~3 ), .combout(\ula_|i2s_intf_|Add0~4_combout ), .cout(\ula_|i2s_intf_|Add0~5 )); // synopsys translate_off -defparam \ula_|i2s_intf_|Add0~4 .lut_mask = 16'hA55F; +defparam \ula_|i2s_intf_|Add0~4 .lut_mask = 16'hC33F; defparam \ula_|i2s_intf_|Add0~4 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X30_Y23_N6 +// Location: LCCOMB_X23_Y32_N22 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[2]~8 ( // Equation(s): // \ula_|i2s_intf_|lrdivider[2]~8_combout = !\ula_|i2s_intf_|Add0~4_combout .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|Add0~4_combout ), + .datac(\ula_|i2s_intf_|Add0~4_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|lrdivider[2]~8_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[2]~8 .lut_mask = 16'h00FF; +defparam \ula_|i2s_intf_|lrdivider[2]~8 .lut_mask = 16'h0F0F; defparam \ula_|i2s_intf_|lrdivider[2]~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y23_N7 +// Location: FF_X23_Y32_N23 dffeas \ula_|i2s_intf_|lrdivider[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider[2]~8_combout ), @@ -55878,7 +55628,7 @@ defparam \ula_|i2s_intf_|lrdivider[2] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N12 +// Location: LCCOMB_X24_Y32_N14 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~6 ( // Equation(s): // \ula_|i2s_intf_|Add0~6_combout = (\ula_|i2s_intf_|lrdivider [3] & (!\ula_|i2s_intf_|Add0~5 )) # (!\ula_|i2s_intf_|lrdivider [3] & (\ula_|i2s_intf_|Add0~5 & VCC)) @@ -55896,24 +55646,24 @@ defparam \ula_|i2s_intf_|Add0~6 .lut_mask = 16'h3C0C; defparam \ula_|i2s_intf_|Add0~6 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X28_Y23_N6 +// Location: LCCOMB_X23_Y32_N4 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[3]~7 ( // Equation(s): // \ula_|i2s_intf_|lrdivider[3]~7_combout = !\ula_|i2s_intf_|Add0~6_combout .dataa(gnd), .datab(gnd), - .datac(\ula_|i2s_intf_|Add0~6_combout ), - .datad(gnd), + .datac(gnd), + .datad(\ula_|i2s_intf_|Add0~6_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|lrdivider[3]~7_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[3]~7 .lut_mask = 16'h0F0F; +defparam \ula_|i2s_intf_|lrdivider[3]~7 .lut_mask = 16'h00FF; defparam \ula_|i2s_intf_|lrdivider[3]~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y23_N7 +// Location: FF_X23_Y32_N5 dffeas \ula_|i2s_intf_|lrdivider[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider[3]~7_combout ), @@ -55932,42 +55682,42 @@ defparam \ula_|i2s_intf_|lrdivider[3] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N14 +// Location: LCCOMB_X24_Y32_N16 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~8 ( // Equation(s): // \ula_|i2s_intf_|Add0~8_combout = (\ula_|i2s_intf_|lrdivider [4] & ((GND) # (!\ula_|i2s_intf_|Add0~7 ))) # (!\ula_|i2s_intf_|lrdivider [4] & (\ula_|i2s_intf_|Add0~7 $ (GND))) // \ula_|i2s_intf_|Add0~9 = CARRY((\ula_|i2s_intf_|lrdivider [4]) # (!\ula_|i2s_intf_|Add0~7 )) - .dataa(gnd), - .datab(\ula_|i2s_intf_|lrdivider [4]), + .dataa(\ula_|i2s_intf_|lrdivider [4]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\ula_|i2s_intf_|Add0~7 ), .combout(\ula_|i2s_intf_|Add0~8_combout ), .cout(\ula_|i2s_intf_|Add0~9 )); // synopsys translate_off -defparam \ula_|i2s_intf_|Add0~8 .lut_mask = 16'h3CCF; +defparam \ula_|i2s_intf_|Add0~8 .lut_mask = 16'h5AAF; defparam \ula_|i2s_intf_|Add0~8 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N4 +// Location: LCCOMB_X23_Y32_N16 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider~1 ( // Equation(s): // \ula_|i2s_intf_|lrdivider~1_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|Add0~8_combout ) - .dataa(\ula_|i2s_intf_|Equal0~2_combout ), + .dataa(gnd), .datab(gnd), - .datac(\ula_|i2s_intf_|Add0~8_combout ), - .datad(gnd), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|Add0~8_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|lrdivider~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider~1 .lut_mask = 16'h5050; +defparam \ula_|i2s_intf_|lrdivider~1 .lut_mask = 16'h0F00; defparam \ula_|i2s_intf_|lrdivider~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X29_Y23_N5 +// Location: FF_X23_Y32_N17 dffeas \ula_|i2s_intf_|lrdivider[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider~1_combout ), @@ -55986,25 +55736,25 @@ defparam \ula_|i2s_intf_|lrdivider[4] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N16 +// Location: LCCOMB_X24_Y32_N18 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~10 ( // Equation(s): // \ula_|i2s_intf_|Add0~10_combout = (\ula_|i2s_intf_|lrdivider [5] & (!\ula_|i2s_intf_|Add0~9 )) # (!\ula_|i2s_intf_|lrdivider [5] & (\ula_|i2s_intf_|Add0~9 & VCC)) // \ula_|i2s_intf_|Add0~11 = CARRY((\ula_|i2s_intf_|lrdivider [5] & !\ula_|i2s_intf_|Add0~9 )) - .dataa(gnd), - .datab(\ula_|i2s_intf_|lrdivider [5]), + .dataa(\ula_|i2s_intf_|lrdivider [5]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\ula_|i2s_intf_|Add0~9 ), .combout(\ula_|i2s_intf_|Add0~10_combout ), .cout(\ula_|i2s_intf_|Add0~11 )); // synopsys translate_off -defparam \ula_|i2s_intf_|Add0~10 .lut_mask = 16'h3C0C; +defparam \ula_|i2s_intf_|Add0~10 .lut_mask = 16'h5A0A; defparam \ula_|i2s_intf_|Add0~10 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N2 +// Location: LCCOMB_X23_Y32_N14 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[5]~6 ( // Equation(s): // \ula_|i2s_intf_|lrdivider[5]~6_combout = !\ula_|i2s_intf_|Add0~10_combout @@ -56021,7 +55771,7 @@ defparam \ula_|i2s_intf_|lrdivider[5]~6 .lut_mask = 16'h00FF; defparam \ula_|i2s_intf_|lrdivider[5]~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X29_Y23_N3 +// Location: FF_X23_Y32_N15 dffeas \ula_|i2s_intf_|lrdivider[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider[5]~6_combout ), @@ -56040,24 +55790,24 @@ defparam \ula_|i2s_intf_|lrdivider[5] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N26 +// Location: LCCOMB_X24_Y32_N0 cycloneive_lcell_comb \ula_|i2s_intf_|Equal0~1 ( // Equation(s): -// \ula_|i2s_intf_|Equal0~1_combout = (\ula_|i2s_intf_|lrdivider [2] & (!\ula_|i2s_intf_|lrdivider [4] & (\ula_|i2s_intf_|lrdivider [3] & \ula_|i2s_intf_|lrdivider [5]))) +// \ula_|i2s_intf_|Equal0~1_combout = (!\ula_|i2s_intf_|lrdivider [4] & (\ula_|i2s_intf_|lrdivider [2] & (\ula_|i2s_intf_|lrdivider [3] & \ula_|i2s_intf_|lrdivider [5]))) - .dataa(\ula_|i2s_intf_|lrdivider [2]), - .datab(\ula_|i2s_intf_|lrdivider [4]), + .dataa(\ula_|i2s_intf_|lrdivider [4]), + .datab(\ula_|i2s_intf_|lrdivider [2]), .datac(\ula_|i2s_intf_|lrdivider [3]), .datad(\ula_|i2s_intf_|lrdivider [5]), .cin(gnd), .combout(\ula_|i2s_intf_|Equal0~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|Equal0~1 .lut_mask = 16'h2000; +defparam \ula_|i2s_intf_|Equal0~1 .lut_mask = 16'h4000; defparam \ula_|i2s_intf_|Equal0~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N18 +// Location: LCCOMB_X24_Y32_N20 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~12 ( // Equation(s): // \ula_|i2s_intf_|Add0~12_combout = (\ula_|i2s_intf_|lrdivider [6] & (\ula_|i2s_intf_|Add0~11 $ (GND))) # (!\ula_|i2s_intf_|lrdivider [6] & ((GND) # (!\ula_|i2s_intf_|Add0~11 ))) @@ -56075,24 +55825,24 @@ defparam \ula_|i2s_intf_|Add0~12 .lut_mask = 16'hA55F; defparam \ula_|i2s_intf_|Add0~12 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X28_Y23_N26 +// Location: LCCOMB_X23_Y32_N0 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[6]~5 ( // Equation(s): // \ula_|i2s_intf_|lrdivider[6]~5_combout = !\ula_|i2s_intf_|Add0~12_combout .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|Add0~12_combout ), + .datac(\ula_|i2s_intf_|Add0~12_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|lrdivider[6]~5_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[6]~5 .lut_mask = 16'h00FF; +defparam \ula_|i2s_intf_|lrdivider[6]~5 .lut_mask = 16'h0F0F; defparam \ula_|i2s_intf_|lrdivider[6]~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y23_N27 +// Location: FF_X23_Y32_N1 dffeas \ula_|i2s_intf_|lrdivider[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider[6]~5_combout ), @@ -56111,42 +55861,42 @@ defparam \ula_|i2s_intf_|lrdivider[6] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N20 +// Location: LCCOMB_X24_Y32_N22 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~14 ( // Equation(s): // \ula_|i2s_intf_|Add0~14_combout = (\ula_|i2s_intf_|lrdivider [7] & (!\ula_|i2s_intf_|Add0~13 )) # (!\ula_|i2s_intf_|lrdivider [7] & (\ula_|i2s_intf_|Add0~13 & VCC)) // \ula_|i2s_intf_|Add0~15 = CARRY((\ula_|i2s_intf_|lrdivider [7] & !\ula_|i2s_intf_|Add0~13 )) - .dataa(\ula_|i2s_intf_|lrdivider [7]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|i2s_intf_|lrdivider [7]), .datac(gnd), .datad(vcc), .cin(\ula_|i2s_intf_|Add0~13 ), .combout(\ula_|i2s_intf_|Add0~14_combout ), .cout(\ula_|i2s_intf_|Add0~15 )); // synopsys translate_off -defparam \ula_|i2s_intf_|Add0~14 .lut_mask = 16'h5A0A; +defparam \ula_|i2s_intf_|Add0~14 .lut_mask = 16'h3C0C; defparam \ula_|i2s_intf_|Add0~14 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X30_Y23_N4 +// Location: LCCOMB_X24_Y32_N2 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[7]~4 ( // Equation(s): // \ula_|i2s_intf_|lrdivider[7]~4_combout = !\ula_|i2s_intf_|Add0~14_combout .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|Add0~14_combout ), + .datac(\ula_|i2s_intf_|Add0~14_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|lrdivider[7]~4_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[7]~4 .lut_mask = 16'h00FF; +defparam \ula_|i2s_intf_|lrdivider[7]~4 .lut_mask = 16'h0F0F; defparam \ula_|i2s_intf_|lrdivider[7]~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y23_N5 +// Location: FF_X24_Y32_N3 dffeas \ula_|i2s_intf_|lrdivider[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider[7]~4_combout ), @@ -56165,25 +55915,25 @@ defparam \ula_|i2s_intf_|lrdivider[7] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N22 +// Location: LCCOMB_X24_Y32_N24 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~16 ( // Equation(s): // \ula_|i2s_intf_|Add0~16_combout = (\ula_|i2s_intf_|lrdivider [8] & ((GND) # (!\ula_|i2s_intf_|Add0~15 ))) # (!\ula_|i2s_intf_|lrdivider [8] & (\ula_|i2s_intf_|Add0~15 $ (GND))) // \ula_|i2s_intf_|Add0~17 = CARRY((\ula_|i2s_intf_|lrdivider [8]) # (!\ula_|i2s_intf_|Add0~15 )) - .dataa(\ula_|i2s_intf_|lrdivider [8]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|i2s_intf_|lrdivider [8]), .datac(gnd), .datad(vcc), .cin(\ula_|i2s_intf_|Add0~15 ), .combout(\ula_|i2s_intf_|Add0~16_combout ), .cout(\ula_|i2s_intf_|Add0~17 )); // synopsys translate_off -defparam \ula_|i2s_intf_|Add0~16 .lut_mask = 16'h5AAF; +defparam \ula_|i2s_intf_|Add0~16 .lut_mask = 16'h3CCF; defparam \ula_|i2s_intf_|Add0~16 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X28_Y23_N16 +// Location: LCCOMB_X24_Y32_N28 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider~0 ( // Equation(s): // \ula_|i2s_intf_|lrdivider~0_combout = (\ula_|i2s_intf_|Add0~16_combout & !\ula_|i2s_intf_|Equal0~2_combout ) @@ -56200,7 +55950,7 @@ defparam \ula_|i2s_intf_|lrdivider~0 .lut_mask = 16'h0C0C; defparam \ula_|i2s_intf_|lrdivider~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y23_N17 +// Location: FF_X24_Y32_N29 dffeas \ula_|i2s_intf_|lrdivider[8] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider~0_combout ), @@ -56219,41 +55969,41 @@ defparam \ula_|i2s_intf_|lrdivider[8] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[8] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N24 +// Location: LCCOMB_X24_Y32_N26 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~18 ( // Equation(s): -// \ula_|i2s_intf_|Add0~18_combout = \ula_|i2s_intf_|Add0~17 $ (\ula_|i2s_intf_|lrdivider [9]) +// \ula_|i2s_intf_|Add0~18_combout = \ula_|i2s_intf_|lrdivider [9] $ (\ula_|i2s_intf_|Add0~17 ) .dataa(gnd), - .datab(gnd), + .datab(\ula_|i2s_intf_|lrdivider [9]), .datac(gnd), - .datad(\ula_|i2s_intf_|lrdivider [9]), + .datad(gnd), .cin(\ula_|i2s_intf_|Add0~17 ), .combout(\ula_|i2s_intf_|Add0~18_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|Add0~18 .lut_mask = 16'h0FF0; +defparam \ula_|i2s_intf_|Add0~18 .lut_mask = 16'h3C3C; defparam \ula_|i2s_intf_|Add0~18 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X28_Y23_N24 +// Location: LCCOMB_X24_Y32_N4 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[9]~3 ( // Equation(s): // \ula_|i2s_intf_|lrdivider[9]~3_combout = !\ula_|i2s_intf_|Add0~18_combout .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|Add0~18_combout ), + .datac(\ula_|i2s_intf_|Add0~18_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|lrdivider[9]~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[9]~3 .lut_mask = 16'h00FF; +defparam \ula_|i2s_intf_|lrdivider[9]~3 .lut_mask = 16'h0F0F; defparam \ula_|i2s_intf_|lrdivider[9]~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y23_N25 +// Location: FF_X24_Y32_N5 dffeas \ula_|i2s_intf_|lrdivider[9] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider[9]~3_combout ), @@ -56272,61 +56022,44 @@ defparam \ula_|i2s_intf_|lrdivider[9] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[9] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N0 +// Location: LCCOMB_X24_Y32_N6 cycloneive_lcell_comb \ula_|i2s_intf_|Equal0~0 ( // Equation(s): -// \ula_|i2s_intf_|Equal0~0_combout = (!\ula_|i2s_intf_|lrdivider [8] & (\ula_|i2s_intf_|lrdivider [9] & (\ula_|i2s_intf_|lrdivider [6] & \ula_|i2s_intf_|lrdivider [7]))) +// \ula_|i2s_intf_|Equal0~0_combout = (\ula_|i2s_intf_|lrdivider [6] & (!\ula_|i2s_intf_|lrdivider [8] & (\ula_|i2s_intf_|lrdivider [9] & \ula_|i2s_intf_|lrdivider [7]))) - .dataa(\ula_|i2s_intf_|lrdivider [8]), - .datab(\ula_|i2s_intf_|lrdivider [9]), - .datac(\ula_|i2s_intf_|lrdivider [6]), + .dataa(\ula_|i2s_intf_|lrdivider [6]), + .datab(\ula_|i2s_intf_|lrdivider [8]), + .datac(\ula_|i2s_intf_|lrdivider [9]), .datad(\ula_|i2s_intf_|lrdivider [7]), .cin(gnd), .combout(\ula_|i2s_intf_|Equal0~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|Equal0~0 .lut_mask = 16'h4000; +defparam \ula_|i2s_intf_|Equal0~0 .lut_mask = 16'h2000; defparam \ula_|i2s_intf_|Equal0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N30 +// Location: LCCOMB_X24_Y32_N30 cycloneive_lcell_comb \ula_|i2s_intf_|Equal0~2 ( // Equation(s): -// \ula_|i2s_intf_|Equal0~2_combout = (\ula_|i2s_intf_|Equal0~1_combout & (!\ula_|i2s_intf_|lrdivider [1] & (\ula_|i2s_intf_|mclk_r~_Duplicate_1_q & \ula_|i2s_intf_|Equal0~0_combout ))) +// \ula_|i2s_intf_|Equal0~2_combout = (!\ula_|i2s_intf_|lrdivider [1] & (\ula_|i2s_intf_|Equal0~1_combout & (\ula_|i2s_intf_|mclk_r~_Duplicate_1_q & \ula_|i2s_intf_|Equal0~0_combout ))) - .dataa(\ula_|i2s_intf_|Equal0~1_combout ), - .datab(\ula_|i2s_intf_|lrdivider [1]), + .dataa(\ula_|i2s_intf_|lrdivider [1]), + .datab(\ula_|i2s_intf_|Equal0~1_combout ), .datac(\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ), .datad(\ula_|i2s_intf_|Equal0~0_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|Equal0~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|Equal0~2 .lut_mask = 16'h2000; +defparam \ula_|i2s_intf_|Equal0~2 .lut_mask = 16'h4000; defparam \ula_|i2s_intf_|Equal0~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y22_N24 -cycloneive_lcell_comb \ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder ( -// Equation(s): -// \ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder_combout = \ula_|i2s_intf_|lrclk_r~0_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|lrclk_r~0_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder .lut_mask = 16'hFF00; -defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y22_N25 +// Location: FF_X23_Y31_N5 dffeas \ula_|i2s_intf_|lrclk_r~_Duplicate_2 ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder_combout ), + .d(\ula_|i2s_intf_|lrclk_r~0_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -56342,20 +56075,20 @@ defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_2 .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_2 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y22_N0 +// Location: LCCOMB_X23_Y31_N4 cycloneive_lcell_comb \ula_|i2s_intf_|lrclk_r~0 ( // Equation(s): // \ula_|i2s_intf_|lrclk_r~0_combout = \ula_|i2s_intf_|Equal0~2_combout $ (\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ) .dataa(gnd), .datab(\ula_|i2s_intf_|Equal0~2_combout ), - .datac(gnd), - .datad(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), + .datac(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|lrclk_r~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrclk_r~0 .lut_mask = 16'h33CC; +defparam \ula_|i2s_intf_|lrclk_r~0 .lut_mask = 16'h3C3C; defparam \ula_|i2s_intf_|lrclk_r~0 .sum_lutc_input = "datac"; // synopsys translate_on @@ -56397,7 +56130,7 @@ defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_1 .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y22_N0 +// Location: LCCOMB_X25_Y31_N0 cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[0]~5 ( // Equation(s): // \ula_|i2s_intf_|bitcount[0]~5_combout = !\ula_|i2s_intf_|bitcount [0] @@ -56415,10 +56148,27 @@ defparam \ula_|i2s_intf_|bitcount[0]~5 .lut_mask = 16'h3333; defparam \ula_|i2s_intf_|bitcount[0]~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y22_N11 +// Location: LCCOMB_X25_Y31_N26 +cycloneive_lcell_comb \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder ( +// Equation(s): +// \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder_combout = \ula_|i2s_intf_|bclk_r~1_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|i2s_intf_|bclk_r~1_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|bclk_r~_Duplicate_1feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder .lut_mask = 16'hFF00; +defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y31_N27 dffeas \ula_|i2s_intf_|bclk_r~_Duplicate_1 ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|bclk_r~1_combout ), + .d(\ula_|i2s_intf_|bclk_r~_Duplicate_1feeder_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -56434,24 +56184,24 @@ defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1 .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y22_N28 +// Location: LCCOMB_X25_Y31_N22 cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[4]~15 ( // Equation(s): -// \ula_|i2s_intf_|bitcount[4]~15_combout = (\ula_|i2s_intf_|Equal0~2_combout ) # ((\ula_|i2s_intf_|shiftreg[4]~1_combout & !\ula_|i2s_intf_|bclk_r~_Duplicate_1_q )) +// \ula_|i2s_intf_|bitcount[4]~15_combout = (\ula_|i2s_intf_|Equal0~2_combout ) # ((!\ula_|i2s_intf_|bclk_r~_Duplicate_1_q & \ula_|i2s_intf_|shiftreg[4]~1_combout )) - .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg[4]~1_combout ), + .dataa(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .datab(gnd), .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .datad(\ula_|i2s_intf_|shiftreg[4]~1_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|bitcount[4]~15_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[4]~15 .lut_mask = 16'hF0FC; +defparam \ula_|i2s_intf_|bitcount[4]~15 .lut_mask = 16'hF5F0; defparam \ula_|i2s_intf_|bitcount[4]~15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y22_N1 +// Location: FF_X25_Y31_N1 dffeas \ula_|i2s_intf_|bitcount[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|bitcount[0]~5_combout ), @@ -56470,25 +56220,25 @@ defparam \ula_|i2s_intf_|bitcount[0] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|bitcount[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y22_N2 +// Location: LCCOMB_X25_Y31_N2 cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[1]~7 ( // Equation(s): // \ula_|i2s_intf_|bitcount[1]~7_combout = (\ula_|i2s_intf_|bitcount [1] & (\ula_|i2s_intf_|bitcount[0]~6 & VCC)) # (!\ula_|i2s_intf_|bitcount [1] & (!\ula_|i2s_intf_|bitcount[0]~6 )) // \ula_|i2s_intf_|bitcount[1]~8 = CARRY((!\ula_|i2s_intf_|bitcount [1] & !\ula_|i2s_intf_|bitcount[0]~6 )) - .dataa(gnd), - .datab(\ula_|i2s_intf_|bitcount [1]), + .dataa(\ula_|i2s_intf_|bitcount [1]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\ula_|i2s_intf_|bitcount[0]~6 ), .combout(\ula_|i2s_intf_|bitcount[1]~7_combout ), .cout(\ula_|i2s_intf_|bitcount[1]~8 )); // synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[1]~7 .lut_mask = 16'hC303; +defparam \ula_|i2s_intf_|bitcount[1]~7 .lut_mask = 16'hA505; defparam \ula_|i2s_intf_|bitcount[1]~7 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y22_N3 +// Location: FF_X25_Y31_N3 dffeas \ula_|i2s_intf_|bitcount[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|bitcount[1]~7_combout ), @@ -56507,7 +56257,7 @@ defparam \ula_|i2s_intf_|bitcount[1] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|bitcount[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y22_N4 +// Location: LCCOMB_X25_Y31_N4 cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[2]~9 ( // Equation(s): // \ula_|i2s_intf_|bitcount[2]~9_combout = (\ula_|i2s_intf_|bitcount [2] & ((GND) # (!\ula_|i2s_intf_|bitcount[1]~8 ))) # (!\ula_|i2s_intf_|bitcount [2] & (\ula_|i2s_intf_|bitcount[1]~8 $ (GND))) @@ -56525,7 +56275,7 @@ defparam \ula_|i2s_intf_|bitcount[2]~9 .lut_mask = 16'h3CCF; defparam \ula_|i2s_intf_|bitcount[2]~9 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y22_N5 +// Location: FF_X25_Y31_N5 dffeas \ula_|i2s_intf_|bitcount[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|bitcount[2]~9_combout ), @@ -56544,7 +56294,7 @@ defparam \ula_|i2s_intf_|bitcount[2] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|bitcount[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y22_N6 +// Location: LCCOMB_X25_Y31_N6 cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[3]~11 ( // Equation(s): // \ula_|i2s_intf_|bitcount[3]~11_combout = (\ula_|i2s_intf_|bitcount [3] & (\ula_|i2s_intf_|bitcount[2]~10 & VCC)) # (!\ula_|i2s_intf_|bitcount [3] & (!\ula_|i2s_intf_|bitcount[2]~10 )) @@ -56562,7 +56312,7 @@ defparam \ula_|i2s_intf_|bitcount[3]~11 .lut_mask = 16'hA505; defparam \ula_|i2s_intf_|bitcount[3]~11 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y22_N7 +// Location: FF_X25_Y31_N7 dffeas \ula_|i2s_intf_|bitcount[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|bitcount[3]~11_combout ), @@ -56581,24 +56331,7 @@ defparam \ula_|i2s_intf_|bitcount[3] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|bitcount[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y22_N24 -cycloneive_lcell_comb \ula_|i2s_intf_|LessThan0~0 ( -// Equation(s): -// \ula_|i2s_intf_|LessThan0~0_combout = (\ula_|i2s_intf_|bitcount [3]) # (((\ula_|i2s_intf_|bitcount [2]) # (\ula_|i2s_intf_|bitcount [1])) # (!\ula_|i2s_intf_|bitcount [0])) - - .dataa(\ula_|i2s_intf_|bitcount [3]), - .datab(\ula_|i2s_intf_|bitcount [0]), - .datac(\ula_|i2s_intf_|bitcount [2]), - .datad(\ula_|i2s_intf_|bitcount [1]), - .cin(gnd), - .combout(\ula_|i2s_intf_|LessThan0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|LessThan0~0 .lut_mask = 16'hFFFB; -defparam \ula_|i2s_intf_|LessThan0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y22_N8 +// Location: LCCOMB_X25_Y31_N8 cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[4]~13 ( // Equation(s): // \ula_|i2s_intf_|bitcount[4]~13_combout = \ula_|i2s_intf_|bitcount [4] $ (\ula_|i2s_intf_|bitcount[3]~12 ) @@ -56615,7 +56348,7 @@ defparam \ula_|i2s_intf_|bitcount[4]~13 .lut_mask = 16'h3C3C; defparam \ula_|i2s_intf_|bitcount[4]~13 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y22_N9 +// Location: FF_X25_Y31_N9 dffeas \ula_|i2s_intf_|bitcount[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|bitcount[4]~13_combout ), @@ -56634,273 +56367,41 @@ defparam \ula_|i2s_intf_|bitcount[4] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|bitcount[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y22_N14 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~7 ( +// Location: LCCOMB_X25_Y31_N20 +cycloneive_lcell_comb \ula_|i2s_intf_|LessThan0~0 ( // Equation(s): -// \ula_|i2s_intf_|Add2~7_cout = CARRY(!\ula_|i2s_intf_|bdivider [0]) +// \ula_|i2s_intf_|LessThan0~0_combout = (\ula_|i2s_intf_|bitcount [1]) # (((\ula_|i2s_intf_|bitcount [2]) # (\ula_|i2s_intf_|bitcount [3])) # (!\ula_|i2s_intf_|bitcount [0])) - .dataa(\ula_|i2s_intf_|bdivider [0]), - .datab(gnd), - .datac(gnd), - .datad(vcc), + .dataa(\ula_|i2s_intf_|bitcount [1]), + .datab(\ula_|i2s_intf_|bitcount [0]), + .datac(\ula_|i2s_intf_|bitcount [2]), + .datad(\ula_|i2s_intf_|bitcount [3]), .cin(gnd), - .combout(), - .cout(\ula_|i2s_intf_|Add2~7_cout )); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~7 .lut_mask = 16'h0055; -defparam \ula_|i2s_intf_|Add2~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y22_N16 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~8 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~8_combout = (\ula_|i2s_intf_|bdivider [1] & (\ula_|i2s_intf_|Add2~7_cout & VCC)) # (!\ula_|i2s_intf_|bdivider [1] & (!\ula_|i2s_intf_|Add2~7_cout )) -// \ula_|i2s_intf_|Add2~9 = CARRY((!\ula_|i2s_intf_|bdivider [1] & !\ula_|i2s_intf_|Add2~7_cout )) - - .dataa(\ula_|i2s_intf_|bdivider [1]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|Add2~7_cout ), - .combout(\ula_|i2s_intf_|Add2~8_combout ), - .cout(\ula_|i2s_intf_|Add2~9 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~8 .lut_mask = 16'hA505; -defparam \ula_|i2s_intf_|Add2~8 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y22_N12 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~20 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~20_combout = (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|Add2~8_combout & ((!\ula_|i2s_intf_|Equal1~0_combout ) # (!\ula_|i2s_intf_|bdivider [0])))) - - .dataa(\ula_|i2s_intf_|bdivider [0]), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), - .datac(\ula_|i2s_intf_|Equal1~0_combout ), - .datad(\ula_|i2s_intf_|Add2~8_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|Add2~20_combout ), + .combout(\ula_|i2s_intf_|LessThan0~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|Add2~20 .lut_mask = 16'h1300; -defparam \ula_|i2s_intf_|Add2~20 .sum_lutc_input = "datac"; +defparam \ula_|i2s_intf_|LessThan0~0 .lut_mask = 16'hFFFB; +defparam \ula_|i2s_intf_|LessThan0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y22_N13 -dffeas \ula_|i2s_intf_|bdivider[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|Add2~20_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bdivider [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bdivider[1] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bdivider[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y22_N18 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~10 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~10_combout = (\ula_|i2s_intf_|bdivider [2] & (\ula_|i2s_intf_|Add2~9 $ (GND))) # (!\ula_|i2s_intf_|bdivider [2] & ((GND) # (!\ula_|i2s_intf_|Add2~9 ))) -// \ula_|i2s_intf_|Add2~11 = CARRY((!\ula_|i2s_intf_|Add2~9 ) # (!\ula_|i2s_intf_|bdivider [2])) - - .dataa(\ula_|i2s_intf_|bdivider [2]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|Add2~9 ), - .combout(\ula_|i2s_intf_|Add2~10_combout ), - .cout(\ula_|i2s_intf_|Add2~11 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~10 .lut_mask = 16'hA55F; -defparam \ula_|i2s_intf_|Add2~10 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y22_N16 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~17 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~17_combout = (!\ula_|i2s_intf_|shiftreg[4]~1_combout & (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~1_combout ) # (!\ula_|i2s_intf_|Add2~10_combout )))) - - .dataa(\ula_|i2s_intf_|Equal1~1_combout ), - .datab(\ula_|i2s_intf_|shiftreg[4]~1_combout ), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|Add2~10_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|Add2~17_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~17 .lut_mask = 16'h0203; -defparam \ula_|i2s_intf_|Add2~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y22_N17 -dffeas \ula_|i2s_intf_|bdivider[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|Add2~17_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bdivider [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bdivider[2] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bdivider[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y22_N20 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~12 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~12_combout = (\ula_|i2s_intf_|bdivider [3] & (\ula_|i2s_intf_|Add2~11 & VCC)) # (!\ula_|i2s_intf_|bdivider [3] & (!\ula_|i2s_intf_|Add2~11 )) -// \ula_|i2s_intf_|Add2~13 = CARRY((!\ula_|i2s_intf_|bdivider [3] & !\ula_|i2s_intf_|Add2~11 )) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|bdivider [3]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|Add2~11 ), - .combout(\ula_|i2s_intf_|Add2~12_combout ), - .cout(\ula_|i2s_intf_|Add2~13 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~12 .lut_mask = 16'hC303; -defparam \ula_|i2s_intf_|Add2~12 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y22_N2 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~19 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~19_combout = (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|Add2~12_combout & ((!\ula_|i2s_intf_|Equal1~0_combout ) # (!\ula_|i2s_intf_|bdivider [0])))) - - .dataa(\ula_|i2s_intf_|bdivider [0]), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), - .datac(\ula_|i2s_intf_|Equal1~0_combout ), - .datad(\ula_|i2s_intf_|Add2~12_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|Add2~19_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~19 .lut_mask = 16'h1300; -defparam \ula_|i2s_intf_|Add2~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y22_N3 -dffeas \ula_|i2s_intf_|bdivider[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|Add2~19_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bdivider [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bdivider[3] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bdivider[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y22_N22 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~14 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~14_combout = \ula_|i2s_intf_|Add2~13 $ (!\ula_|i2s_intf_|bdivider [4]) - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|bdivider [4]), - .cin(\ula_|i2s_intf_|Add2~13 ), - .combout(\ula_|i2s_intf_|Add2~14_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~14 .lut_mask = 16'hF00F; -defparam \ula_|i2s_intf_|Add2~14 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y22_N18 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~16 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~16_combout = (!\ula_|i2s_intf_|shiftreg[4]~1_combout & (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~1_combout ) # (!\ula_|i2s_intf_|Add2~14_combout )))) - - .dataa(\ula_|i2s_intf_|Equal1~1_combout ), - .datab(\ula_|i2s_intf_|shiftreg[4]~1_combout ), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|Add2~14_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|Add2~16_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~16 .lut_mask = 16'h0203; -defparam \ula_|i2s_intf_|Add2~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y22_N19 -dffeas \ula_|i2s_intf_|bdivider[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|Add2~16_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bdivider [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bdivider[4] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bdivider[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y22_N26 -cycloneive_lcell_comb \ula_|i2s_intf_|Equal1~0 ( -// Equation(s): -// \ula_|i2s_intf_|Equal1~0_combout = (!\ula_|i2s_intf_|bdivider [1] & (!\ula_|i2s_intf_|bdivider [3] & (\ula_|i2s_intf_|bdivider [2] & \ula_|i2s_intf_|bdivider [4]))) - - .dataa(\ula_|i2s_intf_|bdivider [1]), - .datab(\ula_|i2s_intf_|bdivider [3]), - .datac(\ula_|i2s_intf_|bdivider [2]), - .datad(\ula_|i2s_intf_|bdivider [4]), - .cin(gnd), - .combout(\ula_|i2s_intf_|Equal1~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Equal1~0 .lut_mask = 16'h1000; -defparam \ula_|i2s_intf_|Equal1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y22_N20 +// Location: LCCOMB_X25_Y31_N10 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[4]~1 ( // Equation(s): // \ula_|i2s_intf_|shiftreg[4]~1_combout = (\ula_|i2s_intf_|bdivider [0] & (\ula_|i2s_intf_|Equal1~0_combout & ((\ula_|i2s_intf_|LessThan0~0_combout ) # (!\ula_|i2s_intf_|bitcount [4])))) .dataa(\ula_|i2s_intf_|bdivider [0]), - .datab(\ula_|i2s_intf_|LessThan0~0_combout ), + .datab(\ula_|i2s_intf_|Equal1~0_combout ), .datac(\ula_|i2s_intf_|bitcount [4]), - .datad(\ula_|i2s_intf_|Equal1~0_combout ), + .datad(\ula_|i2s_intf_|LessThan0~0_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg[4]~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[4]~1 .lut_mask = 16'h8A00; +defparam \ula_|i2s_intf_|shiftreg[4]~1 .lut_mask = 16'h8808; defparam \ula_|i2s_intf_|shiftreg[4]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y22_N12 +// Location: LCCOMB_X24_Y31_N12 cycloneive_lcell_comb \ula_|i2s_intf_|Add2~18 ( // Equation(s): // \ula_|i2s_intf_|Add2~18_combout = (!\ula_|i2s_intf_|Equal0~2_combout & (!\ula_|i2s_intf_|shiftreg[4]~1_combout & ((\ula_|i2s_intf_|Equal1~0_combout ) # (!\ula_|i2s_intf_|bdivider [0])))) @@ -56917,7 +56418,7 @@ defparam \ula_|i2s_intf_|Add2~18 .lut_mask = 16'h1101; defparam \ula_|i2s_intf_|Add2~18 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y22_N13 +// Location: FF_X24_Y31_N13 dffeas \ula_|i2s_intf_|bdivider[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|Add2~18_combout ), @@ -56936,54 +56437,303 @@ defparam \ula_|i2s_intf_|bdivider[0] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|bdivider[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y22_N22 -cycloneive_lcell_comb \ula_|i2s_intf_|Equal1~1 ( +// Location: LCCOMB_X24_Y31_N2 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~7 ( // Equation(s): -// \ula_|i2s_intf_|Equal1~1_combout = (\ula_|i2s_intf_|bdivider [0] & \ula_|i2s_intf_|Equal1~0_combout ) +// \ula_|i2s_intf_|Add2~7_cout = CARRY(!\ula_|i2s_intf_|bdivider [0]) + + .dataa(\ula_|i2s_intf_|bdivider [0]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(), + .cout(\ula_|i2s_intf_|Add2~7_cout )); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~7 .lut_mask = 16'h0055; +defparam \ula_|i2s_intf_|Add2~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y31_N4 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~8 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~8_combout = (\ula_|i2s_intf_|bdivider [1] & (\ula_|i2s_intf_|Add2~7_cout & VCC)) # (!\ula_|i2s_intf_|bdivider [1] & (!\ula_|i2s_intf_|Add2~7_cout )) +// \ula_|i2s_intf_|Add2~9 = CARRY((!\ula_|i2s_intf_|bdivider [1] & !\ula_|i2s_intf_|Add2~7_cout )) + + .dataa(\ula_|i2s_intf_|bdivider [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|Add2~7_cout ), + .combout(\ula_|i2s_intf_|Add2~8_combout ), + .cout(\ula_|i2s_intf_|Add2~9 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~8 .lut_mask = 16'hA505; +defparam \ula_|i2s_intf_|Add2~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y31_N22 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~20 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~20_combout = (\ula_|i2s_intf_|Add2~8_combout & (!\ula_|i2s_intf_|Equal0~2_combout & ((!\ula_|i2s_intf_|Equal1~0_combout ) # (!\ula_|i2s_intf_|bdivider [0])))) + + .dataa(\ula_|i2s_intf_|bdivider [0]), + .datab(\ula_|i2s_intf_|Add2~8_combout ), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|Equal1~0_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|Add2~20_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~20 .lut_mask = 16'h040C; +defparam \ula_|i2s_intf_|Add2~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y31_N23 +dffeas \ula_|i2s_intf_|bdivider[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|Add2~20_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bdivider [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bdivider[1] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bdivider[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y31_N6 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~10 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~10_combout = (\ula_|i2s_intf_|bdivider [2] & (\ula_|i2s_intf_|Add2~9 $ (GND))) # (!\ula_|i2s_intf_|bdivider [2] & ((GND) # (!\ula_|i2s_intf_|Add2~9 ))) +// \ula_|i2s_intf_|Add2~11 = CARRY((!\ula_|i2s_intf_|Add2~9 ) # (!\ula_|i2s_intf_|bdivider [2])) + + .dataa(\ula_|i2s_intf_|bdivider [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|Add2~9 ), + .combout(\ula_|i2s_intf_|Add2~10_combout ), + .cout(\ula_|i2s_intf_|Add2~11 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~10 .lut_mask = 16'hA55F; +defparam \ula_|i2s_intf_|Add2~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y31_N26 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~17 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~17_combout = (!\ula_|i2s_intf_|Equal0~2_combout & (!\ula_|i2s_intf_|shiftreg[4]~1_combout & ((\ula_|i2s_intf_|Equal1~1_combout ) # (!\ula_|i2s_intf_|Add2~10_combout )))) + + .dataa(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(\ula_|i2s_intf_|Equal1~1_combout ), + .datac(\ula_|i2s_intf_|shiftreg[4]~1_combout ), + .datad(\ula_|i2s_intf_|Add2~10_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|Add2~17_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~17 .lut_mask = 16'h0405; +defparam \ula_|i2s_intf_|Add2~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y31_N27 +dffeas \ula_|i2s_intf_|bdivider[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|Add2~17_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bdivider [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bdivider[2] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bdivider[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y31_N8 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~12 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~12_combout = (\ula_|i2s_intf_|bdivider [3] & (\ula_|i2s_intf_|Add2~11 & VCC)) # (!\ula_|i2s_intf_|bdivider [3] & (!\ula_|i2s_intf_|Add2~11 )) +// \ula_|i2s_intf_|Add2~13 = CARRY((!\ula_|i2s_intf_|bdivider [3] & !\ula_|i2s_intf_|Add2~11 )) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|bdivider [3]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|Add2~11 ), + .combout(\ula_|i2s_intf_|Add2~12_combout ), + .cout(\ula_|i2s_intf_|Add2~13 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~12 .lut_mask = 16'hC303; +defparam \ula_|i2s_intf_|Add2~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y31_N0 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~19 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~19_combout = (\ula_|i2s_intf_|Add2~12_combout & (!\ula_|i2s_intf_|Equal0~2_combout & ((!\ula_|i2s_intf_|Equal1~0_combout ) # (!\ula_|i2s_intf_|bdivider [0])))) + + .dataa(\ula_|i2s_intf_|bdivider [0]), + .datab(\ula_|i2s_intf_|Add2~12_combout ), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|Equal1~0_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|Add2~19_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~19 .lut_mask = 16'h040C; +defparam \ula_|i2s_intf_|Add2~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y31_N1 +dffeas \ula_|i2s_intf_|bdivider[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|Add2~19_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bdivider [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bdivider[3] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bdivider[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y31_N10 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~14 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~14_combout = \ula_|i2s_intf_|Add2~13 $ (!\ula_|i2s_intf_|bdivider [4]) .dataa(gnd), .datab(gnd), - .datac(\ula_|i2s_intf_|bdivider [0]), - .datad(\ula_|i2s_intf_|Equal1~0_combout ), + .datac(gnd), + .datad(\ula_|i2s_intf_|bdivider [4]), + .cin(\ula_|i2s_intf_|Add2~13 ), + .combout(\ula_|i2s_intf_|Add2~14_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~14 .lut_mask = 16'hF00F; +defparam \ula_|i2s_intf_|Add2~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y31_N28 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~16 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~16_combout = (!\ula_|i2s_intf_|Equal0~2_combout & (!\ula_|i2s_intf_|shiftreg[4]~1_combout & ((\ula_|i2s_intf_|Equal1~1_combout ) # (!\ula_|i2s_intf_|Add2~14_combout )))) + + .dataa(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(\ula_|i2s_intf_|Equal1~1_combout ), + .datac(\ula_|i2s_intf_|shiftreg[4]~1_combout ), + .datad(\ula_|i2s_intf_|Add2~14_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|Add2~16_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~16 .lut_mask = 16'h0405; +defparam \ula_|i2s_intf_|Add2~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y31_N29 +dffeas \ula_|i2s_intf_|bdivider[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|Add2~16_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bdivider [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bdivider[4] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bdivider[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y31_N20 +cycloneive_lcell_comb \ula_|i2s_intf_|Equal1~0 ( +// Equation(s): +// \ula_|i2s_intf_|Equal1~0_combout = (!\ula_|i2s_intf_|bdivider [1] & (\ula_|i2s_intf_|bdivider [4] & (\ula_|i2s_intf_|bdivider [2] & !\ula_|i2s_intf_|bdivider [3]))) + + .dataa(\ula_|i2s_intf_|bdivider [1]), + .datab(\ula_|i2s_intf_|bdivider [4]), + .datac(\ula_|i2s_intf_|bdivider [2]), + .datad(\ula_|i2s_intf_|bdivider [3]), + .cin(gnd), + .combout(\ula_|i2s_intf_|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Equal1~0 .lut_mask = 16'h0040; +defparam \ula_|i2s_intf_|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y31_N14 +cycloneive_lcell_comb \ula_|i2s_intf_|Equal1~1 ( +// Equation(s): +// \ula_|i2s_intf_|Equal1~1_combout = (\ula_|i2s_intf_|Equal1~0_combout & \ula_|i2s_intf_|bdivider [0]) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|Equal1~0_combout ), + .datac(gnd), + .datad(\ula_|i2s_intf_|bdivider [0]), .cin(gnd), .combout(\ula_|i2s_intf_|Equal1~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|Equal1~1 .lut_mask = 16'hF000; +defparam \ula_|i2s_intf_|Equal1~1 .lut_mask = 16'hCC00; defparam \ula_|i2s_intf_|Equal1~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y22_N14 +// Location: LCCOMB_X25_Y31_N18 cycloneive_lcell_comb \ula_|i2s_intf_|bclk_r~0 ( // Equation(s): // \ula_|i2s_intf_|bclk_r~0_combout = \ula_|i2s_intf_|bclk_r~_Duplicate_1_q $ (((\ula_|i2s_intf_|LessThan0~0_combout ) # (!\ula_|i2s_intf_|bitcount [4]))) - .dataa(gnd), + .dataa(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), .datab(\ula_|i2s_intf_|LessThan0~0_combout ), .datac(\ula_|i2s_intf_|bitcount [4]), - .datad(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|bclk_r~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|bclk_r~0 .lut_mask = 16'h30CF; +defparam \ula_|i2s_intf_|bclk_r~0 .lut_mask = 16'h6565; defparam \ula_|i2s_intf_|bclk_r~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y22_N10 +// Location: LCCOMB_X25_Y31_N24 cycloneive_lcell_comb \ula_|i2s_intf_|bclk_r~1 ( // Equation(s): -// \ula_|i2s_intf_|bclk_r~1_combout = (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~1_combout & (\ula_|i2s_intf_|bclk_r~0_combout )) # (!\ula_|i2s_intf_|Equal1~1_combout & ((\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ))))) +// \ula_|i2s_intf_|bclk_r~1_combout = (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~1_combout & ((\ula_|i2s_intf_|bclk_r~0_combout ))) # (!\ula_|i2s_intf_|Equal1~1_combout & (\ula_|i2s_intf_|bclk_r~_Duplicate_1_q )))) .dataa(\ula_|i2s_intf_|Equal1~1_combout ), - .datab(\ula_|i2s_intf_|bclk_r~0_combout ), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), .datac(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|bclk_r~0_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|bclk_r~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|bclk_r~1 .lut_mask = 16'h00D8; +defparam \ula_|i2s_intf_|bclk_r~1 .lut_mask = 16'h3210; defparam \ula_|i2s_intf_|bclk_r~1 .sum_lutc_input = "datac"; // synopsys translate_on @@ -57006,61 +56756,44 @@ defparam \ula_|i2s_intf_|bclk_r .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|bclk_r .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y19_N24 -cycloneive_lcell_comb \ula_|pcm_outl[13]~feeder ( -// Equation(s): -// \ula_|pcm_outl[13]~feeder_combout = \D[3]~96_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\D[3]~96_combout ), - .cin(gnd), - .combout(\ula_|pcm_outl[13]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|pcm_outl[13]~feeder .lut_mask = 16'hFF00; -defparam \ula_|pcm_outl[13]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N2 +// Location: LCCOMB_X29_Y11_N14 cycloneive_lcell_comb \ula_|always0~2 ( // Equation(s): -// \ula_|always0~2_combout = (\z80_|memory_ifc_|nWR_out~0_combout & (!\z80_|memory_ifc_|nRD_out~2_combout & \z80_|resets_|SYNTHESIZED_WIRE_12~q )) +// \ula_|always0~2_combout = (!\z80_|memory_ifc_|nRD_out~2_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \z80_|memory_ifc_|nWR_out~0_combout )) - .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), - .datab(\z80_|memory_ifc_|nRD_out~2_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(gnd), + .dataa(\z80_|memory_ifc_|nRD_out~2_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(gnd), + .datad(\z80_|memory_ifc_|nWR_out~0_combout ), .cin(gnd), .combout(\ula_|always0~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|always0~2 .lut_mask = 16'h2020; +defparam \ula_|always0~2 .lut_mask = 16'h4400; defparam \ula_|always0~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y12_N20 +// Location: LCCOMB_X29_Y11_N26 cycloneive_lcell_comb \ula_|always0~3 ( // Equation(s): -// \ula_|always0~3_combout = (!\z80_|address_pins_|DFFE_apin_latch [0] & (\z80_|memory_ifc_|nIORQ_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \ula_|always0~2_combout ))) +// \ula_|always0~3_combout = (\z80_|memory_ifc_|nIORQ_out~0_combout & (!\z80_|address_pins_|DFFE_apin_latch [0] & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \ula_|always0~2_combout ))) - .dataa(\z80_|address_pins_|DFFE_apin_latch [0]), - .datab(\z80_|memory_ifc_|nIORQ_out~0_combout ), + .dataa(\z80_|memory_ifc_|nIORQ_out~0_combout ), + .datab(\z80_|address_pins_|DFFE_apin_latch [0]), .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .datad(\ula_|always0~2_combout ), .cin(gnd), .combout(\ula_|always0~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|always0~3 .lut_mask = 16'h4000; +defparam \ula_|always0~3 .lut_mask = 16'h2000; defparam \ula_|always0~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y19_N25 -dffeas \ula_|pcm_outl[13] ( +// Location: FF_X31_Y10_N31 +dffeas \ula_|pcm_outl[14] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|pcm_outl[13]~feeder_combout ), + .d(\D[4]~76_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -57069,27 +56802,27 @@ dffeas \ula_|pcm_outl[13] ( .ena(\ula_|always0~3_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\ula_|pcm_outl [13]), + .q(\ula_|pcm_outl [14]), .prn(vcc)); // synopsys translate_off -defparam \ula_|pcm_outl[13] .is_wysiwyg = "true"; -defparam \ula_|pcm_outl[13] .power_up = "low"; +defparam \ula_|pcm_outl[14] .is_wysiwyg = "true"; +defparam \ula_|pcm_outl[14] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y22_N26 +// Location: LCCOMB_X25_Y31_N16 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[0]~19 ( // Equation(s): // \ula_|i2s_intf_|shiftreg[0]~19_combout = (\ula_|i2s_intf_|Equal1~1_combout & (!\ula_|i2s_intf_|bclk_r~_Duplicate_1_q & ((\ula_|i2s_intf_|LessThan0~0_combout ) # (!\ula_|i2s_intf_|bitcount [4])))) .dataa(\ula_|i2s_intf_|Equal1~1_combout ), - .datab(\ula_|i2s_intf_|LessThan0~0_combout ), - .datac(\ula_|i2s_intf_|bitcount [4]), - .datad(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .datab(\ula_|i2s_intf_|bitcount [4]), + .datac(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .datad(\ula_|i2s_intf_|LessThan0~0_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg[0]~19_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[0]~19 .lut_mask = 16'h008A; +defparam \ula_|i2s_intf_|shiftreg[0]~19 .lut_mask = 16'h0A02; defparam \ula_|i2s_intf_|shiftreg[0]~19 .sum_lutc_input = "datac"; // synopsys translate_on @@ -57103,25 +56836,25 @@ defparam \AUD_ADCDAT~input .bus_hold = "false"; defparam \AUD_ADCDAT~input .simulate_z_as = "z"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N20 +// Location: LCCOMB_X24_Y31_N18 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[0]~20 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg[0]~20_combout = (\ula_|i2s_intf_|shiftreg[0]~19_combout & ((\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|shiftreg [0])) # (!\ula_|i2s_intf_|Equal0~2_combout & ((\AUD_ADCDAT~input_o ))))) # -// (!\ula_|i2s_intf_|shiftreg[0]~19_combout & (((\ula_|i2s_intf_|shiftreg [0])))) +// \ula_|i2s_intf_|shiftreg[0]~20_combout = (\ula_|i2s_intf_|Equal0~2_combout & (((\ula_|i2s_intf_|shiftreg [0])))) # (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|shiftreg[0]~19_combout & ((\AUD_ADCDAT~input_o ))) # +// (!\ula_|i2s_intf_|shiftreg[0]~19_combout & (\ula_|i2s_intf_|shiftreg [0])))) - .dataa(\ula_|i2s_intf_|shiftreg[0]~19_combout ), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .dataa(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(\ula_|i2s_intf_|shiftreg[0]~19_combout ), .datac(\ula_|i2s_intf_|shiftreg [0]), .datad(\AUD_ADCDAT~input_o ), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg[0]~20_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[0]~20 .lut_mask = 16'hF2D0; +defparam \ula_|i2s_intf_|shiftreg[0]~20 .lut_mask = 16'hF4B0; defparam \ula_|i2s_intf_|shiftreg[0]~20 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N21 +// Location: FF_X24_Y31_N19 dffeas \ula_|i2s_intf_|shiftreg[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg[0]~20_combout ), @@ -57140,41 +56873,41 @@ defparam \ula_|i2s_intf_|shiftreg[0] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N26 +// Location: LCCOMB_X23_Y31_N26 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~18 ( // Equation(s): // \ula_|i2s_intf_|shiftreg~18_combout = (\ula_|i2s_intf_|shiftreg [0] & !\ula_|i2s_intf_|Equal0~2_combout ) .dataa(gnd), .datab(\ula_|i2s_intf_|shiftreg [0]), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~18_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~18 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~18 .lut_mask = 16'h0C0C; defparam \ula_|i2s_intf_|shiftreg~18 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y22_N30 +// Location: LCCOMB_X25_Y31_N28 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[4]~2 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg[4]~2_combout = (\ula_|i2s_intf_|Equal0~2_combout ) # ((\ula_|i2s_intf_|shiftreg[4]~1_combout & \ula_|i2s_intf_|bclk_r~_Duplicate_1_q )) +// \ula_|i2s_intf_|shiftreg[4]~2_combout = (\ula_|i2s_intf_|Equal0~2_combout ) # ((\ula_|i2s_intf_|bclk_r~_Duplicate_1_q & \ula_|i2s_intf_|shiftreg[4]~1_combout )) - .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg[4]~1_combout ), + .dataa(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .datab(gnd), .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .datad(\ula_|i2s_intf_|shiftreg[4]~1_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg[4]~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[4]~2 .lut_mask = 16'hFCF0; +defparam \ula_|i2s_intf_|shiftreg[4]~2 .lut_mask = 16'hFAF0; defparam \ula_|i2s_intf_|shiftreg[4]~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N27 +// Location: FF_X23_Y31_N27 dffeas \ula_|i2s_intf_|shiftreg[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~18_combout ), @@ -57193,24 +56926,24 @@ defparam \ula_|i2s_intf_|shiftreg[1] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N24 +// Location: LCCOMB_X23_Y31_N12 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~17 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~17_combout = (\ula_|i2s_intf_|shiftreg [1] & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|shiftreg~17_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [1]) .dataa(gnd), - .datab(gnd), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), .datac(\ula_|i2s_intf_|shiftreg [1]), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~17_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~17 .lut_mask = 16'h00F0; +defparam \ula_|i2s_intf_|shiftreg~17 .lut_mask = 16'h3030; defparam \ula_|i2s_intf_|shiftreg~17 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N25 +// Location: FF_X23_Y31_N13 dffeas \ula_|i2s_intf_|shiftreg[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~17_combout ), @@ -57229,24 +56962,24 @@ defparam \ula_|i2s_intf_|shiftreg[2] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N18 +// Location: LCCOMB_X23_Y31_N22 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~16 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~16_combout = (\ula_|i2s_intf_|shiftreg [2] & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|shiftreg~16_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [2]) .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg [2]), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(gnd), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|shiftreg [2]), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~16_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~16 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~16 .lut_mask = 16'h0F00; defparam \ula_|i2s_intf_|shiftreg~16 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N19 +// Location: FF_X23_Y31_N23 dffeas \ula_|i2s_intf_|shiftreg[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~16_combout ), @@ -57265,24 +56998,24 @@ defparam \ula_|i2s_intf_|shiftreg[3] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N0 +// Location: LCCOMB_X23_Y31_N0 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~15 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~15_combout = (\ula_|i2s_intf_|shiftreg [3] & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|shiftreg~15_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [3]) .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg [3]), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|shiftreg [3]), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~15_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~15 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~15 .lut_mask = 16'h3030; defparam \ula_|i2s_intf_|shiftreg~15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N1 +// Location: FF_X23_Y31_N1 dffeas \ula_|i2s_intf_|shiftreg[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~15_combout ), @@ -57301,24 +57034,24 @@ defparam \ula_|i2s_intf_|shiftreg[4] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N10 +// Location: LCCOMB_X23_Y31_N14 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~14 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~14_combout = (\ula_|i2s_intf_|shiftreg [4] & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|shiftreg~14_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [4]) .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg [4]), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(gnd), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|shiftreg [4]), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~14_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~14 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~14 .lut_mask = 16'h0F00; defparam \ula_|i2s_intf_|shiftreg~14 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N11 +// Location: FF_X23_Y31_N15 dffeas \ula_|i2s_intf_|shiftreg[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~14_combout ), @@ -57337,24 +57070,24 @@ defparam \ula_|i2s_intf_|shiftreg[5] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N16 +// Location: LCCOMB_X23_Y31_N24 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~13 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~13_combout = (\ula_|i2s_intf_|shiftreg [5] & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|shiftreg~13_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [5]) - .dataa(\ula_|i2s_intf_|shiftreg [5]), - .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .dataa(gnd), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|shiftreg [5]), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~13_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~13 .lut_mask = 16'h00AA; +defparam \ula_|i2s_intf_|shiftreg~13 .lut_mask = 16'h3030; defparam \ula_|i2s_intf_|shiftreg~13 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N17 +// Location: FF_X23_Y31_N25 dffeas \ula_|i2s_intf_|shiftreg[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~13_combout ), @@ -57373,24 +57106,24 @@ defparam \ula_|i2s_intf_|shiftreg[6] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N30 +// Location: LCCOMB_X23_Y31_N30 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~12 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~12_combout = (\ula_|i2s_intf_|shiftreg [6] & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|shiftreg~12_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [6]) .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg [6]), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(gnd), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|shiftreg [6]), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~12_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~12 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~12 .lut_mask = 16'h0F00; defparam \ula_|i2s_intf_|shiftreg~12 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N31 +// Location: FF_X23_Y31_N31 dffeas \ula_|i2s_intf_|shiftreg[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~12_combout ), @@ -57409,24 +57142,24 @@ defparam \ula_|i2s_intf_|shiftreg[7] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N28 +// Location: LCCOMB_X23_Y31_N20 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~11 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~11_combout = (\ula_|i2s_intf_|shiftreg [7] & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|shiftreg~11_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [7]) .dataa(gnd), - .datab(gnd), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), .datac(\ula_|i2s_intf_|shiftreg [7]), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~11_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~11 .lut_mask = 16'h00F0; +defparam \ula_|i2s_intf_|shiftreg~11 .lut_mask = 16'h3030; defparam \ula_|i2s_intf_|shiftreg~11 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N29 +// Location: FF_X23_Y31_N21 dffeas \ula_|i2s_intf_|shiftreg[8] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~11_combout ), @@ -57445,24 +57178,24 @@ defparam \ula_|i2s_intf_|shiftreg[8] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[8] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N22 +// Location: LCCOMB_X23_Y31_N6 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~10 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~10_combout = (\ula_|i2s_intf_|shiftreg [8] & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|shiftreg~10_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [8]) .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg [8]), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(gnd), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|shiftreg [8]), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~10_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~10 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~10 .lut_mask = 16'h0F00; defparam \ula_|i2s_intf_|shiftreg~10 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N23 +// Location: FF_X23_Y31_N7 dffeas \ula_|i2s_intf_|shiftreg[9] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~10_combout ), @@ -57481,24 +57214,24 @@ defparam \ula_|i2s_intf_|shiftreg[9] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[9] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N12 +// Location: LCCOMB_X23_Y31_N16 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~9 ( // Equation(s): // \ula_|i2s_intf_|shiftreg~9_combout = (\ula_|i2s_intf_|shiftreg [9] & !\ula_|i2s_intf_|Equal0~2_combout ) - .dataa(gnd), + .dataa(\ula_|i2s_intf_|shiftreg [9]), .datab(gnd), - .datac(\ula_|i2s_intf_|shiftreg [9]), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~9_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~9 .lut_mask = 16'h00F0; +defparam \ula_|i2s_intf_|shiftreg~9 .lut_mask = 16'h0A0A; defparam \ula_|i2s_intf_|shiftreg~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N13 +// Location: FF_X23_Y31_N17 dffeas \ula_|i2s_intf_|shiftreg[10] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~9_combout ), @@ -57517,24 +57250,24 @@ defparam \ula_|i2s_intf_|shiftreg[10] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[10] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N2 +// Location: LCCOMB_X23_Y31_N18 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~8 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~8_combout = (\ula_|i2s_intf_|shiftreg [10] & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|shiftreg~8_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [10]) - .dataa(\ula_|i2s_intf_|shiftreg [10]), + .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|shiftreg [10]), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~8_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~8 .lut_mask = 16'h00AA; +defparam \ula_|i2s_intf_|shiftreg~8 .lut_mask = 16'h0F00; defparam \ula_|i2s_intf_|shiftreg~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N3 +// Location: FF_X23_Y31_N19 dffeas \ula_|i2s_intf_|shiftreg[11] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~8_combout ), @@ -57553,24 +57286,24 @@ defparam \ula_|i2s_intf_|shiftreg[11] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[11] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N8 +// Location: LCCOMB_X23_Y31_N28 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~7 ( // Equation(s): // \ula_|i2s_intf_|shiftreg~7_combout = (\ula_|i2s_intf_|shiftreg [11] & !\ula_|i2s_intf_|Equal0~2_combout ) .dataa(gnd), .datab(\ula_|i2s_intf_|shiftreg [11]), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~7_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~7 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~7 .lut_mask = 16'h0C0C; defparam \ula_|i2s_intf_|shiftreg~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N9 +// Location: FF_X23_Y31_N29 dffeas \ula_|i2s_intf_|shiftreg[12] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~7_combout ), @@ -57589,62 +57322,25 @@ defparam \ula_|i2s_intf_|shiftreg[12] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[12] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y22_N30 -cycloneive_lcell_comb \ula_|i2s_intf_|PCM_INR[14]~0 ( -// Equation(s): -// \ula_|i2s_intf_|PCM_INR[14]~0_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & (\ula_|i2s_intf_|shiftreg [14])) # (!\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & ((\ula_|i2s_intf_|PCM_INR [14]))))) # -// (!\ula_|i2s_intf_|Equal0~2_combout & (((\ula_|i2s_intf_|PCM_INR [14])))) - - .dataa(\ula_|i2s_intf_|shiftreg [14]), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), - .datac(\ula_|i2s_intf_|PCM_INR [14]), - .datad(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), - .cin(gnd), - .combout(\ula_|i2s_intf_|PCM_INR[14]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|PCM_INR[14]~0 .lut_mask = 16'hB8F0; -defparam \ula_|i2s_intf_|PCM_INR[14]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y22_N31 -dffeas \ula_|i2s_intf_|PCM_INR[14] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|PCM_INR[14]~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|PCM_INR [14]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|PCM_INR[14] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|PCM_INR[14] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y22_N28 +// Location: LCCOMB_X24_Y31_N30 cycloneive_lcell_comb \ula_|i2s_intf_|PCM_INL[14]~0 ( // Equation(s): -// \ula_|i2s_intf_|PCM_INL[14]~0_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & ((\ula_|i2s_intf_|PCM_INL [14]))) # (!\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & (\ula_|i2s_intf_|shiftreg [14])))) # +// \ula_|i2s_intf_|PCM_INL[14]~0_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & (\ula_|i2s_intf_|PCM_INL [14])) # (!\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & ((\ula_|i2s_intf_|shiftreg [14]))))) # // (!\ula_|i2s_intf_|Equal0~2_combout & (((\ula_|i2s_intf_|PCM_INL [14])))) - .dataa(\ula_|i2s_intf_|shiftreg [14]), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .dataa(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), .datac(\ula_|i2s_intf_|PCM_INL [14]), - .datad(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), + .datad(\ula_|i2s_intf_|shiftreg [14]), .cin(gnd), .combout(\ula_|i2s_intf_|PCM_INL[14]~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|PCM_INL[14]~0 .lut_mask = 16'hF0B8; +defparam \ula_|i2s_intf_|PCM_INL[14]~0 .lut_mask = 16'hF2D0; defparam \ula_|i2s_intf_|PCM_INL[14]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y22_N29 +// Location: FF_X24_Y31_N31 dffeas \ula_|i2s_intf_|PCM_INL[14] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|PCM_INL[14]~0_combout ), @@ -57663,15 +57359,52 @@ defparam \ula_|i2s_intf_|PCM_INL[14] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|PCM_INL[14] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y22_N6 +// Location: LCCOMB_X24_Y31_N16 +cycloneive_lcell_comb \ula_|i2s_intf_|PCM_INR[14]~0 ( +// Equation(s): +// \ula_|i2s_intf_|PCM_INR[14]~0_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & ((\ula_|i2s_intf_|shiftreg [14]))) # (!\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & (\ula_|i2s_intf_|PCM_INR [14])))) # +// (!\ula_|i2s_intf_|Equal0~2_combout & (((\ula_|i2s_intf_|PCM_INR [14])))) + + .dataa(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), + .datac(\ula_|i2s_intf_|PCM_INR [14]), + .datad(\ula_|i2s_intf_|shiftreg [14]), + .cin(gnd), + .combout(\ula_|i2s_intf_|PCM_INR[14]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|PCM_INR[14]~0 .lut_mask = 16'hF870; +defparam \ula_|i2s_intf_|PCM_INR[14]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y31_N17 +dffeas \ula_|i2s_intf_|PCM_INR[14] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|PCM_INR[14]~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|PCM_INR [14]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|PCM_INR[14] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|PCM_INR[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y31_N24 cycloneive_lcell_comb \ula_|pcm_outr~0 ( // Equation(s): -// \ula_|pcm_outr~0_combout = (\ula_|i2s_intf_|PCM_INR [14]) # (\ula_|i2s_intf_|PCM_INL [14]) +// \ula_|pcm_outr~0_combout = (\ula_|i2s_intf_|PCM_INL [14]) # (\ula_|i2s_intf_|PCM_INR [14]) .dataa(gnd), .datab(gnd), - .datac(\ula_|i2s_intf_|PCM_INR [14]), - .datad(\ula_|i2s_intf_|PCM_INL [14]), + .datac(\ula_|i2s_intf_|PCM_INL [14]), + .datad(\ula_|i2s_intf_|PCM_INR [14]), .cin(gnd), .combout(\ula_|pcm_outr~0_combout ), .cout()); @@ -57680,7 +57413,7 @@ defparam \ula_|pcm_outr~0 .lut_mask = 16'hFFF0; defparam \ula_|pcm_outr~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y22_N7 +// Location: FF_X24_Y31_N25 dffeas \ula_|pcm_outl[12] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\ula_|pcm_outr~0_combout ), @@ -57699,24 +57432,24 @@ defparam \ula_|pcm_outl[12] .is_wysiwyg = "true"; defparam \ula_|pcm_outl[12] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N14 +// Location: LCCOMB_X23_Y31_N10 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~6 ( // Equation(s): // \ula_|i2s_intf_|shiftreg~6_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|pcm_outl [12]))) # (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|shiftreg [12])) .dataa(gnd), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), - .datac(\ula_|i2s_intf_|shiftreg [12]), + .datab(\ula_|i2s_intf_|shiftreg [12]), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), .datad(\ula_|pcm_outl [12]), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~6_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~6 .lut_mask = 16'hFC30; +defparam \ula_|i2s_intf_|shiftreg~6 .lut_mask = 16'hFC0C; defparam \ula_|i2s_intf_|shiftreg~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N15 +// Location: FF_X23_Y31_N11 dffeas \ula_|i2s_intf_|shiftreg[13] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~6_combout ), @@ -57735,24 +57468,43 @@ defparam \ula_|i2s_intf_|shiftreg[13] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[13] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N4 +// Location: FF_X23_Y14_N9 +dffeas \ula_|pcm_outl[13] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\D[3]~74_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|always0~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|pcm_outl [13]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|pcm_outl[13] .is_wysiwyg = "true"; +defparam \ula_|pcm_outl[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y31_N8 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~5 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~5_combout = (\ula_|i2s_intf_|Equal0~2_combout & (\ula_|pcm_outl [13])) # (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|shiftreg [13]))) +// \ula_|i2s_intf_|shiftreg~5_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|pcm_outl [13]))) # (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|shiftreg [13])) - .dataa(gnd), - .datab(\ula_|pcm_outl [13]), - .datac(\ula_|i2s_intf_|shiftreg [13]), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .dataa(\ula_|i2s_intf_|shiftreg [13]), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(gnd), + .datad(\ula_|pcm_outl [13]), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~5_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~5 .lut_mask = 16'hCCF0; +defparam \ula_|i2s_intf_|shiftreg~5 .lut_mask = 16'hEE22; defparam \ula_|i2s_intf_|shiftreg~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N5 +// Location: FF_X23_Y31_N9 dffeas \ula_|i2s_intf_|shiftreg[14] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~5_combout ), @@ -57771,43 +57523,24 @@ defparam \ula_|i2s_intf_|shiftreg[14] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[14] .power_up = "low"; // synopsys translate_on -// Location: FF_X29_Y14_N31 -dffeas \ula_|pcm_outl[14] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\D[4]~98_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|always0~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|pcm_outl [14]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|pcm_outl[14] .is_wysiwyg = "true"; -defparam \ula_|pcm_outl[14] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y22_N4 +// Location: LCCOMB_X23_Y31_N2 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~4 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~4_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|pcm_outl [14]))) # (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|shiftreg [14])) +// \ula_|i2s_intf_|shiftreg~4_combout = (\ula_|i2s_intf_|Equal0~2_combout & (\ula_|pcm_outl [14])) # (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|shiftreg [14]))) - .dataa(\ula_|i2s_intf_|shiftreg [14]), - .datab(gnd), - .datac(\ula_|pcm_outl [14]), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .dataa(\ula_|pcm_outl [14]), + .datab(\ula_|i2s_intf_|shiftreg [14]), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~4_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~4 .lut_mask = 16'hF0AA; +defparam \ula_|i2s_intf_|shiftreg~4 .lut_mask = 16'hACAC; defparam \ula_|i2s_intf_|shiftreg~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y22_N5 +// Location: FF_X23_Y31_N3 dffeas \ula_|i2s_intf_|shiftreg[15] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~4_combout ), @@ -57826,24 +57559,24 @@ defparam \ula_|i2s_intf_|shiftreg[15] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[15] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y22_N0 +// Location: LCCOMB_X23_Y32_N12 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~3 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~3_combout = (\ula_|i2s_intf_|shiftreg [15] & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|shiftreg~3_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [15]) - .dataa(gnd), + .dataa(\ula_|i2s_intf_|Equal0~2_combout ), .datab(gnd), .datac(\ula_|i2s_intf_|shiftreg [15]), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~3 .lut_mask = 16'h00F0; +defparam \ula_|i2s_intf_|shiftreg~3 .lut_mask = 16'h5050; defparam \ula_|i2s_intf_|shiftreg~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y22_N1 +// Location: FF_X23_Y32_N13 dffeas \ula_|i2s_intf_|shiftreg[16] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~3_combout ), @@ -57862,20 +57595,20 @@ defparam \ula_|i2s_intf_|shiftreg[16] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[16] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y22_N10 +// Location: LCCOMB_X23_Y32_N2 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~0 ( // Equation(s): // \ula_|i2s_intf_|shiftreg~0_combout = (\ula_|i2s_intf_|shiftreg [16] & !\ula_|i2s_intf_|Equal0~2_combout ) - .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg [16]), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .dataa(\ula_|i2s_intf_|shiftreg [16]), + .datab(gnd), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~0 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~0 .lut_mask = 16'h0A0A; defparam \ula_|i2s_intf_|shiftreg~0 .sum_lutc_input = "datac"; // synopsys translate_on @@ -57898,32 +57631,85 @@ defparam \ula_|i2s_intf_|shiftreg[17] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[17] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X38_Y33_N8 -cycloneive_lcell_comb \ula_|video_|LessThan2~0 ( +// Location: LCCOMB_X31_Y10_N24 +cycloneive_lcell_comb \ula_|border[1]~feeder ( // Equation(s): -// \ula_|video_|LessThan2~0_combout = (!\ula_|video_|vga_vc [9] & (!\ula_|video_|vga_vc [8] & (!\ula_|video_|vga_vc [7] & !\ula_|video_|vga_vc [6]))) +// \ula_|border[1]~feeder_combout = \D[1]~32_combout - .dataa(\ula_|video_|vga_vc [9]), - .datab(\ula_|video_|vga_vc [8]), - .datac(\ula_|video_|vga_vc [7]), - .datad(\ula_|video_|vga_vc [6]), + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\D[1]~32_combout ), .cin(gnd), - .combout(\ula_|video_|LessThan2~0_combout ), + .combout(\ula_|border[1]~feeder_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|LessThan2~0 .lut_mask = 16'h0001; -defparam \ula_|video_|LessThan2~0 .sum_lutc_input = "datac"; +defparam \ula_|border[1]~feeder .lut_mask = 16'hFF00; +defparam \ula_|border[1]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y33_N4 +// Location: FF_X31_Y10_N25 +dffeas \ula_|border[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|border[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|always0~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|border [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|border[1] .is_wysiwyg = "true"; +defparam \ula_|border[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y32_N30 +cycloneive_lcell_comb \ula_|video_|LessThan4~0 ( +// Equation(s): +// \ula_|video_|LessThan4~0_combout = (((!\ula_|video_|vga_hc [4] & !\ula_|video_|vga_hc [5])) # (!\ula_|video_|vga_hc [7])) # (!\ula_|video_|vga_hc [6]) + + .dataa(\ula_|video_|vga_hc [4]), + .datab(\ula_|video_|vga_hc [6]), + .datac(\ula_|video_|vga_hc [7]), + .datad(\ula_|video_|vga_hc [5]), + .cin(gnd), + .combout(\ula_|video_|LessThan4~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|LessThan4~0 .lut_mask = 16'h3F7F; +defparam \ula_|video_|LessThan4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y32_N26 +cycloneive_lcell_comb \ula_|video_|screen_en~0 ( +// Equation(s): +// \ula_|video_|screen_en~0_combout = (!\ula_|video_|vga_vc [9] & (\ula_|video_|vga_hc [9] $ (((\ula_|video_|vga_hc [8]) # (!\ula_|video_|LessThan4~0_combout ))))) + + .dataa(\ula_|video_|vga_hc [9]), + .datab(\ula_|video_|vga_vc [9]), + .datac(\ula_|video_|vga_hc [8]), + .datad(\ula_|video_|LessThan4~0_combout ), + .cin(gnd), + .combout(\ula_|video_|screen_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|screen_en~0 .lut_mask = 16'h1211; +defparam \ula_|video_|screen_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y32_N28 cycloneive_lcell_comb \ula_|video_|LessThan6~0 ( // Equation(s): -// \ula_|video_|LessThan6~0_combout = (!\ula_|video_|vga_vc [2] & (!\ula_|video_|vga_vc [3] & ((!\ula_|video_|vga_vc [0]) # (!\ula_|video_|vga_vc [1])))) +// \ula_|video_|LessThan6~0_combout = (!\ula_|video_|vga_vc [3] & (!\ula_|video_|vga_vc [2] & ((!\ula_|video_|vga_vc [1]) # (!\ula_|video_|vga_vc [0])))) - .dataa(\ula_|video_|vga_vc [2]), - .datab(\ula_|video_|vga_vc [3]), - .datac(\ula_|video_|vga_vc [1]), - .datad(\ula_|video_|vga_vc [0]), + .dataa(\ula_|video_|vga_vc [3]), + .datab(\ula_|video_|vga_vc [2]), + .datac(\ula_|video_|vga_vc [0]), + .datad(\ula_|video_|vga_vc [1]), .cin(gnd), .combout(\ula_|video_|LessThan6~0_combout ), .cout()); @@ -57932,76 +57718,128 @@ defparam \ula_|video_|LessThan6~0 .lut_mask = 16'h0111; defparam \ula_|video_|LessThan6~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y33_N30 +// Location: LCCOMB_X35_Y32_N12 +cycloneive_lcell_comb \ula_|video_|LessThan6~1 ( +// Equation(s): +// \ula_|video_|LessThan6~1_combout = ((!\ula_|video_|vga_vc [5] & ((\ula_|video_|LessThan6~0_combout ) # (!\ula_|video_|vga_vc [4])))) # (!\ula_|video_|vga_vc [6]) + + .dataa(\ula_|video_|vga_vc [4]), + .datab(\ula_|video_|vga_vc [6]), + .datac(\ula_|video_|vga_vc [5]), + .datad(\ula_|video_|LessThan6~0_combout ), + .cin(gnd), + .combout(\ula_|video_|LessThan6~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|LessThan6~1 .lut_mask = 16'h3F37; +defparam \ula_|video_|LessThan6~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y32_N22 +cycloneive_lcell_comb \ula_|video_|screen_en~1 ( +// Equation(s): +// \ula_|video_|screen_en~1_combout = (\ula_|video_|screen_en~0_combout & ((\ula_|video_|vga_vc [7] & ((\ula_|video_|LessThan6~1_combout ) # (!\ula_|video_|vga_vc [8]))) # (!\ula_|video_|vga_vc [7] & ((\ula_|video_|vga_vc [8]) # +// (!\ula_|video_|LessThan6~1_combout ))))) + + .dataa(\ula_|video_|vga_vc [7]), + .datab(\ula_|video_|vga_vc [8]), + .datac(\ula_|video_|screen_en~0_combout ), + .datad(\ula_|video_|LessThan6~1_combout ), + .cin(gnd), + .combout(\ula_|video_|screen_en~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|screen_en~1 .lut_mask = 16'hE070; +defparam \ula_|video_|screen_en~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y32_N14 +cycloneive_lcell_comb \ula_|video_|LessThan2~0 ( +// Equation(s): +// \ula_|video_|LessThan2~0_combout = (!\ula_|video_|vga_vc [9] & (!\ula_|video_|vga_vc [8] & (!\ula_|video_|vga_vc [6] & !\ula_|video_|vga_vc [7]))) + + .dataa(\ula_|video_|vga_vc [9]), + .datab(\ula_|video_|vga_vc [8]), + .datac(\ula_|video_|vga_vc [6]), + .datad(\ula_|video_|vga_vc [7]), + .cin(gnd), + .combout(\ula_|video_|LessThan2~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|LessThan2~0 .lut_mask = 16'h0001; +defparam \ula_|video_|LessThan2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y32_N12 cycloneive_lcell_comb \ula_|video_|LessThan2~1 ( // Equation(s): // \ula_|video_|LessThan2~1_combout = (\ula_|video_|LessThan2~0_combout & (((!\ula_|video_|vga_vc [4] & \ula_|video_|LessThan6~0_combout )) # (!\ula_|video_|vga_vc [5]))) - .dataa(\ula_|video_|vga_vc [5]), - .datab(\ula_|video_|vga_vc [4]), + .dataa(\ula_|video_|vga_vc [4]), + .datab(\ula_|video_|vga_vc [5]), .datac(\ula_|video_|LessThan2~0_combout ), .datad(\ula_|video_|LessThan6~0_combout ), .cin(gnd), .combout(\ula_|video_|LessThan2~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|LessThan2~1 .lut_mask = 16'h7050; +defparam \ula_|video_|LessThan2~1 .lut_mask = 16'h7030; defparam \ula_|video_|LessThan2~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y33_N16 +// Location: LCCOMB_X36_Y32_N4 cycloneive_lcell_comb \ula_|video_|LessThan3~0 ( // Equation(s): -// \ula_|video_|LessThan3~0_combout = ((\ula_|video_|LessThan6~0_combout & (!\ula_|video_|vga_vc [5] & \ula_|video_|Equal2~0_combout ))) # (!\ula_|video_|vga_vc [9]) +// \ula_|video_|LessThan3~0_combout = ((!\ula_|video_|vga_vc [5] & (\ula_|video_|LessThan6~0_combout & \ula_|video_|Equal2~0_combout ))) # (!\ula_|video_|vga_vc [9]) - .dataa(\ula_|video_|vga_vc [9]), + .dataa(\ula_|video_|vga_vc [5]), .datab(\ula_|video_|LessThan6~0_combout ), - .datac(\ula_|video_|vga_vc [5]), + .datac(\ula_|video_|vga_vc [9]), .datad(\ula_|video_|Equal2~0_combout ), .cin(gnd), .combout(\ula_|video_|LessThan3~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|LessThan3~0 .lut_mask = 16'h5D55; +defparam \ula_|video_|LessThan3~0 .lut_mask = 16'h4F0F; defparam \ula_|video_|LessThan3~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y33_N22 +// Location: LCCOMB_X34_Y32_N2 cycloneive_lcell_comb \ula_|video_|LessThan0~0 ( // Equation(s): -// \ula_|video_|LessThan0~0_combout = (!\ula_|video_|vga_hc [4] & (!\ula_|video_|vga_hc [6] & !\ula_|video_|vga_hc [5])) +// \ula_|video_|LessThan0~0_combout = (!\ula_|video_|vga_hc [6] & (!\ula_|video_|vga_hc [4] & !\ula_|video_|vga_hc [5])) - .dataa(\ula_|video_|vga_hc [4]), + .dataa(gnd), .datab(\ula_|video_|vga_hc [6]), - .datac(gnd), + .datac(\ula_|video_|vga_hc [4]), .datad(\ula_|video_|vga_hc [5]), .cin(gnd), .combout(\ula_|video_|LessThan0~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|LessThan0~0 .lut_mask = 16'h0011; +defparam \ula_|video_|LessThan0~0 .lut_mask = 16'h0003; defparam \ula_|video_|LessThan0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y33_N24 +// Location: LCCOMB_X34_Y32_N0 cycloneive_lcell_comb \ula_|video_|disp_enable~0 ( // Equation(s): -// \ula_|video_|disp_enable~0_combout = (\ula_|video_|vga_hc [8] & (((\ula_|video_|LessThan0~0_combout & !\ula_|video_|vga_hc [7])) # (!\ula_|video_|vga_hc [9]))) # (!\ula_|video_|vga_hc [8] & ((\ula_|video_|vga_hc [9]) # -// ((!\ula_|video_|LessThan0~0_combout & \ula_|video_|vga_hc [7])))) +// \ula_|video_|disp_enable~0_combout = (\ula_|video_|vga_hc [8] & (((!\ula_|video_|vga_hc [7] & \ula_|video_|LessThan0~0_combout )) # (!\ula_|video_|vga_hc [9]))) # (!\ula_|video_|vga_hc [8] & ((\ula_|video_|vga_hc [9]) # ((\ula_|video_|vga_hc [7] & +// !\ula_|video_|LessThan0~0_combout )))) - .dataa(\ula_|video_|LessThan0~0_combout ), + .dataa(\ula_|video_|vga_hc [7]), .datab(\ula_|video_|vga_hc [8]), - .datac(\ula_|video_|vga_hc [7]), - .datad(\ula_|video_|vga_hc [9]), + .datac(\ula_|video_|vga_hc [9]), + .datad(\ula_|video_|LessThan0~0_combout ), .cin(gnd), .combout(\ula_|video_|disp_enable~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|disp_enable~0 .lut_mask = 16'h3BDC; +defparam \ula_|video_|disp_enable~0 .lut_mask = 16'h7C3E; defparam \ula_|video_|disp_enable~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y33_N2 +// Location: LCCOMB_X36_Y32_N6 cycloneive_lcell_comb \ula_|video_|disp_enable~1 ( // Equation(s): // \ula_|video_|disp_enable~1_combout = (!\ula_|video_|LessThan2~1_combout & (\ula_|video_|LessThan3~0_combout & \ula_|video_|disp_enable~0_combout )) @@ -58018,239 +57856,7 @@ defparam \ula_|video_|disp_enable~1 .lut_mask = 16'h4400; defparam \ula_|video_|disp_enable~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y22_N11 -dffeas \ula_|border[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\D[1]~34_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|always0~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|border [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|border[1] .is_wysiwyg = "true"; -defparam \ula_|border[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y33_N8 -cycloneive_lcell_comb \ula_|video_|LessThan6~1 ( -// Equation(s): -// \ula_|video_|LessThan6~1_combout = ((!\ula_|video_|vga_vc [5] & ((\ula_|video_|LessThan6~0_combout ) # (!\ula_|video_|vga_vc [4])))) # (!\ula_|video_|vga_vc [6]) - - .dataa(\ula_|video_|vga_vc [6]), - .datab(\ula_|video_|vga_vc [5]), - .datac(\ula_|video_|vga_vc [4]), - .datad(\ula_|video_|LessThan6~0_combout ), - .cin(gnd), - .combout(\ula_|video_|LessThan6~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|LessThan6~1 .lut_mask = 16'h7757; -defparam \ula_|video_|LessThan6~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N28 -cycloneive_lcell_comb \ula_|video_|LessThan4~0 ( -// Equation(s): -// \ula_|video_|LessThan4~0_combout = (((!\ula_|video_|vga_hc [4] & !\ula_|video_|vga_hc [5])) # (!\ula_|video_|vga_hc [7])) # (!\ula_|video_|vga_hc [6]) - - .dataa(\ula_|video_|vga_hc [4]), - .datab(\ula_|video_|vga_hc [5]), - .datac(\ula_|video_|vga_hc [6]), - .datad(\ula_|video_|vga_hc [7]), - .cin(gnd), - .combout(\ula_|video_|LessThan4~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|LessThan4~0 .lut_mask = 16'h1FFF; -defparam \ula_|video_|LessThan4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y33_N10 -cycloneive_lcell_comb \ula_|video_|screen_en~0 ( -// Equation(s): -// \ula_|video_|screen_en~0_combout = (!\ula_|video_|vga_vc [9] & (\ula_|video_|vga_hc [9] $ (((\ula_|video_|vga_hc [8]) # (!\ula_|video_|LessThan4~0_combout ))))) - - .dataa(\ula_|video_|vga_hc [9]), - .datab(\ula_|video_|vga_vc [9]), - .datac(\ula_|video_|LessThan4~0_combout ), - .datad(\ula_|video_|vga_hc [8]), - .cin(gnd), - .combout(\ula_|video_|screen_en~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|screen_en~0 .lut_mask = 16'h1121; -defparam \ula_|video_|screen_en~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y33_N22 -cycloneive_lcell_comb \ula_|video_|screen_en~1 ( -// Equation(s): -// \ula_|video_|screen_en~1_combout = (\ula_|video_|screen_en~0_combout & ((\ula_|video_|vga_vc [7] & ((\ula_|video_|LessThan6~1_combout ) # (!\ula_|video_|vga_vc [8]))) # (!\ula_|video_|vga_vc [7] & ((\ula_|video_|vga_vc [8]) # -// (!\ula_|video_|LessThan6~1_combout ))))) - - .dataa(\ula_|video_|vga_vc [7]), - .datab(\ula_|video_|vga_vc [8]), - .datac(\ula_|video_|LessThan6~1_combout ), - .datad(\ula_|video_|screen_en~0_combout ), - .cin(gnd), - .combout(\ula_|video_|screen_en~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|screen_en~1 .lut_mask = 16'hE700; -defparam \ula_|video_|screen_en~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y33_N28 -cycloneive_lcell_comb \ula_|video_|attr_prefetch[1]~feeder ( -// Equation(s): -// \ula_|video_|attr_prefetch[1]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|attr_prefetch[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|attr_prefetch[1]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|attr_prefetch[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N10 -cycloneive_lcell_comb \ula_|video_|Decoder0~1 ( -// Equation(s): -// \ula_|video_|Decoder0~1_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|vga_hc [3] & (\ula_|video_|vga_hc [1] & !\ula_|video_|vga_hc [0]))) - - .dataa(\ula_|video_|vga_hc [2]), - .datab(\ula_|video_|vga_hc [3]), - .datac(\ula_|video_|vga_hc [1]), - .datad(\ula_|video_|vga_hc [0]), - .cin(gnd), - .combout(\ula_|video_|Decoder0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Decoder0~1 .lut_mask = 16'h0080; -defparam \ula_|video_|Decoder0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y33_N29 -dffeas \ula_|video_|attr_prefetch[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|attr_prefetch[1]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|attr_prefetch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|attr_prefetch[1] .is_wysiwyg = "true"; -defparam \ula_|video_|attr_prefetch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N12 -cycloneive_lcell_comb \ula_|video_|Decoder0~0 ( -// Equation(s): -// \ula_|video_|Decoder0~0_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|vga_hc [3] & (\ula_|video_|vga_hc [1] & \ula_|video_|vga_hc [0]))) - - .dataa(\ula_|video_|vga_hc [2]), - .datab(\ula_|video_|vga_hc [3]), - .datac(\ula_|video_|vga_hc [1]), - .datad(\ula_|video_|vga_hc [0]), - .cin(gnd), - .combout(\ula_|video_|Decoder0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Decoder0~0 .lut_mask = 16'h8000; -defparam \ula_|video_|Decoder0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y33_N27 -dffeas \ula_|video_|attr[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|attr_prefetch [1]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|Decoder0~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|attr [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|attr[1] .is_wysiwyg = "true"; -defparam \ula_|video_|attr[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y33_N10 -cycloneive_lcell_comb \ula_|video_|attr_prefetch[4]~feeder ( -// Equation(s): -// \ula_|video_|attr_prefetch[4]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|attr_prefetch[4]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|attr_prefetch[4]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|attr_prefetch[4]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y33_N11 -dffeas \ula_|video_|attr_prefetch[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|attr_prefetch[4]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|attr_prefetch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|attr_prefetch[4] .is_wysiwyg = "true"; -defparam \ula_|video_|attr_prefetch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X37_Y33_N13 -dffeas \ula_|video_|attr[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|attr_prefetch [4]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|Decoder0~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|attr [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|attr[4] .is_wysiwyg = "true"; -defparam \ula_|video_|attr[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y33_N24 +// Location: LCCOMB_X38_Y32_N8 cycloneive_lcell_comb \ula_|video_|attr_prefetch[7]~feeder ( // Equation(s): // \ula_|video_|attr_prefetch[7]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 @@ -58267,7 +57873,24 @@ defparam \ula_|video_|attr_prefetch[7]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|attr_prefetch[7]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N25 +// Location: LCCOMB_X35_Y31_N24 +cycloneive_lcell_comb \ula_|video_|Decoder0~1 ( +// Equation(s): +// \ula_|video_|Decoder0~1_combout = (\ula_|video_|vga_hc [1] & (\ula_|video_|vga_hc [3] & (\ula_|video_|vga_hc [2] & !\ula_|video_|vga_hc [0]))) + + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|vga_hc [3]), + .datac(\ula_|video_|vga_hc [2]), + .datad(\ula_|video_|vga_hc [0]), + .cin(gnd), + .combout(\ula_|video_|Decoder0~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Decoder0~1 .lut_mask = 16'h0080; +defparam \ula_|video_|Decoder0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X38_Y32_N9 dffeas \ula_|video_|attr_prefetch[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr_prefetch[7]~feeder_combout ), @@ -58286,7 +57909,24 @@ defparam \ula_|video_|attr_prefetch[7] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[7] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y33_N5 +// Location: LCCOMB_X35_Y31_N2 +cycloneive_lcell_comb \ula_|video_|Decoder0~0 ( +// Equation(s): +// \ula_|video_|Decoder0~0_combout = (\ula_|video_|vga_hc [1] & (\ula_|video_|vga_hc [3] & (\ula_|video_|vga_hc [2] & \ula_|video_|vga_hc [0]))) + + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|vga_hc [3]), + .datac(\ula_|video_|vga_hc [2]), + .datad(\ula_|video_|vga_hc [0]), + .cin(gnd), + .combout(\ula_|video_|Decoder0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Decoder0~0 .lut_mask = 16'h8000; +defparam \ula_|video_|Decoder0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y32_N23 dffeas \ula_|video_|attr[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -58305,24 +57945,24 @@ defparam \ula_|video_|attr[7] .is_wysiwyg = "true"; defparam \ula_|video_|attr[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y33_N22 +// Location: LCCOMB_X35_Y31_N0 cycloneive_lcell_comb \ula_|video_|frame[0]~12 ( // Equation(s): -// \ula_|video_|frame[0]~12_combout = \ula_|video_|Equal3~1_combout $ (\ula_|video_|frame [0]) +// \ula_|video_|frame[0]~12_combout = \ula_|video_|frame [0] $ (\ula_|video_|Equal3~1_combout ) - .dataa(\ula_|video_|Equal3~1_combout ), + .dataa(gnd), .datab(gnd), .datac(\ula_|video_|frame [0]), - .datad(gnd), + .datad(\ula_|video_|Equal3~1_combout ), .cin(gnd), .combout(\ula_|video_|frame[0]~12_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|frame[0]~12 .lut_mask = 16'h5A5A; +defparam \ula_|video_|frame[0]~12 .lut_mask = 16'h0FF0; defparam \ula_|video_|frame[0]~12 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X34_Y33_N23 +// Location: FF_X35_Y31_N1 dffeas \ula_|video_|frame[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|frame[0]~12_combout ), @@ -58341,7 +57981,7 @@ defparam \ula_|video_|frame[0] .is_wysiwyg = "true"; defparam \ula_|video_|frame[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X35_Y33_N24 +// Location: LCCOMB_X35_Y32_N14 cycloneive_lcell_comb \ula_|video_|frame[1]~4 ( // Equation(s): // \ula_|video_|frame[1]~4_combout = (\ula_|video_|frame [0] & (\ula_|video_|frame [1] $ (VCC))) # (!\ula_|video_|frame [0] & (\ula_|video_|frame [1] & VCC)) @@ -58359,7 +57999,7 @@ defparam \ula_|video_|frame[1]~4 .lut_mask = 16'h6688; defparam \ula_|video_|frame[1]~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X35_Y33_N25 +// Location: FF_X35_Y32_N15 dffeas \ula_|video_|frame[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|frame[1]~4_combout ), @@ -58378,25 +58018,25 @@ defparam \ula_|video_|frame[1] .is_wysiwyg = "true"; defparam \ula_|video_|frame[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X35_Y33_N26 +// Location: LCCOMB_X35_Y32_N16 cycloneive_lcell_comb \ula_|video_|frame[2]~6 ( // Equation(s): // \ula_|video_|frame[2]~6_combout = (\ula_|video_|frame [2] & (!\ula_|video_|frame[1]~5 )) # (!\ula_|video_|frame [2] & ((\ula_|video_|frame[1]~5 ) # (GND))) // \ula_|video_|frame[2]~7 = CARRY((!\ula_|video_|frame[1]~5 ) # (!\ula_|video_|frame [2])) - .dataa(\ula_|video_|frame [2]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|video_|frame [2]), .datac(gnd), .datad(vcc), .cin(\ula_|video_|frame[1]~5 ), .combout(\ula_|video_|frame[2]~6_combout ), .cout(\ula_|video_|frame[2]~7 )); // synopsys translate_off -defparam \ula_|video_|frame[2]~6 .lut_mask = 16'h5A5F; +defparam \ula_|video_|frame[2]~6 .lut_mask = 16'h3C3F; defparam \ula_|video_|frame[2]~6 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X35_Y33_N27 +// Location: FF_X35_Y32_N17 dffeas \ula_|video_|frame[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|frame[2]~6_combout ), @@ -58415,7 +58055,7 @@ defparam \ula_|video_|frame[2] .is_wysiwyg = "true"; defparam \ula_|video_|frame[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X35_Y33_N28 +// Location: LCCOMB_X35_Y32_N18 cycloneive_lcell_comb \ula_|video_|frame[3]~8 ( // Equation(s): // \ula_|video_|frame[3]~8_combout = (\ula_|video_|frame [3] & (\ula_|video_|frame[2]~7 $ (GND))) # (!\ula_|video_|frame [3] & (!\ula_|video_|frame[2]~7 & VCC)) @@ -58433,7 +58073,7 @@ defparam \ula_|video_|frame[3]~8 .lut_mask = 16'hC30C; defparam \ula_|video_|frame[3]~8 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X35_Y33_N29 +// Location: FF_X35_Y32_N19 dffeas \ula_|video_|frame[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|frame[3]~8_combout ), @@ -58452,27 +58092,44 @@ defparam \ula_|video_|frame[3] .is_wysiwyg = "true"; defparam \ula_|video_|frame[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X35_Y33_N30 +// Location: LCCOMB_X35_Y32_N20 cycloneive_lcell_comb \ula_|video_|frame[4]~10 ( // Equation(s): -// \ula_|video_|frame[4]~10_combout = \ula_|video_|frame [4] $ (\ula_|video_|frame[3]~9 ) +// \ula_|video_|frame[4]~10_combout = \ula_|video_|frame[3]~9 $ (\ula_|video_|frame [4]) - .dataa(\ula_|video_|frame [4]), + .dataa(gnd), .datab(gnd), .datac(gnd), - .datad(gnd), + .datad(\ula_|video_|frame [4]), .cin(\ula_|video_|frame[3]~9 ), .combout(\ula_|video_|frame[4]~10_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|frame[4]~10 .lut_mask = 16'h5A5A; +defparam \ula_|video_|frame[4]~10 .lut_mask = 16'h0FF0; defparam \ula_|video_|frame[4]~10 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X35_Y33_N31 +// Location: LCCOMB_X37_Y32_N0 +cycloneive_lcell_comb \ula_|video_|frame[4]~feeder ( +// Equation(s): +// \ula_|video_|frame[4]~feeder_combout = \ula_|video_|frame[4]~10_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|frame[4]~10_combout ), + .cin(gnd), + .combout(\ula_|video_|frame[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|frame[4]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|frame[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y32_N1 dffeas \ula_|video_|frame[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|frame[4]~10_combout ), + .d(\ula_|video_|frame[4]~feeder_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -58488,7 +58145,7 @@ defparam \ula_|video_|frame[4] .is_wysiwyg = "true"; defparam \ula_|video_|frame[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N4 +// Location: LCCOMB_X37_Y32_N22 cycloneive_lcell_comb \ula_|video_|inverted ( // Equation(s): // \ula_|video_|inverted~combout = (\ula_|video_|attr [7] & \ula_|video_|frame [4]) @@ -58505,41 +58162,41 @@ defparam \ula_|video_|inverted .lut_mask = 16'hF000; defparam \ula_|video_|inverted .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N12 +// Location: LCCOMB_X38_Y32_N4 cycloneive_lcell_comb \ula_|video_|bits_prefetch[6]~feeder ( // Equation(s): // \ula_|video_|bits_prefetch[6]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 ), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 ), + .datad(gnd), .cin(gnd), .combout(\ula_|video_|bits_prefetch[6]~feeder_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|bits_prefetch[6]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|bits_prefetch[6]~feeder .lut_mask = 16'hF0F0; defparam \ula_|video_|bits_prefetch[6]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y31_N8 +// Location: LCCOMB_X35_Y31_N10 cycloneive_lcell_comb \ula_|video_|Decoder0~2 ( // Equation(s): -// \ula_|video_|Decoder0~2_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [1] & !\ula_|video_|vga_hc [0]))) +// \ula_|video_|Decoder0~2_combout = (!\ula_|video_|vga_hc [1] & (\ula_|video_|vga_hc [3] & (\ula_|video_|vga_hc [2] & !\ula_|video_|vga_hc [0]))) - .dataa(\ula_|video_|vga_hc [2]), + .dataa(\ula_|video_|vga_hc [1]), .datab(\ula_|video_|vga_hc [3]), - .datac(\ula_|video_|vga_hc [1]), + .datac(\ula_|video_|vga_hc [2]), .datad(\ula_|video_|vga_hc [0]), .cin(gnd), .combout(\ula_|video_|Decoder0~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Decoder0~2 .lut_mask = 16'h0008; +defparam \ula_|video_|Decoder0~2 .lut_mask = 16'h0040; defparam \ula_|video_|Decoder0~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N13 +// Location: FF_X38_Y32_N5 dffeas \ula_|video_|bits_prefetch[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits_prefetch[6]~feeder_combout ), @@ -58558,32 +58215,15 @@ defparam \ula_|video_|bits_prefetch[6] .is_wysiwyg = "true"; defparam \ula_|video_|bits_prefetch[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N6 -cycloneive_lcell_comb \ula_|video_|bits[6]~feeder ( -// Equation(s): -// \ula_|video_|bits[6]~feeder_combout = \ula_|video_|bits_prefetch [6] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|bits_prefetch [6]), - .cin(gnd), - .combout(\ula_|video_|bits[6]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|bits[6]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|bits[6]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y33_N7 +// Location: FF_X37_Y32_N27 dffeas \ula_|video_|bits[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|bits[6]~feeder_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\ula_|video_|bits_prefetch [6]), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), + .sload(vcc), .ena(\ula_|video_|Decoder0~0_combout ), .devclrn(devclrn), .devpor(devpor), @@ -58594,7 +58234,7 @@ defparam \ula_|video_|bits[6] .is_wysiwyg = "true"; defparam \ula_|video_|bits[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N22 +// Location: LCCOMB_X38_Y32_N10 cycloneive_lcell_comb \ula_|video_|bits_prefetch[4]~feeder ( // Equation(s): // \ula_|video_|bits_prefetch[4]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 @@ -58611,7 +58251,7 @@ defparam \ula_|video_|bits_prefetch[4]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits_prefetch[4]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N23 +// Location: FF_X38_Y32_N11 dffeas \ula_|video_|bits_prefetch[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits_prefetch[4]~feeder_combout ), @@ -58630,7 +58270,7 @@ defparam \ula_|video_|bits_prefetch[4] .is_wysiwyg = "true"; defparam \ula_|video_|bits_prefetch[4] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y33_N23 +// Location: FF_X37_Y32_N9 dffeas \ula_|video_|bits[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -58649,7 +58289,7 @@ defparam \ula_|video_|bits[4] .is_wysiwyg = "true"; defparam \ula_|video_|bits[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N18 +// Location: LCCOMB_X38_Y32_N26 cycloneive_lcell_comb \ula_|video_|bits_prefetch[5]~feeder ( // Equation(s): // \ula_|video_|bits_prefetch[5]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 @@ -58666,7 +58306,7 @@ defparam \ula_|video_|bits_prefetch[5]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits_prefetch[5]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N19 +// Location: FF_X38_Y32_N27 dffeas \ula_|video_|bits_prefetch[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits_prefetch[5]~feeder_combout ), @@ -58685,7 +58325,7 @@ defparam \ula_|video_|bits_prefetch[5] .is_wysiwyg = "true"; defparam \ula_|video_|bits_prefetch[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N18 +// Location: LCCOMB_X37_Y32_N12 cycloneive_lcell_comb \ula_|video_|bits[5]~feeder ( // Equation(s): // \ula_|video_|bits[5]~feeder_combout = \ula_|video_|bits_prefetch [5] @@ -58702,7 +58342,7 @@ defparam \ula_|video_|bits[5]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits[5]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X36_Y33_N19 +// Location: FF_X37_Y32_N13 dffeas \ula_|video_|bits[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits[5]~feeder_combout ), @@ -58721,7 +58361,7 @@ defparam \ula_|video_|bits[5] .is_wysiwyg = "true"; defparam \ula_|video_|bits[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N0 +// Location: LCCOMB_X38_Y32_N12 cycloneive_lcell_comb \ula_|video_|bits_prefetch[7]~feeder ( // Equation(s): // \ula_|video_|bits_prefetch[7]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 @@ -58738,7 +58378,7 @@ defparam \ula_|video_|bits_prefetch[7]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits_prefetch[7]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N1 +// Location: FF_X38_Y32_N13 dffeas \ula_|video_|bits_prefetch[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits_prefetch[7]~feeder_combout ), @@ -58757,7 +58397,7 @@ defparam \ula_|video_|bits_prefetch[7] .is_wysiwyg = "true"; defparam \ula_|video_|bits_prefetch[7] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y33_N1 +// Location: FF_X37_Y32_N19 dffeas \ula_|video_|bits[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -58776,41 +58416,41 @@ defparam \ula_|video_|bits[7] .is_wysiwyg = "true"; defparam \ula_|video_|bits[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N0 +// Location: LCCOMB_X37_Y32_N18 cycloneive_lcell_comb \ula_|video_|Mux0~0 ( // Equation(s): -// \ula_|video_|Mux0~0_combout = (\ula_|video_|vga_hc [1] & (((\ula_|video_|vga_hc [2])))) # (!\ula_|video_|vga_hc [1] & ((\ula_|video_|vga_hc [2] & (\ula_|video_|bits [5])) # (!\ula_|video_|vga_hc [2] & ((\ula_|video_|bits [7]))))) +// \ula_|video_|Mux0~0_combout = (\ula_|video_|vga_hc [2] & ((\ula_|video_|bits [5]) # ((\ula_|video_|vga_hc [1])))) # (!\ula_|video_|vga_hc [2] & (((\ula_|video_|bits [7] & !\ula_|video_|vga_hc [1])))) .dataa(\ula_|video_|bits [5]), - .datab(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|vga_hc [2]), .datac(\ula_|video_|bits [7]), - .datad(\ula_|video_|vga_hc [2]), + .datad(\ula_|video_|vga_hc [1]), .cin(gnd), .combout(\ula_|video_|Mux0~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Mux0~0 .lut_mask = 16'hEE30; +defparam \ula_|video_|Mux0~0 .lut_mask = 16'hCCB8; defparam \ula_|video_|Mux0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N22 +// Location: LCCOMB_X37_Y32_N8 cycloneive_lcell_comb \ula_|video_|Mux0~1 ( // Equation(s): // \ula_|video_|Mux0~1_combout = (\ula_|video_|vga_hc [1] & ((\ula_|video_|Mux0~0_combout & ((\ula_|video_|bits [4]))) # (!\ula_|video_|Mux0~0_combout & (\ula_|video_|bits [6])))) # (!\ula_|video_|vga_hc [1] & (((\ula_|video_|Mux0~0_combout )))) - .dataa(\ula_|video_|bits [6]), - .datab(\ula_|video_|vga_hc [1]), + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|bits [6]), .datac(\ula_|video_|bits [4]), .datad(\ula_|video_|Mux0~0_combout ), .cin(gnd), .combout(\ula_|video_|Mux0~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Mux0~1 .lut_mask = 16'hF388; +defparam \ula_|video_|Mux0~1 .lut_mask = 16'hF588; defparam \ula_|video_|Mux0~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N16 +// Location: LCCOMB_X38_Y32_N16 cycloneive_lcell_comb \ula_|video_|bits_prefetch[2]~feeder ( // Equation(s): // \ula_|video_|bits_prefetch[2]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 @@ -58827,7 +58467,7 @@ defparam \ula_|video_|bits_prefetch[2]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits_prefetch[2]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N17 +// Location: FF_X38_Y32_N17 dffeas \ula_|video_|bits_prefetch[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits_prefetch[2]~feeder_combout ), @@ -58846,7 +58486,7 @@ defparam \ula_|video_|bits_prefetch[2] .is_wysiwyg = "true"; defparam \ula_|video_|bits_prefetch[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N12 +// Location: LCCOMB_X37_Y32_N30 cycloneive_lcell_comb \ula_|video_|bits[2]~feeder ( // Equation(s): // \ula_|video_|bits[2]~feeder_combout = \ula_|video_|bits_prefetch [2] @@ -58863,7 +58503,7 @@ defparam \ula_|video_|bits[2]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits[2]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X36_Y33_N13 +// Location: FF_X37_Y32_N31 dffeas \ula_|video_|bits[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits[2]~feeder_combout ), @@ -58882,7 +58522,7 @@ defparam \ula_|video_|bits[2] .is_wysiwyg = "true"; defparam \ula_|video_|bits[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N14 +// Location: LCCOMB_X38_Y32_N6 cycloneive_lcell_comb \ula_|video_|bits_prefetch[0]~feeder ( // Equation(s): // \ula_|video_|bits_prefetch[0]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 @@ -58899,7 +58539,7 @@ defparam \ula_|video_|bits_prefetch[0]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits_prefetch[0]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N15 +// Location: FF_X38_Y32_N7 dffeas \ula_|video_|bits_prefetch[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits_prefetch[0]~feeder_combout ), @@ -58918,7 +58558,7 @@ defparam \ula_|video_|bits_prefetch[0] .is_wysiwyg = "true"; defparam \ula_|video_|bits_prefetch[0] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y33_N3 +// Location: FF_X37_Y32_N25 dffeas \ula_|video_|bits[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -58937,7 +58577,7 @@ defparam \ula_|video_|bits[0] .is_wysiwyg = "true"; defparam \ula_|video_|bits[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N6 +// Location: LCCOMB_X38_Y32_N2 cycloneive_lcell_comb \ula_|video_|bits_prefetch[1]~feeder ( // Equation(s): // \ula_|video_|bits_prefetch[1]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 @@ -58954,7 +58594,7 @@ defparam \ula_|video_|bits_prefetch[1]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits_prefetch[1]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N7 +// Location: FF_X38_Y32_N3 dffeas \ula_|video_|bits_prefetch[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits_prefetch[1]~feeder_combout ), @@ -58973,7 +58613,7 @@ defparam \ula_|video_|bits_prefetch[1] .is_wysiwyg = "true"; defparam \ula_|video_|bits_prefetch[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N26 +// Location: LCCOMB_X37_Y32_N28 cycloneive_lcell_comb \ula_|video_|bits[1]~feeder ( // Equation(s): // \ula_|video_|bits[1]~feeder_combout = \ula_|video_|bits_prefetch [1] @@ -58990,7 +58630,7 @@ defparam \ula_|video_|bits[1]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits[1]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X36_Y33_N27 +// Location: FF_X37_Y32_N29 dffeas \ula_|video_|bits[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits[1]~feeder_combout ), @@ -59009,7 +58649,7 @@ defparam \ula_|video_|bits[1] .is_wysiwyg = "true"; defparam \ula_|video_|bits[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N4 +// Location: LCCOMB_X38_Y32_N20 cycloneive_lcell_comb \ula_|video_|bits_prefetch[3]~feeder ( // Equation(s): // \ula_|video_|bits_prefetch[3]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 @@ -59026,7 +58666,7 @@ defparam \ula_|video_|bits_prefetch[3]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits_prefetch[3]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N5 +// Location: FF_X38_Y32_N21 dffeas \ula_|video_|bits_prefetch[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits_prefetch[3]~feeder_combout ), @@ -59045,7 +58685,7 @@ defparam \ula_|video_|bits_prefetch[3] .is_wysiwyg = "true"; defparam \ula_|video_|bits_prefetch[3] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y33_N25 +// Location: FF_X37_Y32_N7 dffeas \ula_|video_|bits[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -59064,109 +58704,219 @@ defparam \ula_|video_|bits[3] .is_wysiwyg = "true"; defparam \ula_|video_|bits[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N24 +// Location: LCCOMB_X37_Y32_N6 cycloneive_lcell_comb \ula_|video_|Mux0~2 ( // Equation(s): // \ula_|video_|Mux0~2_combout = (\ula_|video_|vga_hc [1] & (((\ula_|video_|vga_hc [2])))) # (!\ula_|video_|vga_hc [1] & ((\ula_|video_|vga_hc [2] & (\ula_|video_|bits [1])) # (!\ula_|video_|vga_hc [2] & ((\ula_|video_|bits [3]))))) - .dataa(\ula_|video_|bits [1]), - .datab(\ula_|video_|vga_hc [1]), + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|bits [1]), .datac(\ula_|video_|bits [3]), .datad(\ula_|video_|vga_hc [2]), .cin(gnd), .combout(\ula_|video_|Mux0~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Mux0~2 .lut_mask = 16'hEE30; +defparam \ula_|video_|Mux0~2 .lut_mask = 16'hEE50; defparam \ula_|video_|Mux0~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N2 +// Location: LCCOMB_X37_Y32_N24 cycloneive_lcell_comb \ula_|video_|Mux0~3 ( // Equation(s): // \ula_|video_|Mux0~3_combout = (\ula_|video_|vga_hc [1] & ((\ula_|video_|Mux0~2_combout & ((\ula_|video_|bits [0]))) # (!\ula_|video_|Mux0~2_combout & (\ula_|video_|bits [2])))) # (!\ula_|video_|vga_hc [1] & (((\ula_|video_|Mux0~2_combout )))) - .dataa(\ula_|video_|bits [2]), - .datab(\ula_|video_|vga_hc [1]), + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|bits [2]), .datac(\ula_|video_|bits [0]), .datad(\ula_|video_|Mux0~2_combout ), .cin(gnd), .combout(\ula_|video_|Mux0~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Mux0~3 .lut_mask = 16'hF388; +defparam \ula_|video_|Mux0~3 .lut_mask = 16'hF588; defparam \ula_|video_|Mux0~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N10 +// Location: LCCOMB_X37_Y32_N20 cycloneive_lcell_comb \ula_|video_|cindex[1]~0 ( // Equation(s): // \ula_|video_|cindex[1]~0_combout = \ula_|video_|inverted~combout $ (((\ula_|video_|vga_hc [3] & ((\ula_|video_|Mux0~3_combout ))) # (!\ula_|video_|vga_hc [3] & (\ula_|video_|Mux0~1_combout )))) - .dataa(\ula_|video_|vga_hc [3]), - .datab(\ula_|video_|inverted~combout ), + .dataa(\ula_|video_|inverted~combout ), + .datab(\ula_|video_|vga_hc [3]), .datac(\ula_|video_|Mux0~1_combout ), .datad(\ula_|video_|Mux0~3_combout ), .cin(gnd), .combout(\ula_|video_|cindex[1]~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|cindex[1]~0 .lut_mask = 16'h369C; +defparam \ula_|video_|cindex[1]~0 .lut_mask = 16'h569A; defparam \ula_|video_|cindex[1]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y33_N12 +// Location: LCCOMB_X38_Y32_N14 +cycloneive_lcell_comb \ula_|video_|attr_prefetch[4]~feeder ( +// Equation(s): +// \ula_|video_|attr_prefetch[4]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ula_|video_|attr_prefetch[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|attr_prefetch[4]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|attr_prefetch[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X38_Y32_N15 +dffeas \ula_|video_|attr_prefetch[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|attr_prefetch[4]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|Decoder0~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|attr_prefetch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|attr_prefetch[4] .is_wysiwyg = "true"; +defparam \ula_|video_|attr_prefetch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X36_Y32_N17 +dffeas \ula_|video_|attr[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|attr_prefetch [4]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|attr [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|attr[4] .is_wysiwyg = "true"; +defparam \ula_|video_|attr[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y32_N28 +cycloneive_lcell_comb \ula_|video_|attr_prefetch[1]~feeder ( +// Equation(s): +// \ula_|video_|attr_prefetch[1]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ula_|video_|attr_prefetch[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|attr_prefetch[1]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|attr_prefetch[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X38_Y32_N29 +dffeas \ula_|video_|attr_prefetch[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|attr_prefetch[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|Decoder0~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|attr_prefetch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|attr_prefetch[1] .is_wysiwyg = "true"; +defparam \ula_|video_|attr_prefetch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X36_Y32_N7 +dffeas \ula_|video_|attr[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|attr_prefetch [1]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|attr [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|attr[1] .is_wysiwyg = "true"; +defparam \ula_|video_|attr[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y32_N16 cycloneive_lcell_comb \ula_|video_|cindex[1]~1 ( // Equation(s): -// \ula_|video_|cindex[1]~1_combout = (\ula_|video_|cindex[1]~0_combout & (\ula_|video_|attr [1])) # (!\ula_|video_|cindex[1]~0_combout & ((\ula_|video_|attr [4]))) +// \ula_|video_|cindex[1]~1_combout = (\ula_|video_|cindex[1]~0_combout & ((\ula_|video_|attr [1]))) # (!\ula_|video_|cindex[1]~0_combout & (\ula_|video_|attr [4])) - .dataa(\ula_|video_|attr [1]), + .dataa(\ula_|video_|cindex[1]~0_combout ), .datab(gnd), .datac(\ula_|video_|attr [4]), - .datad(\ula_|video_|cindex[1]~0_combout ), + .datad(\ula_|video_|attr [1]), .cin(gnd), .combout(\ula_|video_|cindex[1]~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|cindex[1]~1 .lut_mask = 16'hAAF0; +defparam \ula_|video_|cindex[1]~1 .lut_mask = 16'hFA50; defparam \ula_|video_|cindex[1]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y33_N24 +// Location: LCCOMB_X36_Y32_N26 cycloneive_lcell_comb \ula_|video_|VGA_R[0]~0 ( // Equation(s): // \ula_|video_|VGA_R[0]~0_combout = (\ula_|video_|disp_enable~1_combout & ((\ula_|video_|screen_en~1_combout & ((\ula_|video_|cindex[1]~1_combout ))) # (!\ula_|video_|screen_en~1_combout & (\ula_|border [1])))) - .dataa(\ula_|video_|disp_enable~1_combout ), - .datab(\ula_|border [1]), - .datac(\ula_|video_|screen_en~1_combout ), + .dataa(\ula_|border [1]), + .datab(\ula_|video_|screen_en~1_combout ), + .datac(\ula_|video_|disp_enable~1_combout ), .datad(\ula_|video_|cindex[1]~1_combout ), .cin(gnd), .combout(\ula_|video_|VGA_R[0]~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|VGA_R[0]~0 .lut_mask = 16'hA808; +defparam \ula_|video_|VGA_R[0]~0 .lut_mask = 16'hE020; defparam \ula_|video_|VGA_R[0]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N26 +// Location: LCCOMB_X38_Y32_N18 cycloneive_lcell_comb \ula_|video_|attr_prefetch[6]~feeder ( // Equation(s): // \ula_|video_|attr_prefetch[6]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 ), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 ), + .datad(gnd), .cin(gnd), .combout(\ula_|video_|attr_prefetch[6]~feeder_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|attr_prefetch[6]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|attr_prefetch[6]~feeder .lut_mask = 16'hF0F0; defparam \ula_|video_|attr_prefetch[6]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N27 +// Location: FF_X38_Y32_N19 dffeas \ula_|video_|attr_prefetch[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr_prefetch[6]~feeder_combout ), @@ -59185,7 +58935,7 @@ defparam \ula_|video_|attr_prefetch[6] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[6] .power_up = "low"; // synopsys translate_on -// Location: FF_X38_Y33_N1 +// Location: FF_X36_Y32_N9 dffeas \ula_|video_|attr[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -59204,7 +58954,7 @@ defparam \ula_|video_|attr[6] .is_wysiwyg = "true"; defparam \ula_|video_|attr[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X38_Y33_N0 +// Location: LCCOMB_X36_Y32_N8 cycloneive_lcell_comb \ula_|video_|VGA_B[1]~0 ( // Equation(s): // \ula_|video_|VGA_B[1]~0_combout = (!\ula_|video_|LessThan2~1_combout & (\ula_|video_|LessThan3~0_combout & (\ula_|video_|attr [6] & \ula_|video_|disp_enable~0_combout ))) @@ -59221,28 +58971,28 @@ defparam \ula_|video_|VGA_B[1]~0 .lut_mask = 16'h4000; defparam \ula_|video_|VGA_B[1]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y33_N2 +// Location: LCCOMB_X36_Y32_N30 cycloneive_lcell_comb \ula_|video_|VGA_R[1]~1 ( // Equation(s): // \ula_|video_|VGA_R[1]~1_combout = (\ula_|video_|screen_en~1_combout & (\ula_|video_|VGA_B[1]~0_combout & \ula_|video_|cindex[1]~1_combout )) .dataa(\ula_|video_|screen_en~1_combout ), - .datab(gnd), - .datac(\ula_|video_|VGA_B[1]~0_combout ), + .datab(\ula_|video_|VGA_B[1]~0_combout ), + .datac(gnd), .datad(\ula_|video_|cindex[1]~1_combout ), .cin(gnd), .combout(\ula_|video_|VGA_R[1]~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|VGA_R[1]~1 .lut_mask = 16'hA000; +defparam \ula_|video_|VGA_R[1]~1 .lut_mask = 16'h8800; defparam \ula_|video_|VGA_R[1]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y12_N17 +// Location: FF_X31_Y10_N27 dffeas \ula_|border[2] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), - .asdata(\D[2]~46_combout ), + .asdata(\D[2]~39_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), @@ -59257,62 +59007,7 @@ defparam \ula_|border[2] .is_wysiwyg = "true"; defparam \ula_|border[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N8 -cycloneive_lcell_comb \ula_|video_|attr_prefetch[2]~feeder ( -// Equation(s): -// \ula_|video_|attr_prefetch[2]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|attr_prefetch[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|attr_prefetch[2]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|attr_prefetch[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y33_N9 -dffeas \ula_|video_|attr_prefetch[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|attr_prefetch[2]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|attr_prefetch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|attr_prefetch[2] .is_wysiwyg = "true"; -defparam \ula_|video_|attr_prefetch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X36_Y33_N21 -dffeas \ula_|video_|attr[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|attr_prefetch [2]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|Decoder0~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|attr [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|attr[2] .is_wysiwyg = "true"; -defparam \ula_|video_|attr[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y33_N30 +// Location: LCCOMB_X38_Y32_N22 cycloneive_lcell_comb \ula_|video_|attr_prefetch[5]~feeder ( // Equation(s): // \ula_|video_|attr_prefetch[5]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 @@ -59329,7 +59024,7 @@ defparam \ula_|video_|attr_prefetch[5]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|attr_prefetch[5]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N31 +// Location: FF_X38_Y32_N23 dffeas \ula_|video_|attr_prefetch[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr_prefetch[5]~feeder_combout ), @@ -59348,7 +59043,7 @@ defparam \ula_|video_|attr_prefetch[5] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[5] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y33_N15 +// Location: FF_X36_Y32_N21 dffeas \ula_|video_|attr[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -59367,24 +59062,79 @@ defparam \ula_|video_|attr[5] .is_wysiwyg = "true"; defparam \ula_|video_|attr[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N14 -cycloneive_lcell_comb \ula_|video_|cindex[2]~2 ( +// Location: LCCOMB_X38_Y32_N0 +cycloneive_lcell_comb \ula_|video_|attr_prefetch[2]~feeder ( // Equation(s): -// \ula_|video_|cindex[2]~2_combout = (\ula_|video_|cindex[1]~0_combout & (\ula_|video_|attr [2])) # (!\ula_|video_|cindex[1]~0_combout & ((\ula_|video_|attr [5]))) +// \ula_|video_|attr_prefetch[2]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 .dataa(gnd), - .datab(\ula_|video_|attr [2]), + .datab(gnd), + .datac(gnd), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ula_|video_|attr_prefetch[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|attr_prefetch[2]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|attr_prefetch[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X38_Y32_N1 +dffeas \ula_|video_|attr_prefetch[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|attr_prefetch[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|Decoder0~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|attr_prefetch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|attr_prefetch[2] .is_wysiwyg = "true"; +defparam \ula_|video_|attr_prefetch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X36_Y32_N19 +dffeas \ula_|video_|attr[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|attr_prefetch [2]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|attr [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|attr[2] .is_wysiwyg = "true"; +defparam \ula_|video_|attr[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y32_N20 +cycloneive_lcell_comb \ula_|video_|cindex[2]~2 ( +// Equation(s): +// \ula_|video_|cindex[2]~2_combout = (\ula_|video_|cindex[1]~0_combout & ((\ula_|video_|attr [2]))) # (!\ula_|video_|cindex[1]~0_combout & (\ula_|video_|attr [5])) + + .dataa(\ula_|video_|cindex[1]~0_combout ), + .datab(gnd), .datac(\ula_|video_|attr [5]), - .datad(\ula_|video_|cindex[1]~0_combout ), + .datad(\ula_|video_|attr [2]), .cin(gnd), .combout(\ula_|video_|cindex[2]~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|cindex[2]~2 .lut_mask = 16'hCCF0; +defparam \ula_|video_|cindex[2]~2 .lut_mask = 16'hFA50; defparam \ula_|video_|cindex[2]~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y33_N26 +// Location: LCCOMB_X36_Y32_N22 cycloneive_lcell_comb \ula_|video_|VGA_G[0]~0 ( // Equation(s): // \ula_|video_|VGA_G[0]~0_combout = (\ula_|video_|disp_enable~1_combout & ((\ula_|video_|screen_en~1_combout & ((\ula_|video_|cindex[2]~2_combout ))) # (!\ula_|video_|screen_en~1_combout & (\ula_|border [2])))) @@ -59401,15 +59151,15 @@ defparam \ula_|video_|VGA_G[0]~0 .lut_mask = 16'hE020; defparam \ula_|video_|VGA_G[0]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N20 +// Location: LCCOMB_X36_Y32_N18 cycloneive_lcell_comb \ula_|video_|VGA_G[1]~1 ( // Equation(s): -// \ula_|video_|VGA_G[1]~1_combout = (\ula_|video_|VGA_B[1]~0_combout & (\ula_|video_|cindex[2]~2_combout & \ula_|video_|screen_en~1_combout )) +// \ula_|video_|VGA_G[1]~1_combout = (\ula_|video_|VGA_B[1]~0_combout & (\ula_|video_|screen_en~1_combout & \ula_|video_|cindex[2]~2_combout )) .dataa(\ula_|video_|VGA_B[1]~0_combout ), - .datab(\ula_|video_|cindex[2]~2_combout ), + .datab(\ula_|video_|screen_en~1_combout ), .datac(gnd), - .datad(\ula_|video_|screen_en~1_combout ), + .datad(\ula_|video_|cindex[2]~2_combout ), .cin(gnd), .combout(\ula_|video_|VGA_G[1]~1_combout ), .cout()); @@ -59418,11 +59168,11 @@ defparam \ula_|video_|VGA_G[1]~1 .lut_mask = 16'h8800; defparam \ula_|video_|VGA_G[1]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y22_N1 +// Location: FF_X23_Y14_N19 dffeas \ula_|border[0] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), - .asdata(\D[0]~58_combout ), + .asdata(\D[0]~46_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), @@ -59437,7 +59187,7 @@ defparam \ula_|border[0] .is_wysiwyg = "true"; defparam \ula_|border[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N20 +// Location: LCCOMB_X38_Y32_N24 cycloneive_lcell_comb \ula_|video_|attr_prefetch[0]~feeder ( // Equation(s): // \ula_|video_|attr_prefetch[0]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 @@ -59454,7 +59204,7 @@ defparam \ula_|video_|attr_prefetch[0]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|attr_prefetch[0]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N21 +// Location: FF_X38_Y32_N25 dffeas \ula_|video_|attr_prefetch[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr_prefetch[0]~feeder_combout ), @@ -59473,7 +59223,7 @@ defparam \ula_|video_|attr_prefetch[0] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X37_Y33_N28 +// Location: LCCOMB_X37_Y32_N10 cycloneive_lcell_comb \ula_|video_|attr[0]~feeder ( // Equation(s): // \ula_|video_|attr[0]~feeder_combout = \ula_|video_|attr_prefetch [0] @@ -59490,7 +59240,7 @@ defparam \ula_|video_|attr[0]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|attr[0]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X37_Y33_N29 +// Location: FF_X37_Y32_N11 dffeas \ula_|video_|attr[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr[0]~feeder_combout ), @@ -59509,7 +59259,7 @@ defparam \ula_|video_|attr[0] .is_wysiwyg = "true"; defparam \ula_|video_|attr[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N2 +// Location: LCCOMB_X38_Y32_N30 cycloneive_lcell_comb \ula_|video_|attr_prefetch[3]~feeder ( // Equation(s): // \ula_|video_|attr_prefetch[3]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 @@ -59526,7 +59276,7 @@ defparam \ula_|video_|attr_prefetch[3]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|attr_prefetch[3]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N3 +// Location: FF_X38_Y32_N31 dffeas \ula_|video_|attr_prefetch[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr_prefetch[3]~feeder_combout ), @@ -59545,7 +59295,7 @@ defparam \ula_|video_|attr_prefetch[3] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[3] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y33_N29 +// Location: FF_X37_Y32_N17 dffeas \ula_|video_|attr[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -59564,48 +59314,48 @@ defparam \ula_|video_|attr[3] .is_wysiwyg = "true"; defparam \ula_|video_|attr[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N28 +// Location: LCCOMB_X37_Y32_N16 cycloneive_lcell_comb \ula_|video_|cindex[0]~3 ( // Equation(s): // \ula_|video_|cindex[0]~3_combout = (\ula_|video_|cindex[1]~0_combout & (\ula_|video_|attr [0])) # (!\ula_|video_|cindex[1]~0_combout & ((\ula_|video_|attr [3]))) - .dataa(gnd), - .datab(\ula_|video_|attr [0]), + .dataa(\ula_|video_|attr [0]), + .datab(gnd), .datac(\ula_|video_|attr [3]), .datad(\ula_|video_|cindex[1]~0_combout ), .cin(gnd), .combout(\ula_|video_|cindex[0]~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|cindex[0]~3 .lut_mask = 16'hCCF0; +defparam \ula_|video_|cindex[0]~3 .lut_mask = 16'hAAF0; defparam \ula_|video_|cindex[0]~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y33_N30 +// Location: LCCOMB_X37_Y32_N14 cycloneive_lcell_comb \ula_|video_|VGA_B[0]~1 ( // Equation(s): // \ula_|video_|VGA_B[0]~1_combout = (\ula_|video_|disp_enable~1_combout & ((\ula_|video_|screen_en~1_combout & ((\ula_|video_|cindex[0]~3_combout ))) # (!\ula_|video_|screen_en~1_combout & (\ula_|border [0])))) - .dataa(\ula_|video_|disp_enable~1_combout ), + .dataa(\ula_|video_|screen_en~1_combout ), .datab(\ula_|border [0]), - .datac(\ula_|video_|screen_en~1_combout ), + .datac(\ula_|video_|disp_enable~1_combout ), .datad(\ula_|video_|cindex[0]~3_combout ), .cin(gnd), .combout(\ula_|video_|VGA_B[0]~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|VGA_B[0]~1 .lut_mask = 16'hA808; +defparam \ula_|video_|VGA_B[0]~1 .lut_mask = 16'hE040; defparam \ula_|video_|VGA_B[0]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y33_N0 +// Location: LCCOMB_X37_Y32_N4 cycloneive_lcell_comb \ula_|video_|VGA_B[1]~2 ( // Equation(s): -// \ula_|video_|VGA_B[1]~2_combout = (\ula_|video_|screen_en~1_combout & (\ula_|video_|VGA_B[1]~0_combout & \ula_|video_|cindex[0]~3_combout )) +// \ula_|video_|VGA_B[1]~2_combout = (\ula_|video_|VGA_B[1]~0_combout & (\ula_|video_|screen_en~1_combout & \ula_|video_|cindex[0]~3_combout )) - .dataa(\ula_|video_|screen_en~1_combout ), + .dataa(\ula_|video_|VGA_B[1]~0_combout ), .datab(gnd), - .datac(\ula_|video_|VGA_B[1]~0_combout ), + .datac(\ula_|video_|screen_en~1_combout ), .datad(\ula_|video_|cindex[0]~3_combout ), .cin(gnd), .combout(\ula_|video_|VGA_B[1]~2_combout ), @@ -59615,24 +59365,24 @@ defparam \ula_|video_|VGA_B[1]~2 .lut_mask = 16'hA000; defparam \ula_|video_|VGA_B[1]~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y33_N26 +// Location: LCCOMB_X35_Y31_N22 cycloneive_lcell_comb \ula_|video_|Equal0~2 ( // Equation(s): -// \ula_|video_|Equal0~2_combout = (\ula_|video_|vga_hc [6] & (!\ula_|video_|vga_hc [9] & !\ula_|video_|vga_hc [8])) +// \ula_|video_|Equal0~2_combout = (!\ula_|video_|vga_hc [8] & (\ula_|video_|vga_hc [6] & !\ula_|video_|vga_hc [9])) - .dataa(\ula_|video_|vga_hc [6]), - .datab(\ula_|video_|vga_hc [9]), - .datac(gnd), - .datad(\ula_|video_|vga_hc [8]), + .dataa(gnd), + .datab(\ula_|video_|vga_hc [8]), + .datac(\ula_|video_|vga_hc [6]), + .datad(\ula_|video_|vga_hc [9]), .cin(gnd), .combout(\ula_|video_|Equal0~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Equal0~2 .lut_mask = 16'h0022; +defparam \ula_|video_|Equal0~2 .lut_mask = 16'h0030; defparam \ula_|video_|Equal0~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X37_Y33_N7 +// Location: FF_X35_Y31_N21 dffeas \ula_|video_|VGA_HS~_Duplicate_1 ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|Selector0~0_combout ), @@ -59651,21 +59401,21 @@ defparam \ula_|video_|VGA_HS~_Duplicate_1 .is_wysiwyg = "true"; defparam \ula_|video_|VGA_HS~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X37_Y33_N6 +// Location: LCCOMB_X35_Y31_N20 cycloneive_lcell_comb \ula_|video_|Selector0~0 ( // Equation(s): -// \ula_|video_|Selector0~0_combout = (\ula_|video_|Equal0~2_combout & ((\ula_|video_|Equal0~1_combout ) # ((\ula_|video_|Equal1~0_combout & \ula_|video_|VGA_HS~_Duplicate_1_q )))) # (!\ula_|video_|Equal0~2_combout & (\ula_|video_|Equal1~0_combout & -// (\ula_|video_|VGA_HS~_Duplicate_1_q ))) +// \ula_|video_|Selector0~0_combout = (\ula_|video_|Equal0~2_combout & ((\ula_|video_|Equal0~1_combout ) # ((\ula_|video_|VGA_HS~_Duplicate_1_q & \ula_|video_|Equal1~0_combout )))) # (!\ula_|video_|Equal0~2_combout & (((\ula_|video_|VGA_HS~_Duplicate_1_q +// & \ula_|video_|Equal1~0_combout )))) .dataa(\ula_|video_|Equal0~2_combout ), - .datab(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Equal0~1_combout ), .datac(\ula_|video_|VGA_HS~_Duplicate_1_q ), - .datad(\ula_|video_|Equal0~1_combout ), + .datad(\ula_|video_|Equal1~0_combout ), .cin(gnd), .combout(\ula_|video_|Selector0~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Selector0~0 .lut_mask = 16'hEAC0; +defparam \ula_|video_|Selector0~0 .lut_mask = 16'hF888; defparam \ula_|video_|Selector0~0 .sum_lutc_input = "datac"; // synopsys translate_on @@ -59688,7 +59438,7 @@ defparam \ula_|video_|VGA_HS .is_wysiwyg = "true"; defparam \ula_|video_|VGA_HS .power_up = "low"; // synopsys translate_on -// Location: FF_X34_Y33_N25 +// Location: FF_X35_Y32_N5 dffeas \ula_|video_|VGA_VS~_Duplicate_1 ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|Selector1~0_combout ), @@ -59707,21 +59457,21 @@ defparam \ula_|video_|VGA_VS~_Duplicate_1 .is_wysiwyg = "true"; defparam \ula_|video_|VGA_VS~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y33_N24 +// Location: LCCOMB_X35_Y32_N4 cycloneive_lcell_comb \ula_|video_|Selector1~0 ( // Equation(s): -// \ula_|video_|Selector1~0_combout = (\ula_|video_|Equal3~1_combout & (\ula_|video_|Equal2~2_combout & ((\ula_|video_|vga_vc [1])))) # (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|VGA_VS~_Duplicate_1_q ) # ((\ula_|video_|Equal2~2_combout & -// \ula_|video_|vga_vc [1])))) +// \ula_|video_|Selector1~0_combout = (\ula_|video_|Equal2~2_combout & ((\ula_|video_|vga_vc [1]) # ((\ula_|video_|VGA_VS~_Duplicate_1_q & !\ula_|video_|Equal3~1_combout )))) # (!\ula_|video_|Equal2~2_combout & (((\ula_|video_|VGA_VS~_Duplicate_1_q & +// !\ula_|video_|Equal3~1_combout )))) - .dataa(\ula_|video_|Equal3~1_combout ), - .datab(\ula_|video_|Equal2~2_combout ), + .dataa(\ula_|video_|Equal2~2_combout ), + .datab(\ula_|video_|vga_vc [1]), .datac(\ula_|video_|VGA_VS~_Duplicate_1_q ), - .datad(\ula_|video_|vga_vc [1]), + .datad(\ula_|video_|Equal3~1_combout ), .cin(gnd), .combout(\ula_|video_|Selector1~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Selector1~0 .lut_mask = 16'hDC50; +defparam \ula_|video_|Selector1~0 .lut_mask = 16'h88F8; defparam \ula_|video_|Selector1~0 .sum_lutc_input = "datac"; // synopsys translate_on @@ -59744,7 +59494,7 @@ defparam \ula_|video_|VGA_VS .is_wysiwyg = "true"; defparam \ula_|video_|VGA_VS .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X47_Y17_N4 +// Location: LCCOMB_X27_Y13_N26 cycloneive_lcell_comb \z80_|memory_ifc_|q1~feeder ( // Equation(s): // \z80_|memory_ifc_|q1~feeder_combout = \z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q @@ -59761,7 +59511,7 @@ defparam \z80_|memory_ifc_|q1~feeder .lut_mask = 16'hFF00; defparam \z80_|memory_ifc_|q1~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X47_Y17_N5 +// Location: FF_X27_Y13_N27 dffeas \z80_|memory_ifc_|q1 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|memory_ifc_|q1~feeder_combout ), @@ -59780,7 +59530,7 @@ defparam \z80_|memory_ifc_|q1 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|q1 .power_up = "low"; // synopsys translate_on -// Location: FF_X47_Y17_N25 +// Location: FF_X27_Y13_N17 dffeas \z80_|memory_ifc_|q2 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), @@ -59799,7 +59549,7 @@ defparam \z80_|memory_ifc_|q2 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|q2 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X47_Y17_N24 +// Location: LCCOMB_X27_Y13_N16 cycloneive_lcell_comb \z80_|memory_ifc_|nRFSH_out~0 ( // Equation(s): // \z80_|memory_ifc_|nRFSH_out~0_combout = (!\z80_|memory_ifc_|q2~q & \z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q ) @@ -59816,41 +59566,41 @@ defparam \z80_|memory_ifc_|nRFSH_out~0 .lut_mask = 16'h0F00; defparam \z80_|memory_ifc_|nRFSH_out~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X47_Y17_N26 +// Location: LCCOMB_X27_Y13_N20 cycloneive_lcell_comb \z80_|memory_ifc_|nM1_out ( // Equation(s): // \z80_|memory_ifc_|nM1_out~combout = (\z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - .dataa(gnd), + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(gnd), .datad(\z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q ), .cin(gnd), .combout(\z80_|memory_ifc_|nM1_out~combout ), .cout()); // synopsys translate_off -defparam \z80_|memory_ifc_|nM1_out .lut_mask = 16'hFF0F; +defparam \z80_|memory_ifc_|nM1_out .lut_mask = 16'hFF55; defparam \z80_|memory_ifc_|nM1_out .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y26_N0 +// Location: LCCOMB_X24_Y10_N28 cycloneive_lcell_comb \ula_|beep~0 ( // Equation(s): -// \ula_|beep~0_combout = \D[4]~98_combout $ (\raw_loader_in~input_o $ (\D[3]~96_combout )) +// \ula_|beep~0_combout = \raw_loader_in~input_o $ (\D[3]~74_combout $ (\D[4]~76_combout )) - .dataa(gnd), - .datab(\D[4]~98_combout ), - .datac(\raw_loader_in~input_o ), - .datad(\D[3]~96_combout ), + .dataa(\raw_loader_in~input_o ), + .datab(\D[3]~74_combout ), + .datac(gnd), + .datad(\D[4]~76_combout ), .cin(gnd), .combout(\ula_|beep~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|beep~0 .lut_mask = 16'hC33C; +defparam \ula_|beep~0 .lut_mask = 16'h9966; defparam \ula_|beep~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X23_Y26_N1 +// Location: FF_X24_Y10_N29 dffeas \ula_|beep ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\ula_|beep~0_combout ), diff --git a/simulation/modelsim/spectrum_6_1200mv_0c_slow.vo b/simulation/modelsim/spectrum_6_1200mv_0c_slow.vo index 5f5d1b7..cb25227 100644 --- a/simulation/modelsim/spectrum_6_1200mv_0c_slow.vo +++ b/simulation/modelsim/spectrum_6_1200mv_0c_slow.vo @@ -16,7 +16,7 @@ // PROGRAM "Quartus II 32-bit" // VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" -// DATE "04/01/2022 18:55:51" +// DATE "04/02/2022 15:53:44" // // Device: Altera EP4CE22F17C6 Package FBGA256 @@ -56,8 +56,8 @@ input CLOCK_50; input [1:0] KEY; input PS2_CLK; input PS2_DAT; -output I2C_SCLK; -output I2C_SDAT; +inout I2C_SCLK; +inout I2C_SDAT; output AUD_XCK; output AUD_ADCLRCK; output AUD_DACLRCK; @@ -178,786 +178,67 @@ wire \SW[2]~input_o ; wire \ula_|clocks_|clk_cpu~0_combout ; wire \ula_|clocks_|clk_cpu~q ; wire \ula_|clocks_|clk_cpu~clkctrl_outclk ; -wire \z80_|sequencer_|DFFE_M1_ff~0_combout ; -wire \z80_|sequencer_|ena_M~combout ; +wire \z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ; +wire \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ; wire \KEY[1]~input_o ; wire \z80_|interrupts_|nmi_armed~feeder_combout ; wire \z80_|interrupts_|SYNTHESIZED_WIRE_9~combout ; wire \z80_|interrupts_|nmi_armed~q ; wire \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder_combout ; -wire \z80_|execute_|ctl_eval_cond~0_combout ; -wire \z80_|execute_|ixy_d~4_combout ; +wire \z80_|sequencer_|DFFE_M2_ff~0_combout ; +wire \z80_|sequencer_|DFFE_M2_ff~q ; wire \z80_|sequencer_|DFFE_M3_ff~0_combout ; wire \z80_|sequencer_|DFFE_M3_ff~q ; -wire \z80_|execute_|fIOWrite~1_combout ; wire \z80_|sequencer_|DFFE_M4_ff~0_combout ; wire \z80_|sequencer_|DFFE_M4_ff~q ; -wire \z80_|pla_decode_|Equal32~0_combout ; -wire \z80_|resets_|SYNTHESIZED_WIRE_11~combout ; -wire \z80_|decode_state_|table_xx~0_combout ; -wire \z80_|pla_decode_|Equal1~7_combout ; -wire \z80_|pla_decode_|Equal2~0_combout ; -wire \z80_|pla_decode_|Equal36~0_combout ; -wire \z80_|execute_|ctl_state_tbl_cb_set~combout ; -wire \z80_|execute_|ctl_state_tbl_we~8_combout ; -wire \z80_|decode_state_|DFFE_instCB~q ; -wire \z80_|pla_decode_|Equal52~0_combout ; -wire \z80_|pla_decode_|Equal2~1_combout ; -wire \z80_|execute_|ctl_state_tbl_ed_set~combout ; -wire \z80_|decode_state_|DFFE_instED~q ; -wire \z80_|pla_decode_|Equal13~0_combout ; -wire \z80_|pla_decode_|Equal33~0_combout ; -wire \z80_|execute_|ctl_im_we~combout ; -wire \z80_|pla_decode_|Equal49~0_combout ; -wire \z80_|pla_decode_|Equal33~1_combout ; -wire \z80_|pla_decode_|Equal6~0_combout ; -wire \z80_|execute_|ctl_mRead~14_combout ; -wire \z80_|pla_decode_|Equal12~0_combout ; -wire \z80_|execute_|ctl_sw_1d~8_combout ; -wire \z80_|nM1_int~2_combout ; -wire \z80_|execute_|ctl_sw_1d~5_combout ; -wire \z80_|pla_decode_|Equal3~0_combout ; -wire \z80_|execute_|ctl_mRead~4_combout ; -wire \z80_|execute_|ixy_d~7_combout ; -wire \z80_|execute_|ctl_state_alu~4_combout ; -wire \z80_|execute_|ctl_sw_1d~4_combout ; -wire \z80_|pla_decode_|Equal40~1_combout ; -wire \z80_|pla_decode_|Equal39~0_combout ; -wire \z80_|execute_|ctl_bus_db_oe~1_combout ; -wire \z80_|pla_decode_|Equal13~1_combout ; -wire \z80_|pla_decode_|Equal13~2_combout ; -wire \z80_|pla_decode_|Equal3~2_combout ; -wire \z80_|execute_|ctl_state_iy_set~2_combout ; -wire \z80_|execute_|ixy_d~8_combout ; -wire \z80_|execute_|ixy_d~6_combout ; -wire \z80_|execute_|ixy_d~9_combout ; -wire \z80_|execute_|ixy_d~12_combout ; -wire \z80_|execute_|ixy_d~10_combout ; -wire \z80_|pla_decode_|Equal44~0_combout ; -wire \z80_|execute_|ixy_d~16_combout ; -wire \z80_|execute_|ixy_d~13_combout ; -wire \z80_|pla_decode_|Equal50~0_combout ; -wire \z80_|pla_decode_|Equal33~2_combout ; -wire \z80_|execute_|ixy_d~17_combout ; -wire \z80_|execute_|ixy_d~5_combout ; -wire \z80_|execute_|ixy_d~14_combout ; -wire \z80_|execute_|ixy_d~11_combout ; -wire \z80_|execute_|ixy_d~15_combout ; -wire \z80_|execute_|ctl_state_ixiy_we~2_combout ; -wire \z80_|decode_state_|DFFE_instIY1~q ; -wire \z80_|execute_|ctl_ir_we~5_combout ; -wire \z80_|execute_|ctl_ir_we~14_combout ; -wire \z80_|execute_|ctl_mWrite~2_combout ; -wire \z80_|execute_|ctl_mWrite~16_combout ; -wire \z80_|execute_|ctl_flags_alu~18_combout ; -wire \z80_|execute_|ctl_mRead~26_combout ; -wire \z80_|execute_|ctl_mRead~27_combout ; -wire \z80_|execute_|ctl_bus_db_oe~7_combout ; -wire \z80_|execute_|ctl_sw_2d~5_combout ; -wire \z80_|execute_|ctl_mRead~18_combout ; -wire \z80_|pla_decode_|Equal55~0_combout ; -wire \z80_|execute_|comb~1_combout ; -wire \z80_|execute_|ctl_mRead~15_combout ; -wire \z80_|execute_|ctl_mRead~17_combout ; -wire \z80_|execute_|ctl_reg_in_hi~5_combout ; -wire \z80_|execute_|ctl_mRead~9_combout ; -wire \z80_|pla_decode_|Equal9~0_combout ; -wire \z80_|execute_|ctl_mRead~10_combout ; -wire \z80_|execute_|ctl_mRead~8_combout ; -wire \z80_|execute_|ctl_mRead~20_combout ; -wire \z80_|pla_decode_|Equal12~1_combout ; -wire \z80_|pla_decode_|Equal9~1_combout ; -wire \z80_|pla_decode_|Equal25~0_combout ; -wire \z80_|execute_|ctl_mRead~21_combout ; -wire \z80_|execute_|ctl_state_alu~6_combout ; -wire \z80_|pla_decode_|Equal19~0_combout ; -wire \z80_|pla_decode_|Equal1~4_combout ; -wire \z80_|pla_decode_|Equal29~0_combout ; -wire \z80_|pla_decode_|Equal24~1_combout ; -wire \z80_|pla_decode_|Equal34~0_combout ; -wire \z80_|pla_decode_|Equal37~0_combout ; -wire \z80_|pla_decode_|Equal35~0_combout ; -wire \z80_|pla_decode_|Equal38~2_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~2_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~3_combout ; -wire \z80_|execute_|comb~0_combout ; -wire \z80_|pla_decode_|Equal47~0_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~4_combout ; -wire \z80_|execute_|ctl_mRead~22_combout ; -wire \z80_|execute_|ctl_mRead~24_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ; -wire \z80_|execute_|ctl_reg_in_hi~6_combout ; -wire \z80_|pla_decode_|Equal6~1_combout ; -wire \z80_|execute_|ctl_mRead~16_combout ; wire \z80_|sequencer_|M5~0_combout ; wire \z80_|sequencer_|M5~q ; -wire \z80_|execute_|ctl_reg_in_hi~2_combout ; -wire \z80_|execute_|setM1~29_combout ; -wire \z80_|execute_|ctl_mRead~25_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~6_combout ; -wire \z80_|execute_|ctl_ir_we~7_combout ; -wire \z80_|pla_decode_|Equal52~1_combout ; -wire \z80_|execute_|ctl_state_alu~14_combout ; -wire \z80_|execute_|ctl_state_alu~8_combout ; -wire \z80_|pla_decode_|Equal24~0_combout ; -wire \z80_|reg_control_|reg_sel_pc~0_combout ; -wire \z80_|reg_control_|reg_sel_pc~1_combout ; -wire \z80_|reg_control_|reg_sel_pc~2_combout ; -wire \z80_|execute_|fMRead~17_combout ; -wire \z80_|execute_|ctl_mRead~6_combout ; -wire \z80_|pla_decode_|Equal11~0_combout ; -wire \z80_|pla_decode_|Equal10~0_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~9_combout ; -wire \z80_|execute_|ctl_sw_2d~4_combout ; -wire \z80_|execute_|ctl_ir_we~15_combout ; -wire \z80_|execute_|fMRead~16_combout ; -wire \z80_|execute_|ctl_ir_we~9_combout ; -wire \z80_|pla_decode_|Equal46~0_combout ; -wire \z80_|execute_|ctl_ir_we~10_combout ; -wire \z80_|execute_|ctl_flags_alu~17_combout ; -wire \z80_|execute_|ctl_flags_alu~6_combout ; -wire \z80_|execute_|ctl_ir_we~6_combout ; -wire \z80_|execute_|ctl_ir_we~8_combout ; -wire \z80_|execute_|ctl_flags_alu~16_combout ; -wire \z80_|execute_|ctl_reg_in_hi~3_combout ; -wire \z80_|execute_|ctl_mWrite~8_combout ; -wire \z80_|execute_|fMRead~18_combout ; -wire \z80_|execute_|fMRead~19_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~16_combout ; -wire \z80_|execute_|ctl_mRead~36_combout ; -wire \z80_|execute_|ctl_alu_op_low~9_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~44_combout ; -wire \z80_|execute_|ctl_mRead~11_combout ; -wire \z80_|execute_|ctl_sw_2d~6_combout ; -wire \z80_|execute_|ctl_sw_2d~7_combout ; -wire \z80_|execute_|ctl_mWrite~7_combout ; -wire \z80_|execute_|ctl_ir_we~11_combout ; -wire \z80_|execute_|ctl_ir_we~12_combout ; -wire \z80_|execute_|ctl_flags_sz_we~0_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ; -wire \z80_|execute_|ctl_sw_2d~8_combout ; -wire \z80_|execute_|ctl_sw_2d~9_combout ; -wire \z80_|execute_|ctl_sw_1d~6_combout ; -wire \z80_|execute_|ctl_sw_1d~7_combout ; -wire \z80_|execute_|ctl_alu_op_low~8_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ; -wire \z80_|execute_|ctl_reg_out_hi~4_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~15_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~38_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_zero~combout ; -wire \z80_|alu_|db_low[2]~4_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~14_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ; -wire \z80_|execute_|ctl_sw_4u~1_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~5_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~30_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~29_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~31_combout ; -wire \z80_|pla_decode_|Equal69~0_combout ; -wire \z80_|pla_decode_|Equal1~5_combout ; -wire \z80_|execute_|ctl_alu_op_low~14_combout ; -wire \z80_|execute_|ctl_alu_op_low~12_combout ; -wire \z80_|pla_decode_|Equal56~0_combout ; -wire \z80_|execute_|ctl_alu_op_low~11_combout ; -wire \z80_|execute_|nextM~2_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~16_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~4_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~5_combout ; -wire \z80_|execute_|ctl_alu_oe~3_combout ; -wire \z80_|execute_|ctl_alu_op_low~15_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~8_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~9_combout ; -wire \z80_|execute_|ctl_alu_core_R~3_combout ; -wire \z80_|execute_|ctl_alu_core_R~4_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~10_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~11_combout ; -wire \z80_|pla_decode_|Equal48~0_combout ; -wire \z80_|execute_|ctl_flags_hf2_we~combout ; -wire \z80_|execute_|ctl_alu_shift_oe~41_combout ; -wire \z80_|execute_|ctl_flags_xy_we~18_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~17_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~19_combout ; -wire \z80_|execute_|ctl_iorw~10_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~18_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~20_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~13_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~9_combout ; -wire \z80_|execute_|ctl_bus_db_oe~3_combout ; -wire \z80_|pla_decode_|Equal20~0_combout ; -wire \z80_|pla_decode_|Equal68~2_combout ; -wire \z80_|execute_|ctl_flags_bus~14_combout ; -wire \z80_|execute_|ctl_alu_op_low~13_combout ; -wire \z80_|execute_|ctl_flags_bus~15_combout ; -wire \z80_|execute_|ctl_flags_bus~11_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~11_combout ; -wire \z80_|execute_|ctl_flags_bus~10_combout ; -wire \z80_|execute_|ctl_flags_bus~8_combout ; -wire \z80_|execute_|ctl_flags_bus~9_combout ; -wire \z80_|execute_|ctl_flags_bus~12_combout ; -wire \z80_|execute_|ctl_flags_xy_we~11_combout ; -wire \z80_|execute_|ctl_flags_xy_we~12_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~6_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~7_combout ; -wire \z80_|execute_|ctl_ir_we~4_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~8_combout ; -wire \z80_|execute_|ctl_bus_db_oe~0_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~12_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~13_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~14_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~15_combout ; -wire \z80_|execute_|ctl_66_oe~2_combout ; -wire \z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ; -wire \z80_|execute_|ctl_alu_op1_sel_zero~5_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_zero~4_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_zero~combout ; -wire \z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_lq~combout ; -wire \z80_|execute_|ctl_alu_op_low~10_combout ; -wire \z80_|execute_|fMWrite~11_combout ; -wire \z80_|execute_|ctl_alu_op_low~21_combout ; +wire \z80_|execute_|ixy_d~5_combout ; wire \z80_|execute_|ctl_alu_op_low~22_combout ; -wire \z80_|execute_|ctl_alu_op_low~16_combout ; -wire \z80_|execute_|ctl_alu_op_low~17_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ; -wire \z80_|execute_|ctl_reg_gp_sel~36_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~4_combout ; -wire \z80_|execute_|ctl_state_alu~5_combout ; -wire \z80_|execute_|ctl_alu_op_low~18_combout ; -wire \z80_|execute_|ctl_alu_op_low~19_combout ; -wire \z80_|execute_|ctl_alu_op_low~33_combout ; -wire \z80_|execute_|ctl_alu_op_low~20_combout ; -wire \z80_|execute_|ctl_alu_op_low~23_combout ; -wire \z80_|execute_|ctl_alu_op_low~24_combout ; -wire \z80_|execute_|ctl_alu_op_low~25_combout ; -wire \z80_|execute_|ctl_alu_op_low~34_combout ; -wire \z80_|execute_|ctl_alu_op_low~combout ; -wire \z80_|execute_|ctl_alu_shift_oe~40_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~37_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~39_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~46_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~42_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~21_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~45_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~22_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~23_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~24_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~25_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~14_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~26_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~27_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~28_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~10_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~11_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~32_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~33_combout ; -wire \z80_|execute_|ctl_reg_use_sp~0_combout ; -wire \z80_|execute_|ctl_reg_use_sp~1_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~12_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~47_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~34_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~35_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~36_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~43_combout ; -wire \z80_|execute_|ctl_reg_in_lo~9_combout ; -wire \z80_|execute_|ctl_alu_op1_oe~0_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ; -wire \z80_|execute_|ctl_alu_op1_oe~1_combout ; -wire \z80_|execute_|ctl_flags_xy_we~8_combout ; -wire \z80_|execute_|ctl_flags_xy_we~9_combout ; -wire \z80_|pla_decode_|Equal8~0_combout ; -wire \z80_|execute_|ctl_flags_alu~9_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~4_combout ; -wire \z80_|execute_|ctl_flags_sz_we~3_combout ; -wire \z80_|pla_decode_|Equal11~1_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ; -wire \z80_|execute_|ctl_flags_alu~10_combout ; -wire \z80_|execute_|ctl_flags_alu~11_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ; -wire \z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ; -wire \z80_|execute_|ctl_flags_use_cf2~13_combout ; -wire \z80_|execute_|ctl_flags_cf_we~7_combout ; -wire \z80_|execute_|ctl_pf_sel[0]~2_combout ; -wire \z80_|execute_|ctl_alu_oe~2_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~25_combout ; -wire \z80_|execute_|ctl_flags_hf_we~5_combout ; -wire \z80_|execute_|ctl_flags_pf_we~10_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ; -wire \z80_|execute_|ctl_flags_pf_we~2_combout ; -wire \z80_|execute_|ctl_flags_pf_we~3_combout ; -wire \z80_|execute_|ctl_flags_xy_we~17_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~5_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~6_combout ; -wire \z80_|execute_|ctl_flags_xy_we~10_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ; -wire \z80_|execute_|ctl_state_alu~7_combout ; -wire \z80_|execute_|ctl_flags_sz_we~1_combout ; -wire \z80_|execute_|ctl_flags_cf_we~2_combout ; -wire \z80_|execute_|ctl_alu_core_S~6_combout ; -wire \z80_|execute_|ctl_alu_core_S~7_combout ; -wire \z80_|execute_|ctl_alu_core_S~4_combout ; -wire \z80_|execute_|ctl_alu_core_S~5_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ; -wire \z80_|execute_|ctl_alu_res_oe~0_combout ; -wire \z80_|execute_|ctl_alu_oe~15_combout ; -wire \z80_|execute_|ctl_alu_res_oe~1_combout ; -wire \z80_|execute_|ctl_alu_res_oe~2_combout ; -wire \z80_|execute_|ctl_alu_op2_oe~0_combout ; -wire \z80_|alu_|db_high[3]~2_combout ; -wire \z80_|alu_|db_high[3]~3_combout ; -wire \z80_|alu_|db_low[2]~24_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~7_combout ; -wire \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ; -wire \z80_|execute_|ctl_reg_in_hi~8_combout ; -wire \z80_|execute_|ctl_alu_oe~8_combout ; -wire \z80_|execute_|ctl_alu_oe~4_combout ; -wire \z80_|execute_|ctl_mWrite~9_combout ; -wire \z80_|execute_|ctl_alu_core_S~10_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~43_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~26_combout ; -wire \z80_|execute_|ctl_bus_db_we~5_combout ; -wire \z80_|execute_|ctl_alu_oe~9_combout ; -wire \z80_|execute_|ctl_alu_oe~11_combout ; -wire \z80_|execute_|ctl_alu_oe~5_combout ; -wire \z80_|execute_|ctl_alu_core_S~11_combout ; -wire \z80_|execute_|ctl_alu_oe~6_combout ; -wire \z80_|execute_|ctl_alu_oe~7_combout ; -wire \z80_|execute_|ctl_alu_oe~12_combout ; -wire \z80_|execute_|ctl_alu_oe~13_combout ; -wire \z80_|execute_|ctl_alu_oe~14_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~24_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~27_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ; -wire \z80_|execute_|ctl_reg_out_hi~8_combout ; -wire \z80_|execute_|setM1~54_combout ; -wire \z80_|execute_|ctl_sw_2u~1_combout ; -wire \z80_|execute_|ctl_sw_2u~4_combout ; -wire \z80_|execute_|ctl_sw_2u~5_combout ; -wire \z80_|execute_|ctl_sw_2u~6_combout ; -wire \z80_|execute_|ctl_inc_cy~35_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ; -wire \z80_|execute_|ctl_mWrite~6_combout ; -wire \z80_|execute_|ctl_sw_2u~2_combout ; -wire \z80_|execute_|ctl_sw_2u~0_combout ; -wire \z80_|execute_|ctl_sw_2u~3_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ; -wire \z80_|execute_|ctl_reg_out_lo~2_combout ; -wire \z80_|execute_|rsel3~combout ; -wire \z80_|execute_|ctl_reg_out_hi~5_combout ; -wire \z80_|execute_|ctl_reg_out_hi~6_combout ; -wire \z80_|execute_|ctl_reg_out_hi~7_combout ; -wire \z80_|execute_|rsel0~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ; -wire \z80_|execute_|ctl_reg_out_lo~6_combout ; -wire \z80_|execute_|ctl_reg_out_lo~7_combout ; -wire \z80_|execute_|ctl_iorw~11_combout ; -wire \z80_|execute_|ctl_sw_2d~10_combout ; -wire \z80_|execute_|ctl_sw_2d~14_combout ; -wire \z80_|execute_|ctl_sw_2d~11_combout ; -wire \z80_|execute_|ctl_sw_2d~12_combout ; -wire \z80_|execute_|ctl_sw_2d~13_combout ; -wire \z80_|execute_|ctl_66_oe~combout ; -wire \z80_|execute_|ctl_inc_cy~34_combout ; -wire \z80_|execute_|ctl_apin_mux~0_combout ; -wire \z80_|execute_|ctl_sw_4u~5_combout ; -wire \z80_|execute_|ctl_inc_cy~75_combout ; -wire \z80_|execute_|ctl_inc_cy~76_combout ; -wire \z80_|pla_decode_|Equal4~0_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~48_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~46_combout ; -wire \z80_|execute_|ctl_inc_cy~53_combout ; -wire \z80_|execute_|ctl_inc_cy~92_combout ; -wire \z80_|pla_decode_|Equal19~1_combout ; -wire \z80_|execute_|ctl_sw_4u~0_combout ; -wire \z80_|execute_|ctl_inc_cy~38_combout ; -wire \z80_|execute_|ctl_inc_cy~93_combout ; -wire \z80_|execute_|ctl_inc_cy~39_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~24_combout ; -wire \z80_|execute_|ctl_reg_gp_we~1_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ; -wire \z80_|execute_|ctl_bus_inc_oe~44_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~5_combout ; -wire \z80_|execute_|ctl_reg_gp_we~0_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ; -wire \z80_|execute_|ctl_sw_4u~2_combout ; -wire \z80_|execute_|ctl_sw_4u~3_combout ; -wire \z80_|execute_|fMRead~3_combout ; -wire \z80_|execute_|ctl_sw_4u~4_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ; -wire \z80_|execute_|ctl_reg_sel_wz~15_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ; -wire \z80_|execute_|ctl_inc_cy~94_combout ; -wire \z80_|execute_|ctl_inc_cy~87_combout ; -wire \z80_|execute_|ctl_inc_cy~42_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~16_combout ; -wire \z80_|execute_|ctl_sw_4u~6_combout ; -wire \z80_|pla_decode_|Equal2~2_combout ; -wire \z80_|pla_decode_|Equal1~6_combout ; -wire \z80_|reg_control_|bank_exx~2_combout ; -wire \z80_|reg_control_|bank_exx~q ; -wire \z80_|reg_control_|bank_hl_de1~0_combout ; -wire \z80_|reg_control_|bank_hl_de1~q ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~10_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~11_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~12_combout ; -wire \z80_|execute_|ctl_mRead~7_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~9_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~37_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~13_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ; -wire \z80_|execute_|fMWrite~3_combout ; -wire \z80_|execute_|ctl_flags_bus~5_combout ; -wire \z80_|execute_|fMRead~2_combout ; -wire \z80_|execute_|ctl_mRead~19_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~7_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~8_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~14_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~16_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~15_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~17_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~19_combout ; -wire \z80_|execute_|ctl_reg_use_sp~2_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~47_combout ; -wire \z80_|execute_|ctl_reg_use_sp~3_combout ; -wire \z80_|execute_|ctl_sw_1d~9_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~21_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~20_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~22_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~18_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~23_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~28_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ; -wire \z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ; -wire \z80_|execute_|ctl_flags_hf_cpl~14_combout ; -wire \z80_|execute_|ctl_flags_hf_cpl~10_combout ; -wire \z80_|execute_|setM1~47_combout ; -wire \z80_|execute_|setM1~48_combout ; -wire \z80_|execute_|ctl_al_we~13_combout ; -wire \z80_|execute_|ctl_flags_oe~0_combout ; -wire \z80_|execute_|ctl_flags_oe~1_combout ; -wire \z80_|execute_|ctl_reg_in_hi~13_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~29_combout ; -wire \z80_|execute_|ctl_inc_cy~40_combout ; -wire \z80_|execute_|ctl_inc_dec~2_combout ; -wire \z80_|execute_|ctl_inc_dec~12_combout ; -wire \z80_|execute_|ctl_inc_cy~43_combout ; -wire \z80_|execute_|ctl_inc_dec~5_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~4_combout ; -wire \z80_|execute_|fMRead~6_combout ; -wire \z80_|execute_|fMRead~7_combout ; -wire \z80_|execute_|fMRead~8_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~26_combout ; -wire \z80_|execute_|ctl_state_alu~13_combout ; -wire \z80_|execute_|ctl_state_alu~10_combout ; -wire \z80_|execute_|ctl_state_alu~11_combout ; -wire \z80_|execute_|ctl_state_alu~9_combout ; -wire \z80_|pla_decode_|Equal62~2_combout ; -wire \z80_|execute_|ctl_flags_pf_we~4_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ; -wire \z80_|pla_decode_|Equal64~0_combout ; -wire \z80_|execute_|ctl_pf_sel[0]~3_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ; -wire \z80_|execute_|ctl_state_alu~15_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~25_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~30_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~31_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~33_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~34_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo~20_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~32_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ; -wire \z80_|reg_control_|reg_sel_de2~5_combout ; -wire \z80_|reg_control_|reg_sel_de2~6_combout ; -wire \z80_|reg_control_|reg_sel_hl~0_combout ; -wire \z80_|reg_control_|bank_hl_de2~0_combout ; -wire \z80_|reg_control_|bank_hl_de2~q ; -wire \z80_|reg_control_|reg_sel_hl2~0_combout ; -wire \z80_|execute_|ctl_reg_in_hi~7_combout ; -wire \z80_|execute_|ctl_reg_gp_we~4_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ; -wire \z80_|execute_|ctl_reg_gp_we~3_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~13_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5~combout ; -wire \z80_|execute_|ctl_reg_gp_we~2_combout ; -wire \z80_|execute_|ctl_reg_gp_we~5_combout ; -wire \z80_|execute_|ctl_reg_gp_we~6_combout ; -wire \z80_|execute_|ctl_al_we~14_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~32_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ; -wire \z80_|execute_|setM1~40_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~93_combout ; -wire \z80_|reg_control_|reg_sel_de~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ; -wire \z80_|execute_|ctl_reg_in_hi~9_combout ; -wire \z80_|execute_|ctl_reg_in_hi~10_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~19_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ; -wire \z80_|execute_|ctl_reg_in_lo~8_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~19_combout ; -wire \z80_|execute_|ctl_reg_use_sp~4_combout ; -wire \z80_|execute_|ctl_reg_use_sp~5_combout ; -wire \z80_|execute_|ctl_reg_use_sp~6_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ; -wire \z80_|pla_decode_|Equal21~2_combout ; -wire \z80_|reg_control_|bank_af~0_combout ; -wire \z80_|reg_control_|bank_af~q ; -wire \z80_|reg_control_|reg_sel_af~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ; -wire \z80_|reg_control_|reg_sel_af2~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ; -wire \z80_|execute_|ctl_reg_sel_wz~12_combout ; -wire \z80_|execute_|ctl_flags_bus~4_combout ; -wire \z80_|execute_|ctl_flags_bus~6_combout ; -wire \z80_|execute_|ctl_flags_bus~7_combout ; -wire \z80_|execute_|fMRead~24_combout ; -wire \z80_|execute_|ctl_flags_bus~13_combout ; -wire \z80_|execute_|ctl_flags_bus~combout ; -wire \z80_|execute_|ctl_inc_dec~3_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~2_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~3_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~6_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~5_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~4_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~7_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~8_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~9_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~10_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~29_combout ; -wire \z80_|execute_|ctl_mRead~13_combout ; -wire \z80_|execute_|pc_inc_hold~49_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~9_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ; -wire \z80_|execute_|pc_inc_hold~28_combout ; -wire \z80_|execute_|setM1~35_combout ; -wire \z80_|execute_|setM1~36_combout ; -wire \z80_|execute_|fMRead~5_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~31_combout ; -wire \z80_|execute_|pc_inc_hold~29_combout ; -wire \z80_|execute_|ctl_reg_sys_we~1_combout ; -wire \z80_|execute_|ctl_reg_sys_we~2_combout ; -wire \z80_|pla_decode_|Equal33~3_combout ; -wire \z80_|execute_|ctl_reg_sys_we~0_combout ; -wire \z80_|execute_|ctl_reg_sys_we~3_combout ; -wire \z80_|execute_|ctl_reg_sys_we_lo~2_combout ; -wire \z80_|execute_|ctl_reg_sys_we_lo~3_combout ; -wire \z80_|execute_|ctl_reg_sys_we_lo~4_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~combout ; -wire \z80_|execute_|ctl_reg_sel_ir~0_combout ; -wire \z80_|execute_|ctl_reg_sel_ir~1_combout ; -wire \z80_|execute_|ctl_reg_out_lo~9_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~36_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ; -wire \z80_|execute_|ctl_reg_in_hi~4_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~4_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ; -wire \z80_|execute_|ctl_reg_sel_wz~5_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~6_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~7_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo~16_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~11_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~12_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~13_combout ; -wire \z80_|execute_|ctl_al_we~4_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~38_combout ; -wire \z80_|execute_|fMRead~0_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ; -wire \z80_|execute_|ctl_inc_dec~4_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~9_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~8_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ; -wire \z80_|execute_|ctl_al_we~5_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~18_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[0]~37_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ; -wire \z80_|execute_|ctl_bus_inc_oe~38_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~39_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~30_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~45_combout ; -wire \z80_|execute_|fMRead~1_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~36_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~27_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~28_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~37_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~40_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~35_combout ; -wire \z80_|execute_|ctl_inc_cy~77_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~32_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~33_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~34_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~41_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~10_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~11_combout ; -wire \z80_|execute_|ctl_sw_4d~3_combout ; -wire \z80_|execute_|ctl_sw_4d~4_combout ; -wire \z80_|execute_|ctl_sw_4d~2_combout ; -wire \z80_|execute_|ctl_sw_4d~5_combout ; -wire \z80_|execute_|setM1~45_combout ; -wire \z80_|execute_|setM1~46_combout ; -wire \z80_|execute_|ctl_sw_4d~1_combout ; -wire \z80_|execute_|ctl_sw_4d~0_combout ; -wire \z80_|execute_|ctl_sw_4d~6_combout ; -wire \z80_|execute_|fMRead~4_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~16_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~14_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~20_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~15_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~17_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~18_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~19_combout ; -wire \z80_|reg_control_|reg_sel_pc~3_combout ; -wire \z80_|reg_control_|reg_sel_pc~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ; -wire \z80_|reg_file_|db_lo_as[0]~2_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ; -wire \z80_|reg_file_|db_lo_as[7]~22_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ; -wire \z80_|reg_file_|db_lo_as[7]~23_combout ; -wire \z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ; -wire \z80_|resets_|SYNTHESIZED_WIRE_10~q ; -wire \z80_|resets_|SYNTHESIZED_WIRE_9~q ; -wire \z80_|resets_|DFFE_intr_ff3~q ; -wire \ula_|pll_|altpll_component|auto_generated|wire_pll1_locked ; -wire \KEY[0]~input_o ; -wire \reset~combout ; -wire \z80_|resets_|x1~0_combout ; -wire \z80_|fpga_reset~feeder_combout ; -wire \z80_|fpga_reset~q ; -wire \z80_|fpga_reset~clkctrl_outclk ; -wire \z80_|resets_|x1~q ; -wire \z80_|resets_|clrpc_int~0_combout ; -wire \z80_|resets_|clrpc_int~q ; -wire \z80_|resets_|clrpc~0_combout ; -wire \z80_|execute_|ctl_apin_mux~1_combout ; -wire \z80_|execute_|ctl_al_we~6_combout ; -wire \z80_|execute_|ctl_al_we~7_combout ; -wire \z80_|execute_|ctl_al_we~8_combout ; -wire \z80_|execute_|ctl_alu_oe~10_combout ; -wire \z80_|execute_|ctl_al_we~9_combout ; -wire \z80_|execute_|ctl_al_we~10_combout ; -wire \z80_|execute_|ctl_al_we~11_combout ; -wire \z80_|execute_|ctl_al_we~12_combout ; -wire \z80_|execute_|ctl_inc_dec~6_combout ; -wire \z80_|execute_|fIOWrite~0_combout ; -wire \z80_|execute_|ctl_inc_dec~8_combout ; -wire \z80_|execute_|ctl_inc_dec~9_combout ; -wire \z80_|execute_|ctl_inc_dec~10_combout ; -wire \z80_|execute_|ctl_inc_dec~7_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~34_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ; -wire \z80_|reg_control_|reg_sel_de2~4_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~33_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~36_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~37_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~39_combout ; -wire \z80_|reg_control_|reg_sel_iy~2_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~38_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ; -wire \z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~35_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~40_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~41_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~42_combout ; -wire \z80_|reg_file_|db_lo_as[2]~7_combout ; -wire \z80_|reg_file_|db_lo_as[2]~8_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~10_combout ; -wire \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~11_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~15_combout ; -wire \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~14_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~16_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~12_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~13_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~17_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~22_combout ; -wire \z80_|reg_file_|db_lo_as[0]~0_combout ; -wire \z80_|reg_file_|db_lo_as[0]~1_combout ; -wire \z80_|execute_|ctl_inc_cy~72_combout ; +wire \z80_|resets_|SYNTHESIZED_WIRE_11~combout ; +wire \z80_|execute_|ctl_ir_we~4_combout ; +wire \z80_|execute_|ctl_state_iy_set~2_combout ; +wire \z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ; +wire \z80_|sequencer_|DFFE_T5_ff~q ; +wire \z80_|execute_|ctl_state_ixiy_we~2_combout ; +wire \z80_|decode_state_|DFFE_instIY1~q ; +wire \z80_|decode_state_|use_ixiy~combout ; +wire \z80_|execute_|ixy_d~4_combout ; +wire \z80_|execute_|ixy_d~11_combout ; +wire \z80_|execute_|ixy_d~9_combout ; +wire \z80_|execute_|ixy_d~7_combout ; +wire \z80_|execute_|ixy_d~6_combout ; +wire \z80_|execute_|ixy_d~8_combout ; +wire \z80_|execute_|ixy_d~12_combout ; +wire \z80_|pla_decode_|Equal33~0_combout ; +wire \z80_|pla_decode_|Equal33~1_combout ; +wire \z80_|pla_decode_|Equal33~2_combout ; +wire \z80_|pla_decode_|Equal21~0_combout ; +wire \z80_|pla_decode_|Equal77~0_combout ; +wire \z80_|pla_decode_|Equal77~1_combout ; +wire \z80_|pla_decode_|Equal1~7_combout ; +wire \z80_|pla_decode_|Equal79~0_combout ; +wire \z80_|interrupts_|iff1~0_combout ; +wire \z80_|interrupts_|DFFE_instIFF2~0_combout ; +wire \z80_|interrupts_|SYNTHESIZED_WIRE_12~combout ; +wire \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl_outclk ; +wire \z80_|interrupts_|DFFE_instIFF2~q ; +wire \z80_|pla_decode_|Equal13~0_combout ; +wire \z80_|pla_decode_|Equal38~2_combout ; +wire \z80_|interrupts_|iff1~1_combout ; +wire \z80_|interrupts_|SYNTHESIZED_WIRE_15~combout ; +wire \z80_|interrupts_|iff1~q ; wire \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ; -wire \ula_|video_|Add0~15 ; -wire \ula_|video_|Add0~16_combout ; -wire \ula_|video_|vga_hc~2_combout ; -wire \ula_|video_|Add0~17 ; -wire \ula_|video_|Add0~18_combout ; -wire \ula_|video_|vga_hc~1_combout ; wire \ula_|video_|Add0~0_combout ; wire \ula_|video_|vga_hc~3_combout ; wire \ula_|video_|Add0~1 ; wire \ula_|video_|Add0~2_combout ; -wire \ula_|video_|vga_hc[1]~feeder_combout ; wire \ula_|video_|Add0~3 ; wire \ula_|video_|Add0~4_combout ; wire \ula_|video_|Add0~5 ; wire \ula_|video_|Add0~6_combout ; -wire \ula_|video_|vga_hc[3]~feeder_combout ; wire \ula_|video_|Add0~7 ; wire \ula_|video_|Add0~8_combout ; -wire \ula_|video_|Equal0~0_combout ; -wire \ula_|video_|Equal0~1_combout ; -wire \ula_|video_|Equal1~0_combout ; wire \ula_|video_|Add0~9 ; wire \ula_|video_|Add0~10_combout ; wire \ula_|video_|vga_hc~0_combout ; @@ -965,10 +246,24 @@ wire \ula_|video_|Add0~11 ; wire \ula_|video_|Add0~12_combout ; wire \ula_|video_|Add0~13 ; wire \ula_|video_|Add0~14_combout ; +wire \ula_|video_|Add0~15 ; +wire \ula_|video_|Add0~16_combout ; +wire \ula_|video_|vga_hc~2_combout ; +wire \ula_|video_|Add0~17 ; +wire \ula_|video_|Add0~18_combout ; +wire \ula_|video_|vga_hc~1_combout ; +wire \ula_|video_|Equal0~0_combout ; +wire \ula_|video_|Equal0~1_combout ; +wire \ula_|video_|Equal1~0_combout ; wire \ula_|video_|Add1~0_combout ; +wire \ula_|video_|vga_vc[0]~0_combout ; +wire \ula_|video_|Add1~1 ; +wire \ula_|video_|Add1~2_combout ; +wire \ula_|video_|vga_vc[1]~1_combout ; wire \ula_|video_|Add1~3 ; wire \ula_|video_|Add1~4_combout ; wire \ula_|video_|vga_vc[2]~2_combout ; +wire \ula_|video_|vga_vc[2]~feeder_combout ; wire \ula_|video_|Add1~5 ; wire \ula_|video_|Add1~6_combout ; wire \ula_|video_|vga_vc[3]~3_combout ; @@ -976,8 +271,6 @@ wire \ula_|video_|Add1~7 ; wire \ula_|video_|Add1~8_combout ; wire \ula_|video_|vga_vc[4]~5_combout ; wire \ula_|video_|Add1~9 ; -wire \ula_|video_|Add1~10_combout ; -wire \ula_|video_|vga_vc[5]~8_combout ; wire \ula_|video_|Add1~11 ; wire \ula_|video_|Add1~12_combout ; wire \ula_|video_|vga_vc[6]~4_combout ; @@ -990,359 +283,1298 @@ wire \ula_|video_|vga_vc[8]~7_combout ; wire \ula_|video_|Add1~17 ; wire \ula_|video_|Add1~18_combout ; wire \ula_|video_|vga_vc[9]~9_combout ; -wire \ula_|video_|Equal2~0_combout ; wire \ula_|video_|Equal3~0_combout ; +wire \ula_|video_|Equal2~0_combout ; wire \ula_|video_|Equal3~1_combout ; -wire \ula_|video_|vga_vc[0]~0_combout ; -wire \ula_|video_|Add1~1 ; -wire \ula_|video_|Add1~2_combout ; -wire \ula_|video_|vga_vc[1]~1_combout ; -wire \SW[1]~input_o ; -wire \z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout ; -wire \z80_|pla_decode_|Equal79~0_combout ; -wire \z80_|interrupts_|DFFE_instIFF2~0_combout ; -wire \z80_|interrupts_|SYNTHESIZED_WIRE_12~combout ; -wire \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl_outclk ; -wire \z80_|interrupts_|DFFE_instIFF2~q ; -wire \z80_|interrupts_|iff1~0_combout ; -wire \z80_|interrupts_|iff1~1_combout ; -wire \z80_|interrupts_|SYNTHESIZED_WIRE_15~combout ; -wire \z80_|interrupts_|iff1~q ; +wire \ula_|video_|Add1~10_combout ; +wire \ula_|video_|vga_vc[5]~8_combout ; wire \ula_|video_|Equal2~1_combout ; wire \ula_|video_|Equal2~2_combout ; +wire \SW[1]~input_o ; +wire \z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout ; wire \z80_|interrupts_|SYNTHESIZED_WIRE_13~combout ; wire \z80_|interrupts_|int_armed~q ; +wire \z80_|interrupts_|DFFE_inst44~feeder_combout ; wire \z80_|interrupts_|DFFE_inst44~q ; -wire \z80_|execute_|pc_inc_hold~38_combout ; -wire \z80_|execute_|ctl_inc_cy~91_combout ; -wire \z80_|execute_|pc_inc_hold~45_combout ; -wire \z80_|execute_|pc_inc_hold~44_combout ; -wire \z80_|execute_|pc_inc_hold~46_combout ; -wire \z80_|execute_|pc_inc_hold~37_combout ; -wire \z80_|execute_|pc_inc_hold~50_combout ; -wire \z80_|execute_|pc_inc_hold~33_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ; -wire \z80_|execute_|pc_inc_hold~31_combout ; -wire \z80_|execute_|pc_inc_hold~32_combout ; -wire \z80_|execute_|pc_inc_hold~34_combout ; -wire \z80_|execute_|pc_inc_hold~51_combout ; -wire \z80_|execute_|pc_inc_hold~30_combout ; -wire \z80_|execute_|pc_inc_hold~52_combout ; -wire \z80_|execute_|pc_inc_hold~35_combout ; -wire \z80_|execute_|pc_inc_hold~36_combout ; -wire \z80_|execute_|ctl_inc_cy~44_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ; -wire \z80_|execute_|ctl_inc_cy~45_combout ; -wire \z80_|execute_|pc_inc_hold~43_combout ; -wire \z80_|execute_|ctl_inc_cy~71_combout ; -wire \z80_|execute_|ctl_inc_cy~73_combout ; -wire \z80_|execute_|ctl_inc_cy~46_combout ; -wire \z80_|execute_|pc_inc_hold~53_combout ; -wire \z80_|execute_|pc_inc_hold~39_combout ; -wire \z80_|execute_|pc_inc_hold~47_combout ; -wire \z80_|execute_|ctl_inc_cy~74_combout ; +wire \z80_|decode_state_|in_halt~0_combout ; +wire \z80_|decode_state_|in_halt~1_combout ; +wire \z80_|decode_state_|in_halt~q ; +wire \z80_|pla_decode_|Equal50~0_combout ; +wire \z80_|execute_|ixy_d~17_combout ; +wire \z80_|pla_decode_|Equal44~0_combout ; +wire \z80_|execute_|ixy_d~16_combout ; +wire \z80_|pla_decode_|Equal3~1_combout ; +wire \z80_|execute_|ixy_d~10_combout ; +wire \z80_|execute_|ixy_d~13_combout ; +wire \z80_|execute_|ixy_d~14_combout ; +wire \z80_|pla_decode_|Equal49~0_combout ; +wire \z80_|execute_|ixy_d~15_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ; +wire \z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout ; +wire \z80_|decode_state_|DFFE_inst4~q ; +wire \z80_|execute_|ctl_ir_we~5_combout ; +wire \z80_|execute_|ctl_ir_we~13_combout ; +wire \z80_|pla_decode_|Equal8~0_combout ; +wire \z80_|execute_|ctl_mRead~6_combout ; +wire \z80_|pla_decode_|Equal9~0_combout ; +wire \z80_|pla_decode_|Equal9~1_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ; +wire \z80_|pla_decode_|Equal13~1_combout ; +wire \z80_|pla_decode_|Equal69~0_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ; +wire \z80_|execute_|ctl_alu_op_low~27_combout ; +wire \z80_|execute_|ctl_reg_out_lo~2_combout ; +wire \z80_|execute_|rsel3~combout ; +wire \z80_|execute_|ctl_ir_we~12_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ; +wire \z80_|pla_decode_|Equal56~0_combout ; +wire \z80_|execute_|ctl_alu_op_low~24_combout ; +wire \z80_|execute_|ctl_alu_op_low~25_combout ; +wire \z80_|execute_|nextM~2_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~16_combout ; +wire \z80_|execute_|ctl_reg_out_lo~3_combout ; +wire \z80_|pla_decode_|Equal40~0_combout ; +wire \z80_|pla_decode_|Equal40~1_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ; +wire \z80_|pla_decode_|Equal3~0_combout ; +wire \z80_|pla_decode_|Equal39~0_combout ; +wire \z80_|execute_|ctl_reg_out_lo~4_combout ; +wire \z80_|execute_|ctl_alu_oe~0_combout ; +wire \z80_|execute_|comb~0_combout ; +wire \z80_|pla_decode_|Equal41~0_combout ; +wire \z80_|pla_decode_|Equal47~0_combout ; +wire \z80_|execute_|ctl_inc_cy~32_combout ; +wire \z80_|pla_decode_|Equal19~0_combout ; +wire \z80_|execute_|ctl_reg_out_lo~9_combout ; +wire \z80_|execute_|ctl_reg_out_lo~5_combout ; +wire \z80_|execute_|ctl_mWrite~4_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ; +wire \z80_|execute_|ctl_mRead~34_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ; +wire \z80_|execute_|ctl_mWrite~5_combout ; +wire \z80_|execute_|nextM~11_combout ; +wire \z80_|pla_decode_|Equal20~0_combout ; +wire \z80_|pla_decode_|Equal13~2_combout ; +wire \z80_|execute_|ctl_mRead~24_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~27_combout ; +wire \z80_|pla_decode_|Equal48~0_combout ; +wire \z80_|pla_decode_|Equal10~0_combout ; +wire \z80_|pla_decode_|Equal11~0_combout ; +wire \z80_|pla_decode_|Equal63~0_combout ; +wire \z80_|execute_|ctl_flags_hf2_we~combout ; +wire \z80_|execute_|ctl_alu_shift_oe~41_combout ; +wire \z80_|pla_decode_|Equal68~3_combout ; +wire \z80_|execute_|ctl_flags_bus~7_combout ; +wire \z80_|execute_|ctl_flags_bus~8_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~9_combout ; +wire \z80_|execute_|ctl_ir_we~6_combout ; +wire \z80_|execute_|ctl_ir_we~8_combout ; +wire \z80_|execute_|ctl_ir_we~14_combout ; +wire \z80_|execute_|ctl_flags_bus~4_combout ; +wire \z80_|execute_|ctl_flags_bus~5_combout ; +wire \z80_|execute_|ctl_mRead~4_combout ; +wire \z80_|execute_|ctl_flags_bus~6_combout ; +wire \z80_|execute_|ctl_flags_bus~9_combout ; +wire \z80_|execute_|ctl_iorw~11_combout ; +wire \z80_|execute_|ctl_mWrite~17_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~18_combout ; +wire \z80_|pla_decode_|Equal37~0_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~19_combout ; +wire \z80_|pla_decode_|Equal35~0_combout ; +wire \z80_|pla_decode_|Equal21~1_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~17_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~20_combout ; +wire \z80_|execute_|ctl_ir_we~9_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~11_combout ; +wire \z80_|execute_|ctl_ir_we~15_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~7_combout ; +wire \z80_|execute_|ctl_ir_we~7_combout ; +wire \z80_|pla_decode_|Equal46~0_combout ; +wire \z80_|execute_|ctl_ir_we~11_combout ; +wire \z80_|execute_|ctl_bus_db_oe~3_combout ; +wire \z80_|pla_decode_|Equal52~1_combout ; +wire \z80_|execute_|ctl_flags_xy_we~21_combout ; +wire \z80_|execute_|ctl_flags_xy_we~13_combout ; +wire \z80_|execute_|ctl_state_alu~6_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~14_combout ; +wire \z80_|execute_|ctl_flags_xy_we~14_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~24_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ; +wire \z80_|execute_|ctl_reg_gp_sel~7_combout ; +wire \z80_|execute_|rsel0~combout ; +wire \z80_|execute_|ctl_state_alu~3_combout ; +wire \z80_|execute_|ctl_reg_use_sp~0_combout ; +wire \z80_|execute_|ctl_state_alu~2_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ; +wire \z80_|execute_|ctl_reg_out_lo~6_combout ; +wire \z80_|execute_|ctl_state_alu~5_combout ; +wire \z80_|execute_|ctl_sw_2u~1_combout ; +wire \z80_|execute_|ctl_alu_oe~1_combout ; +wire \z80_|execute_|ctl_mWrite~7_combout ; +wire \z80_|execute_|ctl_sw_2u~4_combout ; +wire \z80_|execute_|setM1~57_combout ; +wire \z80_|execute_|ctl_sw_2u~5_combout ; +wire \z80_|execute_|ctl_reg_out_lo~7_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~0_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~41_combout ; +wire \z80_|execute_|ctl_inc_cy~86_combout ; +wire \z80_|execute_|ctl_inc_cy~88_combout ; +wire \z80_|execute_|ctl_inc_cy~36_combout ; +wire \z80_|execute_|ctl_inc_cy~87_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~26_combout ; +wire \z80_|execute_|ctl_mWrite~9_combout ; +wire \z80_|execute_|ctl_reg_sys_we~1_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~42_combout ; +wire \z80_|pla_decode_|Equal40~2_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~14_combout ; +wire \z80_|pla_decode_|Equal55~0_combout ; +wire \z80_|execute_|ctl_mRead~11_combout ; +wire \z80_|pla_decode_|Equal6~1_combout ; +wire \z80_|execute_|setM1~36_combout ; +wire \z80_|execute_|comb~1_combout ; +wire \z80_|execute_|ctl_mRead~13_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~11_combout ; +wire \z80_|pla_decode_|Equal24~0_combout ; +wire \z80_|execute_|pc_inc_hold~26_combout ; +wire \z80_|execute_|setM1~37_combout ; +wire \z80_|execute_|pc_inc_hold~6_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo~38_combout ; +wire \z80_|execute_|fMRead~7_combout ; +wire \z80_|execute_|ctl_mRead~12_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~31_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ; +wire \z80_|nM1_int~2_combout ; +wire \z80_|execute_|ctl_sw_4u~0_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ; +wire \z80_|execute_|fMRead~6_combout ; +wire \z80_|execute_|ctl_inc_dec~12_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ; +wire \z80_|pla_decode_|Equal25~0_combout ; +wire \z80_|pla_decode_|Equal12~1_combout ; +wire \z80_|execute_|ctl_inc_cy~38_combout ; +wire \z80_|execute_|ctl_inc_cy~82_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~16_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~32_combout ; +wire \z80_|execute_|ctl_inc_cy~77_combout ; +wire \z80_|pla_decode_|Equal29~0_combout ; wire \z80_|execute_|ctl_inc_cy~78_combout ; wire \z80_|execute_|ctl_inc_cy~79_combout ; -wire \z80_|execute_|ctl_inc_cy~80_combout ; -wire \z80_|execute_|ctl_inc_cy~81_combout ; -wire \z80_|execute_|ctl_inc_cy~82_combout ; -wire \z80_|execute_|ctl_inc_cy~83_combout ; -wire \z80_|execute_|ctl_inc_cy~84_combout ; -wire \z80_|execute_|pc_inc_hold~42_combout ; -wire \z80_|execute_|ctl_inc_cy~90_combout ; -wire \z80_|execute_|pc_inc_hold~41_combout ; -wire \z80_|execute_|ctl_inc_cy~66_combout ; -wire \z80_|execute_|ctl_inc_cy~67_combout ; -wire \z80_|execute_|ctl_inc_cy~68_combout ; -wire \z80_|execute_|ctl_inc_cy~64_combout ; -wire \z80_|execute_|ctl_inc_cy~63_combout ; -wire \z80_|execute_|ctl_inc_cy~65_combout ; -wire \z80_|execute_|ctl_inc_cy~69_combout ; +wire \z80_|execute_|ctl_mRead~14_combout ; wire \z80_|execute_|ctl_inc_cy~49_combout ; -wire \z80_|execute_|ctl_inc_cy~50_combout ; -wire \z80_|execute_|ctl_inc_cy~51_combout ; -wire \z80_|execute_|ctl_inc_cy~52_combout ; -wire \z80_|execute_|ctl_inc_cy~36_combout ; -wire \z80_|execute_|ctl_inc_cy~37_combout ; -wire \z80_|execute_|ctl_inc_cy~54_combout ; -wire \z80_|execute_|ctl_inc_cy~41_combout ; -wire \z80_|execute_|ctl_inc_cy~58_combout ; -wire \z80_|execute_|ctl_inc_cy~55_combout ; -wire \z80_|execute_|ctl_inc_cy~56_combout ; -wire \z80_|execute_|ctl_inc_cy~89_combout ; -wire \z80_|execute_|ctl_inc_cy~57_combout ; -wire \z80_|execute_|ctl_inc_cy~59_combout ; -wire \z80_|execute_|ctl_inc_cy~60_combout ; -wire \z80_|execute_|ctl_inc_cy~47_combout ; -wire \z80_|execute_|ctl_inc_cy~88_combout ; -wire \z80_|execute_|ctl_inc_cy~48_combout ; -wire \z80_|execute_|pc_inc_hold~40_combout ; -wire \z80_|execute_|ctl_inc_cy~61_combout ; -wire \z80_|execute_|ctl_inc_cy~62_combout ; -wire \z80_|execute_|ctl_inc_cy~70_combout ; -wire \z80_|execute_|ctl_inc_cy~85_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ; -wire \z80_|reg_file_|db_lo_as[0]~3_combout ; -wire \z80_|address_latch_|Q[0]~feeder_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ; -wire \z80_|reg_file_|db_lo_as[1]~4_combout ; -wire \z80_|reg_file_|db_lo_as[1]~5_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ; -wire \z80_|reg_file_|db_lo_as[1]~6_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ; -wire \z80_|reg_file_|db_lo_as[2]~9_combout ; -wire \z80_|address_latch_|Q[2]~feeder_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ; -wire \z80_|execute_|ctl_inc_cy~86_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ; -wire \z80_|execute_|ctl_inc_dec~11_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~45_combout ; -wire \z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~48_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~49_combout ; -wire \z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~5_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~40_combout ; +wire \z80_|execute_|ctl_mRead~5_combout ; wire \z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~40_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~41_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[3]~18_combout ; -wire \z80_|execute_|ctl_reg_in_hi~11_combout ; -wire \z80_|execute_|ctl_reg_in_hi~12_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~44_combout ; -wire \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~43_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ; -wire \z80_|reg_control_|reg_sys_we_hi~0_combout ; -wire \z80_|reg_control_|reg_sys_we_hi~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~45_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~42_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~46_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~47_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~17_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~18_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~19_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~16_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~20_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~8_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[1]~15_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~13_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~12_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~10_combout ; -wire \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~11_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~14_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~9_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~15_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~21_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ; -wire \z80_|reg_control_|reg_sw_4d_hi~0_combout ; -wire \z80_|reg_file_|db_hi_as[1]~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ; -wire \z80_|reg_file_|db_hi_as[1]~1_combout ; -wire \z80_|reg_file_|db_hi_as[0]~2_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~23_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~22_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~24_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~26_combout ; -wire \z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~25_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~27_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~28_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[0]~16_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~29_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~30_combout ; -wire \z80_|reg_file_|db_hi_as[0]~4_combout ; -wire \z80_|reg_file_|db_hi_as[0]~5_combout ; -wire \z80_|reg_file_|db_hi_as[0]~6_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ; -wire \z80_|reg_file_|db_hi_as[1]~3_combout ; -wire \z80_|address_latch_|Q[9]~feeder_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~32_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~35_combout ; -wire \z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~34_combout ; -wire \z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~33_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~36_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~37_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~31_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[2]~17_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~38_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~39_combout ; -wire \z80_|reg_file_|db_hi_as[2]~7_combout ; -wire \z80_|reg_file_|db_hi_as[2]~8_combout ; -wire \z80_|reg_file_|db_hi_as[2]~9_combout ; -wire \z80_|address_latch_|Q[10]~feeder_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ; -wire \z80_|reg_file_|db_hi_as[3]~10_combout ; -wire \z80_|reg_file_|db_hi_as[3]~11_combout ; -wire \z80_|reg_file_|db_hi_as[3]~12_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~48_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_low~combout ; -wire \z80_|alu_|alu_op1[3]~3_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~6_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~10_combout ; -wire \z80_|execute_|ctl_alu_core_R~0_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~5_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~7_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~8_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|ena~combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~6_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~20_combout ; -wire \z80_|execute_|ctl_state_alu~12_combout ; -wire \z80_|execute_|ctl_alu_core_hf~18_combout ; -wire \z80_|pla_decode_|Equal61~2_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~16_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~17_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~21_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~15_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~12_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~22_combout ; -wire \z80_|execute_|ctl_alu_core_hf~20_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~36_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~35_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~46_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~33_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~47_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ; +wire \z80_|execute_|ctl_bus_inc_oe~45_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~34_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ; +wire \z80_|execute_|ctl_mWrite~6_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~50_combout ; +wire \z80_|pla_decode_|Equal4~0_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~48_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~49_combout ; +wire \z80_|execute_|ctl_mRead~7_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~29_combout ; +wire \z80_|execute_|ctl_alu_core_S~11_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~27_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~44_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~28_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~30_combout ; +wire \z80_|execute_|ctl_mRead~3_combout ; +wire \z80_|execute_|fMRead~3_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~37_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~38_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~39_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~43_combout ; +wire \z80_|execute_|ctl_alu_oe~3_combout ; +wire \z80_|execute_|fMWrite~1_combout ; +wire \z80_|execute_|ctl_flags_bus~1_combout ; +wire \z80_|execute_|fMRead~5_combout ; +wire \z80_|execute_|ctl_mRead~17_combout ; +wire \z80_|execute_|ctl_iorw~10_combout ; +wire \z80_|execute_|setM1~47_combout ; +wire \z80_|execute_|ctl_mWrite~8_combout ; +wire \z80_|execute_|ctl_al_we~13_combout ; +wire \z80_|execute_|setM1~48_combout ; +wire \z80_|execute_|ctl_sw_4d~0_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ; +wire \z80_|execute_|ctl_mRead~9_combout ; +wire \z80_|execute_|ctl_flags_sz_we~3_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ; +wire \z80_|execute_|ctl_flags_alu~9_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~2_combout ; +wire \z80_|execute_|ctl_flags_alu~10_combout ; +wire \z80_|execute_|ctl_flags_xy_we~10_combout ; +wire \z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ; +wire \z80_|execute_|ctl_flags_xy_we~11_combout ; +wire \z80_|execute_|ctl_flags_alu~11_combout ; +wire \z80_|execute_|ctl_reg_use_sp~1_combout ; +wire \z80_|execute_|ctl_state_alu~4_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~9_combout ; +wire \z80_|execute_|ctl_sw_2d~4_combout ; +wire \z80_|execute_|ctl_flags_sz_we~0_combout ; wire \z80_|execute_|ctl_flags_sz_we~4_combout ; -wire \z80_|pla_decode_|Equal71~2_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ; +wire \z80_|execute_|ctl_alu_op_low~47_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~3_combout ; +wire \z80_|execute_|ctl_flags_alu~12_combout ; +wire \z80_|execute_|ctl_alu_op_low~23_combout ; +wire \z80_|execute_|ctl_flags_xy_we~19_combout ; +wire \z80_|execute_|ctl_flags_alu~13_combout ; +wire \z80_|execute_|ctl_reg_out_hi~4_combout ; +wire \z80_|execute_|ctl_sw_4u~1_combout ; +wire \z80_|execute_|ctl_alu_op_low~29_combout ; +wire \z80_|execute_|ctl_flags_alu~14_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ; +wire \z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ; +wire \z80_|execute_|ctl_flags_use_cf2~13_combout ; +wire \z80_|execute_|ctl_flags_cf_we~7_combout ; +wire \z80_|execute_|ctl_pf_sel[0]~2_combout ; +wire \z80_|execute_|ctl_flags_hf_we~5_combout ; +wire \z80_|execute_|ctl_flags_pf_we~10_combout ; +wire \z80_|pla_decode_|Equal68~2_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~13_combout ; +wire \z80_|execute_|ctl_flags_pf_we~2_combout ; +wire \z80_|execute_|ctl_alu_oe~4_combout ; +wire \z80_|execute_|ctl_flags_xy_we~8_combout ; +wire \z80_|execute_|ctl_flags_xy_we~20_combout ; +wire \z80_|execute_|ctl_flags_xy_we~9_combout ; +wire \z80_|execute_|ctl_flags_sz_we~1_combout ; +wire \z80_|execute_|ctl_bus_db_oe~1_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~10_combout ; +wire \z80_|execute_|ctl_flags_sz_we~2_combout ; +wire \z80_|execute_|ctl_flags_alu~17_combout ; +wire \z80_|execute_|ctl_flags_alu~18_combout ; +wire \z80_|execute_|ctl_flags_alu~6_combout ; +wire \z80_|execute_|ctl_flags_alu~19_combout ; +wire \z80_|pla_decode_|Equal1~5_combout ; +wire \z80_|execute_|ctl_alu_core_R~0_combout ; +wire \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ; +wire \z80_|execute_|ctl_alu_core_R~1_combout ; +wire \z80_|execute_|ctl_flags_alu~7_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~5_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~8_combout ; +wire \z80_|execute_|ctl_flags_alu~8_combout ; +wire \z80_|execute_|ctl_flags_alu~15_combout ; +wire \z80_|execute_|ctl_state_alu~7_combout ; +wire \z80_|execute_|ctl_state_alu~12_combout ; +wire \z80_|execute_|ctl_state_alu~9_combout ; +wire \z80_|execute_|ctl_state_alu~10_combout ; +wire \z80_|execute_|ctl_state_alu~8_combout ; +wire \z80_|pla_decode_|Equal64~0_combout ; +wire \z80_|execute_|ctl_pf_sel[0]~3_combout ; +wire \z80_|pla_decode_|Equal62~2_combout ; +wire \z80_|execute_|ctl_flags_pf_we~4_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~46_combout ; +wire \z80_|execute_|ctl_flags_pf_we~6_combout ; +wire \z80_|execute_|ctl_flags_pf_we~7_combout ; +wire \z80_|execute_|ctl_state_alu~11_combout ; +wire \z80_|pla_decode_|Equal62~3_combout ; +wire \z80_|execute_|ctl_flags_pf_we~5_combout ; +wire \z80_|execute_|ctl_flags_pf_we~3_combout ; +wire \z80_|execute_|ctl_flags_pf_we~8_combout ; +wire \z80_|execute_|ctl_flags_pf_we~9_combout ; +wire \z80_|execute_|ctl_alu_core_S~6_combout ; +wire \z80_|execute_|ctl_alu_core_S~7_combout ; +wire \z80_|execute_|ctl_alu_res_oe~1_combout ; +wire \z80_|execute_|ctl_alu_res_oe~0_combout ; +wire \z80_|execute_|ctl_alu_core_S~4_combout ; +wire \z80_|execute_|ctl_alu_core_S~5_combout ; +wire \z80_|execute_|ctl_alu_res_oe~2_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ; +wire \z80_|reg_control_|reg_sys_we_lo~6_combout ; +wire \z80_|execute_|ctl_flags_xy_we~12_combout ; +wire \z80_|execute_|ctl_flags_cf_we~2_combout ; +wire \z80_|execute_|ctl_alu_res_oe~3_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_high~combout ; +wire \z80_|execute_|ctl_alu_op1_sel_zero~4_combout ; +wire \z80_|execute_|ctl_alu_core_hf~12_combout ; +wire \z80_|pla_decode_|Equal61~2_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~4_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~13_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~14_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~18_combout ; +wire \z80_|execute_|ctl_flags_bus~10_combout ; +wire \z80_|execute_|ctl_flags_bus~2_combout ; +wire \z80_|execute_|ctl_flags_bus~0_combout ; +wire \z80_|execute_|ctl_flags_bus~3_combout ; +wire \z80_|execute_|fMRead~26_combout ; +wire \z80_|execute_|ctl_flags_bus~combout ; +wire \z80_|execute_|ctl_reg_in_lo~9_combout ; +wire \z80_|execute_|ctl_alu_op1_oe~0_combout ; +wire \z80_|execute_|ctl_alu_op1_oe~1_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~6_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~12_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~8_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~9_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~combout ; +wire \z80_|execute_|ctl_alu_op2_oe~0_combout ; +wire \z80_|alu_|db_high[3]~0_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla83M1T3_2~combout ; +wire \z80_|execute_|ctl_alu_shift_oe~15_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~38_combout ; +wire \z80_|execute_|ctl_alu_op_low~28_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~6_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~37_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~39_combout ; +wire \z80_|execute_|ctl_flags_cf2_sel_daa~combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~7_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~8_combout ; +wire \z80_|execute_|ctl_alu_op_low~30_combout ; wire \z80_|execute_|ctl_alu_op_low~31_combout ; +wire \z80_|execute_|ctl_mRead~25_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~40_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~42_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~4_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~47_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~34_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~35_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~36_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~28_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~44_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~29_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~16_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~27_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~10_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~31_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~30_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~32_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~33_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~21_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~45_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~22_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~23_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~24_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~25_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~26_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~43_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_low~combout ; +wire \z80_|execute_|ctl_alu_op1_sel_zero~5_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_zero~combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~13_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~17_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~14_combout ; +wire \z80_|execute_|ctl_alu_core_R~3_combout ; +wire \z80_|execute_|ctl_alu_core_R~4_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~9_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~10_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~11_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~12_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~15_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~6_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|ena~combout ; +wire \z80_|alu_|db_low[3]~15_combout ; +wire \z80_|alu_|db_low[3]~16_combout ; +wire \z80_|execute_|ctl_alu_op_low~33_combout ; +wire \z80_|execute_|ctl_alu_op_low~34_combout ; +wire \z80_|execute_|ctl_alu_op_low~48_combout ; +wire \z80_|execute_|ctl_alu_op_low~35_combout ; +wire \z80_|execute_|ctl_alu_op_low~36_combout ; +wire \z80_|execute_|ctl_alu_op_low~37_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ; +wire \z80_|execute_|ctl_alu_op_low~38_combout ; +wire \z80_|execute_|ctl_alu_op_low~39_combout ; +wire \z80_|execute_|ctl_alu_op_low~40_combout ; +wire \z80_|execute_|ctl_alu_op_low~41_combout ; +wire \z80_|execute_|ctl_alu_op_low~combout ; +wire \z80_|execute_|ctl_alu_oe~5_combout ; +wire \z80_|execute_|ctl_alu_oe~6_combout ; +wire \z80_|execute_|ctl_alu_oe~9_combout ; +wire \z80_|execute_|ctl_alu_core_S~12_combout ; +wire \z80_|execute_|ctl_alu_oe~10_combout ; +wire \z80_|execute_|ctl_alu_oe~2_combout ; +wire \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~15_combout ; +wire \z80_|execute_|ctl_reg_in_hi~8_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~7_combout ; +wire \z80_|execute_|ctl_alu_oe~7_combout ; +wire \z80_|execute_|ctl_mWrite~11_combout ; +wire \z80_|execute_|ctl_bus_db_we~5_combout ; +wire \z80_|execute_|ctl_alu_oe~8_combout ; +wire \z80_|execute_|ctl_flags_alu~16_combout ; +wire \z80_|execute_|ctl_alu_oe~11_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ; +wire \z80_|execute_|ctl_reg_out_hi~8_combout ; +wire \z80_|execute_|ctl_reg_out_hi~5_combout ; +wire \z80_|execute_|ctl_sw_2u~2_combout ; +wire \z80_|execute_|ctl_sw_2u~0_combout ; +wire \z80_|execute_|ctl_sw_2u~3_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ; +wire \z80_|execute_|ctl_inc_cy~33_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~37_combout ; +wire \z80_|execute_|ctl_sw_2u~6_combout ; +wire \z80_|execute_|ctl_reg_out_hi~6_combout ; +wire \z80_|execute_|ctl_reg_out_hi~7_combout ; +wire \z80_|execute_|ctl_mRead~2_combout ; +wire \z80_|execute_|ctl_sw_2d~6_combout ; +wire \z80_|execute_|ctl_sw_2d~7_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ; +wire \z80_|execute_|ctl_sw_2d~8_combout ; +wire \z80_|execute_|ctl_bus_db_oe~7_combout ; +wire \z80_|execute_|ctl_sw_2d~5_combout ; +wire \z80_|execute_|ctl_mRead~19_combout ; +wire \z80_|execute_|ctl_mRead~18_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~2_combout ; +wire \z80_|pla_decode_|Equal24~1_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~3_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~4_combout ; +wire \z80_|execute_|ctl_mRead~20_combout ; +wire \z80_|execute_|ctl_reg_in_hi~5_combout ; +wire \z80_|execute_|ctl_mRead~22_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ; +wire \z80_|execute_|ctl_reg_in_hi~6_combout ; +wire \z80_|execute_|ctl_reg_in_hi~2_combout ; +wire \z80_|execute_|setM1~30_combout ; +wire \z80_|execute_|ctl_mRead~23_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~6_combout ; +wire \z80_|execute_|ctl_reg_in_hi~3_combout ; +wire \z80_|execute_|ctl_mWrite~10_combout ; +wire \z80_|execute_|fMRead~18_combout ; +wire \z80_|reg_control_|reg_sel_pc~0_combout ; +wire \z80_|reg_control_|reg_sel_pc~1_combout ; +wire \z80_|reg_control_|reg_sel_pc~2_combout ; +wire \z80_|execute_|fMRead~19_combout ; +wire \z80_|execute_|fMRead~20_combout ; +wire \z80_|execute_|fMRead~21_combout ; +wire \z80_|execute_|ctl_sw_2d~9_combout ; +wire \z80_|execute_|ctl_sw_2d~14_combout ; +wire \z80_|execute_|ctl_sw_1d~8_combout ; +wire \z80_|execute_|ctl_sw_2d~10_combout ; +wire \z80_|execute_|ctl_sw_2d~11_combout ; +wire \z80_|execute_|ctl_sw_2d~12_combout ; +wire \z80_|execute_|ctl_sw_2d~13_combout ; +wire \z80_|alu_|db[7]~9_combout ; +wire \z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ; +wire \z80_|execute_|ctl_alu_op_low~32_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~2_combout ; +wire \z80_|execute_|ctl_flags_xy_we~22_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~3_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ; wire \z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ; +wire \z80_|execute_|ctl_alu_core_hf~15_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ; -wire \z80_|pla_decode_|Equal72~2_combout ; -wire \z80_|pla_decode_|Equal73~2_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~7_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~17_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ; +wire \z80_|execute_|ctl_flags_nf_we~3_combout ; wire \z80_|execute_|ctl_flags_nf_we~0_combout ; +wire \z80_|pla_decode_|Equal73~2_combout ; +wire \z80_|pla_decode_|Equal72~2_combout ; wire \z80_|execute_|ctl_flags_nf_we~1_combout ; wire \z80_|execute_|ctl_flags_nf_we~2_combout ; -wire \z80_|execute_|ctl_flags_nf_we~3_combout ; wire \z80_|execute_|ctl_flags_sz_we~5_combout ; wire \z80_|execute_|ctl_flags_sz_we~6_combout ; wire \z80_|execute_|ctl_flags_nf_we~4_combout ; -wire \z80_|execute_|setM1~15_combout ; -wire \z80_|execute_|setM1~16_combout ; -wire \z80_|execute_|ctl_flags_xy_we~6_combout ; -wire \z80_|execute_|ctl_flags_xy_we~7_combout ; -wire \z80_|execute_|ctl_flags_sz_we~2_combout ; -wire \z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ; -wire \z80_|execute_|ctl_alu_core_R~1_combout ; -wire \z80_|execute_|ctl_flags_alu~7_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~8_combout ; -wire \z80_|execute_|ctl_flags_alu~8_combout ; -wire \z80_|execute_|ctl_flags_xy_we~16_combout ; -wire \z80_|execute_|ctl_flags_alu~12_combout ; -wire \z80_|execute_|ctl_flags_alu~13_combout ; -wire \z80_|execute_|ctl_flags_alu~14_combout ; -wire \z80_|execute_|ctl_flags_alu~15_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~19_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~7_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~9_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~10_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_nf~q ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~7_combout ; -wire \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ; +wire \z80_|execute_|ctl_flags_hf_cpl~14_combout ; +wire \z80_|execute_|ctl_flags_hf_cpl~10_combout ; +wire \z80_|pla_decode_|Equal45~0_combout ; +wire \z80_|execute_|ctl_flags_hf_cpl~11_combout ; +wire \z80_|execute_|ctl_flags_hf_cpl~12_combout ; +wire \z80_|execute_|ctl_flags_hf_cpl~13_combout ; +wire \z80_|execute_|ctl_alu_core_S~8_combout ; +wire \z80_|execute_|ctl_alu_core_S~9_combout ; +wire \z80_|execute_|ctl_alu_core_S~10_combout ; +wire \z80_|execute_|ctl_alu_core_S~combout ; +wire \z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ; +wire \z80_|alu_|alu_op1[3]~2_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ; +wire \z80_|execute_|ctl_reg_sys_we_lo~2_combout ; +wire \z80_|execute_|ctl_reg_sys_we_lo~3_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~14_combout ; +wire \z80_|reg_control_|reg_sys_we_hi~0_combout ; +wire \z80_|pla_decode_|Equal33~3_combout ; +wire \z80_|execute_|ctl_reg_sys_we~0_combout ; +wire \z80_|execute_|ctl_reg_sys_we~2_combout ; +wire \z80_|execute_|ctl_reg_sys_we~3_combout ; +wire \z80_|execute_|ctl_reg_in_hi~4_combout ; +wire \z80_|reg_control_|reg_sys_we_hi~combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo~17_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~11_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~12_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~13_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ; +wire \z80_|execute_|ctl_reg_sel_wz~6_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~7_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~9_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~8_combout ; +wire \z80_|execute_|ctl_al_we~5_combout ; +wire \z80_|execute_|ctl_al_we~4_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~41_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~10_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo~21_combout ; +wire \z80_|execute_|ctl_inc_dec~3_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ; +wire \z80_|execute_|fMRead~2_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~20_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~29_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~13_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ; +wire \z80_|execute_|ctl_reg_sel_ir~0_combout ; +wire \z80_|execute_|ctl_reg_sel_ir~1_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ; +wire \z80_|execute_|ctl_reg_sys_we_lo~4_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~combout ; +wire \z80_|reg_control_|reg_sw_4d_hi~0_combout ; +wire \z80_|reg_file_|db_hi_as[3]~10_combout ; +wire \z80_|reg_file_|db_hi_as[3]~11_combout ; +wire \z80_|execute_|ctl_apin_mux~1_combout ; +wire \z80_|execute_|ctl_inc_cy~37_combout ; +wire \z80_|execute_|ctl_inc_dec~2_combout ; +wire \z80_|execute_|ctl_inc_cy~40_combout ; +wire \z80_|execute_|ctl_inc_dec~4_combout ; +wire \z80_|execute_|ctl_inc_dec~5_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~4_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ; +wire \z80_|execute_|setM1~42_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~12_combout ; +wire \z80_|execute_|ctl_sw_1d~4_combout ; +wire \z80_|execute_|ctl_sw_4d~3_combout ; +wire \z80_|execute_|fMRead~9_combout ; +wire \z80_|execute_|fMRead~10_combout ; +wire \z80_|execute_|fMRead~8_combout ; +wire \z80_|execute_|ctl_sw_4d~2_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~11_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~12_combout ; +wire \z80_|execute_|ctl_sw_4d~4_combout ; +wire \z80_|execute_|ctl_sw_4d~5_combout ; +wire \z80_|execute_|ctl_al_we~14_combout ; +wire \z80_|execute_|ctl_al_we~10_combout ; +wire \z80_|execute_|ctl_al_we~6_combout ; +wire \z80_|execute_|ctl_al_we~7_combout ; +wire \z80_|execute_|ctl_al_we~8_combout ; +wire \z80_|execute_|ctl_al_we~9_combout ; +wire \z80_|execute_|ctl_al_we~11_combout ; +wire \z80_|execute_|ctl_al_we~12_combout ; +wire \z80_|execute_|fIOWrite~0_combout ; +wire \z80_|execute_|ctl_inc_dec~8_combout ; +wire \z80_|execute_|ctl_reg_gp_we~2_combout ; +wire \z80_|execute_|ctl_inc_dec~9_combout ; +wire \z80_|execute_|ctl_apin_mux~0_combout ; +wire \z80_|execute_|ctl_inc_dec~6_combout ; +wire \z80_|execute_|ctl_inc_dec~7_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~21_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[0]~40_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~39_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[0]~13_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[0]~31_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ; +wire \z80_|execute_|setM1~49_combout ; +wire \z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ; +wire \z80_|execute_|setM1~50_combout ; +wire \z80_|execute_|ctl_flags_oe~0_combout ; +wire \z80_|execute_|ctl_flags_oe~1_combout ; +wire \z80_|execute_|ctl_reg_in_hi~13_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~12_combout ; +wire \z80_|execute_|ctl_reg_in_hi~7_combout ; +wire \z80_|execute_|ctl_state_alu~13_combout ; +wire \z80_|execute_|ctl_reg_gp_we~6_combout ; +wire \z80_|execute_|ctl_reg_gp_we~5_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~17_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ; wire \z80_|execute_|ctl_alu_sel_op2_neg~10_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~8_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~9_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~11_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~14_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~18_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_high~combout ; +wire \z80_|execute_|ctl_sw_1d~9_combout ; +wire \z80_|execute_|ctl_reg_gp_we~9_combout ; +wire \z80_|execute_|ctl_reg_gp_we~4_combout ; +wire \z80_|execute_|ctl_reg_gp_we~7_combout ; +wire \z80_|execute_|ctl_reg_gp_we~3_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~32_combout ; +wire \z80_|execute_|ctl_sw_4u~2_combout ; +wire \z80_|execute_|ctl_sw_4u~3_combout ; +wire \z80_|execute_|ctl_reg_gp_we~8_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~14_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~24_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~46_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~22_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~23_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~26_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~34_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~25_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~21_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ; +wire \z80_|pla_decode_|Equal2~2_combout ; +wire \z80_|pla_decode_|Equal1~6_combout ; +wire \z80_|reg_control_|bank_exx~2_combout ; +wire \z80_|reg_control_|bank_exx~q ; +wire \z80_|reg_control_|bank_hl_de1~0_combout ; +wire \z80_|reg_control_|bank_hl_de1~q ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~28_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~29_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~30_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~13_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ; +wire \z80_|execute_|ctl_reg_use_sp~2_combout ; +wire \z80_|execute_|ctl_reg_use_sp~3_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~14_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~32_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~33_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~16_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~34_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~20_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~21_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~22_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~18_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~37_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~19_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~23_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~16_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~17_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~11_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~36_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~8_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~9_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~10_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~15_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~31_combout ; +wire \z80_|reg_control_|reg_sel_de2~5_combout ; +wire \z80_|reg_control_|reg_sel_de2~6_combout ; +wire \z80_|reg_control_|reg_sel_de~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ; +wire \z80_|reg_control_|bank_hl_de2~0_combout ; +wire \z80_|reg_control_|bank_hl_de2~q ; +wire \z80_|reg_control_|reg_sel_de2~4_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~33_combout ; +wire \z80_|reg_control_|reg_sel_hl~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ; +wire \z80_|reg_control_|reg_sel_hl2~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~34_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~36_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~15_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~18_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~37_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ; +wire \z80_|reg_control_|reg_sel_iy~2_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~38_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ; +wire \z80_|execute_|ctl_reg_in_hi~9_combout ; +wire \z80_|execute_|ctl_reg_in_hi~10_combout ; +wire \z80_|execute_|ctl_reg_in_lo~8_combout ; +wire \z80_|reg_file_|b2v_latch_sp_lo|latch[2]~feeder_combout ; +wire \z80_|execute_|ctl_reg_use_sp~4_combout ; +wire \z80_|execute_|ctl_reg_use_sp~5_combout ; +wire \z80_|execute_|ctl_reg_use_sp~6_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ; +wire \z80_|execute_|ctl_sw_1d~5_combout ; +wire \z80_|execute_|ctl_im_we~combout ; +wire \z80_|execute_|ctl_sw_1d~6_combout ; +wire \z80_|execute_|ctl_sw_1d~7_combout ; +wire \z80_|reg_file_|db_lo_ds[2]~2_combout ; +wire \z80_|alu_control_|db[2]~28_combout ; +wire \z80_|execute_|ctl_reg_in_hi~11_combout ; +wire \z80_|execute_|ctl_reg_in_hi~12_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~18_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ; +wire \z80_|pla_decode_|Equal21~2_combout ; +wire \z80_|reg_control_|bank_af~0_combout ; +wire \z80_|reg_control_|bank_af~q ; +wire \z80_|reg_control_|reg_sel_af~0_combout ; +wire \z80_|reg_control_|reg_sel_af2~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~17_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~19_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~16_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~20_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~34_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~36_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~35_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~33_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~37_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ; +wire \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~31_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[2]~12_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~32_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~38_combout ; +wire \z80_|execute_|ctl_inc_dec~11_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ; +wire \z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ; +wire \z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ; +wire \z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~4_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~5_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~16_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~6_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~7_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~10_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~8_combout ; +wire \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ; +wire \z80_|execute_|ctl_alu_op_low~42_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~9_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ; +wire \z80_|execute_|ctl_mWrite~18_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~2_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ; +wire \z80_|execute_|ctl_flags_cf2_we~4_combout ; +wire \z80_|execute_|ctl_flags_cf2_we~2_combout ; +wire \z80_|execute_|ctl_flags_cf2_we~3_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_32~combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~81_combout ; +wire \z80_|alu_|db_high[2]~8_combout ; +wire \z80_|alu_|db_high[2]~9_combout ; +wire \z80_|alu_|db_high[2]~11_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_lq~combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~5_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~6_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~7_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~8_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_zero~combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|ena~combout ; +wire \z80_|alu_|db_high[2]~10_combout ; +wire \z80_|alu_|db_high[2]~12_combout ; +wire \z80_|alu_|db_high[3]~1_combout ; +wire \z80_|alu_|db_high[2]~13_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~78_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~79_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ; +wire \z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~75_combout ; +wire \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~76_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~77_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~80_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~74_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~73_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~81_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~19_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~18_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~20_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~92_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~21_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ; +wire \z80_|reg_file_|db_lo_as[0]~2_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~55_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~56_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~57_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~59_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~58_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~60_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~53_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~54_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~61_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~62_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ; +wire \z80_|reg_file_|db_lo_as[4]~13_combout ; +wire \z80_|reg_file_|db_lo_as[4]~14_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ; +wire \z80_|reg_file_|db_lo_as[4]~15_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~64_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~63_combout ; +wire \z80_|reg_file_|b2v_latch_af_lo|latch[5]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~65_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~69_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~68_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~66_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~67_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~70_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~71_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~72_combout ; +wire \z80_|reg_file_|db_lo_as[5]~16_combout ; +wire \z80_|reg_file_|db_lo_as[5]~17_combout ; +wire \z80_|reg_file_|db_lo_as[5]~18_combout ; +wire \z80_|execute_|ctl_inc_dec~10_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ; +wire \z80_|reg_file_|db_lo_as[6]~19_combout ; +wire \z80_|reg_file_|db_lo_as[6]~20_combout ; +wire \z80_|reg_file_|db_lo_as[6]~21_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~82_combout ; +wire \z80_|reg_file_|db_lo_ds[6]~0_combout ; +wire \z80_|sw1_|db_down[6]~1_combout ; +wire \z80_|execute_|ctl_66_oe~combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~4_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~2_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~3_combout ; wire \z80_|alu_|alu_op2[1]~1_combout ; wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ; -wire \z80_|execute_|ctl_alu_core_S~9_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8_combout ; -wire \z80_|alu_|alu_op2[0]~3_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~12_combout ; -wire \z80_|execute_|ctl_alu_core_S~8_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ; -wire \z80_|execute_|ctl_alu_core_hf~21_combout ; -wire \z80_|execute_|ctl_alu_core_hf~22_combout ; -wire \z80_|execute_|ctl_alu_core_hf~19_combout ; -wire \z80_|execute_|ctl_alu_op_low~27_combout ; -wire \z80_|execute_|ctl_alu_op_low~29_combout ; -wire \z80_|execute_|ctl_alu_core_hf~23_combout ; -wire \z80_|execute_|ctl_alu_core_hf~37_combout ; -wire \z80_|execute_|ctl_alu_core_hf~38_combout ; -wire \z80_|execute_|ctl_alu_core_hf~24_combout ; -wire \z80_|execute_|ctl_alu_core_hf~25_combout ; -wire \z80_|execute_|ctl_alu_core_hf~26_combout ; -wire \z80_|execute_|ctl_alu_core_hf~27_combout ; -wire \z80_|execute_|ctl_alu_core_hf~28_combout ; -wire \z80_|execute_|ctl_alu_op_low~30_combout ; -wire \z80_|execute_|ctl_alu_core_hf~34_combout ; -wire \z80_|execute_|ctl_alu_core_hf~32_combout ; -wire \z80_|execute_|ctl_alu_core_hf~43_combout ; -wire \z80_|execute_|ctl_alu_core_hf~33_combout ; -wire \z80_|execute_|ctl_alu_core_hf~42_combout ; -wire \z80_|execute_|ctl_alu_core_hf~35_combout ; -wire \z80_|execute_|ctl_alu_core_hf~41_combout ; -wire \z80_|execute_|ctl_alu_core_hf~30_combout ; -wire \z80_|execute_|ctl_mWrite~10_combout ; -wire \z80_|execute_|ctl_alu_core_hf~31_combout ; -wire \z80_|execute_|ctl_alu_core_hf~44_combout ; -wire \z80_|execute_|ctl_alu_core_hf~29_combout ; -wire \z80_|execute_|ctl_alu_core_hf~36_combout ; -wire \z80_|execute_|ctl_alu_core_hf~39_combout ; -wire \z80_|execute_|ctl_alu_core_hf~40_combout ; -wire \z80_|execute_|ctl_flags_hf_we~2_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ; +wire \z80_|execute_|ctl_alu_core_R~5_combout ; wire \z80_|execute_|ctl_alu_core_R~2_combout ; wire \z80_|execute_|ctl_alu_core_R~combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3_combout ; -wire \z80_|alu_|alu_op2[3]~2_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ; +wire \z80_|alu_|db_high[0]~20_combout ; +wire \z80_|alu_|db_high[0]~21_combout ; +wire \z80_|alu_|db_high[0]~22_combout ; +wire \z80_|alu_|db_high[0]~23_combout ; +wire \z80_|alu_|db_high[0]~24_combout ; +wire \z80_|alu_|db_low[0]~4_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~2_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~3_combout ; +wire \z80_|alu_|db_low[0]~5_combout ; +wire \z80_|alu_|db_low[0]~6_combout ; +wire \z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ; +wire \z80_|execute_|ctl_flags_hf_we~2_combout ; +wire \z80_|execute_|ctl_flags_cf_we~3_combout ; +wire \z80_|execute_|ctl_flags_cf_we~4_combout ; +wire \z80_|execute_|ctl_flags_cf_we~5_combout ; +wire \z80_|execute_|ctl_flags_cf_we~6_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf~q ; +wire \z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ; +wire \z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ; +wire \z80_|alu_|db_low[0]~2_combout ; +wire \z80_|alu_|db_low[0]~3_combout ; +wire \z80_|alu_|db_low[0]~24_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~0_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~1_combout ; +wire \z80_|alu_|alu_op2[0]~3_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla26M3T5_8~combout ; +wire \z80_|execute_|ctl_alu_core_hf~14_combout ; +wire \z80_|execute_|ctl_alu_core_hf~16_combout ; +wire \z80_|execute_|ctl_alu_core_hf~13_combout ; +wire \z80_|execute_|ctl_alu_core_hf~17_combout ; +wire \z80_|execute_|ctl_alu_op_low~44_combout ; +wire \z80_|execute_|ctl_alu_core_hf~20_combout ; +wire \z80_|execute_|ctl_alu_core_hf~21_combout ; +wire \z80_|execute_|ctl_alu_core_hf~18_combout ; +wire \z80_|execute_|ctl_alu_core_hf~19_combout ; +wire \z80_|execute_|ctl_alu_core_hf~22_combout ; +wire \z80_|execute_|ctl_alu_op_low~43_combout ; +wire \z80_|execute_|ctl_alu_core_hf~24_combout ; +wire \z80_|execute_|ctl_alu_core_hf~25_combout ; +wire \z80_|execute_|ctl_alu_core_hf~35_combout ; +wire \z80_|execute_|ctl_alu_core_hf~23_combout ; +wire \z80_|execute_|ctl_alu_core_hf~26_combout ; +wire \z80_|execute_|ctl_alu_core_hf~34_combout ; +wire \z80_|execute_|ctl_alu_core_hf~27_combout ; +wire \z80_|execute_|ctl_alu_core_hf~28_combout ; +wire \z80_|execute_|ctl_alu_core_hf~29_combout ; +wire \z80_|execute_|ctl_alu_core_hf~30_combout ; +wire \z80_|execute_|ctl_alu_core_hf~31_combout ; +wire \z80_|execute_|ctl_alu_core_hf~36_combout ; +wire \z80_|execute_|ctl_alu_core_hf~37_combout ; +wire \z80_|execute_|ctl_alu_core_hf~32_combout ; +wire \z80_|execute_|ctl_alu_core_hf~33_combout ; +wire \z80_|alu_control_|alu_core_cf_in~0_combout ; +wire \z80_|alu_|alu_op1[0]~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ; +wire \z80_|alu_|db_high[0]~25_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~6_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ; +wire \z80_|alu_|db_high[1]~14_combout ; +wire \z80_|alu_|db_high[1]~15_combout ; +wire \z80_|alu_|db_high[1]~16_combout ; +wire \z80_|alu_|db_high[1]~17_combout ; +wire \z80_|alu_|db_high[1]~18_combout ; +wire \z80_|alu_|db_high[1]~19_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ; +wire \z80_|alu_control_|out[6]~0_combout ; +wire \z80_|alu_control_|out[6]~1_combout ; +wire \z80_|alu_control_|out[6]~2_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ; +wire \z80_|execute_|ctl_flags_sz_we~7_combout ; +wire \z80_|execute_|ctl_flags_sz_we~8_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ; +wire \z80_|execute_|setM1~51_combout ; +wire \z80_|execute_|ctl_flags_oe~2_combout ; +wire \z80_|execute_|ctl_sw_2u~7_combout ; +wire \z80_|alu_control_|db[6]~20_combout ; +wire \z80_|alu_control_|db[6]~21_combout ; +wire \z80_|execute_|ctl_reg_out_lo~8_combout ; +wire \z80_|alu_control_|db[6]~10_combout ; +wire \z80_|alu_control_|db[6]~11_combout ; +wire \z80_|alu_control_|db[6]~22_combout ; +wire \z80_|alu_|db[6]~21_combout ; +wire \z80_|alu_|db[6]~22_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~80_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~79_combout ; +wire \z80_|reg_file_|b2v_latch_bc_hi|latch[6]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~78_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~82_combout ; +wire \z80_|reg_file_|b2v_latch_hl2_hi|db[6]~5_combout ; +wire \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~76_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~77_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~83_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~84_combout ; +wire \z80_|reg_file_|db_hi_as[6]~22_combout ; +wire \z80_|reg_file_|db_hi_as[6]~23_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~61_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~62_combout ; +wire \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~60_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~63_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~64_combout ; +wire \z80_|reg_file_|b2v_latch_hl2_hi|db[4]~4_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~58_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~59_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~65_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~66_combout ; +wire \z80_|reg_file_|db_hi_as[4]~16_combout ; +wire \z80_|reg_file_|db_hi_as[4]~17_combout ; +wire \z80_|reg_file_|db_hi_as[4]~18_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ; +wire \z80_|reg_file_|db_hi_as[6]~24_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|address[15]~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|address[15]~1_combout ; +wire \z80_|reg_file_|db_hi_as[7]~19_combout ; +wire \z80_|reg_file_|db_hi_as[7]~20_combout ; +wire \z80_|reg_file_|db_hi_as[7]~21_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[7]~15_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~72_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~71_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~70_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~69_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~73_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~68_combout ; +wire \z80_|reg_file_|b2v_latch_de_hi|latch[7]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~67_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~74_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~75_combout ; +wire \z80_|alu_|db[7]~11_combout ; +wire \z80_|alu_|db[7]~12_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf2~q ; +wire \z80_|execute_|ctl_flags_use_cf2~8_combout ; +wire \z80_|execute_|ctl_flags_use_cf2~9_combout ; +wire \z80_|execute_|ctl_flags_use_cf2~10_combout ; +wire \z80_|execute_|ctl_flags_use_cf2~11_combout ; +wire \z80_|execute_|ctl_flags_use_cf2~12_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ; +wire \z80_|execute_|ctl_alu_op_low~46_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~9_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~3_combout ; +wire \z80_|alu_flags_|flags_cf~combout ; +wire \z80_|sw2_|db_up[0]~0_combout ; +wire \z80_|alu_control_|db[0]~8_combout ; +wire \z80_|reg_file_|db_lo_as[0]~0_combout ; +wire \z80_|reg_file_|db_lo_as[0]~1_combout ; +wire \z80_|execute_|ctl_inc_cy~70_combout ; +wire \z80_|execute_|pc_inc_hold~28_combout ; +wire \z80_|execute_|pc_inc_hold~15_combout ; +wire \z80_|execute_|pc_inc_hold~27_combout ; +wire \z80_|execute_|pc_inc_hold~10_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ; +wire \z80_|execute_|pc_inc_hold~11_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ; +wire \z80_|execute_|pc_inc_hold~9_combout ; +wire \z80_|execute_|pc_inc_hold~12_combout ; +wire \z80_|execute_|pc_inc_hold~7_combout ; +wire \z80_|execute_|pc_inc_hold~8_combout ; +wire \z80_|execute_|pc_inc_hold~13_combout ; +wire \z80_|execute_|pc_inc_hold~14_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ; +wire \z80_|execute_|pc_inc_hold~16_combout ; +wire \z80_|execute_|pc_inc_hold~22_combout ; +wire \z80_|execute_|pc_inc_hold~23_combout ; +wire \z80_|execute_|pc_inc_hold~24_combout ; +wire \z80_|execute_|ctl_inc_cy~41_combout ; +wire \z80_|execute_|pc_inc_hold~21_combout ; +wire \z80_|execute_|pc_inc_hold~25_combout ; +wire \z80_|execute_|ctl_inc_cy~69_combout ; +wire \z80_|execute_|pc_inc_hold~17_combout ; +wire \z80_|execute_|ctl_inc_cy~71_combout ; +wire \z80_|execute_|ctl_inc_cy~44_combout ; +wire \z80_|execute_|ctl_inc_cy~42_combout ; +wire \z80_|execute_|ctl_inc_cy~43_combout ; +wire \z80_|execute_|ctl_inc_cy~57_combout ; +wire \z80_|execute_|ctl_inc_cy~54_combout ; +wire \z80_|execute_|ctl_inc_cy~58_combout ; +wire \z80_|execute_|pc_inc_hold~18_combout ; +wire \z80_|execute_|pc_inc_hold~19_combout ; +wire \z80_|execute_|ctl_inc_cy~45_combout ; +wire \z80_|execute_|ctl_inc_cy~34_combout ; +wire \z80_|execute_|ctl_inc_cy~35_combout ; +wire \z80_|execute_|ctl_inc_cy~46_combout ; +wire \z80_|execute_|ctl_inc_cy~47_combout ; +wire \z80_|execute_|ctl_inc_cy~48_combout ; +wire \z80_|execute_|ctl_inc_cy~50_combout ; +wire \z80_|execute_|ctl_inc_cy~51_combout ; +wire \z80_|execute_|ctl_inc_cy~85_combout ; +wire \z80_|execute_|ctl_inc_cy~63_combout ; +wire \z80_|execute_|ctl_inc_cy~64_combout ; +wire \z80_|execute_|ctl_inc_cy~65_combout ; +wire \z80_|execute_|ctl_inc_cy~59_combout ; +wire \z80_|execute_|ctl_inc_cy~60_combout ; +wire \z80_|execute_|ctl_inc_cy~61_combout ; +wire \z80_|execute_|ctl_inc_cy~62_combout ; +wire \z80_|execute_|ctl_inc_cy~66_combout ; +wire \z80_|execute_|ctl_inc_cy~53_combout ; +wire \z80_|execute_|ctl_inc_cy~52_combout ; +wire \z80_|execute_|ctl_inc_cy~84_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ; +wire \z80_|execute_|ctl_inc_cy~55_combout ; +wire \z80_|execute_|ctl_inc_cy~56_combout ; +wire \z80_|execute_|ctl_inc_cy~67_combout ; +wire \z80_|execute_|pc_inc_hold~20_combout ; +wire \z80_|execute_|ctl_inc_cy~83_combout ; +wire \z80_|execute_|ctl_inc_cy~68_combout ; +wire \z80_|address_latch_|Q[0]~feeder_combout ; +wire \z80_|execute_|ctl_inc_cy~72_combout ; +wire \z80_|execute_|ctl_inc_cy~73_combout ; +wire \z80_|execute_|ctl_inc_cy~74_combout ; +wire \z80_|execute_|ctl_inc_cy~75_combout ; +wire \z80_|execute_|ctl_inc_cy~76_combout ; +wire \z80_|execute_|ctl_inc_cy~80_combout ; +wire \z80_|execute_|ctl_inc_cy~81_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ; +wire \z80_|reg_file_|db_lo_as[0]~3_combout ; +wire \z80_|reg_file_|b2v_latch_af_lo|latch[0]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~13_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~12_combout ; +wire \z80_|reg_file_|b2v_latch_de_lo|latch[0]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~10_combout ; +wire \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~11_combout ; +wire \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~14_combout ; +wire \z80_|reg_file_|b2v_latch_sp_lo|latch[0]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~15_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~16_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~17_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~22_combout ; +wire \z80_|alu_control_|db[0]~9_combout ; +wire \z80_|alu_control_|db[0]~12_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~84_combout ; +wire \z80_|reg_file_|b2v_latch_de_lo|latch[7]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~83_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~88_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~86_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~87_combout ; +wire \z80_|reg_file_|b2v_latch_wz_lo|db[7]~0_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~89_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~85_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~90_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~91_combout ; +wire \z80_|reg_file_|db_lo_as[7]~22_combout ; +wire \z80_|reg_file_|db_lo_as[7]~23_combout ; +wire \z80_|reg_file_|db_lo_as[7]~24_combout ; +wire \z80_|address_latch_|Q[7]~feeder_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ; +wire \z80_|reg_file_|db_hi_as[0]~4_combout ; +wire \z80_|reg_file_|db_hi_as[0]~5_combout ; +wire \z80_|reg_file_|db_hi_as[0]~6_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~23_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~25_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~27_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~24_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~26_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~28_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[0]~11_combout ; +wire \z80_|reg_file_|b2v_latch_de_hi|latch[0]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~22_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~29_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~30_combout ; +wire \z80_|alu_|db[0]~13_combout ; +wire \z80_|alu_|db[0]~14_combout ; +wire \z80_|alu_|db_low[1]~10_combout ; +wire \z80_|alu_|db_low[1]~11_combout ; +wire \z80_|alu_|db_low[1]~8_combout ; +wire \z80_|alu_|db_low[1]~7_combout ; +wire \z80_|alu_|result_lo[1]~feeder_combout ; +wire \z80_|alu_|db_low[1]~9_combout ; +wire \z80_|alu_|db_low[1]~12_combout ; +wire \z80_|alu_|db[1]~8_combout ; +wire \z80_|alu_|db[1]~10_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~12_combout ; +wire \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~11_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~10_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~13_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~14_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[1]~10_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~9_combout ; +wire \z80_|reg_file_|b2v_latch_de_hi|latch[1]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~8_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~15_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~21_combout ; +wire \z80_|reg_file_|db_hi_as[1]~0_combout ; +wire \z80_|reg_file_|db_hi_as[1]~1_combout ; +wire \z80_|reg_file_|db_hi_as[1]~3_combout ; +wire \z80_|address_latch_|Q[9]~feeder_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ; +wire \z80_|reg_file_|db_hi_as[2]~7_combout ; +wire \z80_|reg_file_|db_hi_as[2]~8_combout ; +wire \z80_|reg_file_|db_hi_as[2]~9_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~39_combout ; +wire \z80_|alu_|db[2]~15_combout ; +wire \z80_|alu_|db[2]~16_combout ; +wire \z80_|alu_control_|db[2]~27_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ; +wire \z80_|alu_flags_|flags_hf2~0_combout ; +wire \z80_|alu_flags_|flags_hf2~q ; +wire \z80_|alu_control_|db[2]~23_combout ; +wire \z80_|alu_control_|db[2]~29_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~39_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~35_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~40_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~41_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~42_combout ; +wire \z80_|reg_file_|db_lo_as[2]~7_combout ; +wire \z80_|reg_file_|db_lo_as[2]~8_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ; +wire \z80_|reg_file_|db_lo_as[2]~9_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ; +wire \z80_|reg_file_|db_lo_as[3]~10_combout ; +wire \z80_|reg_file_|db_lo_as[3]~11_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ; +wire \z80_|reg_file_|db_lo_as[3]~12_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ; +wire \z80_|reg_file_|db_hi_as[3]~12_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~41_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~45_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~44_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~43_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~42_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~46_combout ; +wire \z80_|reg_file_|b2v_latch_de_hi|latch[3]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~40_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[3]~13_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~47_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~48_combout ; +wire \z80_|alu_|db[3]~19_combout ; +wire \z80_|alu_|db[3]~20_combout ; +wire \z80_|alu_|db_low[2]~21_combout ; +wire \z80_|alu_|db_low[2]~22_combout ; +wire \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~6_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~7_combout ; +wire \z80_|alu_|db_low[2]~18_combout ; +wire \z80_|alu_|db_low[2]~19_combout ; +wire \z80_|alu_|db_low[2]~20_combout ; +wire \z80_|alu_|db_low[2]~23_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~7_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~8_combout ; +wire \z80_|alu_|alu_op1[2]~1_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ; wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ; wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ; @@ -1350,449 +1582,292 @@ wire \z80_|execute_|ctl_flags_hf_we~3_combout ; wire \z80_|execute_|ctl_flags_hf_we~4_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_hf~q ; -wire \z80_|execute_|ctl_flags_hf_cpl~11_combout ; -wire \z80_|execute_|ctl_flags_hf_cpl~12_combout ; -wire \z80_|execute_|ctl_flags_hf_cpl~13_combout ; wire \z80_|alu_flags_|flags_hf~combout ; -wire \z80_|alu_control_|alu_core_cf_in~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ; -wire \z80_|alu_|db_high[0]~23_combout ; -wire \z80_|address_latch_|Q[12]~feeder_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ; -wire \z80_|reg_file_|db_hi_as[4]~16_combout ; -wire \z80_|reg_file_|db_hi_as[4]~17_combout ; -wire \z80_|reg_file_|db_hi_as[4]~18_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~62_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~63_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~61_combout ; -wire \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~60_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~64_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~59_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~58_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[4]~19_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~65_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~66_combout ; -wire \z80_|alu_|db[4]~16_combout ; -wire \z80_|alu_|db[7]~26_combout ; +wire \z80_|alu_control_|db[4]~30_combout ; +wire \z80_|alu_control_|db[4]~31_combout ; +wire \z80_|alu_control_|db[4]~32_combout ; wire \z80_|alu_|db[4]~17_combout ; -wire \z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ; -wire \z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ; -wire \z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ; -wire \z80_|alu_|db_high[0]~24_combout ; -wire \z80_|alu_|db_high[0]~21_combout ; -wire \z80_|alu_|db_high[0]~22_combout ; -wire \z80_|alu_|db_high[0]~25_combout ; -wire \z80_|alu_|db_high[0]~26_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|ena~combout ; -wire \z80_|alu_|alu_op1[0]~1_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ; -wire \z80_|alu_|alu_op1[1]~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ; -wire \z80_|alu_|alu_op1[2]~2_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ; -wire \z80_|execute_|ctl_alu_core_R~5_combout ; +wire \z80_|alu_|db[4]~18_combout ; +wire \z80_|alu_|db_low[3]~13_combout ; +wire \z80_|alu_|db_low[3]~14_combout ; +wire \z80_|alu_|db_low[3]~17_combout ; +wire \z80_|alu_|db_low[3]~25_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~4_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~5_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1_combout ; +wire \z80_|alu_|alu_op2[3]~2_combout ; wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout ; wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ; -wire \z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~69_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~70_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~72_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~71_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~73_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~67_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[7]~20_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~68_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~74_combout ; -wire \z80_|reg_file_|db_hi_as[7]~19_combout ; -wire \z80_|reg_file_|db_hi_as[7]~20_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~54_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~53_combout ; -wire \z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~51_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~52_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~55_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~49_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~50_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[5]~14_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~56_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~57_combout ; -wire \z80_|reg_file_|db_hi_as[5]~13_combout ; -wire \z80_|reg_file_|db_hi_as[5]~14_combout ; -wire \z80_|reg_file_|db_hi_as[5]~15_combout ; -wire \z80_|address_latch_|Q[13]~feeder_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~76_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~80_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~79_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~78_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~81_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~82_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~77_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[6]~21_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~83_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~84_combout ; -wire \z80_|reg_file_|db_hi_as[6]~22_combout ; -wire \z80_|reg_file_|db_hi_as[6]~23_combout ; -wire \z80_|reg_file_|db_hi_as[6]~24_combout ; -wire \z80_|address_latch_|Q[14]~feeder_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout ; -wire \z80_|reg_file_|db_hi_as[7]~21_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~75_combout ; -wire \z80_|alu_|db[7]~20_combout ; -wire \z80_|alu_|db[7]~21_combout ; -wire \z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ; -wire \z80_|execute_|ctl_flags_cf_we~4_combout ; -wire \z80_|execute_|ctl_flags_cf_we~5_combout ; -wire \z80_|execute_|ctl_flags_cf_we~3_combout ; -wire \z80_|execute_|ctl_flags_cf_we~6_combout ; -wire \z80_|execute_|ctl_flags_cf2_we~2_combout ; -wire \z80_|execute_|ctl_flags_cf2_we~4_combout ; -wire \z80_|execute_|ctl_flags_cf2_we~3_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf~q ; -wire \z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ; -wire \z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ; -wire \z80_|alu_|db_high[3]~5_combout ; -wire \z80_|alu_|db_high[3]~6_combout ; +wire \z80_|alu_|db_high[3]~3_combout ; wire \z80_|alu_|db_high[3]~4_combout ; -wire \z80_|alu_|db_high[3]~27_combout ; +wire \z80_|alu_|db_high[3]~5_combout ; +wire \z80_|alu_|db_high[3]~2_combout ; +wire \z80_|alu_|db_high[3]~6_combout ; wire \z80_|alu_|db_high[3]~7_combout ; -wire \z80_|alu_|db_high[3]~8_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4_combout ; -wire \z80_|alu_|db_low[3]~9_combout ; -wire \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ; -wire \z80_|alu_|db_low[3]~10_combout ; -wire \z80_|alu_|db_low[3]~7_combout ; -wire \z80_|alu_|db_low[3]~8_combout ; -wire \z80_|alu_|db_low[3]~11_combout ; -wire \z80_|alu_|db_low[3]~25_combout ; -wire \z80_|alu_|db[3]~10_combout ; -wire \z80_|alu_|db[3]~11_combout ; -wire \z80_|execute_|ctl_sw_2u~7_combout ; -wire \z80_|execute_|setM1~49_combout ; -wire \z80_|execute_|ctl_flags_oe~2_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ; -wire \z80_|execute_|ctl_flags_sz_we~7_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ; -wire \z80_|execute_|ctl_flags_xy_we~13_combout ; -wire \z80_|execute_|ctl_flags_xy_we~14_combout ; -wire \z80_|execute_|ctl_flags_xy_we~15_combout ; -wire \z80_|alu_flags_|flags_xf~q ; -wire \z80_|alu_control_|db[3]~33_combout ; -wire \z80_|execute_|ctl_reg_out_lo~3_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ; -wire \z80_|execute_|ctl_reg_out_lo~4_combout ; -wire \z80_|execute_|ctl_reg_out_lo~5_combout ; -wire \z80_|execute_|ctl_reg_out_lo~8_combout ; -wire \z80_|sw1_|db_down[3]~1_combout ; -wire \z80_|alu_control_|db[3]~34_combout ; -wire \z80_|alu_control_|db[3]~35_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~46_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~47_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~50_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~44_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~43_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~51_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~52_combout ; -wire \z80_|reg_file_|db_lo_as[3]~10_combout ; -wire \z80_|reg_file_|db_lo_as[3]~11_combout ; -wire \z80_|reg_file_|db_lo_as[3]~12_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~53_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~54_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~58_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~59_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~60_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~57_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~55_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~56_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~61_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~62_combout ; -wire \z80_|reg_file_|db_lo_as[4]~13_combout ; -wire \z80_|reg_file_|db_lo_as[4]~14_combout ; -wire \z80_|reg_file_|db_lo_as[4]~15_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~64_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~63_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~66_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~67_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~65_combout ; -wire \z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~69_combout ; -wire \z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~68_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~70_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~71_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~72_combout ; -wire \z80_|reg_file_|db_lo_as[5]~16_combout ; -wire \z80_|reg_file_|db_lo_as[5]~17_combout ; -wire \z80_|reg_file_|db_lo_as[5]~18_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout ; -wire \z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~74_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~73_combout ; -wire \z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~78_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~79_combout ; -wire \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~76_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~77_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~80_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~75_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~81_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~82_combout ; -wire \z80_|reg_file_|db_lo_as[6]~19_combout ; -wire \z80_|reg_file_|db_lo_as[6]~20_combout ; -wire \z80_|reg_file_|db_lo_as[6]~21_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ; -wire \z80_|reg_file_|db_lo_as[7]~24_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~83_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~84_combout ; -wire \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~88_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~86_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~87_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~85_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~89_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~90_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~91_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~92_combout ; -wire \z80_|reg_file_|db_lo_ds[7]~0_combout ; -wire \z80_|interrupts_|im2~q ; -wire \z80_|execute_|ctl_mRead~12_combout ; -wire \z80_|execute_|ctl_sw_mask543_en~0_combout ; -wire \z80_|alu_control_|db[7]~17_combout ; -wire \z80_|alu_control_|db[7]~16_combout ; -wire \z80_|alu_control_|db[7]~18_combout ; wire \z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ; -wire \z80_|execute_|ctl_flags_sz_we~8_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_sf~q ; -wire \z80_|pla_decode_|Equal62~3_combout ; -wire \z80_|execute_|ctl_flags_pf_we~5_combout ; -wire \z80_|execute_|ctl_flags_pf_we~6_combout ; -wire \z80_|execute_|ctl_flags_pf_we~7_combout ; -wire \z80_|execute_|ctl_flags_pf_we~8_combout ; -wire \z80_|execute_|ctl_flags_pf_we~9_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~5_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~7_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~6_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~8_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~11_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~12_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~15_combout ; +wire \z80_|alu_|alu_op2[2]~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ; +wire \z80_|alu_control_|DFFE_latch_pf_tmp~q ; +wire \z80_|alu_|alu_parity_out~0_combout ; +wire \z80_|alu_|alu_parity_out~1_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ; -wire \z80_|decode_state_|DFFE_instNonRep~0_combout ; -wire \z80_|decode_state_|DFFE_instNonRep~3_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~1_combout ; wire \z80_|decode_state_|DFFE_instNonRep~2_combout ; wire \z80_|decode_state_|DFFE_instNonRep~1_combout ; +wire \z80_|decode_state_|DFFE_instNonRep~3_combout ; +wire \z80_|decode_state_|DFFE_instNonRep~0_combout ; wire \z80_|decode_state_|DFFE_instNonRep~4_combout ; wire \z80_|decode_state_|DFFE_instNonRep~5_combout ; wire \z80_|decode_state_|DFFE_instNonRep~q ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~1_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ; -wire \z80_|alu_control_|DFFE_latch_pf_tmp~q ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ; -wire \z80_|alu_|alu_parity_out~0_combout ; -wire \z80_|alu_|alu_parity_out~combout ; wire \z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_pf~10_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_pf~q ; wire \z80_|alu_control_|sel[1]~0_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ; wire \z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ; wire \z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ; wire \z80_|alu_control_|flags_cond_true~0_combout ; wire \z80_|alu_control_|flags_cond_true~q ; -wire \z80_|execute_|ctl_reg_sel_wz~13_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~14_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~17_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~18_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~20_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~21_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~20_combout ; +wire \z80_|execute_|ctl_sw_4d~1_combout ; +wire \z80_|execute_|ctl_sw_4d~6_combout ; +wire \z80_|reg_file_|db_lo_as[1]~4_combout ; +wire \z80_|reg_file_|db_lo_as[1]~5_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ; +wire \z80_|reg_file_|db_lo_as[1]~6_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~29_combout ; wire \z80_|reg_file_|gdfx_temp0[1]~28_combout ; wire \z80_|reg_file_|gdfx_temp0[1]~26_combout ; wire \z80_|reg_file_|gdfx_temp0[1]~27_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~29_combout ; -wire \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~25_combout ; wire \z80_|reg_file_|gdfx_temp0[1]~30_combout ; -wire \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder_combout ; wire \z80_|reg_file_|gdfx_temp0[1]~24_combout ; wire \z80_|reg_file_|gdfx_temp0[1]~23_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~25_combout ; wire \z80_|reg_file_|gdfx_temp0[1]~31_combout ; wire \z80_|reg_file_|gdfx_temp0[1]~32_combout ; wire \z80_|reg_file_|db_lo_ds[1]~1_combout ; wire \z80_|alu_control_|db[1]~25_combout ; wire \z80_|alu_control_|db[1]~24_combout ; wire \z80_|alu_control_|db[1]~26_combout ; -wire \z80_|alu_|db[1]~12_combout ; -wire \z80_|alu_|db[1]~13_combout ; -wire \z80_|alu_|db_low[0]~21_combout ; -wire \z80_|alu_|db_low[0]~22_combout ; -wire \z80_|alu_|db_low[0]~18_combout ; -wire \z80_|alu_|db_low[0]~19_combout ; -wire \z80_|alu_|db_low[0]~20_combout ; -wire \z80_|alu_|db_low[0]~23_combout ; -wire \z80_|alu_|db[0]~18_combout ; -wire \z80_|alu_|db[0]~19_combout ; -wire \z80_|alu_|db_low[1]~15_combout ; -wire \z80_|alu_|db_low[1]~16_combout ; -wire \z80_|alu_|db_low[1]~12_combout ; -wire \z80_|alu_|db_low[1]~13_combout ; -wire \z80_|alu_|db_low[1]~14_combout ; -wire \z80_|alu_|db_low[1]~17_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6_combout ; -wire \z80_|alu_control_|out[6]~0_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ; -wire \z80_|alu_flags_|flags_hf2~0_combout ; -wire \z80_|alu_flags_|flags_hf2~q ; -wire \z80_|alu_control_|db[2]~23_combout ; -wire \z80_|reg_file_|db_lo_ds[2]~2_combout ; -wire \z80_|alu_control_|db[2]~28_combout ; -wire \z80_|alu_control_|db[2]~27_combout ; -wire \z80_|alu_control_|db[2]~29_combout ; -wire \z80_|alu_|db[2]~14_combout ; -wire \z80_|alu_|db[2]~15_combout ; -wire \z80_|alu_|db_low[2]~2_combout ; -wire \z80_|alu_|db_low[2]~3_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1_combout ; -wire \z80_|alu_|db_low[2]~5_combout ; -wire \z80_|alu_|db_low[2]~6_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4_combout ; -wire \z80_|alu_|alu_op2[2]~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ; -wire \z80_|alu_|db_high[2]~9_combout ; -wire \z80_|alu_|db_high[2]~11_combout ; -wire \z80_|alu_|db_high[2]~12_combout ; -wire \z80_|alu_|db_high[2]~10_combout ; -wire \z80_|alu_|db_high[2]~13_combout ; -wire \z80_|alu_|db_high[2]~14_combout ; -wire \z80_|alu_|db[6]~22_combout ; -wire \z80_|alu_|db[6]~23_combout ; -wire \z80_|alu_control_|out[6]~1_combout ; -wire \z80_|alu_control_|out[6]~2_combout ; -wire \z80_|alu_control_|db[6]~19_combout ; -wire \z80_|alu_control_|db[6]~20_combout ; -wire \z80_|alu_control_|db[6]~21_combout ; -wire \z80_|alu_control_|db[6]~22_combout ; -wire \z80_|execute_|ctl_bus_zero_oe~0_combout ; -wire \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ; -wire \z80_|interrupts_|im1~q ; -wire \z80_|execute_|ctl_bus_ff_oe~0_combout ; -wire \z80_|execute_|ctl_bus_ff_oe~1_combout ; -wire \z80_|bus_control_|db[0]~4_combout ; -wire \z80_|bus_control_|db[6]~8_combout ; -wire \z80_|execute_|ctl_mRead~37_combout ; -wire \z80_|execute_|ctl_mRead~28_combout ; -wire \z80_|execute_|ctl_mRead~29_combout ; -wire \z80_|execute_|ctl_mRead~30_combout ; -wire \z80_|execute_|setM1~37_combout ; -wire \z80_|execute_|setM1~55_combout ; -wire \z80_|execute_|setM1~38_combout ; -wire \z80_|execute_|ctl_mRead~34_combout ; -wire \z80_|execute_|nextM~3_combout ; -wire \z80_|execute_|ctl_mRead~31_combout ; -wire \z80_|execute_|ctl_mRead~32_combout ; -wire \z80_|execute_|ctl_mRead~33_combout ; -wire \z80_|execute_|ctl_mRead~35_combout ; -wire \z80_|memory_ifc_|DFFE_mrd_ff1~q ; -wire \z80_|memory_ifc_|wait_mrd~feeder_combout ; -wire \z80_|memory_ifc_|wait_mrd~q ; -wire \z80_|memory_ifc_|DFFE_mrd_ff3~q ; -wire \z80_|memory_ifc_|nRD_out~1_combout ; +wire \z80_|bus_control_|db[1]~10_combout ; wire \z80_|execute_|nextM~4_combout ; wire \z80_|execute_|ctl_iorw~12_combout ; wire \z80_|execute_|ctl_iorw~8_combout ; wire \z80_|execute_|ctl_iorw~9_combout ; wire \z80_|memory_ifc_|DFFE_iorq_ff1~q ; -wire \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder_combout ; wire \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ; +wire \z80_|memory_ifc_|wait_iorq~feeder_combout ; wire \z80_|memory_ifc_|wait_iorq~q ; wire \z80_|memory_ifc_|DFFE_iorq_ff4~q ; wire \z80_|memory_ifc_|iorq~0_combout ; -wire \z80_|execute_|fIORead~1_combout ; -wire \z80_|execute_|fIORead~2_combout ; -wire \z80_|execute_|fIORead~0_combout ; -wire \z80_|execute_|fIORead~3_combout ; wire \z80_|memory_ifc_|DFFE_m1_ff1~q ; wire \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout ; wire \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ; wire \z80_|memory_ifc_|DFFE_m1_ff3~q ; wire \z80_|memory_ifc_|nRD_out~0_combout ; +wire \z80_|execute_|fIORead~0_combout ; +wire \z80_|execute_|fIORead~1_combout ; +wire \z80_|execute_|fIORead~2_combout ; +wire \z80_|execute_|fIOWrite~1_combout ; +wire \z80_|execute_|fIORead~3_combout ; +wire \z80_|execute_|ctl_mRead~30_combout ; +wire \z80_|execute_|ctl_mRead~31_combout ; +wire \z80_|execute_|nextM~3_combout ; +wire \z80_|execute_|ctl_mRead~29_combout ; +wire \z80_|execute_|setM1~58_combout ; +wire \z80_|execute_|setM1~38_combout ; +wire \z80_|execute_|fMRead~4_combout ; +wire \z80_|execute_|setM1~39_combout ; +wire \z80_|execute_|setM1~40_combout ; +wire \z80_|execute_|ctl_mRead~32_combout ; +wire \z80_|execute_|ctl_mRead~33_combout ; +wire \z80_|memory_ifc_|DFFE_mrd_ff1~q ; +wire \z80_|memory_ifc_|wait_mrd~feeder_combout ; +wire \z80_|memory_ifc_|wait_mrd~q ; +wire \z80_|memory_ifc_|DFFE_mrd_ff3~q ; +wire \z80_|memory_ifc_|nRD_out~1_combout ; wire \z80_|memory_ifc_|nRD_out~2_combout ; +wire \z80_|execute_|fIOWrite~3_combout ; +wire \z80_|execute_|fIOWrite~4_combout ; +wire \z80_|execute_|fIOWrite~2_combout ; +wire \z80_|execute_|fIOWrite~5_combout ; +wire \z80_|execute_|ctl_mWrite~15_combout ; +wire \z80_|execute_|ctl_mWrite~12_combout ; +wire \z80_|execute_|ctl_mWrite~13_combout ; +wire \z80_|execute_|ctl_mWrite~14_combout ; +wire \z80_|execute_|ctl_mWrite~16_combout ; +wire \z80_|memory_ifc_|DFFE_mwr_ff1~q ; +wire \z80_|memory_ifc_|wait_mwr~feeder_combout ; +wire \z80_|memory_ifc_|wait_mwr~q ; +wire \z80_|memory_ifc_|mwr_wr~q ; +wire \z80_|memory_ifc_|nWR_out~0_combout ; wire \Equal2~1_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~0_combout ; -wire \z80_|execute_|fMWrite~5_combout ; -wire \z80_|execute_|fMWrite~6_combout ; -wire \z80_|execute_|fMWrite~2_combout ; +wire \z80_|execute_|fMWrite~3_combout ; wire \z80_|execute_|fMWrite~4_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~1_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~2_combout ; +wire \z80_|execute_|fMWrite~0_combout ; +wire \z80_|execute_|fMWrite~2_combout ; wire \z80_|pin_control_|bus_db_pin_oe~3_combout ; -wire \z80_|execute_|fMWrite~7_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~4_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~7_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~6_combout ; -wire \z80_|execute_|fMWrite~9_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~8_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~9_combout ; wire \z80_|execute_|fMWrite~8_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~5_combout ; +wire \z80_|execute_|fMWrite~7_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~16_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~8_combout ; +wire \z80_|execute_|fMWrite~6_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~9_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~7_combout ; wire \z80_|pin_control_|bus_db_pin_oe~10_combout ; -wire \z80_|execute_|fMWrite~10_combout ; wire \z80_|pin_control_|bus_db_pin_oe~11_combout ; +wire \z80_|execute_|fMWrite~5_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~6_combout ; wire \z80_|pin_control_|bus_db_pin_oe~12_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~4_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~5_combout ; wire \z80_|pin_control_|bus_db_pin_oe~13_combout ; wire \z80_|pin_control_|bus_db_pin_oe~14_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~2_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~15_combout ; wire \z80_|clk_delay_|DFF_inst5~feeder_combout ; wire \z80_|clk_delay_|DFF_inst5~q ; -wire \z80_|memory_ifc_|wait_iorqinta~feeder_combout ; wire \z80_|memory_ifc_|wait_iorqinta~q ; wire \z80_|memory_ifc_|DFFE_intr_ff3~q ; wire \z80_|memory_ifc_|nIORQ_out~0_combout ; wire \Equal2~0_combout ; -wire \ExtRamWE~0_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[13]~13_combout ; +wire \z80_|execute_|ctl_apin_mux~2_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[10]~10_combout ; wire \z80_|execute_|ctl_apin_mux2~0_combout ; -wire \z80_|pin_control_|bus_ab_pin_we~2_combout ; -wire \z80_|pin_control_|bus_ab_pin_we~3_combout ; +wire \z80_|pin_control_|bus_ab_pin_we~0_combout ; +wire \z80_|pin_control_|bus_ab_pin_we~1_combout ; +wire \PS2_DAT~input_o ; +wire \ula_|pll_|altpll_component|auto_generated|wire_pll1_locked ; +wire \KEY[0]~input_o ; +wire \reset~combout ; +wire \reset~clkctrl_outclk ; +wire \ula_|ps2_keyboard_|bit_count~3_combout ; +wire \PS2_CLK~input_o ; +wire \ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ; +wire \ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ; +wire \ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ; +wire \ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ; +wire \ula_|ps2_keyboard_|clk_filter[3]~feeder_combout ; +wire \ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ; +wire \ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ; +wire \ula_|ps2_keyboard_|Equal0~0_combout ; +wire \ula_|ps2_keyboard_|Equal0~1_combout ; +wire \ula_|ps2_keyboard_|clk_filter[0]~0_combout ; +wire \ula_|ps2_keyboard_|ps2_clk_in~0_combout ; +wire \ula_|ps2_keyboard_|ps2_clk_in~q ; +wire \ula_|ps2_keyboard_|clk_edge~0_combout ; +wire \ula_|ps2_keyboard_|clk_edge~q ; +wire \ula_|ps2_keyboard_|bit_count~1_combout ; +wire \ula_|ps2_keyboard_|bit_count~2_combout ; +wire \ula_|ps2_keyboard_|bit_count~0_combout ; +wire \ula_|ps2_keyboard_|always1~0_combout ; +wire \ula_|ps2_keyboard_|LessThan0~0_combout ; +wire \ula_|ps2_keyboard_|shiftreg[0]~0_combout ; +wire \ula_|ps2_keyboard_|shiftreg[7]~feeder_combout ; +wire \ula_|ps2_keyboard_|shiftreg[0]~feeder_combout ; +wire \ula_|ps2_keyboard_|WideXor0~0_combout ; +wire \ula_|ps2_keyboard_|WideXor0~1_combout ; +wire \ula_|ps2_keyboard_|WideXor0~2_combout ; +wire \ula_|ps2_keyboard_|scan_code_ready~0_combout ; +wire \ula_|ps2_keyboard_|scan_code_ready~q ; +wire \ula_|zx_keyboard_|Equal0~0_combout ; +wire \ula_|zx_keyboard_|Equal0~1_combout ; +wire \ula_|zx_keyboard_|released~0_combout ; +wire \ula_|zx_keyboard_|released~q ; +wire \ula_|zx_keyboard_|extended~0_combout ; +wire \ula_|zx_keyboard_|extended~q ; +wire \ula_|zx_keyboard_|keys[7][1]~21_combout ; +wire \ula_|zx_keyboard_|keys[5][4]~22_combout ; +wire \ula_|zx_keyboard_|keys[1][4]~23_combout ; +wire \ula_|zx_keyboard_|keys[2][1]~24_combout ; +wire \ula_|zx_keyboard_|keys[2][1]~25_combout ; +wire \ula_|zx_keyboard_|keys[2][1]~q ; +wire \ula_|zx_keyboard_|key_row~0_combout ; +wire \ula_|zx_keyboard_|keys[3][1]~26_combout ; +wire \ula_|zx_keyboard_|keys[3][1]~27_combout ; +wire \ula_|zx_keyboard_|keys[3][1]~28_combout ; +wire \ula_|zx_keyboard_|keys[3][1]~q ; +wire \z80_|address_pins_|DFFE_apin_latch[11]~11_combout ; +wire \z80_|address_pins_|abus[11]~19_combout ; +wire \ula_|zx_keyboard_|keys[7][4]~17_combout ; +wire \ula_|zx_keyboard_|keys[6][4]~18_combout ; +wire \ula_|zx_keyboard_|keys[1][1]~19_combout ; +wire \ula_|zx_keyboard_|keys[1][1]~20_combout ; +wire \ula_|zx_keyboard_|keys[1][1]~q ; +wire \z80_|address_pins_|DFFE_apin_latch[9]~9_combout ; +wire \z80_|address_pins_|abus[9]~17_combout ; +wire \ula_|zx_keyboard_|keys[0][0]~13_combout ; +wire \ula_|zx_keyboard_|shifted~2_combout ; +wire \ula_|zx_keyboard_|keys[0][1]~14_combout ; +wire \ula_|zx_keyboard_|keys[0][1]~15_combout ; +wire \ula_|zx_keyboard_|WideOr17~0_combout ; +wire \ula_|zx_keyboard_|shifted~5_combout ; +wire \ula_|zx_keyboard_|shifted~4_combout ; +wire \ula_|zx_keyboard_|shifted~q ; +wire \ula_|zx_keyboard_|keys[0][1]~12_combout ; +wire \ula_|zx_keyboard_|keys[0][1]~16_combout ; +wire \ula_|zx_keyboard_|keys[0][1]~q ; +wire \z80_|address_pins_|DFFE_apin_latch[8]~8_combout ; +wire \z80_|address_pins_|abus[8]~18_combout ; +wire \D[1]~26_combout ; +wire \D[1]~27_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[12]~12_combout ; +wire \z80_|address_pins_|abus[12]~21_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ; +wire \z80_|address_pins_|DFFE_apin_latch[13]~13_combout ; wire \z80_|address_pins_|abus[13]~20_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~36_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~34_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~35_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~33_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~37_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~q ; +wire \ula_|zx_keyboard_|keys[4][1]~29_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~30_combout ; +wire \ula_|zx_keyboard_|keys[5][2]~31_combout ; +wire \ula_|zx_keyboard_|keys[4][1]~32_combout ; +wire \ula_|zx_keyboard_|keys[4][1]~q ; +wire \D[1]~28_combout ; +wire \z80_|address_pins_|abus[0]~16_combout ; wire \z80_|address_pins_|DFFE_apin_latch[14]~14_combout ; wire \z80_|address_pins_|abus[14]~23_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~40_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~41_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~39_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~38_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~42_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~q ; +wire \ula_|zx_keyboard_|WideOr16~4_combout ; +wire \ula_|zx_keyboard_|WideOr16~2_combout ; +wire \ula_|zx_keyboard_|WideOr16~7_combout ; +wire \ula_|zx_keyboard_|WideOr16~5_combout ; +wire \ula_|zx_keyboard_|WideOr16~6_combout ; +wire \ula_|zx_keyboard_|keys[7][1]~43_combout ; +wire \ula_|zx_keyboard_|keys[7][1]~44_combout ; +wire \ula_|zx_keyboard_|keys[7][1]~q ; wire \z80_|address_pins_|DFFE_apin_latch[15]~15_combout ; wire \z80_|address_pins_|abus[15]~22_combout ; +wire \D[1]~29_combout ; +wire \D[1]~30_combout ; +wire \ExtRamWE~0_combout ; wire \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ; -wire \z80_|address_pins_|abus[0]~16_combout ; wire \z80_|address_pins_|DFFE_apin_latch[1]~1_combout ; wire \z80_|address_pins_|abus[1]~25_combout ; wire \z80_|address_pins_|DFFE_apin_latch[2]~2_combout ; @@ -1807,30 +1882,27 @@ wire \z80_|address_pins_|DFFE_apin_latch[6]~6_combout ; wire \z80_|address_pins_|abus[6]~30_combout ; wire \z80_|address_pins_|DFFE_apin_latch[7]~7_combout ; wire \z80_|address_pins_|abus[7]~31_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[8]~8_combout ; -wire \z80_|address_pins_|abus[8]~18_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[9]~9_combout ; -wire \z80_|address_pins_|abus[9]~17_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[10]~10_combout ; wire \z80_|address_pins_|abus[10]~24_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[11]~11_combout ; -wire \z80_|address_pins_|abus[11]~19_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[12]~12_combout ; -wire \z80_|address_pins_|abus[12]~21_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ; wire \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ; +wire \ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ; wire \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ; -wire \D[6]~90_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout ; wire \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ; -wire \D[6]~91_combout ; -wire \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ; wire \CLOCK_50~inputclkctrl_outclk ; +wire \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ; +wire \Selector3~0_combout ; +wire \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ; wire \~GND~combout ; wire \ula_|video_|vram_address[0]~feeder_combout ; wire \ula_|video_|vram_address~0_combout ; +wire \ula_|video_|vram_address[1]~feeder_combout ; wire \ula_|video_|vram_address[2]~4_combout ; wire \ula_|video_|Add3~0_combout ; wire \ula_|video_|Add3~1_combout ; @@ -1842,483 +1914,369 @@ wire \ula_|video_|Add4~7 ; wire \ula_|video_|Add4~8_combout ; wire \ula_|video_|Add4~9 ; wire \ula_|video_|Add4~10_combout ; +wire \ula_|video_|Add4~0_combout ; wire \ula_|video_|Add4~11 ; wire \ula_|video_|Add4~12_combout ; -wire \ula_|video_|Add4~0_combout ; wire \ula_|video_|Selector6~0_combout ; wire \ula_|video_|vram_address[9]~1_combout ; +wire \ula_|video_|Add4~2_combout ; wire \ula_|video_|Add4~13 ; wire \ula_|video_|Add4~14_combout ; -wire \ula_|video_|Add4~2_combout ; wire \ula_|video_|Selector5~0_combout ; wire \ula_|video_|Add4~4_combout ; wire \ula_|video_|vram_address[10]~2_combout ; wire \ula_|video_|vram_address[10]~3_combout ; wire \ula_|video_|Selector3~0_combout ; wire \ula_|video_|Selector2~0_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ; -wire \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ; -wire \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ; -wire \D[6]~87_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ; -wire \D[6]~88_combout ; -wire \D[6]~89_combout ; -wire \D[6]~111_combout ; -wire \raw_loader_in~input_o ; -wire \D[6]~86_combout ; -wire \D[6]~100_combout ; -wire \D[6]~101_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout ; +wire \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ; +wire \Selector1~0_combout ; +wire \Selector1~1_combout ; +wire \D[1]~81_combout ; +wire \D[1]~31_combout ; +wire \D[1]~32_combout ; wire \z80_|pin_control_|bus_db_pin_re~2_combout ; wire \z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ; -wire \z80_|bus_control_|db[6]~9_combout ; -wire \z80_|ir_|opcode[6]~feeder_combout ; -wire \z80_|execute_|ctl_ir_we~13_combout ; -wire \z80_|pla_decode_|Equal41~0_combout ; +wire \z80_|bus_control_|db[1]~11_combout ; +wire \z80_|pla_decode_|Equal2~0_combout ; +wire \z80_|execute_|ctl_mRead~15_combout ; +wire \z80_|execute_|ctl_inc_cy~39_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~36_combout ; +wire \z80_|execute_|ctl_sw_4u~4_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~16_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~17_combout ; +wire \z80_|execute_|ctl_sw_4u~5_combout ; +wire \z80_|execute_|ctl_sw_4u~6_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~44_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~43_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~46_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~47_combout ; +wire \z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~49_combout ; +wire \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~45_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~48_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~50_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~51_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~52_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ; +wire \z80_|execute_|ctl_flags_xy_we~15_combout ; +wire \z80_|execute_|ctl_flags_xy_we~16_combout ; +wire \z80_|execute_|ctl_flags_xy_we~17_combout ; +wire \z80_|execute_|ctl_flags_xy_we~18_combout ; +wire \z80_|alu_flags_|flags_xf~q ; +wire \z80_|alu_control_|db[3]~33_combout ; +wire \z80_|sw1_|db_down[3]~2_combout ; +wire \z80_|alu_control_|db[3]~34_combout ; +wire \z80_|alu_control_|db[3]~35_combout ; +wire \ula_|zx_keyboard_|keys[3][0]~75_combout ; +wire \ula_|zx_keyboard_|Selector5~0_combout ; +wire \ula_|zx_keyboard_|Selector5~1_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~132_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~106_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~107_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~133_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~108_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~q ; +wire \ula_|zx_keyboard_|keys[5][3]~104_combout ; +wire \ula_|zx_keyboard_|keys[5][3]~105_combout ; +wire \ula_|zx_keyboard_|keys[5][3]~q ; +wire \D[3]~55_combout ; +wire \ula_|zx_keyboard_|keys[6][4]~46_combout ; +wire \ula_|zx_keyboard_|keys[5][4]~62_combout ; +wire \ula_|zx_keyboard_|keys[3][3]~102_combout ; +wire \ula_|zx_keyboard_|keys[3][3]~103_combout ; +wire \ula_|zx_keyboard_|keys[3][3]~q ; +wire \ula_|zx_keyboard_|keys[0][4]~96_combout ; +wire \ula_|zx_keyboard_|keys[2][4]~94_combout ; +wire \ula_|zx_keyboard_|keys[0][3]~95_combout ; +wire \ula_|zx_keyboard_|keys[0][3]~97_combout ; +wire \ula_|zx_keyboard_|keys[0][3]~q ; +wire \ula_|zx_keyboard_|keys[6][4]~45_combout ; +wire \ula_|zx_keyboard_|keys[1][3]~92_combout ; +wire \ula_|zx_keyboard_|keys[1][3]~93_combout ; +wire \ula_|zx_keyboard_|keys[1][3]~q ; +wire \D[3]~53_combout ; +wire \ula_|zx_keyboard_|keys[2][3]~99_combout ; +wire \ula_|zx_keyboard_|keys[2][3]~100_combout ; +wire \ula_|zx_keyboard_|keys[2][3]~98_combout ; +wire \ula_|zx_keyboard_|keys[2][3]~101_combout ; +wire \ula_|zx_keyboard_|keys[2][3]~q ; +wire \ula_|zx_keyboard_|key_row~3_combout ; +wire \D[3]~54_combout ; +wire \ula_|zx_keyboard_|keys[0][4]~109_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~60_combout ; +wire \ula_|zx_keyboard_|keys[7][3]~110_combout ; +wire \ula_|zx_keyboard_|keys[7][3]~111_combout ; +wire \ula_|zx_keyboard_|keys[7][3]~112_combout ; +wire \ula_|zx_keyboard_|keys[7][3]~q ; +wire \ula_|zx_keyboard_|Selector13~0_combout ; +wire \ula_|zx_keyboard_|keys[6][3]~113_combout ; +wire \ula_|zx_keyboard_|keys[6][3]~114_combout ; +wire \ula_|zx_keyboard_|keys[6][3]~135_combout ; +wire \ula_|zx_keyboard_|keys[6][3]~136_combout ; +wire \ula_|zx_keyboard_|keys[6][3]~q ; +wire \D[3]~56_combout ; +wire \D[3]~57_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ; +wire \Selector3~1_combout ; +wire \Selector3~2_combout ; +wire \D[3]~85_combout ; +wire \D[3]~73_combout ; +wire \D[3]~74_combout ; +wire \z80_|bus_control_|db[3]~20_combout ; +wire \z80_|bus_control_|db[3]~21_combout ; +wire \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ; +wire \z80_|interrupts_|im2~q ; +wire \z80_|execute_|ctl_mRead~10_combout ; +wire \z80_|execute_|ctl_sw_mask543_en~0_combout ; +wire \z80_|alu_control_|db[7]~16_combout ; +wire \z80_|alu_control_|db[7]~17_combout ; +wire \z80_|alu_control_|db[7]~18_combout ; +wire \z80_|alu_control_|db[7]~19_combout ; +wire \z80_|bus_control_|db[7]~5_combout ; +wire \D[5]~67_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout ; +wire \Mux0~0_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ; +wire \Mux0~1_combout ; +wire \D[7]~89_combout ; +wire \D[7]~72_combout ; +wire \D[0]~84_combout ; +wire \D[7]~80_combout ; +wire \z80_|bus_control_|db[7]~7_combout ; +wire \z80_|pla_decode_|Equal6~0_combout ; +wire \z80_|pla_decode_|Equal12~0_combout ; +wire \z80_|execute_|ctl_mRead~16_combout ; +wire \z80_|execute_|fMRead~24_combout ; +wire \z80_|execute_|fMRead~25_combout ; +wire \z80_|execute_|ctl_mRead~21_combout ; +wire \z80_|execute_|fMRead~16_combout ; +wire \z80_|execute_|fMRead~14_combout ; +wire \z80_|execute_|fMRead~15_combout ; +wire \z80_|execute_|fMRead~12_combout ; +wire \z80_|execute_|fMRead~11_combout ; +wire \z80_|execute_|fMRead~13_combout ; +wire \z80_|execute_|fMRead~17_combout ; +wire \z80_|execute_|fMRead~22_combout ; +wire \z80_|execute_|fMRead~27_combout ; +wire \z80_|execute_|fMRead~37_combout ; +wire \z80_|execute_|fMRead~31_combout ; +wire \z80_|execute_|fMRead~29_combout ; +wire \z80_|execute_|fMRead~30_combout ; +wire \z80_|execute_|fMRead~28_combout ; +wire \z80_|execute_|fMRead~32_combout ; +wire \z80_|execute_|fMRead~33_combout ; +wire \z80_|execute_|fMRead~23_combout ; +wire \z80_|execute_|fMRead~34_combout ; +wire \z80_|execute_|fMRead~35_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~19_combout ; +wire \z80_|execute_|fMRead~36_combout ; +wire \z80_|pin_control_|bus_db_pin_re~combout ; +wire \ula_|zx_keyboard_|keys[2][4]~118_combout ; +wire \ula_|zx_keyboard_|keys[2][4]~119_combout ; +wire \ula_|zx_keyboard_|keys[2][4]~120_combout ; +wire \ula_|zx_keyboard_|keys[2][4]~q ; +wire \ula_|zx_keyboard_|keys[3][4]~129_combout ; +wire \ula_|zx_keyboard_|keys[3][4]~116_combout ; +wire \ula_|zx_keyboard_|keys[3][4]~134_combout ; +wire \ula_|zx_keyboard_|keys[3][4]~117_combout ; +wire \ula_|zx_keyboard_|keys[3][4]~q ; +wire \D[4]~60_combout ; +wire \ula_|zx_keyboard_|Equal0~2_combout ; +wire \ula_|zx_keyboard_|keys[1][4]~121_combout ; +wire \ula_|zx_keyboard_|keys[1][4]~q ; +wire \ula_|zx_keyboard_|keys[0][4]~115_combout ; +wire \ula_|zx_keyboard_|keys[0][4]~q ; +wire \ula_|zx_keyboard_|key_row~4_combout ; +wire \D[4]~61_combout ; +wire \ula_|zx_keyboard_|keys[4][4]~124_combout ; +wire \ula_|zx_keyboard_|keys[4][4]~125_combout ; +wire \ula_|zx_keyboard_|keys[4][4]~126_combout ; +wire \ula_|zx_keyboard_|keys[4][4]~q ; +wire \ula_|zx_keyboard_|keys[5][4]~122_combout ; +wire \ula_|zx_keyboard_|keys[5][4]~123_combout ; +wire \ula_|zx_keyboard_|keys[5][4]~q ; +wire \D[4]~62_combout ; +wire \ula_|zx_keyboard_|keys[7][4]~49_combout ; +wire \ula_|zx_keyboard_|shifted~3_combout ; +wire \ula_|zx_keyboard_|keys[7][4]~127_combout ; +wire \ula_|zx_keyboard_|keys[7][4]~q ; +wire \ula_|zx_keyboard_|keys[6][4]~128_combout ; +wire \ula_|zx_keyboard_|keys[6][4]~q ; +wire \D[4]~63_combout ; +wire \D[4]~64_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ; +wire \Selector4~0_combout ; +wire \Selector4~1_combout ; +wire \D[4]~86_combout ; +wire \D[4]~75_combout ; +wire \D[4]~76_combout ; +wire \z80_|bus_control_|db[4]~18_combout ; +wire \z80_|bus_control_|db[4]~19_combout ; +wire \z80_|pla_decode_|Equal32~0_combout ; wire \z80_|pla_decode_|Equal41~1_combout ; wire \z80_|pla_decode_|Equal41~2_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~combout ; -wire \z80_|alu_|db_high[1]~15_combout ; -wire \z80_|alu_|db_high[1]~16_combout ; -wire \z80_|alu_|db_high[1]~17_combout ; -wire \z80_|alu_|db_high[1]~18_combout ; -wire \z80_|alu_|db_high[1]~19_combout ; -wire \z80_|alu_|db_high[1]~20_combout ; +wire \z80_|pla_decode_|Equal36~0_combout ; +wire \z80_|execute_|ctl_state_tbl_cb_set~combout ; +wire \z80_|execute_|ctl_state_tbl_we~8_combout ; +wire \z80_|decode_state_|DFFE_instCB~q ; +wire \z80_|pla_decode_|Equal52~0_combout ; +wire \z80_|pla_decode_|Equal2~1_combout ; +wire \z80_|execute_|ctl_state_tbl_ed_set~combout ; +wire \z80_|decode_state_|DFFE_instED~q ; +wire \z80_|decode_state_|table_xx~0_combout ; +wire \z80_|pla_decode_|Equal34~0_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~6_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~5_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~4_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~2_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~3_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~7_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~8_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~9_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~10_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~16_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~17_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~15_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~18_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~19_combout ; +wire \z80_|reg_control_|reg_sel_pc~3_combout ; +wire \z80_|reg_control_|reg_sel_pc~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ; +wire \z80_|reg_file_|db_hi_as[0]~2_combout ; +wire \z80_|reg_file_|db_hi_as[5]~13_combout ; +wire \z80_|reg_file_|db_hi_as[5]~14_combout ; +wire \z80_|reg_file_|db_hi_as[5]~15_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~50_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~53_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~54_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~52_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~51_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~55_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[5]~14_combout ; +wire \z80_|reg_file_|b2v_latch_de_hi|latch[5]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~49_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~56_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~57_combout ; +wire \z80_|alu_|db[5]~23_combout ; wire \z80_|alu_|db[5]~24_combout ; -wire \z80_|alu_|db[5]~25_combout ; wire \z80_|sw1_|db_down[5]~0_combout ; wire \z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout ; wire \z80_|alu_flags_|flags_yf~q ; wire \z80_|alu_control_|db[5]~13_combout ; wire \z80_|alu_control_|db[5]~14_combout ; wire \z80_|alu_control_|db[5]~15_combout ; -wire \D[0]~107_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ; wire \ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ; wire \ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout ; wire \rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ; wire \rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout ; wire \Mux2~0_combout ; wire \Mux2~1_combout ; -wire \D[5]~110_combout ; -wire \D[5]~85_combout ; -wire \D[5]~99_combout ; +wire \D[5]~87_combout ; +wire \D[5]~68_combout ; +wire \D[5]~77_combout ; wire \z80_|bus_control_|db[5]~14_combout ; wire \z80_|bus_control_|db[5]~15_combout ; -wire \z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout ; -wire \z80_|decode_state_|DFFE_inst4~q ; -wire \z80_|decode_state_|use_ixiy~combout ; -wire \z80_|execute_|ctl_mRead~23_combout ; -wire \z80_|execute_|fMRead~34_combout ; -wire \z80_|execute_|fMRead~31_combout ; -wire \z80_|execute_|fMRead~29_combout ; -wire \z80_|execute_|fMRead~30_combout ; -wire \z80_|execute_|fMRead~28_combout ; -wire \z80_|execute_|fMRead~32_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~42_combout ; -wire \z80_|execute_|fMRead~14_combout ; -wire \z80_|execute_|fMRead~10_combout ; -wire \z80_|execute_|fMRead~9_combout ; -wire \z80_|execute_|fMRead~11_combout ; -wire \z80_|execute_|fMRead~12_combout ; -wire \z80_|execute_|fMRead~13_combout ; -wire \z80_|execute_|fMRead~15_combout ; -wire \z80_|execute_|fMRead~20_combout ; -wire \z80_|execute_|pc_inc_hold~48_combout ; -wire \z80_|execute_|fMRead~22_combout ; -wire \z80_|execute_|fMRead~21_combout ; -wire \z80_|execute_|fMRead~23_combout ; -wire \z80_|execute_|fMRead~26_combout ; -wire \z80_|execute_|fMRead~25_combout ; -wire \z80_|execute_|fMRead~27_combout ; -wire \z80_|execute_|fMRead~33_combout ; -wire \z80_|execute_|fMRead~35_combout ; -wire \z80_|pin_control_|bus_db_pin_re~combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ; -wire \Selector1~0_combout ; -wire \Selector1~1_combout ; -wire \D[1]~103_combout ; -wire \PS2_DAT~input_o ; -wire \reset~clkctrl_outclk ; -wire \ula_|ps2_keyboard_|bit_count~0_combout ; -wire \PS2_CLK~input_o ; -wire \ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ; -wire \ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ; -wire \ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ; -wire \ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ; -wire \ula_|ps2_keyboard_|Equal0~0_combout ; -wire \ula_|ps2_keyboard_|clk_filter[3]~feeder_combout ; -wire \ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ; -wire \ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ; -wire \ula_|ps2_keyboard_|Equal0~1_combout ; -wire \ula_|ps2_keyboard_|clk_filter[0]~0_combout ; -wire \ula_|ps2_keyboard_|ps2_clk_in~0_combout ; -wire \ula_|ps2_keyboard_|ps2_clk_in~q ; -wire \ula_|ps2_keyboard_|clk_edge~0_combout ; -wire \ula_|ps2_keyboard_|clk_edge~q ; -wire \ula_|ps2_keyboard_|bit_count~1_combout ; -wire \ula_|ps2_keyboard_|bit_count~3_combout ; -wire \ula_|ps2_keyboard_|bit_count~2_combout ; -wire \ula_|ps2_keyboard_|always1~0_combout ; -wire \ula_|ps2_keyboard_|LessThan0~0_combout ; -wire \ula_|ps2_keyboard_|shiftreg[0]~0_combout ; -wire \ula_|zx_keyboard_|Equal0~0_combout ; -wire \ula_|zx_keyboard_|Equal0~1_combout ; -wire \ula_|zx_keyboard_|extended~0_combout ; -wire \ula_|ps2_keyboard_|WideXor0~1_combout ; -wire \ula_|ps2_keyboard_|WideXor0~0_combout ; -wire \ula_|ps2_keyboard_|WideXor0~2_combout ; -wire \ula_|ps2_keyboard_|scan_code_ready~0_combout ; -wire \ula_|ps2_keyboard_|scan_code_ready~q ; -wire \ula_|zx_keyboard_|extended~q ; -wire \ula_|zx_keyboard_|keys[0][0]~15_combout ; -wire \ula_|zx_keyboard_|keys[5][1]~36_combout ; -wire \ula_|zx_keyboard_|keys[5][1]~37_combout ; -wire \ula_|zx_keyboard_|shifted~0_combout ; -wire \ula_|zx_keyboard_|released~0_combout ; -wire \ula_|zx_keyboard_|released~q ; -wire \ula_|zx_keyboard_|WideOr17~0_combout ; -wire \ula_|zx_keyboard_|shifted~2_combout ; -wire \ula_|zx_keyboard_|shifted~3_combout ; -wire \ula_|zx_keyboard_|shifted~q ; -wire \ula_|zx_keyboard_|keys[5][1]~35_combout ; -wire \ula_|zx_keyboard_|keys[5][1]~38_combout ; -wire \ula_|zx_keyboard_|keys[5][1]~39_combout ; -wire \ula_|zx_keyboard_|keys[5][1]~q ; -wire \ula_|zx_keyboard_|keys[4][1]~31_combout ; -wire \ula_|zx_keyboard_|keys[7][1]~23_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~32_combout ; -wire \ula_|zx_keyboard_|keys[5][2]~33_combout ; -wire \ula_|zx_keyboard_|keys[4][1]~34_combout ; -wire \ula_|zx_keyboard_|keys[4][1]~q ; -wire \D[1]~30_combout ; -wire \ula_|zx_keyboard_|keys[5][4]~24_combout ; -wire \ula_|zx_keyboard_|keys[3][1]~28_combout ; -wire \ula_|zx_keyboard_|keys[3][1]~29_combout ; -wire \ula_|zx_keyboard_|keys[3][1]~30_combout ; -wire \ula_|zx_keyboard_|keys[3][1]~q ; -wire \ula_|zx_keyboard_|keys[1][4]~25_combout ; -wire \ula_|zx_keyboard_|keys[2][1]~26_combout ; -wire \ula_|zx_keyboard_|keys[2][1]~27_combout ; -wire \ula_|zx_keyboard_|keys[2][1]~q ; -wire \ula_|zx_keyboard_|key_row~0_combout ; -wire \ula_|zx_keyboard_|keys[0][1]~14_combout ; -wire \ula_|zx_keyboard_|keys[0][1]~16_combout ; -wire \ula_|zx_keyboard_|keys[0][1]~17_combout ; -wire \ula_|zx_keyboard_|keys[0][1]~18_combout ; -wire \ula_|zx_keyboard_|keys[0][1]~q ; -wire \ula_|zx_keyboard_|keys[7][4]~19_combout ; -wire \ula_|zx_keyboard_|keys[6][4]~20_combout ; -wire \ula_|zx_keyboard_|keys[1][1]~21_combout ; -wire \ula_|zx_keyboard_|keys[1][1]~22_combout ; -wire \ula_|zx_keyboard_|keys[1][1]~q ; -wire \D[1]~28_combout ; -wire \D[1]~29_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~41_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~42_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~43_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~40_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~44_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~q ; -wire \ula_|zx_keyboard_|keys[7][1]~45_combout ; -wire \ula_|zx_keyboard_|WideOr16~5_combout ; -wire \ula_|zx_keyboard_|WideOr16~2_combout ; -wire \ula_|zx_keyboard_|WideOr16~4_combout ; -wire \ula_|zx_keyboard_|WideOr16~7_combout ; -wire \ula_|zx_keyboard_|WideOr16~6_combout ; -wire \ula_|zx_keyboard_|keys[7][1]~46_combout ; -wire \ula_|zx_keyboard_|keys[7][1]~q ; -wire \D[1]~31_combout ; -wire \D[1]~32_combout ; -wire \D[1]~33_combout ; -wire \D[1]~34_combout ; -wire \z80_|bus_control_|db[1]~10_combout ; -wire \z80_|bus_control_|db[1]~11_combout ; -wire \z80_|ir_|opcode[1]~feeder_combout ; -wire \z80_|pla_decode_|Equal40~0_combout ; -wire \z80_|pla_decode_|Equal21~1_combout ; -wire \z80_|execute_|ctl_alu_op_low~26_combout ; -wire \z80_|execute_|ctl_alu_op_low~28_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~3_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~2_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~21_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ; -wire \z80_|execute_|ctl_alu_op_low~32_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~19_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf2~q ; -wire \z80_|execute_|ctl_flags_use_cf2~10_combout ; -wire \z80_|execute_|ctl_flags_use_cf2~11_combout ; -wire \z80_|execute_|ctl_flags_use_cf2~8_combout ; -wire \z80_|execute_|ctl_flags_use_cf2~9_combout ; -wire \z80_|execute_|ctl_flags_use_cf2~12_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~20_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~10_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~8_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~5_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~6_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~7_combout ; -wire \z80_|execute_|ctl_flags_cf_set~0_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~4_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~9_combout ; -wire \z80_|alu_flags_|flags_cf~combout ; -wire \z80_|alu_control_|db[0]~8_combout ; -wire \z80_|sw2_|db_up[0]~0_combout ; -wire \z80_|alu_control_|db[0]~9_combout ; -wire \z80_|alu_control_|db[0]~12_combout ; -wire \ula_|zx_keyboard_|keys[5][0]~67_combout ; -wire \ula_|zx_keyboard_|keys[5][0]~81_combout ; -wire \ula_|zx_keyboard_|keys[5][0]~82_combout ; -wire \ula_|zx_keyboard_|keys[5][0]~83_combout ; -wire \ula_|zx_keyboard_|keys[5][0]~q ; -wire \ula_|zx_keyboard_|keys[4][0]~84_combout ; -wire \ula_|zx_keyboard_|keys[4][0]~85_combout ; -wire \ula_|zx_keyboard_|keys[4][0]~86_combout ; -wire \ula_|zx_keyboard_|keys[4][0]~q ; -wire \D[0]~49_combout ; -wire \ula_|zx_keyboard_|WideOr4~0_combout ; -wire \ula_|zx_keyboard_|keys~76_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~73_combout ; -wire \ula_|zx_keyboard_|keys[6][4]~47_combout ; -wire \ula_|zx_keyboard_|WideOr0~0_combout ; -wire \ula_|zx_keyboard_|keys~74_combout ; -wire \ula_|zx_keyboard_|keys[0][0]~75_combout ; -wire \ula_|zx_keyboard_|keys[0][0]~77_combout ; -wire \ula_|zx_keyboard_|keys[0][0]~q ; -wire \ula_|zx_keyboard_|keys[1][0]~71_combout ; -wire \ula_|zx_keyboard_|keys[1][0]~72_combout ; -wire \ula_|zx_keyboard_|keys[1][0]~q ; -wire \D[0]~47_combout ; -wire \ula_|zx_keyboard_|keys[2][0]~80_combout ; -wire \ula_|zx_keyboard_|keys[2][0]~q ; -wire \ula_|zx_keyboard_|keys[3][0]~78_combout ; -wire \ula_|zx_keyboard_|keys[3][0]~79_combout ; -wire \ula_|zx_keyboard_|keys[3][0]~q ; -wire \ula_|zx_keyboard_|key_row~1_combout ; -wire \D[0]~48_combout ; -wire \ula_|zx_keyboard_|shifted~1_combout ; -wire \ula_|zx_keyboard_|keys[6][0]~90_combout ; -wire \ula_|zx_keyboard_|keys[6][0]~91_combout ; -wire \ula_|zx_keyboard_|keys[6][0]~92_combout ; -wire \ula_|zx_keyboard_|keys[6][0]~q ; -wire \ula_|zx_keyboard_|keys[5][4]~63_combout ; -wire \ula_|zx_keyboard_|WideOr16~3_combout ; -wire \ula_|zx_keyboard_|keys[7][0]~87_combout ; -wire \ula_|zx_keyboard_|keys[7][0]~132_combout ; -wire \ula_|zx_keyboard_|keys[7][0]~88_combout ; -wire \ula_|zx_keyboard_|keys[7][0]~89_combout ; -wire \ula_|zx_keyboard_|keys[7][0]~q ; -wire \D[0]~50_combout ; -wire \D[0]~51_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ; -wire \D[0]~55_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ; -wire \D[0]~56_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ; -wire \D[0]~52_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ; -wire \D[0]~53_combout ; -wire \D[0]~54_combout ; -wire \D[0]~106_combout ; -wire \D[0]~57_combout ; -wire \D[0]~58_combout ; -wire \z80_|bus_control_|db[0]~16_combout ; -wire \z80_|bus_control_|db[0]~17_combout ; -wire \z80_|pla_decode_|Equal63~0_combout ; -wire \z80_|execute_|ctl_flags_cf2_sel_daa~combout ; -wire \z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ; -wire \z80_|alu_control_|db[6]~10_combout ; -wire \z80_|alu_control_|db[6]~11_combout ; -wire \z80_|alu_control_|db[4]~30_combout ; -wire \z80_|alu_control_|db[4]~31_combout ; -wire \z80_|alu_control_|db[4]~32_combout ; -wire \ula_|zx_keyboard_|keys[2][4]~119_combout ; -wire \ula_|zx_keyboard_|keys[2][4]~120_combout ; -wire \ula_|zx_keyboard_|keys[2][4]~95_combout ; -wire \ula_|zx_keyboard_|keys[2][4]~121_combout ; -wire \ula_|zx_keyboard_|keys[2][4]~q ; -wire \ula_|zx_keyboard_|keys[3][4]~117_combout ; -wire \ula_|zx_keyboard_|keys[3][4]~136_combout ; -wire \ula_|zx_keyboard_|keys[3][4]~130_combout ; -wire \ula_|zx_keyboard_|keys[3][4]~118_combout ; -wire \ula_|zx_keyboard_|keys[3][4]~q ; -wire \D[4]~78_combout ; -wire \ula_|zx_keyboard_|keys[6][4]~126_combout ; -wire \ula_|zx_keyboard_|keys[5][4]~128_combout ; -wire \ula_|zx_keyboard_|keys[5][4]~129_combout ; -wire \ula_|zx_keyboard_|keys[5][4]~q ; -wire \ula_|zx_keyboard_|keys[6][4]~127_combout ; -wire \ula_|zx_keyboard_|keys[6][4]~q ; -wire \ula_|zx_keyboard_|Equal0~2_combout ; -wire \ula_|zx_keyboard_|keys[7][4]~51_combout ; -wire \ula_|zx_keyboard_|keys[7][4]~125_combout ; -wire \ula_|zx_keyboard_|keys[7][4]~q ; -wire \D[4]~79_combout ; -wire \ula_|zx_keyboard_|keys[4][4]~122_combout ; -wire \ula_|zx_keyboard_|keys[4][4]~123_combout ; -wire \ula_|zx_keyboard_|keys[4][4]~124_combout ; -wire \ula_|zx_keyboard_|keys[4][4]~q ; -wire \ula_|zx_keyboard_|key_row~3_combout ; -wire \D[4]~80_combout ; -wire \ula_|zx_keyboard_|keys[0][4]~111_combout ; -wire \ula_|zx_keyboard_|keys[0][4]~97_combout ; -wire \ula_|zx_keyboard_|keys[0][4]~116_combout ; -wire \ula_|zx_keyboard_|keys[0][4]~q ; -wire \ula_|zx_keyboard_|keys[1][4]~115_combout ; -wire \ula_|zx_keyboard_|keys[1][4]~q ; -wire \D[4]~77_combout ; -wire \D[4]~81_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout ; -wire \Selector4~0_combout ; -wire \Selector4~1_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2_combout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3_combout ; -wire \D[4]~109_combout ; -wire \D[4]~97_combout ; -wire \D[4]~98_combout ; -wire \z80_|bus_control_|db[4]~18_combout ; -wire \z80_|bus_control_|db[4]~19_combout ; -wire \z80_|pla_decode_|Equal21~0_combout ; -wire \z80_|execute_|ctl_mRead~5_combout ; -wire \z80_|execute_|fIOWrite~2_combout ; -wire \z80_|execute_|fIOWrite~3_combout ; -wire \z80_|execute_|fIOWrite~4_combout ; -wire \z80_|execute_|fIOWrite~5_combout ; -wire \z80_|execute_|ctl_mWrite~11_combout ; -wire \z80_|execute_|ctl_mWrite~12_combout ; -wire \z80_|execute_|ctl_mWrite~13_combout ; -wire \z80_|execute_|ctl_mWrite~14_combout ; -wire \z80_|execute_|ctl_mWrite~15_combout ; -wire \z80_|memory_ifc_|DFFE_mwr_ff1~q ; -wire \z80_|memory_ifc_|wait_mwr~feeder_combout ; -wire \z80_|memory_ifc_|wait_mwr~q ; -wire \z80_|memory_ifc_|mwr_wr~q ; -wire \z80_|memory_ifc_|nWR_out~0_combout ; -wire \D[5]~84_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout ; -wire \Mux0~0_combout ; -wire \Mux0~1_combout ; -wire \D[7]~112_combout ; -wire \D[7]~94_combout ; -wire \D[7]~102_combout ; -wire \z80_|bus_control_|db[7]~5_combout ; -wire \z80_|bus_control_|db[7]~7_combout ; -wire \z80_|pla_decode_|Equal77~0_combout ; -wire \z80_|execute_|ctl_mWrite~5_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ; -wire \z80_|execute_|ctl_bus_db_we~3_combout ; +wire \z80_|execute_|ctl_mRead~8_combout ; wire \z80_|execute_|ctl_bus_db_we~8_combout ; -wire \z80_|execute_|ctl_bus_db_we~2_combout ; wire \z80_|execute_|ctl_bus_db_we~4_combout ; wire \z80_|execute_|ctl_bus_db_we~6_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ; +wire \z80_|execute_|ctl_bus_db_we~3_combout ; +wire \z80_|execute_|ctl_bus_db_we~2_combout ; wire \z80_|execute_|ctl_bus_db_we~7_combout ; -wire \ula_|zx_keyboard_|keys[0][2]~50_combout ; -wire \ula_|zx_keyboard_|keys[0][2]~52_combout ; -wire \ula_|zx_keyboard_|keys[0][2]~q ; -wire \ula_|zx_keyboard_|keys[3][3]~48_combout ; -wire \ula_|zx_keyboard_|keys[1][2]~49_combout ; -wire \ula_|zx_keyboard_|keys[1][2]~q ; -wire \D[2]~35_combout ; -wire \ula_|zx_keyboard_|keys[5][2]~57_combout ; -wire \ula_|zx_keyboard_|keys[5][2]~58_combout ; -wire \ula_|zx_keyboard_|keys[5][2]~q ; -wire \ula_|zx_keyboard_|keys[4][2]~59_combout ; -wire \ula_|zx_keyboard_|keys[4][2]~131_combout ; -wire \ula_|zx_keyboard_|keys[4][2]~60_combout ; -wire \ula_|zx_keyboard_|keys[4][2]~q ; -wire \D[2]~37_combout ; -wire \ula_|zx_keyboard_|keys[3][2]~53_combout ; -wire \ula_|zx_keyboard_|keys[2][2]~55_combout ; -wire \ula_|zx_keyboard_|keys[2][2]~56_combout ; -wire \ula_|zx_keyboard_|keys[2][2]~q ; -wire \ula_|zx_keyboard_|keys[3][2]~54_combout ; -wire \ula_|zx_keyboard_|keys[3][2]~q ; -wire \D[2]~36_combout ; -wire \ula_|zx_keyboard_|keys[6][2]~68_combout ; -wire \ula_|zx_keyboard_|keys[6][2]~69_combout ; -wire \ula_|zx_keyboard_|keys[6][2]~70_combout ; -wire \ula_|zx_keyboard_|keys[6][2]~q ; -wire \ula_|zx_keyboard_|keys[7][2]~61_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~62_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~64_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~65_combout ; -wire \ula_|zx_keyboard_|Selector13~0_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~66_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~q ; -wire \D[2]~38_combout ; -wire \D[2]~39_combout ; -wire \D[2]~104_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ; -wire \D[2]~43_combout ; -wire \D[2]~44_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout ; -wire \D[2]~40_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ; -wire \D[2]~41_combout ; -wire \D[2]~42_combout ; -wire \D[2]~105_combout ; -wire \D[2]~45_combout ; -wire \D[2]~46_combout ; -wire \z80_|bus_control_|db[2]~12_combout ; -wire \z80_|bus_control_|db[2]~13_combout ; -wire \z80_|pla_decode_|Equal3~1_combout ; +wire \ula_|zx_keyboard_|keys[5][0]~66_combout ; +wire \ula_|zx_keyboard_|keys[5][0]~80_combout ; +wire \ula_|zx_keyboard_|keys[5][0]~81_combout ; +wire \ula_|zx_keyboard_|keys[5][0]~82_combout ; +wire \ula_|zx_keyboard_|keys[5][0]~q ; +wire \ula_|zx_keyboard_|keys[4][0]~84_combout ; +wire \ula_|zx_keyboard_|keys[4][0]~83_combout ; +wire \ula_|zx_keyboard_|keys[4][0]~85_combout ; +wire \ula_|zx_keyboard_|keys[4][0]~q ; +wire \D[0]~42_combout ; +wire \ula_|zx_keyboard_|keys[1][0]~78_combout ; +wire \ula_|zx_keyboard_|keys[1][0]~79_combout ; +wire \ula_|zx_keyboard_|keys[1][0]~q ; +wire \ula_|zx_keyboard_|keys[3][0]~76_combout ; +wire \ula_|zx_keyboard_|keys[3][0]~q ; +wire \ula_|zx_keyboard_|keys[2][0]~77_combout ; +wire \ula_|zx_keyboard_|keys[2][0]~q ; +wire \D[0]~40_combout ; +wire \ula_|zx_keyboard_|WideOr0~0_combout ; +wire \ula_|zx_keyboard_|keys~71_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~70_combout ; +wire \ula_|zx_keyboard_|keys[0][0]~72_combout ; +wire \ula_|zx_keyboard_|WideOr4~0_combout ; +wire \ula_|zx_keyboard_|keys~73_combout ; +wire \ula_|zx_keyboard_|keys[0][0]~74_combout ; +wire \ula_|zx_keyboard_|keys[0][0]~q ; +wire \ula_|zx_keyboard_|key_row~2_combout ; +wire \D[0]~41_combout ; +wire \ula_|zx_keyboard_|keys[6][0]~89_combout ; +wire \ula_|zx_keyboard_|keys[6][0]~90_combout ; +wire \ula_|zx_keyboard_|keys[6][0]~91_combout ; +wire \ula_|zx_keyboard_|keys[6][0]~q ; +wire \ula_|zx_keyboard_|keys[7][0]~131_combout ; +wire \ula_|zx_keyboard_|WideOr16~3_combout ; +wire \ula_|zx_keyboard_|keys[7][0]~86_combout ; +wire \ula_|zx_keyboard_|keys[7][0]~87_combout ; +wire \ula_|zx_keyboard_|keys[7][0]~88_combout ; +wire \ula_|zx_keyboard_|keys[7][0]~q ; +wire \D[0]~43_combout ; +wire \D[0]~44_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4_combout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~5_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ; +wire \Selector2~0_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ; +wire \Selector2~1_combout ; +wire \D[0]~83_combout ; +wire \D[0]~45_combout ; +wire \D[0]~46_combout ; +wire \z80_|bus_control_|db[0]~16_combout ; +wire \z80_|bus_control_|db[0]~17_combout ; +wire \z80_|pla_decode_|Equal3~2_combout ; wire \z80_|pla_decode_|Equal43~0_combout ; wire \z80_|interrupts_|test1~2_combout ; wire \z80_|interrupts_|test1~3_combout ; @@ -2326,154 +2284,184 @@ wire \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ; wire \z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout ; wire \z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ; wire \z80_|clk_delay_|hold_clk_iorq~combout ; -wire \z80_|sequencer_|DFFE_T1_ff~q ; -wire \z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ; -wire \z80_|sequencer_|DFFE_T2_ff~q ; -wire \z80_|resets_|x3~combout ; -wire \z80_|resets_|SYNTHESIZED_WIRE_12~q ; -wire \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ; -wire \z80_|sequencer_|DFFE_M1_ff~q ; -wire \z80_|sequencer_|DFFE_M2_ff~0_combout ; -wire \z80_|sequencer_|DFFE_M2_ff~q ; -wire \z80_|execute_|ctl_mWrite~3_combout ; -wire \z80_|execute_|nextM~11_combout ; +wire \z80_|sequencer_|DFFE_T4_ff~q ; +wire \z80_|execute_|ctl_eval_cond~0_combout ; +wire \z80_|execute_|ctl_mRead~27_combout ; +wire \z80_|execute_|ctl_mRead~26_combout ; +wire \z80_|execute_|ctl_mRead~28_combout ; +wire \z80_|execute_|nextM~6_combout ; +wire \z80_|execute_|nextM~7_combout ; wire \z80_|execute_|nextM~8_combout ; wire \z80_|execute_|nextM~9_combout ; wire \z80_|execute_|nextM~10_combout ; wire \z80_|execute_|nextM~12_combout ; wire \z80_|execute_|nextM~15_combout ; -wire \z80_|execute_|nextM~6_combout ; -wire \z80_|execute_|nextM~7_combout ; wire \z80_|execute_|nextM~13_combout ; -wire \z80_|execute_|setM1~39_combout ; +wire \z80_|execute_|setM1~41_combout ; wire \z80_|execute_|nextM~5_combout ; wire \z80_|execute_|nextM~14_combout ; -wire \z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ; -wire \z80_|sequencer_|DFFE_T4_ff~q ; -wire \z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ; -wire \z80_|sequencer_|DFFE_T5_ff~q ; -wire \z80_|sequencer_|SYNTHESIZED_WIRE_17~combout ; -wire \z80_|sequencer_|T6~q ; -wire \z80_|execute_|setM1~13_combout ; -wire \z80_|pla_decode_|Equal77~1_combout ; -wire \z80_|execute_|setM1~12_combout ; -wire \z80_|execute_|setM1~14_combout ; -wire \z80_|execute_|setM1~41_combout ; -wire \z80_|execute_|setM1~42_combout ; -wire \z80_|execute_|setM1~43_combout ; -wire \z80_|execute_|setM1~44_combout ; -wire \z80_|execute_|setM1~50_combout ; -wire \z80_|execute_|setM1~51_combout ; -wire \z80_|execute_|setM1~6_combout ; -wire \z80_|execute_|setM1~7_combout ; -wire \z80_|execute_|setM1~8_combout ; -wire \z80_|execute_|setM1~9_combout ; -wire \z80_|execute_|setM1~10_combout ; -wire \z80_|execute_|setM1~11_combout ; -wire \z80_|execute_|setM1~17_combout ; -wire \z80_|execute_|setM1~31_combout ; -wire \z80_|execute_|setM1~28_combout ; -wire \z80_|execute_|setM1~30_combout ; -wire \z80_|execute_|setM1~32_combout ; -wire \z80_|execute_|setM1~33_combout ; -wire \z80_|execute_|setM1~25_combout ; -wire \z80_|execute_|setM1~26_combout ; -wire \z80_|execute_|setM1~24_combout ; -wire \z80_|execute_|setM1~27_combout ; -wire \z80_|execute_|setM1~22_combout ; -wire \z80_|execute_|setM1~21_combout ; -wire \z80_|execute_|setM1~53_combout ; -wire \z80_|execute_|setM1~23_combout ; -wire \z80_|execute_|setM1~18_combout ; -wire \z80_|execute_|setM1~19_combout ; -wire \z80_|execute_|setM1~20_combout ; -wire \z80_|execute_|setM1~34_combout ; -wire \z80_|execute_|setM1~52_combout ; +wire \z80_|sequencer_|ena_M~combout ; +wire \z80_|sequencer_|DFFE_T1_ff~q ; +wire \z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ; +wire \z80_|sequencer_|DFFE_T2_ff~q ; wire \z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ; wire \z80_|sequencer_|DFFE_T3_ff~q ; wire \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ; -wire \z80_|decode_state_|in_halt~0_combout ; -wire \z80_|decode_state_|in_halt~1_combout ; -wire \z80_|decode_state_|in_halt~q ; +wire \z80_|execute_|ctl_66_oe~2_combout ; +wire \z80_|interrupts_|im1~q ; +wire \z80_|execute_|ctl_bus_ff_oe~0_combout ; +wire \z80_|execute_|ctl_bus_ff_oe~1_combout ; +wire \z80_|execute_|ctl_bus_zero_oe~0_combout ; +wire \z80_|bus_control_|db[0]~4_combout ; +wire \z80_|bus_control_|db[6]~8_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ; +wire \Selector6~0_combout ; +wire \Selector6~1_combout ; +wire \D[6]~88_combout ; +wire \raw_loader_in~input_o ; +wire \D[6]~69_combout ; +wire \D[6]~78_combout ; +wire \D[6]~79_combout ; +wire \z80_|bus_control_|db[6]~9_combout ; +wire \z80_|execute_|ctl_ir_we~10_combout ; +wire \z80_|execute_|ctl_bus_db_oe~0_combout ; +wire \z80_|execute_|ctl_bus_db_oe~4_combout ; wire \z80_|execute_|ctl_bus_db_oe~2_combout ; wire \z80_|execute_|ctl_bus_db_oe~5_combout ; wire \z80_|execute_|ctl_bus_db_oe~6_combout ; -wire \z80_|execute_|ctl_bus_db_oe~4_combout ; wire \z80_|execute_|ctl_bus_db_oe~combout ; wire \z80_|bus_control_|db[0]~6_combout ; -wire \ula_|zx_keyboard_|keys[1][3]~93_combout ; -wire \ula_|zx_keyboard_|keys[1][3]~94_combout ; -wire \ula_|zx_keyboard_|keys[1][3]~q ; -wire \ula_|zx_keyboard_|keys[0][3]~96_combout ; -wire \ula_|zx_keyboard_|keys[0][3]~98_combout ; -wire \ula_|zx_keyboard_|keys[0][3]~q ; -wire \D[3]~65_combout ; -wire \ula_|zx_keyboard_|keys[3][3]~99_combout ; -wire \ula_|zx_keyboard_|keys[3][3]~100_combout ; -wire \ula_|zx_keyboard_|keys[3][3]~q ; -wire \ula_|zx_keyboard_|keys[2][3]~101_combout ; -wire \ula_|zx_keyboard_|keys[2][3]~102_combout ; -wire \ula_|zx_keyboard_|keys[2][3]~133_combout ; -wire \ula_|zx_keyboard_|keys[2][3]~103_combout ; -wire \ula_|zx_keyboard_|keys[2][3]~q ; -wire \D[3]~66_combout ; -wire \ula_|zx_keyboard_|keys[5][3]~104_combout ; -wire \ula_|zx_keyboard_|keys[5][3]~105_combout ; -wire \ula_|zx_keyboard_|keys[5][3]~q ; -wire \ula_|zx_keyboard_|keys[4][3]~106_combout ; -wire \ula_|zx_keyboard_|Selector5~1_combout ; -wire \ula_|zx_keyboard_|Selector5~0_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~134_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~107_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~135_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~108_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~q ; -wire \D[3]~67_combout ; -wire \ula_|zx_keyboard_|keys[7][3]~112_combout ; -wire \ula_|zx_keyboard_|keys[7][3]~113_combout ; -wire \ula_|zx_keyboard_|keys[7][3]~114_combout ; -wire \ula_|zx_keyboard_|keys[7][3]~q ; -wire \ula_|zx_keyboard_|keys[6][3]~109_combout ; -wire \ula_|zx_keyboard_|keys[6][3]~110_combout ; -wire \ula_|zx_keyboard_|keys[6][3]~137_combout ; -wire \ula_|zx_keyboard_|keys[6][3]~138_combout ; -wire \ula_|zx_keyboard_|keys[6][3]~q ; -wire \ula_|zx_keyboard_|key_row~2_combout ; -wire \D[3]~68_combout ; -wire \D[3]~69_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ; -wire \D[3]~73_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ; -wire \D[3]~74_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ; -wire \D[3]~70_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ; -wire \D[3]~71_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ; -wire \D[3]~72_combout ; -wire \D[3]~108_combout ; -wire \D[3]~95_combout ; -wire \D[3]~96_combout ; -wire \z80_|bus_control_|db[3]~20_combout ; -wire \z80_|bus_control_|db[3]~21_combout ; -wire \z80_|execute_|ctl_mWrite~4_combout ; -wire \z80_|execute_|ctl_apin_mux~2_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~61_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~63_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~64_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~65_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~q ; +wire \ula_|zx_keyboard_|keys[6][2]~67_combout ; +wire \ula_|zx_keyboard_|keys[6][2]~68_combout ; +wire \ula_|zx_keyboard_|keys[6][2]~69_combout ; +wire \ula_|zx_keyboard_|keys[6][2]~q ; +wire \D[2]~36_combout ; +wire \ula_|zx_keyboard_|keys[4][2]~58_combout ; +wire \ula_|zx_keyboard_|keys[4][2]~130_combout ; +wire \ula_|zx_keyboard_|keys[4][2]~59_combout ; +wire \ula_|zx_keyboard_|keys[4][2]~q ; +wire \ula_|zx_keyboard_|keys[5][2]~56_combout ; +wire \ula_|zx_keyboard_|keys[5][2]~57_combout ; +wire \ula_|zx_keyboard_|keys[5][2]~q ; +wire \D[2]~35_combout ; +wire \ula_|zx_keyboard_|keys[0][2]~54_combout ; +wire \ula_|zx_keyboard_|keys[0][2]~55_combout ; +wire \ula_|zx_keyboard_|keys[0][2]~q ; +wire \ula_|zx_keyboard_|keys[3][2]~50_combout ; +wire \ula_|zx_keyboard_|keys[3][2]~51_combout ; +wire \ula_|zx_keyboard_|keys[3][2]~q ; +wire \ula_|zx_keyboard_|keys[2][2]~52_combout ; +wire \ula_|zx_keyboard_|keys[2][2]~53_combout ; +wire \ula_|zx_keyboard_|keys[2][2]~q ; +wire \D[2]~33_combout ; +wire \ula_|zx_keyboard_|keys[1][2]~47_combout ; +wire \ula_|zx_keyboard_|keys[1][2]~48_combout ; +wire \ula_|zx_keyboard_|keys[1][2]~q ; +wire \ula_|zx_keyboard_|key_row~1_combout ; +wire \D[2]~34_combout ; +wire \D[2]~37_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~3_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ; +wire \Selector0~0_combout ; +wire \Selector0~1_combout ; +wire \D[2]~82_combout ; +wire \D[2]~38_combout ; +wire \D[2]~39_combout ; +wire \z80_|bus_control_|db[2]~12_combout ; +wire \z80_|bus_control_|db[2]~13_combout ; +wire \z80_|pla_decode_|Equal1~4_combout ; +wire \z80_|execute_|ctl_alu_op_low~26_combout ; +wire \z80_|execute_|ctl_alu_op_low~45_combout ; +wire \z80_|execute_|setM1~17_combout ; +wire \z80_|execute_|setM1~18_combout ; +wire \z80_|execute_|setM1~11_combout ; +wire \z80_|execute_|setM1~10_combout ; +wire \z80_|execute_|setM1~12_combout ; +wire \z80_|execute_|setM1~8_combout ; +wire \z80_|execute_|setM1~9_combout ; +wire \z80_|execute_|setM1~13_combout ; +wire \z80_|execute_|setM1~15_combout ; +wire \z80_|execute_|setM1~14_combout ; +wire \z80_|execute_|setM1~16_combout ; +wire \z80_|execute_|setM1~19_combout ; +wire \z80_|execute_|setM1~23_combout ; +wire \z80_|execute_|setM1~22_combout ; +wire \z80_|execute_|setM1~56_combout ; +wire \z80_|execute_|setM1~24_combout ; +wire \z80_|execute_|setM1~25_combout ; +wire \z80_|execute_|setM1~26_combout ; +wire \z80_|execute_|setM1~27_combout ; +wire \z80_|execute_|setM1~28_combout ; +wire \z80_|execute_|setM1~55_combout ; +wire \z80_|execute_|setM1~29_combout ; +wire \z80_|execute_|setM1~31_combout ; +wire \z80_|execute_|setM1~33_combout ; +wire \z80_|execute_|setM1~32_combout ; +wire \z80_|execute_|setM1~34_combout ; +wire \z80_|execute_|setM1~20_combout ; +wire \z80_|execute_|setM1~21_combout ; +wire \z80_|execute_|setM1~35_combout ; +wire \z80_|execute_|setM1~43_combout ; +wire \z80_|execute_|setM1~44_combout ; +wire \z80_|execute_|setM1~45_combout ; +wire \z80_|execute_|setM1~46_combout ; +wire \z80_|execute_|setM1~52_combout ; +wire \z80_|sequencer_|SYNTHESIZED_WIRE_17~combout ; +wire \z80_|sequencer_|T6~q ; +wire \z80_|execute_|setM1~53_combout ; +wire \z80_|execute_|setM1~54_combout ; +wire \z80_|sequencer_|DFFE_M1_ff~0_combout ; +wire \z80_|sequencer_|DFFE_M1_ff~q ; +wire \z80_|resets_|x1~0_combout ; +wire \z80_|fpga_reset~feeder_combout ; +wire \z80_|fpga_reset~q ; +wire \z80_|fpga_reset~clkctrl_outclk ; +wire \z80_|resets_|x1~q ; +wire \z80_|resets_|x3~combout ; +wire \z80_|resets_|SYNTHESIZED_WIRE_12~q ; +wire \z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ; +wire \z80_|resets_|SYNTHESIZED_WIRE_10~q ; +wire \z80_|resets_|SYNTHESIZED_WIRE_9~feeder_combout ; +wire \z80_|resets_|SYNTHESIZED_WIRE_9~q ; +wire \z80_|resets_|DFFE_intr_ff3~q ; +wire \z80_|resets_|clrpc_int~0_combout ; +wire \z80_|resets_|clrpc_int~q ; +wire \z80_|resets_|clrpc~0_combout ; wire \z80_|address_pins_|DFFE_apin_latch[0]~0_combout ; -wire \D[0]~59_combout ; -wire \D[0]~60_combout ; -wire \D[1]~61_combout ; -wire \D[1]~62_combout ; -wire \D[2]~63_combout ; -wire \D[2]~64_combout ; -wire \D[3]~75_combout ; -wire \D[3]~76_combout ; -wire \D[4]~82_combout ; -wire \D[4]~83_combout ; -wire \D[6]~92_combout ; -wire \D[6]~93_combout ; +wire \D[0]~47_combout ; +wire \D[0]~48_combout ; +wire \D[1]~49_combout ; +wire \D[1]~50_combout ; +wire \D[2]~51_combout ; +wire \D[2]~52_combout ; +wire \D[3]~58_combout ; +wire \D[3]~59_combout ; +wire \D[4]~65_combout ; +wire \D[4]~66_combout ; +wire \D[6]~70_combout ; +wire \D[6]~71_combout ; wire \z80_|nM1_int~3_combout ; wire \z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q ; wire \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder_combout ; @@ -2489,33 +2477,43 @@ wire \ula_|i2c_loader_|divider[1]~6 ; wire \ula_|i2c_loader_|divider[2]~7_combout ; wire \ula_|i2c_loader_|divider[2]~8 ; wire \ula_|i2c_loader_|divider[3]~9_combout ; +wire \ula_|i2c_loader_|WideAnd0~0_combout ; wire \ula_|i2c_loader_|divider[3]~10 ; wire \ula_|i2c_loader_|divider[4]~11_combout ; wire \ula_|i2c_loader_|divider[4]~12 ; wire \ula_|i2c_loader_|divider[5]~13_combout ; -wire \ula_|i2c_loader_|WideAnd0~0_combout ; wire \ula_|i2c_loader_|WideAnd0~combout ; wire \ula_|i2c_loader_|state.Idle~q ; wire \ula_|i2c_loader_|phase~0_combout ; wire \ula_|i2c_loader_|phase~1_combout ; wire \ula_|i2c_loader_|nbit~5_combout ; -wire \ula_|i2c_loader_|thisbyte[0]~8_combout ; +wire \ula_|i2c_loader_|state.Idle~0_combout ; wire \ula_|i2c_loader_|Mux42~0_combout ; +wire \ula_|i2c_loader_|nbit~6_combout ; +wire \ula_|i2c_loader_|state.Done~0_combout ; +wire \ula_|i2c_loader_|state.Ack~0_combout ; +wire \ula_|i2c_loader_|state.Ack~1_combout ; +wire \ula_|i2c_loader_|state.Ack~q ; +wire \ula_|i2c_loader_|nbit[0]~2_combout ; wire \ula_|i2c_loader_|nbyte~4_combout ; wire \ula_|i2c_loader_|thisbyte[0]~7_combout ; wire \I2C_SDAT~input_o ; wire \ula_|i2c_loader_|nbyte[0]~1_combout ; wire \ula_|i2c_loader_|nbyte[0]~2_combout ; wire \ula_|i2c_loader_|nbyte[0]~3_combout ; -wire \ula_|i2c_loader_|state.Stop~0_combout ; -wire \ula_|i2c_loader_|state.Stop~1_combout ; -wire \ula_|i2c_loader_|state.Stop~q ; -wire \ula_|i2c_loader_|state.Idle~0_combout ; +wire \ula_|i2c_loader_|nbit[0]~1_combout ; +wire \ula_|i2c_loader_|nbit[0]~3_combout ; +wire \ula_|i2c_loader_|nbit[0]~4_combout ; wire \ula_|i2c_loader_|nbit~0_combout ; -wire \ula_|i2c_loader_|state.Done~0_combout ; -wire \ula_|i2c_loader_|state.Ack~0_combout ; -wire \ula_|i2c_loader_|state.Ack~1_combout ; -wire \ula_|i2c_loader_|state.Ack~q ; +wire \ula_|i2c_loader_|state.Done~1_combout ; +wire \ula_|i2c_loader_|state~27_combout ; +wire \ula_|i2c_loader_|state~24_combout ; +wire \ula_|i2c_loader_|state~26_combout ; +wire \ula_|i2c_loader_|state.Data~0_combout ; +wire \ula_|i2c_loader_|state.Data~q ; +wire \ula_|i2c_loader_|state.Done~2_combout ; +wire \ula_|i2c_loader_|state.Pause~1_combout ; +wire \ula_|i2c_loader_|thisbyte[0]~8_combout ; wire \ula_|i2c_loader_|nbyte[1]~5_combout ; wire \ula_|i2c_loader_|thisbyte[0]~18_combout ; wire \ula_|i2c_loader_|thisbyte[0]~9 ; @@ -2525,28 +2523,18 @@ wire \ula_|i2c_loader_|thisbyte[2]~12_combout ; wire \ula_|i2c_loader_|thisbyte[2]~13 ; wire \ula_|i2c_loader_|thisbyte[3]~14_combout ; wire \ula_|i2c_loader_|Equal2~0_combout ; -wire \ula_|i2c_loader_|state.Pause~0_combout ; wire \ula_|i2c_loader_|thisbyte[3]~15 ; wire \ula_|i2c_loader_|thisbyte[4]~16_combout ; -wire \ula_|i2c_loader_|state.Pause~1_combout ; -wire \ula_|i2c_loader_|state.Done~2_combout ; +wire \ula_|i2c_loader_|Equal2~1_combout ; +wire \ula_|i2c_loader_|state.Pause~0_combout ; wire \ula_|i2c_loader_|state.Pause~2_combout ; -wire \ula_|i2c_loader_|state.Pause~3_combout ; wire \ula_|i2c_loader_|state.Pause~q ; wire \ula_|i2c_loader_|state~25_combout ; wire \ula_|i2c_loader_|state.Start~q ; wire \ula_|i2c_loader_|nbyte~0_combout ; -wire \ula_|i2c_loader_|nbit[0]~1_combout ; -wire \ula_|i2c_loader_|nbit[0]~2_combout ; -wire \ula_|i2c_loader_|nbit[0]~3_combout ; -wire \ula_|i2c_loader_|nbit[0]~4_combout ; -wire \ula_|i2c_loader_|nbit~6_combout ; -wire \ula_|i2c_loader_|state.Done~1_combout ; -wire \ula_|i2c_loader_|state~27_combout ; -wire \ula_|i2c_loader_|state~24_combout ; -wire \ula_|i2c_loader_|state~26_combout ; -wire \ula_|i2c_loader_|state.Data~0_combout ; -wire \ula_|i2c_loader_|state.Data~q ; +wire \ula_|i2c_loader_|state.Stop~0_combout ; +wire \ula_|i2c_loader_|state.Stop~1_combout ; +wire \ula_|i2c_loader_|state.Stop~q ; wire \ula_|i2c_loader_|scl_out~0_combout ; wire \ula_|i2c_loader_|scl_out~_Duplicate_1_q ; wire \ula_|i2c_loader_|scl_out~1_combout ; @@ -2556,26 +2544,25 @@ wire \ula_|i2c_loader_|sda_out~_Duplicate_1_q ; wire \ula_|i2c_loader_|shiftreg~4_combout ; wire \ula_|i2c_loader_|Mux35~0_combout ; wire \ula_|i2c_loader_|shiftreg~13_combout ; -wire \ula_|i2c_loader_|shiftreg~14_combout ; wire \ula_|i2c_loader_|shiftreg~15_combout ; -wire \ula_|i2c_loader_|shiftreg[0]~24_combout ; -wire \ula_|i2c_loader_|shiftreg[0]~6_combout ; -wire \ula_|i2c_loader_|shiftreg[0]~7_combout ; -wire \ula_|i2c_loader_|shiftreg[0]~8_combout ; -wire \ula_|i2c_loader_|shiftreg~21_combout ; -wire \ula_|i2c_loader_|shiftreg~22_combout ; -wire \ula_|i2c_loader_|shiftreg~23_combout ; -wire \ula_|i2c_loader_|shiftreg[6]~10_combout ; -wire \ula_|i2c_loader_|shiftreg[6]~11_combout ; -wire \ula_|i2c_loader_|shiftreg~18_combout ; -wire \ula_|i2c_loader_|shiftreg~19_combout ; -wire \ula_|i2c_loader_|shiftreg~20_combout ; wire \ula_|i2c_loader_|shiftreg~16_combout ; wire \ula_|i2c_loader_|shiftreg~17_combout ; -wire \ula_|i2c_loader_|shiftreg~26_combout ; +wire \ula_|i2c_loader_|shiftreg~18_combout ; +wire \ula_|i2c_loader_|shiftreg~20_combout ; +wire \ula_|i2c_loader_|shiftreg~21_combout ; +wire \ula_|i2c_loader_|shiftreg[0]~23_combout ; +wire \ula_|i2c_loader_|shiftreg[0]~6_combout ; +wire \ula_|i2c_loader_|shiftreg[0]~7_combout ; +wire \ula_|i2c_loader_|shiftreg~22_combout ; +wire \ula_|i2c_loader_|shiftreg[6]~9_combout ; +wire \ula_|i2c_loader_|shiftreg[6]~10_combout ; +wire \ula_|i2c_loader_|shiftreg~19_combout ; wire \ula_|i2c_loader_|shiftreg~25_combout ; wire \ula_|i2c_loader_|shiftreg~12_combout ; -wire \ula_|i2c_loader_|shiftreg~9_combout ; +wire \ula_|i2c_loader_|shiftreg~14_combout ; +wire \ula_|i2c_loader_|shiftreg~24_combout ; +wire \ula_|i2c_loader_|shiftreg~11_combout ; +wire \ula_|i2c_loader_|shiftreg~8_combout ; wire \ula_|i2c_loader_|shiftreg[7]~5_combout ; wire \ula_|i2c_loader_|sda_out~0_combout ; wire \ula_|i2c_loader_|sda_out~1_combout ; @@ -2616,12 +2603,12 @@ wire \ula_|i2s_intf_|Add0~18_combout ; wire \ula_|i2s_intf_|lrdivider[9]~3_combout ; wire \ula_|i2s_intf_|Equal0~0_combout ; wire \ula_|i2s_intf_|Equal0~2_combout ; -wire \ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder_combout ; wire \ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ; wire \ula_|i2s_intf_|lrclk_r~0_combout ; wire \ula_|i2s_intf_|lrclk_r~q ; wire \ula_|i2s_intf_|lrclk_r~_Duplicate_1_q ; wire \ula_|i2s_intf_|bitcount[0]~5_combout ; +wire \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder_combout ; wire \ula_|i2s_intf_|bclk_r~_Duplicate_1_q ; wire \ula_|i2s_intf_|bitcount[4]~15_combout ; wire \ula_|i2s_intf_|bitcount[0]~6 ; @@ -2630,9 +2617,11 @@ wire \ula_|i2s_intf_|bitcount[1]~8 ; wire \ula_|i2s_intf_|bitcount[2]~9_combout ; wire \ula_|i2s_intf_|bitcount[2]~10 ; wire \ula_|i2s_intf_|bitcount[3]~11_combout ; -wire \ula_|i2s_intf_|LessThan0~0_combout ; wire \ula_|i2s_intf_|bitcount[3]~12 ; wire \ula_|i2s_intf_|bitcount[4]~13_combout ; +wire \ula_|i2s_intf_|LessThan0~0_combout ; +wire \ula_|i2s_intf_|shiftreg[4]~1_combout ; +wire \ula_|i2s_intf_|Add2~18_combout ; wire \ula_|i2s_intf_|Add2~7_cout ; wire \ula_|i2s_intf_|Add2~8_combout ; wire \ula_|i2s_intf_|Add2~20_combout ; @@ -2646,13 +2635,10 @@ wire \ula_|i2s_intf_|Add2~13 ; wire \ula_|i2s_intf_|Add2~14_combout ; wire \ula_|i2s_intf_|Add2~16_combout ; wire \ula_|i2s_intf_|Equal1~0_combout ; -wire \ula_|i2s_intf_|shiftreg[4]~1_combout ; -wire \ula_|i2s_intf_|Add2~18_combout ; wire \ula_|i2s_intf_|Equal1~1_combout ; wire \ula_|i2s_intf_|bclk_r~0_combout ; wire \ula_|i2s_intf_|bclk_r~1_combout ; wire \ula_|i2s_intf_|bclk_r~q ; -wire \ula_|pcm_outl[13]~feeder_combout ; wire \ula_|always0~2_combout ; wire \ula_|always0~3_combout ; wire \ula_|i2s_intf_|shiftreg[0]~19_combout ; @@ -2671,33 +2657,30 @@ wire \ula_|i2s_intf_|shiftreg~10_combout ; wire \ula_|i2s_intf_|shiftreg~9_combout ; wire \ula_|i2s_intf_|shiftreg~8_combout ; wire \ula_|i2s_intf_|shiftreg~7_combout ; -wire \ula_|i2s_intf_|PCM_INR[14]~0_combout ; wire \ula_|i2s_intf_|PCM_INL[14]~0_combout ; +wire \ula_|i2s_intf_|PCM_INR[14]~0_combout ; wire \ula_|pcm_outr~0_combout ; wire \ula_|i2s_intf_|shiftreg~6_combout ; wire \ula_|i2s_intf_|shiftreg~5_combout ; wire \ula_|i2s_intf_|shiftreg~4_combout ; wire \ula_|i2s_intf_|shiftreg~3_combout ; wire \ula_|i2s_intf_|shiftreg~0_combout ; -wire \ula_|video_|LessThan2~0_combout ; +wire \ula_|border[1]~feeder_combout ; +wire \ula_|video_|LessThan4~0_combout ; +wire \ula_|video_|screen_en~0_combout ; wire \ula_|video_|LessThan6~0_combout ; +wire \ula_|video_|LessThan6~1_combout ; +wire \ula_|video_|screen_en~1_combout ; +wire \ula_|video_|LessThan2~0_combout ; wire \ula_|video_|LessThan2~1_combout ; wire \ula_|video_|LessThan3~0_combout ; wire \ula_|video_|LessThan0~0_combout ; wire \ula_|video_|disp_enable~0_combout ; wire \ula_|video_|disp_enable~1_combout ; -wire \ula_|video_|LessThan6~1_combout ; -wire \ula_|video_|LessThan4~0_combout ; -wire \ula_|video_|screen_en~0_combout ; -wire \ula_|video_|screen_en~1_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 ; -wire \ula_|video_|attr_prefetch[1]~feeder_combout ; -wire \ula_|video_|Decoder0~1_combout ; -wire \ula_|video_|Decoder0~0_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 ; -wire \ula_|video_|attr_prefetch[4]~feeder_combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 ; wire \ula_|video_|attr_prefetch[7]~feeder_combout ; +wire \ula_|video_|Decoder0~1_combout ; +wire \ula_|video_|Decoder0~0_combout ; wire \ula_|video_|frame[0]~12_combout ; wire \ula_|video_|frame[1]~4_combout ; wire \ula_|video_|frame[1]~5 ; @@ -2706,11 +2689,12 @@ wire \ula_|video_|frame[2]~7 ; wire \ula_|video_|frame[3]~8_combout ; wire \ula_|video_|frame[3]~9 ; wire \ula_|video_|frame[4]~10_combout ; +wire \ula_|video_|frame[4]~feeder_combout ; wire \ula_|video_|inverted~combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 ; wire \ula_|video_|bits_prefetch[6]~feeder_combout ; wire \ula_|video_|Decoder0~2_combout ; -wire \ula_|video_|bits[6]~feeder_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 ; wire \ula_|video_|bits_prefetch[4]~feeder_combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 ; wire \ula_|video_|bits_prefetch[5]~feeder_combout ; @@ -2723,6 +2707,7 @@ wire \ula_|video_|bits_prefetch[2]~feeder_combout ; wire \ula_|video_|bits[2]~feeder_combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 ; wire \ula_|video_|bits_prefetch[0]~feeder_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 ; wire \ula_|video_|bits_prefetch[1]~feeder_combout ; wire \ula_|video_|bits[1]~feeder_combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 ; @@ -2730,13 +2715,15 @@ wire \ula_|video_|bits_prefetch[3]~feeder_combout ; wire \ula_|video_|Mux0~2_combout ; wire \ula_|video_|Mux0~3_combout ; wire \ula_|video_|cindex[1]~0_combout ; +wire \ula_|video_|attr_prefetch[4]~feeder_combout ; +wire \ula_|video_|attr_prefetch[1]~feeder_combout ; wire \ula_|video_|cindex[1]~1_combout ; wire \ula_|video_|VGA_R[0]~0_combout ; wire \ula_|video_|attr_prefetch[6]~feeder_combout ; wire \ula_|video_|VGA_B[1]~0_combout ; wire \ula_|video_|VGA_R[1]~1_combout ; -wire \ula_|video_|attr_prefetch[2]~feeder_combout ; wire \ula_|video_|attr_prefetch[5]~feeder_combout ; +wire \ula_|video_|attr_prefetch[2]~feeder_combout ; wire \ula_|video_|cindex[2]~2_combout ; wire \ula_|video_|VGA_G[0]~0_combout ; wire \ula_|video_|VGA_G[1]~1_combout ; @@ -2761,42 +2748,24 @@ wire \z80_|memory_ifc_|nM1_out~combout ; wire \ula_|beep~0_combout ; wire \ula_|beep~q ; wire [0:0] \ram0|altsyncram_component|auto_generated|address_reg_a ; -wire [1:0] \ram1|altsyncram_component|auto_generated|address_reg_a ; wire [2:0] \ram1|altsyncram_component|auto_generated|decode3|w_anode244w ; -wire [2:0] \ram1|altsyncram_component|auto_generated|decode3|w_anode223w ; wire [2:0] \ula_|border ; wire [0:0] \ula_|clocks_|counter ; -wire [7:0] \ula_|i2c_loader_|shiftreg ; wire [1:0] \ula_|i2c_loader_|nbyte ; -wire [5:0] \ula_|i2c_loader_|divider ; -wire [17:0] \ula_|i2s_intf_|shiftreg ; wire [4:0] \ula_|i2s_intf_|bitcount ; -wire [15:0] \ula_|i2s_intf_|PCM_INR ; -wire [9:0] \ula_|video_|vga_vc ; wire [4:0] \ula_|video_|frame ; -wire [7:0] \ula_|video_|bits_prefetch ; wire [7:0] \ula_|video_|attr_prefetch ; -wire [7:0] \ula_|ps2_keyboard_|clk_filter ; -wire [7:0] \z80_|reg_file_|b2v_latch_af_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_bc2_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_bc_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_de2_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_de_lo|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_af_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_bc2_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_de2_hi|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_hl2_lo|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_hl_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_ir_lo|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_ix_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_iy_lo|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_pc_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_sp_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_wz_lo|latch ; -wire [3:0] \z80_|alu_|op2_low ; wire [3:0] \z80_|alu_|op1_low ; -wire [15:0] \z80_|address_latch_|Q ; -wire [15:0] \z80_|address_latch_|b2v_inst_inc_dec|address ; -wire [15:0] \z80_|address_pins_|DFFE_apin_latch ; -wire [7:0] \z80_|data_pins_|dout ; -wire [7:0] \z80_|ir_|opcode ; +wire [7:0] \z80_|reg_file_|b2v_latch_af2_hi|latch ; +wire [15:0] \z80_|address_latch_|abusz ; +wire [7:0] \z80_|data_pins_|SYNTHESIZED_WIRE_0 ; wire [0:0] \ram0|altsyncram_component|auto_generated|out_address_reg_a ; wire [1:0] \ram1|altsyncram_component|auto_generated|out_address_reg_a ; wire [2:0] \ram1|altsyncram_component|auto_generated|decode3|w_anode252w ; @@ -2815,13 +2784,11 @@ wire [7:0] \ula_|video_|bits ; wire [7:0] \ula_|video_|attr ; wire [8:0] \ula_|ps2_keyboard_|shiftreg ; wire [3:0] \ula_|ps2_keyboard_|bit_count ; -wire [7:0] \z80_|reg_file_|b2v_latch_af2_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_af_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_bc2_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_bc_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_de2_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_de_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_hl2_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_af_lo|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_bc2_lo|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_bc_lo|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_de2_lo|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_de_lo|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_hl_hi|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_ir_hi|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_ix_hi|latch ; @@ -2829,53 +2796,73 @@ wire [7:0] \z80_|reg_file_|b2v_latch_iy_hi|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_pc_hi|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_sp_hi|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_wz_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_wz_lo|latch ; wire [3:0] \z80_|alu_|result_lo ; wire [3:0] \z80_|alu_|op2_high ; wire [3:0] \z80_|alu_|op1_high ; wire [3:0] \z80_|alu_|b2v_op1_latch_mux_high|Q ; -wire [7:0] \z80_|reg_file_|b2v_latch_af2_hi|latch ; -wire [15:0] \z80_|address_latch_|abusz ; -wire [7:0] \z80_|data_pins_|SYNTHESIZED_WIRE_0 ; +wire [15:0] \z80_|address_latch_|Q ; +wire [15:0] \z80_|address_latch_|b2v_inst_inc_dec|address ; +wire [15:0] \z80_|address_pins_|DFFE_apin_latch ; +wire [7:0] \z80_|data_pins_|dout ; +wire [7:0] \z80_|ir_|opcode ; +wire [1:0] \ram1|altsyncram_component|auto_generated|address_reg_a ; +wire [2:0] \ram1|altsyncram_component|auto_generated|decode3|w_anode223w ; +wire [7:0] \ula_|i2c_loader_|shiftreg ; +wire [5:0] \ula_|i2c_loader_|divider ; +wire [17:0] \ula_|i2s_intf_|shiftreg ; +wire [15:0] \ula_|i2s_intf_|PCM_INR ; +wire [9:0] \ula_|video_|vga_vc ; +wire [7:0] \ula_|video_|bits_prefetch ; +wire [7:0] \ula_|ps2_keyboard_|clk_filter ; +wire [7:0] \z80_|reg_file_|b2v_latch_af2_lo|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_bc_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_de_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_hl2_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_ir_lo|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_iy_lo|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_sp_lo|latch ; +wire [3:0] \z80_|alu_|op2_low ; wire [4:0] \ula_|pll_|altpll_component|auto_generated|pll1_CLK_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a25_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ; -wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ; -wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; -wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; -wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; -wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a28_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ; @@ -2883,33 +2870,33 @@ wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_b wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a4_PORTBDATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ; -wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ; -wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a5_PORTBDATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a5_PORTBDATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ; -wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a31_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ; -wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ; -wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus ; assign \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk [0] = \ula_|pll_|altpll_component|auto_generated|pll1_CLK_bus [0]; assign \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk [1] = \ula_|pll_|altpll_component|auto_generated|pll1_CLK_bus [1]; @@ -2917,82 +2904,82 @@ assign \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk [2] = \ula_|pll_ assign \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk [3] = \ula_|pll_|altpll_component|auto_generated|pll1_CLK_bus [3]; assign \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk [4] = \ula_|pll_|altpll_component|auto_generated|pll1_CLK_bus [4]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus [0]; - assign \ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus [0]; + assign \ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0]; assign \ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a25_PORTADATAOUT_bus [0]; assign \rom|altsyncram_component|auto_generated|ram_block1a9~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a1~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [0]; + assign \ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a1~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus [0]; -assign \ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a10~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a10~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus [0]; -assign \ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a8~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus [0]; +assign \ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a8~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; -assign \ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus [0]; +assign \ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; - -assign \ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus [0]; - -assign \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus [0]; assign \ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus [0]; - assign \ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus [0]; assign \ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a28_PORTADATAOUT_bus [0]; @@ -3007,60 +2994,60 @@ assign \rom|altsyncram_component|auto_generated|ram_block1a4~portadataout = \ro assign \ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus [0]; - assign \ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus [0]; + assign \ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus [0]; assign \ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus [0]; assign \rom|altsyncram_component|auto_generated|ram_block1a13~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a5~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus [0]; + assign \ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a5_PORTBDATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a5~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus [0]; -assign \ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a14~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a6~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a14~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus [0]; - -assign \ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus [0]; - -assign \rom|altsyncram_component|auto_generated|ram_block1a6~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus [0]; assign \ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus [0]; - assign \ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus [0]; assign \ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a31_PORTADATAOUT_bus [0]; assign \rom|altsyncram_component|auto_generated|ram_block1a15~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus [0]; -assign \ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus [0]; - -assign \ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus [0]; - assign \rom|altsyncram_component|auto_generated|ram_block1a7~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus [0]; +assign \ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus [0]; + // Location: IOOBUF_X53_Y21_N23 cycloneive_io_obuf \GPIO_1[0]~output ( .i(\z80_|address_pins_|DFFE_apin_latch [0]), @@ -3271,8 +3258,8 @@ defparam \GPIO_1[15]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y11_N9 cycloneive_io_obuf \GPIO_1[16]~output ( - .i(\D[0]~60_combout ), - .oe(\D[0]~107_combout ), + .i(\D[0]~48_combout ), + .oe(\D[0]~84_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[16]), @@ -3284,8 +3271,8 @@ defparam \GPIO_1[16]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y12_N2 cycloneive_io_obuf \GPIO_1[17]~output ( - .i(\D[1]~62_combout ), - .oe(\D[0]~107_combout ), + .i(\D[1]~50_combout ), + .oe(\D[0]~84_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[17]), @@ -3297,8 +3284,8 @@ defparam \GPIO_1[17]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y8_N23 cycloneive_io_obuf \GPIO_1[18]~output ( - .i(\D[2]~64_combout ), - .oe(\D[0]~107_combout ), + .i(\D[2]~52_combout ), + .oe(\D[0]~84_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[18]), @@ -3310,8 +3297,8 @@ defparam \GPIO_1[18]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y11_N2 cycloneive_io_obuf \GPIO_1[19]~output ( - .i(\D[3]~76_combout ), - .oe(\D[0]~107_combout ), + .i(\D[3]~59_combout ), + .oe(\D[0]~84_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[19]), @@ -3323,8 +3310,8 @@ defparam \GPIO_1[19]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y6_N16 cycloneive_io_obuf \GPIO_1[20]~output ( - .i(\D[4]~83_combout ), - .oe(\D[0]~107_combout ), + .i(\D[4]~66_combout ), + .oe(\D[0]~84_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[20]), @@ -3336,8 +3323,8 @@ defparam \GPIO_1[20]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y7_N9 cycloneive_io_obuf \GPIO_1[21]~output ( - .i(\D[5]~85_combout ), - .oe(\D[0]~107_combout ), + .i(\D[5]~68_combout ), + .oe(\D[0]~84_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[21]), @@ -3349,8 +3336,8 @@ defparam \GPIO_1[21]~output .open_drain_output = "false"; // Location: IOOBUF_X49_Y0_N2 cycloneive_io_obuf \GPIO_1[22]~output ( - .i(\D[6]~93_combout ), - .oe(\D[0]~107_combout ), + .i(\D[6]~71_combout ), + .oe(\D[0]~84_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[22]), @@ -3362,8 +3349,8 @@ defparam \GPIO_1[22]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y9_N23 cycloneive_io_obuf \GPIO_1[23]~output ( - .i(\D[7]~94_combout ), - .oe(\D[0]~107_combout ), + .i(\D[7]~72_combout ), + .oe(\D[0]~84_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[23]), @@ -4024,7 +4011,7 @@ defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl .cl defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: LCCOMB_X25_Y33_N4 +// Location: LCCOMB_X25_Y33_N0 cycloneive_lcell_comb \ula_|clocks_|counter[0]~0 ( // Equation(s): // \ula_|clocks_|counter[0]~0_combout = !\ula_|clocks_|counter [0] @@ -4041,7 +4028,7 @@ defparam \ula_|clocks_|counter[0]~0 .lut_mask = 16'h0F0F; defparam \ula_|clocks_|counter[0]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X25_Y33_N5 +// Location: FF_X25_Y33_N1 dffeas \ula_|clocks_|counter[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), .d(\ula_|clocks_|counter[0]~0_combout ), @@ -4070,7 +4057,7 @@ defparam \SW[2]~input .bus_hold = "false"; defparam \SW[2]~input .simulate_z_as = "z"; // synopsys translate_on -// Location: LCCOMB_X25_Y33_N10 +// Location: LCCOMB_X25_Y33_N4 cycloneive_lcell_comb \ula_|clocks_|clk_cpu~0 ( // Equation(s): // \ula_|clocks_|clk_cpu~0_combout = \ula_|clocks_|clk_cpu~q $ (((\SW[2]~input_o ) # (!\ula_|clocks_|counter [0]))) @@ -4087,7 +4074,7 @@ defparam \ula_|clocks_|clk_cpu~0 .lut_mask = 16'h0FC3; defparam \ula_|clocks_|clk_cpu~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X25_Y33_N11 +// Location: FF_X25_Y33_N5 dffeas \ula_|clocks_|clk_cpu ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), .d(\ula_|clocks_|clk_cpu~0_combout ), @@ -4106,7 +4093,7 @@ defparam \ula_|clocks_|clk_cpu .is_wysiwyg = "true"; defparam \ula_|clocks_|clk_cpu .power_up = "low"; // synopsys translate_on -// Location: CLKCTRL_G14 +// Location: CLKCTRL_G12 cycloneive_clkctrl \ula_|clocks_|clk_cpu~clkctrl ( .ena(vcc), .inclk({vcc,vcc,vcc,\ula_|clocks_|clk_cpu~q }), @@ -4119,38 +4106,34 @@ defparam \ula_|clocks_|clk_cpu~clkctrl .clock_type = "global clock"; defparam \ula_|clocks_|clk_cpu~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: LCCOMB_X32_Y17_N20 -cycloneive_lcell_comb \z80_|sequencer_|DFFE_M1_ff~0 ( +// Location: LCCOMB_X26_Y13_N30 +cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_15 ( // Equation(s): -// \z80_|sequencer_|DFFE_M1_ff~0_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # (\z80_|execute_|nextM~14_combout ))) - - .dataa(\z80_|execute_|setM1~52_combout ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|DFFE_M1_ff~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_M1_ff~0 .lut_mask = 16'hAAA0; -defparam \z80_|sequencer_|DFFE_M1_ff~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N12 -cycloneive_lcell_comb \z80_|sequencer_|ena_M ( -// Equation(s): -// \z80_|sequencer_|ena_M~combout = (\z80_|execute_|setM1~52_combout & !\z80_|execute_|nextM~14_combout ) +// \z80_|sequencer_|SYNTHESIZED_WIRE_15~combout = (\z80_|execute_|setM1~54_combout & (\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|execute_|nextM~14_combout )) .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|setM1~52_combout ), + .datab(\z80_|execute_|setM1~54_combout ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), .datad(\z80_|execute_|nextM~14_combout ), .cin(gnd), - .combout(\z80_|sequencer_|ena_M~combout ), + .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ), .cout()); // synopsys translate_off -defparam \z80_|sequencer_|ena_M .lut_mask = 16'h00F0; -defparam \z80_|sequencer_|ena_M .sum_lutc_input = "datac"; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_15 .lut_mask = 16'h00C0; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: CLKCTRL_G9 +cycloneive_clkctrl \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\z80_|resets_|SYNTHESIZED_WIRE_12~q }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk )); +// synopsys translate_off +defparam \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl .clock_type = "global clock"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl .ena_register_mode = "none"; // synopsys translate_on // Location: IOIBUF_X0_Y16_N8 @@ -4163,7 +4146,7 @@ defparam \KEY[1]~input .bus_hold = "false"; defparam \KEY[1]~input .simulate_z_as = "z"; // synopsys translate_on -// Location: LCCOMB_X24_Y15_N6 +// Location: LCCOMB_X27_Y13_N8 cycloneive_lcell_comb \z80_|interrupts_|nmi_armed~feeder ( // Equation(s): // \z80_|interrupts_|nmi_armed~feeder_combout = VCC @@ -4180,24 +4163,24 @@ defparam \z80_|interrupts_|nmi_armed~feeder .lut_mask = 16'hFFFF; defparam \z80_|interrupts_|nmi_armed~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y15_N2 +// Location: LCCOMB_X27_Y13_N4 cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_9 ( // Equation(s): // \z80_|interrupts_|SYNTHESIZED_WIRE_9~combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .dataa(gnd), .datab(gnd), - .datac(gnd), + .datac(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .cin(gnd), .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_9~combout ), .cout()); // synopsys translate_off -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_9 .lut_mask = 16'hAAFF; +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_9 .lut_mask = 16'hF0FF; defparam \z80_|interrupts_|SYNTHESIZED_WIRE_9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y15_N7 +// Location: FF_X27_Y13_N9 dffeas \z80_|interrupts_|nmi_armed ( .clk(!\KEY[1]~input_o ), .d(\z80_|interrupts_|nmi_armed~feeder_combout ), @@ -4216,7 +4199,7 @@ defparam \z80_|interrupts_|nmi_armed .is_wysiwyg = "true"; defparam \z80_|interrupts_|nmi_armed .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y15_N12 +// Location: LCCOMB_X28_Y13_N0 cycloneive_lcell_comb \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder ( // Equation(s): // \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder_combout = \z80_|interrupts_|nmi_armed~q @@ -4233,58 +4216,60 @@ defparam \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder .lut_mask = 16'hFF00 defparam \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_eval_cond~0 ( +// Location: LCCOMB_X26_Y13_N22 +cycloneive_lcell_comb \z80_|sequencer_|DFFE_M2_ff~0 ( // Equation(s): -// \z80_|execute_|ctl_eval_cond~0_combout = (\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) +// \z80_|sequencer_|DFFE_M2_ff~0_combout = (\z80_|execute_|setM1~54_combout & ((\z80_|execute_|nextM~14_combout & (!\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|DFFE_M2_ff~q ))))) - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|execute_|setM1~54_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|execute_|nextM~14_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_eval_cond~0_combout ), + .combout(\z80_|sequencer_|DFFE_M2_ff~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_eval_cond~0 .lut_mask = 16'h00F0; -defparam \z80_|execute_|ctl_eval_cond~0 .sum_lutc_input = "datac"; +defparam \z80_|sequencer_|DFFE_M2_ff~0 .lut_mask = 16'h44C0; +defparam \z80_|sequencer_|DFFE_M2_ff~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X41_Y18_N0 -cycloneive_lcell_comb \z80_|execute_|ixy_d~4 ( -// Equation(s): -// \z80_|execute_|ixy_d~4_combout = (!\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~4_combout ), - .cout()); +// Location: FF_X26_Y13_N23 +dffeas \z80_|sequencer_|DFFE_M2_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|DFFE_M2_ff~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_M2_ff~q ), + .prn(vcc)); // synopsys translate_off -defparam \z80_|execute_|ixy_d~4 .lut_mask = 16'h1100; -defparam \z80_|execute_|ixy_d~4 .sum_lutc_input = "datac"; +defparam \z80_|sequencer_|DFFE_M2_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_M2_ff .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y17_N30 +// Location: LCCOMB_X26_Y13_N6 cycloneive_lcell_comb \z80_|sequencer_|DFFE_M3_ff~0 ( // Equation(s): -// \z80_|sequencer_|DFFE_M3_ff~0_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|DFFE_M3_ff~q ))))) +// \z80_|sequencer_|DFFE_M3_ff~0_combout = (\z80_|execute_|setM1~54_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|DFFE_M3_ff~q ))))) - .dataa(\z80_|execute_|setM1~52_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|execute_|setM1~54_combout ), .datac(\z80_|sequencer_|DFFE_M3_ff~q ), .datad(\z80_|execute_|nextM~14_combout ), .cin(gnd), .combout(\z80_|sequencer_|DFFE_M3_ff~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|sequencer_|DFFE_M3_ff~0 .lut_mask = 16'h88A0; +defparam \z80_|sequencer_|DFFE_M3_ff~0 .lut_mask = 16'h88C0; defparam \z80_|sequencer_|DFFE_M3_ff~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y17_N31 +// Location: FF_X26_Y13_N7 dffeas \z80_|sequencer_|DFFE_M3_ff ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|sequencer_|DFFE_M3_ff~0_combout ), @@ -4303,41 +4288,24 @@ defparam \z80_|sequencer_|DFFE_M3_ff .is_wysiwyg = "true"; defparam \z80_|sequencer_|DFFE_M3_ff .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X37_Y18_N12 -cycloneive_lcell_comb \z80_|execute_|fIOWrite~1 ( -// Equation(s): -// \z80_|execute_|fIOWrite~1_combout = (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|execute_|ixy_d~4_combout ))) - - .dataa(\z80_|execute_|ixy_d~4_combout ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|fIOWrite~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIOWrite~1 .lut_mask = 16'hD0D0; -defparam \z80_|execute_|fIOWrite~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N2 +// Location: LCCOMB_X26_Y13_N10 cycloneive_lcell_comb \z80_|sequencer_|DFFE_M4_ff~0 ( // Equation(s): -// \z80_|sequencer_|DFFE_M4_ff~0_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|DFFE_M4_ff~q ))))) +// \z80_|sequencer_|DFFE_M4_ff~0_combout = (\z80_|execute_|setM1~54_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|DFFE_M4_ff~q ))))) - .dataa(\z80_|execute_|setM1~52_combout ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|execute_|setM1~54_combout ), .datac(\z80_|sequencer_|DFFE_M4_ff~q ), .datad(\z80_|execute_|nextM~14_combout ), .cin(gnd), .combout(\z80_|sequencer_|DFFE_M4_ff~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|sequencer_|DFFE_M4_ff~0 .lut_mask = 16'h88A0; +defparam \z80_|sequencer_|DFFE_M4_ff~0 .lut_mask = 16'h88C0; defparam \z80_|sequencer_|DFFE_M4_ff~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y17_N3 +// Location: FF_X26_Y13_N11 dffeas \z80_|sequencer_|DFFE_M4_ff ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|sequencer_|DFFE_M4_ff~0_combout ), @@ -4356,1685 +4324,24 @@ defparam \z80_|sequencer_|DFFE_M4_ff .is_wysiwyg = "true"; defparam \z80_|sequencer_|DFFE_M4_ff .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y11_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal32~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal32~0_combout = (\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4]) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [3]), - .datac(gnd), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal32~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal32~0 .lut_mask = 16'h00CC; -defparam \z80_|pla_decode_|Equal32~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N14 -cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_11 ( -// Equation(s): -// \z80_|resets_|SYNTHESIZED_WIRE_11~combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_11 .lut_mask = 16'hFF33; -defparam \z80_|resets_|SYNTHESIZED_WIRE_11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N10 -cycloneive_lcell_comb \z80_|decode_state_|table_xx~0 ( -// Equation(s): -// \z80_|decode_state_|table_xx~0_combout = (\z80_|decode_state_|DFFE_instED~q ) # (\z80_|decode_state_|DFFE_instCB~q ) - - .dataa(\z80_|decode_state_|DFFE_instED~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|decode_state_|DFFE_instCB~q ), - .cin(gnd), - .combout(\z80_|decode_state_|table_xx~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|table_xx~0 .lut_mask = 16'hFFAA; -defparam \z80_|decode_state_|table_xx~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N10 -cycloneive_lcell_comb \z80_|pla_decode_|Equal1~7 ( -// Equation(s): -// \z80_|pla_decode_|Equal1~7_combout = (\z80_|ir_|opcode [7] & (!\z80_|decode_state_|table_xx~0_combout & (\z80_|ir_|opcode [0] & \z80_|ir_|opcode [6]))) - - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|decode_state_|table_xx~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|ir_|opcode [6]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal1~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal1~7 .lut_mask = 16'h2000; -defparam \z80_|pla_decode_|Equal1~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N20 -cycloneive_lcell_comb \z80_|pla_decode_|Equal2~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal2~0_combout = (!\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal2~0 .lut_mask = 16'h0F00; -defparam \z80_|pla_decode_|Equal2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N12 -cycloneive_lcell_comb \z80_|pla_decode_|Equal36~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal36~0_combout = (\z80_|pla_decode_|Equal1~7_combout & (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal32~0_combout & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~7_combout ), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|pla_decode_|Equal32~0_combout ), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal36~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal36~0 .lut_mask = 16'h2000; -defparam \z80_|pla_decode_|Equal36~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_cb_set ( -// Equation(s): -// \z80_|execute_|ctl_state_tbl_cb_set~combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|pla_decode_|Equal41~2_combout ) # ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal36~0_combout )))) # -// (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|pla_decode_|Equal36~0_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|pla_decode_|Equal41~2_combout ), - .datad(\z80_|pla_decode_|Equal36~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_tbl_cb_set~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_tbl_cb_set .lut_mask = 16'hB3A0; -defparam \z80_|execute_|ctl_state_tbl_cb_set .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_state_tbl_we~8_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # ((\z80_|sequencer_|DFFE_T3_ff~q & \z80_|pla_decode_|Equal41~2_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|pla_decode_|Equal41~2_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_tbl_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_tbl_we~8 .lut_mask = 16'h00EA; -defparam \z80_|execute_|ctl_state_tbl_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X41_Y17_N29 -dffeas \z80_|decode_state_|DFFE_instCB ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_state_tbl_cb_set~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_state_tbl_we~8_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|decode_state_|DFFE_instCB~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instCB .is_wysiwyg = "true"; -defparam \z80_|decode_state_|DFFE_instCB .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal52~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal52~0_combout = (\z80_|ir_|opcode [7] & (!\z80_|decode_state_|DFFE_instCB~q & (\z80_|ir_|opcode [6] & !\z80_|decode_state_|DFFE_instED~q ))) - - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|decode_state_|DFFE_instCB~q ), - .datac(\z80_|ir_|opcode [6]), - .datad(\z80_|decode_state_|DFFE_instED~q ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal52~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal52~0 .lut_mask = 16'h0020; -defparam \z80_|pla_decode_|Equal52~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal2~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal2~1_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal32~0_combout & \z80_|pla_decode_|Equal52~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|pla_decode_|Equal32~0_combout ), - .datad(\z80_|pla_decode_|Equal52~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal2~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal2~1 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal2~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_ed_set ( -// Equation(s): -// \z80_|execute_|ctl_state_tbl_ed_set~combout = (\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal2~1_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & !\z80_|ir_|opcode [1]))) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|pla_decode_|Equal2~1_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_tbl_ed_set~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_tbl_ed_set .lut_mask = 16'h0008; -defparam \z80_|execute_|ctl_state_tbl_ed_set .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X41_Y17_N17 -dffeas \z80_|decode_state_|DFFE_instED ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_state_tbl_ed_set~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_state_tbl_we~8_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|decode_state_|DFFE_instED~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instED .is_wysiwyg = "true"; -defparam \z80_|decode_state_|DFFE_instED .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal13~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal13~0_combout = (!\z80_|ir_|opcode [7] & (\z80_|ir_|opcode [6] & \z80_|decode_state_|DFFE_instED~q )) - - .dataa(\z80_|ir_|opcode [7]), - .datab(gnd), - .datac(\z80_|ir_|opcode [6]), - .datad(\z80_|decode_state_|DFFE_instED~q ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal13~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal13~0 .lut_mask = 16'h5000; -defparam \z80_|pla_decode_|Equal13~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal33~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal33~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1])) - - .dataa(\z80_|ir_|opcode [0]), - .datab(gnd), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal33~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal33~0 .lut_mask = 16'h5000; -defparam \z80_|pla_decode_|Equal33~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_im_we ( -// Equation(s): -// \z80_|execute_|ctl_im_we~combout = (\z80_|pla_decode_|Equal13~0_combout & (\z80_|sequencer_|DFFE_T3_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|pla_decode_|Equal33~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_im_we~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_im_we .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_im_we .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N18 -cycloneive_lcell_comb \z80_|pla_decode_|Equal49~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal49~0_combout = (!\z80_|decode_state_|in_halt~q & (\z80_|pla_decode_|Equal77~0_combout & \z80_|pla_decode_|Equal33~0_combout )) - - .dataa(gnd), - .datab(\z80_|decode_state_|in_halt~q ), - .datac(\z80_|pla_decode_|Equal77~0_combout ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal49~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal49~0 .lut_mask = 16'h3000; -defparam \z80_|pla_decode_|Equal49~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N2 -cycloneive_lcell_comb \z80_|pla_decode_|Equal33~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal33~1_combout = (\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [5] & !\z80_|ir_|opcode [3])) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|ir_|opcode [3]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal33~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal33~1 .lut_mask = 16'h0808; -defparam \z80_|pla_decode_|Equal33~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N30 -cycloneive_lcell_comb \z80_|pla_decode_|Equal6~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal6~0_combout = (!\z80_|ir_|opcode [7] & (!\z80_|decode_state_|DFFE_instCB~q & (!\z80_|ir_|opcode [6] & !\z80_|decode_state_|DFFE_instED~q ))) - - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|decode_state_|DFFE_instCB~q ), - .datac(\z80_|ir_|opcode [6]), - .datad(\z80_|decode_state_|DFFE_instED~q ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal6~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal6~0 .lut_mask = 16'h0001; -defparam \z80_|pla_decode_|Equal6~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~14 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~14_combout = (!\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal6~0_combout )) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~14 .lut_mask = 16'h4400; -defparam \z80_|execute_|ctl_mRead~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N18 -cycloneive_lcell_comb \z80_|pla_decode_|Equal12~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal12~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2]))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal12~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal12~0 .lut_mask = 16'h0040; -defparam \z80_|pla_decode_|Equal12~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~8 ( -// Equation(s): -// \z80_|execute_|ctl_sw_1d~8_combout = (((!\z80_|ir_|opcode [4] & \z80_|ir_|opcode [5])) # (!\z80_|pla_decode_|Equal12~0_combout )) # (!\z80_|ir_|opcode [3]) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal12~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~8 .lut_mask = 16'h4FFF; -defparam \z80_|execute_|ctl_sw_1d~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N12 -cycloneive_lcell_comb \z80_|nM1_int~2 ( -// Equation(s): -// \z80_|nM1_int~2_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|nM1_int~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|nM1_int~2 .lut_mask = 16'h0055; -defparam \z80_|nM1_int~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~5 ( -// Equation(s): -// \z80_|execute_|ctl_sw_1d~5_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal49~0_combout ) # ((\z80_|execute_|ctl_mRead~14_combout ) # (!\z80_|execute_|ctl_sw_1d~8_combout )))) - - .dataa(\z80_|pla_decode_|Equal49~0_combout ), - .datab(\z80_|execute_|ctl_mRead~14_combout ), - .datac(\z80_|execute_|ctl_sw_1d~8_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~5 .lut_mask = 16'hEF00; -defparam \z80_|execute_|ctl_sw_1d~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal3~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal3~0_combout = (\z80_|ir_|opcode [3] & \z80_|ir_|opcode [4]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal3~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal3~0 .lut_mask = 16'hF000; -defparam \z80_|pla_decode_|Equal3~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~4 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~4_combout = (\z80_|pla_decode_|Equal1~7_combout & (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal3~0_combout & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~7_combout ), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|pla_decode_|Equal3~0_combout ), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~4 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_mRead~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|ixy_d~7 ( -// Equation(s): -// \z80_|execute_|ixy_d~7_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M3_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~7 .lut_mask = 16'h0F00; -defparam \z80_|execute_|ixy_d~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~4 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~4_combout = (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~4 .lut_mask = 16'hA0A0; -defparam \z80_|execute_|ctl_state_alu~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~4 ( -// Equation(s): -// \z80_|execute_|ctl_sw_1d~4_combout = (\z80_|execute_|ctl_mRead~5_combout & (!\z80_|execute_|ctl_state_alu~4_combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|execute_|ctl_mRead~4_combout )))) # (!\z80_|execute_|ctl_mRead~5_combout & -// (((!\z80_|execute_|ixy_d~7_combout )) # (!\z80_|execute_|ctl_mRead~4_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~5_combout ), - .datab(\z80_|execute_|ctl_mRead~4_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~4 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_sw_1d~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N10 -cycloneive_lcell_comb \z80_|pla_decode_|Equal40~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal40~1_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal40~0_combout & \z80_|ir_|opcode [5])) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal40~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal40~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal40~1 .lut_mask = 16'h8080; -defparam \z80_|pla_decode_|Equal40~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal39~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal39~0_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal40~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal3~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal40~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal3~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal39~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal39~0 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal39~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~1 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~1_combout = (!\z80_|pla_decode_|Equal40~1_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal39~0_combout )) - - .dataa(\z80_|pla_decode_|Equal40~1_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~1 .lut_mask = 16'h0005; -defparam \z80_|execute_|ctl_bus_db_oe~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N26 -cycloneive_lcell_comb \z80_|pla_decode_|Equal13~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal13~1_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1])) - - .dataa(\z80_|ir_|opcode [0]), - .datab(gnd), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal13~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal13~1 .lut_mask = 16'hA000; -defparam \z80_|pla_decode_|Equal13~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal13~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal13~2_combout = (\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|pla_decode_|Equal13~1_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal13~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal13~2 .lut_mask = 16'h2000; -defparam \z80_|pla_decode_|Equal13~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal3~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal3~2_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal3~0_combout & \z80_|pla_decode_|Equal52~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|pla_decode_|Equal3~0_combout ), - .datad(\z80_|pla_decode_|Equal52~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal3~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal3~2 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal3~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_state_iy_set~2 ( -// Equation(s): -// \z80_|execute_|ctl_state_iy_set~2_combout = (\z80_|ir_|opcode [5] & (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal3~2_combout & \z80_|sequencer_|DFFE_T2_ff~q ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|pla_decode_|Equal3~2_combout ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_iy_set~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_iy_set~2 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_state_iy_set~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N26 -cycloneive_lcell_comb \z80_|execute_|ixy_d~8 ( -// Equation(s): -// \z80_|execute_|ixy_d~8_combout = (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T5_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|sequencer_|DFFE_T5_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~8 .lut_mask = 16'hC0C0; -defparam \z80_|execute_|ixy_d~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ixy_d~6 ( -// Equation(s): -// \z80_|execute_|ixy_d~6_combout = (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~6 .lut_mask = 16'hF000; -defparam \z80_|execute_|ixy_d~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N6 -cycloneive_lcell_comb \z80_|execute_|ixy_d~9 ( -// Equation(s): -// \z80_|execute_|ixy_d~9_combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_M3_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~9 .lut_mask = 16'hF000; -defparam \z80_|execute_|ixy_d~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N8 -cycloneive_lcell_comb \z80_|execute_|ixy_d~12 ( -// Equation(s): -// \z80_|execute_|ixy_d~12_combout = (!\z80_|execute_|ixy_d~7_combout & (!\z80_|execute_|ixy_d~8_combout & (!\z80_|execute_|ixy_d~6_combout & !\z80_|execute_|ixy_d~9_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ixy_d~8_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|execute_|ixy_d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~12 .lut_mask = 16'h0001; -defparam \z80_|execute_|ixy_d~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N22 -cycloneive_lcell_comb \z80_|execute_|ixy_d~10 ( -// Equation(s): -// \z80_|execute_|ixy_d~10_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|pla_decode_|Equal3~1_combout ), - .datac(\z80_|decode_state_|use_ixiy~combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~10 .lut_mask = 16'h8000; -defparam \z80_|execute_|ixy_d~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal44~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal44~0_combout = (\z80_|ir_|opcode [7] & (!\z80_|decode_state_|DFFE_instCB~q & (!\z80_|ir_|opcode [6] & !\z80_|decode_state_|DFFE_instED~q ))) - - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|decode_state_|DFFE_instCB~q ), - .datac(\z80_|ir_|opcode [6]), - .datad(\z80_|decode_state_|DFFE_instED~q ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal44~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal44~0 .lut_mask = 16'h0002; -defparam \z80_|pla_decode_|Equal44~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N0 -cycloneive_lcell_comb \z80_|execute_|ixy_d~16 ( -// Equation(s): -// \z80_|execute_|ixy_d~16_combout = (\z80_|pla_decode_|Equal44~0_combout & (\z80_|pla_decode_|Equal33~0_combout & ((\z80_|decode_state_|DFFE_inst4~q ) # (\z80_|decode_state_|DFFE_instIY1~q )))) - - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(\z80_|pla_decode_|Equal44~0_combout ), - .datac(\z80_|decode_state_|DFFE_instIY1~q ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~16 .lut_mask = 16'hC800; -defparam \z80_|execute_|ixy_d~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N28 -cycloneive_lcell_comb \z80_|execute_|ixy_d~13 ( -// Equation(s): -// \z80_|execute_|ixy_d~13_combout = (\z80_|pla_decode_|Equal41~2_combout ) # ((\z80_|execute_|ixy_d~10_combout ) # (\z80_|execute_|ixy_d~16_combout )) - - .dataa(gnd), - .datab(\z80_|pla_decode_|Equal41~2_combout ), - .datac(\z80_|execute_|ixy_d~10_combout ), - .datad(\z80_|execute_|ixy_d~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~13 .lut_mask = 16'hFFFC; -defparam \z80_|execute_|ixy_d~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal50~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal50~0_combout = (!\z80_|decode_state_|in_halt~q & (\z80_|pla_decode_|Equal77~0_combout & \z80_|pla_decode_|Equal33~1_combout )) - - .dataa(gnd), - .datab(\z80_|decode_state_|in_halt~q ), - .datac(\z80_|pla_decode_|Equal77~0_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal50~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal50~0 .lut_mask = 16'h3000; -defparam \z80_|pla_decode_|Equal50~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal33~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal33~2_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal6~0_combout )) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal33~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal33~2 .lut_mask = 16'h8800; -defparam \z80_|pla_decode_|Equal33~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N30 -cycloneive_lcell_comb \z80_|execute_|ixy_d~17 ( -// Equation(s): -// \z80_|execute_|ixy_d~17_combout = (\z80_|decode_state_|DFFE_inst4~q & (!\z80_|pla_decode_|Equal50~0_combout & ((!\z80_|pla_decode_|Equal33~2_combout )))) # (!\z80_|decode_state_|DFFE_inst4~q & (((!\z80_|pla_decode_|Equal50~0_combout & -// !\z80_|pla_decode_|Equal33~2_combout )) # (!\z80_|decode_state_|DFFE_instIY1~q ))) - - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(\z80_|pla_decode_|Equal50~0_combout ), - .datac(\z80_|decode_state_|DFFE_instIY1~q ), - .datad(\z80_|pla_decode_|Equal33~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~17 .lut_mask = 16'h0537; -defparam \z80_|execute_|ixy_d~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N16 -cycloneive_lcell_comb \z80_|execute_|ixy_d~5 ( -// Equation(s): -// \z80_|execute_|ixy_d~5_combout = (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_M3_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~5 .lut_mask = 16'hF000; -defparam \z80_|execute_|ixy_d~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N22 -cycloneive_lcell_comb \z80_|execute_|ixy_d~14 ( -// Equation(s): -// \z80_|execute_|ixy_d~14_combout = (\z80_|execute_|ixy_d~12_combout & (((!\z80_|execute_|ixy_d~13_combout & \z80_|execute_|ixy_d~17_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) # (!\z80_|execute_|ixy_d~12_combout & -// (!\z80_|execute_|ixy_d~13_combout & (\z80_|execute_|ixy_d~17_combout ))) - - .dataa(\z80_|execute_|ixy_d~12_combout ), - .datab(\z80_|execute_|ixy_d~13_combout ), - .datac(\z80_|execute_|ixy_d~17_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~14 .lut_mask = 16'h30BA; -defparam \z80_|execute_|ixy_d~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N18 -cycloneive_lcell_comb \z80_|execute_|ixy_d~11 ( -// Equation(s): -// \z80_|execute_|ixy_d~11_combout = (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T5_ff~q ) # ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|execute_|ixy_d~4_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|execute_|ixy_d~4_combout ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~11 .lut_mask = 16'hCC8C; -defparam \z80_|execute_|ixy_d~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N12 -cycloneive_lcell_comb \z80_|execute_|ixy_d~15 ( -// Equation(s): -// \z80_|execute_|ixy_d~15_combout = ((\z80_|pla_decode_|Equal49~0_combout & (\z80_|decode_state_|use_ixiy~combout & \z80_|execute_|ixy_d~11_combout ))) # (!\z80_|execute_|ixy_d~14_combout ) - - .dataa(\z80_|pla_decode_|Equal49~0_combout ), - .datab(\z80_|decode_state_|use_ixiy~combout ), - .datac(\z80_|execute_|ixy_d~14_combout ), - .datad(\z80_|execute_|ixy_d~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~15 .lut_mask = 16'h8F0F; -defparam \z80_|execute_|ixy_d~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_state_ixiy_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_state_ixiy_we~2_combout = (\z80_|sequencer_|DFFE_T5_ff~q & ((\z80_|execute_|ixy_d~15_combout ) # ((\z80_|sequencer_|DFFE_T2_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )))) # (!\z80_|sequencer_|DFFE_T5_ff~q & -// (\z80_|sequencer_|DFFE_T2_ff~q & ((!\z80_|sequencer_|DFFE_M1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|execute_|ixy_d~15_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_ixiy_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_ixiy_we~2 .lut_mask = 16'hA0EC; -defparam \z80_|execute_|ctl_state_ixiy_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y15_N23 -dffeas \z80_|decode_state_|DFFE_instIY1 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_state_iy_set~2_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_state_ixiy_we~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|decode_state_|DFFE_instIY1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instIY1 .is_wysiwyg = "true"; -defparam \z80_|decode_state_|DFFE_instIY1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~5_combout = (!\z80_|decode_state_|DFFE_inst4~q & (!\z80_|decode_state_|DFFE_instIY1~q & \z80_|decode_state_|DFFE_instCB~q )) - - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(gnd), - .datac(\z80_|decode_state_|DFFE_instIY1~q ), - .datad(\z80_|decode_state_|DFFE_instCB~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~5 .lut_mask = 16'h0500; -defparam \z80_|execute_|ctl_ir_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~14 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~14_combout = (!\z80_|ir_|opcode [6] & (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) - - .dataa(\z80_|ir_|opcode [6]), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|execute_|ctl_ir_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~14 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_ir_we~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~2 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~2_combout = (\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [6] & (\z80_|ir_|opcode [7] & \z80_|decode_state_|DFFE_instED~q ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|ir_|opcode [6]), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|decode_state_|DFFE_instED~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~2 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_mWrite~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~16 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~16_combout = (\z80_|ir_|opcode [1] & (\z80_|execute_|ctl_mWrite~2_combout & (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [0]))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~16 .lut_mask = 16'h0008; -defparam \z80_|execute_|ctl_mWrite~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~18 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~18_combout = (((!\z80_|execute_|ctl_ir_we~14_combout & !\z80_|execute_|ctl_mWrite~16_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|sequencer_|DFFE_T4_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|execute_|ctl_ir_we~14_combout ), - .datad(\z80_|execute_|ctl_mWrite~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~18 .lut_mask = 16'h777F; -defparam \z80_|execute_|ctl_flags_alu~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~26 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~26_combout = (\z80_|pla_decode_|Equal13~2_combout & !\z80_|ir_|opcode [3]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~26 .lut_mask = 16'h00F0; -defparam \z80_|execute_|ctl_mRead~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~27 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~27_combout = (\z80_|pla_decode_|Equal13~2_combout & \z80_|ir_|opcode [3]) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(gnd), - .datac(\z80_|ir_|opcode [3]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~27 .lut_mask = 16'hA0A0; -defparam \z80_|execute_|ctl_mRead~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~7 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~7_combout = (\z80_|execute_|ctl_flags_alu~18_combout & (((!\z80_|execute_|ctl_mRead~26_combout & !\z80_|execute_|ctl_mRead~27_combout )) # (!\z80_|execute_|ixy_d~9_combout ))) - - .dataa(\z80_|execute_|ctl_flags_alu~18_combout ), - .datab(\z80_|execute_|ctl_mRead~26_combout ), - .datac(\z80_|execute_|ctl_mRead~27_combout ), - .datad(\z80_|execute_|ixy_d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~7 .lut_mask = 16'h02AA; -defparam \z80_|execute_|ctl_bus_db_oe~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~5 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~5_combout = (\z80_|execute_|ctl_bus_db_oe~7_combout & (((\z80_|execute_|ctl_bus_db_oe~1_combout & !\z80_|pla_decode_|Equal13~2_combout )) # (!\z80_|execute_|ixy_d~7_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~5 .lut_mask = 16'h5D00; -defparam \z80_|execute_|ctl_sw_2d~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~18 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~18_combout = (!\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal12~0_combout ))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal12~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~18 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_mRead~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N12 -cycloneive_lcell_comb \z80_|pla_decode_|Equal55~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal55~0_combout = (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1])) - - .dataa(\z80_|ir_|opcode [0]), - .datab(gnd), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal55~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal55~0 .lut_mask = 16'h0500; -defparam \z80_|pla_decode_|Equal55~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|comb~1 ( -// Equation(s): -// \z80_|execute_|comb~1_combout = (\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4]) - - .dataa(\z80_|ir_|opcode [5]), - .datab(gnd), - .datac(\z80_|ir_|opcode [4]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|comb~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|comb~1 .lut_mask = 16'hA0A0; -defparam \z80_|execute_|comb~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~15 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~15_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [3] & \z80_|execute_|comb~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|execute_|comb~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~15 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_mRead~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~17 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~17_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~17 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_mRead~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~5_combout = ((!\z80_|execute_|ctl_mRead~18_combout & (!\z80_|execute_|ctl_mRead~15_combout & !\z80_|execute_|ctl_mRead~17_combout ))) # (!\z80_|execute_|ixy_d~6_combout ) - - .dataa(\z80_|execute_|ctl_mRead~18_combout ), - .datab(\z80_|execute_|ctl_mRead~15_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|execute_|ctl_mRead~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~5 .lut_mask = 16'h0F1F; -defparam \z80_|execute_|ctl_reg_in_hi~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~9 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~9_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal55~0_combout & \z80_|pla_decode_|Equal33~1_combout )) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~9 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_mRead~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal9~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal9~0_combout = (!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal9~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal9~0 .lut_mask = 16'h000F; -defparam \z80_|pla_decode_|Equal9~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~10 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~10_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal55~0_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal9~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal9~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~10 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_mRead~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~8 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~8_combout = (\z80_|pla_decode_|Equal13~0_combout & (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~8 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_mRead~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~20 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~20_combout = (\z80_|execute_|ctl_mRead~9_combout ) # ((\z80_|execute_|ctl_mRead~15_combout ) # ((\z80_|execute_|ctl_mRead~10_combout ) # (\z80_|execute_|ctl_mRead~8_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~9_combout ), - .datab(\z80_|execute_|ctl_mRead~15_combout ), - .datac(\z80_|execute_|ctl_mRead~10_combout ), - .datad(\z80_|execute_|ctl_mRead~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~20 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_mRead~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal12~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal12~1_combout = (\z80_|pla_decode_|Equal55~0_combout & (!\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal6~0_combout )) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal12~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal12~1 .lut_mask = 16'h2200; -defparam \z80_|pla_decode_|Equal12~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N10 -cycloneive_lcell_comb \z80_|pla_decode_|Equal9~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal9~1_combout = (\z80_|pla_decode_|Equal9~0_combout & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal1~7_combout ))) - - .dataa(\z80_|pla_decode_|Equal9~0_combout ), - .datab(\z80_|pla_decode_|Equal2~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal1~7_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal9~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal9~1 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal9~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal25~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal25~0_combout = (\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal55~0_combout & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal25~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal25~0 .lut_mask = 16'h2000; -defparam \z80_|pla_decode_|Equal25~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~21 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~21_combout = (\z80_|pla_decode_|Equal9~1_combout ) # ((\z80_|execute_|ctl_mRead~17_combout ) # ((!\z80_|pla_decode_|Equal12~1_combout & \z80_|pla_decode_|Equal25~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal12~1_combout ), - .datab(\z80_|pla_decode_|Equal9~1_combout ), - .datac(\z80_|execute_|ctl_mRead~17_combout ), - .datad(\z80_|pla_decode_|Equal25~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~21 .lut_mask = 16'hFDFC; -defparam \z80_|execute_|ctl_mRead~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~6 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~6_combout = (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_M4_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~6 .lut_mask = 16'hA0A0; -defparam \z80_|execute_|ctl_state_alu~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal19~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal19~0_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal32~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal1~7_combout ))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|pla_decode_|Equal32~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal1~7_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal19~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal19~0 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal19~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N30 -cycloneive_lcell_comb \z80_|pla_decode_|Equal1~4 ( -// Equation(s): -// \z80_|pla_decode_|Equal1~4_combout = (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [1]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal1~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal1~4 .lut_mask = 16'h000F; -defparam \z80_|pla_decode_|Equal1~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N2 -cycloneive_lcell_comb \z80_|pla_decode_|Equal29~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal29~0_combout = (\z80_|pla_decode_|Equal1~7_combout & (\z80_|pla_decode_|Equal1~4_combout & (\z80_|pla_decode_|Equal32~0_combout & !\z80_|ir_|opcode [5]))) - - .dataa(\z80_|pla_decode_|Equal1~7_combout ), - .datab(\z80_|pla_decode_|Equal1~4_combout ), - .datac(\z80_|pla_decode_|Equal32~0_combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal29~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal29~0 .lut_mask = 16'h0080; -defparam \z80_|pla_decode_|Equal29~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N20 -cycloneive_lcell_comb \z80_|pla_decode_|Equal24~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal24~1_combout = (\z80_|pla_decode_|Equal9~0_combout & (\z80_|pla_decode_|Equal2~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal1~7_combout ))) - - .dataa(\z80_|pla_decode_|Equal9~0_combout ), - .datab(\z80_|pla_decode_|Equal2~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal1~7_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal24~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal24~1 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal24~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N18 -cycloneive_lcell_comb \z80_|pla_decode_|Equal34~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal34~0_combout = (!\z80_|ir_|opcode [0] & (!\z80_|decode_state_|table_xx~0_combout & (\z80_|pla_decode_|Equal3~1_combout & \z80_|pla_decode_|Equal41~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|decode_state_|table_xx~0_combout ), - .datac(\z80_|pla_decode_|Equal3~1_combout ), - .datad(\z80_|pla_decode_|Equal41~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal34~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal34~0 .lut_mask = 16'h1000; -defparam \z80_|pla_decode_|Equal34~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal37~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal37~0_combout = (\z80_|pla_decode_|Equal41~0_combout & (!\z80_|decode_state_|table_xx~0_combout & (!\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal1~4_combout ))) - - .dataa(\z80_|pla_decode_|Equal41~0_combout ), - .datab(\z80_|decode_state_|table_xx~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal1~4_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal37~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal37~0 .lut_mask = 16'h0200; -defparam \z80_|pla_decode_|Equal37~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N12 -cycloneive_lcell_comb \z80_|pla_decode_|Equal35~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal35~0_combout = (\z80_|pla_decode_|Equal41~0_combout & (!\z80_|decode_state_|table_xx~0_combout & (!\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal41~0_combout ), - .datab(\z80_|decode_state_|table_xx~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal35~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal35~0 .lut_mask = 16'h0200; -defparam \z80_|pla_decode_|Equal35~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N14 -cycloneive_lcell_comb \z80_|pla_decode_|Equal38~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal38~2_combout = (!\z80_|ir_|opcode [1] & (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [2] & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal38~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal38~2 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal38~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N14 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~2 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~2_combout = (\z80_|pla_decode_|Equal34~0_combout ) # ((\z80_|pla_decode_|Equal37~0_combout ) # ((\z80_|pla_decode_|Equal35~0_combout ) # (\z80_|pla_decode_|Equal38~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal34~0_combout ), - .datab(\z80_|pla_decode_|Equal37~0_combout ), - .datac(\z80_|pla_decode_|Equal35~0_combout ), - .datad(\z80_|pla_decode_|Equal38~2_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~2 .lut_mask = 16'hFFFE; -defparam \z80_|reg_control_|reg_sys_we_lo~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N22 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~3 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~3_combout = (\z80_|pla_decode_|Equal19~0_combout ) # ((\z80_|pla_decode_|Equal29~0_combout ) # ((\z80_|pla_decode_|Equal24~1_combout ) # (\z80_|reg_control_|reg_sys_we_lo~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal19~0_combout ), - .datab(\z80_|pla_decode_|Equal29~0_combout ), - .datac(\z80_|pla_decode_|Equal24~1_combout ), - .datad(\z80_|reg_control_|reg_sys_we_lo~2_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~3 .lut_mask = 16'hFFFE; -defparam \z80_|reg_control_|reg_sys_we_lo~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N4 -cycloneive_lcell_comb \z80_|execute_|comb~0 ( -// Equation(s): -// \z80_|execute_|comb~0_combout = (\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1]) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [2]), - .datac(\z80_|ir_|opcode [1]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|comb~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|comb~0 .lut_mask = 16'hC0C0; -defparam \z80_|execute_|comb~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N30 -cycloneive_lcell_comb \z80_|pla_decode_|Equal47~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal47~0_combout = (\z80_|pla_decode_|Equal41~0_combout & (!\z80_|decode_state_|table_xx~0_combout & (\z80_|ir_|opcode [0] & \z80_|execute_|comb~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal41~0_combout ), - .datab(\z80_|decode_state_|table_xx~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|execute_|comb~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal47~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal47~0 .lut_mask = 16'h2000; -defparam \z80_|pla_decode_|Equal47~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N8 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~4 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~4_combout = (\z80_|execute_|ctl_state_alu~6_combout & (!\z80_|pla_decode_|Equal47~0_combout & ((!\z80_|reg_control_|reg_sys_we_lo~3_combout ) # (!\z80_|execute_|ctl_state_alu~4_combout )))) # -// (!\z80_|execute_|ctl_state_alu~6_combout & (((!\z80_|reg_control_|reg_sys_we_lo~3_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~6_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|reg_control_|reg_sys_we_lo~3_combout ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~4 .lut_mask = 16'h153F; -defparam \z80_|reg_control_|reg_sys_we_lo~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~22 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~22_combout = (\z80_|reg_control_|reg_sys_we_lo~4_combout & (((!\z80_|execute_|ctl_mRead~20_combout & !\z80_|execute_|ctl_mRead~21_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~20_combout ), - .datab(\z80_|execute_|ctl_mRead~21_combout ), - .datac(\z80_|reg_control_|reg_sys_we_lo~4_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~22 .lut_mask = 16'h10F0; -defparam \z80_|execute_|ctl_mRead~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~24 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~24_combout = (\z80_|execute_|ctl_reg_in_hi~5_combout & (\z80_|execute_|ctl_mRead~22_combout & ((!\z80_|execute_|ctl_state_alu~6_combout ) # (!\z80_|execute_|ctl_mRead~18_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~18_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~5_combout ), - .datac(\z80_|execute_|ctl_mRead~22_combout ), - .datad(\z80_|execute_|ctl_state_alu~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~24 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_mRead~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout = (\z80_|pla_decode_|Equal52~0_combout & (!\z80_|ir_|opcode [0] & (\z80_|execute_|ixy_d~6_combout & \z80_|pla_decode_|Equal3~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal52~0_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|pla_decode_|Equal3~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~6_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & (((!\z80_|pla_decode_|Equal19~0_combout & !\z80_|pla_decode_|Equal35~0_combout )) # (!\z80_|execute_|ixy_d~6_combout ))) - - .dataa(\z80_|pla_decode_|Equal19~0_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|pla_decode_|Equal35~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~6 .lut_mask = 16'h0313; -defparam \z80_|execute_|ctl_reg_in_hi~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N20 -cycloneive_lcell_comb \z80_|pla_decode_|Equal6~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal6~1_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal1~4_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal1~4_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal6~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal6~1 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal6~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~16 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~16_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal1~4_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal52~0_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal1~4_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal52~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~16 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_mRead~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N16 +// Location: LCCOMB_X26_Y13_N0 cycloneive_lcell_comb \z80_|sequencer_|M5~0 ( // Equation(s): -// \z80_|sequencer_|M5~0_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|M5~q ))))) +// \z80_|sequencer_|M5~0_combout = (\z80_|execute_|setM1~54_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|M5~q ))))) - .dataa(\z80_|execute_|setM1~52_combout ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|execute_|setM1~54_combout ), .datac(\z80_|sequencer_|M5~q ), .datad(\z80_|execute_|nextM~14_combout ), .cin(gnd), .combout(\z80_|sequencer_|M5~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|sequencer_|M5~0 .lut_mask = 16'h88A0; +defparam \z80_|sequencer_|M5~0 .lut_mask = 16'h88C0; defparam \z80_|sequencer_|M5~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y17_N17 +// Location: FF_X26_Y13_N1 dffeas \z80_|sequencer_|M5 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|sequencer_|M5~0_combout ), @@ -6053,12847 +4360,427 @@ defparam \z80_|sequencer_|M5 .is_wysiwyg = "true"; defparam \z80_|sequencer_|M5 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X38_Y17_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~2 ( +// Location: LCCOMB_X24_Y11_N10 +cycloneive_lcell_comb \z80_|execute_|ixy_d~5 ( // Equation(s): -// \z80_|execute_|ctl_reg_in_hi~2_combout = (\z80_|sequencer_|M5~q & \z80_|sequencer_|DFFE_T3_ff~q ) +// \z80_|execute_|ixy_d~5_combout = (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ) .dataa(gnd), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), .datad(gnd), .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .combout(\z80_|execute_|ixy_d~5_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~2 .lut_mask = 16'hC0C0; -defparam \z80_|execute_|ctl_reg_in_hi~2 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ixy_d~5 .lut_mask = 16'hC0C0; +defparam \z80_|execute_|ixy_d~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|setM1~29 ( -// Equation(s): -// \z80_|execute_|setM1~29_combout = (\z80_|execute_|ctl_mRead~16_combout & (!\z80_|execute_|ixy_d~6_combout & ((!\z80_|execute_|ctl_mRead~17_combout ) # (!\z80_|execute_|ctl_reg_in_hi~2_combout )))) # (!\z80_|execute_|ctl_mRead~16_combout & -// (((!\z80_|execute_|ctl_mRead~17_combout ) # (!\z80_|execute_|ctl_reg_in_hi~2_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~16_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datad(\z80_|execute_|ctl_mRead~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~29 .lut_mask = 16'h0777; -defparam \z80_|execute_|setM1~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~25 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~25_combout = (\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|execute_|ctl_mRead~16_combout & ((!\z80_|execute_|ctl_state_alu~6_combout ) # (!\z80_|execute_|ctl_mRead~17_combout )))) # (!\z80_|execute_|ctl_state_alu~4_combout -// & (((!\z80_|execute_|ctl_state_alu~6_combout )) # (!\z80_|execute_|ctl_mRead~17_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_mRead~17_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_mRead~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~25 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_mRead~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~6_combout = (\z80_|execute_|setM1~29_combout & (\z80_|execute_|ctl_mRead~25_combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|pla_decode_|Equal6~1_combout )))) - - .dataa(\z80_|pla_decode_|Equal6~1_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|execute_|setM1~29_combout ), - .datad(\z80_|execute_|ctl_mRead~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~6 .lut_mask = 16'h7000; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~7_combout = (!\z80_|ir_|opcode [6] & (\z80_|pla_decode_|Equal33~0_combout & (\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) - - .dataa(\z80_|ir_|opcode [6]), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|execute_|ctl_ir_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~7 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_ir_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N2 -cycloneive_lcell_comb \z80_|pla_decode_|Equal52~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal52~1_combout = (!\z80_|decode_state_|DFFE_instED~q & (\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal41~0_combout & !\z80_|decode_state_|DFFE_instCB~q ))) - - .dataa(\z80_|decode_state_|DFFE_instED~q ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|pla_decode_|Equal41~0_combout ), - .datad(\z80_|decode_state_|DFFE_instCB~q ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal52~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal52~1 .lut_mask = 16'h0040; -defparam \z80_|pla_decode_|Equal52~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~14 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~14_combout = (!\z80_|decode_state_|DFFE_inst4~q & (\z80_|pla_decode_|Equal44~0_combout & (!\z80_|decode_state_|DFFE_instIY1~q & \z80_|pla_decode_|Equal33~0_combout ))) - - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(\z80_|pla_decode_|Equal44~0_combout ), - .datac(\z80_|decode_state_|DFFE_instIY1~q ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~14 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_state_alu~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~8 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~8_combout = (\z80_|execute_|ctl_state_alu~4_combout & (((!\z80_|pla_decode_|Equal52~1_combout & !\z80_|execute_|ctl_state_alu~14_combout )))) # (!\z80_|execute_|ctl_state_alu~4_combout & -// (((!\z80_|execute_|ctl_state_alu~14_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_state_alu~6_combout ), - .datac(\z80_|pla_decode_|Equal52~1_combout ), - .datad(\z80_|execute_|ctl_state_alu~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~8 .lut_mask = 16'h115F; -defparam \z80_|execute_|ctl_state_alu~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N20 -cycloneive_lcell_comb \z80_|pla_decode_|Equal24~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal24~0_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|pla_decode_|Equal52~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal24~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal24~0 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal24~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N0 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_pc~0_combout = ((!\z80_|pla_decode_|Equal37~0_combout & ((!\z80_|pla_decode_|Equal9~0_combout ) # (!\z80_|pla_decode_|Equal24~0_combout )))) # (!\z80_|execute_|ixy_d~6_combout ) - - .dataa(\z80_|pla_decode_|Equal24~0_combout ), - .datab(\z80_|pla_decode_|Equal37~0_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|pla_decode_|Equal9~0_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_pc~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_pc~0 .lut_mask = 16'h1F3F; -defparam \z80_|reg_control_|reg_sel_pc~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N26 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~1 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_pc~1_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ctl_reg_in_hi~2_combout & ((!\z80_|pla_decode_|Equal29~0_combout ) # (!\z80_|execute_|ixy_d~6_combout )))) # (!\z80_|pla_decode_|Equal47~0_combout & -// (((!\z80_|pla_decode_|Equal29~0_combout )) # (!\z80_|execute_|ixy_d~6_combout ))) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datad(\z80_|pla_decode_|Equal29~0_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_pc~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_pc~1 .lut_mask = 16'h135F; -defparam \z80_|reg_control_|reg_sel_pc~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N12 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~2 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_pc~2_combout = (\z80_|reg_control_|reg_sel_pc~0_combout & (\z80_|reg_control_|reg_sel_pc~1_combout & ((!\z80_|pla_decode_|Equal38~2_combout ) # (!\z80_|execute_|ixy_d~6_combout )))) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|reg_control_|reg_sel_pc~0_combout ), - .datac(\z80_|reg_control_|reg_sel_pc~1_combout ), - .datad(\z80_|pla_decode_|Equal38~2_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_pc~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_pc~2 .lut_mask = 16'h40C0; -defparam \z80_|reg_control_|reg_sel_pc~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|fMRead~17 ( -// Equation(s): -// \z80_|execute_|fMRead~17_combout = (\z80_|execute_|ctl_state_alu~8_combout & (\z80_|reg_control_|reg_sel_pc~2_combout & ((!\z80_|execute_|ctl_ir_we~7_combout ) # (!\z80_|execute_|ctl_state_alu~4_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_ir_we~7_combout ), - .datac(\z80_|execute_|ctl_state_alu~8_combout ), - .datad(\z80_|reg_control_|reg_sel_pc~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~17 .lut_mask = 16'h7000; -defparam \z80_|execute_|fMRead~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~6 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~6_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal3~1_combout & (!\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|pla_decode_|Equal3~1_combout ), - .datac(\z80_|decode_state_|use_ixiy~combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~6 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_mRead~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal11~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal11~0_combout = (!\z80_|ir_|opcode [1] & (\z80_|execute_|ctl_mWrite~2_combout & (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [0]))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal11~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal11~0 .lut_mask = 16'h0004; -defparam \z80_|pla_decode_|Equal11~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal10~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal10~0_combout = (!\z80_|ir_|opcode [1] & (\z80_|execute_|ctl_mWrite~2_combout & (!\z80_|ir_|opcode [2] & \z80_|ir_|opcode [0]))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal10~0 .lut_mask = 16'h0400; -defparam \z80_|pla_decode_|Equal10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~9_combout = (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|pla_decode_|Equal10~0_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(\z80_|pla_decode_|Equal11~0_combout ), - .datab(\z80_|pla_decode_|Equal10~0_combout ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~9 .lut_mask = 16'h1FFF; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~4 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~4_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & (((!\z80_|execute_|ctl_state_alu~4_combout & !\z80_|execute_|ctl_state_alu~6_combout )) # (!\z80_|execute_|ctl_mRead~6_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_state_alu~6_combout ), - .datac(\z80_|execute_|ctl_mRead~6_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~4 .lut_mask = 16'h1F00; -defparam \z80_|execute_|ctl_sw_2d~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~15 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~15_combout = (\z80_|ir_|opcode [6] & (\z80_|pla_decode_|Equal33~0_combout & (\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) - - .dataa(\z80_|ir_|opcode [6]), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|execute_|ctl_ir_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~15 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_ir_we~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|fMRead~16 ( -// Equation(s): -// \z80_|execute_|fMRead~16_combout = (\z80_|execute_|ctl_reg_in_hi~2_combout & (!\z80_|execute_|ctl_mRead~18_combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_ir_we~15_combout )))) # (!\z80_|execute_|ctl_reg_in_hi~2_combout & -// (((!\z80_|execute_|ctl_state_alu~4_combout )) # (!\z80_|execute_|ctl_ir_we~15_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_mRead~18_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~16 .lut_mask = 16'h135F; -defparam \z80_|execute_|fMRead~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~9 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~9_combout = (\z80_|execute_|ctl_ir_we~5_combout & (\z80_|pla_decode_|Equal41~0_combout & ((!\z80_|decode_state_|DFFE_instCB~q ) # (!\z80_|pla_decode_|Equal33~0_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~5_combout ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|pla_decode_|Equal41~0_combout ), - .datad(\z80_|decode_state_|DFFE_instCB~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~9 .lut_mask = 16'h20A0; -defparam \z80_|execute_|ctl_ir_we~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N22 -cycloneive_lcell_comb \z80_|pla_decode_|Equal46~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal46~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [1] & (\z80_|ir_|opcode [2] & \z80_|decode_state_|DFFE_instCB~q ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [1]), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|decode_state_|DFFE_instCB~q ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal46~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal46~0 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal46~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~10 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~10_combout = (!\z80_|ir_|opcode [6] & (!\z80_|pla_decode_|Equal46~0_combout & (\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) - - .dataa(\z80_|ir_|opcode [6]), - .datab(\z80_|pla_decode_|Equal46~0_combout ), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|execute_|ctl_ir_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~10 .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_ir_we~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~17 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~17_combout = (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|execute_|ctl_ir_we~7_combout ), - .datad(\z80_|execute_|ctl_ir_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~17 .lut_mask = 16'h777F; -defparam \z80_|execute_|ctl_flags_alu~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~6_combout = (\z80_|execute_|ctl_flags_alu~17_combout & (((!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~9_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~15_combout ), - .datab(\z80_|execute_|ctl_ir_we~9_combout ), - .datac(\z80_|execute_|ctl_flags_alu~17_combout ), - .datad(\z80_|execute_|ctl_state_alu~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~6 .lut_mask = 16'h10F0; -defparam \z80_|execute_|ctl_flags_alu~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~6_combout = (!\z80_|ir_|opcode [6] & !\z80_|ir_|opcode [7]) - - .dataa(\z80_|ir_|opcode [6]), - .datab(gnd), - .datac(\z80_|ir_|opcode [7]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~6 .lut_mask = 16'h0505; -defparam \z80_|execute_|ctl_ir_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~8_combout = (\z80_|execute_|ctl_ir_we~5_combout & (\z80_|execute_|ctl_ir_we~6_combout & ((!\z80_|decode_state_|DFFE_instCB~q ) # (!\z80_|pla_decode_|Equal33~0_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~5_combout ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|execute_|ctl_ir_we~6_combout ), - .datad(\z80_|decode_state_|DFFE_instCB~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~8 .lut_mask = 16'h20A0; -defparam \z80_|execute_|ctl_ir_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~16 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~16_combout = (((!\z80_|execute_|ctl_ir_we~8_combout & !\z80_|execute_|ctl_ir_we~14_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M4_ff~q ) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|execute_|ctl_ir_we~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~16 .lut_mask = 16'h3F7F; -defparam \z80_|execute_|ctl_flags_alu~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~3_combout = ((!\z80_|execute_|ctl_mRead~8_combout & (!\z80_|execute_|ctl_mRead~10_combout & !\z80_|execute_|ctl_mRead~9_combout ))) # (!\z80_|execute_|ixy_d~6_combout ) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|execute_|ctl_mRead~8_combout ), - .datac(\z80_|execute_|ctl_mRead~10_combout ), - .datad(\z80_|execute_|ctl_mRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~3 .lut_mask = 16'h5557; -defparam \z80_|execute_|ctl_reg_in_hi~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~8 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~8_combout = (\z80_|execute_|ctl_flags_alu~6_combout & (\z80_|execute_|ctl_flags_alu~16_combout & \z80_|execute_|ctl_reg_in_hi~3_combout )) - - .dataa(\z80_|execute_|ctl_flags_alu~6_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_flags_alu~16_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~8 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_mWrite~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|fMRead~18 ( -// Equation(s): -// \z80_|execute_|fMRead~18_combout = (\z80_|execute_|fMRead~17_combout & (\z80_|execute_|ctl_sw_2d~4_combout & (\z80_|execute_|fMRead~16_combout & \z80_|execute_|ctl_mWrite~8_combout ))) - - .dataa(\z80_|execute_|fMRead~17_combout ), - .datab(\z80_|execute_|ctl_sw_2d~4_combout ), - .datac(\z80_|execute_|fMRead~16_combout ), - .datad(\z80_|execute_|ctl_mWrite~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~18 .lut_mask = 16'h8000; -defparam \z80_|execute_|fMRead~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N26 -cycloneive_lcell_comb \z80_|execute_|fMRead~19 ( -// Equation(s): -// \z80_|execute_|fMRead~19_combout = (\z80_|execute_|ctl_mRead~24_combout & (\z80_|execute_|ctl_reg_in_hi~6_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~6_combout & \z80_|execute_|fMRead~18_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~24_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~6_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), - .datad(\z80_|execute_|fMRead~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~19 .lut_mask = 16'h8000; -defparam \z80_|execute_|fMRead~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~16 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~16_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|execute_|ixy_d~15_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~16 .lut_mask = 16'h0F00; -defparam \z80_|execute_|ctl_alu_shift_oe~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~36 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~36_combout = (\z80_|ir_|opcode [1] & (\z80_|execute_|ctl_mWrite~2_combout & (!\z80_|ir_|opcode [2] & \z80_|ir_|opcode [0]))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~36 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_mRead~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~9_combout = (\z80_|pla_decode_|Equal1~4_combout & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [0] & \z80_|execute_|ctl_mWrite~3_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~4_combout ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|execute_|ctl_mWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~9 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_alu_op_low~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~44 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~44_combout = (!\z80_|execute_|ctl_alu_op_low~9_combout & (((!\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|execute_|ctl_mRead~36_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|execute_|ctl_mRead~36_combout ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|execute_|ctl_alu_op_low~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~44 .lut_mask = 16'h007F; -defparam \z80_|execute_|ctl_alu_shift_oe~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~11 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~11_combout = (\z80_|sequencer_|DFFE_T5_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~11 .lut_mask = 16'h00AA; -defparam \z80_|execute_|ctl_mRead~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~6 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~6_combout = (\z80_|execute_|ixy_d~6_combout & (!\z80_|pla_decode_|Equal9~1_combout & ((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_mRead~11_combout )))) # (!\z80_|execute_|ixy_d~6_combout & -// (((!\z80_|pla_decode_|Equal47~0_combout )) # (!\z80_|execute_|ctl_mRead~11_combout ))) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|execute_|ctl_mRead~11_combout ), - .datac(\z80_|pla_decode_|Equal47~0_combout ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~6 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_sw_2d~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~7 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~7_combout = (\z80_|execute_|ctl_sw_2d~6_combout & (((!\z80_|execute_|ctl_mRead~4_combout & !\z80_|pla_decode_|Equal6~1_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_sw_2d~6_combout ), - .datab(\z80_|execute_|ctl_mRead~4_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal6~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~7 .lut_mask = 16'h0A2A; -defparam \z80_|execute_|ctl_sw_2d~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~7 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~7_combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_M4_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|sequencer_|DFFE_M4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~7 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_mWrite~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~11 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~11_combout = (\z80_|ir_|opcode [6] & (!\z80_|pla_decode_|Equal46~0_combout & (!\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) - - .dataa(\z80_|ir_|opcode [6]), - .datab(\z80_|pla_decode_|Equal46~0_combout ), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|execute_|ctl_ir_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~11 .lut_mask = 16'h0200; -defparam \z80_|execute_|ctl_ir_we~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~12 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~12_combout = (\z80_|ir_|opcode [6] & (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) - - .dataa(\z80_|ir_|opcode [6]), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|execute_|ctl_ir_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~12 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_ir_we~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~0 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~0_combout = (\z80_|execute_|ctl_mWrite~7_combout & (!\z80_|execute_|ctl_ir_we~11_combout & ((!\z80_|execute_|ctl_ir_we~12_combout )))) # (!\z80_|execute_|ctl_mWrite~7_combout & (((!\z80_|execute_|ctl_ir_we~12_combout ) # -// (!\z80_|execute_|ctl_mWrite~3_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~7_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_mWrite~3_combout ), - .datad(\z80_|execute_|ctl_ir_we~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~0 .lut_mask = 16'h0577; -defparam \z80_|execute_|ctl_flags_sz_we~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout = (\z80_|pla_decode_|Equal1~4_combout & (!\z80_|ir_|opcode [0] & (\z80_|nM1_int~2_combout & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~4_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~8 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~8_combout = (\z80_|execute_|ctl_alu_shift_oe~44_combout & (\z80_|execute_|ctl_sw_2d~7_combout & (\z80_|execute_|ctl_flags_sz_we~0_combout & !\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~44_combout ), - .datab(\z80_|execute_|ctl_sw_2d~7_combout ), - .datac(\z80_|execute_|ctl_flags_sz_we~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~8 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_sw_2d~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~9 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~9_combout = (\z80_|execute_|ctl_sw_2d~5_combout & (\z80_|execute_|fMRead~19_combout & (!\z80_|execute_|ctl_alu_shift_oe~16_combout & \z80_|execute_|ctl_sw_2d~8_combout ))) - - .dataa(\z80_|execute_|ctl_sw_2d~5_combout ), - .datab(\z80_|execute_|fMRead~19_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~16_combout ), - .datad(\z80_|execute_|ctl_sw_2d~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~9 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_sw_2d~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~6 ( -// Equation(s): -// \z80_|execute_|ctl_sw_1d~6_combout = (!\z80_|execute_|ctl_im_we~combout & (!\z80_|execute_|ctl_sw_1d~5_combout & (\z80_|execute_|ctl_sw_1d~4_combout & \z80_|execute_|ctl_sw_2d~9_combout ))) - - .dataa(\z80_|execute_|ctl_im_we~combout ), - .datab(\z80_|execute_|ctl_sw_1d~5_combout ), - .datac(\z80_|execute_|ctl_sw_1d~4_combout ), - .datad(\z80_|execute_|ctl_sw_2d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~6 .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_sw_1d~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~7 ( -// Equation(s): -// \z80_|execute_|ctl_sw_1d~7_combout = ((!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & \z80_|pla_decode_|Equal47~0_combout ))) # (!\z80_|execute_|ctl_sw_1d~6_combout ) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|execute_|ctl_sw_1d~6_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~7 .lut_mask = 16'h7333; -defparam \z80_|execute_|ctl_sw_1d~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y18_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~8_combout = (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~8 .lut_mask = 16'hC0C0; -defparam \z80_|execute_|ctl_alu_op_low~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y18_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout = (\z80_|execute_|ctl_mWrite~2_combout & (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal2~0_combout & \z80_|execute_|ctl_alu_op_low~8_combout ))) - - .dataa(\z80_|execute_|ctl_mWrite~2_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|pla_decode_|Equal2~0_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|execute_|ixy_d~15_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~39 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~39_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout & (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & ((!\z80_|execute_|ctl_mRead~36_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_mRead~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~39 .lut_mask = 16'h0111; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|pla_decode_|Equal21~1_combout & !\z80_|sequencer_|DFFE_M1_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|pla_decode_|Equal21~1_combout ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 .lut_mask = 16'h0088; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_hi~4_combout = ((!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal40~1_combout & !\z80_|pla_decode_|Equal39~0_combout ))) # (!\z80_|execute_|ixy_d~9_combout ) - - .dataa(\z80_|execute_|ixy_d~9_combout ), - .datab(\z80_|pla_decode_|Equal21~1_combout ), - .datac(\z80_|pla_decode_|Equal40~1_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_hi~4 .lut_mask = 16'h5557; -defparam \z80_|execute_|ctl_reg_out_hi~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~15 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~15_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal6~0_combout & (!\z80_|pla_decode_|Equal33~1_combout & \z80_|pla_decode_|Equal3~1_combout ))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|pla_decode_|Equal33~1_combout ), - .datad(\z80_|pla_decode_|Equal3~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~15 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_alu_shift_oe~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~38 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~38_combout = (!\z80_|execute_|ctl_alu_shift_oe~15_combout & (((!\z80_|execute_|ctl_state_alu~4_combout & !\z80_|execute_|ctl_state_alu~6_combout )) # (!\z80_|execute_|ctl_mRead~6_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~38 .lut_mask = 16'h0037; -defparam \z80_|execute_|ctl_alu_shift_oe~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_zero ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_zero~combout = ((\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~38_combout ) # (!\z80_|execute_|ctl_reg_out_hi~4_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), - .datac(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_zero .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_alu_op2_sel_zero .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N14 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~4 ( -// Equation(s): -// \z80_|alu_|db_low[2]~4_combout = ((\z80_|bus_control_|db[4]~19_combout & (!\z80_|bus_control_|db[5]~15_combout & !\z80_|bus_control_|db[3]~21_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datab(\z80_|bus_control_|db[4]~19_combout ), - .datac(\z80_|bus_control_|db[5]~15_combout ), - .datad(\z80_|bus_control_|db[3]~21_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~4 .lut_mask = 16'h555D; -defparam \z80_|alu_|db_low[2]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~14_combout = (\z80_|sequencer_|DFFE_M4_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~14 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_alu_shift_oe~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~11 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[0]~11_combout = ((!\z80_|pla_decode_|Equal40~1_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal39~0_combout ))) # (!\z80_|execute_|ixy_d~5_combout ) - - .dataa(\z80_|pla_decode_|Equal40~1_combout ), - .datab(\z80_|pla_decode_|Equal21~1_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~11 .lut_mask = 16'h0F1F; -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~1 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~1_combout = (\z80_|execute_|ctl_reg_out_hi~4_combout & \z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~1 .lut_mask = 16'hCC00; -defparam \z80_|execute_|ctl_sw_4u~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~5_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout & (((!\z80_|pla_decode_|Equal21~1_combout & !\z80_|execute_|ctl_mRead~36_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), - .datab(\z80_|pla_decode_|Equal21~1_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_mRead~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~5 .lut_mask = 16'h0515; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~30 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~30_combout = (\z80_|execute_|ctl_sw_4u~1_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~5_combout & ((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|execute_|ctl_sw_4u~1_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~30 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_alu_shift_oe~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~29 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~29_combout = (\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|execute_|ctl_mRead~36_combout & ((!\z80_|execute_|ctl_mWrite~3_combout ) # (!\z80_|execute_|ctl_mWrite~16_combout )))) # -// (!\z80_|execute_|ctl_state_alu~4_combout & (((!\z80_|execute_|ctl_mWrite~3_combout )) # (!\z80_|execute_|ctl_mWrite~16_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_mWrite~16_combout ), - .datac(\z80_|execute_|ctl_mRead~36_combout ), - .datad(\z80_|execute_|ctl_mWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~29 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_alu_shift_oe~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~31 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~31_combout = (\z80_|execute_|ctl_alu_shift_oe~30_combout & (\z80_|execute_|ctl_alu_shift_oe~29_combout & ((!\z80_|execute_|ctl_mRead~11_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~30_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~29_combout ), - .datad(\z80_|execute_|ctl_mRead~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~31 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_alu_shift_oe~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal69~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal69~0_combout = (!\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|pla_decode_|Equal13~1_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal69~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal69~0 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal69~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N24 -cycloneive_lcell_comb \z80_|pla_decode_|Equal1~5 ( -// Equation(s): -// \z80_|pla_decode_|Equal1~5_combout = (\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [5]) - - .dataa(\z80_|ir_|opcode [4]), - .datab(gnd), - .datac(gnd), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal1~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal1~5 .lut_mask = 16'h00AA; -defparam \z80_|pla_decode_|Equal1~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~14_combout = (\z80_|pla_decode_|Equal1~5_combout & (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~5_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|pla_decode_|Equal13~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~14 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_op_low~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~12 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~12_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal2~0_combout & (!\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal2~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~12 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_alu_op_low~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal56~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal56~0_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal1~4_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal1~4_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal56~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal56~0 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal56~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~11_combout = (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~11 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_alu_op_low~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|nextM~2 ( -// Equation(s): -// \z80_|execute_|nextM~2_combout = (!\z80_|execute_|ctl_alu_op_low~12_combout & (!\z80_|pla_decode_|Equal56~0_combout & !\z80_|execute_|ctl_alu_op_low~11_combout )) - - .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_alu_op_low~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~2 .lut_mask = 16'h0011; -defparam \z80_|execute_|nextM~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~16 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~16_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # ((\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T3_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|execute_|nextM~2_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~16 .lut_mask = 16'h0F08; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~4_combout = (!\z80_|execute_|ctl_alu_op_low~14_combout & (!\z80_|execute_|ctl_alu_op1_sel_bus~16_combout & ((!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # (!\z80_|pla_decode_|Equal69~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal69~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~4 .lut_mask = 16'h0103; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~5_combout = (\z80_|execute_|ctl_alu_shift_oe~38_combout & \z80_|execute_|ctl_alu_op1_sel_bus~4_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~5 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~3 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~3_combout = (\z80_|pla_decode_|Equal77~0_combout & ((\z80_|decode_state_|in_halt~q ) # ((!\z80_|pla_decode_|Equal33~1_combout & !\z80_|pla_decode_|Equal33~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|decode_state_|in_halt~q ), - .datac(\z80_|pla_decode_|Equal77~0_combout ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~3 .lut_mask = 16'hC0D0; -defparam \z80_|execute_|ctl_alu_oe~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~15 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~15_combout = ((!\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|execute_|ixy_d~15_combout ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|execute_|ixy_d~15_combout ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~15 .lut_mask = 16'h0F3F; -defparam \z80_|execute_|ctl_alu_op_low~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~8_combout = (\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|execute_|ctl_ir_we~7_combout & ((!\z80_|execute_|ctl_ir_we~10_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) # -// (!\z80_|execute_|ctl_state_alu~4_combout & (((!\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_ir_we~7_combout ), - .datad(\z80_|execute_|ctl_ir_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~8 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~9_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~8_combout & (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_ir_we~10_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~9 .lut_mask = 16'h1F00; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~3 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~3_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|execute_|ctl_ir_we~9_combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_ir_we~15_combout )))) # -// (!\z80_|execute_|ctl_eval_cond~0_combout & (((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_ir_we~15_combout )))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|ctl_ir_we~9_combout ), - .datac(\z80_|execute_|ctl_ir_we~15_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~3 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_alu_core_R~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~4_combout = (\z80_|execute_|ctl_alu_core_R~3_combout & (((!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~9_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~15_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~3_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_ir_we~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~4 .lut_mask = 16'h0C4C; -defparam \z80_|execute_|ctl_alu_core_R~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|execute_|ctl_ir_we~11_combout )) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|execute_|ctl_ir_we~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 .lut_mask = 16'h3000; -defparam \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~10_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~9_combout & (\z80_|execute_|ctl_flags_sz_we~0_combout & (\z80_|execute_|ctl_alu_core_R~4_combout & !\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout -// ))) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~0_combout ), - .datac(\z80_|execute_|ctl_alu_core_R~4_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~10 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~11_combout = (((\z80_|execute_|ctl_alu_oe~3_combout & \z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~10_combout )) # (!\z80_|execute_|ctl_alu_op_low~15_combout ) - - .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~15_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~11 .lut_mask = 16'h8FFF; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal48~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal48~0_combout = (!\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|pla_decode_|Equal13~1_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal48~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal48~0 .lut_mask = 16'h1000; -defparam \z80_|pla_decode_|Equal48~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf2_we ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf2_we~combout = (\z80_|pla_decode_|Equal63~0_combout & (!\z80_|ir_|opcode [4] & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & !\z80_|ir_|opcode [3]))) - - .dataa(\z80_|pla_decode_|Equal63~0_combout ), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf2_we~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf2_we .lut_mask = 16'h0020; -defparam \z80_|execute_|ctl_flags_hf2_we .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~41 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~41_combout = (!\z80_|execute_|ctl_flags_hf2_we~combout & (((!\z80_|pla_decode_|Equal10~0_combout & !\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|execute_|ctl_flags_hf2_we~combout ), - .datad(\z80_|pla_decode_|Equal11~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~41 .lut_mask = 16'h0307; -defparam \z80_|execute_|ctl_alu_shift_oe~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~18 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~18_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|pla_decode_|Equal44~0_combout & !\z80_|pla_decode_|Equal52~1_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|pla_decode_|Equal44~0_combout ), - .datad(\z80_|pla_decode_|Equal52~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~18 .lut_mask = 16'hBBBF; -defparam \z80_|execute_|ctl_flags_xy_we~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~17 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~17_combout = ((!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal35~0_combout & !\z80_|pla_decode_|Equal39~0_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|pla_decode_|Equal21~1_combout ), - .datac(\z80_|pla_decode_|Equal35~0_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~17 .lut_mask = 16'h5557; -defparam \z80_|execute_|ctl_alu_shift_oe~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~19 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~19_combout = (\z80_|pla_decode_|Equal40~1_combout ) # ((\z80_|pla_decode_|Equal37~0_combout ) # ((\z80_|pla_decode_|Equal41~2_combout ) # (\z80_|pla_decode_|Equal34~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal40~1_combout ), - .datab(\z80_|pla_decode_|Equal37~0_combout ), - .datac(\z80_|pla_decode_|Equal41~2_combout ), - .datad(\z80_|pla_decode_|Equal34~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~19 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_alu_shift_oe~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_iorw~10 ( -// Equation(s): -// \z80_|execute_|ctl_iorw~10_combout = (!\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [2] & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_iorw~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_iorw~10 .lut_mask = 16'h0100; -defparam \z80_|execute_|ctl_iorw~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~18 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~18_combout = ((!\z80_|execute_|ctl_mWrite~16_combout & (!\z80_|execute_|ctl_mRead~36_combout & !\z80_|execute_|ctl_iorw~10_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) - - .dataa(\z80_|execute_|ctl_mWrite~16_combout ), - .datab(\z80_|execute_|ctl_mRead~36_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_iorw~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~18 .lut_mask = 16'h0F1F; -defparam \z80_|execute_|ctl_alu_shift_oe~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~20 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~20_combout = (\z80_|execute_|ctl_alu_shift_oe~17_combout & (\z80_|execute_|ctl_alu_shift_oe~18_combout & ((!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # (!\z80_|execute_|ctl_alu_shift_oe~19_combout )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~17_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~19_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~20 .lut_mask = 16'h2A00; -defparam \z80_|execute_|ctl_alu_shift_oe~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~13 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~13_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~12_combout ))) # (!\z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|execute_|ctl_ir_we~9_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|ctl_ir_we~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~13 .lut_mask = 16'hF5F7; -defparam \z80_|execute_|ctl_alu_bs_oe~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~9_combout = (\z80_|execute_|ctl_alu_bs_oe~13_combout & (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|execute_|ctl_alu_bs_oe~13_combout ), - .datac(\z80_|execute_|ctl_ir_we~10_combout ), - .datad(\z80_|execute_|ctl_ir_we~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~9 .lut_mask = 16'h444C; -defparam \z80_|execute_|ctl_alu_bs_oe~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~3 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~3_combout = (\z80_|execute_|ctl_alu_bs_oe~9_combout & (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~11_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~9_combout ), - .datad(\z80_|execute_|ctl_ir_we~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~3 .lut_mask = 16'h3070; -defparam \z80_|execute_|ctl_bus_db_oe~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N26 -cycloneive_lcell_comb \z80_|pla_decode_|Equal20~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal20~0_combout = (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [5] & (\z80_|execute_|comb~0_combout & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|execute_|comb~0_combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal20~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal20~0 .lut_mask = 16'h2000; -defparam \z80_|pla_decode_|Equal20~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal68~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal68~2_combout = (!\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [2] & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal68~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal68~2 .lut_mask = 16'h1000; -defparam \z80_|pla_decode_|Equal68~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~14 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~14_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal20~0_combout & !\z80_|pla_decode_|Equal68~2_combout ))) # (!\z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|pla_decode_|Equal20~0_combout ), - .datab(\z80_|pla_decode_|Equal68~2_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~14 .lut_mask = 16'hFF1F; -defparam \z80_|execute_|ctl_flags_bus~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~13 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~13_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal3~1_combout & ((!\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal21~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal21~0_combout ), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|pla_decode_|Equal3~1_combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~13 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_alu_op_low~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~15 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~15_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|execute_|ctl_alu_op_low~13_combout & !\z80_|execute_|ctl_alu_op_low~12_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|execute_|ctl_alu_op_low~13_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~15 .lut_mask = 16'hBBBF; -defparam \z80_|execute_|ctl_flags_bus~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~11_combout = (\z80_|execute_|ctl_flags_bus~15_combout & (((!\z80_|execute_|ctl_ir_we~14_combout & !\z80_|execute_|ctl_ir_we~8_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|execute_|ctl_ir_we~14_combout ), - .datac(\z80_|execute_|ctl_ir_we~8_combout ), - .datad(\z80_|execute_|ctl_flags_bus~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~11 .lut_mask = 16'h5700; -defparam \z80_|execute_|ctl_flags_bus~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N20 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~11 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~11_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|pla_decode_|Equal56~0_combout & !\z80_|execute_|ctl_alu_op_low~11_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|execute_|ctl_alu_op_low~11_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~11 .lut_mask = 16'hAFBF; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~10_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~11_combout & (((!\z80_|pla_decode_|Equal21~0_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )) # (!\z80_|pla_decode_|Equal63~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal63~0_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~11_combout ), - .datad(\z80_|pla_decode_|Equal21~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~10 .lut_mask = 16'h70F0; -defparam \z80_|execute_|ctl_flags_bus~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~8_combout = (\z80_|execute_|ixy_d~10_combout ) # ((\z80_|pla_decode_|Equal63~0_combout & ((\z80_|pla_decode_|Equal3~0_combout ) # (\z80_|pla_decode_|Equal32~0_combout )))) - - .dataa(\z80_|execute_|ixy_d~10_combout ), - .datab(\z80_|pla_decode_|Equal63~0_combout ), - .datac(\z80_|pla_decode_|Equal3~0_combout ), - .datad(\z80_|pla_decode_|Equal32~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~8 .lut_mask = 16'hEEEA; -defparam \z80_|execute_|ctl_flags_bus~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~9_combout = ((!\z80_|pla_decode_|Equal13~2_combout & (!\z80_|execute_|ctl_mRead~6_combout & !\z80_|execute_|ctl_flags_bus~8_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|execute_|ctl_mRead~6_combout ), - .datad(\z80_|execute_|ctl_flags_bus~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~9 .lut_mask = 16'h3337; -defparam \z80_|execute_|ctl_flags_bus~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~12 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~12_combout = (\z80_|execute_|ctl_flags_bus~14_combout & (\z80_|execute_|ctl_flags_bus~11_combout & (\z80_|execute_|ctl_flags_bus~10_combout & \z80_|execute_|ctl_flags_bus~9_combout ))) - - .dataa(\z80_|execute_|ctl_flags_bus~14_combout ), - .datab(\z80_|execute_|ctl_flags_bus~11_combout ), - .datac(\z80_|execute_|ctl_flags_bus~10_combout ), - .datad(\z80_|execute_|ctl_flags_bus~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~12 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_bus~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~11_combout = (\z80_|execute_|ctl_flags_xy_we~18_combout & (\z80_|execute_|ctl_alu_shift_oe~20_combout & (\z80_|execute_|ctl_bus_db_oe~3_combout & \z80_|execute_|ctl_flags_bus~12_combout ))) - - .dataa(\z80_|execute_|ctl_flags_xy_we~18_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~20_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~3_combout ), - .datad(\z80_|execute_|ctl_flags_bus~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~11 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_xy_we~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~12 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~12_combout = (\z80_|execute_|ctl_alu_shift_oe~41_combout & (\z80_|execute_|ctl_flags_xy_we~11_combout & ((!\z80_|execute_|ctl_state_alu~14_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~41_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~11_combout ), - .datad(\z80_|execute_|ctl_state_alu~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~12 .lut_mask = 16'h20A0; -defparam \z80_|execute_|ctl_flags_xy_we~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~6_combout = (\z80_|execute_|ctl_mWrite~3_combout & (!\z80_|execute_|ctl_ir_we~14_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|execute_|ctl_ir_we~8_combout )))) # -// (!\z80_|execute_|ctl_mWrite~3_combout & (((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|execute_|ctl_ir_we~8_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~3_combout ), - .datab(\z80_|execute_|ctl_ir_we~14_combout ), - .datac(\z80_|execute_|ctl_ir_we~8_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~6 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~7 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~7_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~6_combout & (\z80_|execute_|ctl_flags_alu~16_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal20~0_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ), - .datac(\z80_|execute_|ctl_flags_alu~16_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~7 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~4_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M4_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~4 .lut_mask = 16'h3030; -defparam \z80_|execute_|ctl_ir_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~8_combout = ((!\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~9_combout ))) # (!\z80_|execute_|ctl_ir_we~4_combout ) - - .dataa(\z80_|execute_|ctl_ir_we~12_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_ir_we~9_combout ), - .datad(\z80_|execute_|ctl_ir_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~8 .lut_mask = 16'h01FF; -defparam \z80_|execute_|ctl_alu_bs_oe~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~0_combout = (\z80_|execute_|ctl_alu_bs_oe~8_combout & (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_ir_we~10_combout ), - .datad(\z80_|execute_|ctl_alu_bs_oe~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~0 .lut_mask = 16'h3700; -defparam \z80_|execute_|ctl_bus_db_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~12 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~12_combout = (!\z80_|execute_|ctl_alu_op_low~9_combout & (((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|pla_decode_|Equal41~2_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~9_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|pla_decode_|Equal41~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~12 .lut_mask = 16'h0515; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~13 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~13_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~7_combout & (\z80_|execute_|ctl_bus_db_oe~0_combout & \z80_|execute_|ctl_alu_op1_sel_bus~12_combout )) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_bus_db_oe~0_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~13 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~14_combout = (\z80_|execute_|ctl_flags_xy_we~12_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~13_combout & ((!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # (!\z80_|pla_decode_|Equal48~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal48~0_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~12_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~14 .lut_mask = 16'h4C00; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~15 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~15_combout = (((\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ) # (!\z80_|execute_|ctl_alu_op1_sel_bus~14_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~5_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~31_combout ) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~31_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~5_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~15 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_66_oe~2 ( -// Equation(s): -// \z80_|execute_|ctl_66_oe~2_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|execute_|comb~0_combout & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal52~0_combout ), - .datac(\z80_|execute_|comb~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_66_oe~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_66_oe~2 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_66_oe~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla11M1T1_11 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|pla_decode_|Equal10~0_combout )) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal10~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel_pla11M1T1_11 .lut_mask = 16'h1100; -defparam \z80_|execute_|ctl_pf_sel_pla11M1T1_11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_zero~5_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal63~0_combout & (\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4]))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|pla_decode_|Equal63~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_zero~5 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_alu_op1_sel_zero~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_zero~4_combout = (\z80_|pla_decode_|Equal3~1_combout & (!\z80_|ir_|opcode [0] & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_zero~4 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_alu_op1_sel_zero~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_zero~combout = (\z80_|execute_|ctl_66_oe~2_combout ) # ((\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ) # (\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ))) - - .dataa(\z80_|execute_|ctl_66_oe~2_combout ), - .datab(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_zero .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_alu_op1_sel_zero .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N16 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[2] ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_high|Q [2] = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & (\z80_|alu_|db_high[2]~14_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .datac(\z80_|alu_|db_high[2]~14_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [2]), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[2] .lut_mask = 16'h00C0; -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N2 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|ena~0 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ) # (\z80_|execute_|ctl_alu_op1_sel_zero~combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_high|ena~0 .lut_mask = 16'hFFF0; -defparam \z80_|alu_|b2v_op1_latch_mux_high|ena~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y10_N17 -dffeas \z80_|alu_|op1_high[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [2]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_high [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_high[2] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_high[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_lq ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_lq~combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ixy_d~7_combout ) # ((\z80_|execute_|ixy_d~6_combout & !\z80_|ir_|opcode [3])))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|pla_decode_|Equal13~2_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_lq .lut_mask = 16'h88C8; -defparam \z80_|execute_|ctl_alu_op2_sel_lq .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~10_combout = (((!\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [3])) # (!\z80_|pla_decode_|Equal63~0_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal63~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~10 .lut_mask = 16'h1FFF; -defparam \z80_|execute_|ctl_alu_op_low~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N28 -cycloneive_lcell_comb \z80_|execute_|fMWrite~11 ( -// Equation(s): -// \z80_|execute_|fMWrite~11_combout = ((!\z80_|pla_decode_|Equal13~2_combout ) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|pla_decode_|Equal13~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~11 .lut_mask = 16'h5FFF; -defparam \z80_|execute_|fMWrite~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~21 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~21_combout = ((\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # (\z80_|execute_|ctl_alu_op_low~9_combout ))) # (!\z80_|execute_|fMWrite~11_combout ) - - .dataa(\z80_|execute_|fMWrite~11_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~21 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_alu_op_low~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N4 +// Location: LCCOMB_X21_Y12_N24 cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~22 ( // Equation(s): -// \z80_|execute_|ctl_alu_op_low~22_combout = ((\z80_|execute_|ctl_alu_op_low~21_combout ) # (!\z80_|execute_|ctl_alu_op1_sel_bus~10_combout )) # (!\z80_|execute_|ctl_alu_op_low~10_combout ) +// \z80_|execute_|ctl_alu_op_low~22_combout = (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ) - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op_low~10_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~21_combout ), + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), .cin(gnd), .combout(\z80_|execute_|ctl_alu_op_low~22_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~22 .lut_mask = 16'hFF3F; +defparam \z80_|execute_|ctl_alu_op_low~22 .lut_mask = 16'hAA00; defparam \z80_|execute_|ctl_alu_op_low~22 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y14_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~16 ( +// Location: LCCOMB_X26_Y16_N30 +cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_11 ( // Equation(s): -// \z80_|execute_|ctl_alu_op_low~16_combout = ((!\z80_|execute_|ixy_d~7_combout & ((\z80_|ir_|opcode [3]) # (!\z80_|execute_|ixy_d~6_combout )))) # (!\z80_|pla_decode_|Equal13~2_combout ) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|pla_decode_|Equal13~2_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~16 .lut_mask = 16'h7737; -defparam \z80_|execute_|ctl_alu_op_low~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~17 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~17_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~7_combout & (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & \z80_|execute_|ctl_alu_op_low~16_combout )) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), - .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_alu_op_low~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~17 .lut_mask = 16'h2200; -defparam \z80_|execute_|ctl_alu_op_low~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout = (!\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal44~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T4_ff~q ))) - - .dataa(\z80_|pla_decode_|Equal33~0_combout ), - .datab(\z80_|pla_decode_|Equal44~0_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel~36 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel~36_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|sequencer_|DFFE_T4_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|pla_decode_|Equal52~0_combout ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel~36 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_gp_sel~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~4_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout & (\z80_|execute_|ctl_state_alu~8_combout & (!\z80_|execute_|ctl_reg_gp_sel~36_combout & \z80_|execute_|ctl_alu_op2_sel_bus~9_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), - .datab(\z80_|execute_|ctl_state_alu~8_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel~36_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~4 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~5 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~5_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ) +// \z80_|resets_|SYNTHESIZED_WIRE_11~combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T2_ff~q ) .dataa(gnd), .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~5 .lut_mask = 16'h0F00; -defparam \z80_|execute_|ctl_state_alu~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~18 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~18_combout = (\z80_|execute_|ctl_mWrite~3_combout & ((\z80_|pla_decode_|Equal56~0_combout ) # ((\z80_|execute_|ctl_alu_op_low~11_combout )))) # (!\z80_|execute_|ctl_mWrite~3_combout & -// (\z80_|execute_|ctl_state_alu~5_combout & ((\z80_|pla_decode_|Equal56~0_combout ) # (\z80_|execute_|ctl_alu_op_low~11_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~3_combout ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|execute_|ctl_state_alu~5_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~18 .lut_mask = 16'hFAC8; -defparam \z80_|execute_|ctl_alu_op_low~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~19 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~19_combout = ((\z80_|execute_|ctl_alu_op_low~14_combout ) # ((\z80_|execute_|ctl_alu_op_low~18_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~38_combout ))) # (!\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~19 .lut_mask = 16'hFFDF; -defparam \z80_|execute_|ctl_alu_op_low~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~33 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~33_combout = (((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|execute_|ctl_alu_op_low~12_combout ) - - .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~33 .lut_mask = 16'h77F7; -defparam \z80_|execute_|ctl_alu_op_low~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~20 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~20_combout = (\z80_|execute_|ctl_alu_op_low~19_combout ) # (!\z80_|execute_|ctl_alu_op_low~33_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_op_low~19_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~33_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~20 .lut_mask = 16'hF0FF; -defparam \z80_|execute_|ctl_alu_op_low~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~23 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~23_combout = (\z80_|execute_|ctl_mRead~36_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout )))) # (!\z80_|execute_|ctl_mRead~36_combout & (\z80_|execute_|ixy_d~5_combout & -// ((\z80_|pla_decode_|Equal39~0_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~36_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~23 .lut_mask = 16'hECA8; -defparam \z80_|execute_|ctl_alu_op_low~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~24 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~24_combout = (\z80_|execute_|ctl_alu_op_low~22_combout ) # (((\z80_|execute_|ctl_alu_op_low~20_combout ) # (\z80_|execute_|ctl_alu_op_low~23_combout )) # (!\z80_|execute_|ctl_alu_op_low~17_combout )) - - .dataa(\z80_|execute_|ctl_alu_op_low~22_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~20_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~23_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~24 .lut_mask = 16'hFFFB; -defparam \z80_|execute_|ctl_alu_op_low~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~25 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~25_combout = (\z80_|execute_|ixy_d~9_combout & (((\z80_|pla_decode_|Equal40~1_combout ) # (\z80_|pla_decode_|Equal39~0_combout )))) # (!\z80_|execute_|ixy_d~9_combout & (\z80_|execute_|ixy_d~5_combout & -// (\z80_|pla_decode_|Equal40~1_combout ))) - - .dataa(\z80_|execute_|ixy_d~9_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|pla_decode_|Equal40~1_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~25 .lut_mask = 16'hEAE0; -defparam \z80_|execute_|ctl_alu_op_low~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~34 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~34_combout = (\z80_|execute_|ctl_alu_op_low~25_combout ) # ((\z80_|pla_decode_|Equal21~1_combout & (\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ))) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|ctl_alu_op_low~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~34 .lut_mask = 16'hFF08; -defparam \z80_|execute_|ctl_alu_op_low~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~combout = ((\z80_|execute_|ctl_alu_op_low~24_combout ) # ((\z80_|execute_|ctl_alu_op_low~34_combout ) # (\z80_|execute_|ctl_alu_op_low~26_combout ))) # (!\z80_|execute_|ctl_alu_op_low~15_combout ) - - .dataa(\z80_|execute_|ctl_alu_op_low~15_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~24_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~34_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~26_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_alu_op_low .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~40 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~40_combout = ((\z80_|execute_|ixy_d~9_combout & ((\z80_|execute_|ctl_mRead~26_combout ) # (\z80_|execute_|ctl_mRead~27_combout )))) # (!\z80_|execute_|ctl_flags_xy_we~18_combout ) - - .dataa(\z80_|execute_|ctl_mRead~26_combout ), - .datab(\z80_|execute_|ctl_mRead~27_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~18_combout ), - .datad(\z80_|execute_|ixy_d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~40 .lut_mask = 16'hEF0F; -defparam \z80_|execute_|ctl_alu_shift_oe~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~37 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~37_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_alu_oe~3_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) - - .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~37 .lut_mask = 16'hAE00; -defparam \z80_|execute_|ctl_alu_shift_oe~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~39 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~39_combout = (\z80_|execute_|ctl_alu_shift_oe~37_combout ) # (((\z80_|execute_|ctl_state_alu~14_combout & \z80_|execute_|ctl_alu_shift_oe~14_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~5_combout )) - - .dataa(\z80_|execute_|ctl_state_alu~14_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~37_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~39 .lut_mask = 16'hECFF; -defparam \z80_|execute_|ctl_alu_shift_oe~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~46 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~46_combout = (\z80_|execute_|ctl_alu_shift_oe~41_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|pla_decode_|Equal48~0_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~41_combout ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|pla_decode_|Equal48~0_combout ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), .datad(\z80_|sequencer_|DFFE_M1_ff~q ), .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~46_combout ), + .combout(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~46 .lut_mask = 16'hAA2A; -defparam \z80_|execute_|ctl_alu_shift_oe~46 .sum_lutc_input = "datac"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_11 .lut_mask = 16'hFF0F; +defparam \z80_|resets_|SYNTHESIZED_WIRE_11 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X40_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~42 ( +// Location: LCCOMB_X31_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~4 ( // Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~42_combout = (\z80_|execute_|ctl_alu_shift_oe~40_combout ) # (((\z80_|execute_|ctl_alu_shift_oe~39_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~46_combout )) # (!\z80_|execute_|ctl_alu_op_low~17_combout )) +// \z80_|execute_|ctl_ir_we~4_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M4_ff~q ) - .dataa(\z80_|execute_|ctl_alu_shift_oe~40_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~39_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~46_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~42 .lut_mask = 16'hFBFF; -defparam \z80_|execute_|ctl_alu_shift_oe~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~21 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~21_combout = (\z80_|execute_|ctl_ir_we~15_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # ((\z80_|execute_|ctl_state_alu~6_combout & !\z80_|execute_|ctl_ir_we~4_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~6_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_ir_we~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~21 .lut_mask = 16'hF200; -defparam \z80_|execute_|ctl_alu_shift_oe~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~45 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~45_combout = (\z80_|execute_|ctl_alu_shift_oe~21_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|execute_|ctl_alu_shift_oe~21_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|ctl_ir_we~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~45 .lut_mask = 16'hC4CC; -defparam \z80_|execute_|ctl_alu_shift_oe~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~22 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~22_combout = (\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_state_alu~6_combout ) # (\z80_|execute_|ctl_alu_shift_oe~45_combout )))) # -// (!\z80_|execute_|ctl_ir_we~9_combout & (((\z80_|execute_|ctl_alu_shift_oe~45_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~6_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_ir_we~9_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~45_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~22 .lut_mask = 16'h3F20; -defparam \z80_|execute_|ctl_alu_shift_oe~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~23 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~23_combout = (\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # (\z80_|execute_|ctl_alu_shift_oe~22_combout )))) # -// (!\z80_|execute_|ctl_ir_we~9_combout & (((\z80_|execute_|ctl_alu_shift_oe~22_combout )))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~22_combout ), - .datac(\z80_|execute_|ctl_ir_we~9_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~23 .lut_mask = 16'h0CEC; -defparam \z80_|execute_|ctl_alu_shift_oe~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~24 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~24_combout = (\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_mWrite~7_combout ) # (\z80_|execute_|ctl_alu_shift_oe~23_combout )))) # -// (!\z80_|execute_|ctl_ir_we~12_combout & (((\z80_|execute_|ctl_alu_shift_oe~23_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~7_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~23_combout ), - .datad(\z80_|execute_|ctl_ir_we~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~24 .lut_mask = 16'h32F0; -defparam \z80_|execute_|ctl_alu_shift_oe~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~25 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~25_combout = (\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|execute_|ctl_alu_shift_oe~24_combout ) # (\z80_|execute_|ctl_mWrite~3_combout )))) # -// (!\z80_|execute_|ctl_ir_we~12_combout & (\z80_|execute_|ctl_alu_shift_oe~24_combout )) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~24_combout ), - .datab(\z80_|execute_|ctl_ir_we~12_combout ), - .datac(\z80_|execute_|ctl_mWrite~3_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~25 .lut_mask = 16'h22EA; -defparam \z80_|execute_|ctl_alu_shift_oe~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~14_combout = (\z80_|execute_|ctl_ir_we~11_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # ((\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~14 .lut_mask = 16'hC0C8; -defparam \z80_|execute_|ctl_alu_bs_oe~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~26 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~26_combout = (!\z80_|execute_|ctl_alu_bs_oe~14_combout & ((\z80_|execute_|ctl_alu_shift_oe~25_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout & \z80_|execute_|ctl_mWrite~7_combout )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~25_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_mWrite~7_combout ), - .datad(\z80_|execute_|ctl_alu_bs_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~26 .lut_mask = 16'h00EA; -defparam \z80_|execute_|ctl_alu_shift_oe~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~27 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~27_combout = (\z80_|execute_|ctl_ir_we~7_combout & ((\z80_|execute_|ctl_state_alu~6_combout ) # ((\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ctl_bus_db_oe~1_combout )))) # (!\z80_|execute_|ctl_ir_we~7_combout & -// (\z80_|execute_|ixy_d~7_combout & ((!\z80_|execute_|ctl_bus_db_oe~1_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~27 .lut_mask = 16'hA0EC; -defparam \z80_|execute_|ctl_alu_shift_oe~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~28 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~28_combout = ((\z80_|execute_|ctl_alu_shift_oe~27_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~20_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~44_combout ) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~44_combout ), + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), .datab(gnd), - .datac(\z80_|execute_|ctl_alu_shift_oe~20_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~27_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~28 .lut_mask = 16'hFF5F; -defparam \z80_|execute_|ctl_alu_shift_oe~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~10_combout = (\z80_|execute_|ctl_ir_we~7_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) # (!\z80_|execute_|ctl_ir_we~7_combout & (\z80_|execute_|ctl_ir_we~4_combout -// & (\z80_|execute_|ctl_ir_we~10_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_ir_we~10_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~10 .lut_mask = 16'hEAC8; -defparam \z80_|execute_|ctl_alu_bs_oe~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~11_combout = (\z80_|execute_|ctl_alu_bs_oe~10_combout ) # ((\z80_|execute_|ctl_alu_bs_oe~14_combout ) # ((!\z80_|execute_|ctl_alu_bs_oe~8_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~9_combout ))) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~10_combout ), - .datab(\z80_|execute_|ctl_alu_bs_oe~14_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~9_combout ), - .datad(\z80_|execute_|ctl_alu_bs_oe~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~11 .lut_mask = 16'hEFFF; -defparam \z80_|execute_|ctl_alu_bs_oe~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~32 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~32_combout = (!\z80_|execute_|ctl_alu_bs_oe~11_combout & ((\z80_|execute_|ctl_alu_shift_oe~28_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~31_combout ))) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_shift_oe~28_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~31_combout ), - .datad(\z80_|execute_|ctl_alu_bs_oe~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~32 .lut_mask = 16'h00CF; -defparam \z80_|execute_|ctl_alu_shift_oe~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~33 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~33_combout = (\z80_|execute_|ctl_alu_shift_oe~32_combout ) # ((!\z80_|execute_|ctl_alu_bs_oe~combout & ((\z80_|execute_|ctl_alu_shift_oe~16_combout ) # (!\z80_|execute_|ctl_alu_op_low~15_combout )))) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datab(\z80_|execute_|ctl_alu_op_low~15_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~16_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~33 .lut_mask = 16'hFF51; -defparam \z80_|execute_|ctl_alu_shift_oe~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~0_combout = ((!\z80_|execute_|ctl_alu_op_low~12_combout & (!\z80_|execute_|ctl_alu_op_low~11_combout & !\z80_|pla_decode_|Equal56~0_combout ))) # (!\z80_|execute_|ctl_state_alu~5_combout ) - - .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~11_combout ), - .datac(\z80_|execute_|ctl_state_alu~5_combout ), - .datad(\z80_|pla_decode_|Equal56~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~0 .lut_mask = 16'h0F1F; -defparam \z80_|execute_|ctl_reg_use_sp~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~1 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~1_combout = (\z80_|execute_|ctl_reg_use_sp~0_combout & \z80_|execute_|nextM~11_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_use_sp~0_combout ), .datac(gnd), - .datad(\z80_|execute_|nextM~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~1 .lut_mask = 16'hCC00; -defparam \z80_|execute_|ctl_reg_use_sp~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~12 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~12_combout = (\z80_|execute_|ctl_alu_bs_oe~14_combout ) # ((!\z80_|execute_|ctl_alu_bs_oe~8_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~9_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_bs_oe~14_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~9_combout ), - .datad(\z80_|execute_|ctl_alu_bs_oe~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~12 .lut_mask = 16'hCFFF; -defparam \z80_|execute_|ctl_alu_bs_oe~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~47 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~47_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|sequencer_|DFFE_M1_ff~q & \z80_|execute_|ctl_ir_we~7_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|ctl_ir_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~47 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_shift_oe~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~34 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~34_combout = (\z80_|execute_|ctl_ir_we~10_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_state_alu~6_combout ) # (\z80_|execute_|ctl_alu_shift_oe~47_combout )))) # -// (!\z80_|execute_|ctl_ir_we~10_combout & (((\z80_|execute_|ctl_alu_shift_oe~47_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~6_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_ir_we~10_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~47_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~34 .lut_mask = 16'h3F20; -defparam \z80_|execute_|ctl_alu_shift_oe~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~35 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~35_combout = (!\z80_|execute_|ctl_alu_bs_oe~12_combout & ((\z80_|execute_|ctl_alu_shift_oe~34_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & \z80_|execute_|ctl_ir_we~10_combout )))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|ctl_ir_we~10_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~12_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~34_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~35 .lut_mask = 16'h0F08; -defparam \z80_|execute_|ctl_alu_shift_oe~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~36 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~36_combout = (((\z80_|execute_|ctl_alu_shift_oe~35_combout ) # (!\z80_|execute_|ctl_reg_use_sp~1_combout )) # (!\z80_|execute_|ctl_flags_bus~12_combout )) # (!\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ), - .datab(\z80_|execute_|ctl_flags_bus~12_combout ), - .datac(\z80_|execute_|ctl_reg_use_sp~1_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~35_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~36 .lut_mask = 16'hFF7F; -defparam \z80_|execute_|ctl_alu_shift_oe~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~43 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~43_combout = (\z80_|execute_|ctl_alu_shift_oe~42_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~26_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~33_combout ) # (\z80_|execute_|ctl_alu_shift_oe~36_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~42_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~26_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~33_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~43 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_alu_shift_oe~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_lo~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_lo~9_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q ))) # (!\z80_|pla_decode_|Equal47~0_combout ) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|M5~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_lo~9 .lut_mask = 16'hF5F7; -defparam \z80_|execute_|ctl_reg_in_lo~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_oe~0_combout = ((\z80_|execute_|ctl_66_oe~2_combout ) # ((\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_alu_shift_oe~14_combout ))) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ) - - .dataa(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datab(\z80_|execute_|ctl_66_oe~2_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_oe~0 .lut_mask = 16'hFDDD; -defparam \z80_|execute_|ctl_alu_op1_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout = (\z80_|pla_decode_|Equal48~0_combout & (\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )) - - .dataa(\z80_|pla_decode_|Equal48~0_combout ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 .lut_mask = 16'h0088; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_oe~1 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_oe~1_combout = (\z80_|execute_|ctl_alu_op1_oe~0_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ) # ((\z80_|execute_|ctl_alu_oe~3_combout & \z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_alu_op1_oe~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_oe~1 .lut_mask = 16'hFFF8; -defparam \z80_|execute_|ctl_alu_op1_oe~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~8_combout = (((!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4])) # (!\z80_|pla_decode_|Equal63~0_combout )) # (!\z80_|nM1_int~2_combout ) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal63~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~8 .lut_mask = 16'h777F; -defparam \z80_|execute_|ctl_flags_xy_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~9_combout = (!\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout & (\z80_|execute_|ctl_flags_xy_we~8_combout & ((!\z80_|sequencer_|DFFE_T5_ff~q ) # (!\z80_|execute_|ixy_d~15_combout )))) - - .dataa(\z80_|execute_|ixy_d~15_combout ), - .datab(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .datac(\z80_|sequencer_|DFFE_T5_ff~q ), - .datad(\z80_|execute_|ctl_flags_xy_we~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~9 .lut_mask = 16'h1300; -defparam \z80_|execute_|ctl_flags_xy_we~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N18 -cycloneive_lcell_comb \z80_|pla_decode_|Equal8~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal8~0_combout = (\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [2] & \z80_|ir_|opcode [0])) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [1]), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal8~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal8~0 .lut_mask = 16'h0C00; -defparam \z80_|pla_decode_|Equal8~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~9_combout = (((!\z80_|nM1_int~2_combout & !\z80_|execute_|ixy_d~6_combout )) # (!\z80_|execute_|ctl_mWrite~2_combout )) # (!\z80_|pla_decode_|Equal8~0_combout ) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal8~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~2_combout ), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~9 .lut_mask = 16'h3F7F; -defparam \z80_|execute_|ctl_flags_alu~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~4_combout = ((!\z80_|pla_decode_|Equal40~1_combout & (!\z80_|pla_decode_|Equal39~0_combout & !\z80_|pla_decode_|Equal21~1_combout ))) # (!\z80_|execute_|ixy_d~8_combout ) - - .dataa(\z80_|pla_decode_|Equal40~1_combout ), - .datab(\z80_|pla_decode_|Equal39~0_combout ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|execute_|ixy_d~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~4 .lut_mask = 16'h01FF; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~3_combout = (\z80_|pla_decode_|Equal21~1_combout & (!\z80_|execute_|ctl_mRead~11_combout & ((!\z80_|pla_decode_|Equal10~0_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) # (!\z80_|pla_decode_|Equal21~1_combout & -// (((!\z80_|pla_decode_|Equal10~0_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|execute_|ctl_mRead~11_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|pla_decode_|Equal10~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~3 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_flags_sz_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal11~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal11~1_combout = (!\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [0]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal11~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal11~1 .lut_mask = 16'h000F; -defparam \z80_|pla_decode_|Equal11~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout = (\z80_|execute_|ixy_d~7_combout & (\z80_|execute_|ctl_mWrite~2_combout & (!\z80_|ir_|opcode [2] & \z80_|pla_decode_|Equal11~1_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|pla_decode_|Equal11~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~10_combout = (\z80_|execute_|ctl_flags_alu~9_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~4_combout & (\z80_|execute_|ctl_flags_sz_we~3_combout & !\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ))) - - .dataa(\z80_|execute_|ctl_flags_alu~9_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), - .datac(\z80_|execute_|ctl_flags_sz_we~3_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~10 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_flags_alu~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~11_combout = (\z80_|execute_|ctl_flags_xy_we~9_combout & (\z80_|execute_|ctl_flags_alu~10_combout & ((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|execute_|ixy_d~15_combout )))) - - .dataa(\z80_|execute_|ixy_d~15_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~9_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|execute_|ctl_flags_alu~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~11 .lut_mask = 16'h4C00; -defparam \z80_|execute_|ctl_flags_alu~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout = (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal63~0_combout & (!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4]))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal63~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 .lut_mask = 16'h0008; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla82M1T1_16 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout = (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [0] & (\z80_|nM1_int~2_combout & \z80_|pla_decode_|Equal3~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal3~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel_pla82M1T1_16 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_pf_sel_pla82M1T1_16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~13 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~13_combout = (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|execute_|ctl_mRead~6_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|execute_|ctl_mRead~6_combout ), .datad(\z80_|sequencer_|DFFE_M4_ff~q ), .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~13_combout ), + .combout(\z80_|execute_|ctl_ir_we~4_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~13 .lut_mask = 16'h3F7F; -defparam \z80_|execute_|ctl_flags_use_cf2~13 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_ir_we~4 .lut_mask = 16'h5500; +defparam \z80_|execute_|ctl_ir_we~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~7 ( +// Location: LCCOMB_X26_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_state_iy_set~2 ( // Equation(s): -// \z80_|execute_|ctl_flags_cf_we~7_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # (((!\z80_|pla_decode_|Equal55~0_combout ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|pla_decode_|Equal13~0_combout )) +// \z80_|execute_|ctl_state_iy_set~2_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal3~2_combout ))) - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|pla_decode_|Equal55~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~7 .lut_mask = 16'hBFFF; -defparam \z80_|execute_|ctl_flags_cf_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel[0]~2 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel[0]~2_combout = (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (\z80_|execute_|ctl_flags_use_cf2~13_combout & \z80_|execute_|ctl_flags_cf_we~7_combout )) - - .dataa(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .datab(\z80_|execute_|ctl_flags_use_cf2~13_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_flags_cf_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel[0]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel[0]~2 .lut_mask = 16'h4400; -defparam \z80_|execute_|ctl_pf_sel[0]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~2 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~2_combout = (\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_T1_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~2 .lut_mask = 16'h00F0; -defparam \z80_|execute_|ctl_alu_oe~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~25 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~25_combout = (\z80_|execute_|ctl_ir_we~14_combout & (!\z80_|execute_|ixy_d~7_combout & ((!\z80_|execute_|ctl_alu_oe~2_combout )))) # (!\z80_|execute_|ctl_ir_we~14_combout & (((!\z80_|execute_|ctl_alu_oe~2_combout ) # -// (!\z80_|execute_|ctl_ir_we~8_combout )))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_ir_we~14_combout ), - .datac(\z80_|execute_|ctl_ir_we~8_combout ), - .datad(\z80_|execute_|ctl_alu_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~25 .lut_mask = 16'h0377; -defparam \z80_|execute_|ctl_bus_inc_oe~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_we~5_combout = (\z80_|execute_|ctl_bus_inc_oe~25_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|execute_|ctl_ir_we~8_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|execute_|ctl_bus_inc_oe~25_combout ), - .datac(\z80_|execute_|ctl_ir_we~8_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_we~5 .lut_mask = 16'hCC8C; -defparam \z80_|execute_|ctl_flags_hf_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~10_combout = (\z80_|execute_|ctl_flags_hf_we~5_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|pla_decode_|Equal13~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(\z80_|execute_|ctl_flags_hf_we~5_combout ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~10 .lut_mask = 16'hCCC4; -defparam \z80_|execute_|ctl_flags_pf_we~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~48 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~48_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|execute_|ctl_alu_op_low~13_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~13_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~48 .lut_mask = 16'h3331; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~2_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout & (\z80_|execute_|ctl_pf_sel[0]~2_combout & (\z80_|execute_|ctl_flags_pf_we~10_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .datab(\z80_|execute_|ctl_pf_sel[0]~2_combout ), - .datac(\z80_|execute_|ctl_flags_pf_we~10_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~2 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_flags_pf_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~3_combout = (\z80_|execute_|ctl_flags_pf_we~2_combout & (((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_ir_we~12_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_flags_pf_we~2_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_ir_we~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~3 .lut_mask = 16'h0A2A; -defparam \z80_|execute_|ctl_flags_pf_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y19_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~17 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~17_combout = (((!\z80_|pla_decode_|Equal13~0_combout ) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|pla_decode_|Equal55~0_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~17 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_flags_xy_we~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N6 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~5 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~5_combout = ((!\z80_|pla_decode_|Equal40~1_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal39~0_combout ))) # (!\z80_|execute_|ixy_d~6_combout ) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|pla_decode_|Equal40~1_combout ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~5 .lut_mask = 16'h5557; -defparam \z80_|reg_control_|reg_sys_we_lo~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N26 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~6 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~6_combout = (\z80_|execute_|ctl_flags_xy_we~17_combout & (\z80_|reg_control_|reg_sys_we_lo~5_combout & ((!\z80_|execute_|ctl_alu_op_low~8_combout ) # (!\z80_|pla_decode_|Equal56~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal56~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~17_combout ), - .datad(\z80_|reg_control_|reg_sys_we_lo~5_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~6 .lut_mask = 16'h7000; -defparam \z80_|reg_control_|reg_sys_we_lo~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~10_combout = (\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ixy_d~7_combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) # (!\z80_|pla_decode_|Equal56~0_combout & -// (((!\z80_|nM1_int~2_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal56~0_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|pla_decode_|Equal20~0_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~10 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_flags_xy_we~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout = (\z80_|execute_|ctl_mWrite~2_combout & (\z80_|execute_|ctl_state_alu~4_combout & (\z80_|pla_decode_|Equal2~0_combout & !\z80_|ir_|opcode [0]))) - - .dataa(\z80_|execute_|ctl_mWrite~2_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|pla_decode_|Equal2~0_combout ), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~7 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~7_combout = (\z80_|ir_|opcode [7] & (!\z80_|pla_decode_|Equal33~0_combout & (!\z80_|ir_|opcode [6] & !\z80_|decode_state_|table_xx~0_combout ))) - - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|ir_|opcode [6]), - .datad(\z80_|decode_state_|table_xx~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~7 .lut_mask = 16'h0002; -defparam \z80_|execute_|ctl_state_alu~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~1 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~1_combout = ((!\z80_|execute_|ctl_state_alu~14_combout & (!\z80_|execute_|ctl_state_alu~7_combout & !\z80_|pla_decode_|Equal52~1_combout ))) # (!\z80_|nM1_int~2_combout ) - - .dataa(\z80_|execute_|ctl_state_alu~14_combout ), - .datab(\z80_|execute_|ctl_state_alu~7_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal52~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~1 .lut_mask = 16'h0F1F; -defparam \z80_|execute_|ctl_flags_sz_we~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~2_combout = (\z80_|reg_control_|reg_sys_we_lo~6_combout & (\z80_|execute_|ctl_flags_xy_we~10_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout & \z80_|execute_|ctl_flags_sz_we~1_combout ))) - - .dataa(\z80_|reg_control_|reg_sys_we_lo~6_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~10_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), - .datad(\z80_|execute_|ctl_flags_sz_we~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~2 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_flags_cf_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~6_combout = (\z80_|nM1_int~2_combout & (!\z80_|execute_|ctl_ir_we~9_combout & ((!\z80_|execute_|ctl_mWrite~3_combout ) # (!\z80_|execute_|ctl_ir_we~15_combout )))) # (!\z80_|nM1_int~2_combout & -// (((!\z80_|execute_|ctl_mWrite~3_combout )) # (!\z80_|execute_|ctl_ir_we~15_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_ir_we~9_combout ), - .datad(\z80_|execute_|ctl_mWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~6 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_alu_core_S~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~7 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~7_combout = (\z80_|execute_|ctl_alu_core_S~6_combout & (((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_alu_oe~2_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~9_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_alu_core_S~6_combout ), - .datad(\z80_|execute_|ctl_alu_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~7 .lut_mask = 16'h10F0; -defparam \z80_|execute_|ctl_alu_core_S~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~4_combout = (\z80_|execute_|ctl_ir_we~7_combout & (!\z80_|execute_|ctl_mWrite~3_combout & ((!\z80_|execute_|ctl_ir_we~10_combout ) # (!\z80_|nM1_int~2_combout )))) # (!\z80_|execute_|ctl_ir_we~7_combout & -// (((!\z80_|execute_|ctl_ir_we~10_combout ) # (!\z80_|nM1_int~2_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_mWrite~3_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_ir_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~4 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_alu_core_S~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~5_combout = (\z80_|execute_|ctl_alu_core_S~4_combout & (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~7_combout )) # (!\z80_|execute_|ctl_alu_oe~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_S~4_combout ), - .datab(\z80_|execute_|ctl_ir_we~10_combout ), - .datac(\z80_|execute_|ctl_ir_we~7_combout ), - .datad(\z80_|execute_|ctl_alu_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~5 .lut_mask = 16'h02AA; -defparam \z80_|execute_|ctl_alu_core_S~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout = (\z80_|execute_|ctl_mWrite~2_combout & (\z80_|pla_decode_|Equal8~0_combout & (\z80_|sequencer_|DFFE_T5_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ))) - - .dataa(\z80_|execute_|ctl_mWrite~2_combout ), - .datab(\z80_|pla_decode_|Equal8~0_combout ), - .datac(\z80_|sequencer_|DFFE_T5_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_alu_res_oe~0_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout & (((!\z80_|pla_decode_|Equal69~0_combout & !\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal69~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_res_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_res_oe~0 .lut_mask = 16'h0133; -defparam \z80_|execute_|ctl_alu_res_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~15 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~15_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_mWrite~2_combout & !\z80_|sequencer_|DFFE_M1_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~2_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~15 .lut_mask = 16'h0040; -defparam \z80_|execute_|ctl_alu_oe~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~1 ( -// Equation(s): -// \z80_|execute_|ctl_alu_res_oe~1_combout = (\z80_|execute_|ctl_alu_core_S~7_combout & (\z80_|execute_|ctl_alu_core_S~5_combout & (\z80_|execute_|ctl_alu_res_oe~0_combout & !\z80_|execute_|ctl_alu_oe~15_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_S~7_combout ), - .datab(\z80_|execute_|ctl_alu_core_S~5_combout ), - .datac(\z80_|execute_|ctl_alu_res_oe~0_combout ), - .datad(\z80_|execute_|ctl_alu_oe~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_res_oe~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_res_oe~1 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_alu_res_oe~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~2 ( -// Equation(s): -// \z80_|execute_|ctl_alu_res_oe~2_combout = (\z80_|execute_|ctl_flags_alu~11_combout & (\z80_|execute_|ctl_flags_pf_we~3_combout & (\z80_|execute_|ctl_flags_cf_we~2_combout & \z80_|execute_|ctl_alu_res_oe~1_combout ))) - - .dataa(\z80_|execute_|ctl_flags_alu~11_combout ), - .datab(\z80_|execute_|ctl_flags_pf_we~3_combout ), - .datac(\z80_|execute_|ctl_flags_cf_we~2_combout ), - .datad(\z80_|execute_|ctl_alu_res_oe~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_res_oe~2 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_res_oe~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_oe~0_combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # ((!\z80_|ir_|opcode [3] & \z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|pla_decode_|Equal13~2_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_oe~0 .lut_mask = 16'h8C88; -defparam \z80_|execute_|ctl_alu_op2_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N4 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~2 ( -// Equation(s): -// \z80_|alu_|db_high[3]~2_combout = (\z80_|execute_|ctl_alu_bs_oe~combout ) # ((\z80_|execute_|ctl_alu_op1_oe~1_combout ) # ((\z80_|execute_|ctl_alu_op2_oe~0_combout ) # (!\z80_|execute_|ctl_alu_res_oe~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~2 .lut_mask = 16'hFFEF; -defparam \z80_|alu_|db_high[3]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N0 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~3 ( -// Equation(s): -// \z80_|alu_|db_high[3]~3_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout ) # (\z80_|alu_|db_high[3]~2_combout ) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datab(gnd), - .datac(\z80_|alu_|db_high[3]~2_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~3 .lut_mask = 16'hFAFA; -defparam \z80_|alu_|db_high[3]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N20 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~24 ( -// Equation(s): -// \z80_|alu_|db_low[2]~24_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout & (\z80_|alu_|db_low[2]~3_combout & (\z80_|alu_|db_low[2]~6_combout ))) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout & (((\z80_|alu_|db_low[2]~3_combout & -// \z80_|alu_|db_low[2]~6_combout )) # (!\z80_|alu_|db_high[3]~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datab(\z80_|alu_|db_low[2]~3_combout ), - .datac(\z80_|alu_|db_low[2]~6_combout ), - .datad(\z80_|alu_|db_high[3]~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~24 .lut_mask = 16'hC0D5; -defparam \z80_|alu_|db_low[2]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N24 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~7 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~7_combout = (\z80_|reg_control_|reg_sys_we_lo~6_combout & ((!\z80_|execute_|ixy_d~15_combout ) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(\z80_|reg_control_|reg_sys_we_lo~6_combout ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~7 .lut_mask = 16'h0AAA; -defparam \z80_|reg_control_|reg_sys_we_lo~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout = (!\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|nM1_int~2_combout & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|pla_decode_|Equal3~1_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~19 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout = ((!\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_ir_we~8_combout & !\z80_|execute_|ctl_ir_we~10_combout ))) # (!\z80_|nM1_int~2_combout ) - - .dataa(\z80_|execute_|ctl_ir_we~9_combout ), - .datab(\z80_|execute_|ctl_ir_we~8_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_ir_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~19 .lut_mask = 16'h0F1F; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~8_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout & (\z80_|execute_|ctl_flags_sz_we~1_combout & (!\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout & \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~1_combout ), - .datac(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~8 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_reg_in_hi~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~8_combout = (\z80_|reg_control_|reg_sys_we_lo~7_combout & (\z80_|execute_|ctl_reg_in_hi~8_combout & ((!\z80_|execute_|ctl_ir_we~4_combout ) # (!\z80_|pla_decode_|Equal13~2_combout )))) - - .dataa(\z80_|reg_control_|reg_sys_we_lo~7_combout ), - .datab(\z80_|pla_decode_|Equal13~2_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~8 .lut_mask = 16'h2A00; -defparam \z80_|execute_|ctl_alu_oe~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~4_combout = ((!\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_alu_op_low~12_combout & !\z80_|execute_|ctl_alu_op_low~11_combout ))) # (!\z80_|execute_|ixy_d~7_combout ) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~12_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~4 .lut_mask = 16'h5557; -defparam \z80_|execute_|ctl_alu_oe~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~9 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~9_combout = (\z80_|execute_|ctl_flags_use_cf2~13_combout & (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_mWrite~3_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_flags_use_cf2~13_combout ), - .datad(\z80_|execute_|ctl_mWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~9 .lut_mask = 16'h10F0; -defparam \z80_|execute_|ctl_mWrite~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~10_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~9_combout ))) # (!\z80_|sequencer_|M5~q ) - - .dataa(\z80_|sequencer_|M5~q ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_ir_we~9_combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~10 .lut_mask = 16'hFF57; -defparam \z80_|execute_|ctl_alu_core_S~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~43 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~43_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~7_combout ))) # (!\z80_|sequencer_|M5~q ) - - .dataa(\z80_|sequencer_|M5~q ), - .datab(\z80_|execute_|ctl_ir_we~10_combout ), - .datac(\z80_|execute_|ctl_ir_we~7_combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~43 .lut_mask = 16'hFF57; -defparam \z80_|execute_|ctl_bus_inc_oe~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~26 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~26_combout = (\z80_|execute_|ctl_alu_core_S~10_combout & (\z80_|execute_|ctl_bus_inc_oe~43_combout & \z80_|execute_|ctl_bus_inc_oe~25_combout )) - - .dataa(\z80_|execute_|ctl_alu_core_S~10_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~26 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_bus_inc_oe~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_we~5_combout = (\z80_|execute_|ctl_mWrite~9_combout & (\z80_|execute_|ctl_bus_inc_oe~26_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|execute_|ctl_mRead~26_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~9_combout ), - .datab(\z80_|execute_|ctl_mRead~26_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~26_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~5 .lut_mask = 16'h20A0; -defparam \z80_|execute_|ctl_bus_db_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~9_combout = (\z80_|execute_|ctl_alu_oe~8_combout & (\z80_|execute_|ctl_alu_oe~4_combout & (\z80_|execute_|ctl_reg_in_lo~9_combout & \z80_|execute_|ctl_bus_db_we~5_combout ))) - - .dataa(\z80_|execute_|ctl_alu_oe~8_combout ), - .datab(\z80_|execute_|ctl_alu_oe~4_combout ), - .datac(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datad(\z80_|execute_|ctl_bus_db_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~9 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_oe~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~11_combout = (\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_alu_oe~3_combout ) # ((\z80_|pla_decode_|Equal69~0_combout ) # (\z80_|execute_|ctl_mWrite~16_combout )))) - - .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), - .datab(\z80_|pla_decode_|Equal69~0_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_mWrite~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~11 .lut_mask = 16'hF0E0; -defparam \z80_|execute_|ctl_alu_oe~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~5_combout = (\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|execute_|ctl_mWrite~16_combout & ((!\z80_|execute_|ctl_mRead~11_combout ) # (!\z80_|execute_|ctl_mRead~36_combout )))) # (!\z80_|execute_|ctl_state_alu~4_combout & -// (((!\z80_|execute_|ctl_mRead~11_combout ) # (!\z80_|execute_|ctl_mRead~36_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_mWrite~16_combout ), - .datac(\z80_|execute_|ctl_mRead~36_combout ), - .datad(\z80_|execute_|ctl_mRead~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~5 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_alu_oe~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~11_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_ir_we~12_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~11_combout ), - .datab(\z80_|execute_|ctl_ir_we~12_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~11 .lut_mask = 16'hFFF1; -defparam \z80_|execute_|ctl_alu_core_S~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~6_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout & (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal20~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~6 .lut_mask = 16'h0013; -defparam \z80_|execute_|ctl_alu_oe~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~7 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~7_combout = (\z80_|execute_|ctl_alu_oe~6_combout & (((!\z80_|execute_|ctl_mRead~27_combout & !\z80_|execute_|ctl_mRead~26_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_mRead~27_combout ), - .datac(\z80_|execute_|ctl_mRead~26_combout ), - .datad(\z80_|execute_|ctl_alu_oe~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~7 .lut_mask = 16'h5700; -defparam \z80_|execute_|ctl_alu_oe~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~12 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~12_combout = (\z80_|execute_|ctl_alu_oe~11_combout ) # (((!\z80_|execute_|ctl_alu_oe~7_combout ) # (!\z80_|execute_|ctl_alu_core_S~11_combout )) # (!\z80_|execute_|ctl_alu_oe~5_combout )) - - .dataa(\z80_|execute_|ctl_alu_oe~11_combout ), - .datab(\z80_|execute_|ctl_alu_oe~5_combout ), - .datac(\z80_|execute_|ctl_alu_core_S~11_combout ), - .datad(\z80_|execute_|ctl_alu_oe~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~12 .lut_mask = 16'hBFFF; -defparam \z80_|execute_|ctl_alu_oe~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~13 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~13_combout = (\z80_|execute_|ctl_alu_oe~12_combout ) # (((\z80_|execute_|ctl_66_oe~2_combout ) # (!\z80_|execute_|ctl_flags_alu~10_combout )) # (!\z80_|execute_|ctl_flags_xy_we~9_combout )) - - .dataa(\z80_|execute_|ctl_alu_oe~12_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~9_combout ), - .datac(\z80_|execute_|ctl_66_oe~2_combout ), - .datad(\z80_|execute_|ctl_flags_alu~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~13 .lut_mask = 16'hFBFF; -defparam \z80_|execute_|ctl_alu_oe~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~14_combout = (\z80_|execute_|ctl_alu_oe~13_combout ) # (!\z80_|execute_|ctl_alu_oe~9_combout ) - - .dataa(\z80_|execute_|ctl_alu_oe~9_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_oe~13_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~14 .lut_mask = 16'hF5F5; -defparam \z80_|execute_|ctl_alu_oe~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~24 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~24_combout = (\z80_|execute_|ctl_flags_xy_we~12_combout & (((!\z80_|pla_decode_|Equal48~0_combout & !\z80_|pla_decode_|Equal69~0_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|pla_decode_|Equal48~0_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~12_combout ), - .datad(\z80_|pla_decode_|Equal69~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~24 .lut_mask = 16'h3070; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~27 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~27_combout = (\z80_|pla_decode_|Equal20~0_combout & (!\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ixy_d~6_combout ) # (!\z80_|execute_|ctl_mRead~26_combout )))) # (!\z80_|pla_decode_|Equal20~0_combout & -// (((!\z80_|execute_|ixy_d~6_combout )) # (!\z80_|execute_|ctl_mRead~26_combout ))) - - .dataa(\z80_|pla_decode_|Equal20~0_combout ), - .datab(\z80_|execute_|ctl_mRead~26_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~27 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~40 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~40_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~24_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~27_combout & \z80_|execute_|nextM~11_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~27_combout ), - .datad(\z80_|execute_|nextM~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~40 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~53 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~53_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal21~1_combout ) # (!\z80_|sequencer_|DFFE_T4_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), - .datad(\z80_|pla_decode_|Equal21~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~53 .lut_mask = 16'hB0F0; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_hi~8_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & ((\z80_|execute_|ctl_ir_we~12_combout ) # (!\z80_|execute_|nextM~2_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~12_combout ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|execute_|nextM~2_combout ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_hi~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_hi~8 .lut_mask = 16'h8C00; -defparam \z80_|execute_|ctl_reg_out_hi~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|setM1~54 ( -// Equation(s): -// \z80_|execute_|setM1~54_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|execute_|ctl_ir_we~9_combout ), - .datac(\z80_|execute_|ctl_ir_we~10_combout ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~54_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~54 .lut_mask = 16'hABFF; -defparam \z80_|execute_|setM1~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~1 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~1_combout = ((!\z80_|execute_|ctl_ir_we~8_combout & (!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_state_alu~7_combout ))) # (!\z80_|execute_|ctl_eval_cond~0_combout ) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_state_alu~7_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~1 .lut_mask = 16'h01FF; -defparam \z80_|execute_|ctl_sw_2u~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~4 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~4_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|execute_|ctl_mWrite~5_combout & ((!\z80_|execute_|ctl_alu_oe~3_combout )))) # (!\z80_|execute_|ctl_eval_cond~0_combout & (((!\z80_|execute_|ctl_ir_we~4_combout )) # -// (!\z80_|execute_|ctl_mWrite~5_combout ))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|ctl_mWrite~5_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|execute_|ctl_alu_oe~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~4 .lut_mask = 16'h1537; -defparam \z80_|execute_|ctl_sw_2u~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~5 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~5_combout = (\z80_|execute_|setM1~54_combout & (\z80_|execute_|ctl_sw_2u~1_combout & \z80_|execute_|ctl_sw_2u~4_combout )) - - .dataa(\z80_|execute_|setM1~54_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_sw_2u~1_combout ), - .datad(\z80_|execute_|ctl_sw_2u~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~5 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_sw_2u~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~6 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~6_combout = (\z80_|execute_|ctl_reg_gp_sel~36_combout & (\z80_|execute_|comb~0_combout $ ((!\z80_|ir_|opcode [0])))) # (!\z80_|execute_|ctl_reg_gp_sel~36_combout & (!\z80_|execute_|ctl_sw_2u~5_combout & -// (\z80_|execute_|comb~0_combout $ (!\z80_|ir_|opcode [0])))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel~36_combout ), - .datab(\z80_|execute_|comb~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|execute_|ctl_sw_2u~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~6 .lut_mask = 16'h82C3; -defparam \z80_|execute_|ctl_sw_2u~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~35 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~35_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ctl_state_alu~5_combout & ((!\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|pla_decode_|Equal47~0_combout & -// (((!\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|pla_decode_|Equal34~0_combout ), - .datad(\z80_|execute_|ctl_state_alu~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~35 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_inc_cy~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~35 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~35_combout = (\z80_|execute_|ctl_inc_cy~35_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|sequencer_|DFFE_M4_ff~q ) # (!\z80_|pla_decode_|Equal19~0_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|pla_decode_|Equal19~0_combout ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|execute_|ctl_inc_cy~35_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~35 .lut_mask = 16'hBF00; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~6 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~6_combout = (\z80_|pla_decode_|Equal55~0_combout & (!\z80_|ir_|opcode [3] & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~6 .lut_mask = 16'h0200; -defparam \z80_|execute_|ctl_mWrite~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~2 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~2_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|execute_|ctl_mWrite~6_combout & ((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|execute_|ctl_eval_cond~0_combout & -// (((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|ctl_mWrite~6_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|execute_|ctl_mRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~2 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_sw_2u~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~0 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~0_combout = (\z80_|pla_decode_|Equal9~1_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((!\z80_|execute_|ctl_mWrite~4_combout ) # (!\z80_|execute_|ctl_state_alu~5_combout )))) # (!\z80_|pla_decode_|Equal9~1_combout & -// (((!\z80_|execute_|ctl_mWrite~4_combout ) # (!\z80_|execute_|ctl_state_alu~5_combout )))) - - .dataa(\z80_|pla_decode_|Equal9~1_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_state_alu~5_combout ), - .datad(\z80_|execute_|ctl_mWrite~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~0 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_sw_2u~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~3 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~3_combout = (\z80_|execute_|ctl_sw_2u~2_combout & (\z80_|execute_|ctl_sw_2u~0_combout & ((!\z80_|execute_|ctl_alu_oe~2_combout ) # (!\z80_|execute_|ctl_mRead~8_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~8_combout ), - .datab(\z80_|execute_|ctl_sw_2u~2_combout ), - .datac(\z80_|execute_|ctl_sw_2u~0_combout ), - .datad(\z80_|execute_|ctl_alu_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~3 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_sw_2u~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~52 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~52_combout = (\z80_|execute_|ctl_sw_2u~3_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|sequencer_|M5~q )) # (!\z80_|execute_|ctl_mRead~10_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|execute_|ctl_sw_2u~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~52 .lut_mask = 16'hDF00; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout = (\z80_|pla_decode_|Equal1~4_combout & (\z80_|ir_|opcode [0] & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~4_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~2_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|pla_decode_|Equal69~0_combout ) # (\z80_|execute_|ctl_alu_op_low~13_combout )))) - - .dataa(\z80_|pla_decode_|Equal69~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~13_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~2 .lut_mask = 16'hFEF0; -defparam \z80_|execute_|ctl_reg_out_lo~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N18 -cycloneive_lcell_comb \z80_|execute_|rsel3 ( -// Equation(s): -// \z80_|execute_|rsel3~combout = \z80_|ir_|opcode [3] $ (((\z80_|ir_|opcode [4] & \z80_|ir_|opcode [5]))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|ir_|opcode [3]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|rsel3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|rsel3 .lut_mask = 16'h7878; -defparam \z80_|execute_|rsel3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_hi~5_combout = (\z80_|execute_|ctl_mRead~5_combout & (!\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|rsel3~combout ) # (!\z80_|execute_|ctl_reg_out_lo~2_combout )))) # (!\z80_|execute_|ctl_mRead~5_combout & -// (((\z80_|execute_|rsel3~combout ) # (!\z80_|execute_|ctl_reg_out_lo~2_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~5_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|execute_|ctl_reg_out_lo~2_combout ), - .datad(\z80_|execute_|rsel3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_hi~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_hi~5 .lut_mask = 16'h7707; -defparam \z80_|execute_|ctl_reg_out_hi~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_hi~6_combout = (!\z80_|execute_|ctl_sw_2u~6_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout & \z80_|execute_|ctl_reg_out_hi~5_combout ))) - - .dataa(\z80_|execute_|ctl_sw_2u~6_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ), - .datad(\z80_|execute_|ctl_reg_out_hi~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_hi~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_hi~6 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_out_hi~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_hi~7_combout = ((\z80_|execute_|ctl_reg_out_hi~8_combout ) # ((!\z80_|execute_|ctl_reg_out_hi~6_combout ) # (!\z80_|execute_|ctl_reg_out_hi~4_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ), - .datab(\z80_|execute_|ctl_reg_out_hi~8_combout ), - .datac(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .datad(\z80_|execute_|ctl_reg_out_hi~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_hi~7 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_reg_out_hi~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N28 -cycloneive_lcell_comb \z80_|execute_|rsel0 ( -// Equation(s): -// \z80_|execute_|rsel0~combout = \z80_|ir_|opcode [0] $ (((\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1]))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(gnd), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|execute_|rsel0~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|rsel0 .lut_mask = 16'h5AAA; -defparam \z80_|execute_|rsel0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout = (\z80_|execute_|ixy_d~15_combout & \z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(gnd), - .datab(\z80_|execute_|ixy_d~15_combout ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 .lut_mask = 16'hC0C0; -defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~33 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~33_combout = (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout & (\z80_|execute_|ctl_reg_use_sp~0_combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_mRead~36_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), - .datab(\z80_|execute_|ctl_reg_use_sp~0_combout ), - .datac(\z80_|execute_|ctl_mRead~36_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~33 .lut_mask = 16'h0444; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~6_combout = (\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout & ((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~6 .lut_mask = 16'h0888; -defparam \z80_|execute_|ctl_reg_out_lo~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~7_combout = (\z80_|execute_|ctl_reg_out_lo~6_combout & (((!\z80_|execute_|ctl_reg_gp_sel~36_combout & \z80_|execute_|ctl_sw_2u~5_combout )) # (!\z80_|execute_|rsel0~combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel~36_combout ), - .datab(\z80_|execute_|rsel0~combout ), - .datac(\z80_|execute_|ctl_reg_out_lo~6_combout ), - .datad(\z80_|execute_|ctl_sw_2u~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~7 .lut_mask = 16'h7030; -defparam \z80_|execute_|ctl_reg_out_lo~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_iorw~11 ( -// Equation(s): -// \z80_|execute_|ctl_iorw~11_combout = (!\z80_|ir_|opcode [1] & (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [2] & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_iorw~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_iorw~11 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_iorw~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~10 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~10_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (((\z80_|execute_|rsel3~combout & \z80_|execute_|ctl_iorw~11_combout )) # (!\z80_|execute_|nextM~2_combout ))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|rsel3~combout ), - .datac(\z80_|execute_|nextM~2_combout ), - .datad(\z80_|execute_|ctl_iorw~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~10 .lut_mask = 16'h8A0A; -defparam \z80_|execute_|ctl_sw_2d~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~14 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~14_combout = (!\z80_|execute_|ctl_mRead~14_combout & (((\z80_|decode_state_|in_halt~q ) # (!\z80_|pla_decode_|Equal33~0_combout )) # (!\z80_|pla_decode_|Equal77~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal77~0_combout ), - .datab(\z80_|decode_state_|in_halt~q ), - .datac(\z80_|execute_|ctl_mRead~14_combout ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~14 .lut_mask = 16'h0D0F; -defparam \z80_|execute_|ctl_sw_2d~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~11 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~11_combout = (\z80_|execute_|ctl_sw_2d~10_combout ) # ((\z80_|nM1_int~2_combout & ((!\z80_|execute_|ctl_sw_1d~8_combout ) # (!\z80_|execute_|ctl_sw_2d~14_combout )))) - - .dataa(\z80_|execute_|ctl_sw_2d~10_combout ), - .datab(\z80_|execute_|ctl_sw_2d~14_combout ), - .datac(\z80_|execute_|ctl_sw_1d~8_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~11 .lut_mask = 16'hBFAA; -defparam \z80_|execute_|ctl_sw_2d~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~12 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~12_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|execute_|rsel3~combout & ((\z80_|execute_|ctl_alu_op_low~14_combout ) # (\z80_|execute_|ctl_alu_shift_oe~15_combout )))) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .datad(\z80_|execute_|rsel3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~12 .lut_mask = 16'hFEAA; -defparam \z80_|execute_|ctl_sw_2d~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~13 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~13_combout = ((\z80_|execute_|ctl_sw_2d~11_combout ) # ((\z80_|execute_|ctl_sw_2d~12_combout ) # (!\z80_|execute_|ctl_sw_2d~9_combout ))) # (!\z80_|execute_|ctl_reg_out_lo~7_combout ) - - .dataa(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .datab(\z80_|execute_|ctl_sw_2d~11_combout ), - .datac(\z80_|execute_|ctl_sw_2d~12_combout ), - .datad(\z80_|execute_|ctl_sw_2d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~13 .lut_mask = 16'hFDFF; -defparam \z80_|execute_|ctl_sw_2d~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_66_oe ( -// Equation(s): -// \z80_|execute_|ctl_66_oe~combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|sequencer_|DFFE_T3_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|pla_decode_|Equal47~0_combout ))) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_66_oe~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_66_oe .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_66_oe .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~34 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~34_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|pla_decode_|Equal47~0_combout & ((!\z80_|execute_|ctl_alu_oe~2_combout ) # (!\z80_|pla_decode_|Equal34~0_combout )))) # (!\z80_|execute_|ixy_d~7_combout & -// (((!\z80_|execute_|ctl_alu_oe~2_combout )) # (!\z80_|pla_decode_|Equal34~0_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|pla_decode_|Equal34~0_combout ), - .datac(\z80_|pla_decode_|Equal47~0_combout ), - .datad(\z80_|execute_|ctl_alu_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~34 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_inc_cy~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~0 ( -// Equation(s): -// \z80_|execute_|ctl_apin_mux~0_combout = (\z80_|execute_|ctl_inc_cy~34_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout & ((!\z80_|execute_|ctl_alu_oe~2_combout ) # (!\z80_|pla_decode_|Equal19~0_combout )))) - - .dataa(\z80_|execute_|ctl_inc_cy~34_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), - .datac(\z80_|pla_decode_|Equal19~0_combout ), - .datad(\z80_|execute_|ctl_alu_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_apin_mux~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_apin_mux~0 .lut_mask = 16'h0888; -defparam \z80_|execute_|ctl_apin_mux~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~5 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~5_combout = (\z80_|execute_|ctl_alu_op_low~14_combout ) # (((\z80_|execute_|ctl_alu_shift_oe~14_combout & \z80_|pla_decode_|Equal47~0_combout )) # (!\z80_|execute_|ctl_sw_4u~1_combout )) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ctl_sw_4u~1_combout ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~5 .lut_mask = 16'hEFCF; -defparam \z80_|execute_|ctl_sw_4u~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~75 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~75_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & (!\z80_|pla_decode_|Equal38~2_combout & ((!\z80_|pla_decode_|Equal37~0_combout )))) # (!\z80_|execute_|ctl_alu_op_low~8_combout & (((!\z80_|pla_decode_|Equal38~2_combout -// & !\z80_|pla_decode_|Equal37~0_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datab(\z80_|pla_decode_|Equal38~2_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|pla_decode_|Equal37~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~75_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~75 .lut_mask = 16'h0537; -defparam \z80_|execute_|ctl_inc_cy~75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~76 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~76_combout = (\z80_|execute_|ctl_inc_cy~75_combout & (((!\z80_|execute_|ctl_alu_op_low~8_combout & !\z80_|execute_|ixy_d~5_combout )) # (!\z80_|pla_decode_|Equal29~0_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~75_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|pla_decode_|Equal29~0_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~76_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~76 .lut_mask = 16'h0A2A; -defparam \z80_|execute_|ctl_inc_cy~76 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal4~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal4~0_combout = (\z80_|execute_|comb~1_combout & (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal1~7_combout & \z80_|pla_decode_|Equal1~4_combout ))) - - .dataa(\z80_|execute_|comb~1_combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|pla_decode_|Equal1~7_combout ), - .datad(\z80_|pla_decode_|Equal1~4_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal4~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal4~0 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y19_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~48 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~48_combout = (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|execute_|ctl_mWrite~4_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|execute_|ctl_mWrite~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~48 .lut_mask = 16'h1FFF; -defparam \z80_|execute_|ctl_bus_inc_oe~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~46 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~46_combout = (\z80_|execute_|ctl_bus_inc_oe~48_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T5_ff~q )) # (!\z80_|pla_decode_|Equal4~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal4~0_combout ), + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|execute_|ctl_bus_inc_oe~48_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal3~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_iy_set~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_iy_set~2 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_state_iy_set~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N18 +cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_16 ( +// Equation(s): +// \z80_|sequencer_|SYNTHESIZED_WIRE_16~combout = (\z80_|execute_|setM1~54_combout & (\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|execute_|nextM~14_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|setM1~54_combout ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_16 .lut_mask = 16'h00C0; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y13_N19 +dffeas \z80_|sequencer_|DFFE_T5_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_T5_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_T5_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_T5_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_state_ixiy_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_state_ixiy_we~2_combout = (\z80_|execute_|ixy_d~15_combout & ((\z80_|sequencer_|DFFE_T5_ff~q ) # ((!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T2_ff~q )))) # (!\z80_|execute_|ixy_d~15_combout & +// (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|execute_|ixy_d~15_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), .datad(\z80_|sequencer_|DFFE_T5_ff~q ), .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~46_combout ), + .combout(\z80_|execute_|ctl_state_ixiy_we~2_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~46 .lut_mask = 16'hD0F0; -defparam \z80_|execute_|ctl_bus_inc_oe~46 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_state_ixiy_we~2 .lut_mask = 16'hBA30; +defparam \z80_|execute_|ctl_state_ixiy_we~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y18_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~53 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~53_combout = (\z80_|execute_|ctl_mRead~16_combout & (!\z80_|execute_|ctl_alu_op_low~8_combout & ((!\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|execute_|ctl_mRead~16_combout & (((!\z80_|execute_|ctl_alu_op_low~8_combout & -// !\z80_|execute_|ixy_d~5_combout )) # (!\z80_|pla_decode_|Equal9~1_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~16_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~53_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~53 .lut_mask = 16'h0537; -defparam \z80_|execute_|ctl_inc_cy~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~92 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~92_combout = (((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|pla_decode_|Equal9~1_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|sequencer_|DFFE_M4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~92_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~92 .lut_mask = 16'h5F7F; -defparam \z80_|execute_|ctl_inc_cy~92 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal19~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal19~1_combout = (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal32~0_combout & \z80_|pla_decode_|Equal52~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|pla_decode_|Equal32~0_combout ), - .datad(\z80_|pla_decode_|Equal52~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal19~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal19~1 .lut_mask = 16'h2000; -defparam \z80_|pla_decode_|Equal19~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~0 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~0_combout = (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|M5~q ) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|sequencer_|M5~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~0 .lut_mask = 16'hAA00; -defparam \z80_|execute_|ctl_sw_4u~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~38 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~38_combout = (((!\z80_|execute_|ctl_alu_shift_oe~14_combout & !\z80_|execute_|ctl_sw_4u~0_combout )) # (!\z80_|pla_decode_|Equal3~1_combout )) # (!\z80_|pla_decode_|Equal19~1_combout ) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|pla_decode_|Equal19~1_combout ), - .datac(\z80_|execute_|ctl_sw_4u~0_combout ), - .datad(\z80_|pla_decode_|Equal3~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~38 .lut_mask = 16'h37FF; -defparam \z80_|execute_|ctl_inc_cy~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~93 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~93_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|pla_decode_|Equal34~0_combout ) - - .dataa(\z80_|pla_decode_|Equal34~0_combout ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~93_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~93 .lut_mask = 16'h57FF; -defparam \z80_|execute_|ctl_inc_cy~93 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~39 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~39_combout = (\z80_|execute_|ctl_inc_cy~93_combout & (((!\z80_|execute_|ctl_alu_op_low~8_combout & !\z80_|execute_|ixy_d~5_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|execute_|ctl_inc_cy~93_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~39 .lut_mask = 16'h444C; -defparam \z80_|execute_|ctl_inc_cy~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~24 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~24_combout = (\z80_|execute_|ctl_inc_cy~92_combout & (\z80_|execute_|ctl_inc_cy~38_combout & \z80_|execute_|ctl_inc_cy~39_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_inc_cy~92_combout ), - .datac(\z80_|execute_|ctl_inc_cy~38_combout ), - .datad(\z80_|execute_|ctl_inc_cy~39_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~24 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_bus_inc_oe~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~1 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~1_combout = (\z80_|execute_|ctl_inc_cy~76_combout & (\z80_|execute_|ctl_bus_inc_oe~46_combout & (\z80_|execute_|ctl_inc_cy~53_combout & \z80_|execute_|ctl_bus_inc_oe~24_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~76_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~46_combout ), - .datac(\z80_|execute_|ctl_inc_cy~53_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~1 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_we~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T5_ff~q & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal8~0_combout ))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T5_ff~q ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|pla_decode_|Equal8~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~44 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~44_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout & (((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|pla_decode_|Equal11~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal11~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~44 .lut_mask = 16'h1333; -defparam \z80_|execute_|ctl_bus_inc_oe~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~5_combout = ((!\z80_|pla_decode_|Equal10~0_combout & (!\z80_|pla_decode_|Equal11~0_combout & !\z80_|execute_|ctl_mRead~36_combout ))) # (!\z80_|execute_|ctl_alu_op_low~8_combout ) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|execute_|ctl_mRead~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~5 .lut_mask = 16'h3337; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~0_combout = (\z80_|execute_|ctl_bus_inc_oe~44_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~5_combout & ((!\z80_|execute_|ctl_mWrite~16_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_mWrite~16_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~0 .lut_mask = 16'h2A00; -defparam \z80_|execute_|ctl_reg_gp_we~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|sequencer_|M5~q & \z80_|pla_decode_|Equal9~1_combout )) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~35 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~35_combout = (\z80_|execute_|ctl_reg_gp_we~0_combout & (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout & ((!\z80_|pla_decode_|Equal10~0_combout ) # (!\z80_|execute_|ixy_d~9_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_we~0_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), - .datad(\z80_|pla_decode_|Equal10~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~35 .lut_mask = 16'h020A; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~2 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~2_combout = (\z80_|execute_|ixy_d~5_combout & (\z80_|execute_|nextM~2_combout & ((!\z80_|execute_|ixy_d~9_combout ) # (!\z80_|pla_decode_|Equal11~0_combout )))) # (!\z80_|execute_|ixy_d~5_combout & -// (((!\z80_|execute_|ixy_d~9_combout )) # (!\z80_|pla_decode_|Equal11~0_combout ))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|execute_|nextM~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~2 .lut_mask = 16'h3F15; -defparam \z80_|execute_|ctl_sw_4u~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~3 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~3_combout = (\z80_|execute_|ctl_reg_gp_we~1_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout & \z80_|execute_|ctl_sw_4u~2_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~1_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ), - .datad(\z80_|execute_|ctl_sw_4u~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~3 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_sw_4u~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N0 -cycloneive_lcell_comb \z80_|execute_|fMRead~3 ( -// Equation(s): -// \z80_|execute_|fMRead~3_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & (!\z80_|execute_|ctl_state_alu~14_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_mRead~15_combout )))) # -// (!\z80_|execute_|ctl_alu_op_low~8_combout & (((!\z80_|execute_|ctl_alu_shift_oe~14_combout )) # (!\z80_|execute_|ctl_mRead~15_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datab(\z80_|execute_|ctl_mRead~15_combout ), - .datac(\z80_|execute_|ctl_state_alu~14_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~3 .lut_mask = 16'h135F; -defparam \z80_|execute_|fMRead~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~4 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~4_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal55~0_combout & (!\z80_|ir_|opcode [5] & \z80_|execute_|ctl_alu_op_low~8_combout ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~4 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_sw_4u~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout = (\z80_|execute_|ctl_alu_shift_oe~14_combout & (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~15 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~15_combout = (!\z80_|execute_|ctl_sw_4u~4_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_ir_we~12_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~12_combout ), - .datab(\z80_|execute_|ctl_sw_4u~4_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~15 .lut_mask = 16'h0013; -defparam \z80_|execute_|ctl_reg_sel_wz~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~8_combout = (\z80_|execute_|ctl_mRead~10_combout & (!\z80_|execute_|ctl_alu_shift_oe~14_combout & ((!\z80_|execute_|ctl_sw_4u~0_combout )))) # (!\z80_|execute_|ctl_mRead~10_combout & -// (((!\z80_|execute_|ctl_alu_shift_oe~14_combout & !\z80_|execute_|ctl_sw_4u~0_combout )) # (!\z80_|execute_|ctl_mRead~8_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datac(\z80_|execute_|ctl_mRead~8_combout ), - .datad(\z80_|execute_|ctl_sw_4u~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~8 .lut_mask = 16'h0537; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~94 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~94_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|execute_|ctl_mRead~17_combout ) - - .dataa(\z80_|execute_|ctl_mRead~17_combout ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~94_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~94 .lut_mask = 16'h57FF; -defparam \z80_|execute_|ctl_inc_cy~94 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~87 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~87_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|pla_decode_|Equal13~2_combout ) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~87_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~87 .lut_mask = 16'h5FFF; -defparam \z80_|execute_|ctl_inc_cy~87 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~42 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~42_combout = (\z80_|pla_decode_|Equal12~1_combout ) # (((!\z80_|execute_|ctl_sw_4u~0_combout & !\z80_|execute_|ctl_alu_shift_oe~14_combout )) # (!\z80_|pla_decode_|Equal25~0_combout )) - - .dataa(\z80_|execute_|ctl_sw_4u~0_combout ), - .datab(\z80_|pla_decode_|Equal12~1_combout ), - .datac(\z80_|pla_decode_|Equal25~0_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~42 .lut_mask = 16'hCFDF; -defparam \z80_|execute_|ctl_inc_cy~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~34 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~34_combout = (\z80_|execute_|ctl_inc_cy~94_combout & (\z80_|execute_|ctl_inc_cy~87_combout & \z80_|execute_|ctl_inc_cy~42_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_inc_cy~94_combout ), - .datac(\z80_|execute_|ctl_inc_cy~87_combout ), - .datad(\z80_|execute_|ctl_inc_cy~42_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~34 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~16 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~16_combout = (\z80_|execute_|fMRead~3_combout & (\z80_|execute_|ctl_reg_sel_wz~15_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ))) - - .dataa(\z80_|execute_|fMRead~3_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~15_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~16 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sel_wz~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~6 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~6_combout = ((\z80_|execute_|ctl_sw_4u~5_combout ) # ((!\z80_|execute_|ctl_reg_sel_wz~16_combout ) # (!\z80_|execute_|ctl_sw_4u~3_combout ))) # (!\z80_|execute_|ctl_apin_mux~0_combout ) - - .dataa(\z80_|execute_|ctl_apin_mux~0_combout ), - .datab(\z80_|execute_|ctl_sw_4u~5_combout ), - .datac(\z80_|execute_|ctl_sw_4u~3_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~6 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_sw_4u~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N22 -cycloneive_lcell_comb \z80_|pla_decode_|Equal2~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal2~2_combout = (\z80_|pla_decode_|Equal1~7_combout & (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal32~0_combout & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~7_combout ), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|pla_decode_|Equal32~0_combout ), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal2~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal2~2 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal2~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal1~6 ( -// Equation(s): -// \z80_|pla_decode_|Equal1~6_combout = (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal1~5_combout & (\z80_|pla_decode_|Equal1~7_combout & \z80_|pla_decode_|Equal1~4_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal1~5_combout ), - .datac(\z80_|pla_decode_|Equal1~7_combout ), - .datad(\z80_|pla_decode_|Equal1~4_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal1~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal1~6 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal1~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N22 -cycloneive_lcell_comb \z80_|reg_control_|bank_exx~2 ( -// Equation(s): -// \z80_|reg_control_|bank_exx~2_combout = \z80_|reg_control_|bank_exx~q $ (((!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal1~6_combout & \z80_|sequencer_|DFFE_T2_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|pla_decode_|Equal1~6_combout ), - .datac(\z80_|reg_control_|bank_exx~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|reg_control_|bank_exx~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|bank_exx~2 .lut_mask = 16'hB4F0; -defparam \z80_|reg_control_|bank_exx~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y13_N23 -dffeas \z80_|reg_control_|bank_exx ( +// Location: FF_X26_Y16_N7 +dffeas \z80_|decode_state_|DFFE_instIY1 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_control_|bank_exx~2_combout ), + .d(\z80_|execute_|ctl_state_iy_set~2_combout ), .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(vcc), + .ena(\z80_|execute_|ctl_state_ixiy_we~2_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|reg_control_|bank_exx~q ), + .q(\z80_|decode_state_|DFFE_instIY1~q ), .prn(vcc)); // synopsys translate_off -defparam \z80_|reg_control_|bank_exx .is_wysiwyg = "true"; -defparam \z80_|reg_control_|bank_exx .power_up = "low"; +defparam \z80_|decode_state_|DFFE_instIY1 .is_wysiwyg = "true"; +defparam \z80_|decode_state_|DFFE_instIY1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y15_N26 -cycloneive_lcell_comb \z80_|reg_control_|bank_hl_de1~0 ( +// Location: LCCOMB_X25_Y16_N10 +cycloneive_lcell_comb \z80_|decode_state_|use_ixiy ( // Equation(s): -// \z80_|reg_control_|bank_hl_de1~0_combout = \z80_|reg_control_|bank_hl_de1~q $ (((\z80_|pla_decode_|Equal2~2_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & !\z80_|reg_control_|bank_exx~q )))) - - .dataa(\z80_|pla_decode_|Equal2~2_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|reg_control_|bank_hl_de1~q ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_control_|bank_hl_de1~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|bank_hl_de1~0 .lut_mask = 16'hF0D2; -defparam \z80_|reg_control_|bank_hl_de1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y15_N27 -dffeas \z80_|reg_control_|bank_hl_de1 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_control_|bank_hl_de1~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_control_|bank_hl_de1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_control_|bank_hl_de1 .is_wysiwyg = "true"; -defparam \z80_|reg_control_|bank_hl_de1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~10 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~10_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|pla_decode_|Equal4~0_combout ) # ((\z80_|pla_decode_|Equal2~1_combout & \z80_|pla_decode_|Equal1~4_combout )))) - - .dataa(\z80_|pla_decode_|Equal4~0_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|pla_decode_|Equal2~1_combout ), - .datad(\z80_|pla_decode_|Equal1~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~10 .lut_mask = 16'hC888; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~11 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~11_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout ) # (\z80_|execute_|ctl_state_alu~4_combout )))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|nextM~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~11 .lut_mask = 16'h00FE; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~12 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~12_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ) # ((\z80_|execute_|ctl_state_alu~4_combout & \z80_|execute_|ctl_mRead~36_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_mRead~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~12 .lut_mask = 16'hFEEE; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~7 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~7_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|decode_state_|use_ixiy~combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~7 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_mRead~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~9_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mRead~5_combout ) # ((\z80_|execute_|ctl_mRead~7_combout ) # (\z80_|execute_|ctl_mWrite~16_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~5_combout ), - .datab(\z80_|execute_|ctl_mRead~7_combout ), - .datac(\z80_|execute_|ctl_mWrite~16_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~9 .lut_mask = 16'hFE00; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~37 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~37_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~5_combout & (((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|execute_|ctl_mWrite~16_combout ))) - - .dataa(\z80_|execute_|ctl_mWrite~16_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~37 .lut_mask = 16'h4CCC; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~13 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~13_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~12_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~9_combout ) # ((\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ) # (!\z80_|execute_|ctl_reg_gp_sel[1]~37_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~12_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~9_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~37_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~13 .lut_mask = 16'hFFEF; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~47 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~47_combout = (\z80_|decode_state_|DFFE_inst4~q ) # ((\z80_|decode_state_|DFFE_instIY1~q ) # ((!\z80_|pla_decode_|Equal50~0_combout & !\z80_|pla_decode_|Equal49~0_combout ))) - - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(\z80_|decode_state_|DFFE_instIY1~q ), - .datac(\z80_|pla_decode_|Equal50~0_combout ), - .datad(\z80_|pla_decode_|Equal49~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~47 .lut_mask = 16'hEEEF; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|fMWrite~3 ( -// Equation(s): -// \z80_|execute_|fMWrite~3_combout = (!\z80_|execute_|ctl_ir_we~15_combout & (!\z80_|execute_|ctl_ir_we~14_combout & (!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_mRead~6_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~15_combout ), - .datab(\z80_|execute_|ctl_ir_we~14_combout ), - .datac(\z80_|execute_|ctl_ir_we~7_combout ), - .datad(\z80_|execute_|ctl_mRead~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~3 .lut_mask = 16'h0001; -defparam \z80_|execute_|fMWrite~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~5_combout = (\z80_|ir_|opcode [2]) # ((\z80_|ir_|opcode [1]) # (!\z80_|execute_|ctl_mWrite~2_combout )) - - .dataa(\z80_|ir_|opcode [2]), - .datab(gnd), - .datac(\z80_|execute_|ctl_mWrite~2_combout ), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~5 .lut_mask = 16'hFFAF; -defparam \z80_|execute_|ctl_flags_bus~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N26 -cycloneive_lcell_comb \z80_|execute_|fMRead~2 ( -// Equation(s): -// \z80_|execute_|fMRead~2_combout = (!\z80_|pla_decode_|Equal13~2_combout & (!\z80_|execute_|ctl_state_alu~14_combout & \z80_|execute_|ctl_flags_bus~5_combout )) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(\z80_|execute_|ctl_state_alu~14_combout ), - .datac(\z80_|execute_|ctl_flags_bus~5_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|fMRead~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~2 .lut_mask = 16'h1010; -defparam \z80_|execute_|fMRead~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~19 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~19_combout = (\z80_|execute_|fMWrite~3_combout & (\z80_|execute_|fMRead~2_combout & !\z80_|execute_|ctl_ir_we~12_combout )) +// \z80_|decode_state_|use_ixiy~combout = (\z80_|decode_state_|DFFE_inst4~q ) # (\z80_|decode_state_|DFFE_instIY1~q ) .dataa(gnd), - .datab(\z80_|execute_|fMWrite~3_combout ), - .datac(\z80_|execute_|fMRead~2_combout ), - .datad(\z80_|execute_|ctl_ir_we~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~19 .lut_mask = 16'h00C0; -defparam \z80_|execute_|ctl_mRead~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~7_combout = (\z80_|execute_|ctl_state_alu~5_combout & (((\z80_|execute_|ctl_mRead~36_combout ) # (!\z80_|execute_|ctl_mRead~19_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), - .datab(\z80_|execute_|ctl_state_alu~5_combout ), - .datac(\z80_|execute_|ctl_mRead~36_combout ), - .datad(\z80_|execute_|ctl_mRead~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~7 .lut_mask = 16'hC4CC; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~8_combout = (\z80_|ir_|opcode [2] & ((!\z80_|execute_|ctl_sw_2u~5_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), - .datab(gnd), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|execute_|ctl_sw_2u~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~8 .lut_mask = 16'h50F0; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~14 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~14_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~13_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~7_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~8_combout ) # (!\z80_|execute_|ctl_alu_op_low~15_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~13_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~7_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~15_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~14 .lut_mask = 16'hFFEF; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~16 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~16_combout = (\z80_|ir_|opcode [3] & (((\z80_|sequencer_|DFFE_T3_ff~q )))) # (!\z80_|ir_|opcode [3] & (((\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|pla_decode_|Equal12~0_combout )) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal12~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~16 .lut_mask = 16'hC5CD; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~15 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~15_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|ir_|opcode [3] & (\z80_|ir_|opcode [7] & \z80_|ir_|opcode [6]))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|ir_|opcode [6]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~15 .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~17 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~17_combout = (\z80_|ir_|opcode [0] & (((\z80_|execute_|ctl_reg_gp_sel[1]~15_combout )))) # (!\z80_|ir_|opcode [0] & (\z80_|execute_|ctl_reg_gp_sel[1]~16_combout & ((\z80_|execute_|ctl_ir_we~6_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~16_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|execute_|ctl_ir_we~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~17 .lut_mask = 16'hCAC0; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~19 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~19_combout = (!\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2])) - - .dataa(\z80_|ir_|opcode [4]), - .datab(gnd), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~19 .lut_mask = 16'h0050; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~2_combout = (((!\z80_|execute_|ctl_mRead~11_combout & !\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal8~0_combout )) # (!\z80_|pla_decode_|Equal6~0_combout ) - - .dataa(\z80_|execute_|ctl_mRead~11_combout ), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal8~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~2 .lut_mask = 16'h37FF; -defparam \z80_|execute_|ctl_reg_use_sp~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~47 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~47_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q ))) # (!\z80_|execute_|ctl_mRead~8_combout ) - - .dataa(\z80_|sequencer_|M5~q ), - .datab(\z80_|execute_|ctl_mRead~8_combout ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~47 .lut_mask = 16'hFF37; -defparam \z80_|execute_|ctl_bus_inc_oe~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~3_combout = (\z80_|execute_|ctl_reg_use_sp~2_combout & (\z80_|execute_|ctl_reg_use_sp~0_combout & (\z80_|execute_|ctl_bus_inc_oe~47_combout & \z80_|execute_|nextM~11_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~2_combout ), - .datab(\z80_|execute_|ctl_reg_use_sp~0_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~47_combout ), - .datad(\z80_|execute_|nextM~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~3 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_use_sp~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~9 ( -// Equation(s): -// \z80_|execute_|ctl_sw_1d~9_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal6~1_combout & !\z80_|sequencer_|DFFE_M1_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal6~1_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~9 .lut_mask = 16'h0050; -defparam \z80_|execute_|ctl_sw_1d~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~21 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~21_combout = (!\z80_|execute_|ctl_sw_1d~9_combout & (((!\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ctl_state_alu~5_combout )) # (!\z80_|execute_|ctl_mWrite~4_combout ))) - - .dataa(\z80_|execute_|ctl_mWrite~4_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|execute_|ctl_state_alu~5_combout ), - .datad(\z80_|execute_|ctl_sw_1d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~21 .lut_mask = 16'h0057; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~20 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~20_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout & ((\z80_|pla_decode_|Equal33~1_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~15_combout & -// !\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~20 .lut_mask = 16'hAB00; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~20 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~20_combout = (!\z80_|execute_|ctl_alu_oe~3_combout & (!\z80_|execute_|ctl_mRead~14_combout & !\z80_|pla_decode_|Equal49~0_combout )) - - .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), - .datab(\z80_|execute_|ctl_mRead~14_combout ), - .datac(\z80_|pla_decode_|Equal49~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~20 .lut_mask = 16'h0101; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~49 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~49_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((\z80_|execute_|ctl_reg_gp_sel[0]~20_combout ) # (\z80_|sequencer_|DFFE_M1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~20_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~49 .lut_mask = 16'hCCC8; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~22 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~22_combout = (\z80_|execute_|ctl_reg_use_sp~3_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~21_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~6_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~3_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[0]~21_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~22 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~18 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~18_combout = (!\z80_|decode_state_|DFFE_instED~q & (!\z80_|decode_state_|DFFE_instCB~q & ((\z80_|sequencer_|M5~q ) # (\z80_|sequencer_|DFFE_M4_ff~q )))) - - .dataa(\z80_|sequencer_|M5~q ), - .datab(\z80_|decode_state_|DFFE_instED~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|decode_state_|DFFE_instCB~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~18 .lut_mask = 16'h0032; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~23 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~23_combout = ((\z80_|execute_|ctl_reg_gp_sel[1]~17_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~19_combout & \z80_|execute_|ctl_reg_gp_sel[1]~18_combout ))) # (!\z80_|execute_|ctl_reg_gp_sel[0]~22_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~17_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~22_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~23 .lut_mask = 16'h8F0F; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~28 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~28_combout = (\z80_|execute_|ctl_sw_2u~2_combout & !\z80_|execute_|ctl_reg_gp_sel~36_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_sw_2u~2_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_gp_sel~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~28 .lut_mask = 16'h00CC; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~23 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~23_combout = (\z80_|execute_|ctl_sw_1d~4_combout & (((!\z80_|pla_decode_|Equal69~0_combout & \z80_|execute_|ctl_sw_1d~8_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_sw_1d~4_combout ), - .datab(\z80_|pla_decode_|Equal69~0_combout ), - .datac(\z80_|execute_|ctl_sw_1d~8_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~23 .lut_mask = 16'h20AA; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_sel_shift~2_combout = (!\z80_|execute_|ctl_ir_we~8_combout & !\z80_|pla_decode_|Equal20~0_combout ) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal20~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~2 .lut_mask = 16'h0505; -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~14 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_cpl~14_combout = (\z80_|ir_|opcode [4]) # (!\z80_|pla_decode_|Equal63~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|pla_decode_|Equal63~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_cpl~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_cpl~14 .lut_mask = 16'hF0FF; -defparam \z80_|execute_|ctl_flags_hf_cpl~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_cpl~10_combout = (!\z80_|pla_decode_|Equal68~2_combout & (!\z80_|execute_|ctl_state_alu~7_combout & (\z80_|execute_|ctl_flags_hf_cpl~14_combout & !\z80_|execute_|ctl_alu_op_low~13_combout ))) - - .dataa(\z80_|pla_decode_|Equal68~2_combout ), - .datab(\z80_|execute_|ctl_state_alu~7_combout ), - .datac(\z80_|execute_|ctl_flags_hf_cpl~14_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_cpl~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_cpl~10 .lut_mask = 16'h0010; -defparam \z80_|execute_|ctl_flags_hf_cpl~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N22 -cycloneive_lcell_comb \z80_|execute_|setM1~47 ( -// Equation(s): -// \z80_|execute_|setM1~47_combout = (!\z80_|execute_|ctl_ir_we~11_combout & (!\z80_|pla_decode_|Equal69~0_combout & ((!\z80_|pla_decode_|Equal21~0_combout ) # (!\z80_|pla_decode_|Equal63~0_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~11_combout ), - .datab(\z80_|pla_decode_|Equal63~0_combout ), - .datac(\z80_|pla_decode_|Equal21~0_combout ), - .datad(\z80_|pla_decode_|Equal69~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~47 .lut_mask = 16'h0015; -defparam \z80_|execute_|setM1~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|setM1~48 ( -// Equation(s): -// \z80_|execute_|setM1~48_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & (\z80_|execute_|ctl_flags_hf_cpl~10_combout & (\z80_|execute_|setM1~47_combout & \z80_|execute_|nextM~2_combout ))) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), - .datab(\z80_|execute_|ctl_flags_hf_cpl~10_combout ), - .datac(\z80_|execute_|setM1~47_combout ), - .datad(\z80_|execute_|nextM~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~48 .lut_mask = 16'h8000; -defparam \z80_|execute_|setM1~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~13 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~13_combout = (\z80_|ir_|opcode [2]) # ((!\z80_|ir_|opcode [1]) # (!\z80_|execute_|ctl_mWrite~2_combout )) - - .dataa(\z80_|ir_|opcode [2]), - .datab(gnd), - .datac(\z80_|execute_|ctl_mWrite~2_combout ), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~13 .lut_mask = 16'hAFFF; -defparam \z80_|execute_|ctl_al_we~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_flags_oe~0_combout = (!\z80_|execute_|ctl_ir_we~14_combout & (!\z80_|execute_|ctl_mRead~6_combout & (!\z80_|execute_|ctl_ir_we~12_combout & !\z80_|execute_|ctl_iorw~10_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~14_combout ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|execute_|ctl_iorw~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_oe~0 .lut_mask = 16'h0001; -defparam \z80_|execute_|ctl_flags_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~1 ( -// Equation(s): -// \z80_|execute_|ctl_flags_oe~1_combout = (\z80_|execute_|ctl_al_we~13_combout & (\z80_|execute_|ctl_flags_bus~5_combout & (!\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_flags_oe~0_combout ))) - - .dataa(\z80_|execute_|ctl_al_we~13_combout ), - .datab(\z80_|execute_|ctl_flags_bus~5_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|ctl_flags_oe~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_oe~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_oe~1 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_flags_oe~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~13 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~13_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & ((!\z80_|execute_|ctl_flags_oe~1_combout ) # (!\z80_|execute_|setM1~48_combout )))) - - .dataa(\z80_|execute_|setM1~48_combout ), - .datab(\z80_|execute_|ctl_flags_oe~1_combout ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~13 .lut_mask = 16'h0070; -defparam \z80_|execute_|ctl_reg_in_hi~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~29 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~29_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~28_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~27_combout & !\z80_|execute_|ctl_reg_in_hi~13_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~28_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~27_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~29 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~40 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~40_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ctl_state_alu~4_combout & ((!\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ctl_state_alu~6_combout )))) # (!\z80_|pla_decode_|Equal47~0_combout & -// (((!\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|execute_|ctl_state_alu~6_combout ), - .datac(\z80_|pla_decode_|Equal34~0_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~40 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_inc_cy~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~2 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~2_combout = (\z80_|execute_|ctl_inc_cy~40_combout & (((!\z80_|pla_decode_|Equal19~0_combout & !\z80_|pla_decode_|Equal9~1_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~40_combout ), - .datab(\z80_|pla_decode_|Equal19~0_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~2 .lut_mask = 16'h0A2A; -defparam \z80_|execute_|ctl_inc_dec~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~12 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~12_combout = (\z80_|execute_|ctl_inc_dec~2_combout & (((!\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|pla_decode_|Equal9~1_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|execute_|ctl_inc_dec~2_combout ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~12 .lut_mask = 16'h4CCC; -defparam \z80_|execute_|ctl_inc_dec~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~43 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~43_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ctl_mRead~11_combout & ((!\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ixy_d~9_combout )))) # (!\z80_|pla_decode_|Equal47~0_combout & -// (((!\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|execute_|ixy_d~9_combout ))) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|pla_decode_|Equal34~0_combout ), - .datad(\z80_|execute_|ctl_mRead~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~43 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_inc_cy~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~5 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~5_combout = (\z80_|execute_|ctl_inc_dec~12_combout & (\z80_|execute_|ctl_inc_cy~43_combout & ((!\z80_|execute_|ixy_d~9_combout ) # (!\z80_|pla_decode_|Equal19~0_combout )))) - - .dataa(\z80_|execute_|ctl_inc_dec~12_combout ), - .datab(\z80_|pla_decode_|Equal19~0_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|execute_|ctl_inc_cy~43_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~5 .lut_mask = 16'h2A00; -defparam \z80_|execute_|ctl_inc_dec~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~4_combout = (\z80_|execute_|ctl_inc_dec~5_combout & (((!\z80_|execute_|ctl_mRead~11_combout & !\z80_|execute_|ctl_state_alu~4_combout )) # (!\z80_|execute_|ctl_mWrite~4_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~11_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_inc_dec~5_combout ), - .datad(\z80_|execute_|ctl_mWrite~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~4 .lut_mask = 16'h10F0; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|fMRead~6 ( -// Equation(s): -// \z80_|execute_|fMRead~6_combout = (\z80_|pla_decode_|Equal29~0_combout & (!\z80_|execute_|ctl_state_alu~5_combout & (!\z80_|execute_|ixy_d~7_combout ))) # (!\z80_|pla_decode_|Equal29~0_combout & (((!\z80_|execute_|ctl_state_alu~5_combout & -// !\z80_|execute_|ixy_d~7_combout )) # (!\z80_|pla_decode_|Equal9~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal29~0_combout ), - .datab(\z80_|execute_|ctl_state_alu~5_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~6 .lut_mask = 16'h0357; -defparam \z80_|execute_|fMRead~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|fMRead~7 ( -// Equation(s): -// \z80_|execute_|fMRead~7_combout = (\z80_|execute_|ctl_state_alu~5_combout & (((!\z80_|pla_decode_|Equal37~0_combout & !\z80_|execute_|ctl_mRead~16_combout )))) # (!\z80_|execute_|ctl_state_alu~5_combout & (((!\z80_|pla_decode_|Equal37~0_combout & -// !\z80_|execute_|ctl_mRead~16_combout )) # (!\z80_|execute_|ixy_d~7_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~5_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|pla_decode_|Equal37~0_combout ), - .datad(\z80_|execute_|ctl_mRead~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~7 .lut_mask = 16'h111F; -defparam \z80_|execute_|fMRead~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N26 -cycloneive_lcell_comb \z80_|execute_|fMRead~8 ( -// Equation(s): -// \z80_|execute_|fMRead~8_combout = (\z80_|execute_|fMRead~7_combout & (((!\z80_|execute_|ctl_state_alu~5_combout & !\z80_|execute_|ixy_d~7_combout )) # (!\z80_|pla_decode_|Equal38~2_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~5_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|execute_|fMRead~7_combout ), - .datad(\z80_|pla_decode_|Equal38~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~8 .lut_mask = 16'h10F0; -defparam \z80_|execute_|fMRead~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~26 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~26_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~4_combout & (\z80_|execute_|ctl_reg_gp_we~1_combout & (\z80_|execute_|fMRead~6_combout & \z80_|execute_|fMRead~8_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~1_combout ), - .datac(\z80_|execute_|fMRead~6_combout ), - .datad(\z80_|execute_|fMRead~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~26 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~13 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~13_combout = (\z80_|execute_|ctl_state_alu~8_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|pla_decode_|Equal52~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal52~1_combout ), - .datab(\z80_|execute_|ctl_state_alu~8_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~13 .lut_mask = 16'hC4CC; -defparam \z80_|execute_|ctl_state_alu~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~10 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~10_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~10 .lut_mask = 16'h3331; -defparam \z80_|execute_|ctl_state_alu~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~11 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~11_combout = (\z80_|execute_|ctl_state_alu~5_combout & ((\z80_|pla_decode_|Equal52~1_combout ) # ((\z80_|execute_|ctl_state_alu~10_combout & \z80_|execute_|ctl_state_alu~7_combout )))) # -// (!\z80_|execute_|ctl_state_alu~5_combout & (((\z80_|execute_|ctl_state_alu~10_combout & \z80_|execute_|ctl_state_alu~7_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~5_combout ), - .datab(\z80_|pla_decode_|Equal52~1_combout ), - .datac(\z80_|execute_|ctl_state_alu~10_combout ), - .datad(\z80_|execute_|ctl_state_alu~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~11 .lut_mask = 16'hF888; -defparam \z80_|execute_|ctl_state_alu~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~9 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~9_combout = (\z80_|execute_|ctl_state_alu~14_combout & (((\z80_|nM1_int~2_combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) # (!\z80_|execute_|ctl_state_alu~14_combout & (\z80_|pla_decode_|Equal52~1_combout & -// ((\z80_|nM1_int~2_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~14_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal52~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~9 .lut_mask = 16'hF3A2; -defparam \z80_|execute_|ctl_state_alu~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N14 -cycloneive_lcell_comb \z80_|pla_decode_|Equal62~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal62~2_combout = (\z80_|ir_|opcode [5] & (((\z80_|execute_|ctl_state_alu~11_combout ) # (\z80_|execute_|ctl_state_alu~9_combout )) # (!\z80_|execute_|ctl_state_alu~13_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~13_combout ), - .datab(\z80_|execute_|ctl_state_alu~11_combout ), - .datac(\z80_|execute_|ctl_state_alu~9_combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal62~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal62~2 .lut_mask = 16'hFD00; -defparam \z80_|pla_decode_|Equal62~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~4_combout = (((\z80_|ir_|opcode [3] & \z80_|ir_|opcode [4])) # (!\z80_|nM1_int~2_combout )) # (!\z80_|pla_decode_|Equal62~2_combout ) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|pla_decode_|Equal62~2_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~4 .lut_mask = 16'h8FFF; -defparam \z80_|execute_|ctl_flags_pf_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~21 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~21_combout = ((!\z80_|execute_|ctl_mRead~4_combout & ((!\z80_|pla_decode_|Equal63~0_combout ) # (!\z80_|pla_decode_|Equal32~0_combout )))) # (!\z80_|nM1_int~2_combout ) - - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_mRead~4_combout ), - .datad(\z80_|pla_decode_|Equal63~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~21 .lut_mask = 16'h373F; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal64~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal64~0_combout = (!\z80_|ir_|opcode [5] & (((\z80_|execute_|ctl_state_alu~11_combout ) # (\z80_|execute_|ctl_state_alu~9_combout )) # (!\z80_|execute_|ctl_state_alu~13_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~13_combout ), - .datab(\z80_|execute_|ctl_state_alu~11_combout ), - .datac(\z80_|execute_|ctl_state_alu~9_combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal64~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal64~0 .lut_mask = 16'h00FD; -defparam \z80_|pla_decode_|Equal64~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel[0]~3 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel[0]~3_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # ((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|pla_decode_|Equal64~0_combout )) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal64~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel[0]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel[0]~3 .lut_mask = 16'hEEFF; -defparam \z80_|execute_|ctl_pf_sel[0]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~22 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~22_combout = (\z80_|execute_|ctl_flags_pf_we~4_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout & (\z80_|execute_|ctl_alu_oe~7_combout & \z80_|execute_|ctl_pf_sel[0]~3_combout ))) - - .dataa(\z80_|execute_|ctl_flags_pf_we~4_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ), - .datac(\z80_|execute_|ctl_alu_oe~7_combout ), - .datad(\z80_|execute_|ctl_pf_sel[0]~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~22 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~15 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~15_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|execute_|ctl_state_alu~14_combout & !\z80_|pla_decode_|Equal52~1_combout ))) # (!\z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(\z80_|execute_|ctl_state_alu~14_combout ), - .datab(\z80_|pla_decode_|Equal52~1_combout ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~15 .lut_mask = 16'hFF1F; -defparam \z80_|execute_|ctl_state_alu~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout = (\z80_|ir_|opcode [4] & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal63~0_combout ))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal63~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~25 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~25_combout = (\z80_|execute_|ctl_state_alu~15_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~24_combout & !\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout )) - - .dataa(\z80_|execute_|ctl_state_alu~15_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~25 .lut_mask = 16'h00A0; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~30 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~30_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~29_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~26_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout & \z80_|execute_|ctl_reg_gp_sel[0]~25_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~29_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~30 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~31 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~31_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~14_combout ) # (((\z80_|execute_|ctl_reg_gp_sel[1]~23_combout & \z80_|ir_|opcode [5])) # (!\z80_|execute_|ctl_reg_gp_sel[0]~30_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~14_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~31 .lut_mask = 16'hEFAF; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~33 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~33_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|pla_decode_|Equal11~0_combout ) # ((\z80_|execute_|ctl_mRead~5_combout )))) # (!\z80_|execute_|ixy_d~7_combout & (\z80_|pla_decode_|Equal11~0_combout & -// ((\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ctl_mRead~5_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~33 .lut_mask = 16'hECA8; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~34 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~34_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ) # ((\z80_|ir_|opcode [1] & ((!\z80_|execute_|ctl_sw_2u~5_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), - .datab(\z80_|execute_|ctl_sw_2u~5_combout ), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~34 .lut_mask = 16'hFF70; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo~20 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo~20_combout = ((\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal55~0_combout )) # (!\z80_|pla_decode_|Equal6~0_combout ) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo~20 .lut_mask = 16'hF7F7; -defparam \z80_|execute_|ctl_reg_sys_hilo~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~32 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~32_combout = (\z80_|ir_|opcode [4] & (((\z80_|execute_|ctl_state_alu~5_combout & !\z80_|execute_|ctl_reg_sys_hilo~20_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~22_combout ))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|execute_|ctl_reg_gp_sel[0]~22_combout ), - .datac(\z80_|execute_|ctl_state_alu~5_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~32 .lut_mask = 16'h22A2; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~35 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~35_combout = ((\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ) # (\z80_|execute_|ctl_reg_gp_sel[0]~32_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~35 .lut_mask = 16'hFFF3; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N18 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~5 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_de2~5_combout = (!\z80_|decode_state_|DFFE_instIY1~q & (!\z80_|decode_state_|DFFE_inst4~q & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|decode_state_|DFFE_instIY1~q ), .datab(\z80_|decode_state_|DFFE_inst4~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_de2~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_de2~5 .lut_mask = 16'h0010; -defparam \z80_|reg_control_|reg_sel_de2~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N24 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~6 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_de2~6_combout = (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & ((\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[0]~30_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_de2~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_de2~6 .lut_mask = 16'h0F0B; -defparam \z80_|reg_control_|reg_sel_de2~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N0 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_hl~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_hl~0_combout = (!\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de1~q & ((\z80_|reg_control_|reg_sel_de2~6_combout ))) # (!\z80_|reg_control_|bank_hl_de1~q & (\z80_|reg_control_|reg_sel_de2~5_combout )))) - - .dataa(\z80_|reg_control_|bank_hl_de1~q ), - .datab(\z80_|reg_control_|reg_sel_de2~5_combout ), - .datac(\z80_|reg_control_|reg_sel_de2~6_combout ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_hl~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_hl~0 .lut_mask = 16'h00E4; -defparam \z80_|reg_control_|reg_sel_hl~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N14 -cycloneive_lcell_comb \z80_|reg_control_|bank_hl_de2~0 ( -// Equation(s): -// \z80_|reg_control_|bank_hl_de2~0_combout = \z80_|reg_control_|bank_hl_de2~q $ (((\z80_|pla_decode_|Equal2~2_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|reg_control_|bank_exx~q )))) - - .dataa(\z80_|pla_decode_|Equal2~2_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|reg_control_|bank_hl_de2~q ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_control_|bank_hl_de2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|bank_hl_de2~0 .lut_mask = 16'hD2F0; -defparam \z80_|reg_control_|bank_hl_de2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y15_N15 -dffeas \z80_|reg_control_|bank_hl_de2 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_control_|bank_hl_de2~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_control_|bank_hl_de2~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_control_|bank_hl_de2 .is_wysiwyg = "true"; -defparam \z80_|reg_control_|bank_hl_de2 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N30 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_hl2~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_hl2~0_combout = (\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de2~q & (\z80_|reg_control_|reg_sel_de2~6_combout )) # (!\z80_|reg_control_|bank_hl_de2~q & ((\z80_|reg_control_|reg_sel_de2~5_combout ))))) - - .dataa(\z80_|reg_control_|reg_sel_de2~6_combout ), - .datab(\z80_|reg_control_|reg_sel_de2~5_combout ), - .datac(\z80_|reg_control_|bank_hl_de2~q ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_hl2~0 .lut_mask = 16'hAC00; -defparam \z80_|reg_control_|reg_sel_hl2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~7_combout = (\z80_|nM1_int~2_combout & (((\z80_|pla_decode_|Equal69~0_combout ) # (!\z80_|execute_|ctl_sw_1d~8_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~20_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~20_combout ), - .datab(\z80_|pla_decode_|Equal69~0_combout ), - .datac(\z80_|execute_|ctl_sw_1d~8_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~7 .lut_mask = 16'hDF00; -defparam \z80_|execute_|ctl_reg_in_hi~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~4_combout = (!\z80_|execute_|ctl_reg_in_hi~7_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout & \z80_|execute_|ctl_state_alu~15_combout )) - - .dataa(\z80_|execute_|ctl_reg_in_hi~7_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), .datac(gnd), - .datad(\z80_|execute_|ctl_state_alu~15_combout ), + .datad(\z80_|decode_state_|DFFE_instIY1~q ), .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~4_combout ), + .combout(\z80_|decode_state_|use_ixiy~combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~4 .lut_mask = 16'h1100; -defparam \z80_|execute_|ctl_reg_gp_we~4 .sum_lutc_input = "datac"; +defparam \z80_|decode_state_|use_ixiy .lut_mask = 16'hFFCC; +defparam \z80_|decode_state_|use_ixiy .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 ( +// Location: LCCOMB_X28_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ixy_d~4 ( // Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M4_ff~q & (\z80_|pla_decode_|Equal25~0_combout & !\z80_|pla_decode_|Equal12~1_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|pla_decode_|Equal25~0_combout ), - .datad(\z80_|pla_decode_|Equal12~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~3_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~6_combout & (!\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout & ((!\z80_|execute_|ctl_iorw~10_combout ) # (!\z80_|nM1_int~2_combout )))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), - .datac(\z80_|execute_|ctl_iorw~10_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~3 .lut_mask = 16'h004C; -defparam \z80_|execute_|ctl_reg_gp_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~13 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~13_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout & ((!\z80_|pla_decode_|Equal21~1_combout ) # (!\z80_|execute_|ctl_mRead~11_combout -// )))) - - .dataa(\z80_|execute_|ctl_mRead~11_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~13 .lut_mask = 16'h0013; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5~combout = (\z80_|execute_|ctl_reg_in_hi~2_combout & (\z80_|pla_decode_|Equal25~0_combout & ((\z80_|ir_|opcode [3]) # (!\z80_|pla_decode_|Equal12~0_combout )))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datab(\z80_|pla_decode_|Equal12~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal25~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5 .lut_mask = 16'hA200; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~2_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~13_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5~combout & !\z80_|execute_|ctl_sw_1d~9_combout ))) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5~combout ), - .datad(\z80_|execute_|ctl_sw_1d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~2 .lut_mask = 16'h0008; -defparam \z80_|execute_|ctl_reg_gp_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~5_combout = (!\z80_|execute_|ctl_reg_in_hi~13_combout & (\z80_|execute_|ctl_reg_gp_we~4_combout & (\z80_|execute_|ctl_reg_gp_we~3_combout & \z80_|execute_|ctl_reg_gp_we~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~13_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~4_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~3_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~5 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_gp_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~6_combout = (((\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout )) # (!\z80_|execute_|ctl_sw_4u~3_combout )) # (!\z80_|execute_|ctl_reg_gp_we~5_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_we~5_combout ), - .datab(\z80_|execute_|ctl_sw_4u~3_combout ), - .datac(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~6 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|ctl_reg_gp_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~14 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~14_combout = (!\z80_|execute_|ctl_mRead~7_combout & (((\z80_|ir_|opcode [2]) # (!\z80_|execute_|ctl_mWrite~2_combout )) # (!\z80_|ir_|opcode [1]))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|execute_|ctl_mRead~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~14 .lut_mask = 16'h00F7; -defparam \z80_|execute_|ctl_al_we~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~50 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~50_combout = (!\z80_|execute_|ctl_flags_oe~1_combout & (((!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|execute_|ctl_flags_oe~1_combout ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~50 .lut_mask = 16'h1033; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~26 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~26_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ) # ((\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mWrite~4_combout ) # (!\z80_|execute_|ctl_al_we~14_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~4_combout ), - .datab(\z80_|execute_|ctl_al_we~14_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~26 .lut_mask = 16'hFBF0; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~27 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~27_combout = (\z80_|execute_|rsel3~combout & (((!\z80_|execute_|ctl_reg_gp_sel[0]~20_combout & \z80_|nM1_int~2_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~20_combout ), - .datab(\z80_|execute_|rsel3~combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~27 .lut_mask = 16'h40CC; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~28 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~28_combout = (((\z80_|execute_|ctl_ir_we~7_combout ) # (\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo~20_combout ) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), - .datac(\z80_|execute_|ctl_ir_we~7_combout ), - .datad(\z80_|execute_|ctl_ir_we~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~28 .lut_mask = 16'hFFF7; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~29 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~29_combout = (\z80_|execute_|ctl_state_alu~5_combout & ((\z80_|execute_|ctl_iorw~11_combout ) # ((\z80_|execute_|ctl_state_alu~14_combout ) # (\z80_|execute_|ctl_reg_gp_hilo[0]~28_combout )))) - - .dataa(\z80_|execute_|ctl_iorw~11_combout ), - .datab(\z80_|execute_|ctl_state_alu~5_combout ), - .datac(\z80_|execute_|ctl_state_alu~14_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~29 .lut_mask = 16'hCCC8; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal9~1_combout & \z80_|sequencer_|M5~q )) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|pla_decode_|Equal9~1_combout ), - .datac(gnd), - .datad(\z80_|sequencer_|M5~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 .lut_mask = 16'h4400; -defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~31 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~31_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout & (((!\z80_|execute_|ctl_mRead~8_combout & !\z80_|execute_|ctl_mRead~10_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~8_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), - .datad(\z80_|execute_|ctl_mRead~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~31 .lut_mask = 16'h0307; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~51 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~51_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # ((\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T2_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|execute_|nextM~2_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~51 .lut_mask = 16'h0F08; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~30 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~30_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ) # (((\z80_|pla_decode_|Equal6~1_combout & \z80_|execute_|ixy_d~7_combout )) # (!\z80_|execute_|ctl_mRead~25_combout )) - - .dataa(\z80_|pla_decode_|Equal6~1_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_mRead~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~30 .lut_mask = 16'hECFF; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~32 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~32_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ) # ((\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ) # -// (!\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~32 .lut_mask = 16'hFFEF; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~34 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~34_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ) # (((\z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ) # (\z80_|execute_|ctl_reg_gp_hilo[0]~32_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~34 .lut_mask = 16'hFFFB; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~24 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout = ((\z80_|execute_|ctl_reg_gp_sel~36_combout ) # (!\z80_|execute_|ctl_sw_2u~5_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_sel~36_combout ), - .datad(\z80_|execute_|ctl_sw_2u~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~24 .lut_mask = 16'hF5FF; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~25 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~25_combout = (\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|execute_|rsel0~combout & ((\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout )))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & -// (((\z80_|execute_|rsel0~combout & \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout )) # (!\z80_|execute_|setM1~48_combout ))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|execute_|rsel0~combout ), - .datac(\z80_|execute_|setM1~48_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~25 .lut_mask = 16'hCD05; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~36 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~36_combout = (\z80_|pla_decode_|Equal11~0_combout & (!\z80_|execute_|ixy_d~6_combout & (!\z80_|execute_|ixy_d~9_combout ))) # (!\z80_|pla_decode_|Equal11~0_combout & (((!\z80_|pla_decode_|Equal10~0_combout )) # -// (!\z80_|execute_|ixy_d~6_combout ))) - - .dataa(\z80_|pla_decode_|Equal11~0_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|pla_decode_|Equal10~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~36 .lut_mask = 16'h1357; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout = (!\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal2~1_combout & (\z80_|execute_|ctl_eval_cond~0_combout & !\z80_|ir_|opcode [1]))) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|pla_decode_|Equal2~1_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 .lut_mask = 16'h0040; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N4 -cycloneive_lcell_comb \z80_|execute_|setM1~40 ( -// Equation(s): -// \z80_|execute_|setM1~40_combout = (!\z80_|pla_decode_|Equal4~0_combout & ((!\z80_|pla_decode_|Equal8~0_combout ) # (!\z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal4~0_combout ), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal8~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~40 .lut_mask = 16'h1155; -defparam \z80_|execute_|setM1~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~18 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout & (!\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout & ((\z80_|execute_|setM1~40_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|setM1~40_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~18 .lut_mask = 16'h1101; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~37 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~37_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout & \z80_|execute_|ctl_reg_gp_sel[1]~26_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~37 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~38 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ) # ((!\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~38 .lut_mask = 16'hEFFF; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~93 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~93_combout = (!\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & ((\z80_|reg_control_|reg_sel_hl~0_combout ) # (\z80_|reg_control_|reg_sel_hl2~0_combout )))) - - .dataa(\z80_|reg_control_|reg_sel_hl~0_combout ), - .datab(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~93_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~93 .lut_mask = 16'h0E00; -defparam \z80_|reg_file_|gdfx_temp0[0]~93 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N28 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_de~0_combout = (!\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de1~q & (\z80_|reg_control_|reg_sel_de2~5_combout )) # (!\z80_|reg_control_|bank_hl_de1~q & ((\z80_|reg_control_|reg_sel_de2~6_combout ))))) - - .dataa(\z80_|reg_control_|bank_hl_de1~q ), - .datab(\z80_|reg_control_|reg_sel_de2~5_combout ), - .datac(\z80_|reg_control_|reg_sel_de2~6_combout ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_de~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_de~0 .lut_mask = 16'h00D8; -defparam \z80_|reg_control_|reg_sel_de~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N0 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_50 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_50~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_de~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_de~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_50 .lut_mask = 16'h0C00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N0 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout = (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 .lut_mask = 16'h0F00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N18 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout = (\z80_|decode_state_|DFFE_inst4~q & (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 .lut_mask = 16'h0080; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N30 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|reg_control_|bank_exx~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 .lut_mask = 16'h0400; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N12 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|reg_control_|bank_exx~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 .lut_mask = 16'h0100; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~9_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|execute_|ctl_mRead~4_combout )))) # (!\z80_|pla_decode_|Equal47~0_combout -// & (((!\z80_|execute_|ixy_d~7_combout )) # (!\z80_|execute_|ctl_mRead~4_combout ))) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|execute_|ctl_mRead~4_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~9 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_reg_in_hi~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~10 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~10_combout = (\z80_|execute_|ctl_reg_in_hi~9_combout & (\z80_|execute_|ctl_reg_in_hi~8_combout & \z80_|execute_|ctl_reg_gp_we~5_combout )) - - .dataa(\z80_|execute_|ctl_reg_in_hi~9_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~8_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_gp_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~10 .lut_mask = 16'h8800; -defparam \z80_|execute_|ctl_reg_in_hi~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~19 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~19_combout = (\z80_|execute_|ctl_mRead~22_combout & (\z80_|reg_control_|reg_sys_we_lo~6_combout & ((!\z80_|execute_|ixy_d~15_combout ) # (!\z80_|sequencer_|DFFE_T3_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|execute_|ctl_mRead~22_combout ), - .datac(\z80_|reg_control_|reg_sys_we_lo~6_combout ), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~19 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_reg_sel_wz~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout = (\z80_|pla_decode_|Equal24~0_combout & (\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|ir_|opcode [3] & \z80_|ir_|opcode [4]))) - - .dataa(\z80_|pla_decode_|Equal24~0_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_lo~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_lo~8_combout = (((\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ) # (!\z80_|execute_|ctl_reg_sel_wz~19_combout )) # (!\z80_|execute_|ctl_reg_in_hi~10_combout )) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ) - - .dataa(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~10_combout ), - .datac(\z80_|execute_|ctl_reg_sel_wz~19_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_lo~8 .lut_mask = 16'hFF7F; -defparam \z80_|execute_|ctl_reg_in_lo~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y12_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~19 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~19_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ) # ((\z80_|execute_|ctl_sw_4u~6_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ) # (\z80_|execute_|ctl_reg_in_lo~8_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|execute_|ctl_sw_4u~6_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .datad(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~19 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp0[0]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~4_combout = (\z80_|pla_decode_|Equal6~1_combout & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_M1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|pla_decode_|Equal6~1_combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~4 .lut_mask = 16'h00B0; -defparam \z80_|execute_|ctl_reg_use_sp~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~5_combout = (\z80_|execute_|ctl_reg_use_sp~4_combout ) # ((\z80_|execute_|ctl_mRead~17_combout & ((\z80_|execute_|ctl_reg_in_hi~2_combout ) # (\z80_|execute_|ctl_state_alu~6_combout )))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datab(\z80_|execute_|ctl_reg_use_sp~4_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_mRead~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~5 .lut_mask = 16'hFECC; -defparam \z80_|execute_|ctl_reg_use_sp~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~6_combout = (\z80_|execute_|ctl_reg_use_sp~5_combout ) # ((!\z80_|execute_|ctl_reg_use_sp~3_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[1]~26_combout )) - - .dataa(\z80_|execute_|ctl_reg_use_sp~5_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), - .datad(\z80_|execute_|ctl_reg_use_sp~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~6 .lut_mask = 16'hAFFF; -defparam \z80_|execute_|ctl_reg_use_sp~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N2 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout = (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal21~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal21~2_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal40~0_combout & !\z80_|ir_|opcode [5])) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal40~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal21~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal21~2 .lut_mask = 16'h0808; -defparam \z80_|pla_decode_|Equal21~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N20 -cycloneive_lcell_comb \z80_|reg_control_|bank_af~0 ( -// Equation(s): -// \z80_|reg_control_|bank_af~0_combout = \z80_|reg_control_|bank_af~q $ (((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|pla_decode_|Equal21~2_combout & \z80_|pla_decode_|Equal32~0_combout )))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|pla_decode_|Equal21~2_combout ), - .datac(\z80_|reg_control_|bank_af~q ), - .datad(\z80_|pla_decode_|Equal32~0_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|bank_af~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|bank_af~0 .lut_mask = 16'hB4F0; -defparam \z80_|reg_control_|bank_af~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y12_N21 -dffeas \z80_|reg_control_|bank_af ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_control_|bank_af~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_control_|bank_af~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_control_|bank_af .is_wysiwyg = "true"; -defparam \z80_|reg_control_|bank_af .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N28 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_af~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_af~0_combout = (!\z80_|execute_|ctl_reg_use_sp~6_combout & (!\z80_|reg_control_|bank_af~q & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datab(\z80_|reg_control_|bank_af~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_af~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_af~0 .lut_mask = 16'h1000; -defparam \z80_|reg_control_|reg_sel_af~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N4 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_34 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_34~combout = (\z80_|reg_control_|reg_sel_af~0_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & !\z80_|execute_|ctl_reg_gp_we~6_combout )) - - .dataa(\z80_|reg_control_|reg_sel_af~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_34 .lut_mask = 16'h0088; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N10 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_af2~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_af2~0_combout = (!\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|reg_control_|bank_af~q & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datab(\z80_|reg_control_|bank_af~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_af2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_af2~0 .lut_mask = 16'h4000; -defparam \z80_|reg_control_|reg_sel_af2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N18 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_30 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_30~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_af2~0_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datac(gnd), - .datad(\z80_|reg_control_|reg_sel_af2~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_30 .lut_mask = 16'h2200; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~12 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~12_combout = (\z80_|execute_|ixy_d~6_combout & (!\z80_|pla_decode_|Equal19~0_combout & ((!\z80_|pla_decode_|Equal9~1_combout )))) # (!\z80_|execute_|ixy_d~6_combout & (((!\z80_|pla_decode_|Equal9~1_combout ) # -// (!\z80_|execute_|ctl_reg_in_hi~2_combout )))) - - .dataa(\z80_|pla_decode_|Equal19~0_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~12 .lut_mask = 16'h035F; -defparam \z80_|execute_|ctl_reg_sel_wz~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~4_combout = (\z80_|ir_|opcode [5]) # ((!\z80_|pla_decode_|Equal13~1_combout ) # (!\z80_|pla_decode_|Equal13~0_combout )) - - .dataa(\z80_|ir_|opcode [5]), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|pla_decode_|Equal13~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~4 .lut_mask = 16'hAFFF; -defparam \z80_|execute_|ctl_flags_bus~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~6_combout = (\z80_|pla_decode_|Equal44~0_combout ) # ((\z80_|pla_decode_|Equal52~0_combout & \z80_|pla_decode_|Equal33~0_combout )) - - .dataa(\z80_|pla_decode_|Equal52~0_combout ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|pla_decode_|Equal44~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~6 .lut_mask = 16'hF8F8; -defparam \z80_|execute_|ctl_flags_bus~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~7_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (((\z80_|execute_|ctl_flags_bus~6_combout ) # (!\z80_|execute_|ctl_flags_bus~5_combout )) # (!\z80_|execute_|ctl_flags_bus~4_combout ))) - - .dataa(\z80_|execute_|ctl_flags_bus~4_combout ), - .datab(\z80_|execute_|ctl_flags_bus~5_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_flags_bus~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~7 .lut_mask = 16'hF070; -defparam \z80_|execute_|ctl_flags_bus~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N22 -cycloneive_lcell_comb \z80_|execute_|fMRead~24 ( -// Equation(s): -// \z80_|execute_|fMRead~24_combout = (\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_state_alu~4_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_state_alu~14_combout )))) # -// (!\z80_|execute_|ctl_ir_we~12_combout & (((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_state_alu~14_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~12_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_state_alu~14_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~24 .lut_mask = 16'h0777; -defparam \z80_|execute_|fMRead~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~13 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~13_combout = (\z80_|execute_|ctl_alu_shift_oe~20_combout & (\z80_|execute_|ctl_bus_db_oe~3_combout & \z80_|execute_|ctl_flags_bus~12_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_shift_oe~20_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~3_combout ), - .datad(\z80_|execute_|ctl_flags_bus~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~13 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_flags_bus~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~combout = (\z80_|execute_|ctl_flags_bus~7_combout ) # (((\z80_|execute_|ctl_flags_hf2_we~combout ) # (!\z80_|execute_|ctl_flags_bus~13_combout )) # (!\z80_|execute_|fMRead~24_combout )) - - .dataa(\z80_|execute_|ctl_flags_bus~7_combout ), - .datab(\z80_|execute_|fMRead~24_combout ), - .datac(\z80_|execute_|ctl_flags_hf2_we~combout ), - .datad(\z80_|execute_|ctl_flags_bus~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus .lut_mask = 16'hFBFF; -defparam \z80_|execute_|ctl_flags_bus .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~3 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~3_combout = ((!\z80_|pla_decode_|Equal11~0_combout & ((!\z80_|execute_|ctl_mWrite~2_combout ) # (!\z80_|pla_decode_|Equal55~0_combout )))) # (!\z80_|execute_|ctl_mWrite~7_combout ) - - .dataa(\z80_|pla_decode_|Equal11~0_combout ), - .datab(\z80_|execute_|ctl_mWrite~7_combout ), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|execute_|ctl_mWrite~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~3 .lut_mask = 16'h3777; -defparam \z80_|execute_|ctl_inc_dec~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~14 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~14_combout = (\z80_|execute_|ctl_inc_dec~3_combout & (!\z80_|nM1_int~2_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout & \z80_|execute_|fMRead~3_combout ))) - - .dataa(\z80_|execute_|ctl_inc_dec~3_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), - .datad(\z80_|execute_|fMRead~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~14 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~2_combout = ((!\z80_|execute_|ctl_mRead~15_combout & ((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout )))) # (!\z80_|execute_|ixy_d~5_combout ) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|ctl_mRead~15_combout ), - .datac(\z80_|pla_decode_|Equal25~0_combout ), - .datad(\z80_|pla_decode_|Equal12~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~2 .lut_mask = 16'h7757; -defparam \z80_|execute_|ctl_reg_sel_pc~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~3_combout = (\z80_|execute_|ctl_reg_sel_pc~2_combout & (((!\z80_|execute_|ctl_mRead~10_combout & !\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~2_combout ), - .datac(\z80_|pla_decode_|Equal19~0_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~3 .lut_mask = 16'h04CC; -defparam \z80_|execute_|ctl_reg_sel_pc~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~6_combout = (\z80_|pla_decode_|Equal34~0_combout & (!\z80_|execute_|ixy_d~5_combout & ((!\z80_|execute_|ctl_alu_op_low~8_combout ) # (!\z80_|execute_|ixy_d~16_combout )))) # (!\z80_|pla_decode_|Equal34~0_combout & -// (((!\z80_|execute_|ctl_alu_op_low~8_combout )) # (!\z80_|execute_|ixy_d~16_combout ))) - - .dataa(\z80_|pla_decode_|Equal34~0_combout ), - .datab(\z80_|execute_|ixy_d~16_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~6 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_reg_sel_pc~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~5_combout = ((!\z80_|execute_|ctl_mRead~8_combout & (!\z80_|execute_|ctl_mRead~17_combout & !\z80_|execute_|ctl_mRead~9_combout ))) # (!\z80_|execute_|ixy_d~5_combout ) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|ctl_mRead~8_combout ), - .datac(\z80_|execute_|ctl_mRead~17_combout ), - .datad(\z80_|execute_|ctl_mRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~5 .lut_mask = 16'h5557; -defparam \z80_|execute_|ctl_reg_sel_pc~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~4_combout = ((!\z80_|execute_|ixy_d~10_combout & ((!\z80_|pla_decode_|Equal21~0_combout ) # (!\z80_|pla_decode_|Equal24~0_combout )))) # (!\z80_|execute_|ctl_alu_op_low~8_combout ) - - .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datab(\z80_|pla_decode_|Equal24~0_combout ), - .datac(\z80_|pla_decode_|Equal21~0_combout ), - .datad(\z80_|execute_|ixy_d~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~4 .lut_mask = 16'h557F; -defparam \z80_|execute_|ctl_reg_sel_pc~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~7_combout = (\z80_|execute_|ctl_reg_sel_pc~3_combout & (\z80_|execute_|ctl_reg_sel_pc~6_combout & (\z80_|execute_|ctl_reg_sel_pc~5_combout & \z80_|execute_|ctl_reg_sel_pc~4_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~3_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~6_combout ), - .datac(\z80_|execute_|ctl_reg_sel_pc~5_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~7 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sel_pc~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~8_combout = (\z80_|pla_decode_|Equal3~0_combout & ((\z80_|pla_decode_|Equal24~0_combout ) # ((\z80_|pla_decode_|Equal25~0_combout & !\z80_|pla_decode_|Equal12~1_combout )))) # (!\z80_|pla_decode_|Equal3~0_combout & -// (((\z80_|pla_decode_|Equal25~0_combout & !\z80_|pla_decode_|Equal12~1_combout )))) - - .dataa(\z80_|pla_decode_|Equal3~0_combout ), - .datab(\z80_|pla_decode_|Equal24~0_combout ), - .datac(\z80_|pla_decode_|Equal25~0_combout ), - .datad(\z80_|pla_decode_|Equal12~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~8 .lut_mask = 16'h88F8; -defparam \z80_|execute_|ctl_reg_sel_pc~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~9_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & ((\z80_|pla_decode_|Equal34~0_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~8_combout ) # (\z80_|execute_|ctl_mRead~17_combout )))) - - .dataa(\z80_|pla_decode_|Equal34~0_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~8_combout ), - .datac(\z80_|execute_|ctl_mRead~17_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~9 .lut_mask = 16'hFE00; -defparam \z80_|execute_|ctl_reg_sel_pc~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~10 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~10_combout = (\z80_|execute_|ctl_reg_sel_pc~7_combout & (!\z80_|execute_|ctl_reg_sel_pc~9_combout & ((!\z80_|pla_decode_|Equal41~2_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~7_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~9_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|pla_decode_|Equal41~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~10 .lut_mask = 16'h0222; -defparam \z80_|execute_|ctl_reg_sel_pc~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~13 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~13_combout = (\z80_|execute_|ctl_reg_sel_pc~10_combout & (\z80_|execute_|ctl_inc_cy~94_combout & (\z80_|execute_|ctl_inc_cy~87_combout & \z80_|execute_|ctl_inc_cy~42_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~10_combout ), - .datab(\z80_|execute_|ctl_inc_cy~94_combout ), - .datac(\z80_|execute_|ctl_inc_cy~87_combout ), - .datad(\z80_|execute_|ctl_inc_cy~42_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~13 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~15 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~15_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout & -// !\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~15 .lut_mask = 16'h0020; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~29 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~29_combout = (!\z80_|execute_|ctl_mRead~14_combout & ((\z80_|ir_|opcode [5]) # ((\z80_|ir_|opcode [3]) # (!\z80_|pla_decode_|Equal12~0_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~14_combout ), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal12~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~29 .lut_mask = 16'h5455; -defparam \z80_|execute_|ctl_bus_inc_oe~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~13 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~13_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|ir_|opcode [3] & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~13 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_mRead~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N8 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~49 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~49_combout = (!\z80_|pla_decode_|Equal35~0_combout & (((\z80_|ir_|opcode [3]) # (\z80_|ir_|opcode [4])) # (!\z80_|pla_decode_|Equal24~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal24~0_combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|pla_decode_|Equal35~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~49 .lut_mask = 16'h00FD; -defparam \z80_|execute_|pc_inc_hold~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~9_combout = (!\z80_|execute_|ctl_mRead~10_combout & (!\z80_|execute_|ctl_mRead~15_combout & (!\z80_|pla_decode_|Equal41~2_combout & !\z80_|execute_|ctl_mRead~8_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|execute_|ctl_mRead~15_combout ), - .datac(\z80_|pla_decode_|Equal41~2_combout ), - .datad(\z80_|execute_|ctl_mRead~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~9 .lut_mask = 16'h0001; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~10 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~10_combout = (\z80_|execute_|pc_inc_hold~49_combout & (!\z80_|pla_decode_|Equal19~0_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~9_combout )) - - .dataa(\z80_|execute_|pc_inc_hold~49_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal19~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~10 .lut_mask = 16'h0A00; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~28 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~28_combout = (!\z80_|pla_decode_|Equal33~2_combout & (((!\z80_|pla_decode_|Equal49~0_combout & !\z80_|pla_decode_|Equal50~0_combout )) # (!\z80_|decode_state_|use_ixiy~combout ))) - - .dataa(\z80_|pla_decode_|Equal33~2_combout ), - .datab(\z80_|pla_decode_|Equal49~0_combout ), - .datac(\z80_|decode_state_|use_ixiy~combout ), - .datad(\z80_|pla_decode_|Equal50~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~28 .lut_mask = 16'h0515; -defparam \z80_|execute_|pc_inc_hold~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|setM1~35 ( -// Equation(s): -// \z80_|execute_|setM1~35_combout = (!\z80_|pla_decode_|Equal6~1_combout & (!\z80_|pla_decode_|Equal39~0_combout & !\z80_|pla_decode_|Equal40~1_combout )) - - .dataa(gnd), - .datab(\z80_|pla_decode_|Equal6~1_combout ), - .datac(\z80_|pla_decode_|Equal39~0_combout ), - .datad(\z80_|pla_decode_|Equal40~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~35 .lut_mask = 16'h0003; -defparam \z80_|execute_|setM1~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N16 -cycloneive_lcell_comb \z80_|execute_|setM1~36 ( -// Equation(s): -// \z80_|execute_|setM1~36_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout & (!\z80_|execute_|ctl_mRead~9_combout & (\z80_|execute_|pc_inc_hold~28_combout & \z80_|execute_|setM1~35_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), - .datab(\z80_|execute_|ctl_mRead~9_combout ), - .datac(\z80_|execute_|pc_inc_hold~28_combout ), - .datad(\z80_|execute_|setM1~35_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~36 .lut_mask = 16'h2000; -defparam \z80_|execute_|setM1~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y18_N2 -cycloneive_lcell_comb \z80_|execute_|fMRead~5 ( -// Equation(s): -// \z80_|execute_|fMRead~5_combout = (!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|execute_|ctl_mRead~13_combout & (!\z80_|pla_decode_|Equal52~1_combout & \z80_|execute_|setM1~36_combout ))) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|execute_|ctl_mRead~13_combout ), - .datac(\z80_|pla_decode_|Equal52~1_combout ), - .datad(\z80_|execute_|setM1~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~5 .lut_mask = 16'h0100; -defparam \z80_|execute_|fMRead~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y18_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~31 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~31_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout & (((\z80_|execute_|ctl_bus_inc_oe~29_combout & \z80_|execute_|fMRead~5_combout )) # (!\z80_|execute_|ctl_alu_op_low~8_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~29_combout ), - .datad(\z80_|execute_|fMRead~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~31 .lut_mask = 16'hA222; -defparam \z80_|execute_|ctl_bus_inc_oe~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N20 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~29 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~29_combout = (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T4_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~29 .lut_mask = 16'hC8C8; -defparam \z80_|execute_|pc_inc_hold~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~1 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we~1_combout = (\z80_|execute_|pc_inc_hold~29_combout & ((\z80_|pla_decode_|Equal10~0_combout ) # (\z80_|execute_|ctl_mRead~36_combout ))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|execute_|ctl_mRead~36_combout ), - .datac(gnd), - .datad(\z80_|execute_|pc_inc_hold~29_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we~1 .lut_mask = 16'hEE00; -defparam \z80_|execute_|ctl_reg_sys_we~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we~2_combout = (!\z80_|execute_|ctl_reg_sys_we~1_combout & (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|execute_|ctl_mWrite~16_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|execute_|ctl_reg_sys_we~1_combout ), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|execute_|ctl_mWrite~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we~2 .lut_mask = 16'h1113; -defparam \z80_|execute_|ctl_reg_sys_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N14 -cycloneive_lcell_comb \z80_|pla_decode_|Equal33~3 ( -// Equation(s): -// \z80_|pla_decode_|Equal33~3_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal33~0_combout & (\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|decode_state_|use_ixiy~combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal33~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal33~3 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal33~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we~0_combout = (\z80_|execute_|ixy_d~5_combout & ((\z80_|pla_decode_|Equal33~3_combout ) # ((\z80_|pla_decode_|Equal6~1_combout ) # (!\z80_|execute_|pc_inc_hold~49_combout )))) - - .dataa(\z80_|pla_decode_|Equal33~3_combout ), - .datab(\z80_|execute_|pc_inc_hold~49_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|pla_decode_|Equal6~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we~0 .lut_mask = 16'hF0B0; -defparam \z80_|execute_|ctl_reg_sys_we~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we~3_combout = (((\z80_|execute_|ctl_reg_sys_we~0_combout ) # (\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout )) # (!\z80_|execute_|ctl_reg_sys_we~2_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~31_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~31_combout ), - .datab(\z80_|execute_|ctl_reg_sys_we~2_combout ), - .datac(\z80_|execute_|ctl_reg_sys_we~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we~3 .lut_mask = 16'hFFF7; -defparam \z80_|execute_|ctl_reg_sys_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we_lo~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we_lo~2_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal55~0_combout & \z80_|pla_decode_|Equal6~0_combout )) - - .dataa(\z80_|ir_|opcode [5]), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we_lo~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we_lo~2 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_reg_sys_we_lo~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we_lo~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we_lo~3_combout = (\z80_|execute_|ctl_reg_sys_we_lo~2_combout ) # ((\z80_|pla_decode_|Equal9~1_combout ) # ((\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal8~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|pla_decode_|Equal8~0_combout ), - .datac(\z80_|execute_|ctl_reg_sys_we_lo~2_combout ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we_lo~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we_lo~3 .lut_mask = 16'hFFF8; -defparam \z80_|execute_|ctl_reg_sys_we_lo~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we_lo~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we_lo~4_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|execute_|ctl_reg_sys_we_lo~3_combout & \z80_|sequencer_|DFFE_M2_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|execute_|ctl_reg_sys_we_lo~3_combout ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we_lo~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we_lo~4 .lut_mask = 16'h8080; -defparam \z80_|execute_|ctl_reg_sys_we_lo~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N20 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~combout = (\z80_|execute_|ctl_reg_sys_we~3_combout ) # ((\z80_|execute_|ctl_reg_sys_we_lo~4_combout ) # ((!\z80_|reg_control_|reg_sys_we_lo~7_combout ) # (!\z80_|reg_control_|reg_sys_we_lo~4_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_we~3_combout ), - .datab(\z80_|execute_|ctl_reg_sys_we_lo~4_combout ), - .datac(\z80_|reg_control_|reg_sys_we_lo~4_combout ), - .datad(\z80_|reg_control_|reg_sys_we_lo~7_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo .lut_mask = 16'hEFFF; -defparam \z80_|reg_control_|reg_sys_we_lo .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_ir~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_ir~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_ir~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_ir~0 .lut_mask = 16'h3330; -defparam \z80_|execute_|ctl_reg_sel_ir~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_ir~1 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_ir~1_combout = ((\z80_|execute_|ctl_reg_sel_ir~0_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & !\z80_|execute_|ctl_flags_bus~4_combout ))) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ) - - .dataa(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_flags_bus~4_combout ), - .datad(\z80_|execute_|ctl_reg_sel_ir~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_ir~1 .lut_mask = 16'hFF5D; -defparam \z80_|execute_|ctl_reg_sel_ir~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~9_combout = (\z80_|execute_|ctl_inc_cy~34_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|sequencer_|M5~q ) # (!\z80_|pla_decode_|Equal19~0_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|execute_|ctl_inc_cy~34_combout ), - .datac(\z80_|pla_decode_|Equal19~0_combout ), - .datad(\z80_|sequencer_|M5~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~9 .lut_mask = 16'h8CCC; -defparam \z80_|execute_|ctl_reg_out_lo~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~36 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~36_combout = (\z80_|execute_|ctl_alu_op_low~14_combout ) # ((\z80_|sequencer_|DFFE_T4_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|pla_decode_|Equal48~0_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|pla_decode_|Equal48~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~36 .lut_mask = 16'hF2F0; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~12 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[0]~12_combout = (((\z80_|ir_|opcode [3] & \z80_|execute_|ctl_reg_sys_hilo[1]~36_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout )) # (!\z80_|execute_|ctl_reg_out_lo~9_combout ) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|execute_|ctl_reg_out_lo~9_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~12 .lut_mask = 16'hBF3F; -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout = (\z80_|sequencer_|DFFE_T5_ff~q & \z80_|execute_|ixy_d~15_combout ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T5_ff~q ), - .datac(gnd), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 .lut_mask = 16'hCC00; -defparam \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~4_combout = (\z80_|reg_control_|reg_sel_pc~2_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~4_combout & (\z80_|execute_|ctl_alu_oe~4_combout & !\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ))) - - .dataa(\z80_|reg_control_|reg_sel_pc~2_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), - .datac(\z80_|execute_|ctl_alu_oe~4_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~4 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_in_hi~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~4_combout = ((!\z80_|pla_decode_|Equal34~0_combout & ((!\z80_|pla_decode_|Equal3~1_combout ) # (!\z80_|pla_decode_|Equal19~1_combout )))) # (!\z80_|execute_|ctl_reg_in_hi~2_combout ) - - .dataa(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datab(\z80_|pla_decode_|Equal34~0_combout ), - .datac(\z80_|pla_decode_|Equal19~1_combout ), - .datad(\z80_|pla_decode_|Equal3~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~4 .lut_mask = 16'h5777; -defparam \z80_|execute_|ctl_reg_sel_wz~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|execute_|comb~0_combout & \z80_|execute_|ixy_d~6_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal52~0_combout ), - .datac(\z80_|execute_|comb~0_combout ), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~5_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & (((!\z80_|execute_|ctl_mRead~10_combout & !\z80_|execute_|ctl_mRead~8_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|execute_|ctl_mRead~8_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~5 .lut_mask = 16'h001F; -defparam \z80_|execute_|ctl_reg_sel_wz~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~6_combout = (\z80_|execute_|ctl_reg_sel_wz~4_combout & \z80_|execute_|ctl_reg_sel_wz~5_combout ) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~4_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_sel_wz~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~6 .lut_mask = 16'hAA00; -defparam \z80_|execute_|ctl_reg_sel_wz~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~7_combout = (\z80_|execute_|ctl_bus_db_oe~0_combout & (\z80_|execute_|ctl_reg_in_hi~4_combout & (\z80_|execute_|ctl_reg_in_hi~3_combout & \z80_|execute_|ctl_reg_sel_wz~6_combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_oe~0_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~4_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~3_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~7 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sel_wz~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo~16 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo~16_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|execute_|ctl_mRead~14_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|execute_|ctl_mRead~14_combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo~16 .lut_mask = 16'h80C0; -defparam \z80_|execute_|ctl_reg_sys_hilo~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~11 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~11_combout = (!\z80_|execute_|ctl_reg_sys_hilo~16_combout & (((!\z80_|execute_|ctl_mRead~36_combout & !\z80_|pla_decode_|Equal10~0_combout )) # (!\z80_|execute_|ctl_mWrite~7_combout ))) - - .dataa(\z80_|execute_|ctl_mWrite~7_combout ), - .datab(\z80_|execute_|ctl_mRead~36_combout ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~11 .lut_mask = 16'h0057; -defparam \z80_|execute_|ctl_reg_sel_pc~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~17 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~17_combout = (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~17 .lut_mask = 16'hE0F0; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~12 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~12_combout = (\z80_|execute_|ctl_reg_sel_pc~11_combout & (((\z80_|execute_|ctl_flags_bus~5_combout & \z80_|execute_|ctl_al_we~13_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~11_combout ), - .datab(\z80_|execute_|ctl_flags_bus~5_combout ), - .datac(\z80_|execute_|ctl_al_we~13_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~12 .lut_mask = 16'h80AA; -defparam \z80_|execute_|ctl_reg_sel_pc~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~13 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~13_combout = (\z80_|execute_|ctl_reg_sel_pc~12_combout & (\z80_|execute_|setM1~52_combout & ((!\z80_|pla_decode_|Equal6~1_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~12_combout ), - .datac(\z80_|execute_|setM1~52_combout ), - .datad(\z80_|pla_decode_|Equal6~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~13 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_reg_sel_pc~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~4_combout = (!\z80_|execute_|ctl_mRead~4_combout & (!\z80_|execute_|ixy_d~16_combout & (!\z80_|execute_|ixy_d~10_combout & !\z80_|execute_|ctl_mRead~5_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~4_combout ), - .datab(\z80_|execute_|ixy_d~16_combout ), - .datac(\z80_|execute_|ixy_d~10_combout ), - .datad(\z80_|execute_|ctl_mRead~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~4 .lut_mask = 16'h0001; -defparam \z80_|execute_|ctl_al_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~38 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~38_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ctl_al_we~4_combout )))) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|pla_decode_|Equal34~0_combout ), - .datad(\z80_|execute_|ctl_al_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~38 .lut_mask = 16'h2022; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y18_N24 -cycloneive_lcell_comb \z80_|execute_|fMRead~0 ( -// Equation(s): -// \z80_|execute_|fMRead~0_combout = ((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|fMRead~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~0 .lut_mask = 16'h5D5D; -defparam \z80_|execute_|fMRead~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~24 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~24_combout = (!\z80_|pla_decode_|Equal6~1_combout & (\z80_|execute_|ctl_bus_db_oe~1_combout & !\z80_|pla_decode_|Equal52~1_combout )) - - .dataa(gnd), - .datab(\z80_|pla_decode_|Equal6~1_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .datad(\z80_|pla_decode_|Equal52~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~24 .lut_mask = 16'h0030; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~25 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~25_combout = (!\z80_|execute_|fMRead~0_combout & ((!\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), - .datab(gnd), - .datac(\z80_|execute_|fMRead~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~25 .lut_mask = 16'h050F; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~4 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~4_combout = ((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~4 .lut_mask = 16'h0FAF; -defparam \z80_|execute_|ctl_inc_dec~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~21 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~21_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & (\z80_|execute_|ctl_reg_sys_hilo~20_combout & ((\z80_|execute_|ctl_inc_dec~4_combout ) # (!\z80_|pla_decode_|Equal33~3_combout )))) # -// (!\z80_|execute_|ctl_alu_op_low~8_combout & (((\z80_|execute_|ctl_inc_dec~4_combout ) # (!\z80_|pla_decode_|Equal33~3_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), - .datac(\z80_|execute_|ctl_inc_dec~4_combout ), - .datad(\z80_|pla_decode_|Equal33~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~21 .lut_mask = 16'hD0DD; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~9_combout = (!\z80_|execute_|ctl_ir_we~8_combout & (!\z80_|execute_|ctl_mRead~15_combout & !\z80_|execute_|ctl_ir_we~14_combout )) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_mRead~15_combout ), - .datad(\z80_|execute_|ctl_ir_we~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~9 .lut_mask = 16'h0005; -defparam \z80_|execute_|ctl_reg_sel_wz~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|execute_|ctl_ir_we~12_combout & \z80_|sequencer_|DFFE_M2_ff~q )) +// \z80_|execute_|ixy_d~4_combout = (!\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) .dataa(gnd), .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~22 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~22_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~21_combout & (!\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout & ((\z80_|execute_|ctl_reg_sel_wz~9_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout -// )))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ), - .datac(\z80_|execute_|ctl_reg_sel_wz~9_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~22 .lut_mask = 16'h00C4; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~23 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~23_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout & (((\z80_|execute_|pc_inc_hold~49_combout & !\z80_|pla_decode_|Equal6~1_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~49_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ), - .datac(\z80_|pla_decode_|Equal6~1_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~23 .lut_mask = 16'h08CC; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~8_combout = (!\z80_|execute_|ctl_mRead~17_combout & ((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~17_combout ), - .datab(\z80_|pla_decode_|Equal12~1_combout ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal25~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~8 .lut_mask = 16'h4455; -defparam \z80_|execute_|ctl_reg_sel_wz~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~18 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~18_combout = (!\z80_|execute_|ctl_reg_sel_wz~8_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # ((\z80_|execute_|ctl_state_alu~5_combout ) # (\z80_|execute_|ctl_alu_oe~2_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~8_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_state_alu~5_combout ), - .datad(\z80_|execute_|ctl_alu_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~18 .lut_mask = 16'h5554; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~19 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~19_combout = (!\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout & ((\z80_|execute_|fMRead~0_combout ) # ((!\z80_|execute_|ctl_mRead~9_combout & \z80_|execute_|pc_inc_hold~28_combout )))) - - .dataa(\z80_|execute_|fMRead~0_combout ), - .datab(\z80_|execute_|ctl_mRead~9_combout ), - .datac(\z80_|execute_|pc_inc_hold~28_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~19 .lut_mask = 16'h00BA; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~26 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~26_combout = (!\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout & (\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~26 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~5_combout = (\z80_|execute_|ctl_reg_sel_wz~8_combout & (!\z80_|pla_decode_|Equal34~0_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout & !\z80_|execute_|ctl_mRead~9_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~8_combout ), - .datab(\z80_|pla_decode_|Equal34~0_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), - .datad(\z80_|execute_|ctl_mRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~5 .lut_mask = 16'h0020; -defparam \z80_|execute_|ctl_al_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~27 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~27_combout = (!\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout & ((\z80_|execute_|ctl_al_we~5_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_al_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~27 .lut_mask = 16'h4404; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~28 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~28_combout = (\z80_|execute_|ctl_reg_sel_wz~7_combout & (\z80_|execute_|ctl_reg_sel_pc~13_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~7_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~13_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~28 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~18 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~18_combout = (\z80_|alu_control_|flags_cond_true~q & (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|pla_decode_|Equal35~0_combout ))) - - .dataa(\z80_|alu_control_|flags_cond_true~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|pla_decode_|Equal35~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~18 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sel_wz~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~37 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[0]~37_combout = (\z80_|execute_|ctl_reg_sel_wz~18_combout ) # ((\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|M5~q & \z80_|pla_decode_|Equal9~1_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~37 .lut_mask = 16'hFF80; -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~29 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[0]~29_combout = (\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ) # (((\z80_|execute_|ctl_reg_sys_hilo[0]~37_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~19_combout )) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~19_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~37_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~29 .lut_mask = 16'hFFBF; -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N12 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_62 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_62~combout = (!\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|execute_|ctl_reg_sel_ir~1_combout & \z80_|execute_|ctl_reg_sys_hilo[0]~29_combout )) - - .dataa(gnd), - .datab(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datac(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_62 .lut_mask = 16'h3000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_62 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~38 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~38_combout = ((\z80_|execute_|ctl_ir_we~11_combout ) # ((\z80_|execute_|ctl_mRead~6_combout ) # (\z80_|execute_|ctl_mRead~7_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_mRead~6_combout ), - .datad(\z80_|execute_|ctl_mRead~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~38 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_bus_inc_oe~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~39 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~39_combout = (\z80_|execute_|ctl_mRead~10_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~38_combout ) # ((\z80_|pla_decode_|Equal13~2_combout ) # (\z80_|execute_|ctl_state_alu~14_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~38_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|ctl_state_alu~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~39 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_bus_inc_oe~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~30 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~30_combout = (\z80_|execute_|pc_inc_hold~49_combout & (!\z80_|pla_decode_|Equal6~1_combout & ((!\z80_|pla_decode_|Equal33~2_combout ) # (!\z80_|decode_state_|use_ixiy~combout )))) - - .dataa(\z80_|execute_|pc_inc_hold~49_combout ), - .datab(\z80_|pla_decode_|Equal6~1_combout ), - .datac(\z80_|decode_state_|use_ixiy~combout ), - .datad(\z80_|pla_decode_|Equal33~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~30 .lut_mask = 16'h0222; -defparam \z80_|execute_|ctl_bus_inc_oe~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~45 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~45_combout = (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & ((!\z80_|execute_|nextM~2_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~30_combout )))) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~30_combout ), - .datab(\z80_|execute_|nextM~2_combout ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~45 .lut_mask = 16'h7000; -defparam \z80_|execute_|ctl_bus_inc_oe~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N12 -cycloneive_lcell_comb \z80_|execute_|fMRead~1 ( -// Equation(s): -// \z80_|execute_|fMRead~1_combout = ((!\z80_|pla_decode_|Equal33~0_combout ) # (!\z80_|ir_|opcode [7])) # (!\z80_|execute_|ctl_ir_we~5_combout ) - - .dataa(\z80_|execute_|ctl_ir_we~5_combout ), - .datab(gnd), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~1 .lut_mask = 16'h5FFF; -defparam \z80_|execute_|fMRead~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~36 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~36_combout = (\z80_|execute_|ixy_d~7_combout & (((\z80_|execute_|ctl_mRead~6_combout ) # (\z80_|execute_|ctl_mRead~5_combout )) # (!\z80_|execute_|fMRead~1_combout ))) - - .dataa(\z80_|execute_|fMRead~1_combout ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_mRead~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~36 .lut_mask = 16'hF0D0; -defparam \z80_|execute_|ctl_bus_inc_oe~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~27 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~27_combout = (\z80_|execute_|ctl_ir_we~4_combout & (!\z80_|execute_|ctl_mRead~9_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|execute_|ctl_mWrite~16_combout )))) # (!\z80_|execute_|ctl_ir_we~4_combout & -// (((!\z80_|execute_|ixy_d~5_combout )) # (!\z80_|execute_|ctl_mWrite~16_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ctl_mWrite~16_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|execute_|ctl_mRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~27 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_bus_inc_oe~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~28 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~28_combout = (\z80_|execute_|ctl_bus_inc_oe~47_combout & (\z80_|execute_|ctl_bus_inc_oe~26_combout & \z80_|execute_|ctl_bus_inc_oe~27_combout )) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~47_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_bus_inc_oe~26_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~27_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~28 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_bus_inc_oe~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~37 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~37_combout = (\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ) # ((\z80_|execute_|ctl_bus_inc_oe~36_combout ) # ((!\z80_|execute_|ctl_bus_inc_oe~28_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~46_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~36_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~46_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~28_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~37 .lut_mask = 16'hEFFF; -defparam \z80_|execute_|ctl_bus_inc_oe~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~40 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~40_combout = (\z80_|execute_|ctl_bus_inc_oe~45_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~37_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~39_combout & \z80_|execute_|ctl_ir_we~4_combout ))) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~39_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~45_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~37_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~40 .lut_mask = 16'hFFEC; -defparam \z80_|execute_|ctl_bus_inc_oe~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~35 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~35_combout = ((\z80_|execute_|ctl_alu_oe~2_combout & ((\z80_|execute_|ctl_mRead~6_combout ) # (\z80_|execute_|ctl_mRead~10_combout )))) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout ) - - .dataa(\z80_|execute_|ctl_mRead~6_combout ), - .datab(\z80_|execute_|ctl_alu_oe~2_combout ), - .datac(\z80_|execute_|ctl_mRead~10_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~35 .lut_mask = 16'hC8FF; -defparam \z80_|execute_|ctl_bus_inc_oe~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~77 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~77_combout = (\z80_|execute_|ctl_inc_cy~76_combout & (((!\z80_|execute_|ctl_alu_shift_oe~14_combout & !\z80_|execute_|ctl_sw_4u~0_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|execute_|ctl_sw_4u~0_combout ), - .datac(\z80_|execute_|ctl_inc_cy~76_combout ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~77_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~77 .lut_mask = 16'h10F0; -defparam \z80_|execute_|ctl_inc_cy~77 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~32 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~32_combout = (\z80_|execute_|ixy_d~9_combout & (!\z80_|pla_decode_|Equal11~0_combout & ((!\z80_|pla_decode_|Equal10~0_combout )))) # (!\z80_|execute_|ixy_d~9_combout & (((!\z80_|execute_|ctl_alu_shift_oe~14_combout )) # -// (!\z80_|pla_decode_|Equal11~0_combout ))) - - .dataa(\z80_|execute_|ixy_d~9_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datad(\z80_|pla_decode_|Equal10~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~32 .lut_mask = 16'h1537; -defparam \z80_|execute_|ctl_bus_inc_oe~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M4_ff~q & (\z80_|execute_|ctl_mWrite~2_combout & \z80_|pla_decode_|Equal55~0_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|execute_|ctl_mWrite~2_combout ), - .datad(\z80_|pla_decode_|Equal55~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~33 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~33_combout = (!\z80_|execute_|ctl_reg_sys_we~1_combout & (\z80_|execute_|ctl_bus_inc_oe~32_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout & \z80_|execute_|ctl_bus_inc_oe~24_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_we~1_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~32_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~33 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_bus_inc_oe~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~34 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~34_combout = (((!\z80_|execute_|ctl_bus_inc_oe~33_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[1]~5_combout )) # (!\z80_|execute_|ctl_inc_cy~77_combout )) # (!\z80_|execute_|ctl_inc_cy~53_combout ) - - .dataa(\z80_|execute_|ctl_inc_cy~53_combout ), - .datab(\z80_|execute_|ctl_inc_cy~77_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~34 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_bus_inc_oe~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~41 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~41_combout = (\z80_|execute_|ctl_bus_inc_oe~40_combout ) # (((\z80_|execute_|ctl_bus_inc_oe~35_combout ) # (\z80_|execute_|ctl_bus_inc_oe~34_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~31_combout )) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~40_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~31_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~35_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~34_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~41 .lut_mask = 16'hFFFB; -defparam \z80_|execute_|ctl_bus_inc_oe~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~10 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~10_combout = (\z80_|execute_|ctl_reg_sel_wz~8_combout & ((\z80_|execute_|ctl_reg_sel_wz~9_combout ) # ((!\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|execute_|ctl_reg_sel_wz~8_combout & -// (((!\z80_|execute_|ctl_alu_oe~2_combout & !\z80_|execute_|ctl_ir_we~4_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~9_combout ), - .datab(\z80_|execute_|ctl_alu_oe~2_combout ), - .datac(\z80_|execute_|ctl_reg_sel_wz~8_combout ), - .datad(\z80_|execute_|ctl_ir_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~10 .lut_mask = 16'hA0F3; -defparam \z80_|execute_|ctl_reg_sel_wz~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~11 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~11_combout = (\z80_|execute_|ctl_reg_sel_wz~7_combout & \z80_|execute_|ctl_reg_sel_wz~10_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_sel_wz~7_combout ), - .datac(\z80_|execute_|ctl_reg_sel_wz~10_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~11 .lut_mask = 16'hC0C0; -defparam \z80_|execute_|ctl_reg_sel_wz~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~3 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~3_combout = (\z80_|execute_|ctl_sw_1d~4_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~4_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout )) - - .dataa(\z80_|execute_|ctl_sw_1d~4_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~3 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_sw_4d~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~4 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~4_combout = (\z80_|execute_|ctl_flags_bus~5_combout & (((!\z80_|execute_|ctl_reg_in_hi~2_combout )) # (!\z80_|pla_decode_|Equal9~1_combout ))) # (!\z80_|execute_|ctl_flags_bus~5_combout & (!\z80_|execute_|ixy_d~6_combout & -// ((!\z80_|execute_|ctl_reg_in_hi~2_combout ) # (!\z80_|pla_decode_|Equal9~1_combout )))) - - .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), - .datab(\z80_|pla_decode_|Equal9~1_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~4 .lut_mask = 16'h2A3F; -defparam \z80_|execute_|ctl_sw_4d~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~2 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~2_combout = (\z80_|execute_|ctl_reg_in_lo~9_combout & (\z80_|execute_|fMRead~6_combout & \z80_|execute_|fMRead~8_combout )) - - .dataa(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datab(gnd), - .datac(\z80_|execute_|fMRead~6_combout ), - .datad(\z80_|execute_|fMRead~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~2 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_sw_4d~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~5 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~5_combout = (\z80_|execute_|ctl_reg_sel_wz~11_combout & (\z80_|execute_|ctl_sw_4d~3_combout & (\z80_|execute_|ctl_sw_4d~4_combout & \z80_|execute_|ctl_sw_4d~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~11_combout ), - .datab(\z80_|execute_|ctl_sw_4d~3_combout ), - .datac(\z80_|execute_|ctl_sw_4d~4_combout ), - .datad(\z80_|execute_|ctl_sw_4d~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~5 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_sw_4d~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|setM1~45 ( -// Equation(s): -// \z80_|execute_|setM1~45_combout = (!\z80_|execute_|ctl_iorw~11_combout & (\z80_|execute_|ctl_mRead~19_combout & (!\z80_|execute_|ctl_mRead~13_combout & !\z80_|execute_|ctl_iorw~10_combout ))) - - .dataa(\z80_|execute_|ctl_iorw~11_combout ), - .datab(\z80_|execute_|ctl_mRead~19_combout ), - .datac(\z80_|execute_|ctl_mRead~13_combout ), - .datad(\z80_|execute_|ctl_iorw~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~45 .lut_mask = 16'h0004; -defparam \z80_|execute_|setM1~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N12 -cycloneive_lcell_comb \z80_|execute_|setM1~46 ( -// Equation(s): -// \z80_|execute_|setM1~46_combout = (\z80_|execute_|ctl_al_we~13_combout & (\z80_|execute_|setM1~45_combout & !\z80_|execute_|ctl_mWrite~6_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_al_we~13_combout ), - .datac(\z80_|execute_|setM1~45_combout ), - .datad(\z80_|execute_|ctl_mWrite~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~46 .lut_mask = 16'h00C0; -defparam \z80_|execute_|setM1~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~1 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~1_combout = ((!\z80_|decode_state_|use_ixiy~combout & ((\z80_|pla_decode_|Equal50~0_combout ) # (\z80_|pla_decode_|Equal49~0_combout )))) # (!\z80_|execute_|setM1~46_combout ) - - .dataa(\z80_|pla_decode_|Equal50~0_combout ), - .datab(\z80_|decode_state_|use_ixiy~combout ), - .datac(\z80_|pla_decode_|Equal49~0_combout ), - .datad(\z80_|execute_|setM1~46_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~1 .lut_mask = 16'h32FF; -defparam \z80_|execute_|ctl_sw_4d~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~0 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~0_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ) # ((\z80_|execute_|ctl_reg_sel_wz~18_combout ) # ((\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ctl_al_we~14_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|execute_|ctl_al_we~14_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~0 .lut_mask = 16'hFFAE; -defparam \z80_|execute_|ctl_sw_4d~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~6 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~6_combout = ((\z80_|execute_|ctl_sw_4d~0_combout ) # ((\z80_|execute_|ctl_sw_4d~1_combout & \z80_|execute_|ctl_state_alu~5_combout ))) # (!\z80_|execute_|ctl_sw_4d~5_combout ) - - .dataa(\z80_|execute_|ctl_sw_4d~5_combout ), - .datab(\z80_|execute_|ctl_sw_4d~1_combout ), - .datac(\z80_|execute_|ctl_state_alu~5_combout ), - .datad(\z80_|execute_|ctl_sw_4d~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~6 .lut_mask = 16'hFFD5; -defparam \z80_|execute_|ctl_sw_4d~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N18 -cycloneive_lcell_comb \z80_|execute_|fMRead~4 ( -// Equation(s): -// \z80_|execute_|fMRead~4_combout = (\z80_|execute_|ctl_reg_sel_wz~8_combout & (!\z80_|pla_decode_|Equal34~0_combout & \z80_|execute_|ctl_al_we~4_combout )) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~8_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal34~0_combout ), - .datad(\z80_|execute_|ctl_al_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~4 .lut_mask = 16'h0A00; -defparam \z80_|execute_|fMRead~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~16 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~16_combout = (((\z80_|execute_|ctl_state_alu~5_combout & !\z80_|execute_|fMRead~4_combout )) # (!\z80_|execute_|ctl_reg_sel_pc~10_combout )) # (!\z80_|execute_|ctl_apin_mux~0_combout ) - - .dataa(\z80_|execute_|ctl_apin_mux~0_combout ), - .datab(\z80_|execute_|ctl_state_alu~5_combout ), - .datac(\z80_|execute_|fMRead~4_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~16 .lut_mask = 16'h5DFF; -defparam \z80_|execute_|ctl_reg_sel_pc~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~14 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~14_combout = (!\z80_|pla_decode_|Equal21~1_combout & (((\z80_|decode_state_|table_xx~0_combout ) # (!\z80_|pla_decode_|Equal33~0_combout )) # (!\z80_|pla_decode_|Equal41~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal41~0_combout ), - .datab(\z80_|decode_state_|table_xx~0_combout ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|pla_decode_|Equal21~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~14 .lut_mask = 16'h00DF; -defparam \z80_|execute_|ctl_reg_sel_pc~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~20 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~20_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|pla_decode_|Equal33~3_combout ) # (!\z80_|execute_|ctl_al_we~5_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|execute_|ctl_al_we~5_combout ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|pla_decode_|Equal33~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~20 .lut_mask = 16'h5010; -defparam \z80_|execute_|ctl_reg_sel_pc~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y18_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~15 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~15_combout = (\z80_|execute_|ctl_reg_sel_pc~20_combout ) # ((!\z80_|execute_|fMRead~0_combout & ((!\z80_|execute_|setM1~36_combout ) # (!\z80_|execute_|ctl_reg_sel_pc~14_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~14_combout ), - .datab(\z80_|execute_|setM1~36_combout ), - .datac(\z80_|execute_|ctl_reg_sel_pc~20_combout ), - .datad(\z80_|execute_|fMRead~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~15 .lut_mask = 16'hF0F7; -defparam \z80_|execute_|ctl_reg_sel_pc~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~17 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~17_combout = (!\z80_|nM1_int~2_combout & (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|execute_|ctl_mWrite~16_combout )) # (!\z80_|execute_|ctl_mWrite~7_combout ))) - - .dataa(\z80_|pla_decode_|Equal11~0_combout ), - .datab(\z80_|execute_|ctl_mWrite~7_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_mWrite~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~17 .lut_mask = 16'h0307; -defparam \z80_|execute_|ctl_reg_sel_pc~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~18 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~18_combout = (((!\z80_|execute_|ctl_bus_inc_oe~30_combout & \z80_|execute_|ixy_d~5_combout )) # (!\z80_|execute_|ctl_reg_sel_pc~17_combout )) # (!\z80_|execute_|ctl_sw_4u~1_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~30_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_sw_4u~1_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~18 .lut_mask = 16'h4FFF; -defparam \z80_|execute_|ctl_reg_sel_pc~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~19 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~19_combout = ((\z80_|execute_|ctl_reg_sel_pc~16_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~15_combout ) # (\z80_|execute_|ctl_reg_sel_pc~18_combout ))) # (!\z80_|execute_|ctl_reg_sel_pc~13_combout ) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~13_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~16_combout ), - .datac(\z80_|execute_|ctl_reg_sel_pc~15_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~19 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_reg_sel_pc~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N24 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~3 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_pc~3_combout = (\z80_|reg_control_|reg_sel_pc~2_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~4_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout & \z80_|execute_|ctl_reg_sel_wz~4_combout ))) - - .dataa(\z80_|reg_control_|reg_sel_pc~2_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~4_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_pc~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_pc~3 .lut_mask = 16'h0800; -defparam \z80_|reg_control_|reg_sel_pc~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N18 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc ( -// Equation(s): -// \z80_|reg_control_|reg_sel_pc~combout = (!\z80_|execute_|ctl_reg_sel_wz~18_combout & (\z80_|execute_|ctl_reg_sel_pc~19_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & \z80_|reg_control_|reg_sel_pc~3_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~18_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~19_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .datad(\z80_|reg_control_|reg_sel_pc~3_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_pc~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_pc .lut_mask = 16'h0400; -defparam \z80_|reg_control_|reg_sel_pc .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N8 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_74 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_74~combout = (\z80_|reg_control_|reg_sel_pc~combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout & !\z80_|reg_control_|reg_sys_we_lo~combout )) - - .dataa(gnd), - .datab(\z80_|reg_control_|reg_sel_pc~combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .datad(\z80_|reg_control_|reg_sys_we_lo~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_74 .lut_mask = 16'h00C0; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N22 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~2 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[0]~2_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ) # ((\z80_|execute_|ctl_bus_inc_oe~41_combout ) # ((\z80_|execute_|ctl_sw_4d~6_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|execute_|ctl_sw_4d~6_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[0]~2 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|db_lo_as[0]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N18 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_75 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_75~combout = (\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout & (\z80_|reg_control_|reg_sel_pc~combout & \z80_|reg_control_|reg_sys_we_lo~combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .datac(\z80_|reg_control_|reg_sel_pc~combout ), - .datad(\z80_|reg_control_|reg_sys_we_lo~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_75 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N3 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[7]~24_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N2 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~22 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[7]~22_combout = (\z80_|reg_file_|gdfx_temp0[7]~92_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) # (!\z80_|reg_file_|gdfx_temp0[7]~92_combout & -// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [7]), - .datad(\z80_|execute_|ctl_sw_4d~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[7]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[7]~22 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_lo_as[7]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N28 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_63 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_63~combout = (\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|execute_|ctl_reg_sel_ir~1_combout & \z80_|execute_|ctl_reg_sys_hilo[0]~29_combout )) - - .dataa(gnd), - .datab(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datac(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_63 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y17_N25 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[7]~24_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N14 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~23 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[7]~23_combout = (\z80_|reg_file_|db_lo_as[7]~22_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datac(\z80_|reg_file_|db_lo_as[7]~22_combout ), - .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[7]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[7]~23 .lut_mask = 16'hF030; -defparam \z80_|reg_file_|db_lo_as[7]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N26 -cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_10~0 ( -// Equation(s): -// \z80_|resets_|SYNTHESIZED_WIRE_10~0_combout = !\z80_|resets_|SYNTHESIZED_WIRE_12~q - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h0F0F; -defparam \z80_|resets_|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y17_N27 -dffeas \z80_|resets_|SYNTHESIZED_WIRE_10 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_10 .is_wysiwyg = "true"; -defparam \z80_|resets_|SYNTHESIZED_WIRE_10 .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y17_N9 -dffeas \z80_|resets_|SYNTHESIZED_WIRE_9 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_9 .is_wysiwyg = "true"; -defparam \z80_|resets_|SYNTHESIZED_WIRE_9 .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y17_N29 -dffeas \z80_|resets_|DFFE_intr_ff3 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|resets_|DFFE_intr_ff3~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|resets_|DFFE_intr_ff3 .is_wysiwyg = "true"; -defparam \z80_|resets_|DFFE_intr_ff3 .power_up = "low"; -// synopsys translate_on - -// Location: IOIBUF_X53_Y14_N1 -cycloneive_io_ibuf \KEY[0]~input ( - .i(KEY[0]), - .ibar(gnd), - .o(\KEY[0]~input_o )); -// synopsys translate_off -defparam \KEY[0]~input .bus_hold = "false"; -defparam \KEY[0]~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: LCCOMB_X52_Y14_N4 -cycloneive_lcell_comb reset( -// Equation(s): -// \reset~combout = (!\KEY[0]~input_o ) # (!\ula_|pll_|altpll_component|auto_generated|wire_pll1_locked ) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|pll_|altpll_component|auto_generated|wire_pll1_locked ), - .datad(\KEY[0]~input_o ), - .cin(gnd), - .combout(\reset~combout ), - .cout()); -// synopsys translate_off -defparam reset.lut_mask = 16'h0FFF; -defparam reset.sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N26 -cycloneive_lcell_comb \z80_|resets_|x1~0 ( -// Equation(s): -// \z80_|resets_|x1~0_combout = !\reset~combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\reset~combout ), - .cin(gnd), - .combout(\z80_|resets_|x1~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|resets_|x1~0 .lut_mask = 16'h00FF; -defparam \z80_|resets_|x1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y33_N0 -cycloneive_lcell_comb \z80_|fpga_reset~feeder ( -// Equation(s): -// \z80_|fpga_reset~feeder_combout = VCC - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(gnd), - .cin(gnd), - .combout(\z80_|fpga_reset~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|fpga_reset~feeder .lut_mask = 16'hFFFF; -defparam \z80_|fpga_reset~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y33_N1 -dffeas \z80_|fpga_reset ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|fpga_reset~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|fpga_reset~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|fpga_reset .is_wysiwyg = "true"; -defparam \z80_|fpga_reset .power_up = "low"; -// synopsys translate_on - -// Location: CLKCTRL_G12 -cycloneive_clkctrl \z80_|fpga_reset~clkctrl ( - .ena(vcc), - .inclk({vcc,vcc,vcc,\z80_|fpga_reset~q }), - .clkselect(2'b00), - .devclrn(devclrn), - .devpor(devpor), - .outclk(\z80_|fpga_reset~clkctrl_outclk )); -// synopsys translate_off -defparam \z80_|fpga_reset~clkctrl .clock_type = "global clock"; -defparam \z80_|fpga_reset~clkctrl .ena_register_mode = "none"; -// synopsys translate_on - -// Location: FF_X35_Y13_N27 -dffeas \z80_|resets_|x1 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|resets_|x1~0_combout ), - .asdata(vcc), - .clrn(\z80_|fpga_reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|resets_|x1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|resets_|x1 .is_wysiwyg = "true"; -defparam \z80_|resets_|x1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N18 -cycloneive_lcell_comb \z80_|resets_|clrpc_int~0 ( -// Equation(s): -// \z80_|resets_|clrpc_int~0_combout = (\z80_|sequencer_|DFFE_M1_ff~q & (((\z80_|resets_|clrpc_int~q )))) # (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|resets_|clrpc_int~q & !\z80_|resets_|x1~q )) # -// (!\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|resets_|clrpc_int~q )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|resets_|clrpc_int~q ), - .datad(\z80_|resets_|x1~q ), - .cin(gnd), - .combout(\z80_|resets_|clrpc_int~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|resets_|clrpc_int~0 .lut_mask = 16'hB0B4; -defparam \z80_|resets_|clrpc_int~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y17_N19 -dffeas \z80_|resets_|clrpc_int ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|resets_|clrpc_int~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|resets_|clrpc_int~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|resets_|clrpc_int .is_wysiwyg = "true"; -defparam \z80_|resets_|clrpc_int .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N28 -cycloneive_lcell_comb \z80_|resets_|clrpc~0 ( -// Equation(s): -// \z80_|resets_|clrpc~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_10~q ) # ((\z80_|resets_|SYNTHESIZED_WIRE_9~q ) # ((\z80_|resets_|DFFE_intr_ff3~q ) # (\z80_|resets_|clrpc_int~q ))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), - .datac(\z80_|resets_|DFFE_intr_ff3~q ), - .datad(\z80_|resets_|clrpc_int~q ), - .cin(gnd), - .combout(\z80_|resets_|clrpc~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|resets_|clrpc~0 .lut_mask = 16'hFFFE; -defparam \z80_|resets_|clrpc~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N4 -cycloneive_lcell_comb \z80_|address_latch_|abusz[7] ( -// Equation(s): -// \z80_|address_latch_|abusz [7] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[7]~24_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(\z80_|reg_file_|db_lo_as[7]~24_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [7]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[7] .lut_mask = 16'h0F00; -defparam \z80_|address_latch_|abusz[7] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~1 ( -// Equation(s): -// \z80_|execute_|ctl_apin_mux~1_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (\z80_|sequencer_|DFFE_M2_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_apin_mux~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_apin_mux~1 .lut_mask = 16'h5550; -defparam \z80_|execute_|ctl_apin_mux~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~6_combout = (\z80_|execute_|ctl_apin_mux~1_combout & (((\z80_|pla_decode_|Equal33~3_combout ) # (!\z80_|execute_|ctl_al_we~14_combout )) # (!\z80_|execute_|ctl_al_we~5_combout ))) - - .dataa(\z80_|execute_|ctl_apin_mux~1_combout ), - .datab(\z80_|execute_|ctl_al_we~5_combout ), - .datac(\z80_|execute_|ctl_al_we~14_combout ), - .datad(\z80_|pla_decode_|Equal33~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~6 .lut_mask = 16'hAA2A; -defparam \z80_|execute_|ctl_al_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~7_combout = (\z80_|execute_|ctl_state_alu~6_combout & (((!\z80_|execute_|ctl_flags_bus~5_combout ) # (!\z80_|execute_|ctl_al_we~13_combout )))) # (!\z80_|execute_|ctl_state_alu~6_combout & (\z80_|execute_|ctl_ir_we~4_combout & -// ((!\z80_|execute_|ctl_flags_bus~5_combout ) # (!\z80_|execute_|ctl_al_we~13_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~6_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_al_we~13_combout ), - .datad(\z80_|execute_|ctl_flags_bus~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~7 .lut_mask = 16'h0EEE; -defparam \z80_|execute_|ctl_al_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~8_combout = ((\z80_|execute_|ctl_al_we~7_combout ) # ((\z80_|execute_|ixy_d~6_combout & \z80_|pla_decode_|Equal35~0_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|execute_|ctl_al_we~7_combout ), - .datad(\z80_|pla_decode_|Equal35~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~8 .lut_mask = 16'hFBF3; -defparam \z80_|execute_|ctl_al_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~10_combout = (\z80_|decode_state_|in_halt~q ) # (((!\z80_|pla_decode_|Equal33~1_combout & !\z80_|pla_decode_|Equal33~0_combout )) # (!\z80_|pla_decode_|Equal77~0_combout )) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|decode_state_|in_halt~q ), - .datac(\z80_|pla_decode_|Equal77~0_combout ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~10 .lut_mask = 16'hCFDF; -defparam \z80_|execute_|ctl_alu_oe~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~9 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~9_combout = (((!\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~29_combout )) # (!\z80_|execute_|ctl_al_we~4_combout )) # (!\z80_|execute_|ctl_alu_oe~10_combout ) - - .dataa(\z80_|execute_|ctl_alu_oe~10_combout ), - .datab(\z80_|execute_|ctl_al_we~4_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~29_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~9 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_al_we~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~10 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~10_combout = (\z80_|execute_|ctl_al_we~8_combout ) # ((\z80_|execute_|ctl_state_alu~5_combout & ((\z80_|execute_|ctl_al_we~9_combout ) # (!\z80_|execute_|setM1~45_combout )))) - - .dataa(\z80_|execute_|ctl_al_we~8_combout ), - .datab(\z80_|execute_|ctl_state_alu~5_combout ), - .datac(\z80_|execute_|setM1~45_combout ), - .datad(\z80_|execute_|ctl_al_we~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~10 .lut_mask = 16'hEEAE; -defparam \z80_|execute_|ctl_al_we~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~11 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~11_combout = (\z80_|execute_|ctl_al_we~6_combout ) # ((\z80_|execute_|ctl_al_we~10_combout ) # (!\z80_|execute_|ctl_sw_4d~5_combout )) - - .dataa(\z80_|execute_|ctl_al_we~6_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_sw_4d~5_combout ), - .datad(\z80_|execute_|ctl_al_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~11 .lut_mask = 16'hFFAF; -defparam \z80_|execute_|ctl_al_we~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~12 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~12_combout = (\z80_|execute_|ctl_al_we~11_combout ) # (((\z80_|execute_|ixy_d~7_combout & \z80_|pla_decode_|Equal6~1_combout )) # (!\z80_|execute_|setM1~52_combout )) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_al_we~11_combout ), - .datac(\z80_|execute_|setM1~52_combout ), - .datad(\z80_|pla_decode_|Equal6~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~12 .lut_mask = 16'hEFCF; -defparam \z80_|execute_|ctl_al_we~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y16_N5 -dffeas \z80_|address_latch_|Q[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [7]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[7] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~6 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~6_combout = (\z80_|execute_|ctl_apin_mux~0_combout & (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout & ((!\z80_|execute_|ctl_ir_we~4_combout ) # (!\z80_|pla_decode_|Equal9~1_combout )))) - - .dataa(\z80_|execute_|ctl_apin_mux~0_combout ), - .datab(\z80_|pla_decode_|Equal9~1_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), - .datad(\z80_|execute_|ctl_ir_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~6 .lut_mask = 16'h020A; -defparam \z80_|execute_|ctl_inc_dec~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N24 -cycloneive_lcell_comb \z80_|execute_|fIOWrite~0 ( -// Equation(s): -// \z80_|execute_|fIOWrite~0_combout = ((!\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q ))) # (!\z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), .datac(\z80_|sequencer_|DFFE_T1_ff~q ), .datad(\z80_|sequencer_|DFFE_T2_ff~q ), .cin(gnd), - .combout(\z80_|execute_|fIOWrite~0_combout ), + .combout(\z80_|execute_|ixy_d~4_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fIOWrite~0 .lut_mask = 16'h3373; -defparam \z80_|execute_|fIOWrite~0 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ixy_d~4 .lut_mask = 16'h0030; +defparam \z80_|execute_|ixy_d~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y18_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~8 ( +// Location: LCCOMB_X21_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|ixy_d~11 ( // Equation(s): -// \z80_|execute_|ctl_inc_dec~8_combout = (\z80_|execute_|ctl_mWrite~4_combout & (((\z80_|execute_|ctl_mRead~11_combout ) # (!\z80_|execute_|fIOWrite~0_combout )) # (!\z80_|execute_|ctl_inc_dec~4_combout ))) +// \z80_|execute_|ixy_d~11_combout = (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # ((\z80_|sequencer_|DFFE_T5_ff~q ) # (!\z80_|execute_|ixy_d~4_combout )))) - .dataa(\z80_|execute_|ctl_inc_dec~4_combout ), - .datab(\z80_|execute_|fIOWrite~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|execute_|ctl_mRead~11_combout ), + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T5_ff~q ), + .datad(\z80_|execute_|ixy_d~4_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~8_combout ), + .combout(\z80_|execute_|ixy_d~11_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~8 .lut_mask = 16'hF070; -defparam \z80_|execute_|ctl_inc_dec~8 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ixy_d~11 .lut_mask = 16'hC8CC; +defparam \z80_|execute_|ixy_d~11 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y18_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~9 ( +// Location: LCCOMB_X21_Y14_N6 +cycloneive_lcell_comb \z80_|execute_|ixy_d~9 ( // Equation(s): -// \z80_|execute_|ctl_inc_dec~9_combout = ((\z80_|execute_|ctl_inc_dec~8_combout ) # ((!\z80_|execute_|ctl_reg_gp_we~0_combout & \z80_|ir_|opcode [3]))) # (!\z80_|execute_|ctl_inc_dec~3_combout ) +// \z80_|execute_|ixy_d~9_combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_M3_ff~q ) - .dataa(\z80_|execute_|ctl_reg_gp_we~0_combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|execute_|ctl_inc_dec~3_combout ), - .datad(\z80_|execute_|ctl_inc_dec~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~9 .lut_mask = 16'hFF4F; -defparam \z80_|execute_|ctl_inc_dec~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~10 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~10_combout = (\z80_|execute_|ctl_inc_dec~9_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_inc_dec~6_combout ), - .datac(\z80_|execute_|ctl_inc_dec~9_combout ), + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), .datad(gnd), .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~10_combout ), + .combout(\z80_|execute_|ixy_d~9_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~10 .lut_mask = 16'hF3F3; -defparam \z80_|execute_|ctl_inc_dec~10 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ixy_d~9 .lut_mask = 16'hA0A0; +defparam \z80_|execute_|ixy_d~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y17_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~7 ( +// Location: LCCOMB_X26_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|ixy_d~7 ( // Equation(s): -// \z80_|execute_|ctl_inc_dec~7_combout = (!\z80_|execute_|ctl_bus_inc_oe~33_combout ) # (!\z80_|execute_|ctl_inc_dec~5_combout ) +// \z80_|execute_|ixy_d~7_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M3_ff~q ) - .dataa(\z80_|execute_|ctl_inc_dec~5_combout ), + .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~7_combout ), + .combout(\z80_|execute_|ixy_d~7_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~7 .lut_mask = 16'h55FF; -defparam \z80_|execute_|ctl_inc_dec~7 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ixy_d~7 .lut_mask = 16'h0F00; +defparam \z80_|execute_|ixy_d~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y17_N17 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[2]~9_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [2]), - .prn(vcc)); +// Location: LCCOMB_X24_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|ixy_d~6 ( +// Equation(s): +// \z80_|execute_|ixy_d~6_combout = (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_M3_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~6_combout ), + .cout()); // synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[2] .power_up = "low"; +defparam \z80_|execute_|ixy_d~6 .lut_mask = 16'hA0A0; +defparam \z80_|execute_|ixy_d~6 .sum_lutc_input = "datac"; // synopsys translate_on // Location: LCCOMB_X26_Y13_N8 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_54 ( +cycloneive_lcell_comb \z80_|execute_|ixy_d~8 ( // Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_54~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl2~0_combout )) +// \z80_|execute_|ixy_d~8_combout = (\z80_|sequencer_|DFFE_T5_ff~q & \z80_|sequencer_|DFFE_M3_ff~q ) .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_54 .lut_mask = 16'h0C00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N22 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_58 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_58~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_58 .lut_mask = 16'h0C00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N26 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_55 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_55~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl2~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_55 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y9_N1 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N0 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_59 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_59~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_59 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_59 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y9_N3 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~34 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~34_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (\z80_|reg_file_|b2v_latch_hl2_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (((\z80_|reg_file_|b2v_latch_hl_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]), - .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [2]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~34 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[2]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N28 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_51 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_51~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_de~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_de~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_51 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y13_N11 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N12 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~4 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_de2~4_combout = (\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de2~q & ((\z80_|reg_control_|reg_sel_de2~5_combout ))) # (!\z80_|reg_control_|bank_hl_de2~q & (\z80_|reg_control_|reg_sel_de2~6_combout )))) - - .dataa(\z80_|reg_control_|reg_sel_de2~6_combout ), - .datab(\z80_|reg_control_|reg_sel_de2~5_combout ), - .datac(\z80_|reg_control_|bank_hl_de2~q ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_de2~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_de2~4 .lut_mask = 16'hCA00; -defparam \z80_|reg_control_|reg_sel_de2~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N2 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_46 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_46~combout = (!\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|reg_control_|reg_sel_de2~4_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datac(\z80_|reg_control_|reg_sel_de2~4_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_46 .lut_mask = 16'h3000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N14 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_47 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_47~combout = (\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|reg_control_|reg_sel_de2~4_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datac(\z80_|reg_control_|reg_sel_de2~4_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_47 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y13_N17 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~33 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~33_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [2] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [2] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [2]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~33 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[2]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N26 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 .lut_mask = 16'hF000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N14 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & !\z80_|reg_control_|bank_exx~q ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 .lut_mask = 16'h0010; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y11_N15 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N8 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & \z80_|reg_control_|bank_exx~q ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 .lut_mask = 16'h1000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y11_N25 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~36 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~36_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [2]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [2]), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~36 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[2]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N30 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_83 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_83~combout = (\z80_|execute_|ctl_reg_sel_wz~17_combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout & \z80_|reg_control_|reg_sys_we_lo~combout )) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~17_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), + .datab(\z80_|sequencer_|DFFE_T5_ff~q ), .datac(gnd), - .datad(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .combout(\z80_|execute_|ixy_d~8_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_83 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_83 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ixy_d~8 .lut_mask = 16'hCC00; +defparam \z80_|execute_|ixy_d~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y10_N13 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~37 ( +// Location: LCCOMB_X27_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|ixy_d~12 ( // Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~37_combout = (\z80_|reg_file_|gdfx_temp0[2]~36_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) +// \z80_|execute_|ixy_d~12_combout = (!\z80_|execute_|ixy_d~9_combout & (!\z80_|execute_|ixy_d~7_combout & (!\z80_|execute_|ixy_d~6_combout & !\z80_|execute_|ixy_d~8_combout ))) - .dataa(\z80_|reg_file_|gdfx_temp0[2]~36_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [2]), - .datad(gnd), + .dataa(\z80_|execute_|ixy_d~9_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ixy_d~8_combout ), .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~37_combout ), + .combout(\z80_|execute_|ixy_d~12_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~37 .lut_mask = 16'hA2A2; -defparam \z80_|reg_file_|gdfx_temp0[2]~37 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ixy_d~12 .lut_mask = 16'h0001; +defparam \z80_|execute_|ixy_d~12 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y12_N6 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 ( +// Location: LCCOMB_X29_Y13_N24 +cycloneive_lcell_comb \z80_|pla_decode_|Equal33~0 ( // Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout = (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) +// \z80_|pla_decode_|Equal33~0_combout = (\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [0] & \z80_|ir_|opcode [1])) - .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|ir_|opcode [0]), + .datac(gnd), + .datad(\z80_|ir_|opcode [1]), .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .combout(\z80_|pla_decode_|Equal33~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal33~0 .lut_mask = 16'h2200; +defparam \z80_|pla_decode_|Equal33~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y10_N25 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~39 ( +// Location: LCCOMB_X20_Y17_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal33~1 ( // Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~39_combout = (\z80_|alu_control_|db[2]~29_combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [2]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) # (!\z80_|alu_control_|db[2]~29_combout & -// (!\z80_|execute_|ctl_reg_in_lo~8_combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) +// \z80_|pla_decode_|Equal33~1_combout = (\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [3])) - .dataa(\z80_|alu_control_|db[2]~29_combout ), - .datab(\z80_|reg_file_|b2v_latch_sp_lo|latch [2]), - .datac(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|ir_|opcode [4]), + .datac(gnd), + .datad(\z80_|ir_|opcode [3]), .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~39_combout ), + .combout(\z80_|pla_decode_|Equal33~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~39 .lut_mask = 16'h8CAF; -defparam \z80_|reg_file_|gdfx_temp0[2]~39 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal33~1 .lut_mask = 16'h0088; +defparam \z80_|pla_decode_|Equal33~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y15_N22 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_iy~2 ( +// Location: LCCOMB_X24_Y15_N24 +cycloneive_lcell_comb \z80_|pla_decode_|Equal33~2 ( // Equation(s): -// \z80_|reg_control_|reg_sel_iy~2_combout = (\z80_|decode_state_|DFFE_instIY1~q & (!\z80_|decode_state_|DFFE_inst4~q & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) +// \z80_|pla_decode_|Equal33~2_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal33~1_combout )) - .dataa(\z80_|decode_state_|DFFE_instIY1~q ), - .datab(\z80_|decode_state_|DFFE_inst4~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal33~1_combout ), .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_iy~2_combout ), + .combout(\z80_|pla_decode_|Equal33~2_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_control_|reg_sel_iy~2 .lut_mask = 16'h0020; -defparam \z80_|reg_control_|reg_sel_iy~2 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal33~2 .lut_mask = 16'h8800; +defparam \z80_|pla_decode_|Equal33~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y10_N26 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_70 ( +// Location: LCCOMB_X28_Y19_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal21~0 ( // Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_70~combout = (!\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & \z80_|reg_control_|reg_sel_iy~2_combout )) +// \z80_|pla_decode_|Equal21~0_combout = (\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [3]) .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datad(\z80_|reg_control_|reg_sel_iy~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70 .lut_mask = 16'h3000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N16 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout = (\z80_|decode_state_|DFFE_inst4~q & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 .lut_mask = 16'h0080; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y10_N31 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N24 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_71 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_71~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (\z80_|reg_control_|reg_sel_iy~2_combout & \z80_|execute_|ctl_reg_gp_we~6_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datab(\z80_|reg_control_|reg_sel_iy~2_combout ), + .datab(\z80_|ir_|opcode [4]), .datac(gnd), - .datad(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datad(\z80_|ir_|opcode [3]), .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .combout(\z80_|pla_decode_|Equal21~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal21~0 .lut_mask = 16'h00CC; +defparam \z80_|pla_decode_|Equal21~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y10_N15 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~38 ( +// Location: LCCOMB_X25_Y16_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal77~0 ( // Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~38_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) +// \z80_|pla_decode_|Equal77~0_combout = (!\z80_|decode_state_|DFFE_instCB~q & (!\z80_|decode_state_|DFFE_instED~q & (!\z80_|ir_|opcode [7] & \z80_|ir_|opcode [6]))) - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [2]), - .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [2]), + .dataa(\z80_|decode_state_|DFFE_instCB~q ), + .datab(\z80_|decode_state_|DFFE_instED~q ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|ir_|opcode [6]), .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~38_combout ), + .combout(\z80_|pla_decode_|Equal77~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~38 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[2]~38 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal77~0 .lut_mask = 16'h0100; +defparam \z80_|pla_decode_|Equal77~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y10_N10 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_31 ( +// Location: LCCOMB_X28_Y16_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal77~1 ( // Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_31~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_af2~0_combout )) +// \z80_|pla_decode_|Equal77~1_combout = (\z80_|pla_decode_|Equal21~0_combout & (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal77~0_combout ))) - .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datac(gnd), - .datad(\z80_|reg_control_|reg_sel_af2~0_combout ), + .dataa(\z80_|pla_decode_|Equal21~0_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|pla_decode_|Equal77~0_combout ), .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .combout(\z80_|pla_decode_|Equal77~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_31 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_31 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal77~1 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal77~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y10_N23 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N28 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder ( +// Location: LCCOMB_X28_Y13_N26 +cycloneive_lcell_comb \z80_|pla_decode_|Equal1~7 ( // Equation(s): -// \z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp0[2]~42_combout +// \z80_|pla_decode_|Equal1~7_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [6] & (!\z80_|decode_state_|table_xx~0_combout & \z80_|ir_|opcode [7]))) - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [6]), + .datac(\z80_|decode_state_|table_xx~0_combout ), + .datad(\z80_|ir_|opcode [7]), .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder_combout ), + .combout(\z80_|pla_decode_|Equal1~7_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal1~7 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal1~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y14_N8 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_35 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_35~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_af~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_af~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_35 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N29 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~35 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~35_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [2]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [2]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~35 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[2]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~40 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~40_combout = (\z80_|reg_file_|gdfx_temp0[2]~37_combout & (\z80_|reg_file_|gdfx_temp0[2]~39_combout & (\z80_|reg_file_|gdfx_temp0[2]~38_combout & \z80_|reg_file_|gdfx_temp0[2]~35_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[2]~37_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[2]~39_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[2]~38_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[2]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~40 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[2]~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~41 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~41_combout = (\z80_|reg_file_|gdfx_temp0[2]~34_combout & (\z80_|reg_file_|gdfx_temp0[2]~33_combout & \z80_|reg_file_|gdfx_temp0[2]~40_combout )) - - .dataa(\z80_|reg_file_|gdfx_temp0[2]~34_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[2]~33_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[2]~40_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~41 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|gdfx_temp0[2]~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~42 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~42_combout = ((\z80_|reg_file_|gdfx_temp0[2]~41_combout & ((\z80_|reg_file_|db_lo_as[2]~9_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .datac(\z80_|execute_|ctl_sw_4u~6_combout ), - .datad(\z80_|reg_file_|db_lo_as[2]~9_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~42 .lut_mask = 16'hBB3B; -defparam \z80_|reg_file_|gdfx_temp0[2]~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N21 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[2]~9_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N20 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~7 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[2]~7_combout = (\z80_|reg_file_|gdfx_temp0[2]~42_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # (!\z80_|reg_file_|gdfx_temp0[2]~42_combout & -// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .datab(\z80_|execute_|ctl_sw_4d~6_combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[2]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[2]~7 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|db_lo_as[2]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N26 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~8 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[2]~8_combout = (\z80_|reg_file_|db_lo_as[2]~7_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_lo|latch [2]), - .datad(\z80_|reg_file_|db_lo_as[2]~7_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[2]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[2]~8 .lut_mask = 16'hF300; -defparam \z80_|reg_file_|db_lo_as[2]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y17_N9 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[0]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y13_N13 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y13_N19 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~10 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~10_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [0] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [0] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [0]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~10 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[0]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y13_N29 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N28 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]) # (!\z80_|reg_control_|reg_sel_hl2~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]), - .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y9_N9 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~11 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~11_combout = (\z80_|reg_file_|gdfx_temp0[0]~10_combout & (\z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0_combout & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[0]~10_combout ), - .datab(\z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_hl_lo|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~11 .lut_mask = 16'h8088; -defparam \z80_|reg_file_|gdfx_temp0[0]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y10_N21 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y10_N19 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~15 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~15_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_sp_lo|latch [0]), - .datac(\z80_|reg_file_|b2v_latch_iy_lo|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~15 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp0[0]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y11_N19 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N30 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder_combout = \z80_|reg_file_|gdfx_temp0[0]~22_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y11_N31 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y11_N1 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~14 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~14_combout = (\z80_|reg_file_|b2v_latch_bc_lo|latch [0] & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # (!\z80_|reg_file_|b2v_latch_bc_lo|latch [0] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc_lo|latch [0]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~14 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[0]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~16 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~16_combout = (\z80_|reg_file_|gdfx_temp0[0]~15_combout & (\z80_|reg_file_|gdfx_temp0[0]~14_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[0]~15_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [0]), - .datad(\z80_|reg_file_|gdfx_temp0[0]~14_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~16 .lut_mask = 16'hA200; -defparam \z80_|reg_file_|gdfx_temp0[0]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y11_N1 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~12 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~12_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [0] & ((\z80_|alu_control_|db[0]~12_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (((\z80_|alu_control_|db[0]~12_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [0]), - .datad(\z80_|alu_control_|db[0]~12_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~12 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[0]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N7 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y10_N13 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~13 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~13_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [0]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [0]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~13 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[0]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~17 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~17_combout = (\z80_|reg_file_|gdfx_temp0[0]~11_combout & (\z80_|reg_file_|gdfx_temp0[0]~16_combout & (\z80_|reg_file_|gdfx_temp0[0]~12_combout & \z80_|reg_file_|gdfx_temp0[0]~13_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[0]~11_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~16_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[0]~12_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[0]~13_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~17 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[0]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~22 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~22_combout = ((\z80_|reg_file_|gdfx_temp0[0]~17_combout & ((\z80_|reg_file_|db_lo_as[0]~3_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~17_combout ), - .datac(\z80_|reg_file_|db_lo_as[0]~3_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~22 .lut_mask = 16'hC4FF; -defparam \z80_|reg_file_|gdfx_temp0[0]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N25 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[0]~3_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N24 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~0 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[0]~0_combout = (\z80_|reg_file_|gdfx_temp0[0]~22_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) # (!\z80_|reg_file_|gdfx_temp0[0]~22_combout & -// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [0]), - .datad(\z80_|execute_|ctl_sw_4d~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[0]~0 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_lo_as[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N22 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~1 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[0]~1_combout = (\z80_|reg_file_|db_lo_as[0]~0_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|b2v_latch_ir_lo|latch [0]), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datad(\z80_|reg_file_|db_lo_as[0]~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[0]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[0]~1 .lut_mask = 16'hCF00; -defparam \z80_|reg_file_|db_lo_as[0]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~72 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~72_combout = (!\z80_|nM1_int~2_combout & (((!\z80_|execute_|ctl_alu_op_low~8_combout & !\z80_|execute_|ixy_d~5_combout )) # (!\z80_|pla_decode_|Equal41~2_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|pla_decode_|Equal41~2_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~72_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~72 .lut_mask = 16'h0515; -defparam \z80_|execute_|ctl_inc_cy~72 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: CLKCTRL_G18 -cycloneive_clkctrl \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl ( - .ena(vcc), - .inclk({vcc,vcc,vcc,\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk [0]}), - .clkselect(2'b00), - .devclrn(devclrn), - .devpor(devpor), - .outclk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk )); -// synopsys translate_off -defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .clock_type = "global clock"; -defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .ena_register_mode = "none"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N16 -cycloneive_lcell_comb \ula_|video_|Add0~14 ( -// Equation(s): -// \ula_|video_|Add0~14_combout = (\ula_|video_|vga_hc [7] & (!\ula_|video_|Add0~13 )) # (!\ula_|video_|vga_hc [7] & ((\ula_|video_|Add0~13 ) # (GND))) -// \ula_|video_|Add0~15 = CARRY((!\ula_|video_|Add0~13 ) # (!\ula_|video_|vga_hc [7])) - - .dataa(gnd), - .datab(\ula_|video_|vga_hc [7]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add0~13 ), - .combout(\ula_|video_|Add0~14_combout ), - .cout(\ula_|video_|Add0~15 )); -// synopsys translate_off -defparam \ula_|video_|Add0~14 .lut_mask = 16'h3C3F; -defparam \ula_|video_|Add0~14 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N18 -cycloneive_lcell_comb \ula_|video_|Add0~16 ( -// Equation(s): -// \ula_|video_|Add0~16_combout = (\ula_|video_|vga_hc [8] & (\ula_|video_|Add0~15 $ (GND))) # (!\ula_|video_|vga_hc [8] & (!\ula_|video_|Add0~15 & VCC)) -// \ula_|video_|Add0~17 = CARRY((\ula_|video_|vga_hc [8] & !\ula_|video_|Add0~15 )) - - .dataa(\ula_|video_|vga_hc [8]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add0~15 ), - .combout(\ula_|video_|Add0~16_combout ), - .cout(\ula_|video_|Add0~17 )); -// synopsys translate_off -defparam \ula_|video_|Add0~16 .lut_mask = 16'hA50A; -defparam \ula_|video_|Add0~16 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N26 -cycloneive_lcell_comb \ula_|video_|vga_hc~2 ( -// Equation(s): -// \ula_|video_|vga_hc~2_combout = (\ula_|video_|Equal1~0_combout & \ula_|video_|Add0~16_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|video_|Equal1~0_combout ), - .datad(\ula_|video_|Add0~16_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_hc~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_hc~2 .lut_mask = 16'hF000; -defparam \ula_|video_|vga_hc~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y33_N27 -dffeas \ula_|video_|vga_hc[8] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_hc~2_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_hc [8]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_hc[8] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_hc[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N20 -cycloneive_lcell_comb \ula_|video_|Add0~18 ( -// Equation(s): -// \ula_|video_|Add0~18_combout = \ula_|video_|Add0~17 $ (\ula_|video_|vga_hc [9]) - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|vga_hc [9]), - .cin(\ula_|video_|Add0~17 ), - .combout(\ula_|video_|Add0~18_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Add0~18 .lut_mask = 16'h0FF0; -defparam \ula_|video_|Add0~18 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y33_N20 -cycloneive_lcell_comb \ula_|video_|vga_hc~1 ( -// Equation(s): -// \ula_|video_|vga_hc~1_combout = (\ula_|video_|Equal1~0_combout & \ula_|video_|Add0~18_combout ) - - .dataa(gnd), - .datab(\ula_|video_|Equal1~0_combout ), - .datac(gnd), - .datad(\ula_|video_|Add0~18_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_hc~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_hc~1 .lut_mask = 16'hCC00; -defparam \ula_|video_|vga_hc~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y33_N21 -dffeas \ula_|video_|vga_hc[9] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_hc~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_hc [9]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_hc[9] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_hc[9] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N2 -cycloneive_lcell_comb \ula_|video_|Add0~0 ( -// Equation(s): -// \ula_|video_|Add0~0_combout = \ula_|video_|vga_hc [0] $ (VCC) -// \ula_|video_|Add0~1 = CARRY(\ula_|video_|vga_hc [0]) - - .dataa(gnd), - .datab(\ula_|video_|vga_hc [0]), - .datac(gnd), - .datad(vcc), - .cin(gnd), - .combout(\ula_|video_|Add0~0_combout ), - .cout(\ula_|video_|Add0~1 )); -// synopsys translate_off -defparam \ula_|video_|Add0~0 .lut_mask = 16'h33CC; -defparam \ula_|video_|Add0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N0 -cycloneive_lcell_comb \ula_|video_|vga_hc~3 ( -// Equation(s): -// \ula_|video_|vga_hc~3_combout = (\ula_|video_|Add0~0_combout & \ula_|video_|Equal1~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|video_|Add0~0_combout ), - .datad(\ula_|video_|Equal1~0_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_hc~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_hc~3 .lut_mask = 16'hF000; -defparam \ula_|video_|vga_hc~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y31_N1 -dffeas \ula_|video_|vga_hc[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_hc~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_hc [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_hc[0] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_hc[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N4 -cycloneive_lcell_comb \ula_|video_|Add0~2 ( -// Equation(s): -// \ula_|video_|Add0~2_combout = (\ula_|video_|vga_hc [1] & (!\ula_|video_|Add0~1 )) # (!\ula_|video_|vga_hc [1] & ((\ula_|video_|Add0~1 ) # (GND))) -// \ula_|video_|Add0~3 = CARRY((!\ula_|video_|Add0~1 ) # (!\ula_|video_|vga_hc [1])) - - .dataa(gnd), - .datab(\ula_|video_|vga_hc [1]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add0~1 ), - .combout(\ula_|video_|Add0~2_combout ), - .cout(\ula_|video_|Add0~3 )); -// synopsys translate_off -defparam \ula_|video_|Add0~2 .lut_mask = 16'h3C3F; -defparam \ula_|video_|Add0~2 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y33_N16 -cycloneive_lcell_comb \ula_|video_|vga_hc[1]~feeder ( -// Equation(s): -// \ula_|video_|vga_hc[1]~feeder_combout = \ula_|video_|Add0~2_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|Add0~2_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_hc[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_hc[1]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|vga_hc[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y33_N17 -dffeas \ula_|video_|vga_hc[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_hc[1]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_hc [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_hc[1] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_hc[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N6 -cycloneive_lcell_comb \ula_|video_|Add0~4 ( -// Equation(s): -// \ula_|video_|Add0~4_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|Add0~3 $ (GND))) # (!\ula_|video_|vga_hc [2] & (!\ula_|video_|Add0~3 & VCC)) -// \ula_|video_|Add0~5 = CARRY((\ula_|video_|vga_hc [2] & !\ula_|video_|Add0~3 )) - - .dataa(gnd), - .datab(\ula_|video_|vga_hc [2]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add0~3 ), - .combout(\ula_|video_|Add0~4_combout ), - .cout(\ula_|video_|Add0~5 )); -// synopsys translate_off -defparam \ula_|video_|Add0~4 .lut_mask = 16'hC30C; -defparam \ula_|video_|Add0~4 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y33_N23 -dffeas \ula_|video_|vga_hc[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|Add0~4_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_hc [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_hc[2] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_hc[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N8 -cycloneive_lcell_comb \ula_|video_|Add0~6 ( -// Equation(s): -// \ula_|video_|Add0~6_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|Add0~5 )) # (!\ula_|video_|vga_hc [3] & ((\ula_|video_|Add0~5 ) # (GND))) -// \ula_|video_|Add0~7 = CARRY((!\ula_|video_|Add0~5 ) # (!\ula_|video_|vga_hc [3])) - - .dataa(gnd), - .datab(\ula_|video_|vga_hc [3]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add0~5 ), - .combout(\ula_|video_|Add0~6_combout ), - .cout(\ula_|video_|Add0~7 )); -// synopsys translate_off -defparam \ula_|video_|Add0~6 .lut_mask = 16'h3C3F; -defparam \ula_|video_|Add0~6 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y33_N8 -cycloneive_lcell_comb \ula_|video_|vga_hc[3]~feeder ( -// Equation(s): -// \ula_|video_|vga_hc[3]~feeder_combout = \ula_|video_|Add0~6_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|Add0~6_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_hc[3]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_hc[3]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|vga_hc[3]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y33_N9 -dffeas \ula_|video_|vga_hc[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_hc[3]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_hc [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_hc[3] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_hc[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N10 -cycloneive_lcell_comb \ula_|video_|Add0~8 ( -// Equation(s): -// \ula_|video_|Add0~8_combout = (\ula_|video_|vga_hc [4] & (\ula_|video_|Add0~7 $ (GND))) # (!\ula_|video_|vga_hc [4] & (!\ula_|video_|Add0~7 & VCC)) -// \ula_|video_|Add0~9 = CARRY((\ula_|video_|vga_hc [4] & !\ula_|video_|Add0~7 )) - - .dataa(\ula_|video_|vga_hc [4]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add0~7 ), - .combout(\ula_|video_|Add0~8_combout ), - .cout(\ula_|video_|Add0~9 )); -// synopsys translate_off -defparam \ula_|video_|Add0~8 .lut_mask = 16'hA50A; -defparam \ula_|video_|Add0~8 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y33_N31 -dffeas \ula_|video_|vga_hc[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|Add0~8_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_hc [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_hc[4] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_hc[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N18 -cycloneive_lcell_comb \ula_|video_|Equal0~0 ( -// Equation(s): -// \ula_|video_|Equal0~0_combout = (!\ula_|video_|vga_hc [2] & (!\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [1] & !\ula_|video_|vga_hc [0]))) - - .dataa(\ula_|video_|vga_hc [2]), - .datab(\ula_|video_|vga_hc [3]), - .datac(\ula_|video_|vga_hc [1]), - .datad(\ula_|video_|vga_hc [0]), - .cin(gnd), - .combout(\ula_|video_|Equal0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Equal0~0 .lut_mask = 16'h0001; -defparam \ula_|video_|Equal0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N30 -cycloneive_lcell_comb \ula_|video_|Equal0~1 ( -// Equation(s): -// \ula_|video_|Equal0~1_combout = (\ula_|video_|vga_hc [5] & (!\ula_|video_|vga_hc [7] & (!\ula_|video_|vga_hc [4] & \ula_|video_|Equal0~0_combout ))) - - .dataa(\ula_|video_|vga_hc [5]), - .datab(\ula_|video_|vga_hc [7]), - .datac(\ula_|video_|vga_hc [4]), - .datad(\ula_|video_|Equal0~0_combout ), - .cin(gnd), - .combout(\ula_|video_|Equal0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Equal0~1 .lut_mask = 16'h0200; -defparam \ula_|video_|Equal0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y33_N16 -cycloneive_lcell_comb \ula_|video_|Equal1~0 ( -// Equation(s): -// \ula_|video_|Equal1~0_combout = (((\ula_|video_|vga_hc [6]) # (!\ula_|video_|Equal0~1_combout )) # (!\ula_|video_|vga_hc [8])) # (!\ula_|video_|vga_hc [9]) - - .dataa(\ula_|video_|vga_hc [9]), - .datab(\ula_|video_|vga_hc [8]), - .datac(\ula_|video_|vga_hc [6]), - .datad(\ula_|video_|Equal0~1_combout ), - .cin(gnd), - .combout(\ula_|video_|Equal1~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Equal1~0 .lut_mask = 16'hF7FF; -defparam \ula_|video_|Equal1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N12 -cycloneive_lcell_comb \ula_|video_|Add0~10 ( -// Equation(s): -// \ula_|video_|Add0~10_combout = (\ula_|video_|vga_hc [5] & (!\ula_|video_|Add0~9 )) # (!\ula_|video_|vga_hc [5] & ((\ula_|video_|Add0~9 ) # (GND))) -// \ula_|video_|Add0~11 = CARRY((!\ula_|video_|Add0~9 ) # (!\ula_|video_|vga_hc [5])) - - .dataa(\ula_|video_|vga_hc [5]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add0~9 ), - .combout(\ula_|video_|Add0~10_combout ), - .cout(\ula_|video_|Add0~11 )); -// synopsys translate_off -defparam \ula_|video_|Add0~10 .lut_mask = 16'h5A5F; -defparam \ula_|video_|Add0~10 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N0 -cycloneive_lcell_comb \ula_|video_|vga_hc~0 ( -// Equation(s): -// \ula_|video_|vga_hc~0_combout = (\ula_|video_|Equal1~0_combout & \ula_|video_|Add0~10_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|video_|Equal1~0_combout ), - .datad(\ula_|video_|Add0~10_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_hc~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_hc~0 .lut_mask = 16'hF000; -defparam \ula_|video_|vga_hc~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y33_N1 -dffeas \ula_|video_|vga_hc[5] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_hc~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_hc [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_hc[5] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_hc[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N14 -cycloneive_lcell_comb \ula_|video_|Add0~12 ( -// Equation(s): -// \ula_|video_|Add0~12_combout = (\ula_|video_|vga_hc [6] & (\ula_|video_|Add0~11 $ (GND))) # (!\ula_|video_|vga_hc [6] & (!\ula_|video_|Add0~11 & VCC)) -// \ula_|video_|Add0~13 = CARRY((\ula_|video_|vga_hc [6] & !\ula_|video_|Add0~11 )) - - .dataa(\ula_|video_|vga_hc [6]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add0~11 ), - .combout(\ula_|video_|Add0~12_combout ), - .cout(\ula_|video_|Add0~13 )); -// synopsys translate_off -defparam \ula_|video_|Add0~12 .lut_mask = 16'hA50A; -defparam \ula_|video_|Add0~12 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y33_N29 -dffeas \ula_|video_|vga_hc[6] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|Add0~12_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_hc [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_hc[6] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_hc[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X39_Y33_N25 -dffeas \ula_|video_|vga_hc[7] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|Add0~14_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_hc [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_hc[7] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_hc[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y33_N0 -cycloneive_lcell_comb \ula_|video_|Add1~0 ( -// Equation(s): -// \ula_|video_|Add1~0_combout = \ula_|video_|vga_vc [0] $ (VCC) -// \ula_|video_|Add1~1 = CARRY(\ula_|video_|vga_vc [0]) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [0]), - .datac(gnd), - .datad(vcc), - .cin(gnd), - .combout(\ula_|video_|Add1~0_combout ), - .cout(\ula_|video_|Add1~1 )); -// synopsys translate_off -defparam \ula_|video_|Add1~0 .lut_mask = 16'h33CC; -defparam \ula_|video_|Add1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y33_N2 -cycloneive_lcell_comb \ula_|video_|Add1~2 ( -// Equation(s): -// \ula_|video_|Add1~2_combout = (\ula_|video_|vga_vc [1] & (!\ula_|video_|Add1~1 )) # (!\ula_|video_|vga_vc [1] & ((\ula_|video_|Add1~1 ) # (GND))) -// \ula_|video_|Add1~3 = CARRY((!\ula_|video_|Add1~1 ) # (!\ula_|video_|vga_vc [1])) - - .dataa(\ula_|video_|vga_vc [1]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add1~1 ), - .combout(\ula_|video_|Add1~2_combout ), - .cout(\ula_|video_|Add1~3 )); -// synopsys translate_off -defparam \ula_|video_|Add1~2 .lut_mask = 16'h5A5F; -defparam \ula_|video_|Add1~2 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y33_N4 -cycloneive_lcell_comb \ula_|video_|Add1~4 ( -// Equation(s): -// \ula_|video_|Add1~4_combout = (\ula_|video_|vga_vc [2] & (\ula_|video_|Add1~3 $ (GND))) # (!\ula_|video_|vga_vc [2] & (!\ula_|video_|Add1~3 & VCC)) -// \ula_|video_|Add1~5 = CARRY((\ula_|video_|vga_vc [2] & !\ula_|video_|Add1~3 )) - - .dataa(\ula_|video_|vga_vc [2]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add1~3 ), - .combout(\ula_|video_|Add1~4_combout ), - .cout(\ula_|video_|Add1~5 )); -// synopsys translate_off -defparam \ula_|video_|Add1~4 .lut_mask = 16'hA50A; -defparam \ula_|video_|Add1~4 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N12 -cycloneive_lcell_comb \ula_|video_|vga_vc[2]~2 ( -// Equation(s): -// \ula_|video_|vga_vc[2]~2_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [2]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~4_combout )))) - - .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Add1~4_combout ), - .datac(\ula_|video_|vga_vc [2]), - .datad(\ula_|video_|Equal3~1_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[2]~2 .lut_mask = 16'h00E4; -defparam \ula_|video_|vga_vc[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y33_N13 -dffeas \ula_|video_|vga_vc[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[2]~2_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[2] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y33_N6 -cycloneive_lcell_comb \ula_|video_|Add1~6 ( -// Equation(s): -// \ula_|video_|Add1~6_combout = (\ula_|video_|vga_vc [3] & (!\ula_|video_|Add1~5 )) # (!\ula_|video_|vga_vc [3] & ((\ula_|video_|Add1~5 ) # (GND))) -// \ula_|video_|Add1~7 = CARRY((!\ula_|video_|Add1~5 ) # (!\ula_|video_|vga_vc [3])) - - .dataa(\ula_|video_|vga_vc [3]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add1~5 ), - .combout(\ula_|video_|Add1~6_combout ), - .cout(\ula_|video_|Add1~7 )); -// synopsys translate_off -defparam \ula_|video_|Add1~6 .lut_mask = 16'h5A5F; -defparam \ula_|video_|Add1~6 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y33_N20 -cycloneive_lcell_comb \ula_|video_|vga_vc[3]~3 ( -// Equation(s): -// \ula_|video_|vga_vc[3]~3_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [3])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~6_combout ))))) - - .dataa(\ula_|video_|Equal3~1_combout ), - .datab(\ula_|video_|Equal1~0_combout ), - .datac(\ula_|video_|vga_vc [3]), - .datad(\ula_|video_|Add1~6_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[3]~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[3]~3 .lut_mask = 16'h5140; -defparam \ula_|video_|vga_vc[3]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y33_N3 -dffeas \ula_|video_|vga_vc[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|vga_vc[3]~3_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[3] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y33_N8 -cycloneive_lcell_comb \ula_|video_|Add1~8 ( -// Equation(s): -// \ula_|video_|Add1~8_combout = (\ula_|video_|vga_vc [4] & (\ula_|video_|Add1~7 $ (GND))) # (!\ula_|video_|vga_vc [4] & (!\ula_|video_|Add1~7 & VCC)) -// \ula_|video_|Add1~9 = CARRY((\ula_|video_|vga_vc [4] & !\ula_|video_|Add1~7 )) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [4]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add1~7 ), - .combout(\ula_|video_|Add1~8_combout ), - .cout(\ula_|video_|Add1~9 )); -// synopsys translate_off -defparam \ula_|video_|Add1~8 .lut_mask = 16'hC30C; -defparam \ula_|video_|Add1~8 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N20 -cycloneive_lcell_comb \ula_|video_|vga_vc[4]~5 ( -// Equation(s): -// \ula_|video_|vga_vc[4]~5_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [4]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~8_combout )))) - - .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Add1~8_combout ), - .datac(\ula_|video_|vga_vc [4]), - .datad(\ula_|video_|Equal3~1_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[4]~5_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[4]~5 .lut_mask = 16'h00E4; -defparam \ula_|video_|vga_vc[4]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y33_N21 -dffeas \ula_|video_|vga_vc[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[4]~5_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[4] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y33_N10 -cycloneive_lcell_comb \ula_|video_|Add1~10 ( -// Equation(s): -// \ula_|video_|Add1~10_combout = (\ula_|video_|vga_vc [5] & (!\ula_|video_|Add1~9 )) # (!\ula_|video_|vga_vc [5] & ((\ula_|video_|Add1~9 ) # (GND))) -// \ula_|video_|Add1~11 = CARRY((!\ula_|video_|Add1~9 ) # (!\ula_|video_|vga_vc [5])) - - .dataa(\ula_|video_|vga_vc [5]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add1~9 ), - .combout(\ula_|video_|Add1~10_combout ), - .cout(\ula_|video_|Add1~11 )); -// synopsys translate_off -defparam \ula_|video_|Add1~10 .lut_mask = 16'h5A5F; -defparam \ula_|video_|Add1~10 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y33_N22 -cycloneive_lcell_comb \ula_|video_|vga_vc[5]~8 ( -// Equation(s): -// \ula_|video_|vga_vc[5]~8_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [5])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~10_combout ))))) - - .dataa(\ula_|video_|Equal3~1_combout ), - .datab(\ula_|video_|Equal1~0_combout ), - .datac(\ula_|video_|vga_vc [5]), - .datad(\ula_|video_|Add1~10_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[5]~8_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[5]~8 .lut_mask = 16'h5140; -defparam \ula_|video_|vga_vc[5]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y33_N17 -dffeas \ula_|video_|vga_vc[5] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|vga_vc[5]~8_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[5] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y33_N12 -cycloneive_lcell_comb \ula_|video_|Add1~12 ( -// Equation(s): -// \ula_|video_|Add1~12_combout = (\ula_|video_|vga_vc [6] & (\ula_|video_|Add1~11 $ (GND))) # (!\ula_|video_|vga_vc [6] & (!\ula_|video_|Add1~11 & VCC)) -// \ula_|video_|Add1~13 = CARRY((\ula_|video_|vga_vc [6] & !\ula_|video_|Add1~11 )) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [6]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add1~11 ), - .combout(\ula_|video_|Add1~12_combout ), - .cout(\ula_|video_|Add1~13 )); -// synopsys translate_off -defparam \ula_|video_|Add1~12 .lut_mask = 16'hC30C; -defparam \ula_|video_|Add1~12 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N6 -cycloneive_lcell_comb \ula_|video_|vga_vc[6]~4 ( -// Equation(s): -// \ula_|video_|vga_vc[6]~4_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [6]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~12_combout )))) - - .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Add1~12_combout ), - .datac(\ula_|video_|vga_vc [6]), - .datad(\ula_|video_|Equal3~1_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[6]~4_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[6]~4 .lut_mask = 16'h00E4; -defparam \ula_|video_|vga_vc[6]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y33_N7 -dffeas \ula_|video_|vga_vc[6] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[6]~4_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[6] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y33_N14 -cycloneive_lcell_comb \ula_|video_|Add1~14 ( -// Equation(s): -// \ula_|video_|Add1~14_combout = (\ula_|video_|vga_vc [7] & (!\ula_|video_|Add1~13 )) # (!\ula_|video_|vga_vc [7] & ((\ula_|video_|Add1~13 ) # (GND))) -// \ula_|video_|Add1~15 = CARRY((!\ula_|video_|Add1~13 ) # (!\ula_|video_|vga_vc [7])) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [7]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add1~13 ), - .combout(\ula_|video_|Add1~14_combout ), - .cout(\ula_|video_|Add1~15 )); -// synopsys translate_off -defparam \ula_|video_|Add1~14 .lut_mask = 16'h3C3F; -defparam \ula_|video_|Add1~14 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N14 -cycloneive_lcell_comb \ula_|video_|vga_vc[7]~6 ( -// Equation(s): -// \ula_|video_|vga_vc[7]~6_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [7]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~14_combout )))) - - .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Add1~14_combout ), - .datac(\ula_|video_|vga_vc [7]), - .datad(\ula_|video_|Equal3~1_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[7]~6_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[7]~6 .lut_mask = 16'h00E4; -defparam \ula_|video_|vga_vc[7]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y33_N15 -dffeas \ula_|video_|vga_vc[7] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[7]~6_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[7] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y33_N16 -cycloneive_lcell_comb \ula_|video_|Add1~16 ( -// Equation(s): -// \ula_|video_|Add1~16_combout = (\ula_|video_|vga_vc [8] & (\ula_|video_|Add1~15 $ (GND))) # (!\ula_|video_|vga_vc [8] & (!\ula_|video_|Add1~15 & VCC)) -// \ula_|video_|Add1~17 = CARRY((\ula_|video_|vga_vc [8] & !\ula_|video_|Add1~15 )) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [8]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add1~15 ), - .combout(\ula_|video_|Add1~16_combout ), - .cout(\ula_|video_|Add1~17 )); -// synopsys translate_off -defparam \ula_|video_|Add1~16 .lut_mask = 16'hC30C; -defparam \ula_|video_|Add1~16 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N24 -cycloneive_lcell_comb \ula_|video_|vga_vc[8]~7 ( -// Equation(s): -// \ula_|video_|vga_vc[8]~7_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [8]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~16_combout )))) - - .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Add1~16_combout ), - .datac(\ula_|video_|vga_vc [8]), - .datad(\ula_|video_|Equal3~1_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[8]~7_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[8]~7 .lut_mask = 16'h00E4; -defparam \ula_|video_|vga_vc[8]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y33_N25 -dffeas \ula_|video_|vga_vc[8] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[8]~7_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [8]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[8] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y33_N18 -cycloneive_lcell_comb \ula_|video_|Add1~18 ( -// Equation(s): -// \ula_|video_|Add1~18_combout = \ula_|video_|Add1~17 $ (\ula_|video_|vga_vc [9]) - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|vga_vc [9]), - .cin(\ula_|video_|Add1~17 ), - .combout(\ula_|video_|Add1~18_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Add1~18 .lut_mask = 16'h0FF0; -defparam \ula_|video_|Add1~18 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N10 -cycloneive_lcell_comb \ula_|video_|vga_vc[9]~9 ( -// Equation(s): -// \ula_|video_|vga_vc[9]~9_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [9]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~18_combout )))) - - .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Add1~18_combout ), - .datac(\ula_|video_|vga_vc [9]), - .datad(\ula_|video_|Equal3~1_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[9]~9_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[9]~9 .lut_mask = 16'h00E4; -defparam \ula_|video_|vga_vc[9]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y33_N11 -dffeas \ula_|video_|vga_vc[9] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[9]~9_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [9]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[9] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[9] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N18 -cycloneive_lcell_comb \ula_|video_|Equal2~0 ( -// Equation(s): -// \ula_|video_|Equal2~0_combout = (!\ula_|video_|vga_vc [6] & (!\ula_|video_|vga_vc [4] & (!\ula_|video_|vga_vc [7] & !\ula_|video_|vga_vc [8]))) - - .dataa(\ula_|video_|vga_vc [6]), - .datab(\ula_|video_|vga_vc [4]), - .datac(\ula_|video_|vga_vc [7]), - .datad(\ula_|video_|vga_vc [8]), - .cin(gnd), - .combout(\ula_|video_|Equal2~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Equal2~0 .lut_mask = 16'h0001; -defparam \ula_|video_|Equal2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y33_N30 -cycloneive_lcell_comb \ula_|video_|Equal3~0 ( -// Equation(s): -// \ula_|video_|Equal3~0_combout = (\ula_|video_|vga_vc [3] & (\ula_|video_|vga_vc [2] & (!\ula_|video_|vga_vc [1] & \ula_|video_|vga_vc [0]))) - - .dataa(\ula_|video_|vga_vc [3]), - .datab(\ula_|video_|vga_vc [2]), - .datac(\ula_|video_|vga_vc [1]), - .datad(\ula_|video_|vga_vc [0]), - .cin(gnd), - .combout(\ula_|video_|Equal3~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Equal3~0 .lut_mask = 16'h0800; -defparam \ula_|video_|Equal3~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y33_N18 -cycloneive_lcell_comb \ula_|video_|Equal3~1 ( -// Equation(s): -// \ula_|video_|Equal3~1_combout = (!\ula_|video_|vga_vc [5] & (\ula_|video_|vga_vc [9] & (\ula_|video_|Equal2~0_combout & \ula_|video_|Equal3~0_combout ))) - - .dataa(\ula_|video_|vga_vc [5]), - .datab(\ula_|video_|vga_vc [9]), - .datac(\ula_|video_|Equal2~0_combout ), - .datad(\ula_|video_|Equal3~0_combout ), - .cin(gnd), - .combout(\ula_|video_|Equal3~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Equal3~1 .lut_mask = 16'h4000; -defparam \ula_|video_|Equal3~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N28 -cycloneive_lcell_comb \ula_|video_|vga_vc[0]~0 ( -// Equation(s): -// \ula_|video_|vga_vc[0]~0_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [0]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~0_combout )))) - - .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Add1~0_combout ), - .datac(\ula_|video_|vga_vc [0]), - .datad(\ula_|video_|Equal3~1_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[0]~0 .lut_mask = 16'h00E4; -defparam \ula_|video_|vga_vc[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y33_N29 -dffeas \ula_|video_|vga_vc[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[0]~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[0] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N22 -cycloneive_lcell_comb \ula_|video_|vga_vc[1]~1 ( -// Equation(s): -// \ula_|video_|vga_vc[1]~1_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [1]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~2_combout )))) - - .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Add1~2_combout ), - .datac(\ula_|video_|vga_vc [1]), - .datad(\ula_|video_|Equal3~1_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[1]~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[1]~1 .lut_mask = 16'h00E4; -defparam \ula_|video_|vga_vc[1]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y33_N23 -dffeas \ula_|video_|vga_vc[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[1]~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[1] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[1] .power_up = "low"; -// synopsys translate_on - -// Location: IOIBUF_X27_Y0_N15 -cycloneive_io_ibuf \SW[1]~input ( - .i(SW[1]), - .ibar(gnd), - .o(\SW[1]~input_o )); -// synopsys translate_off -defparam \SW[1]~input .bus_hold = "false"; -defparam \SW[1]~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N30 -cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_13~0 ( -// Equation(s): -// \z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout = (!\ula_|video_|vga_hc [8] & (!\ula_|video_|vga_vc [1] & (!\SW[1]~input_o & !\ula_|video_|vga_hc [9]))) - - .dataa(\ula_|video_|vga_hc [8]), - .datab(\ula_|video_|vga_vc [1]), - .datac(\SW[1]~input_o ), - .datad(\ula_|video_|vga_hc [9]), - .cin(gnd), - .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13~0 .lut_mask = 16'h0001; -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N30 +// Location: LCCOMB_X29_Y17_N26 cycloneive_lcell_comb \z80_|pla_decode_|Equal79~0 ( // Equation(s): -// \z80_|pla_decode_|Equal79~0_combout = (\z80_|pla_decode_|Equal1~7_combout & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4]))) +// \z80_|pla_decode_|Equal79~0_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal1~7_combout & \z80_|ir_|opcode [4]))) - .dataa(\z80_|pla_decode_|Equal1~7_combout ), + .dataa(\z80_|ir_|opcode [5]), .datab(\z80_|pla_decode_|Equal2~0_combout ), - .datac(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal1~7_combout ), .datad(\z80_|ir_|opcode [4]), .cin(gnd), .combout(\z80_|pla_decode_|Equal79~0_combout ), @@ -18903,38 +4790,56 @@ defparam \z80_|pla_decode_|Equal79~0 .lut_mask = 16'h8000; defparam \z80_|pla_decode_|Equal79~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y17_N16 +// Location: LCCOMB_X29_Y17_N12 +cycloneive_lcell_comb \z80_|interrupts_|iff1~0 ( +// Equation(s): +// \z80_|interrupts_|iff1~0_combout = (\z80_|pla_decode_|Equal79~0_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|ir_|opcode [3]))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|interrupts_|iff1~q )))) # +// (!\z80_|pla_decode_|Equal79~0_combout & (((\z80_|interrupts_|iff1~q )))) + + .dataa(\z80_|pla_decode_|Equal79~0_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|interrupts_|iff1~q ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|interrupts_|iff1~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|iff1~0 .lut_mask = 16'hF870; +defparam \z80_|interrupts_|iff1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N30 cycloneive_lcell_comb \z80_|interrupts_|DFFE_instIFF2~0 ( // Equation(s): -// \z80_|interrupts_|DFFE_instIFF2~0_combout = (\z80_|pla_decode_|Equal79~0_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|ir_|opcode [3])) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|interrupts_|DFFE_instIFF2~q -// ))))) # (!\z80_|pla_decode_|Equal79~0_combout & (((\z80_|interrupts_|DFFE_instIFF2~q )))) +// \z80_|interrupts_|DFFE_instIFF2~0_combout = (\z80_|pla_decode_|Equal79~0_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|ir_|opcode [3]))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|interrupts_|DFFE_instIFF2~q +// )))) # (!\z80_|pla_decode_|Equal79~0_combout & (((\z80_|interrupts_|DFFE_instIFF2~q )))) - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal79~0_combout ), + .dataa(\z80_|pla_decode_|Equal79~0_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), .datac(\z80_|interrupts_|DFFE_instIFF2~q ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|ir_|opcode [3]), .cin(gnd), .combout(\z80_|interrupts_|DFFE_instIFF2~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|interrupts_|DFFE_instIFF2~0 .lut_mask = 16'hB8F0; +defparam \z80_|interrupts_|DFFE_instIFF2~0 .lut_mask = 16'hF870; defparam \z80_|interrupts_|DFFE_instIFF2~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y15_N28 +// Location: LCCOMB_X27_Y11_N24 cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_12 ( // Equation(s): -// \z80_|interrupts_|SYNTHESIZED_WIRE_12~combout = ((!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & \z80_|interrupts_|DFFE_inst44~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) +// \z80_|interrupts_|SYNTHESIZED_WIRE_12~combout = ((\z80_|interrupts_|DFFE_inst44~q & !\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|interrupts_|DFFE_inst44~q ), .datac(gnd), - .datad(\z80_|interrupts_|DFFE_inst44~q ), + .datad(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), .cin(gnd), .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_12~combout ), .cout()); // synopsys translate_off -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12 .lut_mask = 16'h7733; +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12 .lut_mask = 16'h55DD; defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12 .sum_lutc_input = "datac"; // synopsys translate_on @@ -18951,7 +4856,7 @@ defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl .clock_type = "global clo defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: FF_X35_Y17_N17 +// Location: FF_X29_Y17_N31 dffeas \z80_|interrupts_|DFFE_instIFF2 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|interrupts_|DFFE_instIFF2~0_combout ), @@ -18970,60 +4875,76 @@ defparam \z80_|interrupts_|DFFE_instIFF2 .is_wysiwyg = "true"; defparam \z80_|interrupts_|DFFE_instIFF2 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X35_Y17_N2 -cycloneive_lcell_comb \z80_|interrupts_|iff1~0 ( +// Location: LCCOMB_X29_Y13_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal13~0 ( // Equation(s): -// \z80_|interrupts_|iff1~0_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|pla_decode_|Equal79~0_combout & ((\z80_|ir_|opcode [3]))) # (!\z80_|pla_decode_|Equal79~0_combout & (\z80_|interrupts_|iff1~q )))) # -// (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|interrupts_|iff1~q )) +// \z80_|pla_decode_|Equal13~0_combout = (\z80_|decode_state_|DFFE_instED~q & (!\z80_|ir_|opcode [7] & \z80_|ir_|opcode [6])) - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|interrupts_|iff1~q ), - .datac(\z80_|pla_decode_|Equal79~0_combout ), - .datad(\z80_|ir_|opcode [3]), + .dataa(\z80_|decode_state_|DFFE_instED~q ), + .datab(gnd), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|ir_|opcode [6]), .cin(gnd), - .combout(\z80_|interrupts_|iff1~0_combout ), + .combout(\z80_|pla_decode_|Equal13~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|interrupts_|iff1~0 .lut_mask = 16'hEC4C; -defparam \z80_|interrupts_|iff1~0 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal13~0 .lut_mask = 16'h0A00; +defparam \z80_|pla_decode_|Equal13~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y17_N18 +// Location: LCCOMB_X21_Y16_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal38~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal38~2_combout = (\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [1] & \z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal38~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal38~2 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal38~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N0 cycloneive_lcell_comb \z80_|interrupts_|iff1~1 ( // Equation(s): -// \z80_|interrupts_|iff1~1_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|pla_decode_|Equal38~2_combout & (\z80_|interrupts_|DFFE_instIFF2~q )) # (!\z80_|pla_decode_|Equal38~2_combout & ((\z80_|interrupts_|iff1~0_combout ))))) # -// (!\z80_|execute_|ctl_eval_cond~0_combout & (((\z80_|interrupts_|iff1~0_combout )))) +// \z80_|interrupts_|iff1~1_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|pla_decode_|Equal38~2_combout & ((\z80_|interrupts_|DFFE_instIFF2~q ))) # (!\z80_|pla_decode_|Equal38~2_combout & (\z80_|interrupts_|iff1~0_combout )))) # +// (!\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|interrupts_|iff1~0_combout )) - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|interrupts_|DFFE_instIFF2~q ), - .datac(\z80_|pla_decode_|Equal38~2_combout ), - .datad(\z80_|interrupts_|iff1~0_combout ), + .dataa(\z80_|interrupts_|iff1~0_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|interrupts_|DFFE_instIFF2~q ), + .datad(\z80_|pla_decode_|Equal38~2_combout ), .cin(gnd), .combout(\z80_|interrupts_|iff1~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|interrupts_|iff1~1 .lut_mask = 16'hDF80; +defparam \z80_|interrupts_|iff1~1 .lut_mask = 16'hE2AA; defparam \z80_|interrupts_|iff1~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y18_N12 +// Location: LCCOMB_X28_Y13_N20 cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_15 ( // Equation(s): -// \z80_|interrupts_|SYNTHESIZED_WIRE_15~combout = ((\z80_|interrupts_|DFFE_inst44~q ) # (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) +// \z80_|interrupts_|SYNTHESIZED_WIRE_15~combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # ((\z80_|interrupts_|DFFE_inst44~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(gnd), .datac(\z80_|interrupts_|DFFE_inst44~q ), - .datad(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .cin(gnd), .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_15~combout ), .cout()); // synopsys translate_off -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_15 .lut_mask = 16'hFFF3; +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_15 .lut_mask = 16'hFAFF; defparam \z80_|interrupts_|SYNTHESIZED_WIRE_15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X35_Y17_N19 +// Location: FF_X29_Y17_N1 dffeas \z80_|interrupts_|iff1 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|interrupts_|iff1~1_combout ), @@ -19042,14 +4963,1122 @@ defparam \z80_|interrupts_|iff1 .is_wysiwyg = "true"; defparam \z80_|interrupts_|iff1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X37_Y33_N4 -cycloneive_lcell_comb \ula_|video_|Equal2~1 ( +// Location: CLKCTRL_G18 +cycloneive_clkctrl \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk [0]}), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk )); +// synopsys translate_off +defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .clock_type = "global clock"; +defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y32_N6 +cycloneive_lcell_comb \ula_|video_|Add0~0 ( // Equation(s): -// \ula_|video_|Equal2~1_combout = (!\ula_|video_|vga_vc [3] & (!\ula_|video_|vga_vc [2] & (!\ula_|video_|vga_vc [9] & !\ula_|video_|vga_vc [0]))) +// \ula_|video_|Add0~0_combout = \ula_|video_|vga_hc [0] $ (VCC) +// \ula_|video_|Add0~1 = CARRY(\ula_|video_|vga_hc [0]) + + .dataa(gnd), + .datab(\ula_|video_|vga_hc [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\ula_|video_|Add0~0_combout ), + .cout(\ula_|video_|Add0~1 )); +// synopsys translate_off +defparam \ula_|video_|Add0~0 .lut_mask = 16'h33CC; +defparam \ula_|video_|Add0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y32_N28 +cycloneive_lcell_comb \ula_|video_|vga_hc~3 ( +// Equation(s): +// \ula_|video_|vga_hc~3_combout = (\ula_|video_|Add0~0_combout & \ula_|video_|Equal1~0_combout ) + + .dataa(gnd), + .datab(\ula_|video_|Add0~0_combout ), + .datac(gnd), + .datad(\ula_|video_|Equal1~0_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_hc~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_hc~3 .lut_mask = 16'hCC00; +defparam \ula_|video_|vga_hc~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y32_N13 +dffeas \ula_|video_|vga_hc[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|vga_hc~3_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_hc [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_hc[0] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_hc[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y32_N8 +cycloneive_lcell_comb \ula_|video_|Add0~2 ( +// Equation(s): +// \ula_|video_|Add0~2_combout = (\ula_|video_|vga_hc [1] & (!\ula_|video_|Add0~1 )) # (!\ula_|video_|vga_hc [1] & ((\ula_|video_|Add0~1 ) # (GND))) +// \ula_|video_|Add0~3 = CARRY((!\ula_|video_|Add0~1 ) # (!\ula_|video_|vga_hc [1])) + + .dataa(gnd), + .datab(\ula_|video_|vga_hc [1]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add0~1 ), + .combout(\ula_|video_|Add0~2_combout ), + .cout(\ula_|video_|Add0~3 )); +// synopsys translate_off +defparam \ula_|video_|Add0~2 .lut_mask = 16'h3C3F; +defparam \ula_|video_|Add0~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X35_Y32_N25 +dffeas \ula_|video_|vga_hc[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|Add0~2_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_hc [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_hc[1] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_hc[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y32_N10 +cycloneive_lcell_comb \ula_|video_|Add0~4 ( +// Equation(s): +// \ula_|video_|Add0~4_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|Add0~3 $ (GND))) # (!\ula_|video_|vga_hc [2] & (!\ula_|video_|Add0~3 & VCC)) +// \ula_|video_|Add0~5 = CARRY((\ula_|video_|vga_hc [2] & !\ula_|video_|Add0~3 )) + + .dataa(gnd), + .datab(\ula_|video_|vga_hc [2]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add0~3 ), + .combout(\ula_|video_|Add0~4_combout ), + .cout(\ula_|video_|Add0~5 )); +// synopsys translate_off +defparam \ula_|video_|Add0~4 .lut_mask = 16'hC30C; +defparam \ula_|video_|Add0~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X35_Y32_N3 +dffeas \ula_|video_|vga_hc[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|Add0~4_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_hc [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_hc[2] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_hc[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y32_N12 +cycloneive_lcell_comb \ula_|video_|Add0~6 ( +// Equation(s): +// \ula_|video_|Add0~6_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|Add0~5 )) # (!\ula_|video_|vga_hc [3] & ((\ula_|video_|Add0~5 ) # (GND))) +// \ula_|video_|Add0~7 = CARRY((!\ula_|video_|Add0~5 ) # (!\ula_|video_|vga_hc [3])) + + .dataa(\ula_|video_|vga_hc [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add0~5 ), + .combout(\ula_|video_|Add0~6_combout ), + .cout(\ula_|video_|Add0~7 )); +// synopsys translate_off +defparam \ula_|video_|Add0~6 .lut_mask = 16'h5A5F; +defparam \ula_|video_|Add0~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X34_Y32_N21 +dffeas \ula_|video_|vga_hc[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|Add0~6_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_hc [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_hc[3] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_hc[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y32_N14 +cycloneive_lcell_comb \ula_|video_|Add0~8 ( +// Equation(s): +// \ula_|video_|Add0~8_combout = (\ula_|video_|vga_hc [4] & (\ula_|video_|Add0~7 $ (GND))) # (!\ula_|video_|vga_hc [4] & (!\ula_|video_|Add0~7 & VCC)) +// \ula_|video_|Add0~9 = CARRY((\ula_|video_|vga_hc [4] & !\ula_|video_|Add0~7 )) + + .dataa(\ula_|video_|vga_hc [4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add0~7 ), + .combout(\ula_|video_|Add0~8_combout ), + .cout(\ula_|video_|Add0~9 )); +// synopsys translate_off +defparam \ula_|video_|Add0~8 .lut_mask = 16'hA50A; +defparam \ula_|video_|Add0~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X34_Y32_N3 +dffeas \ula_|video_|vga_hc[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|Add0~8_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_hc [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_hc[4] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_hc[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y32_N16 +cycloneive_lcell_comb \ula_|video_|Add0~10 ( +// Equation(s): +// \ula_|video_|Add0~10_combout = (\ula_|video_|vga_hc [5] & (!\ula_|video_|Add0~9 )) # (!\ula_|video_|vga_hc [5] & ((\ula_|video_|Add0~9 ) # (GND))) +// \ula_|video_|Add0~11 = CARRY((!\ula_|video_|Add0~9 ) # (!\ula_|video_|vga_hc [5])) + + .dataa(gnd), + .datab(\ula_|video_|vga_hc [5]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add0~9 ), + .combout(\ula_|video_|Add0~10_combout ), + .cout(\ula_|video_|Add0~11 )); +// synopsys translate_off +defparam \ula_|video_|Add0~10 .lut_mask = 16'h3C3F; +defparam \ula_|video_|Add0~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y32_N26 +cycloneive_lcell_comb \ula_|video_|vga_hc~0 ( +// Equation(s): +// \ula_|video_|vga_hc~0_combout = (\ula_|video_|Add0~10_combout & \ula_|video_|Equal1~0_combout ) + + .dataa(gnd), + .datab(\ula_|video_|Add0~10_combout ), + .datac(gnd), + .datad(\ula_|video_|Equal1~0_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_hc~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_hc~0 .lut_mask = 16'hCC00; +defparam \ula_|video_|vga_hc~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y32_N29 +dffeas \ula_|video_|vga_hc[5] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|vga_hc~0_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_hc [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_hc[5] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_hc[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y32_N18 +cycloneive_lcell_comb \ula_|video_|Add0~12 ( +// Equation(s): +// \ula_|video_|Add0~12_combout = (\ula_|video_|vga_hc [6] & (\ula_|video_|Add0~11 $ (GND))) # (!\ula_|video_|vga_hc [6] & (!\ula_|video_|Add0~11 & VCC)) +// \ula_|video_|Add0~13 = CARRY((\ula_|video_|vga_hc [6] & !\ula_|video_|Add0~11 )) + + .dataa(\ula_|video_|vga_hc [6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add0~11 ), + .combout(\ula_|video_|Add0~12_combout ), + .cout(\ula_|video_|Add0~13 )); +// synopsys translate_off +defparam \ula_|video_|Add0~12 .lut_mask = 16'hA50A; +defparam \ula_|video_|Add0~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X34_Y32_N5 +dffeas \ula_|video_|vga_hc[6] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|Add0~12_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_hc [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_hc[6] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_hc[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y32_N20 +cycloneive_lcell_comb \ula_|video_|Add0~14 ( +// Equation(s): +// \ula_|video_|Add0~14_combout = (\ula_|video_|vga_hc [7] & (!\ula_|video_|Add0~13 )) # (!\ula_|video_|vga_hc [7] & ((\ula_|video_|Add0~13 ) # (GND))) +// \ula_|video_|Add0~15 = CARRY((!\ula_|video_|Add0~13 ) # (!\ula_|video_|vga_hc [7])) + + .dataa(gnd), + .datab(\ula_|video_|vga_hc [7]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add0~13 ), + .combout(\ula_|video_|Add0~14_combout ), + .cout(\ula_|video_|Add0~15 )); +// synopsys translate_off +defparam \ula_|video_|Add0~14 .lut_mask = 16'h3C3F; +defparam \ula_|video_|Add0~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X34_Y32_N27 +dffeas \ula_|video_|vga_hc[7] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|Add0~14_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_hc [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_hc[7] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_hc[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y32_N22 +cycloneive_lcell_comb \ula_|video_|Add0~16 ( +// Equation(s): +// \ula_|video_|Add0~16_combout = (\ula_|video_|vga_hc [8] & (\ula_|video_|Add0~15 $ (GND))) # (!\ula_|video_|vga_hc [8] & (!\ula_|video_|Add0~15 & VCC)) +// \ula_|video_|Add0~17 = CARRY((\ula_|video_|vga_hc [8] & !\ula_|video_|Add0~15 )) + + .dataa(gnd), + .datab(\ula_|video_|vga_hc [8]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add0~15 ), + .combout(\ula_|video_|Add0~16_combout ), + .cout(\ula_|video_|Add0~17 )); +// synopsys translate_off +defparam \ula_|video_|Add0~16 .lut_mask = 16'hC30C; +defparam \ula_|video_|Add0~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y32_N2 +cycloneive_lcell_comb \ula_|video_|vga_hc~2 ( +// Equation(s): +// \ula_|video_|vga_hc~2_combout = (\ula_|video_|Add0~16_combout & \ula_|video_|Equal1~0_combout ) + + .dataa(gnd), + .datab(\ula_|video_|Add0~16_combout ), + .datac(gnd), + .datad(\ula_|video_|Equal1~0_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_hc~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_hc~2 .lut_mask = 16'hCC00; +defparam \ula_|video_|vga_hc~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y32_N27 +dffeas \ula_|video_|vga_hc[8] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|vga_hc~2_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_hc [8]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_hc[8] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_hc[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y32_N24 +cycloneive_lcell_comb \ula_|video_|Add0~18 ( +// Equation(s): +// \ula_|video_|Add0~18_combout = \ula_|video_|Add0~17 $ (\ula_|video_|vga_hc [9]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|vga_hc [9]), + .cin(\ula_|video_|Add0~17 ), + .combout(\ula_|video_|Add0~18_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Add0~18 .lut_mask = 16'h0FF0; +defparam \ula_|video_|Add0~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y32_N4 +cycloneive_lcell_comb \ula_|video_|vga_hc~1 ( +// Equation(s): +// \ula_|video_|vga_hc~1_combout = (\ula_|video_|Add0~18_combout & \ula_|video_|Equal1~0_combout ) + + .dataa(\ula_|video_|Add0~18_combout ), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|Equal1~0_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_hc~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_hc~1 .lut_mask = 16'hAA00; +defparam \ula_|video_|vga_hc~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y32_N1 +dffeas \ula_|video_|vga_hc[9] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|vga_hc~1_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_hc [9]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_hc[9] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_hc[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y31_N14 +cycloneive_lcell_comb \ula_|video_|Equal0~0 ( +// Equation(s): +// \ula_|video_|Equal0~0_combout = (!\ula_|video_|vga_hc [1] & (!\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [2] & !\ula_|video_|vga_hc [0]))) + + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|vga_hc [3]), + .datac(\ula_|video_|vga_hc [2]), + .datad(\ula_|video_|vga_hc [0]), + .cin(gnd), + .combout(\ula_|video_|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Equal0~0 .lut_mask = 16'h0001; +defparam \ula_|video_|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y31_N24 +cycloneive_lcell_comb \ula_|video_|Equal0~1 ( +// Equation(s): +// \ula_|video_|Equal0~1_combout = (!\ula_|video_|vga_hc [4] & (!\ula_|video_|vga_hc [7] & (\ula_|video_|Equal0~0_combout & \ula_|video_|vga_hc [5]))) + + .dataa(\ula_|video_|vga_hc [4]), + .datab(\ula_|video_|vga_hc [7]), + .datac(\ula_|video_|Equal0~0_combout ), + .datad(\ula_|video_|vga_hc [5]), + .cin(gnd), + .combout(\ula_|video_|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Equal0~1 .lut_mask = 16'h1000; +defparam \ula_|video_|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y31_N8 +cycloneive_lcell_comb \ula_|video_|Equal1~0 ( +// Equation(s): +// \ula_|video_|Equal1~0_combout = ((\ula_|video_|vga_hc [6]) # ((!\ula_|video_|Equal0~1_combout ) # (!\ula_|video_|vga_hc [8]))) # (!\ula_|video_|vga_hc [9]) + + .dataa(\ula_|video_|vga_hc [9]), + .datab(\ula_|video_|vga_hc [6]), + .datac(\ula_|video_|vga_hc [8]), + .datad(\ula_|video_|Equal0~1_combout ), + .cin(gnd), + .combout(\ula_|video_|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Equal1~0 .lut_mask = 16'hDFFF; +defparam \ula_|video_|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y31_N2 +cycloneive_lcell_comb \ula_|video_|Add1~0 ( +// Equation(s): +// \ula_|video_|Add1~0_combout = \ula_|video_|vga_vc [0] $ (VCC) +// \ula_|video_|Add1~1 = CARRY(\ula_|video_|vga_vc [0]) + + .dataa(\ula_|video_|vga_vc [0]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\ula_|video_|Add1~0_combout ), + .cout(\ula_|video_|Add1~1 )); +// synopsys translate_off +defparam \ula_|video_|Add1~0 .lut_mask = 16'h55AA; +defparam \ula_|video_|Add1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y31_N28 +cycloneive_lcell_comb \ula_|video_|vga_vc[0]~0 ( +// Equation(s): +// \ula_|video_|vga_vc[0]~0_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [0]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~0_combout )))) + + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Equal3~1_combout ), + .datac(\ula_|video_|Add1~0_combout ), + .datad(\ula_|video_|vga_vc [0]), + .cin(gnd), + .combout(\ula_|video_|vga_vc[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[0]~0 .lut_mask = 16'h3210; +defparam \ula_|video_|vga_vc[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y32_N29 +dffeas \ula_|video_|vga_vc[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|vga_vc[0]~0_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[0] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y31_N4 +cycloneive_lcell_comb \ula_|video_|Add1~2 ( +// Equation(s): +// \ula_|video_|Add1~2_combout = (\ula_|video_|vga_vc [1] & (!\ula_|video_|Add1~1 )) # (!\ula_|video_|vga_vc [1] & ((\ula_|video_|Add1~1 ) # (GND))) +// \ula_|video_|Add1~3 = CARRY((!\ula_|video_|Add1~1 ) # (!\ula_|video_|vga_vc [1])) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [1]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add1~1 ), + .combout(\ula_|video_|Add1~2_combout ), + .cout(\ula_|video_|Add1~3 )); +// synopsys translate_off +defparam \ula_|video_|Add1~2 .lut_mask = 16'h3C3F; +defparam \ula_|video_|Add1~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y32_N10 +cycloneive_lcell_comb \ula_|video_|vga_vc[1]~1 ( +// Equation(s): +// \ula_|video_|vga_vc[1]~1_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [1]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~2_combout )))) + + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Add1~2_combout ), + .datac(\ula_|video_|vga_vc [1]), + .datad(\ula_|video_|Equal3~1_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[1]~1 .lut_mask = 16'h00E4; +defparam \ula_|video_|vga_vc[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y32_N11 +dffeas \ula_|video_|vga_vc[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[1]~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[1] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y31_N6 +cycloneive_lcell_comb \ula_|video_|Add1~4 ( +// Equation(s): +// \ula_|video_|Add1~4_combout = (\ula_|video_|vga_vc [2] & (\ula_|video_|Add1~3 $ (GND))) # (!\ula_|video_|vga_vc [2] & (!\ula_|video_|Add1~3 & VCC)) +// \ula_|video_|Add1~5 = CARRY((\ula_|video_|vga_vc [2] & !\ula_|video_|Add1~3 )) + + .dataa(\ula_|video_|vga_vc [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add1~3 ), + .combout(\ula_|video_|Add1~4_combout ), + .cout(\ula_|video_|Add1~5 )); +// synopsys translate_off +defparam \ula_|video_|Add1~4 .lut_mask = 16'hA50A; +defparam \ula_|video_|Add1~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y31_N22 +cycloneive_lcell_comb \ula_|video_|vga_vc[2]~2 ( +// Equation(s): +// \ula_|video_|vga_vc[2]~2_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [2])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~4_combout ))))) + + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Equal3~1_combout ), + .datac(\ula_|video_|vga_vc [2]), + .datad(\ula_|video_|Add1~4_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[2]~2 .lut_mask = 16'h3120; +defparam \ula_|video_|vga_vc[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y32_N24 +cycloneive_lcell_comb \ula_|video_|vga_vc[2]~feeder ( +// Equation(s): +// \ula_|video_|vga_vc[2]~feeder_combout = \ula_|video_|vga_vc[2]~2_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|vga_vc[2]~2_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[2]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|vga_vc[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y32_N25 +dffeas \ula_|video_|vga_vc[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[2] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y31_N8 +cycloneive_lcell_comb \ula_|video_|Add1~6 ( +// Equation(s): +// \ula_|video_|Add1~6_combout = (\ula_|video_|vga_vc [3] & (!\ula_|video_|Add1~5 )) # (!\ula_|video_|vga_vc [3] & ((\ula_|video_|Add1~5 ) # (GND))) +// \ula_|video_|Add1~7 = CARRY((!\ula_|video_|Add1~5 ) # (!\ula_|video_|vga_vc [3])) .dataa(\ula_|video_|vga_vc [3]), - .datab(\ula_|video_|vga_vc [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add1~5 ), + .combout(\ula_|video_|Add1~6_combout ), + .cout(\ula_|video_|Add1~7 )); +// synopsys translate_off +defparam \ula_|video_|Add1~6 .lut_mask = 16'h5A5F; +defparam \ula_|video_|Add1~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y31_N24 +cycloneive_lcell_comb \ula_|video_|vga_vc[3]~3 ( +// Equation(s): +// \ula_|video_|vga_vc[3]~3_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [3])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~6_combout ))))) + + .dataa(\ula_|video_|vga_vc [3]), + .datab(\ula_|video_|Equal3~1_combout ), + .datac(\ula_|video_|Add1~6_combout ), + .datad(\ula_|video_|Equal1~0_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[3]~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[3]~3 .lut_mask = 16'h2230; +defparam \ula_|video_|vga_vc[3]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y32_N31 +dffeas \ula_|video_|vga_vc[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|vga_vc[3]~3_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[3] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y31_N10 +cycloneive_lcell_comb \ula_|video_|Add1~8 ( +// Equation(s): +// \ula_|video_|Add1~8_combout = (\ula_|video_|vga_vc [4] & (\ula_|video_|Add1~7 $ (GND))) # (!\ula_|video_|vga_vc [4] & (!\ula_|video_|Add1~7 & VCC)) +// \ula_|video_|Add1~9 = CARRY((\ula_|video_|vga_vc [4] & !\ula_|video_|Add1~7 )) + + .dataa(\ula_|video_|vga_vc [4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add1~7 ), + .combout(\ula_|video_|Add1~8_combout ), + .cout(\ula_|video_|Add1~9 )); +// synopsys translate_off +defparam \ula_|video_|Add1~8 .lut_mask = 16'hA50A; +defparam \ula_|video_|Add1~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y32_N6 +cycloneive_lcell_comb \ula_|video_|vga_vc[4]~5 ( +// Equation(s): +// \ula_|video_|vga_vc[4]~5_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [4]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~8_combout )))) + + .dataa(\ula_|video_|Equal3~1_combout ), + .datab(\ula_|video_|Add1~8_combout ), + .datac(\ula_|video_|vga_vc [4]), + .datad(\ula_|video_|Equal1~0_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[4]~5_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[4]~5 .lut_mask = 16'h5044; +defparam \ula_|video_|vga_vc[4]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y32_N7 +dffeas \ula_|video_|vga_vc[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[4]~5_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[4] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y31_N12 +cycloneive_lcell_comb \ula_|video_|Add1~10 ( +// Equation(s): +// \ula_|video_|Add1~10_combout = (\ula_|video_|vga_vc [5] & (!\ula_|video_|Add1~9 )) # (!\ula_|video_|vga_vc [5] & ((\ula_|video_|Add1~9 ) # (GND))) +// \ula_|video_|Add1~11 = CARRY((!\ula_|video_|Add1~9 ) # (!\ula_|video_|vga_vc [5])) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [5]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add1~9 ), + .combout(\ula_|video_|Add1~10_combout ), + .cout(\ula_|video_|Add1~11 )); +// synopsys translate_off +defparam \ula_|video_|Add1~10 .lut_mask = 16'h3C3F; +defparam \ula_|video_|Add1~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y31_N14 +cycloneive_lcell_comb \ula_|video_|Add1~12 ( +// Equation(s): +// \ula_|video_|Add1~12_combout = (\ula_|video_|vga_vc [6] & (\ula_|video_|Add1~11 $ (GND))) # (!\ula_|video_|vga_vc [6] & (!\ula_|video_|Add1~11 & VCC)) +// \ula_|video_|Add1~13 = CARRY((\ula_|video_|vga_vc [6] & !\ula_|video_|Add1~11 )) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [6]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add1~11 ), + .combout(\ula_|video_|Add1~12_combout ), + .cout(\ula_|video_|Add1~13 )); +// synopsys translate_off +defparam \ula_|video_|Add1~12 .lut_mask = 16'hC30C; +defparam \ula_|video_|Add1~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y32_N0 +cycloneive_lcell_comb \ula_|video_|vga_vc[6]~4 ( +// Equation(s): +// \ula_|video_|vga_vc[6]~4_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [6]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~12_combout )))) + + .dataa(\ula_|video_|Equal3~1_combout ), + .datab(\ula_|video_|Add1~12_combout ), + .datac(\ula_|video_|vga_vc [6]), + .datad(\ula_|video_|Equal1~0_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[6]~4_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[6]~4 .lut_mask = 16'h5044; +defparam \ula_|video_|vga_vc[6]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y32_N1 +dffeas \ula_|video_|vga_vc[6] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[6]~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[6] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y31_N16 +cycloneive_lcell_comb \ula_|video_|Add1~14 ( +// Equation(s): +// \ula_|video_|Add1~14_combout = (\ula_|video_|vga_vc [7] & (!\ula_|video_|Add1~13 )) # (!\ula_|video_|vga_vc [7] & ((\ula_|video_|Add1~13 ) # (GND))) +// \ula_|video_|Add1~15 = CARRY((!\ula_|video_|Add1~13 ) # (!\ula_|video_|vga_vc [7])) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [7]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add1~13 ), + .combout(\ula_|video_|Add1~14_combout ), + .cout(\ula_|video_|Add1~15 )); +// synopsys translate_off +defparam \ula_|video_|Add1~14 .lut_mask = 16'h3C3F; +defparam \ula_|video_|Add1~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y32_N8 +cycloneive_lcell_comb \ula_|video_|vga_vc[7]~6 ( +// Equation(s): +// \ula_|video_|vga_vc[7]~6_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [7]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~14_combout )))) + + .dataa(\ula_|video_|Equal3~1_combout ), + .datab(\ula_|video_|Add1~14_combout ), + .datac(\ula_|video_|vga_vc [7]), + .datad(\ula_|video_|Equal1~0_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[7]~6_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[7]~6 .lut_mask = 16'h5044; +defparam \ula_|video_|vga_vc[7]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y32_N9 +dffeas \ula_|video_|vga_vc[7] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[7]~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[7] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y31_N18 +cycloneive_lcell_comb \ula_|video_|Add1~16 ( +// Equation(s): +// \ula_|video_|Add1~16_combout = (\ula_|video_|vga_vc [8] & (\ula_|video_|Add1~15 $ (GND))) # (!\ula_|video_|vga_vc [8] & (!\ula_|video_|Add1~15 & VCC)) +// \ula_|video_|Add1~17 = CARRY((\ula_|video_|vga_vc [8] & !\ula_|video_|Add1~15 )) + + .dataa(\ula_|video_|vga_vc [8]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add1~15 ), + .combout(\ula_|video_|Add1~16_combout ), + .cout(\ula_|video_|Add1~17 )); +// synopsys translate_off +defparam \ula_|video_|Add1~16 .lut_mask = 16'hA50A; +defparam \ula_|video_|Add1~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y32_N0 +cycloneive_lcell_comb \ula_|video_|vga_vc[8]~7 ( +// Equation(s): +// \ula_|video_|vga_vc[8]~7_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [8]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~16_combout )))) + + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Add1~16_combout ), + .datac(\ula_|video_|vga_vc [8]), + .datad(\ula_|video_|Equal3~1_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[8]~7_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[8]~7 .lut_mask = 16'h00E4; +defparam \ula_|video_|vga_vc[8]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y32_N1 +dffeas \ula_|video_|vga_vc[8] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[8]~7_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [8]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[8] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y31_N20 +cycloneive_lcell_comb \ula_|video_|Add1~18 ( +// Equation(s): +// \ula_|video_|Add1~18_combout = \ula_|video_|Add1~17 $ (\ula_|video_|vga_vc [9]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|vga_vc [9]), + .cin(\ula_|video_|Add1~17 ), + .combout(\ula_|video_|Add1~18_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Add1~18 .lut_mask = 16'h0FF0; +defparam \ula_|video_|Add1~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y32_N28 +cycloneive_lcell_comb \ula_|video_|vga_vc[9]~9 ( +// Equation(s): +// \ula_|video_|vga_vc[9]~9_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [9]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~18_combout )))) + + .dataa(\ula_|video_|Add1~18_combout ), + .datab(\ula_|video_|Equal1~0_combout ), .datac(\ula_|video_|vga_vc [9]), + .datad(\ula_|video_|Equal3~1_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[9]~9_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[9]~9 .lut_mask = 16'h00E2; +defparam \ula_|video_|vga_vc[9]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y32_N29 +dffeas \ula_|video_|vga_vc[9] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[9]~9_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [9]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[9] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y30_N0 +cycloneive_lcell_comb \ula_|video_|Equal3~0 ( +// Equation(s): +// \ula_|video_|Equal3~0_combout = (\ula_|video_|vga_vc [0] & (\ula_|video_|vga_vc [3] & (\ula_|video_|vga_vc [2] & !\ula_|video_|vga_vc [1]))) + + .dataa(\ula_|video_|vga_vc [0]), + .datab(\ula_|video_|vga_vc [3]), + .datac(\ula_|video_|vga_vc [2]), + .datad(\ula_|video_|vga_vc [1]), + .cin(gnd), + .combout(\ula_|video_|Equal3~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Equal3~0 .lut_mask = 16'h0080; +defparam \ula_|video_|Equal3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y32_N2 +cycloneive_lcell_comb \ula_|video_|Equal2~0 ( +// Equation(s): +// \ula_|video_|Equal2~0_combout = (!\ula_|video_|vga_vc [6] & (!\ula_|video_|vga_vc [8] & (!\ula_|video_|vga_vc [4] & !\ula_|video_|vga_vc [7]))) + + .dataa(\ula_|video_|vga_vc [6]), + .datab(\ula_|video_|vga_vc [8]), + .datac(\ula_|video_|vga_vc [4]), + .datad(\ula_|video_|vga_vc [7]), + .cin(gnd), + .combout(\ula_|video_|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Equal2~0 .lut_mask = 16'h0001; +defparam \ula_|video_|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y32_N10 +cycloneive_lcell_comb \ula_|video_|Equal3~1 ( +// Equation(s): +// \ula_|video_|Equal3~1_combout = (!\ula_|video_|vga_vc [5] & (\ula_|video_|vga_vc [9] & (\ula_|video_|Equal3~0_combout & \ula_|video_|Equal2~0_combout ))) + + .dataa(\ula_|video_|vga_vc [5]), + .datab(\ula_|video_|vga_vc [9]), + .datac(\ula_|video_|Equal3~0_combout ), + .datad(\ula_|video_|Equal2~0_combout ), + .cin(gnd), + .combout(\ula_|video_|Equal3~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Equal3~1 .lut_mask = 16'h4000; +defparam \ula_|video_|Equal3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y32_N30 +cycloneive_lcell_comb \ula_|video_|vga_vc[5]~8 ( +// Equation(s): +// \ula_|video_|vga_vc[5]~8_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [5]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~10_combout )))) + + .dataa(\ula_|video_|Equal3~1_combout ), + .datab(\ula_|video_|Add1~10_combout ), + .datac(\ula_|video_|vga_vc [5]), + .datad(\ula_|video_|Equal1~0_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[5]~8_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[5]~8 .lut_mask = 16'h5044; +defparam \ula_|video_|vga_vc[5]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y32_N31 +dffeas \ula_|video_|vga_vc[5] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[5]~8_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[5] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y31_N26 +cycloneive_lcell_comb \ula_|video_|Equal2~1 ( +// Equation(s): +// \ula_|video_|Equal2~1_combout = (!\ula_|video_|vga_vc [2] & (!\ula_|video_|vga_vc [9] & (!\ula_|video_|vga_vc [3] & !\ula_|video_|vga_vc [0]))) + + .dataa(\ula_|video_|vga_vc [2]), + .datab(\ula_|video_|vga_vc [9]), + .datac(\ula_|video_|vga_vc [3]), .datad(\ula_|video_|vga_vc [0]), .cin(gnd), .combout(\ula_|video_|Equal2~1_combout ), @@ -19059,41 +6088,68 @@ defparam \ula_|video_|Equal2~1 .lut_mask = 16'h0001; defparam \ula_|video_|Equal2~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y33_N14 +// Location: LCCOMB_X35_Y32_N24 cycloneive_lcell_comb \ula_|video_|Equal2~2 ( // Equation(s): -// \ula_|video_|Equal2~2_combout = (\ula_|video_|Equal2~1_combout & (\ula_|video_|Equal2~0_combout & !\ula_|video_|vga_vc [5])) +// \ula_|video_|Equal2~2_combout = (!\ula_|video_|vga_vc [5] & (\ula_|video_|Equal2~1_combout & \ula_|video_|Equal2~0_combout )) - .dataa(gnd), + .dataa(\ula_|video_|vga_vc [5]), .datab(\ula_|video_|Equal2~1_combout ), - .datac(\ula_|video_|Equal2~0_combout ), - .datad(\ula_|video_|vga_vc [5]), + .datac(gnd), + .datad(\ula_|video_|Equal2~0_combout ), .cin(gnd), .combout(\ula_|video_|Equal2~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Equal2~2 .lut_mask = 16'h00C0; +defparam \ula_|video_|Equal2~2 .lut_mask = 16'h4400; defparam \ula_|video_|Equal2~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y31_N28 +// Location: IOIBUF_X27_Y0_N15 +cycloneive_io_ibuf \SW[1]~input ( + .i(SW[1]), + .ibar(gnd), + .o(\SW[1]~input_o )); +// synopsys translate_off +defparam \SW[1]~input .bus_hold = "false"; +defparam \SW[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y33_N2 +cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_13~0 ( +// Equation(s): +// \z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout = (!\ula_|video_|vga_vc [1] & (!\ula_|video_|vga_hc [8] & (!\ula_|video_|vga_hc [9] & !\SW[1]~input_o ))) + + .dataa(\ula_|video_|vga_vc [1]), + .datab(\ula_|video_|vga_hc [8]), + .datac(\ula_|video_|vga_hc [9]), + .datad(\SW[1]~input_o ), + .cin(gnd), + .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13~0 .lut_mask = 16'h0001; +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y33_N20 cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_13 ( // Equation(s): -// \z80_|interrupts_|SYNTHESIZED_WIRE_13~combout = (!\ula_|video_|vga_hc [7] & (\z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout & (\z80_|interrupts_|iff1~q & \ula_|video_|Equal2~2_combout ))) +// \z80_|interrupts_|SYNTHESIZED_WIRE_13~combout = (\z80_|interrupts_|iff1~q & (\ula_|video_|Equal2~2_combout & (!\ula_|video_|vga_hc [7] & \z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout ))) - .dataa(\ula_|video_|vga_hc [7]), - .datab(\z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout ), - .datac(\z80_|interrupts_|iff1~q ), - .datad(\ula_|video_|Equal2~2_combout ), + .dataa(\z80_|interrupts_|iff1~q ), + .datab(\ula_|video_|Equal2~2_combout ), + .datac(\ula_|video_|vga_hc [7]), + .datad(\z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout ), .cin(gnd), .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_13~combout ), .cout()); // synopsys translate_off -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13 .lut_mask = 16'h4000; +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13 .lut_mask = 16'h0800; defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X35_Y31_N29 +// Location: FF_X35_Y33_N21 dffeas \z80_|interrupts_|int_armed ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|interrupts_|SYNTHESIZED_WIRE_13~combout ), @@ -19112,15 +6168,32 @@ defparam \z80_|interrupts_|int_armed .is_wysiwyg = "true"; defparam \z80_|interrupts_|int_armed .power_up = "low"; // synopsys translate_on -// Location: FF_X32_Y15_N11 +// Location: LCCOMB_X28_Y13_N30 +cycloneive_lcell_comb \z80_|interrupts_|DFFE_inst44~feeder ( +// Equation(s): +// \z80_|interrupts_|DFFE_inst44~feeder_combout = \z80_|interrupts_|int_armed~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|interrupts_|int_armed~q ), + .cin(gnd), + .combout(\z80_|interrupts_|DFFE_inst44~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|DFFE_inst44~feeder .lut_mask = 16'hFF00; +defparam \z80_|interrupts_|DFFE_inst44~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y13_N31 dffeas \z80_|interrupts_|DFFE_inst44 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|interrupts_|int_armed~q ), + .d(\z80_|interrupts_|DFFE_inst44~feeder_combout ), + .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), - .sload(vcc), + .sload(gnd), .ena(\z80_|interrupts_|test1~3_combout ), .devclrn(devclrn), .devpor(devpor), @@ -19131,14509 +6204,44 @@ defparam \z80_|interrupts_|DFFE_inst44 .is_wysiwyg = "true"; defparam \z80_|interrupts_|DFFE_inst44 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~38 ( +// Location: LCCOMB_X28_Y13_N4 +cycloneive_lcell_comb \z80_|decode_state_|in_halt~0 ( // Equation(s): -// \z80_|execute_|pc_inc_hold~38_combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # ((\z80_|decode_state_|in_halt~q ) # (\z80_|interrupts_|DFFE_inst44~q )) +// \z80_|decode_state_|in_halt~0_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (!\z80_|interrupts_|DFFE_inst44~q & \z80_|decode_state_|in_halt~q )) .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), .datab(gnd), - .datac(\z80_|decode_state_|in_halt~q ), - .datad(\z80_|interrupts_|DFFE_inst44~q ), + .datac(\z80_|interrupts_|DFFE_inst44~q ), + .datad(\z80_|decode_state_|in_halt~q ), .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~38_combout ), + .combout(\z80_|decode_state_|in_halt~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~38 .lut_mask = 16'hFFFA; -defparam \z80_|execute_|pc_inc_hold~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~91 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~91_combout = (((!\z80_|sequencer_|DFFE_M3_ff~q & !\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|pla_decode_|Equal34~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~91_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~91 .lut_mask = 16'h57FF; -defparam \z80_|execute_|ctl_inc_cy~91 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~45 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~45_combout = (\z80_|pla_decode_|Equal19~0_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ctl_mRead~36_combout & \z80_|execute_|pc_inc_hold~29_combout )))) # (!\z80_|pla_decode_|Equal19~0_combout & -// (((\z80_|execute_|ctl_mRead~36_combout & \z80_|execute_|pc_inc_hold~29_combout )))) - - .dataa(\z80_|pla_decode_|Equal19~0_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_mRead~36_combout ), - .datad(\z80_|execute_|pc_inc_hold~29_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~45 .lut_mask = 16'hF888; -defparam \z80_|execute_|pc_inc_hold~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~44 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~44_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & ((\z80_|pla_decode_|Equal19~0_combout ) # ((!\z80_|execute_|pc_inc_hold~49_combout ) # (!\z80_|execute_|ctl_bus_db_oe~1_combout )))) - - .dataa(\z80_|pla_decode_|Equal19~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .datad(\z80_|execute_|pc_inc_hold~49_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~44 .lut_mask = 16'h8CCC; -defparam \z80_|execute_|pc_inc_hold~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N2 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~46 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~46_combout = (\z80_|execute_|pc_inc_hold~45_combout ) # ((\z80_|execute_|pc_inc_hold~44_combout ) # ((\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|pc_inc_hold~49_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~45_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|pc_inc_hold~44_combout ), - .datad(\z80_|execute_|pc_inc_hold~49_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~46 .lut_mask = 16'hFAFE; -defparam \z80_|execute_|pc_inc_hold~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N18 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~37 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~37_combout = (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|execute_|pc_inc_hold~29_combout ) # ((\z80_|pla_decode_|Equal52~1_combout & \z80_|execute_|ctl_alu_op_low~8_combout )))) # (!\z80_|pla_decode_|Equal10~0_combout & -// (\z80_|pla_decode_|Equal52~1_combout & (\z80_|execute_|ctl_alu_op_low~8_combout ))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|pla_decode_|Equal52~1_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datad(\z80_|execute_|pc_inc_hold~29_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~37 .lut_mask = 16'hEAC0; -defparam \z80_|execute_|pc_inc_hold~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N12 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~50 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~50_combout = (\z80_|execute_|pc_inc_hold~37_combout ) # ((\z80_|execute_|ixy_d~16_combout & (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ))) - - .dataa(\z80_|execute_|ixy_d~16_combout ), - .datab(\z80_|execute_|pc_inc_hold~37_combout ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~50 .lut_mask = 16'hECCC; -defparam \z80_|execute_|pc_inc_hold~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N22 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~33 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~33_combout = (\z80_|execute_|ctl_mRead~10_combout & (((\z80_|execute_|ctl_alu_op_low~8_combout ) # (\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|execute_|ctl_mRead~10_combout & (\z80_|pla_decode_|Equal6~1_combout & -// ((\z80_|execute_|ctl_alu_op_low~8_combout ) # (\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|pla_decode_|Equal6~1_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~33 .lut_mask = 16'hEEE0; -defparam \z80_|execute_|pc_inc_hold~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|execute_|ixy_d~5_combout & (\z80_|pla_decode_|Equal55~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal33~2_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|decode_state_|use_ixiy~combout ), - .datad(\z80_|pla_decode_|Equal33~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N26 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~31 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~31_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ) # ((\z80_|execute_|ctl_alu_op_low~8_combout & ((\z80_|execute_|ctl_mRead~14_combout ) # (!\z80_|execute_|pc_inc_hold~28_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ), - .datac(\z80_|execute_|ctl_mRead~14_combout ), - .datad(\z80_|execute_|pc_inc_hold~28_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~31 .lut_mask = 16'hECEE; -defparam \z80_|execute_|pc_inc_hold~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N12 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~32 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~32_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & (((\z80_|execute_|ctl_mRead~9_combout ) # (\z80_|execute_|ctl_mRead~15_combout )))) # (!\z80_|execute_|ctl_alu_op_low~8_combout & (\z80_|execute_|ixy_d~5_combout & -// ((\z80_|execute_|ctl_mRead~15_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_mRead~9_combout ), - .datad(\z80_|execute_|ctl_mRead~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~32 .lut_mask = 16'hEEA0; -defparam \z80_|execute_|pc_inc_hold~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N16 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~34 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~34_combout = (\z80_|execute_|pc_inc_hold~33_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ) # ((\z80_|execute_|pc_inc_hold~31_combout ) # (\z80_|execute_|pc_inc_hold~32_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~33_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ), - .datac(\z80_|execute_|pc_inc_hold~31_combout ), - .datad(\z80_|execute_|pc_inc_hold~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~34 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|pc_inc_hold~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N28 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~51 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~51_combout = (((!\z80_|sequencer_|DFFE_M3_ff~q & !\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|execute_|ctl_mRead~17_combout ) - - .dataa(\z80_|execute_|ctl_mRead~17_combout ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~51_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~51 .lut_mask = 16'h57FF; -defparam \z80_|execute_|pc_inc_hold~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N22 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~30 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~30_combout = (\z80_|pla_decode_|Equal12~1_combout ) # (((!\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ctl_alu_op_low~8_combout )) # (!\z80_|pla_decode_|Equal25~0_combout )) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|pla_decode_|Equal12~1_combout ), - .datac(\z80_|pla_decode_|Equal25~0_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~30 .lut_mask = 16'hCFDF; -defparam \z80_|execute_|pc_inc_hold~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N6 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~52 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~52_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|execute_|ctl_mRead~8_combout & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (\z80_|sequencer_|DFFE_M2_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|execute_|ctl_mRead~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~52_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~52 .lut_mask = 16'hA800; -defparam \z80_|execute_|pc_inc_hold~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N8 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~35 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~35_combout = (!\z80_|execute_|pc_inc_hold~34_combout & (\z80_|execute_|pc_inc_hold~51_combout & (\z80_|execute_|pc_inc_hold~30_combout & !\z80_|execute_|pc_inc_hold~52_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~34_combout ), - .datab(\z80_|execute_|pc_inc_hold~51_combout ), - .datac(\z80_|execute_|pc_inc_hold~30_combout ), - .datad(\z80_|execute_|pc_inc_hold~52_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~35 .lut_mask = 16'h0040; -defparam \z80_|execute_|pc_inc_hold~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N4 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~36 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~36_combout = ((\z80_|pla_decode_|Equal11~0_combout & ((\z80_|execute_|ctl_mWrite~7_combout ) # (\z80_|execute_|ctl_alu_shift_oe~14_combout )))) # (!\z80_|execute_|pc_inc_hold~35_combout ) - - .dataa(\z80_|execute_|ctl_mWrite~7_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|pc_inc_hold~35_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~36 .lut_mask = 16'hCF8F; -defparam \z80_|execute_|pc_inc_hold~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~44 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~44_combout = (((!\z80_|pla_decode_|Equal21~0_combout & !\z80_|pla_decode_|Equal3~0_combout )) # (!\z80_|pla_decode_|Equal24~0_combout )) # (!\z80_|execute_|ctl_alu_op_low~8_combout ) - - .dataa(\z80_|pla_decode_|Equal21~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|pla_decode_|Equal3~0_combout ), - .datad(\z80_|pla_decode_|Equal24~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~44 .lut_mask = 16'h37FF; -defparam \z80_|execute_|ctl_inc_cy~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|execute_|ixy_d~10_combout )) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(gnd), - .datad(\z80_|execute_|ixy_d~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 .lut_mask = 16'h8800; -defparam \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~45 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~45_combout = (!\z80_|execute_|pc_inc_hold~50_combout & (!\z80_|execute_|pc_inc_hold~36_combout & (\z80_|execute_|ctl_inc_cy~44_combout & !\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~50_combout ), - .datab(\z80_|execute_|pc_inc_hold~36_combout ), - .datac(\z80_|execute_|ctl_inc_cy~44_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~45 .lut_mask = 16'h0010; -defparam \z80_|execute_|ctl_inc_cy~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~43 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~43_combout = (\z80_|execute_|ctl_mWrite~2_combout & (\z80_|pla_decode_|Equal55~0_combout & ((\z80_|execute_|ctl_mWrite~7_combout ) # (\z80_|execute_|ctl_alu_shift_oe~14_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~7_combout ), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~43 .lut_mask = 16'hC080; -defparam \z80_|execute_|pc_inc_hold~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~71 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~71_combout = (\z80_|execute_|ctl_inc_cy~91_combout & (!\z80_|execute_|pc_inc_hold~46_combout & (\z80_|execute_|ctl_inc_cy~45_combout & !\z80_|execute_|pc_inc_hold~43_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~91_combout ), - .datab(\z80_|execute_|pc_inc_hold~46_combout ), - .datac(\z80_|execute_|ctl_inc_cy~45_combout ), - .datad(\z80_|execute_|pc_inc_hold~43_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~71_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~71 .lut_mask = 16'h0020; -defparam \z80_|execute_|ctl_inc_cy~71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~73 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~73_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (((\z80_|execute_|ctl_inc_cy~72_combout & \z80_|execute_|ctl_inc_cy~71_combout )) # (!\z80_|execute_|pc_inc_hold~38_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|execute_|ctl_inc_cy~72_combout ), - .datac(\z80_|execute_|pc_inc_hold~38_combout ), - .datad(\z80_|execute_|ctl_inc_cy~71_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~73_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~73 .lut_mask = 16'h8A0A; -defparam \z80_|execute_|ctl_inc_cy~73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~46 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~46_combout = (\z80_|execute_|ixy_d~5_combout & (\z80_|execute_|ctl_mWrite~16_combout & ((\z80_|execute_|ctl_inc_cy~45_combout ) # (!\z80_|execute_|pc_inc_hold~38_combout )))) - - .dataa(\z80_|execute_|ctl_inc_cy~45_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|pc_inc_hold~38_combout ), - .datad(\z80_|execute_|ctl_mWrite~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~46 .lut_mask = 16'h8C00; -defparam \z80_|execute_|ctl_inc_cy~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N24 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~53 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~53_combout = (\z80_|pla_decode_|Equal11~0_combout & (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T4_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|sequencer_|DFFE_M4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~53_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~53 .lut_mask = 16'hE000; -defparam \z80_|execute_|pc_inc_hold~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N0 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~39 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~39_combout = (!\z80_|execute_|pc_inc_hold~50_combout & (!\z80_|execute_|pc_inc_hold~53_combout & (\z80_|execute_|pc_inc_hold~35_combout & !\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~50_combout ), - .datab(\z80_|execute_|pc_inc_hold~53_combout ), - .datac(\z80_|execute_|pc_inc_hold~35_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~39 .lut_mask = 16'h0010; -defparam \z80_|execute_|pc_inc_hold~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N10 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~47 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~47_combout = (\z80_|execute_|pc_inc_hold~46_combout ) # ((\z80_|execute_|pc_inc_hold~43_combout ) # ((!\z80_|execute_|ctl_inc_cy~44_combout ) # (!\z80_|execute_|pc_inc_hold~39_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~46_combout ), - .datab(\z80_|execute_|pc_inc_hold~43_combout ), - .datac(\z80_|execute_|pc_inc_hold~39_combout ), - .datad(\z80_|execute_|ctl_inc_cy~44_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~47 .lut_mask = 16'hEFFF; -defparam \z80_|execute_|pc_inc_hold~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~74 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~74_combout = (((!\z80_|execute_|ctl_inc_cy~40_combout ) # (!\z80_|execute_|ctl_inc_cy~34_combout )) # (!\z80_|execute_|ctl_inc_cy~35_combout )) # (!\z80_|execute_|ctl_inc_cy~43_combout ) - - .dataa(\z80_|execute_|ctl_inc_cy~43_combout ), - .datab(\z80_|execute_|ctl_inc_cy~35_combout ), - .datac(\z80_|execute_|ctl_inc_cy~34_combout ), - .datad(\z80_|execute_|ctl_inc_cy~40_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~74_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~74 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_inc_cy~74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~78 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~78_combout = ((\z80_|execute_|ctl_inc_cy~74_combout ) # (!\z80_|execute_|ctl_inc_cy~77_combout )) # (!\z80_|execute_|ctl_inc_cy~39_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_inc_cy~39_combout ), - .datac(\z80_|execute_|ctl_inc_cy~77_combout ), - .datad(\z80_|execute_|ctl_inc_cy~74_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~78_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~78 .lut_mask = 16'hFF3F; -defparam \z80_|execute_|ctl_inc_cy~78 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~79 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~79_combout = (\z80_|execute_|ctl_inc_cy~78_combout & (((!\z80_|execute_|pc_inc_hold~47_combout & \z80_|execute_|ctl_inc_cy~91_combout )) # (!\z80_|execute_|pc_inc_hold~38_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~47_combout ), - .datab(\z80_|execute_|ctl_inc_cy~78_combout ), - .datac(\z80_|execute_|pc_inc_hold~38_combout ), - .datad(\z80_|execute_|ctl_inc_cy~91_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~79_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~79 .lut_mask = 16'h4C0C; -defparam \z80_|execute_|ctl_inc_cy~79 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~80 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~80_combout = (\z80_|execute_|ctl_inc_cy~45_combout & (\z80_|execute_|ctl_alu_op_low~8_combout & (\z80_|execute_|ctl_mRead~36_combout & !\z80_|execute_|pc_inc_hold~43_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~45_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|execute_|ctl_mRead~36_combout ), - .datad(\z80_|execute_|pc_inc_hold~43_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~80_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~80 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_inc_cy~80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~81 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~81_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal19~1_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # (\z80_|execute_|ixy_d~9_combout )))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|pla_decode_|Equal19~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~81_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~81 .lut_mask = 16'hA800; -defparam \z80_|execute_|ctl_inc_cy~81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~82 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~82_combout = (\z80_|execute_|ctl_inc_cy~81_combout ) # ((\z80_|pla_decode_|Equal19~0_combout & ((\z80_|execute_|ctl_state_alu~6_combout ) # (\z80_|execute_|ctl_alu_oe~2_combout )))) - - .dataa(\z80_|execute_|ctl_inc_cy~81_combout ), - .datab(\z80_|pla_decode_|Equal19~0_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_alu_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~82_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~82 .lut_mask = 16'hEEEA; -defparam \z80_|execute_|ctl_inc_cy~82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~83 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~83_combout = (\z80_|execute_|pc_inc_hold~47_combout & (!\z80_|execute_|pc_inc_hold~38_combout & ((\z80_|execute_|ctl_inc_cy~82_combout ) # (!\z80_|execute_|ctl_inc_cy~38_combout )))) # (!\z80_|execute_|pc_inc_hold~47_combout -// & ((\z80_|execute_|ctl_inc_cy~82_combout ) # ((!\z80_|execute_|ctl_inc_cy~38_combout )))) - - .dataa(\z80_|execute_|pc_inc_hold~47_combout ), - .datab(\z80_|execute_|ctl_inc_cy~82_combout ), - .datac(\z80_|execute_|pc_inc_hold~38_combout ), - .datad(\z80_|execute_|ctl_inc_cy~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~83_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~83 .lut_mask = 16'h4C5F; -defparam \z80_|execute_|ctl_inc_cy~83 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~84 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~84_combout = (\z80_|execute_|ctl_inc_cy~79_combout ) # ((\z80_|execute_|ctl_inc_cy~80_combout ) # (\z80_|execute_|ctl_inc_cy~83_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_inc_cy~79_combout ), - .datac(\z80_|execute_|ctl_inc_cy~80_combout ), - .datad(\z80_|execute_|ctl_inc_cy~83_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~84_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~84 .lut_mask = 16'hFFFC; -defparam \z80_|execute_|ctl_inc_cy~84 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N10 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~42 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~42_combout = ((\z80_|execute_|pc_inc_hold~34_combout ) # (\z80_|execute_|pc_inc_hold~52_combout )) # (!\z80_|execute_|pc_inc_hold~30_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|pc_inc_hold~30_combout ), - .datac(\z80_|execute_|pc_inc_hold~34_combout ), - .datad(\z80_|execute_|pc_inc_hold~52_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~42 .lut_mask = 16'hFFF3; -defparam \z80_|execute_|pc_inc_hold~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~90 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~90_combout = (((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|execute_|ctl_mRead~8_combout ) - - .dataa(\z80_|sequencer_|M5~q ), - .datab(\z80_|execute_|ctl_mRead~8_combout ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~90_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~90 .lut_mask = 16'h37FF; -defparam \z80_|execute_|ctl_inc_cy~90 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N2 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~41 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~41_combout = (\z80_|execute_|pc_inc_hold~31_combout ) # ((\z80_|execute_|pc_inc_hold~32_combout ) # ((\z80_|execute_|ixy_d~5_combout & \z80_|execute_|ctl_mRead~9_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~31_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_mRead~9_combout ), - .datad(\z80_|execute_|pc_inc_hold~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~41 .lut_mask = 16'hFFEA; -defparam \z80_|execute_|pc_inc_hold~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~66 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~66_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|execute_|ctl_mRead~14_combout & (!\z80_|decode_state_|in_halt~q & !\z80_|interrupts_|DFFE_inst44~q ))) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|execute_|ctl_mRead~14_combout ), - .datac(\z80_|decode_state_|in_halt~q ), - .datad(\z80_|interrupts_|DFFE_inst44~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~66_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~66 .lut_mask = 16'h0004; -defparam \z80_|execute_|ctl_inc_cy~66 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~67 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~67_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & ((\z80_|execute_|ctl_inc_cy~66_combout ) # ((!\z80_|execute_|ctl_reg_sys_hilo~20_combout & !\z80_|execute_|pc_inc_hold~31_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), - .datac(\z80_|execute_|pc_inc_hold~31_combout ), - .datad(\z80_|execute_|ctl_inc_cy~66_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~67_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~67 .lut_mask = 16'hAA02; -defparam \z80_|execute_|ctl_inc_cy~67 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~68 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~68_combout = (\z80_|execute_|ctl_inc_cy~67_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~14_combout & (!\z80_|execute_|pc_inc_hold~41_combout & \z80_|execute_|ctl_mRead~15_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|execute_|pc_inc_hold~41_combout ), - .datac(\z80_|execute_|ctl_inc_cy~67_combout ), - .datad(\z80_|execute_|ctl_mRead~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~68_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~68 .lut_mask = 16'hF2F0; -defparam \z80_|execute_|ctl_inc_cy~68 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~64 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~64_combout = (!\z80_|execute_|pc_inc_hold~31_combout & (((!\z80_|execute_|ctl_alu_op_low~8_combout & !\z80_|execute_|ixy_d~5_combout )) # (!\z80_|execute_|ctl_mRead~9_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datab(\z80_|execute_|ctl_mRead~9_combout ), - .datac(\z80_|execute_|pc_inc_hold~31_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~64_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~64 .lut_mask = 16'h0307; -defparam \z80_|execute_|ctl_inc_cy~64 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~63 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~63_combout = (\z80_|execute_|ctl_mRead~10_combout & (!\z80_|execute_|pc_inc_hold~34_combout & ((\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (\z80_|execute_|ctl_sw_4u~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|execute_|ctl_mRead~10_combout ), - .datac(\z80_|execute_|pc_inc_hold~34_combout ), - .datad(\z80_|execute_|ctl_sw_4u~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~63_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~63 .lut_mask = 16'h0C08; -defparam \z80_|execute_|ctl_inc_cy~63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~65 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~65_combout = (\z80_|execute_|ctl_inc_cy~63_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & ((\z80_|execute_|ctl_inc_cy~64_combout ) # (!\z80_|execute_|pc_inc_hold~38_combout )))) - - .dataa(\z80_|execute_|pc_inc_hold~38_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), - .datac(\z80_|execute_|ctl_inc_cy~64_combout ), - .datad(\z80_|execute_|ctl_inc_cy~63_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~65_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~65 .lut_mask = 16'hFFC4; -defparam \z80_|execute_|ctl_inc_cy~65 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~69 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~69_combout = (\z80_|execute_|ctl_inc_cy~68_combout ) # ((\z80_|execute_|ctl_inc_cy~65_combout ) # ((!\z80_|execute_|pc_inc_hold~42_combout & !\z80_|execute_|ctl_inc_cy~90_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~42_combout ), - .datab(\z80_|execute_|ctl_inc_cy~90_combout ), - .datac(\z80_|execute_|ctl_inc_cy~68_combout ), - .datad(\z80_|execute_|ctl_inc_cy~65_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~69_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~69 .lut_mask = 16'hFFF1; -defparam \z80_|execute_|ctl_inc_cy~69 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~49 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~49_combout = ((\z80_|pla_decode_|Equal9~1_combout & ((\z80_|execute_|ixy_d~9_combout ) # (\z80_|execute_|ctl_state_alu~6_combout )))) # (!\z80_|execute_|ctl_inc_cy~92_combout ) - - .dataa(\z80_|execute_|ixy_d~9_combout ), - .datab(\z80_|execute_|ctl_state_alu~6_combout ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|execute_|ctl_inc_cy~92_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~49 .lut_mask = 16'hE0FF; -defparam \z80_|execute_|ctl_inc_cy~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~50 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~50_combout = (\z80_|execute_|ixy_d~9_combout & ((\z80_|pla_decode_|Equal11~0_combout ) # ((\z80_|execute_|ctl_mWrite~4_combout & \z80_|execute_|ixy_d~7_combout )))) # (!\z80_|execute_|ixy_d~9_combout & -// (((\z80_|execute_|ctl_mWrite~4_combout & \z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|execute_|ixy_d~9_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~50 .lut_mask = 16'hF888; -defparam \z80_|execute_|ctl_inc_cy~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~51 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~51_combout = (\z80_|execute_|ctl_inc_cy~50_combout ) # (((\z80_|execute_|ctl_mWrite~4_combout & \z80_|execute_|ctl_mRead~11_combout )) # (!\z80_|execute_|ctl_inc_cy~94_combout )) - - .dataa(\z80_|execute_|ctl_inc_cy~50_combout ), - .datab(\z80_|execute_|ctl_mWrite~4_combout ), - .datac(\z80_|execute_|ctl_inc_cy~94_combout ), - .datad(\z80_|execute_|ctl_mRead~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~51_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~51 .lut_mask = 16'hEFAF; -defparam \z80_|execute_|ctl_inc_cy~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~52 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~52_combout = (\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ) # ((\z80_|execute_|ctl_inc_cy~51_combout ) # ((\z80_|execute_|ctl_alu_op_low~8_combout & \z80_|pla_decode_|Equal11~0_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|execute_|ctl_inc_cy~51_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~52_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~52 .lut_mask = 16'hFFEA; -defparam \z80_|execute_|ctl_inc_cy~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~36 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~36_combout = ((!\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|execute_|ctl_alu_op_low~8_combout & !\z80_|execute_|ixy_d~5_combout ))) # (!\z80_|execute_|ctl_mWrite~4_combout ) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|execute_|ctl_mWrite~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~36 .lut_mask = 16'h01FF; -defparam \z80_|execute_|ctl_inc_cy~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~37 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~37_combout = (\z80_|execute_|ctl_sw_2u~0_combout & (\z80_|execute_|ctl_inc_cy~36_combout & ((!\z80_|pla_decode_|Equal11~0_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ctl_sw_2u~0_combout ), - .datad(\z80_|execute_|ctl_inc_cy~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~37 .lut_mask = 16'h7000; -defparam \z80_|execute_|ctl_inc_cy~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~54 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~54_combout = ((\z80_|execute_|ctl_inc_cy~49_combout ) # ((\z80_|execute_|ctl_inc_cy~52_combout ) # (!\z80_|execute_|ctl_inc_cy~37_combout ))) # (!\z80_|execute_|ctl_inc_cy~53_combout ) - - .dataa(\z80_|execute_|ctl_inc_cy~53_combout ), - .datab(\z80_|execute_|ctl_inc_cy~49_combout ), - .datac(\z80_|execute_|ctl_inc_cy~52_combout ), - .datad(\z80_|execute_|ctl_inc_cy~37_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~54_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~54 .lut_mask = 16'hFDFF; -defparam \z80_|execute_|ctl_inc_cy~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~41 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~41_combout = (!\z80_|execute_|ctl_mRead~17_combout & (!\z80_|pla_decode_|Equal34~0_combout & ((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~17_combout ), - .datab(\z80_|pla_decode_|Equal12~1_combout ), - .datac(\z80_|pla_decode_|Equal25~0_combout ), - .datad(\z80_|pla_decode_|Equal34~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~41 .lut_mask = 16'h0045; -defparam \z80_|execute_|ctl_inc_cy~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~58 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~58_combout = (\z80_|execute_|ctl_mRead~4_combout ) # ((\z80_|execute_|ctl_mWrite~6_combout ) # (!\z80_|execute_|ctl_inc_cy~41_combout )) - - .dataa(\z80_|execute_|ctl_mRead~4_combout ), - .datab(\z80_|execute_|ctl_mWrite~6_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_inc_cy~41_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~58_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~58 .lut_mask = 16'hEEFF; -defparam \z80_|execute_|ctl_inc_cy~58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~55 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~55_combout = (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|execute_|ctl_alu_op_low~8_combout ) # ((\z80_|execute_|ixy_d~9_combout )))) # (!\z80_|pla_decode_|Equal10~0_combout & (\z80_|execute_|ctl_alu_op_low~8_combout & -// ((\z80_|execute_|ctl_mRead~36_combout )))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|execute_|ctl_mRead~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~55_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~55 .lut_mask = 16'hECA8; -defparam \z80_|execute_|ctl_inc_cy~55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~56 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~56_combout = (((!\z80_|execute_|ctl_reg_sys_we~2_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout )) # (!\z80_|execute_|ctl_reg_sel_pc~17_combout )) # (!\z80_|execute_|fMRead~3_combout ) - - .dataa(\z80_|execute_|fMRead~3_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~17_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), - .datad(\z80_|execute_|ctl_reg_sys_we~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~56_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~56 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_inc_cy~56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~89 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~89_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|pla_decode_|Equal41~2_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~30_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|execute_|ctl_bus_inc_oe~30_combout ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|pla_decode_|Equal41~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~89_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~89 .lut_mask = 16'hA020; -defparam \z80_|execute_|ctl_inc_cy~89 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~57 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~57_combout = ((\z80_|execute_|ctl_inc_cy~55_combout ) # ((\z80_|execute_|ctl_inc_cy~56_combout ) # (\z80_|execute_|ctl_inc_cy~89_combout ))) # (!\z80_|execute_|ctl_reg_sel_pc~7_combout ) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~7_combout ), - .datab(\z80_|execute_|ctl_inc_cy~55_combout ), - .datac(\z80_|execute_|ctl_inc_cy~56_combout ), - .datad(\z80_|execute_|ctl_inc_cy~89_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~57_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~57 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_inc_cy~57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~59 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~59_combout = (\z80_|execute_|ctl_inc_cy~57_combout ) # ((\z80_|execute_|ctl_alu_op_low~8_combout & ((\z80_|execute_|ctl_inc_cy~58_combout ) # (!\z80_|execute_|fMRead~5_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datab(\z80_|execute_|ctl_inc_cy~58_combout ), - .datac(\z80_|execute_|fMRead~5_combout ), - .datad(\z80_|execute_|ctl_inc_cy~57_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~59_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~59 .lut_mask = 16'hFF8A; -defparam \z80_|execute_|ctl_inc_cy~59 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~60 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~60_combout = (\z80_|execute_|pc_inc_hold~38_combout & (\z80_|execute_|pc_inc_hold~35_combout & (\z80_|execute_|ctl_inc_cy~54_combout ))) # (!\z80_|execute_|pc_inc_hold~38_combout & (((\z80_|execute_|ctl_inc_cy~54_combout ) # -// (\z80_|execute_|ctl_inc_cy~59_combout )))) - - .dataa(\z80_|execute_|pc_inc_hold~38_combout ), - .datab(\z80_|execute_|pc_inc_hold~35_combout ), - .datac(\z80_|execute_|ctl_inc_cy~54_combout ), - .datad(\z80_|execute_|ctl_inc_cy~59_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~60_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~60 .lut_mask = 16'hD5D0; -defparam \z80_|execute_|ctl_inc_cy~60 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~47 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~47_combout = (\z80_|execute_|ctl_state_alu~14_combout & (!\z80_|execute_|pc_inc_hold~36_combout & (\z80_|execute_|ctl_alu_op_low~8_combout & !\z80_|execute_|pc_inc_hold~50_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~14_combout ), - .datab(\z80_|execute_|pc_inc_hold~36_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datad(\z80_|execute_|pc_inc_hold~50_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~47 .lut_mask = 16'h0020; -defparam \z80_|execute_|ctl_inc_cy~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~88 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~88_combout = (\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ) # ((\z80_|pla_decode_|Equal13~2_combout & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ))) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~88_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~88 .lut_mask = 16'hECCC; -defparam \z80_|execute_|ctl_inc_cy~88 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~48 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~48_combout = (\z80_|execute_|ctl_inc_cy~47_combout ) # ((\z80_|execute_|ctl_inc_cy~88_combout & ((\z80_|execute_|pc_inc_hold~39_combout ) # (!\z80_|execute_|pc_inc_hold~38_combout )))) - - .dataa(\z80_|execute_|pc_inc_hold~39_combout ), - .datab(\z80_|execute_|ctl_inc_cy~47_combout ), - .datac(\z80_|execute_|ctl_inc_cy~88_combout ), - .datad(\z80_|execute_|pc_inc_hold~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~48 .lut_mask = 16'hECFC; -defparam \z80_|execute_|ctl_inc_cy~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N18 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~40 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~40_combout = (\z80_|execute_|pc_inc_hold~30_combout & !\z80_|execute_|pc_inc_hold~34_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|pc_inc_hold~30_combout ), - .datac(\z80_|execute_|pc_inc_hold~34_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~40 .lut_mask = 16'h0C0C; -defparam \z80_|execute_|pc_inc_hold~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~61 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~61_combout = (!\z80_|execute_|pc_inc_hold~36_combout & (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|execute_|ixy_d~9_combout ) # (\z80_|execute_|ctl_alu_op_low~8_combout )))) - - .dataa(\z80_|execute_|ixy_d~9_combout ), - .datab(\z80_|execute_|pc_inc_hold~36_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datad(\z80_|pla_decode_|Equal10~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~61_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~61 .lut_mask = 16'h3200; -defparam \z80_|execute_|ctl_inc_cy~61 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~62 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~62_combout = (\z80_|execute_|ctl_inc_cy~61_combout ) # ((!\z80_|execute_|ctl_inc_cy~42_combout & ((\z80_|execute_|pc_inc_hold~40_combout ) # (!\z80_|execute_|pc_inc_hold~38_combout )))) - - .dataa(\z80_|execute_|pc_inc_hold~38_combout ), - .datab(\z80_|execute_|pc_inc_hold~40_combout ), - .datac(\z80_|execute_|ctl_inc_cy~61_combout ), - .datad(\z80_|execute_|ctl_inc_cy~42_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~62_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~62 .lut_mask = 16'hF0FD; -defparam \z80_|execute_|ctl_inc_cy~62 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~70 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~70_combout = (\z80_|execute_|ctl_inc_cy~69_combout ) # ((\z80_|execute_|ctl_inc_cy~60_combout ) # ((\z80_|execute_|ctl_inc_cy~48_combout ) # (\z80_|execute_|ctl_inc_cy~62_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~69_combout ), - .datab(\z80_|execute_|ctl_inc_cy~60_combout ), - .datac(\z80_|execute_|ctl_inc_cy~48_combout ), - .datad(\z80_|execute_|ctl_inc_cy~62_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~70_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~70 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_inc_cy~70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~85 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~85_combout = (\z80_|execute_|ctl_inc_cy~73_combout ) # ((\z80_|execute_|ctl_inc_cy~46_combout ) # ((\z80_|execute_|ctl_inc_cy~84_combout ) # (\z80_|execute_|ctl_inc_cy~70_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~73_combout ), - .datab(\z80_|execute_|ctl_inc_cy~46_combout ), - .datac(\z80_|execute_|ctl_inc_cy~84_combout ), - .datad(\z80_|execute_|ctl_inc_cy~70_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~85_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~85 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_inc_cy~85 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N28 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout = \z80_|address_latch_|Q [0] $ (\z80_|execute_|ctl_inc_cy~85_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|address_latch_|Q [0]), - .datad(\z80_|execute_|ctl_inc_cy~85_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out .lut_mask = 16'h0FF0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N8 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~3 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[0]~3_combout = ((\z80_|reg_file_|db_lo_as[0]~1_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[0]~1_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[0]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[0]~3 .lut_mask = 16'hAF2F; -defparam \z80_|reg_file_|db_lo_as[0]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N28 -cycloneive_lcell_comb \z80_|address_latch_|abusz[0] ( -// Equation(s): -// \z80_|address_latch_|abusz [0] = (\z80_|reg_file_|db_lo_as[0]~3_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|reg_file_|db_lo_as[0]~3_combout ), - .datad(\z80_|resets_|clrpc~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [0]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[0] .lut_mask = 16'h00F0; -defparam \z80_|address_latch_|abusz[0] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N22 -cycloneive_lcell_comb \z80_|address_latch_|Q[0]~feeder ( -// Equation(s): -// \z80_|address_latch_|Q[0]~feeder_combout = \z80_|address_latch_|abusz [0] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [0]), - .cin(gnd), - .combout(\z80_|address_latch_|Q[0]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|Q[0]~feeder .lut_mask = 16'hFF00; -defparam \z80_|address_latch_|Q[0]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N23 -dffeas \z80_|address_latch_|Q[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|Q[0]~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[0] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N4 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout = \z80_|address_latch_|Q [0] $ (((\z80_|execute_|ctl_inc_dec~9_combout ) # ((\z80_|execute_|ctl_inc_dec~7_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout )))) - - .dataa(\z80_|execute_|ctl_inc_dec~9_combout ), - .datab(\z80_|execute_|ctl_inc_dec~6_combout ), - .datac(\z80_|address_latch_|Q [0]), - .datad(\z80_|execute_|ctl_inc_dec~7_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 .lut_mask = 16'h0F4B; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y17_N5 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[1]~6_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X31_Y13_N23 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[1]~6_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N22 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~4 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[1]~4_combout = (\z80_|reg_file_|gdfx_temp0[1]~32_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) # (!\z80_|reg_file_|gdfx_temp0[1]~32_combout & -// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [1]), - .datad(\z80_|execute_|ctl_sw_4d~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[1]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[1]~4 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_lo_as[1]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N26 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~5 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[1]~5_combout = (\z80_|reg_file_|db_lo_as[1]~4_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_lo|latch [1]), - .datad(\z80_|reg_file_|db_lo_as[1]~4_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[1]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[1]~5 .lut_mask = 16'hF300; -defparam \z80_|reg_file_|db_lo_as[1]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N24 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout = \z80_|address_latch_|Q [1] $ (((\z80_|execute_|ctl_inc_cy~85_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ))) - - .dataa(\z80_|address_latch_|Q [1]), - .datab(\z80_|execute_|ctl_inc_cy~85_combout ), - .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out .lut_mask = 16'h6A6A; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N4 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~6 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[1]~6_combout = ((\z80_|reg_file_|db_lo_as[1]~5_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[1]~5_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[1]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[1]~6 .lut_mask = 16'hAF2F; -defparam \z80_|reg_file_|db_lo_as[1]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N14 -cycloneive_lcell_comb \z80_|address_latch_|abusz[1] ( -// Equation(s): -// \z80_|address_latch_|abusz [1] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[1]~6_combout ) - - .dataa(gnd), - .datab(\z80_|resets_|clrpc~0_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|db_lo_as[1]~6_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [1]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[1] .lut_mask = 16'h3300; -defparam \z80_|address_latch_|abusz[1] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y17_N19 -dffeas \z80_|address_latch_|Q[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|address_latch_|abusz [1]), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[1] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N6 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout = \z80_|address_latch_|Q [1] $ ((((\z80_|execute_|ctl_inc_dec~10_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )) # (!\z80_|execute_|ctl_inc_dec~5_combout ))) - - .dataa(\z80_|execute_|ctl_inc_dec~5_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .datac(\z80_|address_latch_|Q [1]), - .datad(\z80_|execute_|ctl_inc_dec~10_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4 .lut_mask = 16'h0F87; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N22 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout = \z80_|address_latch_|Q [2] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout & (\z80_|execute_|ctl_inc_cy~85_combout & -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout )))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), - .datab(\z80_|execute_|ctl_inc_cy~85_combout ), - .datac(\z80_|address_latch_|Q [2]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out .lut_mask = 16'h78F0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N16 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~9 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[2]~9_combout = ((\z80_|reg_file_|db_lo_as[2]~8_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|reg_file_|db_lo_as[2]~8_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[2]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[2]~9 .lut_mask = 16'hF575; -defparam \z80_|reg_file_|db_lo_as[2]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N12 -cycloneive_lcell_comb \z80_|address_latch_|abusz[2] ( -// Equation(s): -// \z80_|address_latch_|abusz [2] = (\z80_|reg_file_|db_lo_as[2]~9_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[2]~9_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|resets_|clrpc~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [2]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[2] .lut_mask = 16'h00AA; -defparam \z80_|address_latch_|abusz[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N14 -cycloneive_lcell_comb \z80_|address_latch_|Q[2]~feeder ( -// Equation(s): -// \z80_|address_latch_|Q[2]~feeder_combout = \z80_|address_latch_|abusz [2] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [2]), - .cin(gnd), - .combout(\z80_|address_latch_|Q[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|Q[2]~feeder .lut_mask = 16'hFF00; -defparam \z80_|address_latch_|Q[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y17_N15 -dffeas \z80_|address_latch_|Q[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|Q[2]~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[2] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N2 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout = \z80_|address_latch_|Q [2] $ (((\z80_|execute_|ctl_inc_dec~10_combout ) # ((!\z80_|execute_|ctl_inc_dec~5_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) - - .dataa(\z80_|execute_|ctl_inc_dec~10_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .datac(\z80_|execute_|ctl_inc_dec~5_combout ), - .datad(\z80_|address_latch_|Q [2]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42 .lut_mask = 16'h40BF; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~86 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~86_combout = (\z80_|execute_|ctl_inc_cy~73_combout ) # ((\z80_|execute_|ctl_inc_cy~79_combout ) # ((\z80_|execute_|ctl_inc_cy~80_combout ) # (\z80_|execute_|ctl_inc_cy~83_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~73_combout ), - .datab(\z80_|execute_|ctl_inc_cy~79_combout ), - .datac(\z80_|execute_|ctl_inc_cy~80_combout ), - .datad(\z80_|execute_|ctl_inc_cy~83_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~86_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~86 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_inc_cy~86 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N0 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout & ((\z80_|execute_|ctl_inc_cy~46_combout ) # ((\z80_|execute_|ctl_inc_cy~86_combout ) # -// (\z80_|execute_|ctl_inc_cy~70_combout )))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), - .datab(\z80_|execute_|ctl_inc_cy~46_combout ), - .datac(\z80_|execute_|ctl_inc_cy~86_combout ), - .datad(\z80_|execute_|ctl_inc_cy~70_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'hAAA8; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~11 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~11_combout = (\z80_|execute_|ctl_inc_dec~9_combout ) # (((!\z80_|execute_|ctl_bus_inc_oe~33_combout ) # (!\z80_|execute_|ctl_inc_dec~5_combout )) # (!\z80_|execute_|ctl_inc_dec~6_combout )) - - .dataa(\z80_|execute_|ctl_inc_dec~9_combout ), - .datab(\z80_|execute_|ctl_inc_dec~6_combout ), - .datac(\z80_|execute_|ctl_inc_dec~5_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~11 .lut_mask = 16'hBFFF; -defparam \z80_|execute_|ctl_inc_dec~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N0 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout = (\z80_|execute_|ctl_inc_cy~85_combout & ((\z80_|address_latch_|Q [1] & (!\z80_|execute_|ctl_inc_dec~11_combout & \z80_|address_latch_|Q [0])) # (!\z80_|address_latch_|Q -// [1] & (\z80_|execute_|ctl_inc_dec~11_combout & !\z80_|address_latch_|Q [0])))) - - .dataa(\z80_|address_latch_|Q [1]), - .datab(\z80_|execute_|ctl_inc_dec~11_combout ), - .datac(\z80_|address_latch_|Q [0]), - .datad(\z80_|execute_|ctl_inc_cy~85_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0 .lut_mask = 16'h2400; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N10 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout = \z80_|address_latch_|Q [3] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout -// ))) - - .dataa(gnd), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ), - .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ), - .datad(\z80_|address_latch_|Q [3]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out .lut_mask = 16'h3FC0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N15 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y10_N21 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~45 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~45_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [3]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [3]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~45 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[3]~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N26 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp0[3]~52_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y11_N27 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y11_N11 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~48 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~48_combout = (\z80_|reg_file_|b2v_latch_ix_lo|latch [3] & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # (!\z80_|reg_file_|b2v_latch_ix_lo|latch [3] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_ix_lo|latch [3]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc_lo|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~48 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[3]~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y10_N5 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y10_N11 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~49 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~49_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [3]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_iy_lo|latch [3]), - .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~49 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[3]~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N12 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp0[3]~52_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y11_N13 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y11_N27 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~41 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~41_combout = ((!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ), - .datac(\z80_|execute_|nextM~2_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~41 .lut_mask = 16'h3F3B; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~42 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~42_combout = ((\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mRead~5_combout ) # (!\z80_|execute_|ctl_al_we~14_combout )))) # (!\z80_|execute_|setM1~29_combout ) - - .dataa(\z80_|execute_|ctl_mRead~5_combout ), - .datab(\z80_|execute_|setM1~29_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_al_we~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~42 .lut_mask = 16'hB3F3; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~43 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~43_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ) # ((!\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout & !\z80_|execute_|rsel3~combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ), - .datab(\z80_|execute_|rsel3~combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~43 .lut_mask = 16'hFFF1; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~44 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~44_combout = ((\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ) # ((!\z80_|execute_|rsel0~combout & \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ), - .datab(\z80_|execute_|rsel0~combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~44 .lut_mask = 16'hF7F5; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~45 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~45_combout = ((\z80_|execute_|ctl_state_alu~5_combout & ((!\z80_|execute_|setM1~46_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout )))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), - .datab(\z80_|execute_|ctl_state_alu~5_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), - .datad(\z80_|execute_|setM1~46_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~45 .lut_mask = 16'h5DDD; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~46 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout = ((\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ) # (!\z80_|execute_|ctl_reg_gp_we~2_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~46 .lut_mask = 16'hFDFF; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N14 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_48 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_48~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_de~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_de~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_48 .lut_mask = 16'h0C00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N20 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_44 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_44~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_de2~4_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_de2~4_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_44 .lut_mask = 16'h0C00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N4 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_45 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_45~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_de2~4_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_de2~4_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_45 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y13_N15 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N6 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_49 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_49~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_de~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_de~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_49 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y13_N1 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~40 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~40_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [3]), - .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [3]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~40 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[3]~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N12 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_52 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_52~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl2~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_52 .lut_mask = 16'h0C00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N18 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_57 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_57~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_57 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N9 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N16 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_53 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_53~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl2~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_53 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N19 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N30 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_56 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_56~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_56 .lut_mask = 16'h0C00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~41 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~41_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [3]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [3]), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~41 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp1[3]~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N26 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_33 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_33~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_af~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_af~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_33 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y14_N5 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N4 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[3]~18 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[3]~18_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [3]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [3]), - .datad(\z80_|reg_control_|reg_sel_af~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[3]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[3]~18 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[3]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~11 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~11_combout = (((\z80_|pla_decode_|Equal9~1_combout & \z80_|execute_|ixy_d~6_combout )) # (!\z80_|execute_|ctl_reg_in_hi~5_combout )) # (!\z80_|execute_|ctl_reg_in_hi~6_combout ) - - .dataa(\z80_|pla_decode_|Equal9~1_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~6_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~11 .lut_mask = 16'hB3FF; -defparam \z80_|execute_|ctl_reg_in_hi~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~12 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~12_combout = (\z80_|execute_|ctl_reg_in_hi~11_combout ) # (((!\z80_|execute_|ctl_reg_in_hi~4_combout ) # (!\z80_|execute_|ctl_reg_in_hi~3_combout )) # (!\z80_|execute_|ctl_reg_in_hi~10_combout )) - - .dataa(\z80_|execute_|ctl_reg_in_hi~11_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~10_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~3_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~12 .lut_mask = 16'hBFFF; -defparam \z80_|execute_|ctl_reg_in_hi~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N12 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_29 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_29~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_af2~0_combout & \z80_|execute_|ctl_reg_gp_we~6_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datab(gnd), - .datac(\z80_|reg_control_|reg_sel_af2~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_29 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y11_N19 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N2 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_28 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_28~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_af2~0_combout & !\z80_|execute_|ctl_reg_gp_we~6_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datab(gnd), - .datac(\z80_|reg_control_|reg_sel_af2~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_28 .lut_mask = 16'h00A0; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~44 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~44_combout = (\z80_|alu_|db[3]~11_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[3]~11_combout & (!\z80_|execute_|ctl_reg_in_hi~12_combout & -// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|alu_|db[3]~11_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~44 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[3]~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N8 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp1[3]~48_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N12 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_69 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_69~combout = (\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & \z80_|reg_control_|reg_sel_iy~2_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datad(\z80_|reg_control_|reg_sel_iy~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y12_N9 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N24 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout = (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(gnd), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 .lut_mask = 16'h4444; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N2 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|decode_state_|DFFE_inst4~q & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|decode_state_|DFFE_inst4~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 .lut_mask = 16'h4000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N8 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & \z80_|execute_|ctl_reg_gp_we~6_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 .lut_mask = 16'hF000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N4 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout = (\z80_|decode_state_|DFFE_inst4~q & (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 .lut_mask = 16'h0080; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y12_N29 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N14 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_68 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_68~combout = (!\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & \z80_|reg_control_|reg_sel_iy~2_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datad(\z80_|reg_control_|reg_sel_iy~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68 .lut_mask = 16'h3000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~43 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~43_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [3] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [3] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [3]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~43 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[3]~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N20 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N22 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout = (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y15_N23 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~31 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~31_combout = (!\z80_|ir_|opcode [3] & ((\z80_|execute_|ctl_alu_op_low~14_combout ) # ((\z80_|pla_decode_|Equal48~0_combout & \z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal48~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~31 .lut_mask = 16'h5450; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~30 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~30_combout = ((\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ) # ((\z80_|pla_decode_|Equal35~0_combout & \z80_|execute_|ixy_d~6_combout ))) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ) - - .dataa(\z80_|pla_decode_|Equal35~0_combout ), - .datab(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~30 .lut_mask = 16'hFFB3; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~32 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~32_combout = (((\z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ) # (\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout )) # (!\z80_|execute_|ctl_reg_out_hi~4_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), - .datab(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~32 .lut_mask = 16'hFFF7; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~33 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~33_combout = ((\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ) # ((!\z80_|execute_|ctl_reg_in_hi~5_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ))) # (!\z80_|execute_|ctl_reg_sel_wz~12_combout ) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~12_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~33 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N30 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_hi~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_hi~0_combout = ((\z80_|execute_|ixy_d~6_combout & ((\z80_|pla_decode_|Equal19~0_combout ) # (\z80_|execute_|ctl_reg_sys_we_lo~3_combout )))) # (!\z80_|execute_|ctl_reg_sel_wz~13_combout ) - - .dataa(\z80_|pla_decode_|Equal19~0_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~13_combout ), - .datac(\z80_|execute_|ctl_reg_sys_we_lo~3_combout ), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_hi~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_hi~0 .lut_mask = 16'hFB33; -defparam \z80_|reg_control_|reg_sys_we_hi~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N14 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_hi ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_hi~combout = ((\z80_|reg_control_|reg_sys_we_hi~0_combout ) # (\z80_|execute_|ctl_reg_sys_we~3_combout )) # (!\z80_|execute_|ctl_reg_in_hi~4_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_in_hi~4_combout ), - .datac(\z80_|reg_control_|reg_sys_we_hi~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_we~3_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_hi~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_hi .lut_mask = 16'hFFF3; -defparam \z80_|reg_control_|reg_sys_we_hi .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N4 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_81 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_81~combout = (\z80_|execute_|ctl_reg_sel_wz~17_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & \z80_|reg_control_|reg_sys_we_hi~combout )) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~17_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_81 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y12_N27 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N22 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_80 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_80~combout = (\z80_|execute_|ctl_reg_sel_wz~17_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & !\z80_|reg_control_|reg_sys_we_hi~combout )) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~17_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_80 .lut_mask = 16'h00A0; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~45 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~45_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [3]), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~45 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[3]~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N6 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & (!\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), - .datab(\z80_|reg_control_|bank_exx~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 .lut_mask = 16'h0002; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y13_N1 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N10 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|reg_control_|bank_exx~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 .lut_mask = 16'h0400; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N16 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & (\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), - .datab(\z80_|reg_control_|bank_exx~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 .lut_mask = 16'h0008; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y13_N3 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N4 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|reg_control_|bank_exx~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 .lut_mask = 16'h0100; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~42 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~42_combout = (\z80_|reg_file_|b2v_latch_bc_hi|latch [3] & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_hi|latch [3] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc_hi|latch [3]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~42 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[3]~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~46 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~46_combout = (\z80_|reg_file_|gdfx_temp1[3]~44_combout & (\z80_|reg_file_|gdfx_temp1[3]~43_combout & (\z80_|reg_file_|gdfx_temp1[3]~45_combout & \z80_|reg_file_|gdfx_temp1[3]~42_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[3]~44_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[3]~43_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[3]~45_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[3]~42_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~46 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[3]~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~47 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~47_combout = (\z80_|reg_file_|gdfx_temp1[3]~40_combout & (\z80_|reg_file_|gdfx_temp1[3]~41_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[3]~18_combout & \z80_|reg_file_|gdfx_temp1[3]~46_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[3]~40_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[3]~41_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|db[3]~18_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[3]~46_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~47 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[3]~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~17 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~17_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ) # ((\z80_|reg_control_|reg_sel_af~0_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) - - .dataa(\z80_|reg_control_|reg_sel_af~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~17 .lut_mask = 16'hFFF8; -defparam \z80_|reg_file_|gdfx_temp1[0]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~18 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~18_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~18 .lut_mask = 16'hFEFE; -defparam \z80_|reg_file_|gdfx_temp1[0]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~19 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~19_combout = (\z80_|reg_file_|gdfx_temp1[0]~17_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ) # ((\z80_|reg_file_|gdfx_temp1[0]~18_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~17_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[0]~18_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~19 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp1[0]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~16 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~16_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~16 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp1[0]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~20 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~20_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout ) # ((\z80_|reg_file_|gdfx_temp1[0]~19_combout ) # ((\z80_|execute_|ctl_sw_4u~6_combout ) # (\z80_|reg_file_|gdfx_temp1[0]~16_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~19_combout ), - .datac(\z80_|execute_|ctl_sw_4u~6_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[0]~16_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~20 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp1[0]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N10 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_73 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_73~combout = (\z80_|reg_control_|reg_sel_pc~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & \z80_|reg_control_|reg_sys_we_hi~combout )) - - .dataa(\z80_|reg_control_|reg_sel_pc~combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_73 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N13 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[1]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y13_N19 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y13_N25 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~8 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~8_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [1]), - .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [1]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~8 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[1]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y14_N3 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N2 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[1]~15 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[1]~15_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [1]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [1]), - .datad(\z80_|reg_control_|reg_sel_af~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[1]~15 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y15_N9 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y12_N11 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~13 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~13_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [1]), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~13 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[1]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y11_N21 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~12 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~12_combout = (\z80_|alu_|db[1]~13_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[1]~13_combout & (!\z80_|execute_|ctl_reg_in_hi~12_combout & -// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|alu_|db[1]~13_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~12 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[1]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y13_N5 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y13_N31 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~10 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~10_combout = (\z80_|reg_file_|b2v_latch_bc_hi|latch [1] & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_hi|latch [1] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc_hi|latch [1]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~10 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[1]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y12_N21 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N28 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder_combout = \z80_|reg_file_|gdfx_temp1[1]~21_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y12_N29 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~11 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~11_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [1]), - .datad(\z80_|reg_file_|b2v_latch_iy_hi|latch [1]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~11 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[1]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~14 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~14_combout = (\z80_|reg_file_|gdfx_temp1[1]~13_combout & (\z80_|reg_file_|gdfx_temp1[1]~12_combout & (\z80_|reg_file_|gdfx_temp1[1]~10_combout & \z80_|reg_file_|gdfx_temp1[1]~11_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[1]~13_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[1]~12_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[1]~10_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[1]~11_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~14 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[1]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N15 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y14_N17 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~9 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~9_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [1]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [1]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~9 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[1]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~15 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~15_combout = (\z80_|reg_file_|gdfx_temp1[1]~8_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[1]~15_combout & (\z80_|reg_file_|gdfx_temp1[1]~14_combout & \z80_|reg_file_|gdfx_temp1[1]~9_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[1]~8_combout ), - .datab(\z80_|reg_file_|b2v_latch_af_hi|db[1]~15_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[1]~14_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[1]~9_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~15 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~21 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~21_combout = ((\z80_|reg_file_|gdfx_temp1[1]~15_combout & ((\z80_|reg_file_|db_hi_as[1]~3_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[1]~15_combout ), - .datac(\z80_|reg_file_|db_hi_as[1]~3_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~21 .lut_mask = 16'hD5DD; -defparam \z80_|reg_file_|gdfx_temp1[1]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N28 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_60 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_60~combout = (!\z80_|reg_control_|reg_sys_we_hi~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & \z80_|execute_|ctl_reg_sel_ir~1_combout )) - - .dataa(\z80_|reg_control_|reg_sys_we_hi~combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datad(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_60 .lut_mask = 16'h5000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_60 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N16 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_61 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_61~combout = (\z80_|reg_control_|reg_sys_we_hi~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & \z80_|execute_|ctl_reg_sel_ir~1_combout )) - - .dataa(\z80_|reg_control_|reg_sys_we_hi~combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datad(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_61 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_61 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y15_N17 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[1]~3_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N6 -cycloneive_lcell_comb \z80_|reg_control_|reg_sw_4d_hi~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sw_4d_hi~0_combout = (\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_control_|reg_sys_we_lo~combout ) # ((!\z80_|execute_|ctl_reg_sel_ir~1_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout )))) - - .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), - .datab(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datad(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sw_4d_hi~0 .lut_mask = 16'h8AAA; -defparam \z80_|reg_control_|reg_sw_4d_hi~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N16 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~0 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[1]~0_combout = (\z80_|reg_file_|gdfx_temp1[1]~21_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) # (!\z80_|reg_file_|gdfx_temp1[1]~21_combout & -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [1]), - .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[1]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[1]~0 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_hi_as[1]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N12 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_72 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_72~combout = (\z80_|reg_control_|reg_sel_pc~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & !\z80_|reg_control_|reg_sys_we_hi~combout )) - - .dataa(\z80_|reg_control_|reg_sel_pc~combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_72 .lut_mask = 16'h00A0; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_72 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N10 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~1 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[1]~1_combout = (\z80_|reg_file_|db_hi_as[1]~0_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|b2v_latch_pc_hi|latch [1]), - .datab(gnd), - .datac(\z80_|reg_file_|db_hi_as[1]~0_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[1]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[1]~1 .lut_mask = 16'hA0F0; -defparam \z80_|reg_file_|db_hi_as[1]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N30 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~2 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[0]~2_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ) # ((\z80_|execute_|ctl_bus_inc_oe~41_combout ) # (\z80_|reg_control_|reg_sw_4d_hi~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[0]~2 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|db_hi_as[0]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N2 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout = \z80_|address_latch_|Q [8] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout & (\z80_|address_latch_|Q [7] $ (\z80_|execute_|ctl_inc_dec~11_combout ))))) - - .dataa(\z80_|address_latch_|Q [7]), - .datab(\z80_|address_latch_|Q [8]), - .datac(\z80_|execute_|ctl_inc_dec~11_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out .lut_mask = 16'h96CC; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y15_N27 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[0]~6_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y14_N3 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y14_N1 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~23 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~23_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [0]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [0]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~23 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[0]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y13_N7 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y13_N29 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~22 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~22_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [0]), - .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [0]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~22 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[0]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y13_N21 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y13_N7 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~24 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~24_combout = (\z80_|reg_file_|b2v_latch_bc2_hi|latch [0] & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # (!\z80_|reg_file_|b2v_latch_bc2_hi|latch [0] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc_hi|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~24 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[0]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y11_N15 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~26 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~26_combout = (\z80_|alu_|db[0]~19_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[0]~19_combout & (!\z80_|execute_|ctl_reg_in_hi~12_combout & -// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|alu_|db[0]~19_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~26 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[0]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N26 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder_combout = \z80_|reg_file_|gdfx_temp1[0]~30_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y12_N27 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y12_N5 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~25 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~25_combout = (\z80_|reg_file_|b2v_latch_ix_hi|latch [0] & (((\z80_|reg_file_|b2v_latch_iy_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ))) # (!\z80_|reg_file_|b2v_latch_ix_hi|latch [0] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & ((\z80_|reg_file_|b2v_latch_iy_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_ix_hi|latch [0]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datac(\z80_|reg_file_|b2v_latch_iy_hi|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~25 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[0]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y14_N13 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X26_Y14_N7 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~27 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~27_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (\z80_|reg_file_|b2v_latch_wz_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (((\z80_|reg_file_|b2v_latch_sp_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_sp_hi|latch [0]), - .datad(\z80_|reg_file_|b2v_latch_wz_hi|latch [0]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~27 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[0]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~28 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~28_combout = (\z80_|reg_file_|gdfx_temp1[0]~24_combout & (\z80_|reg_file_|gdfx_temp1[0]~26_combout & (\z80_|reg_file_|gdfx_temp1[0]~25_combout & \z80_|reg_file_|gdfx_temp1[0]~27_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~24_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~26_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[0]~25_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[0]~27_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~28 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[0]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y14_N29 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N28 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[0]~16 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[0]~16_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [0]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [0]), - .datad(\z80_|reg_control_|reg_sel_af~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[0]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[0]~16 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[0]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~29 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~29_combout = (\z80_|reg_file_|gdfx_temp1[0]~23_combout & (\z80_|reg_file_|gdfx_temp1[0]~22_combout & (\z80_|reg_file_|gdfx_temp1[0]~28_combout & \z80_|reg_file_|b2v_latch_af_hi|db[0]~16_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~23_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~22_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[0]~28_combout ), - .datad(\z80_|reg_file_|b2v_latch_af_hi|db[0]~16_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~29 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[0]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~30 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~30_combout = ((\z80_|reg_file_|gdfx_temp1[0]~29_combout & ((\z80_|reg_file_|db_hi_as[0]~6_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|db_hi_as[0]~6_combout ), - .datab(\z80_|execute_|ctl_sw_4u~6_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[0]~29_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~30 .lut_mask = 16'hBF0F; -defparam \z80_|reg_file_|gdfx_temp1[0]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y15_N21 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[0]~6_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N20 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~4 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[0]~4_combout = (\z80_|reg_control_|reg_sw_4d_hi~0_combout & (\z80_|reg_file_|gdfx_temp1[0]~30_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) - - .dataa(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[0]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[0]~4 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|db_hi_as[0]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N24 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~5 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[0]~5_combout = (\z80_|reg_file_|db_hi_as[0]~4_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datab(gnd), - .datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [0]), - .datad(\z80_|reg_file_|db_hi_as[0]~4_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[0]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[0]~5 .lut_mask = 16'hF500; -defparam \z80_|reg_file_|db_hi_as[0]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N26 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~6 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[0]~6_combout = ((\z80_|reg_file_|db_hi_as[0]~5_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), - .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datad(\z80_|reg_file_|db_hi_as[0]~5_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[0]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[0]~6 .lut_mask = 16'hDF0F; -defparam \z80_|reg_file_|db_hi_as[0]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N8 -cycloneive_lcell_comb \z80_|address_latch_|abusz[8] ( -// Equation(s): -// \z80_|address_latch_|abusz [8] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[0]~6_combout ) - - .dataa(\z80_|resets_|clrpc~0_combout ), - .datab(gnd), - .datac(\z80_|reg_file_|db_hi_as[0]~6_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [8]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[8] .lut_mask = 16'h5050; -defparam \z80_|address_latch_|abusz[8] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y16_N9 -dffeas \z80_|address_latch_|Q[8] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [8]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [8]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[8] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N18 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout & ((\z80_|address_latch_|Q [7] & (\z80_|address_latch_|Q [8] & !\z80_|execute_|ctl_inc_dec~11_combout -// )) # (!\z80_|address_latch_|Q [7] & (!\z80_|address_latch_|Q [8] & \z80_|execute_|ctl_inc_dec~11_combout )))) - - .dataa(\z80_|address_latch_|Q [7]), - .datab(\z80_|address_latch_|Q [8]), - .datac(\z80_|execute_|ctl_inc_dec~11_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 .lut_mask = 16'h1800; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N20 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout = \z80_|address_latch_|Q [9] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|address_latch_|Q [9]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out .lut_mask = 16'h0FF0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N12 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~3 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[1]~3_combout = ((\z80_|reg_file_|db_hi_as[1]~1_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_hi_as[1]~1_combout ), - .datab(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[1]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[1]~3 .lut_mask = 16'hBB3B; -defparam \z80_|reg_file_|db_hi_as[1]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N24 -cycloneive_lcell_comb \z80_|address_latch_|abusz[9] ( -// Equation(s): -// \z80_|address_latch_|abusz [9] = (\z80_|reg_file_|db_hi_as[1]~3_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(gnd), - .datab(\z80_|reg_file_|db_hi_as[1]~3_combout ), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [9]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[9] .lut_mask = 16'h0C0C; -defparam \z80_|address_latch_|abusz[9] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N4 -cycloneive_lcell_comb \z80_|address_latch_|Q[9]~feeder ( -// Equation(s): -// \z80_|address_latch_|Q[9]~feeder_combout = \z80_|address_latch_|abusz [9] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [9]), - .cin(gnd), - .combout(\z80_|address_latch_|Q[9]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|Q[9]~feeder .lut_mask = 16'hFF00; -defparam \z80_|address_latch_|Q[9]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N5 -dffeas \z80_|address_latch_|Q[9] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|Q[9]~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [9]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[9] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[9] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N30 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout = \z80_|address_latch_|Q [10] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout & (\z80_|address_latch_|Q [9] $ -// (\z80_|execute_|ctl_inc_dec~11_combout ))))) - - .dataa(\z80_|address_latch_|Q [10]), - .datab(\z80_|address_latch_|Q [9]), - .datac(\z80_|execute_|ctl_inc_dec~11_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out .lut_mask = 16'h96AA; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N7 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y14_N13 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~32 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~32_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [2]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [2]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~32 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[2]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y11_N25 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~35 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~35_combout = (\z80_|alu_|db[2]~15_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[2]~15_combout & (!\z80_|execute_|ctl_reg_in_hi~12_combout & -// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|alu_|db[2]~15_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~35 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[2]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y12_N19 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N18 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp1[2]~39_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y12_N19 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~34 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~34_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [2]), - .datad(\z80_|reg_file_|b2v_latch_iy_hi|latch [2]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~34 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[2]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N16 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp1[2]~39_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y13_N17 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y13_N15 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~33 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~33_combout = (\z80_|reg_file_|b2v_latch_bc_hi|latch [2] & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_hi|latch [2] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc_hi|latch [2]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~33 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[2]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y15_N21 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y12_N1 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~36 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~36_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [2]), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~36 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[2]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~37 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~37_combout = (\z80_|reg_file_|gdfx_temp1[2]~35_combout & (\z80_|reg_file_|gdfx_temp1[2]~34_combout & (\z80_|reg_file_|gdfx_temp1[2]~33_combout & \z80_|reg_file_|gdfx_temp1[2]~36_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[2]~35_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[2]~34_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[2]~33_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[2]~36_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~37 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[2]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y13_N5 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y13_N31 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~31 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~31_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datab(\z80_|reg_file_|b2v_latch_de_hi|latch [2]), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~31 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[2]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y14_N23 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N22 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[2]~17 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[2]~17_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [2]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [2]), - .datad(\z80_|reg_control_|reg_sel_af~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[2]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[2]~17 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[2]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y12_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~38 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~38_combout = (\z80_|reg_file_|gdfx_temp1[2]~32_combout & (\z80_|reg_file_|gdfx_temp1[2]~37_combout & (\z80_|reg_file_|gdfx_temp1[2]~31_combout & \z80_|reg_file_|b2v_latch_af_hi|db[2]~17_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[2]~32_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[2]~37_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[2]~31_combout ), - .datad(\z80_|reg_file_|b2v_latch_af_hi|db[2]~17_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~38 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[2]~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~39 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~39_combout = ((\z80_|reg_file_|gdfx_temp1[2]~38_combout & ((\z80_|reg_file_|db_hi_as[2]~9_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[2]~38_combout ), - .datab(\z80_|reg_file_|db_hi_as[2]~9_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~39 .lut_mask = 16'h8FAF; -defparam \z80_|reg_file_|gdfx_temp1[2]~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y15_N19 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[2]~9_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N18 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~7 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[2]~7_combout = (\z80_|reg_file_|gdfx_temp1[2]~39_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) # (!\z80_|reg_file_|gdfx_temp1[2]~39_combout & -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [2]), - .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[2]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[2]~7 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_hi_as[2]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y15_N9 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[2]~9_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N2 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~8 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[2]~8_combout = (\z80_|reg_file_|db_hi_as[2]~7_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datab(\z80_|reg_file_|db_hi_as[2]~7_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|b2v_latch_pc_hi|latch [2]), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[2]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[2]~8 .lut_mask = 16'hCC44; -defparam \z80_|reg_file_|db_hi_as[2]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N8 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~9 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[2]~9_combout = ((\z80_|reg_file_|db_hi_as[2]~8_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), - .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datad(\z80_|reg_file_|db_hi_as[2]~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[2]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[2]~9 .lut_mask = 16'hDF0F; -defparam \z80_|reg_file_|db_hi_as[2]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N0 -cycloneive_lcell_comb \z80_|address_latch_|abusz[10] ( -// Equation(s): -// \z80_|address_latch_|abusz [10] = (\z80_|reg_file_|db_hi_as[2]~9_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|reg_file_|db_hi_as[2]~9_combout ), - .datad(\z80_|resets_|clrpc~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [10]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[10] .lut_mask = 16'h00F0; -defparam \z80_|address_latch_|abusz[10] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N26 -cycloneive_lcell_comb \z80_|address_latch_|Q[10]~feeder ( -// Equation(s): -// \z80_|address_latch_|Q[10]~feeder_combout = \z80_|address_latch_|abusz [10] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [10]), - .cin(gnd), - .combout(\z80_|address_latch_|Q[10]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|Q[10]~feeder .lut_mask = 16'hFF00; -defparam \z80_|address_latch_|Q[10]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N27 -dffeas \z80_|address_latch_|Q[10] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|Q[10]~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [10]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[10] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[10] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N10 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout & ((\z80_|address_latch_|Q [10] & (\z80_|address_latch_|Q [9] & -// !\z80_|execute_|ctl_inc_dec~11_combout )) # (!\z80_|address_latch_|Q [10] & (!\z80_|address_latch_|Q [9] & \z80_|execute_|ctl_inc_dec~11_combout )))) - - .dataa(\z80_|address_latch_|Q [10]), - .datab(\z80_|address_latch_|Q [9]), - .datac(\z80_|execute_|ctl_inc_dec~11_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 .lut_mask = 16'h1800; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N14 -cycloneive_lcell_comb \z80_|address_latch_|abusz[11] ( -// Equation(s): -// \z80_|address_latch_|abusz [11] = (\z80_|reg_file_|db_hi_as[3]~12_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(gnd), - .datab(\z80_|reg_file_|db_hi_as[3]~12_combout ), - .datac(gnd), - .datad(\z80_|resets_|clrpc~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [11]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[11] .lut_mask = 16'h00CC; -defparam \z80_|address_latch_|abusz[11] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N15 -dffeas \z80_|address_latch_|Q[11] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [11]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [11]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[11] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[11] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N12 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[11] ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|address [11] = \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout $ (\z80_|address_latch_|Q [11]) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), - .datab(gnd), - .datac(\z80_|address_latch_|Q [11]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[11] .lut_mask = 16'h5A5A; -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[11] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N31 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[3]~12_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y15_N31 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[3]~12_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N30 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~10 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[3]~10_combout = (\z80_|reg_file_|gdfx_temp1[3]~48_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) # (!\z80_|reg_file_|gdfx_temp1[3]~48_combout & -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [3]), - .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[3]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[3]~10 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_hi_as[3]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N0 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~11 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[3]~11_combout = (\z80_|reg_file_|db_hi_as[3]~10_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|b2v_latch_pc_hi|latch [3]), - .datab(gnd), - .datac(\z80_|reg_file_|db_hi_as[3]~10_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[3]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[3]~11 .lut_mask = 16'hA0F0; -defparam \z80_|reg_file_|db_hi_as[3]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N30 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~12 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[3]~12_combout = ((\z80_|reg_file_|db_hi_as[3]~11_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [11]) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datad(\z80_|reg_file_|db_hi_as[3]~11_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[3]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[3]~12 .lut_mask = 16'hBF0F; -defparam \z80_|reg_file_|db_hi_as[3]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~48 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~48_combout = ((\z80_|reg_file_|gdfx_temp1[3]~47_combout & ((\z80_|reg_file_|db_hi_as[3]~12_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[3]~47_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datac(\z80_|reg_file_|db_hi_as[3]~12_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~48 .lut_mask = 16'hB3BB; -defparam \z80_|reg_file_|gdfx_temp1[3]~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N16 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & ((\z80_|alu_|db_low[3]~11_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~43_combout & !\z80_|alu_|db_high[3]~2_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .datab(\z80_|alu_|db_low[3]~11_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datad(\z80_|alu_|db_high[3]~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9 .lut_mask = 16'h888A; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_low ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_low~combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ixy_d~9_combout ) # ((\z80_|execute_|ixy_d~7_combout & !\z80_|ir_|opcode [3])))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_low .lut_mask = 16'hC0E0; -defparam \z80_|execute_|ctl_alu_op1_sel_low .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N6 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[3] ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_high|Q [3] = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & (\z80_|alu_|db_high[3]~8_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .datac(\z80_|alu_|db_high[3]~8_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [3]), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[3] .lut_mask = 16'h00C0; -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[3] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y10_N7 -dffeas \z80_|alu_|op1_high[3] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [3]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_high [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_high[3] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_high[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N10 -cycloneive_lcell_comb \z80_|alu_|alu_op1[3]~3 ( -// Equation(s): -// \z80_|alu_|alu_op1[3]~3_combout = (\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [3]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [3])) - - .dataa(gnd), - .datab(\z80_|alu_|op1_high [3]), - .datac(\z80_|alu_|op1_low [3]), - .datad(\z80_|execute_|ctl_alu_op_low~combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_op1[3]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op1[3]~3 .lut_mask = 16'hF0CC; -defparam \z80_|alu_|alu_op1[3]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N16 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout = (!\z80_|alu_|alu_op2[2]~0_combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_low [2]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_high -// [2])))) - - .dataa(\z80_|alu_|op1_high [2]), - .datab(\z80_|alu_|op1_low [2]), - .datac(\z80_|alu_|alu_op2[2]~0_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h0305; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~6_combout = ((\z80_|pla_decode_|Equal8~0_combout & (\z80_|execute_|ixy_d~5_combout & \z80_|execute_|ctl_mWrite~2_combout ))) # (!\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ) - - .dataa(\z80_|pla_decode_|Equal8~0_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ), - .datad(\z80_|execute_|ctl_mWrite~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~6 .lut_mask = 16'h8F0F; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~10_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ixy_d~15_combout & ((\z80_|execute_|ctl_bus_db_oe~1_combout ) # (!\z80_|sequencer_|DFFE_M3_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~10 .lut_mask = 16'hAAFB; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~0 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~0_combout = (\z80_|pla_decode_|Equal1~5_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~5_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|pla_decode_|Equal13~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~0 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_alu_core_R~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~5_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|execute_|ctl_alu_core_R~0_combout & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T3_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datad(\z80_|execute_|ctl_alu_core_R~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~5 .lut_mask = 16'hFEF0; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~7 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~7_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ) # (((\z80_|execute_|ctl_alu_op2_sel_bus~5_combout ) # (!\z80_|execute_|ctl_reg_use_sp~1_combout )) # (!\z80_|execute_|ctl_alu_op2_sel_bus~10_combout )) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), - .datab(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), - .datac(\z80_|execute_|ctl_reg_use_sp~1_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~7 .lut_mask = 16'hFFBF; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~8_combout = ((\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ) # ((\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_alu_shift_oe~14_combout ))) # (!\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~8 .lut_mask = 16'hFF8F; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N4 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout = (\z80_|alu_|db_low[1]~17_combout & ((\z80_|execute_|ctl_alu_op2_sel_lq~combout ) # ((\z80_|alu_|db_high[1]~20_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) # -// (!\z80_|alu_|db_low[1]~17_combout & (((\z80_|alu_|db_high[1]~20_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) - - .dataa(\z80_|alu_|db_low[1]~17_combout ), - .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datac(\z80_|alu_|db_high[1]~20_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5 .lut_mask = 16'hF888; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N0 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout ) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datab(gnd), - .datac(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6 .lut_mask = 16'h5050; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N16 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|ena ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|ena~combout = (\z80_|execute_|ctl_alu_op2_sel_zero~combout ) # ((\z80_|execute_|ctl_alu_op2_sel_lq~combout ) # (\z80_|execute_|ctl_alu_op2_sel_bus~8_combout )) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|ena .lut_mask = 16'hFFFA; -defparam \z80_|alu_|b2v_op2_latch_mux_high|ena .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y10_N1 -dffeas \z80_|alu_|op2_high[1] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_high [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_high[1] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_high[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N22 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[1] ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_high|Q [1] = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & (\z80_|alu_|db_high[1]~20_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .datac(\z80_|alu_|db_high[1]~20_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [1]), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[1] .lut_mask = 16'h00C0; -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[1] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y10_N23 -dffeas \z80_|alu_|op1_high[1] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [1]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_high [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_high[1] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_high[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N28 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [1])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [1]))))) - - .dataa(\z80_|alu_|op1_low [1]), - .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datac(\z80_|execute_|ctl_alu_op_low~combout ), - .datad(\z80_|alu_|op1_high [1]), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 .lut_mask = 16'h8C80; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N20 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ) # ((\z80_|alu_|db_low[1]~17_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datab(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ), - .datac(\z80_|alu_|db_low[1]~17_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 .lut_mask = 16'h5444; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y10_N21 -dffeas \z80_|alu_|op2_low[1] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_low [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_low[1] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_low[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~6_combout = (((!\z80_|nM1_int~2_combout & !\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal63~0_combout )) # (!\z80_|pla_decode_|Equal32~0_combout ) - - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal63~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~6 .lut_mask = 16'h57FF; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~20 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~20_combout = (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|pla_decode_|Equal68~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal68~2_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~20 .lut_mask = 16'h0D0F; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~12 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~12_combout = (\z80_|execute_|ctl_state_alu~9_combout ) # ((\z80_|execute_|ctl_reg_gp_sel~36_combout ) # ((\z80_|execute_|ctl_state_alu~11_combout ) # (!\z80_|execute_|ctl_state_alu~8_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~9_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel~36_combout ), - .datac(\z80_|execute_|ctl_state_alu~11_combout ), - .datad(\z80_|execute_|ctl_state_alu~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~12 .lut_mask = 16'hFEFF; -defparam \z80_|execute_|ctl_state_alu~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~18 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~18_combout = ((!\z80_|pla_decode_|Equal3~0_combout & ((\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal21~0_combout )))) # (!\z80_|execute_|ctl_state_alu~12_combout ) - - .dataa(\z80_|execute_|ctl_state_alu~12_combout ), - .datab(\z80_|pla_decode_|Equal3~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal21~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~18 .lut_mask = 16'h7577; -defparam \z80_|execute_|ctl_alu_core_hf~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N0 -cycloneive_lcell_comb \z80_|pla_decode_|Equal61~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal61~2_combout = (\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal6~0_combout & (!\z80_|ir_|opcode [1] & \z80_|ir_|opcode [0]))) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal61~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal61~2 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal61~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~16 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~16_combout = (\z80_|pla_decode_|Equal61~2_combout & ((\z80_|sequencer_|DFFE_M2_ff~q ) # (\z80_|sequencer_|DFFE_M4_ff~q ))) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|pla_decode_|Equal61~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~16 .lut_mask = 16'hFC00; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~17 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~17_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~6_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~20_combout & (\z80_|execute_|ctl_alu_core_hf~18_combout & !\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ))) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~20_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~18_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~17 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~21 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~21_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~17_combout & (((!\z80_|execute_|ctl_mWrite~16_combout ) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|execute_|ctl_mWrite~16_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~21 .lut_mask = 16'h7F00; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~15 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~15_combout = (((\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ) # (\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout )) # (!\z80_|execute_|ctl_alu_sel_op2_neg~4_combout )) # (!\z80_|execute_|ctl_reg_out_hi~4_combout -// ) - - .dataa(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~15 .lut_mask = 16'hFFF7; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~12 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~12_combout = (\z80_|execute_|ctl_flags_alu~17_combout & (\z80_|execute_|ctl_bus_inc_oe~43_combout & (\z80_|execute_|ctl_alu_core_S~4_combout & \z80_|execute_|ctl_alu_op1_sel_bus~8_combout ))) - - .dataa(\z80_|execute_|ctl_flags_alu~17_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .datac(\z80_|execute_|ctl_alu_core_S~4_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~12 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N6 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~22 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~22_combout = (\z80_|execute_|ctl_alu_shift_oe~38_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|execute_|ctl_ir_we~11_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~11_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~22 .lut_mask = 16'hC4CC; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~20 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~20_combout = ((\z80_|ir_|opcode [5]) # ((!\z80_|pla_decode_|Equal32~0_combout & !\z80_|pla_decode_|Equal9~0_combout ))) # (!\z80_|execute_|ctl_state_alu~12_combout ) - - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|pla_decode_|Equal9~0_combout ), - .datac(\z80_|execute_|ctl_state_alu~12_combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~20 .lut_mask = 16'hFF1F; -defparam \z80_|execute_|ctl_alu_core_hf~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~4_combout = (\z80_|execute_|ctl_flags_sz_we~0_combout & (((!\z80_|execute_|ctl_ir_we~12_combout & !\z80_|execute_|ctl_ir_we~11_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_flags_sz_we~0_combout ), - .datab(\z80_|execute_|ctl_ir_we~12_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_ir_we~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~4 .lut_mask = 16'h0A2A; -defparam \z80_|execute_|ctl_flags_sz_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N2 -cycloneive_lcell_comb \z80_|pla_decode_|Equal71~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal71~2_combout = (!\z80_|ir_|opcode [3] & (!\z80_|ir_|opcode [4] & (\z80_|execute_|ctl_state_alu~12_combout & \z80_|ir_|opcode [5]))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|execute_|ctl_state_alu~12_combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal71~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal71~2 .lut_mask = 16'h1000; -defparam \z80_|pla_decode_|Equal71~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N18 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~8 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~8_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~22_combout & (\z80_|execute_|ctl_alu_core_hf~20_combout & (\z80_|execute_|ctl_flags_sz_we~4_combout & !\z80_|pla_decode_|Equal71~2_combout ))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~22_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~20_combout ), - .datac(\z80_|execute_|ctl_flags_sz_we~4_combout ), - .datad(\z80_|pla_decode_|Equal71~2_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~8 .lut_mask = 16'h0080; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~31 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~31_combout = (!\z80_|execute_|ctl_alu_op_low~9_combout & (((!\z80_|sequencer_|DFFE_M4_ff~q ) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|pla_decode_|Equal13~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~9_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_M4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~31 .lut_mask = 16'h1333; -defparam \z80_|execute_|ctl_alu_op_low~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N22 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~4 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~4_combout = (\z80_|pla_decode_|Equal21~0_combout & ((\z80_|nM1_int~2_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout )))) # (!\z80_|pla_decode_|Equal21~0_combout & (\z80_|pla_decode_|Equal3~0_combout & -// ((\z80_|nM1_int~2_combout ) # (\z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal21~0_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal3~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~4 .lut_mask = 16'hFCA8; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout = (\z80_|pla_decode_|Equal13~1_combout & (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal6~0_combout & !\z80_|ir_|opcode [5]))) - - .dataa(\z80_|pla_decode_|Equal13~1_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N16 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~5 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~5_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout & \z80_|pla_decode_|Equal63~0_combout -// ))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), - .datac(\z80_|pla_decode_|Equal63~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~5 .lut_mask = 16'hFFEC; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N26 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~6 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~6_combout = (\z80_|execute_|ctl_alu_op_low~31_combout & (\z80_|execute_|ctl_flags_pf_we~10_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~7_combout & !\z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~31_combout ), - .datab(\z80_|execute_|ctl_flags_pf_we~10_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~6 .lut_mask = 16'h0080; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal72~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal72~2_combout = (\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [3] & \z80_|execute_|ctl_state_alu~12_combout ))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|execute_|ctl_state_alu~12_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal72~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal72~2 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal72~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y9_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal73~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal73~2_combout = (\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [3] & (!\z80_|ir_|opcode [4] & \z80_|execute_|ctl_state_alu~12_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|execute_|ctl_state_alu~12_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal73~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal73~2 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal73~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~0 ( -// Equation(s): -// \z80_|execute_|ctl_flags_nf_we~0_combout = (\z80_|pla_decode_|Equal61~2_combout & (!\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|execute_|ctl_mRead~36_combout )))) # (!\z80_|pla_decode_|Equal61~2_combout & -// (((!\z80_|execute_|ixy_d~5_combout )) # (!\z80_|execute_|ctl_mRead~36_combout ))) - - .dataa(\z80_|pla_decode_|Equal61~2_combout ), - .datab(\z80_|execute_|ctl_mRead~36_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_nf_we~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_nf_we~0 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_flags_nf_we~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~1 ( -// Equation(s): -// \z80_|execute_|ctl_flags_nf_we~1_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout & (!\z80_|pla_decode_|Equal72~2_combout & (!\z80_|pla_decode_|Equal73~2_combout & \z80_|execute_|ctl_flags_nf_we~0_combout ))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ), - .datab(\z80_|pla_decode_|Equal72~2_combout ), - .datac(\z80_|pla_decode_|Equal73~2_combout ), - .datad(\z80_|execute_|ctl_flags_nf_we~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_nf_we~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_nf_we~1 .lut_mask = 16'h0200; -defparam \z80_|execute_|ctl_flags_nf_we~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_nf_we~2_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal10~0_combout ) # ((\z80_|pla_decode_|Equal11~0_combout ) # (\z80_|pla_decode_|Equal61~2_combout )))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal61~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_nf_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_nf_we~2 .lut_mask = 16'hF0E0; -defparam \z80_|execute_|ctl_flags_nf_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_nf_we~3_combout = ((\z80_|execute_|ctl_flags_nf_we~2_combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~21_combout )) # (!\z80_|execute_|ctl_flags_nf_we~1_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_flags_nf_we~1_combout ), - .datac(\z80_|execute_|ctl_flags_nf_we~2_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~21_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_nf_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_nf_we~3 .lut_mask = 16'hF3FF; -defparam \z80_|execute_|ctl_flags_nf_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~5_combout = (\z80_|sequencer_|DFFE_T4_ff~q ) # ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~5 .lut_mask = 16'hFAFF; -defparam \z80_|execute_|ctl_flags_sz_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~6_combout = (\z80_|pla_decode_|Equal48~0_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # ((\z80_|execute_|ctl_flags_sz_we~5_combout & \z80_|execute_|ctl_alu_core_R~0_combout )))) # -// (!\z80_|pla_decode_|Equal48~0_combout & (\z80_|execute_|ctl_flags_sz_we~5_combout & ((\z80_|execute_|ctl_alu_core_R~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal48~0_combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~5_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_alu_core_R~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~6 .lut_mask = 16'hECA0; -defparam \z80_|execute_|ctl_flags_sz_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_nf_we~4_combout = (((\z80_|execute_|ctl_flags_nf_we~3_combout ) # (\z80_|execute_|ctl_flags_sz_we~6_combout )) # (!\z80_|execute_|ctl_flags_xy_we~12_combout )) # (!\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~12_combout ), - .datac(\z80_|execute_|ctl_flags_nf_we~3_combout ), - .datad(\z80_|execute_|ctl_flags_sz_we~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_nf_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_nf_we~4 .lut_mask = 16'hFFF7; -defparam \z80_|execute_|ctl_flags_nf_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y9_N12 -cycloneive_lcell_comb \z80_|execute_|setM1~15 ( -// Equation(s): -// \z80_|execute_|setM1~15_combout = (!\z80_|execute_|ctl_alu_shift_oe~15_combout & (\z80_|execute_|ctl_sw_2u~1_combout & \z80_|execute_|ctl_state_alu~8_combout )) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_sw_2u~1_combout ), - .datad(\z80_|execute_|ctl_state_alu~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~15 .lut_mask = 16'h5000; -defparam \z80_|execute_|setM1~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|setM1~16 ( -// Equation(s): -// \z80_|execute_|setM1~16_combout = (\z80_|execute_|setM1~15_combout & (!\z80_|execute_|ctl_alu_op1_sel_zero~4_combout & (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & \z80_|execute_|ctl_alu_op_low~31_combout ))) - - .dataa(\z80_|execute_|setM1~15_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datad(\z80_|execute_|ctl_alu_op_low~31_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~16 .lut_mask = 16'h0200; -defparam \z80_|execute_|setM1~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~6_combout = (!\z80_|execute_|ctl_reg_gp_sel~36_combout & \z80_|execute_|setM1~16_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_sel~36_combout ), - .datad(\z80_|execute_|setM1~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~6 .lut_mask = 16'h0F00; -defparam \z80_|execute_|ctl_flags_xy_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~7_combout = (\z80_|execute_|ctl_flags_pf_we~2_combout & (\z80_|execute_|ctl_flags_xy_we~17_combout & (\z80_|execute_|ctl_flags_xy_we~6_combout & \z80_|execute_|ctl_alu_oe~5_combout ))) - - .dataa(\z80_|execute_|ctl_flags_pf_we~2_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~17_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~6_combout ), - .datad(\z80_|execute_|ctl_alu_oe~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~7 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_xy_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~2_combout = (\z80_|execute_|ctl_flags_sz_we~1_combout & (\z80_|execute_|ctl_flags_xy_we~7_combout & \z80_|execute_|ctl_alu_op2_sel_bus~10_combout )) - - .dataa(\z80_|execute_|ctl_flags_sz_we~1_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~7_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~2 .lut_mask = 16'h8800; -defparam \z80_|execute_|ctl_flags_sz_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla12M1T1_12~0 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout = (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal11~1_combout & (!\z80_|ir_|opcode [2] & \z80_|execute_|ctl_mWrite~2_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal11~1_combout ), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|execute_|ctl_mWrite~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel_pla12M1T1_12~0 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_pf_sel_pla12M1T1_12~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~1 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~1_combout = (\z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ) # ((\z80_|execute_|ctl_alu_core_R~0_combout & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|execute_|ctl_alu_core_R~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~1 .lut_mask = 16'hFBAA; -defparam \z80_|execute_|ctl_alu_core_R~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~7_combout = (\z80_|execute_|ctl_alu_core_R~1_combout ) # (((\z80_|execute_|ixy_d~7_combout & \z80_|pla_decode_|Equal56~0_combout )) # (!\z80_|execute_|ctl_flags_alu~18_combout )) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~1_combout ), - .datac(\z80_|pla_decode_|Equal56~0_combout ), - .datad(\z80_|execute_|ctl_flags_alu~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~7 .lut_mask = 16'hECFF; -defparam \z80_|execute_|ctl_flags_alu~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N24 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~8 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~8_combout = (\z80_|reg_control_|reg_sys_we_lo~5_combout & (((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|pla_decode_|Equal56~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal56~0_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|reg_control_|reg_sys_we_lo~5_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~8 .lut_mask = 16'h7F00; -defparam \z80_|reg_control_|reg_sys_we_lo~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~8_combout = ((\z80_|execute_|ctl_flags_alu~7_combout ) # ((!\z80_|reg_control_|reg_sys_we_lo~8_combout ) # (!\z80_|execute_|ctl_flags_alu~16_combout ))) # (!\z80_|execute_|ctl_flags_alu~6_combout ) - - .dataa(\z80_|execute_|ctl_flags_alu~6_combout ), - .datab(\z80_|execute_|ctl_flags_alu~7_combout ), - .datac(\z80_|execute_|ctl_flags_alu~16_combout ), - .datad(\z80_|reg_control_|reg_sys_we_lo~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~8 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_flags_alu~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~16 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~16_combout = (\z80_|execute_|ctl_alu_op_low~10_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|pla_decode_|Equal20~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal20~0_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|execute_|ctl_alu_op_low~10_combout ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~16 .lut_mask = 16'hD0F0; -defparam \z80_|execute_|ctl_flags_xy_we~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~12 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~12_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~5_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout & ((!\z80_|execute_|ctl_mRead~36_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|ctl_mRead~36_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~12 .lut_mask = 16'h0070; -defparam \z80_|execute_|ctl_flags_alu~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~13 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~13_combout = (\z80_|execute_|ctl_flags_sz_we~4_combout & (\z80_|execute_|ctl_flags_xy_we~16_combout & (\z80_|execute_|ctl_sw_2d~4_combout & \z80_|execute_|ctl_flags_alu~12_combout ))) - - .dataa(\z80_|execute_|ctl_flags_sz_we~4_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~16_combout ), - .datac(\z80_|execute_|ctl_sw_2d~4_combout ), - .datad(\z80_|execute_|ctl_flags_alu~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~13 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_alu~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~14 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~14_combout = (\z80_|execute_|ctl_reg_use_sp~1_combout & (\z80_|execute_|ctl_alu_op_low~15_combout & (\z80_|execute_|ctl_sw_4u~1_combout & \z80_|execute_|ctl_flags_alu~13_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~1_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~15_combout ), - .datac(\z80_|execute_|ctl_sw_4u~1_combout ), - .datad(\z80_|execute_|ctl_flags_alu~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~14 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_alu~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~15 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~15_combout = ((\z80_|execute_|ctl_flags_alu~8_combout ) # ((!\z80_|execute_|ctl_flags_alu~11_combout ) # (!\z80_|execute_|ctl_flags_alu~14_combout ))) # (!\z80_|execute_|ctl_flags_sz_we~2_combout ) - - .dataa(\z80_|execute_|ctl_flags_sz_we~2_combout ), - .datab(\z80_|execute_|ctl_flags_alu~8_combout ), - .datac(\z80_|execute_|ctl_flags_alu~14_combout ), - .datad(\z80_|execute_|ctl_flags_alu~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~15 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_flags_alu~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [3] & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N12 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout = (\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ) # ((\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal10~0_combout ) # (\z80_|pla_decode_|Equal61~2_combout )))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal61~2_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 .lut_mask = 16'hFCEC; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~19 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~19_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal3~1_combout ))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal3~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~19 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N30 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ) # ((\z80_|execute_|ctl_alu_sel_op2_neg~19_combout ) # ((\z80_|alu_control_|db[1]~26_combout & \z80_|execute_|ctl_flags_bus~combout ))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~19_combout ), - .datac(\z80_|alu_control_|db[1]~26_combout ), - .datad(\z80_|execute_|ctl_flags_bus~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 .lut_mask = 16'hFEEE; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N20 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout = ((\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ) # ((\z80_|execute_|ctl_flags_alu~15_combout & \z80_|alu_|db_high[3]~8_combout ))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ) - - .dataa(\z80_|execute_|ctl_flags_alu~15_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), - .datac(\z80_|alu_|db_high[3]~8_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 .lut_mask = 16'hFFB3; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N20 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~7 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~7_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout & (((!\z80_|pla_decode_|Equal32~0_combout & !\z80_|pla_decode_|Equal21~0_combout )) # (!\z80_|pla_decode_|Equal62~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|pla_decode_|Equal62~2_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ), - .datad(\z80_|pla_decode_|Equal21~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~7 .lut_mask = 16'h3070; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N6 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~9 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~9_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~7_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~11_combout & (!\z80_|execute_|ctl_alu_core_R~1_combout & \z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~7_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~11_combout ), - .datac(\z80_|execute_|ctl_alu_core_R~1_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~9 .lut_mask = 16'h0800; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N26 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~10 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~10_combout = (\z80_|execute_|ctl_flags_nf_we~4_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout & ((\z80_|alu_flags_|DFFE_inst_latch_nf~9_combout )))) # (!\z80_|execute_|ctl_flags_nf_we~4_combout & -// (((\z80_|alu_flags_|DFFE_inst_latch_nf~q )))) - - .dataa(\z80_|execute_|ctl_flags_nf_we~4_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~9_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~10 .lut_mask = 16'hD850; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y9_N27 -dffeas \z80_|alu_flags_|DFFE_inst_latch_nf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|DFFE_inst_latch_nf~10_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~7 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~7_combout = ((\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # (\z80_|execute_|ctl_flags_cf2_sel_daa~combout )))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~7 .lut_mask = 16'hE0FF; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [3] & \z80_|execute_|ixy_d~7_combout ))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~10_combout = (\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ) # ((\z80_|pla_decode_|Equal61~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # (\z80_|nM1_int~2_combout )))) - - .dataa(\z80_|pla_decode_|Equal61~2_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~10 .lut_mask = 16'hFFA8; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~8_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (!\z80_|sequencer_|DFFE_T3_ff~q & ((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|sequencer_|DFFE_M3_ff~q )))) # (!\z80_|sequencer_|DFFE_M2_ff~q & -// (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|sequencer_|DFFE_M3_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~8 .lut_mask = 16'h7707; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~9_combout = ((\z80_|pla_decode_|Equal10~0_combout & ((\z80_|nM1_int~2_combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~8_combout )))) # (!\z80_|execute_|ctl_alu_op_low~33_combout ) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~33_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~9 .lut_mask = 16'hB3BB; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~11_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ) # ((\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ) # ((\z80_|execute_|ctl_alu_op_low~8_combout & \z80_|execute_|ctl_alu_op_low~12_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~12_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~11 .lut_mask = 16'hFFEC; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~14_combout = (((\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ) # (\z80_|execute_|ctl_alu_sel_op2_neg~11_combout )) # (!\z80_|execute_|ctl_alu_sel_op2_neg~12_combout )) # (!\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~14 .lut_mask = 16'hFFF7; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~18 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~18_combout = ((\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ) # ((\z80_|execute_|ctl_alu_sel_op2_neg~15_combout & \z80_|alu_flags_|DFFE_inst_latch_sf~q ))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~21_combout ) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~21_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~18 .lut_mask = 16'hFDF5; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_high ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_high~combout = ((\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|pla_decode_|Equal13~2_combout & \z80_|sequencer_|DFFE_M3_ff~q ))) # (!\z80_|execute_|ctl_alu_res_oe~2_combout ) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|pla_decode_|Equal13~2_combout ), - .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_high .lut_mask = 16'h8F0F; -defparam \z80_|execute_|ctl_alu_sel_op2_high .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N6 -cycloneive_lcell_comb \z80_|alu_|alu_op2[1]~1 ( -// Equation(s): -// \z80_|alu_|alu_op2[1]~1_combout = \z80_|execute_|ctl_alu_sel_op2_neg~18_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_high [1])) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_low [1]))))) - - .dataa(\z80_|alu_|op2_high [1]), - .datab(\z80_|alu_|op2_low [1]), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_op2[1]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op2[1]~1 .lut_mask = 16'h5A3C; -defparam \z80_|alu_|alu_op2[1]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N30 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout = (!\z80_|alu_|alu_op2[1]~1_combout & ((\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_low [1])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_high -// [1]))))) - - .dataa(\z80_|alu_|alu_op2[1]~1_combout ), - .datab(\z80_|alu_|op1_low [1]), - .datac(\z80_|execute_|ctl_alu_op_low~combout ), - .datad(\z80_|alu_|op1_high [1]), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'h1015; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~9_combout = (((\z80_|pla_decode_|Equal71~2_combout ) # (!\z80_|execute_|ctl_alu_core_S~11_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~10_combout )) # (!\z80_|execute_|ctl_alu_core_S~5_combout ) - - .dataa(\z80_|execute_|ctl_alu_core_S~5_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), - .datac(\z80_|execute_|ctl_alu_core_S~11_combout ), - .datad(\z80_|pla_decode_|Equal71~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~9 .lut_mask = 16'hFF7F; -defparam \z80_|execute_|ctl_alu_core_S~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N22 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout = (\z80_|alu_|db_high[0]~26_combout & ((\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ) # ((\z80_|alu_|db_low[0]~23_combout & \z80_|execute_|ctl_alu_op2_sel_lq~combout )))) # -// (!\z80_|alu_|db_high[0]~26_combout & (\z80_|alu_|db_low[0]~23_combout & (\z80_|execute_|ctl_alu_op2_sel_lq~combout ))) - - .dataa(\z80_|alu_|db_high[0]~26_combout ), - .datab(\z80_|alu_|db_low[0]~23_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7 .lut_mask = 16'hEAC0; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N6 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8_combout = (\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout & !\z80_|execute_|ctl_alu_op2_sel_zero~combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8 .lut_mask = 16'h00F0; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y10_N7 -dffeas \z80_|alu_|op2_high[0] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_high [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_high[0] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_high[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N2 -cycloneive_lcell_comb \z80_|alu_|alu_op2[0]~3 ( -// Equation(s): -// \z80_|alu_|alu_op2[0]~3_combout = \z80_|execute_|ctl_alu_sel_op2_neg~18_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [0]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [0])))) - - .dataa(\z80_|alu_|op2_low [0]), - .datab(\z80_|alu_|op2_high [0]), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_op2[0]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op2[0]~3 .lut_mask = 16'h3C5A; -defparam \z80_|alu_|alu_op2[0]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N0 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~12 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~12_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout & ((\z80_|ir_|opcode [3]) # ((!\z80_|ir_|opcode [4]) # (!\z80_|pla_decode_|Equal62~2_combout )))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal62~2_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~12 .lut_mask = 16'hB0F0; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~8_combout = (!\z80_|execute_|ctl_alu_core_R~1_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~6_combout & \z80_|execute_|ctl_alu_core_S~7_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_R~1_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~8 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_alu_core_S~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N2 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout = (((!\z80_|execute_|ctl_alu_core_S~9_combout & !\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout )) # (!\z80_|execute_|ctl_alu_core_S~8_combout )) # -// (!\z80_|execute_|ctl_alu_core_R~4_combout ) - - .dataa(\z80_|execute_|ctl_alu_core_S~9_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~4_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 .lut_mask = 16'h37FF; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~21 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~21_combout = (\z80_|execute_|ctl_alu_core_hf~20_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # ((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|execute_|ixy_d~15_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|execute_|ixy_d~15_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~20_combout ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~21 .lut_mask = 16'hB0F0; -defparam \z80_|execute_|ctl_alu_core_hf~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~22 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~22_combout = (((\z80_|execute_|ixy_d~8_combout & \z80_|pla_decode_|Equal21~1_combout )) # (!\z80_|execute_|ctl_alu_core_hf~21_combout )) # (!\z80_|execute_|ctl_alu_core_hf~18_combout ) - - .dataa(\z80_|execute_|ctl_alu_core_hf~18_combout ), - .datab(\z80_|execute_|ixy_d~8_combout ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~21_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~22 .lut_mask = 16'hD5FF; -defparam \z80_|execute_|ctl_alu_core_hf~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~19 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~19_combout = (\z80_|pla_decode_|Equal21~1_combout & ((\z80_|execute_|ctl_mRead~11_combout ) # ((\z80_|execute_|ixy_d~6_combout & !\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~11_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~19 .lut_mask = 16'hA0E0; -defparam \z80_|execute_|ctl_alu_core_hf~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~27 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~27_combout = (\z80_|execute_|ctl_alu_op_low~19_combout ) # (((\z80_|execute_|ctl_alu_op_low~22_combout ) # (!\z80_|execute_|ctl_alu_op_low~33_combout )) # (!\z80_|execute_|ctl_alu_op_low~17_combout )) - - .dataa(\z80_|execute_|ctl_alu_op_low~19_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~22_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~33_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~27 .lut_mask = 16'hFBFF; -defparam \z80_|execute_|ctl_alu_op_low~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~29 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~29_combout = (\z80_|execute_|ctl_alu_op_low~23_combout ) # ((\z80_|execute_|ctl_alu_op_low~34_combout ) # (\z80_|execute_|ctl_alu_op_low~27_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op_low~23_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~34_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~29 .lut_mask = 16'hFFFC; -defparam \z80_|execute_|ctl_alu_op_low~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~23 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~23_combout = (\z80_|execute_|ctl_alu_core_hf~22_combout & (((\z80_|execute_|ctl_alu_core_hf~19_combout & !\z80_|execute_|ctl_alu_op_low~29_combout )) # (!\z80_|execute_|ctl_alu_op_low~28_combout ))) # -// (!\z80_|execute_|ctl_alu_core_hf~22_combout & (\z80_|execute_|ctl_alu_core_hf~19_combout & (!\z80_|execute_|ctl_alu_op_low~29_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~22_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~19_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~29_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~28_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~23 .lut_mask = 16'h0CAE; -defparam \z80_|execute_|ctl_alu_core_hf~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~37 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~37_combout = (\z80_|pla_decode_|Equal39~0_combout ) # ((!\z80_|execute_|ixy_d~5_combout & \z80_|pla_decode_|Equal40~1_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|pla_decode_|Equal40~1_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~37 .lut_mask = 16'hFF30; -defparam \z80_|execute_|ctl_alu_core_hf~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~38 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~38_combout = (\z80_|execute_|ctl_alu_core_hf~37_combout & ((\z80_|execute_|ixy_d~6_combout ) # ((\z80_|execute_|ixy_d~8_combout & !\z80_|execute_|ixy_d~9_combout )))) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|execute_|ixy_d~8_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~37_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~38 .lut_mask = 16'hAE00; -defparam \z80_|execute_|ctl_alu_core_hf~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~24 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~24_combout = (\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (((!\z80_|pla_decode_|Equal32~0_combout ) # (!\z80_|pla_decode_|Equal63~0_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|pla_decode_|Equal63~0_combout ), - .datac(\z80_|pla_decode_|Equal32~0_combout ), - .datad(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~24 .lut_mask = 16'h7F00; -defparam \z80_|execute_|ctl_alu_core_hf~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~25 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~25_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # ((\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ) # ((!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & \z80_|execute_|ctl_alu_core_hf~24_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .datab(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~25 .lut_mask = 16'hEFEE; -defparam \z80_|execute_|ctl_alu_core_hf~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~26 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~26_combout = (\z80_|execute_|ctl_mRead~36_combout & ((\z80_|execute_|ctl_mRead~11_combout ) # ((\z80_|execute_|ixy_d~6_combout & !\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~36_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|execute_|ctl_mRead~11_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~26 .lut_mask = 16'hA0A8; -defparam \z80_|execute_|ctl_alu_core_hf~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~27 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~27_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ) # ((\z80_|execute_|ctl_alu_core_hf~26_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|execute_|ctl_mRead~36_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~36_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~26_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~27 .lut_mask = 16'hDFCC; -defparam \z80_|execute_|ctl_alu_core_hf~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~28 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~28_combout = (\z80_|execute_|ctl_alu_core_hf~25_combout & (((\z80_|execute_|ctl_alu_core_hf~27_combout & !\z80_|execute_|ctl_alu_op_low~27_combout )) # (!\z80_|execute_|ctl_alu_op_low~20_combout ))) # -// (!\z80_|execute_|ctl_alu_core_hf~25_combout & (((\z80_|execute_|ctl_alu_core_hf~27_combout & !\z80_|execute_|ctl_alu_op_low~27_combout )))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~25_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~20_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~27_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~28 .lut_mask = 16'h22F2; -defparam \z80_|execute_|ctl_alu_core_hf~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~30 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~30_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ) # (((\z80_|execute_|ctl_alu_op_low~14_combout ) # (!\z80_|execute_|ctl_alu_op2_sel_bus~9_combout )) # (!\z80_|execute_|ctl_state_alu~13_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), - .datab(\z80_|execute_|ctl_state_alu~13_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~30 .lut_mask = 16'hFBFF; -defparam \z80_|execute_|ctl_alu_op_low~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~34 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~34_combout = (\z80_|execute_|ctl_mRead~6_combout & ((\z80_|execute_|ctl_mWrite~3_combout ) # ((\z80_|execute_|ctl_mWrite~7_combout & !\z80_|execute_|ctl_state_alu~6_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~3_combout ), - .datab(\z80_|execute_|ctl_mWrite~7_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_mRead~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~34 .lut_mask = 16'hAE00; -defparam \z80_|execute_|ctl_alu_core_hf~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~32 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~32_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & (((\z80_|execute_|ctl_alu_op_low~11_combout )))) # (!\z80_|execute_|ctl_alu_op_low~8_combout & (\z80_|execute_|ixy_d~7_combout & -// ((!\z80_|execute_|ctl_mWrite~3_combout )))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~11_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datad(\z80_|execute_|ctl_mWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~32 .lut_mask = 16'hC0CA; -defparam \z80_|execute_|ctl_alu_core_hf~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~43 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~43_combout = (\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|execute_|ctl_mRead~6_combout & (\z80_|execute_|ctl_state_alu~6_combout ))) # (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M2_ff~q ) # -// ((\z80_|execute_|ctl_mRead~6_combout & \z80_|execute_|ctl_state_alu~6_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~43 .lut_mask = 16'hD5C0; -defparam \z80_|execute_|ctl_alu_core_hf~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~33 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~33_combout = (!\z80_|execute_|ctl_alu_core_hf~43_combout & ((\z80_|execute_|ctl_alu_core_hf~32_combout & ((\z80_|pla_decode_|Equal56~0_combout ) # (\z80_|execute_|ctl_alu_op_low~8_combout ))) # -// (!\z80_|execute_|ctl_alu_core_hf~32_combout & (\z80_|pla_decode_|Equal56~0_combout & \z80_|execute_|ctl_alu_op_low~8_combout )))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~32_combout ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~43_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~33 .lut_mask = 16'h00E8; -defparam \z80_|execute_|ctl_alu_core_hf~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~42 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~42_combout = (!\z80_|execute_|ctl_alu_shift_oe~15_combout & (((!\z80_|sequencer_|DFFE_M2_ff~q ) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|execute_|ctl_mRead~6_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~42 .lut_mask = 16'h1555; -defparam \z80_|execute_|ctl_alu_core_hf~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~35 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~35_combout = (\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # ((\z80_|execute_|ctl_alu_core_hf~42_combout & ((\z80_|execute_|ctl_alu_core_hf~34_combout ) # (\z80_|execute_|ctl_alu_core_hf~33_combout )))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~34_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~33_combout ), - .datac(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~42_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~35 .lut_mask = 16'hFEF0; -defparam \z80_|execute_|ctl_alu_core_hf~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~41 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~41_combout = (!\z80_|execute_|ctl_state_alu~4_combout & (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|pla_decode_|Equal10~0_combout & !\z80_|sequencer_|DFFE_T1_ff~q ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~41 .lut_mask = 16'h0040; -defparam \z80_|execute_|ctl_alu_core_hf~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~30 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~30_combout = (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|nM1_int~2_combout ) # ((\z80_|pla_decode_|Equal11~0_combout & !\z80_|execute_|ctl_alu_sel_op2_neg~8_combout )))) # (!\z80_|pla_decode_|Equal10~0_combout & -// (\z80_|pla_decode_|Equal11~0_combout & ((!\z80_|execute_|ctl_alu_sel_op2_neg~8_combout )))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~30 .lut_mask = 16'hA0EC; -defparam \z80_|execute_|ctl_alu_core_hf~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~10 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~10_combout = (!\z80_|ir_|opcode [2] & (\z80_|execute_|ctl_state_alu~4_combout & (\z80_|pla_decode_|Equal11~1_combout & \z80_|execute_|ctl_mWrite~2_combout ))) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|pla_decode_|Equal11~1_combout ), - .datad(\z80_|execute_|ctl_mWrite~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~10 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_mWrite~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~31 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~31_combout = (!\z80_|execute_|ctl_alu_op_low~14_combout & (!\z80_|execute_|ctl_mWrite~10_combout & ((\z80_|execute_|ctl_alu_core_hf~41_combout ) # (\z80_|execute_|ctl_alu_core_hf~30_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~41_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~30_combout ), - .datad(\z80_|execute_|ctl_mWrite~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~31 .lut_mask = 16'h0054; -defparam \z80_|execute_|ctl_alu_core_hf~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~44 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~44_combout = (\z80_|execute_|ctl_alu_op_low~12_combout & (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~44 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_core_hf~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~29 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~29_combout = (!\z80_|execute_|ctl_alu_op_low~19_combout & ((\z80_|execute_|ctl_alu_core_hf~44_combout ) # ((\z80_|execute_|ctl_alu_op_low~11_combout & \z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~44_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~11_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~19_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~29 .lut_mask = 16'h0E0A; -defparam \z80_|execute_|ctl_alu_core_hf~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~36 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~36_combout = (\z80_|execute_|ctl_alu_core_hf~31_combout ) # ((\z80_|execute_|ctl_alu_core_hf~29_combout ) # ((!\z80_|execute_|ctl_alu_op_low~30_combout & \z80_|execute_|ctl_alu_core_hf~35_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~30_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~35_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~31_combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~29_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~36 .lut_mask = 16'hFFF4; -defparam \z80_|execute_|ctl_alu_core_hf~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~39 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~39_combout = (\z80_|execute_|ctl_alu_core_hf~28_combout ) # ((\z80_|execute_|ctl_alu_core_hf~36_combout ) # ((\z80_|execute_|ctl_alu_core_hf~38_combout & !\z80_|execute_|ctl_alu_op_low~24_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~38_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~28_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~36_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~39 .lut_mask = 16'hFCFE; -defparam \z80_|execute_|ctl_alu_core_hf~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~40 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~40_combout = (\z80_|execute_|ctl_alu_core_hf~23_combout ) # ((\z80_|execute_|ctl_alu_core_hf~39_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout & !\z80_|execute_|ctl_alu_op_low~combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~23_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), - .datac(\z80_|execute_|ctl_alu_op_low~combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~39_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~40 .lut_mask = 16'hFFAE; -defparam \z80_|execute_|ctl_alu_core_hf~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_we~2_combout = (\z80_|execute_|ctl_flags_xy_we~11_combout & (\z80_|execute_|ctl_flags_hf_we~5_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_state_alu~14_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~14_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~11_combout ), - .datad(\z80_|execute_|ctl_flags_hf_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_we~2 .lut_mask = 16'h7000; -defparam \z80_|execute_|ctl_flags_hf_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~2 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~2_combout = (\z80_|nM1_int~2_combout & (\z80_|execute_|ctl_mWrite~2_combout & ((\z80_|pla_decode_|Equal55~0_combout ) # (\z80_|pla_decode_|Equal8~0_combout )))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~2_combout ), - .datad(\z80_|pla_decode_|Equal8~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~2 .lut_mask = 16'hA080; -defparam \z80_|execute_|ctl_alu_core_R~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~combout = (\z80_|execute_|ctl_alu_core_R~2_combout ) # (((\z80_|pla_decode_|Equal73~2_combout ) # (!\z80_|execute_|ctl_alu_core_S~8_combout )) # (!\z80_|execute_|ctl_alu_core_R~4_combout )) - - .dataa(\z80_|execute_|ctl_alu_core_R~2_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~4_combout ), - .datac(\z80_|pla_decode_|Equal73~2_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R .lut_mask = 16'hFBFF; -defparam \z80_|execute_|ctl_alu_core_R .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N2 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|alu_|db_low[3]~11_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~43_combout & !\z80_|alu_|db_high[3]~2_combout )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datab(\z80_|alu_|db_low[3]~11_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datad(\z80_|alu_|db_high[3]~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9 .lut_mask = 16'hC0D0; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N8 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~8_combout & \z80_|alu_|db_high[3]~8_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datab(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .datac(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9_combout ), - .datad(\z80_|alu_|db_high[3]~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2 .lut_mask = 16'h5450; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y10_N9 -dffeas \z80_|alu_|op2_high[3] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_high [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_high[3] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_high[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N2 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [3]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [3])))) - - .dataa(\z80_|alu_|op1_high [3]), - .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datac(\z80_|execute_|ctl_alu_op_low~combout ), - .datad(\z80_|alu_|op1_low [3]), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2 .lut_mask = 16'hC808; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N18 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2_combout ) # ((\z80_|alu_|db_low[3]~25_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datab(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2_combout ), - .datac(\z80_|alu_|db_low[3]~25_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3 .lut_mask = 16'h5444; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y10_N19 -dffeas \z80_|alu_|op2_low[3] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_low [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_low[3] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_low[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N26 -cycloneive_lcell_comb \z80_|alu_|alu_op2[3]~2 ( -// Equation(s): -// \z80_|alu_|alu_op2[3]~2_combout = \z80_|execute_|ctl_alu_sel_op2_neg~18_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_high [3])) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_low [3]))))) - - .dataa(\z80_|alu_|op2_high [3]), - .datab(\z80_|alu_|op2_low [3]), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_op2[3]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op2[3]~2 .lut_mask = 16'h5A3C; -defparam \z80_|alu_|alu_op2[3]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N4 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout = (\z80_|execute_|ctl_alu_core_S~9_combout ) # (((\z80_|alu_|alu_op1[3]~3_combout & \z80_|alu_|alu_op2[3]~2_combout )) # (!\z80_|execute_|ctl_alu_core_S~8_combout )) - - .dataa(\z80_|alu_|alu_op1[3]~3_combout ), - .datab(\z80_|execute_|ctl_alu_core_S~9_combout ), - .datac(\z80_|alu_|alu_op2[3]~2_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hECFF; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N16 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout = (!\z80_|alu_|alu_op2[3]~2_combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_low [3]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_high -// [3])))) - - .dataa(\z80_|alu_|alu_op2[3]~2_combout ), - .datab(\z80_|alu_|op1_high [3]), - .datac(\z80_|alu_|op1_low [3]), - .datad(\z80_|execute_|ctl_alu_op_low~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h0511; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N30 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ) # -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_core_R~combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0 .lut_mask = 16'hAFAE; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N2 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_hf~0 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_hf~0_combout = (\z80_|execute_|ctl_flags_bus~combout & ((\z80_|alu_control_|db[4]~32_combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & \z80_|execute_|ctl_flags_alu~15_combout )))) # -// (!\z80_|execute_|ctl_flags_bus~combout & (((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & \z80_|execute_|ctl_flags_alu~15_combout )))) - - .dataa(\z80_|execute_|ctl_flags_bus~combout ), - .datab(\z80_|alu_control_|db[4]~32_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), - .datad(\z80_|execute_|ctl_flags_alu~15_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_hf~0 .lut_mask = 16'h8F88; -defparam \z80_|alu_flags_|DFFE_inst_latch_hf~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_we~3_combout = (\z80_|pla_decode_|Equal11~0_combout & ((\z80_|nM1_int~2_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) # (!\z80_|pla_decode_|Equal11~0_combout & (((\z80_|pla_decode_|Equal10~0_combout & -// \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_we~3 .lut_mask = 16'hFC88; -defparam \z80_|execute_|ctl_flags_hf_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_we~4_combout = ((\z80_|execute_|ctl_flags_sz_we~6_combout ) # ((\z80_|execute_|ctl_flags_hf_we~3_combout ) # (!\z80_|execute_|ctl_flags_xy_we~6_combout ))) # (!\z80_|execute_|ctl_flags_alu~14_combout ) - - .dataa(\z80_|execute_|ctl_flags_alu~14_combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~6_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~6_combout ), - .datad(\z80_|execute_|ctl_flags_hf_we~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_we~4 .lut_mask = 16'hFFDF; -defparam \z80_|execute_|ctl_flags_hf_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N6 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_hf~1 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_hf~1_combout = (\z80_|execute_|ctl_flags_hf_we~2_combout & ((\z80_|execute_|ctl_flags_hf_we~4_combout & (\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout )) # (!\z80_|execute_|ctl_flags_hf_we~4_combout & -// ((\z80_|alu_flags_|DFFE_inst_latch_hf~q ))))) # (!\z80_|execute_|ctl_flags_hf_we~2_combout & (\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout )) - - .dataa(\z80_|execute_|ctl_flags_hf_we~2_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), - .datad(\z80_|execute_|ctl_flags_hf_we~4_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_hf~1 .lut_mask = 16'hCCE4; -defparam \z80_|alu_flags_|DFFE_inst_latch_hf~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y11_N7 -dffeas \z80_|alu_flags_|DFFE_inst_latch_hf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_hf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_hf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_cpl~11_combout = (\z80_|execute_|ctl_mRead~6_combout ) # ((\z80_|pla_decode_|Equal52~1_combout ) # (\z80_|execute_|ctl_state_alu~14_combout )) - - .dataa(\z80_|execute_|ctl_mRead~6_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal52~1_combout ), - .datad(\z80_|execute_|ctl_state_alu~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_cpl~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_cpl~11 .lut_mask = 16'hFFFA; -defparam \z80_|execute_|ctl_flags_hf_cpl~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~12 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_cpl~12_combout = ((\z80_|execute_|ctl_flags_hf_cpl~11_combout ) # ((\z80_|pla_decode_|Equal10~0_combout ) # (\z80_|execute_|ctl_alu_op_low~12_combout ))) # (!\z80_|execute_|ctl_flags_hf_cpl~10_combout ) - - .dataa(\z80_|execute_|ctl_flags_hf_cpl~10_combout ), - .datab(\z80_|execute_|ctl_flags_hf_cpl~11_combout ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_cpl~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_cpl~12 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_flags_hf_cpl~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~13 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_cpl~13_combout = (\z80_|execute_|ctl_flags_hf_cpl~12_combout & (\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|alu_flags_|DFFE_inst_latch_nf~q ))) - - .dataa(\z80_|execute_|ctl_flags_hf_cpl~12_combout ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_cpl~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_cpl~13 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_flags_hf_cpl~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N8 -cycloneive_lcell_comb \z80_|alu_flags_|flags_hf ( -// Equation(s): -// \z80_|alu_flags_|flags_hf~combout = \z80_|alu_flags_|DFFE_inst_latch_hf~q $ (((\z80_|execute_|ctl_flags_hf_cpl~13_combout ) # ((!\z80_|alu_flags_|flags_cf~combout & \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout )))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), - .datab(\z80_|alu_flags_|flags_cf~combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .datad(\z80_|execute_|ctl_flags_hf_cpl~13_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|flags_hf~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_hf .lut_mask = 16'h559A; -defparam \z80_|alu_flags_|flags_hf .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N30 -cycloneive_lcell_comb \z80_|alu_control_|alu_core_cf_in~0 ( -// Equation(s): -// \z80_|alu_control_|alu_core_cf_in~0_combout = (\z80_|execute_|ctl_alu_core_hf~40_combout & ((\z80_|alu_flags_|flags_hf~combout ))) # (!\z80_|execute_|ctl_alu_core_hf~40_combout & (\z80_|alu_flags_|flags_cf~combout )) - - .dataa(\z80_|execute_|ctl_alu_core_hf~40_combout ), - .datab(\z80_|alu_flags_|flags_cf~combout ), - .datac(gnd), - .datad(\z80_|alu_flags_|flags_hf~combout ), - .cin(gnd), - .combout(\z80_|alu_control_|alu_core_cf_in~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|alu_core_cf_in~0 .lut_mask = 16'hEE44; -defparam \z80_|alu_control_|alu_core_cf_in~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N20 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout = (\z80_|alu_|alu_op2[0]~3_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ) # ((\z80_|alu_control_|alu_core_cf_in~0_combout & \z80_|alu_|alu_op1[0]~1_combout )))) -// # (!\z80_|alu_|alu_op2[0]~3_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_control_|alu_core_cf_in~0_combout ) # (\z80_|alu_|alu_op1[0]~1_combout )))) - - .dataa(\z80_|alu_|alu_op2[0]~3_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ), - .datac(\z80_|alu_control_|alu_core_cf_in~0_combout ), - .datad(\z80_|alu_|alu_op1[0]~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 .lut_mask = 16'hECC8; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N12 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~23 ( -// Equation(s): -// \z80_|alu_|db_high[0]~23_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[5]~25_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[3]~11_combout )) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|alu_|db[3]~11_combout ), - .datac(\z80_|alu_|db[5]~25_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~23 .lut_mask = 16'hE4E4; -defparam \z80_|alu_|db_high[0]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N8 -cycloneive_lcell_comb \z80_|address_latch_|abusz[12] ( -// Equation(s): -// \z80_|address_latch_|abusz [12] = (\z80_|reg_file_|db_hi_as[4]~18_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(gnd), - .datab(\z80_|reg_file_|db_hi_as[4]~18_combout ), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [12]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[12] .lut_mask = 16'h0C0C; -defparam \z80_|address_latch_|abusz[12] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N14 -cycloneive_lcell_comb \z80_|address_latch_|Q[12]~feeder ( -// Equation(s): -// \z80_|address_latch_|Q[12]~feeder_combout = \z80_|address_latch_|abusz [12] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [12]), - .cin(gnd), - .combout(\z80_|address_latch_|Q[12]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|Q[12]~feeder .lut_mask = 16'hFF00; -defparam \z80_|address_latch_|Q[12]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N15 -dffeas \z80_|address_latch_|Q[12] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|Q[12]~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [12]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[12] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[12] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N30 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout = \z80_|address_latch_|Q [12] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout & (\z80_|execute_|ctl_inc_dec~11_combout $ -// (\z80_|address_latch_|Q [11]))))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), - .datab(\z80_|execute_|ctl_inc_dec~11_combout ), - .datac(\z80_|address_latch_|Q [12]), - .datad(\z80_|address_latch_|Q [11]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out .lut_mask = 16'hD278; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N5 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[4]~18_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y15_N7 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[4]~18_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N6 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~16 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[4]~16_combout = (\z80_|reg_control_|reg_sw_4d_hi~0_combout & (\z80_|reg_file_|gdfx_temp1[4]~66_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) - - .dataa(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [4]), - .datad(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[4]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[4]~16 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|db_hi_as[4]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N18 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~17 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[4]~17_combout = (\z80_|reg_file_|db_hi_as[4]~16_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datab(gnd), - .datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [4]), - .datad(\z80_|reg_file_|db_hi_as[4]~16_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[4]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[4]~17 .lut_mask = 16'hF500; -defparam \z80_|reg_file_|db_hi_as[4]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N4 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~18 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[4]~18_combout = ((\z80_|reg_file_|db_hi_as[4]~17_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datad(\z80_|reg_file_|db_hi_as[4]~17_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[4]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[4]~18 .lut_mask = 16'hBF0F; -defparam \z80_|reg_file_|db_hi_as[4]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y11_N11 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~62 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~62_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (\z80_|reg_file_|b2v_latch_af2_hi|latch [4] & ((\z80_|alu_|db[4]~17_combout ) # (!\z80_|execute_|ctl_reg_in_hi~12_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (((\z80_|alu_|db[4]~17_combout )) # (!\z80_|execute_|ctl_reg_in_hi~12_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [4]), - .datad(\z80_|alu_|db[4]~17_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~62_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~62 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[4]~62 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y15_N13 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y11_N29 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~63 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~63_combout = (\z80_|reg_file_|b2v_latch_sp_hi|latch [4] & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ))) # (!\z80_|reg_file_|b2v_latch_sp_hi|latch [4] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_sp_hi|latch [4]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~63_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~63 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[4]~63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y12_N23 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y12_N21 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~61 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~61_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (\z80_|reg_file_|b2v_latch_ix_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_iy_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (((\z80_|reg_file_|b2v_latch_iy_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_iy_hi|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~61_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~61 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[4]~61 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N24 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder_combout = \z80_|reg_file_|gdfx_temp1[4]~66_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y13_N25 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y13_N23 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~60 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~60_combout = (\z80_|reg_file_|b2v_latch_bc_hi|latch [4] & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_hi|latch [4] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc_hi|latch [4]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~60_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~60 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[4]~60 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~64 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~64_combout = (\z80_|reg_file_|gdfx_temp1[4]~62_combout & (\z80_|reg_file_|gdfx_temp1[4]~63_combout & (\z80_|reg_file_|gdfx_temp1[4]~61_combout & \z80_|reg_file_|gdfx_temp1[4]~60_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[4]~62_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[4]~63_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[4]~61_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[4]~60_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~64_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~64 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[4]~64 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N31 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y14_N29 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~59 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~59_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~59_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~59 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[4]~59 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y13_N23 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y13_N13 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~58 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~58_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~58_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~58 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[4]~58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y14_N19 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N18 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[4]~19 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[4]~19_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [4]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [4]), - .datad(\z80_|reg_control_|reg_sel_af~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[4]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[4]~19 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[4]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~65 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~65_combout = (\z80_|reg_file_|gdfx_temp1[4]~64_combout & (\z80_|reg_file_|gdfx_temp1[4]~59_combout & (\z80_|reg_file_|gdfx_temp1[4]~58_combout & \z80_|reg_file_|b2v_latch_af_hi|db[4]~19_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[4]~64_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[4]~59_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[4]~58_combout ), - .datad(\z80_|reg_file_|b2v_latch_af_hi|db[4]~19_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~65_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~65 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[4]~65 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~66 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~66_combout = ((\z80_|reg_file_|gdfx_temp1[4]~65_combout & ((\z80_|reg_file_|db_hi_as[4]~18_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datab(\z80_|reg_file_|db_hi_as[4]~18_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[4]~65_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~66 .lut_mask = 16'hD5F5; -defparam \z80_|reg_file_|gdfx_temp1[4]~66 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N26 -cycloneive_lcell_comb \z80_|alu_|db[4]~16 ( -// Equation(s): -// \z80_|alu_|db[4]~16_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[4]~66_combout & ((\z80_|alu_control_|db[4]~32_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & -// (((\z80_|alu_control_|db[4]~32_combout )) # (!\z80_|execute_|ctl_sw_2d~13_combout ))) - - .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datab(\z80_|execute_|ctl_sw_2d~13_combout ), - .datac(\z80_|alu_control_|db[4]~32_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[4]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[4]~16 .lut_mask = 16'hF351; -defparam \z80_|alu_|db[4]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N2 -cycloneive_lcell_comb \z80_|alu_|db[7]~26 ( -// Equation(s): -// \z80_|alu_|db[7]~26_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout ) # ((\z80_|execute_|ctl_alu_oe~13_combout ) # ((\z80_|execute_|ctl_sw_2d~13_combout ) # (!\z80_|execute_|ctl_alu_oe~9_combout ))) - - .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datab(\z80_|execute_|ctl_alu_oe~13_combout ), - .datac(\z80_|execute_|ctl_alu_oe~9_combout ), - .datad(\z80_|execute_|ctl_sw_2d~13_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[7]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[7]~26 .lut_mask = 16'hFFEF; -defparam \z80_|alu_|db[7]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N0 -cycloneive_lcell_comb \z80_|alu_|db[4]~17 ( -// Equation(s): -// \z80_|alu_|db[4]~17_combout = ((\z80_|alu_|db[4]~16_combout & ((\z80_|alu_|db_high[0]~26_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~26_combout ) - - .dataa(\z80_|alu_|db[4]~16_combout ), - .datab(\z80_|alu_|db[7]~26_combout ), - .datac(\z80_|alu_|db_high[0]~26_combout ), - .datad(\z80_|execute_|ctl_alu_oe~14_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[4]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[4]~17 .lut_mask = 16'hB3BB; -defparam \z80_|alu_|db[4]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_sel_shift~3_combout = (\z80_|execute_|ctl_state_alu~6_combout ) # ((\z80_|pla_decode_|Equal33~0_combout & (\z80_|execute_|ctl_mWrite~3_combout & \z80_|decode_state_|DFFE_instCB~q ))) - - .dataa(\z80_|execute_|ctl_state_alu~6_combout ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~3_combout ), - .datad(\z80_|decode_state_|DFFE_instCB~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~3 .lut_mask = 16'hEAAA; -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_sel_shift~5_combout = (\z80_|sequencer_|DFFE_T4_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|execute_|ctl_ir_we~8_combout ) # (\z80_|pla_decode_|Equal20~0_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|pla_decode_|Equal20~0_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~5 .lut_mask = 16'h00C8; -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_sel_shift~4_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ) # ((\z80_|execute_|ctl_ir_we~6_combout & (\z80_|execute_|ctl_flags_cf2_sel_shift~3_combout & \z80_|execute_|ctl_ir_we~5_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~6_combout ), - .datab(\z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ), - .datac(\z80_|execute_|ctl_ir_we~5_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~4 .lut_mask = 16'hFF80; -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N10 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~24 ( -// Equation(s): -// \z80_|alu_|db_high[0]~24_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_high[0]~23_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[4]~17_combout ))) - - .dataa(\z80_|alu_|db_high[0]~23_combout ), - .datab(gnd), - .datac(\z80_|alu_|db[4]~17_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~24 .lut_mask = 16'hAAF0; -defparam \z80_|alu_|db_high[0]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N4 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~21 ( -// Equation(s): -// \z80_|alu_|db_high[0]~21_combout = ((!\z80_|bus_control_|db[4]~19_combout & (\z80_|bus_control_|db[5]~15_combout & !\z80_|bus_control_|db[3]~21_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datab(\z80_|bus_control_|db[4]~19_combout ), - .datac(\z80_|bus_control_|db[5]~15_combout ), - .datad(\z80_|bus_control_|db[3]~21_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~21 .lut_mask = 16'h5575; -defparam \z80_|alu_|db_high[0]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N20 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[0] ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_high|Q [0] = (\z80_|alu_|db_high[0]~26_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) - - .dataa(gnd), - .datab(\z80_|alu_|db_high[0]~26_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [0]), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[0] .lut_mask = 16'h00C0; -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[0] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y10_N21 -dffeas \z80_|alu_|op1_high[0] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [0]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_high [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_high[0] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_high[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N8 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~22 ( -// Equation(s): -// \z80_|alu_|db_high[0]~22_combout = (\z80_|alu_|op1_high [0] & (((\z80_|alu_|op2_high [0]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|alu_|op1_high [0] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_high [0]) # -// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) - - .dataa(\z80_|alu_|op1_high [0]), - .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datac(\z80_|alu_|op2_high [0]), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~22 .lut_mask = 16'hB0BB; -defparam \z80_|alu_|db_high[0]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N4 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~25 ( -// Equation(s): -// \z80_|alu_|db_high[0]~25_combout = (\z80_|alu_|db_high[0]~21_combout & (\z80_|alu_|db_high[0]~22_combout & ((\z80_|alu_|db_high[0]~24_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) - - .dataa(\z80_|alu_|db_high[0]~24_combout ), - .datab(\z80_|alu_|db_high[0]~21_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datad(\z80_|alu_|db_high[0]~22_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~25 .lut_mask = 16'h8C00; -defparam \z80_|alu_|db_high[0]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N22 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~26 ( -// Equation(s): -// \z80_|alu_|db_high[0]~26_combout = ((\z80_|alu_|db_high[0]~25_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) # (!\z80_|alu_|db_high[3]~3_combout ) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), - .datab(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datac(\z80_|alu_|db_high[0]~25_combout ), - .datad(\z80_|alu_|db_high[3]~3_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~26 .lut_mask = 16'hE0FF; -defparam \z80_|alu_|db_high[0]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N4 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout = (\z80_|alu_|db_low[0]~23_combout & ((\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_low~combout & \z80_|alu_|db_high[0]~26_combout )))) # -// (!\z80_|alu_|db_low[0]~23_combout & (((\z80_|execute_|ctl_alu_op1_sel_low~combout & \z80_|alu_|db_high[0]~26_combout )))) - - .dataa(\z80_|alu_|db_low[0]~23_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .datad(\z80_|alu_|db_high[0]~26_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 .lut_mask = 16'hF888; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N30 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8_combout = (\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8 .lut_mask = 16'h00F0; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N12 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|ena ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|ena~combout = (\z80_|execute_|ctl_alu_op1_sel_low~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~combout ) # (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout )) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|ena .lut_mask = 16'hFEFE; -defparam \z80_|alu_|b2v_op1_latch_mux_low|ena .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y10_N31 -dffeas \z80_|alu_|op1_low[0] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_low [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_low[0] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_low[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N12 -cycloneive_lcell_comb \z80_|alu_|alu_op1[0]~1 ( -// Equation(s): -// \z80_|alu_|alu_op1[0]~1_combout = (\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [0])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [0]))) - - .dataa(\z80_|execute_|ctl_alu_op_low~combout ), - .datab(\z80_|alu_|op1_low [0]), - .datac(\z80_|alu_|op1_high [0]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|alu_op1[0]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op1[0]~1 .lut_mask = 16'hD8D8; -defparam \z80_|alu_|alu_op1[0]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N30 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout = (\z80_|alu_|alu_op1[0]~1_combout & ((\z80_|execute_|ctl_alu_op2_sel_lq~combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~8_combout & \z80_|alu_|db_low[0]~23_combout )))) # -// (!\z80_|alu_|alu_op1[0]~1_combout & (\z80_|execute_|ctl_alu_op2_sel_bus~8_combout & ((\z80_|alu_|db_low[0]~23_combout )))) - - .dataa(\z80_|alu_|alu_op1[0]~1_combout ), - .datab(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datad(\z80_|alu_|db_low[0]~23_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 .lut_mask = 16'hECA0; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N14 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datab(gnd), - .datac(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 .lut_mask = 16'h5050; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y10_N15 -dffeas \z80_|alu_|op2_low[0] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_low [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_low[0] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_low[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N12 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout = (\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [0]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [0])) - - .dataa(\z80_|alu_|op2_low [0]), - .datab(gnd), - .datac(\z80_|alu_|op2_high [0]), - .datad(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'hF0AA; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N14 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout = (\z80_|alu_control_|alu_core_cf_in~0_combout & ((\z80_|alu_|alu_op1[0]~1_combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout $ -// (\z80_|execute_|ctl_alu_sel_op2_neg~18_combout )))) # (!\z80_|alu_control_|alu_core_cf_in~0_combout & (\z80_|alu_|alu_op1[0]~1_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout $ -// (\z80_|execute_|ctl_alu_sel_op2_neg~18_combout )))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), - .datac(\z80_|alu_control_|alu_core_cf_in~0_combout ), - .datad(\z80_|alu_|alu_op1[0]~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hF660; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N28 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|execute_|ctl_alu_core_S~9_combout & (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout & -// \z80_|execute_|ctl_alu_core_S~8_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_S~9_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), - .datac(\z80_|execute_|ctl_alu_core_R~combout ), - .datad(\z80_|execute_|ctl_alu_core_S~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 .lut_mask = 16'hF1F0; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N26 -cycloneive_lcell_comb \z80_|alu_|alu_op1[1]~0 ( -// Equation(s): -// \z80_|alu_|alu_op1[1]~0_combout = (\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [1])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [1]))) - - .dataa(\z80_|execute_|ctl_alu_op_low~combout ), - .datab(\z80_|alu_|op1_low [1]), - .datac(gnd), - .datad(\z80_|alu_|op1_high [1]), - .cin(gnd), - .combout(\z80_|alu_|alu_op1[1]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op1[1]~0 .lut_mask = 16'hDD88; -defparam \z80_|alu_|alu_op1[1]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N0 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout = (\z80_|execute_|ctl_alu_core_S~9_combout ) # (((\z80_|alu_|alu_op1[1]~0_combout & \z80_|alu_|alu_op2[1]~1_combout )) # (!\z80_|execute_|ctl_alu_core_S~8_combout )) - - .dataa(\z80_|execute_|ctl_alu_core_S~9_combout ), - .datab(\z80_|execute_|ctl_alu_core_S~8_combout ), - .datac(\z80_|alu_|alu_op1[1]~0_combout ), - .datad(\z80_|alu_|alu_op2[1]~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'hFBBB; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N24 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout = (!\z80_|execute_|ctl_alu_core_R~combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ) # -// ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout & !\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout )))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), - .datac(\z80_|execute_|ctl_alu_core_R~combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 .lut_mask = 16'h0F01; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N26 -cycloneive_lcell_comb \z80_|alu_|alu_op1[2]~2 ( -// Equation(s): -// \z80_|alu_|alu_op1[2]~2_combout = (\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [2]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [2])) - - .dataa(\z80_|alu_|op1_high [2]), - .datab(\z80_|execute_|ctl_alu_op_low~combout ), - .datac(gnd), - .datad(\z80_|alu_|op1_low [2]), - .cin(gnd), - .combout(\z80_|alu_|alu_op1[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op1[2]~2 .lut_mask = 16'hEE22; -defparam \z80_|alu_|alu_op1[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N8 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout = (\z80_|execute_|ctl_alu_core_S~9_combout ) # (((\z80_|alu_|alu_op2[2]~0_combout & \z80_|alu_|alu_op1[2]~2_combout )) # (!\z80_|execute_|ctl_alu_core_S~8_combout )) - - .dataa(\z80_|alu_|alu_op2[2]~0_combout ), - .datab(\z80_|execute_|ctl_alu_core_S~9_combout ), - .datac(\z80_|alu_|alu_op1[2]~2_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hECFF; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N2 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ) # -// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), - .datad(\z80_|execute_|ctl_alu_core_R~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 .lut_mask = 16'hFF0B; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~5_combout = (\z80_|execute_|ctl_alu_core_R~4_combout & \z80_|execute_|ctl_alu_core_S~8_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_core_R~4_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~5 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_alu_core_R~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N6 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ) # -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout )))) # (!\z80_|execute_|ctl_alu_core_R~5_combout ) - - .dataa(\z80_|execute_|ctl_alu_core_R~5_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1 .lut_mask = 16'h5F5D; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N14 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout = (\z80_|alu_|alu_op1[3]~3_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout & -// \z80_|alu_|alu_op2[3]~2_combout )))) # (!\z80_|alu_|alu_op1[3]~3_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_|alu_op2[3]~2_combout ) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout )))) - - .dataa(\z80_|alu_|alu_op1[3]~3_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), - .datac(\z80_|alu_|alu_op2[3]~2_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 .lut_mask = 16'hFB20; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N12 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder_combout = \z80_|reg_file_|gdfx_temp1[7]~75_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y13_N13 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y13_N19 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~69 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~69_combout = (\z80_|reg_file_|b2v_latch_bc_hi|latch [7] & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_hi|latch [7] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc_hi|latch [7]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~69_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~69 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[7]~69 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y12_N3 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y12_N25 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~70 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~70_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (\z80_|reg_file_|b2v_latch_ix_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_iy_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (((\z80_|reg_file_|b2v_latch_iy_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_iy_hi|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~70_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~70 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[7]~70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y15_N11 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y11_N27 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~72 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~72_combout = (\z80_|reg_file_|b2v_latch_sp_hi|latch [7] & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ))) # (!\z80_|reg_file_|b2v_latch_sp_hi|latch [7] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_sp_hi|latch [7]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~72_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~72 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[7]~72 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y11_N17 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~71 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~71_combout = (\z80_|alu_|db[7]~21_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[7]~21_combout & (!\z80_|execute_|ctl_reg_in_hi~12_combout & -// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|alu_|db[7]~21_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~71_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~71 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[7]~71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~73 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~73_combout = (\z80_|reg_file_|gdfx_temp1[7]~69_combout & (\z80_|reg_file_|gdfx_temp1[7]~70_combout & (\z80_|reg_file_|gdfx_temp1[7]~72_combout & \z80_|reg_file_|gdfx_temp1[7]~71_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[7]~69_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[7]~70_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[7]~72_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[7]~71_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~73_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~73 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[7]~73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y13_N27 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y13_N17 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~67 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~67_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~67_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~67 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[7]~67 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y14_N15 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N14 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[7]~20 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[7]~20_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [7]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [7]), - .datad(\z80_|reg_control_|reg_sel_af~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[7]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[7]~20 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[7]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N11 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y14_N21 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~68 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~68_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~68_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~68 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[7]~68 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y11_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~74 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~74_combout = (\z80_|reg_file_|gdfx_temp1[7]~73_combout & (\z80_|reg_file_|gdfx_temp1[7]~67_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[7]~20_combout & \z80_|reg_file_|gdfx_temp1[7]~68_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[7]~73_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[7]~67_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|db[7]~20_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[7]~68_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~74_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~74 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[7]~74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y15_N29 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[7]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N28 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~19 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[7]~19_combout = (\z80_|reg_file_|gdfx_temp1[7]~75_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) # (!\z80_|reg_file_|gdfx_temp1[7]~75_combout & -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [7]), - .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[7]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[7]~19 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_hi_as[7]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N27 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[7]~21_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N28 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~20 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[7]~20_combout = (\z80_|reg_file_|db_hi_as[7]~19_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|db_hi_as[7]~19_combout ), - .datab(gnd), - .datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[7]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[7]~20 .lut_mask = 16'hA0AA; -defparam \z80_|reg_file_|db_hi_as[7]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N2 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout & ((\z80_|execute_|ctl_inc_dec~11_combout & (!\z80_|address_latch_|Q [12] & -// !\z80_|address_latch_|Q [11])) # (!\z80_|execute_|ctl_inc_dec~11_combout & (\z80_|address_latch_|Q [12] & \z80_|address_latch_|Q [11])))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), - .datab(\z80_|execute_|ctl_inc_dec~11_combout ), - .datac(\z80_|address_latch_|Q [12]), - .datad(\z80_|address_latch_|Q [11]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'h2008; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N8 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout = \z80_|address_latch_|Q [13] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|address_latch_|Q [13]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out .lut_mask = 16'h0FF0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y12_N13 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y15_N5 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~54 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~54_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [5]), - .datad(\z80_|reg_file_|b2v_latch_sp_hi|latch [5]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~54_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~54 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[5]~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y11_N1 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~53 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~53_combout = (\z80_|alu_|db[5]~25_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[5]~25_combout & (!\z80_|execute_|ctl_reg_in_hi~12_combout & -// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|alu_|db[5]~25_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~53_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~53 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[5]~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N8 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder_combout = \z80_|reg_file_|gdfx_temp1[5]~57_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y13_N9 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y13_N11 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~51 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~51_combout = (\z80_|reg_file_|b2v_latch_bc_hi|latch [5] & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_hi|latch [5] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc_hi|latch [5]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~51_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~51 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[5]~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y12_N11 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y12_N3 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~52 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~52_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [5] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [5] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [5]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~52_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~52 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[5]~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~55 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~55_combout = (\z80_|reg_file_|gdfx_temp1[5]~54_combout & (\z80_|reg_file_|gdfx_temp1[5]~53_combout & (\z80_|reg_file_|gdfx_temp1[5]~51_combout & \z80_|reg_file_|gdfx_temp1[5]~52_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[5]~54_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[5]~53_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[5]~51_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[5]~52_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~55_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~55 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[5]~55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y13_N9 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y13_N3 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~49 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~49_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datab(\z80_|reg_file_|b2v_latch_de_hi|latch [5]), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~49 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[5]~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N5 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y14_N27 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~50 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~50_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [5]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [5]), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~50 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp1[5]~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y14_N21 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N20 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[5]~14 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[5]~14_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [5]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [5]), - .datad(\z80_|reg_control_|reg_sel_af~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[5]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[5]~14 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[5]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~56 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~56_combout = (\z80_|reg_file_|gdfx_temp1[5]~55_combout & (\z80_|reg_file_|gdfx_temp1[5]~49_combout & (\z80_|reg_file_|gdfx_temp1[5]~50_combout & \z80_|reg_file_|b2v_latch_af_hi|db[5]~14_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[5]~55_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[5]~49_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[5]~50_combout ), - .datad(\z80_|reg_file_|b2v_latch_af_hi|db[5]~14_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~56_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~56 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[5]~56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~57 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~57_combout = ((\z80_|reg_file_|gdfx_temp1[5]~56_combout & ((\z80_|reg_file_|db_hi_as[5]~15_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[5]~56_combout ), - .datac(\z80_|reg_file_|db_hi_as[5]~15_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~57 .lut_mask = 16'hD5DD; -defparam \z80_|reg_file_|gdfx_temp1[5]~57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y15_N1 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[5]~15_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N0 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~13 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[5]~13_combout = (\z80_|reg_control_|reg_sw_4d_hi~0_combout & (\z80_|reg_file_|gdfx_temp1[5]~57_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) - - .dataa(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[5]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[5]~13 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|db_hi_as[5]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N23 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[5]~15_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N16 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~14 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[5]~14_combout = (\z80_|reg_file_|db_hi_as[5]~13_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datab(\z80_|reg_file_|db_hi_as[5]~13_combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [5]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[5]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[5]~14 .lut_mask = 16'hC4C4; -defparam \z80_|reg_file_|db_hi_as[5]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N22 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~15 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[5]~15_combout = ((\z80_|reg_file_|db_hi_as[5]~14_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datad(\z80_|reg_file_|db_hi_as[5]~14_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[5]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[5]~15 .lut_mask = 16'hBF0F; -defparam \z80_|reg_file_|db_hi_as[5]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N2 -cycloneive_lcell_comb \z80_|address_latch_|abusz[13] ( -// Equation(s): -// \z80_|address_latch_|abusz [13] = (\z80_|reg_file_|db_hi_as[5]~15_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(gnd), - .datab(\z80_|reg_file_|db_hi_as[5]~15_combout ), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [13]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[13] .lut_mask = 16'h0C0C; -defparam \z80_|address_latch_|abusz[13] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N22 -cycloneive_lcell_comb \z80_|address_latch_|Q[13]~feeder ( -// Equation(s): -// \z80_|address_latch_|Q[13]~feeder_combout = \z80_|address_latch_|abusz [13] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [13]), - .cin(gnd), - .combout(\z80_|address_latch_|Q[13]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|Q[13]~feeder .lut_mask = 16'hFF00; -defparam \z80_|address_latch_|Q[13]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N23 -dffeas \z80_|address_latch_|Q[13] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|Q[13]~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [13]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[13] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[13] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N6 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout = \z80_|address_latch_|Q [13] $ (\z80_|execute_|ctl_inc_dec~11_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|address_latch_|Q [13]), - .datad(\z80_|execute_|ctl_inc_dec~11_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 .lut_mask = 16'h0FF0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N26 -cycloneive_lcell_comb \z80_|address_latch_|abusz[15] ( -// Equation(s): -// \z80_|address_latch_|abusz [15] = (\z80_|reg_file_|db_hi_as[7]~21_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|reg_file_|db_hi_as[7]~21_combout ), - .datad(\z80_|resets_|clrpc~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [15]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[15] .lut_mask = 16'h00F0; -defparam \z80_|address_latch_|abusz[15] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N27 -dffeas \z80_|address_latch_|Q[15] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [15]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [15]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[15] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[15] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N20 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[14] ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|address [14] = \z80_|address_latch_|Q [14] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout & (\z80_|address_latch_|Q [13] $ (\z80_|execute_|ctl_inc_dec~11_combout ))))) - - .dataa(\z80_|address_latch_|Q [13]), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), - .datac(\z80_|address_latch_|Q [14]), - .datad(\z80_|execute_|ctl_inc_dec~11_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[14] .lut_mask = 16'hB478; -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[14] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N7 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[6]~24_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y13_N11 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y13_N21 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~76 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~76_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~76_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~76 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[6]~76 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y11_N23 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~80 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~80_combout = (\z80_|alu_|db[6]~23_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[6]~23_combout & (!\z80_|execute_|ctl_reg_in_hi~12_combout & -// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|alu_|db[6]~23_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~80_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~80 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[6]~80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y12_N17 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y12_N9 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~79 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~79_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [6] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [6] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [6]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~79_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~79 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[6]~79 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y13_N27 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y13_N29 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~78 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~78_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (\z80_|reg_file_|b2v_latch_bc2_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_bc_hi|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~78_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~78 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[6]~78 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y15_N25 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y12_N7 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~81 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~81_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [6]), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~81_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~81 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[6]~81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~82 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~82_combout = (\z80_|reg_file_|gdfx_temp1[6]~80_combout & (\z80_|reg_file_|gdfx_temp1[6]~79_combout & (\z80_|reg_file_|gdfx_temp1[6]~78_combout & \z80_|reg_file_|gdfx_temp1[6]~81_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[6]~80_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[6]~79_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[6]~78_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[6]~81_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~82_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~82 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[6]~82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N23 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y14_N25 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~77 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~77_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~77_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~77 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[6]~77 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y14_N13 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N12 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[6]~21 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[6]~21_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [6]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [6]), - .datad(\z80_|reg_control_|reg_sel_af~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[6]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[6]~21 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[6]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~83 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~83_combout = (\z80_|reg_file_|gdfx_temp1[6]~76_combout & (\z80_|reg_file_|gdfx_temp1[6]~82_combout & (\z80_|reg_file_|gdfx_temp1[6]~77_combout & \z80_|reg_file_|b2v_latch_af_hi|db[6]~21_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[6]~76_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[6]~82_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[6]~77_combout ), - .datad(\z80_|reg_file_|b2v_latch_af_hi|db[6]~21_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~83_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~83 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[6]~83 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~84 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~84_combout = ((\z80_|reg_file_|gdfx_temp1[6]~83_combout & ((\z80_|reg_file_|db_hi_as[6]~24_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[6]~83_combout ), - .datac(\z80_|reg_file_|db_hi_as[6]~24_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~84 .lut_mask = 16'hD5DD; -defparam \z80_|reg_file_|gdfx_temp1[6]~84 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y15_N19 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[6]~24_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N18 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~22 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[6]~22_combout = (\z80_|reg_control_|reg_sw_4d_hi~0_combout & (\z80_|reg_file_|gdfx_temp1[6]~84_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) - - .dataa(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[6]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[6]~22 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|db_hi_as[6]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N20 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~23 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[6]~23_combout = (\z80_|reg_file_|db_hi_as[6]~22_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|b2v_latch_pc_hi|latch [6]), - .datab(\z80_|reg_file_|db_hi_as[6]~22_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[6]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[6]~23 .lut_mask = 16'h88CC; -defparam \z80_|reg_file_|db_hi_as[6]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N6 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~24 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[6]~24_combout = ((\z80_|reg_file_|db_hi_as[6]~23_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [14]) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), - .datab(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datad(\z80_|reg_file_|db_hi_as[6]~23_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[6]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[6]~24 .lut_mask = 16'hBF33; -defparam \z80_|reg_file_|db_hi_as[6]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N14 -cycloneive_lcell_comb \z80_|address_latch_|abusz[14] ( -// Equation(s): -// \z80_|address_latch_|abusz [14] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[6]~24_combout ) - - .dataa(\z80_|resets_|clrpc~0_combout ), - .datab(gnd), - .datac(\z80_|reg_file_|db_hi_as[6]~24_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [14]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[14] .lut_mask = 16'h5050; -defparam \z80_|address_latch_|abusz[14] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N4 -cycloneive_lcell_comb \z80_|address_latch_|Q[14]~feeder ( -// Equation(s): -// \z80_|address_latch_|Q[14]~feeder_combout = \z80_|address_latch_|abusz [14] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [14]), - .cin(gnd), - .combout(\z80_|address_latch_|Q[14]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|Q[14]~feeder .lut_mask = 16'hFF00; -defparam \z80_|address_latch_|Q[14]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N5 -dffeas \z80_|address_latch_|Q[14] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|Q[14]~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [14]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[14] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[14] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y16_N4 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout = \z80_|address_latch_|Q [14] $ (((\z80_|execute_|ctl_inc_dec~9_combout ) # ((\z80_|execute_|ctl_inc_dec~7_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout )))) - - .dataa(\z80_|execute_|ctl_inc_dec~9_combout ), - .datab(\z80_|address_latch_|Q [14]), - .datac(\z80_|execute_|ctl_inc_dec~6_combout ), - .datad(\z80_|execute_|ctl_inc_dec~7_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16 .lut_mask = 16'h3363; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N12 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[15] ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|address [15] = \z80_|address_latch_|Q [15] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout & -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout )))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), - .datac(\z80_|address_latch_|Q [15]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [15]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[15] .lut_mask = 16'h78F0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[15] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N26 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~21 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[7]~21_combout = ((\z80_|reg_file_|db_hi_as[7]~20_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [15]) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_hi_as[7]~20_combout ), - .datab(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|address [15]), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[7]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[7]~21 .lut_mask = 16'hBB3B; -defparam \z80_|reg_file_|db_hi_as[7]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~75 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~75_combout = ((\z80_|reg_file_|gdfx_temp1[7]~74_combout & ((\z80_|reg_file_|db_hi_as[7]~21_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[7]~74_combout ), - .datac(\z80_|reg_file_|db_hi_as[7]~21_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~75 .lut_mask = 16'hD5DD; -defparam \z80_|reg_file_|gdfx_temp1[7]~75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N6 -cycloneive_lcell_comb \z80_|alu_|db[7]~20 ( -// Equation(s): -// \z80_|alu_|db[7]~20_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[7]~75_combout & ((\z80_|alu_control_|db[7]~18_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & -// (((\z80_|alu_control_|db[7]~18_combout )) # (!\z80_|execute_|ctl_sw_2d~13_combout ))) - - .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datab(\z80_|execute_|ctl_sw_2d~13_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .datad(\z80_|alu_control_|db[7]~18_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[7]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[7]~20 .lut_mask = 16'hF531; -defparam \z80_|alu_|db[7]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N24 -cycloneive_lcell_comb \z80_|alu_|db[7]~21 ( -// Equation(s): -// \z80_|alu_|db[7]~21_combout = ((\z80_|alu_|db[7]~20_combout & ((\z80_|alu_|db_high[3]~8_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~26_combout ) - - .dataa(\z80_|alu_|db[7]~20_combout ), - .datab(\z80_|alu_|db[7]~26_combout ), - .datac(\z80_|alu_|db_high[3]~8_combout ), - .datad(\z80_|execute_|ctl_alu_oe~14_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[7]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[7]~21 .lut_mask = 16'hB3BB; -defparam \z80_|alu_|db[7]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N22 -cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~1 ( -// Equation(s): -// \z80_|alu_control_|b2v_inst_shift_mux|out~1_combout = (\z80_|ir_|opcode [5] & (\z80_|alu_|db[7]~21_combout & ((\z80_|ir_|opcode [3])))) # (!\z80_|ir_|opcode [5] & ((\z80_|ir_|opcode [3] & ((\z80_|alu_|db[0]~19_combout ))) # (!\z80_|ir_|opcode [3] & -// (\z80_|alu_|db[7]~21_combout )))) - - .dataa(\z80_|alu_|db[7]~21_combout ), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|alu_|db[0]~19_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~1 .lut_mask = 16'hB822; -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N4 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~0 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf~0_combout = (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & (\z80_|alu_control_|db[0]~12_combout & (\z80_|execute_|ctl_flags_bus~combout ))) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & -// ((\z80_|execute_|ctl_flags_alu~15_combout ) # ((\z80_|alu_control_|db[0]~12_combout & \z80_|execute_|ctl_flags_bus~combout )))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), - .datab(\z80_|alu_control_|db[0]~12_combout ), - .datac(\z80_|execute_|ctl_flags_bus~combout ), - .datad(\z80_|execute_|ctl_flags_alu~15_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~0 .lut_mask = 16'hD5C0; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~4_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # ((\z80_|execute_|ixy_d~6_combout & \z80_|execute_|ctl_mRead~36_combout ))) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|execute_|ctl_mRead~36_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~4 .lut_mask = 16'hFFF8; -defparam \z80_|execute_|ctl_flags_cf_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~5_combout = ((\z80_|execute_|ctl_flags_cf_we~4_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # (\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ))) # (!\z80_|execute_|ctl_flags_cf_we~7_combout ) - - .dataa(\z80_|execute_|ctl_flags_cf_we~7_combout ), - .datab(\z80_|execute_|ctl_flags_cf_we~4_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .datad(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~5 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_flags_cf_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~3_combout = (\z80_|execute_|ctl_flags_hf2_we~combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((!\z80_|execute_|ctl_flags_bus~5_combout ) # (!\z80_|execute_|ctl_flags_bus~4_combout )))) - - .dataa(\z80_|execute_|ctl_flags_bus~4_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|execute_|ctl_flags_hf2_we~combout ), - .datad(\z80_|execute_|ctl_flags_bus~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~3 .lut_mask = 16'hF4FC; -defparam \z80_|execute_|ctl_flags_cf_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~6_combout = ((\z80_|execute_|ctl_flags_cf_we~5_combout ) # ((\z80_|execute_|ctl_flags_cf_we~3_combout ) # (!\z80_|execute_|ctl_flags_cf_we~2_combout ))) # (!\z80_|execute_|ctl_flags_hf_we~2_combout ) - - .dataa(\z80_|execute_|ctl_flags_hf_we~2_combout ), - .datab(\z80_|execute_|ctl_flags_cf_we~5_combout ), - .datac(\z80_|execute_|ctl_flags_cf_we~3_combout ), - .datad(\z80_|execute_|ctl_flags_cf_we~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~6 .lut_mask = 16'hFDFF; -defparam \z80_|execute_|ctl_flags_cf_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_we~2_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~38_combout ) # (!\z80_|execute_|ctl_alu_op1_sel_bus~7_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_we~2 .lut_mask = 16'hCFFF; -defparam \z80_|execute_|ctl_flags_cf2_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_we~4_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & ((\z80_|pla_decode_|Equal11~0_combout ) # (\z80_|pla_decode_|Equal10~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal11~0_combout ), - .datab(\z80_|pla_decode_|Equal10~0_combout ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_we~4 .lut_mask = 16'hE000; -defparam \z80_|execute_|ctl_flags_cf2_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_we~3_combout = (\z80_|execute_|ctl_flags_cf2_we~2_combout ) # ((\z80_|execute_|ctl_flags_cf2_we~4_combout ) # ((\z80_|sequencer_|DFFE_T3_ff~q & \z80_|execute_|ixy_d~15_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|execute_|ctl_flags_cf2_we~2_combout ), - .datac(\z80_|execute_|ixy_d~15_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_we~3 .lut_mask = 16'hFFEC; -defparam \z80_|execute_|ctl_flags_cf2_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N2 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~1 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf~1_combout = (\z80_|execute_|ctl_flags_cf_we~6_combout & ((\z80_|execute_|ctl_flags_cf2_we~3_combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf~q ))) # (!\z80_|execute_|ctl_flags_cf2_we~3_combout & -// (\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout )))) # (!\z80_|execute_|ctl_flags_cf_we~6_combout & (((\z80_|alu_flags_|DFFE_inst_latch_cf~q )))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ), - .datab(\z80_|execute_|ctl_flags_cf_we~6_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), - .datad(\z80_|execute_|ctl_flags_cf2_we~3_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~1 .lut_mask = 16'hF0B8; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y9_N3 -dffeas \z80_|alu_flags_|DFFE_inst_latch_cf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N0 -cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~0 ( -// Equation(s): -// \z80_|alu_control_|b2v_inst_shift_mux|out~0_combout = (\z80_|ir_|opcode [4] & ((\z80_|ir_|opcode [5] & ((!\z80_|ir_|opcode [3]))) # (!\z80_|ir_|opcode [5] & (\z80_|alu_flags_|DFFE_inst_latch_cf~q )))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~0 .lut_mask = 16'h0A88; -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N4 -cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~2 ( -// Equation(s): -// \z80_|alu_control_|b2v_inst_shift_mux|out~2_combout = (\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ) # ((\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout & !\z80_|ir_|opcode [4])) - - .dataa(\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ), - .datab(\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ), - .datac(gnd), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~2 .lut_mask = 16'hCCEE; -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N14 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~5 ( -// Equation(s): -// \z80_|alu_|db_high[3]~5_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[6]~23_combout ))) - - .dataa(gnd), - .datab(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), - .datac(\z80_|alu_|db[6]~23_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~5 .lut_mask = 16'hCCF0; -defparam \z80_|alu_|db_high[3]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N20 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~6 ( -// Equation(s): -// \z80_|alu_|db_high[3]~6_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_high[3]~5_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[7]~21_combout ))) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .datab(\z80_|alu_|db_high[3]~5_combout ), - .datac(\z80_|alu_|db[7]~21_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~6 .lut_mask = 16'hD8D8; -defparam \z80_|alu_|db_high[3]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N28 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~4 ( -// Equation(s): -// \z80_|alu_|db_high[3]~4_combout = (\z80_|alu_|op2_high [3] & (((\z80_|alu_|op1_high [3])) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout ))) # (!\z80_|alu_|op2_high [3] & (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_high [3]) # -// (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) - - .dataa(\z80_|alu_|op2_high [3]), - .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datac(\z80_|alu_|op1_high [3]), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~4 .lut_mask = 16'hA2F3; -defparam \z80_|alu_|db_high[3]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N30 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~27 ( -// Equation(s): -// \z80_|alu_|db_high[3]~27_combout = ((\z80_|bus_control_|db[4]~19_combout & (\z80_|bus_control_|db[5]~15_combout & \z80_|bus_control_|db[3]~21_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datab(\z80_|bus_control_|db[4]~19_combout ), - .datac(\z80_|bus_control_|db[5]~15_combout ), - .datad(\z80_|bus_control_|db[3]~21_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~27 .lut_mask = 16'hD555; -defparam \z80_|alu_|db_high[3]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N6 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~7 ( -// Equation(s): -// \z80_|alu_|db_high[3]~7_combout = (\z80_|alu_|db_high[3]~4_combout & (\z80_|alu_|db_high[3]~27_combout & ((\z80_|alu_|db_high[3]~6_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) - - .dataa(\z80_|alu_|db_high[3]~6_combout ), - .datab(\z80_|alu_|db_high[3]~4_combout ), - .datac(\z80_|alu_|db_high[3]~27_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~7 .lut_mask = 16'h80C0; -defparam \z80_|alu_|db_high[3]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N28 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~8 ( -// Equation(s): -// \z80_|alu_|db_high[3]~8_combout = ((\z80_|alu_|db_high[3]~7_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) # (!\z80_|alu_|db_high[3]~3_combout ) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), - .datab(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datac(\z80_|alu_|db_high[3]~7_combout ), - .datad(\z80_|alu_|db_high[3]~3_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~8 .lut_mask = 16'hE0FF; -defparam \z80_|alu_|db_high[3]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N14 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & ((\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_low~combout & \z80_|alu_|db_high[3]~8_combout )))) - - .dataa(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .datac(\z80_|alu_|db_high[3]~8_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4 .lut_mask = 16'h00EA; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y10_N15 -dffeas \z80_|alu_|op1_low[3] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_low [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_low[3] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_low[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N0 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~9 ( -// Equation(s): -// \z80_|alu_|db_low[3]~9_combout = (\z80_|alu_|op1_low [3] & (((\z80_|alu_|op2_low [3]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|alu_|op1_low [3] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_low [3]) # -// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) - - .dataa(\z80_|alu_|op1_low [3]), - .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datac(\z80_|alu_|op2_low [3]), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~9 .lut_mask = 16'hB0BB; -defparam \z80_|alu_|db_low[3]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N10 -cycloneive_lcell_comb \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 ( -// Equation(s): -// \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout = (\z80_|bus_control_|db[4]~19_combout & \z80_|bus_control_|db[3]~21_combout ) - - .dataa(gnd), - .datab(\z80_|bus_control_|db[4]~19_combout ), - .datac(gnd), - .datad(\z80_|bus_control_|db[3]~21_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 .lut_mask = 16'hCC00; -defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N24 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~10 ( -// Equation(s): -// \z80_|alu_|db_low[3]~10_combout = (\z80_|alu_|db_low[3]~9_combout & (((!\z80_|bus_control_|db[5]~15_combout & \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout )) # (!\z80_|execute_|ctl_alu_bs_oe~combout ))) - - .dataa(\z80_|bus_control_|db[5]~15_combout ), - .datab(\z80_|alu_|db_low[3]~9_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datad(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~10 .lut_mask = 16'h4C0C; -defparam \z80_|alu_|db_low[3]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y10_N15 -dffeas \z80_|alu_|result_lo[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_alu_op_low~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|result_lo [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|result_lo[3] .is_wysiwyg = "true"; -defparam \z80_|alu_|result_lo[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N14 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~7 ( -// Equation(s): -// \z80_|alu_|db_low[3]~7_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[4]~17_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[2]~15_combout ))) - - .dataa(\z80_|alu_|db[4]~17_combout ), - .datab(gnd), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|alu_|db[2]~15_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~7 .lut_mask = 16'hAFA0; -defparam \z80_|alu_|db_low[3]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N28 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~8 ( -// Equation(s): -// \z80_|alu_|db_low[3]~8_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_low[3]~7_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[3]~11_combout ))) # -// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) - - .dataa(\z80_|alu_|db[3]~11_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datac(\z80_|alu_|db_low[3]~7_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~8 .lut_mask = 16'hF3BB; -defparam \z80_|alu_|db_low[3]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N8 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~11 ( -// Equation(s): -// \z80_|alu_|db_low[3]~11_combout = (\z80_|alu_|db_low[3]~10_combout & (\z80_|alu_|db_low[3]~8_combout & ((\z80_|alu_|result_lo [3]) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) - - .dataa(\z80_|alu_|db_low[3]~10_combout ), - .datab(\z80_|alu_|result_lo [3]), - .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datad(\z80_|alu_|db_low[3]~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~11 .lut_mask = 16'hA800; -defparam \z80_|alu_|db_low[3]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N6 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~25 ( -// Equation(s): -// \z80_|alu_|db_low[3]~25_combout = (\z80_|alu_|db_low[3]~11_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~43_combout & !\z80_|alu_|db_high[3]~2_combout )) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datab(\z80_|alu_|db_high[3]~2_combout ), - .datac(\z80_|alu_|db_low[3]~11_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~25 .lut_mask = 16'hF1F1; -defparam \z80_|alu_|db_low[3]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N12 -cycloneive_lcell_comb \z80_|alu_|db[3]~10 ( -// Equation(s): -// \z80_|alu_|db[3]~10_combout = (\z80_|execute_|ctl_alu_oe~14_combout & (\z80_|alu_|db_low[3]~25_combout & ((\z80_|reg_file_|gdfx_temp1[3]~48_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) # (!\z80_|execute_|ctl_alu_oe~14_combout & -// (((\z80_|reg_file_|gdfx_temp1[3]~48_combout )) # (!\z80_|execute_|ctl_reg_out_hi~7_combout ))) - - .dataa(\z80_|execute_|ctl_alu_oe~14_combout ), - .datab(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .datad(\z80_|alu_|db_low[3]~25_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[3]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[3]~10 .lut_mask = 16'hF351; -defparam \z80_|alu_|db[3]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N12 -cycloneive_lcell_comb \z80_|alu_|db[3]~11 ( -// Equation(s): -// \z80_|alu_|db[3]~11_combout = ((\z80_|alu_|db[3]~10_combout & ((\z80_|alu_control_|db[3]~35_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|alu_|db[7]~26_combout ) - - .dataa(\z80_|alu_|db[3]~10_combout ), - .datab(\z80_|execute_|ctl_sw_2d~13_combout ), - .datac(\z80_|alu_control_|db[3]~35_combout ), - .datad(\z80_|alu_|db[7]~26_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[3]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[3]~11 .lut_mask = 16'hA2FF; -defparam \z80_|alu_|db[3]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~7 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~7_combout = (((\z80_|nM1_int~2_combout & \z80_|execute_|ctl_alu_oe~3_combout )) # (!\z80_|execute_|ctl_reg_out_hi~6_combout )) # (!\z80_|execute_|ctl_alu_oe~9_combout ) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_alu_oe~3_combout ), - .datac(\z80_|execute_|ctl_alu_oe~9_combout ), - .datad(\z80_|execute_|ctl_reg_out_hi~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~7 .lut_mask = 16'h8FFF; -defparam \z80_|execute_|ctl_sw_2u~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|setM1~49 ( -// Equation(s): -// \z80_|execute_|setM1~49_combout = (\z80_|execute_|setM1~48_combout & (!\z80_|pla_decode_|Equal52~1_combout & ((!\z80_|pla_decode_|Equal63~0_combout ) # (!\z80_|pla_decode_|Equal3~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal3~0_combout ), - .datab(\z80_|pla_decode_|Equal63~0_combout ), - .datac(\z80_|execute_|setM1~48_combout ), - .datad(\z80_|pla_decode_|Equal52~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~49 .lut_mask = 16'h0070; -defparam \z80_|execute_|setM1~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_oe~2_combout = (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_state_alu~14_combout ) # ((!\z80_|execute_|ctl_flags_oe~1_combout ) # (!\z80_|execute_|setM1~49_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~14_combout ), - .datab(\z80_|execute_|setM1~49_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|execute_|ctl_flags_oe~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_oe~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_oe~2 .lut_mask = 16'h0B0F; -defparam \z80_|execute_|ctl_flags_oe~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N30 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_35 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout = (\z80_|alu_|db_low[3]~25_combout & ((\z80_|execute_|ctl_flags_alu~15_combout ) # ((\z80_|alu_control_|db[3]~35_combout & \z80_|execute_|ctl_flags_bus~combout )))) # (!\z80_|alu_|db_low[3]~25_combout & -// (\z80_|alu_control_|db[3]~35_combout & (\z80_|execute_|ctl_flags_bus~combout ))) - - .dataa(\z80_|alu_|db_low[3]~25_combout ), - .datab(\z80_|alu_control_|db[3]~35_combout ), - .datac(\z80_|execute_|ctl_flags_bus~combout ), - .datad(\z80_|execute_|ctl_flags_alu~15_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_35 .lut_mask = 16'hEAC0; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~7_combout = (\z80_|execute_|ctl_flags_xy_we~12_combout & !\z80_|execute_|ctl_flags_sz_we~6_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_flags_xy_we~12_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_flags_sz_we~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~7 .lut_mask = 16'h00CC; -defparam \z80_|execute_|ctl_flags_sz_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout = (\z80_|pla_decode_|Equal56~0_combout & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T2_ff~q )) - - .dataa(\z80_|pla_decode_|Equal56~0_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3 .lut_mask = 16'h8080; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~13 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~13_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ) # ((\z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ) # -// (!\z80_|execute_|ctl_flags_xy_we~10_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ), - .datab(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), - .datad(\z80_|execute_|ctl_flags_xy_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~13 .lut_mask = 16'hFEFF; -defparam \z80_|execute_|ctl_flags_xy_we~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~14 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~14_combout = (((\z80_|execute_|ctl_flags_xy_we~13_combout ) # (!\z80_|execute_|ctl_flags_xy_we~7_combout )) # (!\z80_|execute_|ctl_flags_xy_we~9_combout )) # (!\z80_|execute_|ctl_flags_xy_we~16_combout ) - - .dataa(\z80_|execute_|ctl_flags_xy_we~16_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~9_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~13_combout ), - .datad(\z80_|execute_|ctl_flags_xy_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~14 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|ctl_flags_xy_we~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~15 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~15_combout = (((\z80_|execute_|ctl_flags_xy_we~14_combout ) # (!\z80_|execute_|ctl_flags_pf_we~4_combout )) # (!\z80_|execute_|ctl_flags_sz_we~7_combout )) # (!\z80_|execute_|ctl_pf_sel[0]~3_combout ) - - .dataa(\z80_|execute_|ctl_pf_sel[0]~3_combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~7_combout ), - .datac(\z80_|execute_|ctl_flags_pf_we~4_combout ), - .datad(\z80_|execute_|ctl_flags_xy_we~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~15 .lut_mask = 16'hFF7F; -defparam \z80_|execute_|ctl_flags_xy_we~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y11_N31 -dffeas \z80_|alu_flags_|flags_xf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_flags_xy_we~15_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|flags_xf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_xf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|flags_xf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N8 -cycloneive_lcell_comb \z80_|alu_control_|db[3]~33 ( -// Equation(s): -// \z80_|alu_control_|db[3]~33_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & ((\z80_|alu_flags_|flags_xf~q ) # (!\z80_|execute_|ctl_flags_oe~2_combout ))) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_flags_oe~2_combout ), - .datac(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .datad(\z80_|alu_flags_|flags_xf~q ), - .cin(gnd), - .combout(\z80_|alu_control_|db[3]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[3]~33 .lut_mask = 16'hF030; -defparam \z80_|alu_control_|db[3]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~3_combout = (\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ) # ((\z80_|execute_|ctl_reg_out_lo~2_combout & \z80_|execute_|rsel3~combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), - .datab(\z80_|execute_|ctl_reg_out_lo~2_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), - .datad(\z80_|execute_|rsel3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~3 .lut_mask = 16'hFEFA; -defparam \z80_|execute_|ctl_reg_out_lo~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout = (\z80_|pla_decode_|Equal1~7_combout & (\z80_|execute_|ixy_d~7_combout & (!\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal3~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~7_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal3~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~4_combout = (\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ) # ((\z80_|execute_|ixy_d~9_combout & ((\z80_|pla_decode_|Equal40~1_combout ) # (\z80_|pla_decode_|Equal39~0_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ), - .datab(\z80_|pla_decode_|Equal40~1_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~4 .lut_mask = 16'hFAEA; -defparam \z80_|execute_|ctl_reg_out_lo~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~5_combout = (\z80_|execute_|ctl_reg_out_lo~3_combout ) # (((\z80_|execute_|ctl_reg_out_lo~4_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout )) # (!\z80_|execute_|ctl_reg_out_lo~9_combout )) - - .dataa(\z80_|execute_|ctl_reg_out_lo~3_combout ), - .datab(\z80_|execute_|ctl_reg_out_lo~9_combout ), - .datac(\z80_|execute_|ctl_reg_out_lo~4_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~5 .lut_mask = 16'hFBFF; -defparam \z80_|execute_|ctl_reg_out_lo~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~8_combout = ((\z80_|execute_|ctl_reg_out_lo~5_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout )) # (!\z80_|execute_|ctl_reg_out_lo~7_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), - .datad(\z80_|execute_|ctl_reg_out_lo~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~8 .lut_mask = 16'hFF3F; -defparam \z80_|execute_|ctl_reg_out_lo~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N16 -cycloneive_lcell_comb \z80_|sw1_|db_down[3]~1 ( -// Equation(s): -// \z80_|sw1_|db_down[3]~1_combout = (\z80_|bus_control_|db[3]~21_combout ) # ((\z80_|execute_|ctl_sw_1d~6_combout & ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|execute_|ctl_66_oe~2_combout )))) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|execute_|ctl_sw_1d~6_combout ), - .datac(\z80_|execute_|ctl_66_oe~2_combout ), - .datad(\z80_|bus_control_|db[3]~21_combout ), - .cin(gnd), - .combout(\z80_|sw1_|db_down[3]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sw1_|db_down[3]~1 .lut_mask = 16'hFF8C; -defparam \z80_|sw1_|db_down[3]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N10 -cycloneive_lcell_comb \z80_|alu_control_|db[3]~34 ( -// Equation(s): -// \z80_|alu_control_|db[3]~34_combout = (\z80_|alu_control_|db[3]~33_combout & (\z80_|sw1_|db_down[3]~1_combout & ((\z80_|reg_file_|gdfx_temp0[3]~52_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .datab(\z80_|alu_control_|db[3]~33_combout ), - .datac(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datad(\z80_|sw1_|db_down[3]~1_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[3]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[3]~34 .lut_mask = 16'h8C00; -defparam \z80_|alu_control_|db[3]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N0 -cycloneive_lcell_comb \z80_|alu_control_|db[3]~35 ( -// Equation(s): -// \z80_|alu_control_|db[3]~35_combout = ((\z80_|alu_control_|db[3]~34_combout & ((\z80_|alu_|db[3]~11_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|alu_|db[3]~11_combout ), - .datab(\z80_|alu_control_|db[6]~11_combout ), - .datac(\z80_|execute_|ctl_sw_2u~7_combout ), - .datad(\z80_|alu_control_|db[3]~34_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[3]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[3]~35 .lut_mask = 16'hBF33; -defparam \z80_|alu_control_|db[3]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~46 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~46_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [3] & ((\z80_|alu_control_|db[3]~35_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (((\z80_|alu_control_|db[3]~35_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [3]), - .datad(\z80_|alu_control_|db[3]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~46 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[3]~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~47 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~47_combout = (\z80_|reg_file_|gdfx_temp0[3]~46_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(\z80_|reg_file_|b2v_latch_wz_lo|latch [3]), - .datab(gnd), - .datac(\z80_|reg_file_|gdfx_temp0[3]~46_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~47 .lut_mask = 16'hA0F0; -defparam \z80_|reg_file_|gdfx_temp0[3]~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~50 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~50_combout = (\z80_|reg_file_|gdfx_temp0[3]~48_combout & (\z80_|reg_file_|gdfx_temp0[3]~49_combout & \z80_|reg_file_|gdfx_temp0[3]~47_combout )) - - .dataa(gnd), - .datab(\z80_|reg_file_|gdfx_temp0[3]~48_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[3]~49_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[3]~47_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~50 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|gdfx_temp0[3]~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y9_N31 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y9_N5 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~44 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~44_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [3] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [3] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [3]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~44 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[3]~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y13_N7 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y13_N5 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~43 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~43_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [3] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [3] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [3]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~43 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[3]~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~51 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~51_combout = (\z80_|reg_file_|gdfx_temp0[3]~45_combout & (\z80_|reg_file_|gdfx_temp0[3]~50_combout & (\z80_|reg_file_|gdfx_temp0[3]~44_combout & \z80_|reg_file_|gdfx_temp0[3]~43_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[3]~45_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[3]~50_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[3]~44_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[3]~43_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~51 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[3]~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~52 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~52_combout = ((\z80_|reg_file_|gdfx_temp0[3]~51_combout & ((\z80_|reg_file_|db_lo_as[3]~12_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[3]~12_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~52 .lut_mask = 16'h8FCF; -defparam \z80_|reg_file_|gdfx_temp0[3]~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N13 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[3]~12_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N12 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~10 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[3]~10_combout = (\z80_|reg_file_|gdfx_temp0[3]~52_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) # (!\z80_|reg_file_|gdfx_temp0[3]~52_combout & -// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [3]), - .datad(\z80_|execute_|ctl_sw_4d~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[3]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[3]~10 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_lo_as[3]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y17_N3 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[3]~12_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N20 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~11 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[3]~11_combout = (\z80_|reg_file_|db_lo_as[3]~10_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(\z80_|reg_file_|db_lo_as[3]~10_combout ), - .datab(gnd), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [3]), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[3]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[3]~11 .lut_mask = 16'hAA0A; -defparam \z80_|reg_file_|db_lo_as[3]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N2 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~12 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[3]~12_combout = ((\z80_|reg_file_|db_lo_as[3]~11_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datad(\z80_|reg_file_|db_lo_as[3]~11_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[3]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[3]~12 .lut_mask = 16'hBF0F; -defparam \z80_|reg_file_|db_lo_as[3]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N2 -cycloneive_lcell_comb \z80_|address_latch_|abusz[3] ( -// Equation(s): -// \z80_|address_latch_|abusz [3] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[3]~12_combout ) - - .dataa(gnd), - .datab(\z80_|resets_|clrpc~0_combout ), - .datac(\z80_|reg_file_|db_lo_as[3]~12_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [3]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[3] .lut_mask = 16'h3030; -defparam \z80_|address_latch_|abusz[3] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y17_N17 -dffeas \z80_|address_latch_|Q[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|address_latch_|abusz [3]), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[3] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N20 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout = \z80_|address_latch_|Q [3] $ (((\z80_|execute_|ctl_inc_dec~10_combout ) # ((!\z80_|execute_|ctl_inc_dec~5_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) - - .dataa(\z80_|execute_|ctl_inc_dec~10_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .datac(\z80_|execute_|ctl_inc_dec~5_combout ), - .datad(\z80_|address_latch_|Q [3]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4 .lut_mask = 16'h40BF; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N6 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout & -// (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout ))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ), - .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 .lut_mask = 16'h8000; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N12 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout = \z80_|address_latch_|Q [4] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout & -// (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout )))) - - .dataa(\z80_|address_latch_|Q [4]), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ), - .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out .lut_mask = 16'h6AAA; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y13_N27 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y13_N9 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~53 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~53_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [4] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [4] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [4]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~53_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~53 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[4]~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~54 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~54_combout = (\z80_|reg_file_|gdfx_temp0[4]~53_combout & ((\z80_|alu_control_|db[4]~32_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) - - .dataa(\z80_|alu_control_|db[4]~32_combout ), - .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[4]~53_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~54_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~54 .lut_mask = 16'hBB00; -defparam \z80_|reg_file_|gdfx_temp0[4]~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N27 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y10_N1 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~58 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~58_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~58_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~58 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[4]~58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y11_N31 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y11_N23 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y11_N21 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~59 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~59_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_bc_lo|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~59_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~59 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[4]~59 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~60 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~60_combout = (\z80_|reg_file_|gdfx_temp0[4]~58_combout & (\z80_|reg_file_|gdfx_temp0[4]~59_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[4]~58_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [4]), - .datad(\z80_|reg_file_|gdfx_temp0[4]~59_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~60_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~60 .lut_mask = 16'hA200; -defparam \z80_|reg_file_|gdfx_temp0[4]~60 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y9_N21 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y9_N11 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~57 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~57_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (\z80_|reg_file_|b2v_latch_hl2_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (((\z80_|reg_file_|b2v_latch_hl_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~57_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~57 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[4]~57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y10_N1 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y10_N7 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~55 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~55_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datac(\z80_|reg_file_|b2v_latch_iy_lo|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_sp_lo|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~55_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~55 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[4]~55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y11_N21 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~56 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~56_combout = (\z80_|reg_file_|gdfx_temp0[4]~55_combout & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[4]~55_combout ), - .datab(gnd), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~56_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~56 .lut_mask = 16'hA0AA; -defparam \z80_|reg_file_|gdfx_temp0[4]~56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~61 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~61_combout = (\z80_|reg_file_|gdfx_temp0[4]~54_combout & (\z80_|reg_file_|gdfx_temp0[4]~60_combout & (\z80_|reg_file_|gdfx_temp0[4]~57_combout & \z80_|reg_file_|gdfx_temp0[4]~56_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[4]~54_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[4]~60_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[4]~57_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[4]~56_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~61 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[4]~61 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~62 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~62_combout = ((\z80_|reg_file_|gdfx_temp0[4]~61_combout & ((\z80_|reg_file_|db_lo_as[4]~15_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .datac(\z80_|reg_file_|db_lo_as[4]~15_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~62 .lut_mask = 16'hB3BB; -defparam \z80_|reg_file_|gdfx_temp0[4]~62 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N7 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[4]~15_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N6 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~13 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[4]~13_combout = (\z80_|reg_file_|gdfx_temp0[4]~62_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # (!\z80_|reg_file_|gdfx_temp0[4]~62_combout & -// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .datab(\z80_|execute_|ctl_sw_4d~6_combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[4]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[4]~13 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|db_lo_as[4]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y17_N7 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[4]~15_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N12 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~14 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[4]~14_combout = (\z80_|reg_file_|db_lo_as[4]~13_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|db_lo_as[4]~13_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[4]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[4]~14 .lut_mask = 16'hCC0C; -defparam \z80_|reg_file_|db_lo_as[4]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N6 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~15 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[4]~15_combout = ((\z80_|reg_file_|db_lo_as[4]~14_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datad(\z80_|reg_file_|db_lo_as[4]~14_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[4]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[4]~15 .lut_mask = 16'hBF0F; -defparam \z80_|reg_file_|db_lo_as[4]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N16 -cycloneive_lcell_comb \z80_|address_latch_|abusz[4] ( -// Equation(s): -// \z80_|address_latch_|abusz [4] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[4]~15_combout ) - - .dataa(gnd), - .datab(\z80_|resets_|clrpc~0_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|db_lo_as[4]~15_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [4]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[4] .lut_mask = 16'h3300; -defparam \z80_|address_latch_|abusz[4] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y17_N23 -dffeas \z80_|address_latch_|Q[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|address_latch_|abusz [4]), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[4] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N22 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout = \z80_|address_latch_|Q [4] $ (((\z80_|execute_|ctl_inc_dec~9_combout ) # ((\z80_|execute_|ctl_inc_dec~7_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout )))) - - .dataa(\z80_|execute_|ctl_inc_dec~9_combout ), - .datab(\z80_|execute_|ctl_inc_dec~6_combout ), - .datac(\z80_|address_latch_|Q [4]), - .datad(\z80_|execute_|ctl_inc_dec~7_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 .lut_mask = 16'h0F4B; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N28 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout = \z80_|address_latch_|Q [5] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout & \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout -// ))) - - .dataa(\z80_|address_latch_|Q [5]), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out .lut_mask = 16'h6A6A; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y9_N23 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y9_N13 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~64 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~64_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [5] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [5] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [5]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~64_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~64 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[5]~64 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y9_N21 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y9_N23 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~63 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~63_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (\z80_|reg_file_|b2v_latch_de2_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_de_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & ((\z80_|reg_file_|b2v_latch_de_lo|latch [5]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datab(\z80_|reg_file_|b2v_latch_de_lo|latch [5]), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~63_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~63 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[5]~63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y11_N9 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y11_N5 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~66 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~66_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [5] & ((\z80_|alu_control_|db[5]~15_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (((\z80_|alu_control_|db[5]~15_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [5]), - .datad(\z80_|alu_control_|db[5]~15_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~66_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~66 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[5]~66 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~67 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~67_combout = (\z80_|reg_file_|gdfx_temp0[5]~66_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [5]), - .datad(\z80_|reg_file_|gdfx_temp0[5]~66_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~67_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~67 .lut_mask = 16'hF300; -defparam \z80_|reg_file_|gdfx_temp0[5]~67 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N31 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y10_N17 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~65 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~65_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [5]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [5]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~65_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~65 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[5]~65 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y10_N31 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N28 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder_combout = \z80_|reg_file_|gdfx_temp0[5]~72_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y10_N29 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~69 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~69_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [5]), - .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [5]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~69_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~69 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[5]~69 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N6 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder_combout = \z80_|reg_file_|gdfx_temp0[5]~72_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y11_N7 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y11_N3 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~68 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~68_combout = (\z80_|reg_file_|b2v_latch_ix_lo|latch [5] & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # (!\z80_|reg_file_|b2v_latch_ix_lo|latch [5] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_ix_lo|latch [5]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc_lo|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~68_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~68 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[5]~68 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~70 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~70_combout = (\z80_|reg_file_|gdfx_temp0[5]~67_combout & (\z80_|reg_file_|gdfx_temp0[5]~65_combout & (\z80_|reg_file_|gdfx_temp0[5]~69_combout & \z80_|reg_file_|gdfx_temp0[5]~68_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[5]~67_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[5]~65_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[5]~69_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[5]~68_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~70_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~70 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[5]~70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~71 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~71_combout = (\z80_|reg_file_|gdfx_temp0[5]~64_combout & (\z80_|reg_file_|gdfx_temp0[5]~63_combout & \z80_|reg_file_|gdfx_temp0[5]~70_combout )) - - .dataa(\z80_|reg_file_|gdfx_temp0[5]~64_combout ), - .datab(gnd), - .datac(\z80_|reg_file_|gdfx_temp0[5]~63_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[5]~70_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~71 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|gdfx_temp0[5]~71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~72 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~72_combout = ((\z80_|reg_file_|gdfx_temp0[5]~71_combout & ((\z80_|reg_file_|db_lo_as[5]~18_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .datab(\z80_|reg_file_|db_lo_as[5]~18_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~72 .lut_mask = 16'hD5F5; -defparam \z80_|reg_file_|gdfx_temp0[5]~72 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N5 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[5]~18_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N4 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~16 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[5]~16_combout = (\z80_|reg_file_|gdfx_temp0[5]~72_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # (!\z80_|reg_file_|gdfx_temp0[5]~72_combout & -// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .datab(\z80_|execute_|ctl_sw_4d~6_combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[5]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[5]~16 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|db_lo_as[5]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y15_N25 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[5]~18_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N2 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~17 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[5]~17_combout = (\z80_|reg_file_|db_lo_as[5]~16_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datab(gnd), - .datac(\z80_|reg_file_|db_lo_as[5]~16_combout ), - .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [5]), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[5]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[5]~17 .lut_mask = 16'hF050; -defparam \z80_|reg_file_|db_lo_as[5]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N24 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~18 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[5]~18_combout = ((\z80_|reg_file_|db_lo_as[5]~17_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datad(\z80_|reg_file_|db_lo_as[5]~17_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[5]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[5]~18 .lut_mask = 16'hBF0F; -defparam \z80_|reg_file_|db_lo_as[5]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N26 -cycloneive_lcell_comb \z80_|address_latch_|abusz[5] ( -// Equation(s): -// \z80_|address_latch_|abusz [5] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[5]~18_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(\z80_|reg_file_|db_lo_as[5]~18_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [5]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[5] .lut_mask = 16'h0F00; -defparam \z80_|address_latch_|abusz[5] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y16_N27 -dffeas \z80_|address_latch_|Q[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [5]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[5] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N26 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout = \z80_|address_latch_|Q [5] $ ((((\z80_|execute_|ctl_inc_dec~10_combout ) # (!\z80_|execute_|ctl_inc_dec~5_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout ))) - - .dataa(\z80_|address_latch_|Q [5]), - .datab(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .datac(\z80_|execute_|ctl_inc_dec~5_combout ), - .datad(\z80_|execute_|ctl_inc_dec~10_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4 .lut_mask = 16'h5595; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N16 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[6] ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|address [6] = \z80_|address_latch_|Q [6] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout & -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout )))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|address_latch_|Q [6]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[6] .lut_mask = 16'h78F0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[6] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y17_N11 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[6]~21_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y9_N17 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N6 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder_combout = \z80_|reg_file_|gdfx_temp0[6]~82_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y9_N7 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~74 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~74_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (\z80_|reg_file_|b2v_latch_hl2_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (((\z80_|reg_file_|b2v_latch_hl_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~74_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~74 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[6]~74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y9_N19 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y9_N5 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~73 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~73_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (\z80_|reg_file_|b2v_latch_de2_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_de_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & ((\z80_|reg_file_|b2v_latch_de_lo|latch [6]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datab(\z80_|reg_file_|b2v_latch_de_lo|latch [6]), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~73_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~73 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[6]~73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y10_N19 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N2 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder_combout = \z80_|reg_file_|gdfx_temp0[6]~82_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y10_N3 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~78 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~78_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~78_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~78 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[6]~78 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N29 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~79 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~79_combout = (\z80_|reg_file_|b2v_latch_sp_lo|latch [6] & (((\z80_|alu_control_|db[6]~22_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) # (!\z80_|reg_file_|b2v_latch_sp_lo|latch [6] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|alu_control_|db[6]~22_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_sp_lo|latch [6]), - .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datac(\z80_|alu_control_|db[6]~22_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~79_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~79 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[6]~79 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y10_N17 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N16 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder_combout = \z80_|reg_file_|gdfx_temp0[6]~82_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y11_N17 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y11_N19 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~76 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~76_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [6]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [6]), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~76_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~76 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[6]~76 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~77 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~77_combout = (\z80_|reg_file_|gdfx_temp0[6]~76_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [6]), - .datad(\z80_|reg_file_|gdfx_temp0[6]~76_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~77_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~77 .lut_mask = 16'hF300; -defparam \z80_|reg_file_|gdfx_temp0[6]~77 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~80 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~80_combout = (\z80_|reg_file_|gdfx_temp0[6]~78_combout & (\z80_|reg_file_|gdfx_temp0[6]~79_combout & \z80_|reg_file_|gdfx_temp0[6]~77_combout )) - - .dataa(gnd), - .datab(\z80_|reg_file_|gdfx_temp0[6]~78_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[6]~79_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[6]~77_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~80 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|gdfx_temp0[6]~80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N5 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y14_N25 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~75 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~75_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~75_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~75 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[6]~75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~81 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~81_combout = (\z80_|reg_file_|gdfx_temp0[6]~74_combout & (\z80_|reg_file_|gdfx_temp0[6]~73_combout & (\z80_|reg_file_|gdfx_temp0[6]~80_combout & \z80_|reg_file_|gdfx_temp0[6]~75_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[6]~74_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[6]~73_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[6]~75_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~81_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~81 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[6]~81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~82 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~82_combout = ((\z80_|reg_file_|gdfx_temp0[6]~81_combout & ((\z80_|reg_file_|db_lo_as[6]~21_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp0[6]~81_combout ), - .datab(\z80_|reg_file_|db_lo_as[6]~21_combout ), - .datac(\z80_|execute_|ctl_sw_4u~6_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~82 .lut_mask = 16'h8AFF; -defparam \z80_|reg_file_|gdfx_temp0[6]~82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N19 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[6]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N18 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~19 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[6]~19_combout = (\z80_|reg_file_|gdfx_temp0[6]~82_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # (!\z80_|reg_file_|gdfx_temp0[6]~82_combout & -// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .datab(\z80_|execute_|ctl_sw_4d~6_combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[6]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[6]~19 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|db_lo_as[6]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N16 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~20 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[6]~20_combout = (\z80_|reg_file_|db_lo_as[6]~19_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_lo|latch [6]), - .datad(\z80_|reg_file_|db_lo_as[6]~19_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[6]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[6]~20 .lut_mask = 16'hF300; -defparam \z80_|reg_file_|db_lo_as[6]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N10 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~21 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[6]~21_combout = ((\z80_|reg_file_|db_lo_as[6]~20_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [6]) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), - .datac(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datad(\z80_|reg_file_|db_lo_as[6]~20_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[6]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[6]~21 .lut_mask = 16'hDF55; -defparam \z80_|reg_file_|db_lo_as[6]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N22 -cycloneive_lcell_comb \z80_|address_latch_|abusz[6] ( -// Equation(s): -// \z80_|address_latch_|abusz [6] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[6]~21_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(\z80_|reg_file_|db_lo_as[6]~21_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [6]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[6] .lut_mask = 16'h0F00; -defparam \z80_|address_latch_|abusz[6] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y16_N23 -dffeas \z80_|address_latch_|Q[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [6]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[6] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N6 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout = (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|address_latch_|Q [6] $ (((\z80_|execute_|ctl_inc_dec~10_combout ) # (\z80_|execute_|ctl_inc_dec~7_combout ))))) - - .dataa(\z80_|execute_|ctl_inc_dec~10_combout ), - .datab(\z80_|execute_|ctl_inc_dec~7_combout ), - .datac(\z80_|address_latch_|Q [6]), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 .lut_mask = 16'h001E; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N0 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout & -// (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout ))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 .lut_mask = 16'h8000; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N24 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout = \z80_|address_latch_|Q [7] $ (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ) - - .dataa(\z80_|address_latch_|Q [7]), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out .lut_mask = 16'h55AA; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N24 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~24 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[7]~24_combout = ((\z80_|reg_file_|db_lo_as[7]~23_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|reg_file_|db_lo_as[7]~23_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[7]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[7]~24 .lut_mask = 16'hF575; -defparam \z80_|reg_file_|db_lo_as[7]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y9_N25 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y9_N11 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~83 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~83_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (\z80_|reg_file_|b2v_latch_de2_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_de_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & ((\z80_|reg_file_|b2v_latch_de_lo|latch [7]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datab(\z80_|reg_file_|b2v_latch_de_lo|latch [7]), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~83_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~83 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[7]~83 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y9_N29 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y9_N19 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~84 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~84_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (\z80_|reg_file_|b2v_latch_hl2_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (((\z80_|reg_file_|b2v_latch_hl_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~84_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~84 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[7]~84 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y10_N11 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N12 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder_combout = \z80_|reg_file_|gdfx_temp0[7]~92_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y10_N13 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~88 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~88_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~88_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~88 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[7]~88 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y10_N21 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y11_N9 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y11_N7 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~86 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~86_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [7]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [7]), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~86_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~86 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[7]~86 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~87 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~87_combout = (\z80_|reg_file_|gdfx_temp0[7]~86_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [7]), - .datad(\z80_|reg_file_|gdfx_temp0[7]~86_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~87_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~87 .lut_mask = 16'hF300; -defparam \z80_|reg_file_|gdfx_temp0[7]~87 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N25 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y10_N19 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~85 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~85_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~85_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~85 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[7]~85 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N15 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~89 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~89_combout = (\z80_|reg_file_|b2v_latch_sp_lo|latch [7] & (((\z80_|alu_control_|db[7]~18_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) # (!\z80_|reg_file_|b2v_latch_sp_lo|latch [7] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|alu_control_|db[7]~18_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_sp_lo|latch [7]), - .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datac(\z80_|alu_control_|db[7]~18_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~89_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~89 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[7]~89 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~90 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~90_combout = (\z80_|reg_file_|gdfx_temp0[7]~88_combout & (\z80_|reg_file_|gdfx_temp0[7]~87_combout & (\z80_|reg_file_|gdfx_temp0[7]~85_combout & \z80_|reg_file_|gdfx_temp0[7]~89_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[7]~88_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[7]~87_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[7]~85_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[7]~89_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~90 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[7]~90 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~91 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~91_combout = (\z80_|reg_file_|gdfx_temp0[7]~83_combout & (\z80_|reg_file_|gdfx_temp0[7]~84_combout & \z80_|reg_file_|gdfx_temp0[7]~90_combout )) - - .dataa(\z80_|reg_file_|gdfx_temp0[7]~83_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[7]~84_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~91 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|gdfx_temp0[7]~91 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~92 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~92_combout = ((\z80_|reg_file_|gdfx_temp0[7]~91_combout & ((\z80_|reg_file_|db_lo_as[7]~24_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[7]~24_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), - .datac(\z80_|execute_|ctl_sw_4u~6_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~92 .lut_mask = 16'h8CFF; -defparam \z80_|reg_file_|gdfx_temp0[7]~92 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N6 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[7]~0 ( -// Equation(s): -// \z80_|reg_file_|db_lo_ds[7]~0_combout = (\z80_|reg_file_|gdfx_temp0[7]~92_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout & (\z80_|execute_|ctl_reg_out_lo~7_combout & !\z80_|execute_|ctl_reg_out_lo~5_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), - .datab(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .datad(\z80_|execute_|ctl_reg_out_lo~5_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_ds[7]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_ds[7]~0 .lut_mask = 16'hF0F8; -defparam \z80_|reg_file_|db_lo_ds[7]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y10_N11 -dffeas \z80_|interrupts_|im2 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_im_we~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|interrupts_|im2~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|interrupts_|im2 .is_wysiwyg = "true"; -defparam \z80_|interrupts_|im2 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~12 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~12_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|interrupts_|im2~q & \z80_|interrupts_|DFFE_inst44~q )) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(gnd), - .datac(\z80_|interrupts_|im2~q ), - .datad(\z80_|interrupts_|DFFE_inst44~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~12 .lut_mask = 16'h5000; -defparam \z80_|execute_|ctl_mRead~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_mask543_en~0 ( -// Equation(s): -// \z80_|execute_|ctl_sw_mask543_en~0_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (!\z80_|execute_|ctl_mRead~12_combout & \z80_|pla_decode_|Equal47~0_combout ))) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|execute_|ctl_mRead~12_combout ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_mask543_en~0 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_sw_mask543_en~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N12 -cycloneive_lcell_comb \z80_|alu_control_|db[7]~17 ( -// Equation(s): -// \z80_|alu_control_|db[7]~17_combout = (\z80_|reg_file_|db_lo_ds[7]~0_combout & (((!\z80_|execute_|ctl_sw_mask543_en~0_combout & \z80_|bus_control_|db[7]~7_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) - - .dataa(\z80_|reg_file_|db_lo_ds[7]~0_combout ), - .datab(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .datac(\z80_|execute_|ctl_sw_1d~7_combout ), - .datad(\z80_|bus_control_|db[7]~7_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[7]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[7]~17 .lut_mask = 16'h2A0A; -defparam \z80_|alu_control_|db[7]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N16 -cycloneive_lcell_comb \z80_|alu_control_|db[7]~16 ( -// Equation(s): -// \z80_|alu_control_|db[7]~16_combout = (\z80_|execute_|ctl_flags_oe~2_combout & (((\z80_|execute_|ctl_sw_2u~7_combout & !\z80_|alu_|db[7]~21_combout )) # (!\z80_|alu_flags_|DFFE_inst_latch_sf~q ))) # (!\z80_|execute_|ctl_flags_oe~2_combout & -// (\z80_|execute_|ctl_sw_2u~7_combout & (!\z80_|alu_|db[7]~21_combout ))) - - .dataa(\z80_|execute_|ctl_flags_oe~2_combout ), - .datab(\z80_|execute_|ctl_sw_2u~7_combout ), - .datac(\z80_|alu_|db[7]~21_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), - .cin(gnd), - .combout(\z80_|alu_control_|db[7]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[7]~16 .lut_mask = 16'h0CAE; -defparam \z80_|alu_control_|db[7]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N14 -cycloneive_lcell_comb \z80_|alu_control_|db[7]~18 ( -// Equation(s): -// \z80_|alu_control_|db[7]~18_combout = ((\z80_|alu_control_|db[7]~17_combout & (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & !\z80_|alu_control_|db[7]~16_combout ))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|alu_control_|db[7]~17_combout ), - .datab(\z80_|alu_control_|db[6]~11_combout ), - .datac(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .datad(\z80_|alu_control_|db[7]~16_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[7]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[7]~18 .lut_mask = 16'h33B3; -defparam \z80_|alu_control_|db[7]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N8 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_34 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout = (\z80_|execute_|ctl_flags_bus~combout & ((\z80_|alu_control_|db[7]~18_combout ) # ((\z80_|alu_|db_high[3]~8_combout & \z80_|execute_|ctl_flags_alu~15_combout )))) # (!\z80_|execute_|ctl_flags_bus~combout -// & (((\z80_|alu_|db_high[3]~8_combout & \z80_|execute_|ctl_flags_alu~15_combout )))) - - .dataa(\z80_|execute_|ctl_flags_bus~combout ), - .datab(\z80_|alu_control_|db[7]~18_combout ), - .datac(\z80_|alu_|db_high[3]~8_combout ), - .datad(\z80_|execute_|ctl_flags_alu~15_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_34 .lut_mask = 16'hF888; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~8_combout = (((!\z80_|execute_|ctl_flags_sz_we~7_combout ) # (!\z80_|execute_|ctl_flags_sz_we~2_combout )) # (!\z80_|execute_|ctl_flags_sz_we~4_combout )) # (!\z80_|execute_|ctl_flags_sz_we~3_combout ) - - .dataa(\z80_|execute_|ctl_flags_sz_we~3_combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~4_combout ), - .datac(\z80_|execute_|ctl_flags_sz_we~2_combout ), - .datad(\z80_|execute_|ctl_flags_sz_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~8 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_flags_sz_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y9_N9 -dffeas \z80_|alu_flags_|DFFE_inst_latch_sf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_flags_sz_we~8_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_sf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_sf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N26 -cycloneive_lcell_comb \z80_|pla_decode_|Equal62~3 ( -// Equation(s): -// \z80_|pla_decode_|Equal62~3_combout = (\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [3] & \z80_|execute_|ctl_state_alu~12_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|execute_|ctl_state_alu~12_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal62~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal62~3 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal62~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~5_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal62~3_combout ) # ((\z80_|execute_|ctl_mWrite~16_combout ) # (\z80_|pla_decode_|Equal11~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal62~3_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_mWrite~16_combout ), - .datad(\z80_|pla_decode_|Equal11~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~5 .lut_mask = 16'hCCC8; -defparam \z80_|execute_|ctl_flags_pf_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~6_combout = (\z80_|pla_decode_|Equal69~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|pla_decode_|Equal69~0_combout ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~6 .lut_mask = 16'h008C; -defparam \z80_|execute_|ctl_flags_pf_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~7_combout = (\z80_|execute_|ctl_flags_pf_we~6_combout ) # ((\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # ((\z80_|nM1_int~2_combout & \z80_|execute_|ctl_mRead~36_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_mRead~36_combout ), - .datac(\z80_|execute_|ctl_flags_pf_we~6_combout ), - .datad(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~7 .lut_mask = 16'hFFF8; -defparam \z80_|execute_|ctl_flags_pf_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~8_combout = (((\z80_|execute_|ctl_flags_pf_we~5_combout ) # (\z80_|execute_|ctl_flags_pf_we~7_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~46_combout )) # (!\z80_|execute_|ctl_flags_pf_we~3_combout ) - - .dataa(\z80_|execute_|ctl_flags_pf_we~3_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~46_combout ), - .datac(\z80_|execute_|ctl_flags_pf_we~5_combout ), - .datad(\z80_|execute_|ctl_flags_pf_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~8 .lut_mask = 16'hFFF7; -defparam \z80_|execute_|ctl_flags_pf_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~9_combout = ((\z80_|execute_|ctl_flags_pf_we~8_combout ) # ((!\z80_|execute_|ctl_pf_sel[0]~3_combout ) # (!\z80_|execute_|ctl_flags_pf_we~4_combout ))) # (!\z80_|execute_|ctl_flags_xy_we~11_combout ) - - .dataa(\z80_|execute_|ctl_flags_xy_we~11_combout ), - .datab(\z80_|execute_|ctl_flags_pf_we~8_combout ), - .datac(\z80_|execute_|ctl_flags_pf_we~4_combout ), - .datad(\z80_|execute_|ctl_pf_sel[0]~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~9 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_flags_pf_we~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N10 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~0 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~0_combout = (\z80_|execute_|ctl_flags_pf_we~9_combout & (\z80_|execute_|ctl_flags_bus~combout & (\z80_|alu_control_|db[2]~29_combout ))) # (!\z80_|execute_|ctl_flags_pf_we~9_combout & -// (((\z80_|alu_flags_|DFFE_inst_latch_pf~q )))) - - .dataa(\z80_|execute_|ctl_flags_bus~combout ), - .datab(\z80_|alu_control_|db[2]~29_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), - .datad(\z80_|execute_|ctl_flags_pf_we~9_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~0 .lut_mask = 16'h88F0; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N22 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~4 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~4_combout = (\z80_|execute_|ctl_pf_sel[0]~2_combout & (((!\z80_|pla_decode_|Equal62~3_combout & !\z80_|execute_|ctl_alu_op_low~13_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal62~3_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_pf_sel[0]~2_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~13_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~4 .lut_mask = 16'h3070; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N28 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~5 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~5_combout = (\z80_|execute_|ctl_pf_sel[0]~3_combout & (!\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout $ -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout )))) # (!\z80_|execute_|ctl_pf_sel[0]~3_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout $ (((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ))))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), - .datab(\z80_|execute_|ctl_pf_sel[0]~3_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~5 .lut_mask = 16'h152A; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N26 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~6 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~6_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout & (((\z80_|execute_|ctl_flags_bus~5_combout & !\z80_|pla_decode_|Equal69~0_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|pla_decode_|Equal69~0_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~6 .lut_mask = 16'h3B00; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~6 .sum_lutc_input = "datac"; +defparam \z80_|decode_state_|in_halt~0 .lut_mask = 16'h0500; +defparam \z80_|decode_state_|in_halt~0 .sum_lutc_input = "datac"; // synopsys translate_on // Location: LCCOMB_X28_Y16_N24 -cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~0 ( +cycloneive_lcell_comb \z80_|decode_state_|in_halt~1 ( // Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~0_combout = (!\z80_|address_latch_|Q [14] & (!\z80_|address_latch_|Q [12] & (!\z80_|address_latch_|Q [15] & !\z80_|address_latch_|Q [13]))) +// \z80_|decode_state_|in_halt~1_combout = (\z80_|decode_state_|in_halt~0_combout ) # ((\z80_|pla_decode_|Equal77~1_combout & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & !\z80_|decode_state_|in_halt~q ))) - .dataa(\z80_|address_latch_|Q [14]), - .datab(\z80_|address_latch_|Q [12]), - .datac(\z80_|address_latch_|Q [15]), - .datad(\z80_|address_latch_|Q [13]), + .dataa(\z80_|pla_decode_|Equal77~1_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|decode_state_|in_halt~q ), + .datad(\z80_|decode_state_|in_halt~0_combout ), .cin(gnd), - .combout(\z80_|decode_state_|DFFE_instNonRep~0_combout ), + .combout(\z80_|decode_state_|in_halt~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep~0 .lut_mask = 16'h0001; -defparam \z80_|decode_state_|DFFE_instNonRep~0 .sum_lutc_input = "datac"; +defparam \z80_|decode_state_|in_halt~1 .lut_mask = 16'hFF08; +defparam \z80_|decode_state_|in_halt~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y17_N16 -cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~3 ( -// Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~3_combout = (!\z80_|address_latch_|Q [1] & (\z80_|address_latch_|Q [0] & (!\z80_|address_latch_|Q [3] & !\z80_|address_latch_|Q [2]))) - - .dataa(\z80_|address_latch_|Q [1]), - .datab(\z80_|address_latch_|Q [0]), - .datac(\z80_|address_latch_|Q [3]), - .datad(\z80_|address_latch_|Q [2]), - .cin(gnd), - .combout(\z80_|decode_state_|DFFE_instNonRep~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep~3 .lut_mask = 16'h0004; -defparam \z80_|decode_state_|DFFE_instNonRep~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N14 -cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~2 ( -// Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~2_combout = (!\z80_|address_latch_|Q [7] & (!\z80_|address_latch_|Q [6] & (!\z80_|address_latch_|Q [5] & !\z80_|address_latch_|Q [4]))) - - .dataa(\z80_|address_latch_|Q [7]), - .datab(\z80_|address_latch_|Q [6]), - .datac(\z80_|address_latch_|Q [5]), - .datad(\z80_|address_latch_|Q [4]), - .cin(gnd), - .combout(\z80_|decode_state_|DFFE_instNonRep~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep~2 .lut_mask = 16'h0001; -defparam \z80_|decode_state_|DFFE_instNonRep~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N8 -cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~1 ( -// Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~1_combout = (!\z80_|address_latch_|Q [10] & (!\z80_|address_latch_|Q [11] & (!\z80_|address_latch_|Q [9] & !\z80_|address_latch_|Q [8]))) - - .dataa(\z80_|address_latch_|Q [10]), - .datab(\z80_|address_latch_|Q [11]), - .datac(\z80_|address_latch_|Q [9]), - .datad(\z80_|address_latch_|Q [8]), - .cin(gnd), - .combout(\z80_|decode_state_|DFFE_instNonRep~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep~1 .lut_mask = 16'h0001; -defparam \z80_|decode_state_|DFFE_instNonRep~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N18 -cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~4 ( -// Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~4_combout = (\z80_|decode_state_|DFFE_instNonRep~0_combout & (\z80_|decode_state_|DFFE_instNonRep~3_combout & (\z80_|decode_state_|DFFE_instNonRep~2_combout & \z80_|decode_state_|DFFE_instNonRep~1_combout ))) - - .dataa(\z80_|decode_state_|DFFE_instNonRep~0_combout ), - .datab(\z80_|decode_state_|DFFE_instNonRep~3_combout ), - .datac(\z80_|decode_state_|DFFE_instNonRep~2_combout ), - .datad(\z80_|decode_state_|DFFE_instNonRep~1_combout ), - .cin(gnd), - .combout(\z80_|decode_state_|DFFE_instNonRep~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep~4 .lut_mask = 16'h8000; -defparam \z80_|decode_state_|DFFE_instNonRep~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N16 -cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~5 ( -// Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~5_combout = (\z80_|execute_|ctl_flags_bus~5_combout & (((\z80_|decode_state_|DFFE_instNonRep~q )))) # (!\z80_|execute_|ctl_flags_bus~5_combout & ((\z80_|execute_|ixy_d~9_combout & -// ((\z80_|decode_state_|DFFE_instNonRep~4_combout ))) # (!\z80_|execute_|ixy_d~9_combout & (\z80_|decode_state_|DFFE_instNonRep~q )))) - - .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|decode_state_|DFFE_instNonRep~q ), - .datad(\z80_|decode_state_|DFFE_instNonRep~4_combout ), - .cin(gnd), - .combout(\z80_|decode_state_|DFFE_instNonRep~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep~5 .lut_mask = 16'hF4B0; -defparam \z80_|decode_state_|DFFE_instNonRep~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y16_N17 -dffeas \z80_|decode_state_|DFFE_instNonRep ( +// Location: FF_X28_Y16_N25 +dffeas \z80_|decode_state_|in_halt ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|decode_state_|DFFE_instNonRep~5_combout ), + .d(\z80_|decode_state_|in_halt~1_combout ), .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), @@ -33642,7153 +6250,203 @@ dffeas \z80_|decode_state_|DFFE_instNonRep ( .ena(vcc), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|decode_state_|DFFE_instNonRep~q ), + .q(\z80_|decode_state_|in_halt~q ), .prn(vcc)); // synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep .is_wysiwyg = "true"; -defparam \z80_|decode_state_|DFFE_instNonRep .power_up = "low"; +defparam \z80_|decode_state_|in_halt .is_wysiwyg = "true"; +defparam \z80_|decode_state_|in_halt .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y16_N12 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~1 ( +// Location: LCCOMB_X28_Y16_N8 +cycloneive_lcell_comb \z80_|pla_decode_|Equal50~0 ( // Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~1_combout = (!\z80_|pla_decode_|Equal62~3_combout & (\z80_|execute_|ctl_pf_sel[0]~3_combout & (\z80_|execute_|ctl_pf_sel[0]~2_combout & !\z80_|execute_|ctl_alu_op_low~13_combout ))) - - .dataa(\z80_|pla_decode_|Equal62~3_combout ), - .datab(\z80_|execute_|ctl_pf_sel[0]~3_combout ), - .datac(\z80_|execute_|ctl_pf_sel[0]~2_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~13_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~1 .lut_mask = 16'h0040; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N10 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~2 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~2_combout = (\z80_|pla_decode_|Equal69~0_combout & ((\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout & (\z80_|interrupts_|DFFE_instIFF2~q )) # (!\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout & -// ((!\z80_|decode_state_|DFFE_instNonRep~q ))))) - - .dataa(\z80_|interrupts_|DFFE_instIFF2~q ), - .datab(\z80_|decode_state_|DFFE_instNonRep~q ), - .datac(\z80_|pla_decode_|Equal69~0_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~2 .lut_mask = 16'hA030; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N24 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~3 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~3_combout = (\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_flags_bus~5_combout & (\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout )) # (!\z80_|execute_|ctl_flags_bus~5_combout & -// ((!\z80_|decode_state_|DFFE_instNonRep~q ))))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_flags_bus~5_combout ), - .datad(\z80_|decode_state_|DFFE_instNonRep~q ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~3 .lut_mask = 16'h808C; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y10_N23 -dffeas \z80_|alu_control_|DFFE_latch_pf_tmp ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|alu_parity_out~combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_alu_op_low~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_control_|DFFE_latch_pf_tmp~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_control_|DFFE_latch_pf_tmp .is_wysiwyg = "true"; -defparam \z80_|alu_control_|DFFE_latch_pf_tmp .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N16 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ) # -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout )))) # (!\z80_|execute_|ctl_alu_core_R~5_combout ) - - .dataa(\z80_|execute_|ctl_alu_core_R~5_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 .lut_mask = 16'h55FD; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N22 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout = (\z80_|alu_|alu_op2[1]~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout & -// \z80_|alu_|alu_op1[1]~0_combout )))) # (!\z80_|alu_|alu_op2[1]~1_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_|alu_op1[1]~0_combout ) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout )))) - - .dataa(\z80_|alu_|alu_op2[1]~1_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), - .datac(\z80_|alu_|alu_op1[1]~0_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 .lut_mask = 16'hFB20; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N28 -cycloneive_lcell_comb \z80_|alu_|alu_parity_out~0 ( -// Equation(s): -// \z80_|alu_|alu_parity_out~0_combout = \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout $ (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout $ (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout )) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), - .datab(gnd), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_parity_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_parity_out~0 .lut_mask = 16'hA55A; -defparam \z80_|alu_|alu_parity_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N22 -cycloneive_lcell_comb \z80_|alu_|alu_parity_out ( -// Equation(s): -// \z80_|alu_|alu_parity_out~combout = \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout $ (\z80_|alu_|alu_parity_out~0_combout $ (((\z80_|execute_|ctl_alu_op_low~combout ) # (\z80_|alu_control_|DFFE_latch_pf_tmp~q )))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~combout ), - .datac(\z80_|alu_control_|DFFE_latch_pf_tmp~q ), - .datad(\z80_|alu_|alu_parity_out~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_parity_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_parity_out .lut_mask = 16'hA956; -defparam \z80_|alu_|alu_parity_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N20 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~7 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~7_combout = (\z80_|pla_decode_|Equal62~3_combout ) # ((\z80_|pla_decode_|Equal69~0_combout ) # ((\z80_|execute_|ctl_alu_op_low~13_combout ) # (!\z80_|execute_|ctl_flags_bus~5_combout ))) - - .dataa(\z80_|pla_decode_|Equal62~3_combout ), - .datab(\z80_|pla_decode_|Equal69~0_combout ), - .datac(\z80_|execute_|ctl_flags_bus~5_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~13_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~7 .lut_mask = 16'hFFEF; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N2 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~8 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~8_combout = (\z80_|execute_|ctl_pf_sel[0]~2_combout & (\z80_|execute_|ctl_pf_sel[0]~3_combout & ((!\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ) # (!\z80_|nM1_int~2_combout )))) - - .dataa(\z80_|execute_|ctl_pf_sel[0]~2_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_pf_sel[0]~3_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~8 .lut_mask = 16'h20A0; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N4 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~9 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~9_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ) # ((\z80_|alu_|alu_parity_out~combout & \z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ), - .datac(\z80_|alu_|alu_parity_out~combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~9 .lut_mask = 16'hFEEE; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N14 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~10 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~10_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ) # ((\z80_|execute_|ctl_flags_pf_we~9_combout & (\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout & \z80_|execute_|ctl_flags_alu~15_combout ))) - - .dataa(\z80_|execute_|ctl_flags_pf_we~9_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ), - .datad(\z80_|execute_|ctl_flags_alu~15_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~10 .lut_mask = 16'hECCC; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y11_N15 -dffeas \z80_|alu_flags_|DFFE_inst_latch_pf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|DFFE_inst_latch_pf~10_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N14 -cycloneive_lcell_comb \z80_|alu_control_|sel[1]~0 ( -// Equation(s): -// \z80_|alu_control_|sel[1]~0_combout = (\z80_|ir_|opcode [5] & (((!\z80_|pla_decode_|Equal40~0_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal40~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|sel[1]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|sel[1]~0 .lut_mask = 16'h70F0; -defparam \z80_|alu_control_|sel[1]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N18 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout = (!\z80_|alu_|db_high[1]~20_combout & (!\z80_|alu_|db_high[3]~8_combout & (!\z80_|alu_|db_high[2]~14_combout & !\z80_|alu_|db_high[0]~26_combout ))) - - .dataa(\z80_|alu_|db_high[1]~20_combout ), - .datab(\z80_|alu_|db_high[3]~8_combout ), - .datac(\z80_|alu_|db_high[2]~14_combout ), - .datad(\z80_|alu_|db_high[0]~26_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2 .lut_mask = 16'h0001; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N4 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_12 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout = (\z80_|alu_control_|db[6]~22_combout & \z80_|execute_|ctl_flags_bus~combout ) - - .dataa(\z80_|alu_control_|db[6]~22_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|execute_|ctl_flags_bus~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_12 .lut_mask = 16'hAA00; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N14 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout = (!\z80_|alu_|db_low[3]~11_combout & (\z80_|alu_|db_high[3]~3_combout & ((!\z80_|alu_|db_low[2]~3_combout ) # (!\z80_|alu_|db_low[2]~6_combout )))) - - .dataa(\z80_|alu_|db_low[2]~6_combout ), - .datab(\z80_|alu_|db_low[3]~11_combout ), - .datac(\z80_|alu_|db_low[2]~3_combout ), - .datad(\z80_|alu_|db_high[3]~3_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 .lut_mask = 16'h1300; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N8 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout = (!\z80_|alu_|db_low[1]~17_combout & (\z80_|execute_|ctl_flags_alu~15_combout & (!\z80_|alu_|db_low[0]~23_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ))) - - .dataa(\z80_|alu_|db_low[1]~17_combout ), - .datab(\z80_|execute_|ctl_flags_alu~15_combout ), - .datac(\z80_|alu_|db_low[0]~23_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 .lut_mask = 16'h0400; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N2 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout = (((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ) # (!\z80_|execute_|ixy_d~7_combout )) # (!\z80_|pla_decode_|Equal13~0_combout )) # (!\z80_|pla_decode_|Equal55~0_combout ) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 .lut_mask = 16'hF7FF; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N26 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout & ((\z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout )))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 .lut_mask = 16'hEC00; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y13_N27 -dffeas \z80_|alu_flags_|SYNTHESIZED_WIRE_39 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_flags_sz_we~8_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_39 .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_39 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N28 -cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_cond_mux|out~0 ( -// Equation(s): -// \z80_|alu_control_|b2v_inst_cond_mux|out~0_combout = (\z80_|alu_control_|sel[1]~0_combout & (((\z80_|ir_|opcode [4])))) # (!\z80_|alu_control_|sel[1]~0_combout & ((\z80_|ir_|opcode [4] & ((\z80_|alu_flags_|flags_cf~combout ))) # (!\z80_|ir_|opcode [4] -// & (\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q )))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .datab(\z80_|alu_flags_|flags_cf~combout ), - .datac(\z80_|alu_control_|sel[1]~0_combout ), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|b2v_inst_cond_mux|out~0 .lut_mask = 16'hFC0A; -defparam \z80_|alu_control_|b2v_inst_cond_mux|out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N18 -cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_cond_mux|out~1 ( -// Equation(s): -// \z80_|alu_control_|b2v_inst_cond_mux|out~1_combout = (\z80_|alu_control_|sel[1]~0_combout & ((\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout & (\z80_|alu_flags_|DFFE_inst_latch_sf~q )) # (!\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout & -// ((\z80_|alu_flags_|DFFE_inst_latch_pf~q ))))) # (!\z80_|alu_control_|sel[1]~0_combout & (((\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout )))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), - .datac(\z80_|alu_control_|sel[1]~0_combout ), - .datad(\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|b2v_inst_cond_mux|out~1 .lut_mask = 16'hAFC0; -defparam \z80_|alu_control_|b2v_inst_cond_mux|out~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N20 -cycloneive_lcell_comb \z80_|alu_control_|flags_cond_true~0 ( -// Equation(s): -// \z80_|alu_control_|flags_cond_true~0_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|ir_|opcode [3] $ (((!\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ))))) # (!\z80_|execute_|ctl_eval_cond~0_combout & -// (((\z80_|alu_control_|flags_cond_true~q )))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|alu_control_|flags_cond_true~q ), - .datad(\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|flags_cond_true~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|flags_cond_true~0 .lut_mask = 16'hB874; -defparam \z80_|alu_control_|flags_cond_true~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y11_N21 -dffeas \z80_|alu_control_|flags_cond_true ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_control_|flags_cond_true~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_control_|flags_cond_true~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_control_|flags_cond_true .is_wysiwyg = "true"; -defparam \z80_|alu_control_|flags_cond_true .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~13 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~13_combout = (((!\z80_|pla_decode_|Equal35~0_combout & !\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|execute_|ixy_d~6_combout )) # (!\z80_|alu_control_|flags_cond_true~q ) - - .dataa(\z80_|pla_decode_|Equal35~0_combout ), - .datab(\z80_|alu_control_|flags_cond_true~q ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|pla_decode_|Equal34~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~13 .lut_mask = 16'h3F7F; -defparam \z80_|execute_|ctl_reg_sel_wz~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~14 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~14_combout = (((\z80_|execute_|ctl_66_oe~2_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~13_combout )) # (!\z80_|execute_|ctl_reg_in_hi~5_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~12_combout ) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~12_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~5_combout ), - .datac(\z80_|execute_|ctl_66_oe~2_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~14 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|ctl_reg_sel_wz~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~17 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~17_combout = (\z80_|execute_|ctl_reg_sel_wz~14_combout ) # (((!\z80_|execute_|ctl_reg_sel_wz~16_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~19_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~11_combout )) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~14_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~11_combout ), - .datac(\z80_|execute_|ctl_reg_sel_wz~19_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~17 .lut_mask = 16'hBFFF; -defparam \z80_|execute_|ctl_reg_sel_wz~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N16 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_82 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_82~combout = (\z80_|execute_|ctl_reg_sel_wz~17_combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout & !\z80_|reg_control_|reg_sys_we_lo~combout )) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~17_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .datac(gnd), - .datad(\z80_|reg_control_|reg_sys_we_lo~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_82 .lut_mask = 16'h0088; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~18 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~18_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~18 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp0[0]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y12_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~20 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~20_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ) # ((\z80_|reg_file_|gdfx_temp0[0]~19_combout ) # ((\z80_|reg_file_|gdfx_temp0[0]~18_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~19_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[0]~18_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~20 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp0[0]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~21 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~21_combout = (\z80_|reg_file_|gdfx_temp0[0]~93_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ) # ((\z80_|reg_file_|gdfx_temp0[0]~20_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[0]~93_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .datac(\z80_|reg_file_|gdfx_temp0[0]~20_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~21 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp0[0]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y10_N23 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X31_Y10_N27 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~28 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~28_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datab(\z80_|reg_file_|b2v_latch_iy_lo|latch [1]), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~28 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp0[1]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y10_N25 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y11_N13 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y12_N25 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~26 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~26_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [1]), - .datad(\z80_|reg_file_|b2v_latch_bc_lo|latch [1]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~26 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[1]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~27 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~27_combout = (\z80_|reg_file_|gdfx_temp0[1]~26_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) +// \z80_|pla_decode_|Equal50~0_combout = (!\z80_|decode_state_|in_halt~q & (\z80_|pla_decode_|Equal33~1_combout & \z80_|pla_decode_|Equal77~0_combout )) .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [1]), - .datad(\z80_|reg_file_|gdfx_temp0[1]~26_combout ), + .datab(\z80_|decode_state_|in_halt~q ), + .datac(\z80_|pla_decode_|Equal33~1_combout ), + .datad(\z80_|pla_decode_|Equal77~0_combout ), .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~27_combout ), + .combout(\z80_|pla_decode_|Equal50~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~27 .lut_mask = 16'hF300; -defparam \z80_|reg_file_|gdfx_temp0[1]~27 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal50~0 .lut_mask = 16'h3000; +defparam \z80_|pla_decode_|Equal50~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y10_N17 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~29 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~29_combout = (\z80_|reg_file_|b2v_latch_sp_lo|latch [1] & (((\z80_|alu_control_|db[1]~26_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) # (!\z80_|reg_file_|b2v_latch_sp_lo|latch [1] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|alu_control_|db[1]~26_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_sp_lo|latch [1]), - .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datac(\z80_|alu_control_|db[1]~26_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~29 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[1]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N3 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N8 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout = \z80_|reg_file_|gdfx_temp0[1]~32_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N9 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~25 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~25_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [1]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [1]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~25 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[1]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~30 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~30_combout = (\z80_|reg_file_|gdfx_temp0[1]~28_combout & (\z80_|reg_file_|gdfx_temp0[1]~27_combout & (\z80_|reg_file_|gdfx_temp0[1]~29_combout & \z80_|reg_file_|gdfx_temp0[1]~25_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[1]~28_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[1]~27_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[1]~29_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[1]~25_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~30 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[1]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N26 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder_combout = \z80_|reg_file_|gdfx_temp0[1]~32_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y9_N27 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y9_N25 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~24 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~24_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [1] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [1] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [1]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~24 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[1]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y13_N23 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y13_N25 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~23 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~23_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [1] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [1] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [1]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~23 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[1]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~31 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~31_combout = (\z80_|reg_file_|gdfx_temp0[1]~30_combout & (\z80_|reg_file_|gdfx_temp0[1]~24_combout & \z80_|reg_file_|gdfx_temp0[1]~23_combout )) - - .dataa(\z80_|reg_file_|gdfx_temp0[1]~30_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[1]~24_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[1]~23_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~31 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|gdfx_temp0[1]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~32 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~32_combout = ((\z80_|reg_file_|gdfx_temp0[1]~31_combout & ((\z80_|reg_file_|db_lo_as[1]~6_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .datac(\z80_|reg_file_|db_lo_as[1]~6_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[1]~31_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~32 .lut_mask = 16'hF733; -defparam \z80_|reg_file_|gdfx_temp0[1]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N12 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[1]~1 ( -// Equation(s): -// \z80_|reg_file_|db_lo_ds[1]~1_combout = (\z80_|reg_file_|gdfx_temp0[1]~32_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout & (\z80_|execute_|ctl_reg_out_lo~7_combout & !\z80_|execute_|ctl_reg_out_lo~5_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), - .datab(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .datad(\z80_|execute_|ctl_reg_out_lo~5_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_ds[1]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_ds[1]~1 .lut_mask = 16'hF0F8; -defparam \z80_|reg_file_|db_lo_ds[1]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N30 -cycloneive_lcell_comb \z80_|alu_control_|db[1]~25 ( -// Equation(s): -// \z80_|alu_control_|db[1]~25_combout = (\z80_|reg_file_|db_lo_ds[1]~1_combout & (((\z80_|bus_control_|db[1]~11_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) - - .dataa(\z80_|bus_control_|db[1]~11_combout ), - .datab(\z80_|reg_file_|db_lo_ds[1]~1_combout ), - .datac(\z80_|execute_|ctl_sw_1d~7_combout ), - .datad(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[1]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[1]~25 .lut_mask = 16'h0C8C; -defparam \z80_|alu_control_|db[1]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N28 -cycloneive_lcell_comb \z80_|alu_control_|db[1]~24 ( -// Equation(s): -// \z80_|alu_control_|db[1]~24_combout = (\z80_|execute_|ctl_flags_oe~2_combout & (((\z80_|execute_|ctl_sw_2u~7_combout & !\z80_|alu_|db[1]~13_combout )) # (!\z80_|alu_flags_|DFFE_inst_latch_nf~q ))) # (!\z80_|execute_|ctl_flags_oe~2_combout & -// (\z80_|execute_|ctl_sw_2u~7_combout & ((!\z80_|alu_|db[1]~13_combout )))) - - .dataa(\z80_|execute_|ctl_flags_oe~2_combout ), - .datab(\z80_|execute_|ctl_sw_2u~7_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .datad(\z80_|alu_|db[1]~13_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[1]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[1]~24 .lut_mask = 16'h0ACE; -defparam \z80_|alu_control_|db[1]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N20 -cycloneive_lcell_comb \z80_|alu_control_|db[1]~26 ( -// Equation(s): -// \z80_|alu_control_|db[1]~26_combout = ((\z80_|alu_control_|db[1]~25_combout & (\z80_|alu_control_|db[2]~23_combout & !\z80_|alu_control_|db[1]~24_combout ))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|alu_control_|db[1]~25_combout ), - .datab(\z80_|alu_control_|db[2]~23_combout ), - .datac(\z80_|alu_control_|db[6]~11_combout ), - .datad(\z80_|alu_control_|db[1]~24_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[1]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[1]~26 .lut_mask = 16'h0F8F; -defparam \z80_|alu_control_|db[1]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N22 -cycloneive_lcell_comb \z80_|alu_|db[1]~12 ( -// Equation(s): -// \z80_|alu_|db[1]~12_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[1]~21_combout & ((\z80_|alu_control_|db[1]~26_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & -// ((\z80_|alu_control_|db[1]~26_combout ) # ((!\z80_|execute_|ctl_sw_2d~13_combout )))) - - .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datab(\z80_|alu_control_|db[1]~26_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .datad(\z80_|execute_|ctl_sw_2d~13_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[1]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[1]~12 .lut_mask = 16'hC4F5; -defparam \z80_|alu_|db[1]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N8 -cycloneive_lcell_comb \z80_|alu_|db[1]~13 ( -// Equation(s): -// \z80_|alu_|db[1]~13_combout = ((\z80_|alu_|db[1]~12_combout & ((\z80_|alu_|db_low[1]~17_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~26_combout ) - - .dataa(\z80_|alu_|db[1]~12_combout ), - .datab(\z80_|execute_|ctl_alu_oe~14_combout ), - .datac(\z80_|alu_|db_low[1]~17_combout ), - .datad(\z80_|alu_|db[7]~26_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[1]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[1]~13 .lut_mask = 16'hA2FF; -defparam \z80_|alu_|db[1]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N18 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~21 ( -// Equation(s): -// \z80_|alu_|db_low[0]~21_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[1]~13_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(gnd), - .datac(\z80_|alu_|db[1]~13_combout ), - .datad(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~21 .lut_mask = 16'hF5A0; -defparam \z80_|alu_|db_low[0]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N0 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~22 ( -// Equation(s): -// \z80_|alu_|db_low[0]~22_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_low[0]~21_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[0]~19_combout ))) - - .dataa(gnd), - .datab(\z80_|alu_|db_low[0]~21_combout ), - .datac(\z80_|alu_|db[0]~19_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~22 .lut_mask = 16'hCCF0; -defparam \z80_|alu_|db_low[0]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N16 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~18 ( -// Equation(s): -// \z80_|alu_|db_low[0]~18_combout = ((!\z80_|bus_control_|db[4]~19_combout & (!\z80_|bus_control_|db[5]~15_combout & !\z80_|bus_control_|db[3]~21_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datab(\z80_|bus_control_|db[4]~19_combout ), - .datac(\z80_|bus_control_|db[5]~15_combout ), - .datad(\z80_|bus_control_|db[3]~21_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~18 .lut_mask = 16'h5557; -defparam \z80_|alu_|db_low[0]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N20 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~19 ( -// Equation(s): -// \z80_|alu_|db_low[0]~19_combout = (\z80_|alu_|op2_low [0] & (((\z80_|alu_|op1_low [0])) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout ))) # (!\z80_|alu_|op2_low [0] & (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_low [0]) # -// (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) - - .dataa(\z80_|alu_|op2_low [0]), - .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datac(\z80_|alu_|op1_low [0]), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~19 .lut_mask = 16'hA2F3; -defparam \z80_|alu_|db_low[0]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y10_N25 -dffeas \z80_|alu_|result_lo[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_alu_op_low~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|result_lo [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|result_lo[0] .is_wysiwyg = "true"; -defparam \z80_|alu_|result_lo[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N24 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~20 ( -// Equation(s): -// \z80_|alu_|db_low[0]~20_combout = (\z80_|alu_|db_low[0]~18_combout & (\z80_|alu_|db_low[0]~19_combout & ((\z80_|alu_|result_lo [0]) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) - - .dataa(\z80_|alu_|db_low[0]~18_combout ), - .datab(\z80_|alu_|db_low[0]~19_combout ), - .datac(\z80_|alu_|result_lo [0]), - .datad(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~20 .lut_mask = 16'h8880; -defparam \z80_|alu_|db_low[0]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N22 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~23 ( -// Equation(s): -// \z80_|alu_|db_low[0]~23_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout & (\z80_|alu_|db_low[0]~22_combout & ((\z80_|alu_|db_low[0]~20_combout )))) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout & (((\z80_|alu_|db_low[0]~20_combout ) # -// (!\z80_|alu_|db_high[3]~2_combout )))) - - .dataa(\z80_|alu_|db_low[0]~22_combout ), - .datab(\z80_|alu_|db_high[3]~2_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datad(\z80_|alu_|db_low[0]~20_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~23 .lut_mask = 16'hAF03; -defparam \z80_|alu_|db_low[0]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N10 -cycloneive_lcell_comb \z80_|alu_|db[0]~18 ( -// Equation(s): -// \z80_|alu_|db[0]~18_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[0]~30_combout & ((\z80_|alu_|db_low[0]~23_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & -// ((\z80_|alu_|db_low[0]~23_combout ) # ((!\z80_|execute_|ctl_alu_oe~14_combout )))) - - .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datab(\z80_|alu_|db_low[0]~23_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .datad(\z80_|execute_|ctl_alu_oe~14_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[0]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[0]~18 .lut_mask = 16'hC4F5; -defparam \z80_|alu_|db[0]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N16 -cycloneive_lcell_comb \z80_|alu_|db[0]~19 ( -// Equation(s): -// \z80_|alu_|db[0]~19_combout = ((\z80_|alu_|db[0]~18_combout & ((\z80_|alu_control_|db[0]~12_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|alu_|db[7]~26_combout ) - - .dataa(\z80_|alu_|db[0]~18_combout ), - .datab(\z80_|execute_|ctl_sw_2d~13_combout ), - .datac(\z80_|alu_control_|db[0]~12_combout ), - .datad(\z80_|alu_|db[7]~26_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[0]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[0]~19 .lut_mask = 16'hA2FF; -defparam \z80_|alu_|db[0]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N30 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~15 ( -// Equation(s): -// \z80_|alu_|db_low[1]~15_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[2]~15_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[0]~19_combout )) - - .dataa(\z80_|alu_|db[0]~19_combout ), - .datab(gnd), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|alu_|db[2]~15_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~15 .lut_mask = 16'hFA0A; -defparam \z80_|alu_|db_low[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N16 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~16 ( -// Equation(s): -// \z80_|alu_|db_low[1]~16_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_low[1]~15_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[1]~13_combout ))) - - .dataa(\z80_|alu_|db_low[1]~15_combout ), - .datab(gnd), - .datac(\z80_|alu_|db[1]~13_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~16 .lut_mask = 16'hAAF0; -defparam \z80_|alu_|db_low[1]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N6 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~12 ( -// Equation(s): -// \z80_|alu_|db_low[1]~12_combout = ((!\z80_|bus_control_|db[4]~19_combout & (!\z80_|bus_control_|db[5]~15_combout & \z80_|bus_control_|db[3]~21_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datab(\z80_|bus_control_|db[4]~19_combout ), - .datac(\z80_|bus_control_|db[5]~15_combout ), - .datad(\z80_|bus_control_|db[3]~21_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~12 .lut_mask = 16'h5755; -defparam \z80_|alu_|db_low[1]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N18 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~13 ( -// Equation(s): -// \z80_|alu_|db_low[1]~13_combout = (\z80_|alu_|op2_low [1] & (((\z80_|alu_|op1_low [1])) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout ))) # (!\z80_|alu_|op2_low [1] & (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_low [1]) # -// (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) - - .dataa(\z80_|alu_|op2_low [1]), - .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datac(\z80_|alu_|op1_low [1]), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~13 .lut_mask = 16'hA2F3; -defparam \z80_|alu_|db_low[1]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y10_N21 -dffeas \z80_|alu_|result_lo[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_alu_op_low~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|result_lo [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|result_lo[1] .is_wysiwyg = "true"; -defparam \z80_|alu_|result_lo[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N20 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~14 ( -// Equation(s): -// \z80_|alu_|db_low[1]~14_combout = (\z80_|alu_|db_low[1]~12_combout & (\z80_|alu_|db_low[1]~13_combout & ((\z80_|alu_|result_lo [1]) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) - - .dataa(\z80_|alu_|db_low[1]~12_combout ), - .datab(\z80_|alu_|db_low[1]~13_combout ), - .datac(\z80_|alu_|result_lo [1]), - .datad(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~14 .lut_mask = 16'h8880; -defparam \z80_|alu_|db_low[1]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N18 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~17 ( -// Equation(s): -// \z80_|alu_|db_low[1]~17_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout & (((\z80_|alu_|db_low[1]~16_combout & \z80_|alu_|db_low[1]~14_combout )))) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout & (((\z80_|alu_|db_low[1]~14_combout )) # -// (!\z80_|alu_|db_high[3]~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datab(\z80_|alu_|db_high[3]~2_combout ), - .datac(\z80_|alu_|db_low[1]~16_combout ), - .datad(\z80_|alu_|db_low[1]~14_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~17 .lut_mask = 16'hF511; -defparam \z80_|alu_|db_low[1]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N26 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout = (\z80_|alu_|db_low[1]~17_combout & ((\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ) # ((\z80_|alu_|db_high[1]~20_combout & \z80_|execute_|ctl_alu_op1_sel_low~combout )))) # -// (!\z80_|alu_|db_low[1]~17_combout & (((\z80_|alu_|db_high[1]~20_combout & \z80_|execute_|ctl_alu_op1_sel_low~combout )))) - - .dataa(\z80_|alu_|db_low[1]~17_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .datac(\z80_|alu_|db_high[1]~20_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 .lut_mask = 16'hF888; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N0 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6_combout = (\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6 .lut_mask = 16'h00F0; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y10_N1 -dffeas \z80_|alu_|op1_low[1] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_low [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_low[1] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_low[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N28 -cycloneive_lcell_comb \z80_|alu_control_|out[6]~0 ( -// Equation(s): -// \z80_|alu_control_|out[6]~0_combout = (\z80_|alu_|op1_low [3] & ((\z80_|alu_|op1_low [1]) # (\z80_|alu_|op1_low [2]))) - - .dataa(gnd), - .datab(\z80_|alu_|op1_low [1]), - .datac(\z80_|alu_|op1_low [3]), - .datad(\z80_|alu_|op1_low [2]), - .cin(gnd), - .combout(\z80_|alu_control_|out[6]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|out[6]~0 .lut_mask = 16'hF0C0; -defparam \z80_|alu_control_|out[6]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N18 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~2 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf~2_combout = (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & \z80_|execute_|ctl_flags_alu~15_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), - .datad(\z80_|execute_|ctl_flags_alu~15_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~2 .lut_mask = 16'h0F00; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N8 -cycloneive_lcell_comb \z80_|alu_flags_|flags_hf2~0 ( -// Equation(s): -// \z80_|alu_flags_|flags_hf2~0_combout = (\z80_|execute_|ctl_flags_hf2_we~combout & ((\z80_|alu_control_|db[4]~32_combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout )))) # (!\z80_|execute_|ctl_flags_hf2_we~combout & -// (((\z80_|alu_flags_|flags_hf2~q )))) - - .dataa(\z80_|alu_control_|db[4]~32_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ), - .datac(\z80_|alu_flags_|flags_hf2~q ), - .datad(\z80_|execute_|ctl_flags_hf2_we~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|flags_hf2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_hf2~0 .lut_mask = 16'hEEF0; -defparam \z80_|alu_flags_|flags_hf2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y11_N9 -dffeas \z80_|alu_flags_|flags_hf2 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|flags_hf2~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|flags_hf2~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_hf2 .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|flags_hf2 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N12 -cycloneive_lcell_comb \z80_|alu_control_|db[2]~23 ( -// Equation(s): -// \z80_|alu_control_|db[2]~23_combout = (\z80_|execute_|ctl_66_oe~combout ) # ((\z80_|alu_control_|out[6]~0_combout ) # ((\z80_|alu_flags_|flags_hf2~q ) # (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout ))) - - .dataa(\z80_|execute_|ctl_66_oe~combout ), - .datab(\z80_|alu_control_|out[6]~0_combout ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datad(\z80_|alu_flags_|flags_hf2~q ), - .cin(gnd), - .combout(\z80_|alu_control_|db[2]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[2]~23 .lut_mask = 16'hFFEF; -defparam \z80_|alu_control_|db[2]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N26 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[2]~2 ( -// Equation(s): -// \z80_|reg_file_|db_lo_ds[2]~2_combout = (\z80_|reg_file_|gdfx_temp0[2]~42_combout ) # ((!\z80_|execute_|ctl_reg_out_lo~5_combout & (\z80_|execute_|ctl_reg_out_lo~7_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ))) - - .dataa(\z80_|execute_|ctl_reg_out_lo~5_combout ), - .datab(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_ds[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_ds[2]~2 .lut_mask = 16'hFF40; -defparam \z80_|reg_file_|db_lo_ds[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N16 -cycloneive_lcell_comb \z80_|alu_control_|db[2]~28 ( -// Equation(s): -// \z80_|alu_control_|db[2]~28_combout = (\z80_|reg_file_|db_lo_ds[2]~2_combout & (((\z80_|bus_control_|db[2]~13_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) - - .dataa(\z80_|bus_control_|db[2]~13_combout ), - .datab(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .datac(\z80_|execute_|ctl_sw_1d~7_combout ), - .datad(\z80_|reg_file_|db_lo_ds[2]~2_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[2]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[2]~28 .lut_mask = 16'h2F00; -defparam \z80_|alu_control_|db[2]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N28 -cycloneive_lcell_comb \z80_|alu_control_|db[2]~27 ( -// Equation(s): -// \z80_|alu_control_|db[2]~27_combout = (\z80_|execute_|ctl_flags_oe~2_combout & (((!\z80_|alu_|db[2]~15_combout & \z80_|execute_|ctl_sw_2u~7_combout )) # (!\z80_|alu_flags_|DFFE_inst_latch_pf~q ))) # (!\z80_|execute_|ctl_flags_oe~2_combout & -// (!\z80_|alu_|db[2]~15_combout & ((\z80_|execute_|ctl_sw_2u~7_combout )))) - - .dataa(\z80_|execute_|ctl_flags_oe~2_combout ), - .datab(\z80_|alu_|db[2]~15_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), - .datad(\z80_|execute_|ctl_sw_2u~7_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[2]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[2]~27 .lut_mask = 16'h3B0A; -defparam \z80_|alu_control_|db[2]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N22 -cycloneive_lcell_comb \z80_|alu_control_|db[2]~29 ( -// Equation(s): -// \z80_|alu_control_|db[2]~29_combout = ((\z80_|alu_control_|db[2]~23_combout & (\z80_|alu_control_|db[2]~28_combout & !\z80_|alu_control_|db[2]~27_combout ))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|alu_control_|db[6]~11_combout ), - .datab(\z80_|alu_control_|db[2]~23_combout ), - .datac(\z80_|alu_control_|db[2]~28_combout ), - .datad(\z80_|alu_control_|db[2]~27_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[2]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[2]~29 .lut_mask = 16'h55D5; -defparam \z80_|alu_control_|db[2]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N30 -cycloneive_lcell_comb \z80_|alu_|db[2]~14 ( -// Equation(s): -// \z80_|alu_|db[2]~14_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[2]~39_combout & ((\z80_|alu_control_|db[2]~29_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & -// (((\z80_|alu_control_|db[2]~29_combout )) # (!\z80_|execute_|ctl_sw_2d~13_combout ))) - - .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datab(\z80_|execute_|ctl_sw_2d~13_combout ), - .datac(\z80_|alu_control_|db[2]~29_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[2]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[2]~14 .lut_mask = 16'hF351; -defparam \z80_|alu_|db[2]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N4 -cycloneive_lcell_comb \z80_|alu_|db[2]~15 ( -// Equation(s): -// \z80_|alu_|db[2]~15_combout = ((\z80_|alu_|db[2]~14_combout & ((\z80_|alu_|db_low[2]~24_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~26_combout ) - - .dataa(\z80_|alu_|db_low[2]~24_combout ), - .datab(\z80_|execute_|ctl_alu_oe~14_combout ), - .datac(\z80_|alu_|db[2]~14_combout ), - .datad(\z80_|alu_|db[7]~26_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[2]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[2]~15 .lut_mask = 16'hB0FF; -defparam \z80_|alu_|db[2]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N4 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~2 ( -// Equation(s): -// \z80_|alu_|db_low[2]~2_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[3]~11_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[1]~13_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|alu_|db[3]~11_combout ), - .datac(\z80_|alu_|db[1]~13_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~2 .lut_mask = 16'hD8D8; -defparam \z80_|alu_|db_low[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N8 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~3 ( -// Equation(s): -// \z80_|alu_|db_low[2]~3_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_low[2]~2_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[2]~15_combout ))) # -// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) - - .dataa(\z80_|alu_|db[2]~15_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datac(\z80_|alu_|db_low[2]~2_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~3 .lut_mask = 16'hF3BB; -defparam \z80_|alu_|db_low[2]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N18 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & (((\z80_|alu_|db_low[2]~6_combout & \z80_|alu_|db_low[2]~3_combout )) # (!\z80_|alu_|db_high[3]~3_combout ))) - - .dataa(\z80_|alu_|db_low[2]~6_combout ), - .datab(\z80_|alu_|db_high[3]~3_combout ), - .datac(\z80_|alu_|db_low[2]~3_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2 .lut_mask = 16'hB300; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N24 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & ((\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout ) # ((\z80_|alu_|db_high[2]~14_combout & \z80_|execute_|ctl_alu_op1_sel_low~combout )))) - - .dataa(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .datac(\z80_|alu_|db_high[2]~14_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 .lut_mask = 16'h3222; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y10_N25 -dffeas \z80_|alu_|op1_low[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_low [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_low[2] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_low[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N24 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [2]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [2])))) - - .dataa(\z80_|alu_|op1_high [2]), - .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datac(\z80_|execute_|ctl_alu_op_low~combout ), - .datad(\z80_|alu_|op1_low [2]), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0 .lut_mask = 16'hC808; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N12 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0_combout ) # ((\z80_|alu_|db_low[2]~24_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datab(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0_combout ), - .datac(\z80_|alu_|db_low[2]~24_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1 .lut_mask = 16'h5444; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y10_N13 -dffeas \z80_|alu_|op2_low[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_low [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_low[2] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_low[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N30 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~5 ( -// Equation(s): -// \z80_|alu_|db_low[2]~5_combout = (\z80_|alu_|op2_low [2] & ((\z80_|alu_|op1_low [2]) # ((!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) # (!\z80_|alu_|op2_low [2] & (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_low [2]) # -// (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) - - .dataa(\z80_|alu_|op2_low [2]), - .datab(\z80_|alu_|op1_low [2]), - .datac(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~5 .lut_mask = 16'h8ACF; -defparam \z80_|alu_|db_low[2]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y10_N13 -dffeas \z80_|alu_|result_lo[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_alu_op_low~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|result_lo [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|result_lo[2] .is_wysiwyg = "true"; -defparam \z80_|alu_|result_lo[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N30 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~6 ( -// Equation(s): -// \z80_|alu_|db_low[2]~6_combout = (\z80_|alu_|db_low[2]~4_combout & (\z80_|alu_|db_low[2]~5_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|result_lo [2])))) - - .dataa(\z80_|alu_|db_low[2]~4_combout ), - .datab(\z80_|alu_|db_low[2]~5_combout ), - .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datad(\z80_|alu_|result_lo [2]), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~6 .lut_mask = 16'h8880; -defparam \z80_|alu_|db_low[2]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N24 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & (((\z80_|alu_|db_low[2]~6_combout & \z80_|alu_|db_low[2]~3_combout )) # (!\z80_|alu_|db_high[3]~3_combout ))) - - .dataa(\z80_|alu_|db_low[2]~6_combout ), - .datab(\z80_|alu_|db_low[2]~3_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datad(\z80_|alu_|db_high[3]~3_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 .lut_mask = 16'h80F0; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N26 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ) # ((\z80_|alu_|db_high[2]~14_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datab(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ), - .datac(\z80_|alu_|db_high[2]~14_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4 .lut_mask = 16'h5444; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y10_N27 -dffeas \z80_|alu_|op2_high[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_high [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_high[2] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_high[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N14 -cycloneive_lcell_comb \z80_|alu_|alu_op2[2]~0 ( -// Equation(s): -// \z80_|alu_|alu_op2[2]~0_combout = \z80_|execute_|ctl_alu_sel_op2_neg~18_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_high [2])) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_low [2]))))) - - .dataa(\z80_|alu_|op2_high [2]), - .datab(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), - .datad(\z80_|alu_|op2_low [2]), - .cin(gnd), - .combout(\z80_|alu_|alu_op2[2]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op2[2]~0 .lut_mask = 16'h4B78; -defparam \z80_|alu_|alu_op2[2]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N0 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ) # -// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) # (!\z80_|execute_|ctl_alu_core_R~5_combout ) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), - .datad(\z80_|execute_|ctl_alu_core_R~5_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 .lut_mask = 16'h0BFF; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N12 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout = (\z80_|alu_|alu_op2[2]~0_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ) # ((\z80_|alu_|alu_op1[2]~2_combout & -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) # (!\z80_|alu_|alu_op2[2]~0_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_|alu_op1[2]~2_combout ) # -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) - - .dataa(\z80_|alu_|alu_op2[2]~0_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ), - .datac(\z80_|alu_|alu_op1[2]~2_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 .lut_mask = 16'hECC8; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N26 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~9 ( -// Equation(s): -// \z80_|alu_|db_high[2]~9_combout = ((\z80_|bus_control_|db[4]~19_combout & (\z80_|bus_control_|db[5]~15_combout & !\z80_|bus_control_|db[3]~21_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datab(\z80_|bus_control_|db[4]~19_combout ), - .datac(\z80_|bus_control_|db[5]~15_combout ), - .datad(\z80_|bus_control_|db[3]~21_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~9 .lut_mask = 16'h55D5; -defparam \z80_|alu_|db_high[2]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N24 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~11 ( -// Equation(s): -// \z80_|alu_|db_high[2]~11_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[7]~21_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[5]~25_combout )) - - .dataa(\z80_|ir_|opcode [3]), - .datab(gnd), - .datac(\z80_|alu_|db[5]~25_combout ), - .datad(\z80_|alu_|db[7]~21_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~11 .lut_mask = 16'hFA50; -defparam \z80_|alu_|db_high[2]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N22 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~12 ( -// Equation(s): -// \z80_|alu_|db_high[2]~12_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_high[2]~11_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[6]~23_combout ))) - - .dataa(gnd), - .datab(\z80_|alu_|db_high[2]~11_combout ), - .datac(\z80_|alu_|db[6]~23_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~12 .lut_mask = 16'hCCF0; -defparam \z80_|alu_|db_high[2]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N24 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~10 ( -// Equation(s): -// \z80_|alu_|db_high[2]~10_combout = (\z80_|alu_|op1_high [2] & (((\z80_|alu_|op2_high [2]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|alu_|op1_high [2] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_high [2]) # -// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) - - .dataa(\z80_|alu_|op1_high [2]), - .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datac(\z80_|alu_|op2_high [2]), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~10 .lut_mask = 16'hB0BB; -defparam \z80_|alu_|db_high[2]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N20 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~13 ( -// Equation(s): -// \z80_|alu_|db_high[2]~13_combout = (\z80_|alu_|db_high[2]~9_combout & (\z80_|alu_|db_high[2]~10_combout & ((\z80_|alu_|db_high[2]~12_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) - - .dataa(\z80_|alu_|db_high[2]~9_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datac(\z80_|alu_|db_high[2]~12_combout ), - .datad(\z80_|alu_|db_high[2]~10_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~13 .lut_mask = 16'hA200; -defparam \z80_|alu_|db_high[2]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N10 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~14 ( -// Equation(s): -// \z80_|alu_|db_high[2]~14_combout = ((\z80_|alu_|db_high[2]~13_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) # (!\z80_|alu_|db_high[3]~3_combout ) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), - .datab(\z80_|alu_|db_high[3]~3_combout ), - .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datad(\z80_|alu_|db_high[2]~13_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~14 .lut_mask = 16'hFB33; -defparam \z80_|alu_|db_high[2]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N18 -cycloneive_lcell_comb \z80_|alu_|db[6]~22 ( -// Equation(s): -// \z80_|alu_|db[6]~22_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[6]~84_combout & ((\z80_|alu_control_|db[6]~22_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & -// (((\z80_|alu_control_|db[6]~22_combout )) # (!\z80_|execute_|ctl_sw_2d~13_combout ))) - - .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datab(\z80_|execute_|ctl_sw_2d~13_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .datad(\z80_|alu_control_|db[6]~22_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[6]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[6]~22 .lut_mask = 16'hF531; -defparam \z80_|alu_|db[6]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N20 -cycloneive_lcell_comb \z80_|alu_|db[6]~23 ( -// Equation(s): -// \z80_|alu_|db[6]~23_combout = ((\z80_|alu_|db[6]~22_combout & ((\z80_|alu_|db_high[2]~14_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~26_combout ) - - .dataa(\z80_|alu_|db_high[2]~14_combout ), - .datab(\z80_|execute_|ctl_alu_oe~14_combout ), - .datac(\z80_|alu_|db[6]~22_combout ), - .datad(\z80_|alu_|db[7]~26_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[6]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[6]~23 .lut_mask = 16'hB0FF; -defparam \z80_|alu_|db[6]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N10 -cycloneive_lcell_comb \z80_|alu_control_|out[6]~1 ( -// Equation(s): -// \z80_|alu_control_|out[6]~1_combout = (\z80_|alu_|op1_high [2]) # ((\z80_|alu_|op1_high [1]) # ((\z80_|alu_|op1_high [0] & \z80_|alu_control_|out[6]~0_combout ))) - - .dataa(\z80_|alu_|op1_high [2]), - .datab(\z80_|alu_|op1_high [0]), - .datac(\z80_|alu_|op1_high [1]), - .datad(\z80_|alu_control_|out[6]~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|out[6]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|out[6]~1 .lut_mask = 16'hFEFA; -defparam \z80_|alu_control_|out[6]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N26 -cycloneive_lcell_comb \z80_|alu_control_|out[6]~2 ( -// Equation(s): -// \z80_|alu_control_|out[6]~2_combout = (\z80_|execute_|ctl_66_oe~combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_cf~q ) # ((\z80_|alu_control_|out[6]~1_combout & \z80_|alu_|op1_high [3]))) - - .dataa(\z80_|execute_|ctl_66_oe~combout ), - .datab(\z80_|alu_control_|out[6]~1_combout ), - .datac(\z80_|alu_|op1_high [3]), - .datad(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), - .cin(gnd), - .combout(\z80_|alu_control_|out[6]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|out[6]~2 .lut_mask = 16'hFFEA; -defparam \z80_|alu_control_|out[6]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N12 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~19 ( -// Equation(s): -// \z80_|alu_control_|db[6]~19_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & ((\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ) # ((\z80_|alu_control_|out[6]~2_combout )))) # (!\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & -// (!\z80_|execute_|ctl_flags_oe~2_combout & ((\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ) # (\z80_|alu_control_|out[6]~2_combout )))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .datab(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .datac(\z80_|execute_|ctl_flags_oe~2_combout ), - .datad(\z80_|alu_control_|out[6]~2_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~19 .lut_mask = 16'hAF8C; -defparam \z80_|alu_control_|db[6]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N26 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~20 ( -// Equation(s): -// \z80_|alu_control_|db[6]~20_combout = (\z80_|alu_control_|db[6]~19_combout & ((\z80_|alu_|db[6]~23_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout ))) - - .dataa(gnd), - .datab(\z80_|alu_|db[6]~23_combout ), - .datac(\z80_|execute_|ctl_sw_2u~7_combout ), - .datad(\z80_|alu_control_|db[6]~19_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~20 .lut_mask = 16'hCF00; -defparam \z80_|alu_control_|db[6]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N24 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~21 ( -// Equation(s): -// \z80_|alu_control_|db[6]~21_combout = (\z80_|alu_control_|db[6]~20_combout & (((\z80_|bus_control_|db[6]~9_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) - - .dataa(\z80_|bus_control_|db[6]~9_combout ), - .datab(\z80_|execute_|ctl_sw_1d~7_combout ), - .datac(\z80_|alu_control_|db[6]~20_combout ), - .datad(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~21 .lut_mask = 16'h30B0; -defparam \z80_|alu_control_|db[6]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N6 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~22 ( -// Equation(s): -// \z80_|alu_control_|db[6]~22_combout = ((\z80_|alu_control_|db[6]~21_combout & ((\z80_|reg_file_|gdfx_temp0[6]~82_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|alu_control_|db[6]~11_combout ), - .datab(\z80_|alu_control_|db[6]~21_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .datad(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~22 .lut_mask = 16'hD5DD; -defparam \z80_|alu_control_|db[6]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_zero_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_bus_zero_oe~0_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal33~1_combout & ((\z80_|execute_|ctl_alu_op_low~13_combout ) # (\z80_|execute_|ctl_iorw~11_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~13_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_iorw~11_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_zero_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_zero_oe~0 .lut_mask = 16'hC800; -defparam \z80_|execute_|ctl_bus_zero_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N8 -cycloneive_lcell_comb \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 ( -// Equation(s): -// \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout = (\z80_|bus_control_|db[4]~19_combout & !\z80_|bus_control_|db[3]~21_combout ) - - .dataa(gnd), - .datab(\z80_|bus_control_|db[4]~19_combout ), - .datac(gnd), - .datad(\z80_|bus_control_|db[3]~21_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 .lut_mask = 16'h00CC; -defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y10_N9 -dffeas \z80_|interrupts_|im1 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_im_we~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|interrupts_|im1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|interrupts_|im1 .is_wysiwyg = "true"; -defparam \z80_|interrupts_|im1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_ff_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_bus_ff_oe~0_combout = (\z80_|interrupts_|DFFE_inst44~q & ((\z80_|interrupts_|im1~q ) # ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|interrupts_|im2~q )))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|interrupts_|im1~q ), - .datac(\z80_|interrupts_|im2~q ), - .datad(\z80_|interrupts_|DFFE_inst44~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_ff_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_ff_oe~0 .lut_mask = 16'hDC00; -defparam \z80_|execute_|ctl_bus_ff_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_ff_oe~1 ( -// Equation(s): -// \z80_|execute_|ctl_bus_ff_oe~1_combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) # (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|execute_|ctl_bus_ff_oe~0_combout & -// ((\z80_|execute_|ctl_66_oe~2_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|execute_|ctl_bus_ff_oe~0_combout ), - .datac(\z80_|execute_|ctl_66_oe~2_combout ), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_ff_oe~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_ff_oe~1 .lut_mask = 16'h40EE; -defparam \z80_|execute_|ctl_bus_ff_oe~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N0 -cycloneive_lcell_comb \z80_|bus_control_|db[0]~4 ( -// Equation(s): -// \z80_|bus_control_|db[0]~4_combout = (\z80_|execute_|ctl_bus_ff_oe~1_combout ) # ((!\z80_|execute_|ctl_bus_zero_oe~0_combout & ((\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) # (!\z80_|decode_state_|in_halt~q )))) - - .dataa(\z80_|decode_state_|in_halt~q ), - .datab(\z80_|execute_|ctl_bus_zero_oe~0_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|execute_|ctl_bus_ff_oe~1_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[0]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[0]~4 .lut_mask = 16'hFF31; -defparam \z80_|bus_control_|db[0]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N6 -cycloneive_lcell_comb \z80_|bus_control_|db[6]~8 ( -// Equation(s): -// \z80_|bus_control_|db[6]~8_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[6]~22_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) - - .dataa(gnd), - .datab(\z80_|alu_control_|db[6]~22_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|bus_control_|db[0]~4_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[6]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[6]~8 .lut_mask = 16'hCF00; -defparam \z80_|bus_control_|db[6]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~37 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~37_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal37~0_combout & !\z80_|execute_|ctl_mRead~36_combout ))) # (!\z80_|sequencer_|DFFE_T5_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|pla_decode_|Equal37~0_combout ), - .datad(\z80_|execute_|ctl_mRead~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~37 .lut_mask = 16'hDDDF; -defparam \z80_|execute_|ctl_mRead~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~28 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~28_combout = (\z80_|execute_|ctl_mRead~37_combout & (!\z80_|execute_|ctl_reg_gp_sel~36_combout & ((!\z80_|pla_decode_|Equal38~2_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~37_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel~36_combout ), - .datad(\z80_|pla_decode_|Equal38~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~28 .lut_mask = 16'h020A; -defparam \z80_|execute_|ctl_mRead~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~29 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~29_combout = (\z80_|execute_|ctl_mRead~28_combout & (\z80_|execute_|ctl_mRead~25_combout & ((!\z80_|pla_decode_|Equal21~1_combout ) # (!\z80_|execute_|ctl_mRead~11_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~28_combout ), - .datab(\z80_|execute_|ctl_mRead~11_combout ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|execute_|ctl_mRead~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~29 .lut_mask = 16'h2A00; -defparam \z80_|execute_|ctl_mRead~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~30 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~30_combout = (\z80_|execute_|ctl_mRead~29_combout & (\z80_|execute_|ctl_reg_in_hi~5_combout & (\z80_|execute_|ctl_mRead~22_combout & !\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ))) - - .dataa(\z80_|execute_|ctl_mRead~29_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~5_combout ), - .datac(\z80_|execute_|ctl_mRead~22_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~30 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_mRead~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y18_N0 -cycloneive_lcell_comb \z80_|execute_|setM1~37 ( -// Equation(s): -// \z80_|execute_|setM1~37_combout = (!\z80_|pla_decode_|Equal9~1_combout & (!\z80_|pla_decode_|Equal29~0_combout & (\z80_|execute_|ctl_al_we~4_combout & \z80_|execute_|ctl_inc_cy~41_combout ))) - - .dataa(\z80_|pla_decode_|Equal9~1_combout ), - .datab(\z80_|pla_decode_|Equal29~0_combout ), - .datac(\z80_|execute_|ctl_al_we~4_combout ), - .datad(\z80_|execute_|ctl_inc_cy~41_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~37 .lut_mask = 16'h1000; -defparam \z80_|execute_|setM1~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N10 -cycloneive_lcell_comb \z80_|execute_|setM1~55 ( +// Location: LCCOMB_X25_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|ixy_d~17 ( // Equation(s): -// \z80_|execute_|setM1~55_combout = (!\z80_|execute_|ctl_mRead~14_combout & ((\z80_|decode_state_|DFFE_instIY1~q ) # ((\z80_|decode_state_|DFFE_inst4~q ) # (!\z80_|pla_decode_|Equal49~0_combout )))) +// \z80_|execute_|ixy_d~17_combout = (\z80_|decode_state_|DFFE_instIY1~q & (((!\z80_|pla_decode_|Equal33~2_combout & !\z80_|pla_decode_|Equal50~0_combout )))) # (!\z80_|decode_state_|DFFE_instIY1~q & (((!\z80_|pla_decode_|Equal33~2_combout & +// !\z80_|pla_decode_|Equal50~0_combout )) # (!\z80_|decode_state_|DFFE_inst4~q ))) .dataa(\z80_|decode_state_|DFFE_instIY1~q ), - .datab(\z80_|execute_|ctl_mRead~14_combout ), - .datac(\z80_|decode_state_|DFFE_inst4~q ), - .datad(\z80_|pla_decode_|Equal49~0_combout ), + .datab(\z80_|decode_state_|DFFE_inst4~q ), + .datac(\z80_|pla_decode_|Equal33~2_combout ), + .datad(\z80_|pla_decode_|Equal50~0_combout ), .cin(gnd), - .combout(\z80_|execute_|setM1~55_combout ), + .combout(\z80_|execute_|ixy_d~17_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|setM1~55 .lut_mask = 16'h3233; -defparam \z80_|execute_|setM1~55 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ixy_d~17 .lut_mask = 16'h111F; +defparam \z80_|execute_|ixy_d~17 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y18_N30 -cycloneive_lcell_comb \z80_|execute_|setM1~38 ( +// Location: LCCOMB_X25_Y16_N0 +cycloneive_lcell_comb \z80_|pla_decode_|Equal44~0 ( // Equation(s): -// \z80_|execute_|setM1~38_combout = (!\z80_|execute_|ctl_mRead~16_combout & (\z80_|execute_|setM1~37_combout & (\z80_|execute_|setM1~55_combout & \z80_|execute_|setM1~36_combout ))) +// \z80_|pla_decode_|Equal44~0_combout = (!\z80_|decode_state_|DFFE_instCB~q & (!\z80_|decode_state_|DFFE_instED~q & (\z80_|ir_|opcode [7] & !\z80_|ir_|opcode [6]))) - .dataa(\z80_|execute_|ctl_mRead~16_combout ), - .datab(\z80_|execute_|setM1~37_combout ), - .datac(\z80_|execute_|setM1~55_combout ), - .datad(\z80_|execute_|setM1~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~38 .lut_mask = 16'h4000; -defparam \z80_|execute_|setM1~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~34 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~34_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (((\z80_|execute_|ctl_mRead~13_combout ) # (!\z80_|execute_|ctl_mRead~19_combout )) # (!\z80_|execute_|setM1~38_combout ))) - - .dataa(\z80_|execute_|setM1~38_combout ), - .datab(\z80_|execute_|ctl_mRead~13_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_mRead~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~34 .lut_mask = 16'hD0F0; -defparam \z80_|execute_|ctl_mRead~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N2 -cycloneive_lcell_comb \z80_|execute_|nextM~3 ( -// Equation(s): -// \z80_|execute_|nextM~3_combout = (!\z80_|pla_decode_|Equal41~2_combout & (!\z80_|execute_|ixy_d~10_combout & !\z80_|execute_|ixy_d~16_combout )) - - .dataa(gnd), - .datab(\z80_|pla_decode_|Equal41~2_combout ), - .datac(\z80_|execute_|ixy_d~10_combout ), - .datad(\z80_|execute_|ixy_d~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~3 .lut_mask = 16'h0003; -defparam \z80_|execute_|nextM~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~31 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~31_combout = (\z80_|execute_|ixy_d~8_combout & (((\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal49~0_combout )) # (!\z80_|execute_|nextM~3_combout ))) - - .dataa(\z80_|execute_|ixy_d~8_combout ), - .datab(\z80_|decode_state_|use_ixiy~combout ), - .datac(\z80_|execute_|nextM~3_combout ), - .datad(\z80_|pla_decode_|Equal49~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~31 .lut_mask = 16'h8A0A; -defparam \z80_|execute_|ctl_mRead~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~32 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~32_combout = (\z80_|execute_|ctl_state_alu~4_combout & ((\z80_|pla_decode_|Equal33~3_combout ) # ((\z80_|pla_decode_|Equal6~1_combout ) # (\z80_|pla_decode_|Equal41~2_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|pla_decode_|Equal33~3_combout ), - .datac(\z80_|pla_decode_|Equal6~1_combout ), - .datad(\z80_|pla_decode_|Equal41~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~32 .lut_mask = 16'hAAA8; -defparam \z80_|execute_|ctl_mRead~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~33 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~33_combout = (\z80_|execute_|ctl_mRead~32_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & \z80_|execute_|ctl_mRead~12_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .datac(\z80_|execute_|ctl_mRead~12_combout ), - .datad(\z80_|execute_|ctl_mRead~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~33 .lut_mask = 16'hFFC0; -defparam \z80_|execute_|ctl_mRead~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~35 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~35_combout = ((\z80_|execute_|ctl_mRead~34_combout ) # ((\z80_|execute_|ctl_mRead~31_combout ) # (\z80_|execute_|ctl_mRead~33_combout ))) # (!\z80_|execute_|ctl_mRead~30_combout ) - - .dataa(\z80_|execute_|ctl_mRead~30_combout ), - .datab(\z80_|execute_|ctl_mRead~34_combout ), - .datac(\z80_|execute_|ctl_mRead~31_combout ), - .datad(\z80_|execute_|ctl_mRead~33_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~35 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_mRead~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X43_Y17_N23 -dffeas \z80_|memory_ifc_|DFFE_mrd_ff1 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_mRead~35_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_mrd_ff1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_mrd_ff1 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_mrd_ff1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y15_N24 -cycloneive_lcell_comb \z80_|memory_ifc_|wait_mrd~feeder ( -// Equation(s): -// \z80_|memory_ifc_|wait_mrd~feeder_combout = \z80_|memory_ifc_|DFFE_mrd_ff1~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|memory_ifc_|DFFE_mrd_ff1~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|wait_mrd~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_mrd~feeder .lut_mask = 16'hFF00; -defparam \z80_|memory_ifc_|wait_mrd~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X46_Y15_N25 -dffeas \z80_|memory_ifc_|wait_mrd ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|memory_ifc_|wait_mrd~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|wait_mrd~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_mrd .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|wait_mrd .power_up = "low"; -// synopsys translate_on - -// Location: FF_X43_Y17_N3 -dffeas \z80_|memory_ifc_|DFFE_mrd_ff3 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|memory_ifc_|wait_mrd~q ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_mrd_ff3~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_mrd_ff3 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_mrd_ff3 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N8 -cycloneive_lcell_comb \z80_|memory_ifc_|nRD_out~1 ( -// Equation(s): -// \z80_|memory_ifc_|nRD_out~1_combout = (!\z80_|memory_ifc_|wait_mrd~q & !\z80_|memory_ifc_|DFFE_mrd_ff3~q ) - - .dataa(\z80_|memory_ifc_|wait_mrd~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|memory_ifc_|DFFE_mrd_ff3~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|nRD_out~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|nRD_out~1 .lut_mask = 16'h0055; -defparam \z80_|memory_ifc_|nRD_out~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N30 -cycloneive_lcell_comb \z80_|execute_|nextM~4 ( -// Equation(s): -// \z80_|execute_|nextM~4_combout = ((!\z80_|execute_|ctl_mRead~36_combout & ((!\z80_|pla_decode_|Equal24~0_combout ) # (!\z80_|pla_decode_|Equal21~0_combout )))) # (!\z80_|execute_|ctl_state_alu~4_combout ) - - .dataa(\z80_|pla_decode_|Equal21~0_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_mRead~36_combout ), - .datad(\z80_|pla_decode_|Equal24~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~4 .lut_mask = 16'h373F; -defparam \z80_|execute_|nextM~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_iorw~12 ( -// Equation(s): -// \z80_|execute_|ctl_iorw~12_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2]))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|execute_|ctl_iorw~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_iorw~12 .lut_mask = 16'h0008; -defparam \z80_|execute_|ctl_iorw~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_iorw~8 ( -// Equation(s): -// \z80_|execute_|ctl_iorw~8_combout = (\z80_|execute_|ctl_iorw~12_combout ) # ((\z80_|pla_decode_|Equal24~0_combout & (\z80_|pla_decode_|Equal3~0_combout & \z80_|execute_|ctl_state_alu~4_combout ))) - - .dataa(\z80_|pla_decode_|Equal24~0_combout ), - .datab(\z80_|execute_|ctl_iorw~12_combout ), - .datac(\z80_|pla_decode_|Equal3~0_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_iorw~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_iorw~8 .lut_mask = 16'hECCC; -defparam \z80_|execute_|ctl_iorw~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_iorw~9 ( -// Equation(s): -// \z80_|execute_|ctl_iorw~9_combout = ((\z80_|execute_|ctl_iorw~8_combout ) # ((\z80_|execute_|ctl_mRead~11_combout & \z80_|execute_|ctl_mWrite~16_combout ))) # (!\z80_|execute_|nextM~4_combout ) - - .dataa(\z80_|execute_|nextM~4_combout ), - .datab(\z80_|execute_|ctl_mRead~11_combout ), - .datac(\z80_|execute_|ctl_mWrite~16_combout ), - .datad(\z80_|execute_|ctl_iorw~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_iorw~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_iorw~9 .lut_mask = 16'hFFD5; -defparam \z80_|execute_|ctl_iorw~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X43_Y17_N7 -dffeas \z80_|memory_ifc_|DFFE_iorq_ff1 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_iorw~9_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_iorq_ff1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_iorq_ff1 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_iorq_ff1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N26 -cycloneive_lcell_comb \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder ( -// Equation(s): -// \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder_combout = \z80_|memory_ifc_|DFFE_iorq_ff1~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|memory_ifc_|DFFE_iorq_ff1~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder .lut_mask = 16'hFF00; -defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X43_Y17_N27 -dffeas \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 .power_up = "low"; -// synopsys translate_on - -// Location: FF_X43_Y17_N9 -dffeas \z80_|memory_ifc_|wait_iorq ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|wait_iorq~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_iorq .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|wait_iorq .power_up = "low"; -// synopsys translate_on - -// Location: FF_X43_Y17_N13 -dffeas \z80_|memory_ifc_|DFFE_iorq_ff4 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|memory_ifc_|wait_iorq~q ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_iorq_ff4~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_iorq_ff4 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_iorq_ff4 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N12 -cycloneive_lcell_comb \z80_|memory_ifc_|iorq~0 ( -// Equation(s): -// \z80_|memory_ifc_|iorq~0_combout = (\z80_|memory_ifc_|wait_iorq~q ) # ((\z80_|memory_ifc_|DFFE_iorq_ff4~q ) # (\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q )) - - .dataa(gnd), - .datab(\z80_|memory_ifc_|wait_iorq~q ), - .datac(\z80_|memory_ifc_|DFFE_iorq_ff4~q ), - .datad(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|iorq~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|iorq~0 .lut_mask = 16'hFFFC; -defparam \z80_|memory_ifc_|iorq~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|fIORead~1 ( -// Equation(s): -// \z80_|execute_|fIORead~1_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_mWrite~2_combout & ((\z80_|execute_|ctl_state_alu~5_combout ) # (\z80_|execute_|ctl_mWrite~3_combout )))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|execute_|ctl_state_alu~5_combout ), - .datac(\z80_|execute_|ctl_mWrite~3_combout ), - .datad(\z80_|execute_|ctl_mWrite~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIORead~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIORead~1 .lut_mask = 16'hA800; -defparam \z80_|execute_|fIORead~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N18 -cycloneive_lcell_comb \z80_|execute_|fIORead~2 ( -// Equation(s): -// \z80_|execute_|fIORead~2_combout = (\z80_|execute_|fIORead~1_combout ) # ((\z80_|execute_|ctl_alu_op_low~9_combout ) # ((\z80_|execute_|ctl_iorw~10_combout & !\z80_|execute_|fIOWrite~0_combout ))) - - .dataa(\z80_|execute_|ctl_iorw~10_combout ), - .datab(\z80_|execute_|fIOWrite~0_combout ), - .datac(\z80_|execute_|fIORead~1_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIORead~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIORead~2 .lut_mask = 16'hFFF2; -defparam \z80_|execute_|fIORead~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y18_N6 -cycloneive_lcell_comb \z80_|execute_|fIORead~0 ( -// Equation(s): -// \z80_|execute_|fIORead~0_combout = (\z80_|execute_|ctl_mWrite~2_combout & (\z80_|pla_decode_|Equal55~0_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ctl_alu_op_low~8_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~2_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIORead~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIORead~0 .lut_mask = 16'hA080; -defparam \z80_|execute_|fIORead~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N6 -cycloneive_lcell_comb \z80_|execute_|fIORead~3 ( -// Equation(s): -// \z80_|execute_|fIORead~3_combout = (\z80_|execute_|fIORead~2_combout ) # ((\z80_|execute_|fIORead~0_combout ) # ((\z80_|execute_|fIOWrite~1_combout & \z80_|execute_|ctl_mRead~4_combout ))) - - .dataa(\z80_|execute_|fIOWrite~1_combout ), - .datab(\z80_|execute_|fIORead~2_combout ), - .datac(\z80_|execute_|ctl_mRead~4_combout ), - .datad(\z80_|execute_|fIORead~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIORead~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIORead~3 .lut_mask = 16'hFFEC; -defparam \z80_|execute_|fIORead~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X41_Y17_N25 -dffeas \z80_|memory_ifc_|DFFE_m1_ff1 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|setM1~52_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_m1_ff1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_m1_ff1 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_m1_ff1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N14 -cycloneive_lcell_comb \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0 ( -// Equation(s): -// \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout = !\z80_|memory_ifc_|DFFE_m1_ff1~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|memory_ifc_|DFFE_m1_ff1~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0 .lut_mask = 16'h00FF; -defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X43_Y17_N15 -dffeas \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 .power_up = "low"; -// synopsys translate_on - -// Location: FF_X43_Y17_N21 -dffeas \z80_|memory_ifc_|DFFE_m1_ff3 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_m1_ff3~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_m1_ff3 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_m1_ff3 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N20 -cycloneive_lcell_comb \z80_|memory_ifc_|nRD_out~0 ( -// Equation(s): -// \z80_|memory_ifc_|nRD_out~0_combout = (\z80_|interrupts_|DFFE_inst44~q & (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & ((\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ) # (\z80_|memory_ifc_|DFFE_m1_ff3~q )))) # (!\z80_|interrupts_|DFFE_inst44~q & -// ((\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ) # ((\z80_|memory_ifc_|DFFE_m1_ff3~q )))) - - .dataa(\z80_|interrupts_|DFFE_inst44~q ), - .datab(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ), - .datac(\z80_|memory_ifc_|DFFE_m1_ff3~q ), - .datad(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|nRD_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|nRD_out~0 .lut_mask = 16'hFC54; -defparam \z80_|memory_ifc_|nRD_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N18 -cycloneive_lcell_comb \z80_|memory_ifc_|nRD_out~2 ( -// Equation(s): -// \z80_|memory_ifc_|nRD_out~2_combout = ((\z80_|memory_ifc_|nRD_out~0_combout ) # ((\z80_|memory_ifc_|iorq~0_combout & \z80_|execute_|fIORead~3_combout ))) # (!\z80_|memory_ifc_|nRD_out~1_combout ) - - .dataa(\z80_|memory_ifc_|nRD_out~1_combout ), - .datab(\z80_|memory_ifc_|iorq~0_combout ), - .datac(\z80_|execute_|fIORead~3_combout ), - .datad(\z80_|memory_ifc_|nRD_out~0_combout ), - .cin(gnd), - .combout(\z80_|memory_ifc_|nRD_out~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|nRD_out~2 .lut_mask = 16'hFFD5; -defparam \z80_|memory_ifc_|nRD_out~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N24 -cycloneive_lcell_comb \Equal2~1 ( -// Equation(s): -// \Equal2~1_combout = (!\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|memory_ifc_|nRD_out~2_combout & \z80_|resets_|SYNTHESIZED_WIRE_12~q )) - - .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), - .datab(\z80_|memory_ifc_|nRD_out~2_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(gnd), - .cin(gnd), - .combout(\Equal2~1_combout ), - .cout()); -// synopsys translate_off -defparam \Equal2~1 .lut_mask = 16'h4040; -defparam \Equal2~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N30 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~0 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~0_combout = (\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~0 .lut_mask = 16'hFFAA; -defparam \z80_|pin_control_|bus_db_pin_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y18_N10 -cycloneive_lcell_comb \z80_|execute_|fMWrite~5 ( -// Equation(s): -// \z80_|execute_|fMWrite~5_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|sequencer_|DFFE_M4_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~5 .lut_mask = 16'h3F33; -defparam \z80_|execute_|fMWrite~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N8 -cycloneive_lcell_comb \z80_|execute_|fMWrite~6 ( -// Equation(s): -// \z80_|execute_|fMWrite~6_combout = (!\z80_|execute_|fMWrite~5_combout & ((\z80_|execute_|ctl_mRead~7_combout ) # ((\z80_|pla_decode_|Equal13~2_combout ) # (\z80_|execute_|ctl_mWrite~5_combout )))) - - .dataa(\z80_|execute_|fMWrite~5_combout ), - .datab(\z80_|execute_|ctl_mRead~7_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|ctl_mWrite~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~6 .lut_mask = 16'h5554; -defparam \z80_|execute_|fMWrite~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N30 -cycloneive_lcell_comb \z80_|execute_|fMWrite~2 ( -// Equation(s): -// \z80_|execute_|fMWrite~2_combout = ((!\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|M5~q ) - - .dataa(\z80_|sequencer_|M5~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~2 .lut_mask = 16'h555F; -defparam \z80_|execute_|fMWrite~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N2 -cycloneive_lcell_comb \z80_|execute_|fMWrite~4 ( -// Equation(s): -// \z80_|execute_|fMWrite~4_combout = (!\z80_|execute_|fMWrite~3_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ixy_d~6_combout ) # (!\z80_|execute_|fMWrite~2_combout )))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|execute_|fMWrite~2_combout ), - .datad(\z80_|execute_|fMWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~4 .lut_mask = 16'h00EF; -defparam \z80_|execute_|fMWrite~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N20 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~1 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~1_combout = (\z80_|execute_|ctl_bus_inc_oe~24_combout & (!\z80_|execute_|fIOWrite~5_combout & (!\z80_|execute_|fMWrite~6_combout & !\z80_|execute_|fMWrite~4_combout ))) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~24_combout ), - .datab(\z80_|execute_|fIOWrite~5_combout ), - .datac(\z80_|execute_|fMWrite~6_combout ), - .datad(\z80_|execute_|fMWrite~4_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~1 .lut_mask = 16'h0002; -defparam \z80_|pin_control_|bus_db_pin_oe~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N30 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~2 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~2_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|pla_decode_|Equal11~0_combout & ((!\z80_|execute_|ctl_mRead~8_combout ) # (!\z80_|execute_|ctl_reg_in_hi~2_combout )))) # (!\z80_|execute_|ixy_d~7_combout & -// (((!\z80_|execute_|ctl_mRead~8_combout )) # (!\z80_|execute_|ctl_reg_in_hi~2_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|execute_|ctl_mRead~8_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~2 .lut_mask = 16'h135F; -defparam \z80_|pin_control_|bus_db_pin_oe~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N24 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~3 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~3_combout = (\z80_|pin_control_|bus_db_pin_oe~2_combout & (((\z80_|execute_|ixy_d~4_combout ) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|execute_|ctl_mWrite~5_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~2_combout ), - .datab(\z80_|execute_|ctl_mWrite~5_combout ), - .datac(\z80_|execute_|ixy_d~4_combout ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~3 .lut_mask = 16'hA2AA; -defparam \z80_|pin_control_|bus_db_pin_oe~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N8 -cycloneive_lcell_comb \z80_|execute_|fMWrite~7 ( -// Equation(s): -// \z80_|execute_|fMWrite~7_combout = (!\z80_|execute_|ctl_mWrite~16_combout & (!\z80_|execute_|ctl_mWrite~4_combout & !\z80_|execute_|ctl_mRead~7_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_mWrite~16_combout ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|execute_|ctl_mRead~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~7 .lut_mask = 16'h0003; -defparam \z80_|execute_|fMWrite~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N30 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~4 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~4_combout = (\z80_|execute_|ctl_inc_dec~2_combout & ((\z80_|execute_|fMWrite~7_combout ) # ((!\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ixy_d~6_combout )))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|fMWrite~7_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|execute_|ctl_inc_dec~2_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~4 .lut_mask = 16'hCD00; -defparam \z80_|pin_control_|bus_db_pin_oe~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N10 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~7 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~7_combout = (\z80_|execute_|ctl_ir_we~4_combout & (!\z80_|execute_|ctl_mRead~10_combout & ((!\z80_|execute_|ctl_mRead~7_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|execute_|ctl_ir_we~4_combout & -// (((!\z80_|execute_|ctl_mRead~7_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ctl_mRead~10_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|execute_|ctl_mRead~7_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~7 .lut_mask = 16'h0777; -defparam \z80_|pin_control_|bus_db_pin_oe~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N4 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~6 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~6_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|execute_|ctl_mRead~6_combout & ((\z80_|execute_|fMRead~1_combout )))) # (!\z80_|execute_|ixy_d~7_combout & (((!\z80_|execute_|ctl_alu_oe~2_combout )) # -// (!\z80_|execute_|ctl_mRead~6_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|execute_|ctl_alu_oe~2_combout ), - .datad(\z80_|execute_|fMRead~1_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~6 .lut_mask = 16'h3715; -defparam \z80_|pin_control_|bus_db_pin_oe~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|fMWrite~9 ( -// Equation(s): -// \z80_|execute_|fMWrite~9_combout = (\z80_|pla_decode_|Equal46~0_combout ) # (((\z80_|ir_|opcode [6] & !\z80_|ir_|opcode [7])) # (!\z80_|execute_|ctl_ir_we~5_combout )) - - .dataa(\z80_|ir_|opcode [6]), - .datab(\z80_|pla_decode_|Equal46~0_combout ), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|execute_|ctl_ir_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~9 .lut_mask = 16'hCEFF; -defparam \z80_|execute_|fMWrite~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N22 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~8 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~8_combout = (\z80_|execute_|ctl_mWrite~6_combout & (\z80_|execute_|fIOWrite~0_combout & ((\z80_|execute_|fMWrite~2_combout ) # (\z80_|execute_|fMWrite~9_combout )))) # (!\z80_|execute_|ctl_mWrite~6_combout & -// (((\z80_|execute_|fMWrite~2_combout ) # (\z80_|execute_|fMWrite~9_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~6_combout ), - .datab(\z80_|execute_|fIOWrite~0_combout ), - .datac(\z80_|execute_|fMWrite~2_combout ), - .datad(\z80_|execute_|fMWrite~9_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~8 .lut_mask = 16'hDDD0; -defparam \z80_|pin_control_|bus_db_pin_oe~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N0 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~9 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~9_combout = (\z80_|pin_control_|bus_db_pin_oe~8_combout & (\z80_|execute_|fMWrite~11_combout & !\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout )) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~8_combout ), - .datab(\z80_|execute_|fMWrite~11_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~9 .lut_mask = 16'h0808; -defparam \z80_|pin_control_|bus_db_pin_oe~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N26 -cycloneive_lcell_comb \z80_|execute_|fMWrite~8 ( -// Equation(s): -// \z80_|execute_|fMWrite~8_combout = (\z80_|execute_|ctl_state_alu~6_combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # ((\z80_|execute_|ctl_mRead~7_combout ) # (\z80_|execute_|ctl_mRead~9_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~5_combout ), - .datab(\z80_|execute_|ctl_mRead~7_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_mRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~8 .lut_mask = 16'hF0E0; -defparam \z80_|execute_|fMWrite~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N26 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~5 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~5_combout = (\z80_|execute_|ctl_reg_sel_wz~4_combout & (\z80_|execute_|ctl_reg_sel_wz~5_combout & (!\z80_|execute_|fMWrite~8_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~4_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~5_combout ), - .datac(\z80_|execute_|fMWrite~8_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~5 .lut_mask = 16'h0800; -defparam \z80_|pin_control_|bus_db_pin_oe~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N20 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~10 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~10_combout = (\z80_|pin_control_|bus_db_pin_oe~7_combout & (\z80_|pin_control_|bus_db_pin_oe~6_combout & (\z80_|pin_control_|bus_db_pin_oe~9_combout & \z80_|pin_control_|bus_db_pin_oe~5_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~7_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~6_combout ), - .datac(\z80_|pin_control_|bus_db_pin_oe~9_combout ), - .datad(\z80_|pin_control_|bus_db_pin_oe~5_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~10 .lut_mask = 16'h8000; -defparam \z80_|pin_control_|bus_db_pin_oe~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N22 -cycloneive_lcell_comb \z80_|execute_|fMWrite~10 ( -// Equation(s): -// \z80_|execute_|fMWrite~10_combout = (\z80_|execute_|ctl_reg_in_hi~2_combout & ((\z80_|pla_decode_|Equal9~1_combout ) # ((\z80_|execute_|ctl_mRead~10_combout )))) # (!\z80_|execute_|ctl_reg_in_hi~2_combout & (\z80_|execute_|ctl_alu_oe~2_combout & -// ((\z80_|pla_decode_|Equal9~1_combout ) # (\z80_|execute_|ctl_mRead~10_combout )))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datab(\z80_|pla_decode_|Equal9~1_combout ), - .datac(\z80_|execute_|ctl_alu_oe~2_combout ), - .datad(\z80_|execute_|ctl_mRead~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~10 .lut_mask = 16'hFAC8; -defparam \z80_|execute_|fMWrite~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N0 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~11 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~11_combout = (\z80_|pin_control_|bus_db_pin_oe~4_combout & (\z80_|pin_control_|bus_db_pin_oe~10_combout & (!\z80_|execute_|fMWrite~10_combout & \z80_|execute_|ctl_bus_inc_oe~28_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~4_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~10_combout ), - .datac(\z80_|execute_|fMWrite~10_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~28_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~11 .lut_mask = 16'h0800; -defparam \z80_|pin_control_|bus_db_pin_oe~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N26 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~12 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~12_combout = (\z80_|pin_control_|bus_db_pin_oe~3_combout & (\z80_|pin_control_|bus_db_pin_oe~11_combout & ((!\z80_|execute_|ixy_d~6_combout ) # (!\z80_|pla_decode_|Equal11~0_combout )))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~3_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|pin_control_|bus_db_pin_oe~11_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~12 .lut_mask = 16'h2A00; -defparam \z80_|pin_control_|bus_db_pin_oe~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N22 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~13 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~13_combout = (\z80_|execute_|ctl_apin_mux~0_combout & (\z80_|pin_control_|bus_db_pin_oe~1_combout & (\z80_|pin_control_|bus_db_pin_oe~12_combout & \z80_|execute_|ctl_inc_cy~37_combout ))) - - .dataa(\z80_|execute_|ctl_apin_mux~0_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~1_combout ), - .datac(\z80_|pin_control_|bus_db_pin_oe~12_combout ), - .datad(\z80_|execute_|ctl_inc_cy~37_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~13 .lut_mask = 16'h8000; -defparam \z80_|pin_control_|bus_db_pin_oe~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N28 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~14 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~14_combout = (\z80_|pin_control_|bus_db_pin_oe~0_combout & (((\z80_|sequencer_|DFFE_T4_ff~q & \z80_|execute_|fIOWrite~5_combout )) # (!\z80_|pin_control_|bus_db_pin_oe~13_combout ))) # -// (!\z80_|pin_control_|bus_db_pin_oe~0_combout & (((\z80_|sequencer_|DFFE_T4_ff~q & \z80_|execute_|fIOWrite~5_combout )))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~0_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~13_combout ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|execute_|fIOWrite~5_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~14 .lut_mask = 16'hF222; -defparam \z80_|pin_control_|bus_db_pin_oe~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N0 -cycloneive_lcell_comb \z80_|clk_delay_|DFF_inst5~feeder ( -// Equation(s): -// \z80_|clk_delay_|DFF_inst5~feeder_combout = \z80_|clk_delay_|SYNTHESIZED_WIRE_7~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ), - .cin(gnd), - .combout(\z80_|clk_delay_|DFF_inst5~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|clk_delay_|DFF_inst5~feeder .lut_mask = 16'hFF00; -defparam \z80_|clk_delay_|DFF_inst5~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X43_Y15_N1 -dffeas \z80_|clk_delay_|DFF_inst5 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|clk_delay_|DFF_inst5~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|clk_delay_|DFF_inst5~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|clk_delay_|DFF_inst5 .is_wysiwyg = "true"; -defparam \z80_|clk_delay_|DFF_inst5 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N22 -cycloneive_lcell_comb \z80_|memory_ifc_|wait_iorqinta~feeder ( -// Equation(s): -// \z80_|memory_ifc_|wait_iorqinta~feeder_combout = \z80_|clk_delay_|DFF_inst5~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|clk_delay_|DFF_inst5~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|wait_iorqinta~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_iorqinta~feeder .lut_mask = 16'hFF00; -defparam \z80_|memory_ifc_|wait_iorqinta~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X43_Y15_N23 -dffeas \z80_|memory_ifc_|wait_iorqinta ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|memory_ifc_|wait_iorqinta~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|wait_iorqinta~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_iorqinta .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|wait_iorqinta .power_up = "low"; -// synopsys translate_on - -// Location: FF_X43_Y15_N13 -dffeas \z80_|memory_ifc_|DFFE_intr_ff3 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|memory_ifc_|wait_iorqinta~q ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_intr_ff3~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_intr_ff3 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_intr_ff3 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N12 -cycloneive_lcell_comb \z80_|memory_ifc_|nIORQ_out~0 ( -// Equation(s): -// \z80_|memory_ifc_|nIORQ_out~0_combout = (\z80_|memory_ifc_|wait_iorqinta~q ) # ((\z80_|memory_ifc_|DFFE_intr_ff3~q ) # (\z80_|memory_ifc_|iorq~0_combout )) - - .dataa(\z80_|memory_ifc_|wait_iorqinta~q ), - .datab(gnd), - .datac(\z80_|memory_ifc_|DFFE_intr_ff3~q ), - .datad(\z80_|memory_ifc_|iorq~0_combout ), - .cin(gnd), - .combout(\z80_|memory_ifc_|nIORQ_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|nIORQ_out~0 .lut_mask = 16'hFFFA; -defparam \z80_|memory_ifc_|nIORQ_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N18 -cycloneive_lcell_comb \Equal2~0 ( -// Equation(s): -// \Equal2~0_combout = (!\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|memory_ifc_|nRD_out~2_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \z80_|memory_ifc_|nIORQ_out~0_combout ))) - - .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), - .datab(\z80_|memory_ifc_|nRD_out~2_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|memory_ifc_|nIORQ_out~0_combout ), - .cin(gnd), - .combout(\Equal2~0_combout ), - .cout()); -// synopsys translate_off -defparam \Equal2~0 .lut_mask = 16'h4000; -defparam \Equal2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N22 -cycloneive_lcell_comb \ExtRamWE~0 ( -// Equation(s): -// \ExtRamWE~0_combout = (\z80_|memory_ifc_|nWR_out~0_combout & (!\z80_|memory_ifc_|nRD_out~2_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|memory_ifc_|nIORQ_out~0_combout ))) - - .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), - .datab(\z80_|memory_ifc_|nRD_out~2_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|memory_ifc_|nIORQ_out~0_combout ), - .cin(gnd), - .combout(\ExtRamWE~0_combout ), - .cout()); -// synopsys translate_off -defparam \ExtRamWE~0 .lut_mask = 16'h0020; -defparam \ExtRamWE~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N18 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[13]~13 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[13]~13_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [13]))) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [13]), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[13]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[13]~13 .lut_mask = 16'hDD88; -defparam \z80_|address_pins_|DFFE_apin_latch[13]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux2~0 ( -// Equation(s): -// \z80_|execute_|ctl_apin_mux2~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_apin_mux2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_apin_mux2~0 .lut_mask = 16'h0B0B; -defparam \z80_|execute_|ctl_apin_mux2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N28 -cycloneive_lcell_comb \z80_|pin_control_|bus_ab_pin_we~2 ( -// Equation(s): -// \z80_|pin_control_|bus_ab_pin_we~2_combout = (((\z80_|execute_|fMRead~35_combout ) # (\z80_|execute_|fIORead~3_combout )) # (!\z80_|pin_control_|bus_db_pin_oe~13_combout )) # (!\z80_|sequencer_|DFFE_M1_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|pin_control_|bus_db_pin_oe~13_combout ), - .datac(\z80_|execute_|fMRead~35_combout ), - .datad(\z80_|execute_|fIORead~3_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_ab_pin_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_ab_pin_we~2 .lut_mask = 16'hFFF7; -defparam \z80_|pin_control_|bus_ab_pin_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N2 -cycloneive_lcell_comb \z80_|pin_control_|bus_ab_pin_we~3 ( -// Equation(s): -// \z80_|pin_control_|bus_ab_pin_we~3_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (((!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|pin_control_|bus_ab_pin_we~2_combout )) # (!\z80_|sequencer_|DFFE_M1_ff~q ))) # (!\z80_|sequencer_|DFFE_T3_ff~q & -// (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|pin_control_|bus_ab_pin_we~2_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|pin_control_|bus_ab_pin_we~2_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_ab_pin_we~3 .lut_mask = 16'h3B0A; -defparam \z80_|pin_control_|bus_ab_pin_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N19 -dffeas \z80_|address_pins_|DFFE_apin_latch[13] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[13]~13_combout ), - .asdata(\z80_|address_latch_|Q [13]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [13]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[13] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[13] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N0 -cycloneive_lcell_comb \z80_|address_pins_|abus[13]~20 ( -// Equation(s): -// \z80_|address_pins_|abus[13]~20_combout = (\z80_|address_pins_|DFFE_apin_latch [13]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [13]), - .datab(gnd), - .datac(gnd), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\z80_|address_pins_|abus[13]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[13]~20 .lut_mask = 16'hAAFF; -defparam \z80_|address_pins_|abus[13]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N28 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[14]~14 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[14]~14_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|address [14])) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [14]))) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [14]), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[14]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[14]~14 .lut_mask = 16'hDD88; -defparam \z80_|address_pins_|DFFE_apin_latch[14]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N29 -dffeas \z80_|address_pins_|DFFE_apin_latch[14] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[14]~14_combout ), - .asdata(\z80_|address_latch_|Q [14]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [14]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[14] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[14] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N4 -cycloneive_lcell_comb \z80_|address_pins_|abus[14]~23 ( -// Equation(s): -// \z80_|address_pins_|abus[14]~23_combout = (\z80_|address_pins_|DFFE_apin_latch [14]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(gnd), - .datad(\z80_|address_pins_|DFFE_apin_latch [14]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[14]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[14]~23 .lut_mask = 16'hFF33; -defparam \z80_|address_pins_|abus[14]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N10 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[15]~15 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[15]~15_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [15]))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [15])) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|abusz [15]), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|address [15]), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[15]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[15]~15 .lut_mask = 16'hEE44; -defparam \z80_|address_pins_|DFFE_apin_latch[15]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N11 -dffeas \z80_|address_pins_|DFFE_apin_latch[15] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[15]~15_combout ), - .asdata(\z80_|address_latch_|Q [15]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [15]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[15] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[15] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y15_N12 -cycloneive_lcell_comb \z80_|address_pins_|abus[15]~22 ( -// Equation(s): -// \z80_|address_pins_|abus[15]~22_combout = (\z80_|address_pins_|DFFE_apin_latch [15]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [15]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_pins_|abus[15]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[15]~22 .lut_mask = 16'hF3F3; -defparam \z80_|address_pins_|abus[15]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N8 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2] = (\ExtRamWE~0_combout & (\z80_|address_pins_|abus[13]~20_combout & (!\z80_|address_pins_|abus[14]~23_combout & \z80_|address_pins_|abus[15]~22_combout ))) - - .dataa(\ExtRamWE~0_combout ), - .datab(\z80_|address_pins_|abus[13]~20_combout ), - .datac(\z80_|address_pins_|abus[14]~23_combout ), - .datad(\z80_|address_pins_|abus[15]~22_combout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] .lut_mask = 16'h0800; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N22 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\z80_|address_pins_|DFFE_apin_latch [13] & !\z80_|address_pins_|DFFE_apin_latch [14])) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [13]), - .datad(\z80_|address_pins_|DFFE_apin_latch [14]), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 .lut_mask = 16'h00C0; -defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N0 -cycloneive_lcell_comb \z80_|address_pins_|abus[0]~16 ( -// Equation(s): -// \z80_|address_pins_|abus[0]~16_combout = (\z80_|address_pins_|DFFE_apin_latch [0]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [0]), - .datab(gnd), - .datac(gnd), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\z80_|address_pins_|abus[0]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[0]~16 .lut_mask = 16'hAAFF; -defparam \z80_|address_pins_|abus[0]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N28 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[1]~1 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[1]~1_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [1]))) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [1]), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[1]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[1]~1 .lut_mask = 16'hDD88; -defparam \z80_|address_pins_|DFFE_apin_latch[1]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y17_N29 -dffeas \z80_|address_pins_|DFFE_apin_latch[1] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[1]~1_combout ), - .asdata(\z80_|address_latch_|Q [1]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[1] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y18_N20 -cycloneive_lcell_comb \z80_|address_pins_|abus[1]~25 ( -// Equation(s): -// \z80_|address_pins_|abus[1]~25_combout = (\z80_|address_pins_|DFFE_apin_latch [1]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_pins_|DFFE_apin_latch [1]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[1]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[1]~25 .lut_mask = 16'hFF55; -defparam \z80_|address_pins_|abus[1]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N18 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[2]~2 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[2]~2_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [2])) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|abusz [2]), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[2]~2 .lut_mask = 16'hEE44; -defparam \z80_|address_pins_|DFFE_apin_latch[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y17_N19 -dffeas \z80_|address_pins_|DFFE_apin_latch[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[2]~2_combout ), - .asdata(\z80_|address_latch_|Q [2]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[2] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y18_N26 -cycloneive_lcell_comb \z80_|address_pins_|abus[2]~26 ( -// Equation(s): -// \z80_|address_pins_|abus[2]~26_combout = (\z80_|address_pins_|DFFE_apin_latch [2]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|address_pins_|DFFE_apin_latch [2]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[2]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[2]~26 .lut_mask = 16'hFF0F; -defparam \z80_|address_pins_|abus[2]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N0 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[3]~3 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[3]~3_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [3])) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|abusz [3]), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[3]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[3]~3 .lut_mask = 16'hEE44; -defparam \z80_|address_pins_|DFFE_apin_latch[3]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y17_N1 -dffeas \z80_|address_pins_|DFFE_apin_latch[3] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[3]~3_combout ), - .asdata(\z80_|address_latch_|Q [3]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[3] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y18_N12 -cycloneive_lcell_comb \z80_|address_pins_|abus[3]~27 ( -// Equation(s): -// \z80_|address_pins_|abus[3]~27_combout = (\z80_|address_pins_|DFFE_apin_latch [3]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|address_pins_|DFFE_apin_latch [3]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[3]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[3]~27 .lut_mask = 16'hFF0F; -defparam \z80_|address_pins_|abus[3]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N30 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[4]~4 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[4]~4_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [4])) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|abusz [4]), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[4]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[4]~4 .lut_mask = 16'hEE44; -defparam \z80_|address_pins_|DFFE_apin_latch[4]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y17_N31 -dffeas \z80_|address_pins_|DFFE_apin_latch[4] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[4]~4_combout ), - .asdata(\z80_|address_latch_|Q [4]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[4] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y18_N2 -cycloneive_lcell_comb \z80_|address_pins_|abus[4]~28 ( -// Equation(s): -// \z80_|address_pins_|abus[4]~28_combout = (\z80_|address_pins_|DFFE_apin_latch [4]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|address_pins_|DFFE_apin_latch [4]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[4]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[4]~28 .lut_mask = 16'hFF0F; -defparam \z80_|address_pins_|abus[4]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N12 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[5]~5 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[5]~5_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [5])) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|abusz [5]), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[5]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[5]~5 .lut_mask = 16'hEE44; -defparam \z80_|address_pins_|DFFE_apin_latch[5]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y16_N13 -dffeas \z80_|address_pins_|DFFE_apin_latch[5] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[5]~5_combout ), - .asdata(\z80_|address_latch_|Q [5]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[5] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N20 -cycloneive_lcell_comb \z80_|address_pins_|abus[5]~29 ( -// Equation(s): -// \z80_|address_pins_|abus[5]~29_combout = (\z80_|address_pins_|DFFE_apin_latch [5]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [5]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_pins_|abus[5]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[5]~29 .lut_mask = 16'hF3F3; -defparam \z80_|address_pins_|abus[5]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N10 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[6]~6 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[6]~6_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [6]))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [6])) - - .dataa(\z80_|address_latch_|abusz [6]), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), - .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[6]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[6]~6 .lut_mask = 16'hCCAA; -defparam \z80_|address_pins_|DFFE_apin_latch[6]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y16_N11 -dffeas \z80_|address_pins_|DFFE_apin_latch[6] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[6]~6_combout ), - .asdata(\z80_|address_latch_|Q [6]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[6] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y18_N28 -cycloneive_lcell_comb \z80_|address_pins_|abus[6]~30 ( -// Equation(s): -// \z80_|address_pins_|abus[6]~30_combout = (\z80_|address_pins_|DFFE_apin_latch [6]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|address_pins_|DFFE_apin_latch [6]), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_pins_|abus[6]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[6]~30 .lut_mask = 16'hCFCF; -defparam \z80_|address_pins_|abus[6]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N30 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[7]~7 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[7]~7_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [7])) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|abusz [7]), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[7]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[7]~7 .lut_mask = 16'hEE44; -defparam \z80_|address_pins_|DFFE_apin_latch[7]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y16_N31 -dffeas \z80_|address_pins_|DFFE_apin_latch[7] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[7]~7_combout ), - .asdata(\z80_|address_latch_|Q [7]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[7] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y18_N22 -cycloneive_lcell_comb \z80_|address_pins_|abus[7]~31 ( -// Equation(s): -// \z80_|address_pins_|abus[7]~31_combout = (\z80_|address_pins_|DFFE_apin_latch [7]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|address_pins_|DFFE_apin_latch [7]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[7]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[7]~31 .lut_mask = 16'hFF0F; -defparam \z80_|address_pins_|abus[7]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N20 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[8]~8 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[8]~8_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [8])) - - .dataa(\z80_|address_latch_|abusz [8]), - .datab(\z80_|execute_|ctl_apin_mux~2_combout ), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[8]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[8]~8 .lut_mask = 16'hEE22; -defparam \z80_|address_pins_|DFFE_apin_latch[8]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y16_N21 -dffeas \z80_|address_pins_|DFFE_apin_latch[8] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[8]~8_combout ), - .asdata(\z80_|address_latch_|Q [8]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [8]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[8] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N30 -cycloneive_lcell_comb \z80_|address_pins_|abus[8]~18 ( -// Equation(s): -// \z80_|address_pins_|abus[8]~18_combout = (\z80_|address_pins_|DFFE_apin_latch [8]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|address_pins_|DFFE_apin_latch [8]), - .datac(gnd), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\z80_|address_pins_|abus[8]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[8]~18 .lut_mask = 16'hCCFF; -defparam \z80_|address_pins_|abus[8]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N16 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[9]~9 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[9]~9_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [9]))) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [9]), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[9]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[9]~9 .lut_mask = 16'hDD88; -defparam \z80_|address_pins_|DFFE_apin_latch[9]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N17 -dffeas \z80_|address_pins_|DFFE_apin_latch[9] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[9]~9_combout ), - .asdata(\z80_|address_latch_|Q [9]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [9]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[9] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[9] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y18_N4 -cycloneive_lcell_comb \z80_|address_pins_|abus[9]~17 ( -// Equation(s): -// \z80_|address_pins_|abus[9]~17_combout = (\z80_|address_pins_|DFFE_apin_latch [9]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|address_pins_|DFFE_apin_latch [9]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[9]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[9]~17 .lut_mask = 16'hFF0F; -defparam \z80_|address_pins_|abus[9]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N24 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[10]~10 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[10]~10_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [10]))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), - .datab(\z80_|address_latch_|abusz [10]), - .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[10]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[10]~10 .lut_mask = 16'hAACC; -defparam \z80_|address_pins_|DFFE_apin_latch[10]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N25 -dffeas \z80_|address_pins_|DFFE_apin_latch[10] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[10]~10_combout ), - .asdata(\z80_|address_latch_|Q [10]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [10]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[10] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[10] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N24 -cycloneive_lcell_comb \z80_|address_pins_|abus[10]~24 ( -// Equation(s): -// \z80_|address_pins_|abus[10]~24_combout = (\z80_|address_pins_|DFFE_apin_latch [10]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|address_pins_|DFFE_apin_latch [10]), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\z80_|address_pins_|abus[10]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[10]~24 .lut_mask = 16'hF0FF; -defparam \z80_|address_pins_|abus[10]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N6 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[11]~11 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[11]~11_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|address [11])) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [11]))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), - .datab(\z80_|address_latch_|abusz [11]), - .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[11]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[11]~11 .lut_mask = 16'hAACC; -defparam \z80_|address_pins_|DFFE_apin_latch[11]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N7 -dffeas \z80_|address_pins_|DFFE_apin_latch[11] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[11]~11_combout ), - .asdata(\z80_|address_latch_|Q [11]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [11]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[11] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[11] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N8 -cycloneive_lcell_comb \z80_|address_pins_|abus[11]~19 ( -// Equation(s): -// \z80_|address_pins_|abus[11]~19_combout = (\z80_|address_pins_|DFFE_apin_latch [11]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [11]), - .datab(gnd), - .datac(gnd), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\z80_|address_pins_|abus[11]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[11]~19 .lut_mask = 16'hAAFF; -defparam \z80_|address_pins_|abus[11]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N16 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[12]~12 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[12]~12_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [12])) - - .dataa(\z80_|address_latch_|abusz [12]), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[12]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[12]~12 .lut_mask = 16'hCCAA; -defparam \z80_|address_pins_|DFFE_apin_latch[12]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N17 -dffeas \z80_|address_pins_|DFFE_apin_latch[12] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[12]~12_combout ), - .asdata(\z80_|address_latch_|Q [12]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [12]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[12] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[12] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y18_N30 -cycloneive_lcell_comb \z80_|address_pins_|abus[12]~21 ( -// Equation(s): -// \z80_|address_pins_|abus[12]~21_combout = (\z80_|address_pins_|DFFE_apin_latch [12]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_pins_|DFFE_apin_latch [12]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[12]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[12]~21 .lut_mask = 16'hFF55; -defparam \z80_|address_pins_|abus[12]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y11_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a14 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~101_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: FF_X32_Y14_N31 -dffeas \ram1|altsyncram_component|auto_generated|address_reg_a[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|address_pins_|abus[13]~20_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram1|altsyncram_component|auto_generated|address_reg_a [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true"; -defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X32_Y14_N1 -dffeas \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ram1|altsyncram_component|auto_generated|address_reg_a [0]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true"; -defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N12 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2] = (\ExtRamWE~0_combout & (!\z80_|address_pins_|abus[13]~20_combout & (!\z80_|address_pins_|abus[14]~23_combout & \z80_|address_pins_|abus[15]~22_combout ))) - - .dataa(\ExtRamWE~0_combout ), - .datab(\z80_|address_pins_|abus[13]~20_combout ), - .datac(\z80_|address_pins_|abus[14]~23_combout ), - .datad(\z80_|address_pins_|abus[15]~22_combout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] .lut_mask = 16'h0200; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N18 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (!\z80_|address_pins_|DFFE_apin_latch [13] & !\z80_|address_pins_|DFFE_apin_latch [14])) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [13]), - .datad(\z80_|address_pins_|DFFE_apin_latch [14]), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 .lut_mask = 16'h000C; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y10_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a6 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~101_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; -// synopsys translate_on - -// Location: FF_X29_Y14_N5 -dffeas \ram1|altsyncram_component|auto_generated|address_reg_a[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|address_pins_|abus[14]~23_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram1|altsyncram_component|auto_generated|address_reg_a [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1] .is_wysiwyg = "true"; -defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y14_N21 -dffeas \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ram1|altsyncram_component|auto_generated|address_reg_a [1]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] .is_wysiwyg = "true"; -defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N24 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2] = (\ExtRamWE~0_combout & (!\z80_|address_pins_|abus[13]~20_combout & (\z80_|address_pins_|abus[14]~23_combout & \z80_|address_pins_|abus[15]~22_combout ))) - - .dataa(\ExtRamWE~0_combout ), - .datab(\z80_|address_pins_|abus[13]~20_combout ), - .datac(\z80_|address_pins_|abus[14]~23_combout ), - .datad(\z80_|address_pins_|abus[15]~22_combout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] .lut_mask = 16'h2000; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N26 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (!\z80_|address_pins_|DFFE_apin_latch [13] & \z80_|address_pins_|DFFE_apin_latch [14])) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [13]), - .datad(\z80_|address_pins_|DFFE_apin_latch [14]), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 .lut_mask = 16'h0C00; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y10_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a22 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~101_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_first_bit_number = 6; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N10 -cycloneive_lcell_comb \D[6]~90 ( -// Equation(s): -// \D[6]~90_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ) # (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout & ((!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ), - .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .cin(gnd), - .combout(\D[6]~90_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~90 .lut_mask = 16'hCCE2; -defparam \D[6]~90 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N20 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2] = (\ExtRamWE~0_combout & (\z80_|address_pins_|abus[13]~20_combout & (\z80_|address_pins_|abus[14]~23_combout & \z80_|address_pins_|abus[15]~22_combout ))) - - .dataa(\ExtRamWE~0_combout ), - .datab(\z80_|address_pins_|abus[13]~20_combout ), - .datac(\z80_|address_pins_|abus[14]~23_combout ), - .datad(\z80_|address_pins_|abus[15]~22_combout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] .lut_mask = 16'h8000; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N6 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout = ((\z80_|address_pins_|DFFE_apin_latch [13] & \z80_|address_pins_|DFFE_apin_latch [14])) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [13]), - .datad(\z80_|address_pins_|DFFE_apin_latch [14]), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 .lut_mask = 16'hF333; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y6_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a30 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~101_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_first_bit_number = 6; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N16 -cycloneive_lcell_comb \D[6]~91 ( -// Equation(s): -// \D[6]~91_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[6]~90_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ))) # (!\D[6]~90_combout & -// (\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[6]~90_combout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\D[6]~90_combout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ), - .cin(gnd), - .combout(\D[6]~91_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~91 .lut_mask = 16'hF838; -defparam \D[6]~91 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N2 -cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0 ( -// Equation(s): -// \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout = (\ExtRamWE~0_combout & (!\z80_|address_pins_|abus[13]~20_combout & (\z80_|address_pins_|abus[14]~23_combout & !\z80_|address_pins_|abus[15]~22_combout ))) - - .dataa(\ExtRamWE~0_combout ), - .datab(\z80_|address_pins_|abus[13]~20_combout ), - .datac(\z80_|address_pins_|abus[14]~23_combout ), - .datad(\z80_|address_pins_|abus[15]~22_combout ), - .cin(gnd), - .combout(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0 .lut_mask = 16'h0020; -defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: CLKCTRL_G15 -cycloneive_clkctrl \CLOCK_50~inputclkctrl ( - .ena(vcc), - .inclk({vcc,vcc,vcc,\CLOCK_50~input_o }), - .clkselect(2'b00), - .devclrn(devclrn), - .devpor(devpor), - .outclk(\CLOCK_50~inputclkctrl_outclk )); -// synopsys translate_off -defparam \CLOCK_50~inputclkctrl .clock_type = "global clock"; -defparam \CLOCK_50~inputclkctrl .ena_register_mode = "none"; -// synopsys translate_on - -// Location: LCCOMB_X5_Y24_N16 -cycloneive_lcell_comb \~GND ( -// Equation(s): -// \~GND~combout = GND - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(gnd), - .cin(gnd), - .combout(\~GND~combout ), - .cout()); -// synopsys translate_off -defparam \~GND .lut_mask = 16'h0000; -defparam \~GND .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N20 -cycloneive_lcell_comb \ula_|video_|vram_address[0]~feeder ( -// Equation(s): -// \ula_|video_|vram_address[0]~feeder_combout = \ula_|video_|vga_hc [4] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|vga_hc [4]), - .cin(gnd), - .combout(\ula_|video_|vram_address[0]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address[0]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|vram_address[0]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N4 -cycloneive_lcell_comb \ula_|video_|vram_address~0 ( -// Equation(s): -// \ula_|video_|vram_address~0_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [2] $ (\ula_|video_|vga_hc [1])))) - - .dataa(\ula_|video_|vga_hc [2]), - .datab(\ula_|video_|vga_hc [3]), - .datac(\ula_|video_|vga_hc [1]), - .datad(\ula_|video_|vga_hc [0]), - .cin(gnd), - .combout(\ula_|video_|vram_address~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address~0 .lut_mask = 16'h0048; -defparam \ula_|video_|vram_address~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y33_N21 -dffeas \ula_|video_|vram_address[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vram_address[0]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[0] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X34_Y33_N19 -dffeas \ula_|video_|vram_address[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|vga_hc [5]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[1] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N0 -cycloneive_lcell_comb \ula_|video_|vram_address[2]~4 ( -// Equation(s): -// \ula_|video_|vram_address[2]~4_combout = !\ula_|video_|vga_hc [6] - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|video_|vga_hc [6]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|video_|vram_address[2]~4_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address[2]~4 .lut_mask = 16'h0F0F; -defparam \ula_|video_|vram_address[2]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y33_N1 -dffeas \ula_|video_|vram_address[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vram_address[2]~4_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[2] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N26 -cycloneive_lcell_comb \ula_|video_|Add3~0 ( -// Equation(s): -// \ula_|video_|Add3~0_combout = \ula_|video_|vga_hc [6] $ (\ula_|video_|vga_hc [7]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|video_|vga_hc [6]), - .datad(\ula_|video_|vga_hc [7]), - .cin(gnd), - .combout(\ula_|video_|Add3~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Add3~0 .lut_mask = 16'h0FF0; -defparam \ula_|video_|Add3~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y33_N27 -dffeas \ula_|video_|vram_address[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Add3~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[3] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N28 -cycloneive_lcell_comb \ula_|video_|Add3~1 ( -// Equation(s): -// \ula_|video_|Add3~1_combout = \ula_|video_|vga_hc [8] $ (((!\ula_|video_|vga_hc [7]) # (!\ula_|video_|vga_hc [6]))) - - .dataa(\ula_|video_|vga_hc [6]), - .datab(gnd), - .datac(\ula_|video_|vga_hc [8]), - .datad(\ula_|video_|vga_hc [7]), - .cin(gnd), - .combout(\ula_|video_|Add3~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Add3~1 .lut_mask = 16'hA50F; -defparam \ula_|video_|Add3~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y33_N29 -dffeas \ula_|video_|vram_address[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Add3~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[4] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N2 -cycloneive_lcell_comb \ula_|video_|Add4~0 ( -// Equation(s): -// \ula_|video_|Add4~0_combout = (\ula_|video_|vga_vc [0] & (\ula_|video_|vga_vc [1] $ (VCC))) # (!\ula_|video_|vga_vc [0] & (\ula_|video_|vga_vc [1] & VCC)) -// \ula_|video_|Add4~1 = CARRY((\ula_|video_|vga_vc [0] & \ula_|video_|vga_vc [1])) - - .dataa(\ula_|video_|vga_vc [0]), - .datab(\ula_|video_|vga_vc [1]), - .datac(gnd), - .datad(vcc), - .cin(gnd), - .combout(\ula_|video_|Add4~0_combout ), - .cout(\ula_|video_|Add4~1 )); -// synopsys translate_off -defparam \ula_|video_|Add4~0 .lut_mask = 16'h6688; -defparam \ula_|video_|Add4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N4 -cycloneive_lcell_comb \ula_|video_|Add4~2 ( -// Equation(s): -// \ula_|video_|Add4~2_combout = (\ula_|video_|vga_vc [2] & (\ula_|video_|Add4~1 & VCC)) # (!\ula_|video_|vga_vc [2] & (!\ula_|video_|Add4~1 )) -// \ula_|video_|Add4~3 = CARRY((!\ula_|video_|vga_vc [2] & !\ula_|video_|Add4~1 )) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [2]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~1 ), - .combout(\ula_|video_|Add4~2_combout ), - .cout(\ula_|video_|Add4~3 )); -// synopsys translate_off -defparam \ula_|video_|Add4~2 .lut_mask = 16'hC303; -defparam \ula_|video_|Add4~2 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N6 -cycloneive_lcell_comb \ula_|video_|Add4~4 ( -// Equation(s): -// \ula_|video_|Add4~4_combout = (\ula_|video_|vga_vc [3] & ((GND) # (!\ula_|video_|Add4~3 ))) # (!\ula_|video_|vga_vc [3] & (\ula_|video_|Add4~3 $ (GND))) -// \ula_|video_|Add4~5 = CARRY((\ula_|video_|vga_vc [3]) # (!\ula_|video_|Add4~3 )) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [3]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~3 ), - .combout(\ula_|video_|Add4~4_combout ), - .cout(\ula_|video_|Add4~5 )); -// synopsys translate_off -defparam \ula_|video_|Add4~4 .lut_mask = 16'h3CCF; -defparam \ula_|video_|Add4~4 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N8 -cycloneive_lcell_comb \ula_|video_|Add4~6 ( -// Equation(s): -// \ula_|video_|Add4~6_combout = (\ula_|video_|vga_vc [4] & (!\ula_|video_|Add4~5 )) # (!\ula_|video_|vga_vc [4] & ((\ula_|video_|Add4~5 ) # (GND))) -// \ula_|video_|Add4~7 = CARRY((!\ula_|video_|Add4~5 ) # (!\ula_|video_|vga_vc [4])) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [4]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~5 ), - .combout(\ula_|video_|Add4~6_combout ), - .cout(\ula_|video_|Add4~7 )); -// synopsys translate_off -defparam \ula_|video_|Add4~6 .lut_mask = 16'h3C3F; -defparam \ula_|video_|Add4~6 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X34_Y33_N9 -dffeas \ula_|video_|vram_address[5] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Add4~6_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[5] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N10 -cycloneive_lcell_comb \ula_|video_|Add4~8 ( -// Equation(s): -// \ula_|video_|Add4~8_combout = (\ula_|video_|vga_vc [5] & ((GND) # (!\ula_|video_|Add4~7 ))) # (!\ula_|video_|vga_vc [5] & (\ula_|video_|Add4~7 $ (GND))) -// \ula_|video_|Add4~9 = CARRY((\ula_|video_|vga_vc [5]) # (!\ula_|video_|Add4~7 )) - - .dataa(\ula_|video_|vga_vc [5]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~7 ), - .combout(\ula_|video_|Add4~8_combout ), - .cout(\ula_|video_|Add4~9 )); -// synopsys translate_off -defparam \ula_|video_|Add4~8 .lut_mask = 16'h5AAF; -defparam \ula_|video_|Add4~8 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X34_Y33_N11 -dffeas \ula_|video_|vram_address[6] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Add4~8_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[6] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N12 -cycloneive_lcell_comb \ula_|video_|Add4~10 ( -// Equation(s): -// \ula_|video_|Add4~10_combout = (\ula_|video_|vga_vc [6] & (!\ula_|video_|Add4~9 )) # (!\ula_|video_|vga_vc [6] & ((\ula_|video_|Add4~9 ) # (GND))) -// \ula_|video_|Add4~11 = CARRY((!\ula_|video_|Add4~9 ) # (!\ula_|video_|vga_vc [6])) - - .dataa(\ula_|video_|vga_vc [6]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~9 ), - .combout(\ula_|video_|Add4~10_combout ), - .cout(\ula_|video_|Add4~11 )); -// synopsys translate_off -defparam \ula_|video_|Add4~10 .lut_mask = 16'h5A5F; -defparam \ula_|video_|Add4~10 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X34_Y33_N13 -dffeas \ula_|video_|vram_address[7] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Add4~10_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[7] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N14 -cycloneive_lcell_comb \ula_|video_|Add4~12 ( -// Equation(s): -// \ula_|video_|Add4~12_combout = (\ula_|video_|vga_vc [7] & ((GND) # (!\ula_|video_|Add4~11 ))) # (!\ula_|video_|vga_vc [7] & (\ula_|video_|Add4~11 $ (GND))) -// \ula_|video_|Add4~13 = CARRY((\ula_|video_|vga_vc [7]) # (!\ula_|video_|Add4~11 )) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [7]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~11 ), - .combout(\ula_|video_|Add4~12_combout ), - .cout(\ula_|video_|Add4~13 )); -// synopsys translate_off -defparam \ula_|video_|Add4~12 .lut_mask = 16'h3CCF; -defparam \ula_|video_|Add4~12 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N22 -cycloneive_lcell_comb \ula_|video_|Selector6~0 ( -// Equation(s): -// \ula_|video_|Selector6~0_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|Add4~12_combout )) # (!\ula_|video_|vga_hc [2] & ((\ula_|video_|Add4~0_combout ))) - - .dataa(gnd), - .datab(\ula_|video_|Add4~12_combout ), - .datac(\ula_|video_|Add4~0_combout ), - .datad(\ula_|video_|vga_hc [2]), - .cin(gnd), - .combout(\ula_|video_|Selector6~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Selector6~0 .lut_mask = 16'hCCF0; -defparam \ula_|video_|Selector6~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N14 -cycloneive_lcell_comb \ula_|video_|vram_address[9]~1 ( -// Equation(s): -// \ula_|video_|vram_address[9]~1_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [2] $ (\ula_|video_|vga_hc [1])))) - - .dataa(\ula_|video_|vga_hc [2]), - .datab(\ula_|video_|vga_hc [3]), - .datac(\ula_|video_|vga_hc [1]), - .datad(\ula_|video_|vga_hc [0]), - .cin(gnd), - .combout(\ula_|video_|vram_address[9]~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address[9]~1 .lut_mask = 16'h0048; -defparam \ula_|video_|vram_address[9]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y31_N23 -dffeas \ula_|video_|vram_address[8] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Selector6~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address[9]~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [8]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[8] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N16 -cycloneive_lcell_comb \ula_|video_|Add4~14 ( -// Equation(s): -// \ula_|video_|Add4~14_combout = \ula_|video_|Add4~13 $ (!\ula_|video_|vga_vc [8]) - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|vga_vc [8]), - .cin(\ula_|video_|Add4~13 ), - .combout(\ula_|video_|Add4~14_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Add4~14 .lut_mask = 16'hF00F; -defparam \ula_|video_|Add4~14 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N20 -cycloneive_lcell_comb \ula_|video_|Selector5~0 ( -// Equation(s): -// \ula_|video_|Selector5~0_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|Add4~14_combout )) # (!\ula_|video_|vga_hc [2] & ((\ula_|video_|Add4~2_combout ))) - - .dataa(\ula_|video_|Add4~14_combout ), - .datab(gnd), - .datac(\ula_|video_|Add4~2_combout ), - .datad(\ula_|video_|vga_hc [2]), - .cin(gnd), - .combout(\ula_|video_|Selector5~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Selector5~0 .lut_mask = 16'hAAF0; -defparam \ula_|video_|Selector5~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y31_N21 -dffeas \ula_|video_|vram_address[9] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Selector5~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address[9]~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [9]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[9] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[9] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N28 -cycloneive_lcell_comb \ula_|video_|vram_address[10]~2 ( -// Equation(s): -// \ula_|video_|vram_address[10]~2_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [2] $ (\ula_|video_|vga_hc [1])))) - - .dataa(\ula_|video_|vga_hc [2]), - .datab(\ula_|video_|vga_hc [3]), - .datac(\ula_|video_|vga_hc [1]), - .datad(\ula_|video_|vga_hc [0]), - .cin(gnd), - .combout(\ula_|video_|vram_address[10]~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address[10]~2 .lut_mask = 16'h0048; -defparam \ula_|video_|vram_address[10]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N30 -cycloneive_lcell_comb \ula_|video_|vram_address[10]~3 ( -// Equation(s): -// \ula_|video_|vram_address[10]~3_combout = (\ula_|video_|vram_address[10]~2_combout & (\ula_|video_|Add4~4_combout & (\ula_|video_|vga_hc [1]))) # (!\ula_|video_|vram_address[10]~2_combout & (((\ula_|video_|vram_address [10])))) - - .dataa(\ula_|video_|Add4~4_combout ), - .datab(\ula_|video_|vga_hc [1]), - .datac(\ula_|video_|vram_address [10]), - .datad(\ula_|video_|vram_address[10]~2_combout ), - .cin(gnd), - .combout(\ula_|video_|vram_address[10]~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address[10]~3 .lut_mask = 16'h88F0; -defparam \ula_|video_|vram_address[10]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y31_N31 -dffeas \ula_|video_|vram_address[10] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vram_address[10]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [10]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[10] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[10] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N16 -cycloneive_lcell_comb \ula_|video_|Selector3~0 ( -// Equation(s): -// \ula_|video_|Selector3~0_combout = (\ula_|video_|Add4~12_combout ) # (\ula_|video_|vga_hc [2]) - - .dataa(gnd), - .datab(\ula_|video_|Add4~12_combout ), - .datac(gnd), - .datad(\ula_|video_|vga_hc [2]), - .cin(gnd), - .combout(\ula_|video_|Selector3~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Selector3~0 .lut_mask = 16'hFFCC; -defparam \ula_|video_|Selector3~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y31_N17 -dffeas \ula_|video_|vram_address[11] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Selector3~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address[9]~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [11]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[11] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[11] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N26 -cycloneive_lcell_comb \ula_|video_|Selector2~0 ( -// Equation(s): -// \ula_|video_|Selector2~0_combout = (\ula_|video_|Add4~14_combout ) # (\ula_|video_|vga_hc [2]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|video_|Add4~14_combout ), - .datad(\ula_|video_|vga_hc [2]), - .cin(gnd), - .combout(\ula_|video_|Selector2~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Selector2~0 .lut_mask = 16'hFFF0; -defparam \ula_|video_|Selector2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y31_N27 -dffeas \ula_|video_|vram_address[12] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Selector2~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address[9]~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [12]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[12] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[12] .power_up = "low"; -// synopsys translate_on - -// Location: M9K_X33_Y27_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a6 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~101_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_first_bit_number = 6; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFFFFFEBFFFFFFFFFFFFFFFFFFFFFFFBFFFFFFFFFFFFFFFFFDFFFFFFFFFFFFFBFFFFFFFFFEFFFFFFFDFFFFFFFFFFFFFEFFFFFFFDF8FFFFFFF9FFFFFFFFFFFFFFFF3FFFFFFE7FFFFFFFFFFFFFFFF; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000380001887600094C977486989000000000000000000000000FFFFFFFFC0810205C00018C36DC09CF97749EDCD00000000000000000000000000000001FFFFFFFDC004000B6D028BF17749ED8100000000000000000000000000000001BF7EFDF9400404A96D8289B57549FFC10000000000000000000000003F7EFDF90000000140041EB16D8298357DC9F7410000000000000000000000007FFFFFFD8000000340043AB160021E757DC9134100000000000000000000000040810207BFFFFFFF5FE430497702760D60099349000000000000000000000000408102073FFFFFFD5FE40E49774240C96009735D; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h5FE8334948F827C15FF88F8169A80ECB609EAD417A698FC178F33E8171F72A915FE836E948F807C95FF88F81E9A80FC7639E1FC17B2BBEC170730F8D70F7B0C1400826E548B807C95FF88F95E8280FCB63C6BCC17B3B3FC171AB3E81708734C1400826ED58F8258159F88B8168280FC161629DC17A3B3F41738B3F8150AF16E9400826ED581805C151D88A8160682FC1422297C17A2A39C162FB378550CF10A1400826ED58182581D1580B8761EC2FC14232B7C179AA39C5627B7781D0CF10D3400826E158182D81F0488A4B61EC0DC143789FC17BBB39C1610B7F81D45F11D34008A7E958080D01F0088A4160B42DD143689FC17B9B398561837F81D41702B1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h50DF086350368F0151C688016801460157EDE81148F310013FFFFFFF40810103D2D70D4B50168F0141D6C8116C01462153EDA90148F31D01BFFFFFFF40810107D2D7296354D68501403EC0016C01482173FDA08148F11F01800000037FFFFFFD4297893154DE81054022D2116C014D6153FCA00148D10F01000000013F7EFEF9429F810150CEC10143E042016C014C09537DA00148D11F01BF7EFEF900000001469F833150168D0543E04A116F014DA15379B181C8511F03FFFFFFFD00000001449AAB2155368D01482046016F416CA15079B001C8513E03C0810105FFFFFFFF403A8B0155C685014800461167476CA15039B08180413E0500000007FFFFFFFF; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N22 -cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder ( -// Equation(s): -// \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout = \z80_|address_pins_|abus[13]~20_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_pins_|abus[13]~20_combout ), - .cin(gnd), - .combout(\ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder .lut_mask = 16'hFF00; -defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y14_N23 -dffeas \ram0|altsyncram_component|auto_generated|address_reg_a[0] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram0|altsyncram_component|auto_generated|address_reg_a [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true"; -defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y14_N1 -dffeas \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(gnd), - .asdata(\ram0|altsyncram_component|auto_generated|address_reg_a [0]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true"; -defparam \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N10 -cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1 ( -// Equation(s): -// \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout = (\ExtRamWE~0_combout & (\z80_|address_pins_|abus[13]~20_combout & (\z80_|address_pins_|abus[14]~23_combout & !\z80_|address_pins_|abus[15]~22_combout ))) - - .dataa(\ExtRamWE~0_combout ), - .datab(\z80_|address_pins_|abus[13]~20_combout ), - .datac(\z80_|address_pins_|abus[14]~23_combout ), - .datad(\z80_|address_pins_|abus[15]~22_combout ), - .cin(gnd), - .combout(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .cout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1 .lut_mask = 16'h0080; -defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y25_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a14 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(gnd), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~101_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_first_bit_number = 6; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y33_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a14 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h4200420000441C443C0C3C00480018FC387C7C000000007E180038300000204880084204004204423E1E3E02247E3C7E3C7E7E7E7E30007E3C7E7E7E3C7E7C3C0400000000000C34023C2E302464003C00000000000000000020460024000000FF991E65536D2D8D9C9B4DB081C83A5A881B0DFDE2D72DF0FA08FCD6F664173D989098D02025E0F6043B4B9080F4923880C3A3B02D269E730C3DCC423386DCB98B4AD0C5C8D6119602E5121008325B7457090E914F4876EC8A18C664210A4C2392C7658400073421047C75FBE7BE73FDFFF05FEE07BF8AEF7F1378B359E8C61F8F692C2218C98A4A8748531986E7C770D984E0000C02060C000C0DF50F68A580; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h0100046606572583002086010800054C0F2DE8371AC0000A9003E024840C7C0806F6612D770080980A40D293FEC069F16CB2164CA033C539F69B37741AEF1CE3662FF5DF9CB107BB23A39EF7B95E7372200448DBDC18F9C0DE0EF379BF49480657781E91788044213E091339886F337D0612CA646CD48FC58EE77EDD7ECEC466C744FD00E1A7F9E9FBFE4777FD50ABD11F0E57FF4808802282200888A20AA88000000008800AC11D556264251ECFA68C056FBCCB040C614A6850222300D2F6FF59F878FCF5689FCFEF34BFD52FA2422A56A3C113409F7813007F8D6B5F80FE9D7FB1E62675F7C2CBE01032DCA16BADC570C1CBF7ECBC4E7E6C54A5D4550BE1A8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'hE33CB578DEBFAFAEDFD530DE8FA1992072F31B116644B18C72F9F44116C79ADF2F3982C7BE09AD4A32196807648A2495ADF98FD2B16CC096A5E25F5BC811C953CEC3000F432029B3FE3F211712944CA54D1940F193204C199C9F49666CC11B38C23B9D130CA49818913D3A2C1FBF71C5B0C774336F903C677D976189D98CA127AAAD6B6AF36195DA637C6EFA3E36E8FE97FA02EC26EB46198AD8DAD8C11260AF499D7BD86619EE5574CD27C80D39F71E653FDCF1B366737233CBB98D1E7B330F7DCCFC5939C4EC79CF0E1CD43BA7AFC716900A21BDB9DD0FCC7ECE1063238407C7E1B221EA10E38F64EF31CEBF3368E1C712BB1B33781134CFE54C2123349A6E; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h5F9CB25A3631964C20007FF5754FC631A97D4F93986C30CF24394625658DE9A7C228A2050470925E29A35D8D06242712CD25C9241898204D85A710947C802013E1265727652C8F0C422BA8C28A0FBB893B0881E00403DDD8843B2D8EB929D0D8CB76E03779E019E2C4E4028219C38C202C9384E0D24E569C2E4D4D60B670CE37414D536A41D144B6C4624A2B00366D8CF6734A4A2DC465B308462CCBD1BF9CB863FC93EDB2CA5DC61B01639318985C88F01680E307C42311C0124700B28BF9B4FF7CCCEFE1996DE3ED6D8CFBF1871BD98EE7646242664EB2E338BD009838637124C921BB3332DC66D9C1706B6C48C3129639A3BA4088EDB496EDBBBFC2CC40B6; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N2 -cycloneive_lcell_comb \D[6]~87 ( -// Equation(s): -// \D[6]~87_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))) # (!\z80_|address_pins_|abus[14]~23_combout -// & (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout )))) - - .dataa(\z80_|address_pins_|abus[14]~23_combout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout ), - .datad(\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ), - .cin(gnd), - .combout(\D[6]~87_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~87 .lut_mask = 16'hE6A2; -defparam \D[6]~87 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y1_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a6 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h3C766E63DB6481CB39BC8C68831C724633186CC1BAE9D608A5DEF0FF219C28C1EFF4FDE394D0E19B6FD89186C23CF071E6F1CC8F7FC4F1E48756B0DCD8ED6D0C3DA139003D7A86B2F878DD99DAFB70DE1A19F3FB7DB3B8EF2633007664CB19992E43664448EFF06072648DBA32EDB76E26439BCCEF2DFBF664594B04FBAE72A84A3E508B49DC6BEAAB4F3F0CCCF6D8F568F2DA00EB384A7F53249323198000100408002024010408824080002008011482ED5615E40012EE630C3B2CDB2C13A736DB5B7BD2850018CF936621C6863095A73F7BE7442CB13110B9C0BBB96EEF16CE618EEDCFB393738178C476C367909F71307F6803F677575763DB2D8C3118E4; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h881331ED7AC4EFD38DFACDBB236790005719AEA2FAECCF0D126A30A27222D61BBA428334561F4EDB60C6BF8DB6E267BC56CB69BBCE636CCCB3B2B4B103CC46D5CEEC06DAECB0001569589D5F267AFE086C8FED5DE41DFEFF027DFDFF7FFBFBFDFFDFFF6FFFBDFFDFFF57FF7F7FB7FBBDFBDFFDBFF78FFDBFFEDDFFFDFFFEFF6FF7F7FDDFFEDFF6FF7FFEEFFEFEFC4E51EC0888848E1F2044B47B66608D8A3B3919B9466E6D60D27565964244B218B48AD83430D996068EC908D9E112096996041D77401A0C0CCF5DEEE561F7F7E68CBE72E48E570B047C772CBACC33753080E32EB0B348C0B62337739B1BC73192392592C84E37B7AC141CFE65EE76D83C9083; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h1C5CF062CA6F13854A59BDEEEA07E3C6559EBB3618111895CBBACCBCD512B5F07D361CCE72B925658DBE1F7C4707E195C5C665B8118C3C31B196C261DA85A5E11889D25CB816ACC6627802052C61A4099B7B0EC923971DB3B9F9204BDBCCFA457EE296E8986E64C6DC99E59436641567648CB84DEB7D7937F974F038D838274F3D3CF1BE8C84DDB000565880A776E5C0E13166E49F47119A4CA1311CF97B965E7CBBCB2CB384BD0D92ED105D0617856E80441124B31DE58B8C001607FEE668899693E3EFF8FBF1FCEEFBCF7CF9BA6C37640DDF7FFE6187B19ACF089D4C038F6607B78D38001FE67E56CCE399DE36D7DDBD699D5CFC5B6D7A1421CE06FE40DB6E; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h0776C62C316FF94B0BC3A0288DE6A62B14D6C1A2DADF9BDF85B2CCB02CE1DB2D96632C3232C3974CDC1172E1779D8C6738251819975DB8146067301E0C0277B6B657485DCD62AC0662C8C005DDE7494C9CA13AAE3234BB0EE1B708A23A2F48AC4C3838641E940620F9CDDCCA14BCC07104C112BCC9032C48E925594CB886A604C9F7627EB100872A52FB5141D65111E6C8DA0ADB6CEC6004461D0E366B20DCCDB607E624499300E4DF6D95CB62F62FB75403E400EFBC3BD34080FC9CDCFCFCFFFFFFFFFFFFFFFFFFFFF7BFFFFFFFFFFFFFFFFFFFFFFFFFFFCF9FFFFFEFFFF81FFDDFFFFFFFFFFFFFF7FFBFFFBFDC0A6DBE6F8BE5BB7FE7A39B3DA3F3BE13B679; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N6 -cycloneive_lcell_comb \D[6]~88 ( -// Equation(s): -// \D[6]~88_combout = (\z80_|address_pins_|abus[15]~22_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout $ (((\D[6]~87_combout ))))) # (!\z80_|address_pins_|abus[15]~22_combout & -// (((\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout & !\D[6]~87_combout )))) - - .dataa(\z80_|address_pins_|abus[15]~22_combout ), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ), - .datad(\D[6]~87_combout ), - .cin(gnd), - .combout(\D[6]~88_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~88 .lut_mask = 16'h22D8; -defparam \D[6]~88 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N20 -cycloneive_lcell_comb \D[6]~89 ( -// Equation(s): -// \D[6]~89_combout = (\D[6]~87_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout & !\D[6]~88_combout )))) # (!\D[6]~87_combout & -// (((!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & \D[6]~88_combout )))) - - .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ), - .datab(\D[6]~87_combout ), - .datac(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datad(\D[6]~88_combout ), - .cin(gnd), - .combout(\D[6]~89_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~89 .lut_mask = 16'hC3C8; -defparam \D[6]~89 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N14 -cycloneive_lcell_comb \D[6]~111 ( -// Equation(s): -// \D[6]~111_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [15] & (\D[6]~91_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\D[6]~89_combout ))))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & -// (\D[6]~91_combout )) - - .dataa(\D[6]~91_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [15]), - .datad(\D[6]~89_combout ), - .cin(gnd), - .combout(\D[6]~111_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~111 .lut_mask = 16'hAEA2; -defparam \D[6]~111 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: IOIBUF_X16_Y34_N8 -cycloneive_io_ibuf \raw_loader_in~input ( - .i(raw_loader_in), - .ibar(gnd), - .o(\raw_loader_in~input_o )); -// synopsys translate_off -defparam \raw_loader_in~input .bus_hold = "false"; -defparam \raw_loader_in~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N18 -cycloneive_lcell_comb \D[6]~86 ( -// Equation(s): -// \D[6]~86_combout = (\z80_|address_pins_|DFFE_apin_latch [0]) # ((\raw_loader_in~input_o ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [0]), - .datab(gnd), - .datac(\raw_loader_in~input_o ), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\D[6]~86_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~86 .lut_mask = 16'hFAFF; -defparam \D[6]~86 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N28 -cycloneive_lcell_comb \D[6]~100 ( -// Equation(s): -// \D[6]~100_combout = ((\Equal2~0_combout & ((\D[6]~86_combout ))) # (!\Equal2~0_combout & (\D[6]~111_combout ))) # (!\Equal2~1_combout ) - - .dataa(\Equal2~1_combout ), - .datab(\Equal2~0_combout ), - .datac(\D[6]~111_combout ), - .datad(\D[6]~86_combout ), - .cin(gnd), - .combout(\D[6]~100_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~100 .lut_mask = 16'hFD75; -defparam \D[6]~100 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N4 -cycloneive_lcell_comb \D[6]~101 ( -// Equation(s): -// \D[6]~101_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\z80_|data_pins_|dout [6] & \D[6]~100_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\D[6]~100_combout )) # (!\Equal2~1_combout ))) - - .dataa(\Equal2~1_combout ), - .datab(\z80_|data_pins_|dout [6]), - .datac(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datad(\D[6]~100_combout ), - .cin(gnd), - .combout(\D[6]~101_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~101 .lut_mask = 16'hCF05; -defparam \D[6]~101 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N12 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [6] = (\z80_|pin_control_|bus_db_pin_re~combout & ((\D[6]~101_combout ) # ((\z80_|execute_|ctl_bus_db_we~7_combout & \z80_|bus_control_|db[6]~9_combout )))) # (!\z80_|pin_control_|bus_db_pin_re~combout & -// (((\z80_|execute_|ctl_bus_db_we~7_combout & \z80_|bus_control_|db[6]~9_combout )))) - - .dataa(\z80_|pin_control_|bus_db_pin_re~combout ), - .datab(\D[6]~101_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|bus_control_|db[6]~9_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [6]), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] .lut_mask = 16'hF888; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N10 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_re~2 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_re~2_combout = (\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & ((\z80_|execute_|fIORead~3_combout )))) # (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # -// ((\z80_|sequencer_|DFFE_T3_ff~q & \z80_|execute_|fIORead~3_combout )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|execute_|fIORead~3_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_re~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_re~2 .lut_mask = 16'hDC50; -defparam \z80_|pin_control_|bus_db_pin_re~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N16 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_2 ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_2~combout = (\z80_|execute_|ctl_bus_db_we~7_combout ) # ((\z80_|pin_control_|bus_db_pin_re~2_combout ) # ((\z80_|execute_|fMRead~35_combout & \z80_|sequencer_|DFFE_T2_ff~q ))) - - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(\z80_|execute_|fMRead~35_combout ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|pin_control_|bus_db_pin_re~2_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_2 .lut_mask = 16'hFFEA; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y13_N13 -dffeas \z80_|data_pins_|dout[6] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [6]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|data_pins_|dout [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|data_pins_|dout[6] .is_wysiwyg = "true"; -defparam \z80_|data_pins_|dout[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N16 -cycloneive_lcell_comb \z80_|bus_control_|db[6]~9 ( -// Equation(s): -// \z80_|bus_control_|db[6]~9_combout = ((\z80_|bus_control_|db[6]~8_combout & ((\z80_|data_pins_|dout [6]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - - .dataa(\z80_|bus_control_|db[6]~8_combout ), - .datab(\z80_|data_pins_|dout [6]), - .datac(\z80_|execute_|ctl_bus_db_oe~combout ), - .datad(\z80_|bus_control_|db[0]~6_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[6]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[6]~9 .lut_mask = 16'h8AFF; -defparam \z80_|bus_control_|db[6]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N8 -cycloneive_lcell_comb \z80_|ir_|opcode[6]~feeder ( -// Equation(s): -// \z80_|ir_|opcode[6]~feeder_combout = \z80_|bus_control_|db[6]~9_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|bus_control_|db[6]~9_combout ), - .cin(gnd), - .combout(\z80_|ir_|opcode[6]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|ir_|opcode[6]~feeder .lut_mask = 16'hFF00; -defparam \z80_|ir_|opcode[6]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~13 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~13_combout = ((\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_ir_we~5_combout ) # (\z80_|pla_decode_|Equal41~2_combout )))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) - - .dataa(\z80_|execute_|ctl_ir_we~5_combout ), - .datab(\z80_|pla_decode_|Equal41~2_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~13 .lut_mask = 16'hE0FF; -defparam \z80_|execute_|ctl_ir_we~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y12_N9 -dffeas \z80_|ir_|opcode[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|ir_|opcode[6]~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|ir_|opcode [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|ir_|opcode[6] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal41~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal41~0_combout = (\z80_|ir_|opcode [7] & \z80_|ir_|opcode [6]) - - .dataa(gnd), - .datab(gnd), + .dataa(\z80_|decode_state_|DFFE_instCB~q ), + .datab(\z80_|decode_state_|DFFE_instED~q ), .datac(\z80_|ir_|opcode [7]), .datad(\z80_|ir_|opcode [6]), .cin(gnd), - .combout(\z80_|pla_decode_|Equal41~0_combout ), + .combout(\z80_|pla_decode_|Equal44~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal41~0 .lut_mask = 16'hF000; -defparam \z80_|pla_decode_|Equal41~0 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal44~0 .lut_mask = 16'h0010; +defparam \z80_|pla_decode_|Equal44~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y16_N22 -cycloneive_lcell_comb \z80_|pla_decode_|Equal41~1 ( +// Location: LCCOMB_X25_Y16_N20 +cycloneive_lcell_comb \z80_|execute_|ixy_d~16 ( // Equation(s): -// \z80_|pla_decode_|Equal41~1_combout = (!\z80_|ir_|opcode [2] & (\z80_|ir_|opcode [1] & (\z80_|ir_|opcode [0] & !\z80_|ir_|opcode [5]))) +// \z80_|execute_|ixy_d~16_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal44~0_combout & ((\z80_|decode_state_|DFFE_instIY1~q ) # (\z80_|decode_state_|DFFE_inst4~q )))) - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|ir_|opcode [1]), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|ir_|opcode [5]), + .dataa(\z80_|decode_state_|DFFE_instIY1~q ), + .datab(\z80_|decode_state_|DFFE_inst4~q ), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|pla_decode_|Equal44~0_combout ), .cin(gnd), - .combout(\z80_|pla_decode_|Equal41~1_combout ), + .combout(\z80_|execute_|ixy_d~16_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal41~1 .lut_mask = 16'h0040; -defparam \z80_|pla_decode_|Equal41~1 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ixy_d~16 .lut_mask = 16'hE000; +defparam \z80_|execute_|ixy_d~16 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y16_N24 -cycloneive_lcell_comb \z80_|pla_decode_|Equal41~2 ( +// Location: LCCOMB_X23_Y13_N24 +cycloneive_lcell_comb \z80_|pla_decode_|Equal3~1 ( // Equation(s): -// \z80_|pla_decode_|Equal41~2_combout = (\z80_|pla_decode_|Equal41~0_combout & (\z80_|pla_decode_|Equal32~0_combout & (\z80_|pla_decode_|Equal41~1_combout & \z80_|decode_state_|use_ixiy~combout ))) - - .dataa(\z80_|pla_decode_|Equal41~0_combout ), - .datab(\z80_|pla_decode_|Equal32~0_combout ), - .datac(\z80_|pla_decode_|Equal41~1_combout ), - .datad(\z80_|decode_state_|use_ixiy~combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal41~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal41~2 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal41~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~combout = (\z80_|execute_|ctl_alu_bs_oe~11_combout ) # ((\z80_|sequencer_|DFFE_M4_ff~q & (\z80_|pla_decode_|Equal41~2_combout & !\z80_|sequencer_|DFFE_T1_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|pla_decode_|Equal41~2_combout ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|execute_|ctl_alu_bs_oe~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe .lut_mask = 16'hFF08; -defparam \z80_|execute_|ctl_alu_bs_oe .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N2 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~15 ( -// Equation(s): -// \z80_|alu_|db_high[1]~15_combout = ((!\z80_|bus_control_|db[4]~19_combout & (\z80_|bus_control_|db[5]~15_combout & \z80_|bus_control_|db[3]~21_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datab(\z80_|bus_control_|db[4]~19_combout ), - .datac(\z80_|bus_control_|db[5]~15_combout ), - .datad(\z80_|bus_control_|db[3]~21_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~15 .lut_mask = 16'h7555; -defparam \z80_|alu_|db_high[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N10 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~16 ( -// Equation(s): -// \z80_|alu_|db_high[1]~16_combout = (\z80_|alu_|op1_high [1] & (((\z80_|alu_|op2_high [1]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|alu_|op1_high [1] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_high [1]) # -// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) - - .dataa(\z80_|alu_|op1_high [1]), - .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datac(\z80_|alu_|op2_high [1]), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~16 .lut_mask = 16'hB0BB; -defparam \z80_|alu_|db_high[1]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N20 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~17 ( -// Equation(s): -// \z80_|alu_|db_high[1]~17_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[6]~23_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[4]~17_combout ))) - - .dataa(\z80_|alu_|db[6]~23_combout ), - .datab(gnd), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|alu_|db[4]~17_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~17 .lut_mask = 16'hAFA0; -defparam \z80_|alu_|db_high[1]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N26 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~18 ( -// Equation(s): -// \z80_|alu_|db_high[1]~18_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_high[1]~17_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[5]~25_combout ))) +// \z80_|pla_decode_|Equal3~1_combout = (\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [1]) .dataa(gnd), - .datab(\z80_|alu_|db_high[1]~17_combout ), - .datac(\z80_|alu_|db[5]~25_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~18 .lut_mask = 16'hCCF0; -defparam \z80_|alu_|db_high[1]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N12 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~19 ( -// Equation(s): -// \z80_|alu_|db_high[1]~19_combout = (\z80_|alu_|db_high[1]~15_combout & (\z80_|alu_|db_high[1]~16_combout & ((\z80_|alu_|db_high[1]~18_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) - - .dataa(\z80_|alu_|db_high[1]~15_combout ), - .datab(\z80_|alu_|db_high[1]~16_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datad(\z80_|alu_|db_high[1]~18_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~19 .lut_mask = 16'h8808; -defparam \z80_|alu_|db_high[1]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N26 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~20 ( -// Equation(s): -// \z80_|alu_|db_high[1]~20_combout = ((\z80_|alu_|db_high[1]~19_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout )))) # (!\z80_|alu_|db_high[3]~3_combout ) - - .dataa(\z80_|alu_|db_high[1]~19_combout ), - .datab(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), - .datad(\z80_|alu_|db_high[3]~3_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~20 .lut_mask = 16'hA8FF; -defparam \z80_|alu_|db_high[1]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N14 -cycloneive_lcell_comb \z80_|alu_|db[5]~24 ( -// Equation(s): -// \z80_|alu_|db[5]~24_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[5]~57_combout & ((\z80_|alu_control_|db[5]~15_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & -// ((\z80_|alu_control_|db[5]~15_combout ) # ((!\z80_|execute_|ctl_sw_2d~13_combout )))) - - .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datab(\z80_|alu_control_|db[5]~15_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .datad(\z80_|execute_|ctl_sw_2d~13_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[5]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[5]~24 .lut_mask = 16'hC4F5; -defparam \z80_|alu_|db[5]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N28 -cycloneive_lcell_comb \z80_|alu_|db[5]~25 ( -// Equation(s): -// \z80_|alu_|db[5]~25_combout = ((\z80_|alu_|db[5]~24_combout & ((\z80_|alu_|db_high[1]~20_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~26_combout ) - - .dataa(\z80_|alu_|db_high[1]~20_combout ), - .datab(\z80_|alu_|db[7]~26_combout ), - .datac(\z80_|alu_|db[5]~24_combout ), - .datad(\z80_|execute_|ctl_alu_oe~14_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[5]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[5]~25 .lut_mask = 16'hB3F3; -defparam \z80_|alu_|db[5]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N14 -cycloneive_lcell_comb \z80_|sw1_|db_down[5]~0 ( -// Equation(s): -// \z80_|sw1_|db_down[5]~0_combout = (\z80_|bus_control_|db[5]~15_combout ) # ((\z80_|execute_|ctl_sw_1d~6_combout & ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|execute_|ctl_66_oe~2_combout )))) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|bus_control_|db[5]~15_combout ), - .datac(\z80_|execute_|ctl_66_oe~2_combout ), - .datad(\z80_|execute_|ctl_sw_1d~6_combout ), - .cin(gnd), - .combout(\z80_|sw1_|db_down[5]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sw1_|db_down[5]~0 .lut_mask = 16'hEFCC; -defparam \z80_|sw1_|db_down[5]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N22 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_36 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout = (\z80_|alu_control_|db[5]~15_combout & ((\z80_|execute_|ctl_flags_bus~combout ) # ((\z80_|alu_|db_high[1]~20_combout & \z80_|execute_|ctl_flags_alu~15_combout )))) # (!\z80_|alu_control_|db[5]~15_combout -// & (\z80_|alu_|db_high[1]~20_combout & ((\z80_|execute_|ctl_flags_alu~15_combout )))) - - .dataa(\z80_|alu_control_|db[5]~15_combout ), - .datab(\z80_|alu_|db_high[1]~20_combout ), - .datac(\z80_|execute_|ctl_flags_bus~combout ), - .datad(\z80_|execute_|ctl_flags_alu~15_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_36 .lut_mask = 16'hECA0; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y11_N23 -dffeas \z80_|alu_flags_|flags_yf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_flags_xy_we~15_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|flags_yf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_yf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|flags_yf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N2 -cycloneive_lcell_comb \z80_|alu_control_|db[5]~13 ( -// Equation(s): -// \z80_|alu_control_|db[5]~13_combout = (\z80_|alu_flags_|flags_yf~q & ((\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ) # ((\z80_|alu_control_|out[6]~2_combout )))) # (!\z80_|alu_flags_|flags_yf~q & (!\z80_|execute_|ctl_flags_oe~2_combout & -// ((\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ) # (\z80_|alu_control_|out[6]~2_combout )))) - - .dataa(\z80_|alu_flags_|flags_yf~q ), - .datab(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .datac(\z80_|execute_|ctl_flags_oe~2_combout ), - .datad(\z80_|alu_control_|out[6]~2_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[5]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[5]~13 .lut_mask = 16'hAF8C; -defparam \z80_|alu_control_|db[5]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N0 -cycloneive_lcell_comb \z80_|alu_control_|db[5]~14 ( -// Equation(s): -// \z80_|alu_control_|db[5]~14_combout = (\z80_|sw1_|db_down[5]~0_combout & (\z80_|alu_control_|db[5]~13_combout & ((\z80_|reg_file_|gdfx_temp0[5]~72_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) - - .dataa(\z80_|sw1_|db_down[5]~0_combout ), - .datab(\z80_|alu_control_|db[5]~13_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .datad(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[5]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[5]~14 .lut_mask = 16'h8088; -defparam \z80_|alu_control_|db[5]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N10 -cycloneive_lcell_comb \z80_|alu_control_|db[5]~15 ( -// Equation(s): -// \z80_|alu_control_|db[5]~15_combout = ((\z80_|alu_control_|db[5]~14_combout & ((\z80_|alu_|db[5]~25_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|alu_control_|db[6]~11_combout ), - .datab(\z80_|alu_|db[5]~25_combout ), - .datac(\z80_|execute_|ctl_sw_2u~7_combout ), - .datad(\z80_|alu_control_|db[5]~14_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[5]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[5]~15 .lut_mask = 16'hDF55; -defparam \z80_|alu_control_|db[5]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N10 -cycloneive_lcell_comb \D[0]~107 ( -// Equation(s): -// \D[0]~107_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout ) # ((!\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \z80_|memory_ifc_|nRD_out~2_combout ))) - - .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|memory_ifc_|nRD_out~2_combout ), - .datad(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .cin(gnd), - .combout(\D[0]~107_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~107 .lut_mask = 16'hFF40; -defparam \D[0]~107 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y6_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a21 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[5]~99_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_first_bit_number = 5; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y9_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a5 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[5]~99_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_bit_number = 5; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024; -// synopsys translate_on - -// Location: M9K_X22_Y7_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a13 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[5]~99_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_bit_number = 5; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N8 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4 .lut_mask = 16'hDC98; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y23_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a29 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[5]~99_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_first_bit_number = 5; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N6 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4_combout & -// ((\ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout )))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4_combout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4_combout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5 .lut_mask = 16'hF838; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y26_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a13 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(gnd), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[5]~99_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_bit_number = 5; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_first_bit_number = 5; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y29_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a13 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_bit_number = 5; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init3 = 2048'h990442000864A0284030400454782424440404007E404808A4005448387E547C8004420800620824402040024A1242124204044008404208420A4A42424A1242020028008000524A024A4A284252446240001000101042000054265C7E0600007FAF5CA001C181BE0C02418447B1D88BAA85409896BC7C0E5FAC2529CB69A4038E2564731F88FE730045956C357C5ECF7EF8591DF2A8ACFFBFEEF268CD9B51238594AF691A9B8640983B7F76AAB97209EA6257389992FFE684926E0B19FA338B8489D73811171D5C9FF3DCFFFFFF8002000780101F3F4035A0CDED99F79A4775854F179F7D7DBBCF81B2F6421FF684CA6AF85894D29B9D3ACCBA3F27D9DC9911; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init2 = 2048'h5B438D714D4E3DD115E8BD1286EAB5FA1D71BD8F4508BD4BDC8838F9D27B552259BCEFFBB68A6FF529B3B0D92970010BBB6C7D872421210E190E1CCC47A485EAD2F8735647315839EF6F683C64773FC73464D5FE354936D50823A5DAEBEBDBCC6CAFF2622B8D518F63C6030424188FD357718970D25A30CD0731E532DB23002D02C12B12378356DE2C52041CA7A320C51E0D7CA9F5D575775D57FD75DDFDF75FFFDFFFD75F145247F03A0AE7F1E1EB2D5A99D2444108C6A5979B7CC26ABCC241EA4C912568003BB493CE04FF086C188980052BF6ABAAA2FD5D658000011277EB924C10EFAF3CB9B62486512344C61ADE6F15AB67F335A52513FF05AFAEEE8400; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 2048'h0C840083AD485153ACD3C035591630199B8C096CE4DC557D6D55FCCD738573D6E0948817C496E9DE8EA1F88F627B7460106691CC452DB9799E59A5D003733C4EA1BCE33AD2D8BE40A4E5BB7D7BBEC2CEADBBC8B6F87A4A56FBE0B891DE57E4C64EF9AD87727C49CFE7C5DE942B72AC7F6D97DE18920777FDDEE9EB11122A4E18F5569FDE08906765428FB9E6F89FBF0DEAA6064637BCA63FD02E273E5557F0548662C97BC2E8D3FFDB26D23E87BFD97E635A6560CFD93F8EED26E30C70DE8633D6B97C86DF7D9BEDFB99E36B6658F16C6DEFBDD5DF728D6209C852C37FE67CFF32EE4CCCECC64F7E6225FC99EC64C3B6DD7DED0FD7CCEA3BF09A006ECDD1009E; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'hA9C9CE3AECF7BE27C000000A8ABA95251B309A60B9DDC19EC3E391458CBB53CA00A85E3C5AAE2C49DDC2F6C7B013DACB319A769818A1081A7389F711D76A09BCBED23D9A99FF9B77183697955D76BF0E0008822742DA45B883C9193DAF09424501859565800698515E10A8189EE9B323E35CE7388D73C6E7A50D0DE6739C73AC538D134115D860ADA57B5B868E54393B1E31E762062577697D57E8464340420E9434CCA34CC9A1CB1FAACC56168071EAC113F5265D5F6A45A098D604A820508C4EA47F9A7E46083716911B0D585CE937B530218E8D2AD3777EE7D3B4BC56C29ADB46809D15D185F8809229B150C29C8081174CA6173B99703DA466629005C604; -// synopsys translate_on - -// Location: M9K_X33_Y2_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a5 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_bit_number = 5; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init3 = 2048'hE10F8B8C100323720BEBBDEBB81DF13FF97B252E2CB4F27BA091FBD0002D1A611E1EDBBC716D44D2912B80041C44558060CFCF15955C0D780DD5E71393920844F25E16C87C5D0308EEC52C011514BBC13AFA1028924D0C7CE738105BD47A10AA5B5C1D9D4193E4339F492B0E1A64E13AE35BE6B67AC8057BDACC155F14E906A017A1841358335450D4B26CD2A21B3D8F2211080B81EC040D7FA0B51CD48008112508062020A02490900092D2040259108806A328F4006D2AA514B42FB006ECCCCB9A360865678449975A8AE72B5C0F7BA800C1B5DC55D7D6FE2EF4EED85D00AB111821321BA426A4FE4956B43595832C271E83E060341AE5F2023FC808177383; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init2 = 2048'h1A2955372D510AC266A5445146E27000020C320FAE1557E37154040A13202DC6F40B840FB9A59B6DBB296562CB6220EFBE99D2776A202044D9101006FD221D305519198C859000004012AFF4FB060307C92BB732203BFDFEFFFFFFDFFF87FCFFFBFFEFF03FFE0FFFBFAFE0FF80787FFF7FFF83F7F87003FFBFFFFBFFFBFF0FFC0FF81FFF7FFBFFDFFFBFFFE1FF0086F3141AAB6005810A0621595A893F9D85983B9254954341968BAC8C141C90938C05B2C9CD267E11650407375FEDD6A2FEB346AAF6CFDC0791AA97B741995A3B3981E06D1A44D3711955197BB9910FCA20744915C84D6C24BAF53929814CA8A4697E8F4201145AE7415DC122A5F010436107; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048'h02E84F969E3C800AC610D276182020227809001A50DDDBA3487BB6AE802BA06509312DA0E620656EAF24D57C08FFB14D289613DC32083803B84DC6415FD5EDC000300A8D128FA20030ACCBAFA237B7024504D36A4BA26081137F059E78991154FE2AC2A884A8CC7FBBB21C851CC92B12E15593C0C020FFEE066558590E882D5B67459F1A8C3240FE4E6A8D028C0C088FCF471D400A19B38211004DD122212288B111114514CB11840E04828849C621392041163C00808C67223422F00110201DD18FCFFFF3FFE7F9FFFFFFF82C0B422D214711E08904524A069491774E663F48F665955B4E2C63DAC0078652D10120900298F7EE380092442AFD400BEC43C003; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'hB5D49EA9D7036A45AA9E870B8E8016720C7C3102AE925262492C84584942D209042216E0216C85B8912250B7157D5955AD406CB685BBF071B47D5193363C1CECAFE59E91BF11498940A0944996D47EE8D7E3A4EAE611AE19A965D01BA86B55E9C52A6A379A382C6C265FB0DA01396D0800C0046405C06F466DD18C4DD7655CD4E7622EC485808C841D64B737041FF68813B149A41531A0A692FB14AE2E5B49D49CDCADCF90E7BD88125BCE706BF6D04AABFC1C001163DC6EFF7FD3230303030000000000000000000008400000000000000000000000000030600000100007E00220000000000000080040004023AD496997B8C0077B886EEF161CF2298A091B; -// synopsys translate_on - -// Location: M9K_X33_Y29_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a5 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[5]~99_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a5_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_bit_number = 5; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_first_bit_number = 5; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init3 = 2048'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF80000001C000000160F000FF70C0007F78C00000F05001007870010010000000000800000038000000F000000070000000300000006000000000000040000000F00000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000000001D108000BEDA9FA9698A000000000000000000000000FFFFFFFF408102048004188297E014DA9FA9E9CA00000000000000000000000000000000FFFFFFFC800400CA972208DA9FA9CD8E00000000000000000000000000000000FFFFFFFC8004046A97A289FA9FA9CDC20000000000000000000000007FFFFFFC8000000280040E2A97A2997A9DA9CFC20000000000000000000000007FFFFFFE8000000280042EB28002BE369DA9274200000000000000000000000040810206BFFFFFFE9FE430A29D82AC3E8009E34A000000000000000000000000000000023FFFFFFC9FE4B1829FA2800E8009436A; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048'h9FE8334E88F827C697F88D1600A80A44809E8FC2B86999C2B85B3A82B1D32A869FE8336A88F807CA97F88F96A0A80EC2838E8D42B9E98FC2B86B3B82B0D7B2D2800832E288F827CA97F88B82A0080EC683869542B939B8C2B1AB0F8290B730C2800826EA8878078297F88AD2A0280EC283E694C2B83A3BC2A3AB3E8291A316AA800826EE881807C69DE8ABD6A0280BC282209CD2BA2A3D42A2737F82918314E2800806E6981805C69D48AED6A1E80BCA82709FC2BB223DC2A07B7F8295DF11C2800886E6980805869848AAC6A1E42DC281789DC2BBAA3DC6A02B7582955F00928008A6EE98082D9618088AC8A0F40FC289E89DC2BBCA3DC2A18B7782154F02F0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'h174F0870801C870281E2C982A801460297E5AC0288F318023FFFFFFC0000000297DF094A8094870281D6C082AC01460293FDA89288D31902BFFFFFFE40810106879F8D228C8685028016C082AC014642B3FCA80288D10F02800000027FFFFFFE879F893284DEC9028000408AAC014C02937DA00288D10F02800000027FFFFFFC841FA902804E81068BC04292AC0145E29379B00288D11F02FFFFFFFC0000000084FE89328166C1028BE05282AE4144829179B20288511F02FFFFFFFC0000000084F283328516850A88204602874364829179B08280513E0240810104FFFFFFFF843A8302853685828800560287476C928039B00200413E0000000000FFFFFFFF; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N0 -cycloneive_lcell_comb \Mux2~0 ( -// Equation(s): -// \Mux2~0_combout = (\z80_|address_pins_|abus[14]~23_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout )))) # (!\z80_|address_pins_|abus[14]~23_combout & -// (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ))) - - .dataa(\z80_|address_pins_|abus[14]~23_combout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout ), - .cin(gnd), - .combout(\Mux2~0_combout ), - .cout()); -// synopsys translate_off -defparam \Mux2~0 .lut_mask = 16'hBA98; -defparam \Mux2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N2 -cycloneive_lcell_comb \Mux2~1 ( -// Equation(s): -// \Mux2~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Mux2~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout )) # (!\Mux2~0_combout & -// ((\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Mux2~0_combout )))) - - .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ), - .datad(\Mux2~0_combout ), - .cin(gnd), - .combout(\Mux2~1_combout ), - .cout()); -// synopsys translate_off -defparam \Mux2~1 .lut_mask = 16'hBBC0; -defparam \Mux2~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N20 -cycloneive_lcell_comb \D[5]~110 ( -// Equation(s): -// \D[5]~110_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [15] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\Mux2~1_combout ))))) # -// (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout )) - - .dataa(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [15]), - .datad(\Mux2~1_combout ), - .cin(gnd), - .combout(\D[5]~110_combout ), - .cout()); -// synopsys translate_off -defparam \D[5]~110 .lut_mask = 16'hAEA2; -defparam \D[5]~110 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N28 -cycloneive_lcell_comb \D[5]~85 ( -// Equation(s): -// \D[5]~85_combout = (\D[5]~84_combout & (\D[5]~110_combout & ((\z80_|data_pins_|dout [5]) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) # (!\D[5]~84_combout & (((\z80_|data_pins_|dout [5])) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout ))) - - .dataa(\D[5]~84_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datac(\z80_|data_pins_|dout [5]), - .datad(\D[5]~110_combout ), - .cin(gnd), - .combout(\D[5]~85_combout ), - .cout()); -// synopsys translate_off -defparam \D[5]~85 .lut_mask = 16'hF351; -defparam \D[5]~85 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N24 -cycloneive_lcell_comb \D[5]~99 ( -// Equation(s): -// \D[5]~99_combout = (\D[5]~85_combout ) # (!\D[0]~107_combout ) - - .dataa(\D[0]~107_combout ), .datab(gnd), - .datac(gnd), - .datad(\D[5]~85_combout ), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [1]), .cin(gnd), - .combout(\D[5]~99_combout ), + .combout(\z80_|pla_decode_|Equal3~1_combout ), .cout()); // synopsys translate_off -defparam \D[5]~99 .lut_mask = 16'hFF55; -defparam \D[5]~99 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal3~1 .lut_mask = 16'h00F0; +defparam \z80_|pla_decode_|Equal3~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y13_N14 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[5] ( +// Location: LCCOMB_X24_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|ixy_d~10 ( // Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [5] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[5]~15_combout ) # ((\D[5]~99_combout & \z80_|pin_control_|bus_db_pin_re~combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & -// (\D[5]~99_combout & (\z80_|pin_control_|bus_db_pin_re~combout ))) +// \z80_|execute_|ixy_d~10_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal6~0_combout ))) - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(\D[5]~99_combout ), - .datac(\z80_|pin_control_|bus_db_pin_re~combout ), - .datad(\z80_|bus_control_|db[5]~15_combout ), + .dataa(\z80_|pla_decode_|Equal33~1_combout ), + .datab(\z80_|pla_decode_|Equal3~1_combout ), + .datac(\z80_|decode_state_|use_ixiy~combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [5]), + .combout(\z80_|execute_|ixy_d~10_combout ), .cout()); // synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[5] .lut_mask = 16'hEAC0; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[5] .sum_lutc_input = "datac"; +defparam \z80_|execute_|ixy_d~10 .lut_mask = 16'h8000; +defparam \z80_|execute_|ixy_d~10 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y13_N15 -dffeas \z80_|data_pins_|dout[5] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [5]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|data_pins_|dout [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|data_pins_|dout[5] .is_wysiwyg = "true"; -defparam \z80_|data_pins_|dout[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N22 -cycloneive_lcell_comb \z80_|bus_control_|db[5]~14 ( +// Location: LCCOMB_X24_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|ixy_d~13 ( // Equation(s): -// \z80_|bus_control_|db[5]~14_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [5]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) +// \z80_|execute_|ixy_d~13_combout = (\z80_|execute_|ixy_d~16_combout ) # ((\z80_|execute_|ixy_d~10_combout ) # (\z80_|pla_decode_|Equal41~2_combout )) + + .dataa(\z80_|execute_|ixy_d~16_combout ), + .datab(\z80_|execute_|ixy_d~10_combout ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~13 .lut_mask = 16'hFEFE; +defparam \z80_|execute_|ixy_d~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|ixy_d~14 ( +// Equation(s): +// \z80_|execute_|ixy_d~14_combout = (\z80_|execute_|ixy_d~12_combout & (((\z80_|execute_|ixy_d~17_combout & !\z80_|execute_|ixy_d~13_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) # (!\z80_|execute_|ixy_d~12_combout & +// (((\z80_|execute_|ixy_d~17_combout & !\z80_|execute_|ixy_d~13_combout )))) + + .dataa(\z80_|execute_|ixy_d~12_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ixy_d~17_combout ), + .datad(\z80_|execute_|ixy_d~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~14 .lut_mask = 16'h22F2; +defparam \z80_|execute_|ixy_d~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N10 +cycloneive_lcell_comb \z80_|pla_decode_|Equal49~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal49~0_combout = (!\z80_|decode_state_|in_halt~q & (\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal77~0_combout )) .dataa(gnd), - .datab(\z80_|execute_|ctl_bus_db_oe~combout ), - .datac(\z80_|data_pins_|dout [5]), - .datad(\z80_|bus_control_|db[0]~4_combout ), + .datab(\z80_|decode_state_|in_halt~q ), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|pla_decode_|Equal77~0_combout ), .cin(gnd), - .combout(\z80_|bus_control_|db[5]~14_combout ), + .combout(\z80_|pla_decode_|Equal49~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[5]~14 .lut_mask = 16'hF300; -defparam \z80_|bus_control_|db[5]~14 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal49~0 .lut_mask = 16'h3000; +defparam \z80_|pla_decode_|Equal49~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y10_N22 -cycloneive_lcell_comb \z80_|bus_control_|db[5]~15 ( +// Location: LCCOMB_X24_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ixy_d~15 ( // Equation(s): -// \z80_|bus_control_|db[5]~15_combout = ((\z80_|bus_control_|db[5]~14_combout & ((\z80_|alu_control_|db[5]~15_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) +// \z80_|execute_|ixy_d~15_combout = ((\z80_|decode_state_|use_ixiy~combout & (\z80_|execute_|ixy_d~11_combout & \z80_|pla_decode_|Equal49~0_combout ))) # (!\z80_|execute_|ixy_d~14_combout ) - .dataa(\z80_|bus_control_|db[0]~6_combout ), - .datab(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datac(\z80_|alu_control_|db[5]~15_combout ), - .datad(\z80_|bus_control_|db[5]~14_combout ), + .dataa(\z80_|decode_state_|use_ixiy~combout ), + .datab(\z80_|execute_|ixy_d~11_combout ), + .datac(\z80_|execute_|ixy_d~14_combout ), + .datad(\z80_|pla_decode_|Equal49~0_combout ), .cin(gnd), - .combout(\z80_|bus_control_|db[5]~15_combout ), + .combout(\z80_|execute_|ixy_d~15_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[5]~15 .lut_mask = 16'hF755; -defparam \z80_|bus_control_|db[5]~15 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ixy_d~15 .lut_mask = 16'h8F0F; +defparam \z80_|execute_|ixy_d~15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X34_Y10_N13 -dffeas \z80_|ir_|opcode[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|bus_control_|db[5]~15_combout ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|ir_|opcode [5]), - .prn(vcc)); +// Location: LCCOMB_X28_Y18_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout = (\z80_|execute_|ixy_d~15_combout & \z80_|sequencer_|DFFE_T5_ff~q ) + + .dataa(gnd), + .datab(\z80_|execute_|ixy_d~15_combout ), + .datac(\z80_|sequencer_|DFFE_T5_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), + .cout()); // synopsys translate_off -defparam \z80_|ir_|opcode[5] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[5] .power_up = "low"; +defparam \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 .lut_mask = 16'hC0C0; +defparam \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y15_N20 +// Location: LCCOMB_X26_Y16_N28 cycloneive_lcell_comb \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 ( // Equation(s): // \z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (((!\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout )))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (!\z80_|ir_|opcode [5] & @@ -40796,17 +6454,17 @@ cycloneive_lcell_comb \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 ( .dataa(\z80_|ir_|opcode [5]), .datab(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), - .datac(\z80_|pla_decode_|Equal3~2_combout ), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|pla_decode_|Equal3~2_combout ), .cin(gnd), .combout(\z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'h3350; +defparam \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'h3530; defparam \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X37_Y15_N21 +// Location: FF_X26_Y16_N29 dffeas \z80_|decode_state_|DFFE_inst4 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout ), @@ -40825,525 +6483,32592 @@ defparam \z80_|decode_state_|DFFE_inst4 .is_wysiwyg = "true"; defparam \z80_|decode_state_|DFFE_inst4 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X40_Y18_N4 -cycloneive_lcell_comb \z80_|decode_state_|use_ixiy ( +// Location: LCCOMB_X25_Y16_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~5 ( // Equation(s): -// \z80_|decode_state_|use_ixiy~combout = (\z80_|decode_state_|DFFE_inst4~q ) # (\z80_|decode_state_|DFFE_instIY1~q ) +// \z80_|execute_|ctl_ir_we~5_combout = (\z80_|decode_state_|DFFE_instCB~q & (!\z80_|decode_state_|DFFE_inst4~q & !\z80_|decode_state_|DFFE_instIY1~q )) - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(gnd), - .datac(\z80_|decode_state_|DFFE_instIY1~q ), - .datad(gnd), + .dataa(\z80_|decode_state_|DFFE_instCB~q ), + .datab(\z80_|decode_state_|DFFE_inst4~q ), + .datac(gnd), + .datad(\z80_|decode_state_|DFFE_instIY1~q ), .cin(gnd), - .combout(\z80_|decode_state_|use_ixiy~combout ), + .combout(\z80_|execute_|ctl_ir_we~5_combout ), .cout()); // synopsys translate_off -defparam \z80_|decode_state_|use_ixiy .lut_mask = 16'hFAFA; -defparam \z80_|decode_state_|use_ixiy .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_ir_we~5 .lut_mask = 16'h0022; +defparam \z80_|execute_|ctl_ir_we~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y17_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~23 ( +// Location: LCCOMB_X24_Y17_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~13 ( // Equation(s): -// \z80_|execute_|ctl_mRead~23_combout = (!\z80_|decode_state_|use_ixiy~combout & (!\z80_|decode_state_|in_halt~q & (\z80_|pla_decode_|Equal77~0_combout & \z80_|pla_decode_|Equal33~0_combout ))) +// \z80_|execute_|ctl_ir_we~13_combout = ((\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|pla_decode_|Equal41~2_combout ) # (\z80_|execute_|ctl_ir_we~5_combout )))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) - .dataa(\z80_|decode_state_|use_ixiy~combout ), - .datab(\z80_|decode_state_|in_halt~q ), - .datac(\z80_|pla_decode_|Equal77~0_combout ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~23 .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_mRead~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N16 -cycloneive_lcell_comb \z80_|execute_|fMRead~34 ( -// Equation(s): -// \z80_|execute_|fMRead~34_combout = (\z80_|execute_|ctl_mRead~23_combout ) # (((\z80_|execute_|ctl_ir_we~12_combout ) # (!\z80_|execute_|fMRead~5_combout )) # (!\z80_|execute_|fMWrite~3_combout )) - - .dataa(\z80_|execute_|ctl_mRead~23_combout ), - .datab(\z80_|execute_|fMWrite~3_combout ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|execute_|fMRead~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~34 .lut_mask = 16'hFBFF; -defparam \z80_|execute_|fMRead~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N14 -cycloneive_lcell_comb \z80_|execute_|fMRead~31 ( -// Equation(s): -// \z80_|execute_|fMRead~31_combout = (\z80_|execute_|ixy_d~6_combout & ((\z80_|pla_decode_|Equal33~3_combout ) # ((\z80_|pla_decode_|Equal6~1_combout )))) # (!\z80_|execute_|ixy_d~6_combout & (\z80_|execute_|ixy_d~5_combout & -// ((\z80_|pla_decode_|Equal33~3_combout ) # (\z80_|pla_decode_|Equal6~1_combout )))) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|pla_decode_|Equal33~3_combout ), - .datac(\z80_|pla_decode_|Equal6~1_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~31 .lut_mask = 16'hFCA8; -defparam \z80_|execute_|fMRead~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|fMRead~29 ( -// Equation(s): -// \z80_|execute_|fMRead~29_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|execute_|ctl_ir_we~5_combout & ((\z80_|ir_|opcode [6]) # (\z80_|ir_|opcode [7])))) - - .dataa(\z80_|ir_|opcode [6]), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|ir_|opcode [7]), + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|pla_decode_|Equal41~2_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), .datad(\z80_|execute_|ctl_ir_we~5_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~29_combout ), + .combout(\z80_|execute_|ctl_ir_we~13_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~29 .lut_mask = 16'hC800; -defparam \z80_|execute_|fMRead~29 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_ir_we~13 .lut_mask = 16'hF5D5; +defparam \z80_|execute_|ctl_ir_we~13 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y16_N14 -cycloneive_lcell_comb \z80_|execute_|fMRead~30 ( +// Location: FF_X30_Y17_N31 +dffeas \z80_|ir_|opcode[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|bus_control_|db[3]~21_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|ir_|opcode [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|ir_|opcode[3] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y16_N26 +cycloneive_lcell_comb \z80_|pla_decode_|Equal8~0 ( // Equation(s): -// \z80_|execute_|fMRead~30_combout = (\z80_|execute_|ctl_alu_shift_oe~14_combout & ((\z80_|execute_|ctl_ir_we~9_combout ) # ((\z80_|execute_|fMRead~29_combout ) # (\z80_|execute_|ctl_ir_we~10_combout )))) +// \z80_|pla_decode_|Equal8~0_combout = (!\z80_|ir_|opcode [2] & (\z80_|ir_|opcode [1] & \z80_|ir_|opcode [0])) + + .dataa(\z80_|ir_|opcode [2]), + .datab(gnd), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal8~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal8~0 .lut_mask = 16'h5000; +defparam \z80_|pla_decode_|Equal8~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~6 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~6_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal8~0_combout & \z80_|pla_decode_|Equal13~0_combout )) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|pla_decode_|Equal8~0_combout ), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~6 .lut_mask = 16'h3000; +defparam \z80_|execute_|ctl_mRead~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N10 +cycloneive_lcell_comb \z80_|pla_decode_|Equal9~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal9~0_combout = (!\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [3]) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [4]), + .datac(gnd), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal9~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal9~0 .lut_mask = 16'h0033; +defparam \z80_|pla_decode_|Equal9~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal9~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal9~1_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal1~7_combout & \z80_|pla_decode_|Equal9~0_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal2~0_combout ), + .datac(\z80_|pla_decode_|Equal1~7_combout ), + .datad(\z80_|pla_decode_|Equal9~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal9~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal9~1 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal9~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal9~1_combout & \z80_|sequencer_|M5~q )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|pla_decode_|Equal9~1_combout ), + .datad(\z80_|sequencer_|M5~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 .lut_mask = 16'h3000; +defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~28 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~28_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout & (((!\z80_|execute_|ctl_mRead~8_combout & !\z80_|execute_|ctl_mRead~6_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|execute_|ctl_mRead~8_combout ), + .datac(\z80_|execute_|ctl_mRead~6_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~28 .lut_mask = 16'h0057; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y16_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal13~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal13~1_combout = (\z80_|ir_|opcode [2] & (\z80_|ir_|opcode [1] & \z80_|ir_|opcode [0])) + + .dataa(\z80_|ir_|opcode [2]), + .datab(gnd), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal13~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal13~1 .lut_mask = 16'hA000; +defparam \z80_|pla_decode_|Equal13~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y17_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal69~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal69~0_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|ir_|opcode [4] & \z80_|pla_decode_|Equal13~1_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|pla_decode_|Equal13~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal69~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal69~0 .lut_mask = 16'h4000; +defparam \z80_|pla_decode_|Equal69~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout = (\z80_|pla_decode_|Equal1~4_combout & (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal13~0_combout & \z80_|ir_|opcode [0]))) + + .dataa(\z80_|pla_decode_|Equal1~4_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~27 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~27_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal6~0_combout & ((!\z80_|pla_decode_|Equal21~0_combout ) # (!\z80_|ir_|opcode [5])))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal3~1_combout ), + .datac(\z80_|pla_decode_|Equal21~0_combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~27 .lut_mask = 16'h4C00; +defparam \z80_|execute_|ctl_alu_op_low~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~2_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|pla_decode_|Equal69~0_combout ) # (\z80_|execute_|ctl_alu_op_low~27_combout )))) + + .dataa(\z80_|pla_decode_|Equal69~0_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~2 .lut_mask = 16'hFCF8; +defparam \z80_|execute_|ctl_reg_out_lo~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|rsel3 ( +// Equation(s): +// \z80_|execute_|rsel3~combout = \z80_|ir_|opcode [3] $ (((\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4]))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(gnd), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|rsel3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|rsel3 .lut_mask = 16'h5FA0; +defparam \z80_|execute_|rsel3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~12 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~12_combout = (\z80_|execute_|ctl_ir_we~5_combout & (!\z80_|ir_|opcode [7] & (\z80_|pla_decode_|Equal33~0_combout & \z80_|ir_|opcode [6]))) + + .dataa(\z80_|execute_|ctl_ir_we~5_combout ), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~12 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_ir_we~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|execute_|ctl_ir_we~12_combout & \z80_|sequencer_|DFFE_T3_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(gnd), + .datac(\z80_|execute_|ctl_ir_we~12_combout ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal56~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal56~0_combout = (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal1~4_combout & \z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|pla_decode_|Equal1~4_combout ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal56~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal56~0 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal56~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~24 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~24_combout = (\z80_|pla_decode_|Equal2~0_combout & (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|ir_|opcode [3]))) + + .dataa(\z80_|pla_decode_|Equal2~0_combout ), + .datab(\z80_|ir_|opcode [0]), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~24 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_alu_op_low~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~25 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~25_combout = (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|ir_|opcode [3]))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal2~0_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~25 .lut_mask = 16'h0040; +defparam \z80_|execute_|ctl_alu_op_low~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N16 +cycloneive_lcell_comb \z80_|execute_|nextM~2 ( +// Equation(s): +// \z80_|execute_|nextM~2_combout = (!\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_alu_op_low~24_combout & !\z80_|execute_|ctl_alu_op_low~25_combout )) + + .dataa(\z80_|pla_decode_|Equal56~0_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op_low~24_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~2 .lut_mask = 16'h0005; +defparam \z80_|execute_|nextM~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~16 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~16_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # ((\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T3_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|execute_|nextM~2_combout ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~16 .lut_mask = 16'h3320; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~3_combout = (\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ) # ((\z80_|execute_|ctl_reg_out_lo~2_combout & \z80_|execute_|rsel3~combout ))) + + .dataa(\z80_|execute_|ctl_reg_out_lo~2_combout ), + .datab(\z80_|execute_|rsel3~combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~3 .lut_mask = 16'hFFF8; +defparam \z80_|execute_|ctl_reg_out_lo~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y13_N22 +cycloneive_lcell_comb \z80_|pla_decode_|Equal40~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal40~0_combout = (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [1])) + + .dataa(\z80_|ir_|opcode [0]), + .datab(gnd), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal40~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal40~0 .lut_mask = 16'h0005; +defparam \z80_|pla_decode_|Equal40~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y13_N18 +cycloneive_lcell_comb \z80_|pla_decode_|Equal40~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal40~1_combout = (\z80_|pla_decode_|Equal40~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|ir_|opcode [5])) + + .dataa(\z80_|pla_decode_|Equal40~0_combout ), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(gnd), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal40~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal40~1 .lut_mask = 16'h8800; +defparam \z80_|pla_decode_|Equal40~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|execute_|ixy_d~7_combout & \z80_|pla_decode_|Equal1~7_combout ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal3~1_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|pla_decode_|Equal1~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y17_N24 +cycloneive_lcell_comb \z80_|pla_decode_|Equal3~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal3~0_combout = (\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3]) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [4]), + .datac(gnd), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal3~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal3~0 .lut_mask = 16'hCC00; +defparam \z80_|pla_decode_|Equal3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y13_N20 +cycloneive_lcell_comb \z80_|pla_decode_|Equal39~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal39~0_combout = (\z80_|pla_decode_|Equal40~0_combout & (\z80_|pla_decode_|Equal6~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal3~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal40~0_combout ), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal3~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal39~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal39~0 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal39~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~4_combout = (\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ) # ((\z80_|execute_|ixy_d~9_combout & ((\z80_|pla_decode_|Equal40~1_combout ) # (\z80_|pla_decode_|Equal39~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal40~1_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ), + .datac(\z80_|pla_decode_|Equal39~0_combout ), + .datad(\z80_|execute_|ixy_d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~4 .lut_mask = 16'hFECC; +defparam \z80_|execute_|ctl_reg_out_lo~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y18_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~0_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|M5~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|M5~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~0 .lut_mask = 16'h0F00; +defparam \z80_|execute_|ctl_alu_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|comb~0 ( +// Equation(s): +// \z80_|execute_|comb~0_combout = (\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|execute_|comb~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|comb~0 .lut_mask = 16'hF000; +defparam \z80_|execute_|comb~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N28 +cycloneive_lcell_comb \z80_|pla_decode_|Equal41~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal41~0_combout = (\z80_|ir_|opcode [6] & \z80_|ir_|opcode [7]) + + .dataa(\z80_|ir_|opcode [6]), + .datab(gnd), + .datac(gnd), + .datad(\z80_|ir_|opcode [7]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal41~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal41~0 .lut_mask = 16'hAA00; +defparam \z80_|pla_decode_|Equal41~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N30 +cycloneive_lcell_comb \z80_|pla_decode_|Equal47~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal47~0_combout = (\z80_|ir_|opcode [0] & (!\z80_|decode_state_|table_xx~0_combout & (\z80_|execute_|comb~0_combout & \z80_|pla_decode_|Equal41~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|decode_state_|table_xx~0_combout ), + .datac(\z80_|execute_|comb~0_combout ), + .datad(\z80_|pla_decode_|Equal41~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal47~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal47~0 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal47~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y18_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~32 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~32_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|pla_decode_|Equal47~0_combout & ((!\z80_|execute_|ctl_alu_oe~0_combout ) # (!\z80_|pla_decode_|Equal34~0_combout )))) # (!\z80_|execute_|ixy_d~7_combout & +// (((!\z80_|execute_|ctl_alu_oe~0_combout )) # (!\z80_|pla_decode_|Equal34~0_combout ))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|pla_decode_|Equal34~0_combout ), + .datac(\z80_|execute_|ctl_alu_oe~0_combout ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~32 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_inc_cy~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N22 +cycloneive_lcell_comb \z80_|pla_decode_|Equal19~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal19~0_combout = (\z80_|pla_decode_|Equal1~7_combout & (\z80_|pla_decode_|Equal32~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal3~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal1~7_combout ), + .datab(\z80_|pla_decode_|Equal32~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal3~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal19~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal19~0 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal19~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~9_combout = (\z80_|execute_|ctl_inc_cy~32_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|sequencer_|M5~q )) # (!\z80_|pla_decode_|Equal19~0_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~32_combout ), + .datab(\z80_|pla_decode_|Equal19~0_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|M5~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~9 .lut_mask = 16'hA2AA; +defparam \z80_|execute_|ctl_reg_out_lo~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~5_combout = ((\z80_|execute_|ctl_reg_out_lo~3_combout ) # ((\z80_|execute_|ctl_reg_out_lo~4_combout ) # (!\z80_|execute_|ctl_reg_out_lo~9_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~3_combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~4_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~5 .lut_mask = 16'hFDFF; +defparam \z80_|execute_|ctl_reg_out_lo~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~4 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~4_combout = (\z80_|decode_state_|DFFE_instED~q & (\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [7] & !\z80_|ir_|opcode [6]))) + + .dataa(\z80_|decode_state_|DFFE_instED~q ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~4 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_mWrite~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout = (\z80_|pla_decode_|Equal2~0_combout & (\z80_|execute_|ctl_mWrite~4_combout & (!\z80_|ir_|opcode [0] & \z80_|execute_|ctl_alu_op_low~22_combout ))) + + .dataa(\z80_|pla_decode_|Equal2~0_combout ), + .datab(\z80_|execute_|ctl_mWrite~4_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|execute_|ctl_alu_op_low~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~34 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~34_combout = (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [2] & (\z80_|ir_|opcode [1] & \z80_|execute_|ctl_mWrite~4_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|execute_|ctl_mWrite~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~34 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_mRead~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|execute_|ixy_d~15_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|execute_|ixy_d~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y17_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~36 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~36_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout & (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|execute_|ctl_mRead~34_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~36 .lut_mask = 16'h0015; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~5 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~5_combout = (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T4_ff~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~5 .lut_mask = 16'hC0C0; +defparam \z80_|execute_|ctl_mWrite~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N6 +cycloneive_lcell_comb \z80_|execute_|nextM~11 ( +// Equation(s): +// \z80_|execute_|nextM~11_combout = ((!\z80_|execute_|ctl_alu_op_low~25_combout & (!\z80_|execute_|ctl_alu_op_low~24_combout & !\z80_|pla_decode_|Equal56~0_combout ))) # (!\z80_|execute_|ctl_mWrite~5_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~25_combout ), + .datab(\z80_|execute_|ctl_mWrite~5_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~24_combout ), + .datad(\z80_|pla_decode_|Equal56~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~11 .lut_mask = 16'h3337; +defparam \z80_|execute_|nextM~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N26 +cycloneive_lcell_comb \z80_|pla_decode_|Equal20~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal20~0_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|execute_|comb~0_combout & !\z80_|ir_|opcode [5]))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|execute_|comb~0_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal20~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal20~0 .lut_mask = 16'h0080; +defparam \z80_|pla_decode_|Equal20~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y17_N10 +cycloneive_lcell_comb \z80_|pla_decode_|Equal13~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal13~2_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [4] & \z80_|pla_decode_|Equal13~1_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|pla_decode_|Equal13~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal13~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal13~2 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal13~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~24 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~24_combout = (\z80_|pla_decode_|Equal13~2_combout & !\z80_|ir_|opcode [3]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~24 .lut_mask = 16'h00F0; +defparam \z80_|execute_|ctl_mRead~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~27 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~27_combout = (\z80_|pla_decode_|Equal20~0_combout & (!\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ctl_mRead~24_combout ) # (!\z80_|execute_|ixy_d~6_combout )))) # (!\z80_|pla_decode_|Equal20~0_combout & +// (((!\z80_|execute_|ctl_mRead~24_combout ) # (!\z80_|execute_|ixy_d~6_combout )))) + + .dataa(\z80_|pla_decode_|Equal20~0_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ctl_mRead~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~27 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y17_N20 +cycloneive_lcell_comb \z80_|pla_decode_|Equal48~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal48~0_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [4] & \z80_|pla_decode_|Equal13~1_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|pla_decode_|Equal13~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal48~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal48~0 .lut_mask = 16'h0400; +defparam \z80_|pla_decode_|Equal48~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y16_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal10~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal10~0_combout = (!\z80_|ir_|opcode [1] & (\z80_|execute_|ctl_mWrite~4_combout & (!\z80_|ir_|opcode [2] & \z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [1]), + .datab(\z80_|execute_|ctl_mWrite~4_combout ), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal10~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal10~0 .lut_mask = 16'h0400; +defparam \z80_|pla_decode_|Equal10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y16_N0 +cycloneive_lcell_comb \z80_|pla_decode_|Equal11~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal11~0_combout = (!\z80_|ir_|opcode [1] & (\z80_|execute_|ctl_mWrite~4_combout & (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [1]), + .datab(\z80_|execute_|ctl_mWrite~4_combout ), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal11~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal11~0 .lut_mask = 16'h0004; +defparam \z80_|pla_decode_|Equal11~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N24 +cycloneive_lcell_comb \z80_|pla_decode_|Equal63~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal63~0_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|execute_|comb~0_combout & \z80_|ir_|opcode [5]))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|execute_|comb~0_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal63~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal63~0 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal63~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf2_we ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf2_we~combout = (\z80_|pla_decode_|Equal63~0_combout & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (!\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [3]))) + + .dataa(\z80_|pla_decode_|Equal63~0_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf2_we~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf2_we .lut_mask = 16'h0008; +defparam \z80_|execute_|ctl_flags_hf2_we .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~41 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~41_combout = (!\z80_|execute_|ctl_flags_hf2_we~combout & (((!\z80_|pla_decode_|Equal10~0_combout & !\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|execute_|ctl_flags_hf2_we~combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~41 .lut_mask = 16'h010F; +defparam \z80_|execute_|ctl_alu_shift_oe~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y13_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal68~3 ( +// Equation(s): +// \z80_|pla_decode_|Equal68~3_combout = (\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [1] & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal68~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal68~3 .lut_mask = 16'h0020; +defparam \z80_|pla_decode_|Equal68~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~7_combout = (\z80_|execute_|ctl_alu_op_low~27_combout ) # ((\z80_|pla_decode_|Equal68~3_combout ) # ((\z80_|pla_decode_|Equal21~0_combout & \z80_|pla_decode_|Equal63~0_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~27_combout ), + .datab(\z80_|pla_decode_|Equal68~3_combout ), + .datac(\z80_|pla_decode_|Equal21~0_combout ), + .datad(\z80_|pla_decode_|Equal63~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~7 .lut_mask = 16'hFEEE; +defparam \z80_|execute_|ctl_flags_bus~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~8_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|execute_|ctl_alu_op_low~25_combout ) # ((\z80_|execute_|ctl_flags_bus~7_combout ) # (\z80_|pla_decode_|Equal20~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~25_combout ), + .datab(\z80_|execute_|ctl_flags_bus~7_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|pla_decode_|Equal20~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~8 .lut_mask = 16'hF0E0; +defparam \z80_|execute_|ctl_flags_bus~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N18 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~9 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~9_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|execute_|ctl_alu_op_low~24_combout & !\z80_|pla_decode_|Equal56~0_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) + + .dataa(\z80_|execute_|ctl_alu_op_low~24_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|pla_decode_|Equal56~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~9 .lut_mask = 16'hCFDF; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~6_combout = (!\z80_|ir_|opcode [6] & !\z80_|ir_|opcode [7]) + + .dataa(\z80_|ir_|opcode [6]), + .datab(gnd), + .datac(gnd), + .datad(\z80_|ir_|opcode [7]), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~6 .lut_mask = 16'h0055; +defparam \z80_|execute_|ctl_ir_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~8_combout = (\z80_|execute_|ctl_ir_we~5_combout & (\z80_|execute_|ctl_ir_we~6_combout & ((!\z80_|decode_state_|DFFE_instCB~q ) # (!\z80_|pla_decode_|Equal33~0_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~5_combout ), + .datab(\z80_|execute_|ctl_ir_we~6_combout ), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|decode_state_|DFFE_instCB~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~8 .lut_mask = 16'h0888; +defparam \z80_|execute_|ctl_ir_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~14 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~14_combout = (\z80_|execute_|ctl_ir_we~5_combout & (!\z80_|ir_|opcode [7] & (\z80_|pla_decode_|Equal33~0_combout & !\z80_|ir_|opcode [6]))) + + .dataa(\z80_|execute_|ctl_ir_we~5_combout ), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~14 .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_ir_we~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~4_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~8_combout & !\z80_|execute_|ctl_ir_we~14_combout ))) # (!\z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|execute_|ctl_ir_we~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~4 .lut_mask = 16'hF3F7; +defparam \z80_|execute_|ctl_flags_bus~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~5_combout = (\z80_|execute_|ixy_d~10_combout ) # ((\z80_|pla_decode_|Equal63~0_combout & ((\z80_|pla_decode_|Equal32~0_combout ) # (\z80_|pla_decode_|Equal3~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal32~0_combout ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|execute_|ixy_d~10_combout ), + .datad(\z80_|pla_decode_|Equal3~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~5 .lut_mask = 16'hFCF8; +defparam \z80_|execute_|ctl_flags_bus~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~4 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~4_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal3~1_combout & (!\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~1_combout ), + .datab(\z80_|pla_decode_|Equal3~1_combout ), + .datac(\z80_|decode_state_|use_ixiy~combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~4 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_mRead~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~6_combout = ((!\z80_|execute_|ctl_flags_bus~5_combout & (!\z80_|pla_decode_|Equal13~2_combout & !\z80_|execute_|ctl_mRead~4_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) + + .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), + .datab(\z80_|pla_decode_|Equal13~2_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|execute_|ctl_mRead~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~6 .lut_mask = 16'h0F1F; +defparam \z80_|execute_|ctl_flags_bus~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~9 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~9_combout = (!\z80_|execute_|ctl_flags_bus~8_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~9_combout & (\z80_|execute_|ctl_flags_bus~4_combout & \z80_|execute_|ctl_flags_bus~6_combout ))) + + .dataa(\z80_|execute_|ctl_flags_bus~8_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~9_combout ), + .datac(\z80_|execute_|ctl_flags_bus~4_combout ), + .datad(\z80_|execute_|ctl_flags_bus~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~9 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_flags_bus~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_iorw~11 ( +// Equation(s): +// \z80_|execute_|ctl_iorw~11_combout = (!\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_iorw~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_iorw~11 .lut_mask = 16'h0004; +defparam \z80_|execute_|ctl_iorw~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y16_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~17 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~17_combout = (\z80_|ir_|opcode [1] & (\z80_|execute_|ctl_mWrite~4_combout & (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [1]), + .datab(\z80_|execute_|ctl_mWrite~4_combout ), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~17 .lut_mask = 16'h0008; +defparam \z80_|execute_|ctl_mWrite~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y14_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~18 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~18_combout = ((!\z80_|execute_|ctl_iorw~11_combout & (!\z80_|execute_|ctl_mWrite~17_combout & !\z80_|execute_|ctl_mRead~34_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) + + .dataa(\z80_|execute_|ctl_iorw~11_combout ), + .datab(\z80_|execute_|ctl_mWrite~17_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~18 .lut_mask = 16'h01FF; +defparam \z80_|execute_|ctl_alu_shift_oe~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N14 +cycloneive_lcell_comb \z80_|pla_decode_|Equal37~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal37~0_combout = (!\z80_|ir_|opcode [0] & (!\z80_|decode_state_|table_xx~0_combout & (\z80_|pla_decode_|Equal1~4_combout & \z80_|pla_decode_|Equal41~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|decode_state_|table_xx~0_combout ), + .datac(\z80_|pla_decode_|Equal1~4_combout ), + .datad(\z80_|pla_decode_|Equal41~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal37~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal37~0 .lut_mask = 16'h1000; +defparam \z80_|pla_decode_|Equal37~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~19 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~19_combout = (\z80_|pla_decode_|Equal41~2_combout ) # ((\z80_|pla_decode_|Equal37~0_combout ) # ((\z80_|pla_decode_|Equal40~1_combout ) # (\z80_|pla_decode_|Equal34~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal41~2_combout ), + .datab(\z80_|pla_decode_|Equal37~0_combout ), + .datac(\z80_|pla_decode_|Equal40~1_combout ), + .datad(\z80_|pla_decode_|Equal34~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~19 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_alu_shift_oe~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N0 +cycloneive_lcell_comb \z80_|pla_decode_|Equal35~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal35~0_combout = (!\z80_|ir_|opcode [0] & (!\z80_|decode_state_|table_xx~0_combout & (\z80_|pla_decode_|Equal2~0_combout & \z80_|pla_decode_|Equal41~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|decode_state_|table_xx~0_combout ), + .datac(\z80_|pla_decode_|Equal2~0_combout ), + .datad(\z80_|pla_decode_|Equal41~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal35~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal35~0 .lut_mask = 16'h1000; +defparam \z80_|pla_decode_|Equal35~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y13_N0 +cycloneive_lcell_comb \z80_|pla_decode_|Equal21~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal21~1_combout = (\z80_|pla_decode_|Equal40~0_combout & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal21~0_combout & !\z80_|ir_|opcode [5]))) + + .dataa(\z80_|pla_decode_|Equal40~0_combout ), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|pla_decode_|Equal21~0_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal21~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal21~1 .lut_mask = 16'h0080; +defparam \z80_|pla_decode_|Equal21~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~17 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~17_combout = ((!\z80_|pla_decode_|Equal39~0_combout & (!\z80_|pla_decode_|Equal35~0_combout & !\z80_|pla_decode_|Equal21~1_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) + + .dataa(\z80_|pla_decode_|Equal39~0_combout ), + .datab(\z80_|pla_decode_|Equal35~0_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|pla_decode_|Equal21~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~17 .lut_mask = 16'h0F1F; +defparam \z80_|execute_|ctl_alu_shift_oe~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~20 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~20_combout = (\z80_|execute_|ctl_alu_shift_oe~18_combout & (\z80_|execute_|ctl_alu_shift_oe~17_combout & ((!\z80_|execute_|ctl_alu_shift_oe~19_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~19_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~20 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_alu_shift_oe~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~9 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~9_combout = (\z80_|pla_decode_|Equal41~0_combout & (\z80_|execute_|ctl_ir_we~5_combout & ((!\z80_|decode_state_|DFFE_instCB~q ) # (!\z80_|pla_decode_|Equal33~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|pla_decode_|Equal41~0_combout ), + .datac(\z80_|execute_|ctl_ir_we~5_combout ), + .datad(\z80_|decode_state_|DFFE_instCB~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~9 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_ir_we~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y20_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~11_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|execute_|ctl_ir_we~12_combout & !\z80_|execute_|ctl_ir_we~9_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) + + .dataa(\z80_|execute_|ctl_ir_we~12_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|execute_|ctl_ir_we~9_combout ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~11 .lut_mask = 16'hCDFF; +defparam \z80_|execute_|ctl_alu_bs_oe~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~15 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~15_combout = (\z80_|execute_|ctl_ir_we~5_combout & (\z80_|ir_|opcode [7] & (\z80_|pla_decode_|Equal33~0_combout & \z80_|ir_|opcode [6]))) + + .dataa(\z80_|execute_|ctl_ir_we~5_combout ), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~15 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_ir_we~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y20_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~7_combout = (\z80_|execute_|ctl_alu_bs_oe~11_combout & (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|execute_|ctl_ir_we~10_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~11_combout ), + .datad(\z80_|execute_|ctl_ir_we~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~7 .lut_mask = 16'h5070; +defparam \z80_|execute_|ctl_alu_bs_oe~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~7_combout = (\z80_|execute_|ctl_ir_we~5_combout & (\z80_|ir_|opcode [7] & (\z80_|pla_decode_|Equal33~0_combout & !\z80_|ir_|opcode [6]))) + + .dataa(\z80_|execute_|ctl_ir_we~5_combout ), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~7 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_ir_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N4 +cycloneive_lcell_comb \z80_|pla_decode_|Equal46~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal46~0_combout = (\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [0] & (\z80_|decode_state_|DFFE_instCB~q & \z80_|ir_|opcode [1]))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|ir_|opcode [0]), + .datac(\z80_|decode_state_|DFFE_instCB~q ), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal46~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal46~0 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal46~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~11 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~11_combout = (\z80_|ir_|opcode [6] & (!\z80_|ir_|opcode [7] & (\z80_|execute_|ctl_ir_we~5_combout & !\z80_|pla_decode_|Equal46~0_combout ))) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|execute_|ctl_ir_we~5_combout ), + .datad(\z80_|pla_decode_|Equal46~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~11 .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_ir_we~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~3 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~3_combout = (\z80_|execute_|ctl_alu_bs_oe~7_combout & (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~11_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~7_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_ir_we~7_combout ), + .datad(\z80_|execute_|ctl_ir_we~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~3 .lut_mask = 16'h222A; +defparam \z80_|execute_|ctl_bus_db_oe~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal52~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal52~1_combout = (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|decode_state_|DFFE_instED~q & (\z80_|pla_decode_|Equal41~0_combout & !\z80_|decode_state_|DFFE_instCB~q ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|decode_state_|DFFE_instED~q ), + .datac(\z80_|pla_decode_|Equal41~0_combout ), + .datad(\z80_|decode_state_|DFFE_instCB~q ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal52~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal52~1 .lut_mask = 16'h0020; +defparam \z80_|pla_decode_|Equal52~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~21 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~21_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal44~0_combout & !\z80_|pla_decode_|Equal52~1_combout ))) # (!\z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|pla_decode_|Equal44~0_combout ), + .datad(\z80_|pla_decode_|Equal52~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~21 .lut_mask = 16'hDDDF; +defparam \z80_|execute_|ctl_flags_xy_we~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~13 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~13_combout = (\z80_|execute_|ctl_flags_bus~9_combout & (\z80_|execute_|ctl_alu_shift_oe~20_combout & (\z80_|execute_|ctl_bus_db_oe~3_combout & \z80_|execute_|ctl_flags_xy_we~21_combout ))) + + .dataa(\z80_|execute_|ctl_flags_bus~9_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~20_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~3_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~13 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_flags_xy_we~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~6 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~6_combout = (!\z80_|decode_state_|DFFE_instIY1~q & (!\z80_|decode_state_|DFFE_inst4~q & (\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal44~0_combout ))) + + .dataa(\z80_|decode_state_|DFFE_instIY1~q ), + .datab(\z80_|decode_state_|DFFE_inst4~q ), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|pla_decode_|Equal44~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~6 .lut_mask = 16'h1000; +defparam \z80_|execute_|ctl_state_alu~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~14 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~14_combout = (\z80_|sequencer_|DFFE_M4_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~14 .lut_mask = 16'hA0A0; +defparam \z80_|execute_|ctl_alu_shift_oe~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~14 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~14_combout = (\z80_|execute_|ctl_alu_shift_oe~41_combout & (\z80_|execute_|ctl_flags_xy_we~13_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_state_alu~6_combout )))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~41_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~13_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~14 .lut_mask = 16'h0888; +defparam \z80_|execute_|ctl_flags_xy_we~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y19_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~24 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~24_combout = (\z80_|execute_|ctl_flags_xy_we~14_combout & (((!\z80_|pla_decode_|Equal48~0_combout & !\z80_|pla_decode_|Equal69~0_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|pla_decode_|Equal48~0_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|pla_decode_|Equal69~0_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~24 .lut_mask = 16'h3700; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y19_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~37 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~37_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout & (\z80_|execute_|nextM~11_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~27_combout & \z80_|execute_|ctl_reg_gp_sel[0]~24_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ), + .datab(\z80_|execute_|nextM~11_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~27_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~37 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel~7_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|decode_state_|table_xx~0_combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal41~0_combout ))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|decode_state_|table_xx~0_combout ), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|pla_decode_|Equal41~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel~7 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_reg_gp_sel~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|rsel0 ( +// Equation(s): +// \z80_|execute_|rsel0~combout = \z80_|ir_|opcode [0] $ (((\z80_|ir_|opcode [1] & \z80_|ir_|opcode [2]))) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|rsel0~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|rsel0 .lut_mask = 16'h3FC0; +defparam \z80_|execute_|rsel0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~3 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~3_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~3 .lut_mask = 16'h5050; +defparam \z80_|execute_|ctl_state_alu~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~0_combout = ((!\z80_|execute_|ctl_alu_op_low~24_combout & (!\z80_|execute_|ctl_alu_op_low~25_combout & !\z80_|pla_decode_|Equal56~0_combout ))) # (!\z80_|execute_|ctl_state_alu~3_combout ) + + .dataa(\z80_|execute_|ctl_state_alu~3_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~24_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~25_combout ), + .datad(\z80_|pla_decode_|Equal56~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~0 .lut_mask = 16'h5557; +defparam \z80_|execute_|ctl_reg_use_sp~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~2 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~2_combout = (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~2 .lut_mask = 16'hCC00; +defparam \z80_|execute_|ctl_state_alu~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout = (\z80_|execute_|ixy_d~15_combout & \z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|execute_|ixy_d~15_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 .lut_mask = 16'hAA00; +defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~30 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~30_combout = (\z80_|execute_|ctl_reg_use_sp~0_combout & (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout & ((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|ctl_mRead~34_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~34_combout ), + .datab(\z80_|execute_|ctl_reg_use_sp~0_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~30 .lut_mask = 16'h004C; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~12 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[0]~12_combout = ((!\z80_|pla_decode_|Equal39~0_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal40~1_combout ))) # (!\z80_|execute_|ixy_d~5_combout ) + + .dataa(\z80_|pla_decode_|Equal39~0_combout ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|pla_decode_|Equal40~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~12 .lut_mask = 16'h0F1F; +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~6_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~30_combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ), + .datab(\z80_|pla_decode_|Equal47~0_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~6 .lut_mask = 16'h20A0; +defparam \z80_|execute_|ctl_reg_out_lo~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~5 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~5_combout = (!\z80_|decode_state_|table_xx~0_combout & (!\z80_|pla_decode_|Equal33~0_combout & (\z80_|ir_|opcode [7] & !\z80_|ir_|opcode [6]))) + + .dataa(\z80_|decode_state_|table_xx~0_combout ), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~5 .lut_mask = 16'h0010; +defparam \z80_|execute_|ctl_state_alu~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~1 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~1_combout = ((!\z80_|execute_|ctl_ir_we~8_combout & (!\z80_|execute_|ctl_state_alu~5_combout & !\z80_|execute_|ctl_ir_we~11_combout ))) # (!\z80_|execute_|ctl_eval_cond~0_combout ) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_state_alu~5_combout ), + .datad(\z80_|execute_|ctl_ir_we~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~1 .lut_mask = 16'h3337; +defparam \z80_|execute_|ctl_sw_2u~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~1 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~1_combout = (\z80_|pla_decode_|Equal77~0_combout & ((\z80_|decode_state_|in_halt~q ) # ((!\z80_|pla_decode_|Equal33~0_combout & !\z80_|pla_decode_|Equal33~1_combout )))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|decode_state_|in_halt~q ), + .datac(\z80_|pla_decode_|Equal33~1_combout ), + .datad(\z80_|pla_decode_|Equal77~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~1 .lut_mask = 16'hCD00; +defparam \z80_|execute_|ctl_alu_oe~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~7 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~7_combout = (\z80_|pla_decode_|Equal77~0_combout & (\z80_|pla_decode_|Equal33~1_combout & (!\z80_|decode_state_|use_ixiy~combout & !\z80_|decode_state_|in_halt~q ))) + + .dataa(\z80_|pla_decode_|Equal77~0_combout ), + .datab(\z80_|pla_decode_|Equal33~1_combout ), + .datac(\z80_|decode_state_|use_ixiy~combout ), + .datad(\z80_|decode_state_|in_halt~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~7 .lut_mask = 16'h0008; +defparam \z80_|execute_|ctl_mWrite~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~4 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~4_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|execute_|ctl_alu_oe~1_combout & (!\z80_|execute_|ctl_mWrite~7_combout ))) # (!\z80_|execute_|ctl_eval_cond~0_combout & (((!\z80_|execute_|ctl_ir_we~4_combout ) # +// (!\z80_|execute_|ctl_mWrite~7_combout )))) + + .dataa(\z80_|execute_|ctl_alu_oe~1_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~7_combout ), + .datad(\z80_|execute_|ctl_ir_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~4 .lut_mask = 16'h0737; +defparam \z80_|execute_|ctl_sw_2u~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|setM1~57 ( +// Equation(s): +// \z80_|execute_|setM1~57_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~10_combout ))) # (!\z80_|sequencer_|DFFE_T4_ff~q ) .dataa(\z80_|execute_|ctl_ir_we~9_combout ), - .datab(\z80_|execute_|fMRead~29_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datad(\z80_|execute_|ctl_ir_we~10_combout ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|execute_|ctl_ir_we~10_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), .cin(gnd), - .combout(\z80_|execute_|fMRead~30_combout ), + .combout(\z80_|execute_|setM1~57_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~30 .lut_mask = 16'hF0E0; -defparam \z80_|execute_|fMRead~30 .sum_lutc_input = "datac"; +defparam \z80_|execute_|setM1~57 .lut_mask = 16'hFF37; +defparam \z80_|execute_|setM1~57 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X41_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|fMRead~28 ( +// Location: LCCOMB_X29_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~5 ( // Equation(s): -// \z80_|execute_|fMRead~28_combout = ((\z80_|execute_|ixy_d~6_combout & ((\z80_|pla_decode_|Equal41~2_combout ) # (\z80_|pla_decode_|Equal9~1_combout )))) # (!\z80_|execute_|nextM~4_combout ) +// \z80_|execute_|ctl_sw_2u~5_combout = (\z80_|execute_|ctl_sw_2u~1_combout & (\z80_|execute_|ctl_sw_2u~4_combout & \z80_|execute_|setM1~57_combout )) - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|pla_decode_|Equal41~2_combout ), + .dataa(gnd), + .datab(\z80_|execute_|ctl_sw_2u~1_combout ), + .datac(\z80_|execute_|ctl_sw_2u~4_combout ), + .datad(\z80_|execute_|setM1~57_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~5 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_sw_2u~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~7_combout = (\z80_|execute_|ctl_reg_out_lo~6_combout & (((!\z80_|execute_|ctl_reg_gp_sel~7_combout & \z80_|execute_|ctl_sw_2u~5_combout )) # (!\z80_|execute_|rsel0~combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel~7_combout ), + .datab(\z80_|execute_|rsel0~combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~6_combout ), + .datad(\z80_|execute_|ctl_sw_2u~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~7 .lut_mask = 16'h7030; +defparam \z80_|execute_|ctl_reg_out_lo~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~0_combout = (\z80_|execute_|ctl_alu_shift_oe~14_combout & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|execute_|ctl_mWrite~4_combout & !\z80_|ir_|opcode [0]))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datab(\z80_|pla_decode_|Equal2~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~0 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~41 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~41_combout = (\z80_|execute_|ixy_d~9_combout & (((!\z80_|pla_decode_|Equal10~0_combout & !\z80_|pla_decode_|Equal11~0_combout )))) # (!\z80_|execute_|ixy_d~9_combout & (((!\z80_|pla_decode_|Equal11~0_combout )) # +// (!\z80_|execute_|ctl_alu_shift_oe~14_combout ))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datab(\z80_|execute_|ixy_d~9_combout ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|pla_decode_|Equal11~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~41 .lut_mask = 16'h113F; +defparam \z80_|execute_|ctl_bus_inc_oe~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~86 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~86_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|pla_decode_|Equal19~0_combout ) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|pla_decode_|Equal19~0_combout ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|sequencer_|M5~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~86_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~86 .lut_mask = 16'h3F7F; +defparam \z80_|execute_|ctl_inc_cy~86 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y18_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~88 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~88_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|pla_decode_|Equal34~0_combout ) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|pla_decode_|Equal34~0_combout ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~88_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~88 .lut_mask = 16'h37FF; +defparam \z80_|execute_|ctl_inc_cy~88 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~36 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~36_combout = (\z80_|execute_|ctl_inc_cy~88_combout & (((!\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ctl_alu_op_low~22_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|pla_decode_|Equal47~0_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datad(\z80_|execute_|ctl_inc_cy~88_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~36 .lut_mask = 16'h3700; +defparam \z80_|execute_|ctl_inc_cy~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~87 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~87_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|pla_decode_|Equal9~1_combout ) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|sequencer_|M5~q ), .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|execute_|nextM~4_combout ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), .cin(gnd), - .combout(\z80_|execute_|fMRead~28_combout ), + .combout(\z80_|execute_|ctl_inc_cy~87_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~28 .lut_mask = 16'hA8FF; -defparam \z80_|execute_|fMRead~28 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~87 .lut_mask = 16'h1FFF; +defparam \z80_|execute_|ctl_inc_cy~87 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X41_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|fMRead~32 ( +// Location: LCCOMB_X20_Y18_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~26 ( // Equation(s): -// \z80_|execute_|fMRead~32_combout = ((\z80_|execute_|fMRead~31_combout ) # ((\z80_|execute_|fMRead~30_combout ) # (\z80_|execute_|fMRead~28_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ) +// \z80_|execute_|ctl_bus_inc_oe~26_combout = (\z80_|execute_|ctl_inc_cy~86_combout & (\z80_|execute_|ctl_inc_cy~36_combout & \z80_|execute_|ctl_inc_cy~87_combout )) - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ), - .datab(\z80_|execute_|fMRead~31_combout ), - .datac(\z80_|execute_|fMRead~30_combout ), - .datad(\z80_|execute_|fMRead~28_combout ), + .dataa(\z80_|execute_|ctl_inc_cy~86_combout ), + .datab(\z80_|execute_|ctl_inc_cy~36_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_inc_cy~87_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~32_combout ), + .combout(\z80_|execute_|ctl_bus_inc_oe~26_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~32 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|fMRead~32 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_inc_oe~26 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_bus_inc_oe~26 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y18_N30 +// Location: LCCOMB_X30_Y19_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~9 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~9_combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_M4_ff~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~9 .lut_mask = 16'hC0C0; +defparam \z80_|execute_|ctl_mWrite~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y18_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~1 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we~1_combout = (\z80_|pla_decode_|Equal10~0_combout & (((\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (\z80_|execute_|ctl_mWrite~9_combout )))) # (!\z80_|pla_decode_|Equal10~0_combout & (\z80_|execute_|ctl_mRead~34_combout +// & ((\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (\z80_|execute_|ctl_mWrite~9_combout )))) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datad(\z80_|execute_|ctl_mWrite~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we~1 .lut_mask = 16'hEEE0; +defparam \z80_|execute_|ctl_reg_sys_we~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y18_N20 cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~42 ( // Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~42_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~5_combout & (\z80_|execute_|ctl_inc_cy~77_combout & \z80_|execute_|ctl_inc_cy~53_combout )) +// \z80_|execute_|ctl_bus_inc_oe~42_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~0_combout & (\z80_|execute_|ctl_bus_inc_oe~41_combout & (\z80_|execute_|ctl_bus_inc_oe~26_combout & !\z80_|execute_|ctl_reg_sys_we~1_combout ))) - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), - .datab(\z80_|execute_|ctl_inc_cy~77_combout ), - .datac(\z80_|execute_|ctl_inc_cy~53_combout ), - .datad(gnd), + .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~0_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~26_combout ), + .datad(\z80_|execute_|ctl_reg_sys_we~1_combout ), .cin(gnd), .combout(\z80_|execute_|ctl_bus_inc_oe~42_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~42 .lut_mask = 16'h8080; +defparam \z80_|execute_|ctl_bus_inc_oe~42 .lut_mask = 16'h0040; defparam \z80_|execute_|ctl_bus_inc_oe~42 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y18_N12 -cycloneive_lcell_comb \z80_|execute_|fMRead~14 ( +// Location: LCCOMB_X21_Y16_N22 +cycloneive_lcell_comb \z80_|pla_decode_|Equal40~2 ( // Equation(s): -// \z80_|execute_|fMRead~14_combout = (\z80_|execute_|ctl_mRead~23_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout ) # ((\z80_|execute_|ctl_mRead~15_combout ) # (\z80_|execute_|ctl_ir_we~12_combout ))) +// \z80_|pla_decode_|Equal40~2_combout = (!\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal6~0_combout & (!\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [0]))) - .dataa(\z80_|execute_|ctl_mRead~23_combout ), + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal40~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal40~2 .lut_mask = 16'h0004; +defparam \z80_|pla_decode_|Equal40~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~14 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~14_combout = (!\z80_|pla_decode_|Equal52~1_combout & (((\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal40~2_combout )) # (!\z80_|pla_decode_|Equal21~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal52~1_combout ), + .datab(\z80_|pla_decode_|Equal21~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal40~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~14 .lut_mask = 16'h5155; +defparam \z80_|execute_|ctl_reg_sel_pc~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y16_N28 +cycloneive_lcell_comb \z80_|pla_decode_|Equal55~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal55~0_combout = (!\z80_|ir_|opcode [2] & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [0])) + + .dataa(\z80_|ir_|opcode [2]), + .datab(gnd), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal55~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal55~0 .lut_mask = 16'h0050; +defparam \z80_|pla_decode_|Equal55~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~11 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~11_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal55~0_combout & \z80_|ir_|opcode [3]))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~11 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_mRead~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N4 +cycloneive_lcell_comb \z80_|pla_decode_|Equal6~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal6~1_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal1~4_combout & \z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|pla_decode_|Equal1~4_combout ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal6~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal6~1 .lut_mask = 16'h4000; +defparam \z80_|pla_decode_|Equal6~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|setM1~36 ( +// Equation(s): +// \z80_|execute_|setM1~36_combout = (!\z80_|pla_decode_|Equal6~1_combout & (((!\z80_|ir_|opcode [5] & !\z80_|pla_decode_|Equal3~0_combout )) # (!\z80_|pla_decode_|Equal40~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal6~1_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal3~0_combout ), + .datad(\z80_|pla_decode_|Equal40~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~36 .lut_mask = 16'h0155; +defparam \z80_|execute_|setM1~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|comb~1 ( +// Equation(s): +// \z80_|execute_|comb~1_combout = (\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4]) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [5]), + .datac(gnd), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|comb~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|comb~1 .lut_mask = 16'hCC00; +defparam \z80_|execute_|comb~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~13 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~13_combout = (\z80_|execute_|comb~1_combout & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal55~0_combout ))) + + .dataa(\z80_|execute_|comb~1_combout ), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~13 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_mRead~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~11 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~11_combout = (!\z80_|pla_decode_|Equal41~2_combout & (!\z80_|execute_|ctl_mRead~13_combout & (!\z80_|execute_|ctl_mRead~8_combout & !\z80_|execute_|ctl_mRead~6_combout ))) + + .dataa(\z80_|pla_decode_|Equal41~2_combout ), + .datab(\z80_|execute_|ctl_mRead~13_combout ), + .datac(\z80_|execute_|ctl_mRead~8_combout ), + .datad(\z80_|execute_|ctl_mRead~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~11 .lut_mask = 16'h0001; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N28 +cycloneive_lcell_comb \z80_|pla_decode_|Equal24~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal24~0_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|pla_decode_|Equal2~0_combout & !\z80_|ir_|opcode [5]))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal52~0_combout ), + .datac(\z80_|pla_decode_|Equal2~0_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal24~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal24~0 .lut_mask = 16'h0080; +defparam \z80_|pla_decode_|Equal24~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N12 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~26 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~26_combout = (!\z80_|pla_decode_|Equal35~0_combout & ((\z80_|ir_|opcode [4]) # ((\z80_|ir_|opcode [3]) # (!\z80_|pla_decode_|Equal24~0_combout )))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|pla_decode_|Equal35~0_combout ), + .datad(\z80_|pla_decode_|Equal24~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~26 .lut_mask = 16'h0E0F; +defparam \z80_|execute_|pc_inc_hold~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|setM1~37 ( +// Equation(s): +// \z80_|execute_|setM1~37_combout = (!\z80_|pla_decode_|Equal19~0_combout & (\z80_|execute_|setM1~36_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~11_combout & \z80_|execute_|pc_inc_hold~26_combout ))) + + .dataa(\z80_|pla_decode_|Equal19~0_combout ), + .datab(\z80_|execute_|setM1~36_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~11_combout ), + .datad(\z80_|execute_|pc_inc_hold~26_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~37 .lut_mask = 16'h4000; +defparam \z80_|execute_|setM1~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~6 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~6_combout = (!\z80_|pla_decode_|Equal33~2_combout & (((!\z80_|pla_decode_|Equal50~0_combout & !\z80_|pla_decode_|Equal49~0_combout )) # (!\z80_|decode_state_|use_ixiy~combout ))) + + .dataa(\z80_|decode_state_|use_ixiy~combout ), + .datab(\z80_|pla_decode_|Equal50~0_combout ), + .datac(\z80_|pla_decode_|Equal33~2_combout ), + .datad(\z80_|pla_decode_|Equal49~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~6 .lut_mask = 16'h0507; +defparam \z80_|execute_|pc_inc_hold~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo~38 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo~38_combout = (\z80_|execute_|pc_inc_hold~6_combout & (((!\z80_|pla_decode_|Equal33~1_combout ) # (!\z80_|pla_decode_|Equal6~0_combout )) # (!\z80_|pla_decode_|Equal55~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|pla_decode_|Equal33~1_combout ), + .datad(\z80_|execute_|pc_inc_hold~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo~38 .lut_mask = 16'h7F00; +defparam \z80_|execute_|ctl_reg_sys_hilo~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|fMRead~7 ( +// Equation(s): +// \z80_|execute_|fMRead~7_combout = (\z80_|execute_|ctl_reg_sel_pc~14_combout & (!\z80_|execute_|ctl_mRead~11_combout & (\z80_|execute_|setM1~37_combout & \z80_|execute_|ctl_reg_sys_hilo~38_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~14_combout ), + .datab(\z80_|execute_|ctl_mRead~11_combout ), + .datac(\z80_|execute_|setM1~37_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo~38_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~7 .lut_mask = 16'h2000; +defparam \z80_|execute_|fMRead~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~12 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~12_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal6~0_combout & !\z80_|pla_decode_|Equal33~1_combout )) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~12 .lut_mask = 16'h0088; +defparam \z80_|execute_|ctl_mRead~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~31 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~31_combout = (!\z80_|execute_|ctl_mRead~12_combout & ((\z80_|ir_|opcode [3]) # ((\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal12~0_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~12_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|pla_decode_|Equal12~0_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~31 .lut_mask = 16'h5545; +defparam \z80_|execute_|ctl_bus_inc_oe~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_alu_shift_oe~14_combout & \z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~1_combout ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N12 +cycloneive_lcell_comb \z80_|nM1_int~2 ( +// Equation(s): +// \z80_|nM1_int~2_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|nM1_int~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|nM1_int~2 .lut_mask = 16'h000F; +defparam \z80_|nM1_int~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~0 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~0_combout = (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|M5~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(gnd), + .datad(\z80_|sequencer_|M5~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~0 .lut_mask = 16'hCC00; +defparam \z80_|execute_|ctl_sw_4u~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~10 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~10_combout = (\z80_|execute_|ctl_mRead~8_combout & (!\z80_|execute_|ctl_alu_shift_oe~14_combout & (!\z80_|execute_|ctl_sw_4u~0_combout ))) # (!\z80_|execute_|ctl_mRead~8_combout & +// (((!\z80_|execute_|ctl_alu_shift_oe~14_combout & !\z80_|execute_|ctl_sw_4u~0_combout )) # (!\z80_|execute_|ctl_mRead~6_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~8_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datac(\z80_|execute_|ctl_sw_4u~0_combout ), + .datad(\z80_|execute_|ctl_mRead~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~10 .lut_mask = 16'h0357; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|fMRead~6 ( +// Equation(s): +// \z80_|execute_|fMRead~6_combout = (\z80_|execute_|ctl_mRead~13_combout & (!\z80_|execute_|ctl_alu_shift_oe~14_combout & ((!\z80_|execute_|ctl_alu_op_low~22_combout ) # (!\z80_|execute_|ctl_state_alu~6_combout )))) # +// (!\z80_|execute_|ctl_mRead~13_combout & (((!\z80_|execute_|ctl_alu_op_low~22_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~13_combout ), + .datab(\z80_|execute_|ctl_state_alu~6_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~6 .lut_mask = 16'h153F; +defparam \z80_|execute_|fMRead~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~12 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~12_combout = (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|execute_|ctl_mWrite~17_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|sequencer_|DFFE_M4_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|execute_|ctl_mWrite~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~12 .lut_mask = 16'h5F7F; +defparam \z80_|execute_|ctl_inc_dec~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~15 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~15_combout = (!\z80_|nM1_int~2_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout & (\z80_|execute_|fMRead~6_combout & \z80_|execute_|ctl_inc_dec~12_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), + .datac(\z80_|execute_|fMRead~6_combout ), + .datad(\z80_|execute_|ctl_inc_dec~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~15 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N28 +cycloneive_lcell_comb \z80_|pla_decode_|Equal25~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal25~0_combout = (!\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal55~0_combout ))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal25~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal25~0 .lut_mask = 16'h4000; +defparam \z80_|pla_decode_|Equal25~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal12~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal12~1_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal2~0_combout & !\z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|pla_decode_|Equal2~0_combout ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal12~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal12~1 .lut_mask = 16'h0040; +defparam \z80_|pla_decode_|Equal12~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~38 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~38_combout = ((\z80_|pla_decode_|Equal12~1_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~14_combout & !\z80_|execute_|ctl_sw_4u~0_combout ))) # (!\z80_|pla_decode_|Equal25~0_combout ) + + .dataa(\z80_|pla_decode_|Equal25~0_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datac(\z80_|pla_decode_|Equal12~1_combout ), + .datad(\z80_|execute_|ctl_sw_4u~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~38 .lut_mask = 16'hF5F7; +defparam \z80_|execute_|ctl_inc_cy~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~82 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~82_combout = ((!\z80_|sequencer_|DFFE_M2_ff~q ) # (!\z80_|pla_decode_|Equal13~2_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|pla_decode_|Equal13~2_combout ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~82_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~82 .lut_mask = 16'h77FF; +defparam \z80_|execute_|ctl_inc_cy~82 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~14 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~14_combout = (\z80_|execute_|ctl_inc_cy~38_combout & (\z80_|execute_|ctl_inc_cy~39_combout & (\z80_|execute_|ctl_reg_sel_pc~10_combout & \z80_|execute_|ctl_inc_cy~82_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~38_combout ), + .datab(\z80_|execute_|ctl_inc_cy~39_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~10_combout ), + .datad(\z80_|execute_|ctl_inc_cy~82_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~14 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~16 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~16_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout & +// \z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~16 .lut_mask = 16'h1000; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~32 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~32_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~16_combout & (((\z80_|execute_|fMRead~7_combout & \z80_|execute_|ctl_bus_inc_oe~31_combout )) # (!\z80_|execute_|ctl_alu_op_low~22_combout ))) + + .dataa(\z80_|execute_|fMRead~7_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~31_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~32 .lut_mask = 16'hB300; +defparam \z80_|execute_|ctl_bus_inc_oe~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~77 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~77_combout = (\z80_|execute_|ixy_d~5_combout & (((!\z80_|pla_decode_|Equal37~0_combout & !\z80_|pla_decode_|Equal38~2_combout )))) # (!\z80_|execute_|ixy_d~5_combout & (((!\z80_|pla_decode_|Equal37~0_combout & +// !\z80_|pla_decode_|Equal38~2_combout )) # (!\z80_|execute_|ctl_alu_op_low~22_combout ))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datac(\z80_|pla_decode_|Equal37~0_combout ), + .datad(\z80_|pla_decode_|Equal38~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~77_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~77 .lut_mask = 16'h111F; +defparam \z80_|execute_|ctl_inc_cy~77 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N4 +cycloneive_lcell_comb \z80_|pla_decode_|Equal29~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal29~0_combout = (\z80_|pla_decode_|Equal1~7_combout & (\z80_|pla_decode_|Equal32~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal1~4_combout ))) + + .dataa(\z80_|pla_decode_|Equal1~7_combout ), + .datab(\z80_|pla_decode_|Equal32~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal1~4_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal29~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal29~0 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal29~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~78 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~78_combout = (\z80_|execute_|ctl_inc_cy~77_combout & (((!\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ctl_alu_op_low~22_combout )) # (!\z80_|pla_decode_|Equal29~0_combout ))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datac(\z80_|execute_|ctl_inc_cy~77_combout ), + .datad(\z80_|pla_decode_|Equal29~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~78_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~78 .lut_mask = 16'h10F0; +defparam \z80_|execute_|ctl_inc_cy~78 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~79 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~79_combout = (\z80_|execute_|ctl_inc_cy~78_combout & (((!\z80_|execute_|ctl_sw_4u~0_combout & !\z80_|execute_|ctl_alu_shift_oe~14_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) + + .dataa(\z80_|execute_|ctl_sw_4u~0_combout ), + .datab(\z80_|pla_decode_|Equal47~0_combout ), + .datac(\z80_|execute_|ctl_inc_cy~78_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~79_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~79 .lut_mask = 16'h3070; +defparam \z80_|execute_|ctl_inc_cy~79 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~14 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~14_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal1~4_combout ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal52~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal1~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~14 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_mRead~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y18_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~49 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~49_combout = (\z80_|execute_|ixy_d~5_combout & (!\z80_|pla_decode_|Equal9~1_combout & (!\z80_|execute_|ctl_mRead~14_combout ))) # (!\z80_|execute_|ixy_d~5_combout & (((!\z80_|pla_decode_|Equal9~1_combout & +// !\z80_|execute_|ctl_mRead~14_combout )) # (!\z80_|execute_|ctl_alu_op_low~22_combout ))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|pla_decode_|Equal9~1_combout ), + .datac(\z80_|execute_|ctl_mRead~14_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~49_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~49 .lut_mask = 16'h0357; +defparam \z80_|execute_|ctl_inc_cy~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y18_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~5_combout = ((!\z80_|pla_decode_|Equal11~0_combout & (!\z80_|execute_|ctl_mRead~34_combout & !\z80_|pla_decode_|Equal10~0_combout ))) # (!\z80_|execute_|ctl_alu_op_low~22_combout ) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~5 .lut_mask = 16'h01FF; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y18_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~40 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~40_combout = (\z80_|execute_|ctl_inc_cy~79_combout & (\z80_|execute_|ctl_inc_cy~49_combout & \z80_|execute_|ctl_reg_gp_sel[1]~5_combout )) + + .dataa(\z80_|execute_|ctl_inc_cy~79_combout ), + .datab(\z80_|execute_|ctl_inc_cy~49_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~40 .lut_mask = 16'h8080; +defparam \z80_|execute_|ctl_bus_inc_oe~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~5 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~5_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal33~1_combout & (!\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|pla_decode_|Equal33~1_combout ), + .datac(\z80_|decode_state_|use_ixiy~combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~5 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_mRead~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~44 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~44_combout = (\z80_|decode_state_|DFFE_inst4~q ) # ((\z80_|decode_state_|DFFE_instIY1~q ) # ((!\z80_|pla_decode_|Equal49~0_combout & !\z80_|pla_decode_|Equal50~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal49~0_combout ), + .datab(\z80_|decode_state_|DFFE_inst4~q ), + .datac(\z80_|pla_decode_|Equal50~0_combout ), + .datad(\z80_|decode_state_|DFFE_instIY1~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~44 .lut_mask = 16'hFFCD; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~36 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~36_combout = (\z80_|execute_|ctl_mRead~5_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout ) # ((\z80_|execute_|ctl_mRead~4_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~5_combout ), .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_mRead~15_combout ), - .datad(\z80_|execute_|ctl_ir_we~12_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ), + .datad(\z80_|execute_|ctl_mRead~4_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~14_combout ), + .combout(\z80_|execute_|ctl_bus_inc_oe~36_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~14 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|fMRead~14 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_inc_oe~36 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|ctl_bus_inc_oe~36 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y18_N18 -cycloneive_lcell_comb \z80_|execute_|fMRead~10 ( +// Location: LCCOMB_X21_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~35 ( // Equation(s): -// \z80_|execute_|fMRead~10_combout = (!\z80_|execute_|ctl_mRead~4_combout & (!\z80_|pla_decode_|Equal6~1_combout & (!\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_bus_db_oe~1_combout ))) +// \z80_|execute_|ctl_bus_inc_oe~35_combout = (\z80_|execute_|ctl_state_alu~6_combout ) # ((\z80_|pla_decode_|Equal13~2_combout ) # (\z80_|execute_|ctl_mRead~8_combout )) - .dataa(\z80_|execute_|ctl_mRead~4_combout ), - .datab(\z80_|pla_decode_|Equal6~1_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .dataa(\z80_|execute_|ctl_state_alu~6_combout ), + .datab(\z80_|pla_decode_|Equal13~2_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_mRead~8_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~10_combout ), + .combout(\z80_|execute_|ctl_bus_inc_oe~35_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~10 .lut_mask = 16'h0100; -defparam \z80_|execute_|fMRead~10 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_inc_oe~35 .lut_mask = 16'hFFEE; +defparam \z80_|execute_|ctl_bus_inc_oe~35 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y18_N28 -cycloneive_lcell_comb \z80_|execute_|fMRead~9 ( +// Location: LCCOMB_X21_Y17_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~46 ( // Equation(s): -// \z80_|execute_|fMRead~9_combout = (\z80_|execute_|ctl_mRead~23_combout ) # (((\z80_|execute_|ctl_mRead~13_combout ) # (!\z80_|execute_|nextM~3_combout )) # (!\z80_|execute_|pc_inc_hold~28_combout )) +// \z80_|execute_|ctl_bus_inc_oe~46_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|execute_|ctl_bus_inc_oe~36_combout ) # (\z80_|execute_|ctl_bus_inc_oe~35_combout )))) - .dataa(\z80_|execute_|ctl_mRead~23_combout ), - .datab(\z80_|execute_|pc_inc_hold~28_combout ), - .datac(\z80_|execute_|ctl_mRead~13_combout ), - .datad(\z80_|execute_|nextM~3_combout ), + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|execute_|ctl_bus_inc_oe~36_combout ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|execute_|ctl_bus_inc_oe~35_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~9_combout ), + .combout(\z80_|execute_|ctl_bus_inc_oe~46_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~9 .lut_mask = 16'hFBFF; -defparam \z80_|execute_|fMRead~9 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_inc_oe~46 .lut_mask = 16'h5040; +defparam \z80_|execute_|ctl_bus_inc_oe~46 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y18_N24 -cycloneive_lcell_comb \z80_|execute_|fMRead~11 ( +// Location: LCCOMB_X24_Y11_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~33 ( // Equation(s): -// \z80_|execute_|fMRead~11_combout = (\z80_|execute_|ctl_state_alu~4_combout & (((\z80_|execute_|ctl_ir_we~14_combout ) # (\z80_|execute_|fMRead~9_combout )) # (!\z80_|execute_|fMRead~10_combout ))) +// \z80_|execute_|ctl_bus_inc_oe~33_combout = (\z80_|execute_|pc_inc_hold~26_combout & (!\z80_|pla_decode_|Equal6~1_combout & ((!\z80_|pla_decode_|Equal33~2_combout ) # (!\z80_|decode_state_|use_ixiy~combout )))) - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|fMRead~10_combout ), - .datac(\z80_|execute_|ctl_ir_we~14_combout ), - .datad(\z80_|execute_|fMRead~9_combout ), + .dataa(\z80_|decode_state_|use_ixiy~combout ), + .datab(\z80_|execute_|pc_inc_hold~26_combout ), + .datac(\z80_|pla_decode_|Equal6~1_combout ), + .datad(\z80_|pla_decode_|Equal33~2_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~11_combout ), + .combout(\z80_|execute_|ctl_bus_inc_oe~33_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~11 .lut_mask = 16'hAAA2; -defparam \z80_|execute_|fMRead~11 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_inc_oe~33 .lut_mask = 16'h040C; +defparam \z80_|execute_|ctl_bus_inc_oe~33 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|fMRead~12 ( +// Location: LCCOMB_X21_Y17_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~47 ( // Equation(s): -// \z80_|execute_|fMRead~12_combout = (\z80_|execute_|ctl_ir_we~8_combout ) # ((\z80_|execute_|ctl_ir_we~14_combout ) # ((\z80_|pla_decode_|Equal49~0_combout & !\z80_|decode_state_|use_ixiy~combout ))) +// \z80_|execute_|ctl_bus_inc_oe~47_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & ((!\z80_|execute_|ctl_bus_inc_oe~33_combout ) # (!\z80_|execute_|nextM~2_combout )))) - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|execute_|nextM~2_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~47 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_bus_inc_oe~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal8~0_combout & (\z80_|sequencer_|DFFE_T5_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ))) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|pla_decode_|Equal8~0_combout ), + .datac(\z80_|sequencer_|DFFE_T5_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~45 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~45_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout & (((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|pla_decode_|Equal11~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~45 .lut_mask = 16'h070F; +defparam \z80_|execute_|ctl_bus_inc_oe~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~34 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~34_combout = ((\z80_|execute_|ctl_alu_oe~0_combout & ((\z80_|execute_|ctl_mRead~4_combout ) # (\z80_|execute_|ctl_mRead~8_combout )))) # (!\z80_|execute_|ctl_bus_inc_oe~45_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~45_combout ), + .datab(\z80_|execute_|ctl_mRead~4_combout ), + .datac(\z80_|execute_|ctl_alu_oe~0_combout ), + .datad(\z80_|execute_|ctl_mRead~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~34 .lut_mask = 16'hF5D5; +defparam \z80_|execute_|ctl_bus_inc_oe~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout = (\z80_|pla_decode_|Equal9~1_combout & (\z80_|sequencer_|M5~q & \z80_|sequencer_|DFFE_T4_ff~q )) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(gnd), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~6 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~6_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal52~0_combout & \z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal3~1_combout ), + .datac(\z80_|pla_decode_|Equal52~0_combout ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~6 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_mWrite~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~50 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~50_combout = (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|execute_|ctl_mWrite~6_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|execute_|ctl_mWrite~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~50_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~50 .lut_mask = 16'h37FF; +defparam \z80_|execute_|ctl_bus_inc_oe~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal4~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal4~0_combout = (\z80_|pla_decode_|Equal1~4_combout & (\z80_|pla_decode_|Equal1~7_combout & (\z80_|ir_|opcode [3] & \z80_|execute_|comb~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal1~4_combout ), + .datab(\z80_|pla_decode_|Equal1~7_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|execute_|comb~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal4~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal4~0 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~48 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~48_combout = (\z80_|execute_|ctl_bus_inc_oe~50_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|pla_decode_|Equal4~0_combout )) # (!\z80_|sequencer_|DFFE_T5_ff~q ))) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~50_combout ), + .datab(\z80_|sequencer_|DFFE_T5_ff~q ), + .datac(\z80_|pla_decode_|Equal4~0_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~48 .lut_mask = 16'hAA2A; +defparam \z80_|execute_|ctl_bus_inc_oe~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~49 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~49_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q ))) # (!\z80_|execute_|ctl_mRead~6_combout ) + + .dataa(\z80_|sequencer_|M5~q ), + .datab(\z80_|execute_|ctl_mRead~6_combout ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~49_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~49 .lut_mask = 16'hFF37; +defparam \z80_|execute_|ctl_bus_inc_oe~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~7 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~7_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal55~0_combout & \z80_|pla_decode_|Equal6~0_combout )) + + .dataa(\z80_|pla_decode_|Equal33~1_combout ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~7 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_mRead~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~29 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~29_combout = (\z80_|execute_|ixy_d~5_combout & (!\z80_|execute_|ctl_mWrite~17_combout & ((!\z80_|execute_|ctl_ir_we~4_combout ) # (!\z80_|execute_|ctl_mRead~7_combout )))) # (!\z80_|execute_|ixy_d~5_combout & +// (((!\z80_|execute_|ctl_ir_we~4_combout )) # (!\z80_|execute_|ctl_mRead~7_combout ))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_mRead~7_combout ), + .datac(\z80_|execute_|ctl_mWrite~17_combout ), + .datad(\z80_|execute_|ctl_ir_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~29 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_bus_inc_oe~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~11_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # (((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|sequencer_|M5~q )) + + .dataa(\z80_|execute_|ctl_ir_we~9_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|M5~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~11 .lut_mask = 16'hF1FF; +defparam \z80_|execute_|ctl_alu_core_S~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y17_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~27 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~27_combout = (\z80_|execute_|ctl_alu_oe~0_combout & (!\z80_|execute_|ctl_ir_we~14_combout & ((!\z80_|execute_|ctl_ir_we~8_combout )))) # (!\z80_|execute_|ctl_alu_oe~0_combout & (((!\z80_|execute_|ixy_d~7_combout )) # +// (!\z80_|execute_|ctl_ir_we~14_combout ))) + + .dataa(\z80_|execute_|ctl_alu_oe~0_combout ), .datab(\z80_|execute_|ctl_ir_we~14_combout ), - .datac(\z80_|pla_decode_|Equal49~0_combout ), - .datad(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ctl_ir_we~8_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~12_combout ), + .combout(\z80_|execute_|ctl_bus_inc_oe~27_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~12 .lut_mask = 16'hEEFE; -defparam \z80_|execute_|fMRead~12 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_inc_oe~27 .lut_mask = 16'h1537; +defparam \z80_|execute_|ctl_bus_inc_oe~27 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y18_N14 -cycloneive_lcell_comb \z80_|execute_|fMRead~13 ( +// Location: LCCOMB_X23_Y19_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~44 ( // Equation(s): -// \z80_|execute_|fMRead~13_combout = (!\z80_|execute_|fMWrite~5_combout & ((\z80_|execute_|fMRead~12_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout ) # (\z80_|execute_|ctl_mRead~6_combout )))) +// \z80_|execute_|ctl_bus_inc_oe~44_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~7_combout )) # (!\z80_|sequencer_|M5~q )) - .dataa(\z80_|execute_|fMRead~12_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_mRead~6_combout ), - .datad(\z80_|execute_|fMWrite~5_combout ), + .dataa(\z80_|execute_|ctl_ir_we~10_combout ), + .datab(\z80_|execute_|ctl_ir_we~7_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|M5~q ), .cin(gnd), - .combout(\z80_|execute_|fMRead~13_combout ), + .combout(\z80_|execute_|ctl_bus_inc_oe~44_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~13 .lut_mask = 16'h00FE; -defparam \z80_|execute_|fMRead~13 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_inc_oe~44 .lut_mask = 16'hF1FF; +defparam \z80_|execute_|ctl_bus_inc_oe~44 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y18_N30 -cycloneive_lcell_comb \z80_|execute_|fMRead~15 ( +// Location: LCCOMB_X25_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~28 ( // Equation(s): -// \z80_|execute_|fMRead~15_combout = (\z80_|execute_|fMRead~11_combout ) # ((\z80_|execute_|fMRead~13_combout ) # ((\z80_|execute_|fMRead~14_combout & \z80_|execute_|ctl_state_alu~6_combout ))) +// \z80_|execute_|ctl_bus_inc_oe~28_combout = (\z80_|execute_|ctl_alu_core_S~11_combout & (\z80_|execute_|ctl_bus_inc_oe~27_combout & \z80_|execute_|ctl_bus_inc_oe~44_combout )) - .dataa(\z80_|execute_|fMRead~14_combout ), - .datab(\z80_|execute_|fMRead~11_combout ), - .datac(\z80_|execute_|fMRead~13_combout ), - .datad(\z80_|execute_|ctl_state_alu~6_combout ), + .dataa(\z80_|execute_|ctl_alu_core_S~11_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~27_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_bus_inc_oe~44_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~15_combout ), + .combout(\z80_|execute_|ctl_bus_inc_oe~28_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~15 .lut_mask = 16'hFEFC; -defparam \z80_|execute_|fMRead~15 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_inc_oe~28 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_bus_inc_oe~28 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y17_N2 -cycloneive_lcell_comb \z80_|execute_|fMRead~20 ( +// Location: LCCOMB_X23_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~30 ( // Equation(s): -// \z80_|execute_|fMRead~20_combout = (((\z80_|execute_|fMRead~15_combout ) # (!\z80_|execute_|ctl_sw_4d~2_combout )) # (!\z80_|execute_|fMRead~19_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~42_combout ) +// \z80_|execute_|ctl_bus_inc_oe~30_combout = (\z80_|execute_|ctl_bus_inc_oe~49_combout & (\z80_|execute_|ctl_bus_inc_oe~29_combout & \z80_|execute_|ctl_bus_inc_oe~28_combout )) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~49_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~29_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_bus_inc_oe~28_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~30 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_bus_inc_oe~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~3 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~3_combout = (\z80_|pla_decode_|Equal1~7_combout & (\z80_|pla_decode_|Equal2~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal21~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal1~7_combout ), + .datab(\z80_|pla_decode_|Equal2~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal21~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~3 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_mRead~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|fMRead~3 ( +// Equation(s): +// \z80_|execute_|fMRead~3_combout = ((!\z80_|pla_decode_|Equal33~0_combout ) # (!\z80_|ir_|opcode [7])) # (!\z80_|execute_|ctl_ir_we~5_combout ) + + .dataa(\z80_|execute_|ctl_ir_we~5_combout ), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|fMRead~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~3 .lut_mask = 16'h7F7F; +defparam \z80_|execute_|fMRead~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~37 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~37_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mRead~3_combout ) # ((\z80_|execute_|ctl_mRead~4_combout ) # (!\z80_|execute_|fMRead~3_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~3_combout ), + .datab(\z80_|execute_|ctl_mRead~4_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|fMRead~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~37 .lut_mask = 16'hE0F0; +defparam \z80_|execute_|ctl_bus_inc_oe~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~38 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~38_combout = (\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ) # (((\z80_|execute_|ctl_bus_inc_oe~37_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~30_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~48_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~48_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~30_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~37_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~38 .lut_mask = 16'hFFBF; +defparam \z80_|execute_|ctl_bus_inc_oe~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~39 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~39_combout = (\z80_|execute_|ctl_bus_inc_oe~46_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~47_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~34_combout ) # (\z80_|execute_|ctl_bus_inc_oe~38_combout ))) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~46_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~47_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~34_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~38_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~39 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_bus_inc_oe~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~43 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~43_combout = (((\z80_|execute_|ctl_bus_inc_oe~39_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~40_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~32_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~42_combout ) .dataa(\z80_|execute_|ctl_bus_inc_oe~42_combout ), - .datab(\z80_|execute_|fMRead~19_combout ), - .datac(\z80_|execute_|fMRead~15_combout ), - .datad(\z80_|execute_|ctl_sw_4d~2_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~32_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~40_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~39_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~20_combout ), + .combout(\z80_|execute_|ctl_bus_inc_oe~43_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~20 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|fMRead~20 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_inc_oe~43 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_bus_inc_oe~43 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~48 ( +// Location: LCCOMB_X28_Y16_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~3 ( // Equation(s): -// \z80_|execute_|pc_inc_hold~48_combout = (\z80_|execute_|ixy_d~5_combout & ((\z80_|pla_decode_|Equal35~0_combout ) # ((\z80_|pla_decode_|Equal24~0_combout & \z80_|pla_decode_|Equal9~0_combout )))) +// \z80_|execute_|ctl_alu_oe~3_combout = (\z80_|decode_state_|in_halt~q ) # (((!\z80_|pla_decode_|Equal33~0_combout & !\z80_|pla_decode_|Equal33~1_combout )) # (!\z80_|pla_decode_|Equal77~0_combout )) - .dataa(\z80_|pla_decode_|Equal24~0_combout ), - .datab(\z80_|pla_decode_|Equal35~0_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|pla_decode_|Equal9~0_combout ), + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|decode_state_|in_halt~q ), + .datac(\z80_|pla_decode_|Equal33~1_combout ), + .datad(\z80_|pla_decode_|Equal77~0_combout ), .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~48_combout ), + .combout(\z80_|execute_|ctl_alu_oe~3_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~48 .lut_mask = 16'hE0C0; -defparam \z80_|execute_|pc_inc_hold~48 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_alu_oe~3 .lut_mask = 16'hCDFF; +defparam \z80_|execute_|ctl_alu_oe~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X41_Y16_N30 -cycloneive_lcell_comb \z80_|execute_|fMRead~22 ( +// Location: LCCOMB_X25_Y14_N8 +cycloneive_lcell_comb \z80_|execute_|fMWrite~1 ( // Equation(s): -// \z80_|execute_|fMRead~22_combout = (\z80_|execute_|ctl_mRead~17_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # ((\z80_|execute_|ctl_alu_oe~2_combout )))) # (!\z80_|execute_|ctl_mRead~17_combout & (\z80_|execute_|ctl_mRead~18_combout & -// ((\z80_|execute_|ctl_ir_we~4_combout ) # (\z80_|execute_|ctl_alu_oe~2_combout )))) +// \z80_|execute_|fMWrite~1_combout = (!\z80_|execute_|ctl_ir_we~15_combout & (!\z80_|execute_|ctl_mRead~4_combout & (!\z80_|execute_|ctl_ir_we~14_combout & !\z80_|execute_|ctl_ir_we~7_combout ))) - .dataa(\z80_|execute_|ctl_mRead~17_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_mRead~18_combout ), - .datad(\z80_|execute_|ctl_alu_oe~2_combout ), + .dataa(\z80_|execute_|ctl_ir_we~15_combout ), + .datab(\z80_|execute_|ctl_mRead~4_combout ), + .datac(\z80_|execute_|ctl_ir_we~14_combout ), + .datad(\z80_|execute_|ctl_ir_we~7_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~22_combout ), + .combout(\z80_|execute_|fMWrite~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~22 .lut_mask = 16'hFAC8; -defparam \z80_|execute_|fMRead~22 .sum_lutc_input = "datac"; +defparam \z80_|execute_|fMWrite~1 .lut_mask = 16'h0001; +defparam \z80_|execute_|fMWrite~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y15_N2 -cycloneive_lcell_comb \z80_|execute_|fMRead~21 ( +// Location: LCCOMB_X24_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~1 ( // Equation(s): -// \z80_|execute_|fMRead~21_combout = (\z80_|execute_|ctl_state_alu~5_combout & (((\z80_|execute_|ctl_mRead~36_combout ) # (!\z80_|execute_|fMRead~4_combout )) # (!\z80_|execute_|fMRead~2_combout ))) +// \z80_|execute_|ctl_flags_bus~1_combout = ((\z80_|ir_|opcode [2]) # (\z80_|ir_|opcode [1])) # (!\z80_|execute_|ctl_mWrite~4_combout ) - .dataa(\z80_|execute_|fMRead~2_combout ), - .datab(\z80_|execute_|ctl_mRead~36_combout ), - .datac(\z80_|execute_|ctl_state_alu~5_combout ), - .datad(\z80_|execute_|fMRead~4_combout ), + .dataa(gnd), + .datab(\z80_|execute_|ctl_mWrite~4_combout ), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [1]), .cin(gnd), - .combout(\z80_|execute_|fMRead~21_combout ), + .combout(\z80_|execute_|ctl_flags_bus~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~21 .lut_mask = 16'hD0F0; -defparam \z80_|execute_|fMRead~21 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_flags_bus~1 .lut_mask = 16'hFFF3; +defparam \z80_|execute_|ctl_flags_bus~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y15_N10 -cycloneive_lcell_comb \z80_|execute_|fMRead~23 ( +// Location: LCCOMB_X25_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|fMRead~5 ( // Equation(s): -// \z80_|execute_|fMRead~23_combout = ((\z80_|execute_|pc_inc_hold~48_combout ) # ((\z80_|execute_|fMRead~22_combout ) # (\z80_|execute_|fMRead~21_combout ))) # (!\z80_|execute_|ctl_bus_db_oe~0_combout ) +// \z80_|execute_|fMRead~5_combout = (!\z80_|pla_decode_|Equal13~2_combout & (\z80_|execute_|ctl_flags_bus~1_combout & !\z80_|execute_|ctl_state_alu~6_combout )) - .dataa(\z80_|execute_|ctl_bus_db_oe~0_combout ), - .datab(\z80_|execute_|pc_inc_hold~48_combout ), - .datac(\z80_|execute_|fMRead~22_combout ), - .datad(\z80_|execute_|fMRead~21_combout ), + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(\z80_|execute_|ctl_flags_bus~1_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(gnd), .cin(gnd), - .combout(\z80_|execute_|fMRead~23_combout ), + .combout(\z80_|execute_|fMRead~5_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~23 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|fMRead~23 .sum_lutc_input = "datac"; +defparam \z80_|execute_|fMRead~5 .lut_mask = 16'h0404; +defparam \z80_|execute_|fMRead~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y12_N8 +// Location: LCCOMB_X25_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~17 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~17_combout = (\z80_|execute_|fMWrite~1_combout & (!\z80_|execute_|ctl_ir_we~12_combout & \z80_|execute_|fMRead~5_combout )) + + .dataa(\z80_|execute_|fMWrite~1_combout ), + .datab(\z80_|execute_|ctl_ir_we~12_combout ), + .datac(gnd), + .datad(\z80_|execute_|fMRead~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~17 .lut_mask = 16'h2200; +defparam \z80_|execute_|ctl_mRead~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_iorw~10 ( +// Equation(s): +// \z80_|execute_|ctl_iorw~10_combout = (!\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [1] & \z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_iorw~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_iorw~10 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_iorw~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|setM1~47 ( +// Equation(s): +// \z80_|execute_|setM1~47_combout = (!\z80_|execute_|ctl_iorw~11_combout & (!\z80_|execute_|ctl_mRead~11_combout & (\z80_|execute_|ctl_mRead~17_combout & !\z80_|execute_|ctl_iorw~10_combout ))) + + .dataa(\z80_|execute_|ctl_iorw~11_combout ), + .datab(\z80_|execute_|ctl_mRead~11_combout ), + .datac(\z80_|execute_|ctl_mRead~17_combout ), + .datad(\z80_|execute_|ctl_iorw~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~47 .lut_mask = 16'h0010; +defparam \z80_|execute_|setM1~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~8 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~8_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal6~0_combout & (!\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal55~0_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~8 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_mWrite~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~13 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~13_combout = ((\z80_|ir_|opcode [2]) # (!\z80_|ir_|opcode [1])) # (!\z80_|execute_|ctl_mWrite~4_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_mWrite~4_combout ), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~13 .lut_mask = 16'hF3FF; +defparam \z80_|execute_|ctl_al_we~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|setM1~48 ( +// Equation(s): +// \z80_|execute_|setM1~48_combout = (\z80_|execute_|setM1~47_combout & (!\z80_|execute_|ctl_mWrite~8_combout & \z80_|execute_|ctl_al_we~13_combout )) + + .dataa(\z80_|execute_|setM1~47_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_mWrite~8_combout ), + .datad(\z80_|execute_|ctl_al_we~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~48 .lut_mask = 16'h0A00; +defparam \z80_|execute_|setM1~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~0 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~0_combout = (\z80_|execute_|ctl_state_alu~3_combout & (((!\z80_|decode_state_|use_ixiy~combout & !\z80_|execute_|ctl_alu_oe~3_combout )) # (!\z80_|execute_|setM1~48_combout ))) + + .dataa(\z80_|decode_state_|use_ixiy~combout ), + .datab(\z80_|execute_|ctl_state_alu~3_combout ), + .datac(\z80_|execute_|ctl_alu_oe~3_combout ), + .datad(\z80_|execute_|setM1~48_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~0 .lut_mask = 16'h04CC; +defparam \z80_|execute_|ctl_sw_4d~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|pla_decode_|Equal48~0_combout & !\z80_|sequencer_|DFFE_M1_ff~q )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|pla_decode_|Equal48~0_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 .lut_mask = 16'h00C0; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~9 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~9_combout = (\z80_|sequencer_|DFFE_T5_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T5_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~9 .lut_mask = 16'h00F0; +defparam \z80_|execute_|ctl_mRead~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~3_combout = (\z80_|pla_decode_|Equal10~0_combout & (!\z80_|execute_|ixy_d~7_combout & ((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|pla_decode_|Equal21~1_combout )))) # (!\z80_|pla_decode_|Equal10~0_combout & +// (((!\z80_|execute_|ctl_mRead~9_combout )) # (!\z80_|pla_decode_|Equal21~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|execute_|ctl_mRead~9_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~3 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_flags_sz_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout = (\z80_|pla_decode_|Equal11~0_combout & (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M3_ff~q )) + + .dataa(gnd), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 .lut_mask = 16'h0C00; +defparam \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~9 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~9_combout = (((!\z80_|execute_|ixy_d~6_combout & !\z80_|nM1_int~2_combout )) # (!\z80_|execute_|ctl_mWrite~4_combout )) # (!\z80_|pla_decode_|Equal8~0_combout ) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|pla_decode_|Equal8~0_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_mWrite~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~9 .lut_mask = 16'h37FF; +defparam \z80_|execute_|ctl_flags_alu~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~2 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~2_combout = ((!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal39~0_combout & !\z80_|pla_decode_|Equal40~1_combout ))) # (!\z80_|execute_|ixy_d~8_combout ) + + .dataa(\z80_|execute_|ixy_d~8_combout ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|pla_decode_|Equal39~0_combout ), + .datad(\z80_|pla_decode_|Equal40~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~2 .lut_mask = 16'h5557; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~10_combout = (\z80_|execute_|ctl_flags_sz_we~3_combout & (!\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout & (\z80_|execute_|ctl_flags_alu~9_combout & \z80_|execute_|ctl_alu_sel_op2_neg~2_combout ))) + + .dataa(\z80_|execute_|ctl_flags_sz_we~3_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), + .datac(\z80_|execute_|ctl_flags_alu~9_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~10 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_flags_alu~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~10_combout = (((!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4])) # (!\z80_|nM1_int~2_combout )) # (!\z80_|pla_decode_|Equal63~0_combout ) + + .dataa(\z80_|pla_decode_|Equal63~0_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~10 .lut_mask = 16'h777F; +defparam \z80_|execute_|ctl_flags_xy_we~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla11M1T1_11 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|pla_decode_|Equal10~0_combout )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|pla_decode_|Equal10~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel_pla11M1T1_11 .lut_mask = 16'h0300; +defparam \z80_|execute_|ctl_pf_sel_pla11M1T1_11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~11 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~11_combout = (\z80_|execute_|ctl_flags_xy_we~10_combout & (!\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout & ((!\z80_|sequencer_|DFFE_T5_ff~q ) # (!\z80_|execute_|ixy_d~15_combout )))) + + .dataa(\z80_|execute_|ctl_flags_xy_we~10_combout ), + .datab(\z80_|execute_|ixy_d~15_combout ), + .datac(\z80_|sequencer_|DFFE_T5_ff~q ), + .datad(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~11 .lut_mask = 16'h002A; +defparam \z80_|execute_|ctl_flags_xy_we~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~11 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~11_combout = (\z80_|execute_|ctl_flags_alu~10_combout & (\z80_|execute_|ctl_flags_xy_we~11_combout & ((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|execute_|ixy_d~15_combout )))) + + .dataa(\z80_|execute_|ctl_flags_alu~10_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~11_combout ), + .datac(\z80_|execute_|ixy_d~15_combout ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~11 .lut_mask = 16'h0888; +defparam \z80_|execute_|ctl_flags_alu~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~1 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~1_combout = (\z80_|execute_|ctl_reg_use_sp~0_combout & \z80_|execute_|nextM~11_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_use_sp~0_combout ), + .datad(\z80_|execute_|nextM~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~1 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_reg_use_sp~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~4 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~4_combout = (\z80_|sequencer_|DFFE_M4_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~4 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_state_alu~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~9_combout = (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|pla_decode_|Equal10~0_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|pla_decode_|Equal10~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~9 .lut_mask = 16'h777F; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~4 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~4_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & (((!\z80_|execute_|ctl_state_alu~4_combout & !\z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|execute_|ctl_mRead~4_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|ctl_mRead~4_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~4 .lut_mask = 16'h3700; +defparam \z80_|execute_|ctl_sw_2d~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~0 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~0_combout = (\z80_|execute_|ctl_mWrite~9_combout & (((!\z80_|execute_|ctl_ir_we~12_combout & !\z80_|execute_|ctl_ir_we~11_combout )))) # (!\z80_|execute_|ctl_mWrite~9_combout & (((!\z80_|execute_|ctl_ir_we~12_combout )) +// # (!\z80_|execute_|ctl_mWrite~5_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~5_combout ), + .datab(\z80_|execute_|ctl_mWrite~9_combout ), + .datac(\z80_|execute_|ctl_ir_we~12_combout ), + .datad(\z80_|execute_|ctl_ir_we~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~0 .lut_mask = 16'h131F; +defparam \z80_|execute_|ctl_flags_sz_we~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~4_combout = (\z80_|execute_|ctl_flags_sz_we~0_combout & (((!\z80_|execute_|ctl_ir_we~12_combout & !\z80_|execute_|ctl_ir_we~11_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .datab(\z80_|execute_|ctl_ir_we~12_combout ), + .datac(\z80_|execute_|ctl_ir_we~11_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~4 .lut_mask = 16'h02AA; +defparam \z80_|execute_|ctl_flags_sz_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y16_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~47 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~47_combout = (\z80_|pla_decode_|Equal8~0_combout & (\z80_|execute_|ctl_mWrite~4_combout & (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_M3_ff~q ))) + + .dataa(\z80_|pla_decode_|Equal8~0_combout ), + .datab(\z80_|execute_|ctl_mWrite~4_combout ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~47 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_op_low~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~3 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~3_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout & (((!\z80_|pla_decode_|Equal21~1_combout & !\z80_|execute_|ctl_mRead~34_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal21~1_combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~3 .lut_mask = 16'h001F; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~12 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~12_combout = (!\z80_|execute_|ctl_alu_op_low~47_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~3_combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~47_combout ), + .datab(\z80_|pla_decode_|Equal20~0_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~12 .lut_mask = 16'h1050; +defparam \z80_|execute_|ctl_flags_alu~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~23 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~23_combout = (((!\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [3])) # (!\z80_|pla_decode_|Equal63~0_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|pla_decode_|Equal63~0_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~23 .lut_mask = 16'h5F7F; +defparam \z80_|execute_|ctl_alu_op_low~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~19 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~19_combout = (\z80_|execute_|ctl_alu_op_low~23_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|pla_decode_|Equal20~0_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|execute_|ctl_alu_op_low~23_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|pla_decode_|Equal20~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~19 .lut_mask = 16'hC4CC; +defparam \z80_|execute_|ctl_flags_xy_we~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~13 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~13_combout = (\z80_|execute_|ctl_sw_2d~4_combout & (\z80_|execute_|ctl_flags_sz_we~4_combout & (\z80_|execute_|ctl_flags_alu~12_combout & \z80_|execute_|ctl_flags_xy_we~19_combout ))) + + .dataa(\z80_|execute_|ctl_sw_2d~4_combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~4_combout ), + .datac(\z80_|execute_|ctl_flags_alu~12_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~13 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_flags_alu~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_hi~4_combout = ((!\z80_|pla_decode_|Equal40~1_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal39~0_combout ))) # (!\z80_|execute_|ixy_d~9_combout ) + + .dataa(\z80_|pla_decode_|Equal40~1_combout ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|pla_decode_|Equal39~0_combout ), + .datad(\z80_|execute_|ixy_d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_hi~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_hi~4 .lut_mask = 16'h01FF; +defparam \z80_|execute_|ctl_reg_out_hi~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~1 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~1_combout = (\z80_|execute_|ctl_reg_out_hi~4_combout & \z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_out_hi~4_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~1 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_sw_4u~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~29 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~29_combout = ((!\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|execute_|ixy_d~15_combout ) + + .dataa(\z80_|execute_|ixy_d~15_combout ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~29 .lut_mask = 16'h555F; +defparam \z80_|execute_|ctl_alu_op_low~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~14 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~14_combout = (\z80_|execute_|ctl_reg_use_sp~1_combout & (\z80_|execute_|ctl_flags_alu~13_combout & (\z80_|execute_|ctl_sw_4u~1_combout & \z80_|execute_|ctl_alu_op_low~29_combout ))) + + .dataa(\z80_|execute_|ctl_reg_use_sp~1_combout ), + .datab(\z80_|execute_|ctl_flags_alu~13_combout ), + .datac(\z80_|execute_|ctl_sw_4u~1_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~29_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~14 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_flags_alu~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout = (\z80_|pla_decode_|Equal63~0_combout & (\z80_|nM1_int~2_combout & (!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4]))) + + .dataa(\z80_|pla_decode_|Equal63~0_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 .lut_mask = 16'h0008; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla82M1T1_16 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout = (!\z80_|ir_|opcode [0] & (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal3~1_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|pla_decode_|Equal3~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel_pla82M1T1_16 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_pf_sel_pla82M1T1_16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~13 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~13_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|execute_|ctl_mRead~4_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|execute_|ctl_mRead~4_combout ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~13 .lut_mask = 16'h777F; +defparam \z80_|execute_|ctl_flags_use_cf2~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~7_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|pla_decode_|Equal13~0_combout ) # (!\z80_|pla_decode_|Equal55~0_combout ))) # (!\z80_|sequencer_|DFFE_M3_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~7 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_flags_cf_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel[0]~2 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel[0]~2_combout = (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (\z80_|execute_|ctl_flags_use_cf2~13_combout & \z80_|execute_|ctl_flags_cf_we~7_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .datac(\z80_|execute_|ctl_flags_use_cf2~13_combout ), + .datad(\z80_|execute_|ctl_flags_cf_we~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel[0]~2 .lut_mask = 16'h3000; +defparam \z80_|execute_|ctl_pf_sel[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_we~5_combout = (\z80_|execute_|ctl_bus_inc_oe~27_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|execute_|ctl_ir_we~8_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|execute_|ctl_bus_inc_oe~27_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_we~5 .lut_mask = 16'hFD00; +defparam \z80_|execute_|ctl_flags_hf_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~10_combout = (\z80_|execute_|ctl_flags_hf_we~5_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|pla_decode_|Equal13~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|execute_|ctl_flags_hf_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~10 .lut_mask = 16'hFD00; +defparam \z80_|execute_|ctl_flags_pf_we~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N8 +cycloneive_lcell_comb \z80_|pla_decode_|Equal68~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal68~2_combout = (\z80_|ir_|opcode [6] & (\z80_|decode_state_|DFFE_instED~q & (!\z80_|ir_|opcode [7] & !\z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|decode_state_|DFFE_instED~q ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal68~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal68~2 .lut_mask = 16'h0008; +defparam \z80_|pla_decode_|Equal68~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~13 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~13_combout = ((!\z80_|execute_|ctl_alu_op_low~27_combout & ((!\z80_|pla_decode_|Equal68~2_combout ) # (!\z80_|pla_decode_|Equal1~4_combout )))) # (!\z80_|nM1_int~2_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~27_combout ), + .datab(\z80_|pla_decode_|Equal1~4_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal68~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~13 .lut_mask = 16'h1F5F; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~2_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout & (\z80_|execute_|ctl_pf_sel[0]~2_combout & (\z80_|execute_|ctl_flags_pf_we~10_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~13_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .datab(\z80_|execute_|ctl_pf_sel[0]~2_combout ), + .datac(\z80_|execute_|ctl_flags_pf_we~10_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~2 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_flags_pf_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~4_combout = (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|execute_|ctl_mWrite~17_combout & ((!\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|ctl_mRead~9_combout )))) # (!\z80_|execute_|ctl_state_alu~2_combout & +// (((!\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|ctl_mRead~9_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ctl_mWrite~17_combout ), + .datac(\z80_|execute_|ctl_mRead~9_combout ), + .datad(\z80_|execute_|ctl_mRead~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~4 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_alu_oe~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y18_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~8_combout = (!\z80_|execute_|ctl_reg_gp_sel~7_combout & \z80_|execute_|setM1~18_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_sel~7_combout ), + .datab(gnd), + .datac(\z80_|execute_|setM1~18_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~8 .lut_mask = 16'h5050; +defparam \z80_|execute_|ctl_flags_xy_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y19_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~20 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~20_combout = (((!\z80_|pla_decode_|Equal13~0_combout ) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|pla_decode_|Equal55~0_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~20 .lut_mask = 16'h7FFF; +defparam \z80_|execute_|ctl_flags_xy_we~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~9 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~9_combout = (\z80_|execute_|ctl_flags_pf_we~2_combout & (\z80_|execute_|ctl_alu_oe~4_combout & (\z80_|execute_|ctl_flags_xy_we~8_combout & \z80_|execute_|ctl_flags_xy_we~20_combout ))) + + .dataa(\z80_|execute_|ctl_flags_pf_we~2_combout ), + .datab(\z80_|execute_|ctl_alu_oe~4_combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~8_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~9 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_flags_xy_we~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~1 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~1_combout = ((!\z80_|execute_|ctl_state_alu~5_combout & (!\z80_|execute_|ctl_state_alu~6_combout & !\z80_|pla_decode_|Equal52~1_combout ))) # (!\z80_|nM1_int~2_combout ) + + .dataa(\z80_|execute_|ctl_state_alu~5_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|pla_decode_|Equal52~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~1 .lut_mask = 16'h3337; +defparam \z80_|execute_|ctl_flags_sz_we~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~1 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~1_combout = (!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal39~0_combout & !\z80_|pla_decode_|Equal40~1_combout )) + + .dataa(gnd), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|pla_decode_|Equal39~0_combout ), + .datad(\z80_|pla_decode_|Equal40~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~1 .lut_mask = 16'h0003; +defparam \z80_|execute_|ctl_bus_db_oe~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~10_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ixy_d~15_combout & ((\z80_|execute_|ctl_bus_db_oe~1_combout ) # (!\z80_|sequencer_|DFFE_M3_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|execute_|ixy_d~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~10 .lut_mask = 16'hF0FD; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~2_combout = (\z80_|execute_|ctl_flags_xy_we~9_combout & (\z80_|execute_|ctl_flags_sz_we~1_combout & \z80_|execute_|ctl_alu_op2_sel_bus~10_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_flags_xy_we~9_combout ), + .datac(\z80_|execute_|ctl_flags_sz_we~1_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~2 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_flags_sz_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y17_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~17 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~17_combout = (((!\z80_|execute_|ctl_ir_we~14_combout & !\z80_|execute_|ctl_ir_we~8_combout )) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|execute_|ctl_ir_we~14_combout ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|execute_|ctl_ir_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~17 .lut_mask = 16'h5F7F; +defparam \z80_|execute_|ctl_flags_alu~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~18 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~18_combout = (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|execute_|ctl_ir_we~7_combout ), + .datad(\z80_|execute_|ctl_ir_we~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~18 .lut_mask = 16'h777F; +defparam \z80_|execute_|ctl_flags_alu~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~6_combout = (\z80_|execute_|ctl_flags_alu~18_combout & (((!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~9_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~15_combout ), + .datab(\z80_|execute_|ctl_flags_alu~18_combout ), + .datac(\z80_|execute_|ctl_ir_we~9_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~6 .lut_mask = 16'h04CC; +defparam \z80_|execute_|ctl_flags_alu~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~19 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~19_combout = (((!\z80_|execute_|ctl_ir_we~14_combout & !\z80_|execute_|ctl_mWrite~17_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|sequencer_|DFFE_T4_ff~q ) + + .dataa(\z80_|execute_|ctl_ir_we~14_combout ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|execute_|ctl_mWrite~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~19 .lut_mask = 16'h3F7F; +defparam \z80_|execute_|ctl_flags_alu~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N24 +cycloneive_lcell_comb \z80_|pla_decode_|Equal1~5 ( +// Equation(s): +// \z80_|pla_decode_|Equal1~5_combout = (!\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal1~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal1~5 .lut_mask = 16'h0F00; +defparam \z80_|pla_decode_|Equal1~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y19_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~0 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~0_combout = (\z80_|pla_decode_|Equal1~5_combout & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|pla_decode_|Equal13~1_combout & !\z80_|sequencer_|DFFE_M1_ff~q ))) + + .dataa(\z80_|pla_decode_|Equal1~5_combout ), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|pla_decode_|Equal13~1_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~0 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_alu_core_R~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|pla_decode_|Equal11~0_combout )) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2 .lut_mask = 16'h1010; +defparam \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~1 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~1_combout = (\z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ) # ((\z80_|execute_|ctl_alu_core_R~0_combout & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|execute_|ctl_alu_core_R~0_combout ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~1 .lut_mask = 16'hFAF2; +defparam \z80_|execute_|ctl_alu_core_R~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~7_combout = ((\z80_|execute_|ctl_alu_core_R~1_combout ) # ((\z80_|pla_decode_|Equal56~0_combout & \z80_|execute_|ixy_d~7_combout ))) # (!\z80_|execute_|ctl_flags_alu~19_combout ) + + .dataa(\z80_|execute_|ctl_flags_alu~19_combout ), + .datab(\z80_|pla_decode_|Equal56~0_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ctl_alu_core_R~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~7 .lut_mask = 16'hFFD5; +defparam \z80_|execute_|ctl_flags_alu~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N12 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~5 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~5_combout = ((!\z80_|pla_decode_|Equal39~0_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal40~1_combout ))) # (!\z80_|execute_|ixy_d~6_combout ) + + .dataa(\z80_|pla_decode_|Equal39~0_combout ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|pla_decode_|Equal40~1_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~5 .lut_mask = 16'h0F1F; +defparam \z80_|reg_control_|reg_sys_we_lo~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N28 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~8 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~8_combout = (\z80_|reg_control_|reg_sys_we_lo~5_combout & (((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|pla_decode_|Equal56~0_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|pla_decode_|Equal56~0_combout ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|reg_control_|reg_sys_we_lo~5_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~8 .lut_mask = 16'h7F00; +defparam \z80_|reg_control_|reg_sys_we_lo~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~8_combout = (((\z80_|execute_|ctl_flags_alu~7_combout ) # (!\z80_|reg_control_|reg_sys_we_lo~8_combout )) # (!\z80_|execute_|ctl_flags_alu~6_combout )) # (!\z80_|execute_|ctl_flags_alu~17_combout ) + + .dataa(\z80_|execute_|ctl_flags_alu~17_combout ), + .datab(\z80_|execute_|ctl_flags_alu~6_combout ), + .datac(\z80_|execute_|ctl_flags_alu~7_combout ), + .datad(\z80_|reg_control_|reg_sys_we_lo~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~8 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|ctl_flags_alu~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~15 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~15_combout = (((\z80_|execute_|ctl_flags_alu~8_combout ) # (!\z80_|execute_|ctl_flags_sz_we~2_combout )) # (!\z80_|execute_|ctl_flags_alu~14_combout )) # (!\z80_|execute_|ctl_flags_alu~11_combout ) + + .dataa(\z80_|execute_|ctl_flags_alu~11_combout ), + .datab(\z80_|execute_|ctl_flags_alu~14_combout ), + .datac(\z80_|execute_|ctl_flags_sz_we~2_combout ), + .datad(\z80_|execute_|ctl_flags_alu~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~15 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_flags_alu~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~7 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~7_combout = (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|execute_|ctl_state_alu~6_combout & ((!\z80_|pla_decode_|Equal52~1_combout )))) # (!\z80_|execute_|ctl_state_alu~2_combout & +// (((!\z80_|execute_|ctl_state_alu~4_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ctl_state_alu~6_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|pla_decode_|Equal52~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~7 .lut_mask = 16'h1537; +defparam \z80_|execute_|ctl_state_alu~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~12 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~12_combout = (\z80_|execute_|ctl_state_alu~7_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|pla_decode_|Equal52~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal52~1_combout ), + .datab(\z80_|execute_|ctl_state_alu~7_combout ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~12 .lut_mask = 16'hCC4C; +defparam \z80_|execute_|ctl_state_alu~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~9 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~9_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # ((\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~9 .lut_mask = 16'h00EF; +defparam \z80_|execute_|ctl_state_alu~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~10 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~10_combout = (\z80_|execute_|ctl_state_alu~9_combout & ((\z80_|execute_|ctl_state_alu~5_combout ) # ((\z80_|pla_decode_|Equal52~1_combout & \z80_|execute_|ctl_state_alu~3_combout )))) # +// (!\z80_|execute_|ctl_state_alu~9_combout & (((\z80_|pla_decode_|Equal52~1_combout & \z80_|execute_|ctl_state_alu~3_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~9_combout ), + .datab(\z80_|execute_|ctl_state_alu~5_combout ), + .datac(\z80_|pla_decode_|Equal52~1_combout ), + .datad(\z80_|execute_|ctl_state_alu~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~10 .lut_mask = 16'hF888; +defparam \z80_|execute_|ctl_state_alu~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~8 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~8_combout = (\z80_|pla_decode_|Equal52~1_combout & (((\z80_|nM1_int~2_combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) # (!\z80_|pla_decode_|Equal52~1_combout & (\z80_|execute_|ctl_state_alu~6_combout & +// ((\z80_|nM1_int~2_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) + + .dataa(\z80_|pla_decode_|Equal52~1_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~8 .lut_mask = 16'hFA32; +defparam \z80_|execute_|ctl_state_alu~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal64~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal64~0_combout = (!\z80_|ir_|opcode [5] & (((\z80_|execute_|ctl_state_alu~10_combout ) # (\z80_|execute_|ctl_state_alu~8_combout )) # (!\z80_|execute_|ctl_state_alu~12_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|execute_|ctl_state_alu~12_combout ), + .datac(\z80_|execute_|ctl_state_alu~10_combout ), + .datad(\z80_|execute_|ctl_state_alu~8_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal64~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal64~0 .lut_mask = 16'h5551; +defparam \z80_|pla_decode_|Equal64~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel[0]~3 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel[0]~3_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # (\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|pla_decode_|Equal64~0_combout ) + + .dataa(\z80_|pla_decode_|Equal64~0_combout ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel[0]~3 .lut_mask = 16'hFDFD; +defparam \z80_|execute_|ctl_pf_sel[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N22 +cycloneive_lcell_comb \z80_|pla_decode_|Equal62~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal62~2_combout = (\z80_|ir_|opcode [5] & (((\z80_|execute_|ctl_state_alu~10_combout ) # (\z80_|execute_|ctl_state_alu~8_combout )) # (!\z80_|execute_|ctl_state_alu~12_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|execute_|ctl_state_alu~12_combout ), + .datac(\z80_|execute_|ctl_state_alu~10_combout ), + .datad(\z80_|execute_|ctl_state_alu~8_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal62~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal62~2 .lut_mask = 16'hAAA2; +defparam \z80_|pla_decode_|Equal62~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~4_combout = (((\z80_|ir_|opcode [3] & \z80_|ir_|opcode [4])) # (!\z80_|nM1_int~2_combout )) # (!\z80_|pla_decode_|Equal62~2_combout ) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|pla_decode_|Equal62~2_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~4 .lut_mask = 16'h8FFF; +defparam \z80_|execute_|ctl_flags_pf_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~46 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~46_combout = (\z80_|execute_|ctl_alu_shift_oe~41_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|pla_decode_|Equal48~0_combout )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|pla_decode_|Equal48~0_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~41_combout ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~46 .lut_mask = 16'hB0F0; +defparam \z80_|execute_|ctl_alu_shift_oe~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~6_combout = (\z80_|pla_decode_|Equal69~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|pla_decode_|Equal69~0_combout ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~6 .lut_mask = 16'h080A; +defparam \z80_|execute_|ctl_flags_pf_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~7_combout = (\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # ((\z80_|execute_|ctl_flags_pf_we~6_combout ) # ((\z80_|execute_|ctl_mRead~34_combout & \z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~34_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .datad(\z80_|execute_|ctl_flags_pf_we~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~7 .lut_mask = 16'hFFF8; +defparam \z80_|execute_|ctl_flags_pf_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~11 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~11_combout = ((\z80_|execute_|ctl_state_alu~10_combout ) # ((\z80_|execute_|ctl_reg_gp_sel~7_combout ) # (\z80_|execute_|ctl_state_alu~8_combout ))) # (!\z80_|execute_|ctl_state_alu~7_combout ) + + .dataa(\z80_|execute_|ctl_state_alu~7_combout ), + .datab(\z80_|execute_|ctl_state_alu~10_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel~7_combout ), + .datad(\z80_|execute_|ctl_state_alu~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~11 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_state_alu~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y17_N26 +cycloneive_lcell_comb \z80_|pla_decode_|Equal62~3 ( +// Equation(s): +// \z80_|pla_decode_|Equal62~3_combout = (\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [4] & (\z80_|execute_|ctl_state_alu~11_combout & \z80_|ir_|opcode [3]))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|execute_|ctl_state_alu~11_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal62~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal62~3 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal62~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~5_combout = (\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_mWrite~17_combout ) # ((\z80_|pla_decode_|Equal11~0_combout ) # (\z80_|pla_decode_|Equal62~3_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~17_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|pla_decode_|Equal62~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~5 .lut_mask = 16'hCCC8; +defparam \z80_|execute_|ctl_flags_pf_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~3_combout = (\z80_|execute_|ctl_flags_pf_we~2_combout & (((!\z80_|execute_|ctl_ir_we~12_combout & !\z80_|execute_|ctl_ir_we~11_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_ir_we~12_combout ), + .datac(\z80_|execute_|ctl_flags_pf_we~2_combout ), + .datad(\z80_|execute_|ctl_ir_we~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~3 .lut_mask = 16'h5070; +defparam \z80_|execute_|ctl_flags_pf_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~8_combout = ((\z80_|execute_|ctl_flags_pf_we~7_combout ) # ((\z80_|execute_|ctl_flags_pf_we~5_combout ) # (!\z80_|execute_|ctl_flags_pf_we~3_combout ))) # (!\z80_|execute_|ctl_alu_shift_oe~46_combout ) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~46_combout ), + .datab(\z80_|execute_|ctl_flags_pf_we~7_combout ), + .datac(\z80_|execute_|ctl_flags_pf_we~5_combout ), + .datad(\z80_|execute_|ctl_flags_pf_we~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~8 .lut_mask = 16'hFDFF; +defparam \z80_|execute_|ctl_flags_pf_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~9 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~9_combout = (((\z80_|execute_|ctl_flags_pf_we~8_combout ) # (!\z80_|execute_|ctl_flags_pf_we~4_combout )) # (!\z80_|execute_|ctl_pf_sel[0]~3_combout )) # (!\z80_|execute_|ctl_flags_xy_we~13_combout ) + + .dataa(\z80_|execute_|ctl_flags_xy_we~13_combout ), + .datab(\z80_|execute_|ctl_pf_sel[0]~3_combout ), + .datac(\z80_|execute_|ctl_flags_pf_we~4_combout ), + .datad(\z80_|execute_|ctl_flags_pf_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~9 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_flags_pf_we~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y20_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~6_combout = (\z80_|execute_|ctl_ir_we~15_combout & (!\z80_|execute_|ctl_mWrite~5_combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|execute_|ctl_ir_we~9_combout )))) # (!\z80_|execute_|ctl_ir_we~15_combout & +// (((!\z80_|nM1_int~2_combout ) # (!\z80_|execute_|ctl_ir_we~9_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~15_combout ), + .datab(\z80_|execute_|ctl_mWrite~5_combout ), + .datac(\z80_|execute_|ctl_ir_we~9_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~6 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_alu_core_S~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y20_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~7_combout = (\z80_|execute_|ctl_alu_core_S~6_combout & (((!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~9_combout )) # (!\z80_|execute_|ctl_alu_oe~0_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~15_combout ), + .datab(\z80_|execute_|ctl_alu_oe~0_combout ), + .datac(\z80_|execute_|ctl_ir_we~9_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~7 .lut_mask = 16'h3700; +defparam \z80_|execute_|ctl_alu_core_S~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~1 ( +// Equation(s): +// \z80_|execute_|ctl_alu_res_oe~1_combout = (\z80_|execute_|ctl_alu_core_S~7_combout & (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|pla_decode_|Equal69~0_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|pla_decode_|Equal69~0_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_res_oe~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_res_oe~1 .lut_mask = 16'h5700; +defparam \z80_|execute_|ctl_alu_res_oe~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_alu_res_oe~0_combout = (\z80_|pla_decode_|Equal8~0_combout & ((\z80_|execute_|ctl_mRead~9_combout ) # ((\z80_|nM1_int~2_combout & \z80_|pla_decode_|Equal55~0_combout )))) # (!\z80_|pla_decode_|Equal8~0_combout & +// (((\z80_|nM1_int~2_combout & \z80_|pla_decode_|Equal55~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal8~0_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_res_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_res_oe~0 .lut_mask = 16'hF888; +defparam \z80_|execute_|ctl_alu_res_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y20_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~4_combout = (\z80_|execute_|ctl_ir_we~7_combout & (!\z80_|execute_|ctl_mWrite~5_combout & ((!\z80_|execute_|ctl_ir_we~10_combout ) # (!\z80_|nM1_int~2_combout )))) # (!\z80_|execute_|ctl_ir_we~7_combout & +// (((!\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~7_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|execute_|ctl_mWrite~5_combout ), + .datad(\z80_|execute_|ctl_ir_we~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~4 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_alu_core_S~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y20_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~5_combout = (\z80_|execute_|ctl_alu_core_S~4_combout & (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|execute_|ctl_alu_oe~0_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~7_combout ), + .datab(\z80_|execute_|ctl_ir_we~10_combout ), + .datac(\z80_|execute_|ctl_alu_oe~0_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~5 .lut_mask = 16'h1F00; +defparam \z80_|execute_|ctl_alu_core_S~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~2 ( +// Equation(s): +// \z80_|execute_|ctl_alu_res_oe~2_combout = (\z80_|execute_|ctl_alu_res_oe~1_combout & (\z80_|execute_|ctl_alu_core_S~5_combout & ((!\z80_|execute_|ctl_mWrite~4_combout ) # (!\z80_|execute_|ctl_alu_res_oe~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_res_oe~1_combout ), + .datab(\z80_|execute_|ctl_alu_res_oe~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_res_oe~2 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_alu_res_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y17_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout = (\z80_|pla_decode_|Equal2~0_combout & (\z80_|execute_|ctl_mWrite~4_combout & (!\z80_|ir_|opcode [0] & \z80_|execute_|ctl_state_alu~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal2~0_combout ), + .datab(\z80_|execute_|ctl_mWrite~4_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|execute_|ctl_state_alu~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N18 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~6 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~6_combout = (\z80_|reg_control_|reg_sys_we_lo~5_combout & (\z80_|execute_|ctl_flags_xy_we~20_combout & ((!\z80_|pla_decode_|Equal56~0_combout ) # (!\z80_|execute_|ctl_alu_op_low~22_combout )))) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~5_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datac(\z80_|pla_decode_|Equal56~0_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~20_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~6 .lut_mask = 16'h2A00; +defparam \z80_|reg_control_|reg_sys_we_lo~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~12 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~12_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|pla_decode_|Equal56~0_combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) # (!\z80_|execute_|ixy_d~7_combout & +// (((!\z80_|nM1_int~2_combout )) # (!\z80_|pla_decode_|Equal20~0_combout ))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|pla_decode_|Equal20~0_combout ), + .datac(\z80_|pla_decode_|Equal56~0_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~12 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_flags_xy_we~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~2_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout & (\z80_|reg_control_|reg_sys_we_lo~6_combout & (\z80_|execute_|ctl_flags_sz_we~1_combout & \z80_|execute_|ctl_flags_xy_we~12_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), + .datab(\z80_|reg_control_|reg_sys_we_lo~6_combout ), + .datac(\z80_|execute_|ctl_flags_sz_we~1_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~2 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_flags_cf_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~3 ( +// Equation(s): +// \z80_|execute_|ctl_alu_res_oe~3_combout = (\z80_|execute_|ctl_flags_alu~11_combout & (\z80_|execute_|ctl_alu_res_oe~2_combout & (\z80_|execute_|ctl_flags_cf_we~2_combout & \z80_|execute_|ctl_flags_pf_we~3_combout ))) + + .dataa(\z80_|execute_|ctl_flags_alu~11_combout ), + .datab(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datac(\z80_|execute_|ctl_flags_cf_we~2_combout ), + .datad(\z80_|execute_|ctl_flags_pf_we~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_res_oe~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_res_oe~3 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_res_oe~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_high ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_high~combout = ((\z80_|pla_decode_|Equal13~2_combout & (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_M3_ff~q ))) # (!\z80_|execute_|ctl_alu_res_oe~3_combout ) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|execute_|ctl_alu_res_oe~3_combout ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_high .lut_mask = 16'h8F0F; +defparam \z80_|execute_|ctl_alu_sel_op2_high .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_zero~4_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|ir_|opcode [0]))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|pla_decode_|Equal3~1_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_zero~4 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_alu_op1_sel_zero~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~12_combout = ((!\z80_|pla_decode_|Equal3~0_combout & ((\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal21~0_combout )))) # (!\z80_|execute_|ctl_state_alu~11_combout ) + + .dataa(\z80_|pla_decode_|Equal3~0_combout ), + .datab(\z80_|pla_decode_|Equal21~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|execute_|ctl_state_alu~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~12 .lut_mask = 16'h51FF; +defparam \z80_|execute_|ctl_alu_core_hf~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y16_N10 +cycloneive_lcell_comb \z80_|pla_decode_|Equal61~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal61~2_combout = (\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal6~0_combout & (!\z80_|ir_|opcode [1] & \z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal61~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal61~2 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal61~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~4_combout = (((!\z80_|execute_|ctl_eval_cond~0_combout & !\z80_|nM1_int~2_combout )) # (!\z80_|pla_decode_|Equal32~0_combout )) # (!\z80_|pla_decode_|Equal63~0_combout ) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|pla_decode_|Equal63~0_combout ), + .datad(\z80_|pla_decode_|Equal32~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~4 .lut_mask = 16'h1FFF; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~13 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~13_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~4_combout & (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|pla_decode_|Equal61~2_combout ))) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|pla_decode_|Equal61~2_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~13 .lut_mask = 16'h3070; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y20_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~14 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~14_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~4_combout & (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (\z80_|execute_|ctl_alu_core_hf~12_combout & \z80_|execute_|ctl_alu_sel_op2_neg~13_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .datab(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~12_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~14 .lut_mask = 16'h1000; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~18 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~18_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~14_combout & (((!\z80_|execute_|ctl_mWrite~17_combout ) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|execute_|ctl_mWrite~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~18 .lut_mask = 16'h2AAA; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~10_combout = (\z80_|execute_|ctl_flags_bus~9_combout & (\z80_|execute_|ctl_alu_shift_oe~20_combout & \z80_|execute_|ctl_bus_db_oe~3_combout )) + + .dataa(\z80_|execute_|ctl_flags_bus~9_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~20_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~3_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~10 .lut_mask = 16'h8080; +defparam \z80_|execute_|ctl_flags_bus~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~2_combout = (\z80_|pla_decode_|Equal44~0_combout ) # ((\z80_|pla_decode_|Equal52~0_combout & \z80_|pla_decode_|Equal33~0_combout )) + + .dataa(gnd), + .datab(\z80_|pla_decode_|Equal44~0_combout ), + .datac(\z80_|pla_decode_|Equal52~0_combout ), + .datad(\z80_|pla_decode_|Equal33~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~2 .lut_mask = 16'hFCCC; +defparam \z80_|execute_|ctl_flags_bus~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y17_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~0 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~0_combout = (\z80_|ir_|opcode [5]) # ((!\z80_|pla_decode_|Equal13~1_combout ) # (!\z80_|pla_decode_|Equal13~0_combout )) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal13~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~0 .lut_mask = 16'hBBFF; +defparam \z80_|execute_|ctl_flags_bus~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~3_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|execute_|ctl_flags_bus~2_combout ) # ((!\z80_|execute_|ctl_flags_bus~0_combout ) # (!\z80_|execute_|ctl_flags_bus~1_combout )))) + + .dataa(\z80_|execute_|ctl_flags_bus~2_combout ), + .datab(\z80_|execute_|ctl_flags_bus~1_combout ), + .datac(\z80_|execute_|ctl_flags_bus~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~3 .lut_mask = 16'hBF00; +defparam \z80_|execute_|ctl_flags_bus~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N10 cycloneive_lcell_comb \z80_|execute_|fMRead~26 ( // Equation(s): -// \z80_|execute_|fMRead~26_combout = (\z80_|execute_|ctl_mRead~15_combout ) # ((\z80_|pla_decode_|Equal44~0_combout & (\z80_|pla_decode_|Equal33~0_combout & !\z80_|decode_state_|use_ixiy~combout ))) +// \z80_|execute_|fMRead~26_combout = (\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_state_alu~2_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_state_alu~6_combout )))) # (!\z80_|execute_|ctl_ir_we~12_combout +// & (((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_state_alu~6_combout )))) - .dataa(\z80_|pla_decode_|Equal44~0_combout ), - .datab(\z80_|execute_|ctl_mRead~15_combout ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|decode_state_|use_ixiy~combout ), + .dataa(\z80_|execute_|ctl_ir_we~12_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), .cin(gnd), .combout(\z80_|execute_|fMRead~26_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~26 .lut_mask = 16'hCCEC; +defparam \z80_|execute_|fMRead~26 .lut_mask = 16'h0777; defparam \z80_|execute_|fMRead~26 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y19_N20 -cycloneive_lcell_comb \z80_|execute_|fMRead~25 ( +// Location: LCCOMB_X29_Y19_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus ( // Equation(s): -// \z80_|execute_|fMRead~25_combout = ((\z80_|sequencer_|DFFE_M2_ff~q & (!\z80_|execute_|ixy_d~4_combout & \z80_|execute_|ctl_mRead~14_combout ))) # (!\z80_|execute_|fMRead~24_combout ) +// \z80_|execute_|ctl_flags_bus~combout = ((\z80_|execute_|ctl_flags_bus~3_combout ) # ((\z80_|execute_|ctl_flags_hf2_we~combout ) # (!\z80_|execute_|fMRead~26_combout ))) # (!\z80_|execute_|ctl_flags_bus~10_combout ) - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|execute_|ixy_d~4_combout ), - .datac(\z80_|execute_|fMRead~24_combout ), - .datad(\z80_|execute_|ctl_mRead~14_combout ), + .dataa(\z80_|execute_|ctl_flags_bus~10_combout ), + .datab(\z80_|execute_|ctl_flags_bus~3_combout ), + .datac(\z80_|execute_|ctl_flags_hf2_we~combout ), + .datad(\z80_|execute_|fMRead~26_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~25_combout ), + .combout(\z80_|execute_|ctl_flags_bus~combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~25 .lut_mask = 16'h2F0F; -defparam \z80_|execute_|fMRead~25 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_flags_bus .lut_mask = 16'hFDFF; +defparam \z80_|execute_|ctl_flags_bus .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|fMRead~27 ( +// Location: LCCOMB_X26_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_lo~9 ( // Equation(s): -// \z80_|execute_|fMRead~27_combout = ((\z80_|execute_|fMRead~25_combout ) # ((\z80_|execute_|fMRead~26_combout & \z80_|execute_|ctl_ir_we~4_combout ))) # (!\z80_|execute_|fMRead~3_combout ) +// \z80_|execute_|ctl_reg_in_lo~9_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q ))) # (!\z80_|pla_decode_|Equal47~0_combout ) - .dataa(\z80_|execute_|fMRead~26_combout ), - .datab(\z80_|execute_|fMRead~3_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|execute_|fMRead~25_combout ), + .dataa(\z80_|pla_decode_|Equal47~0_combout ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|M5~q ), .cin(gnd), - .combout(\z80_|execute_|fMRead~27_combout ), + .combout(\z80_|execute_|ctl_reg_in_lo~9_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~27 .lut_mask = 16'hFFB3; -defparam \z80_|execute_|fMRead~27 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_reg_in_lo~9 .lut_mask = 16'hF5F7; +defparam \z80_|execute_|ctl_reg_in_lo~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y17_N18 -cycloneive_lcell_comb \z80_|execute_|fMRead~33 ( +// Location: LCCOMB_X30_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_oe~0 ( // Equation(s): -// \z80_|execute_|fMRead~33_combout = (\z80_|execute_|fMRead~32_combout ) # ((\z80_|execute_|fMRead~20_combout ) # ((\z80_|execute_|fMRead~23_combout ) # (\z80_|execute_|fMRead~27_combout ))) +// \z80_|execute_|ctl_alu_op1_oe~0_combout = ((\z80_|execute_|ctl_66_oe~2_combout ) # ((\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_alu_shift_oe~14_combout ))) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ) - .dataa(\z80_|execute_|fMRead~32_combout ), - .datab(\z80_|execute_|fMRead~20_combout ), - .datac(\z80_|execute_|fMRead~23_combout ), - .datad(\z80_|execute_|fMRead~27_combout ), + .dataa(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .datab(\z80_|execute_|ctl_66_oe~2_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~33_combout ), + .combout(\z80_|execute_|ctl_alu_op1_oe~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~33 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|fMRead~33 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_alu_op1_oe~0 .lut_mask = 16'hFDDD; +defparam \z80_|execute_|ctl_alu_op1_oe~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y17_N8 -cycloneive_lcell_comb \z80_|execute_|fMRead~35 ( +// Location: LCCOMB_X30_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_oe~1 ( // Equation(s): -// \z80_|execute_|fMRead~35_combout = (\z80_|execute_|fMRead~33_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~20_combout ) # ((\z80_|execute_|fMRead~34_combout & !\z80_|execute_|fMRead~0_combout ))) +// \z80_|execute_|ctl_alu_op1_oe~1_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ) # ((\z80_|execute_|ctl_alu_op1_oe~0_combout ) # ((\z80_|nM1_int~2_combout & \z80_|execute_|ctl_alu_oe~1_combout ))) - .dataa(\z80_|execute_|fMRead~34_combout ), - .datab(\z80_|execute_|fMRead~33_combout ), - .datac(\z80_|execute_|fMRead~0_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~20_combout ), + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_alu_oe~1_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), + .datad(\z80_|execute_|ctl_alu_op1_oe~0_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~35_combout ), + .combout(\z80_|execute_|ctl_alu_op1_oe~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~35 .lut_mask = 16'hFFCE; -defparam \z80_|execute_|fMRead~35 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_alu_op1_oe~1 .lut_mask = 16'hFFF8; +defparam \z80_|execute_|ctl_alu_op1_oe~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y13_N30 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_re ( +// Location: LCCOMB_X23_Y19_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~6 ( // Equation(s): -// \z80_|pin_control_|bus_db_pin_re~combout = (\z80_|pin_control_|bus_db_pin_re~2_combout ) # ((\z80_|execute_|fMRead~35_combout & \z80_|sequencer_|DFFE_T2_ff~q )) +// \z80_|execute_|ctl_alu_bs_oe~6_combout = ((!\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~15_combout ))) # (!\z80_|execute_|ctl_ir_we~4_combout ) + + .dataa(\z80_|execute_|ctl_ir_we~12_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ctl_ir_we~9_combout ), + .datad(\z80_|execute_|ctl_ir_we~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~6 .lut_mask = 16'h3337; +defparam \z80_|execute_|ctl_alu_bs_oe~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~12_combout = (\z80_|execute_|ctl_ir_we~11_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # ((!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M4_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|execute_|ctl_ir_we~11_combout ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~12 .lut_mask = 16'hCC40; +defparam \z80_|execute_|ctl_alu_bs_oe~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~8_combout = ((\z80_|execute_|ctl_alu_bs_oe~12_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~7_combout )) # (!\z80_|execute_|ctl_alu_bs_oe~6_combout ) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~6_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_bs_oe~12_combout ), + .datad(\z80_|execute_|ctl_alu_bs_oe~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~8 .lut_mask = 16'hF5FF; +defparam \z80_|execute_|ctl_alu_bs_oe~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~9_combout = (\z80_|execute_|ctl_ir_we~7_combout & (((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # (\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|execute_|ctl_ir_we~7_combout & (\z80_|execute_|ctl_ir_we~10_combout +// & ((\z80_|execute_|ctl_ir_we~4_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~10_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_ir_we~7_combout ), + .datad(\z80_|execute_|ctl_ir_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~9 .lut_mask = 16'hFAC0; +defparam \z80_|execute_|ctl_alu_bs_oe~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~combout = (\z80_|execute_|ctl_alu_bs_oe~8_combout ) # ((\z80_|execute_|ctl_alu_bs_oe~9_combout ) # ((\z80_|execute_|ctl_ir_we~4_combout & \z80_|pla_decode_|Equal41~2_combout ))) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~8_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(\z80_|execute_|ctl_alu_bs_oe~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe .lut_mask = 16'hFFEA; +defparam \z80_|execute_|ctl_alu_bs_oe .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_oe~0_combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # ((!\z80_|ir_|opcode [3] & \z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_oe~0 .lut_mask = 16'hB0A0; +defparam \z80_|execute_|ctl_alu_op2_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N12 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~0 ( +// Equation(s): +// \z80_|alu_|db_high[3]~0_combout = (\z80_|execute_|ctl_alu_op1_oe~1_combout ) # ((\z80_|execute_|ctl_alu_bs_oe~combout ) # ((\z80_|execute_|ctl_alu_op2_oe~0_combout ) # (!\z80_|execute_|ctl_alu_res_oe~3_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datab(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datac(\z80_|execute_|ctl_alu_res_oe~3_combout ), + .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~0 .lut_mask = 16'hFFEF; +defparam \z80_|alu_|db_high[3]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y19_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla83M1T3_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla83M1T3_2~combout = (\z80_|pla_decode_|Equal1~5_combout & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|pla_decode_|Equal13~1_combout & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal1~5_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|pla_decode_|Equal13~1_combout ), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla83M1T3_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla83M1T3_2 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla83M1T3_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~15 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~15_combout = (!\z80_|pla_decode_|Equal33~1_combout & (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal3~1_combout & \z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~1_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|pla_decode_|Equal3~1_combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~15 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_alu_shift_oe~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~38 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~38_combout = (!\z80_|execute_|ctl_alu_shift_oe~15_combout & (((!\z80_|execute_|ctl_state_alu~4_combout & !\z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|execute_|ctl_mRead~4_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|ctl_mRead~4_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~38 .lut_mask = 16'h0037; +defparam \z80_|execute_|ctl_alu_shift_oe~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y19_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~28 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~28_combout = (\z80_|pla_decode_|Equal1~5_combout & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|pla_decode_|Equal13~1_combout & \z80_|execute_|ctl_eval_cond~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal1~5_combout ), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|pla_decode_|Equal13~1_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~28 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_op_low~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y19_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~6_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla83M1T3_2~combout & (!\z80_|execute_|ctl_alu_op1_sel_bus~16_combout & (\z80_|execute_|ctl_alu_shift_oe~38_combout & !\z80_|execute_|ctl_alu_op_low~28_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla83M1T3_2~combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~38_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~28_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~6 .lut_mask = 16'h0010; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~37 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~37_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_alu_oe~1_combout ) # ((!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & \z80_|execute_|ctl_ir_we~11_combout )))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_ir_we~11_combout ), + .datad(\z80_|execute_|ctl_alu_oe~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~37 .lut_mask = 16'hAA20; +defparam \z80_|execute_|ctl_alu_shift_oe~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~39 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~39_combout = ((\z80_|execute_|ctl_alu_shift_oe~37_combout ) # ((\z80_|execute_|ctl_state_alu~6_combout & \z80_|execute_|ctl_alu_shift_oe~14_combout ))) # (!\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ) + + .dataa(\z80_|execute_|ctl_state_alu~6_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~37_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~39 .lut_mask = 16'hFBF3; +defparam \z80_|execute_|ctl_alu_shift_oe~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_daa ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_sel_daa~combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal63~0_combout & (!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4]))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_sel_daa .lut_mask = 16'h0008; +defparam \z80_|execute_|ctl_flags_cf2_sel_daa .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y17_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~7_combout = (\z80_|execute_|ctl_ir_we~8_combout & (!\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ctl_mWrite~5_combout ) # (!\z80_|execute_|ctl_ir_we~14_combout )))) # (!\z80_|execute_|ctl_ir_we~8_combout +// & (((!\z80_|execute_|ctl_mWrite~5_combout )) # (!\z80_|execute_|ctl_ir_we~14_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|execute_|ctl_ir_we~14_combout ), + .datac(\z80_|execute_|ctl_mWrite~5_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~7 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y17_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~8_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~7_combout & (\z80_|execute_|ctl_flags_alu~17_combout & ((!\z80_|pla_decode_|Equal20~0_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|pla_decode_|Equal20~0_combout ), + .datad(\z80_|execute_|ctl_flags_alu~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~8 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~30 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~30_combout = ((!\z80_|execute_|ixy_d~7_combout & ((\z80_|ir_|opcode [3]) # (!\z80_|execute_|ixy_d~6_combout )))) # (!\z80_|pla_decode_|Equal13~2_combout ) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~30 .lut_mask = 16'h7757; +defparam \z80_|execute_|ctl_alu_op_low~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y18_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~31 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~31_combout = (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (\z80_|execute_|ctl_alu_op1_sel_bus~8_combout & \z80_|execute_|ctl_alu_op_low~30_combout )) .dataa(gnd), - .datab(\z80_|execute_|fMRead~35_combout ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|pin_control_|bus_db_pin_re~2_combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~30_combout ), .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_re~combout ), + .combout(\z80_|execute_|ctl_alu_op_low~31_combout ), .cout()); // synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_re .lut_mask = 16'hFFC0; -defparam \z80_|pin_control_|bus_db_pin_re .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_alu_op_low~31 .lut_mask = 16'h3000; +defparam \z80_|execute_|ctl_alu_op_low~31 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X33_Y15_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a1 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[1]~34_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), +// Location: LCCOMB_X27_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~25 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~25_combout = (\z80_|pla_decode_|Equal13~2_combout & \z80_|ir_|opcode [3]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~25 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_mRead~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~40 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~40_combout = ((\z80_|execute_|ixy_d~9_combout & ((\z80_|execute_|ctl_mRead~25_combout ) # (\z80_|execute_|ctl_mRead~24_combout )))) # (!\z80_|execute_|ctl_flags_xy_we~21_combout ) + + .dataa(\z80_|execute_|ctl_mRead~25_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~21_combout ), + .datac(\z80_|execute_|ixy_d~9_combout ), + .datad(\z80_|execute_|ctl_mRead~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~40 .lut_mask = 16'hF3B3; +defparam \z80_|execute_|ctl_alu_shift_oe~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~42 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~42_combout = ((\z80_|execute_|ctl_alu_shift_oe~39_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~40_combout ) # (!\z80_|execute_|ctl_alu_op_low~31_combout ))) # (!\z80_|execute_|ctl_alu_shift_oe~46_combout ) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~46_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~39_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~31_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~40_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~42 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|ctl_alu_shift_oe~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout = (!\z80_|pla_decode_|Equal33~0_combout & (\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|pla_decode_|Equal44~0_combout & !\z80_|sequencer_|DFFE_M1_ff~q ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|pla_decode_|Equal44~0_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 .lut_mask = 16'h0040; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y18_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~4_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & (\z80_|execute_|ctl_state_alu~7_combout & (!\z80_|execute_|ctl_reg_gp_sel~7_combout & !\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ))) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), + .datab(\z80_|execute_|ctl_state_alu~7_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel~7_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~4 .lut_mask = 16'h0008; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~47 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~47_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|execute_|ctl_ir_we~7_combout & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_M1_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|execute_|ctl_ir_we~7_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~47 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_shift_oe~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~34 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~34_combout = (\z80_|execute_|ctl_ir_we~10_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ctl_alu_shift_oe~47_combout )))) # +// (!\z80_|execute_|ctl_ir_we~10_combout & (((\z80_|execute_|ctl_alu_shift_oe~47_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~10_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~47_combout ), + .datad(\z80_|execute_|ctl_ir_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~34 .lut_mask = 16'h50F8; +defparam \z80_|execute_|ctl_alu_shift_oe~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~35 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~35_combout = (!\z80_|execute_|ctl_alu_bs_oe~8_combout & ((\z80_|execute_|ctl_alu_shift_oe~34_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & \z80_|execute_|ctl_ir_we~10_combout )))) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~8_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~34_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_ir_we~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~35 .lut_mask = 16'h5444; +defparam \z80_|execute_|ctl_alu_shift_oe~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~36 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~36_combout = (((\z80_|execute_|ctl_alu_shift_oe~35_combout ) # (!\z80_|execute_|ctl_flags_bus~9_combout )) # (!\z80_|execute_|ctl_reg_use_sp~1_combout )) # (!\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ), + .datab(\z80_|execute_|ctl_reg_use_sp~1_combout ), + .datac(\z80_|execute_|ctl_flags_bus~9_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~35_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~36 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_alu_shift_oe~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~28 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~28_combout = (\z80_|execute_|ctl_state_alu~4_combout & ((\z80_|execute_|ctl_ir_we~7_combout ) # ((\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ctl_bus_db_oe~1_combout )))) # (!\z80_|execute_|ctl_state_alu~4_combout +// & (\z80_|execute_|ixy_d~7_combout & ((!\z80_|execute_|ctl_bus_db_oe~1_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|execute_|ctl_ir_we~7_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~28 .lut_mask = 16'hA0EC; +defparam \z80_|execute_|ctl_alu_shift_oe~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~44 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~44_combout = (!\z80_|execute_|ctl_alu_op_low~26_combout & (((!\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~26_combout ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|execute_|ctl_mRead~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~44 .lut_mask = 16'h1555; +defparam \z80_|execute_|ctl_alu_shift_oe~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~29 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~29_combout = (\z80_|execute_|ctl_alu_shift_oe~28_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~44_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~20_combout )) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~28_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_shift_oe~20_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~44_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~29 .lut_mask = 16'hAFFF; +defparam \z80_|execute_|ctl_alu_shift_oe~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~16 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~16_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|execute_|ixy_d~15_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|execute_|ixy_d~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~16 .lut_mask = 16'h0F00; +defparam \z80_|execute_|ctl_alu_shift_oe~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~27 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~27_combout = (!\z80_|execute_|ctl_alu_bs_oe~combout & ((\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ) # (\z80_|execute_|ctl_alu_shift_oe~16_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), + .datab(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~27 .lut_mask = 16'h3332; +defparam \z80_|execute_|ctl_alu_shift_oe~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~10_combout = ((\z80_|execute_|ctl_alu_bs_oe~9_combout ) # ((\z80_|execute_|ctl_alu_bs_oe~12_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~7_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~6_combout ) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~6_combout ), + .datab(\z80_|execute_|ctl_alu_bs_oe~9_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~12_combout ), + .datad(\z80_|execute_|ctl_alu_bs_oe~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~10 .lut_mask = 16'hFDFF; +defparam \z80_|execute_|ctl_alu_bs_oe~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~31 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~31_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~3_combout & (\z80_|execute_|ctl_sw_4u~1_combout & ((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout )))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datab(\z80_|pla_decode_|Equal47~0_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), + .datad(\z80_|execute_|ctl_sw_4u~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~31 .lut_mask = 16'h7000; +defparam \z80_|execute_|ctl_alu_shift_oe~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~30 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~30_combout = (\z80_|execute_|ctl_mWrite~5_combout & (!\z80_|execute_|ctl_mWrite~17_combout & ((!\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|ctl_state_alu~2_combout )))) # +// (!\z80_|execute_|ctl_mWrite~5_combout & (((!\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|ctl_state_alu~2_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~5_combout ), + .datab(\z80_|execute_|ctl_mWrite~17_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_mRead~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~30 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_alu_shift_oe~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~32 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~32_combout = (\z80_|execute_|ctl_alu_shift_oe~31_combout & (\z80_|execute_|ctl_alu_shift_oe~30_combout & ((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_mRead~9_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~9_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~31_combout ), + .datac(\z80_|pla_decode_|Equal47~0_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~30_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~32 .lut_mask = 16'h4C00; +defparam \z80_|execute_|ctl_alu_shift_oe~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~33 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~33_combout = (\z80_|execute_|ctl_alu_shift_oe~27_combout ) # ((!\z80_|execute_|ctl_alu_bs_oe~10_combout & ((\z80_|execute_|ctl_alu_shift_oe~29_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~32_combout )))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~29_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~27_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~10_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~32_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~33 .lut_mask = 16'hCECF; +defparam \z80_|execute_|ctl_alu_shift_oe~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y20_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~21 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~21_combout = (\z80_|execute_|ctl_ir_we~15_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # ((!\z80_|execute_|ctl_ir_we~4_combout & \z80_|execute_|ctl_state_alu~4_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~15_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|ctl_state_alu~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~21 .lut_mask = 16'hAA20; +defparam \z80_|execute_|ctl_alu_shift_oe~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y20_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~45 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~45_combout = (\z80_|execute_|ctl_alu_shift_oe~21_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|execute_|ctl_alu_shift_oe~21_combout ), + .datad(\z80_|execute_|ctl_ir_we~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~45 .lut_mask = 16'hD0F0; +defparam \z80_|execute_|ctl_alu_shift_oe~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y20_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~22 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~22_combout = (\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_alu_shift_oe~45_combout ) # (\z80_|execute_|ctl_state_alu~4_combout )))) # +// (!\z80_|execute_|ctl_ir_we~9_combout & (\z80_|execute_|ctl_alu_shift_oe~45_combout )) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~45_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ctl_ir_we~9_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~22 .lut_mask = 16'h3A2A; +defparam \z80_|execute_|ctl_alu_shift_oe~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y20_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~23 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~23_combout = (\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|execute_|ctl_alu_shift_oe~22_combout ) # (\z80_|execute_|ctl_eval_cond~0_combout )))) # +// (!\z80_|execute_|ctl_ir_we~9_combout & (\z80_|execute_|ctl_alu_shift_oe~22_combout )) + + .dataa(\z80_|execute_|ctl_ir_we~9_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~22_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~23 .lut_mask = 16'h44EC; +defparam \z80_|execute_|ctl_alu_shift_oe~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y20_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~24 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~24_combout = (\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_mWrite~9_combout ) # (\z80_|execute_|ctl_alu_shift_oe~23_combout )))) # +// (!\z80_|execute_|ctl_ir_we~12_combout & (((\z80_|execute_|ctl_alu_shift_oe~23_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~12_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ctl_mWrite~9_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~23_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~24 .lut_mask = 16'h7720; +defparam \z80_|execute_|ctl_alu_shift_oe~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y20_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~25 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~25_combout = (\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # (\z80_|execute_|ctl_alu_shift_oe~24_combout )))) # +// (!\z80_|execute_|ctl_ir_we~12_combout & (((\z80_|execute_|ctl_alu_shift_oe~24_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|execute_|ctl_mWrite~5_combout ), + .datac(\z80_|execute_|ctl_ir_we~12_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~25 .lut_mask = 16'h5F40; +defparam \z80_|execute_|ctl_alu_shift_oe~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~26 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~26_combout = (!\z80_|execute_|ctl_alu_bs_oe~12_combout & ((\z80_|execute_|ctl_alu_shift_oe~25_combout ) # ((\z80_|execute_|ctl_mWrite~9_combout & \z80_|execute_|ctl_ir_we~11_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~9_combout ), + .datab(\z80_|execute_|ctl_ir_we~11_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~25_combout ), + .datad(\z80_|execute_|ctl_alu_bs_oe~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~26 .lut_mask = 16'h00F8; +defparam \z80_|execute_|ctl_alu_shift_oe~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~43 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~43_combout = (\z80_|execute_|ctl_alu_shift_oe~42_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~36_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~33_combout ) # (\z80_|execute_|ctl_alu_shift_oe~26_combout ))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~42_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~36_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~33_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~26_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~43 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_alu_shift_oe~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_low ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_low~combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ixy_d~9_combout ) # ((\z80_|execute_|ixy_d~7_combout & !\z80_|ir_|opcode [3])))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ixy_d~9_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_low .lut_mask = 16'hC0E0; +defparam \z80_|execute_|ctl_alu_op1_sel_low .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_zero~5_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal63~0_combout & !\z80_|ir_|opcode [4]))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|pla_decode_|Equal63~0_combout ), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_zero~5 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_alu_op1_sel_zero~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y17_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_zero~combout = (\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # ((\z80_|execute_|ctl_66_oe~2_combout ) # ((\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # (\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .datab(\z80_|execute_|ctl_66_oe~2_combout ), + .datac(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_zero .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_alu_op1_sel_zero .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y17_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~13 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~13_combout = (!\z80_|execute_|ctl_alu_op_low~26_combout & (((!\z80_|pla_decode_|Equal41~2_combout & !\z80_|execute_|ctl_ir_we~11_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~26_combout ), + .datab(\z80_|pla_decode_|Equal41~2_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|execute_|ctl_ir_we~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~13 .lut_mask = 16'h0515; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y19_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~17 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~17_combout = (\z80_|execute_|ctl_flags_xy_we~14_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|pla_decode_|Equal48~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal48~0_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~14_combout ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~17 .lut_mask = 16'hCC4C; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y19_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~14 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~14_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~13_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~17_combout & (\z80_|execute_|ctl_bus_db_oe~0_combout & \z80_|execute_|ctl_alu_op1_sel_bus~8_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~13_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~17_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~0_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~14 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y20_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~3 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~3_combout = (\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ctl_ir_we~15_combout ) # (!\z80_|execute_|ctl_state_alu~2_combout )))) # (!\z80_|execute_|ctl_ir_we~9_combout +// & (((!\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_state_alu~2_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~9_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_ir_we~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~3 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_alu_core_R~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y20_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~4_combout = (\z80_|execute_|ctl_alu_core_R~3_combout & (((!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~9_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~15_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_ir_we~9_combout ), + .datad(\z80_|execute_|ctl_alu_core_R~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~4 .lut_mask = 16'h3700; +defparam \z80_|execute_|ctl_alu_core_R~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|execute_|ctl_ir_we~11_combout & \z80_|sequencer_|DFFE_T4_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|execute_|ctl_ir_we~11_combout ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 .lut_mask = 16'h4400; +defparam \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y20_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~9_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|execute_|ctl_ir_we~10_combout & ((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|ctl_ir_we~7_combout )))) # +// (!\z80_|execute_|ctl_eval_cond~0_combout & (((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|ctl_ir_we~7_combout )))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|ctl_ir_we~10_combout ), + .datac(\z80_|execute_|ctl_ir_we~7_combout ), + .datad(\z80_|execute_|ctl_state_alu~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~9 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~10_combout = (!\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout & (\z80_|execute_|ctl_flags_sz_we~0_combout & (\z80_|execute_|ctl_flags_alu~18_combout & \z80_|execute_|ctl_alu_op1_sel_bus~9_combout +// ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .datac(\z80_|execute_|ctl_flags_alu~18_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~10 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~11_combout = (((\z80_|execute_|ctl_alu_oe~1_combout & \z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~10_combout )) # (!\z80_|execute_|ctl_alu_core_R~4_combout ) + + .dataa(\z80_|execute_|ctl_alu_oe~1_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_alu_core_R~4_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~11 .lut_mask = 16'h8FFF; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~12_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ) # ((\z80_|execute_|ixy_d~15_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T4_ff~q )))) + + .dataa(\z80_|execute_|ixy_d~15_combout ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~12 .lut_mask = 16'hFFA8; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~15 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~15_combout = ((\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~32_combout ) # (!\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ))) # (!\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~32_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~15 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N6 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & ((\z80_|alu_|db_low[3]~17_combout ) # ((!\z80_|alu_|db_high[3]~0_combout & !\z80_|execute_|ctl_alu_shift_oe~43_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datab(\z80_|alu_|db_high[3]~0_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datad(\z80_|alu_|db_low[3]~17_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9 .lut_mask = 16'hAA02; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N4 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~6 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~6_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & ((\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ) # ((\z80_|alu_|db_high[3]~7_combout & \z80_|execute_|ctl_alu_op1_sel_low~combout )))) + + .dataa(\z80_|alu_|db_high[3]~7_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .datad(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~6 .lut_mask = 16'h0F08; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N30 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|ena ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|ena~combout = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~combout ) # (\z80_|execute_|ctl_alu_op1_sel_low~combout )) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|ena .lut_mask = 16'hFFFA; +defparam \z80_|alu_|b2v_op1_latch_mux_low|ena .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y17_N5 +dffeas \z80_|alu_|op1_low[3] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), .devclrn(devclrn), .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), - .portbdataout()); + .q(\z80_|alu_|op1_low [3]), + .prn(vcc)); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; +defparam \z80_|alu_|op1_low[3] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_low[3] .power_up = "low"; // synopsys translate_on -// Location: M9K_X33_Y18_N0 +// Location: LCCOMB_X31_Y17_N4 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~15 ( +// Equation(s): +// \z80_|alu_|db_low[3]~15_combout = (\z80_|execute_|ctl_alu_op2_oe~0_combout & (\z80_|alu_|op2_low [3] & ((\z80_|alu_|op1_low [3]) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout & (((\z80_|alu_|op1_low [3])) +// # (!\z80_|execute_|ctl_alu_op1_oe~1_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datac(\z80_|alu_|op2_low [3]), + .datad(\z80_|alu_|op1_low [3]), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~15 .lut_mask = 16'hF531; +defparam \z80_|alu_|db_low[3]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N24 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~16 ( +// Equation(s): +// \z80_|alu_|db_low[3]~16_combout = (\z80_|alu_|db_low[3]~15_combout & (((\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout & !\z80_|bus_control_|db[5]~15_combout )) # (!\z80_|execute_|ctl_alu_bs_oe~combout ))) + + .dataa(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), + .datab(\z80_|bus_control_|db[5]~15_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datad(\z80_|alu_|db_low[3]~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~16 .lut_mask = 16'h2F00; +defparam \z80_|alu_|db_low[3]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~33 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~33_combout = (\z80_|execute_|ctl_state_alu~3_combout & (((\z80_|execute_|ctl_alu_op_low~24_combout ) # (\z80_|pla_decode_|Equal56~0_combout )))) # (!\z80_|execute_|ctl_state_alu~3_combout & +// (\z80_|execute_|ctl_mWrite~5_combout & ((\z80_|execute_|ctl_alu_op_low~24_combout ) # (\z80_|pla_decode_|Equal56~0_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~3_combout ), + .datab(\z80_|execute_|ctl_mWrite~5_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~24_combout ), + .datad(\z80_|pla_decode_|Equal56~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~33 .lut_mask = 16'hEEE0; +defparam \z80_|execute_|ctl_alu_op_low~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y20_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~34 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~34_combout = (\z80_|execute_|ctl_alu_op_low~33_combout ) # (((\z80_|execute_|ctl_alu_op_low~28_combout ) # (!\z80_|execute_|ctl_alu_op2_sel_bus~4_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~38_combout )) + + .dataa(\z80_|execute_|ctl_alu_op_low~33_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~38_combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~28_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~34 .lut_mask = 16'hFFBF; +defparam \z80_|execute_|ctl_alu_op_low~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~48 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~48_combout = (((!\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|execute_|ctl_alu_op_low~25_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|execute_|ctl_alu_op_low~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~48 .lut_mask = 16'h73FF; +defparam \z80_|execute_|ctl_alu_op_low~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~35 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~35_combout = (\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # (((\z80_|execute_|ctl_alu_op_low~22_combout & \z80_|execute_|ctl_mWrite~17_combout )) # (!\z80_|execute_|ctl_alu_op_low~45_combout )) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~45_combout ), + .datad(\z80_|execute_|ctl_mWrite~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~35 .lut_mask = 16'hEFAF; +defparam \z80_|execute_|ctl_alu_op_low~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~36 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~36_combout = (((\z80_|execute_|ctl_alu_op_low~35_combout ) # (!\z80_|execute_|ctl_alu_core_R~4_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~10_combout )) # (!\z80_|execute_|ctl_alu_op_low~23_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~23_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), + .datac(\z80_|execute_|ctl_alu_core_R~4_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~35_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~36 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_alu_op_low~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y20_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~37 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~37_combout = (\z80_|execute_|ctl_alu_op_low~34_combout ) # (((\z80_|execute_|ctl_alu_op_low~36_combout ) # (!\z80_|execute_|ctl_alu_op_low~48_combout )) # (!\z80_|execute_|ctl_alu_op_low~31_combout )) + + .dataa(\z80_|execute_|ctl_alu_op_low~34_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~31_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~48_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~36_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~37 .lut_mask = 16'hFFBF; +defparam \z80_|execute_|ctl_alu_op_low~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|pla_decode_|Equal21~1_combout & !\z80_|sequencer_|DFFE_M1_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 .lut_mask = 16'h0088; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y20_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~38 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~38_combout = (\z80_|execute_|ixy_d~5_combout & (((\z80_|execute_|ctl_mRead~34_combout ) # (\z80_|pla_decode_|Equal39~0_combout )))) # (!\z80_|execute_|ixy_d~5_combout & (\z80_|execute_|ctl_eval_cond~0_combout & +// (\z80_|execute_|ctl_mRead~34_combout ))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|pla_decode_|Equal39~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~38 .lut_mask = 16'hECE0; +defparam \z80_|execute_|ctl_alu_op_low~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~39 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~39_combout = (\z80_|execute_|ixy_d~9_combout & ((\z80_|pla_decode_|Equal39~0_combout ) # ((\z80_|pla_decode_|Equal40~1_combout )))) # (!\z80_|execute_|ixy_d~9_combout & (((\z80_|execute_|ixy_d~5_combout & +// \z80_|pla_decode_|Equal40~1_combout )))) + + .dataa(\z80_|pla_decode_|Equal39~0_combout ), + .datab(\z80_|execute_|ixy_d~9_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|pla_decode_|Equal40~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~39 .lut_mask = 16'hFC88; +defparam \z80_|execute_|ctl_alu_op_low~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y20_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~40 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~40_combout = (\z80_|execute_|ctl_alu_op_low~37_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ) # ((\z80_|execute_|ctl_alu_op_low~38_combout ) # (\z80_|execute_|ctl_alu_op_low~39_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~37_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), + .datac(\z80_|execute_|ctl_alu_op_low~38_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~39_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~40 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_alu_op_low~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~41 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~41_combout = (\z80_|execute_|ctl_alu_op_low~40_combout ) # ((\z80_|pla_decode_|Equal21~1_combout & ((\z80_|execute_|ixy_d~5_combout ) # (\z80_|execute_|ixy_d~9_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|execute_|ixy_d~9_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~40_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~41 .lut_mask = 16'hFFC8; +defparam \z80_|execute_|ctl_alu_op_low~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~combout = (\z80_|execute_|ctl_alu_op_low~41_combout ) # ((\z80_|execute_|ixy_d~15_combout & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|execute_|ctl_alu_op_low~41_combout ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|execute_|ixy_d~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low .lut_mask = 16'hFECC; +defparam \z80_|execute_|ctl_alu_op_low .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y16_N25 +dffeas \z80_|alu_|result_lo[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_alu_op_low~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|result_lo [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|result_lo[3] .is_wysiwyg = "true"; +defparam \z80_|alu_|result_lo[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~5_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout & (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal20~0_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .datac(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~5 .lut_mask = 16'h0103; +defparam \z80_|execute_|ctl_alu_oe~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~6_combout = (\z80_|execute_|ctl_alu_oe~5_combout & (((!\z80_|execute_|ctl_mRead~24_combout & !\z80_|execute_|ctl_mRead~25_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~24_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|execute_|ctl_alu_oe~5_combout ), + .datad(\z80_|execute_|ctl_mRead~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~6 .lut_mask = 16'h3070; +defparam \z80_|execute_|ctl_alu_oe~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~9_combout = (\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_mWrite~17_combout ) # ((\z80_|execute_|ctl_alu_oe~1_combout ) # (\z80_|pla_decode_|Equal69~0_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~17_combout ), + .datab(\z80_|execute_|ctl_alu_oe~1_combout ), + .datac(\z80_|pla_decode_|Equal69~0_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~9 .lut_mask = 16'hFE00; +defparam \z80_|execute_|ctl_alu_oe~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~12_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~12_combout & !\z80_|execute_|ctl_ir_we~11_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~12_combout ), + .datab(\z80_|execute_|ctl_ir_we~11_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~12 .lut_mask = 16'hFFF1; +defparam \z80_|execute_|ctl_alu_core_S~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~10_combout = ((\z80_|execute_|ctl_alu_oe~9_combout ) # ((!\z80_|execute_|ctl_alu_core_S~12_combout ) # (!\z80_|execute_|ctl_alu_oe~4_combout ))) # (!\z80_|execute_|ctl_alu_oe~6_combout ) + + .dataa(\z80_|execute_|ctl_alu_oe~6_combout ), + .datab(\z80_|execute_|ctl_alu_oe~9_combout ), + .datac(\z80_|execute_|ctl_alu_oe~4_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~10 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_alu_oe~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~2 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~2_combout = ((!\z80_|execute_|ctl_alu_op_low~25_combout & (!\z80_|execute_|ctl_alu_op_low~24_combout & !\z80_|pla_decode_|Equal56~0_combout ))) # (!\z80_|execute_|ixy_d~7_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~25_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~24_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|pla_decode_|Equal56~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~2 .lut_mask = 16'h0F1F; +defparam \z80_|execute_|ctl_alu_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout = (!\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|nM1_int~2_combout & \z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~1_combout ), + .datab(\z80_|pla_decode_|Equal3~1_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~15 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~15_combout = ((!\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_ir_we~8_combout & !\z80_|execute_|ctl_ir_we~10_combout ))) # (!\z80_|nM1_int~2_combout ) + + .dataa(\z80_|execute_|ctl_ir_we~9_combout ), + .datab(\z80_|execute_|ctl_ir_we~8_combout ), + .datac(\z80_|execute_|ctl_ir_we~10_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~15 .lut_mask = 16'h01FF; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~8_combout = (!\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~15_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout & \z80_|execute_|ctl_flags_sz_we~1_combout ))) + + .dataa(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~15_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), + .datad(\z80_|execute_|ctl_flags_sz_we~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~8 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_reg_in_hi~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N6 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~7 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~7_combout = (\z80_|reg_control_|reg_sys_we_lo~6_combout & ((!\z80_|execute_|ixy_d~15_combout ) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|reg_control_|reg_sys_we_lo~6_combout ), + .datac(\z80_|execute_|ixy_d~15_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~7 .lut_mask = 16'h4C4C; +defparam \z80_|reg_control_|reg_sys_we_lo~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~7_combout = (\z80_|execute_|ctl_reg_in_hi~8_combout & (\z80_|reg_control_|reg_sys_we_lo~7_combout & ((!\z80_|pla_decode_|Equal13~2_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~8_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|reg_control_|reg_sys_we_lo~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~7 .lut_mask = 16'h4C00; +defparam \z80_|execute_|ctl_alu_oe~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y17_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~11 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~11_combout = (\z80_|execute_|ctl_flags_use_cf2~13_combout & (((!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~7_combout )) # (!\z80_|execute_|ctl_mWrite~5_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~5_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|execute_|ctl_ir_we~7_combout ), + .datad(\z80_|execute_|ctl_flags_use_cf2~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~11 .lut_mask = 16'h5700; +defparam \z80_|execute_|ctl_mWrite~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_we~5_combout = (\z80_|execute_|ctl_bus_inc_oe~28_combout & (\z80_|execute_|ctl_mWrite~11_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|execute_|ctl_mRead~24_combout )))) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~28_combout ), + .datab(\z80_|execute_|ctl_mRead~24_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|execute_|ctl_mWrite~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_we~5 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_bus_db_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~8_combout = (\z80_|execute_|ctl_reg_in_lo~9_combout & (\z80_|execute_|ctl_alu_oe~2_combout & (\z80_|execute_|ctl_alu_oe~7_combout & \z80_|execute_|ctl_bus_db_we~5_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .datab(\z80_|execute_|ctl_alu_oe~2_combout ), + .datac(\z80_|execute_|ctl_alu_oe~7_combout ), + .datad(\z80_|execute_|ctl_bus_db_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~8 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_oe~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~16 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~16_combout = (\z80_|execute_|ctl_flags_alu~10_combout & (!\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout & (\z80_|execute_|ctl_flags_xy_we~10_combout & !\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ))) + + .dataa(\z80_|execute_|ctl_flags_alu~10_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~10_combout ), + .datad(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~16 .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_flags_alu~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~11_combout = (\z80_|execute_|ctl_alu_oe~10_combout ) # (((\z80_|execute_|ctl_66_oe~2_combout ) # (!\z80_|execute_|ctl_flags_alu~16_combout )) # (!\z80_|execute_|ctl_alu_oe~8_combout )) + + .dataa(\z80_|execute_|ctl_alu_oe~10_combout ), + .datab(\z80_|execute_|ctl_alu_oe~8_combout ), + .datac(\z80_|execute_|ctl_flags_alu~16_combout ), + .datad(\z80_|execute_|ctl_66_oe~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~11 .lut_mask = 16'hFFBF; +defparam \z80_|execute_|ctl_alu_oe~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y19_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~48 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~48_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|pla_decode_|Equal21~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal21~1_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~48 .lut_mask = 16'hD0F0; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_hi~8_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & ((\z80_|execute_|ctl_ir_we~12_combout ) # (!\z80_|execute_|nextM~2_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|execute_|nextM~2_combout ), + .datac(\z80_|execute_|ctl_ir_we~12_combout ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_hi~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_hi~8 .lut_mask = 16'hA200; +defparam \z80_|execute_|ctl_reg_out_hi~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_hi~5_combout = (\z80_|execute_|ctl_reg_out_lo~2_combout & (\z80_|execute_|rsel3~combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|execute_|ctl_mRead~3_combout )))) # (!\z80_|execute_|ctl_reg_out_lo~2_combout & +// (((!\z80_|execute_|ixy_d~7_combout )) # (!\z80_|execute_|ctl_mRead~3_combout ))) + + .dataa(\z80_|execute_|ctl_reg_out_lo~2_combout ), + .datab(\z80_|execute_|ctl_mRead~3_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|rsel3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_hi~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_hi~5 .lut_mask = 16'h3F15; +defparam \z80_|execute_|ctl_reg_out_hi~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~2 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~2_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|execute_|ctl_mWrite~8_combout & ((!\z80_|execute_|ctl_mRead~7_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|execute_|ctl_eval_cond~0_combout & +// (((!\z80_|execute_|ctl_mRead~7_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|ctl_mWrite~8_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|execute_|ctl_mRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~2 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_sw_2u~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~0 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~0_combout = (\z80_|execute_|ctl_state_alu~3_combout & (!\z80_|execute_|ctl_mWrite~6_combout & ((!\z80_|pla_decode_|Equal9~1_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|execute_|ctl_state_alu~3_combout & +// (((!\z80_|pla_decode_|Equal9~1_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~3_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|pla_decode_|Equal9~1_combout ), + .datad(\z80_|execute_|ctl_mWrite~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~0 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_sw_2u~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~3 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~3_combout = (\z80_|execute_|ctl_sw_2u~2_combout & (\z80_|execute_|ctl_sw_2u~0_combout & ((!\z80_|execute_|ctl_mRead~6_combout ) # (!\z80_|execute_|ctl_alu_oe~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_oe~0_combout ), + .datab(\z80_|execute_|ctl_mRead~6_combout ), + .datac(\z80_|execute_|ctl_sw_2u~2_combout ), + .datad(\z80_|execute_|ctl_sw_2u~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~3 .lut_mask = 16'h7000; +defparam \z80_|execute_|ctl_sw_2u~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y15_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~47 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~47_combout = (\z80_|execute_|ctl_sw_2u~3_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|execute_|ctl_mRead~8_combout )) # (!\z80_|sequencer_|M5~q ))) + + .dataa(\z80_|sequencer_|M5~q ), + .datab(\z80_|execute_|ctl_sw_2u~3_combout ), + .datac(\z80_|execute_|ctl_mRead~8_combout ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~47 .lut_mask = 16'hCC4C; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y18_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~33 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~33_combout = (\z80_|execute_|ctl_state_alu~3_combout & (!\z80_|pla_decode_|Equal47~0_combout & ((!\z80_|execute_|ctl_ir_we~4_combout ) # (!\z80_|pla_decode_|Equal34~0_combout )))) # (!\z80_|execute_|ctl_state_alu~3_combout & +// (((!\z80_|execute_|ctl_ir_we~4_combout )) # (!\z80_|pla_decode_|Equal34~0_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~3_combout ), + .datab(\z80_|pla_decode_|Equal34~0_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~33 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_inc_cy~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~37 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~37_combout = (\z80_|execute_|ctl_inc_cy~33_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|sequencer_|DFFE_M4_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|pla_decode_|Equal19~0_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|execute_|ctl_inc_cy~33_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~37 .lut_mask = 16'hF700; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~6 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~6_combout = (\z80_|execute_|ctl_reg_gp_sel~7_combout & (\z80_|ir_|opcode [0] $ ((!\z80_|execute_|comb~0_combout )))) # (!\z80_|execute_|ctl_reg_gp_sel~7_combout & (!\z80_|execute_|ctl_sw_2u~5_combout & (\z80_|ir_|opcode [0] $ +// (!\z80_|execute_|comb~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel~7_combout ), + .datab(\z80_|ir_|opcode [0]), + .datac(\z80_|execute_|comb~0_combout ), + .datad(\z80_|execute_|ctl_sw_2u~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~6 .lut_mask = 16'h82C3; +defparam \z80_|execute_|ctl_sw_2u~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_hi~6_combout = (\z80_|execute_|ctl_reg_out_hi~5_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~37_combout & !\z80_|execute_|ctl_sw_2u~6_combout ))) + + .dataa(\z80_|execute_|ctl_reg_out_hi~5_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~37_combout ), + .datad(\z80_|execute_|ctl_sw_2u~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_hi~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_hi~6 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_out_hi~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_hi~7_combout = (((\z80_|execute_|ctl_reg_out_hi~8_combout ) # (!\z80_|execute_|ctl_reg_out_hi~6_combout )) # (!\z80_|execute_|ctl_reg_out_hi~4_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), + .datab(\z80_|execute_|ctl_reg_out_hi~4_combout ), + .datac(\z80_|execute_|ctl_reg_out_hi~8_combout ), + .datad(\z80_|execute_|ctl_reg_out_hi~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_hi~7 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|ctl_reg_out_hi~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~2 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~2_combout = (\z80_|pla_decode_|Equal3~0_combout & (\z80_|pla_decode_|Equal1~7_combout & (\z80_|pla_decode_|Equal2~0_combout & !\z80_|ir_|opcode [5]))) + + .dataa(\z80_|pla_decode_|Equal3~0_combout ), + .datab(\z80_|pla_decode_|Equal1~7_combout ), + .datac(\z80_|pla_decode_|Equal2~0_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~2 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_mRead~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~6 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~6_combout = (\z80_|pla_decode_|Equal9~1_combout & (!\z80_|execute_|ixy_d~6_combout & ((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) # (!\z80_|pla_decode_|Equal9~1_combout & +// (((!\z80_|execute_|ctl_mRead~9_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|pla_decode_|Equal47~0_combout ), + .datac(\z80_|execute_|ctl_mRead~9_combout ), + .datad(\z80_|execute_|ixy_d~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~6 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_sw_2d~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~7 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~7_combout = (\z80_|execute_|ctl_sw_2d~6_combout & (((!\z80_|execute_|ctl_mRead~2_combout & !\z80_|pla_decode_|Equal6~1_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_mRead~2_combout ), + .datac(\z80_|pla_decode_|Equal6~1_combout ), + .datad(\z80_|execute_|ctl_sw_2d~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~7 .lut_mask = 16'h5700; +defparam \z80_|execute_|ctl_sw_2d~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout = (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal1~4_combout & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|ir_|opcode [0]))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|pla_decode_|Equal1~4_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~8 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~8_combout = (\z80_|execute_|ctl_flags_sz_we~0_combout & (\z80_|execute_|ctl_sw_2d~7_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout & \z80_|execute_|ctl_alu_shift_oe~44_combout ))) + + .dataa(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .datab(\z80_|execute_|ctl_sw_2d~7_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~44_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~8 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_sw_2d~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~7 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~7_combout = (\z80_|execute_|ctl_flags_alu~19_combout & (((!\z80_|execute_|ctl_mRead~25_combout & !\z80_|execute_|ctl_mRead~24_combout )) # (!\z80_|execute_|ixy_d~9_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~25_combout ), + .datab(\z80_|execute_|ctl_flags_alu~19_combout ), + .datac(\z80_|execute_|ixy_d~9_combout ), + .datad(\z80_|execute_|ctl_mRead~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~7 .lut_mask = 16'h0C4C; +defparam \z80_|execute_|ctl_bus_db_oe~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~5 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~5_combout = (\z80_|execute_|ctl_bus_db_oe~7_combout & (((!\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_bus_db_oe~1_combout )) # (!\z80_|execute_|ixy_d~7_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(\z80_|execute_|ctl_bus_db_oe~7_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~5 .lut_mask = 16'h4C0C; +defparam \z80_|execute_|ctl_sw_2d~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~19 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~19_combout = (\z80_|execute_|ctl_mRead~15_combout ) # ((\z80_|pla_decode_|Equal9~1_combout ) # ((!\z80_|pla_decode_|Equal12~1_combout & \z80_|pla_decode_|Equal25~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal12~1_combout ), + .datab(\z80_|execute_|ctl_mRead~15_combout ), + .datac(\z80_|pla_decode_|Equal9~1_combout ), + .datad(\z80_|pla_decode_|Equal25~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~19 .lut_mask = 16'hFDFC; +defparam \z80_|execute_|ctl_mRead~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~18 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~18_combout = (\z80_|execute_|ctl_mRead~8_combout ) # ((\z80_|execute_|ctl_mRead~13_combout ) # ((\z80_|execute_|ctl_mRead~7_combout ) # (\z80_|execute_|ctl_mRead~6_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~8_combout ), + .datab(\z80_|execute_|ctl_mRead~13_combout ), + .datac(\z80_|execute_|ctl_mRead~7_combout ), + .datad(\z80_|execute_|ctl_mRead~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~18 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_mRead~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N26 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~2 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~2_combout = (\z80_|pla_decode_|Equal35~0_combout ) # ((\z80_|pla_decode_|Equal34~0_combout ) # ((\z80_|pla_decode_|Equal37~0_combout ) # (\z80_|pla_decode_|Equal38~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal35~0_combout ), + .datab(\z80_|pla_decode_|Equal34~0_combout ), + .datac(\z80_|pla_decode_|Equal37~0_combout ), + .datad(\z80_|pla_decode_|Equal38~2_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~2 .lut_mask = 16'hFFFE; +defparam \z80_|reg_control_|reg_sys_we_lo~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal24~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal24~1_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal1~7_combout & \z80_|pla_decode_|Equal9~0_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal2~0_combout ), + .datac(\z80_|pla_decode_|Equal1~7_combout ), + .datad(\z80_|pla_decode_|Equal9~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal24~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal24~1 .lut_mask = 16'h4000; +defparam \z80_|pla_decode_|Equal24~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N12 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~3 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~3_combout = (\z80_|pla_decode_|Equal29~0_combout ) # ((\z80_|pla_decode_|Equal19~0_combout ) # ((\z80_|reg_control_|reg_sys_we_lo~2_combout ) # (\z80_|pla_decode_|Equal24~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal29~0_combout ), + .datab(\z80_|pla_decode_|Equal19~0_combout ), + .datac(\z80_|reg_control_|reg_sys_we_lo~2_combout ), + .datad(\z80_|pla_decode_|Equal24~1_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~3 .lut_mask = 16'hFFFE; +defparam \z80_|reg_control_|reg_sys_we_lo~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N2 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~4 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~4_combout = (\z80_|reg_control_|reg_sys_we_lo~3_combout & (!\z80_|execute_|ctl_state_alu~2_combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) # +// (!\z80_|reg_control_|reg_sys_we_lo~3_combout & (((!\z80_|execute_|ctl_state_alu~4_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~3_combout ), + .datab(\z80_|pla_decode_|Equal47~0_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~4 .lut_mask = 16'h135F; +defparam \z80_|reg_control_|reg_sys_we_lo~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~20 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~20_combout = (\z80_|reg_control_|reg_sys_we_lo~4_combout & (((!\z80_|execute_|ctl_mRead~19_combout & !\z80_|execute_|ctl_mRead~18_combout )) # (!\z80_|execute_|ctl_state_alu~2_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~19_combout ), + .datab(\z80_|execute_|ctl_mRead~18_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|reg_control_|reg_sys_we_lo~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~20 .lut_mask = 16'h1F00; +defparam \z80_|execute_|ctl_mRead~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~5_combout = ((!\z80_|execute_|ctl_mRead~13_combout & (!\z80_|execute_|ctl_mRead~15_combout & !\z80_|execute_|ctl_mRead~16_combout ))) # (!\z80_|execute_|ixy_d~6_combout ) + + .dataa(\z80_|execute_|ctl_mRead~13_combout ), + .datab(\z80_|execute_|ctl_mRead~15_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ctl_mRead~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~5 .lut_mask = 16'h0F1F; +defparam \z80_|execute_|ctl_reg_in_hi~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y17_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~22 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~22_combout = (\z80_|execute_|ctl_mRead~20_combout & (\z80_|execute_|ctl_reg_in_hi~5_combout & ((!\z80_|execute_|ctl_mRead~16_combout ) # (!\z80_|execute_|ctl_state_alu~4_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|ctl_mRead~20_combout ), + .datac(\z80_|execute_|ctl_mRead~16_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~22 .lut_mask = 16'h4C00; +defparam \z80_|execute_|ctl_mRead~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout = (\z80_|execute_|ixy_d~6_combout & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal52~0_combout & !\z80_|ir_|opcode [0]))) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|pla_decode_|Equal3~1_combout ), + .datac(\z80_|pla_decode_|Equal52~0_combout ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~6_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & (((!\z80_|pla_decode_|Equal35~0_combout & !\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|execute_|ixy_d~6_combout ))) + + .dataa(\z80_|pla_decode_|Equal35~0_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~6 .lut_mask = 16'h0037; +defparam \z80_|execute_|ctl_reg_in_hi~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~2_combout = (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|M5~q ) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|sequencer_|M5~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~2 .lut_mask = 16'hAA00; +defparam \z80_|execute_|ctl_reg_in_hi~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|setM1~30 ( +// Equation(s): +// \z80_|execute_|setM1~30_combout = (\z80_|execute_|ixy_d~6_combout & (!\z80_|execute_|ctl_mRead~14_combout & ((!\z80_|execute_|ctl_mRead~15_combout ) # (!\z80_|execute_|ctl_reg_in_hi~2_combout )))) # (!\z80_|execute_|ixy_d~6_combout & +// (((!\z80_|execute_|ctl_mRead~15_combout )) # (!\z80_|execute_|ctl_reg_in_hi~2_combout ))) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datac(\z80_|execute_|ctl_mRead~14_combout ), + .datad(\z80_|execute_|ctl_mRead~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~30 .lut_mask = 16'h135F; +defparam \z80_|execute_|setM1~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~23 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~23_combout = (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|execute_|ctl_mRead~14_combout & ((!\z80_|execute_|ctl_mRead~15_combout ) # (!\z80_|execute_|ctl_state_alu~4_combout )))) # (!\z80_|execute_|ctl_state_alu~2_combout +// & (((!\z80_|execute_|ctl_mRead~15_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_mRead~14_combout ), + .datad(\z80_|execute_|ctl_mRead~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~23 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_mRead~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~6_combout = (\z80_|execute_|setM1~30_combout & (\z80_|execute_|ctl_mRead~23_combout & ((!\z80_|pla_decode_|Equal6~1_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) + + .dataa(\z80_|execute_|setM1~30_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|execute_|ctl_mRead~23_combout ), + .datad(\z80_|pla_decode_|Equal6~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~6 .lut_mask = 16'h20A0; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~3_combout = ((!\z80_|execute_|ctl_mRead~7_combout & (!\z80_|execute_|ctl_mRead~8_combout & !\z80_|execute_|ctl_mRead~6_combout ))) # (!\z80_|execute_|ixy_d~6_combout ) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|execute_|ctl_mRead~7_combout ), + .datac(\z80_|execute_|ctl_mRead~8_combout ), + .datad(\z80_|execute_|ctl_mRead~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~3 .lut_mask = 16'h5557; +defparam \z80_|execute_|ctl_reg_in_hi~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~10 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~10_combout = (\z80_|execute_|ctl_flags_alu~17_combout & (\z80_|execute_|ctl_flags_alu~6_combout & \z80_|execute_|ctl_reg_in_hi~3_combout )) + + .dataa(\z80_|execute_|ctl_flags_alu~17_combout ), + .datab(\z80_|execute_|ctl_flags_alu~6_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_in_hi~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~10 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_mWrite~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y18_N26 +cycloneive_lcell_comb \z80_|execute_|fMRead~18 ( +// Equation(s): +// \z80_|execute_|fMRead~18_combout = (\z80_|execute_|ctl_ir_we~15_combout & (!\z80_|execute_|ctl_state_alu~2_combout & ((!\z80_|execute_|ctl_mRead~16_combout ) # (!\z80_|execute_|ctl_reg_in_hi~2_combout )))) # (!\z80_|execute_|ctl_ir_we~15_combout & +// (((!\z80_|execute_|ctl_mRead~16_combout )) # (!\z80_|execute_|ctl_reg_in_hi~2_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~15_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_mRead~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~18 .lut_mask = 16'h135F; +defparam \z80_|execute_|fMRead~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N14 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_pc~0_combout = ((!\z80_|pla_decode_|Equal37~0_combout & ((!\z80_|pla_decode_|Equal24~0_combout ) # (!\z80_|pla_decode_|Equal9~0_combout )))) # (!\z80_|execute_|ixy_d~6_combout ) + + .dataa(\z80_|pla_decode_|Equal37~0_combout ), + .datab(\z80_|pla_decode_|Equal9~0_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|pla_decode_|Equal24~0_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_pc~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_pc~0 .lut_mask = 16'h1F5F; +defparam \z80_|reg_control_|reg_sel_pc~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N8 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~1 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_pc~1_combout = (\z80_|pla_decode_|Equal29~0_combout & (!\z80_|execute_|ixy_d~6_combout & ((!\z80_|execute_|ctl_reg_in_hi~2_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) # (!\z80_|pla_decode_|Equal29~0_combout & +// (((!\z80_|execute_|ctl_reg_in_hi~2_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal29~0_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|pla_decode_|Equal47~0_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_pc~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_pc~1 .lut_mask = 16'h0777; +defparam \z80_|reg_control_|reg_sel_pc~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N18 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~2 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_pc~2_combout = (\z80_|reg_control_|reg_sel_pc~0_combout & (\z80_|reg_control_|reg_sel_pc~1_combout & ((!\z80_|pla_decode_|Equal38~2_combout ) # (!\z80_|execute_|ixy_d~6_combout )))) + + .dataa(\z80_|reg_control_|reg_sel_pc~0_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|reg_control_|reg_sel_pc~1_combout ), + .datad(\z80_|pla_decode_|Equal38~2_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_pc~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_pc~2 .lut_mask = 16'h20A0; +defparam \z80_|reg_control_|reg_sel_pc~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y18_N18 +cycloneive_lcell_comb \z80_|execute_|fMRead~19 ( +// Equation(s): +// \z80_|execute_|fMRead~19_combout = (\z80_|reg_control_|reg_sel_pc~2_combout & (\z80_|execute_|ctl_state_alu~7_combout & ((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|ctl_ir_we~7_combout )))) + + .dataa(\z80_|reg_control_|reg_sel_pc~2_combout ), + .datab(\z80_|execute_|ctl_ir_we~7_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_state_alu~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~19 .lut_mask = 16'h2A00; +defparam \z80_|execute_|fMRead~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|fMRead~20 ( +// Equation(s): +// \z80_|execute_|fMRead~20_combout = (\z80_|execute_|ctl_mWrite~10_combout & (\z80_|execute_|ctl_sw_2d~4_combout & (\z80_|execute_|fMRead~18_combout & \z80_|execute_|fMRead~19_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~10_combout ), + .datab(\z80_|execute_|ctl_sw_2d~4_combout ), + .datac(\z80_|execute_|fMRead~18_combout ), + .datad(\z80_|execute_|fMRead~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~20 .lut_mask = 16'h8000; +defparam \z80_|execute_|fMRead~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|fMRead~21 ( +// Equation(s): +// \z80_|execute_|fMRead~21_combout = (\z80_|execute_|ctl_mRead~22_combout & (\z80_|execute_|ctl_reg_in_hi~6_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~6_combout & \z80_|execute_|fMRead~20_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~22_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~6_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), + .datad(\z80_|execute_|fMRead~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~21 .lut_mask = 16'h8000; +defparam \z80_|execute_|fMRead~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~9 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~9_combout = (\z80_|execute_|ctl_sw_2d~8_combout & (\z80_|execute_|ctl_sw_2d~5_combout & (!\z80_|execute_|ctl_alu_shift_oe~16_combout & \z80_|execute_|fMRead~21_combout ))) + + .dataa(\z80_|execute_|ctl_sw_2d~8_combout ), + .datab(\z80_|execute_|ctl_sw_2d~5_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~16_combout ), + .datad(\z80_|execute_|fMRead~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~9 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_sw_2d~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~14 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~14_combout = (!\z80_|execute_|ctl_mRead~12_combout & (((\z80_|decode_state_|in_halt~q ) # (!\z80_|pla_decode_|Equal77~0_combout )) # (!\z80_|pla_decode_|Equal33~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|decode_state_|in_halt~q ), + .datac(\z80_|execute_|ctl_mRead~12_combout ), + .datad(\z80_|pla_decode_|Equal77~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~14 .lut_mask = 16'h0D0F; +defparam \z80_|execute_|ctl_sw_2d~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~8 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~8_combout = (((\z80_|ir_|opcode [5] & !\z80_|ir_|opcode [4])) # (!\z80_|ir_|opcode [3])) # (!\z80_|pla_decode_|Equal12~0_combout ) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|pla_decode_|Equal12~0_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~8 .lut_mask = 16'h2FFF; +defparam \z80_|execute_|ctl_sw_1d~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~10 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~10_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (((\z80_|execute_|rsel3~combout & \z80_|execute_|ctl_iorw~10_combout )) # (!\z80_|execute_|nextM~2_combout ))) + + .dataa(\z80_|execute_|rsel3~combout ), + .datab(\z80_|execute_|ctl_iorw~10_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|nextM~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~10 .lut_mask = 16'h80F0; +defparam \z80_|execute_|ctl_sw_2d~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~11 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~11_combout = (\z80_|execute_|ctl_sw_2d~10_combout ) # ((\z80_|nM1_int~2_combout & ((!\z80_|execute_|ctl_sw_1d~8_combout ) # (!\z80_|execute_|ctl_sw_2d~14_combout )))) + + .dataa(\z80_|execute_|ctl_sw_2d~14_combout ), + .datab(\z80_|execute_|ctl_sw_1d~8_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_sw_2d~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~11 .lut_mask = 16'hFF70; +defparam \z80_|execute_|ctl_sw_2d~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~12 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~12_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|execute_|rsel3~combout & ((\z80_|execute_|ctl_alu_shift_oe~15_combout ) # (\z80_|execute_|ctl_alu_op_low~28_combout )))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~15_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~28_combout ), + .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datad(\z80_|execute_|rsel3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~12 .lut_mask = 16'hFEF0; +defparam \z80_|execute_|ctl_sw_2d~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~13 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~13_combout = ((\z80_|execute_|ctl_sw_2d~11_combout ) # ((\z80_|execute_|ctl_sw_2d~12_combout ) # (!\z80_|execute_|ctl_reg_out_lo~7_combout ))) # (!\z80_|execute_|ctl_sw_2d~9_combout ) + + .dataa(\z80_|execute_|ctl_sw_2d~9_combout ), + .datab(\z80_|execute_|ctl_sw_2d~11_combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .datad(\z80_|execute_|ctl_sw_2d~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~13 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|ctl_sw_2d~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N8 +cycloneive_lcell_comb \z80_|alu_|db[7]~9 ( +// Equation(s): +// \z80_|alu_|db[7]~9_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout ) # ((\z80_|execute_|ctl_sw_2d~13_combout ) # (\z80_|execute_|ctl_alu_oe~11_combout )) + + .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_sw_2d~13_combout ), + .datad(\z80_|execute_|ctl_alu_oe~11_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[7]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[7]~9 .lut_mask = 16'hFFFA; +defparam \z80_|alu_|db[7]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N0 +cycloneive_lcell_comb \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 ( +// Equation(s): +// \z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout = (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )) # (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ))) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 .lut_mask = 16'h1333; +defparam \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout = (\z80_|ir_|opcode [3] & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|pla_decode_|Equal63~0_combout & \z80_|ir_|opcode [4]))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|pla_decode_|Equal63~0_combout ), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~32 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~32_combout = (((!\z80_|pla_decode_|Equal3~0_combout & !\z80_|pla_decode_|Equal21~0_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal63~0_combout ) + + .dataa(\z80_|pla_decode_|Equal63~0_combout ), + .datab(\z80_|pla_decode_|Equal3~0_combout ), + .datac(\z80_|pla_decode_|Equal21~0_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~32 .lut_mask = 16'h57FF; +defparam \z80_|execute_|ctl_alu_op_low~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N2 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~2 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~2_combout = ((!\z80_|pla_decode_|Equal20~0_combout & ((!\z80_|pla_decode_|Equal68~2_combout ) # (!\z80_|pla_decode_|Equal1~4_combout )))) # (!\z80_|nM1_int~2_combout ) + + .dataa(\z80_|pla_decode_|Equal20~0_combout ), + .datab(\z80_|pla_decode_|Equal1~4_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal68~2_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~2 .lut_mask = 16'h1F5F; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~22 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~22_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|ir_|opcode [4])) # (!\z80_|pla_decode_|Equal63~0_combout )) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~22 .lut_mask = 16'hFBFF; +defparam \z80_|execute_|ctl_flags_xy_we~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N28 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~3 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~3_combout = (\z80_|execute_|ctl_alu_op_low~32_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~2_combout & \z80_|execute_|ctl_flags_xy_we~22_combout )) + + .dataa(\z80_|execute_|ctl_alu_op_low~32_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~2_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_flags_xy_we~22_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~3 .lut_mask = 16'h8800; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y18_N2 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~4 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~4_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~3_combout & (\z80_|execute_|ctl_flags_pf_we~10_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~8_combout & \z80_|execute_|ctl_alu_op_low~45_combout ))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~3_combout ), + .datab(\z80_|execute_|ctl_flags_pf_we~10_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~45_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~4 .lut_mask = 16'h8000; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N16 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~5 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~5_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout & (((!\z80_|pla_decode_|Equal21~0_combout & !\z80_|pla_decode_|Equal32~0_combout )) # (!\z80_|pla_decode_|Equal62~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal21~0_combout ), + .datab(\z80_|pla_decode_|Equal32~0_combout ), + .datac(\z80_|pla_decode_|Equal62~2_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~5 .lut_mask = 16'h1F00; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N8 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout = (\z80_|execute_|ctl_alu_shift_oe~38_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|execute_|ctl_ir_we~11_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|execute_|ctl_alu_shift_oe~38_combout ), + .datac(\z80_|execute_|ctl_ir_we~11_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 .lut_mask = 16'hCC4C; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N2 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout & (\z80_|execute_|ctl_flags_sz_we~4_combout & ((!\z80_|pla_decode_|Equal62~2_combout ) # (!\z80_|pla_decode_|Equal9~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal9~0_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ), + .datac(\z80_|pla_decode_|Equal62~2_combout ), + .datad(\z80_|execute_|ctl_flags_sz_we~4_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 .lut_mask = 16'h4C00; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~15 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~15_combout = (\z80_|ir_|opcode [5]) # (((!\z80_|pla_decode_|Equal32~0_combout & !\z80_|pla_decode_|Equal9~0_combout )) # (!\z80_|execute_|ctl_state_alu~11_combout )) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|execute_|ctl_state_alu~11_combout ), + .datac(\z80_|pla_decode_|Equal32~0_combout ), + .datad(\z80_|pla_decode_|Equal9~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~15 .lut_mask = 16'hBBBF; +defparam \z80_|execute_|ctl_alu_core_hf~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N8 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~6 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~6_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout & \z80_|execute_|ctl_alu_core_hf~15_combout ) + + .dataa(gnd), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~15_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~6 .lut_mask = 16'hC0C0; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N10 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~7 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~7_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~5_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~9_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout & !\z80_|execute_|ctl_alu_core_R~1_combout ))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~9_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ), + .datad(\z80_|execute_|ctl_alu_core_R~1_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~7 .lut_mask = 16'h0080; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|ir_|opcode [3]))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N20 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout = (\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ) # ((\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal10~0_combout ) # (\z80_|pla_decode_|Equal61~2_combout )))) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal61~2_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 .lut_mask = 16'hFCEC; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~17 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~17_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal3~1_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~17 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N18 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ) # ((\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ) # ((\z80_|alu_control_|db[1]~26_combout & \z80_|execute_|ctl_flags_bus~combout ))) + + .dataa(\z80_|alu_control_|db[1]~26_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ), + .datac(\z80_|execute_|ctl_flags_bus~combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 .lut_mask = 16'hFFEC; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N4 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout = ((\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ) # ((\z80_|alu_|db_high[3]~7_combout & \z80_|execute_|ctl_flags_alu~15_combout ))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ) + + .dataa(\z80_|alu_|db_high[3]~7_combout ), + .datab(\z80_|execute_|ctl_flags_alu~15_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 .lut_mask = 16'hFF8F; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_nf_we~3_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal10~0_combout ) # ((\z80_|pla_decode_|Equal11~0_combout ) # (\z80_|pla_decode_|Equal61~2_combout )))) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal61~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_nf_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_nf_we~3 .lut_mask = 16'hF0E0; +defparam \z80_|execute_|ctl_flags_nf_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y20_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~0 ( +// Equation(s): +// \z80_|execute_|ctl_flags_nf_we~0_combout = (\z80_|pla_decode_|Equal61~2_combout & (!\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|execute_|ctl_mRead~34_combout )))) # (!\z80_|pla_decode_|Equal61~2_combout & +// (((!\z80_|execute_|ixy_d~5_combout )) # (!\z80_|execute_|ctl_mRead~34_combout ))) + + .dataa(\z80_|pla_decode_|Equal61~2_combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_nf_we~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_nf_we~0 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_flags_nf_we~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y17_N0 +cycloneive_lcell_comb \z80_|pla_decode_|Equal73~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal73~2_combout = (\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [4] & (\z80_|execute_|ctl_state_alu~11_combout & \z80_|ir_|opcode [3]))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|execute_|ctl_state_alu~11_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal73~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal73~2 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal73~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N26 +cycloneive_lcell_comb \z80_|pla_decode_|Equal72~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal72~2_combout = (\z80_|ir_|opcode [5] & (\z80_|execute_|ctl_state_alu~11_combout & (\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [3]))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|execute_|ctl_state_alu~11_combout ), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal72~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal72~2 .lut_mask = 16'h0080; +defparam \z80_|pla_decode_|Equal72~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y20_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~1 ( +// Equation(s): +// \z80_|execute_|ctl_flags_nf_we~1_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout & (\z80_|execute_|ctl_flags_nf_we~0_combout & (!\z80_|pla_decode_|Equal73~2_combout & !\z80_|pla_decode_|Equal72~2_combout ))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ), + .datab(\z80_|execute_|ctl_flags_nf_we~0_combout ), + .datac(\z80_|pla_decode_|Equal73~2_combout ), + .datad(\z80_|pla_decode_|Equal72~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_nf_we~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_nf_we~1 .lut_mask = 16'h0008; +defparam \z80_|execute_|ctl_flags_nf_we~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_nf_we~2_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~18_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout & (\z80_|execute_|ctl_alu_core_hf~15_combout & \z80_|execute_|ctl_flags_nf_we~1_combout ))) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~15_combout ), + .datad(\z80_|execute_|ctl_flags_nf_we~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_nf_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_nf_we~2 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_flags_nf_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~5_combout = (\z80_|sequencer_|DFFE_T4_ff~q ) # ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~5 .lut_mask = 16'hFFBB; +defparam \z80_|execute_|ctl_flags_sz_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~6_combout = (\z80_|execute_|ctl_flags_sz_we~5_combout & ((\z80_|execute_|ctl_alu_core_R~0_combout ) # ((\z80_|pla_decode_|Equal48~0_combout & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) # +// (!\z80_|execute_|ctl_flags_sz_we~5_combout & (((\z80_|pla_decode_|Equal48~0_combout & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) + + .dataa(\z80_|execute_|ctl_flags_sz_we~5_combout ), + .datab(\z80_|execute_|ctl_alu_core_R~0_combout ), + .datac(\z80_|pla_decode_|Equal48~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~6 .lut_mask = 16'hF888; +defparam \z80_|execute_|ctl_flags_sz_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_nf_we~4_combout = (\z80_|execute_|ctl_flags_nf_we~3_combout ) # (((\z80_|execute_|ctl_flags_sz_we~6_combout ) # (!\z80_|execute_|ctl_flags_xy_we~14_combout )) # (!\z80_|execute_|ctl_flags_nf_we~2_combout )) + + .dataa(\z80_|execute_|ctl_flags_nf_we~3_combout ), + .datab(\z80_|execute_|ctl_flags_nf_we~2_combout ), + .datac(\z80_|execute_|ctl_flags_sz_we~6_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_nf_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_nf_we~4 .lut_mask = 16'hFBFF; +defparam \z80_|execute_|ctl_flags_nf_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N24 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~8 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~8_combout = (\z80_|execute_|ctl_flags_nf_we~4_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~7_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ))) # (!\z80_|execute_|ctl_flags_nf_we~4_combout & +// (((\z80_|alu_flags_|DFFE_inst_latch_nf~q )))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~7_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .datad(\z80_|execute_|ctl_flags_nf_we~4_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~8 .lut_mask = 16'h88F0; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y19_N25 +dffeas \z80_|alu_flags_|DFFE_inst_latch_nf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~14 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_cpl~14_combout = (\z80_|ir_|opcode [4]) # (!\z80_|pla_decode_|Equal63~0_combout ) + + .dataa(gnd), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(gnd), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_cpl~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_cpl~14 .lut_mask = 16'hFF33; +defparam \z80_|execute_|ctl_flags_hf_cpl~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_cpl~10_combout = (\z80_|execute_|ctl_flags_hf_cpl~14_combout & (!\z80_|execute_|ctl_alu_op_low~27_combout & (!\z80_|execute_|ctl_state_alu~5_combout & !\z80_|pla_decode_|Equal68~3_combout ))) + + .dataa(\z80_|execute_|ctl_flags_hf_cpl~14_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~27_combout ), + .datac(\z80_|execute_|ctl_state_alu~5_combout ), + .datad(\z80_|pla_decode_|Equal68~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_cpl~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_cpl~10 .lut_mask = 16'h0002; +defparam \z80_|execute_|ctl_flags_hf_cpl~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal45~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal45~0_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [1] & \z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~1_combout ), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal45~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal45~0 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal45~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~11 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_cpl~11_combout = (\z80_|execute_|ctl_state_alu~6_combout ) # ((\z80_|pla_decode_|Equal52~1_combout ) # ((\z80_|pla_decode_|Equal45~0_combout & !\z80_|decode_state_|use_ixiy~combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~6_combout ), + .datab(\z80_|pla_decode_|Equal45~0_combout ), + .datac(\z80_|decode_state_|use_ixiy~combout ), + .datad(\z80_|pla_decode_|Equal52~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_cpl~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_cpl~11 .lut_mask = 16'hFFAE; +defparam \z80_|execute_|ctl_flags_hf_cpl~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~12 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_cpl~12_combout = ((\z80_|execute_|ctl_alu_op_low~25_combout ) # ((\z80_|pla_decode_|Equal10~0_combout ) # (\z80_|execute_|ctl_flags_hf_cpl~11_combout ))) # (!\z80_|execute_|ctl_flags_hf_cpl~10_combout ) + + .dataa(\z80_|execute_|ctl_flags_hf_cpl~10_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~25_combout ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|execute_|ctl_flags_hf_cpl~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_cpl~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_cpl~12 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_flags_hf_cpl~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~13 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_cpl~13_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~q & (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|execute_|ctl_flags_hf_cpl~12_combout & \z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|execute_|ctl_flags_hf_cpl~12_combout ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_cpl~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_cpl~13 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_flags_hf_cpl~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y17_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~8_combout = (\z80_|execute_|ctl_alu_core_S~6_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~4_combout & (\z80_|execute_|ctl_alu_core_S~11_combout & !\z80_|execute_|ctl_alu_core_R~1_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_S~6_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), + .datac(\z80_|execute_|ctl_alu_core_S~11_combout ), + .datad(\z80_|execute_|ctl_alu_core_R~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~8 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_alu_core_S~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y20_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~9_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout & (\z80_|execute_|ctl_alu_core_S~8_combout & !\z80_|pla_decode_|Equal72~2_combout )) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_core_S~8_combout ), + .datad(\z80_|pla_decode_|Equal72~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~9 .lut_mask = 16'h00A0; +defparam \z80_|execute_|ctl_alu_core_S~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~10_combout = (((!\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ) # (!\z80_|execute_|ctl_alu_core_S~12_combout )) # (!\z80_|execute_|ctl_alu_core_R~4_combout )) # (!\z80_|execute_|ctl_alu_core_S~5_combout ) + + .dataa(\z80_|execute_|ctl_alu_core_S~5_combout ), + .datab(\z80_|execute_|ctl_alu_core_R~4_combout ), + .datac(\z80_|execute_|ctl_alu_core_S~12_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~10 .lut_mask = 16'h7FFF; +defparam \z80_|execute_|ctl_alu_core_S~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y20_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~combout = ((\z80_|execute_|ctl_alu_core_S~10_combout ) # ((\z80_|pla_decode_|Equal9~0_combout & \z80_|pla_decode_|Equal62~2_combout ))) # (!\z80_|execute_|ctl_alu_core_S~9_combout ) + + .dataa(\z80_|pla_decode_|Equal9~0_combout ), + .datab(\z80_|execute_|ctl_alu_core_S~9_combout ), + .datac(\z80_|execute_|ctl_alu_core_S~10_combout ), + .datad(\z80_|pla_decode_|Equal62~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S .lut_mask = 16'hFBF3; +defparam \z80_|execute_|ctl_alu_core_S .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N12 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[3] ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_high|Q [3] = (\z80_|alu_|db_high[3]~7_combout & (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & \z80_|execute_|ctl_alu_op1_sel_bus~15_combout )) + + .dataa(\z80_|alu_|db_high[3]~7_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [3]), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[3] .lut_mask = 16'h0A00; +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[3] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N8 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|ena~0 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ) # (\z80_|execute_|ctl_alu_op1_sel_zero~combout ) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_high|ena~0 .lut_mask = 16'hFAFA; +defparam \z80_|alu_|b2v_op1_latch_mux_high|ena~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y17_N13 +dffeas \z80_|alu_|op1_high[3] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [3]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_high [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_high[3] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_high[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N14 +cycloneive_lcell_comb \z80_|alu_|alu_op1[3]~2 ( +// Equation(s): +// \z80_|alu_|alu_op1[3]~2_combout = (\z80_|execute_|ctl_alu_op_low~41_combout & (((\z80_|alu_|op1_low [3])))) # (!\z80_|execute_|ctl_alu_op_low~41_combout & ((\z80_|execute_|ctl_alu_op_low~29_combout & (\z80_|alu_|op1_high [3])) # +// (!\z80_|execute_|ctl_alu_op_low~29_combout & ((\z80_|alu_|op1_low [3]))))) + + .dataa(\z80_|execute_|ctl_alu_op_low~41_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~29_combout ), + .datac(\z80_|alu_|op1_high [3]), + .datad(\z80_|alu_|op1_low [3]), + .cin(gnd), + .combout(\z80_|alu_|alu_op1[3]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op1[3]~2 .lut_mask = 16'hFB40; +defparam \z80_|alu_|alu_op1[3]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N12 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout = (\z80_|execute_|ctl_alu_core_S~combout ) # ((\z80_|alu_|alu_op1[3]~2_combout & \z80_|alu_|alu_op2[3]~2_combout )) + + .dataa(\z80_|execute_|ctl_alu_core_S~combout ), + .datab(gnd), + .datac(\z80_|alu_|alu_op1[3]~2_combout ), + .datad(\z80_|alu_|alu_op2[3]~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hFAAA; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we_lo~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we_lo~2_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|ir_|opcode [5])) + + .dataa(gnd), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we_lo~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we_lo~2 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_reg_sys_we_lo~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we_lo~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we_lo~3_combout = (\z80_|pla_decode_|Equal9~1_combout ) # ((\z80_|execute_|ctl_reg_sys_we_lo~2_combout ) # ((\z80_|pla_decode_|Equal8~0_combout & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal8~0_combout ), + .datab(\z80_|pla_decode_|Equal9~1_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_we_lo~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we_lo~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we_lo~3 .lut_mask = 16'hFFEC; +defparam \z80_|execute_|ctl_reg_sys_we_lo~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~14 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~14_combout = (((!\z80_|pla_decode_|Equal35~0_combout & !\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|alu_control_|flags_cond_true~q )) # (!\z80_|execute_|ixy_d~6_combout ) + + .dataa(\z80_|pla_decode_|Equal35~0_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|pla_decode_|Equal34~0_combout ), + .datad(\z80_|alu_control_|flags_cond_true~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~14 .lut_mask = 16'h37FF; +defparam \z80_|execute_|ctl_reg_sel_wz~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N8 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_hi~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_hi~0_combout = ((\z80_|execute_|ixy_d~6_combout & ((\z80_|execute_|ctl_reg_sys_we_lo~3_combout ) # (\z80_|pla_decode_|Equal19~0_combout )))) # (!\z80_|execute_|ctl_reg_sel_wz~14_combout ) + + .dataa(\z80_|execute_|ctl_reg_sys_we_lo~3_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~14_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_hi~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_hi~0 .lut_mask = 16'hC8FF; +defparam \z80_|reg_control_|reg_sys_we_hi~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N20 +cycloneive_lcell_comb \z80_|pla_decode_|Equal33~3 ( +// Equation(s): +// \z80_|pla_decode_|Equal33~3_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal33~1_combout & (\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|pla_decode_|Equal33~1_combout ), + .datac(\z80_|decode_state_|use_ixiy~combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal33~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal33~3 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal33~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we~0_combout = (\z80_|execute_|ixy_d~5_combout & ((\z80_|pla_decode_|Equal33~3_combout ) # ((\z80_|pla_decode_|Equal6~1_combout ) # (!\z80_|execute_|pc_inc_hold~26_combout )))) + + .dataa(\z80_|pla_decode_|Equal33~3_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|pla_decode_|Equal6~1_combout ), + .datad(\z80_|execute_|pc_inc_hold~26_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we~0 .lut_mask = 16'hC8CC; +defparam \z80_|execute_|ctl_reg_sys_we~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we~2_combout = (!\z80_|execute_|ctl_reg_sys_we~1_combout & (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|execute_|ctl_mWrite~17_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout ))) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|execute_|ctl_reg_sys_we~1_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datad(\z80_|execute_|ctl_mWrite~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we~2 .lut_mask = 16'h0313; +defparam \z80_|execute_|ctl_reg_sys_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we~3_combout = (\z80_|execute_|ctl_reg_sys_we~0_combout ) # (((\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ) # (!\z80_|execute_|ctl_reg_sys_we~2_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~32_combout )) + + .dataa(\z80_|execute_|ctl_reg_sys_we~0_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~32_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), + .datad(\z80_|execute_|ctl_reg_sys_we~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we~3 .lut_mask = 16'hFBFF; +defparam \z80_|execute_|ctl_reg_sys_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~4_combout = (\z80_|reg_control_|reg_sel_pc~2_combout & (\z80_|execute_|ctl_alu_oe~2_combout & (!\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout & \z80_|execute_|ctl_alu_sel_op2_neg~2_combout ))) + + .dataa(\z80_|reg_control_|reg_sel_pc~2_combout ), + .datab(\z80_|execute_|ctl_alu_oe~2_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~4 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_in_hi~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N4 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_hi ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_hi~combout = (\z80_|reg_control_|reg_sys_we_hi~0_combout ) # ((\z80_|execute_|ctl_reg_sys_we~3_combout ) # (!\z80_|execute_|ctl_reg_in_hi~4_combout )) + + .dataa(\z80_|reg_control_|reg_sys_we_hi~0_combout ), + .datab(\z80_|execute_|ctl_reg_sys_we~3_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_in_hi~4_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_hi~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_hi .lut_mask = 16'hEEFF; +defparam \z80_|reg_control_|reg_sys_we_hi .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~18 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~18_combout = (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # ((\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~18 .lut_mask = 16'hF0B0; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo~17 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo~17_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|execute_|ctl_mRead~12_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|execute_|ctl_mRead~12_combout ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo~17 .lut_mask = 16'h80C0; +defparam \z80_|execute_|ctl_reg_sys_hilo~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~11 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~11_combout = (!\z80_|execute_|ctl_reg_sys_hilo~17_combout & (((!\z80_|execute_|ctl_mRead~34_combout & !\z80_|pla_decode_|Equal10~0_combout )) # (!\z80_|execute_|ctl_mWrite~9_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~9_combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~11 .lut_mask = 16'h0057; +defparam \z80_|execute_|ctl_reg_sel_pc~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~12 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~12_combout = (\z80_|execute_|ctl_reg_sel_pc~11_combout & (((\z80_|execute_|ctl_flags_bus~1_combout & \z80_|execute_|ctl_al_we~13_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ), + .datab(\z80_|execute_|ctl_flags_bus~1_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~11_combout ), + .datad(\z80_|execute_|ctl_al_we~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~12 .lut_mask = 16'hD050; +defparam \z80_|execute_|ctl_reg_sel_pc~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~13 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~13_combout = (\z80_|execute_|setM1~54_combout & (\z80_|execute_|ctl_reg_sel_pc~12_combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|pla_decode_|Equal6~1_combout )))) + + .dataa(\z80_|execute_|setM1~54_combout ), + .datab(\z80_|pla_decode_|Equal6~1_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~12_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~13 .lut_mask = 16'h20A0; +defparam \z80_|execute_|ctl_reg_sel_pc~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout = (\z80_|execute_|ixy_d~6_combout & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|execute_|comb~0_combout & \z80_|ir_|opcode [0]))) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|pla_decode_|Equal52~0_combout ), + .datac(\z80_|execute_|comb~0_combout ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~6_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & (((!\z80_|execute_|ctl_mRead~8_combout & !\z80_|execute_|ctl_mRead~6_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~8_combout ), + .datab(\z80_|execute_|ctl_mRead~6_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~6 .lut_mask = 16'h010F; +defparam \z80_|execute_|ctl_reg_sel_wz~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~7_combout = (\z80_|execute_|ctl_reg_sel_wz~6_combout & (((!\z80_|pla_decode_|Equal34~0_combout & !\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|execute_|ctl_reg_in_hi~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal34~0_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~7 .lut_mask = 16'h3700; +defparam \z80_|execute_|ctl_reg_sel_wz~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~9_combout = (\z80_|execute_|ctl_bus_db_oe~0_combout & (\z80_|execute_|ctl_reg_in_hi~3_combout & (\z80_|execute_|ctl_reg_sel_wz~7_combout & \z80_|execute_|ctl_reg_in_hi~4_combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_oe~0_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~3_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~7_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~9 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sel_wz~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~25 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~25_combout = (!\z80_|pla_decode_|Equal35~0_combout & (!\z80_|pla_decode_|Equal24~1_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~11_combout & !\z80_|pla_decode_|Equal19~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal35~0_combout ), + .datab(\z80_|pla_decode_|Equal24~1_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~11_combout ), + .datad(\z80_|pla_decode_|Equal19~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~25 .lut_mask = 16'h0010; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~8_combout = (!\z80_|execute_|ctl_mRead~15_combout & ((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~15_combout ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal12~1_combout ), + .datad(\z80_|pla_decode_|Equal25~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~8 .lut_mask = 16'h5055; +defparam \z80_|execute_|ctl_reg_sel_wz~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~5_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout & (!\z80_|pla_decode_|Equal34~0_combout & (\z80_|execute_|ctl_reg_sel_wz~8_combout & !\z80_|execute_|ctl_mRead~7_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ), + .datab(\z80_|pla_decode_|Equal34~0_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~8_combout ), + .datad(\z80_|execute_|ctl_mRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~5 .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_al_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~4_combout = (!\z80_|execute_|ctl_mRead~2_combout & (!\z80_|execute_|ixy_d~10_combout & (!\z80_|execute_|ixy_d~16_combout & !\z80_|execute_|ctl_mRead~3_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~2_combout ), + .datab(\z80_|execute_|ixy_d~10_combout ), + .datac(\z80_|execute_|ixy_d~16_combout ), + .datad(\z80_|execute_|ctl_mRead~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~4 .lut_mask = 16'h0001; +defparam \z80_|execute_|ctl_al_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~41 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~41_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ctl_al_we~4_combout )))) + + .dataa(\z80_|pla_decode_|Equal34~0_combout ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|execute_|ctl_al_we~4_combout ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~41 .lut_mask = 16'h008C; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~10 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~10_combout = (!\z80_|execute_|ctl_ir_we~8_combout & (!\z80_|execute_|ctl_mRead~13_combout & !\z80_|execute_|ctl_ir_we~14_combout )) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_mRead~13_combout ), + .datad(\z80_|execute_|ctl_ir_we~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~10 .lut_mask = 16'h0005; +defparam \z80_|execute_|ctl_reg_sel_wz~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo~21 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo~21_combout = (\z80_|ir_|opcode [5]) # ((!\z80_|pla_decode_|Equal6~0_combout ) # (!\z80_|pla_decode_|Equal55~0_combout )) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo~21 .lut_mask = 16'hBBFF; +defparam \z80_|execute_|ctl_reg_sys_hilo~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~3 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~3_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~3 .lut_mask = 16'h7755; +defparam \z80_|execute_|ctl_inc_dec~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~22 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~22_combout = (\z80_|execute_|ctl_reg_sys_hilo~21_combout & (((\z80_|execute_|ctl_inc_dec~3_combout ) # (!\z80_|pla_decode_|Equal33~3_combout )))) # (!\z80_|execute_|ctl_reg_sys_hilo~21_combout & +// (!\z80_|execute_|ctl_alu_op_low~22_combout & ((\z80_|execute_|ctl_inc_dec~3_combout ) # (!\z80_|pla_decode_|Equal33~3_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo~21_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datac(\z80_|pla_decode_|Equal33~3_combout ), + .datad(\z80_|execute_|ctl_inc_dec~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~22 .lut_mask = 16'hBB0B; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~23 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~23_combout = (!\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout & ((\z80_|execute_|ctl_reg_sel_wz~10_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout +// )))) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~10_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~23 .lut_mask = 16'h2300; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~24 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~24_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout & (((!\z80_|pla_decode_|Equal6~1_combout & \z80_|execute_|pc_inc_hold~26_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) + + .dataa(\z80_|pla_decode_|Equal6~1_combout ), + .datab(\z80_|execute_|pc_inc_hold~26_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~24 .lut_mask = 16'h4F00; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~19 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~19_combout = (!\z80_|execute_|ctl_reg_sel_wz~8_combout & ((\z80_|execute_|ctl_state_alu~3_combout ) # ((\z80_|execute_|ctl_alu_oe~0_combout ) # (\z80_|execute_|ctl_ir_we~4_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~3_combout ), + .datab(\z80_|execute_|ctl_alu_oe~0_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~19 .lut_mask = 16'h00FE; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N28 +cycloneive_lcell_comb \z80_|execute_|fMRead~2 ( +// Equation(s): +// \z80_|execute_|fMRead~2_combout = ((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~2 .lut_mask = 16'h0AFF; +defparam \z80_|execute_|fMRead~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~20 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~20_combout = (!\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout & ((\z80_|execute_|fMRead~2_combout ) # ((\z80_|execute_|pc_inc_hold~6_combout & !\z80_|execute_|ctl_mRead~7_combout )))) + + .dataa(\z80_|execute_|pc_inc_hold~6_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ), + .datac(\z80_|execute_|ctl_mRead~7_combout ), + .datad(\z80_|execute_|fMRead~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~20 .lut_mask = 16'h3302; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~26 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~26_combout = (!\z80_|pla_decode_|Equal52~1_combout & (!\z80_|pla_decode_|Equal6~1_combout & \z80_|execute_|ctl_bus_db_oe~1_combout )) + + .dataa(\z80_|pla_decode_|Equal52~1_combout ), + .datab(\z80_|pla_decode_|Equal6~1_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~26 .lut_mask = 16'h1100; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~27 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~27_combout = (!\z80_|execute_|fMRead~2_combout & ((!\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ), + .datab(\z80_|execute_|fMRead~2_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~27 .lut_mask = 16'h1133; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~28 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~28_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~20_combout & (!\z80_|execute_|ctl_reg_sys_hilo[1]~27_combout & \z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~20_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~28 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~29 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~29_combout = (!\z80_|execute_|ctl_reg_sys_hilo[1]~41_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout & ((\z80_|execute_|ctl_al_we~5_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) + + .dataa(\z80_|execute_|ctl_al_we~5_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~41_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~29 .lut_mask = 16'h2300; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~30 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~30_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~16_combout & (\z80_|execute_|ctl_reg_sel_pc~13_combout & (\z80_|execute_|ctl_reg_sel_wz~9_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~29_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~16_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~13_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~9_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~29_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~30 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~13 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~13_combout = (\z80_|pla_decode_|Equal9~1_combout & (!\z80_|execute_|ixy_d~6_combout & ((!\z80_|execute_|ctl_reg_in_hi~2_combout )))) # (!\z80_|pla_decode_|Equal9~1_combout & (((!\z80_|pla_decode_|Equal19~0_combout )) # +// (!\z80_|execute_|ixy_d~6_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~13 .lut_mask = 16'h1537; +defparam \z80_|execute_|ctl_reg_sel_wz~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~32 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~32_combout = ((\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ) # ((\z80_|pla_decode_|Equal35~0_combout & \z80_|execute_|ixy_d~6_combout ))) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ) + + .dataa(\z80_|pla_decode_|Equal35~0_combout ), + .datab(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~32 .lut_mask = 16'hFFB3; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y19_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~33 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~33_combout = (!\z80_|ir_|opcode [3] & ((\z80_|execute_|ctl_alu_op_low~28_combout ) # ((\z80_|pla_decode_|Equal48~0_combout & \z80_|execute_|ctl_eval_cond~0_combout )))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|execute_|ctl_alu_op_low~28_combout ), + .datac(\z80_|pla_decode_|Equal48~0_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~33 .lut_mask = 16'h5444; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y19_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~34 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~34_combout = (((\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ) # (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout )) # (!\z80_|execute_|ctl_reg_out_hi~4_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~37_combout ) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~37_combout ), + .datab(\z80_|execute_|ctl_reg_out_hi~4_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~34 .lut_mask = 16'hFFF7; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~35 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~35_combout = (((\z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~13_combout )) # (!\z80_|execute_|ctl_reg_in_hi~5_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~5_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~13_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~35 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N22 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_73 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_73~combout = (\z80_|reg_control_|reg_sel_pc~combout & (\z80_|reg_control_|reg_sys_we_hi~combout & \z80_|execute_|ctl_reg_sys_hilo[1]~35_combout )) + + .dataa(\z80_|reg_control_|reg_sel_pc~combout ), + .datab(gnd), + .datac(\z80_|reg_control_|reg_sys_we_hi~combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_73 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_73 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y14_N5 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[3]~12_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_ir~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_ir~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_ir~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_ir~0 .lut_mask = 16'h0F0C; +defparam \z80_|execute_|ctl_reg_sel_ir~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_ir~1 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_ir~1_combout = (\z80_|execute_|ctl_reg_sel_ir~0_combout ) # (((\z80_|execute_|ctl_eval_cond~0_combout & !\z80_|execute_|ctl_flags_bus~0_combout )) # (!\z80_|execute_|ctl_reg_in_lo~9_combout )) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|ctl_flags_bus~0_combout ), + .datac(\z80_|execute_|ctl_reg_sel_ir~0_combout ), + .datad(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_ir~1 .lut_mask = 16'hF2FF; +defparam \z80_|execute_|ctl_reg_sel_ir~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N16 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_60 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_60~combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout & (!\z80_|reg_control_|reg_sys_we_hi~combout & \z80_|execute_|ctl_reg_sel_ir~1_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), + .datac(\z80_|reg_control_|reg_sys_we_hi~combout ), + .datad(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_60 .lut_mask = 16'h0C00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_60 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N20 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_61 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_61~combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout & (\z80_|reg_control_|reg_sys_we_hi~combout & \z80_|execute_|ctl_reg_sel_ir~1_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), + .datac(\z80_|reg_control_|reg_sys_we_hi~combout ), + .datad(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_61 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_61 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y14_N15 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[3]~12_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we_lo~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we_lo~4_combout = (\z80_|execute_|ctl_reg_sys_we_lo~3_combout & (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_M2_ff~q )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_sys_we_lo~3_combout ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we_lo~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we_lo~4 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_reg_sys_we_lo~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N22 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~combout = ((\z80_|execute_|ctl_reg_sys_we_lo~4_combout ) # ((\z80_|execute_|ctl_reg_sys_we~3_combout ) # (!\z80_|reg_control_|reg_sys_we_lo~4_combout ))) # (!\z80_|reg_control_|reg_sys_we_lo~7_combout ) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~7_combout ), + .datab(\z80_|execute_|ctl_reg_sys_we_lo~4_combout ), + .datac(\z80_|reg_control_|reg_sys_we_lo~4_combout ), + .datad(\z80_|execute_|ctl_reg_sys_we~3_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo .lut_mask = 16'hFFDF; +defparam \z80_|reg_control_|reg_sys_we_lo .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N2 +cycloneive_lcell_comb \z80_|reg_control_|reg_sw_4d_hi~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sw_4d_hi~0_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_control_|reg_sys_we_lo~combout ) # (!\z80_|execute_|ctl_reg_sel_ir~1_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ))) + + .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), + .datac(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datad(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sw_4d_hi~0 .lut_mask = 16'hA2AA; +defparam \z80_|reg_control_|reg_sw_4d_hi~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N14 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~10 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[3]~10_combout = (\z80_|reg_file_|gdfx_temp1[3]~48_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) # (!\z80_|reg_file_|gdfx_temp1[3]~48_combout & +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [3]), + .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[3]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[3]~10 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|db_hi_as[3]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N26 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~11 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[3]~11_combout = (\z80_|reg_file_|db_hi_as[3]~10_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [3]), + .datad(\z80_|reg_file_|db_hi_as[3]~10_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[3]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[3]~11 .lut_mask = 16'hF300; +defparam \z80_|reg_file_|db_hi_as[3]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N14 +cycloneive_lcell_comb \z80_|address_latch_|abusz[11] ( +// Equation(s): +// \z80_|address_latch_|abusz [11] = (\z80_|reg_file_|db_hi_as[3]~12_combout & !\z80_|resets_|clrpc~0_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[3]~12_combout ), + .datab(gnd), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [11]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[11] .lut_mask = 16'h0A0A; +defparam \z80_|address_latch_|abusz[11] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~1 ( +// Equation(s): +// \z80_|execute_|ctl_apin_mux~1_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (\z80_|sequencer_|DFFE_M2_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_apin_mux~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_apin_mux~1 .lut_mask = 16'h3232; +defparam \z80_|execute_|ctl_apin_mux~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~37 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~37_combout = (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|pla_decode_|Equal47~0_combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|pla_decode_|Equal34~0_combout )))) # (!\z80_|execute_|ctl_state_alu~2_combout +// & (((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|pla_decode_|Equal34~0_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|pla_decode_|Equal47~0_combout ), + .datac(\z80_|pla_decode_|Equal34~0_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~37 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_inc_cy~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~2 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~2_combout = (\z80_|execute_|ctl_inc_cy~37_combout & (((!\z80_|pla_decode_|Equal9~1_combout & !\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|execute_|ctl_inc_cy~37_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~2 .lut_mask = 16'h3700; +defparam \z80_|execute_|ctl_inc_dec~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~40 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~40_combout = (\z80_|pla_decode_|Equal34~0_combout & (!\z80_|execute_|ixy_d~9_combout & ((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) # (!\z80_|pla_decode_|Equal34~0_combout & +// (((!\z80_|execute_|ctl_mRead~9_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal34~0_combout ), + .datab(\z80_|pla_decode_|Equal47~0_combout ), + .datac(\z80_|execute_|ctl_mRead~9_combout ), + .datad(\z80_|execute_|ixy_d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~40 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_inc_cy~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~4 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~4_combout = (\z80_|execute_|ctl_inc_cy~40_combout & (((!\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|sequencer_|DFFE_M3_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|execute_|ctl_inc_cy~40_combout ), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~4 .lut_mask = 16'h4CCC; +defparam \z80_|execute_|ctl_inc_dec~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~5 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~5_combout = (\z80_|execute_|ctl_inc_dec~2_combout & (\z80_|execute_|ctl_inc_dec~4_combout & ((!\z80_|execute_|ixy_d~9_combout ) # (!\z80_|pla_decode_|Equal9~1_combout )))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ctl_inc_dec~2_combout ), + .datac(\z80_|execute_|ctl_inc_dec~4_combout ), + .datad(\z80_|execute_|ixy_d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~5 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_inc_dec~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~4_combout = (\z80_|execute_|ctl_inc_dec~5_combout & (((!\z80_|execute_|ctl_state_alu~2_combout & !\z80_|execute_|ctl_mRead~9_combout )) # (!\z80_|execute_|ctl_mWrite~6_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datac(\z80_|execute_|ctl_inc_dec~5_combout ), + .datad(\z80_|execute_|ctl_mRead~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~4 .lut_mask = 16'h3070; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal2~1_combout & (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [1]))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|pla_decode_|Equal2~1_combout ), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 .lut_mask = 16'h0008; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|setM1~42 ( +// Equation(s): +// \z80_|execute_|setM1~42_combout = (!\z80_|pla_decode_|Equal4~0_combout & ((!\z80_|pla_decode_|Equal8~0_combout ) # (!\z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal4~0_combout ), + .datad(\z80_|pla_decode_|Equal8~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~42 .lut_mask = 16'h050F; +defparam \z80_|execute_|setM1~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~12 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~12_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout & (!\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout & ((\z80_|execute_|setM1~42_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ), + .datab(\z80_|execute_|setM1~42_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~12 .lut_mask = 16'h0405; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~4 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~4_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|execute_|ctl_mRead~2_combout & ((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|ctl_mRead~3_combout )))) # (!\z80_|execute_|ixy_d~7_combout & +// (((!\z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|execute_|ctl_mRead~3_combout ))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ctl_mRead~3_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_mRead~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~4 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_sw_1d~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~3 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~3_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~4_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~12_combout & \z80_|execute_|ctl_sw_1d~4_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~12_combout ), + .datad(\z80_|execute_|ctl_sw_1d~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~3 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_sw_4d~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N8 +cycloneive_lcell_comb \z80_|execute_|fMRead~9 ( +// Equation(s): +// \z80_|execute_|fMRead~9_combout = (\z80_|execute_|ctl_mRead~14_combout & (((!\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ctl_state_alu~3_combout )))) # (!\z80_|execute_|ctl_mRead~14_combout & (((!\z80_|execute_|ixy_d~7_combout & +// !\z80_|execute_|ctl_state_alu~3_combout )) # (!\z80_|pla_decode_|Equal37~0_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~14_combout ), + .datab(\z80_|pla_decode_|Equal37~0_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ctl_state_alu~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~9 .lut_mask = 16'h111F; +defparam \z80_|execute_|fMRead~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N2 +cycloneive_lcell_comb \z80_|execute_|fMRead~10 ( +// Equation(s): +// \z80_|execute_|fMRead~10_combout = (\z80_|execute_|fMRead~9_combout & (((!\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ctl_state_alu~3_combout )) # (!\z80_|pla_decode_|Equal38~2_combout ))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|fMRead~9_combout ), + .datac(\z80_|pla_decode_|Equal38~2_combout ), + .datad(\z80_|execute_|ctl_state_alu~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~10 .lut_mask = 16'h0C4C; +defparam \z80_|execute_|fMRead~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|fMRead~8 ( +// Equation(s): +// \z80_|execute_|fMRead~8_combout = (\z80_|pla_decode_|Equal9~1_combout & (!\z80_|execute_|ctl_state_alu~3_combout & (!\z80_|execute_|ixy_d~7_combout ))) # (!\z80_|pla_decode_|Equal9~1_combout & (((!\z80_|execute_|ctl_state_alu~3_combout & +// !\z80_|execute_|ixy_d~7_combout )) # (!\z80_|pla_decode_|Equal29~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ctl_state_alu~3_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|pla_decode_|Equal29~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~8 .lut_mask = 16'h0357; +defparam \z80_|execute_|fMRead~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~2 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~2_combout = (\z80_|execute_|fMRead~10_combout & (\z80_|execute_|fMRead~8_combout & \z80_|execute_|ctl_reg_in_lo~9_combout )) + + .dataa(\z80_|execute_|fMRead~10_combout ), + .datab(\z80_|execute_|fMRead~8_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~2 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_sw_4d~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~11 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~11_combout = (\z80_|execute_|ctl_reg_sel_wz~8_combout & (((\z80_|execute_|ctl_reg_sel_wz~10_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|execute_|ctl_reg_sel_wz~8_combout & +// (!\z80_|execute_|ctl_alu_oe~0_combout & (!\z80_|execute_|ctl_ir_we~4_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~8_combout ), + .datab(\z80_|execute_|ctl_alu_oe~0_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~11 .lut_mask = 16'hAB0B; +defparam \z80_|execute_|ctl_reg_sel_wz~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~12 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~12_combout = (\z80_|execute_|ctl_reg_sel_wz~9_combout & \z80_|execute_|ctl_reg_sel_wz~11_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_sel_wz~9_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~12 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_reg_sel_wz~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~4 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~4_combout = (\z80_|pla_decode_|Equal9~1_combout & (!\z80_|execute_|ctl_reg_in_hi~2_combout & ((\z80_|execute_|ctl_flags_bus~1_combout ) # (!\z80_|execute_|ixy_d~6_combout )))) # (!\z80_|pla_decode_|Equal9~1_combout & +// (((\z80_|execute_|ctl_flags_bus~1_combout )) # (!\z80_|execute_|ixy_d~6_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|execute_|ctl_flags_bus~1_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~4 .lut_mask = 16'h51F3; +defparam \z80_|execute_|ctl_sw_4d~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~5 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~5_combout = (\z80_|execute_|ctl_sw_4d~3_combout & (\z80_|execute_|ctl_sw_4d~2_combout & (\z80_|execute_|ctl_reg_sel_wz~12_combout & \z80_|execute_|ctl_sw_4d~4_combout ))) + + .dataa(\z80_|execute_|ctl_sw_4d~3_combout ), + .datab(\z80_|execute_|ctl_sw_4d~2_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~12_combout ), + .datad(\z80_|execute_|ctl_sw_4d~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~5 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_sw_4d~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~14 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~14_combout = (!\z80_|execute_|ctl_mRead~5_combout & ((\z80_|ir_|opcode [2]) # ((!\z80_|ir_|opcode [1]) # (!\z80_|execute_|ctl_mWrite~4_combout )))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|execute_|ctl_mWrite~4_combout ), + .datac(\z80_|execute_|ctl_mRead~5_combout ), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~14 .lut_mask = 16'h0B0F; +defparam \z80_|execute_|ctl_al_we~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~10 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~10_combout = ((\z80_|pla_decode_|Equal33~3_combout ) # (!\z80_|execute_|ctl_al_we~5_combout )) # (!\z80_|execute_|ctl_al_we~14_combout ) + + .dataa(\z80_|execute_|ctl_al_we~14_combout ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal33~3_combout ), + .datad(\z80_|execute_|ctl_al_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~10 .lut_mask = 16'hF5FF; +defparam \z80_|execute_|ctl_al_we~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~6_combout = (\z80_|execute_|ctl_ir_we~4_combout & (((!\z80_|execute_|ctl_al_we~13_combout )) # (!\z80_|execute_|ctl_flags_bus~1_combout ))) # (!\z80_|execute_|ctl_ir_we~4_combout & (\z80_|execute_|ctl_state_alu~4_combout & +// ((!\z80_|execute_|ctl_al_we~13_combout ) # (!\z80_|execute_|ctl_flags_bus~1_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|execute_|ctl_flags_bus~1_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|ctl_al_we~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~6 .lut_mask = 16'h32FA; +defparam \z80_|execute_|ctl_al_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~7_combout = ((\z80_|execute_|ctl_al_we~6_combout ) # ((\z80_|pla_decode_|Equal35~0_combout & \z80_|execute_|ixy_d~6_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|execute_|ctl_al_we~6_combout ), + .datac(\z80_|pla_decode_|Equal35~0_combout ), + .datad(\z80_|execute_|ixy_d~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~7 .lut_mask = 16'hFDDD; +defparam \z80_|execute_|ctl_al_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~8_combout = (((!\z80_|execute_|ctl_al_we~4_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~31_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout )) # (!\z80_|execute_|ctl_alu_oe~3_combout ) + + .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~31_combout ), + .datad(\z80_|execute_|ctl_al_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~8 .lut_mask = 16'h7FFF; +defparam \z80_|execute_|ctl_al_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~9 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~9_combout = (\z80_|execute_|ctl_al_we~7_combout ) # ((\z80_|execute_|ctl_state_alu~3_combout & ((\z80_|execute_|ctl_al_we~8_combout ) # (!\z80_|execute_|setM1~47_combout )))) + + .dataa(\z80_|execute_|ctl_al_we~7_combout ), + .datab(\z80_|execute_|ctl_state_alu~3_combout ), + .datac(\z80_|execute_|setM1~47_combout ), + .datad(\z80_|execute_|ctl_al_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~9 .lut_mask = 16'hEEAE; +defparam \z80_|execute_|ctl_al_we~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~11 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~11_combout = ((\z80_|execute_|ctl_al_we~9_combout ) # ((\z80_|execute_|ctl_apin_mux~1_combout & \z80_|execute_|ctl_al_we~10_combout ))) # (!\z80_|execute_|ctl_sw_4d~5_combout ) + + .dataa(\z80_|execute_|ctl_apin_mux~1_combout ), + .datab(\z80_|execute_|ctl_sw_4d~5_combout ), + .datac(\z80_|execute_|ctl_al_we~10_combout ), + .datad(\z80_|execute_|ctl_al_we~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~11 .lut_mask = 16'hFFB3; +defparam \z80_|execute_|ctl_al_we~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~12 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~12_combout = ((\z80_|execute_|ctl_al_we~11_combout ) # ((\z80_|pla_decode_|Equal6~1_combout & \z80_|execute_|ixy_d~7_combout ))) # (!\z80_|execute_|setM1~54_combout ) + + .dataa(\z80_|execute_|setM1~54_combout ), + .datab(\z80_|pla_decode_|Equal6~1_combout ), + .datac(\z80_|execute_|ctl_al_we~11_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~12 .lut_mask = 16'hFDF5; +defparam \z80_|execute_|ctl_al_we~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y13_N15 +dffeas \z80_|address_latch_|Q[11] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [11]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [11]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[11] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N24 +cycloneive_lcell_comb \z80_|execute_|fIOWrite~0 ( +// Equation(s): +// \z80_|execute_|fIOWrite~0_combout = ((\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q ))) # (!\z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|fIOWrite~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIOWrite~0 .lut_mask = 16'h0F2F; +defparam \z80_|execute_|fIOWrite~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~8 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~8_combout = (\z80_|execute_|ctl_mWrite~6_combout & ((\z80_|execute_|ctl_mRead~9_combout ) # ((!\z80_|execute_|ctl_inc_dec~3_combout ) # (!\z80_|execute_|fIOWrite~0_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~9_combout ), + .datab(\z80_|execute_|fIOWrite~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~6_combout ), + .datad(\z80_|execute_|ctl_inc_dec~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~8 .lut_mask = 16'hB0F0; +defparam \z80_|execute_|ctl_inc_dec~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y18_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~2_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~5_combout & (\z80_|execute_|ctl_bus_inc_oe~45_combout & ((!\z80_|execute_|ctl_mWrite~17_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~45_combout ), + .datad(\z80_|execute_|ctl_mWrite~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~2 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_reg_gp_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~9 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~9_combout = ((\z80_|execute_|ctl_inc_dec~8_combout ) # ((!\z80_|execute_|ctl_reg_gp_we~2_combout & \z80_|ir_|opcode [3]))) # (!\z80_|execute_|ctl_inc_dec~12_combout ) + + .dataa(\z80_|execute_|ctl_inc_dec~12_combout ), + .datab(\z80_|execute_|ctl_inc_dec~8_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~2_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~9 .lut_mask = 16'hDFDD; +defparam \z80_|execute_|ctl_inc_dec~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N22 +cycloneive_lcell_comb \z80_|address_latch_|abusz[1] ( +// Equation(s): +// \z80_|address_latch_|abusz [1] = (\z80_|reg_file_|db_lo_as[1]~6_combout & !\z80_|resets_|clrpc~0_combout ) + + .dataa(\z80_|reg_file_|db_lo_as[1]~6_combout ), + .datab(gnd), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [1]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[1] .lut_mask = 16'h0A0A; +defparam \z80_|address_latch_|abusz[1] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y11_N23 +dffeas \z80_|address_latch_|Q[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [1]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[1] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~0 ( +// Equation(s): +// \z80_|execute_|ctl_apin_mux~0_combout = (\z80_|execute_|ctl_inc_cy~32_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~37_combout & ((!\z80_|pla_decode_|Equal19~0_combout ) # (!\z80_|execute_|ctl_alu_oe~0_combout )))) + + .dataa(\z80_|execute_|ctl_inc_cy~32_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~37_combout ), + .datac(\z80_|execute_|ctl_alu_oe~0_combout ), + .datad(\z80_|pla_decode_|Equal19~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_apin_mux~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_apin_mux~0 .lut_mask = 16'h0888; +defparam \z80_|execute_|ctl_apin_mux~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~6 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~6_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout & (\z80_|execute_|ctl_apin_mux~0_combout & ((!\z80_|pla_decode_|Equal9~1_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|pla_decode_|Equal9~1_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), + .datad(\z80_|execute_|ctl_apin_mux~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~6 .lut_mask = 16'h0700; +defparam \z80_|execute_|ctl_inc_dec~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~7 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~7_combout = (!\z80_|execute_|ctl_bus_inc_oe~42_combout ) # (!\z80_|execute_|ctl_inc_dec~5_combout ) + + .dataa(\z80_|execute_|ctl_inc_dec~5_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_bus_inc_oe~42_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~7 .lut_mask = 16'h5F5F; +defparam \z80_|execute_|ctl_inc_dec~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N6 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout = \z80_|address_latch_|Q [1] $ (((\z80_|execute_|ctl_inc_dec~9_combout ) # ((\z80_|execute_|ctl_inc_dec~7_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout )))) + + .dataa(\z80_|execute_|ctl_inc_dec~9_combout ), + .datab(\z80_|address_latch_|Q [1]), + .datac(\z80_|execute_|ctl_inc_dec~6_combout ), + .datad(\z80_|execute_|ctl_inc_dec~7_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0 .lut_mask = 16'h3363; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~21 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~21_combout = (\z80_|reg_control_|reg_sys_we_lo~6_combout & (\z80_|execute_|ctl_mRead~20_combout & ((!\z80_|execute_|ixy_d~15_combout ) # (!\z80_|sequencer_|DFFE_T3_ff~q )))) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~6_combout ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|execute_|ixy_d~15_combout ), + .datad(\z80_|execute_|ctl_mRead~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~21 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_reg_sel_wz~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~40 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[0]~40_combout = (\z80_|execute_|ctl_reg_sel_wz~20_combout ) # ((\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|M5~q & \z80_|pla_decode_|Equal9~1_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|M5~q ), + .datac(\z80_|execute_|ctl_reg_sel_wz~20_combout ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~40 .lut_mask = 16'hF8F0; +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y19_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~39 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~39_combout = (\z80_|execute_|ctl_alu_op_low~28_combout ) # ((\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|pla_decode_|Equal48~0_combout & !\z80_|sequencer_|DFFE_M1_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|execute_|ctl_alu_op_low~28_combout ), + .datac(\z80_|pla_decode_|Equal48~0_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~39 .lut_mask = 16'hCCEC; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y19_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~13 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[0]~13_combout = (((\z80_|execute_|ctl_reg_sys_hilo[1]~39_combout & \z80_|ir_|opcode [3])) # (!\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout )) # (!\z80_|execute_|ctl_reg_out_lo~9_combout ) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~39_combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~9_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~13 .lut_mask = 16'hBF3F; +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~31 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[0]~31_combout = (((\z80_|execute_|ctl_reg_sys_hilo[0]~40_combout ) # (\z80_|execute_|ctl_reg_sys_hilo[0]~13_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~21_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~21_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[0]~40_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~31 .lut_mask = 16'hFFF7; +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N12 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_63 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_63~combout = (\z80_|execute_|ctl_reg_sys_hilo[0]~31_combout & (\z80_|reg_control_|reg_sys_we_lo~combout & \z80_|execute_|ctl_reg_sel_ir~1_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~31_combout ), + .datac(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datad(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_63 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y12_N9 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[2]~9_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|setM1~49 ( +// Equation(s): +// \z80_|execute_|setM1~49_combout = (!\z80_|execute_|ctl_ir_we~11_combout & (!\z80_|pla_decode_|Equal69~0_combout & ((!\z80_|pla_decode_|Equal63~0_combout ) # (!\z80_|pla_decode_|Equal21~0_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~11_combout ), + .datab(\z80_|pla_decode_|Equal21~0_combout ), + .datac(\z80_|pla_decode_|Equal69~0_combout ), + .datad(\z80_|pla_decode_|Equal63~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~49_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~49 .lut_mask = 16'h0105; +defparam \z80_|execute_|setM1~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_sel_shift~2_combout = (!\z80_|pla_decode_|Equal20~0_combout & !\z80_|execute_|ctl_ir_we~8_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal20~0_combout ), + .datad(\z80_|execute_|ctl_ir_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~2 .lut_mask = 16'h000F; +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|setM1~50 ( +// Equation(s): +// \z80_|execute_|setM1~50_combout = (\z80_|execute_|ctl_flags_hf_cpl~10_combout & (\z80_|execute_|nextM~2_combout & (\z80_|execute_|setM1~49_combout & \z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ))) + + .dataa(\z80_|execute_|ctl_flags_hf_cpl~10_combout ), + .datab(\z80_|execute_|nextM~2_combout ), + .datac(\z80_|execute_|setM1~49_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~50_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~50 .lut_mask = 16'h8000; +defparam \z80_|execute_|setM1~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_flags_oe~0_combout = (!\z80_|execute_|ctl_iorw~11_combout & (!\z80_|execute_|ctl_mRead~4_combout & (!\z80_|execute_|ctl_ir_we~14_combout & !\z80_|execute_|ctl_ir_we~12_combout ))) + + .dataa(\z80_|execute_|ctl_iorw~11_combout ), + .datab(\z80_|execute_|ctl_mRead~4_combout ), + .datac(\z80_|execute_|ctl_ir_we~14_combout ), + .datad(\z80_|execute_|ctl_ir_we~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_oe~0 .lut_mask = 16'h0001; +defparam \z80_|execute_|ctl_flags_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~1 ( +// Equation(s): +// \z80_|execute_|ctl_flags_oe~1_combout = (\z80_|execute_|ctl_al_we~13_combout & (\z80_|execute_|ctl_flags_bus~1_combout & (\z80_|execute_|ctl_flags_oe~0_combout & !\z80_|pla_decode_|Equal13~2_combout ))) + + .dataa(\z80_|execute_|ctl_al_we~13_combout ), + .datab(\z80_|execute_|ctl_flags_bus~1_combout ), + .datac(\z80_|execute_|ctl_flags_oe~0_combout ), + .datad(\z80_|pla_decode_|Equal13~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_oe~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_oe~1 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_flags_oe~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~13 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~13_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & ((!\z80_|execute_|ctl_flags_oe~1_combout ) # (!\z80_|execute_|setM1~50_combout )))) + + .dataa(\z80_|execute_|setM1~50_combout ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|execute_|ctl_flags_oe~1_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~13 .lut_mask = 16'h004C; +defparam \z80_|execute_|ctl_reg_in_hi~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~12 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~12_combout = (!\z80_|execute_|ctl_mRead~12_combout & (!\z80_|execute_|ctl_alu_oe~1_combout & !\z80_|pla_decode_|Equal49~0_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_mRead~12_combout ), + .datac(\z80_|execute_|ctl_alu_oe~1_combout ), + .datad(\z80_|pla_decode_|Equal49~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~12 .lut_mask = 16'h0003; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~7_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal69~0_combout ) # ((!\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ) # (!\z80_|execute_|ctl_sw_1d~8_combout )))) + + .dataa(\z80_|pla_decode_|Equal69~0_combout ), + .datab(\z80_|execute_|ctl_sw_1d~8_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~7 .lut_mask = 16'hBF00; +defparam \z80_|execute_|ctl_reg_in_hi~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~13 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~13_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|execute_|ctl_state_alu~6_combout & !\z80_|pla_decode_|Equal52~1_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|pla_decode_|Equal52~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~13 .lut_mask = 16'hBBBF; +defparam \z80_|execute_|ctl_state_alu~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~6_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout & (!\z80_|execute_|ctl_reg_in_hi~13_combout & (!\z80_|execute_|ctl_reg_in_hi~7_combout & \z80_|execute_|ctl_state_alu~13_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~13_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~7_combout ), + .datad(\z80_|execute_|ctl_state_alu~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~6 .lut_mask = 16'h0100; +defparam \z80_|execute_|ctl_reg_gp_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~5_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout & (((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|pla_decode_|Equal12~1_combout ), + .datad(\z80_|pla_decode_|Equal25~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~5 .lut_mask = 16'h5155; +defparam \z80_|execute_|ctl_reg_gp_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~17 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~17_combout = ((!\z80_|execute_|ctl_mRead~2_combout & ((!\z80_|pla_decode_|Equal32~0_combout ) # (!\z80_|pla_decode_|Equal63~0_combout )))) # (!\z80_|nM1_int~2_combout ) + + .dataa(\z80_|pla_decode_|Equal63~0_combout ), + .datab(\z80_|execute_|ctl_mRead~2_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal32~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~17 .lut_mask = 16'h1F3F; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~18 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~17_combout & (\z80_|execute_|ctl_pf_sel[0]~3_combout & (\z80_|execute_|ctl_flags_pf_we~4_combout & \z80_|execute_|ctl_alu_oe~6_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~17_combout ), + .datab(\z80_|execute_|ctl_pf_sel[0]~3_combout ), + .datac(\z80_|execute_|ctl_flags_pf_we~4_combout ), + .datad(\z80_|execute_|ctl_alu_oe~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~18 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y17_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~10_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout & (((!\z80_|execute_|ctl_mRead~34_combout & !\z80_|pla_decode_|Equal21~1_combout )) # (!\z80_|execute_|ctl_mRead~9_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|execute_|ctl_mRead~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~10 .lut_mask = 16'h0155; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~9 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~9_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|pla_decode_|Equal6~1_combout )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|pla_decode_|Equal6~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~9 .lut_mask = 16'h0300; +defparam \z80_|execute_|ctl_sw_1d~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~9_combout = (!\z80_|execute_|ctl_sw_1d~9_combout & (((!\z80_|execute_|ctl_mRead~16_combout ) # (!\z80_|sequencer_|M5~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|M5~q ), + .datac(\z80_|execute_|ctl_sw_1d~9_combout ), + .datad(\z80_|execute_|ctl_mRead~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~9 .lut_mask = 16'h070F; +defparam \z80_|execute_|ctl_reg_gp_we~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~4_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~10_combout & \z80_|execute_|ctl_reg_gp_we~9_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_gp_we~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~4 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_reg_gp_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~7_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~6_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|execute_|ctl_reg_gp_we~5_combout & \z80_|execute_|ctl_reg_gp_we~4_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~5_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~7 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~3_combout = (\z80_|execute_|ctl_inc_cy~78_combout & (\z80_|execute_|ctl_bus_inc_oe~48_combout & (\z80_|execute_|ctl_bus_inc_oe~26_combout & \z80_|execute_|ctl_inc_cy~49_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~78_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~48_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~26_combout ), + .datad(\z80_|execute_|ctl_inc_cy~49_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~3 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~32 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~32_combout = (\z80_|execute_|ctl_reg_gp_we~2_combout & (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout & ((!\z80_|execute_|ixy_d~9_combout ) # (!\z80_|pla_decode_|Equal10~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~2_combout ), + .datac(\z80_|execute_|ixy_d~9_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~32 .lut_mask = 16'h004C; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~2 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~2_combout = (\z80_|execute_|nextM~2_combout & (((!\z80_|execute_|ixy_d~9_combout )) # (!\z80_|pla_decode_|Equal11~0_combout ))) # (!\z80_|execute_|nextM~2_combout & (!\z80_|execute_|ixy_d~5_combout & +// ((!\z80_|execute_|ixy_d~9_combout ) # (!\z80_|pla_decode_|Equal11~0_combout )))) + + .dataa(\z80_|execute_|nextM~2_combout ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|execute_|ixy_d~9_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~2 .lut_mask = 16'h2A3F; +defparam \z80_|execute_|ctl_sw_4u~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~3 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~3_combout = (\z80_|execute_|ctl_reg_gp_we~3_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout & \z80_|execute_|ctl_sw_4u~2_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~3_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout ), + .datac(\z80_|execute_|ctl_sw_4u~2_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~3 .lut_mask = 16'h8080; +defparam \z80_|execute_|ctl_sw_4u~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~8_combout = (\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # (((!\z80_|execute_|ctl_reg_gp_hilo[1]~15_combout ) # (!\z80_|execute_|ctl_sw_4u~3_combout )) # (!\z80_|execute_|ctl_reg_gp_we~7_combout )) + + .dataa(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datac(\z80_|execute_|ctl_sw_4u~3_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~8 .lut_mask = 16'hBFFF; +defparam \z80_|execute_|ctl_reg_gp_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~14 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~14_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~13_combout & ((\z80_|pla_decode_|Equal33~1_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~15_combout & +// !\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~13_combout ), + .datab(\z80_|pla_decode_|Equal33~1_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~15_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~14 .lut_mask = 16'h888A; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~24 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~24_combout = (\z80_|execute_|rsel3~combout & (((\z80_|nM1_int~2_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~12_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~14_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~14_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ), + .datad(\z80_|execute_|rsel3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~24 .lut_mask = 16'h5D00; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout = (\z80_|sequencer_|DFFE_M4_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & (!\z80_|pla_decode_|Equal12~1_combout & \z80_|pla_decode_|Equal25~0_combout ))) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|pla_decode_|Equal12~1_combout ), + .datad(\z80_|pla_decode_|Equal25~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~25 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~25_combout = (\z80_|execute_|ctl_ir_we~7_combout ) # ((\z80_|execute_|ctl_ir_we~15_combout ) # ((!\z80_|execute_|ctl_reg_sys_hilo~21_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~7_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~25 .lut_mask = 16'hEFFF; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~26 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~26_combout = (\z80_|execute_|ctl_state_alu~3_combout & ((\z80_|execute_|ctl_iorw~10_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ) # (\z80_|execute_|ctl_state_alu~6_combout )))) + + .dataa(\z80_|execute_|ctl_iorw~10_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|ctl_state_alu~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~26 .lut_mask = 16'hFE00; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~46 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~46_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # ((\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T2_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|nextM~2_combout ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~46 .lut_mask = 16'h0E0C; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~27 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~27_combout = ((\z80_|execute_|ctl_reg_gp_hilo[0]~46_combout ) # ((\z80_|pla_decode_|Equal6~1_combout & \z80_|execute_|ixy_d~7_combout ))) # (!\z80_|execute_|ctl_mRead~23_combout ) + + .dataa(\z80_|execute_|ctl_mRead~23_combout ), + .datab(\z80_|pla_decode_|Equal6~1_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~46_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~27 .lut_mask = 16'hFDF5; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~29 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~29_combout = (\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ) # +// (!\z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~29 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~22 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~22_combout = (\z80_|execute_|ixy_d~7_combout & (((\z80_|execute_|ctl_mWrite~6_combout ) # (\z80_|execute_|ctl_mRead~5_combout )) # (!\z80_|execute_|ctl_al_we~13_combout ))) + + .dataa(\z80_|execute_|ctl_al_we~13_combout ), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datac(\z80_|execute_|ctl_mRead~5_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~22 .lut_mask = 16'hFD00; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~23 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~23_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~22_combout ) # ((!\z80_|execute_|ctl_flags_oe~1_combout & ((\z80_|execute_|ctl_state_alu~3_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~3_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|execute_|ctl_flags_oe~1_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~23 .lut_mask = 16'hFF0B; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~31 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~31_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~24_combout ) # (((\z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ) # (\z80_|execute_|ctl_reg_gp_hilo[0]~23_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~30_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~24_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~23_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~31 .lut_mask = 16'hFFFB; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~33 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~33_combout = (\z80_|execute_|ixy_d~6_combout & (((!\z80_|pla_decode_|Equal10~0_combout & !\z80_|pla_decode_|Equal11~0_combout )))) # (!\z80_|execute_|ixy_d~6_combout & (((!\z80_|pla_decode_|Equal11~0_combout )) # +// (!\z80_|execute_|ixy_d~9_combout ))) + + .dataa(\z80_|execute_|ixy_d~9_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|pla_decode_|Equal11~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~33 .lut_mask = 16'h113F; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~26 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~26_combout = (\z80_|execute_|ctl_reg_gp_we~3_combout & (\z80_|execute_|fMRead~8_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~4_combout & \z80_|execute_|fMRead~10_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_we~3_combout ), + .datab(\z80_|execute_|fMRead~8_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), + .datad(\z80_|execute_|fMRead~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~26 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~34 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~34_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~12_combout & \z80_|execute_|ctl_reg_gp_sel[1]~26_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~12_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~34 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~25 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~25_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout & (\z80_|execute_|ctl_state_alu~13_combout & \z80_|execute_|ctl_reg_gp_sel[0]~24_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .datab(\z80_|execute_|ctl_state_alu~13_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~25 .lut_mask = 16'h4040; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~20 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~20_combout = (\z80_|execute_|ctl_reg_gp_sel~7_combout ) # ((!\z80_|execute_|ctl_reg_gp_hilo[1]~15_combout ) # (!\z80_|execute_|ctl_sw_2u~5_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_sel~7_combout ), + .datab(\z80_|execute_|ctl_sw_2u~5_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~20 .lut_mask = 16'hBBFF; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~21 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~21_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout & ((\z80_|execute_|rsel0~combout ) # ((!\z80_|execute_|setM1~50_combout & !\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) # +// (!\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout & (((!\z80_|execute_|setM1~50_combout & !\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), + .datab(\z80_|execute_|rsel0~combout ), + .datac(\z80_|execute_|setM1~50_combout ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~21 .lut_mask = 16'h888F; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~35 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~35_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ) # (((\z80_|execute_|ctl_reg_gp_hilo[0]~21_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[0]~25_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~34_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~34_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~35 .lut_mask = 16'hFFBF; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N14 +cycloneive_lcell_comb \z80_|pla_decode_|Equal2~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal2~2_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal1~7_combout & \z80_|pla_decode_|Equal32~0_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal2~0_combout ), + .datac(\z80_|pla_decode_|Equal1~7_combout ), + .datad(\z80_|pla_decode_|Equal32~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal2~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal2~2 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N14 +cycloneive_lcell_comb \z80_|pla_decode_|Equal1~6 ( +// Equation(s): +// \z80_|pla_decode_|Equal1~6_combout = (\z80_|pla_decode_|Equal1~4_combout & (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal1~5_combout & \z80_|pla_decode_|Equal1~7_combout ))) + + .dataa(\z80_|pla_decode_|Equal1~4_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|pla_decode_|Equal1~5_combout ), + .datad(\z80_|pla_decode_|Equal1~7_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal1~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal1~6 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal1~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N20 +cycloneive_lcell_comb \z80_|reg_control_|bank_exx~2 ( +// Equation(s): +// \z80_|reg_control_|bank_exx~2_combout = \z80_|reg_control_|bank_exx~q $ (((\z80_|pla_decode_|Equal1~6_combout & (\z80_|sequencer_|DFFE_T2_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )))) + + .dataa(\z80_|pla_decode_|Equal1~6_combout ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|reg_control_|bank_exx~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|reg_control_|bank_exx~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|bank_exx~2 .lut_mask = 16'hF078; +defparam \z80_|reg_control_|bank_exx~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y15_N21 +dffeas \z80_|reg_control_|bank_exx ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_control_|bank_exx~2_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_control_|bank_exx~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_control_|bank_exx .is_wysiwyg = "true"; +defparam \z80_|reg_control_|bank_exx .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N6 +cycloneive_lcell_comb \z80_|reg_control_|bank_hl_de1~0 ( +// Equation(s): +// \z80_|reg_control_|bank_hl_de1~0_combout = \z80_|reg_control_|bank_hl_de1~q $ (((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|pla_decode_|Equal2~2_combout & !\z80_|reg_control_|bank_exx~q )))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|pla_decode_|Equal2~2_combout ), + .datac(\z80_|reg_control_|bank_hl_de1~q ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_control_|bank_hl_de1~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|bank_hl_de1~0 .lut_mask = 16'hF0B4; +defparam \z80_|reg_control_|bank_hl_de1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y15_N7 +dffeas \z80_|reg_control_|bank_hl_de1 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_control_|bank_hl_de1~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_control_|bank_hl_de1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_control_|bank_hl_de1 .is_wysiwyg = "true"; +defparam \z80_|reg_control_|bank_hl_de1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~19 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout = (\z80_|execute_|ctl_sw_1d~4_combout & (((\z80_|execute_|ctl_sw_1d~8_combout & !\z80_|pla_decode_|Equal69~0_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_sw_1d~4_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|execute_|ctl_sw_1d~8_combout ), + .datad(\z80_|pla_decode_|Equal69~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~19 .lut_mask = 16'h22A2; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~28 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~28_combout = (!\z80_|execute_|ctl_reg_gp_sel~7_combout & \z80_|execute_|ctl_sw_2u~2_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_sel~7_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_sw_2u~2_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~28 .lut_mask = 16'h5050; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~29 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~29_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~28_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~27_combout & !\z80_|execute_|ctl_reg_in_hi~13_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~28_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~27_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~29 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~30 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~30_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~25_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~29_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~26_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~29_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~30 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y15_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~13 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~13_combout = (!\z80_|execute_|ctl_sw_1d~9_combout & (((!\z80_|execute_|ctl_state_alu~3_combout & !\z80_|execute_|ixy_d~7_combout )) # (!\z80_|execute_|ctl_mWrite~6_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~3_combout ), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ctl_sw_1d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~13 .lut_mask = 16'h0037; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~45 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~45_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~14_combout & ((\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ) # ((\z80_|sequencer_|DFFE_M1_ff~q ) # (\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~14_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~45 .lut_mask = 16'hAAA8; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~2_combout = (((!\z80_|execute_|ctl_mRead~9_combout & !\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal6~0_combout )) # (!\z80_|pla_decode_|Equal8~0_combout ) + + .dataa(\z80_|execute_|ctl_mRead~9_combout ), + .datab(\z80_|pla_decode_|Equal8~0_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~2 .lut_mask = 16'h3F7F; +defparam \z80_|execute_|ctl_reg_use_sp~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~3_combout = (\z80_|execute_|nextM~11_combout & (\z80_|execute_|ctl_bus_inc_oe~49_combout & (\z80_|execute_|ctl_reg_use_sp~0_combout & \z80_|execute_|ctl_reg_use_sp~2_combout ))) + + .dataa(\z80_|execute_|nextM~11_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~49_combout ), + .datac(\z80_|execute_|ctl_reg_use_sp~0_combout ), + .datad(\z80_|execute_|ctl_reg_use_sp~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~3 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_use_sp~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~14 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~14_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~13_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~45_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~6_combout & \z80_|execute_|ctl_reg_use_sp~3_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~13_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), + .datad(\z80_|execute_|ctl_reg_use_sp~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~14 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~32 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~32_combout = (\z80_|ir_|opcode [4] & (((!\z80_|execute_|ctl_reg_sys_hilo~21_combout & \z80_|execute_|ctl_state_alu~3_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|execute_|ctl_reg_sys_hilo~21_combout ), + .datad(\z80_|execute_|ctl_state_alu~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~32 .lut_mask = 16'h4C44; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~33 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~33_combout = (\z80_|execute_|ixy_d~7_combout & (((\z80_|execute_|ctl_mRead~3_combout ) # (\z80_|pla_decode_|Equal11~0_combout )))) # (!\z80_|execute_|ixy_d~7_combout & (\z80_|execute_|ixy_d~5_combout & +// ((\z80_|pla_decode_|Equal11~0_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_mRead~3_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|pla_decode_|Equal11~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~33 .lut_mask = 16'hFAC0; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~16 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~16_combout = (\z80_|execute_|setM1~57_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~15_combout & (\z80_|execute_|ctl_sw_2u~4_combout & \z80_|execute_|ctl_sw_2u~1_combout ))) + + .dataa(\z80_|execute_|setM1~57_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~15_combout ), + .datac(\z80_|execute_|ctl_sw_2u~4_combout ), + .datad(\z80_|execute_|ctl_sw_2u~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~16 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~34 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~34_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ) # ((!\z80_|execute_|ctl_reg_gp_hilo[1]~16_combout & \z80_|ir_|opcode [1])) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~16_combout ), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~34 .lut_mask = 16'hCFCC; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~35 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~35_combout = ((\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ) # (\z80_|execute_|ctl_reg_gp_sel[0]~34_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~35 .lut_mask = 16'hFFF5; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~20 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~20_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|pla_decode_|Equal4~0_combout ) # ((\z80_|pla_decode_|Equal1~4_combout & \z80_|pla_decode_|Equal2~1_combout )))) + + .dataa(\z80_|pla_decode_|Equal4~0_combout ), + .datab(\z80_|pla_decode_|Equal1~4_combout ), + .datac(\z80_|pla_decode_|Equal2~1_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~20 .lut_mask = 16'hEA00; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~21 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~21_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout ) # (\z80_|execute_|ctl_state_alu~2_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|nextM~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~21 .lut_mask = 16'h00FE; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~22 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~22_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~20_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~21_combout ) # ((\z80_|execute_|ctl_mRead~34_combout & \z80_|execute_|ctl_state_alu~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~20_combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~22 .lut_mask = 16'hFFEA; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~18 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~18_combout = (\z80_|execute_|ctl_mWrite~17_combout ) # ((\z80_|execute_|ctl_mRead~5_combout ) # ((\z80_|pla_decode_|Equal21~0_combout & \z80_|pla_decode_|Equal24~0_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~17_combout ), + .datab(\z80_|pla_decode_|Equal21~0_combout ), + .datac(\z80_|execute_|ctl_mRead~5_combout ), + .datad(\z80_|pla_decode_|Equal24~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~18 .lut_mask = 16'hFEFA; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~37 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~37_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~5_combout & (((!\z80_|execute_|ctl_mWrite~17_combout ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), + .datad(\z80_|execute_|ctl_mWrite~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~37 .lut_mask = 16'h70F0; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~19 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~19_combout = ((\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~18_combout & \z80_|execute_|ixy_d~7_combout ))) # (!\z80_|execute_|ctl_reg_gp_sel[1]~37_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~18_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~37_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~19 .lut_mask = 16'hFF8F; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~23 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~23_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~22_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ) # ((!\z80_|execute_|ctl_reg_gp_hilo[1]~16_combout & \z80_|ir_|opcode [2]))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~22_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~16_combout ), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~23 .lut_mask = 16'hEFEE; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y14_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~16 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~16_combout = (\z80_|execute_|ctl_state_alu~3_combout & (((\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout )) # (!\z80_|execute_|ctl_mRead~17_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~17_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|ctl_state_alu~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~16 .lut_mask = 16'hF700; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~17 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~17_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~16_combout ) # ((\z80_|execute_|ixy_d~15_combout & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~16_combout ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|execute_|ixy_d~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~17 .lut_mask = 16'hFECC; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~11 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~11_combout = (!\z80_|decode_state_|DFFE_instCB~q & (!\z80_|decode_state_|DFFE_instED~q & ((\z80_|sequencer_|DFFE_M4_ff~q ) # (\z80_|sequencer_|M5~q )))) + + .dataa(\z80_|decode_state_|DFFE_instCB~q ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|decode_state_|DFFE_instED~q ), + .datad(\z80_|sequencer_|M5~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~11 .lut_mask = 16'h0504; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~36 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~36_combout = (\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [2] & (\z80_|execute_|ctl_reg_gp_sel[1]~11_combout & !\z80_|ir_|opcode [4]))) + + .dataa(\z80_|ir_|opcode [1]), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~36 .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~8_combout = (\z80_|ir_|opcode [7] & (!\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|ir_|opcode [3] & \z80_|ir_|opcode [6]))) + + .dataa(\z80_|ir_|opcode [7]), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~8 .lut_mask = 16'h0200; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~9_combout = (\z80_|ir_|opcode [3] & (((\z80_|sequencer_|DFFE_T3_ff~q )))) # (!\z80_|ir_|opcode [3] & (((!\z80_|pla_decode_|Equal12~0_combout & \z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal12~0_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~9 .lut_mask = 16'hBF05; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~10 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~10_combout = (\z80_|ir_|opcode [0] & (\z80_|execute_|ctl_reg_gp_sel[1]~8_combout )) # (!\z80_|ir_|opcode [0] & (((\z80_|execute_|ctl_reg_gp_sel[1]~9_combout & \z80_|execute_|ctl_ir_we~6_combout )))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~8_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~9_combout ), + .datad(\z80_|execute_|ctl_ir_we~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~10 .lut_mask = 16'hD888; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~15 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~15_combout = (\z80_|ir_|opcode [5] & (((\z80_|execute_|ctl_reg_gp_sel[1]~36_combout & \z80_|execute_|ctl_reg_gp_sel[1]~10_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~15 .lut_mask = 16'hA222; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~31 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~31_combout = ((\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~17_combout ) # (\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ))) # (!\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~17_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~31 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N24 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~5 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_de2~5_combout = (!\z80_|decode_state_|DFFE_instIY1~q & (!\z80_|decode_state_|DFFE_inst4~q & (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & \z80_|execute_|ctl_reg_gp_sel[1]~31_combout ))) + + .dataa(\z80_|decode_state_|DFFE_instIY1~q ), + .datab(\z80_|decode_state_|DFFE_inst4~q ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_de2~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_de2~5 .lut_mask = 16'h0100; +defparam \z80_|reg_control_|reg_sel_de2~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N28 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~6 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_de2~6_combout = (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (((\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ) # (\z80_|execute_|ctl_reg_gp_sel[0]~32_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_de2~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_de2~6 .lut_mask = 16'h00FD; +defparam \z80_|reg_control_|reg_sel_de2~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N24 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_de~0_combout = (!\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de1~q & (\z80_|reg_control_|reg_sel_de2~5_combout )) # (!\z80_|reg_control_|bank_hl_de1~q & ((\z80_|reg_control_|reg_sel_de2~6_combout ))))) + + .dataa(\z80_|reg_control_|bank_hl_de1~q ), + .datab(\z80_|reg_control_|bank_exx~q ), + .datac(\z80_|reg_control_|reg_sel_de2~5_combout ), + .datad(\z80_|reg_control_|reg_sel_de2~6_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_de~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_de~0 .lut_mask = 16'h3120; +defparam \z80_|reg_control_|reg_sel_de~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N14 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_50 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_50~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout & \z80_|reg_control_|reg_sel_de~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .datad(\z80_|reg_control_|reg_sel_de~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_50 .lut_mask = 16'h5000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N22 +cycloneive_lcell_comb \z80_|reg_control_|bank_hl_de2~0 ( +// Equation(s): +// \z80_|reg_control_|bank_hl_de2~0_combout = \z80_|reg_control_|bank_hl_de2~q $ (((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|pla_decode_|Equal2~2_combout & \z80_|reg_control_|bank_exx~q )))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|pla_decode_|Equal2~2_combout ), + .datac(\z80_|reg_control_|bank_hl_de2~q ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_control_|bank_hl_de2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|bank_hl_de2~0 .lut_mask = 16'hB4F0; +defparam \z80_|reg_control_|bank_hl_de2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y15_N23 +dffeas \z80_|reg_control_|bank_hl_de2 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_control_|bank_hl_de2~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_control_|bank_hl_de2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_control_|bank_hl_de2 .is_wysiwyg = "true"; +defparam \z80_|reg_control_|bank_hl_de2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N16 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~4 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_de2~4_combout = (\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de2~q & (\z80_|reg_control_|reg_sel_de2~5_combout )) # (!\z80_|reg_control_|bank_hl_de2~q & ((\z80_|reg_control_|reg_sel_de2~6_combout ))))) + + .dataa(\z80_|reg_control_|bank_hl_de2~q ), + .datab(\z80_|reg_control_|bank_exx~q ), + .datac(\z80_|reg_control_|reg_sel_de2~5_combout ), + .datad(\z80_|reg_control_|reg_sel_de2~6_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_de2~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_de2~4 .lut_mask = 16'hC480; +defparam \z80_|reg_control_|reg_sel_de2~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N24 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_46 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_46~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout & \z80_|reg_control_|reg_sel_de2~4_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .datad(\z80_|reg_control_|reg_sel_de2~4_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_46 .lut_mask = 16'h5000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N22 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_47 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_47~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout & \z80_|reg_control_|reg_sel_de2~4_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .datad(\z80_|reg_control_|reg_sel_de2~4_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_47 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y11_N1 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N16 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_51 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_51~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout & \z80_|reg_control_|reg_sel_de~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .datad(\z80_|reg_control_|reg_sel_de~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_51 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y11_N7 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~33 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~33_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [2]), + .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~33 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[2]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N8 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_hl~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_hl~0_combout = (!\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de1~q & ((\z80_|reg_control_|reg_sel_de2~6_combout ))) # (!\z80_|reg_control_|bank_hl_de1~q & (\z80_|reg_control_|reg_sel_de2~5_combout )))) + + .dataa(\z80_|reg_control_|bank_hl_de1~q ), + .datab(\z80_|reg_control_|bank_exx~q ), + .datac(\z80_|reg_control_|reg_sel_de2~5_combout ), + .datad(\z80_|reg_control_|reg_sel_de2~6_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_hl~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_hl~0 .lut_mask = 16'h3210; +defparam \z80_|reg_control_|reg_sel_hl~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N26 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_59 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_59~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout & (\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|reg_control_|reg_sel_hl~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_59 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y12_N31 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N30 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_hl2~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_hl2~0_combout = (\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de2~q & ((\z80_|reg_control_|reg_sel_de2~6_combout ))) # (!\z80_|reg_control_|bank_hl_de2~q & (\z80_|reg_control_|reg_sel_de2~5_combout )))) + + .dataa(\z80_|reg_control_|bank_hl_de2~q ), + .datab(\z80_|reg_control_|bank_exx~q ), + .datac(\z80_|reg_control_|reg_sel_de2~5_combout ), + .datad(\z80_|reg_control_|reg_sel_de2~6_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_hl2~0 .lut_mask = 16'hC840; +defparam \z80_|reg_control_|reg_sel_hl2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N4 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_54 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_54~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout & (!\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|reg_control_|reg_sel_hl2~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_54 .lut_mask = 16'h2200; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N18 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_55 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_55~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout & (\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|reg_control_|reg_sel_hl2~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_55 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y12_N25 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N20 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_58 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_58~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout & (!\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|reg_control_|reg_sel_hl~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_58 .lut_mask = 16'h0A00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~34 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~34_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [2] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [2] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [2]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~34 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp0[2]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N2 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout & !\z80_|execute_|ctl_reg_gp_we~8_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 .lut_mask = 16'h0C0C; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N0 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout = (\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & !\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ))) + + .dataa(\z80_|reg_control_|bank_exx~q ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 .lut_mask = 16'h0020; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N22 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout & \z80_|execute_|ctl_reg_gp_we~8_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 .lut_mask = 16'hC0C0; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N18 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout = (!\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & !\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ))) + + .dataa(\z80_|reg_control_|bank_exx~q ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 .lut_mask = 16'h0010; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y14_N29 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N12 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout = (\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & !\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ))) + + .dataa(\z80_|reg_control_|bank_exx~q ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 .lut_mask = 16'h0020; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y14_N7 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N16 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout = (!\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & !\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ))) + + .dataa(\z80_|reg_control_|bank_exx~q ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 .lut_mask = 16'h0010; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~36 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~36_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [2]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [2]), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~36 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[2]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~15 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~15_combout = (((\z80_|execute_|ctl_66_oe~2_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~14_combout )) # (!\z80_|execute_|ctl_reg_in_hi~5_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~13_combout ) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~13_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~5_combout ), + .datac(\z80_|execute_|ctl_66_oe~2_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~15 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|ctl_reg_sel_wz~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~18 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~18_combout = (((\z80_|execute_|ctl_reg_sel_wz~15_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~12_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~21_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~17_combout ) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~17_combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~21_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~12_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~18 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_reg_sel_wz~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N0 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_83 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_83~combout = (\z80_|execute_|ctl_reg_sel_wz~18_combout & (\z80_|reg_control_|reg_sys_we_lo~combout & \z80_|execute_|ctl_reg_sys_hilo[0]~31_combout )) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~18_combout ), + .datab(gnd), + .datac(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_83 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_83 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y13_N5 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N8 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_82 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_82~combout = (\z80_|execute_|ctl_reg_sel_wz~18_combout & (!\z80_|reg_control_|reg_sys_we_lo~combout & \z80_|execute_|ctl_reg_sys_hilo[0]~31_combout )) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~18_combout ), + .datab(gnd), + .datac(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_82 .lut_mask = 16'h0A00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_82 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~37 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~37_combout = (\z80_|reg_file_|gdfx_temp0[2]~36_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|gdfx_temp0[2]~36_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~37 .lut_mask = 16'hC0CC; +defparam \z80_|reg_file_|gdfx_temp0[2]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N6 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & (\z80_|decode_state_|DFFE_inst4~q & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), + .datab(\z80_|decode_state_|DFFE_inst4~q ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 .lut_mask = 16'h0080; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N14 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_iy~2 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_iy~2_combout = (\z80_|decode_state_|DFFE_instIY1~q & (!\z80_|decode_state_|DFFE_inst4~q & (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & \z80_|execute_|ctl_reg_gp_sel[1]~31_combout ))) + + .dataa(\z80_|decode_state_|DFFE_instIY1~q ), + .datab(\z80_|decode_state_|DFFE_inst4~q ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_iy~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_iy~2 .lut_mask = 16'h0200; +defparam \z80_|reg_control_|reg_sel_iy~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N10 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_71 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_71~combout = (\z80_|reg_control_|reg_sel_iy~2_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout & \z80_|execute_|ctl_reg_gp_we~8_combout )) + + .dataa(gnd), + .datab(\z80_|reg_control_|reg_sel_iy~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y12_N3 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N28 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|decode_state_|DFFE_inst4~q ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|decode_state_|DFFE_inst4~q ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 .lut_mask = 16'h2000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y12_N1 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N12 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_70 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_70~combout = (\z80_|reg_control_|reg_sel_iy~2_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout & !\z80_|execute_|ctl_reg_gp_we~8_combout )) + + .dataa(gnd), + .datab(\z80_|reg_control_|reg_sel_iy~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70 .lut_mask = 16'h00C0; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~38 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~38_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (\z80_|reg_file_|b2v_latch_ix_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [2]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_iy_lo|latch [2]), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~38 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[2]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout = (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|ir_|opcode [3] & (\z80_|ir_|opcode [4] & \z80_|pla_decode_|Equal24~0_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|pla_decode_|Equal24~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~9_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|execute_|ctl_mRead~2_combout )))) # (!\z80_|pla_decode_|Equal47~0_combout +// & (((!\z80_|execute_|ixy_d~7_combout )) # (!\z80_|execute_|ctl_mRead~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal47~0_combout ), + .datab(\z80_|execute_|ctl_mRead~2_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~9 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_reg_in_hi~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~10 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~10_combout = (\z80_|execute_|ctl_reg_gp_we~7_combout & (\z80_|execute_|ctl_reg_in_hi~8_combout & \z80_|execute_|ctl_reg_in_hi~9_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_in_hi~8_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~10 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_reg_in_hi~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_lo~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_lo~8_combout = (\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ) # (((!\z80_|execute_|ctl_reg_in_hi~10_combout ) # (!\z80_|execute_|ctl_reg_in_lo~9_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~21_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~21_combout ), + .datac(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_lo~8 .lut_mask = 16'hBFFF; +defparam \z80_|execute_|ctl_reg_in_lo~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N0 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_sp_lo|latch[2]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_sp_lo|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp0[2]~42_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_sp_lo|latch[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[2]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~4_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal6~1_combout & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_M1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|pla_decode_|Equal6~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~4 .lut_mask = 16'h0D00; +defparam \z80_|execute_|ctl_reg_use_sp~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~5_combout = (\z80_|execute_|ctl_reg_use_sp~4_combout ) # ((\z80_|execute_|ctl_mRead~15_combout & ((\z80_|execute_|ctl_reg_in_hi~2_combout ) # (\z80_|execute_|ctl_state_alu~4_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~15_combout ), + .datab(\z80_|execute_|ctl_reg_use_sp~4_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~5 .lut_mask = 16'hEEEC; +defparam \z80_|execute_|ctl_reg_use_sp~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~6_combout = (\z80_|execute_|ctl_reg_use_sp~5_combout ) # ((!\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ) # (!\z80_|execute_|ctl_reg_use_sp~3_combout )) + + .dataa(\z80_|execute_|ctl_reg_use_sp~5_combout ), + .datab(\z80_|execute_|ctl_reg_use_sp~3_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~6 .lut_mask = 16'hBFBF; +defparam \z80_|execute_|ctl_reg_use_sp~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N14 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout = (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & \z80_|execute_|ctl_reg_gp_sel[1]~31_combout ))) + + .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y12_N1 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_sp_lo|latch[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~5 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~5_combout = (\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_mRead~12_combout ) # ((\z80_|pla_decode_|Equal49~0_combout ) # (!\z80_|execute_|ctl_sw_1d~8_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~12_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|execute_|ctl_sw_1d~8_combout ), + .datad(\z80_|pla_decode_|Equal49~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~5 .lut_mask = 16'hCC8C; +defparam \z80_|execute_|ctl_sw_1d~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y19_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_im_we ( +// Equation(s): +// \z80_|execute_|ctl_im_we~combout = (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_im_we~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_im_we .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_im_we .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~6 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~6_combout = (\z80_|execute_|ctl_sw_1d~4_combout & (!\z80_|execute_|ctl_sw_1d~5_combout & (\z80_|execute_|ctl_sw_2d~9_combout & !\z80_|execute_|ctl_im_we~combout ))) + + .dataa(\z80_|execute_|ctl_sw_1d~4_combout ), + .datab(\z80_|execute_|ctl_sw_1d~5_combout ), + .datac(\z80_|execute_|ctl_sw_2d~9_combout ), + .datad(\z80_|execute_|ctl_im_we~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~6 .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_sw_1d~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~7 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~7_combout = ((\z80_|execute_|ctl_66_oe~2_combout & !\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q )) # (!\z80_|execute_|ctl_sw_1d~6_combout ) + + .dataa(\z80_|execute_|ctl_66_oe~2_combout ), + .datab(\z80_|execute_|ctl_sw_1d~6_combout ), + .datac(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~7 .lut_mask = 16'h3B3B; +defparam \z80_|execute_|ctl_sw_1d~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N18 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[2]~2 ( +// Equation(s): +// \z80_|reg_file_|db_lo_ds[2]~2_combout = (\z80_|reg_file_|gdfx_temp0[2]~42_combout ) # ((!\z80_|execute_|ctl_reg_out_lo~5_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout & \z80_|execute_|ctl_reg_out_lo~7_combout ))) + + .dataa(\z80_|execute_|ctl_reg_out_lo~5_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_ds[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_ds[2]~2 .lut_mask = 16'hFF40; +defparam \z80_|reg_file_|db_lo_ds[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N8 +cycloneive_lcell_comb \z80_|alu_control_|db[2]~28 ( +// Equation(s): +// \z80_|alu_control_|db[2]~28_combout = (\z80_|reg_file_|db_lo_ds[2]~2_combout & (((!\z80_|execute_|ctl_sw_mask543_en~0_combout & \z80_|bus_control_|db[2]~13_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) + + .dataa(\z80_|execute_|ctl_sw_mask543_en~0_combout ), + .datab(\z80_|bus_control_|db[2]~13_combout ), + .datac(\z80_|execute_|ctl_sw_1d~7_combout ), + .datad(\z80_|reg_file_|db_lo_ds[2]~2_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[2]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[2]~28 .lut_mask = 16'h4F00; +defparam \z80_|alu_control_|db[2]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~11 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~11_combout = (((\z80_|execute_|ixy_d~6_combout & \z80_|pla_decode_|Equal9~1_combout )) # (!\z80_|execute_|ctl_reg_in_hi~5_combout )) # (!\z80_|execute_|ctl_reg_in_hi~6_combout ) + + .dataa(\z80_|execute_|ctl_reg_in_hi~6_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~5_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~11 .lut_mask = 16'hF777; +defparam \z80_|execute_|ctl_reg_in_hi~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~12 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~12_combout = (((\z80_|execute_|ctl_reg_in_hi~11_combout ) # (!\z80_|execute_|ctl_reg_in_hi~4_combout )) # (!\z80_|execute_|ctl_reg_in_hi~3_combout )) # (!\z80_|execute_|ctl_reg_in_hi~10_combout ) + + .dataa(\z80_|execute_|ctl_reg_in_hi~10_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~3_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~11_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~12 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|ctl_reg_in_hi~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~42 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~42_combout = ((\z80_|execute_|ctl_state_alu~3_combout & ((!\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ) # (!\z80_|execute_|setM1~48_combout )))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~34_combout ) + + .dataa(\z80_|execute_|setM1~48_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ), + .datac(\z80_|execute_|ctl_state_alu~3_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~42 .lut_mask = 16'h70FF; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~39 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~39_combout = ((\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mRead~3_combout ) # (!\z80_|execute_|ctl_al_we~14_combout )))) # (!\z80_|execute_|setM1~30_combout ) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|setM1~30_combout ), + .datac(\z80_|execute_|ctl_mRead~3_combout ), + .datad(\z80_|execute_|ctl_al_we~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~39 .lut_mask = 16'hB3BB; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~38 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~38_combout = ((!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ixy_d~5_combout ) # (\z80_|execute_|ctl_state_alu~2_combout )))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), + .datad(\z80_|execute_|nextM~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~38 .lut_mask = 16'h0FEF; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~40 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~40_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ) # ((!\z80_|execute_|rsel3~combout & !\z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ), + .datab(\z80_|execute_|rsel3~combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~40 .lut_mask = 16'hFAFB; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~41 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~41_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ) # (((!\z80_|execute_|rsel0~combout & \z80_|execute_|ctl_reg_gp_hilo[1]~20_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), + .datab(\z80_|execute_|rsel0~combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~41 .lut_mask = 16'hBFAF; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~43 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~43_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ) # (((\z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ) # (!\z80_|execute_|ctl_reg_gp_we~4_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~43 .lut_mask = 16'hFBFF; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N12 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout & !\z80_|execute_|ctl_reg_gp_we~8_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 .lut_mask = 16'h00F0; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N14 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout & (\z80_|decode_state_|DFFE_inst4~q & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .datac(\z80_|decode_state_|DFFE_inst4~q ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 .lut_mask = 16'h0080; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N30 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|execute_|ctl_reg_use_sp~6_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datac(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N14 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_68 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_68~combout = (\z80_|reg_control_|reg_sel_iy~2_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout & !\z80_|execute_|ctl_reg_gp_we~8_combout )) + + .dataa(gnd), + .datab(\z80_|reg_control_|reg_sel_iy~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68 .lut_mask = 16'h00C0; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N0 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout = (!\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) + + .dataa(\z80_|reg_control_|bank_exx~q ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 .lut_mask = 16'h0010; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N8 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout = (\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) + + .dataa(\z80_|reg_control_|bank_exx~q ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 .lut_mask = 16'h0200; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~18 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~18_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~18 .lut_mask = 16'hFEFE; +defparam \z80_|reg_file_|gdfx_temp1[0]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N26 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_80 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_80~combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout & (!\z80_|reg_control_|reg_sys_we_hi~combout & \z80_|execute_|ctl_reg_sel_wz~18_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), + .datac(\z80_|reg_control_|reg_sys_we_hi~combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~18_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_80 .lut_mask = 16'h0C00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y13_N14 +cycloneive_lcell_comb \z80_|pla_decode_|Equal21~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal21~2_combout = (\z80_|pla_decode_|Equal40~0_combout & (\z80_|pla_decode_|Equal6~0_combout & !\z80_|ir_|opcode [5])) + + .dataa(\z80_|pla_decode_|Equal40~0_combout ), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(gnd), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal21~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal21~2 .lut_mask = 16'h0088; +defparam \z80_|pla_decode_|Equal21~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N4 +cycloneive_lcell_comb \z80_|reg_control_|bank_af~0 ( +// Equation(s): +// \z80_|reg_control_|bank_af~0_combout = \z80_|reg_control_|bank_af~q $ (((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|pla_decode_|Equal32~0_combout & \z80_|pla_decode_|Equal21~2_combout )))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|pla_decode_|Equal32~0_combout ), + .datac(\z80_|reg_control_|bank_af~q ), + .datad(\z80_|pla_decode_|Equal21~2_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|bank_af~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|bank_af~0 .lut_mask = 16'hB4F0; +defparam \z80_|reg_control_|bank_af~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y13_N5 +dffeas \z80_|reg_control_|bank_af ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_control_|bank_af~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_control_|bank_af~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_control_|bank_af .is_wysiwyg = "true"; +defparam \z80_|reg_control_|bank_af .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N24 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_af~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_af~0_combout = (!\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (!\z80_|reg_control_|bank_af~q & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) + + .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datac(\z80_|reg_control_|bank_af~q ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_af~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_af~0 .lut_mask = 16'h0400; +defparam \z80_|reg_control_|reg_sel_af~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N10 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_af2~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_af2~0_combout = (!\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_control_|bank_af~q & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) + + .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datac(\z80_|reg_control_|bank_af~q ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_af2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_af2~0 .lut_mask = 16'h4000; +defparam \z80_|reg_control_|reg_sel_af2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N4 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_28 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_28~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout & (\z80_|reg_control_|reg_sel_af2~0_combout & !\z80_|execute_|ctl_reg_gp_we~8_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datab(gnd), + .datac(\z80_|reg_control_|reg_sel_af2~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_28 .lut_mask = 16'h00A0; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~17 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~17_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout & \z80_|reg_control_|reg_sel_af~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .datac(\z80_|reg_control_|reg_sel_af~0_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~17 .lut_mask = 16'hFFEA; +defparam \z80_|reg_file_|gdfx_temp1[0]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~19 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~19_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ) # ((\z80_|reg_file_|gdfx_temp1[0]~18_combout ) # (\z80_|reg_file_|gdfx_temp1[0]~17_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~18_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[0]~17_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~19 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp1[0]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N0 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_52 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_52~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout & (!\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|reg_control_|reg_sel_hl2~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_52 .lut_mask = 16'h0A00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N28 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_44 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_44~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout & \z80_|reg_control_|reg_sel_de2~4_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datad(\z80_|reg_control_|reg_sel_de2~4_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_44 .lut_mask = 16'h5000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N30 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_48 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_48~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout & \z80_|reg_control_|reg_sel_de~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datad(\z80_|reg_control_|reg_sel_de~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_48 .lut_mask = 16'h5000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N20 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_56 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_56~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout & \z80_|reg_control_|reg_sel_hl~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_56 .lut_mask = 16'h5000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~16 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~16_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~16 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp1[0]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~20 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~20_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout ) # ((\z80_|reg_file_|gdfx_temp1[0]~19_combout ) # ((\z80_|reg_file_|gdfx_temp1[0]~16_combout ) # (\z80_|execute_|ctl_sw_4u~6_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[0]~19_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~16_combout ), + .datad(\z80_|execute_|ctl_sw_4u~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~20 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp1[0]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N6 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout & \z80_|execute_|ctl_reg_gp_we~8_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 .lut_mask = 16'hF000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N4 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & (\z80_|decode_state_|DFFE_inst4~q & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), + .datab(\z80_|decode_state_|DFFE_inst4~q ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 .lut_mask = 16'h0080; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y16_N7 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N8 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_69 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_69~combout = (\z80_|reg_control_|reg_sel_iy~2_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout & \z80_|execute_|ctl_reg_gp_we~8_combout )) + + .dataa(gnd), + .datab(\z80_|reg_control_|reg_sel_iy~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y16_N25 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~34 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~34_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [2]), + .datad(\z80_|reg_file_|b2v_latch_iy_hi|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~34 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[2]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N2 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|execute_|ctl_reg_use_sp~6_combout & \z80_|execute_|ctl_reg_gp_sel[1]~31_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datac(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y15_N15 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N30 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_81 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_81~combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout & (\z80_|reg_control_|reg_sys_we_hi~combout & \z80_|execute_|ctl_reg_sel_wz~18_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), + .datac(\z80_|reg_control_|reg_sys_we_hi~combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~18_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_81 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_81 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y15_N9 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~36 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~36_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (\z80_|reg_file_|b2v_latch_wz_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [2]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [2]), + .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~36 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp1[2]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N18 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_29 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_29~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout & (\z80_|reg_control_|reg_sel_af2~0_combout & \z80_|execute_|ctl_reg_gp_we~8_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datab(gnd), + .datac(\z80_|reg_control_|reg_sel_af2~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_29 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y16_N25 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~35 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~35_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout & (\z80_|alu_|db[2]~16_combout & ((\z80_|reg_file_|b2v_latch_af2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # +// (!\z80_|execute_|ctl_reg_in_hi~12_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .datab(\z80_|alu_|db[2]~16_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~35 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[2]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N22 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout = (\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ))) + + .dataa(\z80_|reg_control_|bank_exx~q ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 .lut_mask = 16'h0200; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y16_N31 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N20 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout = (!\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ))) + + .dataa(\z80_|reg_control_|bank_exx~q ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 .lut_mask = 16'h0100; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y16_N13 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~33 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~33_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (\z80_|reg_file_|b2v_latch_bc2_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]), + .datad(\z80_|reg_file_|b2v_latch_bc_hi|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~33 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[2]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~37 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~37_combout = (\z80_|reg_file_|gdfx_temp1[2]~34_combout & (\z80_|reg_file_|gdfx_temp1[2]~36_combout & (\z80_|reg_file_|gdfx_temp1[2]~35_combout & \z80_|reg_file_|gdfx_temp1[2]~33_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[2]~34_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[2]~36_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[2]~35_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[2]~33_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~37 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[2]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N20 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_45 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_45~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout & \z80_|reg_control_|reg_sel_de2~4_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sel_de2~4_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_45 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y15_N31 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N12 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp1[2]~39_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N24 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_49 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_49~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout & \z80_|reg_control_|reg_sel_de~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datad(\z80_|reg_control_|reg_sel_de~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_49 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y15_N13 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~31 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~31_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [2]), + .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~31 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[2]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N2 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_33 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_33~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout & \z80_|reg_control_|reg_sel_af~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_33 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y15_N31 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N30 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[2]~12 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[2]~12_combout = (\z80_|execute_|ctl_reg_gp_we~8_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [2]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [2]), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[2]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[2]~12 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[2]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N26 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_57 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_57~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout & \z80_|reg_control_|reg_sel_hl~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_57 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y14_N21 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N2 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_53 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_53~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout & (\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|reg_control_|reg_sel_hl2~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_53 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y14_N7 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~32 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~32_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (\z80_|reg_file_|b2v_latch_hl_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_hl2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (((\z80_|reg_file_|b2v_latch_hl2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [2]), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~32 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[2]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~38 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~38_combout = (\z80_|reg_file_|gdfx_temp1[2]~37_combout & (\z80_|reg_file_|gdfx_temp1[2]~31_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[2]~12_combout & \z80_|reg_file_|gdfx_temp1[2]~32_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[2]~37_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[2]~31_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|db[2]~12_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[2]~32_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~38 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[2]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~11 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~11_combout = (((\z80_|execute_|ctl_inc_dec~9_combout ) # (!\z80_|execute_|ctl_inc_dec~5_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~42_combout )) # (!\z80_|execute_|ctl_inc_dec~6_combout ) + + .dataa(\z80_|execute_|ctl_inc_dec~6_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~42_combout ), + .datac(\z80_|execute_|ctl_inc_dec~5_combout ), + .datad(\z80_|execute_|ctl_inc_dec~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~11 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_inc_dec~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N8 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout = \z80_|address_latch_|Q [9] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ) + + .dataa(\z80_|address_latch_|Q [9]), + .datab(gnd), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out .lut_mask = 16'h5A5A; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y14_N31 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[1]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y17_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_sel_shift~5_combout = (\z80_|sequencer_|DFFE_T4_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|pla_decode_|Equal20~0_combout ) # (\z80_|execute_|ctl_ir_we~8_combout )))) + + .dataa(\z80_|pla_decode_|Equal20~0_combout ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|execute_|ctl_ir_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~5 .lut_mask = 16'h0C08; +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_sel_shift~3_combout = (\z80_|execute_|ctl_state_alu~4_combout ) # ((\z80_|decode_state_|DFFE_instCB~q & (\z80_|pla_decode_|Equal33~0_combout & \z80_|execute_|ctl_mWrite~5_combout ))) + + .dataa(\z80_|decode_state_|DFFE_instCB~q ), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~5_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~3 .lut_mask = 16'hFF80; +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_sel_shift~4_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ) # ((\z80_|execute_|ctl_ir_we~6_combout & (\z80_|execute_|ctl_ir_we~5_combout & \z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ))) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ), + .datab(\z80_|execute_|ctl_ir_we~6_combout ), + .datac(\z80_|execute_|ctl_ir_we~5_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~4 .lut_mask = 16'hEAAA; +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~4_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [0] & !\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) + + .dataa(\z80_|pla_decode_|Equal3~1_combout ), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~4 .lut_mask = 16'h0008; +defparam \z80_|execute_|ctl_flags_cf_cpl~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~5_combout = ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_state_alu~5_combout ) # (\z80_|execute_|ctl_alu_op_low~25_combout )))) # (!\z80_|execute_|ctl_state_alu~13_combout ) + + .dataa(\z80_|execute_|ctl_state_alu~5_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|execute_|ctl_alu_op_low~25_combout ), + .datad(\z80_|execute_|ctl_state_alu~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~5 .lut_mask = 16'h32FF; +defparam \z80_|execute_|ctl_flags_cf_cpl~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~16 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~16_combout = (\z80_|pla_decode_|Equal9~0_combout & (\z80_|pla_decode_|Equal63~0_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # (\z80_|nM1_int~2_combout )))) + + .dataa(\z80_|pla_decode_|Equal9~0_combout ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~16 .lut_mask = 16'h8880; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~6_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_flags_cf_cpl~4_combout ) # ((\z80_|execute_|ctl_flags_cf_cpl~5_combout )))) # (!\z80_|alu_flags_|DFFE_inst_latch_nf~q & +// (((\z80_|execute_|ctl_alu_sel_op2_neg~16_combout )))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .datab(\z80_|execute_|ctl_flags_cf_cpl~4_combout ), + .datac(\z80_|execute_|ctl_flags_cf_cpl~5_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~6 .lut_mask = 16'hFDA8; +defparam \z80_|execute_|ctl_flags_cf_cpl~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~7_combout = (\z80_|execute_|ctl_flags_cf_cpl~6_combout ) # ((\z80_|pla_decode_|Equal9~0_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal62~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~0_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|pla_decode_|Equal62~2_combout ), + .datad(\z80_|execute_|ctl_flags_cf_cpl~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~7 .lut_mask = 16'hFF20; +defparam \z80_|execute_|ctl_flags_cf_cpl~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y20_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~10_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ) # ((!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|execute_|ctl_alu_op_low~25_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|execute_|ctl_alu_op_low~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~10 .lut_mask = 16'hDCCC; +defparam \z80_|execute_|ctl_flags_cf_cpl~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y20_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~8_combout = (\z80_|execute_|ctl_flags_cf_cpl~10_combout ) # ((\z80_|execute_|ctl_alu_op_low~34_combout & (\z80_|execute_|ctl_alu_op_low~25_combout & \z80_|execute_|ctl_alu_op_low~22_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~34_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~25_combout ), + .datac(\z80_|execute_|ctl_flags_cf_cpl~10_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~8 .lut_mask = 16'hF8F0; +defparam \z80_|execute_|ctl_flags_cf_cpl~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ixy_d~7_combout & (!\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y20_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~42 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~42_combout = (\z80_|execute_|ctl_alu_op_low~34_combout ) # (!\z80_|execute_|ctl_alu_op_low~48_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op_low~48_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~42 .lut_mask = 16'hFF0F; +defparam \z80_|execute_|ctl_alu_op_low~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y20_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~9 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~9_combout = (\z80_|execute_|ctl_flags_cf_cpl~7_combout ) # ((\z80_|execute_|ctl_flags_cf_cpl~8_combout ) # ((\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout & \z80_|execute_|ctl_alu_op_low~42_combout ))) + + .dataa(\z80_|execute_|ctl_flags_cf_cpl~7_combout ), + .datab(\z80_|execute_|ctl_flags_cf_cpl~8_combout ), + .datac(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), + .datad(\z80_|execute_|ctl_alu_op_low~42_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~9 .lut_mask = 16'hFEEE; +defparam \z80_|execute_|ctl_flags_cf_cpl~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y17_N12 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout = (\z80_|execute_|ctl_alu_op_low~40_combout & (\z80_|pla_decode_|Equal21~1_combout & ((\z80_|execute_|ixy_d~6_combout ) # (\z80_|execute_|ctl_mRead~9_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~40_combout ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ctl_mRead~9_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 .lut_mask = 16'h8880; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y20_N24 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout = ((!\z80_|pla_decode_|Equal39~0_combout & ((!\z80_|pla_decode_|Equal40~2_combout ) # (!\z80_|ir_|opcode [5])))) # (!\z80_|execute_|ixy_d~6_combout ) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal40~2_combout ), + .datad(\z80_|pla_decode_|Equal39~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 .lut_mask = 16'h557F; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y20_N22 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout = (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout & ((\z80_|execute_|ctl_alu_op_low~37_combout ) # (\z80_|execute_|ctl_alu_op_low~38_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~37_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~38_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 .lut_mask = 16'h3232; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~18 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~18_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|pla_decode_|Equal11~0_combout & \z80_|sequencer_|DFFE_T3_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~18 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_mWrite~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N14 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1_combout = (!\z80_|execute_|ctl_mWrite~18_combout & (((!\z80_|execute_|ctl_mWrite~17_combout & !\z80_|pla_decode_|Equal61~2_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~17_combout ), + .datab(\z80_|pla_decode_|Equal61~2_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_mWrite~18_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1 .lut_mask = 16'h001F; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y20_N16 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2_combout = (\z80_|nM1_int~2_combout & (!\z80_|execute_|ctl_mRead~34_combout & ((!\z80_|pla_decode_|Equal56~0_combout ) # (!\z80_|execute_|ctl_state_alu~3_combout )))) # (!\z80_|nM1_int~2_combout & +// (((!\z80_|pla_decode_|Equal56~0_combout ) # (!\z80_|execute_|ctl_state_alu~3_combout )))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|execute_|ctl_state_alu~3_combout ), + .datad(\z80_|pla_decode_|Equal56~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2 .lut_mask = 16'h0777; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y20_N10 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3_combout = (\z80_|execute_|ctl_alu_core_R~4_combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~1_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_R~4_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~1_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~2_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3 .lut_mask = 16'h8000; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y20_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~2_combout = (\z80_|execute_|ctl_alu_op_low~37_combout & (((\z80_|execute_|ctl_mRead~34_combout & \z80_|execute_|ixy_d~6_combout )) # (!\z80_|execute_|ctl_alu_oe~4_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~37_combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ctl_alu_oe~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~2 .lut_mask = 16'h80AA; +defparam \z80_|execute_|ctl_flags_cf_cpl~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y20_N2 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~3_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~13_combout & (\z80_|execute_|ctl_alu_core_S~7_combout & !\z80_|execute_|ctl_alu_core_R~1_combout ))) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), + .datac(\z80_|execute_|ctl_alu_core_S~7_combout ), + .datad(\z80_|execute_|ctl_alu_core_R~1_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'h0080; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y20_N6 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~3_combout & (!\z80_|execute_|ctl_flags_cf_cpl~2_combout & (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0_combout ))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~3_combout ), + .datab(\z80_|execute_|ctl_flags_cf_cpl~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 .lut_mask = 16'h0200; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y20_N12 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout = (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout & (\z80_|execute_|ctl_flags_nf_we~1_combout & (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ), + .datab(\z80_|execute_|ctl_flags_nf_we~1_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 .lut_mask = 16'h0400; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_we~4_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & ((\z80_|pla_decode_|Equal11~0_combout ) # (\z80_|pla_decode_|Equal10~0_combout )))) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|pla_decode_|Equal10~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_we~4 .lut_mask = 16'h8880; +defparam \z80_|execute_|ctl_flags_cf2_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y18_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_we~2_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~38_combout ) # (!\z80_|execute_|ctl_alu_op1_sel_bus~8_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~38_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_we~2 .lut_mask = 16'hCFFF; +defparam \z80_|execute_|ctl_flags_cf2_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_we~3_combout = (\z80_|execute_|ctl_flags_cf2_we~4_combout ) # ((\z80_|execute_|ctl_flags_cf2_we~2_combout ) # ((\z80_|execute_|ixy_d~15_combout & \z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(\z80_|execute_|ctl_flags_cf2_we~4_combout ), + .datab(\z80_|execute_|ixy_d~15_combout ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|execute_|ctl_flags_cf2_we~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_we~3 .lut_mask = 16'hFFEA; +defparam \z80_|execute_|ctl_flags_cf2_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y15_N13 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N8 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_32 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_32~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout & \z80_|reg_control_|reg_sel_af~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_32~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_32 .lut_mask = 16'h4400; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y15_N21 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X35_Y15_N27 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~81 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~81_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (\z80_|reg_file_|b2v_latch_wz_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (((\z80_|reg_file_|b2v_latch_sp_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .datab(\z80_|reg_file_|b2v_latch_wz_hi|latch [6]), + .datac(\z80_|reg_file_|b2v_latch_sp_hi|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~81_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~81 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[6]~81 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N22 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~8 ( +// Equation(s): +// \z80_|alu_|db_high[2]~8_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[7]~12_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[5]~24_combout )) + + .dataa(gnd), + .datab(\z80_|alu_|db[5]~24_combout ), + .datac(\z80_|alu_|db[7]~12_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|alu_|db_high[2]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[2]~8 .lut_mask = 16'hF0CC; +defparam \z80_|alu_|db_high[2]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N28 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~9 ( +// Equation(s): +// \z80_|alu_|db_high[2]~9_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_high[2]~8_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[6]~22_combout ))) # +// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) + + .dataa(\z80_|alu_|db[6]~22_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datac(\z80_|alu_|db_high[2]~8_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[2]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[2]~9 .lut_mask = 16'hF3BB; +defparam \z80_|alu_|db_high[2]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N14 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~11 ( +// Equation(s): +// \z80_|alu_|db_high[2]~11_combout = (\z80_|bus_control_|db[4]~19_combout & (!\z80_|bus_control_|db[3]~21_combout & \z80_|bus_control_|db[5]~15_combout )) + + .dataa(gnd), + .datab(\z80_|bus_control_|db[4]~19_combout ), + .datac(\z80_|bus_control_|db[3]~21_combout ), + .datad(\z80_|bus_control_|db[5]~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[2]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[2]~11 .lut_mask = 16'h0C00; +defparam \z80_|alu_|db_high[2]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N18 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[2] ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_high|Q [2] = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & (\z80_|alu_|db_high[2]~13_combout & \z80_|execute_|ctl_alu_op1_sel_bus~15_combout )) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .datab(gnd), + .datac(\z80_|alu_|db_high[2]~13_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [2]), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[2] .lut_mask = 16'h5000; +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y17_N19 +dffeas \z80_|alu_|op1_high[2] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [2]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_high [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_high[2] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_high[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_lq ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_lq~combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ixy_d~7_combout ) # ((\z80_|execute_|ixy_d~6_combout & !\z80_|ir_|opcode [3])))) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_lq .lut_mask = 16'h88A8; +defparam \z80_|execute_|ctl_alu_op2_sel_lq .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N6 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & \z80_|alu_|db_low[2]~23_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datad(\z80_|alu_|db_low[2]~23_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2 .lut_mask = 16'hF000; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~5_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|execute_|ctl_alu_core_R~0_combout & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T3_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datad(\z80_|execute_|ctl_alu_core_R~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~5 .lut_mask = 16'hFEF0; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~6_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~5_combout ) # ((\z80_|execute_|ctl_alu_op_low~47_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~14_combout & \z80_|pla_decode_|Equal13~2_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~5_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~47_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~6 .lut_mask = 16'hFFEA; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~7_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~4_combout & (\z80_|execute_|ctl_reg_use_sp~0_combout & \z80_|execute_|nextM~11_combout )) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_use_sp~0_combout ), + .datad(\z80_|execute_|nextM~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~7 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~8_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ) # (((!\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ) # (!\z80_|execute_|ctl_alu_op1_sel_bus~14_combout )) # (!\z80_|execute_|ctl_alu_op2_sel_bus~10_combout )) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~8 .lut_mask = 16'hBFFF; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y19_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_zero ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_zero~combout = (((\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ) # (!\z80_|execute_|ctl_alu_shift_oe~38_combout )) # (!\z80_|execute_|ctl_reg_out_hi~4_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ), + .datab(\z80_|execute_|ctl_reg_out_hi~4_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~38_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_zero .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_alu_op2_sel_zero .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N10 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2_combout ) # ((\z80_|alu_|db_high[2]~13_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) + + .dataa(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2_combout ), + .datab(\z80_|alu_|db_high[2]~13_combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 .lut_mask = 16'h00EA; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N0 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|ena ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|ena~combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout ) # ((\z80_|execute_|ctl_alu_op2_sel_zero~combout ) # (\z80_|execute_|ctl_alu_op2_sel_bus~8_combout )) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|ena .lut_mask = 16'hFEFE; +defparam \z80_|alu_|b2v_op2_latch_mux_high|ena .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y18_N11 +dffeas \z80_|alu_|op2_high[2] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_high [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_high[2] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_high[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N28 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~10 ( +// Equation(s): +// \z80_|alu_|db_high[2]~10_combout = (\z80_|alu_|op1_high [2] & (((\z80_|alu_|op2_high [2]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|alu_|op1_high [2] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_high [2]) # +// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) + + .dataa(\z80_|alu_|op1_high [2]), + .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datac(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datad(\z80_|alu_|op2_high [2]), + .cin(gnd), + .combout(\z80_|alu_|db_high[2]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[2]~10 .lut_mask = 16'hBB0B; +defparam \z80_|alu_|db_high[2]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N16 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~12 ( +// Equation(s): +// \z80_|alu_|db_high[2]~12_combout = (\z80_|alu_|db_high[2]~9_combout & (\z80_|alu_|db_high[2]~10_combout & ((\z80_|alu_|db_high[2]~11_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~combout )))) + + .dataa(\z80_|alu_|db_high[2]~9_combout ), + .datab(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datac(\z80_|alu_|db_high[2]~11_combout ), + .datad(\z80_|alu_|db_high[2]~10_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[2]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[2]~12 .lut_mask = 16'hA200; +defparam \z80_|alu_|db_high[2]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N6 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~1 ( +// Equation(s): +// \z80_|alu_|db_high[3]~1_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout ) # (\z80_|alu_|db_high[3]~0_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datac(gnd), + .datad(\z80_|alu_|db_high[3]~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~1 .lut_mask = 16'hFFCC; +defparam \z80_|alu_|db_high[3]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N0 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~13 ( +// Equation(s): +// \z80_|alu_|db_high[2]~13_combout = ((\z80_|alu_|db_high[2]~12_combout & ((\z80_|execute_|ctl_alu_res_oe~3_combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout )))) # (!\z80_|alu_|db_high[3]~1_combout ) + + .dataa(\z80_|execute_|ctl_alu_res_oe~3_combout ), + .datab(\z80_|alu_|db_high[2]~12_combout ), + .datac(\z80_|alu_|db_high[3]~1_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[2]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[2]~13 .lut_mask = 16'hCF8F; +defparam \z80_|alu_|db_high[2]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y12_N29 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X31_Y12_N19 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~78 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~78_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (\z80_|reg_file_|b2v_latch_ix_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [6]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_iy_lo|latch [6]), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~78_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~78 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[6]~78 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N26 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout = (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & \z80_|execute_|ctl_reg_gp_sel[1]~31_combout ))) + + .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y12_N5 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~79 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~79_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [6] & ((\z80_|alu_control_|db[6]~22_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|alu_control_|db[6]~22_combout ) # ((!\z80_|execute_|ctl_reg_in_lo~8_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datab(\z80_|alu_control_|db[6]~22_combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [6]), + .datad(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~79_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~79 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[6]~79 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N10 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_34 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_34~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_af~0_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~35_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(gnd), + .datac(\z80_|reg_control_|reg_sel_af~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_34 .lut_mask = 16'h5000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N18 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder_combout = \z80_|reg_file_|gdfx_temp0[6]~82_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N0 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_35 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_35~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_af~0_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~35_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(gnd), + .datac(\z80_|reg_control_|reg_sel_af~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_35 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y13_N19 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N14 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_31 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_31~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout & \z80_|reg_control_|reg_sel_af2~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .datac(\z80_|reg_control_|reg_sel_af2~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_31 .lut_mask = 16'h8080; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y13_N21 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N28 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_30 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_30~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout & \z80_|reg_control_|reg_sel_af2~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .datac(\z80_|reg_control_|reg_sel_af2~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_30 .lut_mask = 16'h4040; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~75 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~75_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (\z80_|reg_file_|b2v_latch_af_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_af2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (((\z80_|reg_file_|b2v_latch_af2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datab(\z80_|reg_file_|b2v_latch_af_lo|latch [6]), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~75_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~75 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp0[6]~75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N20 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder_combout = \z80_|reg_file_|gdfx_temp0[6]~82_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y14_N21 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X32_Y14_N31 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~76 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~76_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [6]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [6]), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~76_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~76 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[6]~76 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y13_N21 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~77 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~77_combout = (\z80_|reg_file_|gdfx_temp0[6]~76_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[6]~76_combout ), + .datab(gnd), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~77_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~77 .lut_mask = 16'hA0AA; +defparam \z80_|reg_file_|gdfx_temp0[6]~77 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~80 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~80_combout = (\z80_|reg_file_|gdfx_temp0[6]~78_combout & (\z80_|reg_file_|gdfx_temp0[6]~79_combout & (\z80_|reg_file_|gdfx_temp0[6]~75_combout & \z80_|reg_file_|gdfx_temp0[6]~77_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[6]~78_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[6]~79_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[6]~75_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[6]~77_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~80 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[6]~80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y12_N1 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y12_N3 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~74 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~74_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (\z80_|reg_file_|b2v_latch_hl_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl_lo|latch [6]), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~74_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~74 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp0[6]~74 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y11_N13 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y11_N11 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~73 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~73_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [6] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [6] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [6]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~73_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~73 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp0[6]~73 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~81 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~81_combout = (\z80_|reg_file_|gdfx_temp0[6]~80_combout & (\z80_|reg_file_|gdfx_temp0[6]~74_combout & \z80_|reg_file_|gdfx_temp0[6]~73_combout )) + + .dataa(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[6]~74_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[6]~73_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~81_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~81 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|gdfx_temp0[6]~81 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~19 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~19_combout = (\z80_|execute_|ctl_sw_4u~6_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ) # (\z80_|execute_|ctl_reg_in_lo~8_combout ))) + + .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datad(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~19 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp0[0]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~18 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~18_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~18 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp0[0]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~20 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~20_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ) # ((\z80_|reg_file_|gdfx_temp0[0]~19_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ) # (\z80_|reg_file_|gdfx_temp0[0]~18_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~19_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~18_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~20 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp0[0]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~92 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~92_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout & (!\z80_|execute_|ctl_reg_gp_we~8_combout & ((\z80_|reg_control_|reg_sel_hl2~0_combout ) # (\z80_|reg_control_|reg_sel_hl~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .datab(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~92_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~92 .lut_mask = 16'h0A08; +defparam \z80_|reg_file_|gdfx_temp0[0]~92 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~21 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~21_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ) # ((\z80_|reg_file_|gdfx_temp0[0]~20_combout ) # (\z80_|reg_file_|gdfx_temp0[0]~92_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datac(\z80_|reg_file_|gdfx_temp0[0]~20_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~92_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~21 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp0[0]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N4 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_74 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_74~combout = (\z80_|reg_control_|reg_sel_pc~combout & (!\z80_|reg_control_|reg_sys_we_lo~combout & \z80_|execute_|ctl_reg_sys_hilo[0]~31_combout )) + + .dataa(\z80_|reg_control_|reg_sel_pc~combout ), + .datab(gnd), + .datac(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_74 .lut_mask = 16'h0A00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_74 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N6 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_62 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_62~combout = (\z80_|execute_|ctl_reg_sys_hilo[0]~31_combout & (!\z80_|reg_control_|reg_sys_we_lo~combout & \z80_|execute_|ctl_reg_sel_ir~1_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~31_combout ), + .datac(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datad(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_62 .lut_mask = 16'h0C00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N26 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~2 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[0]~2_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ) # ((\z80_|execute_|ctl_sw_4d~6_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~43_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .datab(\z80_|execute_|ctl_sw_4d~6_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[0]~2 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|db_lo_as[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y12_N13 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[4]~15_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X31_Y12_N9 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X32_Y12_N3 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~55 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~55_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_sp_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_iy_lo|latch [4]), + .datad(\z80_|reg_file_|b2v_latch_sp_lo|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~55_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~55 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[4]~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y12_N23 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~56 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~56_combout = (\z80_|reg_file_|gdfx_temp0[4]~55_combout & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|gdfx_temp0[4]~55_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~56_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~56 .lut_mask = 16'hC0CC; +defparam \z80_|reg_file_|gdfx_temp0[4]~56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y12_N13 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y12_N23 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~57 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~57_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [4] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [4] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [4]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~57_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~57 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp0[4]~57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y14_N5 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X32_Y14_N11 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~59 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~59_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [4]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [4]), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~59_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~59 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[4]~59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y13_N17 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X31_Y13_N31 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~58 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~58_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (\z80_|reg_file_|b2v_latch_af_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_af2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (((\z80_|reg_file_|b2v_latch_af2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datab(\z80_|reg_file_|b2v_latch_af_lo|latch [4]), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~58_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~58 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp0[4]~58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y13_N1 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~60 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~60_combout = (\z80_|reg_file_|gdfx_temp0[4]~59_combout & (\z80_|reg_file_|gdfx_temp0[4]~58_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp0[4]~59_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[4]~58_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~60_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~60 .lut_mask = 16'h8088; +defparam \z80_|reg_file_|gdfx_temp0[4]~60 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y11_N23 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X31_Y11_N17 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~53 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~53_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [4]), + .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~53_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~53 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[4]~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~54 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~54_combout = (\z80_|reg_file_|gdfx_temp0[4]~53_combout & ((\z80_|alu_control_|db[4]~32_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datab(gnd), + .datac(\z80_|alu_control_|db[4]~32_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[4]~53_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~54_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~54 .lut_mask = 16'hF500; +defparam \z80_|reg_file_|gdfx_temp0[4]~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~61 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~61_combout = (\z80_|reg_file_|gdfx_temp0[4]~56_combout & (\z80_|reg_file_|gdfx_temp0[4]~57_combout & (\z80_|reg_file_|gdfx_temp0[4]~60_combout & \z80_|reg_file_|gdfx_temp0[4]~54_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[4]~56_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[4]~57_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[4]~60_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[4]~54_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~61 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[4]~61 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~62 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~62_combout = ((\z80_|reg_file_|gdfx_temp0[4]~61_combout & ((\z80_|reg_file_|db_lo_as[4]~15_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .datac(\z80_|execute_|ctl_sw_4u~6_combout ), + .datad(\z80_|reg_file_|db_lo_as[4]~15_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~62 .lut_mask = 16'hBB3B; +defparam \z80_|reg_file_|gdfx_temp0[4]~62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N10 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_75 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_75~combout = (\z80_|reg_control_|reg_sel_pc~combout & (\z80_|reg_control_|reg_sys_we_lo~combout & \z80_|execute_|ctl_reg_sys_hilo[0]~31_combout )) + + .dataa(\z80_|reg_control_|reg_sel_pc~combout ), + .datab(gnd), + .datac(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_75 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y12_N3 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[4]~15_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N2 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~13 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[4]~13_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[4]~62_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # +// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[4]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[4]~13 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_lo_as[4]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N18 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~14 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[4]~14_combout = (\z80_|reg_file_|db_lo_as[4]~13_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_ir_lo|latch [4]), + .datab(\z80_|reg_file_|db_lo_as[4]~13_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[4]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[4]~14 .lut_mask = 16'h88CC; +defparam \z80_|reg_file_|db_lo_as[4]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N16 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout = \z80_|address_latch_|Q [4] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|address_latch_|Q [4]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out .lut_mask = 16'h0FF0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N12 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~15 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[4]~15_combout = ((\z80_|reg_file_|db_lo_as[4]~14_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .datab(\z80_|reg_file_|db_lo_as[4]~14_combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), + .datad(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[4]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[4]~15 .lut_mask = 16'hC4FF; +defparam \z80_|reg_file_|db_lo_as[4]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N12 +cycloneive_lcell_comb \z80_|address_latch_|abusz[4] ( +// Equation(s): +// \z80_|address_latch_|abusz [4] = (\z80_|reg_file_|db_lo_as[4]~15_combout & !\z80_|resets_|clrpc~0_combout ) + + .dataa(gnd), + .datab(\z80_|reg_file_|db_lo_as[4]~15_combout ), + .datac(gnd), + .datad(\z80_|resets_|clrpc~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [4]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[4] .lut_mask = 16'h00CC; +defparam \z80_|address_latch_|abusz[4] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y10_N13 +dffeas \z80_|address_latch_|Q[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [4]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[4] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N20 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout = \z80_|address_latch_|Q [5] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout & (\z80_|execute_|ctl_inc_dec~11_combout $ (\z80_|address_latch_|Q +// [4]))))) + + .dataa(\z80_|execute_|ctl_inc_dec~11_combout ), + .datab(\z80_|address_latch_|Q [4]), + .datac(\z80_|address_latch_|Q [5]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out .lut_mask = 16'h96F0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y12_N29 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[5]~18_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y12_N17 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y12_N15 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~64 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~64_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [5] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [5] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [5]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~64_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~64 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp0[5]~64 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y11_N27 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X31_Y11_N25 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~63 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~63_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [5]), + .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [5]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~63_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~63 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[5]~63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y11_N17 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N18 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[5]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_lo|latch[5]~feeder_combout = \z80_|reg_file_|gdfx_temp0[5]~72_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[5]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y11_N19 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_af_lo|latch[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~65 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~65_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [5]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [5]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~65_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~65 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[5]~65 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y12_N21 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X32_Y12_N23 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~69 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~69_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [5]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_iy_lo|latch [5]), + .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~69_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~69 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[5]~69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y13_N29 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X32_Y14_N27 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~68 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~68_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (\z80_|reg_file_|b2v_latch_ix_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_ix_lo|latch [5]), + .datac(\z80_|reg_file_|b2v_latch_bc_lo|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~68_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~68 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp0[5]~68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y13_N3 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X32_Y14_N17 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~66 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~66_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [5] & ((\z80_|alu_control_|db[5]~15_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|alu_control_|db[5]~15_combout ) # ((!\z80_|execute_|ctl_reg_in_lo~8_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datab(\z80_|alu_control_|db[5]~15_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [5]), + .datad(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~66_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~66 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[5]~66 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~67 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~67_combout = (\z80_|reg_file_|gdfx_temp0[5]~66_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [5]), + .datad(\z80_|reg_file_|gdfx_temp0[5]~66_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~67_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~67 .lut_mask = 16'hF300; +defparam \z80_|reg_file_|gdfx_temp0[5]~67 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~70 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~70_combout = (\z80_|reg_file_|gdfx_temp0[5]~65_combout & (\z80_|reg_file_|gdfx_temp0[5]~69_combout & (\z80_|reg_file_|gdfx_temp0[5]~68_combout & \z80_|reg_file_|gdfx_temp0[5]~67_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[5]~65_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[5]~69_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[5]~68_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[5]~67_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~70_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~70 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[5]~70 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~71 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~71_combout = (\z80_|reg_file_|gdfx_temp0[5]~64_combout & (\z80_|reg_file_|gdfx_temp0[5]~63_combout & \z80_|reg_file_|gdfx_temp0[5]~70_combout )) + + .dataa(\z80_|reg_file_|gdfx_temp0[5]~64_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[5]~63_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[5]~70_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~71 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|gdfx_temp0[5]~71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~72 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~72_combout = ((\z80_|reg_file_|gdfx_temp0[5]~71_combout & ((\z80_|reg_file_|db_lo_as[5]~18_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), + .datab(\z80_|reg_file_|db_lo_as[5]~18_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .datad(\z80_|execute_|ctl_sw_4u~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~72 .lut_mask = 16'h8FAF; +defparam \z80_|reg_file_|gdfx_temp0[5]~72 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y12_N7 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[5]~18_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N6 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~16 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[5]~16_combout = (\z80_|reg_file_|gdfx_temp0[5]~72_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # (!\z80_|reg_file_|gdfx_temp0[5]~72_combout & +// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .datab(\z80_|execute_|ctl_sw_4d~6_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[5]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[5]~16 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|db_lo_as[5]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N14 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~17 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[5]~17_combout = (\z80_|reg_file_|db_lo_as[5]~16_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|b2v_latch_ir_lo|latch [5]), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .datad(\z80_|reg_file_|db_lo_as[5]~16_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[5]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[5]~17 .lut_mask = 16'hCF00; +defparam \z80_|reg_file_|db_lo_as[5]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N28 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~18 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[5]~18_combout = ((\z80_|reg_file_|db_lo_as[5]~17_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), + .datac(\z80_|reg_file_|db_lo_as[5]~17_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[5]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[5]~18 .lut_mask = 16'hD5F5; +defparam \z80_|reg_file_|db_lo_as[5]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N8 +cycloneive_lcell_comb \z80_|address_latch_|abusz[5] ( +// Equation(s): +// \z80_|address_latch_|abusz [5] = (\z80_|reg_file_|db_lo_as[5]~18_combout & !\z80_|resets_|clrpc~0_combout ) + + .dataa(gnd), + .datab(\z80_|reg_file_|db_lo_as[5]~18_combout ), + .datac(gnd), + .datad(\z80_|resets_|clrpc~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [5]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[5] .lut_mask = 16'h00CC; +defparam \z80_|address_latch_|abusz[5] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y10_N9 +dffeas \z80_|address_latch_|Q[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [5]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[5] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~10 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~10_combout = (\z80_|execute_|ctl_inc_dec~9_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_inc_dec~6_combout ), + .datad(\z80_|execute_|ctl_inc_dec~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~10 .lut_mask = 16'hFF0F; +defparam \z80_|execute_|ctl_inc_dec~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N30 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout = \z80_|address_latch_|Q [5] $ ((((\z80_|execute_|ctl_inc_dec~10_combout ) # (!\z80_|execute_|ctl_inc_dec~5_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~42_combout ))) + + .dataa(\z80_|address_latch_|Q [5]), + .datab(\z80_|execute_|ctl_bus_inc_oe~42_combout ), + .datac(\z80_|execute_|ctl_inc_dec~10_combout ), + .datad(\z80_|execute_|ctl_inc_dec~5_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4 .lut_mask = 16'h5955; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N8 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout = \z80_|address_latch_|Q [4] $ ((((\z80_|execute_|ctl_inc_dec~10_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~42_combout )) # (!\z80_|execute_|ctl_inc_dec~5_combout ))) + + .dataa(\z80_|execute_|ctl_inc_dec~5_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~42_combout ), + .datac(\z80_|execute_|ctl_inc_dec~10_combout ), + .datad(\z80_|address_latch_|Q [4]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 .lut_mask = 16'h08F7; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N20 +cycloneive_lcell_comb \z80_|address_latch_|abusz[6] ( +// Equation(s): +// \z80_|address_latch_|abusz [6] = (\z80_|reg_file_|db_lo_as[6]~21_combout & !\z80_|resets_|clrpc~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|reg_file_|db_lo_as[6]~21_combout ), + .datad(\z80_|resets_|clrpc~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [6]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[6] .lut_mask = 16'h00F0; +defparam \z80_|address_latch_|abusz[6] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y10_N21 +dffeas \z80_|address_latch_|Q[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [6]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[6] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N20 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[6] ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|address [6] = \z80_|address_latch_|Q [6] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout & +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout )))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), + .datac(\z80_|address_latch_|Q [6]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[6] .lut_mask = 16'h78F0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[6] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y12_N25 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[6]~21_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X36_Y12_N11 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[6]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N10 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~19 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[6]~19_combout = (\z80_|reg_file_|gdfx_temp0[6]~82_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # (!\z80_|reg_file_|gdfx_temp0[6]~82_combout & +// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .datab(\z80_|execute_|ctl_sw_4d~6_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[6]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[6]~19 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|db_lo_as[6]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N22 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~20 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[6]~20_combout = (\z80_|reg_file_|db_lo_as[6]~19_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|b2v_latch_ir_lo|latch [6]), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .datad(\z80_|reg_file_|db_lo_as[6]~19_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[6]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[6]~20 .lut_mask = 16'hCF00; +defparam \z80_|reg_file_|db_lo_as[6]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N24 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~21 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[6]~21_combout = ((\z80_|reg_file_|db_lo_as[6]~20_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [6]) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), + .datac(\z80_|reg_file_|db_lo_as[6]~20_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[6]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[6]~21 .lut_mask = 16'hD5F5; +defparam \z80_|reg_file_|db_lo_as[6]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~82 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~82_combout = ((\z80_|reg_file_|gdfx_temp0[6]~81_combout & ((\z80_|reg_file_|db_lo_as[6]~21_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[6]~81_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .datad(\z80_|reg_file_|db_lo_as[6]~21_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~82 .lut_mask = 16'hCF4F; +defparam \z80_|reg_file_|gdfx_temp0[6]~82 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N10 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[6]~0 ( +// Equation(s): +// \z80_|reg_file_|db_lo_ds[6]~0_combout = (\z80_|reg_file_|gdfx_temp0[6]~82_combout ) # ((!\z80_|execute_|ctl_reg_out_lo~5_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout & \z80_|execute_|ctl_reg_out_lo~7_combout ))) + + .dataa(\z80_|execute_|ctl_reg_out_lo~5_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_ds[6]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_ds[6]~0 .lut_mask = 16'hFF40; +defparam \z80_|reg_file_|db_lo_ds[6]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N28 +cycloneive_lcell_comb \z80_|sw1_|db_down[6]~1 ( +// Equation(s): +// \z80_|sw1_|db_down[6]~1_combout = ((\z80_|bus_control_|db[6]~9_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ) + + .dataa(gnd), + .datab(\z80_|bus_control_|db[6]~9_combout ), + .datac(\z80_|execute_|ctl_sw_1d~7_combout ), + .datad(\z80_|execute_|ctl_sw_mask543_en~0_combout ), + .cin(gnd), + .combout(\z80_|sw1_|db_down[6]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sw1_|db_down[6]~1 .lut_mask = 16'h0FCF; +defparam \z80_|sw1_|db_down[6]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_66_oe ( +// Equation(s): +// \z80_|execute_|ctl_66_oe~combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & \z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(\z80_|pla_decode_|Equal47~0_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_66_oe~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_66_oe .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_66_oe .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N24 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[1] ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_high|Q [1] = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & \z80_|alu_|db_high[1]~19_combout )) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .datad(\z80_|alu_|db_high[1]~19_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [1]), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[1] .lut_mask = 16'h0A00; +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[1] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y17_N25 +dffeas \z80_|alu_|op1_high[1] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [1]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_high [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_high[1] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_high[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N8 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~4 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~4_combout = (\z80_|alu_|db_low[1]~12_combout & \z80_|execute_|ctl_alu_op2_sel_lq~combout ) + + .dataa(gnd), + .datab(\z80_|alu_|db_low[1]~12_combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~4 .lut_mask = 16'hC0C0; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N16 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~4_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~8_combout & \z80_|alu_|db_high[1]~19_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .datab(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~4_combout ), + .datac(\z80_|alu_|db_high[1]~19_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5 .lut_mask = 16'h00EC; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y18_N17 +dffeas \z80_|alu_|op2_high[1] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_high [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_high[1] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_high[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N18 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~2 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~2_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [1]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [1])))) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datab(\z80_|alu_|op1_high [1]), + .datac(\z80_|execute_|ctl_alu_op_low~combout ), + .datad(\z80_|alu_|op1_low [1]), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~2 .lut_mask = 16'hA808; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N14 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~3 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~3_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~2_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~8_combout & \z80_|alu_|db_low[1]~12_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datac(\z80_|alu_|db_low[1]~12_combout ), + .datad(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~3 .lut_mask = 16'h3320; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y18_N15 +dffeas \z80_|alu_|op2_low[1] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_low [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_low[1] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_low[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N16 +cycloneive_lcell_comb \z80_|alu_|alu_op2[1]~1 ( +// Equation(s): +// \z80_|alu_|alu_op2[1]~1_combout = \z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_high [1])) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_low [1]))))) + + .dataa(\z80_|alu_|op2_high [1]), + .datab(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), + .datad(\z80_|alu_|op2_low [1]), + .cin(gnd), + .combout(\z80_|alu_|alu_op2[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op2[1]~1 .lut_mask = 16'h4B78; +defparam \z80_|alu_|alu_op2[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N0 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout = (!\z80_|alu_|alu_op2[1]~1_combout & ((\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_low [1])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_high +// [1]))))) + + .dataa(\z80_|alu_|op1_low [1]), + .datab(\z80_|alu_|op1_high [1]), + .datac(\z80_|execute_|ctl_alu_op_low~combout ), + .datad(\z80_|alu_|alu_op2[1]~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'h0053; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N30 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout = (\z80_|alu_|alu_op2[1]~1_combout & ((\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [1])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [1]))))) + + .dataa(\z80_|alu_|op1_low [1]), + .datab(\z80_|alu_|op1_high [1]), + .datac(\z80_|execute_|ctl_alu_op_low~combout ), + .datad(\z80_|alu_|alu_op2[1]~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0 .lut_mask = 16'hAC00; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N14 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout = (\z80_|execute_|ctl_alu_core_S~combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_core_S~combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'hFFF0; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y20_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~5_combout = (\z80_|execute_|ctl_alu_core_S~8_combout & (\z80_|execute_|ctl_alu_core_R~4_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout & !\z80_|pla_decode_|Equal72~2_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_S~8_combout ), + .datab(\z80_|execute_|ctl_alu_core_R~4_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ), + .datad(\z80_|pla_decode_|Equal72~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~5 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_alu_core_R~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~2 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~2_combout = (\z80_|execute_|ctl_mWrite~4_combout & (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal8~0_combout ) # (\z80_|pla_decode_|Equal55~0_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~4_combout ), + .datab(\z80_|pla_decode_|Equal8~0_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~2 .lut_mask = 16'hA080; +defparam \z80_|execute_|ctl_alu_core_R~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y20_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~combout = (((\z80_|pla_decode_|Equal73~2_combout ) # (\z80_|execute_|ctl_alu_core_R~2_combout )) # (!\z80_|execute_|ctl_alu_core_S~9_combout )) # (!\z80_|execute_|ctl_alu_core_R~4_combout ) + + .dataa(\z80_|execute_|ctl_alu_core_R~4_combout ), + .datab(\z80_|execute_|ctl_alu_core_S~9_combout ), + .datac(\z80_|pla_decode_|Equal73~2_combout ), + .datad(\z80_|execute_|ctl_alu_core_R~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R .lut_mask = 16'hFFF7; +defparam \z80_|execute_|ctl_alu_core_R .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N8 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~20 ( +// Equation(s): +// \z80_|alu_|db_high[0]~20_combout = ((!\z80_|bus_control_|db[3]~21_combout & (\z80_|bus_control_|db[5]~15_combout & !\z80_|bus_control_|db[4]~19_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) + + .dataa(\z80_|bus_control_|db[3]~21_combout ), + .datab(\z80_|bus_control_|db[5]~15_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datad(\z80_|bus_control_|db[4]~19_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~20 .lut_mask = 16'h0F4F; +defparam \z80_|alu_|db_high[0]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N26 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[0] ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_high|Q [0] = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & \z80_|alu_|db_high[0]~25_combout )) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .datad(\z80_|alu_|db_high[0]~25_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [0]), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[0] .lut_mask = 16'h0A00; +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[0] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y17_N27 +dffeas \z80_|alu_|op1_high[0] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [0]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_high [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_high[0] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_high[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N30 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~21 ( +// Equation(s): +// \z80_|alu_|db_high[0]~21_combout = (\z80_|execute_|ctl_alu_op1_oe~1_combout & (\z80_|alu_|op1_high [0] & ((\z80_|alu_|op2_high [0]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout & (((\z80_|alu_|op2_high +// [0]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datab(\z80_|alu_|op1_high [0]), + .datac(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datad(\z80_|alu_|op2_high [0]), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~21 .lut_mask = 16'hDD0D; +defparam \z80_|alu_|db_high[0]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N2 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~22 ( +// Equation(s): +// \z80_|alu_|db_high[0]~22_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[5]~24_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[3]~20_combout )) + + .dataa(gnd), + .datab(\z80_|alu_|db[3]~20_combout ), + .datac(\z80_|alu_|db[5]~24_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~22 .lut_mask = 16'hF0CC; +defparam \z80_|alu_|db_high[0]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N20 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~23 ( +// Equation(s): +// \z80_|alu_|db_high[0]~23_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_high[0]~22_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[4]~18_combout )) + + .dataa(\z80_|alu_|db[4]~18_combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .datac(gnd), + .datad(\z80_|alu_|db_high[0]~22_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~23 .lut_mask = 16'hEE22; +defparam \z80_|alu_|db_high[0]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N26 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~24 ( +// Equation(s): +// \z80_|alu_|db_high[0]~24_combout = (\z80_|alu_|db_high[0]~20_combout & (\z80_|alu_|db_high[0]~21_combout & ((\z80_|alu_|db_high[0]~23_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) + + .dataa(\z80_|alu_|db_high[0]~20_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datac(\z80_|alu_|db_high[0]~21_combout ), + .datad(\z80_|alu_|db_high[0]~23_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~24 .lut_mask = 16'hA020; +defparam \z80_|alu_|db_high[0]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N4 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~4 ( +// Equation(s): +// \z80_|alu_|db_low[0]~4_combout = ((!\z80_|bus_control_|db[3]~21_combout & (!\z80_|bus_control_|db[5]~15_combout & !\z80_|bus_control_|db[4]~19_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) + + .dataa(\z80_|bus_control_|db[3]~21_combout ), + .datab(\z80_|bus_control_|db[5]~15_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datad(\z80_|bus_control_|db[4]~19_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~4 .lut_mask = 16'h0F1F; +defparam \z80_|alu_|db_low[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y18_N27 +dffeas \z80_|alu_|result_lo[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_alu_op_low~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|result_lo [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|result_lo[0] .is_wysiwyg = "true"; +defparam \z80_|alu_|result_lo[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N20 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~2 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~2_combout = (\z80_|alu_|db_low[0]~24_combout & ((\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ) # ((\z80_|alu_|db_high[0]~25_combout & \z80_|execute_|ctl_alu_op1_sel_low~combout )))) # +// (!\z80_|alu_|db_low[0]~24_combout & (\z80_|alu_|db_high[0]~25_combout & ((\z80_|execute_|ctl_alu_op1_sel_low~combout )))) + + .dataa(\z80_|alu_|db_low[0]~24_combout ), + .datab(\z80_|alu_|db_high[0]~25_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~2 .lut_mask = 16'hECA0; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N0 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~3 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~3_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .datad(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~3 .lut_mask = 16'h0F00; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y17_N1 +dffeas \z80_|alu_|op1_low[0] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_low [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_low[0] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_low[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N24 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~5 ( +// Equation(s): +// \z80_|alu_|db_low[0]~5_combout = (\z80_|execute_|ctl_alu_op1_oe~1_combout & (\z80_|alu_|op1_low [0] & ((\z80_|alu_|op2_low [0]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout & (((\z80_|alu_|op2_low [0]) # +// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datab(\z80_|alu_|op1_low [0]), + .datac(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datad(\z80_|alu_|op2_low [0]), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~5 .lut_mask = 16'hDD0D; +defparam \z80_|alu_|db_low[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N26 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~6 ( +// Equation(s): +// \z80_|alu_|db_low[0]~6_combout = (\z80_|alu_|db_low[0]~4_combout & (\z80_|alu_|db_low[0]~5_combout & ((\z80_|execute_|ctl_alu_res_oe~3_combout ) # (\z80_|alu_|result_lo [0])))) + + .dataa(\z80_|execute_|ctl_alu_res_oe~3_combout ), + .datab(\z80_|alu_|db_low[0]~4_combout ), + .datac(\z80_|alu_|result_lo [0]), + .datad(\z80_|alu_|db_low[0]~5_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~6 .lut_mask = 16'hC800; +defparam \z80_|alu_|db_low[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N30 +cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~1 ( +// Equation(s): +// \z80_|alu_control_|b2v_inst_shift_mux|out~1_combout = (\z80_|ir_|opcode [5] & (\z80_|alu_|db[7]~12_combout & (\z80_|ir_|opcode [3]))) # (!\z80_|ir_|opcode [5] & ((\z80_|ir_|opcode [3] & ((\z80_|alu_|db[0]~14_combout ))) # (!\z80_|ir_|opcode [3] & +// (\z80_|alu_|db[7]~12_combout )))) + + .dataa(\z80_|alu_|db[7]~12_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|alu_|db[0]~14_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~1 .lut_mask = 16'hB282; +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_we~2_combout = (\z80_|execute_|ctl_flags_hf_we~5_combout & (\z80_|execute_|ctl_flags_xy_we~13_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_state_alu~6_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~6_combout ), + .datab(\z80_|execute_|ctl_flags_hf_we~5_combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~13_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_we~2 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_flags_hf_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~3_combout = (\z80_|execute_|ctl_flags_hf2_we~combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((!\z80_|execute_|ctl_flags_bus~1_combout ) # (!\z80_|execute_|ctl_flags_bus~0_combout )))) + + .dataa(\z80_|execute_|ctl_flags_bus~0_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_flags_hf2_we~combout ), + .datad(\z80_|execute_|ctl_flags_bus~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~3 .lut_mask = 16'hF4FC; +defparam \z80_|execute_|ctl_flags_cf_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~4_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # ((\z80_|execute_|ixy_d~6_combout & \z80_|execute_|ctl_mRead~34_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~4 .lut_mask = 16'hFFEA; +defparam \z80_|execute_|ctl_flags_cf_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~5_combout = ((\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # (\z80_|execute_|ctl_flags_cf_we~4_combout ))) # (!\z80_|execute_|ctl_flags_cf_we~7_combout ) + + .dataa(\z80_|execute_|ctl_flags_cf_we~7_combout ), + .datab(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .datad(\z80_|execute_|ctl_flags_cf_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~5 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_flags_cf_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~6_combout = (((\z80_|execute_|ctl_flags_cf_we~3_combout ) # (\z80_|execute_|ctl_flags_cf_we~5_combout )) # (!\z80_|execute_|ctl_flags_hf_we~2_combout )) # (!\z80_|execute_|ctl_flags_cf_we~2_combout ) + + .dataa(\z80_|execute_|ctl_flags_cf_we~2_combout ), + .datab(\z80_|execute_|ctl_flags_hf_we~2_combout ), + .datac(\z80_|execute_|ctl_flags_cf_we~3_combout ), + .datad(\z80_|execute_|ctl_flags_cf_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~6 .lut_mask = 16'hFFF7; +defparam \z80_|execute_|ctl_flags_cf_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N16 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~0 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf~0_combout = (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & (\z80_|execute_|ctl_flags_bus~combout & ((\z80_|alu_control_|db[0]~12_combout )))) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout +// & ((\z80_|execute_|ctl_flags_alu~15_combout ) # ((\z80_|execute_|ctl_flags_bus~combout & \z80_|alu_control_|db[0]~12_combout )))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), + .datab(\z80_|execute_|ctl_flags_bus~combout ), + .datac(\z80_|execute_|ctl_flags_alu~15_combout ), + .datad(\z80_|alu_control_|db[0]~12_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~0 .lut_mask = 16'hDC50; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N18 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~1 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf~1_combout = (\z80_|execute_|ctl_flags_cf_we~6_combout & ((\z80_|execute_|ctl_flags_cf2_we~3_combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf~q ))) # (!\z80_|execute_|ctl_flags_cf2_we~3_combout & +// (\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout )))) # (!\z80_|execute_|ctl_flags_cf_we~6_combout & (((\z80_|alu_flags_|DFFE_inst_latch_cf~q )))) + + .dataa(\z80_|execute_|ctl_flags_cf_we~6_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), + .datad(\z80_|execute_|ctl_flags_cf2_we~3_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~1 .lut_mask = 16'hF0D8; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y18_N19 +dffeas \z80_|alu_flags_|DFFE_inst_latch_cf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N4 +cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~0 ( +// Equation(s): +// \z80_|alu_control_|b2v_inst_shift_mux|out~0_combout = (\z80_|ir_|opcode [4] & ((\z80_|ir_|opcode [5] & ((!\z80_|ir_|opcode [3]))) # (!\z80_|ir_|opcode [5] & (\z80_|alu_flags_|DFFE_inst_latch_cf~q )))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~0 .lut_mask = 16'h20A8; +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N8 +cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~2 ( +// Equation(s): +// \z80_|alu_control_|b2v_inst_shift_mux|out~2_combout = (\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ) # ((\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout & !\z80_|ir_|opcode [4])) + + .dataa(\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ), + .datab(\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ), + .datac(\z80_|ir_|opcode [4]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~2 .lut_mask = 16'hCECE; +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N14 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~2 ( +// Equation(s): +// \z80_|alu_|db_low[0]~2_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[1]~10_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ))) + + .dataa(\z80_|alu_|db[1]~10_combout ), + .datab(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), + .datac(gnd), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~2 .lut_mask = 16'hAACC; +defparam \z80_|alu_|db_low[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N20 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~3 ( +// Equation(s): +// \z80_|alu_|db_low[0]~3_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_low[0]~2_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[0]~14_combout )))) # +// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .datac(\z80_|alu_|db_low[0]~2_combout ), + .datad(\z80_|alu_|db[0]~14_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~3 .lut_mask = 16'hF7D5; +defparam \z80_|alu_|db_low[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N16 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~24 ( +// Equation(s): +// \z80_|alu_|db_low[0]~24_combout = (\z80_|alu_|db_low[0]~6_combout & ((\z80_|alu_|db_low[0]~3_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~43_combout & !\z80_|alu_|db_high[3]~0_combout )))) # (!\z80_|alu_|db_low[0]~6_combout & +// (((!\z80_|execute_|ctl_alu_shift_oe~43_combout & !\z80_|alu_|db_high[3]~0_combout )))) + + .dataa(\z80_|alu_|db_low[0]~6_combout ), + .datab(\z80_|alu_|db_low[0]~3_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datad(\z80_|alu_|db_high[3]~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~24 .lut_mask = 16'h888F; +defparam \z80_|alu_|db_low[0]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N2 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~0 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~0_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [0]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [0])))) + + .dataa(\z80_|execute_|ctl_alu_op_low~combout ), + .datab(\z80_|alu_|op1_high [0]), + .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datad(\z80_|alu_|op1_low [0]), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~0 .lut_mask = 16'hE040; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N4 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~1 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~1_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~0_combout ) # ((\z80_|alu_|db_low[0]~24_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) + + .dataa(\z80_|alu_|db_low[0]~24_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .datad(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~1 .lut_mask = 16'h3320; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y18_N5 +dffeas \z80_|alu_|op2_low[0] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_low [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_low[0] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_low[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N6 +cycloneive_lcell_comb \z80_|alu_|alu_op2[0]~3 ( +// Equation(s): +// \z80_|alu_|alu_op2[0]~3_combout = \z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_high [0])) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_low [0]))))) + + .dataa(\z80_|alu_|op2_high [0]), + .datab(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), + .datad(\z80_|alu_|op2_low [0]), + .cin(gnd), + .combout(\z80_|alu_|alu_op2[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op2[0]~3 .lut_mask = 16'h4B78; +defparam \z80_|alu_|alu_op2[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N0 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout = ((!\z80_|execute_|ctl_alu_core_S~combout & !\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout )) # (!\z80_|execute_|ctl_alu_core_R~5_combout ) + + .dataa(\z80_|execute_|ctl_alu_core_S~combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_core_R~5_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 .lut_mask = 16'h0F5F; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla26M3T5_8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla26M3T5_8~combout = (\z80_|sequencer_|DFFE_T5_ff~q & (\z80_|pla_decode_|Equal21~1_combout & \z80_|sequencer_|DFFE_M3_ff~q )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T5_ff~q ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla26M3T5_8~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla26M3T5_8 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla26M3T5_8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~14 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~14_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla26M3T5_8~combout ) # ((\z80_|sequencer_|DFFE_T3_ff~q & (!\z80_|sequencer_|DFFE_T2_ff~q & \z80_|execute_|ixy_d~15_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla26M3T5_8~combout ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|execute_|ixy_d~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~14 .lut_mask = 16'hCECC; +defparam \z80_|execute_|ctl_alu_core_hf~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~16 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~16_combout = ((\z80_|execute_|ctl_alu_core_hf~14_combout ) # (!\z80_|execute_|ctl_alu_core_hf~15_combout )) # (!\z80_|execute_|ctl_alu_core_hf~12_combout ) + + .dataa(\z80_|execute_|ctl_alu_core_hf~12_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_core_hf~15_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~16 .lut_mask = 16'hFF5F; +defparam \z80_|execute_|ctl_alu_core_hf~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~13 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~13_combout = (\z80_|pla_decode_|Equal21~1_combout & ((\z80_|execute_|ctl_mRead~9_combout ) # ((!\z80_|execute_|ixy_d~5_combout & \z80_|execute_|ixy_d~6_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ctl_mRead~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~13 .lut_mask = 16'hCC40; +defparam \z80_|execute_|ctl_alu_core_hf~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~17 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~17_combout = (\z80_|execute_|ctl_alu_core_hf~16_combout & (((\z80_|execute_|ctl_alu_core_hf~13_combout & !\z80_|execute_|ctl_alu_op_low~40_combout )) # (!\z80_|execute_|ctl_alu_op_low~41_combout ))) # +// (!\z80_|execute_|ctl_alu_core_hf~16_combout & (\z80_|execute_|ctl_alu_core_hf~13_combout & ((!\z80_|execute_|ctl_alu_op_low~40_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~16_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~13_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~41_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~40_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~17 .lut_mask = 16'h0ACE; +defparam \z80_|execute_|ctl_alu_core_hf~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y20_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~44 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~44_combout = (\z80_|execute_|ctl_alu_op_low~38_combout ) # ((\z80_|execute_|ctl_alu_op_low~42_combout ) # ((\z80_|execute_|ctl_alu_op_low~36_combout ) # (!\z80_|execute_|ctl_alu_op_low~31_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~38_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~42_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~31_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~36_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~44 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|ctl_alu_op_low~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~20 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~20_combout = (\z80_|execute_|ctl_mRead~34_combout & ((\z80_|execute_|ctl_mRead~9_combout ) # ((!\z80_|execute_|ixy_d~5_combout & \z80_|execute_|ixy_d~6_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ctl_mRead~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~20 .lut_mask = 16'hCC40; +defparam \z80_|execute_|ctl_alu_core_hf~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y17_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~21 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~21_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ) # ((\z80_|execute_|ctl_alu_core_hf~20_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|execute_|ctl_mRead~34_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~21 .lut_mask = 16'hBFAA; +defparam \z80_|execute_|ctl_alu_core_hf~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~18 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~18_combout = (\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (((!\z80_|pla_decode_|Equal32~0_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal63~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal63~0_combout ), + .datab(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|pla_decode_|Equal32~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~18 .lut_mask = 16'h4CCC; +defparam \z80_|execute_|ctl_alu_core_hf~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~19 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~19_combout = (\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # ((\z80_|execute_|ctl_alu_core_hf~18_combout & !\z80_|execute_|ctl_flags_cf2_sel_daa~combout ))) + + .dataa(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~18_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~19 .lut_mask = 16'hEEFE; +defparam \z80_|execute_|ctl_alu_core_hf~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y20_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~22 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~22_combout = (\z80_|execute_|ctl_alu_op_low~37_combout & (!\z80_|execute_|ctl_alu_op_low~42_combout & ((\z80_|execute_|ctl_alu_core_hf~19_combout )))) # (!\z80_|execute_|ctl_alu_op_low~37_combout & +// ((\z80_|execute_|ctl_alu_core_hf~21_combout ) # ((!\z80_|execute_|ctl_alu_op_low~42_combout & \z80_|execute_|ctl_alu_core_hf~19_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~37_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~42_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~21_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~22 .lut_mask = 16'h7350; +defparam \z80_|execute_|ctl_alu_core_hf~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~43 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~43_combout = ((\z80_|execute_|ctl_alu_op_low~28_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ) # (!\z80_|execute_|ctl_state_alu~12_combout ))) # (!\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~28_combout ), + .datac(\z80_|execute_|ctl_state_alu~12_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~43 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|ctl_alu_op_low~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y20_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~24 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~24_combout = (\z80_|execute_|ctl_state_alu~2_combout & (\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|execute_|ctl_state_alu~2_combout & (\z80_|execute_|ixy_d~7_combout & ((\z80_|pla_decode_|Equal11~0_combout ) # +// (\z80_|pla_decode_|Equal10~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|execute_|ctl_state_alu~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~24 .lut_mask = 16'hAAC8; +defparam \z80_|execute_|ctl_alu_core_hf~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y20_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~25 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~25_combout = (!\z80_|execute_|ctl_alu_op_low~28_combout & (!\z80_|execute_|ctl_mWrite~18_combout & ((\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # (\z80_|execute_|ctl_alu_core_hf~24_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~28_combout ), + .datab(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .datac(\z80_|execute_|ctl_mWrite~18_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~25 .lut_mask = 16'h0504; +defparam \z80_|execute_|ctl_alu_core_hf~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~35 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~35_combout = (\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|execute_|ctl_alu_op_low~25_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|execute_|ctl_alu_op_low~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~35 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_core_hf~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y20_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~23 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~23_combout = (!\z80_|execute_|ctl_alu_op_low~34_combout & ((\z80_|execute_|ctl_alu_core_hf~35_combout ) # ((\z80_|execute_|ixy_d~7_combout & \z80_|execute_|ctl_alu_op_low~24_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~34_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~35_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~23 .lut_mask = 16'h5450; +defparam \z80_|execute_|ctl_alu_core_hf~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~26 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~26_combout = (!\z80_|execute_|ctl_alu_shift_oe~15_combout & (((\z80_|decode_state_|use_ixiy~combout ) # (!\z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|pla_decode_|Equal45~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal45~0_combout ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~26 .lut_mask = 16'h00DF; +defparam \z80_|execute_|ctl_alu_core_hf~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~34 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~34_combout = (\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|execute_|ctl_mRead~4_combout & ((\z80_|execute_|ctl_state_alu~4_combout )))) # (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M2_ff~q ) # +// ((\z80_|execute_|ctl_mRead~4_combout & \z80_|execute_|ctl_state_alu~4_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|execute_|ctl_mRead~4_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~34 .lut_mask = 16'hDC50; +defparam \z80_|execute_|ctl_alu_core_hf~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~27 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~27_combout = (\z80_|execute_|ctl_alu_op_low~22_combout & (((\z80_|execute_|ctl_alu_op_low~24_combout )))) # (!\z80_|execute_|ctl_alu_op_low~22_combout & (\z80_|execute_|ixy_d~7_combout & +// (!\z80_|execute_|ctl_mWrite~5_combout ))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ctl_mWrite~5_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~24_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~27 .lut_mask = 16'hF022; +defparam \z80_|execute_|ctl_alu_core_hf~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~28 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~28_combout = (!\z80_|execute_|ctl_alu_core_hf~34_combout & ((\z80_|pla_decode_|Equal56~0_combout & ((\z80_|execute_|ctl_alu_core_hf~27_combout ) # (\z80_|execute_|ctl_alu_op_low~22_combout ))) # +// (!\z80_|pla_decode_|Equal56~0_combout & (\z80_|execute_|ctl_alu_core_hf~27_combout & \z80_|execute_|ctl_alu_op_low~22_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~34_combout ), + .datab(\z80_|pla_decode_|Equal56~0_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~27_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~28 .lut_mask = 16'h5440; +defparam \z80_|execute_|ctl_alu_core_hf~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~29 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~29_combout = (\z80_|execute_|ctl_mRead~4_combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # ((!\z80_|execute_|ctl_state_alu~4_combout & \z80_|execute_|ctl_mWrite~9_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|ctl_mWrite~9_combout ), + .datac(\z80_|execute_|ctl_mRead~4_combout ), + .datad(\z80_|execute_|ctl_mWrite~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~29 .lut_mask = 16'hF040; +defparam \z80_|execute_|ctl_alu_core_hf~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~30 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~30_combout = (\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # ((\z80_|execute_|ctl_alu_core_hf~26_combout & ((\z80_|execute_|ctl_alu_core_hf~28_combout ) # (\z80_|execute_|ctl_alu_core_hf~29_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~26_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~28_combout ), + .datac(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~29_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~30 .lut_mask = 16'hFAF8; +defparam \z80_|execute_|ctl_alu_core_hf~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y20_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~31 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~31_combout = (\z80_|execute_|ctl_alu_core_hf~25_combout ) # ((\z80_|execute_|ctl_alu_core_hf~23_combout ) # ((!\z80_|execute_|ctl_alu_op_low~43_combout & \z80_|execute_|ctl_alu_core_hf~30_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~43_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~25_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~23_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~30_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~31 .lut_mask = 16'hFDFC; +defparam \z80_|execute_|ctl_alu_core_hf~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~36 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~36_combout = (\z80_|execute_|ixy_d~6_combout ) # ((\z80_|execute_|ixy_d~8_combout & !\z80_|execute_|ixy_d~9_combout )) + + .dataa(\z80_|execute_|ixy_d~8_combout ), + .datab(gnd), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ixy_d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~36 .lut_mask = 16'hF0FA; +defparam \z80_|execute_|ctl_alu_core_hf~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~37 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~37_combout = (\z80_|execute_|ctl_alu_core_hf~36_combout & ((\z80_|pla_decode_|Equal39~0_combout ) # ((!\z80_|execute_|ixy_d~5_combout & \z80_|pla_decode_|Equal40~1_combout )))) + + .dataa(\z80_|pla_decode_|Equal39~0_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~36_combout ), + .datad(\z80_|pla_decode_|Equal40~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~37 .lut_mask = 16'hB0A0; +defparam \z80_|execute_|ctl_alu_core_hf~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y20_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~32 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~32_combout = (\z80_|execute_|ctl_alu_core_hf~22_combout ) # ((\z80_|execute_|ctl_alu_core_hf~31_combout ) # ((!\z80_|execute_|ctl_alu_op_low~44_combout & \z80_|execute_|ctl_alu_core_hf~37_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~44_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~22_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~31_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~37_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~32 .lut_mask = 16'hFDFC; +defparam \z80_|execute_|ctl_alu_core_hf~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~33 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~33_combout = (\z80_|execute_|ctl_alu_core_hf~17_combout ) # ((\z80_|execute_|ctl_alu_core_hf~32_combout ) # ((!\z80_|execute_|ctl_alu_op_low~combout & \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~17_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~32_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~33 .lut_mask = 16'hFFF4; +defparam \z80_|execute_|ctl_alu_core_hf~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y14_N22 +cycloneive_lcell_comb \z80_|alu_control_|alu_core_cf_in~0 ( +// Equation(s): +// \z80_|alu_control_|alu_core_cf_in~0_combout = (\z80_|execute_|ctl_alu_core_hf~33_combout & (\z80_|alu_flags_|flags_hf~combout )) # (!\z80_|execute_|ctl_alu_core_hf~33_combout & ((\z80_|alu_flags_|flags_cf~combout ))) + + .dataa(\z80_|alu_flags_|flags_hf~combout ), + .datab(\z80_|alu_flags_|flags_cf~combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~33_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_control_|alu_core_cf_in~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|alu_core_cf_in~0 .lut_mask = 16'hACAC; +defparam \z80_|alu_control_|alu_core_cf_in~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N12 +cycloneive_lcell_comb \z80_|alu_|alu_op1[0]~0 ( +// Equation(s): +// \z80_|alu_|alu_op1[0]~0_combout = (\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [0]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [0])) + + .dataa(\z80_|execute_|ctl_alu_op_low~combout ), + .datab(\z80_|alu_|op1_high [0]), + .datac(gnd), + .datad(\z80_|alu_|op1_low [0]), + .cin(gnd), + .combout(\z80_|alu_|alu_op1[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op1[0]~0 .lut_mask = 16'hEE44; +defparam \z80_|alu_|alu_op1[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N8 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout = (\z80_|alu_|alu_op2[0]~3_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ) # ((\z80_|alu_control_|alu_core_cf_in~0_combout & \z80_|alu_|alu_op1[0]~0_combout )))) +// # (!\z80_|alu_|alu_op2[0]~3_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_control_|alu_core_cf_in~0_combout ) # (\z80_|alu_|alu_op1[0]~0_combout )))) + + .dataa(\z80_|alu_|alu_op2[0]~3_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ), + .datac(\z80_|alu_control_|alu_core_cf_in~0_combout ), + .datad(\z80_|alu_|alu_op1[0]~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 .lut_mask = 16'hECC8; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N30 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~25 ( +// Equation(s): +// \z80_|alu_|db_high[0]~25_combout = ((\z80_|alu_|db_high[0]~24_combout & ((\z80_|execute_|ctl_alu_res_oe~3_combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout )))) # (!\z80_|alu_|db_high[3]~1_combout ) + + .dataa(\z80_|alu_|db_high[0]~24_combout ), + .datab(\z80_|alu_|db_high[3]~1_combout ), + .datac(\z80_|execute_|ctl_alu_res_oe~3_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~25 .lut_mask = 16'hBBB3; +defparam \z80_|alu_|db_high[0]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N26 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~6 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~6_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|alu_|db_low[0]~24_combout ) # ((\z80_|alu_|db_high[0]~25_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) # +// (!\z80_|execute_|ctl_alu_op2_sel_lq~combout & (\z80_|alu_|db_high[0]~25_combout & (\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datab(\z80_|alu_|db_high[0]~25_combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .datad(\z80_|alu_|db_low[0]~24_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~6 .lut_mask = 16'hEAC0; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N2 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~6_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datac(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~6_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7 .lut_mask = 16'h3030; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y18_N3 +dffeas \z80_|alu_|op2_high[0] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_high [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_high[0] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_high[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N18 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout = (\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_high [0])) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_low [0]))) + + .dataa(\z80_|alu_|op2_high [0]), + .datab(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .datac(gnd), + .datad(\z80_|alu_|op2_low [0]), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'hBB88; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N16 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout = (\z80_|alu_control_|alu_core_cf_in~0_combout & ((\z80_|alu_|alu_op1[0]~0_combout ) # (\z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout )))) # (!\z80_|alu_control_|alu_core_cf_in~0_combout & (\z80_|alu_|alu_op1[0]~0_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ), + .datac(\z80_|alu_control_|alu_core_cf_in~0_combout ), + .datad(\z80_|alu_|alu_op1[0]~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hF660; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N10 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|execute_|ctl_alu_core_S~combout & !\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_core_R~combout ), + .datac(\z80_|execute_|ctl_alu_core_S~combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 .lut_mask = 16'hCCCF; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N22 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ) # +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout )))) # (!\z80_|execute_|ctl_alu_core_R~5_combout ) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), + .datac(\z80_|execute_|ctl_alu_core_R~5_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 .lut_mask = 16'h3F2F; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N28 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout = (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout & (((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout )) # +// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ))) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout & (((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout & +// !\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout )))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 .lut_mask = 16'h50FC; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N6 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~14 ( +// Equation(s): +// \z80_|alu_|db_high[1]~14_combout = ((\z80_|bus_control_|db[3]~21_combout & (\z80_|bus_control_|db[5]~15_combout & !\z80_|bus_control_|db[4]~19_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) + + .dataa(\z80_|bus_control_|db[3]~21_combout ), + .datab(\z80_|bus_control_|db[5]~15_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datad(\z80_|bus_control_|db[4]~19_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~14 .lut_mask = 16'h0F8F; +defparam \z80_|alu_|db_high[1]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N18 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~15 ( +// Equation(s): +// \z80_|alu_|db_high[1]~15_combout = (\z80_|execute_|ctl_alu_op2_oe~0_combout & (\z80_|alu_|op2_high [1] & ((\z80_|alu_|op1_high [1]) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_high +// [1]) # ((!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datab(\z80_|alu_|op1_high [1]), + .datac(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datad(\z80_|alu_|op2_high [1]), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~15 .lut_mask = 16'hCF45; +defparam \z80_|alu_|db_high[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N18 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~16 ( +// Equation(s): +// \z80_|alu_|db_high[1]~16_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[6]~22_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[4]~18_combout ))) + + .dataa(\z80_|alu_|db[6]~22_combout ), + .datab(gnd), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|alu_|db[4]~18_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~16 .lut_mask = 16'hAFA0; +defparam \z80_|alu_|db_high[1]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N12 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~17 ( +// Equation(s): +// \z80_|alu_|db_high[1]~17_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_high[1]~16_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[5]~24_combout )) + + .dataa(\z80_|alu_|db[5]~24_combout ), + .datab(\z80_|alu_|db_high[1]~16_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~17 .lut_mask = 16'hCCAA; +defparam \z80_|alu_|db_high[1]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N6 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~18 ( +// Equation(s): +// \z80_|alu_|db_high[1]~18_combout = (\z80_|alu_|db_high[1]~14_combout & (\z80_|alu_|db_high[1]~15_combout & ((\z80_|alu_|db_high[1]~17_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) + + .dataa(\z80_|alu_|db_high[1]~14_combout ), + .datab(\z80_|alu_|db_high[1]~15_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datad(\z80_|alu_|db_high[1]~17_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~18 .lut_mask = 16'h8808; +defparam \z80_|alu_|db_high[1]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N8 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~19 ( +// Equation(s): +// \z80_|alu_|db_high[1]~19_combout = ((\z80_|alu_|db_high[1]~18_combout & ((\z80_|execute_|ctl_alu_res_oe~3_combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout )))) # (!\z80_|alu_|db_high[3]~1_combout ) + + .dataa(\z80_|execute_|ctl_alu_res_oe~3_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), + .datac(\z80_|alu_|db_high[3]~1_combout ), + .datad(\z80_|alu_|db_high[1]~18_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~19 .lut_mask = 16'hEF0F; +defparam \z80_|alu_|db_high[1]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N16 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & ((\z80_|alu_|db_low[1]~12_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_low~combout & \z80_|alu_|db_high[1]~19_combout )))) # +// (!\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & (\z80_|execute_|ctl_alu_op1_sel_low~combout & ((\z80_|alu_|db_high[1]~19_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .datac(\z80_|alu_|db_low[1]~12_combout ), + .datad(\z80_|alu_|db_high[1]~19_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4 .lut_mask = 16'hECA0; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N22 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .datad(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 .lut_mask = 16'h0F00; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y17_N23 +dffeas \z80_|alu_|op1_low[1] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_low [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_low[1] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_low[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N14 +cycloneive_lcell_comb \z80_|alu_control_|out[6]~0 ( +// Equation(s): +// \z80_|alu_control_|out[6]~0_combout = (\z80_|alu_|op1_low [3] & ((\z80_|alu_|op1_low [1]) # (\z80_|alu_|op1_low [2]))) + + .dataa(\z80_|alu_|op1_low [1]), + .datab(gnd), + .datac(\z80_|alu_|op1_low [3]), + .datad(\z80_|alu_|op1_low [2]), + .cin(gnd), + .combout(\z80_|alu_control_|out[6]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|out[6]~0 .lut_mask = 16'hF0A0; +defparam \z80_|alu_control_|out[6]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N22 +cycloneive_lcell_comb \z80_|alu_control_|out[6]~1 ( +// Equation(s): +// \z80_|alu_control_|out[6]~1_combout = (\z80_|alu_|op1_high [2]) # ((\z80_|alu_|op1_high [1]) # ((\z80_|alu_control_|out[6]~0_combout & \z80_|alu_|op1_high [0]))) + + .dataa(\z80_|alu_|op1_high [2]), + .datab(\z80_|alu_control_|out[6]~0_combout ), + .datac(\z80_|alu_|op1_high [0]), + .datad(\z80_|alu_|op1_high [1]), + .cin(gnd), + .combout(\z80_|alu_control_|out[6]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|out[6]~1 .lut_mask = 16'hFFEA; +defparam \z80_|alu_control_|out[6]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N4 +cycloneive_lcell_comb \z80_|alu_control_|out[6]~2 ( +// Equation(s): +// \z80_|alu_control_|out[6]~2_combout = (\z80_|execute_|ctl_66_oe~combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_cf~q ) # ((\z80_|alu_control_|out[6]~1_combout & \z80_|alu_|op1_high [3]))) + + .dataa(\z80_|alu_control_|out[6]~1_combout ), + .datab(\z80_|execute_|ctl_66_oe~combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), + .datad(\z80_|alu_|op1_high [3]), + .cin(gnd), + .combout(\z80_|alu_control_|out[6]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|out[6]~2 .lut_mask = 16'hFEFC; +defparam \z80_|alu_control_|out[6]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N6 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_12 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout = (\z80_|alu_control_|db[6]~22_combout & \z80_|execute_|ctl_flags_bus~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|alu_control_|db[6]~22_combout ), + .datad(\z80_|execute_|ctl_flags_bus~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_12 .lut_mask = 16'hF000; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N0 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ) # (((!\z80_|pla_decode_|Equal13~0_combout ) # (!\z80_|execute_|ixy_d~7_combout )) # (!\z80_|pla_decode_|Equal55~0_combout )) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 .lut_mask = 16'hBFFF; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N28 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout = (!\z80_|alu_|db_high[3]~7_combout & (!\z80_|alu_|db_high[0]~25_combout & (!\z80_|alu_|db_high[2]~13_combout & !\z80_|alu_|db_high[1]~19_combout ))) + + .dataa(\z80_|alu_|db_high[3]~7_combout ), + .datab(\z80_|alu_|db_high[0]~25_combout ), + .datac(\z80_|alu_|db_high[2]~13_combout ), + .datad(\z80_|alu_|db_high[1]~19_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2 .lut_mask = 16'h0001; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N4 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout = (\z80_|alu_|db_high[3]~1_combout & (!\z80_|alu_|db_low[1]~12_combout & ((!\z80_|alu_|db_low[0]~3_combout ) # (!\z80_|alu_|db_low[0]~6_combout )))) + + .dataa(\z80_|alu_|db_low[0]~6_combout ), + .datab(\z80_|alu_|db_high[3]~1_combout ), + .datac(\z80_|alu_|db_low[1]~12_combout ), + .datad(\z80_|alu_|db_low[0]~3_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 .lut_mask = 16'h040C; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N24 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout = (!\z80_|alu_|db_low[2]~23_combout & (\z80_|execute_|ctl_flags_alu~15_combout & (!\z80_|alu_|db_low[3]~25_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ))) + + .dataa(\z80_|alu_|db_low[2]~23_combout ), + .datab(\z80_|execute_|ctl_flags_alu~15_combout ), + .datac(\z80_|alu_|db_low[3]~25_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 .lut_mask = 16'h0400; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N12 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout & ((\z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout )))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 .lut_mask = 16'hC888; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~7_combout = (!\z80_|execute_|ctl_flags_sz_we~6_combout & \z80_|execute_|ctl_flags_xy_we~14_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_flags_sz_we~6_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~7 .lut_mask = 16'h0F00; +defparam \z80_|execute_|ctl_flags_sz_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~8_combout = (((!\z80_|execute_|ctl_flags_sz_we~3_combout ) # (!\z80_|execute_|ctl_flags_sz_we~2_combout )) # (!\z80_|execute_|ctl_flags_sz_we~4_combout )) # (!\z80_|execute_|ctl_flags_sz_we~7_combout ) + + .dataa(\z80_|execute_|ctl_flags_sz_we~7_combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~4_combout ), + .datac(\z80_|execute_|ctl_flags_sz_we~2_combout ), + .datad(\z80_|execute_|ctl_flags_sz_we~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~8 .lut_mask = 16'h7FFF; +defparam \z80_|execute_|ctl_flags_sz_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y16_N13 +dffeas \z80_|alu_flags_|SYNTHESIZED_WIRE_39 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_flags_sz_we~8_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_39 .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_39 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N20 +cycloneive_lcell_comb \z80_|execute_|setM1~51 ( +// Equation(s): +// \z80_|execute_|setM1~51_combout = (\z80_|execute_|setM1~50_combout & (!\z80_|pla_decode_|Equal52~1_combout & ((!\z80_|pla_decode_|Equal63~0_combout ) # (!\z80_|pla_decode_|Equal3~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal3~0_combout ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|execute_|setM1~50_combout ), + .datad(\z80_|pla_decode_|Equal52~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~51_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~51 .lut_mask = 16'h0070; +defparam \z80_|execute_|setM1~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_oe~2_combout = (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (((\z80_|execute_|ctl_state_alu~6_combout ) # (!\z80_|execute_|ctl_flags_oe~1_combout )) # (!\z80_|execute_|setM1~51_combout ))) + + .dataa(\z80_|execute_|setM1~51_combout ), + .datab(\z80_|execute_|ctl_flags_oe~1_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_oe~2 .lut_mask = 16'h00F7; +defparam \z80_|execute_|ctl_flags_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~7 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~7_combout = (((\z80_|execute_|ctl_alu_oe~1_combout & \z80_|nM1_int~2_combout )) # (!\z80_|execute_|ctl_alu_oe~8_combout )) # (!\z80_|execute_|ctl_reg_out_hi~6_combout ) + + .dataa(\z80_|execute_|ctl_alu_oe~1_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|execute_|ctl_reg_out_hi~6_combout ), + .datad(\z80_|execute_|ctl_alu_oe~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~7 .lut_mask = 16'h8FFF; +defparam \z80_|execute_|ctl_sw_2u~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N10 +cycloneive_lcell_comb \z80_|alu_control_|db[6]~20 ( +// Equation(s): +// \z80_|alu_control_|db[6]~20_combout = (\z80_|alu_|db[6]~22_combout & (!\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & (\z80_|execute_|ctl_flags_oe~2_combout ))) # (!\z80_|alu_|db[6]~22_combout & ((\z80_|execute_|ctl_sw_2u~7_combout ) # +// ((!\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & \z80_|execute_|ctl_flags_oe~2_combout )))) + + .dataa(\z80_|alu_|db[6]~22_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datac(\z80_|execute_|ctl_flags_oe~2_combout ), + .datad(\z80_|execute_|ctl_sw_2u~7_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[6]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[6]~20 .lut_mask = 16'h7530; +defparam \z80_|alu_control_|db[6]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N16 +cycloneive_lcell_comb \z80_|alu_control_|db[6]~21 ( +// Equation(s): +// \z80_|alu_control_|db[6]~21_combout = (!\z80_|alu_control_|db[6]~20_combout & ((\z80_|alu_control_|out[6]~2_combout ) # ((!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & !\z80_|execute_|ctl_66_oe~combout )))) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datab(\z80_|execute_|ctl_66_oe~combout ), + .datac(\z80_|alu_control_|out[6]~2_combout ), + .datad(\z80_|alu_control_|db[6]~20_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[6]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[6]~21 .lut_mask = 16'h00F1; +defparam \z80_|alu_control_|db[6]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~8_combout = (\z80_|execute_|ctl_reg_out_lo~5_combout ) # ((!\z80_|execute_|ctl_reg_out_lo~7_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout )) + + .dataa(\z80_|execute_|ctl_reg_out_lo~5_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~8 .lut_mask = 16'hBFBF; +defparam \z80_|execute_|ctl_reg_out_lo~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N2 +cycloneive_lcell_comb \z80_|alu_control_|db[6]~10 ( +// Equation(s): +// \z80_|alu_control_|db[6]~10_combout = (\z80_|execute_|ctl_flags_oe~2_combout ) # ((\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|execute_|ctl_66_oe~2_combout & \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ))) + + .dataa(\z80_|execute_|ctl_66_oe~2_combout ), + .datab(\z80_|execute_|ctl_flags_oe~2_combout ), + .datac(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[6]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[6]~10 .lut_mask = 16'hFFEC; +defparam \z80_|alu_control_|db[6]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N28 +cycloneive_lcell_comb \z80_|alu_control_|db[6]~11 ( +// Equation(s): +// \z80_|alu_control_|db[6]~11_combout = (\z80_|execute_|ctl_sw_1d~7_combout ) # ((\z80_|execute_|ctl_reg_out_lo~8_combout ) # ((\z80_|execute_|ctl_sw_2u~7_combout ) # (\z80_|alu_control_|db[6]~10_combout ))) + + .dataa(\z80_|execute_|ctl_sw_1d~7_combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .datac(\z80_|execute_|ctl_sw_2u~7_combout ), + .datad(\z80_|alu_control_|db[6]~10_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[6]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[6]~11 .lut_mask = 16'hFFFE; +defparam \z80_|alu_control_|db[6]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N20 +cycloneive_lcell_comb \z80_|alu_control_|db[6]~22 ( +// Equation(s): +// \z80_|alu_control_|db[6]~22_combout = ((\z80_|reg_file_|db_lo_ds[6]~0_combout & (\z80_|sw1_|db_down[6]~1_combout & \z80_|alu_control_|db[6]~21_combout ))) # (!\z80_|alu_control_|db[6]~11_combout ) + + .dataa(\z80_|reg_file_|db_lo_ds[6]~0_combout ), + .datab(\z80_|sw1_|db_down[6]~1_combout ), + .datac(\z80_|alu_control_|db[6]~21_combout ), + .datad(\z80_|alu_control_|db[6]~11_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[6]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[6]~22 .lut_mask = 16'h80FF; +defparam \z80_|alu_control_|db[6]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N10 +cycloneive_lcell_comb \z80_|alu_|db[6]~21 ( +// Equation(s): +// \z80_|alu_|db[6]~21_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[6]~84_combout & ((\z80_|alu_control_|db[6]~22_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & +// ((\z80_|alu_control_|db[6]~22_combout ) # ((!\z80_|execute_|ctl_sw_2d~13_combout )))) + + .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .datab(\z80_|alu_control_|db[6]~22_combout ), + .datac(\z80_|execute_|ctl_sw_2d~13_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[6]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[6]~21 .lut_mask = 16'hCF45; +defparam \z80_|alu_|db[6]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N24 +cycloneive_lcell_comb \z80_|alu_|db[6]~22 ( +// Equation(s): +// \z80_|alu_|db[6]~22_combout = ((\z80_|alu_|db[6]~21_combout & ((\z80_|alu_|db_high[2]~13_combout ) # (!\z80_|execute_|ctl_alu_oe~11_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|execute_|ctl_alu_oe~11_combout ), + .datab(\z80_|alu_|db[7]~9_combout ), + .datac(\z80_|alu_|db_high[2]~13_combout ), + .datad(\z80_|alu_|db[6]~21_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[6]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[6]~22 .lut_mask = 16'hF733; +defparam \z80_|alu_|db[6]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y16_N3 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~80 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~80_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout & (\z80_|alu_|db[6]~22_combout & ((\z80_|reg_file_|b2v_latch_af2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # +// (!\z80_|execute_|ctl_reg_in_hi~12_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .datab(\z80_|alu_|db[6]~22_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~80_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~80 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[6]~80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y16_N23 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y16_N1 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~79 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~79_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [6]), + .datad(\z80_|reg_file_|b2v_latch_iy_hi|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~79_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~79 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[6]~79 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y16_N23 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N20 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_hi|latch[6]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_bc_hi|latch[6]~feeder_combout = \z80_|reg_file_|gdfx_temp1[6]~84_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_bc_hi|latch[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[6]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y16_N21 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_bc_hi|latch[6]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~78 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~78_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (\z80_|reg_file_|b2v_latch_bc2_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]), + .datad(\z80_|reg_file_|b2v_latch_bc_hi|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~78_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~78 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[6]~78 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y16_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~82 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~82_combout = (\z80_|reg_file_|gdfx_temp1[6]~81_combout & (\z80_|reg_file_|gdfx_temp1[6]~80_combout & (\z80_|reg_file_|gdfx_temp1[6]~79_combout & \z80_|reg_file_|gdfx_temp1[6]~78_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[6]~81_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[6]~80_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[6]~79_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[6]~78_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~82_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~82 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[6]~82 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y14_N19 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N18 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl2_hi|db[6]~5 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_hl2_hi|db[6]~5_combout = (\z80_|execute_|ctl_reg_gp_we~8_combout ) # (((\z80_|reg_file_|b2v_latch_hl2_hi|latch [6]) # (!\z80_|reg_control_|reg_sel_hl2~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [6]), + .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_hl2_hi|db[6]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|db[6]~5 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|db[6]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y15_N7 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X37_Y15_N19 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N24 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder_combout = \z80_|reg_file_|gdfx_temp1[6]~84_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y15_N25 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~76 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~76_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [6]), + .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~76_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~76 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[6]~76 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~77 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~77_combout = (\z80_|reg_file_|b2v_latch_hl2_hi|db[6]~5_combout & (\z80_|reg_file_|gdfx_temp1[6]~76_combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl2_hi|db[6]~5_combout ), + .datac(\z80_|reg_file_|b2v_latch_hl_hi|latch [6]), + .datad(\z80_|reg_file_|gdfx_temp1[6]~76_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~77_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~77 .lut_mask = 16'hC400; +defparam \z80_|reg_file_|gdfx_temp1[6]~77 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~83 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~83_combout = (\z80_|reg_file_|gdfx_temp1[6]~82_combout & (\z80_|reg_file_|gdfx_temp1[6]~77_combout & ((\z80_|reg_file_|b2v_latch_af_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_32~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_af_hi|latch [6]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_32~combout ), + .datac(\z80_|reg_file_|gdfx_temp1[6]~82_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[6]~77_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~83_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~83 .lut_mask = 16'hB000; +defparam \z80_|reg_file_|gdfx_temp1[6]~83 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~84 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~84_combout = ((\z80_|reg_file_|gdfx_temp1[6]~83_combout & ((\z80_|reg_file_|db_hi_as[6]~24_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[6]~83_combout ), + .datac(\z80_|reg_file_|db_hi_as[6]~24_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~84 .lut_mask = 16'hC4FF; +defparam \z80_|reg_file_|gdfx_temp1[6]~84 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y14_N19 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[6]~24_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N18 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~22 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[6]~22_combout = (\z80_|reg_control_|reg_sw_4d_hi~0_combout & (\z80_|reg_file_|gdfx_temp1[6]~84_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[6]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[6]~22 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_hi_as[6]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y14_N17 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[6]~24_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N26 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~23 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[6]~23_combout = (\z80_|reg_file_|db_hi_as[6]~22_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|db_hi_as[6]~22_combout ), + .datab(\z80_|reg_file_|b2v_latch_pc_hi|latch [6]), + .datac(gnd), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[6]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[6]~23 .lut_mask = 16'h88AA; +defparam \z80_|reg_file_|db_hi_as[6]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N14 +cycloneive_lcell_comb \z80_|address_latch_|abusz[13] ( +// Equation(s): +// \z80_|address_latch_|abusz [13] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[5]~15_combout ) + + .dataa(\z80_|resets_|clrpc~0_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|db_hi_as[5]~15_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [13]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[13] .lut_mask = 16'h5500; +defparam \z80_|address_latch_|abusz[13] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y13_N15 +dffeas \z80_|address_latch_|Q[13] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [13]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [13]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[13] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N18 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout = \z80_|address_latch_|Q [12] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout & (\z80_|address_latch_|Q [11] $ +// (\z80_|execute_|ctl_inc_dec~11_combout ))))) + + .dataa(\z80_|address_latch_|Q [11]), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), + .datac(\z80_|execute_|ctl_inc_dec~11_combout ), + .datad(\z80_|address_latch_|Q [12]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out .lut_mask = 16'hB748; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y16_N31 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y16_N29 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~61 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~61_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [4]), + .datad(\z80_|reg_file_|b2v_latch_iy_hi|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~61_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~61 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[4]~61 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y16_N15 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~62 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~62_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout & (\z80_|alu_|db[4]~18_combout & ((\z80_|reg_file_|b2v_latch_af2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # +// (!\z80_|execute_|ctl_reg_in_hi~12_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .datab(\z80_|alu_|db[4]~18_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~62_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~62 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[4]~62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y16_N3 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N0 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder_combout = \z80_|reg_file_|gdfx_temp1[4]~66_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y16_N1 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~60 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~60_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (\z80_|reg_file_|b2v_latch_bc2_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]), + .datad(\z80_|reg_file_|b2v_latch_bc_hi|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~60_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~60 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[4]~60 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y15_N29 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X35_Y15_N23 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~63 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~63_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (\z80_|reg_file_|b2v_latch_wz_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (((\z80_|reg_file_|b2v_latch_sp_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .datab(\z80_|reg_file_|b2v_latch_wz_hi|latch [4]), + .datac(\z80_|reg_file_|b2v_latch_sp_hi|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~63_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~63 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[4]~63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~64 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~64_combout = (\z80_|reg_file_|gdfx_temp1[4]~61_combout & (\z80_|reg_file_|gdfx_temp1[4]~62_combout & (\z80_|reg_file_|gdfx_temp1[4]~60_combout & \z80_|reg_file_|gdfx_temp1[4]~63_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[4]~61_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[4]~62_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[4]~60_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[4]~63_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~64_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~64 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[4]~64 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y15_N5 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X37_Y14_N5 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N4 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl2_hi|db[4]~4 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_hl2_hi|db[4]~4_combout = (\z80_|execute_|ctl_reg_gp_we~8_combout ) # (((\z80_|reg_file_|b2v_latch_hl2_hi|latch [4]) # (!\z80_|reg_control_|reg_sel_hl2~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [4]), + .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_hl2_hi|db[4]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|db[4]~4 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|db[4]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y15_N1 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X37_Y15_N5 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X37_Y15_N23 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~58 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~58_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datab(\z80_|reg_file_|b2v_latch_de_hi|latch [4]), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~58_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~58 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[4]~58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~59 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~59_combout = (\z80_|reg_file_|b2v_latch_hl2_hi|db[4]~4_combout & (\z80_|reg_file_|gdfx_temp1[4]~58_combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl2_hi|db[4]~4_combout ), + .datac(\z80_|reg_file_|b2v_latch_hl_hi|latch [4]), + .datad(\z80_|reg_file_|gdfx_temp1[4]~58_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~59_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~59 .lut_mask = 16'hC400; +defparam \z80_|reg_file_|gdfx_temp1[4]~59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~65 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~65_combout = (\z80_|reg_file_|gdfx_temp1[4]~64_combout & (\z80_|reg_file_|gdfx_temp1[4]~59_combout & ((\z80_|reg_file_|b2v_latch_af_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_32~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[4]~64_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_32~combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [4]), + .datad(\z80_|reg_file_|gdfx_temp1[4]~59_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~65_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~65 .lut_mask = 16'hA200; +defparam \z80_|reg_file_|gdfx_temp1[4]~65 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~66 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~66_combout = ((\z80_|reg_file_|gdfx_temp1[4]~65_combout & ((\z80_|reg_file_|db_hi_as[4]~18_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), + .datab(\z80_|reg_file_|db_hi_as[4]~18_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[4]~65_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~66 .lut_mask = 16'hD0FF; +defparam \z80_|reg_file_|gdfx_temp1[4]~66 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y14_N11 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[4]~18_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N10 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~16 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[4]~16_combout = (\z80_|reg_control_|reg_sw_4d_hi~0_combout & (\z80_|reg_file_|gdfx_temp1[4]~66_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[4]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[4]~16 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_hi_as[4]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y14_N25 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[4]~18_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N2 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~17 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[4]~17_combout = (\z80_|reg_file_|db_hi_as[4]~16_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|db_hi_as[4]~16_combout ), + .datab(\z80_|reg_file_|b2v_latch_pc_hi|latch [4]), + .datac(gnd), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[4]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[4]~17 .lut_mask = 16'h88AA; +defparam \z80_|reg_file_|db_hi_as[4]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N24 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~18 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[4]~18_combout = ((\z80_|reg_file_|db_hi_as[4]~17_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), + .datab(\z80_|reg_file_|db_hi_as[4]~17_combout ), + .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[4]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[4]~18 .lut_mask = 16'h8FCF; +defparam \z80_|reg_file_|db_hi_as[4]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N22 +cycloneive_lcell_comb \z80_|address_latch_|abusz[12] ( +// Equation(s): +// \z80_|address_latch_|abusz [12] = (\z80_|reg_file_|db_hi_as[4]~18_combout & !\z80_|resets_|clrpc~0_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[4]~18_combout ), + .datab(gnd), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [12]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[12] .lut_mask = 16'h0A0A; +defparam \z80_|address_latch_|abusz[12] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y13_N23 +dffeas \z80_|address_latch_|Q[12] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [12]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [12]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[12] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N20 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout & ((\z80_|address_latch_|Q [11] & (!\z80_|execute_|ctl_inc_dec~11_combout & +// \z80_|address_latch_|Q [12])) # (!\z80_|address_latch_|Q [11] & (\z80_|execute_|ctl_inc_dec~11_combout & !\z80_|address_latch_|Q [12])))) + + .dataa(\z80_|address_latch_|Q [11]), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), + .datac(\z80_|execute_|ctl_inc_dec~11_combout ), + .datad(\z80_|address_latch_|Q [12]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'h0840; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N24 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[14] ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|address [14] = \z80_|address_latch_|Q [14] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout & (\z80_|address_latch_|Q [13] $ (\z80_|execute_|ctl_inc_dec~11_combout ))))) + + .dataa(\z80_|address_latch_|Q [13]), + .datab(\z80_|execute_|ctl_inc_dec~11_combout ), + .datac(\z80_|address_latch_|Q [14]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[14] .lut_mask = 16'h96F0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[14] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N16 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~24 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[6]~24_combout = ((\z80_|reg_file_|db_hi_as[6]~23_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [14]) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .datab(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datac(\z80_|reg_file_|db_hi_as[6]~23_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[6]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[6]~24 .lut_mask = 16'hF373; +defparam \z80_|reg_file_|db_hi_as[6]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N30 +cycloneive_lcell_comb \z80_|address_latch_|abusz[14] ( +// Equation(s): +// \z80_|address_latch_|abusz [14] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[6]~24_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(\z80_|reg_file_|db_hi_as[6]~24_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [14]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[14] .lut_mask = 16'h0F00; +defparam \z80_|address_latch_|abusz[14] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y13_N31 +dffeas \z80_|address_latch_|Q[14] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [14]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [14]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[14] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N4 +cycloneive_lcell_comb \z80_|address_latch_|abusz[15] ( +// Equation(s): +// \z80_|address_latch_|abusz [15] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[7]~21_combout ) + + .dataa(\z80_|resets_|clrpc~0_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|db_hi_as[7]~21_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [15]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[15] .lut_mask = 16'h5500; +defparam \z80_|address_latch_|abusz[15] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y13_N5 +dffeas \z80_|address_latch_|Q[15] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [15]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [15]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[15] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N2 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[15]~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|address[15]~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout & (\z80_|address_latch_|Q [13] $ (((\z80_|execute_|ctl_inc_dec~10_combout ) # +// (\z80_|execute_|ctl_inc_dec~7_combout ))))) + + .dataa(\z80_|execute_|ctl_inc_dec~10_combout ), + .datab(\z80_|execute_|ctl_inc_dec~7_combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), + .datad(\z80_|address_latch_|Q [13]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|address[15]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[15]~0 .lut_mask = 16'h10E0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[15]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N0 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[15]~1 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|address[15]~1_combout = \z80_|address_latch_|Q [15] $ (((\z80_|address_latch_|b2v_inst_inc_dec|address[15]~0_combout & (\z80_|address_latch_|Q [14] $ (\z80_|execute_|ctl_inc_dec~11_combout ))))) + + .dataa(\z80_|address_latch_|Q [14]), + .datab(\z80_|execute_|ctl_inc_dec~11_combout ), + .datac(\z80_|address_latch_|Q [15]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|address[15]~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|address[15]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[15]~1 .lut_mask = 16'h96F0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[15]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y14_N7 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[7]~21_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X35_Y14_N21 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[7]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N20 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~19 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[7]~19_combout = (\z80_|reg_control_|reg_sw_4d_hi~0_combout & (\z80_|reg_file_|gdfx_temp1[7]~75_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) + + .dataa(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [7]), + .datad(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[7]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[7]~19 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|db_hi_as[7]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N12 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~20 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[7]~20_combout = (\z80_|reg_file_|db_hi_as[7]~19_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_pc_hi|latch [7]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datac(gnd), + .datad(\z80_|reg_file_|db_hi_as[7]~19_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[7]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[7]~20 .lut_mask = 16'hBB00; +defparam \z80_|reg_file_|db_hi_as[7]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N6 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~21 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[7]~21_combout = ((\z80_|reg_file_|db_hi_as[7]~20_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address[15]~1_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|address[15]~1_combout ), + .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datad(\z80_|reg_file_|db_hi_as[7]~20_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[7]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[7]~21 .lut_mask = 16'hDF0F; +defparam \z80_|reg_file_|db_hi_as[7]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y15_N29 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N28 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[7]~15 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[7]~15_combout = (\z80_|execute_|ctl_reg_gp_we~8_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [7]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [7]), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[7]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[7]~15 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[7]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y15_N31 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X35_Y15_N25 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~72 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~72_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (\z80_|reg_file_|b2v_latch_wz_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [7]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [7]), + .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~72_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~72 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp1[7]~72 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y16_N17 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~71 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~71_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout & (\z80_|alu_|db[7]~12_combout & ((\z80_|reg_file_|b2v_latch_af2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # +// (!\z80_|execute_|ctl_reg_in_hi~12_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .datab(\z80_|alu_|db[7]~12_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~71_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~71 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[7]~71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y16_N11 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y16_N13 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~70 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~70_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [7]), + .datad(\z80_|reg_file_|b2v_latch_iy_hi|latch [7]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~70_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~70 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[7]~70 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y16_N15 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X37_Y16_N29 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~69 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~69_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (\z80_|reg_file_|b2v_latch_bc2_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]), + .datad(\z80_|reg_file_|b2v_latch_bc_hi|latch [7]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~69_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~69 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[7]~69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y16_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~73 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~73_combout = (\z80_|reg_file_|gdfx_temp1[7]~72_combout & (\z80_|reg_file_|gdfx_temp1[7]~71_combout & (\z80_|reg_file_|gdfx_temp1[7]~70_combout & \z80_|reg_file_|gdfx_temp1[7]~69_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[7]~72_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[7]~71_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[7]~70_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[7]~69_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~73_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~73 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[7]~73 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y14_N15 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X37_Y14_N25 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~68 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~68_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (\z80_|reg_file_|b2v_latch_hl_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_hl2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (((\z80_|reg_file_|b2v_latch_hl2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [7]), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~68_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~68 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[7]~68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y15_N3 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N0 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_hi|latch[7]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_de_hi|latch[7]~feeder_combout = \z80_|reg_file_|gdfx_temp1[7]~75_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_de_hi|latch[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[7]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y15_N1 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_de_hi|latch[7]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~67 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~67_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [7]), + .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [7]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~67_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~67 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[7]~67 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y15_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~74 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~74_combout = (\z80_|reg_file_|b2v_latch_af_hi|db[7]~15_combout & (\z80_|reg_file_|gdfx_temp1[7]~73_combout & (\z80_|reg_file_|gdfx_temp1[7]~68_combout & \z80_|reg_file_|gdfx_temp1[7]~67_combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_af_hi|db[7]~15_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[7]~73_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[7]~68_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[7]~67_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~74_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~74 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[7]~74 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~75 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~75_combout = ((\z80_|reg_file_|gdfx_temp1[7]~74_combout & ((\z80_|reg_file_|db_hi_as[7]~21_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[7]~21_combout ), + .datab(\z80_|execute_|ctl_sw_4u~6_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[7]~74_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~75 .lut_mask = 16'hBF0F; +defparam \z80_|reg_file_|gdfx_temp1[7]~75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N0 +cycloneive_lcell_comb \z80_|alu_|db[7]~11 ( +// Equation(s): +// \z80_|alu_|db[7]~11_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[7]~75_combout & ((\z80_|alu_control_|db[7]~19_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & +// ((\z80_|alu_control_|db[7]~19_combout ) # ((!\z80_|execute_|ctl_sw_2d~13_combout )))) + + .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .datab(\z80_|alu_control_|db[7]~19_combout ), + .datac(\z80_|execute_|ctl_sw_2d~13_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[7]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[7]~11 .lut_mask = 16'hCF45; +defparam \z80_|alu_|db[7]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N30 +cycloneive_lcell_comb \z80_|alu_|db[7]~12 ( +// Equation(s): +// \z80_|alu_|db[7]~12_combout = ((\z80_|alu_|db[7]~11_combout & ((\z80_|alu_|db_high[3]~7_combout ) # (!\z80_|execute_|ctl_alu_oe~11_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|execute_|ctl_alu_oe~11_combout ), + .datab(\z80_|alu_|db[7]~9_combout ), + .datac(\z80_|alu_|db_high[3]~7_combout ), + .datad(\z80_|alu_|db[7]~11_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[7]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[7]~12 .lut_mask = 16'hF733; +defparam \z80_|alu_|db[7]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N28 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~0 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[0]~14_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[7]~12_combout ))) + + .dataa(\z80_|alu_|db[0]~14_combout ), + .datab(gnd), + .datac(\z80_|alu_|db[7]~12_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~0 .lut_mask = 16'hAAF0; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N2 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~1 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_control_|out[6]~2_combout ))) + + .dataa(gnd), + .datab(\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ), + .datac(\z80_|alu_control_|out[6]~2_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~1 .lut_mask = 16'hCCF0; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N20 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~2 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (((\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout & !\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout )))) # (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout +// & ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((!\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout )))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ), + .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~2 .lut_mask = 16'h03CA; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N8 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~3 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout = (\z80_|execute_|ctl_flags_cf2_we~3_combout & (\z80_|execute_|ctl_flags_cf2_sel_daa~combout $ (((!\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ))))) # (!\z80_|execute_|ctl_flags_cf2_we~3_combout & +// ((\z80_|alu_flags_|DFFE_inst_latch_cf2~q ) # ((\z80_|execute_|ctl_flags_cf2_sel_daa~combout & \z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout )))) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datab(\z80_|execute_|ctl_flags_cf2_we~3_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~3 .lut_mask = 16'hBA74; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y14_N9 +dffeas \z80_|alu_flags_|DFFE_inst_latch_cf2 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2 .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~8_combout = (\z80_|pla_decode_|Equal20~0_combout ) # ((\z80_|execute_|ctl_ir_we~14_combout ) # (\z80_|execute_|ctl_ir_we~8_combout )) + + .dataa(\z80_|pla_decode_|Equal20~0_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_ir_we~14_combout ), + .datad(\z80_|execute_|ctl_ir_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~8 .lut_mask = 16'hFFFA; +defparam \z80_|execute_|ctl_flags_use_cf2~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~9 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~9_combout = (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_flags_use_cf2~8_combout ) # ((\z80_|pla_decode_|Equal63~0_combout & \z80_|pla_decode_|Equal9~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal63~0_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|execute_|ctl_flags_use_cf2~8_combout ), + .datad(\z80_|pla_decode_|Equal9~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~9 .lut_mask = 16'h3230; +defparam \z80_|execute_|ctl_flags_use_cf2~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~10_combout = (\z80_|pla_decode_|Equal11~0_combout & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_M1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~10 .lut_mask = 16'h0C04; +defparam \z80_|execute_|ctl_flags_use_cf2~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~11 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~11_combout = (\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # ((\z80_|execute_|ctl_flags_use_cf2~10_combout ) # ((\z80_|execute_|ixy_d~7_combout & \z80_|pla_decode_|Equal10~0_combout ))) + + .dataa(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|execute_|ctl_flags_use_cf2~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~11 .lut_mask = 16'hFFEA; +defparam \z80_|execute_|ctl_flags_use_cf2~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~12 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~12_combout = ((\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # ((\z80_|execute_|ctl_flags_use_cf2~9_combout ) # (\z80_|execute_|ctl_flags_use_cf2~11_combout ))) # (!\z80_|execute_|ctl_flags_use_cf2~13_combout ) + + .dataa(\z80_|execute_|ctl_flags_use_cf2~13_combout ), + .datab(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .datac(\z80_|execute_|ctl_flags_use_cf2~9_combout ), + .datad(\z80_|execute_|ctl_flags_use_cf2~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~12 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_flags_use_cf2~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N28 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout = (\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & (\z80_|alu_flags_|DFFE_inst_latch_cf2~q )) # (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & ((\z80_|execute_|ctl_flags_use_cf2~12_combout & +// (\z80_|alu_flags_|DFFE_inst_latch_cf2~q )) # (!\z80_|execute_|ctl_flags_use_cf2~12_combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf~q ))))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), + .datac(\z80_|execute_|ctl_flags_use_cf2~12_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 .lut_mask = 16'hABA8; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~46 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~46_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|pla_decode_|Equal10~0_combout & \z80_|sequencer_|DFFE_T3_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|pla_decode_|Equal10~0_combout ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~46 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_alu_op_low~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~9_combout = (\z80_|execute_|ctl_alu_core_S~4_combout & (\z80_|execute_|ctl_bus_inc_oe~44_combout & (\z80_|execute_|ctl_flags_alu~18_combout & \z80_|execute_|ctl_alu_op1_sel_bus~9_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_S~4_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .datac(\z80_|execute_|ctl_flags_alu~18_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~9 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N28 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|pla_decode_|Equal63~0_combout & (\z80_|pla_decode_|Equal21~0_combout & !\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) + + .dataa(\z80_|pla_decode_|Equal63~0_combout ), + .datab(\z80_|pla_decode_|Equal21~0_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 .lut_mask = 16'hFF08; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N10 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout = (\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # ((\z80_|execute_|ctl_alu_op_low~46_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~46_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 .lut_mask = 16'hFFEF; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N16 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout = ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ) # ((\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & \z80_|execute_|ctl_alu_op_low~42_combout ))) # (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ) + + .dataa(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~42_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 .lut_mask = 16'hFBF3; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y17_N16 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout = (\z80_|execute_|ctl_state_alu~11_combout & ((\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3])) # (!\z80_|ir_|opcode [5] & ((!\z80_|ir_|opcode [3]))))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|execute_|ctl_state_alu~11_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 .lut_mask = 16'h8050; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N22 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ) # ((\z80_|execute_|ctl_alu_op_low~41_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~41_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 .lut_mask = 16'hFEFA; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~3_combout = (\z80_|execute_|ctl_alu_op_low~41_combout & (\z80_|pla_decode_|Equal64~0_combout & ((\z80_|pla_decode_|Equal9~0_combout ) # (\z80_|pla_decode_|Equal3~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~41_combout ), + .datab(\z80_|pla_decode_|Equal9~0_combout ), + .datac(\z80_|pla_decode_|Equal64~0_combout ), + .datad(\z80_|pla_decode_|Equal3~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~3 .lut_mask = 16'hA080; +defparam \z80_|execute_|ctl_flags_cf_cpl~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N20 +cycloneive_lcell_comb \z80_|alu_flags_|flags_cf ( +// Equation(s): +// \z80_|alu_flags_|flags_cf~combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout $ (((\z80_|execute_|ctl_flags_cf_cpl~9_combout ) # (\z80_|execute_|ctl_flags_cf_cpl~3_combout ))))) + + .dataa(\z80_|execute_|ctl_flags_cf_cpl~9_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ), + .datad(\z80_|execute_|ctl_flags_cf_cpl~3_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|flags_cf~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|flags_cf .lut_mask = 16'h0C48; +defparam \z80_|alu_flags_|flags_cf .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N14 +cycloneive_lcell_comb \z80_|sw2_|db_up[0]~0 ( +// Equation(s): +// \z80_|sw2_|db_up[0]~0_combout = (\z80_|alu_|db[0]~14_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|alu_|db[0]~14_combout ), + .datad(\z80_|execute_|ctl_sw_2u~7_combout ), + .cin(gnd), + .combout(\z80_|sw2_|db_up[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sw2_|db_up[0]~0 .lut_mask = 16'hF0FF; +defparam \z80_|sw2_|db_up[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N14 +cycloneive_lcell_comb \z80_|alu_control_|db[0]~8 ( +// Equation(s): +// \z80_|alu_control_|db[0]~8_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & (((!\z80_|execute_|ctl_sw_mask543_en~0_combout & \z80_|bus_control_|db[0]~17_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) + + .dataa(\z80_|execute_|ctl_sw_mask543_en~0_combout ), + .datab(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .datac(\z80_|execute_|ctl_sw_1d~7_combout ), + .datad(\z80_|bus_control_|db[0]~17_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[0]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[0]~8 .lut_mask = 16'h4C0C; +defparam \z80_|alu_control_|db[0]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y12_N11 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[0]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y12_N5 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[0]~3_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N4 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~0 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[0]~0_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[0]~22_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # +// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[0]~0 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_lo_as[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N0 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~1 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[0]~1_combout = (\z80_|reg_file_|db_lo_as[0]~0_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_ir_lo|latch [0]), + .datab(gnd), + .datac(\z80_|reg_file_|db_lo_as[0]~0_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[0]~1 .lut_mask = 16'hA0F0; +defparam \z80_|reg_file_|db_lo_as[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~70 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~70_combout = (!\z80_|nM1_int~2_combout & (((!\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ctl_alu_op_low~22_combout )) # (!\z80_|pla_decode_|Equal41~2_combout ))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|pla_decode_|Equal41~2_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~70_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~70 .lut_mask = 16'h0307; +defparam \z80_|execute_|ctl_inc_cy~70 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N8 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~28 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~28_combout = (\z80_|pla_decode_|Equal10~0_combout & (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|pla_decode_|Equal10~0_combout ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~28 .lut_mask = 16'hC080; +defparam \z80_|execute_|pc_inc_hold~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N10 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~15 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~15_combout = (\z80_|execute_|pc_inc_hold~28_combout ) # ((\z80_|execute_|ctl_alu_op_low~22_combout & ((\z80_|pla_decode_|Equal52~1_combout ) # (\z80_|execute_|ixy_d~16_combout )))) + + .dataa(\z80_|pla_decode_|Equal52~1_combout ), + .datab(\z80_|execute_|ixy_d~16_combout ), + .datac(\z80_|execute_|pc_inc_hold~28_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~15 .lut_mask = 16'hFEF0; +defparam \z80_|execute_|pc_inc_hold~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N18 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~27 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~27_combout = (\z80_|pla_decode_|Equal11~0_combout & (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~27 .lut_mask = 16'hC080; +defparam \z80_|execute_|pc_inc_hold~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~10 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~10_combout = (\z80_|execute_|ctl_alu_op_low~22_combout & (((\z80_|execute_|ctl_mRead~7_combout ) # (\z80_|execute_|ctl_mRead~13_combout )))) # (!\z80_|execute_|ctl_alu_op_low~22_combout & (\z80_|execute_|ixy_d~5_combout & +// ((\z80_|execute_|ctl_mRead~13_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_mRead~7_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datad(\z80_|execute_|ctl_mRead~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~10 .lut_mask = 16'hFAC0; +defparam \z80_|execute_|pc_inc_hold~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout = (\z80_|execute_|ixy_d~5_combout & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal55~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~11 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~11_combout = (\z80_|execute_|ctl_alu_op_low~22_combout & ((\z80_|pla_decode_|Equal6~1_combout ) # ((\z80_|execute_|ctl_mRead~8_combout )))) # (!\z80_|execute_|ctl_alu_op_low~22_combout & (\z80_|execute_|ixy_d~5_combout & +// ((\z80_|pla_decode_|Equal6~1_combout ) # (\z80_|execute_|ctl_mRead~8_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datab(\z80_|pla_decode_|Equal6~1_combout ), + .datac(\z80_|execute_|ctl_mRead~8_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~11 .lut_mask = 16'hFCA8; +defparam \z80_|execute_|pc_inc_hold~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout = (\z80_|decode_state_|use_ixiy~combout & (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|pla_decode_|Equal33~2_combout ))) + + .dataa(\z80_|decode_state_|use_ixiy~combout ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|pla_decode_|Equal33~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~9 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~9_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ) # ((\z80_|execute_|ctl_alu_op_low~22_combout & ((\z80_|execute_|ctl_mRead~12_combout ) # (!\z80_|execute_|pc_inc_hold~6_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datac(\z80_|execute_|ctl_mRead~12_combout ), + .datad(\z80_|execute_|pc_inc_hold~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~9 .lut_mask = 16'hEAEE; +defparam \z80_|execute_|pc_inc_hold~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~12 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~12_combout = (\z80_|execute_|pc_inc_hold~10_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ) # ((\z80_|execute_|pc_inc_hold~11_combout ) # (\z80_|execute_|pc_inc_hold~9_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~10_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ), + .datac(\z80_|execute_|pc_inc_hold~11_combout ), + .datad(\z80_|execute_|pc_inc_hold~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~12 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|pc_inc_hold~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~7 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~7_combout = ((\z80_|pla_decode_|Equal12~1_combout ) # ((!\z80_|execute_|ctl_alu_op_low~22_combout & !\z80_|execute_|ixy_d~5_combout ))) # (!\z80_|pla_decode_|Equal25~0_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datab(\z80_|pla_decode_|Equal25~0_combout ), + .datac(\z80_|pla_decode_|Equal12~1_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~7 .lut_mask = 16'hF3F7; +defparam \z80_|execute_|pc_inc_hold~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y14_N8 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~8 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~8_combout = (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|execute_|ctl_mRead~15_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|execute_|ctl_mRead~15_combout ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~8 .lut_mask = 16'h5F7F; +defparam \z80_|execute_|pc_inc_hold~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~13 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~13_combout = (\z80_|execute_|ctl_mRead~6_combout & (\z80_|sequencer_|DFFE_T2_ff~q & ((\z80_|sequencer_|DFFE_M2_ff~q ) # (\z80_|sequencer_|DFFE_M3_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|execute_|ctl_mRead~6_combout ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~13 .lut_mask = 16'hE000; +defparam \z80_|execute_|pc_inc_hold~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y14_N14 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~14 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~14_combout = (!\z80_|execute_|pc_inc_hold~12_combout & (\z80_|execute_|pc_inc_hold~7_combout & (\z80_|execute_|pc_inc_hold~8_combout & !\z80_|execute_|pc_inc_hold~13_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~12_combout ), + .datab(\z80_|execute_|pc_inc_hold~7_combout ), + .datac(\z80_|execute_|pc_inc_hold~8_combout ), + .datad(\z80_|execute_|pc_inc_hold~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~14 .lut_mask = 16'h0040; +defparam \z80_|execute_|pc_inc_hold~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal45~0_combout & \z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|pla_decode_|Equal45~0_combout ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y14_N16 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~16 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~16_combout = (!\z80_|execute_|pc_inc_hold~15_combout & (!\z80_|execute_|pc_inc_hold~27_combout & (\z80_|execute_|pc_inc_hold~14_combout & !\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~15_combout ), + .datab(\z80_|execute_|pc_inc_hold~27_combout ), + .datac(\z80_|execute_|pc_inc_hold~14_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~16 .lut_mask = 16'h0010; +defparam \z80_|execute_|pc_inc_hold~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N8 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~22 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~22_combout = (\z80_|execute_|ctl_mRead~34_combout & (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q )))) + + .dataa(\z80_|execute_|ctl_mRead~34_combout ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~22 .lut_mask = 16'h8880; +defparam \z80_|execute_|pc_inc_hold~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~23 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~23_combout = (\z80_|execute_|pc_inc_hold~26_combout & (!\z80_|pla_decode_|Equal19~0_combout & ((\z80_|execute_|ctl_bus_db_oe~1_combout ) # (!\z80_|execute_|ctl_alu_op_low~22_combout )))) + + .dataa(\z80_|execute_|pc_inc_hold~26_combout ), + .datab(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~23 .lut_mask = 16'h080A; +defparam \z80_|execute_|pc_inc_hold~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~24 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~24_combout = (\z80_|execute_|pc_inc_hold~22_combout ) # ((!\z80_|execute_|pc_inc_hold~23_combout & ((\z80_|execute_|ixy_d~5_combout ) # (\z80_|execute_|ctl_alu_op_low~22_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|pc_inc_hold~22_combout ), + .datac(\z80_|execute_|pc_inc_hold~23_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~24 .lut_mask = 16'hCFCE; +defparam \z80_|execute_|pc_inc_hold~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~41 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~41_combout = (((!\z80_|pla_decode_|Equal3~0_combout & !\z80_|pla_decode_|Equal21~0_combout )) # (!\z80_|pla_decode_|Equal24~0_combout )) # (!\z80_|execute_|ctl_alu_op_low~22_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datab(\z80_|pla_decode_|Equal3~0_combout ), + .datac(\z80_|pla_decode_|Equal21~0_combout ), + .datad(\z80_|pla_decode_|Equal24~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~41 .lut_mask = 16'h57FF; +defparam \z80_|execute_|ctl_inc_cy~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~21 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~21_combout = (\z80_|execute_|ctl_mWrite~4_combout & (\z80_|pla_decode_|Equal55~0_combout & ((\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (\z80_|execute_|ctl_mWrite~9_combout )))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datab(\z80_|execute_|ctl_mWrite~4_combout ), + .datac(\z80_|execute_|ctl_mWrite~9_combout ), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~21 .lut_mask = 16'hC800; +defparam \z80_|execute_|pc_inc_hold~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y15_N8 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~25 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~25_combout = ((\z80_|execute_|pc_inc_hold~24_combout ) # ((\z80_|execute_|pc_inc_hold~21_combout ) # (!\z80_|execute_|ctl_inc_cy~41_combout ))) # (!\z80_|execute_|pc_inc_hold~16_combout ) + + .dataa(\z80_|execute_|pc_inc_hold~16_combout ), + .datab(\z80_|execute_|pc_inc_hold~24_combout ), + .datac(\z80_|execute_|ctl_inc_cy~41_combout ), + .datad(\z80_|execute_|pc_inc_hold~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~25 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|pc_inc_hold~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~69 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~69_combout = (!\z80_|execute_|pc_inc_hold~25_combout & (((!\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ctl_alu_op_low~22_combout )) # (!\z80_|pla_decode_|Equal34~0_combout ))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datac(\z80_|execute_|pc_inc_hold~25_combout ), + .datad(\z80_|pla_decode_|Equal34~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~69_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~69 .lut_mask = 16'h010F; +defparam \z80_|execute_|ctl_inc_cy~69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~17 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~17_combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # ((\z80_|interrupts_|DFFE_inst44~q ) # (\z80_|decode_state_|in_halt~q )) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(gnd), + .datac(\z80_|interrupts_|DFFE_inst44~q ), + .datad(\z80_|decode_state_|in_halt~q ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~17 .lut_mask = 16'hFFFA; +defparam \z80_|execute_|pc_inc_hold~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~71 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~71_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (((\z80_|execute_|ctl_inc_cy~70_combout & \z80_|execute_|ctl_inc_cy~69_combout )) # (!\z80_|execute_|pc_inc_hold~17_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|execute_|ctl_inc_cy~70_combout ), + .datac(\z80_|execute_|ctl_inc_cy~69_combout ), + .datad(\z80_|execute_|pc_inc_hold~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~71_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~71 .lut_mask = 16'h80AA; +defparam \z80_|execute_|ctl_inc_cy~71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~44 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~44_combout = (\z80_|execute_|ctl_inc_cy~82_combout & (\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout & ((\z80_|execute_|pc_inc_hold~16_combout ) # (!\z80_|execute_|pc_inc_hold~17_combout )))) # +// (!\z80_|execute_|ctl_inc_cy~82_combout & (((\z80_|execute_|pc_inc_hold~16_combout ) # (!\z80_|execute_|pc_inc_hold~17_combout )))) + + .dataa(\z80_|execute_|ctl_inc_cy~82_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), + .datac(\z80_|execute_|pc_inc_hold~16_combout ), + .datad(\z80_|execute_|pc_inc_hold~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~44 .lut_mask = 16'hD0DD; +defparam \z80_|execute_|ctl_inc_cy~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~42 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~42_combout = (\z80_|execute_|pc_inc_hold~16_combout & \z80_|execute_|ctl_inc_cy~41_combout ) + + .dataa(\z80_|execute_|pc_inc_hold~16_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_inc_cy~41_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~42 .lut_mask = 16'hA0A0; +defparam \z80_|execute_|ctl_inc_cy~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~43 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~43_combout = (\z80_|execute_|ctl_mWrite~17_combout & (\z80_|execute_|ixy_d~5_combout & ((\z80_|execute_|ctl_inc_cy~42_combout ) # (!\z80_|execute_|pc_inc_hold~17_combout )))) + + .dataa(\z80_|execute_|pc_inc_hold~17_combout ), + .datab(\z80_|execute_|ctl_inc_cy~42_combout ), + .datac(\z80_|execute_|ctl_mWrite~17_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~43 .lut_mask = 16'hD000; +defparam \z80_|execute_|ctl_inc_cy~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~57 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~57_combout = (\z80_|execute_|ctl_inc_cy~38_combout ) # ((\z80_|execute_|pc_inc_hold~17_combout & ((\z80_|execute_|pc_inc_hold~12_combout ) # (!\z80_|execute_|pc_inc_hold~7_combout )))) + + .dataa(\z80_|execute_|ctl_inc_cy~38_combout ), + .datab(\z80_|execute_|pc_inc_hold~17_combout ), + .datac(\z80_|execute_|pc_inc_hold~7_combout ), + .datad(\z80_|execute_|pc_inc_hold~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~57_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~57 .lut_mask = 16'hEEAE; +defparam \z80_|execute_|ctl_inc_cy~57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~54 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~54_combout = ((!\z80_|execute_|ctl_alu_op_low~22_combout & ((!\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_T4_ff~q )))) # (!\z80_|pla_decode_|Equal10~0_combout ) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~54_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~54 .lut_mask = 16'h0F7F; +defparam \z80_|execute_|ctl_inc_cy~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~58 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~58_combout = ((!\z80_|execute_|pc_inc_hold~27_combout & (\z80_|execute_|pc_inc_hold~14_combout & !\z80_|execute_|ctl_inc_cy~54_combout ))) # (!\z80_|execute_|ctl_inc_cy~57_combout ) + + .dataa(\z80_|execute_|ctl_inc_cy~57_combout ), + .datab(\z80_|execute_|pc_inc_hold~27_combout ), + .datac(\z80_|execute_|pc_inc_hold~14_combout ), + .datad(\z80_|execute_|ctl_inc_cy~54_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~58_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~58 .lut_mask = 16'h5575; +defparam \z80_|execute_|ctl_inc_cy~58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~18 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~18_combout = (\z80_|execute_|pc_inc_hold~10_combout ) # ((\z80_|execute_|pc_inc_hold~9_combout ) # ((\z80_|execute_|ixy_d~5_combout & \z80_|execute_|ctl_mRead~7_combout ))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_mRead~7_combout ), + .datac(\z80_|execute_|pc_inc_hold~10_combout ), + .datad(\z80_|execute_|pc_inc_hold~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~18 .lut_mask = 16'hFFF8; +defparam \z80_|execute_|pc_inc_hold~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y14_N30 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~19 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~19_combout = (\z80_|execute_|pc_inc_hold~18_combout ) # ((\z80_|execute_|pc_inc_hold~13_combout ) # ((\z80_|execute_|pc_inc_hold~11_combout ) # (!\z80_|execute_|pc_inc_hold~7_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~18_combout ), + .datab(\z80_|execute_|pc_inc_hold~13_combout ), + .datac(\z80_|execute_|pc_inc_hold~7_combout ), + .datad(\z80_|execute_|pc_inc_hold~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~19 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|pc_inc_hold~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~45 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~45_combout = ((\z80_|pla_decode_|Equal9~1_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ixy_d~9_combout )))) # (!\z80_|execute_|ctl_inc_cy~87_combout ) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_inc_cy~87_combout ), + .datad(\z80_|execute_|ixy_d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~45 .lut_mask = 16'hAF8F; +defparam \z80_|execute_|ctl_inc_cy~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~34 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~34_combout = ((!\z80_|execute_|ctl_alu_op_low~22_combout & (!\z80_|execute_|ctl_state_alu~2_combout & !\z80_|execute_|ixy_d~5_combout ))) # (!\z80_|execute_|ctl_mWrite~6_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~34 .lut_mask = 16'h3337; +defparam \z80_|execute_|ctl_inc_cy~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~35 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~35_combout = (\z80_|execute_|ctl_sw_2u~0_combout & (\z80_|execute_|ctl_inc_cy~34_combout & ((!\z80_|pla_decode_|Equal11~0_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_sw_2u~0_combout ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|execute_|ctl_inc_cy~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~35 .lut_mask = 16'h4C00; +defparam \z80_|execute_|ctl_inc_cy~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~46 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~46_combout = (\z80_|pla_decode_|Equal11~0_combout & ((\z80_|execute_|ixy_d~9_combout ) # ((\z80_|execute_|ctl_mWrite~6_combout & \z80_|execute_|ixy_d~7_combout )))) # (!\z80_|pla_decode_|Equal11~0_combout & +// (\z80_|execute_|ctl_mWrite~6_combout & (\z80_|execute_|ixy_d~7_combout ))) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ixy_d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~46 .lut_mask = 16'hEAC0; +defparam \z80_|execute_|ctl_inc_cy~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~47 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~47_combout = ((\z80_|execute_|ctl_inc_cy~46_combout ) # ((\z80_|execute_|ctl_mWrite~6_combout & \z80_|execute_|ctl_mRead~9_combout ))) # (!\z80_|execute_|ctl_inc_cy~39_combout ) + + .dataa(\z80_|execute_|ctl_inc_cy~39_combout ), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datac(\z80_|execute_|ctl_mRead~9_combout ), + .datad(\z80_|execute_|ctl_inc_cy~46_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~47 .lut_mask = 16'hFFD5; +defparam \z80_|execute_|ctl_inc_cy~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~48 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~48_combout = (\z80_|execute_|ctl_inc_cy~47_combout ) # ((\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ) # ((\z80_|pla_decode_|Equal11~0_combout & \z80_|execute_|ctl_alu_op_low~22_combout ))) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datac(\z80_|execute_|ctl_inc_cy~47_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~48 .lut_mask = 16'hFFF8; +defparam \z80_|execute_|ctl_inc_cy~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y18_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~50 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~50_combout = (\z80_|execute_|ctl_inc_cy~45_combout ) # (((\z80_|execute_|ctl_inc_cy~48_combout ) # (!\z80_|execute_|ctl_inc_cy~35_combout )) # (!\z80_|execute_|ctl_inc_cy~49_combout )) + + .dataa(\z80_|execute_|ctl_inc_cy~45_combout ), + .datab(\z80_|execute_|ctl_inc_cy~49_combout ), + .datac(\z80_|execute_|ctl_inc_cy~35_combout ), + .datad(\z80_|execute_|ctl_inc_cy~48_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~50_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~50 .lut_mask = 16'hFFBF; +defparam \z80_|execute_|ctl_inc_cy~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y14_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~51 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~51_combout = (\z80_|execute_|ctl_inc_cy~50_combout & (((!\z80_|execute_|pc_inc_hold~19_combout & \z80_|execute_|pc_inc_hold~8_combout )) # (!\z80_|execute_|pc_inc_hold~17_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~19_combout ), + .datab(\z80_|execute_|pc_inc_hold~17_combout ), + .datac(\z80_|execute_|pc_inc_hold~8_combout ), + .datad(\z80_|execute_|ctl_inc_cy~50_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~51_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~51 .lut_mask = 16'h7300; +defparam \z80_|execute_|ctl_inc_cy~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y14_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~85 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~85_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|execute_|ctl_mRead~6_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|execute_|ctl_mRead~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~85_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~85 .lut_mask = 16'h57FF; +defparam \z80_|execute_|ctl_inc_cy~85 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~63 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~63_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (!\z80_|interrupts_|DFFE_inst44~q & (\z80_|execute_|ctl_mRead~12_combout & !\z80_|decode_state_|in_halt~q ))) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|interrupts_|DFFE_inst44~q ), + .datac(\z80_|execute_|ctl_mRead~12_combout ), + .datad(\z80_|decode_state_|in_halt~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~63_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~63 .lut_mask = 16'h0010; +defparam \z80_|execute_|ctl_inc_cy~63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~64 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~64_combout = (\z80_|execute_|ctl_alu_op_low~22_combout & ((\z80_|execute_|ctl_inc_cy~63_combout ) # ((!\z80_|execute_|ctl_reg_sys_hilo~21_combout & !\z80_|execute_|pc_inc_hold~9_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo~21_combout ), + .datab(\z80_|execute_|ctl_inc_cy~63_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datad(\z80_|execute_|pc_inc_hold~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~64_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~64 .lut_mask = 16'hC0D0; +defparam \z80_|execute_|ctl_inc_cy~64 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~65 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~65_combout = (\z80_|execute_|ctl_inc_cy~64_combout ) # ((\z80_|execute_|ctl_mRead~13_combout & (\z80_|execute_|ctl_alu_shift_oe~14_combout & !\z80_|execute_|pc_inc_hold~18_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~13_combout ), + .datab(\z80_|execute_|ctl_inc_cy~64_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datad(\z80_|execute_|pc_inc_hold~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~65_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~65 .lut_mask = 16'hCCEC; +defparam \z80_|execute_|ctl_inc_cy~65 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~59 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~59_combout = (((!\z80_|pla_decode_|Equal55~0_combout ) # (!\z80_|execute_|ctl_alu_op_low~22_combout )) # (!\z80_|pla_decode_|Equal6~0_combout )) # (!\z80_|pla_decode_|Equal33~1_combout ) + + .dataa(\z80_|pla_decode_|Equal33~1_combout ), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~59_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~59 .lut_mask = 16'h7FFF; +defparam \z80_|execute_|ctl_inc_cy~59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~60 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~60_combout = ((\z80_|execute_|ctl_inc_cy~59_combout & (!\z80_|execute_|pc_inc_hold~9_combout & !\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ))) # (!\z80_|execute_|pc_inc_hold~17_combout ) + + .dataa(\z80_|execute_|ctl_inc_cy~59_combout ), + .datab(\z80_|execute_|pc_inc_hold~9_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ), + .datad(\z80_|execute_|pc_inc_hold~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~60_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~60 .lut_mask = 16'h02FF; +defparam \z80_|execute_|ctl_inc_cy~60 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~61 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~61_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|execute_|ctl_mRead~8_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|execute_|ctl_mRead~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~61_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~61 .lut_mask = 16'h57FF; +defparam \z80_|execute_|ctl_inc_cy~61 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y14_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~62 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~62_combout = (\z80_|execute_|pc_inc_hold~12_combout & (\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & (\z80_|execute_|ctl_inc_cy~60_combout ))) # (!\z80_|execute_|pc_inc_hold~12_combout & +// (((\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & \z80_|execute_|ctl_inc_cy~60_combout )) # (!\z80_|execute_|ctl_inc_cy~61_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~12_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), + .datac(\z80_|execute_|ctl_inc_cy~60_combout ), + .datad(\z80_|execute_|ctl_inc_cy~61_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~62_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~62 .lut_mask = 16'hC0D5; +defparam \z80_|execute_|ctl_inc_cy~62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y14_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~66 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~66_combout = (\z80_|execute_|ctl_inc_cy~65_combout ) # ((\z80_|execute_|ctl_inc_cy~62_combout ) # ((!\z80_|execute_|ctl_inc_cy~85_combout & !\z80_|execute_|pc_inc_hold~19_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~85_combout ), + .datab(\z80_|execute_|ctl_inc_cy~65_combout ), + .datac(\z80_|execute_|pc_inc_hold~19_combout ), + .datad(\z80_|execute_|ctl_inc_cy~62_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~66_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~66 .lut_mask = 16'hFFCD; +defparam \z80_|execute_|ctl_inc_cy~66 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~53 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~53_combout = ((\z80_|execute_|ixy_d~5_combout & ((\z80_|pla_decode_|Equal41~2_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) # (!\z80_|execute_|ctl_reg_sel_pc~7_combout ) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~7_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datad(\z80_|pla_decode_|Equal41~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~53_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~53 .lut_mask = 16'hBB3B; +defparam \z80_|execute_|ctl_inc_cy~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~52 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~52_combout = (\z80_|execute_|ctl_mRead~2_combout ) # ((\z80_|execute_|ctl_mWrite~8_combout ) # ((\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~8_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~2_combout ), + .datab(\z80_|execute_|ctl_mWrite~8_combout ), + .datac(\z80_|pla_decode_|Equal34~0_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~52_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~52 .lut_mask = 16'hFEFF; +defparam \z80_|execute_|ctl_inc_cy~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~84 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~84_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & ((\z80_|execute_|ctl_inc_cy~52_combout ) # (!\z80_|execute_|fMRead~7_combout )))) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|execute_|ctl_inc_cy~52_combout ), + .datac(\z80_|execute_|fMRead~7_combout ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~84_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~84 .lut_mask = 16'h8A00; +defparam \z80_|execute_|ctl_inc_cy~84 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|pla_decode_|Equal8~0_combout & \z80_|execute_|ctl_mWrite~4_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|pla_decode_|Equal8~0_combout ), + .datad(\z80_|execute_|ctl_mWrite~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~55 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~55_combout = ((\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ) # ((!\z80_|execute_|ctl_inc_cy~54_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ))) # (!\z80_|execute_|ctl_reg_sys_we~2_combout ) + + .dataa(\z80_|execute_|ctl_reg_sys_we~2_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), + .datad(\z80_|execute_|ctl_inc_cy~54_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~55_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~55 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_inc_cy~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y14_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~56 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~56_combout = (!\z80_|execute_|pc_inc_hold~17_combout & ((\z80_|execute_|ctl_inc_cy~53_combout ) # ((\z80_|execute_|ctl_inc_cy~84_combout ) # (\z80_|execute_|ctl_inc_cy~55_combout )))) + + .dataa(\z80_|execute_|ctl_inc_cy~53_combout ), + .datab(\z80_|execute_|ctl_inc_cy~84_combout ), + .datac(\z80_|execute_|pc_inc_hold~17_combout ), + .datad(\z80_|execute_|ctl_inc_cy~55_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~56_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~56 .lut_mask = 16'h0F0E; +defparam \z80_|execute_|ctl_inc_cy~56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~67 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~67_combout = (\z80_|execute_|ctl_inc_cy~58_combout ) # ((\z80_|execute_|ctl_inc_cy~51_combout ) # ((\z80_|execute_|ctl_inc_cy~66_combout ) # (\z80_|execute_|ctl_inc_cy~56_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~58_combout ), + .datab(\z80_|execute_|ctl_inc_cy~51_combout ), + .datac(\z80_|execute_|ctl_inc_cy~66_combout ), + .datad(\z80_|execute_|ctl_inc_cy~56_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~67_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~67 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_inc_cy~67 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y14_N20 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~20 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~20_combout = (\z80_|execute_|pc_inc_hold~19_combout ) # ((\z80_|execute_|pc_inc_hold~27_combout ) # ((\z80_|execute_|pc_inc_hold~15_combout ) # (!\z80_|execute_|pc_inc_hold~8_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~19_combout ), + .datab(\z80_|execute_|pc_inc_hold~27_combout ), + .datac(\z80_|execute_|pc_inc_hold~8_combout ), + .datad(\z80_|execute_|pc_inc_hold~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~20 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|pc_inc_hold~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y15_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~83 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~83_combout = (\z80_|execute_|ctl_state_alu~6_combout & (\z80_|sequencer_|DFFE_M2_ff~q & (!\z80_|execute_|pc_inc_hold~20_combout & \z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|execute_|ctl_state_alu~6_combout ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|execute_|pc_inc_hold~20_combout ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~83_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~83 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_inc_cy~83 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~68 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~68_combout = (\z80_|execute_|ctl_inc_cy~44_combout ) # ((\z80_|execute_|ctl_inc_cy~43_combout ) # ((\z80_|execute_|ctl_inc_cy~67_combout ) # (\z80_|execute_|ctl_inc_cy~83_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~44_combout ), + .datab(\z80_|execute_|ctl_inc_cy~43_combout ), + .datac(\z80_|execute_|ctl_inc_cy~67_combout ), + .datad(\z80_|execute_|ctl_inc_cy~83_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~68_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~68 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_inc_cy~68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N30 +cycloneive_lcell_comb \z80_|address_latch_|Q[0]~feeder ( +// Equation(s): +// \z80_|address_latch_|Q[0]~feeder_combout = \z80_|address_latch_|abusz [0] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [0]), + .cin(gnd), + .combout(\z80_|address_latch_|Q[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|Q[0]~feeder .lut_mask = 16'hFF00; +defparam \z80_|address_latch_|Q[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y11_N31 +dffeas \z80_|address_latch_|Q[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|Q[0]~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[0] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~72 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~72_combout = (\z80_|execute_|pc_inc_hold~16_combout & (\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout & (\z80_|execute_|ctl_inc_cy~41_combout & !\z80_|execute_|pc_inc_hold~21_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~16_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ), + .datac(\z80_|execute_|ctl_inc_cy~41_combout ), + .datad(\z80_|execute_|pc_inc_hold~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~72_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~72 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_inc_cy~72 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y18_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~73 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~73_combout = (\z80_|execute_|ixy_d~9_combout ) # ((\z80_|execute_|ctl_alu_oe~0_combout ) # ((\z80_|sequencer_|DFFE_M4_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|execute_|ixy_d~9_combout ), + .datac(\z80_|execute_|ctl_alu_oe~0_combout ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~73_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~73 .lut_mask = 16'hFEFC; +defparam \z80_|execute_|ctl_inc_cy~73 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y18_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~74 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~74_combout = ((\z80_|pla_decode_|Equal19~0_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # (\z80_|execute_|ctl_inc_cy~73_combout )))) # (!\z80_|execute_|ctl_inc_cy~86_combout ) + + .dataa(\z80_|execute_|ctl_inc_cy~86_combout ), + .datab(\z80_|pla_decode_|Equal19~0_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|execute_|ctl_inc_cy~73_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~74_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~74 .lut_mask = 16'hDDD5; +defparam \z80_|execute_|ctl_inc_cy~74 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~75 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~75_combout = (\z80_|execute_|ctl_inc_cy~72_combout ) # ((\z80_|execute_|ctl_inc_cy~74_combout & ((!\z80_|execute_|pc_inc_hold~17_combout ) # (!\z80_|execute_|pc_inc_hold~25_combout )))) + + .dataa(\z80_|execute_|ctl_inc_cy~72_combout ), + .datab(\z80_|execute_|pc_inc_hold~25_combout ), + .datac(\z80_|execute_|ctl_inc_cy~74_combout ), + .datad(\z80_|execute_|pc_inc_hold~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~75_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~75 .lut_mask = 16'hBAFA; +defparam \z80_|execute_|ctl_inc_cy~75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~76 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~76_combout = (((!\z80_|execute_|ctl_inc_cy~40_combout ) # (!\z80_|execute_|ctl_inc_cy~37_combout )) # (!\z80_|execute_|ctl_inc_cy~33_combout )) # (!\z80_|execute_|ctl_inc_cy~32_combout ) + + .dataa(\z80_|execute_|ctl_inc_cy~32_combout ), + .datab(\z80_|execute_|ctl_inc_cy~33_combout ), + .datac(\z80_|execute_|ctl_inc_cy~37_combout ), + .datad(\z80_|execute_|ctl_inc_cy~40_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~76_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~76 .lut_mask = 16'h7FFF; +defparam \z80_|execute_|ctl_inc_cy~76 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y18_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~80 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~80_combout = (\z80_|execute_|ctl_inc_cy~76_combout ) # ((!\z80_|execute_|ctl_inc_cy~36_combout ) # (!\z80_|execute_|ctl_inc_cy~79_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_inc_cy~76_combout ), + .datac(\z80_|execute_|ctl_inc_cy~79_combout ), + .datad(\z80_|execute_|ctl_inc_cy~36_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~80_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~80 .lut_mask = 16'hCFFF; +defparam \z80_|execute_|ctl_inc_cy~80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~81 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~81_combout = (\z80_|execute_|ctl_inc_cy~75_combout ) # ((\z80_|execute_|ctl_inc_cy~80_combout & ((\z80_|execute_|ctl_inc_cy~69_combout ) # (!\z80_|execute_|pc_inc_hold~17_combout )))) + + .dataa(\z80_|execute_|pc_inc_hold~17_combout ), + .datab(\z80_|execute_|ctl_inc_cy~69_combout ), + .datac(\z80_|execute_|ctl_inc_cy~75_combout ), + .datad(\z80_|execute_|ctl_inc_cy~80_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~81_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~81 .lut_mask = 16'hFDF0; +defparam \z80_|execute_|ctl_inc_cy~81 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N20 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout = \z80_|address_latch_|Q [0] $ (((\z80_|execute_|ctl_inc_cy~71_combout ) # ((\z80_|execute_|ctl_inc_cy~68_combout ) # (\z80_|execute_|ctl_inc_cy~81_combout )))) + + .dataa(\z80_|execute_|ctl_inc_cy~71_combout ), + .datab(\z80_|execute_|ctl_inc_cy~68_combout ), + .datac(\z80_|address_latch_|Q [0]), + .datad(\z80_|execute_|ctl_inc_cy~81_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out .lut_mask = 16'h0F1E; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N10 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~3 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[0]~3_combout = ((\z80_|reg_file_|db_lo_as[0]~1_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .datab(\z80_|reg_file_|db_lo_as[0]~1_combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), + .datad(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[0]~3 .lut_mask = 16'hC4FF; +defparam \z80_|reg_file_|db_lo_as[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y11_N1 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N10 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[0]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_lo|latch[0]~feeder_combout = \z80_|reg_file_|gdfx_temp0[0]~22_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[0]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y11_N11 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_af_lo|latch[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~13 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~13_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [0]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~13 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[0]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y14_N9 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~12 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~12_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [0] & ((\z80_|alu_control_|db[0]~12_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|alu_control_|db[0]~12_combout ) # ((!\z80_|execute_|ctl_reg_in_lo~8_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datab(\z80_|alu_control_|db[0]~12_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [0]), + .datad(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~12 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[0]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N8 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_lo|latch[0]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_de_lo|latch[0]~feeder_combout = \z80_|reg_file_|gdfx_temp0[0]~22_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_de_lo|latch[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[0]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y11_N9 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_de_lo|latch[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y11_N27 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~10 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~10_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [0] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [0] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [0]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~10 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp0[0]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y12_N3 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N2 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0_combout = ((\z80_|execute_|ctl_reg_gp_we~8_combout ) # ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]) # (!\z80_|reg_control_|reg_sel_hl2~0_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]), + .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0 .lut_mask = 16'hFDFF; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y12_N9 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~11 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~11_combout = (\z80_|reg_file_|gdfx_temp0[0]~10_combout & (\z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0_combout & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp0[0]~10_combout ), + .datab(\z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_hl_lo|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~11 .lut_mask = 16'h8088; +defparam \z80_|reg_file_|gdfx_temp0[0]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N2 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder_combout = \z80_|reg_file_|gdfx_temp0[0]~22_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y14_N3 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X32_Y13_N13 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~14 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~14_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (\z80_|reg_file_|b2v_latch_ix_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [0]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [0]), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~14 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[0]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y13_N11 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N20 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_sp_lo|latch[0]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_sp_lo|latch[0]~feeder_combout = \z80_|reg_file_|gdfx_temp0[0]~22_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_sp_lo|latch[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[0]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y12_N21 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_sp_lo|latch[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X31_Y12_N17 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~15 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~15_combout = (\z80_|reg_file_|b2v_latch_sp_lo|latch [0] & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # (!\z80_|reg_file_|b2v_latch_sp_lo|latch [0] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_sp_lo|latch [0]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_iy_lo|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~15 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp0[0]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~16 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~16_combout = (\z80_|reg_file_|gdfx_temp0[0]~14_combout & (\z80_|reg_file_|gdfx_temp0[0]~15_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp0[0]~14_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [0]), + .datad(\z80_|reg_file_|gdfx_temp0[0]~15_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~16 .lut_mask = 16'hA200; +defparam \z80_|reg_file_|gdfx_temp0[0]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~17 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~17_combout = (\z80_|reg_file_|gdfx_temp0[0]~13_combout & (\z80_|reg_file_|gdfx_temp0[0]~12_combout & (\z80_|reg_file_|gdfx_temp0[0]~11_combout & \z80_|reg_file_|gdfx_temp0[0]~16_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[0]~13_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~12_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[0]~11_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~16_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~17 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[0]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~22 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~22_combout = ((\z80_|reg_file_|gdfx_temp0[0]~17_combout & ((\z80_|reg_file_|db_lo_as[0]~3_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .datac(\z80_|reg_file_|db_lo_as[0]~3_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~17_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~22 .lut_mask = 16'hF733; +defparam \z80_|reg_file_|gdfx_temp0[0]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N22 +cycloneive_lcell_comb \z80_|alu_control_|db[0]~9 ( +// Equation(s): +// \z80_|alu_control_|db[0]~9_combout = (\z80_|sw2_|db_up[0]~0_combout & (\z80_|alu_control_|db[0]~8_combout & ((\z80_|reg_file_|gdfx_temp0[0]~22_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) + + .dataa(\z80_|sw2_|db_up[0]~0_combout ), + .datab(\z80_|alu_control_|db[0]~8_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[0]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[0]~9 .lut_mask = 16'h8088; +defparam \z80_|alu_control_|db[0]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N0 +cycloneive_lcell_comb \z80_|alu_control_|db[0]~12 ( +// Equation(s): +// \z80_|alu_control_|db[0]~12_combout = ((\z80_|alu_control_|db[0]~9_combout & ((\z80_|alu_flags_|flags_cf~combout ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) + + .dataa(\z80_|alu_flags_|flags_cf~combout ), + .datab(\z80_|execute_|ctl_flags_oe~2_combout ), + .datac(\z80_|alu_control_|db[0]~9_combout ), + .datad(\z80_|alu_control_|db[6]~11_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[0]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[0]~12 .lut_mask = 16'hB0FF; +defparam \z80_|alu_control_|db[0]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N2 +cycloneive_lcell_comb \z80_|address_latch_|abusz[8] ( +// Equation(s): +// \z80_|address_latch_|abusz [8] = (\z80_|reg_file_|db_hi_as[0]~6_combout & !\z80_|resets_|clrpc~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|reg_file_|db_hi_as[0]~6_combout ), + .datad(\z80_|resets_|clrpc~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [8]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[8] .lut_mask = 16'h00F0; +defparam \z80_|address_latch_|abusz[8] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y10_N3 +dffeas \z80_|address_latch_|Q[8] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [8]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [8]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[8] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N4 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout = \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout $ (\z80_|address_latch_|Q [7]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), + .datad(\z80_|address_latch_|Q [7]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out .lut_mask = 16'h0FF0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y12_N21 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y12_N11 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~84 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~84_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (\z80_|reg_file_|b2v_latch_hl_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl_lo|latch [7]), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~84_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~84 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp0[7]~84 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N20 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_lo|latch[7]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_de_lo|latch[7]~feeder_combout = \z80_|reg_file_|gdfx_temp0[7]~91_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_de_lo|latch[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[7]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y11_N21 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_de_lo|latch[7]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y11_N7 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~83 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~83_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [7] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [7] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [7]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~83_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~83 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp0[7]~83 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y12_N29 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~88 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~88_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [7] & ((\z80_|alu_control_|db[7]~19_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|alu_control_|db[7]~19_combout ) # ((!\z80_|execute_|ctl_reg_in_lo~8_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datab(\z80_|alu_control_|db[7]~19_combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [7]), + .datad(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~88_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~88 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[7]~88 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y14_N25 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X32_Y14_N23 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~86 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~86_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [7]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [7]), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~86_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~86 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[7]~86 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y12_N25 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X31_Y12_N27 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~87 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~87_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (\z80_|reg_file_|b2v_latch_ix_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [7]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_iy_lo|latch [7]), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~87_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~87 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[7]~87 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y12_N29 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N28 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_wz_lo|db[7]~0 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_wz_lo|db[7]~0_combout = (\z80_|reg_control_|reg_sys_we_lo~combout ) # (((\z80_|reg_file_|b2v_latch_wz_lo|latch [7]) # (!\z80_|execute_|ctl_reg_sel_wz~18_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[0]~31_combout )) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~31_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [7]), + .datad(\z80_|execute_|ctl_reg_sel_wz~18_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_wz_lo|db[7]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|db[7]~0 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_wz_lo|db[7]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~89 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~89_combout = (\z80_|reg_file_|gdfx_temp0[7]~88_combout & (\z80_|reg_file_|gdfx_temp0[7]~86_combout & (\z80_|reg_file_|gdfx_temp0[7]~87_combout & \z80_|reg_file_|b2v_latch_wz_lo|db[7]~0_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[7]~88_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[7]~86_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[7]~87_combout ), + .datad(\z80_|reg_file_|b2v_latch_wz_lo|db[7]~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~89_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~89 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[7]~89 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y11_N29 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X32_Y11_N7 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~85 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~85_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [7]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [7]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~85_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~85 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[7]~85 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~90 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~90_combout = (\z80_|reg_file_|gdfx_temp0[7]~84_combout & (\z80_|reg_file_|gdfx_temp0[7]~83_combout & (\z80_|reg_file_|gdfx_temp0[7]~89_combout & \z80_|reg_file_|gdfx_temp0[7]~85_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[7]~84_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[7]~83_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[7]~89_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[7]~85_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~90 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[7]~90 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~91 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~91_combout = ((\z80_|reg_file_|gdfx_temp0[7]~90_combout & ((\z80_|reg_file_|db_lo_as[7]~24_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .datac(\z80_|execute_|ctl_sw_4u~6_combout ), + .datad(\z80_|reg_file_|db_lo_as[7]~24_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~91 .lut_mask = 16'hBB3B; +defparam \z80_|reg_file_|gdfx_temp0[7]~91 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y12_N15 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[7]~24_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N14 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~22 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[7]~22_combout = (\z80_|reg_file_|gdfx_temp0[7]~91_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) # (!\z80_|reg_file_|gdfx_temp0[7]~91_combout & +// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [7]), + .datad(\z80_|execute_|ctl_sw_4d~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[7]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[7]~22 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|db_lo_as[7]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y12_N13 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[7]~24_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N18 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~23 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[7]~23_combout = (\z80_|reg_file_|db_lo_as[7]~22_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(\z80_|reg_file_|db_lo_as[7]~22_combout ), + .datab(gnd), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [7]), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[7]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[7]~23 .lut_mask = 16'hAA0A; +defparam \z80_|reg_file_|db_lo_as[7]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N12 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~24 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[7]~24_combout = ((\z80_|reg_file_|db_lo_as[7]~23_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), + .datab(\z80_|reg_file_|db_lo_as[7]~23_combout ), + .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[7]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[7]~24 .lut_mask = 16'h8FCF; +defparam \z80_|reg_file_|db_lo_as[7]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N6 +cycloneive_lcell_comb \z80_|address_latch_|abusz[7] ( +// Equation(s): +// \z80_|address_latch_|abusz [7] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[7]~24_combout ) + + .dataa(\z80_|resets_|clrpc~0_combout ), + .datab(gnd), + .datac(\z80_|reg_file_|db_lo_as[7]~24_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [7]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[7] .lut_mask = 16'h5050; +defparam \z80_|address_latch_|abusz[7] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N16 +cycloneive_lcell_comb \z80_|address_latch_|Q[7]~feeder ( +// Equation(s): +// \z80_|address_latch_|Q[7]~feeder_combout = \z80_|address_latch_|abusz [7] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [7]), + .cin(gnd), + .combout(\z80_|address_latch_|Q[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|Q[7]~feeder .lut_mask = 16'hFF00; +defparam \z80_|address_latch_|Q[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y13_N17 +dffeas \z80_|address_latch_|Q[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|Q[7]~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[7] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N10 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout = \z80_|address_latch_|Q [8] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout & (\z80_|execute_|ctl_inc_dec~11_combout $ (\z80_|address_latch_|Q [7]))))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), + .datab(\z80_|address_latch_|Q [8]), + .datac(\z80_|execute_|ctl_inc_dec~11_combout ), + .datad(\z80_|address_latch_|Q [7]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out .lut_mask = 16'hC66C; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y14_N23 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[0]~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X35_Y14_N29 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[0]~6_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N28 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~4 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[0]~4_combout = (\z80_|reg_control_|reg_sw_4d_hi~0_combout & (\z80_|reg_file_|gdfx_temp1[0]~30_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) + + .dataa(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [0]), + .datad(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[0]~4 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|db_hi_as[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N0 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~5 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[0]~5_combout = (\z80_|reg_file_|db_hi_as[0]~4_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [0]), + .datad(\z80_|reg_file_|db_hi_as[0]~4_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[0]~5 .lut_mask = 16'hF300; +defparam \z80_|reg_file_|db_hi_as[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N22 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~6 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[0]~6_combout = ((\z80_|reg_file_|db_hi_as[0]~5_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), + .datab(\z80_|reg_file_|db_hi_as[0]~5_combout ), + .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[0]~6 .lut_mask = 16'h8FCF; +defparam \z80_|reg_file_|db_hi_as[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y14_N27 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X37_Y14_N13 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~23 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~23_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (\z80_|reg_file_|b2v_latch_hl_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_hl2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (((\z80_|reg_file_|b2v_latch_hl2_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [0]), + .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~23 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[0]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y16_N27 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X35_Y16_N5 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~25 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~25_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_iy_hi|latch [0]), + .datad(\z80_|reg_file_|b2v_latch_ix_hi|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~25 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[0]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y15_N11 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X35_Y15_N13 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~27 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~27_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (\z80_|reg_file_|b2v_latch_wz_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (((\z80_|reg_file_|b2v_latch_sp_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .datab(\z80_|reg_file_|b2v_latch_wz_hi|latch [0]), + .datac(\z80_|reg_file_|b2v_latch_sp_hi|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~27 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[0]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y16_N27 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X37_Y16_N25 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~24 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~24_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (\z80_|reg_file_|b2v_latch_bc2_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc_hi|latch [0]), + .datad(\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~24 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[0]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y16_N27 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~26 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~26_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout & (\z80_|alu_|db[0]~14_combout & ((\z80_|reg_file_|b2v_latch_af2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # +// (!\z80_|execute_|ctl_reg_in_hi~12_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .datab(\z80_|alu_|db[0]~14_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~26 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[0]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~28 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~28_combout = (\z80_|reg_file_|gdfx_temp1[0]~25_combout & (\z80_|reg_file_|gdfx_temp1[0]~27_combout & (\z80_|reg_file_|gdfx_temp1[0]~24_combout & \z80_|reg_file_|gdfx_temp1[0]~26_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~25_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[0]~27_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~24_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[0]~26_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~28 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[0]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y15_N17 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N16 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[0]~11 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[0]~11_combout = (\z80_|execute_|ctl_reg_gp_we~8_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [0]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [0]), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[0]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[0]~11 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[0]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y15_N11 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N16 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_hi|latch[0]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_de_hi|latch[0]~feeder_combout = \z80_|reg_file_|gdfx_temp1[0]~30_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_de_hi|latch[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[0]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y15_N17 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_de_hi|latch[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~22 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~22_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [0]), + .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~22 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[0]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~29 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~29_combout = (\z80_|reg_file_|gdfx_temp1[0]~23_combout & (\z80_|reg_file_|gdfx_temp1[0]~28_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[0]~11_combout & \z80_|reg_file_|gdfx_temp1[0]~22_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~23_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[0]~28_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|db[0]~11_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[0]~22_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~29 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[0]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~30 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~30_combout = ((\z80_|reg_file_|gdfx_temp1[0]~29_combout & ((\z80_|reg_file_|db_hi_as[0]~6_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[0]~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[0]~29_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datad(\z80_|execute_|ctl_sw_4u~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~30 .lut_mask = 16'h8FCF; +defparam \z80_|reg_file_|gdfx_temp1[0]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N12 +cycloneive_lcell_comb \z80_|alu_|db[0]~13 ( +// Equation(s): +// \z80_|alu_|db[0]~13_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[0]~30_combout & ((\z80_|alu_|db_low[0]~24_combout ) # (!\z80_|execute_|ctl_alu_oe~11_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & +// (((\z80_|alu_|db_low[0]~24_combout ) # (!\z80_|execute_|ctl_alu_oe~11_combout )))) + + .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .datac(\z80_|alu_|db_low[0]~24_combout ), + .datad(\z80_|execute_|ctl_alu_oe~11_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[0]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[0]~13 .lut_mask = 16'hD0DD; +defparam \z80_|alu_|db[0]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N22 +cycloneive_lcell_comb \z80_|alu_|db[0]~14 ( +// Equation(s): +// \z80_|alu_|db[0]~14_combout = ((\z80_|alu_|db[0]~13_combout & ((\z80_|alu_control_|db[0]~12_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|alu_control_|db[0]~12_combout ), + .datab(\z80_|alu_|db[7]~9_combout ), + .datac(\z80_|execute_|ctl_sw_2d~13_combout ), + .datad(\z80_|alu_|db[0]~13_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[0]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[0]~14 .lut_mask = 16'hBF33; +defparam \z80_|alu_|db[0]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N12 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~10 ( +// Equation(s): +// \z80_|alu_|db_low[1]~10_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[2]~16_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[0]~14_combout ))) + + .dataa(\z80_|alu_|db[2]~16_combout ), + .datab(\z80_|alu_|db[0]~14_combout ), + .datac(gnd), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~10 .lut_mask = 16'hAACC; +defparam \z80_|alu_|db_low[1]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N10 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~11 ( +// Equation(s): +// \z80_|alu_|db_low[1]~11_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_low[1]~10_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[1]~10_combout )) + + .dataa(\z80_|alu_|db[1]~10_combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .datac(gnd), + .datad(\z80_|alu_|db_low[1]~10_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~11 .lut_mask = 16'hEE22; +defparam \z80_|alu_|db_low[1]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N22 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~8 ( +// Equation(s): +// \z80_|alu_|db_low[1]~8_combout = (\z80_|execute_|ctl_alu_op2_oe~0_combout & (\z80_|alu_|op2_low [1] & ((\z80_|alu_|op1_low [1]) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout & (((\z80_|alu_|op1_low [1]) # +// (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datab(\z80_|alu_|op2_low [1]), + .datac(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datad(\z80_|alu_|op1_low [1]), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~8 .lut_mask = 16'hDD0D; +defparam \z80_|alu_|db_low[1]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N2 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~7 ( +// Equation(s): +// \z80_|alu_|db_low[1]~7_combout = ((\z80_|bus_control_|db[3]~21_combout & (!\z80_|bus_control_|db[5]~15_combout & !\z80_|bus_control_|db[4]~19_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) + + .dataa(\z80_|bus_control_|db[3]~21_combout ), + .datab(\z80_|bus_control_|db[5]~15_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datad(\z80_|bus_control_|db[4]~19_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~7 .lut_mask = 16'h0F2F; +defparam \z80_|alu_|db_low[1]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N4 +cycloneive_lcell_comb \z80_|alu_|result_lo[1]~feeder ( +// Equation(s): +// \z80_|alu_|result_lo[1]~feeder_combout = \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|result_lo[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|result_lo[1]~feeder .lut_mask = 16'hFF00; +defparam \z80_|alu_|result_lo[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y18_N5 +dffeas \z80_|alu_|result_lo[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|result_lo[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_alu_op_low~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|result_lo [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|result_lo[1] .is_wysiwyg = "true"; +defparam \z80_|alu_|result_lo[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N4 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~9 ( +// Equation(s): +// \z80_|alu_|db_low[1]~9_combout = (\z80_|alu_|db_low[1]~8_combout & (\z80_|alu_|db_low[1]~7_combout & ((\z80_|execute_|ctl_alu_res_oe~3_combout ) # (\z80_|alu_|result_lo [1])))) + + .dataa(\z80_|alu_|db_low[1]~8_combout ), + .datab(\z80_|alu_|db_low[1]~7_combout ), + .datac(\z80_|execute_|ctl_alu_res_oe~3_combout ), + .datad(\z80_|alu_|result_lo [1]), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~9 .lut_mask = 16'h8880; +defparam \z80_|alu_|db_low[1]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N26 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~12 ( +// Equation(s): +// \z80_|alu_|db_low[1]~12_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout & (\z80_|alu_|db_low[1]~11_combout & ((\z80_|alu_|db_low[1]~9_combout )))) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout & (((\z80_|alu_|db_low[1]~9_combout ) # +// (!\z80_|alu_|db_high[3]~0_combout )))) + + .dataa(\z80_|alu_|db_low[1]~11_combout ), + .datab(\z80_|alu_|db_high[3]~0_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datad(\z80_|alu_|db_low[1]~9_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~12 .lut_mask = 16'hAF03; +defparam \z80_|alu_|db_low[1]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N2 +cycloneive_lcell_comb \z80_|alu_|db[1]~8 ( +// Equation(s): +// \z80_|alu_|db[1]~8_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[1]~21_combout & ((\z80_|alu_control_|db[1]~26_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & +// (((\z80_|alu_control_|db[1]~26_combout )) # (!\z80_|execute_|ctl_sw_2d~13_combout ))) + + .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .datab(\z80_|execute_|ctl_sw_2d~13_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .datad(\z80_|alu_control_|db[1]~26_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[1]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[1]~8 .lut_mask = 16'hF531; +defparam \z80_|alu_|db[1]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N18 +cycloneive_lcell_comb \z80_|alu_|db[1]~10 ( +// Equation(s): +// \z80_|alu_|db[1]~10_combout = ((\z80_|alu_|db[1]~8_combout & ((\z80_|alu_|db_low[1]~12_combout ) # (!\z80_|execute_|ctl_alu_oe~11_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|execute_|ctl_alu_oe~11_combout ), + .datab(\z80_|alu_|db[7]~9_combout ), + .datac(\z80_|alu_|db_low[1]~12_combout ), + .datad(\z80_|alu_|db[1]~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[1]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[1]~10 .lut_mask = 16'hF733; +defparam \z80_|alu_|db[1]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y16_N11 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~12 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~12_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout & (\z80_|alu_|db[1]~10_combout & ((\z80_|reg_file_|b2v_latch_af2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # +// (!\z80_|execute_|ctl_reg_in_hi~12_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .datab(\z80_|alu_|db[1]~10_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~12 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[1]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N4 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder_combout = \z80_|reg_file_|gdfx_temp1[1]~21_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y16_N5 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X35_Y16_N1 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~11 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~11_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datab(\z80_|reg_file_|b2v_latch_iy_hi|latch [1]), + .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~11 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[1]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y16_N11 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X37_Y16_N17 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~10 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~10_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (\z80_|reg_file_|b2v_latch_bc2_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]), + .datad(\z80_|reg_file_|b2v_latch_bc_hi|latch [1]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~10 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[1]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y15_N3 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X35_Y15_N1 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~13 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~13_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (\z80_|reg_file_|b2v_latch_wz_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [1]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [1]), + .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~13 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp1[1]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~14 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~14_combout = (\z80_|reg_file_|gdfx_temp1[1]~12_combout & (\z80_|reg_file_|gdfx_temp1[1]~11_combout & (\z80_|reg_file_|gdfx_temp1[1]~10_combout & \z80_|reg_file_|gdfx_temp1[1]~13_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[1]~12_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[1]~11_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[1]~10_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[1]~13_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~14 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[1]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y15_N25 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N24 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[1]~10 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[1]~10_combout = (\z80_|execute_|ctl_reg_gp_we~8_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [1]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [1]), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[1]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[1]~10 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[1]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y14_N29 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X37_Y14_N11 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~9 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~9_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (\z80_|reg_file_|b2v_latch_hl_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_hl2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (((\z80_|reg_file_|b2v_latch_hl2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [1]), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~9 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[1]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y15_N7 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N20 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_hi|latch[1]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_de_hi|latch[1]~feeder_combout = \z80_|reg_file_|gdfx_temp1[1]~21_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_de_hi|latch[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[1]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y15_N21 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_de_hi|latch[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~8 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~8_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [1]), + .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [1]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~8 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[1]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~15 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~15_combout = (\z80_|reg_file_|gdfx_temp1[1]~14_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[1]~10_combout & (\z80_|reg_file_|gdfx_temp1[1]~9_combout & \z80_|reg_file_|gdfx_temp1[1]~8_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[1]~14_combout ), + .datab(\z80_|reg_file_|b2v_latch_af_hi|db[1]~10_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[1]~9_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[1]~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~15 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~21 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~21_combout = ((\z80_|reg_file_|gdfx_temp1[1]~15_combout & ((\z80_|reg_file_|db_hi_as[1]~3_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[1]~15_combout ), + .datac(\z80_|reg_file_|db_hi_as[1]~3_combout ), + .datad(\z80_|execute_|ctl_sw_4u~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~21 .lut_mask = 16'hD5DD; +defparam \z80_|reg_file_|gdfx_temp1[1]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y14_N25 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[1]~3_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N24 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~0 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[1]~0_combout = (\z80_|reg_file_|gdfx_temp1[1]~21_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # (!\z80_|reg_file_|gdfx_temp1[1]~21_combout & +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[1]~0 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|db_hi_as[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N20 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~1 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[1]~1_combout = (\z80_|reg_file_|db_hi_as[1]~0_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_pc_hi|latch [1]), + .datab(\z80_|reg_file_|db_hi_as[1]~0_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[1]~1 .lut_mask = 16'h88CC; +defparam \z80_|reg_file_|db_hi_as[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N30 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~3 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[1]~3_combout = ((\z80_|reg_file_|db_hi_as[1]~1_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), + .datab(\z80_|reg_file_|db_hi_as[1]~1_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .datad(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[1]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[1]~3 .lut_mask = 16'h8CFF; +defparam \z80_|reg_file_|db_hi_as[1]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N24 +cycloneive_lcell_comb \z80_|address_latch_|abusz[9] ( +// Equation(s): +// \z80_|address_latch_|abusz [9] = (\z80_|reg_file_|db_hi_as[1]~3_combout & !\z80_|resets_|clrpc~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|reg_file_|db_hi_as[1]~3_combout ), + .datad(\z80_|resets_|clrpc~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [9]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[9] .lut_mask = 16'h00F0; +defparam \z80_|address_latch_|abusz[9] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N22 +cycloneive_lcell_comb \z80_|address_latch_|Q[9]~feeder ( +// Equation(s): +// \z80_|address_latch_|Q[9]~feeder_combout = \z80_|address_latch_|abusz [9] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [9]), + .cin(gnd), + .combout(\z80_|address_latch_|Q[9]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|Q[9]~feeder .lut_mask = 16'hFF00; +defparam \z80_|address_latch_|Q[9]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y10_N23 +dffeas \z80_|address_latch_|Q[9] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|Q[9]~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [9]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[9] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N26 +cycloneive_lcell_comb \z80_|address_latch_|abusz[10] ( +// Equation(s): +// \z80_|address_latch_|abusz [10] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[2]~9_combout ) + + .dataa(\z80_|resets_|clrpc~0_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|db_hi_as[2]~9_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [10]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[10] .lut_mask = 16'h5500; +defparam \z80_|address_latch_|abusz[10] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y13_N27 +dffeas \z80_|address_latch_|Q[10] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [10]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [10]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[10] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N12 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout = \z80_|address_latch_|Q [10] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout & (\z80_|execute_|ctl_inc_dec~11_combout $ +// (\z80_|address_latch_|Q [9]))))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), + .datab(\z80_|execute_|ctl_inc_dec~11_combout ), + .datac(\z80_|address_latch_|Q [9]), + .datad(\z80_|address_latch_|Q [10]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out .lut_mask = 16'hD728; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y14_N13 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[2]~9_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N12 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~7 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[2]~7_combout = (\z80_|reg_file_|gdfx_temp1[2]~39_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # (!\z80_|reg_file_|gdfx_temp1[2]~39_combout & +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[2]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[2]~7 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|db_hi_as[2]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y14_N19 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[2]~9_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N8 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~8 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[2]~8_combout = (\z80_|reg_file_|db_hi_as[2]~7_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|db_hi_as[2]~7_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datac(gnd), + .datad(\z80_|reg_file_|b2v_latch_pc_hi|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[2]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[2]~8 .lut_mask = 16'hAA22; +defparam \z80_|reg_file_|db_hi_as[2]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N18 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~9 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[2]~9_combout = ((\z80_|reg_file_|db_hi_as[2]~8_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .datac(\z80_|reg_file_|db_hi_as[2]~8_combout ), + .datad(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[2]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[2]~9 .lut_mask = 16'hB0FF; +defparam \z80_|reg_file_|db_hi_as[2]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~39 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~39_combout = ((\z80_|reg_file_|gdfx_temp1[2]~38_combout & ((\z80_|reg_file_|db_hi_as[2]~9_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[2]~38_combout ), + .datac(\z80_|reg_file_|db_hi_as[2]~9_combout ), + .datad(\z80_|execute_|ctl_sw_4u~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~39 .lut_mask = 16'hD5DD; +defparam \z80_|reg_file_|gdfx_temp1[2]~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N24 +cycloneive_lcell_comb \z80_|alu_|db[2]~15 ( +// Equation(s): +// \z80_|alu_|db[2]~15_combout = (\z80_|execute_|ctl_sw_2d~13_combout & (\z80_|alu_control_|db[2]~29_combout & ((\z80_|reg_file_|gdfx_temp1[2]~39_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) # (!\z80_|execute_|ctl_sw_2d~13_combout & +// ((\z80_|reg_file_|gdfx_temp1[2]~39_combout ) # ((!\z80_|execute_|ctl_reg_out_hi~7_combout )))) + + .dataa(\z80_|execute_|ctl_sw_2d~13_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .datac(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .datad(\z80_|alu_control_|db[2]~29_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[2]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[2]~15 .lut_mask = 16'hCF45; +defparam \z80_|alu_|db[2]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N4 +cycloneive_lcell_comb \z80_|alu_|db[2]~16 ( +// Equation(s): +// \z80_|alu_|db[2]~16_combout = ((\z80_|alu_|db[2]~15_combout & ((\z80_|alu_|db_low[2]~23_combout ) # (!\z80_|execute_|ctl_alu_oe~11_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|execute_|ctl_alu_oe~11_combout ), + .datab(\z80_|alu_|db[2]~15_combout ), + .datac(\z80_|alu_|db[7]~9_combout ), + .datad(\z80_|alu_|db_low[2]~23_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[2]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[2]~16 .lut_mask = 16'hCF4F; +defparam \z80_|alu_|db[2]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N24 +cycloneive_lcell_comb \z80_|alu_control_|db[2]~27 ( +// Equation(s): +// \z80_|alu_control_|db[2]~27_combout = (\z80_|alu_|db[2]~16_combout & (!\z80_|alu_flags_|DFFE_inst_latch_pf~q & ((\z80_|execute_|ctl_flags_oe~2_combout )))) # (!\z80_|alu_|db[2]~16_combout & ((\z80_|execute_|ctl_sw_2u~7_combout ) # +// ((!\z80_|alu_flags_|DFFE_inst_latch_pf~q & \z80_|execute_|ctl_flags_oe~2_combout )))) + + .dataa(\z80_|alu_|db[2]~16_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), + .datac(\z80_|execute_|ctl_sw_2u~7_combout ), + .datad(\z80_|execute_|ctl_flags_oe~2_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[2]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[2]~27 .lut_mask = 16'h7350; +defparam \z80_|alu_control_|db[2]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N0 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~2 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf~2_combout = (\z80_|execute_|ctl_flags_alu~15_combout & !\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_flags_alu~15_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~2 .lut_mask = 16'h0C0C; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N26 +cycloneive_lcell_comb \z80_|alu_flags_|flags_hf2~0 ( +// Equation(s): +// \z80_|alu_flags_|flags_hf2~0_combout = (\z80_|execute_|ctl_flags_hf2_we~combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ) # ((\z80_|alu_control_|db[4]~32_combout )))) # (!\z80_|execute_|ctl_flags_hf2_we~combout & +// (((\z80_|alu_flags_|flags_hf2~q )))) + + .dataa(\z80_|execute_|ctl_flags_hf2_we~combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ), + .datac(\z80_|alu_flags_|flags_hf2~q ), + .datad(\z80_|alu_control_|db[4]~32_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|flags_hf2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|flags_hf2~0 .lut_mask = 16'hFAD8; +defparam \z80_|alu_flags_|flags_hf2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y18_N27 +dffeas \z80_|alu_flags_|flags_hf2 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|flags_hf2~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|flags_hf2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|flags_hf2 .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|flags_hf2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N30 +cycloneive_lcell_comb \z80_|alu_control_|db[2]~23 ( +// Equation(s): +// \z80_|alu_control_|db[2]~23_combout = ((\z80_|alu_flags_|flags_hf2~q ) # ((\z80_|alu_control_|out[6]~0_combout ) # (\z80_|execute_|ctl_66_oe~combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datab(\z80_|alu_flags_|flags_hf2~q ), + .datac(\z80_|alu_control_|out[6]~0_combout ), + .datad(\z80_|execute_|ctl_66_oe~combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[2]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[2]~23 .lut_mask = 16'hFFFD; +defparam \z80_|alu_control_|db[2]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N30 +cycloneive_lcell_comb \z80_|alu_control_|db[2]~29 ( +// Equation(s): +// \z80_|alu_control_|db[2]~29_combout = ((\z80_|alu_control_|db[2]~28_combout & (!\z80_|alu_control_|db[2]~27_combout & \z80_|alu_control_|db[2]~23_combout ))) # (!\z80_|alu_control_|db[6]~11_combout ) + + .dataa(\z80_|alu_control_|db[2]~28_combout ), + .datab(\z80_|alu_control_|db[2]~27_combout ), + .datac(\z80_|alu_control_|db[2]~23_combout ), + .datad(\z80_|alu_control_|db[6]~11_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[2]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[2]~29 .lut_mask = 16'h20FF; +defparam \z80_|alu_control_|db[2]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~39 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~39_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout & (\z80_|alu_control_|db[2]~29_combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) # +// (!\z80_|execute_|ctl_reg_in_lo~8_combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [2]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datab(\z80_|reg_file_|b2v_latch_sp_lo|latch [2]), + .datac(\z80_|alu_control_|db[2]~29_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~39 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[2]~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y11_N3 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X32_Y11_N21 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~35 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~35_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [2]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~35 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[2]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~40 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~40_combout = (\z80_|reg_file_|gdfx_temp0[2]~37_combout & (\z80_|reg_file_|gdfx_temp0[2]~38_combout & (\z80_|reg_file_|gdfx_temp0[2]~39_combout & \z80_|reg_file_|gdfx_temp0[2]~35_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[2]~37_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[2]~38_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[2]~39_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[2]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~40 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[2]~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~41 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~41_combout = (\z80_|reg_file_|gdfx_temp0[2]~33_combout & (\z80_|reg_file_|gdfx_temp0[2]~34_combout & \z80_|reg_file_|gdfx_temp0[2]~40_combout )) + + .dataa(\z80_|reg_file_|gdfx_temp0[2]~33_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[2]~34_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[2]~40_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~41 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|gdfx_temp0[2]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~42 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~42_combout = ((\z80_|reg_file_|gdfx_temp0[2]~41_combout & ((\z80_|reg_file_|db_lo_as[2]~9_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .datad(\z80_|reg_file_|db_lo_as[2]~9_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~42 .lut_mask = 16'hCF4F; +defparam \z80_|reg_file_|gdfx_temp0[2]~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y12_N15 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[2]~9_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N14 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~7 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[2]~7_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[2]~42_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # +// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[2]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[2]~7 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_lo_as[2]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N6 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~8 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[2]~8_combout = (\z80_|reg_file_|db_lo_as[2]~7_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_ir_lo|latch [2]), + .datab(gnd), + .datac(\z80_|reg_file_|db_lo_as[2]~7_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[2]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[2]~8 .lut_mask = 16'hA0F0; +defparam \z80_|reg_file_|db_lo_as[2]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N4 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout = \z80_|address_latch_|Q [0] $ (((\z80_|execute_|ctl_inc_dec~9_combout ) # ((\z80_|execute_|ctl_inc_dec~7_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout )))) + + .dataa(\z80_|execute_|ctl_inc_dec~9_combout ), + .datab(\z80_|address_latch_|Q [0]), + .datac(\z80_|execute_|ctl_inc_dec~6_combout ), + .datad(\z80_|execute_|ctl_inc_dec~7_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 .lut_mask = 16'h3363; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N26 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout & ((\z80_|execute_|ctl_inc_cy~71_combout ) # ((\z80_|execute_|ctl_inc_cy~81_combout ) # +// (\z80_|execute_|ctl_inc_cy~68_combout )))) + + .dataa(\z80_|execute_|ctl_inc_cy~71_combout ), + .datab(\z80_|execute_|ctl_inc_cy~81_combout ), + .datac(\z80_|execute_|ctl_inc_cy~68_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'hFE00; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N0 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout = \z80_|address_latch_|Q [2] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout & +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout ))) + + .dataa(\z80_|address_latch_|Q [2]), + .datab(gnd), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out .lut_mask = 16'h5AAA; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N8 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~9 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[2]~9_combout = ((\z80_|reg_file_|db_lo_as[2]~8_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|reg_file_|db_lo_as[2]~8_combout ), + .datab(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[2]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[2]~9 .lut_mask = 16'hBB3B; +defparam \z80_|reg_file_|db_lo_as[2]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N8 +cycloneive_lcell_comb \z80_|address_latch_|abusz[2] ( +// Equation(s): +// \z80_|address_latch_|abusz [2] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[2]~9_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(\z80_|reg_file_|db_lo_as[2]~9_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [2]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[2] .lut_mask = 16'h0F00; +defparam \z80_|address_latch_|abusz[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y11_N9 +dffeas \z80_|address_latch_|Q[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [2]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[2] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N18 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout = \z80_|address_latch_|Q [2] $ ((((\z80_|execute_|ctl_inc_dec~10_combout ) # (!\z80_|execute_|ctl_inc_dec~5_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~42_combout ))) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~42_combout ), + .datab(\z80_|address_latch_|Q [2]), + .datac(\z80_|execute_|ctl_inc_dec~10_combout ), + .datad(\z80_|execute_|ctl_inc_dec~5_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42 .lut_mask = 16'h3933; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y12_N25 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[3]~12_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N24 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~10 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[3]~10_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[3]~52_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # +// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[3]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[3]~10 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_lo_as[3]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y12_N31 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[3]~12_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N28 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~11 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[3]~11_combout = (\z80_|reg_file_|db_lo_as[3]~10_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .datab(\z80_|reg_file_|db_lo_as[3]~10_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [3]), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[3]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[3]~11 .lut_mask = 16'hCC44; +defparam \z80_|reg_file_|db_lo_as[3]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N26 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout = \z80_|address_latch_|Q [3] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout & +// (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout )))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout ), + .datab(\z80_|address_latch_|Q [3]), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out .lut_mask = 16'h6CCC; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N30 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~12 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[3]~12_combout = ((\z80_|reg_file_|db_lo_as[3]~11_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .datab(\z80_|reg_file_|db_lo_as[3]~11_combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), + .datad(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[3]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[3]~12 .lut_mask = 16'hC4FF; +defparam \z80_|reg_file_|db_lo_as[3]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N14 +cycloneive_lcell_comb \z80_|address_latch_|abusz[3] ( +// Equation(s): +// \z80_|address_latch_|abusz [3] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[3]~12_combout ) + + .dataa(gnd), + .datab(\z80_|resets_|clrpc~0_combout ), + .datac(\z80_|reg_file_|db_lo_as[3]~12_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [3]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[3] .lut_mask = 16'h3030; +defparam \z80_|address_latch_|abusz[3] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y11_N15 +dffeas \z80_|address_latch_|Q[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [3]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[3] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N24 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout = \z80_|address_latch_|Q [3] $ ((((\z80_|execute_|ctl_inc_dec~10_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~42_combout )) # (!\z80_|execute_|ctl_inc_dec~5_combout ))) + + .dataa(\z80_|execute_|ctl_inc_dec~5_combout ), + .datab(\z80_|address_latch_|Q [3]), + .datac(\z80_|execute_|ctl_inc_dec~10_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~42_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4 .lut_mask = 16'h3933; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N10 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout & +// (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout ))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 .lut_mask = 16'h8000; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N16 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout = (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|address_latch_|Q [6] $ (((\z80_|execute_|ctl_inc_dec~7_combout ) # (\z80_|execute_|ctl_inc_dec~10_combout ))))) + + .dataa(\z80_|address_latch_|Q [6]), + .datab(\z80_|execute_|ctl_inc_dec~7_combout ), + .datac(\z80_|execute_|ctl_inc_dec~10_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 .lut_mask = 16'h0056; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N14 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout & +// (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 .lut_mask = 16'h8000; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N22 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout & ((\z80_|address_latch_|Q [8] & (!\z80_|execute_|ctl_inc_dec~11_combout & \z80_|address_latch_|Q +// [7])) # (!\z80_|address_latch_|Q [8] & (\z80_|execute_|ctl_inc_dec~11_combout & !\z80_|address_latch_|Q [7])))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), + .datab(\z80_|address_latch_|Q [8]), + .datac(\z80_|execute_|ctl_inc_dec~11_combout ), + .datad(\z80_|address_latch_|Q [7]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 .lut_mask = 16'h0820; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N28 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout & ((\z80_|execute_|ctl_inc_dec~11_combout & (!\z80_|address_latch_|Q [9] & +// !\z80_|address_latch_|Q [10])) # (!\z80_|execute_|ctl_inc_dec~11_combout & (\z80_|address_latch_|Q [9] & \z80_|address_latch_|Q [10])))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), + .datab(\z80_|execute_|ctl_inc_dec~11_combout ), + .datac(\z80_|address_latch_|Q [9]), + .datad(\z80_|address_latch_|Q [10]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 .lut_mask = 16'h2008; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N26 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[11] ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|address [11] = \z80_|address_latch_|Q [11] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|address_latch_|Q [11]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[11] .lut_mask = 16'h0FF0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[11] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N4 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~12 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[3]~12_combout = ((\z80_|reg_file_|db_hi_as[3]~11_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [11]) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .datac(\z80_|reg_file_|db_hi_as[3]~11_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[3]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[3]~12 .lut_mask = 16'hF575; +defparam \z80_|reg_file_|db_hi_as[3]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y14_N17 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X37_Y14_N31 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~41 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~41_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (\z80_|reg_file_|b2v_latch_hl_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_hl2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (((\z80_|reg_file_|b2v_latch_hl2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [3]), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~41 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[3]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y15_N5 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X35_Y15_N7 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~45 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~45_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (\z80_|reg_file_|b2v_latch_wz_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (((\z80_|reg_file_|b2v_latch_sp_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [3]), + .datad(\z80_|reg_file_|b2v_latch_sp_hi|latch [3]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~45 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[3]~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y16_N23 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~44 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~44_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout & (\z80_|alu_|db[3]~20_combout & ((\z80_|reg_file_|b2v_latch_af2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # +// (!\z80_|execute_|ctl_reg_in_hi~12_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .datab(\z80_|alu_|db[3]~20_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~44 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[3]~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y16_N19 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y16_N9 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~43 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~43_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [3]), + .datad(\z80_|reg_file_|b2v_latch_iy_hi|latch [3]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~43 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[3]~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y16_N9 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X37_Y16_N7 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~42 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~42_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (\z80_|reg_file_|b2v_latch_bc2_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [3]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_bc_hi|latch [3]), + .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~42 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp1[3]~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~46 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~46_combout = (\z80_|reg_file_|gdfx_temp1[3]~45_combout & (\z80_|reg_file_|gdfx_temp1[3]~44_combout & (\z80_|reg_file_|gdfx_temp1[3]~43_combout & \z80_|reg_file_|gdfx_temp1[3]~42_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[3]~45_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[3]~44_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[3]~43_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[3]~42_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~46 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[3]~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N8 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_hi|latch[3]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_de_hi|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp1[3]~48_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_de_hi|latch[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[3]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y15_N9 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_de_hi|latch[3]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X37_Y15_N27 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~40 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~40_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datab(\z80_|reg_file_|b2v_latch_de_hi|latch [3]), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~40 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[3]~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y15_N21 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N10 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[3]~13 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[3]~13_combout = (\z80_|execute_|ctl_reg_gp_we~8_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [3]) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout )) # (!\z80_|reg_control_|reg_sel_af~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(\z80_|reg_control_|reg_sel_af~0_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datad(\z80_|reg_file_|b2v_latch_af_hi|latch [3]), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[3]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[3]~13 .lut_mask = 16'hFFBF; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[3]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~47 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~47_combout = (\z80_|reg_file_|gdfx_temp1[3]~41_combout & (\z80_|reg_file_|gdfx_temp1[3]~46_combout & (\z80_|reg_file_|gdfx_temp1[3]~40_combout & \z80_|reg_file_|b2v_latch_af_hi|db[3]~13_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[3]~41_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[3]~46_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[3]~40_combout ), + .datad(\z80_|reg_file_|b2v_latch_af_hi|db[3]~13_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~47 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[3]~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~48 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~48_combout = ((\z80_|reg_file_|gdfx_temp1[3]~47_combout & ((\z80_|reg_file_|db_hi_as[3]~12_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[3]~12_combout ), + .datab(\z80_|execute_|ctl_sw_4u~6_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[3]~47_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~48 .lut_mask = 16'hBF0F; +defparam \z80_|reg_file_|gdfx_temp1[3]~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N6 +cycloneive_lcell_comb \z80_|alu_|db[3]~19 ( +// Equation(s): +// \z80_|alu_|db[3]~19_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[3]~48_combout & ((\z80_|alu_|db_low[3]~25_combout ) # (!\z80_|execute_|ctl_alu_oe~11_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & +// ((\z80_|alu_|db_low[3]~25_combout ) # ((!\z80_|execute_|ctl_alu_oe~11_combout )))) + + .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .datab(\z80_|alu_|db_low[3]~25_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .datad(\z80_|execute_|ctl_alu_oe~11_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[3]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[3]~19 .lut_mask = 16'hC4F5; +defparam \z80_|alu_|db[3]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N28 +cycloneive_lcell_comb \z80_|alu_|db[3]~20 ( +// Equation(s): +// \z80_|alu_|db[3]~20_combout = ((\z80_|alu_|db[3]~19_combout & ((\z80_|alu_control_|db[3]~35_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|alu_control_|db[3]~35_combout ), + .datab(\z80_|alu_|db[7]~9_combout ), + .datac(\z80_|execute_|ctl_sw_2d~13_combout ), + .datad(\z80_|alu_|db[3]~19_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[3]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[3]~20 .lut_mask = 16'hBF33; +defparam \z80_|alu_|db[3]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N18 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~21 ( +// Equation(s): +// \z80_|alu_|db_low[2]~21_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[3]~20_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[1]~10_combout ))) + + .dataa(\z80_|alu_|db[3]~20_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(gnd), + .datad(\z80_|alu_|db[1]~10_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[2]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[2]~21 .lut_mask = 16'hBB88; +defparam \z80_|alu_|db_low[2]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N12 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~22 ( +// Equation(s): +// \z80_|alu_|db_low[2]~22_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_low[2]~21_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[2]~16_combout ))) + + .dataa(gnd), + .datab(\z80_|alu_|db_low[2]~21_combout ), + .datac(\z80_|alu_|db[2]~16_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[2]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[2]~22 .lut_mask = 16'hCCF0; +defparam \z80_|alu_|db_low[2]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y17_N1 +dffeas \z80_|alu_|result_lo[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_alu_op_low~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|result_lo [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|result_lo[2] .is_wysiwyg = "true"; +defparam \z80_|alu_|result_lo[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N10 +cycloneive_lcell_comb \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 ( +// Equation(s): +// \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout = (\z80_|bus_control_|db[4]~19_combout & !\z80_|bus_control_|db[3]~21_combout ) + + .dataa(gnd), + .datab(\z80_|bus_control_|db[4]~19_combout ), + .datac(\z80_|bus_control_|db[3]~21_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 .lut_mask = 16'h0C0C; +defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N22 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~6 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~6_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [2])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [2]))))) + + .dataa(\z80_|alu_|op1_low [2]), + .datab(\z80_|execute_|ctl_alu_op_low~combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datad(\z80_|alu_|op1_high [2]), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~6 .lut_mask = 16'hB080; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N30 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~7 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~7_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~6_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~8_combout & \z80_|alu_|db_low[2]~23_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datac(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~6_combout ), + .datad(\z80_|alu_|db_low[2]~23_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~7 .lut_mask = 16'h3230; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y18_N31 +dffeas \z80_|alu_|op2_low[2] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~7_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_low [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_low[2] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_low[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N6 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~18 ( +// Equation(s): +// \z80_|alu_|db_low[2]~18_combout = (\z80_|execute_|ctl_alu_op2_oe~0_combout & (\z80_|alu_|op2_low [2] & ((\z80_|alu_|op1_low [2]) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_low [2]) # +// ((!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datab(\z80_|alu_|op1_low [2]), + .datac(\z80_|alu_|op2_low [2]), + .datad(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[2]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[2]~18 .lut_mask = 16'hC4F5; +defparam \z80_|alu_|db_low[2]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N22 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~19 ( +// Equation(s): +// \z80_|alu_|db_low[2]~19_combout = (\z80_|alu_|db_low[2]~18_combout & (((\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout & !\z80_|bus_control_|db[5]~15_combout )) # (!\z80_|execute_|ctl_alu_bs_oe~combout ))) + + .dataa(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), + .datab(\z80_|bus_control_|db[5]~15_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datad(\z80_|alu_|db_low[2]~18_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[2]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[2]~19 .lut_mask = 16'h2F00; +defparam \z80_|alu_|db_low[2]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N0 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~20 ( +// Equation(s): +// \z80_|alu_|db_low[2]~20_combout = (\z80_|alu_|db_low[2]~19_combout & ((\z80_|execute_|ctl_alu_res_oe~3_combout ) # (\z80_|alu_|result_lo [2]))) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_res_oe~3_combout ), + .datac(\z80_|alu_|result_lo [2]), + .datad(\z80_|alu_|db_low[2]~19_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[2]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[2]~20 .lut_mask = 16'hFC00; +defparam \z80_|alu_|db_low[2]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N2 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~23 ( +// Equation(s): +// \z80_|alu_|db_low[2]~23_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout & (\z80_|alu_|db_low[2]~22_combout & ((\z80_|alu_|db_low[2]~20_combout )))) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout & (((\z80_|alu_|db_low[2]~20_combout ) # +// (!\z80_|alu_|db_high[3]~0_combout )))) + + .dataa(\z80_|alu_|db_low[2]~22_combout ), + .datab(\z80_|alu_|db_high[3]~0_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datad(\z80_|alu_|db_low[2]~20_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[2]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[2]~23 .lut_mask = 16'hAF03; +defparam \z80_|alu_|db_low[2]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N2 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~7 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~7_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & ((\z80_|alu_|db_low[2]~23_combout ) # ((\z80_|alu_|db_high[2]~13_combout & \z80_|execute_|ctl_alu_op1_sel_low~combout )))) # +// (!\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & (((\z80_|alu_|db_high[2]~13_combout & \z80_|execute_|ctl_alu_op1_sel_low~combout )))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datab(\z80_|alu_|db_low[2]~23_combout ), + .datac(\z80_|alu_|db_high[2]~13_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~7 .lut_mask = 16'hF888; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N10 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~8 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~8_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~7_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .datad(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~7_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~8 .lut_mask = 16'h0F00; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y17_N11 +dffeas \z80_|alu_|op1_low[2] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~8_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_low [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_low[2] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_low[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N26 +cycloneive_lcell_comb \z80_|alu_|alu_op1[2]~1 ( +// Equation(s): +// \z80_|alu_|alu_op1[2]~1_combout = (\z80_|execute_|ctl_alu_op_low~41_combout & (\z80_|alu_|op1_low [2])) # (!\z80_|execute_|ctl_alu_op_low~41_combout & ((\z80_|execute_|ctl_alu_op_low~29_combout & ((\z80_|alu_|op1_high [2]))) # +// (!\z80_|execute_|ctl_alu_op_low~29_combout & (\z80_|alu_|op1_low [2])))) + + .dataa(\z80_|alu_|op1_low [2]), + .datab(\z80_|execute_|ctl_alu_op_low~41_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~29_combout ), + .datad(\z80_|alu_|op1_high [2]), + .cin(gnd), + .combout(\z80_|alu_|alu_op1[2]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op1[2]~1 .lut_mask = 16'hBA8A; +defparam \z80_|alu_|alu_op1[2]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N30 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout = (\z80_|execute_|ctl_alu_core_S~combout ) # ((\z80_|alu_|alu_op1[2]~1_combout & \z80_|alu_|alu_op2[2]~0_combout )) + + .dataa(\z80_|alu_|alu_op1[2]~1_combout ), + .datab(gnd), + .datac(\z80_|alu_|alu_op2[2]~0_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hFFA0; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N8 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout = (!\z80_|alu_|alu_op2[2]~0_combout & ((\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_low [2])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_high +// [2]))))) + + .dataa(\z80_|alu_|alu_op2[2]~0_combout ), + .datab(\z80_|alu_|op1_low [2]), + .datac(\z80_|alu_|op1_high [2]), + .datad(\z80_|execute_|ctl_alu_op_low~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h1105; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N20 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout = (!\z80_|execute_|ctl_alu_core_R~combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ) # +// ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout & !\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout )))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), + .datab(\z80_|execute_|ctl_alu_core_R~combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 .lut_mask = 16'h3031; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N16 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ) # +// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), + .datab(\z80_|execute_|ctl_alu_core_R~combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 .lut_mask = 16'hDCDD; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N20 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout = (!\z80_|alu_|alu_op2[3]~2_combout & ((\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_low [3])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_high +// [3]))))) + + .dataa(\z80_|alu_|op1_low [3]), + .datab(\z80_|alu_|alu_op2[3]~2_combout ), + .datac(\z80_|alu_|op1_high [3]), + .datad(\z80_|execute_|ctl_alu_op_low~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h1103; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N10 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ) # +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout )))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .datac(\z80_|execute_|ctl_alu_core_R~combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0 .lut_mask = 16'hF5F4; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N6 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_hf~0 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_hf~0_combout = (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & (\z80_|execute_|ctl_flags_bus~combout & ((\z80_|alu_control_|db[4]~32_combout )))) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout +// & ((\z80_|execute_|ctl_flags_alu~15_combout ) # ((\z80_|execute_|ctl_flags_bus~combout & \z80_|alu_control_|db[4]~32_combout )))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), + .datab(\z80_|execute_|ctl_flags_bus~combout ), + .datac(\z80_|execute_|ctl_flags_alu~15_combout ), + .datad(\z80_|alu_control_|db[4]~32_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_hf~0 .lut_mask = 16'hDC50; +defparam \z80_|alu_flags_|DFFE_inst_latch_hf~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_we~3_combout = (\z80_|pla_decode_|Equal11~0_combout & (((\z80_|nM1_int~2_combout ) # (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) # (!\z80_|pla_decode_|Equal11~0_combout & (\z80_|pla_decode_|Equal10~0_combout & +// ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_we~3 .lut_mask = 16'hEEC0; +defparam \z80_|execute_|ctl_flags_hf_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_we~4_combout = ((\z80_|execute_|ctl_flags_sz_we~6_combout ) # ((\z80_|execute_|ctl_flags_hf_we~3_combout ) # (!\z80_|execute_|ctl_flags_alu~14_combout ))) # (!\z80_|execute_|ctl_flags_xy_we~8_combout ) + + .dataa(\z80_|execute_|ctl_flags_xy_we~8_combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~6_combout ), + .datac(\z80_|execute_|ctl_flags_alu~14_combout ), + .datad(\z80_|execute_|ctl_flags_hf_we~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_we~4 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|ctl_flags_hf_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N28 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_hf~1 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_hf~1_combout = (\z80_|execute_|ctl_flags_hf_we~2_combout & ((\z80_|execute_|ctl_flags_hf_we~4_combout & (\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout )) # (!\z80_|execute_|ctl_flags_hf_we~4_combout & +// ((\z80_|alu_flags_|DFFE_inst_latch_hf~q ))))) # (!\z80_|execute_|ctl_flags_hf_we~2_combout & (\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout )) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ), + .datab(\z80_|execute_|ctl_flags_hf_we~2_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), + .datad(\z80_|execute_|ctl_flags_hf_we~4_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_hf~1 .lut_mask = 16'hAAE2; +defparam \z80_|alu_flags_|DFFE_inst_latch_hf~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y18_N29 +dffeas \z80_|alu_flags_|DFFE_inst_latch_hf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_hf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_hf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N16 +cycloneive_lcell_comb \z80_|alu_flags_|flags_hf ( +// Equation(s): +// \z80_|alu_flags_|flags_hf~combout = \z80_|alu_flags_|DFFE_inst_latch_hf~q $ (((\z80_|execute_|ctl_flags_hf_cpl~13_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout & !\z80_|alu_flags_|flags_cf~combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .datab(\z80_|execute_|ctl_flags_hf_cpl~13_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), + .datad(\z80_|alu_flags_|flags_cf~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|flags_hf~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|flags_hf .lut_mask = 16'h3C1E; +defparam \z80_|alu_flags_|flags_hf .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N16 +cycloneive_lcell_comb \z80_|alu_control_|db[4]~30 ( +// Equation(s): +// \z80_|alu_control_|db[4]~30_combout = (\z80_|alu_|db[4]~18_combout & (!\z80_|reg_file_|gdfx_temp0[4]~62_combout & ((\z80_|execute_|ctl_reg_out_lo~8_combout )))) # (!\z80_|alu_|db[4]~18_combout & ((\z80_|execute_|ctl_sw_2u~7_combout ) # +// ((!\z80_|reg_file_|gdfx_temp0[4]~62_combout & \z80_|execute_|ctl_reg_out_lo~8_combout )))) + + .dataa(\z80_|alu_|db[4]~18_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .datac(\z80_|execute_|ctl_sw_2u~7_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[4]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[4]~30 .lut_mask = 16'h7350; +defparam \z80_|alu_control_|db[4]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N10 +cycloneive_lcell_comb \z80_|alu_control_|db[4]~31 ( +// Equation(s): +// \z80_|alu_control_|db[4]~31_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & (!\z80_|alu_control_|db[4]~30_combout & ((\z80_|alu_flags_|flags_hf~combout ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) + + .dataa(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .datab(\z80_|alu_flags_|flags_hf~combout ), + .datac(\z80_|execute_|ctl_flags_oe~2_combout ), + .datad(\z80_|alu_control_|db[4]~30_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[4]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[4]~31 .lut_mask = 16'h008A; +defparam \z80_|alu_control_|db[4]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N2 +cycloneive_lcell_comb \z80_|alu_control_|db[4]~32 ( +// Equation(s): +// \z80_|alu_control_|db[4]~32_combout = ((\z80_|alu_control_|db[4]~31_combout & ((\z80_|bus_control_|db[4]~19_combout ) # (!\z80_|execute_|ctl_sw_1d~7_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) + + .dataa(\z80_|bus_control_|db[4]~19_combout ), + .datab(\z80_|alu_control_|db[4]~31_combout ), + .datac(\z80_|execute_|ctl_sw_1d~7_combout ), + .datad(\z80_|alu_control_|db[6]~11_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[4]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[4]~32 .lut_mask = 16'h8CFF; +defparam \z80_|alu_control_|db[4]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N26 +cycloneive_lcell_comb \z80_|alu_|db[4]~17 ( +// Equation(s): +// \z80_|alu_|db[4]~17_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[4]~66_combout & ((\z80_|alu_control_|db[4]~32_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & +// ((\z80_|alu_control_|db[4]~32_combout ) # ((!\z80_|execute_|ctl_sw_2d~13_combout )))) + + .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .datab(\z80_|alu_control_|db[4]~32_combout ), + .datac(\z80_|execute_|ctl_sw_2d~13_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[4]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[4]~17 .lut_mask = 16'hCF45; +defparam \z80_|alu_|db[4]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N16 +cycloneive_lcell_comb \z80_|alu_|db[4]~18 ( +// Equation(s): +// \z80_|alu_|db[4]~18_combout = ((\z80_|alu_|db[4]~17_combout & ((\z80_|alu_|db_high[0]~25_combout ) # (!\z80_|execute_|ctl_alu_oe~11_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|execute_|ctl_alu_oe~11_combout ), + .datab(\z80_|alu_|db[7]~9_combout ), + .datac(\z80_|alu_|db[4]~17_combout ), + .datad(\z80_|alu_|db_high[0]~25_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[4]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[4]~18 .lut_mask = 16'hF373; +defparam \z80_|alu_|db[4]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N16 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~13 ( +// Equation(s): +// \z80_|alu_|db_low[3]~13_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[4]~18_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[2]~16_combout ))) + + .dataa(\z80_|alu_|db[4]~18_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(gnd), + .datad(\z80_|alu_|db[2]~16_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~13 .lut_mask = 16'hBB88; +defparam \z80_|alu_|db_low[3]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N10 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~14 ( +// Equation(s): +// \z80_|alu_|db_low[3]~14_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_low[3]~13_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[3]~20_combout )))) # +// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) + + .dataa(\z80_|alu_|db_low[3]~13_combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datad(\z80_|alu_|db[3]~20_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~14 .lut_mask = 16'hBF8F; +defparam \z80_|alu_|db_low[3]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N24 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~17 ( +// Equation(s): +// \z80_|alu_|db_low[3]~17_combout = (\z80_|alu_|db_low[3]~16_combout & (\z80_|alu_|db_low[3]~14_combout & ((\z80_|execute_|ctl_alu_res_oe~3_combout ) # (\z80_|alu_|result_lo [3])))) + + .dataa(\z80_|execute_|ctl_alu_res_oe~3_combout ), + .datab(\z80_|alu_|db_low[3]~16_combout ), + .datac(\z80_|alu_|result_lo [3]), + .datad(\z80_|alu_|db_low[3]~14_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~17 .lut_mask = 16'hC800; +defparam \z80_|alu_|db_low[3]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N14 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~25 ( +// Equation(s): +// \z80_|alu_|db_low[3]~25_combout = (\z80_|alu_|db_low[3]~17_combout ) # ((!\z80_|alu_|db_high[3]~0_combout & !\z80_|execute_|ctl_alu_shift_oe~43_combout )) + + .dataa(gnd), + .datab(\z80_|alu_|db_high[3]~0_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datad(\z80_|alu_|db_low[3]~17_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~25 .lut_mask = 16'hFF03; +defparam \z80_|alu_|db_low[3]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N24 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~4 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~4_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [3]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [3])))) + + .dataa(\z80_|alu_|op1_high [3]), + .datab(\z80_|execute_|ctl_alu_op_low~combout ), + .datac(\z80_|alu_|op1_low [3]), + .datad(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~4 .lut_mask = 16'hE200; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N28 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~5 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~5_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~4_combout ) # ((\z80_|alu_|db_low[3]~25_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) + + .dataa(\z80_|alu_|db_low[3]~25_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .datad(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~4_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~5 .lut_mask = 16'h3320; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y18_N29 +dffeas \z80_|alu_|op2_low[3] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~5_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_low [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_low[3] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_low[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N12 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~8_combout & ((\z80_|alu_|db_high[3]~7_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_lq~combout & \z80_|alu_|db_low[3]~25_combout )))) # +// (!\z80_|execute_|ctl_alu_op2_sel_bus~8_combout & (\z80_|execute_|ctl_alu_op2_sel_lq~combout & (\z80_|alu_|db_low[3]~25_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datac(\z80_|alu_|db_low[3]~25_combout ), + .datad(\z80_|alu_|db_high[3]~7_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0 .lut_mask = 16'hEAC0; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N20 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datac(gnd), + .datad(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1 .lut_mask = 16'h3300; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y18_N21 +dffeas \z80_|alu_|op2_high[3] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_high [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_high[3] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_high[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N2 +cycloneive_lcell_comb \z80_|alu_|alu_op2[3]~2 ( +// Equation(s): +// \z80_|alu_|alu_op2[3]~2_combout = \z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [3]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [3])))) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .datab(\z80_|alu_|op2_low [3]), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), + .datad(\z80_|alu_|op2_high [3]), + .cin(gnd), + .combout(\z80_|alu_|alu_op2[3]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op2[3]~2 .lut_mask = 16'h1EB4; +defparam \z80_|alu_|alu_op2[3]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N22 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ) # +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout )))) # (!\z80_|execute_|ctl_alu_core_R~5_combout ) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), + .datac(\z80_|execute_|ctl_alu_core_R~5_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1 .lut_mask = 16'h5F4F; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N20 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout = (\z80_|alu_|alu_op2[3]~2_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout ) # ((\z80_|alu_|alu_op1[3]~2_combout & +// !\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout )))) # (!\z80_|alu_|alu_op2[3]~2_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_|alu_op1[3]~2_combout ) # +// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout )))) + + .dataa(\z80_|alu_|alu_op2[3]~2_combout ), + .datab(\z80_|alu_|alu_op1[3]~2_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 .lut_mask = 16'hEF08; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N14 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~3 ( +// Equation(s): +// \z80_|alu_|db_high[3]~3_combout = (\z80_|execute_|ctl_alu_op2_oe~0_combout & (\z80_|alu_|op2_high [3] & ((\z80_|alu_|op1_high [3]) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout & (((\z80_|alu_|op1_high +// [3]) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datab(\z80_|alu_|op2_high [3]), + .datac(\z80_|alu_|op1_high [3]), + .datad(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~3 .lut_mask = 16'hD0DD; +defparam \z80_|alu_|db_high[3]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N18 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~4 ( +// Equation(s): +// \z80_|alu_|db_high[3]~4_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[6]~22_combout )) + + .dataa(\z80_|alu_|db[6]~22_combout ), + .datab(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), + .datac(gnd), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~4 .lut_mask = 16'hCCAA; +defparam \z80_|alu_|db_high[3]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N28 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~5 ( +// Equation(s): +// \z80_|alu_|db_high[3]~5_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_high[3]~4_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[7]~12_combout )) + + .dataa(\z80_|alu_|db[7]~12_combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .datac(gnd), + .datad(\z80_|alu_|db_high[3]~4_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~5 .lut_mask = 16'hEE22; +defparam \z80_|alu_|db_high[3]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N28 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~2 ( +// Equation(s): +// \z80_|alu_|db_high[3]~2_combout = ((\z80_|bus_control_|db[3]~21_combout & (\z80_|bus_control_|db[5]~15_combout & \z80_|bus_control_|db[4]~19_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) + + .dataa(\z80_|bus_control_|db[3]~21_combout ), + .datab(\z80_|bus_control_|db[5]~15_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datad(\z80_|bus_control_|db[4]~19_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~2 .lut_mask = 16'h8F0F; +defparam \z80_|alu_|db_high[3]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N0 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~6 ( +// Equation(s): +// \z80_|alu_|db_high[3]~6_combout = (\z80_|alu_|db_high[3]~3_combout & (\z80_|alu_|db_high[3]~2_combout & ((\z80_|alu_|db_high[3]~5_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) + + .dataa(\z80_|alu_|db_high[3]~3_combout ), + .datab(\z80_|alu_|db_high[3]~5_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datad(\z80_|alu_|db_high[3]~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~6 .lut_mask = 16'h8A00; +defparam \z80_|alu_|db_high[3]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N22 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~7 ( +// Equation(s): +// \z80_|alu_|db_high[3]~7_combout = ((\z80_|alu_|db_high[3]~6_combout & ((\z80_|execute_|ctl_alu_res_oe~3_combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout )))) # (!\z80_|alu_|db_high[3]~1_combout ) + + .dataa(\z80_|execute_|ctl_alu_res_oe~3_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), + .datac(\z80_|alu_|db_high[3]~1_combout ), + .datad(\z80_|alu_|db_high[3]~6_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~7 .lut_mask = 16'hEF0F; +defparam \z80_|alu_|db_high[3]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N24 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_34 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout = (\z80_|execute_|ctl_flags_bus~combout & ((\z80_|alu_control_|db[7]~19_combout ) # ((\z80_|alu_|db_high[3]~7_combout & \z80_|execute_|ctl_flags_alu~15_combout )))) # (!\z80_|execute_|ctl_flags_bus~combout +// & (((\z80_|alu_|db_high[3]~7_combout & \z80_|execute_|ctl_flags_alu~15_combout )))) + + .dataa(\z80_|execute_|ctl_flags_bus~combout ), + .datab(\z80_|alu_control_|db[7]~19_combout ), + .datac(\z80_|alu_|db_high[3]~7_combout ), + .datad(\z80_|execute_|ctl_flags_alu~15_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_34 .lut_mask = 16'hF888; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y16_N25 +dffeas \z80_|alu_flags_|DFFE_inst_latch_sf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_flags_sz_we~8_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_sf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_sf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~5_combout = ((\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # (\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout )))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~5 .lut_mask = 16'hEF0F; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~7_combout = (\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ) # ((\z80_|pla_decode_|Equal61~2_combout & ((\z80_|nM1_int~2_combout ) # (\z80_|execute_|ctl_eval_cond~0_combout )))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), + .datac(\z80_|pla_decode_|Equal61~2_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~7 .lut_mask = 16'hFCEC; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout = (\z80_|pla_decode_|Equal13~0_combout & (\z80_|execute_|ctl_alu_op_low~22_combout & (\z80_|pla_decode_|Equal55~0_combout & !\z80_|ir_|opcode [3]))) + + .dataa(\z80_|pla_decode_|Equal13~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~6_combout = (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # ((\z80_|execute_|ixy_d~7_combout ) # (\z80_|nM1_int~2_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~6 .lut_mask = 16'hF0E0; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~8_combout = ((\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ) # (\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ))) # (!\z80_|execute_|ctl_alu_op_low~48_combout +// ) + + .dataa(\z80_|execute_|ctl_alu_op_low~48_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~8 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~11_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ) # (((\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~10_combout )) # (!\z80_|execute_|ctl_alu_sel_op2_neg~9_combout )) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~11 .lut_mask = 16'hFFBF; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~12_combout = (((\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ) # (\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout )) # (!\z80_|execute_|ctl_alu_sel_op2_neg~2_combout )) # (!\z80_|execute_|ctl_reg_out_hi~4_combout +// ) + + .dataa(\z80_|execute_|ctl_reg_out_hi~4_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~12 .lut_mask = 16'hFFF7; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~15 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~15_combout = ((\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_sf~q & \z80_|execute_|ctl_alu_sel_op2_neg~12_combout ))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~15 .lut_mask = 16'hFDF5; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N26 +cycloneive_lcell_comb \z80_|alu_|alu_op2[2]~0 ( +// Equation(s): +// \z80_|alu_|alu_op2[2]~0_combout = \z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [2]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [2])))) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), + .datac(\z80_|alu_|op2_low [2]), + .datad(\z80_|alu_|op2_high [2]), + .cin(gnd), + .combout(\z80_|alu_|alu_op2[2]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op2[2]~0 .lut_mask = 16'h369C; +defparam \z80_|alu_|alu_op2[2]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N18 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ) # +// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) # (!\z80_|execute_|ctl_alu_core_R~5_combout ) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), + .datac(\z80_|execute_|ctl_alu_core_R~5_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 .lut_mask = 16'h4F5F; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N24 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout = (\z80_|alu_|alu_op2[2]~0_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ) # ((\z80_|alu_|alu_op1[2]~1_combout & +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) # (!\z80_|alu_|alu_op2[2]~0_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_|alu_op1[2]~1_combout ) # +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) + + .dataa(\z80_|alu_|alu_op2[2]~0_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ), + .datac(\z80_|alu_|alu_op1[2]~1_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 .lut_mask = 16'hECC8; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y17_N11 +dffeas \z80_|alu_control_|DFFE_latch_pf_tmp ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|alu_parity_out~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_alu_op_low~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_control_|DFFE_latch_pf_tmp~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_control_|DFFE_latch_pf_tmp .is_wysiwyg = "true"; +defparam \z80_|alu_control_|DFFE_latch_pf_tmp .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N8 +cycloneive_lcell_comb \z80_|alu_|alu_parity_out~0 ( +// Equation(s): +// \z80_|alu_|alu_parity_out~0_combout = \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout $ (((\z80_|execute_|ctl_alu_op_low~29_combout & (!\z80_|alu_control_|DFFE_latch_pf_tmp~q & !\z80_|execute_|ctl_alu_op_low~41_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~29_combout ), + .datab(\z80_|alu_control_|DFFE_latch_pf_tmp~q ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~41_combout ), + .cin(gnd), + .combout(\z80_|alu_|alu_parity_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_parity_out~0 .lut_mask = 16'hF0D2; +defparam \z80_|alu_|alu_parity_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N10 +cycloneive_lcell_comb \z80_|alu_|alu_parity_out~1 ( +// Equation(s): +// \z80_|alu_|alu_parity_out~1_combout = \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout $ (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout $ (\z80_|alu_|alu_parity_out~0_combout $ +// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), + .datac(\z80_|alu_|alu_parity_out~0_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|alu_parity_out~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_parity_out~1 .lut_mask = 16'h9669; +defparam \z80_|alu_|alu_parity_out~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N24 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~4 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~4_combout = (\z80_|execute_|ctl_pf_sel[0]~2_combout & (((!\z80_|pla_decode_|Equal62~3_combout & !\z80_|execute_|ctl_alu_op_low~27_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_pf_sel[0]~2_combout ), + .datab(\z80_|pla_decode_|Equal62~3_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~4 .lut_mask = 16'h0A2A; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N18 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~5 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~5_combout = (\z80_|execute_|ctl_pf_sel[0]~3_combout & (!\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout $ +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout )))) # (!\z80_|execute_|ctl_pf_sel[0]~3_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout $ ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout )))) + + .dataa(\z80_|execute_|ctl_pf_sel[0]~3_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~5 .lut_mask = 16'h143C; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N16 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~6 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~6_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout & (((!\z80_|pla_decode_|Equal69~0_combout & \z80_|execute_|ctl_flags_bus~1_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal69~0_combout ), + .datab(\z80_|execute_|ctl_flags_bus~1_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~6 .lut_mask = 16'h4F00; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N6 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~1 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~1_combout = (\z80_|execute_|ctl_pf_sel[0]~3_combout & (!\z80_|execute_|ctl_alu_op_low~27_combout & (\z80_|execute_|ctl_pf_sel[0]~2_combout & !\z80_|pla_decode_|Equal62~3_combout ))) + + .dataa(\z80_|execute_|ctl_pf_sel[0]~3_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~27_combout ), + .datac(\z80_|execute_|ctl_pf_sel[0]~2_combout ), + .datad(\z80_|pla_decode_|Equal62~3_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~1 .lut_mask = 16'h0020; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N30 +cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~2 ( +// Equation(s): +// \z80_|decode_state_|DFFE_instNonRep~2_combout = (!\z80_|address_latch_|Q [6] & (!\z80_|address_latch_|Q [5] & (!\z80_|address_latch_|Q [4] & !\z80_|address_latch_|Q [7]))) + + .dataa(\z80_|address_latch_|Q [6]), + .datab(\z80_|address_latch_|Q [5]), + .datac(\z80_|address_latch_|Q [4]), + .datad(\z80_|address_latch_|Q [7]), + .cin(gnd), + .combout(\z80_|decode_state_|DFFE_instNonRep~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep~2 .lut_mask = 16'h0001; +defparam \z80_|decode_state_|DFFE_instNonRep~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N0 +cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~1 ( +// Equation(s): +// \z80_|decode_state_|DFFE_instNonRep~1_combout = (!\z80_|address_latch_|Q [9] & (!\z80_|address_latch_|Q [8] & (!\z80_|address_latch_|Q [11] & !\z80_|address_latch_|Q [10]))) + + .dataa(\z80_|address_latch_|Q [9]), + .datab(\z80_|address_latch_|Q [8]), + .datac(\z80_|address_latch_|Q [11]), + .datad(\z80_|address_latch_|Q [10]), + .cin(gnd), + .combout(\z80_|decode_state_|DFFE_instNonRep~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep~1 .lut_mask = 16'h0001; +defparam \z80_|decode_state_|DFFE_instNonRep~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N4 +cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~3 ( +// Equation(s): +// \z80_|decode_state_|DFFE_instNonRep~3_combout = (\z80_|address_latch_|Q [0] & (!\z80_|address_latch_|Q [2] & (!\z80_|address_latch_|Q [3] & !\z80_|address_latch_|Q [1]))) + + .dataa(\z80_|address_latch_|Q [0]), + .datab(\z80_|address_latch_|Q [2]), + .datac(\z80_|address_latch_|Q [3]), + .datad(\z80_|address_latch_|Q [1]), + .cin(gnd), + .combout(\z80_|decode_state_|DFFE_instNonRep~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep~3 .lut_mask = 16'h0002; +defparam \z80_|decode_state_|DFFE_instNonRep~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N28 +cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~0 ( +// Equation(s): +// \z80_|decode_state_|DFFE_instNonRep~0_combout = (!\z80_|address_latch_|Q [14] & (!\z80_|address_latch_|Q [15] & (!\z80_|address_latch_|Q [12] & !\z80_|address_latch_|Q [13]))) + + .dataa(\z80_|address_latch_|Q [14]), + .datab(\z80_|address_latch_|Q [15]), + .datac(\z80_|address_latch_|Q [12]), + .datad(\z80_|address_latch_|Q [13]), + .cin(gnd), + .combout(\z80_|decode_state_|DFFE_instNonRep~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep~0 .lut_mask = 16'h0001; +defparam \z80_|decode_state_|DFFE_instNonRep~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N24 +cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~4 ( +// Equation(s): +// \z80_|decode_state_|DFFE_instNonRep~4_combout = (\z80_|decode_state_|DFFE_instNonRep~2_combout & (\z80_|decode_state_|DFFE_instNonRep~1_combout & (\z80_|decode_state_|DFFE_instNonRep~3_combout & \z80_|decode_state_|DFFE_instNonRep~0_combout ))) + + .dataa(\z80_|decode_state_|DFFE_instNonRep~2_combout ), + .datab(\z80_|decode_state_|DFFE_instNonRep~1_combout ), + .datac(\z80_|decode_state_|DFFE_instNonRep~3_combout ), + .datad(\z80_|decode_state_|DFFE_instNonRep~0_combout ), + .cin(gnd), + .combout(\z80_|decode_state_|DFFE_instNonRep~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep~4 .lut_mask = 16'h8000; +defparam \z80_|decode_state_|DFFE_instNonRep~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N20 +cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~5 ( +// Equation(s): +// \z80_|decode_state_|DFFE_instNonRep~5_combout = (\z80_|execute_|ctl_flags_bus~1_combout & (((\z80_|decode_state_|DFFE_instNonRep~q )))) # (!\z80_|execute_|ctl_flags_bus~1_combout & ((\z80_|execute_|ixy_d~9_combout & +// (\z80_|decode_state_|DFFE_instNonRep~4_combout )) # (!\z80_|execute_|ixy_d~9_combout & ((\z80_|decode_state_|DFFE_instNonRep~q ))))) + + .dataa(\z80_|decode_state_|DFFE_instNonRep~4_combout ), + .datab(\z80_|execute_|ctl_flags_bus~1_combout ), + .datac(\z80_|decode_state_|DFFE_instNonRep~q ), + .datad(\z80_|execute_|ixy_d~9_combout ), + .cin(gnd), + .combout(\z80_|decode_state_|DFFE_instNonRep~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep~5 .lut_mask = 16'hE2F0; +defparam \z80_|decode_state_|DFFE_instNonRep~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y15_N21 +dffeas \z80_|decode_state_|DFFE_instNonRep ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|decode_state_|DFFE_instNonRep~5_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|decode_state_|DFFE_instNonRep~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep .is_wysiwyg = "true"; +defparam \z80_|decode_state_|DFFE_instNonRep .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N12 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~2 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~2_combout = (\z80_|pla_decode_|Equal69~0_combout & ((\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout & ((\z80_|interrupts_|DFFE_instIFF2~q ))) # (!\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout & +// (!\z80_|decode_state_|DFFE_instNonRep~q )))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout ), + .datab(\z80_|decode_state_|DFFE_instNonRep~q ), + .datac(\z80_|interrupts_|DFFE_instIFF2~q ), + .datad(\z80_|pla_decode_|Equal69~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~2 .lut_mask = 16'hB100; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N14 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~3 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~3_combout = (\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_flags_bus~1_combout & (\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout )) # (!\z80_|execute_|ctl_flags_bus~1_combout & +// ((!\z80_|decode_state_|DFFE_instNonRep~q ))))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|decode_state_|DFFE_instNonRep~q ), + .datad(\z80_|execute_|ctl_flags_bus~1_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~3 .lut_mask = 16'h880C; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N2 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~7 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~7_combout = (\z80_|pla_decode_|Equal69~0_combout ) # (((\z80_|pla_decode_|Equal62~3_combout ) # (\z80_|execute_|ctl_alu_op_low~27_combout )) # (!\z80_|execute_|ctl_flags_bus~1_combout )) + + .dataa(\z80_|pla_decode_|Equal69~0_combout ), + .datab(\z80_|execute_|ctl_flags_bus~1_combout ), + .datac(\z80_|pla_decode_|Equal62~3_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~7 .lut_mask = 16'hFFFB; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N0 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~8 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~8_combout = (\z80_|execute_|ctl_pf_sel[0]~2_combout & (\z80_|execute_|ctl_pf_sel[0]~3_combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout )))) + + .dataa(\z80_|execute_|ctl_pf_sel[0]~2_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_pf_sel[0]~3_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~8 .lut_mask = 16'h2A00; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N26 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~9 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~9_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ) # ((\z80_|alu_|alu_parity_out~1_combout & \z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ))) + + .dataa(\z80_|alu_|alu_parity_out~1_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~9 .lut_mask = 16'hFEFC; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N0 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~0 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~0_combout = (\z80_|execute_|ctl_flags_pf_we~9_combout & (\z80_|execute_|ctl_flags_bus~combout & ((\z80_|alu_control_|db[2]~29_combout )))) # (!\z80_|execute_|ctl_flags_pf_we~9_combout & +// (((\z80_|alu_flags_|DFFE_inst_latch_pf~q )))) + + .dataa(\z80_|execute_|ctl_flags_bus~combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), + .datac(\z80_|execute_|ctl_flags_pf_we~9_combout ), + .datad(\z80_|alu_control_|db[2]~29_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~0 .lut_mask = 16'hAC0C; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N16 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~10 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~10_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ) # ((\z80_|execute_|ctl_flags_alu~15_combout & (\z80_|execute_|ctl_flags_pf_we~9_combout & \z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ))) + + .dataa(\z80_|execute_|ctl_flags_alu~15_combout ), + .datab(\z80_|execute_|ctl_flags_pf_we~9_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~10 .lut_mask = 16'hFF80; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y15_N17 +dffeas \z80_|alu_flags_|DFFE_inst_latch_pf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|DFFE_inst_latch_pf~10_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y13_N6 +cycloneive_lcell_comb \z80_|alu_control_|sel[1]~0 ( +// Equation(s): +// \z80_|alu_control_|sel[1]~0_combout = (\z80_|ir_|opcode [5] & (((!\z80_|pla_decode_|Equal6~0_combout ) # (!\z80_|pla_decode_|Equal40~0_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal40~0_combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|sel[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|sel[1]~0 .lut_mask = 16'h4CCC; +defparam \z80_|alu_control_|sel[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N18 +cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_cond_mux|out~0 ( +// Equation(s): +// \z80_|alu_control_|b2v_inst_cond_mux|out~0_combout = (\z80_|alu_control_|sel[1]~0_combout & (((\z80_|ir_|opcode [4])))) # (!\z80_|alu_control_|sel[1]~0_combout & ((\z80_|ir_|opcode [4] & ((\z80_|alu_flags_|flags_cf~combout ))) # (!\z80_|ir_|opcode [4] +// & (\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q )))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datab(\z80_|alu_flags_|flags_cf~combout ), + .datac(\z80_|alu_control_|sel[1]~0_combout ), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|b2v_inst_cond_mux|out~0 .lut_mask = 16'hFC0A; +defparam \z80_|alu_control_|b2v_inst_cond_mux|out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N16 +cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_cond_mux|out~1 ( +// Equation(s): +// \z80_|alu_control_|b2v_inst_cond_mux|out~1_combout = (\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout & (((\z80_|alu_flags_|DFFE_inst_latch_sf~q ) # (!\z80_|alu_control_|sel[1]~0_combout )))) # (!\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout & +// (\z80_|alu_flags_|DFFE_inst_latch_pf~q & (\z80_|alu_control_|sel[1]~0_combout ))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), + .datab(\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ), + .datac(\z80_|alu_control_|sel[1]~0_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), + .cin(gnd), + .combout(\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|b2v_inst_cond_mux|out~1 .lut_mask = 16'hEC2C; +defparam \z80_|alu_control_|b2v_inst_cond_mux|out~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N26 +cycloneive_lcell_comb \z80_|alu_control_|flags_cond_true~0 ( +// Equation(s): +// \z80_|alu_control_|flags_cond_true~0_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|ir_|opcode [3] $ (((!\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ))))) # (!\z80_|execute_|ctl_eval_cond~0_combout & +// (((\z80_|alu_control_|flags_cond_true~q )))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|alu_control_|flags_cond_true~q ), + .datad(\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|flags_cond_true~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|flags_cond_true~0 .lut_mask = 16'hD872; +defparam \z80_|alu_control_|flags_cond_true~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y16_N27 +dffeas \z80_|alu_control_|flags_cond_true ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_control_|flags_cond_true~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_control_|flags_cond_true~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_control_|flags_cond_true .is_wysiwyg = "true"; +defparam \z80_|alu_control_|flags_cond_true .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~20 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~20_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|pla_decode_|Equal35~0_combout & \z80_|alu_control_|flags_cond_true~q ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|pla_decode_|Equal35~0_combout ), + .datad(\z80_|alu_control_|flags_cond_true~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~20 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sel_wz~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~1 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~1_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ) # ((\z80_|execute_|ctl_reg_sel_wz~20_combout ) # ((\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ctl_al_we~14_combout ))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~20_combout ), + .datad(\z80_|execute_|ctl_al_we~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~1 .lut_mask = 16'hFCFE; +defparam \z80_|execute_|ctl_sw_4d~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~6 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~6_combout = (\z80_|execute_|ctl_sw_4d~0_combout ) # ((\z80_|execute_|ctl_sw_4d~1_combout ) # (!\z80_|execute_|ctl_sw_4d~5_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_sw_4d~0_combout ), + .datac(\z80_|execute_|ctl_sw_4d~1_combout ), + .datad(\z80_|execute_|ctl_sw_4d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~6 .lut_mask = 16'hFCFF; +defparam \z80_|execute_|ctl_sw_4d~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y12_N17 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[1]~6_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N16 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~4 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[1]~4_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[1]~32_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # +// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[1]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[1]~4 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_lo_as[1]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y12_N23 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[1]~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N20 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~5 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[1]~5_combout = (\z80_|reg_file_|db_lo_as[1]~4_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|db_lo_as[1]~4_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_lo|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[1]~5 .lut_mask = 16'hC0CC; +defparam \z80_|reg_file_|db_lo_as[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N18 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout = \z80_|address_latch_|Q [1] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ) + + .dataa(\z80_|address_latch_|Q [1]), + .datab(gnd), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out .lut_mask = 16'h5A5A; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N22 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~6 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[1]~6_combout = ((\z80_|reg_file_|db_lo_as[1]~5_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .datab(\z80_|reg_file_|db_lo_as[1]~5_combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), + .datad(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[1]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[1]~6 .lut_mask = 16'hC4FF; +defparam \z80_|reg_file_|db_lo_as[1]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y12_N7 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~29 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~29_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [1] & ((\z80_|alu_control_|db[1]~26_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (((\z80_|alu_control_|db[1]~26_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [1]), + .datad(\z80_|alu_control_|db[1]~26_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~29 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[1]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y12_N15 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X31_Y12_N5 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~28 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~28_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datab(\z80_|reg_file_|b2v_latch_iy_lo|latch [1]), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~28 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp0[1]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y14_N1 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X32_Y14_N19 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~26 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~26_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [1]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [1]), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~26 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[1]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y13_N19 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~27 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~27_combout = (\z80_|reg_file_|gdfx_temp0[1]~26_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|gdfx_temp0[1]~26_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~27 .lut_mask = 16'hC0CC; +defparam \z80_|reg_file_|gdfx_temp0[1]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~30 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~30_combout = (\z80_|reg_file_|gdfx_temp0[1]~29_combout & (\z80_|reg_file_|gdfx_temp0[1]~28_combout & \z80_|reg_file_|gdfx_temp0[1]~27_combout )) + + .dataa(\z80_|reg_file_|gdfx_temp0[1]~29_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[1]~28_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[1]~27_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~30 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|gdfx_temp0[1]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y12_N7 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y12_N1 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~24 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~24_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [1] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [1] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [1]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~24 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp0[1]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y11_N5 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X31_Y11_N19 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~23 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~23_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [1]), + .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [1]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~23 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[1]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y11_N23 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X32_Y11_N25 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~25 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~25_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [1]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [1]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~25 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[1]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~31 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~31_combout = (\z80_|reg_file_|gdfx_temp0[1]~30_combout & (\z80_|reg_file_|gdfx_temp0[1]~24_combout & (\z80_|reg_file_|gdfx_temp0[1]~23_combout & \z80_|reg_file_|gdfx_temp0[1]~25_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[1]~30_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[1]~24_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[1]~23_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[1]~25_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~31 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[1]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~32 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~32_combout = ((\z80_|reg_file_|gdfx_temp0[1]~31_combout & ((\z80_|reg_file_|db_lo_as[1]~6_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), + .datab(\z80_|reg_file_|db_lo_as[1]~6_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[1]~31_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~32 .lut_mask = 16'hD0FF; +defparam \z80_|reg_file_|gdfx_temp0[1]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N30 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[1]~1 ( +// Equation(s): +// \z80_|reg_file_|db_lo_ds[1]~1_combout = (\z80_|reg_file_|gdfx_temp0[1]~32_combout ) # ((!\z80_|execute_|ctl_reg_out_lo~5_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout & \z80_|execute_|ctl_reg_out_lo~7_combout ))) + + .dataa(\z80_|execute_|ctl_reg_out_lo~5_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_ds[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_ds[1]~1 .lut_mask = 16'hFF40; +defparam \z80_|reg_file_|db_lo_ds[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N16 +cycloneive_lcell_comb \z80_|alu_control_|db[1]~25 ( +// Equation(s): +// \z80_|alu_control_|db[1]~25_combout = (\z80_|reg_file_|db_lo_ds[1]~1_combout & (((\z80_|bus_control_|db[1]~11_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) + + .dataa(\z80_|reg_file_|db_lo_ds[1]~1_combout ), + .datab(\z80_|bus_control_|db[1]~11_combout ), + .datac(\z80_|execute_|ctl_sw_1d~7_combout ), + .datad(\z80_|execute_|ctl_sw_mask543_en~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[1]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[1]~25 .lut_mask = 16'h0A8A; +defparam \z80_|alu_control_|db[1]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N4 +cycloneive_lcell_comb \z80_|alu_control_|db[1]~24 ( +// Equation(s): +// \z80_|alu_control_|db[1]~24_combout = (\z80_|execute_|ctl_flags_oe~2_combout & (((!\z80_|alu_|db[1]~10_combout & \z80_|execute_|ctl_sw_2u~7_combout )) # (!\z80_|alu_flags_|DFFE_inst_latch_nf~q ))) # (!\z80_|execute_|ctl_flags_oe~2_combout & +// (!\z80_|alu_|db[1]~10_combout & (\z80_|execute_|ctl_sw_2u~7_combout ))) + + .dataa(\z80_|execute_|ctl_flags_oe~2_combout ), + .datab(\z80_|alu_|db[1]~10_combout ), + .datac(\z80_|execute_|ctl_sw_2u~7_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .cin(gnd), + .combout(\z80_|alu_control_|db[1]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[1]~24 .lut_mask = 16'h30BA; +defparam \z80_|alu_control_|db[1]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N18 +cycloneive_lcell_comb \z80_|alu_control_|db[1]~26 ( +// Equation(s): +// \z80_|alu_control_|db[1]~26_combout = ((\z80_|alu_control_|db[1]~25_combout & (!\z80_|alu_control_|db[1]~24_combout & \z80_|alu_control_|db[2]~23_combout ))) # (!\z80_|alu_control_|db[6]~11_combout ) + + .dataa(\z80_|alu_control_|db[1]~25_combout ), + .datab(\z80_|alu_control_|db[1]~24_combout ), + .datac(\z80_|alu_control_|db[2]~23_combout ), + .datad(\z80_|alu_control_|db[6]~11_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[1]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[1]~26 .lut_mask = 16'h20FF; +defparam \z80_|alu_control_|db[1]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N2 +cycloneive_lcell_comb \z80_|bus_control_|db[1]~10 ( +// Equation(s): +// \z80_|bus_control_|db[1]~10_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[1]~26_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) + + .dataa(\z80_|bus_control_|db[0]~4_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datad(\z80_|alu_control_|db[1]~26_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[1]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[1]~10 .lut_mask = 16'hAA0A; +defparam \z80_|bus_control_|db[1]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|nextM~4 ( +// Equation(s): +// \z80_|execute_|nextM~4_combout = ((!\z80_|execute_|ctl_mRead~34_combout & ((!\z80_|pla_decode_|Equal24~0_combout ) # (!\z80_|pla_decode_|Equal21~0_combout )))) # (!\z80_|execute_|ctl_state_alu~2_combout ) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|pla_decode_|Equal21~0_combout ), + .datad(\z80_|pla_decode_|Equal24~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~4 .lut_mask = 16'h5777; +defparam \z80_|execute_|nextM~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_iorw~12 ( +// Equation(s): +// \z80_|execute_|ctl_iorw~12_combout = (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [2] & \z80_|execute_|ctl_eval_cond~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~0_combout ), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_iorw~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_iorw~12 .lut_mask = 16'h0200; +defparam \z80_|execute_|ctl_iorw~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_iorw~8 ( +// Equation(s): +// \z80_|execute_|ctl_iorw~8_combout = (\z80_|execute_|ctl_iorw~12_combout ) # ((\z80_|execute_|ctl_state_alu~2_combout & (\z80_|pla_decode_|Equal3~0_combout & \z80_|pla_decode_|Equal24~0_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ctl_iorw~12_combout ), + .datac(\z80_|pla_decode_|Equal3~0_combout ), + .datad(\z80_|pla_decode_|Equal24~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_iorw~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_iorw~8 .lut_mask = 16'hECCC; +defparam \z80_|execute_|ctl_iorw~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_iorw~9 ( +// Equation(s): +// \z80_|execute_|ctl_iorw~9_combout = ((\z80_|execute_|ctl_iorw~8_combout ) # ((\z80_|execute_|ctl_mWrite~17_combout & \z80_|execute_|ctl_mRead~9_combout ))) # (!\z80_|execute_|nextM~4_combout ) + + .dataa(\z80_|execute_|ctl_mWrite~17_combout ), + .datab(\z80_|execute_|nextM~4_combout ), + .datac(\z80_|execute_|ctl_mRead~9_combout ), + .datad(\z80_|execute_|ctl_iorw~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_iorw~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_iorw~9 .lut_mask = 16'hFFB3; +defparam \z80_|execute_|ctl_iorw~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y11_N29 +dffeas \z80_|memory_ifc_|DFFE_iorq_ff1 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|execute_|ctl_iorw~9_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_iorq_ff1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_iorq_ff1 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_iorq_ff1 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y11_N25 +dffeas \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|memory_ifc_|DFFE_iorq_ff1~q ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N14 +cycloneive_lcell_comb \z80_|memory_ifc_|wait_iorq~feeder ( +// Equation(s): +// \z80_|memory_ifc_|wait_iorq~feeder_combout = \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|wait_iorq~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_iorq~feeder .lut_mask = 16'hFF00; +defparam \z80_|memory_ifc_|wait_iorq~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y11_N15 +dffeas \z80_|memory_ifc_|wait_iorq ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|memory_ifc_|wait_iorq~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|wait_iorq~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_iorq .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|wait_iorq .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y11_N9 +dffeas \z80_|memory_ifc_|DFFE_iorq_ff4 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|memory_ifc_|wait_iorq~q ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_iorq_ff4~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_iorq_ff4 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_iorq_ff4 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N8 +cycloneive_lcell_comb \z80_|memory_ifc_|iorq~0 ( +// Equation(s): +// \z80_|memory_ifc_|iorq~0_combout = (\z80_|memory_ifc_|wait_iorq~q ) # ((\z80_|memory_ifc_|DFFE_iorq_ff4~q ) # (\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q )) + + .dataa(gnd), + .datab(\z80_|memory_ifc_|wait_iorq~q ), + .datac(\z80_|memory_ifc_|DFFE_iorq_ff4~q ), + .datad(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|iorq~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|iorq~0 .lut_mask = 16'hFFFC; +defparam \z80_|memory_ifc_|iorq~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y11_N3 +dffeas \z80_|memory_ifc_|DFFE_m1_ff1 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|execute_|setM1~54_combout ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_m1_ff1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_m1_ff1 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_m1_ff1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N26 +cycloneive_lcell_comb \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0 ( +// Equation(s): +// \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout = !\z80_|memory_ifc_|DFFE_m1_ff1~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|memory_ifc_|DFFE_m1_ff1~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0 .lut_mask = 16'h00FF; +defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y11_N27 +dffeas \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y11_N19 +dffeas \z80_|memory_ifc_|DFFE_m1_ff3 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_m1_ff3~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_m1_ff3 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_m1_ff3 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N18 +cycloneive_lcell_comb \z80_|memory_ifc_|nRD_out~0 ( +// Equation(s): +// \z80_|memory_ifc_|nRD_out~0_combout = (\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q & (((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q )) # (!\z80_|interrupts_|DFFE_inst44~q ))) # (!\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q & +// (\z80_|memory_ifc_|DFFE_m1_ff3~q & ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|interrupts_|DFFE_inst44~q )))) + + .dataa(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ), + .datab(\z80_|interrupts_|DFFE_inst44~q ), + .datac(\z80_|memory_ifc_|DFFE_m1_ff3~q ), + .datad(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|nRD_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|nRD_out~0 .lut_mask = 16'hFA32; +defparam \z80_|memory_ifc_|nRD_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|fIORead~0 ( +// Equation(s): +// \z80_|execute_|fIORead~0_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_mWrite~4_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # (\z80_|execute_|ctl_alu_op_low~22_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIORead~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIORead~0 .lut_mask = 16'hC080; +defparam \z80_|execute_|fIORead~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N22 +cycloneive_lcell_comb \z80_|execute_|fIORead~1 ( +// Equation(s): +// \z80_|execute_|fIORead~1_combout = (\z80_|pla_decode_|Equal68~2_combout & (\z80_|pla_decode_|Equal1~4_combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # (!\z80_|execute_|fIOWrite~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal68~2_combout ), + .datab(\z80_|pla_decode_|Equal1~4_combout ), + .datac(\z80_|execute_|ctl_mWrite~5_combout ), + .datad(\z80_|execute_|fIOWrite~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIORead~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIORead~1 .lut_mask = 16'h8088; +defparam \z80_|execute_|fIORead~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N30 +cycloneive_lcell_comb \z80_|execute_|fIORead~2 ( +// Equation(s): +// \z80_|execute_|fIORead~2_combout = (\z80_|execute_|fIORead~1_combout ) # ((\z80_|execute_|ctl_mWrite~17_combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # (\z80_|execute_|ctl_state_alu~3_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~5_combout ), + .datab(\z80_|execute_|ctl_state_alu~3_combout ), + .datac(\z80_|execute_|fIORead~1_combout ), + .datad(\z80_|execute_|ctl_mWrite~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIORead~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIORead~2 .lut_mask = 16'hFEF0; +defparam \z80_|execute_|fIORead~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|fIOWrite~1 ( +// Equation(s): +// \z80_|execute_|fIOWrite~1_combout = (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|execute_|ixy_d~4_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|execute_|ixy_d~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIOWrite~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIOWrite~1 .lut_mask = 16'hA0F0; +defparam \z80_|execute_|fIOWrite~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|fIORead~3 ( +// Equation(s): +// \z80_|execute_|fIORead~3_combout = (\z80_|execute_|fIORead~0_combout ) # ((\z80_|execute_|fIORead~2_combout ) # ((\z80_|execute_|ctl_mRead~2_combout & \z80_|execute_|fIOWrite~1_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~2_combout ), + .datab(\z80_|execute_|fIORead~0_combout ), + .datac(\z80_|execute_|fIORead~2_combout ), + .datad(\z80_|execute_|fIOWrite~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIORead~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIORead~3 .lut_mask = 16'hFEFC; +defparam \z80_|execute_|fIORead~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~30 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~30_combout = (\z80_|execute_|ctl_state_alu~2_combout & ((\z80_|pla_decode_|Equal33~3_combout ) # ((\z80_|pla_decode_|Equal41~2_combout ) # (\z80_|pla_decode_|Equal6~1_combout )))) + + .dataa(\z80_|pla_decode_|Equal33~3_combout ), + .datab(\z80_|pla_decode_|Equal41~2_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|pla_decode_|Equal6~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~30 .lut_mask = 16'hF0E0; +defparam \z80_|execute_|ctl_mRead~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~31 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~31_combout = (\z80_|execute_|ctl_mRead~30_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & \z80_|execute_|ctl_mRead~10_combout )) + + .dataa(\z80_|execute_|ctl_mRead~30_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .datad(\z80_|execute_|ctl_mRead~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~31 .lut_mask = 16'hFAAA; +defparam \z80_|execute_|ctl_mRead~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|nextM~3 ( +// Equation(s): +// \z80_|execute_|nextM~3_combout = (!\z80_|execute_|ixy_d~16_combout & (!\z80_|execute_|ixy_d~10_combout & !\z80_|pla_decode_|Equal41~2_combout )) + + .dataa(\z80_|execute_|ixy_d~16_combout ), + .datab(\z80_|execute_|ixy_d~10_combout ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|nextM~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~3 .lut_mask = 16'h0101; +defparam \z80_|execute_|nextM~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~29 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~29_combout = (\z80_|execute_|ixy_d~8_combout & (((\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal49~0_combout )) # (!\z80_|execute_|nextM~3_combout ))) + + .dataa(\z80_|execute_|nextM~3_combout ), + .datab(\z80_|execute_|ixy_d~8_combout ), + .datac(\z80_|decode_state_|use_ixiy~combout ), + .datad(\z80_|pla_decode_|Equal49~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~29 .lut_mask = 16'hC444; +defparam \z80_|execute_|ctl_mRead~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N26 +cycloneive_lcell_comb \z80_|execute_|setM1~58 ( +// Equation(s): +// \z80_|execute_|setM1~58_combout = (!\z80_|execute_|ctl_mRead~12_combout & ((\z80_|decode_state_|DFFE_instIY1~q ) # ((\z80_|decode_state_|DFFE_inst4~q ) # (!\z80_|pla_decode_|Equal49~0_combout )))) + + .dataa(\z80_|decode_state_|DFFE_instIY1~q ), + .datab(\z80_|decode_state_|DFFE_inst4~q ), + .datac(\z80_|pla_decode_|Equal49~0_combout ), + .datad(\z80_|execute_|ctl_mRead~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~58_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~58 .lut_mask = 16'h00EF; +defparam \z80_|execute_|setM1~58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|setM1~38 ( +// Equation(s): +// \z80_|execute_|setM1~38_combout = (\z80_|execute_|setM1~37_combout & \z80_|execute_|ctl_reg_sys_hilo~38_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|setM1~37_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo~38_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~38 .lut_mask = 16'hF000; +defparam \z80_|execute_|setM1~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|fMRead~4 ( +// Equation(s): +// \z80_|execute_|fMRead~4_combout = (\z80_|execute_|ctl_al_we~4_combout & (\z80_|execute_|ctl_reg_sel_wz~8_combout & !\z80_|pla_decode_|Equal34~0_combout )) + + .dataa(\z80_|execute_|ctl_al_we~4_combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~8_combout ), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal34~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~4 .lut_mask = 16'h0088; +defparam \z80_|execute_|fMRead~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N14 +cycloneive_lcell_comb \z80_|execute_|setM1~39 ( +// Equation(s): +// \z80_|execute_|setM1~39_combout = (!\z80_|pla_decode_|Equal29~0_combout & (\z80_|execute_|fMRead~4_combout & !\z80_|pla_decode_|Equal9~1_combout )) + + .dataa(\z80_|pla_decode_|Equal29~0_combout ), + .datab(gnd), + .datac(\z80_|execute_|fMRead~4_combout ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~39 .lut_mask = 16'h0050; +defparam \z80_|execute_|setM1~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N4 +cycloneive_lcell_comb \z80_|execute_|setM1~40 ( +// Equation(s): +// \z80_|execute_|setM1~40_combout = (\z80_|execute_|setM1~58_combout & (\z80_|execute_|setM1~38_combout & (\z80_|execute_|setM1~39_combout & !\z80_|execute_|ctl_mRead~14_combout ))) + + .dataa(\z80_|execute_|setM1~58_combout ), + .datab(\z80_|execute_|setM1~38_combout ), + .datac(\z80_|execute_|setM1~39_combout ), + .datad(\z80_|execute_|ctl_mRead~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~40 .lut_mask = 16'h0080; +defparam \z80_|execute_|setM1~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y14_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~32 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~32_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (((\z80_|execute_|ctl_mRead~11_combout ) # (!\z80_|execute_|setM1~40_combout )) # (!\z80_|execute_|ctl_mRead~17_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~17_combout ), + .datab(\z80_|execute_|ctl_mRead~11_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|setM1~40_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~32 .lut_mask = 16'hD0F0; +defparam \z80_|execute_|ctl_mRead~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y14_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~33 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~33_combout = (\z80_|execute_|ctl_mRead~31_combout ) # (((\z80_|execute_|ctl_mRead~29_combout ) # (\z80_|execute_|ctl_mRead~32_combout )) # (!\z80_|execute_|ctl_mRead~28_combout )) + + .dataa(\z80_|execute_|ctl_mRead~31_combout ), + .datab(\z80_|execute_|ctl_mRead~28_combout ), + .datac(\z80_|execute_|ctl_mRead~29_combout ), + .datad(\z80_|execute_|ctl_mRead~32_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~33 .lut_mask = 16'hFFFB; +defparam \z80_|execute_|ctl_mRead~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y14_N17 +dffeas \z80_|memory_ifc_|DFFE_mrd_ff1 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|execute_|ctl_mRead~33_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_mrd_ff1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_mrd_ff1 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_mrd_ff1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N30 +cycloneive_lcell_comb \z80_|memory_ifc_|wait_mrd~feeder ( +// Equation(s): +// \z80_|memory_ifc_|wait_mrd~feeder_combout = \z80_|memory_ifc_|DFFE_mrd_ff1~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|memory_ifc_|DFFE_mrd_ff1~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|wait_mrd~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_mrd~feeder .lut_mask = 16'hFF00; +defparam \z80_|memory_ifc_|wait_mrd~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y11_N31 +dffeas \z80_|memory_ifc_|wait_mrd ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|memory_ifc_|wait_mrd~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|wait_mrd~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_mrd .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|wait_mrd .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y11_N17 +dffeas \z80_|memory_ifc_|DFFE_mrd_ff3 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|memory_ifc_|wait_mrd~q ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_mrd_ff3~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_mrd_ff3 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_mrd_ff3 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N12 +cycloneive_lcell_comb \z80_|memory_ifc_|nRD_out~1 ( +// Equation(s): +// \z80_|memory_ifc_|nRD_out~1_combout = (!\z80_|memory_ifc_|wait_mrd~q & !\z80_|memory_ifc_|DFFE_mrd_ff3~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|memory_ifc_|wait_mrd~q ), + .datad(\z80_|memory_ifc_|DFFE_mrd_ff3~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|nRD_out~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|nRD_out~1 .lut_mask = 16'h000F; +defparam \z80_|memory_ifc_|nRD_out~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N20 +cycloneive_lcell_comb \z80_|memory_ifc_|nRD_out~2 ( +// Equation(s): +// \z80_|memory_ifc_|nRD_out~2_combout = (\z80_|memory_ifc_|nRD_out~0_combout ) # (((\z80_|memory_ifc_|iorq~0_combout & \z80_|execute_|fIORead~3_combout )) # (!\z80_|memory_ifc_|nRD_out~1_combout )) + + .dataa(\z80_|memory_ifc_|iorq~0_combout ), + .datab(\z80_|memory_ifc_|nRD_out~0_combout ), + .datac(\z80_|execute_|fIORead~3_combout ), + .datad(\z80_|memory_ifc_|nRD_out~1_combout ), + .cin(gnd), + .combout(\z80_|memory_ifc_|nRD_out~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|nRD_out~2 .lut_mask = 16'hECFF; +defparam \z80_|memory_ifc_|nRD_out~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|fIOWrite~3 ( +// Equation(s): +// \z80_|execute_|fIOWrite~3_combout = ((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|fIOWrite~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIOWrite~3 .lut_mask = 16'h0FCF; +defparam \z80_|execute_|fIOWrite~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|fIOWrite~4 ( +// Equation(s): +// \z80_|execute_|fIOWrite~4_combout = (\z80_|execute_|ctl_mRead~34_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ixy_d~6_combout ) # (!\z80_|execute_|fIOWrite~3_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|execute_|fIOWrite~3_combout ), + .datad(\z80_|execute_|ixy_d~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIOWrite~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIOWrite~4 .lut_mask = 16'hCC8C; +defparam \z80_|execute_|fIOWrite~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N22 +cycloneive_lcell_comb \z80_|execute_|fIOWrite~2 ( +// Equation(s): +// \z80_|execute_|fIOWrite~2_combout = (\z80_|execute_|ctl_iorw~10_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # ((\z80_|execute_|ctl_mWrite~5_combout ) # (!\z80_|execute_|fMRead~2_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ctl_iorw~10_combout ), + .datac(\z80_|execute_|ctl_mWrite~5_combout ), + .datad(\z80_|execute_|fMRead~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIOWrite~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIOWrite~2 .lut_mask = 16'hC8CC; +defparam \z80_|execute_|fIOWrite~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|fIOWrite~5 ( +// Equation(s): +// \z80_|execute_|fIOWrite~5_combout = (\z80_|execute_|fIOWrite~4_combout ) # ((\z80_|execute_|fIOWrite~2_combout ) # ((\z80_|execute_|ctl_mRead~3_combout & \z80_|execute_|fIOWrite~1_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~3_combout ), + .datab(\z80_|execute_|fIOWrite~4_combout ), + .datac(\z80_|execute_|fIOWrite~2_combout ), + .datad(\z80_|execute_|fIOWrite~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIOWrite~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIOWrite~5 .lut_mask = 16'hFEFC; +defparam \z80_|execute_|fIOWrite~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~15 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~15_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_mWrite~7_combout ) # ((\z80_|execute_|ctl_state_alu~2_combout & \z80_|execute_|ctl_mRead~5_combout )))) # (!\z80_|execute_|ctl_eval_cond~0_combout & +// (((\z80_|execute_|ctl_state_alu~2_combout & \z80_|execute_|ctl_mRead~5_combout )))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|ctl_mWrite~7_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_mRead~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~15 .lut_mask = 16'hF888; +defparam \z80_|execute_|ctl_mWrite~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~12 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~12_combout = (!\z80_|execute_|ctl_mWrite~18_combout & (((!\z80_|execute_|ctl_mRead~6_combout & !\z80_|execute_|ctl_mRead~8_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|ctl_mWrite~18_combout ), + .datac(\z80_|execute_|ctl_mRead~6_combout ), + .datad(\z80_|execute_|ctl_mRead~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~12 .lut_mask = 16'h1113; +defparam \z80_|execute_|ctl_mWrite~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~13 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~13_combout = (\z80_|execute_|ctl_mWrite~12_combout & (\z80_|execute_|ctl_mWrite~10_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|execute_|ctl_mWrite~8_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~8_combout ), + .datab(\z80_|execute_|ctl_mWrite~12_combout ), + .datac(\z80_|execute_|ctl_mWrite~10_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~13 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_mWrite~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~14 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~14_combout = (\z80_|execute_|ctl_mWrite~11_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~4_combout & (\z80_|execute_|ctl_mWrite~13_combout & \z80_|execute_|ctl_bus_db_oe~7_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~11_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), + .datac(\z80_|execute_|ctl_mWrite~13_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~14 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_mWrite~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~16 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~16_combout = (\z80_|execute_|ctl_mWrite~15_combout ) # (((\z80_|execute_|ixy_d~8_combout & !\z80_|execute_|ixy_d~17_combout )) # (!\z80_|execute_|ctl_mWrite~14_combout )) + + .dataa(\z80_|execute_|ctl_mWrite~15_combout ), + .datab(\z80_|execute_|ixy_d~8_combout ), + .datac(\z80_|execute_|ixy_d~17_combout ), + .datad(\z80_|execute_|ctl_mWrite~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~16 .lut_mask = 16'hAEFF; +defparam \z80_|execute_|ctl_mWrite~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y11_N7 +dffeas \z80_|memory_ifc_|DFFE_mwr_ff1 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|execute_|ctl_mWrite~16_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_mwr_ff1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_mwr_ff1 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_mwr_ff1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N22 +cycloneive_lcell_comb \z80_|memory_ifc_|wait_mwr~feeder ( +// Equation(s): +// \z80_|memory_ifc_|wait_mwr~feeder_combout = \z80_|memory_ifc_|DFFE_mwr_ff1~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|memory_ifc_|DFFE_mwr_ff1~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|wait_mwr~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_mwr~feeder .lut_mask = 16'hFF00; +defparam \z80_|memory_ifc_|wait_mwr~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y11_N23 +dffeas \z80_|memory_ifc_|wait_mwr ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|memory_ifc_|wait_mwr~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|wait_mwr~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_mwr .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|wait_mwr .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y11_N21 +dffeas \z80_|memory_ifc_|mwr_wr ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|memory_ifc_|wait_mwr~q ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|mwr_wr~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|mwr_wr .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|mwr_wr .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N20 +cycloneive_lcell_comb \z80_|memory_ifc_|nWR_out~0 ( +// Equation(s): +// \z80_|memory_ifc_|nWR_out~0_combout = (\z80_|memory_ifc_|mwr_wr~q ) # ((\z80_|execute_|fIOWrite~5_combout & \z80_|memory_ifc_|iorq~0_combout )) + + .dataa(\z80_|execute_|fIOWrite~5_combout ), + .datab(\z80_|memory_ifc_|iorq~0_combout ), + .datac(\z80_|memory_ifc_|mwr_wr~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|memory_ifc_|nWR_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|nWR_out~0 .lut_mask = 16'hF8F8; +defparam \z80_|memory_ifc_|nWR_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N16 +cycloneive_lcell_comb \Equal2~1 ( +// Equation(s): +// \Equal2~1_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\z80_|memory_ifc_|nRD_out~2_combout & !\z80_|memory_ifc_|nWR_out~0_combout )) + + .dataa(gnd), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|memory_ifc_|nRD_out~2_combout ), + .datad(\z80_|memory_ifc_|nWR_out~0_combout ), + .cin(gnd), + .combout(\Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \Equal2~1 .lut_mask = 16'h00C0; +defparam \Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|fMWrite~3 ( +// Equation(s): +// \z80_|execute_|fMWrite~3_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|sequencer_|DFFE_M4_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~3 .lut_mask = 16'h7373; +defparam \z80_|execute_|fMWrite~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|fMWrite~4 ( +// Equation(s): +// \z80_|execute_|fMWrite~4_combout = (!\z80_|execute_|fMWrite~3_combout & ((\z80_|execute_|ctl_mWrite~7_combout ) # ((\z80_|pla_decode_|Equal13~2_combout ) # (\z80_|execute_|ctl_mRead~5_combout )))) + + .dataa(\z80_|execute_|fMWrite~3_combout ), + .datab(\z80_|execute_|ctl_mWrite~7_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|execute_|ctl_mRead~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~4 .lut_mask = 16'h5554; +defparam \z80_|execute_|fMWrite~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N24 +cycloneive_lcell_comb \z80_|execute_|fMWrite~0 ( +// Equation(s): +// \z80_|execute_|fMWrite~0_combout = ((!\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|M5~q ) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~0 .lut_mask = 16'h0F5F; +defparam \z80_|execute_|fMWrite~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|fMWrite~2 ( +// Equation(s): +// \z80_|execute_|fMWrite~2_combout = (!\z80_|execute_|fMWrite~1_combout & (((\z80_|execute_|ixy_d~6_combout ) # (\z80_|execute_|ixy_d~5_combout )) # (!\z80_|execute_|fMWrite~0_combout ))) + + .dataa(\z80_|execute_|fMWrite~1_combout ), + .datab(\z80_|execute_|fMWrite~0_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~2 .lut_mask = 16'h5551; +defparam \z80_|execute_|fMWrite~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N8 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~3 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~3_combout = (\z80_|execute_|ctl_bus_inc_oe~26_combout & (!\z80_|execute_|fMWrite~4_combout & (!\z80_|execute_|fMWrite~2_combout & !\z80_|execute_|fIOWrite~5_combout ))) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~26_combout ), + .datab(\z80_|execute_|fMWrite~4_combout ), + .datac(\z80_|execute_|fMWrite~2_combout ), + .datad(\z80_|execute_|fIOWrite~5_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~3 .lut_mask = 16'h0002; +defparam \z80_|pin_control_|bus_db_pin_oe~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|fMWrite~8 ( +// Equation(s): +// \z80_|execute_|fMWrite~8_combout = (\z80_|pla_decode_|Equal9~1_combout & (((\z80_|execute_|ctl_alu_oe~0_combout ) # (\z80_|execute_|ctl_reg_in_hi~2_combout )))) # (!\z80_|pla_decode_|Equal9~1_combout & (\z80_|execute_|ctl_mRead~8_combout & +// ((\z80_|execute_|ctl_alu_oe~0_combout ) # (\z80_|execute_|ctl_reg_in_hi~2_combout )))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ctl_mRead~8_combout ), + .datac(\z80_|execute_|ctl_alu_oe~0_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~8 .lut_mask = 16'hEEE0; +defparam \z80_|execute_|fMWrite~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|fMWrite~7 ( +// Equation(s): +// \z80_|execute_|fMWrite~7_combout = (\z80_|execute_|ctl_state_alu~4_combout & ((\z80_|execute_|ctl_mRead~5_combout ) # ((\z80_|execute_|ctl_mWrite~7_combout ) # (\z80_|execute_|ctl_mRead~7_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~5_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_mWrite~7_combout ), + .datad(\z80_|execute_|ctl_mRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~7 .lut_mask = 16'hCCC8; +defparam \z80_|execute_|fMWrite~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N26 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~16 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~16_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & (((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|pla_decode_|Equal13~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), + .datab(\z80_|pla_decode_|Equal13~2_combout ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~16 .lut_mask = 16'h1555; +defparam \z80_|pin_control_|bus_db_pin_oe~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N14 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~8 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~8_combout = (\z80_|execute_|ixy_d~5_combout & (!\z80_|execute_|ctl_mRead~5_combout & ((!\z80_|execute_|ctl_ir_we~4_combout ) # (!\z80_|execute_|ctl_mRead~8_combout )))) # (!\z80_|execute_|ixy_d~5_combout & +// (((!\z80_|execute_|ctl_ir_we~4_combout )) # (!\z80_|execute_|ctl_mRead~8_combout ))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_mRead~8_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|execute_|ctl_mRead~5_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~8 .lut_mask = 16'h153F; +defparam \z80_|pin_control_|bus_db_pin_oe~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|fMWrite~6 ( +// Equation(s): +// \z80_|execute_|fMWrite~6_combout = ((\z80_|pla_decode_|Equal46~0_combout ) # ((\z80_|ir_|opcode [6] & !\z80_|ir_|opcode [7]))) # (!\z80_|execute_|ctl_ir_we~5_combout ) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|execute_|ctl_ir_we~5_combout ), + .datad(\z80_|pla_decode_|Equal46~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~6 .lut_mask = 16'hFF2F; +defparam \z80_|execute_|fMWrite~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N8 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~9 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~9_combout = (\z80_|execute_|fMWrite~6_combout & (((\z80_|execute_|fIOWrite~0_combout )) # (!\z80_|execute_|ctl_mWrite~8_combout ))) # (!\z80_|execute_|fMWrite~6_combout & (\z80_|execute_|fMWrite~0_combout & +// ((\z80_|execute_|fIOWrite~0_combout ) # (!\z80_|execute_|ctl_mWrite~8_combout )))) + + .dataa(\z80_|execute_|fMWrite~6_combout ), + .datab(\z80_|execute_|ctl_mWrite~8_combout ), + .datac(\z80_|execute_|fIOWrite~0_combout ), + .datad(\z80_|execute_|fMWrite~0_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~9 .lut_mask = 16'hF3A2; +defparam \z80_|pin_control_|bus_db_pin_oe~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N28 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~7 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~7_combout = (\z80_|execute_|ixy_d~7_combout & (((\z80_|execute_|fMRead~3_combout & !\z80_|execute_|ctl_mRead~4_combout )))) # (!\z80_|execute_|ixy_d~7_combout & (((!\z80_|execute_|ctl_mRead~4_combout )) # +// (!\z80_|execute_|ctl_alu_oe~0_combout ))) + + .dataa(\z80_|execute_|ctl_alu_oe~0_combout ), + .datab(\z80_|execute_|fMRead~3_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ctl_mRead~4_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~7 .lut_mask = 16'h05CF; +defparam \z80_|pin_control_|bus_db_pin_oe~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N10 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~10 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~10_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (\z80_|pin_control_|bus_db_pin_oe~8_combout & (\z80_|pin_control_|bus_db_pin_oe~9_combout & \z80_|pin_control_|bus_db_pin_oe~7_combout ))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~8_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~9_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~7_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~10 .lut_mask = 16'h8000; +defparam \z80_|pin_control_|bus_db_pin_oe~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N20 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~11 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~11_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout & (!\z80_|execute_|fMWrite~7_combout & (\z80_|execute_|ctl_reg_sel_wz~7_combout & \z80_|pin_control_|bus_db_pin_oe~10_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), + .datab(\z80_|execute_|fMWrite~7_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~7_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~10_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~11 .lut_mask = 16'h2000; +defparam \z80_|pin_control_|bus_db_pin_oe~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N6 +cycloneive_lcell_comb \z80_|execute_|fMWrite~5 ( +// Equation(s): +// \z80_|execute_|fMWrite~5_combout = (!\z80_|execute_|ctl_mWrite~17_combout & (!\z80_|execute_|ctl_mWrite~6_combout & !\z80_|execute_|ctl_mRead~5_combout )) + + .dataa(\z80_|execute_|ctl_mWrite~17_combout ), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datac(\z80_|execute_|ctl_mRead~5_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~5 .lut_mask = 16'h0101; +defparam \z80_|execute_|fMWrite~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N28 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~6 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~6_combout = (\z80_|execute_|ctl_inc_dec~2_combout & ((\z80_|execute_|fMWrite~5_combout ) # ((!\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ixy_d~6_combout )))) + + .dataa(\z80_|execute_|fMWrite~5_combout ), + .datab(\z80_|execute_|ctl_inc_dec~2_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ixy_d~6_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~6 .lut_mask = 16'h888C; +defparam \z80_|pin_control_|bus_db_pin_oe~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N26 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~12 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~12_combout = (!\z80_|execute_|fMWrite~8_combout & (\z80_|pin_control_|bus_db_pin_oe~11_combout & (\z80_|execute_|ctl_bus_inc_oe~30_combout & \z80_|pin_control_|bus_db_pin_oe~6_combout ))) + + .dataa(\z80_|execute_|fMWrite~8_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~11_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~30_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~6_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~12 .lut_mask = 16'h4000; +defparam \z80_|pin_control_|bus_db_pin_oe~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y16_N20 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~4 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~4_combout = (\z80_|pla_decode_|Equal11~0_combout & (!\z80_|execute_|ixy_d~7_combout & ((!\z80_|execute_|ctl_mRead~6_combout ) # (!\z80_|execute_|ctl_reg_in_hi~2_combout )))) # (!\z80_|pla_decode_|Equal11~0_combout & +// (((!\z80_|execute_|ctl_mRead~6_combout )) # (!\z80_|execute_|ctl_reg_in_hi~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datac(\z80_|execute_|ctl_mRead~6_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~4 .lut_mask = 16'h153F; +defparam \z80_|pin_control_|bus_db_pin_oe~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N30 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~5 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~5_combout = (\z80_|pin_control_|bus_db_pin_oe~4_combout & (((\z80_|execute_|ixy_d~4_combout ) # (!\z80_|execute_|ctl_mWrite~7_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|execute_|ctl_mWrite~7_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~4_combout ), + .datad(\z80_|execute_|ixy_d~4_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~5 .lut_mask = 16'hF070; +defparam \z80_|pin_control_|bus_db_pin_oe~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N24 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~13 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~13_combout = (\z80_|pin_control_|bus_db_pin_oe~12_combout & (\z80_|pin_control_|bus_db_pin_oe~5_combout & ((!\z80_|execute_|ixy_d~6_combout ) # (!\z80_|pla_decode_|Equal11~0_combout )))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~12_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~5_combout ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|execute_|ixy_d~6_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~13 .lut_mask = 16'h0888; +defparam \z80_|pin_control_|bus_db_pin_oe~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y18_N12 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~14 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~14_combout = (\z80_|pin_control_|bus_db_pin_oe~3_combout & (\z80_|execute_|ctl_inc_cy~35_combout & (\z80_|execute_|ctl_apin_mux~0_combout & \z80_|pin_control_|bus_db_pin_oe~13_combout ))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~3_combout ), + .datab(\z80_|execute_|ctl_inc_cy~35_combout ), + .datac(\z80_|execute_|ctl_apin_mux~0_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~13_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~14 .lut_mask = 16'h8000; +defparam \z80_|pin_control_|bus_db_pin_oe~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N4 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~2 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~2_combout = (\z80_|sequencer_|DFFE_T3_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~2 .lut_mask = 16'hFFCC; +defparam \z80_|pin_control_|bus_db_pin_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N14 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~15 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~15_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout & (\z80_|execute_|fIOWrite~5_combout & ((\z80_|sequencer_|DFFE_T4_ff~q )))) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout & +// ((\z80_|pin_control_|bus_db_pin_oe~2_combout ) # ((\z80_|execute_|fIOWrite~5_combout & \z80_|sequencer_|DFFE_T4_ff~q )))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .datab(\z80_|execute_|fIOWrite~5_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~2_combout ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~15 .lut_mask = 16'hDC50; +defparam \z80_|pin_control_|bus_db_pin_oe~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N12 +cycloneive_lcell_comb \z80_|clk_delay_|DFF_inst5~feeder ( +// Equation(s): +// \z80_|clk_delay_|DFF_inst5~feeder_combout = \z80_|clk_delay_|SYNTHESIZED_WIRE_7~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ), + .cin(gnd), + .combout(\z80_|clk_delay_|DFF_inst5~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|clk_delay_|DFF_inst5~feeder .lut_mask = 16'hFF00; +defparam \z80_|clk_delay_|DFF_inst5~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X38_Y11_N13 +dffeas \z80_|clk_delay_|DFF_inst5 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|clk_delay_|DFF_inst5~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|clk_delay_|DFF_inst5~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|clk_delay_|DFF_inst5 .is_wysiwyg = "true"; +defparam \z80_|clk_delay_|DFF_inst5 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y11_N15 +dffeas \z80_|memory_ifc_|wait_iorqinta ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|clk_delay_|DFF_inst5~q ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|wait_iorqinta~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_iorqinta .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|wait_iorqinta .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y11_N31 +dffeas \z80_|memory_ifc_|DFFE_intr_ff3 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|memory_ifc_|wait_iorqinta~q ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_intr_ff3~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_intr_ff3 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_intr_ff3 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N30 +cycloneive_lcell_comb \z80_|memory_ifc_|nIORQ_out~0 ( +// Equation(s): +// \z80_|memory_ifc_|nIORQ_out~0_combout = (\z80_|memory_ifc_|iorq~0_combout ) # ((\z80_|memory_ifc_|wait_iorqinta~q ) # (\z80_|memory_ifc_|DFFE_intr_ff3~q )) + + .dataa(\z80_|memory_ifc_|iorq~0_combout ), + .datab(\z80_|memory_ifc_|wait_iorqinta~q ), + .datac(\z80_|memory_ifc_|DFFE_intr_ff3~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|memory_ifc_|nIORQ_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|nIORQ_out~0 .lut_mask = 16'hFEFE; +defparam \z80_|memory_ifc_|nIORQ_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N28 +cycloneive_lcell_comb \Equal2~0 ( +// Equation(s): +// \Equal2~0_combout = (\z80_|memory_ifc_|nIORQ_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\z80_|memory_ifc_|nRD_out~2_combout & !\z80_|memory_ifc_|nWR_out~0_combout ))) + + .dataa(\z80_|memory_ifc_|nIORQ_out~0_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|memory_ifc_|nRD_out~2_combout ), + .datad(\z80_|memory_ifc_|nWR_out~0_combout ), + .cin(gnd), + .combout(\Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \Equal2~0 .lut_mask = 16'h0080; +defparam \Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~2 ( +// Equation(s): +// \z80_|execute_|ctl_apin_mux~2_combout = ((\z80_|execute_|ctl_apin_mux~1_combout & \z80_|execute_|ctl_mWrite~6_combout )) # (!\z80_|execute_|ctl_inc_dec~6_combout ) + + .dataa(\z80_|execute_|ctl_apin_mux~1_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_inc_dec~6_combout ), + .datad(\z80_|execute_|ctl_mWrite~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_apin_mux~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_apin_mux~2 .lut_mask = 16'hAF0F; +defparam \z80_|execute_|ctl_apin_mux~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N8 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[10]~10 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[10]~10_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [10]))) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [10]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[10]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[10]~10 .lut_mask = 16'hDD88; +defparam \z80_|address_pins_|DFFE_apin_latch[10]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux2~0 ( +// Equation(s): +// \z80_|execute_|ctl_apin_mux2~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_apin_mux2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_apin_mux2~0 .lut_mask = 16'h4545; +defparam \z80_|execute_|ctl_apin_mux2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N24 +cycloneive_lcell_comb \z80_|pin_control_|bus_ab_pin_we~0 ( +// Equation(s): +// \z80_|pin_control_|bus_ab_pin_we~0_combout = ((\z80_|execute_|fIORead~3_combout ) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout )) # (!\z80_|sequencer_|DFFE_M1_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|execute_|fIORead~3_combout ), + .datac(gnd), + .datad(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_ab_pin_we~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_ab_pin_we~0 .lut_mask = 16'hDDFF; +defparam \z80_|pin_control_|bus_ab_pin_we~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N26 +cycloneive_lcell_comb \z80_|pin_control_|bus_ab_pin_we~1 ( +// Equation(s): +// \z80_|pin_control_|bus_ab_pin_we~1_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # ((!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|execute_|fMRead~36_combout ) # (\z80_|pin_control_|bus_ab_pin_we~0_combout )))) + + .dataa(\z80_|execute_|fMRead~36_combout ), + .datab(\z80_|pin_control_|bus_ab_pin_we~0_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_ab_pin_we~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_ab_pin_we~1 .lut_mask = 16'hFF0E; +defparam \z80_|pin_control_|bus_ab_pin_we~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y13_N9 +dffeas \z80_|address_pins_|DFFE_apin_latch[10] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[10]~10_combout ), + .asdata(\z80_|address_latch_|Q [10]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [10]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[10] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[10] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X18_Y34_N1 +cycloneive_io_ibuf \PS2_DAT~input ( + .i(PS2_DAT), + .ibar(gnd), + .o(\PS2_DAT~input_o )); +// synopsys translate_off +defparam \PS2_DAT~input .bus_hold = "false"; +defparam \PS2_DAT~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X53_Y14_N1 +cycloneive_io_ibuf \KEY[0]~input ( + .i(KEY[0]), + .ibar(gnd), + .o(\KEY[0]~input_o )); +// synopsys translate_off +defparam \KEY[0]~input .bus_hold = "false"; +defparam \KEY[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X52_Y17_N6 +cycloneive_lcell_comb reset( +// Equation(s): +// \reset~combout = (!\KEY[0]~input_o ) # (!\ula_|pll_|altpll_component|auto_generated|wire_pll1_locked ) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|pll_|altpll_component|auto_generated|wire_pll1_locked ), + .datad(\KEY[0]~input_o ), + .cin(gnd), + .combout(\reset~combout ), + .cout()); +// synopsys translate_off +defparam reset.lut_mask = 16'h0FFF; +defparam reset.sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: CLKCTRL_G8 +cycloneive_clkctrl \reset~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\reset~combout }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\reset~clkctrl_outclk )); +// synopsys translate_off +defparam \reset~clkctrl .clock_type = "global clock"; +defparam \reset~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y10_N0 +cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~3 ( +// Equation(s): +// \ula_|ps2_keyboard_|bit_count~3_combout = (\ula_|ps2_keyboard_|bit_count [2] & (\ula_|ps2_keyboard_|bit_count [0] & (!\ula_|ps2_keyboard_|bit_count [3] & \ula_|ps2_keyboard_|bit_count [1]))) # (!\ula_|ps2_keyboard_|bit_count [2] & +// (((\ula_|ps2_keyboard_|bit_count [3] & !\ula_|ps2_keyboard_|bit_count [1])))) + + .dataa(\ula_|ps2_keyboard_|bit_count [0]), + .datab(\ula_|ps2_keyboard_|bit_count [2]), + .datac(\ula_|ps2_keyboard_|bit_count [3]), + .datad(\ula_|ps2_keyboard_|bit_count [1]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|bit_count~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count~3 .lut_mask = 16'h0830; +defparam \ula_|ps2_keyboard_|bit_count~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X9_Y34_N8 +cycloneive_io_ibuf \PS2_CLK~input ( + .i(PS2_CLK), + .ibar(gnd), + .o(\PS2_CLK~input_o )); +// synopsys translate_off +defparam \PS2_CLK~input .bus_hold = "false"; +defparam \PS2_CLK~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y26_N20 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[7]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[7]~feeder_combout = \PS2_CLK~input_o + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\PS2_CLK~input_o ), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[7]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y26_N21 +dffeas \ula_|ps2_keyboard_|clk_filter[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[7] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y26_N18 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[6]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[6]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [7] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [7]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[6]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y26_N19 +dffeas \ula_|ps2_keyboard_|clk_filter[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[6] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y26_N0 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[5]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[5]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [6] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [6]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[5]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y26_N1 +dffeas \ula_|ps2_keyboard_|clk_filter[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[5] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y26_N6 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[4]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[4]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [5]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[4]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y26_N7 +dffeas \ula_|ps2_keyboard_|clk_filter[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[4] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y26_N10 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[3]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[3]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [4] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [4]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[3]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y26_N11 +dffeas \ula_|ps2_keyboard_|clk_filter[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[3]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[3] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y26_N24 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[2]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[2]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [3] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [3]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[2]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y26_N25 +dffeas \ula_|ps2_keyboard_|clk_filter[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[2] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y26_N26 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[1]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[1]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [2]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[1]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y26_N27 +dffeas \ula_|ps2_keyboard_|clk_filter[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[1] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y26_N16 +cycloneive_lcell_comb \ula_|ps2_keyboard_|Equal0~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|Equal0~0_combout = (!\ula_|ps2_keyboard_|clk_filter [4] & (!\ula_|ps2_keyboard_|clk_filter [7] & (!\ula_|ps2_keyboard_|clk_filter [6] & !\ula_|ps2_keyboard_|clk_filter [5]))) + + .dataa(\ula_|ps2_keyboard_|clk_filter [4]), + .datab(\ula_|ps2_keyboard_|clk_filter [7]), + .datac(\ula_|ps2_keyboard_|clk_filter [6]), + .datad(\ula_|ps2_keyboard_|clk_filter [5]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|Equal0~0 .lut_mask = 16'h0001; +defparam \ula_|ps2_keyboard_|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y26_N12 +cycloneive_lcell_comb \ula_|ps2_keyboard_|Equal0~1 ( +// Equation(s): +// \ula_|ps2_keyboard_|Equal0~1_combout = (!\ula_|ps2_keyboard_|clk_filter [3] & (!\ula_|ps2_keyboard_|clk_filter [2] & (!\ula_|ps2_keyboard_|clk_filter [1] & \ula_|ps2_keyboard_|Equal0~0_combout ))) + + .dataa(\ula_|ps2_keyboard_|clk_filter [3]), + .datab(\ula_|ps2_keyboard_|clk_filter [2]), + .datac(\ula_|ps2_keyboard_|clk_filter [1]), + .datad(\ula_|ps2_keyboard_|Equal0~0_combout ), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|Equal0~1 .lut_mask = 16'h0100; +defparam \ula_|ps2_keyboard_|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y26_N2 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[0]~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[0]~0_combout = !\ula_|ps2_keyboard_|clk_filter [1] + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|clk_filter [1]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[0]~0 .lut_mask = 16'h0F0F; +defparam \ula_|ps2_keyboard_|clk_filter[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y26_N3 +dffeas \ula_|ps2_keyboard_|clk_filter[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[0]~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[0] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y26_N22 +cycloneive_lcell_comb \ula_|ps2_keyboard_|ps2_clk_in~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|ps2_clk_in~0_combout = (\ula_|ps2_keyboard_|Equal0~1_combout & ((\ula_|ps2_keyboard_|clk_filter [0]))) # (!\ula_|ps2_keyboard_|Equal0~1_combout & (\ula_|ps2_keyboard_|ps2_clk_in~q )) + + .dataa(\ula_|ps2_keyboard_|Equal0~1_combout ), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|ps2_clk_in~q ), + .datad(\ula_|ps2_keyboard_|clk_filter [0]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|ps2_clk_in~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|ps2_clk_in~0 .lut_mask = 16'hFA50; +defparam \ula_|ps2_keyboard_|ps2_clk_in~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y26_N23 +dffeas \ula_|ps2_keyboard_|ps2_clk_in ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|ps2_clk_in~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|ps2_clk_in~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|ps2_clk_in .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|ps2_clk_in .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y26_N28 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_edge~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_edge~0_combout = (\ula_|ps2_keyboard_|Equal0~1_combout & (!\ula_|ps2_keyboard_|ps2_clk_in~q & \ula_|ps2_keyboard_|clk_filter [0])) + + .dataa(\ula_|ps2_keyboard_|Equal0~1_combout ), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|ps2_clk_in~q ), + .datad(\ula_|ps2_keyboard_|clk_filter [0]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_edge~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_edge~0 .lut_mask = 16'h0A00; +defparam \ula_|ps2_keyboard_|clk_edge~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y26_N29 +dffeas \ula_|ps2_keyboard_|clk_edge ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_edge~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_edge~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_edge .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_edge .power_up = "low"; +// synopsys translate_on + +// Location: FF_X21_Y10_N1 +dffeas \ula_|ps2_keyboard_|bit_count[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|bit_count~3_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|clk_edge~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|bit_count [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count[3] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|bit_count[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y10_N28 +cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~1 ( +// Equation(s): +// \ula_|ps2_keyboard_|bit_count~1_combout = (!\ula_|ps2_keyboard_|bit_count [3] & (\ula_|ps2_keyboard_|bit_count [2] $ (((\ula_|ps2_keyboard_|bit_count [0] & \ula_|ps2_keyboard_|bit_count [1]))))) + + .dataa(\ula_|ps2_keyboard_|bit_count [0]), + .datab(\ula_|ps2_keyboard_|bit_count [3]), + .datac(\ula_|ps2_keyboard_|bit_count [2]), + .datad(\ula_|ps2_keyboard_|bit_count [1]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|bit_count~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count~1 .lut_mask = 16'h1230; +defparam \ula_|ps2_keyboard_|bit_count~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y10_N29 +dffeas \ula_|ps2_keyboard_|bit_count[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|bit_count~1_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|clk_edge~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|bit_count [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count[2] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|bit_count[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y10_N10 +cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~2 ( +// Equation(s): +// \ula_|ps2_keyboard_|bit_count~2_combout = (\ula_|ps2_keyboard_|bit_count [0] & (!\ula_|ps2_keyboard_|bit_count [1] & ((!\ula_|ps2_keyboard_|bit_count [3]) # (!\ula_|ps2_keyboard_|bit_count [2])))) # (!\ula_|ps2_keyboard_|bit_count [0] & +// (((\ula_|ps2_keyboard_|bit_count [1] & !\ula_|ps2_keyboard_|bit_count [3])))) + + .dataa(\ula_|ps2_keyboard_|bit_count [0]), + .datab(\ula_|ps2_keyboard_|bit_count [2]), + .datac(\ula_|ps2_keyboard_|bit_count [1]), + .datad(\ula_|ps2_keyboard_|bit_count [3]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|bit_count~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count~2 .lut_mask = 16'h025A; +defparam \ula_|ps2_keyboard_|bit_count~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y10_N11 +dffeas \ula_|ps2_keyboard_|bit_count[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|bit_count~2_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|clk_edge~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|bit_count [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count[1] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|bit_count[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y10_N22 +cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|bit_count~0_combout = (!\ula_|ps2_keyboard_|bit_count [0] & (((!\ula_|ps2_keyboard_|bit_count [1] & !\ula_|ps2_keyboard_|bit_count [2])) # (!\ula_|ps2_keyboard_|bit_count [3]))) + + .dataa(\ula_|ps2_keyboard_|bit_count [1]), + .datab(\ula_|ps2_keyboard_|bit_count [2]), + .datac(\ula_|ps2_keyboard_|bit_count [0]), + .datad(\ula_|ps2_keyboard_|bit_count [3]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|bit_count~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count~0 .lut_mask = 16'h010F; +defparam \ula_|ps2_keyboard_|bit_count~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y10_N23 +dffeas \ula_|ps2_keyboard_|bit_count[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|bit_count~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|clk_edge~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|bit_count [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count[0] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|bit_count[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y10_N2 +cycloneive_lcell_comb \ula_|ps2_keyboard_|always1~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|always1~0_combout = (!\ula_|ps2_keyboard_|bit_count [1] & (!\ula_|ps2_keyboard_|bit_count [2] & (!\PS2_DAT~input_o & !\ula_|ps2_keyboard_|bit_count [3]))) + + .dataa(\ula_|ps2_keyboard_|bit_count [1]), + .datab(\ula_|ps2_keyboard_|bit_count [2]), + .datac(\PS2_DAT~input_o ), + .datad(\ula_|ps2_keyboard_|bit_count [3]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|always1~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|always1~0 .lut_mask = 16'h0001; +defparam \ula_|ps2_keyboard_|always1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y10_N12 +cycloneive_lcell_comb \ula_|ps2_keyboard_|LessThan0~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|LessThan0~0_combout = (\ula_|ps2_keyboard_|bit_count [3] & ((\ula_|ps2_keyboard_|bit_count [1]) # (\ula_|ps2_keyboard_|bit_count [2]))) + + .dataa(\ula_|ps2_keyboard_|bit_count [1]), + .datab(\ula_|ps2_keyboard_|bit_count [2]), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|bit_count [3]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|LessThan0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|LessThan0~0 .lut_mask = 16'hEE00; +defparam \ula_|ps2_keyboard_|LessThan0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y10_N26 +cycloneive_lcell_comb \ula_|ps2_keyboard_|shiftreg[0]~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|shiftreg[0]~0_combout = (\ula_|ps2_keyboard_|clk_edge~q & (!\ula_|ps2_keyboard_|LessThan0~0_combout & ((\ula_|ps2_keyboard_|bit_count [0]) # (!\ula_|ps2_keyboard_|always1~0_combout )))) + + .dataa(\ula_|ps2_keyboard_|bit_count [0]), + .datab(\ula_|ps2_keyboard_|always1~0_combout ), + .datac(\ula_|ps2_keyboard_|clk_edge~q ), + .datad(\ula_|ps2_keyboard_|LessThan0~0_combout ), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[0]~0 .lut_mask = 16'h00B0; +defparam \ula_|ps2_keyboard_|shiftreg[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y8_N17 +dffeas \ula_|ps2_keyboard_|shiftreg[8] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\PS2_DAT~input_o ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [8]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[8] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N14 +cycloneive_lcell_comb \ula_|ps2_keyboard_|shiftreg[7]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|shiftreg[7]~feeder_combout = \ula_|ps2_keyboard_|shiftreg [8] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [8]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|shiftreg[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[7]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|shiftreg[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y8_N15 +dffeas \ula_|ps2_keyboard_|shiftreg[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|shiftreg[7]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[7] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y8_N9 +dffeas \ula_|ps2_keyboard_|shiftreg[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [7]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[6] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y8_N5 +dffeas \ula_|ps2_keyboard_|shiftreg[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [6]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[5] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y8_N23 +dffeas \ula_|ps2_keyboard_|shiftreg[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [5]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[4] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y9_N17 +dffeas \ula_|ps2_keyboard_|shiftreg[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [4]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[3] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y8_N23 +dffeas \ula_|ps2_keyboard_|shiftreg[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [3]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[2] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y8_N21 +dffeas \ula_|ps2_keyboard_|shiftreg[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [2]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[1] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N18 +cycloneive_lcell_comb \ula_|ps2_keyboard_|shiftreg[0]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|shiftreg[0]~feeder_combout = \ula_|ps2_keyboard_|shiftreg [1] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|shiftreg[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[0]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|shiftreg[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y10_N19 +dffeas \ula_|ps2_keyboard_|shiftreg[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|shiftreg[0]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[0] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N4 +cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|WideXor0~0_combout = \ula_|ps2_keyboard_|shiftreg [1] $ (\ula_|ps2_keyboard_|shiftreg [0] $ (\ula_|ps2_keyboard_|shiftreg [3] $ (\ula_|ps2_keyboard_|shiftreg [2]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|WideXor0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|WideXor0~0 .lut_mask = 16'h6996; +defparam \ula_|ps2_keyboard_|WideXor0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N16 +cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~1 ( +// Equation(s): +// \ula_|ps2_keyboard_|WideXor0~1_combout = \ula_|ps2_keyboard_|shiftreg [6] $ (\ula_|ps2_keyboard_|shiftreg [5] $ (\ula_|ps2_keyboard_|shiftreg [8] $ (\ula_|ps2_keyboard_|shiftreg [7]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|ps2_keyboard_|shiftreg [8]), + .datad(\ula_|ps2_keyboard_|shiftreg [7]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|WideXor0~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|WideXor0~1 .lut_mask = 16'h6996; +defparam \ula_|ps2_keyboard_|WideXor0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N22 +cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~2 ( +// Equation(s): +// \ula_|ps2_keyboard_|WideXor0~2_combout = \ula_|ps2_keyboard_|shiftreg [4] $ (\ula_|ps2_keyboard_|WideXor0~0_combout $ (\ula_|ps2_keyboard_|WideXor0~1_combout )) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|WideXor0~0_combout ), + .datad(\ula_|ps2_keyboard_|WideXor0~1_combout ), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|WideXor0~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|WideXor0~2 .lut_mask = 16'hA55A; +defparam \ula_|ps2_keyboard_|WideXor0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y10_N4 +cycloneive_lcell_comb \ula_|ps2_keyboard_|scan_code_ready~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|scan_code_ready~0_combout = (\PS2_DAT~input_o & (\ula_|ps2_keyboard_|clk_edge~q & (\ula_|ps2_keyboard_|WideXor0~2_combout & \ula_|ps2_keyboard_|LessThan0~0_combout ))) + + .dataa(\PS2_DAT~input_o ), + .datab(\ula_|ps2_keyboard_|clk_edge~q ), + .datac(\ula_|ps2_keyboard_|WideXor0~2_combout ), + .datad(\ula_|ps2_keyboard_|LessThan0~0_combout ), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|scan_code_ready~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|scan_code_ready~0 .lut_mask = 16'h8000; +defparam \ula_|ps2_keyboard_|scan_code_ready~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y10_N5 +dffeas \ula_|ps2_keyboard_|scan_code_ready ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|scan_code_ready~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|scan_code_ready~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|scan_code_ready .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|scan_code_ready .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~0 ( +// Equation(s): +// \ula_|zx_keyboard_|Equal0~0_combout = (\ula_|ps2_keyboard_|shiftreg [7] & (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [7]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|Equal0~0 .lut_mask = 16'h0200; +defparam \ula_|zx_keyboard_|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~1 ( +// Equation(s): +// \ula_|zx_keyboard_|Equal0~1_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|Equal0~0_combout & !\ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|zx_keyboard_|Equal0~0_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|Equal0~1 .lut_mask = 16'h0020; +defparam \ula_|zx_keyboard_|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|released~0 ( +// Equation(s): +// \ula_|zx_keyboard_|released~0_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (\ula_|zx_keyboard_|Equal0~1_combout & ((\ula_|ps2_keyboard_|shiftreg [4]) # (\ula_|zx_keyboard_|released~q )))) # (!\ula_|ps2_keyboard_|scan_code_ready~q & +// (((\ula_|zx_keyboard_|released~q )))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|scan_code_ready~q ), + .datac(\ula_|zx_keyboard_|released~q ), + .datad(\ula_|zx_keyboard_|Equal0~1_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|released~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|released~0 .lut_mask = 16'hF830; +defparam \ula_|zx_keyboard_|released~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y8_N25 +dffeas \ula_|zx_keyboard_|released ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|released~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|released~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|released .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|released .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|extended~0 ( +// Equation(s): +// \ula_|zx_keyboard_|extended~0_combout = (\ula_|zx_keyboard_|Equal0~1_combout & ((\ula_|zx_keyboard_|extended~q ) # (!\ula_|ps2_keyboard_|shiftreg [4]))) + + .dataa(\ula_|zx_keyboard_|Equal0~1_combout ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|extended~q ), + .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|extended~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|extended~0 .lut_mask = 16'hA0AA; +defparam \ula_|zx_keyboard_|extended~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y8_N31 +dffeas \ula_|zx_keyboard_|extended ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|extended~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|scan_code_ready~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|extended~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|extended .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|extended .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~21 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][1]~21_combout = (!\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [7] & \ula_|ps2_keyboard_|scan_code_ready~q )) + + .dataa(\ula_|zx_keyboard_|extended~q ), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [7]), + .datad(\ula_|ps2_keyboard_|scan_code_ready~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][1]~21_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][1]~21 .lut_mask = 16'h0500; +defparam \ula_|zx_keyboard_|keys[7][1]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~22 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][4]~22_combout = (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [4]) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][4]~22_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][4]~22 .lut_mask = 16'hA0A0; +defparam \ula_|zx_keyboard_|keys[5][4]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][4]~23 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][4]~23_combout = (\ula_|zx_keyboard_|keys[7][1]~21_combout & (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[5][4]~22_combout & !\ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|zx_keyboard_|keys[7][1]~21_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|zx_keyboard_|keys[5][4]~22_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][4]~23_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][4]~23 .lut_mask = 16'h0020; +defparam \ula_|zx_keyboard_|keys[1][4]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][1]~24 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][1]~24_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[1][4]~23_combout )) + + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(gnd), + .datad(\ula_|zx_keyboard_|keys[1][4]~23_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][1]~24_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][1]~24 .lut_mask = 16'h2200; +defparam \ula_|zx_keyboard_|keys[2][1]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][1]~25 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][1]~25_combout = (\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[2][1]~24_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[2][1]~24_combout & ((\ula_|zx_keyboard_|keys[2][1]~q ))))) # +// (!\ula_|ps2_keyboard_|shiftreg [3] & (((\ula_|zx_keyboard_|keys[2][1]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|zx_keyboard_|keys[2][1]~q ), + .datad(\ula_|zx_keyboard_|keys[2][1]~24_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][1]~25_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][1]~25 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[2][1]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y9_N21 +dffeas \ula_|zx_keyboard_|keys[2][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[2][1]~25_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[2][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[2][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~0 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row~0_combout = ((\z80_|address_pins_|DFFE_apin_latch [10]) # (!\ula_|zx_keyboard_|keys[2][1]~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [10]), + .datad(\ula_|zx_keyboard_|keys[2][1]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row~0 .lut_mask = 16'hF3FF; +defparam \ula_|zx_keyboard_|key_row~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~26 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][1]~26_combout = (\ula_|zx_keyboard_|keys[7][1]~21_combout & (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[5][4]~22_combout & !\ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|zx_keyboard_|keys[7][1]~21_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|zx_keyboard_|keys[5][4]~22_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][1]~26_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][1]~26 .lut_mask = 16'h0020; +defparam \ula_|zx_keyboard_|keys[3][1]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~27 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][1]~27_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [3])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][1]~27_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][1]~27 .lut_mask = 16'h2200; +defparam \ula_|zx_keyboard_|keys[3][1]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~28 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][1]~28_combout = (\ula_|zx_keyboard_|keys[3][1]~26_combout & ((\ula_|zx_keyboard_|keys[3][1]~27_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][1]~27_combout & ((\ula_|zx_keyboard_|keys[3][1]~q +// ))))) # (!\ula_|zx_keyboard_|keys[3][1]~26_combout & (((\ula_|zx_keyboard_|keys[3][1]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[3][1]~26_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[3][1]~q ), + .datad(\ula_|zx_keyboard_|keys[3][1]~27_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][1]~28_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][1]~28 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[3][1]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y9_N29 +dffeas \ula_|zx_keyboard_|keys[3][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[3][1]~28_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[3][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[3][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N12 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[11]~11 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[11]~11_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|address [11])) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [11]))) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [11]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[11]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[11]~11 .lut_mask = 16'hDD88; +defparam \z80_|address_pins_|DFFE_apin_latch[11]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y13_N13 +dffeas \z80_|address_pins_|DFFE_apin_latch[11] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[11]~11_combout ), + .asdata(\z80_|address_latch_|Q [11]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [11]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[11] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y6_N16 +cycloneive_lcell_comb \z80_|address_pins_|abus[11]~19 ( +// Equation(s): +// \z80_|address_pins_|abus[11]~19_combout = (\z80_|address_pins_|DFFE_apin_latch [11]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [11]), + .cin(gnd), + .combout(\z80_|address_pins_|abus[11]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[11]~19 .lut_mask = 16'hFF0F; +defparam \z80_|address_pins_|abus[11]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~17 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][4]~17_combout = (!\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [7] & \ula_|ps2_keyboard_|scan_code_ready~q ))) + + .dataa(\ula_|zx_keyboard_|extended~q ), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [7]), + .datad(\ula_|ps2_keyboard_|scan_code_ready~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][4]~17_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][4]~17 .lut_mask = 16'h0100; +defparam \ula_|zx_keyboard_|keys[7][4]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~18 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][4]~18_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][4]~18_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][4]~18 .lut_mask = 16'h4000; +defparam \ula_|zx_keyboard_|keys[6][4]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][1]~19 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][1]~19_combout = (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[7][4]~17_combout & \ula_|zx_keyboard_|keys[6][4]~18_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|zx_keyboard_|keys[7][4]~17_combout ), + .datad(\ula_|zx_keyboard_|keys[6][4]~18_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][1]~19_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][1]~19 .lut_mask = 16'h4000; +defparam \ula_|zx_keyboard_|keys[1][1]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][1]~20 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][1]~20_combout = (\ula_|zx_keyboard_|keys[1][1]~19_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[1][1]~19_combout & ((\ula_|zx_keyboard_|keys[1][1]~q ))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[1][1]~q ), + .datad(\ula_|zx_keyboard_|keys[1][1]~19_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][1]~20_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][1]~20 .lut_mask = 16'h55F0; +defparam \ula_|zx_keyboard_|keys[1][1]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y7_N17 +dffeas \ula_|zx_keyboard_|keys[1][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[1][1]~20_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[1][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[1][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N4 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[9]~9 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[9]~9_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [9]))) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [9]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[9]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[9]~9 .lut_mask = 16'hDD88; +defparam \z80_|address_pins_|DFFE_apin_latch[9]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y10_N5 +dffeas \z80_|address_pins_|DFFE_apin_latch[9] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[9]~9_combout ), + .asdata(\z80_|address_latch_|Q [9]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [9]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[9] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N10 +cycloneive_lcell_comb \z80_|address_pins_|abus[9]~17 ( +// Equation(s): +// \z80_|address_pins_|abus[9]~17_combout = (\z80_|address_pins_|DFFE_apin_latch [9]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [9]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_pins_|abus[9]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[9]~17 .lut_mask = 16'hCFCF; +defparam \z80_|address_pins_|abus[9]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~13 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][0]~13_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (!\ula_|ps2_keyboard_|shiftreg [7] & !\ula_|zx_keyboard_|Equal0~1_combout )) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|scan_code_ready~q ), + .datac(\ula_|ps2_keyboard_|shiftreg [7]), + .datad(\ula_|zx_keyboard_|Equal0~1_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][0]~13_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][0]~13 .lut_mask = 16'h000C; +defparam \ula_|zx_keyboard_|keys[0][0]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~2 ( +// Equation(s): +// \ula_|zx_keyboard_|shifted~2_combout = (!\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|zx_keyboard_|extended~q & \ula_|zx_keyboard_|keys[0][0]~13_combout )) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|zx_keyboard_|extended~q ), + .datad(\ula_|zx_keyboard_|keys[0][0]~13_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|shifted~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|shifted~2 .lut_mask = 16'h0300; +defparam \ula_|zx_keyboard_|shifted~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~14 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][1]~14_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [4] $ (\ula_|ps2_keyboard_|shiftreg [2])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][1]~14_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][1]~14 .lut_mask = 16'h1020; +defparam \ula_|zx_keyboard_|keys[0][1]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~15 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][1]~15_combout = (\ula_|zx_keyboard_|keys[0][1]~14_combout & ((\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [1])) # (!\ula_|ps2_keyboard_|shiftreg [4] & +// (\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [1])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|zx_keyboard_|keys[0][1]~14_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][1]~15 .lut_mask = 16'h0840; +defparam \ula_|zx_keyboard_|keys[0][1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr17~0 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr17~0_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [3]))) # (!\ula_|ps2_keyboard_|shiftreg [1] & +// (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [3]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr17~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr17~0 .lut_mask = 16'h4002; +defparam \ula_|zx_keyboard_|WideOr17~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~5 ( +// Equation(s): +// \ula_|zx_keyboard_|shifted~5_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|zx_keyboard_|WideOr17~0_combout )) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|zx_keyboard_|WideOr17~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|shifted~5_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|shifted~5 .lut_mask = 16'h2020; +defparam \ula_|zx_keyboard_|shifted~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~4 ( +// Equation(s): +// \ula_|zx_keyboard_|shifted~4_combout = (\ula_|zx_keyboard_|shifted~5_combout & ((\ula_|zx_keyboard_|shifted~2_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|shifted~2_combout & ((\ula_|zx_keyboard_|shifted~q ))))) # +// (!\ula_|zx_keyboard_|shifted~5_combout & (((\ula_|zx_keyboard_|shifted~q )))) + + .dataa(\ula_|zx_keyboard_|shifted~5_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|shifted~q ), + .datad(\ula_|zx_keyboard_|shifted~2_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|shifted~4_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|shifted~4 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|shifted~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y10_N27 +dffeas \ula_|zx_keyboard_|shifted ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|shifted~4_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|shifted~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|shifted .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|shifted .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~12 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][1]~12_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & !\ula_|ps2_keyboard_|shiftreg [4])) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|shifted~q ), + .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][1]~12_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][1]~12 .lut_mask = 16'hCCCF; +defparam \ula_|zx_keyboard_|keys[0][1]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~16 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][1]~16_combout = (\ula_|zx_keyboard_|shifted~2_combout & ((\ula_|zx_keyboard_|keys[0][1]~15_combout & ((!\ula_|zx_keyboard_|keys[0][1]~12_combout ))) # (!\ula_|zx_keyboard_|keys[0][1]~15_combout & +// (\ula_|zx_keyboard_|keys[0][1]~q )))) # (!\ula_|zx_keyboard_|shifted~2_combout & (((\ula_|zx_keyboard_|keys[0][1]~q )))) + + .dataa(\ula_|zx_keyboard_|shifted~2_combout ), + .datab(\ula_|zx_keyboard_|keys[0][1]~15_combout ), + .datac(\ula_|zx_keyboard_|keys[0][1]~q ), + .datad(\ula_|zx_keyboard_|keys[0][1]~12_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][1]~16_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][1]~16 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[0][1]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y10_N21 +dffeas \ula_|zx_keyboard_|keys[0][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[0][1]~16_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[0][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[0][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N0 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[8]~8 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[8]~8_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [8]))) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [8]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[8]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[8]~8 .lut_mask = 16'hDD88; +defparam \z80_|address_pins_|DFFE_apin_latch[8]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y10_N1 +dffeas \z80_|address_pins_|DFFE_apin_latch[8] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[8]~8_combout ), + .asdata(\z80_|address_latch_|Q [8]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [8]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[8] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N24 +cycloneive_lcell_comb \z80_|address_pins_|abus[8]~18 ( +// Equation(s): +// \z80_|address_pins_|abus[8]~18_combout = (\z80_|address_pins_|DFFE_apin_latch [8]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [8]), + .cin(gnd), + .combout(\z80_|address_pins_|abus[8]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[8]~18 .lut_mask = 16'hFF0F; +defparam \z80_|address_pins_|abus[8]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N2 +cycloneive_lcell_comb \D[1]~26 ( +// Equation(s): +// \D[1]~26_combout = (\ula_|zx_keyboard_|keys[1][1]~q & (\z80_|address_pins_|abus[9]~17_combout & ((\z80_|address_pins_|abus[8]~18_combout ) # (!\ula_|zx_keyboard_|keys[0][1]~q )))) # (!\ula_|zx_keyboard_|keys[1][1]~q & +// (((\z80_|address_pins_|abus[8]~18_combout ) # (!\ula_|zx_keyboard_|keys[0][1]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[1][1]~q ), + .datab(\z80_|address_pins_|abus[9]~17_combout ), + .datac(\ula_|zx_keyboard_|keys[0][1]~q ), + .datad(\z80_|address_pins_|abus[8]~18_combout ), + .cin(gnd), + .combout(\D[1]~26_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~26 .lut_mask = 16'hDD0D; +defparam \D[1]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N4 +cycloneive_lcell_comb \D[1]~27 ( +// Equation(s): +// \D[1]~27_combout = (\ula_|zx_keyboard_|key_row~0_combout & (\D[1]~26_combout & ((\z80_|address_pins_|abus[11]~19_combout ) # (!\ula_|zx_keyboard_|keys[3][1]~q )))) + + .dataa(\ula_|zx_keyboard_|key_row~0_combout ), + .datab(\ula_|zx_keyboard_|keys[3][1]~q ), + .datac(\z80_|address_pins_|abus[11]~19_combout ), + .datad(\D[1]~26_combout ), + .cin(gnd), + .combout(\D[1]~27_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~27 .lut_mask = 16'hA200; +defparam \D[1]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N16 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[12]~12 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[12]~12_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [12]))) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [12]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[12]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[12]~12 .lut_mask = 16'hDD88; +defparam \z80_|address_pins_|DFFE_apin_latch[12]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y13_N17 +dffeas \z80_|address_pins_|DFFE_apin_latch[12] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[12]~12_combout ), + .asdata(\z80_|address_latch_|Q [12]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [12]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[12] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N28 +cycloneive_lcell_comb \z80_|address_pins_|abus[12]~21 ( +// Equation(s): +// \z80_|address_pins_|abus[12]~21_combout = (\z80_|address_pins_|DFFE_apin_latch [12]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [12]), + .cin(gnd), + .combout(\z80_|address_pins_|abus[12]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[12]~21 .lut_mask = 16'hFF0F; +defparam \z80_|address_pins_|abus[12]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N2 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout = \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout $ (\z80_|address_latch_|Q [13]) + + .dataa(gnd), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), + .datac(gnd), + .datad(\z80_|address_latch_|Q [13]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out .lut_mask = 16'h33CC; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N6 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[13]~13 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[13]~13_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [13])) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|abusz [13]), + .datac(gnd), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[13]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[13]~13 .lut_mask = 16'hEE44; +defparam \z80_|address_pins_|DFFE_apin_latch[13]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y13_N7 +dffeas \z80_|address_pins_|DFFE_apin_latch[13] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[13]~13_combout ), + .asdata(\z80_|address_latch_|Q [13]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [13]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[13] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N6 +cycloneive_lcell_comb \z80_|address_pins_|abus[13]~20 ( +// Equation(s): +// \z80_|address_pins_|abus[13]~20_combout = (\z80_|address_pins_|DFFE_apin_latch [13]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(gnd), + .datad(\z80_|address_pins_|DFFE_apin_latch [13]), + .cin(gnd), + .combout(\z80_|address_pins_|abus[13]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[13]~20 .lut_mask = 16'hFF33; +defparam \z80_|address_pins_|abus[13]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~36 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][1]~36_combout = (!\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [5])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][1]~36_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1]~36 .lut_mask = 16'h0005; +defparam \ula_|zx_keyboard_|keys[5][1]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~34 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][1]~34_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|zx_keyboard_|extended~q & \ula_|zx_keyboard_|keys[0][0]~13_combout )) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|zx_keyboard_|extended~q ), + .datad(\ula_|zx_keyboard_|keys[0][0]~13_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][1]~34_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1]~34 .lut_mask = 16'h0300; +defparam \ula_|zx_keyboard_|keys[5][1]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~35 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][1]~35_combout = (\ula_|zx_keyboard_|keys[5][1]~34_combout & (\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [2])) + + .dataa(\ula_|zx_keyboard_|keys[5][1]~34_combout ), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][1]~35_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1]~35 .lut_mask = 16'hA000; +defparam \ula_|zx_keyboard_|keys[5][1]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~33 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][1]~33_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [3] & \ula_|zx_keyboard_|shifted~q )) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|zx_keyboard_|shifted~q ), + .datac(gnd), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][1]~33_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1]~33 .lut_mask = 16'hFF88; +defparam \ula_|zx_keyboard_|keys[5][1]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~37 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][1]~37_combout = (\ula_|zx_keyboard_|keys[5][1]~36_combout & ((\ula_|zx_keyboard_|keys[5][1]~35_combout & ((!\ula_|zx_keyboard_|keys[5][1]~33_combout ))) # (!\ula_|zx_keyboard_|keys[5][1]~35_combout & +// (\ula_|zx_keyboard_|keys[5][1]~q )))) # (!\ula_|zx_keyboard_|keys[5][1]~36_combout & (((\ula_|zx_keyboard_|keys[5][1]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][1]~36_combout ), + .datab(\ula_|zx_keyboard_|keys[5][1]~35_combout ), + .datac(\ula_|zx_keyboard_|keys[5][1]~q ), + .datad(\ula_|zx_keyboard_|keys[5][1]~33_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][1]~37_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1]~37 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[5][1]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y10_N23 +dffeas \ula_|zx_keyboard_|keys[5][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[5][1]~37_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[5][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[5][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][1]~29 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][1]~29_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [2]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][1]~29_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][1]~29 .lut_mask = 16'h0F00; +defparam \ula_|zx_keyboard_|keys[4][1]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~30 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][2]~30_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [5])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][2]~30_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2]~30 .lut_mask = 16'h0202; +defparam \ula_|zx_keyboard_|keys[7][2]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~31 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][2]~31_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[7][1]~21_combout & (\ula_|zx_keyboard_|keys[7][2]~30_combout & \ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|zx_keyboard_|keys[7][1]~21_combout ), + .datac(\ula_|zx_keyboard_|keys[7][2]~30_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][2]~31_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][2]~31 .lut_mask = 16'h4000; +defparam \ula_|zx_keyboard_|keys[5][2]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][1]~32 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][1]~32_combout = (\ula_|zx_keyboard_|keys[4][1]~29_combout & ((\ula_|zx_keyboard_|keys[5][2]~31_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[5][2]~31_combout & ((\ula_|zx_keyboard_|keys[4][1]~q +// ))))) # (!\ula_|zx_keyboard_|keys[4][1]~29_combout & (((\ula_|zx_keyboard_|keys[4][1]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[4][1]~29_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[4][1]~q ), + .datad(\ula_|zx_keyboard_|keys[5][2]~31_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][1]~32_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][1]~32 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[4][1]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y10_N25 +dffeas \ula_|zx_keyboard_|keys[4][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[4][1]~32_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[4][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[4][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N28 +cycloneive_lcell_comb \D[1]~28 ( +// Equation(s): +// \D[1]~28_combout = (\z80_|address_pins_|abus[12]~21_combout & ((\z80_|address_pins_|abus[13]~20_combout ) # ((!\ula_|zx_keyboard_|keys[5][1]~q )))) # (!\z80_|address_pins_|abus[12]~21_combout & (!\ula_|zx_keyboard_|keys[4][1]~q & +// ((\z80_|address_pins_|abus[13]~20_combout ) # (!\ula_|zx_keyboard_|keys[5][1]~q )))) + + .dataa(\z80_|address_pins_|abus[12]~21_combout ), + .datab(\z80_|address_pins_|abus[13]~20_combout ), + .datac(\ula_|zx_keyboard_|keys[5][1]~q ), + .datad(\ula_|zx_keyboard_|keys[4][1]~q ), + .cin(gnd), + .combout(\D[1]~28_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~28 .lut_mask = 16'h8ACF; +defparam \D[1]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N6 +cycloneive_lcell_comb \z80_|address_pins_|abus[0]~16 ( +// Equation(s): +// \z80_|address_pins_|abus[0]~16_combout = (\z80_|address_pins_|DFFE_apin_latch [0]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [0]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_pins_|abus[0]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[0]~16 .lut_mask = 16'hCFCF; +defparam \z80_|address_pins_|abus[0]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N18 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[14]~14 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[14]~14_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|address [14])) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [14]))) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [14]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[14]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[14]~14 .lut_mask = 16'hDD88; +defparam \z80_|address_pins_|DFFE_apin_latch[14]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y13_N19 +dffeas \z80_|address_pins_|DFFE_apin_latch[14] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[14]~14_combout ), + .asdata(\z80_|address_latch_|Q [14]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [14]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[14] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N20 +cycloneive_lcell_comb \z80_|address_pins_|abus[14]~23 ( +// Equation(s): +// \z80_|address_pins_|abus[14]~23_combout = (\z80_|address_pins_|DFFE_apin_latch [14]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [14]), + .cin(gnd), + .combout(\z80_|address_pins_|abus[14]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[14]~23 .lut_mask = 16'hFF0F; +defparam \z80_|address_pins_|abus[14]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~40 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][1]~40_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [1])) # (!\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [4] & +// \ula_|ps2_keyboard_|shiftreg [1])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][1]~40_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1]~40 .lut_mask = 16'h1188; +defparam \ula_|zx_keyboard_|keys[6][1]~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~41 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][1]~41_combout = (\ula_|zx_keyboard_|keys[6][1]~40_combout & (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [2] $ (\ula_|ps2_keyboard_|shiftreg [3])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|zx_keyboard_|keys[6][1]~40_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][1]~41_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1]~41 .lut_mask = 16'h6000; +defparam \ula_|zx_keyboard_|keys[6][1]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~39 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][1]~39_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|zx_keyboard_|keys[0][0]~13_combout & !\ula_|zx_keyboard_|extended~q ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|zx_keyboard_|keys[0][0]~13_combout ), + .datad(\ula_|zx_keyboard_|extended~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][1]~39_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1]~39 .lut_mask = 16'h0020; +defparam \ula_|zx_keyboard_|keys[6][1]~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~38 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][1]~38_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [2])) + + .dataa(\ula_|zx_keyboard_|shifted~q ), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][1]~38_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1]~38 .lut_mask = 16'hFFA0; +defparam \ula_|zx_keyboard_|keys[6][1]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~42 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][1]~42_combout = (\ula_|zx_keyboard_|keys[6][1]~41_combout & ((\ula_|zx_keyboard_|keys[6][1]~39_combout & ((!\ula_|zx_keyboard_|keys[6][1]~38_combout ))) # (!\ula_|zx_keyboard_|keys[6][1]~39_combout & +// (\ula_|zx_keyboard_|keys[6][1]~q )))) # (!\ula_|zx_keyboard_|keys[6][1]~41_combout & (((\ula_|zx_keyboard_|keys[6][1]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[6][1]~41_combout ), + .datab(\ula_|zx_keyboard_|keys[6][1]~39_combout ), + .datac(\ula_|zx_keyboard_|keys[6][1]~q ), + .datad(\ula_|zx_keyboard_|keys[6][1]~38_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][1]~42_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1]~42 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[6][1]~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y9_N23 +dffeas \ula_|zx_keyboard_|keys[6][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[6][1]~42_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[6][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[6][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~4 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~4_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [2])) # (!\ula_|ps2_keyboard_|shiftreg [1] & +// (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [2])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~4_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~4 .lut_mask = 16'h0402; +defparam \ula_|zx_keyboard_|WideOr16~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~2 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~2_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [1])) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~2 .lut_mask = 16'h000C; +defparam \ula_|zx_keyboard_|WideOr16~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~7 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~7_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|WideOr16~4_combout )) # (!\ula_|ps2_keyboard_|shiftreg [6] & (((\ula_|zx_keyboard_|WideOr16~2_combout & !\ula_|ps2_keyboard_|shiftreg [2])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|zx_keyboard_|WideOr16~4_combout ), + .datac(\ula_|zx_keyboard_|WideOr16~2_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~7_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~7 .lut_mask = 16'h88D8; +defparam \ula_|zx_keyboard_|WideOr16~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~5 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~5_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [1] & ((!\ula_|ps2_keyboard_|shiftreg [2])))) # (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & +// ((\ula_|ps2_keyboard_|shiftreg [1]) # (\ula_|ps2_keyboard_|shiftreg [2])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~5_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~5 .lut_mask = 16'h3064; +defparam \ula_|zx_keyboard_|WideOr16~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~6 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~6_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|zx_keyboard_|WideOr16~7_combout )) # (!\ula_|ps2_keyboard_|shiftreg [4] & (((\ula_|ps2_keyboard_|shiftreg [6] & \ula_|zx_keyboard_|WideOr16~5_combout )))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|zx_keyboard_|WideOr16~7_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(\ula_|zx_keyboard_|WideOr16~5_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~6_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~6 .lut_mask = 16'hD888; +defparam \ula_|zx_keyboard_|WideOr16~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~43 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][1]~43_combout = (!\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [7] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|scan_code_ready~q ))) + + .dataa(\ula_|zx_keyboard_|extended~q ), + .datab(\ula_|ps2_keyboard_|shiftreg [7]), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|ps2_keyboard_|scan_code_ready~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][1]~43_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][1]~43 .lut_mask = 16'h0100; +defparam \ula_|zx_keyboard_|keys[7][1]~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~44 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][1]~44_combout = (\ula_|zx_keyboard_|WideOr16~6_combout & ((\ula_|zx_keyboard_|keys[7][1]~43_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[7][1]~43_combout & (\ula_|zx_keyboard_|keys[7][1]~q )))) +// # (!\ula_|zx_keyboard_|WideOr16~6_combout & (((\ula_|zx_keyboard_|keys[7][1]~q )))) + + .dataa(\ula_|zx_keyboard_|WideOr16~6_combout ), + .datab(\ula_|zx_keyboard_|keys[7][1]~43_combout ), + .datac(\ula_|zx_keyboard_|keys[7][1]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][1]~44_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][1]~44 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[7][1]~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y10_N25 +dffeas \ula_|zx_keyboard_|keys[7][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[7][1]~44_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[7][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[7][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N10 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[15]~15 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[15]~15_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address[15]~1_combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [15])) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|abusz [15]), + .datac(gnd), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|address[15]~1_combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[15]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[15]~15 .lut_mask = 16'hEE44; +defparam \z80_|address_pins_|DFFE_apin_latch[15]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y13_N11 +dffeas \z80_|address_pins_|DFFE_apin_latch[15] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[15]~15_combout ), + .asdata(\z80_|address_latch_|Q [15]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [15]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[15] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N8 +cycloneive_lcell_comb \z80_|address_pins_|abus[15]~22 ( +// Equation(s): +// \z80_|address_pins_|abus[15]~22_combout = (\z80_|address_pins_|DFFE_apin_latch [15]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [15]), + .cin(gnd), + .combout(\z80_|address_pins_|abus[15]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[15]~22 .lut_mask = 16'hFF0F; +defparam \z80_|address_pins_|abus[15]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N16 +cycloneive_lcell_comb \D[1]~29 ( +// Equation(s): +// \D[1]~29_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\z80_|address_pins_|abus[15]~22_combout ) # (!\ula_|zx_keyboard_|keys[7][1]~q )))) # (!\z80_|address_pins_|abus[14]~23_combout & (!\ula_|zx_keyboard_|keys[6][1]~q & +// ((\z80_|address_pins_|abus[15]~22_combout ) # (!\ula_|zx_keyboard_|keys[7][1]~q )))) + + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\ula_|zx_keyboard_|keys[6][1]~q ), + .datac(\ula_|zx_keyboard_|keys[7][1]~q ), + .datad(\z80_|address_pins_|abus[15]~22_combout ), + .cin(gnd), + .combout(\D[1]~29_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~29 .lut_mask = 16'hBB0B; +defparam \D[1]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N26 +cycloneive_lcell_comb \D[1]~30 ( +// Equation(s): +// \D[1]~30_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[1]~27_combout & (\D[1]~28_combout & \D[1]~29_combout ))) + + .dataa(\D[1]~27_combout ), + .datab(\D[1]~28_combout ), + .datac(\z80_|address_pins_|abus[0]~16_combout ), + .datad(\D[1]~29_combout ), + .cin(gnd), + .combout(\D[1]~30_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~30 .lut_mask = 16'hF8F0; +defparam \D[1]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N20 +cycloneive_lcell_comb \ExtRamWE~0 ( +// Equation(s): +// \ExtRamWE~0_combout = (!\z80_|memory_ifc_|nIORQ_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (!\z80_|memory_ifc_|nRD_out~2_combout & \z80_|memory_ifc_|nWR_out~0_combout ))) + + .dataa(\z80_|memory_ifc_|nIORQ_out~0_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|memory_ifc_|nRD_out~2_combout ), + .datad(\z80_|memory_ifc_|nWR_out~0_combout ), + .cin(gnd), + .combout(\ExtRamWE~0_combout ), + .cout()); +// synopsys translate_off +defparam \ExtRamWE~0 .lut_mask = 16'h0400; +defparam \ExtRamWE~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N0 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2] = (!\z80_|address_pins_|abus[14]~23_combout & (\ExtRamWE~0_combout & (\z80_|address_pins_|abus[15]~22_combout & \z80_|address_pins_|abus[13]~20_combout ))) + + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\ExtRamWE~0_combout ), + .datac(\z80_|address_pins_|abus[15]~22_combout ), + .datad(\z80_|address_pins_|abus[13]~20_combout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] .lut_mask = 16'h4000; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N10 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout = (!\z80_|address_pins_|DFFE_apin_latch [14] & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \z80_|address_pins_|DFFE_apin_latch [13])) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [14]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [13]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 .lut_mask = 16'h3000; +defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N6 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[1]~1 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[1]~1_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [1])) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|abusz [1]), + .datac(gnd), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[1]~1 .lut_mask = 16'hEE44; +defparam \z80_|address_pins_|DFFE_apin_latch[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y11_N7 +dffeas \z80_|address_pins_|DFFE_apin_latch[1] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[1]~1_combout ), + .asdata(\z80_|address_latch_|Q [1]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[1] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N10 +cycloneive_lcell_comb \z80_|address_pins_|abus[1]~25 ( +// Equation(s): +// \z80_|address_pins_|abus[1]~25_combout = (\z80_|address_pins_|DFFE_apin_latch [1]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [1]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_pins_|abus[1]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[1]~25 .lut_mask = 16'hCFCF; +defparam \z80_|address_pins_|abus[1]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N12 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[2]~2 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[2]~2_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [2]))) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [2]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[2]~2 .lut_mask = 16'hDD88; +defparam \z80_|address_pins_|DFFE_apin_latch[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y11_N13 +dffeas \z80_|address_pins_|DFFE_apin_latch[2] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[2]~2_combout ), + .asdata(\z80_|address_latch_|Q [2]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[2] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N16 +cycloneive_lcell_comb \z80_|address_pins_|abus[2]~26 ( +// Equation(s): +// \z80_|address_pins_|abus[2]~26_combout = (\z80_|address_pins_|DFFE_apin_latch [2]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [2]), + .cin(gnd), + .combout(\z80_|address_pins_|abus[2]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[2]~26 .lut_mask = 16'hFF0F; +defparam \z80_|address_pins_|abus[2]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N28 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[3]~3 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[3]~3_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [3])) + + .dataa(\z80_|address_latch_|abusz [3]), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_apin_mux~2_combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[3]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[3]~3 .lut_mask = 16'hCCAA; +defparam \z80_|address_pins_|DFFE_apin_latch[3]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y11_N29 +dffeas \z80_|address_pins_|DFFE_apin_latch[3] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[3]~3_combout ), + .asdata(\z80_|address_latch_|Q [3]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[3] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N0 +cycloneive_lcell_comb \z80_|address_pins_|abus[3]~27 ( +// Equation(s): +// \z80_|address_pins_|abus[3]~27_combout = (\z80_|address_pins_|DFFE_apin_latch [3]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [3]), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_pins_|abus[3]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[3]~27 .lut_mask = 16'hAFAF; +defparam \z80_|address_pins_|abus[3]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N16 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[4]~4 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[4]~4_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [4]))) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [4]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[4]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[4]~4 .lut_mask = 16'hDD88; +defparam \z80_|address_pins_|DFFE_apin_latch[4]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y10_N17 +dffeas \z80_|address_pins_|DFFE_apin_latch[4] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[4]~4_combout ), + .asdata(\z80_|address_latch_|Q [4]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[4] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N6 +cycloneive_lcell_comb \z80_|address_pins_|abus[4]~28 ( +// Equation(s): +// \z80_|address_pins_|abus[4]~28_combout = (\z80_|address_pins_|DFFE_apin_latch [4]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [4]), + .cin(gnd), + .combout(\z80_|address_pins_|abus[4]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[4]~28 .lut_mask = 16'hFF0F; +defparam \z80_|address_pins_|abus[4]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N18 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[5]~5 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[5]~5_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [5]))) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [5]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[5]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[5]~5 .lut_mask = 16'hDD88; +defparam \z80_|address_pins_|DFFE_apin_latch[5]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y10_N19 +dffeas \z80_|address_pins_|DFFE_apin_latch[5] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[5]~5_combout ), + .asdata(\z80_|address_latch_|Q [5]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[5] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N30 +cycloneive_lcell_comb \z80_|address_pins_|abus[5]~29 ( +// Equation(s): +// \z80_|address_pins_|abus[5]~29_combout = (\z80_|address_pins_|DFFE_apin_latch [5]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [5]), + .cin(gnd), + .combout(\z80_|address_pins_|abus[5]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[5]~29 .lut_mask = 16'hFF0F; +defparam \z80_|address_pins_|abus[5]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N14 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[6]~6 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[6]~6_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|address [6])) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [6]))) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [6]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[6]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[6]~6 .lut_mask = 16'hDD88; +defparam \z80_|address_pins_|DFFE_apin_latch[6]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y10_N15 +dffeas \z80_|address_pins_|DFFE_apin_latch[6] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[6]~6_combout ), + .asdata(\z80_|address_latch_|Q [6]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[6] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N26 +cycloneive_lcell_comb \z80_|address_pins_|abus[6]~30 ( +// Equation(s): +// \z80_|address_pins_|abus[6]~30_combout = (\z80_|address_pins_|DFFE_apin_latch [6]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [6]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_pins_|abus[6]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[6]~30 .lut_mask = 16'hCFCF; +defparam \z80_|address_pins_|abus[6]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N20 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[7]~7 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[7]~7_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [7])) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|abusz [7]), + .datac(gnd), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[7]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[7]~7 .lut_mask = 16'hEE44; +defparam \z80_|address_pins_|DFFE_apin_latch[7]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y13_N21 +dffeas \z80_|address_pins_|DFFE_apin_latch[7] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[7]~7_combout ), + .asdata(\z80_|address_latch_|Q [7]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[7] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N24 +cycloneive_lcell_comb \z80_|address_pins_|abus[7]~31 ( +// Equation(s): +// \z80_|address_pins_|abus[7]~31_combout = (\z80_|address_pins_|DFFE_apin_latch [7]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_pins_|DFFE_apin_latch [7]), + .cin(gnd), + .combout(\z80_|address_pins_|abus[7]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[7]~31 .lut_mask = 16'hFF55; +defparam \z80_|address_pins_|abus[7]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N0 +cycloneive_lcell_comb \z80_|address_pins_|abus[10]~24 ( +// Equation(s): +// \z80_|address_pins_|abus[10]~24_combout = (\z80_|address_pins_|DFFE_apin_latch [10]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_pins_|DFFE_apin_latch [10]), + .cin(gnd), + .combout(\z80_|address_pins_|abus[10]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[10]~24 .lut_mask = 16'hFF55; +defparam \z80_|address_pins_|abus[10]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y12_N0 cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a9 ( .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), .portare(vcc), @@ -41359,7 +39084,7 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a9 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[1]~34_combout }), + .portadatain({\D[1]~32_combout }), .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , \z80_|address_pins_|abus[0]~16_combout }), @@ -41400,26 +39125,187 @@ defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 204 defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: LCCOMB_X32_Y14_N28 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0 ( +// Location: LCCOMB_X29_Y11_N4 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] ( // Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout )))) +// \ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2] = (!\z80_|address_pins_|abus[14]~23_combout & (\ExtRamWE~0_combout & (\z80_|address_pins_|abus[15]~22_combout & !\z80_|address_pins_|abus[13]~20_combout ))) - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ), + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\ExtRamWE~0_combout ), + .datac(\z80_|address_pins_|abus[15]~22_combout ), + .datad(\z80_|address_pins_|abus[13]~20_combout ), .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout ), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), .cout()); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0 .lut_mask = 16'hDC98; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0 .sum_lutc_input = "datac"; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] .lut_mask = 16'h0040; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X33_Y19_N0 +// Location: LCCOMB_X23_Y10_N0 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout = (!\z80_|address_pins_|DFFE_apin_latch [14] & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|address_pins_|DFFE_apin_latch [13])) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [14]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [13]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 .lut_mask = 16'h0030; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y10_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a1 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[1]~32_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N22 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout = \z80_|address_pins_|abus[13]~20_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_pins_|abus[13]~20_combout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder .lut_mask = 16'hFF00; +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y10_N23 +dffeas \ram1|altsyncram_component|auto_generated|address_reg_a[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram1|altsyncram_component|auto_generated|address_reg_a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true"; +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X23_Y10_N7 +dffeas \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ram1|altsyncram_component|auto_generated|address_reg_a [0]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true"; +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N24 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2] = (\z80_|address_pins_|abus[14]~23_combout & (\ExtRamWE~0_combout & (\z80_|address_pins_|abus[15]~22_combout & !\z80_|address_pins_|abus[13]~20_combout ))) + + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\ExtRamWE~0_combout ), + .datac(\z80_|address_pins_|abus[15]~22_combout ), + .datad(\z80_|address_pins_|abus[13]~20_combout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] .lut_mask = 16'h0080; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y10_N12 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout = (!\z80_|address_pins_|DFFE_apin_latch [13] & (\z80_|address_pins_|DFFE_apin_latch [14] & \z80_|resets_|SYNTHESIZED_WIRE_12~q )) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [13]), + .datac(\z80_|address_pins_|DFFE_apin_latch [14]), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 .lut_mask = 16'h3000; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y8_N0 cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a17 ( .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), .portare(vcc), @@ -41435,7 +39321,7 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a17 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[1]~34_combout }), + .portadatain({\D[1]~32_combout }), .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , \z80_|address_pins_|abus[0]~16_combout }), @@ -41476,7 +39362,98 @@ defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init1 = 20 defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: M9K_X33_Y20_N0 +// Location: FF_X23_Y14_N5 +dffeas \ram1|altsyncram_component|auto_generated|address_reg_a[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|address_pins_|abus[14]~23_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram1|altsyncram_component|auto_generated|address_reg_a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1] .is_wysiwyg = "true"; +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X23_Y14_N27 +dffeas \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ram1|altsyncram_component|auto_generated|address_reg_a [1]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] .is_wysiwyg = "true"; +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N8 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0 .lut_mask = 16'hFC22; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N18 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2] = (\z80_|address_pins_|abus[14]~23_combout & (\ExtRamWE~0_combout & (\z80_|address_pins_|abus[15]~22_combout & \z80_|address_pins_|abus[13]~20_combout ))) + + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\ExtRamWE~0_combout ), + .datac(\z80_|address_pins_|abus[15]~22_combout ), + .datad(\z80_|address_pins_|abus[13]~20_combout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] .lut_mask = 16'h8000; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y10_N30 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout = ((\z80_|address_pins_|DFFE_apin_latch [13] & \z80_|address_pins_|DFFE_apin_latch [14])) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [13]), + .datac(\z80_|address_pins_|DFFE_apin_latch [14]), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 .lut_mask = 16'hC0FF; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y7_N0 cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a25 ( .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), .portare(vcc), @@ -41492,7 +39469,7 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a25 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[1]~34_combout }), + .portadatain({\D[1]~32_combout }), .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , \z80_|address_pins_|abus[0]~16_combout }), @@ -41533,28 +39510,875 @@ defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init1 = 20 defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: LCCOMB_X32_Y14_N16 +// Location: LCCOMB_X31_Y10_N6 cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1 ( // Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout & -// ((\ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout )))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout )) +// \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout = (\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout & (((\ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout & +// (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]))) - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ), .datab(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout ), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), .datad(\ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ), .cin(gnd), .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ), .cout()); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1 .lut_mask = 16'hEC64; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1 .lut_mask = 16'hEC2C; defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X33_Y24_N0 +// Location: M9K_X33_Y2_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a1 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h35C65240B61076066A23CE4CFC5E76063A1C2AE07DF555007338BDC080EA0C23082C891C76A4845096304A0D8502080C1198911998821D09C29CA830C337499236E0548D65FF9125A765F0220F6EB9D1B318244CC6CA2CBC9CEC6979C14EB28DE2E0440C6CBD61341FC178649A852D4A2A0627C688D905B882524E191E7951EAEF30312A73337CBAD4838F42A3293859CD169240D8E652F6D72D8D19D56DD7675939FC47C933E1B0AEF12A484454C247B00A6BEC5402AA08B5106E3065602454C80CEC08A7F5F85CE65326632B4C4F3920019A35AE2AEB321131046EE45B81D4EFD5995634050D4CFEC166B032B6415553AF0358304080D9DD0A2E5948593830; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h376E511217E00B624A46BA2E4CC10B729C326F710F24CFE78C5E63F3024B17CC5E1380C938A0A16C9B696272DE7A2948BE8AFE81310146B8AAE5E549FA27EFBE27929938B8E10530250877A4998D0DF0004852125C20CA8D4279881E41208B14198817644F293AC1946061117122A39D8841818C1389D51BDAC549181902516571163594CEC5863F0F56625E221D6B8180848C6B2BE24AA0AEEE5D187201CAAE6AA394A8644314895565192AE415630A42894D6EF21343903B348EED8642F2310644C9567C0BF9911B870B989C59330089AA4C8065AB1B11132213EE0FD830817DE6C2ED45D76325CA2A8E198859334553AB02945CAB1F17C142288008073004; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h20721F982534A8179F13E2C6328CDE7D2A73087D3A9314419022103DFF7677769FE2D1F27443253D58403577C801AE23371F00290A17E1C4A40258BFD204230EE9969472A81B83113144528F831AA6C3221E137C1E9C670E26809A894013828D9E2DBCBF62498A769893D7218899245CD18AE49F0146517422EE475D520029ED39BCEF6BF4D23532957455F1C80115524179D59C4C4534DF7296991146CE24508366123AA809AB30B47977571C5D70397A93C723106D0A2C254714359DC7C9E13AE624C94932927924D20024CD638A05C8620023319662D80E05805625BC4A4006C78011F78D8B82E59F0CD4B32D6801669BE3EB0B96960DFF152005EC7C16CB; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h9C8CA06AA05B63C89A59A3E4E80807B27A70B0006624C4AC4A0595CCD8CA20824CA272352720BCD900A6D79BFD9D0595EC0D044ABC8CC28E9AE946E3D2000A4EFA4F91915C6AC9D8570C292F10848189906127BCBE06FFE92DAFB4AAFB240D88DDBB7B207EFA1709B05E1C4801BD45625A36BB62220506E171891964A31BED2215408676F600F490FAA59B488C7998CC8CCC28922AC62644EEBB432EEECB51B16CDEE7468681D6C31E4991CA3736E9ACB7531EC6D8BBCD453718101EA25D79278C6AC955A8A6140421573E413CF5A80AA1436D8B4C31A2AB26D2A61CE834248BAD5751BD429B4F61318427560CE39D49299002165212181064E24FF0093B997B; +// synopsys translate_on + +// Location: M9K_X22_Y2_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a9 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h420000004200000000000000000080000000000000000000000000000030004480000000424202423E1E3E02304C3C0C3C7E7E40403E427E3402421824347C1C0400280000003C3406303220344C403C0400100010100000005062742400000091991809FB3BD9084A1241F5015988B3C506031934089E0E1FA8043DDAF2CC07D94A6F2B1D133C211222B22C787D430E45D4C53282288077DFC0F704AAD55127A2BEAEA114958D2817AB1213183A4E1A15E3690A08A33B429284A202011A1243D49CACA1C0A441405A720D21A0921294045F746229E287B95E956AA3DE0CA3B7A019C8039C4DDA6BC99371248CC6008A54CB84503442C4F91309238ECB252072; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h81F3167814687CBD683E54D44555E6C95B5F2A72C0C193C6110C0221A448D0C9A0D8E36A84D5C61285128845215F8F8821C308E368283D8E2B42989C04A8B51354E09A38775020189010680840800297C31282442326D008D1F2351A89FFD7C16087F8B130F04418C0A1C082FC005843F5B42CADD9455ADBD328C13219110DE100D988737BBB44C414210118C673B0C1BDF76C499226F78FF41A0AF7AFD3308AAA0AAA22B1C70003F542A66FD1F1CF9D4578315F8C1C6FEC3EDB9B322CB204821A94A248414CE030020F207BF040A06A3DF993DEA3823423F405294A52014565100E0A7211342DF02958046899EEBE6E491299A09312778193FEBD7FFABA8000; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h2C05EF54A3C0F7F5F017E03F5800377CCF6E493C84E8F56441831087370A084801DEC1A54696B9912E8B0705C8587D4F7D36C8638947A620554CC77819B55B7A12D552A8A0496EFE3AAC6F34739A94E798101823148D811212E9A349CC219049527CCD419525AD29AB7D372C0B56AA0A065F8BDC905346478059EC82801920687FF29C990C9E66273CC78041192D03081CC62A8A0D8CB4D9CF2F2558131A78B8A807C3A1110211AFCA2A142F0BA928156D142250438143D339E4E2079F298493C08C4847914664518E27EF7EB9C870A226AFC35BEDB651840466400D4B3C0F877740114D6B08228BCC693FB12CECCCD2461586069445ACFC910B1241434622B6; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h5FFE6AD3343986C4103935236B6E6E11B940EF46A8FC06E6872A6929D50DCDB75621E625522D34519BF2C353F8AA030B9109C2F9686AD3AF57AF3016D9160354C0BED5FBD379F904A41BAFB6BE4EE9F208058229DD0C354F034A6C4D8B6C16A29F0120108829220B230F44550832C1022530CC13C4C30D8254ECA5200A1941266EE48A1CA6430860DE613153615CAF4C8D191004CE9C6105D8C6795B6484467D21D9DC46029B8376E97F2C7BF8C3A218EE79DDBCF886B2BBDE702F71B38AEC6914E5DCCAFE50CC13922A5B149C598A621F80C24D215291228844E7F33F9763C6639303AE5376F664C7125632C1A280CECD5740C77849D937472B202579964F60; +// synopsys translate_on + +// Location: CLKCTRL_G15 +cycloneive_clkctrl \CLOCK_50~inputclkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\CLOCK_50~input_o }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\CLOCK_50~inputclkctrl_outclk )); +// synopsys translate_off +defparam \CLOCK_50~inputclkctrl .clock_type = "global clock"; +defparam \CLOCK_50~inputclkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N4 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout = \z80_|address_pins_|abus[13]~20_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_pins_|abus[13]~20_combout ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder .lut_mask = 16'hFF00; +defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y10_N5 +dffeas \ram0|altsyncram_component|auto_generated|address_reg_a[0] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram0|altsyncram_component|auto_generated|address_reg_a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true"; +defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X23_Y10_N15 +dffeas \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(gnd), + .asdata(\ram0|altsyncram_component|auto_generated|address_reg_a [0]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true"; +defparam \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N14 +cycloneive_lcell_comb \Selector3~0 ( +// Equation(s): +// \Selector3~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [14] & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))) # (!\z80_|address_pins_|DFFE_apin_latch [14] & +// (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0])))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\z80_|address_pins_|DFFE_apin_latch [14]), + .cin(gnd), + .combout(\Selector3~0_combout ), + .cout()); +// synopsys translate_off +defparam \Selector3~0 .lut_mask = 16'hF0B8; +defparam \Selector3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N22 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout = (\z80_|address_pins_|abus[14]~23_combout & (\ExtRamWE~0_combout & (!\z80_|address_pins_|abus[15]~22_combout & \z80_|address_pins_|abus[13]~20_combout ))) + + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\ExtRamWE~0_combout ), + .datac(\z80_|address_pins_|abus[15]~22_combout ), + .datad(\z80_|address_pins_|abus[13]~20_combout ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0 .lut_mask = 16'h0800; +defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y31_N14 +cycloneive_lcell_comb \~GND ( +// Equation(s): +// \~GND~combout = GND + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\~GND~combout ), + .cout()); +// synopsys translate_off +defparam \~GND .lut_mask = 16'h0000; +defparam \~GND .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y30_N24 +cycloneive_lcell_comb \ula_|video_|vram_address[0]~feeder ( +// Equation(s): +// \ula_|video_|vram_address[0]~feeder_combout = \ula_|video_|vga_hc [4] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|vga_hc [4]), + .cin(gnd), + .combout(\ula_|video_|vram_address[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address[0]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|vram_address[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y31_N26 +cycloneive_lcell_comb \ula_|video_|vram_address~0 ( +// Equation(s): +// \ula_|video_|vram_address~0_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [1] $ (\ula_|video_|vga_hc [2])))) + + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|vga_hc [3]), + .datac(\ula_|video_|vga_hc [2]), + .datad(\ula_|video_|vga_hc [0]), + .cin(gnd), + .combout(\ula_|video_|vram_address~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address~0 .lut_mask = 16'h0048; +defparam \ula_|video_|vram_address~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y30_N25 +dffeas \ula_|video_|vram_address[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vram_address[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[0] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y30_N22 +cycloneive_lcell_comb \ula_|video_|vram_address[1]~feeder ( +// Equation(s): +// \ula_|video_|vram_address[1]~feeder_combout = \ula_|video_|vga_hc [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|vga_hc [5]), + .cin(gnd), + .combout(\ula_|video_|vram_address[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address[1]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|vram_address[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y30_N23 +dffeas \ula_|video_|vram_address[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vram_address[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[1] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y30_N20 +cycloneive_lcell_comb \ula_|video_|vram_address[2]~4 ( +// Equation(s): +// \ula_|video_|vram_address[2]~4_combout = !\ula_|video_|vga_hc [6] + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|video_|vga_hc [6]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|video_|vram_address[2]~4_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address[2]~4 .lut_mask = 16'h0F0F; +defparam \ula_|video_|vram_address[2]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y30_N21 +dffeas \ula_|video_|vram_address[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vram_address[2]~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[2] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y30_N30 +cycloneive_lcell_comb \ula_|video_|Add3~0 ( +// Equation(s): +// \ula_|video_|Add3~0_combout = \ula_|video_|vga_hc [6] $ (\ula_|video_|vga_hc [7]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|video_|vga_hc [6]), + .datad(\ula_|video_|vga_hc [7]), + .cin(gnd), + .combout(\ula_|video_|Add3~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Add3~0 .lut_mask = 16'h0FF0; +defparam \ula_|video_|Add3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y30_N31 +dffeas \ula_|video_|vram_address[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Add3~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[3] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y30_N16 +cycloneive_lcell_comb \ula_|video_|Add3~1 ( +// Equation(s): +// \ula_|video_|Add3~1_combout = \ula_|video_|vga_hc [8] $ (((!\ula_|video_|vga_hc [7]) # (!\ula_|video_|vga_hc [6]))) + + .dataa(\ula_|video_|vga_hc [8]), + .datab(gnd), + .datac(\ula_|video_|vga_hc [6]), + .datad(\ula_|video_|vga_hc [7]), + .cin(gnd), + .combout(\ula_|video_|Add3~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Add3~1 .lut_mask = 16'hA555; +defparam \ula_|video_|Add3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y30_N17 +dffeas \ula_|video_|vram_address[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Add3~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[4] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y30_N10 +cycloneive_lcell_comb \ula_|video_|Add4~0 ( +// Equation(s): +// \ula_|video_|Add4~0_combout = (\ula_|video_|vga_vc [0] & (\ula_|video_|vga_vc [1] $ (VCC))) # (!\ula_|video_|vga_vc [0] & (\ula_|video_|vga_vc [1] & VCC)) +// \ula_|video_|Add4~1 = CARRY((\ula_|video_|vga_vc [0] & \ula_|video_|vga_vc [1])) + + .dataa(\ula_|video_|vga_vc [0]), + .datab(\ula_|video_|vga_vc [1]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\ula_|video_|Add4~0_combout ), + .cout(\ula_|video_|Add4~1 )); +// synopsys translate_off +defparam \ula_|video_|Add4~0 .lut_mask = 16'h6688; +defparam \ula_|video_|Add4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y30_N12 +cycloneive_lcell_comb \ula_|video_|Add4~2 ( +// Equation(s): +// \ula_|video_|Add4~2_combout = (\ula_|video_|vga_vc [2] & (\ula_|video_|Add4~1 & VCC)) # (!\ula_|video_|vga_vc [2] & (!\ula_|video_|Add4~1 )) +// \ula_|video_|Add4~3 = CARRY((!\ula_|video_|vga_vc [2] & !\ula_|video_|Add4~1 )) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [2]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~1 ), + .combout(\ula_|video_|Add4~2_combout ), + .cout(\ula_|video_|Add4~3 )); +// synopsys translate_off +defparam \ula_|video_|Add4~2 .lut_mask = 16'hC303; +defparam \ula_|video_|Add4~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y30_N14 +cycloneive_lcell_comb \ula_|video_|Add4~4 ( +// Equation(s): +// \ula_|video_|Add4~4_combout = (\ula_|video_|vga_vc [3] & ((GND) # (!\ula_|video_|Add4~3 ))) # (!\ula_|video_|vga_vc [3] & (\ula_|video_|Add4~3 $ (GND))) +// \ula_|video_|Add4~5 = CARRY((\ula_|video_|vga_vc [3]) # (!\ula_|video_|Add4~3 )) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [3]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~3 ), + .combout(\ula_|video_|Add4~4_combout ), + .cout(\ula_|video_|Add4~5 )); +// synopsys translate_off +defparam \ula_|video_|Add4~4 .lut_mask = 16'h3CCF; +defparam \ula_|video_|Add4~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y30_N16 +cycloneive_lcell_comb \ula_|video_|Add4~6 ( +// Equation(s): +// \ula_|video_|Add4~6_combout = (\ula_|video_|vga_vc [4] & (!\ula_|video_|Add4~5 )) # (!\ula_|video_|vga_vc [4] & ((\ula_|video_|Add4~5 ) # (GND))) +// \ula_|video_|Add4~7 = CARRY((!\ula_|video_|Add4~5 ) # (!\ula_|video_|vga_vc [4])) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [4]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~5 ), + .combout(\ula_|video_|Add4~6_combout ), + .cout(\ula_|video_|Add4~7 )); +// synopsys translate_off +defparam \ula_|video_|Add4~6 .lut_mask = 16'h3C3F; +defparam \ula_|video_|Add4~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X35_Y30_N17 +dffeas \ula_|video_|vram_address[5] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Add4~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[5] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y30_N18 +cycloneive_lcell_comb \ula_|video_|Add4~8 ( +// Equation(s): +// \ula_|video_|Add4~8_combout = (\ula_|video_|vga_vc [5] & ((GND) # (!\ula_|video_|Add4~7 ))) # (!\ula_|video_|vga_vc [5] & (\ula_|video_|Add4~7 $ (GND))) +// \ula_|video_|Add4~9 = CARRY((\ula_|video_|vga_vc [5]) # (!\ula_|video_|Add4~7 )) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [5]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~7 ), + .combout(\ula_|video_|Add4~8_combout ), + .cout(\ula_|video_|Add4~9 )); +// synopsys translate_off +defparam \ula_|video_|Add4~8 .lut_mask = 16'h3CCF; +defparam \ula_|video_|Add4~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X35_Y30_N19 +dffeas \ula_|video_|vram_address[6] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Add4~8_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[6] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y30_N20 +cycloneive_lcell_comb \ula_|video_|Add4~10 ( +// Equation(s): +// \ula_|video_|Add4~10_combout = (\ula_|video_|vga_vc [6] & (!\ula_|video_|Add4~9 )) # (!\ula_|video_|vga_vc [6] & ((\ula_|video_|Add4~9 ) # (GND))) +// \ula_|video_|Add4~11 = CARRY((!\ula_|video_|Add4~9 ) # (!\ula_|video_|vga_vc [6])) + + .dataa(\ula_|video_|vga_vc [6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~9 ), + .combout(\ula_|video_|Add4~10_combout ), + .cout(\ula_|video_|Add4~11 )); +// synopsys translate_off +defparam \ula_|video_|Add4~10 .lut_mask = 16'h5A5F; +defparam \ula_|video_|Add4~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X35_Y30_N21 +dffeas \ula_|video_|vram_address[7] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Add4~10_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[7] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y30_N22 +cycloneive_lcell_comb \ula_|video_|Add4~12 ( +// Equation(s): +// \ula_|video_|Add4~12_combout = (\ula_|video_|vga_vc [7] & ((GND) # (!\ula_|video_|Add4~11 ))) # (!\ula_|video_|vga_vc [7] & (\ula_|video_|Add4~11 $ (GND))) +// \ula_|video_|Add4~13 = CARRY((\ula_|video_|vga_vc [7]) # (!\ula_|video_|Add4~11 )) + + .dataa(\ula_|video_|vga_vc [7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~11 ), + .combout(\ula_|video_|Add4~12_combout ), + .cout(\ula_|video_|Add4~13 )); +// synopsys translate_off +defparam \ula_|video_|Add4~12 .lut_mask = 16'h5AAF; +defparam \ula_|video_|Add4~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y30_N26 +cycloneive_lcell_comb \ula_|video_|Selector6~0 ( +// Equation(s): +// \ula_|video_|Selector6~0_combout = (\ula_|video_|vga_hc [2] & ((\ula_|video_|Add4~12_combout ))) # (!\ula_|video_|vga_hc [2] & (\ula_|video_|Add4~0_combout )) + + .dataa(gnd), + .datab(\ula_|video_|vga_hc [2]), + .datac(\ula_|video_|Add4~0_combout ), + .datad(\ula_|video_|Add4~12_combout ), + .cin(gnd), + .combout(\ula_|video_|Selector6~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Selector6~0 .lut_mask = 16'hFC30; +defparam \ula_|video_|Selector6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y31_N16 +cycloneive_lcell_comb \ula_|video_|vram_address[9]~1 ( +// Equation(s): +// \ula_|video_|vram_address[9]~1_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [1] $ (\ula_|video_|vga_hc [2])))) + + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|vga_hc [3]), + .datac(\ula_|video_|vga_hc [2]), + .datad(\ula_|video_|vga_hc [0]), + .cin(gnd), + .combout(\ula_|video_|vram_address[9]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address[9]~1 .lut_mask = 16'h0048; +defparam \ula_|video_|vram_address[9]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y30_N27 +dffeas \ula_|video_|vram_address[8] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Selector6~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address[9]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [8]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[8] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y30_N24 +cycloneive_lcell_comb \ula_|video_|Add4~14 ( +// Equation(s): +// \ula_|video_|Add4~14_combout = \ula_|video_|Add4~13 $ (!\ula_|video_|vga_vc [8]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|vga_vc [8]), + .cin(\ula_|video_|Add4~13 ), + .combout(\ula_|video_|Add4~14_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Add4~14 .lut_mask = 16'hF00F; +defparam \ula_|video_|Add4~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y30_N12 +cycloneive_lcell_comb \ula_|video_|Selector5~0 ( +// Equation(s): +// \ula_|video_|Selector5~0_combout = (\ula_|video_|vga_hc [2] & ((\ula_|video_|Add4~14_combout ))) # (!\ula_|video_|vga_hc [2] & (\ula_|video_|Add4~2_combout )) + + .dataa(gnd), + .datab(\ula_|video_|vga_hc [2]), + .datac(\ula_|video_|Add4~2_combout ), + .datad(\ula_|video_|Add4~14_combout ), + .cin(gnd), + .combout(\ula_|video_|Selector5~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Selector5~0 .lut_mask = 16'hFC30; +defparam \ula_|video_|Selector5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y30_N13 +dffeas \ula_|video_|vram_address[9] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Selector5~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address[9]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [9]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[9] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y31_N6 +cycloneive_lcell_comb \ula_|video_|vram_address[10]~2 ( +// Equation(s): +// \ula_|video_|vram_address[10]~2_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [1] $ (\ula_|video_|vga_hc [2])))) + + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|vga_hc [3]), + .datac(\ula_|video_|vga_hc [2]), + .datad(\ula_|video_|vga_hc [0]), + .cin(gnd), + .combout(\ula_|video_|vram_address[10]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address[10]~2 .lut_mask = 16'h0048; +defparam \ula_|video_|vram_address[10]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y31_N28 +cycloneive_lcell_comb \ula_|video_|vram_address[10]~3 ( +// Equation(s): +// \ula_|video_|vram_address[10]~3_combout = (\ula_|video_|vram_address[10]~2_combout & (\ula_|video_|vga_hc [1] & (\ula_|video_|Add4~4_combout ))) # (!\ula_|video_|vram_address[10]~2_combout & (((\ula_|video_|vram_address [10])))) + + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|Add4~4_combout ), + .datac(\ula_|video_|vram_address [10]), + .datad(\ula_|video_|vram_address[10]~2_combout ), + .cin(gnd), + .combout(\ula_|video_|vram_address[10]~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address[10]~3 .lut_mask = 16'h88F0; +defparam \ula_|video_|vram_address[10]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y31_N29 +dffeas \ula_|video_|vram_address[10] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vram_address[10]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [10]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[10] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y30_N6 +cycloneive_lcell_comb \ula_|video_|Selector3~0 ( +// Equation(s): +// \ula_|video_|Selector3~0_combout = (\ula_|video_|vga_hc [2]) # (\ula_|video_|Add4~12_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|video_|vga_hc [2]), + .datad(\ula_|video_|Add4~12_combout ), + .cin(gnd), + .combout(\ula_|video_|Selector3~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Selector3~0 .lut_mask = 16'hFFF0; +defparam \ula_|video_|Selector3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y30_N7 +dffeas \ula_|video_|vram_address[11] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Selector3~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address[9]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [11]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[11] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y30_N8 +cycloneive_lcell_comb \ula_|video_|Selector2~0 ( +// Equation(s): +// \ula_|video_|Selector2~0_combout = (\ula_|video_|vga_hc [2]) # (\ula_|video_|Add4~14_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|video_|vga_hc [2]), + .datad(\ula_|video_|Add4~14_combout ), + .cin(gnd), + .combout(\ula_|video_|Selector2~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Selector2~0 .lut_mask = 16'hFFF0; +defparam \ula_|video_|Selector2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y30_N9 +dffeas \ula_|video_|vram_address[12] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Selector2~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address[9]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [12]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[12] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[12] .power_up = "low"; +// synopsys translate_on + +// Location: M9K_X33_Y26_N0 cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a9 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), @@ -41568,7 +40392,7 @@ cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a9 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[1]~34_combout }), + .portadatain({\D[1]~32_combout }), .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , \z80_|address_pins_|abus[0]~16_combout }), @@ -41625,125 +40449,26 @@ defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 204 defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: M9K_X33_Y32_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a9 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), - .portbdataout()); +// Location: LCCOMB_X29_Y11_N10 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout = (\z80_|address_pins_|abus[14]~23_combout & (\ExtRamWE~0_combout & (!\z80_|address_pins_|abus[15]~22_combout & !\z80_|address_pins_|abus[13]~20_combout ))) + + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\ExtRamWE~0_combout ), + .datac(\z80_|address_pins_|abus[15]~22_combout ), + .datad(\z80_|address_pins_|abus[13]~20_combout ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ), + .cout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h420000004200000000000000000080000000000000000000000000000030004480000000424202423E1E3E02304C3C0C3C7E7E40403E427E3402421824347C1C0400280000003C3406303220344C403C0400100010100000005062742400000091991809FB3BD9084A1241F5015988B3C506031934089E0E1FA8043DDAF2CC07D94A6F2B1D133C211222B22C787D430E45D4C53282288077DFC0F704AAD55127A2BEAEA114958D2817AB1213183A4E1A15E3690A08A33B429284A202011A1243D49CACA1C0A441405A720D21A0921294045F746229E287B95E956AA3DE0CA3B7A019C8039C4DDA6BC99371248CC6008A54CB84503442C4F91309238ECB252072; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h81F3167814687CBD683E54D44555E6C95B5F2A72C0C193C6110C0221A448D0C9A0D8E36A84D5C61285128845215F8F8821C308E368283D8E2B42989C04A8B51354E09A38775020189010680840800297C31282442326D008D1F2351A89FFD7C16087F8B130F04418C0A1C082FC005843F5B42CADD9455ADBD328C13219110DE100D988737BBB44C414210118C673B0C1BDF76C499226F78FF41A0AF7AFD3308AAA0AAA22B1C70003F542A66FD1F1CF9D4578315F8C1C6FEC3EDB9B322CB204821A94A248414CE030020F207BF040A06A3DF993DEA3823423F405294A52014565100E0A7211342DF02958046899EEBE6E491299A09312778193FEBD7FFABA8000; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h2C05EF54A3C0F7F5F017E03F5800377CCF6E493C84E8F56441831087370A084801DEC1A54696B9912E8B0705C8587D4F7D36C8638947A620554CC77819B55B7A12D552A8A0496EFE3AAC6F34739A94E798101823148D811212E9A349CC219049527CCD419525AD29AB7D372C0B56AA0A065F8BDC905346478059EC82801920687FF29C990C9E66273CC78041192D03081CC62A8A0D8CB4D9CF2F2558131A78B8A807C3A1110211AFCA2A142F0BA928156D142250438143D339E4E2079F298493C08C4847914664518E27EF7EB9C870A226AFC35BEDB651840466400D4B3C0F877740114D6B08228BCC693FB12CECCCD2461586069445ACFC910B1241434622B6; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h5FFE6AD3343986C4103935236B6E6E11B940EF46A8FC06E6872A6929D50DCDB75621E625522D34519BF2C353F8AA030B9109C2F9686AD3AF57AF3016D9160354C0BED5FBD379F904A41BAFB6BE4EE9F208058229DD0C354F034A6C4D8B6C16A29F0120108829220B230F44550832C1022530CC13C4C30D8254ECA5200A1941266EE48A1CA6430860DE613153615CAF4C8D191004CE9C6105D8C6795B6484467D21D9DC46029B8376E97F2C7BF8C3A218EE79DDBCF886B2BBDE702F71B38AEC6914E5DCCAFE50CC13922A5B149C598A621F80C24D215291228844E7F33F9763C6639303AE5376F664C7125632C1A280CECD5740C77849D937472B202579964F60; +defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1 .lut_mask = 16'h0008; +defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X33_Y21_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a1 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h35C65240B61076066A23CE4CFC5E76063A1C2AE07DF555007338BDC080EA0C23082C891C76A4845096304A0D8502080C1198911998821D09C29CA830C337499236E0548D65FF9125A765F0220F6EB9D1B318244CC6CA2CBC9CEC6979C14EB28DE2E0440C6CBD61341FC178649A852D4A2A0627C688D905B882524E191E7951EAEF30312A73337CBAD4838F42A3293859CD169240D8E652F6D72D8D19D56DD7675939FC47C933E1B0AEF12A484454C247B00A6BEC5402AA08B5106E3065602454C80CEC08A7F5F85CE65326632B4C4F3920019A35AE2AEB321131046EE45B81D4EFD5995634050D4CFEC166B032B6415553AF0358304080D9DD0A2E5948593830; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h376E511217E00B624A46BA2E4CC10B729C326F710F24CFE78C5E63F3024B17CC5E1380C938A0A16C9B696272DE7A2948BE8AFE81310146B8AAE5E549FA27EFBE27929938B8E10530250877A4998D0DF0004852125C20CA8D4279881E41208B14198817644F293AC1946061117122A39D8841818C1389D51BDAC549181902516571163594CEC5863F0F56625E221D6B8180848C6B2BE24AA0AEEE5D187201CAAE6AA394A8644314895565192AE415630A42894D6EF21343903B348EED8642F2310644C9567C0BF9911B870B989C59330089AA4C8065AB1B11132213EE0FD830817DE6C2ED45D76325CA2A8E198859334553AB02945CAB1F17C142288008073004; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h20721F982534A8179F13E2C6328CDE7D2A73087D3A9314419022103DFF7677769FE2D1F27443253D58403577C801AE23371F00290A17E1C4A40258BFD204230EE9969472A81B83113144528F831AA6C3221E137C1E9C670E26809A894013828D9E2DBCBF62498A769893D7218899245CD18AE49F0146517422EE475D520029ED39BCEF6BF4D23532957455F1C80115524179D59C4C4534DF7296991146CE24508366123AA809AB30B47977571C5D70397A93C723106D0A2C254714359DC7C9E13AE624C94932927924D20024CD638A05C8620023319662D80E05805625BC4A4006C78011F78D8B82E59F0CD4B32D6801669BE3EB0B96960DFF152005EC7C16CB; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h9C8CA06AA05B63C89A59A3E4E80807B27A70B0006624C4AC4A0595CCD8CA20824CA272352720BCD900A6D79BFD9D0595EC0D044ABC8CC28E9AE946E3D2000A4EFA4F91915C6AC9D8570C292F10848189906127BCBE06FFE92DAFB4AAFB240D88DDBB7B207EFA1709B05E1C4801BD45625A36BB62220506E171891964A31BED2215408676F600F490FAA59B488C7998CC8CCC28922AC62644EEBB432EEECB51B16CDEE7468681D6C31E4991CA3736E9ACB7531EC6D8BBCD453718101EA25D79278C6AC955A8A6140421573E413CF5A80AA1436D8B4C31A2AB26D2A61CE834248BAD5751BD429B4F61318427560CE39D49299002165212181064E24FF0093B997B; -// synopsys translate_on - -// Location: M9K_X33_Y22_N0 +// Location: M9K_X33_Y30_N0 cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a1 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), @@ -41757,7 +40482,7 @@ cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a1 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[1]~34_combout }), + .portadatain({\D[1]~32_combout }), .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , \z80_|address_pins_|abus[0]~16_combout }), @@ -41813,2095 +40538,104 @@ defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 204 defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'hCB9C84F288C855028DE04086AC0122869175A48288D30882FFFFFFFCC0000002CB9C80B78DD447828DE440828C0126829175840280D10B82FFFFFFFDE0408082C8D480838FD45582881C4482840160028179800280510B82C0000001BFFFFFFE8AD480BA8F844182880860828601660A8179900280510B02800000009FBF7F7C8B90A1328C8401828BE0608A86836E1281791012805107029FBF7F7D800000008B9883228C9405828BE0728286832E0281799042C0500F43BFFFFFFF80000000889081128FD400828A0066828782288281199002C0401F03A0408083FFFFFFFF888881128FE440828800268287D22CE280199022A0003F00E0408080FFFFFFFF; // synopsys translate_on -// Location: LCCOMB_X32_Y18_N0 +// Location: LCCOMB_X30_Y10_N20 cycloneive_lcell_comb \Selector1~0 ( // Equation(s): -// \Selector1~0_combout = (\z80_|address_pins_|abus[14]~23_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout )))) # (!\z80_|address_pins_|abus[14]~23_combout -// & (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ))) +// \Selector1~0_combout = (\z80_|address_pins_|abus[14]~23_combout & ((\Selector3~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout )) # (!\Selector3~0_combout & +// ((\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ))))) # (!\z80_|address_pins_|abus[14]~23_combout & (\Selector3~0_combout )) .dataa(\z80_|address_pins_|abus[14]~23_combout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ), + .datab(\Selector3~0_combout ), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout ), .datad(\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ), .cin(gnd), .combout(\Selector1~0_combout ), .cout()); // synopsys translate_off -defparam \Selector1~0 .lut_mask = 16'hBA98; +defparam \Selector1~0 .lut_mask = 16'hE6C4; defparam \Selector1~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y18_N2 +// Location: LCCOMB_X30_Y10_N22 cycloneive_lcell_comb \Selector1~1 ( // Equation(s): -// \Selector1~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Selector1~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout )) # (!\Selector1~0_combout & -// ((\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Selector1~0_combout )))) +// \Selector1~1_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\Selector1~0_combout )))) # (!\z80_|address_pins_|abus[14]~23_combout & ((\Selector1~0_combout & ((\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ))) # +// (!\Selector1~0_combout & (\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout )))) - .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ), .datac(\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ), .datad(\Selector1~0_combout ), .cin(gnd), .combout(\Selector1~1_combout ), .cout()); // synopsys translate_off -defparam \Selector1~1 .lut_mask = 16'hBBC0; +defparam \Selector1~1 .lut_mask = 16'hFA44; defparam \Selector1~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y18_N12 -cycloneive_lcell_comb \D[1]~103 ( +// Location: LCCOMB_X31_Y10_N28 +cycloneive_lcell_comb \D[1]~81 ( // Equation(s): -// \D[1]~103_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [15] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\Selector1~1_combout -// ))))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout )))) +// \D[1]~81_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\Selector1~1_combout ))) +// # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout )))) - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .dataa(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ), .datab(\z80_|address_pins_|DFFE_apin_latch [15]), - .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .datad(\Selector1~1_combout ), .cin(gnd), - .combout(\D[1]~103_combout ), + .combout(\D[1]~81_combout ), .cout()); // synopsys translate_off -defparam \D[1]~103 .lut_mask = 16'hF2D0; -defparam \D[1]~103 .sum_lutc_input = "datac"; +defparam \D[1]~81 .lut_mask = 16'hBA8A; +defparam \D[1]~81 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: IOIBUF_X18_Y34_N1 -cycloneive_io_ibuf \PS2_DAT~input ( - .i(PS2_DAT), - .ibar(gnd), - .o(\PS2_DAT~input_o )); -// synopsys translate_off -defparam \PS2_DAT~input .bus_hold = "false"; -defparam \PS2_DAT~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: CLKCTRL_G5 -cycloneive_clkctrl \reset~clkctrl ( - .ena(vcc), - .inclk({vcc,vcc,vcc,\reset~combout }), - .clkselect(2'b00), - .devclrn(devclrn), - .devpor(devpor), - .outclk(\reset~clkctrl_outclk )); -// synopsys translate_off -defparam \reset~clkctrl .clock_type = "global clock"; -defparam \reset~clkctrl .ena_register_mode = "none"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y21_N2 -cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|bit_count~0_combout = (!\ula_|ps2_keyboard_|bit_count [0] & (((!\ula_|ps2_keyboard_|bit_count [1] & !\ula_|ps2_keyboard_|bit_count [2])) # (!\ula_|ps2_keyboard_|bit_count [3]))) - - .dataa(\ula_|ps2_keyboard_|bit_count [1]), - .datab(\ula_|ps2_keyboard_|bit_count [3]), - .datac(\ula_|ps2_keyboard_|bit_count [0]), - .datad(\ula_|ps2_keyboard_|bit_count [2]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|bit_count~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count~0 .lut_mask = 16'h0307; -defparam \ula_|ps2_keyboard_|bit_count~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: IOIBUF_X9_Y34_N8 -cycloneive_io_ibuf \PS2_CLK~input ( - .i(PS2_CLK), - .ibar(gnd), - .o(\PS2_CLK~input_o )); -// synopsys translate_off -defparam \PS2_CLK~input .bus_hold = "false"; -defparam \PS2_CLK~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N0 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[7]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[7]~feeder_combout = \PS2_CLK~input_o - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\PS2_CLK~input_o ), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[7]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[7]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y26_N1 -dffeas \ula_|ps2_keyboard_|clk_filter[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[7] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N6 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[6]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[6]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [7] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [7]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[6]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[6]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y26_N7 -dffeas \ula_|ps2_keyboard_|clk_filter[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[6] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N20 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[5]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[5]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [6] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [6]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[5]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[5]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y26_N21 -dffeas \ula_|ps2_keyboard_|clk_filter[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[5] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N18 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[4]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[4]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [5] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [5]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[4]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[4]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y26_N19 -dffeas \ula_|ps2_keyboard_|clk_filter[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[4] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N12 -cycloneive_lcell_comb \ula_|ps2_keyboard_|Equal0~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|Equal0~0_combout = (!\ula_|ps2_keyboard_|clk_filter [6] & (!\ula_|ps2_keyboard_|clk_filter [7] & (!\ula_|ps2_keyboard_|clk_filter [5] & !\ula_|ps2_keyboard_|clk_filter [4]))) - - .dataa(\ula_|ps2_keyboard_|clk_filter [6]), - .datab(\ula_|ps2_keyboard_|clk_filter [7]), - .datac(\ula_|ps2_keyboard_|clk_filter [5]), - .datad(\ula_|ps2_keyboard_|clk_filter [4]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|Equal0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|Equal0~0 .lut_mask = 16'h0001; -defparam \ula_|ps2_keyboard_|Equal0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N2 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[3]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[3]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [4] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [4]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[3]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[3]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[3]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y26_N3 -dffeas \ula_|ps2_keyboard_|clk_filter[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[3]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[3] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N28 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[2]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[2]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [3] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [3]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[2]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y26_N29 -dffeas \ula_|ps2_keyboard_|clk_filter[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[2] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N22 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[1]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[1]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [2] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [2]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[1]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y26_N23 -dffeas \ula_|ps2_keyboard_|clk_filter[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[1] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N16 -cycloneive_lcell_comb \ula_|ps2_keyboard_|Equal0~1 ( -// Equation(s): -// \ula_|ps2_keyboard_|Equal0~1_combout = (\ula_|ps2_keyboard_|Equal0~0_combout & (!\ula_|ps2_keyboard_|clk_filter [2] & (!\ula_|ps2_keyboard_|clk_filter [1] & !\ula_|ps2_keyboard_|clk_filter [3]))) - - .dataa(\ula_|ps2_keyboard_|Equal0~0_combout ), - .datab(\ula_|ps2_keyboard_|clk_filter [2]), - .datac(\ula_|ps2_keyboard_|clk_filter [1]), - .datad(\ula_|ps2_keyboard_|clk_filter [3]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|Equal0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|Equal0~1 .lut_mask = 16'h0002; -defparam \ula_|ps2_keyboard_|Equal0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N10 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[0]~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[0]~0_combout = !\ula_|ps2_keyboard_|clk_filter [1] - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|clk_filter [1]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[0]~0 .lut_mask = 16'h0F0F; -defparam \ula_|ps2_keyboard_|clk_filter[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y26_N11 -dffeas \ula_|ps2_keyboard_|clk_filter[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[0]~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[0] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N26 -cycloneive_lcell_comb \ula_|ps2_keyboard_|ps2_clk_in~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|ps2_clk_in~0_combout = (\ula_|ps2_keyboard_|Equal0~1_combout & ((\ula_|ps2_keyboard_|clk_filter [0]))) # (!\ula_|ps2_keyboard_|Equal0~1_combout & (\ula_|ps2_keyboard_|ps2_clk_in~q )) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|Equal0~1_combout ), - .datac(\ula_|ps2_keyboard_|ps2_clk_in~q ), - .datad(\ula_|ps2_keyboard_|clk_filter [0]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|ps2_clk_in~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|ps2_clk_in~0 .lut_mask = 16'hFC30; -defparam \ula_|ps2_keyboard_|ps2_clk_in~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y26_N27 -dffeas \ula_|ps2_keyboard_|ps2_clk_in ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|ps2_clk_in~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|ps2_clk_in~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|ps2_clk_in .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|ps2_clk_in .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N4 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_edge~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_edge~0_combout = (\ula_|ps2_keyboard_|Equal0~1_combout & (!\ula_|ps2_keyboard_|ps2_clk_in~q & \ula_|ps2_keyboard_|clk_filter [0])) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|Equal0~1_combout ), - .datac(\ula_|ps2_keyboard_|ps2_clk_in~q ), - .datad(\ula_|ps2_keyboard_|clk_filter [0]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_edge~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_edge~0 .lut_mask = 16'h0C00; -defparam \ula_|ps2_keyboard_|clk_edge~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y26_N5 -dffeas \ula_|ps2_keyboard_|clk_edge ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_edge~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_edge~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_edge .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_edge .power_up = "low"; -// synopsys translate_on - -// Location: FF_X26_Y21_N3 -dffeas \ula_|ps2_keyboard_|bit_count[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|bit_count~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|ps2_keyboard_|clk_edge~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|bit_count [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count[0] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|bit_count[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y21_N0 -cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~1 ( -// Equation(s): -// \ula_|ps2_keyboard_|bit_count~1_combout = (!\ula_|ps2_keyboard_|bit_count [3] & (\ula_|ps2_keyboard_|bit_count [2] $ (((\ula_|ps2_keyboard_|bit_count [1] & \ula_|ps2_keyboard_|bit_count [0]))))) - - .dataa(\ula_|ps2_keyboard_|bit_count [1]), - .datab(\ula_|ps2_keyboard_|bit_count [3]), - .datac(\ula_|ps2_keyboard_|bit_count [2]), - .datad(\ula_|ps2_keyboard_|bit_count [0]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|bit_count~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count~1 .lut_mask = 16'h1230; -defparam \ula_|ps2_keyboard_|bit_count~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y21_N1 -dffeas \ula_|ps2_keyboard_|bit_count[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|bit_count~1_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|ps2_keyboard_|clk_edge~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|bit_count [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count[2] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|bit_count[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y21_N16 -cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~3 ( -// Equation(s): -// \ula_|ps2_keyboard_|bit_count~3_combout = (\ula_|ps2_keyboard_|bit_count [1] & (\ula_|ps2_keyboard_|bit_count [2] & (!\ula_|ps2_keyboard_|bit_count [3] & \ula_|ps2_keyboard_|bit_count [0]))) # (!\ula_|ps2_keyboard_|bit_count [1] & -// (!\ula_|ps2_keyboard_|bit_count [2] & (\ula_|ps2_keyboard_|bit_count [3]))) - - .dataa(\ula_|ps2_keyboard_|bit_count [1]), - .datab(\ula_|ps2_keyboard_|bit_count [2]), - .datac(\ula_|ps2_keyboard_|bit_count [3]), - .datad(\ula_|ps2_keyboard_|bit_count [0]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|bit_count~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count~3 .lut_mask = 16'h1810; -defparam \ula_|ps2_keyboard_|bit_count~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y21_N17 -dffeas \ula_|ps2_keyboard_|bit_count[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|bit_count~3_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|ps2_keyboard_|clk_edge~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|bit_count [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count[3] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|bit_count[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y21_N26 -cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~2 ( -// Equation(s): -// \ula_|ps2_keyboard_|bit_count~2_combout = (\ula_|ps2_keyboard_|bit_count [3] & (!\ula_|ps2_keyboard_|bit_count [2] & (!\ula_|ps2_keyboard_|bit_count [1] & \ula_|ps2_keyboard_|bit_count [0]))) # (!\ula_|ps2_keyboard_|bit_count [3] & -// ((\ula_|ps2_keyboard_|bit_count [1] $ (\ula_|ps2_keyboard_|bit_count [0])))) - - .dataa(\ula_|ps2_keyboard_|bit_count [3]), - .datab(\ula_|ps2_keyboard_|bit_count [2]), - .datac(\ula_|ps2_keyboard_|bit_count [1]), - .datad(\ula_|ps2_keyboard_|bit_count [0]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|bit_count~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count~2 .lut_mask = 16'h0750; -defparam \ula_|ps2_keyboard_|bit_count~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y21_N27 -dffeas \ula_|ps2_keyboard_|bit_count[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|bit_count~2_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|ps2_keyboard_|clk_edge~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|bit_count [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count[1] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|bit_count[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y21_N22 -cycloneive_lcell_comb \ula_|ps2_keyboard_|always1~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|always1~0_combout = (!\ula_|ps2_keyboard_|bit_count [1] & (!\ula_|ps2_keyboard_|bit_count [3] & (!\PS2_DAT~input_o & !\ula_|ps2_keyboard_|bit_count [2]))) - - .dataa(\ula_|ps2_keyboard_|bit_count [1]), - .datab(\ula_|ps2_keyboard_|bit_count [3]), - .datac(\PS2_DAT~input_o ), - .datad(\ula_|ps2_keyboard_|bit_count [2]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|always1~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|always1~0 .lut_mask = 16'h0001; -defparam \ula_|ps2_keyboard_|always1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y21_N12 -cycloneive_lcell_comb \ula_|ps2_keyboard_|LessThan0~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|LessThan0~0_combout = (\ula_|ps2_keyboard_|bit_count [3] & ((\ula_|ps2_keyboard_|bit_count [1]) # (\ula_|ps2_keyboard_|bit_count [2]))) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|bit_count [3]), - .datac(\ula_|ps2_keyboard_|bit_count [1]), - .datad(\ula_|ps2_keyboard_|bit_count [2]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|LessThan0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|LessThan0~0 .lut_mask = 16'hCCC0; -defparam \ula_|ps2_keyboard_|LessThan0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y21_N6 -cycloneive_lcell_comb \ula_|ps2_keyboard_|shiftreg[0]~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|shiftreg[0]~0_combout = (\ula_|ps2_keyboard_|clk_edge~q & (!\ula_|ps2_keyboard_|LessThan0~0_combout & ((\ula_|ps2_keyboard_|bit_count [0]) # (!\ula_|ps2_keyboard_|always1~0_combout )))) - - .dataa(\ula_|ps2_keyboard_|always1~0_combout ), - .datab(\ula_|ps2_keyboard_|bit_count [0]), - .datac(\ula_|ps2_keyboard_|clk_edge~q ), - .datad(\ula_|ps2_keyboard_|LessThan0~0_combout ), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[0]~0 .lut_mask = 16'h00D0; -defparam \ula_|ps2_keyboard_|shiftreg[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y21_N9 -dffeas \ula_|ps2_keyboard_|shiftreg[8] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\PS2_DAT~input_o ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [8]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[8] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[8] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y21_N15 -dffeas \ula_|ps2_keyboard_|shiftreg[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [8]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[7] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y21_N5 -dffeas \ula_|ps2_keyboard_|shiftreg[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [7]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[6] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y21_N11 -dffeas \ula_|ps2_keyboard_|shiftreg[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [6]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[5] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y21_N11 -dffeas \ula_|ps2_keyboard_|shiftreg[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [5]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[4] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y21_N25 -dffeas \ula_|ps2_keyboard_|shiftreg[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [4]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[3] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y21_N29 -dffeas \ula_|ps2_keyboard_|shiftreg[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [3]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[2] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y21_N1 -dffeas \ula_|ps2_keyboard_|shiftreg[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [2]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[1] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y21_N17 -dffeas \ula_|ps2_keyboard_|shiftreg[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [1]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[0] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~0 ( -// Equation(s): -// \ula_|zx_keyboard_|Equal0~0_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [7] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [5]), - .datab(\ula_|ps2_keyboard_|shiftreg [7]), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|Equal0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|Equal0~0 .lut_mask = 16'h0008; -defparam \ula_|zx_keyboard_|Equal0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~1 ( -// Equation(s): -// \ula_|zx_keyboard_|Equal0~1_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|Equal0~0_combout & !\ula_|ps2_keyboard_|shiftreg [1]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|zx_keyboard_|Equal0~0_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|Equal0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|Equal0~1 .lut_mask = 16'h0020; -defparam \ula_|zx_keyboard_|Equal0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|extended~0 ( -// Equation(s): -// \ula_|zx_keyboard_|extended~0_combout = (\ula_|zx_keyboard_|Equal0~1_combout & ((\ula_|zx_keyboard_|extended~q ) # (!\ula_|ps2_keyboard_|shiftreg [4]))) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [4]), - .datac(\ula_|zx_keyboard_|extended~q ), - .datad(\ula_|zx_keyboard_|Equal0~1_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|extended~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|extended~0 .lut_mask = 16'hF300; -defparam \ula_|zx_keyboard_|extended~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y21_N8 -cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~1 ( -// Equation(s): -// \ula_|ps2_keyboard_|WideXor0~1_combout = \ula_|ps2_keyboard_|shiftreg [6] $ (\ula_|ps2_keyboard_|shiftreg [7] $ (\ula_|ps2_keyboard_|shiftreg [8] $ (\ula_|ps2_keyboard_|shiftreg [5]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|ps2_keyboard_|shiftreg [7]), - .datac(\ula_|ps2_keyboard_|shiftreg [8]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|WideXor0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|WideXor0~1 .lut_mask = 16'h6996; -defparam \ula_|ps2_keyboard_|WideXor0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y21_N0 -cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|WideXor0~0_combout = \ula_|ps2_keyboard_|shiftreg [2] $ (\ula_|ps2_keyboard_|shiftreg [0] $ (\ula_|ps2_keyboard_|shiftreg [1] $ (\ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|WideXor0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|WideXor0~0 .lut_mask = 16'h6996; -defparam \ula_|ps2_keyboard_|WideXor0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y21_N6 -cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~2 ( -// Equation(s): -// \ula_|ps2_keyboard_|WideXor0~2_combout = \ula_|ps2_keyboard_|shiftreg [4] $ (\ula_|ps2_keyboard_|WideXor0~1_combout $ (\ula_|ps2_keyboard_|WideXor0~0_combout )) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [4]), - .datac(\ula_|ps2_keyboard_|WideXor0~1_combout ), - .datad(\ula_|ps2_keyboard_|WideXor0~0_combout ), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|WideXor0~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|WideXor0~2 .lut_mask = 16'hC33C; -defparam \ula_|ps2_keyboard_|WideXor0~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y21_N8 -cycloneive_lcell_comb \ula_|ps2_keyboard_|scan_code_ready~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|scan_code_ready~0_combout = (\ula_|ps2_keyboard_|LessThan0~0_combout & (\PS2_DAT~input_o & (\ula_|ps2_keyboard_|clk_edge~q & \ula_|ps2_keyboard_|WideXor0~2_combout ))) - - .dataa(\ula_|ps2_keyboard_|LessThan0~0_combout ), - .datab(\PS2_DAT~input_o ), - .datac(\ula_|ps2_keyboard_|clk_edge~q ), - .datad(\ula_|ps2_keyboard_|WideXor0~2_combout ), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|scan_code_ready~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|scan_code_ready~0 .lut_mask = 16'h8000; -defparam \ula_|ps2_keyboard_|scan_code_ready~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y21_N9 -dffeas \ula_|ps2_keyboard_|scan_code_ready ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|scan_code_ready~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|scan_code_ready~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|scan_code_ready .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|scan_code_ready .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y20_N1 -dffeas \ula_|zx_keyboard_|extended ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|extended~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|ps2_keyboard_|scan_code_ready~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|extended~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|extended .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|extended .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y21_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~15 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][0]~15_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (!\ula_|zx_keyboard_|Equal0~1_combout & !\ula_|ps2_keyboard_|shiftreg [7])) - - .dataa(\ula_|ps2_keyboard_|scan_code_ready~q ), - .datab(\ula_|zx_keyboard_|Equal0~1_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [7]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][0]~15 .lut_mask = 16'h0202; -defparam \ula_|zx_keyboard_|keys[0][0]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~36 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][1]~36_combout = (!\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[0][0]~15_combout )) - - .dataa(\ula_|zx_keyboard_|extended~q ), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][1]~36_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1]~36 .lut_mask = 16'h0500; -defparam \ula_|zx_keyboard_|keys[5][1]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~37 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][1]~37_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[5][1]~36_combout & \ula_|ps2_keyboard_|shiftreg [2])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[5][1]~36_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][1]~37_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1]~37 .lut_mask = 16'hA000; -defparam \ula_|zx_keyboard_|keys[5][1]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~0 ( -// Equation(s): -// \ula_|zx_keyboard_|shifted~0_combout = (\ula_|zx_keyboard_|keys[0][0]~15_combout & (!\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|zx_keyboard_|extended~q )) - - .dataa(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|zx_keyboard_|extended~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|shifted~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|shifted~0 .lut_mask = 16'h000A; -defparam \ula_|zx_keyboard_|shifted~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y21_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|released~0 ( -// Equation(s): -// \ula_|zx_keyboard_|released~0_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (\ula_|zx_keyboard_|Equal0~1_combout & ((\ula_|ps2_keyboard_|shiftreg [4]) # (\ula_|zx_keyboard_|released~q )))) # (!\ula_|ps2_keyboard_|scan_code_ready~q & -// (((\ula_|zx_keyboard_|released~q )))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|zx_keyboard_|Equal0~1_combout ), - .datac(\ula_|zx_keyboard_|released~q ), - .datad(\ula_|ps2_keyboard_|scan_code_ready~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|released~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|released~0 .lut_mask = 16'hC8F0; -defparam \ula_|zx_keyboard_|released~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y21_N19 -dffeas \ula_|zx_keyboard_|released ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|released~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|released~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|released .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|released .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr17~0 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr17~0_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [0]))) # (!\ula_|ps2_keyboard_|shiftreg [1] & -// (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [0]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr17~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr17~0 .lut_mask = 16'h4002; -defparam \ula_|zx_keyboard_|WideOr17~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~2 ( -// Equation(s): -// \ula_|zx_keyboard_|shifted~2_combout = (\ula_|zx_keyboard_|WideOr17~0_combout & (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [4])) - - .dataa(\ula_|zx_keyboard_|WideOr17~0_combout ), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|shifted~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|shifted~2 .lut_mask = 16'h0A00; -defparam \ula_|zx_keyboard_|shifted~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~3 ( -// Equation(s): -// \ula_|zx_keyboard_|shifted~3_combout = (\ula_|zx_keyboard_|shifted~0_combout & ((\ula_|zx_keyboard_|shifted~2_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|shifted~2_combout & ((\ula_|zx_keyboard_|shifted~q ))))) # -// (!\ula_|zx_keyboard_|shifted~0_combout & (((\ula_|zx_keyboard_|shifted~q )))) - - .dataa(\ula_|zx_keyboard_|shifted~0_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|shifted~q ), - .datad(\ula_|zx_keyboard_|shifted~2_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|shifted~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|shifted~3 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|shifted~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y21_N3 -dffeas \ula_|zx_keyboard_|shifted ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|shifted~3_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|shifted~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|shifted .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|shifted .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~35 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][1]~35_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [3])) - - .dataa(\ula_|zx_keyboard_|shifted~q ), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(gnd), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][1]~35_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1]~35 .lut_mask = 16'hFF88; -defparam \ula_|zx_keyboard_|keys[5][1]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~38 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][1]~38_combout = (!\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [0])) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][1]~38_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1]~38 .lut_mask = 16'h0003; -defparam \ula_|zx_keyboard_|keys[5][1]~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~39 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][1]~39_combout = (\ula_|zx_keyboard_|keys[5][1]~37_combout & ((\ula_|zx_keyboard_|keys[5][1]~38_combout & (!\ula_|zx_keyboard_|keys[5][1]~35_combout )) # (!\ula_|zx_keyboard_|keys[5][1]~38_combout & -// ((\ula_|zx_keyboard_|keys[5][1]~q ))))) # (!\ula_|zx_keyboard_|keys[5][1]~37_combout & (((\ula_|zx_keyboard_|keys[5][1]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[5][1]~37_combout ), - .datab(\ula_|zx_keyboard_|keys[5][1]~35_combout ), - .datac(\ula_|zx_keyboard_|keys[5][1]~q ), - .datad(\ula_|zx_keyboard_|keys[5][1]~38_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][1]~39_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1]~39 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[5][1]~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y18_N19 -dffeas \ula_|zx_keyboard_|keys[5][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[5][1]~39_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[5][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[5][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][1]~31 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][1]~31_combout = (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [0]) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][1]~31_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][1]~31 .lut_mask = 16'h00CC; -defparam \ula_|zx_keyboard_|keys[4][1]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y21_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~23 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][1]~23_combout = (!\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [7] & \ula_|ps2_keyboard_|scan_code_ready~q )) - - .dataa(\ula_|zx_keyboard_|extended~q ), - .datab(\ula_|ps2_keyboard_|shiftreg [7]), - .datac(\ula_|ps2_keyboard_|scan_code_ready~q ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][1]~23_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][1]~23 .lut_mask = 16'h1010; -defparam \ula_|zx_keyboard_|keys[7][1]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y21_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~32 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~32_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [4])) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~32_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~32 .lut_mask = 16'h000C; -defparam \ula_|zx_keyboard_|keys[7][2]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y21_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~33 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][2]~33_combout = (\ula_|zx_keyboard_|keys[7][1]~23_combout & (\ula_|zx_keyboard_|keys[7][2]~32_combout & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|zx_keyboard_|keys[7][1]~23_combout ), - .datab(\ula_|zx_keyboard_|keys[7][2]~32_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][2]~33_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][2]~33 .lut_mask = 16'h0080; -defparam \ula_|zx_keyboard_|keys[5][2]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][1]~34 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][1]~34_combout = (\ula_|zx_keyboard_|keys[4][1]~31_combout & ((\ula_|zx_keyboard_|keys[5][2]~33_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[5][2]~33_combout & (\ula_|zx_keyboard_|keys[4][1]~q -// )))) # (!\ula_|zx_keyboard_|keys[4][1]~31_combout & (((\ula_|zx_keyboard_|keys[4][1]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[4][1]~31_combout ), - .datab(\ula_|zx_keyboard_|keys[5][2]~33_combout ), - .datac(\ula_|zx_keyboard_|keys[4][1]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][1]~34_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][1]~34 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[4][1]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y18_N9 -dffeas \ula_|zx_keyboard_|keys[4][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[4][1]~34_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[4][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[4][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N24 -cycloneive_lcell_comb \D[1]~30 ( -// Equation(s): -// \D[1]~30_combout = (\z80_|address_pins_|abus[13]~20_combout & (((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][1]~q )))) # (!\z80_|address_pins_|abus[13]~20_combout & (!\ula_|zx_keyboard_|keys[5][1]~q & -// ((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][1]~q )))) - - .dataa(\z80_|address_pins_|abus[13]~20_combout ), - .datab(\ula_|zx_keyboard_|keys[5][1]~q ), - .datac(\ula_|zx_keyboard_|keys[4][1]~q ), - .datad(\z80_|address_pins_|abus[12]~21_combout ), - .cin(gnd), - .combout(\D[1]~30_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~30 .lut_mask = 16'hBB0B; -defparam \D[1]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~24 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][4]~24_combout = (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [2]) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][4]~24_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][4]~24 .lut_mask = 16'hA0A0; -defparam \ula_|zx_keyboard_|keys[5][4]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~28 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][1]~28_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[7][1]~23_combout & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[5][4]~24_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|zx_keyboard_|keys[7][1]~23_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|zx_keyboard_|keys[5][4]~24_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][1]~28_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][1]~28 .lut_mask = 16'h0400; -defparam \ula_|zx_keyboard_|keys[3][1]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~29 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][1]~29_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [0])) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][1]~29_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][1]~29 .lut_mask = 16'h00C0; -defparam \ula_|zx_keyboard_|keys[3][1]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~30 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][1]~30_combout = (\ula_|zx_keyboard_|keys[3][1]~28_combout & ((\ula_|zx_keyboard_|keys[3][1]~29_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][1]~29_combout & ((\ula_|zx_keyboard_|keys[3][1]~q -// ))))) # (!\ula_|zx_keyboard_|keys[3][1]~28_combout & (((\ula_|zx_keyboard_|keys[3][1]~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[3][1]~28_combout ), - .datac(\ula_|zx_keyboard_|keys[3][1]~q ), - .datad(\ula_|zx_keyboard_|keys[3][1]~29_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][1]~30_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][1]~30 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[3][1]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y18_N17 -dffeas \ula_|zx_keyboard_|keys[3][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[3][1]~30_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[3][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[3][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][4]~25 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][4]~25_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[5][4]~24_combout & (\ula_|zx_keyboard_|keys[7][1]~23_combout & !\ula_|ps2_keyboard_|shiftreg [1]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|zx_keyboard_|keys[5][4]~24_combout ), - .datac(\ula_|zx_keyboard_|keys[7][1]~23_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][4]~25_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][4]~25 .lut_mask = 16'h0040; -defparam \ula_|zx_keyboard_|keys[1][4]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][1]~26 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][1]~26_combout = (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|zx_keyboard_|keys[1][4]~25_combout & \ula_|ps2_keyboard_|shiftreg [0])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [5]), - .datab(\ula_|zx_keyboard_|keys[1][4]~25_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][1]~26_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][1]~26 .lut_mask = 16'h4040; -defparam \ula_|zx_keyboard_|keys[2][1]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][1]~27 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][1]~27_combout = (\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[2][1]~26_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[2][1]~26_combout & ((\ula_|zx_keyboard_|keys[2][1]~q ))))) # -// (!\ula_|ps2_keyboard_|shiftreg [3] & (((\ula_|zx_keyboard_|keys[2][1]~q )))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[2][1]~q ), - .datad(\ula_|zx_keyboard_|keys[2][1]~26_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][1]~27_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][1]~27 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[2][1]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y20_N17 -dffeas \ula_|zx_keyboard_|keys[2][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[2][1]~27_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[2][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[2][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~0 ( -// Equation(s): -// \ula_|zx_keyboard_|key_row~0_combout = ((\z80_|address_pins_|DFFE_apin_latch [10]) # (!\ula_|zx_keyboard_|keys[2][1]~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [10]), - .datad(\ula_|zx_keyboard_|keys[2][1]~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|key_row~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|key_row~0 .lut_mask = 16'hF3FF; -defparam \ula_|zx_keyboard_|key_row~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~14 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][1]~14_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & !\ula_|ps2_keyboard_|shiftreg [4])) - - .dataa(gnd), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|shifted~q ), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][1]~14_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][1]~14 .lut_mask = 16'hCCCF; -defparam \ula_|zx_keyboard_|keys[0][1]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~16 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][1]~16_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [4] $ (\ula_|ps2_keyboard_|shiftreg [2])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][1]~16_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][1]~16 .lut_mask = 16'h0060; -defparam \ula_|zx_keyboard_|keys[0][1]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~17 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][1]~17_combout = (\ula_|zx_keyboard_|keys[0][1]~16_combout & ((\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [4])) # (!\ula_|ps2_keyboard_|shiftreg [1] & -// (\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [4])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|zx_keyboard_|keys[0][1]~16_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][1]~17_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][1]~17 .lut_mask = 16'h2040; -defparam \ula_|zx_keyboard_|keys[0][1]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~18 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][1]~18_combout = (\ula_|zx_keyboard_|shifted~0_combout & ((\ula_|zx_keyboard_|keys[0][1]~17_combout & (!\ula_|zx_keyboard_|keys[0][1]~14_combout )) # (!\ula_|zx_keyboard_|keys[0][1]~17_combout & -// ((\ula_|zx_keyboard_|keys[0][1]~q ))))) # (!\ula_|zx_keyboard_|shifted~0_combout & (((\ula_|zx_keyboard_|keys[0][1]~q )))) - - .dataa(\ula_|zx_keyboard_|shifted~0_combout ), - .datab(\ula_|zx_keyboard_|keys[0][1]~14_combout ), - .datac(\ula_|zx_keyboard_|keys[0][1]~q ), - .datad(\ula_|zx_keyboard_|keys[0][1]~17_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][1]~18_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][1]~18 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[0][1]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y21_N7 -dffeas \ula_|zx_keyboard_|keys[0][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[0][1]~18_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[0][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[0][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~19 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][4]~19_combout = (!\ula_|ps2_keyboard_|shiftreg [7] & (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|zx_keyboard_|extended~q & \ula_|ps2_keyboard_|scan_code_ready~q ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [7]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|zx_keyboard_|extended~q ), - .datad(\ula_|ps2_keyboard_|scan_code_ready~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][4]~19_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][4]~19 .lut_mask = 16'h0100; -defparam \ula_|zx_keyboard_|keys[7][4]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~20 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][4]~20_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [2]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [0]), - .datab(\ula_|ps2_keyboard_|shiftreg [4]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][4]~20_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][4]~20 .lut_mask = 16'h0080; -defparam \ula_|zx_keyboard_|keys[6][4]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][1]~21 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][1]~21_combout = (\ula_|zx_keyboard_|keys[7][4]~19_combout & (\ula_|zx_keyboard_|keys[6][4]~20_combout & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|zx_keyboard_|keys[7][4]~19_combout ), - .datab(\ula_|zx_keyboard_|keys[6][4]~20_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][1]~21_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][1]~21 .lut_mask = 16'h0800; -defparam \ula_|zx_keyboard_|keys[1][1]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][1]~22 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][1]~22_combout = (\ula_|zx_keyboard_|keys[1][1]~21_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[1][1]~21_combout & (\ula_|zx_keyboard_|keys[1][1]~q )) - - .dataa(gnd), - .datab(\ula_|zx_keyboard_|keys[1][1]~21_combout ), - .datac(\ula_|zx_keyboard_|keys[1][1]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][1]~22_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][1]~22 .lut_mask = 16'h30FC; -defparam \ula_|zx_keyboard_|keys[1][1]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y20_N13 -dffeas \ula_|zx_keyboard_|keys[1][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[1][1]~22_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[1][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[1][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N2 -cycloneive_lcell_comb \D[1]~28 ( -// Equation(s): -// \D[1]~28_combout = (\ula_|zx_keyboard_|keys[0][1]~q & (\z80_|address_pins_|abus[8]~18_combout & ((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][1]~q )))) # (!\ula_|zx_keyboard_|keys[0][1]~q & -// (((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][1]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[0][1]~q ), - .datab(\z80_|address_pins_|abus[8]~18_combout ), - .datac(\z80_|address_pins_|abus[9]~17_combout ), - .datad(\ula_|zx_keyboard_|keys[1][1]~q ), - .cin(gnd), - .combout(\D[1]~28_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~28 .lut_mask = 16'hD0DD; -defparam \D[1]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N26 -cycloneive_lcell_comb \D[1]~29 ( -// Equation(s): -// \D[1]~29_combout = (\ula_|zx_keyboard_|key_row~0_combout & (\D[1]~28_combout & ((\z80_|address_pins_|abus[11]~19_combout ) # (!\ula_|zx_keyboard_|keys[3][1]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[3][1]~q ), - .datab(\ula_|zx_keyboard_|key_row~0_combout ), - .datac(\z80_|address_pins_|abus[11]~19_combout ), - .datad(\D[1]~28_combout ), - .cin(gnd), - .combout(\D[1]~29_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~29 .lut_mask = 16'hC400; -defparam \D[1]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~41 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][1]~41_combout = (!\ula_|zx_keyboard_|extended~q & (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[0][0]~15_combout ))) - - .dataa(\ula_|zx_keyboard_|extended~q ), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][1]~41_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1]~41 .lut_mask = 16'h0400; -defparam \ula_|zx_keyboard_|keys[6][1]~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~42 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][1]~42_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [3]))) # (!\ula_|ps2_keyboard_|shiftreg [1] & -// (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][1]~42_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1]~42 .lut_mask = 16'h0240; -defparam \ula_|zx_keyboard_|keys[6][1]~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~43 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][1]~43_combout = (\ula_|zx_keyboard_|keys[6][1]~41_combout & (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|zx_keyboard_|keys[6][1]~42_combout )) - - .dataa(\ula_|zx_keyboard_|keys[6][1]~41_combout ), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|zx_keyboard_|keys[6][1]~42_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][1]~43_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1]~43 .lut_mask = 16'hA000; -defparam \ula_|zx_keyboard_|keys[6][1]~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~40 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][1]~40_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [2] & \ula_|zx_keyboard_|shifted~q )) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|zx_keyboard_|shifted~q ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][1]~40_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1]~40 .lut_mask = 16'hEAEA; -defparam \ula_|zx_keyboard_|keys[6][1]~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~44 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][1]~44_combout = (\ula_|zx_keyboard_|keys[6][1]~43_combout & ((!\ula_|zx_keyboard_|keys[6][1]~40_combout ))) # (!\ula_|zx_keyboard_|keys[6][1]~43_combout & (\ula_|zx_keyboard_|keys[6][1]~q )) - - .dataa(\ula_|zx_keyboard_|keys[6][1]~43_combout ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[6][1]~q ), - .datad(\ula_|zx_keyboard_|keys[6][1]~40_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][1]~44_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1]~44 .lut_mask = 16'h50FA; -defparam \ula_|zx_keyboard_|keys[6][1]~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y20_N25 -dffeas \ula_|zx_keyboard_|keys[6][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[6][1]~44_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[6][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[6][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y21_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~45 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][1]~45_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (!\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [7]))) - - .dataa(\ula_|ps2_keyboard_|scan_code_ready~q ), - .datab(\ula_|zx_keyboard_|extended~q ), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|ps2_keyboard_|shiftreg [7]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][1]~45_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][1]~45 .lut_mask = 16'h0002; -defparam \ula_|zx_keyboard_|keys[7][1]~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~5 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~5_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (((!\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [1])))) # (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & -// ((\ula_|ps2_keyboard_|shiftreg [2]) # (\ula_|ps2_keyboard_|shiftreg [1])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~5_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~5 .lut_mask = 16'h0A38; -defparam \ula_|zx_keyboard_|WideOr16~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~2 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~2_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~2 .lut_mask = 16'h0044; -defparam \ula_|zx_keyboard_|WideOr16~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~4 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~4_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1])) # (!\ula_|ps2_keyboard_|shiftreg [2] & -// (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [1])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~4_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~4 .lut_mask = 16'h0140; -defparam \ula_|zx_keyboard_|WideOr16~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~7 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~7_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (((\ula_|zx_keyboard_|WideOr16~4_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|WideOr16~2_combout & (!\ula_|ps2_keyboard_|shiftreg [2]))) - - .dataa(\ula_|zx_keyboard_|WideOr16~2_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|zx_keyboard_|WideOr16~4_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~7_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~7 .lut_mask = 16'hF022; -defparam \ula_|zx_keyboard_|WideOr16~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~6 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~6_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (((\ula_|zx_keyboard_|WideOr16~7_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|WideOr16~5_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|zx_keyboard_|WideOr16~5_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|WideOr16~7_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~6_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~6 .lut_mask = 16'hF808; -defparam \ula_|zx_keyboard_|WideOr16~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y21_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~46 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][1]~46_combout = (\ula_|zx_keyboard_|keys[7][1]~45_combout & ((\ula_|zx_keyboard_|WideOr16~6_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|WideOr16~6_combout & ((\ula_|zx_keyboard_|keys[7][1]~q ))))) # -// (!\ula_|zx_keyboard_|keys[7][1]~45_combout & (((\ula_|zx_keyboard_|keys[7][1]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[7][1]~45_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[7][1]~q ), - .datad(\ula_|zx_keyboard_|WideOr16~6_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][1]~46_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][1]~46 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[7][1]~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y21_N31 -dffeas \ula_|zx_keyboard_|keys[7][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[7][1]~46_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[7][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[7][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N20 +// Location: LCCOMB_X31_Y10_N20 cycloneive_lcell_comb \D[1]~31 ( // Equation(s): -// \D[1]~31_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\z80_|address_pins_|abus[15]~22_combout ) # (!\ula_|zx_keyboard_|keys[7][1]~q )))) # (!\z80_|address_pins_|abus[14]~23_combout & (!\ula_|zx_keyboard_|keys[6][1]~q & -// ((\z80_|address_pins_|abus[15]~22_combout ) # (!\ula_|zx_keyboard_|keys[7][1]~q )))) +// \D[1]~31_combout = ((\Equal2~0_combout & (\D[1]~30_combout )) # (!\Equal2~0_combout & ((\D[1]~81_combout )))) # (!\Equal2~1_combout ) - .dataa(\z80_|address_pins_|abus[14]~23_combout ), - .datab(\ula_|zx_keyboard_|keys[6][1]~q ), - .datac(\z80_|address_pins_|abus[15]~22_combout ), - .datad(\ula_|zx_keyboard_|keys[7][1]~q ), + .dataa(\Equal2~1_combout ), + .datab(\Equal2~0_combout ), + .datac(\D[1]~30_combout ), + .datad(\D[1]~81_combout ), .cin(gnd), .combout(\D[1]~31_combout ), .cout()); // synopsys translate_off -defparam \D[1]~31 .lut_mask = 16'hB0BB; +defparam \D[1]~31 .lut_mask = 16'hF7D5; defparam \D[1]~31 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y20_N18 +// Location: LCCOMB_X31_Y10_N2 cycloneive_lcell_comb \D[1]~32 ( // Equation(s): -// \D[1]~32_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[1]~30_combout & (\D[1]~29_combout & \D[1]~31_combout ))) +// \D[1]~32_combout = (\z80_|pin_control_|bus_db_pin_oe~15_combout & (((\z80_|data_pins_|dout [1] & \D[1]~31_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout & (((\D[1]~31_combout )) # (!\Equal2~1_combout ))) - .dataa(\D[1]~30_combout ), - .datab(\z80_|address_pins_|abus[0]~16_combout ), - .datac(\D[1]~29_combout ), + .dataa(\Equal2~1_combout ), + .datab(\z80_|data_pins_|dout [1]), + .datac(\z80_|pin_control_|bus_db_pin_oe~15_combout ), .datad(\D[1]~31_combout ), .cin(gnd), .combout(\D[1]~32_combout ), .cout()); // synopsys translate_off -defparam \D[1]~32 .lut_mask = 16'hECCC; +defparam \D[1]~32 .lut_mask = 16'hCF05; defparam \D[1]~32 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y22_N4 -cycloneive_lcell_comb \D[1]~33 ( -// Equation(s): -// \D[1]~33_combout = ((\Equal2~0_combout & ((\D[1]~32_combout ))) # (!\Equal2~0_combout & (\D[1]~103_combout ))) # (!\Equal2~1_combout ) - - .dataa(\Equal2~0_combout ), - .datab(\Equal2~1_combout ), - .datac(\D[1]~103_combout ), - .datad(\D[1]~32_combout ), - .cin(gnd), - .combout(\D[1]~33_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~33 .lut_mask = 16'hFB73; -defparam \D[1]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y22_N8 -cycloneive_lcell_comb \D[1]~34 ( -// Equation(s): -// \D[1]~34_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\D[1]~33_combout & \z80_|data_pins_|dout [1])))) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\D[1]~33_combout )) # (!\Equal2~1_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datab(\Equal2~1_combout ), - .datac(\D[1]~33_combout ), - .datad(\z80_|data_pins_|dout [1]), - .cin(gnd), - .combout(\D[1]~34_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~34 .lut_mask = 16'hF151; -defparam \D[1]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N18 +// Location: LCCOMB_X30_Y13_N14 cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] ( // Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [1] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[1]~11_combout ) # ((\z80_|pin_control_|bus_db_pin_re~combout & \D[1]~34_combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & -// (((\z80_|pin_control_|bus_db_pin_re~combout & \D[1]~34_combout )))) +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [1] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[1]~11_combout ) # ((\D[1]~32_combout & \z80_|pin_control_|bus_db_pin_re~combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & +// (((\D[1]~32_combout & \z80_|pin_control_|bus_db_pin_re~combout )))) .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), .datab(\z80_|bus_control_|db[1]~11_combout ), - .datac(\z80_|pin_control_|bus_db_pin_re~combout ), - .datad(\D[1]~34_combout ), + .datac(\D[1]~32_combout ), + .datad(\z80_|pin_control_|bus_db_pin_re~combout ), .cin(gnd), .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [1]), .cout()); @@ -43910,7 +40644,42 @@ defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] .lut_mask = 16'hF888; defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y13_N19 +// Location: LCCOMB_X28_Y12_N16 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_re~2 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_re~2_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (((\z80_|execute_|fIORead~3_combout & \z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M1_ff~q ))) # (!\z80_|sequencer_|DFFE_T2_ff~q & +// (\z80_|execute_|fIORead~3_combout & ((\z80_|sequencer_|DFFE_T3_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|execute_|fIORead~3_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_re~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_re~2 .lut_mask = 16'hCE0A; +defparam \z80_|pin_control_|bus_db_pin_re~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N8 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_2 ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_2~combout = (\z80_|execute_|ctl_bus_db_we~7_combout ) # ((\z80_|pin_control_|bus_db_pin_re~2_combout ) # ((\z80_|execute_|fMRead~36_combout & \z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datab(\z80_|execute_|fMRead~36_combout ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|pin_control_|bus_db_pin_re~2_combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_2 .lut_mask = 16'hFFEA; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y13_N15 dffeas \z80_|data_pins_|dout[1] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [1]), @@ -43929,61 +40698,27 @@ defparam \z80_|data_pins_|dout[1] .is_wysiwyg = "true"; defparam \z80_|data_pins_|dout[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N30 -cycloneive_lcell_comb \z80_|bus_control_|db[1]~10 ( -// Equation(s): -// \z80_|bus_control_|db[1]~10_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[1]~26_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) - - .dataa(gnd), - .datab(\z80_|alu_control_|db[1]~26_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|bus_control_|db[0]~4_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[1]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[1]~10 .lut_mask = 16'hCF00; -defparam \z80_|bus_control_|db[1]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N24 +// Location: LCCOMB_X30_Y13_N28 cycloneive_lcell_comb \z80_|bus_control_|db[1]~11 ( // Equation(s): // \z80_|bus_control_|db[1]~11_combout = ((\z80_|bus_control_|db[1]~10_combout & ((\z80_|data_pins_|dout [1]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - .dataa(\z80_|execute_|ctl_bus_db_oe~combout ), - .datab(\z80_|data_pins_|dout [1]), - .datac(\z80_|bus_control_|db[1]~10_combout ), - .datad(\z80_|bus_control_|db[0]~6_combout ), + .dataa(\z80_|bus_control_|db[0]~6_combout ), + .datab(\z80_|bus_control_|db[1]~10_combout ), + .datac(\z80_|data_pins_|dout [1]), + .datad(\z80_|execute_|ctl_bus_db_oe~combout ), .cin(gnd), .combout(\z80_|bus_control_|db[1]~11_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[1]~11 .lut_mask = 16'hD0FF; +defparam \z80_|bus_control_|db[1]~11 .lut_mask = 16'hD5DD; defparam \z80_|bus_control_|db[1]~11 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N14 -cycloneive_lcell_comb \z80_|ir_|opcode[1]~feeder ( -// Equation(s): -// \z80_|ir_|opcode[1]~feeder_combout = \z80_|bus_control_|db[1]~11_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|bus_control_|db[1]~11_combout ), - .cin(gnd), - .combout(\z80_|ir_|opcode[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|ir_|opcode[1]~feeder .lut_mask = 16'hFF00; -defparam \z80_|ir_|opcode[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y12_N15 +// Location: FF_X30_Y13_N29 dffeas \z80_|ir_|opcode[1] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|ir_|opcode[1]~feeder_combout ), + .d(\z80_|bus_control_|db[1]~11_combout ), .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), @@ -43999,8110 +40734,848 @@ defparam \z80_|ir_|opcode[1] .is_wysiwyg = "true"; defparam \z80_|ir_|opcode[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y13_N18 -cycloneive_lcell_comb \z80_|pla_decode_|Equal40~0 ( +// Location: LCCOMB_X27_Y13_N0 +cycloneive_lcell_comb \z80_|pla_decode_|Equal2~0 ( // Equation(s): -// \z80_|pla_decode_|Equal40~0_combout = (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [1])) +// \z80_|pla_decode_|Equal2~0_combout = (!\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1]) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|ir_|opcode [1]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal2~0 .lut_mask = 16'h3030; +defparam \z80_|pla_decode_|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~15 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~15_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal13~0_combout & \z80_|ir_|opcode [3]))) .dataa(\z80_|ir_|opcode [0]), - .datab(gnd), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal40~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal40~0 .lut_mask = 16'h0005; -defparam \z80_|pla_decode_|Equal40~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N24 -cycloneive_lcell_comb \z80_|pla_decode_|Equal21~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal21~1_combout = (\z80_|pla_decode_|Equal21~0_combout & (\z80_|pla_decode_|Equal40~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal21~0_combout ), - .datab(\z80_|pla_decode_|Equal40~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal21~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal21~1 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal21~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~26 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~26_combout = (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|pla_decode_|Equal21~1_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T4_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~26 .lut_mask = 16'hC080; -defparam \z80_|execute_|ctl_alu_op_low~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~28 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~28_combout = (\z80_|execute_|ctl_alu_op_low~26_combout ) # ((\z80_|execute_|ctl_alu_op_low~23_combout ) # ((\z80_|execute_|ctl_alu_op_low~34_combout ) # (\z80_|execute_|ctl_alu_op_low~27_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~26_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~23_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~34_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~28 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_alu_op_low~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~3_combout = (\z80_|execute_|ctl_alu_op_low~28_combout & (\z80_|pla_decode_|Equal64~0_combout & ((\z80_|pla_decode_|Equal9~0_combout ) # (\z80_|pla_decode_|Equal3~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~28_combout ), - .datab(\z80_|pla_decode_|Equal9~0_combout ), - .datac(\z80_|pla_decode_|Equal64~0_combout ), - .datad(\z80_|pla_decode_|Equal3~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~3 .lut_mask = 16'hA080; -defparam \z80_|execute_|ctl_flags_cf_cpl~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~2_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ) # ((\z80_|execute_|ctl_mRead~36_combout & ((\z80_|execute_|ixy_d~6_combout ) # (\z80_|execute_|ctl_mRead~11_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~36_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|execute_|ctl_mRead~11_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~2 .lut_mask = 16'hFFA8; -defparam \z80_|execute_|ctl_flags_cf_cpl~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N20 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout = (!\z80_|execute_|ctl_mWrite~10_combout & (((!\z80_|pla_decode_|Equal61~2_combout & !\z80_|execute_|ctl_mWrite~16_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal61~2_combout ), - .datab(\z80_|execute_|ctl_mWrite~16_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_mWrite~10_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 .lut_mask = 16'h001F; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N2 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout = (\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_state_alu~5_combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|execute_|ctl_mRead~36_combout )))) # (!\z80_|pla_decode_|Equal56~0_combout & -// (((!\z80_|nM1_int~2_combout )) # (!\z80_|execute_|ctl_mRead~36_combout ))) - - .dataa(\z80_|pla_decode_|Equal56~0_combout ), - .datab(\z80_|execute_|ctl_mRead~36_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_state_alu~5_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 .lut_mask = 16'h153F; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N28 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout = (\z80_|execute_|ctl_alu_core_R~4_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_R~4_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 .lut_mask = 16'h8000; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N16 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~6_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~5_combout & !\z80_|execute_|ctl_alu_sel_op2_neg~16_combout )) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 .lut_mask = 16'h0088; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N22 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout = (!\z80_|execute_|ctl_alu_core_R~1_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout & (\z80_|execute_|ctl_alu_core_S~7_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_R~1_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ), - .datac(\z80_|execute_|ctl_alu_core_S~7_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 .lut_mask = 16'h4000; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N18 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout & (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout & ((!\z80_|execute_|ctl_alu_op_low~27_combout ) # (!\z80_|execute_|ctl_flags_cf_cpl~2_combout )))) - - .dataa(\z80_|execute_|ctl_flags_cf_cpl~2_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), - .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 .lut_mask = 16'h040C; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N30 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~21 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~21_combout = (((!\z80_|pla_decode_|Equal40~1_combout & !\z80_|pla_decode_|Equal39~0_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|pla_decode_|Equal40~1_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~21 .lut_mask = 16'h777F; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N26 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout = (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~21_combout & ((\z80_|execute_|ctl_alu_op_low~23_combout ) # (\z80_|execute_|ctl_alu_op_low~27_combout ))) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op_low~23_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~21_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 .lut_mask = 16'h0F0C; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N4 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout = (\z80_|pla_decode_|Equal21~1_combout & ((\z80_|execute_|ixy_d~6_combout ) # ((\z80_|sequencer_|DFFE_T5_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 .lut_mask = 16'hC0E0; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N28 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout & ((\z80_|execute_|ctl_alu_op_low~23_combout ) # ((\z80_|execute_|ctl_alu_op_low~34_combout ) # (\z80_|execute_|ctl_alu_op_low~27_combout )))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~23_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~34_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 .lut_mask = 16'hAAA8; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N0 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout = (\z80_|execute_|ctl_flags_nf_we~1_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout & (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout & !\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ))) - - .dataa(\z80_|execute_|ctl_flags_nf_we~1_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 .lut_mask = 16'h0008; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N22 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~22_combout & (\z80_|execute_|ctl_flags_sz_we~4_combout & ((!\z80_|pla_decode_|Equal9~0_combout ) # (!\z80_|pla_decode_|Equal62~2_combout )))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~22_combout ), - .datab(\z80_|pla_decode_|Equal62~2_combout ), - .datac(\z80_|execute_|ctl_flags_sz_we~4_combout ), - .datad(\z80_|pla_decode_|Equal9~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17 .lut_mask = 16'h20A0; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~32 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~32_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|pla_decode_|Equal10~0_combout )) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal10~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~32 .lut_mask = 16'h8800; -defparam \z80_|execute_|ctl_alu_op_low~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N18 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|pla_decode_|Equal21~0_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal63~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal21~0_combout ), - .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|pla_decode_|Equal63~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 .lut_mask = 16'hCECC; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N20 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout = (\z80_|execute_|ctl_alu_op_low~32_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~32_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 .lut_mask = 16'hFFEF; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N24 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout = ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ) # ((\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & \z80_|execute_|ctl_alu_op_low~20_combout ))) # (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ) - - .dataa(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~20_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18 .lut_mask = 16'hFFB3; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N0 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~19 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~19_combout = (\z80_|execute_|ctl_state_alu~12_combout & ((\z80_|ir_|opcode [3] & (\z80_|ir_|opcode [4] & \z80_|ir_|opcode [5])) # (!\z80_|ir_|opcode [3] & ((!\z80_|ir_|opcode [5]))))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|execute_|ctl_state_alu~12_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~19 .lut_mask = 16'h8500; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N10 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~0 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[0]~19_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[7]~21_combout )) - - .dataa(\z80_|alu_|db[7]~21_combout ), - .datab(gnd), - .datac(\z80_|alu_|db[0]~19_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~0 .lut_mask = 16'hF0AA; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N28 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~1 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_control_|out[6]~2_combout )) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .datab(gnd), - .datac(\z80_|alu_control_|out[6]~2_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~1 .lut_mask = 16'hFA50; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N18 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~2 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout & ((!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout )))) # (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout -// & ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (!\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ))))) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~2 .lut_mask = 16'h11D8; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N30 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~3 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout = (\z80_|execute_|ctl_flags_cf2_we~3_combout & (\z80_|execute_|ctl_flags_cf2_sel_daa~combout $ ((!\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout )))) # (!\z80_|execute_|ctl_flags_cf2_we~3_combout & -// ((\z80_|alu_flags_|DFFE_inst_latch_cf2~q ) # ((\z80_|execute_|ctl_flags_cf2_sel_daa~combout & \z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout )))) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), - .datad(\z80_|execute_|ctl_flags_cf2_we~3_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~3 .lut_mask = 16'h99F8; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y9_N31 -dffeas \z80_|alu_flags_|DFFE_inst_latch_cf2 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2 .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~10_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal11~0_combout & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_M1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|pla_decode_|Equal11~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~10 .lut_mask = 16'h0B00; -defparam \z80_|execute_|ctl_flags_use_cf2~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~11_combout = (\z80_|execute_|ctl_flags_use_cf2~10_combout ) # ((\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # ((\z80_|pla_decode_|Equal10~0_combout & \z80_|execute_|ixy_d~7_combout ))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|execute_|ctl_flags_use_cf2~10_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~11 .lut_mask = 16'hFFEC; -defparam \z80_|execute_|ctl_flags_use_cf2~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~8_combout = (\z80_|execute_|ctl_ir_we~8_combout ) # ((\z80_|pla_decode_|Equal20~0_combout ) # (\z80_|execute_|ctl_ir_we~14_combout )) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal20~0_combout ), - .datad(\z80_|execute_|ctl_ir_we~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~8 .lut_mask = 16'hFFFA; -defparam \z80_|execute_|ctl_flags_use_cf2~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~9_combout = (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_flags_use_cf2~8_combout ) # ((\z80_|pla_decode_|Equal9~0_combout & \z80_|pla_decode_|Equal63~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal9~0_combout ), - .datab(\z80_|pla_decode_|Equal63~0_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|execute_|ctl_flags_use_cf2~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~9 .lut_mask = 16'h0F08; -defparam \z80_|execute_|ctl_flags_use_cf2~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~12 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~12_combout = (\z80_|execute_|ctl_flags_use_cf2~11_combout ) # (((\z80_|execute_|ctl_flags_use_cf2~9_combout ) # (\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout )) # (!\z80_|execute_|ctl_flags_use_cf2~13_combout )) - - .dataa(\z80_|execute_|ctl_flags_use_cf2~11_combout ), - .datab(\z80_|execute_|ctl_flags_use_cf2~13_combout ), - .datac(\z80_|execute_|ctl_flags_use_cf2~9_combout ), - .datad(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~12 .lut_mask = 16'hFFFB; -defparam \z80_|execute_|ctl_flags_use_cf2~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N16 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout = (\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & (((\z80_|alu_flags_|DFFE_inst_latch_cf2~q )))) # (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & ((\z80_|execute_|ctl_flags_use_cf2~12_combout & -// ((\z80_|alu_flags_|DFFE_inst_latch_cf2~q ))) # (!\z80_|execute_|ctl_flags_use_cf2~12_combout & (\z80_|alu_flags_|DFFE_inst_latch_cf~q )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), - .datad(\z80_|execute_|ctl_flags_use_cf2~12_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 .lut_mask = 16'hF0E4; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N22 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~20 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~20_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~19_combout & \z80_|execute_|ctl_alu_op_low~28_combout ))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~19_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~28_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~20 .lut_mask = 16'hFEFA; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~10_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ) # ((!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|execute_|ctl_alu_op_low~12_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|execute_|ctl_alu_op_low~12_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~10 .lut_mask = 16'hFF40; -defparam \z80_|execute_|ctl_flags_cf_cpl~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~8_combout = (\z80_|execute_|ctl_flags_cf_cpl~10_combout ) # ((\z80_|execute_|ctl_alu_op_low~12_combout & (\z80_|execute_|ctl_alu_op_low~8_combout & \z80_|execute_|ctl_alu_op_low~19_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), - .datab(\z80_|execute_|ctl_flags_cf_cpl~10_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~8 .lut_mask = 16'hECCC; -defparam \z80_|execute_|ctl_flags_cf_cpl~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~5_combout = ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_alu_op_low~12_combout ) # (\z80_|execute_|ctl_state_alu~7_combout )))) # (!\z80_|execute_|ctl_state_alu~15_combout ) - - .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), - .datab(\z80_|execute_|ctl_state_alu~15_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|execute_|ctl_state_alu~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~5 .lut_mask = 16'h3F3B; -defparam \z80_|execute_|ctl_flags_cf_cpl~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~6_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_flags_cf_cpl~5_combout ) # ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal68~2_combout )))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|pla_decode_|Equal68~2_combout ), - .datad(\z80_|execute_|ctl_flags_cf_cpl~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~6 .lut_mask = 16'hAA20; -defparam \z80_|execute_|ctl_flags_cf_cpl~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~7_combout = (\z80_|execute_|ctl_flags_cf_cpl~6_combout ) # ((!\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # (\z80_|execute_|ctl_flags_cf2_sel_daa~combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datad(\z80_|execute_|ctl_flags_cf_cpl~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~7 .lut_mask = 16'hFF32; -defparam \z80_|execute_|ctl_flags_cf_cpl~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_set~0 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_set~0_combout = (\z80_|execute_|ctl_state_alu~12_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal9~0_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~12_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal9~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_set~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_set~0 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_flags_cf_set~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~4_combout = (\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout & ((\z80_|execute_|ctl_alu_op_low~19_combout ) # (!\z80_|execute_|ctl_alu_op_low~33_combout ))) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), - .datac(\z80_|execute_|ctl_alu_op_low~19_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~33_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~4 .lut_mask = 16'hC0CC; -defparam \z80_|execute_|ctl_flags_cf_cpl~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~9_combout = (\z80_|execute_|ctl_flags_cf_cpl~8_combout ) # ((\z80_|execute_|ctl_flags_cf_cpl~7_combout ) # ((\z80_|execute_|ctl_flags_cf_set~0_combout ) # (\z80_|execute_|ctl_flags_cf_cpl~4_combout ))) - - .dataa(\z80_|execute_|ctl_flags_cf_cpl~8_combout ), - .datab(\z80_|execute_|ctl_flags_cf_cpl~7_combout ), - .datac(\z80_|execute_|ctl_flags_cf_set~0_combout ), - .datad(\z80_|execute_|ctl_flags_cf_cpl~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~9 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_flags_cf_cpl~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N4 -cycloneive_lcell_comb \z80_|alu_flags_|flags_cf ( -// Equation(s): -// \z80_|alu_flags_|flags_cf~combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~20_combout $ (((\z80_|execute_|ctl_flags_cf_cpl~3_combout ) # (\z80_|execute_|ctl_flags_cf_cpl~9_combout ))))) - - .dataa(\z80_|execute_|ctl_flags_cf_cpl~3_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~20_combout ), - .datad(\z80_|execute_|ctl_flags_cf_cpl~9_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|flags_cf~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_cf .lut_mask = 16'h0C48; -defparam \z80_|alu_flags_|flags_cf .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N2 -cycloneive_lcell_comb \z80_|alu_control_|db[0]~8 ( -// Equation(s): -// \z80_|alu_control_|db[0]~8_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & (((\z80_|bus_control_|db[0]~17_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) - - .dataa(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .datab(\z80_|execute_|ctl_sw_1d~7_combout ), - .datac(\z80_|bus_control_|db[0]~17_combout ), - .datad(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[0]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[0]~8 .lut_mask = 16'h22A2; -defparam \z80_|alu_control_|db[0]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N20 -cycloneive_lcell_comb \z80_|sw2_|db_up[0]~0 ( -// Equation(s): -// \z80_|sw2_|db_up[0]~0_combout = (\z80_|alu_|db[0]~19_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_sw_2u~7_combout ), - .datad(\z80_|alu_|db[0]~19_combout ), - .cin(gnd), - .combout(\z80_|sw2_|db_up[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sw2_|db_up[0]~0 .lut_mask = 16'hFF0F; -defparam \z80_|sw2_|db_up[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N4 -cycloneive_lcell_comb \z80_|alu_control_|db[0]~9 ( -// Equation(s): -// \z80_|alu_control_|db[0]~9_combout = (\z80_|alu_control_|db[0]~8_combout & (\z80_|sw2_|db_up[0]~0_combout & ((\z80_|reg_file_|gdfx_temp0[0]~22_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) - - .dataa(\z80_|alu_control_|db[0]~8_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .datac(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datad(\z80_|sw2_|db_up[0]~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[0]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[0]~9 .lut_mask = 16'h8A00; -defparam \z80_|alu_control_|db[0]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N26 -cycloneive_lcell_comb \z80_|alu_control_|db[0]~12 ( -// Equation(s): -// \z80_|alu_control_|db[0]~12_combout = ((\z80_|alu_control_|db[0]~9_combout & ((\z80_|alu_flags_|flags_cf~combout ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|alu_flags_|flags_cf~combout ), - .datab(\z80_|execute_|ctl_flags_oe~2_combout ), - .datac(\z80_|alu_control_|db[0]~9_combout ), - .datad(\z80_|alu_control_|db[6]~11_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[0]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[0]~12 .lut_mask = 16'hB0FF; -defparam \z80_|alu_control_|db[0]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~67 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][0]~67_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [4])) - - .dataa(\ula_|zx_keyboard_|shifted~q ), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][0]~67_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][0]~67 .lut_mask = 16'hFF50; -defparam \ula_|zx_keyboard_|keys[5][0]~67 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~81 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][0]~81_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [3]))) # (!\ula_|ps2_keyboard_|shiftreg [1] & -// (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][0]~81_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][0]~81 .lut_mask = 16'h0420; -defparam \ula_|zx_keyboard_|keys[5][0]~81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~82 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][0]~82_combout = (\ula_|zx_keyboard_|keys[5][0]~81_combout & (\ula_|zx_keyboard_|keys[6][1]~41_combout & (\ula_|ps2_keyboard_|shiftreg [2] $ (\ula_|ps2_keyboard_|shiftreg [4])))) - - .dataa(\ula_|zx_keyboard_|keys[5][0]~81_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|keys[6][1]~41_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][0]~82_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][0]~82 .lut_mask = 16'h2800; -defparam \ula_|zx_keyboard_|keys[5][0]~82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~83 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][0]~83_combout = (\ula_|zx_keyboard_|keys[5][0]~82_combout & (!\ula_|zx_keyboard_|keys[5][0]~67_combout )) # (!\ula_|zx_keyboard_|keys[5][0]~82_combout & ((\ula_|zx_keyboard_|keys[5][0]~q ))) - - .dataa(\ula_|zx_keyboard_|keys[5][0]~67_combout ), - .datab(\ula_|zx_keyboard_|keys[5][0]~82_combout ), - .datac(\ula_|zx_keyboard_|keys[5][0]~q ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][0]~83_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][0]~83 .lut_mask = 16'h7474; -defparam \ula_|zx_keyboard_|keys[5][0]~83 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y20_N11 -dffeas \ula_|zx_keyboard_|keys[5][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[5][0]~83_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[5][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[5][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~84 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][0]~84_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [5] $ (\ula_|ps2_keyboard_|shiftreg [3])))) # (!\ula_|ps2_keyboard_|shiftreg [1] & -// (!\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [0]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [5]), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][0]~84_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][0]~84 .lut_mask = 16'h0160; -defparam \ula_|zx_keyboard_|keys[4][0]~84 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~85 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][0]~85_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [3])) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|shifted~q ), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][0]~85_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][0]~85 .lut_mask = 16'hBABA; -defparam \ula_|zx_keyboard_|keys[4][0]~85 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~86 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][0]~86_combout = (\ula_|zx_keyboard_|keys[5][1]~37_combout & ((\ula_|zx_keyboard_|keys[4][0]~84_combout & ((!\ula_|zx_keyboard_|keys[4][0]~85_combout ))) # (!\ula_|zx_keyboard_|keys[4][0]~84_combout & -// (\ula_|zx_keyboard_|keys[4][0]~q )))) # (!\ula_|zx_keyboard_|keys[5][1]~37_combout & (((\ula_|zx_keyboard_|keys[4][0]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[5][1]~37_combout ), - .datab(\ula_|zx_keyboard_|keys[4][0]~84_combout ), - .datac(\ula_|zx_keyboard_|keys[4][0]~q ), - .datad(\ula_|zx_keyboard_|keys[4][0]~85_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][0]~86_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][0]~86 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[4][0]~86 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y18_N27 -dffeas \ula_|zx_keyboard_|keys[4][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[4][0]~86_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[4][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[4][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N20 -cycloneive_lcell_comb \D[0]~49 ( -// Equation(s): -// \D[0]~49_combout = (\z80_|address_pins_|abus[13]~20_combout & (((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][0]~q )))) # (!\z80_|address_pins_|abus[13]~20_combout & (!\ula_|zx_keyboard_|keys[5][0]~q & -// ((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][0]~q )))) - - .dataa(\z80_|address_pins_|abus[13]~20_combout ), - .datab(\ula_|zx_keyboard_|keys[5][0]~q ), - .datac(\ula_|zx_keyboard_|keys[4][0]~q ), - .datad(\z80_|address_pins_|abus[12]~21_combout ), - .cin(gnd), - .combout(\D[0]~49_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~49 .lut_mask = 16'hBB0B; -defparam \D[0]~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr4~0 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr4~0_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [5] & ((\ula_|ps2_keyboard_|shiftreg [6])))) # (!\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [5] & -// (\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [6]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr4~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr4~0 .lut_mask = 16'h8810; -defparam \ula_|zx_keyboard_|WideOr4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys~76 ( -// Equation(s): -// \ula_|zx_keyboard_|keys~76_combout = (!\ula_|zx_keyboard_|extended~q & (((\ula_|ps2_keyboard_|shiftreg [3]) # (!\ula_|zx_keyboard_|keys[4][1]~31_combout )) # (!\ula_|zx_keyboard_|WideOr4~0_combout ))) - - .dataa(\ula_|zx_keyboard_|WideOr4~0_combout ), - .datab(\ula_|zx_keyboard_|extended~q ), - .datac(\ula_|zx_keyboard_|keys[4][1]~31_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys~76_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys~76 .lut_mask = 16'h3313; -defparam \ula_|zx_keyboard_|keys~76 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~73 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~73_combout = (\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [6]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][3]~73_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~73 .lut_mask = 16'hF000; -defparam \ula_|zx_keyboard_|keys[4][3]~73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~47 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][4]~47_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [2])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][4]~47_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][4]~47 .lut_mask = 16'h0808; -defparam \ula_|zx_keyboard_|keys[6][4]~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr0~0 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr0~0_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [2])) # (!\ula_|ps2_keyboard_|shiftreg [1] & -// ((\ula_|ps2_keyboard_|shiftreg [2]))))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [0]), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr0~0 .lut_mask = 16'h0310; -defparam \ula_|zx_keyboard_|WideOr0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys~74 ( -// Equation(s): -// \ula_|zx_keyboard_|keys~74_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (((!\ula_|zx_keyboard_|WideOr0~0_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [4] & (((!\ula_|ps2_keyboard_|shiftreg [3])) # (!\ula_|zx_keyboard_|keys[6][4]~47_combout ))) - - .dataa(\ula_|zx_keyboard_|keys[6][4]~47_combout ), - .datab(\ula_|zx_keyboard_|WideOr0~0_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys~74_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys~74 .lut_mask = 16'h353F; -defparam \ula_|zx_keyboard_|keys~74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~75 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][0]~75_combout = (\ula_|zx_keyboard_|keys[0][0]~15_combout & (((\ula_|zx_keyboard_|keys[4][3]~73_combout & !\ula_|zx_keyboard_|keys~74_combout )) # (!\ula_|zx_keyboard_|extended~q ))) - - .dataa(\ula_|zx_keyboard_|keys[4][3]~73_combout ), - .datab(\ula_|zx_keyboard_|keys~74_combout ), - .datac(\ula_|zx_keyboard_|extended~q ), - .datad(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][0]~75_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][0]~75 .lut_mask = 16'h2F00; -defparam \ula_|zx_keyboard_|keys[0][0]~75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~77 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][0]~77_combout = (\ula_|zx_keyboard_|keys~76_combout & (((\ula_|zx_keyboard_|keys[0][0]~q )))) # (!\ula_|zx_keyboard_|keys~76_combout & ((\ula_|zx_keyboard_|keys[0][0]~75_combout & ((!\ula_|zx_keyboard_|released~q ))) # -// (!\ula_|zx_keyboard_|keys[0][0]~75_combout & (\ula_|zx_keyboard_|keys[0][0]~q )))) - - .dataa(\ula_|zx_keyboard_|keys~76_combout ), - .datab(\ula_|zx_keyboard_|keys[0][0]~75_combout ), - .datac(\ula_|zx_keyboard_|keys[0][0]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][0]~77_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][0]~77 .lut_mask = 16'hB0F4; -defparam \ula_|zx_keyboard_|keys[0][0]~77 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y20_N15 -dffeas \ula_|zx_keyboard_|keys[0][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[0][0]~77_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[0][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[0][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][0]~71 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][0]~71_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[1][4]~25_combout & !\ula_|ps2_keyboard_|shiftreg [5]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [0]), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|zx_keyboard_|keys[1][4]~25_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][0]~71_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][0]~71 .lut_mask = 16'h0040; -defparam \ula_|zx_keyboard_|keys[1][0]~71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][0]~72 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][0]~72_combout = (\ula_|zx_keyboard_|keys[1][0]~71_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[1][0]~71_combout & (\ula_|zx_keyboard_|keys[1][0]~q )) - - .dataa(gnd), - .datab(\ula_|zx_keyboard_|keys[1][0]~71_combout ), - .datac(\ula_|zx_keyboard_|keys[1][0]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][0]~72_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][0]~72 .lut_mask = 16'h30FC; -defparam \ula_|zx_keyboard_|keys[1][0]~72 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y19_N17 -dffeas \ula_|zx_keyboard_|keys[1][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[1][0]~72_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[1][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[1][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N30 -cycloneive_lcell_comb \D[0]~47 ( -// Equation(s): -// \D[0]~47_combout = (\ula_|zx_keyboard_|keys[0][0]~q & (\z80_|address_pins_|abus[8]~18_combout & ((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][0]~q )))) # (!\ula_|zx_keyboard_|keys[0][0]~q & -// (((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][0]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[0][0]~q ), - .datab(\z80_|address_pins_|abus[8]~18_combout ), - .datac(\z80_|address_pins_|abus[9]~17_combout ), - .datad(\ula_|zx_keyboard_|keys[1][0]~q ), - .cin(gnd), - .combout(\D[0]~47_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~47 .lut_mask = 16'hD0DD; -defparam \D[0]~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][0]~80 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][0]~80_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (((\ula_|zx_keyboard_|keys[2][0]~q )))) # (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[2][1]~26_combout & (!\ula_|zx_keyboard_|released~q )) # -// (!\ula_|zx_keyboard_|keys[2][1]~26_combout & ((\ula_|zx_keyboard_|keys[2][0]~q ))))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[2][0]~q ), - .datad(\ula_|zx_keyboard_|keys[2][1]~26_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][0]~80_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][0]~80 .lut_mask = 16'hB1F0; -defparam \ula_|zx_keyboard_|keys[2][0]~80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y20_N23 -dffeas \ula_|zx_keyboard_|keys[2][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[2][0]~80_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[2][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[2][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][0]~78 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][0]~78_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [0])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][0]~78_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][0]~78 .lut_mask = 16'h000A; -defparam \ula_|zx_keyboard_|keys[3][0]~78 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][0]~79 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][0]~79_combout = (\ula_|zx_keyboard_|keys[3][0]~78_combout & ((\ula_|zx_keyboard_|keys[3][1]~28_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[3][1]~28_combout & (\ula_|zx_keyboard_|keys[3][0]~q -// )))) # (!\ula_|zx_keyboard_|keys[3][0]~78_combout & (((\ula_|zx_keyboard_|keys[3][0]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[3][0]~78_combout ), - .datab(\ula_|zx_keyboard_|keys[3][1]~28_combout ), - .datac(\ula_|zx_keyboard_|keys[3][0]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][0]~79_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][0]~79 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[3][0]~79 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y20_N5 -dffeas \ula_|zx_keyboard_|keys[3][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[3][0]~79_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[3][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[3][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~1 ( -// Equation(s): -// \ula_|zx_keyboard_|key_row~1_combout = ((\z80_|address_pins_|DFFE_apin_latch [11]) # (!\ula_|zx_keyboard_|keys[3][0]~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\ula_|zx_keyboard_|keys[3][0]~q ), - .datad(\z80_|address_pins_|DFFE_apin_latch [11]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|key_row~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|key_row~1 .lut_mask = 16'hFF3F; -defparam \ula_|zx_keyboard_|key_row~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N4 -cycloneive_lcell_comb \D[0]~48 ( -// Equation(s): -// \D[0]~48_combout = (\D[0]~47_combout & (\ula_|zx_keyboard_|key_row~1_combout & ((\z80_|address_pins_|abus[10]~24_combout ) # (!\ula_|zx_keyboard_|keys[2][0]~q )))) - - .dataa(\D[0]~47_combout ), - .datab(\z80_|address_pins_|abus[10]~24_combout ), - .datac(\ula_|zx_keyboard_|keys[2][0]~q ), - .datad(\ula_|zx_keyboard_|key_row~1_combout ), - .cin(gnd), - .combout(\D[0]~48_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~48 .lut_mask = 16'h8A00; -defparam \D[0]~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~1 ( -// Equation(s): -// \ula_|zx_keyboard_|shifted~1_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [4]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|shifted~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|shifted~1 .lut_mask = 16'h0F00; -defparam \ula_|zx_keyboard_|shifted~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~90 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][0]~90_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][0]~90_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][0]~90 .lut_mask = 16'h0200; -defparam \ula_|zx_keyboard_|keys[6][0]~90 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~91 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][0]~91_combout = (\ula_|zx_keyboard_|shifted~1_combout & (\ula_|zx_keyboard_|keys[7][1]~23_combout & (\ula_|zx_keyboard_|keys[6][0]~90_combout & \ula_|ps2_keyboard_|shiftreg [1]))) - - .dataa(\ula_|zx_keyboard_|shifted~1_combout ), - .datab(\ula_|zx_keyboard_|keys[7][1]~23_combout ), - .datac(\ula_|zx_keyboard_|keys[6][0]~90_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][0]~91_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][0]~91 .lut_mask = 16'h8000; -defparam \ula_|zx_keyboard_|keys[6][0]~91 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~92 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][0]~92_combout = (\ula_|zx_keyboard_|keys[6][0]~91_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[6][0]~91_combout & ((\ula_|zx_keyboard_|keys[6][0]~q ))) - - .dataa(gnd), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[6][0]~q ), - .datad(\ula_|zx_keyboard_|keys[6][0]~91_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][0]~92_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][0]~92 .lut_mask = 16'h33F0; -defparam \ula_|zx_keyboard_|keys[6][0]~92 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y20_N21 -dffeas \ula_|zx_keyboard_|keys[6][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[6][0]~92_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[6][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[6][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y21_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~63 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][4]~63_combout = (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [0]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][4]~63_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][4]~63 .lut_mask = 16'h0F00; -defparam \ula_|zx_keyboard_|keys[5][4]~63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y21_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~3 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~3_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [2]) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~3 .lut_mask = 16'h0303; -defparam \ula_|zx_keyboard_|WideOr16~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y21_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~87 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][0]~87_combout = (\ula_|zx_keyboard_|keys[5][4]~63_combout & (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|WideOr16~3_combout ))) - - .dataa(\ula_|zx_keyboard_|keys[5][4]~63_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|WideOr16~3_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][0]~87_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][0]~87 .lut_mask = 16'h0800; -defparam \ula_|zx_keyboard_|keys[7][0]~87 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~132 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][0]~132_combout = (\ula_|zx_keyboard_|keys[3][0]~78_combout & (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [4]))) - - .dataa(\ula_|zx_keyboard_|keys[3][0]~78_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][0]~132_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][0]~132 .lut_mask = 16'h8000; -defparam \ula_|zx_keyboard_|keys[7][0]~132 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y21_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~88 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][0]~88_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|zx_keyboard_|keys[7][1]~23_combout & ((\ula_|zx_keyboard_|keys[7][0]~87_combout ) # (\ula_|zx_keyboard_|keys[7][0]~132_combout )))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [5]), - .datab(\ula_|zx_keyboard_|keys[7][1]~23_combout ), - .datac(\ula_|zx_keyboard_|keys[7][0]~87_combout ), - .datad(\ula_|zx_keyboard_|keys[7][0]~132_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][0]~88_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][0]~88 .lut_mask = 16'h8880; -defparam \ula_|zx_keyboard_|keys[7][0]~88 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~89 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][0]~89_combout = (\ula_|zx_keyboard_|keys[7][0]~88_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[7][0]~88_combout & (\ula_|zx_keyboard_|keys[7][0]~q )) - - .dataa(\ula_|zx_keyboard_|keys[7][0]~88_combout ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[7][0]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][0]~89_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][0]~89 .lut_mask = 16'h50FA; -defparam \ula_|zx_keyboard_|keys[7][0]~89 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y20_N7 -dffeas \ula_|zx_keyboard_|keys[7][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[7][0]~89_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[7][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[7][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N28 -cycloneive_lcell_comb \D[0]~50 ( -// Equation(s): -// \D[0]~50_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\z80_|address_pins_|abus[15]~22_combout ) # (!\ula_|zx_keyboard_|keys[7][0]~q )))) # (!\z80_|address_pins_|abus[14]~23_combout & (!\ula_|zx_keyboard_|keys[6][0]~q & -// ((\z80_|address_pins_|abus[15]~22_combout ) # (!\ula_|zx_keyboard_|keys[7][0]~q )))) - - .dataa(\z80_|address_pins_|abus[14]~23_combout ), - .datab(\ula_|zx_keyboard_|keys[6][0]~q ), - .datac(\z80_|address_pins_|abus[15]~22_combout ), - .datad(\ula_|zx_keyboard_|keys[7][0]~q ), - .cin(gnd), - .combout(\D[0]~50_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~50 .lut_mask = 16'hB0BB; -defparam \D[0]~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N10 -cycloneive_lcell_comb \D[0]~51 ( -// Equation(s): -// \D[0]~51_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[0]~49_combout & (\D[0]~48_combout & \D[0]~50_combout ))) - - .dataa(\D[0]~49_combout ), - .datab(\z80_|address_pins_|abus[0]~16_combout ), - .datac(\D[0]~48_combout ), - .datad(\D[0]~50_combout ), - .cin(gnd), - .combout(\D[0]~51_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~51 .lut_mask = 16'hECCC; -defparam \D[0]~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y16_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a24 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[0]~58_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_first_bit_number = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y14_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a16 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[0]~58_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_first_bit_number = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y13_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a0 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[0]~58_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N14 -cycloneive_lcell_comb \D[0]~55 ( -// Equation(s): -// \D[0]~55_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & -// ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout )) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & -// ((\ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ))))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ), - .cin(gnd), - .combout(\D[0]~55_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~55 .lut_mask = 16'hE3E0; -defparam \D[0]~55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y13_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a8 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[0]~58_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N22 -cycloneive_lcell_comb \D[0]~56 ( -// Equation(s): -// \D[0]~56_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[0]~55_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout )) # (!\D[0]~55_combout & -// ((\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ))))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[0]~55_combout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\D[0]~55_combout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ), - .cin(gnd), - .combout(\D[0]~56_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~56 .lut_mask = 16'hBCB0; -defparam \D[0]~56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y28_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a0 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[0]~58_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_bit_number = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF0000000000000000000000003FF03FFC20107FFC3FF00B9C3FF007FC18000FFC3FF03FD42FF43FFC2FFC3FE01FFE7FE81FFE3FDC07FE3FFC07FE2FFC07FE0F0807FE1F18207F0F3030FD8C30383300600000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h000000000000000000000000FFFFFFFFE0408103E004044390120EAA803920C6000000000000000000000000FFFFFFFFE0408103A004005A84723CEA813930C2000000000000000000000000800000009FBF7EFD8004027A8572358A813950EA000000000000000000000000800000009FBF7EFC8005157A85733F0A8139518E0000000000000000000000009FBF7EFC800000008006113A8C73330A813919EA0000000000000000000000009FBF7EFC8000000080060022801333A2813973EA00000000000000000000000080000000DFFFFFFD9FF6022A84730366801913FE000000000000000000000000E0408102FFFFFFFD9FF60ABA84730426901913EE; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h9FF81326887812F28FF0D7C2CC6856E3894C8B62980099E28988BFC2B9EC79829FE81362887842E68FF0C7C2CCE056E2896C89E2888098E28AA8BBC299FC1AC280081372887842E69EE0C7CA8CE046E289E089E289C899E28AA8BEC2993C1AE28008837E882852C69EE0874288E046E2886099E289689FCE8AD8BFC2999C09F680088376880846C69CA88382880042A289D08DE289F098C28AF8BFC289FC88F280088376880857C29CA893C2888043A289508DE288F0D9428BF0AFC289F4888A800883F2880857829C2891C3889047F2898885E2899081428990AF8289FC8BE3800893F6880847C2DC0894E389944F62888899668918914289803582CB8C8AF3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'hCBAC80F38DA845828DF44582840124029375A4A288D108A2FFFFFFFDE0408082CAEC80968DF855828CE4408284012006917194C280510B82DFFFFFFC8000000288EC84A28FFC4586880C648A860124128179900280510F82800000009FBF7F7C8BA080BA8FEC40828808618286012C028179901280510702800000009FBF7F7C8BB081BA8CAC408289E0618286812C1281791002805007029FBF7F7C8000000089B881828CB440828BE07782868322028139909280400F029FBF7F7D8000000089A4C3928FF444828A00260A8792227281199022A0001F03E0408081FFFFFFFF89A0C1928FD440828800260687B720C280199002E0001F03E0408083FFFFFFFF; -// synopsys translate_on - -// Location: M9K_X22_Y30_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a8 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h3C00000000000000000000000000000000000000000000000000000000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005DB824E17CAAE881C1908A79F24B7D1B4857A981A6AF39DFF5A2FEE9141EB33592D8E9B82471FDDA6791810A1C29D415CC1A8FA03444DF0083F83506BA93E8D1A1856A768D73A08418BFB25A40001DD4833DAF33BD311BB45F39667627407EF59ED569C483EB3BE1B10551B1428A6169579293ED063CAA9C6ADB0433CFC15C33AFF04C710408C20AC28B5909A229CD7D1DB4EB9A44CE0EEDBBBD391D3128AAA3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'hDDE6FC8EBE3F9F3C3DFC6E8F07BFD31D50660B1E0B2506A533CE0E340C7C745CAEC4837C2A5FECBB94C1C969FFDDFF79BFFAAFDCA8D748399ABF75558ADD02F56F6DFFF29CB70FFD25A59DFFFED7B3F7E8B4CE6FFF3EF9CEC6BAE57ABFFFCEE647B2AFF5B87AA26AFFDD317DEDCFBDFFE1A0CAD3B58877DD2F647F7DF748E7CF4693FD3C1238FFAFBD7FDF567FA8FEF024F33AFD3AABC6B105EA80272D64895FFF9FFF6E3881C81AFDCF2257FD4F8ED5257D0E9B800726B6564D2B05012F76DF636CDEB4BDFCAEEFC61DFFEFB7E26262DEF2CB9F71565824FEBF3F7BDDEABB593F1BF746FBFFC353E37263FF38A796EF39E3FD7DFEBA7FFEFFBD97ABAF09E909; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'hE629BDF93D7F5B5BAF92FBAB477E9B315DB5A310CFACC7408DF9A544B1E57AF6EFEF92C2FA4D8D4E4AC86C277338FA37BCDD9D47782DB75EFF80781BCD23D0AFCAE30B9FE6AA29FFF6F72DA73DFE4F7ACD39687B9E69C5359E9B991F0246EFFBC5595561AC64787878F5CE14C664CF9EB0CDAFFBABEF1E83358371B9ED96E5069555AFBBD3AEBFCABFBBED7A5C5FE9BD0E6A91C6E7610042695EEB08D8881B1D735AF87DAE59FABBD7DEAF8717F2B72F428F5E37E5D6E13157B99CBD2D73B9C73C563C8B02C8CC39C64DDCEA1BEEB5E7353F93786145598FE634EF1000179B345725EA43CE18F187A1DE4DAABEA97963E3A7A96B8B7CBC095BEB7CE46274D9AF; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h4ED4AE2B1650D21EAFE01E7099EFCA3094FD4D705CF6B84AE21583E13385F8650004406BD60A023AB063D4E5966EA41AA997F5A49BFCB0657A9732D28EB8217E65F627A15E1057ADEE7B9E27122A58FB2B98B1EA560390C7E87715861814E04DCB76FAB179E9619BC7E7E9C9FD801CF87DBA1EA496E829D4E62861E1AF436A7585287860729C77B6C68CAEA3033A6E84D67249B594C407B39C68B4C1C97FDEFC6BAD12FDBB525EF4F87F4A23EC13CBC0262D8899A3A290F04F41C1324045B9FCEEC890579E95D5A0A546CCCDD48577558ABE7CA36EF67A70F6A8758BDA052D5B95DE707778B17C2379847A23AE5D4BB01F36F3F44A8162566D9FB15DE7CC83F7; -// synopsys translate_on - -// Location: M9K_X22_Y27_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a8 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(gnd), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[0]~58_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_first_bit_number = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N4 -cycloneive_lcell_comb \D[0]~52 ( -// Equation(s): -// \D[0]~52_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\z80_|address_pins_|abus[14]~23_combout & ((\ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ))) # (!\z80_|address_pins_|abus[14]~23_combout & -// (\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\z80_|address_pins_|abus[14]~23_combout )))) - - .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ), - .datac(\z80_|address_pins_|abus[14]~23_combout ), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ), - .cin(gnd), - .combout(\D[0]~52_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~52 .lut_mask = 16'hF858; -defparam \D[0]~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y20_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a0 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h1EEA3633EFEA856D05BA968C1B3C30CA1788DD95D16B8F914DDDFC3EE5C69945DF7D7BF31C6072BFA7993996AB7DD2F3EE4009844CC9D6CF9E583AEC48A52F2904B57D8E0D755851232838F9B5348838530D7AF95411555D263B8CA86A5D29D7CE4B65409D6F04C5709A56C241C3BCEF07459A416EB4E8F3D73CC714F4333AFE605D53A5C955D5D1412F8361617A54446971FD187442A60FB04457857BECC3120A01FDC7FE2CBF038A61DEE5FCE2D10C8F35FBF80C05ABFF4B6935287B125E8D56F9FDFE7D64C1F4E1F5641845CD17E836B97780400C702523FA8E7C7BBD6F0666591A35ADD26B6B7E33CA56E9AB329EFA7E68F98AE7CE9507755C74C430286A; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h88537A811D4EF6CD9668CCD3E2E7A8041788DCA5F7E08AF52AF5276078304DEB75B74BB9AC3C1A492952F7EEAA0E7CF9FBEDD0FB47EEFDCC3734B816F355C913CD2E1AF14C30545297A91BED3AEAEFF8F696B5F4FC80BC6B1A2559492E9198E4A5875745B625C6CA7A7292332492D139728A689DA1AE78B6B44CE4F4A4EA5A22F331598B364EF27516CC49A4662C5E5C92ED140D96373678F833AE434698237599716B8CBAE2D3D061F2C3D6337AB435B5C2144AB6FA2F8BB51357801066B6589467DA6C480E6D19CEEA8451CEFA88FD70E7925B0302F877F87FA833FBD147E937309C08305A10187707E3D57DDE4931F1D9E97A8F378981ABBF8D7B6B7539C3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h763DD7AA7EED3F4AD4EA7491ADE6F14E6DBADD0F090A8DF34D7BAD35DD2275F0BCCF19EEF299751C919C9C13C6FB9ED711AC4DA7D947CC79E9B6323EF6CE62638CEBCB187AE5D44ECA689C9BD4E5AE544DEA7E90D186B9F335F3323877AAD54196CE81973CB555904419599375501366EC343561BCF83357F8823671393B278C1C387A7970C7F3E688673CF5975EE3E5FF105CFCCFAB725D698FB088B063063C7833830C7B2C7AFB8A8D203C312306DA0E72641FFB93D59B5EC84F44AD55F4B884735325ACC969B2EAE10A1478D866F667DDEF7BBF75E6958B6D02DC6D0F807660A229B98541E6FE734DE2280A9B57FCD5A9BEFEF7CDA5ABEB44FD73D2794D56; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'hD0734B461A36980411EB2A6C1BE76029258777EF227A8F6E84F74C4436098F67BA611013110188547995B108BB2DAE76F423A0D98845F9248BDFA45E10CA403A5E2B1A3E16869E1D37BCE906B82F401CBD467617DB34D9E0C80B5E6E10063EC4BD52921D249E377D95CFAAA309EEDAA57DA85F55DBB7048A69A4C801013948B617F7F5724D40707E6FF30002982023020449B4680C45D1CE6D8EB30A061DB8FEDD6E630C15271E48CA801988654FB501D5393392EE765C1EC95C1E4D86F18A965372B72B484E2F2664B735B69A5AB532B086BA4C62AD6D56EECBDB6984B251454845BD5B243DAED2B2489B313A35C50252AFD3E0B76FEF342335C7F1321D92FF; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N28 -cycloneive_lcell_comb \D[0]~53 ( -// Equation(s): -// \D[0]~53_combout = (\z80_|address_pins_|abus[15]~22_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout $ ((\D[0]~52_combout )))) # (!\z80_|address_pins_|abus[15]~22_combout & (((!\D[0]~52_combout & -// \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ), - .datab(\z80_|address_pins_|abus[15]~22_combout ), - .datac(\D[0]~52_combout ), - .datad(\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ), - .cin(gnd), - .combout(\D[0]~53_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~53 .lut_mask = 16'h4B48; -defparam \D[0]~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N16 -cycloneive_lcell_comb \D[0]~54 ( -// Equation(s): -// \D[0]~54_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[0]~52_combout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[0]~52_combout & -// (\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout & !\D[0]~53_combout )) # (!\D[0]~52_combout & ((\D[0]~53_combout ))))) - - .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\D[0]~52_combout ), - .datad(\D[0]~53_combout ), - .cin(gnd), - .combout(\D[0]~54_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~54 .lut_mask = 16'hC3E0; -defparam \D[0]~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N8 -cycloneive_lcell_comb \D[0]~106 ( -// Equation(s): -// \D[0]~106_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\D[0]~56_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\D[0]~54_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & -// (\D[0]~56_combout )))) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\D[0]~56_combout ), - .datad(\D[0]~54_combout ), - .cin(gnd), - .combout(\D[0]~106_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~106 .lut_mask = 16'hF4B0; -defparam \D[0]~106 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N14 -cycloneive_lcell_comb \D[0]~57 ( -// Equation(s): -// \D[0]~57_combout = ((\Equal2~0_combout & (\D[0]~51_combout )) # (!\Equal2~0_combout & ((\D[0]~106_combout )))) # (!\Equal2~1_combout ) - - .dataa(\Equal2~1_combout ), - .datab(\D[0]~51_combout ), - .datac(\D[0]~106_combout ), - .datad(\Equal2~0_combout ), - .cin(gnd), - .combout(\D[0]~57_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~57 .lut_mask = 16'hDDF5; -defparam \D[0]~57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N0 -cycloneive_lcell_comb \D[0]~58 ( -// Equation(s): -// \D[0]~58_combout = (\D[0]~57_combout & (((\z80_|data_pins_|dout [0]) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) # (!\D[0]~57_combout & (!\Equal2~1_combout & ((!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) - - .dataa(\Equal2~1_combout ), - .datab(\z80_|data_pins_|dout [0]), - .datac(\D[0]~57_combout ), - .datad(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .cin(gnd), - .combout(\D[0]~58_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~58 .lut_mask = 16'hC0F5; -defparam \D[0]~58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N0 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [0] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[0]~17_combout ) # ((\z80_|pin_control_|bus_db_pin_re~combout & \D[0]~58_combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & -// (((\z80_|pin_control_|bus_db_pin_re~combout & \D[0]~58_combout )))) - - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(\z80_|bus_control_|db[0]~17_combout ), - .datac(\z80_|pin_control_|bus_db_pin_re~combout ), - .datad(\D[0]~58_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [0]), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] .lut_mask = 16'hF888; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y13_N1 -dffeas \z80_|data_pins_|dout[0] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [0]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|data_pins_|dout [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|data_pins_|dout[0] .is_wysiwyg = "true"; -defparam \z80_|data_pins_|dout[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N4 -cycloneive_lcell_comb \z80_|bus_control_|db[0]~16 ( -// Equation(s): -// \z80_|bus_control_|db[0]~16_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [0]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) - - .dataa(gnd), - .datab(\z80_|bus_control_|db[0]~4_combout ), - .datac(\z80_|data_pins_|dout [0]), - .datad(\z80_|execute_|ctl_bus_db_oe~combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[0]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[0]~16 .lut_mask = 16'hC0CC; -defparam \z80_|bus_control_|db[0]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N28 -cycloneive_lcell_comb \z80_|bus_control_|db[0]~17 ( -// Equation(s): -// \z80_|bus_control_|db[0]~17_combout = ((\z80_|bus_control_|db[0]~16_combout & ((\z80_|alu_control_|db[0]~12_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - - .dataa(\z80_|bus_control_|db[0]~6_combout ), - .datab(\z80_|alu_control_|db[0]~12_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|bus_control_|db[0]~16_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[0]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[0]~17 .lut_mask = 16'hDF55; -defparam \z80_|bus_control_|db[0]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y13_N27 -dffeas \z80_|ir_|opcode[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|bus_control_|db[0]~17_combout ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|ir_|opcode [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|ir_|opcode[0] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal63~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal63~0_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [5] & (\z80_|execute_|comb~0_combout & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|execute_|comb~0_combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal63~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal63~0 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal63~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_daa ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_sel_daa~combout = (!\z80_|ir_|opcode [4] & (!\z80_|ir_|opcode [3] & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal63~0_combout ))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal63~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_sel_daa .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_flags_cf2_sel_daa .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N20 -cycloneive_lcell_comb \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 ( -// Equation(s): -// \z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout = (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )) # (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ))) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 .lut_mask = 16'h070F; -defparam \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N22 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~10 ( -// Equation(s): -// \z80_|alu_control_|db[6]~10_combout = ((\z80_|execute_|ctl_sw_2u~7_combout ) # (\z80_|execute_|ctl_flags_oe~2_combout )) # (!\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ) - - .dataa(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_sw_2u~7_combout ), - .datad(\z80_|execute_|ctl_flags_oe~2_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~10 .lut_mask = 16'hFFF5; -defparam \z80_|alu_control_|db[6]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N28 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~11 ( -// Equation(s): -// \z80_|alu_control_|db[6]~11_combout = (\z80_|alu_control_|db[6]~10_combout ) # ((\z80_|execute_|ctl_sw_1d~7_combout ) # (\z80_|execute_|ctl_reg_out_lo~8_combout )) - - .dataa(\z80_|alu_control_|db[6]~10_combout ), - .datab(\z80_|execute_|ctl_sw_1d~7_combout ), - .datac(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~11 .lut_mask = 16'hFEFE; -defparam \z80_|alu_control_|db[6]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N18 -cycloneive_lcell_comb \z80_|alu_control_|db[4]~30 ( -// Equation(s): -// \z80_|alu_control_|db[4]~30_combout = (\z80_|alu_|db[4]~17_combout & (\z80_|execute_|ctl_reg_out_lo~8_combout & (!\z80_|reg_file_|gdfx_temp0[4]~62_combout ))) # (!\z80_|alu_|db[4]~17_combout & ((\z80_|execute_|ctl_sw_2u~7_combout ) # -// ((\z80_|execute_|ctl_reg_out_lo~8_combout & !\z80_|reg_file_|gdfx_temp0[4]~62_combout )))) - - .dataa(\z80_|alu_|db[4]~17_combout ), - .datab(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .datad(\z80_|execute_|ctl_sw_2u~7_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[4]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[4]~30 .lut_mask = 16'h5D0C; -defparam \z80_|alu_control_|db[4]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N24 -cycloneive_lcell_comb \z80_|alu_control_|db[4]~31 ( -// Equation(s): -// \z80_|alu_control_|db[4]~31_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & (!\z80_|alu_control_|db[4]~30_combout & ((\z80_|alu_flags_|flags_hf~combout ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) - - .dataa(\z80_|alu_flags_|flags_hf~combout ), - .datab(\z80_|execute_|ctl_flags_oe~2_combout ), - .datac(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .datad(\z80_|alu_control_|db[4]~30_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[4]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[4]~31 .lut_mask = 16'h00B0; -defparam \z80_|alu_control_|db[4]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N6 -cycloneive_lcell_comb \z80_|alu_control_|db[4]~32 ( -// Equation(s): -// \z80_|alu_control_|db[4]~32_combout = ((\z80_|alu_control_|db[4]~31_combout & ((\z80_|bus_control_|db[4]~19_combout ) # (!\z80_|execute_|ctl_sw_1d~7_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|bus_control_|db[4]~19_combout ), - .datab(\z80_|alu_control_|db[6]~11_combout ), - .datac(\z80_|execute_|ctl_sw_1d~7_combout ), - .datad(\z80_|alu_control_|db[4]~31_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[4]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[4]~32 .lut_mask = 16'hBF33; -defparam \z80_|alu_control_|db[4]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~119 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][4]~119_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [2]))) # (!\ula_|ps2_keyboard_|shiftreg [0] & -// (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [2]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [0]), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][4]~119_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][4]~119 .lut_mask = 16'h0420; -defparam \ula_|zx_keyboard_|keys[2][4]~119 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~120 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][4]~120_combout = (\ula_|zx_keyboard_|keys[5][1]~36_combout & (\ula_|zx_keyboard_|keys[2][4]~119_combout & (\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [1]))) - - .dataa(\ula_|zx_keyboard_|keys[5][1]~36_combout ), - .datab(\ula_|zx_keyboard_|keys[2][4]~119_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][4]~120_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][4]~120 .lut_mask = 16'h0080; -defparam \ula_|zx_keyboard_|keys[2][4]~120 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~95 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][4]~95_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [6])) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|shifted~q ), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][4]~95_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][4]~95 .lut_mask = 16'hAFAA; -defparam \ula_|zx_keyboard_|keys[2][4]~95 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~121 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][4]~121_combout = (\ula_|zx_keyboard_|keys[2][4]~120_combout & ((!\ula_|zx_keyboard_|keys[2][4]~95_combout ))) # (!\ula_|zx_keyboard_|keys[2][4]~120_combout & (\ula_|zx_keyboard_|keys[2][4]~q )) - - .dataa(\ula_|zx_keyboard_|keys[2][4]~120_combout ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[2][4]~q ), - .datad(\ula_|zx_keyboard_|keys[2][4]~95_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][4]~121_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][4]~121 .lut_mask = 16'h50FA; -defparam \ula_|zx_keyboard_|keys[2][4]~121 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y18_N23 -dffeas \ula_|zx_keyboard_|keys[2][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[2][4]~121_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[2][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[2][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~117 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][4]~117_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|zx_keyboard_|extended~q ))) # (!\ula_|ps2_keyboard_|shiftreg [2] & -// (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|zx_keyboard_|extended~q ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|zx_keyboard_|extended~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][4]~117_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][4]~117 .lut_mask = 16'h4002; -defparam \ula_|zx_keyboard_|keys[3][4]~117 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~136 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][4]~136_combout = (\ula_|zx_keyboard_|keys[3][4]~117_combout & (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [4]))) - - .dataa(\ula_|zx_keyboard_|keys[3][4]~117_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][4]~136_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][4]~136 .lut_mask = 16'h0080; -defparam \ula_|zx_keyboard_|keys[3][4]~136 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y21_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~130 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][4]~130_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (!\ula_|zx_keyboard_|Equal0~1_combout & (!\ula_|ps2_keyboard_|shiftreg [7] & \ula_|ps2_keyboard_|shiftreg [5]))) - - .dataa(\ula_|ps2_keyboard_|scan_code_ready~q ), - .datab(\ula_|zx_keyboard_|Equal0~1_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [7]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][4]~130_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][4]~130 .lut_mask = 16'h0200; -defparam \ula_|zx_keyboard_|keys[3][4]~130 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~118 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][4]~118_combout = (\ula_|zx_keyboard_|keys[3][4]~136_combout & ((\ula_|zx_keyboard_|keys[3][4]~130_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][4]~130_combout & ((\ula_|zx_keyboard_|keys[3][4]~q -// ))))) # (!\ula_|zx_keyboard_|keys[3][4]~136_combout & (((\ula_|zx_keyboard_|keys[3][4]~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[3][4]~136_combout ), - .datac(\ula_|zx_keyboard_|keys[3][4]~q ), - .datad(\ula_|zx_keyboard_|keys[3][4]~130_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][4]~118_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][4]~118 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[3][4]~118 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y18_N9 -dffeas \ula_|zx_keyboard_|keys[3][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[3][4]~118_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[3][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[3][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N18 -cycloneive_lcell_comb \D[4]~78 ( -// Equation(s): -// \D[4]~78_combout = (\z80_|address_pins_|abus[11]~19_combout & ((\z80_|address_pins_|abus[10]~24_combout ) # ((!\ula_|zx_keyboard_|keys[2][4]~q )))) # (!\z80_|address_pins_|abus[11]~19_combout & (!\ula_|zx_keyboard_|keys[3][4]~q & -// ((\z80_|address_pins_|abus[10]~24_combout ) # (!\ula_|zx_keyboard_|keys[2][4]~q )))) - - .dataa(\z80_|address_pins_|abus[11]~19_combout ), - .datab(\z80_|address_pins_|abus[10]~24_combout ), - .datac(\ula_|zx_keyboard_|keys[2][4]~q ), - .datad(\ula_|zx_keyboard_|keys[3][4]~q ), - .cin(gnd), - .combout(\D[4]~78_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~78 .lut_mask = 16'h8ACF; -defparam \D[4]~78 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~126 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][4]~126_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[7][1]~23_combout & (\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [6]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|zx_keyboard_|keys[7][1]~23_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][4]~126_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][4]~126 .lut_mask = 16'h0040; -defparam \ula_|zx_keyboard_|keys[6][4]~126 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~128 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][4]~128_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [1]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][4]~128_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][4]~128 .lut_mask = 16'h0080; -defparam \ula_|zx_keyboard_|keys[5][4]~128 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~129 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][4]~129_combout = (\ula_|zx_keyboard_|keys[6][4]~126_combout & ((\ula_|zx_keyboard_|keys[5][4]~128_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[5][4]~128_combout & -// (\ula_|zx_keyboard_|keys[5][4]~q )))) # (!\ula_|zx_keyboard_|keys[6][4]~126_combout & (((\ula_|zx_keyboard_|keys[5][4]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[6][4]~126_combout ), - .datab(\ula_|zx_keyboard_|keys[5][4]~128_combout ), - .datac(\ula_|zx_keyboard_|keys[5][4]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][4]~129_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][4]~129 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[5][4]~129 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y19_N9 -dffeas \ula_|zx_keyboard_|keys[5][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[5][4]~129_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[5][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[5][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~127 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][4]~127_combout = (\ula_|zx_keyboard_|keys[6][4]~126_combout & ((\ula_|zx_keyboard_|keys[6][4]~20_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[6][4]~20_combout & ((\ula_|zx_keyboard_|keys[6][4]~q -// ))))) # (!\ula_|zx_keyboard_|keys[6][4]~126_combout & (((\ula_|zx_keyboard_|keys[6][4]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[6][4]~126_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[6][4]~q ), - .datad(\ula_|zx_keyboard_|keys[6][4]~20_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][4]~127_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][4]~127 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[6][4]~127 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y20_N5 -dffeas \ula_|zx_keyboard_|keys[6][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[6][4]~127_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[6][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[6][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~2 ( -// Equation(s): -// \ula_|zx_keyboard_|Equal0~2_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [0])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|Equal0~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|Equal0~2 .lut_mask = 16'h0050; -defparam \ula_|zx_keyboard_|Equal0~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~51 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][4]~51_combout = (\ula_|zx_keyboard_|keys[7][1]~23_combout & (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [1] & \ula_|zx_keyboard_|Equal0~2_combout ))) - - .dataa(\ula_|zx_keyboard_|keys[7][1]~23_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|zx_keyboard_|Equal0~2_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][4]~51_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][4]~51 .lut_mask = 16'h2000; -defparam \ula_|zx_keyboard_|keys[7][4]~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~125 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][4]~125_combout = (\ula_|zx_keyboard_|shifted~1_combout & ((\ula_|zx_keyboard_|keys[7][4]~51_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[7][4]~51_combout & ((\ula_|zx_keyboard_|keys[7][4]~q ))))) -// # (!\ula_|zx_keyboard_|shifted~1_combout & (((\ula_|zx_keyboard_|keys[7][4]~q )))) - - .dataa(\ula_|zx_keyboard_|shifted~1_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[7][4]~q ), - .datad(\ula_|zx_keyboard_|keys[7][4]~51_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][4]~125_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][4]~125 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[7][4]~125 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y20_N11 -dffeas \ula_|zx_keyboard_|keys[7][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[7][4]~125_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[7][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[7][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N30 -cycloneive_lcell_comb \D[4]~79 ( -// Equation(s): -// \D[4]~79_combout = (\z80_|address_pins_|abus[15]~22_combout & ((\z80_|address_pins_|abus[14]~23_combout ) # ((!\ula_|zx_keyboard_|keys[6][4]~q )))) # (!\z80_|address_pins_|abus[15]~22_combout & (!\ula_|zx_keyboard_|keys[7][4]~q & -// ((\z80_|address_pins_|abus[14]~23_combout ) # (!\ula_|zx_keyboard_|keys[6][4]~q )))) - - .dataa(\z80_|address_pins_|abus[15]~22_combout ), - .datab(\z80_|address_pins_|abus[14]~23_combout ), - .datac(\ula_|zx_keyboard_|keys[6][4]~q ), - .datad(\ula_|zx_keyboard_|keys[7][4]~q ), - .cin(gnd), - .combout(\D[4]~79_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~79 .lut_mask = 16'h8ACF; -defparam \D[4]~79 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~122 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][4]~122_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|zx_keyboard_|extended~q )) # (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [6] & -// \ula_|zx_keyboard_|extended~q )) - - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(gnd), - .datad(\ula_|zx_keyboard_|extended~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][4]~122_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][4]~122 .lut_mask = 16'h4422; -defparam \ula_|zx_keyboard_|keys[4][4]~122 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~123 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][4]~123_combout = (\ula_|zx_keyboard_|Equal0~2_combout & (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[4][4]~122_combout ))) - - .dataa(\ula_|zx_keyboard_|Equal0~2_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|keys[4][4]~122_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][4]~123_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][4]~123 .lut_mask = 16'h8000; -defparam \ula_|zx_keyboard_|keys[4][4]~123 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~124 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][4]~124_combout = (\ula_|zx_keyboard_|keys[0][0]~15_combout & ((\ula_|zx_keyboard_|keys[4][4]~123_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[4][4]~123_combout & ((\ula_|zx_keyboard_|keys[4][4]~q -// ))))) # (!\ula_|zx_keyboard_|keys[0][0]~15_combout & (((\ula_|zx_keyboard_|keys[4][4]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[4][4]~q ), - .datad(\ula_|zx_keyboard_|keys[4][4]~123_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][4]~124_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][4]~124 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[4][4]~124 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y19_N25 -dffeas \ula_|zx_keyboard_|keys[4][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[4][4]~124_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[4][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[4][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~3 ( -// Equation(s): -// \ula_|zx_keyboard_|key_row~3_combout = ((\z80_|address_pins_|DFFE_apin_latch [12]) # (!\ula_|zx_keyboard_|keys[4][4]~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [12]), - .datad(\ula_|zx_keyboard_|keys[4][4]~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|key_row~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|key_row~3 .lut_mask = 16'hF3FF; -defparam \ula_|zx_keyboard_|key_row~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N8 -cycloneive_lcell_comb \D[4]~80 ( -// Equation(s): -// \D[4]~80_combout = (\D[4]~79_combout & (\ula_|zx_keyboard_|key_row~3_combout & ((\z80_|address_pins_|abus[13]~20_combout ) # (!\ula_|zx_keyboard_|keys[5][4]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[5][4]~q ), - .datab(\D[4]~79_combout ), - .datac(\z80_|address_pins_|abus[13]~20_combout ), - .datad(\ula_|zx_keyboard_|key_row~3_combout ), - .cin(gnd), - .combout(\D[4]~80_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~80 .lut_mask = 16'hC400; -defparam \D[4]~80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~111 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][4]~111_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [6])) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|shifted~q ), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][4]~111_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][4]~111 .lut_mask = 16'hFAAA; -defparam \ula_|zx_keyboard_|keys[0][4]~111 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~97 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][4]~97_combout = (\ula_|zx_keyboard_|keys[5][1]~36_combout & (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [6] $ (\ula_|ps2_keyboard_|shiftreg [5])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|zx_keyboard_|keys[5][1]~36_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][4]~97_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][4]~97 .lut_mask = 16'h0060; -defparam \ula_|zx_keyboard_|keys[0][4]~97 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~116 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][4]~116_combout = (\ula_|zx_keyboard_|keys[3][1]~29_combout & ((\ula_|zx_keyboard_|keys[0][4]~97_combout & (!\ula_|zx_keyboard_|keys[0][4]~111_combout )) # (!\ula_|zx_keyboard_|keys[0][4]~97_combout & -// ((\ula_|zx_keyboard_|keys[0][4]~q ))))) # (!\ula_|zx_keyboard_|keys[3][1]~29_combout & (((\ula_|zx_keyboard_|keys[0][4]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[3][1]~29_combout ), - .datab(\ula_|zx_keyboard_|keys[0][4]~111_combout ), - .datac(\ula_|zx_keyboard_|keys[0][4]~q ), - .datad(\ula_|zx_keyboard_|keys[0][4]~97_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][4]~116_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][4]~116 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[0][4]~116 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y18_N11 -dffeas \ula_|zx_keyboard_|keys[0][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[0][4]~116_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[0][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[0][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][4]~115 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][4]~115_combout = (\ula_|zx_keyboard_|Equal0~2_combout & ((\ula_|zx_keyboard_|keys[1][4]~25_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[1][4]~25_combout & (\ula_|zx_keyboard_|keys[1][4]~q )))) # -// (!\ula_|zx_keyboard_|Equal0~2_combout & (((\ula_|zx_keyboard_|keys[1][4]~q )))) - - .dataa(\ula_|zx_keyboard_|Equal0~2_combout ), - .datab(\ula_|zx_keyboard_|keys[1][4]~25_combout ), - .datac(\ula_|zx_keyboard_|keys[1][4]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][4]~115_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][4]~115 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[1][4]~115 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y19_N7 -dffeas \ula_|zx_keyboard_|keys[1][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[1][4]~115_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[1][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[1][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N28 -cycloneive_lcell_comb \D[4]~77 ( -// Equation(s): -// \D[4]~77_combout = (\z80_|address_pins_|abus[9]~17_combout & ((\z80_|address_pins_|abus[8]~18_combout ) # ((!\ula_|zx_keyboard_|keys[0][4]~q )))) # (!\z80_|address_pins_|abus[9]~17_combout & (!\ula_|zx_keyboard_|keys[1][4]~q & -// ((\z80_|address_pins_|abus[8]~18_combout ) # (!\ula_|zx_keyboard_|keys[0][4]~q )))) - - .dataa(\z80_|address_pins_|abus[9]~17_combout ), - .datab(\z80_|address_pins_|abus[8]~18_combout ), - .datac(\ula_|zx_keyboard_|keys[0][4]~q ), - .datad(\ula_|zx_keyboard_|keys[1][4]~q ), - .cin(gnd), - .combout(\D[4]~77_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~77 .lut_mask = 16'h8ACF; -defparam \D[4]~77 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N26 -cycloneive_lcell_comb \D[4]~81 ( -// Equation(s): -// \D[4]~81_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[4]~78_combout & (\D[4]~80_combout & \D[4]~77_combout ))) - - .dataa(\z80_|address_pins_|abus[0]~16_combout ), - .datab(\D[4]~78_combout ), - .datac(\D[4]~80_combout ), - .datad(\D[4]~77_combout ), - .cin(gnd), - .combout(\D[4]~81_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~81 .lut_mask = 16'hEAAA; -defparam \D[4]~81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y1_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a12 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'hA50276000854A0103840403E540424244404783E18807A08A47C54484448544A807E7E10005270182040407E4A1252124208084008404208420A4A42424A125A024428106448524A624A4A24425242522060108010543C00044A105424005E0031ED1E0529E507AE2F6FF1CD51D4C772A648E65F6532C28022061303F06C36CDBD319B55CB8E626C20E46C93C1463A0B1CE594F0ED3B62330C104DECE46CA6CD966B1386612C7B43980349408F36FB64C14342DAE26CE4D8D5E791388729D743B09A27AB81D71A14AB3D24E385B602248476D00249239514B58D3098504ACD119B99E9021B650A69494C22600667473128DA5010D2195982823226DED0ADFCB8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h5861917919344A4685CC0990862A11324792E761B6D41C0FCC0838C1C27211A2453FDC2219C225E421B320085A8FBFD0C42135B16448DFC226E09B3438A740C352979565817114DE46462844A57F7958873FC4B255C8AE549BDD1A87415D5018F88D5002628FFD13203066C850F10649F21319109208387641120B362124803F0678522BA2812C1454A502ED1A59CBD76A034756F5765DF7555F57575F7F57FFFF7FFF7D5712524D4A30723514B2B3064A84B4742D48415281863DDFAA9D9B7E7BB16DDB96B7845371C30B55DB96C8F6EB4B453242FF6A4DF84A76B5AEDC88A68DC6A06905054C8C36E4199E74638E6532965218A965909BA456000451343351; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'hE2975A2686A7AE0288F140141B698E2A82A835F478453A1D722CFCED12859FD735188757AC5A42DEB501FE010586249AC1EA60D08F74CFA5086EC78FC9190C056059E332C311521E6522901852D484B423A98816C9B26A08C92368E9FF05524502288A804612A2A0A102A418CBDFBA554499541660F8124640110101263142892A086B442661015380041594608092D9CB919250100A37DDA3919A1427F660963C251301FB2CA45562245308885131119115C652B2493252340201101942D26000CC60799124A8520C08050122171281808058018C38A645D07931896B39ED259A22242CB58413089465B246231330D806105010035100B08761A08506094160; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h1228D91C352915424000000AA0088F63153A8AD81B945C8789F01C86548D12CEAB6AA38578BD55CEC9AA28082C285B8C0201104838AD502AC160C13C70620B818249144AB52CED94200A0202A885100E0D938A30A34512C0CEC98F08A98900F2093E11673256B3169C12284980E92A034141E0782507800F8100009C403C07867000000030082004A17800828F090A0C318CE120012172286317922341A2A12840B6C18040682080125C75401AEC44E8C01A8D40D1412B25A09F7600B0C6FEC65BFE5CE861A20F71E8032916A78F29CC546518461522E4E14998DD54BC0E40B64B710C9DC948F06010DF01D880E2044BE8854062D10DD93F30A62AA7FD227C4C; -// synopsys translate_on - -// Location: M9K_X22_Y22_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a12 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(gnd), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[4]~98_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_first_bit_number = 4; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y3_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a4 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h35861A00A6112A1481AF1A50A6004A05291627227FF08229B87389E08119A28A7888672DC999B7046A61E60810A7434450E3D33E330F321A18E8A120D1EDC8623DA2C64840C2CCE811522B42008095E5A456C98F4B25EAEA410610545024640CF10410AC463BF9349074917E9A74A12830EFA280EBD3131E484A255D0191C6852730A263DBCCAAA88712242B3BE49AA5338990229B391158C726BC7EB4ECC32308980020680249882691A680488292310B4313CE87FFCD5329A64B708CAC8533316412C4900F646A36630261DA093053D98F19D2C5B653165D4A71AA5682B29B89B6054CC727D292805705A93268676A31111371390B240EC3CC85D331813EB1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h1AA1C248D293110CB951445117D9B6AA500F65068B8CC508BD00184F8705B010A0CC46CC9302649242CE08191634113154562B149100204551178DE805D98EC8A2E5A64B241400267194CD524499BC01D31058CD18684A817A5800B65143281C1310B00A49902C0104004C654E0582040001103654011012021912281216B000C653A0510A1B00C36AC88058CAC126E14E198DFB07E81C3F41510BB08F8F851C3B9AF0147BC1F730B4E91D9D11C3A8F1B82DF19988ACC44072FDB17B4D81882E9DD952B29003D7767BA581A68BC41C2B16AD6EB57F1D048CD4E464190D25ADF2C194E3598360AFB031A1690F4625BB628363B4C90A400E3A04DAA70DA0CC4776; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'hC82B30671933680037A65978674DDEC2D30EEEDA78F5F2A1DEE660FFEA11B175DCB42E9277212A58842051A078007109A0D820166B881042600284403143048295D23A0E191EBC2134B833D53D37E42B05018289A10300A188E315CE98640F548A370D60A0AA3E7288A0B0869FA5E703D1AE17C0EC276B2AFB747B550A8B41021620D1A60A901095D12A0973B95E20838001330138951361967847D42901910A3488480610A91A851E84FF08783F81AEA52D2FDC2200BD2FE81C0357FBEC1D875686C6CA41B2224C88D8456C1DBF20D820A6649774CB11B69933246E9739C998470542C2E3C783A4C24767084C52DC209D60E95DBC096D9A0171A12D5AB99BAB; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h17A24D2C636ED2478B5AE1C99D40761B1E7AA6A89DDD1BBD8DBD223E70531BCDE90C8E38C8E0478AD8B388F94891C9673A50BC32478E083074657E8E0EA53BEE861F8BC1993560946D92D1C0C7F046A245B5849CB751FF15B97FCD50BC7B8524C13E7C640F3645082248D1CC14296E30DEA3057B35C641762CD00D40DABC27472251A60725008AAA056591C4000BB48C0BC29B8034A03400027B84769B520D9196968460CA3388A03ECB45F2C4B70F1829221000FFFC7FEC346F079F13079798EC2A08157331C6CC0E30884244916A0DE26D4D22454091290404A492016887E2111F830F9851184101370588A06D3BF9AE621A5F4E632A6799C83EFAAE06769D; -// synopsys translate_on - -// Location: M9K_X22_Y25_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a4 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[4]~98_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a4_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_first_bit_number = 4; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFFF0000003E0000003E0000C83F0000D83F0000F03F0000303E0000303E0000003F0010003F0010203F0010F03F0010703F0018303F001C603D800C003CFE26003C7F0F803FFFFFFFFFFFFFFFF; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF00000000000008108000BDF288E9688E000000000000000000000000FFFFFFFF0000000000041D989EA296D29EE969CA000000000000000000000000000000007FFFFFFC8004198A9AA298929EE9498A00000000000000000000000000000000FFFFFFFE800400CA9AA2AADA8AE949CE0000000000000000000000007FFFFFFEC00000028004046A9F22BA5A9EE90FC20000000000000000000000007FFFFFFE8000000280040FEA8002AA7A9EE12742000000000000000000000000000000023FFFFFFC9FE42BA298E2293A80096742000000000000000000000000000000003FFFFFFC9FE4B19298E3181E8009436A; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'h9FE8234A88F836EE9FF8BD4208282BC080DE87C2B84199C2B85E37C2B05B3A829FE8236688F837CE9FF8898208A82A44808A87CAB9C19DC2B80E3AC2927F2AC2800833E288F837C69FE8AB9688882E4283248DC2B9D188C2ABAE2F8291371092800832EA887807C69FE8AB8688080AC283E49D42B914BFC2A3BF1E82910712EA800802EA883807869DE88E8688080AC68BC4BDC2BB1439C2A27F5F82910314E2800886E6880807C69CC89A8681800BC289549CC2AB0C3942A04B7F82953315E2800886EE900805C61C089FC081E415C289D89DC2AB4E3142A1233D8217330090800086EE900805821C08BEC080D407C289C89DC2AADE3142A13B7F82176300F0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h076B0A5083288F028370C182A801468297E5AC1288D308023FFFFFFC00000000072BA9608BA08D028BF4D182AC015682937CA80288D308023FFFFFFC00000002872B892A8FA08F028A14509AAC0166B2B37DA80288D10D02800000027FFFFFFE852BAD128E388D028A004082AC0166C2937DA00288D10F02C00000027FFFFFFE846289368968C90289E0528A8C016CA29379B20280510F02FFFFFFFE0000000085E2A922816089828BE0428286416C829179B00280511F027FFFFFFC0000000087EA8B32872089828800569287436CA28179B20200513F0000000000FFFFFFFF8768A3028610858288004682874364828019900200403E0000000000FFFFFFFF; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N2 -cycloneive_lcell_comb \Selector4~0 ( -// Equation(s): -// \Selector4~0_combout = (\z80_|address_pins_|abus[14]~23_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout )))) # (!\z80_|address_pins_|abus[14]~23_combout -// & (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ))) - - .dataa(\z80_|address_pins_|abus[14]~23_combout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout ), - .cin(gnd), - .combout(\Selector4~0_combout ), - .cout()); -// synopsys translate_off -defparam \Selector4~0 .lut_mask = 16'hBA98; -defparam \Selector4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N26 -cycloneive_lcell_comb \Selector4~1 ( -// Equation(s): -// \Selector4~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Selector4~0_combout & ((\ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ))) # (!\Selector4~0_combout & -// (\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Selector4~0_combout )))) - - .dataa(\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ), - .datad(\Selector4~0_combout ), - .cin(gnd), - .combout(\Selector4~1_combout ), - .cout()); -// synopsys translate_off -defparam \Selector4~1 .lut_mask = 16'hF388; -defparam \Selector4~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y14_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a28 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[4]~98_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a28_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_first_bit_number = 4; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y8_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a12 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[4]~98_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y16_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a20 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[4]~98_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_first_bit_number = 4; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y3_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a4 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[4]~98_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N20 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout )) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ))))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout ), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2 .lut_mask = 16'hE5E0; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N10 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2_combout & -// (\ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout )) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ))))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2_combout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2_combout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3 .lut_mask = 16'hAFC0; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N6 -cycloneive_lcell_comb \D[4]~109 ( -// Equation(s): -// \D[4]~109_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\Selector4~1_combout -// )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3_combout ))))) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\Selector4~1_combout ), - .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3_combout ), - .cin(gnd), - .combout(\D[4]~109_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~109 .lut_mask = 16'hFB40; -defparam \D[4]~109 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N18 -cycloneive_lcell_comb \D[4]~97 ( -// Equation(s): -// \D[4]~97_combout = ((\Equal2~0_combout & (\D[4]~81_combout )) # (!\Equal2~0_combout & ((\D[4]~109_combout )))) # (!\Equal2~1_combout ) - - .dataa(\Equal2~0_combout ), - .datab(\D[4]~81_combout ), - .datac(\Equal2~1_combout ), - .datad(\D[4]~109_combout ), - .cin(gnd), - .combout(\D[4]~97_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~97 .lut_mask = 16'hDF8F; -defparam \D[4]~97 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N30 -cycloneive_lcell_comb \D[4]~98 ( -// Equation(s): -// \D[4]~98_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout & (\z80_|data_pins_|dout [4] & ((\D[4]~97_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\D[4]~97_combout ) # (!\Equal2~1_combout )))) - - .dataa(\z80_|data_pins_|dout [4]), - .datab(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datac(\Equal2~1_combout ), - .datad(\D[4]~97_combout ), - .cin(gnd), - .combout(\D[4]~98_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~98 .lut_mask = 16'hBB03; -defparam \D[4]~98 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N24 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[4] ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [4] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[4]~19_combout ) # ((\D[4]~98_combout & \z80_|pin_control_|bus_db_pin_re~combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & -// (\D[4]~98_combout & (\z80_|pin_control_|bus_db_pin_re~combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(\D[4]~98_combout ), - .datac(\z80_|pin_control_|bus_db_pin_re~combout ), - .datad(\z80_|bus_control_|db[4]~19_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [4]), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[4] .lut_mask = 16'hEAC0; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[4] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y13_N25 -dffeas \z80_|data_pins_|dout[4] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [4]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|data_pins_|dout [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|data_pins_|dout[4] .is_wysiwyg = "true"; -defparam \z80_|data_pins_|dout[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N20 -cycloneive_lcell_comb \z80_|bus_control_|db[4]~18 ( -// Equation(s): -// \z80_|bus_control_|db[4]~18_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [4]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) - - .dataa(\z80_|data_pins_|dout [4]), - .datab(\z80_|bus_control_|db[0]~4_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_bus_db_oe~combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[4]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[4]~18 .lut_mask = 16'h88CC; -defparam \z80_|bus_control_|db[4]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N18 -cycloneive_lcell_comb \z80_|bus_control_|db[4]~19 ( -// Equation(s): -// \z80_|bus_control_|db[4]~19_combout = ((\z80_|bus_control_|db[4]~18_combout & ((\z80_|alu_control_|db[4]~32_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - - .dataa(\z80_|bus_control_|db[0]~6_combout ), - .datab(\z80_|alu_control_|db[4]~32_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|bus_control_|db[4]~18_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[4]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[4]~19 .lut_mask = 16'hDF55; -defparam \z80_|bus_control_|db[4]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y10_N19 -dffeas \z80_|ir_|opcode[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|bus_control_|db[4]~19_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|ir_|opcode [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|ir_|opcode[4] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal21~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal21~0_combout = (!\z80_|ir_|opcode [3] & \z80_|ir_|opcode [4]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal21~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal21~0 .lut_mask = 16'h0F00; -defparam \z80_|pla_decode_|Equal21~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~5 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~5_combout = (\z80_|pla_decode_|Equal21~0_combout & (\z80_|pla_decode_|Equal2~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal1~7_combout ))) - - .dataa(\z80_|pla_decode_|Equal21~0_combout ), .datab(\z80_|pla_decode_|Equal2~0_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~15 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_mRead~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~39 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~39_combout = (((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|execute_|ctl_mRead~15_combout ) + + .dataa(\z80_|sequencer_|M5~q ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|execute_|ctl_mRead~15_combout ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~39 .lut_mask = 16'h1FFF; +defparam \z80_|execute_|ctl_inc_cy~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~36 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~36_combout = (\z80_|execute_|ctl_inc_cy~39_combout & (\z80_|execute_|ctl_inc_cy~38_combout & \z80_|execute_|ctl_inc_cy~82_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_inc_cy~39_combout ), + .datac(\z80_|execute_|ctl_inc_cy~38_combout ), + .datad(\z80_|execute_|ctl_inc_cy~82_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~36 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~4 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~4_combout = (\z80_|execute_|ctl_alu_op_low~22_combout & (\z80_|pla_decode_|Equal55~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal1~7_combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~5_combout ), + .combout(\z80_|execute_|ctl_sw_4u~4_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mRead~5 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_mRead~5 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_sw_4u~4 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_sw_4u~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y18_N22 -cycloneive_lcell_comb \z80_|execute_|fIOWrite~2 ( +// Location: LCCOMB_X21_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~16 ( // Equation(s): -// \z80_|execute_|fIOWrite~2_combout = (\z80_|execute_|ctl_iorw~11_combout & ((\z80_|execute_|ctl_mWrite~3_combout ) # ((\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|fMRead~0_combout )))) +// \z80_|execute_|ctl_reg_sel_wz~16_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & (!\z80_|execute_|ctl_sw_4u~4_combout & ((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|ctl_ir_we~12_combout )))) - .dataa(\z80_|execute_|ctl_mWrite~3_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_iorw~11_combout ), - .datad(\z80_|execute_|fMRead~0_combout ), + .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), + .datab(\z80_|execute_|ctl_ir_we~12_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_sw_4u~4_combout ), .cin(gnd), - .combout(\z80_|execute_|fIOWrite~2_combout ), + .combout(\z80_|execute_|ctl_reg_sel_wz~16_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fIOWrite~2 .lut_mask = 16'hE0F0; -defparam \z80_|execute_|fIOWrite~2 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_reg_sel_wz~16 .lut_mask = 16'h0015; +defparam \z80_|execute_|ctl_reg_sel_wz~16 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y18_N16 -cycloneive_lcell_comb \z80_|execute_|fIOWrite~3 ( +// Location: LCCOMB_X21_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~17 ( // Equation(s): -// \z80_|execute_|fIOWrite~3_combout = ((!\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ) +// \z80_|execute_|ctl_reg_sel_wz~17_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~36_combout & (\z80_|execute_|fMRead~6_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout & \z80_|execute_|ctl_reg_sel_wz~16_combout ))) - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~36_combout ), + .datab(\z80_|execute_|fMRead~6_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~16_combout ), .cin(gnd), - .combout(\z80_|execute_|fIOWrite~3_combout ), + .combout(\z80_|execute_|ctl_reg_sel_wz~17_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fIOWrite~3 .lut_mask = 16'h3F0F; -defparam \z80_|execute_|fIOWrite~3 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_reg_sel_wz~17 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sel_wz~17 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y18_N2 -cycloneive_lcell_comb \z80_|execute_|fIOWrite~4 ( +// Location: LCCOMB_X27_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~5 ( // Equation(s): -// \z80_|execute_|fIOWrite~4_combout = (\z80_|execute_|ctl_mRead~36_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ixy_d~6_combout ) # (!\z80_|execute_|fIOWrite~3_combout )))) +// \z80_|execute_|ctl_sw_4u~5_combout = (\z80_|execute_|ctl_alu_op_low~28_combout ) # (((\z80_|execute_|ctl_alu_shift_oe~14_combout & \z80_|pla_decode_|Equal47~0_combout )) # (!\z80_|execute_|ctl_sw_4u~1_combout )) - .dataa(\z80_|execute_|ctl_mRead~36_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|execute_|fIOWrite~3_combout ), + .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datab(\z80_|pla_decode_|Equal47~0_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~28_combout ), + .datad(\z80_|execute_|ctl_sw_4u~1_combout ), .cin(gnd), - .combout(\z80_|execute_|fIOWrite~4_combout ), + .combout(\z80_|execute_|ctl_sw_4u~5_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fIOWrite~4 .lut_mask = 16'hA8AA; -defparam \z80_|execute_|fIOWrite~4 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_sw_4u~5 .lut_mask = 16'hF8FF; +defparam \z80_|execute_|ctl_sw_4u~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y18_N4 -cycloneive_lcell_comb \z80_|execute_|fIOWrite~5 ( +// Location: LCCOMB_X29_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~6 ( // Equation(s): -// \z80_|execute_|fIOWrite~5_combout = (\z80_|execute_|fIOWrite~2_combout ) # ((\z80_|execute_|fIOWrite~4_combout ) # ((\z80_|execute_|fIOWrite~1_combout & \z80_|execute_|ctl_mRead~5_combout ))) +// \z80_|execute_|ctl_sw_4u~6_combout = (((\z80_|execute_|ctl_sw_4u~5_combout ) # (!\z80_|execute_|ctl_sw_4u~3_combout )) # (!\z80_|execute_|ctl_apin_mux~0_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~17_combout ) - .dataa(\z80_|execute_|fIOWrite~1_combout ), - .datab(\z80_|execute_|ctl_mRead~5_combout ), - .datac(\z80_|execute_|fIOWrite~2_combout ), - .datad(\z80_|execute_|fIOWrite~4_combout ), + .dataa(\z80_|execute_|ctl_reg_sel_wz~17_combout ), + .datab(\z80_|execute_|ctl_apin_mux~0_combout ), + .datac(\z80_|execute_|ctl_sw_4u~3_combout ), + .datad(\z80_|execute_|ctl_sw_4u~5_combout ), .cin(gnd), - .combout(\z80_|execute_|fIOWrite~5_combout ), + .combout(\z80_|execute_|ctl_sw_4u~6_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fIOWrite~5 .lut_mask = 16'hFFF8; -defparam \z80_|execute_|fIOWrite~5 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_sw_4u~6 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_sw_4u~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y17_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~11 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~11_combout = (!\z80_|execute_|ctl_mWrite~10_combout & (((!\z80_|execute_|ctl_mRead~10_combout & !\z80_|execute_|ctl_mRead~8_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|execute_|ctl_mWrite~10_combout ), - .datac(\z80_|execute_|ctl_mRead~8_combout ), - .datad(\z80_|execute_|ctl_state_alu~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~11 .lut_mask = 16'h0133; -defparam \z80_|execute_|ctl_mWrite~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~12 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~12_combout = (\z80_|execute_|ctl_mWrite~8_combout & (\z80_|execute_|ctl_mWrite~11_combout & ((!\z80_|execute_|ctl_mWrite~6_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|ctl_mWrite~8_combout ), - .datac(\z80_|execute_|ctl_mWrite~6_combout ), - .datad(\z80_|execute_|ctl_mWrite~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~12 .lut_mask = 16'h4C00; -defparam \z80_|execute_|ctl_mWrite~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~13 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~13_combout = (\z80_|execute_|ctl_mWrite~12_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~4_combout & (\z80_|execute_|ctl_mWrite~9_combout & \z80_|execute_|ctl_bus_db_oe~7_combout ))) - - .dataa(\z80_|execute_|ctl_mWrite~12_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), - .datac(\z80_|execute_|ctl_mWrite~9_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~13 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_mWrite~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~14 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~14_combout = (\z80_|execute_|ctl_state_alu~4_combout & ((\z80_|execute_|ctl_mRead~7_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & \z80_|execute_|ctl_mWrite~5_combout )))) # (!\z80_|execute_|ctl_state_alu~4_combout & -// (((\z80_|execute_|ctl_eval_cond~0_combout & \z80_|execute_|ctl_mWrite~5_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_mRead~7_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_mWrite~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~14 .lut_mask = 16'hF888; -defparam \z80_|execute_|ctl_mWrite~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~15 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~15_combout = ((\z80_|execute_|ctl_mWrite~14_combout ) # ((!\z80_|execute_|ixy_d~17_combout & \z80_|execute_|ixy_d~8_combout ))) # (!\z80_|execute_|ctl_mWrite~13_combout ) - - .dataa(\z80_|execute_|ixy_d~17_combout ), - .datab(\z80_|execute_|ctl_mWrite~13_combout ), - .datac(\z80_|execute_|ctl_mWrite~14_combout ), - .datad(\z80_|execute_|ixy_d~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~15 .lut_mask = 16'hF7F3; -defparam \z80_|execute_|ctl_mWrite~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X43_Y17_N29 -dffeas \z80_|memory_ifc_|DFFE_mwr_ff1 ( +// Location: FF_X30_Y12_N27 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[3] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_mWrite~15_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_mwr_ff1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_mwr_ff1 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_mwr_ff1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N4 -cycloneive_lcell_comb \z80_|memory_ifc_|wait_mwr~feeder ( -// Equation(s): -// \z80_|memory_ifc_|wait_mwr~feeder_combout = \z80_|memory_ifc_|DFFE_mwr_ff1~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|memory_ifc_|DFFE_mwr_ff1~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|wait_mwr~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_mwr~feeder .lut_mask = 16'hFF00; -defparam \z80_|memory_ifc_|wait_mwr~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X43_Y17_N5 -dffeas \z80_|memory_ifc_|wait_mwr ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|memory_ifc_|wait_mwr~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|wait_mwr~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_mwr .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|wait_mwr .power_up = "low"; -// synopsys translate_on - -// Location: FF_X43_Y17_N17 -dffeas \z80_|memory_ifc_|mwr_wr ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), - .asdata(\z80_|memory_ifc_|wait_mwr~q ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|mwr_wr~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|mwr_wr .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|mwr_wr .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N16 -cycloneive_lcell_comb \z80_|memory_ifc_|nWR_out~0 ( -// Equation(s): -// \z80_|memory_ifc_|nWR_out~0_combout = (\z80_|memory_ifc_|mwr_wr~q ) # ((\z80_|execute_|fIOWrite~5_combout & \z80_|memory_ifc_|iorq~0_combout )) - - .dataa(\z80_|execute_|fIOWrite~5_combout ), - .datab(\z80_|memory_ifc_|iorq~0_combout ), - .datac(\z80_|memory_ifc_|mwr_wr~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|memory_ifc_|nWR_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|nWR_out~0 .lut_mask = 16'hF8F8; -defparam \z80_|memory_ifc_|nWR_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N4 -cycloneive_lcell_comb \D[5]~84 ( -// Equation(s): -// \D[5]~84_combout = (!\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|memory_ifc_|nRD_out~2_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|memory_ifc_|nIORQ_out~0_combout ))) - - .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), - .datab(\z80_|memory_ifc_|nRD_out~2_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|memory_ifc_|nIORQ_out~0_combout ), - .cin(gnd), - .combout(\D[5]~84_combout ), - .cout()); -// synopsys translate_off -defparam \D[5]~84 .lut_mask = 16'h0040; -defparam \D[5]~84 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y5_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a23 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[7]~102_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_first_bit_number = 7; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y4_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a7 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[7]~102_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081; -// synopsys translate_on - -// Location: M9K_X33_Y7_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a15 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[7]~102_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N14 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]) # -// ((\ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & -// (\ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6 .lut_mask = 16'hBA98; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y4_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a31 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[7]~102_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a31_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_first_bit_number = 7; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N4 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6_combout & -// ((\ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout )))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6_combout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout ), - .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6_combout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7 .lut_mask = 16'hF858; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y24_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a15 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(gnd), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[7]~102_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_first_bit_number = 7; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y30_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a15 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h3C0000000000000000000000000000000000000000000000000000000000000080000000000002000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFB91060128E2D09899B4D10A148392808351AD282E76190E029FDC286449331D89080802222C0D04D1121484041D21084C223B0A12EBE72083D81421B93CA9589A04864A853089602E536320C2A5944831907110C246020089C76EE701A4E23964C6586008731635460418000008202040C300110000FCE7E12403749F8C6AB8F69167210EF8A4B8228710884C5C47A9986E8840C02862C088C36E19CF1D315; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h03020CCE064769B15020A6030880234C64E9BEF8E98A81489083A026140D648906E5AD6C882882990A40D293FED064710CB226CDA0330D7B189B344442EC35E3763C75FA1DB107B865E5B8F7B95E77F222244C6BDC1879C0562EF779BE0009465775469089F04C623E19317B486F653C1C22CA642CD685C10EE47EDD66C8C226C7C57F084106FB3B8B1E47463C0088D11104F23C180222A0AA22A22882A202A00000000288964258156302504F5F660C054DEDCA20CC201A4074192601E376C9596CD8B4B568A4DFEF3DBF8027A3422A56A2C003E514582104BF8D6B5D80BB397FBBEC46E8B3CAEBE0100275A1092081D0C1E5716DF09CFEEC00AD800529E1A8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h873CB568FC3F09080F4400DAC600092017210911A6081DCC4979244124815884AE6302C4BE6BA8C22A084803225A0855ABBBC528B1CA2456A4951A53C1209153CFC3000F43632B49C39723270C604B184D1940F1B2A04459BEB088666843BB38C23A8D170CED981891256A2C1D9B31C0F040202103900E6765976089DB8DE16E0001022EC10015E263787F7E581EF83F062200C626EC4E19021840D9C112400C4B987A78AE1BF80005EF370C0739371E0D3E5CF1E3677332370BB98D1831B30F7D8CDC0131C444798F040DC0116E2C4336B0166109A15D1FCC7EDE31EB23862203C11245EE31E38E6DEF2188BE2068F3C716E10317783020D8EF5C256774BA0E; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h1B9CE2DA363196DC20007FF5554FC631286DC716B048384C26510685218DF9E6C629E6050C619658692170C1022C2232C965C92C189020C705873084858910322166D72DC524870C422BBFFD4808A7032B088DE3000B853800736C8E9968C19A4B72C08871D2413188E4829219C38C2025920480D64856902E4D4D60B640C833C14D536A45D144B244C24A290076E58CC2E64E4A2DC4C5939C4C2DDBD1B918B231248625B2C0DD0F07A27A111CB80A48808C7C21C205029100010400228BB3BDFF7DCCEF40196C8381658D8840043B119B86A46247665810E2203000141023C366CB633B3376DC625DA8A0856C484392B779E1BA4088EDB4A6CDB9BD46DCC0B2; -// synopsys translate_on - -// Location: M9K_X22_Y2_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a7 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h7C762E21DB2481CB6BB88C68811C76C63B18ECC1BACDC6110DCC70BC20940800C71478E35468600B01A93082C63DD073AE4181844449C08D8D56B0DCC881251C202139803D3000B2E0209DB9101160989A5916381001B0446631006064DB1B996E436E644CF6C8606F124DA230E9B66E2F46BB466E2CE068661B4B05F02F7D00CB3E518948104042F84F1840401018406877D800A00000F5122597005DA4411000800020249004081008924124080114000000020BFFFFEC638C31207B6C321407D901787004001C459326210CCE00C6AF707B84440C313110B8C4D13B2C6E06C4C088B1A9B24BEB0178C4D6C18230DF72B07A28063647CC4721026D8C711864; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h881B30810845E6D18622EC9B6236A000030986A4F0644601226000A2F220D40310438334E51C28000400B18422CA60FC42C9C03F066366ECBBB010B00B004807CC0E00DAEC3000194A52B80C606262092D84A1102410000001400010002000800200080020000800200008000800400040002004000040002000020002000801000010004002001000200008000AEE708008880C86112251B45B36C0048833B319B4C2CE6660D2C0619246C4B208BC0AD00202001E104FC30911410804201E92102B400E8004C40AD6E4614466308ABC7165AA57060A3A736A188ABB300200A10BB04344008422327B1393C43396A931B8C8C87227A6141C0E2DCC76D830B082; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h101CC0024A6C32005CCB31908842211604D8B326101118B54B188CB4D502F5F02DA65C2472B824F109BC594C2401209C01A0E59830002C73B396C6015B85A163184B56183004204267600220A061A004893E1D609106BDBB553920A011AA5AE581E08228382D54C2989BC59535528176240438C9AA757917F95C7428981A26470D1C3E528444D9B00E561C40973AE1806031C464834F03D34A11233A34B34A1D1A55A50C3384B549B64C381920140D4008004020B119D5834C10064000006001169808000200040100000002F8986E37654DDFF88E20860382DC089D4C239F6E4C3C8D784218667F524CE209881213DC91099C14744901620044C802DA414966; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h84724A241226DB4809C9A1100DE6A63984D651A2624A09420496DDC12CC10964B6E370363701B41848117683379C8422106D001BB41FB8248067301E1002C636A276585D5273AC87206840415DA74B4E9D213CAE3234B308E19608AA38250844883838649E1442A0D983F4A9094A5AD4A52D56C5D80CAC58D9645944A230091549F30426B100842A12B25160D6D991E6C8C81AFB4C644004C2140A342020D84C9001624489A10045D16C944B02763FF55405E400BADFE5BFFFFFF00000000011042250089108884888410924041204444209102084241104204108824114455292225124929249248894408541300A6DB00791E5B12FEF24037181F1901B007B; -// synopsys translate_on - -// Location: M9K_X33_Y26_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a7 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[7]~102_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_first_bit_number = 7; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h000000000000000000000000FFFFFFFFC0810207C0001A176020155177486D89000000000000000000000000FFFFFFFF80000003C0000217724019F17748EDC900000000000000000000000000000001BF7EFDF9400406B17A400BF57748AD81000000000000000000000000000000013F7EFDF940041EB1724218157749A7910000000000000000000000003F7EFDF90000000140042AF97B426C157DC9B7590000000000000000000000003F7EFDF90000000140042069600246057DC95351000000000000000000000000408102053FFFFFF95FE4084175C246896009F35100000000000000000000000040810207BFFFFFFF7FE4147177C2004960291759; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h7FE8374958F827C15FF88F91E9A80DC3629A9FC172033EC170FB0E8173F792815FE826E158F805C95FF8AF8169A80DC3629A1EC17B033BC1706B3E8173FFB0C1400826E558F805C15DF8AF9169A82DD163C21BC17B133BC1716B3781723F14C1400826E958D825815DD8AF8168482DC161229BC17A133FC171AB3781723F16E9400826E95818058179582F9160480FC162229FC17ACA39C172FB3F8152CF10A1400826E958180D8179580F05614C0DC162329BC171EB398173537F8152E310D1400826E158180D81F8580FD1612C0F41631293C173BB398D63037F81D22313D1400827E958080F01F8188FCB60A40F41435083C1723B198161834F01D67300E3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'hD4FB0D2352268F0151E680016803440977EDE98148F31101BFFFFFFF4081010750FB094B52728F0151FEC0016C034C0153EDA90148F31F013FFFFFFB4081010152F3096156DA8901503ED2016C03480173FDA00148F11F01000000013F7EFEF952E3017156DA85015022C2016C034C0153FCA00148F10F01000000013F7EFEF956B3A9115052850543C2C2116C014D2153FDA12148D11F013F7EFEF900000001469F8B3150728D0143C05A016D014C81537DA00148D11E01BF7EFEF900000001528F8F2156628D0140004E016F054481513DA181C8513E0580000007FFFFFFFF528E8B2156E28C0148024E0167676C415139B041C8513E07C0810107FFFFFFFF; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N18 -cycloneive_lcell_comb \Mux0~0 ( -// Equation(s): -// \Mux0~0_combout = (\z80_|address_pins_|abus[14]~23_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout )))) # (!\z80_|address_pins_|abus[14]~23_combout & -// (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ))) - - .dataa(\z80_|address_pins_|abus[14]~23_combout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout ), - .cin(gnd), - .combout(\Mux0~0_combout ), - .cout()); -// synopsys translate_off -defparam \Mux0~0 .lut_mask = 16'hBA98; -defparam \Mux0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N12 -cycloneive_lcell_comb \Mux0~1 ( -// Equation(s): -// \Mux0~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Mux0~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout )) # (!\Mux0~0_combout & -// ((\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Mux0~0_combout )))) - - .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ), - .datad(\Mux0~0_combout ), - .cin(gnd), - .combout(\Mux0~1_combout ), - .cout()); -// synopsys translate_off -defparam \Mux0~1 .lut_mask = 16'hBBC0; -defparam \Mux0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N22 -cycloneive_lcell_comb \D[7]~112 ( -// Equation(s): -// \D[7]~112_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\Mux0~1_combout ))) -// # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout )))) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout ), - .datad(\Mux0~1_combout ), - .cin(gnd), - .combout(\D[7]~112_combout ), - .cout()); -// synopsys translate_off -defparam \D[7]~112 .lut_mask = 16'hF4B0; -defparam \D[7]~112 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N30 -cycloneive_lcell_comb \D[7]~94 ( -// Equation(s): -// \D[7]~94_combout = (\D[5]~84_combout & (\D[7]~112_combout & ((\z80_|data_pins_|dout [7]) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) # (!\D[5]~84_combout & ((\z80_|data_pins_|dout [7]) # ((!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) - - .dataa(\D[5]~84_combout ), - .datab(\z80_|data_pins_|dout [7]), - .datac(\D[7]~112_combout ), - .datad(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .cin(gnd), - .combout(\D[7]~94_combout ), - .cout()); -// synopsys translate_off -defparam \D[7]~94 .lut_mask = 16'hC4F5; -defparam \D[7]~94 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N26 -cycloneive_lcell_comb \D[7]~102 ( -// Equation(s): -// \D[7]~102_combout = (\D[7]~94_combout ) # (!\D[0]~107_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\D[7]~94_combout ), - .datad(\D[0]~107_combout ), - .cin(gnd), - .combout(\D[7]~102_combout ), - .cout()); -// synopsys translate_off -defparam \D[7]~102 .lut_mask = 16'hF0FF; -defparam \D[7]~102 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N26 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [7] = (\D[7]~102_combout & ((\z80_|pin_control_|bus_db_pin_re~combout ) # ((\z80_|bus_control_|db[7]~7_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\D[7]~102_combout & (\z80_|bus_control_|db[7]~7_combout -// & ((\z80_|execute_|ctl_bus_db_we~7_combout )))) - - .dataa(\D[7]~102_combout ), - .datab(\z80_|bus_control_|db[7]~7_combout ), - .datac(\z80_|pin_control_|bus_db_pin_re~combout ), - .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [7]), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] .lut_mask = 16'hECA0; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y13_N27 -dffeas \z80_|data_pins_|dout[7] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [7]), - .asdata(vcc), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), - .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|data_pins_|dout [7]), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [3]), .prn(vcc)); // synopsys translate_off -defparam \z80_|data_pins_|dout[7] .is_wysiwyg = "true"; -defparam \z80_|data_pins_|dout[7] .power_up = "low"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y13_N2 -cycloneive_lcell_comb \z80_|bus_control_|db[7]~5 ( -// Equation(s): -// \z80_|bus_control_|db[7]~5_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[7]~18_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) - - .dataa(gnd), - .datab(\z80_|alu_control_|db[7]~18_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|bus_control_|db[0]~4_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[7]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[7]~5 .lut_mask = 16'hCF00; -defparam \z80_|bus_control_|db[7]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N8 -cycloneive_lcell_comb \z80_|bus_control_|db[7]~7 ( -// Equation(s): -// \z80_|bus_control_|db[7]~7_combout = ((\z80_|bus_control_|db[7]~5_combout & ((\z80_|data_pins_|dout [7]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - - .dataa(\z80_|data_pins_|dout [7]), - .datab(\z80_|execute_|ctl_bus_db_oe~combout ), - .datac(\z80_|bus_control_|db[0]~6_combout ), - .datad(\z80_|bus_control_|db[7]~5_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[7]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[7]~7 .lut_mask = 16'hBF0F; -defparam \z80_|bus_control_|db[7]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y13_N21 -dffeas \z80_|ir_|opcode[7] ( +// Location: FF_X30_Y12_N29 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), - .asdata(\z80_|bus_control_|db[7]~7_combout ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(vcc), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|ir_|opcode [7]), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]), .prn(vcc)); // synopsys translate_off -defparam \z80_|ir_|opcode[7] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[7] .power_up = "low"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y13_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal77~0 ( +// Location: LCCOMB_X30_Y12_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~44 ( // Equation(s): -// \z80_|pla_decode_|Equal77~0_combout = (!\z80_|ir_|opcode [7] & (!\z80_|decode_state_|DFFE_instCB~q & (\z80_|ir_|opcode [6] & !\z80_|decode_state_|DFFE_instED~q ))) +// \z80_|reg_file_|gdfx_temp0[3]~44_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [3] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [3] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|decode_state_|DFFE_instCB~q ), - .datac(\z80_|ir_|opcode [6]), - .datad(\z80_|decode_state_|DFFE_instED~q ), + .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [3]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), .cin(gnd), - .combout(\z80_|pla_decode_|Equal77~0_combout ), + .combout(\z80_|reg_file_|gdfx_temp0[3]~44_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal77~0 .lut_mask = 16'h0010; -defparam \z80_|pla_decode_|Equal77~0 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|gdfx_temp0[3]~44 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp0[3]~44 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~5 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~5_combout = (\z80_|pla_decode_|Equal77~0_combout & (!\z80_|decode_state_|in_halt~q & (!\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal33~1_combout ))) +// Location: FF_X31_Y11_N21 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[3] .power_up = "low"; +// synopsys translate_on - .dataa(\z80_|pla_decode_|Equal77~0_combout ), - .datab(\z80_|decode_state_|in_halt~q ), - .datac(\z80_|decode_state_|use_ixiy~combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), +// Location: FF_X31_Y11_N11 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~43 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~43_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [3]), + .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [3]), .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~5_combout ), + .combout(\z80_|reg_file_|gdfx_temp0[3]~43_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~5 .lut_mask = 16'h0200; -defparam \z80_|execute_|ctl_mWrite~5 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|gdfx_temp0[3]~43 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[3]~43 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout = (\z80_|pla_decode_|Equal13~0_combout & (\z80_|execute_|ctl_ir_we~4_combout & (\z80_|pla_decode_|Equal8~0_combout & !\z80_|ir_|opcode [3]))) +// Location: FF_X32_Y13_N7 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3] .power_up = "low"; +// synopsys translate_on - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|pla_decode_|Equal8~0_combout ), - .datad(\z80_|ir_|opcode [3]), +// Location: FF_X32_Y14_N13 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~46 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~46_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [3] & ((\z80_|alu_control_|db[3]~35_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (((\z80_|alu_control_|db[3]~35_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [3]), + .datad(\z80_|alu_control_|db[3]~35_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ), + .combout(\z80_|reg_file_|gdfx_temp0[3]~46_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|gdfx_temp0[3]~46 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[3]~46 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y16_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~3 ( +// Location: LCCOMB_X32_Y13_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~47 ( // Equation(s): -// \z80_|execute_|ctl_bus_db_we~3_combout = (\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # (\z80_|execute_|ctl_iorw~11_combout )))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|ctl_mWrite~5_combout ), - .datac(\z80_|execute_|ctl_iorw~11_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~3 .lut_mask = 16'hFFA8; -defparam \z80_|execute_|ctl_bus_db_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_we~8_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|M5~q & ((\z80_|execute_|ctl_mRead~10_combout ) # (\z80_|pla_decode_|Equal9~1_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~8 .lut_mask = 16'h3020; -defparam \z80_|execute_|ctl_bus_db_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_we~2_combout = (\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_mRead~10_combout ) # ((\z80_|pla_decode_|Equal13~2_combout ) # (\z80_|execute_|ctl_mWrite~5_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|ctl_mWrite~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~2 .lut_mask = 16'hCCC8; -defparam \z80_|execute_|ctl_bus_db_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_we~4_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mWrite~4_combout ) # ((\z80_|pla_decode_|Equal21~0_combout & \z80_|pla_decode_|Equal24~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal21~0_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|pla_decode_|Equal24~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~4 .lut_mask = 16'hC8C0; -defparam \z80_|execute_|ctl_bus_db_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_we~6_combout = (((\z80_|execute_|ctl_bus_db_we~4_combout ) # (!\z80_|execute_|ctl_sw_2u~3_combout )) # (!\z80_|execute_|ctl_bus_db_we~5_combout )) # (!\z80_|execute_|ctl_apin_mux~0_combout ) - - .dataa(\z80_|execute_|ctl_apin_mux~0_combout ), - .datab(\z80_|execute_|ctl_bus_db_we~5_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~4_combout ), - .datad(\z80_|execute_|ctl_sw_2u~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~6 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|ctl_bus_db_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_we~7_combout = (\z80_|execute_|ctl_bus_db_we~3_combout ) # ((\z80_|execute_|ctl_bus_db_we~8_combout ) # ((\z80_|execute_|ctl_bus_db_we~2_combout ) # (\z80_|execute_|ctl_bus_db_we~6_combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_we~3_combout ), - .datab(\z80_|execute_|ctl_bus_db_we~8_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~2_combout ), - .datad(\z80_|execute_|ctl_bus_db_we~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~7 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_bus_db_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][2]~50 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][2]~50_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [4]) +// \z80_|reg_file_|gdfx_temp0[3]~47_combout = (\z80_|reg_file_|gdfx_temp0[3]~46_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) .dataa(gnd), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [3]), + .datad(\z80_|reg_file_|gdfx_temp0[3]~46_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][2]~50_combout ), + .combout(\z80_|reg_file_|gdfx_temp0[3]~47_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][2]~50 .lut_mask = 16'h000F; -defparam \ula_|zx_keyboard_|keys[0][2]~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][2]~52 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][2]~52_combout = (\ula_|zx_keyboard_|keys[7][4]~51_combout & ((\ula_|zx_keyboard_|keys[0][2]~50_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[0][2]~50_combout & ((\ula_|zx_keyboard_|keys[0][2]~q -// ))))) # (!\ula_|zx_keyboard_|keys[7][4]~51_combout & (((\ula_|zx_keyboard_|keys[0][2]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[7][4]~51_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[0][2]~q ), - .datad(\ula_|zx_keyboard_|keys[0][2]~50_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][2]~52_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][2]~52 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[0][2]~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y20_N17 -dffeas \ula_|zx_keyboard_|keys[0][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[0][2]~52_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[0][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[0][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][3]~48 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][3]~48_combout = (\ula_|zx_keyboard_|keys[7][4]~19_combout & (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|zx_keyboard_|keys[7][4]~19_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][3]~48_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][3]~48 .lut_mask = 16'h0008; -defparam \ula_|zx_keyboard_|keys[3][3]~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][2]~49 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][2]~49_combout = (\ula_|zx_keyboard_|keys[3][3]~48_combout & ((\ula_|zx_keyboard_|keys[6][4]~47_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[6][4]~47_combout & (\ula_|zx_keyboard_|keys[1][2]~q -// )))) # (!\ula_|zx_keyboard_|keys[3][3]~48_combout & (((\ula_|zx_keyboard_|keys[1][2]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[3][3]~48_combout ), - .datab(\ula_|zx_keyboard_|keys[6][4]~47_combout ), - .datac(\ula_|zx_keyboard_|keys[1][2]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][2]~49_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][2]~49 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[1][2]~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y20_N23 -dffeas \ula_|zx_keyboard_|keys[1][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[1][2]~49_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[1][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[1][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N22 -cycloneive_lcell_comb \D[2]~35 ( -// Equation(s): -// \D[2]~35_combout = (\z80_|address_pins_|abus[8]~18_combout & (((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][2]~q )))) # (!\z80_|address_pins_|abus[8]~18_combout & (!\ula_|zx_keyboard_|keys[0][2]~q & -// ((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][2]~q )))) - - .dataa(\z80_|address_pins_|abus[8]~18_combout ), - .datab(\ula_|zx_keyboard_|keys[0][2]~q ), - .datac(\ula_|zx_keyboard_|keys[1][2]~q ), - .datad(\z80_|address_pins_|abus[9]~17_combout ), - .cin(gnd), - .combout(\D[2]~35_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~35 .lut_mask = 16'hBB0B; -defparam \D[2]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~57 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][2]~57_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [0]) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][2]~57_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][2]~57 .lut_mask = 16'h3300; -defparam \ula_|zx_keyboard_|keys[5][2]~57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~58 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][2]~58_combout = (\ula_|zx_keyboard_|keys[5][2]~57_combout & ((\ula_|zx_keyboard_|keys[5][2]~33_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[5][2]~33_combout & (\ula_|zx_keyboard_|keys[5][2]~q -// )))) # (!\ula_|zx_keyboard_|keys[5][2]~57_combout & (((\ula_|zx_keyboard_|keys[5][2]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[5][2]~57_combout ), - .datab(\ula_|zx_keyboard_|keys[5][2]~33_combout ), - .datac(\ula_|zx_keyboard_|keys[5][2]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][2]~58_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][2]~58 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[5][2]~58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y18_N15 -dffeas \ula_|zx_keyboard_|keys[5][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[5][2]~58_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[5][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[5][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~59 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][2]~59_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|zx_keyboard_|extended~q ))) # (!\ula_|ps2_keyboard_|shiftreg [1] & -// (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|zx_keyboard_|extended~q ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|zx_keyboard_|extended~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][2]~59_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][2]~59 .lut_mask = 16'h0420; -defparam \ula_|zx_keyboard_|keys[4][2]~59 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~131 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][2]~131_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|keys[4][2]~59_combout & (\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [0]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|zx_keyboard_|keys[4][2]~59_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][2]~131_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][2]~131 .lut_mask = 16'h0080; -defparam \ula_|zx_keyboard_|keys[4][2]~131 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~60 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][2]~60_combout = (\ula_|zx_keyboard_|keys[4][2]~131_combout & ((\ula_|zx_keyboard_|keys[3][4]~130_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][4]~130_combout & ((\ula_|zx_keyboard_|keys[4][2]~q -// ))))) # (!\ula_|zx_keyboard_|keys[4][2]~131_combout & (((\ula_|zx_keyboard_|keys[4][2]~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[4][2]~131_combout ), - .datac(\ula_|zx_keyboard_|keys[4][2]~q ), - .datad(\ula_|zx_keyboard_|keys[3][4]~130_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][2]~60_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][2]~60 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[4][2]~60 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y18_N15 -dffeas \ula_|zx_keyboard_|keys[4][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[4][2]~60_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[4][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[4][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N4 -cycloneive_lcell_comb \D[2]~37 ( -// Equation(s): -// \D[2]~37_combout = (\z80_|address_pins_|abus[13]~20_combout & (((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][2]~q )))) # (!\z80_|address_pins_|abus[13]~20_combout & (!\ula_|zx_keyboard_|keys[5][2]~q & -// ((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][2]~q )))) - - .dataa(\z80_|address_pins_|abus[13]~20_combout ), - .datab(\ula_|zx_keyboard_|keys[5][2]~q ), - .datac(\ula_|zx_keyboard_|keys[4][2]~q ), - .datad(\z80_|address_pins_|abus[12]~21_combout ), - .cin(gnd), - .combout(\D[2]~37_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~37 .lut_mask = 16'hBB0B; -defparam \D[2]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][2]~53 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][2]~53_combout = (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [4]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][2]~53_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][2]~53 .lut_mask = 16'h00F0; -defparam \ula_|zx_keyboard_|keys[3][2]~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][2]~55 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][2]~55_combout = (\ula_|zx_keyboard_|keys[7][4]~19_combout & (\ula_|zx_keyboard_|keys[3][2]~53_combout & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|zx_keyboard_|Equal0~2_combout ))) - - .dataa(\ula_|zx_keyboard_|keys[7][4]~19_combout ), - .datab(\ula_|zx_keyboard_|keys[3][2]~53_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|zx_keyboard_|Equal0~2_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][2]~55_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][2]~55 .lut_mask = 16'h0800; -defparam \ula_|zx_keyboard_|keys[2][2]~55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][2]~56 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][2]~56_combout = (\ula_|zx_keyboard_|keys[2][2]~55_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[2][2]~55_combout & ((\ula_|zx_keyboard_|keys[2][2]~q ))) - - .dataa(gnd), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[2][2]~q ), - .datad(\ula_|zx_keyboard_|keys[2][2]~55_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][2]~56_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][2]~56 .lut_mask = 16'h33F0; -defparam \ula_|zx_keyboard_|keys[2][2]~56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y20_N27 -dffeas \ula_|zx_keyboard_|keys[2][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[2][2]~56_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[2][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[2][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][2]~54 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][2]~54_combout = (\ula_|zx_keyboard_|keys[7][4]~51_combout & ((\ula_|zx_keyboard_|keys[3][2]~53_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][2]~53_combout & ((\ula_|zx_keyboard_|keys[3][2]~q -// ))))) # (!\ula_|zx_keyboard_|keys[7][4]~51_combout & (((\ula_|zx_keyboard_|keys[3][2]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[7][4]~51_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[3][2]~q ), - .datad(\ula_|zx_keyboard_|keys[3][2]~53_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][2]~54_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][2]~54 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[3][2]~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y20_N29 -dffeas \ula_|zx_keyboard_|keys[3][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[3][2]~54_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[3][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[3][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N8 -cycloneive_lcell_comb \D[2]~36 ( -// Equation(s): -// \D[2]~36_combout = (\ula_|zx_keyboard_|keys[2][2]~q & (\z80_|address_pins_|abus[10]~24_combout & ((\z80_|address_pins_|abus[11]~19_combout ) # (!\ula_|zx_keyboard_|keys[3][2]~q )))) # (!\ula_|zx_keyboard_|keys[2][2]~q & -// (((\z80_|address_pins_|abus[11]~19_combout )) # (!\ula_|zx_keyboard_|keys[3][2]~q ))) - - .dataa(\ula_|zx_keyboard_|keys[2][2]~q ), - .datab(\ula_|zx_keyboard_|keys[3][2]~q ), - .datac(\z80_|address_pins_|abus[10]~24_combout ), - .datad(\z80_|address_pins_|abus[11]~19_combout ), - .cin(gnd), - .combout(\D[2]~36_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~36 .lut_mask = 16'hF531; -defparam \D[2]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~68 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][2]~68_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [1]))) # (!\ula_|ps2_keyboard_|shiftreg [4] & -// (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [1]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][2]~68_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][2]~68 .lut_mask = 16'h0180; -defparam \ula_|zx_keyboard_|keys[6][2]~68 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~69 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][2]~69_combout = (\ula_|zx_keyboard_|keys[6][1]~41_combout & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|zx_keyboard_|keys[6][2]~68_combout )) - - .dataa(\ula_|zx_keyboard_|keys[6][1]~41_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(gnd), - .datad(\ula_|zx_keyboard_|keys[6][2]~68_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][2]~69_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][2]~69 .lut_mask = 16'h2200; -defparam \ula_|zx_keyboard_|keys[6][2]~69 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~70 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][2]~70_combout = (\ula_|zx_keyboard_|keys[6][2]~69_combout & (!\ula_|zx_keyboard_|keys[5][0]~67_combout )) # (!\ula_|zx_keyboard_|keys[6][2]~69_combout & ((\ula_|zx_keyboard_|keys[6][2]~q ))) - - .dataa(\ula_|zx_keyboard_|keys[5][0]~67_combout ), - .datab(\ula_|zx_keyboard_|keys[6][2]~69_combout ), - .datac(\ula_|zx_keyboard_|keys[6][2]~q ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][2]~70_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][2]~70 .lut_mask = 16'h7474; -defparam \ula_|zx_keyboard_|keys[6][2]~70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y20_N1 -dffeas \ula_|zx_keyboard_|keys[6][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[6][2]~70_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[6][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[6][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y21_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~61 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~61_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [5]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~61_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~61 .lut_mask = 16'h0F00; -defparam \ula_|zx_keyboard_|keys[7][2]~61 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y21_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~62 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~62_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|zx_keyboard_|keys[7][2]~61_combout & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [0]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|zx_keyboard_|keys[7][2]~61_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~62_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~62 .lut_mask = 16'h0080; -defparam \ula_|zx_keyboard_|keys[7][2]~62 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y21_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~64 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~64_combout = (\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[7][2]~62_combout ) # ((\ula_|zx_keyboard_|keys[5][4]~63_combout & \ula_|zx_keyboard_|keys[7][2]~32_combout )))) - - .dataa(\ula_|zx_keyboard_|keys[5][4]~63_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|zx_keyboard_|keys[7][2]~62_combout ), - .datad(\ula_|zx_keyboard_|keys[7][2]~32_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~64_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~64 .lut_mask = 16'hC8C0; -defparam \ula_|zx_keyboard_|keys[7][2]~64 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y21_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~65 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~65_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|zx_keyboard_|extended~q & (\ula_|zx_keyboard_|keys[0][0]~15_combout & \ula_|zx_keyboard_|keys[7][2]~64_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|zx_keyboard_|extended~q ), - .datac(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .datad(\ula_|zx_keyboard_|keys[7][2]~64_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~65_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~65 .lut_mask = 16'h1000; -defparam \ula_|zx_keyboard_|keys[7][2]~65 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|Selector13~0 ( -// Equation(s): -// \ula_|zx_keyboard_|Selector13~0_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & !\ula_|ps2_keyboard_|shiftreg [5])) - - .dataa(\ula_|zx_keyboard_|shifted~q ), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(gnd), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|Selector13~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|Selector13~0 .lut_mask = 16'hFF22; -defparam \ula_|zx_keyboard_|Selector13~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y21_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~66 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~66_combout = (\ula_|zx_keyboard_|keys[7][2]~65_combout & ((!\ula_|zx_keyboard_|Selector13~0_combout ))) # (!\ula_|zx_keyboard_|keys[7][2]~65_combout & (\ula_|zx_keyboard_|keys[7][2]~q )) - - .dataa(\ula_|zx_keyboard_|keys[7][2]~65_combout ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[7][2]~q ), - .datad(\ula_|zx_keyboard_|Selector13~0_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~66_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~66 .lut_mask = 16'h50FA; -defparam \ula_|zx_keyboard_|keys[7][2]~66 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y21_N13 -dffeas \ula_|zx_keyboard_|keys[7][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[7][2]~66_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[7][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[7][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y21_N0 -cycloneive_lcell_comb \D[2]~38 ( -// Equation(s): -// \D[2]~38_combout = (\z80_|address_pins_|abus[15]~22_combout & (((\z80_|address_pins_|abus[14]~23_combout )) # (!\ula_|zx_keyboard_|keys[6][2]~q ))) # (!\z80_|address_pins_|abus[15]~22_combout & (!\ula_|zx_keyboard_|keys[7][2]~q & -// ((\z80_|address_pins_|abus[14]~23_combout ) # (!\ula_|zx_keyboard_|keys[6][2]~q )))) - - .dataa(\z80_|address_pins_|abus[15]~22_combout ), - .datab(\ula_|zx_keyboard_|keys[6][2]~q ), - .datac(\z80_|address_pins_|abus[14]~23_combout ), - .datad(\ula_|zx_keyboard_|keys[7][2]~q ), - .cin(gnd), - .combout(\D[2]~38_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~38 .lut_mask = 16'hA2F3; -defparam \D[2]~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N14 -cycloneive_lcell_comb \D[2]~39 ( -// Equation(s): -// \D[2]~39_combout = (\D[2]~35_combout & (\D[2]~37_combout & (\D[2]~36_combout & \D[2]~38_combout ))) - - .dataa(\D[2]~35_combout ), - .datab(\D[2]~37_combout ), - .datac(\D[2]~36_combout ), - .datad(\D[2]~38_combout ), - .cin(gnd), - .combout(\D[2]~39_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~39 .lut_mask = 16'h8000; -defparam \D[2]~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N14 -cycloneive_lcell_comb \D[2]~104 ( -// Equation(s): -// \D[2]~104_combout = ((\z80_|address_pins_|DFFE_apin_latch [0]) # (\D[2]~39_combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [0]), - .datad(\D[2]~39_combout ), - .cin(gnd), - .combout(\D[2]~104_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~104 .lut_mask = 16'hFFF3; -defparam \D[2]~104 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y8_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a26 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[2]~46_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_first_bit_number = 2; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y12_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a10 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[2]~46_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y9_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a18 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[2]~46_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_first_bit_number = 2; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y12_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a2 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[2]~46_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N8 -cycloneive_lcell_comb \D[2]~43 ( -// Equation(s): -// \D[2]~43_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout )))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ), - .cin(gnd), - .combout(\D[2]~43_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~43 .lut_mask = 16'hB9A8; -defparam \D[2]~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N6 -cycloneive_lcell_comb \D[2]~44 ( -// Equation(s): -// \D[2]~44_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[2]~43_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout )) # (!\D[2]~43_combout & -// ((\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ))))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[2]~43_combout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ), - .datad(\D[2]~43_combout ), - .cin(gnd), - .combout(\D[2]~44_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~44 .lut_mask = 16'hBBC0; -defparam \D[2]~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y17_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a10 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h8102080042447C443C0C3C402004FC1838787840407A00707C02487E444878428008004042460424402040024A3242124220044022404208520A4A24424A125A0A1028440000524A0A4A4A204A5240460800100010540042002064547E0600001FA9BE02B828694B8A82CB8C8158226808198E9EC6B021F07A2098D5E0ECB639D2B1908129B6A2D646516192D87593189D8B2B26CD6E16234C1CC90AD9831EBD89EAD271ECC39A80507716BB49626B743DFFCF99576C3FAC889860E46618ACB79EC30EEDE42EB1E31F3976CA23243179FAA96DCD66D51535351770D410DC8531866136E6184518410368288C446EC63A4FEE425019C244097049C2B2DC8D93C4; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'hA111466C9493A2A7CA2204102414CC798BF0EEC2995A4814580BD07585585ED92E5172E82E845070000A846100500E84EA1803B8B07B99E1DC75BE6419674597B38F54EB9091AE3320201EE395AD63902282A031CE3E87CC902954AA515D5D6B6A855EC94CFEC4E0172C59A7D054F8F9F4356C312C204E40B05E2059407C8DC84683814663FB910969D1D631A952B381B7F635A33FD38D5CF15DF47D057F7FF555B555C2278100000A24804D7D98EB98602733818A12094F281287422CB40002464C92242004E0AE8518E001D124A7628010115D23C30462FC00A014A12133582A191E00538FC8A5004036A959ACB7A463D23E419EA06B744005385455A71250; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h6C60009CA281AEACDC1762945981B869F93D683EAF4AC7EE52412E85B60B91CD03AD0025F0D509F63202D877ECD8BF8005451F7BD346CF9E17B36F1850A7D80A8CF14A288EAE3BFE00FB2DB45080D4A50C58263A3B398DD51AB9CB554ECAA7B2E73D9D6D2C265859DB844C2C1952AD10241100174FE0444E6707D80A098D8585AAAC4802B74190FB007C0C0206186AFC1B3A2A46864F26118ED1D03ACB1062B7315502751655F60070E6B2C50609369611365AD1E3352327320331A51818030C7D8C4C59396600DC0C420495A0D987501490002BAD38012E20620D556A230B1796450B74E95A860FF3E434C65F1308F16F92395816B914F0CE870C1323347A4E; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h7FC8531A7A319F3EBFC1383FFCDB0E09BD288288B078B4AD220B6FA934CF6187D972662C0D31E34E63B31CFC6EB4B35A69B67D85489E62EA99899A94F6800FDBA5D31B86A0288D29CE2EAAFF86A6A9F7000082293E6BB54F06E98ECCB199973EDA00FADB1D3A630BA18050635DE7DCB13B9B86E0CE6E08DC46331A352F716E3C441A0CC068A0823F8668A00621B779DE35FEC004050469F34866AEE766743D8C00FDF3B9F8DE7B76E97F8D32F0F39E4CAC68D9BBB68EA3915F6225F932CAAFDAD6E60DC661155EC9E80F8CEE659F19CC554B2C67C33EDCDA63BAD91B7D1842A7177AF49DF118FE47ACE3344964EBCADCFBB543F7729CCB340866D1157B6CCDDB; -// synopsys translate_on - -// Location: M9K_X33_Y28_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a10 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(gnd), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[2]~46_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_first_bit_number = 2; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N12 -cycloneive_lcell_comb \D[2]~40 ( -// Equation(s): -// \D[2]~40_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))) # (!\z80_|address_pins_|abus[14]~23_combout -// & (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ))) - - .dataa(\z80_|address_pins_|abus[14]~23_combout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout ), - .cin(gnd), - .combout(\D[2]~40_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~40 .lut_mask = 16'hEA62; -defparam \D[2]~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y31_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a2 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[2]~46_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_bit_number = 2; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF00000000FFFFFFFFFFFFFFFFFFF68003FFF38003FFF9F403FFF8B003D8F87003FFF8F01BEDFC701FEBFEA01FDBFDC00FDBFDC01FC7FDC0FFC7FDE87FC7FCDC8FC7FCF89FC07071FFC0F873F3E0303FE7FFFFFFFFFFFFFFFF; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000000040078400234B1474928D1000000000000000000000000FFFFFFFF204081024004027153423DA5474928DD000000000000000000000000000000003FFFFFFF40041CB14162378547495999000000000000000000000000000000003FFFFFFF4004189141623485474959F90000000000000000000000003FFFFFFE40000001400400815B6223C15FC913DD0000000000000000000000007FFFFFFE40000001400402E9400333715FC973E5000000000000000000000000604081027FFFFFFD5FE60AE95763353540091361000000000000000000000000400000003FFFFFFC5FE60AE95763081D40011361; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h5FE0236948F816F55FE897C10C28028041DC8DE178059BC16900BB4173E47AC15FE8236148E806F55FE891054CA80E8148288DE179E597C169903AC153F13A8140080365486806D55FE891D548080A8148608FE159E493C16BB03FD152BD1AE14008037D482017D15FE881C548A00AC148E08FE159FC9AC16AA02FC15AAF18F1400083F1482007C15EE882C148E00A4148B08FE148F88D4168E436915ABB01E9400092F9480007815C2882C148E00B6149B49F614868FD41436476814AFA42A1400892FD480807C15C0883C149800FE149DC9FE14A60BD41431C3F914AEA01C1400882F1480817C11C0883C041940FE549CC9EE54860BDC143BC7D8108D2C4D0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h0B928870484885014DE84481680162815375AC0148D308813FFFFFFC400000004B9288314DC0970149FC44856C0166815375AC8140D108817FFFFFFD6040808249D0A2094F908581481C40814C016099417DA88140D10B01400000017FFFFFFE48D083394B9085814A085081440166814179900140510F01400000013FFFFFFE4A508335498001814BE0608146016E8941799041405107413FFFFFFF000000004B98812149C005814BE0628146836E814179100140510F013FFFFFFF000000004B98A1114BE801814A00668147832C814119904140401F4120408082FFFFFFFF48D881154EA801854800768147C22CC14019900100003E0000000000FFFFFFFF; -// synopsys translate_on - -// Location: M9K_X33_Y17_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a2 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h77A47C739FF6A22B8B5CDC49E748E9C739BDE6756DB4D22437E74183E12400CBF7D3C6CC8C7841AB49CC538E8A72F2E73C64D3DF3662B19C07D7D299CBEDEF3E7DA5F4A8458A9451315B681ADA9AB0D63218DFB77D3353C32837E954604B9D98144A4566F47B71715BE6CDB8BA64D536762E9224D70F9A5C374B4D1CAB8DF527027170C5DBCC2B6AD72B8E4CCC94DAA139D8BA64E3384337426E7F274CC88A373AB1F9007B8A7F2936D16274F9BF8B6BABD48FCE74047C1E738C5B303E815BA720C76D6362915156A7671331CE657011862E594E46A6D99392E2D640D766869389A4D43867379AB880C1ACE279E451CB3A9063A0B320F65E536B8EEF9CBB9C76; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h9A2921ED6AA0CC8387B267B9E7A182720833CEE061E6450C8E4A72E3C043F21A0AD007E832124E92429C091D167806C10041AF32DDE13A669990457D098CC2FE3AC884B1E69101135CD080022451F20884CCB9CD203C141402A5AD293C3BABA95ADFAF6726384795A7656B753D2369B9EB5595BAA722012DF8DCFBF15BF46D6EB755D1CBF0DCF6FD40BEEC16EAB4A6D16839C98CBE9DBB437C69FB709F8E79993B9DDFE4F823D6E124B75BCE9B29F799F926619184B6C1178389F07349210436293A130C900FBA4EA70D2BA25B343C5B026D8E8766A4E4267CDAEC99E830D2307D94E6ED80D6722F3989B91E31C63B64C363DCE71A861C14382E270FC02868C7; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h386BA04E797A3F8551DAD9D24A8D259A03ECFF5AB81B1C31DFDAE10100544F8CF1A8CCFC0C7A15BD9E7C2557CB00BF2584E16AAD13D7EDB525A85ABF90C0136DD195D748900C29DF7F381280A9738CDC3BF5BBF937D3A4D99CE2BCCD97CEF2C7F00030AFDB7F22E68CBAA4D9BE7633D3B53E90E4B124422A2A4454BACA5A8DC9352CD1DAFC910CC504334DF9E6F1F4F30161A36293CC5CCF1CA13994ED29D34A5699692496359B8E67A7E74D9A0FC504C8465638CF74A0AF9185921A7D2629893091900604017933442359491FBAB63F346F0C5EC8E3A531984B09E605A30A0627271C28420E47B8DEC74738FC3EDF9FBD40EC09FC7B4D3A1475BE433705FB5F; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h973FED2E9BEDBA474B70B121A8D60F3B4EE3F1A238FB3B730EDEEE74EC632DB4D7779D7B79D1C75DF87378E98719C1AF38B1B801C71D180CE86370AE9C2BF38CF84DBBB9878C55457324E92D3DAE91D729AC76BBAD4C6EECA74DAB5EE9A175EE34ABEB9DFAA48538A57E3E5C158947081CA41402E8E65478737F73BB629AAE2EE51D405CAF70F622DD4599602D7910DCAC8214B2A42025110593202C8B164C8DF6369572C3BB8AA1984A8D12F776E224ECEEB21F97FCD6C0CF17A044EC2BBF0571A553CCDD8ABA79BD27B7AF735ED2D34F1EF3A81A160C9ECB1B1FAE6EDEEFF99E28CC30C7C2553DED3378D655AD194B2E6C1BCBED700F6713D960F33E4C361A; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N16 -cycloneive_lcell_comb \D[2]~41 ( -// Equation(s): -// \D[2]~41_combout = (\z80_|address_pins_|abus[15]~22_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout $ (\D[2]~40_combout )))) # (!\z80_|address_pins_|abus[15]~22_combout & -// (\rom|altsyncram_component|auto_generated|ram_block1a2~portadataout & ((!\D[2]~40_combout )))) - - .dataa(\z80_|address_pins_|abus[15]~22_combout ), - .datab(\rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ), - .datad(\D[2]~40_combout ), - .cin(gnd), - .combout(\D[2]~41_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~41 .lut_mask = 16'h0AE4; -defparam \D[2]~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N30 -cycloneive_lcell_comb \D[2]~42 ( -// Equation(s): -// \D[2]~42_combout = (\D[2]~40_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout & !\D[2]~41_combout )))) # (!\D[2]~40_combout & -// (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[2]~41_combout )))) - - .dataa(\D[2]~40_combout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ), - .datad(\D[2]~41_combout ), - .cin(gnd), - .combout(\D[2]~42_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~42 .lut_mask = 16'h99A8; -defparam \D[2]~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N0 -cycloneive_lcell_comb \D[2]~105 ( -// Equation(s): -// \D[2]~105_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (\D[2]~44_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\D[2]~42_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & -// (\D[2]~44_combout )))) - - .dataa(\D[2]~44_combout ), - .datab(\z80_|address_pins_|DFFE_apin_latch [15]), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\D[2]~42_combout ), - .cin(gnd), - .combout(\D[2]~105_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~105 .lut_mask = 16'hBA8A; -defparam \D[2]~105 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N28 -cycloneive_lcell_comb \D[2]~45 ( -// Equation(s): -// \D[2]~45_combout = ((\Equal2~0_combout & (\D[2]~104_combout )) # (!\Equal2~0_combout & ((\D[2]~105_combout )))) # (!\Equal2~1_combout ) - - .dataa(\Equal2~0_combout ), - .datab(\Equal2~1_combout ), - .datac(\D[2]~104_combout ), - .datad(\D[2]~105_combout ), - .cin(gnd), - .combout(\D[2]~45_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~45 .lut_mask = 16'hF7B3; -defparam \D[2]~45 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|gdfx_temp0[3]~47 .lut_mask = 16'hF300; +defparam \z80_|reg_file_|gdfx_temp0[3]~47 .sum_lutc_input = "datac"; // synopsys translate_on // Location: LCCOMB_X31_Y12_N30 -cycloneive_lcell_comb \D[2]~46 ( +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder ( // Equation(s): -// \D[2]~46_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout & (\z80_|data_pins_|dout [2] & ((\D[2]~45_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\D[2]~45_combout ) # (!\Equal2~1_combout )))) +// \z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp0[3]~52_combout - .dataa(\z80_|data_pins_|dout [2]), - .datab(\Equal2~1_combout ), - .datac(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datad(\D[2]~45_combout ), + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), .cin(gnd), - .combout(\D[2]~46_combout ), + .combout(\z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder_combout ), .cout()); // synopsys translate_off -defparam \D[2]~46 .lut_mask = 16'hAF03; -defparam \D[2]~46 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N2 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [2] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[2]~13_combout ) # ((\z80_|pin_control_|bus_db_pin_re~combout & \D[2]~46_combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & -// (\z80_|pin_control_|bus_db_pin_re~combout & (\D[2]~46_combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(\z80_|pin_control_|bus_db_pin_re~combout ), - .datac(\D[2]~46_combout ), - .datad(\z80_|bus_control_|db[2]~13_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [2]), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] .lut_mask = 16'hEAC0; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y12_N3 -dffeas \z80_|data_pins_|dout[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [2]), +// Location: FF_X31_Y12_N31 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|data_pins_|dout [2]), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [3]), .prn(vcc)); // synopsys translate_off -defparam \z80_|data_pins_|dout[2] .is_wysiwyg = "true"; -defparam \z80_|data_pins_|dout[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N18 -cycloneive_lcell_comb \z80_|bus_control_|db[2]~12 ( -// Equation(s): -// \z80_|bus_control_|db[2]~12_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[2]~29_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) - - .dataa(gnd), - .datab(\z80_|alu_control_|db[2]~29_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|bus_control_|db[0]~4_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[2]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[2]~12 .lut_mask = 16'hCF00; -defparam \z80_|bus_control_|db[2]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N12 -cycloneive_lcell_comb \z80_|bus_control_|db[2]~13 ( -// Equation(s): -// \z80_|bus_control_|db[2]~13_combout = ((\z80_|bus_control_|db[2]~12_combout & ((\z80_|data_pins_|dout [2]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - - .dataa(\z80_|data_pins_|dout [2]), - .datab(\z80_|bus_control_|db[0]~6_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~combout ), - .datad(\z80_|bus_control_|db[2]~12_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[2]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[2]~13 .lut_mask = 16'hBF33; -defparam \z80_|bus_control_|db[2]~13 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[3] .power_up = "low"; // synopsys translate_on // Location: FF_X32_Y12_N13 -dffeas \z80_|ir_|opcode[2] ( +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[3] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|bus_control_|db[2]~13_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|ir_|opcode [2]), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [3]), .prn(vcc)); // synopsys translate_off -defparam \z80_|ir_|opcode[2] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[2] .power_up = "low"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X38_Y16_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal3~1 ( +// Location: LCCOMB_X32_Y12_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~49 ( // Equation(s): -// \z80_|pla_decode_|Equal3~1_combout = (\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [1]) +// \z80_|reg_file_|gdfx_temp0[3]~49_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [3]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_iy_lo|latch [3]), + .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~49_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~49 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[3]~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y11_N27 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N12 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp0[3]~52_combout .dataa(gnd), .datab(gnd), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal3~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal3~1 .lut_mask = 16'h00F0; -defparam \z80_|pla_decode_|Equal3~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N26 -cycloneive_lcell_comb \z80_|pla_decode_|Equal43~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal43~0_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal32~0_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal1~7_combout ))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|pla_decode_|Equal32~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal1~7_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal43~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal43~0 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal43~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N24 -cycloneive_lcell_comb \z80_|interrupts_|test1~2 ( -// Equation(s): -// \z80_|interrupts_|test1~2_combout = (!\z80_|pla_decode_|Equal43~0_combout & (!\z80_|pla_decode_|Equal3~2_combout & (!\z80_|pla_decode_|Equal79~0_combout & !\z80_|pla_decode_|Equal36~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal43~0_combout ), - .datab(\z80_|pla_decode_|Equal3~2_combout ), - .datac(\z80_|pla_decode_|Equal79~0_combout ), - .datad(\z80_|pla_decode_|Equal36~0_combout ), - .cin(gnd), - .combout(\z80_|interrupts_|test1~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|interrupts_|test1~2 .lut_mask = 16'h0001; -defparam \z80_|interrupts_|test1~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N26 -cycloneive_lcell_comb \z80_|interrupts_|test1~3 ( -// Equation(s): -// \z80_|interrupts_|test1~3_combout = (!\z80_|execute_|setM1~52_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((\z80_|interrupts_|test1~2_combout ) # (!\z80_|sequencer_|DFFE_T4_ff~q )))) - - .dataa(\z80_|execute_|setM1~52_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|interrupts_|test1~2_combout ), - .cin(gnd), - .combout(\z80_|interrupts_|test1~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|interrupts_|test1~3 .lut_mask = 16'h5545; -defparam \z80_|interrupts_|test1~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y15_N13 -dffeas \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|interrupts_|test1~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED .is_wysiwyg = "true"; -defparam \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N2 -cycloneive_lcell_comb \z80_|clk_delay_|SYNTHESIZED_WIRE_4 ( -// Equation(s): -// \z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (!\z80_|sequencer_|DFFE_M1_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|interrupts_|DFFE_inst44~q ))) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|interrupts_|DFFE_inst44~q ), - .cin(gnd), - .combout(\z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_4 .lut_mask = 16'h0100; -defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X43_Y15_N3 -dffeas \z80_|clk_delay_|SYNTHESIZED_WIRE_7 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_7 .is_wysiwyg = "true"; -defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_7 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N20 -cycloneive_lcell_comb \z80_|clk_delay_|hold_clk_iorq ( -// Equation(s): -// \z80_|clk_delay_|hold_clk_iorq~combout = (!\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q & !\z80_|clk_delay_|DFF_inst5~q ) - - .dataa(gnd), - .datab(\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ), .datac(gnd), - .datad(\z80_|clk_delay_|DFF_inst5~q ), + .datad(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), .cin(gnd), - .combout(\z80_|clk_delay_|hold_clk_iorq~combout ), + .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder_combout ), .cout()); // synopsys translate_off -defparam \z80_|clk_delay_|hold_clk_iorq .lut_mask = 16'h0033; -defparam \z80_|clk_delay_|hold_clk_iorq .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y17_N13 -dffeas \z80_|sequencer_|DFFE_T1_ff ( +// Location: FF_X32_Y11_N13 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[3] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|ena_M~combout ), + .d(\z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder_combout ), .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|sequencer_|DFFE_T1_ff~q ), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [3]), .prn(vcc)); // synopsys translate_off -defparam \z80_|sequencer_|DFFE_T1_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_T1_ff .power_up = "low"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y17_N4 -cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_13 ( +// Location: LCCOMB_X32_Y11_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~45 ( // Equation(s): -// \z80_|sequencer_|SYNTHESIZED_WIRE_13~combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|execute_|setM1~52_combout & !\z80_|execute_|nextM~14_combout )) +// \z80_|reg_file_|gdfx_temp0[3]~45_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(gnd), - .datac(\z80_|execute_|setM1~52_combout ), - .datad(\z80_|execute_|nextM~14_combout ), + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [3]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [3]), .cin(gnd), - .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ), + .combout(\z80_|reg_file_|gdfx_temp0[3]~45_combout ), .cout()); // synopsys translate_off -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_13 .lut_mask = 16'h0050; -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_13 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|gdfx_temp0[3]~45 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[3]~45 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y17_N5 -dffeas \z80_|sequencer_|DFFE_T2_ff ( +// Location: FF_X32_Y13_N17 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[3] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|sequencer_|DFFE_T2_ff~q ), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [3]), .prn(vcc)); // synopsys translate_off -defparam \z80_|sequencer_|DFFE_T2_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_T2_ff .power_up = "low"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X35_Y13_N10 -cycloneive_lcell_comb \z80_|resets_|x3 ( -// Equation(s): -// \z80_|resets_|x3~combout = (\z80_|resets_|x1~q ) # ((\z80_|sequencer_|DFFE_T2_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )) +// Location: FF_X32_Y14_N15 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[3] .power_up = "low"; +// synopsys translate_on - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(gnd), - .datac(\z80_|resets_|x1~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), +// Location: LCCOMB_X32_Y14_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~48 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~48_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (\z80_|reg_file_|b2v_latch_ix_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_ix_lo|latch [3]), + .datac(\z80_|reg_file_|b2v_latch_bc_lo|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), .cin(gnd), - .combout(\z80_|resets_|x3~combout ), + .combout(\z80_|reg_file_|gdfx_temp0[3]~48_combout ), .cout()); // synopsys translate_off -defparam \z80_|resets_|x3 .lut_mask = 16'hF0FA; -defparam \z80_|resets_|x3 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|gdfx_temp0[3]~48 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp0[3]~48 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X35_Y13_N11 -dffeas \z80_|resets_|SYNTHESIZED_WIRE_12 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|resets_|x3~combout ), - .asdata(vcc), - .clrn(\z80_|fpga_reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_12 .is_wysiwyg = "true"; -defparam \z80_|resets_|SYNTHESIZED_WIRE_12 .power_up = "low"; -// synopsys translate_on - -// Location: CLKCTRL_G7 -cycloneive_clkctrl \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl ( - .ena(vcc), - .inclk({vcc,vcc,vcc,\z80_|resets_|SYNTHESIZED_WIRE_12~q }), - .clkselect(2'b00), - .devclrn(devclrn), - .devpor(devpor), - .outclk(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk )); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl .clock_type = "global clock"; -defparam \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl .ena_register_mode = "none"; -// synopsys translate_on - -// Location: FF_X32_Y17_N21 -dffeas \z80_|sequencer_|DFFE_M1_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|DFFE_M1_ff~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|DFFE_M1_ff~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_M1_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_M1_ff .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N10 -cycloneive_lcell_comb \z80_|sequencer_|DFFE_M2_ff~0 ( +// Location: LCCOMB_X32_Y11_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~50 ( // Equation(s): -// \z80_|sequencer_|DFFE_M2_ff~0_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|execute_|nextM~14_combout & (!\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|DFFE_M2_ff~q ))))) +// \z80_|reg_file_|gdfx_temp0[3]~50_combout = (\z80_|reg_file_|gdfx_temp0[3]~47_combout & (\z80_|reg_file_|gdfx_temp0[3]~49_combout & (\z80_|reg_file_|gdfx_temp0[3]~45_combout & \z80_|reg_file_|gdfx_temp0[3]~48_combout ))) - .dataa(\z80_|execute_|setM1~52_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|execute_|nextM~14_combout ), + .dataa(\z80_|reg_file_|gdfx_temp0[3]~47_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[3]~49_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[3]~45_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[3]~48_combout ), .cin(gnd), - .combout(\z80_|sequencer_|DFFE_M2_ff~0_combout ), + .combout(\z80_|reg_file_|gdfx_temp0[3]~50_combout ), .cout()); // synopsys translate_off -defparam \z80_|sequencer_|DFFE_M2_ff~0 .lut_mask = 16'h22A0; -defparam \z80_|sequencer_|DFFE_M2_ff~0 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|gdfx_temp0[3]~50 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[3]~50 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y17_N11 -dffeas \z80_|sequencer_|DFFE_M2_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|DFFE_M2_ff~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|DFFE_M2_ff~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_M2_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_M2_ff .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~3 ( +// Location: LCCOMB_X31_Y11_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~51 ( // Equation(s): -// \z80_|execute_|ctl_mWrite~3_combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ) +// \z80_|reg_file_|gdfx_temp0[3]~51_combout = (\z80_|reg_file_|gdfx_temp0[3]~44_combout & (\z80_|reg_file_|gdfx_temp0[3]~43_combout & \z80_|reg_file_|gdfx_temp0[3]~50_combout )) + + .dataa(\z80_|reg_file_|gdfx_temp0[3]~44_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[3]~43_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[3]~50_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~51 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|gdfx_temp0[3]~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~52 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~52_combout = ((\z80_|reg_file_|gdfx_temp0[3]~51_combout & ((\z80_|reg_file_|db_lo_as[3]~12_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), + .datac(\z80_|reg_file_|db_lo_as[3]~12_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~52 .lut_mask = 16'hC4FF; +defparam \z80_|reg_file_|gdfx_temp0[3]~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N20 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_35 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout = (\z80_|execute_|ctl_flags_bus~combout & ((\z80_|alu_control_|db[3]~35_combout ) # ((\z80_|execute_|ctl_flags_alu~15_combout & \z80_|alu_|db_low[3]~25_combout )))) # (!\z80_|execute_|ctl_flags_bus~combout +// & (((\z80_|execute_|ctl_flags_alu~15_combout & \z80_|alu_|db_low[3]~25_combout )))) + + .dataa(\z80_|execute_|ctl_flags_bus~combout ), + .datab(\z80_|alu_control_|db[3]~35_combout ), + .datac(\z80_|execute_|ctl_flags_alu~15_combout ), + .datad(\z80_|alu_|db_low[3]~25_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_35 .lut_mask = 16'hF888; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~15 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~15_combout = (\z80_|execute_|ctl_state_alu~2_combout & ((\z80_|execute_|ctl_ir_we~12_combout ) # ((\z80_|execute_|ctl_alu_op_low~22_combout & \z80_|pla_decode_|Equal56~0_combout )))) # +// (!\z80_|execute_|ctl_state_alu~2_combout & (\z80_|execute_|ctl_alu_op_low~22_combout & (\z80_|pla_decode_|Equal56~0_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datac(\z80_|pla_decode_|Equal56~0_combout ), + .datad(\z80_|execute_|ctl_ir_we~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~15 .lut_mask = 16'hEAC0; +defparam \z80_|execute_|ctl_flags_xy_we~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~16 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~16_combout = (\z80_|execute_|ctl_flags_xy_we~15_combout ) # ((\z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ) # (!\z80_|execute_|ctl_flags_xy_we~12_combout )) .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|execute_|ctl_flags_xy_we~15_combout ), + .datac(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~12_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~3_combout ), + .combout(\z80_|execute_|ctl_flags_xy_we~16_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~3 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_mWrite~3 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_flags_xy_we~16 .lut_mask = 16'hFCFF; +defparam \z80_|execute_|ctl_flags_xy_we~16 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X41_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|nextM~11 ( +// Location: LCCOMB_X28_Y18_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~17 ( // Equation(s): -// \z80_|execute_|nextM~11_combout = ((!\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_alu_op_low~12_combout & !\z80_|execute_|ctl_alu_op_low~11_combout ))) # (!\z80_|execute_|ctl_mWrite~3_combout ) +// \z80_|execute_|ctl_flags_xy_we~17_combout = (\z80_|execute_|ctl_flags_xy_we~16_combout ) # (((!\z80_|execute_|ctl_flags_xy_we~19_combout ) # (!\z80_|execute_|ctl_flags_xy_we~9_combout )) # (!\z80_|execute_|ctl_flags_xy_we~11_combout )) - .dataa(\z80_|execute_|ctl_mWrite~3_combout ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~12_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~11_combout ), + .dataa(\z80_|execute_|ctl_flags_xy_we~16_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~11_combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~9_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~19_combout ), .cin(gnd), - .combout(\z80_|execute_|nextM~11_combout ), + .combout(\z80_|execute_|ctl_flags_xy_we~17_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|nextM~11 .lut_mask = 16'h5557; -defparam \z80_|execute_|nextM~11 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_flags_xy_we~17 .lut_mask = 16'hBFFF; +defparam \z80_|execute_|ctl_flags_xy_we~17 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X40_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|nextM~8 ( +// Location: LCCOMB_X28_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~18 ( // Equation(s): -// \z80_|execute_|nextM~8_combout = (\z80_|alu_control_|flags_cond_true~q & (((\z80_|execute_|ixy_d~8_combout & !\z80_|execute_|ctl_flags_bus~5_combout )))) # (!\z80_|alu_control_|flags_cond_true~q & ((\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout -// ) # ((\z80_|execute_|ixy_d~8_combout & !\z80_|execute_|ctl_flags_bus~5_combout )))) +// \z80_|execute_|ctl_flags_xy_we~18_combout = ((\z80_|execute_|ctl_flags_xy_we~17_combout ) # ((!\z80_|execute_|ctl_flags_pf_we~4_combout ) # (!\z80_|execute_|ctl_pf_sel[0]~3_combout ))) # (!\z80_|execute_|ctl_flags_sz_we~7_combout ) - .dataa(\z80_|alu_control_|flags_cond_true~q ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), - .datac(\z80_|execute_|ixy_d~8_combout ), - .datad(\z80_|execute_|ctl_flags_bus~5_combout ), + .dataa(\z80_|execute_|ctl_flags_sz_we~7_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~17_combout ), + .datac(\z80_|execute_|ctl_pf_sel[0]~3_combout ), + .datad(\z80_|execute_|ctl_flags_pf_we~4_combout ), .cin(gnd), - .combout(\z80_|execute_|nextM~8_combout ), + .combout(\z80_|execute_|ctl_flags_xy_we~18_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|nextM~8 .lut_mask = 16'h44F4; -defparam \z80_|execute_|nextM~8 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_flags_xy_we~18 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_flags_xy_we~18 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|nextM~9 ( -// Equation(s): -// \z80_|execute_|nextM~9_combout = (\z80_|execute_|ctl_mWrite~2_combout & (\z80_|pla_decode_|Equal55~0_combout & ((\z80_|execute_|ctl_mRead~11_combout ) # (\z80_|execute_|ixy_d~6_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~2_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|execute_|ctl_mRead~11_combout ), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~9 .lut_mask = 16'h8880; -defparam \z80_|execute_|nextM~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|nextM~10 ( -// Equation(s): -// \z80_|execute_|nextM~10_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ) # ((\z80_|execute_|nextM~9_combout ) # ((\z80_|execute_|ctl_mRead~36_combout & \z80_|execute_|ixy_d~9_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .datab(\z80_|execute_|nextM~9_combout ), - .datac(\z80_|execute_|ctl_mRead~36_combout ), - .datad(\z80_|execute_|ixy_d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~10 .lut_mask = 16'hFEEE; -defparam \z80_|execute_|nextM~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|nextM~12 ( -// Equation(s): -// \z80_|execute_|nextM~12_combout = ((\z80_|execute_|nextM~8_combout ) # ((\z80_|execute_|nextM~10_combout ) # (\z80_|execute_|ctl_alu_op_low~32_combout ))) # (!\z80_|execute_|nextM~11_combout ) - - .dataa(\z80_|execute_|nextM~11_combout ), - .datab(\z80_|execute_|nextM~8_combout ), - .datac(\z80_|execute_|nextM~10_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~12 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|nextM~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N22 -cycloneive_lcell_comb \z80_|execute_|nextM~15 ( -// Equation(s): -// \z80_|execute_|nextM~15_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & ((\z80_|execute_|ctl_mRead~7_combout ) # (!\z80_|execute_|fMRead~10_combout )))) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|execute_|ctl_mRead~7_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|execute_|fMRead~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~15 .lut_mask = 16'h80A0; -defparam \z80_|execute_|nextM~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N8 -cycloneive_lcell_comb \z80_|execute_|nextM~6 ( -// Equation(s): -// \z80_|execute_|nextM~6_combout = (((\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal49~0_combout )) # (!\z80_|execute_|nextM~3_combout )) # (!\z80_|execute_|ixy_d~17_combout ) - - .dataa(\z80_|execute_|ixy_d~17_combout ), - .datab(\z80_|decode_state_|use_ixiy~combout ), - .datac(\z80_|execute_|nextM~3_combout ), - .datad(\z80_|pla_decode_|Equal49~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~6 .lut_mask = 16'hDF5F; -defparam \z80_|execute_|nextM~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N6 -cycloneive_lcell_comb \z80_|execute_|nextM~7 ( -// Equation(s): -// \z80_|execute_|nextM~7_combout = ((\z80_|execute_|nextM~6_combout & ((\z80_|execute_|ixy_d~8_combout ) # (\z80_|execute_|ctl_state_alu~4_combout )))) # (!\z80_|execute_|nextM~4_combout ) - - .dataa(\z80_|execute_|ixy_d~8_combout ), - .datab(\z80_|execute_|nextM~6_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|nextM~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~7 .lut_mask = 16'hC8FF; -defparam \z80_|execute_|nextM~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N6 -cycloneive_lcell_comb \z80_|execute_|nextM~13 ( -// Equation(s): -// \z80_|execute_|nextM~13_combout = (\z80_|execute_|nextM~12_combout ) # ((\z80_|execute_|nextM~15_combout ) # (\z80_|execute_|nextM~7_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|nextM~12_combout ), - .datac(\z80_|execute_|nextM~15_combout ), - .datad(\z80_|execute_|nextM~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~13 .lut_mask = 16'hFFFC; -defparam \z80_|execute_|nextM~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N12 -cycloneive_lcell_comb \z80_|execute_|setM1~39 ( -// Equation(s): -// \z80_|execute_|setM1~39_combout = (!\z80_|execute_|ctl_mWrite~5_combout & \z80_|execute_|setM1~38_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_mWrite~5_combout ), - .datad(\z80_|execute_|setM1~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~39 .lut_mask = 16'h0F00; -defparam \z80_|execute_|setM1~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N6 -cycloneive_lcell_comb \z80_|execute_|nextM~5 ( -// Equation(s): -// \z80_|execute_|nextM~5_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (((!\z80_|execute_|setM1~45_combout ) # (!\z80_|execute_|nextM~2_combout )) # (!\z80_|execute_|setM1~39_combout ))) - - .dataa(\z80_|execute_|setM1~39_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|nextM~2_combout ), - .datad(\z80_|execute_|setM1~45_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~5 .lut_mask = 16'h4CCC; -defparam \z80_|execute_|nextM~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|nextM~14 ( -// Equation(s): -// \z80_|execute_|nextM~14_combout = (\z80_|execute_|nextM~13_combout ) # (((\z80_|execute_|nextM~5_combout ) # (!\z80_|execute_|ctl_mRead~30_combout )) # (!\z80_|execute_|ctl_mWrite~13_combout )) - - .dataa(\z80_|execute_|nextM~13_combout ), - .datab(\z80_|execute_|ctl_mWrite~13_combout ), - .datac(\z80_|execute_|ctl_mRead~30_combout ), - .datad(\z80_|execute_|nextM~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~14 .lut_mask = 16'hFFBF; -defparam \z80_|execute_|nextM~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N14 -cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_15 ( -// Equation(s): -// \z80_|sequencer_|SYNTHESIZED_WIRE_15~combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|execute_|setM1~52_combout & !\z80_|execute_|nextM~14_combout )) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|execute_|setM1~52_combout ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_15 .lut_mask = 16'h00C0; -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y17_N15 -dffeas \z80_|sequencer_|DFFE_T4_ff ( +// Location: FF_X31_Y15_N21 +dffeas \z80_|alu_flags_|flags_xf ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ), + .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ), .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .ena(\z80_|execute_|ctl_flags_xy_we~18_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|sequencer_|DFFE_T4_ff~q ), + .q(\z80_|alu_flags_|flags_xf~q ), .prn(vcc)); // synopsys translate_off -defparam \z80_|sequencer_|DFFE_T4_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_T4_ff .power_up = "low"; +defparam \z80_|alu_flags_|flags_xf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|flags_xf .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y17_N18 -cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_16 ( +// Location: LCCOMB_X31_Y15_N30 +cycloneive_lcell_comb \z80_|alu_control_|db[3]~33 ( // Equation(s): -// \z80_|sequencer_|SYNTHESIZED_WIRE_16~combout = (\z80_|execute_|setM1~52_combout & (\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|execute_|nextM~14_combout )) - - .dataa(\z80_|execute_|setM1~52_combout ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_16 .lut_mask = 16'h00A0; -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y17_N19 -dffeas \z80_|sequencer_|DFFE_T5_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|DFFE_T5_ff~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_T5_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_T5_ff .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N26 -cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_17 ( -// Equation(s): -// \z80_|sequencer_|SYNTHESIZED_WIRE_17~combout = (\z80_|sequencer_|DFFE_T5_ff~q & (\z80_|execute_|setM1~52_combout & !\z80_|execute_|nextM~14_combout )) +// \z80_|alu_control_|db[3]~33_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & ((\z80_|alu_flags_|flags_xf~q ) # (!\z80_|execute_|ctl_flags_oe~2_combout ))) .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T5_ff~q ), - .datac(\z80_|execute_|setM1~52_combout ), - .datad(\z80_|execute_|nextM~14_combout ), + .datab(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .datac(\z80_|execute_|ctl_flags_oe~2_combout ), + .datad(\z80_|alu_flags_|flags_xf~q ), .cin(gnd), - .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_17~combout ), + .combout(\z80_|alu_control_|db[3]~33_combout ), .cout()); // synopsys translate_off -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_17 .lut_mask = 16'h00C0; -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_17 .sum_lutc_input = "datac"; +defparam \z80_|alu_control_|db[3]~33 .lut_mask = 16'hCC0C; +defparam \z80_|alu_control_|db[3]~33 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y17_N27 -dffeas \z80_|sequencer_|T6 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|SYNTHESIZED_WIRE_17~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|T6~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|T6 .is_wysiwyg = "true"; -defparam \z80_|sequencer_|T6 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|setM1~13 ( +// Location: LCCOMB_X31_Y14_N20 +cycloneive_lcell_comb \z80_|sw1_|db_down[3]~2 ( // Equation(s): -// \z80_|execute_|setM1~13_combout = (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|pla_decode_|Equal33~0_combout & ((!\z80_|pla_decode_|Equal32~0_combout ) # (!\z80_|pla_decode_|Equal21~2_combout )))) # (!\z80_|pla_decode_|Equal13~0_combout & -// (((!\z80_|pla_decode_|Equal32~0_combout )) # (!\z80_|pla_decode_|Equal21~2_combout ))) +// \z80_|sw1_|db_down[3]~2_combout = (\z80_|bus_control_|db[3]~21_combout ) # ((\z80_|execute_|ctl_sw_1d~6_combout & ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|execute_|ctl_66_oe~2_combout )))) - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|pla_decode_|Equal21~2_combout ), - .datac(\z80_|pla_decode_|Equal32~0_combout ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~13 .lut_mask = 16'h153F; -defparam \z80_|execute_|setM1~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal77~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal77~1_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal21~0_combout & (\z80_|pla_decode_|Equal77~0_combout & \z80_|pla_decode_|Equal33~0_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|pla_decode_|Equal21~0_combout ), - .datac(\z80_|pla_decode_|Equal77~0_combout ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal77~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal77~1 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal77~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|setM1~12 ( -// Equation(s): -// \z80_|execute_|setM1~12_combout = (!\z80_|pla_decode_|Equal77~1_combout & (!\z80_|execute_|ctl_alu_oe~3_combout & (!\z80_|pla_decode_|Equal1~6_combout & !\z80_|pla_decode_|Equal2~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal77~1_combout ), - .datab(\z80_|execute_|ctl_alu_oe~3_combout ), - .datac(\z80_|pla_decode_|Equal1~6_combout ), - .datad(\z80_|pla_decode_|Equal2~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~12 .lut_mask = 16'h0001; -defparam \z80_|execute_|setM1~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|setM1~14 ( -// Equation(s): -// \z80_|execute_|setM1~14_combout = (\z80_|execute_|setM1~13_combout & (\z80_|interrupts_|test1~2_combout & \z80_|execute_|setM1~12_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|setM1~13_combout ), - .datac(\z80_|interrupts_|test1~2_combout ), - .datad(\z80_|execute_|setM1~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~14 .lut_mask = 16'hC000; -defparam \z80_|execute_|setM1~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|setM1~41 ( -// Equation(s): -// \z80_|execute_|setM1~41_combout = (!\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_mWrite~4_combout & !\z80_|execute_|ctl_ir_we~10_combout )) - - .dataa(\z80_|execute_|ctl_ir_we~9_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|execute_|ctl_ir_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~41 .lut_mask = 16'h0005; -defparam \z80_|execute_|setM1~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|setM1~42 ( -// Equation(s): -// \z80_|execute_|setM1~42_combout = (!\z80_|pla_decode_|Equal38~2_combout & (!\z80_|pla_decode_|Equal37~0_combout & (!\z80_|pla_decode_|Equal47~0_combout & \z80_|sequencer_|DFFE_T4_ff~q ))) - - .dataa(\z80_|pla_decode_|Equal38~2_combout ), - .datab(\z80_|pla_decode_|Equal37~0_combout ), - .datac(\z80_|pla_decode_|Equal47~0_combout ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~42 .lut_mask = 16'h0100; -defparam \z80_|execute_|setM1~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|setM1~43 ( -// Equation(s): -// \z80_|execute_|setM1~43_combout = (!\z80_|pla_decode_|Equal21~1_combout & (\z80_|execute_|setM1~41_combout & (!\z80_|pla_decode_|Equal48~0_combout & \z80_|execute_|setM1~42_combout ))) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|execute_|setM1~41_combout ), - .datac(\z80_|pla_decode_|Equal48~0_combout ), - .datad(\z80_|execute_|setM1~42_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~43 .lut_mask = 16'h0400; -defparam \z80_|execute_|setM1~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N26 -cycloneive_lcell_comb \z80_|execute_|setM1~44 ( -// Equation(s): -// \z80_|execute_|setM1~44_combout = (\z80_|execute_|setM1~43_combout & (\z80_|execute_|setM1~40_combout & ((!\z80_|pla_decode_|Equal2~1_combout ) # (!\z80_|pla_decode_|Equal1~4_combout )))) - - .dataa(\z80_|execute_|setM1~43_combout ), - .datab(\z80_|pla_decode_|Equal1~4_combout ), - .datac(\z80_|execute_|setM1~40_combout ), - .datad(\z80_|pla_decode_|Equal2~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~44 .lut_mask = 16'h20A0; -defparam \z80_|execute_|setM1~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N20 -cycloneive_lcell_comb \z80_|execute_|setM1~50 ( -// Equation(s): -// \z80_|execute_|setM1~50_combout = (\z80_|execute_|setM1~46_combout & (\z80_|execute_|setM1~14_combout & (\z80_|execute_|setM1~44_combout & \z80_|execute_|setM1~49_combout ))) - - .dataa(\z80_|execute_|setM1~46_combout ), - .datab(\z80_|execute_|setM1~14_combout ), - .datac(\z80_|execute_|setM1~44_combout ), - .datad(\z80_|execute_|setM1~49_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~50 .lut_mask = 16'h8000; -defparam \z80_|execute_|setM1~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|setM1~51 ( -// Equation(s): -// \z80_|execute_|setM1~51_combout = (\z80_|sequencer_|T6~q & (((\z80_|execute_|setM1~50_combout & \z80_|execute_|setM1~39_combout )) # (!\z80_|execute_|setM1~40_combout ))) # (!\z80_|sequencer_|T6~q & (\z80_|execute_|setM1~50_combout & -// ((\z80_|execute_|setM1~39_combout )))) - - .dataa(\z80_|sequencer_|T6~q ), - .datab(\z80_|execute_|setM1~50_combout ), - .datac(\z80_|execute_|setM1~40_combout ), - .datad(\z80_|execute_|setM1~39_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~51_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~51 .lut_mask = 16'hCE0A; -defparam \z80_|execute_|setM1~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N2 -cycloneive_lcell_comb \z80_|execute_|setM1~6 ( -// Equation(s): -// \z80_|execute_|setM1~6_combout = (\z80_|execute_|ctl_al_we~13_combout & (\z80_|sequencer_|M5~q & (\z80_|pla_decode_|Equal9~1_combout ))) # (!\z80_|execute_|ctl_al_we~13_combout & ((\z80_|sequencer_|DFFE_M4_ff~q ) # ((\z80_|sequencer_|M5~q & -// \z80_|pla_decode_|Equal9~1_combout )))) - - .dataa(\z80_|execute_|ctl_al_we~13_combout ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|sequencer_|DFFE_M4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~6 .lut_mask = 16'hD5C0; -defparam \z80_|execute_|setM1~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N12 -cycloneive_lcell_comb \z80_|execute_|setM1~7 ( -// Equation(s): -// \z80_|execute_|setM1~7_combout = ((\z80_|sequencer_|DFFE_T5_ff~q & \z80_|execute_|setM1~6_combout )) # (!\z80_|execute_|ctl_flags_xy_we~16_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_flags_xy_we~16_combout ), - .datac(\z80_|sequencer_|DFFE_T5_ff~q ), - .datad(\z80_|execute_|setM1~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~7 .lut_mask = 16'hF333; -defparam \z80_|execute_|setM1~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N0 -cycloneive_lcell_comb \z80_|execute_|setM1~8 ( -// Equation(s): -// \z80_|execute_|setM1~8_combout = (\z80_|execute_|ctl_mWrite~4_combout ) # ((\z80_|execute_|ctl_mRead~7_combout ) # ((\z80_|pla_decode_|Equal6~1_combout ) # (!\z80_|execute_|fMWrite~3_combout ))) - - .dataa(\z80_|execute_|ctl_mWrite~4_combout ), - .datab(\z80_|execute_|ctl_mRead~7_combout ), - .datac(\z80_|pla_decode_|Equal6~1_combout ), - .datad(\z80_|execute_|fMWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~8 .lut_mask = 16'hFEFF; -defparam \z80_|execute_|setM1~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N10 -cycloneive_lcell_comb \z80_|execute_|setM1~9 ( -// Equation(s): -// \z80_|execute_|setM1~9_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ) # ((!\z80_|ir_|opcode [4] & (!\z80_|ir_|opcode [2] & \z80_|execute_|ctl_mWrite~2_combout ))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [2]), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .datad(\z80_|execute_|ctl_mWrite~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~9 .lut_mask = 16'hF1F0; -defparam \z80_|execute_|setM1~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N10 -cycloneive_lcell_comb \z80_|execute_|setM1~10 ( -// Equation(s): -// \z80_|execute_|setM1~10_combout = ((\z80_|execute_|setM1~8_combout ) # ((\z80_|execute_|ctl_mWrite~16_combout & \z80_|execute_|setM1~9_combout ))) # (!\z80_|execute_|nextM~2_combout ) - - .dataa(\z80_|execute_|ctl_mWrite~16_combout ), - .datab(\z80_|execute_|nextM~2_combout ), - .datac(\z80_|execute_|setM1~8_combout ), - .datad(\z80_|execute_|setM1~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~10 .lut_mask = 16'hFBF3; -defparam \z80_|execute_|setM1~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N26 -cycloneive_lcell_comb \z80_|execute_|setM1~11 ( -// Equation(s): -// \z80_|execute_|setM1~11_combout = (\z80_|execute_|setM1~7_combout ) # (((\z80_|execute_|ixy_d~6_combout & \z80_|execute_|setM1~10_combout )) # (!\z80_|reg_control_|reg_sel_pc~3_combout )) - - .dataa(\z80_|execute_|setM1~7_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|execute_|setM1~10_combout ), - .datad(\z80_|reg_control_|reg_sel_pc~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~11 .lut_mask = 16'hEAFF; -defparam \z80_|execute_|setM1~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|setM1~17 ( -// Equation(s): -// \z80_|execute_|setM1~17_combout = ((\z80_|execute_|setM1~11_combout ) # ((!\z80_|execute_|setM1~14_combout & \z80_|execute_|ctl_eval_cond~0_combout ))) # (!\z80_|execute_|setM1~16_combout ) - - .dataa(\z80_|execute_|setM1~16_combout ), - .datab(\z80_|execute_|setM1~14_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|setM1~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~17 .lut_mask = 16'hFF75; -defparam \z80_|execute_|setM1~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N16 -cycloneive_lcell_comb \z80_|execute_|setM1~31 ( -// Equation(s): -// \z80_|execute_|setM1~31_combout = (\z80_|pla_decode_|Equal35~0_combout & ((\z80_|execute_|ixy_d~6_combout ) # ((\z80_|execute_|ctl_reg_in_hi~2_combout & \z80_|execute_|ctl_mRead~18_combout )))) # (!\z80_|pla_decode_|Equal35~0_combout & -// (\z80_|execute_|ctl_reg_in_hi~2_combout & ((\z80_|execute_|ctl_mRead~18_combout )))) - - .dataa(\z80_|pla_decode_|Equal35~0_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|execute_|ctl_mRead~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~31 .lut_mask = 16'hECA0; -defparam \z80_|execute_|setM1~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N2 -cycloneive_lcell_comb \z80_|execute_|setM1~28 ( -// Equation(s): -// \z80_|execute_|setM1~28_combout = ((\z80_|execute_|ctl_mRead~9_combout ) # ((\z80_|execute_|ctl_mRead~15_combout ) # (\z80_|execute_|ctl_mRead~7_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), - .datab(\z80_|execute_|ctl_mRead~9_combout ), - .datac(\z80_|execute_|ctl_mRead~15_combout ), - .datad(\z80_|execute_|ctl_mRead~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~28 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|setM1~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|setM1~30 ( -// Equation(s): -// \z80_|execute_|setM1~30_combout = (((\z80_|execute_|ctl_state_alu~6_combout & \z80_|execute_|setM1~28_combout )) # (!\z80_|execute_|setM1~29_combout )) # (!\z80_|execute_|setM1~54_combout ) - - .dataa(\z80_|execute_|setM1~54_combout ), - .datab(\z80_|execute_|setM1~29_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|setM1~28_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~30 .lut_mask = 16'hF777; -defparam \z80_|execute_|setM1~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N10 -cycloneive_lcell_comb \z80_|execute_|setM1~32 ( -// Equation(s): -// \z80_|execute_|setM1~32_combout = (\z80_|execute_|ctl_mRead~5_combout ) # ((\z80_|execute_|ctl_mRead~4_combout ) # ((\z80_|execute_|setM1~9_combout & \z80_|execute_|ctl_mRead~36_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~5_combout ), - .datab(\z80_|execute_|setM1~9_combout ), - .datac(\z80_|execute_|ctl_mRead~36_combout ), - .datad(\z80_|execute_|ctl_mRead~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~32 .lut_mask = 16'hFFEA; -defparam \z80_|execute_|setM1~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N8 -cycloneive_lcell_comb \z80_|execute_|setM1~33 ( -// Equation(s): -// \z80_|execute_|setM1~33_combout = (\z80_|execute_|setM1~31_combout ) # ((\z80_|execute_|setM1~30_combout ) # ((\z80_|execute_|ixy_d~9_combout & \z80_|execute_|setM1~32_combout ))) - - .dataa(\z80_|execute_|setM1~31_combout ), - .datab(\z80_|execute_|setM1~30_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|execute_|setM1~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~33 .lut_mask = 16'hFEEE; -defparam \z80_|execute_|setM1~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|setM1~25 ( -// Equation(s): -// \z80_|execute_|setM1~25_combout = ((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & \z80_|pla_decode_|Equal21~1_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), - .datad(\z80_|pla_decode_|Equal21~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~25 .lut_mask = 16'hAF0F; -defparam \z80_|execute_|setM1~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|setM1~26 ( -// Equation(s): -// \z80_|execute_|setM1~26_combout = ((\z80_|execute_|ctl_mRead~13_combout ) # ((!\z80_|alu_control_|flags_cond_true~q & \z80_|pla_decode_|Equal40~1_combout ))) # (!\z80_|execute_|ctl_bus_inc_oe~29_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~29_combout ), - .datab(\z80_|alu_control_|flags_cond_true~q ), - .datac(\z80_|execute_|ctl_mRead~13_combout ), - .datad(\z80_|pla_decode_|Equal40~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~26 .lut_mask = 16'hF7F5; -defparam \z80_|execute_|setM1~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|setM1~24 ( -// Equation(s): -// \z80_|execute_|setM1~24_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & (((\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & !\z80_|alu_control_|flags_cond_true~q )) # (!\z80_|execute_|ctl_mRead~12_combout ))) # -// (!\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & (\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & ((!\z80_|alu_control_|flags_cond_true~q )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), - .datac(\z80_|execute_|ctl_mRead~12_combout ), - .datad(\z80_|alu_control_|flags_cond_true~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~24 .lut_mask = 16'h0ACE; -defparam \z80_|execute_|setM1~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N18 -cycloneive_lcell_comb \z80_|execute_|setM1~27 ( -// Equation(s): -// \z80_|execute_|setM1~27_combout = (\z80_|execute_|setM1~24_combout ) # ((\z80_|execute_|ctl_state_alu~4_combout & ((\z80_|execute_|setM1~25_combout ) # (\z80_|execute_|setM1~26_combout )))) - - .dataa(\z80_|execute_|setM1~25_combout ), - .datab(\z80_|execute_|setM1~26_combout ), - .datac(\z80_|execute_|setM1~24_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~27 .lut_mask = 16'hFEF0; -defparam \z80_|execute_|setM1~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N6 -cycloneive_lcell_comb \z80_|execute_|setM1~22 ( -// Equation(s): -// \z80_|execute_|setM1~22_combout = (!\z80_|execute_|ctl_mRead~10_combout & (\z80_|execute_|fMWrite~9_combout & (!\z80_|execute_|ctl_mRead~8_combout & \z80_|execute_|fMWrite~3_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|execute_|fMWrite~9_combout ), - .datac(\z80_|execute_|ctl_mRead~8_combout ), - .datad(\z80_|execute_|fMWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~22 .lut_mask = 16'h0400; -defparam \z80_|execute_|setM1~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N26 -cycloneive_lcell_comb \z80_|execute_|setM1~21 ( -// Equation(s): -// \z80_|execute_|setM1~21_combout = (\z80_|decode_state_|DFFE_instNonRep~q ) # ((!\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [4] & \z80_|execute_|ctl_mWrite~2_combout ))) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|decode_state_|DFFE_instNonRep~q ), - .datad(\z80_|execute_|ctl_mWrite~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~21 .lut_mask = 16'hF1F0; -defparam \z80_|execute_|setM1~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N2 -cycloneive_lcell_comb \z80_|execute_|setM1~53 ( -// Equation(s): -// \z80_|execute_|setM1~53_combout = (\z80_|sequencer_|DFFE_T5_ff~q & ((\z80_|sequencer_|DFFE_M4_ff~q ) # ((\z80_|execute_|setM1~21_combout & \z80_|sequencer_|DFFE_M3_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|sequencer_|DFFE_T5_ff~q ), - .datac(\z80_|execute_|setM1~21_combout ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~53_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~53 .lut_mask = 16'hC888; -defparam \z80_|execute_|setM1~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N4 -cycloneive_lcell_comb \z80_|execute_|setM1~23 ( -// Equation(s): -// \z80_|execute_|setM1~23_combout = (\z80_|execute_|setM1~22_combout & (((!\z80_|execute_|ctl_flags_bus~5_combout & \z80_|execute_|setM1~53_combout )))) # (!\z80_|execute_|setM1~22_combout & ((\z80_|execute_|ctl_reg_in_hi~2_combout ) # -// ((!\z80_|execute_|ctl_flags_bus~5_combout & \z80_|execute_|setM1~53_combout )))) - - .dataa(\z80_|execute_|setM1~22_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datac(\z80_|execute_|ctl_flags_bus~5_combout ), - .datad(\z80_|execute_|setM1~53_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~23 .lut_mask = 16'h4F44; -defparam \z80_|execute_|setM1~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N6 -cycloneive_lcell_comb \z80_|execute_|setM1~18 ( -// Equation(s): -// \z80_|execute_|setM1~18_combout = (\z80_|execute_|ctl_mRead~11_combout & (((\z80_|pla_decode_|Equal37~0_combout & !\z80_|alu_control_|flags_cond_true~q )) # (!\z80_|execute_|ctl_flags_bus~4_combout ))) - - .dataa(\z80_|pla_decode_|Equal37~0_combout ), - .datab(\z80_|execute_|ctl_mRead~11_combout ), - .datac(\z80_|alu_control_|flags_cond_true~q ), - .datad(\z80_|execute_|ctl_flags_bus~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~18 .lut_mask = 16'h08CC; -defparam \z80_|execute_|setM1~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|setM1~19 ( -// Equation(s): -// \z80_|execute_|setM1~19_combout = (\z80_|execute_|setM1~18_combout ) # ((\z80_|execute_|ixy_d~8_combout & (\z80_|pla_decode_|Equal10~0_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ))) - - .dataa(\z80_|execute_|setM1~18_combout ), - .datab(\z80_|execute_|ixy_d~8_combout ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~19 .lut_mask = 16'hEAAA; -defparam \z80_|execute_|setM1~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|setM1~20 ( -// Equation(s): -// \z80_|execute_|setM1~20_combout = ((\z80_|execute_|setM1~19_combout ) # ((\z80_|execute_|ctl_iorw~11_combout & \z80_|execute_|ctl_mWrite~3_combout ))) # (!\z80_|execute_|ctl_flags_sz_we~0_combout ) - - .dataa(\z80_|execute_|ctl_iorw~11_combout ), - .datab(\z80_|execute_|ctl_mWrite~3_combout ), - .datac(\z80_|execute_|ctl_flags_sz_we~0_combout ), - .datad(\z80_|execute_|setM1~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~20 .lut_mask = 16'hFF8F; -defparam \z80_|execute_|setM1~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N16 -cycloneive_lcell_comb \z80_|execute_|setM1~34 ( -// Equation(s): -// \z80_|execute_|setM1~34_combout = (\z80_|execute_|setM1~33_combout ) # ((\z80_|execute_|setM1~27_combout ) # ((\z80_|execute_|setM1~23_combout ) # (\z80_|execute_|setM1~20_combout ))) - - .dataa(\z80_|execute_|setM1~33_combout ), - .datab(\z80_|execute_|setM1~27_combout ), - .datac(\z80_|execute_|setM1~23_combout ), - .datad(\z80_|execute_|setM1~20_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~34 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|setM1~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|setM1~52 ( -// Equation(s): -// \z80_|execute_|setM1~52_combout = (!\z80_|execute_|setM1~17_combout & (!\z80_|execute_|setM1~34_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|execute_|setM1~51_combout )))) - - .dataa(\z80_|execute_|setM1~51_combout ), - .datab(\z80_|execute_|setM1~17_combout ), - .datac(\z80_|execute_|setM1~34_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~52_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~52 .lut_mask = 16'h0301; -defparam \z80_|execute_|setM1~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N24 -cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_14 ( -// Equation(s): -// \z80_|sequencer_|SYNTHESIZED_WIRE_14~combout = (\z80_|execute_|setM1~52_combout & (\z80_|sequencer_|DFFE_T2_ff~q & !\z80_|execute_|nextM~14_combout )) - - .dataa(\z80_|execute_|setM1~52_combout ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_14 .lut_mask = 16'h00A0; -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y17_N25 -dffeas \z80_|sequencer_|DFFE_T3_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|DFFE_T3_ff~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_T3_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_T3_ff .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout = (\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 .lut_mask = 16'h00F0; -defparam \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N24 -cycloneive_lcell_comb \z80_|decode_state_|in_halt~0 ( -// Equation(s): -// \z80_|decode_state_|in_halt~0_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|decode_state_|in_halt~q & !\z80_|interrupts_|DFFE_inst44~q )) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(gnd), - .datac(\z80_|decode_state_|in_halt~q ), - .datad(\z80_|interrupts_|DFFE_inst44~q ), - .cin(gnd), - .combout(\z80_|decode_state_|in_halt~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|in_halt~0 .lut_mask = 16'h0050; -defparam \z80_|decode_state_|in_halt~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N24 -cycloneive_lcell_comb \z80_|decode_state_|in_halt~1 ( -// Equation(s): -// \z80_|decode_state_|in_halt~1_combout = (\z80_|decode_state_|in_halt~0_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (!\z80_|decode_state_|in_halt~q & \z80_|pla_decode_|Equal77~1_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|decode_state_|in_halt~0_combout ), - .datac(\z80_|decode_state_|in_halt~q ), - .datad(\z80_|pla_decode_|Equal77~1_combout ), - .cin(gnd), - .combout(\z80_|decode_state_|in_halt~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|in_halt~1 .lut_mask = 16'hCECC; -defparam \z80_|decode_state_|in_halt~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y13_N25 -dffeas \z80_|decode_state_|in_halt ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|decode_state_|in_halt~1_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|decode_state_|in_halt~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|decode_state_|in_halt .is_wysiwyg = "true"; -defparam \z80_|decode_state_|in_halt .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~2 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~2_combout = (!\z80_|execute_|ctl_bus_zero_oe~0_combout & (!\z80_|execute_|ctl_bus_ff_oe~1_combout & ((\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) # (!\z80_|decode_state_|in_halt~q )))) - - .dataa(\z80_|decode_state_|in_halt~q ), - .datab(\z80_|execute_|ctl_bus_zero_oe~0_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|execute_|ctl_bus_ff_oe~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~2 .lut_mask = 16'h0031; -defparam \z80_|execute_|ctl_bus_db_oe~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~5 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~5_combout = (\z80_|execute_|ctl_ir_we~8_combout ) # ((\z80_|execute_|ctl_ir_we~14_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout ) # (\z80_|pla_decode_|Equal41~2_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(\z80_|execute_|ctl_ir_we~14_combout ), - .datac(\z80_|execute_|ctl_ir_we~11_combout ), - .datad(\z80_|pla_decode_|Equal41~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~5 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_bus_db_oe~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~6 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~6_combout = ((\z80_|execute_|ctl_66_oe~2_combout ) # ((\z80_|execute_|ctl_ir_we~4_combout & \z80_|execute_|ctl_bus_db_oe~5_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_66_oe~2_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~6 .lut_mask = 16'hFDF5; -defparam \z80_|execute_|ctl_bus_db_oe~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~4 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~4_combout = (!\z80_|execute_|ctl_bus_db_oe~3_combout ) # (!\z80_|execute_|ctl_bus_db_oe~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_bus_db_oe~0_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~4 .lut_mask = 16'h0FFF; -defparam \z80_|execute_|ctl_bus_db_oe~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~combout = (\z80_|execute_|ctl_bus_db_oe~2_combout & (((\z80_|execute_|ctl_bus_db_oe~6_combout ) # (\z80_|execute_|ctl_bus_db_oe~4_combout )) # (!\z80_|execute_|ctl_sw_1d~6_combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_oe~2_combout ), + .dataa(\z80_|execute_|ctl_66_oe~2_combout ), .datab(\z80_|execute_|ctl_sw_1d~6_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~6_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~4_combout ), + .datac(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datad(\z80_|bus_control_|db[3]~21_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~combout ), + .combout(\z80_|sw1_|db_down[3]~2_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe .lut_mask = 16'hAAA2; -defparam \z80_|execute_|ctl_bus_db_oe .sum_lutc_input = "datac"; +defparam \z80_|sw1_|db_down[3]~2 .lut_mask = 16'hFFC4; +defparam \z80_|sw1_|db_down[3]~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N28 -cycloneive_lcell_comb \z80_|bus_control_|db[0]~6 ( +// Location: LCCOMB_X31_Y14_N6 +cycloneive_lcell_comb \z80_|alu_control_|db[3]~34 ( // Equation(s): -// \z80_|bus_control_|db[0]~6_combout = (\z80_|execute_|ctl_bus_db_oe~combout ) # ((\z80_|execute_|ctl_bus_db_we~7_combout ) # (!\z80_|execute_|ctl_bus_db_oe~2_combout )) +// \z80_|alu_control_|db[3]~34_combout = (\z80_|alu_control_|db[3]~33_combout & (\z80_|sw1_|db_down[3]~2_combout & ((\z80_|reg_file_|gdfx_temp0[3]~52_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) - .dataa(\z80_|execute_|ctl_bus_db_oe~combout ), + .dataa(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .datac(\z80_|alu_control_|db[3]~33_combout ), + .datad(\z80_|sw1_|db_down[3]~2_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[3]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[3]~34 .lut_mask = 16'hB000; +defparam \z80_|alu_control_|db[3]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N0 +cycloneive_lcell_comb \z80_|alu_control_|db[3]~35 ( +// Equation(s): +// \z80_|alu_control_|db[3]~35_combout = ((\z80_|alu_control_|db[3]~34_combout & ((\z80_|alu_|db[3]~20_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) + + .dataa(\z80_|alu_control_|db[3]~34_combout ), + .datab(\z80_|execute_|ctl_sw_2u~7_combout ), + .datac(\z80_|alu_|db[3]~20_combout ), + .datad(\z80_|alu_control_|db[6]~11_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[3]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[3]~35 .lut_mask = 16'hA2FF; +defparam \z80_|alu_control_|db[3]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][0]~75 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][0]~75_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [1])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), .datab(gnd), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~2_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[0]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[0]~6 .lut_mask = 16'hFAFF; -defparam \z80_|bus_control_|db[0]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][3]~93 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][3]~93_combout = (\ula_|zx_keyboard_|keys[7][4]~19_combout & (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[6][4]~47_combout ))) - - .dataa(\ula_|zx_keyboard_|keys[7][4]~19_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|keys[6][4]~47_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][3]~93_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][3]~93 .lut_mask = 16'h0800; -defparam \ula_|zx_keyboard_|keys[1][3]~93 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][3]~94 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][3]~94_combout = (\ula_|zx_keyboard_|keys[1][3]~93_combout & ((\ula_|ps2_keyboard_|shiftreg [3] & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[1][3]~q )))) # -// (!\ula_|zx_keyboard_|keys[1][3]~93_combout & (((\ula_|zx_keyboard_|keys[1][3]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[1][3]~93_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|zx_keyboard_|keys[1][3]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][3]~94_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][3]~94 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[1][3]~94 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y19_N31 -dffeas \ula_|zx_keyboard_|keys[1][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[1][3]~94_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[1][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[1][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][3]~96 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][3]~96_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [1]))) # (!\ula_|ps2_keyboard_|shiftreg [3] & -// (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), .datad(\ula_|ps2_keyboard_|shiftreg [1]), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][3]~96_combout ), + .combout(\ula_|zx_keyboard_|keys[3][0]~75_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][3]~96 .lut_mask = 16'h0810; -defparam \ula_|zx_keyboard_|keys[0][3]~96 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[3][0]~75 .lut_mask = 16'h0500; +defparam \ula_|zx_keyboard_|keys[3][0]~75 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y18_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][3]~98 ( +// Location: LCCOMB_X27_Y8_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|Selector5~0 ( // Equation(s): -// \ula_|zx_keyboard_|keys[0][3]~98_combout = (\ula_|zx_keyboard_|keys[0][3]~96_combout & ((\ula_|zx_keyboard_|keys[0][4]~97_combout & ((!\ula_|zx_keyboard_|keys[2][4]~95_combout ))) # (!\ula_|zx_keyboard_|keys[0][4]~97_combout & -// (\ula_|zx_keyboard_|keys[0][3]~q )))) # (!\ula_|zx_keyboard_|keys[0][3]~96_combout & (((\ula_|zx_keyboard_|keys[0][3]~q )))) +// \ula_|zx_keyboard_|Selector5~0_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|keys[3][0]~75_combout & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [6]))) - .dataa(\ula_|zx_keyboard_|keys[0][3]~96_combout ), - .datab(\ula_|zx_keyboard_|keys[0][4]~97_combout ), - .datac(\ula_|zx_keyboard_|keys[0][3]~q ), - .datad(\ula_|zx_keyboard_|keys[2][4]~95_combout ), + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|zx_keyboard_|keys[3][0]~75_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][3]~98_combout ), + .combout(\ula_|zx_keyboard_|Selector5~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][3]~98 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[0][3]~98 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|Selector5~0 .lut_mask = 16'h0400; +defparam \ula_|zx_keyboard_|Selector5~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X29_Y18_N1 -dffeas \ula_|zx_keyboard_|keys[0][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[0][3]~98_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[0][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[0][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N4 -cycloneive_lcell_comb \D[3]~65 ( +// Location: LCCOMB_X26_Y10_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|Selector5~1 ( // Equation(s): -// \D[3]~65_combout = (\z80_|address_pins_|abus[9]~17_combout & ((\z80_|address_pins_|abus[8]~18_combout ) # ((!\ula_|zx_keyboard_|keys[0][3]~q )))) # (!\z80_|address_pins_|abus[9]~17_combout & (!\ula_|zx_keyboard_|keys[1][3]~q & -// ((\z80_|address_pins_|abus[8]~18_combout ) # (!\ula_|zx_keyboard_|keys[0][3]~q )))) - - .dataa(\z80_|address_pins_|abus[9]~17_combout ), - .datab(\z80_|address_pins_|abus[8]~18_combout ), - .datac(\ula_|zx_keyboard_|keys[1][3]~q ), - .datad(\ula_|zx_keyboard_|keys[0][3]~q ), - .cin(gnd), - .combout(\D[3]~65_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~65 .lut_mask = 16'h8CAF; -defparam \D[3]~65 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][3]~99 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][3]~99_combout = (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [2])) +// \ula_|zx_keyboard_|Selector5~1_combout = (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [2]))) .dataa(\ula_|ps2_keyboard_|shiftreg [1]), .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][3]~99_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][3]~99 .lut_mask = 16'h4040; -defparam \ula_|zx_keyboard_|keys[3][3]~99 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][3]~100 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][3]~100_combout = (\ula_|zx_keyboard_|keys[3][3]~48_combout & ((\ula_|zx_keyboard_|keys[3][3]~99_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[3][3]~99_combout & (\ula_|zx_keyboard_|keys[3][3]~q -// )))) # (!\ula_|zx_keyboard_|keys[3][3]~48_combout & (((\ula_|zx_keyboard_|keys[3][3]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[3][3]~48_combout ), - .datab(\ula_|zx_keyboard_|keys[3][3]~99_combout ), - .datac(\ula_|zx_keyboard_|keys[3][3]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][3]~100_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][3]~100 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[3][3]~100 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y20_N9 -dffeas \ula_|zx_keyboard_|keys[3][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[3][3]~100_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[3][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[3][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~101 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][3]~101_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & !\ula_|ps2_keyboard_|shiftreg [2])) - - .dataa(\ula_|zx_keyboard_|shifted~q ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), .datad(\ula_|ps2_keyboard_|shiftreg [2]), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][3]~101_combout ), + .combout(\ula_|zx_keyboard_|Selector5~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][3]~101 .lut_mask = 16'hCCDD; -defparam \ula_|zx_keyboard_|keys[2][3]~101 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|Selector5~1 .lut_mask = 16'h4000; +defparam \ula_|zx_keyboard_|Selector5~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y18_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~102 ( +// Location: LCCOMB_X27_Y8_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~132 ( // Equation(s): -// \ula_|zx_keyboard_|keys[2][3]~102_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [2]))) # (!\ula_|ps2_keyboard_|shiftreg [3] & -// (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [2]))) +// \ula_|zx_keyboard_|keys[4][3]~132_combout = (\ula_|zx_keyboard_|Selector5~0_combout ) # ((\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|zx_keyboard_|Selector5~1_combout ))) - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .dataa(\ula_|zx_keyboard_|Selector5~0_combout ), .datab(\ula_|ps2_keyboard_|shiftreg [5]), .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|zx_keyboard_|Selector5~1_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][3]~102_combout ), + .combout(\ula_|zx_keyboard_|keys[4][3]~132_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][3]~102 .lut_mask = 16'h0810; -defparam \ula_|zx_keyboard_|keys[2][3]~102 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[4][3]~132 .lut_mask = 16'hAEAA; +defparam \ula_|zx_keyboard_|keys[4][3]~132 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y18_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~133 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][3]~133_combout = (\ula_|zx_keyboard_|keys[5][1]~36_combout & (\ula_|zx_keyboard_|keys[2][3]~102_combout & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1]))) - - .dataa(\ula_|zx_keyboard_|keys[5][1]~36_combout ), - .datab(\ula_|zx_keyboard_|keys[2][3]~102_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][3]~133_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][3]~133 .lut_mask = 16'h0080; -defparam \ula_|zx_keyboard_|keys[2][3]~133 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~103 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][3]~103_combout = (\ula_|zx_keyboard_|keys[2][3]~133_combout & (!\ula_|zx_keyboard_|keys[2][3]~101_combout )) # (!\ula_|zx_keyboard_|keys[2][3]~133_combout & ((\ula_|zx_keyboard_|keys[2][3]~q ))) - - .dataa(\ula_|zx_keyboard_|keys[2][3]~101_combout ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[2][3]~q ), - .datad(\ula_|zx_keyboard_|keys[2][3]~133_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][3]~103_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][3]~103 .lut_mask = 16'h55F0; -defparam \ula_|zx_keyboard_|keys[2][3]~103 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y18_N3 -dffeas \ula_|zx_keyboard_|keys[2][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[2][3]~103_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[2][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[2][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N28 -cycloneive_lcell_comb \D[3]~66 ( -// Equation(s): -// \D[3]~66_combout = (\z80_|address_pins_|abus[11]~19_combout & (((\z80_|address_pins_|abus[10]~24_combout ) # (!\ula_|zx_keyboard_|keys[2][3]~q )))) # (!\z80_|address_pins_|abus[11]~19_combout & (!\ula_|zx_keyboard_|keys[3][3]~q & -// ((\z80_|address_pins_|abus[10]~24_combout ) # (!\ula_|zx_keyboard_|keys[2][3]~q )))) - - .dataa(\z80_|address_pins_|abus[11]~19_combout ), - .datab(\ula_|zx_keyboard_|keys[3][3]~q ), - .datac(\z80_|address_pins_|abus[10]~24_combout ), - .datad(\ula_|zx_keyboard_|keys[2][3]~q ), - .cin(gnd), - .combout(\D[3]~66_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~66 .lut_mask = 16'hB0BB; -defparam \D[3]~66 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][3]~104 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][3]~104_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [0])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [5]), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][3]~104_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][3]~104 .lut_mask = 16'h0808; -defparam \ula_|zx_keyboard_|keys[5][3]~104 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][3]~105 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][3]~105_combout = (\ula_|zx_keyboard_|keys[5][3]~104_combout & ((\ula_|zx_keyboard_|keys[1][4]~25_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[1][4]~25_combout & (\ula_|zx_keyboard_|keys[5][3]~q -// )))) # (!\ula_|zx_keyboard_|keys[5][3]~104_combout & (((\ula_|zx_keyboard_|keys[5][3]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[5][3]~104_combout ), - .datab(\ula_|zx_keyboard_|keys[1][4]~25_combout ), - .datac(\ula_|zx_keyboard_|keys[5][3]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][3]~105_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][3]~105 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[5][3]~105 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y19_N23 -dffeas \ula_|zx_keyboard_|keys[5][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[5][3]~105_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[5][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[5][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N16 +// Location: LCCOMB_X27_Y8_N10 cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~106 ( // Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~106_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[5][4]~24_combout & (\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|WideOr16~2_combout ))) +// \ula_|zx_keyboard_|keys[4][3]~106_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|WideOr16~2_combout & (\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[5][4]~22_combout ))) .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|zx_keyboard_|keys[5][4]~24_combout ), + .datab(\ula_|zx_keyboard_|WideOr16~2_combout ), .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|zx_keyboard_|WideOr16~2_combout ), + .datad(\ula_|zx_keyboard_|keys[5][4]~22_combout ), .cin(gnd), .combout(\ula_|zx_keyboard_|keys[4][3]~106_combout ), .cout()); @@ -52111,110 +41584,59 @@ defparam \ula_|zx_keyboard_|keys[4][3]~106 .lut_mask = 16'h8000; defparam \ula_|zx_keyboard_|keys[4][3]~106 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X27_Y21_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|Selector5~1 ( -// Equation(s): -// \ula_|zx_keyboard_|Selector5~1_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|Selector5~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|Selector5~1 .lut_mask = 16'h0800; -defparam \ula_|zx_keyboard_|Selector5~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|Selector5~0 ( -// Equation(s): -// \ula_|zx_keyboard_|Selector5~0_combout = (\ula_|zx_keyboard_|keys[3][0]~78_combout & (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [5]))) - - .dataa(\ula_|zx_keyboard_|keys[3][0]~78_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|Selector5~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|Selector5~0 .lut_mask = 16'h0020; -defparam \ula_|zx_keyboard_|Selector5~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y21_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~134 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~134_combout = (\ula_|zx_keyboard_|Selector5~0_combout ) # ((\ula_|zx_keyboard_|Selector5~1_combout & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [5]))) - - .dataa(\ula_|zx_keyboard_|Selector5~1_combout ), - .datab(\ula_|zx_keyboard_|Selector5~0_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][3]~134_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~134 .lut_mask = 16'hCECC; -defparam \ula_|zx_keyboard_|keys[4][3]~134 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y21_N6 +// Location: LCCOMB_X27_Y8_N26 cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~107 ( // Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~107_combout = (\ula_|zx_keyboard_|extended~q & (\ula_|zx_keyboard_|keys[4][3]~106_combout )) # (!\ula_|zx_keyboard_|extended~q & (((\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[4][3]~134_combout )))) +// \ula_|zx_keyboard_|keys[4][3]~107_combout = (\ula_|zx_keyboard_|extended~q & (((\ula_|zx_keyboard_|keys[4][3]~106_combout )))) # (!\ula_|zx_keyboard_|extended~q & (\ula_|zx_keyboard_|keys[4][3]~132_combout & (\ula_|ps2_keyboard_|shiftreg [4]))) .dataa(\ula_|zx_keyboard_|extended~q ), - .datab(\ula_|zx_keyboard_|keys[4][3]~106_combout ), + .datab(\ula_|zx_keyboard_|keys[4][3]~132_combout ), .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|keys[4][3]~134_combout ), + .datad(\ula_|zx_keyboard_|keys[4][3]~106_combout ), .cin(gnd), .combout(\ula_|zx_keyboard_|keys[4][3]~107_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~107 .lut_mask = 16'hD888; +defparam \ula_|zx_keyboard_|keys[4][3]~107 .lut_mask = 16'hEA40; defparam \ula_|zx_keyboard_|keys[4][3]~107 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y21_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~135 ( +// Location: LCCOMB_X27_Y8_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~133 ( // Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~135_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|shifted~q ))) +// \ula_|zx_keyboard_|keys[4][3]~133_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|shifted~q ))) .dataa(\ula_|zx_keyboard_|extended~q ), .datab(\ula_|zx_keyboard_|released~q ), .datac(\ula_|ps2_keyboard_|shiftreg [5]), .datad(\ula_|zx_keyboard_|shifted~q ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][3]~135_combout ), + .combout(\ula_|zx_keyboard_|keys[4][3]~133_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~135 .lut_mask = 16'hCDCC; -defparam \ula_|zx_keyboard_|keys[4][3]~135 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[4][3]~133 .lut_mask = 16'hCDCC; +defparam \ula_|zx_keyboard_|keys[4][3]~133 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y21_N22 +// Location: LCCOMB_X27_Y8_N6 cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~108 ( // Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~108_combout = (\ula_|zx_keyboard_|keys[4][3]~107_combout & ((\ula_|zx_keyboard_|keys[0][0]~15_combout & ((!\ula_|zx_keyboard_|keys[4][3]~135_combout ))) # (!\ula_|zx_keyboard_|keys[0][0]~15_combout & -// (\ula_|zx_keyboard_|keys[4][3]~q )))) # (!\ula_|zx_keyboard_|keys[4][3]~107_combout & (((\ula_|zx_keyboard_|keys[4][3]~q )))) +// \ula_|zx_keyboard_|keys[4][3]~108_combout = (\ula_|zx_keyboard_|keys[4][3]~107_combout & ((\ula_|zx_keyboard_|keys[0][0]~13_combout & (!\ula_|zx_keyboard_|keys[4][3]~133_combout )) # (!\ula_|zx_keyboard_|keys[0][0]~13_combout & +// ((\ula_|zx_keyboard_|keys[4][3]~q ))))) # (!\ula_|zx_keyboard_|keys[4][3]~107_combout & (((\ula_|zx_keyboard_|keys[4][3]~q )))) .dataa(\ula_|zx_keyboard_|keys[4][3]~107_combout ), - .datab(\ula_|zx_keyboard_|keys[0][0]~15_combout ), + .datab(\ula_|zx_keyboard_|keys[4][3]~133_combout ), .datac(\ula_|zx_keyboard_|keys[4][3]~q ), - .datad(\ula_|zx_keyboard_|keys[4][3]~135_combout ), + .datad(\ula_|zx_keyboard_|keys[0][0]~13_combout ), .cin(gnd), .combout(\ula_|zx_keyboard_|keys[4][3]~108_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~108 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[4][3]~108 .lut_mask = 16'h72F0; defparam \ula_|zx_keyboard_|keys[4][3]~108 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y21_N23 +// Location: FF_X27_Y8_N7 dffeas \ula_|zx_keyboard_|keys[4][3] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\ula_|zx_keyboard_|keys[4][3]~108_combout ), @@ -52233,79 +41655,555 @@ defparam \ula_|zx_keyboard_|keys[4][3] .is_wysiwyg = "true"; defparam \ula_|zx_keyboard_|keys[4][3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y19_N20 -cycloneive_lcell_comb \D[3]~67 ( +// Location: LCCOMB_X28_Y7_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][3]~104 ( // Equation(s): -// \D[3]~67_combout = (\ula_|zx_keyboard_|keys[5][3]~q & (\z80_|address_pins_|abus[13]~20_combout & ((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][3]~q )))) # (!\ula_|zx_keyboard_|keys[5][3]~q & -// (((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][3]~q )))) +// \ula_|zx_keyboard_|keys[5][3]~104_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [5])) - .dataa(\ula_|zx_keyboard_|keys[5][3]~q ), - .datab(\z80_|address_pins_|abus[13]~20_combout ), - .datac(\ula_|zx_keyboard_|keys[4][3]~q ), - .datad(\z80_|address_pins_|abus[12]~21_combout ), + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), .cin(gnd), - .combout(\D[3]~67_combout ), + .combout(\ula_|zx_keyboard_|keys[5][3]~104_combout ), .cout()); // synopsys translate_off -defparam \D[3]~67 .lut_mask = 16'hDD0D; -defparam \D[3]~67 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[5][3]~104 .lut_mask = 16'h0A00; +defparam \ula_|zx_keyboard_|keys[5][3]~104 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X27_Y21_N4 +// Location: LCCOMB_X28_Y7_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][3]~105 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][3]~105_combout = (\ula_|zx_keyboard_|keys[1][4]~23_combout & ((\ula_|zx_keyboard_|keys[5][3]~104_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[5][3]~104_combout & ((\ula_|zx_keyboard_|keys[5][3]~q +// ))))) # (!\ula_|zx_keyboard_|keys[1][4]~23_combout & (((\ula_|zx_keyboard_|keys[5][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[1][4]~23_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[5][3]~q ), + .datad(\ula_|zx_keyboard_|keys[5][3]~104_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][3]~105_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][3]~105 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[5][3]~105 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y7_N23 +dffeas \ula_|zx_keyboard_|keys[5][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[5][3]~105_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[5][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[5][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N12 +cycloneive_lcell_comb \D[3]~55 ( +// Equation(s): +// \D[3]~55_combout = (\z80_|address_pins_|abus[12]~21_combout & (((\z80_|address_pins_|abus[13]~20_combout ) # (!\ula_|zx_keyboard_|keys[5][3]~q )))) # (!\z80_|address_pins_|abus[12]~21_combout & (!\ula_|zx_keyboard_|keys[4][3]~q & +// ((\z80_|address_pins_|abus[13]~20_combout ) # (!\ula_|zx_keyboard_|keys[5][3]~q )))) + + .dataa(\z80_|address_pins_|abus[12]~21_combout ), + .datab(\ula_|zx_keyboard_|keys[4][3]~q ), + .datac(\ula_|zx_keyboard_|keys[5][3]~q ), + .datad(\z80_|address_pins_|abus[13]~20_combout ), + .cin(gnd), + .combout(\D[3]~55_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~55 .lut_mask = 16'hBB0B; +defparam \D[3]~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~46 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][4]~46_combout = (\ula_|zx_keyboard_|keys[7][1]~21_combout & (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|zx_keyboard_|keys[7][1]~21_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][4]~46_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][4]~46 .lut_mask = 16'h0200; +defparam \ula_|zx_keyboard_|keys[6][4]~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~62 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][4]~62_combout = (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][4]~62_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][4]~62 .lut_mask = 16'h00F0; +defparam \ula_|zx_keyboard_|keys[5][4]~62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][3]~102 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][3]~102_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|zx_keyboard_|keys[6][4]~46_combout & (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|zx_keyboard_|keys[5][4]~62_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|zx_keyboard_|keys[6][4]~46_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|zx_keyboard_|keys[5][4]~62_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][3]~102_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][3]~102 .lut_mask = 16'h4000; +defparam \ula_|zx_keyboard_|keys[3][3]~102 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][3]~103 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][3]~103_combout = (\ula_|zx_keyboard_|keys[3][3]~102_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][3]~102_combout & ((\ula_|zx_keyboard_|keys[3][3]~q ))) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[3][3]~q ), + .datad(\ula_|zx_keyboard_|keys[3][3]~102_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][3]~103_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][3]~103 .lut_mask = 16'h33F0; +defparam \ula_|zx_keyboard_|keys[3][3]~103 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y7_N11 +dffeas \ula_|zx_keyboard_|keys[3][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[3][3]~103_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[3][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[3][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~96 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][4]~96_combout = (\ula_|zx_keyboard_|keys[5][1]~34_combout & (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [5] $ (\ula_|ps2_keyboard_|shiftreg [6])))) + + .dataa(\ula_|zx_keyboard_|keys[5][1]~34_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][4]~96_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][4]~96 .lut_mask = 16'h0208; +defparam \ula_|zx_keyboard_|keys[0][4]~96 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~94 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][4]~94_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [6])) + + .dataa(\ula_|zx_keyboard_|shifted~q ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][4]~94_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][4]~94 .lut_mask = 16'hDDCC; +defparam \ula_|zx_keyboard_|keys[2][4]~94 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][3]~95 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][3]~95_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [6]))) # (!\ula_|ps2_keyboard_|shiftreg [1] & +// (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [6]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][3]~95_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][3]~95 .lut_mask = 16'h0810; +defparam \ula_|zx_keyboard_|keys[0][3]~95 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][3]~97 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][3]~97_combout = (\ula_|zx_keyboard_|keys[0][4]~96_combout & ((\ula_|zx_keyboard_|keys[0][3]~95_combout & (!\ula_|zx_keyboard_|keys[2][4]~94_combout )) # (!\ula_|zx_keyboard_|keys[0][3]~95_combout & +// ((\ula_|zx_keyboard_|keys[0][3]~q ))))) # (!\ula_|zx_keyboard_|keys[0][4]~96_combout & (((\ula_|zx_keyboard_|keys[0][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[0][4]~96_combout ), + .datab(\ula_|zx_keyboard_|keys[2][4]~94_combout ), + .datac(\ula_|zx_keyboard_|keys[0][3]~q ), + .datad(\ula_|zx_keyboard_|keys[0][3]~95_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][3]~97_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][3]~97 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[0][3]~97 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y9_N19 +dffeas \ula_|zx_keyboard_|keys[0][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[0][3]~97_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[0][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[0][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~45 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][4]~45_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [1])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][4]~45_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][4]~45 .lut_mask = 16'h5000; +defparam \ula_|zx_keyboard_|keys[6][4]~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][3]~92 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][3]~92_combout = (\ula_|zx_keyboard_|keys[6][4]~45_combout & (\ula_|zx_keyboard_|keys[7][4]~17_combout & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|zx_keyboard_|keys[6][4]~45_combout ), + .datab(\ula_|zx_keyboard_|keys[7][4]~17_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][3]~92_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][3]~92 .lut_mask = 16'h0800; +defparam \ula_|zx_keyboard_|keys[1][3]~92 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][3]~93 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][3]~93_combout = (\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[1][3]~92_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[1][3]~92_combout & ((\ula_|zx_keyboard_|keys[1][3]~q ))))) # +// (!\ula_|ps2_keyboard_|shiftreg [3] & (((\ula_|zx_keyboard_|keys[1][3]~q )))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[1][3]~q ), + .datad(\ula_|zx_keyboard_|keys[1][3]~92_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][3]~93_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][3]~93 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[1][3]~93 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y7_N15 +dffeas \ula_|zx_keyboard_|keys[1][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[1][3]~93_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[1][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[1][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N0 +cycloneive_lcell_comb \D[3]~53 ( +// Equation(s): +// \D[3]~53_combout = (\ula_|zx_keyboard_|keys[0][3]~q & (\z80_|address_pins_|abus[8]~18_combout & ((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][3]~q )))) # (!\ula_|zx_keyboard_|keys[0][3]~q & +// (((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[0][3]~q ), + .datab(\z80_|address_pins_|abus[8]~18_combout ), + .datac(\ula_|zx_keyboard_|keys[1][3]~q ), + .datad(\z80_|address_pins_|abus[9]~17_combout ), + .cin(gnd), + .combout(\D[3]~53_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~53 .lut_mask = 16'hDD0D; +defparam \D[3]~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~99 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][3]~99_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [6])) # (!\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [2] & +// \ula_|ps2_keyboard_|shiftreg [6])) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][3]~99_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][3]~99 .lut_mask = 16'h03C0; +defparam \ula_|zx_keyboard_|keys[2][3]~99 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~100 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][3]~100_combout = (\ula_|zx_keyboard_|keys[2][3]~99_combout & (\ula_|zx_keyboard_|keys[5][4]~62_combout & (\ula_|ps2_keyboard_|shiftreg [2] $ (!\ula_|ps2_keyboard_|shiftreg [3])))) + + .dataa(\ula_|zx_keyboard_|keys[2][3]~99_combout ), + .datab(\ula_|zx_keyboard_|keys[5][4]~62_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][3]~100_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][3]~100 .lut_mask = 16'h8008; +defparam \ula_|zx_keyboard_|keys[2][3]~100 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~98 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][3]~98_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & !\ula_|ps2_keyboard_|shiftreg [2])) + + .dataa(\ula_|zx_keyboard_|shifted~q ), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][3]~98_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][3]~98 .lut_mask = 16'hFF05; +defparam \ula_|zx_keyboard_|keys[2][3]~98 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~101 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][3]~101_combout = (\ula_|zx_keyboard_|keys[5][1]~34_combout & ((\ula_|zx_keyboard_|keys[2][3]~100_combout & ((!\ula_|zx_keyboard_|keys[2][3]~98_combout ))) # (!\ula_|zx_keyboard_|keys[2][3]~100_combout & +// (\ula_|zx_keyboard_|keys[2][3]~q )))) # (!\ula_|zx_keyboard_|keys[5][1]~34_combout & (((\ula_|zx_keyboard_|keys[2][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][1]~34_combout ), + .datab(\ula_|zx_keyboard_|keys[2][3]~100_combout ), + .datac(\ula_|zx_keyboard_|keys[2][3]~q ), + .datad(\ula_|zx_keyboard_|keys[2][3]~98_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][3]~101_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][3]~101 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[2][3]~101 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y9_N9 +dffeas \ula_|zx_keyboard_|keys[2][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[2][3]~101_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[2][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[2][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~3 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row~3_combout = ((\z80_|address_pins_|DFFE_apin_latch [10]) # (!\ula_|zx_keyboard_|keys[2][3]~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|address_pins_|DFFE_apin_latch [10]), + .datac(gnd), + .datad(\ula_|zx_keyboard_|keys[2][3]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row~3 .lut_mask = 16'hDDFF; +defparam \ula_|zx_keyboard_|key_row~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N20 +cycloneive_lcell_comb \D[3]~54 ( +// Equation(s): +// \D[3]~54_combout = (\D[3]~53_combout & (\ula_|zx_keyboard_|key_row~3_combout & ((\z80_|address_pins_|abus[11]~19_combout ) # (!\ula_|zx_keyboard_|keys[3][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[3][3]~q ), + .datab(\D[3]~53_combout ), + .datac(\z80_|address_pins_|abus[11]~19_combout ), + .datad(\ula_|zx_keyboard_|key_row~3_combout ), + .cin(gnd), + .combout(\D[3]~54_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~54 .lut_mask = 16'hC400; +defparam \D[3]~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~109 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][4]~109_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [6])) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|shifted~q ), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][4]~109_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][4]~109 .lut_mask = 16'hFFC0; +defparam \ula_|zx_keyboard_|keys[0][4]~109 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~60 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][2]~60_combout = (\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [6]) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][2]~60_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2]~60 .lut_mask = 16'h0C0C; +defparam \ula_|zx_keyboard_|keys[7][2]~60 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][3]~110 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][3]~110_combout = (\ula_|zx_keyboard_|WideOr16~2_combout & ((\ula_|zx_keyboard_|keys[7][2]~30_combout ) # ((\ula_|zx_keyboard_|keys[7][2]~60_combout & \ula_|ps2_keyboard_|shiftreg [4])))) + + .dataa(\ula_|zx_keyboard_|keys[7][2]~60_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|zx_keyboard_|WideOr16~2_combout ), + .datad(\ula_|zx_keyboard_|keys[7][2]~30_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][3]~110_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][3]~110 .lut_mask = 16'hF080; +defparam \ula_|zx_keyboard_|keys[7][3]~110 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][3]~111 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][3]~111_combout = (\ula_|zx_keyboard_|keys[0][0]~13_combout & (!\ula_|zx_keyboard_|extended~q & (\ula_|zx_keyboard_|keys[7][3]~110_combout & !\ula_|ps2_keyboard_|shiftreg [2]))) + + .dataa(\ula_|zx_keyboard_|keys[0][0]~13_combout ), + .datab(\ula_|zx_keyboard_|extended~q ), + .datac(\ula_|zx_keyboard_|keys[7][3]~110_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][3]~111_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][3]~111 .lut_mask = 16'h0020; +defparam \ula_|zx_keyboard_|keys[7][3]~111 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N14 cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][3]~112 ( // Equation(s): -// \ula_|zx_keyboard_|keys[7][3]~112_combout = (\ula_|zx_keyboard_|WideOr16~2_combout & ((\ula_|zx_keyboard_|keys[7][2]~32_combout ) # ((\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[7][2]~61_combout )))) +// \ula_|zx_keyboard_|keys[7][3]~112_combout = (\ula_|zx_keyboard_|keys[7][3]~111_combout & (!\ula_|zx_keyboard_|keys[0][4]~109_combout )) # (!\ula_|zx_keyboard_|keys[7][3]~111_combout & ((\ula_|zx_keyboard_|keys[7][3]~q ))) - .dataa(\ula_|zx_keyboard_|WideOr16~2_combout ), - .datab(\ula_|zx_keyboard_|keys[7][2]~32_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|keys[7][2]~61_combout ), + .dataa(\ula_|zx_keyboard_|keys[0][4]~109_combout ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[7][3]~q ), + .datad(\ula_|zx_keyboard_|keys[7][3]~111_combout ), .cin(gnd), .combout(\ula_|zx_keyboard_|keys[7][3]~112_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][3]~112 .lut_mask = 16'hA888; +defparam \ula_|zx_keyboard_|keys[7][3]~112 .lut_mask = 16'h55F0; defparam \ula_|zx_keyboard_|keys[7][3]~112 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X27_Y21_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][3]~113 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][3]~113_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|keys[7][3]~112_combout & (\ula_|zx_keyboard_|keys[0][0]~15_combout & !\ula_|zx_keyboard_|extended~q ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|zx_keyboard_|keys[7][3]~112_combout ), - .datac(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .datad(\ula_|zx_keyboard_|extended~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][3]~113_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][3]~113 .lut_mask = 16'h0040; -defparam \ula_|zx_keyboard_|keys[7][3]~113 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y20_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][3]~114 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][3]~114_combout = (\ula_|zx_keyboard_|keys[7][3]~113_combout & ((!\ula_|zx_keyboard_|keys[0][4]~111_combout ))) # (!\ula_|zx_keyboard_|keys[7][3]~113_combout & (\ula_|zx_keyboard_|keys[7][3]~q )) - - .dataa(gnd), - .datab(\ula_|zx_keyboard_|keys[7][3]~113_combout ), - .datac(\ula_|zx_keyboard_|keys[7][3]~q ), - .datad(\ula_|zx_keyboard_|keys[0][4]~111_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][3]~114_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][3]~114 .lut_mask = 16'h30FC; -defparam \ula_|zx_keyboard_|keys[7][3]~114 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y20_N9 +// Location: FF_X29_Y9_N15 dffeas \ula_|zx_keyboard_|keys[7][3] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[7][3]~114_combout ), + .d(\ula_|zx_keyboard_|keys[7][3]~112_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -52321,79 +42219,96 @@ defparam \ula_|zx_keyboard_|keys[7][3] .is_wysiwyg = "true"; defparam \ula_|zx_keyboard_|keys[7][3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X27_Y21_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~109 ( +// Location: LCCOMB_X28_Y9_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|Selector13~0 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][3]~109_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [5]))) +// \ula_|zx_keyboard_|Selector13~0_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|shifted~q )) - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), + .datab(\ula_|zx_keyboard_|shifted~q ), + .datac(gnd), + .datad(\ula_|zx_keyboard_|released~q ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][3]~109_combout ), + .combout(\ula_|zx_keyboard_|Selector13~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][3]~109 .lut_mask = 16'h1000; -defparam \ula_|zx_keyboard_|keys[6][3]~109 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|Selector13~0 .lut_mask = 16'hFF44; +defparam \ula_|zx_keyboard_|Selector13~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X27_Y21_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~110 ( +// Location: LCCOMB_X29_Y9_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~113 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][3]~110_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (((\ula_|zx_keyboard_|keys[6][3]~109_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|keys[7][2]~32_combout ))) +// \ula_|zx_keyboard_|keys[6][3]~113_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [2]))) - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|zx_keyboard_|keys[7][2]~32_combout ), - .datac(\ula_|zx_keyboard_|keys[6][3]~109_combout ), + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][3]~113_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][3]~113 .lut_mask = 16'h0040; +defparam \ula_|zx_keyboard_|keys[6][3]~113 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~114 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][3]~114_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|zx_keyboard_|keys[6][3]~113_combout )) # (!\ula_|ps2_keyboard_|shiftreg [0] & (((\ula_|ps2_keyboard_|shiftreg [2] & \ula_|zx_keyboard_|keys[7][2]~30_combout )))) + + .dataa(\ula_|zx_keyboard_|keys[6][3]~113_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|zx_keyboard_|keys[7][2]~30_combout ), .datad(\ula_|ps2_keyboard_|shiftreg [0]), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][3]~110_combout ), + .combout(\ula_|zx_keyboard_|keys[6][3]~114_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][3]~110 .lut_mask = 16'hF088; -defparam \ula_|zx_keyboard_|keys[6][3]~110 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[6][3]~114 .lut_mask = 16'hAAC0; +defparam \ula_|zx_keyboard_|keys[6][3]~114 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y21_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~137 ( +// Location: LCCOMB_X29_Y9_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~135 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][3]~137_combout = (\ula_|zx_keyboard_|extended~q ) # (((!\ula_|zx_keyboard_|keys[0][0]~15_combout ) # (!\ula_|ps2_keyboard_|shiftreg [3])) # (!\ula_|zx_keyboard_|keys[6][3]~110_combout )) +// \ula_|zx_keyboard_|keys[6][3]~135_combout = ((\ula_|zx_keyboard_|extended~q ) # ((!\ula_|zx_keyboard_|keys[6][3]~114_combout ) # (!\ula_|ps2_keyboard_|shiftreg [3]))) # (!\ula_|zx_keyboard_|keys[0][0]~13_combout ) - .dataa(\ula_|zx_keyboard_|extended~q ), - .datab(\ula_|zx_keyboard_|keys[6][3]~110_combout ), + .dataa(\ula_|zx_keyboard_|keys[0][0]~13_combout ), + .datab(\ula_|zx_keyboard_|extended~q ), .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|zx_keyboard_|keys[0][0]~15_combout ), + .datad(\ula_|zx_keyboard_|keys[6][3]~114_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][3]~137_combout ), + .combout(\ula_|zx_keyboard_|keys[6][3]~135_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][3]~137 .lut_mask = 16'hBFFF; -defparam \ula_|zx_keyboard_|keys[6][3]~137 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[6][3]~135 .lut_mask = 16'hDFFF; +defparam \ula_|zx_keyboard_|keys[6][3]~135 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y21_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~138 ( +// Location: LCCOMB_X29_Y9_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~136 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][3]~138_combout = (\ula_|ps2_keyboard_|shiftreg [1] & ((\ula_|zx_keyboard_|keys[6][3]~137_combout & ((\ula_|zx_keyboard_|keys[6][3]~q ))) # (!\ula_|zx_keyboard_|keys[6][3]~137_combout & -// (!\ula_|zx_keyboard_|Selector13~0_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [1] & (((\ula_|zx_keyboard_|keys[6][3]~q )))) +// \ula_|zx_keyboard_|keys[6][3]~136_combout = (\ula_|zx_keyboard_|keys[6][3]~135_combout & (((\ula_|zx_keyboard_|keys[6][3]~q )))) # (!\ula_|zx_keyboard_|keys[6][3]~135_combout & ((\ula_|ps2_keyboard_|shiftreg [1] & +// (!\ula_|zx_keyboard_|Selector13~0_combout )) # (!\ula_|ps2_keyboard_|shiftreg [1] & ((\ula_|zx_keyboard_|keys[6][3]~q ))))) - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|zx_keyboard_|Selector13~0_combout ), + .dataa(\ula_|zx_keyboard_|Selector13~0_combout ), + .datab(\ula_|zx_keyboard_|keys[6][3]~135_combout ), .datac(\ula_|zx_keyboard_|keys[6][3]~q ), - .datad(\ula_|zx_keyboard_|keys[6][3]~137_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][3]~138_combout ), + .combout(\ula_|zx_keyboard_|keys[6][3]~136_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][3]~138 .lut_mask = 16'hF072; -defparam \ula_|zx_keyboard_|keys[6][3]~138 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[6][3]~136 .lut_mask = 16'hD1F0; +defparam \ula_|zx_keyboard_|keys[6][3]~136 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y21_N29 +// Location: FF_X29_Y9_N9 dffeas \ula_|zx_keyboard_|keys[6][3] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[6][3]~138_combout ), + .d(\ula_|zx_keyboard_|keys[6][3]~136_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -52409,247 +42324,42 @@ defparam \ula_|zx_keyboard_|keys[6][3] .is_wysiwyg = "true"; defparam \ula_|zx_keyboard_|keys[6][3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~2 ( +// Location: LCCOMB_X29_Y9_N30 +cycloneive_lcell_comb \D[3]~56 ( // Equation(s): -// \ula_|zx_keyboard_|key_row~2_combout = (\z80_|address_pins_|DFFE_apin_latch [14]) # ((!\ula_|zx_keyboard_|keys[6][3]~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) +// \D[3]~56_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\z80_|address_pins_|abus[15]~22_combout )) # (!\ula_|zx_keyboard_|keys[7][3]~q ))) # (!\z80_|address_pins_|abus[14]~23_combout & (!\ula_|zx_keyboard_|keys[6][3]~q & +// ((\z80_|address_pins_|abus[15]~22_combout ) # (!\ula_|zx_keyboard_|keys[7][3]~q )))) - .dataa(gnd), - .datab(\z80_|address_pins_|DFFE_apin_latch [14]), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\ula_|zx_keyboard_|keys[6][3]~q ), + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\ula_|zx_keyboard_|keys[7][3]~q ), + .datac(\ula_|zx_keyboard_|keys[6][3]~q ), + .datad(\z80_|address_pins_|abus[15]~22_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|key_row~2_combout ), + .combout(\D[3]~56_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|key_row~2 .lut_mask = 16'hCFFF; -defparam \ula_|zx_keyboard_|key_row~2 .sum_lutc_input = "datac"; +defparam \D[3]~56 .lut_mask = 16'hAF23; +defparam \D[3]~56 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N8 -cycloneive_lcell_comb \D[3]~68 ( +// Location: LCCOMB_X28_Y7_N30 +cycloneive_lcell_comb \D[3]~57 ( // Equation(s): -// \D[3]~68_combout = (\D[3]~67_combout & (\ula_|zx_keyboard_|key_row~2_combout & ((\z80_|address_pins_|abus[15]~22_combout ) # (!\ula_|zx_keyboard_|keys[7][3]~q )))) +// \D[3]~57_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[3]~55_combout & (\D[3]~54_combout & \D[3]~56_combout ))) - .dataa(\z80_|address_pins_|abus[15]~22_combout ), - .datab(\D[3]~67_combout ), - .datac(\ula_|zx_keyboard_|keys[7][3]~q ), - .datad(\ula_|zx_keyboard_|key_row~2_combout ), + .dataa(\D[3]~55_combout ), + .datab(\D[3]~54_combout ), + .datac(\z80_|address_pins_|abus[0]~16_combout ), + .datad(\D[3]~56_combout ), .cin(gnd), - .combout(\D[3]~68_combout ), + .combout(\D[3]~57_combout ), .cout()); // synopsys translate_off -defparam \D[3]~68 .lut_mask = 16'h8C00; -defparam \D[3]~68 .sum_lutc_input = "datac"; +defparam \D[3]~57 .lut_mask = 16'hF8F0; +defparam \D[3]~57 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N30 -cycloneive_lcell_comb \D[3]~69 ( -// Equation(s): -// \D[3]~69_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[3]~65_combout & (\D[3]~66_combout & \D[3]~68_combout ))) - - .dataa(\D[3]~65_combout ), - .datab(\z80_|address_pins_|abus[0]~16_combout ), - .datac(\D[3]~66_combout ), - .datad(\D[3]~68_combout ), - .cin(gnd), - .combout(\D[3]~69_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~69 .lut_mask = 16'hECCC; -defparam \D[3]~69 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y11_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a19 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[3]~96_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_first_bit_number = 3; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y15_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a3 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[3]~96_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; -// synopsys translate_on - -// Location: M9K_X22_Y18_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a11 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[3]~96_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X23_Y15_N14 -cycloneive_lcell_comb \D[3]~73 ( -// Equation(s): -// \D[3]~73_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ) # (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout & ((!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ), - .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .cin(gnd), - .combout(\D[3]~73_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~73 .lut_mask = 16'hCCE2; -defparam \D[3]~73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y5_N0 +// Location: M9K_X33_Y14_N0 cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a27 ( .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), .portare(vcc), @@ -52665,7 +42375,7 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a27 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[3]~96_combout }), + .portadatain({\D[3]~74_combout }), .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , \z80_|address_pins_|abus[0]~16_combout }), @@ -52706,25 +42416,274 @@ defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init1 = 20 defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N16 -cycloneive_lcell_comb \D[3]~74 ( -// Equation(s): -// \D[3]~74_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\D[3]~73_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ))) # (!\D[3]~73_combout & -// (\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\D[3]~73_combout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ), - .datac(\D[3]~73_combout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ), - .cin(gnd), - .combout(\D[3]~74_combout ), - .cout()); +// Location: M9K_X22_Y14_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a3 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[3]~74_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), + .portbdataout()); // synopsys translate_off -defparam \D[3]~74 .lut_mask = 16'hF858; -defparam \D[3]~74 .sum_lutc_input = "datac"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; // synopsys translate_on -// Location: M9K_X22_Y19_N0 +// Location: M9K_X22_Y13_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a19 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[3]~74_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_first_bit_number = 3; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X23_Y14_N26 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6 .lut_mask = 16'hF4A4; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y16_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a11 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[3]~74_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X23_Y14_N22 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout & +// (\ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout )) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ))))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7 .lut_mask = 16'hDAD0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y20_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a3 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h7BBD7F79FFE0AB8FC33758D1C1145DDD6311CF69FFFDF62EDD236FC6A0358FA2B4B15EB89456517DFF58F68BDADB95B5F764CAE7E7C7E7D70CADB8FFD8F9A72BFBB9EB400590D7F939FF5A70A29817DC2CC29B679B2D7146BD21D47EF06F7D5EAF72F66DC666B0726D66FD941AD9BC6D758D5EC24DFEBA64871D6B86D37DF1DFBFF05FBD6AD8CA62C6CBE43BDBFD99E9EB6DD724D235FBEA9FE7D6767D811C40681A00AF8D864D8BB6D2A0916C8A93250A76B8A977F82E8FDFBE68F8E0F8DF237CA976FE488D1069D687A6F1D68A70F37CAAA367A74CBB75D3A6FFB4B1E8D4B7F7F22D2FE1509BDF80E6DD7B717D7E9C6531C3A86BE9F1D7A6AFD5BFB7A37A60; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h8AB3B7FDEE7B9CC735FCCE93E3AC1AAAA691AD6350E57F1F5773302B6F36F63D130E0574D6BB44B2C0D7A907702A748D0BA50F8FA5437ACD3B343C35039F44D19CD4E55E6CB00410842B02A7FD105706DF9E2A1FA025005632A0CC080400D280CCCA0665222D038CC873351A21B23939A98CC08803282189C8440D40CD40462421A40982C046D22C10146484345CAF7BC828BFE79DFBE3C631CBF660C487EBB759BD7F8DE9E0F27A65DE5245BEB8F7829C36F0D136168F97C2BD77D649A39EB4DDB3A42AC80797FDEF4DE3EEF7ED8C7307E4CE6A6317F7BF25D077BBF03AEA3363B065F7D671322D6BFB2B8759433929CEC27E3FD7741292A4A5AF02703CC4E3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'hFD5CB07B6C729B510A78BEC5F7C7A1E7809F1976D0DD3615C1D27D2DF596BFE7A8BCDC2E6655185CC45008B39EFD1FA6E9F5E816114F93E1E7A2A27C72C7349F3497229CB9044B6E7A7861A04A712AAF29EFBD393727F1F3FC2AA1E6CF571457F0A09C47F23F20FE2AABF5FD3ABE6167E5FD36E1D9735BBD5375C1F79BD0424ECF133BF47B9D3DA46DD6DBF3A8ADCDD3DF1176D2FE23447DFC65E1DD7BF3BE5E1C9DCD8EBB9D36AF570CF25CDD16F645D1DE9F9EE575E3A2B91D5659FC131CE3DCD4560015805B13AC0290001EF8261B7E4EB867C828D9777FFF47B6903008DDD7D77EF5E2C6D7220BE64B3C6E9EF22AFDFCC8005C2FFFFA3AB9AD1ADFC0AFE7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h06ABC52D5DBEF57EEB3311A9D85D253B44E250E1566BED57C6DBEB2ABFD1ADF6FF4DEBFBDEB376DF68D5EEDB5EB4D5AB5B79745D76CD8ADC59CB30C8AA33E1551D2FCA8DCB43C5356BAE638588C302868CE1161CACADFEF7696F8C3AA82EC16F47A8EA413A2DCF09B996582318DBF3C4711871B3BC0404EC45252A485234A663C1FFFB3487617BE24FD79501DE05F1A341B89EC82FD5702497FD866639C0DE08B383E6E7C3B310E1F7FF595C5DF6F0E9A9FFFBE16D3FFBE82C1E0051F1E060D500812F408CC6501331852531B04480021D9220D4903A41404312032840153FE9CC8070206B8245AC240020752EBC2BEF3E74AB288F360C239C4AFAE93F68775A; +// synopsys translate_on + +// Location: M9K_X22_Y32_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a11 ( .portawe(vcc), .portare(vcc), @@ -52732,7 +42691,7 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a11 ( .portbwe(gnd), .portbre(vcc), .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .clk1(gnd), .ena0(\z80_|address_pins_|abus[13]~20_combout ), .ena1(vcc), @@ -52782,9 +42741,9 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 204 defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h420539B476E305B8200E47DFAAE8D5D1D0724DCC3FD72C4F8DE54622A1DD1BA78CA3CE9F24BEFA9E2BB9D89B423C327C8E050114401A62FDCD2054E166C0005F7941B61372AC884EE60A372057B59CFF30A6020B875C06E7C5FBDF9A91F8F0588ED67F67AA66B0674CD240410F613700B8DFE7F8837F88FF4520002E4BFD7FA2768008002000002624793100811F43BC315A6004052671392B47FEB7F5DC90E62175C7B8FC48FCC916D46F9315DFDECBE43E5F03D7D27F97E09E4700AA694552A1FF3BE5E159FFDDEB2FBECAEB87BBCC5FCF6E23D77E4DD4C9DEBC93C10F636326FAFE3BE30DFAF7B9E7A5FFE44BF314DAA1C1529CDBFFE9D94EB11A9F68D4DF; // synopsys translate_on -// Location: M9K_X22_Y23_N0 +// Location: M9K_X22_Y22_N0 cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a11 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), @@ -52798,7 +42757,7 @@ cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a11 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[3]~96_combout }), + .portadatain({\D[3]~74_combout }), .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , \z80_|address_pins_|abus[0]~16_combout }), @@ -52855,103 +42814,9 @@ defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 20 defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N24 -cycloneive_lcell_comb \D[3]~70 ( -// Equation(s): -// \D[3]~70_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\z80_|address_pins_|abus[14]~23_combout & ((\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ))) # (!\z80_|address_pins_|abus[14]~23_combout & -// (\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\z80_|address_pins_|abus[14]~23_combout )) - - .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\z80_|address_pins_|abus[14]~23_combout ), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ), - .cin(gnd), - .combout(\D[3]~70_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~70 .lut_mask = 16'hEC64; -defparam \D[3]~70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y21_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a3 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h7BBD7F79FFE0AB8FC33758D1C1145DDD6311CF69FFFDF62EDD236FC6A0358FA2B4B15EB89456517DFF58F68BDADB95B5F764CAE7E7C7E7D70CADB8FFD8F9A72BFBB9EB400590D7F939FF5A70A29817DC2CC29B679B2D7146BD21D47EF06F7D5EAF72F66DC666B0726D66FD941AD9BC6D758D5EC24DFEBA64871D6B86D37DF1DFBFF05FBD6AD8CA62C6CBE43BDBFD99E9EB6DD724D235FBEA9FE7D6767D811C40681A00AF8D864D8BB6D2A0916C8A93250A76B8A977F82E8FDFBE68F8E0F8DF237CA976FE488D1069D687A6F1D68A70F37CAAA367A74CBB75D3A6FFB4B1E8D4B7F7F22D2FE1509BDF80E6DD7B717D7E9C6531C3A86BE9F1D7A6AFD5BFB7A37A60; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h8AB3B7FDEE7B9CC735FCCE93E3AC1AAAA691AD6350E57F1F5773302B6F36F63D130E0574D6BB44B2C0D7A907702A748D0BA50F8FA5437ACD3B343C35039F44D19CD4E55E6CB00410842B02A7FD105706DF9E2A1FA025005632A0CC080400D280CCCA0665222D038CC873351A21B23939A98CC08803282189C8440D40CD40462421A40982C046D22C10146484345CAF7BC828BFE79DFBE3C631CBF660C487EBB759BD7F8DE9E0F27A65DE5245BEB8F7829C36F0D136168F97C2BD77D649A39EB4DDB3A42AC80797FDEF4DE3EEF7ED8C7307E4CE6A6317F7BF25D077BBF03AEA3363B065F7D671322D6BFB2B8759433929CEC27E3FD7741292A4A5AF02703CC4E3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'hFD5CB07B6C729B510A78BEC5F7C7A1E7809F1976D0DD3615C1D27D2DF596BFE7A8BCDC2E6655185CC45008B39EFD1FA6E9F5E816114F93E1E7A2A27C72C7349F3497229CB9044B6E7A7861A04A712AAF29EFBD393727F1F3FC2AA1E6CF571457F0A09C47F23F20FE2AABF5FD3ABE6167E5FD36E1D9735BBD5375C1F79BD0424ECF133BF47B9D3DA46DD6DBF3A8ADCDD3DF1176D2FE23447DFC65E1DD7BF3BE5E1C9DCD8EBB9D36AF570CF25CDD16F645D1DE9F9EE575E3A2B91D5659FC131CE3DCD4560015805B13AC0290001EF8261B7E4EB867C828D9777FFF47B6903008DDD7D77EF5E2C6D7220BE64B3C6E9EF22AFDFCC8005C2FFFFA3AB9AD1ADFC0AFE7; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h06ABC52D5DBEF57EEB3311A9D85D253B44E250E1566BED57C6DBEB2ABFD1ADF6FF4DEBFBDEB376DF68D5EEDB5EB4D5AB5B79745D76CD8ADC59CB30C8AA33E1551D2FCA8DCB43C5356BAE638588C302868CE1161CACADFEF7696F8C3AA82EC16F47A8EA413A2DCF09B996582318DBF3C4711871B3BC0404EC45252A485234A663C1FFFB3487617BE24FD79501DE05F1A341B89EC82FD5702497FD866639C0DE08B383E6E7C3B310E1F7FF595C5DF6F0E9A9FFFBE16D3FFBE82C1E0051F1E060D500812F408CC6501331852531B04480021D9220D4903A41404312032840153FE9CC8070206B8245AC240020752EBC2BEF3E74AB288F360C239C4AFAE93F68775A; -// synopsys translate_on - -// Location: LCCOMB_X23_Y15_N22 -cycloneive_lcell_comb \D[3]~71 ( -// Equation(s): -// \D[3]~71_combout = (\z80_|address_pins_|abus[15]~22_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout $ (((\D[3]~70_combout ))))) # (!\z80_|address_pins_|abus[15]~22_combout & -// (((\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout & !\D[3]~70_combout )))) - - .dataa(\z80_|address_pins_|abus[15]~22_combout ), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ), - .datad(\D[3]~70_combout ), - .cin(gnd), - .combout(\D[3]~71_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~71 .lut_mask = 16'h22D8; -defparam \D[3]~71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y31_N0 +// Location: M9K_X22_Y30_N0 cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a3 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), @@ -52965,7 +42830,7 @@ cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a3 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[3]~96_combout }), + .portadatain({\D[3]~74_combout }), .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , \z80_|address_pins_|abus[0]~16_combout }), @@ -53021,95 +42886,113 @@ defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 204 defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h022388704B6887014BD84185680166815764AC0148D308813FFFFFFC0000000003228A304BA085014BFC40816C0166915375AC0140D308013FFFFFFC40000000432289294EB08F014A1C40816C016681537DA80140D10E01400000017FFFFFFE406281154FB08D014A0040894C016299437DB00140D10F01400000037FFFFFFE4062A13149A88D814BE0429146016EA14179B001405107017FFFFFFF0000000043E0812549C889814BE0528146016C814179924140511F413FFFFFFE0000000043E881314EE881814A00468147436C814159100100513F0000000000FFFFFFFF4B6883014EA881814800668147C22C814019900100003E0000000000FFFFFFFF; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N20 -cycloneive_lcell_comb \D[3]~72 ( +// Location: LCCOMB_X23_Y14_N24 +cycloneive_lcell_comb \Selector3~1 ( // Equation(s): -// \D[3]~72_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\D[3]~70_combout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[3]~70_combout & (!\D[3]~71_combout & -// \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout )) # (!\D[3]~70_combout & (\D[3]~71_combout )))) +// \Selector3~1_combout = (\Selector3~0_combout & (((\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout )) # (!\z80_|address_pins_|abus[14]~23_combout ))) # (!\Selector3~0_combout & (\z80_|address_pins_|abus[14]~23_combout & +// ((\ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout )))) - .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\D[3]~70_combout ), - .datac(\D[3]~71_combout ), + .dataa(\Selector3~0_combout ), + .datab(\z80_|address_pins_|abus[14]~23_combout ), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ), .datad(\ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ), .cin(gnd), - .combout(\D[3]~72_combout ), + .combout(\Selector3~1_combout ), .cout()); // synopsys translate_off -defparam \D[3]~72 .lut_mask = 16'h9C98; -defparam \D[3]~72 .sum_lutc_input = "datac"; +defparam \Selector3~1 .lut_mask = 16'hE6A2; +defparam \Selector3~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N28 -cycloneive_lcell_comb \D[3]~108 ( +// Location: LCCOMB_X23_Y14_N16 +cycloneive_lcell_comb \Selector3~2 ( // Equation(s): -// \D[3]~108_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (\D[3]~74_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\D[3]~72_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & -// (\D[3]~74_combout )))) +// \Selector3~2_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\Selector3~1_combout )))) # (!\z80_|address_pins_|abus[14]~23_combout & ((\Selector3~1_combout & ((\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ))) # +// (!\Selector3~1_combout & (\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout )))) + + .dataa(\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ), + .datab(\z80_|address_pins_|abus[14]~23_combout ), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ), + .datad(\Selector3~1_combout ), + .cin(gnd), + .combout(\Selector3~2_combout ), + .cout()); +// synopsys translate_off +defparam \Selector3~2 .lut_mask = 16'hFC22; +defparam \Selector3~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y14_N10 +cycloneive_lcell_comb \D[3]~85 ( +// Equation(s): +// \D[3]~85_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\Selector3~2_combout +// ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout )))) .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), - .datab(\D[3]~74_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\D[3]~72_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout ), + .datad(\Selector3~2_combout ), .cin(gnd), - .combout(\D[3]~108_combout ), + .combout(\D[3]~85_combout ), .cout()); // synopsys translate_off -defparam \D[3]~108 .lut_mask = 16'hDC8C; -defparam \D[3]~108 .sum_lutc_input = "datac"; +defparam \D[3]~85 .lut_mask = 16'hF4B0; +defparam \D[3]~85 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N4 -cycloneive_lcell_comb \D[3]~95 ( +// Location: LCCOMB_X23_Y14_N2 +cycloneive_lcell_comb \D[3]~73 ( // Equation(s): -// \D[3]~95_combout = ((\Equal2~0_combout & (\D[3]~69_combout )) # (!\Equal2~0_combout & ((\D[3]~108_combout )))) # (!\Equal2~1_combout ) +// \D[3]~73_combout = ((\Equal2~0_combout & (\D[3]~57_combout )) # (!\Equal2~0_combout & ((\D[3]~85_combout )))) # (!\Equal2~1_combout ) - .dataa(\D[3]~69_combout ), + .dataa(\D[3]~57_combout ), .datab(\Equal2~1_combout ), .datac(\Equal2~0_combout ), - .datad(\D[3]~108_combout ), + .datad(\D[3]~85_combout ), .cin(gnd), - .combout(\D[3]~95_combout ), + .combout(\D[3]~73_combout ), .cout()); // synopsys translate_off -defparam \D[3]~95 .lut_mask = 16'hBFB3; -defparam \D[3]~95 .sum_lutc_input = "datac"; +defparam \D[3]~73 .lut_mask = 16'hBFB3; +defparam \D[3]~73 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N26 -cycloneive_lcell_comb \D[3]~96 ( +// Location: LCCOMB_X23_Y14_N8 +cycloneive_lcell_comb \D[3]~74 ( // Equation(s): -// \D[3]~96_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\z80_|data_pins_|dout [3] & \D[3]~95_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\D[3]~95_combout )) # (!\Equal2~1_combout ))) +// \D[3]~74_combout = (\z80_|pin_control_|bus_db_pin_oe~15_combout & (\z80_|data_pins_|dout [3] & ((\D[3]~73_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout & (((\D[3]~73_combout ) # (!\Equal2~1_combout )))) - .dataa(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .dataa(\z80_|data_pins_|dout [3]), .datab(\Equal2~1_combout ), - .datac(\z80_|data_pins_|dout [3]), - .datad(\D[3]~95_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .datad(\D[3]~73_combout ), .cin(gnd), - .combout(\D[3]~96_combout ), + .combout(\D[3]~74_combout ), .cout()); // synopsys translate_off -defparam \D[3]~96 .lut_mask = 16'hF511; -defparam \D[3]~96 .sum_lutc_input = "datac"; +defparam \D[3]~74 .lut_mask = 16'hAF03; +defparam \D[3]~74 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y13_N6 +// Location: LCCOMB_X30_Y13_N16 cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] ( // Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [3] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[3]~21_combout ) # ((\D[3]~96_combout & \z80_|pin_control_|bus_db_pin_re~combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & -// (\D[3]~96_combout & (\z80_|pin_control_|bus_db_pin_re~combout ))) +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [3] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[3]~21_combout ) # ((\z80_|pin_control_|bus_db_pin_re~combout & \D[3]~74_combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & +// (\z80_|pin_control_|bus_db_pin_re~combout & ((\D[3]~74_combout )))) .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(\D[3]~96_combout ), - .datac(\z80_|pin_control_|bus_db_pin_re~combout ), - .datad(\z80_|bus_control_|db[3]~21_combout ), + .datab(\z80_|pin_control_|bus_db_pin_re~combout ), + .datac(\z80_|bus_control_|db[3]~21_combout ), + .datad(\D[3]~74_combout ), .cin(gnd), .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [3]), .cout()); // synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] .lut_mask = 16'hEAC0; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] .lut_mask = 16'hECA0; defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y13_N7 +// Location: FF_X30_Y13_N17 dffeas \z80_|data_pins_|dout[3] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [3]), @@ -53128,44 +43011,903 @@ defparam \z80_|data_pins_|dout[3] .is_wysiwyg = "true"; defparam \z80_|data_pins_|dout[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N4 +// Location: LCCOMB_X29_Y13_N20 cycloneive_lcell_comb \z80_|bus_control_|db[3]~20 ( // Equation(s): // \z80_|bus_control_|db[3]~20_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [3]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) - .dataa(\z80_|execute_|ctl_bus_db_oe~combout ), - .datab(\z80_|data_pins_|dout [3]), - .datac(gnd), - .datad(\z80_|bus_control_|db[0]~4_combout ), + .dataa(gnd), + .datab(\z80_|bus_control_|db[0]~4_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~combout ), + .datad(\z80_|data_pins_|dout [3]), .cin(gnd), .combout(\z80_|bus_control_|db[3]~20_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[3]~20 .lut_mask = 16'hDD00; +defparam \z80_|bus_control_|db[3]~20 .lut_mask = 16'hCC0C; defparam \z80_|bus_control_|db[3]~20 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y10_N0 +// Location: LCCOMB_X30_Y17_N30 cycloneive_lcell_comb \z80_|bus_control_|db[3]~21 ( // Equation(s): // \z80_|bus_control_|db[3]~21_combout = ((\z80_|bus_control_|db[3]~20_combout & ((\z80_|alu_control_|db[3]~35_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) .dataa(\z80_|bus_control_|db[0]~6_combout ), - .datab(\z80_|bus_control_|db[3]~20_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|alu_control_|db[3]~35_combout ), + .datab(\z80_|alu_control_|db[3]~35_combout ), + .datac(\z80_|bus_control_|db[3]~20_combout ), + .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), .cin(gnd), .combout(\z80_|bus_control_|db[3]~21_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[3]~21 .lut_mask = 16'hDD5D; +defparam \z80_|bus_control_|db[3]~21 .lut_mask = 16'hD5F5; defparam \z80_|bus_control_|db[3]~21 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X34_Y10_N1 -dffeas \z80_|ir_|opcode[3] ( +// Location: LCCOMB_X30_Y17_N12 +cycloneive_lcell_comb \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 ( +// Equation(s): +// \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout = (\z80_|bus_control_|db[4]~19_combout & \z80_|bus_control_|db[3]~21_combout ) + + .dataa(gnd), + .datab(\z80_|bus_control_|db[4]~19_combout ), + .datac(\z80_|bus_control_|db[3]~21_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 .lut_mask = 16'hC0C0; +defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y17_N13 +dffeas \z80_|interrupts_|im2 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|bus_control_|db[3]~21_combout ), + .d(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_im_we~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|interrupts_|im2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|interrupts_|im2 .is_wysiwyg = "true"; +defparam \z80_|interrupts_|im2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~10 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~10_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|interrupts_|im2~q & \z80_|interrupts_|DFFE_inst44~q )) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|interrupts_|im2~q ), + .datac(\z80_|interrupts_|DFFE_inst44~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~10 .lut_mask = 16'h4040; +defparam \z80_|execute_|ctl_mRead~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_mask543_en~0 ( +// Equation(s): +// \z80_|execute_|ctl_sw_mask543_en~0_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (!\z80_|execute_|ctl_mRead~10_combout & (\z80_|pla_decode_|Equal47~0_combout & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|execute_|ctl_mRead~10_combout ), + .datac(\z80_|pla_decode_|Equal47~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_mask543_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_mask543_en~0 .lut_mask = 16'h1000; +defparam \z80_|execute_|ctl_sw_mask543_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N24 +cycloneive_lcell_comb \z80_|alu_control_|db[7]~16 ( +// Equation(s): +// \z80_|alu_control_|db[7]~16_combout = (\z80_|alu_flags_|DFFE_inst_latch_sf~q & (!\z80_|alu_|db[7]~12_combout & ((\z80_|execute_|ctl_sw_2u~7_combout )))) # (!\z80_|alu_flags_|DFFE_inst_latch_sf~q & ((\z80_|execute_|ctl_flags_oe~2_combout ) # +// ((!\z80_|alu_|db[7]~12_combout & \z80_|execute_|ctl_sw_2u~7_combout )))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), + .datab(\z80_|alu_|db[7]~12_combout ), + .datac(\z80_|execute_|ctl_flags_oe~2_combout ), + .datad(\z80_|execute_|ctl_sw_2u~7_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[7]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[7]~16 .lut_mask = 16'h7350; +defparam \z80_|alu_control_|db[7]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N6 +cycloneive_lcell_comb \z80_|alu_control_|db[7]~17 ( +// Equation(s): +// \z80_|alu_control_|db[7]~17_combout = (!\z80_|alu_control_|db[7]~16_combout & (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & ((\z80_|reg_file_|gdfx_temp0[7]~91_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), + .datab(\z80_|alu_control_|db[7]~16_combout ), + .datac(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[7]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[7]~17 .lut_mask = 16'h2030; +defparam \z80_|alu_control_|db[7]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N12 +cycloneive_lcell_comb \z80_|alu_control_|db[7]~18 ( +// Equation(s): +// \z80_|alu_control_|db[7]~18_combout = (\z80_|alu_control_|db[7]~17_combout & (((!\z80_|execute_|ctl_sw_mask543_en~0_combout & \z80_|bus_control_|db[7]~7_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) + + .dataa(\z80_|execute_|ctl_sw_mask543_en~0_combout ), + .datab(\z80_|bus_control_|db[7]~7_combout ), + .datac(\z80_|execute_|ctl_sw_1d~7_combout ), + .datad(\z80_|alu_control_|db[7]~17_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[7]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[7]~18 .lut_mask = 16'h4F00; +defparam \z80_|alu_control_|db[7]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N26 +cycloneive_lcell_comb \z80_|alu_control_|db[7]~19 ( +// Equation(s): +// \z80_|alu_control_|db[7]~19_combout = (\z80_|alu_control_|db[7]~18_combout ) # (!\z80_|alu_control_|db[6]~11_combout ) + + .dataa(\z80_|alu_control_|db[7]~18_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|alu_control_|db[6]~11_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[7]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[7]~19 .lut_mask = 16'hAAFF; +defparam \z80_|alu_control_|db[7]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N28 +cycloneive_lcell_comb \z80_|bus_control_|db[7]~5 ( +// Equation(s): +// \z80_|bus_control_|db[7]~5_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[7]~19_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datab(\z80_|bus_control_|db[0]~4_combout ), + .datac(gnd), + .datad(\z80_|alu_control_|db[7]~19_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[7]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[7]~5 .lut_mask = 16'hCC44; +defparam \z80_|bus_control_|db[7]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N2 +cycloneive_lcell_comb \D[5]~67 ( +// Equation(s): +// \D[5]~67_combout = (!\z80_|memory_ifc_|nIORQ_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\z80_|memory_ifc_|nRD_out~2_combout & !\z80_|memory_ifc_|nWR_out~0_combout ))) + + .dataa(\z80_|memory_ifc_|nIORQ_out~0_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|memory_ifc_|nRD_out~2_combout ), + .datad(\z80_|memory_ifc_|nWR_out~0_combout ), + .cin(gnd), + .combout(\D[5]~67_combout ), + .cout()); +// synopsys translate_off +defparam \D[5]~67 .lut_mask = 16'h0040; +defparam \D[5]~67 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y21_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a7 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[7]~80_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081; +// synopsys translate_on + +// Location: M9K_X33_Y20_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a23 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[7]~80_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_first_bit_number = 7; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N10 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout ) # +// (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout & +// ((!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14 .lut_mask = 16'hCCE2; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y18_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a31 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[7]~80_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a31_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_first_bit_number = 7; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y16_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a15 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[7]~80_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N24 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15_combout = (\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ) # +// ((!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14_combout & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & +// \ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14_combout ), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15 .lut_mask = 16'hDA8A; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y29_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a15 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h3C0000000000000000000000000000000000000000000000000000000000000080000000000002000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFB91060128E2D09899B4D10A148392808351AD282E76190E029FDC286449331D89080802222C0D04D1121484041D21084C223B0A12EBE72083D81421B93CA9589A04864A853089602E536320C2A5944831907110C246020089C76EE701A4E23964C6586008731635460418000008202040C300110000FCE7E12403749F8C6AB8F69167210EF8A4B8228710884C5C47A9986E8840C02862C088C36E19CF1D315; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h03020CCE064769B15020A6030880234C64E9BEF8E98A81489083A026140D648906E5AD6C882882990A40D293FED064710CB226CDA0330D7B189B344442EC35E3763C75FA1DB107B865E5B8F7B95E77F222244C6BDC1879C0562EF779BE0009465775469089F04C623E19317B486F653C1C22CA642CD685C10EE47EDD66C8C226C7C57F084106FB3B8B1E47463C0088D11104F23C180222A0AA22A22882A202A00000000288964258156302504F5F660C054DEDCA20CC201A4074192601E376C9596CD8B4B568A4DFEF3DBF8027A3422A56A2C003E514582104BF8D6B5D80BB397FBBEC46E8B3CAEBE0100275A1092081D0C1E5716DF09CFEEC00AD800529E1A8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h873CB568FC3F09080F4400DAC600092017210911A6081DCC4979244124815884AE6302C4BE6BA8C22A084803225A0855ABBBC528B1CA2456A4951A53C1209153CFC3000F43632B49C39723270C604B184D1940F1B2A04459BEB088666843BB38C23A8D170CED981891256A2C1D9B31C0F040202103900E6765976089DB8DE16E0001022EC10015E263787F7E581EF83F062200C626EC4E19021840D9C112400C4B987A78AE1BF80005EF370C0739371E0D3E5CF1E3677332370BB98D1831B30F7D8CDC0131C444798F040DC0116E2C4336B0166109A15D1FCC7EDE31EB23862203C11245EE31E38E6DEF2188BE2068F3C716E10317783020D8EF5C256774BA0E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h1B9CE2DA363196DC20007FF5554FC631286DC716B048384C26510685218DF9E6C629E6050C619658692170C1022C2232C965C92C189020C705873084858910322166D72DC524870C422BBFFD4808A7032B088DE3000B853800736C8E9968C19A4B72C08871D2413188E4829219C38C2025920480D64856902E4D4D60B640C833C14D536A45D144B244C24A290076E58CC2E64E4A2DC4C5939C4C2DDBD1B918B231248625B2C0DD0F07A27A111CB80A48808C7C21C205029100010400228BB3BDFF7DCCEF40196C8381658D8840043B119B86A46247665810E2203000141023C366CB633B3376DC625DA8A0856C484392B779E1BA4088EDB4A6CDB9BD46DCC0B2; +// synopsys translate_on + +// Location: M9K_X33_Y23_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a15 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(gnd), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[7]~80_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_first_bit_number = 7; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y24_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a7 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[7]~80_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_first_bit_number = 7; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h000000000000000000000000FFFFFFFFC0810207C0001A176020155177486D89000000000000000000000000FFFFFFFF80000003C0000217724019F17748EDC900000000000000000000000000000001BF7EFDF9400406B17A400BF57748AD81000000000000000000000000000000013F7EFDF940041EB1724218157749A7910000000000000000000000003F7EFDF90000000140042AF97B426C157DC9B7590000000000000000000000003F7EFDF90000000140042069600246057DC95351000000000000000000000000408102053FFFFFF95FE4084175C246896009F35100000000000000000000000040810207BFFFFFFF7FE4147177C2004960291759; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h7FE8374958F827C15FF88F91E9A80DC3629A9FC172033EC170FB0E8173F792815FE826E158F805C95FF8AF8169A80DC3629A1EC17B033BC1706B3E8173FFB0C1400826E558F805C15DF8AF9169A82DD163C21BC17B133BC1716B3781723F14C1400826E958D825815DD8AF8168482DC161229BC17A133FC171AB3781723F16E9400826E95818058179582F9160480FC162229FC17ACA39C172FB3F8152CF10A1400826E958180D8179580F05614C0DC162329BC171EB398173537F8152E310D1400826E158180D81F8580FD1612C0F41631293C173BB398D63037F81D22313D1400827E958080F01F8188FCB60A40F41435083C1723B198161834F01D67300E3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'hD4FB0D2352268F0151E680016803440977EDE98148F31101BFFFFFFF4081010750FB094B52728F0151FEC0016C034C0153EDA90148F31F013FFFFFFB4081010152F3096156DA8901503ED2016C03480173FDA00148F11F01000000013F7EFEF952E3017156DA85015022C2016C034C0153FCA00148F10F01000000013F7EFEF956B3A9115052850543C2C2116C014D2153FDA12148D11F013F7EFEF900000001469F8B3150728D0143C05A016D014C81537DA00148D11E01BF7EFEF900000001528F8F2156628D0140004E016F054481513DA181C8513E0580000007FFFFFFFF528E8B2156E28C0148024E0167676C415139B041C8513E07C0810107FFFFFFFF; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N14 +cycloneive_lcell_comb \Mux0~0 ( +// Equation(s): +// \Mux0~0_combout = (\z80_|address_pins_|abus[14]~23_combout & ((\Selector3~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout )) # (!\Selector3~0_combout & +// ((\ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout ))))) # (!\z80_|address_pins_|abus[14]~23_combout & (((\Selector3~0_combout )))) + + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout ), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout ), + .datad(\Selector3~0_combout ), + .cin(gnd), + .combout(\Mux0~0_combout ), + .cout()); +// synopsys translate_off +defparam \Mux0~0 .lut_mask = 16'hDDA0; +defparam \Mux0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y32_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a7 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h7C762E21DB2481CB6BB88C68811C76C63B18ECC1BACDC6110DCC70BC20940800C71478E35468600B01A93082C63DD073AE4181844449C08D8D56B0DCC881251C202139803D3000B2E0209DB9101160989A5916381001B0446631006064DB1B996E436E644CF6C8606F124DA230E9B66E2F46BB466E2CE068661B4B05F02F7D00CB3E518948104042F84F1840401018406877D800A00000F5122597005DA4411000800020249004081008924124080114000000020BFFFFEC638C31207B6C321407D901787004001C459326210CCE00C6AF707B84440C313110B8C4D13B2C6E06C4C088B1A9B24BEB0178C4D6C18230DF72B07A28063647CC4721026D8C711864; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h881B30810845E6D18622EC9B6236A000030986A4F0644601226000A2F220D40310438334E51C28000400B18422CA60FC42C9C03F066366ECBBB010B00B004807CC0E00DAEC3000194A52B80C606262092D84A1102410000001400010002000800200080020000800200008000800400040002004000040002000020002000801000010004002001000200008000AEE708008880C86112251B45B36C0048833B319B4C2CE6660D2C0619246C4B208BC0AD00202001E104FC30911410804201E92102B400E8004C40AD6E4614466308ABC7165AA57060A3A736A188ABB300200A10BB04344008422327B1393C43396A931B8C8C87227A6141C0E2DCC76D830B082; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h101CC0024A6C32005CCB31908842211604D8B326101118B54B188CB4D502F5F02DA65C2472B824F109BC594C2401209C01A0E59830002C73B396C6015B85A163184B56183004204267600220A061A004893E1D609106BDBB553920A011AA5AE581E08228382D54C2989BC59535528176240438C9AA757917F95C7428981A26470D1C3E528444D9B00E561C40973AE1806031C464834F03D34A11233A34B34A1D1A55A50C3384B549B64C381920140D4008004020B119D5834C10064000006001169808000200040100000002F8986E37654DDFF88E20860382DC089D4C239F6E4C3C8D784218667F524CE209881213DC91099C14744901620044C802DA414966; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h84724A241226DB4809C9A1100DE6A63984D651A2624A09420496DDC12CC10964B6E370363701B41848117683379C8422106D001BB41FB8248067301E1002C636A276585D5273AC87206840415DA74B4E9D213CAE3234B308E19608AA38250844883838649E1442A0D983F4A9094A5AD4A52D56C5D80CAC58D9645944A230091549F30426B100842A12B25160D6D991E6C8C81AFB4C644004C2140A342020D84C9001624489A10045D16C944B02763FF55405E400BADFE5BFFFFFF00000000011042250089108884888410924041204444209102084241104204108824114455292225124929249248894408541300A6DB00791E5B12FEF24037181F1901B007B; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N16 +cycloneive_lcell_comb \Mux0~1 ( +// Equation(s): +// \Mux0~1_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\Mux0~0_combout )))) # (!\z80_|address_pins_|abus[14]~23_combout & ((\Mux0~0_combout & (\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout )) # (!\Mux0~0_combout & +// ((\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ))))) + + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ), + .datac(\Mux0~0_combout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ), + .cin(gnd), + .combout(\Mux0~1_combout ), + .cout()); +// synopsys translate_off +defparam \Mux0~1 .lut_mask = 16'hE5E0; +defparam \Mux0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N22 +cycloneive_lcell_comb \D[7]~89 ( +// Equation(s): +// \D[7]~89_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [15] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\Mux0~1_combout ))))) # +// (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15_combout )) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15_combout ), + .datac(\z80_|address_pins_|DFFE_apin_latch [15]), + .datad(\Mux0~1_combout ), + .cin(gnd), + .combout(\D[7]~89_combout ), + .cout()); +// synopsys translate_off +defparam \D[7]~89 .lut_mask = 16'hCEC4; +defparam \D[7]~89 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N30 +cycloneive_lcell_comb \D[7]~72 ( +// Equation(s): +// \D[7]~72_combout = (\D[5]~67_combout & (\D[7]~89_combout & ((\z80_|data_pins_|dout [7]) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout )))) # (!\D[5]~67_combout & ((\z80_|data_pins_|dout [7]) # ((!\z80_|pin_control_|bus_db_pin_oe~15_combout )))) + + .dataa(\D[5]~67_combout ), + .datab(\z80_|data_pins_|dout [7]), + .datac(\D[7]~89_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .cin(gnd), + .combout(\D[7]~72_combout ), + .cout()); +// synopsys translate_off +defparam \D[7]~72 .lut_mask = 16'hC4F5; +defparam \D[7]~72 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N12 +cycloneive_lcell_comb \D[0]~84 ( +// Equation(s): +// \D[0]~84_combout = (\z80_|pin_control_|bus_db_pin_oe~15_combout ) # ((\z80_|memory_ifc_|nRD_out~2_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|memory_ifc_|nWR_out~0_combout ))) + + .dataa(\z80_|memory_ifc_|nRD_out~2_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .datad(\z80_|memory_ifc_|nWR_out~0_combout ), + .cin(gnd), + .combout(\D[0]~84_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~84 .lut_mask = 16'hF0F8; +defparam \D[0]~84 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N6 +cycloneive_lcell_comb \D[7]~80 ( +// Equation(s): +// \D[7]~80_combout = (\D[7]~72_combout ) # (!\D[0]~84_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\D[7]~72_combout ), + .datad(\D[0]~84_combout ), + .cin(gnd), + .combout(\D[7]~80_combout ), + .cout()); +// synopsys translate_off +defparam \D[7]~80 .lut_mask = 16'hF0FF; +defparam \D[7]~80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N12 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [7] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[7]~7_combout ) # ((\D[7]~80_combout & \z80_|pin_control_|bus_db_pin_re~combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & +// (((\D[7]~80_combout & \z80_|pin_control_|bus_db_pin_re~combout )))) + + .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datab(\z80_|bus_control_|db[7]~7_combout ), + .datac(\D[7]~80_combout ), + .datad(\z80_|pin_control_|bus_db_pin_re~combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [7]), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] .lut_mask = 16'hF888; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y13_N13 +dffeas \z80_|data_pins_|dout[7] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [7]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|data_pins_|dout [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|data_pins_|dout[7] .is_wysiwyg = "true"; +defparam \z80_|data_pins_|dout[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N20 +cycloneive_lcell_comb \z80_|bus_control_|db[7]~7 ( +// Equation(s): +// \z80_|bus_control_|db[7]~7_combout = ((\z80_|bus_control_|db[7]~5_combout & ((\z80_|data_pins_|dout [7]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) + + .dataa(\z80_|bus_control_|db[0]~6_combout ), + .datab(\z80_|bus_control_|db[7]~5_combout ), + .datac(\z80_|data_pins_|dout [7]), + .datad(\z80_|execute_|ctl_bus_db_oe~combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[7]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[7]~7 .lut_mask = 16'hD5DD; +defparam \z80_|bus_control_|db[7]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y13_N21 +dffeas \z80_|ir_|opcode[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|bus_control_|db[7]~7_combout ), .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), @@ -53174,65 +43916,9090 @@ dffeas \z80_|ir_|opcode[3] ( .ena(\z80_|execute_|ctl_ir_we~13_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|ir_|opcode [3]), + .q(\z80_|ir_|opcode [7]), .prn(vcc)); // synopsys translate_off -defparam \z80_|ir_|opcode[3] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[3] .power_up = "low"; +defparam \z80_|ir_|opcode[7] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X40_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~4 ( +// Location: LCCOMB_X29_Y13_N30 +cycloneive_lcell_comb \z80_|pla_decode_|Equal6~0 ( // Equation(s): -// \z80_|execute_|ctl_mWrite~4_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal52~0_combout ))) +// \z80_|pla_decode_|Equal6~0_combout = (!\z80_|decode_state_|DFFE_instED~q & (!\z80_|decode_state_|DFFE_instCB~q & (!\z80_|ir_|opcode [7] & !\z80_|ir_|opcode [6]))) - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal3~1_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal52~0_combout ), + .dataa(\z80_|decode_state_|DFFE_instED~q ), + .datab(\z80_|decode_state_|DFFE_instCB~q ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|ir_|opcode [6]), .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~4_combout ), + .combout(\z80_|pla_decode_|Equal6~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~4 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_mWrite~4 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal6~0 .lut_mask = 16'h0001; +defparam \z80_|pla_decode_|Equal6~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y17_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~2 ( +// Location: LCCOMB_X21_Y16_N4 +cycloneive_lcell_comb \z80_|pla_decode_|Equal12~0 ( // Equation(s): -// \z80_|execute_|ctl_apin_mux~2_combout = ((\z80_|execute_|ctl_mWrite~4_combout & \z80_|execute_|ctl_apin_mux~1_combout )) # (!\z80_|execute_|ctl_inc_dec~6_combout ) +// \z80_|pla_decode_|Equal12~0_combout = (!\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [0]))) - .dataa(\z80_|execute_|ctl_mWrite~4_combout ), - .datab(\z80_|execute_|ctl_apin_mux~1_combout ), - .datac(\z80_|execute_|ctl_inc_dec~6_combout ), + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal12~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal12~0 .lut_mask = 16'h0040; +defparam \z80_|pla_decode_|Equal12~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~16 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~16_combout = (\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal12~0_combout & \z80_|ir_|opcode [3]))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|pla_decode_|Equal12~0_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~16 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_mRead~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|fMRead~24 ( +// Equation(s): +// \z80_|execute_|fMRead~24_combout = (\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_mRead~16_combout ) # ((\z80_|execute_|ctl_mRead~15_combout )))) # (!\z80_|execute_|ctl_ir_we~4_combout & (\z80_|execute_|ctl_alu_oe~0_combout & +// ((\z80_|execute_|ctl_mRead~16_combout ) # (\z80_|execute_|ctl_mRead~15_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|execute_|ctl_mRead~16_combout ), + .datac(\z80_|execute_|ctl_mRead~15_combout ), + .datad(\z80_|execute_|ctl_alu_oe~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~24 .lut_mask = 16'hFCA8; +defparam \z80_|execute_|fMRead~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N12 +cycloneive_lcell_comb \z80_|execute_|fMRead~25 ( +// Equation(s): +// \z80_|execute_|fMRead~25_combout = ((\z80_|execute_|fMRead~24_combout ) # ((\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|pc_inc_hold~26_combout ))) # (!\z80_|execute_|ctl_bus_db_oe~0_combout ) + + .dataa(\z80_|execute_|ctl_bus_db_oe~0_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|fMRead~24_combout ), + .datad(\z80_|execute_|pc_inc_hold~26_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~25 .lut_mask = 16'hF5FD; +defparam \z80_|execute_|fMRead~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~21 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~21_combout = (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|decode_state_|in_halt~q & (!\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal77~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|decode_state_|in_halt~q ), + .datac(\z80_|decode_state_|use_ixiy~combout ), + .datad(\z80_|pla_decode_|Equal77~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~21 .lut_mask = 16'h0200; +defparam \z80_|execute_|ctl_mRead~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|fMRead~16 ( +// Equation(s): +// \z80_|execute_|fMRead~16_combout = (\z80_|execute_|ctl_ir_we~11_combout ) # ((\z80_|execute_|ctl_ir_we~12_combout ) # ((\z80_|execute_|ctl_mRead~13_combout ) # (\z80_|execute_|ctl_mRead~21_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~11_combout ), + .datab(\z80_|execute_|ctl_ir_we~12_combout ), + .datac(\z80_|execute_|ctl_mRead~13_combout ), + .datad(\z80_|execute_|ctl_mRead~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~16 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|fMRead~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|fMRead~14 ( +// Equation(s): +// \z80_|execute_|fMRead~14_combout = (\z80_|execute_|ctl_ir_we~14_combout ) # ((\z80_|execute_|ctl_ir_we~8_combout ) # ((!\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal49~0_combout ))) + + .dataa(\z80_|decode_state_|use_ixiy~combout ), + .datab(\z80_|pla_decode_|Equal49~0_combout ), + .datac(\z80_|execute_|ctl_ir_we~14_combout ), + .datad(\z80_|execute_|ctl_ir_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~14 .lut_mask = 16'hFFF4; +defparam \z80_|execute_|fMRead~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y14_N2 +cycloneive_lcell_comb \z80_|execute_|fMRead~15 ( +// Equation(s): +// \z80_|execute_|fMRead~15_combout = (!\z80_|execute_|fMWrite~3_combout & ((\z80_|execute_|ctl_ir_we~11_combout ) # ((\z80_|execute_|ctl_mRead~4_combout ) # (\z80_|execute_|fMRead~14_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~11_combout ), + .datab(\z80_|execute_|ctl_mRead~4_combout ), + .datac(\z80_|execute_|fMRead~14_combout ), + .datad(\z80_|execute_|fMWrite~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~15 .lut_mask = 16'h00FE; +defparam \z80_|execute_|fMRead~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|fMRead~12 ( +// Equation(s): +// \z80_|execute_|fMRead~12_combout = (!\z80_|pla_decode_|Equal13~2_combout & (!\z80_|execute_|ctl_mRead~2_combout & (!\z80_|pla_decode_|Equal6~1_combout & \z80_|execute_|ctl_bus_db_oe~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(\z80_|execute_|ctl_mRead~2_combout ), + .datac(\z80_|pla_decode_|Equal6~1_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~12 .lut_mask = 16'h0100; +defparam \z80_|execute_|fMRead~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y14_N18 +cycloneive_lcell_comb \z80_|execute_|fMRead~11 ( +// Equation(s): +// \z80_|execute_|fMRead~11_combout = (((\z80_|execute_|ctl_mRead~11_combout ) # (\z80_|execute_|ctl_mRead~21_combout )) # (!\z80_|execute_|pc_inc_hold~6_combout )) # (!\z80_|execute_|nextM~3_combout ) + + .dataa(\z80_|execute_|nextM~3_combout ), + .datab(\z80_|execute_|pc_inc_hold~6_combout ), + .datac(\z80_|execute_|ctl_mRead~11_combout ), + .datad(\z80_|execute_|ctl_mRead~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~11 .lut_mask = 16'hFFF7; +defparam \z80_|execute_|fMRead~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|fMRead~13 ( +// Equation(s): +// \z80_|execute_|fMRead~13_combout = (\z80_|execute_|ctl_state_alu~2_combout & (((\z80_|execute_|ctl_ir_we~14_combout ) # (\z80_|execute_|fMRead~11_combout )) # (!\z80_|execute_|fMRead~12_combout ))) + + .dataa(\z80_|execute_|fMRead~12_combout ), + .datab(\z80_|execute_|ctl_ir_we~14_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|fMRead~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~13 .lut_mask = 16'hF0D0; +defparam \z80_|execute_|fMRead~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y14_N6 +cycloneive_lcell_comb \z80_|execute_|fMRead~17 ( +// Equation(s): +// \z80_|execute_|fMRead~17_combout = (\z80_|execute_|fMRead~15_combout ) # ((\z80_|execute_|fMRead~13_combout ) # ((\z80_|execute_|fMRead~16_combout & \z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|execute_|fMRead~16_combout ), + .datab(\z80_|execute_|fMRead~15_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|fMRead~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~17 .lut_mask = 16'hFFEC; +defparam \z80_|execute_|fMRead~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|fMRead~22 ( +// Equation(s): +// \z80_|execute_|fMRead~22_combout = (\z80_|execute_|fMRead~17_combout ) # (((!\z80_|execute_|fMRead~21_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~40_combout )) # (!\z80_|execute_|ctl_sw_4d~2_combout )) + + .dataa(\z80_|execute_|fMRead~17_combout ), + .datab(\z80_|execute_|ctl_sw_4d~2_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~40_combout ), + .datad(\z80_|execute_|fMRead~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~22 .lut_mask = 16'hBFFF; +defparam \z80_|execute_|fMRead~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|fMRead~27 ( +// Equation(s): +// \z80_|execute_|fMRead~27_combout = ((\z80_|sequencer_|DFFE_M2_ff~q & (!\z80_|execute_|ixy_d~4_combout & \z80_|execute_|ctl_mRead~12_combout ))) # (!\z80_|execute_|fMRead~26_combout ) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|execute_|fMRead~26_combout ), + .datac(\z80_|execute_|ixy_d~4_combout ), + .datad(\z80_|execute_|ctl_mRead~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~27 .lut_mask = 16'h3B33; +defparam \z80_|execute_|fMRead~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|fMRead~37 ( +// Equation(s): +// \z80_|execute_|fMRead~37_combout = (\z80_|sequencer_|DFFE_M4_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|execute_|ctl_mRead~13_combout ) # (\z80_|execute_|ctl_state_alu~6_combout )))) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|execute_|ctl_mRead~13_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|execute_|ctl_state_alu~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~37 .lut_mask = 16'h0A08; +defparam \z80_|execute_|fMRead~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|fMRead~31 ( +// Equation(s): +// \z80_|execute_|fMRead~31_combout = (\z80_|pla_decode_|Equal33~3_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ixy_d~6_combout )))) # (!\z80_|pla_decode_|Equal33~3_combout & (\z80_|pla_decode_|Equal6~1_combout & +// ((\z80_|execute_|ixy_d~5_combout ) # (\z80_|execute_|ixy_d~6_combout )))) + + .dataa(\z80_|pla_decode_|Equal33~3_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|pla_decode_|Equal6~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~31 .lut_mask = 16'hFCA8; +defparam \z80_|execute_|fMRead~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N14 +cycloneive_lcell_comb \z80_|execute_|fMRead~29 ( +// Equation(s): +// \z80_|execute_|fMRead~29_combout = (\z80_|execute_|ctl_ir_we~5_combout & (\z80_|pla_decode_|Equal33~0_combout & ((\z80_|ir_|opcode [7]) # (\z80_|ir_|opcode [6])))) + + .dataa(\z80_|execute_|ctl_ir_we~5_combout ), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|execute_|fMRead~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~29 .lut_mask = 16'hA080; +defparam \z80_|execute_|fMRead~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|fMRead~30 ( +// Equation(s): +// \z80_|execute_|fMRead~30_combout = (\z80_|execute_|ctl_alu_shift_oe~14_combout & ((\z80_|execute_|ctl_ir_we~9_combout ) # ((\z80_|execute_|fMRead~29_combout ) # (\z80_|execute_|ctl_ir_we~10_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~9_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datac(\z80_|execute_|fMRead~29_combout ), + .datad(\z80_|execute_|ctl_ir_we~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~30 .lut_mask = 16'hCCC8; +defparam \z80_|execute_|fMRead~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|fMRead~28 ( +// Equation(s): +// \z80_|execute_|fMRead~28_combout = ((\z80_|execute_|ixy_d~6_combout & ((\z80_|pla_decode_|Equal41~2_combout ) # (\z80_|pla_decode_|Equal9~1_combout )))) # (!\z80_|execute_|nextM~4_combout ) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|execute_|nextM~4_combout ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~28 .lut_mask = 16'hBBB3; +defparam \z80_|execute_|fMRead~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|fMRead~32 ( +// Equation(s): +// \z80_|execute_|fMRead~32_combout = ((\z80_|execute_|fMRead~31_combout ) # ((\z80_|execute_|fMRead~30_combout ) # (\z80_|execute_|fMRead~28_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ), + .datab(\z80_|execute_|fMRead~31_combout ), + .datac(\z80_|execute_|fMRead~30_combout ), + .datad(\z80_|execute_|fMRead~28_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~32 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|fMRead~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|fMRead~33 ( +// Equation(s): +// \z80_|execute_|fMRead~33_combout = (\z80_|execute_|fMRead~27_combout ) # (((\z80_|execute_|fMRead~37_combout ) # (\z80_|execute_|fMRead~32_combout )) # (!\z80_|execute_|fMRead~6_combout )) + + .dataa(\z80_|execute_|fMRead~27_combout ), + .datab(\z80_|execute_|fMRead~6_combout ), + .datac(\z80_|execute_|fMRead~37_combout ), + .datad(\z80_|execute_|fMRead~32_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~33 .lut_mask = 16'hFFFB; +defparam \z80_|execute_|fMRead~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|fMRead~23 ( +// Equation(s): +// \z80_|execute_|fMRead~23_combout = (\z80_|execute_|ctl_state_alu~3_combout & (((\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|fMRead~5_combout )) # (!\z80_|execute_|fMRead~4_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~3_combout ), + .datab(\z80_|execute_|fMRead~4_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|fMRead~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~23 .lut_mask = 16'hA2AA; +defparam \z80_|execute_|fMRead~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N26 +cycloneive_lcell_comb \z80_|execute_|fMRead~34 ( +// Equation(s): +// \z80_|execute_|fMRead~34_combout = (\z80_|execute_|fMRead~25_combout ) # ((\z80_|execute_|fMRead~22_combout ) # ((\z80_|execute_|fMRead~33_combout ) # (\z80_|execute_|fMRead~23_combout ))) + + .dataa(\z80_|execute_|fMRead~25_combout ), + .datab(\z80_|execute_|fMRead~22_combout ), + .datac(\z80_|execute_|fMRead~33_combout ), + .datad(\z80_|execute_|fMRead~23_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~34 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|fMRead~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y14_N14 +cycloneive_lcell_comb \z80_|execute_|fMRead~35 ( +// Equation(s): +// \z80_|execute_|fMRead~35_combout = ((\z80_|execute_|ctl_ir_we~12_combout ) # ((\z80_|execute_|ctl_mRead~21_combout ) # (!\z80_|execute_|fMRead~7_combout ))) # (!\z80_|execute_|fMWrite~1_combout ) + + .dataa(\z80_|execute_|fMWrite~1_combout ), + .datab(\z80_|execute_|ctl_ir_we~12_combout ), + .datac(\z80_|execute_|fMRead~7_combout ), + .datad(\z80_|execute_|ctl_mRead~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~35 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|fMRead~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~19 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~19_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|pla_decode_|Equal33~3_combout ) # (!\z80_|execute_|ctl_al_we~5_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|pla_decode_|Equal33~3_combout ), + .datad(\z80_|execute_|ctl_al_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~19 .lut_mask = 16'h4044; +defparam \z80_|execute_|ctl_reg_sel_pc~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N16 +cycloneive_lcell_comb \z80_|execute_|fMRead~36 ( +// Equation(s): +// \z80_|execute_|fMRead~36_combout = (\z80_|execute_|fMRead~34_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~19_combout ) # ((!\z80_|execute_|fMRead~2_combout & \z80_|execute_|fMRead~35_combout ))) + + .dataa(\z80_|execute_|fMRead~34_combout ), + .datab(\z80_|execute_|fMRead~2_combout ), + .datac(\z80_|execute_|fMRead~35_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~36 .lut_mask = 16'hFFBA; +defparam \z80_|execute_|fMRead~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N22 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_re ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_re~combout = (\z80_|pin_control_|bus_db_pin_re~2_combout ) # ((\z80_|sequencer_|DFFE_T2_ff~q & \z80_|execute_|fMRead~36_combout )) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(gnd), + .datac(\z80_|execute_|fMRead~36_combout ), + .datad(\z80_|pin_control_|bus_db_pin_re~2_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_re~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_re .lut_mask = 16'hFFA0; +defparam \z80_|pin_control_|bus_db_pin_re .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~118 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][4]~118_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [6]))) # (!\ula_|ps2_keyboard_|shiftreg [2] & +// (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [6]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][4]~118_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][4]~118 .lut_mask = 16'h1008; +defparam \ula_|zx_keyboard_|keys[2][4]~118 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~119 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][4]~119_combout = (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[2][4]~118_combout & \ula_|zx_keyboard_|keys[5][1]~34_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|zx_keyboard_|keys[2][4]~118_combout ), + .datad(\ula_|zx_keyboard_|keys[5][1]~34_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][4]~119_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][4]~119 .lut_mask = 16'h4000; +defparam \ula_|zx_keyboard_|keys[2][4]~119 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~120 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][4]~120_combout = (\ula_|zx_keyboard_|keys[2][4]~119_combout & ((!\ula_|zx_keyboard_|keys[2][4]~94_combout ))) # (!\ula_|zx_keyboard_|keys[2][4]~119_combout & (\ula_|zx_keyboard_|keys[2][4]~q )) + + .dataa(\ula_|zx_keyboard_|keys[2][4]~119_combout ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[2][4]~q ), + .datad(\ula_|zx_keyboard_|keys[2][4]~94_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][4]~120_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][4]~120 .lut_mask = 16'h50FA; +defparam \ula_|zx_keyboard_|keys[2][4]~120 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y9_N1 +dffeas \ula_|zx_keyboard_|keys[2][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[2][4]~120_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[2][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[2][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~129 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][4]~129_combout = (!\ula_|ps2_keyboard_|shiftreg [7] & (\ula_|ps2_keyboard_|scan_code_ready~q & (!\ula_|zx_keyboard_|Equal0~1_combout & \ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [7]), + .datab(\ula_|ps2_keyboard_|scan_code_ready~q ), + .datac(\ula_|zx_keyboard_|Equal0~1_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][4]~129_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][4]~129 .lut_mask = 16'h0400; +defparam \ula_|zx_keyboard_|keys[3][4]~129 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~116 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][4]~116_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [0]))) # (!\ula_|ps2_keyboard_|shiftreg [6] & +// (!\ula_|zx_keyboard_|extended~q & (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [0]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|zx_keyboard_|extended~q ), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][4]~116_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][4]~116 .lut_mask = 16'h0810; +defparam \ula_|zx_keyboard_|keys[3][4]~116 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~134 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][4]~134_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [1] & \ula_|zx_keyboard_|keys[3][4]~116_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|zx_keyboard_|keys[3][4]~116_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][4]~134_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][4]~134 .lut_mask = 16'h4000; +defparam \ula_|zx_keyboard_|keys[3][4]~134 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~117 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][4]~117_combout = (\ula_|zx_keyboard_|keys[3][4]~129_combout & ((\ula_|zx_keyboard_|keys[3][4]~134_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][4]~134_combout & ((\ula_|zx_keyboard_|keys[3][4]~q +// ))))) # (!\ula_|zx_keyboard_|keys[3][4]~129_combout & (((\ula_|zx_keyboard_|keys[3][4]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[3][4]~129_combout ), + .datac(\ula_|zx_keyboard_|keys[3][4]~q ), + .datad(\ula_|zx_keyboard_|keys[3][4]~134_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][4]~117_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][4]~117 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[3][4]~117 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y8_N19 +dffeas \ula_|zx_keyboard_|keys[3][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[3][4]~117_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[3][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[3][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N6 +cycloneive_lcell_comb \D[4]~60 ( +// Equation(s): +// \D[4]~60_combout = (\z80_|address_pins_|abus[11]~19_combout & ((\z80_|address_pins_|abus[10]~24_combout ) # ((!\ula_|zx_keyboard_|keys[2][4]~q )))) # (!\z80_|address_pins_|abus[11]~19_combout & (!\ula_|zx_keyboard_|keys[3][4]~q & +// ((\z80_|address_pins_|abus[10]~24_combout ) # (!\ula_|zx_keyboard_|keys[2][4]~q )))) + + .dataa(\z80_|address_pins_|abus[11]~19_combout ), + .datab(\z80_|address_pins_|abus[10]~24_combout ), + .datac(\ula_|zx_keyboard_|keys[2][4]~q ), + .datad(\ula_|zx_keyboard_|keys[3][4]~q ), + .cin(gnd), + .combout(\D[4]~60_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~60 .lut_mask = 16'h8ACF; +defparam \D[4]~60 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~2 ( +// Equation(s): +// \ula_|zx_keyboard_|Equal0~2_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [3])) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|Equal0~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|Equal0~2 .lut_mask = 16'h000C; +defparam \ula_|zx_keyboard_|Equal0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][4]~121 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][4]~121_combout = (\ula_|zx_keyboard_|keys[1][4]~23_combout & ((\ula_|zx_keyboard_|Equal0~2_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|Equal0~2_combout & ((\ula_|zx_keyboard_|keys[1][4]~q ))))) # +// (!\ula_|zx_keyboard_|keys[1][4]~23_combout & (((\ula_|zx_keyboard_|keys[1][4]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[1][4]~23_combout ), + .datac(\ula_|zx_keyboard_|keys[1][4]~q ), + .datad(\ula_|zx_keyboard_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][4]~121_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][4]~121 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[1][4]~121 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y9_N9 +dffeas \ula_|zx_keyboard_|keys[1][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[1][4]~121_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[1][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[1][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~115 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][4]~115_combout = (\ula_|zx_keyboard_|keys[3][1]~27_combout & ((\ula_|zx_keyboard_|keys[0][4]~96_combout & ((!\ula_|zx_keyboard_|keys[0][4]~109_combout ))) # (!\ula_|zx_keyboard_|keys[0][4]~96_combout & +// (\ula_|zx_keyboard_|keys[0][4]~q )))) # (!\ula_|zx_keyboard_|keys[3][1]~27_combout & (((\ula_|zx_keyboard_|keys[0][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[3][1]~27_combout ), + .datab(\ula_|zx_keyboard_|keys[0][4]~96_combout ), + .datac(\ula_|zx_keyboard_|keys[0][4]~q ), + .datad(\ula_|zx_keyboard_|keys[0][4]~109_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][4]~115_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][4]~115 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[0][4]~115 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y9_N31 +dffeas \ula_|zx_keyboard_|keys[0][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[0][4]~115_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[0][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[0][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~4 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row~4_combout = ((\z80_|address_pins_|DFFE_apin_latch [8]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) # (!\ula_|zx_keyboard_|keys[0][4]~q ) + + .dataa(\ula_|zx_keyboard_|keys[0][4]~q ), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [8]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row~4_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row~4 .lut_mask = 16'hFF5F; +defparam \ula_|zx_keyboard_|key_row~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N22 +cycloneive_lcell_comb \D[4]~61 ( +// Equation(s): +// \D[4]~61_combout = (\D[4]~60_combout & (\ula_|zx_keyboard_|key_row~4_combout & ((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][4]~q )))) + + .dataa(\D[4]~60_combout ), + .datab(\z80_|address_pins_|abus[9]~17_combout ), + .datac(\ula_|zx_keyboard_|keys[1][4]~q ), + .datad(\ula_|zx_keyboard_|key_row~4_combout ), + .cin(gnd), + .combout(\D[4]~61_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~61 .lut_mask = 16'h8A00; +defparam \D[4]~61 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~124 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][4]~124_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|extended~q & !\ula_|ps2_keyboard_|shiftreg [2])) # (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|zx_keyboard_|extended~q & \ula_|ps2_keyboard_|shiftreg +// [2])) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|zx_keyboard_|extended~q ), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][4]~124_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][4]~124 .lut_mask = 16'h03C0; +defparam \ula_|zx_keyboard_|keys[4][4]~124 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~125 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][4]~125_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|zx_keyboard_|keys[4][4]~124_combout & (\ula_|zx_keyboard_|Equal0~2_combout & \ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|zx_keyboard_|keys[4][4]~124_combout ), + .datac(\ula_|zx_keyboard_|Equal0~2_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][4]~125_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][4]~125 .lut_mask = 16'h8000; +defparam \ula_|zx_keyboard_|keys[4][4]~125 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~126 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][4]~126_combout = (\ula_|zx_keyboard_|keys[0][0]~13_combout & ((\ula_|zx_keyboard_|keys[4][4]~125_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[4][4]~125_combout & ((\ula_|zx_keyboard_|keys[4][4]~q +// ))))) # (!\ula_|zx_keyboard_|keys[0][0]~13_combout & (((\ula_|zx_keyboard_|keys[4][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[0][0]~13_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[4][4]~q ), + .datad(\ula_|zx_keyboard_|keys[4][4]~125_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][4]~126_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][4]~126 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[4][4]~126 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y8_N7 +dffeas \ula_|zx_keyboard_|keys[4][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[4][4]~126_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[4][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[4][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~122 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][4]~122_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [2]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][4]~122_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][4]~122 .lut_mask = 16'h2000; +defparam \ula_|zx_keyboard_|keys[5][4]~122 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~123 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][4]~123_combout = (\ula_|zx_keyboard_|keys[6][4]~46_combout & ((\ula_|zx_keyboard_|keys[5][4]~122_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[5][4]~122_combout & (\ula_|zx_keyboard_|keys[5][4]~q +// )))) # (!\ula_|zx_keyboard_|keys[6][4]~46_combout & (((\ula_|zx_keyboard_|keys[5][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[6][4]~46_combout ), + .datab(\ula_|zx_keyboard_|keys[5][4]~122_combout ), + .datac(\ula_|zx_keyboard_|keys[5][4]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][4]~123_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][4]~123 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[5][4]~123 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y8_N1 +dffeas \ula_|zx_keyboard_|keys[5][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[5][4]~123_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[5][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[5][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N8 +cycloneive_lcell_comb \D[4]~62 ( +// Equation(s): +// \D[4]~62_combout = (\ula_|zx_keyboard_|keys[4][4]~q & (\z80_|address_pins_|abus[12]~21_combout & ((\z80_|address_pins_|abus[13]~20_combout ) # (!\ula_|zx_keyboard_|keys[5][4]~q )))) # (!\ula_|zx_keyboard_|keys[4][4]~q & +// ((\z80_|address_pins_|abus[13]~20_combout ) # ((!\ula_|zx_keyboard_|keys[5][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[4][4]~q ), + .datab(\z80_|address_pins_|abus[13]~20_combout ), + .datac(\z80_|address_pins_|abus[12]~21_combout ), + .datad(\ula_|zx_keyboard_|keys[5][4]~q ), + .cin(gnd), + .combout(\D[4]~62_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~62 .lut_mask = 16'hC4F5; +defparam \D[4]~62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~49 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][4]~49_combout = (\ula_|zx_keyboard_|keys[7][1]~21_combout & (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|zx_keyboard_|Equal0~2_combout & !\ula_|ps2_keyboard_|shiftreg [6]))) + + .dataa(\ula_|zx_keyboard_|keys[7][1]~21_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\ula_|zx_keyboard_|Equal0~2_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][4]~49_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][4]~49 .lut_mask = 16'h0080; +defparam \ula_|zx_keyboard_|keys[7][4]~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~3 ( +// Equation(s): +// \ula_|zx_keyboard_|shifted~3_combout = (\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [2]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|shifted~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|shifted~3 .lut_mask = 16'h00F0; +defparam \ula_|zx_keyboard_|shifted~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~127 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][4]~127_combout = (\ula_|zx_keyboard_|keys[7][4]~49_combout & ((\ula_|zx_keyboard_|shifted~3_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|shifted~3_combout & ((\ula_|zx_keyboard_|keys[7][4]~q ))))) # +// (!\ula_|zx_keyboard_|keys[7][4]~49_combout & (((\ula_|zx_keyboard_|keys[7][4]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[7][4]~49_combout ), + .datac(\ula_|zx_keyboard_|keys[7][4]~q ), + .datad(\ula_|zx_keyboard_|shifted~3_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][4]~127_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][4]~127 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[7][4]~127 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y7_N23 +dffeas \ula_|zx_keyboard_|keys[7][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[7][4]~127_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[7][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[7][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~128 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][4]~128_combout = (\ula_|zx_keyboard_|keys[6][4]~46_combout & ((\ula_|zx_keyboard_|keys[6][4]~18_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[6][4]~18_combout & ((\ula_|zx_keyboard_|keys[6][4]~q +// ))))) # (!\ula_|zx_keyboard_|keys[6][4]~46_combout & (((\ula_|zx_keyboard_|keys[6][4]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[6][4]~46_combout ), + .datac(\ula_|zx_keyboard_|keys[6][4]~q ), + .datad(\ula_|zx_keyboard_|keys[6][4]~18_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][4]~128_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][4]~128 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[6][4]~128 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y7_N9 +dffeas \ula_|zx_keyboard_|keys[6][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[6][4]~128_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[6][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[6][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N28 +cycloneive_lcell_comb \D[4]~63 ( +// Equation(s): +// \D[4]~63_combout = (\ula_|zx_keyboard_|keys[7][4]~q & (\z80_|address_pins_|abus[15]~22_combout & ((\z80_|address_pins_|abus[14]~23_combout ) # (!\ula_|zx_keyboard_|keys[6][4]~q )))) # (!\ula_|zx_keyboard_|keys[7][4]~q & +// (((\z80_|address_pins_|abus[14]~23_combout ) # (!\ula_|zx_keyboard_|keys[6][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[7][4]~q ), + .datab(\z80_|address_pins_|abus[15]~22_combout ), + .datac(\ula_|zx_keyboard_|keys[6][4]~q ), + .datad(\z80_|address_pins_|abus[14]~23_combout ), + .cin(gnd), + .combout(\D[4]~63_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~63 .lut_mask = 16'hDD0D; +defparam \D[4]~63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N6 +cycloneive_lcell_comb \D[4]~64 ( +// Equation(s): +// \D[4]~64_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[4]~61_combout & (\D[4]~62_combout & \D[4]~63_combout ))) + + .dataa(\D[4]~61_combout ), + .datab(\D[4]~62_combout ), + .datac(\z80_|address_pins_|abus[0]~16_combout ), + .datad(\D[4]~63_combout ), + .cin(gnd), + .combout(\D[4]~64_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~64 .lut_mask = 16'hF8F0; +defparam \D[4]~64 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y5_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a28 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[4]~76_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a28_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_first_bit_number = 4; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y6_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a20 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[4]~76_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_first_bit_number = 4; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y11_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a12 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[4]~76_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y9_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a4 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[4]~76_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N4 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ) # +// ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout & +// !\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8 .lut_mask = 16'hAAD8; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N14 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout = (\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ) # +// ((!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout & (((\ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout & +// \ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout ), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9 .lut_mask = 16'hACF0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y3_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a12 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'hA50276000854A0103840403E540424244404783E18807A08A47C54484448544A807E7E10005270182040407E4A1252124208084008404208420A4A42424A125A024428106448524A624A4A24425242522060108010543C00044A105424005E0031ED1E0529E507AE2F6FF1CD51D4C772A648E65F6532C28022061303F06C36CDBD319B55CB8E626C20E46C93C1463A0B1CE594F0ED3B62330C104DECE46CA6CD966B1386612C7B43980349408F36FB64C14342DAE26CE4D8D5E791388729D743B09A27AB81D71A14AB3D24E385B602248476D00249239514B58D3098504ACD119B99E9021B650A69494C22600667473128DA5010D2195982823226DED0ADFCB8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h5861917919344A4685CC0990862A11324792E761B6D41C0FCC0838C1C27211A2453FDC2219C225E421B320085A8FBFD0C42135B16448DFC226E09B3438A740C352979565817114DE46462844A57F7958873FC4B255C8AE549BDD1A87415D5018F88D5002628FFD13203066C850F10649F21319109208387641120B362124803F0678522BA2812C1454A502ED1A59CBD76A034756F5765DF7555F57575F7F57FFFF7FFF7D5712524D4A30723514B2B3064A84B4742D48415281863DDFAA9D9B7E7BB16DDB96B7845371C30B55DB96C8F6EB4B453242FF6A4DF84A76B5AEDC88A68DC6A06905054C8C36E4199E74638E6532965218A965909BA456000451343351; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'hE2975A2686A7AE0288F140141B698E2A82A835F478453A1D722CFCED12859FD735188757AC5A42DEB501FE010586249AC1EA60D08F74CFA5086EC78FC9190C056059E332C311521E6522901852D484B423A98816C9B26A08C92368E9FF05524502288A804612A2A0A102A418CBDFBA554499541660F8124640110101263142892A086B442661015380041594608092D9CB919250100A37DDA3919A1427F660963C251301FB2CA45562245308885131119115C652B2493252340201101942D26000CC60799124A8520C08050122171281808058018C38A645D07931896B39ED259A22242CB58413089465B246231330D806105010035100B08761A08506094160; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h1228D91C352915424000000AA0088F63153A8AD81B945C8789F01C86548D12CEAB6AA38578BD55CEC9AA28082C285B8C0201104838AD502AC160C13C70620B818249144AB52CED94200A0202A885100E0D938A30A34512C0CEC98F08A98900F2093E11673256B3169C12284980E92A034141E0782507800F8100009C403C07867000000030082004A17800828F090A0C318CE120012172286317922341A2A12840B6C18040682080125C75401AEC44E8C01A8D40D1412B25A09F7600B0C6FEC65BFE5CE861A20F71E8032916A78F29CC546518461522E4E14998DD54BC0E40B64B710C9DC948F06010DF01D880E2044BE8854062D10DD93F30A62AA7FD227C4C; +// synopsys translate_on + +// Location: M9K_X33_Y27_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a12 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(gnd), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[4]~76_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_first_bit_number = 4; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y24_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a4 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[4]~76_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a4_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_first_bit_number = 4; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFFF0000003E0000003E0000C83F0000D83F0000F03F0000303E0000303E0000003F0010003F0010203F0010F03F0010703F0018303F001C603D800C003CFE26003C7F0F803FFFFFFFFFFFFFFFF; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF00000000000008108000BDF288E9688E000000000000000000000000FFFFFFFF0000000000041D989EA296D29EE969CA000000000000000000000000000000007FFFFFFC8004198A9AA298929EE9498A00000000000000000000000000000000FFFFFFFE800400CA9AA2AADA8AE949CE0000000000000000000000007FFFFFFEC00000028004046A9F22BA5A9EE90FC20000000000000000000000007FFFFFFE8000000280040FEA8002AA7A9EE12742000000000000000000000000000000023FFFFFFC9FE42BA298E2293A80096742000000000000000000000000000000003FFFFFFC9FE4B19298E3181E8009436A; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'h9FE8234A88F836EE9FF8BD4208282BC080DE87C2B84199C2B85E37C2B05B3A829FE8236688F837CE9FF8898208A82A44808A87CAB9C19DC2B80E3AC2927F2AC2800833E288F837C69FE8AB9688882E4283248DC2B9D188C2ABAE2F8291371092800832EA887807C69FE8AB8688080AC283E49D42B914BFC2A3BF1E82910712EA800802EA883807869DE88E8688080AC68BC4BDC2BB1439C2A27F5F82910314E2800886E6880807C69CC89A8681800BC289549CC2AB0C3942A04B7F82953315E2800886EE900805C61C089FC081E415C289D89DC2AB4E3142A1233D8217330090800086EE900805821C08BEC080D407C289C89DC2AADE3142A13B7F82176300F0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h076B0A5083288F028370C182A801468297E5AC1288D308023FFFFFFC00000000072BA9608BA08D028BF4D182AC015682937CA80288D308023FFFFFFC00000002872B892A8FA08F028A14509AAC0166B2B37DA80288D10D02800000027FFFFFFE852BAD128E388D028A004082AC0166C2937DA00288D10F02C00000027FFFFFFE846289368968C90289E0528A8C016CA29379B20280510F02FFFFFFFE0000000085E2A922816089828BE0428286416C829179B00280511F027FFFFFFC0000000087EA8B32872089828800569287436CA28179B20200513F0000000000FFFFFFFF8768A3028610858288004682874364828019900200403E0000000000FFFFFFFF; +// synopsys translate_on + +// Location: M9K_X33_Y4_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a4 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h35861A00A6112A1481AF1A50A6004A05291627227FF08229B87389E08119A28A7888672DC999B7046A61E60810A7434450E3D33E330F321A18E8A120D1EDC8623DA2C64840C2CCE811522B42008095E5A456C98F4B25EAEA410610545024640CF10410AC463BF9349074917E9A74A12830EFA280EBD3131E484A255D0191C6852730A263DBCCAAA88712242B3BE49AA5338990229B391158C726BC7EB4ECC32308980020680249882691A680488292310B4313CE87FFCD5329A64B708CAC8533316412C4900F646A36630261DA093053D98F19D2C5B653165D4A71AA5682B29B89B6054CC727D292805705A93268676A31111371390B240EC3CC85D331813EB1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h1AA1C248D293110CB951445117D9B6AA500F65068B8CC508BD00184F8705B010A0CC46CC9302649242CE08191634113154562B149100204551178DE805D98EC8A2E5A64B241400267194CD524499BC01D31058CD18684A817A5800B65143281C1310B00A49902C0104004C654E0582040001103654011012021912281216B000C653A0510A1B00C36AC88058CAC126E14E198DFB07E81C3F41510BB08F8F851C3B9AF0147BC1F730B4E91D9D11C3A8F1B82DF19988ACC44072FDB17B4D81882E9DD952B29003D7767BA581A68BC41C2B16AD6EB57F1D048CD4E464190D25ADF2C194E3598360AFB031A1690F4625BB628363B4C90A400E3A04DAA70DA0CC4776; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'hC82B30671933680037A65978674DDEC2D30EEEDA78F5F2A1DEE660FFEA11B175DCB42E9277212A58842051A078007109A0D820166B881042600284403143048295D23A0E191EBC2134B833D53D37E42B05018289A10300A188E315CE98640F548A370D60A0AA3E7288A0B0869FA5E703D1AE17C0EC276B2AFB747B550A8B41021620D1A60A901095D12A0973B95E20838001330138951361967847D42901910A3488480610A91A851E84FF08783F81AEA52D2FDC2200BD2FE81C0357FBEC1D875686C6CA41B2224C88D8456C1DBF20D820A6649774CB11B69933246E9739C998470542C2E3C783A4C24767084C52DC209D60E95DBC096D9A0171A12D5AB99BAB; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h17A24D2C636ED2478B5AE1C99D40761B1E7AA6A89DDD1BBD8DBD223E70531BCDE90C8E38C8E0478AD8B388F94891C9673A50BC32478E083074657E8E0EA53BEE861F8BC1993560946D92D1C0C7F046A245B5849CB751FF15B97FCD50BC7B8524C13E7C640F3645082248D1CC14296E30DEA3057B35C641762CD00D40DABC27472251A60725008AAA056591C4000BB48C0BC29B8034A03400027B84769B520D9196968460CA3388A03ECB45F2C4B70F1829221000FFFC7FEC346F079F13079798EC2A08157331C6CC0E30884244916A0DE26D4D22454091290404A492016887E2111F830F9851184101370588A06D3BF9AE621A5F4E632A6799C83EFAAE06769D; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N24 +cycloneive_lcell_comb \Selector4~0 ( +// Equation(s): +// \Selector4~0_combout = (\z80_|address_pins_|abus[14]~23_combout & ((\Selector3~0_combout ) # ((\ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout )))) # (!\z80_|address_pins_|abus[14]~23_combout & (!\Selector3~0_combout & +// ((\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout )))) + + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\Selector3~0_combout ), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ), + .cin(gnd), + .combout(\Selector4~0_combout ), + .cout()); +// synopsys translate_off +defparam \Selector4~0 .lut_mask = 16'hB9A8; +defparam \Selector4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N14 +cycloneive_lcell_comb \Selector4~1 ( +// Equation(s): +// \Selector4~1_combout = (\Selector3~0_combout & ((\Selector4~0_combout & ((\ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ))) # (!\Selector4~0_combout & (\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout )))) # +// (!\Selector3~0_combout & (((\Selector4~0_combout )))) + + .dataa(\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ), + .datab(\Selector3~0_combout ), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ), + .datad(\Selector4~0_combout ), + .cin(gnd), + .combout(\Selector4~1_combout ), + .cout()); +// synopsys translate_off +defparam \Selector4~1 .lut_mask = 16'hF388; +defparam \Selector4~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N10 +cycloneive_lcell_comb \D[4]~86 ( +// Equation(s): +// \D[4]~86_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [15] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\Selector4~1_combout +// ))))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout )))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|address_pins_|DFFE_apin_latch [15]), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout ), + .datad(\Selector4~1_combout ), + .cin(gnd), + .combout(\D[4]~86_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~86 .lut_mask = 16'hF2D0; +defparam \D[4]~86 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N16 +cycloneive_lcell_comb \D[4]~75 ( +// Equation(s): +// \D[4]~75_combout = ((\Equal2~0_combout & (\D[4]~64_combout )) # (!\Equal2~0_combout & ((\D[4]~86_combout )))) # (!\Equal2~1_combout ) + + .dataa(\Equal2~1_combout ), + .datab(\D[4]~64_combout ), + .datac(\Equal2~0_combout ), + .datad(\D[4]~86_combout ), + .cin(gnd), + .combout(\D[4]~75_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~75 .lut_mask = 16'hDFD5; +defparam \D[4]~75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N30 +cycloneive_lcell_comb \D[4]~76 ( +// Equation(s): +// \D[4]~76_combout = (\z80_|pin_control_|bus_db_pin_oe~15_combout & (((\z80_|data_pins_|dout [4] & \D[4]~75_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout & (((\D[4]~75_combout )) # (!\Equal2~1_combout ))) + + .dataa(\Equal2~1_combout ), + .datab(\z80_|data_pins_|dout [4]), + .datac(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .datad(\D[4]~75_combout ), + .cin(gnd), + .combout(\D[4]~76_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~76 .lut_mask = 16'hCF05; +defparam \D[4]~76 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N30 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[4] ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [4] = (\z80_|bus_control_|db[4]~19_combout & ((\z80_|execute_|ctl_bus_db_we~7_combout ) # ((\z80_|pin_control_|bus_db_pin_re~combout & \D[4]~76_combout )))) # (!\z80_|bus_control_|db[4]~19_combout & +// (\z80_|pin_control_|bus_db_pin_re~combout & ((\D[4]~76_combout )))) + + .dataa(\z80_|bus_control_|db[4]~19_combout ), + .datab(\z80_|pin_control_|bus_db_pin_re~combout ), + .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datad(\D[4]~76_combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [4]), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[4] .lut_mask = 16'hECA0; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[4] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y13_N31 +dffeas \z80_|data_pins_|dout[4] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [4]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|data_pins_|dout [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|data_pins_|dout[4] .is_wysiwyg = "true"; +defparam \z80_|data_pins_|dout[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N24 +cycloneive_lcell_comb \z80_|bus_control_|db[4]~18 ( +// Equation(s): +// \z80_|bus_control_|db[4]~18_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [4]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) + + .dataa(\z80_|bus_control_|db[0]~4_combout ), + .datab(\z80_|data_pins_|dout [4]), + .datac(gnd), + .datad(\z80_|execute_|ctl_bus_db_oe~combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[4]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[4]~18 .lut_mask = 16'h88AA; +defparam \z80_|bus_control_|db[4]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N0 +cycloneive_lcell_comb \z80_|bus_control_|db[4]~19 ( +// Equation(s): +// \z80_|bus_control_|db[4]~19_combout = ((\z80_|bus_control_|db[4]~18_combout & ((\z80_|alu_control_|db[4]~32_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) + + .dataa(\z80_|bus_control_|db[0]~6_combout ), + .datab(\z80_|bus_control_|db[4]~18_combout ), + .datac(\z80_|alu_control_|db[4]~32_combout ), + .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[4]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[4]~19 .lut_mask = 16'hD5DD; +defparam \z80_|bus_control_|db[4]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y17_N1 +dffeas \z80_|ir_|opcode[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|bus_control_|db[4]~19_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|ir_|opcode [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|ir_|opcode[4] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y17_N18 +cycloneive_lcell_comb \z80_|pla_decode_|Equal32~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal32~0_combout = (!\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3]) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [4]), + .datac(gnd), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal32~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal32~0 .lut_mask = 16'h3300; +defparam \z80_|pla_decode_|Equal32~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N18 +cycloneive_lcell_comb \z80_|pla_decode_|Equal41~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal41~1_combout = (\z80_|ir_|opcode [7] & (\z80_|ir_|opcode [6] & ((\z80_|decode_state_|DFFE_instIY1~q ) # (\z80_|decode_state_|DFFE_inst4~q )))) + + .dataa(\z80_|decode_state_|DFFE_instIY1~q ), + .datab(\z80_|decode_state_|DFFE_inst4~q ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal41~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal41~1 .lut_mask = 16'hE000; +defparam \z80_|pla_decode_|Equal41~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal41~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal41~2_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal32~0_combout & (\z80_|pla_decode_|Equal41~1_combout & \z80_|pla_decode_|Equal8~0_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal32~0_combout ), + .datac(\z80_|pla_decode_|Equal41~1_combout ), + .datad(\z80_|pla_decode_|Equal8~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal41~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal41~2 .lut_mask = 16'h4000; +defparam \z80_|pla_decode_|Equal41~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal36~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal36~0_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal1~7_combout & \z80_|pla_decode_|Equal32~0_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal2~0_combout ), + .datac(\z80_|pla_decode_|Equal1~7_combout ), + .datad(\z80_|pla_decode_|Equal32~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal36~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal36~0 .lut_mask = 16'h4000; +defparam \z80_|pla_decode_|Equal36~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_cb_set ( +// Equation(s): +// \z80_|execute_|ctl_state_tbl_cb_set~combout = (\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|pla_decode_|Equal41~2_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & +// ((\z80_|pla_decode_|Equal36~0_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & \z80_|pla_decode_|Equal41~2_combout )))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(\z80_|pla_decode_|Equal36~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_tbl_cb_set~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_tbl_cb_set .lut_mask = 16'hD5C0; +defparam \z80_|execute_|ctl_state_tbl_cb_set .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_state_tbl_we~8_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # ((\z80_|sequencer_|DFFE_T3_ff~q & \z80_|pla_decode_|Equal41~2_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_tbl_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_tbl_we~8 .lut_mask = 16'h00EC; +defparam \z80_|execute_|ctl_state_tbl_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y13_N9 +dffeas \z80_|decode_state_|DFFE_instCB ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|execute_|ctl_state_tbl_cb_set~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_state_tbl_we~8_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|decode_state_|DFFE_instCB~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instCB .is_wysiwyg = "true"; +defparam \z80_|decode_state_|DFFE_instCB .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal52~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal52~0_combout = (!\z80_|decode_state_|DFFE_instCB~q & (!\z80_|decode_state_|DFFE_instED~q & (\z80_|ir_|opcode [7] & \z80_|ir_|opcode [6]))) + + .dataa(\z80_|decode_state_|DFFE_instCB~q ), + .datab(\z80_|decode_state_|DFFE_instED~q ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal52~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal52~0 .lut_mask = 16'h1000; +defparam \z80_|pla_decode_|Equal52~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal2~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal2~1_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal32~0_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal52~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal32~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal2~1 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_ed_set ( +// Equation(s): +// \z80_|execute_|ctl_state_tbl_ed_set~combout = (\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal2~1_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & !\z80_|ir_|opcode [1]))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|pla_decode_|Equal2~1_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_tbl_ed_set~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_tbl_ed_set .lut_mask = 16'h0008; +defparam \z80_|execute_|ctl_state_tbl_ed_set .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y13_N13 +dffeas \z80_|decode_state_|DFFE_instED ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|execute_|ctl_state_tbl_ed_set~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_state_tbl_we~8_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|decode_state_|DFFE_instED~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instED .is_wysiwyg = "true"; +defparam \z80_|decode_state_|DFFE_instED .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N26 +cycloneive_lcell_comb \z80_|decode_state_|table_xx~0 ( +// Equation(s): +// \z80_|decode_state_|table_xx~0_combout = (\z80_|decode_state_|DFFE_instED~q ) # (\z80_|decode_state_|DFFE_instCB~q ) + + .dataa(\z80_|decode_state_|DFFE_instED~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|decode_state_|DFFE_instCB~q ), + .cin(gnd), + .combout(\z80_|decode_state_|table_xx~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|table_xx~0 .lut_mask = 16'hFFAA; +defparam \z80_|decode_state_|table_xx~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N24 +cycloneive_lcell_comb \z80_|pla_decode_|Equal34~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal34~0_combout = (!\z80_|ir_|opcode [0] & (!\z80_|decode_state_|table_xx~0_combout & (\z80_|pla_decode_|Equal3~1_combout & \z80_|pla_decode_|Equal41~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|decode_state_|table_xx~0_combout ), + .datac(\z80_|pla_decode_|Equal3~1_combout ), + .datad(\z80_|pla_decode_|Equal41~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal34~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal34~0 .lut_mask = 16'h1000; +defparam \z80_|pla_decode_|Equal34~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~6_combout = (\z80_|execute_|ctl_alu_op_low~22_combout & (!\z80_|execute_|ixy_d~16_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|pla_decode_|Equal34~0_combout )))) # (!\z80_|execute_|ctl_alu_op_low~22_combout & +// (((!\z80_|execute_|ixy_d~5_combout )) # (!\z80_|pla_decode_|Equal34~0_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datab(\z80_|pla_decode_|Equal34~0_combout ), + .datac(\z80_|execute_|ixy_d~16_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~6 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_reg_sel_pc~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~5_combout = ((!\z80_|execute_|ctl_mRead~6_combout & (!\z80_|execute_|ctl_mRead~7_combout & !\z80_|execute_|ctl_mRead~15_combout ))) # (!\z80_|execute_|ixy_d~5_combout ) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_mRead~6_combout ), + .datac(\z80_|execute_|ctl_mRead~7_combout ), + .datad(\z80_|execute_|ctl_mRead~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~5 .lut_mask = 16'h5557; +defparam \z80_|execute_|ctl_reg_sel_pc~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~4_combout = ((!\z80_|execute_|ixy_d~10_combout & ((!\z80_|pla_decode_|Equal24~0_combout ) # (!\z80_|pla_decode_|Equal21~0_combout )))) # (!\z80_|execute_|ctl_alu_op_low~22_combout ) + + .dataa(\z80_|execute_|ixy_d~10_combout ), + .datab(\z80_|pla_decode_|Equal21~0_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datad(\z80_|pla_decode_|Equal24~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~4 .lut_mask = 16'h1F5F; +defparam \z80_|execute_|ctl_reg_sel_pc~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~2_combout = ((!\z80_|execute_|ctl_mRead~13_combout & ((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout )))) # (!\z80_|execute_|ixy_d~5_combout ) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_mRead~13_combout ), + .datac(\z80_|pla_decode_|Equal12~1_combout ), + .datad(\z80_|pla_decode_|Equal25~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~2 .lut_mask = 16'h7577; +defparam \z80_|execute_|ctl_reg_sel_pc~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~3_combout = (\z80_|execute_|ctl_reg_sel_pc~2_combout & (((!\z80_|pla_decode_|Equal19~0_combout & !\z80_|execute_|ctl_mRead~8_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) + + .dataa(\z80_|pla_decode_|Equal19~0_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~2_combout ), + .datac(\z80_|execute_|ctl_mRead~8_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~3 .lut_mask = 16'h04CC; +defparam \z80_|execute_|ctl_reg_sel_pc~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~7_combout = (\z80_|execute_|ctl_reg_sel_pc~6_combout & (\z80_|execute_|ctl_reg_sel_pc~5_combout & (\z80_|execute_|ctl_reg_sel_pc~4_combout & \z80_|execute_|ctl_reg_sel_pc~3_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~6_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~5_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~4_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~7 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sel_pc~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~8_combout = (\z80_|pla_decode_|Equal12~1_combout & (((\z80_|pla_decode_|Equal3~0_combout & \z80_|pla_decode_|Equal24~0_combout )))) # (!\z80_|pla_decode_|Equal12~1_combout & ((\z80_|pla_decode_|Equal25~0_combout ) # +// ((\z80_|pla_decode_|Equal3~0_combout & \z80_|pla_decode_|Equal24~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal12~1_combout ), + .datab(\z80_|pla_decode_|Equal25~0_combout ), + .datac(\z80_|pla_decode_|Equal3~0_combout ), + .datad(\z80_|pla_decode_|Equal24~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~8 .lut_mask = 16'hF444; +defparam \z80_|execute_|ctl_reg_sel_pc~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~9_combout = (\z80_|execute_|ctl_alu_op_low~22_combout & ((\z80_|execute_|ctl_mRead~15_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~8_combout ) # (\z80_|pla_decode_|Equal34~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datab(\z80_|execute_|ctl_mRead~15_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~8_combout ), + .datad(\z80_|pla_decode_|Equal34~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~9 .lut_mask = 16'hAAA8; +defparam \z80_|execute_|ctl_reg_sel_pc~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~10 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~10_combout = (\z80_|execute_|ctl_reg_sel_pc~7_combout & (!\z80_|execute_|ctl_reg_sel_pc~9_combout & ((!\z80_|pla_decode_|Equal41~2_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~7_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~9_combout ), + .datad(\z80_|pla_decode_|Equal41~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~10 .lut_mask = 16'h040C; +defparam \z80_|execute_|ctl_reg_sel_pc~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~16 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~16_combout = (((\z80_|execute_|ctl_state_alu~3_combout & !\z80_|execute_|fMRead~4_combout )) # (!\z80_|execute_|ctl_apin_mux~0_combout )) # (!\z80_|execute_|ctl_reg_sel_pc~10_combout ) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~10_combout ), + .datab(\z80_|execute_|ctl_apin_mux~0_combout ), + .datac(\z80_|execute_|ctl_state_alu~3_combout ), + .datad(\z80_|execute_|fMRead~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~16 .lut_mask = 16'h77F7; +defparam \z80_|execute_|ctl_reg_sel_pc~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~17 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~17_combout = (\z80_|nM1_int~2_combout ) # ((\z80_|execute_|ctl_reg_sys_we~0_combout ) # ((!\z80_|execute_|ctl_sw_4u~1_combout ) # (!\z80_|execute_|ctl_inc_dec~12_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_reg_sys_we~0_combout ), + .datac(\z80_|execute_|ctl_inc_dec~12_combout ), + .datad(\z80_|execute_|ctl_sw_4u~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~17 .lut_mask = 16'hEFFF; +defparam \z80_|execute_|ctl_reg_sel_pc~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~15 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~15_combout = (\z80_|execute_|ctl_reg_sel_pc~19_combout ) # ((!\z80_|execute_|fMRead~2_combout & ((!\z80_|execute_|ctl_reg_sel_pc~14_combout ) # (!\z80_|execute_|setM1~38_combout )))) + + .dataa(\z80_|execute_|setM1~38_combout ), + .datab(\z80_|execute_|fMRead~2_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~14_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~15 .lut_mask = 16'hFF13; +defparam \z80_|execute_|ctl_reg_sel_pc~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~18 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~18_combout = (\z80_|execute_|ctl_reg_sel_pc~16_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~17_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~15_combout ) # (!\z80_|execute_|ctl_reg_sel_pc~13_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~16_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~17_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~13_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~18 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|ctl_reg_sel_pc~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~19 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~19_combout = (((!\z80_|pla_decode_|Equal19~0_combout & !\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|sequencer_|M5~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|pla_decode_|Equal19~0_combout ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|pla_decode_|Equal34~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~19 .lut_mask = 16'h5F7F; +defparam \z80_|execute_|ctl_reg_sel_wz~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N20 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~3 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_pc~3_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout & (\z80_|execute_|ctl_reg_sel_wz~19_combout & (\z80_|reg_control_|reg_sel_pc~2_combout & \z80_|execute_|ctl_alu_sel_op2_neg~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~19_combout ), + .datac(\z80_|reg_control_|reg_sel_pc~2_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_pc~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_pc~3 .lut_mask = 16'h4000; +defparam \z80_|reg_control_|reg_sel_pc~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N24 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc ( +// Equation(s): +// \z80_|reg_control_|reg_sel_pc~combout = (\z80_|execute_|ctl_reg_sel_pc~18_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & (!\z80_|execute_|ctl_reg_sel_wz~20_combout & \z80_|reg_control_|reg_sel_pc~3_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~18_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~20_combout ), + .datad(\z80_|reg_control_|reg_sel_pc~3_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_pc~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_pc .lut_mask = 16'h0200; +defparam \z80_|reg_control_|reg_sel_pc .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N24 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_72 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_72~combout = (\z80_|reg_control_|reg_sel_pc~combout & (!\z80_|reg_control_|reg_sys_we_hi~combout & \z80_|execute_|ctl_reg_sys_hilo[1]~35_combout )) + + .dataa(\z80_|reg_control_|reg_sel_pc~combout ), + .datab(gnd), + .datac(\z80_|reg_control_|reg_sys_we_hi~combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_72 .lut_mask = 16'h0A00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_72 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N10 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~2 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[0]~2_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ) # ((\z80_|reg_control_|reg_sw_4d_hi~0_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~43_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[0]~2 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|db_hi_as[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y14_N23 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[5]~15_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y14_N17 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[5]~15_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N16 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~13 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[5]~13_combout = (\z80_|reg_file_|gdfx_temp1[5]~57_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # (!\z80_|reg_file_|gdfx_temp1[5]~57_combout & +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[5]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[5]~13 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|db_hi_as[5]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N28 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~14 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[5]~14_combout = (\z80_|reg_file_|db_hi_as[5]~13_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datab(\z80_|reg_file_|b2v_latch_pc_hi|latch [5]), + .datac(gnd), + .datad(\z80_|reg_file_|db_hi_as[5]~13_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[5]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[5]~14 .lut_mask = 16'hDD00; +defparam \z80_|reg_file_|db_hi_as[5]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N22 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~15 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[5]~15_combout = ((\z80_|reg_file_|db_hi_as[5]~14_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .datad(\z80_|reg_file_|db_hi_as[5]~14_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[5]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[5]~15 .lut_mask = 16'hDF55; +defparam \z80_|reg_file_|db_hi_as[5]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y14_N9 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X37_Y14_N23 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~50 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~50_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (\z80_|reg_file_|b2v_latch_hl_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_hl2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (((\z80_|reg_file_|b2v_latch_hl2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [5]), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~50_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~50 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[5]~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y16_N13 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~53 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~53_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout & (\z80_|alu_|db[5]~24_combout & ((\z80_|reg_file_|b2v_latch_af2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # +// (!\z80_|execute_|ctl_reg_in_hi~12_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .datab(\z80_|alu_|db[5]~24_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~53_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~53 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[5]~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y15_N19 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X35_Y15_N17 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~54 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~54_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (\z80_|reg_file_|b2v_latch_wz_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [5]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [5]), + .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~54_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~54 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp1[5]~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y16_N3 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y16_N21 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~52 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~52_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [5]), + .datad(\z80_|reg_file_|b2v_latch_iy_hi|latch [5]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~52_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~52 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[5]~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y16_N5 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X37_Y16_N19 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~51 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~51_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (\z80_|reg_file_|b2v_latch_bc2_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [5]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_bc_hi|latch [5]), + .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~51_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~51 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp1[5]~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~55 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~55_combout = (\z80_|reg_file_|gdfx_temp1[5]~53_combout & (\z80_|reg_file_|gdfx_temp1[5]~54_combout & (\z80_|reg_file_|gdfx_temp1[5]~52_combout & \z80_|reg_file_|gdfx_temp1[5]~51_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[5]~53_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[5]~54_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[5]~52_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[5]~51_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~55_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~55 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[5]~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y15_N27 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N26 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[5]~14 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[5]~14_combout = (\z80_|execute_|ctl_reg_gp_we~8_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [5]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [5]), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[5]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[5]~14 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[5]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y15_N15 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N28 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_hi|latch[5]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_de_hi|latch[5]~feeder_combout = \z80_|reg_file_|gdfx_temp1[5]~57_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_de_hi|latch[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[5]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y15_N29 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_de_hi|latch[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~49 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~49_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [5]), + .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [5]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~49_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~49 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[5]~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y15_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~56 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~56_combout = (\z80_|reg_file_|gdfx_temp1[5]~50_combout & (\z80_|reg_file_|gdfx_temp1[5]~55_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[5]~14_combout & \z80_|reg_file_|gdfx_temp1[5]~49_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[5]~50_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[5]~55_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|db[5]~14_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[5]~49_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~56_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~56 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[5]~56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~57 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~57_combout = ((\z80_|reg_file_|gdfx_temp1[5]~56_combout & ((\z80_|reg_file_|db_hi_as[5]~15_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[5]~15_combout ), + .datab(\z80_|execute_|ctl_sw_4u~6_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[5]~56_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~57 .lut_mask = 16'hBF0F; +defparam \z80_|reg_file_|gdfx_temp1[5]~57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N14 +cycloneive_lcell_comb \z80_|alu_|db[5]~23 ( +// Equation(s): +// \z80_|alu_|db[5]~23_combout = (\z80_|alu_control_|db[5]~15_combout & ((\z80_|reg_file_|gdfx_temp1[5]~57_combout ) # ((!\z80_|execute_|ctl_reg_out_hi~7_combout )))) # (!\z80_|alu_control_|db[5]~15_combout & (!\z80_|execute_|ctl_sw_2d~13_combout & +// ((\z80_|reg_file_|gdfx_temp1[5]~57_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) + + .dataa(\z80_|alu_control_|db[5]~15_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .datac(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .datad(\z80_|execute_|ctl_sw_2d~13_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[5]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[5]~23 .lut_mask = 16'h8ACF; +defparam \z80_|alu_|db[5]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N14 +cycloneive_lcell_comb \z80_|alu_|db[5]~24 ( +// Equation(s): +// \z80_|alu_|db[5]~24_combout = ((\z80_|alu_|db[5]~23_combout & ((\z80_|alu_|db_high[1]~19_combout ) # (!\z80_|execute_|ctl_alu_oe~11_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|alu_|db[5]~23_combout ), + .datab(\z80_|alu_|db_high[1]~19_combout ), + .datac(\z80_|alu_|db[7]~9_combout ), + .datad(\z80_|execute_|ctl_alu_oe~11_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[5]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[5]~24 .lut_mask = 16'h8FAF; +defparam \z80_|alu_|db[5]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N26 +cycloneive_lcell_comb \z80_|sw1_|db_down[5]~0 ( +// Equation(s): +// \z80_|sw1_|db_down[5]~0_combout = (\z80_|bus_control_|db[5]~15_combout ) # ((\z80_|execute_|ctl_sw_1d~6_combout & ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|execute_|ctl_66_oe~2_combout )))) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|execute_|ctl_sw_1d~6_combout ), + .datac(\z80_|bus_control_|db[5]~15_combout ), + .datad(\z80_|execute_|ctl_66_oe~2_combout ), + .cin(gnd), + .combout(\z80_|sw1_|db_down[5]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sw1_|db_down[5]~0 .lut_mask = 16'hF8FC; +defparam \z80_|sw1_|db_down[5]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N22 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_36 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout = (\z80_|execute_|ctl_flags_bus~combout & ((\z80_|alu_control_|db[5]~15_combout ) # ((\z80_|alu_|db_high[1]~19_combout & \z80_|execute_|ctl_flags_alu~15_combout )))) # (!\z80_|execute_|ctl_flags_bus~combout +// & (\z80_|alu_|db_high[1]~19_combout & (\z80_|execute_|ctl_flags_alu~15_combout ))) + + .dataa(\z80_|execute_|ctl_flags_bus~combout ), + .datab(\z80_|alu_|db_high[1]~19_combout ), + .datac(\z80_|execute_|ctl_flags_alu~15_combout ), + .datad(\z80_|alu_control_|db[5]~15_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_36 .lut_mask = 16'hEAC0; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y15_N23 +dffeas \z80_|alu_flags_|flags_yf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_flags_xy_we~18_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|flags_yf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|flags_yf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|flags_yf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N26 +cycloneive_lcell_comb \z80_|alu_control_|db[5]~13 ( +// Equation(s): +// \z80_|alu_control_|db[5]~13_combout = (\z80_|execute_|ctl_flags_oe~2_combout & (\z80_|alu_flags_|flags_yf~q & ((\z80_|alu_control_|out[6]~2_combout ) # (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout )))) # (!\z80_|execute_|ctl_flags_oe~2_combout & +// ((\z80_|alu_control_|out[6]~2_combout ) # ((\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout )))) + + .dataa(\z80_|execute_|ctl_flags_oe~2_combout ), + .datab(\z80_|alu_control_|out[6]~2_combout ), + .datac(\z80_|alu_flags_|flags_yf~q ), + .datad(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[5]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[5]~13 .lut_mask = 16'hF5C4; +defparam \z80_|alu_control_|db[5]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N8 +cycloneive_lcell_comb \z80_|alu_control_|db[5]~14 ( +// Equation(s): +// \z80_|alu_control_|db[5]~14_combout = (\z80_|sw1_|db_down[5]~0_combout & (\z80_|alu_control_|db[5]~13_combout & ((\z80_|reg_file_|gdfx_temp0[5]~72_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) + + .dataa(\z80_|sw1_|db_down[5]~0_combout ), + .datab(\z80_|alu_control_|db[5]~13_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[5]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[5]~14 .lut_mask = 16'h8088; +defparam \z80_|alu_control_|db[5]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N14 +cycloneive_lcell_comb \z80_|alu_control_|db[5]~15 ( +// Equation(s): +// \z80_|alu_control_|db[5]~15_combout = ((\z80_|alu_control_|db[5]~14_combout & ((\z80_|alu_|db[5]~24_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) + + .dataa(\z80_|alu_|db[5]~24_combout ), + .datab(\z80_|execute_|ctl_sw_2u~7_combout ), + .datac(\z80_|alu_control_|db[5]~14_combout ), + .datad(\z80_|alu_control_|db[6]~11_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[5]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[5]~15 .lut_mask = 16'hB0FF; +defparam \z80_|alu_control_|db[5]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y17_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a29 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[5]~77_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_first_bit_number = 5; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y15_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a13 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[5]~77_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_bit_number = 5; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y19_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a21 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[5]~77_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_first_bit_number = 5; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y22_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a5 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[5]~77_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_bit_number = 5; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N28 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ) # +// ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout & +// !\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10 .lut_mask = 16'hCCB8; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N18 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout & +// (\ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout )) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ))))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11 .lut_mask = 16'hAFC0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y31_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a13 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_bit_number = 5; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init3 = 2048'h990442000864A0284030400454782424440404007E404808A4005448387E547C8004420800620824402040024A1242124204044008404208420A4A42424A1242020028008000524A024A4A284252446240001000101042000054265C7E0600007FAF5CA001C181BE0C02418447B1D88BAA85409896BC7C0E5FAC2529CB69A4038E2564731F88FE730045956C357C5ECF7EF8591DF2A8ACFFBFEEF268CD9B51238594AF691A9B8640983B7F76AAB97209EA6257389992FFE684926E0B19FA338B8489D73811171D5C9FF3DCFFFFFF8002000780101F3F4035A0CDED99F79A4775854F179F7D7DBBCF81B2F6421FF684CA6AF85894D29B9D3ACCBA3F27D9DC9911; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init2 = 2048'h5B438D714D4E3DD115E8BD1286EAB5FA1D71BD8F4508BD4BDC8838F9D27B552259BCEFFBB68A6FF529B3B0D92970010BBB6C7D872421210E190E1CCC47A485EAD2F8735647315839EF6F683C64773FC73464D5FE354936D50823A5DAEBEBDBCC6CAFF2622B8D518F63C6030424188FD357718970D25A30CD0731E532DB23002D02C12B12378356DE2C52041CA7A320C51E0D7CA9F5D575775D57FD75DDFDF75FFFDFFFD75F145247F03A0AE7F1E1EB2D5A99D2444108C6A5979B7CC26ABCC241EA4C912568003BB493CE04FF086C188980052BF6ABAAA2FD5D658000011277EB924C10EFAF3CB9B62486512344C61ADE6F15AB67F335A52513FF05AFAEEE8400; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 2048'h0C840083AD485153ACD3C035591630199B8C096CE4DC557D6D55FCCD738573D6E0948817C496E9DE8EA1F88F627B7460106691CC452DB9799E59A5D003733C4EA1BCE33AD2D8BE40A4E5BB7D7BBEC2CEADBBC8B6F87A4A56FBE0B891DE57E4C64EF9AD87727C49CFE7C5DE942B72AC7F6D97DE18920777FDDEE9EB11122A4E18F5569FDE08906765428FB9E6F89FBF0DEAA6064637BCA63FD02E273E5557F0548662C97BC2E8D3FFDB26D23E87BFD97E635A6560CFD93F8EED26E30C70DE8633D6B97C86DF7D9BEDFB99E36B6658F16C6DEFBDD5DF728D6209C852C37FE67CFF32EE4CCCECC64F7E6225FC99EC64C3B6DD7DED0FD7CCEA3BF09A006ECDD1009E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'hA9C9CE3AECF7BE27C000000A8ABA95251B309A60B9DDC19EC3E391458CBB53CA00A85E3C5AAE2C49DDC2F6C7B013DACB319A769818A1081A7389F711D76A09BCBED23D9A99FF9B77183697955D76BF0E0008822742DA45B883C9193DAF09424501859565800698515E10A8189EE9B323E35CE7388D73C6E7A50D0DE6739C73AC538D134115D860ADA57B5B868E54393B1E31E762062577697D57E8464340420E9434CCA34CC9A1CB1FAACC56168071EAC113F5265D5F6A45A098D604A820508C4EA47F9A7E46083716911B0D585CE937B530218E8D2AD3777EE7D3B4BC56C29ADB46809D15D185F8809229B150C29C8081174CA6173B99703DA466629005C604; +// synopsys translate_on + +// Location: M9K_X33_Y1_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a5 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_bit_number = 5; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init3 = 2048'hE10F8B8C100323720BEBBDEBB81DF13FF97B252E2CB4F27BA091FBD0002D1A611E1EDBBC716D44D2912B80041C44558060CFCF15955C0D780DD5E71393920844F25E16C87C5D0308EEC52C011514BBC13AFA1028924D0C7CE738105BD47A10AA5B5C1D9D4193E4339F492B0E1A64E13AE35BE6B67AC8057BDACC155F14E906A017A1841358335450D4B26CD2A21B3D8F2211080B81EC040D7FA0B51CD48008112508062020A02490900092D2040259108806A328F4006D2AA514B42FB006ECCCCB9A360865678449975A8AE72B5C0F7BA800C1B5DC55D7D6FE2EF4EED85D00AB111821321BA426A4FE4956B43595832C271E83E060341AE5F2023FC808177383; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init2 = 2048'h1A2955372D510AC266A5445146E27000020C320FAE1557E37154040A13202DC6F40B840FB9A59B6DBB296562CB6220EFBE99D2776A202044D9101006FD221D305519198C859000004012AFF4FB060307C92BB732203BFDFEFFFFFFDFFF87FCFFFBFFEFF03FFE0FFFBFAFE0FF80787FFF7FFF83F7F87003FFBFFFFBFFFBFF0FFC0FF81FFF7FFBFFDFFFBFFFE1FF0086F3141AAB6005810A0621595A893F9D85983B9254954341968BAC8C141C90938C05B2C9CD267E11650407375FEDD6A2FEB346AAF6CFDC0791AA97B741995A3B3981E06D1A44D3711955197BB9910FCA20744915C84D6C24BAF53929814CA8A4697E8F4201145AE7415DC122A5F010436107; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048'h02E84F969E3C800AC610D276182020227809001A50DDDBA3487BB6AE802BA06509312DA0E620656EAF24D57C08FFB14D289613DC32083803B84DC6415FD5EDC000300A8D128FA20030ACCBAFA237B7024504D36A4BA26081137F059E78991154FE2AC2A884A8CC7FBBB21C851CC92B12E15593C0C020FFEE066558590E882D5B67459F1A8C3240FE4E6A8D028C0C088FCF471D400A19B38211004DD122212288B111114514CB11840E04828849C621392041163C00808C67223422F00110201DD18FCFFFF3FFE7F9FFFFFFF82C0B422D214711E08904524A069491774E663F48F665955B4E2C63DAC0078652D10120900298F7EE380092442AFD400BEC43C003; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'hB5D49EA9D7036A45AA9E870B8E8016720C7C3102AE925262492C84584942D209042216E0216C85B8912250B7157D5955AD406CB685BBF071B47D5193363C1CECAFE59E91BF11498940A0944996D47EE8D7E3A4EAE611AE19A965D01BA86B55E9C52A6A379A382C6C265FB0DA01396D0800C0046405C06F466DD18C4DD7655CD4E7622EC485808C841D64B737041FF68813B149A41531A0A692FB14AE2E5B49D49CDCADCF90E7BD88125BCE706BF6D04AABFC1C001163DC6EFF7FD3230303030000000000000000000008400000000000000000000000000030600000100007E00220000000000000080040004023AD496997B8C0077B886EEF161CF2298A091B; +// synopsys translate_on + +// Location: M9K_X33_Y25_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a13 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(gnd), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[5]~77_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_bit_number = 5; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_first_bit_number = 5; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y28_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a5 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[5]~77_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a5_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_bit_number = 5; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_first_bit_number = 5; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init3 = 2048'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF80000001C000000160F000FF70C0007F78C00000F05001007870010010000000000800000038000000F000000070000000300000006000000000000040000000F00000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000000001D108000BEDA9FA9698A000000000000000000000000FFFFFFFF408102048004188297E014DA9FA9E9CA00000000000000000000000000000000FFFFFFFC800400CA972208DA9FA9CD8E00000000000000000000000000000000FFFFFFFC8004046A97A289FA9FA9CDC20000000000000000000000007FFFFFFC8000000280040E2A97A2997A9DA9CFC20000000000000000000000007FFFFFFE8000000280042EB28002BE369DA9274200000000000000000000000040810206BFFFFFFE9FE430A29D82AC3E8009E34A000000000000000000000000000000023FFFFFFC9FE4B1829FA2800E8009436A; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048'h9FE8334E88F827C697F88D1600A80A44809E8FC2B86999C2B85B3A82B1D32A869FE8336A88F807CA97F88F96A0A80EC2838E8D42B9E98FC2B86B3B82B0D7B2D2800832E288F827CA97F88B82A0080EC683869542B939B8C2B1AB0F8290B730C2800826EA8878078297F88AD2A0280EC283E694C2B83A3BC2A3AB3E8291A316AA800826EE881807C69DE8ABD6A0280BC282209CD2BA2A3D42A2737F82918314E2800806E6981805C69D48AED6A1E80BCA82709FC2BB223DC2A07B7F8295DF11C2800886E6980805869848AAC6A1E42DC281789DC2BBAA3DC6A02B7582955F00928008A6EE98082D9618088AC8A0F40FC289E89DC2BBCA3DC2A18B7782154F02F0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'h174F0870801C870281E2C982A801460297E5AC0288F318023FFFFFFC0000000297DF094A8094870281D6C082AC01460293FDA89288D31902BFFFFFFE40810106879F8D228C8685028016C082AC014642B3FCA80288D10F02800000027FFFFFFE879F893284DEC9028000408AAC014C02937DA00288D10F02800000027FFFFFFC841FA902804E81068BC04292AC0145E29379B00288D11F02FFFFFFFC0000000084FE89328166C1028BE05282AE4144829179B20288511F02FFFFFFFC0000000084F283328516850A88204602874364829179B08280513E0240810104FFFFFFFF843A8302853685828800560287476C928039B00200413E0000000000FFFFFFFF; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N20 +cycloneive_lcell_comb \Mux2~0 ( +// Equation(s): +// \Mux2~0_combout = (\Selector3~0_combout & (((\ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout )) # (!\z80_|address_pins_|abus[14]~23_combout ))) # (!\Selector3~0_combout & (\z80_|address_pins_|abus[14]~23_combout & +// ((\ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout )))) + + .dataa(\Selector3~0_combout ), + .datab(\z80_|address_pins_|abus[14]~23_combout ), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout ), + .cin(gnd), + .combout(\Mux2~0_combout ), + .cout()); +// synopsys translate_off +defparam \Mux2~0 .lut_mask = 16'hE6A2; +defparam \Mux2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N26 +cycloneive_lcell_comb \Mux2~1 ( +// Equation(s): +// \Mux2~1_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\Mux2~0_combout )))) # (!\z80_|address_pins_|abus[14]~23_combout & ((\Mux2~0_combout & (\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout )) # (!\Mux2~0_combout & +// ((\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ))))) + + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ), + .datad(\Mux2~0_combout ), + .cin(gnd), + .combout(\Mux2~1_combout ), + .cout()); +// synopsys translate_off +defparam \Mux2~1 .lut_mask = 16'hEE50; +defparam \Mux2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N8 +cycloneive_lcell_comb \D[5]~87 ( +// Equation(s): +// \D[5]~87_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [15] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\Mux2~1_combout ))))) # +// (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout )) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout ), + .datac(\Mux2~1_combout ), + .datad(\z80_|address_pins_|DFFE_apin_latch [15]), + .cin(gnd), + .combout(\D[5]~87_combout ), + .cout()); +// synopsys translate_off +defparam \D[5]~87 .lut_mask = 16'hCCE4; +defparam \D[5]~87 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N4 +cycloneive_lcell_comb \D[5]~68 ( +// Equation(s): +// \D[5]~68_combout = (\D[5]~67_combout & (\D[5]~87_combout & ((\z80_|data_pins_|dout [5]) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout )))) # (!\D[5]~67_combout & ((\z80_|data_pins_|dout [5]) # ((!\z80_|pin_control_|bus_db_pin_oe~15_combout )))) + + .dataa(\D[5]~67_combout ), + .datab(\z80_|data_pins_|dout [5]), + .datac(\D[5]~87_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .cin(gnd), + .combout(\D[5]~68_combout ), + .cout()); +// synopsys translate_off +defparam \D[5]~68 .lut_mask = 16'hC4F5; +defparam \D[5]~68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N12 +cycloneive_lcell_comb \D[5]~77 ( +// Equation(s): +// \D[5]~77_combout = (\D[5]~68_combout ) # (!\D[0]~84_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\D[5]~68_combout ), + .datad(\D[0]~84_combout ), + .cin(gnd), + .combout(\D[5]~77_combout ), + .cout()); +// synopsys translate_off +defparam \D[5]~77 .lut_mask = 16'hF0FF; +defparam \D[5]~77 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N16 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[5] ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [5] = (\D[5]~77_combout & ((\z80_|pin_control_|bus_db_pin_re~combout ) # ((\z80_|execute_|ctl_bus_db_we~7_combout & \z80_|bus_control_|db[5]~15_combout )))) # (!\D[5]~77_combout & +// (((\z80_|execute_|ctl_bus_db_we~7_combout & \z80_|bus_control_|db[5]~15_combout )))) + + .dataa(\D[5]~77_combout ), + .datab(\z80_|pin_control_|bus_db_pin_re~combout ), + .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datad(\z80_|bus_control_|db[5]~15_combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [5]), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[5] .lut_mask = 16'hF888; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[5] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y13_N25 +dffeas \z80_|data_pins_|dout[5] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [5]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|data_pins_|dout [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|data_pins_|dout[5] .is_wysiwyg = "true"; +defparam \z80_|data_pins_|dout[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N10 +cycloneive_lcell_comb \z80_|bus_control_|db[5]~14 ( +// Equation(s): +// \z80_|bus_control_|db[5]~14_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [5]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_bus_db_oe~combout ), + .datac(\z80_|bus_control_|db[0]~4_combout ), + .datad(\z80_|data_pins_|dout [5]), + .cin(gnd), + .combout(\z80_|bus_control_|db[5]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[5]~14 .lut_mask = 16'hF030; +defparam \z80_|bus_control_|db[5]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N18 +cycloneive_lcell_comb \z80_|bus_control_|db[5]~15 ( +// Equation(s): +// \z80_|bus_control_|db[5]~15_combout = ((\z80_|bus_control_|db[5]~14_combout & ((\z80_|alu_control_|db[5]~15_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) + + .dataa(\z80_|bus_control_|db[0]~6_combout ), + .datab(\z80_|alu_control_|db[5]~15_combout ), + .datac(\z80_|bus_control_|db[5]~14_combout ), + .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[5]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[5]~15 .lut_mask = 16'hD5F5; +defparam \z80_|bus_control_|db[5]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y16_N17 +dffeas \z80_|ir_|opcode[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|bus_control_|db[5]~15_combout ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|ir_|opcode [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|ir_|opcode[5] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~8 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~8_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal9~0_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal9~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~8 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_mRead~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_we~8_combout = (\z80_|sequencer_|M5~q & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|execute_|ctl_mRead~8_combout ) # (\z80_|pla_decode_|Equal9~1_combout )))) + + .dataa(\z80_|sequencer_|M5~q ), + .datab(\z80_|execute_|ctl_mRead~8_combout ), + .datac(\z80_|pla_decode_|Equal9~1_combout ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_we~8 .lut_mask = 16'h00A8; +defparam \z80_|execute_|ctl_bus_db_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y15_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_we~4_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mWrite~6_combout ) # ((\z80_|pla_decode_|Equal21~0_combout & \z80_|pla_decode_|Equal24~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal21~0_combout ), + .datab(\z80_|pla_decode_|Equal24~0_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ctl_mWrite~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_we~4 .lut_mask = 16'hF080; +defparam \z80_|execute_|ctl_bus_db_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_we~6_combout = (\z80_|execute_|ctl_bus_db_we~4_combout ) # (((!\z80_|execute_|ctl_apin_mux~0_combout ) # (!\z80_|execute_|ctl_sw_2u~3_combout )) # (!\z80_|execute_|ctl_bus_db_we~5_combout )) + + .dataa(\z80_|execute_|ctl_bus_db_we~4_combout ), + .datab(\z80_|execute_|ctl_bus_db_we~5_combout ), + .datac(\z80_|execute_|ctl_sw_2u~3_combout ), + .datad(\z80_|execute_|ctl_apin_mux~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_we~6 .lut_mask = 16'hBFFF; +defparam \z80_|execute_|ctl_bus_db_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout = (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal8~0_combout & \z80_|execute_|ctl_ir_we~4_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~0_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|pla_decode_|Equal8~0_combout ), + .datad(\z80_|execute_|ctl_ir_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_we~3_combout = (\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_iorw~10_combout ) # (\z80_|execute_|ctl_mWrite~7_combout )))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ), + .datac(\z80_|execute_|ctl_iorw~10_combout ), + .datad(\z80_|execute_|ctl_mWrite~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_we~3 .lut_mask = 16'hEEEC; +defparam \z80_|execute_|ctl_bus_db_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_we~2_combout = (\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|pla_decode_|Equal13~2_combout ) # ((\z80_|execute_|ctl_mRead~8_combout ) # (\z80_|execute_|ctl_mWrite~7_combout )))) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ctl_mRead~8_combout ), + .datad(\z80_|execute_|ctl_mWrite~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_we~2 .lut_mask = 16'hCCC8; +defparam \z80_|execute_|ctl_bus_db_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_we~7_combout = (\z80_|execute_|ctl_bus_db_we~8_combout ) # ((\z80_|execute_|ctl_bus_db_we~6_combout ) # ((\z80_|execute_|ctl_bus_db_we~3_combout ) # (\z80_|execute_|ctl_bus_db_we~2_combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_we~8_combout ), + .datab(\z80_|execute_|ctl_bus_db_we~6_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~3_combout ), + .datad(\z80_|execute_|ctl_bus_db_we~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_we~7 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_bus_db_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~66 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][0]~66_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|zx_keyboard_|shifted~q )) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|shifted~q ), .datad(gnd), .cin(gnd), - .combout(\z80_|execute_|ctl_apin_mux~2_combout ), + .combout(\ula_|zx_keyboard_|keys[5][0]~66_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_apin_mux~2 .lut_mask = 16'h8F8F; -defparam \z80_|execute_|ctl_apin_mux~2 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[5][0]~66 .lut_mask = 16'hCECE; +defparam \ula_|zx_keyboard_|keys[5][0]~66 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y16_N18 +// Location: LCCOMB_X29_Y8_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~80 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][0]~80_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [0]))) # (!\ula_|ps2_keyboard_|shiftreg [4] & +// (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [0]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][0]~80_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][0]~80 .lut_mask = 16'h1008; +defparam \ula_|zx_keyboard_|keys[5][0]~80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~81 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][0]~81_combout = (\ula_|zx_keyboard_|keys[5][0]~80_combout & (\ula_|ps2_keyboard_|shiftreg [2] $ (\ula_|ps2_keyboard_|shiftreg [4]))) + + .dataa(\ula_|zx_keyboard_|keys[5][0]~80_combout ), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][0]~81_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][0]~81 .lut_mask = 16'h0AA0; +defparam \ula_|zx_keyboard_|keys[5][0]~81 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~82 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][0]~82_combout = (\ula_|zx_keyboard_|keys[6][1]~39_combout & ((\ula_|zx_keyboard_|keys[5][0]~81_combout & (!\ula_|zx_keyboard_|keys[5][0]~66_combout )) # (!\ula_|zx_keyboard_|keys[5][0]~81_combout & +// ((\ula_|zx_keyboard_|keys[5][0]~q ))))) # (!\ula_|zx_keyboard_|keys[6][1]~39_combout & (((\ula_|zx_keyboard_|keys[5][0]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][0]~66_combout ), + .datab(\ula_|zx_keyboard_|keys[6][1]~39_combout ), + .datac(\ula_|zx_keyboard_|keys[5][0]~q ), + .datad(\ula_|zx_keyboard_|keys[5][0]~81_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][0]~82_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][0]~82 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[5][0]~82 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y8_N5 +dffeas \ula_|zx_keyboard_|keys[5][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[5][0]~82_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[5][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[5][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~84 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][0]~84_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|zx_keyboard_|shifted~q )) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|zx_keyboard_|shifted~q ), + .datac(gnd), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][0]~84_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][0]~84 .lut_mask = 16'hFF22; +defparam \ula_|zx_keyboard_|keys[4][0]~84 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~83 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][0]~83_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [5] $ (\ula_|ps2_keyboard_|shiftreg [3])))) # (!\ula_|ps2_keyboard_|shiftreg [1] & +// (!\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [0]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][0]~83_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][0]~83 .lut_mask = 16'h0148; +defparam \ula_|zx_keyboard_|keys[4][0]~83 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~85 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][0]~85_combout = (\ula_|zx_keyboard_|keys[4][0]~83_combout & ((\ula_|zx_keyboard_|keys[5][1]~35_combout & (!\ula_|zx_keyboard_|keys[4][0]~84_combout )) # (!\ula_|zx_keyboard_|keys[5][1]~35_combout & +// ((\ula_|zx_keyboard_|keys[4][0]~q ))))) # (!\ula_|zx_keyboard_|keys[4][0]~83_combout & (((\ula_|zx_keyboard_|keys[4][0]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[4][0]~84_combout ), + .datab(\ula_|zx_keyboard_|keys[4][0]~83_combout ), + .datac(\ula_|zx_keyboard_|keys[4][0]~q ), + .datad(\ula_|zx_keyboard_|keys[5][1]~35_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][0]~85_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][0]~85 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[4][0]~85 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y10_N21 +dffeas \ula_|zx_keyboard_|keys[4][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[4][0]~85_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[4][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[4][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N14 +cycloneive_lcell_comb \D[0]~42 ( +// Equation(s): +// \D[0]~42_combout = (\z80_|address_pins_|abus[12]~21_combout & (((\z80_|address_pins_|abus[13]~20_combout )) # (!\ula_|zx_keyboard_|keys[5][0]~q ))) # (!\z80_|address_pins_|abus[12]~21_combout & (!\ula_|zx_keyboard_|keys[4][0]~q & +// ((\z80_|address_pins_|abus[13]~20_combout ) # (!\ula_|zx_keyboard_|keys[5][0]~q )))) + + .dataa(\z80_|address_pins_|abus[12]~21_combout ), + .datab(\ula_|zx_keyboard_|keys[5][0]~q ), + .datac(\z80_|address_pins_|abus[13]~20_combout ), + .datad(\ula_|zx_keyboard_|keys[4][0]~q ), + .cin(gnd), + .combout(\D[0]~42_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~42 .lut_mask = 16'hA2F3; +defparam \D[0]~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][0]~78 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][0]~78_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|zx_keyboard_|keys[1][4]~23_combout & \ula_|ps2_keyboard_|shiftreg [3]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|zx_keyboard_|keys[1][4]~23_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][0]~78_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][0]~78 .lut_mask = 16'h1000; +defparam \ula_|zx_keyboard_|keys[1][0]~78 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][0]~79 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][0]~79_combout = (\ula_|zx_keyboard_|keys[1][0]~78_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[1][0]~78_combout & ((\ula_|zx_keyboard_|keys[1][0]~q ))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[1][0]~q ), + .datad(\ula_|zx_keyboard_|keys[1][0]~78_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][0]~79_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][0]~79 .lut_mask = 16'h55F0; +defparam \ula_|zx_keyboard_|keys[1][0]~79 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y9_N27 +dffeas \ula_|zx_keyboard_|keys[1][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[1][0]~79_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[1][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[1][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][0]~76 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][0]~76_combout = (\ula_|zx_keyboard_|keys[3][1]~26_combout & ((\ula_|zx_keyboard_|keys[3][0]~75_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][0]~75_combout & ((\ula_|zx_keyboard_|keys[3][0]~q +// ))))) # (!\ula_|zx_keyboard_|keys[3][1]~26_combout & (((\ula_|zx_keyboard_|keys[3][0]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[3][1]~26_combout ), + .datac(\ula_|zx_keyboard_|keys[3][0]~q ), + .datad(\ula_|zx_keyboard_|keys[3][0]~75_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][0]~76_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][0]~76 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[3][0]~76 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y9_N13 +dffeas \ula_|zx_keyboard_|keys[3][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[3][0]~76_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[3][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[3][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][0]~77 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][0]~77_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (((\ula_|zx_keyboard_|keys[2][0]~q )))) # (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[2][1]~24_combout & (!\ula_|zx_keyboard_|released~q )) # +// (!\ula_|zx_keyboard_|keys[2][1]~24_combout & ((\ula_|zx_keyboard_|keys[2][0]~q ))))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|zx_keyboard_|keys[2][0]~q ), + .datad(\ula_|zx_keyboard_|keys[2][1]~24_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][0]~77_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][0]~77 .lut_mask = 16'hD1F0; +defparam \ula_|zx_keyboard_|keys[2][0]~77 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y9_N11 +dffeas \ula_|zx_keyboard_|keys[2][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[2][0]~77_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[2][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[2][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N28 +cycloneive_lcell_comb \D[0]~40 ( +// Equation(s): +// \D[0]~40_combout = (\ula_|zx_keyboard_|keys[3][0]~q & (\z80_|address_pins_|abus[11]~19_combout & ((\z80_|address_pins_|abus[10]~24_combout ) # (!\ula_|zx_keyboard_|keys[2][0]~q )))) # (!\ula_|zx_keyboard_|keys[3][0]~q & +// ((\z80_|address_pins_|abus[10]~24_combout ) # ((!\ula_|zx_keyboard_|keys[2][0]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[3][0]~q ), + .datab(\z80_|address_pins_|abus[10]~24_combout ), + .datac(\z80_|address_pins_|abus[11]~19_combout ), + .datad(\ula_|zx_keyboard_|keys[2][0]~q ), + .cin(gnd), + .combout(\D[0]~40_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~40 .lut_mask = 16'hC4F5; +defparam \D[0]~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr0~0 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr0~0_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [0])) # (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg +// [2])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr0~0 .lut_mask = 16'h1012; +defparam \ula_|zx_keyboard_|WideOr0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys~71 ( +// Equation(s): +// \ula_|zx_keyboard_|keys~71_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (((!\ula_|zx_keyboard_|WideOr0~0_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [4] & (((!\ula_|ps2_keyboard_|shiftreg [3])) # (!\ula_|zx_keyboard_|keys[6][4]~45_combout ))) + + .dataa(\ula_|zx_keyboard_|keys[6][4]~45_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|zx_keyboard_|WideOr0~0_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys~71_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys~71 .lut_mask = 16'h13DF; +defparam \ula_|zx_keyboard_|keys~71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~70 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][3]~70_combout = (\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [6]) + + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][3]~70_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][3]~70 .lut_mask = 16'hAA00; +defparam \ula_|zx_keyboard_|keys[4][3]~70 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~72 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][0]~72_combout = (\ula_|zx_keyboard_|keys[0][0]~13_combout & (((!\ula_|zx_keyboard_|keys~71_combout & \ula_|zx_keyboard_|keys[4][3]~70_combout )) # (!\ula_|zx_keyboard_|extended~q ))) + + .dataa(\ula_|zx_keyboard_|extended~q ), + .datab(\ula_|zx_keyboard_|keys~71_combout ), + .datac(\ula_|zx_keyboard_|keys[0][0]~13_combout ), + .datad(\ula_|zx_keyboard_|keys[4][3]~70_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][0]~72_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][0]~72 .lut_mask = 16'h7050; +defparam \ula_|zx_keyboard_|keys[0][0]~72 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr4~0 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr4~0_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (((\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [1])))) # (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [4] & +// (!\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr4~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr4~0 .lut_mask = 16'hA004; +defparam \ula_|zx_keyboard_|WideOr4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys~73 ( +// Equation(s): +// \ula_|zx_keyboard_|keys~73_combout = (!\ula_|zx_keyboard_|extended~q & (((\ula_|ps2_keyboard_|shiftreg [3]) # (!\ula_|zx_keyboard_|WideOr4~0_combout )) # (!\ula_|zx_keyboard_|keys[4][1]~29_combout ))) + + .dataa(\ula_|zx_keyboard_|extended~q ), + .datab(\ula_|zx_keyboard_|keys[4][1]~29_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|zx_keyboard_|WideOr4~0_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys~73_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys~73 .lut_mask = 16'h5155; +defparam \ula_|zx_keyboard_|keys~73 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~74 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][0]~74_combout = (\ula_|zx_keyboard_|keys[0][0]~72_combout & ((\ula_|zx_keyboard_|keys~73_combout & (\ula_|zx_keyboard_|keys[0][0]~q )) # (!\ula_|zx_keyboard_|keys~73_combout & ((!\ula_|zx_keyboard_|released~q ))))) # +// (!\ula_|zx_keyboard_|keys[0][0]~72_combout & (((\ula_|zx_keyboard_|keys[0][0]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[0][0]~72_combout ), + .datab(\ula_|zx_keyboard_|keys~73_combout ), + .datac(\ula_|zx_keyboard_|keys[0][0]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][0]~74_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][0]~74 .lut_mask = 16'hD0F2; +defparam \ula_|zx_keyboard_|keys[0][0]~74 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y8_N11 +dffeas \ula_|zx_keyboard_|keys[0][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[0][0]~74_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[0][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[0][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~2 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row~2_combout = ((\z80_|address_pins_|DFFE_apin_latch [8]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) # (!\ula_|zx_keyboard_|keys[0][0]~q ) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|keys[0][0]~q ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [8]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row~2 .lut_mask = 16'hFF3F; +defparam \ula_|zx_keyboard_|key_row~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N16 +cycloneive_lcell_comb \D[0]~41 ( +// Equation(s): +// \D[0]~41_combout = (\D[0]~40_combout & (\ula_|zx_keyboard_|key_row~2_combout & ((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][0]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[1][0]~q ), + .datab(\D[0]~40_combout ), + .datac(\ula_|zx_keyboard_|key_row~2_combout ), + .datad(\z80_|address_pins_|abus[9]~17_combout ), + .cin(gnd), + .combout(\D[0]~41_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~41 .lut_mask = 16'hC040; +defparam \D[0]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~89 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][0]~89_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][0]~89_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][0]~89 .lut_mask = 16'h0008; +defparam \ula_|zx_keyboard_|keys[6][0]~89 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~90 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][0]~90_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|zx_keyboard_|keys[6][0]~89_combout & (\ula_|zx_keyboard_|shifted~3_combout & \ula_|zx_keyboard_|keys[7][1]~21_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|zx_keyboard_|keys[6][0]~89_combout ), + .datac(\ula_|zx_keyboard_|shifted~3_combout ), + .datad(\ula_|zx_keyboard_|keys[7][1]~21_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][0]~90_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][0]~90 .lut_mask = 16'h8000; +defparam \ula_|zx_keyboard_|keys[6][0]~90 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~91 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][0]~91_combout = (\ula_|zx_keyboard_|keys[6][0]~90_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[6][0]~90_combout & (\ula_|zx_keyboard_|keys[6][0]~q )) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|keys[6][0]~90_combout ), + .datac(\ula_|zx_keyboard_|keys[6][0]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][0]~91_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][0]~91 .lut_mask = 16'h30FC; +defparam \ula_|zx_keyboard_|keys[6][0]~91 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y10_N19 +dffeas \ula_|zx_keyboard_|keys[6][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[6][0]~91_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[6][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[6][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~131 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][0]~131_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|keys[3][0]~75_combout & (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [6]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|zx_keyboard_|keys[3][0]~75_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][0]~131_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][0]~131 .lut_mask = 16'h8000; +defparam \ula_|zx_keyboard_|keys[7][0]~131 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~3 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~3_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [6]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~3 .lut_mask = 16'h000F; +defparam \ula_|zx_keyboard_|WideOr16~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~86 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][0]~86_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|zx_keyboard_|keys[5][4]~62_combout & (\ula_|zx_keyboard_|WideOr16~3_combout & \ula_|ps2_keyboard_|shiftreg [3]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|zx_keyboard_|keys[5][4]~62_combout ), + .datac(\ula_|zx_keyboard_|WideOr16~3_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][0]~86_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][0]~86 .lut_mask = 16'h4000; +defparam \ula_|zx_keyboard_|keys[7][0]~86 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~87 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][0]~87_combout = (\ula_|zx_keyboard_|keys[7][1]~21_combout & (\ula_|ps2_keyboard_|shiftreg [5] & ((\ula_|zx_keyboard_|keys[7][0]~131_combout ) # (\ula_|zx_keyboard_|keys[7][0]~86_combout )))) + + .dataa(\ula_|zx_keyboard_|keys[7][1]~21_combout ), + .datab(\ula_|zx_keyboard_|keys[7][0]~131_combout ), + .datac(\ula_|zx_keyboard_|keys[7][0]~86_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][0]~87_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][0]~87 .lut_mask = 16'hA800; +defparam \ula_|zx_keyboard_|keys[7][0]~87 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~88 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][0]~88_combout = (\ula_|zx_keyboard_|keys[7][0]~87_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[7][0]~87_combout & (\ula_|zx_keyboard_|keys[7][0]~q )) + + .dataa(\ula_|zx_keyboard_|keys[7][0]~87_combout ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[7][0]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][0]~88_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][0]~88 .lut_mask = 16'h50FA; +defparam \ula_|zx_keyboard_|keys[7][0]~88 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y10_N5 +dffeas \ula_|zx_keyboard_|keys[7][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[7][0]~88_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[7][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[7][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N12 +cycloneive_lcell_comb \D[0]~43 ( +// Equation(s): +// \D[0]~43_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\z80_|address_pins_|abus[15]~22_combout ) # (!\ula_|zx_keyboard_|keys[7][0]~q )))) # (!\z80_|address_pins_|abus[14]~23_combout & (!\ula_|zx_keyboard_|keys[6][0]~q & +// ((\z80_|address_pins_|abus[15]~22_combout ) # (!\ula_|zx_keyboard_|keys[7][0]~q )))) + + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\ula_|zx_keyboard_|keys[6][0]~q ), + .datac(\ula_|zx_keyboard_|keys[7][0]~q ), + .datad(\z80_|address_pins_|abus[15]~22_combout ), + .cin(gnd), + .combout(\D[0]~43_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~43 .lut_mask = 16'hBB0B; +defparam \D[0]~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N10 +cycloneive_lcell_comb \D[0]~44 ( +// Equation(s): +// \D[0]~44_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[0]~42_combout & (\D[0]~41_combout & \D[0]~43_combout ))) + + .dataa(\D[0]~42_combout ), + .datab(\D[0]~41_combout ), + .datac(\z80_|address_pins_|abus[0]~16_combout ), + .datad(\D[0]~43_combout ), + .cin(gnd), + .combout(\D[0]~44_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~44 .lut_mask = 16'hF8F0; +defparam \D[0]~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y17_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a24 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[0]~46_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_first_bit_number = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y18_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a16 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[0]~46_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_first_bit_number = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y15_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a8 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[0]~46_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y19_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a0 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[0]~46_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081; +// synopsys translate_on + +// Location: LCCOMB_X23_Y14_N12 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout )) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ))))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4 .lut_mask = 16'hE3E0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y14_N6 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~5 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~5_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4_combout & +// (\ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout )) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout ))))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4_combout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~5 .lut_mask = 16'hAFC0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y13_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a8 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h3C00000000000000000000000000000000000000000000000000000000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005DB824E17CAAE881C1908A79F24B7D1B4857A981A6AF39DFF5A2FEE9141EB33592D8E9B82471FDDA6791810A1C29D415CC1A8FA03444DF0083F83506BA93E8D1A1856A768D73A08418BFB25A40001DD4833DAF33BD311BB45F39667627407EF59ED569C483EB3BE1B10551B1428A6169579293ED063CAA9C6ADB0433CFC15C33AFF04C710408C20AC28B5909A229CD7D1DB4EB9A44CE0EEDBBBD391D3128AAA3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'hDDE6FC8EBE3F9F3C3DFC6E8F07BFD31D50660B1E0B2506A533CE0E340C7C745CAEC4837C2A5FECBB94C1C969FFDDFF79BFFAAFDCA8D748399ABF75558ADD02F56F6DFFF29CB70FFD25A59DFFFED7B3F7E8B4CE6FFF3EF9CEC6BAE57ABFFFCEE647B2AFF5B87AA26AFFDD317DEDCFBDFFE1A0CAD3B58877DD2F647F7DF748E7CF4693FD3C1238FFAFBD7FDF567FA8FEF024F33AFD3AABC6B105EA80272D64895FFF9FFF6E3881C81AFDCF2257FD4F8ED5257D0E9B800726B6564D2B05012F76DF636CDEB4BDFCAEEFC61DFFEFB7E26262DEF2CB9F71565824FEBF3F7BDDEABB593F1BF746FBFFC353E37263FF38A796EF39E3FD7DFEBA7FFEFFBD97ABAF09E909; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'hE629BDF93D7F5B5BAF92FBAB477E9B315DB5A310CFACC7408DF9A544B1E57AF6EFEF92C2FA4D8D4E4AC86C277338FA37BCDD9D47782DB75EFF80781BCD23D0AFCAE30B9FE6AA29FFF6F72DA73DFE4F7ACD39687B9E69C5359E9B991F0246EFFBC5595561AC64787878F5CE14C664CF9EB0CDAFFBABEF1E83358371B9ED96E5069555AFBBD3AEBFCABFBBED7A5C5FE9BD0E6A91C6E7610042695EEB08D8881B1D735AF87DAE59FABBD7DEAF8717F2B72F428F5E37E5D6E13157B99CBD2D73B9C73C563C8B02C8CC39C64DDCEA1BEEB5E7353F93786145598FE634EF1000179B345725EA43CE18F187A1DE4DAABEA97963E3A7A96B8B7CBC095BEB7CE46274D9AF; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h4ED4AE2B1650D21EAFE01E7099EFCA3094FD4D705CF6B84AE21583E13385F8650004406BD60A023AB063D4E5966EA41AA997F5A49BFCB0657A9732D28EB8217E65F627A15E1057ADEE7B9E27122A58FB2B98B1EA560390C7E87715861814E04DCB76FAB179E9619BC7E7E9C9FD801CF87DBA1EA496E829D4E62861E1AF436A7585287860729C77B6C68CAEA3033A6E84D67249B594C407B39C68B4C1C97FDEFC6BAD12FDBB525EF4F87F4A23EC13CBC0262D8899A3A290F04F41C1324045B9FCEEC890579E95D5A0A546CCCDD48577558ABE7CA36EF67A70F6A8758BDA052D5B95DE707778B17C2379847A23AE5D4BB01F36F3F44A8162566D9FB15DE7CC83F7; +// synopsys translate_on + +// Location: M9K_X22_Y28_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a0 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[0]~46_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_bit_number = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF0000000000000000000000003FF03FFC20107FFC3FF00B9C3FF007FC18000FFC3FF03FD42FF43FFC2FFC3FE01FFE7FE81FFE3FDC07FE3FFC07FE2FFC07FE0F0807FE1F18207F0F3030FD8C30383300600000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h000000000000000000000000FFFFFFFFE0408103E004044390120EAA803920C6000000000000000000000000FFFFFFFFE0408103A004005A84723CEA813930C2000000000000000000000000800000009FBF7EFD8004027A8572358A813950EA000000000000000000000000800000009FBF7EFC8005157A85733F0A8139518E0000000000000000000000009FBF7EFC800000008006113A8C73330A813919EA0000000000000000000000009FBF7EFC8000000080060022801333A2813973EA00000000000000000000000080000000DFFFFFFD9FF6022A84730366801913FE000000000000000000000000E0408102FFFFFFFD9FF60ABA84730426901913EE; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h9FF81326887812F28FF0D7C2CC6856E3894C8B62980099E28988BFC2B9EC79829FE81362887842E68FF0C7C2CCE056E2896C89E2888098E28AA8BBC299FC1AC280081372887842E69EE0C7CA8CE046E289E089E289C899E28AA8BEC2993C1AE28008837E882852C69EE0874288E046E2886099E289689FCE8AD8BFC2999C09F680088376880846C69CA88382880042A289D08DE289F098C28AF8BFC289FC88F280088376880857C29CA893C2888043A289508DE288F0D9428BF0AFC289F4888A800883F2880857829C2891C3889047F2898885E2899081428990AF8289FC8BE3800893F6880847C2DC0894E389944F62888899668918914289803582CB8C8AF3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'hCBAC80F38DA845828DF44582840124029375A4A288D108A2FFFFFFFDE0408082CAEC80968DF855828CE4408284012006917194C280510B82DFFFFFFC8000000288EC84A28FFC4586880C648A860124128179900280510F82800000009FBF7F7C8BA080BA8FEC40828808618286012C028179901280510702800000009FBF7F7C8BB081BA8CAC408289E0618286812C1281791002805007029FBF7F7C8000000089B881828CB440828BE07782868322028139909280400F029FBF7F7D8000000089A4C3928FF444828A00260A8792227281199022A0001F03E0408081FFFFFFFF89A0C1928FD440828800260687B720C280199002E0001F03E0408083FFFFFFFF; +// synopsys translate_on + +// Location: M9K_X22_Y21_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a8 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(gnd), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[0]~46_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_first_bit_number = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X23_Y14_N4 +cycloneive_lcell_comb \Selector2~0 ( +// Equation(s): +// \Selector2~0_combout = (\Selector3~0_combout & (((\ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ) # (!\z80_|address_pins_|abus[14]~23_combout )))) # (!\Selector3~0_combout & +// (\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout & (\z80_|address_pins_|abus[14]~23_combout ))) + + .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ), + .datab(\Selector3~0_combout ), + .datac(\z80_|address_pins_|abus[14]~23_combout ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ), + .cin(gnd), + .combout(\Selector2~0_combout ), + .cout()); +// synopsys translate_off +defparam \Selector2~0 .lut_mask = 16'hEC2C; +defparam \Selector2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y31_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a0 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h1EEA3633EFEA856D05BA968C1B3C30CA1788DD95D16B8F914DDDFC3EE5C69945DF7D7BF31C6072BFA7993996AB7DD2F3EE4009844CC9D6CF9E583AEC48A52F2904B57D8E0D755851232838F9B5348838530D7AF95411555D263B8CA86A5D29D7CE4B65409D6F04C5709A56C241C3BCEF07459A416EB4E8F3D73CC714F4333AFE605D53A5C955D5D1412F8361617A54446971FD187442A60FB04457857BECC3120A01FDC7FE2CBF038A61DEE5FCE2D10C8F35FBF80C05ABFF4B6935287B125E8D56F9FDFE7D64C1F4E1F5641845CD17E836B97780400C702523FA8E7C7BBD6F0666591A35ADD26B6B7E33CA56E9AB329EFA7E68F98AE7CE9507755C74C430286A; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h88537A811D4EF6CD9668CCD3E2E7A8041788DCA5F7E08AF52AF5276078304DEB75B74BB9AC3C1A492952F7EEAA0E7CF9FBEDD0FB47EEFDCC3734B816F355C913CD2E1AF14C30545297A91BED3AEAEFF8F696B5F4FC80BC6B1A2559492E9198E4A5875745B625C6CA7A7292332492D139728A689DA1AE78B6B44CE4F4A4EA5A22F331598B364EF27516CC49A4662C5E5C92ED140D96373678F833AE434698237599716B8CBAE2D3D061F2C3D6337AB435B5C2144AB6FA2F8BB51357801066B6589467DA6C480E6D19CEEA8451CEFA88FD70E7925B0302F877F87FA833FBD147E937309C08305A10187707E3D57DDE4931F1D9E97A8F378981ABBF8D7B6B7539C3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h763DD7AA7EED3F4AD4EA7491ADE6F14E6DBADD0F090A8DF34D7BAD35DD2275F0BCCF19EEF299751C919C9C13C6FB9ED711AC4DA7D947CC79E9B6323EF6CE62638CEBCB187AE5D44ECA689C9BD4E5AE544DEA7E90D186B9F335F3323877AAD54196CE81973CB555904419599375501366EC343561BCF83357F8823671393B278C1C387A7970C7F3E688673CF5975EE3E5FF105CFCCFAB725D698FB088B063063C7833830C7B2C7AFB8A8D203C312306DA0E72641FFB93D59B5EC84F44AD55F4B884735325ACC969B2EAE10A1478D866F667DDEF7BBF75E6958B6D02DC6D0F807660A229B98541E6FE734DE2280A9B57FCD5A9BEFEF7CDA5ABEB44FD73D2794D56; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'hD0734B461A36980411EB2A6C1BE76029258777EF227A8F6E84F74C4436098F67BA611013110188547995B108BB2DAE76F423A0D98845F9248BDFA45E10CA403A5E2B1A3E16869E1D37BCE906B82F401CBD467617DB34D9E0C80B5E6E10063EC4BD52921D249E377D95CFAAA309EEDAA57DA85F55DBB7048A69A4C801013948B617F7F5724D40707E6FF30002982023020449B4680C45D1CE6D8EB30A061DB8FEDD6E630C15271E48CA801988654FB501D5393392EE765C1EC95C1E4D86F18A965372B72B484E2F2664B735B69A5AB532B086BA4C62AD6D56EECBDB6984B251454845BD5B243DAED2B2489B313A35C50252AFD3E0B76FEF342335C7F1321D92FF; +// synopsys translate_on + +// Location: LCCOMB_X23_Y14_N28 +cycloneive_lcell_comb \Selector2~1 ( +// Equation(s): +// \Selector2~1_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\Selector2~0_combout )))) # (!\z80_|address_pins_|abus[14]~23_combout & ((\Selector2~0_combout & (\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout )) # +// (!\Selector2~0_combout & ((\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ))))) + + .dataa(\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ), + .datab(\z80_|address_pins_|abus[14]~23_combout ), + .datac(\Selector2~0_combout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ), + .cin(gnd), + .combout(\Selector2~1_combout ), + .cout()); +// synopsys translate_off +defparam \Selector2~1 .lut_mask = 16'hE3E0; +defparam \Selector2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y14_N30 +cycloneive_lcell_comb \D[0]~83 ( +// Equation(s): +// \D[0]~83_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [15] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~5_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\Selector2~1_combout +// ))))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~5_combout )) + + .dataa(\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~5_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [15]), + .datad(\Selector2~1_combout ), + .cin(gnd), + .combout(\D[0]~83_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~83 .lut_mask = 16'hAEA2; +defparam \D[0]~83 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y14_N14 +cycloneive_lcell_comb \D[0]~45 ( +// Equation(s): +// \D[0]~45_combout = ((\Equal2~0_combout & (\D[0]~44_combout )) # (!\Equal2~0_combout & ((\D[0]~83_combout )))) # (!\Equal2~1_combout ) + + .dataa(\Equal2~0_combout ), + .datab(\D[0]~44_combout ), + .datac(\D[0]~83_combout ), + .datad(\Equal2~1_combout ), + .cin(gnd), + .combout(\D[0]~45_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~45 .lut_mask = 16'hD8FF; +defparam \D[0]~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y14_N0 +cycloneive_lcell_comb \D[0]~46 ( +// Equation(s): +// \D[0]~46_combout = (\z80_|pin_control_|bus_db_pin_oe~15_combout & (((\D[0]~45_combout & \z80_|data_pins_|dout [0])))) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout & (((\D[0]~45_combout )) # (!\Equal2~1_combout ))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .datab(\Equal2~1_combout ), + .datac(\D[0]~45_combout ), + .datad(\z80_|data_pins_|dout [0]), + .cin(gnd), + .combout(\D[0]~46_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~46 .lut_mask = 16'hF151; +defparam \D[0]~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N26 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [0] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[0]~17_combout ) # ((\D[0]~46_combout & \z80_|pin_control_|bus_db_pin_re~combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & +// (\D[0]~46_combout & ((\z80_|pin_control_|bus_db_pin_re~combout )))) + + .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datab(\D[0]~46_combout ), + .datac(\z80_|bus_control_|db[0]~17_combout ), + .datad(\z80_|pin_control_|bus_db_pin_re~combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [0]), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] .lut_mask = 16'hECA0; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y13_N27 +dffeas \z80_|data_pins_|dout[0] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [0]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|data_pins_|dout [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|data_pins_|dout[0] .is_wysiwyg = "true"; +defparam \z80_|data_pins_|dout[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N10 +cycloneive_lcell_comb \z80_|bus_control_|db[0]~16 ( +// Equation(s): +// \z80_|bus_control_|db[0]~16_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [0]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) + + .dataa(\z80_|data_pins_|dout [0]), + .datab(\z80_|bus_control_|db[0]~4_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|bus_control_|db[0]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[0]~16 .lut_mask = 16'h8C8C; +defparam \z80_|bus_control_|db[0]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N0 +cycloneive_lcell_comb \z80_|bus_control_|db[0]~17 ( +// Equation(s): +// \z80_|bus_control_|db[0]~17_combout = ((\z80_|bus_control_|db[0]~16_combout & ((\z80_|alu_control_|db[0]~12_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) + + .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datab(\z80_|alu_control_|db[0]~12_combout ), + .datac(\z80_|bus_control_|db[0]~6_combout ), + .datad(\z80_|bus_control_|db[0]~16_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[0]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[0]~17 .lut_mask = 16'hDF0F; +defparam \z80_|bus_control_|db[0]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y13_N1 +dffeas \z80_|ir_|opcode[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|bus_control_|db[0]~17_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|ir_|opcode [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|ir_|opcode[0] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal3~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal3~2_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal52~0_combout & \z80_|pla_decode_|Equal3~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal3~1_combout ), + .datac(\z80_|pla_decode_|Equal52~0_combout ), + .datad(\z80_|pla_decode_|Equal3~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal3~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal3~2 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal3~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal43~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal43~0_combout = (\z80_|pla_decode_|Equal1~7_combout & (\z80_|pla_decode_|Equal32~0_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal3~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal1~7_combout ), + .datab(\z80_|pla_decode_|Equal32~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal3~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal43~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal43~0 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal43~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N24 +cycloneive_lcell_comb \z80_|interrupts_|test1~2 ( +// Equation(s): +// \z80_|interrupts_|test1~2_combout = (!\z80_|pla_decode_|Equal3~2_combout & (!\z80_|pla_decode_|Equal43~0_combout & (!\z80_|pla_decode_|Equal79~0_combout & !\z80_|pla_decode_|Equal36~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal3~2_combout ), + .datab(\z80_|pla_decode_|Equal43~0_combout ), + .datac(\z80_|pla_decode_|Equal79~0_combout ), + .datad(\z80_|pla_decode_|Equal36~0_combout ), + .cin(gnd), + .combout(\z80_|interrupts_|test1~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|test1~2 .lut_mask = 16'h0001; +defparam \z80_|interrupts_|test1~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N22 +cycloneive_lcell_comb \z80_|interrupts_|test1~3 ( +// Equation(s): +// \z80_|interrupts_|test1~3_combout = (!\z80_|execute_|setM1~54_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (\z80_|interrupts_|test1~2_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|execute_|setM1~54_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|interrupts_|test1~2_combout ), + .cin(gnd), + .combout(\z80_|interrupts_|test1~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|test1~3 .lut_mask = 16'h3331; +defparam \z80_|interrupts_|test1~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y13_N1 +dffeas \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|interrupts_|test1~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED .is_wysiwyg = "true"; +defparam \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N6 +cycloneive_lcell_comb \z80_|clk_delay_|SYNTHESIZED_WIRE_4 ( +// Equation(s): +// \z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (!\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|interrupts_|DFFE_inst44~q ))) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|interrupts_|DFFE_inst44~q ), + .cin(gnd), + .combout(\z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_4 .lut_mask = 16'h0100; +defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y14_N7 +dffeas \z80_|clk_delay_|SYNTHESIZED_WIRE_7 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_7 .is_wysiwyg = "true"; +defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_7 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N12 +cycloneive_lcell_comb \z80_|clk_delay_|hold_clk_iorq ( +// Equation(s): +// \z80_|clk_delay_|hold_clk_iorq~combout = (!\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q & !\z80_|clk_delay_|DFF_inst5~q ) + + .dataa(\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ), + .datab(\z80_|clk_delay_|DFF_inst5~q ), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\z80_|clk_delay_|hold_clk_iorq~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|clk_delay_|hold_clk_iorq .lut_mask = 16'h1111; +defparam \z80_|clk_delay_|hold_clk_iorq .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y13_N31 +dffeas \z80_|sequencer_|DFFE_T4_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_T4_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_T4_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_T4_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_eval_cond~0 ( +// Equation(s): +// \z80_|execute_|ctl_eval_cond~0_combout = (\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_eval_cond~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_eval_cond~0 .lut_mask = 16'h00F0; +defparam \z80_|execute_|ctl_eval_cond~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~27 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~27_combout = (\z80_|execute_|ctl_mRead~23_combout & (((!\z80_|pla_decode_|Equal38~2_combout & !\z80_|pla_decode_|Equal52~1_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|pla_decode_|Equal38~2_combout ), + .datac(\z80_|execute_|ctl_mRead~23_combout ), + .datad(\z80_|pla_decode_|Equal52~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~27 .lut_mask = 16'h5070; +defparam \z80_|execute_|ctl_mRead~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~26 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~26_combout = (\z80_|execute_|ctl_mRead~34_combout ) # ((\z80_|pla_decode_|Equal21~1_combout ) # (\z80_|pla_decode_|Equal37~0_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|pla_decode_|Equal37~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~26 .lut_mask = 16'hFFFC; +defparam \z80_|execute_|ctl_mRead~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y17_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~28 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~28_combout = (\z80_|execute_|ctl_mRead~27_combout & (\z80_|execute_|ctl_mRead~22_combout & ((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|execute_|ctl_mRead~26_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~27_combout ), + .datab(\z80_|execute_|ctl_mRead~26_combout ), + .datac(\z80_|execute_|ctl_mRead~22_combout ), + .datad(\z80_|execute_|ctl_mRead~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~28 .lut_mask = 16'h20A0; +defparam \z80_|execute_|ctl_mRead~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|nextM~6 ( +// Equation(s): +// \z80_|execute_|nextM~6_combout = (((\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal49~0_combout )) # (!\z80_|execute_|nextM~3_combout )) # (!\z80_|execute_|ixy_d~17_combout ) + + .dataa(\z80_|decode_state_|use_ixiy~combout ), + .datab(\z80_|execute_|ixy_d~17_combout ), + .datac(\z80_|execute_|nextM~3_combout ), + .datad(\z80_|pla_decode_|Equal49~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~6 .lut_mask = 16'hBF3F; +defparam \z80_|execute_|nextM~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N10 +cycloneive_lcell_comb \z80_|execute_|nextM~7 ( +// Equation(s): +// \z80_|execute_|nextM~7_combout = ((\z80_|execute_|nextM~6_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # (\z80_|execute_|ixy_d~8_combout )))) # (!\z80_|execute_|nextM~4_combout ) + + .dataa(\z80_|execute_|nextM~6_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|execute_|ixy_d~8_combout ), + .datad(\z80_|execute_|nextM~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~7 .lut_mask = 16'hA8FF; +defparam \z80_|execute_|nextM~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|nextM~8 ( +// Equation(s): +// \z80_|execute_|nextM~8_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & (((\z80_|execute_|ixy_d~8_combout & !\z80_|execute_|ctl_flags_bus~1_combout )) # (!\z80_|alu_control_|flags_cond_true~q ))) # +// (!\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & (\z80_|execute_|ixy_d~8_combout & ((!\z80_|execute_|ctl_flags_bus~1_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), + .datab(\z80_|execute_|ixy_d~8_combout ), + .datac(\z80_|alu_control_|flags_cond_true~q ), + .datad(\z80_|execute_|ctl_flags_bus~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~8 .lut_mask = 16'h0ACE; +defparam \z80_|execute_|nextM~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|nextM~9 ( +// Equation(s): +// \z80_|execute_|nextM~9_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_mWrite~4_combout & ((\z80_|execute_|ctl_mRead~9_combout ) # (\z80_|execute_|ixy_d~6_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~9_combout ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ctl_mWrite~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~9 .lut_mask = 16'hC800; +defparam \z80_|execute_|nextM~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|nextM~10 ( +// Equation(s): +// \z80_|execute_|nextM~10_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ) # ((\z80_|execute_|nextM~9_combout ) # ((\z80_|execute_|ctl_mRead~34_combout & \z80_|execute_|ixy_d~9_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|execute_|nextM~9_combout ), + .datad(\z80_|execute_|ixy_d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~10 .lut_mask = 16'hFEFA; +defparam \z80_|execute_|nextM~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N20 +cycloneive_lcell_comb \z80_|execute_|nextM~12 ( +// Equation(s): +// \z80_|execute_|nextM~12_combout = (\z80_|execute_|nextM~8_combout ) # ((\z80_|execute_|ctl_alu_op_low~46_combout ) # ((\z80_|execute_|nextM~10_combout ) # (!\z80_|execute_|nextM~11_combout ))) + + .dataa(\z80_|execute_|nextM~8_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~46_combout ), + .datac(\z80_|execute_|nextM~10_combout ), + .datad(\z80_|execute_|nextM~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~12 .lut_mask = 16'hFEFF; +defparam \z80_|execute_|nextM~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|nextM~15 ( +// Equation(s): +// \z80_|execute_|nextM~15_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & ((\z80_|execute_|ctl_mRead~5_combout ) # (!\z80_|execute_|fMRead~12_combout )))) + + .dataa(\z80_|execute_|fMRead~12_combout ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|execute_|ctl_mRead~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~15 .lut_mask = 16'hC040; +defparam \z80_|execute_|nextM~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|nextM~13 ( +// Equation(s): +// \z80_|execute_|nextM~13_combout = (\z80_|execute_|nextM~7_combout ) # ((\z80_|execute_|nextM~12_combout ) # (\z80_|execute_|nextM~15_combout )) + + .dataa(\z80_|execute_|nextM~7_combout ), + .datab(\z80_|execute_|nextM~12_combout ), + .datac(gnd), + .datad(\z80_|execute_|nextM~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~13 .lut_mask = 16'hFFEE; +defparam \z80_|execute_|nextM~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N6 +cycloneive_lcell_comb \z80_|execute_|setM1~41 ( +// Equation(s): +// \z80_|execute_|setM1~41_combout = (\z80_|execute_|setM1~40_combout & !\z80_|execute_|ctl_mWrite~7_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|setM1~40_combout ), + .datac(\z80_|execute_|ctl_mWrite~7_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|setM1~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~41 .lut_mask = 16'h0C0C; +defparam \z80_|execute_|setM1~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|nextM~5 ( +// Equation(s): +// \z80_|execute_|nextM~5_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (((!\z80_|execute_|setM1~41_combout ) # (!\z80_|execute_|setM1~47_combout )) # (!\z80_|execute_|nextM~2_combout ))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|nextM~2_combout ), + .datac(\z80_|execute_|setM1~47_combout ), + .datad(\z80_|execute_|setM1~41_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~5 .lut_mask = 16'h2AAA; +defparam \z80_|execute_|nextM~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N0 +cycloneive_lcell_comb \z80_|execute_|nextM~14 ( +// Equation(s): +// \z80_|execute_|nextM~14_combout = (((\z80_|execute_|nextM~13_combout ) # (\z80_|execute_|nextM~5_combout )) # (!\z80_|execute_|ctl_mWrite~14_combout )) # (!\z80_|execute_|ctl_mRead~28_combout ) + + .dataa(\z80_|execute_|ctl_mRead~28_combout ), + .datab(\z80_|execute_|ctl_mWrite~14_combout ), + .datac(\z80_|execute_|nextM~13_combout ), + .datad(\z80_|execute_|nextM~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~14 .lut_mask = 16'hFFF7; +defparam \z80_|execute_|nextM~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N24 +cycloneive_lcell_comb \z80_|sequencer_|ena_M ( +// Equation(s): +// \z80_|sequencer_|ena_M~combout = (\z80_|execute_|setM1~54_combout & !\z80_|execute_|nextM~14_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|setM1~54_combout ), + .datac(gnd), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|ena_M~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|ena_M .lut_mask = 16'h00CC; +defparam \z80_|sequencer_|ena_M .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y13_N25 +dffeas \z80_|sequencer_|DFFE_T1_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|ena_M~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_T1_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_T1_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_T1_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N20 +cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_13 ( +// Equation(s): +// \z80_|sequencer_|SYNTHESIZED_WIRE_13~combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|execute_|setM1~54_combout & !\z80_|execute_|nextM~14_combout )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|execute_|setM1~54_combout ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_13 .lut_mask = 16'h0030; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y13_N21 +dffeas \z80_|sequencer_|DFFE_T2_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_T2_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_T2_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_T2_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N16 +cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_14 ( +// Equation(s): +// \z80_|sequencer_|SYNTHESIZED_WIRE_14~combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|execute_|setM1~54_combout & !\z80_|execute_|nextM~14_combout )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|execute_|setM1~54_combout ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_14 .lut_mask = 16'h00C0; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y13_N17 +dffeas \z80_|sequencer_|DFFE_T3_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_T3_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_T3_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_T3_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout = (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 .lut_mask = 16'h0F00; +defparam \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_66_oe~2 ( +// Equation(s): +// \z80_|execute_|ctl_66_oe~2_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|execute_|comb~0_combout & \z80_|ir_|opcode [0]))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|pla_decode_|Equal52~0_combout ), + .datac(\z80_|execute_|comb~0_combout ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_66_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_66_oe~2 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_66_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y17_N11 +dffeas \z80_|interrupts_|im1 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_im_we~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|interrupts_|im1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|interrupts_|im1 .is_wysiwyg = "true"; +defparam \z80_|interrupts_|im1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_ff_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_bus_ff_oe~0_combout = (\z80_|interrupts_|DFFE_inst44~q & ((\z80_|interrupts_|im1~q ) # ((\z80_|interrupts_|im2~q & !\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) + + .dataa(\z80_|interrupts_|DFFE_inst44~q ), + .datab(\z80_|interrupts_|im2~q ), + .datac(\z80_|interrupts_|im1~q ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_ff_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_ff_oe~0 .lut_mask = 16'hA0A8; +defparam \z80_|execute_|ctl_bus_ff_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_ff_oe~1 ( +// Equation(s): +// \z80_|execute_|ctl_bus_ff_oe~1_combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) # (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|execute_|ctl_bus_ff_oe~0_combout & +// ((\z80_|execute_|ctl_66_oe~2_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) + + .dataa(\z80_|execute_|ctl_66_oe~2_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datad(\z80_|execute_|ctl_bus_ff_oe~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_ff_oe~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_ff_oe~1 .lut_mask = 16'h3B30; +defparam \z80_|execute_|ctl_bus_ff_oe~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_zero_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_bus_zero_oe~0_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_iorw~10_combout ) # (\z80_|execute_|ctl_alu_op_low~27_combout )))) + + .dataa(\z80_|pla_decode_|Equal33~1_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_iorw~10_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_zero_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_zero_oe~0 .lut_mask = 16'h8880; +defparam \z80_|execute_|ctl_bus_zero_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N18 +cycloneive_lcell_comb \z80_|bus_control_|db[0]~4 ( +// Equation(s): +// \z80_|bus_control_|db[0]~4_combout = (\z80_|execute_|ctl_bus_ff_oe~1_combout ) # ((!\z80_|execute_|ctl_bus_zero_oe~0_combout & ((\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) # (!\z80_|decode_state_|in_halt~q )))) + + .dataa(\z80_|execute_|ctl_bus_ff_oe~1_combout ), + .datab(\z80_|execute_|ctl_bus_zero_oe~0_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|decode_state_|in_halt~q ), + .cin(gnd), + .combout(\z80_|bus_control_|db[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[0]~4 .lut_mask = 16'hBABB; +defparam \z80_|bus_control_|db[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N24 +cycloneive_lcell_comb \z80_|bus_control_|db[6]~8 ( +// Equation(s): +// \z80_|bus_control_|db[6]~8_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[6]~22_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) + + .dataa(\z80_|bus_control_|db[0]~4_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datad(\z80_|alu_control_|db[6]~22_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[6]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[6]~8 .lut_mask = 16'hAA0A; +defparam \z80_|bus_control_|db[6]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y7_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a22 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~79_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_first_bit_number = 6; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y8_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a30 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~79_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_first_bit_number = 6; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y11_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a14 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~79_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y10_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a6 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~79_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N16 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ) # +// ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout & +// !\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12 .lut_mask = 16'hF0AC; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y10_N22 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13_combout = (\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout & (((\ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout & +// ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout ), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13 .lut_mask = 16'hCAF0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y1_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a6 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h3C766E63DB6481CB39BC8C68831C724633186CC1BAE9D608A5DEF0FF219C28C1EFF4FDE394D0E19B6FD89186C23CF071E6F1CC8F7FC4F1E48756B0DCD8ED6D0C3DA139003D7A86B2F878DD99DAFB70DE1A19F3FB7DB3B8EF2633007664CB19992E43664448EFF06072648DBA32EDB76E26439BCCEF2DFBF664594B04FBAE72A84A3E508B49DC6BEAAB4F3F0CCCF6D8F568F2DA00EB384A7F53249323198000100408002024010408824080002008011482ED5615E40012EE630C3B2CDB2C13A736DB5B7BD2850018CF936621C6863095A73F7BE7442CB13110B9C0BBB96EEF16CE618EEDCFB393738178C476C367909F71307F6803F677575763DB2D8C3118E4; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h881331ED7AC4EFD38DFACDBB236790005719AEA2FAECCF0D126A30A27222D61BBA428334561F4EDB60C6BF8DB6E267BC56CB69BBCE636CCCB3B2B4B103CC46D5CEEC06DAECB0001569589D5F267AFE086C8FED5DE41DFEFF027DFDFF7FFBFBFDFFDFFF6FFFBDFFDFFF57FF7F7FB7FBBDFBDFFDBFF78FFDBFFEDDFFFDFFFEFF6FF7F7FDDFFEDFF6FF7FFEEFFEFEFC4E51EC0888848E1F2044B47B66608D8A3B3919B9466E6D60D27565964244B218B48AD83430D996068EC908D9E112096996041D77401A0C0CCF5DEEE561F7F7E68CBE72E48E570B047C772CBACC33753080E32EB0B348C0B62337739B1BC73192392592C84E37B7AC141CFE65EE76D83C9083; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h1C5CF062CA6F13854A59BDEEEA07E3C6559EBB3618111895CBBACCBCD512B5F07D361CCE72B925658DBE1F7C4707E195C5C665B8118C3C31B196C261DA85A5E11889D25CB816ACC6627802052C61A4099B7B0EC923971DB3B9F9204BDBCCFA457EE296E8986E64C6DC99E59436641567648CB84DEB7D7937F974F038D838274F3D3CF1BE8C84DDB000565880A776E5C0E13166E49F47119A4CA1311CF97B965E7CBBCB2CB384BD0D92ED105D0617856E80441124B31DE58B8C001607FEE668899693E3EFF8FBF1FCEEFBCF7CF9BA6C37640DDF7FFE6187B19ACF089D4C038F6607B78D38001FE67E56CCE399DE36D7DDBD699D5CFC5B6D7A1421CE06FE40DB6E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h0776C62C316FF94B0BC3A0288DE6A62B14D6C1A2DADF9BDF85B2CCB02CE1DB2D96632C3232C3974CDC1172E1779D8C6738251819975DB8146067301E0C0277B6B657485DCD62AC0662C8C005DDE7494C9CA13AAE3234BB0EE1B708A23A2F48AC4C3838641E940620F9CDDCCA14BCC07104C112BCC9032C48E925594CB886A604C9F7627EB100872A52FB5141D65111E6C8DA0ADB6CEC6004461D0E366B20DCCDB607E624499300E4DF6D95CB62F62FB75403E400EFBC3BD34080FC9CDCFCFCFFFFFFFFFFFFFFFFFFFFF7BFFFFFFFFFFFFFFFFFFFFFFFFFFFCF9FFFFFEFFFF81FFDDFFFFFFFFFFFFFF7FFBFFFBFDC0A6DBE6F8BE5BB7FE7A39B3DA3F3BE13B679; +// synopsys translate_on + +// Location: M9K_X22_Y4_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a14 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h4200420000441C443C0C3C00480018FC387C7C000000007E180038300000204880084204004204423E1E3E02247E3C7E3C7E7E7E7E30007E3C7E7E7E3C7E7C3C0400000000000C34023C2E302464003C00000000000000000020460024000000FF991E65536D2D8D9C9B4DB081C83A5A881B0DFDE2D72DF0FA08FCD6F664173D989098D02025E0F6043B4B9080F4923880C3A3B02D269E730C3DCC423386DCB98B4AD0C5C8D6119602E5121008325B7457090E914F4876EC8A18C664210A4C2392C7658400073421047C75FBE7BE73FDFFF05FEE07BF8AEF7F1378B359E8C61F8F692C2218C98A4A8748531986E7C770D984E0000C02060C000C0DF50F68A580; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h0100046606572583002086010800054C0F2DE8371AC0000A9003E024840C7C0806F6612D770080980A40D293FEC069F16CB2164CA033C539F69B37741AEF1CE3662FF5DF9CB107BB23A39EF7B95E7372200448DBDC18F9C0DE0EF379BF49480657781E91788044213E091339886F337D0612CA646CD48FC58EE77EDD7ECEC466C744FD00E1A7F9E9FBFE4777FD50ABD11F0E57FF4808802282200888A20AA88000000008800AC11D556264251ECFA68C056FBCCB040C614A6850222300D2F6FF59F878FCF5689FCFEF34BFD52FA2422A56A3C113409F7813007F8D6B5F80FE9D7FB1E62675F7C2CBE01032DCA16BADC570C1CBF7ECBC4E7E6C54A5D4550BE1A8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'hE33CB578DEBFAFAEDFD530DE8FA1992072F31B116644B18C72F9F44116C79ADF2F3982C7BE09AD4A32196807648A2495ADF98FD2B16CC096A5E25F5BC811C953CEC3000F432029B3FE3F211712944CA54D1940F193204C199C9F49666CC11B38C23B9D130CA49818913D3A2C1FBF71C5B0C774336F903C677D976189D98CA127AAAD6B6AF36195DA637C6EFA3E36E8FE97FA02EC26EB46198AD8DAD8C11260AF499D7BD86619EE5574CD27C80D39F71E653FDCF1B366737233CBB98D1E7B330F7DCCFC5939C4EC79CF0E1CD43BA7AFC716900A21BDB9DD0FCC7ECE1063238407C7E1B221EA10E38F64EF31CEBF3368E1C712BB1B33781134CFE54C2123349A6E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h5F9CB25A3631964C20007FF5754FC631A97D4F93986C30CF24394625658DE9A7C228A2050470925E29A35D8D06242712CD25C9241898204D85A710947C802013E1265727652C8F0C422BA8C28A0FBB893B0881E00403DDD8843B2D8EB929D0D8CB76E03779E019E2C4E4028219C38C202C9384E0D24E569C2E4D4D60B670CE37414D536A41D144B6C4624A2B00366D8CF6734A4A2DC465B308462CCBD1BF9CB863FC93EDB2CA5DC61B01639318985C88F01680E307C42311C0124700B28BF9B4FF7CCCEFE1996DE3ED6D8CFBF1871BD98EE7646242664EB2E338BD009838637124C921BB3332DC66D9C1706B6C48C3129639A3BA4088EDB496EDBBBFC2CC40B6; +// synopsys translate_on + +// Location: M9K_X22_Y23_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a14 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(gnd), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~79_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_first_bit_number = 6; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y26_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a6 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~79_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_first_bit_number = 6; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFFFFFEBFFFFFFFFFFFFFFFFFFFFFFFBFFFFFFFFFFFFFFFFFDFFFFFFFFFFFFFBFFFFFFFFFEFFFFFFFDFFFFFFFFFFFFFEFFFFFFFDF8FFFFFFF9FFFFFFFFFFFFFFFF3FFFFFFE7FFFFFFFFFFFFFFFF; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000380001887600094C977486989000000000000000000000000FFFFFFFFC0810205C00018C36DC09CF97749EDCD00000000000000000000000000000001FFFFFFFDC004000B6D028BF17749ED8100000000000000000000000000000001BF7EFDF9400404A96D8289B57549FFC10000000000000000000000003F7EFDF90000000140041EB16D8298357DC9F7410000000000000000000000007FFFFFFD8000000340043AB160021E757DC9134100000000000000000000000040810207BFFFFFFF5FE430497702760D60099349000000000000000000000000408102073FFFFFFD5FE40E49774240C96009735D; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h5FE8334948F827C15FF88F8169A80ECB609EAD417A698FC178F33E8171F72A915FE836E948F807C95FF88F81E9A80FC7639E1FC17B2BBEC170730F8D70F7B0C1400826E548B807C95FF88F95E8280FCB63C6BCC17B3B3FC171AB3E81708734C1400826ED58F8258159F88B8168280FC161629DC17A3B3F41738B3F8150AF16E9400826ED581805C151D88A8160682FC1422297C17A2A39C162FB378550CF10A1400826ED58182581D1580B8761EC2FC14232B7C179AA39C5627B7781D0CF10D3400826E158182D81F0488A4B61EC0DC143789FC17BBB39C1610B7F81D45F11D34008A7E958080D01F0088A4160B42DD143689FC17B9B398561837F81D41702B1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h50DF086350368F0151C688016801460157EDE81148F310013FFFFFFF40810103D2D70D4B50168F0141D6C8116C01462153EDA90148F31D01BFFFFFFF40810107D2D7296354D68501403EC0016C01482173FDA08148F11F01800000037FFFFFFD4297893154DE81054022D2116C014D6153FCA00148D10F01000000013F7EFEF9429F810150CEC10143E042016C014C09537DA00148D11F01BF7EFEF900000001469F833150168D0543E04A116F014DA15379B181C8511F03FFFFFFFD00000001449AAB2155368D01482046016F416CA15079B001C8513E03C0810105FFFFFFFF403A8B0155C685014800461167476CA15039B08180413E0500000007FFFFFFFF; +// synopsys translate_on + +// Location: LCCOMB_X24_Y10_N16 +cycloneive_lcell_comb \Selector6~0 ( +// Equation(s): +// \Selector6~0_combout = (\z80_|address_pins_|abus[14]~23_combout & ((\Selector3~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout )) # (!\Selector3~0_combout & +// ((\ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ))))) # (!\z80_|address_pins_|abus[14]~23_combout & (\Selector3~0_combout )) + + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\Selector3~0_combout ), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ), + .cin(gnd), + .combout(\Selector6~0_combout ), + .cout()); +// synopsys translate_off +defparam \Selector6~0 .lut_mask = 16'hE6C4; +defparam \Selector6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y10_N18 +cycloneive_lcell_comb \Selector6~1 ( +// Equation(s): +// \Selector6~1_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\Selector6~0_combout )))) # (!\z80_|address_pins_|abus[14]~23_combout & ((\Selector6~0_combout & ((\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ))) # +// (!\Selector6~0_combout & (\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout )))) + + .dataa(\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ), + .datab(\z80_|address_pins_|abus[14]~23_combout ), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .datad(\Selector6~0_combout ), + .cin(gnd), + .combout(\Selector6~1_combout ), + .cout()); +// synopsys translate_off +defparam \Selector6~1 .lut_mask = 16'hFC22; +defparam \Selector6~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y10_N4 +cycloneive_lcell_comb \D[6]~88 ( +// Equation(s): +// \D[6]~88_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\Selector6~1_combout +// ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13_combout )))) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13_combout ), + .datad(\Selector6~1_combout ), + .cin(gnd), + .combout(\D[6]~88_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~88 .lut_mask = 16'hF4B0; +defparam \D[6]~88 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X16_Y34_N8 +cycloneive_io_ibuf \raw_loader_in~input ( + .i(raw_loader_in), + .ibar(gnd), + .o(\raw_loader_in~input_o )); +// synopsys translate_off +defparam \raw_loader_in~input .bus_hold = "false"; +defparam \raw_loader_in~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y10_N24 +cycloneive_lcell_comb \D[6]~69 ( +// Equation(s): +// \D[6]~69_combout = ((\z80_|address_pins_|DFFE_apin_latch [0]) # (\raw_loader_in~input_o )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [0]), + .datad(\raw_loader_in~input_o ), + .cin(gnd), + .combout(\D[6]~69_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~69 .lut_mask = 16'hFFF3; +defparam \D[6]~69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y10_N0 +cycloneive_lcell_comb \D[6]~78 ( +// Equation(s): +// \D[6]~78_combout = ((\Equal2~0_combout & ((\D[6]~69_combout ))) # (!\Equal2~0_combout & (\D[6]~88_combout ))) # (!\Equal2~1_combout ) + + .dataa(\Equal2~0_combout ), + .datab(\Equal2~1_combout ), + .datac(\D[6]~88_combout ), + .datad(\D[6]~69_combout ), + .cin(gnd), + .combout(\D[6]~78_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~78 .lut_mask = 16'hFB73; +defparam \D[6]~78 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y10_N6 +cycloneive_lcell_comb \D[6]~79 ( +// Equation(s): +// \D[6]~79_combout = (\z80_|pin_control_|bus_db_pin_oe~15_combout & (\z80_|data_pins_|dout [6] & ((\D[6]~78_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout & (((\D[6]~78_combout ) # (!\Equal2~1_combout )))) + + .dataa(\z80_|data_pins_|dout [6]), + .datab(\Equal2~1_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .datad(\D[6]~78_combout ), + .cin(gnd), + .combout(\D[6]~79_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~79 .lut_mask = 16'hAF03; +defparam \D[6]~79 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N18 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [6] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[6]~9_combout ) # ((\z80_|pin_control_|bus_db_pin_re~combout & \D[6]~79_combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & +// (\z80_|pin_control_|bus_db_pin_re~combout & (\D[6]~79_combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datab(\z80_|pin_control_|bus_db_pin_re~combout ), + .datac(\D[6]~79_combout ), + .datad(\z80_|bus_control_|db[6]~9_combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [6]), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] .lut_mask = 16'hEAC0; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y13_N19 +dffeas \z80_|data_pins_|dout[6] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [6]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|data_pins_|dout [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|data_pins_|dout[6] .is_wysiwyg = "true"; +defparam \z80_|data_pins_|dout[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N6 +cycloneive_lcell_comb \z80_|bus_control_|db[6]~9 ( +// Equation(s): +// \z80_|bus_control_|db[6]~9_combout = ((\z80_|bus_control_|db[6]~8_combout & ((\z80_|data_pins_|dout [6]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) + + .dataa(\z80_|bus_control_|db[0]~6_combout ), + .datab(\z80_|bus_control_|db[6]~8_combout ), + .datac(\z80_|data_pins_|dout [6]), + .datad(\z80_|execute_|ctl_bus_db_oe~combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[6]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[6]~9 .lut_mask = 16'hD5DD; +defparam \z80_|bus_control_|db[6]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y13_N7 +dffeas \z80_|ir_|opcode[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|bus_control_|db[6]~9_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|ir_|opcode [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|ir_|opcode[6] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~10 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~10_combout = (!\z80_|ir_|opcode [6] & (\z80_|ir_|opcode [7] & (\z80_|execute_|ctl_ir_we~5_combout & !\z80_|pla_decode_|Equal46~0_combout ))) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|execute_|ctl_ir_we~5_combout ), + .datad(\z80_|pla_decode_|Equal46~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~10 .lut_mask = 16'h0040; +defparam \z80_|execute_|ctl_ir_we~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~0_combout = (\z80_|execute_|ctl_alu_bs_oe~6_combout & (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~7_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~10_combout ), + .datab(\z80_|execute_|ctl_ir_we~7_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~6_combout ), + .datad(\z80_|execute_|ctl_ir_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~0 .lut_mask = 16'h10F0; +defparam \z80_|execute_|ctl_bus_db_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~4 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~4_combout = (!\z80_|execute_|ctl_bus_db_oe~3_combout ) # (!\z80_|execute_|ctl_bus_db_oe~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_bus_db_oe~0_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~4 .lut_mask = 16'h0FFF; +defparam \z80_|execute_|ctl_bus_db_oe~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~2 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~2_combout = (!\z80_|execute_|ctl_bus_ff_oe~1_combout & (!\z80_|execute_|ctl_bus_zero_oe~0_combout & ((\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) # (!\z80_|decode_state_|in_halt~q )))) + + .dataa(\z80_|execute_|ctl_bus_ff_oe~1_combout ), + .datab(\z80_|execute_|ctl_bus_zero_oe~0_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|decode_state_|in_halt~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~2 .lut_mask = 16'h1011; +defparam \z80_|execute_|ctl_bus_db_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y17_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~5 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~5_combout = (\z80_|execute_|ctl_ir_we~8_combout ) # ((\z80_|pla_decode_|Equal41~2_combout ) # ((\z80_|execute_|ctl_ir_we~14_combout ) # (\z80_|execute_|ctl_ir_we~11_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|pla_decode_|Equal41~2_combout ), + .datac(\z80_|execute_|ctl_ir_we~14_combout ), + .datad(\z80_|execute_|ctl_ir_we~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~5 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_bus_db_oe~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~6 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~6_combout = ((\z80_|execute_|ctl_66_oe~2_combout ) # ((\z80_|execute_|ctl_bus_db_oe~5_combout & \z80_|execute_|ctl_ir_we~4_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|execute_|ctl_bus_db_oe~5_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|execute_|ctl_66_oe~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~6 .lut_mask = 16'hFFD5; +defparam \z80_|execute_|ctl_bus_db_oe~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~combout = (\z80_|execute_|ctl_bus_db_oe~2_combout & ((\z80_|execute_|ctl_bus_db_oe~4_combout ) # ((\z80_|execute_|ctl_bus_db_oe~6_combout ) # (!\z80_|execute_|ctl_sw_1d~6_combout )))) + + .dataa(\z80_|execute_|ctl_bus_db_oe~4_combout ), + .datab(\z80_|execute_|ctl_bus_db_oe~2_combout ), + .datac(\z80_|execute_|ctl_sw_1d~6_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe .lut_mask = 16'hCC8C; +defparam \z80_|execute_|ctl_bus_db_oe .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N14 +cycloneive_lcell_comb \z80_|bus_control_|db[0]~6 ( +// Equation(s): +// \z80_|bus_control_|db[0]~6_combout = (\z80_|execute_|ctl_bus_db_oe~combout ) # ((\z80_|execute_|ctl_bus_db_we~7_combout ) # (!\z80_|execute_|ctl_bus_db_oe~2_combout )) + + .dataa(\z80_|execute_|ctl_bus_db_oe~combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~2_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[0]~6 .lut_mask = 16'hFAFF; +defparam \z80_|bus_control_|db[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~61 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][2]~61_combout = (\ula_|zx_keyboard_|keys[7][2]~60_combout & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|zx_keyboard_|keys[7][2]~60_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][2]~61_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2]~61 .lut_mask = 16'h2000; +defparam \ula_|zx_keyboard_|keys[7][2]~61 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~63 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][2]~63_combout = (\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[7][2]~61_combout ) # ((\ula_|zx_keyboard_|keys[5][4]~62_combout & \ula_|zx_keyboard_|keys[7][2]~30_combout )))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|zx_keyboard_|keys[7][2]~61_combout ), + .datac(\ula_|zx_keyboard_|keys[5][4]~62_combout ), + .datad(\ula_|zx_keyboard_|keys[7][2]~30_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][2]~63_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2]~63 .lut_mask = 16'hA888; +defparam \ula_|zx_keyboard_|keys[7][2]~63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~64 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][2]~64_combout = (\ula_|zx_keyboard_|keys[0][0]~13_combout & (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|keys[7][2]~63_combout & !\ula_|zx_keyboard_|extended~q ))) + + .dataa(\ula_|zx_keyboard_|keys[0][0]~13_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|zx_keyboard_|keys[7][2]~63_combout ), + .datad(\ula_|zx_keyboard_|extended~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][2]~64_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2]~64 .lut_mask = 16'h0020; +defparam \ula_|zx_keyboard_|keys[7][2]~64 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~65 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][2]~65_combout = (\ula_|zx_keyboard_|keys[7][2]~64_combout & (!\ula_|zx_keyboard_|Selector13~0_combout )) # (!\ula_|zx_keyboard_|keys[7][2]~64_combout & ((\ula_|zx_keyboard_|keys[7][2]~q ))) + + .dataa(\ula_|zx_keyboard_|Selector13~0_combout ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[7][2]~q ), + .datad(\ula_|zx_keyboard_|keys[7][2]~64_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][2]~65_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2]~65 .lut_mask = 16'h55F0; +defparam \ula_|zx_keyboard_|keys[7][2]~65 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y9_N5 +dffeas \ula_|zx_keyboard_|keys[7][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[7][2]~65_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[7][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[7][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~67 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][2]~67_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [4])) # (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [1] & +// !\ula_|ps2_keyboard_|shiftreg [4])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][2]~67_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][2]~67 .lut_mask = 16'h2244; +defparam \ula_|zx_keyboard_|keys[6][2]~67 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~68 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][2]~68_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[6][2]~67_combout & (\ula_|ps2_keyboard_|shiftreg [4] $ (!\ula_|ps2_keyboard_|shiftreg [2])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|zx_keyboard_|keys[6][2]~67_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][2]~68_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][2]~68 .lut_mask = 16'h2100; +defparam \ula_|zx_keyboard_|keys[6][2]~68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~69 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][2]~69_combout = (\ula_|zx_keyboard_|keys[6][1]~39_combout & ((\ula_|zx_keyboard_|keys[6][2]~68_combout & (!\ula_|zx_keyboard_|keys[5][0]~66_combout )) # (!\ula_|zx_keyboard_|keys[6][2]~68_combout & +// ((\ula_|zx_keyboard_|keys[6][2]~q ))))) # (!\ula_|zx_keyboard_|keys[6][1]~39_combout & (((\ula_|zx_keyboard_|keys[6][2]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][0]~66_combout ), + .datab(\ula_|zx_keyboard_|keys[6][1]~39_combout ), + .datac(\ula_|zx_keyboard_|keys[6][2]~q ), + .datad(\ula_|zx_keyboard_|keys[6][2]~68_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][2]~69_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][2]~69 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[6][2]~69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y8_N11 +dffeas \ula_|zx_keyboard_|keys[6][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[6][2]~69_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[6][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[6][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N12 +cycloneive_lcell_comb \D[2]~36 ( +// Equation(s): +// \D[2]~36_combout = (\ula_|zx_keyboard_|keys[7][2]~q & (\z80_|address_pins_|abus[15]~22_combout & ((\z80_|address_pins_|abus[14]~23_combout ) # (!\ula_|zx_keyboard_|keys[6][2]~q )))) # (!\ula_|zx_keyboard_|keys[7][2]~q & +// (((\z80_|address_pins_|abus[14]~23_combout )) # (!\ula_|zx_keyboard_|keys[6][2]~q ))) + + .dataa(\ula_|zx_keyboard_|keys[7][2]~q ), + .datab(\ula_|zx_keyboard_|keys[6][2]~q ), + .datac(\z80_|address_pins_|abus[14]~23_combout ), + .datad(\z80_|address_pins_|abus[15]~22_combout ), + .cin(gnd), + .combout(\D[2]~36_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~36 .lut_mask = 16'hF351; +defparam \D[2]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~58 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][2]~58_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [1]))) # (!\ula_|ps2_keyboard_|shiftreg [6] & +// (!\ula_|zx_keyboard_|extended~q & (\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|zx_keyboard_|extended~q ), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][2]~58_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][2]~58 .lut_mask = 16'h1008; +defparam \ula_|zx_keyboard_|keys[4][2]~58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~130 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][2]~130_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|zx_keyboard_|keys[4][2]~58_combout & (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [0]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|zx_keyboard_|keys[4][2]~58_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][2]~130_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][2]~130 .lut_mask = 16'h0080; +defparam \ula_|zx_keyboard_|keys[4][2]~130 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~59 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][2]~59_combout = (\ula_|zx_keyboard_|keys[3][4]~129_combout & ((\ula_|zx_keyboard_|keys[4][2]~130_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[4][2]~130_combout & ((\ula_|zx_keyboard_|keys[4][2]~q +// ))))) # (!\ula_|zx_keyboard_|keys[3][4]~129_combout & (((\ula_|zx_keyboard_|keys[4][2]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[3][4]~129_combout ), + .datac(\ula_|zx_keyboard_|keys[4][2]~q ), + .datad(\ula_|zx_keyboard_|keys[4][2]~130_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][2]~59_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][2]~59 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[4][2]~59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y8_N25 +dffeas \ula_|zx_keyboard_|keys[4][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[4][2]~59_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[4][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[4][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~56 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][2]~56_combout = (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [2]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][2]~56_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][2]~56 .lut_mask = 16'h00F0; +defparam \ula_|zx_keyboard_|keys[5][2]~56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~57 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][2]~57_combout = (\ula_|zx_keyboard_|keys[5][2]~56_combout & ((\ula_|zx_keyboard_|keys[5][2]~31_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[5][2]~31_combout & ((\ula_|zx_keyboard_|keys[5][2]~q +// ))))) # (!\ula_|zx_keyboard_|keys[5][2]~56_combout & (((\ula_|zx_keyboard_|keys[5][2]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][2]~56_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[5][2]~q ), + .datad(\ula_|zx_keyboard_|keys[5][2]~31_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][2]~57_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][2]~57 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[5][2]~57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y10_N19 +dffeas \ula_|zx_keyboard_|keys[5][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[5][2]~57_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[5][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[5][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N24 +cycloneive_lcell_comb \D[2]~35 ( +// Equation(s): +// \D[2]~35_combout = (\z80_|address_pins_|abus[13]~20_combout & (((\z80_|address_pins_|abus[12]~21_combout )) # (!\ula_|zx_keyboard_|keys[4][2]~q ))) # (!\z80_|address_pins_|abus[13]~20_combout & (!\ula_|zx_keyboard_|keys[5][2]~q & +// ((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][2]~q )))) + + .dataa(\z80_|address_pins_|abus[13]~20_combout ), + .datab(\ula_|zx_keyboard_|keys[4][2]~q ), + .datac(\z80_|address_pins_|abus[12]~21_combout ), + .datad(\ula_|zx_keyboard_|keys[5][2]~q ), + .cin(gnd), + .combout(\D[2]~35_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~35 .lut_mask = 16'hA2F3; +defparam \D[2]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][2]~54 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][2]~54_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [2]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][2]~54_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][2]~54 .lut_mask = 16'h000F; +defparam \ula_|zx_keyboard_|keys[0][2]~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][2]~55 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][2]~55_combout = (\ula_|zx_keyboard_|keys[7][4]~49_combout & ((\ula_|zx_keyboard_|keys[0][2]~54_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[0][2]~54_combout & ((\ula_|zx_keyboard_|keys[0][2]~q +// ))))) # (!\ula_|zx_keyboard_|keys[7][4]~49_combout & (((\ula_|zx_keyboard_|keys[0][2]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[7][4]~49_combout ), + .datac(\ula_|zx_keyboard_|keys[0][2]~q ), + .datad(\ula_|zx_keyboard_|keys[0][2]~54_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][2]~55_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][2]~55 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[0][2]~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y7_N19 +dffeas \ula_|zx_keyboard_|keys[0][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[0][2]~55_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[0][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[0][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][2]~50 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][2]~50_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [2]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][2]~50_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][2]~50 .lut_mask = 16'h0F00; +defparam \ula_|zx_keyboard_|keys[3][2]~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][2]~51 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][2]~51_combout = (\ula_|zx_keyboard_|keys[3][2]~50_combout & ((\ula_|zx_keyboard_|keys[7][4]~49_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[7][4]~49_combout & (\ula_|zx_keyboard_|keys[3][2]~q +// )))) # (!\ula_|zx_keyboard_|keys[3][2]~50_combout & (((\ula_|zx_keyboard_|keys[3][2]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[3][2]~50_combout ), + .datab(\ula_|zx_keyboard_|keys[7][4]~49_combout ), + .datac(\ula_|zx_keyboard_|keys[3][2]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][2]~51_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][2]~51 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[3][2]~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y7_N15 +dffeas \ula_|zx_keyboard_|keys[3][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[3][2]~51_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[3][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[3][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][2]~52 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][2]~52_combout = (\ula_|zx_keyboard_|Equal0~2_combout & (\ula_|zx_keyboard_|keys[7][4]~17_combout & (\ula_|zx_keyboard_|keys[3][2]~50_combout & !\ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|zx_keyboard_|Equal0~2_combout ), + .datab(\ula_|zx_keyboard_|keys[7][4]~17_combout ), + .datac(\ula_|zx_keyboard_|keys[3][2]~50_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][2]~52_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][2]~52 .lut_mask = 16'h0080; +defparam \ula_|zx_keyboard_|keys[2][2]~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][2]~53 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][2]~53_combout = (\ula_|zx_keyboard_|keys[2][2]~52_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[2][2]~52_combout & ((\ula_|zx_keyboard_|keys[2][2]~q ))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[2][2]~q ), + .datad(\ula_|zx_keyboard_|keys[2][2]~52_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][2]~53_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][2]~53 .lut_mask = 16'h55F0; +defparam \ula_|zx_keyboard_|keys[2][2]~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y7_N25 +dffeas \ula_|zx_keyboard_|keys[2][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[2][2]~53_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[2][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[2][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N8 +cycloneive_lcell_comb \D[2]~33 ( +// Equation(s): +// \D[2]~33_combout = (\ula_|zx_keyboard_|keys[3][2]~q & (\z80_|address_pins_|abus[11]~19_combout & ((\z80_|address_pins_|abus[10]~24_combout ) # (!\ula_|zx_keyboard_|keys[2][2]~q )))) # (!\ula_|zx_keyboard_|keys[3][2]~q & +// (((\z80_|address_pins_|abus[10]~24_combout )) # (!\ula_|zx_keyboard_|keys[2][2]~q ))) + + .dataa(\ula_|zx_keyboard_|keys[3][2]~q ), + .datab(\ula_|zx_keyboard_|keys[2][2]~q ), + .datac(\z80_|address_pins_|abus[11]~19_combout ), + .datad(\z80_|address_pins_|abus[10]~24_combout ), + .cin(gnd), + .combout(\D[2]~33_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~33 .lut_mask = 16'hF531; +defparam \D[2]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][2]~47 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][2]~47_combout = (\ula_|zx_keyboard_|keys[6][4]~45_combout & (\ula_|zx_keyboard_|keys[6][4]~46_combout & !\ula_|ps2_keyboard_|shiftreg [4])) + + .dataa(\ula_|zx_keyboard_|keys[6][4]~45_combout ), + .datab(\ula_|zx_keyboard_|keys[6][4]~46_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][2]~47_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][2]~47 .lut_mask = 16'h0808; +defparam \ula_|zx_keyboard_|keys[1][2]~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][2]~48 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][2]~48_combout = (\ula_|zx_keyboard_|keys[1][2]~47_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[1][2]~47_combout & (\ula_|zx_keyboard_|keys[1][2]~q )) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|keys[1][2]~47_combout ), + .datac(\ula_|zx_keyboard_|keys[1][2]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][2]~48_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][2]~48 .lut_mask = 16'h30FC; +defparam \ula_|zx_keyboard_|keys[1][2]~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y7_N7 +dffeas \ula_|zx_keyboard_|keys[1][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[1][2]~48_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[1][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[1][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~1 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row~1_combout = (\z80_|address_pins_|DFFE_apin_latch [9]) # ((!\ula_|zx_keyboard_|keys[1][2]~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [9]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\ula_|zx_keyboard_|keys[1][2]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row~1 .lut_mask = 16'hCFFF; +defparam \ula_|zx_keyboard_|key_row~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N4 +cycloneive_lcell_comb \D[2]~34 ( +// Equation(s): +// \D[2]~34_combout = (\D[2]~33_combout & (\ula_|zx_keyboard_|key_row~1_combout & ((\z80_|address_pins_|abus[8]~18_combout ) # (!\ula_|zx_keyboard_|keys[0][2]~q )))) + + .dataa(\z80_|address_pins_|abus[8]~18_combout ), + .datab(\ula_|zx_keyboard_|keys[0][2]~q ), + .datac(\D[2]~33_combout ), + .datad(\ula_|zx_keyboard_|key_row~1_combout ), + .cin(gnd), + .combout(\D[2]~34_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~34 .lut_mask = 16'hB000; +defparam \D[2]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N28 +cycloneive_lcell_comb \D[2]~37 ( +// Equation(s): +// \D[2]~37_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[2]~36_combout & (\D[2]~35_combout & \D[2]~34_combout ))) + + .dataa(\D[2]~36_combout ), + .datab(\D[2]~35_combout ), + .datac(\D[2]~34_combout ), + .datad(\z80_|address_pins_|abus[0]~16_combout ), + .cin(gnd), + .combout(\D[2]~37_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~37 .lut_mask = 16'hFF80; +defparam \D[2]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y6_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a18 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[2]~39_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_first_bit_number = 2; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y9_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a2 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[2]~39_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024; +// synopsys translate_on + +// Location: M9K_X22_Y12_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a10 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[2]~39_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N26 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2 .lut_mask = 16'hDC98; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y5_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a26 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[2]~39_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_first_bit_number = 2; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N8 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~3 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~3_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout & +// ((\ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout )))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~3_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~3 .lut_mask = 16'hF838; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y3_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a10 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h8102080042447C443C0C3C402004FC1838787840407A00707C02487E444878428008004042460424402040024A3242124220044022404208520A4A24424A125A0A1028440000524A0A4A4A204A5240460800100010540042002064547E0600001FA9BE02B828694B8A82CB8C8158226808198E9EC6B021F07A2098D5E0ECB639D2B1908129B6A2D646516192D87593189D8B2B26CD6E16234C1CC90AD9831EBD89EAD271ECC39A80507716BB49626B743DFFCF99576C3FAC889860E46618ACB79EC30EEDE42EB1E31F3976CA23243179FAA96DCD66D51535351770D410DC8531866136E6184518410368288C446EC63A4FEE425019C244097049C2B2DC8D93C4; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'hA111466C9493A2A7CA2204102414CC798BF0EEC2995A4814580BD07585585ED92E5172E82E845070000A846100500E84EA1803B8B07B99E1DC75BE6419674597B38F54EB9091AE3320201EE395AD63902282A031CE3E87CC902954AA515D5D6B6A855EC94CFEC4E0172C59A7D054F8F9F4356C312C204E40B05E2059407C8DC84683814663FB910969D1D631A952B381B7F635A33FD38D5CF15DF47D057F7FF555B555C2278100000A24804D7D98EB98602733818A12094F281287422CB40002464C92242004E0AE8518E001D124A7628010115D23C30462FC00A014A12133582A191E00538FC8A5004036A959ACB7A463D23E419EA06B744005385455A71250; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h6C60009CA281AEACDC1762945981B869F93D683EAF4AC7EE52412E85B60B91CD03AD0025F0D509F63202D877ECD8BF8005451F7BD346CF9E17B36F1850A7D80A8CF14A288EAE3BFE00FB2DB45080D4A50C58263A3B398DD51AB9CB554ECAA7B2E73D9D6D2C265859DB844C2C1952AD10241100174FE0444E6707D80A098D8585AAAC4802B74190FB007C0C0206186AFC1B3A2A46864F26118ED1D03ACB1062B7315502751655F60070E6B2C50609369611365AD1E3352327320331A51818030C7D8C4C59396600DC0C420495A0D987501490002BAD38012E20620D556A230B1796450B74E95A860FF3E434C65F1308F16F92395816B914F0CE870C1323347A4E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h7FC8531A7A319F3EBFC1383FFCDB0E09BD288288B078B4AD220B6FA934CF6187D972662C0D31E34E63B31CFC6EB4B35A69B67D85489E62EA99899A94F6800FDBA5D31B86A0288D29CE2EAAFF86A6A9F7000082293E6BB54F06E98ECCB199973EDA00FADB1D3A630BA18050635DE7DCB13B9B86E0CE6E08DC46331A352F716E3C441A0CC068A0823F8668A00621B779DE35FEC004050469F34866AEE766743D8C00FDF3B9F8DE7B76E97F8D32F0F39E4CAC68D9BBB68EA3915F6225F932CAAFDAD6E60DC661155EC9E80F8CEE659F19CC554B2C67C33EDCDA63BAD91B7D1842A7177AF49DF118FE47ACE3344964EBCADCFBB543F7729CCB340866D1157B6CCDDB; +// synopsys translate_on + +// Location: M9K_X22_Y29_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a2 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h77A47C739FF6A22B8B5CDC49E748E9C739BDE6756DB4D22437E74183E12400CBF7D3C6CC8C7841AB49CC538E8A72F2E73C64D3DF3662B19C07D7D299CBEDEF3E7DA5F4A8458A9451315B681ADA9AB0D63218DFB77D3353C32837E954604B9D98144A4566F47B71715BE6CDB8BA64D536762E9224D70F9A5C374B4D1CAB8DF527027170C5DBCC2B6AD72B8E4CCC94DAA139D8BA64E3384337426E7F274CC88A373AB1F9007B8A7F2936D16274F9BF8B6BABD48FCE74047C1E738C5B303E815BA720C76D6362915156A7671331CE657011862E594E46A6D99392E2D640D766869389A4D43867379AB880C1ACE279E451CB3A9063A0B320F65E536B8EEF9CBB9C76; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h9A2921ED6AA0CC8387B267B9E7A182720833CEE061E6450C8E4A72E3C043F21A0AD007E832124E92429C091D167806C10041AF32DDE13A669990457D098CC2FE3AC884B1E69101135CD080022451F20884CCB9CD203C141402A5AD293C3BABA95ADFAF6726384795A7656B753D2369B9EB5595BAA722012DF8DCFBF15BF46D6EB755D1CBF0DCF6FD40BEEC16EAB4A6D16839C98CBE9DBB437C69FB709F8E79993B9DDFE4F823D6E124B75BCE9B29F799F926619184B6C1178389F07349210436293A130C900FBA4EA70D2BA25B343C5B026D8E8766A4E4267CDAEC99E830D2307D94E6ED80D6722F3989B91E31C63B64C363DCE71A861C14382E270FC02868C7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h386BA04E797A3F8551DAD9D24A8D259A03ECFF5AB81B1C31DFDAE10100544F8CF1A8CCFC0C7A15BD9E7C2557CB00BF2584E16AAD13D7EDB525A85ABF90C0136DD195D748900C29DF7F381280A9738CDC3BF5BBF937D3A4D99CE2BCCD97CEF2C7F00030AFDB7F22E68CBAA4D9BE7633D3B53E90E4B124422A2A4454BACA5A8DC9352CD1DAFC910CC504334DF9E6F1F4F30161A36293CC5CCF1CA13994ED29D34A5699692496359B8E67A7E74D9A0FC504C8465638CF74A0AF9185921A7D2629893091900604017933442359491FBAB63F346F0C5EC8E3A531984B09E605A30A0627271C28420E47B8DEC74738FC3EDF9FBD40EC09FC7B4D3A1475BE433705FB5F; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h973FED2E9BEDBA474B70B121A8D60F3B4EE3F1A238FB3B730EDEEE74EC632DB4D7779D7B79D1C75DF87378E98719C1AF38B1B801C71D180CE86370AE9C2BF38CF84DBBB9878C55457324E92D3DAE91D729AC76BBAD4C6EECA74DAB5EE9A175EE34ABEB9DFAA48538A57E3E5C158947081CA41402E8E65478737F73BB629AAE2EE51D405CAF70F622DD4599602D7910DCAC8214B2A42025110593202C8B164C8DF6369572C3BB8AA1984A8D12F776E224ECEEB21F97FCD6C0CF17A044EC2BBF0571A553CCDD8ABA79BD27B7AF735ED2D34F1EF3A81A160C9ECB1B1FAE6EDEEFF99E28CC30C7C2553DED3378D655AD194B2E6C1BCBED700F6713D960F33E4C361A; +// synopsys translate_on + +// Location: M9K_X22_Y25_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a10 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(gnd), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[2]~39_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_first_bit_number = 2; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y27_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a2 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[2]~39_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_bit_number = 2; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF00000000FFFFFFFFFFFFFFFFFFF68003FFF38003FFF9F403FFF8B003D8F87003FFF8F01BEDFC701FEBFEA01FDBFDC00FDBFDC01FC7FDC0FFC7FDE87FC7FCDC8FC7FCF89FC07071FFC0F873F3E0303FE7FFFFFFFFFFFFFFFF; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000000040078400234B1474928D1000000000000000000000000FFFFFFFF204081024004027153423DA5474928DD000000000000000000000000000000003FFFFFFF40041CB14162378547495999000000000000000000000000000000003FFFFFFF4004189141623485474959F90000000000000000000000003FFFFFFE40000001400400815B6223C15FC913DD0000000000000000000000007FFFFFFE40000001400402E9400333715FC973E5000000000000000000000000604081027FFFFFFD5FE60AE95763353540091361000000000000000000000000400000003FFFFFFC5FE60AE95763081D40011361; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h5FE0236948F816F55FE897C10C28028041DC8DE178059BC16900BB4173E47AC15FE8236148E806F55FE891054CA80E8148288DE179E597C169903AC153F13A8140080365486806D55FE891D548080A8148608FE159E493C16BB03FD152BD1AE14008037D482017D15FE881C548A00AC148E08FE159FC9AC16AA02FC15AAF18F1400083F1482007C15EE882C148E00A4148B08FE148F88D4168E436915ABB01E9400092F9480007815C2882C148E00B6149B49F614868FD41436476814AFA42A1400892FD480807C15C0883C149800FE149DC9FE14A60BD41431C3F914AEA01C1400882F1480817C11C0883C041940FE549CC9EE54860BDC143BC7D8108D2C4D0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h0B928870484885014DE84481680162815375AC0148D308813FFFFFFC400000004B9288314DC0970149FC44856C0166815375AC8140D108817FFFFFFD6040808249D0A2094F908581481C40814C016099417DA88140D10B01400000017FFFFFFE48D083394B9085814A085081440166814179900140510F01400000013FFFFFFE4A508335498001814BE0608146016E8941799041405107413FFFFFFF000000004B98812149C005814BE0628146836E814179100140510F013FFFFFFF000000004B98A1114BE801814A00668147832C814119904140401F4120408082FFFFFFFF48D881154EA801854800768147C22CC14019900100003E0000000000FFFFFFFF; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N24 +cycloneive_lcell_comb \Selector0~0 ( +// Equation(s): +// \Selector0~0_combout = (\Selector3~0_combout & (((\ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout )) # (!\z80_|address_pins_|abus[14]~23_combout ))) # (!\Selector3~0_combout & (\z80_|address_pins_|abus[14]~23_combout & +// ((\ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout )))) + + .dataa(\Selector3~0_combout ), + .datab(\z80_|address_pins_|abus[14]~23_combout ), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ), + .cin(gnd), + .combout(\Selector0~0_combout ), + .cout()); +// synopsys translate_off +defparam \Selector0~0 .lut_mask = 16'hE6A2; +defparam \Selector0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N18 +cycloneive_lcell_comb \Selector0~1 ( +// Equation(s): +// \Selector0~1_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\Selector0~0_combout )))) # (!\z80_|address_pins_|abus[14]~23_combout & ((\Selector0~0_combout & (\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout )) # +// (!\Selector0~0_combout & ((\rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ))))) + + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ), + .datad(\Selector0~0_combout ), + .cin(gnd), + .combout(\Selector0~1_combout ), + .cout()); +// synopsys translate_off +defparam \Selector0~1 .lut_mask = 16'hEE50; +defparam \Selector0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N28 +cycloneive_lcell_comb \D[2]~82 ( +// Equation(s): +// \D[2]~82_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~3_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\Selector0~1_combout +// ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~3_combout )))) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~3_combout ), + .datad(\Selector0~1_combout ), + .cin(gnd), + .combout(\D[2]~82_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~82 .lut_mask = 16'hF4B0; +defparam \D[2]~82 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N12 +cycloneive_lcell_comb \D[2]~38 ( +// Equation(s): +// \D[2]~38_combout = ((\Equal2~0_combout & (\D[2]~37_combout )) # (!\Equal2~0_combout & ((\D[2]~82_combout )))) # (!\Equal2~1_combout ) + + .dataa(\Equal2~1_combout ), + .datab(\Equal2~0_combout ), + .datac(\D[2]~37_combout ), + .datad(\D[2]~82_combout ), + .cin(gnd), + .combout(\D[2]~38_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~38 .lut_mask = 16'hF7D5; +defparam \D[2]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N30 +cycloneive_lcell_comb \D[2]~39 ( +// Equation(s): +// \D[2]~39_combout = (\z80_|pin_control_|bus_db_pin_oe~15_combout & (((\z80_|data_pins_|dout [2] & \D[2]~38_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout & (((\D[2]~38_combout )) # (!\Equal2~1_combout ))) + + .dataa(\Equal2~1_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .datac(\z80_|data_pins_|dout [2]), + .datad(\D[2]~38_combout ), + .cin(gnd), + .combout(\D[2]~39_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~39 .lut_mask = 16'hF311; +defparam \D[2]~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N4 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [2] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[2]~13_combout ) # ((\D[2]~39_combout & \z80_|pin_control_|bus_db_pin_re~combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & +// (((\D[2]~39_combout & \z80_|pin_control_|bus_db_pin_re~combout )))) + + .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datab(\z80_|bus_control_|db[2]~13_combout ), + .datac(\D[2]~39_combout ), + .datad(\z80_|pin_control_|bus_db_pin_re~combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [2]), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] .lut_mask = 16'hF888; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y13_N5 +dffeas \z80_|data_pins_|dout[2] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [2]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|data_pins_|dout [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|data_pins_|dout[2] .is_wysiwyg = "true"; +defparam \z80_|data_pins_|dout[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N6 +cycloneive_lcell_comb \z80_|bus_control_|db[2]~12 ( +// Equation(s): +// \z80_|bus_control_|db[2]~12_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[2]~29_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) + + .dataa(\z80_|bus_control_|db[0]~4_combout ), + .datab(gnd), + .datac(\z80_|alu_control_|db[2]~29_combout ), + .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[2]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[2]~12 .lut_mask = 16'hA0AA; +defparam \z80_|bus_control_|db[2]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N0 +cycloneive_lcell_comb \z80_|bus_control_|db[2]~13 ( +// Equation(s): +// \z80_|bus_control_|db[2]~13_combout = ((\z80_|bus_control_|db[2]~12_combout & ((\z80_|data_pins_|dout [2]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) + + .dataa(\z80_|bus_control_|db[0]~6_combout ), + .datab(\z80_|execute_|ctl_bus_db_oe~combout ), + .datac(\z80_|data_pins_|dout [2]), + .datad(\z80_|bus_control_|db[2]~12_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[2]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[2]~13 .lut_mask = 16'hF755; +defparam \z80_|bus_control_|db[2]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y13_N27 +dffeas \z80_|ir_|opcode[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|bus_control_|db[2]~13_combout ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|ir_|opcode [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|ir_|opcode[2] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N18 +cycloneive_lcell_comb \z80_|pla_decode_|Equal1~4 ( +// Equation(s): +// \z80_|pla_decode_|Equal1~4_combout = (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [1]) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|ir_|opcode [1]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal1~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal1~4 .lut_mask = 16'h0303; +defparam \z80_|pla_decode_|Equal1~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~26 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~26_combout = (\z80_|pla_decode_|Equal1~4_combout & (\z80_|execute_|ctl_mWrite~5_combout & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|ir_|opcode [0]))) + + .dataa(\z80_|pla_decode_|Equal1~4_combout ), + .datab(\z80_|execute_|ctl_mWrite~5_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~26 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_alu_op_low~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~45 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~45_combout = (!\z80_|execute_|ctl_alu_op_low~26_combout & (((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|pla_decode_|Equal13~2_combout )) # (!\z80_|sequencer_|DFFE_M4_ff~q ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~26_combout ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~45 .lut_mask = 16'h1555; +defparam \z80_|execute_|ctl_alu_op_low~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|setM1~17 ( +// Equation(s): +// \z80_|execute_|setM1~17_combout = (!\z80_|execute_|ctl_alu_shift_oe~15_combout & (\z80_|execute_|ctl_sw_2u~1_combout & \z80_|execute_|ctl_state_alu~7_combout )) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~15_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_sw_2u~1_combout ), + .datad(\z80_|execute_|ctl_state_alu~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~17 .lut_mask = 16'h5000; +defparam \z80_|execute_|setM1~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|setM1~18 ( +// Equation(s): +// \z80_|execute_|setM1~18_combout = (\z80_|execute_|ctl_alu_op_low~45_combout & (\z80_|execute_|setM1~17_combout & (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & !\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~45_combout ), + .datab(\z80_|execute_|setM1~17_combout ), + .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~18 .lut_mask = 16'h0008; +defparam \z80_|execute_|setM1~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|setM1~11 ( +// Equation(s): +// \z80_|execute_|setM1~11_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ) # ((!\z80_|ir_|opcode [2] & (\z80_|execute_|ctl_mWrite~4_combout & !\z80_|ir_|opcode [4]))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|setM1~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~11 .lut_mask = 16'hAABA; +defparam \z80_|execute_|setM1~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|setM1~10 ( +// Equation(s): +// \z80_|execute_|setM1~10_combout = (\z80_|execute_|ctl_mRead~5_combout ) # (((\z80_|execute_|ctl_mWrite~6_combout ) # (\z80_|pla_decode_|Equal6~1_combout )) # (!\z80_|execute_|fMWrite~1_combout )) + + .dataa(\z80_|execute_|ctl_mRead~5_combout ), + .datab(\z80_|execute_|fMWrite~1_combout ), + .datac(\z80_|execute_|ctl_mWrite~6_combout ), + .datad(\z80_|pla_decode_|Equal6~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~10 .lut_mask = 16'hFFFB; +defparam \z80_|execute_|setM1~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|setM1~12 ( +// Equation(s): +// \z80_|execute_|setM1~12_combout = ((\z80_|execute_|setM1~10_combout ) # ((\z80_|execute_|setM1~11_combout & \z80_|execute_|ctl_mWrite~17_combout ))) # (!\z80_|execute_|nextM~2_combout ) + + .dataa(\z80_|execute_|nextM~2_combout ), + .datab(\z80_|execute_|setM1~11_combout ), + .datac(\z80_|execute_|ctl_mWrite~17_combout ), + .datad(\z80_|execute_|setM1~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~12 .lut_mask = 16'hFFD5; +defparam \z80_|execute_|setM1~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|setM1~8 ( +// Equation(s): +// \z80_|execute_|setM1~8_combout = (\z80_|execute_|ctl_al_we~13_combout & (\z80_|sequencer_|M5~q & ((\z80_|pla_decode_|Equal9~1_combout )))) # (!\z80_|execute_|ctl_al_we~13_combout & ((\z80_|sequencer_|DFFE_M4_ff~q ) # ((\z80_|sequencer_|M5~q & +// \z80_|pla_decode_|Equal9~1_combout )))) + + .dataa(\z80_|execute_|ctl_al_we~13_combout ), + .datab(\z80_|sequencer_|M5~q ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~8 .lut_mask = 16'hDC50; +defparam \z80_|execute_|setM1~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|setM1~9 ( +// Equation(s): +// \z80_|execute_|setM1~9_combout = ((\z80_|sequencer_|DFFE_T5_ff~q & \z80_|execute_|setM1~8_combout )) # (!\z80_|execute_|ctl_flags_xy_we~19_combout ) + + .dataa(\z80_|execute_|ctl_flags_xy_we~19_combout ), + .datab(\z80_|sequencer_|DFFE_T5_ff~q ), + .datac(gnd), + .datad(\z80_|execute_|setM1~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~9 .lut_mask = 16'hDD55; +defparam \z80_|execute_|setM1~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|setM1~13 ( +// Equation(s): +// \z80_|execute_|setM1~13_combout = ((\z80_|execute_|setM1~9_combout ) # ((\z80_|execute_|setM1~12_combout & \z80_|execute_|ixy_d~6_combout ))) # (!\z80_|reg_control_|reg_sel_pc~3_combout ) + + .dataa(\z80_|reg_control_|reg_sel_pc~3_combout ), + .datab(\z80_|execute_|setM1~12_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|setM1~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~13 .lut_mask = 16'hFFD5; +defparam \z80_|execute_|setM1~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|setM1~15 ( +// Equation(s): +// \z80_|execute_|setM1~15_combout = (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|pla_decode_|Equal13~0_combout & ((!\z80_|pla_decode_|Equal21~2_combout ) # (!\z80_|pla_decode_|Equal32~0_combout )))) # (!\z80_|pla_decode_|Equal33~0_combout & +// (((!\z80_|pla_decode_|Equal21~2_combout )) # (!\z80_|pla_decode_|Equal32~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|pla_decode_|Equal32~0_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|pla_decode_|Equal21~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~15 .lut_mask = 16'h135F; +defparam \z80_|execute_|setM1~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|setM1~14 ( +// Equation(s): +// \z80_|execute_|setM1~14_combout = (!\z80_|execute_|ctl_alu_oe~1_combout & (!\z80_|pla_decode_|Equal77~1_combout & (!\z80_|pla_decode_|Equal1~6_combout & !\z80_|pla_decode_|Equal2~2_combout ))) + + .dataa(\z80_|execute_|ctl_alu_oe~1_combout ), + .datab(\z80_|pla_decode_|Equal77~1_combout ), + .datac(\z80_|pla_decode_|Equal1~6_combout ), + .datad(\z80_|pla_decode_|Equal2~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~14 .lut_mask = 16'h0001; +defparam \z80_|execute_|setM1~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|setM1~16 ( +// Equation(s): +// \z80_|execute_|setM1~16_combout = (\z80_|interrupts_|test1~2_combout & (\z80_|execute_|setM1~15_combout & \z80_|execute_|setM1~14_combout )) + + .dataa(gnd), + .datab(\z80_|interrupts_|test1~2_combout ), + .datac(\z80_|execute_|setM1~15_combout ), + .datad(\z80_|execute_|setM1~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~16 .lut_mask = 16'hC000; +defparam \z80_|execute_|setM1~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|setM1~19 ( +// Equation(s): +// \z80_|execute_|setM1~19_combout = ((\z80_|execute_|setM1~13_combout ) # ((!\z80_|execute_|setM1~16_combout & \z80_|execute_|ctl_eval_cond~0_combout ))) # (!\z80_|execute_|setM1~18_combout ) + + .dataa(\z80_|execute_|setM1~18_combout ), + .datab(\z80_|execute_|setM1~13_combout ), + .datac(\z80_|execute_|setM1~16_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~19 .lut_mask = 16'hDFDD; +defparam \z80_|execute_|setM1~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N16 +cycloneive_lcell_comb \z80_|execute_|setM1~23 ( +// Equation(s): +// \z80_|execute_|setM1~23_combout = (\z80_|execute_|fMWrite~1_combout & (!\z80_|execute_|ctl_mRead~8_combout & (!\z80_|execute_|ctl_mRead~6_combout & \z80_|execute_|fMWrite~6_combout ))) + + .dataa(\z80_|execute_|fMWrite~1_combout ), + .datab(\z80_|execute_|ctl_mRead~8_combout ), + .datac(\z80_|execute_|ctl_mRead~6_combout ), + .datad(\z80_|execute_|fMWrite~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~23 .lut_mask = 16'h0200; +defparam \z80_|execute_|setM1~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|setM1~22 ( +// Equation(s): +// \z80_|execute_|setM1~22_combout = (\z80_|decode_state_|DFFE_instNonRep~q ) # ((!\z80_|ir_|opcode [2] & (\z80_|execute_|ctl_mWrite~4_combout & !\z80_|ir_|opcode [4]))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|execute_|ctl_mWrite~4_combout ), + .datac(\z80_|decode_state_|DFFE_instNonRep~q ), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|setM1~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~22 .lut_mask = 16'hF0F4; +defparam \z80_|execute_|setM1~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|setM1~56 ( +// Equation(s): +// \z80_|execute_|setM1~56_combout = (\z80_|sequencer_|DFFE_T5_ff~q & ((\z80_|sequencer_|DFFE_M4_ff~q ) # ((\z80_|sequencer_|DFFE_M3_ff~q & \z80_|execute_|setM1~22_combout )))) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|sequencer_|DFFE_T5_ff~q ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|execute_|setM1~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~56_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~56 .lut_mask = 16'hC8C0; +defparam \z80_|execute_|setM1~56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|setM1~24 ( +// Equation(s): +// \z80_|execute_|setM1~24_combout = (\z80_|execute_|setM1~23_combout & (!\z80_|execute_|ctl_flags_bus~1_combout & ((\z80_|execute_|setM1~56_combout )))) # (!\z80_|execute_|setM1~23_combout & ((\z80_|execute_|ctl_reg_in_hi~2_combout ) # +// ((!\z80_|execute_|ctl_flags_bus~1_combout & \z80_|execute_|setM1~56_combout )))) + + .dataa(\z80_|execute_|setM1~23_combout ), + .datab(\z80_|execute_|ctl_flags_bus~1_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datad(\z80_|execute_|setM1~56_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~24 .lut_mask = 16'h7350; +defparam \z80_|execute_|setM1~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|setM1~25 ( +// Equation(s): +// \z80_|execute_|setM1~25_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & (((\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & !\z80_|execute_|ctl_mRead~10_combout )) # (!\z80_|alu_control_|flags_cond_true~q ))) # +// (!\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & (((\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & !\z80_|execute_|ctl_mRead~10_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), + .datab(\z80_|alu_control_|flags_cond_true~q ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .datad(\z80_|execute_|ctl_mRead~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~25 .lut_mask = 16'h22F2; +defparam \z80_|execute_|setM1~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|setM1~26 ( +// Equation(s): +// \z80_|execute_|setM1~26_combout = ((\z80_|execute_|ctl_mRead~11_combout ) # ((!\z80_|alu_control_|flags_cond_true~q & \z80_|pla_decode_|Equal40~1_combout ))) # (!\z80_|execute_|ctl_bus_inc_oe~31_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~31_combout ), + .datab(\z80_|alu_control_|flags_cond_true~q ), + .datac(\z80_|pla_decode_|Equal40~1_combout ), + .datad(\z80_|execute_|ctl_mRead~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~26 .lut_mask = 16'hFF75; +defparam \z80_|execute_|setM1~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|setM1~27 ( +// Equation(s): +// \z80_|execute_|setM1~27_combout = (\z80_|execute_|setM1~26_combout ) # (((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & \z80_|pla_decode_|Equal21~1_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout )) + + .dataa(\z80_|execute_|setM1~26_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ), + .datad(\z80_|pla_decode_|Equal21~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~27 .lut_mask = 16'hEFAF; +defparam \z80_|execute_|setM1~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|setM1~28 ( +// Equation(s): +// \z80_|execute_|setM1~28_combout = (\z80_|execute_|setM1~24_combout ) # ((\z80_|execute_|setM1~25_combout ) # ((\z80_|execute_|ctl_state_alu~2_combout & \z80_|execute_|setM1~27_combout ))) + + .dataa(\z80_|execute_|setM1~24_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|execute_|setM1~25_combout ), + .datad(\z80_|execute_|setM1~27_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~28 .lut_mask = 16'hFEFA; +defparam \z80_|execute_|setM1~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|setM1~55 ( +// Equation(s): +// \z80_|execute_|setM1~55_combout = ((\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|execute_|ctl_iorw~10_combout ))) # (!\z80_|execute_|ctl_flags_sz_we~0_combout ) + + .dataa(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|execute_|ctl_iorw~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~55_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~55 .lut_mask = 16'hD555; +defparam \z80_|execute_|setM1~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|setM1~29 ( +// Equation(s): +// \z80_|execute_|setM1~29_combout = (\z80_|execute_|ctl_mRead~13_combout ) # ((\z80_|execute_|ctl_mRead~5_combout ) # ((\z80_|execute_|ctl_mRead~7_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~13_combout ), + .datab(\z80_|execute_|ctl_mRead~5_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ), + .datad(\z80_|execute_|ctl_mRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~29 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|setM1~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|setM1~31 ( +// Equation(s): +// \z80_|execute_|setM1~31_combout = (((\z80_|execute_|ctl_state_alu~4_combout & \z80_|execute_|setM1~29_combout )) # (!\z80_|execute_|setM1~57_combout )) # (!\z80_|execute_|setM1~30_combout ) + + .dataa(\z80_|execute_|setM1~30_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|setM1~29_combout ), + .datad(\z80_|execute_|setM1~57_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~31 .lut_mask = 16'hD5FF; +defparam \z80_|execute_|setM1~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|setM1~33 ( +// Equation(s): +// \z80_|execute_|setM1~33_combout = (\z80_|execute_|ctl_mRead~2_combout ) # ((\z80_|execute_|ctl_mRead~3_combout ) # ((\z80_|execute_|ctl_mRead~34_combout & \z80_|execute_|setM1~11_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~2_combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|execute_|setM1~11_combout ), + .datad(\z80_|execute_|ctl_mRead~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~33 .lut_mask = 16'hFFEA; +defparam \z80_|execute_|setM1~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|setM1~32 ( +// Equation(s): +// \z80_|execute_|setM1~32_combout = (\z80_|pla_decode_|Equal35~0_combout & ((\z80_|execute_|ixy_d~6_combout ) # ((\z80_|execute_|ctl_reg_in_hi~2_combout & \z80_|execute_|ctl_mRead~16_combout )))) # (!\z80_|pla_decode_|Equal35~0_combout & +// (\z80_|execute_|ctl_reg_in_hi~2_combout & ((\z80_|execute_|ctl_mRead~16_combout )))) + + .dataa(\z80_|pla_decode_|Equal35~0_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ctl_mRead~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~32 .lut_mask = 16'hECA0; +defparam \z80_|execute_|setM1~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|setM1~34 ( +// Equation(s): +// \z80_|execute_|setM1~34_combout = (\z80_|execute_|setM1~31_combout ) # ((\z80_|execute_|setM1~32_combout ) # ((\z80_|execute_|setM1~33_combout & \z80_|execute_|ixy_d~9_combout ))) + + .dataa(\z80_|execute_|setM1~31_combout ), + .datab(\z80_|execute_|setM1~33_combout ), + .datac(\z80_|execute_|ixy_d~9_combout ), + .datad(\z80_|execute_|setM1~32_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~34 .lut_mask = 16'hFFEA; +defparam \z80_|execute_|setM1~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|setM1~20 ( +// Equation(s): +// \z80_|execute_|setM1~20_combout = (\z80_|execute_|ctl_mRead~9_combout & (((\z80_|pla_decode_|Equal37~0_combout & !\z80_|alu_control_|flags_cond_true~q )) # (!\z80_|execute_|ctl_flags_bus~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal37~0_combout ), + .datab(\z80_|alu_control_|flags_cond_true~q ), + .datac(\z80_|execute_|ctl_mRead~9_combout ), + .datad(\z80_|execute_|ctl_flags_bus~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~20 .lut_mask = 16'h20F0; +defparam \z80_|execute_|setM1~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|setM1~21 ( +// Equation(s): +// \z80_|execute_|setM1~21_combout = (\z80_|execute_|setM1~20_combout ) # ((\z80_|execute_|ixy_d~8_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & \z80_|pla_decode_|Equal10~0_combout ))) + + .dataa(\z80_|execute_|ixy_d~8_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|execute_|setM1~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~21 .lut_mask = 16'hFF80; +defparam \z80_|execute_|setM1~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|setM1~35 ( +// Equation(s): +// \z80_|execute_|setM1~35_combout = (\z80_|execute_|setM1~28_combout ) # ((\z80_|execute_|setM1~55_combout ) # ((\z80_|execute_|setM1~34_combout ) # (\z80_|execute_|setM1~21_combout ))) + + .dataa(\z80_|execute_|setM1~28_combout ), + .datab(\z80_|execute_|setM1~55_combout ), + .datac(\z80_|execute_|setM1~34_combout ), + .datad(\z80_|execute_|setM1~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~35 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|setM1~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|setM1~43 ( +// Equation(s): +// \z80_|execute_|setM1~43_combout = (!\z80_|execute_|ctl_mWrite~6_combout & (!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~9_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datac(\z80_|execute_|ctl_ir_we~10_combout ), + .datad(\z80_|execute_|ctl_ir_we~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~43 .lut_mask = 16'h0003; +defparam \z80_|execute_|setM1~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N6 +cycloneive_lcell_comb \z80_|execute_|setM1~44 ( +// Equation(s): +// \z80_|execute_|setM1~44_combout = (!\z80_|pla_decode_|Equal47~0_combout & (!\z80_|pla_decode_|Equal37~0_combout & (!\z80_|pla_decode_|Equal38~2_combout & \z80_|sequencer_|DFFE_T4_ff~q ))) + + .dataa(\z80_|pla_decode_|Equal47~0_combout ), + .datab(\z80_|pla_decode_|Equal37~0_combout ), + .datac(\z80_|pla_decode_|Equal38~2_combout ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|setM1~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~44 .lut_mask = 16'h0100; +defparam \z80_|execute_|setM1~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N18 +cycloneive_lcell_comb \z80_|execute_|setM1~45 ( +// Equation(s): +// \z80_|execute_|setM1~45_combout = (!\z80_|pla_decode_|Equal21~1_combout & (\z80_|execute_|setM1~43_combout & (!\z80_|pla_decode_|Equal48~0_combout & \z80_|execute_|setM1~44_combout ))) + + .dataa(\z80_|pla_decode_|Equal21~1_combout ), + .datab(\z80_|execute_|setM1~43_combout ), + .datac(\z80_|pla_decode_|Equal48~0_combout ), + .datad(\z80_|execute_|setM1~44_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~45 .lut_mask = 16'h0400; +defparam \z80_|execute_|setM1~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|setM1~46 ( +// Equation(s): +// \z80_|execute_|setM1~46_combout = (\z80_|execute_|setM1~45_combout & (\z80_|execute_|setM1~42_combout & ((!\z80_|pla_decode_|Equal1~4_combout ) # (!\z80_|pla_decode_|Equal2~1_combout )))) + + .dataa(\z80_|execute_|setM1~45_combout ), + .datab(\z80_|pla_decode_|Equal2~1_combout ), + .datac(\z80_|pla_decode_|Equal1~4_combout ), + .datad(\z80_|execute_|setM1~42_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~46 .lut_mask = 16'h2A00; +defparam \z80_|execute_|setM1~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|setM1~52 ( +// Equation(s): +// \z80_|execute_|setM1~52_combout = (\z80_|execute_|setM1~48_combout & (\z80_|execute_|setM1~46_combout & (\z80_|execute_|setM1~16_combout & \z80_|execute_|setM1~51_combout ))) + + .dataa(\z80_|execute_|setM1~48_combout ), + .datab(\z80_|execute_|setM1~46_combout ), + .datac(\z80_|execute_|setM1~16_combout ), + .datad(\z80_|execute_|setM1~51_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~52_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~52 .lut_mask = 16'h8000; +defparam \z80_|execute_|setM1~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N4 +cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_17 ( +// Equation(s): +// \z80_|sequencer_|SYNTHESIZED_WIRE_17~combout = (\z80_|execute_|setM1~54_combout & (\z80_|sequencer_|DFFE_T5_ff~q & !\z80_|execute_|nextM~14_combout )) + + .dataa(\z80_|execute_|setM1~54_combout ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T5_ff~q ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_17~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_17 .lut_mask = 16'h00A0; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y12_N5 +dffeas \z80_|sequencer_|T6 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|SYNTHESIZED_WIRE_17~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|T6~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|T6 .is_wysiwyg = "true"; +defparam \z80_|sequencer_|T6 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|setM1~53 ( +// Equation(s): +// \z80_|execute_|setM1~53_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|execute_|setM1~41_combout ) # ((\z80_|sequencer_|T6~q & !\z80_|execute_|setM1~42_combout )))) # (!\z80_|execute_|setM1~52_combout & (((\z80_|sequencer_|T6~q & +// !\z80_|execute_|setM1~42_combout )))) + + .dataa(\z80_|execute_|setM1~52_combout ), + .datab(\z80_|execute_|setM1~41_combout ), + .datac(\z80_|sequencer_|T6~q ), + .datad(\z80_|execute_|setM1~42_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~53_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~53 .lut_mask = 16'h88F8; +defparam \z80_|execute_|setM1~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|setM1~54 ( +// Equation(s): +// \z80_|execute_|setM1~54_combout = (!\z80_|execute_|setM1~19_combout & (!\z80_|execute_|setM1~35_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|execute_|setM1~53_combout )))) + + .dataa(\z80_|execute_|setM1~19_combout ), + .datab(\z80_|execute_|setM1~35_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|execute_|setM1~53_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~54_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~54 .lut_mask = 16'h1011; +defparam \z80_|execute_|setM1~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N28 +cycloneive_lcell_comb \z80_|sequencer_|DFFE_M1_ff~0 ( +// Equation(s): +// \z80_|sequencer_|DFFE_M1_ff~0_combout = (\z80_|execute_|setM1~54_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # (\z80_|execute_|nextM~14_combout ))) + + .dataa(gnd), + .datab(\z80_|execute_|setM1~54_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|DFFE_M1_ff~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_M1_ff~0 .lut_mask = 16'hCCC0; +defparam \z80_|sequencer_|DFFE_M1_ff~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y13_N29 +dffeas \z80_|sequencer_|DFFE_M1_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|DFFE_M1_ff~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_M1_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_M1_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_M1_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X52_Y17_N4 +cycloneive_lcell_comb \z80_|resets_|x1~0 ( +// Equation(s): +// \z80_|resets_|x1~0_combout = !\reset~combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\reset~combout ), + .cin(gnd), + .combout(\z80_|resets_|x1~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|resets_|x1~0 .lut_mask = 16'h00FF; +defparam \z80_|resets_|x1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y16_N16 +cycloneive_lcell_comb \z80_|fpga_reset~feeder ( +// Equation(s): +// \z80_|fpga_reset~feeder_combout = VCC + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\z80_|fpga_reset~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|fpga_reset~feeder .lut_mask = 16'hFFFF; +defparam \z80_|fpga_reset~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X1_Y16_N17 +dffeas \z80_|fpga_reset ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|fpga_reset~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|fpga_reset~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|fpga_reset .is_wysiwyg = "true"; +defparam \z80_|fpga_reset .power_up = "low"; +// synopsys translate_on + +// Location: CLKCTRL_G2 +cycloneive_clkctrl \z80_|fpga_reset~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\z80_|fpga_reset~q }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\z80_|fpga_reset~clkctrl_outclk )); +// synopsys translate_off +defparam \z80_|fpga_reset~clkctrl .clock_type = "global clock"; +defparam \z80_|fpga_reset~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: FF_X52_Y17_N5 +dffeas \z80_|resets_|x1 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|resets_|x1~0_combout ), + .asdata(vcc), + .clrn(\z80_|fpga_reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|resets_|x1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|resets_|x1 .is_wysiwyg = "true"; +defparam \z80_|resets_|x1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X52_Y17_N12 +cycloneive_lcell_comb \z80_|resets_|x3 ( +// Equation(s): +// \z80_|resets_|x3~combout = (\z80_|resets_|x1~q ) # ((!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T2_ff~q )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|resets_|x1~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|resets_|x3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|resets_|x3 .lut_mask = 16'hF3F0; +defparam \z80_|resets_|x3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X52_Y17_N13 +dffeas \z80_|resets_|SYNTHESIZED_WIRE_12 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|resets_|x3~combout ), + .asdata(vcc), + .clrn(\z80_|fpga_reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|resets_|SYNTHESIZED_WIRE_12 .is_wysiwyg = "true"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_12 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N28 +cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_10~0 ( +// Equation(s): +// \z80_|resets_|SYNTHESIZED_WIRE_10~0_combout = !\z80_|resets_|SYNTHESIZED_WIRE_12~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .cin(gnd), + .combout(\z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|resets_|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h00FF; +defparam \z80_|resets_|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y13_N29 +dffeas \z80_|resets_|SYNTHESIZED_WIRE_10 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|resets_|SYNTHESIZED_WIRE_10 .is_wysiwyg = "true"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_10 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N22 +cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_9~feeder ( +// Equation(s): +// \z80_|resets_|SYNTHESIZED_WIRE_9~feeder_combout = \z80_|resets_|SYNTHESIZED_WIRE_10~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), + .cin(gnd), + .combout(\z80_|resets_|SYNTHESIZED_WIRE_9~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|resets_|SYNTHESIZED_WIRE_9~feeder .lut_mask = 16'hFF00; +defparam \z80_|resets_|SYNTHESIZED_WIRE_9~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y13_N23 +dffeas \z80_|resets_|SYNTHESIZED_WIRE_9 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|resets_|SYNTHESIZED_WIRE_9~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|resets_|SYNTHESIZED_WIRE_9 .is_wysiwyg = "true"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_9 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X36_Y13_N19 +dffeas \z80_|resets_|DFFE_intr_ff3 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|resets_|DFFE_intr_ff3~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|resets_|DFFE_intr_ff3 .is_wysiwyg = "true"; +defparam \z80_|resets_|DFFE_intr_ff3 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N0 +cycloneive_lcell_comb \z80_|resets_|clrpc_int~0 ( +// Equation(s): +// \z80_|resets_|clrpc_int~0_combout = (\z80_|sequencer_|DFFE_M1_ff~q & (((\z80_|resets_|clrpc_int~q )))) # (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|resets_|clrpc_int~q & !\z80_|resets_|x1~q )) # +// (!\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|resets_|clrpc_int~q )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|resets_|clrpc_int~q ), + .datad(\z80_|resets_|x1~q ), + .cin(gnd), + .combout(\z80_|resets_|clrpc_int~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|resets_|clrpc_int~0 .lut_mask = 16'hB0B4; +defparam \z80_|resets_|clrpc_int~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y13_N1 +dffeas \z80_|resets_|clrpc_int ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|resets_|clrpc_int~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|resets_|clrpc_int~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|resets_|clrpc_int .is_wysiwyg = "true"; +defparam \z80_|resets_|clrpc_int .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N18 +cycloneive_lcell_comb \z80_|resets_|clrpc~0 ( +// Equation(s): +// \z80_|resets_|clrpc~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_9~q ) # ((\z80_|resets_|SYNTHESIZED_WIRE_10~q ) # ((\z80_|resets_|DFFE_intr_ff3~q ) # (\z80_|resets_|clrpc_int~q ))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), + .datac(\z80_|resets_|DFFE_intr_ff3~q ), + .datad(\z80_|resets_|clrpc_int~q ), + .cin(gnd), + .combout(\z80_|resets_|clrpc~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|resets_|clrpc~0 .lut_mask = 16'hFFFE; +defparam \z80_|resets_|clrpc~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N2 +cycloneive_lcell_comb \z80_|address_latch_|abusz[0] ( +// Equation(s): +// \z80_|address_latch_|abusz [0] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[0]~3_combout ) + + .dataa(gnd), + .datab(\z80_|resets_|clrpc~0_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|db_lo_as[0]~3_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [0]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[0] .lut_mask = 16'h3300; +defparam \z80_|address_latch_|abusz[0] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N24 cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[0]~0 ( // Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[0]~0_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [0]))) +// \z80_|address_pins_|DFFE_apin_latch[0]~0_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [0])) - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), + .dataa(\z80_|address_latch_|abusz [0]), + .datab(\z80_|execute_|ctl_apin_mux~2_combout ), .datac(gnd), - .datad(\z80_|address_latch_|abusz [0]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), .cin(gnd), .combout(\z80_|address_pins_|DFFE_apin_latch[0]~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[0]~0 .lut_mask = 16'hDD88; +defparam \z80_|address_pins_|DFFE_apin_latch[0]~0 .lut_mask = 16'hEE22; defparam \z80_|address_pins_|DFFE_apin_latch[0]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y16_N19 +// Location: FF_X34_Y11_N25 dffeas \z80_|address_pins_|DFFE_apin_latch[0] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|address_pins_|DFFE_apin_latch[0]~0_combout ), @@ -53241,7 +53008,7 @@ dffeas \z80_|address_pins_|DFFE_apin_latch[0] ( .aload(gnd), .sclr(gnd), .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~1_combout ), .devclrn(devclrn), .devpor(devpor), .q(\z80_|address_pins_|DFFE_apin_latch [0]), @@ -53251,228 +53018,228 @@ defparam \z80_|address_pins_|DFFE_apin_latch[0] .is_wysiwyg = "true"; defparam \z80_|address_pins_|DFFE_apin_latch[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y14_N12 -cycloneive_lcell_comb \D[0]~59 ( +// Location: LCCOMB_X23_Y14_N20 +cycloneive_lcell_comb \D[0]~47 ( // Equation(s): -// \D[0]~59_combout = (\Equal2~0_combout & (\D[0]~51_combout )) # (!\Equal2~0_combout & ((\D[0]~106_combout ))) +// \D[0]~47_combout = (\Equal2~0_combout & (\D[0]~44_combout )) # (!\Equal2~0_combout & ((\D[0]~83_combout ))) .dataa(\Equal2~0_combout ), - .datab(\D[0]~51_combout ), - .datac(\D[0]~106_combout ), + .datab(\D[0]~44_combout ), + .datac(\D[0]~83_combout ), .datad(gnd), .cin(gnd), - .combout(\D[0]~59_combout ), + .combout(\D[0]~47_combout ), .cout()); // synopsys translate_off -defparam \D[0]~59 .lut_mask = 16'hD8D8; -defparam \D[0]~59 .sum_lutc_input = "datac"; +defparam \D[0]~47 .lut_mask = 16'hD8D8; +defparam \D[0]~47 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N8 -cycloneive_lcell_comb \D[0]~60 ( +// Location: LCCOMB_X24_Y14_N24 +cycloneive_lcell_comb \D[0]~48 ( // Equation(s): -// \D[0]~60_combout = (\Equal2~1_combout & (\D[0]~59_combout & ((\z80_|data_pins_|dout [0]) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) # (!\Equal2~1_combout & ((\z80_|data_pins_|dout [0]) # ((!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) +// \D[0]~48_combout = (\z80_|data_pins_|dout [0] & (((\D[0]~47_combout ) # (!\Equal2~1_combout )))) # (!\z80_|data_pins_|dout [0] & (!\z80_|pin_control_|bus_db_pin_oe~15_combout & ((\D[0]~47_combout ) # (!\Equal2~1_combout )))) + + .dataa(\z80_|data_pins_|dout [0]), + .datab(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .datac(\Equal2~1_combout ), + .datad(\D[0]~47_combout ), + .cin(gnd), + .combout(\D[0]~48_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~48 .lut_mask = 16'hBB0B; +defparam \D[0]~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N12 +cycloneive_lcell_comb \D[1]~49 ( +// Equation(s): +// \D[1]~49_combout = (\Equal2~0_combout & (\D[1]~30_combout )) # (!\Equal2~0_combout & ((\D[1]~81_combout ))) + + .dataa(\D[1]~30_combout ), + .datab(gnd), + .datac(\Equal2~0_combout ), + .datad(\D[1]~81_combout ), + .cin(gnd), + .combout(\D[1]~49_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~49 .lut_mask = 16'hAFA0; +defparam \D[1]~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N18 +cycloneive_lcell_comb \D[1]~50 ( +// Equation(s): +// \D[1]~50_combout = (\Equal2~1_combout & (\D[1]~49_combout & ((\z80_|data_pins_|dout [1]) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout )))) # (!\Equal2~1_combout & ((\z80_|data_pins_|dout [1]) # ((!\z80_|pin_control_|bus_db_pin_oe~15_combout )))) .dataa(\Equal2~1_combout ), - .datab(\z80_|data_pins_|dout [0]), - .datac(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datad(\D[0]~59_combout ), + .datab(\z80_|data_pins_|dout [1]), + .datac(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .datad(\D[1]~49_combout ), .cin(gnd), - .combout(\D[0]~60_combout ), + .combout(\D[1]~50_combout ), .cout()); // synopsys translate_off -defparam \D[0]~60 .lut_mask = 16'hCF45; -defparam \D[0]~60 .sum_lutc_input = "datac"; +defparam \D[1]~50 .lut_mask = 16'hCF45; +defparam \D[1]~50 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y18_N20 -cycloneive_lcell_comb \D[1]~61 ( +// Location: LCCOMB_X23_Y10_N2 +cycloneive_lcell_comb \D[2]~51 ( // Equation(s): -// \D[1]~61_combout = (\Equal2~0_combout & (\D[1]~32_combout )) # (!\Equal2~0_combout & ((\D[1]~103_combout ))) +// \D[2]~51_combout = (\Equal2~0_combout & (\D[2]~37_combout )) # (!\Equal2~0_combout & ((\D[2]~82_combout ))) - .dataa(\Equal2~0_combout ), + .dataa(\D[2]~37_combout ), .datab(gnd), - .datac(\D[1]~32_combout ), - .datad(\D[1]~103_combout ), + .datac(\Equal2~0_combout ), + .datad(\D[2]~82_combout ), .cin(gnd), - .combout(\D[1]~61_combout ), + .combout(\D[2]~51_combout ), .cout()); // synopsys translate_off -defparam \D[1]~61 .lut_mask = 16'hF5A0; -defparam \D[1]~61 .sum_lutc_input = "datac"; +defparam \D[2]~51 .lut_mask = 16'hAFA0; +defparam \D[2]~51 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y18_N22 -cycloneive_lcell_comb \D[1]~62 ( +// Location: LCCOMB_X24_Y10_N2 +cycloneive_lcell_comb \D[2]~52 ( // Equation(s): -// \D[1]~62_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout & (\z80_|data_pins_|dout [1] & ((\D[1]~61_combout ) # (!\Equal2~1_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\D[1]~61_combout )) # (!\Equal2~1_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datab(\Equal2~1_combout ), - .datac(\z80_|data_pins_|dout [1]), - .datad(\D[1]~61_combout ), - .cin(gnd), - .combout(\D[1]~62_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~62 .lut_mask = 16'hF531; -defparam \D[1]~62 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N12 -cycloneive_lcell_comb \D[2]~63 ( -// Equation(s): -// \D[2]~63_combout = (\Equal2~0_combout & (\D[2]~104_combout )) # (!\Equal2~0_combout & ((\D[2]~105_combout ))) - - .dataa(\Equal2~0_combout ), - .datab(gnd), - .datac(\D[2]~104_combout ), - .datad(\D[2]~105_combout ), - .cin(gnd), - .combout(\D[2]~63_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~63 .lut_mask = 16'hF5A0; -defparam \D[2]~63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N26 -cycloneive_lcell_comb \D[2]~64 ( -// Equation(s): -// \D[2]~64_combout = (\z80_|data_pins_|dout [2] & (((\D[2]~63_combout )) # (!\Equal2~1_combout ))) # (!\z80_|data_pins_|dout [2] & (!\z80_|pin_control_|bus_db_pin_oe~14_combout & ((\D[2]~63_combout ) # (!\Equal2~1_combout )))) +// \D[2]~52_combout = (\z80_|data_pins_|dout [2] & (((\D[2]~51_combout )) # (!\Equal2~1_combout ))) # (!\z80_|data_pins_|dout [2] & (!\z80_|pin_control_|bus_db_pin_oe~15_combout & ((\D[2]~51_combout ) # (!\Equal2~1_combout )))) .dataa(\z80_|data_pins_|dout [2]), .datab(\Equal2~1_combout ), - .datac(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datad(\D[2]~63_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .datad(\D[2]~51_combout ), .cin(gnd), - .combout(\D[2]~64_combout ), + .combout(\D[2]~52_combout ), .cout()); // synopsys translate_off -defparam \D[2]~64 .lut_mask = 16'hAF23; -defparam \D[2]~64 .sum_lutc_input = "datac"; +defparam \D[2]~52 .lut_mask = 16'hAF23; +defparam \D[2]~52 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N2 -cycloneive_lcell_comb \D[3]~75 ( +// Location: LCCOMB_X23_Y14_N18 +cycloneive_lcell_comb \D[3]~58 ( // Equation(s): -// \D[3]~75_combout = (\Equal2~0_combout & (\D[3]~69_combout )) # (!\Equal2~0_combout & ((\D[3]~108_combout ))) - - .dataa(\D[3]~69_combout ), - .datab(gnd), - .datac(\Equal2~0_combout ), - .datad(\D[3]~108_combout ), - .cin(gnd), - .combout(\D[3]~75_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~75 .lut_mask = 16'hAFA0; -defparam \D[3]~75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y15_N20 -cycloneive_lcell_comb \D[3]~76 ( -// Equation(s): -// \D[3]~76_combout = (\z80_|data_pins_|dout [3] & (((\D[3]~75_combout )) # (!\Equal2~1_combout ))) # (!\z80_|data_pins_|dout [3] & (!\z80_|pin_control_|bus_db_pin_oe~14_combout & ((\D[3]~75_combout ) # (!\Equal2~1_combout )))) - - .dataa(\z80_|data_pins_|dout [3]), - .datab(\Equal2~1_combout ), - .datac(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datad(\D[3]~75_combout ), - .cin(gnd), - .combout(\D[3]~76_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~76 .lut_mask = 16'hAF23; -defparam \D[3]~76 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N24 -cycloneive_lcell_comb \D[4]~82 ( -// Equation(s): -// \D[4]~82_combout = (\Equal2~0_combout & (\D[4]~81_combout )) # (!\Equal2~0_combout & ((\D[4]~109_combout ))) +// \D[3]~58_combout = (\Equal2~0_combout & (\D[3]~57_combout )) # (!\Equal2~0_combout & ((\D[3]~85_combout ))) .dataa(\Equal2~0_combout ), - .datab(\D[4]~81_combout ), + .datab(\D[3]~57_combout ), .datac(gnd), - .datad(\D[4]~109_combout ), + .datad(\D[3]~85_combout ), .cin(gnd), - .combout(\D[4]~82_combout ), + .combout(\D[3]~58_combout ), .cout()); // synopsys translate_off -defparam \D[4]~82 .lut_mask = 16'hDD88; -defparam \D[4]~82 .sum_lutc_input = "datac"; +defparam \D[3]~58 .lut_mask = 16'hDD88; +defparam \D[3]~58 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N26 -cycloneive_lcell_comb \D[4]~83 ( +// Location: LCCOMB_X24_Y14_N18 +cycloneive_lcell_comb \D[3]~59 ( // Equation(s): -// \D[4]~83_combout = (\Equal2~1_combout & (\D[4]~82_combout & ((\z80_|data_pins_|dout [4]) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) # (!\Equal2~1_combout & ((\z80_|data_pins_|dout [4]) # ((!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) +// \D[3]~59_combout = (\z80_|data_pins_|dout [3] & (((\D[3]~58_combout ) # (!\Equal2~1_combout )))) # (!\z80_|data_pins_|dout [3] & (!\z80_|pin_control_|bus_db_pin_oe~15_combout & ((\D[3]~58_combout ) # (!\Equal2~1_combout )))) + + .dataa(\z80_|data_pins_|dout [3]), + .datab(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .datac(\Equal2~1_combout ), + .datad(\D[3]~58_combout ), + .cin(gnd), + .combout(\D[3]~59_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~59 .lut_mask = 16'hBB0B; +defparam \D[3]~59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N0 +cycloneive_lcell_comb \D[4]~65 ( +// Equation(s): +// \D[4]~65_combout = (\Equal2~0_combout & (\D[4]~64_combout )) # (!\Equal2~0_combout & ((\D[4]~86_combout ))) + + .dataa(gnd), + .datab(\D[4]~64_combout ), + .datac(\Equal2~0_combout ), + .datad(\D[4]~86_combout ), + .cin(gnd), + .combout(\D[4]~65_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~65 .lut_mask = 16'hCFC0; +defparam \D[4]~65 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N22 +cycloneive_lcell_comb \D[4]~66 ( +// Equation(s): +// \D[4]~66_combout = (\Equal2~1_combout & (\D[4]~65_combout & ((\z80_|data_pins_|dout [4]) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout )))) # (!\Equal2~1_combout & ((\z80_|data_pins_|dout [4]) # ((!\z80_|pin_control_|bus_db_pin_oe~15_combout )))) .dataa(\Equal2~1_combout ), .datab(\z80_|data_pins_|dout [4]), - .datac(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datad(\D[4]~82_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .datad(\D[4]~65_combout ), .cin(gnd), - .combout(\D[4]~83_combout ), + .combout(\D[4]~66_combout ), .cout()); // synopsys translate_off -defparam \D[4]~83 .lut_mask = 16'hCF45; -defparam \D[4]~83 .sum_lutc_input = "datac"; +defparam \D[4]~66 .lut_mask = 16'hCF45; +defparam \D[4]~66 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N24 -cycloneive_lcell_comb \D[6]~92 ( +// Location: LCCOMB_X24_Y10_N20 +cycloneive_lcell_comb \D[6]~70 ( // Equation(s): -// \D[6]~92_combout = (\Equal2~0_combout & ((\D[6]~86_combout ))) # (!\Equal2~0_combout & (\D[6]~111_combout )) +// \D[6]~70_combout = (\Equal2~0_combout & ((\D[6]~69_combout ))) # (!\Equal2~0_combout & (\D[6]~88_combout )) - .dataa(gnd), - .datab(\Equal2~0_combout ), - .datac(\D[6]~111_combout ), - .datad(\D[6]~86_combout ), + .dataa(\Equal2~0_combout ), + .datab(gnd), + .datac(\D[6]~88_combout ), + .datad(\D[6]~69_combout ), .cin(gnd), - .combout(\D[6]~92_combout ), + .combout(\D[6]~70_combout ), .cout()); // synopsys translate_off -defparam \D[6]~92 .lut_mask = 16'hFC30; -defparam \D[6]~92 .sum_lutc_input = "datac"; +defparam \D[6]~70 .lut_mask = 16'hFA50; +defparam \D[6]~70 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N10 -cycloneive_lcell_comb \D[6]~93 ( +// Location: LCCOMB_X24_Y10_N10 +cycloneive_lcell_comb \D[6]~71 ( // Equation(s): -// \D[6]~93_combout = (\Equal2~1_combout & (\D[6]~92_combout & ((\z80_|data_pins_|dout [6]) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) # (!\Equal2~1_combout & ((\z80_|data_pins_|dout [6]) # ((!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) +// \D[6]~71_combout = (\z80_|data_pins_|dout [6] & (((\D[6]~70_combout )) # (!\Equal2~1_combout ))) # (!\z80_|data_pins_|dout [6] & (!\z80_|pin_control_|bus_db_pin_oe~15_combout & ((\D[6]~70_combout ) # (!\Equal2~1_combout )))) - .dataa(\Equal2~1_combout ), - .datab(\z80_|data_pins_|dout [6]), - .datac(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datad(\D[6]~92_combout ), + .dataa(\z80_|data_pins_|dout [6]), + .datab(\Equal2~1_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .datad(\D[6]~70_combout ), .cin(gnd), - .combout(\D[6]~93_combout ), + .combout(\D[6]~71_combout ), .cout()); // synopsys translate_off -defparam \D[6]~93 .lut_mask = 16'hCF45; -defparam \D[6]~93 .sum_lutc_input = "datac"; +defparam \D[6]~71 .lut_mask = 16'hAF23; +defparam \D[6]~71 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X43_Y17_N0 +// Location: LCCOMB_X27_Y13_N28 cycloneive_lcell_comb \z80_|nM1_int~3 ( // Equation(s): -// \z80_|nM1_int~3_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # (\z80_|sequencer_|DFFE_M1_ff~q ))) +// \z80_|nM1_int~3_combout = (\z80_|execute_|setM1~54_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # (\z80_|sequencer_|DFFE_M1_ff~q ))) - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|setM1~52_combout ), + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|execute_|setM1~54_combout ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), .cin(gnd), .combout(\z80_|nM1_int~3_combout ), .cout()); // synopsys translate_off -defparam \z80_|nM1_int~3 .lut_mask = 16'hFC00; +defparam \z80_|nM1_int~3 .lut_mask = 16'hCC88; defparam \z80_|nM1_int~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X43_Y17_N1 +// Location: FF_X27_Y13_N29 dffeas \z80_|memory_ifc_|SYNTHESIZED_WIRE_16 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|nM1_int~3_combout ), @@ -53491,7 +53258,7 @@ defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_16 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_16 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X43_Y17_N30 +// Location: LCCOMB_X27_Y11_N4 cycloneive_lcell_comb \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder ( // Equation(s): // \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder_combout = \z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q @@ -53508,7 +53275,7 @@ defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder .lut_mask = 16'hFF00; defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X43_Y17_N31 +// Location: FF_X27_Y11_N5 dffeas \z80_|memory_ifc_|SYNTHESIZED_WIRE_17 ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder_combout ), @@ -53527,7 +53294,7 @@ defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_17 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_17 .power_up = "low"; // synopsys translate_on -// Location: FF_X43_Y17_N25 +// Location: FF_X27_Y11_N11 dffeas \z80_|memory_ifc_|DFFE_mreq_ff2 ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), @@ -53546,32 +53313,32 @@ defparam \z80_|memory_ifc_|DFFE_mreq_ff2 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|DFFE_mreq_ff2 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X43_Y17_N24 +// Location: LCCOMB_X27_Y11_N10 cycloneive_lcell_comb \z80_|memory_ifc_|nMREQ_out~0 ( // Equation(s): // \z80_|memory_ifc_|nMREQ_out~0_combout = (\z80_|memory_ifc_|wait_mwr~q ) # ((\z80_|memory_ifc_|mwr_wr~q ) # ((\z80_|memory_ifc_|SYNTHESIZED_WIRE_17~q & !\z80_|memory_ifc_|DFFE_mreq_ff2~q ))) - .dataa(\z80_|memory_ifc_|SYNTHESIZED_WIRE_17~q ), - .datab(\z80_|memory_ifc_|wait_mwr~q ), + .dataa(\z80_|memory_ifc_|wait_mwr~q ), + .datab(\z80_|memory_ifc_|SYNTHESIZED_WIRE_17~q ), .datac(\z80_|memory_ifc_|DFFE_mreq_ff2~q ), .datad(\z80_|memory_ifc_|mwr_wr~q ), .cin(gnd), .combout(\z80_|memory_ifc_|nMREQ_out~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|memory_ifc_|nMREQ_out~0 .lut_mask = 16'hFFCE; +defparam \z80_|memory_ifc_|nMREQ_out~0 .lut_mask = 16'hFFAE; defparam \z80_|memory_ifc_|nMREQ_out~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X43_Y17_N2 +// Location: LCCOMB_X27_Y11_N16 cycloneive_lcell_comb \z80_|memory_ifc_|nMREQ_out~1 ( // Equation(s): -// \z80_|memory_ifc_|nMREQ_out~1_combout = (!\z80_|memory_ifc_|wait_mrd~q & (!\z80_|memory_ifc_|nMREQ_out~0_combout & (!\z80_|memory_ifc_|DFFE_mrd_ff3~q & !\z80_|memory_ifc_|nRD_out~0_combout ))) +// \z80_|memory_ifc_|nMREQ_out~1_combout = (!\z80_|memory_ifc_|wait_mrd~q & (!\z80_|memory_ifc_|nRD_out~0_combout & (!\z80_|memory_ifc_|DFFE_mrd_ff3~q & !\z80_|memory_ifc_|nMREQ_out~0_combout ))) .dataa(\z80_|memory_ifc_|wait_mrd~q ), - .datab(\z80_|memory_ifc_|nMREQ_out~0_combout ), + .datab(\z80_|memory_ifc_|nRD_out~0_combout ), .datac(\z80_|memory_ifc_|DFFE_mrd_ff3~q ), - .datad(\z80_|memory_ifc_|nRD_out~0_combout ), + .datad(\z80_|memory_ifc_|nMREQ_out~0_combout ), .cin(gnd), .combout(\z80_|memory_ifc_|nMREQ_out~1_combout ), .cout()); @@ -53593,7 +53360,7 @@ defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl .cl defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N0 +// Location: LCCOMB_X3_Y23_N28 cycloneive_lcell_comb \ula_|i2c_loader_|state.Idle~feeder ( // Equation(s): // \ula_|i2c_loader_|state.Idle~feeder_combout = VCC @@ -53610,7 +53377,7 @@ defparam \ula_|i2c_loader_|state.Idle~feeder .lut_mask = 16'hFFFF; defparam \ula_|i2c_loader_|state.Idle~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X4_Y24_N0 +// Location: LCCOMB_X1_Y24_N22 cycloneive_lcell_comb \ula_|i2c_loader_|divider[0]~15 ( // Equation(s): // \ula_|i2c_loader_|divider[0]~15_combout = !\ula_|i2c_loader_|divider [0] @@ -53627,7 +53394,7 @@ defparam \ula_|i2c_loader_|divider[0]~15 .lut_mask = 16'h0F0F; defparam \ula_|i2c_loader_|divider[0]~15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X4_Y24_N1 +// Location: FF_X1_Y24_N23 dffeas \ula_|i2c_loader_|divider[0] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[0]~15_combout ), @@ -53646,14 +53413,14 @@ defparam \ula_|i2c_loader_|divider[0] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X4_Y24_N10 +// Location: LCCOMB_X1_Y24_N0 cycloneive_lcell_comb \ula_|i2c_loader_|divider[1]~5 ( // Equation(s): -// \ula_|i2c_loader_|divider[1]~5_combout = (\ula_|i2c_loader_|divider [1] & (\ula_|i2c_loader_|divider [0] $ (VCC))) # (!\ula_|i2c_loader_|divider [1] & (\ula_|i2c_loader_|divider [0] & VCC)) -// \ula_|i2c_loader_|divider[1]~6 = CARRY((\ula_|i2c_loader_|divider [1] & \ula_|i2c_loader_|divider [0])) +// \ula_|i2c_loader_|divider[1]~5_combout = (\ula_|i2c_loader_|divider [0] & (\ula_|i2c_loader_|divider [1] $ (VCC))) # (!\ula_|i2c_loader_|divider [0] & (\ula_|i2c_loader_|divider [1] & VCC)) +// \ula_|i2c_loader_|divider[1]~6 = CARRY((\ula_|i2c_loader_|divider [0] & \ula_|i2c_loader_|divider [1])) - .dataa(\ula_|i2c_loader_|divider [1]), - .datab(\ula_|i2c_loader_|divider [0]), + .dataa(\ula_|i2c_loader_|divider [0]), + .datab(\ula_|i2c_loader_|divider [1]), .datac(gnd), .datad(vcc), .cin(gnd), @@ -53664,7 +53431,7 @@ defparam \ula_|i2c_loader_|divider[1]~5 .lut_mask = 16'h6688; defparam \ula_|i2c_loader_|divider[1]~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X4_Y24_N11 +// Location: FF_X1_Y24_N1 dffeas \ula_|i2c_loader_|divider[1] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[1]~5_combout ), @@ -53683,25 +53450,25 @@ defparam \ula_|i2c_loader_|divider[1] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X4_Y24_N12 +// Location: LCCOMB_X1_Y24_N2 cycloneive_lcell_comb \ula_|i2c_loader_|divider[2]~7 ( // Equation(s): // \ula_|i2c_loader_|divider[2]~7_combout = (\ula_|i2c_loader_|divider [2] & (!\ula_|i2c_loader_|divider[1]~6 )) # (!\ula_|i2c_loader_|divider [2] & ((\ula_|i2c_loader_|divider[1]~6 ) # (GND))) // \ula_|i2c_loader_|divider[2]~8 = CARRY((!\ula_|i2c_loader_|divider[1]~6 ) # (!\ula_|i2c_loader_|divider [2])) - .dataa(\ula_|i2c_loader_|divider [2]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|i2c_loader_|divider [2]), .datac(gnd), .datad(vcc), .cin(\ula_|i2c_loader_|divider[1]~6 ), .combout(\ula_|i2c_loader_|divider[2]~7_combout ), .cout(\ula_|i2c_loader_|divider[2]~8 )); // synopsys translate_off -defparam \ula_|i2c_loader_|divider[2]~7 .lut_mask = 16'h5A5F; +defparam \ula_|i2c_loader_|divider[2]~7 .lut_mask = 16'h3C3F; defparam \ula_|i2c_loader_|divider[2]~7 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X4_Y24_N13 +// Location: FF_X1_Y24_N3 dffeas \ula_|i2c_loader_|divider[2] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[2]~7_combout ), @@ -53720,7 +53487,7 @@ defparam \ula_|i2c_loader_|divider[2] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X4_Y24_N14 +// Location: LCCOMB_X1_Y24_N4 cycloneive_lcell_comb \ula_|i2c_loader_|divider[3]~9 ( // Equation(s): // \ula_|i2c_loader_|divider[3]~9_combout = (\ula_|i2c_loader_|divider [3] & (\ula_|i2c_loader_|divider[2]~8 $ (GND))) # (!\ula_|i2c_loader_|divider [3] & (!\ula_|i2c_loader_|divider[2]~8 & VCC)) @@ -53738,7 +53505,7 @@ defparam \ula_|i2c_loader_|divider[3]~9 .lut_mask = 16'hC30C; defparam \ula_|i2c_loader_|divider[3]~9 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X4_Y24_N15 +// Location: FF_X1_Y24_N5 dffeas \ula_|i2c_loader_|divider[3] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[3]~9_combout ), @@ -53757,25 +53524,42 @@ defparam \ula_|i2c_loader_|divider[3] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X4_Y24_N16 +// Location: LCCOMB_X1_Y24_N12 +cycloneive_lcell_comb \ula_|i2c_loader_|WideAnd0~0 ( +// Equation(s): +// \ula_|i2c_loader_|WideAnd0~0_combout = (((!\ula_|i2c_loader_|divider [2]) # (!\ula_|i2c_loader_|divider [3])) # (!\ula_|i2c_loader_|divider [1])) # (!\ula_|i2c_loader_|divider [0]) + + .dataa(\ula_|i2c_loader_|divider [0]), + .datab(\ula_|i2c_loader_|divider [1]), + .datac(\ula_|i2c_loader_|divider [3]), + .datad(\ula_|i2c_loader_|divider [2]), + .cin(gnd), + .combout(\ula_|i2c_loader_|WideAnd0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|WideAnd0~0 .lut_mask = 16'h7FFF; +defparam \ula_|i2c_loader_|WideAnd0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y24_N6 cycloneive_lcell_comb \ula_|i2c_loader_|divider[4]~11 ( // Equation(s): // \ula_|i2c_loader_|divider[4]~11_combout = (\ula_|i2c_loader_|divider [4] & (!\ula_|i2c_loader_|divider[3]~10 )) # (!\ula_|i2c_loader_|divider [4] & ((\ula_|i2c_loader_|divider[3]~10 ) # (GND))) // \ula_|i2c_loader_|divider[4]~12 = CARRY((!\ula_|i2c_loader_|divider[3]~10 ) # (!\ula_|i2c_loader_|divider [4])) - .dataa(gnd), - .datab(\ula_|i2c_loader_|divider [4]), + .dataa(\ula_|i2c_loader_|divider [4]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\ula_|i2c_loader_|divider[3]~10 ), .combout(\ula_|i2c_loader_|divider[4]~11_combout ), .cout(\ula_|i2c_loader_|divider[4]~12 )); // synopsys translate_off -defparam \ula_|i2c_loader_|divider[4]~11 .lut_mask = 16'h3C3F; +defparam \ula_|i2c_loader_|divider[4]~11 .lut_mask = 16'h5A5F; defparam \ula_|i2c_loader_|divider[4]~11 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X4_Y24_N17 +// Location: FF_X1_Y24_N7 dffeas \ula_|i2c_loader_|divider[4] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[4]~11_combout ), @@ -53794,24 +53578,24 @@ defparam \ula_|i2c_loader_|divider[4] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X4_Y24_N18 +// Location: LCCOMB_X1_Y24_N8 cycloneive_lcell_comb \ula_|i2c_loader_|divider[5]~13 ( // Equation(s): -// \ula_|i2c_loader_|divider[5]~13_combout = \ula_|i2c_loader_|divider[4]~12 $ (!\ula_|i2c_loader_|divider [5]) +// \ula_|i2c_loader_|divider[5]~13_combout = \ula_|i2c_loader_|divider [5] $ (!\ula_|i2c_loader_|divider[4]~12 ) .dataa(gnd), - .datab(gnd), + .datab(\ula_|i2c_loader_|divider [5]), .datac(gnd), - .datad(\ula_|i2c_loader_|divider [5]), + .datad(gnd), .cin(\ula_|i2c_loader_|divider[4]~12 ), .combout(\ula_|i2c_loader_|divider[5]~13_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|divider[5]~13 .lut_mask = 16'hF00F; +defparam \ula_|i2c_loader_|divider[5]~13 .lut_mask = 16'hC3C3; defparam \ula_|i2c_loader_|divider[5]~13 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X4_Y24_N19 +// Location: FF_X1_Y24_N9 dffeas \ula_|i2c_loader_|divider[5] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[5]~13_combout ), @@ -53830,41 +53614,24 @@ defparam \ula_|i2c_loader_|divider[5] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X4_Y24_N22 -cycloneive_lcell_comb \ula_|i2c_loader_|WideAnd0~0 ( -// Equation(s): -// \ula_|i2c_loader_|WideAnd0~0_combout = (((!\ula_|i2c_loader_|divider [2]) # (!\ula_|i2c_loader_|divider [3])) # (!\ula_|i2c_loader_|divider [0])) # (!\ula_|i2c_loader_|divider [1]) - - .dataa(\ula_|i2c_loader_|divider [1]), - .datab(\ula_|i2c_loader_|divider [0]), - .datac(\ula_|i2c_loader_|divider [3]), - .datad(\ula_|i2c_loader_|divider [2]), - .cin(gnd), - .combout(\ula_|i2c_loader_|WideAnd0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|WideAnd0~0 .lut_mask = 16'h7FFF; -defparam \ula_|i2c_loader_|WideAnd0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y24_N8 +// Location: LCCOMB_X1_Y24_N30 cycloneive_lcell_comb \ula_|i2c_loader_|WideAnd0 ( // Equation(s): -// \ula_|i2c_loader_|WideAnd0~combout = ((\ula_|i2c_loader_|WideAnd0~0_combout ) # (!\ula_|i2c_loader_|divider [4])) # (!\ula_|i2c_loader_|divider [5]) +// \ula_|i2c_loader_|WideAnd0~combout = (\ula_|i2c_loader_|WideAnd0~0_combout ) # ((!\ula_|i2c_loader_|divider [4]) # (!\ula_|i2c_loader_|divider [5])) - .dataa(gnd), - .datab(\ula_|i2c_loader_|divider [5]), - .datac(\ula_|i2c_loader_|WideAnd0~0_combout ), + .dataa(\ula_|i2c_loader_|WideAnd0~0_combout ), + .datab(gnd), + .datac(\ula_|i2c_loader_|divider [5]), .datad(\ula_|i2c_loader_|divider [4]), .cin(gnd), .combout(\ula_|i2c_loader_|WideAnd0~combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|WideAnd0 .lut_mask = 16'hF3FF; +defparam \ula_|i2c_loader_|WideAnd0 .lut_mask = 16'hAFFF; defparam \ula_|i2c_loader_|WideAnd0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X1_Y23_N1 +// Location: FF_X3_Y23_N29 dffeas \ula_|i2c_loader_|state.Idle ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|state.Idle~feeder_combout ), @@ -53883,7 +53650,7 @@ defparam \ula_|i2c_loader_|state.Idle .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|state.Idle .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N4 +// Location: LCCOMB_X3_Y23_N0 cycloneive_lcell_comb \ula_|i2c_loader_|phase~0 ( // Equation(s): // \ula_|i2c_loader_|phase~0_combout = (!\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|state.Idle~q ) @@ -53900,7 +53667,7 @@ defparam \ula_|i2c_loader_|phase~0 .lut_mask = 16'h0F00; defparam \ula_|i2c_loader_|phase~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X1_Y23_N5 +// Location: FF_X3_Y23_N1 dffeas \ula_|i2c_loader_|phase[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|phase~0_combout ), @@ -53919,7 +53686,7 @@ defparam \ula_|i2c_loader_|phase[0] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|phase[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N14 +// Location: LCCOMB_X3_Y23_N2 cycloneive_lcell_comb \ula_|i2c_loader_|phase~1 ( // Equation(s): // \ula_|i2c_loader_|phase~1_combout = (\ula_|i2c_loader_|state.Idle~q & (\ula_|i2c_loader_|phase [0] $ (\ula_|i2c_loader_|phase [1]))) @@ -53936,7 +53703,7 @@ defparam \ula_|i2c_loader_|phase~1 .lut_mask = 16'h3C00; defparam \ula_|i2c_loader_|phase~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X1_Y23_N15 +// Location: FF_X3_Y23_N3 dffeas \ula_|i2c_loader_|phase[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|phase~1_combout ), @@ -53955,59 +53722,182 @@ defparam \ula_|i2c_loader_|phase[1] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|phase[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y24_N2 +// Location: LCCOMB_X2_Y24_N2 cycloneive_lcell_comb \ula_|i2c_loader_|nbit~5 ( // Equation(s): -// \ula_|i2c_loader_|nbit~5_combout = (!\ula_|i2c_loader_|nbit [0]) # (!\ula_|i2c_loader_|state.Data~q ) +// \ula_|i2c_loader_|nbit~5_combout = (!\ula_|i2c_loader_|state.Data~q ) # (!\ula_|i2c_loader_|nbit [0]) - .dataa(\ula_|i2c_loader_|state.Data~q ), + .dataa(gnd), .datab(gnd), .datac(\ula_|i2c_loader_|nbit [0]), - .datad(gnd), + .datad(\ula_|i2c_loader_|state.Data~q ), .cin(gnd), .combout(\ula_|i2c_loader_|nbit~5_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|nbit~5 .lut_mask = 16'h5F5F; +defparam \ula_|i2c_loader_|nbit~5 .lut_mask = 16'h0FFF; defparam \ula_|i2c_loader_|nbit~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N14 -cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[0]~8 ( +// Location: LCCOMB_X2_Y23_N16 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Idle~0 ( // Equation(s): -// \ula_|i2c_loader_|thisbyte[0]~8_combout = \ula_|i2c_loader_|thisbyte [0] $ (VCC) -// \ula_|i2c_loader_|thisbyte[0]~9 = CARRY(\ula_|i2c_loader_|thisbyte [0]) +// \ula_|i2c_loader_|state.Idle~0_combout = (!\ula_|i2c_loader_|state.Stop~q & (!\ula_|i2c_loader_|state.Ack~q & (!\ula_|i2c_loader_|state.Start~q & !\ula_|i2c_loader_|state.Pause~q ))) - .dataa(gnd), - .datab(\ula_|i2c_loader_|thisbyte [0]), - .datac(gnd), - .datad(vcc), + .dataa(\ula_|i2c_loader_|state.Stop~q ), + .datab(\ula_|i2c_loader_|state.Ack~q ), + .datac(\ula_|i2c_loader_|state.Start~q ), + .datad(\ula_|i2c_loader_|state.Pause~q ), .cin(gnd), - .combout(\ula_|i2c_loader_|thisbyte[0]~8_combout ), - .cout(\ula_|i2c_loader_|thisbyte[0]~9 )); + .combout(\ula_|i2c_loader_|state.Idle~0_combout ), + .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[0]~8 .lut_mask = 16'h33CC; -defparam \ula_|i2c_loader_|thisbyte[0]~8 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|state.Idle~0 .lut_mask = 16'h0001; +defparam \ula_|i2c_loader_|state.Idle~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N8 +// Location: LCCOMB_X1_Y23_N30 cycloneive_lcell_comb \ula_|i2c_loader_|Mux42~0 ( // Equation(s): -// \ula_|i2c_loader_|Mux42~0_combout = (\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|phase [1]) +// \ula_|i2c_loader_|Mux42~0_combout = (\ula_|i2c_loader_|phase [1] & \ula_|i2c_loader_|phase [0]) .dataa(gnd), - .datab(gnd), + .datab(\ula_|i2c_loader_|phase [1]), .datac(\ula_|i2c_loader_|phase [0]), - .datad(\ula_|i2c_loader_|phase [1]), + .datad(gnd), .cin(gnd), .combout(\ula_|i2c_loader_|Mux42~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|Mux42~0 .lut_mask = 16'hF000; +defparam \ula_|i2c_loader_|Mux42~0 .lut_mask = 16'hC0C0; defparam \ula_|i2c_loader_|Mux42~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N28 +// Location: LCCOMB_X2_Y24_N0 +cycloneive_lcell_comb \ula_|i2c_loader_|nbit~6 ( +// Equation(s): +// \ula_|i2c_loader_|nbit~6_combout = (\ula_|i2c_loader_|nbit [1] $ (!\ula_|i2c_loader_|nbit [0])) # (!\ula_|i2c_loader_|state.Data~q ) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|state.Data~q ), + .datac(\ula_|i2c_loader_|nbit [1]), + .datad(\ula_|i2c_loader_|nbit [0]), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbit~6_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit~6 .lut_mask = 16'hF33F; +defparam \ula_|i2c_loader_|nbit~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y24_N1 +dffeas \ula_|i2c_loader_|nbit[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|nbit~6_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2c_loader_|nbit[0]~4_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|nbit [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit[1] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|nbit[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y24_N30 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Done~0 ( +// Equation(s): +// \ula_|i2c_loader_|state.Done~0_combout = (!\ula_|i2c_loader_|nbit [2] & (!\ula_|i2c_loader_|nbit [0] & (\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|nbit [1]))) + + .dataa(\ula_|i2c_loader_|nbit [2]), + .datab(\ula_|i2c_loader_|nbit [0]), + .datac(\ula_|i2c_loader_|state.Data~q ), + .datad(\ula_|i2c_loader_|nbit [1]), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Done~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Done~0 .lut_mask = 16'h0010; +defparam \ula_|i2c_loader_|state.Done~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N18 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Ack~0 ( +// Equation(s): +// \ula_|i2c_loader_|state.Ack~0_combout = ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Done~0_combout ) # (!\ula_|i2c_loader_|state.Idle~0_combout )))) # (!\ula_|i2c_loader_|state.Idle~q ) + + .dataa(\ula_|i2c_loader_|state.Idle~0_combout ), + .datab(\ula_|i2c_loader_|Mux42~0_combout ), + .datac(\ula_|i2c_loader_|state.Done~0_combout ), + .datad(\ula_|i2c_loader_|state.Idle~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Ack~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Ack~0 .lut_mask = 16'hC4FF; +defparam \ula_|i2c_loader_|state.Ack~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N24 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Ack~1 ( +// Equation(s): +// \ula_|i2c_loader_|state.Ack~1_combout = (\ula_|i2c_loader_|WideAnd0~combout & (((\ula_|i2c_loader_|state.Ack~q )))) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|state.Ack~0_combout & (\ula_|i2c_loader_|state.Data~q )) # +// (!\ula_|i2c_loader_|state.Ack~0_combout & ((\ula_|i2c_loader_|state.Ack~q ))))) + + .dataa(\ula_|i2c_loader_|WideAnd0~combout ), + .datab(\ula_|i2c_loader_|state.Data~q ), + .datac(\ula_|i2c_loader_|state.Ack~q ), + .datad(\ula_|i2c_loader_|state.Ack~0_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Ack~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Ack~1 .lut_mask = 16'hE4F0; +defparam \ula_|i2c_loader_|state.Ack~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y23_N25 +dffeas \ula_|i2c_loader_|state.Ack ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|state.Ack~1_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|state.Ack~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Ack .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|state.Ack .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N2 +cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~2 ( +// Equation(s): +// \ula_|i2c_loader_|nbit[0]~2_combout = (\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|phase [0])) # (!\ula_|i2c_loader_|phase [1]))) # (!\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|state.Ack~q )))) + + .dataa(\ula_|i2c_loader_|phase [1]), + .datab(\ula_|i2c_loader_|state.Ack~q ), + .datac(\ula_|i2c_loader_|phase [0]), + .datad(\ula_|i2c_loader_|state.Data~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbit[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit[0]~2 .lut_mask = 16'h5F33; +defparam \ula_|i2c_loader_|nbit[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N26 cycloneive_lcell_comb \ula_|i2c_loader_|nbyte~4 ( // Equation(s): // \ula_|i2c_loader_|nbyte~4_combout = (\ula_|i2c_loader_|state.Start~q ) # ((\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|nbyte [0] $ (!\ula_|i2c_loader_|nbyte [1])))) @@ -54024,14 +53914,14 @@ defparam \ula_|i2c_loader_|nbyte~4 .lut_mask = 16'hFF84; defparam \ula_|i2c_loader_|nbyte~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N26 +// Location: LCCOMB_X1_Y23_N4 cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[0]~7 ( // Equation(s): -// \ula_|i2c_loader_|thisbyte[0]~7_combout = (\ula_|i2c_loader_|phase [1] & \ula_|i2c_loader_|state.Ack~q ) +// \ula_|i2c_loader_|thisbyte[0]~7_combout = (\ula_|i2c_loader_|state.Ack~q & \ula_|i2c_loader_|phase [1]) .dataa(gnd), - .datab(\ula_|i2c_loader_|phase [1]), - .datac(\ula_|i2c_loader_|state.Ack~q ), + .datab(\ula_|i2c_loader_|state.Ack~q ), + .datac(\ula_|i2c_loader_|phase [1]), .datad(gnd), .cin(gnd), .combout(\ula_|i2c_loader_|thisbyte[0]~7_combout ), @@ -54051,13 +53941,13 @@ defparam \I2C_SDAT~input .bus_hold = "false"; defparam \I2C_SDAT~input .simulate_z_as = "z"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N20 +// Location: LCCOMB_X2_Y23_N20 cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~1 ( // Equation(s): -// \ula_|i2c_loader_|nbyte[0]~1_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|nbyte [0]) # ((\ula_|i2c_loader_|nbyte [1])))) # (!\ula_|i2c_loader_|phase [0] & (((\I2C_SDAT~input_o )))) +// \ula_|i2c_loader_|nbyte[0]~1_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|nbyte [1]) # ((\ula_|i2c_loader_|nbyte [0])))) # (!\ula_|i2c_loader_|phase [0] & (((\I2C_SDAT~input_o )))) - .dataa(\ula_|i2c_loader_|nbyte [0]), - .datab(\ula_|i2c_loader_|nbyte [1]), + .dataa(\ula_|i2c_loader_|nbyte [1]), + .datab(\ula_|i2c_loader_|nbyte [0]), .datac(\ula_|i2c_loader_|phase [0]), .datad(\I2C_SDAT~input_o ), .cin(gnd), @@ -54068,7 +53958,7 @@ defparam \ula_|i2c_loader_|nbyte[0]~1 .lut_mask = 16'hEFE0; defparam \ula_|i2c_loader_|nbyte[0]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N18 +// Location: LCCOMB_X2_Y23_N10 cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~2 ( // Equation(s): // \ula_|i2c_loader_|nbyte[0]~2_combout = (\ula_|i2c_loader_|state.Start~q & (\ula_|i2c_loader_|Mux42~0_combout )) # (!\ula_|i2c_loader_|state.Start~q & (((\ula_|i2c_loader_|thisbyte[0]~7_combout & \ula_|i2c_loader_|nbyte[0]~1_combout )))) @@ -54085,24 +53975,24 @@ defparam \ula_|i2c_loader_|nbyte[0]~2 .lut_mask = 16'hD888; defparam \ula_|i2c_loader_|nbyte[0]~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N24 +// Location: LCCOMB_X2_Y23_N8 cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~3 ( // Equation(s): -// \ula_|i2c_loader_|nbyte[0]~3_combout = (!\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|state.Idle~q & \ula_|i2c_loader_|nbyte[0]~2_combout )) +// \ula_|i2c_loader_|nbyte[0]~3_combout = (\ula_|i2c_loader_|state.Idle~q & (!\ula_|i2c_loader_|WideAnd0~combout & \ula_|i2c_loader_|nbyte[0]~2_combout )) .dataa(gnd), - .datab(\ula_|i2c_loader_|WideAnd0~combout ), - .datac(\ula_|i2c_loader_|state.Idle~q ), + .datab(\ula_|i2c_loader_|state.Idle~q ), + .datac(\ula_|i2c_loader_|WideAnd0~combout ), .datad(\ula_|i2c_loader_|nbyte[0]~2_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|nbyte[0]~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|nbyte[0]~3 .lut_mask = 16'h3000; +defparam \ula_|i2c_loader_|nbyte[0]~3 .lut_mask = 16'h0C00; defparam \ula_|i2c_loader_|nbyte[0]~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X1_Y23_N29 +// Location: FF_X2_Y23_N27 dffeas \ula_|i2c_loader_|nbyte[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|nbyte~4_combout ), @@ -54121,632 +54011,41 @@ defparam \ula_|i2c_loader_|nbyte[1] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|nbyte[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N18 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Stop~0 ( -// Equation(s): -// \ula_|i2c_loader_|state.Stop~0_combout = (!\ula_|i2c_loader_|nbyte [0] & (!\ula_|i2c_loader_|nbyte [1] & \ula_|i2c_loader_|state.Ack~q )) - - .dataa(\ula_|i2c_loader_|nbyte [0]), - .datab(\ula_|i2c_loader_|nbyte [1]), - .datac(\ula_|i2c_loader_|state.Ack~q ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Stop~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Stop~0 .lut_mask = 16'h1010; -defparam \ula_|i2c_loader_|state.Stop~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y24_N2 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Stop~1 ( -// Equation(s): -// \ula_|i2c_loader_|state.Stop~1_combout = (\ula_|i2c_loader_|WideAnd0~combout & (((\ula_|i2c_loader_|state.Stop~q )))) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Stop~0_combout ))) # -// (!\ula_|i2c_loader_|Mux42~0_combout & (\ula_|i2c_loader_|state.Stop~q )))) - - .dataa(\ula_|i2c_loader_|WideAnd0~combout ), - .datab(\ula_|i2c_loader_|Mux42~0_combout ), - .datac(\ula_|i2c_loader_|state.Stop~q ), - .datad(\ula_|i2c_loader_|state.Stop~0_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Stop~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Stop~1 .lut_mask = 16'hF4B0; -defparam \ula_|i2c_loader_|state.Stop~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X1_Y24_N3 -dffeas \ula_|i2c_loader_|state.Stop ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|state.Stop~1_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|state.Stop~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Stop .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|state.Stop .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y24_N20 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Idle~0 ( -// Equation(s): -// \ula_|i2c_loader_|state.Idle~0_combout = (!\ula_|i2c_loader_|state.Start~q & (!\ula_|i2c_loader_|state.Stop~q & (!\ula_|i2c_loader_|state.Pause~q & !\ula_|i2c_loader_|state.Ack~q ))) - - .dataa(\ula_|i2c_loader_|state.Start~q ), - .datab(\ula_|i2c_loader_|state.Stop~q ), - .datac(\ula_|i2c_loader_|state.Pause~q ), - .datad(\ula_|i2c_loader_|state.Ack~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Idle~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Idle~0 .lut_mask = 16'h0001; -defparam \ula_|i2c_loader_|state.Idle~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y24_N0 -cycloneive_lcell_comb \ula_|i2c_loader_|nbit~0 ( -// Equation(s): -// \ula_|i2c_loader_|nbit~0_combout = (\ula_|i2c_loader_|nbit [2] $ (((!\ula_|i2c_loader_|nbit [0] & !\ula_|i2c_loader_|nbit [1])))) # (!\ula_|i2c_loader_|state.Data~q ) - - .dataa(\ula_|i2c_loader_|state.Data~q ), - .datab(\ula_|i2c_loader_|nbit [0]), - .datac(\ula_|i2c_loader_|nbit [2]), - .datad(\ula_|i2c_loader_|nbit [1]), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbit~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit~0 .lut_mask = 16'hF5D7; -defparam \ula_|i2c_loader_|nbit~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X3_Y24_N1 -dffeas \ula_|i2c_loader_|nbit[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|nbit~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2c_loader_|nbit[0]~4_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|nbit [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit[2] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|nbit[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y24_N6 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Done~0 ( -// Equation(s): -// \ula_|i2c_loader_|state.Done~0_combout = (!\ula_|i2c_loader_|nbit [1] & (!\ula_|i2c_loader_|nbit [2] & (\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|nbit [0]))) - - .dataa(\ula_|i2c_loader_|nbit [1]), - .datab(\ula_|i2c_loader_|nbit [2]), - .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|nbit [0]), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Done~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Done~0 .lut_mask = 16'h0010; -defparam \ula_|i2c_loader_|state.Done~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N12 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Ack~0 ( -// Equation(s): -// \ula_|i2c_loader_|state.Ack~0_combout = ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Done~0_combout ) # (!\ula_|i2c_loader_|state.Idle~0_combout )))) # (!\ula_|i2c_loader_|state.Idle~q ) - - .dataa(\ula_|i2c_loader_|Mux42~0_combout ), - .datab(\ula_|i2c_loader_|state.Idle~0_combout ), - .datac(\ula_|i2c_loader_|state.Idle~q ), - .datad(\ula_|i2c_loader_|state.Done~0_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Ack~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Ack~0 .lut_mask = 16'hAF2F; -defparam \ula_|i2c_loader_|state.Ack~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N30 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Ack~1 ( -// Equation(s): -// \ula_|i2c_loader_|state.Ack~1_combout = (\ula_|i2c_loader_|state.Ack~0_combout & ((\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|state.Ack~q )) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|state.Data~q ))))) # -// (!\ula_|i2c_loader_|state.Ack~0_combout & (((\ula_|i2c_loader_|state.Ack~q )))) - - .dataa(\ula_|i2c_loader_|state.Ack~0_combout ), - .datab(\ula_|i2c_loader_|WideAnd0~combout ), - .datac(\ula_|i2c_loader_|state.Ack~q ), - .datad(\ula_|i2c_loader_|state.Data~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Ack~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Ack~1 .lut_mask = 16'hF2D0; -defparam \ula_|i2c_loader_|state.Ack~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X2_Y24_N31 -dffeas \ula_|i2c_loader_|state.Ack ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|state.Ack~1_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|state.Ack~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Ack .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|state.Ack .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N30 -cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[1]~5 ( -// Equation(s): -// \ula_|i2c_loader_|nbyte[1]~5_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|nbyte [0]) # ((\ula_|i2c_loader_|nbyte [1])))) # (!\ula_|i2c_loader_|phase [0] & (((\I2C_SDAT~input_o )))) - - .dataa(\ula_|i2c_loader_|nbyte [0]), - .datab(\ula_|i2c_loader_|nbyte [1]), - .datac(\ula_|i2c_loader_|phase [0]), - .datad(\I2C_SDAT~input_o ), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbyte[1]~5_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbyte[1]~5 .lut_mask = 16'hEFE0; -defparam \ula_|i2c_loader_|nbyte[1]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N8 -cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[0]~18 ( -// Equation(s): -// \ula_|i2c_loader_|thisbyte[0]~18_combout = (\ula_|i2c_loader_|phase [1] & (\ula_|i2c_loader_|state.Ack~q & (!\ula_|i2c_loader_|WideAnd0~combout & \ula_|i2c_loader_|nbyte[1]~5_combout ))) - - .dataa(\ula_|i2c_loader_|phase [1]), - .datab(\ula_|i2c_loader_|state.Ack~q ), - .datac(\ula_|i2c_loader_|WideAnd0~combout ), - .datad(\ula_|i2c_loader_|nbyte[1]~5_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|thisbyte[0]~18_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[0]~18 .lut_mask = 16'h0800; -defparam \ula_|i2c_loader_|thisbyte[0]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X2_Y23_N15 -dffeas \ula_|i2c_loader_|thisbyte[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|thisbyte[0]~8_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(!\ula_|i2c_loader_|phase [0]), - .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|thisbyte [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[0] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|thisbyte[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N16 -cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[1]~10 ( -// Equation(s): -// \ula_|i2c_loader_|thisbyte[1]~10_combout = (\ula_|i2c_loader_|thisbyte [1] & (!\ula_|i2c_loader_|thisbyte[0]~9 )) # (!\ula_|i2c_loader_|thisbyte [1] & ((\ula_|i2c_loader_|thisbyte[0]~9 ) # (GND))) -// \ula_|i2c_loader_|thisbyte[1]~11 = CARRY((!\ula_|i2c_loader_|thisbyte[0]~9 ) # (!\ula_|i2c_loader_|thisbyte [1])) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|thisbyte [1]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2c_loader_|thisbyte[0]~9 ), - .combout(\ula_|i2c_loader_|thisbyte[1]~10_combout ), - .cout(\ula_|i2c_loader_|thisbyte[1]~11 )); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[1]~10 .lut_mask = 16'h3C3F; -defparam \ula_|i2c_loader_|thisbyte[1]~10 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X2_Y23_N17 -dffeas \ula_|i2c_loader_|thisbyte[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|thisbyte[1]~10_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(!\ula_|i2c_loader_|phase [0]), - .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|thisbyte [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[1] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|thisbyte[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N18 -cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[2]~12 ( -// Equation(s): -// \ula_|i2c_loader_|thisbyte[2]~12_combout = (\ula_|i2c_loader_|thisbyte [2] & (\ula_|i2c_loader_|thisbyte[1]~11 $ (GND))) # (!\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte[1]~11 & VCC)) -// \ula_|i2c_loader_|thisbyte[2]~13 = CARRY((\ula_|i2c_loader_|thisbyte [2] & !\ula_|i2c_loader_|thisbyte[1]~11 )) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|thisbyte [2]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2c_loader_|thisbyte[1]~11 ), - .combout(\ula_|i2c_loader_|thisbyte[2]~12_combout ), - .cout(\ula_|i2c_loader_|thisbyte[2]~13 )); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[2]~12 .lut_mask = 16'hC30C; -defparam \ula_|i2c_loader_|thisbyte[2]~12 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X2_Y23_N19 -dffeas \ula_|i2c_loader_|thisbyte[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|thisbyte[2]~12_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(!\ula_|i2c_loader_|phase [0]), - .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|thisbyte [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[2] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|thisbyte[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N20 -cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[3]~14 ( -// Equation(s): -// \ula_|i2c_loader_|thisbyte[3]~14_combout = (\ula_|i2c_loader_|thisbyte [3] & (!\ula_|i2c_loader_|thisbyte[2]~13 )) # (!\ula_|i2c_loader_|thisbyte [3] & ((\ula_|i2c_loader_|thisbyte[2]~13 ) # (GND))) -// \ula_|i2c_loader_|thisbyte[3]~15 = CARRY((!\ula_|i2c_loader_|thisbyte[2]~13 ) # (!\ula_|i2c_loader_|thisbyte [3])) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|thisbyte [3]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2c_loader_|thisbyte[2]~13 ), - .combout(\ula_|i2c_loader_|thisbyte[3]~14_combout ), - .cout(\ula_|i2c_loader_|thisbyte[3]~15 )); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[3]~14 .lut_mask = 16'h3C3F; -defparam \ula_|i2c_loader_|thisbyte[3]~14 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X2_Y23_N21 -dffeas \ula_|i2c_loader_|thisbyte[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|thisbyte[3]~14_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(!\ula_|i2c_loader_|phase [0]), - .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|thisbyte [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[3] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|thisbyte[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N2 -cycloneive_lcell_comb \ula_|i2c_loader_|Equal2~0 ( -// Equation(s): -// \ula_|i2c_loader_|Equal2~0_combout = (\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte [1] & (!\ula_|i2c_loader_|thisbyte [0] & !\ula_|i2c_loader_|thisbyte [3]))) - - .dataa(\ula_|i2c_loader_|thisbyte [2]), - .datab(\ula_|i2c_loader_|thisbyte [1]), - .datac(\ula_|i2c_loader_|thisbyte [0]), - .datad(\ula_|i2c_loader_|thisbyte [3]), - .cin(gnd), - .combout(\ula_|i2c_loader_|Equal2~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|Equal2~0 .lut_mask = 16'h0002; -defparam \ula_|i2c_loader_|Equal2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y24_N26 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~0 ( -// Equation(s): -// \ula_|i2c_loader_|state.Pause~0_combout = (\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|phase [0])) # (!\ula_|i2c_loader_|phase [1]))) # (!\ula_|i2c_loader_|state.Data~q & (((\ula_|i2c_loader_|state.Stop~q )))) - - .dataa(\ula_|i2c_loader_|phase [1]), - .datab(\ula_|i2c_loader_|state.Stop~q ), - .datac(\ula_|i2c_loader_|phase [0]), - .datad(\ula_|i2c_loader_|state.Data~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Pause~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Pause~0 .lut_mask = 16'h5FCC; -defparam \ula_|i2c_loader_|state.Pause~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N22 -cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[4]~16 ( -// Equation(s): -// \ula_|i2c_loader_|thisbyte[4]~16_combout = \ula_|i2c_loader_|thisbyte [4] $ (!\ula_|i2c_loader_|thisbyte[3]~15 ) - - .dataa(\ula_|i2c_loader_|thisbyte [4]), - .datab(gnd), - .datac(gnd), - .datad(gnd), - .cin(\ula_|i2c_loader_|thisbyte[3]~15 ), - .combout(\ula_|i2c_loader_|thisbyte[4]~16_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[4]~16 .lut_mask = 16'hA5A5; -defparam \ula_|i2c_loader_|thisbyte[4]~16 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X2_Y23_N23 -dffeas \ula_|i2c_loader_|thisbyte[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|thisbyte[4]~16_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(!\ula_|i2c_loader_|phase [0]), - .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|thisbyte [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[4] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|thisbyte[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N20 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~1 ( -// Equation(s): -// \ula_|i2c_loader_|state.Pause~1_combout = (\ula_|i2c_loader_|state.Pause~0_combout & ((!\ula_|i2c_loader_|thisbyte [4]) # (!\ula_|i2c_loader_|Equal2~0_combout ))) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|Equal2~0_combout ), - .datac(\ula_|i2c_loader_|state.Pause~0_combout ), - .datad(\ula_|i2c_loader_|thisbyte [4]), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Pause~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Pause~1 .lut_mask = 16'h30F0; -defparam \ula_|i2c_loader_|state.Pause~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y24_N24 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Done~2 ( -// Equation(s): -// \ula_|i2c_loader_|state.Done~2_combout = (\ula_|i2c_loader_|scl_out~0_combout & (((\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|state.Done~1_combout )) # (!\ula_|i2c_loader_|state.Pause~q ))) # (!\ula_|i2c_loader_|scl_out~0_combout & -// (\ula_|i2c_loader_|state.Data~q & ((!\ula_|i2c_loader_|state.Done~1_combout )))) - - .dataa(\ula_|i2c_loader_|scl_out~0_combout ), - .datab(\ula_|i2c_loader_|state.Data~q ), - .datac(\ula_|i2c_loader_|state.Pause~q ), - .datad(\ula_|i2c_loader_|state.Done~1_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Done~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Done~2 .lut_mask = 16'h0ACE; -defparam \ula_|i2c_loader_|state.Done~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y24_N18 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~2 ( -// Equation(s): -// \ula_|i2c_loader_|state.Pause~2_combout = ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Start~q ) # (!\ula_|i2c_loader_|state.Done~2_combout )))) # (!\ula_|i2c_loader_|state.Idle~q ) - - .dataa(\ula_|i2c_loader_|state.Done~2_combout ), - .datab(\ula_|i2c_loader_|Mux42~0_combout ), - .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|state.Idle~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Pause~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Pause~2 .lut_mask = 16'hC4FF; -defparam \ula_|i2c_loader_|state.Pause~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y24_N22 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~3 ( -// Equation(s): -// \ula_|i2c_loader_|state.Pause~3_combout = (\ula_|i2c_loader_|WideAnd0~combout & (((\ula_|i2c_loader_|state.Pause~q )))) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|state.Pause~2_combout & (\ula_|i2c_loader_|state.Pause~1_combout )) # -// (!\ula_|i2c_loader_|state.Pause~2_combout & ((\ula_|i2c_loader_|state.Pause~q ))))) - - .dataa(\ula_|i2c_loader_|state.Pause~1_combout ), - .datab(\ula_|i2c_loader_|WideAnd0~combout ), - .datac(\ula_|i2c_loader_|state.Pause~q ), - .datad(\ula_|i2c_loader_|state.Pause~2_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Pause~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Pause~3 .lut_mask = 16'hE2F0; -defparam \ula_|i2c_loader_|state.Pause~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X1_Y24_N23 -dffeas \ula_|i2c_loader_|state.Pause ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|state.Pause~3_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|state.Pause~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Pause .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|state.Pause .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y24_N30 -cycloneive_lcell_comb \ula_|i2c_loader_|state~25 ( -// Equation(s): -// \ula_|i2c_loader_|state~25_combout = ((\ula_|i2c_loader_|Mux42~0_combout & (\ula_|i2c_loader_|state.Pause~q & !\ula_|i2c_loader_|state.Start~q )) # (!\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Start~q )))) # -// (!\ula_|i2c_loader_|state.Idle~q ) - - .dataa(\ula_|i2c_loader_|state.Pause~q ), - .datab(\ula_|i2c_loader_|Mux42~0_combout ), - .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|state.Idle~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state~25_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state~25 .lut_mask = 16'h38FF; -defparam \ula_|i2c_loader_|state~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X1_Y24_N31 -dffeas \ula_|i2c_loader_|state.Start ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|state~25_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(!\ula_|i2c_loader_|WideAnd0~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|state.Start~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Start .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|state.Start .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N10 -cycloneive_lcell_comb \ula_|i2c_loader_|nbyte~0 ( -// Equation(s): -// \ula_|i2c_loader_|nbyte~0_combout = (\ula_|i2c_loader_|phase [0] & (!\ula_|i2c_loader_|nbyte [0] & !\ula_|i2c_loader_|state.Start~q )) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|phase [0]), - .datac(\ula_|i2c_loader_|nbyte [0]), - .datad(\ula_|i2c_loader_|state.Start~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbyte~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbyte~0 .lut_mask = 16'h000C; -defparam \ula_|i2c_loader_|nbyte~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X1_Y23_N11 -dffeas \ula_|i2c_loader_|nbyte[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|nbyte~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2c_loader_|nbyte[0]~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|nbyte [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbyte[0] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|nbyte[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N22 +// Location: LCCOMB_X2_Y23_N28 cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~1 ( // Equation(s): -// \ula_|i2c_loader_|nbit[0]~1_combout = (!\ula_|i2c_loader_|nbyte [0] & (!\ula_|i2c_loader_|nbyte [1] & !\ula_|i2c_loader_|state.Data~q )) +// \ula_|i2c_loader_|nbit[0]~1_combout = (!\ula_|i2c_loader_|nbyte [1] & (!\ula_|i2c_loader_|nbyte [0] & !\ula_|i2c_loader_|state.Data~q )) - .dataa(\ula_|i2c_loader_|nbyte [0]), - .datab(gnd), - .datac(\ula_|i2c_loader_|nbyte [1]), - .datad(\ula_|i2c_loader_|state.Data~q ), + .dataa(\ula_|i2c_loader_|nbyte [1]), + .datab(\ula_|i2c_loader_|nbyte [0]), + .datac(\ula_|i2c_loader_|state.Data~q ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2c_loader_|nbit[0]~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|nbit[0]~1 .lut_mask = 16'h0005; +defparam \ula_|i2c_loader_|nbit[0]~1 .lut_mask = 16'h0101; defparam \ula_|i2c_loader_|nbit[0]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N0 -cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~2 ( -// Equation(s): -// \ula_|i2c_loader_|nbit[0]~2_combout = (\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|phase [1])) # (!\ula_|i2c_loader_|phase [0]))) # (!\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|state.Ack~q )))) - - .dataa(\ula_|i2c_loader_|phase [0]), - .datab(\ula_|i2c_loader_|state.Data~q ), - .datac(\ula_|i2c_loader_|state.Ack~q ), - .datad(\ula_|i2c_loader_|phase [1]), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbit[0]~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit[0]~2 .lut_mask = 16'h47CF; -defparam \ula_|i2c_loader_|nbit[0]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N6 +// Location: LCCOMB_X2_Y23_N30 cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~3 ( // Equation(s): -// \ula_|i2c_loader_|nbit[0]~3_combout = (!\ula_|i2c_loader_|state.Start~q & ((\ula_|i2c_loader_|nbit[0]~1_combout ) # ((\ula_|i2c_loader_|nbit[0]~2_combout ) # (\ula_|i2c_loader_|state.Done~0_combout )))) +// \ula_|i2c_loader_|nbit[0]~3_combout = (!\ula_|i2c_loader_|state.Start~q & ((\ula_|i2c_loader_|nbit[0]~2_combout ) # ((\ula_|i2c_loader_|nbit[0]~1_combout ) # (\ula_|i2c_loader_|state.Done~0_combout )))) - .dataa(\ula_|i2c_loader_|nbit[0]~1_combout ), - .datab(\ula_|i2c_loader_|nbit[0]~2_combout ), - .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|state.Done~0_combout ), + .dataa(\ula_|i2c_loader_|nbit[0]~2_combout ), + .datab(\ula_|i2c_loader_|nbit[0]~1_combout ), + .datac(\ula_|i2c_loader_|state.Done~0_combout ), + .datad(\ula_|i2c_loader_|state.Start~q ), .cin(gnd), .combout(\ula_|i2c_loader_|nbit[0]~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|nbit[0]~3 .lut_mask = 16'h0F0E; +defparam \ula_|i2c_loader_|nbit[0]~3 .lut_mask = 16'h00FE; defparam \ula_|i2c_loader_|nbit[0]~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N4 +// Location: LCCOMB_X2_Y23_N0 cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~4 ( // Equation(s): // \ula_|i2c_loader_|nbit[0]~4_combout = (!\ula_|i2c_loader_|nbit[0]~3_combout & (\ula_|i2c_loader_|Mux42~0_combout & (!\ula_|i2c_loader_|WideAnd0~combout & \ula_|i2c_loader_|state.Idle~q ))) @@ -54763,7 +54062,7 @@ defparam \ula_|i2c_loader_|nbit[0]~4 .lut_mask = 16'h0400; defparam \ula_|i2c_loader_|nbit[0]~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y24_N3 +// Location: FF_X2_Y24_N3 dffeas \ula_|i2c_loader_|nbit[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|nbit~5_combout ), @@ -54782,27 +54081,27 @@ defparam \ula_|i2c_loader_|nbit[0] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|nbit[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y24_N12 -cycloneive_lcell_comb \ula_|i2c_loader_|nbit~6 ( +// Location: LCCOMB_X2_Y24_N12 +cycloneive_lcell_comb \ula_|i2c_loader_|nbit~0 ( // Equation(s): -// \ula_|i2c_loader_|nbit~6_combout = (\ula_|i2c_loader_|nbit [1] $ (!\ula_|i2c_loader_|nbit [0])) # (!\ula_|i2c_loader_|state.Data~q ) +// \ula_|i2c_loader_|nbit~0_combout = (\ula_|i2c_loader_|nbit [2] $ (((!\ula_|i2c_loader_|nbit [0] & !\ula_|i2c_loader_|nbit [1])))) # (!\ula_|i2c_loader_|state.Data~q ) .dataa(\ula_|i2c_loader_|state.Data~q ), - .datab(gnd), - .datac(\ula_|i2c_loader_|nbit [1]), - .datad(\ula_|i2c_loader_|nbit [0]), + .datab(\ula_|i2c_loader_|nbit [0]), + .datac(\ula_|i2c_loader_|nbit [2]), + .datad(\ula_|i2c_loader_|nbit [1]), .cin(gnd), - .combout(\ula_|i2c_loader_|nbit~6_combout ), + .combout(\ula_|i2c_loader_|nbit~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|nbit~6 .lut_mask = 16'hF55F; -defparam \ula_|i2c_loader_|nbit~6 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|nbit~0 .lut_mask = 16'hF5D7; +defparam \ula_|i2c_loader_|nbit~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y24_N13 -dffeas \ula_|i2c_loader_|nbit[1] ( +// Location: FF_X2_Y24_N13 +dffeas \ula_|i2c_loader_|nbit[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|nbit~6_combout ), + .d(\ula_|i2c_loader_|nbit~0_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -54811,22 +54110,22 @@ dffeas \ula_|i2c_loader_|nbit[1] ( .ena(\ula_|i2c_loader_|nbit[0]~4_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\ula_|i2c_loader_|nbit [1]), + .q(\ula_|i2c_loader_|nbit [2]), .prn(vcc)); // synopsys translate_off -defparam \ula_|i2c_loader_|nbit[1] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|nbit[1] .power_up = "low"; +defparam \ula_|i2c_loader_|nbit[2] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|nbit[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y24_N16 +// Location: LCCOMB_X2_Y24_N28 cycloneive_lcell_comb \ula_|i2c_loader_|state.Done~1 ( // Equation(s): -// \ula_|i2c_loader_|state.Done~1_combout = (!\ula_|i2c_loader_|nbit [1] & (!\ula_|i2c_loader_|nbit [2] & !\ula_|i2c_loader_|nbit [0])) +// \ula_|i2c_loader_|state.Done~1_combout = (!\ula_|i2c_loader_|nbit [2] & (!\ula_|i2c_loader_|nbit [0] & !\ula_|i2c_loader_|nbit [1])) - .dataa(\ula_|i2c_loader_|nbit [1]), - .datab(\ula_|i2c_loader_|nbit [2]), + .dataa(\ula_|i2c_loader_|nbit [2]), + .datab(\ula_|i2c_loader_|nbit [0]), .datac(gnd), - .datad(\ula_|i2c_loader_|nbit [0]), + .datad(\ula_|i2c_loader_|nbit [1]), .cin(gnd), .combout(\ula_|i2c_loader_|state.Done~1_combout ), .cout()); @@ -54835,75 +54134,75 @@ defparam \ula_|i2c_loader_|state.Done~1 .lut_mask = 16'h0011; defparam \ula_|i2c_loader_|state.Done~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N6 +// Location: LCCOMB_X1_Y23_N18 cycloneive_lcell_comb \ula_|i2c_loader_|state~27 ( // Equation(s): // \ula_|i2c_loader_|state~27_combout = ((!\ula_|i2c_loader_|state.Done~1_combout ) # (!\ula_|i2c_loader_|phase [0])) # (!\ula_|i2c_loader_|phase [1]) .dataa(\ula_|i2c_loader_|phase [1]), - .datab(gnd), - .datac(\ula_|i2c_loader_|phase [0]), - .datad(\ula_|i2c_loader_|state.Done~1_combout ), + .datab(\ula_|i2c_loader_|phase [0]), + .datac(\ula_|i2c_loader_|state.Done~1_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2c_loader_|state~27_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|state~27 .lut_mask = 16'h5FFF; +defparam \ula_|i2c_loader_|state~27 .lut_mask = 16'h7F7F; defparam \ula_|i2c_loader_|state~27 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N28 +// Location: LCCOMB_X2_Y23_N14 cycloneive_lcell_comb \ula_|i2c_loader_|state~24 ( // Equation(s): // \ula_|i2c_loader_|state~24_combout = (\ula_|i2c_loader_|state.Ack~q & ((\ula_|i2c_loader_|nbyte [0]) # (\ula_|i2c_loader_|nbyte [1]))) - .dataa(\ula_|i2c_loader_|nbyte [0]), - .datab(\ula_|i2c_loader_|nbyte [1]), - .datac(\ula_|i2c_loader_|state.Ack~q ), - .datad(gnd), + .dataa(gnd), + .datab(\ula_|i2c_loader_|nbyte [0]), + .datac(\ula_|i2c_loader_|nbyte [1]), + .datad(\ula_|i2c_loader_|state.Ack~q ), .cin(gnd), .combout(\ula_|i2c_loader_|state~24_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|state~24 .lut_mask = 16'hE0E0; +defparam \ula_|i2c_loader_|state~24 .lut_mask = 16'hFC00; defparam \ula_|i2c_loader_|state~24 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N16 +// Location: LCCOMB_X2_Y23_N2 cycloneive_lcell_comb \ula_|i2c_loader_|state~26 ( // Equation(s): -// \ula_|i2c_loader_|state~26_combout = (\ula_|i2c_loader_|phase [1] & (\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|state~24_combout )) +// \ula_|i2c_loader_|state~26_combout = (\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|state~24_combout & \ula_|i2c_loader_|phase [1])) - .dataa(\ula_|i2c_loader_|phase [1]), - .datab(gnd), - .datac(\ula_|i2c_loader_|phase [0]), - .datad(\ula_|i2c_loader_|state~24_combout ), + .dataa(gnd), + .datab(\ula_|i2c_loader_|phase [0]), + .datac(\ula_|i2c_loader_|state~24_combout ), + .datad(\ula_|i2c_loader_|phase [1]), .cin(gnd), .combout(\ula_|i2c_loader_|state~26_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|state~26 .lut_mask = 16'hA000; +defparam \ula_|i2c_loader_|state~26 .lut_mask = 16'hC000; defparam \ula_|i2c_loader_|state~26 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N28 +// Location: LCCOMB_X1_Y23_N0 cycloneive_lcell_comb \ula_|i2c_loader_|state.Data~0 ( // Equation(s): // \ula_|i2c_loader_|state.Data~0_combout = (\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|state~27_combout )) # (!\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|state~26_combout ))) - .dataa(\ula_|i2c_loader_|state~27_combout ), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|i2c_loader_|state~27_combout ), .datac(\ula_|i2c_loader_|state.Data~q ), .datad(\ula_|i2c_loader_|state~26_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|state.Data~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|state.Data~0 .lut_mask = 16'hAFA0; +defparam \ula_|i2c_loader_|state.Data~0 .lut_mask = 16'hCFC0; defparam \ula_|i2c_loader_|state.Data~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X1_Y24_N29 +// Location: FF_X1_Y23_N1 dffeas \ula_|i2c_loader_|state.Data ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|state.Data~0_combout ), @@ -54922,24 +54221,492 @@ defparam \ula_|i2c_loader_|state.Data .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|state.Data .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N12 -cycloneive_lcell_comb \ula_|i2c_loader_|scl_out~0 ( +// Location: LCCOMB_X1_Y23_N16 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Done~2 ( // Equation(s): -// \ula_|i2c_loader_|scl_out~0_combout = (!\ula_|i2c_loader_|state.Data~q & (!\ula_|i2c_loader_|state.Ack~q & !\ula_|i2c_loader_|state.Stop~q )) +// \ula_|i2c_loader_|state.Done~2_combout = (\ula_|i2c_loader_|scl_out~0_combout & (((\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|state.Done~1_combout )) # (!\ula_|i2c_loader_|state.Pause~q ))) # (!\ula_|i2c_loader_|scl_out~0_combout & +// (\ula_|i2c_loader_|state.Data~q & (!\ula_|i2c_loader_|state.Done~1_combout ))) + + .dataa(\ula_|i2c_loader_|scl_out~0_combout ), + .datab(\ula_|i2c_loader_|state.Data~q ), + .datac(\ula_|i2c_loader_|state.Done~1_combout ), + .datad(\ula_|i2c_loader_|state.Pause~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Done~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Done~2 .lut_mask = 16'h0CAE; +defparam \ula_|i2c_loader_|state.Done~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N10 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~1 ( +// Equation(s): +// \ula_|i2c_loader_|state.Pause~1_combout = ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Start~q ) # (!\ula_|i2c_loader_|state.Done~2_combout )))) # (!\ula_|i2c_loader_|state.Idle~q ) + + .dataa(\ula_|i2c_loader_|state.Start~q ), + .datab(\ula_|i2c_loader_|state.Done~2_combout ), + .datac(\ula_|i2c_loader_|Mux42~0_combout ), + .datad(\ula_|i2c_loader_|state.Idle~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Pause~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Pause~1 .lut_mask = 16'hB0FF; +defparam \ula_|i2c_loader_|state.Pause~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X5_Y23_N18 +cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[0]~8 ( +// Equation(s): +// \ula_|i2c_loader_|thisbyte[0]~8_combout = \ula_|i2c_loader_|thisbyte [0] $ (VCC) +// \ula_|i2c_loader_|thisbyte[0]~9 = CARRY(\ula_|i2c_loader_|thisbyte [0]) .dataa(gnd), + .datab(\ula_|i2c_loader_|thisbyte [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\ula_|i2c_loader_|thisbyte[0]~8_combout ), + .cout(\ula_|i2c_loader_|thisbyte[0]~9 )); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[0]~8 .lut_mask = 16'h33CC; +defparam \ula_|i2c_loader_|thisbyte[0]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X5_Y23_N28 +cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[1]~5 ( +// Equation(s): +// \ula_|i2c_loader_|nbyte[1]~5_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|nbyte [0]) # ((\ula_|i2c_loader_|nbyte [1])))) # (!\ula_|i2c_loader_|phase [0] & (((\I2C_SDAT~input_o )))) + + .dataa(\ula_|i2c_loader_|phase [0]), + .datab(\ula_|i2c_loader_|nbyte [0]), + .datac(\ula_|i2c_loader_|nbyte [1]), + .datad(\I2C_SDAT~input_o ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbyte[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbyte[1]~5 .lut_mask = 16'hFDA8; +defparam \ula_|i2c_loader_|nbyte[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X5_Y23_N16 +cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[0]~18 ( +// Equation(s): +// \ula_|i2c_loader_|thisbyte[0]~18_combout = (\ula_|i2c_loader_|state.Ack~q & (\ula_|i2c_loader_|phase [1] & (!\ula_|i2c_loader_|WideAnd0~combout & \ula_|i2c_loader_|nbyte[1]~5_combout ))) + + .dataa(\ula_|i2c_loader_|state.Ack~q ), + .datab(\ula_|i2c_loader_|phase [1]), + .datac(\ula_|i2c_loader_|WideAnd0~combout ), + .datad(\ula_|i2c_loader_|nbyte[1]~5_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|thisbyte[0]~18_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[0]~18 .lut_mask = 16'h0800; +defparam \ula_|i2c_loader_|thisbyte[0]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X5_Y23_N19 +dffeas \ula_|i2c_loader_|thisbyte[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|thisbyte[0]~8_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\ula_|i2c_loader_|phase [0]), + .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|thisbyte [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[0] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|thisbyte[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X5_Y23_N20 +cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[1]~10 ( +// Equation(s): +// \ula_|i2c_loader_|thisbyte[1]~10_combout = (\ula_|i2c_loader_|thisbyte [1] & (!\ula_|i2c_loader_|thisbyte[0]~9 )) # (!\ula_|i2c_loader_|thisbyte [1] & ((\ula_|i2c_loader_|thisbyte[0]~9 ) # (GND))) +// \ula_|i2c_loader_|thisbyte[1]~11 = CARRY((!\ula_|i2c_loader_|thisbyte[0]~9 ) # (!\ula_|i2c_loader_|thisbyte [1])) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|thisbyte [1]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2c_loader_|thisbyte[0]~9 ), + .combout(\ula_|i2c_loader_|thisbyte[1]~10_combout ), + .cout(\ula_|i2c_loader_|thisbyte[1]~11 )); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[1]~10 .lut_mask = 16'h3C3F; +defparam \ula_|i2c_loader_|thisbyte[1]~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X5_Y23_N21 +dffeas \ula_|i2c_loader_|thisbyte[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|thisbyte[1]~10_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\ula_|i2c_loader_|phase [0]), + .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|thisbyte [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[1] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|thisbyte[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X5_Y23_N22 +cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[2]~12 ( +// Equation(s): +// \ula_|i2c_loader_|thisbyte[2]~12_combout = (\ula_|i2c_loader_|thisbyte [2] & (\ula_|i2c_loader_|thisbyte[1]~11 $ (GND))) # (!\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte[1]~11 & VCC)) +// \ula_|i2c_loader_|thisbyte[2]~13 = CARRY((\ula_|i2c_loader_|thisbyte [2] & !\ula_|i2c_loader_|thisbyte[1]~11 )) + + .dataa(\ula_|i2c_loader_|thisbyte [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2c_loader_|thisbyte[1]~11 ), + .combout(\ula_|i2c_loader_|thisbyte[2]~12_combout ), + .cout(\ula_|i2c_loader_|thisbyte[2]~13 )); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[2]~12 .lut_mask = 16'hA50A; +defparam \ula_|i2c_loader_|thisbyte[2]~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X5_Y23_N23 +dffeas \ula_|i2c_loader_|thisbyte[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|thisbyte[2]~12_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\ula_|i2c_loader_|phase [0]), + .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|thisbyte [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[2] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|thisbyte[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X5_Y23_N24 +cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[3]~14 ( +// Equation(s): +// \ula_|i2c_loader_|thisbyte[3]~14_combout = (\ula_|i2c_loader_|thisbyte [3] & (!\ula_|i2c_loader_|thisbyte[2]~13 )) # (!\ula_|i2c_loader_|thisbyte [3] & ((\ula_|i2c_loader_|thisbyte[2]~13 ) # (GND))) +// \ula_|i2c_loader_|thisbyte[3]~15 = CARRY((!\ula_|i2c_loader_|thisbyte[2]~13 ) # (!\ula_|i2c_loader_|thisbyte [3])) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|thisbyte [3]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2c_loader_|thisbyte[2]~13 ), + .combout(\ula_|i2c_loader_|thisbyte[3]~14_combout ), + .cout(\ula_|i2c_loader_|thisbyte[3]~15 )); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[3]~14 .lut_mask = 16'h3C3F; +defparam \ula_|i2c_loader_|thisbyte[3]~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X5_Y23_N25 +dffeas \ula_|i2c_loader_|thisbyte[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|thisbyte[3]~14_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\ula_|i2c_loader_|phase [0]), + .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|thisbyte [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[3] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|thisbyte[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y23_N4 +cycloneive_lcell_comb \ula_|i2c_loader_|Equal2~0 ( +// Equation(s): +// \ula_|i2c_loader_|Equal2~0_combout = (\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte [3] & (!\ula_|i2c_loader_|thisbyte [1] & !\ula_|i2c_loader_|thisbyte [0]))) + + .dataa(\ula_|i2c_loader_|thisbyte [2]), + .datab(\ula_|i2c_loader_|thisbyte [3]), + .datac(\ula_|i2c_loader_|thisbyte [1]), + .datad(\ula_|i2c_loader_|thisbyte [0]), + .cin(gnd), + .combout(\ula_|i2c_loader_|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|Equal2~0 .lut_mask = 16'h0002; +defparam \ula_|i2c_loader_|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X5_Y23_N26 +cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[4]~16 ( +// Equation(s): +// \ula_|i2c_loader_|thisbyte[4]~16_combout = \ula_|i2c_loader_|thisbyte [4] $ (!\ula_|i2c_loader_|thisbyte[3]~15 ) + + .dataa(\ula_|i2c_loader_|thisbyte [4]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\ula_|i2c_loader_|thisbyte[3]~15 ), + .combout(\ula_|i2c_loader_|thisbyte[4]~16_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[4]~16 .lut_mask = 16'hA5A5; +defparam \ula_|i2c_loader_|thisbyte[4]~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X5_Y23_N27 +dffeas \ula_|i2c_loader_|thisbyte[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|thisbyte[4]~16_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\ula_|i2c_loader_|phase [0]), + .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|thisbyte [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[4] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|thisbyte[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y23_N30 +cycloneive_lcell_comb \ula_|i2c_loader_|Equal2~1 ( +// Equation(s): +// \ula_|i2c_loader_|Equal2~1_combout = (\ula_|i2c_loader_|Equal2~0_combout & \ula_|i2c_loader_|thisbyte [4]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|i2c_loader_|Equal2~0_combout ), + .datad(\ula_|i2c_loader_|thisbyte [4]), + .cin(gnd), + .combout(\ula_|i2c_loader_|Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|Equal2~1 .lut_mask = 16'hF000; +defparam \ula_|i2c_loader_|Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N22 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~0 ( +// Equation(s): +// \ula_|i2c_loader_|state.Pause~0_combout = (!\ula_|i2c_loader_|Equal2~1_combout & ((\ula_|i2c_loader_|state.Data~q & ((!\ula_|i2c_loader_|Mux42~0_combout ))) # (!\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|state.Stop~q )))) + + .dataa(\ula_|i2c_loader_|state.Stop~q ), + .datab(\ula_|i2c_loader_|Mux42~0_combout ), + .datac(\ula_|i2c_loader_|state.Data~q ), + .datad(\ula_|i2c_loader_|Equal2~1_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Pause~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Pause~0 .lut_mask = 16'h003A; +defparam \ula_|i2c_loader_|state.Pause~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N24 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~2 ( +// Equation(s): +// \ula_|i2c_loader_|state.Pause~2_combout = (\ula_|i2c_loader_|state.Pause~1_combout & ((\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|state.Pause~q )) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|state.Pause~0_combout ))))) # +// (!\ula_|i2c_loader_|state.Pause~1_combout & (((\ula_|i2c_loader_|state.Pause~q )))) + + .dataa(\ula_|i2c_loader_|state.Pause~1_combout ), + .datab(\ula_|i2c_loader_|WideAnd0~combout ), + .datac(\ula_|i2c_loader_|state.Pause~q ), + .datad(\ula_|i2c_loader_|state.Pause~0_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Pause~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Pause~2 .lut_mask = 16'hF2D0; +defparam \ula_|i2c_loader_|state.Pause~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X1_Y23_N25 +dffeas \ula_|i2c_loader_|state.Pause ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|state.Pause~2_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|state.Pause~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Pause .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|state.Pause .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y23_N26 +cycloneive_lcell_comb \ula_|i2c_loader_|state~25 ( +// Equation(s): +// \ula_|i2c_loader_|state~25_combout = ((\ula_|i2c_loader_|Mux42~0_combout & (\ula_|i2c_loader_|state.Pause~q & !\ula_|i2c_loader_|state.Start~q )) # (!\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Start~q )))) # +// (!\ula_|i2c_loader_|state.Idle~q ) + + .dataa(\ula_|i2c_loader_|state.Pause~q ), + .datab(\ula_|i2c_loader_|Mux42~0_combout ), + .datac(\ula_|i2c_loader_|state.Start~q ), + .datad(\ula_|i2c_loader_|state.Idle~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state~25_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state~25 .lut_mask = 16'h38FF; +defparam \ula_|i2c_loader_|state~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X3_Y23_N27 +dffeas \ula_|i2c_loader_|state.Start ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|state~25_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(!\ula_|i2c_loader_|WideAnd0~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|state.Start~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Start .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|state.Start .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N4 +cycloneive_lcell_comb \ula_|i2c_loader_|nbyte~0 ( +// Equation(s): +// \ula_|i2c_loader_|nbyte~0_combout = (\ula_|i2c_loader_|phase [0] & (!\ula_|i2c_loader_|nbyte [0] & !\ula_|i2c_loader_|state.Start~q )) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|phase [0]), + .datac(\ula_|i2c_loader_|nbyte [0]), + .datad(\ula_|i2c_loader_|state.Start~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbyte~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbyte~0 .lut_mask = 16'h000C; +defparam \ula_|i2c_loader_|nbyte~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y23_N5 +dffeas \ula_|i2c_loader_|nbyte[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|nbyte~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2c_loader_|nbyte[0]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|nbyte [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbyte[0] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|nbyte[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N12 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Stop~0 ( +// Equation(s): +// \ula_|i2c_loader_|state.Stop~0_combout = (!\ula_|i2c_loader_|nbyte [0] & (!\ula_|i2c_loader_|nbyte [1] & \ula_|i2c_loader_|state.Ack~q )) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|nbyte [0]), + .datac(\ula_|i2c_loader_|nbyte [1]), + .datad(\ula_|i2c_loader_|state.Ack~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Stop~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Stop~0 .lut_mask = 16'h0300; +defparam \ula_|i2c_loader_|state.Stop~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N6 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Stop~1 ( +// Equation(s): +// \ula_|i2c_loader_|state.Stop~1_combout = (\ula_|i2c_loader_|WideAnd0~combout & (((\ula_|i2c_loader_|state.Stop~q )))) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|Mux42~0_combout & (\ula_|i2c_loader_|state.Stop~0_combout )) # +// (!\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Stop~q ))))) + + .dataa(\ula_|i2c_loader_|state.Stop~0_combout ), + .datab(\ula_|i2c_loader_|WideAnd0~combout ), + .datac(\ula_|i2c_loader_|state.Stop~q ), + .datad(\ula_|i2c_loader_|Mux42~0_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Stop~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Stop~1 .lut_mask = 16'hE2F0; +defparam \ula_|i2c_loader_|state.Stop~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y23_N7 +dffeas \ula_|i2c_loader_|state.Stop ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|state.Stop~1_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|state.Stop~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Stop .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|state.Stop .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N22 +cycloneive_lcell_comb \ula_|i2c_loader_|scl_out~0 ( +// Equation(s): +// \ula_|i2c_loader_|scl_out~0_combout = (!\ula_|i2c_loader_|state.Stop~q & (!\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|state.Ack~q )) + + .dataa(\ula_|i2c_loader_|state.Stop~q ), .datab(\ula_|i2c_loader_|state.Data~q ), - .datac(\ula_|i2c_loader_|state.Ack~q ), - .datad(\ula_|i2c_loader_|state.Stop~q ), + .datac(gnd), + .datad(\ula_|i2c_loader_|state.Ack~q ), .cin(gnd), .combout(\ula_|i2c_loader_|scl_out~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|scl_out~0 .lut_mask = 16'h0003; +defparam \ula_|i2c_loader_|scl_out~0 .lut_mask = 16'h0011; defparam \ula_|i2c_loader_|scl_out~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X1_Y23_N13 +// Location: FF_X1_Y23_N7 dffeas \ula_|i2c_loader_|scl_out~_Duplicate_1 ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|scl_out~2_combout ), @@ -54958,7 +54725,7 @@ defparam \ula_|i2c_loader_|scl_out~_Duplicate_1 .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|scl_out~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N16 +// Location: LCCOMB_X1_Y23_N8 cycloneive_lcell_comb \ula_|i2c_loader_|scl_out~1 ( // Equation(s): // \ula_|i2c_loader_|scl_out~1_combout = (\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|state.Start~q $ (((!\ula_|i2c_loader_|scl_out~_Duplicate_1_q ))))) # (!\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|phase [1]) # @@ -54976,20 +54743,20 @@ defparam \ula_|i2c_loader_|scl_out~1 .lut_mask = 16'hBA74; defparam \ula_|i2c_loader_|scl_out~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N12 +// Location: LCCOMB_X1_Y23_N6 cycloneive_lcell_comb \ula_|i2c_loader_|scl_out~2 ( // Equation(s): // \ula_|i2c_loader_|scl_out~2_combout = (\ula_|i2c_loader_|scl_out~1_combout & ((\ula_|i2c_loader_|state.Start~q ))) # (!\ula_|i2c_loader_|scl_out~1_combout & (!\ula_|i2c_loader_|scl_out~0_combout & !\ula_|i2c_loader_|state.Start~q )) .dataa(\ula_|i2c_loader_|scl_out~0_combout ), .datab(\ula_|i2c_loader_|scl_out~1_combout ), - .datac(gnd), - .datad(\ula_|i2c_loader_|state.Start~q ), + .datac(\ula_|i2c_loader_|state.Start~q ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2c_loader_|scl_out~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|scl_out~2 .lut_mask = 16'hCC11; +defparam \ula_|i2c_loader_|scl_out~2 .lut_mask = 16'hC1C1; defparam \ula_|i2c_loader_|scl_out~2 .sum_lutc_input = "datac"; // synopsys translate_on @@ -55012,7 +54779,7 @@ defparam \ula_|i2c_loader_|scl_out .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|scl_out .power_up = "high"; // synopsys translate_on -// Location: FF_X1_Y23_N23 +// Location: FF_X1_Y23_N13 dffeas \ula_|i2c_loader_|sda_out~_Duplicate_1 ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|sda_out~4_combout ), @@ -55031,32 +54798,32 @@ defparam \ula_|i2c_loader_|sda_out~_Duplicate_1 .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|sda_out~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N10 +// Location: LCCOMB_X4_Y23_N10 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~4 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~4_combout = (!\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|state.Start~q ) +// \ula_|i2c_loader_|shiftreg~4_combout = (!\ula_|i2c_loader_|state.Start~q & !\ula_|i2c_loader_|state.Data~q ) - .dataa(gnd), + .dataa(\ula_|i2c_loader_|state.Start~q ), .datab(gnd), .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|state.Start~q ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg~4_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~4 .lut_mask = 16'h000F; +defparam \ula_|i2c_loader_|shiftreg~4 .lut_mask = 16'h0505; defparam \ula_|i2c_loader_|shiftreg~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N0 +// Location: LCCOMB_X4_Y23_N20 cycloneive_lcell_comb \ula_|i2c_loader_|Mux35~0 ( // Equation(s): -// \ula_|i2c_loader_|Mux35~0_combout = (\ula_|i2c_loader_|thisbyte [0] & (\ula_|i2c_loader_|thisbyte [2] & ((!\ula_|i2c_loader_|thisbyte [1]) # (!\ula_|i2c_loader_|thisbyte [3])))) +// \ula_|i2c_loader_|Mux35~0_combout = (\ula_|i2c_loader_|thisbyte [2] & (\ula_|i2c_loader_|thisbyte [0] & ((!\ula_|i2c_loader_|thisbyte [1]) # (!\ula_|i2c_loader_|thisbyte [3])))) - .dataa(\ula_|i2c_loader_|thisbyte [0]), + .dataa(\ula_|i2c_loader_|thisbyte [2]), .datab(\ula_|i2c_loader_|thisbyte [3]), .datac(\ula_|i2c_loader_|thisbyte [1]), - .datad(\ula_|i2c_loader_|thisbyte [2]), + .datad(\ula_|i2c_loader_|thisbyte [0]), .cin(gnd), .combout(\ula_|i2c_loader_|Mux35~0_combout ), .cout()); @@ -55065,135 +54832,186 @@ defparam \ula_|i2c_loader_|Mux35~0 .lut_mask = 16'h2A00; defparam \ula_|i2c_loader_|Mux35~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N30 +// Location: LCCOMB_X5_Y23_N12 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~13 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~13_combout = (!\ula_|i2c_loader_|thisbyte [2] & ((\ula_|i2c_loader_|thisbyte [4] & ((!\ula_|i2c_loader_|thisbyte [0]))) # (!\ula_|i2c_loader_|thisbyte [4] & (!\ula_|i2c_loader_|thisbyte [1] & \ula_|i2c_loader_|thisbyte [0])))) +// \ula_|i2c_loader_|shiftreg~13_combout = (!\ula_|i2c_loader_|thisbyte [2] & \ula_|i2c_loader_|thisbyte [4]) - .dataa(\ula_|i2c_loader_|thisbyte [4]), - .datab(\ula_|i2c_loader_|thisbyte [1]), - .datac(\ula_|i2c_loader_|thisbyte [0]), - .datad(\ula_|i2c_loader_|thisbyte [2]), + .dataa(\ula_|i2c_loader_|thisbyte [2]), + .datab(gnd), + .datac(\ula_|i2c_loader_|thisbyte [4]), + .datad(gnd), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg~13_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~13 .lut_mask = 16'h001A; +defparam \ula_|i2c_loader_|shiftreg~13 .lut_mask = 16'h5050; defparam \ula_|i2c_loader_|shiftreg~13 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N24 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~14 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~14_combout = (\ula_|i2c_loader_|thisbyte [4] & !\ula_|i2c_loader_|thisbyte [2]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2c_loader_|thisbyte [4]), - .datad(\ula_|i2c_loader_|thisbyte [2]), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~14_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~14 .lut_mask = 16'h00F0; -defparam \ula_|i2c_loader_|shiftreg~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N10 +// Location: LCCOMB_X5_Y23_N4 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~15 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~15_combout = (\ula_|i2c_loader_|shiftreg~13_combout ) # ((!\ula_|i2c_loader_|thisbyte [3] & (\ula_|i2c_loader_|thisbyte [0] & !\ula_|i2c_loader_|shiftreg~14_combout ))) +// \ula_|i2c_loader_|shiftreg~15_combout = (\ula_|i2c_loader_|thisbyte [2] & (((!\ula_|i2c_loader_|thisbyte [3])))) # (!\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte [1] & (\ula_|i2c_loader_|thisbyte [4]))) - .dataa(\ula_|i2c_loader_|shiftreg~13_combout ), - .datab(\ula_|i2c_loader_|thisbyte [3]), - .datac(\ula_|i2c_loader_|thisbyte [0]), - .datad(\ula_|i2c_loader_|shiftreg~14_combout ), + .dataa(\ula_|i2c_loader_|thisbyte [2]), + .datab(\ula_|i2c_loader_|thisbyte [1]), + .datac(\ula_|i2c_loader_|thisbyte [4]), + .datad(\ula_|i2c_loader_|thisbyte [3]), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg~15_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~15 .lut_mask = 16'hAABA; +defparam \ula_|i2c_loader_|shiftreg~15 .lut_mask = 16'h10BA; defparam \ula_|i2c_loader_|shiftreg~15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N12 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~24 ( +// Location: LCCOMB_X5_Y23_N10 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~16 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg[0]~24_combout = (!\ula_|i2c_loader_|thisbyte [3] & (!\ula_|i2c_loader_|state.Data~q & \ula_|i2c_loader_|thisbyte [0])) +// \ula_|i2c_loader_|shiftreg~16_combout = (\ula_|i2c_loader_|thisbyte [0] & (((\ula_|i2c_loader_|shiftreg~15_combout )))) # (!\ula_|i2c_loader_|thisbyte [0] & (!\ula_|i2c_loader_|shiftreg~13_combout & (\ula_|i2c_loader_|thisbyte [3]))) + + .dataa(\ula_|i2c_loader_|shiftreg~13_combout ), + .datab(\ula_|i2c_loader_|thisbyte [3]), + .datac(\ula_|i2c_loader_|shiftreg~15_combout ), + .datad(\ula_|i2c_loader_|thisbyte [0]), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~16_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~16 .lut_mask = 16'hF044; +defparam \ula_|i2c_loader_|shiftreg~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y23_N12 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~17 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~17_combout = (\ula_|i2c_loader_|thisbyte [0] & ((\ula_|i2c_loader_|thisbyte [4] & (!\ula_|i2c_loader_|thisbyte [1])) # (!\ula_|i2c_loader_|thisbyte [4] & ((!\ula_|i2c_loader_|thisbyte [3]))))) + + .dataa(\ula_|i2c_loader_|thisbyte [4]), + .datab(\ula_|i2c_loader_|thisbyte [0]), + .datac(\ula_|i2c_loader_|thisbyte [1]), + .datad(\ula_|i2c_loader_|thisbyte [3]), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~17_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~17 .lut_mask = 16'h084C; +defparam \ula_|i2c_loader_|shiftreg~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y23_N22 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~18 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~18_combout = ((\ula_|i2c_loader_|thisbyte [2] & ((!\ula_|i2c_loader_|thisbyte [0]))) # (!\ula_|i2c_loader_|thisbyte [2] & (\ula_|i2c_loader_|shiftreg~17_combout ))) # (!\ula_|i2c_loader_|shiftreg~4_combout ) + + .dataa(\ula_|i2c_loader_|shiftreg~17_combout ), + .datab(\ula_|i2c_loader_|thisbyte [2]), + .datac(\ula_|i2c_loader_|shiftreg~4_combout ), + .datad(\ula_|i2c_loader_|thisbyte [0]), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~18_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~18 .lut_mask = 16'h2FEF; +defparam \ula_|i2c_loader_|shiftreg~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y23_N14 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~20 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~20_combout = (\ula_|i2c_loader_|thisbyte [0] & ((\ula_|i2c_loader_|thisbyte [3] & (\ula_|i2c_loader_|thisbyte [2])) # (!\ula_|i2c_loader_|thisbyte [3] & (!\ula_|i2c_loader_|thisbyte [2] & !\ula_|i2c_loader_|thisbyte [4])))) + + .dataa(\ula_|i2c_loader_|thisbyte [0]), + .datab(\ula_|i2c_loader_|thisbyte [3]), + .datac(\ula_|i2c_loader_|thisbyte [2]), + .datad(\ula_|i2c_loader_|thisbyte [4]), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~20_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~20 .lut_mask = 16'h8082; +defparam \ula_|i2c_loader_|shiftreg~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y23_N24 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~21 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~21_combout = (\ula_|i2c_loader_|shiftreg~4_combout & ((\ula_|i2c_loader_|shiftreg~20_combout ) # ((\ula_|i2c_loader_|thisbyte [1] & !\ula_|i2c_loader_|thisbyte [0])))) + + .dataa(\ula_|i2c_loader_|shiftreg~4_combout ), + .datab(\ula_|i2c_loader_|shiftreg~20_combout ), + .datac(\ula_|i2c_loader_|thisbyte [1]), + .datad(\ula_|i2c_loader_|thisbyte [0]), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~21_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~21 .lut_mask = 16'h88A8; +defparam \ula_|i2c_loader_|shiftreg~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y23_N0 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~23 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg[0]~23_combout = (!\ula_|i2c_loader_|thisbyte [3] & (!\ula_|i2c_loader_|state.Data~q & \ula_|i2c_loader_|thisbyte [0])) .dataa(gnd), .datab(\ula_|i2c_loader_|thisbyte [3]), .datac(\ula_|i2c_loader_|state.Data~q ), .datad(\ula_|i2c_loader_|thisbyte [0]), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg[0]~24_combout ), + .combout(\ula_|i2c_loader_|shiftreg[0]~23_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[0]~24 .lut_mask = 16'h0300; -defparam \ula_|i2c_loader_|shiftreg[0]~24 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg[0]~23 .lut_mask = 16'h0300; +defparam \ula_|i2c_loader_|shiftreg[0]~23 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N14 +// Location: LCCOMB_X3_Y23_N30 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~6 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg[0]~6_combout = (!\ula_|i2c_loader_|phase [1] & (\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|state.Data~q )) +// \ula_|i2c_loader_|shiftreg[0]~6_combout = (\ula_|i2c_loader_|phase [1] & ((\ula_|i2c_loader_|state~24_combout ) # ((\ula_|i2c_loader_|state.Start~q )))) # (!\ula_|i2c_loader_|phase [1] & (((\ula_|i2c_loader_|state.Data~q )))) - .dataa(\ula_|i2c_loader_|phase [1]), - .datab(gnd), - .datac(\ula_|i2c_loader_|phase [0]), - .datad(\ula_|i2c_loader_|state.Data~q ), + .dataa(\ula_|i2c_loader_|state~24_combout ), + .datab(\ula_|i2c_loader_|state.Data~q ), + .datac(\ula_|i2c_loader_|state.Start~q ), + .datad(\ula_|i2c_loader_|phase [1]), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg[0]~6_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[0]~6 .lut_mask = 16'h5000; +defparam \ula_|i2c_loader_|shiftreg[0]~6 .lut_mask = 16'hFACC; defparam \ula_|i2c_loader_|shiftreg[0]~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N0 +// Location: LCCOMB_X3_Y23_N8 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~7 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg[0]~7_combout = (\ula_|i2c_loader_|shiftreg[0]~6_combout ) # ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Start~q ) # (\ula_|i2c_loader_|state~24_combout )))) +// \ula_|i2c_loader_|shiftreg[0]~7_combout = (\ula_|i2c_loader_|shiftreg[0]~6_combout & (\ula_|i2c_loader_|phase [0] & (!\ula_|i2c_loader_|WideAnd0~combout & \ula_|i2c_loader_|state.Idle~q ))) - .dataa(\ula_|i2c_loader_|state.Start~q ), - .datab(\ula_|i2c_loader_|Mux42~0_combout ), - .datac(\ula_|i2c_loader_|shiftreg[0]~6_combout ), - .datad(\ula_|i2c_loader_|state~24_combout ), + .dataa(\ula_|i2c_loader_|shiftreg[0]~6_combout ), + .datab(\ula_|i2c_loader_|phase [0]), + .datac(\ula_|i2c_loader_|WideAnd0~combout ), + .datad(\ula_|i2c_loader_|state.Idle~q ), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg[0]~7_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[0]~7 .lut_mask = 16'hFCF8; +defparam \ula_|i2c_loader_|shiftreg[0]~7 .lut_mask = 16'h0800; defparam \ula_|i2c_loader_|shiftreg[0]~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N10 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~8 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg[0]~8_combout = (\ula_|i2c_loader_|state.Idle~q & (!\ula_|i2c_loader_|WideAnd0~combout & \ula_|i2c_loader_|shiftreg[0]~7_combout )) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|state.Idle~q ), - .datac(\ula_|i2c_loader_|WideAnd0~combout ), - .datad(\ula_|i2c_loader_|shiftreg[0]~7_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg[0]~8_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[0]~8 .lut_mask = 16'h0C00; -defparam \ula_|i2c_loader_|shiftreg[0]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X3_Y23_N13 +// Location: FF_X4_Y23_N1 dffeas \ula_|i2c_loader_|shiftreg[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|shiftreg[0]~24_combout ), + .d(\ula_|i2c_loader_|shiftreg[0]~23_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(\ula_|i2c_loader_|state.Start~q ), .sload(gnd), - .ena(\ula_|i2c_loader_|shiftreg[0]~8_combout ), + .ena(\ula_|i2c_loader_|shiftreg[0]~7_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [0]), @@ -55203,102 +55021,68 @@ defparam \ula_|i2c_loader_|shiftreg[0] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N26 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~21 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~21_combout = (\ula_|i2c_loader_|thisbyte [0] & ((\ula_|i2c_loader_|thisbyte [3] & ((\ula_|i2c_loader_|thisbyte [2]))) # (!\ula_|i2c_loader_|thisbyte [3] & (!\ula_|i2c_loader_|thisbyte [4] & !\ula_|i2c_loader_|thisbyte [2])))) - - .dataa(\ula_|i2c_loader_|thisbyte [4]), - .datab(\ula_|i2c_loader_|thisbyte [3]), - .datac(\ula_|i2c_loader_|thisbyte [0]), - .datad(\ula_|i2c_loader_|thisbyte [2]), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~21_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~21 .lut_mask = 16'hC010; -defparam \ula_|i2c_loader_|shiftreg~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y23_N28 +// Location: LCCOMB_X4_Y23_N28 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~22 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~22_combout = (\ula_|i2c_loader_|shiftreg~4_combout & ((\ula_|i2c_loader_|shiftreg~21_combout ) # ((\ula_|i2c_loader_|thisbyte [1] & !\ula_|i2c_loader_|thisbyte [0])))) +// \ula_|i2c_loader_|shiftreg~22_combout = (\ula_|i2c_loader_|shiftreg~21_combout ) # ((\ula_|i2c_loader_|state.Data~q & \ula_|i2c_loader_|shiftreg [0])) - .dataa(\ula_|i2c_loader_|shiftreg~21_combout ), - .datab(\ula_|i2c_loader_|shiftreg~4_combout ), - .datac(\ula_|i2c_loader_|thisbyte [1]), - .datad(\ula_|i2c_loader_|thisbyte [0]), + .dataa(gnd), + .datab(\ula_|i2c_loader_|shiftreg~21_combout ), + .datac(\ula_|i2c_loader_|state.Data~q ), + .datad(\ula_|i2c_loader_|shiftreg [0]), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg~22_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~22 .lut_mask = 16'h88C8; +defparam \ula_|i2c_loader_|shiftreg~22 .lut_mask = 16'hFCCC; defparam \ula_|i2c_loader_|shiftreg~22 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N22 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~23 ( +// Location: LCCOMB_X3_Y23_N10 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[6]~9 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~23_combout = (\ula_|i2c_loader_|shiftreg~22_combout ) # ((\ula_|i2c_loader_|shiftreg [0] & \ula_|i2c_loader_|state.Data~q )) +// \ula_|i2c_loader_|shiftreg[6]~9_combout = (\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|state.Start~q $ (!\ula_|i2c_loader_|phase [1])))) # (!\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|phase [1] & ((\ula_|i2c_loader_|state~24_combout +// ) # (\ula_|i2c_loader_|state.Start~q )))) - .dataa(\ula_|i2c_loader_|shiftreg [0]), - .datab(gnd), - .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|shiftreg~22_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~23_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~23 .lut_mask = 16'hFFA0; -defparam \ula_|i2c_loader_|shiftreg~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N10 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[6]~10 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg[6]~10_combout = (\ula_|i2c_loader_|phase [1] & ((\ula_|i2c_loader_|state.Start~q ) # ((!\ula_|i2c_loader_|state.Data~q & \ula_|i2c_loader_|state~24_combout )))) # (!\ula_|i2c_loader_|phase [1] & (\ula_|i2c_loader_|state.Data~q -// & (!\ula_|i2c_loader_|state.Start~q ))) - - .dataa(\ula_|i2c_loader_|phase [1]), + .dataa(\ula_|i2c_loader_|state~24_combout ), .datab(\ula_|i2c_loader_|state.Data~q ), .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|state~24_combout ), + .datad(\ula_|i2c_loader_|phase [1]), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg[6]~9_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg[6]~9 .lut_mask = 16'hF20C; +defparam \ula_|i2c_loader_|shiftreg[6]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y23_N12 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[6]~10 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg[6]~10_combout = (\ula_|i2c_loader_|shiftreg[6]~9_combout & (\ula_|i2c_loader_|phase [0] & (!\ula_|i2c_loader_|WideAnd0~combout & \ula_|i2c_loader_|state.Idle~q ))) + + .dataa(\ula_|i2c_loader_|shiftreg[6]~9_combout ), + .datab(\ula_|i2c_loader_|phase [0]), + .datac(\ula_|i2c_loader_|WideAnd0~combout ), + .datad(\ula_|i2c_loader_|state.Idle~q ), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg[6]~10_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[6]~10 .lut_mask = 16'hA6A4; +defparam \ula_|i2c_loader_|shiftreg[6]~10 .lut_mask = 16'h0800; defparam \ula_|i2c_loader_|shiftreg[6]~10 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N24 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[6]~11 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg[6]~11_combout = (\ula_|i2c_loader_|phase [0] & (!\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|state.Idle~q & \ula_|i2c_loader_|shiftreg[6]~10_combout ))) - - .dataa(\ula_|i2c_loader_|phase [0]), - .datab(\ula_|i2c_loader_|WideAnd0~combout ), - .datac(\ula_|i2c_loader_|state.Idle~q ), - .datad(\ula_|i2c_loader_|shiftreg[6]~10_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg[6]~11_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[6]~11 .lut_mask = 16'h2000; -defparam \ula_|i2c_loader_|shiftreg[6]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X3_Y23_N23 +// Location: FF_X4_Y23_N29 dffeas \ula_|i2c_loader_|shiftreg[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|shiftreg~23_combout ), + .d(\ula_|i2c_loader_|shiftreg~22_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2c_loader_|shiftreg[6]~11_combout ), + .ena(\ula_|i2c_loader_|shiftreg[6]~10_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [1]), @@ -55308,67 +55092,33 @@ defparam \ula_|i2c_loader_|shiftreg[1] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N4 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~18 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~18_combout = (\ula_|i2c_loader_|thisbyte [0] & ((\ula_|i2c_loader_|thisbyte [4] & ((!\ula_|i2c_loader_|thisbyte [1]))) # (!\ula_|i2c_loader_|thisbyte [4] & (!\ula_|i2c_loader_|thisbyte [3])))) - - .dataa(\ula_|i2c_loader_|thisbyte [4]), - .datab(\ula_|i2c_loader_|thisbyte [3]), - .datac(\ula_|i2c_loader_|thisbyte [0]), - .datad(\ula_|i2c_loader_|thisbyte [1]), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~18_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~18 .lut_mask = 16'h10B0; -defparam \ula_|i2c_loader_|shiftreg~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y23_N24 +// Location: LCCOMB_X4_Y23_N2 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~19 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~19_combout = ((\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte [0])) # (!\ula_|i2c_loader_|thisbyte [2] & ((\ula_|i2c_loader_|shiftreg~18_combout )))) # (!\ula_|i2c_loader_|shiftreg~4_combout ) +// \ula_|i2c_loader_|shiftreg~19_combout = (\ula_|i2c_loader_|shiftreg~18_combout & ((\ula_|i2c_loader_|shiftreg [1]) # (!\ula_|i2c_loader_|state.Data~q ))) - .dataa(\ula_|i2c_loader_|thisbyte [0]), - .datab(\ula_|i2c_loader_|thisbyte [2]), - .datac(\ula_|i2c_loader_|shiftreg~18_combout ), - .datad(\ula_|i2c_loader_|shiftreg~4_combout ), + .dataa(\ula_|i2c_loader_|shiftreg~18_combout ), + .datab(\ula_|i2c_loader_|shiftreg [1]), + .datac(\ula_|i2c_loader_|state.Data~q ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg~19_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~19 .lut_mask = 16'h74FF; +defparam \ula_|i2c_loader_|shiftreg~19 .lut_mask = 16'h8A8A; defparam \ula_|i2c_loader_|shiftreg~19 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N2 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~20 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~20_combout = (\ula_|i2c_loader_|shiftreg~19_combout & ((\ula_|i2c_loader_|shiftreg [1]) # (!\ula_|i2c_loader_|state.Data~q ))) - - .dataa(\ula_|i2c_loader_|shiftreg [1]), - .datab(gnd), - .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|shiftreg~19_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~20_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~20 .lut_mask = 16'hAF00; -defparam \ula_|i2c_loader_|shiftreg~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X3_Y23_N3 +// Location: FF_X4_Y23_N3 dffeas \ula_|i2c_loader_|shiftreg[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|shiftreg~20_combout ), + .d(\ula_|i2c_loader_|shiftreg~19_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2c_loader_|shiftreg[6]~11_combout ), + .ena(\ula_|i2c_loader_|shiftreg[6]~10_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [2]), @@ -55378,67 +55128,33 @@ defparam \ula_|i2c_loader_|shiftreg[2] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N28 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~16 ( +// Location: LCCOMB_X4_Y23_N8 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~25 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~16_combout = (\ula_|i2c_loader_|thisbyte [2] & (((!\ula_|i2c_loader_|thisbyte [3])))) # (!\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte [1] & (\ula_|i2c_loader_|thisbyte [4]))) - - .dataa(\ula_|i2c_loader_|thisbyte [2]), - .datab(\ula_|i2c_loader_|thisbyte [1]), - .datac(\ula_|i2c_loader_|thisbyte [4]), - .datad(\ula_|i2c_loader_|thisbyte [3]), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~16_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~16 .lut_mask = 16'h10BA; -defparam \ula_|i2c_loader_|shiftreg~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y23_N20 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~17 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~17_combout = (\ula_|i2c_loader_|thisbyte [0] & (((\ula_|i2c_loader_|shiftreg~16_combout )))) # (!\ula_|i2c_loader_|thisbyte [0] & (\ula_|i2c_loader_|thisbyte [3] & ((!\ula_|i2c_loader_|shiftreg~14_combout )))) - - .dataa(\ula_|i2c_loader_|thisbyte [0]), - .datab(\ula_|i2c_loader_|thisbyte [3]), - .datac(\ula_|i2c_loader_|shiftreg~16_combout ), - .datad(\ula_|i2c_loader_|shiftreg~14_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~17_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~17 .lut_mask = 16'hA0E4; -defparam \ula_|i2c_loader_|shiftreg~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y23_N6 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~26 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~26_combout = (\ula_|i2c_loader_|state.Data~q & (((\ula_|i2c_loader_|shiftreg [2])))) # (!\ula_|i2c_loader_|state.Data~q & (!\ula_|i2c_loader_|state.Start~q & ((\ula_|i2c_loader_|shiftreg~17_combout )))) +// \ula_|i2c_loader_|shiftreg~25_combout = (\ula_|i2c_loader_|state.Data~q & (((\ula_|i2c_loader_|shiftreg [2])))) # (!\ula_|i2c_loader_|state.Data~q & (!\ula_|i2c_loader_|state.Start~q & (\ula_|i2c_loader_|shiftreg~16_combout ))) .dataa(\ula_|i2c_loader_|state.Start~q ), - .datab(\ula_|i2c_loader_|shiftreg [2]), - .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|shiftreg~17_combout ), + .datab(\ula_|i2c_loader_|state.Data~q ), + .datac(\ula_|i2c_loader_|shiftreg~16_combout ), + .datad(\ula_|i2c_loader_|shiftreg [2]), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~26_combout ), + .combout(\ula_|i2c_loader_|shiftreg~25_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~26 .lut_mask = 16'hC5C0; -defparam \ula_|i2c_loader_|shiftreg~26 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg~25 .lut_mask = 16'hDC10; +defparam \ula_|i2c_loader_|shiftreg~25 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y23_N7 +// Location: FF_X4_Y23_N9 dffeas \ula_|i2c_loader_|shiftreg[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|shiftreg~26_combout ), + .d(\ula_|i2c_loader_|shiftreg~25_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2c_loader_|shiftreg[6]~11_combout ), + .ena(\ula_|i2c_loader_|shiftreg[6]~10_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [3]), @@ -55448,33 +55164,67 @@ defparam \ula_|i2c_loader_|shiftreg[3] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N0 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~25 ( +// Location: LCCOMB_X5_Y23_N14 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~12 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~25_combout = (\ula_|i2c_loader_|state.Data~q & (((\ula_|i2c_loader_|shiftreg [3])))) # (!\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|shiftreg~15_combout ) # ((\ula_|i2c_loader_|state.Start~q )))) +// \ula_|i2c_loader_|shiftreg~12_combout = (!\ula_|i2c_loader_|thisbyte [2] & ((\ula_|i2c_loader_|thisbyte [4] & ((!\ula_|i2c_loader_|thisbyte [0]))) # (!\ula_|i2c_loader_|thisbyte [4] & (!\ula_|i2c_loader_|thisbyte [1] & \ula_|i2c_loader_|thisbyte [0])))) - .dataa(\ula_|i2c_loader_|shiftreg~15_combout ), - .datab(\ula_|i2c_loader_|state.Data~q ), - .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|shiftreg [3]), + .dataa(\ula_|i2c_loader_|thisbyte [2]), + .datab(\ula_|i2c_loader_|thisbyte [1]), + .datac(\ula_|i2c_loader_|thisbyte [4]), + .datad(\ula_|i2c_loader_|thisbyte [0]), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~25_combout ), + .combout(\ula_|i2c_loader_|shiftreg~12_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~25 .lut_mask = 16'hFE32; -defparam \ula_|i2c_loader_|shiftreg~25 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg~12 .lut_mask = 16'h0150; +defparam \ula_|i2c_loader_|shiftreg~12 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X2_Y23_N1 +// Location: LCCOMB_X5_Y23_N6 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~14 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~14_combout = (\ula_|i2c_loader_|shiftreg~12_combout ) # ((!\ula_|i2c_loader_|shiftreg~13_combout & (!\ula_|i2c_loader_|thisbyte [3] & \ula_|i2c_loader_|thisbyte [0]))) + + .dataa(\ula_|i2c_loader_|shiftreg~13_combout ), + .datab(\ula_|i2c_loader_|thisbyte [3]), + .datac(\ula_|i2c_loader_|shiftreg~12_combout ), + .datad(\ula_|i2c_loader_|thisbyte [0]), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~14_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~14 .lut_mask = 16'hF1F0; +defparam \ula_|i2c_loader_|shiftreg~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y23_N6 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~24 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~24_combout = (\ula_|i2c_loader_|state.Data~q & (((\ula_|i2c_loader_|shiftreg [3])))) # (!\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|state.Start~q ) # ((\ula_|i2c_loader_|shiftreg~14_combout )))) + + .dataa(\ula_|i2c_loader_|state.Start~q ), + .datab(\ula_|i2c_loader_|shiftreg [3]), + .datac(\ula_|i2c_loader_|state.Data~q ), + .datad(\ula_|i2c_loader_|shiftreg~14_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~24_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~24 .lut_mask = 16'hCFCA; +defparam \ula_|i2c_loader_|shiftreg~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X4_Y23_N7 dffeas \ula_|i2c_loader_|shiftreg[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|shiftreg~25_combout ), + .d(\ula_|i2c_loader_|shiftreg~24_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2c_loader_|shiftreg[6]~11_combout ), + .ena(\ula_|i2c_loader_|shiftreg[6]~10_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [4]), @@ -55484,33 +55234,33 @@ defparam \ula_|i2c_loader_|shiftreg[4] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N4 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~12 ( +// Location: LCCOMB_X3_Y23_N24 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~11 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~12_combout = (\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|shiftreg [4]))) # (!\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|Mux35~0_combout )) +// \ula_|i2c_loader_|shiftreg~11_combout = (\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|shiftreg [4]))) # (!\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|Mux35~0_combout )) .dataa(\ula_|i2c_loader_|Mux35~0_combout ), .datab(\ula_|i2c_loader_|state.Data~q ), .datac(gnd), .datad(\ula_|i2c_loader_|shiftreg [4]), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~12_combout ), + .combout(\ula_|i2c_loader_|shiftreg~11_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~12 .lut_mask = 16'hEE22; -defparam \ula_|i2c_loader_|shiftreg~12 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg~11 .lut_mask = 16'hEE22; +defparam \ula_|i2c_loader_|shiftreg~11 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X2_Y24_N5 +// Location: FF_X3_Y23_N25 dffeas \ula_|i2c_loader_|shiftreg[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|shiftreg~12_combout ), + .d(\ula_|i2c_loader_|shiftreg~11_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(\ula_|i2c_loader_|state.Start~q ), - .ena(\ula_|i2c_loader_|shiftreg[6]~11_combout ), + .ena(\ula_|i2c_loader_|shiftreg[6]~10_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [5]), @@ -55520,33 +55270,33 @@ defparam \ula_|i2c_loader_|shiftreg[5] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N18 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~9 ( +// Location: LCCOMB_X4_Y23_N18 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~8 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~9_combout = (\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|shiftreg [5])) # (!\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|Mux35~0_combout ))) +// \ula_|i2c_loader_|shiftreg~8_combout = (\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|shiftreg [5])) # (!\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|Mux35~0_combout ))) .dataa(gnd), .datab(\ula_|i2c_loader_|shiftreg [5]), .datac(\ula_|i2c_loader_|state.Data~q ), .datad(\ula_|i2c_loader_|Mux35~0_combout ), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~9_combout ), + .combout(\ula_|i2c_loader_|shiftreg~8_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~9 .lut_mask = 16'hCFC0; -defparam \ula_|i2c_loader_|shiftreg~9 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg~8 .lut_mask = 16'hCFC0; +defparam \ula_|i2c_loader_|shiftreg~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y23_N19 +// Location: FF_X4_Y23_N19 dffeas \ula_|i2c_loader_|shiftreg[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|shiftreg~9_combout ), + .d(\ula_|i2c_loader_|shiftreg~8_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(\ula_|i2c_loader_|state.Start~q ), .sload(gnd), - .ena(\ula_|i2c_loader_|shiftreg[6]~11_combout ), + .ena(\ula_|i2c_loader_|shiftreg[6]~10_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [6]), @@ -55556,7 +55306,7 @@ defparam \ula_|i2c_loader_|shiftreg[6] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N4 +// Location: LCCOMB_X4_Y23_N16 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[7]~5 ( // Equation(s): // \ula_|i2c_loader_|shiftreg[7]~5_combout = (\ula_|i2c_loader_|state.Data~q & \ula_|i2c_loader_|shiftreg [6]) @@ -55573,7 +55323,7 @@ defparam \ula_|i2c_loader_|shiftreg[7]~5 .lut_mask = 16'hF000; defparam \ula_|i2c_loader_|shiftreg[7]~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y23_N5 +// Location: FF_X4_Y23_N17 dffeas \ula_|i2c_loader_|shiftreg[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|shiftreg[7]~5_combout ), @@ -55582,7 +55332,7 @@ dffeas \ula_|i2c_loader_|shiftreg[7] ( .aload(gnd), .sclr(\ula_|i2c_loader_|state.Start~q ), .sload(gnd), - .ena(\ula_|i2c_loader_|shiftreg[0]~8_combout ), + .ena(\ula_|i2c_loader_|shiftreg[0]~7_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [7]), @@ -55592,25 +55342,25 @@ defparam \ula_|i2c_loader_|shiftreg[7] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N12 +// Location: LCCOMB_X1_Y23_N26 cycloneive_lcell_comb \ula_|i2c_loader_|sda_out~0 ( // Equation(s): -// \ula_|i2c_loader_|sda_out~0_combout = (\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|shiftreg [7]))) # (!\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|state.Ack~q )))) # (!\ula_|i2c_loader_|state.Data~q & +// \ula_|i2c_loader_|sda_out~0_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|shiftreg [7])) # (!\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|state.Ack~q ))))) # (!\ula_|i2c_loader_|phase [0] & // (((\ula_|i2c_loader_|state.Ack~q )))) - .dataa(\ula_|i2c_loader_|state.Data~q ), - .datab(\ula_|i2c_loader_|phase [0]), - .datac(\ula_|i2c_loader_|state.Ack~q ), - .datad(\ula_|i2c_loader_|shiftreg [7]), + .dataa(\ula_|i2c_loader_|shiftreg [7]), + .datab(\ula_|i2c_loader_|state.Ack~q ), + .datac(\ula_|i2c_loader_|phase [0]), + .datad(\ula_|i2c_loader_|state.Data~q ), .cin(gnd), .combout(\ula_|i2c_loader_|sda_out~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|sda_out~0 .lut_mask = 16'hF870; +defparam \ula_|i2c_loader_|sda_out~0 .lut_mask = 16'hACCC; defparam \ula_|i2c_loader_|sda_out~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N6 +// Location: LCCOMB_X1_Y23_N20 cycloneive_lcell_comb \ula_|i2c_loader_|sda_out~1 ( // Equation(s): // \ula_|i2c_loader_|sda_out~1_combout = (\ula_|i2c_loader_|sda_out~0_combout & ((\ula_|i2c_loader_|phase [0]) # ((\ula_|i2c_loader_|shiftreg~4_combout & !\I2C_SDAT~input_o )))) @@ -55627,55 +55377,55 @@ defparam \ula_|i2c_loader_|sda_out~1 .lut_mask = 16'hC0E0; defparam \ula_|i2c_loader_|sda_out~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N8 +// Location: LCCOMB_X1_Y23_N14 cycloneive_lcell_comb \ula_|i2c_loader_|sda_out~2 ( // Equation(s): // \ula_|i2c_loader_|sda_out~2_combout = (!\ula_|i2c_loader_|sda_out~_Duplicate_1_q & ((\ula_|i2c_loader_|phase [0]) # ((\ula_|i2c_loader_|phase [1] & !\ula_|i2c_loader_|sda_out~1_combout )))) .dataa(\ula_|i2c_loader_|sda_out~_Duplicate_1_q ), - .datab(\ula_|i2c_loader_|phase [0]), - .datac(\ula_|i2c_loader_|phase [1]), + .datab(\ula_|i2c_loader_|phase [1]), + .datac(\ula_|i2c_loader_|phase [0]), .datad(\ula_|i2c_loader_|sda_out~1_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|sda_out~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|sda_out~2 .lut_mask = 16'h4454; +defparam \ula_|i2c_loader_|sda_out~2 .lut_mask = 16'h5054; defparam \ula_|i2c_loader_|sda_out~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N2 +// Location: LCCOMB_X1_Y23_N28 cycloneive_lcell_comb \ula_|i2c_loader_|sda_out~3 ( // Equation(s): -// \ula_|i2c_loader_|sda_out~3_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|phase [1] & (\ula_|i2c_loader_|sda_out~_Duplicate_1_q )) # (!\ula_|i2c_loader_|phase [1] & ((!\ula_|i2c_loader_|sda_out~1_combout ))))) # (!\ula_|i2c_loader_|phase -// [0] & ((\ula_|i2c_loader_|sda_out~_Duplicate_1_q ) # ((\ula_|i2c_loader_|phase [1] & \ula_|i2c_loader_|sda_out~1_combout )))) +// \ula_|i2c_loader_|sda_out~3_combout = (\ula_|i2c_loader_|phase [1] & ((\ula_|i2c_loader_|sda_out~_Duplicate_1_q ) # ((!\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|sda_out~1_combout )))) # (!\ula_|i2c_loader_|phase [1] & ((\ula_|i2c_loader_|phase [0] +// & ((!\ula_|i2c_loader_|sda_out~1_combout ))) # (!\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|sda_out~_Duplicate_1_q )))) .dataa(\ula_|i2c_loader_|sda_out~_Duplicate_1_q ), - .datab(\ula_|i2c_loader_|phase [0]), - .datac(\ula_|i2c_loader_|phase [1]), + .datab(\ula_|i2c_loader_|phase [1]), + .datac(\ula_|i2c_loader_|phase [0]), .datad(\ula_|i2c_loader_|sda_out~1_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|sda_out~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|sda_out~3 .lut_mask = 16'hB2AE; +defparam \ula_|i2c_loader_|sda_out~3 .lut_mask = 16'h8EBA; defparam \ula_|i2c_loader_|sda_out~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N22 +// Location: LCCOMB_X1_Y23_N12 cycloneive_lcell_comb \ula_|i2c_loader_|sda_out~4 ( // Equation(s): // \ula_|i2c_loader_|sda_out~4_combout = (\ula_|i2c_loader_|state.Start~q & (((!\ula_|i2c_loader_|sda_out~2_combout )))) # (!\ula_|i2c_loader_|state.Start~q & (!\ula_|i2c_loader_|scl_out~0_combout & ((\ula_|i2c_loader_|sda_out~3_combout )))) - .dataa(\ula_|i2c_loader_|state.Start~q ), - .datab(\ula_|i2c_loader_|scl_out~0_combout ), + .dataa(\ula_|i2c_loader_|scl_out~0_combout ), + .datab(\ula_|i2c_loader_|state.Start~q ), .datac(\ula_|i2c_loader_|sda_out~2_combout ), .datad(\ula_|i2c_loader_|sda_out~3_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|sda_out~4_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|sda_out~4 .lut_mask = 16'h1B0A; +defparam \ula_|i2c_loader_|sda_out~4 .lut_mask = 16'h1D0C; defparam \ula_|i2c_loader_|sda_out~4 .sum_lutc_input = "datac"; // synopsys translate_on @@ -55698,7 +55448,7 @@ defparam \ula_|i2c_loader_|sda_out .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|sda_out .power_up = "high"; // synopsys translate_on -// Location: LCCOMB_X27_Y23_N16 +// Location: LCCOMB_X25_Y32_N20 cycloneive_lcell_comb \ula_|i2s_intf_|mclk_r~0 ( // Equation(s): // \ula_|i2s_intf_|mclk_r~0_combout = !\ula_|i2s_intf_|mclk_r~_Duplicate_1_q @@ -55715,7 +55465,7 @@ defparam \ula_|i2s_intf_|mclk_r~0 .lut_mask = 16'h0F0F; defparam \ula_|i2s_intf_|mclk_r~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X27_Y23_N17 +// Location: FF_X25_Y32_N21 dffeas \ula_|i2s_intf_|mclk_r~_Duplicate_1 ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|mclk_r~0_combout ), @@ -55753,7 +55503,7 @@ defparam \ula_|i2s_intf_|mclk_r .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|mclk_r .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N6 +// Location: LCCOMB_X24_Y32_N8 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~1 ( // Equation(s): // \ula_|i2s_intf_|Add0~1_cout = CARRY(!\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ) @@ -55770,25 +55520,25 @@ defparam \ula_|i2s_intf_|Add0~1 .lut_mask = 16'h0055; defparam \ula_|i2s_intf_|Add0~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N8 +// Location: LCCOMB_X24_Y32_N10 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~2 ( // Equation(s): // \ula_|i2s_intf_|Add0~2_combout = (\ula_|i2s_intf_|lrdivider [1] & (\ula_|i2s_intf_|Add0~1_cout & VCC)) # (!\ula_|i2s_intf_|lrdivider [1] & (!\ula_|i2s_intf_|Add0~1_cout )) // \ula_|i2s_intf_|Add0~3 = CARRY((!\ula_|i2s_intf_|lrdivider [1] & !\ula_|i2s_intf_|Add0~1_cout )) - .dataa(gnd), - .datab(\ula_|i2s_intf_|lrdivider [1]), + .dataa(\ula_|i2s_intf_|lrdivider [1]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\ula_|i2s_intf_|Add0~1_cout ), .combout(\ula_|i2s_intf_|Add0~2_combout ), .cout(\ula_|i2s_intf_|Add0~3 )); // synopsys translate_off -defparam \ula_|i2s_intf_|Add0~2 .lut_mask = 16'hC303; +defparam \ula_|i2s_intf_|Add0~2 .lut_mask = 16'hA505; defparam \ula_|i2s_intf_|Add0~2 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N28 +// Location: LCCOMB_X23_Y32_N10 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider~2 ( // Equation(s): // \ula_|i2s_intf_|lrdivider~2_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|Add0~2_combout ) @@ -55805,7 +55555,7 @@ defparam \ula_|i2s_intf_|lrdivider~2 .lut_mask = 16'h5050; defparam \ula_|i2s_intf_|lrdivider~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X29_Y23_N29 +// Location: FF_X23_Y32_N11 dffeas \ula_|i2s_intf_|lrdivider[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider~2_combout ), @@ -55824,42 +55574,42 @@ defparam \ula_|i2s_intf_|lrdivider[1] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N10 +// Location: LCCOMB_X24_Y32_N12 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~4 ( // Equation(s): // \ula_|i2s_intf_|Add0~4_combout = (\ula_|i2s_intf_|lrdivider [2] & (\ula_|i2s_intf_|Add0~3 $ (GND))) # (!\ula_|i2s_intf_|lrdivider [2] & ((GND) # (!\ula_|i2s_intf_|Add0~3 ))) // \ula_|i2s_intf_|Add0~5 = CARRY((!\ula_|i2s_intf_|Add0~3 ) # (!\ula_|i2s_intf_|lrdivider [2])) - .dataa(\ula_|i2s_intf_|lrdivider [2]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|i2s_intf_|lrdivider [2]), .datac(gnd), .datad(vcc), .cin(\ula_|i2s_intf_|Add0~3 ), .combout(\ula_|i2s_intf_|Add0~4_combout ), .cout(\ula_|i2s_intf_|Add0~5 )); // synopsys translate_off -defparam \ula_|i2s_intf_|Add0~4 .lut_mask = 16'hA55F; +defparam \ula_|i2s_intf_|Add0~4 .lut_mask = 16'hC33F; defparam \ula_|i2s_intf_|Add0~4 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X30_Y23_N6 +// Location: LCCOMB_X23_Y32_N22 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[2]~8 ( // Equation(s): // \ula_|i2s_intf_|lrdivider[2]~8_combout = !\ula_|i2s_intf_|Add0~4_combout .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|Add0~4_combout ), + .datac(\ula_|i2s_intf_|Add0~4_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|lrdivider[2]~8_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[2]~8 .lut_mask = 16'h00FF; +defparam \ula_|i2s_intf_|lrdivider[2]~8 .lut_mask = 16'h0F0F; defparam \ula_|i2s_intf_|lrdivider[2]~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y23_N7 +// Location: FF_X23_Y32_N23 dffeas \ula_|i2s_intf_|lrdivider[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider[2]~8_combout ), @@ -55878,7 +55628,7 @@ defparam \ula_|i2s_intf_|lrdivider[2] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N12 +// Location: LCCOMB_X24_Y32_N14 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~6 ( // Equation(s): // \ula_|i2s_intf_|Add0~6_combout = (\ula_|i2s_intf_|lrdivider [3] & (!\ula_|i2s_intf_|Add0~5 )) # (!\ula_|i2s_intf_|lrdivider [3] & (\ula_|i2s_intf_|Add0~5 & VCC)) @@ -55896,24 +55646,24 @@ defparam \ula_|i2s_intf_|Add0~6 .lut_mask = 16'h3C0C; defparam \ula_|i2s_intf_|Add0~6 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X28_Y23_N6 +// Location: LCCOMB_X23_Y32_N4 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[3]~7 ( // Equation(s): // \ula_|i2s_intf_|lrdivider[3]~7_combout = !\ula_|i2s_intf_|Add0~6_combout .dataa(gnd), .datab(gnd), - .datac(\ula_|i2s_intf_|Add0~6_combout ), - .datad(gnd), + .datac(gnd), + .datad(\ula_|i2s_intf_|Add0~6_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|lrdivider[3]~7_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[3]~7 .lut_mask = 16'h0F0F; +defparam \ula_|i2s_intf_|lrdivider[3]~7 .lut_mask = 16'h00FF; defparam \ula_|i2s_intf_|lrdivider[3]~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y23_N7 +// Location: FF_X23_Y32_N5 dffeas \ula_|i2s_intf_|lrdivider[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider[3]~7_combout ), @@ -55932,42 +55682,42 @@ defparam \ula_|i2s_intf_|lrdivider[3] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N14 +// Location: LCCOMB_X24_Y32_N16 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~8 ( // Equation(s): // \ula_|i2s_intf_|Add0~8_combout = (\ula_|i2s_intf_|lrdivider [4] & ((GND) # (!\ula_|i2s_intf_|Add0~7 ))) # (!\ula_|i2s_intf_|lrdivider [4] & (\ula_|i2s_intf_|Add0~7 $ (GND))) // \ula_|i2s_intf_|Add0~9 = CARRY((\ula_|i2s_intf_|lrdivider [4]) # (!\ula_|i2s_intf_|Add0~7 )) - .dataa(gnd), - .datab(\ula_|i2s_intf_|lrdivider [4]), + .dataa(\ula_|i2s_intf_|lrdivider [4]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\ula_|i2s_intf_|Add0~7 ), .combout(\ula_|i2s_intf_|Add0~8_combout ), .cout(\ula_|i2s_intf_|Add0~9 )); // synopsys translate_off -defparam \ula_|i2s_intf_|Add0~8 .lut_mask = 16'h3CCF; +defparam \ula_|i2s_intf_|Add0~8 .lut_mask = 16'h5AAF; defparam \ula_|i2s_intf_|Add0~8 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N4 +// Location: LCCOMB_X23_Y32_N16 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider~1 ( // Equation(s): // \ula_|i2s_intf_|lrdivider~1_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|Add0~8_combout ) - .dataa(\ula_|i2s_intf_|Equal0~2_combout ), + .dataa(gnd), .datab(gnd), - .datac(\ula_|i2s_intf_|Add0~8_combout ), - .datad(gnd), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|Add0~8_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|lrdivider~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider~1 .lut_mask = 16'h5050; +defparam \ula_|i2s_intf_|lrdivider~1 .lut_mask = 16'h0F00; defparam \ula_|i2s_intf_|lrdivider~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X29_Y23_N5 +// Location: FF_X23_Y32_N17 dffeas \ula_|i2s_intf_|lrdivider[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider~1_combout ), @@ -55986,25 +55736,25 @@ defparam \ula_|i2s_intf_|lrdivider[4] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N16 +// Location: LCCOMB_X24_Y32_N18 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~10 ( // Equation(s): // \ula_|i2s_intf_|Add0~10_combout = (\ula_|i2s_intf_|lrdivider [5] & (!\ula_|i2s_intf_|Add0~9 )) # (!\ula_|i2s_intf_|lrdivider [5] & (\ula_|i2s_intf_|Add0~9 & VCC)) // \ula_|i2s_intf_|Add0~11 = CARRY((\ula_|i2s_intf_|lrdivider [5] & !\ula_|i2s_intf_|Add0~9 )) - .dataa(gnd), - .datab(\ula_|i2s_intf_|lrdivider [5]), + .dataa(\ula_|i2s_intf_|lrdivider [5]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\ula_|i2s_intf_|Add0~9 ), .combout(\ula_|i2s_intf_|Add0~10_combout ), .cout(\ula_|i2s_intf_|Add0~11 )); // synopsys translate_off -defparam \ula_|i2s_intf_|Add0~10 .lut_mask = 16'h3C0C; +defparam \ula_|i2s_intf_|Add0~10 .lut_mask = 16'h5A0A; defparam \ula_|i2s_intf_|Add0~10 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N2 +// Location: LCCOMB_X23_Y32_N14 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[5]~6 ( // Equation(s): // \ula_|i2s_intf_|lrdivider[5]~6_combout = !\ula_|i2s_intf_|Add0~10_combout @@ -56021,7 +55771,7 @@ defparam \ula_|i2s_intf_|lrdivider[5]~6 .lut_mask = 16'h00FF; defparam \ula_|i2s_intf_|lrdivider[5]~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X29_Y23_N3 +// Location: FF_X23_Y32_N15 dffeas \ula_|i2s_intf_|lrdivider[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider[5]~6_combout ), @@ -56040,24 +55790,24 @@ defparam \ula_|i2s_intf_|lrdivider[5] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N26 +// Location: LCCOMB_X24_Y32_N0 cycloneive_lcell_comb \ula_|i2s_intf_|Equal0~1 ( // Equation(s): -// \ula_|i2s_intf_|Equal0~1_combout = (\ula_|i2s_intf_|lrdivider [2] & (!\ula_|i2s_intf_|lrdivider [4] & (\ula_|i2s_intf_|lrdivider [3] & \ula_|i2s_intf_|lrdivider [5]))) +// \ula_|i2s_intf_|Equal0~1_combout = (!\ula_|i2s_intf_|lrdivider [4] & (\ula_|i2s_intf_|lrdivider [2] & (\ula_|i2s_intf_|lrdivider [3] & \ula_|i2s_intf_|lrdivider [5]))) - .dataa(\ula_|i2s_intf_|lrdivider [2]), - .datab(\ula_|i2s_intf_|lrdivider [4]), + .dataa(\ula_|i2s_intf_|lrdivider [4]), + .datab(\ula_|i2s_intf_|lrdivider [2]), .datac(\ula_|i2s_intf_|lrdivider [3]), .datad(\ula_|i2s_intf_|lrdivider [5]), .cin(gnd), .combout(\ula_|i2s_intf_|Equal0~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|Equal0~1 .lut_mask = 16'h2000; +defparam \ula_|i2s_intf_|Equal0~1 .lut_mask = 16'h4000; defparam \ula_|i2s_intf_|Equal0~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N18 +// Location: LCCOMB_X24_Y32_N20 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~12 ( // Equation(s): // \ula_|i2s_intf_|Add0~12_combout = (\ula_|i2s_intf_|lrdivider [6] & (\ula_|i2s_intf_|Add0~11 $ (GND))) # (!\ula_|i2s_intf_|lrdivider [6] & ((GND) # (!\ula_|i2s_intf_|Add0~11 ))) @@ -56075,24 +55825,24 @@ defparam \ula_|i2s_intf_|Add0~12 .lut_mask = 16'hA55F; defparam \ula_|i2s_intf_|Add0~12 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X28_Y23_N26 +// Location: LCCOMB_X23_Y32_N0 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[6]~5 ( // Equation(s): // \ula_|i2s_intf_|lrdivider[6]~5_combout = !\ula_|i2s_intf_|Add0~12_combout .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|Add0~12_combout ), + .datac(\ula_|i2s_intf_|Add0~12_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|lrdivider[6]~5_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[6]~5 .lut_mask = 16'h00FF; +defparam \ula_|i2s_intf_|lrdivider[6]~5 .lut_mask = 16'h0F0F; defparam \ula_|i2s_intf_|lrdivider[6]~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y23_N27 +// Location: FF_X23_Y32_N1 dffeas \ula_|i2s_intf_|lrdivider[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider[6]~5_combout ), @@ -56111,42 +55861,42 @@ defparam \ula_|i2s_intf_|lrdivider[6] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N20 +// Location: LCCOMB_X24_Y32_N22 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~14 ( // Equation(s): // \ula_|i2s_intf_|Add0~14_combout = (\ula_|i2s_intf_|lrdivider [7] & (!\ula_|i2s_intf_|Add0~13 )) # (!\ula_|i2s_intf_|lrdivider [7] & (\ula_|i2s_intf_|Add0~13 & VCC)) // \ula_|i2s_intf_|Add0~15 = CARRY((\ula_|i2s_intf_|lrdivider [7] & !\ula_|i2s_intf_|Add0~13 )) - .dataa(\ula_|i2s_intf_|lrdivider [7]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|i2s_intf_|lrdivider [7]), .datac(gnd), .datad(vcc), .cin(\ula_|i2s_intf_|Add0~13 ), .combout(\ula_|i2s_intf_|Add0~14_combout ), .cout(\ula_|i2s_intf_|Add0~15 )); // synopsys translate_off -defparam \ula_|i2s_intf_|Add0~14 .lut_mask = 16'h5A0A; +defparam \ula_|i2s_intf_|Add0~14 .lut_mask = 16'h3C0C; defparam \ula_|i2s_intf_|Add0~14 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X30_Y23_N4 +// Location: LCCOMB_X24_Y32_N2 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[7]~4 ( // Equation(s): // \ula_|i2s_intf_|lrdivider[7]~4_combout = !\ula_|i2s_intf_|Add0~14_combout .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|Add0~14_combout ), + .datac(\ula_|i2s_intf_|Add0~14_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|lrdivider[7]~4_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[7]~4 .lut_mask = 16'h00FF; +defparam \ula_|i2s_intf_|lrdivider[7]~4 .lut_mask = 16'h0F0F; defparam \ula_|i2s_intf_|lrdivider[7]~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y23_N5 +// Location: FF_X24_Y32_N3 dffeas \ula_|i2s_intf_|lrdivider[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider[7]~4_combout ), @@ -56165,25 +55915,25 @@ defparam \ula_|i2s_intf_|lrdivider[7] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N22 +// Location: LCCOMB_X24_Y32_N24 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~16 ( // Equation(s): // \ula_|i2s_intf_|Add0~16_combout = (\ula_|i2s_intf_|lrdivider [8] & ((GND) # (!\ula_|i2s_intf_|Add0~15 ))) # (!\ula_|i2s_intf_|lrdivider [8] & (\ula_|i2s_intf_|Add0~15 $ (GND))) // \ula_|i2s_intf_|Add0~17 = CARRY((\ula_|i2s_intf_|lrdivider [8]) # (!\ula_|i2s_intf_|Add0~15 )) - .dataa(\ula_|i2s_intf_|lrdivider [8]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|i2s_intf_|lrdivider [8]), .datac(gnd), .datad(vcc), .cin(\ula_|i2s_intf_|Add0~15 ), .combout(\ula_|i2s_intf_|Add0~16_combout ), .cout(\ula_|i2s_intf_|Add0~17 )); // synopsys translate_off -defparam \ula_|i2s_intf_|Add0~16 .lut_mask = 16'h5AAF; +defparam \ula_|i2s_intf_|Add0~16 .lut_mask = 16'h3CCF; defparam \ula_|i2s_intf_|Add0~16 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X28_Y23_N16 +// Location: LCCOMB_X24_Y32_N28 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider~0 ( // Equation(s): // \ula_|i2s_intf_|lrdivider~0_combout = (\ula_|i2s_intf_|Add0~16_combout & !\ula_|i2s_intf_|Equal0~2_combout ) @@ -56200,7 +55950,7 @@ defparam \ula_|i2s_intf_|lrdivider~0 .lut_mask = 16'h0C0C; defparam \ula_|i2s_intf_|lrdivider~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y23_N17 +// Location: FF_X24_Y32_N29 dffeas \ula_|i2s_intf_|lrdivider[8] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider~0_combout ), @@ -56219,41 +55969,41 @@ defparam \ula_|i2s_intf_|lrdivider[8] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[8] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N24 +// Location: LCCOMB_X24_Y32_N26 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~18 ( // Equation(s): -// \ula_|i2s_intf_|Add0~18_combout = \ula_|i2s_intf_|Add0~17 $ (\ula_|i2s_intf_|lrdivider [9]) +// \ula_|i2s_intf_|Add0~18_combout = \ula_|i2s_intf_|lrdivider [9] $ (\ula_|i2s_intf_|Add0~17 ) .dataa(gnd), - .datab(gnd), + .datab(\ula_|i2s_intf_|lrdivider [9]), .datac(gnd), - .datad(\ula_|i2s_intf_|lrdivider [9]), + .datad(gnd), .cin(\ula_|i2s_intf_|Add0~17 ), .combout(\ula_|i2s_intf_|Add0~18_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|Add0~18 .lut_mask = 16'h0FF0; +defparam \ula_|i2s_intf_|Add0~18 .lut_mask = 16'h3C3C; defparam \ula_|i2s_intf_|Add0~18 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X28_Y23_N24 +// Location: LCCOMB_X24_Y32_N4 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[9]~3 ( // Equation(s): // \ula_|i2s_intf_|lrdivider[9]~3_combout = !\ula_|i2s_intf_|Add0~18_combout .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|Add0~18_combout ), + .datac(\ula_|i2s_intf_|Add0~18_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|lrdivider[9]~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[9]~3 .lut_mask = 16'h00FF; +defparam \ula_|i2s_intf_|lrdivider[9]~3 .lut_mask = 16'h0F0F; defparam \ula_|i2s_intf_|lrdivider[9]~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y23_N25 +// Location: FF_X24_Y32_N5 dffeas \ula_|i2s_intf_|lrdivider[9] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider[9]~3_combout ), @@ -56272,61 +56022,44 @@ defparam \ula_|i2s_intf_|lrdivider[9] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[9] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N0 +// Location: LCCOMB_X24_Y32_N6 cycloneive_lcell_comb \ula_|i2s_intf_|Equal0~0 ( // Equation(s): -// \ula_|i2s_intf_|Equal0~0_combout = (!\ula_|i2s_intf_|lrdivider [8] & (\ula_|i2s_intf_|lrdivider [9] & (\ula_|i2s_intf_|lrdivider [6] & \ula_|i2s_intf_|lrdivider [7]))) +// \ula_|i2s_intf_|Equal0~0_combout = (\ula_|i2s_intf_|lrdivider [6] & (!\ula_|i2s_intf_|lrdivider [8] & (\ula_|i2s_intf_|lrdivider [9] & \ula_|i2s_intf_|lrdivider [7]))) - .dataa(\ula_|i2s_intf_|lrdivider [8]), - .datab(\ula_|i2s_intf_|lrdivider [9]), - .datac(\ula_|i2s_intf_|lrdivider [6]), + .dataa(\ula_|i2s_intf_|lrdivider [6]), + .datab(\ula_|i2s_intf_|lrdivider [8]), + .datac(\ula_|i2s_intf_|lrdivider [9]), .datad(\ula_|i2s_intf_|lrdivider [7]), .cin(gnd), .combout(\ula_|i2s_intf_|Equal0~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|Equal0~0 .lut_mask = 16'h4000; +defparam \ula_|i2s_intf_|Equal0~0 .lut_mask = 16'h2000; defparam \ula_|i2s_intf_|Equal0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N30 +// Location: LCCOMB_X24_Y32_N30 cycloneive_lcell_comb \ula_|i2s_intf_|Equal0~2 ( // Equation(s): -// \ula_|i2s_intf_|Equal0~2_combout = (\ula_|i2s_intf_|Equal0~1_combout & (!\ula_|i2s_intf_|lrdivider [1] & (\ula_|i2s_intf_|mclk_r~_Duplicate_1_q & \ula_|i2s_intf_|Equal0~0_combout ))) +// \ula_|i2s_intf_|Equal0~2_combout = (!\ula_|i2s_intf_|lrdivider [1] & (\ula_|i2s_intf_|Equal0~1_combout & (\ula_|i2s_intf_|mclk_r~_Duplicate_1_q & \ula_|i2s_intf_|Equal0~0_combout ))) - .dataa(\ula_|i2s_intf_|Equal0~1_combout ), - .datab(\ula_|i2s_intf_|lrdivider [1]), + .dataa(\ula_|i2s_intf_|lrdivider [1]), + .datab(\ula_|i2s_intf_|Equal0~1_combout ), .datac(\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ), .datad(\ula_|i2s_intf_|Equal0~0_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|Equal0~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|Equal0~2 .lut_mask = 16'h2000; +defparam \ula_|i2s_intf_|Equal0~2 .lut_mask = 16'h4000; defparam \ula_|i2s_intf_|Equal0~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y22_N24 -cycloneive_lcell_comb \ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder ( -// Equation(s): -// \ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder_combout = \ula_|i2s_intf_|lrclk_r~0_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|lrclk_r~0_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder .lut_mask = 16'hFF00; -defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y22_N25 +// Location: FF_X23_Y31_N5 dffeas \ula_|i2s_intf_|lrclk_r~_Duplicate_2 ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder_combout ), + .d(\ula_|i2s_intf_|lrclk_r~0_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -56342,20 +56075,20 @@ defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_2 .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_2 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y22_N0 +// Location: LCCOMB_X23_Y31_N4 cycloneive_lcell_comb \ula_|i2s_intf_|lrclk_r~0 ( // Equation(s): // \ula_|i2s_intf_|lrclk_r~0_combout = \ula_|i2s_intf_|Equal0~2_combout $ (\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ) .dataa(gnd), .datab(\ula_|i2s_intf_|Equal0~2_combout ), - .datac(gnd), - .datad(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), + .datac(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|lrclk_r~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrclk_r~0 .lut_mask = 16'h33CC; +defparam \ula_|i2s_intf_|lrclk_r~0 .lut_mask = 16'h3C3C; defparam \ula_|i2s_intf_|lrclk_r~0 .sum_lutc_input = "datac"; // synopsys translate_on @@ -56397,7 +56130,7 @@ defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_1 .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y22_N0 +// Location: LCCOMB_X25_Y31_N0 cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[0]~5 ( // Equation(s): // \ula_|i2s_intf_|bitcount[0]~5_combout = !\ula_|i2s_intf_|bitcount [0] @@ -56415,10 +56148,27 @@ defparam \ula_|i2s_intf_|bitcount[0]~5 .lut_mask = 16'h3333; defparam \ula_|i2s_intf_|bitcount[0]~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y22_N11 +// Location: LCCOMB_X25_Y31_N26 +cycloneive_lcell_comb \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder ( +// Equation(s): +// \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder_combout = \ula_|i2s_intf_|bclk_r~1_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|i2s_intf_|bclk_r~1_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|bclk_r~_Duplicate_1feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder .lut_mask = 16'hFF00; +defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y31_N27 dffeas \ula_|i2s_intf_|bclk_r~_Duplicate_1 ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|bclk_r~1_combout ), + .d(\ula_|i2s_intf_|bclk_r~_Duplicate_1feeder_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -56434,24 +56184,24 @@ defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1 .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y22_N28 +// Location: LCCOMB_X25_Y31_N22 cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[4]~15 ( // Equation(s): -// \ula_|i2s_intf_|bitcount[4]~15_combout = (\ula_|i2s_intf_|Equal0~2_combout ) # ((\ula_|i2s_intf_|shiftreg[4]~1_combout & !\ula_|i2s_intf_|bclk_r~_Duplicate_1_q )) +// \ula_|i2s_intf_|bitcount[4]~15_combout = (\ula_|i2s_intf_|Equal0~2_combout ) # ((!\ula_|i2s_intf_|bclk_r~_Duplicate_1_q & \ula_|i2s_intf_|shiftreg[4]~1_combout )) - .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg[4]~1_combout ), + .dataa(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .datab(gnd), .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .datad(\ula_|i2s_intf_|shiftreg[4]~1_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|bitcount[4]~15_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[4]~15 .lut_mask = 16'hF0FC; +defparam \ula_|i2s_intf_|bitcount[4]~15 .lut_mask = 16'hF5F0; defparam \ula_|i2s_intf_|bitcount[4]~15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y22_N1 +// Location: FF_X25_Y31_N1 dffeas \ula_|i2s_intf_|bitcount[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|bitcount[0]~5_combout ), @@ -56470,25 +56220,25 @@ defparam \ula_|i2s_intf_|bitcount[0] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|bitcount[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y22_N2 +// Location: LCCOMB_X25_Y31_N2 cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[1]~7 ( // Equation(s): // \ula_|i2s_intf_|bitcount[1]~7_combout = (\ula_|i2s_intf_|bitcount [1] & (\ula_|i2s_intf_|bitcount[0]~6 & VCC)) # (!\ula_|i2s_intf_|bitcount [1] & (!\ula_|i2s_intf_|bitcount[0]~6 )) // \ula_|i2s_intf_|bitcount[1]~8 = CARRY((!\ula_|i2s_intf_|bitcount [1] & !\ula_|i2s_intf_|bitcount[0]~6 )) - .dataa(gnd), - .datab(\ula_|i2s_intf_|bitcount [1]), + .dataa(\ula_|i2s_intf_|bitcount [1]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\ula_|i2s_intf_|bitcount[0]~6 ), .combout(\ula_|i2s_intf_|bitcount[1]~7_combout ), .cout(\ula_|i2s_intf_|bitcount[1]~8 )); // synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[1]~7 .lut_mask = 16'hC303; +defparam \ula_|i2s_intf_|bitcount[1]~7 .lut_mask = 16'hA505; defparam \ula_|i2s_intf_|bitcount[1]~7 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y22_N3 +// Location: FF_X25_Y31_N3 dffeas \ula_|i2s_intf_|bitcount[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|bitcount[1]~7_combout ), @@ -56507,7 +56257,7 @@ defparam \ula_|i2s_intf_|bitcount[1] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|bitcount[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y22_N4 +// Location: LCCOMB_X25_Y31_N4 cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[2]~9 ( // Equation(s): // \ula_|i2s_intf_|bitcount[2]~9_combout = (\ula_|i2s_intf_|bitcount [2] & ((GND) # (!\ula_|i2s_intf_|bitcount[1]~8 ))) # (!\ula_|i2s_intf_|bitcount [2] & (\ula_|i2s_intf_|bitcount[1]~8 $ (GND))) @@ -56525,7 +56275,7 @@ defparam \ula_|i2s_intf_|bitcount[2]~9 .lut_mask = 16'h3CCF; defparam \ula_|i2s_intf_|bitcount[2]~9 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y22_N5 +// Location: FF_X25_Y31_N5 dffeas \ula_|i2s_intf_|bitcount[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|bitcount[2]~9_combout ), @@ -56544,7 +56294,7 @@ defparam \ula_|i2s_intf_|bitcount[2] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|bitcount[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y22_N6 +// Location: LCCOMB_X25_Y31_N6 cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[3]~11 ( // Equation(s): // \ula_|i2s_intf_|bitcount[3]~11_combout = (\ula_|i2s_intf_|bitcount [3] & (\ula_|i2s_intf_|bitcount[2]~10 & VCC)) # (!\ula_|i2s_intf_|bitcount [3] & (!\ula_|i2s_intf_|bitcount[2]~10 )) @@ -56562,7 +56312,7 @@ defparam \ula_|i2s_intf_|bitcount[3]~11 .lut_mask = 16'hA505; defparam \ula_|i2s_intf_|bitcount[3]~11 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y22_N7 +// Location: FF_X25_Y31_N7 dffeas \ula_|i2s_intf_|bitcount[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|bitcount[3]~11_combout ), @@ -56581,24 +56331,7 @@ defparam \ula_|i2s_intf_|bitcount[3] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|bitcount[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y22_N24 -cycloneive_lcell_comb \ula_|i2s_intf_|LessThan0~0 ( -// Equation(s): -// \ula_|i2s_intf_|LessThan0~0_combout = (\ula_|i2s_intf_|bitcount [3]) # (((\ula_|i2s_intf_|bitcount [2]) # (\ula_|i2s_intf_|bitcount [1])) # (!\ula_|i2s_intf_|bitcount [0])) - - .dataa(\ula_|i2s_intf_|bitcount [3]), - .datab(\ula_|i2s_intf_|bitcount [0]), - .datac(\ula_|i2s_intf_|bitcount [2]), - .datad(\ula_|i2s_intf_|bitcount [1]), - .cin(gnd), - .combout(\ula_|i2s_intf_|LessThan0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|LessThan0~0 .lut_mask = 16'hFFFB; -defparam \ula_|i2s_intf_|LessThan0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y22_N8 +// Location: LCCOMB_X25_Y31_N8 cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[4]~13 ( // Equation(s): // \ula_|i2s_intf_|bitcount[4]~13_combout = \ula_|i2s_intf_|bitcount [4] $ (\ula_|i2s_intf_|bitcount[3]~12 ) @@ -56615,7 +56348,7 @@ defparam \ula_|i2s_intf_|bitcount[4]~13 .lut_mask = 16'h3C3C; defparam \ula_|i2s_intf_|bitcount[4]~13 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y22_N9 +// Location: FF_X25_Y31_N9 dffeas \ula_|i2s_intf_|bitcount[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|bitcount[4]~13_combout ), @@ -56634,273 +56367,41 @@ defparam \ula_|i2s_intf_|bitcount[4] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|bitcount[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y22_N14 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~7 ( +// Location: LCCOMB_X25_Y31_N20 +cycloneive_lcell_comb \ula_|i2s_intf_|LessThan0~0 ( // Equation(s): -// \ula_|i2s_intf_|Add2~7_cout = CARRY(!\ula_|i2s_intf_|bdivider [0]) +// \ula_|i2s_intf_|LessThan0~0_combout = (\ula_|i2s_intf_|bitcount [1]) # (((\ula_|i2s_intf_|bitcount [2]) # (\ula_|i2s_intf_|bitcount [3])) # (!\ula_|i2s_intf_|bitcount [0])) - .dataa(\ula_|i2s_intf_|bdivider [0]), - .datab(gnd), - .datac(gnd), - .datad(vcc), + .dataa(\ula_|i2s_intf_|bitcount [1]), + .datab(\ula_|i2s_intf_|bitcount [0]), + .datac(\ula_|i2s_intf_|bitcount [2]), + .datad(\ula_|i2s_intf_|bitcount [3]), .cin(gnd), - .combout(), - .cout(\ula_|i2s_intf_|Add2~7_cout )); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~7 .lut_mask = 16'h0055; -defparam \ula_|i2s_intf_|Add2~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y22_N16 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~8 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~8_combout = (\ula_|i2s_intf_|bdivider [1] & (\ula_|i2s_intf_|Add2~7_cout & VCC)) # (!\ula_|i2s_intf_|bdivider [1] & (!\ula_|i2s_intf_|Add2~7_cout )) -// \ula_|i2s_intf_|Add2~9 = CARRY((!\ula_|i2s_intf_|bdivider [1] & !\ula_|i2s_intf_|Add2~7_cout )) - - .dataa(\ula_|i2s_intf_|bdivider [1]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|Add2~7_cout ), - .combout(\ula_|i2s_intf_|Add2~8_combout ), - .cout(\ula_|i2s_intf_|Add2~9 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~8 .lut_mask = 16'hA505; -defparam \ula_|i2s_intf_|Add2~8 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y22_N12 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~20 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~20_combout = (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|Add2~8_combout & ((!\ula_|i2s_intf_|Equal1~0_combout ) # (!\ula_|i2s_intf_|bdivider [0])))) - - .dataa(\ula_|i2s_intf_|bdivider [0]), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), - .datac(\ula_|i2s_intf_|Equal1~0_combout ), - .datad(\ula_|i2s_intf_|Add2~8_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|Add2~20_combout ), + .combout(\ula_|i2s_intf_|LessThan0~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|Add2~20 .lut_mask = 16'h1300; -defparam \ula_|i2s_intf_|Add2~20 .sum_lutc_input = "datac"; +defparam \ula_|i2s_intf_|LessThan0~0 .lut_mask = 16'hFFFB; +defparam \ula_|i2s_intf_|LessThan0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y22_N13 -dffeas \ula_|i2s_intf_|bdivider[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|Add2~20_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bdivider [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bdivider[1] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bdivider[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y22_N18 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~10 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~10_combout = (\ula_|i2s_intf_|bdivider [2] & (\ula_|i2s_intf_|Add2~9 $ (GND))) # (!\ula_|i2s_intf_|bdivider [2] & ((GND) # (!\ula_|i2s_intf_|Add2~9 ))) -// \ula_|i2s_intf_|Add2~11 = CARRY((!\ula_|i2s_intf_|Add2~9 ) # (!\ula_|i2s_intf_|bdivider [2])) - - .dataa(\ula_|i2s_intf_|bdivider [2]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|Add2~9 ), - .combout(\ula_|i2s_intf_|Add2~10_combout ), - .cout(\ula_|i2s_intf_|Add2~11 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~10 .lut_mask = 16'hA55F; -defparam \ula_|i2s_intf_|Add2~10 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y22_N16 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~17 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~17_combout = (!\ula_|i2s_intf_|shiftreg[4]~1_combout & (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~1_combout ) # (!\ula_|i2s_intf_|Add2~10_combout )))) - - .dataa(\ula_|i2s_intf_|Equal1~1_combout ), - .datab(\ula_|i2s_intf_|shiftreg[4]~1_combout ), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|Add2~10_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|Add2~17_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~17 .lut_mask = 16'h0203; -defparam \ula_|i2s_intf_|Add2~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y22_N17 -dffeas \ula_|i2s_intf_|bdivider[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|Add2~17_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bdivider [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bdivider[2] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bdivider[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y22_N20 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~12 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~12_combout = (\ula_|i2s_intf_|bdivider [3] & (\ula_|i2s_intf_|Add2~11 & VCC)) # (!\ula_|i2s_intf_|bdivider [3] & (!\ula_|i2s_intf_|Add2~11 )) -// \ula_|i2s_intf_|Add2~13 = CARRY((!\ula_|i2s_intf_|bdivider [3] & !\ula_|i2s_intf_|Add2~11 )) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|bdivider [3]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|Add2~11 ), - .combout(\ula_|i2s_intf_|Add2~12_combout ), - .cout(\ula_|i2s_intf_|Add2~13 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~12 .lut_mask = 16'hC303; -defparam \ula_|i2s_intf_|Add2~12 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y22_N2 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~19 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~19_combout = (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|Add2~12_combout & ((!\ula_|i2s_intf_|Equal1~0_combout ) # (!\ula_|i2s_intf_|bdivider [0])))) - - .dataa(\ula_|i2s_intf_|bdivider [0]), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), - .datac(\ula_|i2s_intf_|Equal1~0_combout ), - .datad(\ula_|i2s_intf_|Add2~12_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|Add2~19_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~19 .lut_mask = 16'h1300; -defparam \ula_|i2s_intf_|Add2~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y22_N3 -dffeas \ula_|i2s_intf_|bdivider[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|Add2~19_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bdivider [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bdivider[3] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bdivider[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y22_N22 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~14 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~14_combout = \ula_|i2s_intf_|Add2~13 $ (!\ula_|i2s_intf_|bdivider [4]) - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|bdivider [4]), - .cin(\ula_|i2s_intf_|Add2~13 ), - .combout(\ula_|i2s_intf_|Add2~14_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~14 .lut_mask = 16'hF00F; -defparam \ula_|i2s_intf_|Add2~14 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y22_N18 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~16 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~16_combout = (!\ula_|i2s_intf_|shiftreg[4]~1_combout & (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~1_combout ) # (!\ula_|i2s_intf_|Add2~14_combout )))) - - .dataa(\ula_|i2s_intf_|Equal1~1_combout ), - .datab(\ula_|i2s_intf_|shiftreg[4]~1_combout ), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|Add2~14_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|Add2~16_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~16 .lut_mask = 16'h0203; -defparam \ula_|i2s_intf_|Add2~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y22_N19 -dffeas \ula_|i2s_intf_|bdivider[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|Add2~16_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bdivider [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bdivider[4] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bdivider[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y22_N26 -cycloneive_lcell_comb \ula_|i2s_intf_|Equal1~0 ( -// Equation(s): -// \ula_|i2s_intf_|Equal1~0_combout = (!\ula_|i2s_intf_|bdivider [1] & (!\ula_|i2s_intf_|bdivider [3] & (\ula_|i2s_intf_|bdivider [2] & \ula_|i2s_intf_|bdivider [4]))) - - .dataa(\ula_|i2s_intf_|bdivider [1]), - .datab(\ula_|i2s_intf_|bdivider [3]), - .datac(\ula_|i2s_intf_|bdivider [2]), - .datad(\ula_|i2s_intf_|bdivider [4]), - .cin(gnd), - .combout(\ula_|i2s_intf_|Equal1~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Equal1~0 .lut_mask = 16'h1000; -defparam \ula_|i2s_intf_|Equal1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y22_N20 +// Location: LCCOMB_X25_Y31_N10 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[4]~1 ( // Equation(s): // \ula_|i2s_intf_|shiftreg[4]~1_combout = (\ula_|i2s_intf_|bdivider [0] & (\ula_|i2s_intf_|Equal1~0_combout & ((\ula_|i2s_intf_|LessThan0~0_combout ) # (!\ula_|i2s_intf_|bitcount [4])))) .dataa(\ula_|i2s_intf_|bdivider [0]), - .datab(\ula_|i2s_intf_|LessThan0~0_combout ), + .datab(\ula_|i2s_intf_|Equal1~0_combout ), .datac(\ula_|i2s_intf_|bitcount [4]), - .datad(\ula_|i2s_intf_|Equal1~0_combout ), + .datad(\ula_|i2s_intf_|LessThan0~0_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg[4]~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[4]~1 .lut_mask = 16'h8A00; +defparam \ula_|i2s_intf_|shiftreg[4]~1 .lut_mask = 16'h8808; defparam \ula_|i2s_intf_|shiftreg[4]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y22_N12 +// Location: LCCOMB_X24_Y31_N12 cycloneive_lcell_comb \ula_|i2s_intf_|Add2~18 ( // Equation(s): // \ula_|i2s_intf_|Add2~18_combout = (!\ula_|i2s_intf_|Equal0~2_combout & (!\ula_|i2s_intf_|shiftreg[4]~1_combout & ((\ula_|i2s_intf_|Equal1~0_combout ) # (!\ula_|i2s_intf_|bdivider [0])))) @@ -56917,7 +56418,7 @@ defparam \ula_|i2s_intf_|Add2~18 .lut_mask = 16'h1101; defparam \ula_|i2s_intf_|Add2~18 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y22_N13 +// Location: FF_X24_Y31_N13 dffeas \ula_|i2s_intf_|bdivider[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|Add2~18_combout ), @@ -56936,54 +56437,303 @@ defparam \ula_|i2s_intf_|bdivider[0] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|bdivider[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y22_N22 -cycloneive_lcell_comb \ula_|i2s_intf_|Equal1~1 ( +// Location: LCCOMB_X24_Y31_N2 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~7 ( // Equation(s): -// \ula_|i2s_intf_|Equal1~1_combout = (\ula_|i2s_intf_|bdivider [0] & \ula_|i2s_intf_|Equal1~0_combout ) +// \ula_|i2s_intf_|Add2~7_cout = CARRY(!\ula_|i2s_intf_|bdivider [0]) + + .dataa(\ula_|i2s_intf_|bdivider [0]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(), + .cout(\ula_|i2s_intf_|Add2~7_cout )); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~7 .lut_mask = 16'h0055; +defparam \ula_|i2s_intf_|Add2~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y31_N4 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~8 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~8_combout = (\ula_|i2s_intf_|bdivider [1] & (\ula_|i2s_intf_|Add2~7_cout & VCC)) # (!\ula_|i2s_intf_|bdivider [1] & (!\ula_|i2s_intf_|Add2~7_cout )) +// \ula_|i2s_intf_|Add2~9 = CARRY((!\ula_|i2s_intf_|bdivider [1] & !\ula_|i2s_intf_|Add2~7_cout )) + + .dataa(\ula_|i2s_intf_|bdivider [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|Add2~7_cout ), + .combout(\ula_|i2s_intf_|Add2~8_combout ), + .cout(\ula_|i2s_intf_|Add2~9 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~8 .lut_mask = 16'hA505; +defparam \ula_|i2s_intf_|Add2~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y31_N22 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~20 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~20_combout = (\ula_|i2s_intf_|Add2~8_combout & (!\ula_|i2s_intf_|Equal0~2_combout & ((!\ula_|i2s_intf_|Equal1~0_combout ) # (!\ula_|i2s_intf_|bdivider [0])))) + + .dataa(\ula_|i2s_intf_|bdivider [0]), + .datab(\ula_|i2s_intf_|Add2~8_combout ), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|Equal1~0_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|Add2~20_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~20 .lut_mask = 16'h040C; +defparam \ula_|i2s_intf_|Add2~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y31_N23 +dffeas \ula_|i2s_intf_|bdivider[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|Add2~20_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bdivider [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bdivider[1] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bdivider[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y31_N6 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~10 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~10_combout = (\ula_|i2s_intf_|bdivider [2] & (\ula_|i2s_intf_|Add2~9 $ (GND))) # (!\ula_|i2s_intf_|bdivider [2] & ((GND) # (!\ula_|i2s_intf_|Add2~9 ))) +// \ula_|i2s_intf_|Add2~11 = CARRY((!\ula_|i2s_intf_|Add2~9 ) # (!\ula_|i2s_intf_|bdivider [2])) + + .dataa(\ula_|i2s_intf_|bdivider [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|Add2~9 ), + .combout(\ula_|i2s_intf_|Add2~10_combout ), + .cout(\ula_|i2s_intf_|Add2~11 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~10 .lut_mask = 16'hA55F; +defparam \ula_|i2s_intf_|Add2~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y31_N26 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~17 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~17_combout = (!\ula_|i2s_intf_|Equal0~2_combout & (!\ula_|i2s_intf_|shiftreg[4]~1_combout & ((\ula_|i2s_intf_|Equal1~1_combout ) # (!\ula_|i2s_intf_|Add2~10_combout )))) + + .dataa(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(\ula_|i2s_intf_|Equal1~1_combout ), + .datac(\ula_|i2s_intf_|shiftreg[4]~1_combout ), + .datad(\ula_|i2s_intf_|Add2~10_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|Add2~17_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~17 .lut_mask = 16'h0405; +defparam \ula_|i2s_intf_|Add2~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y31_N27 +dffeas \ula_|i2s_intf_|bdivider[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|Add2~17_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bdivider [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bdivider[2] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bdivider[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y31_N8 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~12 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~12_combout = (\ula_|i2s_intf_|bdivider [3] & (\ula_|i2s_intf_|Add2~11 & VCC)) # (!\ula_|i2s_intf_|bdivider [3] & (!\ula_|i2s_intf_|Add2~11 )) +// \ula_|i2s_intf_|Add2~13 = CARRY((!\ula_|i2s_intf_|bdivider [3] & !\ula_|i2s_intf_|Add2~11 )) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|bdivider [3]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|Add2~11 ), + .combout(\ula_|i2s_intf_|Add2~12_combout ), + .cout(\ula_|i2s_intf_|Add2~13 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~12 .lut_mask = 16'hC303; +defparam \ula_|i2s_intf_|Add2~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y31_N0 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~19 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~19_combout = (\ula_|i2s_intf_|Add2~12_combout & (!\ula_|i2s_intf_|Equal0~2_combout & ((!\ula_|i2s_intf_|Equal1~0_combout ) # (!\ula_|i2s_intf_|bdivider [0])))) + + .dataa(\ula_|i2s_intf_|bdivider [0]), + .datab(\ula_|i2s_intf_|Add2~12_combout ), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|Equal1~0_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|Add2~19_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~19 .lut_mask = 16'h040C; +defparam \ula_|i2s_intf_|Add2~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y31_N1 +dffeas \ula_|i2s_intf_|bdivider[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|Add2~19_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bdivider [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bdivider[3] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bdivider[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y31_N10 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~14 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~14_combout = \ula_|i2s_intf_|Add2~13 $ (!\ula_|i2s_intf_|bdivider [4]) .dataa(gnd), .datab(gnd), - .datac(\ula_|i2s_intf_|bdivider [0]), - .datad(\ula_|i2s_intf_|Equal1~0_combout ), + .datac(gnd), + .datad(\ula_|i2s_intf_|bdivider [4]), + .cin(\ula_|i2s_intf_|Add2~13 ), + .combout(\ula_|i2s_intf_|Add2~14_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~14 .lut_mask = 16'hF00F; +defparam \ula_|i2s_intf_|Add2~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y31_N28 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~16 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~16_combout = (!\ula_|i2s_intf_|Equal0~2_combout & (!\ula_|i2s_intf_|shiftreg[4]~1_combout & ((\ula_|i2s_intf_|Equal1~1_combout ) # (!\ula_|i2s_intf_|Add2~14_combout )))) + + .dataa(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(\ula_|i2s_intf_|Equal1~1_combout ), + .datac(\ula_|i2s_intf_|shiftreg[4]~1_combout ), + .datad(\ula_|i2s_intf_|Add2~14_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|Add2~16_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~16 .lut_mask = 16'h0405; +defparam \ula_|i2s_intf_|Add2~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y31_N29 +dffeas \ula_|i2s_intf_|bdivider[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|Add2~16_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bdivider [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bdivider[4] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bdivider[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y31_N20 +cycloneive_lcell_comb \ula_|i2s_intf_|Equal1~0 ( +// Equation(s): +// \ula_|i2s_intf_|Equal1~0_combout = (!\ula_|i2s_intf_|bdivider [1] & (\ula_|i2s_intf_|bdivider [4] & (\ula_|i2s_intf_|bdivider [2] & !\ula_|i2s_intf_|bdivider [3]))) + + .dataa(\ula_|i2s_intf_|bdivider [1]), + .datab(\ula_|i2s_intf_|bdivider [4]), + .datac(\ula_|i2s_intf_|bdivider [2]), + .datad(\ula_|i2s_intf_|bdivider [3]), + .cin(gnd), + .combout(\ula_|i2s_intf_|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Equal1~0 .lut_mask = 16'h0040; +defparam \ula_|i2s_intf_|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y31_N14 +cycloneive_lcell_comb \ula_|i2s_intf_|Equal1~1 ( +// Equation(s): +// \ula_|i2s_intf_|Equal1~1_combout = (\ula_|i2s_intf_|Equal1~0_combout & \ula_|i2s_intf_|bdivider [0]) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|Equal1~0_combout ), + .datac(gnd), + .datad(\ula_|i2s_intf_|bdivider [0]), .cin(gnd), .combout(\ula_|i2s_intf_|Equal1~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|Equal1~1 .lut_mask = 16'hF000; +defparam \ula_|i2s_intf_|Equal1~1 .lut_mask = 16'hCC00; defparam \ula_|i2s_intf_|Equal1~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y22_N14 +// Location: LCCOMB_X25_Y31_N18 cycloneive_lcell_comb \ula_|i2s_intf_|bclk_r~0 ( // Equation(s): // \ula_|i2s_intf_|bclk_r~0_combout = \ula_|i2s_intf_|bclk_r~_Duplicate_1_q $ (((\ula_|i2s_intf_|LessThan0~0_combout ) # (!\ula_|i2s_intf_|bitcount [4]))) - .dataa(gnd), + .dataa(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), .datab(\ula_|i2s_intf_|LessThan0~0_combout ), .datac(\ula_|i2s_intf_|bitcount [4]), - .datad(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|bclk_r~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|bclk_r~0 .lut_mask = 16'h30CF; +defparam \ula_|i2s_intf_|bclk_r~0 .lut_mask = 16'h6565; defparam \ula_|i2s_intf_|bclk_r~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y22_N10 +// Location: LCCOMB_X25_Y31_N24 cycloneive_lcell_comb \ula_|i2s_intf_|bclk_r~1 ( // Equation(s): -// \ula_|i2s_intf_|bclk_r~1_combout = (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~1_combout & (\ula_|i2s_intf_|bclk_r~0_combout )) # (!\ula_|i2s_intf_|Equal1~1_combout & ((\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ))))) +// \ula_|i2s_intf_|bclk_r~1_combout = (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~1_combout & ((\ula_|i2s_intf_|bclk_r~0_combout ))) # (!\ula_|i2s_intf_|Equal1~1_combout & (\ula_|i2s_intf_|bclk_r~_Duplicate_1_q )))) .dataa(\ula_|i2s_intf_|Equal1~1_combout ), - .datab(\ula_|i2s_intf_|bclk_r~0_combout ), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), .datac(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|bclk_r~0_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|bclk_r~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|bclk_r~1 .lut_mask = 16'h00D8; +defparam \ula_|i2s_intf_|bclk_r~1 .lut_mask = 16'h3210; defparam \ula_|i2s_intf_|bclk_r~1 .sum_lutc_input = "datac"; // synopsys translate_on @@ -57006,61 +56756,44 @@ defparam \ula_|i2s_intf_|bclk_r .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|bclk_r .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y19_N24 -cycloneive_lcell_comb \ula_|pcm_outl[13]~feeder ( -// Equation(s): -// \ula_|pcm_outl[13]~feeder_combout = \D[3]~96_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\D[3]~96_combout ), - .cin(gnd), - .combout(\ula_|pcm_outl[13]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|pcm_outl[13]~feeder .lut_mask = 16'hFF00; -defparam \ula_|pcm_outl[13]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N2 +// Location: LCCOMB_X29_Y11_N14 cycloneive_lcell_comb \ula_|always0~2 ( // Equation(s): -// \ula_|always0~2_combout = (\z80_|memory_ifc_|nWR_out~0_combout & (!\z80_|memory_ifc_|nRD_out~2_combout & \z80_|resets_|SYNTHESIZED_WIRE_12~q )) +// \ula_|always0~2_combout = (!\z80_|memory_ifc_|nRD_out~2_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \z80_|memory_ifc_|nWR_out~0_combout )) - .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), - .datab(\z80_|memory_ifc_|nRD_out~2_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(gnd), + .dataa(\z80_|memory_ifc_|nRD_out~2_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(gnd), + .datad(\z80_|memory_ifc_|nWR_out~0_combout ), .cin(gnd), .combout(\ula_|always0~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|always0~2 .lut_mask = 16'h2020; +defparam \ula_|always0~2 .lut_mask = 16'h4400; defparam \ula_|always0~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y12_N20 +// Location: LCCOMB_X29_Y11_N26 cycloneive_lcell_comb \ula_|always0~3 ( // Equation(s): -// \ula_|always0~3_combout = (!\z80_|address_pins_|DFFE_apin_latch [0] & (\z80_|memory_ifc_|nIORQ_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \ula_|always0~2_combout ))) +// \ula_|always0~3_combout = (\z80_|memory_ifc_|nIORQ_out~0_combout & (!\z80_|address_pins_|DFFE_apin_latch [0] & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \ula_|always0~2_combout ))) - .dataa(\z80_|address_pins_|DFFE_apin_latch [0]), - .datab(\z80_|memory_ifc_|nIORQ_out~0_combout ), + .dataa(\z80_|memory_ifc_|nIORQ_out~0_combout ), + .datab(\z80_|address_pins_|DFFE_apin_latch [0]), .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .datad(\ula_|always0~2_combout ), .cin(gnd), .combout(\ula_|always0~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|always0~3 .lut_mask = 16'h4000; +defparam \ula_|always0~3 .lut_mask = 16'h2000; defparam \ula_|always0~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y19_N25 -dffeas \ula_|pcm_outl[13] ( +// Location: FF_X31_Y10_N31 +dffeas \ula_|pcm_outl[14] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|pcm_outl[13]~feeder_combout ), + .d(\D[4]~76_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -57069,27 +56802,27 @@ dffeas \ula_|pcm_outl[13] ( .ena(\ula_|always0~3_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\ula_|pcm_outl [13]), + .q(\ula_|pcm_outl [14]), .prn(vcc)); // synopsys translate_off -defparam \ula_|pcm_outl[13] .is_wysiwyg = "true"; -defparam \ula_|pcm_outl[13] .power_up = "low"; +defparam \ula_|pcm_outl[14] .is_wysiwyg = "true"; +defparam \ula_|pcm_outl[14] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y22_N26 +// Location: LCCOMB_X25_Y31_N16 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[0]~19 ( // Equation(s): // \ula_|i2s_intf_|shiftreg[0]~19_combout = (\ula_|i2s_intf_|Equal1~1_combout & (!\ula_|i2s_intf_|bclk_r~_Duplicate_1_q & ((\ula_|i2s_intf_|LessThan0~0_combout ) # (!\ula_|i2s_intf_|bitcount [4])))) .dataa(\ula_|i2s_intf_|Equal1~1_combout ), - .datab(\ula_|i2s_intf_|LessThan0~0_combout ), - .datac(\ula_|i2s_intf_|bitcount [4]), - .datad(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .datab(\ula_|i2s_intf_|bitcount [4]), + .datac(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .datad(\ula_|i2s_intf_|LessThan0~0_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg[0]~19_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[0]~19 .lut_mask = 16'h008A; +defparam \ula_|i2s_intf_|shiftreg[0]~19 .lut_mask = 16'h0A02; defparam \ula_|i2s_intf_|shiftreg[0]~19 .sum_lutc_input = "datac"; // synopsys translate_on @@ -57103,25 +56836,25 @@ defparam \AUD_ADCDAT~input .bus_hold = "false"; defparam \AUD_ADCDAT~input .simulate_z_as = "z"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N20 +// Location: LCCOMB_X24_Y31_N18 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[0]~20 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg[0]~20_combout = (\ula_|i2s_intf_|shiftreg[0]~19_combout & ((\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|shiftreg [0])) # (!\ula_|i2s_intf_|Equal0~2_combout & ((\AUD_ADCDAT~input_o ))))) # -// (!\ula_|i2s_intf_|shiftreg[0]~19_combout & (((\ula_|i2s_intf_|shiftreg [0])))) +// \ula_|i2s_intf_|shiftreg[0]~20_combout = (\ula_|i2s_intf_|Equal0~2_combout & (((\ula_|i2s_intf_|shiftreg [0])))) # (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|shiftreg[0]~19_combout & ((\AUD_ADCDAT~input_o ))) # +// (!\ula_|i2s_intf_|shiftreg[0]~19_combout & (\ula_|i2s_intf_|shiftreg [0])))) - .dataa(\ula_|i2s_intf_|shiftreg[0]~19_combout ), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .dataa(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(\ula_|i2s_intf_|shiftreg[0]~19_combout ), .datac(\ula_|i2s_intf_|shiftreg [0]), .datad(\AUD_ADCDAT~input_o ), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg[0]~20_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[0]~20 .lut_mask = 16'hF2D0; +defparam \ula_|i2s_intf_|shiftreg[0]~20 .lut_mask = 16'hF4B0; defparam \ula_|i2s_intf_|shiftreg[0]~20 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N21 +// Location: FF_X24_Y31_N19 dffeas \ula_|i2s_intf_|shiftreg[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg[0]~20_combout ), @@ -57140,41 +56873,41 @@ defparam \ula_|i2s_intf_|shiftreg[0] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N26 +// Location: LCCOMB_X23_Y31_N26 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~18 ( // Equation(s): // \ula_|i2s_intf_|shiftreg~18_combout = (\ula_|i2s_intf_|shiftreg [0] & !\ula_|i2s_intf_|Equal0~2_combout ) .dataa(gnd), .datab(\ula_|i2s_intf_|shiftreg [0]), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~18_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~18 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~18 .lut_mask = 16'h0C0C; defparam \ula_|i2s_intf_|shiftreg~18 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y22_N30 +// Location: LCCOMB_X25_Y31_N28 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[4]~2 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg[4]~2_combout = (\ula_|i2s_intf_|Equal0~2_combout ) # ((\ula_|i2s_intf_|shiftreg[4]~1_combout & \ula_|i2s_intf_|bclk_r~_Duplicate_1_q )) +// \ula_|i2s_intf_|shiftreg[4]~2_combout = (\ula_|i2s_intf_|Equal0~2_combout ) # ((\ula_|i2s_intf_|bclk_r~_Duplicate_1_q & \ula_|i2s_intf_|shiftreg[4]~1_combout )) - .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg[4]~1_combout ), + .dataa(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .datab(gnd), .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .datad(\ula_|i2s_intf_|shiftreg[4]~1_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg[4]~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[4]~2 .lut_mask = 16'hFCF0; +defparam \ula_|i2s_intf_|shiftreg[4]~2 .lut_mask = 16'hFAF0; defparam \ula_|i2s_intf_|shiftreg[4]~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N27 +// Location: FF_X23_Y31_N27 dffeas \ula_|i2s_intf_|shiftreg[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~18_combout ), @@ -57193,24 +56926,24 @@ defparam \ula_|i2s_intf_|shiftreg[1] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N24 +// Location: LCCOMB_X23_Y31_N12 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~17 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~17_combout = (\ula_|i2s_intf_|shiftreg [1] & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|shiftreg~17_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [1]) .dataa(gnd), - .datab(gnd), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), .datac(\ula_|i2s_intf_|shiftreg [1]), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~17_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~17 .lut_mask = 16'h00F0; +defparam \ula_|i2s_intf_|shiftreg~17 .lut_mask = 16'h3030; defparam \ula_|i2s_intf_|shiftreg~17 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N25 +// Location: FF_X23_Y31_N13 dffeas \ula_|i2s_intf_|shiftreg[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~17_combout ), @@ -57229,24 +56962,24 @@ defparam \ula_|i2s_intf_|shiftreg[2] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N18 +// Location: LCCOMB_X23_Y31_N22 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~16 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~16_combout = (\ula_|i2s_intf_|shiftreg [2] & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|shiftreg~16_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [2]) .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg [2]), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(gnd), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|shiftreg [2]), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~16_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~16 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~16 .lut_mask = 16'h0F00; defparam \ula_|i2s_intf_|shiftreg~16 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N19 +// Location: FF_X23_Y31_N23 dffeas \ula_|i2s_intf_|shiftreg[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~16_combout ), @@ -57265,24 +56998,24 @@ defparam \ula_|i2s_intf_|shiftreg[3] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N0 +// Location: LCCOMB_X23_Y31_N0 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~15 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~15_combout = (\ula_|i2s_intf_|shiftreg [3] & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|shiftreg~15_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [3]) .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg [3]), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|shiftreg [3]), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~15_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~15 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~15 .lut_mask = 16'h3030; defparam \ula_|i2s_intf_|shiftreg~15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N1 +// Location: FF_X23_Y31_N1 dffeas \ula_|i2s_intf_|shiftreg[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~15_combout ), @@ -57301,24 +57034,24 @@ defparam \ula_|i2s_intf_|shiftreg[4] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N10 +// Location: LCCOMB_X23_Y31_N14 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~14 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~14_combout = (\ula_|i2s_intf_|shiftreg [4] & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|shiftreg~14_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [4]) .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg [4]), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(gnd), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|shiftreg [4]), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~14_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~14 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~14 .lut_mask = 16'h0F00; defparam \ula_|i2s_intf_|shiftreg~14 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N11 +// Location: FF_X23_Y31_N15 dffeas \ula_|i2s_intf_|shiftreg[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~14_combout ), @@ -57337,24 +57070,24 @@ defparam \ula_|i2s_intf_|shiftreg[5] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N16 +// Location: LCCOMB_X23_Y31_N24 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~13 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~13_combout = (\ula_|i2s_intf_|shiftreg [5] & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|shiftreg~13_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [5]) - .dataa(\ula_|i2s_intf_|shiftreg [5]), - .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .dataa(gnd), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|shiftreg [5]), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~13_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~13 .lut_mask = 16'h00AA; +defparam \ula_|i2s_intf_|shiftreg~13 .lut_mask = 16'h3030; defparam \ula_|i2s_intf_|shiftreg~13 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N17 +// Location: FF_X23_Y31_N25 dffeas \ula_|i2s_intf_|shiftreg[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~13_combout ), @@ -57373,24 +57106,24 @@ defparam \ula_|i2s_intf_|shiftreg[6] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N30 +// Location: LCCOMB_X23_Y31_N30 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~12 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~12_combout = (\ula_|i2s_intf_|shiftreg [6] & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|shiftreg~12_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [6]) .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg [6]), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(gnd), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|shiftreg [6]), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~12_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~12 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~12 .lut_mask = 16'h0F00; defparam \ula_|i2s_intf_|shiftreg~12 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N31 +// Location: FF_X23_Y31_N31 dffeas \ula_|i2s_intf_|shiftreg[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~12_combout ), @@ -57409,24 +57142,24 @@ defparam \ula_|i2s_intf_|shiftreg[7] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N28 +// Location: LCCOMB_X23_Y31_N20 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~11 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~11_combout = (\ula_|i2s_intf_|shiftreg [7] & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|shiftreg~11_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [7]) .dataa(gnd), - .datab(gnd), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), .datac(\ula_|i2s_intf_|shiftreg [7]), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~11_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~11 .lut_mask = 16'h00F0; +defparam \ula_|i2s_intf_|shiftreg~11 .lut_mask = 16'h3030; defparam \ula_|i2s_intf_|shiftreg~11 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N29 +// Location: FF_X23_Y31_N21 dffeas \ula_|i2s_intf_|shiftreg[8] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~11_combout ), @@ -57445,24 +57178,24 @@ defparam \ula_|i2s_intf_|shiftreg[8] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[8] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N22 +// Location: LCCOMB_X23_Y31_N6 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~10 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~10_combout = (\ula_|i2s_intf_|shiftreg [8] & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|shiftreg~10_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [8]) .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg [8]), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(gnd), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|shiftreg [8]), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~10_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~10 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~10 .lut_mask = 16'h0F00; defparam \ula_|i2s_intf_|shiftreg~10 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N23 +// Location: FF_X23_Y31_N7 dffeas \ula_|i2s_intf_|shiftreg[9] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~10_combout ), @@ -57481,24 +57214,24 @@ defparam \ula_|i2s_intf_|shiftreg[9] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[9] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N12 +// Location: LCCOMB_X23_Y31_N16 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~9 ( // Equation(s): // \ula_|i2s_intf_|shiftreg~9_combout = (\ula_|i2s_intf_|shiftreg [9] & !\ula_|i2s_intf_|Equal0~2_combout ) - .dataa(gnd), + .dataa(\ula_|i2s_intf_|shiftreg [9]), .datab(gnd), - .datac(\ula_|i2s_intf_|shiftreg [9]), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~9_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~9 .lut_mask = 16'h00F0; +defparam \ula_|i2s_intf_|shiftreg~9 .lut_mask = 16'h0A0A; defparam \ula_|i2s_intf_|shiftreg~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N13 +// Location: FF_X23_Y31_N17 dffeas \ula_|i2s_intf_|shiftreg[10] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~9_combout ), @@ -57517,24 +57250,24 @@ defparam \ula_|i2s_intf_|shiftreg[10] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[10] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N2 +// Location: LCCOMB_X23_Y31_N18 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~8 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~8_combout = (\ula_|i2s_intf_|shiftreg [10] & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|shiftreg~8_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [10]) - .dataa(\ula_|i2s_intf_|shiftreg [10]), + .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|shiftreg [10]), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~8_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~8 .lut_mask = 16'h00AA; +defparam \ula_|i2s_intf_|shiftreg~8 .lut_mask = 16'h0F00; defparam \ula_|i2s_intf_|shiftreg~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N3 +// Location: FF_X23_Y31_N19 dffeas \ula_|i2s_intf_|shiftreg[11] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~8_combout ), @@ -57553,24 +57286,24 @@ defparam \ula_|i2s_intf_|shiftreg[11] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[11] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N8 +// Location: LCCOMB_X23_Y31_N28 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~7 ( // Equation(s): // \ula_|i2s_intf_|shiftreg~7_combout = (\ula_|i2s_intf_|shiftreg [11] & !\ula_|i2s_intf_|Equal0~2_combout ) .dataa(gnd), .datab(\ula_|i2s_intf_|shiftreg [11]), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~7_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~7 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~7 .lut_mask = 16'h0C0C; defparam \ula_|i2s_intf_|shiftreg~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N9 +// Location: FF_X23_Y31_N29 dffeas \ula_|i2s_intf_|shiftreg[12] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~7_combout ), @@ -57589,62 +57322,25 @@ defparam \ula_|i2s_intf_|shiftreg[12] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[12] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y22_N30 -cycloneive_lcell_comb \ula_|i2s_intf_|PCM_INR[14]~0 ( -// Equation(s): -// \ula_|i2s_intf_|PCM_INR[14]~0_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & (\ula_|i2s_intf_|shiftreg [14])) # (!\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & ((\ula_|i2s_intf_|PCM_INR [14]))))) # -// (!\ula_|i2s_intf_|Equal0~2_combout & (((\ula_|i2s_intf_|PCM_INR [14])))) - - .dataa(\ula_|i2s_intf_|shiftreg [14]), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), - .datac(\ula_|i2s_intf_|PCM_INR [14]), - .datad(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), - .cin(gnd), - .combout(\ula_|i2s_intf_|PCM_INR[14]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|PCM_INR[14]~0 .lut_mask = 16'hB8F0; -defparam \ula_|i2s_intf_|PCM_INR[14]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y22_N31 -dffeas \ula_|i2s_intf_|PCM_INR[14] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|PCM_INR[14]~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|PCM_INR [14]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|PCM_INR[14] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|PCM_INR[14] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y22_N28 +// Location: LCCOMB_X24_Y31_N30 cycloneive_lcell_comb \ula_|i2s_intf_|PCM_INL[14]~0 ( // Equation(s): -// \ula_|i2s_intf_|PCM_INL[14]~0_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & ((\ula_|i2s_intf_|PCM_INL [14]))) # (!\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & (\ula_|i2s_intf_|shiftreg [14])))) # +// \ula_|i2s_intf_|PCM_INL[14]~0_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & (\ula_|i2s_intf_|PCM_INL [14])) # (!\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & ((\ula_|i2s_intf_|shiftreg [14]))))) # // (!\ula_|i2s_intf_|Equal0~2_combout & (((\ula_|i2s_intf_|PCM_INL [14])))) - .dataa(\ula_|i2s_intf_|shiftreg [14]), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .dataa(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), .datac(\ula_|i2s_intf_|PCM_INL [14]), - .datad(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), + .datad(\ula_|i2s_intf_|shiftreg [14]), .cin(gnd), .combout(\ula_|i2s_intf_|PCM_INL[14]~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|PCM_INL[14]~0 .lut_mask = 16'hF0B8; +defparam \ula_|i2s_intf_|PCM_INL[14]~0 .lut_mask = 16'hF2D0; defparam \ula_|i2s_intf_|PCM_INL[14]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y22_N29 +// Location: FF_X24_Y31_N31 dffeas \ula_|i2s_intf_|PCM_INL[14] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|PCM_INL[14]~0_combout ), @@ -57663,15 +57359,52 @@ defparam \ula_|i2s_intf_|PCM_INL[14] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|PCM_INL[14] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y22_N6 +// Location: LCCOMB_X24_Y31_N16 +cycloneive_lcell_comb \ula_|i2s_intf_|PCM_INR[14]~0 ( +// Equation(s): +// \ula_|i2s_intf_|PCM_INR[14]~0_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & ((\ula_|i2s_intf_|shiftreg [14]))) # (!\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & (\ula_|i2s_intf_|PCM_INR [14])))) # +// (!\ula_|i2s_intf_|Equal0~2_combout & (((\ula_|i2s_intf_|PCM_INR [14])))) + + .dataa(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), + .datac(\ula_|i2s_intf_|PCM_INR [14]), + .datad(\ula_|i2s_intf_|shiftreg [14]), + .cin(gnd), + .combout(\ula_|i2s_intf_|PCM_INR[14]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|PCM_INR[14]~0 .lut_mask = 16'hF870; +defparam \ula_|i2s_intf_|PCM_INR[14]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y31_N17 +dffeas \ula_|i2s_intf_|PCM_INR[14] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|PCM_INR[14]~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|PCM_INR [14]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|PCM_INR[14] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|PCM_INR[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y31_N24 cycloneive_lcell_comb \ula_|pcm_outr~0 ( // Equation(s): -// \ula_|pcm_outr~0_combout = (\ula_|i2s_intf_|PCM_INR [14]) # (\ula_|i2s_intf_|PCM_INL [14]) +// \ula_|pcm_outr~0_combout = (\ula_|i2s_intf_|PCM_INL [14]) # (\ula_|i2s_intf_|PCM_INR [14]) .dataa(gnd), .datab(gnd), - .datac(\ula_|i2s_intf_|PCM_INR [14]), - .datad(\ula_|i2s_intf_|PCM_INL [14]), + .datac(\ula_|i2s_intf_|PCM_INL [14]), + .datad(\ula_|i2s_intf_|PCM_INR [14]), .cin(gnd), .combout(\ula_|pcm_outr~0_combout ), .cout()); @@ -57680,7 +57413,7 @@ defparam \ula_|pcm_outr~0 .lut_mask = 16'hFFF0; defparam \ula_|pcm_outr~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y22_N7 +// Location: FF_X24_Y31_N25 dffeas \ula_|pcm_outl[12] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\ula_|pcm_outr~0_combout ), @@ -57699,24 +57432,24 @@ defparam \ula_|pcm_outl[12] .is_wysiwyg = "true"; defparam \ula_|pcm_outl[12] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N14 +// Location: LCCOMB_X23_Y31_N10 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~6 ( // Equation(s): // \ula_|i2s_intf_|shiftreg~6_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|pcm_outl [12]))) # (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|shiftreg [12])) .dataa(gnd), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), - .datac(\ula_|i2s_intf_|shiftreg [12]), + .datab(\ula_|i2s_intf_|shiftreg [12]), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), .datad(\ula_|pcm_outl [12]), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~6_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~6 .lut_mask = 16'hFC30; +defparam \ula_|i2s_intf_|shiftreg~6 .lut_mask = 16'hFC0C; defparam \ula_|i2s_intf_|shiftreg~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N15 +// Location: FF_X23_Y31_N11 dffeas \ula_|i2s_intf_|shiftreg[13] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~6_combout ), @@ -57735,24 +57468,43 @@ defparam \ula_|i2s_intf_|shiftreg[13] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[13] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N4 +// Location: FF_X23_Y14_N9 +dffeas \ula_|pcm_outl[13] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\D[3]~74_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|always0~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|pcm_outl [13]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|pcm_outl[13] .is_wysiwyg = "true"; +defparam \ula_|pcm_outl[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y31_N8 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~5 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~5_combout = (\ula_|i2s_intf_|Equal0~2_combout & (\ula_|pcm_outl [13])) # (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|shiftreg [13]))) +// \ula_|i2s_intf_|shiftreg~5_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|pcm_outl [13]))) # (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|shiftreg [13])) - .dataa(gnd), - .datab(\ula_|pcm_outl [13]), - .datac(\ula_|i2s_intf_|shiftreg [13]), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .dataa(\ula_|i2s_intf_|shiftreg [13]), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(gnd), + .datad(\ula_|pcm_outl [13]), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~5_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~5 .lut_mask = 16'hCCF0; +defparam \ula_|i2s_intf_|shiftreg~5 .lut_mask = 16'hEE22; defparam \ula_|i2s_intf_|shiftreg~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N5 +// Location: FF_X23_Y31_N9 dffeas \ula_|i2s_intf_|shiftreg[14] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~5_combout ), @@ -57771,43 +57523,24 @@ defparam \ula_|i2s_intf_|shiftreg[14] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[14] .power_up = "low"; // synopsys translate_on -// Location: FF_X29_Y14_N31 -dffeas \ula_|pcm_outl[14] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\D[4]~98_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|always0~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|pcm_outl [14]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|pcm_outl[14] .is_wysiwyg = "true"; -defparam \ula_|pcm_outl[14] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y22_N4 +// Location: LCCOMB_X23_Y31_N2 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~4 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~4_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|pcm_outl [14]))) # (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|shiftreg [14])) +// \ula_|i2s_intf_|shiftreg~4_combout = (\ula_|i2s_intf_|Equal0~2_combout & (\ula_|pcm_outl [14])) # (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|shiftreg [14]))) - .dataa(\ula_|i2s_intf_|shiftreg [14]), - .datab(gnd), - .datac(\ula_|pcm_outl [14]), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .dataa(\ula_|pcm_outl [14]), + .datab(\ula_|i2s_intf_|shiftreg [14]), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~4_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~4 .lut_mask = 16'hF0AA; +defparam \ula_|i2s_intf_|shiftreg~4 .lut_mask = 16'hACAC; defparam \ula_|i2s_intf_|shiftreg~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y22_N5 +// Location: FF_X23_Y31_N3 dffeas \ula_|i2s_intf_|shiftreg[15] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~4_combout ), @@ -57826,24 +57559,24 @@ defparam \ula_|i2s_intf_|shiftreg[15] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[15] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y22_N0 +// Location: LCCOMB_X23_Y32_N12 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~3 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~3_combout = (\ula_|i2s_intf_|shiftreg [15] & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|shiftreg~3_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [15]) - .dataa(gnd), + .dataa(\ula_|i2s_intf_|Equal0~2_combout ), .datab(gnd), .datac(\ula_|i2s_intf_|shiftreg [15]), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~3 .lut_mask = 16'h00F0; +defparam \ula_|i2s_intf_|shiftreg~3 .lut_mask = 16'h5050; defparam \ula_|i2s_intf_|shiftreg~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y22_N1 +// Location: FF_X23_Y32_N13 dffeas \ula_|i2s_intf_|shiftreg[16] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~3_combout ), @@ -57862,20 +57595,20 @@ defparam \ula_|i2s_intf_|shiftreg[16] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[16] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y22_N10 +// Location: LCCOMB_X23_Y32_N2 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~0 ( // Equation(s): // \ula_|i2s_intf_|shiftreg~0_combout = (\ula_|i2s_intf_|shiftreg [16] & !\ula_|i2s_intf_|Equal0~2_combout ) - .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg [16]), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .dataa(\ula_|i2s_intf_|shiftreg [16]), + .datab(gnd), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~0 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~0 .lut_mask = 16'h0A0A; defparam \ula_|i2s_intf_|shiftreg~0 .sum_lutc_input = "datac"; // synopsys translate_on @@ -57898,32 +57631,85 @@ defparam \ula_|i2s_intf_|shiftreg[17] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[17] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X38_Y33_N8 -cycloneive_lcell_comb \ula_|video_|LessThan2~0 ( +// Location: LCCOMB_X31_Y10_N24 +cycloneive_lcell_comb \ula_|border[1]~feeder ( // Equation(s): -// \ula_|video_|LessThan2~0_combout = (!\ula_|video_|vga_vc [9] & (!\ula_|video_|vga_vc [8] & (!\ula_|video_|vga_vc [7] & !\ula_|video_|vga_vc [6]))) +// \ula_|border[1]~feeder_combout = \D[1]~32_combout - .dataa(\ula_|video_|vga_vc [9]), - .datab(\ula_|video_|vga_vc [8]), - .datac(\ula_|video_|vga_vc [7]), - .datad(\ula_|video_|vga_vc [6]), + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\D[1]~32_combout ), .cin(gnd), - .combout(\ula_|video_|LessThan2~0_combout ), + .combout(\ula_|border[1]~feeder_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|LessThan2~0 .lut_mask = 16'h0001; -defparam \ula_|video_|LessThan2~0 .sum_lutc_input = "datac"; +defparam \ula_|border[1]~feeder .lut_mask = 16'hFF00; +defparam \ula_|border[1]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y33_N4 +// Location: FF_X31_Y10_N25 +dffeas \ula_|border[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|border[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|always0~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|border [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|border[1] .is_wysiwyg = "true"; +defparam \ula_|border[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y32_N30 +cycloneive_lcell_comb \ula_|video_|LessThan4~0 ( +// Equation(s): +// \ula_|video_|LessThan4~0_combout = (((!\ula_|video_|vga_hc [4] & !\ula_|video_|vga_hc [5])) # (!\ula_|video_|vga_hc [7])) # (!\ula_|video_|vga_hc [6]) + + .dataa(\ula_|video_|vga_hc [4]), + .datab(\ula_|video_|vga_hc [6]), + .datac(\ula_|video_|vga_hc [7]), + .datad(\ula_|video_|vga_hc [5]), + .cin(gnd), + .combout(\ula_|video_|LessThan4~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|LessThan4~0 .lut_mask = 16'h3F7F; +defparam \ula_|video_|LessThan4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y32_N26 +cycloneive_lcell_comb \ula_|video_|screen_en~0 ( +// Equation(s): +// \ula_|video_|screen_en~0_combout = (!\ula_|video_|vga_vc [9] & (\ula_|video_|vga_hc [9] $ (((\ula_|video_|vga_hc [8]) # (!\ula_|video_|LessThan4~0_combout ))))) + + .dataa(\ula_|video_|vga_hc [9]), + .datab(\ula_|video_|vga_vc [9]), + .datac(\ula_|video_|vga_hc [8]), + .datad(\ula_|video_|LessThan4~0_combout ), + .cin(gnd), + .combout(\ula_|video_|screen_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|screen_en~0 .lut_mask = 16'h1211; +defparam \ula_|video_|screen_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y32_N28 cycloneive_lcell_comb \ula_|video_|LessThan6~0 ( // Equation(s): -// \ula_|video_|LessThan6~0_combout = (!\ula_|video_|vga_vc [2] & (!\ula_|video_|vga_vc [3] & ((!\ula_|video_|vga_vc [0]) # (!\ula_|video_|vga_vc [1])))) +// \ula_|video_|LessThan6~0_combout = (!\ula_|video_|vga_vc [3] & (!\ula_|video_|vga_vc [2] & ((!\ula_|video_|vga_vc [1]) # (!\ula_|video_|vga_vc [0])))) - .dataa(\ula_|video_|vga_vc [2]), - .datab(\ula_|video_|vga_vc [3]), - .datac(\ula_|video_|vga_vc [1]), - .datad(\ula_|video_|vga_vc [0]), + .dataa(\ula_|video_|vga_vc [3]), + .datab(\ula_|video_|vga_vc [2]), + .datac(\ula_|video_|vga_vc [0]), + .datad(\ula_|video_|vga_vc [1]), .cin(gnd), .combout(\ula_|video_|LessThan6~0_combout ), .cout()); @@ -57932,76 +57718,128 @@ defparam \ula_|video_|LessThan6~0 .lut_mask = 16'h0111; defparam \ula_|video_|LessThan6~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y33_N30 +// Location: LCCOMB_X35_Y32_N12 +cycloneive_lcell_comb \ula_|video_|LessThan6~1 ( +// Equation(s): +// \ula_|video_|LessThan6~1_combout = ((!\ula_|video_|vga_vc [5] & ((\ula_|video_|LessThan6~0_combout ) # (!\ula_|video_|vga_vc [4])))) # (!\ula_|video_|vga_vc [6]) + + .dataa(\ula_|video_|vga_vc [4]), + .datab(\ula_|video_|vga_vc [6]), + .datac(\ula_|video_|vga_vc [5]), + .datad(\ula_|video_|LessThan6~0_combout ), + .cin(gnd), + .combout(\ula_|video_|LessThan6~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|LessThan6~1 .lut_mask = 16'h3F37; +defparam \ula_|video_|LessThan6~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y32_N22 +cycloneive_lcell_comb \ula_|video_|screen_en~1 ( +// Equation(s): +// \ula_|video_|screen_en~1_combout = (\ula_|video_|screen_en~0_combout & ((\ula_|video_|vga_vc [7] & ((\ula_|video_|LessThan6~1_combout ) # (!\ula_|video_|vga_vc [8]))) # (!\ula_|video_|vga_vc [7] & ((\ula_|video_|vga_vc [8]) # +// (!\ula_|video_|LessThan6~1_combout ))))) + + .dataa(\ula_|video_|vga_vc [7]), + .datab(\ula_|video_|vga_vc [8]), + .datac(\ula_|video_|screen_en~0_combout ), + .datad(\ula_|video_|LessThan6~1_combout ), + .cin(gnd), + .combout(\ula_|video_|screen_en~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|screen_en~1 .lut_mask = 16'hE070; +defparam \ula_|video_|screen_en~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y32_N14 +cycloneive_lcell_comb \ula_|video_|LessThan2~0 ( +// Equation(s): +// \ula_|video_|LessThan2~0_combout = (!\ula_|video_|vga_vc [9] & (!\ula_|video_|vga_vc [8] & (!\ula_|video_|vga_vc [6] & !\ula_|video_|vga_vc [7]))) + + .dataa(\ula_|video_|vga_vc [9]), + .datab(\ula_|video_|vga_vc [8]), + .datac(\ula_|video_|vga_vc [6]), + .datad(\ula_|video_|vga_vc [7]), + .cin(gnd), + .combout(\ula_|video_|LessThan2~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|LessThan2~0 .lut_mask = 16'h0001; +defparam \ula_|video_|LessThan2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y32_N12 cycloneive_lcell_comb \ula_|video_|LessThan2~1 ( // Equation(s): // \ula_|video_|LessThan2~1_combout = (\ula_|video_|LessThan2~0_combout & (((!\ula_|video_|vga_vc [4] & \ula_|video_|LessThan6~0_combout )) # (!\ula_|video_|vga_vc [5]))) - .dataa(\ula_|video_|vga_vc [5]), - .datab(\ula_|video_|vga_vc [4]), + .dataa(\ula_|video_|vga_vc [4]), + .datab(\ula_|video_|vga_vc [5]), .datac(\ula_|video_|LessThan2~0_combout ), .datad(\ula_|video_|LessThan6~0_combout ), .cin(gnd), .combout(\ula_|video_|LessThan2~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|LessThan2~1 .lut_mask = 16'h7050; +defparam \ula_|video_|LessThan2~1 .lut_mask = 16'h7030; defparam \ula_|video_|LessThan2~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y33_N16 +// Location: LCCOMB_X36_Y32_N4 cycloneive_lcell_comb \ula_|video_|LessThan3~0 ( // Equation(s): -// \ula_|video_|LessThan3~0_combout = ((\ula_|video_|LessThan6~0_combout & (!\ula_|video_|vga_vc [5] & \ula_|video_|Equal2~0_combout ))) # (!\ula_|video_|vga_vc [9]) +// \ula_|video_|LessThan3~0_combout = ((!\ula_|video_|vga_vc [5] & (\ula_|video_|LessThan6~0_combout & \ula_|video_|Equal2~0_combout ))) # (!\ula_|video_|vga_vc [9]) - .dataa(\ula_|video_|vga_vc [9]), + .dataa(\ula_|video_|vga_vc [5]), .datab(\ula_|video_|LessThan6~0_combout ), - .datac(\ula_|video_|vga_vc [5]), + .datac(\ula_|video_|vga_vc [9]), .datad(\ula_|video_|Equal2~0_combout ), .cin(gnd), .combout(\ula_|video_|LessThan3~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|LessThan3~0 .lut_mask = 16'h5D55; +defparam \ula_|video_|LessThan3~0 .lut_mask = 16'h4F0F; defparam \ula_|video_|LessThan3~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y33_N22 +// Location: LCCOMB_X34_Y32_N2 cycloneive_lcell_comb \ula_|video_|LessThan0~0 ( // Equation(s): -// \ula_|video_|LessThan0~0_combout = (!\ula_|video_|vga_hc [4] & (!\ula_|video_|vga_hc [6] & !\ula_|video_|vga_hc [5])) +// \ula_|video_|LessThan0~0_combout = (!\ula_|video_|vga_hc [6] & (!\ula_|video_|vga_hc [4] & !\ula_|video_|vga_hc [5])) - .dataa(\ula_|video_|vga_hc [4]), + .dataa(gnd), .datab(\ula_|video_|vga_hc [6]), - .datac(gnd), + .datac(\ula_|video_|vga_hc [4]), .datad(\ula_|video_|vga_hc [5]), .cin(gnd), .combout(\ula_|video_|LessThan0~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|LessThan0~0 .lut_mask = 16'h0011; +defparam \ula_|video_|LessThan0~0 .lut_mask = 16'h0003; defparam \ula_|video_|LessThan0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y33_N24 +// Location: LCCOMB_X34_Y32_N0 cycloneive_lcell_comb \ula_|video_|disp_enable~0 ( // Equation(s): -// \ula_|video_|disp_enable~0_combout = (\ula_|video_|vga_hc [8] & (((\ula_|video_|LessThan0~0_combout & !\ula_|video_|vga_hc [7])) # (!\ula_|video_|vga_hc [9]))) # (!\ula_|video_|vga_hc [8] & ((\ula_|video_|vga_hc [9]) # -// ((!\ula_|video_|LessThan0~0_combout & \ula_|video_|vga_hc [7])))) +// \ula_|video_|disp_enable~0_combout = (\ula_|video_|vga_hc [8] & (((!\ula_|video_|vga_hc [7] & \ula_|video_|LessThan0~0_combout )) # (!\ula_|video_|vga_hc [9]))) # (!\ula_|video_|vga_hc [8] & ((\ula_|video_|vga_hc [9]) # ((\ula_|video_|vga_hc [7] & +// !\ula_|video_|LessThan0~0_combout )))) - .dataa(\ula_|video_|LessThan0~0_combout ), + .dataa(\ula_|video_|vga_hc [7]), .datab(\ula_|video_|vga_hc [8]), - .datac(\ula_|video_|vga_hc [7]), - .datad(\ula_|video_|vga_hc [9]), + .datac(\ula_|video_|vga_hc [9]), + .datad(\ula_|video_|LessThan0~0_combout ), .cin(gnd), .combout(\ula_|video_|disp_enable~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|disp_enable~0 .lut_mask = 16'h3BDC; +defparam \ula_|video_|disp_enable~0 .lut_mask = 16'h7C3E; defparam \ula_|video_|disp_enable~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y33_N2 +// Location: LCCOMB_X36_Y32_N6 cycloneive_lcell_comb \ula_|video_|disp_enable~1 ( // Equation(s): // \ula_|video_|disp_enable~1_combout = (!\ula_|video_|LessThan2~1_combout & (\ula_|video_|LessThan3~0_combout & \ula_|video_|disp_enable~0_combout )) @@ -58018,239 +57856,7 @@ defparam \ula_|video_|disp_enable~1 .lut_mask = 16'h4400; defparam \ula_|video_|disp_enable~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y22_N11 -dffeas \ula_|border[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\D[1]~34_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|always0~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|border [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|border[1] .is_wysiwyg = "true"; -defparam \ula_|border[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y33_N8 -cycloneive_lcell_comb \ula_|video_|LessThan6~1 ( -// Equation(s): -// \ula_|video_|LessThan6~1_combout = ((!\ula_|video_|vga_vc [5] & ((\ula_|video_|LessThan6~0_combout ) # (!\ula_|video_|vga_vc [4])))) # (!\ula_|video_|vga_vc [6]) - - .dataa(\ula_|video_|vga_vc [6]), - .datab(\ula_|video_|vga_vc [5]), - .datac(\ula_|video_|vga_vc [4]), - .datad(\ula_|video_|LessThan6~0_combout ), - .cin(gnd), - .combout(\ula_|video_|LessThan6~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|LessThan6~1 .lut_mask = 16'h7757; -defparam \ula_|video_|LessThan6~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N28 -cycloneive_lcell_comb \ula_|video_|LessThan4~0 ( -// Equation(s): -// \ula_|video_|LessThan4~0_combout = (((!\ula_|video_|vga_hc [4] & !\ula_|video_|vga_hc [5])) # (!\ula_|video_|vga_hc [7])) # (!\ula_|video_|vga_hc [6]) - - .dataa(\ula_|video_|vga_hc [4]), - .datab(\ula_|video_|vga_hc [5]), - .datac(\ula_|video_|vga_hc [6]), - .datad(\ula_|video_|vga_hc [7]), - .cin(gnd), - .combout(\ula_|video_|LessThan4~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|LessThan4~0 .lut_mask = 16'h1FFF; -defparam \ula_|video_|LessThan4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y33_N10 -cycloneive_lcell_comb \ula_|video_|screen_en~0 ( -// Equation(s): -// \ula_|video_|screen_en~0_combout = (!\ula_|video_|vga_vc [9] & (\ula_|video_|vga_hc [9] $ (((\ula_|video_|vga_hc [8]) # (!\ula_|video_|LessThan4~0_combout ))))) - - .dataa(\ula_|video_|vga_hc [9]), - .datab(\ula_|video_|vga_vc [9]), - .datac(\ula_|video_|LessThan4~0_combout ), - .datad(\ula_|video_|vga_hc [8]), - .cin(gnd), - .combout(\ula_|video_|screen_en~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|screen_en~0 .lut_mask = 16'h1121; -defparam \ula_|video_|screen_en~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y33_N22 -cycloneive_lcell_comb \ula_|video_|screen_en~1 ( -// Equation(s): -// \ula_|video_|screen_en~1_combout = (\ula_|video_|screen_en~0_combout & ((\ula_|video_|vga_vc [7] & ((\ula_|video_|LessThan6~1_combout ) # (!\ula_|video_|vga_vc [8]))) # (!\ula_|video_|vga_vc [7] & ((\ula_|video_|vga_vc [8]) # -// (!\ula_|video_|LessThan6~1_combout ))))) - - .dataa(\ula_|video_|vga_vc [7]), - .datab(\ula_|video_|vga_vc [8]), - .datac(\ula_|video_|LessThan6~1_combout ), - .datad(\ula_|video_|screen_en~0_combout ), - .cin(gnd), - .combout(\ula_|video_|screen_en~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|screen_en~1 .lut_mask = 16'hE700; -defparam \ula_|video_|screen_en~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y33_N28 -cycloneive_lcell_comb \ula_|video_|attr_prefetch[1]~feeder ( -// Equation(s): -// \ula_|video_|attr_prefetch[1]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|attr_prefetch[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|attr_prefetch[1]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|attr_prefetch[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N10 -cycloneive_lcell_comb \ula_|video_|Decoder0~1 ( -// Equation(s): -// \ula_|video_|Decoder0~1_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|vga_hc [3] & (\ula_|video_|vga_hc [1] & !\ula_|video_|vga_hc [0]))) - - .dataa(\ula_|video_|vga_hc [2]), - .datab(\ula_|video_|vga_hc [3]), - .datac(\ula_|video_|vga_hc [1]), - .datad(\ula_|video_|vga_hc [0]), - .cin(gnd), - .combout(\ula_|video_|Decoder0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Decoder0~1 .lut_mask = 16'h0080; -defparam \ula_|video_|Decoder0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y33_N29 -dffeas \ula_|video_|attr_prefetch[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|attr_prefetch[1]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|attr_prefetch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|attr_prefetch[1] .is_wysiwyg = "true"; -defparam \ula_|video_|attr_prefetch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N12 -cycloneive_lcell_comb \ula_|video_|Decoder0~0 ( -// Equation(s): -// \ula_|video_|Decoder0~0_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|vga_hc [3] & (\ula_|video_|vga_hc [1] & \ula_|video_|vga_hc [0]))) - - .dataa(\ula_|video_|vga_hc [2]), - .datab(\ula_|video_|vga_hc [3]), - .datac(\ula_|video_|vga_hc [1]), - .datad(\ula_|video_|vga_hc [0]), - .cin(gnd), - .combout(\ula_|video_|Decoder0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Decoder0~0 .lut_mask = 16'h8000; -defparam \ula_|video_|Decoder0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y33_N27 -dffeas \ula_|video_|attr[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|attr_prefetch [1]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|Decoder0~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|attr [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|attr[1] .is_wysiwyg = "true"; -defparam \ula_|video_|attr[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y33_N10 -cycloneive_lcell_comb \ula_|video_|attr_prefetch[4]~feeder ( -// Equation(s): -// \ula_|video_|attr_prefetch[4]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|attr_prefetch[4]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|attr_prefetch[4]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|attr_prefetch[4]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y33_N11 -dffeas \ula_|video_|attr_prefetch[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|attr_prefetch[4]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|attr_prefetch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|attr_prefetch[4] .is_wysiwyg = "true"; -defparam \ula_|video_|attr_prefetch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X37_Y33_N13 -dffeas \ula_|video_|attr[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|attr_prefetch [4]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|Decoder0~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|attr [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|attr[4] .is_wysiwyg = "true"; -defparam \ula_|video_|attr[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y33_N24 +// Location: LCCOMB_X38_Y32_N8 cycloneive_lcell_comb \ula_|video_|attr_prefetch[7]~feeder ( // Equation(s): // \ula_|video_|attr_prefetch[7]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 @@ -58267,7 +57873,24 @@ defparam \ula_|video_|attr_prefetch[7]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|attr_prefetch[7]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N25 +// Location: LCCOMB_X35_Y31_N24 +cycloneive_lcell_comb \ula_|video_|Decoder0~1 ( +// Equation(s): +// \ula_|video_|Decoder0~1_combout = (\ula_|video_|vga_hc [1] & (\ula_|video_|vga_hc [3] & (\ula_|video_|vga_hc [2] & !\ula_|video_|vga_hc [0]))) + + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|vga_hc [3]), + .datac(\ula_|video_|vga_hc [2]), + .datad(\ula_|video_|vga_hc [0]), + .cin(gnd), + .combout(\ula_|video_|Decoder0~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Decoder0~1 .lut_mask = 16'h0080; +defparam \ula_|video_|Decoder0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X38_Y32_N9 dffeas \ula_|video_|attr_prefetch[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr_prefetch[7]~feeder_combout ), @@ -58286,7 +57909,24 @@ defparam \ula_|video_|attr_prefetch[7] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[7] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y33_N5 +// Location: LCCOMB_X35_Y31_N2 +cycloneive_lcell_comb \ula_|video_|Decoder0~0 ( +// Equation(s): +// \ula_|video_|Decoder0~0_combout = (\ula_|video_|vga_hc [1] & (\ula_|video_|vga_hc [3] & (\ula_|video_|vga_hc [2] & \ula_|video_|vga_hc [0]))) + + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|vga_hc [3]), + .datac(\ula_|video_|vga_hc [2]), + .datad(\ula_|video_|vga_hc [0]), + .cin(gnd), + .combout(\ula_|video_|Decoder0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Decoder0~0 .lut_mask = 16'h8000; +defparam \ula_|video_|Decoder0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y32_N23 dffeas \ula_|video_|attr[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -58305,24 +57945,24 @@ defparam \ula_|video_|attr[7] .is_wysiwyg = "true"; defparam \ula_|video_|attr[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y33_N22 +// Location: LCCOMB_X35_Y31_N0 cycloneive_lcell_comb \ula_|video_|frame[0]~12 ( // Equation(s): -// \ula_|video_|frame[0]~12_combout = \ula_|video_|Equal3~1_combout $ (\ula_|video_|frame [0]) +// \ula_|video_|frame[0]~12_combout = \ula_|video_|frame [0] $ (\ula_|video_|Equal3~1_combout ) - .dataa(\ula_|video_|Equal3~1_combout ), + .dataa(gnd), .datab(gnd), .datac(\ula_|video_|frame [0]), - .datad(gnd), + .datad(\ula_|video_|Equal3~1_combout ), .cin(gnd), .combout(\ula_|video_|frame[0]~12_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|frame[0]~12 .lut_mask = 16'h5A5A; +defparam \ula_|video_|frame[0]~12 .lut_mask = 16'h0FF0; defparam \ula_|video_|frame[0]~12 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X34_Y33_N23 +// Location: FF_X35_Y31_N1 dffeas \ula_|video_|frame[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|frame[0]~12_combout ), @@ -58341,7 +57981,7 @@ defparam \ula_|video_|frame[0] .is_wysiwyg = "true"; defparam \ula_|video_|frame[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X35_Y33_N24 +// Location: LCCOMB_X35_Y32_N14 cycloneive_lcell_comb \ula_|video_|frame[1]~4 ( // Equation(s): // \ula_|video_|frame[1]~4_combout = (\ula_|video_|frame [0] & (\ula_|video_|frame [1] $ (VCC))) # (!\ula_|video_|frame [0] & (\ula_|video_|frame [1] & VCC)) @@ -58359,7 +57999,7 @@ defparam \ula_|video_|frame[1]~4 .lut_mask = 16'h6688; defparam \ula_|video_|frame[1]~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X35_Y33_N25 +// Location: FF_X35_Y32_N15 dffeas \ula_|video_|frame[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|frame[1]~4_combout ), @@ -58378,25 +58018,25 @@ defparam \ula_|video_|frame[1] .is_wysiwyg = "true"; defparam \ula_|video_|frame[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X35_Y33_N26 +// Location: LCCOMB_X35_Y32_N16 cycloneive_lcell_comb \ula_|video_|frame[2]~6 ( // Equation(s): // \ula_|video_|frame[2]~6_combout = (\ula_|video_|frame [2] & (!\ula_|video_|frame[1]~5 )) # (!\ula_|video_|frame [2] & ((\ula_|video_|frame[1]~5 ) # (GND))) // \ula_|video_|frame[2]~7 = CARRY((!\ula_|video_|frame[1]~5 ) # (!\ula_|video_|frame [2])) - .dataa(\ula_|video_|frame [2]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|video_|frame [2]), .datac(gnd), .datad(vcc), .cin(\ula_|video_|frame[1]~5 ), .combout(\ula_|video_|frame[2]~6_combout ), .cout(\ula_|video_|frame[2]~7 )); // synopsys translate_off -defparam \ula_|video_|frame[2]~6 .lut_mask = 16'h5A5F; +defparam \ula_|video_|frame[2]~6 .lut_mask = 16'h3C3F; defparam \ula_|video_|frame[2]~6 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X35_Y33_N27 +// Location: FF_X35_Y32_N17 dffeas \ula_|video_|frame[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|frame[2]~6_combout ), @@ -58415,7 +58055,7 @@ defparam \ula_|video_|frame[2] .is_wysiwyg = "true"; defparam \ula_|video_|frame[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X35_Y33_N28 +// Location: LCCOMB_X35_Y32_N18 cycloneive_lcell_comb \ula_|video_|frame[3]~8 ( // Equation(s): // \ula_|video_|frame[3]~8_combout = (\ula_|video_|frame [3] & (\ula_|video_|frame[2]~7 $ (GND))) # (!\ula_|video_|frame [3] & (!\ula_|video_|frame[2]~7 & VCC)) @@ -58433,7 +58073,7 @@ defparam \ula_|video_|frame[3]~8 .lut_mask = 16'hC30C; defparam \ula_|video_|frame[3]~8 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X35_Y33_N29 +// Location: FF_X35_Y32_N19 dffeas \ula_|video_|frame[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|frame[3]~8_combout ), @@ -58452,27 +58092,44 @@ defparam \ula_|video_|frame[3] .is_wysiwyg = "true"; defparam \ula_|video_|frame[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X35_Y33_N30 +// Location: LCCOMB_X35_Y32_N20 cycloneive_lcell_comb \ula_|video_|frame[4]~10 ( // Equation(s): -// \ula_|video_|frame[4]~10_combout = \ula_|video_|frame [4] $ (\ula_|video_|frame[3]~9 ) +// \ula_|video_|frame[4]~10_combout = \ula_|video_|frame[3]~9 $ (\ula_|video_|frame [4]) - .dataa(\ula_|video_|frame [4]), + .dataa(gnd), .datab(gnd), .datac(gnd), - .datad(gnd), + .datad(\ula_|video_|frame [4]), .cin(\ula_|video_|frame[3]~9 ), .combout(\ula_|video_|frame[4]~10_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|frame[4]~10 .lut_mask = 16'h5A5A; +defparam \ula_|video_|frame[4]~10 .lut_mask = 16'h0FF0; defparam \ula_|video_|frame[4]~10 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X35_Y33_N31 +// Location: LCCOMB_X37_Y32_N0 +cycloneive_lcell_comb \ula_|video_|frame[4]~feeder ( +// Equation(s): +// \ula_|video_|frame[4]~feeder_combout = \ula_|video_|frame[4]~10_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|frame[4]~10_combout ), + .cin(gnd), + .combout(\ula_|video_|frame[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|frame[4]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|frame[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y32_N1 dffeas \ula_|video_|frame[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|frame[4]~10_combout ), + .d(\ula_|video_|frame[4]~feeder_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -58488,7 +58145,7 @@ defparam \ula_|video_|frame[4] .is_wysiwyg = "true"; defparam \ula_|video_|frame[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N4 +// Location: LCCOMB_X37_Y32_N22 cycloneive_lcell_comb \ula_|video_|inverted ( // Equation(s): // \ula_|video_|inverted~combout = (\ula_|video_|attr [7] & \ula_|video_|frame [4]) @@ -58505,41 +58162,41 @@ defparam \ula_|video_|inverted .lut_mask = 16'hF000; defparam \ula_|video_|inverted .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N12 +// Location: LCCOMB_X38_Y32_N4 cycloneive_lcell_comb \ula_|video_|bits_prefetch[6]~feeder ( // Equation(s): // \ula_|video_|bits_prefetch[6]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 ), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 ), + .datad(gnd), .cin(gnd), .combout(\ula_|video_|bits_prefetch[6]~feeder_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|bits_prefetch[6]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|bits_prefetch[6]~feeder .lut_mask = 16'hF0F0; defparam \ula_|video_|bits_prefetch[6]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y31_N8 +// Location: LCCOMB_X35_Y31_N10 cycloneive_lcell_comb \ula_|video_|Decoder0~2 ( // Equation(s): -// \ula_|video_|Decoder0~2_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [1] & !\ula_|video_|vga_hc [0]))) +// \ula_|video_|Decoder0~2_combout = (!\ula_|video_|vga_hc [1] & (\ula_|video_|vga_hc [3] & (\ula_|video_|vga_hc [2] & !\ula_|video_|vga_hc [0]))) - .dataa(\ula_|video_|vga_hc [2]), + .dataa(\ula_|video_|vga_hc [1]), .datab(\ula_|video_|vga_hc [3]), - .datac(\ula_|video_|vga_hc [1]), + .datac(\ula_|video_|vga_hc [2]), .datad(\ula_|video_|vga_hc [0]), .cin(gnd), .combout(\ula_|video_|Decoder0~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Decoder0~2 .lut_mask = 16'h0008; +defparam \ula_|video_|Decoder0~2 .lut_mask = 16'h0040; defparam \ula_|video_|Decoder0~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N13 +// Location: FF_X38_Y32_N5 dffeas \ula_|video_|bits_prefetch[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits_prefetch[6]~feeder_combout ), @@ -58558,32 +58215,15 @@ defparam \ula_|video_|bits_prefetch[6] .is_wysiwyg = "true"; defparam \ula_|video_|bits_prefetch[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N6 -cycloneive_lcell_comb \ula_|video_|bits[6]~feeder ( -// Equation(s): -// \ula_|video_|bits[6]~feeder_combout = \ula_|video_|bits_prefetch [6] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|bits_prefetch [6]), - .cin(gnd), - .combout(\ula_|video_|bits[6]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|bits[6]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|bits[6]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y33_N7 +// Location: FF_X37_Y32_N27 dffeas \ula_|video_|bits[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|bits[6]~feeder_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\ula_|video_|bits_prefetch [6]), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), + .sload(vcc), .ena(\ula_|video_|Decoder0~0_combout ), .devclrn(devclrn), .devpor(devpor), @@ -58594,7 +58234,7 @@ defparam \ula_|video_|bits[6] .is_wysiwyg = "true"; defparam \ula_|video_|bits[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N22 +// Location: LCCOMB_X38_Y32_N10 cycloneive_lcell_comb \ula_|video_|bits_prefetch[4]~feeder ( // Equation(s): // \ula_|video_|bits_prefetch[4]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 @@ -58611,7 +58251,7 @@ defparam \ula_|video_|bits_prefetch[4]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits_prefetch[4]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N23 +// Location: FF_X38_Y32_N11 dffeas \ula_|video_|bits_prefetch[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits_prefetch[4]~feeder_combout ), @@ -58630,7 +58270,7 @@ defparam \ula_|video_|bits_prefetch[4] .is_wysiwyg = "true"; defparam \ula_|video_|bits_prefetch[4] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y33_N23 +// Location: FF_X37_Y32_N9 dffeas \ula_|video_|bits[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -58649,7 +58289,7 @@ defparam \ula_|video_|bits[4] .is_wysiwyg = "true"; defparam \ula_|video_|bits[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N18 +// Location: LCCOMB_X38_Y32_N26 cycloneive_lcell_comb \ula_|video_|bits_prefetch[5]~feeder ( // Equation(s): // \ula_|video_|bits_prefetch[5]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 @@ -58666,7 +58306,7 @@ defparam \ula_|video_|bits_prefetch[5]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits_prefetch[5]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N19 +// Location: FF_X38_Y32_N27 dffeas \ula_|video_|bits_prefetch[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits_prefetch[5]~feeder_combout ), @@ -58685,7 +58325,7 @@ defparam \ula_|video_|bits_prefetch[5] .is_wysiwyg = "true"; defparam \ula_|video_|bits_prefetch[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N18 +// Location: LCCOMB_X37_Y32_N12 cycloneive_lcell_comb \ula_|video_|bits[5]~feeder ( // Equation(s): // \ula_|video_|bits[5]~feeder_combout = \ula_|video_|bits_prefetch [5] @@ -58702,7 +58342,7 @@ defparam \ula_|video_|bits[5]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits[5]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X36_Y33_N19 +// Location: FF_X37_Y32_N13 dffeas \ula_|video_|bits[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits[5]~feeder_combout ), @@ -58721,7 +58361,7 @@ defparam \ula_|video_|bits[5] .is_wysiwyg = "true"; defparam \ula_|video_|bits[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N0 +// Location: LCCOMB_X38_Y32_N12 cycloneive_lcell_comb \ula_|video_|bits_prefetch[7]~feeder ( // Equation(s): // \ula_|video_|bits_prefetch[7]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 @@ -58738,7 +58378,7 @@ defparam \ula_|video_|bits_prefetch[7]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits_prefetch[7]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N1 +// Location: FF_X38_Y32_N13 dffeas \ula_|video_|bits_prefetch[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits_prefetch[7]~feeder_combout ), @@ -58757,7 +58397,7 @@ defparam \ula_|video_|bits_prefetch[7] .is_wysiwyg = "true"; defparam \ula_|video_|bits_prefetch[7] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y33_N1 +// Location: FF_X37_Y32_N19 dffeas \ula_|video_|bits[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -58776,41 +58416,41 @@ defparam \ula_|video_|bits[7] .is_wysiwyg = "true"; defparam \ula_|video_|bits[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N0 +// Location: LCCOMB_X37_Y32_N18 cycloneive_lcell_comb \ula_|video_|Mux0~0 ( // Equation(s): -// \ula_|video_|Mux0~0_combout = (\ula_|video_|vga_hc [1] & (((\ula_|video_|vga_hc [2])))) # (!\ula_|video_|vga_hc [1] & ((\ula_|video_|vga_hc [2] & (\ula_|video_|bits [5])) # (!\ula_|video_|vga_hc [2] & ((\ula_|video_|bits [7]))))) +// \ula_|video_|Mux0~0_combout = (\ula_|video_|vga_hc [2] & ((\ula_|video_|bits [5]) # ((\ula_|video_|vga_hc [1])))) # (!\ula_|video_|vga_hc [2] & (((\ula_|video_|bits [7] & !\ula_|video_|vga_hc [1])))) .dataa(\ula_|video_|bits [5]), - .datab(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|vga_hc [2]), .datac(\ula_|video_|bits [7]), - .datad(\ula_|video_|vga_hc [2]), + .datad(\ula_|video_|vga_hc [1]), .cin(gnd), .combout(\ula_|video_|Mux0~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Mux0~0 .lut_mask = 16'hEE30; +defparam \ula_|video_|Mux0~0 .lut_mask = 16'hCCB8; defparam \ula_|video_|Mux0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N22 +// Location: LCCOMB_X37_Y32_N8 cycloneive_lcell_comb \ula_|video_|Mux0~1 ( // Equation(s): // \ula_|video_|Mux0~1_combout = (\ula_|video_|vga_hc [1] & ((\ula_|video_|Mux0~0_combout & ((\ula_|video_|bits [4]))) # (!\ula_|video_|Mux0~0_combout & (\ula_|video_|bits [6])))) # (!\ula_|video_|vga_hc [1] & (((\ula_|video_|Mux0~0_combout )))) - .dataa(\ula_|video_|bits [6]), - .datab(\ula_|video_|vga_hc [1]), + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|bits [6]), .datac(\ula_|video_|bits [4]), .datad(\ula_|video_|Mux0~0_combout ), .cin(gnd), .combout(\ula_|video_|Mux0~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Mux0~1 .lut_mask = 16'hF388; +defparam \ula_|video_|Mux0~1 .lut_mask = 16'hF588; defparam \ula_|video_|Mux0~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N16 +// Location: LCCOMB_X38_Y32_N16 cycloneive_lcell_comb \ula_|video_|bits_prefetch[2]~feeder ( // Equation(s): // \ula_|video_|bits_prefetch[2]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 @@ -58827,7 +58467,7 @@ defparam \ula_|video_|bits_prefetch[2]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits_prefetch[2]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N17 +// Location: FF_X38_Y32_N17 dffeas \ula_|video_|bits_prefetch[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits_prefetch[2]~feeder_combout ), @@ -58846,7 +58486,7 @@ defparam \ula_|video_|bits_prefetch[2] .is_wysiwyg = "true"; defparam \ula_|video_|bits_prefetch[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N12 +// Location: LCCOMB_X37_Y32_N30 cycloneive_lcell_comb \ula_|video_|bits[2]~feeder ( // Equation(s): // \ula_|video_|bits[2]~feeder_combout = \ula_|video_|bits_prefetch [2] @@ -58863,7 +58503,7 @@ defparam \ula_|video_|bits[2]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits[2]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X36_Y33_N13 +// Location: FF_X37_Y32_N31 dffeas \ula_|video_|bits[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits[2]~feeder_combout ), @@ -58882,7 +58522,7 @@ defparam \ula_|video_|bits[2] .is_wysiwyg = "true"; defparam \ula_|video_|bits[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N14 +// Location: LCCOMB_X38_Y32_N6 cycloneive_lcell_comb \ula_|video_|bits_prefetch[0]~feeder ( // Equation(s): // \ula_|video_|bits_prefetch[0]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 @@ -58899,7 +58539,7 @@ defparam \ula_|video_|bits_prefetch[0]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits_prefetch[0]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N15 +// Location: FF_X38_Y32_N7 dffeas \ula_|video_|bits_prefetch[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits_prefetch[0]~feeder_combout ), @@ -58918,7 +58558,7 @@ defparam \ula_|video_|bits_prefetch[0] .is_wysiwyg = "true"; defparam \ula_|video_|bits_prefetch[0] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y33_N3 +// Location: FF_X37_Y32_N25 dffeas \ula_|video_|bits[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -58937,7 +58577,7 @@ defparam \ula_|video_|bits[0] .is_wysiwyg = "true"; defparam \ula_|video_|bits[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N6 +// Location: LCCOMB_X38_Y32_N2 cycloneive_lcell_comb \ula_|video_|bits_prefetch[1]~feeder ( // Equation(s): // \ula_|video_|bits_prefetch[1]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 @@ -58954,7 +58594,7 @@ defparam \ula_|video_|bits_prefetch[1]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits_prefetch[1]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N7 +// Location: FF_X38_Y32_N3 dffeas \ula_|video_|bits_prefetch[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits_prefetch[1]~feeder_combout ), @@ -58973,7 +58613,7 @@ defparam \ula_|video_|bits_prefetch[1] .is_wysiwyg = "true"; defparam \ula_|video_|bits_prefetch[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N26 +// Location: LCCOMB_X37_Y32_N28 cycloneive_lcell_comb \ula_|video_|bits[1]~feeder ( // Equation(s): // \ula_|video_|bits[1]~feeder_combout = \ula_|video_|bits_prefetch [1] @@ -58990,7 +58630,7 @@ defparam \ula_|video_|bits[1]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits[1]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X36_Y33_N27 +// Location: FF_X37_Y32_N29 dffeas \ula_|video_|bits[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits[1]~feeder_combout ), @@ -59009,7 +58649,7 @@ defparam \ula_|video_|bits[1] .is_wysiwyg = "true"; defparam \ula_|video_|bits[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N4 +// Location: LCCOMB_X38_Y32_N20 cycloneive_lcell_comb \ula_|video_|bits_prefetch[3]~feeder ( // Equation(s): // \ula_|video_|bits_prefetch[3]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 @@ -59026,7 +58666,7 @@ defparam \ula_|video_|bits_prefetch[3]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits_prefetch[3]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N5 +// Location: FF_X38_Y32_N21 dffeas \ula_|video_|bits_prefetch[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits_prefetch[3]~feeder_combout ), @@ -59045,7 +58685,7 @@ defparam \ula_|video_|bits_prefetch[3] .is_wysiwyg = "true"; defparam \ula_|video_|bits_prefetch[3] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y33_N25 +// Location: FF_X37_Y32_N7 dffeas \ula_|video_|bits[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -59064,109 +58704,219 @@ defparam \ula_|video_|bits[3] .is_wysiwyg = "true"; defparam \ula_|video_|bits[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N24 +// Location: LCCOMB_X37_Y32_N6 cycloneive_lcell_comb \ula_|video_|Mux0~2 ( // Equation(s): // \ula_|video_|Mux0~2_combout = (\ula_|video_|vga_hc [1] & (((\ula_|video_|vga_hc [2])))) # (!\ula_|video_|vga_hc [1] & ((\ula_|video_|vga_hc [2] & (\ula_|video_|bits [1])) # (!\ula_|video_|vga_hc [2] & ((\ula_|video_|bits [3]))))) - .dataa(\ula_|video_|bits [1]), - .datab(\ula_|video_|vga_hc [1]), + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|bits [1]), .datac(\ula_|video_|bits [3]), .datad(\ula_|video_|vga_hc [2]), .cin(gnd), .combout(\ula_|video_|Mux0~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Mux0~2 .lut_mask = 16'hEE30; +defparam \ula_|video_|Mux0~2 .lut_mask = 16'hEE50; defparam \ula_|video_|Mux0~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N2 +// Location: LCCOMB_X37_Y32_N24 cycloneive_lcell_comb \ula_|video_|Mux0~3 ( // Equation(s): // \ula_|video_|Mux0~3_combout = (\ula_|video_|vga_hc [1] & ((\ula_|video_|Mux0~2_combout & ((\ula_|video_|bits [0]))) # (!\ula_|video_|Mux0~2_combout & (\ula_|video_|bits [2])))) # (!\ula_|video_|vga_hc [1] & (((\ula_|video_|Mux0~2_combout )))) - .dataa(\ula_|video_|bits [2]), - .datab(\ula_|video_|vga_hc [1]), + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|bits [2]), .datac(\ula_|video_|bits [0]), .datad(\ula_|video_|Mux0~2_combout ), .cin(gnd), .combout(\ula_|video_|Mux0~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Mux0~3 .lut_mask = 16'hF388; +defparam \ula_|video_|Mux0~3 .lut_mask = 16'hF588; defparam \ula_|video_|Mux0~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N10 +// Location: LCCOMB_X37_Y32_N20 cycloneive_lcell_comb \ula_|video_|cindex[1]~0 ( // Equation(s): // \ula_|video_|cindex[1]~0_combout = \ula_|video_|inverted~combout $ (((\ula_|video_|vga_hc [3] & ((\ula_|video_|Mux0~3_combout ))) # (!\ula_|video_|vga_hc [3] & (\ula_|video_|Mux0~1_combout )))) - .dataa(\ula_|video_|vga_hc [3]), - .datab(\ula_|video_|inverted~combout ), + .dataa(\ula_|video_|inverted~combout ), + .datab(\ula_|video_|vga_hc [3]), .datac(\ula_|video_|Mux0~1_combout ), .datad(\ula_|video_|Mux0~3_combout ), .cin(gnd), .combout(\ula_|video_|cindex[1]~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|cindex[1]~0 .lut_mask = 16'h369C; +defparam \ula_|video_|cindex[1]~0 .lut_mask = 16'h569A; defparam \ula_|video_|cindex[1]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y33_N12 +// Location: LCCOMB_X38_Y32_N14 +cycloneive_lcell_comb \ula_|video_|attr_prefetch[4]~feeder ( +// Equation(s): +// \ula_|video_|attr_prefetch[4]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ula_|video_|attr_prefetch[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|attr_prefetch[4]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|attr_prefetch[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X38_Y32_N15 +dffeas \ula_|video_|attr_prefetch[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|attr_prefetch[4]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|Decoder0~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|attr_prefetch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|attr_prefetch[4] .is_wysiwyg = "true"; +defparam \ula_|video_|attr_prefetch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X36_Y32_N17 +dffeas \ula_|video_|attr[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|attr_prefetch [4]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|attr [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|attr[4] .is_wysiwyg = "true"; +defparam \ula_|video_|attr[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y32_N28 +cycloneive_lcell_comb \ula_|video_|attr_prefetch[1]~feeder ( +// Equation(s): +// \ula_|video_|attr_prefetch[1]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ula_|video_|attr_prefetch[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|attr_prefetch[1]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|attr_prefetch[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X38_Y32_N29 +dffeas \ula_|video_|attr_prefetch[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|attr_prefetch[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|Decoder0~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|attr_prefetch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|attr_prefetch[1] .is_wysiwyg = "true"; +defparam \ula_|video_|attr_prefetch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X36_Y32_N7 +dffeas \ula_|video_|attr[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|attr_prefetch [1]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|attr [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|attr[1] .is_wysiwyg = "true"; +defparam \ula_|video_|attr[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y32_N16 cycloneive_lcell_comb \ula_|video_|cindex[1]~1 ( // Equation(s): -// \ula_|video_|cindex[1]~1_combout = (\ula_|video_|cindex[1]~0_combout & (\ula_|video_|attr [1])) # (!\ula_|video_|cindex[1]~0_combout & ((\ula_|video_|attr [4]))) +// \ula_|video_|cindex[1]~1_combout = (\ula_|video_|cindex[1]~0_combout & ((\ula_|video_|attr [1]))) # (!\ula_|video_|cindex[1]~0_combout & (\ula_|video_|attr [4])) - .dataa(\ula_|video_|attr [1]), + .dataa(\ula_|video_|cindex[1]~0_combout ), .datab(gnd), .datac(\ula_|video_|attr [4]), - .datad(\ula_|video_|cindex[1]~0_combout ), + .datad(\ula_|video_|attr [1]), .cin(gnd), .combout(\ula_|video_|cindex[1]~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|cindex[1]~1 .lut_mask = 16'hAAF0; +defparam \ula_|video_|cindex[1]~1 .lut_mask = 16'hFA50; defparam \ula_|video_|cindex[1]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y33_N24 +// Location: LCCOMB_X36_Y32_N26 cycloneive_lcell_comb \ula_|video_|VGA_R[0]~0 ( // Equation(s): // \ula_|video_|VGA_R[0]~0_combout = (\ula_|video_|disp_enable~1_combout & ((\ula_|video_|screen_en~1_combout & ((\ula_|video_|cindex[1]~1_combout ))) # (!\ula_|video_|screen_en~1_combout & (\ula_|border [1])))) - .dataa(\ula_|video_|disp_enable~1_combout ), - .datab(\ula_|border [1]), - .datac(\ula_|video_|screen_en~1_combout ), + .dataa(\ula_|border [1]), + .datab(\ula_|video_|screen_en~1_combout ), + .datac(\ula_|video_|disp_enable~1_combout ), .datad(\ula_|video_|cindex[1]~1_combout ), .cin(gnd), .combout(\ula_|video_|VGA_R[0]~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|VGA_R[0]~0 .lut_mask = 16'hA808; +defparam \ula_|video_|VGA_R[0]~0 .lut_mask = 16'hE020; defparam \ula_|video_|VGA_R[0]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N26 +// Location: LCCOMB_X38_Y32_N18 cycloneive_lcell_comb \ula_|video_|attr_prefetch[6]~feeder ( // Equation(s): // \ula_|video_|attr_prefetch[6]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 ), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 ), + .datad(gnd), .cin(gnd), .combout(\ula_|video_|attr_prefetch[6]~feeder_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|attr_prefetch[6]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|attr_prefetch[6]~feeder .lut_mask = 16'hF0F0; defparam \ula_|video_|attr_prefetch[6]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N27 +// Location: FF_X38_Y32_N19 dffeas \ula_|video_|attr_prefetch[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr_prefetch[6]~feeder_combout ), @@ -59185,7 +58935,7 @@ defparam \ula_|video_|attr_prefetch[6] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[6] .power_up = "low"; // synopsys translate_on -// Location: FF_X38_Y33_N1 +// Location: FF_X36_Y32_N9 dffeas \ula_|video_|attr[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -59204,7 +58954,7 @@ defparam \ula_|video_|attr[6] .is_wysiwyg = "true"; defparam \ula_|video_|attr[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X38_Y33_N0 +// Location: LCCOMB_X36_Y32_N8 cycloneive_lcell_comb \ula_|video_|VGA_B[1]~0 ( // Equation(s): // \ula_|video_|VGA_B[1]~0_combout = (!\ula_|video_|LessThan2~1_combout & (\ula_|video_|LessThan3~0_combout & (\ula_|video_|attr [6] & \ula_|video_|disp_enable~0_combout ))) @@ -59221,28 +58971,28 @@ defparam \ula_|video_|VGA_B[1]~0 .lut_mask = 16'h4000; defparam \ula_|video_|VGA_B[1]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y33_N2 +// Location: LCCOMB_X36_Y32_N30 cycloneive_lcell_comb \ula_|video_|VGA_R[1]~1 ( // Equation(s): // \ula_|video_|VGA_R[1]~1_combout = (\ula_|video_|screen_en~1_combout & (\ula_|video_|VGA_B[1]~0_combout & \ula_|video_|cindex[1]~1_combout )) .dataa(\ula_|video_|screen_en~1_combout ), - .datab(gnd), - .datac(\ula_|video_|VGA_B[1]~0_combout ), + .datab(\ula_|video_|VGA_B[1]~0_combout ), + .datac(gnd), .datad(\ula_|video_|cindex[1]~1_combout ), .cin(gnd), .combout(\ula_|video_|VGA_R[1]~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|VGA_R[1]~1 .lut_mask = 16'hA000; +defparam \ula_|video_|VGA_R[1]~1 .lut_mask = 16'h8800; defparam \ula_|video_|VGA_R[1]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y12_N17 +// Location: FF_X31_Y10_N27 dffeas \ula_|border[2] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), - .asdata(\D[2]~46_combout ), + .asdata(\D[2]~39_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), @@ -59257,62 +59007,7 @@ defparam \ula_|border[2] .is_wysiwyg = "true"; defparam \ula_|border[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N8 -cycloneive_lcell_comb \ula_|video_|attr_prefetch[2]~feeder ( -// Equation(s): -// \ula_|video_|attr_prefetch[2]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|attr_prefetch[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|attr_prefetch[2]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|attr_prefetch[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y33_N9 -dffeas \ula_|video_|attr_prefetch[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|attr_prefetch[2]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|attr_prefetch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|attr_prefetch[2] .is_wysiwyg = "true"; -defparam \ula_|video_|attr_prefetch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X36_Y33_N21 -dffeas \ula_|video_|attr[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|attr_prefetch [2]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|Decoder0~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|attr [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|attr[2] .is_wysiwyg = "true"; -defparam \ula_|video_|attr[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y33_N30 +// Location: LCCOMB_X38_Y32_N22 cycloneive_lcell_comb \ula_|video_|attr_prefetch[5]~feeder ( // Equation(s): // \ula_|video_|attr_prefetch[5]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 @@ -59329,7 +59024,7 @@ defparam \ula_|video_|attr_prefetch[5]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|attr_prefetch[5]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N31 +// Location: FF_X38_Y32_N23 dffeas \ula_|video_|attr_prefetch[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr_prefetch[5]~feeder_combout ), @@ -59348,7 +59043,7 @@ defparam \ula_|video_|attr_prefetch[5] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[5] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y33_N15 +// Location: FF_X36_Y32_N21 dffeas \ula_|video_|attr[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -59367,24 +59062,79 @@ defparam \ula_|video_|attr[5] .is_wysiwyg = "true"; defparam \ula_|video_|attr[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N14 -cycloneive_lcell_comb \ula_|video_|cindex[2]~2 ( +// Location: LCCOMB_X38_Y32_N0 +cycloneive_lcell_comb \ula_|video_|attr_prefetch[2]~feeder ( // Equation(s): -// \ula_|video_|cindex[2]~2_combout = (\ula_|video_|cindex[1]~0_combout & (\ula_|video_|attr [2])) # (!\ula_|video_|cindex[1]~0_combout & ((\ula_|video_|attr [5]))) +// \ula_|video_|attr_prefetch[2]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 .dataa(gnd), - .datab(\ula_|video_|attr [2]), + .datab(gnd), + .datac(gnd), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ula_|video_|attr_prefetch[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|attr_prefetch[2]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|attr_prefetch[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X38_Y32_N1 +dffeas \ula_|video_|attr_prefetch[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|attr_prefetch[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|Decoder0~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|attr_prefetch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|attr_prefetch[2] .is_wysiwyg = "true"; +defparam \ula_|video_|attr_prefetch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X36_Y32_N19 +dffeas \ula_|video_|attr[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|attr_prefetch [2]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|attr [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|attr[2] .is_wysiwyg = "true"; +defparam \ula_|video_|attr[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y32_N20 +cycloneive_lcell_comb \ula_|video_|cindex[2]~2 ( +// Equation(s): +// \ula_|video_|cindex[2]~2_combout = (\ula_|video_|cindex[1]~0_combout & ((\ula_|video_|attr [2]))) # (!\ula_|video_|cindex[1]~0_combout & (\ula_|video_|attr [5])) + + .dataa(\ula_|video_|cindex[1]~0_combout ), + .datab(gnd), .datac(\ula_|video_|attr [5]), - .datad(\ula_|video_|cindex[1]~0_combout ), + .datad(\ula_|video_|attr [2]), .cin(gnd), .combout(\ula_|video_|cindex[2]~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|cindex[2]~2 .lut_mask = 16'hCCF0; +defparam \ula_|video_|cindex[2]~2 .lut_mask = 16'hFA50; defparam \ula_|video_|cindex[2]~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y33_N26 +// Location: LCCOMB_X36_Y32_N22 cycloneive_lcell_comb \ula_|video_|VGA_G[0]~0 ( // Equation(s): // \ula_|video_|VGA_G[0]~0_combout = (\ula_|video_|disp_enable~1_combout & ((\ula_|video_|screen_en~1_combout & ((\ula_|video_|cindex[2]~2_combout ))) # (!\ula_|video_|screen_en~1_combout & (\ula_|border [2])))) @@ -59401,15 +59151,15 @@ defparam \ula_|video_|VGA_G[0]~0 .lut_mask = 16'hE020; defparam \ula_|video_|VGA_G[0]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N20 +// Location: LCCOMB_X36_Y32_N18 cycloneive_lcell_comb \ula_|video_|VGA_G[1]~1 ( // Equation(s): -// \ula_|video_|VGA_G[1]~1_combout = (\ula_|video_|VGA_B[1]~0_combout & (\ula_|video_|cindex[2]~2_combout & \ula_|video_|screen_en~1_combout )) +// \ula_|video_|VGA_G[1]~1_combout = (\ula_|video_|VGA_B[1]~0_combout & (\ula_|video_|screen_en~1_combout & \ula_|video_|cindex[2]~2_combout )) .dataa(\ula_|video_|VGA_B[1]~0_combout ), - .datab(\ula_|video_|cindex[2]~2_combout ), + .datab(\ula_|video_|screen_en~1_combout ), .datac(gnd), - .datad(\ula_|video_|screen_en~1_combout ), + .datad(\ula_|video_|cindex[2]~2_combout ), .cin(gnd), .combout(\ula_|video_|VGA_G[1]~1_combout ), .cout()); @@ -59418,11 +59168,11 @@ defparam \ula_|video_|VGA_G[1]~1 .lut_mask = 16'h8800; defparam \ula_|video_|VGA_G[1]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y22_N1 +// Location: FF_X23_Y14_N19 dffeas \ula_|border[0] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), - .asdata(\D[0]~58_combout ), + .asdata(\D[0]~46_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), @@ -59437,7 +59187,7 @@ defparam \ula_|border[0] .is_wysiwyg = "true"; defparam \ula_|border[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N20 +// Location: LCCOMB_X38_Y32_N24 cycloneive_lcell_comb \ula_|video_|attr_prefetch[0]~feeder ( // Equation(s): // \ula_|video_|attr_prefetch[0]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 @@ -59454,7 +59204,7 @@ defparam \ula_|video_|attr_prefetch[0]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|attr_prefetch[0]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N21 +// Location: FF_X38_Y32_N25 dffeas \ula_|video_|attr_prefetch[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr_prefetch[0]~feeder_combout ), @@ -59473,7 +59223,7 @@ defparam \ula_|video_|attr_prefetch[0] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X37_Y33_N28 +// Location: LCCOMB_X37_Y32_N10 cycloneive_lcell_comb \ula_|video_|attr[0]~feeder ( // Equation(s): // \ula_|video_|attr[0]~feeder_combout = \ula_|video_|attr_prefetch [0] @@ -59490,7 +59240,7 @@ defparam \ula_|video_|attr[0]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|attr[0]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X37_Y33_N29 +// Location: FF_X37_Y32_N11 dffeas \ula_|video_|attr[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr[0]~feeder_combout ), @@ -59509,7 +59259,7 @@ defparam \ula_|video_|attr[0] .is_wysiwyg = "true"; defparam \ula_|video_|attr[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N2 +// Location: LCCOMB_X38_Y32_N30 cycloneive_lcell_comb \ula_|video_|attr_prefetch[3]~feeder ( // Equation(s): // \ula_|video_|attr_prefetch[3]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 @@ -59526,7 +59276,7 @@ defparam \ula_|video_|attr_prefetch[3]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|attr_prefetch[3]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N3 +// Location: FF_X38_Y32_N31 dffeas \ula_|video_|attr_prefetch[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr_prefetch[3]~feeder_combout ), @@ -59545,7 +59295,7 @@ defparam \ula_|video_|attr_prefetch[3] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[3] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y33_N29 +// Location: FF_X37_Y32_N17 dffeas \ula_|video_|attr[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -59564,48 +59314,48 @@ defparam \ula_|video_|attr[3] .is_wysiwyg = "true"; defparam \ula_|video_|attr[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N28 +// Location: LCCOMB_X37_Y32_N16 cycloneive_lcell_comb \ula_|video_|cindex[0]~3 ( // Equation(s): // \ula_|video_|cindex[0]~3_combout = (\ula_|video_|cindex[1]~0_combout & (\ula_|video_|attr [0])) # (!\ula_|video_|cindex[1]~0_combout & ((\ula_|video_|attr [3]))) - .dataa(gnd), - .datab(\ula_|video_|attr [0]), + .dataa(\ula_|video_|attr [0]), + .datab(gnd), .datac(\ula_|video_|attr [3]), .datad(\ula_|video_|cindex[1]~0_combout ), .cin(gnd), .combout(\ula_|video_|cindex[0]~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|cindex[0]~3 .lut_mask = 16'hCCF0; +defparam \ula_|video_|cindex[0]~3 .lut_mask = 16'hAAF0; defparam \ula_|video_|cindex[0]~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y33_N30 +// Location: LCCOMB_X37_Y32_N14 cycloneive_lcell_comb \ula_|video_|VGA_B[0]~1 ( // Equation(s): // \ula_|video_|VGA_B[0]~1_combout = (\ula_|video_|disp_enable~1_combout & ((\ula_|video_|screen_en~1_combout & ((\ula_|video_|cindex[0]~3_combout ))) # (!\ula_|video_|screen_en~1_combout & (\ula_|border [0])))) - .dataa(\ula_|video_|disp_enable~1_combout ), + .dataa(\ula_|video_|screen_en~1_combout ), .datab(\ula_|border [0]), - .datac(\ula_|video_|screen_en~1_combout ), + .datac(\ula_|video_|disp_enable~1_combout ), .datad(\ula_|video_|cindex[0]~3_combout ), .cin(gnd), .combout(\ula_|video_|VGA_B[0]~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|VGA_B[0]~1 .lut_mask = 16'hA808; +defparam \ula_|video_|VGA_B[0]~1 .lut_mask = 16'hE040; defparam \ula_|video_|VGA_B[0]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y33_N0 +// Location: LCCOMB_X37_Y32_N4 cycloneive_lcell_comb \ula_|video_|VGA_B[1]~2 ( // Equation(s): -// \ula_|video_|VGA_B[1]~2_combout = (\ula_|video_|screen_en~1_combout & (\ula_|video_|VGA_B[1]~0_combout & \ula_|video_|cindex[0]~3_combout )) +// \ula_|video_|VGA_B[1]~2_combout = (\ula_|video_|VGA_B[1]~0_combout & (\ula_|video_|screen_en~1_combout & \ula_|video_|cindex[0]~3_combout )) - .dataa(\ula_|video_|screen_en~1_combout ), + .dataa(\ula_|video_|VGA_B[1]~0_combout ), .datab(gnd), - .datac(\ula_|video_|VGA_B[1]~0_combout ), + .datac(\ula_|video_|screen_en~1_combout ), .datad(\ula_|video_|cindex[0]~3_combout ), .cin(gnd), .combout(\ula_|video_|VGA_B[1]~2_combout ), @@ -59615,24 +59365,24 @@ defparam \ula_|video_|VGA_B[1]~2 .lut_mask = 16'hA000; defparam \ula_|video_|VGA_B[1]~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y33_N26 +// Location: LCCOMB_X35_Y31_N22 cycloneive_lcell_comb \ula_|video_|Equal0~2 ( // Equation(s): -// \ula_|video_|Equal0~2_combout = (\ula_|video_|vga_hc [6] & (!\ula_|video_|vga_hc [9] & !\ula_|video_|vga_hc [8])) +// \ula_|video_|Equal0~2_combout = (!\ula_|video_|vga_hc [8] & (\ula_|video_|vga_hc [6] & !\ula_|video_|vga_hc [9])) - .dataa(\ula_|video_|vga_hc [6]), - .datab(\ula_|video_|vga_hc [9]), - .datac(gnd), - .datad(\ula_|video_|vga_hc [8]), + .dataa(gnd), + .datab(\ula_|video_|vga_hc [8]), + .datac(\ula_|video_|vga_hc [6]), + .datad(\ula_|video_|vga_hc [9]), .cin(gnd), .combout(\ula_|video_|Equal0~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Equal0~2 .lut_mask = 16'h0022; +defparam \ula_|video_|Equal0~2 .lut_mask = 16'h0030; defparam \ula_|video_|Equal0~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X37_Y33_N7 +// Location: FF_X35_Y31_N21 dffeas \ula_|video_|VGA_HS~_Duplicate_1 ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|Selector0~0_combout ), @@ -59651,21 +59401,21 @@ defparam \ula_|video_|VGA_HS~_Duplicate_1 .is_wysiwyg = "true"; defparam \ula_|video_|VGA_HS~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X37_Y33_N6 +// Location: LCCOMB_X35_Y31_N20 cycloneive_lcell_comb \ula_|video_|Selector0~0 ( // Equation(s): -// \ula_|video_|Selector0~0_combout = (\ula_|video_|Equal0~2_combout & ((\ula_|video_|Equal0~1_combout ) # ((\ula_|video_|Equal1~0_combout & \ula_|video_|VGA_HS~_Duplicate_1_q )))) # (!\ula_|video_|Equal0~2_combout & (\ula_|video_|Equal1~0_combout & -// (\ula_|video_|VGA_HS~_Duplicate_1_q ))) +// \ula_|video_|Selector0~0_combout = (\ula_|video_|Equal0~2_combout & ((\ula_|video_|Equal0~1_combout ) # ((\ula_|video_|VGA_HS~_Duplicate_1_q & \ula_|video_|Equal1~0_combout )))) # (!\ula_|video_|Equal0~2_combout & (((\ula_|video_|VGA_HS~_Duplicate_1_q +// & \ula_|video_|Equal1~0_combout )))) .dataa(\ula_|video_|Equal0~2_combout ), - .datab(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Equal0~1_combout ), .datac(\ula_|video_|VGA_HS~_Duplicate_1_q ), - .datad(\ula_|video_|Equal0~1_combout ), + .datad(\ula_|video_|Equal1~0_combout ), .cin(gnd), .combout(\ula_|video_|Selector0~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Selector0~0 .lut_mask = 16'hEAC0; +defparam \ula_|video_|Selector0~0 .lut_mask = 16'hF888; defparam \ula_|video_|Selector0~0 .sum_lutc_input = "datac"; // synopsys translate_on @@ -59688,7 +59438,7 @@ defparam \ula_|video_|VGA_HS .is_wysiwyg = "true"; defparam \ula_|video_|VGA_HS .power_up = "low"; // synopsys translate_on -// Location: FF_X34_Y33_N25 +// Location: FF_X35_Y32_N5 dffeas \ula_|video_|VGA_VS~_Duplicate_1 ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|Selector1~0_combout ), @@ -59707,21 +59457,21 @@ defparam \ula_|video_|VGA_VS~_Duplicate_1 .is_wysiwyg = "true"; defparam \ula_|video_|VGA_VS~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y33_N24 +// Location: LCCOMB_X35_Y32_N4 cycloneive_lcell_comb \ula_|video_|Selector1~0 ( // Equation(s): -// \ula_|video_|Selector1~0_combout = (\ula_|video_|Equal3~1_combout & (\ula_|video_|Equal2~2_combout & ((\ula_|video_|vga_vc [1])))) # (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|VGA_VS~_Duplicate_1_q ) # ((\ula_|video_|Equal2~2_combout & -// \ula_|video_|vga_vc [1])))) +// \ula_|video_|Selector1~0_combout = (\ula_|video_|Equal2~2_combout & ((\ula_|video_|vga_vc [1]) # ((\ula_|video_|VGA_VS~_Duplicate_1_q & !\ula_|video_|Equal3~1_combout )))) # (!\ula_|video_|Equal2~2_combout & (((\ula_|video_|VGA_VS~_Duplicate_1_q & +// !\ula_|video_|Equal3~1_combout )))) - .dataa(\ula_|video_|Equal3~1_combout ), - .datab(\ula_|video_|Equal2~2_combout ), + .dataa(\ula_|video_|Equal2~2_combout ), + .datab(\ula_|video_|vga_vc [1]), .datac(\ula_|video_|VGA_VS~_Duplicate_1_q ), - .datad(\ula_|video_|vga_vc [1]), + .datad(\ula_|video_|Equal3~1_combout ), .cin(gnd), .combout(\ula_|video_|Selector1~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Selector1~0 .lut_mask = 16'hDC50; +defparam \ula_|video_|Selector1~0 .lut_mask = 16'h88F8; defparam \ula_|video_|Selector1~0 .sum_lutc_input = "datac"; // synopsys translate_on @@ -59744,7 +59494,7 @@ defparam \ula_|video_|VGA_VS .is_wysiwyg = "true"; defparam \ula_|video_|VGA_VS .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X47_Y17_N4 +// Location: LCCOMB_X27_Y13_N26 cycloneive_lcell_comb \z80_|memory_ifc_|q1~feeder ( // Equation(s): // \z80_|memory_ifc_|q1~feeder_combout = \z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q @@ -59761,7 +59511,7 @@ defparam \z80_|memory_ifc_|q1~feeder .lut_mask = 16'hFF00; defparam \z80_|memory_ifc_|q1~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X47_Y17_N5 +// Location: FF_X27_Y13_N27 dffeas \z80_|memory_ifc_|q1 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|memory_ifc_|q1~feeder_combout ), @@ -59780,7 +59530,7 @@ defparam \z80_|memory_ifc_|q1 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|q1 .power_up = "low"; // synopsys translate_on -// Location: FF_X47_Y17_N25 +// Location: FF_X27_Y13_N17 dffeas \z80_|memory_ifc_|q2 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), @@ -59799,7 +59549,7 @@ defparam \z80_|memory_ifc_|q2 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|q2 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X47_Y17_N24 +// Location: LCCOMB_X27_Y13_N16 cycloneive_lcell_comb \z80_|memory_ifc_|nRFSH_out~0 ( // Equation(s): // \z80_|memory_ifc_|nRFSH_out~0_combout = (!\z80_|memory_ifc_|q2~q & \z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q ) @@ -59816,41 +59566,41 @@ defparam \z80_|memory_ifc_|nRFSH_out~0 .lut_mask = 16'h0F00; defparam \z80_|memory_ifc_|nRFSH_out~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X47_Y17_N26 +// Location: LCCOMB_X27_Y13_N20 cycloneive_lcell_comb \z80_|memory_ifc_|nM1_out ( // Equation(s): // \z80_|memory_ifc_|nM1_out~combout = (\z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - .dataa(gnd), + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(gnd), .datad(\z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q ), .cin(gnd), .combout(\z80_|memory_ifc_|nM1_out~combout ), .cout()); // synopsys translate_off -defparam \z80_|memory_ifc_|nM1_out .lut_mask = 16'hFF0F; +defparam \z80_|memory_ifc_|nM1_out .lut_mask = 16'hFF55; defparam \z80_|memory_ifc_|nM1_out .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y26_N0 +// Location: LCCOMB_X24_Y10_N28 cycloneive_lcell_comb \ula_|beep~0 ( // Equation(s): -// \ula_|beep~0_combout = \D[4]~98_combout $ (\raw_loader_in~input_o $ (\D[3]~96_combout )) +// \ula_|beep~0_combout = \raw_loader_in~input_o $ (\D[3]~74_combout $ (\D[4]~76_combout )) - .dataa(gnd), - .datab(\D[4]~98_combout ), - .datac(\raw_loader_in~input_o ), - .datad(\D[3]~96_combout ), + .dataa(\raw_loader_in~input_o ), + .datab(\D[3]~74_combout ), + .datac(gnd), + .datad(\D[4]~76_combout ), .cin(gnd), .combout(\ula_|beep~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|beep~0 .lut_mask = 16'hC33C; +defparam \ula_|beep~0 .lut_mask = 16'h9966; defparam \ula_|beep~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X23_Y26_N1 +// Location: FF_X24_Y10_N29 dffeas \ula_|beep ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\ula_|beep~0_combout ), diff --git a/simulation/modelsim/spectrum_6_1200mv_0c_v_slow.sdo b/simulation/modelsim/spectrum_6_1200mv_0c_v_slow.sdo index 33e447c..b89e11a 100644 --- a/simulation/modelsim/spectrum_6_1200mv_0c_v_slow.sdo +++ b/simulation/modelsim/spectrum_6_1200mv_0c_v_slow.sdo @@ -29,7 +29,7 @@ (DELAYFILE (SDFVERSION "2.1") (DESIGN "spectrum") - (DATE "04/01/2022 18:55:52") + (DATE "04/02/2022 15:53:45") (VENDOR "Altera") (PROGRAM "Quartus II 32-bit") (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition") @@ -41,8 +41,8 @@ (INSTANCE GPIO_1\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (1954:1954:1954) (1953:1953:1953)) - (PORT oe (1513:1513:1513) (1540:1540:1540)) + (PORT i (1685:1685:1685) (1692:1692:1692)) + (PORT oe (613:613:613) (645:645:645)) (IOPATH i o (2194:2194:2194) (2119:2119:2119)) (IOPATH oe o (2175:2175:2175) (2064:2064:2064)) ) @@ -53,8 +53,8 @@ (INSTANCE GPIO_1\[1\]\~output) (DELAY (ABSOLUTE - (PORT i (1975:1975:1975) (1942:1942:1942)) - (PORT oe (1769:1769:1769) (1737:1737:1737)) + (PORT i (1389:1389:1389) (1378:1378:1378)) + (PORT oe (2452:2452:2452) (2380:2380:2380)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) (IOPATH oe o (2265:2265:2265) (2140:2140:2140)) ) @@ -65,8 +65,8 @@ (INSTANCE GPIO_1\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (1830:1830:1830) (1856:1856:1856)) - (PORT oe (1769:1769:1769) (1737:1737:1737)) + (PORT i (1495:1495:1495) (1494:1494:1494)) + (PORT oe (2452:2452:2452) (2380:2380:2380)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) (IOPATH oe o (2265:2265:2265) (2140:2140:2140)) ) @@ -77,8 +77,8 @@ (INSTANCE GPIO_1\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (2041:2041:2041) (2075:2075:2075)) - (PORT oe (1983:1983:1983) (2026:2026:2026)) + (PORT i (1235:1235:1235) (1221:1221:1221)) + (PORT oe (2274:2274:2274) (2208:2208:2208)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) (IOPATH oe o (2265:2265:2265) (2140:2140:2140)) ) @@ -89,8 +89,8 @@ (INSTANCE GPIO_1\[4\]\~output) (DELAY (ABSOLUTE - (PORT i (2091:2091:2091) (2141:2141:2141)) - (PORT oe (1983:1983:1983) (2026:2026:2026)) + (PORT i (1237:1237:1237) (1244:1244:1244)) + (PORT oe (2274:2274:2274) (2208:2208:2208)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) (IOPATH oe o (2265:2265:2265) (2140:2140:2140)) ) @@ -101,8 +101,8 @@ (INSTANCE GPIO_1\[5\]\~output) (DELAY (ABSOLUTE - (PORT i (1824:1824:1824) (1811:1811:1811)) - (PORT oe (1772:1772:1772) (1805:1805:1805)) + (PORT i (1326:1326:1326) (1336:1336:1336)) + (PORT oe (2089:2089:2089) (2031:2031:2031)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) (IOPATH oe o (2265:2265:2265) (2140:2140:2140)) ) @@ -113,8 +113,8 @@ (INSTANCE GPIO_1\[6\]\~output) (DELAY (ABSOLUTE - (PORT i (1513:1513:1513) (1526:1526:1526)) - (PORT oe (1772:1772:1772) (1805:1805:1805)) + (PORT i (1105:1105:1105) (1130:1130:1130)) + (PORT oe (2089:2089:2089) (2031:2031:2031)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) (IOPATH oe o (2265:2265:2265) (2140:2140:2140)) ) @@ -125,8 +125,8 @@ (INSTANCE GPIO_1\[7\]\~output) (DELAY (ABSOLUTE - (PORT i (1827:1827:1827) (1912:1912:1912)) - (PORT oe (1772:1772:1772) (1805:1805:1805)) + (PORT i (844:844:844) (877:877:877)) + (PORT oe (2089:2089:2089) (2031:2031:2031)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) (IOPATH oe o (2265:2265:2265) (2140:2140:2140)) ) @@ -137,8 +137,8 @@ (INSTANCE GPIO_1\[8\]\~output) (DELAY (ABSOLUTE - (PORT i (909:909:909) (940:940:940)) - (PORT oe (1999:1999:1999) (2033:2033:2033)) + (PORT i (1080:1080:1080) (1099:1099:1099)) + (PORT oe (1846:1846:1846) (1798:1798:1798)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) (IOPATH oe o (2265:2265:2265) (2140:2140:2140)) ) @@ -149,8 +149,8 @@ (INSTANCE GPIO_1\[9\]\~output) (DELAY (ABSOLUTE - (PORT i (1589:1589:1589) (1611:1611:1611)) - (PORT oe (1999:1999:1999) (2033:2033:2033)) + (PORT i (1098:1098:1098) (1129:1129:1129)) + (PORT oe (1846:1846:1846) (1798:1798:1798)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) (IOPATH oe o (2265:2265:2265) (2140:2140:2140)) ) @@ -161,8 +161,8 @@ (INSTANCE GPIO_1\[10\]\~output) (DELAY (ABSOLUTE - (PORT i (1797:1797:1797) (1798:1798:1798)) - (PORT oe (2219:2219:2219) (2301:2301:2301)) + (PORT i (1271:1271:1271) (1296:1296:1296)) + (PORT oe (2168:2168:2168) (2165:2165:2165)) (IOPATH i o (4033:4033:4033) (3610:3610:3610)) (IOPATH oe o (4029:4029:4029) (3565:3565:3565)) ) @@ -173,8 +173,8 @@ (INSTANCE GPIO_1\[11\]\~output) (DELAY (ABSOLUTE - (PORT i (1305:1305:1305) (1313:1313:1313)) - (PORT oe (1999:1999:1999) (2033:2033:2033)) + (PORT i (848:848:848) (888:888:888)) + (PORT oe (1846:1846:1846) (1798:1798:1798)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) (IOPATH oe o (2265:2265:2265) (2140:2140:2140)) ) @@ -185,8 +185,8 @@ (INSTANCE GPIO_1\[12\]\~output) (DELAY (ABSOLUTE - (PORT i (2024:2024:2024) (1964:1964:1964)) - (PORT oe (1581:1581:1581) (1553:1553:1553)) + (PORT i (1787:1787:1787) (1787:1787:1787)) + (PORT oe (2662:2662:2662) (2560:2560:2560)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) (IOPATH oe o (2265:2265:2265) (2140:2140:2140)) ) @@ -197,8 +197,8 @@ (INSTANCE GPIO_1\[13\]\~output) (DELAY (ABSOLUTE - (PORT i (2054:2054:2054) (2078:2078:2078)) - (PORT oe (2220:2220:2220) (2301:2301:2301)) + (PORT i (836:836:836) (861:861:861)) + (PORT oe (2168:2168:2168) (2165:2165:2165)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) (IOPATH oe o (2265:2265:2265) (2140:2140:2140)) ) @@ -209,8 +209,8 @@ (INSTANCE GPIO_1\[14\]\~output) (DELAY (ABSOLUTE - (PORT i (1495:1495:1495) (1526:1526:1526)) - (PORT oe (1979:1979:1979) (2021:2021:2021)) + (PORT i (1343:1343:1343) (1354:1354:1354)) + (PORT oe (2302:2302:2302) (2232:2232:2232)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) (IOPATH oe o (2265:2265:2265) (2140:2140:2140)) ) @@ -221,8 +221,8 @@ (INSTANCE GPIO_1\[15\]\~output) (DELAY (ABSOLUTE - (PORT i (1599:1599:1599) (1663:1663:1663)) - (PORT oe (1787:1787:1787) (1749:1749:1749)) + (PORT i (1097:1097:1097) (1143:1143:1143)) + (PORT oe (2413:2413:2413) (2343:2343:2343)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) (IOPATH oe o (2265:2265:2265) (2140:2140:2140)) ) @@ -233,8 +233,8 @@ (INSTANCE GPIO_1\[16\]\~output) (DELAY (ABSOLUTE - (PORT i (1110:1110:1110) (1123:1123:1123)) - (PORT oe (2254:2254:2254) (2230:2230:2230)) + (PORT i (1128:1128:1128) (1170:1170:1170)) + (PORT oe (2248:2248:2248) (2235:2235:2235)) (IOPATH i o (2277:2277:2277) (2180:2180:2180)) (IOPATH oe o (2262:2262:2262) (2120:2120:2120)) ) @@ -245,8 +245,8 @@ (INSTANCE GPIO_1\[17\]\~output) (DELAY (ABSOLUTE - (PORT i (1121:1121:1121) (1144:1144:1144)) - (PORT oe (2255:2255:2255) (2231:2231:2231)) + (PORT i (1080:1080:1080) (1062:1062:1062)) + (PORT oe (2249:2249:2249) (2236:2236:2236)) (IOPATH i o (2277:2277:2277) (2180:2180:2180)) (IOPATH oe o (2262:2262:2262) (2120:2120:2120)) ) @@ -257,8 +257,8 @@ (INSTANCE GPIO_1\[18\]\~output) (DELAY (ABSOLUTE - (PORT i (1039:1039:1039) (1034:1034:1034)) - (PORT oe (1972:1972:1972) (1940:1940:1940)) + (PORT i (1311:1311:1311) (1313:1313:1313)) + (PORT oe (1968:1968:1968) (1946:1946:1946)) (IOPATH i o (2277:2277:2277) (2180:2180:2180)) (IOPATH oe o (2262:2262:2262) (2120:2120:2120)) ) @@ -269,8 +269,8 @@ (INSTANCE GPIO_1\[19\]\~output) (DELAY (ABSOLUTE - (PORT i (1077:1077:1077) (1107:1107:1107)) - (PORT oe (2254:2254:2254) (2230:2230:2230)) + (PORT i (1285:1285:1285) (1270:1270:1270)) + (PORT oe (2248:2248:2248) (2235:2235:2235)) (IOPATH i o (2277:2277:2277) (2180:2180:2180)) (IOPATH oe o (2262:2262:2262) (2120:2120:2120)) ) @@ -281,8 +281,8 @@ (INSTANCE GPIO_1\[20\]\~output) (DELAY (ABSOLUTE - (PORT i (1347:1347:1347) (1360:1360:1360)) - (PORT oe (1937:1937:1937) (1909:1909:1909)) + (PORT i (1107:1107:1107) (1122:1122:1122)) + (PORT oe (1941:1941:1941) (1912:1912:1912)) (IOPATH i o (2194:2194:2194) (2119:2119:2119)) (IOPATH oe o (2175:2175:2175) (2064:2064:2064)) ) @@ -293,8 +293,8 @@ (INSTANCE GPIO_1\[21\]\~output) (DELAY (ABSOLUTE - (PORT i (1247:1247:1247) (1225:1225:1225)) - (PORT oe (1971:1971:1971) (1939:1939:1939)) + (PORT i (1314:1314:1314) (1311:1311:1311)) + (PORT oe (1967:1967:1967) (1945:1945:1945)) (IOPATH i o (2277:2277:2277) (2180:2180:2180)) (IOPATH oe o (2262:2262:2262) (2120:2120:2120)) ) @@ -305,8 +305,8 @@ (INSTANCE GPIO_1\[22\]\~output) (DELAY (ABSOLUTE - (PORT i (1127:1127:1127) (1128:1128:1128)) - (PORT oe (1883:1883:1883) (1842:1842:1842)) + (PORT i (1320:1320:1320) (1327:1327:1327)) + (PORT oe (1878:1878:1878) (1847:1847:1847)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) (IOPATH oe o (2265:2265:2265) (2140:2140:2140)) ) @@ -317,8 +317,8 @@ (INSTANCE GPIO_1\[23\]\~output) (DELAY (ABSOLUTE - (PORT i (1045:1045:1045) (1025:1025:1025)) - (PORT oe (2220:2220:2220) (2182:2182:2182)) + (PORT i (1185:1185:1185) (1233:1233:1233)) + (PORT oe (2221:2221:2221) (2201:2201:2201)) (IOPATH i o (2277:2277:2277) (2180:2180:2180)) (IOPATH oe o (2262:2262:2262) (2120:2120:2120)) ) @@ -329,8 +329,8 @@ (INSTANCE GPIO_1\[27\]\~output) (DELAY (ABSOLUTE - (PORT i (1255:1255:1255) (1313:1313:1313)) - (PORT oe (1518:1518:1518) (1539:1539:1539)) + (PORT i (1934:1934:1934) (2037:2037:2037)) + (PORT oe (1173:1173:1173) (1249:1249:1249)) (IOPATH i o (2119:2119:2119) (2194:2194:2194)) (IOPATH oe o (2175:2175:2175) (2064:2064:2064)) ) @@ -341,8 +341,8 @@ (INSTANCE GPIO_1\[28\]\~output) (DELAY (ABSOLUTE - (PORT i (1602:1602:1602) (1577:1577:1577)) - (PORT oe (1787:1787:1787) (1749:1749:1749)) + (PORT i (1341:1341:1341) (1403:1403:1403)) + (PORT oe (2413:2413:2413) (2343:2343:2343)) (IOPATH i o (2180:2180:2180) (2265:2265:2265)) (IOPATH oe o (2265:2265:2265) (2140:2140:2140)) ) @@ -353,8 +353,8 @@ (INSTANCE GPIO_1\[29\]\~output) (DELAY (ABSOLUTE - (PORT i (1357:1357:1357) (1419:1419:1419)) - (PORT oe (1250:1250:1250) (1266:1266:1266)) + (PORT i (1476:1476:1476) (1560:1560:1560)) + (PORT oe (889:889:889) (957:957:957)) (IOPATH i o (2180:2180:2180) (2277:2277:2277)) (IOPATH oe o (2262:2262:2262) (2120:2120:2120)) ) @@ -365,8 +365,8 @@ (INSTANCE GPIO_1\[30\]\~output) (DELAY (ABSOLUTE - (PORT i (967:967:967) (940:940:940)) - (PORT oe (1226:1226:1226) (1242:1242:1242)) + (PORT i (1626:1626:1626) (1557:1557:1557)) + (PORT oe (620:620:620) (668:668:668)) (IOPATH i o (2277:2277:2277) (2180:2180:2180)) (IOPATH oe o (2262:2262:2262) (2120:2120:2120)) ) @@ -377,7 +377,7 @@ (INSTANCE LED\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (1447:1447:1447) (1410:1410:1410)) + (PORT i (1458:1458:1458) (1418:1418:1418)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) ) ) @@ -397,7 +397,7 @@ (INSTANCE LED\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (1202:1202:1202) (1194:1194:1194)) + (PORT i (1275:1275:1275) (1288:1288:1288)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) ) ) @@ -452,7 +452,7 @@ (INSTANCE VGA_R\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (1082:1082:1082) (1068:1068:1068)) + (PORT i (1269:1269:1269) (1257:1257:1257)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) ) ) @@ -462,7 +462,7 @@ (INSTANCE VGA_R\[1\]\~output) (DELAY (ABSOLUTE - (PORT i (995:995:995) (1003:1003:1003)) + (PORT i (1082:1082:1082) (1080:1080:1080)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) ) ) @@ -472,7 +472,7 @@ (INSTANCE VGA_R\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (719:719:719) (672:672:672)) + (PORT i (470:470:470) (453:453:453)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) ) ) @@ -482,7 +482,7 @@ (INSTANCE VGA_R\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (917:917:917) (865:865:865)) + (PORT i (956:956:956) (917:917:917)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) ) ) @@ -492,7 +492,7 @@ (INSTANCE VGA_G\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (908:908:908) (871:871:871)) + (PORT i (735:735:735) (699:699:699)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) ) ) @@ -502,7 +502,7 @@ (INSTANCE VGA_G\[1\]\~output) (DELAY (ABSOLUTE - (PORT i (670:670:670) (626:626:626)) + (PORT i (726:726:726) (691:691:691)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) ) ) @@ -512,7 +512,7 @@ (INSTANCE VGA_G\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (784:784:784) (728:728:728)) + (PORT i (963:963:963) (913:913:913)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) ) ) @@ -522,7 +522,7 @@ (INSTANCE VGA_G\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (784:784:784) (728:728:728)) + (PORT i (939:939:939) (893:893:893)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) ) ) @@ -532,7 +532,7 @@ (INSTANCE VGA_B\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (664:664:664) (633:633:633)) + (PORT i (719:719:719) (679:679:679)) (IOPATH i o (4033:4033:4033) (3610:3610:3610)) ) ) @@ -542,7 +542,7 @@ (INSTANCE VGA_B\[1\]\~output) (DELAY (ABSOLUTE - (PORT i (645:645:645) (617:617:617)) + (PORT i (674:674:674) (653:653:653)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) ) ) @@ -552,7 +552,7 @@ (INSTANCE VGA_B\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (883:883:883) (830:830:830)) + (PORT i (912:912:912) (879:879:879)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) ) ) @@ -562,7 +562,7 @@ (INSTANCE VGA_B\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (1278:1278:1278) (1196:1196:1196)) + (PORT i (1004:1004:1004) (989:989:989)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) ) ) @@ -590,7 +590,7 @@ (INSTANCE GPIO_1\[25\]\~output) (DELAY (ABSOLUTE - (PORT i (1842:1842:1842) (1809:1809:1809)) + (PORT i (2044:2044:2044) (2097:2097:2097)) (IOPATH i o (2180:2180:2180) (2265:2265:2265)) ) ) @@ -600,7 +600,7 @@ (INSTANCE GPIO_1\[26\]\~output) (DELAY (ABSOLUTE - (PORT i (1161:1161:1161) (1186:1186:1186)) + (PORT i (1549:1549:1549) (1625:1625:1625)) (IOPATH i o (3539:3539:3539) (3961:3961:3961)) ) ) @@ -610,7 +610,7 @@ (INSTANCE GPIO_1\[31\]\~output) (DELAY (ABSOLUTE - (PORT i (862:862:862) (826:826:826)) + (PORT i (1340:1340:1340) (1280:1280:1280)) (IOPATH i o (2277:2277:2277) (2180:2180:2180)) ) ) @@ -620,7 +620,7 @@ (INSTANCE buzzer_out\~output) (DELAY (ABSOLUTE - (PORT i (1253:1253:1253) (1261:1261:1261)) + (PORT i (2103:2103:2103) (2135:2135:2135)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) ) ) @@ -707,8 +707,8 @@ (INSTANCE ula_\|clocks_\|clk_cpu\~0) (DELAY (ABSOLUTE - (PORT datab (223:223:223) (293:293:293)) - (PORT datad (493:493:493) (526:526:526)) + (PORT datab (222:222:222) (291:291:291)) + (PORT datad (492:492:492) (527:527:527)) (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -734,35 +734,33 @@ (INSTANCE ula_\|clocks_\|clk_cpu\~clkctrl) (DELAY (ABSOLUTE - (PORT inclk[0] (655:655:655) (669:669:669)) + (PORT inclk[0] (658:658:658) (673:673:673)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|DFFE_M1_ff\~0) + (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_15) (DELAY (ABSOLUTE - (PORT dataa (1052:1052:1052) (1052:1052:1052)) - (PORT datad (1052:1052:1052) (1044:1044:1044)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|ena_M) - (DELAY - (ABSOLUTE - (PORT datac (1029:1029:1029) (1028:1028:1028)) - (PORT datad (1049:1049:1049) (1040:1040:1040)) + (PORT datab (1065:1065:1065) (1105:1105:1105)) + (PORT datac (575:575:575) (608:608:608)) + (PORT datad (829:829:829) (885:885:885)) + (IOPATH datab combout (308:308:308) (300:300:300)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_12\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (546:546:546) (592:592:592)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_io_ibuf") (INSTANCE KEY\[1\]\~input) @@ -777,9 +775,9 @@ (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_9) (DELAY (ABSOLUTE - (PORT dataa (321:321:321) (448:448:448)) - (PORT datad (1849:1849:1849) (1871:1871:1871)) - (IOPATH dataa combout (273:273:273) (269:269:269)) + (PORT datac (380:380:380) (421:421:421)) + (PORT datad (2330:2330:2330) (2381:2381:2381)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -789,9 +787,9 @@ (INSTANCE z80_\|interrupts_\|nmi_armed) (DELAY (ABSOLUTE - (PORT clk (1351:1351:1351) (1338:1338:1338)) + (PORT clk (1591:1591:1591) (1572:1572:1572)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1229:1229:1229) (1175:1175:1175)) + (PORT clrn (695:695:695) (696:696:696)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -805,47 +803,52 @@ (INSTANCE z80_\|interrupts_\|in_nmi_ALTERA_SYNTHESIZED\~feeder) (DELAY (ABSOLUTE - (PORT datad (736:736:736) (745:745:745)) + (PORT datad (329:329:329) (368:368:368)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_eval_cond\~0) + (INSTANCE z80_\|sequencer_\|DFFE_M2_ff\~0) (DELAY (ABSOLUTE - (PORT datac (219:219:219) (288:288:288)) - (PORT datad (226:226:226) (290:290:290)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (PORT dataa (396:396:396) (450:450:450)) + (PORT datab (1065:1065:1065) (1105:1105:1105)) + (PORT datad (826:826:826) (885:885:885)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~4) + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_M2_ff) (DELAY (ABSOLUTE - (PORT dataa (2229:2229:2229) (2292:2292:2292)) - (PORT datab (2226:2226:2226) (2286:2286:2286)) - (PORT datad (1468:1468:1468) (1557:1557:1557)) - (IOPATH dataa combout (267:267:267) (273:273:273)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (PORT clk (1337:1337:1337) (1354:1354:1354)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1380:1380:1380) (1352:1352:1352)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|sequencer_\|DFFE_M3_ff\~0) (DELAY (ABSOLUTE - (PORT dataa (1045:1045:1045) (1047:1047:1047)) - (PORT datab (378:378:378) (425:425:425)) - (PORT datad (1056:1056:1056) (1045:1045:1045)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (265:265:265) (275:275:275)) + (PORT dataa (243:243:243) (317:317:317)) + (PORT datab (1067:1067:1067) (1106:1106:1106)) + (PORT datad (829:829:829) (885:885:885)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -856,9 +859,9 @@ (INSTANCE z80_\|sequencer_\|DFFE_M3_ff) (DELAY (ABSOLUTE - (PORT clk (1362:1362:1362) (1383:1383:1383)) + (PORT clk (1337:1337:1337) (1354:1354:1354)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1408:1408:1408) (1379:1379:1379)) + (PORT clrn (1380:1380:1380) (1352:1352:1352)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -867,30 +870,16 @@ (HOLD d (posedge clk) (144:144:144)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1262:1262:1262) (1213:1213:1213)) - (PORT datab (1423:1423:1423) (1478:1478:1478)) - (PORT datac (1249:1249:1249) (1279:1279:1279)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|sequencer_\|DFFE_M4_ff\~0) (DELAY (ABSOLUTE - (PORT dataa (1060:1060:1060) (1066:1066:1066)) - (PORT datab (379:379:379) (433:433:433)) - (PORT datad (1043:1043:1043) (1031:1031:1031)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (265:265:265) (275:275:275)) + (PORT dataa (263:263:263) (350:350:350)) + (PORT datab (1064:1064:1064) (1111:1111:1111)) + (PORT datad (828:828:828) (885:885:885)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -901,9 +890,9 @@ (INSTANCE z80_\|sequencer_\|DFFE_M4_ff) (DELAY (ABSOLUTE - (PORT clk (1362:1362:1362) (1383:1383:1383)) + (PORT clk (1337:1337:1337) (1354:1354:1354)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1408:1408:1408) (1379:1379:1379)) + (PORT clrn (1380:1380:1380) (1352:1352:1352)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -912,1468 +901,16 @@ (HOLD d (posedge clk) (144:144:144)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal32\~0) - (DELAY - (ABSOLUTE - (PORT datab (360:360:360) (412:412:412)) - (PORT datad (612:612:612) (661:661:661)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_11) - (DELAY - (ABSOLUTE - (PORT datab (2400:2400:2400) (2429:2429:2429)) - (PORT datad (1482:1482:1482) (1552:1552:1552)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|table_xx\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1268:1268:1268) (1344:1344:1344)) - (PORT datad (1113:1113:1113) (1173:1173:1173)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal1\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1551:1551:1551) (1547:1547:1547)) - (PORT datab (863:863:863) (876:876:876)) - (PORT datac (1969:1969:1969) (2066:2066:2066)) - (PORT datad (1075:1075:1075) (1083:1083:1083)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal2\~0) - (DELAY - (ABSOLUTE - (PORT datac (1336:1336:1336) (1371:1371:1371)) - (PORT datad (2093:2093:2093) (2156:2156:2156)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal36\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1155:1155:1155) (1200:1200:1200)) - (PORT datab (1518:1518:1518) (1601:1601:1601)) - (PORT datac (834:834:834) (865:865:865)) - (PORT datad (878:878:878) (895:895:895)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_tbl_cb_set) - (DELAY - (ABSOLUTE - (PORT dataa (1601:1601:1601) (1614:1614:1614)) - (PORT datab (1315:1315:1315) (1312:1312:1312)) - (PORT datac (783:783:783) (794:794:794)) - (PORT datad (731:731:731) (698:698:698)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_tbl_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1132:1132:1132) (1169:1169:1169)) - (PORT datab (2443:2443:2443) (2464:2464:2464)) - (PORT datac (781:781:781) (791:791:791)) - (PORT datad (898:898:898) (951:951:951)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|DFFE_instCB) - (DELAY - (ABSOLUTE - (PORT clk (1354:1354:1354) (1376:1376:1376)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1400:1400:1400) (1371:1371:1371)) - (PORT ena (716:716:716) (714:714:714)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal52\~0) - (DELAY - (ABSOLUTE - (PORT dataa (662:662:662) (725:725:725)) - (PORT datab (1149:1149:1149) (1197:1197:1197)) - (PORT datac (897:897:897) (935:935:935)) - (PORT datad (1227:1227:1227) (1306:1306:1306)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal2\~1) - (DELAY - (ABSOLUTE - (PORT dataa (2170:2170:2170) (2236:2236:2236)) - (PORT datab (1514:1514:1514) (1603:1603:1603)) - (PORT datac (834:834:834) (863:863:863)) - (PORT datad (622:622:622) (647:647:647)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_tbl_ed_set) - (DELAY - (ABSOLUTE - (PORT dataa (1618:1618:1618) (1654:1654:1654)) - (PORT datab (780:780:780) (764:764:764)) - (PORT datac (1286:1286:1286) (1282:1282:1282)) - (PORT datad (1889:1889:1889) (1943:1943:1943)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|DFFE_instED) - (DELAY - (ABSOLUTE - (PORT clk (1354:1354:1354) (1376:1376:1376)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1400:1400:1400) (1371:1371:1371)) - (PORT ena (716:716:716) (714:714:714)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal13\~0) - (DELAY - (ABSOLUTE - (PORT dataa (665:665:665) (728:728:728)) - (PORT datac (890:890:890) (927:927:927)) - (PORT datad (1223:1223:1223) (1301:1301:1301)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal33\~0) - (DELAY - (ABSOLUTE - (PORT dataa (2001:2001:2001) (2098:2098:2098)) - (PORT datac (1337:1337:1337) (1368:1368:1368)) - (PORT datad (2095:2095:2095) (2153:2153:2153)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_im_we) - (DELAY - (ABSOLUTE - (PORT dataa (564:564:564) (569:569:569)) - (PORT datab (972:972:972) (1033:1033:1033)) - (PORT datac (1235:1235:1235) (1324:1324:1324)) - (PORT datad (850:850:850) (879:879:879)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal49\~0) - (DELAY - (ABSOLUTE - (PORT datab (917:917:917) (979:979:979)) - (PORT datac (601:601:601) (640:640:640)) - (PORT datad (1151:1151:1151) (1208:1208:1208)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal33\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1302:1302:1302) (1348:1348:1348)) - (PORT datab (1375:1375:1375) (1421:1421:1421)) - (PORT datac (1321:1321:1321) (1379:1379:1379)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal6\~0) - (DELAY - (ABSOLUTE - (PORT dataa (662:662:662) (725:725:725)) - (PORT datab (1149:1149:1149) (1197:1197:1197)) - (PORT datac (897:897:897) (936:936:936)) - (PORT datad (1227:1227:1227) (1307:1307:1307)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1126:1126:1126) (1167:1167:1167)) - (PORT datab (1177:1177:1177) (1243:1243:1243)) - (PORT datad (653:653:653) (694:694:694)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal12\~0) - (DELAY - (ABSOLUTE - (PORT dataa (2447:2447:2447) (2537:2537:2537)) - (PORT datab (821:821:821) (835:835:835)) - (PORT datac (1028:1028:1028) (1065:1065:1065)) - (PORT datad (1063:1063:1063) (1082:1082:1082)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~8) - (DELAY - (ABSOLUTE - (PORT dataa (863:863:863) (923:923:923)) - (PORT datab (1440:1440:1440) (1502:1502:1502)) - (PORT datac (1299:1299:1299) (1315:1315:1315)) - (PORT datad (182:182:182) (214:214:214)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|nM1_int\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1028:1028:1028) (1119:1119:1119)) - (PORT datad (1947:1947:1947) (2004:2004:2004)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1001:1001:1001) (1052:1052:1052)) - (PORT datab (1029:1029:1029) (1024:1024:1024)) - (PORT datac (310:310:310) (319:319:319)) - (PORT datad (638:638:638) (672:672:672)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal3\~0) - (DELAY - (ABSOLUTE - (PORT datac (1314:1314:1314) (1383:1383:1383)) - (PORT datad (1350:1350:1350) (1411:1411:1411)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1153:1153:1153) (1191:1191:1191)) - (PORT datab (1516:1516:1516) (1601:1601:1601)) - (PORT datac (1576:1576:1576) (1593:1593:1593)) - (PORT datad (879:879:879) (897:897:897)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~7) - (DELAY - (ABSOLUTE - (PORT datac (1830:1830:1830) (1949:1949:1949)) - (PORT datad (1139:1139:1139) (1170:1170:1170)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1785:1785:1785) (1823:1823:1823)) - (PORT datac (2376:2376:2376) (2399:2399:2399)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~4) - (DELAY - (ABSOLUTE - (PORT dataa (825:825:825) (835:835:835)) - (PORT datab (947:947:947) (992:992:992)) - (PORT datac (779:779:779) (830:830:830)) - (PORT datad (859:859:859) (876:876:876)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal40\~1) - (DELAY - (ABSOLUTE - (PORT dataa (836:836:836) (842:842:842)) - (PORT datab (821:821:821) (826:826:826)) - (PORT datac (838:838:838) (890:890:890)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal39\~0) - (DELAY - (ABSOLUTE - (PORT dataa (837:837:837) (841:841:841)) - (PORT datab (824:824:824) (822:822:822)) - (PORT datac (839:839:839) (888:888:888)) - (PORT datad (1082:1082:1082) (1087:1087:1087)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~1) - (DELAY - (ABSOLUTE - (PORT dataa (798:798:798) (807:807:807)) - (PORT datac (904:904:904) (936:936:936)) - (PORT datad (1074:1074:1074) (1054:1054:1054)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal13\~1) - (DELAY - (ABSOLUTE - (PORT dataa (2000:2000:2000) (2094:2094:2094)) - (PORT datac (1337:1337:1337) (1365:1365:1365)) - (PORT datad (2091:2091:2091) (2150:2150:2150)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal13\~2) - (DELAY - (ABSOLUTE - (PORT dataa (807:807:807) (861:861:861)) - (PORT datab (1587:1587:1587) (1615:1615:1615)) - (PORT datac (1051:1051:1051) (1035:1035:1035)) - (PORT datad (602:602:602) (618:618:618)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal3\~2) - (DELAY - (ABSOLUTE - (PORT dataa (873:873:873) (871:871:871)) - (PORT datab (2149:2149:2149) (2219:2219:2219)) - (PORT datac (1578:1578:1578) (1596:1596:1596)) - (PORT datad (618:618:618) (643:643:643)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_iy_set\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1111:1111:1111) (1186:1186:1186)) - (PORT datab (1912:1912:1912) (2034:2034:2034)) - (PORT datac (798:798:798) (784:784:784)) - (PORT datad (1339:1339:1339) (1371:1371:1371)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~8) - (DELAY - (ABSOLUTE - (PORT datab (1310:1310:1310) (1338:1338:1338)) - (PORT datac (1438:1438:1438) (1451:1451:1451)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~6) - (DELAY - (ABSOLUTE - (PORT datac (1484:1484:1484) (1509:1509:1509)) - (PORT datad (1740:1740:1740) (1785:1785:1785)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~9) - (DELAY - (ABSOLUTE - (PORT datac (951:951:951) (1008:1008:1008)) - (PORT datad (910:910:910) (938:938:938)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~12) - (DELAY - (ABSOLUTE - (PORT dataa (924:924:924) (955:955:955)) - (PORT datab (917:917:917) (933:933:933)) - (PORT datac (837:837:837) (836:836:836)) - (PORT datad (1899:1899:1899) (1915:1915:1915)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~10) - (DELAY - (ABSOLUTE - (PORT dataa (384:384:384) (411:411:411)) - (PORT datab (1065:1065:1065) (1080:1080:1080)) - (PORT datac (573:573:573) (605:605:605)) - (PORT datad (1017:1017:1017) (1034:1034:1034)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal44\~0) - (DELAY - (ABSOLUTE - (PORT dataa (662:662:662) (727:727:727)) - (PORT datab (1154:1154:1154) (1202:1202:1202)) - (PORT datac (891:891:891) (928:928:928)) - (PORT datad (1223:1223:1223) (1302:1302:1302)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~16) - (DELAY - (ABSOLUTE - (PORT dataa (896:896:896) (972:972:972)) - (PORT datab (1230:1230:1230) (1207:1207:1207)) - (PORT datac (856:856:856) (914:914:914)) - (PORT datad (1025:1025:1025) (1004:1004:1004)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~13) - (DELAY - (ABSOLUTE - (PORT datab (773:773:773) (797:797:797)) - (PORT datac (572:572:572) (595:595:595)) - (PORT datad (192:192:192) (222:222:222)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal50\~0) - (DELAY - (ABSOLUTE - (PORT datab (918:918:918) (983:983:983)) - (PORT datac (602:602:602) (637:637:637)) - (PORT datad (1080:1080:1080) (1127:1127:1127)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal33\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1127:1127:1127) (1166:1166:1166)) - (PORT datab (1178:1178:1178) (1243:1243:1243)) - (PORT datad (653:653:653) (694:694:694)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~17) - (DELAY - (ABSOLUTE - (PORT dataa (888:888:888) (961:961:961)) - (PORT datab (1021:1021:1021) (990:990:990)) - (PORT datac (854:854:854) (908:908:908)) - (PORT datad (1001:1001:1001) (970:970:970)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~5) - (DELAY - (ABSOLUTE - (PORT datac (1464:1464:1464) (1537:1537:1537)) - (PORT datad (909:909:909) (938:938:938)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~14) - (DELAY - (ABSOLUTE - (PORT dataa (568:568:568) (600:600:600)) - (PORT datab (180:180:180) (212:212:212)) - (PORT datac (180:180:180) (216:216:216)) - (PORT datad (1021:1021:1021) (995:995:995)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1465:1465:1465) (1484:1484:1484)) - (PORT datab (1312:1312:1312) (1341:1341:1341)) - (PORT datac (350:350:350) (354:354:354)) - (PORT datad (1660:1660:1660) (1718:1718:1718)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1006:1006:1006) (1006:1006:1006)) - (PORT datab (212:212:212) (254:254:254)) - (PORT datac (156:156:156) (187:187:187)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_ixiy_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1185:1185:1185) (1234:1234:1234)) - (PORT datab (1381:1381:1381) (1410:1410:1410)) - (PORT datac (1348:1348:1348) (1401:1401:1401)) - (PORT datad (1893:1893:1893) (2005:2005:2005)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|DFFE_instIY1) - (DELAY - (ABSOLUTE - (PORT clk (1348:1348:1348) (1369:1369:1369)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1407:1407:1407) (1373:1373:1373)) - (PORT ena (745:745:745) (752:752:752)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (812:812:812) (851:851:851)) - (PORT datac (591:591:591) (628:628:628)) - (PORT datad (1268:1268:1268) (1330:1330:1330)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1163:1163:1163) (1209:1209:1209)) - (PORT datab (418:418:418) (465:465:465)) - (PORT datac (1561:1561:1561) (1571:1571:1571)) - (PORT datad (244:244:244) (293:293:293)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~2) - (DELAY - (ABSOLUTE - (PORT dataa (650:650:650) (710:710:710)) - (PORT datab (925:925:925) (963:963:963)) - (PORT datac (632:632:632) (694:694:694)) - (PORT datad (1226:1226:1226) (1304:1304:1304)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1491:1491:1491) (1603:1603:1603)) - (PORT datab (1405:1405:1405) (1444:1444:1444)) - (PORT datac (1574:1574:1574) (1628:1628:1628)) - (PORT datad (1380:1380:1380) (1457:1457:1457)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1201:1201:1201) (1253:1253:1253)) - (PORT datab (1150:1150:1150) (1183:1183:1183)) - (PORT datac (957:957:957) (983:983:983)) - (PORT datad (1554:1554:1554) (1554:1554:1554)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~26) - (DELAY - (ABSOLUTE - (PORT datac (625:625:625) (655:655:655)) - (PORT datad (1595:1595:1595) (1666:1666:1666)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~27) - (DELAY - (ABSOLUTE - (PORT dataa (597:597:597) (593:593:593)) - (PORT datac (1016:1016:1016) (1041:1041:1041)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~7) - (DELAY - (ABSOLUTE - (PORT dataa (189:189:189) (227:227:227)) - (PORT datab (218:218:218) (262:262:262)) - (PORT datac (616:616:616) (628:628:628)) - (PORT datad (1898:1898:1898) (1914:1914:1914)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~5) - (DELAY - (ABSOLUTE - (PORT dataa (927:927:927) (960:960:960)) - (PORT datab (1142:1142:1142) (1138:1138:1138)) - (PORT datac (627:627:627) (661:661:661)) - (PORT datad (164:164:164) (186:186:186)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~18) - (DELAY - (ABSOLUTE - (PORT dataa (861:861:861) (921:921:921)) - (PORT datab (1436:1436:1436) (1502:1502:1502)) - (PORT datac (1297:1297:1297) (1313:1313:1313)) - (PORT datad (184:184:184) (214:214:214)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal55\~0) - (DELAY - (ABSOLUTE - (PORT dataa (261:261:261) (346:346:346)) - (PORT datac (833:833:833) (861:861:861)) - (PORT datad (852:852:852) (878:878:878)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|comb\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1621:1621:1621) (1670:1670:1670)) - (PORT datac (1054:1054:1054) (1097:1097:1097)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~15) - (DELAY - (ABSOLUTE - (PORT dataa (575:575:575) (597:597:597)) - (PORT datab (1083:1083:1083) (1081:1081:1081)) - (PORT datac (858:858:858) (922:922:922)) - (PORT datad (166:166:166) (192:192:192)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~17) - (DELAY - (ABSOLUTE - (PORT dataa (612:612:612) (638:638:638)) - (PORT datab (601:601:601) (604:604:604)) - (PORT datac (859:859:859) (924:924:924)) - (PORT datad (829:829:829) (826:826:826)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~5) - (DELAY - (ABSOLUTE - (PORT dataa (864:864:864) (868:868:868)) - (PORT datab (1107:1107:1107) (1080:1080:1080)) - (PORT datac (1672:1672:1672) (1725:1725:1725)) - (PORT datad (807:807:807) (820:820:820)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1556:1556:1556) (1580:1580:1580)) - (PORT datac (1522:1522:1522) (1548:1548:1548)) - (PORT datad (1081:1081:1081) (1109:1109:1109)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal9\~0) - (DELAY - (ABSOLUTE - (PORT datac (767:767:767) (786:786:786)) - (PORT datad (825:825:825) (873:873:873)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1554:1554:1554) (1584:1584:1584)) - (PORT datab (1552:1552:1552) (1580:1580:1580)) - (PORT datac (1363:1363:1363) (1419:1419:1419)) - (PORT datad (1142:1142:1142) (1162:1162:1162)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1359:1359:1359) (1387:1387:1387)) - (PORT datab (1132:1132:1132) (1189:1189:1189)) - (PORT datac (1315:1315:1315) (1370:1370:1370)) - (PORT datad (770:770:770) (747:747:747)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~20) - (DELAY - (ABSOLUTE - (PORT dataa (827:827:827) (808:808:808)) - (PORT datab (1149:1149:1149) (1166:1166:1166)) - (PORT datac (1267:1267:1267) (1245:1245:1245)) - (PORT datad (1175:1175:1175) (1183:1183:1183)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal12\~1) - (DELAY - (ABSOLUTE - (PORT dataa (570:570:570) (590:590:590)) - (PORT datab (881:881:881) (942:942:942)) - (PORT datad (1060:1060:1060) (1048:1048:1048)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal9\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1442:1442:1442) (1476:1476:1476)) - (PORT datab (917:917:917) (932:932:932)) - (PORT datac (1484:1484:1484) (1570:1570:1570)) - (PORT datad (1129:1129:1129) (1157:1157:1157)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal25\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1344:1344:1344) (1415:1415:1415)) - (PORT datab (1421:1421:1421) (1497:1497:1497)) - (PORT datac (1271:1271:1271) (1288:1288:1288)) - (PORT datad (1447:1447:1447) (1437:1437:1437)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~21) - (DELAY - (ABSOLUTE - (PORT dataa (832:832:832) (819:819:819)) - (PORT datab (1683:1683:1683) (1701:1701:1701)) - (PORT datac (805:805:805) (790:790:790)) - (PORT datad (1375:1375:1375) (1390:1390:1390)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1127:1127:1127) (1167:1167:1167)) - (PORT datac (876:876:876) (907:907:907)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal19\~0) - (DELAY - (ABSOLUTE - (PORT dataa (869:869:869) (865:865:865)) - (PORT datab (863:863:863) (893:893:893)) - (PORT datac (1483:1483:1483) (1575:1575:1575)) - (PORT datad (1128:1128:1128) (1157:1157:1157)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal1\~4) - (DELAY - (ABSOLUTE - (PORT datac (1578:1578:1578) (1613:1613:1613)) - (PORT datad (1886:1886:1886) (1938:1938:1938)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal29\~0) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (237:237:237)) - (PORT datab (1078:1078:1078) (1072:1072:1072)) - (PORT datac (1486:1486:1486) (1452:1452:1452)) - (PORT datad (1339:1339:1339) (1387:1387:1387)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal24\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1441:1441:1441) (1474:1474:1474)) - (PORT datab (913:913:913) (929:929:929)) - (PORT datac (1483:1483:1483) (1581:1581:1581)) - (PORT datad (1134:1134:1134) (1164:1164:1164)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal34\~0) - (DELAY - (ABSOLUTE - (PORT dataa (2001:2001:2001) (2097:2097:2097)) - (PORT datab (865:865:865) (881:881:881)) - (PORT datac (175:175:175) (206:206:206)) - (PORT datad (385:385:385) (421:421:421)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal37\~0) - (DELAY - (ABSOLUTE - (PORT dataa (410:410:410) (453:453:453)) - (PORT datab (863:863:863) (875:875:875)) - (PORT datac (1973:1973:1973) (2062:2062:2062)) - (PORT datad (1053:1053:1053) (1052:1052:1052)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal35\~0) - (DELAY - (ABSOLUTE - (PORT dataa (412:412:412) (452:452:452)) - (PORT datab (863:863:863) (876:876:876)) - (PORT datac (1969:1969:1969) (2064:2064:2064)) - (PORT datad (178:178:178) (200:200:200)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal38\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1493:1493:1493) (1602:1602:1602)) - (PORT datab (1418:1418:1418) (1497:1497:1497)) - (PORT datac (1573:1573:1573) (1625:1625:1625)) - (PORT datad (1334:1334:1334) (1354:1354:1354)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1033:1033:1033) (1015:1015:1015)) - (PORT datab (1013:1013:1013) (1053:1053:1053)) - (PORT datac (546:546:546) (546:546:546)) - (PORT datad (822:822:822) (842:842:842)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~3) - (DELAY - (ABSOLUTE - (PORT dataa (800:800:800) (821:821:821)) - (PORT datab (1265:1265:1265) (1297:1297:1297)) - (PORT datac (543:543:543) (561:561:561)) - (PORT datad (547:547:547) (536:536:536)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|comb\~0) - (DELAY - (ABSOLUTE - (PORT datab (1792:1792:1792) (1827:1827:1827)) - (PORT datac (1077:1077:1077) (1135:1135:1135)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal47\~0) - (DELAY - (ABSOLUTE - (PORT dataa (416:416:416) (461:461:461)) - (PORT datab (865:865:865) (881:881:881)) - (PORT datac (1972:1972:1972) (2061:2061:2061)) - (PORT datad (340:340:340) (342:342:342)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1189:1189:1189) (1227:1227:1227)) - (PORT datab (1119:1119:1119) (1117:1117:1117)) - (PORT datac (156:156:156) (186:186:186)) - (PORT datad (1173:1173:1173) (1221:1221:1221)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~22) - (DELAY - (ABSOLUTE - (PORT dataa (610:610:610) (636:636:636)) - (PORT datab (594:594:594) (585:585:585)) - (PORT datac (163:163:163) (197:197:197)) - (PORT datad (1082:1082:1082) (1083:1083:1083)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~24) - (DELAY - (ABSOLUTE - (PORT dataa (862:862:862) (869:869:869)) - (PORT datab (208:208:208) (254:254:254)) - (PORT datac (576:576:576) (584:584:584)) - (PORT datad (603:603:603) (621:621:621)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla42M3T3_6) - (DELAY - (ABSOLUTE - (PORT dataa (1339:1339:1339) (1327:1327:1327)) - (PORT datab (1126:1126:1126) (1187:1187:1187)) - (PORT datac (631:631:631) (657:657:657)) - (PORT datad (1056:1056:1056) (1051:1051:1051)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~6) - (DELAY - (ABSOLUTE - (PORT dataa (644:644:644) (680:680:680)) - (PORT datab (1062:1062:1062) (1049:1049:1049)) - (PORT datac (1678:1678:1678) (1728:1728:1728)) - (PORT datad (540:540:540) (545:545:545)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal6\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1345:1345:1345) (1407:1407:1407)) - (PORT datab (1044:1044:1044) (1070:1070:1070)) - (PORT datac (1099:1099:1099) (1163:1163:1163)) - (PORT datad (600:600:600) (626:626:626)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1351:1351:1351) (1413:1413:1413)) - (PORT datab (628:628:628) (661:661:661)) - (PORT datac (1097:1097:1097) (1155:1155:1155)) - (PORT datad (1294:1294:1294) (1285:1285:1285)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|sequencer_\|M5\~0) (DELAY (ABSOLUTE - (PORT dataa (1055:1055:1055) (1060:1060:1060)) - (PORT datab (243:243:243) (313:313:313)) - (PORT datad (1055:1055:1055) (1041:1041:1041)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (265:265:265) (275:275:275)) + (PORT dataa (243:243:243) (316:316:316)) + (PORT datab (1068:1068:1068) (1112:1112:1112)) + (PORT datad (830:830:830) (888:888:888)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -2384,9 +921,9 @@ (INSTANCE z80_\|sequencer_\|M5) (DELAY (ABSOLUTE - (PORT clk (1362:1362:1362) (1383:1383:1383)) + (PORT clk (1337:1337:1337) (1354:1354:1354)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1408:1408:1408) (1379:1379:1379)) + (PORT clrn (1380:1380:1380) (1352:1352:1352)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -2397,11 +934,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~2) + (INSTANCE z80_\|execute_\|ixy_d\~5) (DELAY (ABSOLUTE - (PORT datab (1460:1460:1460) (1548:1548:1548)) - (PORT datac (2403:2403:2403) (2409:2409:2409)) + (PORT datab (1095:1095:1095) (1194:1194:1194)) + (PORT datac (891:891:891) (915:915:915)) (IOPATH datab combout (308:308:308) (300:300:300)) (IOPATH datac combout (220:220:220) (216:216:216)) ) @@ -2409,1874 +946,49 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~29) + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~22) (DELAY (ABSOLUTE - (PORT dataa (599:599:599) (596:596:596)) - (PORT datab (866:866:866) (895:895:895)) - (PORT datac (934:934:934) (949:949:949)) - (PORT datad (608:608:608) (635:635:635)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~25) - (DELAY - (ABSOLUTE - (PORT dataa (1795:1795:1795) (1857:1857:1857)) - (PORT datab (633:633:633) (669:669:669)) - (PORT datac (612:612:612) (643:643:643)) - (PORT datad (551:551:551) (551:551:551)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1769:1769:1769) (1771:1771:1771)) - (PORT datab (824:824:824) (869:869:869)) - (PORT datac (174:174:174) (206:206:206)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1164:1164:1164) (1212:1212:1212)) - (PORT datab (419:419:419) (463:463:463)) - (PORT datac (1560:1560:1560) (1572:1572:1572)) - (PORT datad (242:242:242) (294:294:294)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal52\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1269:1269:1269) (1344:1344:1344)) - (PORT datab (863:863:863) (909:909:909)) - (PORT datac (889:889:889) (907:907:907)) - (PORT datad (1117:1117:1117) (1173:1173:1173)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~14) - (DELAY - (ABSOLUTE - (PORT dataa (892:892:892) (968:968:968)) - (PORT datab (1229:1229:1229) (1209:1209:1209)) - (PORT datac (851:851:851) (913:913:913)) - (PORT datad (1024:1024:1024) (1000:1000:1000)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~8) - (DELAY - (ABSOLUTE - (PORT dataa (588:588:588) (598:598:598)) - (PORT datab (1162:1162:1162) (1169:1169:1169)) - (PORT datac (524:524:524) (520:520:520)) - (PORT datad (1507:1507:1507) (1516:1516:1516)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal24\~0) - (DELAY - (ABSOLUTE - (PORT dataa (648:648:648) (713:713:713)) - (PORT datab (199:199:199) (233:233:233)) - (PORT datac (231:231:231) (314:314:314)) - (PORT datad (826:826:826) (839:839:839)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_pc\~0) - (DELAY - (ABSOLUTE - (PORT dataa (821:821:821) (845:845:845)) - (PORT datab (1015:1015:1015) (1057:1057:1057)) - (PORT datac (1018:1018:1018) (1024:1024:1024)) - (PORT datad (622:622:622) (638:638:638)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_pc\~1) - (DELAY - (ABSOLUTE - (PORT dataa (409:409:409) (438:438:438)) - (PORT datab (1792:1792:1792) (1867:1867:1867)) - (PORT datac (958:958:958) (971:971:971)) - (PORT datad (1445:1445:1445) (1464:1464:1464)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_pc\~2) - (DELAY - (ABSOLUTE - (PORT dataa (860:860:860) (886:886:886)) - (PORT datab (181:181:181) (213:213:213)) - (PORT datac (156:156:156) (187:187:187)) - (PORT datad (822:822:822) (840:840:840)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~17) - (DELAY - (ABSOLUTE - (PORT dataa (589:589:589) (602:602:602)) - (PORT datab (1112:1112:1112) (1118:1118:1118)) - (PORT datac (185:185:185) (225:225:225)) - (PORT datad (578:578:578) (592:592:592)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~6) - (DELAY - (ABSOLUTE - (PORT dataa (382:382:382) (408:408:408)) - (PORT datab (1081:1081:1081) (1087:1087:1087)) - (PORT datac (571:571:571) (603:603:603)) - (PORT datad (1022:1022:1022) (1035:1035:1035)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal11\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1492:1492:1492) (1602:1602:1602)) - (PORT datab (1404:1404:1404) (1447:1447:1447)) - (PORT datac (1574:1574:1574) (1625:1625:1625)) - (PORT datad (1378:1378:1378) (1458:1458:1458)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal10\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1491:1491:1491) (1604:1604:1604)) - (PORT datab (1406:1406:1406) (1443:1443:1443)) - (PORT datac (1575:1575:1575) (1624:1624:1624)) - (PORT datad (1381:1381:1381) (1455:1455:1455)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1563:1563:1563) (1599:1599:1599)) - (PORT datab (1362:1362:1362) (1404:1404:1404)) - (PORT datac (2378:2378:2378) (2398:2398:2398)) - (PORT datad (1743:1743:1743) (1779:1779:1779)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~4) - (DELAY - (ABSOLUTE - (PORT dataa (589:589:589) (602:602:602)) - (PORT datab (1161:1161:1161) (1170:1170:1170)) - (PORT datac (1041:1041:1041) (1032:1032:1032)) - (PORT datad (523:523:523) (506:506:506)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1164:1164:1164) (1212:1212:1212)) - (PORT datab (419:419:419) (462:462:462)) - (PORT datac (1561:1561:1561) (1572:1572:1572)) - (PORT datad (241:241:241) (293:293:293)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1028:1028:1028) (1044:1044:1044)) - (PORT datab (1056:1056:1056) (1076:1076:1076)) - (PORT datac (507:507:507) (487:487:487)) - (PORT datad (565:565:565) (562:562:562)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~9) - (DELAY - (ABSOLUTE - (PORT dataa (265:265:265) (325:325:325)) - (PORT datab (421:421:421) (461:461:461)) - (PORT datac (173:173:173) (203:203:203)) - (PORT datad (1271:1271:1271) (1327:1327:1327)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal46\~0) - (DELAY - (ABSOLUTE - (PORT dataa (259:259:259) (342:342:342)) - (PORT datab (875:875:875) (908:908:908)) - (PORT datac (836:836:836) (860:860:860)) - (PORT datad (1108:1108:1108) (1167:1167:1167)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1156:1156:1156) (1205:1205:1205)) - (PORT datab (794:794:794) (808:808:808)) - (PORT datac (1564:1564:1564) (1573:1573:1573)) - (PORT datad (242:242:242) (287:287:287)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1957:1957:1957) (1991:1991:1991)) - (PORT datab (1894:1894:1894) (1936:1936:1936)) - (PORT datac (896:896:896) (945:945:945)) - (PORT datad (1119:1119:1119) (1134:1134:1134)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1279:1279:1279) (1291:1291:1291)) - (PORT datab (978:978:978) (1022:1022:1022)) - (PORT datac (711:711:711) (680:680:680)) - (PORT datad (1137:1137:1137) (1143:1143:1143)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (907:907:907) (947:947:947)) - (PORT datac (1064:1064:1064) (1085:1085:1085)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (269:269:269) (332:332:332)) - (PORT datab (420:420:420) (460:460:460)) - (PORT datac (1115:1115:1115) (1139:1139:1139)) - (PORT datad (1266:1266:1266) (1324:1324:1324)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1041:1041:1041) (1136:1136:1136)) - (PORT datab (2035:2035:2035) (2054:2054:2054)) - (PORT datac (1230:1230:1230) (1285:1285:1285)) - (PORT datad (884:884:884) (922:922:922)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1669:1669:1669) (1692:1692:1692)) - (PORT datab (1199:1199:1199) (1213:1213:1213)) - (PORT datac (1267:1267:1267) (1246:1246:1246)) - (PORT datad (814:814:814) (797:797:797)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~8) - (DELAY - (ABSOLUTE - (PORT dataa (564:564:564) (562:562:562)) - (PORT datac (510:510:510) (508:508:508)) - (PORT datad (1141:1141:1141) (1159:1159:1159)) + (PORT dataa (1184:1184:1184) (1195:1195:1195)) + (PORT datad (1606:1606:1606) (1628:1628:1628)) (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~18) + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_11) (DELAY (ABSOLUTE - (PORT dataa (183:183:183) (218:218:218)) - (PORT datab (200:200:200) (232:232:232)) - (PORT datac (156:156:156) (186:186:186)) - (PORT datad (178:178:178) (200:200:200)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~19) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (188:188:188) (225:225:225)) - (PORT datac (793:793:793) (783:783:783)) - (PORT datad (788:788:788) (795:795:795)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~16) - (DELAY - (ABSOLUTE - (PORT datac (1912:1912:1912) (1952:1952:1952)) - (PORT datad (880:880:880) (918:918:918)) + (PORT datac (1541:1541:1541) (1555:1555:1555)) + (PORT datad (1901:1901:1901) (1982:1982:1982)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~36) - (DELAY - (ABSOLUTE - (PORT dataa (1483:1483:1483) (1600:1600:1600)) - (PORT datab (1404:1404:1404) (1443:1443:1443)) - (PORT datac (1566:1566:1566) (1623:1623:1623)) - (PORT datad (1374:1374:1374) (1455:1455:1455)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~9) - (DELAY - (ABSOLUTE - (PORT dataa (625:625:625) (655:655:655)) - (PORT datab (1379:1379:1379) (1404:1404:1404)) - (PORT datac (1050:1050:1050) (1096:1096:1096)) - (PORT datad (1279:1279:1279) (1264:1264:1264)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~44) - (DELAY - (ABSOLUTE - (PORT dataa (1976:1976:1976) (2058:2058:2058)) - (PORT datab (622:622:622) (670:670:670)) - (PORT datac (1582:1582:1582) (1588:1588:1588)) - (PORT datad (185:185:185) (212:212:212)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1183:1183:1183) (1233:1233:1233)) - (PORT datad (1885:1885:1885) (1995:1995:1995)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~6) - (DELAY - (ABSOLUTE - (PORT dataa (859:859:859) (885:885:885)) - (PORT datab (419:419:419) (435:435:435)) - (PORT datac (369:369:369) (398:398:398)) - (PORT datad (1436:1436:1436) (1448:1448:1448)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~7) - (DELAY - (ABSOLUTE - (PORT dataa (584:584:584) (593:593:593)) - (PORT datab (1062:1062:1062) (1073:1073:1073)) - (PORT datac (1335:1335:1335) (1345:1345:1345)) - (PORT datad (312:312:312) (324:324:324)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~7) - (DELAY - (ABSOLUTE - (PORT datac (1401:1401:1401) (1456:1456:1456)) - (PORT datad (1072:1072:1072) (1084:1084:1084)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1166:1166:1166) (1212:1212:1212)) - (PORT datab (794:794:794) (806:806:806)) - (PORT datac (1559:1559:1559) (1567:1567:1567)) - (PORT datad (244:244:244) (294:294:294)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1165:1165:1165) (1211:1211:1211)) - (PORT datab (419:419:419) (460:460:460)) - (PORT datac (1559:1559:1559) (1568:1568:1568)) - (PORT datad (248:248:248) (293:293:293)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1311:1311:1311) (1310:1310:1310)) - (PORT datab (1018:1018:1018) (1005:1005:1005)) - (PORT datac (995:995:995) (972:972:972)) - (PORT datad (868:868:868) (909:909:909)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla27npla34M1T1_3) - (DELAY - (ABSOLUTE - (PORT dataa (626:626:626) (658:658:658)) - (PORT datab (1076:1076:1076) (1125:1125:1125)) - (PORT datac (1339:1339:1339) (1351:1351:1351)) - (PORT datad (1353:1353:1353) (1375:1375:1375)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~8) - (DELAY - (ABSOLUTE - (PORT dataa (362:362:362) (375:375:375)) - (PORT datab (183:183:183) (216:216:216)) - (PORT datac (571:571:571) (590:590:590)) - (PORT datad (170:170:170) (198:198:198)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~9) - (DELAY - (ABSOLUTE - (PORT dataa (529:529:529) (528:528:528)) - (PORT datab (799:799:799) (782:782:782)) - (PORT datac (788:788:788) (812:812:812)) - (PORT datad (747:747:747) (739:739:739)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1069:1069:1069) (1062:1062:1062)) - (PORT datab (180:180:180) (212:212:212)) - (PORT datac (169:169:169) (209:209:209)) - (PORT datad (164:164:164) (186:186:186)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~7) - (DELAY - (ABSOLUTE - (PORT dataa (320:320:320) (440:440:440)) - (PORT datab (1127:1127:1127) (1143:1143:1143)) - (PORT datac (630:630:630) (641:641:641)) - (PORT datad (1195:1195:1195) (1262:1262:1262)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~8) - (DELAY - (ABSOLUTE - (PORT datab (2689:2689:2689) (2747:2747:2747)) - (PORT datac (1865:1865:1865) (1891:1891:1891)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla21M2T2_3) - (DELAY - (ABSOLUTE - (PORT dataa (1749:1749:1749) (1741:1741:1741)) - (PORT datab (1929:1929:1929) (1999:1999:1999)) - (PORT datac (1035:1035:1035) (1006:1006:1006)) - (PORT datad (188:188:188) (215:215:215)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_ixy_dT4_2) - (DELAY - (ABSOLUTE - (PORT datac (1142:1142:1142) (1188:1188:1188)) - (PORT datad (578:578:578) (592:592:592)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~39) - (DELAY - (ABSOLUTE - (PORT dataa (1097:1097:1097) (1115:1115:1115)) - (PORT datab (845:845:845) (865:865:865)) - (PORT datac (1866:1866:1866) (1858:1858:1858)) - (PORT datad (1360:1360:1360) (1373:1373:1373)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla26M1T4_3) - (DELAY - (ABSOLUTE - (PORT dataa (975:975:975) (1040:1040:1040)) - (PORT datab (2198:2198:2198) (2252:2252:2252)) - (PORT datad (1951:1951:1951) (2009:2009:2009)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1369:1369:1369) (1399:1399:1399)) - (PORT datab (934:934:934) (962:962:962)) - (PORT datac (824:824:824) (840:840:840)) - (PORT datad (1077:1077:1077) (1057:1057:1057)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1337:1337:1337) (1317:1317:1317)) - (PORT datab (1045:1045:1045) (1069:1069:1069)) - (PORT datac (313:313:313) (327:327:327)) - (PORT datad (1050:1050:1050) (1046:1046:1046)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~38) - (DELAY - (ABSOLUTE - (PORT dataa (352:352:352) (371:371:371)) - (PORT datab (1005:1005:1005) (1005:1005:1005)) - (PORT datac (1453:1453:1453) (1473:1473:1473)) - (PORT datad (754:754:754) (748:748:748)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_zero) - (DELAY - (ABSOLUTE - (PORT dataa (1057:1057:1057) (1058:1058:1058)) - (PORT datab (1080:1080:1080) (1081:1081:1081)) - (PORT datac (784:784:784) (792:792:792)) - (PORT datad (748:748:748) (744:744:744)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1095:1095:1095) (1095:1095:1095)) - (PORT datab (247:247:247) (316:316:316)) - (PORT datac (224:224:224) (279:279:279)) - (PORT datad (230:230:230) (267:267:267)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~14) - (DELAY - (ABSOLUTE - (PORT datac (876:876:876) (907:907:907)) - (PORT datad (1861:1861:1861) (1900:1900:1900)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (799:799:799) (807:807:807)) - (PORT datab (935:935:935) (964:964:964)) - (PORT datac (1128:1128:1128) (1143:1143:1143)) - (PORT datad (1076:1076:1076) (1053:1053:1053)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~1) - (DELAY - (ABSOLUTE - (PORT datab (200:200:200) (232:232:232)) - (PORT datad (177:177:177) (198:198:198)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1095:1095:1095) (1114:1114:1114)) - (PORT datab (936:936:936) (965:965:965)) - (PORT datac (1864:1864:1864) (1858:1858:1858)) - (PORT datad (1360:1360:1360) (1376:1376:1376)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~30) - (DELAY - (ABSOLUTE - (PORT dataa (1201:1201:1201) (1242:1242:1242)) - (PORT datab (1088:1088:1088) (1118:1118:1118)) - (PORT datac (782:782:782) (781:781:781)) - (PORT datad (1227:1227:1227) (1301:1301:1301)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~29) - (DELAY - (ABSOLUTE - (PORT dataa (856:856:856) (896:896:896)) - (PORT datab (883:883:883) (907:907:907)) - (PORT datac (1114:1114:1114) (1158:1158:1158)) - (PORT datad (607:607:607) (628:628:628)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~31) - (DELAY - (ABSOLUTE - (PORT dataa (1254:1254:1254) (1342:1342:1342)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (156:156:156) (186:186:186)) - (PORT datad (356:356:356) (362:362:362)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal69\~0) - (DELAY - (ABSOLUTE - (PORT dataa (803:803:803) (857:857:857)) - (PORT datab (1584:1584:1584) (1611:1611:1611)) - (PORT datac (1047:1047:1047) (1030:1030:1030)) - (PORT datad (605:605:605) (621:621:621)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal1\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1105:1105:1105) (1153:1153:1153)) - (PORT datad (1097:1097:1097) (1114:1114:1114)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~14) - (DELAY - (ABSOLUTE - (PORT dataa (935:935:935) (946:946:946)) - (PORT datab (1862:1862:1862) (1865:1865:1865)) - (PORT datac (1051:1051:1051) (1035:1035:1035)) - (PORT datad (602:602:602) (618:618:618)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1626:1626:1626) (1696:1696:1696)) - (PORT datab (862:862:862) (871:871:871)) - (PORT datad (197:197:197) (219:219:219)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal56\~0) - (DELAY - (ABSOLUTE - (PORT dataa (614:614:614) (640:640:640)) - (PORT datab (1083:1083:1083) (1081:1081:1081)) - (PORT datac (857:857:857) (921:921:921)) - (PORT datad (843:843:843) (863:863:863)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1361:1361:1361) (1388:1388:1388)) - (PORT datab (1126:1126:1126) (1184:1184:1184)) - (PORT datac (1320:1320:1320) (1376:1376:1376)) - (PORT datad (766:766:766) (743:743:743)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~2) - (DELAY - (ABSOLUTE - (PORT dataa (763:763:763) (765:765:765)) - (PORT datab (785:785:785) (803:803:803)) - (PORT datad (612:612:612) (635:635:635)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1851:1851:1851) (1879:1879:1879)) - (PORT datab (1944:1944:1944) (1958:1958:1958)) - (PORT datac (513:513:513) (506:506:506)) - (PORT datad (1594:1594:1594) (1608:1608:1608)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~4) - (DELAY - (ABSOLUTE - (PORT dataa (798:798:798) (798:798:798)) - (PORT datab (877:877:877) (901:901:901)) - (PORT datac (160:160:160) (193:193:193)) - (PORT datad (1351:1351:1351) (1370:1370:1370)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~5) - (DELAY - (ABSOLUTE - (PORT datac (1076:1076:1076) (1085:1085:1085)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1126:1126:1126) (1170:1170:1170)) - (PORT datab (912:912:912) (976:976:976)) - (PORT datac (603:603:603) (636:636:636)) - (PORT datad (1148:1148:1148) (1203:1203:1203)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~15) - (DELAY - (ABSOLUTE - (PORT datab (996:996:996) (1071:1071:1071)) - (PORT datac (1357:1357:1357) (1402:1402:1402)) - (PORT datad (2154:2154:2154) (2212:2212:2212)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~8) - (DELAY - (ABSOLUTE - (PORT dataa (620:620:620) (656:656:656)) - (PORT datab (1652:1652:1652) (1651:1651:1651)) - (PORT datac (898:898:898) (950:950:950)) - (PORT datad (1119:1119:1119) (1138:1138:1138)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~9) - (DELAY - (ABSOLUTE - (PORT dataa (934:934:934) (980:980:980)) - (PORT datab (1157:1157:1157) (1169:1169:1169)) - (PORT datac (1014:1014:1014) (1031:1031:1031)) - (PORT datad (168:168:168) (192:192:192)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~3) - (DELAY - (ABSOLUTE - (PORT dataa (873:873:873) (880:880:880)) - (PORT datab (1011:1011:1011) (1050:1050:1050)) - (PORT datac (912:912:912) (952:952:952)) - (PORT datad (1082:1082:1082) (1086:1086:1086)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~4) - (DELAY - (ABSOLUTE - (PORT dataa (938:938:938) (980:980:980)) - (PORT datab (180:180:180) (212:212:212)) - (PORT datac (1152:1152:1152) (1191:1191:1191)) - (PORT datad (973:973:973) (1014:1014:1014)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4) - (DELAY - (ABSOLUTE - (PORT datab (1410:1410:1410) (1479:1479:1479)) - (PORT datac (1389:1389:1389) (1444:1444:1444)) - (PORT datad (1204:1204:1204) (1168:1168:1168)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~10) - (DELAY - (ABSOLUTE - (PORT dataa (741:741:741) (740:740:740)) - (PORT datab (799:799:799) (766:766:766)) - (PORT datac (1149:1149:1149) (1124:1124:1124)) - (PORT datad (159:159:159) (181:181:181)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1298:1298:1298) (1298:1298:1298)) - (PORT datab (1920:1920:1920) (1910:1910:1910)) - (PORT datac (776:776:776) (769:769:769)) - (PORT datad (734:734:734) (710:710:710)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal48\~0) - (DELAY - (ABSOLUTE - (PORT dataa (803:803:803) (857:857:857)) - (PORT datab (1584:1584:1584) (1610:1610:1610)) - (PORT datac (1047:1047:1047) (1029:1029:1029)) - (PORT datad (606:606:606) (621:621:621)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf2_we) - (DELAY - (ABSOLUTE - (PORT dataa (857:857:857) (892:892:892)) - (PORT datab (833:833:833) (876:876:876)) - (PORT datac (874:874:874) (902:902:902)) - (PORT datad (1198:1198:1198) (1213:1213:1213)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~41) - (DELAY - (ABSOLUTE - (PORT dataa (1149:1149:1149) (1212:1212:1212)) - (PORT datab (910:910:910) (938:938:938)) - (PORT datac (187:187:187) (223:223:223)) - (PORT datad (1100:1100:1100) (1133:1133:1133)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1710:1710:1710) (1758:1758:1758)) - (PORT datab (1197:1197:1197) (1242:1242:1242)) - (PORT datac (1863:1863:1863) (1898:1898:1898)) - (PORT datad (776:776:776) (751:751:751)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1116:1116:1116) (1130:1130:1130)) - (PORT datab (935:935:935) (959:959:959)) - (PORT datac (573:573:573) (592:592:592)) - (PORT datad (1081:1081:1081) (1058:1058:1058)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~19) - (DELAY - (ABSOLUTE - (PORT dataa (815:815:815) (829:829:829)) - (PORT datab (980:980:980) (1012:1012:1012)) - (PORT datac (534:534:534) (541:541:541)) - (PORT datad (1010:1010:1010) (990:990:990)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_iorw\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1486:1486:1486) (1597:1597:1597)) - (PORT datab (1406:1406:1406) (1486:1486:1486)) - (PORT datac (1570:1570:1570) (1623:1623:1623)) - (PORT datad (1338:1338:1338) (1358:1358:1358)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1559:1559:1559) (1557:1557:1557)) - (PORT datab (1417:1417:1417) (1466:1466:1466)) - (PORT datac (875:875:875) (902:902:902)) - (PORT datad (1069:1069:1069) (1109:1109:1109)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~20) - (DELAY - (ABSOLUTE - (PORT dataa (547:547:547) (564:564:564)) - (PORT datab (861:861:861) (862:862:862)) - (PORT datac (878:878:878) (906:906:906)) - (PORT datad (159:159:159) (181:181:181)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1509:1509:1509) (1553:1553:1553)) - (PORT datab (986:986:986) (1053:1053:1053)) - (PORT datac (1675:1675:1675) (1745:1745:1745)) - (PORT datad (871:871:871) (912:912:912)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1145:1145:1145) (1159:1159:1159)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (889:889:889) (916:916:916)) - (PORT datad (840:840:840) (871:871:871)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1245:1245:1245) (1268:1268:1268)) - (PORT datab (907:907:907) (938:938:938)) - (PORT datac (544:544:544) (545:545:545)) - (PORT datad (586:586:586) (604:604:604)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal20\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1846:1846:1846) (1909:1909:1909)) - (PORT datab (1409:1409:1409) (1459:1459:1459)) - (PORT datac (201:201:201) (245:245:245)) - (PORT datad (1019:1019:1019) (1030:1030:1030)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal68\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1485:1485:1485) (1596:1596:1596)) - (PORT datab (1407:1407:1407) (1486:1486:1486)) - (PORT datac (1569:1569:1569) (1622:1622:1622)) - (PORT datad (1338:1338:1338) (1358:1358:1358)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~14) - (DELAY - (ABSOLUTE - (PORT dataa (859:859:859) (890:890:890)) - (PORT datab (1324:1324:1324) (1342:1342:1342)) - (PORT datac (1230:1230:1230) (1288:1288:1288)) - (PORT datad (1439:1439:1439) (1489:1489:1489)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~13) - (DELAY - (ABSOLUTE - (PORT dataa (641:641:641) (643:643:643)) - (PORT datab (1512:1512:1512) (1464:1464:1464)) - (PORT datac (1211:1211:1211) (1179:1179:1179)) - (PORT datad (1329:1329:1329) (1380:1380:1380)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1465:1465:1465) (1527:1527:1527)) - (PORT datab (1258:1258:1258) (1314:1314:1314)) - (PORT datac (1072:1072:1072) (1074:1074:1074)) - (PORT datad (764:764:764) (745:745:745)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~11) - (DELAY - (ABSOLUTE - (PORT dataa (624:624:624) (652:652:652)) - (PORT datab (917:917:917) (953:953:953)) - (PORT datac (993:993:993) (1090:1090:1090)) - (PORT datad (158:158:158) (178:178:178)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~11) - (DELAY - (ABSOLUTE - (PORT dataa (2092:2092:2092) (2170:2170:2170)) - (PORT datab (780:780:780) (796:796:796)) - (PORT datac (1947:1947:1947) (1965:1965:1965)) - (PORT datad (609:609:609) (634:634:634)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~10) - (DELAY - (ABSOLUTE - (PORT dataa (856:856:856) (891:891:891)) - (PORT datab (910:910:910) (942:942:942)) - (PORT datac (1321:1321:1321) (1340:1340:1340)) - (PORT datad (1414:1414:1414) (1436:1436:1436)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~8) - (DELAY - (ABSOLUTE - (PORT dataa (604:604:604) (611:611:611)) - (PORT datab (412:412:412) (427:427:427)) - (PORT datac (181:181:181) (215:215:215)) - (PORT datad (1303:1303:1303) (1297:1297:1297)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~9) - (DELAY - (ABSOLUTE - (PORT dataa (598:598:598) (580:580:580)) - (PORT datab (907:907:907) (935:935:935)) - (PORT datac (817:817:817) (816:816:816)) - (PORT datad (754:754:754) (757:757:757)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~12) - (DELAY - (ABSOLUTE - (PORT dataa (348:348:348) (352:352:352)) - (PORT datab (307:307:307) (325:325:325)) - (PORT datac (154:154:154) (184:184:184)) - (PORT datad (159:159:159) (179:179:179)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~11) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (240:240:240)) - (PORT datab (206:206:206) (245:245:245)) - (PORT datac (181:181:181) (216:216:216)) - (PORT datad (184:184:184) (209:209:209)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~12) - (DELAY - (ABSOLUTE - (PORT dataa (583:583:583) (584:584:584)) - (PORT datab (1311:1311:1311) (1349:1349:1349)) - (PORT datac (579:579:579) (584:584:584)) - (PORT datad (1507:1507:1507) (1522:1522:1522)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~6) - (DELAY - (ABSOLUTE - (PORT dataa (617:617:617) (631:631:631)) - (PORT datab (917:917:917) (951:951:951)) - (PORT datac (993:993:993) (1088:1088:1088)) - (PORT datad (2123:2123:2123) (2118:2118:2118)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~7) - (DELAY - (ABSOLUTE - (PORT dataa (859:859:859) (890:890:890)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (320:320:320) (331:331:331)) - (PORT datad (2124:2124:2124) (2121:2121:2121)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_ir_we\~4) (DELAY (ABSOLUTE - (PORT datab (976:976:976) (1054:1054:1054)) - (PORT datac (1345:1345:1345) (1372:1372:1372)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1290:1290:1290) (1309:1309:1309)) - (PORT datab (882:882:882) (907:907:907)) - (PORT datac (958:958:958) (1025:1025:1025)) - (PORT datad (1298:1298:1298) (1305:1305:1305)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (898:898:898) (934:934:934)) - (PORT datab (1321:1321:1321) (1331:1331:1331)) - (PORT datac (889:889:889) (919:919:919)) - (PORT datad (178:178:178) (201:201:201)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1038:1038:1038) (1018:1018:1018)) - (PORT datab (1093:1093:1093) (1100:1100:1100)) - (PORT datac (609:609:609) (638:638:638)) - (PORT datad (810:810:810) (832:832:832)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~13) - (DELAY - (ABSOLUTE - (PORT dataa (554:554:554) (555:555:555)) - (PORT datac (539:539:539) (529:529:529)) - (PORT datad (491:491:491) (485:485:485)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~14) - (DELAY - (ABSOLUTE - (PORT dataa (226:226:226) (275:275:275)) - (PORT datab (1147:1147:1147) (1139:1139:1139)) - (PORT datac (1072:1072:1072) (1085:1085:1085)) - (PORT datad (160:160:160) (182:182:182)) + (PORT dataa (1107:1107:1107) (1176:1176:1176)) + (PORT datad (1038:1038:1038) (1050:1050:1050)) (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~15) + (INSTANCE z80_\|execute_\|ctl_state_iy_set\~2) (DELAY (ABSOLUTE - (PORT dataa (816:816:816) (838:838:838)) - (PORT datab (791:791:791) (782:782:782)) - (PORT datac (320:320:320) (326:326:326)) - (PORT datad (178:178:178) (200:200:200)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_66_oe\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1843:1843:1843) (1913:1913:1913)) - (PORT datab (830:830:830) (855:855:855)) - (PORT datac (198:198:198) (243:243:243)) - (PORT datad (1301:1301:1301) (1303:1303:1303)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel_pla11M1T1_11) - (DELAY - (ABSOLUTE - (PORT dataa (1673:1673:1673) (1743:1743:1743)) - (PORT datab (1490:1490:1490) (1552:1552:1552)) - (PORT datad (1304:1304:1304) (1336:1336:1336)) - (IOPATH dataa combout (267:267:267) (273:273:273)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1897:1897:1897) (1897:1897:1897)) - (PORT datab (869:869:869) (915:915:915)) - (PORT datac (1005:1005:1005) (1022:1022:1022)) - (PORT datad (848:848:848) (890:890:890)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1248:1248:1248) (1215:1215:1215)) - (PORT datab (1074:1074:1074) (1125:1125:1125)) - (PORT datac (1366:1366:1366) (1365:1365:1365)) - (PORT datad (1353:1353:1353) (1375:1375:1375)) + (PORT dataa (1587:1587:1587) (1597:1597:1597)) + (PORT datab (1946:1946:1946) (2023:2023:2023)) + (PORT datac (659:659:659) (718:718:718)) + (PORT datad (358:358:358) (369:369:369)) (IOPATH dataa combout (273:273:273) (269:269:269)) (IOPATH datab combout (295:295:295) (294:294:294)) (IOPATH datac combout (218:218:218) (216:216:216)) @@ -4286,28 +998,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero) + (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_16) (DELAY (ABSOLUTE - (PORT dataa (1068:1068:1068) (1064:1064:1064)) - (PORT datab (202:202:202) (242:242:242)) - (PORT datac (157:157:157) (187:187:187)) - (PORT datad (780:780:780) (768:768:768)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[2\]) - (DELAY - (ABSOLUTE - (PORT datab (888:888:888) (913:913:913)) - (PORT datac (547:547:547) (540:540:540)) - (PORT datad (628:628:628) (648:648:648)) + (PORT datab (1064:1064:1064) (1111:1111:1111)) + (PORT datac (215:215:215) (282:282:282)) + (PORT datad (830:830:830) (884:884:884)) (IOPATH datab combout (308:308:308) (300:300:300)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -4315,26 +1011,50 @@ ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|ena\~0) + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_T5_ff) (DELAY (ABSOLUTE - (PORT datac (858:858:858) (882:882:882)) - (PORT datad (633:633:633) (656:656:656)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (PORT clk (1337:1337:1337) (1354:1354:1354)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1380:1380:1380) (1352:1352:1352)) + (PORT ena (1325:1325:1325) (1300:1300:1300)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_ixiy_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (792:792:792) (795:795:795)) + (PORT datab (1946:1946:1946) (2026:2026:2026)) + (PORT datac (1549:1549:1549) (1566:1566:1566)) + (PORT datad (828:828:828) (913:913:913)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_high\[2\]) + (INSTANCE z80_\|decode_state_\|DFFE_instIY1) (DELAY (ABSOLUTE - (PORT clk (1350:1350:1350) (1357:1357:1357)) + (PORT clk (1346:1346:1346) (1368:1368:1368)) (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1382:1382:1382) (1354:1354:1354)) (PORT ena (745:745:745) (751:751:751)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) ) (TIMINGCHECK @@ -4344,213 +1064,25 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_lq) + (INSTANCE z80_\|decode_state_\|use_ixiy) (DELAY (ABSOLUTE - (PORT dataa (927:927:927) (959:959:959)) - (PORT datab (655:655:655) (689:689:689)) - (PORT datac (837:837:837) (839:839:839)) - (PORT datad (1600:1600:1600) (1674:1674:1674)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (308:308:308) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (PORT datab (452:452:452) (522:522:522)) + (PORT datad (414:414:414) (470:470:470)) + (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~10) + (INSTANCE z80_\|execute_\|ixy_d\~4) (DELAY (ABSOLUTE - (PORT dataa (1376:1376:1376) (1454:1454:1454)) - (PORT datab (1348:1348:1348) (1415:1415:1415)) - (PORT datac (1702:1702:1702) (1704:1704:1704)) - (PORT datad (376:376:376) (398:398:398)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1126:1126:1126) (1166:1166:1166)) - (PORT datac (873:873:873) (903:903:903)) - (PORT datad (1115:1115:1115) (1158:1158:1158)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1128:1128:1128) (1145:1145:1145)) - (PORT datab (1319:1319:1319) (1327:1327:1327)) - (PORT datac (1020:1020:1020) (994:994:994)) - (PORT datad (1237:1237:1237) (1210:1210:1210)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~22) - (DELAY - (ABSOLUTE - (PORT datab (864:864:864) (860:860:860)) - (PORT datac (496:496:496) (486:486:486)) - (PORT datad (157:157:157) (177:177:177)) + (PORT datab (932:932:932) (961:961:961)) + (PORT datac (1374:1374:1374) (1458:1458:1458)) + (PORT datad (867:867:867) (898:898:898)) (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~16) - (DELAY - (ABSOLUTE - (PORT dataa (925:925:925) (958:958:958)) - (PORT datab (655:655:655) (689:689:689)) - (PORT datac (835:835:835) (838:838:838)) - (PORT datad (1599:1599:1599) (1672:1672:1672)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1256:1256:1256) (1253:1253:1253)) - (PORT datab (843:843:843) (852:852:852)) - (PORT datad (569:569:569) (580:580:580)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla65npla52M1T4_4) - (DELAY - (ABSOLUTE - (PORT dataa (804:804:804) (816:816:816)) - (PORT datab (1350:1350:1350) (1391:1391:1391)) - (PORT datac (1212:1212:1212) (1289:1289:1289)) - (PORT datad (2057:2057:2057) (2079:2079:2079)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\~36) - (DELAY - (ABSOLUTE - (PORT dataa (2171:2171:2171) (2222:2222:2222)) - (PORT datab (828:828:828) (853:853:853)) - (PORT datac (345:345:345) (360:360:360)) - (PORT datad (1356:1356:1356) (1393:1393:1393)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~4) - (DELAY - (ABSOLUTE - (PORT dataa (192:192:192) (234:234:234)) - (PORT datab (215:215:215) (256:256:256)) - (PORT datac (780:780:780) (771:771:771)) - (PORT datad (525:525:525) (507:507:507)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~5) - (DELAY - (ABSOLUTE - (PORT datac (2248:2248:2248) (2394:2394:2394)) - (PORT datad (1842:1842:1842) (1860:1860:1860)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1349:1349:1349) (1371:1371:1371)) - (PORT datab (775:775:775) (797:797:797)) - (PORT datac (849:849:849) (884:884:884)) - (PORT datad (606:606:606) (629:629:629)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (308:308:308) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1321:1321:1321) (1320:1320:1320)) - (PORT datab (1246:1246:1246) (1217:1217:1217)) - (PORT datac (792:792:792) (789:789:789)) - (PORT datad (754:754:754) (719:719:719)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~33) - (DELAY - (ABSOLUTE - (PORT dataa (1015:1015:1015) (999:999:999)) - (PORT datab (2388:2388:2388) (2382:2382:2382)) - (PORT datac (1421:1421:1421) (1511:1511:1511)) - (PORT datad (1582:1582:1582) (1635:1635:1635)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -4558,202 +1090,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~20) + (INSTANCE z80_\|execute_\|ixy_d\~11) (DELAY (ABSOLUTE - (PORT datac (187:187:187) (225:225:225)) - (PORT datad (190:190:190) (216:216:216)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~23) - (DELAY - (ABSOLUTE - (PORT dataa (1125:1125:1125) (1147:1147:1147)) - (PORT datab (1182:1182:1182) (1237:1237:1237)) - (PORT datac (1617:1617:1617) (1628:1628:1628)) - (PORT datad (783:783:783) (768:768:768)) - (IOPATH dataa combout (307:307:307) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~24) - (DELAY - (ABSOLUTE - (PORT dataa (378:378:378) (378:378:378)) - (PORT datab (376:376:376) (377:377:377)) - (PORT datac (346:346:346) (350:350:350)) - (PORT datad (183:183:183) (220:220:220)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~25) - (DELAY - (ABSOLUTE - (PORT dataa (1369:1369:1369) (1400:1400:1400)) - (PORT datab (1173:1173:1173) (1231:1231:1231)) - (PORT datac (824:824:824) (841:841:841)) - (PORT datad (1076:1076:1076) (1060:1060:1060)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~34) - (DELAY - (ABSOLUTE - (PORT dataa (651:651:651) (676:676:676)) - (PORT datab (2586:2586:2586) (2576:2576:2576)) - (PORT datac (1203:1203:1203) (1279:1279:1279)) - (PORT datad (528:528:528) (521:521:521)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low) - (DELAY - (ABSOLUTE - (PORT dataa (816:816:816) (813:813:813)) - (PORT datab (202:202:202) (236:236:236)) - (PORT datac (175:175:175) (215:215:215)) - (PORT datad (167:167:167) (193:193:193)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~40) - (DELAY - (ABSOLUTE - (PORT dataa (597:597:597) (619:619:619)) - (PORT datab (199:199:199) (233:233:233)) - (PORT datac (539:539:539) (532:532:532)) - (PORT datad (1313:1313:1313) (1331:1331:1331)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~37) - (DELAY - (ABSOLUTE - (PORT dataa (1275:1275:1275) (1269:1269:1269)) - (PORT datab (1702:1702:1702) (1643:1643:1643)) - (PORT datac (1043:1043:1043) (1045:1045:1045)) - (PORT datad (1615:1615:1615) (1615:1615:1615)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~39) - (DELAY - (ABSOLUTE - (PORT dataa (1738:1738:1738) (1736:1736:1736)) - (PORT datab (181:181:181) (213:213:213)) - (PORT datac (1052:1052:1052) (1081:1081:1081)) - (PORT datad (560:560:560) (567:567:567)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~46) - (DELAY - (ABSOLUTE - (PORT dataa (586:586:586) (586:586:586)) - (PORT datab (958:958:958) (1002:1002:1002)) - (PORT datac (817:817:817) (816:816:816)) - (PORT datad (1479:1479:1479) (1546:1546:1546)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~42) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (336:336:336) (355:355:355)) - (PORT datac (155:155:155) (184:184:184)) - (PORT datad (966:966:966) (920:920:920)) + (PORT dataa (1393:1393:1393) (1449:1449:1449)) + (PORT datab (2478:2478:2478) (2556:2556:2556)) + (PORT datac (1213:1213:1213) (1256:1256:1256)) + (PORT datad (806:806:806) (799:799:799)) (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1322:1322:1322) (1335:1335:1335)) - (PORT datab (1318:1318:1318) (1333:1333:1333)) - (PORT datac (568:568:568) (566:566:566)) - (PORT datad (838:838:838) (870:870:870)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~45) - (DELAY - (ABSOLUTE - (PORT dataa (1510:1510:1510) (1554:1554:1554)) - (PORT datab (182:182:182) (216:216:216)) - (PORT datac (1675:1675:1675) (1745:1745:1745)) - (PORT datad (845:845:845) (877:877:877)) - (IOPATH dataa combout (287:287:287) (280:280:280)) (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -4762,1387 +1106,23 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~22) + (INSTANCE z80_\|execute_\|ixy_d\~9) (DELAY (ABSOLUTE - (PORT dataa (1322:1322:1322) (1335:1335:1335)) - (PORT datab (1317:1317:1317) (1334:1334:1334)) - (PORT datac (961:961:961) (1026:1026:1026)) - (PORT datad (160:160:160) (182:182:182)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~23) - (DELAY - (ABSOLUTE - (PORT dataa (1666:1666:1666) (1679:1679:1679)) - (PORT datab (310:310:310) (325:325:325)) - (PORT datac (958:958:958) (1026:1026:1026)) - (PORT datad (1099:1099:1099) (1115:1115:1115)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~24) - (DELAY - (ABSOLUTE - (PORT dataa (1310:1310:1310) (1309:1309:1309)) - (PORT datab (1319:1319:1319) (1327:1327:1327)) - (PORT datac (156:156:156) (187:187:187)) - (PORT datad (867:867:867) (906:906:906)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~25) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (219:219:219)) - (PORT datab (908:908:908) (942:942:942)) - (PORT datac (997:997:997) (973:973:973)) - (PORT datad (1098:1098:1098) (1114:1114:1114)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (308:308:308) (294:294:294)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1816:1816:1816) (1865:1865:1865)) - (PORT datab (1699:1699:1699) (1638:1638:1638)) - (PORT datac (1040:1040:1040) (1043:1043:1043)) - (PORT datad (1843:1843:1843) (1917:1917:1917)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (308:308:308) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~26) - (DELAY - (ABSOLUTE - (PORT dataa (359:359:359) (361:361:361)) - (PORT datab (1699:1699:1699) (1639:1639:1639)) - (PORT datac (1465:1465:1465) (1441:1441:1441)) - (PORT datad (169:169:169) (199:199:199)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~27) - (DELAY - (ABSOLUTE - (PORT dataa (584:584:584) (612:612:612)) - (PORT datab (919:919:919) (961:961:961)) - (PORT datac (1200:1200:1200) (1207:1207:1207)) - (PORT datad (743:743:743) (733:733:733)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~28) - (DELAY - (ABSOLUTE - (PORT dataa (584:584:584) (599:599:599)) - (PORT datac (980:980:980) (963:963:963)) - (PORT datad (158:158:158) (178:178:178)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~10) - (DELAY - (ABSOLUTE - (PORT dataa (900:900:900) (934:934:934)) - (PORT datab (1320:1320:1320) (1328:1328:1328)) - (PORT datac (892:892:892) (915:915:915)) - (PORT datad (1102:1102:1102) (1119:1119:1119)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (308:308:308) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~11) - (DELAY - (ABSOLUTE - (PORT dataa (364:364:364) (366:366:366)) - (PORT datab (194:194:194) (232:232:232)) - (PORT datac (331:331:331) (342:342:342)) - (PORT datad (324:324:324) (326:326:326)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~32) - (DELAY - (ABSOLUTE - (PORT datab (598:598:598) (600:600:600)) - (PORT datac (802:802:802) (819:819:819)) - (PORT datad (166:166:166) (189:189:189)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~33) - (DELAY - (ABSOLUTE - (PORT dataa (565:565:565) (547:547:547)) - (PORT datab (825:825:825) (812:812:812)) - (PORT datac (174:174:174) (206:206:206)) - (PORT datad (157:157:157) (177:177:177)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~0) - (DELAY - (ABSOLUTE - (PORT dataa (762:762:762) (760:760:760)) - (PORT datab (634:634:634) (663:663:663)) - (PORT datac (850:850:850) (886:886:886)) - (PORT datad (751:751:751) (757:757:757)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~1) - (DELAY - (ABSOLUTE - (PORT datab (805:805:805) (798:798:798)) - (PORT datad (757:757:757) (738:738:738)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~12) - (DELAY - (ABSOLUTE - (PORT datab (195:195:195) (234:234:234)) - (PORT datac (332:332:332) (342:342:342)) - (PORT datad (324:324:324) (326:326:326)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~47) - (DELAY - (ABSOLUTE - (PORT dataa (1509:1509:1509) (1555:1555:1555)) - (PORT datab (1686:1686:1686) (1724:1724:1724)) - (PORT datac (1674:1674:1674) (1748:1748:1748)) - (PORT datad (873:873:873) (896:896:896)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~34) - (DELAY - (ABSOLUTE - (PORT dataa (1322:1322:1322) (1336:1336:1336)) - (PORT datab (1319:1319:1319) (1328:1328:1328)) - (PORT datac (892:892:892) (920:920:920)) - (PORT datad (159:159:159) (181:181:181)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~35) - (DELAY - (ABSOLUTE - (PORT dataa (1667:1667:1667) (1681:1681:1681)) - (PORT datab (918:918:918) (948:948:948)) - (PORT datac (297:297:297) (304:304:304)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~36) - (DELAY - (ABSOLUTE - (PORT dataa (617:617:617) (616:616:616)) - (PORT datab (559:559:559) (561:561:561)) - (PORT datac (762:762:762) (744:744:744)) - (PORT datad (314:314:314) (313:313:313)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~43) - (DELAY - (ABSOLUTE - (PORT dataa (181:181:181) (218:218:218)) - (PORT datab (182:182:182) (215:215:215)) - (PORT datac (155:155:155) (186:186:186)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_lo\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1188:1188:1188) (1198:1198:1198)) - (PORT datab (909:909:909) (990:990:990)) - (PORT datac (993:993:993) (1063:1063:1063)) - (PORT datad (891:891:891) (962:962:962)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1358:1358:1358) (1324:1324:1324)) - (PORT datab (1281:1281:1281) (1252:1252:1252)) - (PORT datac (1502:1502:1502) (1479:1479:1479)) - (PORT datad (1157:1157:1157) (1199:1199:1199)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla57M1T4_4) - (DELAY - (ABSOLUTE - (PORT dataa (1120:1120:1120) (1110:1110:1110)) - (PORT datab (966:966:966) (1033:1033:1033)) - (PORT datad (1249:1249:1249) (1347:1347:1347)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_oe\~1) - (DELAY - (ABSOLUTE - (PORT dataa (621:621:621) (656:656:656)) - (PORT datab (922:922:922) (918:918:918)) - (PORT datac (517:517:517) (502:502:502)) - (PORT datad (202:202:202) (225:225:225)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (676:676:676) (715:715:715)) - (PORT datab (871:871:871) (917:917:917)) - (PORT datac (1005:1005:1005) (1023:1023:1023)) - (PORT datad (843:843:843) (885:885:885)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1132:1132:1132) (1172:1172:1172)) - (PORT datab (203:203:203) (245:245:245)) - (PORT datac (2166:2166:2166) (2200:2200:2200)) - (PORT datad (157:157:157) (177:177:177)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal8\~0) - (DELAY - (ABSOLUTE - (PORT datab (1924:1924:1924) (1977:1977:1977)) - (PORT datac (1577:1577:1577) (1617:1617:1617)) - (PORT datad (1064:1064:1064) (1115:1115:1115)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1336:1336:1336) (1342:1342:1342)) - (PORT datab (1328:1328:1328) (1302:1302:1302)) - (PORT datac (772:772:772) (771:771:771)) - (PORT datad (364:364:364) (378:378:378)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~4) - (DELAY - (ABSOLUTE - (PORT dataa (800:800:800) (804:804:804)) - (PORT datab (1094:1094:1094) (1088:1088:1088)) - (PORT datac (908:908:908) (931:931:931)) - (PORT datad (900:900:900) (934:934:934)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1847:1847:1847) (1918:1918:1918)) - (PORT datab (415:415:415) (432:432:432)) - (PORT datac (920:920:920) (954:954:954)) - (PORT datad (834:834:834) (846:846:846)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal11\~1) - (DELAY - (ABSOLUTE - (PORT datac (1462:1462:1462) (1567:1567:1567)) - (PORT datad (1383:1383:1383) (1455:1455:1455)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla12M3T1_2) - (DELAY - (ABSOLUTE - (PORT dataa (882:882:882) (927:927:927)) - (PORT datab (1103:1103:1103) (1088:1088:1088)) - (PORT datac (1796:1796:1796) (1829:1829:1829)) - (PORT datad (596:596:596) (615:615:615)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~10) - (DELAY - (ABSOLUTE - (PORT dataa (181:181:181) (217:217:217)) - (PORT datab (573:573:573) (590:590:590)) - (PORT datac (1558:1558:1558) (1610:1610:1610)) - (PORT datad (578:578:578) (592:592:592)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1386:1386:1386) (1425:1425:1425)) - (PORT datab (329:329:329) (353:353:353)) - (PORT datac (1936:1936:1936) (1950:1950:1950)) - (PORT datad (552:552:552) (533:533:533)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla77M1T1_3) - (DELAY - (ABSOLUTE - (PORT dataa (675:675:675) (715:715:715)) - (PORT datab (870:870:870) (912:912:912)) - (PORT datac (1004:1004:1004) (1021:1021:1021)) - (PORT datad (845:845:845) (889:889:889)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel_pla82M1T1_16) - (DELAY - (ABSOLUTE - (PORT dataa (1359:1359:1359) (1390:1390:1390)) - (PORT datab (1129:1129:1129) (1189:1189:1189)) - (PORT datac (1349:1349:1349) (1357:1357:1357)) - (PORT datad (1052:1052:1052) (1047:1047:1047)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1699:1699:1699) (1727:1727:1727)) - (PORT datab (1918:1918:1918) (1966:1966:1966)) - (PORT datac (1236:1236:1236) (1200:1200:1200)) - (PORT datad (1859:1859:1859) (1904:1904:1904)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1032:1032:1032) (1089:1089:1089)) - (PORT datab (602:602:602) (604:604:604)) - (PORT datac (1124:1124:1124) (1159:1159:1159)) - (PORT datad (553:553:553) (559:559:559)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel\[0\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1048:1048:1048) (1038:1038:1038)) - (PORT datab (786:786:786) (772:772:772)) - (PORT datad (534:534:534) (525:525:525)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~2) - (DELAY - (ABSOLUTE - (PORT datac (1624:1624:1624) (1672:1672:1672)) - (PORT datad (1455:1455:1455) (1524:1524:1524)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~25) - (DELAY - (ABSOLUTE - (PORT dataa (940:940:940) (967:967:967)) - (PORT datab (959:959:959) (994:994:994)) - (PORT datac (978:978:978) (1009:1009:1009)) - (PORT datad (585:585:585) (593:593:593)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1467:1467:1467) (1544:1544:1544)) - (PORT datab (188:188:188) (223:223:223)) - (PORT datac (978:978:978) (1009:1009:1009)) - (PORT datad (1658:1658:1658) (1738:1738:1738)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1122:1122:1122) (1132:1132:1132)) - (PORT datab (639:639:639) (634:634:634)) - (PORT datac (1175:1175:1175) (1251:1251:1251)) - (PORT datad (1462:1462:1462) (1539:1539:1539)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~48) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (239:239:239)) - (PORT datab (194:194:194) (234:234:234)) - (PORT datac (1174:1174:1174) (1251:1251:1251)) - (PORT datad (1465:1465:1465) (1543:1543:1543)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1133:1133:1133) (1133:1133:1133)) - (PORT datab (1529:1529:1529) (1476:1476:1476)) - (PORT datac (729:729:729) (713:713:713)) - (PORT datad (541:541:541) (543:543:543)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (594:594:594) (597:597:597)) - (PORT datab (610:610:610) (626:626:626)) - (PORT datac (627:627:627) (658:658:658)) - (PORT datad (740:740:740) (792:792:792)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~17) - (DELAY - (ABSOLUTE - (PORT dataa (917:917:917) (963:963:963)) - (PORT datab (1558:1558:1558) (1560:1560:1560)) - (PORT datac (1455:1455:1455) (1513:1513:1513)) - (PORT datad (889:889:889) (912:912:912)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1194:1194:1194) (1204:1204:1204)) - (PORT datab (854:854:854) (864:864:864)) - (PORT datac (905:905:905) (931:931:931)) - (PORT datad (1082:1082:1082) (1058:1058:1058)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~6) - (DELAY - (ABSOLUTE - (PORT dataa (334:334:334) (351:351:351)) - (PORT datab (1367:1367:1367) (1350:1350:1350)) - (PORT datac (995:995:995) (995:995:995)) - (PORT datad (1254:1254:1254) (1233:1233:1233)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~10) - (DELAY - (ABSOLUTE - (PORT dataa (335:335:335) (353:353:353)) - (PORT datab (216:216:216) (250:250:250)) - (PORT datac (969:969:969) (989:989:989)) - (PORT datad (1280:1280:1280) (1284:1284:1284)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla21M2T3_4) - (DELAY - (ABSOLUTE - (PORT dataa (803:803:803) (806:806:806)) - (PORT datab (342:342:342) (353:353:353)) - (PORT datac (605:605:605) (626:626:626)) - (PORT datad (771:771:771) (793:793:793)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~7) - (DELAY - (ABSOLUTE - (PORT dataa (665:665:665) (727:727:727)) - (PORT datab (863:863:863) (905:905:905)) - (PORT datac (889:889:889) (926:926:926)) - (PORT datad (176:176:176) (197:197:197)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1343:1343:1343) (1389:1389:1389)) - (PORT datab (571:571:571) (573:573:573)) - (PORT datac (1107:1107:1107) (1146:1146:1146)) - (PORT datad (778:778:778) (761:761:761)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (249:249:249)) - (PORT datab (190:190:190) (226:226:226)) - (PORT datac (548:548:548) (534:534:534)) - (PORT datad (797:797:797) (784:784:784)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1112:1112:1112) (1118:1118:1118)) - (PORT datab (888:888:888) (925:925:925)) - (PORT datac (963:963:963) (1020:1020:1020)) - (PORT datad (1328:1328:1328) (1332:1332:1332)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~7) - (DELAY - (ABSOLUTE - (PORT dataa (993:993:993) (1052:1052:1052)) - (PORT datab (893:893:893) (931:931:931)) - (PORT datac (292:292:292) (301:301:301)) - (PORT datad (588:588:588) (597:597:597)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~4) - (DELAY - (ABSOLUTE - (PORT dataa (933:933:933) (981:981:981)) - (PORT datab (1278:1278:1278) (1267:1267:1267)) - (PORT datac (1084:1084:1084) (1086:1086:1086)) - (PORT datad (1118:1118:1118) (1133:1133:1133)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~5) - (DELAY - (ABSOLUTE - (PORT dataa (189:189:189) (229:229:229)) - (PORT datab (1155:1155:1155) (1173:1173:1173)) - (PORT datac (894:894:894) (943:943:943)) - (PORT datad (585:585:585) (594:594:594)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla20M1T5_5) - (DELAY - (ABSOLUTE - (PORT dataa (805:805:805) (809:809:809)) - (PORT datab (1331:1331:1331) (1306:1306:1306)) - (PORT datac (1553:1553:1553) (1554:1554:1554)) - (PORT datad (1898:1898:1898) (1969:1969:1969)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (572:572:572) (574:574:574)) - (PORT datab (189:189:189) (226:226:226)) - (PORT datac (1291:1291:1291) (1332:1332:1332)) - (PORT datad (1314:1314:1314) (1311:1311:1311)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1677:1677:1677) (1730:1730:1730)) - (PORT datab (780:780:780) (772:772:772)) - (PORT datac (774:774:774) (776:776:776)) - (PORT datad (1897:1897:1897) (1970:1970:1970)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~1) - (DELAY - (ABSOLUTE - (PORT dataa (775:775:775) (754:754:754)) - (PORT datab (731:731:731) (724:724:724)) - (PORT datac (154:154:154) (184:184:184)) - (PORT datad (159:159:159) (179:179:179)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~2) - (DELAY - (ABSOLUTE - (PORT dataa (326:326:326) (339:339:339)) - (PORT datab (200:200:200) (233:233:233)) - (PORT datac (175:175:175) (207:207:207)) - (PORT datad (506:506:506) (496:496:496)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (880:880:880) (899:899:899)) - (PORT datab (807:807:807) (798:798:798)) - (PORT datac (1556:1556:1556) (1622:1622:1622)) - (PORT datad (1087:1087:1087) (1096:1096:1096)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1253:1253:1253) (1205:1205:1205)) - (PORT datab (1072:1072:1072) (1087:1087:1087)) - (PORT datac (1037:1037:1037) (1010:1010:1010)) - (PORT datad (620:620:620) (635:635:635)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1101:1101:1101) (1124:1124:1124)) - (PORT datac (549:549:549) (548:548:548)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (1096:1096:1096) (1119:1119:1119)) - (PORT datab (603:603:603) (603:603:603)) - (PORT datac (174:174:174) (223:223:223)) - (PORT datad (571:571:571) (570:570:570)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~7) - (DELAY - (ABSOLUTE - (PORT dataa (207:207:207) (248:248:248)) - (PORT datac (1939:1939:1939) (1948:1948:1948)) - (PORT datad (1345:1345:1345) (1382:1382:1382)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel_pla66npla53M1T1_15) - (DELAY - (ABSOLUTE - (PORT dataa (384:384:384) (411:411:411)) - (PORT datab (1066:1066:1066) (1075:1075:1075)) - (PORT datac (1350:1350:1350) (1358:1358:1358)) - (PORT datad (1016:1016:1016) (1032:1032:1032)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (991:991:991) (1047:1047:1047)) - (PORT datab (960:960:960) (1002:1002:1002)) - (PORT datac (1084:1084:1084) (1085:1085:1085)) - (PORT datad (1118:1118:1118) (1133:1133:1133)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~8) - (DELAY - (ABSOLUTE - (PORT dataa (828:828:828) (817:817:817)) - (PORT datab (606:606:606) (624:624:624)) - (PORT datac (1030:1030:1030) (994:994:994)) - (PORT datad (723:723:723) (705:705:705)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1040:1040:1040) (1029:1029:1029)) - (PORT datab (1420:1420:1420) (1483:1483:1483)) - (PORT datac (568:568:568) (595:595:595)) - (PORT datad (165:165:165) (190:190:190)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~4) - (DELAY - (ABSOLUTE - (PORT dataa (674:674:674) (703:703:703)) - (PORT datab (781:781:781) (795:795:795)) - (PORT datac (733:733:733) (731:731:731)) - (PORT datad (610:610:610) (634:634:634)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~9) - (DELAY - (ABSOLUTE - (PORT dataa (933:933:933) (981:981:981)) - (PORT datab (892:892:892) (930:930:930)) - (PORT datac (173:173:173) (203:203:203)) - (PORT datad (1328:1328:1328) (1329:1329:1329)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1192:1192:1192) (1254:1254:1254)) - (PORT datab (891:891:891) (929:929:929)) - (PORT datac (965:965:965) (1018:1018:1018)) - (PORT datad (1442:1442:1442) (1506:1506:1506)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~43) - (DELAY - (ABSOLUTE - (PORT dataa (1191:1191:1191) (1254:1254:1254)) - (PORT datab (1156:1156:1156) (1167:1167:1167)) - (PORT datac (894:894:894) (945:945:945)) - (PORT datad (1443:1443:1443) (1507:1507:1507)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~26) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (219:219:219)) - (PORT datac (161:161:161) (196:196:196)) - (PORT datad (165:165:165) (191:191:191)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (530:530:530) (517:517:517)) - (PORT datab (217:217:217) (259:259:259)) - (PORT datac (503:503:503) (491:491:491)) - (PORT datad (1341:1341:1341) (1348:1348:1348)) + (PORT dataa (1591:1591:1591) (1622:1622:1622)) + (PORT datac (2225:2225:2225) (2322:2322:2322)) (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~9) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (219:219:219)) - (PORT datab (1285:1285:1285) (1264:1264:1264)) - (PORT datac (533:533:533) (527:527:527)) - (PORT datad (559:559:559) (564:564:564)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~11) - (DELAY - (ABSOLUTE - (PORT dataa (621:621:621) (656:656:656)) - (PORT datab (1042:1042:1042) (1050:1050:1050)) - (PORT datac (894:894:894) (891:891:891)) - (PORT datad (1079:1079:1079) (1090:1090:1090)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~5) - (DELAY - (ABSOLUTE - (PORT dataa (853:853:853) (896:896:896)) - (PORT datab (883:883:883) (906:906:906)) - (PORT datac (1114:1114:1114) (1159:1159:1159)) - (PORT datad (355:355:355) (359:359:359)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1638:1638:1638) (1596:1596:1596)) - (PORT datab (1504:1504:1504) (1511:1511:1511)) - (PORT datac (1208:1208:1208) (1288:1288:1288)) - (PORT datad (1428:1428:1428) (1521:1521:1521)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1032:1032:1032) (1036:1036:1036)) - (PORT datab (970:970:970) (989:989:989)) - (PORT datac (876:876:876) (885:885:885)) - (PORT datad (764:764:764) (753:753:753)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~7) - (DELAY - (ABSOLUTE - (PORT dataa (902:902:902) (917:917:917)) - (PORT datab (644:644:644) (656:656:656)) - (PORT datac (191:191:191) (236:236:236)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~12) - (DELAY - (ABSOLUTE - (PORT dataa (791:791:791) (790:790:790)) - (PORT datab (602:602:602) (612:612:612)) - (PORT datac (814:814:814) (813:813:813)) - (PORT datad (759:759:759) (751:751:751)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~13) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (329:329:329) (355:355:355)) - (PORT datac (899:899:899) (931:931:931)) - (PORT datad (552:552:552) (532:532:532)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~14) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (239:239:239)) - (PORT datac (1584:1584:1584) (1557:1557:1557)) - (IOPATH dataa combout (329:329:329) (332:332:332)) (IOPATH datac combout (220:220:220) (216:216:216)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~24) + (INSTANCE z80_\|execute_\|ixy_d\~7) (DELAY (ABSOLUTE - (PORT dataa (220:220:220) (268:268:268)) - (PORT datab (1098:1098:1098) (1106:1106:1106)) - (PORT datac (1117:1117:1117) (1107:1107:1107)) - (PORT datad (521:521:521) (507:507:507)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (1031:1031:1031) (1039:1039:1039)) - (PORT datab (220:220:220) (265:265:265)) - (PORT datac (835:835:835) (838:838:838)) - (PORT datad (1812:1812:1812) (1811:1811:1811)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) + (PORT datac (1662:1662:1662) (1688:1688:1688)) + (PORT datad (882:882:882) (970:970:970)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -6150,1767 +1130,37 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~40) + (INSTANCE z80_\|execute_\|ixy_d\~6) (DELAY (ABSOLUTE - (PORT dataa (768:768:768) (752:752:752)) - (PORT datab (804:804:804) (790:790:790)) - (PORT datac (554:554:554) (548:548:548)) - (PORT datad (758:758:758) (736:736:736)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~53) - (DELAY - (ABSOLUTE - (PORT dataa (1996:1996:1996) (2051:2051:2051)) - (PORT datab (1617:1617:1617) (1676:1676:1676)) - (PORT datac (813:813:813) (805:805:805)) - (PORT datad (2159:2159:2159) (2213:2213:2213)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~8) - (DELAY - (ABSOLUTE - (PORT dataa (894:894:894) (933:933:933)) - (PORT datab (1942:1942:1942) (1959:1959:1959)) - (PORT datac (513:513:513) (510:510:510)) - (PORT datad (1825:1825:1825) (1841:1841:1841)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~54) - (DELAY - (ABSOLUTE - (PORT dataa (1648:1648:1648) (1706:1706:1706)) - (PORT datab (988:988:988) (1054:1054:1054)) - (PORT datac (889:889:889) (915:915:915)) - (PORT datad (1891:1891:1891) (1927:1927:1927)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1041:1041:1041) (1131:1131:1131)) - (PORT datab (1090:1090:1090) (1095:1095:1095)) - (PORT datac (564:564:564) (560:560:560)) - (PORT datad (2123:2123:2123) (2121:2121:2121)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~4) - (DELAY - (ABSOLUTE - (PORT dataa (915:915:915) (928:928:928)) - (PORT datab (1059:1059:1059) (1039:1039:1039)) - (PORT datac (321:321:321) (343:343:343)) - (PORT datad (576:576:576) (601:601:601)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~5) - (DELAY - (ABSOLUTE - (PORT dataa (806:806:806) (815:815:815)) - (PORT datac (775:775:775) (771:771:771)) - (PORT datad (485:485:485) (478:478:478)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~6) - (DELAY - (ABSOLUTE - (PORT dataa (215:215:215) (260:260:260)) - (PORT datab (223:223:223) (267:267:267)) - (PORT datac (1819:1819:1819) (1877:1877:1877)) - (PORT datad (184:184:184) (214:214:214)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~35) - (DELAY - (ABSOLUTE - (PORT dataa (1253:1253:1253) (1338:1338:1338)) - (PORT datab (1252:1252:1252) (1227:1227:1227)) - (PORT datac (806:806:806) (800:800:800)) - (PORT datad (1348:1348:1348) (1350:1350:1350)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (1021:1021:1021) (1092:1092:1092)) - (PORT datab (627:627:627) (671:671:671)) - (PORT datac (883:883:883) (964:964:964)) - (PORT datad (568:568:568) (558:558:558)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~6) - (DELAY - (ABSOLUTE - (PORT dataa (578:578:578) (597:597:597)) - (PORT datab (890:890:890) (953:953:953)) - (PORT datac (1596:1596:1596) (1638:1638:1638)) - (PORT datad (1056:1056:1056) (1043:1043:1043)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1834:1834:1834) (1832:1832:1832)) - (PORT datab (811:811:811) (805:805:805)) - (PORT datac (1249:1249:1249) (1292:1292:1292)) - (PORT datad (1251:1251:1251) (1268:1268:1268)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~0) - (DELAY - (ABSOLUTE - (PORT dataa (569:569:569) (584:584:584)) - (PORT datab (977:977:977) (1008:1008:1008)) - (PORT datac (186:186:186) (223:223:223)) - (PORT datad (810:810:810) (824:824:824)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~3) - (DELAY - (ABSOLUTE - (PORT dataa (572:572:572) (571:571:571)) - (PORT datab (184:184:184) (221:221:221)) - (PORT datac (804:804:804) (814:814:814)) - (PORT datad (797:797:797) (788:788:788)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~52) - (DELAY - (ABSOLUTE - (PORT dataa (1600:1600:1600) (1606:1606:1606)) - (PORT datab (979:979:979) (1057:1057:1057)) - (PORT datac (1109:1109:1109) (1153:1153:1153)) - (PORT datad (803:803:803) (799:799:799)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (628:628:628) (657:657:657)) - (PORT datab (1074:1074:1074) (1122:1122:1122)) - (PORT datac (1365:1365:1365) (1362:1362:1362)) - (PORT datad (1355:1355:1355) (1371:1371:1371)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~2) - (DELAY - (ABSOLUTE - (PORT dataa (797:797:797) (797:797:797)) - (PORT datab (1287:1287:1287) (1268:1268:1268)) - (PORT datac (730:730:730) (706:706:706)) - (PORT datad (1594:1594:1594) (1604:1604:1604)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|rsel3) - (DELAY - (ABSOLUTE - (PORT dataa (1293:1293:1293) (1323:1323:1323)) - (PORT datab (2166:2166:2166) (2220:2220:2220)) - (PORT datac (1040:1040:1040) (1047:1047:1047)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~5) - (DELAY - (ABSOLUTE - (PORT dataa (886:886:886) (905:905:905)) - (PORT datab (946:946:946) (963:963:963)) - (PORT datac (163:163:163) (199:199:199)) - (PORT datad (592:592:592) (606:606:606)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~6) - (DELAY - (ABSOLUTE - (PORT dataa (550:550:550) (567:567:567)) - (PORT datab (622:622:622) (640:640:640)) - (PORT datac (474:474:474) (464:464:464)) - (PORT datad (780:780:780) (784:784:784)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~7) - (DELAY - (ABSOLUTE - (PORT dataa (190:190:190) (231:231:231)) - (PORT datab (820:820:820) (834:834:834)) - (PORT datac (817:817:817) (831:831:831)) - (PORT datad (165:165:165) (189:189:189)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|rsel0) - (DELAY - (ABSOLUTE - (PORT dataa (2000:2000:2000) (2094:2094:2094)) - (PORT datac (1337:1337:1337) (1366:1366:1366)) - (PORT datad (2090:2090:2090) (2151:2151:2151)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_ixy_dT2_2) - (DELAY - (ABSOLUTE - (PORT datab (855:855:855) (898:898:898)) - (PORT datac (1428:1428:1428) (1488:1488:1488)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (651:651:651) (663:663:663)) - (PORT datab (804:804:804) (798:798:798)) - (PORT datac (1185:1185:1185) (1244:1244:1244)) - (PORT datad (830:830:830) (837:837:837)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1371:1371:1371) (1382:1382:1382)) - (PORT datab (186:186:186) (221:221:221)) - (PORT datac (915:915:915) (939:939:939)) - (PORT datad (943:943:943) (974:974:974)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~7) - (DELAY - (ABSOLUTE - (PORT dataa (213:213:213) (257:257:257)) - (PORT datab (348:348:348) (358:358:358)) - (PORT datac (557:557:557) (574:574:574)) - (PORT datad (182:182:182) (214:214:214)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_iorw\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1490:1490:1490) (1599:1599:1599)) - (PORT datab (1414:1414:1414) (1492:1492:1492)) - (PORT datac (1571:1571:1571) (1623:1623:1623)) - (PORT datad (1336:1336:1336) (1357:1357:1357)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1639:1639:1639) (1647:1647:1647)) - (PORT datab (618:618:618) (642:642:642)) - (PORT datac (515:515:515) (508:508:508)) - (PORT datad (1048:1048:1048) (1051:1051:1051)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~14) - (DELAY - (ABSOLUTE - (PORT dataa (627:627:627) (671:671:671)) - (PORT datab (921:921:921) (982:982:982)) - (PORT datac (174:174:174) (205:205:205)) - (PORT datad (1151:1151:1151) (1208:1208:1208)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~11) - (DELAY - (ABSOLUTE - (PORT dataa (568:568:568) (562:562:562)) - (PORT datab (813:813:813) (811:811:811)) - (PORT datac (314:314:314) (324:324:324)) - (PORT datad (635:635:635) (668:668:668)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~12) - (DELAY - (ABSOLUTE - (PORT dataa (606:606:606) (630:630:630)) - (PORT datab (875:875:875) (898:898:898)) - (PORT datac (542:542:542) (538:538:538)) - (PORT datad (593:593:593) (607:607:607)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1065:1065:1065) (1038:1038:1038)) - (PORT datab (180:180:180) (213:213:213)) - (PORT datac (537:537:537) (532:532:532)) - (PORT datad (165:165:165) (187:187:187)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_66_oe) - (DELAY - (ABSOLUTE - (PORT dataa (330:330:330) (453:453:453)) - (PORT datab (1209:1209:1209) (1252:1252:1252)) - (PORT datac (633:633:633) (694:694:694)) - (PORT datad (1201:1201:1201) (1265:1265:1265)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~34) - (DELAY - (ABSOLUTE - (PORT dataa (1460:1460:1460) (1479:1479:1479)) - (PORT datab (843:843:843) (847:847:847)) - (PORT datac (1162:1162:1162) (1169:1169:1169)) - (PORT datad (1542:1542:1542) (1536:1536:1536)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_apin_mux\~0) - (DELAY - (ABSOLUTE - (PORT dataa (345:345:345) (355:355:355)) - (PORT datab (201:201:201) (236:236:236)) - (PORT datac (595:595:595) (637:637:637)) - (PORT datad (1543:1543:1543) (1538:1538:1538)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1202:1202:1202) (1240:1240:1240)) - (PORT datab (1096:1096:1096) (1120:1120:1120)) - (PORT datac (1060:1060:1060) (1088:1088:1088)) - (PORT datad (1228:1228:1228) (1299:1299:1299)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~75) - (DELAY - (ABSOLUTE - (PORT dataa (837:837:837) (838:838:838)) - (PORT datab (357:357:357) (362:362:362)) - (PORT datac (595:595:595) (625:625:625)) - (PORT datad (1112:1112:1112) (1131:1131:1131)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~76) - (DELAY - (ABSOLUTE - (PORT dataa (1036:1036:1036) (1010:1010:1010)) - (PORT datab (840:840:840) (845:845:845)) - (PORT datac (938:938:938) (942:942:942)) - (PORT datad (844:844:844) (850:850:850)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (189:189:189) (226:226:226)) - (PORT datab (882:882:882) (943:943:943)) - (PORT datac (788:788:788) (775:775:775)) - (PORT datad (845:845:845) (863:863:863)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~48) - (DELAY - (ABSOLUTE - (PORT dataa (915:915:915) (960:960:960)) - (PORT datab (1111:1111:1111) (1133:1133:1133)) - (PORT datac (1453:1453:1453) (1510:1510:1510)) - (PORT datad (1061:1061:1061) (1067:1067:1067)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~46) - (DELAY - (ABSOLUTE - (PORT dataa (568:568:568) (599:599:599)) - (PORT datab (1910:1910:1910) (2031:2031:2031)) - (PORT datac (794:794:794) (793:793:793)) - (PORT datad (1137:1137:1137) (1187:1187:1187)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~53) - (DELAY - (ABSOLUTE - (PORT dataa (830:830:830) (853:853:853)) - (PORT datab (838:838:838) (837:837:837)) - (PORT datac (1039:1039:1039) (1029:1029:1029)) - (PORT datad (845:845:845) (851:851:851)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~92) - (DELAY - (ABSOLUTE - (PORT dataa (946:946:946) (1006:1006:1006)) - (PORT datab (1459:1459:1459) (1555:1555:1555)) - (PORT datac (578:578:578) (579:579:579)) - (PORT datad (1554:1554:1554) (1605:1605:1605)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal19\~1) - (DELAY - (ABSOLUTE - (PORT dataa (2170:2170:2170) (2236:2236:2236)) - (PORT datab (1515:1515:1515) (1602:1602:1602)) - (PORT datac (833:833:833) (863:863:863)) - (PORT datad (622:622:622) (647:647:647)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~0) - (DELAY - (ABSOLUTE - (PORT dataa (929:929:929) (994:994:994)) - (PORT datad (1419:1419:1419) (1497:1497:1497)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~38) - (DELAY - (ABSOLUTE - (PORT dataa (1204:1204:1204) (1241:1241:1241)) - (PORT datab (604:604:604) (626:626:626)) - (PORT datac (1256:1256:1256) (1261:1261:1261)) - (PORT datad (824:824:824) (814:814:814)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~93) - (DELAY - (ABSOLUTE - (PORT dataa (1046:1046:1046) (1058:1058:1058)) - (PORT datab (1581:1581:1581) (1635:1635:1635)) - (PORT datac (1431:1431:1431) (1520:1520:1520)) - (PORT datad (922:922:922) (971:971:971)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~39) - (DELAY - (ABSOLUTE - (PORT dataa (1258:1258:1258) (1338:1338:1338)) - (PORT datab (769:769:769) (764:764:764)) - (PORT datac (1036:1036:1036) (1044:1044:1044)) - (PORT datad (587:587:587) (616:616:616)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~24) - (DELAY - (ABSOLUTE - (PORT datab (1090:1090:1090) (1101:1101:1101)) - (PORT datac (175:175:175) (207:207:207)) - (PORT datad (166:166:166) (192:192:192)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~1) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (240:240:240)) - (PORT datab (792:792:792) (802:802:802)) - (PORT datac (176:176:176) (220:220:220)) - (PORT datad (620:620:620) (653:653:653)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla9M1T5_2) - (DELAY - (ABSOLUTE - (PORT dataa (898:898:898) (937:937:937)) - (PORT datab (857:857:857) (883:883:883)) - (PORT datac (1297:1297:1297) (1301:1301:1301)) - (PORT datad (505:505:505) (493:493:493)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~44) - (DELAY - (ABSOLUTE - (PORT dataa (553:553:553) (573:573:573)) - (PORT datab (813:813:813) (797:797:797)) - (PORT datac (1265:1265:1265) (1299:1299:1299)) - (PORT datad (1371:1371:1371) (1415:1415:1415)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (877:877:877) (902:902:902)) - (PORT datab (838:838:838) (839:839:839)) - (PORT datac (844:844:844) (867:867:867)) - (PORT datad (1421:1421:1421) (1476:1476:1476)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1087:1087:1087) (1086:1086:1086)) - (PORT datab (598:598:598) (626:626:626)) - (PORT datac (842:842:842) (851:851:851)) - (PORT datad (313:313:313) (321:321:321)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla10M5T4_2) - (DELAY - (ABSOLUTE - (PORT datab (1398:1398:1398) (1449:1449:1449)) - (PORT datac (1595:1595:1595) (1640:1640:1640)) - (PORT datad (992:992:992) (983:983:983)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (629:629:629) (651:651:651)) - (PORT datab (1077:1077:1077) (1092:1092:1092)) - (PORT datac (791:791:791) (802:802:802)) - (PORT datad (1085:1085:1085) (1121:1121:1121)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~2) - (DELAY - (ABSOLUTE - (PORT dataa (889:889:889) (893:893:893)) - (PORT datab (871:871:871) (898:898:898)) - (PORT datac (588:588:588) (608:608:608)) - (PORT datad (1068:1068:1068) (1085:1085:1085)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~3) - (DELAY - (ABSOLUTE - (PORT datab (795:795:795) (812:812:812)) - (PORT datac (162:162:162) (193:193:193)) - (PORT datad (785:785:785) (796:796:796)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~3) - (DELAY - (ABSOLUTE - (PORT dataa (982:982:982) (955:955:955)) - (PORT datab (1347:1347:1347) (1362:1362:1362)) - (PORT datac (1202:1202:1202) (1202:1202:1202)) - (PORT datad (796:796:796) (783:783:783)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1554:1554:1554) (1584:1584:1584)) - (PORT datab (1555:1555:1555) (1584:1584:1584)) - (PORT datac (1364:1364:1364) (1421:1421:1421)) - (PORT datad (800:800:800) (784:784:784)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla38pla13M4T2_4) - (DELAY - (ABSOLUTE - (PORT dataa (1339:1339:1339) (1364:1364:1364)) - (PORT datab (1555:1555:1555) (1579:1579:1579)) - (PORT datac (1526:1526:1526) (1546:1546:1546)) - (PORT datad (1081:1081:1081) (1109:1109:1109)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~15) - (DELAY - (ABSOLUTE - (PORT dataa (766:766:766) (823:823:823)) - (PORT datab (566:566:566) (558:558:558)) - (PORT datac (1372:1372:1372) (1392:1392:1392)) - (PORT datad (529:529:529) (531:531:531)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (856:856:856) (889:889:889)) - (PORT datab (852:852:852) (861:861:861)) - (PORT datac (819:819:819) (835:835:835)) - (PORT datad (178:178:178) (200:200:200)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~94) - (DELAY - (ABSOLUTE - (PORT dataa (1666:1666:1666) (1693:1693:1693)) - (PORT datab (1579:1579:1579) (1635:1635:1635)) - (PORT datac (1433:1433:1433) (1520:1520:1520)) - (PORT datad (924:924:924) (971:971:971)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~87) - (DELAY - (ABSOLUTE - (PORT dataa (1490:1490:1490) (1562:1562:1562)) - (PORT datac (2316:2316:2316) (2354:2354:2354)) - (PORT datad (1370:1370:1370) (1419:1419:1419)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~42) - (DELAY - (ABSOLUTE - (PORT dataa (1093:1093:1093) (1079:1079:1079)) - (PORT datab (1076:1076:1076) (1084:1084:1084)) - (PORT datac (175:175:175) (206:206:206)) - (PORT datad (801:801:801) (790:790:790)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~34) - (DELAY - (ABSOLUTE - (PORT datab (633:633:633) (649:649:649)) - (PORT datac (350:350:350) (372:372:372)) - (PORT datad (185:185:185) (210:210:210)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~16) - (DELAY - (ABSOLUTE - (PORT dataa (415:415:415) (441:441:441)) - (PORT datab (180:180:180) (212:212:212)) - (PORT datac (755:755:755) (733:733:733)) - (PORT datad (158:158:158) (178:178:178)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~6) - (DELAY - (ABSOLUTE - (PORT dataa (349:349:349) (366:366:366)) - (PORT datab (840:840:840) (809:809:809)) - (PORT datac (583:583:583) (587:587:587)) - (PORT datad (1100:1100:1100) (1110:1110:1110)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal2\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1160:1160:1160) (1201:1201:1201)) - (PORT datab (1520:1520:1520) (1606:1606:1606)) - (PORT datac (837:837:837) (864:864:864)) - (PORT datad (875:875:875) (891:891:891)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal1\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1344:1344:1344) (1403:1403:1403)) - (PORT datab (1544:1544:1544) (1566:1566:1566)) - (PORT datac (780:780:780) (766:766:766)) - (PORT datad (599:599:599) (622:622:622)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|bank_exx\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1303:1303:1303) (1397:1397:1397)) - (PORT datab (841:841:841) (835:835:835)) - (PORT datad (2159:2159:2159) (2215:2215:2215)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_control_\|bank_exx) - (DELAY - (ABSOLUTE - (PORT clk (1340:1340:1340) (1357:1357:1357)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1394:1394:1394) (1365:1365:1365)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|bank_hl_de1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1082:1082:1082) (1075:1075:1075)) - (PORT datab (1111:1111:1111) (1127:1127:1127)) - (PORT datad (1118:1118:1118) (1164:1164:1164)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_control_\|bank_hl_de1) - (DELAY - (ABSOLUTE - (PORT clk (1355:1355:1355) (1376:1376:1376)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1414:1414:1414) (1380:1380:1380)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (855:855:855) (872:872:872)) - (PORT datab (1882:1882:1882) (1862:1862:1862)) - (PORT datac (749:749:749) (731:731:731)) - (PORT datad (308:308:308) (321:321:321)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (889:889:889) (889:889:889)) - (PORT datab (1596:1596:1596) (1576:1576:1576)) - (PORT datac (1137:1137:1137) (1193:1193:1193)) - (PORT datad (1069:1069:1069) (1084:1084:1084)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (721:721:721) (704:704:704)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (1138:1138:1138) (1195:1195:1195)) - (PORT datad (1423:1423:1423) (1478:1478:1478)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1127:1127:1127) (1167:1167:1167)) - (PORT datab (1180:1180:1180) (1243:1243:1243)) - (PORT datac (1064:1064:1064) (1081:1081:1081)) - (PORT datad (653:653:653) (698:698:698)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (572:572:572) (587:587:587)) - (PORT datab (558:558:558) (547:547:547)) - (PORT datac (842:842:842) (851:851:851)) - (PORT datad (1614:1614:1614) (1636:1636:1636)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (877:877:877) (882:882:882)) - (PORT datab (334:334:334) (351:351:351)) - (PORT datac (1095:1095:1095) (1094:1094:1094)) - (PORT datad (1866:1866:1866) (1908:1908:1908)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (321:321:321) (333:333:333)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (156:156:156) (186:186:186)) - (PORT datad (814:814:814) (838:838:838)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~47) - (DELAY - (ABSOLUTE - (PORT dataa (890:890:890) (966:966:966)) - (PORT datab (841:841:841) (903:903:903)) - (PORT datac (994:994:994) (962:962:962)) - (PORT datad (981:981:981) (973:973:973)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1243:1243:1243) (1274:1274:1274)) - (PORT datab (836:836:836) (860:860:860)) - (PORT datac (614:614:614) (619:619:619)) - (PORT datad (1077:1077:1077) (1096:1096:1096)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1883:1883:1883) (1905:1905:1905)) - (PORT datac (1526:1526:1526) (1519:1519:1519)) - (PORT datad (1594:1594:1594) (1640:1640:1640)) + (PORT dataa (586:586:586) (632:632:632)) + (PORT datac (632:632:632) (684:684:684)) (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~2) - (DELAY - (ABSOLUTE - (PORT dataa (916:916:916) (952:952:952)) - (PORT datab (1230:1230:1230) (1233:1233:1233)) - (PORT datac (1216:1216:1216) (1250:1250:1250)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) (IOPATH datac combout (220:220:220) (216:216:216)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~19) + (INSTANCE z80_\|execute_\|ixy_d\~8) (DELAY (ABSOLUTE - (PORT datab (614:614:614) (609:609:609)) - (PORT datac (605:605:605) (605:605:605)) - (PORT datad (830:830:830) (864:864:864)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (PORT datab (244:244:244) (315:315:315)) + (PORT datad (235:235:235) (306:306:306)) + (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~7) + (INSTANCE z80_\|execute_\|ixy_d\~12) (DELAY (ABSOLUTE - (PORT dataa (613:613:613) (614:614:614)) - (PORT datab (656:656:656) (655:655:655)) - (PORT datac (625:625:625) (659:659:659)) - (PORT datad (773:773:773) (751:751:751)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (792:792:792) (788:788:788)) - (PORT datac (1768:1768:1768) (1803:1803:1803)) - (PORT datad (182:182:182) (216:216:216)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (568:568:568) (599:599:599)) - (PORT datab (802:802:802) (832:832:832)) - (PORT datac (1015:1015:1015) (1007:1007:1007)) - (PORT datad (767:767:767) (769:769:769)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (985:985:985) (1061:1061:1061)) - (PORT datab (925:925:925) (982:982:982)) - (PORT datac (1298:1298:1298) (1315:1315:1315)) - (PORT datad (185:185:185) (216:216:216)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (308:308:308) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (988:988:988) (1063:1063:1063)) - (PORT datab (1826:1826:1826) (1865:1865:1865)) - (PORT datac (1066:1066:1066) (1087:1087:1087)) - (PORT datad (862:862:862) (902:902:902)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (183:183:183) (216:216:216)) - (PORT datac (2410:2410:2410) (2500:2500:2500)) - (PORT datad (176:176:176) (198:198:198)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (862:862:862) (922:922:922)) - (PORT datac (1027:1027:1027) (1063:1063:1063)) - (PORT datad (1062:1062:1062) (1079:1079:1079)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~2) - (DELAY - (ABSOLUTE - (PORT dataa (898:898:898) (923:923:923)) - (PORT datab (784:784:784) (755:755:755)) - (PORT datac (1854:1854:1854) (1845:1845:1845)) - (PORT datad (1290:1290:1290) (1271:1271:1271)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~47) - (DELAY - (ABSOLUTE - (PORT dataa (1463:1463:1463) (1537:1537:1537)) - (PORT datab (846:846:846) (865:865:865)) - (PORT datac (857:857:857) (889:889:889)) - (PORT datad (1410:1410:1410) (1477:1477:1477)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~3) - (DELAY - (ABSOLUTE - (PORT dataa (589:589:589) (602:602:602)) - (PORT datab (806:806:806) (796:796:796)) - (PORT datac (556:556:556) (588:588:588)) - (PORT datad (756:756:756) (737:737:737)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1028:1028:1028) (1120:1120:1120)) - (PORT datac (1287:1287:1287) (1310:1310:1310)) - (PORT datad (1946:1946:1946) (2000:2000:2000)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (838:838:838) (866:866:866)) - (PORT datab (1437:1437:1437) (1489:1489:1489)) - (PORT datac (189:189:189) (227:227:227)) - (PORT datad (571:571:571) (571:571:571)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (1273:1273:1273) (1297:1297:1297)) - (PORT datab (570:570:570) (567:567:567)) - (PORT datac (730:730:730) (709:709:709)) - (PORT datad (553:553:553) (545:545:545)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (1541:1541:1541) (1540:1540:1540)) - (PORT datab (1032:1032:1032) (1027:1027:1027)) - (PORT datac (973:973:973) (1020:1020:1020)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~49) - (DELAY - (ABSOLUTE - (PORT dataa (1222:1222:1222) (1283:1283:1283)) - (PORT datab (188:188:188) (223:223:223)) - (PORT datac (553:553:553) (560:560:560)) - (PORT datad (1361:1361:1361) (1405:1405:1405)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (308:308:308) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (542:542:542) (529:529:529)) - (PORT datab (572:572:572) (598:598:598)) - (PORT datac (568:568:568) (565:565:565)) - (PORT datad (543:543:543) (521:521:521)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (2077:2077:2077) (2125:2125:2125)) - (PORT datab (237:237:237) (304:304:304)) - (PORT datac (1069:1069:1069) (1106:1106:1106)) - (PORT datad (214:214:214) (271:271:271)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (219:219:219)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (161:161:161) (196:196:196)) - (PORT datad (809:809:809) (823:823:823)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~28) - (DELAY - (ABSOLUTE - (PORT datab (189:189:189) (226:226:226)) - (PORT datad (614:614:614) (630:630:630)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (195:195:195) (239:239:239)) - (PORT datab (959:959:959) (957:957:957)) - (PORT datac (310:310:310) (319:319:319)) - (PORT datad (637:637:637) (668:668:668)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1041:1041:1041) (1135:1135:1135)) - (PORT datac (825:825:825) (856:856:856)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~14) - (DELAY - (ABSOLUTE - (PORT datac (611:611:611) (666:666:666)) - (PORT datad (830:830:830) (826:826:826)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1328:1328:1328) (1337:1337:1337)) - (PORT datab (575:575:575) (576:576:576)) - (PORT datac (156:156:156) (186:186:186)) - (PORT datad (1052:1052:1052) (1050:1050:1050)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~47) - (DELAY - (ABSOLUTE - (PORT dataa (572:572:572) (570:570:570)) - (PORT datab (602:602:602) (594:594:594)) - (PORT datac (827:827:827) (826:826:826)) - (PORT datad (819:819:819) (832:832:832)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~48) - (DELAY - (ABSOLUTE - (PORT dataa (324:324:324) (341:341:341)) - (PORT datab (201:201:201) (235:235:235)) - (PORT datac (566:566:566) (585:585:585)) - (PORT datad (985:985:985) (968:968:968)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1884:1884:1884) (1906:1906:1906)) - (PORT datac (1526:1526:1526) (1518:1518:1518)) - (PORT datad (1595:1595:1595) (1640:1640:1640)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1225:1225:1225) (1290:1290:1290)) - (PORT datab (1026:1026:1026) (1009:1009:1009)) - (PORT datac (849:849:849) (867:867:867)) - (PORT datad (521:521:521) (513:513:513)) + (PORT dataa (1871:1871:1871) (1846:1846:1846)) + (PORT datab (875:875:875) (912:912:912)) + (PORT datac (1545:1545:1545) (1556:1556:1556)) + (PORT datad (1158:1158:1158) (1217:1217:1217)) (IOPATH dataa combout (309:309:309) (326:326:326)) (IOPATH datab combout (309:309:309) (328:328:328)) (IOPATH datac combout (218:218:218) (215:215:215)) @@ -7920,1174 +1170,67 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_oe\~1) + (INSTANCE z80_\|pla_decode_\|Equal33\~0) (DELAY (ABSOLUTE - (PORT dataa (209:209:209) (250:250:250)) - (PORT datab (207:207:207) (246:246:246)) - (PORT datac (1092:1092:1092) (1118:1118:1118)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~13) - (DELAY - (ABSOLUTE - (PORT dataa (757:757:757) (754:754:754)) - (PORT datab (1168:1168:1168) (1189:1189:1189)) - (PORT datac (1657:1657:1657) (1708:1708:1708)) - (PORT datad (1950:1950:1950) (2008:2008:2008)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (585:585:585) (583:583:583)) - (PORT datac (554:554:554) (549:549:549)) - (PORT datad (782:782:782) (777:777:777)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~40) - (DELAY - (ABSOLUTE - (PORT dataa (1258:1258:1258) (1344:1344:1344)) - (PORT datab (688:688:688) (729:729:729)) - (PORT datac (809:809:809) (805:805:805)) - (PORT datad (829:829:829) (860:860:860)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~2) - (DELAY - (ABSOLUTE - (PORT dataa (835:835:835) (809:809:809)) - (PORT datab (623:623:623) (666:666:666)) - (PORT datac (899:899:899) (929:929:929)) - (PORT datad (1646:1646:1646) (1664:1664:1664)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1201:1201:1201) (1254:1254:1254)) - (PORT datab (820:820:820) (825:825:825)) - (PORT datac (579:579:579) (580:580:580)) - (PORT datad (1600:1600:1600) (1599:1599:1599)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~43) - (DELAY - (ABSOLUTE - (PORT dataa (1258:1258:1258) (1346:1346:1346)) - (PORT datab (597:597:597) (633:633:633)) - (PORT datac (810:810:810) (806:806:806)) - (PORT datad (355:355:355) (359:359:359)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~5) - (DELAY - (ABSOLUTE - (PORT dataa (837:837:837) (851:851:851)) - (PORT datab (627:627:627) (668:668:668)) - (PORT datac (894:894:894) (935:935:935)) - (PORT datad (579:579:579) (570:570:570)) + (PORT dataa (1558:1558:1558) (1576:1576:1576)) + (PORT datab (245:245:245) (319:319:319)) + (PORT datad (354:354:354) (393:393:393)) (IOPATH dataa combout (273:273:273) (269:269:269)) (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~4) + (INSTANCE z80_\|pla_decode_\|Equal33\~1) (DELAY (ABSOLUTE - (PORT dataa (1347:1347:1347) (1368:1368:1368)) - (PORT datab (867:867:867) (863:863:863)) - (PORT datac (173:173:173) (204:204:204)) - (PORT datad (1302:1302:1302) (1304:1304:1304)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT dataa (1848:1848:1848) (1985:1985:1985)) + (PORT datab (1121:1121:1121) (1151:1151:1151)) + (PORT datad (1176:1176:1176) (1214:1214:1214)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~6) + (INSTANCE z80_\|pla_decode_\|Equal33\~2) (DELAY (ABSOLUTE - (PORT dataa (1469:1469:1469) (1500:1500:1500)) - (PORT datab (1474:1474:1474) (1453:1453:1453)) - (PORT datac (920:920:920) (954:954:954)) - (PORT datad (1434:1434:1434) (1445:1445:1445)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1352:1352:1352) (1366:1366:1366)) - (PORT datab (824:824:824) (865:865:865)) - (PORT datac (758:758:758) (792:792:792)) - (PORT datad (550:550:550) (549:549:549)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1349:1349:1349) (1363:1363:1363)) - (PORT datab (825:825:825) (869:869:869)) - (PORT datac (156:156:156) (187:187:187)) - (PORT datad (842:842:842) (874:874:874)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (554:554:554) (549:549:549)) - (PORT datab (794:794:794) (812:812:812)) - (PORT datac (731:731:731) (762:762:762)) - (PORT datad (725:725:725) (755:755:755)) + (PORT dataa (1128:1128:1128) (1164:1164:1164)) + (PORT datab (917:917:917) (949:949:949)) + (PORT datad (1508:1508:1508) (1486:1486:1486)) (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~13) + (INSTANCE z80_\|pla_decode_\|Equal21\~0) (DELAY (ABSOLUTE - (PORT dataa (606:606:606) (604:604:604)) - (PORT datab (214:214:214) (255:255:255)) - (PORT datac (1213:1213:1213) (1288:1288:1288)) - (PORT datad (2060:2060:2060) (2081:2081:2081)) - (IOPATH dataa combout (287:287:287) (280:280:280)) + (PORT datab (1315:1315:1315) (1334:1334:1334)) + (PORT datad (1329:1329:1329) (1374:1374:1374)) (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~10) + (INSTANCE z80_\|pla_decode_\|Equal77\~0) (DELAY (ABSOLUTE - (PORT dataa (1666:1666:1666) (1749:1749:1749)) - (PORT datab (1520:1520:1520) (1585:1585:1585)) - (PORT datac (1196:1196:1196) (1253:1253:1253)) - (PORT datad (2365:2365:2365) (2392:2392:2392)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1167:1167:1167) (1182:1182:1182)) - (PORT datab (803:803:803) (793:793:793)) - (PORT datac (157:157:157) (188:188:188)) - (PORT datad (546:546:546) (541:541:541)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1342:1342:1342) (1384:1384:1384)) - (PORT datab (236:236:236) (278:278:278)) - (PORT datac (1106:1106:1106) (1143:1143:1143)) - (PORT datad (776:776:776) (760:760:760)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal62\~2) - (DELAY - (ABSOLUTE - (PORT dataa (784:784:784) (815:815:815)) - (PORT datab (827:827:827) (812:812:812)) - (PORT datac (798:798:798) (782:782:782)) - (PORT datad (830:830:830) (868:868:868)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (795:795:795) (821:821:821)) - (PORT datab (865:865:865) (910:910:910)) - (PORT datac (173:173:173) (217:217:217)) - (PORT datad (1070:1070:1070) (1075:1075:1075)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1350:1350:1350) (1336:1336:1336)) - (PORT datab (1385:1385:1385) (1402:1402:1402)) - (PORT datac (1018:1018:1018) (1017:1017:1017)) - (PORT datad (369:369:369) (395:395:395)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal64\~0) - (DELAY - (ABSOLUTE - (PORT dataa (782:782:782) (812:812:812)) - (PORT datab (829:829:829) (812:812:812)) - (PORT datac (800:800:800) (784:784:784)) - (PORT datad (831:831:831) (871:871:871)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel\[0\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (660:660:660) (727:727:727)) - (PORT datab (721:721:721) (791:791:791)) - (PORT datad (1092:1092:1092) (1075:1075:1075)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (555:555:555) (538:538:538)) - (PORT datab (1080:1080:1080) (1067:1067:1067)) - (PORT datac (796:796:796) (816:816:816)) - (PORT datad (838:838:838) (844:844:844)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1342:1342:1342) (1386:1386:1386)) - (PORT datab (799:799:799) (795:795:795)) - (PORT datac (1177:1177:1177) (1213:1213:1213)) - (PORT datad (1481:1481:1481) (1552:1552:1552)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla89M1T2_3) - (DELAY - (ABSOLUTE - (PORT dataa (1376:1376:1376) (1455:1455:1455)) - (PORT datab (1328:1328:1328) (1314:1314:1314)) - (PORT datac (1318:1318:1318) (1387:1387:1387)) - (PORT datad (376:376:376) (397:397:397)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (936:936:936) (940:940:940)) - (PORT datac (742:742:742) (722:722:722)) - (PORT datad (941:941:941) (930:930:930)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (368:368:368) (398:398:398)) - (PORT datac (907:907:907) (902:902:902)) - (PORT datad (167:167:167) (191:191:191)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (319:319:319) (330:330:330)) - (PORT datab (181:181:181) (212:212:212)) - (PORT datac (547:547:547) (551:551:551)) - (PORT datad (1399:1399:1399) (1467:1467:1467)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (1125:1125:1125) (1148:1148:1148)) - (PORT datab (1126:1126:1126) (1152:1152:1152)) - (PORT datac (820:820:820) (852:852:852)) - (PORT datad (1400:1400:1400) (1447:1447:1447)) - (IOPATH dataa combout (307:307:307) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (792:792:792) (784:784:784)) - (PORT datab (208:208:208) (247:247:247)) - (PORT datac (1074:1074:1074) (1134:1134:1134)) - (PORT datad (159:159:159) (179:179:179)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\~20) - (DELAY - (ABSOLUTE - (PORT dataa (1554:1554:1554) (1578:1578:1578)) - (PORT datab (1555:1555:1555) (1584:1584:1584)) - (PORT datac (1366:1366:1366) (1422:1422:1422)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (863:863:863) (923:923:923)) - (PORT datab (187:187:187) (221:221:221)) - (PORT datac (1105:1105:1105) (1128:1128:1128)) - (PORT datad (820:820:820) (821:821:821)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~35) - (DELAY - (ABSOLUTE - (PORT datab (1117:1117:1117) (1098:1098:1098)) - (PORT datac (1157:1157:1157) (1166:1166:1166)) - (PORT datad (735:735:735) (714:714:714)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_de2\~5) - (DELAY - (ABSOLUTE - (PORT dataa (832:832:832) (864:864:864)) - (PORT datab (873:873:873) (894:894:894)) - (PORT datac (1056:1056:1056) (1047:1047:1047)) - (PORT datad (356:356:356) (376:376:376)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_de2\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1190:1190:1190) (1198:1198:1198)) - (PORT datab (1113:1113:1113) (1096:1096:1096)) - (PORT datac (1053:1053:1053) (1046:1046:1046)) - (PORT datad (735:735:735) (713:713:713)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_hl\~0) - (DELAY - (ABSOLUTE - (PORT dataa (230:230:230) (307:307:307)) - (PORT datab (200:200:200) (245:245:245)) - (PORT datac (316:316:316) (331:331:331)) - (PORT datad (1131:1131:1131) (1174:1174:1174)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|bank_hl_de2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1084:1084:1084) (1078:1078:1078)) - (PORT datab (1108:1108:1108) (1126:1126:1126)) - (PORT datad (1131:1131:1131) (1181:1181:1181)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_control_\|bank_hl_de2) - (DELAY - (ABSOLUTE - (PORT clk (1355:1355:1355) (1376:1376:1376)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1414:1414:1414) (1380:1380:1380)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_hl2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (342:342:342) (357:357:357)) - (PORT datab (199:199:199) (242:242:242)) - (PORT datac (200:200:200) (270:270:270)) - (PORT datad (1114:1114:1114) (1162:1162:1162)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~7) - (DELAY - (ABSOLUTE - (PORT dataa (526:526:526) (519:519:519)) - (PORT datab (960:960:960) (961:961:961)) - (PORT datac (314:314:314) (324:324:324)) - (PORT datad (635:635:635) (668:668:668)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (596:596:596) (629:629:629)) - (PORT datab (1595:1595:1595) (1613:1613:1613)) - (PORT datad (813:813:813) (804:804:804)) - (IOPATH dataa combout (267:267:267) (273:273:273)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla30npla13M4T3_5) - (DELAY - (ABSOLUTE - (PORT dataa (2436:2436:2436) (2440:2440:2440)) - (PORT datab (1579:1579:1579) (1634:1634:1634)) - (PORT datac (945:945:945) (943:943:943)) - (PORT datad (1419:1419:1419) (1423:1423:1423)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (251:251:251)) - (PORT datab (819:819:819) (824:824:824)) - (PORT datac (1371:1371:1371) (1418:1418:1418)) - (PORT datad (1122:1122:1122) (1134:1134:1134)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~13) - (DELAY - (ABSOLUTE - (PORT dataa (897:897:897) (921:921:921)) - (PORT datab (185:185:185) (222:222:222)) - (PORT datac (878:878:878) (906:906:906)) - (PORT datad (190:190:190) (217:217:217)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla30npla13M5T3_5) - (DELAY - (ABSOLUTE - (PORT dataa (878:878:878) (908:908:908)) - (PORT datab (210:210:210) (251:251:251)) - (PORT datac (1296:1296:1296) (1317:1317:1317)) - (PORT datad (1395:1395:1395) (1410:1410:1410)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1065:1065:1065) (1073:1073:1073)) - (PORT datab (1434:1434:1434) (1430:1430:1430)) - (PORT datac (553:553:553) (573:573:573)) - (PORT datad (177:177:177) (198:198:198)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (332:332:332) (347:347:347)) - (PORT datab (180:180:180) (212:212:212)) - (PORT datac (155:155:155) (184:184:184)) - (PORT datad (163:163:163) (187:187:187)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (845:845:845) (847:847:847)) - (PORT datab (615:615:615) (615:615:615)) - (PORT datac (1030:1030:1030) (994:994:994)) - (PORT datad (723:723:723) (705:705:705)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1491:1491:1491) (1597:1597:1597)) - (PORT datab (1403:1403:1403) (1444:1444:1444)) - (PORT datac (1573:1573:1573) (1621:1621:1621)) - (PORT datad (986:986:986) (963:963:963)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~50) - (DELAY - (ABSOLUTE - (PORT dataa (1855:1855:1855) (1982:1982:1982)) - (PORT datab (1351:1351:1351) (1392:1392:1392)) - (PORT datac (1387:1387:1387) (1427:1427:1427)) - (PORT datad (1772:1772:1772) (1781:1781:1781)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (835:835:835) (863:863:863)) - (PORT datab (808:808:808) (808:808:808)) - (PORT datac (747:747:747) (789:789:789)) - (PORT datad (1402:1402:1402) (1458:1458:1458)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (579:579:579) (590:590:590)) - (PORT datab (616:616:616) (645:645:645)) - (PORT datac (850:850:850) (872:872:872)) - (PORT datad (164:164:164) (190:190:190)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (649:649:649) (669:669:669)) - (PORT datab (1098:1098:1098) (1128:1128:1128)) - (PORT datac (615:615:615) (620:620:620)) - (PORT datad (1199:1199:1199) (1235:1235:1235)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (1268:1268:1268) (1283:1283:1283)) - (PORT datab (599:599:599) (612:612:612)) - (PORT datac (1228:1228:1228) (1222:1222:1222)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (308:308:308) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla10M5T1_5\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1022:1022:1022) (1093:1093:1093)) - (PORT datab (1683:1683:1683) (1698:1698:1698)) - (PORT datad (892:892:892) (959:959:959)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (841:841:841) (839:839:839)) - (PORT datab (631:631:631) (663:663:663)) - (PORT datac (182:182:182) (216:216:216)) - (PORT datad (2040:2040:2040) (2019:2019:2019)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~51) - (DELAY - (ABSOLUTE - (PORT dataa (1154:1154:1154) (1188:1188:1188)) - (PORT datab (1375:1375:1375) (1404:1404:1404)) - (PORT datac (1140:1140:1140) (1139:1139:1139)) - (PORT datad (1133:1133:1133) (1131:1131:1131)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (1770:1770:1770) (1773:1773:1773)) - (PORT datab (182:182:182) (215:215:215)) - (PORT datac (797:797:797) (838:838:838)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (575:575:575) (568:568:568)) - (PORT datab (199:199:199) (233:233:233)) - (PORT datac (824:824:824) (827:827:827)) - (PORT datad (752:752:752) (779:779:779)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (751:751:751) (800:800:800)) - (PORT datab (186:186:186) (222:222:222)) - (PORT datac (521:521:521) (520:520:520)) - (PORT datad (572:572:572) (593:593:593)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (792:792:792) (787:787:787)) - (PORT datac (188:188:188) (230:230:230)) - (PORT datad (184:184:184) (217:217:217)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (1214:1214:1214) (1240:1240:1240)) - (PORT datab (574:574:574) (563:563:563)) - (PORT datac (779:779:779) (772:772:772)) - (PORT datad (568:568:568) (574:574:574)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (1303:1303:1303) (1325:1325:1325)) - (PORT datab (851:851:851) (858:858:858)) - (PORT datac (1050:1050:1050) (1064:1064:1064)) - (PORT datad (1086:1086:1086) (1124:1124:1124)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla6M1T4_4) - (DELAY - (ABSOLUTE - (PORT dataa (1615:1615:1615) (1648:1648:1648)) - (PORT datab (777:777:777) (759:759:759)) - (PORT datac (1852:1852:1852) (1834:1834:1834)) - (PORT datad (1888:1888:1888) (1939:1939:1939)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~40) - (DELAY - (ABSOLUTE - (PORT dataa (855:855:855) (870:870:870)) - (PORT datab (1014:1014:1014) (1032:1032:1032)) - (PORT datad (177:177:177) (199:199:199)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (508:508:508) (501:501:501)) - (PORT datab (615:615:615) (629:629:629)) - (PORT datac (1842:1842:1842) (1822:1822:1822)) - (PORT datad (511:511:511) (487:487:487)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (218:218:218)) - (PORT datab (791:791:791) (833:833:833)) - (PORT datac (162:162:162) (194:194:194)) - (PORT datad (178:178:178) (200:200:200)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~38) - (DELAY - (ABSOLUTE - (PORT dataa (184:184:184) (220:220:220)) - (PORT datab (790:790:790) (781:781:781)) - (PORT datac (530:530:530) (525:525:525)) - (PORT datad (166:166:166) (189:189:189)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~93) - (DELAY - (ABSOLUTE - (PORT dataa (1105:1105:1105) (1110:1110:1110)) - (PORT datab (984:984:984) (938:938:938)) - (PORT datac (1084:1084:1084) (1078:1078:1078)) - (PORT datad (1262:1262:1262) (1238:1238:1238)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_de\~0) - (DELAY - (ABSOLUTE - (PORT dataa (226:226:226) (301:301:301)) - (PORT datab (199:199:199) (242:242:242)) - (PORT datac (314:314:314) (326:326:326)) - (PORT datad (1115:1115:1115) (1162:1162:1162)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_50) - (DELAY - (ABSOLUTE - (PORT datab (1303:1303:1303) (1278:1278:1278)) - (PORT datac (1080:1080:1080) (1073:1073:1073)) - (PORT datad (551:551:551) (560:560:560)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_70\~2) - (DELAY - (ABSOLUTE - (PORT datac (836:836:836) (844:844:844)) - (PORT datad (1247:1247:1247) (1232:1232:1232)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_66\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1085:1085:1085) (1104:1104:1104)) - (PORT datab (202:202:202) (244:244:244)) - (PORT datac (1054:1054:1054) (1051:1051:1051)) - (PORT datad (624:624:624) (643:643:643)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_38\~0) - (DELAY - (ABSOLUTE - (PORT dataa (651:651:651) (685:685:685)) - (PORT datab (1364:1364:1364) (1393:1393:1393)) - (PORT datac (1057:1057:1057) (1051:1051:1051)) - (PORT datad (179:179:179) (212:212:212)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_42\~0) - (DELAY - (ABSOLUTE - (PORT dataa (643:643:643) (678:678:678)) - (PORT datab (1366:1366:1366) (1398:1398:1398)) - (PORT datac (1051:1051:1051) (1047:1047:1047)) - (PORT datad (176:176:176) (209:209:209)) + (PORT dataa (958:958:958) (1027:1027:1027)) + (PORT datab (916:916:916) (988:988:988)) + (PORT datac (860:860:860) (938:938:938)) + (PORT datad (905:905:905) (964:964:964)) (IOPATH dataa combout (265:265:265) (273:273:273)) (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (215:215:215)) @@ -9097,153 +1240,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~9) + (INSTANCE z80_\|pla_decode_\|Equal77\~1) (DELAY (ABSOLUTE - (PORT dataa (1241:1241:1241) (1264:1264:1264)) - (PORT datab (802:802:802) (818:818:818)) - (PORT datac (1675:1675:1675) (1702:1702:1702)) - (PORT datad (1446:1446:1446) (1466:1466:1466)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~10) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (219:219:219)) - (PORT datab (188:188:188) (223:223:223)) - (PORT datad (798:798:798) (802:802:802)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~19) - (DELAY - (ABSOLUTE - (PORT dataa (907:907:907) (968:968:968)) - (PORT datab (603:603:603) (608:608:608)) - (PORT datac (851:851:851) (875:875:875)) - (PORT datad (1334:1334:1334) (1387:1387:1387)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla37pla28M2T3_4) - (DELAY - (ABSOLUTE - (PORT dataa (1018:1018:1018) (1057:1057:1057)) - (PORT datab (651:651:651) (704:704:704)) - (PORT datac (1319:1319:1319) (1387:1387:1387)) - (PORT datad (1351:1351:1351) (1415:1415:1415)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_lo\~8) - (DELAY - (ABSOLUTE - (PORT dataa (559:559:559) (558:558:558)) - (PORT datab (187:187:187) (223:223:223)) - (PORT datac (576:576:576) (588:588:588)) - (PORT datad (1016:1016:1016) (977:977:977)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (367:367:367) (370:370:370)) - (PORT datab (1097:1097:1097) (1091:1091:1091)) - (PORT datac (330:330:330) (337:337:337)) - (PORT datad (1019:1019:1019) (993:993:993)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1153:1153:1153) (1192:1192:1192)) - (PORT datab (1464:1464:1464) (1534:1534:1534)) - (PORT datac (2034:2034:2034) (2016:2016:2016)) - (PORT datad (985:985:985) (1044:1044:1044)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~5) - (DELAY - (ABSOLUTE - (PORT dataa (880:880:880) (909:909:909)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (1151:1151:1151) (1162:1162:1162)) - (PORT datad (178:178:178) (199:199:199)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~6) - (DELAY - (ABSOLUTE - (PORT dataa (576:576:576) (587:587:587)) - (PORT datac (614:614:614) (623:623:623)) - (PORT datad (519:519:519) (489:489:489)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_78\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1065:1065:1065) (1076:1076:1076)) - (PORT datab (198:198:198) (238:238:238)) - (PORT datac (1048:1048:1048) (1041:1041:1041)) - (PORT datad (615:615:615) (635:635:635)) + (PORT dataa (620:620:620) (649:649:649)) + (PORT datab (607:607:607) (654:654:654)) + (PORT datac (1569:1569:1569) (1582:1582:1582)) + (PORT datad (542:542:542) (536:536:536)) (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) @@ -9253,60 +1256,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal21\~2) + (INSTANCE z80_\|pla_decode_\|Equal1\~7) (DELAY (ABSOLUTE - (PORT dataa (837:837:837) (840:840:840)) - (PORT datab (823:823:823) (821:821:821)) - (PORT datac (839:839:839) (888:888:888)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) + (PORT dataa (1126:1126:1126) (1147:1147:1147)) + (PORT datab (573:573:573) (596:596:596)) + (PORT datac (532:532:532) (513:513:513)) + (PORT datad (547:547:547) (577:577:577)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (215:215:215)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|bank_af\~0) - (DELAY - (ABSOLUTE - (PORT dataa (655:655:655) (674:674:674)) - (PORT datab (1094:1094:1094) (1073:1073:1073)) - (PORT datad (877:877:877) (872:872:872)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_control_\|bank_af) - (DELAY - (ABSOLUTE - (PORT clk (1343:1343:1343) (1361:1361:1361)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1396:1396:1396) (1368:1368:1368)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_af\~0) + (INSTANCE z80_\|pla_decode_\|Equal79\~0) (DELAY (ABSOLUTE - (PORT dataa (1063:1063:1063) (1081:1081:1081)) - (PORT datab (225:225:225) (296:296:296)) - (PORT datac (1056:1056:1056) (1051:1051:1051)) - (PORT datad (624:624:624) (643:643:643)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) + (PORT dataa (711:711:711) (776:776:776)) + (PORT datab (1768:1768:1768) (1837:1837:1837)) + (PORT datac (1178:1178:1178) (1203:1203:1203)) + (PORT datad (1503:1503:1503) (1491:1491:1491)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -9314,101 +1288,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_34) + (INSTANCE z80_\|interrupts_\|iff1\~0) (DELAY (ABSOLUTE - (PORT dataa (634:634:634) (644:644:644)) - (PORT datab (1269:1269:1269) (1248:1248:1248)) - (PORT datad (843:843:843) (858:858:858)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_af2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1063:1063:1063) (1075:1075:1075)) - (PORT datab (226:226:226) (299:299:299)) - (PORT datac (1050:1050:1050) (1045:1045:1045)) - (PORT datad (614:614:614) (638:638:638)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_30) - (DELAY - (ABSOLUTE - (PORT dataa (1612:1612:1612) (1604:1604:1604)) - (PORT datab (1085:1085:1085) (1084:1084:1084)) - (PORT datad (744:744:744) (705:705:705)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~12) - (DELAY - (ABSOLUTE - (PORT dataa (645:645:645) (681:681:681)) - (PORT datab (857:857:857) (878:878:878)) - (PORT datac (1675:1675:1675) (1732:1732:1732)) - (PORT datad (1057:1057:1057) (1054:1054:1054)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1364:1364:1364) (1424:1424:1424)) - (PORT datac (942:942:942) (961:961:961)) - (PORT datad (304:304:304) (309:309:309)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1321:1321:1321) (1321:1321:1321)) - (PORT datab (1079:1079:1079) (1103:1103:1103)) - (PORT datac (1868:1868:1868) (1905:1905:1905)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1079:1079:1079) (1075:1075:1075)) - (PORT datab (1895:1895:1895) (1904:1904:1904)) - (PORT datac (878:878:878) (907:907:907)) - (PORT datad (160:160:160) (182:182:182)) + (PORT dataa (198:198:198) (242:242:242)) + (PORT datab (1297:1297:1297) (1282:1282:1282)) + (PORT datac (361:361:361) (404:404:404)) + (PORT datad (1129:1129:1129) (1181:1181:1181)) (IOPATH dataa combout (318:318:318) (327:327:327)) (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (220:220:220) (216:216:216)) @@ -9418,1826 +1304,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~24) + (INSTANCE z80_\|interrupts_\|DFFE_instIFF2\~0) (DELAY (ABSOLUTE - (PORT dataa (764:764:764) (823:823:823)) - (PORT datab (1401:1401:1401) (1421:1421:1421)) - (PORT datac (1205:1205:1205) (1204:1204:1204)) - (PORT datad (802:802:802) (787:787:787)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~13) - (DELAY - (ABSOLUTE - (PORT datab (207:207:207) (246:246:246)) - (PORT datac (182:182:182) (217:217:217)) - (PORT datad (184:184:184) (209:209:209)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (219:219:219)) - (PORT datab (1424:1424:1424) (1497:1497:1497)) - (PORT datac (186:186:186) (222:222:222)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~3) - (DELAY - (ABSOLUTE - (PORT dataa (549:549:549) (551:551:551)) - (PORT datab (811:811:811) (812:812:812)) - (PORT datac (1275:1275:1275) (1293:1293:1293)) - (PORT datad (1806:1806:1806) (1800:1800:1800)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (203:203:203) (240:240:240)) - (PORT datab (1860:1860:1860) (1858:1858:1858)) - (PORT datac (752:752:752) (731:731:731)) - (PORT datad (177:177:177) (199:199:199)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~2) - (DELAY - (ABSOLUTE - (PORT dataa (633:633:633) (662:662:662)) - (PORT datab (1339:1339:1339) (1359:1359:1359)) - (PORT datac (330:330:330) (348:348:348)) - (PORT datad (1037:1037:1037) (1058:1058:1058)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~3) - (DELAY - (ABSOLUTE - (PORT dataa (209:209:209) (251:251:251)) - (PORT datab (527:527:527) (514:514:514)) - (PORT datac (745:745:745) (740:740:740)) - (PORT datad (550:550:550) (564:564:564)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1084:1084:1084) (1118:1118:1118)) - (PORT datab (554:554:554) (551:551:551)) - (PORT datac (594:594:594) (624:624:624)) - (PORT datad (792:792:792) (796:796:796)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~5) - (DELAY - (ABSOLUTE - (PORT dataa (632:632:632) (659:659:659)) - (PORT datab (1109:1109:1109) (1110:1110:1110)) - (PORT datac (1070:1070:1070) (1080:1080:1080)) - (PORT datad (549:549:549) (536:536:536)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~4) - (DELAY - (ABSOLUTE - (PORT dataa (831:831:831) (830:830:830)) - (PORT datab (1103:1103:1103) (1126:1126:1126)) - (PORT datac (830:830:830) (843:843:843)) - (PORT datad (586:586:586) (608:608:608)) + (PORT dataa (197:197:197) (239:239:239)) + (PORT datab (1297:1297:1297) (1280:1280:1280)) + (PORT datad (1131:1131:1131) (1183:1183:1183)) (IOPATH dataa combout (318:318:318) (327:327:327)) (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~7) - (DELAY - (ABSOLUTE - (PORT dataa (543:543:543) (543:543:543)) - (PORT datab (182:182:182) (216:216:216)) - (PORT datac (157:157:157) (187:187:187)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~8) - (DELAY - (ABSOLUTE - (PORT dataa (865:865:865) (862:862:862)) - (PORT datab (1104:1104:1104) (1125:1125:1125)) - (PORT datac (332:332:332) (352:352:352)) - (PORT datad (1035:1035:1035) (1058:1058:1058)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1083:1083:1083) (1119:1119:1119)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (1071:1071:1071) (1083:1083:1083)) - (PORT datad (789:789:789) (795:795:795)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~10) - (DELAY - (ABSOLUTE - (PORT dataa (188:188:188) (228:228:228)) - (PORT datab (180:180:180) (213:213:213)) - (PORT datac (593:593:593) (623:623:623)) - (PORT datad (785:785:785) (799:799:799)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (577:577:577) (565:565:565)) - (PORT datab (634:634:634) (646:646:646)) - (PORT datac (350:350:350) (370:370:370)) - (PORT datad (184:184:184) (208:208:208)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (219:219:219)) - (PORT datab (565:565:565) (563:563:563)) - (PORT datac (499:499:499) (482:482:482)) - (PORT datad (781:781:781) (787:787:787)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~29) - (DELAY - (ABSOLUTE - (PORT dataa (860:860:860) (880:880:880)) - (PORT datab (1437:1437:1437) (1501:1501:1501)) - (PORT datac (1296:1296:1296) (1312:1312:1312)) - (PORT datad (182:182:182) (213:213:213)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~13) - (DELAY - (ABSOLUTE - (PORT dataa (569:569:569) (594:594:594)) - (PORT datab (884:884:884) (945:945:945)) - (PORT datac (1595:1595:1595) (1641:1641:1641)) - (PORT datad (1057:1057:1057) (1049:1049:1049)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~49) - (DELAY - (ABSOLUTE - (PORT dataa (1019:1019:1019) (1055:1055:1055)) - (PORT datab (1346:1346:1346) (1415:1415:1415)) - (PORT datac (1487:1487:1487) (1528:1528:1528)) - (PORT datad (1084:1084:1084) (1099:1099:1099)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1292:1292:1292) (1272:1272:1272)) - (PORT datab (1148:1148:1148) (1164:1164:1164)) - (PORT datac (1167:1167:1167) (1153:1153:1153)) - (PORT datad (1172:1172:1172) (1180:1180:1180)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1049:1049:1049) (1030:1030:1030)) - (PORT datac (570:570:570) (565:565:565)) - (PORT datad (158:158:158) (178:178:178)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~28) - (DELAY - (ABSOLUTE - (PORT dataa (215:215:215) (256:256:256)) - (PORT datab (199:199:199) (231:231:231)) - (PORT datac (1059:1059:1059) (1076:1076:1076)) - (PORT datad (177:177:177) (197:197:197)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~35) - (DELAY - (ABSOLUTE - (PORT datab (1858:1858:1858) (1864:1864:1864)) - (PORT datac (1247:1247:1247) (1235:1235:1235)) - (PORT datad (790:790:790) (789:789:789)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~36) - (DELAY - (ABSOLUTE - (PORT dataa (196:196:196) (240:240:240)) - (PORT datab (840:840:840) (833:833:833)) - (PORT datac (578:578:578) (576:576:576)) - (PORT datad (849:849:849) (870:870:870)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1397:1397:1397) (1416:1416:1416)) - (PORT datab (1081:1081:1081) (1069:1069:1069)) - (PORT datac (1016:1016:1016) (1034:1034:1034)) - (PORT datad (505:505:505) (499:499:499)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~31) - (DELAY - (ABSOLUTE - (PORT dataa (573:573:573) (580:580:580)) - (PORT datab (213:213:213) (251:251:251)) - (PORT datac (1050:1050:1050) (1062:1062:1062)) - (PORT datad (179:179:179) (201:201:201)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~29) - (DELAY - (ABSOLUTE - (PORT dataa (1502:1502:1502) (1572:1572:1572)) - (PORT datab (938:938:938) (988:988:988)) - (PORT datac (951:951:951) (1012:1012:1012)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (308:308:308) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1081:1081:1081) (1102:1102:1102)) - (PORT datab (1421:1421:1421) (1474:1474:1474)) - (PORT datad (184:184:184) (207:207:207)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (825:825:825) (825:825:825)) - (PORT datab (529:529:529) (526:526:526)) - (PORT datac (561:561:561) (561:561:561)) - (PORT datad (557:557:557) (551:551:551)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal33\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1126:1126:1126) (1167:1167:1167)) - (PORT datab (1177:1177:1177) (1248:1248:1248)) - (PORT datac (1063:1063:1063) (1080:1080:1080)) - (PORT datad (650:650:650) (693:693:693)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~0) - (DELAY - (ABSOLUTE - (PORT dataa (642:642:642) (658:658:658)) - (PORT datab (1248:1248:1248) (1207:1207:1207)) - (PORT datac (1129:1129:1129) (1140:1140:1140)) - (PORT datad (1536:1536:1536) (1551:1551:1551)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (933:933:933) (979:979:979)) - (PORT datab (833:833:833) (842:842:842)) - (PORT datac (154:154:154) (184:184:184)) - (PORT datad (202:202:202) (225:225:225)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we_lo\~2) - (DELAY - (ABSOLUTE - (PORT dataa (947:947:947) (1023:1023:1023)) - (PORT datac (2019:2019:2019) (2030:2030:2030)) - (PORT datad (599:599:599) (636:636:636)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we_lo\~3) - (DELAY - (ABSOLUTE - (PORT dataa (667:667:667) (697:697:697)) - (PORT datab (1056:1056:1056) (1042:1042:1042)) - (PORT datac (155:155:155) (186:186:186)) - (PORT datad (1057:1057:1057) (1062:1062:1062)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we_lo\~4) - (DELAY - (ABSOLUTE - (PORT dataa (939:939:939) (993:993:993)) - (PORT datab (618:618:618) (616:616:616)) - (PORT datac (929:929:929) (990:990:990)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo) - (DELAY - (ABSOLUTE - (PORT dataa (190:190:190) (230:230:230)) - (PORT datab (182:182:182) (216:216:216)) - (PORT datac (163:163:163) (197:197:197)) - (PORT datad (863:863:863) (870:870:870)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_ir\~0) - (DELAY - (ABSOLUTE - (PORT datab (251:251:251) (327:327:327)) - (PORT datac (217:217:217) (285:285:285)) - (PORT datad (223:223:223) (285:285:285)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_ir\~1) - (DELAY - (ABSOLUTE - (PORT dataa (879:879:879) (887:887:887)) - (PORT datab (199:199:199) (232:232:232)) - (PORT datac (1024:1024:1024) (1002:1002:1002)) - (PORT datad (160:160:160) (182:182:182)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1021:1021:1021) (1095:1095:1095)) - (PORT datab (200:200:200) (233:233:233)) - (PORT datac (592:592:592) (638:638:638)) - (PORT datad (891:891:891) (959:959:959)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (2372:2372:2372) (2400:2400:2400)) - (PORT datab (1481:1481:1481) (1548:1548:1548)) - (PORT datac (175:175:175) (207:207:207)) - (PORT datad (199:199:199) (236:236:236)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (987:987:987) (1008:1008:1008)) - (PORT datab (186:186:186) (221:221:221)) - (PORT datac (822:822:822) (802:802:802)) - (PORT datad (770:770:770) (760:760:760)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_ixy_dT5_7) - (DELAY - (ABSOLUTE - (PORT datab (852:852:852) (879:879:879)) - (PORT datad (579:579:579) (590:590:590)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~4) - (DELAY - (ABSOLUTE - (PORT dataa (581:581:581) (607:607:607)) - (PORT datab (843:843:843) (873:873:873)) - (PORT datac (998:998:998) (992:992:992)) - (PORT datad (183:183:183) (207:207:207)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~4) - (DELAY - (ABSOLUTE - (PORT dataa (827:827:827) (855:855:855)) - (PORT datab (836:836:836) (832:832:832)) - (PORT datac (577:577:577) (600:600:600)) - (PORT datad (826:826:826) (816:816:816)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla56M3T3_6) - (DELAY - (ABSOLUTE - (PORT dataa (1848:1848:1848) (1914:1914:1914)) - (PORT datab (833:833:833) (859:859:859)) - (PORT datac (197:197:197) (239:239:239)) - (PORT datad (1066:1066:1066) (1061:1061:1061)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~5) - (DELAY - (ABSOLUTE - (PORT dataa (853:853:853) (886:886:886)) - (PORT datab (847:847:847) (864:864:864)) - (PORT datac (815:815:815) (817:817:817)) - (PORT datad (555:555:555) (563:563:563)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~6) - (DELAY - (ABSOLUTE - (PORT dataa (833:833:833) (845:845:845)) - (PORT datad (164:164:164) (189:189:189)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1003:1003:1003) (988:988:988)) - (PORT datab (828:828:828) (845:845:845)) - (PORT datac (561:561:561) (591:591:591)) - (PORT datad (799:799:799) (810:810:810)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\~16) - (DELAY - (ABSOLUTE - (PORT dataa (2231:2231:2231) (2295:2295:2295)) - (PORT datab (1676:1676:1676) (1732:1732:1732)) - (PORT datac (994:994:994) (967:967:967)) - (PORT datad (1468:1468:1468) (1554:1554:1554)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~11) - (DELAY - (ABSOLUTE - (PORT dataa (769:769:769) (746:746:746)) - (PORT datab (846:846:846) (845:845:845)) - (PORT datac (771:771:771) (772:772:772)) - (PORT datad (159:159:159) (179:179:179)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (2232:2232:2232) (2296:2296:2296)) - (PORT datab (2223:2223:2223) (2283:2283:2283)) - (PORT datac (1302:1302:1302) (1339:1339:1339)) - (PORT datad (1465:1465:1465) (1553:1553:1553)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~12) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (207:207:207) (245:245:245)) - (PORT datac (183:183:183) (220:220:220)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1150:1150:1150) (1196:1196:1196)) - (PORT datab (182:182:182) (215:215:215)) - (PORT datac (769:769:769) (746:746:746)) - (PORT datad (807:807:807) (817:817:817)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (817:817:817) (796:796:796)) - (PORT datab (216:216:216) (254:254:254)) - (PORT datac (572:572:572) (594:594:594)) - (PORT datad (1245:1245:1245) (1260:1260:1260)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~38) - (DELAY - (ABSOLUTE - (PORT dataa (1130:1130:1130) (1195:1195:1195)) - (PORT datab (1281:1281:1281) (1366:1366:1366)) - (PORT datac (800:800:800) (838:838:838)) - (PORT datad (779:779:779) (766:766:766)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1902:1902:1902) (1924:1924:1924)) - (PORT datab (2319:2319:2319) (2469:2469:2469)) - (PORT datac (2661:2661:2661) (2717:2717:2717)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~24) - (DELAY - (ABSOLUTE - (PORT datab (786:786:786) (805:805:805)) - (PORT datac (919:919:919) (926:926:926)) - (PORT datad (1273:1273:1273) (1259:1259:1259)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (197:197:197) (241:241:241)) - (PORT datac (609:609:609) (621:621:621)) - (PORT datad (955:955:955) (992:992:992)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1226:1226:1226) (1317:1317:1317)) - (PORT datac (1093:1093:1093) (1091:1091:1091)) - (PORT datad (1863:1863:1863) (1900:1900:1900)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1036:1036:1036) (1029:1029:1029)) - (PORT datab (204:204:204) (240:240:240)) - (PORT datac (557:557:557) (554:554:554)) - (PORT datad (1064:1064:1064) (1079:1079:1079)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1023:1023:1023) (1113:1113:1113)) - (PORT datac (1050:1050:1050) (1044:1044:1044)) - (PORT datad (880:880:880) (917:917:917)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3) - (DELAY - (ABSOLUTE - (PORT datab (1942:1942:1942) (1961:1961:1961)) - (PORT datac (856:856:856) (896:896:896)) - (PORT datad (1825:1825:1825) (1843:1843:1843)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (1094:1094:1094) (1117:1117:1117)) - (PORT datab (565:565:565) (549:549:549)) - (PORT datac (806:806:806) (820:820:820)) - (PORT datad (1059:1059:1059) (1068:1068:1068)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (1048:1048:1048) (1033:1033:1033)) - (PORT datab (553:553:553) (543:543:543)) - (PORT datac (1042:1042:1042) (1045:1045:1045)) - (PORT datad (810:810:810) (811:811:811)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1663:1663:1663) (1690:1690:1690)) - (PORT datab (1460:1460:1460) (1462:1462:1462)) - (PORT datad (920:920:920) (921:921:921)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (852:852:852) (853:853:853)) - (PORT datab (1074:1074:1074) (1100:1100:1100)) - (PORT datac (1370:1370:1370) (1409:1409:1409)) - (PORT datad (1025:1025:1025) (1017:1017:1017)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (648:648:648) (656:656:656)) - (PORT datab (843:843:843) (834:834:834)) - (PORT datac (575:575:575) (572:572:572)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (217:217:217)) - (PORT datab (182:182:182) (213:213:213)) - (PORT datac (1401:1401:1401) (1413:1413:1413)) - (PORT datad (158:158:158) (178:178:178)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (853:853:853) (855:855:855)) - (PORT datab (829:829:829) (870:870:870)) - (PORT datac (169:169:169) (207:207:207)) - (PORT datad (816:816:816) (798:798:798)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (181:181:181) (217:217:217)) - (PORT datab (180:180:180) (212:212:212)) - (PORT datac (1591:1591:1591) (1613:1613:1613)) - (PORT datad (303:303:303) (314:314:314)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (1101:1101:1101) (1097:1097:1097)) - (PORT datab (780:780:780) (766:766:766)) - (PORT datac (784:784:784) (778:778:778)) - (PORT datad (161:161:161) (182:182:182)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1431:1431:1431) (1492:1492:1492)) - (PORT datab (1625:1625:1625) (1632:1632:1632)) - (PORT datac (2403:2403:2403) (2409:2409:2409)) - (PORT datad (1067:1067:1067) (1081:1081:1081)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (2438:2438:2438) (2445:2445:2445)) - (PORT datab (1459:1459:1459) (1552:1552:1552)) - (PORT datac (581:581:581) (581:581:581)) - (PORT datad (185:185:185) (212:212:212)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (572:572:572) (563:563:563)) - (PORT datab (604:604:604) (616:616:616)) - (PORT datac (583:583:583) (607:607:607)) - (PORT datad (790:790:790) (806:806:806)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_62) - (DELAY - (ABSOLUTE - (PORT datab (659:659:659) (665:665:665)) - (PORT datac (981:981:981) (963:963:963)) - (PORT datad (842:842:842) (856:856:856)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~38) - (DELAY - (ABSOLUTE - (PORT dataa (333:333:333) (357:357:357)) - (PORT datab (1036:1036:1036) (1034:1034:1034)) - (PORT datac (965:965:965) (955:955:955)) - (PORT datad (773:773:773) (761:761:761)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~39) - (DELAY - (ABSOLUTE - (PORT dataa (1599:1599:1599) (1605:1605:1605)) - (PORT datab (824:824:824) (816:816:816)) - (PORT datac (1393:1393:1393) (1460:1460:1460)) - (PORT datad (1048:1048:1048) (1075:1075:1075)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~30) - (DELAY - (ABSOLUTE - (PORT dataa (1064:1064:1064) (1034:1034:1034)) - (PORT datab (1534:1534:1534) (1529:1529:1529)) - (PORT datac (1059:1059:1059) (1072:1072:1072)) - (PORT datad (194:194:194) (224:224:224)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~45) - (DELAY - (ABSOLUTE - (PORT dataa (621:621:621) (626:626:626)) - (PORT datab (1072:1072:1072) (1065:1065:1065)) - (PORT datac (1092:1092:1092) (1109:1109:1109)) - (PORT datad (891:891:891) (936:936:936)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~1) - (DELAY - (ABSOLUTE - (PORT dataa (266:266:266) (330:330:330)) - (PORT datac (1563:1563:1563) (1574:1574:1574)) - (PORT datad (394:394:394) (428:428:428)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~36) - (DELAY - (ABSOLUTE - (PORT dataa (611:611:611) (623:623:623)) - (PORT datab (1068:1068:1068) (1096:1096:1096)) - (PORT datac (1370:1370:1370) (1407:1407:1407)) - (PORT datad (1176:1176:1176) (1194:1194:1194)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~27) - (DELAY - (ABSOLUTE - (PORT dataa (1333:1333:1333) (1335:1335:1335)) - (PORT datab (846:846:846) (864:864:864)) - (PORT datac (830:830:830) (829:829:829)) - (PORT datad (893:893:893) (897:897:897)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~28) - (DELAY - (ABSOLUTE - (PORT dataa (814:814:814) (806:806:806)) - (PORT datac (924:924:924) (944:944:944)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~37) - (DELAY - (ABSOLUTE - (PORT dataa (984:984:984) (1014:1014:1014)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (1006:1006:1006) (987:987:987)) - (PORT datad (165:165:165) (188:188:188)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~40) - (DELAY - (ABSOLUTE - (PORT dataa (322:322:322) (331:331:331)) - (PORT datab (180:180:180) (212:212:212)) - (PORT datac (320:320:320) (344:344:344)) - (PORT datad (793:793:793) (779:779:779)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~35) - (DELAY - (ABSOLUTE - (PORT dataa (1310:1310:1310) (1282:1282:1282)) - (PORT datab (770:770:770) (753:753:753)) - (PORT datac (1562:1562:1562) (1571:1571:1571)) - (PORT datad (851:851:851) (864:864:864)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~77) - (DELAY - (ABSOLUTE - (PORT dataa (1022:1022:1022) (1026:1026:1026)) - (PORT datab (620:620:620) (624:624:624)) - (PORT datac (805:805:805) (782:782:782)) - (PORT datad (811:811:811) (819:819:819)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~32) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (249:249:249)) - (PORT datab (594:594:594) (608:608:608)) - (PORT datac (1273:1273:1273) (1300:1300:1300)) - (PORT datad (1052:1052:1052) (1059:1059:1059)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla91pla21M4T2_3\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1503:1503:1503) (1574:1574:1574)) - (PORT datab (939:939:939) (984:984:984)) - (PORT datac (1792:1792:1792) (1771:1771:1771)) - (PORT datad (1535:1535:1535) (1547:1547:1547)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~33) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (237:237:237)) - (PORT datab (182:182:182) (214:214:214)) - (PORT datac (155:155:155) (185:185:185)) - (PORT datad (598:598:598) (624:624:624)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~34) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (246:246:246)) - (PORT datab (598:598:598) (591:591:591)) - (PORT datac (181:181:181) (215:215:215)) - (PORT datad (1100:1100:1100) (1080:1080:1080)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~41) - (DELAY - (ABSOLUTE - (PORT dataa (181:181:181) (217:217:217)) - (PORT datab (949:949:949) (970:970:970)) - (PORT datac (157:157:157) (187:187:187)) - (PORT datad (552:552:552) (562:562:562)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~10) - (DELAY - (ABSOLUTE - (PORT dataa (831:831:831) (859:859:859)) - (PORT datab (1049:1049:1049) (1051:1051:1051)) - (PORT datac (814:814:814) (819:819:819)) - (PORT datad (1055:1055:1055) (1070:1070:1070)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~11) - (DELAY - (ABSOLUTE - (PORT datab (199:199:199) (231:231:231)) - (PORT datac (547:547:547) (579:579:579)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~3) - (DELAY - (ABSOLUTE - (PORT dataa (194:194:194) (238:238:238)) - (PORT datac (514:514:514) (511:511:511)) - (PORT datad (750:750:750) (794:794:794)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1201:1201:1201) (1239:1239:1239)) - (PORT datab (610:610:610) (611:611:611)) - (PORT datac (176:176:176) (208:208:208)) - (PORT datad (1090:1090:1090) (1098:1098:1098)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~2) - (DELAY - (ABSOLUTE - (PORT dataa (527:527:527) (521:521:521)) - (PORT datac (731:731:731) (762:762:762)) - (PORT datad (724:724:724) (755:755:755)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~5) - (DELAY - (ABSOLUTE - (PORT dataa (844:844:844) (850:850:850)) - (PORT datab (615:615:615) (631:631:631)) - (PORT datac (349:349:349) (360:360:360)) - (PORT datad (549:549:549) (569:569:569)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~45) - (DELAY - (ABSOLUTE - (PORT dataa (586:586:586) (619:619:619)) - (PORT datab (810:810:810) (784:784:784)) - (PORT datac (794:794:794) (808:808:808)) - (PORT datad (591:591:591) (614:614:614)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~46) - (DELAY - (ABSOLUTE - (PORT datab (767:767:767) (753:753:753)) - (PORT datac (180:180:180) (215:215:215)) - (PORT datad (1316:1316:1316) (1348:1348:1348)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~1) - (DELAY - (ABSOLUTE - (PORT dataa (551:551:551) (542:542:542)) - (PORT datab (860:860:860) (874:874:874)) - (PORT datac (541:541:541) (537:537:537)) - (PORT datad (552:552:552) (548:548:548)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~0) - (DELAY - (ABSOLUTE - (PORT dataa (895:895:895) (904:904:904)) - (PORT datab (1439:1439:1439) (1492:1492:1492)) - (PORT datac (778:778:778) (780:780:780)) - (PORT datad (347:347:347) (357:357:357)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~6) - (DELAY - (ABSOLUTE - (PORT dataa (188:188:188) (225:225:225)) - (PORT datab (317:317:317) (334:334:334)) - (PORT datac (189:189:189) (227:227:227)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~4) - (DELAY - (ABSOLUTE - (PORT dataa (853:853:853) (859:859:859)) - (PORT datac (801:801:801) (843:843:843)) - (PORT datad (777:777:777) (765:765:765)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~16) - (DELAY - (ABSOLUTE - (PORT dataa (595:595:595) (609:609:609)) - (PORT datab (1386:1386:1386) (1385:1385:1385)) - (PORT datac (759:759:759) (755:755:755)) - (PORT datad (767:767:767) (781:781:781)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~14) - (DELAY - (ABSOLUTE - (PORT dataa (412:412:412) (456:456:456)) - (PORT datab (863:863:863) (880:880:880)) - (PORT datac (347:347:347) (362:362:362)) - (PORT datad (1765:1765:1765) (1823:1823:1823)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~20) - (DELAY - (ABSOLUTE - (PORT dataa (2276:2276:2276) (2425:2425:2425)) - (PORT datab (513:513:513) (511:511:511)) - (PORT datac (825:825:825) (840:840:840)) - (PORT datad (1041:1041:1041) (1050:1050:1050)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~15) - (DELAY - (ABSOLUTE - (PORT dataa (596:596:596) (620:620:620)) - (PORT datab (539:539:539) (531:531:531)) - (PORT datac (725:725:725) (754:754:754)) - (PORT datad (184:184:184) (208:208:208)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~17) - (DELAY - (ABSOLUTE - (PORT dataa (548:548:548) (551:551:551)) - (PORT datab (811:811:811) (812:812:812)) - (PORT datac (1834:1834:1834) (1833:1833:1833)) - (PORT datad (558:558:558) (552:552:552)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1067:1067:1067) (1036:1036:1036)) - (PORT datab (1449:1449:1449) (1509:1509:1509)) - (PORT datac (592:592:592) (615:615:615)) - (PORT datad (560:560:560) (573:573:573)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~19) - (DELAY - (ABSOLUTE - (PORT dataa (824:824:824) (822:822:822)) - (PORT datab (522:522:522) (518:518:518)) - (PORT datac (567:567:567) (580:580:580)) - (PORT datad (159:159:159) (181:181:181)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_pc\~3) - (DELAY - (ABSOLUTE - (PORT dataa (582:582:582) (608:608:608)) - (PORT datab (843:843:843) (873:873:873)) - (PORT datac (499:499:499) (485:485:485)) - (PORT datad (808:808:808) (804:804:804)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_pc) - (DELAY - (ABSOLUTE - (PORT dataa (209:209:209) (249:249:249)) - (PORT datab (604:604:604) (610:610:610)) - (PORT datac (777:777:777) (770:770:770)) - (PORT datad (321:321:321) (324:324:324)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_74) - (DELAY - (ABSOLUTE - (PORT datab (1339:1339:1339) (1361:1361:1361)) - (PORT datac (845:845:845) (849:849:849)) - (PORT datad (758:758:758) (746:746:746)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (249:249:249)) - (PORT datab (1244:1244:1244) (1192:1192:1192)) - (PORT datac (1279:1279:1279) (1261:1261:1261)) - (PORT datad (291:291:291) (298:298:298)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_75) - (DELAY - (ABSOLUTE - (PORT datab (868:868:868) (895:895:895)) - (PORT datac (1335:1335:1335) (1361:1361:1361)) - (PORT datad (622:622:622) (633:633:633)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1362:1362:1362)) - (PORT asdata (890:890:890) (916:916:916)) - (PORT ena (1105:1105:1105) (1078:1078:1078)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (1743:1743:1743) (1706:1706:1706)) - (PORT datab (649:649:649) (667:667:667)) - (PORT datad (1111:1111:1111) (1126:1126:1126)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -11245,875 +1319,52 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_63) + (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_12) (DELAY (ABSOLUTE - (PORT datab (661:661:661) (663:663:663)) - (PORT datac (983:983:983) (964:964:964)) - (PORT datad (844:844:844) (855:855:855)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT dataa (2589:2589:2589) (2609:2609:2609)) + (PORT datab (639:639:639) (691:691:691)) + (PORT datad (821:821:821) (863:863:863)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1363:1363:1363) (1384:1384:1384)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1175:1175:1175) (1170:1170:1170)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~23) - (DELAY - (ABSOLUTE - (PORT datab (677:677:677) (704:704:704)) - (PORT datac (571:571:571) (586:586:586)) - (PORT datad (198:198:198) (256:256:256)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_10\~0) - (DELAY - (ABSOLUTE - (PORT datac (1855:1855:1855) (1856:1856:1856)) - (IOPATH datac combout (218:218:218) (215:215:215)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_10) - (DELAY - (ABSOLUTE - (PORT clk (1370:1370:1370) (1377:1377:1377)) - (PORT d (67:67:67) (78:78:78)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_9) - (DELAY - (ABSOLUTE - (PORT clk (1370:1370:1370) (1377:1377:1377)) - (PORT asdata (513:513:513) (580:580:580)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|resets_\|DFFE_intr_ff3) - (DELAY - (ABSOLUTE - (PORT clk (1370:1370:1370) (1377:1377:1377)) - (PORT asdata (513:513:513) (581:581:581)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_io_ibuf") - (INSTANCE KEY\[0\]\~input) - (DELAY - (ABSOLUTE - (IOPATH i o (461:461:461) (708:708:708)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE reset) - (DELAY - (ABSOLUTE - (PORT datac (1395:1395:1395) (1420:1420:1420)) - (PORT datad (490:490:490) (462:462:462)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|resets_\|x1\~0) - (DELAY - (ABSOLUTE - (PORT datad (1368:1368:1368) (1388:1388:1388)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|fpga_reset) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1368:1368:1368)) - (PORT d (67:67:67) (78:78:78)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) (CELL (CELLTYPE "cycloneive_clkctrl") - (INSTANCE z80_\|fpga_reset\~clkctrl) + (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_12\~clkctrl) (DELAY (ABSOLUTE - (PORT inclk[0] (666:666:666) (673:673:673)) + (PORT inclk[0] (997:997:997) (1001:1001:1001)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|resets_\|x1) - (DELAY - (ABSOLUTE - (PORT clk (1343:1343:1343) (1354:1354:1354)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1667:1667:1667) (1646:1646:1646)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|resets_\|clrpc_int\~0) - (DELAY - (ABSOLUTE - (PORT dataa (604:604:604) (644:644:644)) - (PORT datab (568:568:568) (588:588:588)) - (PORT datad (1091:1091:1091) (1101:1101:1101)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (312:312:312)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|resets_\|clrpc_int) - (DELAY - (ABSOLUTE - (PORT clk (1370:1370:1370) (1377:1377:1377)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1409:1409:1409) (1380:1380:1380)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|resets_\|clrpc\~0) - (DELAY - (ABSOLUTE - (PORT dataa (228:228:228) (302:302:302)) - (PORT datab (230:230:230) (302:302:302)) - (PORT datad (198:198:198) (254:254:254)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[7\]) - (DELAY - (ABSOLUTE - (PORT datac (609:609:609) (625:625:625)) - (PORT datad (564:564:564) (566:566:566)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_apin_mux\~1) - (DELAY - (ABSOLUTE - (PORT dataa (2273:2273:2273) (2429:2429:2429)) - (PORT datac (825:825:825) (843:843:843)) - (PORT datad (1842:1842:1842) (1863:1863:1863)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (341:341:341) (351:351:351)) - (PORT datab (517:517:517) (516:516:516)) - (PORT datac (782:782:782) (783:783:783)) - (PORT datad (1040:1040:1040) (1050:1050:1050)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1033:1033:1033) (1044:1044:1044)) - (PORT datab (1069:1069:1069) (1075:1075:1075)) - (PORT datac (742:742:742) (726:726:726)) - (PORT datad (591:591:591) (584:584:584)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (912:912:912) (948:948:948)) - (PORT datab (1520:1520:1520) (1487:1487:1487)) - (PORT datac (157:157:157) (188:188:188)) - (PORT datad (1059:1059:1059) (1072:1072:1072)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1127:1127:1127) (1168:1168:1168)) - (PORT datab (921:921:921) (984:984:984)) - (PORT datac (599:599:599) (642:642:642)) - (PORT datad (1151:1151:1151) (1210:1210:1210)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~9) - (DELAY - (ABSOLUTE - (PORT dataa (727:727:727) (703:703:703)) - (PORT datab (610:610:610) (603:603:603)) - (PORT datac (777:777:777) (798:798:798)) - (PORT datad (957:957:957) (972:972:972)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~10) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (219:219:219)) - (PORT datab (659:659:659) (658:658:658)) - (PORT datac (181:181:181) (214:214:214)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~11) - (DELAY - (ABSOLUTE - (PORT dataa (185:185:185) (222:222:222)) - (PORT datac (164:164:164) (200:200:200)) - (PORT datad (506:506:506) (506:506:506)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1152:1152:1152) (1192:1192:1192)) - (PORT datab (776:776:776) (746:746:746)) - (PORT datac (772:772:772) (748:748:748)) - (PORT datad (809:809:809) (817:817:817)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1400:1400:1400) (1370:1370:1370)) - (PORT ena (1981:1981:1981) (2010:2010:2010)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~6) - (DELAY - (ABSOLUTE - (PORT dataa (378:378:378) (387:387:387)) - (PORT datab (1678:1678:1678) (1697:1697:1697)) - (PORT datac (181:181:181) (214:214:214)) - (PORT datad (594:594:594) (626:626:626)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1125:1125:1125) (1167:1167:1167)) - (PORT datab (1853:1853:1853) (1913:1913:1913)) - (PORT datac (1198:1198:1198) (1284:1284:1284)) - (PORT datad (1866:1866:1866) (1903:1903:1903)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~8) - (DELAY - (ABSOLUTE - (PORT dataa (356:356:356) (367:367:367)) - (PORT datab (192:192:192) (233:233:233)) - (PORT datac (1025:1025:1025) (1018:1018:1018)) - (PORT datad (1111:1111:1111) (1100:1100:1100)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~9) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (239:239:239)) - (PORT datab (1573:1573:1573) (1616:1616:1616)) - (PORT datac (518:518:518) (494:494:494)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~10) - (DELAY - (ABSOLUTE - (PORT datab (919:919:919) (924:924:924)) - (PORT datac (1042:1042:1042) (1028:1028:1028)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~7) - (DELAY - (ABSOLUTE - (PORT dataa (927:927:927) (951:951:951)) - (PORT datad (1038:1038:1038) (1031:1031:1031)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[2\]) + (INSTANCE z80_\|interrupts_\|DFFE_instIFF2) (DELAY (ABSOLUTE (PORT clk (1363:1363:1363) (1384:1384:1384)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (1175:1175:1175) (1170:1170:1170)) + (PORT clrn (1380:1380:1380) (1358:1358:1358)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) ) (TIMINGCHECK (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_54) + (INSTANCE z80_\|pla_decode_\|Equal13\~0) (DELAY (ABSOLUTE - (PORT datab (1448:1448:1448) (1428:1428:1428)) - (PORT datac (1112:1112:1112) (1131:1131:1131)) - (PORT datad (1000:1000:1000) (984:984:984)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_58) - (DELAY - (ABSOLUTE - (PORT datab (1445:1445:1445) (1427:1427:1427)) - (PORT datac (1120:1120:1120) (1140:1140:1140)) - (PORT datad (914:914:914) (922:922:922)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_55) - (DELAY - (ABSOLUTE - (PORT datab (1444:1444:1444) (1428:1428:1428)) - (PORT datac (1121:1121:1121) (1141:1141:1141)) - (PORT datad (1001:1001:1001) (984:984:984)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1338:1338:1338) (1356:1356:1356)) - (PORT asdata (1304:1304:1304) (1285:1285:1285)) - (PORT ena (1588:1588:1588) (1555:1555:1555)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_59) - (DELAY - (ABSOLUTE - (PORT datab (1449:1449:1449) (1432:1432:1432)) - (PORT datac (1106:1106:1106) (1125:1125:1125)) - (PORT datad (919:919:919) (927:927:927)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1338:1338:1338) (1356:1356:1356)) - (PORT asdata (1304:1304:1304) (1285:1285:1285)) - (PORT ena (1297:1297:1297) (1275:1275:1275)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (808:808:808) (840:840:840)) - (PORT datab (886:886:886) (937:937:937)) - (PORT datad (196:196:196) (252:252:252)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_51) - (DELAY - (ABSOLUTE - (PORT datab (1300:1300:1300) (1274:1274:1274)) - (PORT datac (1084:1084:1084) (1079:1079:1079)) - (PORT datad (546:546:546) (554:554:554)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1362:1362:1362)) - (PORT asdata (668:668:668) (669:669:669)) - (PORT ena (735:735:735) (733:733:733)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_de2\~4) - (DELAY - (ABSOLUTE - (PORT dataa (343:343:343) (359:359:359)) - (PORT datab (200:200:200) (245:245:245)) - (PORT datac (200:200:200) (269:269:269)) - (PORT datad (1129:1129:1129) (1170:1170:1170)) + (PORT dataa (259:259:259) (343:343:343)) + (PORT datac (365:365:365) (418:418:418)) + (PORT datad (363:363:363) (400:400:400)) (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_46) - (DELAY - (ABSOLUTE - (PORT datab (1107:1107:1107) (1100:1100:1100)) - (PORT datac (587:587:587) (609:609:609)) - (PORT datad (1264:1264:1264) (1244:1244:1244)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_47) - (DELAY - (ABSOLUTE - (PORT datab (1109:1109:1109) (1104:1104:1104)) - (PORT datac (588:588:588) (608:608:608)) - (PORT datad (1264:1264:1264) (1238:1238:1238)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1362:1362:1362)) - (PORT asdata (667:667:667) (668:668:668)) - (PORT ena (763:763:763) (771:771:771)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (222:222:222) (295:295:295)) - (PORT datab (231:231:231) (284:284:284)) - (PORT datad (211:211:211) (246:246:246)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_71\~2) - (DELAY - (ABSOLUTE - (PORT datac (836:836:836) (843:843:843)) - (PORT datad (1245:1245:1245) (1229:1229:1229)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_43\~0) - (DELAY - (ABSOLUTE - (PORT dataa (645:645:645) (680:680:680)) - (PORT datab (1084:1084:1084) (1078:1078:1078)) - (PORT datac (174:174:174) (214:214:214)) - (PORT datad (1330:1330:1330) (1362:1362:1362)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1342:1342:1342) (1359:1359:1359)) - (PORT asdata (1094:1094:1094) (1096:1096:1096)) - (PORT ena (1155:1155:1155) (1140:1140:1140)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_39\~0) - (DELAY - (ABSOLUTE - (PORT dataa (640:640:640) (681:681:681)) - (PORT datab (1081:1081:1081) (1078:1078:1078)) - (PORT datac (175:175:175) (213:213:213)) - (PORT datad (1333:1333:1333) (1363:1363:1363)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1342:1342:1342) (1359:1359:1359)) - (PORT asdata (1095:1095:1095) (1094:1094:1094)) - (PORT ena (1109:1109:1109) (1074:1074:1074)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (405:405:405) (444:444:444)) - (PORT datab (220:220:220) (288:288:288)) - (PORT datad (587:587:587) (590:590:590)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_83) - (DELAY - (ABSOLUTE - (PORT dataa (595:595:595) (593:593:593)) - (PORT datab (869:869:869) (890:890:890)) - (PORT datad (623:623:623) (628:628:628)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1370:1370:1370)) - (PORT asdata (1550:1550:1550) (1525:1525:1525)) - (PORT ena (1380:1380:1380) (1365:1365:1365)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (607:607:607) (603:603:603)) - (PORT datab (1301:1301:1301) (1284:1284:1284)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_79\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1065:1065:1065) (1076:1076:1076)) - (PORT datab (1080:1080:1080) (1077:1077:1077)) - (PORT datac (174:174:174) (213:213:213)) - (PORT datad (614:614:614) (636:636:636)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1370:1370:1370)) - (PORT asdata (1121:1121:1121) (1124:1124:1124)) - (PORT ena (1123:1123:1123) (1106:1106:1106)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~39) - (DELAY - (ABSOLUTE - (PORT dataa (850:850:850) (845:845:845)) - (PORT datab (385:385:385) (422:422:422)) - (PORT datac (853:853:853) (854:854:854)) - (PORT datad (566:566:566) (575:575:575)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (273:273:273) (275:275:275)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -12121,716 +1372,64 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_iy\~2) + (INSTANCE z80_\|pla_decode_\|Equal38\~2) (DELAY (ABSOLUTE - (PORT dataa (832:832:832) (861:861:861)) - (PORT datab (871:871:871) (892:892:892)) - (PORT datac (1053:1053:1053) (1048:1048:1048)) - (PORT datad (356:356:356) (371:371:371)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_70) - (DELAY - (ABSOLUTE - (PORT datab (863:863:863) (889:889:889)) - (PORT datac (1245:1245:1245) (1225:1225:1225)) - (PORT datad (819:819:819) (837:837:837)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_67\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1088:1088:1088) (1108:1108:1108)) - (PORT datab (1086:1086:1086) (1078:1078:1078)) - (PORT datac (174:174:174) (214:214:214)) - (PORT datad (624:624:624) (642:642:642)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1370:1370:1370)) - (PORT asdata (1551:1551:1551) (1526:1526:1526)) - (PORT ena (1132:1132:1132) (1112:1112:1112)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_71) - (DELAY - (ABSOLUTE - (PORT dataa (1680:1680:1680) (1620:1620:1620)) - (PORT datab (844:844:844) (872:872:872)) - (PORT datad (840:840:840) (857:857:857)) + (PORT dataa (1444:1444:1444) (1533:1533:1533)) + (PORT datab (1387:1387:1387) (1391:1391:1391)) + (PORT datac (1259:1259:1259) (1371:1371:1371)) + (PORT datad (1411:1411:1411) (1455:1455:1455)) (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1370:1370:1370)) - (PORT asdata (1122:1122:1122) (1126:1126:1126)) - (PORT ena (744:744:744) (751:751:751)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~38) - (DELAY - (ABSOLUTE - (PORT dataa (394:394:394) (415:415:415)) - (PORT datab (583:583:583) (608:608:608)) - (PORT datad (337:337:337) (366:366:366)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_31) - (DELAY - (ABSOLUTE - (PORT dataa (1612:1612:1612) (1601:1601:1601)) - (PORT datab (1087:1087:1087) (1086:1086:1086)) - (PORT datad (743:743:743) (706:706:706)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1371:1371:1371)) - (PORT asdata (1298:1298:1298) (1281:1281:1281)) - (PORT ena (746:746:746) (759:759:759)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (784:784:784) (790:790:790)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_35) - (DELAY - (ABSOLUTE - (PORT datab (977:977:977) (950:950:950)) - (PORT datac (843:843:843) (859:859:859)) - (PORT datad (821:821:821) (834:834:834)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1371:1371:1371)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1154:1154:1154) (1142:1142:1142)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (381:381:381) (423:423:423)) - (PORT datab (543:543:543) (552:552:552)) - (PORT datad (197:197:197) (253:253:253)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~40) + (INSTANCE z80_\|interrupts_\|iff1\~1) (DELAY (ABSOLUTE (PORT dataa (183:183:183) (219:219:219)) - (PORT datab (183:183:183) (216:216:216)) - (PORT datac (155:155:155) (185:185:185)) - (PORT datad (497:497:497) (482:482:482)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~41) - (DELAY - (ABSOLUTE - (PORT dataa (610:610:610) (617:617:617)) - (PORT datab (182:182:182) (215:215:215)) - (PORT datad (727:727:727) (719:719:719)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~42) - (DELAY - (ABSOLUTE - (PORT dataa (350:350:350) (356:356:356)) - (PORT datab (579:579:579) (582:582:582)) - (PORT datac (1289:1289:1289) (1259:1259:1259)) - (PORT datad (578:578:578) (598:598:598)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1362:1362:1362)) - (PORT asdata (1299:1299:1299) (1282:1282:1282)) - (PORT ena (1105:1105:1105) (1078:1078:1078)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (238:238:238)) - (PORT datab (1144:1144:1144) (1154:1154:1154)) - (PORT datad (603:603:603) (628:628:628)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~8) - (DELAY - (ABSOLUTE - (PORT datab (632:632:632) (639:639:639)) - (PORT datac (1056:1056:1056) (1072:1072:1072)) - (PORT datad (158:158:158) (178:178:178)) + (PORT datab (921:921:921) (950:950:950)) + (PORT datac (218:218:218) (286:286:286)) + (PORT datad (1020:1020:1020) (1015:1015:1015)) + (IOPATH dataa combout (318:318:318) (323:323:323)) (IOPATH datab combout (295:295:295) (285:285:285)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_15) + (DELAY + (ABSOLUTE + (PORT dataa (450:450:450) (522:522:522)) + (PORT datac (240:240:240) (319:319:319)) + (PORT datad (2722:2722:2722) (2749:2749:2749)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[0\]) + (INSTANCE z80_\|interrupts_\|iff1) (DELAY (ABSOLUTE (PORT clk (1363:1363:1363) (1384:1384:1384)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (1175:1175:1175) (1170:1170:1170)) + (PORT clrn (1125:1125:1125) (1122:1122:1122)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) ) (TIMINGCHECK (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1362:1362:1362)) - (PORT asdata (1344:1344:1344) (1323:1323:1323)) - (PORT ena (735:735:735) (733:733:733)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1362:1362:1362)) - (PORT asdata (1344:1344:1344) (1323:1323:1323)) - (PORT ena (763:763:763) (771:771:771)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (222:222:222) (295:295:295)) - (PORT datab (232:232:232) (284:284:284)) - (PORT datad (211:211:211) (246:246:246)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1337:1337:1337) (1354:1354:1354)) - (PORT asdata (1095:1095:1095) (1097:1097:1097)) - (PORT ena (739:739:739) (742:742:742)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|db\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1103:1103:1103) (1101:1101:1101)) - (PORT datab (1444:1444:1444) (1427:1427:1427)) - (PORT datad (1001:1001:1001) (984:984:984)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1338:1338:1338) (1356:1356:1356)) - (PORT asdata (1365:1365:1365) (1374:1374:1374)) - (PORT ena (1297:1297:1297) (1275:1275:1275)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (587:587:587) (610:610:610)) - (PORT datab (1005:1005:1005) (1016:1016:1016)) - (PORT datad (860:860:860) (895:895:895)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1370:1370:1370)) - (PORT asdata (1126:1126:1126) (1114:1114:1114)) - (PORT ena (1123:1123:1123) (1106:1106:1106)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1370:1370:1370)) - (PORT asdata (1126:1126:1126) (1114:1114:1114)) - (PORT ena (744:744:744) (751:751:751)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (599:599:599) (636:636:636)) - (PORT datab (220:220:220) (289:289:289)) - (PORT datad (344:344:344) (355:355:355)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1342:1342:1342) (1359:1359:1359)) - (PORT asdata (1347:1347:1347) (1368:1368:1368)) - (PORT ena (1381:1381:1381) (1365:1365:1365)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (320:320:320) (337:337:337)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1342:1342:1342) (1359:1359:1359)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1155:1155:1155) (1140:1140:1140)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1342:1342:1342) (1359:1359:1359)) - (PORT asdata (1345:1345:1345) (1365:1365:1365)) - (PORT ena (1295:1295:1295) (1246:1246:1246)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (403:403:403) (439:439:439)) - (PORT datab (607:607:607) (599:599:599)) - (PORT datad (765:765:765) (749:749:749)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1123:1123:1123) (1128:1128:1128)) - (PORT datab (855:855:855) (860:860:860)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1342:1342:1342) (1359:1359:1359)) - (PORT asdata (869:869:869) (860:860:860)) - (PORT ena (1109:1109:1109) (1074:1074:1074)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (400:400:400) (435:435:435)) - (PORT datab (1063:1063:1063) (1045:1045:1045)) - (PORT datad (504:504:504) (492:492:492)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1371:1371:1371)) - (PORT asdata (1580:1580:1580) (1593:1593:1593)) - (PORT ena (746:746:746) (759:759:759)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1371:1371:1371)) - (PORT asdata (1580:1580:1580) (1596:1596:1596)) - (PORT ena (1154:1154:1154) (1142:1142:1142)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (386:386:386) (426:426:426)) - (PORT datab (538:538:538) (545:545:545)) - (PORT datad (197:197:197) (252:252:252)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (558:558:558) (578:578:578)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (322:322:322) (325:325:325)) - (PORT datad (550:550:550) (542:542:542)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (1119:1119:1119) (1114:1114:1114)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (1018:1018:1018) (1023:1023:1023)) - (PORT datad (763:763:763) (762:762:762)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1362:1362:1362)) - (PORT asdata (1466:1466:1466) (1434:1434:1434)) - (PORT ena (1105:1105:1105) (1078:1078:1078)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1083:1083:1083) (1062:1062:1062)) - (PORT datab (642:642:642) (660:660:660)) - (PORT datad (1099:1099:1099) (1118:1118:1118)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~1) - (DELAY - (ABSOLUTE - (PORT datab (222:222:222) (290:290:290)) - (PORT datac (648:648:648) (673:673:673)) - (PORT datad (775:775:775) (771:771:771)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~72) - (DELAY - (ABSOLUTE - (PORT dataa (863:863:863) (877:877:877)) - (PORT datab (849:849:849) (884:884:884)) - (PORT datac (1400:1400:1400) (1394:1394:1394)) - (PORT datad (613:613:613) (652:652:652)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) ) ) (CELL @@ -12842,103 +1441,12 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add0\~14) - (DELAY - (ABSOLUTE - (PORT datab (1297:1297:1297) (1300:1300:1300)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datab cout (385:385:385) (280:280:280)) - (IOPATH datad combout (119:119:119) (106:106:106)) - (IOPATH cin combout (408:408:408) (387:387:387)) - (IOPATH cin cout (50:50:50) (50:50:50)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add0\~16) - (DELAY - (ABSOLUTE - (PORT dataa (241:241:241) (314:314:314)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH dataa cout (376:376:376) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - (IOPATH cin combout (408:408:408) (387:387:387)) - (IOPATH cin cout (50:50:50) (50:50:50)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vga_hc\~2) - (DELAY - (ABSOLUTE - (PORT datac (777:777:777) (776:776:776)) - (PORT datad (159:159:159) (179:179:179)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_hc\[8\]) - (DELAY - (ABSOLUTE - (PORT clk (1354:1354:1354) (1369:1369:1369)) - (PORT d (67:67:67) (78:78:78)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add0\~18) - (DELAY - (ABSOLUTE - (PORT datad (609:609:609) (646:646:646)) - (IOPATH datad combout (119:119:119) (106:106:106)) - (IOPATH cin combout (408:408:408) (387:387:387)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vga_hc\~1) - (DELAY - (ABSOLUTE - (PORT datab (208:208:208) (246:246:246)) - (PORT datad (529:529:529) (517:517:517)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_hc\[9\]) - (DELAY - (ABSOLUTE - (PORT clk (1357:1357:1357) (1372:1372:1372)) - (PORT d (67:67:67) (78:78:78)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|Add0\~0) (DELAY (ABSOLUTE - (PORT datab (997:997:997) (981:981:981)) + (PORT datab (363:363:363) (411:411:411)) (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -12950,9 +1458,9 @@ (INSTANCE ula_\|video_\|vga_hc\~3) (DELAY (ABSOLUTE - (PORT datac (772:772:772) (785:785:785)) - (PORT datad (844:844:844) (838:838:838)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT datab (323:323:323) (332:332:332)) + (PORT datad (798:798:798) (800:800:800)) + (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -12962,13 +1470,13 @@ (INSTANCE ula_\|video_\|vga_hc\[0\]) (DELAY (ABSOLUTE - (PORT clk (1359:1359:1359) (1375:1375:1375)) - (PORT d (67:67:67) (78:78:78)) + (PORT clk (1688:1688:1688) (1706:1706:1706)) + (PORT asdata (1580:1580:1580) (1527:1527:1527)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) ) ) (CELL @@ -12976,7 +1484,7 @@ (INSTANCE ula_\|video_\|Add0\~2) (DELAY (ABSOLUTE - (PORT datab (629:629:629) (645:645:645)) + (PORT datab (1135:1135:1135) (1167:1167:1167)) (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -12985,28 +1493,18 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vga_hc\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (552:552:552) (552:552:552)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|video_\|vga_hc\[1\]) (DELAY (ABSOLUTE - (PORT clk (1357:1357:1357) (1373:1373:1373)) - (PORT d (67:67:67) (78:78:78)) + (PORT clk (1359:1359:1359) (1375:1375:1375)) + (PORT asdata (782:782:782) (764:764:764)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) ) ) (CELL @@ -13014,7 +1512,7 @@ (INSTANCE ula_\|video_\|Add0\~4) (DELAY (ABSOLUTE - (PORT datab (377:377:377) (431:431:431)) + (PORT datab (1325:1325:1325) (1300:1300:1300)) (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -13028,8 +1526,8 @@ (INSTANCE ula_\|video_\|vga_hc\[2\]) (DELAY (ABSOLUTE - (PORT clk (1354:1354:1354) (1369:1369:1369)) - (PORT asdata (607:607:607) (607:607:607)) + (PORT clk (1359:1359:1359) (1375:1375:1375)) + (PORT asdata (1140:1140:1140) (1127:1127:1127)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -13042,37 +1540,27 @@ (INSTANCE ula_\|video_\|Add0\~6) (DELAY (ABSOLUTE - (PORT datab (640:640:640) (667:667:667)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datab cout (385:385:385) (280:280:280)) + (PORT dataa (604:604:604) (634:634:634)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) (IOPATH cin cout (50:50:50) (50:50:50)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vga_hc\[3\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (523:523:523) (522:522:522)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|video_\|vga_hc\[3\]) (DELAY (ABSOLUTE - (PORT clk (1357:1357:1357) (1373:1373:1373)) - (PORT d (67:67:67) (78:78:78)) + (PORT clk (1359:1359:1359) (1375:1375:1375)) + (PORT asdata (796:796:796) (782:782:782)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) ) ) (CELL @@ -13080,7 +1568,7 @@ (INSTANCE ula_\|video_\|Add0\~8) (DELAY (ABSOLUTE - (PORT dataa (1015:1015:1015) (1000:1000:1000)) + (PORT dataa (1193:1193:1193) (1237:1237:1237)) (IOPATH dataa combout (318:318:318) (323:323:323)) (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -13094,8 +1582,8 @@ (INSTANCE ula_\|video_\|vga_hc\[4\]) (DELAY (ABSOLUTE - (PORT clk (1354:1354:1354) (1369:1369:1369)) - (PORT asdata (607:607:607) (607:607:607)) + (PORT clk (1359:1359:1359) (1375:1375:1375)) + (PORT asdata (467:467:467) (492:492:492)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -13103,61 +1591,14 @@ (HOLD asdata (posedge clk) (144:144:144)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Equal0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1151:1151:1151) (1185:1185:1185)) - (PORT datab (892:892:892) (947:947:947)) - (PORT datac (891:891:891) (943:943:943)) - (PORT datad (258:258:258) (326:326:326)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Equal0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (635:635:635) (653:653:653)) - (PORT datab (1298:1298:1298) (1302:1302:1302)) - (PORT datad (874:874:874) (842:842:842)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Equal1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (414:414:414) (463:463:463)) - (PORT datab (641:641:641) (668:668:668)) - (PORT datac (600:600:600) (630:630:630)) - (PORT datad (528:528:528) (511:511:511)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|Add0\~10) (DELAY (ABSOLUTE - (PORT dataa (633:633:633) (650:650:650)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH dataa cout (376:376:376) (275:275:275)) + (PORT datab (642:642:642) (666:666:666)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) (IOPATH cin cout (50:50:50) (50:50:50)) @@ -13169,9 +1610,9 @@ (INSTANCE ula_\|video_\|vga_hc\~0) (DELAY (ABSOLUTE - (PORT datac (780:780:780) (780:780:780)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT datab (523:523:523) (507:507:507)) + (PORT datad (798:798:798) (800:800:800)) + (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -13181,13 +1622,13 @@ (INSTANCE ula_\|video_\|vga_hc\[5\]) (DELAY (ABSOLUTE - (PORT clk (1354:1354:1354) (1369:1369:1369)) - (PORT d (67:67:67) (78:78:78)) + (PORT clk (1359:1359:1359) (1375:1375:1375)) + (PORT asdata (767:767:767) (749:749:749)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) ) ) (CELL @@ -13195,7 +1636,7 @@ (INSTANCE ula_\|video_\|Add0\~12) (DELAY (ABSOLUTE - (PORT dataa (590:590:590) (608:608:608)) + (PORT dataa (389:389:389) (443:443:443)) (IOPATH dataa combout (318:318:318) (323:323:323)) (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -13209,8 +1650,8 @@ (INSTANCE ula_\|video_\|vga_hc\[6\]) (DELAY (ABSOLUTE - (PORT clk (1354:1354:1354) (1369:1369:1369)) - (PORT asdata (467:467:467) (493:493:493)) + (PORT clk (1359:1359:1359) (1375:1375:1375)) + (PORT asdata (606:606:606) (610:610:610)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -13218,13 +1659,27 @@ (HOLD asdata (posedge clk) (144:144:144)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add0\~14) + (DELAY + (ABSOLUTE + (PORT datab (387:387:387) (434:434:434)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|video_\|vga_hc\[7\]) (DELAY (ABSOLUTE - (PORT clk (1354:1354:1354) (1369:1369:1369)) - (PORT asdata (806:806:806) (780:780:780)) + (PORT clk (1359:1359:1359) (1375:1375:1375)) + (PORT asdata (603:603:603) (601:601:601)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -13234,36 +1689,220 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add1\~0) + (INSTANCE ula_\|video_\|Add0\~16) (DELAY (ABSOLUTE - (PORT datab (669:669:669) (695:695:695)) + (PORT datab (402:402:402) (445:445:445)) (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add1\~2) - (DELAY - (ABSOLUTE - (PORT dataa (654:654:654) (681:681:681)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH dataa cout (376:376:376) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) (IOPATH cin cout (50:50:50) (50:50:50)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vga_hc\~2) + (DELAY + (ABSOLUTE + (PORT datab (319:319:319) (338:338:338)) + (PORT datad (825:825:825) (826:826:826)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vga_hc\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1359:1359:1359) (1375:1375:1375)) + (PORT asdata (1476:1476:1476) (1431:1431:1431)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add0\~18) + (DELAY + (ABSOLUTE + (PORT datad (219:219:219) (277:277:277)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vga_hc\~1) + (DELAY + (ABSOLUTE + (PORT dataa (752:752:752) (729:729:729)) + (PORT datad (797:797:797) (795:795:795)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vga_hc\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1359:1359:1359) (1375:1375:1375)) + (PORT asdata (595:595:595) (607:607:607)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (691:691:691) (752:752:752)) + (PORT datab (675:675:675) (730:730:730)) + (PORT datac (1063:1063:1063) (1075:1075:1075)) + (PORT datad (633:633:633) (669:669:669)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1184:1184:1184) (1231:1231:1231)) + (PORT datab (1267:1267:1267) (1259:1259:1259)) + (PORT datac (323:323:323) (325:325:325)) + (PORT datad (829:829:829) (846:846:846)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (944:944:944) (1003:1003:1003)) + (PORT datab (652:652:652) (698:698:698)) + (PORT datac (591:591:591) (623:623:623)) + (PORT datad (504:504:504) (500:500:500)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (902:902:902) (922:922:922)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH dataa cout (376:376:376) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vga_vc\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (376:376:376)) + (PORT datab (835:835:835) (834:834:834)) + (PORT datac (318:318:318) (328:328:328)) + (PORT datad (860:860:860) (886:886:886)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vga_vc\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1357:1357:1357) (1373:1373:1373)) + (PORT asdata (854:854:854) (846:846:846)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add1\~2) + (DELAY + (ABSOLUTE + (PORT datab (839:839:839) (858:858:858)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vga_vc\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (554:554:554) (574:574:574)) + (PORT datab (528:528:528) (530:530:530)) + (PORT datad (1188:1188:1188) (1151:1151:1151)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vga_vc\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1357:1357:1357) (1373:1373:1373)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|Add1\~4) (DELAY (ABSOLUTE - (PORT dataa (637:637:637) (664:664:664)) + (PORT dataa (666:666:666) (690:690:690)) (IOPATH dataa combout (318:318:318) (323:323:323)) (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -13277,12 +1916,23 @@ (INSTANCE ula_\|video_\|vga_vc\[2\]\~2) (DELAY (ABSOLUTE - (PORT dataa (452:452:452) (501:501:501)) - (PORT datab (556:556:556) (546:546:546)) - (PORT datad (829:829:829) (818:818:818)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (312:312:312) (325:325:325)) + (PORT dataa (344:344:344) (371:371:371)) + (PORT datab (834:834:834) (835:835:835)) + (PORT datac (1088:1088:1088) (1101:1101:1101)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vga_vc\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (526:526:526) (519:519:519)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -13292,7 +1942,7 @@ (INSTANCE ula_\|video_\|vga_vc\[2\]) (DELAY (ABSOLUTE - (PORT clk (1353:1353:1353) (1369:1369:1369)) + (PORT clk (1357:1357:1357) (1373:1373:1373)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -13306,7 +1956,7 @@ (INSTANCE ula_\|video_\|Add1\~6) (DELAY (ABSOLUTE - (PORT dataa (660:660:660) (695:695:695)) + (PORT dataa (626:626:626) (674:674:674)) (IOPATH dataa combout (318:318:318) (327:327:327)) (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -13320,13 +1970,13 @@ (INSTANCE ula_\|video_\|vga_vc\[3\]\~3) (DELAY (ABSOLUTE - (PORT dataa (574:574:574) (576:576:576)) - (PORT datab (598:598:598) (610:610:610)) - (PORT datac (626:626:626) (665:665:665)) - (PORT datad (161:161:161) (182:182:182)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT dataa (629:629:629) (675:675:675)) + (PORT datab (834:834:834) (834:834:834)) + (PORT datac (157:157:157) (187:187:187)) + (PORT datad (320:320:320) (334:334:334)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -13336,8 +1986,8 @@ (INSTANCE ula_\|video_\|vga_vc\[3\]) (DELAY (ABSOLUTE - (PORT clk (1353:1353:1353) (1369:1369:1369)) - (PORT asdata (1257:1257:1257) (1200:1200:1200)) + (PORT clk (1357:1357:1357) (1373:1373:1373)) + (PORT asdata (1391:1391:1391) (1385:1385:1385)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -13350,9 +2000,9 @@ (INSTANCE ula_\|video_\|Add1\~8) (DELAY (ABSOLUTE - (PORT datab (630:630:630) (668:668:668)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datab cout (385:385:385) (280:280:280)) + (PORT dataa (693:693:693) (727:727:727)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) (IOPATH cin cout (50:50:50) (50:50:50)) @@ -13364,9 +2014,9 @@ (INSTANCE ula_\|video_\|vga_vc\[4\]\~5) (DELAY (ABSOLUTE - (PORT dataa (454:454:454) (503:503:503)) - (PORT datab (581:581:581) (564:564:564)) - (PORT datad (827:827:827) (817:817:817)) + (PORT dataa (1045:1045:1045) (1051:1051:1051)) + (PORT datab (762:762:762) (758:758:758)) + (PORT datad (824:824:824) (827:827:827)) (IOPATH dataa combout (329:329:329) (332:332:332)) (IOPATH datab combout (319:319:319) (307:307:307)) (IOPATH datac combout (312:312:312) (325:325:325)) @@ -13379,7 +2029,7 @@ (INSTANCE ula_\|video_\|vga_vc\[4\]) (DELAY (ABSOLUTE - (PORT clk (1353:1353:1353) (1369:1369:1369)) + (PORT clk (1359:1359:1359) (1375:1375:1375)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -13393,51 +2043,21 @@ (INSTANCE ula_\|video_\|Add1\~10) (DELAY (ABSOLUTE - (PORT dataa (641:641:641) (684:684:684)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH dataa cout (376:376:376) (275:275:275)) + (PORT datab (654:654:654) (687:687:687)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) (IOPATH cin cout (50:50:50) (50:50:50)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vga_vc\[5\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (574:574:574) (573:573:573)) - (PORT datab (598:598:598) (607:607:607)) - (PORT datac (654:654:654) (677:677:677)) - (PORT datad (160:160:160) (180:180:180)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_vc\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1369:1369:1369)) - (PORT asdata (812:812:812) (796:796:796)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|Add1\~12) (DELAY (ABSOLUTE - (PORT datab (665:665:665) (689:689:689)) + (PORT datab (1090:1090:1090) (1090:1090:1090)) (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -13451,9 +2071,9 @@ (INSTANCE ula_\|video_\|vga_vc\[6\]\~4) (DELAY (ABSOLUTE - (PORT dataa (453:453:453) (501:501:501)) - (PORT datab (546:546:546) (539:539:539)) - (PORT datad (831:831:831) (812:812:812)) + (PORT dataa (1047:1047:1047) (1052:1052:1052)) + (PORT datab (768:768:768) (752:752:752)) + (PORT datad (825:825:825) (827:827:827)) (IOPATH dataa combout (329:329:329) (332:332:332)) (IOPATH datab combout (319:319:319) (307:307:307)) (IOPATH datac combout (312:312:312) (325:325:325)) @@ -13466,7 +2086,7 @@ (INSTANCE ula_\|video_\|vga_vc\[6\]) (DELAY (ABSOLUTE - (PORT clk (1353:1353:1353) (1369:1369:1369)) + (PORT clk (1359:1359:1359) (1375:1375:1375)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -13480,7 +2100,7 @@ (INSTANCE ula_\|video_\|Add1\~14) (DELAY (ABSOLUTE - (PORT datab (641:641:641) (663:663:663)) + (PORT datab (1052:1052:1052) (1057:1057:1057)) (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -13494,9 +2114,9 @@ (INSTANCE ula_\|video_\|vga_vc\[7\]\~6) (DELAY (ABSOLUTE - (PORT dataa (452:452:452) (500:500:500)) - (PORT datab (1086:1086:1086) (1066:1066:1066)) - (PORT datad (830:830:830) (816:816:816)) + (PORT dataa (1045:1045:1045) (1052:1052:1052)) + (PORT datab (802:802:802) (791:791:791)) + (PORT datad (823:823:823) (828:828:828)) (IOPATH dataa combout (329:329:329) (332:332:332)) (IOPATH datab combout (319:319:319) (307:307:307)) (IOPATH datac combout (312:312:312) (325:325:325)) @@ -13509,7 +2129,7 @@ (INSTANCE ula_\|video_\|vga_vc\[7\]) (DELAY (ABSOLUTE - (PORT clk (1353:1353:1353) (1369:1369:1369)) + (PORT clk (1359:1359:1359) (1375:1375:1375)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -13523,9 +2143,9 @@ (INSTANCE ula_\|video_\|Add1\~16) (DELAY (ABSOLUTE - (PORT datab (685:685:685) (711:711:711)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datab cout (385:385:385) (280:280:280)) + (PORT dataa (925:925:925) (986:986:986)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) (IOPATH cin cout (50:50:50) (50:50:50)) @@ -13537,9 +2157,9 @@ (INSTANCE ula_\|video_\|vga_vc\[8\]\~7) (DELAY (ABSOLUTE - (PORT dataa (454:454:454) (497:497:497)) - (PORT datab (929:929:929) (887:887:887)) - (PORT datad (822:822:822) (812:812:812)) + (PORT dataa (556:556:556) (575:575:575)) + (PORT datab (1050:1050:1050) (1008:1008:1008)) + (PORT datad (1190:1190:1190) (1149:1149:1149)) (IOPATH dataa combout (329:329:329) (332:332:332)) (IOPATH datab combout (319:319:319) (307:307:307)) (IOPATH datac combout (312:312:312) (325:325:325)) @@ -13552,7 +2172,7 @@ (INSTANCE ula_\|video_\|vga_vc\[8\]) (DELAY (ABSOLUTE - (PORT clk (1353:1353:1353) (1369:1369:1369)) + (PORT clk (1357:1357:1357) (1373:1373:1373)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -13566,7 +2186,7 @@ (INSTANCE ula_\|video_\|Add1\~18) (DELAY (ABSOLUTE - (PORT datad (607:607:607) (634:634:634)) + (PORT datad (1155:1155:1155) (1196:1196:1196)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) ) @@ -13577,11 +2197,11 @@ (INSTANCE ula_\|video_\|vga_vc\[9\]\~9) (DELAY (ABSOLUTE - (PORT dataa (452:452:452) (496:496:496)) - (PORT datab (942:942:942) (906:906:906)) - (PORT datad (827:827:827) (818:818:818)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) + (PORT dataa (536:536:536) (543:543:543)) + (PORT datab (585:585:585) (583:583:583)) + (PORT datad (1022:1022:1022) (1014:1014:1014)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -13592,7 +2212,7 @@ (INSTANCE ula_\|video_\|vga_vc\[9\]) (DELAY (ABSOLUTE - (PORT clk (1353:1353:1353) (1369:1369:1369)) + (PORT clk (1359:1359:1359) (1375:1375:1375)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -13603,31 +2223,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Equal2\~0) + (INSTANCE ula_\|video_\|Equal3\~0) (DELAY (ABSOLUTE - (PORT dataa (247:247:247) (322:322:322)) - (PORT datab (244:244:244) (318:318:318)) - (PORT datac (237:237:237) (307:307:307)) - (PORT datad (221:221:221) (283:283:283)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT dataa (866:866:866) (901:901:901)) + (PORT datab (1082:1082:1082) (1090:1090:1090)) + (PORT datac (881:881:881) (907:907:907)) + (PORT datad (1085:1085:1085) (1089:1089:1089)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Equal3\~0) + (INSTANCE ula_\|video_\|Equal2\~0) (DELAY (ABSOLUTE - (PORT dataa (1082:1082:1082) (1131:1131:1131)) - (PORT datab (788:788:788) (823:823:823)) - (PORT datac (589:589:589) (595:595:595)) - (PORT datad (623:623:623) (667:667:667)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) + (PORT dataa (426:426:426) (466:466:466)) + (PORT datab (260:260:260) (333:333:333)) + (PORT datac (376:376:376) (418:418:418)) + (PORT datad (356:356:356) (395:395:395)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -13638,10 +2258,10 @@ (INSTANCE ula_\|video_\|Equal3\~1) (DELAY (ABSOLUTE - (PORT dataa (597:597:597) (627:627:627)) - (PORT datab (621:621:621) (651:651:651)) - (PORT datac (530:530:530) (525:525:525)) - (PORT datad (286:286:286) (291:291:291)) + (PORT dataa (1146:1146:1146) (1172:1172:1172)) + (PORT datab (247:247:247) (320:320:320)) + (PORT datac (547:547:547) (554:554:554)) + (PORT datad (327:327:327) (328:328:328)) (IOPATH dataa combout (287:287:287) (289:289:289)) (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) @@ -13651,12 +2271,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vga_vc\[0\]\~0) + (INSTANCE ula_\|video_\|vga_vc\[5\]\~8) (DELAY (ABSOLUTE - (PORT dataa (454:454:454) (500:500:500)) - (PORT datab (518:518:518) (503:503:503)) - (PORT datad (823:823:823) (811:811:811)) + (PORT dataa (1048:1048:1048) (1054:1054:1054)) + (PORT datab (577:577:577) (575:575:575)) + (PORT datad (826:826:826) (829:829:829)) (IOPATH dataa combout (329:329:329) (332:332:332)) (IOPATH datab combout (319:319:319) (307:307:307)) (IOPATH datac combout (312:312:312) (325:325:325)) @@ -13666,10 +2286,10 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_vc\[0\]) + (INSTANCE ula_\|video_\|vga_vc\[5\]) (DELAY (ABSOLUTE - (PORT clk (1353:1353:1353) (1369:1369:1369)) + (PORT clk (1359:1359:1359) (1375:1375:1375)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -13680,32 +2300,33 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vga_vc\[1\]\~1) + (INSTANCE ula_\|video_\|Equal2\~1) (DELAY (ABSOLUTE - (PORT dataa (454:454:454) (499:499:499)) - (PORT datab (526:526:526) (522:522:522)) - (PORT datad (821:821:821) (812:812:812)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (312:312:312) (325:325:325)) + (PORT dataa (669:669:669) (694:694:694)) + (PORT datab (1180:1180:1180) (1225:1225:1225)) + (PORT datac (809:809:809) (834:834:834)) + (PORT datad (858:858:858) (884:884:884)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_vc\[1\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Equal2\~2) (DELAY (ABSOLUTE - (PORT clk (1353:1353:1353) (1369:1369:1369)) - (PORT d (67:67:67) (78:78:78)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (PORT dataa (1145:1145:1145) (1168:1168:1168)) + (PORT datab (562:562:562) (552:552:552)) + (PORT datad (329:329:329) (331:331:331)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) ) (CELL (CELLTYPE "cycloneive_io_ibuf") @@ -13721,10 +2342,10 @@ (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_13\~0) (DELAY (ABSOLUTE - (PORT dataa (1332:1332:1332) (1337:1337:1337)) - (PORT datab (659:659:659) (713:713:713)) - (PORT datac (1648:1648:1648) (1616:1616:1616)) - (PORT datad (627:627:627) (644:644:644)) + (PORT dataa (792:792:792) (803:803:803)) + (PORT datab (923:923:923) (977:977:977)) + (PORT datac (1115:1115:1115) (1148:1148:1148)) + (PORT datad (1693:1693:1693) (1659:1659:1659)) (IOPATH dataa combout (309:309:309) (326:326:326)) (IOPATH datab combout (309:309:309) (328:328:328)) (IOPATH datac combout (218:218:218) (215:215:215)) @@ -13732,180 +2353,18 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal79\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1161:1161:1161) (1205:1205:1205)) - (PORT datab (912:912:912) (925:925:925)) - (PORT datac (1486:1486:1486) (1580:1580:1580)) - (PORT datad (1098:1098:1098) (1166:1166:1166)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|DFFE_instIFF2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1390:1390:1390) (1431:1431:1431)) - (PORT datab (333:333:333) (349:349:349)) - (PORT datad (607:607:607) (643:643:643)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_12) - (DELAY - (ABSOLUTE - (PORT dataa (327:327:327) (454:454:454)) - (PORT datab (1869:1869:1869) (1898:1898:1898)) - (PORT datad (251:251:251) (319:319:319)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_clkctrl") - (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_12\~clkctrl) - (DELAY - (ABSOLUTE - (PORT inclk[0] (1460:1460:1460) (1433:1433:1433)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|DFFE_instIFF2) - (DELAY - (ABSOLUTE - (PORT clk (1358:1358:1358) (1380:1380:1380)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1376:1376:1376) (1354:1354:1354)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|iff1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (653:653:653) (684:684:684)) - (PORT datab (242:242:242) (312:312:312)) - (PORT datac (184:184:184) (218:218:218)) - (PORT datad (1342:1342:1342) (1384:1384:1384)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|iff1\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1188:1188:1188) (1199:1199:1199)) - (PORT datab (242:242:242) (312:312:312)) - (PORT datac (825:825:825) (840:840:840)) - (PORT datad (160:160:160) (182:182:182)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_15) - (DELAY - (ABSOLUTE - (PORT datab (1328:1328:1328) (1332:1332:1332)) - (PORT datac (1398:1398:1398) (1422:1422:1422)) - (PORT datad (1171:1171:1171) (1211:1211:1211)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|iff1) - (DELAY - (ABSOLUTE - (PORT clk (1358:1358:1358) (1380:1380:1380)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1290:1290:1290) (1255:1255:1255)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Equal2\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1477:1477:1477) (1499:1499:1499)) - (PORT datab (784:784:784) (804:804:804)) - (PORT datac (591:591:591) (619:619:619)) - (PORT datad (398:398:398) (440:440:440)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Equal2\~2) - (DELAY - (ABSOLUTE - (PORT datab (182:182:182) (215:215:215)) - (PORT datac (531:531:531) (526:526:526)) - (PORT datad (405:405:405) (457:457:457)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_13) (DELAY (ABSOLUTE - (PORT dataa (1091:1091:1091) (1093:1093:1093)) - (PORT datab (582:582:582) (590:590:590)) - (PORT datac (1420:1420:1420) (1485:1485:1485)) - (PORT datad (780:780:780) (777:777:777)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT dataa (1365:1365:1365) (1406:1406:1406)) + (PORT datab (520:520:520) (521:521:521)) + (PORT datac (575:575:575) (598:598:598)) + (PORT datad (161:161:161) (183:183:183)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -13915,9 +2374,9 @@ (INSTANCE z80_\|interrupts_\|int_armed) (DELAY (ABSOLUTE - (PORT clk (1351:1351:1351) (1368:1368:1368)) + (PORT clk (1353:1353:1353) (1369:1369:1369)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1386:1386:1386) (1364:1364:1364)) + (PORT clrn (1387:1387:1387) (1364:1364:1364)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -13926,49 +2385,43 @@ (HOLD d (posedge clk) (144:144:144)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|DFFE_inst44\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1403:1403:1403) (1442:1442:1442)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|interrupts_\|DFFE_inst44) (DELAY (ABSOLUTE - (PORT clk (1354:1354:1354) (1375:1375:1375)) - (PORT asdata (1978:1978:1978) (2024:2024:2024)) - (PORT clrn (1413:1413:1413) (1379:1379:1379)) - (PORT ena (1556:1556:1556) (1512:1512:1512)) + (PORT clk (1345:1345:1345) (1362:1362:1362)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1388:1388:1388) (1361:1361:1361)) + (PORT ena (877:877:877) (871:871:871)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) + (HOLD d (posedge clk) (144:144:144)) (HOLD ena (posedge clk) (144:144:144)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~38) + (INSTANCE z80_\|decode_state_\|in_halt\~0) (DELAY (ABSOLUTE - (PORT dataa (324:324:324) (445:445:445)) - (PORT datac (1096:1096:1096) (1138:1138:1138)) - (PORT datad (245:245:245) (311:311:311)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~91) - (DELAY - (ABSOLUTE - (PORT dataa (1544:1544:1544) (1565:1565:1565)) - (PORT datab (1160:1160:1160) (1190:1190:1190)) - (PORT datac (895:895:895) (947:947:947)) - (PORT datad (810:810:810) (791:791:791)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (285:285:285)) + (PORT dataa (446:446:446) (515:515:515)) + (PORT datac (239:239:239) (319:319:319)) + (PORT datad (649:649:649) (696:696:696)) + (IOPATH dataa combout (287:287:287) (280:280:280)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -13976,15 +2429,44 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~45) + (INSTANCE z80_\|decode_state_\|in_halt\~1) (DELAY (ABSOLUTE - (PORT dataa (1008:1008:1008) (1008:1008:1008)) - (PORT datab (651:651:651) (683:683:683)) - (PORT datac (1101:1101:1101) (1142:1142:1142)) - (PORT datad (580:580:580) (593:593:593)) + (PORT dataa (325:325:325) (337:337:337)) + (PORT datab (1527:1527:1527) (1481:1481:1481)) + (PORT datad (567:567:567) (590:590:590)) (IOPATH dataa combout (300:300:300) (323:323:323)) (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|decode_state_\|in_halt) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1390:1390:1390) (1362:1362:1362)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal50\~0) + (DELAY + (ABSOLUTE + (PORT datab (273:273:273) (364:364:364)) + (PORT datac (1698:1698:1698) (1675:1675:1675)) + (PORT datad (538:538:538) (530:530:530)) + (IOPATH datab combout (295:295:295) (294:294:294)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -13992,15 +2474,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~44) + (INSTANCE z80_\|execute_\|ixy_d\~17) (DELAY (ABSOLUTE - (PORT dataa (1011:1011:1011) (1009:1009:1009)) - (PORT datab (847:847:847) (880:880:880)) - (PORT datac (793:793:793) (800:800:800)) - (PORT datad (1020:1020:1020) (981:981:981)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) + (PORT dataa (450:450:450) (515:515:515)) + (PORT datab (443:443:443) (510:510:510)) + (PORT datac (764:764:764) (746:746:746)) + (PORT datad (552:552:552) (537:537:537)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -14008,190 +2490,268 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~46) + (INSTANCE z80_\|pla_decode_\|Equal44\~0) (DELAY (ABSOLUTE - (PORT dataa (310:310:310) (332:332:332)) - (PORT datab (654:654:654) (687:687:687)) - (PORT datac (158:158:158) (189:189:189)) - (PORT datad (1024:1024:1024) (986:986:986)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT dataa (955:955:955) (1024:1024:1024)) + (PORT datab (917:917:917) (988:988:988)) + (PORT datac (863:863:863) (941:941:941)) + (PORT datad (903:903:903) (961:961:961)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~37) + (INSTANCE z80_\|execute_\|ixy_d\~16) (DELAY (ABSOLUTE - (PORT dataa (1077:1077:1077) (1102:1102:1102)) - (PORT datab (822:822:822) (841:841:841)) - (PORT datac (987:987:987) (979:979:979)) - (PORT datad (184:184:184) (209:209:209)) + (PORT dataa (446:446:446) (515:515:515)) + (PORT datab (448:448:448) (512:512:512)) + (PORT datac (1126:1126:1126) (1127:1127:1127)) + (PORT datad (186:186:186) (211:211:211)) (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal3\~1) + (DELAY + (ABSOLUTE + (PORT datac (828:828:828) (850:850:850)) + (PORT datad (1204:1204:1204) (1259:1259:1259)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1533:1533:1533) (1524:1524:1524)) + (PORT datab (607:607:607) (628:628:628)) + (PORT datac (833:833:833) (855:855:855)) + (PORT datad (878:878:878) (911:911:911)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1114:1114:1114) (1111:1111:1111)) + (PORT datab (346:346:346) (372:372:372)) + (PORT datac (1441:1441:1441) (1492:1492:1492)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~14) + (DELAY + (ABSOLUTE + (PORT dataa (987:987:987) (1018:1018:1018)) + (PORT datab (604:604:604) (629:629:629)) + (PORT datac (593:593:593) (592:592:592)) + (PORT datad (157:157:157) (177:177:177)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal49\~0) + (DELAY + (ABSOLUTE + (PORT datab (276:276:276) (369:369:369)) + (PORT datac (1567:1567:1567) (1585:1585:1585)) + (PORT datad (539:539:539) (530:530:530)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~15) + (DELAY + (ABSOLUTE + (PORT dataa (878:878:878) (895:895:895)) + (PORT datab (850:850:850) (855:855:855)) + (PORT datac (154:154:154) (184:184:184)) + (PORT datad (1171:1171:1171) (1166:1166:1166)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_ixy_dT5_7) + (DELAY + (ABSOLUTE + (PORT datab (831:831:831) (863:863:863)) + (PORT datac (1313:1313:1313) (1391:1391:1391)) (IOPATH datab combout (308:308:308) (300:300:300)) (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~50) + (INSTANCE z80_\|decode_state_\|SYNTHESIZED_WIRE_0\~0) (DELAY (ABSOLUTE - (PORT dataa (776:776:776) (772:772:772)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (1461:1461:1461) (1534:1534:1534)) - (PORT datad (2107:2107:2107) (2149:2149:2149)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT dataa (686:686:686) (748:748:748)) + (PORT datab (902:902:902) (929:929:929)) + (PORT datac (174:174:174) (205:205:205)) + (PORT datad (361:361:361) (373:373:373)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~33) + (CELLTYPE "dffeas") + (INSTANCE z80_\|decode_state_\|DFFE_inst4) (DELAY (ABSOLUTE - (PORT dataa (209:209:209) (249:249:249)) - (PORT datab (1071:1071:1071) (1094:1094:1094)) - (PORT datac (1006:1006:1006) (997:997:997)) - (PORT datad (551:551:551) (559:559:559)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (PORT clk (1346:1346:1346) (1368:1368:1368)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1382:1382:1382) (1354:1354:1354)) + (PORT ena (745:745:745) (751:751:751)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla38pla13M3T2_4) + (INSTANCE z80_\|execute_\|ctl_ir_we\~5) (DELAY (ABSOLUTE - (PORT dataa (1554:1554:1554) (1584:1584:1584)) - (PORT datab (576:576:576) (597:597:597)) - (PORT datac (1526:1526:1526) (1554:1554:1554)) - (PORT datad (1081:1081:1081) (1112:1112:1112)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla40M3T2_4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (672:672:672) (721:721:721)) - (PORT datab (626:626:626) (663:663:663)) - (PORT datac (1059:1059:1059) (1071:1071:1071)) - (PORT datad (193:193:193) (224:224:224)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~31) - (DELAY - (ABSOLUTE - (PORT dataa (1035:1035:1035) (1028:1028:1028)) - (PORT datab (794:794:794) (779:779:779)) - (PORT datac (1125:1125:1125) (1118:1118:1118)) - (PORT datad (765:765:765) (755:755:755)) + (PORT dataa (956:956:956) (1025:1025:1025)) + (PORT datab (452:452:452) (521:521:521)) + (PORT datad (412:412:412) (463:463:463)) (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~32) + (INSTANCE z80_\|execute_\|ctl_ir_we\~13) (DELAY (ABSOLUTE - (PORT dataa (1034:1034:1034) (1031:1031:1031)) - (PORT datab (575:575:575) (597:597:597)) - (PORT datac (186:186:186) (226:226:226)) - (PORT datad (1521:1521:1521) (1537:1537:1537)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~34) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (219:219:219)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (174:174:174) (216:216:216)) - (PORT datad (165:165:165) (189:189:189)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~51) - (DELAY - (ABSOLUTE - (PORT dataa (1062:1062:1062) (1079:1079:1079)) - (PORT datab (1294:1294:1294) (1329:1329:1329)) - (PORT datac (2314:2314:2314) (2350:2350:2350)) - (PORT datad (1371:1371:1371) (1420:1420:1420)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~30) - (DELAY - (ABSOLUTE - (PORT dataa (631:631:631) (660:660:660)) - (PORT datab (1059:1059:1059) (1088:1088:1088)) - (PORT datac (334:334:334) (351:351:351)) - (PORT datad (791:791:791) (793:793:793)) - (IOPATH dataa combout (299:299:299) (304:304:304)) + (PORT dataa (904:904:904) (942:942:942)) + (PORT datab (557:557:557) (561:561:561)) + (PORT datac (1817:1817:1817) (1823:1823:1823)) + (PORT datad (808:808:808) (806:806:806)) + (IOPATH dataa combout (329:329:329) (332:332:332)) (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1363:1363:1363) (1384:1384:1384)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1388:1388:1388) (1362:1362:1362)) + (PORT ena (1285:1285:1285) (1246:1246:1246)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal8\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1440:1440:1440) (1522:1522:1522)) + (PORT datac (1247:1247:1247) (1355:1355:1355)) + (PORT datad (1415:1415:1415) (1460:1460:1460)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~52) + (INSTANCE z80_\|execute_\|ctl_mRead\~6) (DELAY (ABSOLUTE - (PORT dataa (1391:1391:1391) (1451:1451:1451)) - (PORT datab (1290:1290:1290) (1325:1325:1325)) - (PORT datac (2318:2318:2318) (2353:2353:2353)) - (PORT datad (980:980:980) (990:990:990)) - (IOPATH dataa combout (273:273:273) (269:269:269)) + (PORT datab (1221:1221:1221) (1253:1253:1253)) + (PORT datac (594:594:594) (595:595:595)) + (PORT datad (1104:1104:1104) (1133:1133:1133)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal9\~0) + (DELAY + (ABSOLUTE + (PORT datab (1315:1315:1315) (1337:1337:1337)) + (PORT datad (1329:1329:1329) (1374:1374:1374)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal9\~1) + (DELAY + (ABSOLUTE + (PORT dataa (2337:2337:2337) (2424:2424:2424)) + (PORT datab (897:897:897) (937:937:937)) + (PORT datac (1553:1553:1553) (1587:1587:1587)) + (PORT datad (843:843:843) (863:863:863)) + (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -14200,13 +2760,197 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~35) + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla10M5T1_5\~2) (DELAY (ABSOLUTE - (PORT dataa (343:343:343) (361:361:361)) - (PORT datab (182:182:182) (214:214:214)) - (PORT datac (574:574:574) (576:576:576)) - (PORT datad (164:164:164) (187:187:187)) + (PORT datab (1180:1180:1180) (1201:1201:1201)) + (PORT datac (1657:1657:1657) (1677:1677:1677)) + (PORT datad (933:933:933) (978:978:978)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (1266:1266:1266) (1249:1249:1249)) + (PORT datab (1162:1162:1162) (1164:1164:1164)) + (PORT datac (1105:1105:1105) (1110:1110:1110)) + (PORT datad (594:594:594) (612:612:612)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal13\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1446:1446:1446) (1532:1532:1532)) + (PORT datac (1260:1260:1260) (1373:1373:1373)) + (PORT datad (1414:1414:1414) (1457:1457:1457)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal69\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1847:1847:1847) (1982:1982:1982)) + (PORT datab (1130:1130:1130) (1171:1171:1171)) + (PORT datac (1087:1087:1087) (1114:1114:1114)) + (PORT datad (1101:1101:1101) (1096:1096:1096)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (584:584:584) (613:613:613)) + (PORT datab (1404:1404:1404) (1455:1455:1455)) + (PORT datac (791:791:791) (791:791:791)) + (PORT datad (855:855:855) (896:896:896)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~27) + (DELAY + (ABSOLUTE + (PORT dataa (1248:1248:1248) (1332:1332:1332)) + (PORT datab (207:207:207) (246:246:246)) + (PORT datac (1128:1128:1128) (1157:1157:1157)) + (PORT datad (789:789:789) (800:800:800)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1568:1568:1568) (1551:1551:1551)) + (PORT datab (913:913:913) (925:925:925)) + (PORT datac (1050:1050:1050) (1044:1044:1044)) + (PORT datad (1119:1119:1119) (1131:1131:1131)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|rsel3) + (DELAY + (ABSOLUTE + (PORT dataa (713:713:713) (787:787:787)) + (PORT datac (1271:1271:1271) (1271:1271:1271)) + (PORT datad (1127:1127:1127) (1179:1179:1179)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~12) + (DELAY + (ABSOLUTE + (PORT dataa (657:657:657) (707:707:707)) + (PORT datab (962:962:962) (1046:1046:1046)) + (PORT datac (1180:1180:1180) (1196:1196:1196)) + (PORT datad (927:927:927) (996:996:996)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3) + (DELAY + (ABSOLUTE + (PORT dataa (903:903:903) (984:984:984)) + (PORT datac (1018:1018:1018) (1010:1010:1010)) + (PORT datad (1271:1271:1271) (1291:1291:1291)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal56\~0) + (DELAY + (ABSOLUTE + (PORT dataa (906:906:906) (970:970:970)) + (PORT datab (1402:1402:1402) (1423:1423:1423)) + (PORT datac (937:937:937) (971:971:971)) + (PORT datad (1526:1526:1526) (1613:1613:1613)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~24) + (DELAY + (ABSOLUTE + (PORT dataa (1925:1925:1925) (1951:1951:1951)) + (PORT datab (2052:2052:2052) (2054:2054:2054)) + (PORT datac (1790:1790:1790) (1793:1793:1793)) + (PORT datad (849:849:849) (887:887:887)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~25) + (DELAY + (ABSOLUTE + (PORT dataa (2022:2022:2022) (2095:2095:2095)) + (PORT datab (900:900:900) (941:941:941)) + (PORT datac (1081:1081:1081) (1095:1095:1095)) + (PORT datad (824:824:824) (861:861:861)) (IOPATH dataa combout (318:318:318) (327:327:327)) (IOPATH datab combout (308:308:308) (281:281:281)) (IOPATH datac combout (220:220:220) (215:215:215)) @@ -14216,15 +2960,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~36) + (INSTANCE z80_\|execute_\|nextM\~2) (DELAY (ABSOLUTE - (PORT dataa (1029:1029:1029) (1017:1017:1017)) - (PORT datab (595:595:595) (607:607:607)) - (PORT datac (578:578:578) (566:566:566)) - (PORT datad (1278:1278:1278) (1289:1289:1289)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) + (PORT dataa (831:831:831) (887:887:887)) + (PORT datac (531:531:531) (525:525:525)) + (PORT datad (979:979:979) (964:964:964)) + (IOPATH dataa combout (329:329:329) (332:332:332)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -14232,75 +2974,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~44) + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~16) (DELAY (ABSOLUTE - (PORT dataa (1920:1920:1920) (1948:1948:1948)) - (PORT datab (847:847:847) (880:880:880)) - (PORT datac (1304:1304:1304) (1325:1325:1325)) - (PORT datad (594:594:594) (621:621:621)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_use_ixiypla53M2T2_4) - (DELAY - (ABSOLUTE - (PORT dataa (1231:1231:1231) (1280:1280:1280)) - (PORT datab (1626:1626:1626) (1684:1684:1684)) - (PORT datad (587:587:587) (607:607:607)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~45) - (DELAY - (ABSOLUTE - (PORT dataa (196:196:196) (240:240:240)) - (PORT datab (195:195:195) (236:236:236)) - (PORT datac (621:621:621) (640:640:640)) - (PORT datad (531:531:531) (525:525:525)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~43) - (DELAY - (ABSOLUTE - (PORT dataa (1317:1317:1317) (1312:1312:1312)) - (PORT datab (618:618:618) (637:637:637)) - (PORT datac (1836:1836:1836) (1869:1869:1869)) - (PORT datad (1153:1153:1153) (1156:1156:1156)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~71) - (DELAY - (ABSOLUTE - (PORT dataa (189:189:189) (228:228:228)) - (PORT datab (201:201:201) (235:235:235)) - (PORT datac (578:578:578) (601:601:601)) - (PORT datad (173:173:173) (201:201:201)) + (PORT dataa (905:905:905) (987:987:987)) + (PORT datab (898:898:898) (937:937:937)) + (PORT datac (1219:1219:1219) (1210:1210:1210)) + (PORT datad (1131:1131:1131) (1158:1158:1158)) (IOPATH dataa combout (307:307:307) (280:280:280)) (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (220:220:220) (215:215:215)) @@ -14310,15 +2990,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~73) + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~3) (DELAY (ABSOLUTE - (PORT dataa (363:363:363) (378:378:378)) - (PORT datab (182:182:182) (215:215:215)) - (PORT datac (582:582:582) (587:587:587)) - (PORT datad (159:159:159) (181:181:181)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (265:265:265) (275:275:275)) + (PORT dataa (587:587:587) (618:618:618)) + (PORT datab (619:619:619) (657:657:657)) + (PORT datac (175:175:175) (206:206:206)) + (PORT datad (177:177:177) (199:199:199)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal40\~0) + (DELAY + (ABSOLUTE + (PORT dataa (909:909:909) (942:942:942)) + (PORT datac (828:828:828) (851:851:851)) + (PORT datad (1204:1204:1204) (1260:1260:1260)) + (IOPATH dataa combout (329:329:329) (332:332:332)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -14326,30 +3020,28 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~46) + (INSTANCE z80_\|pla_decode_\|Equal40\~1) (DELAY (ABSOLUTE - (PORT dataa (615:615:615) (637:637:637)) - (PORT datab (651:651:651) (684:684:684)) - (PORT datac (584:584:584) (587:587:587)) - (PORT datad (1073:1073:1073) (1095:1095:1095)) + (PORT dataa (212:212:212) (265:265:265)) + (PORT datab (811:811:811) (832:832:832)) + (PORT datad (1260:1260:1260) (1345:1345:1345)) (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~53) + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla23pla16M3T1_5\~0) (DELAY (ABSOLUTE - (PORT dataa (1502:1502:1502) (1574:1574:1574)) - (PORT datab (981:981:981) (1037:1037:1037)) - (PORT datac (567:567:567) (581:581:581)) - (PORT datad (902:902:902) (949:949:949)) - (IOPATH dataa combout (273:273:273) (269:269:269)) + (PORT dataa (906:906:906) (969:969:969)) + (PORT datab (1000:1000:1000) (1030:1030:1030)) + (PORT datac (867:867:867) (875:875:875)) + (PORT datad (949:949:949) (984:984:984)) + (IOPATH dataa combout (287:287:287) (289:289:289)) (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -14358,13 +3050,1147 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~39) + (INSTANCE z80_\|pla_decode_\|Equal3\~0) (DELAY (ABSOLUTE - (PORT dataa (195:195:195) (238:238:238)) - (PORT datab (182:182:182) (216:216:216)) - (PORT datac (579:579:579) (567:567:567)) - (PORT datad (526:526:526) (520:520:520)) + (PORT datab (1127:1127:1127) (1158:1158:1158)) + (PORT datad (1173:1173:1173) (1208:1208:1208)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal39\~0) + (DELAY + (ABSOLUTE + (PORT dataa (212:212:212) (265:265:265)) + (PORT datab (810:810:810) (833:833:833)) + (PORT datac (1222:1222:1222) (1302:1302:1302)) + (PORT datad (820:820:820) (833:833:833)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1187:1187:1187) (1212:1212:1212)) + (PORT datab (603:603:603) (614:614:614)) + (PORT datac (1272:1272:1272) (1289:1289:1289)) + (PORT datad (1842:1842:1842) (1816:1816:1816)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~0) + (DELAY + (ABSOLUTE + (PORT datac (1456:1456:1456) (1488:1488:1488)) + (PORT datad (1211:1211:1211) (1289:1289:1289)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|comb\~0) + (DELAY + (ABSOLUTE + (PORT datac (1293:1293:1293) (1303:1303:1303)) + (PORT datad (1114:1114:1114) (1123:1123:1123)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal41\~0) + (DELAY + (ABSOLUTE + (PORT dataa (955:955:955) (1037:1037:1037)) + (PORT datad (924:924:924) (1013:1013:1013)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal47\~0) + (DELAY + (ABSOLUTE + (PORT dataa (901:901:901) (945:945:945)) + (PORT datab (618:618:618) (603:603:603)) + (PORT datac (588:588:588) (588:588:588)) + (PORT datad (627:627:627) (654:654:654)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~32) + (DELAY + (ABSOLUTE + (PORT dataa (1155:1155:1155) (1175:1175:1175)) + (PORT datab (1602:1602:1602) (1606:1606:1606)) + (PORT datac (189:189:189) (226:226:226)) + (PORT datad (1242:1242:1242) (1275:1275:1275)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal19\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1207:1207:1207) (1236:1236:1236)) + (PORT datab (821:821:821) (825:825:825)) + (PORT datac (672:672:672) (745:745:745)) + (PORT datad (1001:1001:1001) (994:994:994)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~9) + (DELAY + (ABSOLUTE + (PORT dataa (196:196:196) (240:240:240)) + (PORT datab (1123:1123:1123) (1125:1125:1125)) + (PORT datac (1453:1453:1453) (1486:1486:1486)) + (PORT datad (1206:1206:1206) (1286:1286:1286)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~5) + (DELAY + (ABSOLUTE + (PORT dataa (576:576:576) (568:568:568)) + (PORT datab (181:181:181) (213:213:213)) + (PORT datac (533:533:533) (557:557:557)) + (PORT datad (1239:1239:1239) (1220:1220:1220)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~4) + (DELAY + (ABSOLUTE + (PORT dataa (262:262:262) (346:346:346)) + (PORT datab (1074:1074:1074) (1088:1088:1088)) + (PORT datac (362:362:362) (418:418:418)) + (PORT datad (367:367:367) (402:402:402)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla21M2T2_3) + (DELAY + (ABSOLUTE + (PORT dataa (893:893:893) (926:926:926)) + (PORT datab (1546:1546:1546) (1546:1546:1546)) + (PORT datac (867:867:867) (940:940:940)) + (PORT datad (2381:2381:2381) (2459:2459:2459)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~34) + (DELAY + (ABSOLUTE + (PORT dataa (648:648:648) (715:715:715)) + (PORT datab (1585:1585:1585) (1610:1610:1610)) + (PORT datac (1035:1035:1035) (1051:1051:1051)) + (PORT datad (839:839:839) (842:842:842)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_ixy_dT4_2) + (DELAY + (ABSOLUTE + (PORT datac (1467:1467:1467) (1567:1567:1567)) + (PORT datad (1003:1003:1003) (1013:1013:1013)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (189:189:189) (228:228:228)) + (PORT datab (1030:1030:1030) (1083:1083:1083)) + (PORT datac (889:889:889) (923:923:923)) + (PORT datad (992:992:992) (986:986:986)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~5) + (DELAY + (ABSOLUTE + (PORT datab (435:435:435) (480:480:480)) + (PORT datac (388:388:388) (431:431:431)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~11) + (DELAY + (ABSOLUTE + (PORT dataa (781:781:781) (776:776:776)) + (PORT datab (1584:1584:1584) (1569:1569:1569)) + (PORT datac (793:793:793) (796:796:796)) + (PORT datad (828:828:828) (901:901:901)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal20\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1584:1584:1584) (1669:1669:1669)) + (PORT datab (1398:1398:1398) (1414:1414:1414)) + (PORT datac (1197:1197:1197) (1227:1227:1227)) + (PORT datad (608:608:608) (646:646:646)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal13\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1847:1847:1847) (1987:1987:1987)) + (PORT datab (1128:1128:1128) (1171:1171:1171)) + (PORT datac (1089:1089:1089) (1118:1118:1118)) + (PORT datad (1097:1097:1097) (1095:1095:1095)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~24) + (DELAY + (ABSOLUTE + (PORT datac (2002:2002:2002) (2024:2024:2024)) + (PORT datad (1322:1322:1322) (1340:1340:1340)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (1031:1031:1031) (1058:1058:1058)) + (PORT datab (908:908:908) (923:923:923)) + (PORT datac (1253:1253:1253) (1263:1263:1263)) + (PORT datad (1057:1057:1057) (1056:1056:1056)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal48\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1858:1858:1858) (1995:1995:1995)) + (PORT datab (1127:1127:1127) (1169:1169:1169)) + (PORT datac (1094:1094:1094) (1124:1124:1124)) + (PORT datad (1097:1097:1097) (1095:1095:1095)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal10\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1302:1302:1302) (1412:1412:1412)) + (PORT datab (1142:1142:1142) (1161:1161:1161)) + (PORT datac (1416:1416:1416) (1496:1496:1496)) + (PORT datad (1415:1415:1415) (1457:1457:1457)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal11\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1303:1303:1303) (1412:1412:1412)) + (PORT datab (1142:1142:1142) (1161:1161:1161)) + (PORT datac (1417:1417:1417) (1497:1497:1497)) + (PORT datad (1416:1416:1416) (1457:1457:1457)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal63\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1584:1584:1584) (1669:1669:1669)) + (PORT datab (1398:1398:1398) (1416:1416:1416)) + (PORT datac (1197:1197:1197) (1227:1227:1227)) + (PORT datad (607:607:607) (645:645:645)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf2_we) + (DELAY + (ABSOLUTE + (PORT dataa (1069:1069:1069) (1066:1066:1066)) + (PORT datab (1314:1314:1314) (1282:1282:1282)) + (PORT datac (1315:1315:1315) (1324:1324:1324)) + (PORT datad (847:847:847) (884:884:884)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~41) + (DELAY + (ABSOLUTE + (PORT dataa (2165:2165:2165) (2175:2175:2175)) + (PORT datab (1600:1600:1600) (1609:1609:1609)) + (PORT datac (182:182:182) (217:217:217)) + (PORT datad (1277:1277:1277) (1250:1250:1250)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal68\~3) + (DELAY + (ABSOLUTE + (PORT dataa (859:859:859) (885:885:885)) + (PORT datab (1232:1232:1232) (1297:1297:1297)) + (PORT datac (791:791:791) (796:796:796)) + (PORT datad (864:864:864) (900:900:900)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~7) + (DELAY + (ABSOLUTE + (PORT dataa (220:220:220) (258:258:258)) + (PORT datab (190:190:190) (225:225:225)) + (PORT datac (1131:1131:1131) (1158:1158:1158)) + (PORT datad (990:990:990) (1037:1037:1037)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1005:1005:1005) (1003:1003:1003)) + (PORT datab (1465:1465:1465) (1468:1468:1468)) + (PORT datac (1523:1523:1523) (1503:1503:1503)) + (PORT datad (798:798:798) (817:817:817)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~9) + (DELAY + (ABSOLUTE + (PORT dataa (558:558:558) (555:555:555)) + (PORT datab (1596:1596:1596) (1618:1618:1618)) + (PORT datac (1749:1749:1749) (1787:1787:1787)) + (PORT datad (787:787:787) (847:847:847)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (951:951:951) (1035:1035:1035)) + (PORT datad (922:922:922) (1015:1015:1015)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (669:669:669) (724:724:724)) + (PORT datab (205:205:205) (242:242:242)) + (PORT datac (1183:1183:1183) (1203:1203:1203)) + (PORT datad (897:897:897) (956:956:956)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~14) + (DELAY + (ABSOLUTE + (PORT dataa (671:671:671) (721:721:721)) + (PORT datab (966:966:966) (1050:1050:1050)) + (PORT datac (1184:1184:1184) (1205:1205:1205)) + (PORT datad (918:918:918) (984:984:984)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~4) + (DELAY + (ABSOLUTE + (PORT dataa (822:822:822) (810:810:810)) + (PORT datab (1775:1775:1775) (1814:1814:1814)) + (PORT datac (1568:1568:1568) (1588:1588:1588)) + (PORT datad (564:564:564) (577:577:577)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1115:1115:1115) (1113:1113:1113)) + (PORT datab (1541:1541:1541) (1569:1569:1569)) + (PORT datac (504:504:504) (496:496:496)) + (PORT datad (1282:1282:1282) (1235:1235:1235)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1531:1531:1531) (1521:1521:1521)) + (PORT datab (602:602:602) (622:622:622)) + (PORT datac (840:840:840) (865:865:865)) + (PORT datad (886:886:886) (917:917:917)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~6) + (DELAY + (ABSOLUTE + (PORT dataa (805:805:805) (850:850:850)) + (PORT datab (1417:1417:1417) (1432:1432:1432)) + (PORT datac (1523:1523:1523) (1503:1503:1503)) + (PORT datad (1334:1334:1334) (1313:1313:1313)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~9) + (DELAY + (ABSOLUTE + (PORT dataa (184:184:184) (221:221:221)) + (PORT datab (188:188:188) (225:225:225)) + (PORT datac (156:156:156) (187:187:187)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_iorw\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1442:1442:1442) (1527:1527:1527)) + (PORT datab (1387:1387:1387) (1391:1391:1391)) + (PORT datac (1254:1254:1254) (1363:1363:1363)) + (PORT datad (1414:1414:1414) (1463:1463:1463)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1300:1300:1300) (1410:1410:1410)) + (PORT datab (1140:1140:1140) (1162:1162:1162)) + (PORT datac (1414:1414:1414) (1494:1494:1494)) + (PORT datad (1413:1413:1413) (1458:1458:1458)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~18) + (DELAY + (ABSOLUTE + (PORT dataa (869:869:869) (883:883:883)) + (PORT datab (2312:2312:2312) (2248:2248:2248)) + (PORT datac (804:804:804) (809:809:809)) + (PORT datad (777:777:777) (767:767:767)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal37\~0) + (DELAY + (ABSOLUTE + (PORT dataa (901:901:901) (941:941:941)) + (PORT datab (623:623:623) (608:608:608)) + (PORT datac (557:557:557) (582:582:582)) + (PORT datad (627:627:627) (656:656:656)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~19) + (DELAY + (ABSOLUTE + (PORT dataa (973:973:973) (993:993:993)) + (PORT datab (1090:1090:1090) (1093:1093:1093)) + (PORT datac (1076:1076:1076) (1090:1090:1090)) + (PORT datad (1651:1651:1651) (1677:1677:1677)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal35\~0) + (DELAY + (ABSOLUTE + (PORT dataa (902:902:902) (939:939:939)) + (PORT datab (624:624:624) (609:609:609)) + (PORT datac (516:516:516) (509:509:509)) + (PORT datad (630:630:630) (660:660:660)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal21\~1) + (DELAY + (ABSOLUTE + (PORT dataa (213:213:213) (267:267:267)) + (PORT datab (817:817:817) (837:837:837)) + (PORT datac (1128:1128:1128) (1155:1155:1155)) + (PORT datad (1262:1262:1262) (1348:1348:1348)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1303:1303:1303) (1326:1326:1326)) + (PORT datab (971:971:971) (1005:1005:1005)) + (PORT datac (778:778:778) (788:788:788)) + (PORT datad (1534:1534:1534) (1567:1567:1567)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~20) + (DELAY + (ABSOLUTE + (PORT dataa (787:787:787) (792:792:792)) + (PORT datab (806:806:806) (817:817:817)) + (PORT datac (154:154:154) (184:184:184)) + (PORT datad (161:161:161) (182:182:182)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1218:1218:1218) (1239:1239:1239)) + (PORT datab (201:201:201) (235:235:235)) + (PORT datac (636:636:636) (682:682:682)) + (PORT datad (898:898:898) (957:957:957)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1043:1043:1043) (1064:1064:1064)) + (PORT datab (1404:1404:1404) (1472:1472:1472)) + (PORT datac (879:879:879) (890:890:890)) + (PORT datad (2344:2344:2344) (2344:2344:2344)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~15) + (DELAY + (ABSOLUTE + (PORT dataa (669:669:669) (724:724:724)) + (PORT datab (969:969:969) (1056:1056:1056)) + (PORT datac (1183:1183:1183) (1203:1203:1203)) + (PORT datad (919:919:919) (990:990:990)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1350:1350:1350) (1357:1357:1357)) + (PORT datab (1052:1052:1052) (1053:1053:1053)) + (PORT datac (154:154:154) (184:184:184)) + (PORT datad (866:866:866) (887:887:887)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~7) + (DELAY + (ABSOLUTE + (PORT dataa (665:665:665) (713:713:713)) + (PORT datab (960:960:960) (1056:1056:1056)) + (PORT datac (1181:1181:1181) (1201:1201:1201)) + (PORT datad (925:925:925) (995:995:995)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal46\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1561:1561:1561) (1578:1578:1578)) + (PORT datab (241:241:241) (314:314:314)) + (PORT datac (216:216:216) (286:286:286)) + (PORT datad (359:359:359) (396:396:396)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~11) + (DELAY + (ABSOLUTE + (PORT dataa (955:955:955) (1038:1038:1038)) + (PORT datab (964:964:964) (1049:1049:1049)) + (PORT datac (626:626:626) (662:662:662)) + (PORT datad (1062:1062:1062) (1042:1042:1042)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~3) + (DELAY + (ABSOLUTE + (PORT dataa (643:643:643) (644:644:644)) + (PORT datab (1366:1366:1366) (1354:1354:1354)) + (PORT datac (864:864:864) (861:861:861)) + (PORT datad (839:839:839) (843:843:843)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal52\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1166:1166:1166) (1161:1161:1161)) + (PORT datab (916:916:916) (986:986:986)) + (PORT datac (586:586:586) (592:592:592)) + (PORT datad (911:911:911) (984:984:984)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~21) + (DELAY + (ABSOLUTE + (PORT dataa (2221:2221:2221) (2238:2238:2238)) + (PORT datab (1157:1157:1157) (1214:1214:1214)) + (PORT datac (753:753:753) (734:734:734)) + (PORT datad (355:355:355) (370:370:370)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~13) + (DELAY + (ABSOLUTE + (PORT dataa (567:567:567) (584:584:584)) + (PORT datab (1153:1153:1153) (1143:1143:1143)) + (PORT datac (697:697:697) (669:669:669)) + (PORT datad (1014:1014:1014) (1005:1005:1005)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~6) + (DELAY + (ABSOLUTE + (PORT dataa (447:447:447) (516:516:516)) + (PORT datab (441:441:441) (517:517:517)) + (PORT datac (1124:1124:1124) (1125:1125:1125)) + (PORT datad (186:186:186) (211:211:211)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1408:1408:1408) (1406:1406:1406)) + (PORT datac (926:926:926) (950:950:950)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~14) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (238:238:238)) + (PORT datab (200:200:200) (232:232:232)) + (PORT datac (1045:1045:1045) (1061:1061:1061)) + (PORT datad (1445:1445:1445) (1506:1506:1506)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (1478:1478:1478) (1483:1483:1483)) + (PORT datab (1777:1777:1777) (1752:1752:1752)) + (PORT datac (1526:1526:1526) (1498:1498:1498)) + (PORT datad (508:508:508) (502:502:502)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (736:736:736) (769:769:769)) + (PORT datab (1071:1071:1071) (1075:1075:1075)) + (PORT datac (574:574:574) (581:581:581)) + (PORT datad (178:178:178) (200:200:200)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1902:1902:1902) (1948:1948:1948)) + (PORT datab (621:621:621) (606:606:606)) + (PORT datac (799:799:799) (780:780:780)) + (PORT datad (628:628:628) (657:657:657)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|rsel0) + (DELAY + (ABSOLUTE + (PORT datab (1398:1398:1398) (1421:1421:1421)) + (PORT datac (1334:1334:1334) (1375:1375:1375)) + (PORT datad (846:846:846) (894:894:894)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1960:1960:1960) (2001:2001:2001)) + (PORT datac (1430:1430:1430) (1477:1477:1477)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~0) + (DELAY + (ABSOLUTE + (PORT dataa (834:834:834) (833:833:833)) + (PORT datab (823:823:823) (828:828:828)) + (PORT datac (753:753:753) (748:748:748)) + (PORT datad (826:826:826) (903:903:903)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~2) + (DELAY + (ABSOLUTE + (PORT datab (366:366:366) (415:415:415)) + (PORT datad (400:400:400) (446:446:446)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_ixy_dT2_2) + (DELAY + (ABSOLUTE + (PORT dataa (1021:1021:1021) (1042:1042:1042)) + (PORT datad (1605:1605:1605) (1621:1621:1621)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (901:901:901) (917:917:917)) + (PORT datab (201:201:201) (243:243:243)) + (PORT datac (1269:1269:1269) (1334:1334:1334)) + (PORT datad (1170:1170:1170) (1168:1168:1168)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1301:1301:1301) (1322:1322:1322)) + (PORT datab (1572:1572:1572) (1595:1595:1595)) + (PORT datac (1490:1490:1490) (1503:1503:1503)) + (PORT datad (1141:1141:1141) (1170:1170:1170)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1046:1046:1046) (1001:1001:1001)) + (PORT datab (2074:2074:2074) (2114:2114:2114)) + (PORT datac (714:714:714) (757:757:757)) + (PORT datad (1806:1806:1806) (1858:1858:1858)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~5) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (238:238:238)) + (PORT datab (199:199:199) (233:233:233)) + (PORT datac (362:362:362) (421:421:421)) + (PORT datad (364:364:364) (405:405:405)) (IOPATH dataa combout (299:299:299) (304:304:304)) (IOPATH datab combout (300:300:300) (312:312:312)) (IOPATH datac combout (220:220:220) (215:215:215)) @@ -14374,14 +4200,30 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~47) + (INSTANCE z80_\|execute_\|ctl_sw_2u\~1) (DELAY (ABSOLUTE - (PORT dataa (370:370:370) (377:377:377)) - (PORT datab (194:194:194) (231:231:231)) - (PORT datac (581:581:581) (601:601:601)) - (PORT datad (179:179:179) (201:201:201)) - (IOPATH dataa combout (273:273:273) (269:269:269)) + (PORT dataa (401:401:401) (438:438:438)) + (PORT datab (2161:2161:2161) (2172:2172:2172)) + (PORT datac (1272:1272:1272) (1286:1286:1286)) + (PORT datad (556:556:556) (554:554:554)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1599:1599:1599) (1613:1613:1613)) + (PORT datab (273:273:273) (364:364:364)) + (PORT datac (1698:1698:1698) (1674:1674:1674)) + (PORT datad (538:538:538) (528:528:528)) + (IOPATH dataa combout (265:265:265) (273:273:273)) (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -14390,13 +4232,447 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~74) + (INSTANCE z80_\|execute_\|ctl_mWrite\~7) + (DELAY + (ABSOLUTE + (PORT dataa (567:567:567) (573:573:573)) + (PORT datab (1728:1728:1728) (1705:1705:1705)) + (PORT datac (571:571:571) (597:597:597)) + (PORT datad (250:250:250) (332:332:332)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1023:1023:1023) (1042:1042:1042)) + (PORT datab (199:199:199) (232:232:232)) + (PORT datac (1007:1007:1007) (982:982:982)) + (PORT datad (759:759:759) (744:744:744)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~57) + (DELAY + (ABSOLUTE + (PORT dataa (643:643:643) (671:671:671)) + (PORT datab (1036:1036:1036) (1098:1098:1098)) + (PORT datac (1165:1165:1165) (1160:1160:1160)) + (PORT datad (1282:1282:1282) (1283:1283:1283)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~5) + (DELAY + (ABSOLUTE + (PORT datab (801:801:801) (829:829:829)) + (PORT datac (757:757:757) (754:754:754)) + (PORT datad (1023:1023:1023) (1020:1020:1020)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~7) + (DELAY + (ABSOLUTE + (PORT dataa (883:883:883) (922:922:922)) + (PORT datab (813:813:813) (804:804:804)) + (PORT datac (737:737:737) (732:732:732)) + (PORT datad (173:173:173) (202:202:202)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla91pla21M4T2_3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1946:1946:1946) (1988:1988:1988)) + (PORT datab (1108:1108:1108) (1123:1123:1123)) + (PORT datac (1553:1553:1553) (1548:1548:1548)) + (PORT datad (1365:1365:1365) (1392:1392:1392)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~41) + (DELAY + (ABSOLUTE + (PORT dataa (1947:1947:1947) (1987:1987:1987)) + (PORT datab (1603:1603:1603) (1608:1608:1608)) + (PORT datac (2581:2581:2581) (2554:2554:2554)) + (PORT datad (855:855:855) (871:871:871)) + (IOPATH dataa combout (267:267:267) (273:273:273)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~86) + (DELAY + (ABSOLUTE + (PORT dataa (1439:1439:1439) (1510:1510:1510)) + (PORT datab (1122:1122:1122) (1130:1130:1130)) + (PORT datac (1604:1604:1604) (1638:1638:1638)) + (PORT datad (1208:1208:1208) (1291:1291:1291)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~88) + (DELAY + (ABSOLUTE + (PORT dataa (1439:1439:1439) (1505:1505:1505)) + (PORT datab (1601:1601:1601) (1606:1606:1606)) + (PORT datac (1496:1496:1496) (1581:1581:1581)) + (PORT datad (1413:1413:1413) (1449:1449:1449)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~36) + (DELAY + (ABSOLUTE + (PORT dataa (1210:1210:1210) (1257:1257:1257)) + (PORT datab (1282:1282:1282) (1314:1314:1314)) + (PORT datac (1076:1076:1076) (1080:1080:1080)) + (PORT datad (157:157:157) (178:178:178)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~87) + (DELAY + (ABSOLUTE + (PORT dataa (1441:1441:1441) (1506:1506:1506)) + (PORT datab (1231:1231:1231) (1319:1319:1319)) + (PORT datac (847:847:847) (852:852:852)) + (PORT datad (1415:1415:1415) (1450:1450:1450)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~26) + (DELAY + (ABSOLUTE + (PORT dataa (190:190:190) (231:231:231)) + (PORT datab (188:188:188) (223:223:223)) + (PORT datad (178:178:178) (199:199:199)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~9) + (DELAY + (ABSOLUTE + (PORT datab (1490:1490:1490) (1586:1586:1586)) + (PORT datac (1326:1326:1326) (1355:1355:1355)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~1) + (DELAY + (ABSOLUTE + (PORT dataa (2608:2608:2608) (2587:2587:2587)) + (PORT datab (892:892:892) (910:910:910)) + (PORT datac (1911:1911:1911) (1956:1956:1956)) + (PORT datad (1021:1021:1021) (1007:1007:1007)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~42) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (219:219:219)) + (PORT datab (180:180:180) (213:213:213)) + (PORT datac (546:546:546) (550:550:550)) + (PORT datad (164:164:164) (190:190:190)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal40\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1439:1439:1439) (1526:1526:1526)) + (PORT datab (1437:1437:1437) (1471:1471:1471)) + (PORT datac (1246:1246:1246) (1362:1362:1362)) + (PORT datad (1417:1417:1417) (1458:1458:1458)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~14) + (DELAY + (ABSOLUTE + (PORT dataa (604:604:604) (598:598:598)) + (PORT datab (1166:1166:1166) (1197:1197:1197)) + (PORT datac (2281:2281:2281) (2345:2345:2345)) + (PORT datad (1088:1088:1088) (1110:1110:1110)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal55\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1440:1440:1440) (1523:1523:1523)) + (PORT datac (1247:1247:1247) (1355:1355:1355)) + (PORT datad (1415:1415:1415) (1461:1461:1461)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1728:1728:1728) (1800:1800:1800)) + (PORT datab (1689:1689:1689) (1706:1706:1706)) + (PORT datac (628:628:628) (663:663:663)) + (PORT datad (1641:1641:1641) (1691:1691:1691)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal6\~1) + (DELAY + (ABSOLUTE + (PORT dataa (905:905:905) (970:970:970)) + (PORT datab (1402:1402:1402) (1418:1418:1418)) + (PORT datac (937:937:937) (969:969:969)) + (PORT datad (1527:1527:1527) (1614:1614:1614)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~36) + (DELAY + (ABSOLUTE + (PORT dataa (1852:1852:1852) (1865:1865:1865)) + (PORT datab (2306:2306:2306) (2371:2371:2371)) + (PORT datac (843:843:843) (847:847:847)) + (PORT datad (1091:1091:1091) (1113:1113:1113)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|comb\~1) + (DELAY + (ABSOLUTE + (PORT datab (1012:1012:1012) (1098:1098:1098)) + (PORT datad (1497:1497:1497) (1456:1456:1456)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1047:1047:1047) (1026:1026:1026)) + (PORT datab (1531:1531:1531) (1593:1593:1593)) + (PORT datac (1946:1946:1946) (1990:1990:1990)) + (PORT datad (818:818:818) (840:840:840)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1293:1293:1293) (1266:1266:1266)) + (PORT datab (631:631:631) (669:669:669)) + (PORT datac (878:878:878) (899:899:899)) + (PORT datad (611:611:611) (638:638:638)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal24\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1585:1585:1585) (1670:1670:1670)) + (PORT datab (599:599:599) (619:619:619)) + (PORT datac (1975:1975:1975) (2011:2011:2011)) + (PORT datad (608:608:608) (646:646:646)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~26) + (DELAY + (ABSOLUTE + (PORT dataa (1586:1586:1586) (1571:1571:1571)) + (PORT datab (1931:1931:1931) (1987:1987:1987)) + (PORT datac (1204:1204:1204) (1234:1234:1234)) + (PORT datad (626:626:626) (641:641:641)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~37) + (DELAY + (ABSOLUTE + (PORT dataa (1332:1332:1332) (1325:1325:1325)) + (PORT datab (180:180:180) (212:212:212)) + (PORT datac (566:566:566) (567:567:567)) + (PORT datad (177:177:177) (197:197:197)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~6) (DELAY (ABSOLUTE (PORT dataa (202:202:202) (240:240:240)) - (PORT datab (199:199:199) (233:233:233)) - (PORT datac (817:817:817) (795:795:795)) - (PORT datad (178:178:178) (200:200:200)) + (PORT datab (588:588:588) (571:571:571)) + (PORT datac (763:763:763) (746:746:746)) + (PORT datad (588:588:588) (592:592:592)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\~38) + (DELAY + (ABSOLUTE + (PORT dataa (667:667:667) (702:702:702)) + (PORT datab (1691:1691:1691) (1709:1709:1709)) + (PORT datac (1253:1253:1253) (1217:1217:1217)) + (PORT datad (878:878:878) (887:887:887)) (IOPATH dataa combout (287:287:287) (289:289:289)) (IOPATH datab combout (295:295:295) (294:294:294)) (IOPATH datac combout (218:218:218) (215:215:215)) @@ -14404,16 +4680,310 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1348:1348:1348) (1382:1382:1382)) + (PORT datab (206:206:206) (240:240:240)) + (PORT datac (819:819:819) (826:826:826)) + (PORT datad (167:167:167) (191:191:191)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1127:1127:1127) (1165:1165:1165)) + (PORT datab (918:918:918) (950:950:950)) + (PORT datad (1507:1507:1507) (1485:1485:1485)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~31) + (DELAY + (ABSOLUTE + (PORT dataa (856:856:856) (874:874:874)) + (PORT datab (1214:1214:1214) (1241:1241:1241)) + (PORT datac (623:623:623) (637:637:637)) + (PORT datad (1831:1831:1831) (1951:1951:1951)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla38pla13M4T2_4) + (DELAY + (ABSOLUTE + (PORT dataa (865:865:865) (876:876:876)) + (PORT datab (856:856:856) (870:870:870)) + (PORT datac (531:531:531) (526:526:526)) + (PORT datad (1496:1496:1496) (1557:1557:1557)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|nM1_int\~2) + (DELAY + (ABSOLUTE + (PORT datac (1512:1512:1512) (1540:1540:1540)) + (PORT datad (1752:1752:1752) (1814:1814:1814)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~0) + (DELAY + (ABSOLUTE + (PORT datab (1650:1650:1650) (1702:1702:1702)) + (PORT datad (1150:1150:1150) (1193:1193:1193)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (916:916:916) (931:931:931)) + (PORT datab (811:811:811) (813:813:813)) + (PORT datac (1094:1094:1094) (1078:1078:1078)) + (PORT datad (615:615:615) (635:635:635)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~6) + (DELAY + (ABSOLUTE + (PORT dataa (588:588:588) (592:592:592)) + (PORT datab (870:870:870) (876:876:876)) + (PORT datac (621:621:621) (649:649:649)) + (PORT datad (182:182:182) (209:209:209)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~12) + (DELAY + (ABSOLUTE + (PORT dataa (885:885:885) (947:947:947)) + (PORT datab (1153:1153:1153) (1184:1184:1184)) + (PORT datac (1412:1412:1412) (1496:1496:1496)) + (PORT datad (1190:1190:1190) (1193:1193:1193)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1470:1470:1470) (1534:1534:1534)) + (PORT datab (1258:1258:1258) (1221:1221:1221)) + (PORT datac (168:168:168) (208:208:208)) + (PORT datad (1246:1246:1246) (1303:1303:1303)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal25\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1349:1349:1349) (1364:1364:1364)) + (PORT datab (1526:1526:1526) (1586:1586:1586)) + (PORT datac (1484:1484:1484) (1560:1560:1560)) + (PORT datad (816:816:816) (832:832:832)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal12\~1) + (DELAY + (ABSOLUTE + (PORT dataa (903:903:903) (973:973:973)) + (PORT datab (1399:1399:1399) (1419:1419:1419)) + (PORT datac (1974:1974:1974) (2009:2009:2009)) + (PORT datad (1536:1536:1536) (1623:1623:1623)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~38) + (DELAY + (ABSOLUTE + (PORT dataa (1326:1326:1326) (1296:1296:1296)) + (PORT datab (1831:1831:1831) (1886:1886:1886)) + (PORT datac (570:570:570) (576:576:576)) + (PORT datad (185:185:185) (212:212:212)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~82) + (DELAY + (ABSOLUTE + (PORT dataa (1188:1188:1188) (1251:1251:1251)) + (PORT datab (1406:1406:1406) (1420:1420:1420)) + (PORT datad (1376:1376:1376) (1414:1414:1414)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1113:1113:1113) (1116:1116:1116)) + (PORT datab (560:560:560) (571:571:571)) + (PORT datac (542:542:542) (554:554:554)) + (PORT datad (579:579:579) (585:585:585)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (333:333:333) (349:349:349)) + (PORT datab (1390:1390:1390) (1366:1366:1366)) + (PORT datac (175:175:175) (206:206:206)) + (PORT datad (165:165:165) (190:190:190)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~32) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (248:248:248)) + (PORT datab (206:206:206) (243:243:243)) + (PORT datac (1542:1542:1542) (1509:1509:1509)) + (PORT datad (565:565:565) (557:557:557)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~77) + (DELAY + (ABSOLUTE + (PORT dataa (1209:1209:1209) (1214:1214:1214)) + (PORT datab (1443:1443:1443) (1508:1508:1508)) + (PORT datac (795:795:795) (789:789:789)) + (PORT datad (1910:1910:1910) (1866:1866:1866)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal29\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1210:1210:1210) (1237:1237:1237)) + (PORT datab (828:828:828) (827:827:827)) + (PORT datac (679:679:679) (752:752:752)) + (PORT datad (1638:1638:1638) (1668:1668:1668)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_inc_cy\~78) (DELAY (ABSOLUTE - (PORT datab (189:189:189) (224:224:224)) - (PORT datac (582:582:582) (603:603:603)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT dataa (1208:1208:1208) (1217:1217:1217)) + (PORT datab (1441:1441:1441) (1510:1510:1510)) + (PORT datac (155:155:155) (186:186:186)) + (PORT datad (1013:1013:1013) (1011:1011:1011)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -14423,184 +4993,12 @@ (INSTANCE z80_\|execute_\|ctl_inc_cy\~79) (DELAY (ABSOLUTE - (PORT dataa (191:191:191) (233:233:233)) - (PORT datab (319:319:319) (333:333:333)) - (PORT datac (584:584:584) (590:590:590)) - (PORT datad (167:167:167) (194:194:194)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~80) - (DELAY - (ABSOLUTE - (PORT dataa (618:618:618) (636:636:636)) - (PORT datab (848:848:848) (883:883:883)) - (PORT datac (1100:1100:1100) (1143:1143:1143)) - (PORT datad (171:171:171) (199:199:199)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~81) - (DELAY - (ABSOLUTE - (PORT dataa (815:815:815) (833:833:833)) - (PORT datab (632:632:632) (662:662:662)) - (PORT datac (893:893:893) (935:935:935)) - (PORT datad (575:575:575) (598:598:598)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~82) - (DELAY - (ABSOLUTE - (PORT dataa (181:181:181) (217:217:217)) - (PORT datab (624:624:624) (666:666:666)) - (PORT datac (899:899:899) (931:931:931)) - (PORT datad (1543:1543:1543) (1538:1538:1538)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~83) - (DELAY - (ABSOLUTE - (PORT dataa (190:190:190) (231:231:231)) - (PORT datab (312:312:312) (331:331:331)) - (PORT datac (583:583:583) (588:588:588)) - (PORT datad (334:334:334) (333:333:333)) + (PORT dataa (208:208:208) (248:248:248)) + (PORT datab (2069:2069:2069) (2110:2110:2110)) + (PORT datac (739:739:739) (781:781:781)) + (PORT datad (1807:1807:1807) (1859:1859:1859)) (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~84) - (DELAY - (ABSOLUTE - (PORT datab (186:186:186) (221:221:221)) - (PORT datac (162:162:162) (195:195:195)) - (PORT datad (165:165:165) (187:187:187)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~42) - (DELAY - (ABSOLUTE - (PORT datab (603:603:603) (606:606:606)) - (PORT datac (315:315:315) (333:333:333)) - (PORT datad (165:165:165) (189:189:189)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~90) - (DELAY - (ABSOLUTE - (PORT dataa (940:940:940) (985:985:985)) - (PORT datab (1013:1013:1013) (1022:1022:1022)) - (PORT datac (1086:1086:1086) (1108:1108:1108)) - (PORT datad (1371:1371:1371) (1420:1420:1420)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~41) - (DELAY - (ABSOLUTE - (PORT dataa (204:204:204) (249:249:249)) - (PORT datab (580:580:580) (599:599:599)) - (PORT datac (186:186:186) (223:223:223)) - (PORT datad (165:165:165) (187:187:187)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~66) - (DELAY - (ABSOLUTE - (PORT dataa (325:325:325) (453:453:453)) - (PORT datab (841:841:841) (855:855:855)) - (PORT datac (1095:1095:1095) (1138:1138:1138)) - (PORT datad (249:249:249) (317:317:317)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~67) - (DELAY - (ABSOLUTE - (PORT dataa (1034:1034:1034) (1029:1029:1029)) - (PORT datab (205:205:205) (243:243:243)) - (PORT datac (175:175:175) (220:220:220)) - (PORT datad (804:804:804) (807:807:807)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~68) - (DELAY - (ABSOLUTE - (PORT dataa (1338:1338:1338) (1364:1364:1364)) - (PORT datab (179:179:179) (212:212:212)) - (PORT datac (154:154:154) (184:184:184)) - (PORT datad (1522:1522:1522) (1538:1538:1538)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -14608,64 +5006,16 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~64) + (INSTANCE z80_\|execute_\|ctl_mRead\~14) (DELAY (ABSOLUTE - (PORT dataa (1034:1034:1034) (1029:1029:1029)) - (PORT datab (212:212:212) (249:249:249)) - (PORT datac (175:175:175) (219:219:219)) - (PORT datad (550:550:550) (559:559:559)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~63) - (DELAY - (ABSOLUTE - (PORT dataa (812:812:812) (790:790:790)) - (PORT datab (1045:1045:1045) (1051:1051:1051)) - (PORT datac (319:319:319) (335:335:335)) - (PORT datad (796:796:796) (792:792:792)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~65) - (DELAY - (ABSOLUTE - (PORT dataa (1065:1065:1065) (1069:1069:1069)) - (PORT datab (349:349:349) (358:358:358)) - (PORT datac (290:290:290) (293:293:293)) - (PORT datad (157:157:157) (177:177:177)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~69) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (219:219:219)) - (PORT datab (182:182:182) (215:215:215)) - (PORT datac (308:308:308) (313:313:313)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (PORT dataa (902:902:902) (970:970:970)) + (PORT datab (596:596:596) (616:616:616)) + (PORT datac (1086:1086:1086) (1127:1127:1127)) + (PORT datad (591:591:591) (620:620:620)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -14675,44 +5025,12 @@ (INSTANCE z80_\|execute_\|ctl_inc_cy\~49) (DELAY (ABSOLUTE - (PORT dataa (616:616:616) (636:636:636)) - (PORT datab (384:384:384) (391:391:391)) - (PORT datac (1039:1039:1039) (1029:1029:1029)) - (PORT datad (795:795:795) (794:794:794)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~50) - (DELAY - (ABSOLUTE - (PORT dataa (615:615:615) (641:641:641)) - (PORT datab (870:870:870) (898:898:898)) - (PORT datac (1048:1048:1048) (1038:1038:1038)) - (PORT datad (1587:1587:1587) (1611:1611:1611)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~51) - (DELAY - (ABSOLUTE - (PORT dataa (349:349:349) (355:355:355)) - (PORT datab (1054:1054:1054) (1048:1048:1048)) - (PORT datac (972:972:972) (945:945:945)) - (PORT datad (1110:1110:1110) (1100:1100:1100)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (275:275:275) (275:275:275)) + (PORT dataa (1471:1471:1471) (1494:1494:1494)) + (PORT datab (1173:1173:1173) (1169:1169:1169)) + (PORT datac (949:949:949) (1001:1001:1001)) + (PORT datad (2260:2260:2260) (2354:2354:2354)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -14720,29 +5038,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~52) + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~5) (DELAY (ABSOLUTE - (PORT dataa (603:603:603) (639:639:639)) - (PORT datab (843:843:843) (842:842:842)) - (PORT datac (842:842:842) (866:866:866)) - (PORT datad (294:294:294) (292:292:292)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~36) - (DELAY - (ABSOLUTE - (PORT dataa (842:842:842) (884:884:884)) - (PORT datab (831:831:831) (839:839:839)) - (PORT datac (1318:1318:1318) (1302:1302:1302)) - (PORT datad (794:794:794) (793:793:793)) + (PORT dataa (878:878:878) (905:905:905)) + (PORT datab (889:889:889) (907:907:907)) + (PORT datac (2583:2583:2583) (2556:2556:2556)) + (PORT datad (2261:2261:2261) (2352:2352:2352)) (IOPATH dataa combout (265:265:265) (273:273:273)) (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (215:215:215)) @@ -14752,910 +5054,30 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~37) + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~40) (DELAY (ABSOLUTE - (PORT dataa (1346:1346:1346) (1338:1338:1338)) - (PORT datab (841:841:841) (888:888:888)) - (PORT datac (300:300:300) (317:317:317)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~54) - (DELAY - (ABSOLUTE - (PORT dataa (205:205:205) (251:251:251)) - (PORT datab (183:183:183) (217:217:217)) - (PORT datac (154:154:154) (184:184:184)) - (PORT datad (548:548:548) (534:534:534)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~41) - (DELAY - (ABSOLUTE - (PORT dataa (1097:1097:1097) (1113:1113:1113)) - (PORT datab (1059:1059:1059) (1091:1091:1091)) - (PORT datac (334:334:334) (354:354:354)) - (PORT datad (1059:1059:1059) (1083:1083:1083)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~58) - (DELAY - (ABSOLUTE - (PORT dataa (1029:1029:1029) (1030:1030:1030)) - (PORT datab (1064:1064:1064) (1084:1084:1084)) - (PORT datad (178:178:178) (199:199:199)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~55) - (DELAY - (ABSOLUTE - (PORT dataa (882:882:882) (905:905:905)) - (PORT datab (843:843:843) (841:841:841)) - (PORT datac (591:591:591) (607:607:607)) - (PORT datad (1424:1424:1424) (1478:1478:1478)) - (IOPATH dataa combout (307:307:307) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~56) - (DELAY - (ABSOLUTE - (PORT dataa (418:418:418) (445:445:445)) - (PORT datab (200:200:200) (234:234:234)) - (PORT datac (753:753:753) (732:732:732)) - (PORT datad (177:177:177) (199:199:199)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~89) - (DELAY - (ABSOLUTE - (PORT dataa (1230:1230:1230) (1279:1279:1279)) - (PORT datab (1072:1072:1072) (1037:1037:1037)) - (PORT datac (1318:1318:1318) (1311:1311:1311)) - (PORT datad (785:785:785) (799:799:799)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~57) - (DELAY - (ABSOLUTE - (PORT dataa (189:189:189) (228:228:228)) - (PORT datab (775:775:775) (761:761:761)) - (PORT datac (295:295:295) (301:301:301)) - (PORT datad (157:157:157) (178:178:178)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~59) - (DELAY - (ABSOLUTE - (PORT dataa (836:836:836) (835:835:835)) - (PORT datab (181:181:181) (213:213:213)) - (PORT datac (549:549:549) (539:539:539)) - (PORT datad (160:160:160) (182:182:182)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~60) - (DELAY - (ABSOLUTE - (PORT dataa (1064:1064:1064) (1070:1070:1070)) - (PORT datab (199:199:199) (231:231:231)) - (PORT datac (517:517:517) (505:505:505)) - (PORT datad (522:522:522) (514:514:514)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~47) - (DELAY - (ABSOLUTE - (PORT dataa (1017:1017:1017) (1017:1017:1017)) - (PORT datab (191:191:191) (231:231:231)) - (PORT datac (989:989:989) (981:981:981)) - (PORT datad (171:171:171) (202:202:202)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~88) - (DELAY - (ABSOLUTE - (PORT dataa (1491:1491:1491) (1562:1562:1562)) - (PORT datab (813:813:813) (800:800:800)) - (PORT datac (2318:2318:2318) (2351:2351:2351)) - (PORT datad (1368:1368:1368) (1417:1417:1417)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~48) - (DELAY - (ABSOLUTE - (PORT dataa (557:557:557) (543:543:543)) - (PORT datab (546:546:546) (527:527:527)) - (PORT datac (156:156:156) (186:186:186)) - (PORT datad (1045:1045:1045) (1037:1037:1037)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~40) - (DELAY - (ABSOLUTE - (PORT datab (603:603:603) (606:606:606)) - (PORT datac (317:317:317) (331:331:331)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~61) - (DELAY - (ABSOLUTE - (PORT dataa (209:209:209) (251:251:251)) - (PORT datab (193:193:193) (234:234:234)) - (PORT datac (986:986:986) (981:981:981)) - (PORT datad (1053:1053:1053) (1063:1063:1063)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~62) - (DELAY - (ABSOLUTE - (PORT dataa (1067:1067:1067) (1075:1075:1075)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (511:511:511) (508:508:508)) - (PORT datad (370:370:370) (382:382:382)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~70) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (219:219:219)) - (PORT datab (182:182:182) (215:215:215)) - (PORT datac (153:153:153) (183:183:183)) - (PORT datad (158:158:158) (178:178:178)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~85) - (DELAY - (ABSOLUTE - (PORT dataa (1047:1047:1047) (1031:1031:1031)) - (PORT datab (1034:1034:1034) (999:999:999)) - (PORT datac (993:993:993) (991:991:991)) - (PORT datad (1086:1086:1086) (1100:1100:1100)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|d0_out) - (DELAY - (ABSOLUTE - (PORT datac (646:646:646) (694:694:694)) - (PORT datad (338:338:338) (349:349:349)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (219:219:219)) - (PORT datab (882:882:882) (898:898:898)) - (PORT datac (626:626:626) (663:663:663)) - (PORT datad (314:314:314) (326:326:326)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[0\]) - (DELAY - (ABSOLUTE - (PORT datac (934:934:934) (903:903:903)) - (PORT datad (852:852:852) (845:845:845)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|Q\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (164:164:164) (187:187:187)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1363:1363:1363)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1400:1400:1400) (1370:1370:1370)) - (PORT ena (1924:1924:1924) (1928:1928:1928)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_41) - (DELAY - (ABSOLUTE - (PORT dataa (1071:1071:1071) (1059:1059:1059)) - (PORT datab (920:920:920) (926:926:926)) - (PORT datac (642:642:642) (688:688:688)) - (PORT datad (183:183:183) (207:207:207)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1363:1363:1363) (1384:1384:1384)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1175:1175:1175) (1170:1170:1170)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1362:1362:1362)) - (PORT asdata (899:899:899) (920:920:920)) - (PORT ena (1105:1105:1105) (1078:1078:1078)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (328:328:328) (354:354:354)) - (PORT datab (642:642:642) (662:662:662)) - (PORT datad (1099:1099:1099) (1119:1119:1119)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~5) - (DELAY - (ABSOLUTE - (PORT datab (679:679:679) (706:706:706)) - (PORT datac (197:197:197) (264:264:264)) - (PORT datad (568:568:568) (585:585:585)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|d1_out) - (DELAY - (ABSOLUTE - (PORT dataa (783:783:783) (805:805:805)) - (PORT datab (376:376:376) (384:384:384)) - (PORT datac (175:175:175) (207:207:207)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (219:219:219)) - (PORT datab (883:883:883) (896:896:896)) - (PORT datac (627:627:627) (664:664:664)) - (PORT datad (315:315:315) (324:324:324)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[1\]) - (DELAY - (ABSOLUTE - (PORT datab (370:370:370) (379:379:379)) - (PORT datad (322:322:322) (329:329:329)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1363:1363:1363) (1384:1384:1384)) - (PORT asdata (485:485:485) (512:512:512)) - (PORT clrn (1409:1409:1409) (1380:1380:1380)) - (PORT ena (1969:1969:1969) (1997:1997:1997)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_40\~4) - (DELAY - (ABSOLUTE - (PORT dataa (929:929:929) (948:948:948)) - (PORT datab (1064:1064:1064) (1061:1061:1061)) - (PORT datac (753:753:753) (774:774:774)) - (PORT datad (331:331:331) (342:342:342)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|d0_out) - (DELAY - (ABSOLUTE - (PORT dataa (388:388:388) (392:392:392)) - (PORT datab (200:200:200) (233:233:233)) - (PORT datac (214:214:214) (279:279:279)) - (PORT datad (307:307:307) (308:308:308)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (656:656:656) (692:692:692)) - (PORT datab (885:885:885) (898:898:898)) - (PORT datac (579:579:579) (599:599:599)) - (PORT datad (491:491:491) (483:483:483)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[2\]) - (DELAY - (ABSOLUTE - (PORT dataa (516:516:516) (518:518:518)) - (PORT datad (192:192:192) (224:224:224)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|Q\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (178:178:178) (199:199:199)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1363:1363:1363) (1384:1384:1384)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1409:1409:1409) (1380:1380:1380)) - (PORT ena (1976:1976:1976) (1995:1995:1995)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_42) - (DELAY - (ABSOLUTE - (PORT dataa (355:355:355) (379:379:379)) - (PORT datab (1064:1064:1064) (1065:1065:1065)) - (PORT datac (891:891:891) (917:917:917)) - (PORT datad (368:368:368) (400:400:400)) + (PORT dataa (1364:1364:1364) (1356:1356:1356)) + (PORT datab (194:194:194) (233:233:233)) + (PORT datac (167:167:167) (205:205:205)) (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~86) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (236:236:236)) - (PORT datab (186:186:186) (223:223:223)) - (PORT datac (160:160:160) (192:192:192)) - (PORT datad (164:164:164) (187:187:187)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|SYNTHESIZED_WIRE_0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (385:385:385) (389:389:389)) - (PORT datab (1032:1032:1032) (997:997:997)) - (PORT datac (998:998:998) (976:976:976)) - (PORT datad (1091:1091:1091) (1105:1105:1105)) - (IOPATH dataa combout (307:307:307) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1068:1068:1068) (1057:1057:1057)) - (PORT datab (915:915:915) (924:924:924)) - (PORT datac (886:886:886) (910:910:910)) - (PORT datad (1039:1039:1039) (1026:1026:1026)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|carry_borrow_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (783:783:783) (807:807:807)) - (PORT datab (1284:1284:1284) (1227:1227:1227)) - (PORT datac (641:641:641) (688:688:688)) - (PORT datad (342:342:342) (353:353:353)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|d1_out) - (DELAY - (ABSOLUTE - (PORT datab (186:186:186) (223:223:223)) - (PORT datac (307:307:307) (317:317:317)) - (PORT datad (222:222:222) (282:282:282)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1371:1371:1371)) - (PORT asdata (1283:1283:1283) (1264:1264:1264)) - (PORT ena (746:746:746) (759:759:759)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1371:1371:1371)) - (PORT asdata (1285:1285:1285) (1265:1265:1265)) - (PORT ena (1154:1154:1154) (1142:1142:1142)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~45) - (DELAY - (ABSOLUTE - (PORT dataa (389:389:389) (434:434:434)) - (PORT datab (546:546:546) (555:555:555)) - (PORT datad (200:200:200) (257:257:257)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[3\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (755:755:755) (755:755:755)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1342:1342:1342) (1359:1359:1359)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1295:1295:1295) (1246:1246:1246)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1342:1342:1342) (1359:1359:1359)) - (PORT asdata (1067:1067:1067) (1060:1060:1060)) - (PORT ena (1155:1155:1155) (1140:1140:1140)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~48) - (DELAY - (ABSOLUTE - (PORT dataa (578:578:578) (596:596:596)) - (PORT datab (774:774:774) (774:774:774)) - (PORT datad (589:589:589) (599:599:599)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1370:1370:1370)) - (PORT asdata (1104:1104:1104) (1099:1099:1099)) - (PORT ena (744:744:744) (751:751:751)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1370:1370:1370)) - (PORT asdata (1103:1103:1103) (1102:1102:1102)) - (PORT ena (1123:1123:1123) (1106:1106:1106)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~49) - (DELAY - (ABSOLUTE - (PORT dataa (603:603:603) (646:646:646)) - (PORT datab (223:223:223) (293:293:293)) - (PORT datad (347:347:347) (360:360:360)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[3\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (753:753:753) (752:752:752)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1342:1342:1342) (1359:1359:1359)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1381:1381:1381) (1365:1365:1365)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1342:1342:1342) (1359:1359:1359)) - (PORT asdata (1070:1070:1070) (1064:1064:1064)) - (PORT ena (1109:1109:1109) (1074:1074:1074)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~41) - (DELAY - (ABSOLUTE - (PORT dataa (869:869:869) (865:865:865)) - (PORT datab (565:565:565) (561:561:561)) - (PORT datac (513:513:513) (507:507:507)) - (PORT datad (1405:1405:1405) (1456:1456:1456)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~42) - (DELAY - (ABSOLUTE - (PORT dataa (889:889:889) (908:908:908)) - (PORT datab (536:536:536) (546:546:546)) - (PORT datac (918:918:918) (935:935:935)) - (PORT datad (794:794:794) (808:808:808)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datab combout (295:295:295) (300:300:300)) (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~43) + (INSTANCE z80_\|execute_\|ctl_mRead\~5) (DELAY (ABSOLUTE - (PORT dataa (201:201:201) (238:238:238)) - (PORT datab (619:619:619) (648:648:648)) - (PORT datac (157:157:157) (188:188:188)) - (PORT datad (156:156:156) (177:177:177)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (PORT dataa (1126:1126:1126) (1162:1162:1162)) + (PORT datab (1706:1706:1706) (1684:1684:1684)) + (PORT datac (837:837:837) (859:859:859)) + (PORT datad (881:881:881) (912:912:912)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -15665,12 +5087,58 @@ (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~44) (DELAY (ABSOLUTE - (PORT dataa (503:503:503) (496:496:496)) - (PORT datab (572:572:572) (561:561:561)) - (PORT datac (790:790:790) (807:807:807)) - (PORT datad (567:567:567) (574:574:574)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (295:295:295) (285:285:285)) + (PORT dataa (611:611:611) (628:628:628)) + (PORT datab (442:442:442) (509:509:509)) + (PORT datac (535:535:535) (533:533:533)) + (PORT datad (423:423:423) (475:475:475)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (308:308:308) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~36) + (DELAY + (ABSOLUTE + (PORT dataa (1113:1113:1113) (1126:1126:1126)) + (PORT datab (805:805:805) (784:784:784)) + (PORT datac (834:834:834) (842:842:842)) + (PORT datad (873:873:873) (879:879:879)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~35) + (DELAY + (ABSOLUTE + (PORT dataa (1124:1124:1124) (1149:1149:1149)) + (PORT datab (1068:1068:1068) (1086:1086:1086)) + (PORT datad (573:573:573) (579:579:579)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~46) + (DELAY + (ABSOLUTE + (PORT dataa (1654:1654:1654) (1695:1695:1695)) + (PORT datab (181:181:181) (213:213:213)) + (PORT datac (1560:1560:1560) (1586:1586:1586)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -15678,15 +5146,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~45) + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~33) (DELAY (ABSOLUTE - (PORT dataa (580:580:580) (606:606:606)) - (PORT datab (600:600:600) (612:612:612)) - (PORT datac (1070:1070:1070) (1099:1099:1099)) - (PORT datad (550:550:550) (550:550:550)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) + (PORT dataa (1103:1103:1103) (1098:1098:1098)) + (PORT datab (880:880:880) (891:891:891)) + (PORT datac (1323:1323:1323) (1319:1319:1319)) + (PORT datad (582:582:582) (598:598:598)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -15694,342 +5162,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~46) + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~47) (DELAY (ABSOLUTE - (PORT dataa (190:190:190) (231:231:231)) - (PORT datab (181:181:181) (215:215:215)) - (PORT datac (566:566:566) (567:567:567)) - (PORT datad (167:167:167) (190:190:190)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_48) - (DELAY - (ABSOLUTE - (PORT datab (1320:1320:1320) (1344:1344:1344)) - (PORT datac (1116:1116:1116) (1136:1136:1136)) - (PORT datad (788:788:788) (810:810:810)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_44) - (DELAY - (ABSOLUTE - (PORT datab (1320:1320:1320) (1346:1346:1346)) - (PORT datac (1120:1120:1120) (1139:1139:1139)) - (PORT datad (785:785:785) (795:795:795)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_45) - (DELAY - (ABSOLUTE - (PORT datab (1321:1321:1321) (1338:1338:1338)) - (PORT datac (1109:1109:1109) (1129:1129:1129)) - (PORT datad (785:785:785) (793:793:793)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT asdata (933:933:933) (955:955:955)) - (PORT ena (906:906:906) (905:905:905)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_49) - (DELAY - (ABSOLUTE - (PORT datab (1321:1321:1321) (1339:1339:1339)) - (PORT datac (1111:1111:1111) (1130:1130:1130)) - (PORT datad (790:790:790) (811:811:811)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT asdata (936:936:936) (957:957:957)) - (PORT ena (893:893:893) (877:877:877)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~40) - (DELAY - (ABSOLUTE - (PORT dataa (425:425:425) (472:472:472)) - (PORT datab (450:450:450) (480:480:480)) - (PORT datad (198:198:198) (255:255:255)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_52) - (DELAY - (ABSOLUTE - (PORT datab (1320:1320:1320) (1340:1340:1340)) - (PORT datac (1115:1115:1115) (1134:1134:1134)) - (PORT datad (999:999:999) (984:984:984)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_57) - (DELAY - (ABSOLUTE - (PORT datab (1320:1320:1320) (1346:1346:1346)) - (PORT datac (1120:1120:1120) (1139:1139:1139)) - (PORT datad (916:916:916) (925:925:925)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1346:1346:1346) (1363:1363:1363)) - (PORT asdata (1093:1093:1093) (1077:1077:1077)) - (PORT ena (1281:1281:1281) (1292:1292:1292)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_53) - (DELAY - (ABSOLUTE - (PORT datab (1321:1321:1321) (1342:1342:1342)) - (PORT datac (1119:1119:1119) (1139:1139:1139)) - (PORT datad (1001:1001:1001) (985:985:985)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1346:1346:1346) (1363:1363:1363)) - (PORT asdata (1095:1095:1095) (1080:1080:1080)) - (PORT ena (1271:1271:1271) (1296:1296:1296)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_56) - (DELAY - (ABSOLUTE - (PORT datab (1323:1323:1323) (1343:1343:1343)) - (PORT datac (1122:1122:1122) (1141:1141:1141)) - (PORT datad (914:914:914) (922:922:922)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~41) - (DELAY - (ABSOLUTE - (PORT dataa (831:831:831) (892:892:892)) - (PORT datab (221:221:221) (290:290:290)) - (PORT datad (799:799:799) (856:856:856)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_33) - (DELAY - (ABSOLUTE - (PORT datab (1114:1114:1114) (1152:1152:1152)) - (PORT datac (829:829:829) (849:849:849)) - (PORT datad (833:833:833) (842:842:842)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1346:1346:1346) (1363:1363:1363)) - (PORT asdata (1119:1119:1119) (1113:1113:1113)) - (PORT ena (720:720:720) (722:722:722)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[3\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (869:869:869) (898:898:898)) - (PORT datab (1114:1114:1114) (1148:1148:1148)) - (PORT datad (821:821:821) (832:832:832)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1080:1080:1080) (1087:1087:1087)) - (PORT datab (186:186:186) (222:222:222)) - (PORT datac (1680:1680:1680) (1729:1729:1729)) - (PORT datad (181:181:181) (218:218:218)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~12) - (DELAY - (ABSOLUTE - (PORT dataa (816:816:816) (809:809:809)) - (PORT datab (187:187:187) (223:223:223)) - (PORT datac (561:561:561) (588:588:588)) - (PORT datad (806:806:806) (810:810:810)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_29) - (DELAY - (ABSOLUTE - (PORT dataa (1359:1359:1359) (1373:1373:1373)) - (PORT datac (773:773:773) (748:748:748)) - (PORT datad (1042:1042:1042) (1034:1034:1034)) + (PORT dataa (1434:1434:1434) (1472:1472:1472)) + (PORT datab (1101:1101:1101) (1114:1114:1114)) + (PORT datac (1054:1054:1054) (1053:1053:1053)) + (PORT datad (2325:2325:2325) (2374:2374:2374)) (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1343:1343:1343) (1360:1360:1360)) - (PORT asdata (906:906:906) (925:925:925)) - (PORT ena (716:716:716) (714:714:714)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_28) + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla9M1T5_2) (DELAY (ABSOLUTE - (PORT dataa (1361:1361:1361) (1373:1373:1373)) - (PORT datac (774:774:774) (748:748:748)) - (PORT datad (1045:1045:1045) (1035:1035:1035)) - (IOPATH dataa combout (307:307:307) (306:306:306)) + (PORT dataa (989:989:989) (1005:1005:1005)) + (PORT datab (1573:1573:1573) (1529:1529:1529)) + (PORT datac (768:768:768) (837:837:837)) + (PORT datad (883:883:883) (925:925:925)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -16037,80 +5194,59 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~44) + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~45) (DELAY (ABSOLUTE - (PORT dataa (1007:1007:1007) (991:991:991)) - (PORT datab (1073:1073:1073) (1081:1081:1081)) - (PORT datad (219:219:219) (252:252:252)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) + (PORT dataa (881:881:881) (909:909:909)) + (PORT datab (1642:1642:1642) (1723:1723:1723)) + (PORT datac (1431:1431:1431) (1501:1501:1501)) + (PORT datad (1668:1668:1668) (1705:1705:1705)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[3\]\~feeder) + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~34) (DELAY (ABSOLUTE - (PORT datad (614:614:614) (637:637:637)) + (PORT dataa (884:884:884) (868:868:868)) + (PORT datab (907:907:907) (909:909:909)) + (PORT datac (1535:1535:1535) (1523:1523:1523)) + (PORT datad (571:571:571) (576:576:576)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_69) + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla10M5T4_2) (DELAY (ABSOLUTE - (PORT datab (1043:1043:1043) (1038:1038:1038)) - (PORT datac (1294:1294:1294) (1292:1292:1292)) - (PORT datad (762:762:762) (769:769:769)) - (IOPATH datab combout (275:275:275) (275:275:275)) + (PORT dataa (1118:1118:1118) (1135:1135:1135)) + (PORT datac (1206:1206:1206) (1284:1284:1284)) + (PORT datad (1673:1673:1673) (1709:1709:1709)) + (IOPATH dataa combout (273:273:273) (269:269:269)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1361:1361:1361)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (716:716:716) (714:714:714)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_68\~2) + (INSTANCE z80_\|execute_\|ctl_mWrite\~6) (DELAY (ABSOLUTE - (PORT dataa (859:859:859) (888:888:888)) - (PORT datab (1113:1113:1113) (1147:1147:1147)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_64\~0) - (DELAY - (ABSOLUTE - (PORT dataa (376:376:376) (406:406:406)) - (PORT datab (876:876:876) (897:897:897)) - (PORT datac (1060:1060:1060) (1056:1056:1056)) - (PORT datad (615:615:615) (618:618:618)) + (PORT dataa (904:904:904) (971:971:971)) + (PORT datab (1006:1006:1006) (1031:1031:1031)) + (PORT datac (562:562:562) (582:582:582)) + (PORT datad (1530:1530:1530) (1616:1616:1616)) (IOPATH dataa combout (287:287:287) (289:289:289)) (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) @@ -16120,11 +5256,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_69\~2) + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~50) (DELAY (ABSOLUTE - (PORT datac (1323:1323:1323) (1335:1335:1335)) - (PORT datad (1042:1042:1042) (1031:1031:1031)) + (PORT dataa (1062:1062:1062) (1080:1080:1080)) + (PORT datab (909:909:909) (937:937:937)) + (PORT datac (904:904:904) (964:964:964)) + (PORT datad (1184:1184:1184) (1225:1225:1225)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (348:348:348) (379:379:379)) + (PORT datab (368:368:368) (372:372:372)) + (PORT datac (1176:1176:1176) (1232:1232:1232)) + (PORT datad (177:177:177) (199:199:199)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -16132,44 +5288,500 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_65\~0) + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~48) (DELAY (ABSOLUTE - (PORT dataa (1091:1091:1091) (1108:1108:1108)) - (PORT datab (755:755:755) (739:739:739)) - (PORT datac (1047:1047:1047) (1044:1044:1044)) - (PORT datad (615:615:615) (635:635:635)) + (PORT dataa (325:325:325) (342:342:342)) + (PORT datab (799:799:799) (868:868:868)) + (PORT datac (743:743:743) (779:779:779)) + (PORT datad (882:882:882) (921:921:921)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~49) + (DELAY + (ABSOLUTE + (PORT dataa (939:939:939) (991:991:991)) + (PORT datab (630:630:630) (664:664:664)) + (PORT datac (1118:1118:1118) (1140:1140:1140)) + (PORT datad (1409:1409:1409) (1433:1433:1433)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~7) + (DELAY + (ABSOLUTE + (PORT dataa (864:864:864) (877:877:877)) + (PORT datab (856:856:856) (872:872:872)) + (PORT datad (1491:1491:1491) (1556:1556:1556)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~29) + (DELAY + (ABSOLUTE + (PORT dataa (926:926:926) (959:959:959)) + (PORT datab (1383:1383:1383) (1389:1389:1389)) + (PORT datac (976:976:976) (967:967:967)) + (PORT datad (1519:1519:1519) (1542:1542:1542)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~11) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (240:240:240)) + (PORT datab (219:219:219) (254:254:254)) + (PORT datac (2189:2189:2189) (2218:2218:2218)) + (PORT datad (917:917:917) (980:980:980)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~27) + (DELAY + (ABSOLUTE + (PORT dataa (1285:1285:1285) (1294:1294:1294)) + (PORT datab (577:577:577) (591:591:591)) + (PORT datac (877:877:877) (898:898:898)) + (PORT datad (374:374:374) (401:401:401)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~44) + (DELAY + (ABSOLUTE + (PORT dataa (863:863:863) (896:896:896)) + (PORT datab (887:887:887) (890:890:890)) + (PORT datac (1722:1722:1722) (1761:1761:1761)) + (PORT datad (1728:1728:1728) (1817:1817:1817)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~28) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (240:240:240)) + (PORT datab (367:367:367) (373:373:373)) + (PORT datad (772:772:772) (746:746:746)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~30) + (DELAY + (ABSOLUTE + (PORT dataa (825:825:825) (848:848:848)) + (PORT datab (779:779:779) (751:751:751)) + (PORT datad (796:796:796) (798:798:798)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1207:1207:1207) (1239:1239:1239)) + (PORT datab (1768:1768:1768) (1837:1837:1837)) + (PORT datac (675:675:675) (748:748:748)) + (PORT datad (764:764:764) (761:761:761)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~3) + (DELAY + (ABSOLUTE + (PORT dataa (657:657:657) (709:709:709)) + (PORT datab (961:961:961) (1048:1048:1048)) + (PORT datac (1179:1179:1179) (1198:1198:1198)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~37) + (DELAY + (ABSOLUTE + (PORT dataa (1001:1001:1001) (969:969:969)) + (PORT datab (912:912:912) (914:914:914)) + (PORT datac (1143:1143:1143) (1151:1151:1151)) + (PORT datad (578:578:578) (566:566:566)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~38) + (DELAY + (ABSOLUTE + (PORT dataa (577:577:577) (592:592:592)) + (PORT datab (1223:1223:1223) (1287:1287:1287)) + (PORT datac (836:836:836) (828:828:828)) + (PORT datad (157:157:157) (178:178:178)) (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~39) + (DELAY + (ABSOLUTE + (PORT dataa (181:181:181) (216:216:216)) + (PORT datab (180:180:180) (213:213:213)) + (PORT datac (156:156:156) (187:187:187)) + (PORT datad (157:157:157) (177:177:177)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[3\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~43) (DELAY (ABSOLUTE - (PORT clk (1344:1344:1344) (1361:1361:1361)) - (PORT asdata (1390:1390:1390) (1376:1376:1376)) - (PORT ena (1039:1039:1039) (993:993:993)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (PORT dataa (1054:1054:1054) (1078:1078:1078)) + (PORT datab (604:604:604) (613:613:613)) + (PORT datac (1075:1075:1075) (1079:1079:1079)) + (PORT datad (1117:1117:1117) (1123:1123:1123)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_68) + (INSTANCE z80_\|execute_\|ctl_alu_oe\~3) (DELAY (ABSOLUTE - (PORT datab (1043:1043:1043) (1039:1039:1039)) - (PORT datac (1294:1294:1294) (1292:1292:1292)) - (PORT datad (762:762:762) (766:766:766)) + (PORT dataa (1597:1597:1597) (1617:1617:1617)) + (PORT datab (275:275:275) (368:368:368)) + (PORT datac (1701:1701:1701) (1679:1679:1679)) + (PORT datad (542:542:542) (536:536:536)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~1) + (DELAY + (ABSOLUTE + (PORT dataa (635:635:635) (665:665:665)) + (PORT datab (1632:1632:1632) (1644:1644:1644)) + (PORT datac (622:622:622) (653:653:653)) + (PORT datad (798:798:798) (810:810:810)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~1) + (DELAY + (ABSOLUTE + (PORT datab (1091:1091:1091) (1072:1072:1072)) + (PORT datac (1292:1292:1292) (1300:1300:1300)) + (PORT datad (1115:1115:1115) (1124:1124:1124)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1405:1405:1405) (1422:1422:1422)) + (PORT datab (952:952:952) (994:994:994)) + (PORT datac (786:786:786) (796:796:796)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~17) + (DELAY + (ABSOLUTE + (PORT dataa (334:334:334) (365:365:365)) + (PORT datab (871:871:871) (882:882:882)) + (PORT datad (569:569:569) (584:584:584)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_iorw\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1444:1444:1444) (1531:1531:1531)) + (PORT datab (1388:1388:1388) (1391:1391:1391)) + (PORT datac (1258:1258:1258) (1369:1369:1369)) + (PORT datad (1411:1411:1411) (1456:1456:1456)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~47) + (DELAY + (ABSOLUTE + (PORT dataa (868:868:868) (882:882:882)) + (PORT datab (868:868:868) (879:879:879)) + (PORT datac (169:169:169) (207:207:207)) + (PORT datad (1468:1468:1468) (1388:1388:1388)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1510:1510:1510) (1590:1590:1590)) + (PORT datab (1524:1524:1524) (1585:1585:1585)) + (PORT datac (1947:1947:1947) (1988:1988:1988)) + (PORT datad (814:814:814) (835:835:835)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~13) + (DELAY + (ABSOLUTE + (PORT datab (1092:1092:1092) (1074:1074:1074)) + (PORT datac (1295:1295:1295) (1304:1304:1304)) + (PORT datad (1114:1114:1114) (1120:1120:1120)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~48) + (DELAY + (ABSOLUTE + (PORT dataa (605:605:605) (615:615:615)) + (PORT datac (1008:1008:1008) (969:969:969)) + (PORT datad (527:527:527) (512:512:512)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~0) + (DELAY + (ABSOLUTE + (PORT dataa (834:834:834) (847:847:847)) + (PORT datab (1378:1378:1378) (1380:1380:1380)) + (PORT datac (770:770:770) (780:780:780)) + (PORT datad (178:178:178) (200:200:200)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla57M1T4_4) + (DELAY + (ABSOLUTE + (PORT datab (1036:1036:1036) (1098:1098:1098)) + (PORT datac (2194:2194:2194) (2237:2237:2237)) + (PORT datad (1282:1282:1282) (1283:1283:1283)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~9) + (DELAY + (ABSOLUTE + (PORT datac (771:771:771) (841:841:841)) + (PORT datad (882:882:882) (921:921:921)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (2375:2375:2375) (2341:2341:2341)) + (PORT datab (1569:1569:1569) (1597:1597:1597)) + (PORT datac (1896:1896:1896) (1893:1893:1893)) + (PORT datad (853:853:853) (884:884:884)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla12M3T1_2) + (DELAY + (ABSOLUTE + (PORT datab (1461:1461:1461) (1494:1494:1494)) + (PORT datac (1657:1657:1657) (1683:1683:1683)) + (PORT datad (881:881:881) (972:972:972)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1046:1046:1046) (1088:1088:1088)) + (PORT datab (1926:1926:1926) (1918:1918:1918)) + (PORT datac (1325:1325:1325) (1374:1374:1374)) + (PORT datad (809:809:809) (797:797:797)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1182:1182:1182) (1255:1255:1255)) + (PORT datab (1569:1569:1569) (1597:1597:1597)) + (PORT datac (1269:1269:1269) (1287:1287:1287)) + (PORT datad (1140:1140:1140) (1175:1175:1175)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~10) + (DELAY + (ABSOLUTE + (PORT dataa (774:774:774) (828:828:828)) + (PORT datab (760:760:760) (794:794:794)) + (PORT datac (330:330:330) (342:342:342)) + (PORT datad (577:577:577) (601:601:601)) + (IOPATH dataa combout (273:273:273) (269:269:269)) (IOPATH datab combout (295:295:295) (294:294:294)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -16178,28 +5790,519 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~43) + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~10) (DELAY (ABSOLUTE - (PORT dataa (351:351:351) (405:405:405)) - (PORT datab (813:813:813) (838:838:838)) - (PORT datad (339:339:339) (352:352:352)) - (IOPATH dataa combout (273:273:273) (269:269:269)) + (PORT dataa (866:866:866) (894:894:894)) + (PORT datab (984:984:984) (1034:1034:1034)) + (PORT datac (1651:1651:1651) (1716:1716:1716)) + (PORT datad (1045:1045:1045) (1044:1044:1044)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel_pla11M1T1_11) + (DELAY + (ABSOLUTE + (PORT datab (1135:1135:1135) (1170:1170:1170)) + (PORT datac (1071:1071:1071) (1142:1142:1142)) + (PORT datad (1402:1402:1402) (1399:1399:1399)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~11) + (DELAY + (ABSOLUTE + (PORT dataa (554:554:554) (555:555:555)) + (PORT datab (831:831:831) (866:866:866)) + (PORT datac (1313:1313:1313) (1395:1395:1395)) + (PORT datad (790:790:790) (803:803:803)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~11) + (DELAY + (ABSOLUTE + (PORT dataa (611:611:611) (641:641:641)) + (PORT datab (187:187:187) (224:224:224)) + (PORT datac (804:804:804) (839:839:839)) + (PORT datad (1736:1736:1736) (1766:1766:1766)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~1) + (DELAY + (ABSOLUTE + (PORT datac (173:173:173) (212:212:212)) + (PORT datad (190:190:190) (217:217:217)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~4) + (DELAY + (ABSOLUTE + (PORT datac (1167:1167:1167) (1211:1211:1211)) + (PORT datad (2204:2204:2204) (2262:2262:2262)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1389:1389:1389) (1456:1456:1456)) + (PORT datab (1793:1793:1793) (1818:1818:1818)) + (PORT datac (1178:1178:1178) (1209:1209:1209)) + (PORT datad (1377:1377:1377) (1384:1384:1384)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~4) + (DELAY + (ABSOLUTE + (PORT dataa (873:873:873) (900:900:900)) + (PORT datab (1356:1356:1356) (1334:1334:1334)) + (PORT datac (1119:1119:1119) (1150:1150:1150)) + (PORT datad (586:586:586) (606:606:606)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1104:1104:1104) (1109:1109:1109)) + (PORT datab (1317:1317:1317) (1302:1302:1302)) + (PORT datac (1517:1517:1517) (1519:1519:1519)) + (PORT datad (839:839:839) (843:843:843)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (533:533:533) (527:527:527)) + (PORT datab (585:585:585) (616:616:616)) + (PORT datac (593:593:593) (617:617:617)) + (PORT datad (1174:1174:1174) (1213:1213:1213)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~47) + (DELAY + (ABSOLUTE + (PORT dataa (209:209:209) (249:249:249)) + (PORT datab (1142:1142:1142) (1164:1164:1164)) + (PORT datac (1417:1417:1417) (1464:1464:1464)) + (PORT datad (2169:2169:2169) (2250:2250:2250)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1518:1518:1518) (1543:1543:1543)) + (PORT datab (1031:1031:1031) (1079:1079:1079)) + (PORT datac (892:892:892) (924:924:924)) + (PORT datad (165:165:165) (190:190:190)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1052:1052:1052) (1045:1045:1045)) + (PORT datab (1074:1074:1074) (1075:1075:1075)) + (PORT datac (359:359:359) (381:381:381)) + (PORT datad (878:878:878) (911:911:911)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~23) + (DELAY + (ABSOLUTE + (PORT dataa (2135:2135:2135) (2143:2143:2143)) + (PORT datab (1318:1318:1318) (1334:1334:1334)) + (PORT datac (587:587:587) (609:609:609)) + (PORT datad (1329:1329:1329) (1371:1371:1371)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1705:1705:1705) (1786:1786:1786)) + (PORT datab (198:198:198) (231:231:231)) + (PORT datac (1619:1619:1619) (1656:1656:1656)) + (PORT datad (598:598:598) (632:632:632)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~13) + (DELAY + (ABSOLUTE + (PORT dataa (533:533:533) (533:533:533)) + (PORT datab (822:822:822) (829:829:829)) + (PORT datac (556:556:556) (553:553:553)) + (PORT datad (941:941:941) (911:911:911)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1186:1186:1186) (1219:1219:1219)) + (PORT datab (1569:1569:1569) (1597:1597:1597)) + (PORT datac (1268:1268:1268) (1286:1286:1286)) + (PORT datad (1839:1839:1839) (1817:1817:1817)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~1) + (DELAY + (ABSOLUTE + (PORT datac (488:488:488) (486:486:486)) + (PORT datad (556:556:556) (562:562:562)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~29) + (DELAY + (ABSOLUTE + (PORT dataa (1028:1028:1028) (1050:1050:1050)) + (PORT datac (1466:1466:1466) (1567:1567:1567)) + (PORT datad (1602:1602:1602) (1618:1618:1618)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~14) + (DELAY + (ABSOLUTE + (PORT dataa (536:536:536) (534:534:534)) + (PORT datab (182:182:182) (213:213:213)) + (PORT datac (176:176:176) (206:206:206)) + (PORT datad (1099:1099:1099) (1091:1091:1091)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla77M1T1_3) + (DELAY + (ABSOLUTE + (PORT dataa (866:866:866) (892:892:892)) + (PORT datab (985:985:985) (1033:1033:1033)) + (PORT datac (1650:1650:1650) (1715:1715:1715)) + (PORT datad (1046:1046:1046) (1040:1040:1040)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel_pla82M1T1_16) + (DELAY + (ABSOLUTE + (PORT dataa (2022:2022:2022) (2092:2092:2092)) + (PORT datab (1159:1159:1159) (1197:1197:1197)) + (PORT datac (1080:1080:1080) (1096:1096:1096)) + (PORT datad (1470:1470:1470) (1466:1466:1466)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1587:1587:1587) (1625:1625:1625)) + (PORT datab (892:892:892) (873:873:873)) + (PORT datac (1119:1119:1119) (1143:1143:1143)) + (PORT datad (1834:1834:1834) (1852:1852:1852)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1666:1666:1666) (1729:1729:1729)) + (PORT datab (2228:2228:2228) (2265:2265:2265)) + (PORT datac (900:900:900) (936:936:936)) + (PORT datad (1537:1537:1537) (1535:1535:1535)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT datab (1123:1123:1123) (1122:1122:1122)) + (PORT datac (806:806:806) (838:838:838)) + (PORT datad (164:164:164) (189:189:189)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (393:393:393) (430:430:430)) + (PORT datab (2269:2269:2269) (2305:2305:2305)) + (PORT datac (1405:1405:1405) (1444:1444:1444)) + (PORT datad (179:179:179) (201:201:201)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1800:1800:1800) (1834:1834:1834)) + (PORT datab (1373:1373:1373) (1462:1462:1462)) + (PORT datac (1791:1791:1791) (1809:1809:1809)) + (PORT datad (751:751:751) (721:721:721)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal68\~2) + (DELAY + (ABSOLUTE + (PORT dataa (929:929:929) (997:997:997)) + (PORT datab (915:915:915) (985:985:985)) + (PORT datac (861:861:861) (937:937:937)) + (PORT datad (1114:1114:1114) (1167:1167:1167)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1072:1072:1072) (1099:1099:1099)) + (PORT datab (1468:1468:1468) (1535:1535:1535)) + (PORT datac (1798:1798:1798) (1859:1859:1859)) + (PORT datad (585:585:585) (606:606:606)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (330:330:330) (349:349:349)) + (PORT datab (313:313:313) (332:332:332)) + (PORT datac (566:566:566) (572:572:572)) + (PORT datad (544:544:544) (545:545:545)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1314:1314:1314) (1341:1341:1341)) + (PORT datab (1216:1216:1216) (1228:1228:1228)) + (PORT datac (2312:2312:2312) (2339:2339:2339)) + (PORT datad (583:583:583) (591:591:591)) + (IOPATH dataa combout (329:329:329) (332:332:332)) (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_76\~0) + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~8) (DELAY (ABSOLUTE - (PORT dataa (381:381:381) (416:416:416)) - (PORT datab (1312:1312:1312) (1291:1291:1291)) - (PORT datac (1056:1056:1056) (1048:1048:1048)) - (PORT datad (612:612:612) (615:615:615)) + (PORT dataa (885:885:885) (913:913:913)) + (PORT datac (175:175:175) (206:206:206)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~20) + (DELAY + (ABSOLUTE + (PORT dataa (1895:1895:1895) (1941:1941:1941)) + (PORT datab (1368:1368:1368) (1368:1368:1368)) + (PORT datac (1601:1601:1601) (1634:1634:1634)) + (PORT datad (1557:1557:1557) (1574:1574:1574)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~9) + (DELAY + (ABSOLUTE + (PORT dataa (544:544:544) (566:566:566)) + (PORT datab (1242:1242:1242) (1308:1308:1308)) + (PORT datac (533:533:533) (527:527:527)) + (PORT datad (542:542:542) (536:536:536)) (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) @@ -16209,13 +6312,481 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_77\~0) + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~1) (DELAY (ABSOLUTE - (PORT dataa (1067:1067:1067) (1076:1076:1076)) - (PORT datab (757:757:757) (741:741:741)) - (PORT datac (1055:1055:1055) (1050:1050:1050)) - (PORT datad (622:622:622) (644:644:644)) + (PORT dataa (1660:1660:1660) (1702:1702:1702)) + (PORT datab (1493:1493:1493) (1550:1550:1550)) + (PORT datac (1113:1113:1113) (1116:1116:1116)) + (PORT datad (1553:1553:1553) (1510:1510:1510)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~1) + (DELAY + (ABSOLUTE + (PORT datab (1568:1568:1568) (1591:1591:1591)) + (PORT datac (1267:1267:1267) (1282:1282:1282)) + (PORT datad (1143:1143:1143) (1177:1177:1177)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1211:1211:1211) (1294:1294:1294)) + (PORT datab (779:779:779) (760:760:760)) + (PORT datac (1341:1341:1341) (1438:1438:1438)) + (PORT datad (996:996:996) (1007:1007:1007)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~2) + (DELAY + (ABSOLUTE + (PORT datab (328:328:328) (345:345:345)) + (PORT datac (1726:1726:1726) (1713:1713:1713)) + (PORT datad (602:602:602) (602:602:602)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1961:1961:1961) (2014:2014:2014)) + (PORT datab (573:573:573) (590:590:590)) + (PORT datac (1205:1205:1205) (1252:1252:1252)) + (PORT datad (365:365:365) (394:394:394)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1959:1959:1959) (1993:1993:1993)) + (PORT datab (1678:1678:1678) (1722:1722:1722)) + (PORT datac (861:861:861) (858:858:858)) + (PORT datad (841:841:841) (855:855:855)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1326:1326:1326) (1291:1291:1291)) + (PORT datab (196:196:196) (234:234:234)) + (PORT datac (869:869:869) (857:857:857)) + (PORT datad (617:617:617) (651:651:651)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~19) + (DELAY + (ABSOLUTE + (PORT dataa (608:608:608) (618:618:618)) + (PORT datab (1657:1657:1657) (1694:1694:1694)) + (PORT datac (1177:1177:1177) (1233:1233:1233)) + (PORT datad (1221:1221:1221) (1222:1222:1222)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal1\~5) + (DELAY + (ABSOLUTE + (PORT datac (987:987:987) (1024:1024:1024)) + (PORT datad (1274:1274:1274) (1248:1248:1248)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~0) + (DELAY + (ABSOLUTE + (PORT dataa (872:872:872) (898:898:898)) + (PORT datab (1582:1582:1582) (1609:1609:1609)) + (PORT datac (1066:1066:1066) (1076:1076:1076)) + (PORT datad (1664:1664:1664) (1718:1718:1718)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel_pla12M1T1_12\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1643:1643:1643) (1684:1684:1684)) + (PORT datab (1964:1964:1964) (1990:1990:1990)) + (PORT datac (1103:1103:1103) (1143:1143:1143)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~1) + (DELAY + (ABSOLUTE + (PORT dataa (359:359:359) (370:370:370)) + (PORT datab (1964:1964:1964) (1991:1991:1991)) + (PORT datac (161:161:161) (193:193:193)) + (PORT datad (1660:1660:1660) (1745:1745:1745)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~7) + (DELAY + (ABSOLUTE + (PORT dataa (807:807:807) (799:799:799)) + (PORT datab (865:865:865) (936:936:936)) + (PORT datac (643:643:643) (692:692:692)) + (PORT datad (941:941:941) (957:957:957)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1300:1300:1300) (1323:1323:1323)) + (PORT datab (1569:1569:1569) (1600:1600:1600)) + (PORT datac (1543:1543:1543) (1559:1559:1559)) + (PORT datad (1140:1140:1140) (1176:1176:1176)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1158:1158:1158) (1241:1241:1241)) + (PORT datab (1295:1295:1295) (1339:1339:1339)) + (PORT datac (1594:1594:1594) (1625:1625:1625)) + (PORT datad (547:547:547) (543:543:543)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~8) + (DELAY + (ABSOLUTE + (PORT dataa (787:787:787) (788:788:788)) + (PORT datab (736:736:736) (715:715:715)) + (PORT datac (494:494:494) (479:479:479)) + (PORT datad (549:549:549) (540:540:540)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~15) + (DELAY + (ABSOLUTE + (PORT dataa (334:334:334) (347:347:347)) + (PORT datab (330:330:330) (346:346:346)) + (PORT datac (300:300:300) (306:306:306)) + (PORT datad (308:308:308) (315:315:315)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~7) + (DELAY + (ABSOLUTE + (PORT dataa (846:846:846) (843:843:843)) + (PORT datab (365:365:365) (371:371:371)) + (PORT datac (619:619:619) (647:647:647)) + (PORT datad (350:350:350) (362:362:362)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~12) + (DELAY + (ABSOLUTE + (PORT dataa (379:379:379) (401:401:401)) + (PORT datab (201:201:201) (236:236:236)) + (PORT datac (1407:1407:1407) (1446:1446:1446)) + (PORT datad (1132:1132:1132) (1181:1181:1181)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1475:1475:1475) (1535:1535:1535)) + (PORT datab (1896:1896:1896) (1923:1923:1923)) + (PORT datac (1934:1934:1934) (1967:1967:1967)) + (PORT datad (1769:1769:1769) (1778:1778:1778)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~10) + (DELAY + (ABSOLUTE + (PORT dataa (181:181:181) (216:216:216)) + (PORT datab (1307:1307:1307) (1322:1322:1322)) + (PORT datac (1034:1034:1034) (1024:1024:1024)) + (PORT datad (182:182:182) (208:208:208)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~8) + (DELAY + (ABSOLUTE + (PORT dataa (846:846:846) (870:870:870)) + (PORT datab (1389:1389:1389) (1440:1440:1440)) + (PORT datac (816:816:816) (826:826:826)) + (PORT datad (1175:1175:1175) (1213:1213:1213)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal64\~0) + (DELAY + (ABSOLUTE + (PORT dataa (931:931:931) (1011:1011:1011)) + (PORT datab (607:607:607) (635:635:635)) + (PORT datac (296:296:296) (312:312:312)) + (PORT datad (172:172:172) (198:198:198)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (585:585:585) (572:572:572)) + (PORT datab (1967:1967:1967) (1995:1995:1995)) + (PORT datac (1619:1619:1619) (1656:1656:1656)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal62\~2) + (DELAY + (ABSOLUTE + (PORT dataa (931:931:931) (1008:1008:1008)) + (PORT datab (604:604:604) (633:633:633)) + (PORT datac (298:298:298) (315:315:315)) + (PORT datad (171:171:171) (195:195:195)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1404:1404:1404) (1464:1464:1464)) + (PORT datab (1076:1076:1076) (1082:1082:1082)) + (PORT datac (192:192:192) (230:230:230)) + (PORT datad (1174:1174:1174) (1209:1209:1209)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~46) + (DELAY + (ABSOLUTE + (PORT dataa (1543:1543:1543) (1569:1569:1569)) + (PORT datab (1319:1319:1319) (1324:1324:1324)) + (PORT datac (595:595:595) (590:590:590)) + (PORT datad (2549:2549:2549) (2520:2520:2520)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1100:1100:1100) (1098:1098:1098)) + (PORT datab (2573:2573:2573) (2557:2557:2557)) + (PORT datac (1515:1515:1515) (1541:1541:1541)) + (PORT datad (1753:1753:1753) (1815:1815:1815)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~7) + (DELAY + (ABSOLUTE + (PORT dataa (612:612:612) (640:640:640)) + (PORT datab (605:605:605) (608:608:608)) + (PORT datac (1052:1052:1052) (1054:1054:1054)) + (PORT datad (159:159:159) (181:181:181)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~11) + (DELAY + (ABSOLUTE + (PORT dataa (633:633:633) (659:659:659)) + (PORT datab (326:326:326) (345:345:345)) + (PORT datac (850:850:850) (890:890:890)) + (PORT datad (172:172:172) (196:196:196)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal62\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1858:1858:1858) (1994:1994:1994)) + (PORT datab (1129:1129:1129) (1158:1158:1158)) + (PORT datac (890:890:890) (894:894:894)) + (PORT datad (1175:1175:1175) (1207:1207:1207)) (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) @@ -16223,14 +6794,1526 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1132:1132:1132) (1133:1133:1133)) + (PORT datab (604:604:604) (604:604:604)) + (PORT datac (2049:2049:2049) (2064:2064:2064)) + (PORT datad (1030:1030:1030) (1029:1029:1029)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (308:308:308) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (237:237:237)) + (PORT datab (841:841:841) (872:872:872)) + (PORT datac (743:743:743) (741:741:741)) + (PORT datad (1074:1074:1074) (1080:1080:1080)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (189:189:189) (230:230:230)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (157:157:157) (187:187:187)) + (PORT datad (177:177:177) (199:199:199)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~9) + (DELAY + (ABSOLUTE + (PORT dataa (541:541:541) (545:545:545)) + (PORT datab (199:199:199) (233:233:233)) + (PORT datac (763:763:763) (755:755:755)) + (PORT datad (585:585:585) (580:580:580)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~6) + (DELAY + (ABSOLUTE + (PORT dataa (906:906:906) (920:920:920)) + (PORT datab (1599:1599:1599) (1580:1580:1580)) + (PORT datac (883:883:883) (895:895:895)) + (PORT datad (614:614:614) (626:626:626)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~7) + (DELAY + (ABSOLUTE + (PORT dataa (908:908:908) (924:924:924)) + (PORT datab (864:864:864) (866:866:866)) + (PORT datac (881:881:881) (894:894:894)) + (PORT datad (177:177:177) (199:199:199)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~1) + (DELAY + (ABSOLUTE + (PORT dataa (570:570:570) (567:567:567)) + (PORT datab (1164:1164:1164) (1202:1202:1202)) + (PORT datac (1019:1019:1019) (1006:1006:1006)) + (PORT datad (508:508:508) (487:487:487)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (884:884:884) (894:894:894)) + (PORT datab (1156:1156:1156) (1175:1175:1175)) + (PORT datac (1134:1134:1134) (1174:1174:1174)) + (PORT datad (842:842:842) (856:856:856)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~4) + (DELAY + (ABSOLUTE + (PORT dataa (869:869:869) (888:888:888)) + (PORT datab (649:649:649) (657:657:657)) + (PORT datac (1575:1575:1575) (1561:1561:1561)) + (PORT datad (1028:1028:1028) (1020:1020:1020)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~5) + (DELAY + (ABSOLUTE + (PORT dataa (869:869:869) (892:892:892)) + (PORT datab (1051:1051:1051) (1057:1057:1057)) + (PORT datac (837:837:837) (840:840:840)) + (PORT datad (178:178:178) (199:199:199)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~2) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (220:220:220)) + (PORT datab (812:812:812) (807:807:807)) + (PORT datac (1088:1088:1088) (1081:1081:1081)) + (PORT datad (523:523:523) (524:524:524)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla21M2T3_4) + (DELAY + (ABSOLUTE + (PORT dataa (895:895:895) (929:929:929)) + (PORT datab (1549:1549:1549) (1548:1548:1548)) + (PORT datac (869:869:869) (943:943:943)) + (PORT datad (606:606:606) (641:641:641)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~6) + (DELAY + (ABSOLUTE + (PORT dataa (591:591:591) (584:584:584)) + (PORT datab (1556:1556:1556) (1672:1672:1672)) + (PORT datac (1263:1263:1263) (1310:1310:1310)) + (PORT datad (295:295:295) (304:304:304)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~12) + (DELAY + (ABSOLUTE + (PORT dataa (916:916:916) (946:946:946)) + (PORT datab (632:632:632) (666:666:666)) + (PORT datac (1262:1262:1262) (1307:1307:1307)) + (PORT datad (638:638:638) (658:658:658)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (999:999:999) (962:962:962)) + (PORT datab (1226:1226:1226) (1183:1183:1183)) + (PORT datac (1726:1726:1726) (1712:1712:1712)) + (PORT datad (588:588:588) (583:583:583)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~3) + (DELAY + (ABSOLUTE + (PORT dataa (334:334:334) (350:350:350)) + (PORT datab (765:765:765) (775:775:775)) + (PORT datac (162:162:162) (198:198:198)) + (PORT datad (557:557:557) (574:574:574)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_high) + (DELAY + (ABSOLUTE + (PORT dataa (2029:2029:2029) (2054:2054:2054)) + (PORT datab (1723:1723:1723) (1781:1781:1781)) + (PORT datac (495:495:495) (488:488:488)) + (PORT datad (1141:1141:1141) (1209:1209:1209)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1174:1174:1174) (1199:1199:1199)) + (PORT datab (1495:1495:1495) (1499:1499:1499)) + (PORT datac (1080:1080:1080) (1096:1096:1096)) + (PORT datad (1567:1567:1567) (1612:1612:1612)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1516:1516:1516) (1457:1457:1457)) + (PORT datab (1166:1166:1166) (1198:1198:1198)) + (PORT datac (2281:2281:2281) (2348:2348:2348)) + (PORT datad (841:841:841) (841:841:841)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal61\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1443:1443:1443) (1534:1534:1534)) + (PORT datab (1441:1441:1441) (1476:1476:1476)) + (PORT datac (1259:1259:1259) (1372:1372:1372)) + (PORT datad (1412:1412:1412) (1456:1456:1456)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1178:1178:1178) (1204:1204:1204)) + (PORT datab (1161:1161:1161) (1200:1200:1200)) + (PORT datac (1043:1043:1043) (1048:1048:1048)) + (PORT datad (575:575:575) (579:579:579)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1384:1384:1384) (1451:1451:1451)) + (PORT datab (1061:1061:1061) (1041:1041:1041)) + (PORT datac (987:987:987) (943:943:943)) + (PORT datad (658:658:658) (717:717:717)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1057:1057:1057) (1046:1046:1046)) + (PORT datab (791:791:791) (787:787:787)) + (PORT datac (789:789:789) (793:793:793)) + (PORT datad (1486:1486:1486) (1453:1453:1453)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~18) + (DELAY + (ABSOLUTE + (PORT dataa (603:603:603) (602:602:602)) + (PORT datab (1657:1657:1657) (1698:1698:1698)) + (PORT datac (1181:1181:1181) (1239:1239:1239)) + (PORT datad (1219:1219:1219) (1221:1221:1221)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~10) + (DELAY + (ABSOLUTE + (PORT dataa (569:569:569) (584:584:584)) + (PORT datab (1155:1155:1155) (1143:1143:1143)) + (PORT datac (696:696:696) (668:668:668)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~2) + (DELAY + (ABSOLUTE + (PORT datab (564:564:564) (552:552:552)) + (PORT datac (563:563:563) (582:582:582)) + (PORT datad (1728:1728:1728) (1709:1709:1709)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1851:1851:1851) (1985:1985:1985)) + (PORT datab (1128:1128:1128) (1168:1168:1168)) + (PORT datad (1097:1097:1097) (1091:1091:1091)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~3) + (DELAY + (ABSOLUTE + (PORT dataa (879:879:879) (904:904:904)) + (PORT datab (1148:1148:1148) (1195:1195:1195)) + (PORT datac (2531:2531:2531) (2581:2581:2581)) + (PORT datad (1281:1281:1281) (1254:1254:1254)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~26) + (DELAY + (ABSOLUTE + (PORT dataa (995:995:995) (1012:1012:1012)) + (PORT datab (1175:1175:1175) (1210:1210:1210)) + (PORT datac (1049:1049:1049) (1067:1067:1067)) + (PORT datad (1445:1445:1445) (1510:1510:1510)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus) + (DELAY + (ABSOLUTE + (PORT dataa (184:184:184) (220:220:220)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (182:182:182) (217:217:217)) + (PORT datad (178:178:178) (199:199:199)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_lo\~9) + (DELAY + (ABSOLUTE + (PORT dataa (2034:2034:2034) (2114:2114:2114)) + (PORT datab (683:683:683) (742:742:742)) + (PORT datac (1661:1661:1661) (1688:1688:1688)) + (PORT datad (857:857:857) (934:934:934)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (874:874:874) (913:913:913)) + (PORT datab (788:788:788) (803:803:803)) + (PORT datac (2001:2001:2001) (2027:2027:2027)) + (PORT datad (1591:1591:1591) (1635:1635:1635)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_oe\~1) + (DELAY + (ABSOLUTE + (PORT dataa (913:913:913) (933:933:933)) + (PORT datab (803:803:803) (814:814:814)) + (PORT datac (849:849:849) (885:885:885)) + (PORT datad (159:159:159) (181:181:181)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~6) + (DELAY + (ABSOLUTE + (PORT dataa (819:819:819) (821:821:821)) + (PORT datab (1541:1541:1541) (1556:1556:1556)) + (PORT datac (868:868:868) (854:854:854)) + (PORT datad (1282:1282:1282) (1245:1245:1245)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1378:1378:1378) (1472:1472:1472)) + (PORT datab (865:865:865) (888:888:888)) + (PORT datac (1325:1325:1325) (1356:1356:1356)) + (PORT datad (1752:1752:1752) (1711:1711:1711)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~8) + (DELAY + (ABSOLUTE + (PORT dataa (198:198:198) (242:242:242)) + (PORT datac (980:980:980) (954:954:954)) + (PORT datad (595:595:595) (599:599:599)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~9) + (DELAY + (ABSOLUTE + (PORT dataa (867:867:867) (894:894:894)) + (PORT datab (1366:1366:1366) (1351:1351:1351)) + (PORT datac (862:862:862) (859:859:859)) + (PORT datad (1518:1518:1518) (1526:1526:1526)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe) + (DELAY + (ABSOLUTE + (PORT dataa (191:191:191) (232:232:232)) + (PORT datab (1542:1542:1542) (1560:1560:1560)) + (PORT datac (1152:1152:1152) (1187:1187:1187)) + (PORT datad (166:166:166) (192:192:192)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (590:590:590) (630:630:630)) + (PORT datab (1350:1350:1350) (1377:1377:1377)) + (PORT datac (2003:2003:2003) (2023:2023:2023)) + (PORT datad (1219:1219:1219) (1244:1244:1244)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (226:226:226) (266:266:266)) + (PORT datab (1471:1471:1471) (1430:1430:1430)) + (PORT datac (498:498:498) (490:490:490)) + (PORT datad (199:199:199) (234:234:234)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla83M1T3_2) + (DELAY + (ABSOLUTE + (PORT dataa (874:874:874) (896:896:896)) + (PORT datab (1778:1778:1778) (1750:1750:1750)) + (PORT datac (1069:1069:1069) (1081:1081:1081)) + (PORT datad (1558:1558:1558) (1574:1574:1574)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1533:1533:1533) (1525:1525:1525)) + (PORT datab (1393:1393:1393) (1406:1406:1406)) + (PORT datac (580:580:580) (601:601:601)) + (PORT datad (877:877:877) (912:912:912)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~38) + (DELAY + (ABSOLUTE + (PORT dataa (909:909:909) (940:940:940)) + (PORT datab (1367:1367:1367) (1362:1362:1362)) + (PORT datac (1270:1270:1270) (1331:1331:1331)) + (PORT datad (834:834:834) (843:843:843)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~28) + (DELAY + (ABSOLUTE + (PORT dataa (874:874:874) (896:896:896)) + (PORT datab (1583:1583:1583) (1607:1607:1607)) + (PORT datac (1069:1069:1069) (1081:1081:1081)) + (PORT datad (2107:2107:2107) (2098:2098:2098)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~6) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (219:219:219)) + (PORT datab (646:646:646) (659:659:659)) + (PORT datac (752:752:752) (785:785:785)) + (PORT datad (189:189:189) (220:220:220)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~37) + (DELAY + (ABSOLUTE + (PORT dataa (2121:2121:2121) (2119:2119:2119)) + (PORT datab (1547:1547:1547) (1527:1527:1527)) + (PORT datac (563:563:563) (582:582:582)) + (PORT datad (829:829:829) (858:858:858)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~39) + (DELAY + (ABSOLUTE + (PORT dataa (1088:1088:1088) (1099:1099:1099)) + (PORT datab (500:500:500) (495:495:495)) + (PORT datac (527:527:527) (529:529:529)) + (PORT datad (1444:1444:1444) (1506:1506:1506)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_daa) + (DELAY + (ABSOLUTE + (PORT dataa (1978:1978:1978) (1996:1996:1996)) + (PORT datab (823:823:823) (845:845:845)) + (PORT datac (1650:1650:1650) (1717:1717:1717)) + (PORT datad (1046:1046:1046) (1042:1042:1042)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~7) + (DELAY + (ABSOLUTE + (PORT dataa (394:394:394) (438:438:438)) + (PORT datab (574:574:574) (590:590:590)) + (PORT datac (1582:1582:1582) (1593:1593:1593)) + (PORT datad (2138:2138:2138) (2143:2143:2143)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~8) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (220:220:220)) + (PORT datab (2161:2161:2161) (2172:2172:2172)) + (PORT datac (819:819:819) (854:854:854)) + (PORT datad (179:179:179) (201:201:201)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~30) + (DELAY + (ABSOLUTE + (PORT dataa (1587:1587:1587) (1640:1640:1640)) + (PORT datab (878:878:878) (914:914:914)) + (PORT datac (1543:1543:1543) (1560:1560:1560)) + (PORT datad (963:963:963) (1010:1010:1010)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~31) + (DELAY + (ABSOLUTE + (PORT datab (573:573:573) (574:574:574)) + (PORT datac (787:787:787) (765:765:765)) + (PORT datad (518:518:518) (483:483:483)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~25) + (DELAY + (ABSOLUTE + (PORT datac (1574:1574:1574) (1588:1588:1588)) + (PORT datad (584:584:584) (611:611:611)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~40) + (DELAY + (ABSOLUTE + (PORT dataa (617:617:617) (632:632:632)) + (PORT datab (1326:1326:1326) (1308:1308:1308)) + (PORT datac (1326:1326:1326) (1351:1351:1351)) + (PORT datad (782:782:782) (782:782:782)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~42) + (DELAY + (ABSOLUTE + (PORT dataa (191:191:191) (233:233:233)) + (PORT datab (588:588:588) (578:578:578)) + (PORT datac (749:749:749) (740:740:740)) + (PORT datad (157:157:157) (178:178:178)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla65npla52M1T4_4) + (DELAY + (ABSOLUTE + (PORT dataa (1341:1341:1341) (1311:1311:1311)) + (PORT datab (1436:1436:1436) (1475:1475:1475)) + (PORT datac (752:752:752) (732:732:732)) + (PORT datad (1133:1133:1133) (1184:1184:1184)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~4) + (DELAY + (ABSOLUTE + (PORT dataa (611:611:611) (644:644:644)) + (PORT datab (657:657:657) (682:682:682)) + (PORT datac (846:846:846) (876:876:876)) + (PORT datad (569:569:569) (579:579:579)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~47) + (DELAY + (ABSOLUTE + (PORT dataa (2141:2141:2141) (2161:2161:2161)) + (PORT datab (862:862:862) (863:863:863)) + (PORT datac (1428:1428:1428) (1474:1474:1474)) + (PORT datad (1768:1768:1768) (1778:1778:1778)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~34) + (DELAY + (ABSOLUTE + (PORT dataa (867:867:867) (896:896:896)) + (PORT datab (640:640:640) (684:684:684)) + (PORT datac (524:524:524) (507:507:507)) + (PORT datad (1517:1517:1517) (1523:1523:1523)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~35) + (DELAY + (ABSOLUTE + (PORT dataa (191:191:191) (233:233:233)) + (PORT datab (318:318:318) (330:330:330)) + (PORT datac (1134:1134:1134) (1150:1150:1150)) + (PORT datad (841:841:841) (859:859:859)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~36) + (DELAY + (ABSOLUTE + (PORT dataa (1020:1020:1020) (1005:1005:1005)) + (PORT datab (798:798:798) (783:783:783)) + (PORT datac (541:541:541) (544:544:544)) + (PORT datad (506:506:506) (502:502:502)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~28) + (DELAY + (ABSOLUTE + (PORT dataa (654:654:654) (681:681:681)) + (PORT datab (888:888:888) (890:890:890)) + (PORT datac (1084:1084:1084) (1106:1106:1106)) + (PORT datad (1033:1033:1033) (1046:1046:1046)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~44) + (DELAY + (ABSOLUTE + (PORT dataa (613:613:613) (641:641:641)) + (PORT datab (1567:1567:1567) (1572:1572:1572)) + (PORT datac (1300:1300:1300) (1412:1412:1412)) + (PORT datad (567:567:567) (591:591:591)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~29) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (220:220:220)) + (PORT datac (798:798:798) (812:812:812)) + (PORT datad (165:165:165) (189:189:189)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~16) + (DELAY + (ABSOLUTE + (PORT datac (1343:1343:1343) (1441:1441:1441)) + (PORT datad (1002:1002:1002) (1011:1011:1011)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~27) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (239:239:239)) + (PORT datab (1473:1473:1473) (1439:1439:1439)) + (PORT datac (174:174:174) (206:206:206)) + (PORT datad (316:316:316) (315:315:315)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~10) + (DELAY + (ABSOLUTE + (PORT dataa (196:196:196) (241:241:241)) + (PORT datab (189:189:189) (225:225:225)) + (PORT datac (981:981:981) (956:956:956)) + (PORT datad (596:596:596) (600:600:600)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~31) + (DELAY + (ABSOLUTE + (PORT dataa (1826:1826:1826) (1875:1875:1875)) + (PORT datab (2074:2074:2074) (2116:2116:2116)) + (PORT datac (359:359:359) (382:382:382)) + (PORT datad (600:600:600) (612:612:612)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~30) + (DELAY + (ABSOLUTE + (PORT dataa (1165:1165:1165) (1204:1204:1204)) + (PORT datab (1219:1219:1219) (1232:1232:1232)) + (PORT datac (811:811:811) (824:824:824)) + (PORT datad (582:582:582) (588:588:588)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~32) + (DELAY + (ABSOLUTE + (PORT dataa (2348:2348:2348) (2371:2371:2371)) + (PORT datab (180:180:180) (213:213:213)) + (PORT datac (2044:2044:2044) (2087:2087:2087)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~33) + (DELAY + (ABSOLUTE + (PORT dataa (957:957:957) (951:951:951)) + (PORT datab (181:181:181) (212:212:212)) + (PORT datac (707:707:707) (708:708:708)) + (PORT datad (743:743:743) (709:709:709)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~21) + (DELAY + (ABSOLUTE + (PORT dataa (912:912:912) (929:929:929)) + (PORT datab (1681:1681:1681) (1680:1680:1680)) + (PORT datac (874:874:874) (894:894:894)) + (PORT datad (1354:1354:1354) (1380:1380:1380)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~45) + (DELAY + (ABSOLUTE + (PORT dataa (2388:2388:2388) (2385:2385:2385)) + (PORT datab (1405:1405:1405) (1473:1473:1473)) + (PORT datac (156:156:156) (187:187:187)) + (PORT datad (861:861:861) (880:880:880)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~22) + (DELAY + (ABSOLUTE + (PORT dataa (323:323:323) (338:338:338)) + (PORT datab (1682:1682:1682) (1684:1684:1684)) + (PORT datac (880:880:880) (894:894:894)) + (PORT datad (876:876:876) (898:898:898)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~23) + (DELAY + (ABSOLUTE + (PORT dataa (911:911:911) (927:927:927)) + (PORT datab (182:182:182) (215:215:215)) + (PORT datac (1634:1634:1634) (1657:1657:1657)) + (PORT datad (1324:1324:1324) (1320:1320:1320)) + (IOPATH dataa combout (307:307:307) (289:289:289)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~24) + (DELAY + (ABSOLUTE + (PORT dataa (1045:1045:1045) (1066:1066:1066)) + (PORT datab (1684:1684:1684) (1683:1683:1683)) + (PORT datac (1296:1296:1296) (1274:1274:1274)) + (PORT datad (158:158:158) (179:179:179)) + (IOPATH dataa combout (307:307:307) (289:289:289)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~25) + (DELAY + (ABSOLUTE + (PORT dataa (1350:1350:1350) (1358:1358:1358)) + (PORT datab (1605:1605:1605) (1588:1588:1588)) + (PORT datac (1017:1017:1017) (1034:1034:1034)) + (PORT datad (159:159:159) (181:181:181)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~26) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (236:236:236)) + (PORT datab (867:867:867) (886:886:886)) + (PORT datac (752:752:752) (731:731:731)) + (PORT datad (177:177:177) (197:197:197)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~43) + (DELAY + (ABSOLUTE + (PORT dataa (532:532:532) (516:516:516)) + (PORT datab (543:543:543) (527:527:527)) + (PORT datac (155:155:155) (186:186:186)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_low) + (DELAY + (ABSOLUTE + (PORT dataa (915:915:915) (945:945:945)) + (PORT datab (1795:1795:1795) (1799:1799:1799)) + (PORT datac (2007:2007:2007) (2044:2044:2044)) + (PORT datad (1331:1331:1331) (1372:1372:1372)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1180:1180:1180) (1207:1207:1207)) + (PORT datab (850:850:850) (893:893:893)) + (PORT datac (1045:1045:1045) (1048:1048:1048)) + (PORT datad (777:777:777) (791:791:791)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero) + (DELAY + (ABSOLUTE + (PORT dataa (565:565:565) (563:563:563)) + (PORT datab (1706:1706:1706) (1703:1703:1703)) + (PORT datac (1496:1496:1496) (1551:1551:1551)) + (PORT datad (489:489:489) (473:473:473)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~13) + (DELAY + (ABSOLUTE + (PORT dataa (611:611:611) (636:636:636)) + (PORT datab (557:557:557) (559:559:559)) + (PORT datac (1817:1817:1817) (1823:1823:1823)) + (PORT datad (559:559:559) (558:558:558)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1480:1480:1480) (1485:1485:1485)) + (PORT datab (530:530:530) (535:535:535)) + (PORT datac (1746:1746:1746) (1766:1766:1766)) + (PORT datad (1665:1665:1665) (1717:1717:1717)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1233:1233:1233) (1261:1261:1261)) + (PORT datab (182:182:182) (213:213:213)) + (PORT datac (1871:1871:1871) (1945:1945:1945)) + (PORT datad (935:935:935) (942:942:942)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~3) + (DELAY + (ABSOLUTE + (PORT dataa (909:909:909) (925:925:925)) + (PORT datab (1607:1607:1607) (1621:1621:1621)) + (PORT datac (1631:1631:1631) (1654:1654:1654)) + (PORT datad (863:863:863) (881:881:881)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~4) + (DELAY + (ABSOLUTE + (PORT dataa (907:907:907) (923:923:923)) + (PORT datab (916:916:916) (934:934:934)) + (PORT datac (882:882:882) (893:893:893)) + (PORT datad (158:158:158) (179:179:179)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4) + (DELAY + (ABSOLUTE + (PORT dataa (1814:1814:1814) (1824:1824:1824)) + (PORT datab (1127:1127:1127) (1131:1131:1131)) + (PORT datad (1432:1432:1432) (1498:1498:1498)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1660:1660:1660) (1684:1684:1684)) + (PORT datab (1051:1051:1051) (1052:1052:1052)) + (PORT datac (842:842:842) (859:859:859)) + (PORT datad (1352:1352:1352) (1377:1377:1377)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~10) + (DELAY + (ABSOLUTE + (PORT dataa (321:321:321) (335:335:335)) + (PORT datab (201:201:201) (236:236:236)) + (PORT datac (166:166:166) (202:202:202)) + (PORT datad (591:591:591) (592:592:592)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~11) + (DELAY + (ABSOLUTE + (PORT dataa (643:643:643) (671:671:671)) + (PORT datab (1671:1671:1671) (1684:1684:1684)) + (PORT datac (572:572:572) (593:593:593)) + (PORT datad (758:758:758) (735:735:735)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1024:1024:1024) (1050:1050:1050)) + (PORT datab (1642:1642:1642) (1657:1657:1657)) + (PORT datac (1465:1465:1465) (1567:1567:1567)) + (PORT datad (541:541:541) (543:543:543)) + (IOPATH dataa combout (307:307:307) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~15) + (DELAY + (ABSOLUTE + (PORT dataa (523:523:523) (519:519:519)) + (PORT datab (183:183:183) (216:216:216)) + (PORT datac (479:479:479) (468:468:468)) + (PORT datad (744:744:744) (710:710:710)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[3\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (870:870:870) (897:897:897)) + (PORT datab (798:798:798) (786:786:786)) + (PORT datac (809:809:809) (802:802:802)) + (PORT datad (576:576:576) (578:578:578)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[3\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (651:651:651) (677:677:677)) + (PORT datab (822:822:822) (819:819:819)) + (PORT datac (805:805:805) (820:820:820)) + (PORT datad (157:157:157) (177:177:177)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|ena) + (DELAY + (ABSOLUTE + (PORT dataa (868:868:868) (895:895:895)) + (PORT datac (810:810:810) (831:831:831)) + (PORT datad (781:781:781) (781:781:781)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[3\]) + (INSTANCE z80_\|alu_\|op1_low\[3\]) (DELAY (ABSOLUTE - (PORT clk (1355:1355:1355) (1376:1376:1376)) + (PORT clk (1369:1369:1369) (1376:1376:1376)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (1347:1347:1347) (1329:1329:1329)) + (PORT ena (720:720:720) (722:722:722)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -16241,32 +8324,2585 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~31) + (INSTANCE z80_\|alu_\|db_low\[3\]\~15) (DELAY (ABSOLUTE - (PORT dataa (1646:1646:1646) (1716:1716:1716)) - (PORT datab (893:893:893) (908:908:908)) - (PORT datac (1355:1355:1355) (1341:1341:1341)) - (PORT datad (1815:1815:1815) (1812:1812:1812)) + (PORT dataa (606:606:606) (610:610:610)) + (PORT datab (652:652:652) (649:649:649)) + (PORT datac (625:625:625) (657:657:657)) + (PORT datad (396:396:396) (440:440:440)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[3\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (218:218:218)) + (PORT datab (241:241:241) (297:297:297)) + (PORT datac (1015:1015:1015) (1022:1022:1022)) + (PORT datad (321:321:321) (324:324:324)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~33) + (DELAY + (ABSOLUTE + (PORT dataa (835:835:835) (835:835:835)) + (PORT datab (1581:1581:1581) (1571:1571:1571)) + (PORT datac (795:795:795) (797:797:797)) + (PORT datad (826:826:826) (904:904:904)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~34) + (DELAY + (ABSOLUTE + (PORT dataa (564:564:564) (579:579:579)) + (PORT datab (1028:1028:1028) (1071:1071:1071)) + (PORT datac (571:571:571) (577:577:577)) + (PORT datad (828:828:828) (832:832:832)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~48) + (DELAY + (ABSOLUTE + (PORT dataa (1476:1476:1476) (1538:1538:1538)) + (PORT datab (1458:1458:1458) (1502:1502:1502)) + (PORT datac (1932:1932:1932) (1971:1971:1971)) + (PORT datad (1031:1031:1031) (1003:1003:1003)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~35) + (DELAY + (ABSOLUTE + (PORT dataa (797:797:797) (822:822:822)) + (PORT datab (1473:1473:1473) (1551:1551:1551)) + (PORT datac (768:768:768) (774:774:774)) + (PORT datad (1094:1094:1094) (1089:1089:1089)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~36) + (DELAY + (ABSOLUTE + (PORT dataa (580:580:580) (582:582:582)) + (PORT datab (781:781:781) (767:767:767)) + (PORT datac (570:570:570) (589:589:589)) + (PORT datad (159:159:159) (178:178:178)) (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~37) + (DELAY + (ABSOLUTE + (PORT dataa (204:204:204) (252:252:252)) + (PORT datab (603:603:603) (607:607:607)) + (PORT datac (545:545:545) (541:541:541)) + (PORT datad (552:552:552) (532:532:532)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla26M1T4_3) + (DELAY + (ABSOLUTE + (PORT dataa (1478:1478:1478) (1541:1541:1541)) + (PORT datab (1537:1537:1537) (1510:1510:1510)) + (PORT datad (1769:1769:1769) (1782:1782:1782)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~38) + (DELAY + (ABSOLUTE + (PORT dataa (938:938:938) (972:972:972)) + (PORT datab (1901:1901:1901) (1922:1922:1922)) + (PORT datac (990:990:990) (1021:1021:1021)) + (PORT datad (1025:1025:1025) (1038:1038:1038)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~39) + (DELAY + (ABSOLUTE + (PORT dataa (1296:1296:1296) (1315:1315:1315)) + (PORT datab (1875:1875:1875) (1847:1847:1847)) + (PORT datac (1490:1490:1490) (1506:1506:1506)) + (PORT datad (1143:1143:1143) (1177:1177:1177)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~40) + (DELAY + (ABSOLUTE + (PORT dataa (382:382:382) (394:394:394)) + (PORT datab (758:758:758) (756:756:756)) + (PORT datac (180:180:180) (215:215:215)) + (PORT datad (770:770:770) (802:802:802)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~41) + (DELAY + (ABSOLUTE + (PORT dataa (1762:1762:1762) (1798:1798:1798)) + (PORT datab (789:789:789) (798:798:798)) + (PORT datac (2236:2236:2236) (2237:2237:2237)) + (PORT datad (819:819:819) (839:839:839)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (308:308:308) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low) + (DELAY + (ABSOLUTE + (PORT dataa (907:907:907) (958:958:958)) + (PORT datab (212:212:212) (253:253:253)) + (PORT datac (1546:1546:1546) (1556:1556:1556)) + (PORT datad (765:765:765) (758:758:758)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|result_lo\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1344:1344:1344) (1363:1363:1363)) + (PORT asdata (869:869:869) (876:876:876)) + (PORT ena (1815:1815:1815) (1774:1774:1774)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~5) + (DELAY + (ABSOLUTE + (PORT dataa (820:820:820) (853:853:853)) + (PORT datab (217:217:217) (259:259:259)) + (PORT datac (1094:1094:1094) (1096:1096:1096)) + (PORT datad (948:948:948) (1002:1002:1002)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~6) + (DELAY + (ABSOLUTE + (PORT dataa (803:803:803) (815:815:815)) + (PORT datab (602:602:602) (607:607:607)) + (PORT datac (752:752:752) (757:757:757)) + (PORT datad (569:569:569) (585:585:585)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1131:1131:1131) (1135:1135:1135)) + (PORT datab (593:593:593) (637:637:637)) + (PORT datac (1013:1013:1013) (1008:1008:1008)) + (PORT datad (578:578:578) (573:573:573)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1241:1241:1241) (1242:1242:1242)) + (PORT datab (1107:1107:1107) (1111:1111:1111)) + (PORT datac (1513:1513:1513) (1539:1539:1539)) + (PORT datad (1751:1751:1751) (1814:1814:1814)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~10) + (DELAY + (ABSOLUTE + (PORT dataa (188:188:188) (225:225:225)) + (PORT datab (181:181:181) (213:213:213)) + (PORT datac (964:964:964) (1009:1009:1009)) + (PORT datad (177:177:177) (199:199:199)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~2) + (DELAY + (ABSOLUTE + (PORT dataa (781:781:781) (776:776:776)) + (PORT datab (822:822:822) (824:824:824)) + (PORT datac (647:647:647) (693:693:693)) + (PORT datad (828:828:828) (901:901:901)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel_pla66npla53M1T1_15) + (DELAY + (ABSOLUTE + (PORT dataa (1766:1766:1766) (1741:1741:1741)) + (PORT datab (1002:1002:1002) (1033:1033:1033)) + (PORT datac (1329:1329:1329) (1387:1387:1387)) + (PORT datad (1361:1361:1361) (1387:1387:1387)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (643:643:643) (668:668:668)) + (PORT datab (821:821:821) (832:832:832)) + (PORT datac (1165:1165:1165) (1163:1163:1163)) + (PORT datad (1287:1287:1287) (1346:1346:1346)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~8) + (DELAY + (ABSOLUTE + (PORT dataa (898:898:898) (904:904:904)) + (PORT datab (854:854:854) (858:858:858)) + (PORT datac (827:827:827) (840:840:840)) + (PORT datad (1007:1007:1007) (993:993:993)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1780:1780:1780) (1807:1807:1807)) + (PORT datab (1246:1246:1246) (1203:1203:1203)) + (PORT datac (803:803:803) (836:836:836)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~7) + (DELAY + (ABSOLUTE + (PORT dataa (762:762:762) (757:757:757)) + (PORT datab (545:545:545) (538:538:538)) + (PORT datac (1087:1087:1087) (1107:1107:1107)) + (PORT datad (558:558:558) (574:574:574)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1611:1611:1611) (1620:1620:1620)) + (PORT datab (387:387:387) (387:387:387)) + (PORT datac (552:552:552) (553:553:553)) + (PORT datad (1063:1063:1063) (1074:1074:1074)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (526:526:526) (532:532:532)) + (PORT datab (1080:1080:1080) (1088:1088:1088)) + (PORT datac (1458:1458:1458) (1468:1468:1468)) + (PORT datad (540:540:540) (550:550:550)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~8) + (DELAY + (ABSOLUTE + (PORT dataa (866:866:866) (877:877:877)) + (PORT datab (976:976:976) (1019:1019:1019)) + (PORT datac (156:156:156) (186:186:186)) + (PORT datad (765:765:765) (764:764:764)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~16) + (DELAY + (ABSOLUTE + (PORT dataa (610:610:610) (643:643:643)) + (PORT datab (199:199:199) (233:233:233)) + (PORT datac (533:533:533) (527:527:527)) + (PORT datad (789:789:789) (799:799:799)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1023:1023:1023) (1014:1014:1014)) + (PORT datab (538:538:538) (522:522:522)) + (PORT datac (1407:1407:1407) (1358:1358:1358)) + (PORT datad (773:773:773) (770:770:770)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~48) + (DELAY + (ABSOLUTE + (PORT dataa (1098:1098:1098) (1113:1113:1113)) + (PORT datab (1705:1705:1705) (1754:1754:1754)) + (PORT datac (526:526:526) (512:512:512)) + (PORT datad (1583:1583:1583) (1620:1620:1620)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1318:1318:1318) (1336:1336:1336)) + (PORT datab (898:898:898) (934:934:934)) + (PORT datac (1018:1018:1018) (1009:1009:1009)) + (PORT datad (881:881:881) (951:951:951)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~5) + (DELAY + (ABSOLUTE + (PORT dataa (589:589:589) (616:616:616)) + (PORT datab (639:639:639) (662:662:662)) + (PORT datac (584:584:584) (586:586:586)) + (PORT datad (593:593:593) (623:623:623)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~2) + (DELAY + (ABSOLUTE + (PORT dataa (2420:2420:2420) (2427:2427:2427)) + (PORT datab (845:845:845) (830:830:830)) + (PORT datac (1503:1503:1503) (1544:1544:1544)) + (PORT datad (1076:1076:1076) (1086:1086:1086)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~0) + (DELAY + (ABSOLUTE + (PORT dataa (890:890:890) (912:912:912)) + (PORT datab (1532:1532:1532) (1574:1574:1574)) + (PORT datac (867:867:867) (913:913:913)) + (PORT datad (1142:1142:1142) (1166:1166:1166)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~3) + (DELAY + (ABSOLUTE + (PORT dataa (986:986:986) (981:981:981)) + (PORT datab (617:617:617) (642:642:642)) + (PORT datac (176:176:176) (207:207:207)) + (PORT datad (164:164:164) (188:188:188)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (1225:1225:1225) (1299:1299:1299)) + (PORT datab (339:339:339) (351:351:351)) + (PORT datac (1140:1140:1140) (1134:1134:1134)) + (PORT datad (1225:1225:1225) (1262:1262:1262)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~33) + (DELAY + (ABSOLUTE + (PORT dataa (1061:1061:1061) (1052:1052:1052)) + (PORT datab (1601:1601:1601) (1608:1608:1608)) + (PORT datac (1244:1244:1244) (1273:1273:1273)) + (PORT datad (1243:1243:1243) (1278:1278:1278)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (1439:1439:1439) (1510:1510:1510)) + (PORT datab (1121:1121:1121) (1128:1128:1128)) + (PORT datac (1454:1454:1454) (1489:1489:1489)) + (PORT datad (165:165:165) (190:190:190)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~6) + (DELAY + (ABSOLUTE + (PORT dataa (883:883:883) (922:922:922)) + (PORT datab (846:846:846) (885:885:885)) + (PORT datac (983:983:983) (956:956:956)) + (PORT datad (172:172:172) (201:201:201)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~6) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (219:219:219)) + (PORT datab (841:841:841) (821:821:821)) + (PORT datac (1225:1225:1225) (1196:1196:1196)) + (PORT datad (293:293:293) (293:293:293)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~7) + (DELAY + (ABSOLUTE + (PORT dataa (633:633:633) (656:656:656)) + (PORT datab (614:614:614) (650:650:650)) + (PORT datac (155:155:155) (186:186:186)) + (PORT datad (178:178:178) (200:200:200)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~2) + (DELAY + (ABSOLUTE + (PORT dataa (583:583:583) (585:585:585)) + (PORT datab (1584:1584:1584) (1617:1617:1617)) + (PORT datac (870:870:870) (914:914:914)) + (PORT datad (2311:2311:2311) (2391:2391:2391)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1122:1122:1122) (1130:1130:1130)) + (PORT datab (1243:1243:1243) (1290:1290:1290)) + (PORT datac (1408:1408:1408) (1434:1434:1434)) + (PORT datad (1821:1821:1821) (1866:1866:1866)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1564:1564:1564) (1597:1597:1597)) + (PORT datab (678:678:678) (705:705:705)) + (PORT datac (528:528:528) (525:525:525)) + (PORT datad (805:805:805) (804:804:804)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla27npla34M1T1_3) + (DELAY + (ABSOLUTE + (PORT dataa (699:699:699) (747:747:747)) + (PORT datab (1672:1672:1672) (1700:1700:1700)) + (PORT datac (2041:2041:2041) (2052:2052:2052)) + (PORT datad (639:639:639) (701:701:701)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~8) + (DELAY + (ABSOLUTE + (PORT dataa (815:815:815) (825:825:825)) + (PORT datab (180:180:180) (212:212:212)) + (PORT datac (1021:1021:1021) (1007:1007:1007)) + (PORT datad (164:164:164) (187:187:187)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~7) + (DELAY + (ABSOLUTE + (PORT dataa (615:615:615) (630:630:630)) + (PORT datab (556:556:556) (544:544:544)) + (PORT datac (1328:1328:1328) (1353:1353:1353)) + (PORT datad (780:780:780) (780:780:780)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~5) + (DELAY + (ABSOLUTE + (PORT dataa (904:904:904) (926:926:926)) + (PORT datab (835:835:835) (873:873:873)) + (PORT datac (859:859:859) (862:862:862)) + (PORT datad (1033:1033:1033) (1046:1046:1046)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~19) + (DELAY + (ABSOLUTE + (PORT dataa (825:825:825) (822:822:822)) + (PORT datab (858:858:858) (892:892:892)) + (PORT datac (872:872:872) (907:907:907)) + (PORT datad (825:825:825) (827:827:827)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~18) + (DELAY + (ABSOLUTE + (PORT dataa (915:915:915) (929:929:929)) + (PORT datab (632:632:632) (669:669:669)) + (PORT datac (1024:1024:1024) (1017:1017:1017)) + (PORT datad (611:611:611) (636:636:636)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~2) + (DELAY + (ABSOLUTE + (PORT dataa (365:365:365) (379:379:379)) + (PORT datab (198:198:198) (231:231:231)) + (PORT datac (193:193:193) (224:224:224)) + (PORT datad (1568:1568:1568) (1541:1541:1541)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal24\~1) + (DELAY + (ABSOLUTE + (PORT dataa (2337:2337:2337) (2425:2425:2425)) + (PORT datab (897:897:897) (936:936:936)) + (PORT datac (1553:1553:1553) (1586:1586:1586)) + (PORT datad (843:843:843) (866:866:866)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~3) + (DELAY + (ABSOLUTE + (PORT dataa (839:839:839) (870:870:870)) + (PORT datab (1327:1327:1327) (1321:1321:1321)) + (PORT datac (156:156:156) (187:187:187)) + (PORT datad (578:578:578) (600:600:600)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1101:1101:1101) (1132:1132:1132)) + (PORT datab (1247:1247:1247) (1297:1297:1297)) + (PORT datac (1161:1161:1161) (1209:1209:1209)) + (PORT datad (907:907:907) (939:939:939)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~20) + (DELAY + (ABSOLUTE + (PORT dataa (576:576:576) (559:559:559)) + (PORT datab (552:552:552) (555:555:555)) + (PORT datac (901:901:901) (940:940:940)) + (PORT datad (866:866:866) (885:885:885)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~5) + (DELAY + (ABSOLUTE + (PORT dataa (670:670:670) (674:674:674)) + (PORT datab (797:797:797) (818:818:818)) + (PORT datac (558:558:558) (553:553:553)) + (PORT datad (1028:1028:1028) (1031:1031:1031)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~22) + (DELAY + (ABSOLUTE + (PORT dataa (875:875:875) (890:890:890)) + (PORT datab (1097:1097:1097) (1095:1095:1095)) + (PORT datac (768:768:768) (755:755:755)) + (PORT datad (542:542:542) (556:556:556)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla42M3T3_6) + (DELAY + (ABSOLUTE + (PORT dataa (1085:1085:1085) (1114:1114:1114)) + (PORT datab (1002:1002:1002) (1031:1031:1031)) + (PORT datac (567:567:567) (588:588:588)) + (PORT datad (1537:1537:1537) (1625:1625:1625)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~6) + (DELAY + (ABSOLUTE + (PORT dataa (805:805:805) (820:820:820)) + (PORT datab (861:861:861) (855:855:855)) + (PORT datac (1937:1937:1937) (1968:1968:1968)) + (PORT datad (816:816:816) (832:832:832)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1774:1774:1774) (1789:1789:1789)) + (PORT datad (1115:1115:1115) (1136:1136:1136)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~30) + (DELAY + (ABSOLUTE + (PORT dataa (586:586:586) (581:581:581)) + (PORT datab (660:660:660) (674:674:674)) + (PORT datac (957:957:957) (1009:1009:1009)) + (PORT datad (774:774:774) (786:786:786)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~23) + (DELAY + (ABSOLUTE + (PORT dataa (595:595:595) (582:582:582)) + (PORT datab (1183:1183:1183) (1219:1219:1219)) + (PORT datac (956:956:956) (1008:1008:1008)) + (PORT datad (774:774:774) (785:785:785)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1281:1281:1281) (1298:1298:1298)) + (PORT datab (200:200:200) (234:234:234)) + (PORT datac (544:544:544) (575:575:575)) + (PORT datad (812:812:812) (816:816:816)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~3) + (DELAY + (ABSOLUTE + (PORT dataa (2104:2104:2104) (2160:2160:2160)) + (PORT datab (1054:1054:1054) (1046:1046:1046)) + (PORT datac (878:878:878) (896:896:896)) + (PORT datad (609:609:609) (633:633:633)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~10) + (DELAY + (ABSOLUTE + (PORT dataa (786:786:786) (790:790:790)) + (PORT datab (736:736:736) (716:716:716)) + (PORT datad (1061:1061:1061) (1054:1054:1054)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~18) + (DELAY + (ABSOLUTE + (PORT dataa (821:821:821) (808:808:808)) + (PORT datab (1142:1142:1142) (1152:1152:1152)) + (PORT datac (1122:1122:1122) (1154:1154:1154)) + (PORT datad (1041:1041:1041) (1012:1012:1012)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_pc\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1093:1093:1093) (1076:1076:1076)) + (PORT datab (824:824:824) (856:856:856)) + (PORT datac (1720:1720:1720) (1743:1743:1743)) + (PORT datad (626:626:626) (641:641:641)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_pc\~1) + (DELAY + (ABSOLUTE + (PORT dataa (838:838:838) (869:869:869)) + (PORT datab (218:218:218) (260:260:260)) + (PORT datac (194:194:194) (225:225:225)) + (PORT datad (855:855:855) (847:847:847)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_pc\~2) + (DELAY + (ABSOLUTE + (PORT dataa (619:619:619) (629:629:629)) + (PORT datab (219:219:219) (263:263:263)) + (PORT datac (156:156:156) (187:187:187)) + (PORT datad (1568:1568:1568) (1540:1540:1540)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~19) + (DELAY + (ABSOLUTE + (PORT dataa (854:854:854) (863:863:863)) + (PORT datab (634:634:634) (635:635:635)) + (PORT datac (1120:1120:1120) (1154:1154:1154)) + (PORT datad (619:619:619) (648:648:648)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~20) + (DELAY + (ABSOLUTE + (PORT dataa (566:566:566) (552:552:552)) + (PORT datab (200:200:200) (234:234:234)) + (PORT datac (154:154:154) (184:184:184)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~21) + (DELAY + (ABSOLUTE + (PORT dataa (846:846:846) (883:883:883)) + (PORT datab (776:776:776) (842:842:842)) + (PORT datac (180:180:180) (215:215:215)) + (PORT datad (581:581:581) (605:605:605)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~9) + (DELAY + (ABSOLUTE + (PORT dataa (605:605:605) (615:615:615)) + (PORT datab (592:592:592) (608:608:608)) + (PORT datac (1099:1099:1099) (1122:1122:1122)) + (PORT datad (566:566:566) (568:568:568)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1598:1598:1598) (1613:1613:1613)) + (PORT datab (273:273:273) (363:363:363)) + (PORT datac (784:784:784) (781:781:781)) + (PORT datad (544:544:544) (534:534:534)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_1d\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1858:1858:1858) (1994:1994:1994)) + (PORT datab (1129:1129:1129) (1157:1157:1157)) + (PORT datac (623:623:623) (637:637:637)) + (PORT datad (1175:1175:1175) (1207:1207:1207)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~10) + (DELAY + (ABSOLUTE + (PORT dataa (601:601:601) (632:632:632)) + (PORT datab (1052:1052:1052) (1077:1077:1077)) + (PORT datac (835:835:835) (838:838:838)) + (PORT datad (1072:1072:1072) (1092:1092:1092)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~11) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (221:221:221)) + (PORT datab (1126:1126:1126) (1113:1113:1113)) + (PORT datac (660:660:660) (717:717:717)) + (PORT datad (157:157:157) (177:177:177)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1096:1096:1096) (1093:1093:1093)) + (PORT datab (884:884:884) (899:899:899)) + (PORT datac (547:547:547) (548:548:548)) + (PORT datad (794:794:794) (798:798:798)) + (IOPATH dataa combout (272:272:272) (269:269:269)) (IOPATH datab combout (273:273:273) (275:275:275)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~13) + (DELAY + (ABSOLUTE + (PORT dataa (827:827:827) (827:827:827)) + (PORT datab (183:183:183) (217:217:217)) + (PORT datac (772:772:772) (747:747:747)) + (PORT datad (776:776:776) (763:763:763)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[7\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (576:576:576) (601:601:601)) + (PORT datac (528:528:528) (535:535:535)) + (PORT datad (626:626:626) (650:650:650)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|SYNTHESIZED_WIRE_2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (581:581:581) (620:620:620)) + (PORT datab (1029:1029:1029) (1038:1038:1038)) + (PORT datac (298:298:298) (306:306:306)) + (PORT datad (1836:1836:1836) (1911:1911:1911)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla89M1T2_3) + (DELAY + (ABSOLUTE + (PORT dataa (1675:1675:1675) (1745:1745:1745)) + (PORT datab (870:870:870) (914:914:914)) + (PORT datac (833:833:833) (858:858:858)) + (PORT datad (1047:1047:1047) (1040:1040:1040)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~32) + (DELAY + (ABSOLUTE + (PORT dataa (625:625:625) (645:645:645)) + (PORT datab (872:872:872) (877:877:877)) + (PORT datac (1130:1130:1130) (1159:1159:1159)) + (PORT datad (1909:1909:1909) (1944:1944:1944)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~2) + (DELAY + (ABSOLUTE + (PORT dataa (865:865:865) (886:886:886)) + (PORT datab (1468:1468:1468) (1534:1534:1534)) + (PORT datac (1797:1797:1797) (1858:1858:1858)) + (PORT datad (586:586:586) (606:606:606)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~22) + (DELAY + (ABSOLUTE + (PORT dataa (1815:1815:1815) (1821:1821:1821)) + (PORT datab (895:895:895) (917:917:917)) + (PORT datac (1935:1935:1935) (1972:1972:1972)) + (PORT datad (1051:1051:1051) (1048:1048:1048)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~3) + (DELAY + (ABSOLUTE + (PORT dataa (613:613:613) (628:628:628)) + (PORT datab (183:183:183) (217:217:217)) + (PORT datad (161:161:161) (182:182:182)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~4) + (DELAY + (ABSOLUTE + (PORT dataa (565:565:565) (568:568:568)) + (PORT datab (593:593:593) (597:597:597)) + (PORT datac (787:787:787) (766:766:766)) + (PORT datad (569:569:569) (598:598:598)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~5) + (DELAY + (ABSOLUTE + (PORT dataa (556:556:556) (555:555:555)) + (PORT datab (1061:1061:1061) (1056:1056:1056)) + (PORT datac (193:193:193) (234:234:234)) + (PORT datad (570:570:570) (563:563:563)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1154:1154:1154) (1219:1219:1219)) + (PORT datab (1304:1304:1304) (1337:1337:1337)) + (PORT datac (595:595:595) (618:618:618)) + (PORT datad (1633:1633:1633) (1688:1688:1688)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~13) + (DELAY + (ABSOLUTE + (PORT dataa (602:602:602) (596:596:596)) + (PORT datab (180:180:180) (212:212:212)) + (PORT datac (194:194:194) (235:235:235)) + (PORT datad (178:178:178) (200:200:200)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~15) + (DELAY + (ABSOLUTE + (PORT dataa (935:935:935) (1009:1009:1009)) + (PORT datab (206:206:206) (244:244:244)) + (PORT datac (1031:1031:1031) (1024:1024:1024)) + (PORT datad (556:556:556) (554:554:554)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~6) + (DELAY + (ABSOLUTE + (PORT datab (527:527:527) (524:524:524)) + (PORT datac (297:297:297) (317:317:317)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~7) + (DELAY + (ABSOLUTE + (PORT dataa (351:351:351) (359:359:359)) + (PORT datab (189:189:189) (227:227:227)) + (PORT datac (156:156:156) (187:187:187)) + (PORT datad (534:534:534) (523:523:523)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_nop3pla68M1T3_2) + (DELAY + (ABSOLUTE + (PORT dataa (1561:1561:1561) (1555:1555:1555)) + (PORT datab (1318:1318:1318) (1289:1289:1289)) + (PORT datac (1792:1792:1792) (1793:1793:1793)) + (PORT datad (852:852:852) (891:891:891)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2169:2169:2169) (2179:2179:2179)) + (PORT datab (183:183:183) (217:217:217)) + (PORT datac (822:822:822) (834:834:834)) + (PORT datad (1256:1256:1256) (1224:1224:1224)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~17) + (DELAY + (ABSOLUTE + (PORT dataa (911:911:911) (945:945:945)) + (PORT datab (208:208:208) (245:245:245)) + (PORT datac (1103:1103:1103) (1101:1101:1101)) + (PORT datad (791:791:791) (796:796:796)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1785:1785:1785) (1769:1769:1769)) + (PORT datab (182:182:182) (215:215:215)) + (PORT datac (176:176:176) (207:207:207)) + (PORT datad (1048:1048:1048) (1053:1053:1053)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~2) + (DELAY + (ABSOLUTE + (PORT dataa (785:785:785) (796:796:796)) + (PORT datab (599:599:599) (609:609:609)) + (PORT datac (765:765:765) (771:771:771)) + (PORT datad (158:158:158) (179:179:179)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (2169:2169:2169) (2180:2180:2180)) + (PORT datab (1604:1604:1604) (1614:1614:1614)) + (PORT datac (823:823:823) (831:831:831)) + (PORT datad (1255:1255:1255) (1221:1221:1221)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1079:1079:1079) (1084:1084:1084)) + (PORT datab (1017:1017:1017) (1053:1053:1053)) + (PORT datac (1872:1872:1872) (1899:1899:1899)) + (PORT datad (1604:1604:1604) (1611:1611:1611)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal73\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1848:1848:1848) (1982:1982:1982)) + (PORT datab (1119:1119:1119) (1145:1145:1145)) + (PORT datac (894:894:894) (899:899:899)) + (PORT datad (1182:1182:1182) (1215:1215:1215)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal72\~2) + (DELAY + (ABSOLUTE + (PORT dataa (932:932:932) (1008:1008:1008)) + (PORT datab (204:204:204) (240:240:240)) + (PORT datac (1047:1047:1047) (1054:1054:1054)) + (PORT datad (1380:1380:1380) (1428:1428:1428)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~1) + (DELAY + (ABSOLUTE + (PORT dataa (601:601:601) (616:616:616)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (1028:1028:1028) (1009:1009:1009)) + (PORT datad (559:559:559) (559:559:559)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (327:327:327) (339:339:339)) + (PORT datab (527:527:527) (524:524:524)) + (PORT datac (297:297:297) (316:316:316)) + (PORT datad (744:744:744) (767:767:767)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (631:631:631) (676:676:676)) + (PORT datab (1400:1400:1400) (1482:1482:1482)) + (PORT datad (896:896:896) (934:934:934)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (219:219:219)) + (PORT datab (857:857:857) (885:885:885)) + (PORT datac (2071:2071:2071) (2067:2067:2067)) + (PORT datad (820:820:820) (821:821:821)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (545:545:545) (550:550:550)) + (PORT datab (181:181:181) (213:213:213)) + (PORT datac (1349:1349:1349) (1386:1386:1386)) + (PORT datad (538:538:538) (541:541:541)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~8) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (220:220:220)) + (PORT datab (535:535:535) (533:533:533)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~14) + (DELAY + (ABSOLUTE + (PORT datab (1026:1026:1026) (1072:1072:1072)) + (PORT datad (1250:1250:1250) (1267:1267:1267)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~10) + (DELAY + (ABSOLUTE + (PORT dataa (184:184:184) (221:221:221)) + (PORT datab (357:357:357) (371:371:371)) + (PORT datac (1608:1608:1608) (1641:1641:1641)) + (PORT datad (164:164:164) (189:189:189)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal45\~0) + (DELAY + (ABSOLUTE + (PORT dataa (865:865:865) (874:874:874)) + (PORT datab (1082:1082:1082) (1116:1116:1116)) + (PORT datac (1127:1127:1127) (1168:1168:1168)) + (PORT datad (1495:1495:1495) (1557:1557:1557)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1142:1142:1142) (1150:1150:1150)) + (PORT datab (816:816:816) (801:801:801)) + (PORT datac (1070:1070:1070) (1060:1060:1060)) + (PORT datad (1553:1553:1553) (1508:1508:1508)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1162:1162:1162) (1187:1187:1187)) + (PORT datab (891:891:891) (908:908:908)) + (PORT datac (1666:1666:1666) (1683:1683:1683)) + (PORT datad (161:161:161) (182:182:182)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1440:1440:1440) (1459:1459:1459)) + (PORT datab (1156:1156:1156) (1198:1198:1198)) + (PORT datac (157:157:157) (188:188:188)) + (PORT datad (922:922:922) (949:949:949)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~8) + (DELAY + (ABSOLUTE + (PORT dataa (819:819:819) (837:837:837)) + (PORT datab (554:554:554) (541:541:541)) + (PORT datac (331:331:331) (341:341:341)) + (PORT datad (971:971:971) (971:971:971)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~9) + (DELAY + (ABSOLUTE + (PORT dataa (602:602:602) (613:613:613)) + (PORT datac (567:567:567) (578:578:578)) + (PORT datad (561:561:561) (559:559:559)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~10) + (DELAY + (ABSOLUTE + (PORT dataa (568:568:568) (563:563:563)) + (PORT datab (598:598:598) (615:615:615)) + (PORT datac (316:316:316) (322:322:322)) + (PORT datad (763:763:763) (739:739:739)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S) + (DELAY + (ABSOLUTE + (PORT dataa (809:809:809) (799:799:799)) + (PORT datab (187:187:187) (224:224:224)) + (PORT datac (357:357:357) (370:370:370)) + (PORT datad (563:563:563) (556:556:556)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[3\]) + (DELAY + (ABSOLUTE + (PORT dataa (652:652:652) (682:682:682)) + (PORT datac (806:806:806) (825:825:825)) + (PORT datad (765:765:765) (772:772:772)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|ena\~0) + (DELAY + (ABSOLUTE + (PORT dataa (870:870:870) (897:897:897)) + (PORT datac (805:805:805) (822:822:822)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_high\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1369:1369:1369) (1376:1376:1376)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (745:745:745) (751:751:751)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op1\[3\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1080:1080:1080) (1124:1124:1124)) + (PORT datab (635:635:635) (651:651:651)) + (PORT datac (376:376:376) (426:426:426)) + (PORT datad (397:397:397) (443:443:443)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|SYNTHESIZED_WIRE_10\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1187:1187:1187) (1221:1221:1221)) + (PORT datac (174:174:174) (206:206:206)) + (PORT datad (183:183:183) (210:210:210)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_we_lo\~2) + (DELAY + (ABSOLUTE + (PORT datab (880:880:880) (891:891:891)) + (PORT datac (1103:1103:1103) (1114:1114:1114)) + (PORT datad (2311:2311:2311) (2392:2392:2392)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_we_lo\~3) + (DELAY + (ABSOLUTE + (PORT dataa (882:882:882) (892:892:892)) + (PORT datab (331:331:331) (343:343:343)) + (PORT datac (1079:1079:1079) (1098:1098:1098)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~14) + (DELAY + (ABSOLUTE + (PORT dataa (807:807:807) (819:819:819)) + (PORT datab (864:864:864) (856:856:856)) + (PORT datac (804:804:804) (787:787:787)) + (PORT datad (852:852:852) (904:904:904)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_hi\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1733:1733:1733) (1717:1717:1717)) + (PORT datab (862:862:862) (852:852:852)) + (PORT datac (1937:1937:1937) (1966:1966:1966)) + (PORT datad (166:166:166) (188:188:188)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal33\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1127:1127:1127) (1163:1163:1163)) + (PORT datab (1706:1706:1706) (1684:1684:1684)) + (PORT datac (836:836:836) (859:859:859)) + (PORT datad (881:881:881) (913:913:913)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~0) + (DELAY + (ABSOLUTE + (PORT dataa (599:599:599) (627:627:627)) + (PORT datab (588:588:588) (586:586:586)) + (PORT datac (1322:1322:1322) (1323:1323:1323)) + (PORT datad (843:843:843) (860:860:860)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (878:878:878) (907:907:907)) + (PORT datab (188:188:188) (221:221:221)) + (PORT datac (1913:1913:1913) (1954:1954:1954)) + (PORT datad (1074:1074:1074) (1075:1075:1075)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (750:750:750) (746:746:746)) + (PORT datab (605:605:605) (615:615:615)) + (PORT datac (1421:1421:1421) (1416:1416:1416)) + (PORT datad (999:999:999) (997:997:997)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~4) + (DELAY + (ABSOLUTE + (PORT dataa (819:819:819) (824:824:824)) + (PORT datab (974:974:974) (1016:1016:1016)) + (PORT datac (608:608:608) (631:631:631)) + (PORT datad (590:590:590) (620:620:620)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_hi) + (DELAY + (ABSOLUTE + (PORT dataa (830:830:830) (819:819:819)) + (PORT datab (818:818:818) (815:815:815)) + (PORT datad (170:170:170) (195:195:195)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (855:855:855) (869:869:869)) + (PORT datab (1180:1180:1180) (1201:1201:1201)) + (PORT datac (1136:1136:1136) (1189:1189:1189)) + (PORT datad (1097:1097:1097) (1107:1107:1107)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1142:1142:1142) (1148:1148:1148)) + (PORT datab (1673:1673:1673) (1707:1707:1707)) + (PORT datac (793:793:793) (795:795:795)) + (PORT datad (1155:1155:1155) (1172:1172:1172)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1277:1277:1277) (1276:1276:1276)) + (PORT datab (1647:1647:1647) (1635:1635:1635)) + (PORT datac (1064:1064:1064) (1049:1049:1049)) + (PORT datad (158:158:158) (179:179:179)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~12) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (219:219:219)) + (PORT datab (365:365:365) (379:379:379)) + (PORT datac (155:155:155) (186:186:186)) + (PORT datad (339:339:339) (348:348:348)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~13) + (DELAY + (ABSOLUTE + (PORT dataa (209:209:209) (256:256:256)) + (PORT datab (1597:1597:1597) (1584:1584:1584)) + (PORT datac (524:524:524) (508:508:508)) + (PORT datad (1394:1394:1394) (1439:1439:1439)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla56M3T3_6) + (DELAY + (ABSOLUTE + (PORT dataa (1086:1086:1086) (1113:1113:1113)) + (PORT datab (599:599:599) (620:620:620)) + (PORT datac (1196:1196:1196) (1227:1227:1227)) + (PORT datad (1539:1539:1539) (1626:1626:1626)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1178:1178:1178) (1185:1185:1185)) + (PORT datab (1134:1134:1134) (1140:1140:1140)) + (PORT datac (560:560:560) (560:560:560)) + (PORT datad (183:183:183) (209:209:209)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~7) + (DELAY + (ABSOLUTE + (PORT dataa (830:830:830) (815:815:815)) + (PORT datab (207:207:207) (241:241:241)) + (PORT datac (1939:1939:1939) (1966:1966:1966)) + (PORT datad (742:742:742) (735:735:735)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1642:1642:1642) (1678:1678:1678)) + (PORT datab (1388:1388:1388) (1428:1428:1428)) + (PORT datac (1020:1020:1020) (1007:1007:1007)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (1240:1240:1240) (1267:1267:1267)) + (PORT datab (592:592:592) (593:593:593)) + (PORT datac (566:566:566) (569:569:569)) + (PORT datad (1289:1289:1289) (1287:1287:1287)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~8) + (DELAY + (ABSOLUTE + (PORT dataa (837:837:837) (850:850:850)) + (PORT datac (1014:1014:1014) (995:995:995)) + (PORT datad (1095:1095:1095) (1080:1080:1080)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (569:569:569) (591:591:591)) + (PORT datab (619:619:619) (606:606:606)) + (PORT datac (562:562:562) (582:582:582)) + (PORT datad (860:860:860) (855:855:855)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (634:634:634) (668:668:668)) + (PORT datab (346:346:346) (369:369:369)) + (PORT datac (1084:1084:1084) (1078:1078:1078)) + (PORT datad (1059:1059:1059) (1057:1057:1057)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~41) + (DELAY + (ABSOLUTE + (PORT dataa (1064:1064:1064) (1039:1039:1039)) + (PORT datab (1672:1672:1672) (1707:1707:1707)) + (PORT datac (1049:1049:1049) (1042:1042:1042)) + (PORT datad (1154:1154:1154) (1172:1172:1172)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~10) + (DELAY + (ABSOLUTE + (PORT dataa (869:869:869) (888:888:888)) + (PORT datac (821:821:821) (832:832:832)) + (PORT datad (842:842:842) (863:863:863)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\~21) + (DELAY + (ABSOLUTE + (PORT dataa (1510:1510:1510) (1590:1590:1590)) + (PORT datab (852:852:852) (871:871:871)) + (PORT datad (1484:1484:1484) (1551:1551:1551)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~3) + (DELAY + (ABSOLUTE + (PORT dataa (258:258:258) (345:345:345)) + (PORT datab (244:244:244) (318:318:318)) + (PORT datad (222:222:222) (283:283:283)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (774:774:774) (752:752:752)) + (PORT datab (1079:1079:1079) (1076:1076:1076)) + (PORT datac (780:780:780) (771:771:771)) + (PORT datad (178:178:178) (199:199:199)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (189:189:189) (226:226:226)) + (PORT datab (610:610:610) (601:601:601)) + (PORT datac (1239:1239:1239) (1222:1222:1222)) + (PORT datad (975:975:975) (993:993:993)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (1361:1361:1361) (1355:1355:1355)) + (PORT datab (881:881:881) (891:891:891)) + (PORT datac (562:562:562) (560:560:560)) + (PORT datad (569:569:569) (577:577:577)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (888:888:888) (907:907:907)) + (PORT datab (1562:1562:1562) (1567:1567:1567)) + (PORT datac (1238:1238:1238) (1217:1217:1217)) + (PORT datad (303:303:303) (317:317:317)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1441:1441:1441) (1482:1482:1482)) + (PORT datac (894:894:894) (919:919:919)) + (PORT datad (834:834:834) (867:867:867)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (1118:1118:1118) (1109:1109:1109)) + (PORT datab (987:987:987) (978:978:978)) + (PORT datac (844:844:844) (845:845:845)) + (PORT datad (192:192:192) (228:228:228)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (379:379:379) (401:401:401)) + (PORT datab (559:559:559) (557:557:557)) + (PORT datad (1033:1033:1033) (1044:1044:1044)) + (IOPATH dataa combout (267:267:267) (273:273:273)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (823:823:823) (834:834:834)) + (PORT datab (218:218:218) (262:262:262)) + (PORT datad (785:785:785) (793:793:793)) + (IOPATH dataa combout (267:267:267) (273:273:273)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (219:219:219)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (156:156:156) (186:186:186)) + (PORT datad (860:860:860) (877:877:877)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (237:237:237)) + (PORT datab (180:180:180) (212:212:212)) + (PORT datac (1419:1419:1419) (1466:1466:1466)) + (PORT datad (530:530:530) (518:518:518)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~30) (DELAY (ABSOLUTE - (PORT dataa (586:586:586) (588:588:588)) - (PORT datab (1157:1157:1157) (1140:1140:1140)) - (PORT datac (1681:1681:1681) (1734:1734:1734)) - (PORT datad (1026:1026:1026) (1018:1018:1018)) - (IOPATH dataa combout (290:290:290) (306:306:306)) + (PORT dataa (826:826:826) (838:838:838)) + (PORT datab (539:539:539) (528:528:528)) + (PORT datac (781:781:781) (789:789:789)) + (PORT datad (461:461:461) (449:449:449)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1866:1866:1866) (1905:1905:1905)) + (PORT datab (864:864:864) (857:857:857)) + (PORT datac (1939:1939:1939) (1969:1969:1969)) + (PORT datad (183:183:183) (208:208:208)) + (IOPATH dataa combout (329:329:329) (332:332:332)) (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -16276,11 +10912,11 @@ (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~32) (DELAY (ABSOLUTE - (PORT dataa (597:597:597) (625:625:625)) - (PORT datab (846:846:846) (872:872:872)) - (PORT datac (804:804:804) (801:801:801)) - (PORT datad (157:157:157) (177:177:177)) - (IOPATH dataa combout (329:329:329) (332:332:332)) + (PORT dataa (808:808:808) (818:818:818)) + (PORT datab (756:756:756) (817:817:817)) + (PORT datac (837:837:837) (829:829:829)) + (PORT datad (817:817:817) (830:830:830)) + (IOPATH dataa combout (290:290:290) (306:306:306)) (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -16292,28 +10928,12 @@ (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~33) (DELAY (ABSOLUTE - (PORT dataa (190:190:190) (232:232:232)) - (PORT datab (182:182:182) (215:215:215)) - (PORT datac (1071:1071:1071) (1070:1070:1070)) - (PORT datad (183:183:183) (218:218:218)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_hi\~0) - (DELAY - (ABSOLUTE - (PORT dataa (648:648:648) (686:686:686)) - (PORT datab (188:188:188) (221:221:221)) - (PORT datac (322:322:322) (336:336:336)) - (PORT datad (1066:1066:1066) (1059:1059:1059)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) + (PORT dataa (1393:1393:1393) (1431:1431:1431)) + (PORT datab (212:212:212) (251:251:251)) + (PORT datac (1453:1453:1453) (1451:1451:1451)) + (PORT datad (2109:2109:2109) (2096:2096:2096)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -16321,12 +10941,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_hi) + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~34) (DELAY (ABSOLUTE - (PORT datab (856:856:856) (854:854:854)) - (PORT datac (552:552:552) (546:546:546)) - (PORT datad (166:166:166) (192:192:192)) + (PORT dataa (1551:1551:1551) (1536:1536:1536)) + (PORT datab (605:605:605) (621:621:621)) + (PORT datac (1131:1131:1131) (1205:1205:1205)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (329:329:329) (332:332:332)) (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -16335,12 +10957,28 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_81) + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~35) (DELAY (ABSOLUTE - (PORT dataa (822:822:822) (813:813:813)) - (PORT datac (1053:1053:1053) (1034:1034:1034)) - (PORT datad (775:775:775) (763:763:763)) + (PORT dataa (190:190:190) (230:230:230)) + (PORT datab (601:601:601) (601:601:601)) + (PORT datac (161:161:161) (196:196:196)) + (PORT datad (1069:1069:1069) (1141:1141:1141)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_73) + (DELAY + (ABSOLUTE + (PORT dataa (972:972:972) (955:955:955)) + (PORT datac (1015:1015:1015) (997:997:997)) + (PORT datad (825:825:825) (844:844:844)) (IOPATH dataa combout (273:273:273) (269:269:269)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -16349,91 +10987,58 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[3\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[3\]) (DELAY (ABSOLUTE - (PORT clk (1344:1344:1344) (1361:1361:1361)) - (PORT asdata (1392:1392:1392) (1376:1376:1376)) - (PORT ena (1164:1164:1164) (1167:1167:1167)) + (PORT clk (1342:1342:1342) (1359:1359:1359)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1154:1154:1154) (1149:1149:1149)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) + (HOLD d (posedge clk) (144:144:144)) (HOLD ena (posedge clk) (144:144:144)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_80) + (INSTANCE z80_\|execute_\|ctl_reg_sel_ir\~0) (DELAY (ABSOLUTE - (PORT dataa (819:819:819) (811:811:811)) - (PORT datac (1047:1047:1047) (1033:1033:1033)) - (PORT datad (777:777:777) (763:763:763)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~45) - (DELAY - (ABSOLUTE - (PORT dataa (1019:1019:1019) (1011:1011:1011)) - (PORT datab (1187:1187:1187) (1245:1245:1245)) - (PORT datad (776:776:776) (789:789:789)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_41\~0) - (DELAY - (ABSOLUTE - (PORT dataa (588:588:588) (614:614:614)) - (PORT datab (1170:1170:1170) (1220:1220:1220)) - (PORT datac (1060:1060:1060) (1052:1052:1052)) - (PORT datad (350:350:350) (371:371:371)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) + (PORT datab (934:934:934) (962:962:962)) + (PORT datac (877:877:877) (910:910:910)) + (PORT datad (872:872:872) (903:903:903)) + (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[3\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_ir\~1) (DELAY (ABSOLUTE - (PORT clk (1345:1345:1345) (1362:1362:1362)) - (PORT asdata (912:912:912) (931:931:931)) - (PORT ena (1093:1093:1093) (1070:1070:1070)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (PORT dataa (1203:1203:1203) (1255:1255:1255)) + (PORT datab (1272:1272:1272) (1290:1290:1290)) + (PORT datac (321:321:321) (324:324:324)) + (PORT datad (750:750:750) (812:812:812)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_36\~0) + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_60) (DELAY (ABSOLUTE - (PORT dataa (377:377:377) (411:411:411)) - (PORT datab (1170:1170:1170) (1212:1212:1212)) - (PORT datac (1055:1055:1055) (1054:1054:1054)) - (PORT datad (612:612:612) (618:618:618)) - (IOPATH dataa combout (287:287:287) (280:280:280)) + (PORT datab (850:850:850) (883:883:883)) + (PORT datac (1016:1016:1016) (998:998:998)) + (PORT datad (743:743:743) (722:722:722)) (IOPATH datab combout (273:273:273) (275:275:275)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -16442,28 +11047,26 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_37\~0) + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_61) (DELAY (ABSOLUTE - (PORT dataa (589:589:589) (616:616:616)) - (PORT datab (1166:1166:1166) (1211:1211:1211)) - (PORT datac (1057:1057:1057) (1053:1053:1053)) - (PORT datad (356:356:356) (372:372:372)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT datab (850:850:850) (879:879:879)) + (PORT datac (1018:1018:1018) (1000:1000:1000)) + (PORT datad (744:744:744) (722:722:722)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[3\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[3\]) (DELAY (ABSOLUTE - (PORT clk (1345:1345:1345) (1362:1362:1362)) - (PORT asdata (912:912:912) (931:931:931)) - (PORT ena (1173:1173:1173) (1169:1169:1169)) + (PORT clk (1342:1342:1342) (1359:1359:1359)) + (PORT asdata (485:485:485) (512:512:512)) + (PORT ena (1335:1335:1335) (1307:1307:1307)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -16474,13 +11077,954 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_40\~0) + (INSTANCE z80_\|execute_\|ctl_reg_sys_we_lo\~4) (DELAY (ABSOLUTE - (PORT dataa (376:376:376) (409:409:409)) - (PORT datab (1169:1169:1169) (1219:1219:1219)) - (PORT datac (1060:1060:1060) (1052:1052:1052)) - (PORT datad (615:615:615) (614:614:614)) + (PORT datab (1082:1082:1082) (1072:1072:1072)) + (PORT datac (1507:1507:1507) (1507:1507:1507)) + (PORT datad (853:853:853) (893:893:893)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo) + (DELAY + (ABSOLUTE + (PORT dataa (581:581:581) (608:608:608)) + (PORT datab (183:183:183) (216:216:216)) + (PORT datac (1591:1591:1591) (1622:1622:1622)) + (PORT datad (789:789:789) (779:779:779)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sw_4d_hi\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1028:1028:1028) (1007:1007:1007)) + (PORT datab (853:853:853) (878:878:878)) + (PORT datac (1048:1048:1048) (1038:1038:1038)) + (PORT datad (744:744:744) (720:720:720)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (819:819:819) (811:811:811)) + (PORT datab (620:620:620) (645:645:645)) + (PORT datad (615:615:615) (641:641:641)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~11) + (DELAY + (ABSOLUTE + (PORT datab (632:632:632) (642:642:642)) + (PORT datac (328:328:328) (375:375:375)) + (PORT datad (296:296:296) (292:292:292)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[11\]) + (DELAY + (ABSOLUTE + (PORT dataa (631:631:631) (625:625:625)) + (PORT datac (545:545:545) (535:535:535)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_apin_mux\~1) + (DELAY + (ABSOLUTE + (PORT dataa (944:944:944) (1004:1004:1004)) + (PORT datab (1400:1400:1400) (1482:1482:1482)) + (PORT datac (1035:1035:1035) (1053:1053:1053)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~37) + (DELAY + (ABSOLUTE + (PORT dataa (1185:1185:1185) (1238:1238:1238)) + (PORT datab (1244:1244:1244) (1296:1296:1296)) + (PORT datac (1585:1585:1585) (1580:1580:1580)) + (PORT datad (905:905:905) (937:937:937)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1117:1117:1117) (1128:1128:1128)) + (PORT datab (945:945:945) (974:974:974)) + (PORT datac (1075:1075:1075) (1079:1079:1079)) + (PORT datad (177:177:177) (198:198:198)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~40) + (DELAY + (ABSOLUTE + (PORT dataa (1613:1613:1613) (1608:1608:1608)) + (PORT datab (1247:1247:1247) (1292:1292:1292)) + (PORT datac (1405:1405:1405) (1429:1429:1429)) + (PORT datad (1343:1343:1343) (1349:1349:1349)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1896:1896:1896) (1962:1962:1962)) + (PORT datab (200:200:200) (233:233:233)) + (PORT datac (1074:1074:1074) (1078:1078:1078)) + (PORT datad (1672:1672:1672) (1707:1707:1707)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1117:1117:1117) (1130:1130:1130)) + (PORT datab (188:188:188) (226:226:226)) + (PORT datac (155:155:155) (186:186:186)) + (PORT datad (1340:1340:1340) (1351:1351:1351)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (627:627:627) (673:673:673)) + (PORT datab (1047:1047:1047) (1052:1052:1052)) + (PORT datac (1392:1392:1392) (1434:1434:1434)) + (PORT datad (1337:1337:1337) (1333:1333:1333)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla6M1T4_4) + (DELAY + (ABSOLUTE + (PORT dataa (1206:1206:1206) (1259:1259:1259)) + (PORT datab (888:888:888) (921:921:921)) + (PORT datac (1518:1518:1518) (1532:1532:1532)) + (PORT datad (892:892:892) (907:907:907)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~42) + (DELAY + (ABSOLUTE + (PORT dataa (989:989:989) (1009:1009:1009)) + (PORT datac (743:743:743) (782:782:782)) + (PORT datad (1536:1536:1536) (1493:1493:1493)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (238:238:238)) + (PORT datab (195:195:195) (232:232:232)) + (PORT datac (725:725:725) (763:763:763)) + (PORT datad (1185:1185:1185) (1227:1227:1227)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_1d\~4) + (DELAY + (ABSOLUTE + (PORT dataa (616:616:616) (620:620:620)) + (PORT datab (636:636:636) (658:658:658)) + (PORT datac (853:853:853) (864:864:864)) + (PORT datad (1038:1038:1038) (1038:1038:1038)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~3) + (DELAY + (ABSOLUTE + (PORT datab (795:795:795) (854:854:854)) + (PORT datac (545:545:545) (559:559:559)) + (PORT datad (559:559:559) (553:553:553)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~9) + (DELAY + (ABSOLUTE + (PORT dataa (770:770:770) (800:800:800)) + (PORT datab (1134:1134:1134) (1173:1173:1173)) + (PORT datac (1611:1611:1611) (1638:1638:1638)) + (PORT datad (1333:1333:1333) (1327:1327:1327)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1640:1640:1640) (1671:1671:1671)) + (PORT datab (180:180:180) (212:212:212)) + (PORT datac (1537:1537:1537) (1531:1531:1531)) + (PORT datad (1332:1332:1332) (1326:1326:1326)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1878:1878:1878) (1903:1903:1903)) + (PORT datab (1331:1331:1331) (1334:1334:1334)) + (PORT datac (611:611:611) (616:616:616)) + (PORT datad (1015:1015:1015) (1012:1012:1012)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~2) + (DELAY + (ABSOLUTE + (PORT dataa (373:373:373) (399:399:399)) + (PORT datab (201:201:201) (236:236:236)) + (PORT datad (727:727:727) (758:758:758)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~11) + (DELAY + (ABSOLUTE + (PORT dataa (328:328:328) (356:356:356)) + (PORT datab (1562:1562:1562) (1570:1570:1570)) + (PORT datac (1234:1234:1234) (1220:1220:1220)) + (PORT datad (166:166:166) (192:192:192)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~12) + (DELAY + (ABSOLUTE + (PORT datac (782:782:782) (792:792:792)) + (PORT datad (774:774:774) (757:757:757)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1654:1654:1654) (1701:1701:1701)) + (PORT datab (217:217:217) (260:260:260)) + (PORT datac (610:610:610) (634:634:634)) + (PORT datad (854:854:854) (846:846:846)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~5) + (DELAY + (ABSOLUTE + (PORT dataa (821:821:821) (828:828:828)) + (PORT datab (558:558:558) (573:573:573)) + (PORT datac (334:334:334) (341:341:341)) + (PORT datad (564:564:564) (562:562:562)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1320:1320:1320) (1335:1335:1335)) + (PORT datab (1091:1091:1091) (1077:1077:1077)) + (PORT datac (579:579:579) (612:612:612)) + (PORT datad (1113:1113:1113) (1124:1124:1124)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~10) + (DELAY + (ABSOLUTE + (PORT dataa (360:360:360) (371:371:371)) + (PORT datac (978:978:978) (962:962:962)) + (PORT datad (548:548:548) (540:540:540)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1744:1744:1744) (1706:1706:1706)) + (PORT datab (366:366:366) (382:382:382)) + (PORT datac (1363:1363:1363) (1372:1372:1372)) + (PORT datad (340:340:340) (348:348:348)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1098:1098:1098) (1090:1090:1090)) + (PORT datab (559:559:559) (550:550:550)) + (PORT datac (325:325:325) (341:341:341)) + (PORT datad (195:195:195) (229:229:229)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (798:798:798) (812:812:812)) + (PORT datab (591:591:591) (626:626:626)) + (PORT datac (1703:1703:1703) (1649:1649:1649)) + (PORT datad (558:558:558) (569:569:569)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~9) + (DELAY + (ABSOLUTE + (PORT dataa (608:608:608) (602:602:602)) + (PORT datab (1381:1381:1381) (1380:1380:1380)) + (PORT datac (566:566:566) (578:578:578)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~11) + (DELAY + (ABSOLUTE + (PORT dataa (578:578:578) (566:566:566)) + (PORT datab (188:188:188) (223:223:223)) + (PORT datac (156:156:156) (185:185:185)) + (PORT datad (158:158:158) (179:179:179)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~12) + (DELAY + (ABSOLUTE + (PORT dataa (212:212:212) (255:255:255)) + (PORT datab (1600:1600:1600) (1586:1586:1586)) + (PORT datac (322:322:322) (325:325:325)) + (PORT datad (1396:1396:1396) (1441:1441:1441)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1341:1341:1341) (1358:1358:1358)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1384:1384:1384) (1357:1357:1357)) + (PORT ena (1540:1540:1540) (1508:1508:1508)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIOWrite\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1961:1961:1961) (1999:1999:1999)) + (PORT datab (2117:2117:2117) (2138:2138:2138)) + (PORT datac (1432:1432:1432) (1479:1479:1479)) + (PORT datad (1849:1849:1849) (1867:1867:1867)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~8) + (DELAY + (ABSOLUTE + (PORT dataa (2349:2349:2349) (2372:2372:2372)) + (PORT datab (1100:1100:1100) (1081:1081:1081)) + (PORT datac (593:593:593) (595:595:595)) + (PORT datad (768:768:768) (823:823:823)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1469:1469:1469) (1491:1491:1491)) + (PORT datab (192:192:192) (230:230:230)) + (PORT datac (175:175:175) (207:207:207)) + (PORT datad (1074:1074:1074) (1075:1075:1075)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~9) + (DELAY + (ABSOLUTE + (PORT dataa (209:209:209) (248:248:248)) + (PORT datab (182:182:182) (214:214:214)) + (PORT datac (765:765:765) (757:757:757)) + (PORT datad (585:585:585) (612:612:612)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[1\]) + (DELAY + (ABSOLUTE + (PORT dataa (575:575:575) (581:581:581)) + (PORT datac (857:857:857) (855:855:855)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1347:1347:1347) (1368:1368:1368)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1394:1394:1394) (1364:1364:1364)) + (PORT ena (1828:1828:1828) (1776:1776:1776)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_apin_mux\~0) + (DELAY + (ABSOLUTE + (PORT dataa (196:196:196) (240:240:240)) + (PORT datab (199:199:199) (232:232:232)) + (PORT datac (187:187:187) (224:224:224)) + (PORT datad (1084:1084:1084) (1093:1093:1093)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1744:1744:1744) (1706:1706:1706)) + (PORT datab (1708:1708:1708) (1748:1748:1748)) + (PORT datac (175:175:175) (207:207:207)) + (PORT datad (1122:1122:1122) (1134:1134:1134)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1764:1764:1764) (1811:1811:1811)) + (PORT datac (1624:1624:1624) (1669:1669:1669)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_40\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1708:1708:1708) (1741:1741:1741)) + (PORT datab (363:363:363) (414:414:414)) + (PORT datac (1190:1190:1190) (1155:1155:1155)) + (PORT datad (177:177:177) (210:210:210)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~21) + (DELAY + (ABSOLUTE + (PORT dataa (1068:1068:1068) (1067:1067:1067)) + (PORT datab (1416:1416:1416) (1450:1450:1450)) + (PORT datac (1205:1205:1205) (1170:1170:1170)) + (PORT datad (1044:1044:1044) (1059:1059:1059)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (1772:1772:1772) (1787:1787:1787)) + (PORT datab (1154:1154:1154) (1171:1171:1171)) + (PORT datac (174:174:174) (206:206:206)) + (PORT datad (1841:1841:1841) (1868:1868:1868)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (1609:1609:1609) (1660:1660:1660)) + (PORT datab (211:211:211) (250:250:250)) + (PORT datac (1453:1453:1453) (1451:1451:1451)) + (PORT datad (1663:1663:1663) (1711:1711:1711)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (184:184:184) (222:222:222)) + (PORT datab (1498:1498:1498) (1535:1535:1535)) + (PORT datac (742:742:742) (783:783:783)) + (PORT datad (1346:1346:1346) (1388:1388:1388)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (191:191:191) (233:233:233)) + (PORT datab (1335:1335:1335) (1309:1309:1309)) + (PORT datac (156:156:156) (186:186:186)) + (PORT datad (1193:1193:1193) (1264:1264:1264)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_63) + (DELAY + (ABSOLUTE + (PORT datab (833:833:833) (854:854:854)) + (PORT datac (1044:1044:1044) (1034:1034:1034)) + (PORT datad (744:744:744) (720:720:720)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1340:1340:1340) (1357:1357:1357)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1132:1132:1132) (1111:1111:1111)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~49) + (DELAY + (ABSOLUTE + (PORT dataa (1801:1801:1801) (1779:1779:1779)) + (PORT datab (1158:1158:1158) (1182:1182:1182)) + (PORT datac (847:847:847) (867:867:867)) + (PORT datad (994:994:994) (1039:1039:1039)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~2) + (DELAY + (ABSOLUTE + (PORT datac (793:793:793) (783:783:783)) + (PORT datad (597:597:597) (629:629:629)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~50) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (240:240:240)) + (PORT datab (1183:1183:1183) (1222:1222:1222)) + (PORT datac (157:157:157) (188:188:188)) + (PORT datad (540:540:540) (529:529:529)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (868:868:868) (882:882:882)) + (PORT datab (1635:1635:1635) (1648:1648:1648)) + (PORT datac (625:625:625) (657:657:657)) + (PORT datad (833:833:833) (847:847:847)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_oe\~1) + (DELAY + (ABSOLUTE + (PORT dataa (209:209:209) (250:250:250)) + (PORT datab (218:218:218) (252:252:252)) + (PORT datac (587:587:587) (595:595:595)) + (PORT datad (1123:1123:1123) (1131:1131:1131)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~13) + (DELAY + (ABSOLUTE + (PORT dataa (817:817:817) (819:819:819)) + (PORT datab (1128:1128:1128) (1187:1187:1187)) + (PORT datac (776:776:776) (771:771:771)) + (PORT datad (1126:1126:1126) (1170:1170:1170)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~12) + (DELAY + (ABSOLUTE + (PORT datab (793:793:793) (798:798:798)) + (PORT datac (533:533:533) (528:528:528)) + (PORT datad (516:516:516) (498:498:498)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1791:1791:1791) (1771:1771:1771)) + (PORT datab (1307:1307:1307) (1266:1266:1266)) + (PORT datac (545:545:545) (548:548:548)) + (PORT datad (1325:1325:1325) (1377:1377:1377)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1266:1266:1266) (1280:1280:1280)) + (PORT datab (1128:1128:1128) (1186:1186:1186)) + (PORT datac (905:905:905) (920:920:920)) + (PORT datad (822:822:822) (799:799:799)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1373:1373:1373) (1341:1341:1341)) + (PORT datab (190:190:190) (226:226:226)) + (PORT datac (318:318:318) (341:341:341)) + (PORT datad (183:183:183) (208:208:208)) (IOPATH dataa combout (265:265:265) (273:273:273)) (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (215:215:215)) @@ -16490,12 +12034,1382 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~42) + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~5) (DELAY (ABSOLUTE - (PORT dataa (390:390:390) (429:429:429)) - (PORT datab (1479:1479:1479) (1478:1478:1478)) - (PORT datad (1098:1098:1098) (1089:1089:1089)) + (PORT dataa (1056:1056:1056) (1053:1053:1053)) + (PORT datab (207:207:207) (240:240:240)) + (PORT datac (1016:1016:1016) (996:996:996)) + (PORT datad (1097:1097:1097) (1080:1080:1080)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1084:1084:1084) (1085:1085:1085)) + (PORT datab (201:201:201) (235:235:235)) + (PORT datac (1131:1131:1131) (1169:1169:1169)) + (PORT datad (578:578:578) (582:582:582)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (967:967:967) (965:965:965)) + (PORT datab (609:609:609) (598:598:598)) + (PORT datac (767:767:767) (773:773:773)) + (PORT datad (167:167:167) (193:193:193)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~10) + (DELAY + (ABSOLUTE + (PORT dataa (210:210:210) (253:253:253)) + (PORT datab (1031:1031:1031) (1079:1079:1079)) + (PORT datac (1721:1721:1721) (1727:1727:1727)) + (PORT datad (1337:1337:1337) (1338:1338:1338)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_1d\~9) + (DELAY + (ABSOLUTE + (PORT datab (1689:1689:1689) (1712:1712:1712)) + (PORT datac (1913:1913:1913) (2002:2002:2002)) + (PORT datad (810:810:810) (814:814:814)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~9) + (DELAY + (ABSOLUTE + (PORT dataa (2048:2048:2048) (2103:2103:2103)) + (PORT datab (896:896:896) (971:971:971)) + (PORT datac (175:175:175) (205:205:205)) + (PORT datad (1207:1207:1207) (1171:1171:1171)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (903:903:903) (938:938:938)) + (PORT datab (783:783:783) (815:815:815)) + (PORT datad (321:321:321) (336:336:336)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~7) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (391:391:391)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (513:513:513) (504:504:504)) + (PORT datad (165:165:165) (189:189:189)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1021:1021:1021) (1084:1084:1084)) + (PORT datab (1477:1477:1477) (1527:1527:1527)) + (PORT datac (546:546:546) (547:547:547)) + (PORT datad (171:171:171) (201:201:201)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (2129:2129:2129) (2111:2111:2111)) + (PORT datab (817:817:817) (815:815:815)) + (PORT datac (1846:1846:1846) (1883:1883:1883)) + (PORT datad (1872:1872:1872) (1909:1909:1909)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1467:1467:1467) (1524:1524:1524)) + (PORT datab (1245:1245:1245) (1286:1286:1286)) + (PORT datac (1846:1846:1846) (1884:1884:1884)) + (PORT datad (1152:1152:1152) (1150:1150:1150)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~3) + (DELAY + (ABSOLUTE + (PORT dataa (826:826:826) (836:836:836)) + (PORT datab (187:187:187) (224:224:224)) + (PORT datac (156:156:156) (187:187:187)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (901:901:901) (909:909:909)) + (PORT datab (633:633:633) (635:635:635)) + (PORT datac (786:786:786) (790:790:790)) + (PORT datad (822:822:822) (827:827:827)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (586:586:586) (619:619:619)) + (PORT datab (1706:1706:1706) (1681:1681:1681)) + (PORT datac (301:301:301) (309:309:309)) + (PORT datad (566:566:566) (589:589:589)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (534:534:534) (541:541:541)) + (PORT datab (1362:1362:1362) (1412:1412:1412)) + (PORT datac (546:546:546) (550:550:550)) + (PORT datad (1224:1224:1224) (1240:1240:1240)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla30npla13M4T3_5) + (DELAY + (ABSOLUTE + (PORT dataa (1203:1203:1203) (1244:1244:1244)) + (PORT datab (2228:2228:2228) (2297:2297:2297)) + (PORT datac (1015:1015:1015) (997:997:997)) + (PORT datad (1095:1095:1095) (1082:1082:1082)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (880:880:880) (875:875:875)) + (PORT datab (893:893:893) (880:880:880)) + (PORT datac (1498:1498:1498) (1483:1483:1483)) + (PORT datad (1046:1046:1046) (1011:1011:1011)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (1106:1106:1106) (1073:1073:1073)) + (PORT datab (182:182:182) (215:215:215)) + (PORT datac (1359:1359:1359) (1366:1366:1366)) + (PORT datad (865:865:865) (874:874:874)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (896:896:896) (942:942:942)) + (PORT datab (1387:1387:1387) (1422:1422:1422)) + (PORT datac (1125:1125:1125) (1174:1174:1174)) + (PORT datad (1083:1083:1083) (1082:1082:1082)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (802:802:802) (787:787:787)) + (PORT datab (1598:1598:1598) (1584:1584:1584)) + (PORT datac (157:157:157) (188:188:188)) + (PORT datad (1394:1394:1394) (1439:1439:1439)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (218:218:218)) + (PORT datab (181:181:181) (212:212:212)) + (PORT datac (175:175:175) (206:206:206)) + (PORT datad (566:566:566) (570:570:570)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (249:249:249)) + (PORT datab (892:892:892) (917:917:917)) + (PORT datac (579:579:579) (610:610:610)) + (PORT datad (1393:1393:1393) (1438:1438:1438)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (1550:1550:1550) (1557:1557:1557)) + (PORT datab (1089:1089:1089) (1117:1117:1117)) + (PORT datac (776:776:776) (770:770:770)) + (PORT datad (764:764:764) (746:746:746)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (217:217:217)) + (PORT datab (584:584:584) (618:618:618)) + (PORT datac (528:528:528) (531:531:531)) + (PORT datad (331:331:331) (340:340:340)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (1881:1881:1881) (1915:1915:1915)) + (PORT datab (1033:1033:1033) (1069:1069:1069)) + (PORT datac (2103:2103:2103) (2080:2080:2080)) + (PORT datad (1222:1222:1222) (1255:1255:1255)) + (IOPATH dataa combout (267:267:267) (273:273:273)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (824:824:824) (834:834:834)) + (PORT datab (395:395:395) (412:412:412)) + (PORT datac (768:768:768) (827:827:827)) + (PORT datad (177:177:177) (199:199:199)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (185:185:185) (222:222:222)) + (PORT datab (188:188:188) (225:225:225)) + (PORT datac (545:545:545) (558:558:558)) + (PORT datad (177:177:177) (198:198:198)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (1372:1372:1372) (1340:1340:1340)) + (PORT datab (207:207:207) (240:240:240)) + (PORT datac (627:627:627) (645:645:645)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (882:882:882) (922:922:922)) + (PORT datab (194:194:194) (231:231:231)) + (PORT datad (818:818:818) (829:829:829)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (587:587:587) (577:577:577)) + (PORT datab (1015:1015:1015) (1005:1005:1005)) + (PORT datac (780:780:780) (784:784:784)) + (PORT datad (1068:1068:1068) (1088:1088:1088)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (384:384:384) (400:400:400)) + (PORT datab (359:359:359) (387:387:387)) + (PORT datac (162:162:162) (198:198:198)) + (PORT datad (157:157:157) (177:177:177)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal2\~2) + (DELAY + (ABSOLUTE + (PORT dataa (713:713:713) (786:786:786)) + (PORT datab (1766:1766:1766) (1835:1835:1835)) + (PORT datac (1180:1180:1180) (1208:1208:1208)) + (PORT datad (799:799:799) (790:790:790)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal1\~6) + (DELAY + (ABSOLUTE + (PORT dataa (347:347:347) (380:380:380)) + (PORT datab (1205:1205:1205) (1259:1259:1259)) + (PORT datac (760:760:760) (794:794:794)) + (PORT datad (332:332:332) (338:338:338)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|bank_exx\~2) + (DELAY + (ABSOLUTE + (PORT dataa (819:819:819) (815:815:815)) + (PORT datab (1363:1363:1363) (1384:1384:1384)) + (PORT datad (1100:1100:1100) (1139:1139:1139)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_control_\|bank_exx) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1389:1389:1389) (1362:1362:1362)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|bank_hl_de1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (881:881:881) (903:903:903)) + (PORT datab (577:577:577) (599:599:599)) + (PORT datad (245:245:245) (320:320:320)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (312:312:312)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_control_\|bank_hl_de1) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1389:1389:1389) (1362:1362:1362)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (576:576:576) (591:591:591)) + (PORT datab (687:687:687) (742:742:742)) + (PORT datac (1097:1097:1097) (1085:1085:1085)) + (PORT datad (1491:1491:1491) (1464:1464:1464)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (863:863:863) (879:879:879)) + (PORT datac (555:555:555) (547:547:547)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (799:799:799) (778:778:778)) + (PORT datab (542:542:542) (531:531:531)) + (PORT datac (803:803:803) (794:794:794)) + (PORT datad (166:166:166) (193:193:193)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (190:190:190) (230:230:230)) + (PORT datab (182:182:182) (215:215:215)) + (PORT datac (763:763:763) (736:736:736)) + (PORT datad (856:856:856) (894:894:894)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (889:889:889) (910:910:910)) + (PORT datab (1169:1169:1169) (1197:1197:1197)) + (PORT datac (1578:1578:1578) (1591:1591:1591)) + (PORT datad (586:586:586) (567:567:567)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~45) + (DELAY + (ABSOLUTE + (PORT dataa (533:533:533) (540:540:540)) + (PORT datab (577:577:577) (579:579:579)) + (PORT datac (1918:1918:1918) (1999:1999:1999)) + (PORT datad (1651:1651:1651) (1665:1665:1665)) + (IOPATH dataa combout (307:307:307) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~2) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (247:247:247)) + (PORT datab (1574:1574:1574) (1530:1530:1530)) + (PORT datac (951:951:951) (970:970:970)) + (PORT datad (1183:1183:1183) (1223:1223:1223)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~3) + (DELAY + (ABSOLUTE + (PORT dataa (217:217:217) (259:259:259)) + (PORT datab (1089:1089:1089) (1100:1100:1100)) + (PORT datac (174:174:174) (215:215:215)) + (PORT datad (1411:1411:1411) (1440:1440:1440)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (586:586:586) (605:605:605)) + (PORT datab (200:200:200) (233:233:233)) + (PORT datac (180:180:180) (212:212:212)) + (PORT datad (746:746:746) (791:791:791)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (601:601:601) (604:604:604)) + (PORT datab (1321:1321:1321) (1330:1330:1330)) + (PORT datac (1077:1077:1077) (1043:1043:1043)) + (PORT datad (864:864:864) (875:875:875)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (993:993:993) (1030:1030:1030)) + (PORT datab (635:635:635) (657:657:657)) + (PORT datac (589:589:589) (589:589:589)) + (PORT datad (1447:1447:1447) (1455:1455:1455)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1073:1073:1073) (1065:1065:1065)) + (PORT datab (854:854:854) (860:860:860)) + (PORT datac (759:759:759) (755:755:755)) + (PORT datad (774:774:774) (793:793:793)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~34) + (DELAY + (ABSOLUTE + (PORT datab (313:313:313) (331:331:331)) + (PORT datac (161:161:161) (195:195:195)) + (PORT datad (847:847:847) (883:883:883)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (537:537:537) (536:536:536)) + (PORT datac (710:710:710) (695:695:695)) + (PORT datad (295:295:295) (304:304:304)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (770:770:770) (809:809:809)) + (PORT datab (620:620:620) (621:621:621)) + (PORT datac (862:862:862) (893:893:893)) + (PORT datad (1186:1186:1186) (1227:1227:1227)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (994:994:994) (1029:1029:1029)) + (PORT datab (1159:1159:1159) (1196:1196:1196)) + (PORT datac (854:854:854) (864:864:864)) + (PORT datad (867:867:867) (907:907:907)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (566:566:566) (579:579:579)) + (PORT datab (1233:1233:1233) (1209:1209:1209)) + (PORT datac (853:853:853) (868:868:868)) + (PORT datad (158:158:158) (179:179:179)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (831:831:831) (818:818:818)) + (PORT datab (1165:1165:1165) (1194:1194:1194)) + (PORT datac (1469:1469:1469) (1463:1463:1463)) + (PORT datad (624:624:624) (640:640:640)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (1713:1713:1713) (1745:1745:1745)) + (PORT datab (1642:1642:1642) (1722:1722:1722)) + (PORT datac (167:167:167) (205:205:205)) + (PORT datad (1077:1077:1077) (1079:1079:1079)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (991:991:991) (953:953:953)) + (PORT datab (578:578:578) (596:596:596)) + (PORT datac (949:949:949) (940:940:940)) + (PORT datad (1039:1039:1039) (1055:1055:1055)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (347:347:347) (352:352:352)) + (PORT datab (181:181:181) (213:213:213)) + (PORT datac (161:161:161) (193:193:193)) + (PORT datad (1536:1536:1536) (1562:1562:1562)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (195:195:195) (239:239:239)) + (PORT datab (999:999:999) (991:991:991)) + (PORT datac (806:806:806) (811:811:811)) + (PORT datad (1324:1324:1324) (1318:1318:1318)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (908:908:908) (960:960:960)) + (PORT datab (980:980:980) (956:956:956)) + (PORT datac (1541:1541:1541) (1556:1556:1556)) + (PORT datad (767:767:767) (757:757:757)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (658:658:658) (680:680:680)) + (PORT datab (389:389:389) (432:432:432)) + (PORT datac (588:588:588) (623:623:623)) + (PORT datad (213:213:213) (270:270:270)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (630:630:630) (661:661:661)) + (PORT datab (1566:1566:1566) (1604:1604:1604)) + (PORT datac (321:321:321) (345:345:345)) + (PORT datad (1493:1493:1493) (1455:1455:1455)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (650:650:650) (697:697:697)) + (PORT datab (1098:1098:1098) (1167:1167:1167)) + (PORT datac (649:649:649) (719:719:719)) + (PORT datad (1087:1087:1087) (1133:1133:1133)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (676:676:676) (746:746:746)) + (PORT datab (1093:1093:1093) (1083:1083:1083)) + (PORT datac (1070:1070:1070) (1140:1140:1140)) + (PORT datad (1265:1265:1265) (1274:1274:1274)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (851:851:851) (899:899:899)) + (PORT datab (182:182:182) (215:215:215)) + (PORT datac (156:156:156) (187:187:187)) + (PORT datad (1059:1059:1059) (1051:1051:1051)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (678:678:678) (713:713:713)) + (PORT datab (588:588:588) (600:600:600)) + (PORT datac (746:746:746) (744:744:744)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (534:534:534) (535:535:535)) + (PORT datab (344:344:344) (352:352:352)) + (PORT datac (792:792:792) (794:794:794)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_de2\~5) + (DELAY + (ABSOLUTE + (PORT dataa (448:448:448) (516:516:516)) + (PORT datab (442:442:442) (515:515:515)) + (PORT datac (785:785:785) (776:776:776)) + (PORT datad (845:845:845) (846:846:846)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_de2\~6) + (DELAY + (ABSOLUTE + (PORT dataa (535:535:535) (531:531:531)) + (PORT datab (316:316:316) (334:334:334)) + (PORT datac (713:713:713) (698:698:698)) + (PORT datad (178:178:178) (200:200:200)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_de\~0) + (DELAY + (ABSOLUTE + (PORT dataa (228:228:228) (304:304:304)) + (PORT datab (267:267:267) (351:351:351)) + (PORT datac (990:990:990) (952:952:952)) + (PORT datad (176:176:176) (204:204:204)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_50) + (DELAY + (ABSOLUTE + (PORT dataa (655:655:655) (695:695:695)) + (PORT datac (746:746:746) (756:756:756)) + (PORT datad (574:574:574) (585:585:585)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|bank_hl_de2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (883:883:883) (904:904:904)) + (PORT datab (572:572:572) (597:597:597)) + (PORT datad (245:245:245) (320:320:320)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_control_\|bank_hl_de2) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1389:1389:1389) (1362:1362:1362)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_de2\~4) + (DELAY + (ABSOLUTE + (PORT dataa (228:228:228) (304:304:304)) + (PORT datab (269:269:269) (355:355:355)) + (PORT datac (988:988:988) (952:952:952)) + (PORT datad (178:178:178) (206:206:206)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_46) + (DELAY + (ABSOLUTE + (PORT dataa (658:658:658) (698:698:698)) + (PORT datac (750:750:750) (755:755:755)) + (PORT datad (596:596:596) (612:612:612)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_47) + (DELAY + (ABSOLUTE + (PORT dataa (658:658:658) (695:695:695)) + (PORT datac (751:751:751) (756:756:756)) + (PORT datad (596:596:596) (613:613:613)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1351:1351:1351) (1372:1372:1372)) + (PORT asdata (1431:1431:1431) (1426:1426:1426)) + (PORT ena (892:892:892) (882:882:882)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_51) + (DELAY + (ABSOLUTE + (PORT dataa (658:658:658) (698:698:698)) + (PORT datac (750:750:750) (756:756:756)) + (PORT datad (574:574:574) (585:585:585)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1351:1351:1351) (1372:1372:1372)) + (PORT asdata (1430:1430:1430) (1424:1424:1424)) + (PORT ena (893:893:893) (883:883:883)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (382:382:382) (408:408:408)) + (PORT datab (404:404:404) (423:423:423)) + (PORT datad (196:196:196) (253:253:253)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_hl\~0) + (DELAY + (ABSOLUTE + (PORT dataa (227:227:227) (303:303:303)) + (PORT datab (268:268:268) (352:352:352)) + (PORT datac (986:986:986) (950:950:950)) + (PORT datad (178:178:178) (206:206:206)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_59) + (DELAY + (ABSOLUTE + (PORT dataa (839:839:839) (866:866:866)) + (PORT datab (595:595:595) (623:623:623)) + (PORT datad (558:558:558) (564:564:564)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1361:1361:1361)) + (PORT asdata (820:820:820) (799:799:799)) + (PORT ena (904:904:904) (889:889:889)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_hl2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (227:227:227) (303:303:303)) + (PORT datab (270:270:270) (352:352:352)) + (PORT datac (990:990:990) (956:956:956)) + (PORT datad (177:177:177) (203:203:203)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_54) + (DELAY + (ABSOLUTE + (PORT dataa (837:837:837) (860:860:860)) + (PORT datab (1107:1107:1107) (1103:1103:1103)) + (PORT datad (587:587:587) (601:601:601)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_55) + (DELAY + (ABSOLUTE + (PORT dataa (837:837:837) (866:866:866)) + (PORT datab (1104:1104:1104) (1105:1105:1105)) + (PORT datad (584:584:584) (600:600:600)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1361:1361:1361)) + (PORT asdata (819:819:819) (799:799:799)) + (PORT ena (735:735:735) (733:733:733)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_58) + (DELAY + (ABSOLUTE + (PORT dataa (836:836:836) (866:866:866)) + (PORT datac (566:566:566) (595:595:595)) + (PORT datad (557:557:557) (563:563:563)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (293:293:293)) + (PORT datab (224:224:224) (273:273:273)) + (PORT datad (208:208:208) (239:239:239)) (IOPATH dataa combout (273:273:273) (269:269:269)) (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (312:312:312) (325:325:325)) @@ -16505,75 +13419,957 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~46) + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_70\~2) (DELAY (ABSOLUTE - (PORT dataa (563:563:563) (566:566:566)) - (PORT datab (180:180:180) (213:213:213)) - (PORT datac (155:155:155) (185:185:185)) - (PORT datad (730:730:730) (696:696:696)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (PORT datab (1068:1068:1068) (1078:1078:1078)) + (PORT datac (874:874:874) (908:908:908)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~47) + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_38\~0) (DELAY (ABSOLUTE - (PORT dataa (573:573:573) (583:583:583)) - (PORT datab (312:312:312) (332:332:332)) - (PORT datac (155:155:155) (186:186:186)) - (PORT datad (578:578:578) (588:588:588)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (860:860:860) (882:882:882)) - (PORT datab (199:199:199) (232:232:232)) - (PORT datac (572:572:572) (586:586:586)) - (PORT datad (728:728:728) (697:697:697)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) + (PORT dataa (934:934:934) (984:984:984)) + (PORT datab (709:709:709) (735:735:735)) + (PORT datac (575:575:575) (596:596:596)) + (PORT datad (869:869:869) (872:872:872)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_71\~2) + (DELAY + (ABSOLUTE + (PORT datab (1065:1065:1065) (1073:1073:1073)) + (PORT datac (870:870:870) (902:902:902)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_43\~0) + (DELAY + (ABSOLUTE + (PORT dataa (940:940:940) (995:995:995)) + (PORT datab (701:701:701) (728:728:728)) + (PORT datac (565:565:565) (590:590:590)) + (PORT datad (864:864:864) (870:870:870)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1362:1362:1362)) + (PORT asdata (1164:1164:1164) (1165:1165:1165)) + (PORT ena (1115:1115:1115) (1103:1103:1103)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_39\~0) + (DELAY + (ABSOLUTE + (PORT dataa (940:940:940) (994:994:994)) + (PORT datab (706:706:706) (739:739:739)) + (PORT datac (564:564:564) (592:592:592)) + (PORT datad (866:866:866) (869:869:869)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1362:1362:1362)) + (PORT asdata (1163:1163:1163) (1162:1162:1162)) + (PORT ena (1104:1104:1104) (1087:1087:1087)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_42\~0) + (DELAY + (ABSOLUTE + (PORT dataa (938:938:938) (992:992:992)) + (PORT datab (702:702:702) (734:734:734)) + (PORT datac (579:579:579) (602:602:602)) + (PORT datad (864:864:864) (868:868:868)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (810:810:810) (835:835:835)) + (PORT datab (221:221:221) (290:290:290)) + (PORT datad (619:619:619) (646:646:646)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~15) + (DELAY + (ABSOLUTE + (PORT dataa (191:191:191) (230:230:230)) + (PORT datab (605:605:605) (605:605:605)) + (PORT datac (961:961:961) (932:932:932)) + (PORT datad (166:166:166) (190:190:190)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1035:1035:1035) (1002:1002:1002)) + (PORT datab (1333:1333:1333) (1309:1309:1309)) + (PORT datac (324:324:324) (337:337:337)) + (PORT datad (159:159:159) (181:181:181)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_83) + (DELAY + (ABSOLUTE + (PORT dataa (907:907:907) (921:921:921)) + (PORT datac (1049:1049:1049) (1038:1038:1038)) + (PORT datad (809:809:809) (822:822:822)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1344:1344:1344) (1361:1361:1361)) + (PORT asdata (1430:1430:1430) (1428:1428:1428)) + (PORT ena (1175:1175:1175) (1148:1148:1148)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_82) + (DELAY + (ABSOLUTE + (PORT dataa (906:906:906) (920:920:920)) + (PORT datac (1046:1046:1046) (1038:1038:1038)) + (PORT datad (806:806:806) (823:823:823)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~37) + (DELAY + (ABSOLUTE + (PORT datab (582:582:582) (585:585:585)) + (PORT datad (857:857:857) (855:855:855)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_66\~0) + (DELAY + (ABSOLUTE + (PORT dataa (613:613:613) (633:633:633)) + (PORT datab (880:880:880) (919:919:919)) + (PORT datac (847:847:847) (850:850:850)) + (PORT datad (667:667:667) (696:696:696)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_iy\~2) + (DELAY + (ABSOLUTE + (PORT dataa (443:443:443) (514:514:514)) + (PORT datab (452:452:452) (522:522:522)) + (PORT datac (787:787:787) (779:779:779)) + (PORT datad (846:846:846) (849:849:849)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_71) + (DELAY + (ABSOLUTE + (PORT datab (995:995:995) (1001:1001:1001)) + (PORT datac (761:761:761) (763:763:763)) + (PORT datad (1062:1062:1062) (1067:1067:1067)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1360:1360:1360)) + (PORT asdata (1184:1184:1184) (1187:1187:1187)) + (PORT ena (716:716:716) (714:714:714)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_67\~0) + (DELAY + (ABSOLUTE + (PORT dataa (593:593:593) (620:620:620)) + (PORT datab (691:691:691) (724:724:724)) + (PORT datac (849:849:849) (851:851:851)) + (PORT datad (853:853:853) (886:886:886)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1360:1360:1360)) + (PORT asdata (1183:1183:1183) (1187:1187:1187)) + (PORT ena (1177:1177:1177) (1173:1173:1173)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_70) + (DELAY + (ABSOLUTE + (PORT datab (995:995:995) (1000:1000:1000)) + (PORT datac (761:761:761) (763:763:763)) + (PORT datad (1062:1062:1062) (1066:1066:1066)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (616:616:616) (659:659:659)) + (PORT datab (219:219:219) (287:287:287)) + (PORT datad (212:212:212) (245:245:245)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla37pla28M2T3_4) + (DELAY + (ABSOLUTE + (PORT dataa (1150:1150:1150) (1172:1172:1172)) + (PORT datab (1931:1931:1931) (1987:1987:1987)) + (PORT datac (1558:1558:1558) (1542:1542:1542)) + (PORT datad (626:626:626) (642:642:642)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1019:1019:1019) (1008:1008:1008)) + (PORT datab (1831:1831:1831) (1845:1845:1845)) + (PORT datac (1611:1611:1611) (1636:1636:1636)) + (PORT datad (532:532:532) (517:517:517)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~10) + (DELAY + (ABSOLUTE + (PORT dataa (958:958:958) (991:991:991)) + (PORT datac (516:516:516) (508:508:508)) + (PORT datad (294:294:294) (302:302:302)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_lo\~8) + (DELAY + (ABSOLUTE + (PORT dataa (985:985:985) (956:956:956)) + (PORT datab (1081:1081:1081) (1058:1058:1058)) + (PORT datac (829:829:829) (843:843:843)) + (PORT datad (165:165:165) (191:191:191)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (177:177:177) (198:198:198)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1946:1946:1946) (2029:2029:2029)) + (PORT datab (919:919:919) (1008:1008:1008)) + (PORT datac (1659:1659:1659) (1687:1687:1687)) + (PORT datad (812:812:812) (816:816:816)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~5) + (DELAY + (ABSOLUTE + (PORT dataa (862:862:862) (874:874:874)) + (PORT datab (360:360:360) (361:361:361)) + (PORT datac (574:574:574) (596:596:596)) + (PORT datad (580:580:580) (578:578:578)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~6) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (347:347:347)) + (PORT datab (770:770:770) (827:827:827)) + (PORT datac (776:776:776) (762:762:762)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_79\~0) + (DELAY + (ABSOLUTE + (PORT dataa (807:807:807) (798:798:798)) + (PORT datab (706:706:706) (737:737:737)) + (PORT datac (563:563:563) (592:592:592)) + (PORT datad (866:866:866) (872:872:872)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1360:1360:1360)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1321:1321:1321) (1324:1324:1324)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_1d\~5) + (DELAY + (ABSOLUTE + (PORT dataa (811:811:811) (811:811:811)) + (PORT datab (687:687:687) (747:747:747)) + (PORT datac (1099:1099:1099) (1089:1089:1089)) + (PORT datad (178:178:178) (200:200:200)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_im_we) + (DELAY + (ABSOLUTE + (PORT dataa (1885:1885:1885) (1928:1928:1928)) + (PORT datab (1702:1702:1702) (1750:1750:1750)) + (PORT datac (1744:1744:1744) (1764:1764:1764)) + (PORT datad (1557:1557:1557) (1572:1572:1572)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_1d\~6) + (DELAY + (ABSOLUTE + (PORT dataa (575:575:575) (592:592:592)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (787:787:787) (790:790:790)) + (PORT datad (583:583:583) (594:594:594)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_1d\~7) + (DELAY + (ABSOLUTE + (PORT dataa (797:797:797) (811:811:811)) + (PORT datab (1273:1273:1273) (1229:1229:1229)) + (PORT datac (577:577:577) (616:616:616)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_ds\[2\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (770:770:770) (771:771:771)) + (PORT datab (1035:1035:1035) (1037:1037:1037)) + (PORT datac (598:598:598) (610:610:610)) + (PORT datad (1126:1126:1126) (1115:1115:1115)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[2\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (795:795:795) (792:792:792)) + (PORT datab (345:345:345) (364:364:364)) + (PORT datac (374:374:374) (396:396:396)) + (PORT datad (161:161:161) (182:182:182)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~11) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (237:237:237)) + (PORT datab (605:605:605) (602:602:602)) + (PORT datac (833:833:833) (822:822:822)) + (PORT datad (1840:1840:1840) (1866:1866:1866)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~12) + (DELAY + (ABSOLUTE + (PORT dataa (190:190:190) (229:229:229)) + (PORT datab (1389:1389:1389) (1428:1428:1428)) + (PORT datac (773:773:773) (771:771:771)) + (PORT datad (172:172:172) (198:198:198)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (1190:1190:1190) (1187:1187:1187)) + (PORT datab (1335:1335:1335) (1334:1334:1334)) + (PORT datac (1523:1523:1523) (1530:1530:1530)) + (PORT datad (333:333:333) (356:356:356)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (614:614:614) (623:623:623)) + (PORT datab (1073:1073:1073) (1076:1076:1076)) + (PORT datac (608:608:608) (633:633:633)) + (PORT datad (1028:1028:1028) (1028:1028:1028)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (990:990:990) (1026:1026:1026)) + (PORT datab (882:882:882) (896:896:896)) + (PORT datac (567:567:567) (557:557:557)) + (PORT datad (862:862:862) (901:901:901)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (218:218:218)) + (PORT datab (622:622:622) (661:661:661)) + (PORT datac (158:158:158) (189:189:189)) + (PORT datad (561:561:561) (549:549:549)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~41) + (DELAY + (ABSOLUTE + (PORT dataa (328:328:328) (346:346:346)) + (PORT datab (1013:1013:1013) (1001:1001:1001)) + (PORT datac (811:811:811) (805:805:805)) + (PORT datad (543:543:543) (538:538:538)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~43) + (DELAY + (ABSOLUTE + (PORT dataa (184:184:184) (221:221:221)) + (PORT datab (615:615:615) (633:633:633)) + (PORT datac (154:154:154) (184:184:184)) + (PORT datad (165:165:165) (187:187:187)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_68\~2) + (DELAY + (ABSOLUTE + (PORT datac (1714:1714:1714) (1750:1750:1750)) + (PORT datad (1628:1628:1628) (1640:1640:1640)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_64\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1106:1106:1106) (1101:1101:1101)) + (PORT datab (557:557:557) (553:553:553)) + (PORT datac (876:876:876) (909:909:909)) + (PORT datad (592:592:592) (587:587:587)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_76\~0) + (DELAY + (ABSOLUTE + (PORT dataa (879:879:879) (884:884:884)) + (PORT datab (689:689:689) (724:724:724)) + (PORT datac (768:768:768) (758:758:758)) + (PORT datad (607:607:607) (608:608:608)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_68) + (DELAY + (ABSOLUTE + (PORT datab (976:976:976) (958:958:958)) + (PORT datac (1715:1715:1715) (1752:1752:1752)) + (PORT datad (1630:1630:1630) (1642:1642:1642)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_40\~0) + (DELAY + (ABSOLUTE + (PORT dataa (641:641:641) (672:672:672)) + (PORT datab (1372:1372:1372) (1331:1331:1331)) + (PORT datac (816:816:816) (793:793:793)) + (PORT datad (581:581:581) (570:570:570)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_36\~0) + (DELAY + (ABSOLUTE + (PORT dataa (936:936:936) (987:987:987)) + (PORT datab (707:707:707) (736:736:736)) + (PORT datac (847:847:847) (850:850:850)) + (PORT datad (607:607:607) (608:608:608)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~18) (DELAY (ABSOLUTE - (PORT dataa (987:987:987) (1001:1001:1001)) - (PORT datab (778:778:778) (771:771:771)) - (PORT datac (192:192:192) (237:237:237)) + (PORT dataa (637:637:637) (655:655:655)) + (PORT datab (321:321:321) (342:342:342)) + (PORT datac (564:564:564) (565:565:565)) (IOPATH dataa combout (318:318:318) (307:307:307)) (IOPATH datab combout (319:319:319) (307:307:307)) (IOPATH datac combout (220:220:220) (216:216:216)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_80) + (DELAY + (ABSOLUTE + (PORT datab (852:852:852) (877:877:877)) + (PORT datac (1020:1020:1020) (999:999:999)) + (PORT datad (865:865:865) (882:882:882)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal21\~2) + (DELAY + (ABSOLUTE + (PORT dataa (211:211:211) (264:264:264)) + (PORT datab (814:814:814) (827:827:827)) + (PORT datad (1261:1261:1261) (1345:1345:1345)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|bank_af\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1099:1099:1099) (1091:1091:1091)) + (PORT datab (1352:1352:1352) (1331:1331:1331)) + (PORT datad (306:306:306) (300:300:300)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_control_\|bank_af) + (DELAY + (ABSOLUTE + (PORT clk (1336:1336:1336) (1354:1354:1354)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1380:1380:1380) (1352:1352:1352)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_af\~0) + (DELAY + (ABSOLUTE + (PORT dataa (805:805:805) (795:795:795)) + (PORT datab (891:891:891) (901:901:901)) + (PORT datac (1211:1211:1211) (1322:1322:1322)) + (PORT datad (654:654:654) (685:685:685)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_af2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (805:805:805) (801:801:801)) + (PORT datab (893:893:893) (908:908:908)) + (PORT datac (1211:1211:1211) (1325:1325:1325)) + (PORT datad (665:665:665) (696:696:696)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_28) + (DELAY + (ABSOLUTE + (PORT dataa (1749:1749:1749) (1780:1780:1780)) + (PORT datac (569:569:569) (581:581:581)) + (PORT datad (1620:1620:1620) (1634:1634:1634)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (623:623:623) (637:637:637)) + (PORT datab (545:545:545) (547:547:547)) + (PORT datac (562:562:562) (557:557:557)) + (PORT datad (376:376:376) (398:398:398)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~19) (DELAY (ABSOLUTE - (PORT dataa (605:605:605) (606:606:606)) - (PORT datab (777:777:777) (776:776:776)) - (PORT datac (158:158:158) (189:189:189)) - (PORT datad (811:811:811) (817:817:817)) + (PORT dataa (349:349:349) (360:360:360)) + (PORT datab (622:622:622) (621:621:621)) + (PORT datac (294:294:294) (300:300:300)) + (PORT datad (159:159:159) (180:180:180)) (IOPATH dataa combout (318:318:318) (307:307:307)) (IOPATH datab combout (319:319:319) (307:307:307)) (IOPATH datac combout (220:220:220) (215:215:215)) @@ -16581,14 +14377,70 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_52) + (DELAY + (ABSOLUTE + (PORT dataa (1038:1038:1038) (1038:1038:1038)) + (PORT datac (1294:1294:1294) (1290:1290:1290)) + (PORT datad (768:768:768) (748:748:748)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_44) + (DELAY + (ABSOLUTE + (PORT dataa (1682:1682:1682) (1695:1695:1695)) + (PORT datac (1720:1720:1720) (1759:1759:1759)) + (PORT datad (1039:1039:1039) (1013:1013:1013)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_48) + (DELAY + (ABSOLUTE + (PORT dataa (1683:1683:1683) (1696:1696:1696)) + (PORT datac (1720:1720:1720) (1760:1760:1760)) + (PORT datad (1021:1021:1021) (985:985:985)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_56) + (DELAY + (ABSOLUTE + (PORT dataa (1679:1679:1679) (1694:1694:1694)) + (PORT datac (1718:1718:1718) (1757:1757:1757)) + (PORT datad (1014:1014:1014) (981:981:981)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~16) (DELAY (ABSOLUTE - (PORT dataa (201:201:201) (239:239:239)) - (PORT datab (200:200:200) (234:234:234)) - (PORT datac (176:176:176) (208:208:208)) + (PORT dataa (832:832:832) (817:817:817)) + (PORT datab (202:202:202) (236:236:236)) + (PORT datac (177:177:177) (209:209:209)) (PORT datad (178:178:178) (201:201:201)) (IOPATH dataa combout (318:318:318) (307:307:307)) (IOPATH datab combout (319:319:319) (307:307:307)) @@ -16602,10 +14454,10 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~20) (DELAY (ABSOLUTE - (PORT dataa (1448:1448:1448) (1385:1385:1385)) - (PORT datab (782:782:782) (820:820:820)) - (PORT datac (1049:1049:1049) (1030:1030:1030)) - (PORT datad (159:159:159) (179:179:179)) + (PORT dataa (1082:1082:1082) (1105:1105:1105)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (534:534:534) (518:518:518)) + (PORT datad (1049:1049:1049) (1028:1028:1028)) (IOPATH dataa combout (318:318:318) (307:307:307)) (IOPATH datab combout (319:319:319) (307:307:307)) (IOPATH datac combout (220:220:220) (215:215:215)) @@ -16615,368 +14467,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_73) + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_69\~2) (DELAY (ABSOLUTE - (PORT dataa (1211:1211:1211) (1259:1259:1259)) - (PORT datac (1051:1051:1051) (1039:1039:1039)) - (PORT datad (774:774:774) (762:762:762)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1364:1364:1364)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1196:1196:1196) (1178:1178:1178)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT asdata (1080:1080:1080) (1105:1105:1105)) - (PORT ena (906:906:906) (905:905:905)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT asdata (1079:1079:1079) (1103:1103:1103)) - (PORT ena (893:893:893) (877:877:877)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (425:425:425) (478:478:478)) - (PORT datab (451:451:451) (487:487:487)) - (PORT datad (197:197:197) (254:254:254)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1346:1346:1346) (1363:1363:1363)) - (PORT asdata (1792:1792:1792) (1799:1799:1799)) - (PORT ena (720:720:720) (722:722:722)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (870:870:870) (892:892:892)) - (PORT datab (1114:1114:1114) (1155:1155:1155)) - (PORT datad (821:821:821) (832:832:832)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1355:1355:1355) (1376:1376:1376)) - (PORT asdata (493:493:493) (524:524:524)) - (PORT ena (1347:1347:1347) (1329:1329:1329)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1361:1361:1361)) - (PORT asdata (1574:1574:1574) (1581:1581:1581)) - (PORT ena (1164:1164:1164) (1167:1167:1167)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1018:1018:1018) (1013:1013:1013)) - (PORT datab (603:603:603) (645:645:645)) - (PORT datad (779:779:779) (797:797:797)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1343:1343:1343) (1360:1360:1360)) - (PORT asdata (2031:2031:2031) (2021:2021:2021)) - (PORT ena (716:716:716) (714:714:714)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (787:787:787) (778:778:778)) - (PORT datab (1073:1073:1073) (1082:1082:1082)) - (PORT datad (219:219:219) (253:253:253)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1362:1362:1362)) - (PORT asdata (1819:1819:1819) (1793:1793:1793)) - (PORT ena (1093:1093:1093) (1070:1070:1070)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1362:1362:1362)) - (PORT asdata (1820:1820:1820) (1797:1797:1797)) - (PORT ena (1173:1173:1173) (1169:1169:1169)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (364:364:364) (414:414:414)) - (PORT datab (1473:1473:1473) (1469:1469:1469)) - (PORT datad (1097:1097:1097) (1083:1083:1083)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1361:1361:1361)) - (PORT asdata (1573:1573:1573) (1580:1580:1580)) - (PORT ena (1039:1039:1039) (993:993:993)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1482:1482:1482) (1473:1473:1473)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1361:1361:1361)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (716:716:716) (714:714:714)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (362:362:362) (391:391:391)) - (PORT datab (812:812:812) (837:837:837)) - (PORT datad (800:800:800) (823:823:823)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (217:217:217)) - (PORT datab (591:591:591) (579:579:579)) - (PORT datac (311:311:311) (318:318:318)) - (PORT datad (158:158:158) (180:180:180)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1346:1346:1346) (1363:1363:1363)) - (PORT asdata (2181:2181:2181) (2175:2175:2175)) - (PORT ena (1271:1271:1271) (1296:1296:1296)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1346:1346:1346) (1363:1363:1363)) - (PORT asdata (2180:2180:2180) (2174:2174:2174)) - (PORT ena (1281:1281:1281) (1292:1292:1292)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (829:829:829) (889:889:889)) - (PORT datab (826:826:826) (890:890:890)) - (PORT datad (198:198:198) (254:254:254)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (604:604:604) (602:602:602)) - (PORT datab (180:180:180) (212:212:212)) - (PORT datac (559:559:559) (557:557:557)) - (PORT datad (296:296:296) (289:289:289)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) + (PORT datac (1710:1710:1710) (1746:1746:1746)) + (PORT datad (1622:1622:1622) (1637:1637:1637)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -16984,803 +14479,28 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~21) + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_65\~0) (DELAY (ABSOLUTE - (PORT dataa (814:814:814) (859:859:859)) - (PORT datab (507:507:507) (508:508:508)) - (PORT datac (969:969:969) (991:991:991)) - (PORT datad (1211:1211:1211) (1199:1199:1199)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_60) - (DELAY - (ABSOLUTE - (PORT dataa (799:799:799) (807:807:807)) - (PORT datac (1048:1048:1048) (1033:1033:1033)) - (PORT datad (786:786:786) (789:789:789)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_61) - (DELAY - (ABSOLUTE - (PORT dataa (798:798:798) (805:805:805)) - (PORT datac (1051:1051:1051) (1036:1036:1036)) - (PORT datad (787:787:787) (792:792:792)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1355:1355:1355) (1376:1376:1376)) - (PORT asdata (1278:1278:1278) (1296:1296:1296)) - (PORT ena (857:857:857) (835:835:835)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sw_4d_hi\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1093:1093:1093) (1067:1067:1067)) - (PORT datab (777:777:777) (766:766:766)) - (PORT datac (1052:1052:1052) (1034:1034:1034)) - (PORT datad (787:787:787) (789:789:789)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (248:248:248)) - (PORT datab (376:376:376) (397:397:397)) - (PORT datad (358:358:358) (374:374:374)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_72) - (DELAY - (ABSOLUTE - (PORT dataa (1211:1211:1211) (1258:1258:1258)) - (PORT datac (1051:1051:1051) (1036:1036:1036)) - (PORT datad (774:774:774) (762:762:762)) - (IOPATH dataa combout (307:307:307) (306:306:306)) + (PORT dataa (605:605:605) (614:614:614)) + (PORT datab (883:883:883) (923:923:923)) + (PORT datac (847:847:847) (851:851:851)) + (PORT datad (668:668:668) (697:697:697)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (222:222:222) (295:295:295)) - (PORT datac (702:702:702) (733:733:733)) - (PORT datad (596:596:596) (596:596:596)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (218:218:218) (265:265:265)) - (PORT datab (212:212:212) (250:250:250)) - (PORT datac (1025:1025:1025) (991:991:991)) - (PORT datad (194:194:194) (224:224:224)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|d1_out) - (DELAY - (ABSOLUTE - (PORT dataa (392:392:392) (452:452:452)) - (PORT datab (251:251:251) (325:325:325)) - (PORT datac (1235:1235:1235) (1184:1184:1184)) - (PORT datad (169:169:169) (195:195:195)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1355:1355:1355) (1376:1376:1376)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (765:765:765) (779:779:779)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1346:1346:1346) (1363:1363:1363)) - (PORT asdata (877:877:877) (870:870:870)) - (PORT ena (1271:1271:1271) (1296:1296:1296)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1346:1346:1346) (1363:1363:1363)) - (PORT asdata (876:876:876) (869:869:869)) - (PORT ena (1281:1281:1281) (1292:1292:1292)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (826:826:826) (882:882:882)) - (PORT datab (829:829:829) (893:893:893)) - (PORT datad (195:195:195) (252:252:252)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT asdata (1273:1273:1273) (1283:1283:1283)) - (PORT ena (906:906:906) (905:905:905)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT asdata (1270:1270:1270) (1280:1280:1280)) - (PORT ena (893:893:893) (877:877:877)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (426:426:426) (471:471:471)) - (PORT datab (454:454:454) (482:482:482)) - (PORT datad (198:198:198) (255:255:255)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1362:1362:1362)) - (PORT asdata (1169:1169:1169) (1176:1176:1176)) - (PORT ena (1173:1173:1173) (1169:1169:1169)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1362:1362:1362)) - (PORT asdata (1169:1169:1169) (1174:1174:1174)) - (PORT ena (1093:1093:1093) (1070:1070:1070)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (360:360:360) (403:403:403)) - (PORT datab (1479:1479:1479) (1472:1472:1472)) - (PORT datad (1098:1098:1098) (1082:1082:1082)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1343:1343:1343) (1360:1360:1360)) - (PORT asdata (1130:1130:1130) (1150:1150:1150)) - (PORT ena (716:716:716) (714:714:714)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (980:980:980) (950:950:950)) - (PORT datab (1074:1074:1074) (1080:1080:1080)) - (PORT datad (217:217:217) (250:250:250)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (747:747:747) (778:778:778)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1361:1361:1361)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1118:1118:1118) (1094:1094:1094)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1361:1361:1361)) - (PORT asdata (1154:1154:1154) (1178:1178:1178)) - (PORT ena (716:716:716) (714:714:714)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (222:222:222) (295:295:295)) - (PORT datab (217:217:217) (259:259:259)) - (PORT datad (812:812:812) (819:819:819)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1338:1338:1338) (1355:1355:1355)) - (PORT asdata (631:631:631) (635:635:635)) - (PORT ena (1298:1298:1298) (1265:1265:1265)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1338:1338:1338) (1355:1355:1355)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1357:1357:1357) (1333:1333:1333)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (981:981:981) (954:954:954)) - (PORT datab (1176:1176:1176) (1200:1200:1200)) - (PORT datad (197:197:197) (254:254:254)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (782:782:782) (766:766:766)) - (PORT datab (952:952:952) (970:970:970)) - (PORT datac (745:745:745) (771:771:771)) - (PORT datad (159:159:159) (178:178:178)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1346:1346:1346) (1363:1363:1363)) - (PORT asdata (887:887:887) (875:875:875)) - (PORT ena (720:720:720) (722:722:722)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[0\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (861:861:861) (887:887:887)) - (PORT datab (1114:1114:1114) (1151:1151:1151)) - (PORT datad (833:833:833) (842:842:842)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (355:355:355) (381:381:381)) - (PORT datab (768:768:768) (789:789:789)) - (PORT datac (154:154:154) (184:184:184)) - (PORT datad (522:522:522) (514:514:514)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (781:781:781) (779:779:779)) - (PORT datab (813:813:813) (808:808:808)) - (PORT datac (750:750:750) (780:780:780)) - (PORT datad (157:157:157) (178:178:178)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1355:1355:1355) (1376:1376:1376)) - (PORT asdata (815:815:815) (794:794:794)) - (PORT ena (862:862:862) (838:838:838)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (217:217:217) (259:259:259)) - (PORT datab (839:839:839) (848:848:848)) - (PORT datad (189:189:189) (221:221:221)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (216:216:216) (261:261:261)) - (PORT datac (194:194:194) (260:260:260)) - (PORT datad (158:158:158) (178:178:178)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1062:1062:1062) (1027:1027:1027)) - (PORT datab (767:767:767) (747:747:747)) - (PORT datac (179:179:179) (212:212:212)) - (PORT datad (157:157:157) (177:177:177)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[8\]) - (DELAY - (ABSOLUTE - (PORT dataa (636:636:636) (656:656:656)) - (PORT datac (742:742:742) (728:728:728)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[8\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1400:1400:1400) (1370:1370:1370)) - (PORT ena (1981:1981:1981) (2010:2010:2010)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|carry_borrow_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (396:396:396) (458:458:458)) - (PORT datab (252:252:252) (329:329:329)) - (PORT datac (1232:1232:1232) (1182:1182:1182)) - (PORT datad (173:173:173) (200:200:200)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|d0_out) - (DELAY - (ABSOLUTE - (PORT datac (220:220:220) (301:301:301)) - (PORT datad (302:302:302) (312:312:312)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (219:219:219)) - (PORT datab (659:659:659) (668:668:668)) - (PORT datac (759:759:759) (753:753:753)) - (PORT datad (542:542:542) (535:535:535)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[9\]) - (DELAY - (ABSOLUTE - (PORT datab (337:337:337) (345:345:345)) - (PORT datac (817:817:817) (816:816:816)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|Q\[9\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (512:512:512) (503:503:503)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[9\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1363:1363:1363)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1400:1400:1400) (1370:1370:1370)) - (PORT ena (1924:1924:1924) (1928:1928:1928)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|d1_out) - (DELAY - (ABSOLUTE - (PORT dataa (243:243:243) (325:325:325)) - (PORT datab (250:250:250) (331:331:331)) - (PORT datac (1244:1244:1244) (1192:1192:1192)) - (PORT datad (303:303:303) (309:309:309)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1346:1346:1346) (1363:1363:1363)) - (PORT asdata (1010:1010:1010) (1030:1030:1030)) - (PORT ena (1271:1271:1271) (1296:1296:1296)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1346:1346:1346) (1363:1363:1363)) - (PORT asdata (1011:1011:1011) (1031:1031:1031)) - (PORT ena (1281:1281:1281) (1292:1292:1292)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (827:827:827) (884:884:884)) - (PORT datab (828:828:828) (886:886:886)) - (PORT datad (197:197:197) (252:252:252)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1343:1343:1343) (1360:1360:1360)) - (PORT asdata (1776:1776:1776) (1820:1820:1820)) - (PORT ena (716:716:716) (714:714:714)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (757:757:757) (743:743:743)) - (PORT datab (1075:1075:1075) (1081:1081:1081)) - (PORT datad (220:220:220) (254:254:254)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[2\]) (DELAY (ABSOLUTE - (PORT clk (1344:1344:1344) (1361:1361:1361)) - (PORT asdata (1312:1312:1312) (1376:1376:1376)) - (PORT ena (1039:1039:1039) (993:993:993)) + (PORT clk (1341:1341:1341) (1359:1359:1359)) + (PORT asdata (1404:1404:1404) (1390:1390:1390)) + (PORT ena (1132:1132:1132) (1121:1121:1121)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -17791,10 +14511,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[2\]\~feeder) + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_69) (DELAY (ABSOLUTE - (PORT datad (714:714:714) (768:768:768)) + (PORT datab (976:976:976) (957:957:957)) + (PORT datac (1711:1711:1711) (1749:1749:1749)) + (PORT datad (1624:1624:1624) (1640:1640:1640)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -17804,66 +14528,9 @@ (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[2\]) (DELAY (ABSOLUTE - (PORT clk (1344:1344:1344) (1361:1361:1361)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (716:716:716) (714:714:714)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (362:362:362) (390:390:390)) - (PORT datab (812:812:812) (837:837:837)) - (PORT datad (325:325:325) (363:363:363)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (927:927:927) (951:951:951)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1362:1362:1362)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1093:1093:1093) (1070:1070:1070)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1362:1362:1362)) - (PORT asdata (1824:1824:1824) (1865:1865:1865)) - (PORT ena (1173:1173:1173) (1169:1169:1169)) + (PORT clk (1341:1341:1341) (1359:1359:1359)) + (PORT asdata (1407:1407:1407) (1394:1394:1394)) + (PORT ena (1076:1076:1076) (1031:1031:1031)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -17874,27 +14541,43 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~33) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~34) (DELAY (ABSOLUTE - (PORT dataa (529:529:529) (565:565:565)) - (PORT datab (1478:1478:1478) (1476:1476:1476)) - (PORT datad (1096:1096:1096) (1087:1087:1087)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) + (PORT dataa (634:634:634) (645:645:645)) + (PORT datab (234:234:234) (291:291:291)) + (PORT datad (198:198:198) (255:255:255)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_77\~0) + (DELAY + (ABSOLUTE + (PORT dataa (606:606:606) (615:615:615)) + (PORT datab (710:710:710) (736:736:736)) + (PORT datac (771:771:771) (766:766:766)) + (PORT datad (869:869:869) (873:873:873)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[2\]) (DELAY (ABSOLUTE - (PORT clk (1355:1355:1355) (1376:1376:1376)) + (PORT clk (1340:1340:1340) (1358:1358:1358)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (1347:1347:1347) (1329:1329:1329)) + (PORT ena (1376:1376:1376) (1350:1350:1350)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -17903,14 +14586,28 @@ (HOLD ena (posedge clk) (144:144:144)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_81) + (DELAY + (ABSOLUTE + (PORT datab (854:854:854) (879:879:879)) + (PORT datac (1022:1022:1022) (1000:1000:1000)) + (PORT datad (866:866:866) (883:883:883)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[2\]) (DELAY (ABSOLUTE - (PORT clk (1344:1344:1344) (1361:1361:1361)) - (PORT asdata (1312:1312:1312) (1374:1374:1374)) - (PORT ena (1164:1164:1164) (1167:1167:1167)) + (PORT clk (1340:1340:1340) (1358:1358:1358)) + (PORT asdata (1563:1563:1563) (1523:1523:1523)) + (PORT ena (1131:1131:1131) (1124:1124:1124)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -17924,9 +14621,54 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~36) (DELAY (ABSOLUTE - (PORT dataa (1020:1020:1020) (1009:1009:1009)) - (PORT datab (628:628:628) (666:666:666)) - (PORT datad (783:783:783) (799:799:799)) + (PORT dataa (649:649:649) (696:696:696)) + (PORT datab (221:221:221) (288:288:288)) + (PORT datad (645:645:645) (658:658:658)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_29) + (DELAY + (ABSOLUTE + (PORT dataa (1758:1758:1758) (1794:1794:1794)) + (PORT datac (571:571:571) (585:585:585)) + (PORT datad (1632:1632:1632) (1647:1647:1647)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1340:1340:1340) (1358:1358:1358)) + (PORT asdata (1104:1104:1104) (1084:1084:1084)) + (PORT ena (1109:1109:1109) (1079:1079:1079)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (1084:1084:1084) (1111:1111:1111)) + (PORT datab (839:839:839) (829:829:829)) + (PORT datad (377:377:377) (392:392:392)) (IOPATH dataa combout (309:309:309) (326:326:326)) (IOPATH datab combout (306:306:306) (324:324:324)) (IOPATH datac combout (312:312:312) (325:325:325)) @@ -17934,15 +14676,94 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_37\~0) + (DELAY + (ABSOLUTE + (PORT dataa (942:942:942) (994:994:994)) + (PORT datab (697:697:697) (729:729:729)) + (PORT datac (848:848:848) (851:851:851)) + (PORT datad (582:582:582) (579:579:579)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1356:1356:1356)) + (PORT asdata (1237:1237:1237) (1271:1271:1271)) + (PORT ena (1126:1126:1126) (1110:1110:1110)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_41\~0) + (DELAY + (ABSOLUTE + (PORT dataa (942:942:942) (995:995:995)) + (PORT datab (699:699:699) (730:730:730)) + (PORT datac (849:849:849) (852:852:852)) + (PORT datad (580:580:580) (583:583:583)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1356:1356:1356)) + (PORT asdata (1235:1235:1235) (1269:1269:1269)) + (PORT ena (1322:1322:1322) (1264:1264:1264)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (647:647:647) (684:684:684)) + (PORT datab (599:599:599) (600:600:600)) + (PORT datad (198:198:198) (255:255:255)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~37) (DELAY (ABSOLUTE - (PORT dataa (592:592:592) (582:582:582)) - (PORT datab (181:181:181) (213:213:213)) - (PORT datac (552:552:552) (555:555:555)) - (PORT datad (160:160:160) (182:182:182)) + (PORT dataa (561:561:561) (566:566:566)) + (PORT datab (590:590:590) (586:586:586)) + (PORT datac (566:566:566) (580:580:580)) + (PORT datad (925:925:925) (927:927:927)) (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) @@ -17950,35 +14771,73 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_45) + (DELAY + (ABSOLUTE + (PORT dataa (1386:1386:1386) (1423:1423:1423)) + (PORT datab (1999:1999:1999) (1989:1989:1989)) + (PORT datad (1295:1295:1295) (1252:1252:1252)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1356:1356:1356)) + (PORT asdata (886:886:886) (889:889:889)) + (PORT ena (898:898:898) (891:891:891)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (519:519:519) (522:522:522)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_49) + (DELAY + (ABSOLUTE + (PORT dataa (1681:1681:1681) (1695:1695:1695)) + (PORT datac (1719:1719:1719) (1758:1758:1758)) + (PORT datad (1021:1021:1021) (983:983:983)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[2\]) (DELAY (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT asdata (1994:1994:1994) (2056:2056:2056)) - (PORT ena (893:893:893) (877:877:877)) + (PORT clk (1338:1338:1338) (1356:1356:1356)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1093:1093:1093) (1055:1055:1055)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT asdata (1995:1995:1995) (2060:2060:2060)) - (PORT ena (906:906:906) (905:905:905)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) + (HOLD d (posedge clk) (144:144:144)) (HOLD ena (posedge clk) (144:144:144)) ) ) @@ -17987,24 +14846,38 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~31) (DELAY (ABSOLUTE - (PORT dataa (428:428:428) (478:478:478)) - (PORT datab (222:222:222) (291:291:291)) - (PORT datad (413:413:413) (447:447:447)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) + (PORT dataa (628:628:628) (643:643:643)) + (PORT datab (634:634:634) (644:644:644)) + (PORT datad (198:198:198) (255:255:255)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_33) + (DELAY + (ABSOLUTE + (PORT dataa (1384:1384:1384) (1415:1415:1415)) + (PORT datab (2004:2004:2004) (1998:1998:1998)) + (PORT datad (1256:1256:1256) (1219:1219:1219)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[2\]) (DELAY (ABSOLUTE - (PORT clk (1346:1346:1346) (1363:1363:1363)) - (PORT asdata (2016:2016:2016) (2070:2070:2070)) - (PORT ena (720:720:720) (722:722:722)) + (PORT clk (1339:1339:1339) (1357:1357:1357)) + (PORT asdata (836:836:836) (829:829:829)) + (PORT ena (716:716:716) (714:714:714)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -18015,12 +14888,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[2\]\~17) + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[2\]\~12) (DELAY (ABSOLUTE - (PORT dataa (858:858:858) (891:891:891)) - (PORT datab (1113:1113:1113) (1148:1148:1148)) - (PORT datad (831:831:831) (837:837:837)) + (PORT dataa (1388:1388:1388) (1422:1422:1422)) + (PORT datab (1995:1995:1995) (1987:1987:1987)) + (PORT datad (1259:1259:1259) (1223:1223:1223)) (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (312:312:312) (325:325:325)) @@ -18028,15 +14901,90 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_57) + (DELAY + (ABSOLUTE + (PORT dataa (1682:1682:1682) (1695:1695:1695)) + (PORT datac (1720:1720:1720) (1759:1759:1759)) + (PORT datad (1014:1014:1014) (979:979:979)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1356:1356:1356)) + (PORT asdata (1112:1112:1112) (1093:1093:1093)) + (PORT ena (1132:1132:1132) (1119:1119:1119)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_53) + (DELAY + (ABSOLUTE + (PORT dataa (1038:1038:1038) (1038:1038:1038)) + (PORT datac (1294:1294:1294) (1290:1290:1290)) + (PORT datad (768:768:768) (748:748:748)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1356:1356:1356)) + (PORT asdata (1111:1111:1111) (1090:1090:1090)) + (PORT ena (744:744:744) (751:751:751)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (659:659:659) (686:686:686)) + (PORT datab (221:221:221) (289:289:289)) + (PORT datad (206:206:206) (239:239:239)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~38) (DELAY (ABSOLUTE - (PORT dataa (716:716:716) (753:753:753)) - (PORT datab (524:524:524) (527:527:527)) - (PORT datac (521:521:521) (502:502:502)) - (PORT datad (787:787:787) (800:800:800)) + (PORT dataa (311:311:311) (331:331:331)) + (PORT datab (579:579:579) (584:584:584)) + (PORT datac (313:313:313) (320:320:320)) + (PORT datad (297:297:297) (297:297:297)) (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) @@ -18046,92 +14994,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~39) + (INSTANCE z80_\|execute_\|ctl_inc_dec\~11) (DELAY (ABSOLUTE - (PORT dataa (769:769:769) (825:825:825)) - (PORT datab (372:372:372) (373:373:373)) - (PORT datac (786:786:786) (830:830:830)) - (PORT datad (1209:1209:1209) (1198:1198:1198)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1355:1355:1355) (1376:1376:1376)) - (PORT asdata (492:492:492) (521:521:521)) - (PORT ena (862:862:862) (838:838:838)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1743:1743:1743) (1803:1803:1803)) - (PORT datab (213:213:213) (254:254:254)) - (PORT datad (193:193:193) (223:223:223)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1355:1355:1355) (1376:1376:1376)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (765:765:765) (779:779:779)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (216:216:216) (260:260:260)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datad (334:334:334) (367:367:367)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1066:1066:1066) (1029:1029:1029)) - (PORT datab (517:517:517) (500:500:500)) - (PORT datac (181:181:181) (216:216:216)) - (PORT datad (158:158:158) (178:178:178)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) + (PORT dataa (1214:1214:1214) (1186:1186:1186)) + (PORT datab (1653:1653:1653) (1695:1695:1695)) + (PORT datac (1903:1903:1903) (1913:1913:1913)) + (PORT datad (1663:1663:1663) (1701:1701:1701)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -18139,97 +15010,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[10\]) + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|d0_out) (DELAY (ABSOLUTE - (PORT datac (180:180:180) (213:213:213)) - (PORT datad (805:805:805) (809:809:809)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|Q\[10\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (495:495:495) (485:485:485)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[10\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1363:1363:1363)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1400:1400:1400) (1370:1370:1370)) - (PORT ena (1924:1924:1924) (1928:1928:1928)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|carry_borrow_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (245:245:245) (330:330:330)) - (PORT datab (246:246:246) (327:327:327)) - (PORT datac (1247:1247:1247) (1195:1195:1195)) - (PORT datad (302:302:302) (311:311:311)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[11\]) - (DELAY - (ABSOLUTE - (PORT datab (554:554:554) (576:576:576)) - (PORT datad (852:852:852) (845:845:845)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[11\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1363:1363:1363)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1400:1400:1400) (1370:1370:1370)) - (PORT ena (1924:1924:1924) (1928:1928:1928)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[11\]) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (239:239:239)) - (PORT datac (530:530:530) (559:559:559)) + (PORT dataa (896:896:896) (941:941:941)) + (PORT datac (170:170:170) (209:209:209)) (IOPATH dataa combout (318:318:318) (327:327:327)) (IOPATH datac combout (220:220:220) (216:216:216)) ) @@ -18237,12 +15022,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[3\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[1\]) (DELAY (ABSOLUTE - (PORT clk (1345:1345:1345) (1364:1364:1364)) + (PORT clk (1342:1342:1342) (1359:1359:1359)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (1196:1196:1196) (1178:1178:1178)) + (PORT ena (1154:1154:1154) (1149:1149:1149)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -18252,13 +15037,481 @@ ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[3\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~5) (DELAY (ABSOLUTE - (PORT clk (1355:1355:1355) (1376:1376:1376)) - (PORT asdata (671:671:671) (690:690:690)) - (PORT ena (857:857:857) (835:835:835)) + (PORT dataa (844:844:844) (887:887:887)) + (PORT datab (1435:1435:1435) (1483:1483:1483)) + (PORT datac (1406:1406:1406) (1445:1445:1445)) + (PORT datad (370:370:370) (396:396:396)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~3) + (DELAY + (ABSOLUTE + (PORT dataa (928:928:928) (1000:1000:1000)) + (PORT datab (1124:1124:1124) (1121:1121:1121)) + (PORT datac (1582:1582:1582) (1591:1591:1591)) + (PORT datad (619:619:619) (664:664:664)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~4) + (DELAY + (ABSOLUTE + (PORT dataa (319:319:319) (330:330:330)) + (PORT datab (206:206:206) (244:244:244)) + (PORT datac (632:632:632) (668:668:668)) + (PORT datad (309:309:309) (321:321:321)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1457:1457:1457) (1452:1452:1452)) + (PORT datab (1552:1552:1552) (1568:1568:1568)) + (PORT datac (2260:2260:2260) (2270:2270:2270)) + (PORT datad (1357:1357:1357) (1410:1410:1410)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1107:1107:1107) (1134:1134:1134)) + (PORT datab (1390:1390:1390) (1444:1444:1444)) + (PORT datac (762:762:762) (760:760:760)) + (PORT datad (848:848:848) (860:860:860)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~16) + (DELAY + (ABSOLUTE + (PORT dataa (600:600:600) (595:595:595)) + (PORT datab (860:860:860) (868:868:868)) + (PORT datac (1866:1866:1866) (1878:1878:1878)) + (PORT datad (1174:1174:1174) (1213:1213:1213)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~6) + (DELAY + (ABSOLUTE + (PORT dataa (589:589:589) (618:618:618)) + (PORT datab (183:183:183) (216:216:216)) + (PORT datac (155:155:155) (185:185:185)) + (PORT datad (159:159:159) (179:179:179)) + (IOPATH dataa combout (307:307:307) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~7) + (DELAY + (ABSOLUTE + (PORT dataa (601:601:601) (596:596:596)) + (PORT datab (1390:1390:1390) (1440:1440:1440)) + (PORT datac (192:192:192) (232:232:232)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1933:1933:1933) (1958:1958:1958)) + (PORT datab (1236:1236:1236) (1186:1186:1186)) + (PORT datac (1324:1324:1324) (1388:1388:1388)) + (PORT datad (775:775:775) (783:783:783)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~8) + (DELAY + (ABSOLUTE + (PORT dataa (205:205:205) (252:252:252)) + (PORT datab (814:814:814) (819:819:819)) + (PORT datac (155:155:155) (186:186:186)) + (PORT datad (1735:1735:1735) (1794:1794:1794)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel_nop3pla68M3T1_20) + (DELAY + (ABSOLUTE + (PORT dataa (865:865:865) (916:916:916)) + (PORT datab (902:902:902) (921:921:921)) + (PORT datac (1651:1651:1651) (1715:1715:1715)) + (PORT datad (1538:1538:1538) (1535:1535:1535)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~42) + (DELAY + (ABSOLUTE + (PORT datac (545:545:545) (539:539:539)) + (PORT datad (180:180:180) (216:216:216)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~9) + (DELAY + (ABSOLUTE + (PORT dataa (545:545:545) (552:552:552)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (833:833:833) (832:832:832)) + (PORT datad (189:189:189) (220:220:220)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~5) + (DELAY + (ABSOLUTE + (PORT dataa (593:593:593) (622:622:622)) + (PORT datab (1750:1750:1750) (1757:1757:1757)) + (PORT datac (1048:1048:1048) (1072:1072:1072)) + (PORT datad (1332:1332:1332) (1334:1334:1334)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1987:1987:1987) (2015:2015:2015)) + (PORT datab (898:898:898) (966:966:966)) + (PORT datac (986:986:986) (990:990:990)) + (PORT datad (1022:1022:1022) (1036:1036:1036)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~7) + (DELAY + (ABSOLUTE + (PORT dataa (378:378:378) (394:394:394)) + (PORT datab (180:180:180) (212:212:212)) + (PORT datac (181:181:181) (215:215:215)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1387:1387:1387) (1453:1453:1453)) + (PORT datac (1182:1182:1182) (1214:1214:1214)) + (PORT datad (1753:1753:1753) (1783:1783:1783)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1093:1093:1093) (1108:1108:1108)) + (PORT datab (863:863:863) (886:886:886)) + (PORT datac (1799:1799:1799) (1861:1861:1861)) + (PORT datad (565:565:565) (589:589:589)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (585:585:585) (579:579:579)) + (PORT datab (1017:1017:1017) (1053:1053:1053)) + (PORT datac (756:756:756) (738:738:738)) + (PORT datad (781:781:781) (835:835:835)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~3) + (DELAY + (ABSOLUTE + (PORT dataa (526:526:526) (546:546:546)) + (PORT datab (814:814:814) (859:859:859)) + (PORT datac (727:727:727) (705:705:705)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~2) + (DELAY + (ABSOLUTE + (PORT dataa (383:383:383) (399:399:399)) + (PORT datab (1018:1018:1018) (1050:1050:1050)) + (PORT datac (1965:1965:1965) (1989:1989:1989)) + (PORT datad (751:751:751) (793:793:793)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1047:1047:1047) (1041:1041:1041)) + (PORT datab (1264:1264:1264) (1232:1232:1232)) + (PORT datac (522:522:522) (512:512:512)) + (PORT datad (772:772:772) (761:761:761)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~4) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (217:217:217)) + (PORT datab (180:180:180) (212:212:212)) + (PORT datac (778:778:778) (771:771:771)) + (PORT datad (157:157:157) (178:178:178)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~8) + (DELAY + (ABSOLUTE + (PORT dataa (580:580:580) (594:594:594)) + (PORT datab (201:201:201) (235:235:235)) + (PORT datac (156:156:156) (187:187:187)) + (PORT datad (158:158:158) (179:179:179)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1388:1388:1388) (1453:1453:1453)) + (PORT datab (1792:1792:1792) (1817:1817:1817)) + (PORT datac (1183:1183:1183) (1216:1216:1216)) + (PORT datad (1375:1375:1375) (1382:1382:1382)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~2) + (DELAY + (ABSOLUTE + (PORT datab (574:574:574) (579:579:579)) + (PORT datac (788:788:788) (769:769:769)) + (PORT datad (336:336:336) (334:334:334)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (844:844:844) (868:868:868)) + (PORT datab (1238:1238:1238) (1229:1229:1229)) + (PORT datac (1498:1498:1498) (1542:1542:1542)) + (PORT datad (542:542:542) (544:544:544)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1357:1357:1357)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (716:716:716) (714:714:714)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_32) + (DELAY + (ABSOLUTE + (PORT dataa (1383:1383:1383) (1415:1415:1415)) + (PORT datab (2003:2003:2003) (1998:1998:1998)) + (PORT datad (1255:1255:1255) (1218:1218:1218)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1340:1340:1340) (1358:1358:1358)) + (PORT asdata (655:655:655) (667:667:667)) + (PORT ena (1131:1131:1131) (1124:1124:1124)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1340:1340:1340) (1358:1358:1358)) + (PORT asdata (655:655:655) (667:667:667)) + (PORT ena (1376:1376:1376) (1350:1350:1350)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -18269,14 +15522,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~10) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~81) (DELAY (ABSOLUTE - (PORT dataa (201:201:201) (237:237:237)) - (PORT datab (373:373:373) (393:393:393)) - (PORT datad (364:364:364) (377:377:377)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) + (PORT dataa (643:643:643) (688:688:688)) + (PORT datab (219:219:219) (287:287:287)) + (PORT datad (649:649:649) (665:665:665)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -18284,43 +15537,27 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~11) + (INSTANCE z80_\|alu_\|db_high\[2\]\~8) (DELAY (ABSOLUTE - (PORT dataa (225:225:225) (299:299:299)) - (PORT datac (750:750:750) (785:785:785)) - (PORT datad (594:594:594) (591:591:591)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT datab (806:806:806) (799:799:799)) + (PORT datac (746:746:746) (738:738:738)) + (PORT datad (1089:1089:1089) (1120:1120:1120)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~12) + (INSTANCE z80_\|alu_\|db_high\[2\]\~9) (DELAY (ABSOLUTE - (PORT dataa (532:532:532) (520:520:520)) - (PORT datab (792:792:792) (788:788:788)) - (PORT datac (630:630:630) (643:643:643)) - (PORT datad (161:161:161) (183:183:183)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~48) - (DELAY - (ABSOLUTE - (PORT dataa (567:567:567) (572:572:572)) - (PORT datab (758:758:758) (804:804:804)) - (PORT datac (360:360:360) (384:384:384)) - (PORT datad (1211:1211:1211) (1194:1194:1194)) + (PORT dataa (1015:1015:1015) (991:991:991)) + (PORT datab (644:644:644) (664:664:664)) + (PORT datac (157:157:157) (188:188:188)) + (PORT datad (1175:1175:1175) (1141:1141:1141)) (IOPATH dataa combout (300:300:300) (323:323:323)) (IOPATH datab combout (309:309:309) (328:328:328)) (IOPATH datac combout (218:218:218) (216:216:216)) @@ -18330,15 +15567,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[3\]\~9) + (INSTANCE z80_\|alu_\|db_high\[2\]\~11) (DELAY (ABSOLUTE - (PORT dataa (809:809:809) (834:834:834)) - (PORT datab (200:200:200) (244:244:244)) - (PORT datac (1069:1069:1069) (1087:1087:1087)) - (PORT datad (571:571:571) (569:569:569)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (295:295:295) (300:300:300)) + (PORT datab (247:247:247) (298:298:298)) + (PORT datac (220:220:220) (282:282:282)) + (PORT datad (217:217:217) (269:269:269)) + (IOPATH datab combout (273:273:273) (275:275:275)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -18346,40 +15581,24 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_low) + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[2\]) (DELAY (ABSOLUTE - (PORT dataa (925:925:925) (963:963:963)) - (PORT datab (1937:1937:1937) (1953:1953:1953)) - (PORT datac (626:626:626) (660:660:660)) - (PORT datad (1598:1598:1598) (1668:1668:1668)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[3\]) - (DELAY - (ABSOLUTE - (PORT datab (889:889:889) (910:910:910)) - (PORT datac (1062:1062:1062) (1036:1036:1036)) - (PORT datad (632:632:632) (648:648:648)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (PORT dataa (848:848:848) (868:868:868)) + (PORT datac (571:571:571) (582:582:582)) + (PORT datad (765:765:765) (772:772:772)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_high\[3\]) + (INSTANCE z80_\|alu_\|op1_high\[2\]) (DELAY (ABSOLUTE - (PORT clk (1350:1350:1350) (1357:1357:1357)) + (PORT clk (1369:1369:1369) (1376:1376:1376)) (PORT d (67:67:67) (78:78:78)) (PORT ena (745:745:745) (751:751:751)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) @@ -18392,61 +15611,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op1\[3\]\~3) + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_lq) (DELAY (ABSOLUTE - (PORT datab (601:601:601) (629:629:629)) - (PORT datac (593:593:593) (618:618:618)) - (PORT datad (590:590:590) (591:591:591)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_10\~0) - (DELAY - (ABSOLUTE - (PORT dataa (591:591:591) (626:626:626)) - (PORT datab (598:598:598) (633:633:633)) - (PORT datac (175:175:175) (206:206:206)) - (PORT datad (543:543:543) (529:529:529)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1051:1051:1051) (1043:1043:1043)) - (PORT datab (1175:1175:1175) (1231:1231:1231)) - (PORT datac (561:561:561) (568:568:568)) - (PORT datad (1041:1041:1041) (1014:1014:1014)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1856:1856:1856) (1979:1979:1979)) - (PORT datab (1176:1176:1176) (1205:1205:1205)) - (PORT datac (914:914:914) (922:922:922)) - (PORT datad (1343:1343:1343) (1387:1387:1387)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) + (PORT dataa (1588:1588:1588) (1643:1643:1643)) + (PORT datab (880:880:880) (919:919:919)) + (PORT datac (1544:1544:1544) (1562:1562:1562)) + (PORT datad (965:965:965) (1014:1014:1014)) + (IOPATH dataa combout (307:307:307) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -18454,15 +15627,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~0) + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[2\]\~2) (DELAY (ABSOLUTE - (PORT dataa (938:938:938) (951:951:951)) - (PORT datab (1484:1484:1484) (1550:1550:1550)) - (PORT datac (1048:1048:1048) (1029:1029:1029)) - (PORT datad (606:606:606) (624:624:624)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) + (PORT datac (550:550:550) (560:560:560)) + (PORT datad (600:600:600) (605:605:605)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -18473,10 +15642,10 @@ (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~5) (DELAY (ABSOLUTE - (PORT dataa (2373:2373:2373) (2398:2398:2398)) - (PORT datab (1443:1443:1443) (1492:1492:1492)) - (PORT datac (800:800:800) (809:809:809)) - (PORT datad (175:175:175) (202:202:202)) + (PORT dataa (1709:1709:1709) (1792:1792:1792)) + (PORT datab (1758:1758:1758) (1796:1796:1796)) + (PORT datac (979:979:979) (980:980:980)) + (PORT datad (315:315:315) (331:331:331)) (IOPATH dataa combout (272:272:272) (269:269:269)) (IOPATH datab combout (273:273:273) (275:275:275)) (IOPATH datac combout (220:220:220) (216:216:216)) @@ -18484,18 +15653,32 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~6) + (DELAY + (ABSOLUTE + (PORT dataa (567:567:567) (589:589:589)) + (PORT datab (1833:1833:1833) (1890:1890:1890)) + (PORT datac (1575:1575:1575) (1589:1589:1589)) + (PORT datad (1028:1028:1028) (1007:1007:1007)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~7) (DELAY (ABSOLUTE - (PORT dataa (362:362:362) (364:364:364)) - (PORT datab (744:744:744) (771:771:771)) - (PORT datac (778:778:778) (763:763:763)) - (PORT datad (159:159:159) (179:179:179)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT dataa (329:329:329) (344:344:344)) + (PORT datac (175:175:175) (217:217:217)) + (PORT datad (193:193:193) (223:223:223)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -18505,12 +15688,12 @@ (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~8) (DELAY (ABSOLUTE - (PORT dataa (596:596:596) (594:594:594)) - (PORT datab (1079:1079:1079) (1111:1111:1111)) - (PORT datac (520:520:520) (505:505:505)) - (PORT datad (553:553:553) (546:546:546)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) + (PORT dataa (800:800:800) (825:825:825)) + (PORT datab (200:200:200) (233:233:233)) + (PORT datac (496:496:496) (488:488:488)) + (PORT datad (938:938:938) (963:963:963)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -18518,29 +15701,33 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[1\]\~5) + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_zero) (DELAY (ABSOLUTE - (PORT dataa (549:549:549) (548:548:548)) - (PORT datab (1031:1031:1031) (1053:1053:1053)) - (PORT datac (521:521:521) (520:520:520)) - (PORT datad (843:843:843) (869:869:869)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT dataa (736:736:736) (766:766:766)) + (PORT datab (606:606:606) (622:622:622)) + (PORT datac (754:754:754) (786:786:786)) + (PORT datad (522:522:522) (524:524:524)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[1\]\~6) + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[2\]\~3) (DELAY (ABSOLUTE - (PORT dataa (234:234:234) (306:306:306)) - (PORT datac (154:154:154) (184:184:184)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT dataa (182:182:182) (219:219:219)) + (PORT datab (831:831:831) (833:833:833)) + (PORT datac (848:848:848) (851:851:851)) + (PORT datad (796:796:796) (797:797:797)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) @@ -18549,10 +15736,1862 @@ (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|ena) (DELAY (ABSOLUTE - (PORT dataa (241:241:241) (312:312:312)) - (PORT datac (1002:1002:1002) (1029:1029:1029)) - (PORT datad (840:840:840) (869:869:869)) + (PORT dataa (589:589:589) (601:601:601)) + (PORT datab (839:839:839) (839:839:839)) + (PORT datac (854:854:854) (853:853:853)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_high\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1356:1356:1356) (1366:1366:1366)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (745:745:745) (751:751:751)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[2\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (566:566:566) (597:597:597)) + (PORT datab (648:648:648) (646:646:646)) + (PORT datac (580:580:580) (579:579:579)) + (PORT datad (613:613:613) (638:638:638)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[2\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (579:579:579) (599:599:599)) + (PORT datab (1043:1043:1043) (1051:1051:1051)) + (PORT datac (155:155:155) (186:186:186)) + (PORT datad (302:302:302) (302:302:302)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~1) + (DELAY + (ABSOLUTE + (PORT datab (640:640:640) (658:658:658)) + (PORT datad (597:597:597) (614:614:614)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[2\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (809:809:809) (833:833:833)) + (PORT datab (557:557:557) (569:569:569)) + (PORT datac (316:316:316) (329:329:329)) + (PORT datad (572:572:572) (585:585:585)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1360:1360:1360)) + (PORT asdata (864:864:864) (868:868:868)) + (PORT ena (716:716:716) (714:714:714)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1360:1360:1360)) + (PORT asdata (866:866:866) (871:871:871)) + (PORT ena (1177:1177:1177) (1173:1173:1173)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~78) + (DELAY + (ABSOLUTE + (PORT dataa (616:616:616) (665:665:665)) + (PORT datab (220:220:220) (289:289:289)) + (PORT datad (212:212:212) (249:249:249)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_78\~0) + (DELAY + (ABSOLUTE + (PORT dataa (805:805:805) (792:792:792)) + (PORT datab (692:692:692) (722:722:722)) + (PORT datac (579:579:579) (603:603:603)) + (PORT datad (864:864:864) (865:865:865)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1360:1360:1360)) + (PORT asdata (485:485:485) (512:512:512)) + (PORT ena (1321:1321:1321) (1324:1324:1324)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~79) + (DELAY + (ABSOLUTE + (PORT dataa (644:644:644) (679:679:679)) + (PORT datab (801:801:801) (796:796:796)) + (PORT datad (1245:1245:1245) (1192:1192:1192)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_34) + (DELAY + (ABSOLUTE + (PORT dataa (909:909:909) (943:943:943)) + (PORT datac (1470:1470:1470) (1431:1431:1431)) + (PORT datad (1040:1040:1040) (1043:1043:1043)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (814:814:814) (806:806:806)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_35) + (DELAY + (ABSOLUTE + (PORT dataa (913:913:913) (945:945:945)) + (PORT datac (1473:1473:1473) (1433:1433:1433)) + (PORT datad (1043:1043:1043) (1044:1044:1044)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1344:1344:1344) (1362:1362:1362)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (735:735:735) (734:734:734)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_31) + (DELAY + (ABSOLUTE + (PORT dataa (910:910:910) (940:940:940)) + (PORT datab (1067:1067:1067) (1076:1076:1076)) + (PORT datac (735:735:735) (732:732:732)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1344:1344:1344) (1362:1362:1362)) + (PORT asdata (1132:1132:1132) (1120:1120:1120)) + (PORT ena (763:763:763) (771:771:771)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_30) + (DELAY + (ABSOLUTE + (PORT dataa (908:908:908) (934:934:934)) + (PORT datab (1065:1065:1065) (1072:1072:1072)) + (PORT datac (736:736:736) (730:730:730)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~75) + (DELAY + (ABSOLUTE + (PORT dataa (210:210:210) (253:253:253)) + (PORT datab (220:220:220) (289:289:289)) + (PORT datad (184:184:184) (209:209:209)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (591:591:591) (609:609:609)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1362:1362:1362)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1115:1115:1115) (1103:1103:1103)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1362:1362:1362)) + (PORT asdata (1079:1079:1079) (1082:1082:1082)) + (PORT ena (1104:1104:1104) (1087:1087:1087)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~76) + (DELAY + (ABSOLUTE + (PORT dataa (804:804:804) (827:827:827)) + (PORT datab (220:220:220) (288:288:288)) + (PORT datad (624:624:624) (654:654:654)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1344:1344:1344) (1361:1361:1361)) + (PORT asdata (889:889:889) (897:897:897)) + (PORT ena (1175:1175:1175) (1148:1148:1148)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~77) + (DELAY + (ABSOLUTE + (PORT dataa (355:355:355) (362:362:362)) + (PORT datad (851:851:851) (856:856:856)) (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~80) + (DELAY + (ABSOLUTE + (PORT dataa (521:521:521) (512:512:512)) + (PORT datab (492:492:492) (478:478:478)) + (PORT datac (717:717:717) (687:687:687)) + (PORT datad (772:772:772) (742:742:742)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1344:1344:1344) (1361:1361:1361)) + (PORT asdata (856:856:856) (859:859:859)) + (PORT ena (894:894:894) (869:869:869)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1344:1344:1344) (1361:1361:1361)) + (PORT asdata (856:856:856) (859:859:859)) + (PORT ena (927:927:927) (910:910:910)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~74) + (DELAY + (ABSOLUTE + (PORT dataa (353:353:353) (370:370:370)) + (PORT datab (218:218:218) (286:286:286)) + (PORT datad (344:344:344) (347:347:347)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1351:1351:1351) (1372:1372:1372)) + (PORT asdata (1079:1079:1079) (1070:1070:1070)) + (PORT ena (735:735:735) (733:733:733)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1351:1351:1351) (1372:1372:1372)) + (PORT asdata (1079:1079:1079) (1070:1070:1070)) + (PORT ena (765:765:765) (779:779:779)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~73) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (295:295:295)) + (PORT datab (212:212:212) (255:255:255)) + (PORT datad (192:192:192) (219:219:219)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~81) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (218:218:218)) + (PORT datab (183:183:183) (215:215:215)) + (PORT datad (559:559:559) (554:554:554)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1044:1044:1044) (1060:1060:1060)) + (PORT datab (616:616:616) (632:632:632)) + (PORT datac (585:585:585) (603:603:603)) + (PORT datad (1246:1246:1246) (1193:1193:1193)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (629:629:629) (624:624:624)) + (PORT datab (589:589:589) (595:595:595)) + (PORT datac (612:612:612) (648:648:648)) + (PORT datad (1086:1086:1086) (1053:1053:1053)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (388:388:388) (400:400:400)) + (PORT datab (180:180:180) (212:212:212)) + (PORT datac (562:562:562) (583:583:583)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~92) + (DELAY + (ABSOLUTE + (PORT dataa (836:836:836) (865:865:865)) + (PORT datab (608:608:608) (636:636:636)) + (PORT datac (562:562:562) (590:590:590)) + (PORT datad (554:554:554) (561:561:561)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (379:379:379) (411:411:411)) + (PORT datab (403:403:403) (421:421:421)) + (PORT datac (559:559:559) (551:551:551)) + (PORT datad (538:538:538) (530:530:530)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_74) + (DELAY + (ABSOLUTE + (PORT dataa (974:974:974) (955:955:955)) + (PORT datac (1047:1047:1047) (1039:1039:1039)) + (PORT datad (807:807:807) (824:824:824)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_62) + (DELAY + (ABSOLUTE + (PORT datab (833:833:833) (859:859:859)) + (PORT datac (1046:1046:1046) (1039:1039:1039)) + (PORT datad (743:743:743) (718:718:718)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (425:425:425) (438:438:438)) + (PORT datab (993:993:993) (970:970:970)) + (PORT datac (1493:1493:1493) (1492:1492:1492)) + (PORT datad (572:572:572) (568:568:568)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1340:1340:1340) (1357:1357:1357)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1132:1132:1132) (1111:1111:1111)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1360:1360:1360)) + (PORT asdata (672:672:672) (682:682:682)) + (PORT ena (716:716:716) (714:714:714)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1360:1360:1360)) + (PORT asdata (484:484:484) (510:510:510)) + (PORT ena (1321:1321:1321) (1324:1324:1324)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~55) + (DELAY + (ABSOLUTE + (PORT dataa (235:235:235) (283:283:283)) + (PORT datab (585:585:585) (613:613:613)) + (PORT datad (338:338:338) (369:369:369)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1360:1360:1360)) + (PORT asdata (675:675:675) (683:683:683)) + (PORT ena (1177:1177:1177) (1173:1173:1173)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~56) + (DELAY + (ABSOLUTE + (PORT datab (182:182:182) (214:214:214)) + (PORT datad (596:596:596) (624:624:624)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1361:1361:1361)) + (PORT asdata (838:838:838) (834:834:834)) + (PORT ena (904:904:904) (889:889:889)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1361:1361:1361)) + (PORT asdata (838:838:838) (832:832:832)) + (PORT ena (735:735:735) (733:733:733)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~57) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (294:294:294)) + (PORT datab (224:224:224) (273:273:273)) + (PORT datad (209:209:209) (239:239:239)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1362:1362:1362)) + (PORT asdata (925:925:925) (943:943:943)) + (PORT ena (1115:1115:1115) (1103:1103:1103)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1362:1362:1362)) + (PORT asdata (925:925:925) (946:946:946)) + (PORT ena (1104:1104:1104) (1087:1087:1087)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~59) + (DELAY + (ABSOLUTE + (PORT dataa (808:808:808) (836:836:836)) + (PORT datab (220:220:220) (289:289:289)) + (PORT datad (619:619:619) (650:650:650)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1344:1344:1344) (1362:1362:1362)) + (PORT asdata (948:948:948) (954:954:954)) + (PORT ena (735:735:735) (734:734:734)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1344:1344:1344) (1362:1362:1362)) + (PORT asdata (948:948:948) (956:956:956)) + (PORT ena (763:763:763) (771:771:771)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~58) + (DELAY + (ABSOLUTE + (PORT dataa (210:210:210) (253:253:253)) + (PORT datab (220:220:220) (288:288:288)) + (PORT datad (183:183:183) (206:206:206)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1344:1344:1344) (1361:1361:1361)) + (PORT asdata (1294:1294:1294) (1267:1267:1267)) + (PORT ena (1175:1175:1175) (1148:1148:1148)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~60) + (DELAY + (ABSOLUTE + (PORT dataa (583:583:583) (584:584:584)) + (PORT datab (312:312:312) (331:331:331)) + (PORT datad (858:858:858) (858:858:858)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1351:1351:1351) (1372:1372:1372)) + (PORT asdata (1085:1085:1085) (1062:1062:1062)) + (PORT ena (892:892:892) (882:882:882)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1351:1351:1351) (1372:1372:1372)) + (PORT asdata (1086:1086:1086) (1063:1063:1063)) + (PORT ena (893:893:893) (883:883:883)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~53) + (DELAY + (ABSOLUTE + (PORT dataa (383:383:383) (408:408:408)) + (PORT datab (398:398:398) (416:416:416)) + (PORT datad (197:197:197) (253:253:253)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~54) + (DELAY + (ABSOLUTE + (PORT dataa (800:800:800) (802:802:802)) + (PORT datac (827:827:827) (811:811:811)) + (PORT datad (783:783:783) (782:782:782)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~61) + (DELAY + (ABSOLUTE + (PORT dataa (586:586:586) (579:579:579)) + (PORT datab (566:566:566) (572:572:572)) + (PORT datac (323:323:323) (327:327:327)) + (PORT datad (318:318:318) (318:318:318)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~62) + (DELAY + (ABSOLUTE + (PORT dataa (583:583:583) (580:580:580)) + (PORT datab (609:609:609) (618:618:618)) + (PORT datac (1016:1016:1016) (1029:1029:1029)) + (PORT datad (579:579:579) (578:578:578)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_75) + (DELAY + (ABSOLUTE + (PORT dataa (971:971:971) (959:959:959)) + (PORT datac (1045:1045:1045) (1035:1035:1035)) + (PORT datad (808:808:808) (819:819:819)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1340:1340:1340) (1357:1357:1357)) + (PORT asdata (621:621:621) (622:622:622)) + (PORT ena (1107:1107:1107) (1064:1064:1064)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (827:827:827) (847:847:847)) + (PORT datab (623:623:623) (629:629:629)) + (PORT datad (375:375:375) (389:389:389)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (223:223:223) (296:296:296)) + (PORT datab (182:182:182) (215:215:215)) + (PORT datad (569:569:569) (568:568:568)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_4\|d0_out) + (DELAY + (ABSOLUTE + (PORT datac (861:861:861) (918:918:918)) + (PORT datad (554:554:554) (548:548:548)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1523:1523:1523) (1531:1531:1531)) + (PORT datab (182:182:182) (215:215:215)) + (PORT datac (540:540:540) (527:527:527)) + (PORT datad (330:330:330) (340:340:340)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[4\]) + (DELAY + (ABSOLUTE + (PORT datab (874:874:874) (875:875:875)) + (PORT datad (875:875:875) (884:884:884)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1357:1357:1357)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1382:1382:1382) (1355:1355:1355)) + (PORT ena (1784:1784:1784) (1745:1745:1745)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_4\|d1_out) + (DELAY + (ABSOLUTE + (PORT dataa (1038:1038:1038) (1033:1033:1033)) + (PORT datab (889:889:889) (946:946:946)) + (PORT datac (843:843:843) (889:889:889)) + (PORT datad (555:555:555) (549:549:549)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1355:1355:1355)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (903:903:903) (900:900:900)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1361:1361:1361)) + (PORT asdata (1621:1621:1621) (1576:1576:1576)) + (PORT ena (904:904:904) (889:889:889)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1361:1361:1361)) + (PORT asdata (1620:1620:1620) (1575:1575:1575)) + (PORT ena (735:735:735) (733:733:733)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~64) + (DELAY + (ABSOLUTE + (PORT dataa (357:357:357) (403:403:403)) + (PORT datab (224:224:224) (275:275:275)) + (PORT datad (210:210:210) (242:242:242)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1351:1351:1351) (1372:1372:1372)) + (PORT asdata (1110:1110:1110) (1095:1095:1095)) + (PORT ena (892:892:892) (882:882:882)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1351:1351:1351) (1372:1372:1372)) + (PORT asdata (1110:1110:1110) (1095:1095:1095)) + (PORT ena (893:893:893) (883:883:883)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~63) + (DELAY + (ABSOLUTE + (PORT dataa (383:383:383) (412:412:412)) + (PORT datab (399:399:399) (415:415:415)) + (PORT datad (196:196:196) (252:252:252)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1350:1350:1350) (1371:1371:1371)) + (PORT asdata (1612:1612:1612) (1579:1579:1579)) + (PORT ena (1138:1138:1138) (1126:1126:1126)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (783:783:783) (762:762:762)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1350:1350:1350) (1371:1371:1371)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1110:1110:1110) (1080:1080:1080)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~65) + (DELAY + (ABSOLUTE + (PORT dataa (648:648:648) (681:681:681)) + (PORT datab (647:647:647) (666:666:666)) + (PORT datad (198:198:198) (254:254:254)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1360:1360:1360)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (716:716:716) (714:714:714)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1360:1360:1360)) + (PORT asdata (1575:1575:1575) (1528:1528:1528)) + (PORT ena (1321:1321:1321) (1324:1324:1324)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~69) + (DELAY + (ABSOLUTE + (PORT dataa (640:640:640) (677:677:677)) + (PORT datab (572:572:572) (601:601:601)) + (PORT datad (344:344:344) (354:354:354)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1344:1344:1344) (1361:1361:1361)) + (PORT asdata (1369:1369:1369) (1346:1346:1346)) + (PORT ena (1131:1131:1131) (1119:1119:1119)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1362:1362:1362)) + (PORT asdata (1873:1873:1873) (1841:1841:1841)) + (PORT ena (1115:1115:1115) (1103:1103:1103)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~68) + (DELAY + (ABSOLUTE + (PORT dataa (592:592:592) (621:621:621)) + (PORT datab (626:626:626) (656:656:656)) + (PORT datad (624:624:624) (654:654:654)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1344:1344:1344) (1361:1361:1361)) + (PORT asdata (1371:1371:1371) (1349:1349:1349)) + (PORT ena (1175:1175:1175) (1148:1148:1148)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1362:1362:1362)) + (PORT asdata (1873:1873:1873) (1842:1842:1842)) + (PORT ena (1104:1104:1104) (1087:1087:1087)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~66) + (DELAY + (ABSOLUTE + (PORT dataa (808:808:808) (834:834:834)) + (PORT datab (544:544:544) (544:544:544)) + (PORT datad (515:515:515) (513:513:513)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~67) + (DELAY + (ABSOLUTE + (PORT datab (883:883:883) (892:892:892)) + (PORT datad (560:560:560) (550:550:550)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~70) + (DELAY + (ABSOLUTE + (PORT dataa (592:592:592) (598:598:598)) + (PORT datab (620:620:620) (617:617:617)) + (PORT datac (550:550:550) (543:543:543)) + (PORT datad (160:160:160) (182:182:182)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~71) + (DELAY + (ABSOLUTE + (PORT dataa (313:313:313) (332:332:332)) + (PORT datab (594:594:594) (582:582:582)) + (PORT datad (551:551:551) (538:538:538)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~72) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (220:220:220)) + (PORT datab (777:777:777) (760:760:760)) + (PORT datac (582:582:582) (588:588:588)) + (PORT datad (762:762:762) (765:765:765)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1355:1355:1355)) + (PORT asdata (843:843:843) (827:827:827)) + (PORT ena (888:888:888) (871:871:871)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[5\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1330:1330:1330) (1299:1299:1299)) + (PORT datab (977:977:977) (961:961:961)) + (PORT datad (519:519:519) (509:509:509)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[5\]\~17) + (DELAY + (ABSOLUTE + (PORT datab (222:222:222) (291:291:291)) + (PORT datac (311:311:311) (321:321:321)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[5\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (540:540:540) (540:540:540)) + (PORT datab (200:200:200) (233:233:233)) + (PORT datac (156:156:156) (186:186:186)) + (PORT datad (1693:1693:1693) (1661:1661:1661)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[5\]) + (DELAY + (ABSOLUTE + (PORT datab (843:843:843) (827:827:827)) + (PORT datad (876:876:876) (879:879:879)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1357:1357:1357)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1382:1382:1382) (1355:1355:1355)) + (PORT ena (1784:1784:1784) (1745:1745:1745)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~10) + (DELAY + (ABSOLUTE + (PORT datac (1185:1185:1185) (1153:1153:1153)) + (PORT datad (1665:1665:1665) (1700:1700:1700)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_43\~4) + (DELAY + (ABSOLUTE + (PORT dataa (932:932:932) (948:948:948)) + (PORT datab (1654:1654:1654) (1697:1697:1697)) + (PORT datac (188:188:188) (229:229:229)) + (PORT datad (1719:1719:1719) (1769:1769:1769)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_44) + (DELAY + (ABSOLUTE + (PORT dataa (1758:1758:1758) (1805:1805:1805)) + (PORT datab (1653:1653:1653) (1692:1692:1692)) + (PORT datac (186:186:186) (230:230:230)) + (PORT datad (1129:1129:1129) (1168:1168:1168)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[6\]) + (DELAY + (ABSOLUTE + (PORT datac (811:811:811) (807:807:807)) + (PORT datad (874:874:874) (883:883:883)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1357:1357:1357)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1382:1382:1382) (1355:1355:1355)) + (PORT ena (1784:1784:1784) (1745:1745:1745)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[6\]) + (DELAY + (ABSOLUTE + (PORT dataa (189:189:189) (229:229:229)) + (PORT datab (189:189:189) (226:226:226)) + (PORT datac (869:869:869) (899:899:899)) + (PORT datad (186:186:186) (213:213:213)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1355:1355:1355)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (903:903:903) (900:900:900)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1355:1355:1355)) + (PORT asdata (615:615:615) (621:621:621)) + (PORT ena (888:888:888) (871:871:871)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (601:601:601) (617:617:617)) + (PORT datab (977:977:977) (964:964:964)) + (PORT datad (519:519:519) (509:509:509)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~20) + (DELAY + (ABSOLUTE + (PORT datab (221:221:221) (289:289:289)) + (PORT datac (313:313:313) (320:320:320)) + (PORT datad (159:159:159) (179:179:179)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (540:540:540) (539:539:539)) + (PORT datab (793:793:793) (768:768:768)) + (PORT datac (155:155:155) (184:184:184)) + (PORT datad (1692:1692:1692) (1661:1661:1661)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~82) + (DELAY + (ABSOLUTE + (PORT dataa (1045:1045:1045) (1060:1060:1060)) + (PORT datab (562:562:562) (551:551:551)) + (PORT datac (585:585:585) (593:593:593)) + (PORT datad (589:589:589) (585:585:585)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_ds\[6\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (764:764:764) (765:765:765)) + (PORT datab (1028:1028:1028) (1028:1028:1028)) + (PORT datac (594:594:594) (606:606:606)) + (PORT datad (808:808:808) (800:800:800)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sw1_\|db_down\[6\]\~1) + (DELAY + (ABSOLUTE + (PORT datab (611:611:611) (598:598:598)) + (PORT datac (371:371:371) (396:396:396)) + (PORT datad (766:766:766) (753:753:753)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_66_oe) + (DELAY + (ABSOLUTE + (PORT dataa (2117:2117:2117) (2169:2169:2169)) + (PORT datab (1140:1140:1140) (1192:1192:1192)) + (PORT datac (551:551:551) (585:585:585)) + (PORT datad (1498:1498:1498) (1503:1503:1503)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[1\]) + (DELAY + (ABSOLUTE + (PORT dataa (867:867:867) (897:897:897)) + (PORT datac (810:810:810) (829:829:829)) + (PORT datad (573:573:573) (575:575:575)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_high\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1369:1369:1369) (1376:1376:1376)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (745:745:745) (751:751:751)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[1\]\~4) + (DELAY + (ABSOLUTE + (PORT datab (605:605:605) (640:640:640)) + (PORT datac (550:550:550) (560:560:560)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[1\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (878:878:878) (880:880:880)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (581:581:581) (598:598:598)) + (PORT datad (794:794:794) (796:796:796)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -18563,7 +17602,7 @@ (INSTANCE z80_\|alu_\|op2_high\[1\]) (DELAY (ABSOLUTE - (PORT clk (1350:1350:1350) (1356:1356:1356)) + (PORT clk (1356:1356:1356) (1366:1366:1366)) (PORT d (67:67:67) (78:78:78)) (PORT ena (745:745:745) (751:751:751)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) @@ -18576,72 +17615,42 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[1\]) + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[1\]\~2) (DELAY (ABSOLUTE - (PORT datab (893:893:893) (911:911:911)) - (PORT datac (339:339:339) (364:364:364)) - (PORT datad (624:624:624) (645:645:645)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_high\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1350:1350:1350) (1357:1357:1357)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (745:745:745) (751:751:751)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[1\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (626:626:626) (654:654:654)) - (PORT datab (1034:1034:1034) (1063:1063:1063)) - (PORT datac (551:551:551) (544:544:544)) - (PORT datad (353:353:353) (393:393:393)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[1\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (241:241:241) (312:312:312)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (520:520:520) (517:517:517)) - (PORT datad (838:838:838) (866:866:866)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) + (PORT dataa (587:587:587) (600:600:600)) + (PORT datab (668:668:668) (689:689:689)) + (PORT datac (1015:1015:1015) (1008:1008:1008)) + (PORT datad (1025:1025:1025) (1018:1018:1018)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[1\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (879:879:879) (881:881:881)) + (PORT datab (835:835:835) (833:833:833)) + (PORT datac (579:579:579) (614:614:614)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|alu_\|op2_low\[1\]) (DELAY (ABSOLUTE - (PORT clk (1350:1350:1350) (1356:1356:1356)) + (PORT clk (1356:1356:1356) (1366:1366:1366)) (PORT d (67:67:67) (78:78:78)) (PORT ena (745:745:745) (751:751:751)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) @@ -18652,991 +17661,16 @@ (HOLD ena (posedge clk) (144:144:144)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1348:1348:1348) (1339:1339:1339)) - (PORT datab (1386:1386:1386) (1404:1404:1404)) - (PORT datac (1701:1701:1701) (1703:1703:1703)) - (PORT datad (373:373:373) (394:394:394)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~20) - (DELAY - (ABSOLUTE - (PORT dataa (1326:1326:1326) (1339:1339:1339)) - (PORT datab (1518:1518:1518) (1587:1587:1587)) - (PORT datac (986:986:986) (975:975:975)) - (PORT datad (1189:1189:1189) (1255:1255:1255)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~12) - (DELAY - (ABSOLUTE - (PORT dataa (821:821:821) (807:807:807)) - (PORT datab (875:875:875) (878:878:878)) - (PORT datac (797:797:797) (781:781:781)) - (PORT datad (603:603:603) (611:611:611)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~18) - (DELAY - (ABSOLUTE - (PORT dataa (443:443:443) (460:460:460)) - (PORT datab (1102:1102:1102) (1116:1116:1116)) - (PORT datac (843:843:843) (891:891:891)) - (PORT datad (1284:1284:1284) (1328:1328:1328)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal61\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1605:1605:1605) (1652:1652:1652)) - (PORT datab (1274:1274:1274) (1292:1292:1292)) - (PORT datac (1463:1463:1463) (1566:1566:1566)) - (PORT datad (1384:1384:1384) (1457:1457:1457)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~16) - (DELAY - (ABSOLUTE - (PORT datab (1689:1689:1689) (1725:1725:1725)) - (PORT datac (1573:1573:1573) (1613:1613:1613)) - (PORT datad (847:847:847) (878:878:878)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1726:1726:1726) (1696:1696:1696)) - (PORT datab (181:181:181) (215:215:215)) - (PORT datac (809:809:809) (787:787:787)) - (PORT datad (750:750:750) (734:734:734)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1234:1234:1234) (1289:1289:1289)) - (PORT datab (1624:1624:1624) (1652:1652:1652)) - (PORT datac (1346:1346:1346) (1370:1370:1370)) - (PORT datad (177:177:177) (200:200:200)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1414:1414:1414) (1447:1447:1447)) - (PORT datab (843:843:843) (875:875:875)) - (PORT datac (174:174:174) (206:206:206)) - (PORT datad (185:185:185) (209:209:209)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~12) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (236:236:236)) - (PORT datab (189:189:189) (224:224:224)) - (PORT datac (161:161:161) (195:195:195)) - (PORT datad (167:167:167) (192:192:192)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~22) - (DELAY - (ABSOLUTE - (PORT dataa (1638:1638:1638) (1596:1596:1596)) - (PORT datab (779:779:779) (785:785:785)) - (PORT datac (1208:1208:1208) (1288:1288:1288)) - (PORT datad (2364:2364:2364) (2375:2375:2375)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~20) - (DELAY - (ABSOLUTE - (PORT dataa (545:545:545) (551:551:551)) - (PORT datab (225:225:225) (259:259:259)) - (PORT datac (199:199:199) (233:233:233)) - (PORT datad (831:831:831) (867:867:867)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (980:980:980) (953:953:953)) - (PORT datab (1500:1500:1500) (1507:1507:1507)) - (PORT datac (1094:1094:1094) (1102:1102:1102)) - (PORT datad (1617:1617:1617) (1563:1563:1563)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal71\~2) - (DELAY - (ABSOLUTE - (PORT dataa (797:797:797) (821:821:821)) - (PORT datab (866:866:866) (911:911:911)) - (PORT datac (197:197:197) (231:231:231)) - (PORT datad (830:830:830) (866:866:866)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~8) - (DELAY - (ABSOLUTE - (PORT dataa (192:192:192) (234:234:234)) - (PORT datab (200:200:200) (234:234:234)) - (PORT datac (181:181:181) (216:216:216)) - (PORT datad (167:167:167) (191:191:191)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~31) - (DELAY - (ABSOLUTE - (PORT dataa (1123:1123:1123) (1133:1133:1133)) - (PORT datab (207:207:207) (242:242:242)) - (PORT datac (1906:1906:1906) (1932:1932:1932)) - (PORT datad (1305:1305:1305) (1352:1352:1352)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~4) - (DELAY - (ABSOLUTE - (PORT dataa (639:639:639) (640:640:640)) - (PORT datab (1366:1366:1366) (1379:1379:1379)) - (PORT datac (1366:1366:1366) (1362:1362:1362)) - (PORT datad (588:588:588) (584:584:584)) - (IOPATH dataa combout (307:307:307) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla25M1T1_3) - (DELAY - (ABSOLUTE - (PORT dataa (779:779:779) (767:767:767)) - (PORT datab (1367:1367:1367) (1380:1380:1380)) - (PORT datac (1486:1486:1486) (1439:1439:1439)) - (PORT datad (1331:1331:1331) (1383:1383:1383)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~5) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (219:219:219)) - (PORT datab (194:194:194) (232:232:232)) - (PORT datac (778:778:778) (779:779:779)) - (PORT datad (177:177:177) (199:199:199)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~6) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (240:240:240)) - (PORT datab (201:201:201) (235:235:235)) - (PORT datac (984:984:984) (969:969:969)) - (PORT datad (158:158:158) (178:178:178)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal72\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1292:1292:1292) (1320:1320:1320)) - (PORT datab (2167:2167:2167) (2220:2220:2220)) - (PORT datac (1039:1039:1039) (1045:1045:1045)) - (PORT datad (787:787:787) (766:766:766)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal73\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1843:1843:1843) (1911:1911:1911)) - (PORT datab (1033:1033:1033) (1056:1056:1056)) - (PORT datac (1247:1247:1247) (1267:1267:1267)) - (PORT datad (795:795:795) (774:774:774)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~0) - (DELAY - (ABSOLUTE - (PORT dataa (898:898:898) (929:929:929)) - (PORT datab (886:886:886) (934:934:934)) - (PORT datac (1635:1635:1635) (1643:1643:1643)) - (PORT datad (1348:1348:1348) (1364:1364:1364)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~1) - (DELAY - (ABSOLUTE - (PORT dataa (974:974:974) (963:963:963)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (566:566:566) (569:569:569)) - (PORT datad (553:553:553) (547:547:547)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1393:1393:1393) (1432:1432:1432)) - (PORT datab (1814:1814:1814) (1843:1843:1843)) - (PORT datac (1150:1150:1150) (1194:1194:1194)) - (PORT datad (852:852:852) (886:886:886)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~3) - (DELAY - (ABSOLUTE - (PORT datab (806:806:806) (799:799:799)) - (PORT datac (757:757:757) (768:768:768)) - (PORT datad (753:753:753) (745:745:745)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (2375:2375:2375) (2401:2401:2401)) - (PORT datac (1415:1415:1415) (1465:1465:1465)) - (PORT datad (1429:1429:1429) (1504:1504:1504)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (226:226:226) (276:276:276)) - (PORT datab (182:182:182) (214:214:214)) - (PORT datac (1075:1075:1075) (1083:1083:1083)) - (PORT datad (175:175:175) (203:203:203)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (749:749:749) (771:771:771)) - (PORT datab (570:570:570) (593:593:593)) - (PORT datac (155:155:155) (186:186:186)) - (PORT datad (735:735:735) (796:796:796)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~15) - (DELAY - (ABSOLUTE - (PORT dataa (851:851:851) (856:856:856)) - (PORT datac (771:771:771) (772:772:772)) - (PORT datad (594:594:594) (607:607:607)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~16) - (DELAY - (ABSOLUTE - (PORT dataa (847:847:847) (863:863:863)) - (PORT datab (339:339:339) (350:350:350)) - (PORT datac (545:545:545) (554:554:554)) - (PORT datad (318:318:318) (317:317:317)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~6) - (DELAY - (ABSOLUTE - (PORT datac (819:819:819) (825:825:825)) - (PORT datad (768:768:768) (767:767:767)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~7) - (DELAY - (ABSOLUTE - (PORT dataa (593:593:593) (595:595:595)) - (PORT datab (1019:1019:1019) (1019:1019:1019)) - (PORT datac (712:712:712) (684:684:684)) - (PORT datad (566:566:566) (579:579:579)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (842:842:842) (826:826:826)) - (PORT datab (190:190:190) (225:225:225)) - (PORT datad (178:178:178) (200:200:200)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel_pla12M1T1_12\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1849:1849:1849) (1839:1839:1839)) - (PORT datab (207:207:207) (243:243:243)) - (PORT datac (1567:1567:1567) (1621:1621:1621)) - (PORT datad (1378:1378:1378) (1406:1406:1406)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1052:1052:1052) (1063:1063:1063)) - (PORT datab (1465:1465:1465) (1537:1537:1537)) - (PORT datac (2344:2344:2344) (2367:2367:2367)) - (PORT datad (173:173:173) (200:200:200)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~7) - (DELAY - (ABSOLUTE - (PORT dataa (926:926:926) (957:957:957)) - (PORT datab (1202:1202:1202) (1227:1227:1227)) - (PORT datac (828:828:828) (821:821:821)) - (PORT datad (165:165:165) (190:190:190)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~8) - (DELAY - (ABSOLUTE - (PORT dataa (592:592:592) (596:596:596)) - (PORT datab (2125:2125:2125) (2116:2116:2116)) - (PORT datac (1899:1899:1899) (1945:1945:1945)) - (PORT datad (1071:1071:1071) (1063:1063:1063)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~8) - (DELAY - (ABSOLUTE - (PORT dataa (569:569:569) (567:567:567)) - (PORT datab (564:564:564) (566:566:566)) - (PORT datac (508:508:508) (506:506:506)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~16) - (DELAY - (ABSOLUTE - (PORT dataa (953:953:953) (964:964:964)) - (PORT datab (1889:1889:1889) (1959:1959:1959)) - (PORT datac (761:761:761) (747:747:747)) - (PORT datad (2321:2321:2321) (2343:2343:2343)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1430:1430:1430) (1444:1444:1444)) - (PORT datab (865:865:865) (915:915:915)) - (PORT datac (559:559:559) (587:587:587)) - (PORT datad (534:534:534) (521:521:521)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~13) - (DELAY - (ABSOLUTE - (PORT dataa (772:772:772) (828:828:828)) - (PORT datab (201:201:201) (233:233:233)) - (PORT datac (617:617:617) (630:630:630)) - (PORT datad (159:159:159) (179:179:179)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~14) - (DELAY - (ABSOLUTE - (PORT dataa (610:610:610) (610:610:610)) - (PORT datab (1080:1080:1080) (1089:1089:1089)) - (PORT datac (594:594:594) (617:617:617)) - (PORT datad (287:287:287) (294:294:294)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~15) - (DELAY - (ABSOLUTE - (PORT dataa (600:600:600) (608:608:608)) - (PORT datab (742:742:742) (790:790:790)) - (PORT datac (1019:1019:1019) (1018:1018:1018)) - (PORT datad (548:548:548) (553:553:553)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_nop3pla68M1T3_2) - (DELAY - (ABSOLUTE - (PORT dataa (578:578:578) (600:600:600)) - (PORT datab (600:600:600) (610:610:610)) - (PORT datac (859:859:859) (925:925:925)) - (PORT datad (772:772:772) (765:765:765)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1393:1393:1393) (1433:1433:1433)) - (PORT datab (979:979:979) (967:967:967)) - (PORT datac (1150:1150:1150) (1195:1195:1195)) - (PORT datad (850:850:850) (884:884:884)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1339:1339:1339) (1319:1319:1319)) - (PORT datab (1049:1049:1049) (1071:1071:1071)) - (PORT datac (1100:1100:1100) (1162:1162:1162)) - (PORT datad (1057:1057:1057) (1051:1051:1051)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~1) - (DELAY - (ABSOLUTE - (PORT dataa (587:587:587) (591:591:591)) - (PORT datab (949:949:949) (972:972:972)) - (PORT datac (738:738:738) (720:720:720)) - (PORT datad (572:572:572) (566:566:566)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~2) - (DELAY - (ABSOLUTE - (PORT dataa (209:209:209) (249:249:249)) - (PORT datab (958:958:958) (972:972:972)) - (PORT datac (793:793:793) (769:769:769)) - (PORT datad (551:551:551) (557:557:557)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~7) - (DELAY - (ABSOLUTE - (PORT dataa (547:547:547) (556:556:556)) - (PORT datab (201:201:201) (245:245:245)) - (PORT datac (765:765:765) (777:777:777)) - (PORT datad (1268:1268:1268) (1337:1337:1337)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~9) - (DELAY - (ABSOLUTE - (PORT dataa (718:718:718) (754:754:754)) - (PORT datab (780:780:780) (772:772:772)) - (PORT datac (697:697:697) (758:758:758)) - (PORT datad (703:703:703) (726:726:726)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~10) - (DELAY - (ABSOLUTE - (PORT dataa (184:184:184) (221:221:221)) - (PORT datab (180:180:180) (212:212:212)) - (PORT datad (160:160:160) (182:182:182)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf) - (DELAY - (ABSOLUTE - (PORT clk (1331:1331:1331) (1350:1350:1350)) - (PORT d (67:67:67) (78:78:78)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1133:1133:1133) (1133:1133:1133)) - (PORT datab (640:640:640) (667:667:667)) - (PORT datac (841:841:841) (887:887:887)) - (PORT datad (988:988:988) (976:976:976)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel_nop3pla68M3T1_20) - (DELAY - (ABSOLUTE - (PORT dataa (575:575:575) (599:599:599)) - (PORT datab (601:601:601) (604:604:604)) - (PORT datac (858:858:858) (924:924:924)) - (PORT datad (362:362:362) (363:363:363)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~10) - (DELAY - (ABSOLUTE - (PORT dataa (894:894:894) (921:921:921)) - (PORT datab (1659:1659:1659) (1669:1669:1669)) - (PORT datac (1148:1148:1148) (1193:1193:1193)) - (PORT datad (984:984:984) (962:962:962)) - (IOPATH dataa combout (307:307:307) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1863:1863:1863) (1886:1886:1886)) - (PORT datab (2223:2223:2223) (2282:2282:2282)) - (PORT datac (1279:1279:1279) (1294:1294:1294)) - (PORT datad (1468:1468:1468) (1553:1553:1553)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1391:1391:1391) (1425:1425:1425)) - (PORT datab (359:359:359) (365:365:365)) - (PORT datac (1149:1149:1149) (1187:1187:1187)) - (PORT datad (807:807:807) (816:816:816)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1122:1122:1122) (1150:1150:1150)) - (PORT datab (318:318:318) (332:332:332)) - (PORT datac (988:988:988) (973:973:973)) - (PORT datad (314:314:314) (316:316:316)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~14) - (DELAY - (ABSOLUTE - (PORT dataa (329:329:329) (347:347:347)) - (PORT datab (596:596:596) (587:587:587)) - (PORT datac (153:153:153) (183:183:183)) - (PORT datad (566:566:566) (571:571:571)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~18) - (DELAY - (ABSOLUTE - (PORT dataa (776:776:776) (781:781:781)) - (PORT datab (1040:1040:1040) (1059:1059:1059)) - (PORT datac (784:784:784) (802:802:802)) - (PORT datad (334:334:334) (376:376:376)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_high) - (DELAY - (ABSOLUTE - (PORT dataa (2372:2372:2372) (2401:2401:2401)) - (PORT datab (201:201:201) (235:235:235)) - (PORT datac (1289:1289:1289) (1277:1277:1277)) - (PORT datad (1742:1742:1742) (1773:1773:1773)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|alu_\|alu_op2\[1\]\~1) (DELAY (ABSOLUTE - (PORT dataa (420:420:420) (472:472:472)) - (PORT datab (418:418:418) (467:467:467)) - (PORT datac (802:802:802) (802:802:802)) - (PORT datad (611:611:611) (624:624:624)) - (IOPATH dataa combout (287:287:287) (289:289:289)) + (PORT dataa (559:559:559) (588:588:588)) + (PORT datab (200:200:200) (233:233:233)) + (PORT datac (174:174:174) (206:206:206)) + (PORT datad (518:518:518) (535:535:535)) + (IOPATH dataa combout (318:318:318) (327:327:327)) (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -19648,12 +17682,28 @@ (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_10\~1) (DELAY (ABSOLUTE - (PORT dataa (508:508:508) (513:513:513)) - (PORT datab (582:582:582) (628:628:628)) - (PORT datac (577:577:577) (576:576:576)) - (PORT datad (583:583:583) (615:615:615)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (300:300:300) (312:312:312)) + (PORT dataa (861:861:861) (865:865:865)) + (PORT datab (805:805:805) (832:832:832)) + (PORT datac (1025:1025:1025) (1015:1015:1015)) + (PORT datad (166:166:166) (189:189:189)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_8\~0) + (DELAY + (ABSOLUTE + (PORT dataa (862:862:862) (871:871:871)) + (PORT datab (810:810:810) (838:838:838)) + (PORT datac (1027:1027:1027) (1019:1019:1019)) + (PORT datad (165:165:165) (187:187:187)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (273:273:273) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -19661,15 +17711,75 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~9) + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_10\~0) (DELAY (ABSOLUTE - (PORT dataa (760:760:760) (755:755:755)) - (PORT datab (579:579:579) (568:568:568)) - (PORT datac (176:176:176) (207:207:207)) - (PORT datad (167:167:167) (192:192:192)) + (PORT datac (974:974:974) (1011:1011:1011)) + (PORT datad (299:299:299) (309:309:309)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~5) + (DELAY + (ABSOLUTE + (PORT dataa (594:594:594) (609:609:609)) + (PORT datab (905:905:905) (888:888:888)) + (PORT datac (565:565:565) (579:579:579)) + (PORT datad (561:561:561) (559:559:559)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~2) + (DELAY + (ABSOLUTE + (PORT dataa (828:828:828) (828:828:828)) + (PORT datab (1922:1922:1922) (1914:1914:1914)) + (PORT datac (1322:1322:1322) (1371:1371:1371)) + (PORT datad (1331:1331:1331) (1342:1342:1342)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R) + (DELAY + (ABSOLUTE + (PORT dataa (528:528:528) (549:549:549)) + (PORT datab (185:185:185) (221:221:221)) + (PORT datac (1029:1029:1029) (1010:1010:1010)) + (PORT datad (1174:1174:1174) (1245:1245:1245)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[0\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (253:253:253) (321:321:321)) + (PORT datab (242:242:242) (301:301:301)) + (PORT datac (1011:1011:1011) (1020:1020:1020)) + (PORT datad (222:222:222) (263:263:263)) (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datab combout (308:308:308) (281:281:281)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -19677,14 +17787,227 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[0\]\~7) + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[0\]) (DELAY (ABSOLUTE - (PORT dataa (758:758:758) (732:732:732)) - (PORT datab (573:573:573) (570:570:570)) - (PORT datac (1004:1004:1004) (1027:1027:1027)) - (PORT datad (831:831:831) (865:865:865)) - (IOPATH dataa combout (273:273:273) (269:269:269)) + (PORT dataa (868:868:868) (894:894:894)) + (PORT datac (810:810:810) (830:830:830)) + (PORT datad (598:598:598) (619:619:619)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_high\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1369:1369:1369) (1376:1376:1376)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (745:745:745) (751:751:751)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[0\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (397:397:397) (413:413:413)) + (PORT datab (878:878:878) (889:889:889)) + (PORT datac (329:329:329) (339:339:339)) + (PORT datad (357:357:357) (398:398:398)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[0\]\~22) + (DELAY + (ABSOLUTE + (PORT datab (796:796:796) (782:782:782)) + (PORT datac (778:778:778) (770:770:770)) + (PORT datad (1094:1094:1094) (1126:1126:1126)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[0\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (841:841:841) (827:827:827)) + (PORT datab (1201:1201:1201) (1179:1179:1179)) + (PORT datad (162:162:162) (184:184:184)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[0\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (616:616:616) (622:622:622)) + (PORT datab (638:638:638) (657:657:657)) + (PORT datac (597:597:597) (609:609:609)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (252:252:252) (322:322:322)) + (PORT datab (242:242:242) (302:302:302)) + (PORT datac (1011:1011:1011) (1020:1020:1020)) + (PORT datad (217:217:217) (257:257:257)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|result_lo\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1353:1353:1353) (1370:1370:1370)) + (PORT asdata (486:486:486) (513:513:513)) + (PORT ena (1571:1571:1571) (1556:1556:1556)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (568:568:568) (597:597:597)) + (PORT datab (635:635:635) (657:657:657)) + (PORT datac (839:839:839) (865:865:865)) + (PORT datad (781:781:781) (786:786:786)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT datac (804:804:804) (818:818:818)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_low\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1369:1369:1369) (1376:1376:1376)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (720:720:720) (722:722:722)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (397:397:397) (410:410:410)) + (PORT datab (576:576:576) (603:603:603)) + (PORT datac (329:329:329) (337:337:337)) + (PORT datad (373:373:373) (409:409:409)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (512:512:512) (507:507:507)) + (PORT datab (553:553:553) (544:544:544)) + (PORT datad (157:157:157) (178:178:178)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~1) + (DELAY + (ABSOLUTE + (PORT dataa (769:769:769) (764:764:764)) + (PORT datab (245:245:245) (317:317:317)) + (PORT datac (613:613:613) (669:669:669)) + (PORT datad (764:764:764) (743:743:743)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1052:1052:1052) (1081:1081:1081)) + (PORT datab (785:785:785) (753:753:753)) + (PORT datac (574:574:574) (573:573:573)) + (PORT datad (1713:1713:1713) (1750:1750:1750)) + (IOPATH dataa combout (287:287:287) (289:289:289)) (IOPATH datab combout (308:308:308) (300:300:300)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -19693,11 +18016,216 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[0\]\~8) + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~3) (DELAY (ABSOLUTE + (PORT dataa (2291:2291:2291) (2347:2347:2347)) + (PORT datab (999:999:999) (981:981:981)) + (PORT datac (340:340:340) (351:351:351)) + (PORT datad (1592:1592:1592) (1587:1587:1587)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (203:203:203) (242:242:242)) + (PORT datab (1794:1794:1794) (1787:1787:1787)) + (PORT datac (826:826:826) (843:843:843)) + (PORT datad (1056:1056:1056) (1063:1063:1063)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (191:191:191) (230:230:230)) + (PORT datab (1124:1124:1124) (1128:1128:1128)) + (PORT datac (193:193:193) (239:239:239)) + (PORT datad (160:160:160) (182:182:182)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (188:188:188) (227:227:227)) + (PORT datab (187:187:187) (223:223:223)) (PORT datac (156:156:156) (186:186:186)) - (PORT datad (213:213:213) (265:265:265)) + (PORT datad (546:546:546) (541:541:541)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~0) + (DELAY + (ABSOLUTE + (PORT dataa (762:762:762) (738:738:738)) + (PORT datab (813:813:813) (793:793:793)) + (PORT datac (186:186:186) (226:226:226)) + (PORT datad (563:563:563) (578:578:578)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~1) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (219:219:219)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datad (178:178:178) (201:201:201)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf) + (DELAY + (ABSOLUTE + (PORT clk (1353:1353:1353) (1371:1371:1371)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1014:1014:1014) (1006:1006:1006)) + (PORT datab (244:244:244) (317:317:317)) + (PORT datac (792:792:792) (831:831:831)) + (PORT datad (1087:1087:1087) (1117:1117:1117)) + (IOPATH dataa combout (307:307:307) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~2) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (220:220:220)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (987:987:987) (976:976:976)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (775:775:775) (778:778:778)) + (PORT datab (187:187:187) (224:224:224)) + (PORT datad (1086:1086:1086) (1123:1123:1123)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (660:660:660) (699:699:699)) + (PORT datab (1028:1028:1028) (1031:1031:1031)) + (PORT datac (553:553:553) (544:544:544)) + (PORT datad (752:752:752) (739:739:739)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (641:641:641) (659:659:659)) + (PORT datab (188:188:188) (223:223:223)) + (PORT datac (633:633:633) (667:667:667)) + (PORT datad (609:609:609) (635:635:635)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1009:1009:1009) (1014:1014:1014)) + (PORT datab (883:883:883) (897:897:897)) + (PORT datac (500:500:500) (490:490:490)) + (PORT datad (546:546:546) (574:574:574)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (620:620:620) (641:641:641)) + (PORT datab (838:838:838) (836:836:836)) + (PORT datac (854:854:854) (851:851:851)) + (PORT datad (301:301:301) (306:306:306)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -19705,10 +18233,10 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_high\[0\]) + (INSTANCE z80_\|alu_\|op2_low\[0\]) (DELAY (ABSOLUTE - (PORT clk (1350:1350:1350) (1356:1356:1356)) + (PORT clk (1356:1356:1356) (1366:1366:1366)) (PORT d (67:67:67) (78:78:78)) (PORT ena (745:745:745) (751:751:751)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) @@ -19724,60 +18252,26 @@ (INSTANCE z80_\|alu_\|alu_op2\[0\]\~3) (DELAY (ABSOLUTE - (PORT dataa (399:399:399) (468:468:468)) - (PORT datab (625:625:625) (653:653:653)) - (PORT datac (802:802:802) (803:803:803)) - (PORT datad (611:611:611) (629:629:629)) + (PORT dataa (376:376:376) (428:428:428)) + (PORT datab (377:377:377) (387:387:387)) + (PORT datac (572:572:572) (560:560:560)) + (PORT datad (368:368:368) (405:405:405)) (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~12) - (DELAY - (ABSOLUTE - (PORT dataa (797:797:797) (822:822:822)) - (PORT datab (200:200:200) (241:241:241)) - (PORT datac (767:767:767) (779:779:779)) - (PORT datad (829:829:829) (876:876:876)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~8) - (DELAY - (ABSOLUTE - (PORT dataa (719:719:719) (754:754:754)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (1684:1684:1684) (1638:1638:1638)) - (PORT datad (741:741:741) (728:728:728)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_1) (DELAY (ABSOLUTE - (PORT dataa (620:620:620) (624:624:624)) - (PORT datab (1646:1646:1646) (1589:1589:1589)) - (PORT datac (161:161:161) (194:194:194)) - (PORT datad (763:763:763) (749:749:749)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (295:295:295) (294:294:294)) + (PORT dataa (1012:1012:1012) (1048:1048:1048)) + (PORT datac (1012:1012:1012) (991:991:991)) + (PORT datad (166:166:166) (190:190:190)) + (IOPATH dataa combout (318:318:318) (327:327:327)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -19785,31 +18279,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~21) + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla26M3T5_8) (DELAY (ABSOLUTE - (PORT dataa (2200:2200:2200) (2255:2255:2255)) - (PORT datab (1385:1385:1385) (1430:1430:1430)) - (PORT datac (812:812:812) (800:800:800)) - (PORT datad (936:936:936) (996:996:996)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~22) - (DELAY - (ABSOLUTE - (PORT dataa (536:536:536) (525:525:525)) - (PORT datab (910:910:910) (930:930:930)) - (PORT datac (615:615:615) (641:641:641)) - (PORT datad (759:759:759) (743:743:743)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (265:265:265) (275:275:275)) + (PORT datab (862:862:862) (945:945:945)) + (PORT datac (761:761:761) (771:771:771)) + (PORT datad (1201:1201:1201) (1314:1314:1314)) + (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -19817,45 +18293,45 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~19) + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~14) (DELAY (ABSOLUTE - (PORT dataa (898:898:898) (922:922:922)) - (PORT datab (407:407:407) (416:416:416)) - (PORT datac (878:878:878) (907:907:907)) - (PORT datad (1087:1087:1087) (1100:1100:1100)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~27) - (DELAY - (ABSOLUTE - (PORT dataa (214:214:214) (255:255:255)) - (PORT datab (202:202:202) (236:236:236)) - (PORT datac (176:176:176) (208:208:208)) - (PORT datad (190:190:190) (214:214:214)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~29) - (DELAY - (ABSOLUTE - (PORT datab (205:205:205) (251:251:251)) - (PORT datac (172:172:172) (211:211:211)) - (PORT datad (351:351:351) (351:351:351)) + (PORT dataa (2850:2850:2850) (2840:2840:2840)) + (PORT datab (181:181:181) (213:213:213)) + (PORT datac (1543:1543:1543) (1562:1562:1562)) + (PORT datad (765:765:765) (757:757:757)) + (IOPATH dataa combout (272:272:272) (269:269:269)) (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1241:1241:1241) (1274:1274:1274)) + (PORT datac (545:545:545) (567:567:567)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1522:1522:1522) (1559:1559:1559)) + (PORT datab (1753:1753:1753) (1761:1761:1761)) + (PORT datac (1049:1049:1049) (1071:1071:1071)) + (PORT datad (1331:1331:1331) (1330:1330:1330)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -19863,13 +18339,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~23) + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~17) (DELAY (ABSOLUTE - (PORT dataa (183:183:183) (219:219:219)) - (PORT datab (590:590:590) (599:599:599)) - (PORT datac (156:156:156) (186:186:186)) - (PORT datad (178:178:178) (199:199:199)) + (PORT dataa (181:181:181) (216:216:216)) + (PORT datab (578:578:578) (596:596:596)) + (PORT datac (184:184:184) (223:223:223)) + (PORT datad (820:820:820) (839:839:839)) (IOPATH dataa combout (318:318:318) (307:307:307)) (IOPATH datab combout (319:319:319) (307:307:307)) (IOPATH datac combout (218:218:218) (215:215:215)) @@ -19879,13 +18355,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~37) + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~44) (DELAY (ABSOLUTE - (PORT datab (1176:1176:1176) (1233:1233:1233)) - (PORT datac (824:824:824) (837:837:837)) - (PORT datad (1082:1082:1082) (1061:1061:1061)) - (IOPATH datab combout (325:325:325) (332:332:332)) + (PORT dataa (381:381:381) (383:383:383)) + (PORT datab (214:214:214) (255:255:255)) + (PORT datac (571:571:571) (578:578:578)) + (PORT datad (553:553:553) (537:537:537)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~20) + (DELAY + (ABSOLUTE + (PORT dataa (1521:1521:1521) (1558:1558:1558)) + (PORT datab (1032:1032:1032) (1085:1085:1085)) + (PORT datac (1049:1049:1049) (1070:1070:1070)) + (PORT datad (1332:1332:1332) (1330:1330:1330)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -19893,15 +18387,79 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~38) + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~21) (DELAY (ABSOLUTE - (PORT dataa (1191:1191:1191) (1202:1202:1202)) - (PORT datab (936:936:936) (969:969:969)) - (PORT datac (1342:1342:1342) (1366:1366:1366)) - (PORT datad (160:160:160) (182:182:182)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (273:273:273) (275:275:275)) + (PORT dataa (208:208:208) (250:250:250)) + (PORT datab (1030:1030:1030) (1085:1085:1085)) + (PORT datac (889:889:889) (924:924:924)) + (PORT datad (158:158:158) (179:179:179)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~18) + (DELAY + (ABSOLUTE + (PORT dataa (864:864:864) (889:889:889)) + (PORT datab (1124:1124:1124) (1126:1126:1126)) + (PORT datac (1940:1940:1940) (1958:1958:1958)) + (PORT datad (1523:1523:1523) (1489:1489:1489)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~19) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (239:239:239)) + (PORT datab (218:218:218) (263:263:263)) + (PORT datac (156:156:156) (186:186:186)) + (PORT datad (191:191:191) (220:220:220)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~22) + (DELAY + (ABSOLUTE + (PORT dataa (203:203:203) (241:241:241)) + (PORT datab (215:215:215) (256:256:256)) + (PORT datac (548:548:548) (562:562:562)) + (PORT datad (573:573:573) (583:583:583)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~43) + (DELAY + (ABSOLUTE + (PORT dataa (610:610:610) (642:642:642)) + (PORT datab (885:885:885) (901:901:901)) + (PORT datac (1491:1491:1491) (1484:1484:1484)) + (PORT datad (568:568:568) (577:577:577)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (295:295:295) (300:300:300)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -19912,13 +18470,13 @@ (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~24) (DELAY (ABSOLUTE - (PORT dataa (1896:1896:1896) (1896:1896:1896)) - (PORT datab (866:866:866) (914:914:914)) - (PORT datac (1118:1118:1118) (1108:1108:1108)) - (PORT datad (1005:1005:1005) (1001:1001:1001)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT dataa (1158:1158:1158) (1161:1161:1161)) + (PORT datab (945:945:945) (969:969:969)) + (PORT datac (2790:2790:2790) (2764:2764:2764)) + (PORT datad (1348:1348:1348) (1370:1370:1370)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (308:308:308) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -19928,156 +18486,12 @@ (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~25) (DELAY (ABSOLUTE - (PORT dataa (854:854:854) (850:850:850)) - (PORT datab (981:981:981) (964:964:964)) - (PORT datac (819:819:819) (829:829:829)) - (PORT datad (524:524:524) (522:522:522)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~26) - (DELAY - (ABSOLUTE - (PORT dataa (1375:1375:1375) (1411:1411:1411)) - (PORT datab (408:408:408) (415:415:415)) - (PORT datac (859:859:859) (884:884:884)) - (PORT datad (1089:1089:1089) (1098:1098:1098)) - (IOPATH dataa combout (307:307:307) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~27) - (DELAY - (ABSOLUTE - (PORT dataa (1379:1379:1379) (1416:1416:1416)) - (PORT datab (214:214:214) (251:251:251)) - (PORT datac (1854:1854:1854) (1845:1845:1845)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~28) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (219:219:219)) - (PORT datab (200:200:200) (234:234:234)) - (PORT datac (571:571:571) (585:585:585)) - (PORT datad (177:177:177) (199:199:199)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~30) - (DELAY - (ABSOLUTE - (PORT dataa (192:192:192) (234:234:234)) - (PORT datab (198:198:198) (231:231:231)) - (PORT datac (745:745:745) (775:775:775)) - (PORT datad (525:525:525) (507:507:507)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~34) - (DELAY - (ABSOLUTE - (PORT dataa (1348:1348:1348) (1376:1376:1376)) - (PORT datab (1303:1303:1303) (1272:1272:1272)) - (PORT datac (1453:1453:1453) (1474:1474:1474)) - (PORT datad (983:983:983) (973:973:973)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~32) - (DELAY - (ABSOLUTE - (PORT dataa (674:674:674) (700:700:700)) - (PORT datab (637:637:637) (664:664:664)) - (PORT datac (1479:1479:1479) (1443:1443:1443)) - (PORT datad (1325:1325:1325) (1335:1335:1335)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~43) - (DELAY - (ABSOLUTE - (PORT dataa (1242:1242:1242) (1288:1288:1288)) - (PORT datab (1003:1003:1003) (1001:1001:1001)) - (PORT datac (1453:1453:1453) (1470:1470:1470)) - (PORT datad (1656:1656:1656) (1697:1697:1697)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~33) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (219:219:219)) - (PORT datab (776:776:776) (796:796:796)) - (PORT datac (1482:1482:1482) (1447:1447:1447)) - (PORT datad (157:157:157) (178:178:178)) - (IOPATH dataa combout (307:307:307) (323:323:323)) - (IOPATH datab combout (308:308:308) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~42) - (DELAY - (ABSOLUTE - (PORT dataa (776:776:776) (781:781:781)) - (PORT datab (1008:1008:1008) (1007:1007:1007)) - (PORT datac (1948:1948:1948) (1963:1963:1963)) - (PORT datad (1650:1650:1650) (1690:1690:1690)) + (PORT dataa (874:874:874) (874:874:874)) + (PORT datab (1112:1112:1112) (1133:1133:1133)) + (PORT datac (827:827:827) (836:836:836)) + (PORT datad (159:159:159) (181:181:181)) (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datab combout (319:319:319) (307:307:307)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -20088,11 +18502,27 @@ (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~35) (DELAY (ABSOLUTE - (PORT dataa (182:182:182) (218:218:218)) - (PORT datab (182:182:182) (214:214:214)) - (PORT datac (947:947:947) (926:926:926)) - (PORT datad (158:158:158) (178:178:178)) - (IOPATH dataa combout (272:272:272) (269:269:269)) + (PORT dataa (1961:1961:1961) (2003:2003:2003)) + (PORT datab (1898:1898:1898) (1927:1927:1927)) + (PORT datac (1431:1431:1431) (1477:1477:1477)) + (PORT datad (1031:1031:1031) (1004:1004:1004)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~23) + (DELAY + (ABSOLUTE + (PORT dataa (205:205:205) (253:253:253)) + (PORT datab (946:946:946) (969:969:969)) + (PORT datac (534:534:534) (527:527:527)) + (PORT datad (784:784:784) (777:777:777)) + (IOPATH dataa combout (318:318:318) (327:327:327)) (IOPATH datab combout (273:273:273) (275:275:275)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -20101,31 +18531,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~41) + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~26) (DELAY (ABSOLUTE - (PORT dataa (628:628:628) (642:642:642)) - (PORT datab (1892:1892:1892) (1909:1909:1909)) - (PORT datac (1365:1365:1365) (1394:1394:1394)) - (PORT datad (1233:1233:1233) (1319:1319:1319)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (PORT dataa (1343:1343:1343) (1331:1331:1331)) + (PORT datab (1018:1018:1018) (1026:1026:1026)) + (PORT datac (1271:1271:1271) (1335:1335:1335)) + (PORT datad (835:835:835) (843:843:843)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~30) + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~34) (DELAY (ABSOLUTE - (PORT dataa (1393:1393:1393) (1426:1426:1426)) - (PORT datab (1812:1812:1812) (1838:1838:1838)) - (PORT datac (1150:1150:1150) (1187:1187:1187)) - (PORT datad (805:805:805) (815:815:815)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (319:319:319) (324:324:324)) + (PORT dataa (2368:2368:2368) (2410:2410:2410)) + (PORT datab (1368:1368:1368) (1367:1367:1367)) + (PORT datac (1338:1338:1338) (1394:1394:1394)) + (PORT datad (842:842:842) (867:867:867)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (273:273:273) (275:275:275)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -20133,15 +18563,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~10) + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~27) (DELAY (ABSOLUTE - (PORT dataa (1607:1607:1607) (1662:1662:1662)) - (PORT datab (951:951:951) (989:989:989)) - (PORT datac (178:178:178) (214:214:214)) - (PORT datad (1379:1379:1379) (1408:1408:1408)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) + (PORT dataa (684:684:684) (728:728:728)) + (PORT datab (1584:1584:1584) (1569:1569:1569)) + (PORT datac (794:794:794) (795:795:795)) + (PORT datad (1773:1773:1773) (1873:1873:1873)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -20149,32 +18579,16 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~31) + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~28) (DELAY (ABSOLUTE - (PORT dataa (1071:1071:1071) (1049:1049:1049)) - (PORT datab (182:182:182) (215:215:215)) - (PORT datac (156:156:156) (187:187:187)) - (PORT datad (1252:1252:1252) (1248:1248:1248)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~44) - (DELAY - (ABSOLUTE - (PORT dataa (762:762:762) (761:761:761)) - (PORT datab (1679:1679:1679) (1738:1738:1738)) - (PORT datac (1205:1205:1205) (1254:1254:1254)) - (PORT datad (1656:1656:1656) (1697:1697:1697)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT dataa (184:184:184) (222:222:222)) + (PORT datab (866:866:866) (941:941:941)) + (PORT datac (154:154:154) (184:184:184)) + (PORT datad (1774:1774:1774) (1875:1875:1875)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -20182,15 +18596,47 @@ (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~29) + (DELAY + (ABSOLUTE + (PORT dataa (909:909:909) (939:939:939)) + (PORT datab (827:827:827) (828:828:828)) + (PORT datac (1337:1337:1337) (1333:1333:1333)) + (PORT datad (1543:1543:1543) (1538:1538:1538)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~30) (DELAY (ABSOLUTE (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (638:638:638) (671:671:671)) - (PORT datac (801:801:801) (797:797:797)) - (PORT datad (628:628:628) (658:658:658)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT datab (180:180:180) (213:213:213)) + (PORT datac (1037:1037:1037) (1065:1065:1065)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~31) + (DELAY + (ABSOLUTE + (PORT dataa (565:565:565) (574:574:574)) + (PORT datab (179:179:179) (211:211:211)) + (PORT datac (156:156:156) (187:187:187)) + (PORT datad (558:558:558) (565:565:565)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -20200,28 +18646,10 @@ (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~36) (DELAY (ABSOLUTE - (PORT dataa (499:499:499) (493:493:493)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (594:594:594) (607:607:607)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~39) - (DELAY - (ABSOLUTE - (PORT dataa (549:549:549) (556:556:556)) - (PORT datab (181:181:181) (213:213:213)) - (PORT datac (561:561:561) (564:564:564)) - (PORT datad (320:320:320) (324:324:324)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) + (PORT dataa (1180:1180:1180) (1253:1253:1253)) + (PORT datac (1543:1543:1543) (1556:1556:1556)) + (PORT datad (1842:1842:1842) (1816:1816:1816)) + (IOPATH dataa combout (318:318:318) (323:323:323)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -20229,47 +18657,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~40) + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~37) (DELAY (ABSOLUTE - (PORT dataa (182:182:182) (219:219:219)) - (PORT datab (848:848:848) (862:862:862)) - (PORT datac (174:174:174) (206:206:206)) - (PORT datad (297:297:297) (298:298:298)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1554:1554:1554) (1565:1565:1565)) - (PORT datab (1312:1312:1312) (1351:1351:1351)) - (PORT datac (580:580:580) (585:585:585)) - (PORT datad (792:792:792) (769:769:769)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1337:1337:1337) (1346:1346:1346)) - (PORT datab (783:783:783) (774:774:774)) - (PORT datac (772:772:772) (771:771:771)) - (PORT datad (1291:1291:1291) (1267:1267:1267)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) + (PORT dataa (1302:1302:1302) (1326:1326:1326)) + (PORT datab (1519:1519:1519) (1531:1531:1531)) + (PORT datac (154:154:154) (184:184:184)) + (PORT datad (1141:1141:1141) (1170:1170:1170)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (267:267:267) (275:275:275)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -20277,314 +18673,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R) + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~32) (DELAY (ABSOLUTE - (PORT dataa (779:779:779) (768:768:768)) - (PORT datab (1647:1647:1647) (1590:1590:1590)) - (PORT datac (567:567:567) (568:568:568)) - (PORT datad (762:762:762) (748:748:748)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[3\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1101:1101:1101) (1125:1125:1125)) - (PORT datab (199:199:199) (241:241:241)) - (PORT datac (845:845:845) (862:862:862)) - (PORT datad (571:571:571) (566:566:566)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[3\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (240:240:240) (306:306:306)) - (PORT datab (883:883:883) (904:904:904)) - (PORT datac (493:493:493) (487:487:487)) - (PORT datad (1039:1039:1039) (999:999:999)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_high\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1350:1350:1350) (1356:1356:1356)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (745:745:745) (751:751:751)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[3\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (555:555:555) (599:599:599)) - (PORT datab (1031:1031:1031) (1053:1053:1053)) - (PORT datac (547:547:547) (538:538:538)) - (PORT datad (364:364:364) (394:394:394)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[3\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (240:240:240) (311:311:311)) - (PORT datab (183:183:183) (216:216:216)) - (PORT datac (517:517:517) (522:522:522)) - (PORT datad (839:839:839) (865:865:865)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_low\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1350:1350:1350) (1356:1356:1356)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (745:745:745) (751:751:751)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op2\[3\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (391:391:391) (459:459:459)) - (PORT datab (386:386:386) (447:447:447)) - (PORT datac (803:803:803) (806:806:806)) - (PORT datad (608:608:608) (621:621:621)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|SYNTHESIZED_WIRE_10\~1) - (DELAY - (ABSOLUTE - (PORT dataa (189:189:189) (229:229:229)) - (PORT datab (584:584:584) (588:588:588)) - (PORT datac (325:325:325) (340:340:340)) - (PORT datad (769:769:769) (749:749:749)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|SYNTHESIZED_WIRE_10\~0) - (DELAY - (ABSOLUTE - (PORT dataa (360:360:360) (376:376:376)) - (PORT datab (601:601:601) (629:629:629)) - (PORT datac (594:594:594) (618:618:618)) - (PORT datad (590:590:590) (589:589:589)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|cy_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (390:390:390) (393:393:393)) - (PORT datab (214:214:214) (257:257:257)) - (PORT datac (164:164:164) (197:197:197)) - (PORT datad (165:165:165) (187:187:187)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf\~0) - (DELAY - (ABSOLUTE - (PORT dataa (652:652:652) (659:659:659)) - (PORT datab (1092:1092:1092) (1142:1142:1142)) - (PORT datac (795:795:795) (806:806:806)) - (PORT datad (620:620:620) (631:631:631)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1189:1189:1189) (1229:1229:1229)) - (PORT datab (1813:1813:1813) (1842:1842:1842)) - (PORT datac (1365:1365:1365) (1399:1399:1399)) - (PORT datad (1379:1379:1379) (1403:1403:1403)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1051:1051:1051) (1044:1044:1044)) - (PORT datab (560:560:560) (584:584:584)) - (PORT datac (766:766:766) (737:737:737)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf\~1) - (DELAY - (ABSOLUTE - (PORT dataa (191:191:191) (232:232:232)) + (PORT dataa (182:182:182) (218:218:218)) (PORT datab (180:180:180) (212:212:212)) - (PORT datad (743:743:743) (721:721:721)) + (PORT datac (155:155:155) (185:185:185)) + (PORT datad (758:758:758) (739:739:739)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~33) + (DELAY + (ABSOLUTE + (PORT dataa (326:326:326) (341:341:341)) + (PORT datab (900:900:900) (928:928:928)) + (PORT datac (156:156:156) (187:187:187)) + (PORT datad (558:558:558) (580:580:580)) (IOPATH dataa combout (329:329:329) (332:332:332)) (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf) - (DELAY - (ABSOLUTE - (PORT clk (1336:1336:1336) (1353:1353:1353)) - (PORT d (67:67:67) (78:78:78)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1078:1078:1078) (1068:1068:1068)) - (PORT datac (525:525:525) (522:522:522)) - (PORT datad (1507:1507:1507) (1518:1518:1518)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~12) - (DELAY - (ABSOLUTE - (PORT dataa (849:849:849) (829:829:829)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (1689:1689:1689) (1734:1734:1734)) - (PORT datad (520:520:520) (523:523:523)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~13) - (DELAY - (ABSOLUTE - (PORT dataa (352:352:352) (370:370:370)) - (PORT datab (1925:1925:1925) (1970:1970:1970)) - (PORT datac (1213:1213:1213) (1286:1286:1286)) - (PORT datad (835:835:835) (875:875:875)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|flags_hf) - (DELAY - (ABSOLUTE - (PORT dataa (359:359:359) (406:406:406)) - (PORT datab (566:566:566) (560:560:560)) - (PORT datac (1084:1084:1084) (1116:1116:1116)) - (PORT datad (762:762:762) (766:766:766)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (300:300:300) (312:312:312)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -20595,9 +18708,23 @@ (INSTANCE z80_\|alu_control_\|alu_core_cf_in\~0) (DELAY (ABSOLUTE - (PORT dataa (536:536:536) (529:529:529)) - (PORT datab (569:569:569) (564:564:564)) - (PORT datad (528:528:528) (509:509:509)) + (PORT dataa (586:586:586) (592:592:592)) + (PORT datab (783:783:783) (787:787:787)) + (PORT datac (781:781:781) (772:772:772)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op1\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1009:1009:1009) (1013:1013:1013)) + (PORT datab (878:878:878) (893:893:893)) + (PORT datad (540:540:540) (570:570:570)) (IOPATH dataa combout (329:329:329) (332:332:332)) (IOPATH datab combout (319:319:319) (307:307:307)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -20609,687 +18736,13 @@ (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|result\~0) (DELAY (ABSOLUTE - (PORT dataa (612:612:612) (609:609:609)) - (PORT datab (182:182:182) (215:215:215)) - (PORT datac (742:742:742) (717:717:717)) - (PORT datad (185:185:185) (209:209:209)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (308:308:308) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (1567:1567:1567) (1575:1575:1575)) - (PORT datab (848:848:848) (842:842:842)) - (PORT datac (817:817:817) (812:812:812)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[12\]) - (DELAY - (ABSOLUTE - (PORT datab (369:369:369) (402:402:402)) - (PORT datac (821:821:821) (818:818:818)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|Q\[12\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (293:293:293) (300:300:300)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[12\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1400:1400:1400) (1371:1371:1371)) - (PORT ena (1896:1896:1896) (1904:1904:1904)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|d0_out) - (DELAY - (ABSOLUTE - (PORT dataa (577:577:577) (566:566:566)) - (PORT datab (839:839:839) (828:828:828)) - (PORT datac (214:214:214) (291:291:291)) - (PORT datad (540:540:540) (567:567:567)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1364:1364:1364)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1196:1196:1196) (1178:1178:1178)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1355:1355:1355) (1376:1376:1376)) - (PORT asdata (1164:1164:1164) (1172:1172:1172)) - (PORT ena (857:857:857) (835:835:835)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (383:383:383) (408:408:408)) - (PORT datab (379:379:379) (396:396:396)) - (PORT datad (177:177:177) (197:197:197)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (625:625:625) (638:638:638)) - (PORT datac (196:196:196) (263:263:263)) - (PORT datad (716:716:716) (727:727:727)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (368:368:368) (369:369:369)) - (PORT datab (786:786:786) (780:780:780)) - (PORT datac (630:630:630) (636:636:636)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1343:1343:1343) (1360:1360:1360)) - (PORT asdata (1869:1869:1869) (1838:1838:1838)) - (PORT ena (716:716:716) (714:714:714)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~62) - (DELAY - (ABSOLUTE - (PORT dataa (379:379:379) (391:391:391)) - (PORT datab (1072:1072:1072) (1080:1080:1080)) - (PORT datad (694:694:694) (665:665:665)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1355:1355:1355) (1376:1376:1376)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1347:1347:1347) (1329:1329:1329)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1343:1343:1343) (1360:1360:1360)) - (PORT asdata (1869:1869:1869) (1835:1835:1835)) - (PORT ena (1140:1140:1140) (1144:1144:1144)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~63) - (DELAY - (ABSOLUTE - (PORT dataa (643:643:643) (688:688:688)) - (PORT datab (813:813:813) (820:820:820)) - (PORT datad (802:802:802) (793:793:793)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1361:1361:1361)) - (PORT asdata (1261:1261:1261) (1287:1287:1287)) - (PORT ena (1118:1118:1118) (1094:1094:1094)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1361:1361:1361)) - (PORT asdata (1260:1260:1260) (1289:1289:1289)) - (PORT ena (716:716:716) (714:714:714)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~61) - (DELAY - (ABSOLUTE - (PORT dataa (839:839:839) (857:857:857)) - (PORT datab (218:218:218) (260:260:260)) - (PORT datad (197:197:197) (253:253:253)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[4\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1284:1284:1284) (1247:1247:1247)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1362:1362:1362)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1093:1093:1093) (1070:1070:1070)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1362:1362:1362)) - (PORT asdata (1583:1583:1583) (1534:1534:1534)) - (PORT ena (1173:1173:1173) (1169:1169:1169)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~60) - (DELAY - (ABSOLUTE - (PORT dataa (363:363:363) (411:411:411)) - (PORT datab (1472:1472:1472) (1470:1470:1470)) - (PORT datad (1096:1096:1096) (1083:1083:1083)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~64) - (DELAY - (ABSOLUTE - (PORT dataa (184:184:184) (221:221:221)) + (PORT dataa (182:182:182) (217:217:217)) (PORT datab (180:180:180) (212:212:212)) - (PORT datac (749:749:749) (726:726:726)) - (PORT datad (565:565:565) (572:572:572)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1346:1346:1346) (1363:1363:1363)) - (PORT asdata (1722:1722:1722) (1763:1763:1763)) - (PORT ena (1271:1271:1271) (1296:1296:1296)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1346:1346:1346) (1363:1363:1363)) - (PORT asdata (1722:1722:1722) (1763:1763:1763)) - (PORT ena (1281:1281:1281) (1292:1292:1292)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~59) - (DELAY - (ABSOLUTE - (PORT dataa (832:832:832) (894:894:894)) - (PORT datab (827:827:827) (886:886:886)) - (PORT datad (196:196:196) (252:252:252)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT asdata (1788:1788:1788) (1721:1721:1721)) - (PORT ena (906:906:906) (905:905:905)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT asdata (1785:1785:1785) (1721:1721:1721)) - (PORT ena (893:893:893) (877:877:877)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~58) - (DELAY - (ABSOLUTE - (PORT dataa (428:428:428) (473:473:473)) - (PORT datab (449:449:449) (482:482:482)) - (PORT datad (198:198:198) (254:254:254)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1346:1346:1346) (1363:1363:1363)) - (PORT asdata (1719:1719:1719) (1758:1758:1758)) - (PORT ena (720:720:720) (722:722:722)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[4\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (868:868:868) (888:888:888)) - (PORT datab (1114:1114:1114) (1157:1157:1157)) - (PORT datad (832:832:832) (841:841:841)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~65) - (DELAY - (ABSOLUTE - (PORT dataa (610:610:610) (616:616:616)) - (PORT datab (308:308:308) (325:325:325)) - (PORT datac (541:541:541) (534:534:534)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~66) - (DELAY - (ABSOLUTE - (PORT dataa (816:816:816) (863:863:863)) - (PORT datab (772:772:772) (825:825:825)) - (PORT datac (786:786:786) (755:755:755)) - (PORT datad (1208:1208:1208) (1196:1196:1196)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[4\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1180:1180:1180) (1212:1212:1212)) - (PORT datab (897:897:897) (908:908:908)) - (PORT datac (817:817:817) (809:809:809)) - (PORT datad (1327:1327:1327) (1311:1311:1311)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[7\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (1168:1168:1168) (1194:1194:1194)) - (PORT datab (1141:1141:1141) (1122:1122:1122)) - (PORT datac (845:845:845) (859:859:859)) - (PORT datad (861:861:861) (871:871:871)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[4\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (188:188:188) (226:226:226)) - (PORT datab (227:227:227) (274:274:274)) - (PORT datac (995:995:995) (950:950:950)) - (PORT datad (877:877:877) (892:892:892)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1187:1187:1187) (1217:1217:1217)) - (PORT datab (863:863:863) (907:907:907)) - (PORT datac (348:348:348) (357:357:357)) - (PORT datad (1116:1116:1116) (1172:1172:1172)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1023:1023:1023) (1113:1113:1113)) - (PORT datab (1690:1690:1690) (1727:1727:1727)) - (PORT datac (819:819:819) (847:847:847)) - (PORT datad (1442:1442:1442) (1492:1492:1492)) + (PORT datac (958:958:958) (936:936:936)) + (PORT datad (165:165:165) (187:187:187)) (IOPATH dataa combout (300:300:300) (323:323:323)) (IOPATH datab combout (308:308:308) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~4) - (DELAY - (ABSOLUTE - (PORT dataa (856:856:856) (881:881:881)) - (PORT datab (588:588:588) (597:597:597)) - (PORT datac (1286:1286:1286) (1346:1346:1346)) - (PORT datad (544:544:544) (546:546:546)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (186:186:186) (224:224:224)) - (PORT datac (860:860:860) (864:864:864)) - (PORT datad (220:220:220) (254:254:254)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1095:1095:1095) (1096:1096:1096)) - (PORT datab (251:251:251) (320:320:320)) - (PORT datac (223:223:223) (275:275:275)) - (PORT datad (225:225:225) (262:262:262)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[0\]) - (DELAY - (ABSOLUTE - (PORT datab (334:334:334) (356:356:356)) - (PORT datac (857:857:857) (887:887:887)) - (PORT datad (625:625:625) (655:655:655)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_high\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1350:1350:1350) (1357:1357:1357)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (745:745:745) (751:751:751)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (593:593:593) (623:623:623)) - (PORT datab (1072:1072:1072) (1085:1085:1085)) - (PORT datac (595:595:595) (626:626:626)) - (PORT datad (619:619:619) (635:635:635)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -21299,56 +18752,12 @@ (INSTANCE z80_\|alu_\|db_high\[0\]\~25) (DELAY (ABSOLUTE - (PORT dataa (559:559:559) (560:560:560)) - (PORT datab (306:306:306) (321:321:321)) - (PORT datac (1071:1071:1071) (1088:1088:1088)) - (PORT datad (504:504:504) (485:485:485)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (603:603:603) (606:606:606)) - (PORT datab (919:919:919) (929:929:929)) - (PORT datac (156:156:156) (186:186:186)) - (PORT datad (199:199:199) (238:238:238)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[0\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (556:556:556) (543:543:543)) - (PORT datab (889:889:889) (910:910:910)) - (PORT datac (799:799:799) (810:810:810)) - (PORT datad (312:312:312) (322:322:322)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[0\]\~8) - (DELAY - (ABSOLUTE - (PORT datac (157:157:157) (188:188:188)) - (PORT datad (619:619:619) (648:648:648)) + (PORT dataa (346:346:346) (354:354:354)) + (PORT datab (348:348:348) (362:362:362)) + (PORT datac (781:781:781) (797:797:797)) + (PORT datad (999:999:999) (953:953:953)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -21356,59 +18765,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|ena) + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[0\]\~6) (DELAY (ABSOLUTE - (PORT dataa (842:842:842) (853:853:853)) - (PORT datab (670:670:670) (693:693:693)) - (PORT datac (859:859:859) (885:885:885)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_low\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1350:1350:1350) (1357:1357:1357)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (716:716:716) (714:714:714)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op1\[0\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (601:601:601) (607:607:607)) - (PORT datab (590:590:590) (623:623:623)) - (PORT datac (566:566:566) (594:594:594)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[0\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (584:584:584) (583:583:583)) - (PORT datab (874:874:874) (897:897:897)) - (PORT datac (1004:1004:1004) (1034:1034:1034)) - (PORT datad (536:536:536) (536:536:536)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (275:275:275) (275:275:275)) + (PORT dataa (588:588:588) (596:596:596)) + (PORT datab (605:605:605) (626:626:626)) + (PORT datac (842:842:842) (837:837:837)) + (PORT datad (575:575:575) (602:602:602)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -21416,22 +18781,22 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[0\]\~7) + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[0\]\~7) (DELAY (ABSOLUTE - (PORT dataa (240:240:240) (311:311:311)) - (PORT datac (156:156:156) (186:186:186)) - (IOPATH dataa combout (318:318:318) (327:327:327)) + (PORT datab (838:838:838) (838:838:838)) + (PORT datac (157:157:157) (188:188:188)) + (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (220:220:220) (216:216:216)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_low\[0\]) + (INSTANCE z80_\|alu_\|op2_high\[0\]) (DELAY (ABSOLUTE - (PORT clk (1350:1350:1350) (1356:1356:1356)) + (PORT clk (1356:1356:1356) (1366:1366:1366)) (PORT d (67:67:67) (78:78:78)) (PORT ena (745:745:745) (751:751:751)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) @@ -21447,11 +18812,11 @@ (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_10\~0) (DELAY (ABSOLUTE - (PORT dataa (397:397:397) (467:467:467)) - (PORT datac (596:596:596) (629:629:629)) - (PORT datad (609:609:609) (628:628:628)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT dataa (380:380:380) (432:432:432)) + (PORT datab (374:374:374) (387:387:387)) + (PORT datad (372:372:372) (409:409:409)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -21461,10 +18826,10 @@ (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_10\~1) (DELAY (ABSOLUTE - (PORT dataa (549:549:549) (534:534:534)) - (PORT datab (765:765:765) (758:758:758)) - (PORT datac (740:740:740) (715:715:715)) - (PORT datad (184:184:184) (209:209:209)) + (PORT dataa (607:607:607) (594:594:594)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (956:956:956) (936:936:936)) + (PORT datad (165:165:165) (189:189:189)) (IOPATH dataa combout (318:318:318) (327:327:327)) (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (220:220:220) (216:216:216)) @@ -21477,58 +18842,10 @@ (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|cy_out\~0) (DELAY (ABSOLUTE - (PORT dataa (625:625:625) (629:629:629)) - (PORT datab (188:188:188) (223:223:223)) - (PORT datac (182:182:182) (217:217:217)) - (PORT datad (758:758:758) (742:742:742)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op1\[1\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (604:604:604) (606:606:606)) - (PORT datab (582:582:582) (628:628:628)) - (PORT datad (583:583:583) (615:615:615)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_10\~0) - (DELAY - (ABSOLUTE - (PORT dataa (621:621:621) (621:621:621)) - (PORT datab (801:801:801) (784:784:784)) - (PORT datac (163:163:163) (197:197:197)) - (PORT datad (480:480:480) (472:472:472)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (187:187:187) (226:226:226)) - (PORT datab (192:192:192) (232:232:232)) - (PORT datac (181:181:181) (215:215:215)) - (PORT datad (167:167:167) (191:191:191)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) + (PORT datab (1267:1267:1267) (1296:1296:1296)) + (PORT datac (974:974:974) (1014:1014:1014)) + (PORT datad (166:166:166) (190:190:190)) + (IOPATH datab combout (308:308:308) (300:300:300)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -21536,89 +18853,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op1\[2\]\~2) + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_1) (DELAY (ABSOLUTE - (PORT dataa (585:585:585) (633:633:633)) - (PORT datab (616:616:616) (621:621:621)) - (PORT datad (567:567:567) (579:579:579)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_10\~1) - (DELAY - (ABSOLUTE - (PORT dataa (343:343:343) (365:365:365)) - (PORT datab (585:585:585) (589:589:589)) - (PORT datac (163:163:163) (195:195:195)) - (PORT datad (768:768:768) (749:749:749)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|cy_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (358:358:358) (368:368:368)) - (PORT datab (368:368:368) (374:374:374)) - (PORT datac (161:161:161) (194:194:194)) - (PORT datad (340:340:340) (345:345:345)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~5) - (DELAY - (ABSOLUTE - (PORT datac (1618:1618:1618) (1563:1563:1563)) - (PORT datad (762:762:762) (748:748:748)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|SYNTHESIZED_WIRE_1) - (DELAY - (ABSOLUTE - (PORT dataa (347:347:347) (363:363:363)) - (PORT datab (210:210:210) (251:251:251)) - (PORT datac (160:160:160) (193:193:193)) - (PORT datad (164:164:164) (187:187:187)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|result\~0) - (DELAY - (ABSOLUTE - (PORT dataa (190:190:190) (231:231:231)) - (PORT datab (212:212:212) (254:254:254)) - (PORT datac (325:325:325) (338:338:338)) - (PORT datad (159:159:159) (180:180:180)) + (PORT dataa (364:364:364) (380:380:380)) + (PORT datab (188:188:188) (221:221:221)) + (PORT datac (1009:1009:1009) (988:988:988)) + (PORT datad (172:172:172) (197:197:197)) (IOPATH dataa combout (307:307:307) (280:280:280)) (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|result\~0) + (DELAY + (ABSOLUTE + (PORT dataa (365:365:365) (381:381:381)) + (PORT datab (320:320:320) (340:340:340)) + (PORT datac (154:154:154) (184:184:184)) + (PORT datad (173:173:173) (200:200:200)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -21626,829 +18885,135 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[7\]\~feeder) + (INSTANCE z80_\|alu_\|db_high\[1\]\~14) (DELAY (ABSOLUTE - (PORT datad (987:987:987) (994:994:994)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1362:1362:1362)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1093:1093:1093) (1070:1070:1070)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1362:1362:1362)) - (PORT asdata (1322:1322:1322) (1333:1333:1333)) - (PORT ena (1173:1173:1173) (1169:1169:1169)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~69) - (DELAY - (ABSOLUTE - (PORT dataa (222:222:222) (295:295:295)) - (PORT datab (1475:1475:1475) (1473:1473:1473)) - (PORT datad (1095:1095:1095) (1089:1089:1089)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1361:1361:1361)) - (PORT asdata (1514:1514:1514) (1542:1542:1542)) - (PORT ena (1118:1118:1118) (1094:1094:1094)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1361:1361:1361)) - (PORT asdata (1512:1512:1512) (1538:1538:1538)) - (PORT ena (716:716:716) (714:714:714)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~70) - (DELAY - (ABSOLUTE - (PORT dataa (836:836:836) (854:854:854)) - (PORT datab (219:219:219) (261:261:261)) - (PORT datad (199:199:199) (256:256:256)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1355:1355:1355) (1376:1376:1376)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1347:1347:1347) (1329:1329:1329)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1343:1343:1343) (1360:1360:1360)) - (PORT asdata (1287:1287:1287) (1329:1329:1329)) - (PORT ena (1140:1140:1140) (1144:1144:1144)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~72) - (DELAY - (ABSOLUTE - (PORT dataa (657:657:657) (702:702:702)) - (PORT datab (813:813:813) (820:820:820)) - (PORT datad (802:802:802) (793:793:793)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1343:1343:1343) (1360:1360:1360)) - (PORT asdata (1287:1287:1287) (1330:1330:1330)) - (PORT ena (716:716:716) (714:714:714)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~71) - (DELAY - (ABSOLUTE - (PORT dataa (1299:1299:1299) (1263:1263:1263)) - (PORT datab (1074:1074:1074) (1082:1082:1082)) - (PORT datad (218:218:218) (251:251:251)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) + (PORT dataa (253:253:253) (322:322:322)) + (PORT datab (246:246:246) (307:307:307)) + (PORT datac (1010:1010:1010) (1020:1020:1020)) + (PORT datad (221:221:221) (262:262:262)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~73) + (INSTANCE z80_\|alu_\|db_high\[1\]\~15) (DELAY (ABSOLUTE - (PORT dataa (764:764:764) (758:758:758)) - (PORT datab (991:991:991) (1012:1012:1012)) - (PORT datac (156:156:156) (187:187:187)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT asdata (1326:1326:1326) (1339:1339:1339)) - (PORT ena (906:906:906) (905:905:905)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT asdata (1324:1324:1324) (1338:1338:1338)) - (PORT ena (893:893:893) (877:877:877)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~67) - (DELAY - (ABSOLUTE - (PORT dataa (429:429:429) (477:477:477)) - (PORT datab (450:450:450) (481:481:481)) - (PORT datad (197:197:197) (253:253:253)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1346:1346:1346) (1363:1363:1363)) - (PORT asdata (1262:1262:1262) (1284:1284:1284)) - (PORT ena (720:720:720) (722:722:722)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[7\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (871:871:871) (895:895:895)) - (PORT datab (1115:1115:1115) (1156:1156:1156)) - (PORT datad (827:827:827) (840:840:840)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1346:1346:1346) (1363:1363:1363)) - (PORT asdata (1086:1086:1086) (1125:1125:1125)) - (PORT ena (1271:1271:1271) (1296:1296:1296)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1346:1346:1346) (1363:1363:1363)) - (PORT asdata (1086:1086:1086) (1124:1124:1124)) - (PORT ena (1281:1281:1281) (1292:1292:1292)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~68) - (DELAY - (ABSOLUTE - (PORT dataa (828:828:828) (885:885:885)) - (PORT datab (825:825:825) (893:893:893)) - (PORT datad (198:198:198) (255:255:255)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) + (PORT dataa (224:224:224) (274:274:274)) + (PORT datab (809:809:809) (837:837:837)) + (PORT datac (553:553:553) (544:544:544)) + (PORT datad (536:536:536) (553:553:553)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~74) + (INSTANCE z80_\|alu_\|db_high\[1\]\~16) (DELAY (ABSOLUTE - (PORT dataa (362:362:362) (363:363:363)) - (PORT datab (586:586:586) (607:607:607)) - (PORT datac (586:586:586) (597:597:597)) - (PORT datad (726:726:726) (777:777:777)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1355:1355:1355) (1376:1376:1376)) - (PORT asdata (1039:1039:1039) (1059:1059:1059)) - (PORT ena (857:857:857) (835:835:835)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (240:240:240)) - (PORT datab (374:374:374) (393:393:393)) - (PORT datad (364:364:364) (377:377:377)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1364:1364:1364)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1196:1196:1196) (1178:1178:1178)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (730:730:730) (777:777:777)) - (PORT datac (193:193:193) (259:259:259)) - (PORT datad (600:600:600) (600:600:600)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|SYNTHESIZED_WIRE_0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (576:576:576) (563:563:563)) - (PORT datab (843:843:843) (835:835:835)) - (PORT datac (213:213:213) (287:287:287)) - (PORT datad (539:539:539) (564:564:564)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|d1_out) - (DELAY - (ABSOLUTE - (PORT datac (232:232:232) (309:309:309)) - (PORT datad (169:169:169) (199:199:199)) + (PORT dataa (530:530:530) (526:526:526)) + (PORT datac (881:881:881) (920:920:920)) + (PORT datad (326:326:326) (328:328:328)) + (IOPATH dataa combout (307:307:307) (306:306:306)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1361:1361:1361)) - (PORT asdata (1287:1287:1287) (1338:1338:1338)) - (PORT ena (1164:1164:1164) (1167:1167:1167)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1355:1355:1355) (1376:1376:1376)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1347:1347:1347) (1329:1329:1329)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~54) + (INSTANCE z80_\|alu_\|db_high\[1\]\~17) (DELAY (ABSOLUTE - (PORT dataa (1018:1018:1018) (1013:1013:1013)) - (PORT datab (817:817:817) (832:832:832)) - (PORT datad (611:611:611) (654:654:654)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1343:1343:1343) (1360:1360:1360)) - (PORT asdata (1879:1879:1879) (1893:1893:1893)) - (PORT ena (716:716:716) (714:714:714)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~53) - (DELAY - (ABSOLUTE - (PORT dataa (1533:1533:1533) (1489:1489:1489)) - (PORT datab (1071:1071:1071) (1076:1076:1076)) - (PORT datad (210:210:210) (243:243:243)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[5\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1017:1017:1017) (1055:1055:1055)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1362:1362:1362)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1093:1093:1093) (1070:1070:1070)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1362:1362:1362)) - (PORT asdata (1300:1300:1300) (1335:1335:1335)) - (PORT ena (1173:1173:1173) (1169:1169:1169)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~51) - (DELAY - (ABSOLUTE - (PORT dataa (358:358:358) (408:408:408)) - (PORT datab (1474:1474:1474) (1477:1477:1477)) - (PORT datad (1095:1095:1095) (1089:1089:1089)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1361:1361:1361)) - (PORT asdata (1647:1647:1647) (1670:1670:1670)) - (PORT ena (716:716:716) (714:714:714)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1361:1361:1361)) - (PORT asdata (1288:1288:1288) (1337:1337:1337)) - (PORT ena (1039:1039:1039) (993:993:993)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~52) - (DELAY - (ABSOLUTE - (PORT dataa (387:387:387) (427:427:427)) - (PORT datab (808:808:808) (830:830:830)) - (PORT datad (339:339:339) (347:347:347)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~55) - (DELAY - (ABSOLUTE - (PORT dataa (184:184:184) (221:221:221)) - (PORT datab (310:310:310) (329:329:329)) - (PORT datac (736:736:736) (718:718:718)) - (PORT datad (161:161:161) (182:182:182)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT asdata (1322:1322:1322) (1359:1359:1359)) - (PORT ena (893:893:893) (877:877:877)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT asdata (1323:1323:1323) (1361:1361:1361)) - (PORT ena (906:906:906) (905:905:905)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~49) - (DELAY - (ABSOLUTE - (PORT dataa (426:426:426) (473:473:473)) - (PORT datab (219:219:219) (287:287:287)) - (PORT datad (416:416:416) (454:454:454)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1346:1346:1346) (1363:1363:1363)) - (PORT asdata (1580:1580:1580) (1596:1596:1596)) - (PORT ena (1281:1281:1281) (1292:1292:1292)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1346:1346:1346) (1363:1363:1363)) - (PORT asdata (1581:1581:1581) (1599:1599:1599)) - (PORT ena (1271:1271:1271) (1296:1296:1296)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~50) - (DELAY - (ABSOLUTE - (PORT dataa (832:832:832) (892:892:892)) - (PORT datab (222:222:222) (291:291:291)) - (PORT datad (800:800:800) (850:850:850)) - (IOPATH dataa combout (329:329:329) (332:332:332)) + (PORT dataa (783:783:783) (785:785:785)) + (PORT datab (586:586:586) (592:592:592)) + (PORT datad (1023:1023:1023) (1012:1012:1012)) + (IOPATH dataa combout (318:318:318) (323:323:323)) (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (591:591:591) (602:602:602)) + (PORT datab (591:591:591) (605:605:605)) + (PORT datac (635:635:635) (664:664:664)) + (PORT datad (548:548:548) (562:562:562)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[1\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (805:805:805) (828:828:828)) + (PORT datab (634:634:634) (645:645:645)) + (PORT datac (316:316:316) (329:329:329)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[1\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (869:869:869) (900:900:900)) + (PORT datab (820:820:820) (821:821:821)) + (PORT datac (597:597:597) (610:610:610)) + (PORT datad (572:572:572) (576:576:576)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[1\]\~5) + (DELAY + (ABSOLUTE + (PORT datac (810:810:810) (828:828:828)) + (PORT datad (159:159:159) (178:178:178)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[5\]) + (INSTANCE z80_\|alu_\|op1_low\[1\]) (DELAY (ABSOLUTE - (PORT clk (1346:1346:1346) (1363:1363:1363)) - (PORT asdata (1621:1621:1621) (1650:1650:1650)) + (PORT clk (1369:1369:1369) (1376:1376:1376)) + (PORT d (67:67:67) (78:78:78)) (PORT ena (720:720:720) (722:722:722)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[5\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (866:866:866) (890:890:890)) - (PORT datab (1113:1113:1113) (1157:1157:1157)) - (PORT datad (830:830:830) (842:842:842)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~56) - (DELAY - (ABSOLUTE - (PORT dataa (611:611:611) (615:615:615)) - (PORT datab (761:761:761) (785:785:785)) - (PORT datac (572:572:572) (565:565:565)) - (PORT datad (773:773:773) (752:752:752)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~57) - (DELAY - (ABSOLUTE - (PORT dataa (817:817:817) (861:861:861)) - (PORT datab (180:180:180) (211:211:211)) - (PORT datac (744:744:744) (776:776:776)) - (PORT datad (1208:1208:1208) (1193:1193:1193)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1355:1355:1355) (1376:1376:1376)) - (PORT asdata (1055:1055:1055) (1083:1083:1083)) - (PORT ena (857:857:857) (835:835:835)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (382:382:382) (408:408:408)) - (PORT datab (198:198:198) (232:232:232)) - (PORT datad (354:354:354) (365:365:365)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1364:1364:1364)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1196:1196:1196) (1178:1178:1178)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) (TIMINGCHECK (HOLD d (posedge clk) (144:144:144)) (HOLD ena (posedge clk) (144:144:144)) @@ -22456,27 +19021,71 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~14) + (INSTANCE z80_\|alu_control_\|out\[6\]\~0) (DELAY (ABSOLUTE - (PORT dataa (624:624:624) (637:637:637)) - (PORT datab (348:348:348) (378:378:378)) - (PORT datac (195:195:195) (262:262:262)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) + (PORT dataa (240:240:240) (312:312:312)) + (PORT datac (213:213:213) (279:279:279)) + (PORT datad (234:234:234) (291:291:291)) + (IOPATH dataa combout (307:307:307) (306:306:306)) (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~15) + (INSTANCE z80_\|alu_control_\|out\[6\]\~1) (DELAY (ABSOLUTE - (PORT dataa (530:530:530) (514:514:514)) - (PORT datab (791:791:791) (787:787:787)) - (PORT datac (633:633:633) (637:637:637)) - (PORT datad (159:159:159) (178:178:178)) + (PORT dataa (837:837:837) (885:885:885)) + (PORT datab (822:822:822) (825:825:825)) + (PORT datac (837:837:837) (885:885:885)) + (PORT datad (788:788:788) (818:818:818)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|out\[6\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (220:220:220)) + (PORT datab (193:193:193) (232:232:232)) + (PORT datac (622:622:622) (686:686:686)) + (PORT datad (792:792:792) (823:823:823)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_12) + (DELAY + (ABSOLUTE + (PORT datac (622:622:622) (641:641:641)) + (PORT datad (789:789:789) (794:794:794)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_37\~0) + (DELAY + (ABSOLUTE + (PORT dataa (250:250:250) (326:326:326)) + (PORT datab (2012:2012:2012) (2029:2029:2029)) + (PORT datac (854:854:854) (864:864:864)) + (PORT datad (2071:2071:2071) (2092:2092:2092)) (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (267:267:267) (275:275:275)) (IOPATH datac combout (218:218:218) (215:215:215)) @@ -22486,37 +19095,105 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[13\]) + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11\~2) (DELAY (ABSOLUTE - (PORT datab (351:351:351) (381:381:381)) - (PORT datac (821:821:821) (822:822:822)) + (PORT dataa (653:653:653) (682:682:682)) + (PORT datab (635:635:635) (653:653:653)) + (PORT datac (572:572:572) (580:580:580)) + (PORT datad (573:573:573) (578:578:578)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11\~0) + (DELAY + (ABSOLUTE + (PORT dataa (643:643:643) (659:659:659)) + (PORT datab (344:344:344) (357:357:357)) + (PORT datac (174:174:174) (206:206:206)) + (PORT datad (164:164:164) (189:189:189)) + (IOPATH dataa combout (287:287:287) (280:280:280)) (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|Q\[13\]\~feeder) + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11\~1) (DELAY (ABSOLUTE - (PORT datad (312:312:312) (317:317:317)) + (PORT dataa (344:344:344) (360:360:360)) + (PORT datab (833:833:833) (830:830:830)) + (PORT datac (341:341:341) (342:342:342)) + (PORT datad (318:318:318) (319:319:319)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_37\~1) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (218:218:218)) + (PORT datab (182:182:182) (215:215:215)) + (PORT datac (769:769:769) (754:754:754)) + (PORT datad (314:314:314) (315:315:315)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~7) + (DELAY + (ABSOLUTE + (PORT datac (1352:1352:1352) (1390:1390:1390)) + (PORT datad (536:536:536) (539:539:539)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1095:1095:1095) (1093:1093:1093)) + (PORT datab (822:822:822) (829:829:829)) + (PORT datac (299:299:299) (313:313:313)) + (PORT datad (560:560:560) (574:574:574)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[13\]) + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_39) (DELAY (ABSOLUTE (PORT clk (1345:1345:1345) (1363:1363:1363)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1400:1400:1400) (1371:1371:1371)) - (PORT ena (1896:1896:1896) (1904:1904:1904)) + (PORT ena (1116:1116:1116) (1099:1099:1099)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) ) (TIMINGCHECK @@ -22526,121 +19203,174 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_53\~0) + (INSTANCE z80_\|execute_\|setM1\~51) (DELAY (ABSOLUTE - (PORT datac (232:232:232) (309:309:309)) - (PORT datad (805:805:805) (797:797:797)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[15\]) - (DELAY - (ABSOLUTE - (PORT datac (333:333:333) (341:341:341)) - (PORT datad (803:803:803) (800:800:800)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[15\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1400:1400:1400) (1371:1371:1371)) - (PORT ena (1896:1896:1896) (1904:1904:1904)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[14\]) - (DELAY - (ABSOLUTE - (PORT dataa (260:260:260) (341:341:341)) - (PORT datab (196:196:196) (235:235:235)) - (PORT datac (221:221:221) (291:291:291)) - (PORT datad (802:802:802) (798:798:798)) + (PORT dataa (1325:1325:1325) (1279:1279:1279)) + (PORT datab (793:793:793) (829:829:829)) + (PORT datac (783:783:783) (789:789:789)) + (PORT datad (821:821:821) (799:799:799)) (IOPATH dataa combout (318:318:318) (327:327:327)) (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_oe\~2) + (DELAY + (ABSOLUTE + (PORT dataa (544:544:544) (534:534:534)) + (PORT datab (803:803:803) (798:798:798)) + (PORT datac (903:903:903) (918:918:918)) + (PORT datad (1065:1065:1065) (1084:1084:1084)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~7) + (DELAY + (ABSOLUTE + (PORT dataa (809:809:809) (821:821:821)) + (PORT datab (1222:1222:1222) (1252:1252:1252)) + (PORT datac (757:757:757) (731:731:731)) + (PORT datad (511:511:511) (498:498:498)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[6\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (835:835:835) (824:824:824)) + (PORT datab (661:661:661) (704:704:704)) + (PORT datac (768:768:768) (757:757:757)) + (PORT datad (510:510:510) (497:497:497)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[6\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[6\]\~21) (DELAY (ABSOLUTE - (PORT clk (1345:1345:1345) (1364:1364:1364)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1196:1196:1196) (1178:1178:1178)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (PORT dataa (1055:1055:1055) (1071:1071:1071)) + (PORT datab (194:194:194) (233:233:233)) + (PORT datac (168:168:168) (206:206:206)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT asdata (2087:2087:2087) (2176:2176:2176)) - (PORT ena (906:906:906) (905:905:905)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT asdata (2087:2087:2087) (2177:2177:2177)) - (PORT ena (893:893:893) (877:877:877)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~76) + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~8) (DELAY (ABSOLUTE - (PORT dataa (424:424:424) (472:472:472)) - (PORT datab (451:451:451) (487:487:487)) - (PORT datad (198:198:198) (255:255:255)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) + (PORT dataa (766:766:766) (761:761:761)) + (PORT datab (1031:1031:1031) (1032:1032:1032)) + (PORT datac (593:593:593) (601:601:601)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[6\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (797:797:797) (807:807:807)) + (PORT datab (813:813:813) (809:809:809)) + (PORT datac (579:579:579) (617:617:617)) + (PORT datad (971:971:971) (975:975:975)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[6\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (239:239:239)) + (PORT datab (385:385:385) (395:395:395)) + (PORT datac (330:330:330) (355:355:355)) + (PORT datad (160:160:160) (182:182:182)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[6\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (220:220:220)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (312:312:312) (323:323:323)) + (PORT datad (340:340:340) (344:344:344)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[6\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (581:581:581) (603:603:603)) + (PORT datab (866:866:866) (843:843:843)) + (PORT datac (532:532:532) (539:539:539)) + (PORT datad (630:630:630) (635:635:635)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[6\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (677:677:677) (694:694:694)) + (PORT datab (225:225:225) (286:286:286)) + (PORT datac (790:790:790) (777:777:777)) + (PORT datad (161:161:161) (182:182:182)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -22650,9 +19380,9 @@ (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[6\]) (DELAY (ABSOLUTE - (PORT clk (1343:1343:1343) (1360:1360:1360)) - (PORT asdata (1723:1723:1723) (1782:1782:1782)) - (PORT ena (716:716:716) (714:714:714)) + (PORT clk (1340:1340:1340) (1358:1358:1358)) + (PORT asdata (1320:1320:1320) (1291:1291:1291)) + (PORT ena (1109:1109:1109) (1079:1079:1079)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -22666,11 +19396,11 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~80) (DELAY (ABSOLUTE - (PORT dataa (763:763:763) (739:739:739)) - (PORT datab (1074:1074:1074) (1081:1081:1081)) - (PORT datad (219:219:219) (254:254:254)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) + (PORT dataa (1082:1082:1082) (1107:1107:1107)) + (PORT datab (1061:1061:1061) (1049:1049:1049)) + (PORT datad (366:366:366) (389:389:389)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -22678,12 +19408,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[6\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[6\]) (DELAY (ABSOLUTE - (PORT clk (1344:1344:1344) (1361:1361:1361)) - (PORT asdata (1085:1085:1085) (1135:1135:1135)) - (PORT ena (716:716:716) (714:714:714)) + (PORT clk (1341:1341:1341) (1359:1359:1359)) + (PORT asdata (1160:1160:1160) (1153:1153:1153)) + (PORT ena (1132:1132:1132) (1121:1121:1121)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -22694,12 +19424,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[6\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[6\]) (DELAY (ABSOLUTE - (PORT clk (1344:1344:1344) (1361:1361:1361)) - (PORT asdata (1949:1949:1949) (1996:1996:1996)) - (PORT ena (1039:1039:1039) (993:993:993)) + (PORT clk (1341:1341:1341) (1359:1359:1359)) + (PORT asdata (1165:1165:1165) (1157:1157:1157)) + (PORT ena (1076:1076:1076) (1031:1031:1031)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -22713,11 +19443,11 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~79) (DELAY (ABSOLUTE - (PORT dataa (365:365:365) (408:408:408)) - (PORT datab (809:809:809) (832:832:832)) - (PORT datad (339:339:339) (348:348:348)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) + (PORT dataa (635:635:635) (651:651:651)) + (PORT datab (235:235:235) (291:291:291)) + (PORT datad (199:199:199) (257:257:257)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -22728,25 +19458,9 @@ (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[6\]) (DELAY (ABSOLUTE - (PORT clk (1345:1345:1345) (1362:1362:1362)) - (PORT asdata (1324:1324:1324) (1348:1348:1348)) - (PORT ena (1173:1173:1173) (1169:1169:1169)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1362:1362:1362)) - (PORT asdata (1324:1324:1324) (1348:1348:1348)) - (PORT ena (1093:1093:1093) (1070:1070:1070)) + (PORT clk (1338:1338:1338) (1356:1356:1356)) + (PORT asdata (1320:1320:1320) (1293:1293:1293)) + (PORT ena (1126:1126:1126) (1110:1110:1110)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -22757,27 +19471,22 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~78) + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[6\]\~feeder) (DELAY (ABSOLUTE - (PORT dataa (1207:1207:1207) (1200:1200:1200)) - (PORT datab (1135:1135:1135) (1117:1117:1117)) - (PORT datad (195:195:195) (252:252:252)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) + (PORT datad (1005:1005:1005) (984:984:984)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[6\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[6\]) (DELAY (ABSOLUTE - (PORT clk (1355:1355:1355) (1376:1376:1376)) + (PORT clk (1338:1338:1338) (1356:1356:1356)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (1347:1347:1347) (1329:1329:1329)) + (PORT ena (1322:1322:1322) (1264:1264:1264)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -22786,32 +19495,16 @@ (HOLD ena (posedge clk) (144:144:144)) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1361:1361:1361)) - (PORT asdata (1951:1951:1951) (1996:1996:1996)) - (PORT ena (1164:1164:1164) (1167:1167:1167)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~81) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~78) (DELAY (ABSOLUTE - (PORT dataa (1019:1019:1019) (1008:1008:1008)) - (PORT datab (631:631:631) (669:669:669)) - (PORT datad (783:783:783) (794:794:794)) + (PORT dataa (645:645:645) (684:684:684)) + (PORT datab (597:597:597) (603:603:603)) + (PORT datad (197:197:197) (253:253:253)) (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -22822,10 +19515,10 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~82) (DELAY (ABSOLUTE - (PORT dataa (559:559:559) (554:554:554)) - (PORT datab (182:182:182) (214:214:214)) - (PORT datac (548:548:548) (544:544:544)) - (PORT datad (159:159:159) (180:180:180)) + (PORT dataa (784:784:784) (775:775:775)) + (PORT datab (517:517:517) (501:501:501)) + (PORT datac (528:528:528) (535:535:535)) + (PORT datad (316:316:316) (332:332:332)) (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) @@ -22838,25 +19531,9 @@ (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[6\]) (DELAY (ABSOLUTE - (PORT clk (1346:1346:1346) (1363:1363:1363)) - (PORT asdata (1096:1096:1096) (1141:1141:1141)) - (PORT ena (1271:1271:1271) (1296:1296:1296)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1346:1346:1346) (1363:1363:1363)) - (PORT asdata (1097:1097:1097) (1141:1141:1141)) - (PORT ena (1281:1281:1281) (1292:1292:1292)) + (PORT clk (1339:1339:1339) (1356:1356:1356)) + (PORT asdata (1091:1091:1091) (1072:1072:1072)) + (PORT ena (744:744:744) (751:751:751)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -22867,14 +19544,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~77) + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|db\[6\]\~5) (DELAY (ABSOLUTE - (PORT dataa (832:832:832) (890:890:890)) - (PORT datab (826:826:826) (887:887:887)) - (PORT datad (197:197:197) (253:253:253)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) + (PORT dataa (1319:1319:1319) (1320:1320:1320)) + (PORT datab (1099:1099:1099) (1086:1086:1086)) + (PORT datad (771:771:771) (753:753:753)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -22882,12 +19559,28 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[6\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[6\]) (DELAY (ABSOLUTE - (PORT clk (1346:1346:1346) (1363:1363:1363)) - (PORT asdata (1992:1992:1992) (1966:1966:1966)) - (PORT ena (720:720:720) (722:722:722)) + (PORT clk (1339:1339:1339) (1357:1357:1357)) + (PORT asdata (815:815:815) (824:824:824)) + (PORT ena (1170:1170:1170) (1151:1151:1151)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1356:1356:1356)) + (PORT asdata (856:856:856) (857:857:857)) + (PORT ena (898:898:898) (891:891:891)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -22898,14 +19591,55 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[6\]\~21) + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[6\]\~feeder) (DELAY (ABSOLUTE - (PORT dataa (872:872:872) (899:899:899)) - (PORT datab (1113:1113:1113) (1158:1158:1158)) - (PORT datad (825:825:825) (837:837:837)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) + (PORT datad (536:536:536) (535:535:535)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1356:1356:1356)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1093:1093:1093) (1055:1055:1055)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~76) + (DELAY + (ABSOLUTE + (PORT dataa (627:627:627) (642:642:642)) + (PORT datab (631:631:631) (647:647:647)) + (PORT datad (197:197:197) (254:254:254)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~77) + (DELAY + (ABSOLUTE + (PORT dataa (595:595:595) (602:602:602)) + (PORT datab (567:567:567) (567:567:567)) + (PORT datad (314:314:314) (314:314:314)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -22916,12 +19650,12 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~83) (DELAY (ABSOLUTE - (PORT dataa (590:590:590) (582:582:582)) - (PORT datab (585:585:585) (603:603:603)) - (PORT datac (460:460:460) (454:454:454)) - (PORT datad (158:158:158) (178:178:178)) + (PORT dataa (222:222:222) (295:295:295)) + (PORT datab (188:188:188) (225:225:225)) + (PORT datac (525:525:525) (503:503:503)) + (PORT datad (159:159:159) (180:180:180)) (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datab combout (267:267:267) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -22932,12 +19666,12 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~84) (DELAY (ABSOLUTE - (PORT dataa (814:814:814) (859:859:859)) - (PORT datab (618:618:618) (614:614:614)) - (PORT datac (722:722:722) (755:755:755)) - (PORT datad (1211:1211:1211) (1194:1194:1194)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) + (PORT dataa (798:798:798) (797:797:797)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (1017:1017:1017) (988:988:988)) + (PORT datad (558:558:558) (554:554:554)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -22948,9 +19682,9 @@ (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[6\]) (DELAY (ABSOLUTE - (PORT clk (1355:1355:1355) (1376:1376:1376)) - (PORT asdata (1035:1035:1035) (1063:1063:1063)) - (PORT ena (857:857:857) (835:835:835)) + (PORT clk (1341:1341:1341) (1358:1358:1358)) + (PORT asdata (621:621:621) (618:618:618)) + (PORT ena (1132:1132:1132) (1119:1119:1119)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -22964,9 +19698,9 @@ (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~22) (DELAY (ABSOLUTE - (PORT dataa (383:383:383) (415:415:415)) - (PORT datab (199:199:199) (233:233:233)) - (PORT datad (351:351:351) (363:363:363)) + (PORT dataa (618:618:618) (645:645:645)) + (PORT datab (826:826:826) (809:809:809)) + (PORT datad (577:577:577) (593:593:593)) (IOPATH dataa combout (309:309:309) (326:326:326)) (IOPATH datab combout (306:306:306) (324:324:324)) (IOPATH datac combout (312:312:312) (325:325:325)) @@ -22974,67 +19708,57 @@ ) ) ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1341:1341:1341) (1358:1358:1358)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1169:1169:1169) (1174:1174:1174)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~23) (DELAY (ABSOLUTE - (PORT dataa (223:223:223) (297:297:297)) - (PORT datab (620:620:620) (618:618:618)) - (PORT datad (600:600:600) (599:599:599)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) + (PORT dataa (326:326:326) (343:343:343)) + (PORT datab (221:221:221) (289:289:289)) + (PORT datad (969:969:969) (946:946:946)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~24) + (INSTANCE z80_\|address_latch_\|abusz\[13\]) (DELAY (ABSOLUTE - (PORT dataa (343:343:343) (354:354:354)) - (PORT datab (659:659:659) (664:664:664)) - (PORT datac (758:758:758) (750:750:750)) - (PORT datad (159:159:159) (179:179:179)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[14\]) - (DELAY - (ABSOLUTE - (PORT dataa (848:848:848) (851:851:851)) - (PORT datac (334:334:334) (355:355:355)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|Q\[14\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (302:302:302) (296:296:296)) + (PORT dataa (584:584:584) (598:598:598)) + (PORT datad (1011:1011:1011) (979:979:979)) + (IOPATH dataa combout (287:287:287) (289:289:289)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[14\]) + (INSTANCE z80_\|address_latch_\|Q\[13\]) (DELAY (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT clk (1340:1340:1340) (1357:1357:1357)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1400:1400:1400) (1371:1371:1371)) - (PORT ena (1896:1896:1896) (1904:1904:1904)) + (PORT clrn (1384:1384:1384) (1356:1356:1356)) + (PORT ena (1738:1738:1738) (1696:1696:1696)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -23046,252 +19770,93 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_16) + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|d0_out) (DELAY (ABSOLUTE - (PORT dataa (1056:1056:1056) (1060:1060:1060)) - (PORT datab (374:374:374) (427:427:427)) - (PORT datac (1030:1030:1030) (991:991:991)) - (PORT datad (586:586:586) (589:589:589)) + (PORT dataa (396:396:396) (446:446:446)) + (PORT datab (194:194:194) (234:234:234)) + (PORT datac (602:602:602) (630:630:630)) + (PORT datad (381:381:381) (418:418:418)) (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[15\]) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (219:219:219)) - (PORT datab (194:194:194) (233:233:233)) - (PORT datac (209:209:209) (281:281:281)) - (PORT datad (316:316:316) (319:319:319)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datab combout (308:308:308) (324:324:324)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~21) + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[4\]) (DELAY (ABSOLUTE - (PORT dataa (352:352:352) (370:370:370)) - (PORT datab (660:660:660) (671:671:671)) - (PORT datac (762:762:762) (758:758:758)) - (PORT datad (514:514:514) (503:503:503)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (PORT clk (1341:1341:1341) (1359:1359:1359)) + (PORT asdata (1122:1122:1122) (1107:1107:1107)) + (PORT ena (1132:1132:1132) (1121:1121:1121)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1341:1341:1341) (1359:1359:1359)) + (PORT asdata (1122:1122:1122) (1109:1109:1109)) + (PORT ena (1076:1076:1076) (1031:1031:1031)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~75) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~61) (DELAY (ABSOLUTE - (PORT dataa (813:813:813) (866:866:866)) - (PORT datab (615:615:615) (626:626:626)) - (PORT datac (726:726:726) (751:751:751)) - (PORT datad (1207:1207:1207) (1198:1198:1198)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[7\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (1175:1175:1175) (1203:1203:1203)) - (PORT datab (905:905:905) (909:909:909)) - (PORT datac (1722:1722:1722) (1740:1740:1740)) - (PORT datad (765:765:765) (752:752:752)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[7\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (187:187:187) (224:224:224)) - (PORT datab (231:231:231) (282:282:282)) - (PORT datac (1100:1100:1100) (1078:1078:1078)) - (PORT datad (870:870:870) (885:885:885)) - (IOPATH dataa combout (300:300:300) (323:323:323)) + (PORT dataa (639:639:639) (649:649:649)) + (PORT datab (238:238:238) (298:298:298)) + (PORT datad (196:196:196) (252:252:252)) + (IOPATH dataa combout (318:318:318) (327:327:327)) (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~1) + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[4\]) (DELAY (ABSOLUTE - (PORT dataa (860:860:860) (862:862:862)) - (PORT datab (1122:1122:1122) (1147:1147:1147)) - (PORT datac (839:839:839) (832:832:832)) - (PORT datad (1284:1284:1284) (1294:1294:1294)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (PORT clk (1340:1340:1340) (1358:1358:1358)) + (PORT asdata (1731:1731:1731) (1737:1737:1737)) + (PORT ena (1109:1109:1109) (1079:1079:1079)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~0) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~62) (DELAY (ABSOLUTE - (PORT dataa (832:832:832) (838:838:838)) - (PORT datab (614:614:614) (613:613:613)) - (PORT datac (614:614:614) (619:619:619)) - (PORT datad (621:621:621) (632:632:632)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1407:1407:1407) (1450:1450:1450)) - (PORT datab (1289:1289:1289) (1361:1361:1361)) - (PORT datac (1297:1297:1297) (1317:1317:1317)) - (PORT datad (780:780:780) (770:770:770)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (560:560:560) (564:564:564)) - (PORT datab (182:182:182) (215:215:215)) - (PORT datac (176:176:176) (207:207:207)) - (PORT datad (1005:1005:1005) (1002:1002:1002)) + (PORT dataa (1084:1084:1084) (1113:1113:1113)) + (PORT datab (825:825:825) (825:825:825)) + (PORT datad (373:373:373) (396:396:396)) (IOPATH dataa combout (309:309:309) (326:326:326)) (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1081:1081:1081) (1074:1074:1074)) - (PORT datab (912:912:912) (944:944:944)) - (PORT datac (190:190:190) (227:227:227)) - (PORT datad (1859:1859:1859) (1867:1867:1867)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (193:193:193) (236:236:236)) - (PORT datab (589:589:589) (575:575:575)) - (PORT datac (561:561:561) (550:550:550)) - (PORT datad (568:568:568) (566:566:566)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~2) - (DELAY - (ABSOLUTE - (PORT datab (642:642:642) (672:672:672)) - (PORT datac (1228:1228:1228) (1212:1212:1212)) - (PORT datad (1061:1061:1061) (1068:1068:1068)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1568:1568:1568) (1604:1604:1604)) - (PORT datab (1366:1366:1366) (1410:1410:1410)) - (PORT datac (2377:2377:2377) (2403:2403:2403)) - (PORT datad (1740:1740:1740) (1778:1778:1778)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1788:1788:1788) (1824:1824:1824)) - (PORT datab (182:182:182) (214:214:214)) - (PORT datac (842:842:842) (859:859:859)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~1) - (DELAY - (ABSOLUTE - (PORT dataa (586:586:586) (608:608:608)) - (PORT datab (590:590:590) (598:598:598)) - (PORT datad (809:809:809) (830:830:830)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -23299,162 +19864,130 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf) + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[4\]) (DELAY (ABSOLUTE - (PORT clk (1332:1332:1332) (1350:1350:1350)) + (PORT clk (1338:1338:1338) (1356:1356:1356)) + (PORT asdata (1069:1069:1069) (1059:1059:1059)) + (PORT ena (1126:1126:1126) (1110:1110:1110)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (569:569:569) (570:570:570)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1356:1356:1356)) (PORT d (67:67:67) (78:78:78)) + (PORT ena (1322:1322:1322) (1264:1264:1264)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) (TIMINGCHECK (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~0) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~60) (DELAY (ABSOLUTE - (PORT dataa (1103:1103:1103) (1149:1149:1149)) - (PORT datab (231:231:231) (304:304:304)) - (PORT datac (1255:1255:1255) (1261:1261:1261)) - (PORT datad (1099:1099:1099) (1117:1117:1117)) - (IOPATH dataa combout (300:300:300) (323:323:323)) + (PORT dataa (644:644:644) (682:682:682)) + (PORT datab (603:603:603) (610:610:610)) + (PORT datad (195:195:195) (252:252:252)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1340:1340:1340) (1358:1358:1358)) + (PORT asdata (1581:1581:1581) (1552:1552:1552)) + (PORT ena (1131:1131:1131) (1124:1124:1124)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1340:1340:1340) (1358:1358:1358)) + (PORT asdata (1580:1580:1580) (1551:1551:1551)) + (PORT ena (1376:1376:1376) (1350:1350:1350)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~63) + (DELAY + (ABSOLUTE + (PORT dataa (643:643:643) (690:690:690)) + (PORT datab (220:220:220) (288:288:288)) + (PORT datad (648:648:648) (659:659:659)) + (IOPATH dataa combout (309:309:309) (326:326:326)) (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~2) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~64) (DELAY (ABSOLUTE - (PORT dataa (182:182:182) (219:219:219)) - (PORT datab (179:179:179) (212:212:212)) - (PORT datad (1079:1079:1079) (1113:1113:1113)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~5) - (DELAY - (ABSOLUTE - (PORT datab (200:200:200) (234:234:234)) - (PORT datac (822:822:822) (821:821:821)) - (PORT datad (1281:1281:1281) (1295:1295:1295)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (385:385:385) (397:397:397)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (823:823:823) (829:829:829)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (391:391:391) (459:459:459)) - (PORT datab (1065:1065:1065) (1077:1077:1077)) - (PORT datac (550:550:550) (577:577:577)) - (PORT datad (618:618:618) (634:634:634)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (1093:1093:1093) (1092:1092:1092)) - (PORT datab (243:243:243) (309:309:309)) - (PORT datac (219:219:219) (274:274:274)) - (PORT datad (234:234:234) (271:271:271)) - (IOPATH dataa combout (329:329:329) (332:332:332)) + (PORT dataa (543:543:543) (529:529:529)) + (PORT datab (552:552:552) (556:556:556)) + (PORT datac (568:568:568) (561:561:561)) + (PORT datad (290:290:290) (298:298:298)) + (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (320:320:320) (333:333:333)) - (PORT datab (749:749:749) (742:742:742)) - (PORT datac (463:463:463) (447:447:447)) - (PORT datad (1014:1014:1014) (1005:1005:1005)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (557:557:557) (567:567:567)) - (PORT datab (920:920:920) (930:930:930)) - (PORT datac (542:542:542) (538:538:538)) - (PORT datad (200:200:200) (239:239:239)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[3\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (353:353:353) (361:361:361)) - (PORT datab (826:826:826) (839:839:839)) - (PORT datac (1063:1063:1063) (1038:1038:1038)) - (PORT datad (630:630:630) (650:650:650)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_low\[3\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[4\]) (DELAY (ABSOLUTE - (PORT clk (1350:1350:1350) (1357:1357:1357)) + (PORT clk (1339:1339:1339) (1357:1357:1357)) (PORT d (67:67:67) (78:78:78)) (PORT ena (716:716:716) (714:714:714)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) @@ -23466,16 +19999,125 @@ ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~9) + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[4\]) (DELAY (ABSOLUTE - (PORT dataa (641:641:641) (676:676:676)) - (PORT datab (1072:1072:1072) (1089:1089:1089)) - (PORT datac (571:571:571) (605:605:605)) - (PORT datad (621:621:621) (641:641:641)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) + (PORT clk (1339:1339:1339) (1356:1356:1356)) + (PORT asdata (1234:1234:1234) (1229:1229:1229)) + (PORT ena (744:744:744) (751:751:751)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|db\[4\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1321:1321:1321) (1320:1320:1320)) + (PORT datab (1098:1098:1098) (1083:1083:1083)) + (PORT datad (768:768:768) (750:750:750)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1357:1357:1357)) + (PORT asdata (848:848:848) (845:845:845)) + (PORT ena (1170:1170:1170) (1151:1151:1151)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1356:1356:1356)) + (PORT asdata (615:615:615) (633:633:633)) + (PORT ena (1093:1093:1093) (1055:1055:1055)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1356:1356:1356)) + (PORT asdata (619:619:619) (636:636:636)) + (PORT ena (898:898:898) (891:891:891)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~58) + (DELAY + (ABSOLUTE + (PORT dataa (627:627:627) (640:640:640)) + (PORT datab (221:221:221) (289:289:289)) + (PORT datad (574:574:574) (569:569:569)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~59) + (DELAY + (ABSOLUTE + (PORT dataa (595:595:595) (602:602:602)) + (PORT datab (592:592:592) (582:582:582)) + (PORT datad (316:316:316) (316:316:316)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~65) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (219:219:219)) + (PORT datab (188:188:188) (224:224:224)) + (PORT datac (196:196:196) (262:262:262)) + (PORT datad (160:160:160) (182:182:182)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -23483,40 +20125,59 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\~2) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~66) (DELAY (ABSOLUTE - (PORT datab (249:249:249) (315:315:315)) - (PORT datad (229:229:229) (266:266:266)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (250:250:250) (308:308:308)) - (PORT datab (583:583:583) (570:570:570)) - (PORT datac (1062:1062:1062) (1058:1058:1058)) - (PORT datad (159:159:159) (179:179:179)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT dataa (799:799:799) (799:799:799)) + (PORT datab (850:850:850) (832:832:832)) + (PORT datac (155:155:155) (186:186:186)) + (PORT datad (560:560:560) (553:553:553)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|result_lo\[3\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[4\]) (DELAY (ABSOLUTE - (PORT clk (1339:1339:1339) (1361:1361:1361)) + (PORT clk (1341:1341:1341) (1358:1358:1358)) + (PORT asdata (614:614:614) (620:620:620)) + (PORT ena (1132:1132:1132) (1119:1119:1119)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (618:618:618) (642:642:642)) + (PORT datab (1129:1129:1129) (1127:1127:1127)) + (PORT datad (577:577:577) (593:593:593)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1341:1341:1341) (1358:1358:1358)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (1177:1177:1177) (1162:1162:1162)) + (PORT ena (1169:1169:1169) (1174:1174:1174)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -23527,229 +20188,119 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~7) + (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~17) (DELAY (ABSOLUTE - (PORT dataa (893:893:893) (892:892:892)) - (PORT datac (1533:1533:1533) (1538:1538:1538)) - (PORT datad (1304:1304:1304) (1277:1277:1277)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1045:1045:1045) (1033:1033:1033)) - (PORT datab (1038:1038:1038) (1036:1036:1036)) - (PORT datac (156:156:156) (186:186:186)) - (PORT datad (220:220:220) (254:254:254)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (487:487:487) (476:476:476)) - (PORT datab (820:820:820) (835:835:835)) - (PORT datac (884:884:884) (892:892:892)) - (PORT datad (554:554:554) (543:543:543)) - (IOPATH dataa combout (273:273:273) (269:269:269)) + (PORT dataa (181:181:181) (217:217:217)) + (PORT datab (223:223:223) (292:292:292)) + (PORT datad (973:973:973) (951:951:951)) + (IOPATH dataa combout (318:318:318) (323:323:323)) (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~25) + (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~18) (DELAY (ABSOLUTE - (PORT dataa (1099:1099:1099) (1121:1121:1121)) - (PORT datab (575:575:575) (574:574:574)) - (PORT datac (171:171:171) (213:213:213)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[3\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (625:625:625) (626:626:626)) - (PORT datab (858:858:858) (851:851:851)) - (PORT datac (795:795:795) (793:793:793)) - (PORT datad (1069:1069:1069) (1065:1065:1065)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[3\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (593:593:593) (599:599:599)) - (PORT datab (897:897:897) (906:906:906)) - (PORT datac (1066:1066:1066) (1069:1069:1069)) - (PORT datad (202:202:202) (243:243:243)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~7) - (DELAY - (ABSOLUTE - (PORT dataa (210:210:210) (252:252:252)) - (PORT datab (1335:1335:1335) (1345:1345:1345)) - (PORT datac (1038:1038:1038) (1033:1033:1033)) - (PORT datad (163:163:163) (186:186:186)) + (PORT dataa (606:606:606) (605:605:605)) + (PORT datab (183:183:183) (216:216:216)) + (PORT datac (541:541:541) (541:541:541)) + (PORT datad (1237:1237:1237) (1229:1229:1229)) (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~49) - (DELAY - (ABSOLUTE - (PORT dataa (1109:1109:1109) (1129:1129:1129)) - (PORT datab (871:871:871) (866:866:866)) - (PORT datac (499:499:499) (489:489:489)) - (PORT datad (778:778:778) (762:762:762)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_oe\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1340:1340:1340) (1384:1384:1384)) - (PORT datab (199:199:199) (232:232:232)) - (PORT datac (209:209:209) (250:250:250)) - (PORT datad (1300:1300:1300) (1310:1310:1310)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_35) - (DELAY - (ABSOLUTE - (PORT dataa (599:599:599) (593:593:593)) - (PORT datab (568:568:568) (581:581:581)) - (PORT datac (609:609:609) (615:615:615)) - (PORT datad (626:626:626) (639:639:639)) - (IOPATH dataa combout (273:273:273) (269:269:269)) (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~7) + (INSTANCE z80_\|address_latch_\|abusz\[12\]) (DELAY (ABSOLUTE - (PORT datab (567:567:567) (590:590:590)) - (PORT datad (734:734:734) (793:793:793)) - (IOPATH datab combout (319:319:319) (324:324:324)) + (PORT dataa (618:618:618) (618:618:618)) + (PORT datac (558:558:558) (562:562:562)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1340:1340:1340) (1357:1357:1357)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1384:1384:1384) (1356:1356:1356)) + (PORT ena (1738:1738:1738) (1696:1696:1696)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|SYNTHESIZED_WIRE_0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (396:396:396) (446:446:446)) + (PORT datab (194:194:194) (234:234:234)) + (PORT datac (602:602:602) (630:630:630)) + (PORT datad (381:381:381) (418:418:418)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla69M2T2_3) + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[14\]) (DELAY (ABSOLUTE - (PORT dataa (592:592:592) (597:597:597)) - (PORT datab (2129:2129:2129) (2118:2118:2118)) - (PORT datac (1897:1897:1897) (1944:1944:1944)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~13) - (DELAY - (ABSOLUTE - (PORT dataa (353:353:353) (378:378:378)) - (PORT datab (1506:1506:1506) (1510:1510:1510)) - (PORT datac (771:771:771) (762:762:762)) - (PORT datad (163:163:163) (189:189:189)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~14) - (DELAY - (ABSOLUTE - (PORT dataa (749:749:749) (788:788:788)) - (PORT datab (327:327:327) (353:353:353)) - (PORT datac (157:157:157) (187:187:187)) - (PORT datad (166:166:166) (191:191:191)) + (PORT dataa (402:402:402) (446:446:446)) + (PORT datab (788:788:788) (795:795:795)) + (PORT datac (213:213:213) (292:292:292)) + (PORT datad (318:318:318) (332:332:332)) (IOPATH dataa combout (287:287:287) (280:280:280)) (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~15) + (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~24) (DELAY (ABSOLUTE - (PORT dataa (862:862:862) (884:884:884)) - (PORT datab (639:639:639) (644:644:644)) - (PORT datac (528:528:528) (512:512:512)) - (PORT datad (567:567:567) (575:575:575)) + (PORT dataa (1257:1257:1257) (1267:1267:1267)) + (PORT datab (567:567:567) (571:571:571)) + (PORT datac (156:156:156) (186:186:186)) + (PORT datad (584:584:584) (575:575:575)) (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[14\]) + (DELAY + (ABSOLUTE + (PORT datac (559:559:559) (563:563:563)) + (PORT datad (581:581:581) (572:572:572)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -23757,13 +20308,15 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|flags_xf) + (INSTANCE z80_\|address_latch_\|Q\[14\]) (DELAY (ABSOLUTE - (PORT clk (1336:1336:1336) (1353:1353:1353)) + (PORT clk (1340:1340:1340) (1357:1357:1357)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (745:745:745) (751:751:751)) + (PORT clrn (1384:1384:1384) (1356:1356:1356)) + (PORT ena (1738:1738:1738) (1696:1696:1696)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) ) (TIMINGCHECK @@ -23773,60 +20326,44 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[3\]\~33) + (INSTANCE z80_\|address_latch_\|abusz\[15\]) (DELAY (ABSOLUTE - (PORT datab (881:881:881) (876:876:876)) - (PORT datac (584:584:584) (610:610:610)) - (PORT datad (607:607:607) (634:634:634)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT dataa (587:587:587) (595:595:595)) + (PORT datad (565:565:565) (561:561:561)) + (IOPATH dataa combout (287:287:287) (289:289:289)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~3) + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[15\]) (DELAY (ABSOLUTE - (PORT dataa (324:324:324) (334:334:334)) - (PORT datab (190:190:190) (226:226:226)) - (PORT datac (160:160:160) (192:192:192)) - (PORT datad (592:592:592) (607:607:607)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (PORT clk (1340:1340:1340) (1357:1357:1357)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1384:1384:1384) (1356:1356:1356)) + (PORT ena (1738:1738:1738) (1696:1696:1696)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla23pla16M3T1_5\~0) + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[15\]\~0) (DELAY (ABSOLUTE - (PORT dataa (820:820:820) (804:804:804)) - (PORT datab (920:920:920) (947:947:947)) - (PORT datac (1321:1321:1321) (1376:1376:1376)) - (PORT datad (1057:1057:1057) (1052:1052:1052)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~4) - (DELAY - (ABSOLUTE - (PORT dataa (592:592:592) (617:617:617)) - (PORT datab (855:855:855) (865:865:865)) - (PORT datac (1341:1341:1341) (1367:1367:1367)) - (PORT datad (1066:1066:1066) (1053:1053:1053)) - (IOPATH dataa combout (318:318:318) (323:323:323)) + (PORT dataa (217:217:217) (267:267:267)) + (PORT datab (205:205:205) (247:247:247)) + (PORT datac (546:546:546) (557:557:557)) + (PORT datad (630:630:630) (673:673:673)) + (IOPATH dataa combout (307:307:307) (280:280:280)) (IOPATH datab combout (308:308:308) (281:281:281)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -23835,92 +20372,62 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~5) + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[15\]\~1) (DELAY (ABSOLUTE - (PORT dataa (590:590:590) (578:578:578)) - (PORT datab (187:187:187) (224:224:224)) - (PORT datac (820:820:820) (831:831:831)) - (PORT datad (176:176:176) (198:198:198)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT dataa (246:246:246) (329:329:329)) + (PORT datab (787:787:787) (794:794:794)) + (PORT datac (339:339:339) (391:391:391)) + (PORT datad (554:554:554) (556:556:556)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~8) + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[7\]) (DELAY (ABSOLUTE - (PORT datab (1528:1528:1528) (1520:1520:1520)) - (PORT datac (1336:1336:1336) (1338:1338:1338)) - (PORT datad (1075:1075:1075) (1068:1068:1068)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (PORT clk (1341:1341:1341) (1358:1358:1358)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1169:1169:1169) (1174:1174:1174)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1341:1341:1341) (1358:1358:1358)) + (PORT asdata (825:825:825) (809:809:809)) + (PORT ena (1132:1132:1132) (1119:1119:1119)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sw1_\|db_down\[3\]\~1) + (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~19) (DELAY (ABSOLUTE - (PORT dataa (330:330:330) (458:458:458)) - (PORT datab (1131:1131:1131) (1152:1152:1152)) - (PORT datac (1069:1069:1069) (1065:1065:1065)) - (PORT datad (845:845:845) (849:849:849)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[3\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (800:800:800) (812:812:812)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (806:806:806) (817:817:817)) - (PORT datad (580:580:580) (589:589:589)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[3\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (575:575:575) (575:575:575)) - (PORT datab (221:221:221) (266:266:266)) - (PORT datac (1066:1066:1066) (1070:1070:1070)) - (PORT datad (158:158:158) (178:178:178)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~46) - (DELAY - (ABSOLUTE - (PORT dataa (411:411:411) (450:450:450)) - (PORT datab (1071:1071:1071) (1055:1055:1055)) - (PORT datad (1350:1350:1350) (1340:1340:1340)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) + (PORT dataa (618:618:618) (645:645:645)) + (PORT datab (614:614:614) (628:628:628)) + (PORT datad (1297:1297:1297) (1243:1243:1243)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -23928,56 +20435,120 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~47) + (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~20) (DELAY (ABSOLUTE - (PORT dataa (392:392:392) (434:434:434)) - (PORT datac (157:157:157) (188:188:188)) - (PORT datad (1501:1501:1501) (1461:1461:1461)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT dataa (222:222:222) (296:296:296)) + (PORT datab (994:994:994) (982:982:982)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~50) + (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~21) (DELAY (ABSOLUTE - (PORT datab (331:331:331) (345:345:345)) - (PORT datac (731:731:731) (710:710:710)) - (PORT datad (301:301:301) (301:301:301)) + (PORT dataa (1257:1257:1257) (1264:1264:1264)) + (PORT datab (334:334:334) (351:351:351)) + (PORT datac (539:539:539) (540:540:540)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1357:1357:1357)) + (PORT asdata (1331:1331:1331) (1286:1286:1286)) + (PORT ena (716:716:716) (714:714:714)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[7\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1388:1388:1388) (1421:1421:1421)) + (PORT datab (1995:1995:1995) (1986:1986:1986)) + (PORT datad (1258:1258:1258) (1223:1223:1223)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1340:1340:1340) (1358:1358:1358)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1376:1376:1376) (1350:1350:1350)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1340:1340:1340) (1358:1358:1358)) + (PORT asdata (484:484:484) (510:510:510)) + (PORT ena (1131:1131:1131) (1124:1124:1124)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~72) + (DELAY + (ABSOLUTE + (PORT dataa (643:643:643) (689:689:689)) + (PORT datab (600:600:600) (615:615:615)) + (PORT datad (648:648:648) (659:659:659)) + (IOPATH dataa combout (329:329:329) (332:332:332)) (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[3\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (1338:1338:1338) (1356:1356:1356)) - (PORT asdata (887:887:887) (908:908:908)) - (PORT ena (1297:1297:1297) (1275:1275:1275)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1338:1338:1338) (1356:1356:1356)) - (PORT asdata (887:887:887) (908:908:908)) - (PORT ena (1588:1588:1588) (1555:1555:1555)) + (PORT clk (1340:1340:1340) (1358:1358:1358)) + (PORT asdata (1527:1527:1527) (1483:1483:1483)) + (PORT ena (1109:1109:1109) (1079:1079:1079)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -23988,13 +20559,60 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~44) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~71) (DELAY (ABSOLUTE - (PORT dataa (225:225:225) (300:300:300)) - (PORT datab (891:891:891) (937:937:937)) - (PORT datad (786:786:786) (805:805:805)) - (IOPATH dataa combout (300:300:300) (323:323:323)) + (PORT dataa (1084:1084:1084) (1113:1113:1113)) + (PORT datab (872:872:872) (853:853:853)) + (PORT datad (376:376:376) (394:394:394)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1341:1341:1341) (1359:1359:1359)) + (PORT asdata (1352:1352:1352) (1323:1323:1323)) + (PORT ena (1132:1132:1132) (1121:1121:1121)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1341:1341:1341) (1359:1359:1359)) + (PORT asdata (1352:1352:1352) (1322:1322:1322)) + (PORT ena (1076:1076:1076) (1031:1031:1031)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~70) + (DELAY + (ABSOLUTE + (PORT dataa (635:635:635) (653:653:653)) + (PORT datab (237:237:237) (296:296:296)) + (PORT datad (197:197:197) (255:255:255)) + (IOPATH dataa combout (318:318:318) (327:327:327)) (IOPATH datab combout (309:309:309) (328:328:328)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -24003,433 +20621,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1362:1362:1362)) - (PORT asdata (797:797:797) (781:781:781)) - (PORT ena (735:735:735) (733:733:733)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1362:1362:1362)) - (PORT asdata (797:797:797) (781:781:781)) - (PORT ena (763:763:763) (771:771:771)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~43) - (DELAY - (ABSOLUTE - (PORT dataa (223:223:223) (296:296:296)) - (PORT datab (231:231:231) (282:282:282)) - (PORT datad (207:207:207) (242:242:242)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~51) - (DELAY - (ABSOLUTE - (PORT dataa (791:791:791) (771:771:771)) - (PORT datab (185:185:185) (219:219:219)) - (PORT datac (560:560:560) (567:567:567)) - (PORT datad (575:575:575) (587:587:587)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~52) - (DELAY - (ABSOLUTE - (PORT dataa (798:798:798) (794:794:794)) - (PORT datab (564:564:564) (570:570:570)) - (PORT datac (311:311:311) (318:318:318)) - (PORT datad (1035:1035:1035) (1014:1014:1014)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1362:1362:1362)) - (PORT asdata (886:886:886) (890:890:890)) - (PORT ena (1105:1105:1105) (1078:1078:1078)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1236:1236:1236) (1213:1213:1213)) - (PORT datab (647:647:647) (665:665:665)) - (PORT datad (1107:1107:1107) (1126:1126:1126)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1363:1363:1363) (1384:1384:1384)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1175:1175:1175) (1170:1170:1170)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (561:561:561) (590:590:590)) - (PORT datac (647:647:647) (678:678:678)) - (PORT datad (201:201:201) (259:259:259)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (355:355:355) (361:361:361)) - (PORT datab (884:884:884) (895:895:895)) - (PORT datac (628:628:628) (660:660:660)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[3\]) - (DELAY - (ABSOLUTE - (PORT datab (217:217:217) (259:259:259)) - (PORT datac (511:511:511) (501:501:501)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1363:1363:1363) (1384:1384:1384)) - (PORT asdata (794:794:794) (788:788:788)) - (PORT clrn (1409:1409:1409) (1380:1380:1380)) - (PORT ena (1969:1969:1969) (1997:1997:1997)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_45\~4) - (DELAY - (ABSOLUTE - (PORT dataa (356:356:356) (384:384:384)) - (PORT datab (1063:1063:1063) (1066:1066:1066)) - (PORT datac (889:889:889) (916:916:916)) - (PORT datad (222:222:222) (282:282:282)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|carry_borrow_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (328:328:328) (346:346:346)) - (PORT datab (180:180:180) (213:213:213)) - (PORT datac (318:318:318) (325:325:325)) - (PORT datad (304:304:304) (306:306:306)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_4\|d0_out) - (DELAY - (ABSOLUTE - (PORT dataa (241:241:241) (315:315:315)) - (PORT datab (187:187:187) (224:224:224)) - (PORT datac (308:308:308) (318:318:318)) - (PORT datad (178:178:178) (200:200:200)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1362:1362:1362)) - (PORT asdata (1136:1136:1136) (1120:1120:1120)) - (PORT ena (735:735:735) (733:733:733)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1362:1362:1362)) - (PORT asdata (1133:1133:1133) (1116:1116:1116)) - (PORT ena (763:763:763) (771:771:771)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~53) - (DELAY - (ABSOLUTE - (PORT dataa (223:223:223) (295:295:295)) - (PORT datab (229:229:229) (280:280:280)) - (PORT datad (207:207:207) (240:240:240)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~54) - (DELAY - (ABSOLUTE - (PORT dataa (590:590:590) (591:591:591)) - (PORT datab (1063:1063:1063) (1050:1050:1050)) - (PORT datad (582:582:582) (589:589:589)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1371:1371:1371)) - (PORT asdata (1104:1104:1104) (1087:1087:1087)) - (PORT ena (746:746:746) (759:759:759)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1371:1371:1371)) - (PORT asdata (1108:1108:1108) (1092:1092:1092)) - (PORT ena (1154:1154:1154) (1142:1142:1142)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~58) - (DELAY - (ABSOLUTE - (PORT dataa (382:382:382) (421:421:421)) - (PORT datab (544:544:544) (554:554:554)) - (PORT datad (199:199:199) (257:257:257)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1342:1342:1342) (1359:1359:1359)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1381:1381:1381) (1365:1365:1365)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1342:1342:1342) (1359:1359:1359)) - (PORT asdata (873:873:873) (865:865:865)) - (PORT ena (1109:1109:1109) (1074:1074:1074)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1342:1342:1342) (1359:1359:1359)) - (PORT asdata (874:874:874) (867:867:867)) - (PORT ena (1155:1155:1155) (1140:1140:1140)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~59) - (DELAY - (ABSOLUTE - (PORT dataa (405:405:405) (444:444:444)) - (PORT datab (612:612:612) (626:626:626)) - (PORT datad (197:197:197) (253:253:253)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~60) - (DELAY - (ABSOLUTE - (PORT dataa (600:600:600) (595:595:595)) - (PORT datab (856:856:856) (860:860:860)) - (PORT datac (193:193:193) (258:258:258)) - (PORT datad (312:312:312) (313:313:313)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[4\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[7\]) (DELAY (ABSOLUTE (PORT clk (1338:1338:1338) (1356:1356:1356)) - (PORT asdata (917:917:917) (924:924:924)) - (PORT ena (1588:1588:1588) (1555:1555:1555)) + (PORT asdata (1138:1138:1138) (1142:1142:1142)) + (PORT ena (1126:1126:1126) (1110:1110:1110)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -24440,12 +20637,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[4\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[7\]) (DELAY (ABSOLUTE (PORT clk (1338:1338:1338) (1356:1356:1356)) - (PORT asdata (918:918:918) (926:926:926)) - (PORT ena (1297:1297:1297) (1275:1275:1275)) + (PORT asdata (1135:1135:1135) (1141:1141:1141)) + (PORT ena (1322:1322:1322) (1264:1264:1264)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -24456,11 +20653,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~57) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~69) (DELAY (ABSOLUTE - (PORT dataa (813:813:813) (846:846:846)) - (PORT datab (881:881:881) (934:934:934)) + (PORT dataa (647:647:647) (686:686:686)) + (PORT datab (601:601:601) (605:605:605)) (PORT datad (198:198:198) (255:255:255)) (IOPATH dataa combout (309:309:309) (326:326:326)) (IOPATH datab combout (325:325:325) (332:332:332)) @@ -24470,12 +20667,44 @@ ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[4\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~73) (DELAY (ABSOLUTE - (PORT clk (1349:1349:1349) (1370:1370:1370)) - (PORT asdata (903:903:903) (902:902:902)) + (PORT dataa (779:779:779) (760:760:760)) + (PORT datab (574:574:574) (557:557:557)) + (PORT datac (498:498:498) (484:484:484)) + (PORT datad (319:319:319) (330:330:330)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1356:1356:1356)) + (PORT asdata (841:841:841) (827:827:827)) + (PORT ena (1132:1132:1132) (1119:1119:1119)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1356:1356:1356)) + (PORT asdata (843:843:843) (829:829:829)) (PORT ena (744:744:744) (751:751:751)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -24486,13 +20715,28 @@ ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[4\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~68) (DELAY (ABSOLUTE - (PORT clk (1349:1349:1349) (1370:1370:1370)) - (PORT asdata (901:901:901) (899:899:899)) - (PORT ena (1123:1123:1123) (1106:1106:1106)) + (PORT dataa (654:654:654) (684:684:684)) + (PORT datab (220:220:220) (288:288:288)) + (PORT datad (212:212:212) (246:246:246)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1356:1356:1356)) + (PORT asdata (1311:1311:1311) (1275:1275:1275)) + (PORT ena (898:898:898) (891:891:891)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -24503,119 +20747,22 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~55) + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[7\]\~feeder) (DELAY (ABSOLUTE - (PORT dataa (603:603:603) (640:640:640)) - (PORT datab (372:372:372) (391:391:391)) - (PORT datad (196:196:196) (253:253:253)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) + (PORT datad (809:809:809) (800:800:800)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[4\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (1342:1342:1342) (1359:1359:1359)) - (PORT asdata (804:804:804) (785:785:785)) - (PORT ena (1295:1295:1295) (1246:1246:1246)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~56) - (DELAY - (ABSOLUTE - (PORT dataa (500:500:500) (490:490:490)) - (PORT datad (763:763:763) (747:747:747)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~61) - (DELAY - (ABSOLUTE - (PORT dataa (318:318:318) (332:332:332)) - (PORT datab (181:181:181) (213:213:213)) - (PORT datac (945:945:945) (917:917:917)) - (PORT datad (158:158:158) (178:178:178)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~62) - (DELAY - (ABSOLUTE - (PORT dataa (181:181:181) (217:217:217)) - (PORT datab (800:800:800) (794:794:794)) - (PORT datac (1018:1018:1018) (1017:1017:1017)) - (PORT datad (1076:1076:1076) (1075:1075:1075)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1362:1362:1362)) - (PORT asdata (1258:1258:1258) (1240:1240:1240)) - (PORT ena (1105:1105:1105) (1078:1078:1078)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (823:823:823) (805:805:805)) - (PORT datab (1148:1148:1148) (1158:1158:1158)) - (PORT datad (609:609:609) (629:629:629)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1363:1363:1363) (1384:1384:1384)) + (PORT clk (1338:1338:1338) (1356:1356:1356)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (1175:1175:1175) (1170:1170:1170)) + (PORT ena (1093:1093:1093) (1055:1055:1055)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -24626,369 +20773,428 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~14) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~67) (DELAY (ABSOLUTE - (PORT datab (579:579:579) (601:601:601)) - (PORT datac (647:647:647) (676:676:676)) - (PORT datad (197:197:197) (255:255:255)) + (PORT dataa (621:621:621) (634:634:634)) + (PORT datab (632:632:632) (644:644:644)) + (PORT datad (195:195:195) (252:252:252)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~74) + (DELAY + (ABSOLUTE + (PORT dataa (519:519:519) (517:517:517)) + (PORT datab (727:727:727) (768:768:768)) + (PORT datac (707:707:707) (725:725:725)) + (PORT datad (334:334:334) (346:346:346)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~75) + (DELAY + (ABSOLUTE + (PORT dataa (789:789:789) (775:775:775)) + (PORT datab (850:850:850) (850:850:850)) + (PORT datac (1046:1046:1046) (1044:1044:1044)) + (PORT datad (522:522:522) (512:512:512)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[7\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (585:585:585) (606:606:606)) + (PORT datab (837:837:837) (823:823:823)) + (PORT datac (532:532:532) (536:536:536)) + (PORT datad (591:591:591) (583:583:583)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[7\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (678:678:678) (698:698:698)) + (PORT datab (226:226:226) (284:284:284)) + (PORT datac (823:823:823) (816:816:816)) + (PORT datad (163:163:163) (185:185:185)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (844:844:844) (831:831:831)) + (PORT datac (521:521:521) (513:513:513)) + (PORT datad (644:644:644) (715:715:715)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~1) + (DELAY + (ABSOLUTE + (PORT datab (183:183:183) (217:217:217)) + (PORT datac (166:166:166) (203:203:203)) + (PORT datad (1038:1038:1038) (1035:1035:1035)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~2) + (DELAY + (ABSOLUTE + (PORT dataa (812:812:812) (827:827:827)) + (PORT datab (182:182:182) (215:215:215)) + (PORT datac (1027:1027:1027) (1042:1042:1042)) + (PORT datad (1036:1036:1036) (1034:1034:1034)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1053:1053:1053) (1069:1069:1069)) + (PORT datab (629:629:629) (644:644:644)) + (PORT datad (159:159:159) (179:179:179)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2) + (DELAY + (ABSOLUTE + (PORT clk (1346:1346:1346) (1363:1363:1363)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~8) + (DELAY + (ABSOLUTE + (PORT dataa (844:844:844) (887:887:887)) + (PORT datac (545:545:545) (561:561:561)) + (PORT datad (368:368:368) (394:394:394)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1081:1081:1081) (1082:1082:1082)) + (PORT datab (918:918:918) (949:949:949)) + (PORT datac (294:294:294) (304:304:304)) + (PORT datad (842:842:842) (863:863:863)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1940:1940:1940) (2030:2030:2030)) + (PORT datab (1459:1459:1459) (1490:1490:1490)) + (PORT datac (1661:1661:1661) (1683:1683:1683)) + (PORT datad (882:882:882) (969:969:969)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~11) + (DELAY + (ABSOLUTE + (PORT dataa (898:898:898) (903:903:903)) + (PORT datab (575:575:575) (593:593:593)) + (PORT datac (2292:2292:2292) (2239:2239:2239)) + (PORT datad (533:533:533) (532:532:532)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1306:1306:1306) (1262:1262:1262)) + (PORT datab (356:356:356) (362:362:362)) + (PORT datac (985:985:985) (963:963:963)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~9) + (DELAY + (ABSOLUTE + (PORT dataa (572:572:572) (609:609:609)) + (PORT datab (1119:1119:1119) (1124:1124:1124)) + (PORT datac (567:567:567) (560:560:560)) + (PORT datad (622:622:622) (679:679:679)) + (IOPATH dataa combout (307:307:307) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~46) + (DELAY + (ABSOLUTE + (PORT dataa (1387:1387:1387) (1454:1454:1454)) + (PORT datab (1413:1413:1413) (1417:1417:1417)) + (PORT datad (1753:1753:1753) (1785:1785:1785)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~9) + (DELAY + (ABSOLUTE + (PORT dataa (591:591:591) (594:594:594)) + (PORT datab (200:200:200) (234:234:234)) + (PORT datac (167:167:167) (205:205:205)) + (PORT datad (589:589:589) (592:592:592)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~10) + (DELAY + (ABSOLUTE + (PORT dataa (863:863:863) (888:888:888)) + (PORT datab (803:803:803) (789:789:789)) + (PORT datac (843:843:843) (890:890:890)) + (PORT datad (192:192:192) (222:222:222)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1386:1386:1386) (1412:1412:1412)) + (PORT datab (188:188:188) (225:225:225)) + (PORT datac (743:743:743) (746:746:746)) + (PORT datad (561:561:561) (586:586:586)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1052:1052:1052) (1074:1074:1074)) + (PORT datab (606:606:606) (631:631:631)) + (PORT datac (540:540:540) (534:534:534)) + (PORT datad (589:589:589) (599:599:599)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1856:1856:1856) (1993:1993:1993)) + (PORT datab (1122:1122:1122) (1155:1155:1155)) + (PORT datac (892:892:892) (897:897:897)) + (PORT datad (1179:1179:1179) (1212:1212:1212)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~16) + (DELAY + (ABSOLUTE + (PORT dataa (951:951:951) (952:952:952)) + (PORT datab (212:212:212) (252:252:252)) + (PORT datac (295:295:295) (301:301:301)) + (PORT datad (1321:1321:1321) (1316:1316:1316)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~3) + (DELAY + (ABSOLUTE + (PORT dataa (585:585:585) (601:601:601)) + (PORT datab (1102:1102:1102) (1107:1107:1107)) + (PORT datac (759:759:759) (760:760:760)) + (PORT datad (1021:1021:1021) (1003:1003:1003)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|flags_cf) + (DELAY + (ABSOLUTE + (PORT dataa (607:607:607) (630:630:630)) + (PORT datab (795:795:795) (837:837:837)) + (PORT datac (155:155:155) (186:186:186)) + (PORT datad (349:349:349) (361:361:361)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sw2_\|db_up\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT datac (808:808:808) (798:798:798)) + (PORT datad (512:512:512) (502:502:502)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[0\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (794:794:794) (793:793:793)) + (PORT datab (551:551:551) (553:553:553)) + (PORT datac (374:374:374) (400:400:400)) + (PORT datad (557:557:557) (552:552:552)) + (IOPATH dataa combout (287:287:287) (289:289:289)) (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (355:355:355) (361:361:361)) - (PORT datab (883:883:883) (898:898:898)) - (PORT datac (627:627:627) (663:663:663)) - (PORT datad (158:158:158) (178:178:178)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[4\]) - (DELAY - (ABSOLUTE - (PORT datab (215:215:215) (256:256:256)) - (PORT datad (489:489:489) (481:481:481)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[4\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[0\]) (DELAY (ABSOLUTE - (PORT clk (1363:1363:1363) (1384:1384:1384)) - (PORT asdata (784:784:784) (765:765:765)) - (PORT clrn (1409:1409:1409) (1380:1380:1380)) - (PORT ena (1969:1969:1969) (1997:1997:1997)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_44) - (DELAY - (ABSOLUTE - (PORT dataa (1068:1068:1068) (1057:1057:1057)) - (PORT datab (917:917:917) (925:925:925)) - (PORT datad (183:183:183) (207:207:207)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_4\|d1_out) - (DELAY - (ABSOLUTE - (PORT dataa (646:646:646) (680:680:680)) - (PORT datab (1067:1067:1067) (1069:1069:1069)) - (PORT datac (576:576:576) (586:586:586)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1338:1338:1338) (1356:1356:1356)) - (PORT asdata (816:816:816) (799:799:799)) - (PORT ena (1297:1297:1297) (1275:1275:1275)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1338:1338:1338) (1356:1356:1356)) - (PORT asdata (815:815:815) (801:801:801)) - (PORT ena (1588:1588:1588) (1555:1555:1555)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~64) - (DELAY - (ABSOLUTE - (PORT dataa (222:222:222) (295:295:295)) - (PORT datab (882:882:882) (936:936:936)) - (PORT datad (785:785:785) (805:805:805)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1338:1338:1338) (1356:1356:1356)) - (PORT asdata (634:634:634) (638:638:638)) - (PORT ena (1353:1353:1353) (1319:1319:1319)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1338:1338:1338) (1356:1356:1356)) - (PORT asdata (634:634:634) (635:635:635)) - (PORT ena (1145:1145:1145) (1131:1131:1131)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~63) - (DELAY - (ABSOLUTE - (PORT dataa (1020:1020:1020) (1039:1039:1039)) - (PORT datab (220:220:220) (288:288:288)) - (PORT datad (604:604:604) (622:622:622)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1342:1342:1342) (1359:1359:1359)) - (PORT asdata (1330:1330:1330) (1311:1311:1311)) - (PORT ena (1381:1381:1381) (1365:1365:1365)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1342:1342:1342) (1359:1359:1359)) - (PORT asdata (1341:1341:1341) (1321:1321:1321)) - (PORT ena (1109:1109:1109) (1074:1074:1074)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~66) - (DELAY - (ABSOLUTE - (PORT dataa (401:401:401) (436:436:436)) - (PORT datab (1062:1062:1062) (1044:1044:1044)) - (PORT datad (581:581:581) (571:571:571)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~67) - (DELAY - (ABSOLUTE - (PORT datab (854:854:854) (856:856:856)) - (PORT datad (315:315:315) (318:318:318)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1371:1371:1371)) - (PORT asdata (1121:1121:1121) (1091:1091:1091)) - (PORT ena (746:746:746) (759:759:759)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1371:1371:1371)) - (PORT asdata (1120:1120:1120) (1090:1090:1090)) - (PORT ena (1154:1154:1154) (1142:1142:1142)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~65) - (DELAY - (ABSOLUTE - (PORT dataa (383:383:383) (422:422:422)) - (PORT datab (545:545:545) (555:555:555)) - (PORT datad (197:197:197) (253:253:253)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1370:1370:1370)) - (PORT asdata (1343:1343:1343) (1328:1328:1328)) - (PORT ena (1123:1123:1123) (1106:1106:1106)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[5\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (560:560:560) (554:554:554)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1370:1370:1370)) + (PORT clk (1340:1340:1340) (1357:1357:1357)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (744:744:744) (751:751:751)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~69) - (DELAY - (ABSOLUTE - (PORT dataa (599:599:599) (633:633:633)) - (PORT datab (366:366:366) (384:384:384)) - (PORT datad (196:196:196) (252:252:252)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[5\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (790:790:790) (780:780:780)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1342:1342:1342) (1359:1359:1359)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1295:1295:1295) (1246:1246:1246)) + (PORT ena (1132:1132:1132) (1111:1111:1111)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -24999,12 +21205,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[5\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[0\]) (DELAY (ABSOLUTE - (PORT clk (1342:1342:1342) (1359:1359:1359)) - (PORT asdata (1342:1342:1342) (1323:1323:1323)) - (PORT ena (1155:1155:1155) (1140:1140:1140)) + (PORT clk (1340:1340:1340) (1357:1357:1357)) + (PORT asdata (618:618:618) (624:624:624)) + (PORT ena (1107:1107:1107) (1064:1064:1064)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -25015,14 +21221,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~68) + (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~0) (DELAY (ABSOLUTE - (PORT dataa (529:529:529) (564:564:564)) - (PORT datab (769:769:769) (765:765:765)) - (PORT datad (591:591:591) (597:597:597)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) + (PORT dataa (827:827:827) (846:846:846)) + (PORT datab (1136:1136:1136) (1139:1139:1139)) + (PORT datad (375:375:375) (389:389:389)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -25030,29 +21236,109 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~70) + (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~1) (DELAY (ABSOLUTE - (PORT dataa (593:593:593) (597:597:597)) - (PORT datab (1039:1039:1039) (1014:1014:1014)) - (PORT datac (313:313:313) (320:320:320)) - (PORT datad (542:542:542) (549:549:549)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~71) - (DELAY - (ABSOLUTE - (PORT dataa (348:348:348) (354:354:354)) - (PORT datac (155:155:155) (185:185:185)) - (PORT datad (161:161:161) (183:183:183)) + (PORT dataa (224:224:224) (296:296:296)) + (PORT datac (154:154:154) (184:184:184)) + (PORT datad (570:570:570) (561:561:561)) (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~70) + (DELAY + (ABSOLUTE + (PORT dataa (929:929:929) (966:966:966)) + (PORT datab (1508:1508:1508) (1459:1459:1459)) + (PORT datac (1439:1439:1439) (1486:1486:1486)) + (PORT datad (2564:2564:2564) (2665:2665:2665)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~28) + (DELAY + (ABSOLUTE + (PORT dataa (1591:1591:1591) (1622:1622:1622)) + (PORT datab (1690:1690:1690) (1705:1705:1705)) + (PORT datac (1118:1118:1118) (1140:1140:1140)) + (PORT datad (921:921:921) (945:945:945)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1576:1576:1576) (1547:1547:1547)) + (PORT datab (848:848:848) (854:854:854)) + (PORT datac (155:155:155) (186:186:186)) + (PORT datad (624:624:624) (663:663:663)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~27) + (DELAY + (ABSOLUTE + (PORT dataa (1589:1589:1589) (1621:1621:1621)) + (PORT datab (644:644:644) (666:666:666)) + (PORT datac (1120:1120:1120) (1143:1143:1143)) + (PORT datad (918:918:918) (944:944:944)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~10) + (DELAY + (ABSOLUTE + (PORT dataa (911:911:911) (948:948:948)) + (PORT datab (205:205:205) (242:242:242)) + (PORT datac (790:790:790) (808:808:808)) + (PORT datad (185:185:185) (212:212:212)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla38pla13M3T2_4) + (DELAY + (ABSOLUTE + (PORT dataa (908:908:908) (943:943:943)) + (PORT datab (1533:1533:1533) (1590:1590:1590)) + (PORT datac (1018:1018:1018) (1016:1016:1016)) + (PORT datad (819:819:819) (831:831:831)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -25060,76 +21346,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~72) + (INSTANCE z80_\|execute_\|pc_inc_hold\~11) (DELAY (ABSOLUTE - (PORT dataa (597:597:597) (621:621:621)) - (PORT datab (861:861:861) (871:871:871)) - (PORT datac (156:156:156) (186:186:186)) - (PORT datad (1497:1497:1497) (1445:1445:1445)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1362:1362:1362)) - (PORT asdata (1126:1126:1126) (1121:1121:1121)) - (PORT ena (1105:1105:1105) (1078:1078:1078)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[5\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1092:1092:1092) (1090:1090:1090)) - (PORT datab (1149:1149:1149) (1158:1158:1158)) - (PORT datad (610:610:610) (629:629:629)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1354:1354:1354) (1375:1375:1375)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (735:735:735) (733:733:733)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[5\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (249:249:249)) - (PORT datac (562:562:562) (576:576:576)) - (PORT datad (199:199:199) (257:257:257)) - (IOPATH dataa combout (318:318:318) (327:327:327)) + (PORT dataa (2593:2593:2593) (2702:2702:2702)) + (PORT datab (2140:2140:2140) (2117:2117:2117)) + (PORT datac (1140:1140:1140) (1134:1134:1134)) + (PORT datad (1170:1170:1170) (1189:1189:1189)) + (IOPATH dataa combout (307:307:307) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -25137,60 +21362,142 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[5\]\~18) + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla40M3T2_4\~0) (DELAY (ABSOLUTE - (PORT dataa (609:609:609) (601:601:601)) - (PORT datab (1245:1245:1245) (1193:1193:1193)) - (PORT datac (174:174:174) (204:204:204)) - (PORT datad (160:160:160) (182:182:182)) + (PORT dataa (1108:1108:1108) (1100:1100:1100)) + (PORT datab (1095:1095:1095) (1191:1191:1191)) + (PORT datac (890:890:890) (914:914:914)) + (PORT datad (585:585:585) (599:599:599)) (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[5\]) + (INSTANCE z80_\|execute_\|pc_inc_hold\~9) (DELAY (ABSOLUTE - (PORT datac (606:606:606) (623:623:623)) - (PORT datad (770:770:770) (749:749:749)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT dataa (812:812:812) (795:795:795)) + (PORT datab (206:206:206) (243:243:243)) + (PORT datac (1013:1013:1013) (1014:1014:1014)) + (PORT datad (878:878:878) (885:885:885)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[5\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~12) (DELAY (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1400:1400:1400) (1370:1370:1370)) - (PORT ena (1981:1981:1981) (2010:2010:2010)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + (PORT dataa (190:190:190) (229:229:229)) + (PORT datab (187:187:187) (223:223:223)) + (PORT datac (602:602:602) (619:619:619)) + (PORT datad (576:576:576) (576:576:576)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_43\~4) + (INSTANCE z80_\|execute_\|pc_inc_hold\~7) (DELAY (ABSOLUTE - (PORT dataa (843:843:843) (881:881:881)) - (PORT datab (1064:1064:1064) (1061:1061:1061)) - (PORT datac (886:886:886) (910:910:910)) - (PORT datad (335:335:335) (347:347:347)) + (PORT dataa (1086:1086:1086) (1081:1081:1081)) + (PORT datab (863:863:863) (861:861:861)) + (PORT datac (798:798:798) (790:790:790)) + (PORT datad (1202:1202:1202) (1235:1235:1235)) (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1196:1196:1196) (1255:1255:1255)) + (PORT datab (1400:1400:1400) (1428:1428:1428)) + (PORT datac (825:825:825) (851:851:851)) + (PORT datad (2619:2619:2619) (2671:2671:2671)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1861:1861:1861) (1888:1888:1888)) + (PORT datab (2257:2257:2257) (2351:2351:2351)) + (PORT datac (607:607:607) (641:641:641)) + (PORT datad (915:915:915) (943:943:943)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~14) + (DELAY + (ABSOLUTE + (PORT dataa (607:607:607) (609:609:609)) + (PORT datab (607:607:607) (615:615:615)) + (PORT datac (168:168:168) (204:204:204)) + (PORT datad (322:322:322) (325:325:325)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_use_ixiypla53M2T2_4) + (DELAY + (ABSOLUTE + (PORT dataa (1861:1861:1861) (1888:1888:1888)) + (PORT datab (1103:1103:1103) (1093:1093:1093)) + (PORT datac (788:788:788) (774:774:774)) + (PORT datad (915:915:915) (943:943:943)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~16) + (DELAY + (ABSOLUTE + (PORT dataa (532:532:532) (525:525:525)) + (PORT datab (365:365:365) (370:370:370)) + (PORT datac (162:162:162) (195:195:195)) + (PORT datad (314:314:314) (314:314:314)) + (IOPATH dataa combout (299:299:299) (304:304:304)) (IOPATH datab combout (300:300:300) (312:312:312)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -25199,385 +21506,599 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[6\]) + (INSTANCE z80_\|execute_\|pc_inc_hold\~22) (DELAY (ABSOLUTE - (PORT dataa (604:604:604) (619:619:619)) - (PORT datab (1066:1066:1066) (1068:1068:1068)) - (PORT datac (751:751:751) (759:759:759)) - (PORT datad (564:564:564) (573:573:573)) + (PORT dataa (612:612:612) (631:631:631)) + (PORT datab (1234:1234:1234) (1281:1281:1281)) + (PORT datac (1405:1405:1405) (1446:1446:1446)) + (PORT datad (1531:1531:1531) (1536:1536:1536)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~23) + (DELAY + (ABSOLUTE + (PORT dataa (376:376:376) (386:386:386)) + (PORT datab (1059:1059:1059) (1076:1076:1076)) + (PORT datac (1265:1265:1265) (1259:1259:1259)) + (PORT datad (2000:2000:2000) (2106:2106:2106)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~24) + (DELAY + (ABSOLUTE + (PORT dataa (1409:1409:1409) (1444:1444:1444)) + (PORT datab (182:182:182) (215:215:215)) + (PORT datac (153:153:153) (183:183:183)) + (PORT datad (1999:1999:1999) (2106:2106:2106)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~41) + (DELAY + (ABSOLUTE + (PORT dataa (904:904:904) (911:911:911)) + (PORT datab (877:877:877) (883:883:883)) + (PORT datac (1135:1135:1135) (1169:1169:1169)) + (PORT datad (617:617:617) (635:635:635)) (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1363:1363:1363) (1384:1384:1384)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1175:1175:1175) (1170:1170:1170)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1338:1338:1338) (1356:1356:1356)) - (PORT asdata (1549:1549:1549) (1512:1512:1512)) - (PORT ena (1588:1588:1588) (1555:1555:1555)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[6\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1237:1237:1237) (1208:1208:1208)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1338:1338:1338) (1356:1356:1356)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1297:1297:1297) (1275:1275:1275)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~74) - (DELAY - (ABSOLUTE - (PORT dataa (808:808:808) (843:843:843)) - (PORT datab (882:882:882) (933:933:933)) - (PORT datad (198:198:198) (255:255:255)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1338:1338:1338) (1356:1356:1356)) - (PORT asdata (1744:1744:1744) (1690:1690:1690)) - (PORT ena (1353:1353:1353) (1319:1319:1319)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1338:1338:1338) (1356:1356:1356)) - (PORT asdata (1742:1742:1742) (1687:1687:1687)) - (PORT ena (1145:1145:1145) (1131:1131:1131)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~73) - (DELAY - (ABSOLUTE - (PORT dataa (1017:1017:1017) (1038:1038:1038)) - (PORT datab (220:220:220) (289:289:289)) - (PORT datad (601:601:601) (620:620:620)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1370:1370:1370)) - (PORT asdata (1991:1991:1991) (1931:1931:1931)) - (PORT ena (1132:1132:1132) (1112:1112:1112)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[6\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (971:971:971) (951:951:951)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1370:1370:1370)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (744:744:744) (751:751:751)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~78) - (DELAY - (ABSOLUTE - (PORT dataa (396:396:396) (420:420:420)) - (PORT datab (585:585:585) (612:612:612)) - (PORT datad (346:346:346) (387:387:387)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1362:1362:1362)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1342:1342:1342) (1311:1311:1311)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~79) - (DELAY - (ABSOLUTE - (PORT dataa (646:646:646) (679:679:679)) - (PORT datab (881:881:881) (880:880:880)) - (PORT datac (813:813:813) (804:804:804)) - (PORT datad (564:564:564) (571:571:571)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1370:1370:1370)) - (PORT asdata (1992:1992:1992) (1930:1930:1930)) - (PORT ena (1380:1380:1380) (1365:1365:1365)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[6\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1208:1208:1208) (1166:1166:1166)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1342:1342:1342) (1359:1359:1359)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1155:1155:1155) (1140:1140:1140)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1342:1342:1342) (1359:1359:1359)) - (PORT asdata (1485:1485:1485) (1445:1445:1445)) - (PORT ena (1109:1109:1109) (1074:1074:1074)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~76) - (DELAY - (ABSOLUTE - (PORT dataa (405:405:405) (444:444:444)) - (PORT datab (220:220:220) (289:289:289)) - (PORT datad (586:586:586) (594:594:594)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~77) - (DELAY - (ABSOLUTE - (PORT datab (1303:1303:1303) (1285:1285:1285)) - (PORT datad (522:522:522) (515:515:515)) (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~80) + (INSTANCE z80_\|execute_\|pc_inc_hold\~21) (DELAY (ABSOLUTE - (PORT datab (182:182:182) (214:214:214)) - (PORT datac (155:155:155) (186:186:186)) - (PORT datad (159:159:159) (180:180:180)) + (PORT dataa (788:788:788) (787:787:787)) + (PORT datab (1287:1287:1287) (1281:1281:1281)) + (PORT datac (1504:1504:1504) (1480:1480:1480)) + (PORT datad (769:769:769) (773:773:773)) + (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1371:1371:1371)) - (PORT asdata (1242:1242:1242) (1213:1213:1213)) - (PORT ena (746:746:746) (759:759:759)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1346:1346:1346) (1363:1363:1363)) - (PORT asdata (1317:1317:1317) (1303:1303:1303)) - (PORT ena (763:763:763) (771:771:771)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~75) + (INSTANCE z80_\|execute_\|pc_inc_hold\~25) (DELAY (ABSOLUTE - (PORT dataa (386:386:386) (426:426:426)) - (PORT datab (537:537:537) (544:544:544)) - (PORT datad (773:773:773) (790:790:790)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) + (PORT dataa (611:611:611) (618:618:618)) + (PORT datab (847:847:847) (820:820:820)) + (PORT datac (810:810:810) (802:802:802)) + (PORT datad (165:165:165) (188:188:188)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~81) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~69) (DELAY (ABSOLUTE - (PORT dataa (350:350:350) (357:357:357)) - (PORT datab (182:182:182) (214:214:214)) - (PORT datac (736:736:736) (706:706:706)) - (PORT datad (717:717:717) (689:689:689)) + (PORT dataa (927:927:927) (963:963:963)) + (PORT datab (2600:2600:2600) (2702:2702:2702)) + (PORT datac (161:161:161) (196:196:196)) + (PORT datad (1284:1284:1284) (1261:1261:1261)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~17) + (DELAY + (ABSOLUTE + (PORT dataa (443:443:443) (512:512:512)) + (PORT datac (237:237:237) (315:315:315)) + (PORT datad (647:647:647) (693:693:693)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~71) + (DELAY + (ABSOLUTE + (PORT dataa (1539:1539:1539) (1510:1510:1510)) + (PORT datab (182:182:182) (215:215:215)) + (PORT datac (160:160:160) (194:194:194)) + (PORT datad (1090:1090:1090) (1084:1084:1084)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~44) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (236:236:236)) + (PORT datab (1247:1247:1247) (1278:1278:1278)) + (PORT datac (581:581:581) (585:585:585)) + (PORT datad (1091:1091:1091) (1090:1090:1090)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~42) + (DELAY + (ABSOLUTE + (PORT dataa (611:611:611) (622:622:622)) + (PORT datac (810:810:810) (801:801:801)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~43) + (DELAY + (ABSOLUTE + (PORT dataa (1136:1136:1136) (1127:1127:1127)) + (PORT datab (183:183:183) (216:216:216)) + (PORT datac (975:975:975) (964:964:964)) + (PORT datad (905:905:905) (929:929:929)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~57) + (DELAY + (ABSOLUTE + (PORT dataa (1283:1283:1283) (1257:1257:1257)) + (PORT datab (1080:1080:1080) (1066:1066:1066)) + (PORT datac (577:577:577) (587:587:587)) + (PORT datad (561:561:561) (566:566:566)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~54) + (DELAY + (ABSOLUTE + (PORT dataa (1588:1588:1588) (1619:1619:1619)) + (PORT datab (2257:2257:2257) (2354:2354:2354)) + (PORT datac (1666:1666:1666) (1683:1683:1683)) + (PORT datad (624:624:624) (660:660:660)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~58) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (219:219:219)) + (PORT datab (365:365:365) (368:368:368)) + (PORT datac (162:162:162) (196:196:196)) + (PORT datad (302:302:302) (302:302:302)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~18) + (DELAY + (ABSOLUTE + (PORT dataa (910:910:910) (947:947:947)) + (PORT datab (206:206:206) (243:243:243)) + (PORT datac (162:162:162) (198:198:198)) + (PORT datad (577:577:577) (575:575:575)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~19) + (DELAY + (ABSOLUTE + (PORT dataa (818:818:818) (785:785:785)) + (PORT datab (355:355:355) (357:357:357)) + (PORT datac (580:580:580) (591:591:591)) + (PORT datad (551:551:551) (542:542:542)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~45) + (DELAY + (ABSOLUTE + (PORT dataa (1122:1122:1122) (1136:1136:1136)) + (PORT datab (940:940:940) (967:967:967)) + (PORT datac (529:529:529) (511:511:511)) + (PORT datad (1338:1338:1338) (1347:1347:1347)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~34) + (DELAY + (ABSOLUTE + (PORT dataa (2594:2594:2594) (2704:2704:2704)) + (PORT datab (1170:1170:1170) (1202:1202:1202)) + (PORT datac (903:903:903) (944:944:944)) + (PORT datad (1168:1168:1168) (1189:1189:1189)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~35) + (DELAY + (ABSOLUTE + (PORT dataa (1192:1192:1192) (1225:1225:1225)) + (PORT datab (189:189:189) (223:223:223)) + (PORT datac (632:632:632) (651:651:651)) + (PORT datad (157:157:157) (177:177:177)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~46) + (DELAY + (ABSOLUTE + (PORT dataa (1187:1187:1187) (1199:1199:1199)) + (PORT datab (1158:1158:1158) (1177:1177:1177)) + (PORT datac (1157:1157:1157) (1172:1172:1172)) + (PORT datad (1342:1342:1342) (1352:1352:1352)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~47) + (DELAY + (ABSOLUTE + (PORT dataa (573:573:573) (607:607:607)) + (PORT datab (1158:1158:1158) (1177:1177:1177)) + (PORT datac (1408:1408:1408) (1433:1433:1433)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~48) + (DELAY + (ABSOLUTE + (PORT dataa (875:875:875) (907:907:907)) + (PORT datab (2283:2283:2283) (2388:2388:2388)) + (PORT datac (566:566:566) (559:559:559)) + (PORT datad (856:856:856) (883:883:883)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~50) + (DELAY + (ABSOLUTE + (PORT dataa (611:611:611) (609:609:609)) + (PORT datab (194:194:194) (230:230:230)) + (PORT datac (838:838:838) (845:845:845)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~51) + (DELAY + (ABSOLUTE + (PORT dataa (196:196:196) (240:240:240)) + (PORT datab (1082:1082:1082) (1067:1067:1067)) + (PORT datac (169:169:169) (206:206:206)) + (PORT datad (848:848:848) (870:870:870)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~85) + (DELAY + (ABSOLUTE + (PORT dataa (1195:1195:1195) (1255:1255:1255)) + (PORT datab (1153:1153:1153) (1165:1165:1165)) + (PORT datac (884:884:884) (938:938:938)) + (PORT datad (596:596:596) (625:625:625)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~63) + (DELAY + (ABSOLUTE + (PORT dataa (446:446:446) (517:517:517)) + (PORT datab (861:861:861) (877:877:877)) + (PORT datac (786:786:786) (789:789:789)) + (PORT datad (642:642:642) (692:692:692)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~64) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (238:238:238)) + (PORT datab (828:828:828) (818:818:818)) + (PORT datac (790:790:790) (811:811:811)) + (PORT datad (577:577:577) (574:574:574)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~65) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (246:246:246)) + (PORT datab (182:182:182) (215:215:215)) + (PORT datac (533:533:533) (527:527:527)) + (PORT datad (178:178:178) (200:200:200)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~59) + (DELAY + (ABSOLUTE + (PORT dataa (864:864:864) (873:873:873)) + (PORT datab (1533:1533:1533) (1590:1590:1590)) + (PORT datac (792:792:792) (809:809:809)) + (PORT datad (821:821:821) (837:837:837)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~60) + (DELAY + (ABSOLUTE + (PORT dataa (181:181:181) (217:217:217)) + (PORT datab (617:617:617) (609:609:609)) + (PORT datac (160:160:160) (193:193:193)) + (PORT datad (783:783:783) (771:771:771)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~61) + (DELAY + (ABSOLUTE + (PORT dataa (1196:1196:1196) (1253:1253:1253)) + (PORT datab (1153:1153:1153) (1166:1166:1166)) + (PORT datac (885:885:885) (941:941:941)) + (PORT datad (1056:1056:1056) (1047:1047:1047)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~62) + (DELAY + (ABSOLUTE + (PORT dataa (606:606:606) (606:606:606)) + (PORT datab (603:603:603) (596:596:596)) + (PORT datac (561:561:561) (565:565:565)) + (PORT datad (158:158:158) (179:179:179)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~66) + (DELAY + (ABSOLUTE + (PORT dataa (181:181:181) (216:216:216)) + (PORT datab (314:314:314) (332:332:332)) + (PORT datac (169:169:169) (210:210:210)) + (PORT datad (157:157:157) (177:177:177)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (308:308:308) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~53) + (DELAY + (ABSOLUTE + (PORT dataa (1224:1224:1224) (1277:1277:1277)) + (PORT datab (187:187:187) (224:224:224)) + (PORT datac (1096:1096:1096) (1082:1082:1082)) + (PORT datad (1248:1248:1248) (1224:1224:1224)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~52) + (DELAY + (ABSOLUTE + (PORT dataa (1170:1170:1170) (1193:1193:1193)) + (PORT datab (1291:1291:1291) (1258:1258:1258)) + (PORT datac (1027:1027:1027) (998:998:998)) + (PORT datad (808:808:808) (813:813:813)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~84) + (DELAY + (ABSOLUTE + (PORT dataa (1651:1651:1651) (1669:1669:1669)) + (PORT datab (179:179:179) (212:212:212)) + (PORT datac (181:181:181) (218:218:218)) + (PORT datad (1135:1135:1135) (1148:1148:1148)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla91pla20M2T2_3) + (DELAY + (ABSOLUTE + (PORT dataa (1198:1198:1198) (1258:1258:1258)) + (PORT datab (1397:1397:1397) (1426:1426:1426)) + (PORT datac (839:839:839) (824:824:824)) + (PORT datad (1487:1487:1487) (1457:1457:1457)) (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) @@ -25587,75 +22108,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~82) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~55) (DELAY (ABSOLUTE - (PORT dataa (550:550:550) (577:577:577)) - (PORT datab (620:620:620) (634:634:634)) - (PORT datac (1289:1289:1289) (1259:1259:1259)) - (PORT datad (554:554:554) (550:550:550)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1362:1362:1362)) - (PORT asdata (900:900:900) (912:912:912)) - (PORT ena (1105:1105:1105) (1078:1078:1078)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1228:1228:1228) (1220:1220:1220)) - (PORT datab (1145:1145:1145) (1153:1153:1153)) - (PORT datad (604:604:604) (628:628:628)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~20) - (DELAY - (ABSOLUTE - (PORT datab (634:634:634) (641:641:641)) - (PORT datac (611:611:611) (663:663:663)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (654:654:654) (695:695:695)) - (PORT datab (598:598:598) (620:620:620)) - (PORT datac (853:853:853) (867:867:867)) - (PORT datad (555:555:555) (576:576:576)) - (IOPATH dataa combout (329:329:329) (332:332:332)) + (PORT dataa (846:846:846) (874:874:874)) + (PORT datab (199:199:199) (232:232:232)) + (PORT datac (738:738:738) (713:713:713)) + (PORT datad (302:302:302) (302:302:302)) + (IOPATH dataa combout (267:267:267) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -25664,25 +22124,103 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[6\]) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~56) (DELAY (ABSOLUTE - (PORT datac (606:606:606) (624:624:624)) - (PORT datad (759:759:759) (749:749:749)) + (PORT dataa (565:565:565) (575:575:575)) + (PORT datab (603:603:603) (605:605:605)) + (PORT datac (1054:1054:1054) (1037:1037:1037)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[6\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~67) (DELAY (ABSOLUTE - (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT dataa (181:181:181) (217:217:217)) + (PORT datab (181:181:181) (212:212:212)) + (PORT datac (156:156:156) (186:186:186)) + (PORT datad (160:160:160) (180:180:180)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~20) + (DELAY + (ABSOLUTE + (PORT dataa (196:196:196) (240:240:240)) + (PORT datab (364:364:364) (372:372:372)) + (PORT datac (169:169:169) (206:206:206)) + (PORT datad (487:487:487) (484:484:484)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~83) + (DELAY + (ABSOLUTE + (PORT dataa (1179:1179:1179) (1198:1198:1198)) + (PORT datab (1414:1414:1414) (1451:1451:1451)) + (PORT datac (560:560:560) (557:557:557)) + (PORT datad (1162:1162:1162) (1215:1215:1215)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~68) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (220:220:220)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (561:561:561) (566:566:566)) + (PORT datad (158:158:158) (179:179:179)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|Q\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (180:180:180) (202:202:202)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1347:1347:1347) (1368:1368:1368)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1400:1400:1400) (1370:1370:1370)) - (PORT ena (1981:1981:1981) (2010:2010:2010)) + (PORT clrn (1394:1394:1394) (1364:1364:1364)) + (PORT ena (1828:1828:1828) (1776:1776:1776)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -25694,13 +22232,123 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_47\~0) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~72) (DELAY (ABSOLUTE - (PORT dataa (587:587:587) (600:600:600)) - (PORT datab (583:583:583) (601:601:601)) - (PORT datac (749:749:749) (757:757:757)) - (PORT datad (1076:1076:1076) (1064:1064:1064)) + (PORT dataa (609:609:609) (621:621:621)) + (PORT datab (592:592:592) (590:590:590)) + (PORT datac (810:810:810) (804:804:804)) + (PORT datad (166:166:166) (190:190:190)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~73) + (DELAY + (ABSOLUTE + (PORT dataa (1440:1440:1440) (1510:1510:1510)) + (PORT datab (885:885:885) (894:894:894)) + (PORT datac (186:186:186) (223:223:223)) + (PORT datad (1658:1658:1658) (1708:1708:1708)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~74) + (DELAY + (ABSOLUTE + (PORT dataa (189:189:189) (229:229:229)) + (PORT datab (1125:1125:1125) (1130:1130:1130)) + (PORT datac (1243:1243:1243) (1270:1270:1270)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~75) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (218:218:218)) + (PORT datab (188:188:188) (223:223:223)) + (PORT datac (577:577:577) (595:595:595)) + (PORT datad (1094:1094:1094) (1085:1085:1085)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~76) + (DELAY + (ABSOLUTE + (PORT dataa (197:197:197) (242:242:242)) + (PORT datab (188:188:188) (221:221:221)) + (PORT datac (498:498:498) (484:484:484)) + (PORT datad (334:334:334) (336:336:336)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~80) + (DELAY + (ABSOLUTE + (PORT datab (182:182:182) (215:215:215)) + (PORT datac (1072:1072:1072) (1064:1064:1064)) + (PORT datad (166:166:166) (192:192:192)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~81) + (DELAY + (ABSOLUTE + (PORT dataa (1136:1136:1136) (1129:1129:1129)) + (PORT datab (188:188:188) (223:223:223)) + (PORT datac (156:156:156) (186:186:186)) + (PORT datad (560:560:560) (574:574:574)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|d0_out) + (DELAY + (ABSOLUTE + (PORT dataa (1399:1399:1399) (1476:1476:1476)) + (PORT datab (1451:1451:1451) (1407:1407:1407)) + (PORT datac (225:225:225) (299:299:299)) + (PORT datad (1359:1359:1359) (1394:1394:1394)) (IOPATH dataa combout (318:318:318) (307:307:307)) (IOPATH datab combout (319:319:319) (312:312:312)) (IOPATH datac combout (220:220:220) (215:215:215)) @@ -25710,72 +22358,85 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_47) + (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~3) (DELAY (ABSOLUTE - (PORT dataa (182:182:182) (218:218:218)) - (PORT datab (1063:1063:1063) (1063:1063:1063)) - (PORT datac (578:578:578) (590:590:590)) - (PORT datad (565:565:565) (573:573:573)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) + (PORT dataa (1523:1523:1523) (1532:1532:1532)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (741:741:741) (723:723:723)) + (PORT datad (330:330:330) (342:342:342)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|d0_out) + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[0\]) (DELAY (ABSOLUTE - (PORT dataa (397:397:397) (459:459:459)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (318:318:318) (323:323:323)) + (PORT clk (1350:1350:1350) (1371:1371:1371)) + (PORT asdata (904:904:904) (897:897:897)) + (PORT ena (1138:1138:1138) (1126:1126:1126)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1340:1340:1340) (1344:1344:1344)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~24) + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[0\]) (DELAY (ABSOLUTE - (PORT dataa (649:649:649) (686:686:686)) - (PORT datab (886:886:886) (899:899:899)) - (PORT datac (155:155:155) (185:185:185)) - (PORT datad (573:573:573) (580:580:580)) - (IOPATH dataa combout (329:329:329) (332:332:332)) + (PORT clk (1350:1350:1350) (1371:1371:1371)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1110:1110:1110) (1080:1080:1080)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (652:652:652) (686:686:686)) + (PORT datab (651:651:651) (670:670:670)) + (PORT datad (197:197:197) (254:254:254)) + (IOPATH dataa combout (309:309:309) (326:326:326)) (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[7\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[0\]) (DELAY (ABSOLUTE - (PORT clk (1338:1338:1338) (1356:1356:1356)) - (PORT asdata (1115:1115:1115) (1112:1112:1112)) - (PORT ena (1353:1353:1353) (1319:1319:1319)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1338:1338:1338) (1356:1356:1356)) - (PORT asdata (1114:1114:1114) (1114:1114:1114)) - (PORT ena (1145:1145:1145) (1131:1131:1131)) + (PORT clk (1345:1345:1345) (1362:1362:1362)) + (PORT asdata (1152:1152:1152) (1148:1148:1148)) + (PORT ena (1104:1104:1104) (1087:1087:1087)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -25786,12 +22447,188 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~83) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~12) (DELAY (ABSOLUTE - (PORT dataa (1018:1018:1018) (1038:1038:1038)) - (PORT datab (221:221:221) (291:291:291)) - (PORT datad (602:602:602) (623:623:623)) + (PORT dataa (810:810:810) (835:835:835)) + (PORT datab (1056:1056:1056) (1035:1035:1035)) + (PORT datad (517:517:517) (512:512:512)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1077:1077:1077) (1083:1083:1083)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1351:1351:1351) (1372:1372:1372)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (735:735:735) (733:733:733)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1351:1351:1351) (1372:1372:1372)) + (PORT asdata (1629:1629:1629) (1616:1616:1616)) + (PORT ena (765:765:765) (779:779:779)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (364:364:364) (414:414:414)) + (PORT datab (212:212:212) (254:254:254)) + (PORT datad (190:190:190) (214:214:214)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1361:1361:1361)) + (PORT asdata (859:859:859) (854:854:854)) + (PORT ena (735:735:735) (733:733:733)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|db\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (837:837:837) (861:861:861)) + (PORT datab (590:590:590) (617:617:617)) + (PORT datad (587:587:587) (606:606:606)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1361:1361:1361)) + (PORT asdata (859:859:859) (852:852:852)) + (PORT ena (904:904:904) (889:889:889)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (554:554:554) (561:561:561)) + (PORT datab (180:180:180) (213:213:213)) + (PORT datad (209:209:209) (239:239:239)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (594:594:594) (613:613:613)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1362:1362:1362)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1115:1115:1115) (1103:1103:1103)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1344:1344:1344) (1361:1361:1361)) + (PORT asdata (1423:1423:1423) (1413:1413:1413)) + (PORT ena (1131:1131:1131) (1119:1119:1119)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (576:576:576) (614:614:614)) + (PORT datab (649:649:649) (673:673:673)) + (PORT datad (579:579:579) (600:600:600)) (IOPATH dataa combout (329:329:329) (332:332:332)) (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datac combout (312:312:312) (325:325:325)) @@ -25801,12 +22638,206 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[7\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[0\]) (DELAY (ABSOLUTE - (PORT clk (1338:1338:1338) (1356:1356:1356)) - (PORT asdata (1299:1299:1299) (1274:1274:1274)) - (PORT ena (1588:1588:1588) (1555:1555:1555)) + (PORT clk (1344:1344:1344) (1361:1361:1361)) + (PORT asdata (1422:1422:1422) (1413:1413:1413)) + (PORT ena (1175:1175:1175) (1148:1148:1148)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (178:178:178) (200:200:200)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1360:1360:1360)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1321:1321:1321) (1324:1324:1324)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1360:1360:1360)) + (PORT asdata (828:828:828) (821:821:821)) + (PORT ena (716:716:716) (714:714:714)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (360:360:360) (410:410:410)) + (PORT datab (584:584:584) (614:614:614)) + (PORT datad (212:212:212) (247:247:247)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (220:220:220)) + (PORT datab (880:880:880) (891:891:891)) + (PORT datad (523:523:523) (517:517:517)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (601:601:601) (610:610:610)) + (PORT datab (586:586:586) (580:580:580)) + (PORT datac (789:789:789) (777:777:777)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (1045:1045:1045) (1063:1063:1063)) + (PORT datab (611:611:611) (619:619:619)) + (PORT datac (575:575:575) (581:581:581)) + (PORT datad (570:570:570) (566:566:566)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[0\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (327:327:327) (336:336:336)) + (PORT datab (185:185:185) (217:217:217)) + (PORT datac (831:831:831) (835:835:835)) + (PORT datad (183:183:183) (207:207:207)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[0\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (799:799:799) (820:820:820)) + (PORT datab (826:826:826) (814:814:814)) + (PORT datac (157:157:157) (187:187:187)) + (PORT datad (345:345:345) (348:348:348)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[8\]) + (DELAY + (ABSOLUTE + (PORT datac (799:799:799) (797:797:797)) + (PORT datad (877:877:877) (884:884:884)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1357:1357:1357)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1382:1382:1382) (1355:1355:1355)) + (PORT ena (1784:1784:1784) (1745:1745:1745)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|d0_out) + (DELAY + (ABSOLUTE + (PORT datac (587:587:587) (598:598:598)) + (PORT datad (545:545:545) (566:566:566)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1344:1344:1344) (1361:1361:1361)) + (PORT asdata (854:854:854) (853:853:853)) + (PORT ena (894:894:894) (869:869:869)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -25817,12 +22848,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[7\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (1338:1338:1338) (1356:1356:1356)) - (PORT asdata (1299:1299:1299) (1276:1276:1276)) - (PORT ena (1297:1297:1297) (1275:1275:1275)) + (PORT clk (1344:1344:1344) (1361:1361:1361)) + (PORT asdata (854:854:854) (854:854:854)) + (PORT ena (927:927:927) (910:910:910)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -25836,50 +22867,34 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~84) (DELAY (ABSOLUTE - (PORT dataa (814:814:814) (848:848:848)) - (PORT datab (881:881:881) (927:927:927)) - (PORT datad (197:197:197) (253:253:253)) + (PORT dataa (350:350:350) (370:370:370)) + (PORT datab (221:221:221) (290:290:290)) + (PORT datad (345:345:345) (350:350:350)) (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datab combout (306:306:306) (324:324:324)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1370:1370:1370)) - (PORT asdata (1782:1782:1782) (1748:1748:1748)) - (PORT ena (1132:1132:1132) (1112:1112:1112)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[7\]\~feeder) + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[7\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (1496:1496:1496) (1460:1460:1460)) + (PORT datad (1063:1063:1063) (1040:1040:1040)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[7\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (1349:1349:1349) (1370:1370:1370)) + (PORT clk (1351:1351:1351) (1372:1372:1372)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (744:744:744) (751:751:751)) + (PORT ena (735:735:735) (733:733:733)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -25888,29 +22903,14 @@ (HOLD ena (posedge clk) (144:144:144)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~88) - (DELAY - (ABSOLUTE - (PORT dataa (396:396:396) (419:419:419)) - (PORT datab (585:585:585) (612:612:612)) - (PORT datad (342:342:342) (382:382:382)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[7\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (1349:1349:1349) (1370:1370:1370)) - (PORT asdata (1781:1781:1781) (1748:1748:1748)) - (PORT ena (1380:1380:1380) (1365:1365:1365)) + (PORT clk (1351:1351:1351) (1372:1372:1372)) + (PORT asdata (1120:1120:1120) (1101:1101:1101)) + (PORT ena (765:765:765) (779:779:779)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -25919,14 +22919,60 @@ (HOLD ena (posedge clk) (144:144:144)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~83) + (DELAY + (ABSOLUTE + (PORT dataa (360:360:360) (403:403:403)) + (PORT datab (211:211:211) (251:251:251)) + (PORT datad (190:190:190) (217:217:217)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1360:1360:1360)) + (PORT asdata (485:485:485) (512:512:512)) + (PORT ena (1321:1321:1321) (1324:1324:1324)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~88) + (DELAY + (ABSOLUTE + (PORT dataa (640:640:640) (676:676:676)) + (PORT datab (796:796:796) (794:794:794)) + (PORT datad (1246:1246:1246) (1196:1196:1196)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (1342:1342:1342) (1359:1359:1359)) - (PORT asdata (1795:1795:1795) (1766:1766:1766)) - (PORT ena (1155:1155:1155) (1140:1140:1140)) + (PORT clk (1345:1345:1345) (1362:1362:1362)) + (PORT asdata (1096:1096:1096) (1101:1101:1101)) + (PORT ena (1115:1115:1115) (1103:1103:1103)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -25940,9 +22986,9 @@ (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (1342:1342:1342) (1359:1359:1359)) - (PORT asdata (1795:1795:1795) (1766:1766:1766)) - (PORT ena (1109:1109:1109) (1074:1074:1074)) + (PORT clk (1345:1345:1345) (1362:1362:1362)) + (PORT asdata (1096:1096:1096) (1101:1101:1101)) + (PORT ena (1104:1104:1104) (1087:1087:1087)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -25956,9 +23002,9 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~86) (DELAY (ABSOLUTE - (PORT dataa (401:401:401) (436:436:436)) - (PORT datab (220:220:220) (287:287:287)) - (PORT datad (587:587:587) (591:591:591)) + (PORT dataa (803:803:803) (829:829:829)) + (PORT datab (220:220:220) (288:288:288)) + (PORT datad (624:624:624) (648:648:648)) (IOPATH dataa combout (329:329:329) (332:332:332)) (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datac combout (312:312:312) (325:325:325)) @@ -25966,27 +23012,108 @@ ) ) ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1360:1360:1360)) + (PORT asdata (870:870:870) (860:860:860)) + (PORT ena (716:716:716) (714:714:714)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1360:1360:1360)) + (PORT asdata (870:870:870) (862:862:862)) + (PORT ena (1177:1177:1177) (1173:1173:1173)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~87) (DELAY (ABSOLUTE - (PORT datab (1303:1303:1303) (1287:1287:1287)) - (PORT datad (543:543:543) (535:535:535)) - (IOPATH datab combout (295:295:295) (285:285:285)) + (PORT dataa (621:621:621) (666:666:666)) + (PORT datab (219:219:219) (287:287:287)) + (PORT datad (212:212:212) (248:248:248)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1356:1356:1356)) + (PORT asdata (894:894:894) (897:897:897)) + (PORT ena (764:764:764) (771:771:771)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|db\[7\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1078:1078:1078) (1060:1060:1060)) + (PORT datab (820:820:820) (841:841:841)) + (PORT datad (865:865:865) (883:883:883)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~89) + (DELAY + (ABSOLUTE + (PORT dataa (599:599:599) (588:588:588)) + (PORT datab (832:832:832) (831:831:831)) + (PORT datac (538:538:538) (531:531:531)) + (PORT datad (158:158:158) (179:179:179)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (1349:1349:1349) (1371:1371:1371)) - (PORT asdata (1602:1602:1602) (1574:1574:1574)) - (PORT ena (746:746:746) (759:759:759)) + (PORT clk (1350:1350:1350) (1371:1371:1371)) + (PORT asdata (1142:1142:1142) (1121:1121:1121)) + (PORT ena (1138:1138:1138) (1126:1126:1126)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -26000,9 +23127,9 @@ (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (1349:1349:1349) (1371:1371:1371)) - (PORT asdata (1600:1600:1600) (1576:1576:1576)) - (PORT ena (1154:1154:1154) (1142:1142:1142)) + (PORT clk (1350:1350:1350) (1371:1371:1371)) + (PORT asdata (1138:1138:1138) (1116:1116:1116)) + (PORT ena (1110:1110:1110) (1080:1080:1080)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -26016,9 +23143,9 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~85) (DELAY (ABSOLUTE - (PORT dataa (381:381:381) (422:422:422)) - (PORT datab (544:544:544) (553:553:553)) - (PORT datad (197:197:197) (252:252:252)) + (PORT dataa (645:645:645) (674:674:674)) + (PORT datab (647:647:647) (664:664:664)) + (PORT datad (199:199:199) (256:256:256)) (IOPATH dataa combout (309:309:309) (326:326:326)) (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (312:312:312) (325:325:325)) @@ -26026,47 +23153,15 @@ ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1344:1344:1344) (1362:1362:1362)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1342:1342:1342) (1311:1311:1311)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~89) - (DELAY - (ABSOLUTE - (PORT dataa (594:594:594) (648:648:648)) - (PORT datab (881:881:881) (883:883:883)) - (PORT datac (778:778:778) (757:757:757)) - (PORT datad (562:562:562) (569:569:569)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~90) (DELAY (ABSOLUTE - (PORT dataa (182:182:182) (218:218:218)) - (PORT datab (182:182:182) (214:214:214)) - (PORT datac (462:462:462) (448:448:448)) - (PORT datad (159:159:159) (181:181:181)) + (PORT dataa (183:183:183) (219:219:219)) + (PORT datab (609:609:609) (603:603:603)) + (PORT datac (724:724:724) (696:696:696)) + (PORT datad (723:723:723) (695:695:695)) (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) @@ -26079,26 +23174,73 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~91) (DELAY (ABSOLUTE - (PORT dataa (184:184:184) (221:221:221)) - (PORT datab (340:340:340) (346:346:346)) - (PORT datad (532:532:532) (520:520:520)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) + (PORT dataa (546:546:546) (541:541:541)) + (PORT datab (609:609:609) (621:621:621)) + (PORT datac (1015:1015:1015) (1033:1033:1033)) + (PORT datad (567:567:567) (560:560:560)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~92) + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[7\]) (DELAY (ABSOLUTE - (PORT dataa (616:616:616) (641:641:641)) - (PORT datab (615:615:615) (627:627:627)) - (PORT datac (1288:1288:1288) (1258:1258:1258)) - (PORT datad (553:553:553) (552:552:552)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (273:273:273) (275:275:275)) + (PORT clk (1339:1339:1339) (1356:1356:1356)) + (PORT asdata (638:638:638) (640:640:640)) + (PORT ena (735:735:735) (733:733:733)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (609:609:609) (623:623:623)) + (PORT datab (200:200:200) (234:234:234)) + (PORT datad (983:983:983) (966:966:966)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1355:1355:1355)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (903:903:903) (900:900:900)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (319:319:319) (329:329:329)) + (PORT datac (313:313:313) (322:322:322)) + (PORT datad (198:198:198) (256:256:256)) + (IOPATH dataa combout (318:318:318) (323:323:323)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -26106,29 +23248,51 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_ds\[7\]\~0) + (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~24) (DELAY (ABSOLUTE - (PORT dataa (1379:1379:1379) (1380:1380:1380)) - (PORT datab (1534:1534:1534) (1526:1526:1526)) - (PORT datac (807:807:807) (810:810:810)) - (PORT datad (1078:1078:1078) (1071:1071:1071)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) + (PORT dataa (762:762:762) (748:748:748)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (512:512:512) (511:511:511)) + (PORT datad (1692:1692:1692) (1662:1662:1662)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[7\]) + (DELAY + (ABSOLUTE + (PORT dataa (573:573:573) (563:563:563)) + (PORT datac (788:788:788) (773:773:773)) + (IOPATH dataa combout (318:318:318) (327:327:327)) (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|Q\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (177:177:177) (199:199:199)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|im2) + (INSTANCE z80_\|address_latch_\|Q\[7\]) (DELAY (ABSOLUTE - (PORT clk (1345:1345:1345) (1366:1366:1366)) + (PORT clk (1341:1341:1341) (1358:1358:1358)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1390:1390:1390) (1361:1361:1361)) - (PORT ena (1156:1156:1156) (1147:1147:1147)) + (PORT clrn (1384:1384:1384) (1357:1357:1357)) + (PORT ena (1540:1540:1540) (1508:1508:1508)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -26140,13 +23304,76 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~12) + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|d1_out) (DELAY (ABSOLUTE - (PORT dataa (325:325:325) (451:451:451)) - (PORT datac (1130:1130:1130) (1175:1175:1175)) - (PORT datad (250:250:250) (317:317:317)) - (IOPATH dataa combout (287:287:287) (289:289:289)) + (PORT dataa (834:834:834) (836:836:836)) + (PORT datab (890:890:890) (933:933:933)) + (PORT datac (602:602:602) (629:629:629)) + (PORT datad (545:545:545) (569:569:569)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1341:1341:1341) (1358:1358:1358)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1169:1169:1169) (1174:1174:1174)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1341:1341:1341) (1358:1358:1358)) + (PORT asdata (1338:1338:1338) (1305:1305:1305)) + (PORT ena (1132:1132:1132) (1119:1119:1119)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (619:619:619) (641:641:641)) + (PORT datab (613:613:613) (623:623:623)) + (PORT datad (559:559:559) (549:549:549)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT datab (998:998:998) (984:984:984)) + (PORT datac (197:197:197) (264:264:264)) + (PORT datad (161:161:161) (182:182:182)) + (IOPATH datab combout (295:295:295) (285:285:285)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -26154,95 +23381,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_mask543_en\~0) + (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~6) (DELAY (ABSOLUTE - (PORT dataa (326:326:326) (453:453:453)) - (PORT datab (663:663:663) (674:674:674)) - (PORT datac (173:173:173) (204:204:204)) - (PORT datad (1201:1201:1201) (1270:1270:1270)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[7\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (813:813:813) (813:813:813)) - (PORT datab (862:862:862) (865:865:865)) - (PORT datac (573:573:573) (605:605:605)) - (PORT datad (589:589:589) (590:590:590)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[7\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (778:778:778) (765:765:765)) - (PORT datab (785:785:785) (798:798:798)) - (PORT datac (832:832:832) (840:840:840)) - (PORT datad (587:587:587) (633:633:633)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[7\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (186:186:186) (224:224:224)) - (PORT datab (219:219:219) (262:262:262)) - (PORT datac (584:584:584) (609:609:609)) - (PORT datad (574:574:574) (563:563:563)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_34) - (DELAY - (ABSOLUTE - (PORT dataa (642:642:642) (662:662:662)) - (PORT datab (825:825:825) (837:837:837)) - (PORT datac (791:791:791) (766:766:766)) - (PORT datad (184:184:184) (210:210:210)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1159:1159:1159) (1215:1215:1215)) - (PORT datab (793:793:793) (816:816:816)) - (PORT datac (563:563:563) (574:574:574)) - (PORT datad (177:177:177) (199:199:199)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) + (PORT dataa (616:616:616) (608:608:608)) + (PORT datab (183:183:183) (216:216:216)) + (PORT datac (541:541:541) (541:541:541)) + (PORT datad (1236:1236:1236) (1229:1229:1229)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -26250,12 +23397,304 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_sf) + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[0\]) (DELAY (ABSOLUTE - (PORT clk (1331:1331:1331) (1350:1350:1350)) + (PORT clk (1339:1339:1339) (1356:1356:1356)) + (PORT asdata (1080:1080:1080) (1055:1055:1055)) + (PORT ena (744:744:744) (751:751:751)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1356:1356:1356)) + (PORT asdata (1080:1080:1080) (1058:1058:1058)) + (PORT ena (1132:1132:1132) (1119:1119:1119)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (655:655:655) (681:681:681)) + (PORT datab (238:238:238) (282:282:282)) + (PORT datad (198:198:198) (255:255:255)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1341:1341:1341) (1359:1359:1359)) + (PORT asdata (1725:1725:1725) (1703:1703:1703)) + (PORT ena (1076:1076:1076) (1031:1031:1031)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1340:1340:1340) (1358:1358:1358)) + (PORT asdata (1726:1726:1726) (1693:1693:1693)) + (PORT ena (1127:1127:1127) (1112:1112:1112)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (637:637:637) (648:648:648)) + (PORT datab (238:238:238) (297:297:297)) + (PORT datad (358:358:358) (392:392:392)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1340:1340:1340) (1358:1358:1358)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (765:765:765) (779:779:779)) + (PORT ena (1131:1131:1131) (1124:1124:1124)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1340:1340:1340) (1358:1358:1358)) + (PORT asdata (822:822:822) (802:802:802)) + (PORT ena (1376:1376:1376) (1350:1350:1350)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (646:646:646) (696:696:696)) + (PORT datab (545:545:545) (583:583:583)) + (PORT datad (645:645:645) (662:662:662)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1356:1356:1356)) + (PORT asdata (1544:1544:1544) (1545:1545:1545)) + (PORT ena (1322:1322:1322) (1264:1264:1264)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1356:1356:1356)) + (PORT asdata (1543:1543:1543) (1545:1545:1545)) + (PORT ena (1126:1126:1126) (1110:1110:1110)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (646:646:646) (683:683:683)) + (PORT datab (599:599:599) (599:599:599)) + (PORT datad (196:196:196) (252:252:252)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1340:1340:1340) (1358:1358:1358)) + (PORT asdata (1729:1729:1729) (1697:1697:1697)) + (PORT ena (1109:1109:1109) (1079:1079:1079)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (1085:1085:1085) (1110:1110:1110)) + (PORT datab (841:841:841) (843:843:843)) + (PORT datad (378:378:378) (400:400:400)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (555:555:555) (561:561:561)) + (PORT datab (357:357:357) (358:358:358)) + (PORT datac (809:809:809) (800:800:800)) + (PORT datad (566:566:566) (558:558:558)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1357:1357:1357)) + (PORT asdata (1700:1700:1700) (1686:1686:1686)) + (PORT ena (716:716:716) (714:714:714)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[0\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1385:1385:1385) (1422:1422:1422)) + (PORT datab (2001:2001:2001) (1996:1996:1996)) + (PORT datad (1257:1257:1257) (1223:1223:1223)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1356:1356:1356)) + (PORT asdata (1679:1679:1679) (1659:1659:1659)) + (PORT ena (898:898:898) (891:891:891)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1159:1159:1159) (1144:1144:1144)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1356:1356:1356)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1093:1093:1093) (1055:1055:1055)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -26266,13 +23705,28 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal62\~3) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~22) (DELAY (ABSOLUTE - (PORT dataa (1352:1352:1352) (1422:1422:1422)) - (PORT datab (1360:1360:1360) (1401:1401:1401)) - (PORT datac (1021:1021:1021) (1041:1041:1041)) - (PORT datad (597:597:597) (607:607:607)) + (PORT dataa (623:623:623) (642:642:642)) + (PORT datab (631:631:631) (648:648:648)) + (PORT datad (198:198:198) (255:255:255)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (835:835:835) (843:843:843)) + (PORT datab (183:183:183) (216:216:216)) + (PORT datac (581:581:581) (564:564:564)) + (PORT datad (556:556:556) (555:555:555)) (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) @@ -26282,31 +23736,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~5) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~30) (DELAY (ABSOLUTE - (PORT dataa (1042:1042:1042) (1037:1037:1037)) - (PORT datab (694:694:694) (696:696:696)) - (PORT datac (1298:1298:1298) (1313:1313:1313)) - (PORT datad (1097:1097:1097) (1118:1118:1118)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (308:308:308) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (859:859:859) (899:899:899)) - (PORT datab (1077:1077:1077) (1086:1086:1086)) - (PORT datac (682:682:682) (744:744:744)) - (PORT datad (1745:1745:1745) (1842:1842:1842)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (319:319:319) (324:324:324)) + (PORT dataa (588:588:588) (605:605:605)) + (PORT datab (343:343:343) (350:350:350)) + (PORT datac (1045:1045:1045) (1049:1049:1049)) + (PORT datad (810:810:810) (822:822:822)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -26314,14 +23752,890 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~7) + (INSTANCE z80_\|alu_\|db\[0\]\~13) (DELAY (ABSOLUTE - (PORT dataa (676:676:676) (717:717:717)) - (PORT datab (1288:1288:1288) (1362:1362:1362)) - (PORT datac (1032:1032:1032) (1024:1024:1024)) - (PORT datad (179:179:179) (212:212:212)) + (PORT dataa (581:581:581) (606:606:606)) + (PORT datab (637:637:637) (630:630:630)) + (PORT datac (778:778:778) (759:759:759)) + (PORT datad (632:632:632) (656:656:656)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[0\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (791:791:791) (795:795:795)) + (PORT datab (226:226:226) (285:285:285)) + (PORT datac (531:531:531) (536:536:536)) + (PORT datad (161:161:161) (182:182:182)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (835:835:835) (828:828:828)) + (PORT datab (788:788:788) (779:779:779)) + (PORT datad (1085:1085:1085) (1119:1119:1119)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (779:779:779) (784:784:784)) + (PORT datab (1196:1196:1196) (1174:1174:1174)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (223:223:223) (271:271:271)) + (PORT datab (544:544:544) (568:568:568)) + (PORT datac (553:553:553) (542:542:542)) + (PORT datad (819:819:819) (826:826:826)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (255:255:255) (321:321:321)) + (PORT datab (244:244:244) (304:304:304)) + (PORT datac (1010:1010:1010) (1017:1017:1017)) + (PORT datad (216:216:216) (256:256:256)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|result_lo\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (178:178:178) (201:201:201)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|result_lo\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1353:1353:1353) (1370:1370:1370)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1571:1571:1571) (1556:1556:1556)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (220:220:220)) + (PORT datab (737:737:737) (726:726:726)) + (PORT datac (499:499:499) (491:491:491)) + (PORT datad (355:355:355) (388:388:388)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (350:350:350) (358:358:358)) + (PORT datab (645:645:645) (665:665:665)) + (PORT datac (632:632:632) (661:661:661)) + (PORT datad (553:553:553) (554:554:554)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[1\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (584:584:584) (606:606:606)) + (PORT datab (562:562:562) (566:566:566)) + (PORT datac (593:593:593) (599:599:599)) + (PORT datad (1049:1049:1049) (1055:1055:1055)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (675:675:675) (699:699:699)) + (PORT datab (224:224:224) (282:282:282)) + (PORT datac (806:806:806) (788:788:788)) + (PORT datad (162:162:162) (184:184:184)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1340:1340:1340) (1358:1358:1358)) + (PORT asdata (1314:1314:1314) (1297:1297:1297)) + (PORT ena (1109:1109:1109) (1079:1079:1079)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1083:1083:1083) (1111:1111:1111)) + (PORT datab (1347:1347:1347) (1343:1343:1343)) + (PORT datad (370:370:370) (396:396:396)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (814:814:814) (807:807:807)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1341:1341:1341) (1359:1359:1359)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1076:1076:1076) (1031:1031:1031)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1340:1340:1340) (1358:1358:1358)) + (PORT asdata (1316:1316:1316) (1297:1297:1297)) + (PORT ena (1127:1127:1127) (1112:1112:1112)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (562:562:562) (566:566:566)) + (PORT datab (347:347:347) (397:397:397)) + (PORT datad (326:326:326) (322:322:322)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1356:1356:1356)) + (PORT asdata (1339:1339:1339) (1324:1324:1324)) + (PORT ena (1126:1126:1126) (1110:1110:1110)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1356:1356:1356)) + (PORT asdata (1340:1340:1340) (1323:1323:1323)) + (PORT ena (1322:1322:1322) (1264:1264:1264)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (644:644:644) (687:687:687)) + (PORT datab (600:600:600) (610:610:610)) + (PORT datad (198:198:198) (255:255:255)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1340:1340:1340) (1358:1358:1358)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1376:1376:1376) (1350:1350:1350)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1340:1340:1340) (1358:1358:1358)) + (PORT asdata (644:644:644) (658:658:658)) + (PORT ena (1131:1131:1131) (1124:1124:1124)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (651:651:651) (700:700:700)) + (PORT datab (219:219:219) (287:287:287)) + (PORT datad (646:646:646) (657:657:657)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (184:184:184) (221:221:221)) + (PORT datab (184:184:184) (217:217:217)) + (PORT datac (583:583:583) (571:571:571)) + (PORT datad (516:516:516) (497:497:497)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1357:1357:1357)) + (PORT asdata (826:826:826) (820:820:820)) + (PORT ena (716:716:716) (714:714:714)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1387:1387:1387) (1423:1423:1423)) + (PORT datab (1993:1993:1993) (1991:1991:1991)) + (PORT datad (1257:1257:1257) (1221:1221:1221)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1356:1356:1356)) + (PORT asdata (1352:1352:1352) (1367:1367:1367)) + (PORT ena (1132:1132:1132) (1119:1119:1119)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1356:1356:1356)) + (PORT asdata (1349:1349:1349) (1364:1364:1364)) + (PORT ena (744:744:744) (751:751:751)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (658:658:658) (688:688:688)) + (PORT datab (222:222:222) (291:291:291)) + (PORT datad (208:208:208) (241:241:241)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1356:1356:1356)) + (PORT asdata (1363:1363:1363) (1377:1377:1377)) + (PORT ena (898:898:898) (891:891:891)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (557:557:557) (558:558:558)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1356:1356:1356)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1093:1093:1093) (1055:1055:1055)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (622:622:622) (635:635:635)) + (PORT datab (632:632:632) (643:643:643)) + (PORT datad (198:198:198) (254:254:254)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (587:587:587) (582:582:582)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (562:562:562) (555:555:555)) + (PORT datad (298:298:298) (300:300:300)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (1086:1086:1086) (1085:1085:1085)) + (PORT datab (352:352:352) (351:351:351)) + (PORT datac (774:774:774) (754:754:754)) + (PORT datad (813:813:813) (822:822:822)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1342:1342:1342) (1359:1359:1359)) + (PORT asdata (780:780:780) (769:769:769)) + (PORT ena (1335:1335:1335) (1307:1307:1307)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (645:645:645) (653:653:653)) + (PORT datab (652:652:652) (671:671:671)) + (PORT datad (593:593:593) (607:607:607)) (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (295:295:295)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datad (595:595:595) (611:611:611)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1041:1041:1041) (1053:1053:1053)) + (PORT datab (181:181:181) (213:213:213)) + (PORT datac (1256:1256:1256) (1257:1257:1257)) + (PORT datad (200:200:200) (235:235:235)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[9\]) + (DELAY + (ABSOLUTE + (PORT datac (828:828:828) (829:829:829)) + (PORT datad (875:875:875) (879:879:879)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|Q\[9\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (164:164:164) (187:187:187)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1357:1357:1357)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1382:1382:1382) (1355:1355:1355)) + (PORT ena (1784:1784:1784) (1745:1745:1745)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[10\]) + (DELAY + (ABSOLUTE + (PORT dataa (587:587:587) (595:595:595)) + (PORT datad (551:551:551) (550:550:550)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1340:1340:1340) (1357:1357:1357)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1384:1384:1384) (1356:1356:1356)) + (PORT ena (1738:1738:1738) (1696:1696:1696)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|d1_out) + (DELAY + (ABSOLUTE + (PORT dataa (198:198:198) (242:242:242)) + (PORT datab (631:631:631) (656:656:656)) + (PORT datac (868:868:868) (912:912:912)) + (PORT datad (389:389:389) (428:428:428)) + (IOPATH dataa combout (307:307:307) (323:323:323)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1342:1342:1342) (1359:1359:1359)) + (PORT asdata (615:615:615) (630:630:630)) + (PORT ena (1335:1335:1335) (1307:1307:1307)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (824:824:824) (819:819:819)) + (PORT datab (652:652:652) (676:676:676)) + (PORT datad (595:595:595) (612:612:612)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1342:1342:1342) (1359:1359:1359)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1154:1154:1154) (1149:1149:1149)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (217:217:217)) + (PORT datab (633:633:633) (643:643:643)) + (PORT datad (199:199:199) (255:255:255)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (582:582:582) (598:598:598)) + (PORT datab (1283:1283:1283) (1286:1286:1286)) + (PORT datac (156:156:156) (187:187:187)) + (PORT datad (200:200:200) (235:235:235)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (1082:1082:1082) (1077:1077:1077)) + (PORT datab (531:531:531) (529:529:529)) + (PORT datac (575:575:575) (578:578:578)) + (PORT datad (811:811:811) (819:819:819)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[2\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (577:577:577) (567:567:567)) + (PORT datab (585:585:585) (583:583:583)) + (PORT datac (494:494:494) (485:485:485)) + (PORT datad (559:559:559) (555:555:555)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[2\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (673:673:673) (690:690:690)) + (PORT datab (536:536:536) (533:533:533)) + (PORT datac (190:190:190) (243:243:243)) + (PORT datad (589:589:589) (585:585:585)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[2\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (608:608:608) (605:605:605)) + (PORT datab (807:807:807) (813:813:813)) + (PORT datac (330:330:330) (351:351:351)) + (PORT datad (786:786:786) (772:772:772)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~2) + (DELAY + (ABSOLUTE + (PORT datab (213:213:213) (250:250:250)) + (PORT datac (739:739:739) (711:711:711)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|flags_hf2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (380:380:380) (388:388:388)) + (PORT datab (183:183:183) (217:217:217)) + (PORT datad (604:604:604) (626:626:626)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|flags_hf2) + (DELAY + (ABSOLUTE + (PORT clk (1353:1353:1353) (1371:1371:1371)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[2\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (1055:1055:1055) (1070:1070:1070)) + (PORT datab (655:655:655) (712:712:712)) + (PORT datac (794:794:794) (801:801:801)) + (PORT datad (170:170:170) (198:198:198)) + (IOPATH dataa combout (309:309:309) (326:326:326)) (IOPATH datab combout (306:306:306) (324:324:324)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -26330,13 +24644,446 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~8) + (INSTANCE z80_\|alu_control_\|db\[2\]\~29) (DELAY (ABSOLUTE - (PORT dataa (604:604:604) (593:593:593)) - (PORT datab (762:762:762) (741:741:741)) - (PORT datac (1037:1037:1037) (1041:1041:1041)) - (PORT datad (158:158:158) (178:178:178)) + (PORT dataa (316:316:316) (335:335:335)) + (PORT datab (180:180:180) (212:212:212)) + (PORT datac (550:550:550) (543:543:543)) + (PORT datad (196:196:196) (223:223:223)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (773:773:773) (768:768:768)) + (PORT datab (567:567:567) (588:588:588)) + (PORT datac (323:323:323) (337:337:337)) + (PORT datad (556:556:556) (569:569:569)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1350:1350:1350) (1371:1371:1371)) + (PORT asdata (1143:1143:1143) (1114:1114:1114)) + (PORT ena (1138:1138:1138) (1126:1126:1126)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1350:1350:1350) (1371:1371:1371)) + (PORT asdata (1140:1140:1140) (1111:1111:1111)) + (PORT ena (1110:1110:1110) (1080:1080:1080)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (651:651:651) (685:685:685)) + (PORT datab (651:651:651) (669:669:669)) + (PORT datad (198:198:198) (256:256:256)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (365:365:365)) + (PORT datab (310:310:310) (329:329:329)) + (PORT datac (157:157:157) (188:188:188)) + (PORT datad (584:584:584) (595:595:595)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~41) + (DELAY + (ABSOLUTE + (PORT dataa (496:496:496) (485:485:485)) + (PORT datab (180:180:180) (213:213:213)) + (PORT datad (570:570:570) (564:564:564)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (1044:1044:1044) (1066:1066:1066)) + (PORT datab (576:576:576) (560:560:560)) + (PORT datac (581:581:581) (593:593:593)) + (PORT datad (601:601:601) (605:605:605)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1340:1340:1340) (1357:1357:1357)) + (PORT asdata (485:485:485) (512:512:512)) + (PORT ena (1107:1107:1107) (1064:1064:1064)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (826:826:826) (850:850:850)) + (PORT datab (639:639:639) (643:643:643)) + (PORT datad (377:377:377) (394:394:394)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (358:358:358) (407:407:407)) + (PORT datac (155:155:155) (184:184:184)) + (PORT datad (569:569:569) (562:562:562)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_41) + (DELAY + (ABSOLUTE + (PORT dataa (1708:1708:1708) (1740:1740:1740)) + (PORT datab (368:368:368) (414:414:414)) + (PORT datac (1190:1190:1190) (1155:1155:1155)) + (PORT datad (177:177:177) (210:210:210)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|SYNTHESIZED_WIRE_0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1402:1402:1402) (1477:1477:1477)) + (PORT datab (1382:1382:1382) (1424:1424:1424)) + (PORT datac (1425:1425:1425) (1382:1382:1382)) + (PORT datad (318:318:318) (321:321:321)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|d0_out) + (DELAY + (ABSOLUTE + (PORT dataa (887:887:887) (927:927:927)) + (PORT datac (345:345:345) (360:360:360)) + (PORT datad (172:172:172) (202:202:202)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (217:217:217)) + (PORT datab (358:358:358) (374:374:374)) + (PORT datac (1495:1495:1495) (1496:1496:1496)) + (PORT datad (555:555:555) (545:545:545)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[2\]) + (DELAY + (ABSOLUTE + (PORT datac (857:857:857) (856:856:856)) + (PORT datad (570:570:570) (564:564:564)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1347:1347:1347) (1368:1368:1368)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1394:1394:1394) (1364:1364:1364)) + (PORT ena (1828:1828:1828) (1776:1776:1776)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_42) + (DELAY + (ABSOLUTE + (PORT dataa (1631:1631:1631) (1673:1673:1673)) + (PORT datab (1325:1325:1325) (1310:1310:1310)) + (PORT datac (188:188:188) (234:234:234)) + (PORT datad (1716:1716:1716) (1768:1768:1768)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1340:1340:1340) (1357:1357:1357)) + (PORT asdata (484:484:484) (510:510:510)) + (PORT ena (1107:1107:1107) (1064:1064:1064)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (826:826:826) (846:846:846)) + (PORT datab (1046:1046:1046) (1031:1031:1031)) + (PORT datad (380:380:380) (391:391:391)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1340:1340:1340) (1357:1357:1357)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1132:1132:1132) (1111:1111:1111)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (597:597:597) (606:606:606)) + (PORT datab (180:180:180) (212:212:212)) + (PORT datad (330:330:330) (372:372:372)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|d1_out) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (242:242:242)) + (PORT datab (609:609:609) (641:641:641)) + (PORT datac (340:340:340) (353:353:353)) + (PORT datad (164:164:164) (188:188:188)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1523:1523:1523) (1527:1527:1527)) + (PORT datab (180:180:180) (212:212:212)) + (PORT datac (565:565:565) (557:557:557)) + (PORT datad (329:329:329) (338:338:338)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[3\]) + (DELAY + (ABSOLUTE + (PORT datab (887:887:887) (886:886:886)) + (PORT datac (525:525:525) (509:509:509)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1347:1347:1347) (1368:1368:1368)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1394:1394:1394) (1364:1364:1364)) + (PORT ena (1828:1828:1828) (1776:1776:1776)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_45\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1763:1763:1763) (1810:1810:1810)) + (PORT datab (610:610:610) (638:638:638)) + (PORT datac (185:185:185) (229:229:229)) + (PORT datad (1608:1608:1608) (1634:1634:1634)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|carry_borrow_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (197:197:197) (241:241:241)) + (PORT datab (189:189:189) (224:224:224)) + (PORT datac (342:342:342) (359:359:359)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_47\~0) + (DELAY + (ABSOLUTE + (PORT dataa (895:895:895) (928:928:928)) + (PORT datab (201:201:201) (243:243:243)) + (PORT datac (187:187:187) (233:233:233)) + (PORT datad (1236:1236:1236) (1200:1200:1200)) (IOPATH dataa combout (329:329:329) (332:332:332)) (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (220:220:220) (215:215:215)) @@ -26346,14 +25093,1213 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~9) + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_47) (DELAY (ABSOLUTE - (PORT dataa (615:615:615) (617:617:617)) - (PORT datab (956:956:956) (977:977:977)) - (PORT datac (527:527:527) (511:511:511)) - (PORT datad (836:836:836) (845:845:845)) - (IOPATH dataa combout (267:267:267) (269:269:269)) + (PORT dataa (209:209:209) (248:248:248)) + (PORT datab (188:188:188) (225:225:225)) + (PORT datac (163:163:163) (199:199:199)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|carry_borrow_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (837:837:837) (838:838:838)) + (PORT datab (892:892:892) (931:931:931)) + (PORT datac (606:606:606) (626:626:626)) + (PORT datad (546:546:546) (565:565:565)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|carry_borrow_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (196:196:196) (237:237:237)) + (PORT datab (633:633:633) (659:659:659)) + (PORT datac (867:867:867) (908:908:908)) + (PORT datad (387:387:387) (423:423:423)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[11\]) + (DELAY + (ABSOLUTE + (PORT datac (220:220:220) (289:289:289)) + (PORT datad (169:169:169) (198:198:198)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (220:220:220) (265:265:265)) + (PORT datab (1280:1280:1280) (1280:1280:1280)) + (PORT datac (156:156:156) (187:187:187)) + (PORT datad (564:564:564) (559:559:559)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1356:1356:1356)) + (PORT asdata (1099:1099:1099) (1077:1077:1077)) + (PORT ena (1132:1132:1132) (1119:1119:1119)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1356:1356:1356)) + (PORT asdata (1097:1097:1097) (1075:1075:1075)) + (PORT ena (744:744:744) (751:751:751)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~41) + (DELAY + (ABSOLUTE + (PORT dataa (655:655:655) (682:682:682)) + (PORT datab (220:220:220) (288:288:288)) + (PORT datad (214:214:214) (248:248:248)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1340:1340:1340) (1358:1358:1358)) + (PORT asdata (635:635:635) (642:642:642)) + (PORT ena (1131:1131:1131) (1124:1124:1124)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1340:1340:1340) (1358:1358:1358)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1376:1376:1376) (1350:1350:1350)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~45) + (DELAY + (ABSOLUTE + (PORT dataa (650:650:650) (697:697:697)) + (PORT datab (584:584:584) (584:584:584)) + (PORT datad (196:196:196) (252:252:252)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1340:1340:1340) (1358:1358:1358)) + (PORT asdata (918:918:918) (917:917:917)) + (PORT ena (1109:1109:1109) (1079:1079:1079)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~44) + (DELAY + (ABSOLUTE + (PORT dataa (1084:1084:1084) (1111:1111:1111)) + (PORT datab (857:857:857) (860:860:860)) + (PORT datad (377:377:377) (392:392:392)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1341:1341:1341) (1359:1359:1359)) + (PORT asdata (915:915:915) (914:914:914)) + (PORT ena (1132:1132:1132) (1121:1121:1121)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1341:1341:1341) (1359:1359:1359)) + (PORT asdata (914:914:914) (911:911:911)) + (PORT ena (1076:1076:1076) (1031:1031:1031)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~43) + (DELAY + (ABSOLUTE + (PORT dataa (637:637:637) (649:649:649)) + (PORT datab (237:237:237) (297:297:297)) + (PORT datad (327:327:327) (366:366:366)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1356:1356:1356)) + (PORT asdata (1137:1137:1137) (1120:1120:1120)) + (PORT ena (1322:1322:1322) (1264:1264:1264)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1356:1356:1356)) + (PORT asdata (1137:1137:1137) (1119:1119:1119)) + (PORT ena (1126:1126:1126) (1110:1110:1110)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (643:643:643) (680:680:680)) + (PORT datab (220:220:220) (287:287:287)) + (PORT datad (564:564:564) (570:570:570)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (577:577:577) (587:587:587)) + (PORT datab (309:309:309) (328:328:328)) + (PORT datac (493:493:493) (477:477:477)) + (PORT datad (301:301:301) (302:302:302)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (563:563:563) (557:557:557)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1356:1356:1356)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1093:1093:1093) (1055:1055:1055)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1356:1356:1356)) + (PORT asdata (871:871:871) (862:862:862)) + (PORT ena (898:898:898) (891:891:891)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (627:627:627) (642:642:642)) + (PORT datab (221:221:221) (290:290:290)) + (PORT datad (573:573:573) (572:572:572)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1357:1357:1357)) + (PORT asdata (1070:1070:1070) (1050:1050:1050)) + (PORT ena (716:716:716) (714:714:714)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[3\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1672:1672:1672) (1686:1686:1686)) + (PORT datab (610:610:610) (609:609:609)) + (PORT datac (1712:1712:1712) (1748:1748:1748)) + (PORT datad (801:801:801) (811:811:811)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (596:596:596) (622:622:622)) + (PORT datab (181:181:181) (213:213:213)) + (PORT datac (586:586:586) (582:582:582)) + (PORT datad (159:159:159) (179:179:179)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~48) + (DELAY + (ABSOLUTE + (PORT dataa (591:591:591) (602:602:602)) + (PORT datab (851:851:851) (852:852:852)) + (PORT datac (1045:1045:1045) (1044:1044:1044)) + (PORT datad (547:547:547) (533:533:533)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[3\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (577:577:577) (601:601:601)) + (PORT datab (581:581:581) (586:586:586)) + (PORT datac (583:583:583) (579:579:579)) + (PORT datad (626:626:626) (649:649:649)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[3\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (558:558:558) (558:558:558)) + (PORT datab (225:225:225) (283:283:283)) + (PORT datac (532:532:532) (540:540:540)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[2\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (1016:1016:1016) (996:996:996)) + (PORT datab (1067:1067:1067) (1102:1102:1102)) + (PORT datad (570:570:570) (568:568:568)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[2\]\~22) + (DELAY + (ABSOLUTE + (PORT datab (182:182:182) (215:215:215)) + (PORT datac (620:620:620) (629:629:629)) + (PORT datad (1002:1002:1002) (997:997:997)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|result_lo\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1363:1363:1363) (1384:1384:1384)) + (PORT asdata (620:620:620) (626:626:626)) + (PORT ena (1849:1849:1849) (1797:1797:1797)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\~3) + (DELAY + (ABSOLUTE + (PORT datab (246:246:246) (296:296:296)) + (PORT datac (224:224:224) (285:285:285)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[2\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (657:657:657) (696:696:696)) + (PORT datab (1047:1047:1047) (1033:1033:1033)) + (PORT datac (549:549:549) (560:560:560)) + (PORT datad (620:620:620) (651:651:651)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[2\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (873:873:873) (872:872:872)) + (PORT datab (828:828:828) (827:827:827)) + (PORT datac (155:155:155) (185:185:185)) + (PORT datad (602:602:602) (607:607:607)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_low\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1356:1356:1356) (1366:1366:1366)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (745:745:745) (751:751:751)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[2\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (606:606:606) (610:610:610)) + (PORT datab (403:403:403) (447:447:447)) + (PORT datac (540:540:540) (555:555:555)) + (PORT datad (615:615:615) (614:614:614)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[2\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (219:219:219)) + (PORT datab (242:242:242) (298:298:298)) + (PORT datac (1015:1015:1015) (1022:1022:1022)) + (PORT datad (302:302:302) (303:303:303)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[2\]\~20) + (DELAY + (ABSOLUTE + (PORT datab (1004:1004:1004) (974:974:974)) + (PORT datad (289:289:289) (295:295:295)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[2\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (218:218:218)) + (PORT datab (648:648:648) (671:671:671)) + (PORT datac (635:635:635) (669:669:669)) + (PORT datad (554:554:554) (547:547:547)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[2\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (870:870:870) (902:902:902)) + (PORT datab (608:608:608) (618:618:618)) + (PORT datac (573:573:573) (582:582:582)) + (PORT datad (784:784:784) (788:788:788)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[2\]\~8) + (DELAY + (ABSOLUTE + (PORT datac (806:806:806) (824:824:824)) + (PORT datad (158:158:158) (179:179:179)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_low\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1369:1369:1369) (1376:1376:1376)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (720:720:720) (722:722:722)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op1\[2\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (610:610:610) (632:632:632)) + (PORT datab (1050:1050:1050) (1093:1093:1093)) + (PORT datac (596:596:596) (616:616:616)) + (PORT datad (563:563:563) (587:587:587)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_10\~1) + (DELAY + (ABSOLUTE + (PORT dataa (355:355:355) (368:368:368)) + (PORT datac (169:169:169) (207:207:207)) + (PORT datad (923:923:923) (972:972:972)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_10\~0) + (DELAY + (ABSOLUTE + (PORT dataa (196:196:196) (239:239:239)) + (PORT datab (402:402:402) (446:446:446)) + (PORT datac (539:539:539) (567:567:567)) + (PORT datad (1292:1292:1292) (1262:1262:1262)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (364:364:364) (380:380:380)) + (PORT datab (1267:1267:1267) (1295:1295:1295)) + (PORT datac (162:162:162) (198:198:198)) + (PORT datad (173:173:173) (200:200:200)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|cy_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (190:190:190) (231:231:231)) + (PORT datab (969:969:969) (1030:1030:1030)) + (PORT datac (161:161:161) (196:196:196)) + (PORT datad (585:585:585) (585:585:585)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|SYNTHESIZED_WIRE_10\~0) + (DELAY + (ABSOLUTE + (PORT dataa (444:444:444) (486:486:486)) + (PORT datab (208:208:208) (244:244:244)) + (PORT datac (378:378:378) (427:427:427)) + (PORT datad (1291:1291:1291) (1264:1264:1264)) + (IOPATH dataa combout (267:267:267) (273:273:273)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|cy_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (190:190:190) (232:232:232)) + (PORT datab (208:208:208) (243:243:243)) + (PORT datac (1212:1212:1212) (1228:1228:1228)) + (PORT datad (165:165:165) (191:191:191)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf\~0) + (DELAY + (ABSOLUTE + (PORT dataa (765:765:765) (738:738:738)) + (PORT datab (814:814:814) (791:791:791)) + (PORT datac (185:185:185) (223:223:223)) + (PORT datad (600:600:600) (622:622:622)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (2169:2169:2169) (2181:2181:2181)) + (PORT datab (1604:1604:1604) (1614:1614:1614)) + (PORT datac (823:823:823) (831:831:831)) + (PORT datad (1277:1277:1277) (1249:1249:1249)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (559:559:559) (558:558:558)) + (PORT datab (883:883:883) (901:901:901)) + (PORT datac (174:174:174) (205:205:205)) + (PORT datad (563:563:563) (554:554:554)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf\~1) + (DELAY + (ABSOLUTE + (PORT dataa (184:184:184) (221:221:221)) + (PORT datab (187:187:187) (223:223:223)) + (PORT datad (303:303:303) (310:310:310)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf) + (DELAY + (ABSOLUTE + (PORT clk (1353:1353:1353) (1371:1371:1371)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|flags_hf) + (DELAY + (ABSOLUTE + (PORT dataa (861:861:861) (869:869:869)) + (PORT datab (182:182:182) (215:215:215)) + (PORT datac (1747:1747:1747) (1741:1741:1741)) + (PORT datad (1062:1062:1062) (1041:1041:1041)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (312:312:312)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[4\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (1100:1100:1100) (1127:1127:1127)) + (PORT datab (641:641:641) (681:681:681)) + (PORT datac (325:325:325) (351:351:351)) + (PORT datad (350:350:350) (365:365:365)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[4\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (567:567:567) (555:555:555)) + (PORT datab (1013:1013:1013) (975:975:975)) + (PORT datac (784:784:784) (773:773:773)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[4\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (639:639:639) (663:663:663)) + (PORT datab (319:319:319) (331:331:331)) + (PORT datac (371:371:371) (391:391:391)) + (PORT datad (345:345:345) (348:348:348)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[4\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (580:580:580) (602:602:602)) + (PORT datab (857:857:857) (830:830:830)) + (PORT datac (536:536:536) (545:545:545)) + (PORT datad (617:617:617) (619:619:619)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[4\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (676:676:676) (695:695:695)) + (PORT datab (223:223:223) (284:284:284)) + (PORT datac (159:159:159) (190:190:190)) + (PORT datad (553:553:553) (552:552:552)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[3\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (842:842:842) (827:827:827)) + (PORT datab (1111:1111:1111) (1154:1154:1154)) + (PORT datad (785:785:785) (781:781:781)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[3\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (352:352:352) (362:362:362)) + (PORT datab (1027:1027:1027) (1030:1030:1030)) + (PORT datac (632:632:632) (668:668:668)) + (PORT datad (990:990:990) (955:955:955)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[3\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (809:809:809) (828:828:828)) + (PORT datab (839:839:839) (821:821:821)) + (PORT datad (159:159:159) (179:179:179)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[3\]\~25) + (DELAY + (ABSOLUTE + (PORT datab (646:646:646) (669:669:669)) + (PORT datac (632:632:632) (666:666:666)) + (PORT datad (178:178:178) (199:199:199)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[3\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (619:619:619) (666:666:666)) + (PORT datab (1047:1047:1047) (1033:1033:1033)) + (PORT datac (621:621:621) (651:651:651)) + (PORT datad (717:717:717) (693:693:693)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[3\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1097:1097:1097) (1094:1094:1094)) + (PORT datab (829:829:829) (826:826:826)) + (PORT datac (843:843:843) (838:838:838)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_low\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1356:1356:1356) (1366:1366:1366)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (745:745:745) (751:751:751)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[3\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (878:878:878) (884:884:884)) + (PORT datab (755:755:755) (730:730:730)) + (PORT datac (1071:1071:1071) (1067:1067:1067)) + (PORT datad (579:579:579) (606:606:606)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[3\]\~1) + (DELAY + (ABSOLUTE + (PORT datab (832:832:832) (833:833:833)) + (PORT datad (159:159:159) (181:181:181)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_high\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1356:1356:1356) (1366:1366:1366)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (745:745:745) (751:751:751)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op2\[3\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (644:644:644) (646:646:646)) + (PORT datab (652:652:652) (682:682:682)) + (PORT datac (812:812:812) (789:789:789)) + (PORT datad (608:608:608) (640:640:640)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (312:312:312)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|SYNTHESIZED_WIRE_1) + (DELAY + (ABSOLUTE + (PORT dataa (190:190:190) (229:229:229)) + (PORT datab (187:187:187) (221:221:221)) + (PORT datac (1039:1039:1039) (1031:1031:1031)) + (PORT datad (183:183:183) (208:208:208)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|result\~0) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (359:359:359)) + (PORT datab (370:370:370) (371:371:371)) + (PORT datac (515:515:515) (502:502:502)) + (PORT datad (316:316:316) (319:319:319)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (223:223:223) (272:272:272)) + (PORT datab (571:571:571) (598:598:598)) + (PORT datac (1356:1356:1356) (1388:1388:1388)) + (PORT datad (203:203:203) (231:231:231)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1009:1009:1009) (984:984:984)) + (PORT datab (192:192:192) (230:230:230)) + (PORT datad (1086:1086:1086) (1120:1120:1120)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1012:1012:1012) (984:984:984)) + (PORT datab (1027:1027:1027) (1025:1025:1025)) + (PORT datad (286:286:286) (291:291:291)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (240:240:240) (302:302:302)) + (PORT datab (241:241:241) (299:299:299)) + (PORT datac (1015:1015:1015) (1027:1027:1027)) + (PORT datad (224:224:224) (265:265:265)) + (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -26362,15 +26308,111 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~0) + (INSTANCE z80_\|alu_\|db_high\[3\]\~6) (DELAY (ABSOLUTE - (PORT dataa (649:649:649) (659:659:659)) - (PORT datab (571:571:571) (563:563:563)) - (PORT datac (215:215:215) (282:282:282)) - (PORT datad (166:166:166) (193:193:193)) - (IOPATH dataa combout (265:265:265) (269:269:269)) + (PORT dataa (594:594:594) (613:613:613)) + (PORT datab (321:321:321) (332:332:332)) + (PORT datac (597:597:597) (615:615:615)) + (PORT datad (558:558:558) (566:566:566)) + (IOPATH dataa combout (272:272:272) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (809:809:809) (829:829:829)) + (PORT datab (585:585:585) (597:597:597)) + (PORT datac (319:319:319) (330:330:330)) + (PORT datad (517:517:517) (497:497:497)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_34) + (DELAY + (ABSOLUTE + (PORT dataa (815:815:815) (832:832:832)) + (PORT datab (1002:1002:1002) (972:972:972)) + (PORT datac (491:491:491) (482:482:482)) + (PORT datad (582:582:582) (603:603:603)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_sf) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1116:1116:1116) (1099:1099:1099)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~5) + (DELAY + (ABSOLUTE + (PORT dataa (216:216:216) (259:259:259)) + (PORT datab (220:220:220) (265:265:265)) + (PORT datac (575:575:575) (567:567:567)) + (PORT datad (815:815:815) (827:827:827)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1585:1585:1585) (1613:1613:1613)) + (PORT datab (826:826:826) (835:835:835)) + (PORT datac (969:969:969) (933:933:933)) + (PORT datad (866:866:866) (888:888:888)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_nop3pla68M2T2_3) + (DELAY + (ABSOLUTE + (PORT dataa (2115:2115:2115) (2131:2131:2131)) + (PORT datab (2033:2033:2033) (2123:2123:2123)) + (PORT datac (1982:1982:1982) (2000:2000:2000)) + (PORT datad (661:661:661) (729:729:729)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -26378,13 +26420,173 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~4) + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~6) (DELAY (ABSOLUTE - (PORT dataa (1043:1043:1043) (1037:1037:1037)) - (PORT datab (690:690:690) (692:692:692)) - (PORT datac (837:837:837) (854:854:854)) - (PORT datad (1098:1098:1098) (1095:1095:1095)) + (PORT dataa (1179:1179:1179) (1204:1204:1204)) + (PORT datab (880:880:880) (892:892:892)) + (PORT datac (1868:1868:1868) (1837:1837:1837)) + (PORT datad (1537:1537:1537) (1568:1568:1568)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~8) + (DELAY + (ABSOLUTE + (PORT dataa (812:812:812) (832:832:832)) + (PORT datab (182:182:182) (215:215:215)) + (PORT datac (154:154:154) (184:184:184)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~11) + (DELAY + (ABSOLUTE + (PORT dataa (765:765:765) (743:743:743)) + (PORT datab (993:993:993) (972:972:972)) + (PORT datac (1148:1148:1148) (1156:1156:1156)) + (PORT datad (538:538:538) (543:543:543)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~12) + (DELAY + (ABSOLUTE + (PORT dataa (617:617:617) (651:651:651)) + (PORT datab (614:614:614) (649:649:649)) + (PORT datac (609:609:609) (632:632:632)) + (PORT datad (1086:1086:1086) (1092:1092:1092)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~15) + (DELAY + (ABSOLUTE + (PORT dataa (773:773:773) (785:785:785)) + (PORT datab (683:683:683) (748:748:748)) + (PORT datac (156:156:156) (187:187:187)) + (PORT datad (931:931:931) (907:907:907)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op2\[2\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (648:648:648) (652:652:652)) + (PORT datab (843:843:843) (821:821:821)) + (PORT datac (541:541:541) (557:557:557)) + (PORT datad (613:613:613) (638:638:638)) + (IOPATH dataa combout (299:299:299) (306:306:306)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_1) + (DELAY + (ABSOLUTE + (PORT dataa (189:189:189) (231:231:231)) + (PORT datab (189:189:189) (225:225:225)) + (PORT datac (1041:1041:1041) (1032:1032:1032)) + (PORT datad (584:584:584) (587:587:587)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|result\~0) + (DELAY + (ABSOLUTE + (PORT dataa (195:195:195) (237:237:237)) + (PORT datab (180:180:180) (212:212:212)) + (PORT datac (319:319:319) (333:333:333)) + (PORT datad (586:586:586) (585:585:585)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (308:308:308) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_control_\|DFFE_latch_pf_tmp) + (DELAY + (ABSOLUTE + (PORT clk (1363:1363:1363) (1384:1384:1384)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (2015:2015:2015) (1944:1944:1944)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_parity_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (867:867:867) (863:863:863)) + (PORT datab (362:362:362) (402:402:402)) + (PORT datac (805:805:805) (778:778:778)) + (PORT datad (1004:1004:1004) (1050:1050:1050)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_parity_out\~1) + (DELAY + (ABSOLUTE + (PORT dataa (507:507:507) (504:504:504)) + (PORT datab (498:498:498) (499:499:499)) + (PORT datac (155:155:155) (186:186:186)) + (PORT datad (800:800:800) (782:782:782)) (IOPATH dataa combout (318:318:318) (327:327:327)) (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (220:220:220) (216:216:216)) @@ -26394,13 +26596,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~5) + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~4) (DELAY (ABSOLUTE - (PORT dataa (1337:1337:1337) (1338:1338:1338)) - (PORT datab (620:620:620) (638:638:638)) - (PORT datac (155:155:155) (185:185:185)) - (PORT datad (1307:1307:1307) (1301:1301:1301)) + (PORT dataa (857:857:857) (851:851:851)) + (PORT datab (1340:1340:1340) (1346:1346:1346)) + (PORT datac (686:686:686) (747:747:747)) + (PORT datad (1117:1117:1117) (1131:1131:1131)) (IOPATH dataa combout (318:318:318) (323:323:323)) (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (218:218:218) (215:215:215)) @@ -26408,17 +26610,33 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~5) + (DELAY + (ABSOLUTE + (PORT dataa (922:922:922) (958:958:958)) + (PORT datab (512:512:512) (501:501:501)) + (PORT datac (519:519:519) (507:507:507)) + (PORT datad (158:158:158) (180:180:180)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~6) (DELAY (ABSOLUTE - (PORT dataa (1325:1325:1325) (1320:1320:1320)) - (PORT datab (691:691:691) (692:692:692)) - (PORT datac (1053:1053:1053) (1064:1064:1064)) - (PORT datad (157:157:157) (177:177:177)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) + (PORT dataa (1572:1572:1572) (1556:1556:1556)) + (PORT datab (1412:1412:1412) (1471:1471:1471)) + (PORT datac (685:685:685) (749:749:749)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -26426,31 +26644,16 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~0) + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~1) (DELAY (ABSOLUTE - (PORT dataa (389:389:389) (441:441:441)) - (PORT datab (241:241:241) (316:316:316)) - (PORT datac (206:206:206) (278:278:278)) - (PORT datad (566:566:566) (580:580:580)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~3) - (DELAY - (ABSOLUTE - (PORT dataa (783:783:783) (808:808:808)) - (PORT datab (673:673:673) (721:721:721)) - (PORT datad (370:370:370) (403:403:403)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (312:312:312) (325:325:325)) + (PORT dataa (920:920:920) (955:955:955)) + (PORT datab (1144:1144:1144) (1164:1164:1164)) + (PORT datac (824:824:824) (819:819:819)) + (PORT datad (1305:1305:1305) (1313:1313:1313)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -26460,10 +26663,10 @@ (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~2) (DELAY (ABSOLUTE - (PORT dataa (395:395:395) (458:458:458)) - (PORT datab (357:357:357) (410:410:410)) - (PORT datac (611:611:611) (650:650:650)) - (PORT datad (624:624:624) (668:668:668)) + (PORT dataa (894:894:894) (924:924:924)) + (PORT datab (1138:1138:1138) (1166:1166:1166)) + (PORT datac (1133:1133:1133) (1157:1157:1157)) + (PORT datad (547:547:547) (566:566:566)) (IOPATH dataa combout (309:309:309) (326:326:326)) (IOPATH datab combout (309:309:309) (328:328:328)) (IOPATH datac combout (218:218:218) (215:215:215)) @@ -26476,10 +26679,42 @@ (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~1) (DELAY (ABSOLUTE - (PORT dataa (244:244:244) (329:329:329)) - (PORT datab (559:559:559) (586:586:586)) - (PORT datac (217:217:217) (297:297:297)) - (PORT datad (344:344:344) (382:382:382)) + (PORT dataa (900:900:900) (946:946:946)) + (PORT datab (890:890:890) (931:931:931)) + (PORT datac (220:220:220) (288:288:288)) + (PORT datad (392:392:392) (430:430:430)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~3) + (DELAY + (ABSOLUTE + (PORT dataa (253:253:253) (332:332:332)) + (PORT datab (245:245:245) (315:315:315)) + (PORT datac (218:218:218) (287:287:287)) + (PORT datad (757:757:757) (759:759:759)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~0) + (DELAY + (ABSOLUTE + (PORT dataa (242:242:242) (322:322:322)) + (PORT datab (371:371:371) (423:423:423)) + (PORT datac (219:219:219) (288:288:288)) + (PORT datad (378:378:378) (412:412:412)) (IOPATH dataa combout (309:309:309) (326:326:326)) (IOPATH datab combout (309:309:309) (328:328:328)) (IOPATH datac combout (218:218:218) (215:215:215)) @@ -26492,10 +26727,10 @@ (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~4) (DELAY (ABSOLUTE - (PORT dataa (546:546:546) (536:536:536)) - (PORT datab (840:840:840) (821:821:821)) - (PORT datac (523:523:523) (518:518:518)) - (PORT datad (287:287:287) (291:291:291)) + (PORT dataa (183:183:183) (219:219:219)) + (PORT datab (185:185:185) (218:218:218)) + (PORT datac (563:563:563) (572:572:572)) + (PORT datad (296:296:296) (295:295:295)) (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) @@ -26508,11 +26743,11 @@ (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~5) (DELAY (ABSOLUTE - (PORT dataa (1326:1326:1326) (1322:1322:1322)) - (PORT datab (1427:1427:1427) (1456:1456:1456)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (300:300:300) (312:312:312)) + (PORT dataa (823:823:823) (826:826:826)) + (PORT datab (1070:1070:1070) (1072:1072:1072)) + (PORT datad (1992:1992:1992) (1997:1997:1997)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -26525,7 +26760,7 @@ (ABSOLUTE (PORT clk (1344:1344:1344) (1362:1362:1362)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1399:1399:1399) (1369:1369:1369)) + (PORT clrn (1388:1388:1388) (1361:1361:1361)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -26534,34 +26769,18 @@ (HOLD d (posedge clk) (144:144:144)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1041:1041:1041) (1036:1036:1036)) - (PORT datab (619:619:619) (638:638:638)) - (PORT datac (838:838:838) (856:856:856)) - (PORT datad (1096:1096:1096) (1095:1095:1095)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~2) (DELAY (ABSOLUTE - (PORT dataa (907:907:907) (928:928:928)) - (PORT datab (247:247:247) (318:318:318)) - (PORT datac (1050:1050:1050) (1062:1062:1062)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT dataa (183:183:183) (220:220:220)) + (PORT datab (1082:1082:1082) (1083:1083:1083)) + (PORT datac (382:382:382) (416:416:416)) + (PORT datad (1525:1525:1525) (1512:1512:1512)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -26571,90 +26790,13 @@ (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~3) (DELAY (ABSOLUTE - (PORT dataa (183:183:183) (219:219:219)) - (PORT datab (691:691:691) (692:692:692)) - (PORT datac (1297:1297:1297) (1289:1289:1289)) - (PORT datad (221:221:221) (282:282:282)) - (IOPATH dataa combout (290:290:290) (306:306:306)) + (PORT dataa (183:183:183) (220:220:220)) + (PORT datab (714:714:714) (776:776:776)) + (PORT datac (1053:1053:1053) (1056:1056:1056)) + (PORT datad (1386:1386:1386) (1436:1436:1436)) + (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_control_\|DFFE_latch_pf_tmp) - (DELAY - (ABSOLUTE - (PORT clk (1339:1339:1339) (1361:1361:1361)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1177:1177:1177) (1162:1162:1162)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_1) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (238:238:238)) - (PORT datab (193:193:193) (234:234:234)) - (PORT datac (163:163:163) (198:198:198)) - (PORT datad (166:166:166) (190:190:190)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|result\~0) - (DELAY - (ABSOLUTE - (PORT dataa (507:507:507) (509:509:509)) - (PORT datab (192:192:192) (232:232:232)) - (PORT datac (160:160:160) (193:193:193)) - (PORT datad (158:158:158) (178:178:178)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_parity_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (754:754:754) (727:727:727)) - (PORT datac (305:305:305) (316:316:316)) - (PORT datad (178:178:178) (200:200:200)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_parity_out) - (DELAY - (ABSOLUTE - (PORT dataa (326:326:326) (338:338:338)) - (PORT datab (616:616:616) (622:622:622)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -26664,13 +26806,13 @@ (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~7) (DELAY (ABSOLUTE - (PORT dataa (1041:1041:1041) (1041:1041:1041)) - (PORT datab (1081:1081:1081) (1091:1091:1091)) - (PORT datac (1297:1297:1297) (1292:1292:1292)) - (PORT datad (1098:1098:1098) (1098:1098:1098)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT dataa (1569:1569:1569) (1552:1552:1552)) + (PORT datab (1414:1414:1414) (1473:1473:1473)) + (PORT datac (1924:1924:1924) (1866:1866:1866)) + (PORT datad (1120:1120:1120) (1136:1136:1136)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -26680,13 +26822,13 @@ (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~8) (DELAY (ABSOLUTE - (PORT dataa (868:868:868) (888:888:888)) - (PORT datab (694:694:694) (697:697:697)) - (PORT datac (592:592:592) (608:608:608)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (307:307:307) (306:306:306)) + (PORT dataa (862:862:862) (858:858:858)) + (PORT datab (180:180:180) (212:212:212)) + (PORT datac (685:685:685) (746:746:746)) + (PORT datad (896:896:896) (918:918:918)) + (IOPATH dataa combout (273:273:273) (269:269:269)) (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -26696,12 +26838,28 @@ (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~9) (DELAY (ABSOLUTE - (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (181:181:181) (215:215:215)) - (PORT datac (1280:1280:1280) (1286:1286:1286)) - (PORT datad (157:157:157) (178:178:178)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) + (PORT dataa (184:184:184) (221:221:221)) + (PORT datab (181:181:181) (213:213:213)) + (PORT datac (156:156:156) (187:187:187)) + (PORT datad (161:161:161) (183:183:183)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~0) + (DELAY + (ABSOLUTE + (PORT dataa (799:799:799) (823:823:823)) + (PORT datab (242:242:242) (312:312:312)) + (PORT datac (771:771:771) (770:770:770)) + (PORT datad (554:554:554) (550:550:550)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -26712,13 +26870,13 @@ (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~10) (DELAY (ABSOLUTE - (PORT dataa (190:190:190) (229:229:229)) - (PORT datab (317:317:317) (327:327:327)) - (PORT datac (1118:1118:1118) (1119:1119:1119)) - (PORT datad (622:622:622) (636:636:636)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT dataa (1075:1075:1075) (1068:1068:1068)) + (PORT datab (800:800:800) (800:800:800)) + (PORT datac (991:991:991) (968:968:968)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -26728,7 +26886,7 @@ (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf) (DELAY (ABSOLUTE - (PORT clk (1336:1336:1336) (1353:1353:1353)) + (PORT clk (1344:1344:1344) (1363:1363:1363)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -26742,134 +26900,26 @@ (INSTANCE z80_\|alu_control_\|sel\[1\]\~0) (DELAY (ABSOLUTE - (PORT dataa (839:839:839) (847:847:847)) - (PORT datab (1855:1855:1855) (1877:1877:1877)) - (PORT datac (839:839:839) (893:893:893)) - (PORT datad (786:786:786) (790:790:790)) + (PORT dataa (1140:1140:1140) (1135:1135:1135)) + (PORT datab (1288:1288:1288) (1378:1378:1378)) + (PORT datac (184:184:184) (231:231:231)) + (PORT datad (792:792:792) (797:797:797)) (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11\~2) - (DELAY - (ABSOLUTE - (PORT dataa (378:378:378) (402:402:402)) - (PORT datab (1089:1089:1089) (1066:1066:1066)) - (PORT datac (547:547:547) (540:540:540)) - (PORT datad (310:310:310) (323:323:323)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_12) - (DELAY - (ABSOLUTE - (PORT dataa (765:765:765) (773:773:773)) - (PORT datad (312:312:312) (317:317:317)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11\~0) - (DELAY - (ABSOLUTE - (PORT dataa (204:204:204) (253:253:253)) - (PORT datab (200:200:200) (243:243:243)) - (PORT datac (573:573:573) (573:573:573)) - (PORT datad (195:195:195) (234:234:234)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11\~1) - (DELAY - (ABSOLUTE - (PORT dataa (553:553:553) (539:539:539)) - (PORT datab (631:631:631) (626:626:626)) - (PORT datac (528:528:528) (512:512:512)) - (PORT datad (295:295:295) (288:288:288)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_37\~0) - (DELAY - (ABSOLUTE - (PORT dataa (573:573:573) (593:593:593)) - (PORT datab (599:599:599) (604:604:604)) - (PORT datac (217:217:217) (285:285:285)) - (PORT datad (360:360:360) (362:362:362)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_37\~1) - (DELAY - (ABSOLUTE - (PORT dataa (593:593:593) (614:614:614)) - (PORT datab (183:183:183) (216:216:216)) - (PORT datac (571:571:571) (575:575:575)) - (PORT datad (161:161:161) (183:183:183)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_39) - (DELAY - (ABSOLUTE - (PORT clk (1339:1339:1339) (1356:1356:1356)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1141:1141:1141) (1119:1119:1119)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|alu_control_\|b2v_inst_cond_mux\|out\~0) (DELAY (ABSOLUTE - (PORT dataa (1504:1504:1504) (1518:1518:1518)) - (PORT datab (202:202:202) (237:237:237)) - (PORT datac (163:163:163) (197:197:197)) - (PORT datad (812:812:812) (852:852:852)) + (PORT dataa (250:250:250) (328:328:328)) + (PORT datab (569:569:569) (567:567:567)) + (PORT datac (936:936:936) (928:928:928)) + (PORT datad (980:980:980) (962:962:962)) (IOPATH dataa combout (318:318:318) (323:323:323)) (IOPATH datab combout (273:273:273) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) @@ -26882,13 +26932,13 @@ (INSTANCE z80_\|alu_control_\|b2v_inst_cond_mux\|out\~1) (DELAY (ABSOLUTE - (PORT dataa (614:614:614) (674:674:674)) - (PORT datab (615:615:615) (632:632:632)) - (PORT datac (163:163:163) (198:198:198)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (PORT dataa (845:845:845) (856:856:856)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (935:935:935) (926:926:926)) + (PORT datad (218:218:218) (276:276:276)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -26898,11 +26948,11 @@ (INSTANCE z80_\|alu_control_\|flags_cond_true\~0) (DELAY (ABSOLUTE - (PORT dataa (1678:1678:1678) (1708:1708:1708)) - (PORT datab (1857:1857:1857) (1879:1879:1879)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (325:325:325) (332:332:332)) + (PORT dataa (914:914:914) (933:933:933)) + (PORT datab (700:700:700) (766:766:766)) + (PORT datad (158:158:158) (179:179:179)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -26913,7 +26963,7 @@ (INSTANCE z80_\|alu_control_\|flags_cond_true) (DELAY (ABSOLUTE - (PORT clk (1336:1336:1336) (1352:1352:1352)) + (PORT clk (1345:1345:1345) (1363:1363:1363)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -26924,31 +26974,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~13) + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~20) (DELAY (ABSOLUTE - (PORT dataa (585:585:585) (590:590:590)) - (PORT datab (1645:1645:1645) (1688:1688:1688)) - (PORT datac (1674:1674:1674) (1728:1728:1728)) - (PORT datad (517:517:517) (529:529:529)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~14) - (DELAY - (ABSOLUTE - (PORT dataa (190:190:190) (232:232:232)) - (PORT datab (207:207:207) (252:252:252)) - (PORT datac (530:530:530) (526:526:526)) - (PORT datad (164:164:164) (191:191:191)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (295:295:295) (285:285:285)) + (PORT dataa (1773:1773:1773) (1785:1785:1785)) + (PORT datab (831:831:831) (915:915:915)) + (PORT datac (778:778:778) (787:787:787)) + (PORT datad (855:855:855) (904:904:904)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -26956,106 +26990,42 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~17) + (INSTANCE z80_\|execute_\|ctl_sw_4d\~1) (DELAY (ABSOLUTE - (PORT dataa (827:827:827) (822:822:822)) - (PORT datab (202:202:202) (236:236:236)) - (PORT datac (577:577:577) (585:585:585)) - (PORT datad (1103:1103:1103) (1114:1114:1114)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_82) - (DELAY - (ABSOLUTE - (PORT dataa (594:594:594) (593:593:593)) - (PORT datab (868:868:868) (890:890:890)) - (PORT datad (622:622:622) (629:629:629)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (598:598:598) (634:634:634)) - (PORT datab (490:490:490) (477:477:477)) - (PORT datac (692:692:692) (663:663:663)) - (PORT datad (1026:1026:1026) (1006:1006:1006)) + (PORT dataa (839:839:839) (841:841:841)) + (PORT datab (1450:1450:1450) (1444:1444:1444)) + (PORT datac (544:544:544) (540:540:540)) + (PORT datad (315:315:315) (331:331:331)) (IOPATH dataa combout (318:318:318) (307:307:307)) (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~20) + (INSTANCE z80_\|execute_\|ctl_sw_4d\~6) (DELAY (ABSOLUTE - (PORT dataa (512:512:512) (511:511:511)) - (PORT datab (183:183:183) (216:216:216)) - (PORT datac (538:538:538) (550:550:550)) - (PORT datad (582:582:582) (583:583:583)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (181:181:181) (218:218:218)) - (PORT datab (236:236:236) (281:281:281)) - (PORT datac (558:558:558) (555:555:555)) - (PORT datad (208:208:208) (250:250:250)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (PORT datab (181:181:181) (213:213:213)) + (PORT datac (155:155:155) (185:185:185)) + (PORT datad (163:163:163) (188:188:188)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[1\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[1\]) (DELAY (ABSOLUTE - (PORT clk (1349:1349:1349) (1370:1370:1370)) - (PORT asdata (1730:1730:1730) (1680:1680:1680)) - (PORT ena (744:744:744) (751:751:751)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1370:1370:1370)) - (PORT asdata (1694:1694:1694) (1639:1639:1639)) - (PORT ena (1132:1132:1132) (1112:1112:1112)) + (PORT clk (1340:1340:1340) (1357:1357:1357)) + (PORT asdata (824:824:824) (809:809:809)) + (PORT ena (1107:1107:1107) (1064:1064:1064)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -27066,12 +27036,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~28) + (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~4) (DELAY (ABSOLUTE - (PORT dataa (395:395:395) (415:415:415)) - (PORT datab (350:350:350) (401:401:401)) - (PORT datad (558:558:558) (575:575:575)) + (PORT dataa (826:826:826) (851:851:851)) + (PORT datab (1104:1104:1104) (1093:1093:1093)) + (PORT datad (375:375:375) (392:392:392)) (IOPATH dataa combout (309:309:309) (326:326:326)) (IOPATH datab combout (306:306:306) (324:324:324)) (IOPATH datac combout (312:312:312) (325:325:325)) @@ -27081,76 +27051,58 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[1\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[1\]) (DELAY (ABSOLUTE - (PORT clk (1349:1349:1349) (1370:1370:1370)) - (PORT asdata (1694:1694:1694) (1639:1639:1639)) - (PORT ena (1380:1380:1380) (1365:1365:1365)) + (PORT clk (1340:1340:1340) (1357:1357:1357)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1132:1132:1132) (1111:1111:1111)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1342:1342:1342) (1359:1359:1359)) - (PORT asdata (1963:1963:1963) (1914:1914:1914)) - (PORT ena (1109:1109:1109) (1074:1074:1074)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1343:1343:1343) (1361:1361:1361)) - (PORT asdata (1965:1965:1965) (1916:1916:1916)) - (PORT ena (763:763:763) (771:771:771)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) + (HOLD d (posedge clk) (144:144:144)) (HOLD ena (posedge clk) (144:144:144)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~26) + (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~5) (DELAY (ABSOLUTE - (PORT dataa (402:402:402) (440:440:440)) - (PORT datab (612:612:612) (630:630:630)) - (PORT datad (588:588:588) (609:609:609)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (195:195:195) (262:262:262)) + (PORT datad (569:569:569) (568:568:568)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~27) + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|d1_out) (DELAY (ABSOLUTE - (PORT datab (1303:1303:1303) (1283:1283:1283)) - (PORT datad (541:541:541) (532:532:532)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (312:312:312) (325:325:325)) + (PORT dataa (613:613:613) (644:644:644)) + (PORT datac (174:174:174) (206:206:206)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1521:1521:1521) (1529:1529:1529)) + (PORT datab (181:181:181) (213:213:213)) + (PORT datac (981:981:981) (959:959:959)) + (PORT datad (328:328:328) (339:339:339)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -27160,9 +27112,9 @@ (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[1\]) (DELAY (ABSOLUTE - (PORT clk (1349:1349:1349) (1370:1370:1370)) - (PORT asdata (1730:1730:1730) (1679:1679:1679)) - (PORT ena (1123:1123:1123) (1106:1106:1106)) + (PORT clk (1343:1343:1343) (1360:1360:1360)) + (PORT asdata (1190:1190:1190) (1171:1171:1171)) + (PORT ena (1321:1321:1321) (1324:1324:1324)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -27176,25 +27128,40 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~29) (DELAY (ABSOLUTE - (PORT dataa (602:602:602) (628:628:628)) - (PORT datab (882:882:882) (879:879:879)) - (PORT datac (831:831:831) (826:826:826)) - (PORT datad (564:564:564) (571:571:571)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT dataa (643:643:643) (679:679:679)) + (PORT datab (1286:1286:1286) (1241:1241:1241)) + (PORT datad (791:791:791) (774:774:774)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[1\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[1\]) (DELAY (ABSOLUTE - (PORT clk (1349:1349:1349) (1371:1371:1371)) - (PORT asdata (1498:1498:1498) (1466:1466:1466)) - (PORT ena (746:746:746) (759:759:759)) + (PORT clk (1343:1343:1343) (1360:1360:1360)) + (PORT asdata (894:894:894) (892:892:892)) + (PORT ena (716:716:716) (714:714:714)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1360:1360:1360)) + (PORT asdata (895:895:895) (889:889:889)) + (PORT ena (1177:1177:1177) (1173:1173:1173)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -27205,40 +27172,90 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[1\]\~feeder) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~28) (DELAY (ABSOLUTE - (PORT datad (764:764:764) (753:753:753)) + (PORT dataa (234:234:234) (283:283:283)) + (PORT datab (219:219:219) (286:286:286)) + (PORT datad (592:592:592) (621:621:621)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[1\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[1\]) (DELAY (ABSOLUTE - (PORT clk (1349:1349:1349) (1371:1371:1371)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1154:1154:1154) (1142:1142:1142)) + (PORT clk (1345:1345:1345) (1362:1362:1362)) + (PORT asdata (891:891:891) (891:891:891)) + (PORT ena (1115:1115:1115) (1103:1103:1103)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1362:1362:1362)) + (PORT asdata (893:893:893) (894:894:894)) + (PORT ena (1104:1104:1104) (1087:1087:1087)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) (HOLD ena (posedge clk) (144:144:144)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~25) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~26) (DELAY (ABSOLUTE - (PORT dataa (387:387:387) (429:429:429)) - (PORT datab (537:537:537) (543:543:543)) - (PORT datad (544:544:544) (560:560:560)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) + (PORT dataa (807:807:807) (834:834:834)) + (PORT datab (222:222:222) (291:291:291)) + (PORT datad (623:623:623) (652:652:652)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1344:1344:1344) (1361:1361:1361)) + (PORT asdata (1674:1674:1674) (1652:1652:1652)) + (PORT ena (1175:1175:1175) (1148:1148:1148)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~27) + (DELAY + (ABSOLUTE + (PORT datab (558:558:558) (551:551:551)) + (PORT datad (851:851:851) (855:855:855)) + (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -27249,23 +27266,11 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~30) (DELAY (ABSOLUTE - (PORT dataa (185:185:185) (222:222:222)) - (PORT datab (183:183:183) (216:216:216)) - (PORT datac (154:154:154) (184:184:184)) - (PORT datad (508:508:508) (497:497:497)) + (PORT dataa (553:553:553) (539:539:539)) + (PORT datab (182:182:182) (214:214:214)) + (PORT datad (753:753:753) (717:717:717)) (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1422:1422:1422) (1371:1371:1371)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -27275,14 +27280,14 @@ (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[1\]) (DELAY (ABSOLUTE - (PORT clk (1338:1338:1338) (1356:1356:1356)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1297:1297:1297) (1275:1275:1275)) + (PORT clk (1343:1343:1343) (1361:1361:1361)) + (PORT asdata (938:938:938) (935:935:935)) + (PORT ena (904:904:904) (889:889:889)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) (HOLD ena (posedge clk) (144:144:144)) ) ) @@ -27291,9 +27296,9 @@ (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[1\]) (DELAY (ABSOLUTE - (PORT clk (1338:1338:1338) (1356:1356:1356)) - (PORT asdata (1714:1714:1714) (1658:1658:1658)) - (PORT ena (1588:1588:1588) (1555:1555:1555)) + (PORT clk (1343:1343:1343) (1361:1361:1361)) + (PORT asdata (939:939:939) (937:937:937)) + (PORT ena (735:735:735) (733:733:733)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -27308,10 +27313,10 @@ (DELAY (ABSOLUTE (PORT dataa (221:221:221) (293:293:293)) - (PORT datab (881:881:881) (929:929:929)) - (PORT datad (789:789:789) (804:804:804)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) + (PORT datab (223:223:223) (270:270:270)) + (PORT datad (212:212:212) (244:244:244)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -27319,12 +27324,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[1\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[1\]) (DELAY (ABSOLUTE - (PORT clk (1345:1345:1345) (1362:1362:1362)) - (PORT asdata (654:654:654) (660:660:660)) - (PORT ena (735:735:735) (733:733:733)) + (PORT clk (1351:1351:1351) (1372:1372:1372)) + (PORT asdata (508:508:508) (537:537:537)) + (PORT ena (892:892:892) (882:882:882)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -27335,12 +27340,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[1\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[1\]) (DELAY (ABSOLUTE - (PORT clk (1345:1345:1345) (1362:1362:1362)) - (PORT asdata (654:654:654) (660:660:660)) - (PORT ena (763:763:763) (771:771:771)) + (PORT clk (1351:1351:1351) (1372:1372:1372)) + (PORT asdata (510:510:510) (540:540:540)) + (PORT ena (893:893:893) (883:883:883)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -27354,11 +27359,58 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~23) (DELAY (ABSOLUTE - (PORT dataa (221:221:221) (293:293:293)) - (PORT datab (233:233:233) (286:286:286)) - (PORT datad (213:213:213) (247:247:247)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) + (PORT dataa (381:381:381) (408:408:408)) + (PORT datab (404:404:404) (417:417:417)) + (PORT datad (197:197:197) (254:254:254)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1350:1350:1350) (1371:1371:1371)) + (PORT asdata (884:884:884) (873:873:873)) + (PORT ena (1138:1138:1138) (1126:1126:1126)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1350:1350:1350) (1371:1371:1371)) + (PORT asdata (884:884:884) (873:873:873)) + (PORT ena (1110:1110:1110) (1080:1080:1080)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (644:644:644) (678:678:678)) + (PORT datab (647:647:647) (664:664:664)) + (PORT datad (197:197:197) (253:253:253)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -27369,11 +27421,13 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~31) (DELAY (ABSOLUTE - (PORT dataa (632:632:632) (643:643:643)) - (PORT datab (590:590:590) (599:599:599)) - (PORT datad (158:158:158) (179:179:179)) + (PORT dataa (562:562:562) (559:559:559)) + (PORT datab (579:579:579) (571:571:571)) + (PORT datac (157:157:157) (188:188:188)) + (PORT datad (312:312:312) (313:313:313)) (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -27383,12 +27437,12 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~32) (DELAY (ABSOLUTE - (PORT dataa (1254:1254:1254) (1219:1219:1219)) - (PORT datab (577:577:577) (581:581:581)) - (PORT datac (590:590:590) (615:615:615)) - (PORT datad (288:288:288) (293:293:293)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (336:336:336) (337:337:337)) + (PORT dataa (794:794:794) (795:795:795)) + (PORT datab (806:806:806) (805:805:805)) + (PORT datac (157:157:157) (187:187:187)) + (PORT datad (184:184:184) (207:207:207)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -27399,13 +27453,13 @@ (INSTANCE z80_\|reg_file_\|db_lo_ds\[1\]\~1) (DELAY (ABSOLUTE - (PORT dataa (1376:1376:1376) (1382:1382:1382)) - (PORT datab (1533:1533:1533) (1529:1529:1529)) - (PORT datac (1413:1413:1413) (1363:1363:1363)) - (PORT datad (1079:1079:1079) (1074:1074:1074)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT dataa (772:772:772) (768:768:768)) + (PORT datab (1036:1036:1036) (1039:1039:1039)) + (PORT datac (598:598:598) (606:606:606)) + (PORT datad (609:609:609) (630:630:630)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -27415,12 +27469,12 @@ (INSTANCE z80_\|alu_control_\|db\[1\]\~25) (DELAY (ABSOLUTE - (PORT dataa (908:908:908) (909:909:909)) - (PORT datab (819:819:819) (814:814:814)) - (PORT datac (849:849:849) (861:861:861)) - (PORT datad (819:819:819) (821:821:821)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (319:319:319) (324:324:324)) + (PORT dataa (186:186:186) (224:224:224)) + (PORT datab (654:654:654) (651:651:651)) + (PORT datac (374:374:374) (398:398:398)) + (PORT datad (767:767:767) (755:755:755)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (295:295:295) (300:300:300)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -27431,13 +27485,13 @@ (INSTANCE z80_\|alu_control_\|db\[1\]\~24) (DELAY (ABSOLUTE - (PORT dataa (635:635:635) (640:640:640)) - (PORT datab (1060:1060:1060) (1067:1067:1067)) - (PORT datac (821:821:821) (860:860:860)) - (PORT datad (1088:1088:1088) (1085:1085:1085)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT dataa (813:813:813) (802:802:802)) + (PORT datab (1038:1038:1038) (1012:1012:1012)) + (PORT datac (325:325:325) (349:349:349)) + (PORT datad (1292:1292:1292) (1311:1311:1311)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -27447,1393 +27501,42 @@ (INSTANCE z80_\|alu_control_\|db\[1\]\~26) (DELAY (ABSOLUTE - (PORT dataa (186:186:186) (223:223:223)) - (PORT datab (870:870:870) (873:873:873)) - (PORT datac (599:599:599) (602:602:602)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[1\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1179:1179:1179) (1209:1209:1209)) - (PORT datab (871:871:871) (867:867:867)) - (PORT datac (1329:1329:1329) (1335:1335:1335)) - (PORT datad (855:855:855) (872:872:872)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[1\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (187:187:187) (224:224:224)) - (PORT datab (913:913:913) (921:921:921)) - (PORT datac (838:838:838) (837:837:837)) - (PORT datad (199:199:199) (240:240:240)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1565:1565:1565) (1571:1571:1571)) - (PORT datac (827:827:827) (824:824:824)) - (PORT datad (341:341:341) (342:342:342)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~22) - (DELAY - (ABSOLUTE + (PORT dataa (328:328:328) (341:341:341)) (PORT datab (182:182:182) (215:215:215)) - (PORT datac (856:856:856) (855:855:855)) - (PORT datad (216:216:216) (246:246:246)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1095:1095:1095) (1096:1096:1096)) - (PORT datab (247:247:247) (312:312:312)) - (PORT datac (223:223:223) (279:279:279)) - (PORT datad (233:233:233) (269:269:269)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (398:398:398) (471:471:471)) - (PORT datab (1068:1068:1068) (1086:1086:1086)) - (PORT datac (1069:1069:1069) (1080:1080:1080)) - (PORT datad (615:615:615) (638:638:638)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|result_lo\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1339:1339:1339) (1361:1361:1361)) - (PORT asdata (616:616:616) (621:621:621)) - (PORT ena (1177:1177:1177) (1162:1162:1162)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (585:585:585) (594:594:594)) - (PORT datab (343:343:343) (350:350:350)) - (PORT datad (1055:1055:1055) (1049:1049:1049)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (539:539:539) (539:539:539)) - (PORT datab (201:201:201) (234:234:234)) - (PORT datac (1038:1038:1038) (1019:1019:1019)) - (PORT datad (312:312:312) (313:313:313)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[0\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1170:1170:1170) (1202:1202:1202)) - (PORT datab (855:855:855) (828:828:828)) - (PORT datac (1037:1037:1037) (1036:1036:1036)) - (PORT datad (873:873:873) (892:892:892)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[0\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (219:219:219)) - (PORT datab (896:896:896) (905:905:905)) - (PORT datac (754:754:754) (730:730:730)) - (PORT datad (204:204:204) (245:245:245)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (899:899:899) (897:897:897)) - (PORT datac (1538:1538:1538) (1534:1534:1534)) - (PORT datad (1302:1302:1302) (1274:1274:1274)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (219:219:219)) - (PORT datac (831:831:831) (829:829:829)) - (PORT datad (219:219:219) (253:253:253)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1095:1095:1095) (1095:1095:1095)) - (PORT datab (248:248:248) (314:314:314)) - (PORT datac (225:225:225) (275:275:275)) - (PORT datad (226:226:226) (263:263:263)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (618:618:618) (652:652:652)) - (PORT datab (1068:1068:1068) (1086:1086:1086)) - (PORT datac (566:566:566) (605:605:605)) - (PORT datad (615:615:615) (637:637:637)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|result_lo\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1339:1339:1339) (1361:1361:1361)) - (PORT asdata (1037:1037:1037) (1004:1004:1004)) - (PORT ena (1177:1177:1177) (1162:1162:1162)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (511:511:511) (520:520:520)) - (PORT datab (308:308:308) (328:328:328)) - (PORT datad (1055:1055:1055) (1049:1049:1049)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (630:630:630) (640:640:640)) - (PORT datab (335:335:335) (351:351:351)) - (PORT datac (741:741:741) (727:727:727)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[1\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (551:551:551) (536:536:536)) - (PORT datab (893:893:893) (917:917:917)) - (PORT datac (339:339:339) (363:363:363)) - (PORT datad (797:797:797) (815:815:815)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[1\]\~6) - (DELAY - (ABSOLUTE - (PORT datac (157:157:157) (188:188:188)) - (PORT datad (633:633:633) (656:656:656)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_low\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1350:1350:1350) (1357:1357:1357)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (716:716:716) (714:714:714)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|out\[6\]\~0) - (DELAY - (ABSOLUTE - (PORT datab (240:240:240) (310:310:310)) - (PORT datac (213:213:213) (279:279:279)) - (PORT datad (214:214:214) (271:271:271)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~2) - (DELAY - (ABSOLUTE - (PORT datac (792:792:792) (801:801:801)) - (PORT datad (625:625:625) (638:638:638)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|flags_hf2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (636:636:636) (643:643:643)) - (PORT datab (182:182:182) (214:214:214)) - (PORT datad (569:569:569) (563:563:563)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|flags_hf2) - (DELAY - (ABSOLUTE - (PORT clk (1336:1336:1336) (1353:1353:1353)) - (PORT d (67:67:67) (78:78:78)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[2\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (1092:1092:1092) (1097:1097:1097)) - (PORT datab (632:632:632) (626:626:626)) - (PORT datac (1043:1043:1043) (1070:1070:1070)) - (PORT datad (608:608:608) (650:650:650)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_ds\[2\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1107:1107:1107) (1114:1114:1114)) - (PORT datab (1529:1529:1529) (1523:1523:1523)) - (PORT datac (1336:1336:1336) (1338:1338:1338)) - (PORT datad (781:781:781) (791:791:791)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[2\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (610:610:610) (610:610:610)) - (PORT datab (862:862:862) (866:866:866)) - (PORT datac (572:572:572) (606:606:606)) - (PORT datad (779:779:779) (767:767:767)) + (PORT datac (551:551:551) (546:546:546)) + (PORT datad (197:197:197) (226:226:226)) (IOPATH dataa combout (273:273:273) (269:269:269)) (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[2\]\~27) + (INSTANCE z80_\|bus_control_\|db\[1\]\~10) (DELAY (ABSOLUTE - (PORT dataa (774:774:774) (759:759:759)) - (PORT datab (838:838:838) (834:834:834)) - (PORT datac (386:386:386) (421:421:421)) - (PORT datad (771:771:771) (777:777:777)) + (PORT dataa (533:533:533) (536:536:536)) + (PORT datac (1292:1292:1292) (1282:1282:1282)) + (PORT datad (552:552:552) (540:540:540)) (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (295:295:295) (294:294:294)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[2\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (633:633:633) (636:636:636)) - (PORT datab (870:870:870) (873:873:873)) - (PORT datac (540:540:540) (538:538:538)) - (PORT datad (297:297:297) (297:297:297)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[2\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1180:1180:1180) (1213:1213:1213)) - (PORT datab (895:895:895) (908:908:908)) - (PORT datac (855:855:855) (841:841:841)) - (PORT datad (1429:1429:1429) (1463:1463:1463)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[2\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (583:583:583) (578:578:578)) - (PORT datab (914:914:914) (921:921:921)) - (PORT datac (159:159:159) (191:191:191)) - (PORT datad (198:198:198) (239:239:239)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1562:1562:1562) (1566:1566:1566)) - (PORT datab (845:845:845) (834:834:834)) - (PORT datac (833:833:833) (828:828:828)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1329:1329:1329) (1313:1313:1313)) - (PORT datab (1038:1038:1038) (1037:1037:1037)) - (PORT datac (155:155:155) (185:185:185)) - (PORT datad (214:214:214) (247:247:247)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[2\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (254:254:254)) - (PORT datab (223:223:223) (273:273:273)) - (PORT datac (574:574:574) (576:576:576)) - (PORT datad (785:785:785) (799:799:799)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[2\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (511:511:511) (516:516:516)) - (PORT datab (662:662:662) (684:684:684)) - (PORT datac (547:547:547) (541:541:541)) - (PORT datad (799:799:799) (812:812:812)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_low\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1350:1350:1350) (1357:1357:1357)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (716:716:716) (714:714:714)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[2\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (605:605:605) (637:637:637)) - (PORT datab (1034:1034:1034) (1055:1055:1055)) - (PORT datac (551:551:551) (541:541:541)) - (PORT datad (370:370:370) (411:411:411)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[2\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (238:238:238) (310:310:310)) - (PORT datab (182:182:182) (216:216:216)) - (PORT datac (525:525:525) (514:514:514)) - (PORT datad (842:842:842) (871:871:871)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_low\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1350:1350:1350) (1356:1356:1356)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (745:745:745) (751:751:751)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (428:428:428) (482:482:482)) - (PORT datab (595:595:595) (630:630:630)) - (PORT datac (1025:1025:1025) (1003:1003:1003)) - (PORT datad (618:618:618) (634:634:634)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|result_lo\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1339:1339:1339) (1361:1361:1361)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1177:1177:1177) (1162:1162:1162)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (321:321:321) (330:330:330)) - (PORT datab (554:554:554) (558:558:558)) - (PORT datac (889:889:889) (901:901:901)) - (PORT datad (549:549:549) (571:571:571)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[2\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (250:250:250)) - (PORT datab (606:606:606) (599:599:599)) - (PORT datac (847:847:847) (864:864:864)) - (PORT datad (199:199:199) (239:239:239)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[2\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (239:239:239) (308:308:308)) - (PORT datab (559:559:559) (546:546:546)) - (PORT datac (535:535:535) (527:527:527)) - (PORT datad (833:833:833) (861:861:861)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_high\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1350:1350:1350) (1356:1356:1356)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (745:745:745) (751:751:751)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op2\[2\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (426:426:426) (475:475:475)) - (PORT datab (647:647:647) (660:660:660)) - (PORT datac (802:802:802) (805:805:805)) - (PORT datad (380:380:380) (436:436:436)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_1) - (DELAY - (ABSOLUTE - (PORT dataa (359:359:359) (369:369:369)) - (PORT datab (369:369:369) (374:374:374)) - (PORT datac (161:161:161) (194:194:194)) - (PORT datad (325:325:325) (327:327:327)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|result\~0) - (DELAY - (ABSOLUTE - (PORT dataa (342:342:342) (364:364:364)) - (PORT datab (181:181:181) (213:213:213)) - (PORT datac (163:163:163) (197:197:197)) - (PORT datad (330:330:330) (335:335:335)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (308:308:308) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1092:1092:1092) (1091:1091:1091)) - (PORT datab (243:243:243) (308:308:308)) - (PORT datac (218:218:218) (274:274:274)) - (PORT datad (234:234:234) (271:271:271)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1567:1567:1567) (1566:1566:1566)) - (PORT datac (816:816:816) (808:808:808)) - (PORT datad (814:814:814) (823:823:823)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~12) - (DELAY - (ABSOLUTE - (PORT datab (181:181:181) (213:213:213)) - (PORT datac (848:848:848) (853:853:853)) - (PORT datad (216:216:216) (249:249:249)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (591:591:591) (624:624:624)) - (PORT datab (1065:1065:1065) (1080:1080:1080)) - (PORT datac (386:386:386) (440:440:440)) - (PORT datad (617:617:617) (636:636:636)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (219:219:219)) - (PORT datab (1030:1030:1030) (1049:1049:1049)) - (PORT datac (560:560:560) (551:551:551)) - (PORT datad (584:584:584) (585:585:585)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1166:1166:1166) (1201:1201:1201)) - (PORT datab (217:217:217) (269:269:269)) - (PORT datac (885:885:885) (895:895:895)) - (PORT datad (305:305:305) (313:313:313)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[6\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (1174:1174:1174) (1204:1204:1204)) - (PORT datab (895:895:895) (906:906:906)) - (PORT datac (1476:1476:1476) (1517:1517:1517)) - (PORT datad (802:802:802) (796:796:796)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[6\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (601:601:601) (599:599:599)) - (PORT datab (911:911:911) (924:924:924)) - (PORT datac (295:295:295) (308:308:308)) - (PORT datad (204:204:204) (246:246:246)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|out\[6\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (361:361:361) (410:410:410)) - (PORT datab (239:239:239) (308:308:308)) - (PORT datac (213:213:213) (280:280:280)) - (PORT datad (179:179:179) (201:201:201)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|out\[6\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1091:1091:1091) (1094:1094:1094)) - (PORT datab (609:609:609) (601:601:601)) - (PORT datac (589:589:589) (613:613:613)) - (PORT datad (211:211:211) (277:277:277)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1065:1065:1065) (1068:1068:1068)) - (PORT datab (822:822:822) (846:846:846)) - (PORT datac (599:599:599) (610:610:610)) - (PORT datad (817:817:817) (808:808:808)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~20) - (DELAY - (ABSOLUTE - (PORT datab (856:856:856) (838:838:838)) - (PORT datac (1032:1032:1032) (1039:1039:1039)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (897:897:897) (902:902:902)) - (PORT datab (874:874:874) (880:880:880)) - (PORT datac (154:154:154) (184:184:184)) - (PORT datad (817:817:817) (818:818:818)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (639:639:639) (638:638:638)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (1481:1481:1481) (1435:1435:1435)) - (PORT datad (802:802:802) (786:786:786)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_zero_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (594:594:594) (584:584:584)) - (PORT datab (1154:1154:1154) (1156:1156:1156)) - (PORT datac (1065:1065:1065) (1071:1071:1071)) - (PORT datad (315:315:315) (325:325:325)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\~3) - (DELAY - (ABSOLUTE - (PORT datab (249:249:249) (313:313:313)) - (PORT datad (228:228:228) (264:264:264)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|im1) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1366:1366:1366)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1390:1390:1390) (1361:1361:1361)) - (PORT ena (1156:1156:1156) (1147:1147:1147)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_ff_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1132:1132:1132) (1144:1144:1144)) - (PORT datab (1113:1113:1113) (1145:1145:1145)) - (PORT datac (1126:1126:1126) (1169:1169:1169)) - (PORT datad (248:248:248) (311:311:311)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_ff_oe\~1) - (DELAY - (ABSOLUTE - (PORT dataa (322:322:322) (443:443:443)) - (PORT datab (179:179:179) (212:212:212)) - (PORT datac (1067:1067:1067) (1059:1059:1059)) - (PORT datad (1086:1086:1086) (1100:1100:1100)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[0\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (918:918:918) (940:940:940)) - (PORT datab (1082:1082:1082) (1085:1085:1085)) - (PORT datac (627:627:627) (642:642:642)) - (PORT datad (580:580:580) (596:596:596)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[6\]\~8) - (DELAY - (ABSOLUTE - (PORT datab (806:806:806) (794:794:794)) - (PORT datac (873:873:873) (899:899:899)) - (PORT datad (195:195:195) (224:224:224)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~37) - (DELAY - (ABSOLUTE - (PORT dataa (1182:1182:1182) (1236:1236:1236)) - (PORT datab (1913:1913:1913) (2038:2038:2038)) - (PORT datac (758:758:758) (794:794:794)) - (PORT datad (845:845:845) (866:866:866)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~28) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (1172:1172:1172) (1168:1168:1168)) - (PORT datac (1298:1298:1298) (1286:1286:1286)) - (PORT datad (841:841:841) (874:874:874)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~29) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (218:218:218)) - (PORT datab (220:220:220) (254:254:254)) - (PORT datac (1794:1794:1794) (1850:1850:1850)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~30) - (DELAY - (ABSOLUTE - (PORT dataa (818:818:818) (824:824:824)) - (PORT datab (207:207:207) (249:249:249)) - (PORT datac (578:578:578) (585:585:585)) - (PORT datad (883:883:883) (899:899:899)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~37) - (DELAY - (ABSOLUTE - (PORT dataa (969:969:969) (985:985:985)) - (PORT datab (983:983:983) (994:994:994)) - (PORT datac (972:972:972) (942:942:942)) - (PORT datad (583:583:583) (575:575:575)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~55) - (DELAY - (ABSOLUTE - (PORT dataa (879:879:879) (946:946:946)) - (PORT datab (1050:1050:1050) (1021:1021:1021)) - (PORT datac (862:862:862) (936:936:936)) - (PORT datad (981:981:981) (970:970:970)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~38) - (DELAY - (ABSOLUTE - (PORT dataa (830:830:830) (822:822:822)) - (PORT datab (183:183:183) (217:217:217)) - (PORT datac (502:502:502) (489:489:489)) - (PORT datad (502:502:502) (495:495:495)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~34) - (DELAY - (ABSOLUTE - (PORT dataa (631:631:631) (627:627:627)) - (PORT datab (825:825:825) (839:839:839)) - (PORT datac (1827:1827:1827) (1808:1808:1808)) - (PORT datad (771:771:771) (749:749:749)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~3) - (DELAY - (ABSOLUTE - (PORT datab (770:770:770) (793:793:793)) - (PORT datac (574:574:574) (598:598:598)) - (PORT datad (187:187:187) (216:216:216)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~31) - (DELAY - (ABSOLUTE - (PORT dataa (210:210:210) (253:253:253)) - (PORT datab (214:214:214) (257:257:257)) - (PORT datac (328:328:328) (343:343:343)) - (PORT datad (982:982:982) (974:974:974)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~32) - (DELAY - (ABSOLUTE - (PORT dataa (665:665:665) (711:711:711)) - (PORT datab (1492:1492:1492) (1462:1462:1462)) - (PORT datac (571:571:571) (584:584:584)) - (PORT datad (509:509:509) (507:507:507)) - (IOPATH dataa combout (307:307:307) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~33) - (DELAY - (ABSOLUTE - (PORT datab (517:517:517) (515:515:515)) - (PORT datac (1224:1224:1224) (1208:1208:1208)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~35) - (DELAY - (ABSOLUTE - (PORT dataa (974:974:974) (964:964:964)) - (PORT datab (543:543:543) (527:527:527)) - (PORT datac (728:728:728) (703:703:703)) - (PORT datad (717:717:717) (688:688:688)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|DFFE_mrd_ff1) - (DELAY - (ABSOLUTE - (PORT clk (1357:1357:1357) (1378:1378:1378)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1403:1403:1403) (1374:1374:1374)) - (PORT ena (1189:1189:1189) (1191:1191:1191)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|wait_mrd\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (758:758:758) (781:781:781)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|wait_mrd) - (DELAY - (ABSOLUTE - (PORT clk (1357:1357:1357) (1364:1364:1364)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1409:1409:1409) (1375:1375:1375)) - (PORT ena (1071:1071:1071) (1043:1043:1043)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|DFFE_mrd_ff3) - (DELAY - (ABSOLUTE - (PORT clk (1364:1364:1364) (1371:1371:1371)) - (PORT asdata (1135:1135:1135) (1150:1150:1150)) - (PORT clrn (1403:1403:1403) (1374:1374:1374)) - (PORT ena (1217:1217:1217) (1223:1223:1223)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|nRD_out\~1) - (DELAY - (ABSOLUTE - (PORT dataa (848:848:848) (871:871:871)) - (PORT datad (196:196:196) (253:253:253)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|nextM\~4) (DELAY (ABSOLUTE - (PORT dataa (211:211:211) (254:254:254)) - (PORT datab (653:653:653) (703:703:703)) - (PORT datac (796:796:796) (805:805:805)) - (PORT datad (998:998:998) (1024:1024:1024)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) + (PORT dataa (1151:1151:1151) (1179:1179:1179)) + (PORT datab (630:630:630) (649:649:649)) + (PORT datac (1135:1135:1135) (1167:1167:1167)) + (PORT datad (623:623:623) (638:638:638)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -28844,12 +27547,12 @@ (INSTANCE z80_\|execute_\|ctl_iorw\~12) (DELAY (ABSOLUTE - (PORT dataa (1744:1744:1744) (1744:1744:1744)) - (PORT datab (1365:1365:1365) (1377:1377:1377)) - (PORT datac (1368:1368:1368) (1420:1420:1420)) - (PORT datad (1779:1779:1779) (1810:1810:1810)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) + (PORT dataa (829:829:829) (833:833:833)) + (PORT datab (1232:1232:1232) (1297:1297:1297)) + (PORT datac (831:831:831) (855:855:855)) + (PORT datad (1379:1379:1379) (1430:1430:1430)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -28860,10 +27563,10 @@ (INSTANCE z80_\|execute_\|ctl_iorw\~8) (DELAY (ABSOLUTE - (PORT dataa (1021:1021:1021) (1058:1058:1058)) - (PORT datab (180:180:180) (213:213:213)) - (PORT datac (180:180:180) (214:214:214)) - (PORT datad (631:631:631) (673:673:673)) + (PORT dataa (1155:1155:1155) (1181:1181:1181)) + (PORT datab (596:596:596) (624:624:624)) + (PORT datac (850:850:850) (856:856:856)) + (PORT datad (616:616:616) (637:637:637)) (IOPATH dataa combout (273:273:273) (269:269:269)) (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datac combout (218:218:218) (216:216:216)) @@ -28876,12 +27579,12 @@ (INSTANCE z80_\|execute_\|ctl_iorw\~9) (DELAY (ABSOLUTE - (PORT dataa (812:812:812) (798:798:798)) - (PORT datab (1077:1077:1077) (1094:1094:1094)) - (PORT datac (766:766:766) (763:763:763)) - (PORT datad (743:743:743) (727:727:727)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (295:295:295) (300:300:300)) + (PORT dataa (1564:1564:1564) (1537:1537:1537)) + (PORT datab (1067:1067:1067) (1064:1064:1064)) + (PORT datac (386:386:386) (406:406:406)) + (PORT datad (927:927:927) (901:901:901)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -28892,10 +27595,10 @@ (INSTANCE z80_\|memory_ifc_\|DFFE_iorq_ff1) (DELAY (ABSOLUTE - (PORT clk (1357:1357:1357) (1378:1378:1378)) + (PORT clk (1352:1352:1352) (1373:1373:1373)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1403:1403:1403) (1374:1374:1374)) - (PORT ena (1189:1189:1189) (1191:1191:1191)) + (PORT clrn (1399:1399:1399) (1369:1369:1369)) + (PORT ena (1340:1340:1340) (1313:1313:1313)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -28905,43 +27608,15 @@ (HOLD ena (posedge clk) (144:144:144)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_15\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (201:201:201) (258:258:258)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_15) (DELAY (ABSOLUTE - (PORT clk (1357:1357:1357) (1378:1378:1378)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1403:1403:1403) (1374:1374:1374)) - (PORT ena (1189:1189:1189) (1191:1191:1191)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|wait_iorq) - (DELAY - (ABSOLUTE - (PORT clk (1364:1364:1364) (1371:1371:1371)) - (PORT asdata (525:525:525) (588:588:588)) - (PORT clrn (1403:1403:1403) (1374:1374:1374)) - (PORT ena (1217:1217:1217) (1223:1223:1223)) + (PORT clk (1352:1352:1352) (1373:1373:1373)) + (PORT asdata (677:677:677) (723:723:723)) + (PORT clrn (1399:1399:1399) (1369:1369:1369)) + (PORT ena (1340:1340:1340) (1313:1313:1313)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -28951,15 +27626,43 @@ (HOLD ena (posedge clk) (144:144:144)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|wait_iorq\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (206:206:206) (265:265:265)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|wait_iorq) + (DELAY + (ABSOLUTE + (PORT clk (1359:1359:1359) (1366:1366:1366)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1399:1399:1399) (1369:1369:1369)) + (PORT ena (1312:1312:1312) (1277:1277:1277)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|memory_ifc_\|DFFE_iorq_ff4) (DELAY (ABSOLUTE - (PORT clk (1364:1364:1364) (1371:1371:1371)) - (PORT asdata (511:511:511) (578:578:578)) - (PORT clrn (1403:1403:1403) (1374:1374:1374)) - (PORT ena (1217:1217:1217) (1223:1223:1223)) + (PORT clk (1359:1359:1359) (1366:1366:1366)) + (PORT asdata (511:511:511) (576:576:576)) + (PORT clrn (1399:1399:1399) (1369:1369:1369)) + (PORT ena (1312:1312:1312) (1277:1277:1277)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -28974,93 +27677,29 @@ (INSTANCE z80_\|memory_ifc_\|iorq\~0) (DELAY (ABSOLUTE - (PORT datab (226:226:226) (298:298:298)) - (PORT datad (568:568:568) (588:588:588)) + (PORT datab (227:227:227) (296:296:296)) + (PORT datad (205:205:205) (263:263:263)) (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIORead\~1) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (239:239:239)) - (PORT datab (877:877:877) (922:922:922)) - (PORT datac (350:350:350) (355:355:355)) - (PORT datad (198:198:198) (220:220:220)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIORead\~2) - (DELAY - (ABSOLUTE - (PORT dataa (823:823:823) (813:813:813)) - (PORT datab (193:193:193) (235:235:235)) - (PORT datac (1101:1101:1101) (1087:1087:1087)) - (PORT datad (1018:1018:1018) (1021:1021:1021)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIORead\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1748:1748:1748) (1738:1738:1738)) - (PORT datab (1405:1405:1405) (1431:1431:1431)) - (PORT datac (2026:2026:2026) (2020:2020:2020)) - (PORT datad (190:190:190) (219:219:219)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIORead\~3) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (237:237:237)) - (PORT datab (312:312:312) (331:331:331)) - (PORT datac (535:535:535) (526:526:526)) - (PORT datad (330:330:330) (340:340:340)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|memory_ifc_\|DFFE_m1_ff1) (DELAY (ABSOLUTE - (PORT clk (1362:1362:1362) (1368:1368:1368)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1400:1400:1400) (1371:1371:1371)) - (PORT ena (1671:1671:1671) (1677:1677:1677)) + (PORT clk (1359:1359:1359) (1366:1366:1366)) + (PORT asdata (835:835:835) (835:835:835)) + (PORT clrn (1399:1399:1399) (1369:1369:1369)) + (PORT ena (1312:1312:1312) (1277:1277:1277)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) (HOLD ena (posedge clk) (144:144:144)) ) ) @@ -29069,7 +27708,7 @@ (INSTANCE z80_\|memory_ifc_\|wait_m_ALTERA_SYNTHESIZED1\~0) (DELAY (ABSOLUTE - (PORT datad (545:545:545) (566:566:566)) + (PORT datad (201:201:201) (259:259:259)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -29079,10 +27718,10 @@ (INSTANCE z80_\|memory_ifc_\|wait_m_ALTERA_SYNTHESIZED1) (DELAY (ABSOLUTE - (PORT clk (1364:1364:1364) (1371:1371:1371)) + (PORT clk (1359:1359:1359) (1366:1366:1366)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1403:1403:1403) (1374:1374:1374)) - (PORT ena (1217:1217:1217) (1223:1223:1223)) + (PORT clrn (1399:1399:1399) (1369:1369:1369)) + (PORT ena (1312:1312:1312) (1277:1277:1277)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -29097,10 +27736,10 @@ (INSTANCE z80_\|memory_ifc_\|DFFE_m1_ff3) (DELAY (ABSOLUTE - (PORT clk (1357:1357:1357) (1378:1378:1378)) - (PORT asdata (512:512:512) (579:579:579)) - (PORT clrn (1403:1403:1403) (1374:1374:1374)) - (PORT ena (1189:1189:1189) (1191:1191:1191)) + (PORT clk (1352:1352:1352) (1373:1373:1373)) + (PORT asdata (512:512:512) (580:580:580)) + (PORT clrn (1399:1399:1399) (1369:1369:1369)) + (PORT ena (1340:1340:1340) (1313:1313:1313)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -29115,11 +27754,11 @@ (INSTANCE z80_\|memory_ifc_\|nRD_out\~0) (DELAY (ABSOLUTE - (PORT dataa (1338:1338:1338) (1362:1362:1362)) - (PORT datab (227:227:227) (299:299:299)) - (PORT datad (1375:1375:1375) (1395:1395:1395)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) + (PORT dataa (228:228:228) (303:303:303)) + (PORT datab (638:638:638) (692:692:692)) + (PORT datad (821:821:821) (865:865:865)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -29127,99 +27766,151 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|nRD_out\~2) + (INSTANCE z80_\|execute_\|fIORead\~0) (DELAY (ABSOLUTE - (PORT dataa (312:312:312) (336:336:336)) - (PORT datab (331:331:331) (350:350:350)) - (PORT datac (957:957:957) (925:925:925)) - (PORT datad (165:165:165) (189:189:189)) - (IOPATH dataa combout (329:329:329) (332:332:332)) + (PORT dataa (1181:1181:1181) (1210:1210:1210)) + (PORT datab (2015:2015:2015) (2032:2032:2032)) + (PORT datac (1030:1030:1030) (1020:1020:1020)) + (PORT datad (1995:1995:1995) (2088:2088:2088)) + (IOPATH dataa combout (290:290:290) (306:306:306)) (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Equal2\~1) + (INSTANCE z80_\|execute_\|fIORead\~1) (DELAY (ABSOLUTE - (PORT dataa (1619:1619:1619) (1653:1653:1653)) - (PORT datab (1479:1479:1479) (1531:1531:1531)) - (PORT datac (1107:1107:1107) (1125:1125:1125)) - (IOPATH dataa combout (318:318:318) (327:327:327)) + (PORT dataa (612:612:612) (644:644:644)) + (PORT datab (1470:1470:1470) (1536:1536:1536)) + (PORT datac (1543:1543:1543) (1547:1547:1547)) + (PORT datad (177:177:177) (198:198:198)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIORead\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1570:1570:1570) (1579:1579:1579)) + (PORT datab (207:207:207) (242:242:242)) + (PORT datac (155:155:155) (185:185:185)) + (PORT datad (1071:1071:1071) (1075:1075:1075)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIOWrite\~1) + (DELAY + (ABSOLUTE + (PORT dataa (633:633:633) (678:678:678)) + (PORT datac (908:908:908) (970:970:970)) + (PORT datad (177:177:177) (199:199:199)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIORead\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1115:1115:1115) (1152:1152:1152)) + (PORT datab (597:597:597) (622:622:622)) + (PORT datac (1224:1224:1224) (1219:1219:1219)) + (PORT datad (166:166:166) (190:190:190)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~30) + (DELAY + (ABSOLUTE + (PORT dataa (1070:1070:1070) (1055:1055:1055)) + (PORT datab (1274:1274:1274) (1264:1264:1264)) + (PORT datac (1341:1341:1341) (1354:1354:1354)) + (PORT datad (1217:1217:1217) (1195:1195:1195)) + (IOPATH dataa combout (307:307:307) (280:280:280)) (IOPATH datab combout (308:308:308) (281:281:281)) (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~0) + (INSTANCE z80_\|execute_\|ctl_mRead\~31) (DELAY (ABSOLUTE - (PORT dataa (2204:2204:2204) (2261:2261:2261)) - (PORT datad (935:935:935) (996:996:996)) + (PORT dataa (880:880:880) (896:896:896)) + (PORT datac (553:553:553) (545:545:545)) + (PORT datad (806:806:806) (816:816:816)) (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~5) + (INSTANCE z80_\|execute_\|nextM\~3) (DELAY (ABSOLUTE - (PORT datab (1235:1235:1235) (1290:1290:1290)) - (PORT datac (2660:2660:2660) (2719:2719:2719)) - (PORT datad (2283:2283:2283) (2440:2440:2440)) - (IOPATH datab combout (336:336:336) (337:337:337)) + (PORT dataa (1112:1112:1112) (1108:1108:1108)) + (PORT datab (342:342:342) (366:366:366)) + (PORT datac (1446:1446:1446) (1499:1499:1499)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~6) + (INSTANCE z80_\|execute_\|ctl_mRead\~29) (DELAY (ABSOLUTE - (PORT dataa (354:354:354) (361:361:361)) - (PORT datab (801:801:801) (795:795:795)) - (PORT datac (880:880:880) (918:918:918)) - (PORT datad (988:988:988) (949:949:949)) + (PORT dataa (209:209:209) (249:249:249)) + (PORT datab (1066:1066:1066) (1090:1090:1090)) + (PORT datac (838:838:838) (865:865:865)) + (PORT datad (1169:1169:1169) (1165:1165:1165)) (IOPATH dataa combout (329:329:329) (332:332:332)) (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~2) + (INSTANCE z80_\|execute_\|setM1\~58) (DELAY (ABSOLUTE - (PORT dataa (859:859:859) (914:914:914)) - (PORT datac (1100:1100:1100) (1137:1137:1137)) - (PORT datad (1867:1867:1867) (1908:1908:1908)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1350:1350:1350) (1340:1340:1340)) - (PORT datab (842:842:842) (882:882:882)) - (PORT datac (334:334:334) (340:340:340)) - (PORT datad (176:176:176) (197:197:197)) + (PORT dataa (240:240:240) (313:313:313)) + (PORT datab (253:253:253) (322:322:322)) + (PORT datac (553:553:553) (544:544:544)) + (PORT datad (757:757:757) (747:747:747)) (IOPATH dataa combout (307:307:307) (280:280:280)) (IOPATH datab combout (308:308:308) (281:281:281)) (IOPATH datac combout (218:218:218) (215:215:215)) @@ -29229,14 +27920,272 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~1) + (INSTANCE z80_\|execute_\|setM1\~38) (DELAY (ABSOLUTE - (PORT dataa (627:627:627) (658:658:658)) - (PORT datab (776:776:776) (772:772:772)) - (PORT datac (808:808:808) (793:793:793)) - (PORT datad (160:160:160) (182:182:182)) - (IOPATH dataa combout (318:318:318) (307:307:307)) + (PORT datac (818:818:818) (825:825:825)) + (PORT datad (166:166:166) (189:189:189)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1078:1078:1078) (1076:1076:1076)) + (PORT datab (587:587:587) (607:607:607)) + (PORT datad (584:584:584) (575:575:575)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~39) + (DELAY + (ABSOLUTE + (PORT dataa (1037:1037:1037) (1048:1048:1048)) + (PORT datac (777:777:777) (774:774:774)) + (PORT datad (1831:1831:1831) (1859:1859:1859)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~40) + (DELAY + (ABSOLUTE + (PORT dataa (789:789:789) (813:813:813)) + (PORT datab (848:848:848) (859:859:859)) + (PORT datac (155:155:155) (183:183:183)) + (PORT datad (741:741:741) (766:766:766)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~32) + (DELAY + (ABSOLUTE + (PORT dataa (197:197:197) (242:242:242)) + (PORT datab (869:869:869) (881:881:881)) + (PORT datac (321:321:321) (335:335:335)) + (PORT datad (338:338:338) (339:339:339)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~33) + (DELAY + (ABSOLUTE + (PORT dataa (354:354:354) (361:361:361)) + (PORT datab (651:651:651) (669:669:669)) + (PORT datac (1277:1277:1277) (1246:1246:1246)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|DFFE_mrd_ff1) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1355:1355:1355)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1381:1381:1381) (1353:1353:1353)) + (PORT ena (1346:1346:1346) (1333:1333:1333)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|wait_mrd\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (847:847:847) (876:876:876)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|wait_mrd) + (DELAY + (ABSOLUTE + (PORT clk (1359:1359:1359) (1366:1366:1366)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1399:1399:1399) (1369:1369:1369)) + (PORT ena (1312:1312:1312) (1277:1277:1277)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|DFFE_mrd_ff3) + (DELAY + (ABSOLUTE + (PORT clk (1359:1359:1359) (1366:1366:1366)) + (PORT asdata (519:519:519) (589:589:589)) + (PORT clrn (1399:1399:1399) (1369:1369:1369)) + (PORT ena (1312:1312:1312) (1277:1277:1277)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|nRD_out\~1) + (DELAY + (ABSOLUTE + (PORT datac (209:209:209) (284:284:284)) + (PORT datad (198:198:198) (255:255:255)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|nRD_out\~2) + (DELAY + (ABSOLUTE + (PORT dataa (335:335:335) (356:356:356)) + (PORT datab (328:328:328) (347:347:347)) + (PORT datac (566:566:566) (555:555:555)) + (PORT datad (304:304:304) (310:310:310)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIOWrite\~3) + (DELAY + (ABSOLUTE + (PORT datab (1405:1405:1405) (1487:1487:1487)) + (PORT datac (909:909:909) (971:971:971)) + (PORT datad (609:609:609) (641:641:641)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIOWrite\~4) + (DELAY + (ABSOLUTE + (PORT dataa (967:967:967) (983:983:983)) + (PORT datab (621:621:621) (629:629:629)) + (PORT datac (158:158:158) (189:189:189)) + (PORT datad (980:980:980) (946:946:946)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIOWrite\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1183:1183:1183) (1206:1206:1206)) + (PORT datab (1067:1067:1067) (1094:1094:1094)) + (PORT datac (784:784:784) (805:805:805)) + (PORT datad (1419:1419:1419) (1415:1415:1415)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIOWrite\~5) + (DELAY + (ABSOLUTE + (PORT dataa (925:925:925) (937:937:937)) + (PORT datab (183:183:183) (216:216:216)) + (PORT datac (539:539:539) (550:550:550)) + (PORT datad (165:165:165) (187:187:187)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1391:1391:1391) (1396:1396:1396)) + (PORT datab (830:830:830) (828:828:828)) + (PORT datac (626:626:626) (649:649:649)) + (PORT datad (317:317:317) (336:336:336)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~12) + (DELAY + (ABSOLUTE + (PORT dataa (667:667:667) (705:705:705)) + (PORT datab (584:584:584) (615:615:615)) + (PORT datac (558:558:558) (560:560:560)) + (PORT datad (321:321:321) (335:335:335)) + (IOPATH dataa combout (299:299:299) (304:304:304)) (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -29245,32 +28194,231 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~2) + (INSTANCE z80_\|execute_\|ctl_mWrite\~13) (DELAY (ABSOLUTE - (PORT dataa (1151:1151:1151) (1196:1196:1196)) - (PORT datab (804:804:804) (788:788:788)) - (PORT datac (1202:1202:1202) (1187:1187:1187)) - (PORT datad (579:579:579) (611:611:611)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (295:295:295) (285:285:285)) + (PORT dataa (1108:1108:1108) (1124:1124:1124)) + (PORT datab (545:545:545) (547:547:547)) + (PORT datac (560:560:560) (566:566:566)) + (PORT datad (873:873:873) (891:891:891)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~14) + (DELAY + (ABSOLUTE + (PORT dataa (565:565:565) (587:587:587)) + (PORT datab (600:600:600) (602:602:602)) + (PORT datac (156:156:156) (187:187:187)) + (PORT datad (578:578:578) (593:593:593)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~16) + (DELAY + (ABSOLUTE + (PORT dataa (798:798:798) (806:806:806)) + (PORT datab (786:786:786) (820:820:820)) + (PORT datac (922:922:922) (943:943:943)) + (PORT datad (845:845:845) (868:868:868)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (273:273:273) (275:275:275)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|DFFE_mwr_ff1) + (DELAY + (ABSOLUTE + (PORT clk (1352:1352:1352) (1373:1373:1373)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1399:1399:1399) (1369:1369:1369)) + (PORT ena (1340:1340:1340) (1313:1313:1313)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|wait_mwr\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (200:200:200) (257:257:257)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|wait_mwr) + (DELAY + (ABSOLUTE + (PORT clk (1359:1359:1359) (1366:1366:1366)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1399:1399:1399) (1369:1369:1369)) + (PORT ena (1312:1312:1312) (1277:1277:1277)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|mwr_wr) + (DELAY + (ABSOLUTE + (PORT clk (1359:1359:1359) (1366:1366:1366)) + (PORT asdata (513:513:513) (580:580:580)) + (PORT clrn (1399:1399:1399) (1369:1369:1369)) + (PORT ena (1312:1312:1312) (1277:1277:1277)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|nWR_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (611:611:611) (602:602:602)) + (PORT datab (202:202:202) (236:236:236)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal2\~1) + (DELAY + (ABSOLUTE + (PORT datab (2584:2584:2584) (2643:2643:2643)) + (PORT datac (508:508:508) (506:506:506)) + (PORT datad (564:564:564) (563:563:563)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1182:1182:1182) (1191:1191:1191)) + (PORT datab (1403:1403:1403) (1411:1411:1411)) + (PORT datac (1670:1670:1670) (1672:1672:1672)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~4) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (239:239:239)) + (PORT datab (1095:1095:1095) (1110:1110:1110)) + (PORT datac (1076:1076:1076) (1075:1075:1075)) + (PORT datad (824:824:824) (834:834:834)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1923:1923:1923) (1957:1957:1957)) + (PORT datac (1452:1452:1452) (1537:1537:1537)) + (PORT datad (1389:1389:1389) (1427:1427:1427)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1137:1137:1137) (1161:1161:1161)) + (PORT datab (187:187:187) (221:221:221)) + (PORT datac (1564:1564:1564) (1592:1592:1592)) + (PORT datad (1184:1184:1184) (1218:1218:1218)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~3) (DELAY (ABSOLUTE - (PORT dataa (181:181:181) (218:218:218)) - (PORT datab (1011:1011:1011) (984:984:984)) - (PORT datac (342:342:342) (353:353:353)) - (PORT datad (1653:1653:1653) (1697:1697:1697)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT dataa (325:325:325) (335:335:335)) + (PORT datab (839:839:839) (872:872:872)) + (PORT datac (567:567:567) (558:558:558)) + (PORT datad (1624:1624:1624) (1620:1620:1620)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~8) + (DELAY + (ABSOLUTE + (PORT dataa (893:893:893) (946:946:946)) + (PORT datab (1167:1167:1167) (1161:1161:1161)) + (PORT datac (994:994:994) (972:972:972)) + (PORT datad (1101:1101:1101) (1093:1093:1093)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -29280,74 +28428,28 @@ (INSTANCE z80_\|execute_\|fMWrite\~7) (DELAY (ABSOLUTE - (PORT datab (851:851:851) (867:867:867)) - (PORT datac (798:798:798) (800:800:800)) - (PORT datad (722:722:722) (701:701:701)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT dataa (849:849:849) (872:872:872)) + (PORT datab (974:974:974) (1005:1005:1005)) + (PORT datac (1066:1066:1066) (1085:1085:1085)) + (PORT datad (1043:1043:1043) (1028:1028:1028)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (308:308:308) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~4) + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~16) (DELAY (ABSOLUTE - (PORT dataa (1398:1398:1398) (1438:1438:1438)) - (PORT datab (183:183:183) (216:216:216)) - (PORT datac (1584:1584:1584) (1587:1587:1587)) - (PORT datad (811:811:811) (816:816:816)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1336:1336:1336) (1339:1339:1339)) - (PORT datab (1075:1075:1075) (1065:1065:1065)) - (PORT datac (828:828:828) (827:827:827)) - (PORT datad (722:722:722) (703:703:703)) + (PORT dataa (578:578:578) (608:608:608)) + (PORT datab (1068:1068:1068) (1084:1084:1084)) + (PORT datac (1562:1562:1562) (1585:1585:1585)) + (PORT datad (1900:1900:1900) (1923:1923:1923)) (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1395:1395:1395) (1436:1436:1436)) - (PORT datab (1065:1065:1065) (1092:1092:1092)) - (PORT datac (1018:1018:1018) (1007:1007:1007)) - (PORT datad (562:562:562) (576:576:576)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1156:1156:1156) (1202:1202:1202)) - (PORT datab (797:797:797) (811:811:811)) - (PORT datac (1565:1565:1565) (1576:1576:1576)) - (PORT datad (238:238:238) (287:287:287)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datab combout (267:267:267) (275:275:275)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -29358,13 +28460,29 @@ (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~8) (DELAY (ABSOLUTE - (PORT dataa (1062:1062:1062) (1058:1058:1058)) - (PORT datab (192:192:192) (233:233:233)) - (PORT datac (174:174:174) (205:205:205)) - (PORT datad (576:576:576) (591:591:591)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (PORT dataa (1228:1228:1228) (1261:1261:1261)) + (PORT datab (600:600:600) (609:609:609)) + (PORT datac (1583:1583:1583) (1592:1592:1592)) + (PORT datad (1067:1067:1067) (1084:1084:1084)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~6) + (DELAY + (ABSOLUTE + (PORT dataa (943:943:943) (1020:1020:1020)) + (PORT datab (967:967:967) (1051:1051:1051)) + (PORT datac (641:641:641) (684:684:684)) + (PORT datad (1060:1060:1060) (1039:1039:1039)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -29374,26 +28492,12 @@ (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~9) (DELAY (ABSOLUTE - (PORT dataa (184:184:184) (221:221:221)) - (PORT datab (202:202:202) (237:237:237)) - (PORT datac (977:977:977) (948:948:948)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1014:1014:1014) (988:988:988)) - (PORT datab (798:798:798) (790:790:790)) - (PORT datac (562:562:562) (584:584:584)) - (PORT datad (1108:1108:1108) (1102:1102:1102)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) + (PORT dataa (619:619:619) (607:607:607)) + (PORT datab (858:858:858) (857:857:857)) + (PORT datac (861:861:861) (869:869:869)) + (PORT datad (165:165:165) (190:190:190)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -29401,15 +28505,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~5) + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~7) (DELAY (ABSOLUTE - (PORT dataa (833:833:833) (846:846:846)) - (PORT datab (189:189:189) (222:222:222)) - (PORT datac (543:543:543) (535:535:535)) - (PORT datad (180:180:180) (202:202:202)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) + (PORT dataa (1562:1562:1562) (1554:1554:1554)) + (PORT datab (611:611:611) (597:597:597)) + (PORT datac (1146:1146:1146) (1156:1156:1156)) + (PORT datad (870:870:870) (875:875:875)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (308:308:308) (300:300:300)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -29421,9 +28525,9 @@ (DELAY (ABSOLUTE (PORT dataa (184:184:184) (221:221:221)) - (PORT datab (183:183:183) (216:216:216)) - (PORT datac (310:310:310) (316:316:316)) - (PORT datad (755:755:755) (755:755:755)) + (PORT datab (182:182:182) (215:215:215)) + (PORT datac (156:156:156) (186:186:186)) + (PORT datad (160:160:160) (182:182:182)) (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) @@ -29433,31 +28537,45 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~10) + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~11) (DELAY (ABSOLUTE - (PORT dataa (823:823:823) (811:811:811)) - (PORT datab (959:959:959) (991:991:991)) - (PORT datac (1017:1017:1017) (1007:1007:1007)) - (PORT datad (1035:1035:1035) (1028:1028:1028)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (308:308:308) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT dataa (1043:1043:1043) (1022:1022:1022)) + (PORT datab (564:564:564) (581:581:581)) + (PORT datac (1324:1324:1324) (1301:1301:1301)) + (PORT datad (564:564:564) (582:582:582)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~11) + (INSTANCE z80_\|execute_\|fMWrite\~5) (DELAY (ABSOLUTE - (PORT dataa (185:185:185) (223:223:223)) - (PORT datab (183:183:183) (216:216:216)) - (PORT datac (157:157:157) (188:188:188)) - (PORT datad (166:166:166) (190:190:190)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) + (PORT dataa (1405:1405:1405) (1398:1398:1398)) + (PORT datab (1159:1159:1159) (1175:1175:1175)) + (PORT datac (839:839:839) (853:853:853)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~6) + (DELAY + (ABSOLUTE + (PORT dataa (184:184:184) (221:221:221)) + (PORT datab (190:190:190) (228:228:228)) + (PORT datac (1155:1155:1155) (1169:1169:1169)) + (PORT datad (1822:1822:1822) (1865:1865:1865)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -29468,29 +28586,61 @@ (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~12) (DELAY (ABSOLUTE - (PORT dataa (536:536:536) (538:538:538)) - (PORT datab (1030:1030:1030) (1034:1034:1034)) - (PORT datac (1583:1583:1583) (1587:1587:1587)) - (PORT datad (161:161:161) (182:182:182)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) + (PORT dataa (623:623:623) (648:648:648)) + (PORT datab (586:586:586) (617:617:617)) + (PORT datac (848:848:848) (835:835:835)) + (PORT datad (157:157:157) (177:177:177)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~4) + (DELAY + (ABSOLUTE + (PORT dataa (374:374:374) (382:382:382)) + (PORT datab (1371:1371:1371) (1363:1363:1363)) + (PORT datac (602:602:602) (625:625:625)) + (PORT datad (1392:1392:1392) (1404:1404:1404)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1653:1653:1653) (1675:1675:1675)) + (PORT datab (1096:1096:1096) (1113:1113:1113)) + (PORT datac (560:560:560) (568:568:568)) + (PORT datad (803:803:803) (797:797:797)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~13) (DELAY (ABSOLUTE - (PORT dataa (628:628:628) (650:650:650)) - (PORT datab (181:181:181) (213:213:213)) - (PORT datac (574:574:574) (566:566:566)) - (PORT datad (178:178:178) (199:199:199)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT dataa (181:181:181) (217:217:217)) + (PORT datab (893:893:893) (918:918:918)) + (PORT datac (1148:1148:1148) (1162:1162:1162)) + (PORT datad (1822:1822:1822) (1866:1866:1866)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -29500,23 +28650,51 @@ (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~14) (DELAY (ABSOLUTE - (PORT dataa (181:181:181) (217:217:217)) - (PORT datab (861:861:861) (857:857:857)) - (PORT datac (971:971:971) (1049:1049:1049)) - (PORT datad (1053:1053:1053) (1051:1051:1051)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) + (PORT dataa (558:558:558) (564:564:564)) + (PORT datab (863:863:863) (870:870:870)) + (PORT datac (551:551:551) (554:554:554)) + (PORT datad (551:551:551) (546:546:546)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~2) + (DELAY + (ABSOLUTE + (PORT datab (935:935:935) (964:964:964)) + (PORT datad (873:873:873) (904:904:904)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1255:1255:1255) (1257:1257:1257)) + (PORT datab (316:316:316) (335:335:335)) + (PORT datac (156:156:156) (187:187:187)) + (PORT datad (607:607:607) (640:640:640)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|clk_delay_\|DFF_inst5\~feeder) (DELAY (ABSOLUTE - (PORT datad (203:203:203) (264:264:264)) + (PORT datad (1224:1224:1224) (1226:1226:1226)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -29526,9 +28704,9 @@ (INSTANCE z80_\|clk_delay_\|DFF_inst5) (DELAY (ABSOLUTE - (PORT clk (1349:1349:1349) (1370:1370:1370)) + (PORT clk (1341:1341:1341) (1362:1362:1362)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1408:1408:1408) (1374:1374:1374)) + (PORT clrn (1388:1388:1388) (1358:1358:1358)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -29537,30 +28715,20 @@ (HOLD d (posedge clk) (144:144:144)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|wait_iorqinta\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (208:208:208) (268:268:268)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|memory_ifc_\|wait_iorqinta) (DELAY (ABSOLUTE - (PORT clk (1356:1356:1356) (1363:1363:1363)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1408:1408:1408) (1374:1374:1374)) + (PORT clk (1358:1358:1358) (1365:1365:1365)) + (PORT asdata (1384:1384:1384) (1399:1399:1399)) + (PORT clrn (1398:1398:1398) (1368:1368:1368)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) ) ) (CELL @@ -29568,9 +28736,9 @@ (INSTANCE z80_\|memory_ifc_\|DFFE_intr_ff3) (DELAY (ABSOLUTE - (PORT clk (1349:1349:1349) (1370:1370:1370)) - (PORT asdata (514:514:514) (581:581:581)) - (PORT clrn (1408:1408:1408) (1374:1374:1374)) + (PORT clk (1351:1351:1351) (1372:1372:1372)) + (PORT asdata (512:512:512) (580:580:580)) + (PORT clrn (1398:1398:1398) (1368:1368:1368)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -29584,11 +28752,11 @@ (INSTANCE z80_\|memory_ifc_\|nIORQ_out\~0) (DELAY (ABSOLUTE - (PORT dataa (229:229:229) (305:305:305)) - (PORT datad (572:572:572) (576:576:576)) - (IOPATH dataa combout (318:318:318) (323:323:323)) + (PORT dataa (527:527:527) (516:516:516)) + (PORT datab (228:228:228) (300:300:300)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) @@ -29597,28 +28765,12 @@ (INSTANCE Equal2\~0) (DELAY (ABSOLUTE - (PORT dataa (1620:1620:1620) (1655:1655:1655)) - (PORT datab (1476:1476:1476) (1535:1535:1535)) - (PORT datac (1106:1106:1106) (1124:1124:1124)) - (PORT datad (1131:1131:1131) (1160:1160:1160)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ExtRamWE\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1619:1619:1619) (1653:1653:1653)) - (PORT datab (1479:1479:1479) (1531:1531:1531)) - (PORT datac (1107:1107:1107) (1125:1125:1125)) - (PORT datad (1130:1130:1130) (1159:1159:1159)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) + (PORT dataa (223:223:223) (272:272:272)) + (PORT datab (2585:2585:2585) (2645:2645:2645)) + (PORT datac (508:508:508) (503:503:503)) + (PORT datad (564:564:564) (559:559:559)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -29626,12 +28778,26 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[13\]\~13) + (INSTANCE z80_\|execute_\|ctl_apin_mux\~2) (DELAY (ABSOLUTE - (PORT dataa (1673:1673:1673) (1606:1606:1606)) - (PORT datab (793:793:793) (773:773:773)) - (PORT datad (312:312:312) (319:319:319)) + (PORT dataa (818:818:818) (814:814:814)) + (PORT datac (1378:1378:1378) (1352:1352:1352)) + (PORT datad (786:786:786) (813:813:813)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[10\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1325:1325:1325) (1336:1336:1336)) + (PORT datab (499:499:499) (491:491:491)) + (PORT datad (301:301:301) (302:302:302)) (IOPATH dataa combout (300:300:300) (323:323:323)) (IOPATH datab combout (306:306:306) (324:324:324)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -29643,651 +28809,55 @@ (INSTANCE z80_\|execute_\|ctl_apin_mux2\~0) (DELAY (ABSOLUTE - (PORT dataa (879:879:879) (920:920:920)) - (PORT datab (921:921:921) (968:968:968)) - (PORT datac (1740:1740:1740) (1842:1842:1842)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) + (PORT dataa (1830:1830:1830) (1843:1843:1843)) + (PORT datab (1525:1525:1525) (1570:1570:1570)) + (PORT datac (1347:1347:1347) (1438:1438:1438)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (308:308:308) (281:281:281)) (IOPATH datac combout (218:218:218) (215:215:215)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_ab_pin_we\~2) + (INSTANCE z80_\|pin_control_\|bus_ab_pin_we\~0) (DELAY (ABSOLUTE - (PORT dataa (1557:1557:1557) (1646:1646:1646)) - (PORT datab (908:908:908) (918:918:918)) - (PORT datac (878:878:878) (894:894:894)) - (PORT datad (1117:1117:1117) (1116:1116:1116)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_ab_pin_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (878:878:878) (919:919:919)) - (PORT datab (922:922:922) (968:968:968)) - (PORT datac (1740:1740:1740) (1842:1842:1842)) - (PORT datad (573:573:573) (588:588:588)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[13\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1359:1359:1359)) - (PORT d (67:67:67) (78:78:78)) - (PORT asdata (544:544:544) (617:617:617)) - (PORT sload (1041:1041:1041) (1053:1053:1053)) - (PORT ena (1068:1068:1068) (1021:1021:1021)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD sload (posedge clk) (144:144:144)) - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[13\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (1091:1091:1091) (1116:1116:1116)) - (PORT datad (1866:1866:1866) (1899:1899:1899)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[14\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1672:1672:1672) (1604:1604:1604)) - (PORT datab (199:199:199) (232:232:232)) - (PORT datad (304:304:304) (299:299:299)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[14\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1359:1359:1359)) - (PORT d (67:67:67) (78:78:78)) - (PORT asdata (532:532:532) (598:598:598)) - (PORT sload (1041:1041:1041) (1053:1053:1053)) - (PORT ena (1068:1068:1068) (1021:1021:1021)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD sload (posedge clk) (144:144:144)) - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[14\]\~23) - (DELAY - (ABSOLUTE - (PORT datab (1891:1891:1891) (1933:1933:1933)) - (PORT datad (1054:1054:1054) (1082:1082:1082)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[15\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1672:1672:1672) (1607:1607:1607)) - (PORT datab (319:319:319) (332:332:332)) - (PORT datad (517:517:517) (497:497:497)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[15\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1359:1359:1359)) - (PORT d (67:67:67) (78:78:78)) - (PORT asdata (520:520:520) (588:588:588)) - (PORT sload (1041:1041:1041) (1053:1053:1053)) - (PORT ena (1068:1068:1068) (1021:1021:1021)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD sload (posedge clk) (144:144:144)) - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[15\]\~22) - (DELAY - (ABSOLUTE - (PORT datab (1530:1530:1530) (1544:1544:1544)) - (PORT datac (1457:1457:1457) (1454:1454:1454)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode236w\[2\]) - (DELAY - (ABSOLUTE - (PORT dataa (630:630:630) (659:659:659)) - (PORT datab (230:230:230) (284:284:284)) - (PORT datac (331:331:331) (358:358:358)) - (PORT datad (1200:1200:1200) (1152:1152:1152)) - (IOPATH dataa combout (265:265:265) (269:269:269)) + (PORT dataa (902:902:902) (941:941:941)) + (PORT datab (206:206:206) (243:243:243)) + (PORT datad (1234:1234:1234) (1220:1220:1220)) + (IOPATH dataa combout (267:267:267) (273:273:273)) (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|rden_decode\|w_anode284w\[2\]\~0) + (INSTANCE z80_\|pin_control_\|bus_ab_pin_we\~1) (DELAY (ABSOLUTE - (PORT datab (1881:1881:1881) (1928:1928:1928)) - (PORT datac (1050:1050:1050) (1076:1076:1076)) - (PORT datad (1051:1051:1051) (1083:1083:1083)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[0\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (845:845:845) (880:880:880)) - (PORT datad (1844:1844:1844) (1865:1865:1865)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[1\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (799:799:799) (793:793:793)) - (PORT datab (348:348:348) (356:356:356)) - (PORT datad (316:316:316) (308:308:308)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1370:1370:1370) (1377:1377:1377)) - (PORT d (67:67:67) (78:78:78)) - (PORT asdata (1041:1041:1041) (1043:1043:1043)) - (PORT sload (1115:1115:1115) (1155:1155:1155)) - (PORT ena (1333:1333:1333) (1296:1296:1296)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD sload (posedge clk) (144:144:144)) - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[1\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (1659:1659:1659) (1683:1683:1683)) - (PORT datad (623:623:623) (656:656:656)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[2\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (802:802:802) (794:794:794)) - (PORT datab (560:560:560) (552:552:552)) - (PORT datad (491:491:491) (483:483:483)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1370:1370:1370) (1377:1377:1377)) - (PORT d (67:67:67) (78:78:78)) - (PORT asdata (915:915:915) (930:930:930)) - (PORT sload (1115:1115:1115) (1155:1155:1155)) - (PORT ena (1333:1333:1333) (1296:1296:1296)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD sload (posedge clk) (144:144:144)) - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[2\]\~26) - (DELAY - (ABSOLUTE - (PORT datac (1617:1617:1617) (1642:1642:1642)) - (PORT datad (587:587:587) (619:619:619)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[3\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (805:805:805) (801:801:801)) - (PORT datab (498:498:498) (489:489:489)) - (PORT datad (310:310:310) (319:319:319)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1370:1370:1370) (1377:1377:1377)) - (PORT d (67:67:67) (78:78:78)) - (PORT asdata (688:688:688) (723:723:723)) - (PORT sload (1115:1115:1115) (1155:1155:1155)) - (PORT ena (1333:1333:1333) (1296:1296:1296)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD sload (posedge clk) (144:144:144)) - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[3\]\~27) - (DELAY - (ABSOLUTE - (PORT datac (1622:1622:1622) (1649:1649:1649)) - (PORT datad (336:336:336) (379:379:379)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[4\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (799:799:799) (793:793:793)) - (PORT datab (499:499:499) (494:494:494)) - (PORT datad (310:310:310) (321:321:321)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1370:1370:1370) (1377:1377:1377)) - (PORT d (67:67:67) (78:78:78)) - (PORT asdata (896:896:896) (916:916:916)) - (PORT sload (1115:1115:1115) (1155:1155:1155)) - (PORT ena (1333:1333:1333) (1296:1296:1296)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD sload (posedge clk) (144:144:144)) - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[4\]\~28) - (DELAY - (ABSOLUTE - (PORT datac (1624:1624:1624) (1654:1654:1654)) - (PORT datad (595:595:595) (629:629:629)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[5\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1261:1261:1261) (1230:1230:1230)) - (PORT datab (320:320:320) (332:332:332)) - (PORT datad (179:179:179) (201:201:201)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1359:1359:1359)) - (PORT d (67:67:67) (78:78:78)) - (PORT asdata (922:922:922) (957:957:957)) - (PORT sload (1062:1062:1062) (1091:1091:1091)) - (PORT ena (1086:1086:1086) (1050:1050:1050)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD sload (posedge clk) (144:144:144)) - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[5\]\~29) - (DELAY - (ABSOLUTE - (PORT datab (1883:1883:1883) (1881:1881:1881)) - (PORT datac (621:621:621) (665:665:665)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[6\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (201:201:201) (235:235:235)) - (PORT datad (1236:1236:1236) (1194:1194:1194)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1359:1359:1359)) - (PORT d (67:67:67) (78:78:78)) - (PORT asdata (1061:1061:1061) (1067:1067:1067)) - (PORT sload (1062:1062:1062) (1091:1091:1091)) - (PORT ena (1086:1086:1086) (1050:1050:1050)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD sload (posedge clk) (144:144:144)) - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[6\]\~30) - (DELAY - (ABSOLUTE - (PORT datab (641:641:641) (694:694:694)) - (PORT datac (1617:1617:1617) (1643:1643:1643)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[7\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1264:1264:1264) (1232:1232:1232)) - (PORT datab (183:183:183) (216:216:216)) - (PORT datad (177:177:177) (198:198:198)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1359:1359:1359)) - (PORT d (67:67:67) (78:78:78)) - (PORT asdata (1519:1519:1519) (1486:1486:1486)) - (PORT sload (1062:1062:1062) (1091:1091:1091)) - (PORT ena (1086:1086:1086) (1050:1050:1050)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD sload (posedge clk) (144:144:144)) - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[7\]\~31) - (DELAY - (ABSOLUTE - (PORT datac (1615:1615:1615) (1647:1647:1647)) - (PORT datad (854:854:854) (894:894:894)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[8\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (314:314:314) (339:339:339)) - (PORT datab (1265:1265:1265) (1219:1219:1219)) - (PORT datad (179:179:179) (201:201:201)) + (PORT dataa (996:996:996) (959:959:959)) + (PORT datab (180:180:180) (212:212:212)) + (PORT datac (1375:1375:1375) (1460:1460:1460)) + (PORT datad (816:816:816) (817:817:817)) (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[8\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1359:1359:1359)) - (PORT d (67:67:67) (78:78:78)) - (PORT asdata (536:536:536) (608:608:608)) - (PORT sload (1062:1062:1062) (1091:1091:1091)) - (PORT ena (1086:1086:1086) (1050:1050:1050)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD sload (posedge clk) (144:144:144)) - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[8\]\~18) - (DELAY - (ABSOLUTE - (PORT datab (871:871:871) (913:913:913)) - (PORT datad (1856:1856:1856) (1888:1888:1888)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[9\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1294:1294:1294) (1266:1266:1266)) - (PORT datab (200:200:200) (234:234:234)) - (PORT datad (511:511:511) (504:504:504)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[9\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1358:1358:1358)) - (PORT d (67:67:67) (78:78:78)) - (PORT asdata (529:529:529) (605:605:605)) - (PORT sload (1033:1033:1033) (1049:1049:1049)) - (PORT ena (735:735:735) (733:733:733)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD sload (posedge clk) (144:144:144)) - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[9\]\~17) - (DELAY - (ABSOLUTE - (PORT datac (1624:1624:1624) (1649:1649:1649)) - (PORT datad (626:626:626) (674:674:674)) + (IOPATH datab combout (319:319:319) (307:307:307)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[10\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (238:238:238)) - (PORT datab (532:532:532) (519:519:519)) - (PORT datad (1271:1271:1271) (1229:1229:1229)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[10\]) (DELAY (ABSOLUTE - (PORT clk (1349:1349:1349) (1358:1358:1358)) + (PORT clk (1343:1343:1343) (1354:1354:1354)) (PORT d (67:67:67) (78:78:78)) - (PORT asdata (525:525:525) (601:601:601)) - (PORT sload (1033:1033:1033) (1049:1049:1049)) - (PORT ena (735:735:735) (733:733:733)) + (PORT asdata (525:525:525) (588:588:588)) + (PORT sload (1864:1864:1864) (1899:1899:1899)) + (PORT ena (2103:2103:2103) (2034:2034:2034)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -30298,5778 +28868,6 @@ (HOLD ena (posedge clk) (144:144:144)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[10\]\~24) - (DELAY - (ABSOLUTE - (PORT datac (844:844:844) (879:879:879)) - (PORT datad (1349:1349:1349) (1383:1383:1383)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[11\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (237:237:237)) - (PORT datab (180:180:180) (212:212:212)) - (PORT datad (1268:1268:1268) (1227:1227:1227)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[11\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1358:1358:1358)) - (PORT d (67:67:67) (78:78:78)) - (PORT asdata (842:842:842) (864:864:864)) - (PORT sload (1033:1033:1033) (1049:1049:1049)) - (PORT ena (735:735:735) (733:733:733)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD sload (posedge clk) (144:144:144)) - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[11\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (890:890:890) (913:913:913)) - (PORT datad (1349:1349:1349) (1385:1385:1385)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[12\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (316:316:316) (337:337:337)) - (PORT datab (756:756:756) (741:741:741)) - (PORT datad (1458:1458:1458) (1392:1392:1392)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[12\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1359:1359:1359)) - (PORT d (67:67:67) (78:78:78)) - (PORT asdata (524:524:524) (596:596:596)) - (PORT sload (1041:1041:1041) (1053:1053:1053)) - (PORT ena (1068:1068:1068) (1021:1021:1021)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD sload (posedge clk) (144:144:144)) - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[12\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1657:1657:1657) (1678:1678:1678)) - (PORT datad (796:796:796) (826:826:826)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (942:942:942) (945:945:945)) - (PORT clk (1643:1643:1643) (1670:1670:1670)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (930:930:930) (940:940:940)) - (PORT d[1] (1926:1926:1926) (2072:2072:2072)) - (PORT d[2] (1357:1357:1357) (1362:1362:1362)) - (PORT d[3] (2658:2658:2658) (2763:2763:2763)) - (PORT d[4] (2440:2440:2440) (2546:2546:2546)) - (PORT d[5] (2926:2926:2926) (3031:3031:3031)) - (PORT d[6] (1266:1266:1266) (1301:1301:1301)) - (PORT d[7] (2683:2683:2683) (2727:2727:2727)) - (PORT d[8] (924:924:924) (930:930:930)) - (PORT d[9] (1474:1474:1474) (1500:1500:1500)) - (PORT d[10] (1486:1486:1486) (1519:1519:1519)) - (PORT d[11] (2077:2077:2077) (2152:2152:2152)) - (PORT d[12] (1485:1485:1485) (1526:1526:1526)) - (PORT clk (1640:1640:1640) (1668:1668:1668)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (876:876:876) (848:848:848)) - (PORT clk (1640:1640:1640) (1668:1668:1668)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1643:1643:1643) (1670:1670:1670)) - (PORT d[0] (1323:1323:1323) (1298:1298:1298)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1644:1644:1644) (1671:1671:1671)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1644:1644:1644) (1671:1671:1671)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1644:1644:1644) (1671:1671:1671)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1644:1644:1644) (1671:1671:1671)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1607:1607:1607) (1634:1634:1634)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (878:878:878) (881:881:881)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (879:879:879) (882:882:882)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (879:879:879) (882:882:882)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (879:879:879) (882:882:882)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1680:1680:1680) (1699:1699:1699)) - (PORT asdata (1873:1873:1873) (1892:1892:1892)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1352:1352:1352) (1368:1368:1368)) - (PORT asdata (1325:1325:1325) (1320:1320:1320)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode223w\[2\]) - (DELAY - (ABSOLUTE - (PORT dataa (630:630:630) (658:658:658)) - (PORT datab (231:231:231) (286:286:286)) - (PORT datac (332:332:332) (357:357:357)) - (PORT datad (1201:1201:1201) (1156:1156:1156)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode223w\[2\]\~0) - (DELAY - (ABSOLUTE - (PORT datab (1888:1888:1888) (1933:1933:1933)) - (PORT datac (1051:1051:1051) (1079:1079:1079)) - (PORT datad (1052:1052:1052) (1086:1086:1086)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (923:923:923) (927:927:927)) - (PORT clk (1640:1640:1640) (1668:1668:1668)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (930:930:930) (941:941:941)) - (PORT d[1] (1940:1940:1940) (2085:2085:2085)) - (PORT d[2] (3079:3079:3079) (3130:3130:3130)) - (PORT d[3] (2650:2650:2650) (2742:2742:2742)) - (PORT d[4] (2385:2385:2385) (2480:2480:2480)) - (PORT d[5] (2942:2942:2942) (3050:3050:3050)) - (PORT d[6] (1495:1495:1495) (1516:1516:1516)) - (PORT d[7] (2675:2675:2675) (2709:2709:2709)) - (PORT d[8] (950:950:950) (959:959:959)) - (PORT d[9] (2990:2990:2990) (3064:3064:3064)) - (PORT d[10] (1520:1520:1520) (1559:1559:1559)) - (PORT d[11] (1785:1785:1785) (1857:1857:1857)) - (PORT d[12] (1722:1722:1722) (1759:1759:1759)) - (PORT clk (1637:1637:1637) (1666:1666:1666)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (869:869:869) (834:834:834)) - (PORT clk (1637:1637:1637) (1666:1666:1666)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1640:1640:1640) (1668:1668:1668)) - (PORT d[0] (1538:1538:1538) (1499:1499:1499)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1641:1641:1641) (1669:1669:1669)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1641:1641:1641) (1669:1669:1669)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1641:1641:1641) (1669:1669:1669)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1641:1641:1641) (1669:1669:1669)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1604:1604:1604) (1632:1632:1632)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (875:875:875) (879:879:879)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (876:876:876) (880:880:880)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (876:876:876) (880:880:880)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (876:876:876) (880:880:880)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1352:1352:1352) (1369:1369:1369)) - (PORT asdata (1357:1357:1357) (1368:1368:1368)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1352:1352:1352) (1369:1369:1369)) - (PORT asdata (641:641:641) (686:686:686)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode244w\[2\]) - (DELAY - (ABSOLUTE - (PORT dataa (631:631:631) (658:658:658)) - (PORT datab (234:234:234) (289:289:289)) - (PORT datac (334:334:334) (358:358:358)) - (PORT datad (1201:1201:1201) (1153:1153:1153)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode244w\[2\]\~0) - (DELAY - (ABSOLUTE - (PORT datab (1882:1882:1882) (1925:1925:1925)) - (PORT datac (1050:1050:1050) (1074:1074:1074)) - (PORT datad (1050:1050:1050) (1082:1082:1082)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1107:1107:1107) (1120:1120:1120)) - (PORT clk (1632:1632:1632) (1660:1660:1660)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3685:3685:3685) (3782:3782:3782)) - (PORT d[1] (1575:1575:1575) (1658:1658:1658)) - (PORT d[2] (3077:3077:3077) (3135:3135:3135)) - (PORT d[3] (1984:1984:1984) (2041:2041:2041)) - (PORT d[4] (1991:1991:1991) (2039:2039:2039)) - (PORT d[5] (1534:1534:1534) (1598:1598:1598)) - (PORT d[6] (1634:1634:1634) (1654:1654:1654)) - (PORT d[7] (2839:2839:2839) (2868:2868:2868)) - (PORT d[8] (3080:3080:3080) (3193:3193:3193)) - (PORT d[9] (1627:1627:1627) (1656:1656:1656)) - (PORT d[10] (2978:2978:2978) (3070:3070:3070)) - (PORT d[11] (1943:1943:1943) (1980:1980:1980)) - (PORT d[12] (1645:1645:1645) (1683:1683:1683)) - (PORT clk (1629:1629:1629) (1658:1658:1658)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2067:2067:2067) (2031:2031:2031)) - (PORT clk (1629:1629:1629) (1658:1658:1658)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1632:1632:1632) (1660:1660:1660)) - (PORT d[0] (2694:2694:2694) (2699:2699:2699)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1633:1633:1633) (1661:1661:1661)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1633:1633:1633) (1661:1661:1661)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1633:1633:1633) (1661:1661:1661)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1633:1633:1633) (1661:1661:1661)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1596:1596:1596) (1624:1624:1624)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (867:867:867) (871:871:871)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (868:868:868) (872:872:872)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (868:868:868) (872:872:872)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (868:868:868) (872:872:872)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~90) - (DELAY - (ABSOLUTE - (PORT dataa (565:565:565) (548:548:548)) - (PORT datab (896:896:896) (943:943:943)) - (PORT datac (772:772:772) (757:757:757)) - (PORT datad (1051:1051:1051) (1082:1082:1082)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode252w\[2\]) - (DELAY - (ABSOLUTE - (PORT dataa (630:630:630) (663:663:663)) - (PORT datab (233:233:233) (288:288:288)) - (PORT datac (334:334:334) (361:361:361)) - (PORT datad (1200:1200:1200) (1155:1155:1155)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode252w\[2\]\~0) - (DELAY - (ABSOLUTE - (PORT datab (1891:1891:1891) (1933:1933:1933)) - (PORT datac (1053:1053:1053) (1077:1077:1077)) - (PORT datad (1055:1055:1055) (1083:1083:1083)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1113:1113:1113) (1106:1106:1106)) - (PORT clk (1640:1640:1640) (1668:1668:1668)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3904:3904:3904) (3985:3985:3985)) - (PORT d[1] (2171:2171:2171) (2294:2294:2294)) - (PORT d[2] (2971:2971:2971) (2995:2995:2995)) - (PORT d[3] (2388:2388:2388) (2476:2476:2476)) - (PORT d[4] (2373:2373:2373) (2471:2471:2471)) - (PORT d[5] (2627:2627:2627) (2712:2712:2712)) - (PORT d[6] (1769:1769:1769) (1832:1832:1832)) - (PORT d[7] (2401:2401:2401) (2428:2428:2428)) - (PORT d[8] (3102:3102:3102) (3241:3241:3241)) - (PORT d[9] (2698:2698:2698) (2767:2767:2767)) - (PORT d[10] (4706:4706:4706) (4798:4798:4798)) - (PORT d[11] (1774:1774:1774) (1826:1826:1826)) - (PORT d[12] (1997:1997:1997) (2046:2046:2046)) - (PORT clk (1637:1637:1637) (1666:1666:1666)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1851:1851:1851) (1777:1777:1777)) - (PORT clk (1637:1637:1637) (1666:1666:1666)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1640:1640:1640) (1668:1668:1668)) - (PORT d[0] (2025:2025:2025) (1959:1959:1959)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1641:1641:1641) (1669:1669:1669)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1641:1641:1641) (1669:1669:1669)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1641:1641:1641) (1669:1669:1669)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1641:1641:1641) (1669:1669:1669)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1604:1604:1604) (1632:1632:1632)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (875:875:875) (879:879:879)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (876:876:876) (880:880:880)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (876:876:876) (880:880:880)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (876:876:876) (880:880:880)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~91) - (DELAY - (ABSOLUTE - (PORT dataa (782:782:782) (763:763:763)) - (PORT datab (1311:1311:1311) (1347:1347:1347)) - (PORT datac (296:296:296) (303:303:303)) - (PORT datad (1025:1025:1025) (1001:1001:1001)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|decode2\|eq_node\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (631:631:631) (658:658:658)) - (PORT datab (228:228:228) (282:282:282)) - (PORT datac (330:330:330) (356:356:356)) - (PORT datad (1201:1201:1201) (1152:1152:1152)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_clkctrl") - (INSTANCE CLOCK_50\~inputclkctrl) - (DELAY - (ABSOLUTE - (PORT inclk[0] (133:133:133) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vram_address\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (977:977:977) (979:979:979)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vram_address\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1154:1154:1154) (1185:1185:1185)) - (PORT datab (896:896:896) (950:950:950)) - (PORT datac (885:885:885) (936:936:936)) - (PORT datad (252:252:252) (321:321:321)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1360:1360:1360) (1375:1375:1375)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1111:1111:1111) (1090:1090:1090)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1360:1360:1360) (1375:1375:1375)) - (PORT asdata (1110:1110:1110) (1132:1132:1132)) - (PORT ena (1111:1111:1111) (1090:1090:1090)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vram_address\[2\]\~4) - (DELAY - (ABSOLUTE - (PORT datac (833:833:833) (864:864:864)) - (IOPATH datac combout (218:218:218) (215:215:215)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1360:1360:1360) (1375:1375:1375)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1111:1111:1111) (1090:1090:1090)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add3\~0) - (DELAY - (ABSOLUTE - (PORT datac (829:829:829) (860:860:860)) - (PORT datad (1338:1338:1338) (1335:1335:1335)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1360:1360:1360) (1375:1375:1375)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1111:1111:1111) (1090:1090:1090)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add3\~1) - (DELAY - (ABSOLUTE - (PORT dataa (866:866:866) (895:895:895)) - (PORT datac (1295:1295:1295) (1303:1303:1303)) - (PORT datad (1339:1339:1339) (1335:1335:1335)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1360:1360:1360) (1375:1375:1375)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1111:1111:1111) (1090:1090:1090)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (650:650:650) (694:694:694)) - (PORT datab (663:663:663) (715:715:715)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH dataa cout (376:376:376) (275:275:275)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datab cout (385:385:385) (280:280:280)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~2) - (DELAY - (ABSOLUTE - (PORT datab (607:607:607) (640:640:640)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datab cout (385:385:385) (280:280:280)) - (IOPATH datad combout (119:119:119) (106:106:106)) - (IOPATH cin combout (408:408:408) (387:387:387)) - (IOPATH cin cout (50:50:50) (50:50:50)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~4) - (DELAY - (ABSOLUTE - (PORT datab (659:659:659) (688:688:688)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datab cout (385:385:385) (280:280:280)) - (IOPATH datad combout (119:119:119) (106:106:106)) - (IOPATH cin combout (408:408:408) (387:387:387)) - (IOPATH cin cout (50:50:50) (50:50:50)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~6) - (DELAY - (ABSOLUTE - (PORT datab (634:634:634) (682:682:682)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datab cout (385:385:385) (280:280:280)) - (IOPATH datad combout (119:119:119) (106:106:106)) - (IOPATH cin combout (408:408:408) (387:387:387)) - (IOPATH cin cout (50:50:50) (50:50:50)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1360:1360:1360) (1375:1375:1375)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1111:1111:1111) (1090:1090:1090)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~8) - (DELAY - (ABSOLUTE - (PORT dataa (654:654:654) (702:702:702)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH dataa cout (376:376:376) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - (IOPATH cin combout (408:408:408) (387:387:387)) - (IOPATH cin cout (50:50:50) (50:50:50)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1360:1360:1360) (1375:1375:1375)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1111:1111:1111) (1090:1090:1090)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~10) - (DELAY - (ABSOLUTE - (PORT dataa (907:907:907) (921:921:921)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH dataa cout (376:376:376) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - (IOPATH cin combout (408:408:408) (387:387:387)) - (IOPATH cin cout (50:50:50) (50:50:50)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1360:1360:1360) (1375:1375:1375)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1111:1111:1111) (1090:1090:1090)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~12) - (DELAY - (ABSOLUTE - (PORT datab (645:645:645) (681:681:681)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datab cout (385:385:385) (280:280:280)) - (IOPATH datad combout (119:119:119) (106:106:106)) - (IOPATH cin combout (408:408:408) (387:387:387)) - (IOPATH cin cout (50:50:50) (50:50:50)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Selector6\~0) - (DELAY - (ABSOLUTE - (PORT datab (559:559:559) (581:581:581)) - (PORT datac (526:526:526) (531:531:531)) - (PORT datad (889:889:889) (923:923:923)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vram_address\[9\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1154:1154:1154) (1188:1188:1188)) - (PORT datab (895:895:895) (951:951:951)) - (PORT datac (889:889:889) (941:941:941)) - (PORT datad (257:257:257) (326:326:326)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[8\]) - (DELAY - (ABSOLUTE - (PORT clk (1359:1359:1359) (1375:1375:1375)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (745:745:745) (752:752:752)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~14) - (DELAY - (ABSOLUTE - (PORT datad (652:652:652) (694:694:694)) - (IOPATH datad combout (119:119:119) (106:106:106)) - (IOPATH cin combout (408:408:408) (387:387:387)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Selector5\~0) - (DELAY - (ABSOLUTE - (PORT dataa (604:604:604) (612:612:612)) - (PORT datac (736:736:736) (733:733:733)) - (PORT datad (889:889:889) (927:927:927)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[9\]) - (DELAY - (ABSOLUTE - (PORT clk (1359:1359:1359) (1375:1375:1375)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (745:745:745) (752:752:752)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vram_address\[10\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1152:1152:1152) (1182:1182:1182)) - (PORT datab (891:891:891) (944:944:944)) - (PORT datac (893:893:893) (945:945:945)) - (PORT datad (261:261:261) (330:330:330)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vram_address\[10\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (574:574:574) (583:583:583)) - (PORT datab (925:925:925) (976:976:976)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[10\]) - (DELAY - (ABSOLUTE - (PORT clk (1359:1359:1359) (1375:1375:1375)) - (PORT d (67:67:67) (78:78:78)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Selector3\~0) - (DELAY - (ABSOLUTE - (PORT datab (562:562:562) (582:582:582)) - (PORT datad (890:890:890) (925:925:925)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[11\]) - (DELAY - (ABSOLUTE - (PORT clk (1359:1359:1359) (1375:1375:1375)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (745:745:745) (752:752:752)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Selector2\~0) - (DELAY - (ABSOLUTE - (PORT datac (566:566:566) (578:578:578)) - (PORT datad (889:889:889) (923:923:923)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[12\]) - (DELAY - (ABSOLUTE - (PORT clk (1359:1359:1359) (1375:1375:1375)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (745:745:745) (752:752:752)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1438:1438:1438) (1457:1457:1457)) - (PORT clk (1649:1649:1649) (1677:1677:1677)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2413:2413:2413) (2427:2427:2427)) - (PORT d[1] (2186:2186:2186) (2314:2314:2314)) - (PORT d[2] (2143:2143:2143) (2219:2219:2219)) - (PORT d[3] (1833:1833:1833) (1876:1876:1876)) - (PORT d[4] (2724:2724:2724) (2866:2866:2866)) - (PORT d[5] (1945:1945:1945) (2062:2062:2062)) - (PORT d[6] (1446:1446:1446) (1485:1485:1485)) - (PORT d[7] (1502:1502:1502) (1535:1535:1535)) - (PORT d[8] (2576:2576:2576) (2689:2689:2689)) - (PORT d[9] (1919:1919:1919) (1944:1944:1944)) - (PORT d[10] (1964:1964:1964) (1995:1995:1995)) - (PORT d[11] (2954:2954:2954) (3003:3003:3003)) - (PORT d[12] (2038:2038:2038) (2059:2059:2059)) - (PORT clk (1646:1646:1646) (1675:1675:1675)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2558:2558:2558) (2482:2482:2482)) - (PORT clk (1646:1646:1646) (1675:1675:1675)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1649:1649:1649) (1677:1677:1677)) - (PORT d[0] (2573:2573:2573) (2575:2575:2575)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1650:1650:1650) (1678:1678:1678)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1650:1650:1650) (1678:1678:1678)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1650:1650:1650) (1678:1678:1678)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1650:1650:1650) (1678:1678:1678)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1608:1608:1608) (1607:1607:1607)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1996:1996:1996) (1985:1985:1985)) - (PORT clk (1616:1616:1616) (1614:1614:1614)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4310:4310:4310) (4203:4203:4203)) - (PORT d[1] (4109:4109:4109) (3957:3957:3957)) - (PORT d[2] (4248:4248:4248) (4146:4146:4146)) - (PORT d[3] (4389:4389:4389) (4241:4241:4241)) - (PORT d[4] (3981:3981:3981) (3826:3826:3826)) - (PORT d[5] (4115:4115:4115) (3954:3954:3954)) - (PORT d[6] (4311:4311:4311) (4251:4251:4251)) - (PORT d[7] (4106:4106:4106) (3931:3931:3931)) - (PORT d[8] (4394:4394:4394) (4226:4226:4226)) - (PORT d[9] (4253:4253:4253) (4312:4312:4312)) - (PORT d[10] (4136:4136:4136) (4024:4024:4024)) - (PORT d[11] (4334:4334:4334) (4189:4189:4189)) - (PORT d[12] (4138:4138:4138) (4057:4057:4057)) - (PORT clk (1613:1613:1613) (1611:1611:1611)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1616:1616:1616) (1614:1614:1614)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1617:1617:1617) (1615:1615:1615)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1617:1617:1617) (1615:1615:1615)) - (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1617:1617:1617) (1615:1615:1615)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1617:1617:1617) (1615:1615:1615)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1609:1609:1609) (1608:1608:1608)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|address_reg_a\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1113:1113:1113) (1158:1158:1158)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|address_reg_a\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1706:1706:1706) (1725:1725:1725)) - (PORT d (67:67:67) (78:78:78)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1352:1352:1352) (1369:1369:1369)) - (PORT asdata (1584:1584:1584) (1576:1576:1576)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|decode2\|eq_node\[1\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (630:630:630) (658:658:658)) - (PORT datab (231:231:231) (285:285:285)) - (PORT datac (331:331:331) (357:357:357)) - (PORT datad (1200:1200:1200) (1156:1156:1156)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1404:1404:1404) (1421:1421:1421)) - (PORT clk (1643:1643:1643) (1670:1670:1670)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2693:2693:2693) (2714:2714:2714)) - (PORT d[1] (2208:2208:2208) (2339:2339:2339)) - (PORT d[2] (1126:1126:1126) (1144:1144:1144)) - (PORT d[3] (1855:1855:1855) (1908:1908:1908)) - (PORT d[4] (2708:2708:2708) (2836:2836:2836)) - (PORT d[5] (2235:2235:2235) (2355:2355:2355)) - (PORT d[6] (1416:1416:1416) (1429:1429:1429)) - (PORT d[7] (1186:1186:1186) (1211:1211:1211)) - (PORT d[8] (1580:1580:1580) (1586:1586:1586)) - (PORT d[9] (1446:1446:1446) (1451:1451:1451)) - (PORT d[10] (2003:2003:2003) (2052:2052:2052)) - (PORT d[11] (2973:2973:2973) (3030:3030:3030)) - (PORT d[12] (1779:1779:1779) (1812:1812:1812)) - (PORT clk (1640:1640:1640) (1668:1668:1668)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2500:2500:2500) (2409:2409:2409)) - (PORT clk (1640:1640:1640) (1668:1668:1668)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1643:1643:1643) (1670:1670:1670)) - (PORT d[0] (2817:2817:2817) (2815:2815:2815)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1644:1644:1644) (1671:1671:1671)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1644:1644:1644) (1671:1671:1671)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1644:1644:1644) (1671:1671:1671)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1644:1644:1644) (1671:1671:1671)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1602:1602:1602) (1600:1600:1600)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2015:2015:2015) (2003:2003:2003)) - (PORT clk (1610:1610:1610) (1607:1607:1607)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4298:4298:4298) (4182:4182:4182)) - (PORT d[1] (3895:3895:3895) (3763:3763:3763)) - (PORT d[2] (3977:3977:3977) (3887:3887:3887)) - (PORT d[3] (4174:4174:4174) (4075:4075:4075)) - (PORT d[4] (4037:4037:4037) (3903:3903:3903)) - (PORT d[5] (4054:4054:4054) (3954:3954:3954)) - (PORT d[6] (4151:4151:4151) (4124:4124:4124)) - (PORT d[7] (3882:3882:3882) (3713:3713:3713)) - (PORT d[8] (4101:4101:4101) (3936:3936:3936)) - (PORT d[9] (4231:4231:4231) (4282:4282:4282)) - (PORT d[10] (4119:4119:4119) (4022:4022:4022)) - (PORT d[11] (4215:4215:4215) (4129:4129:4129)) - (PORT d[12] (4134:4134:4134) (4050:4050:4050)) - (PORT clk (1607:1607:1607) (1604:1604:1604)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1610:1610:1610) (1607:1607:1607)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1611:1611:1611) (1608:1608:1608)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1611:1611:1611) (1608:1608:1608)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1611:1611:1611) (1608:1608:1608)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1611:1611:1611) (1608:1608:1608)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2355:2355:2355) (2346:2346:2346)) - (PORT d[1] (2066:2066:2066) (2149:2149:2149)) - (PORT d[2] (2142:2142:2142) (2225:2225:2225)) - (PORT d[3] (2023:2023:2023) (2092:2092:2092)) - (PORT d[4] (2698:2698:2698) (2836:2836:2836)) - (PORT d[5] (2125:2125:2125) (2238:2238:2238)) - (PORT d[6] (1723:1723:1723) (1771:1771:1771)) - (PORT d[7] (2056:2056:2056) (2040:2040:2040)) - (PORT d[8] (2548:2548:2548) (2649:2649:2649)) - (PORT d[9] (1614:1614:1614) (1648:1648:1648)) - (PORT d[10] (1630:1630:1630) (1624:1624:1624)) - (PORT d[11] (2891:2891:2891) (2914:2914:2914)) - (PORT d[12] (1192:1192:1192) (1217:1217:1217)) - (PORT clk (1654:1654:1654) (1681:1681:1681)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1654:1654:1654) (1681:1681:1681)) - (PORT d[0] (2020:2020:2020) (2024:2024:2024)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1655:1655:1655) (1682:1682:1682)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1621:1621:1621) (1647:1647:1647)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (892:892:892) (894:894:894)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (893:893:893) (895:895:895)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (893:893:893) (895:895:895)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (893:893:893) (895:895:895)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~87) - (DELAY - (ABSOLUTE - (PORT dataa (1255:1255:1255) (1240:1240:1240)) - (PORT datab (248:248:248) (325:325:325)) - (PORT datac (1284:1284:1284) (1276:1276:1276)) - (PORT datad (1538:1538:1538) (1507:1507:1507)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3394:3394:3394) (3476:3476:3476)) - (PORT d[1] (2412:2412:2412) (2539:2539:2539)) - (PORT d[2] (2265:2265:2265) (2288:2288:2288)) - (PORT d[3] (1992:1992:1992) (2060:2060:2060)) - (PORT d[4] (2069:2069:2069) (2140:2140:2140)) - (PORT d[5] (1928:1928:1928) (2016:2016:2016)) - (PORT d[6] (1784:1784:1784) (1847:1847:1847)) - (PORT d[7] (1844:1844:1844) (1862:1862:1862)) - (PORT d[8] (2787:2787:2787) (2891:2891:2891)) - (PORT d[9] (2420:2420:2420) (2486:2486:2486)) - (PORT d[10] (4385:4385:4385) (4449:4449:4449)) - (PORT d[11] (1943:1943:1943) (1988:1988:1988)) - (PORT d[12] (2255:2255:2255) (2302:2302:2302)) - (PORT clk (1643:1643:1643) (1672:1672:1672)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1643:1643:1643) (1672:1672:1672)) - (PORT d[0] (2836:2836:2836) (2867:2867:2867)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1644:1644:1644) (1673:1673:1673)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1610:1610:1610) (1638:1638:1638)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (881:881:881) (885:885:885)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (886:886:886)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (886:886:886)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (886:886:886)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~88) - (DELAY - (ABSOLUTE - (PORT dataa (1191:1191:1191) (1152:1152:1152)) - (PORT datab (1080:1080:1080) (1050:1050:1050)) - (PORT datac (1488:1488:1488) (1466:1466:1466)) - (PORT datad (163:163:163) (188:188:188)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~89) - (DELAY - (ABSOLUTE - (PORT dataa (1324:1324:1324) (1337:1337:1337)) - (PORT datab (190:190:190) (225:225:225)) - (PORT datac (580:580:580) (608:608:608)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (308:308:308) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~111) - (DELAY - (ABSOLUTE - (PORT dataa (598:598:598) (604:604:604)) - (PORT datab (1866:1866:1866) (1894:1894:1894)) - (PORT datac (848:848:848) (891:891:891)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_io_ibuf") - (INSTANCE raw_loader_in\~input) - (DELAY - (ABSOLUTE - (IOPATH i o (459:459:459) (708:708:708)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~86) - (DELAY - (ABSOLUTE - (PORT dataa (843:843:843) (876:876:876)) - (PORT datac (1426:1426:1426) (1503:1503:1503)) - (PORT datad (1841:1841:1841) (1862:1862:1862)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~100) - (DELAY - (ABSOLUTE - (PORT dataa (879:879:879) (895:895:895)) - (PORT datab (1277:1277:1277) (1232:1232:1232)) - (PORT datac (163:163:163) (197:197:197)) - (PORT datad (166:166:166) (188:188:188)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~101) - (DELAY - (ABSOLUTE - (PORT dataa (875:875:875) (888:888:888)) - (PORT datab (824:824:824) (860:860:860)) - (PORT datac (1535:1535:1535) (1519:1519:1519)) - (PORT datad (159:159:159) (181:181:181)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[6\]) - (DELAY - (ABSOLUTE - (PORT dataa (243:243:243) (297:297:297)) - (PORT datab (1288:1288:1288) (1272:1272:1272)) - (PORT datac (874:874:874) (915:915:915)) - (PORT datad (772:772:772) (740:740:740)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_re\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1556:1556:1556) (1645:1645:1645)) - (PORT datab (703:703:703) (765:765:765)) - (PORT datac (881:881:881) (918:918:918)) - (PORT datad (1120:1120:1120) (1121:1121:1121)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_2) - (DELAY - (ABSOLUTE - (PORT dataa (900:900:900) (944:944:944)) - (PORT datab (906:906:906) (920:920:920)) - (PORT datac (883:883:883) (919:919:919)) - (PORT datad (166:166:166) (189:189:189)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1347:1347:1347) (1358:1358:1358)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (763:763:763) (771:771:771)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[6\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (219:219:219)) - (PORT datab (1089:1089:1089) (1102:1102:1102)) - (PORT datac (202:202:202) (249:249:249)) - (PORT datad (190:190:190) (219:219:219)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|ir_\|opcode\[6\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (178:178:178) (198:198:198)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1024:1024:1024) (1078:1078:1078)) - (PORT datab (838:838:838) (869:869:869)) - (PORT datac (607:607:607) (638:638:638)) - (PORT datad (352:352:352) (353:353:353)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1343:1343:1343) (1360:1360:1360)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1395:1395:1395) (1367:1367:1367)) - (PORT ena (1130:1130:1130) (1103:1103:1103)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal41\~0) - (DELAY - (ABSOLUTE - (PORT datac (1564:1564:1564) (1572:1572:1572)) - (PORT datad (1132:1132:1132) (1167:1167:1167)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal41\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1375:1375:1375) (1400:1400:1400)) - (PORT datab (2129:2129:2129) (2186:2186:2186)) - (PORT datac (1970:1970:1970) (2062:2062:2062)) - (PORT datad (1338:1338:1338) (1386:1386:1386)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal41\~2) - (DELAY - (ABSOLUTE - (PORT dataa (415:415:415) (454:454:454)) - (PORT datab (1517:1517:1517) (1484:1484:1484)) - (PORT datac (155:155:155) (184:184:184)) - (PORT datad (1017:1017:1017) (1026:1026:1026)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe) - (DELAY - (ABSOLUTE - (PORT dataa (1815:1815:1815) (1864:1864:1864)) - (PORT datab (1040:1040:1040) (1024:1024:1024)) - (PORT datac (1910:1910:1910) (1950:1950:1950)) - (PORT datad (164:164:164) (186:186:186)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1096:1096:1096) (1097:1097:1097)) - (PORT datab (252:252:252) (318:318:318)) - (PORT datac (228:228:228) (287:287:287)) - (PORT datad (224:224:224) (260:260:260)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1046:1046:1046) (1077:1077:1077)) - (PORT datab (1066:1066:1066) (1087:1087:1087)) - (PORT datac (384:384:384) (438:438:438)) - (PORT datad (619:619:619) (637:637:637)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (889:889:889) (890:890:890)) - (PORT datac (1540:1540:1540) (1543:1543:1543)) - (PORT datad (836:836:836) (826:826:826)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~18) - (DELAY - (ABSOLUTE - (PORT datab (184:184:184) (217:217:217)) - (PORT datac (820:820:820) (816:816:816)) - (PORT datad (223:223:223) (257:257:257)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (346:346:346) (350:350:350)) - (PORT datab (585:585:585) (576:576:576)) - (PORT datac (1068:1068:1068) (1089:1089:1089)) - (PORT datad (565:565:565) (556:556:556)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (919:919:919) (929:929:929)) - (PORT datac (549:549:549) (545:545:545)) - (PORT datad (200:200:200) (239:239:239)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[5\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (1176:1176:1176) (1208:1208:1208)) - (PORT datab (868:868:868) (867:867:867)) - (PORT datac (1676:1676:1676) (1689:1689:1689)) - (PORT datad (864:864:864) (874:874:874)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[5\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (607:607:607) (606:606:606)) - (PORT datab (230:230:230) (282:282:282)) - (PORT datac (159:159:159) (190:190:190)) - (PORT datad (871:871:871) (883:883:883)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sw1_\|db_down\[5\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (330:330:330) (459:459:459)) - (PORT datab (1249:1249:1249) (1259:1259:1259)) - (PORT datac (1070:1070:1070) (1065:1065:1065)) - (PORT datad (1106:1106:1106) (1118:1118:1118)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_36) - (DELAY - (ABSOLUTE - (PORT dataa (517:517:517) (511:511:511)) - (PORT datab (584:584:584) (585:585:585)) - (PORT datac (608:608:608) (617:617:617)) - (PORT datad (625:625:625) (634:634:634)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|flags_yf) - (DELAY - (ABSOLUTE - (PORT clk (1336:1336:1336) (1353:1353:1353)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (745:745:745) (751:751:751)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[5\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (604:604:604) (618:618:618)) - (PORT datab (827:827:827) (852:852:852)) - (PORT datac (605:605:605) (615:615:615)) - (PORT datad (821:821:821) (812:812:812)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[5\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (899:899:899) (902:902:902)) - (PORT datab (183:183:183) (216:216:216)) - (PORT datac (874:874:874) (874:874:874)) - (PORT datad (805:805:805) (791:791:791)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[5\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (636:636:636) (641:641:641)) - (PORT datab (1109:1109:1109) (1091:1091:1091)) - (PORT datac (1028:1028:1028) (1036:1036:1036)) - (PORT datad (160:160:160) (182:182:182)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~107) - (DELAY - (ABSOLUTE - (PORT dataa (1618:1618:1618) (1660:1660:1660)) - (PORT datab (1133:1133:1133) (1150:1150:1150)) - (PORT datac (1446:1446:1446) (1508:1508:1508)) - (PORT datad (1045:1045:1045) (1034:1034:1034)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1107:1107:1107) (1081:1081:1081)) - (PORT clk (1632:1632:1632) (1660:1660:1660)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3423:3423:3423) (3511:3511:3511)) - (PORT d[1] (1610:1610:1610) (1712:1712:1712)) - (PORT d[2] (2815:2815:2815) (2865:2865:2865)) - (PORT d[3] (1754:1754:1754) (1799:1799:1799)) - (PORT d[4] (2040:2040:2040) (2098:2098:2098)) - (PORT d[5] (2484:2484:2484) (2590:2590:2590)) - (PORT d[6] (1915:1915:1915) (1948:1948:1948)) - (PORT d[7] (2568:2568:2568) (2586:2586:2586)) - (PORT d[8] (2819:2819:2819) (2925:2925:2925)) - (PORT d[9] (2617:2617:2617) (2662:2662:2662)) - (PORT d[10] (3254:3254:3254) (3360:3360:3360)) - (PORT d[11] (1682:1682:1682) (1715:1715:1715)) - (PORT d[12] (1930:1930:1930) (1983:1983:1983)) - (PORT clk (1629:1629:1629) (1658:1658:1658)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1794:1794:1794) (1753:1753:1753)) - (PORT clk (1629:1629:1629) (1658:1658:1658)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1632:1632:1632) (1660:1660:1660)) - (PORT d[0] (2430:2430:2430) (2431:2431:2431)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1633:1633:1633) (1661:1661:1661)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1633:1633:1633) (1661:1661:1661)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1633:1633:1633) (1661:1661:1661)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1633:1633:1633) (1661:1661:1661)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1596:1596:1596) (1624:1624:1624)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (867:867:867) (871:871:871)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (868:868:868) (872:872:872)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (868:868:868) (872:872:872)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (868:868:868) (872:872:872)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1096:1096:1096) (1074:1074:1074)) - (PORT clk (1630:1630:1630) (1658:1658:1658)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3694:3694:3694) (3794:3794:3794)) - (PORT d[1] (1581:1581:1581) (1666:1666:1666)) - (PORT d[2] (3056:3056:3056) (3113:3113:3113)) - (PORT d[3] (1749:1749:1749) (1779:1779:1779)) - (PORT d[4] (1736:1736:1736) (1765:1765:1765)) - (PORT d[5] (1519:1519:1519) (1586:1586:1586)) - (PORT d[6] (1635:1635:1635) (1666:1666:1666)) - (PORT d[7] (2830:2830:2830) (2851:2851:2851)) - (PORT d[8] (3086:3086:3086) (3198:3198:3198)) - (PORT d[9] (2654:2654:2654) (2713:2713:2713)) - (PORT d[10] (3197:3197:3197) (3270:3270:3270)) - (PORT d[11] (1430:1430:1430) (1454:1454:1454)) - (PORT d[12] (1604:1604:1604) (1641:1641:1641)) - (PORT clk (1627:1627:1627) (1656:1656:1656)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1789:1789:1789) (1719:1719:1719)) - (PORT clk (1627:1627:1627) (1656:1656:1656)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1630:1630:1630) (1658:1658:1658)) - (PORT d[0] (2199:2199:2199) (2121:2121:2121)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1631:1631:1631) (1659:1659:1659)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1631:1631:1631) (1659:1659:1659)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1631:1631:1631) (1659:1659:1659)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1631:1631:1631) (1659:1659:1659)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1594:1594:1594) (1622:1622:1622)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (865:865:865) (869:869:869)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (866:866:866) (870:870:870)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (866:866:866) (870:870:870)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (866:866:866) (870:870:870)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1132:1132:1132) (1118:1118:1118)) - (PORT clk (1630:1630:1630) (1658:1658:1658)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3424:3424:3424) (3512:3512:3512)) - (PORT d[1] (1571:1571:1571) (1675:1675:1675)) - (PORT d[2] (2754:2754:2754) (2823:2823:2823)) - (PORT d[3] (1969:1969:1969) (1988:1988:1988)) - (PORT d[4] (2069:2069:2069) (2124:2124:2124)) - (PORT d[5] (2492:2492:2492) (2612:2612:2612)) - (PORT d[6] (1673:1673:1673) (1720:1720:1720)) - (PORT d[7] (2571:2571:2571) (2592:2592:2592)) - (PORT d[8] (3107:3107:3107) (3211:3211:3211)) - (PORT d[9] (2672:2672:2672) (2732:2732:2732)) - (PORT d[10] (3224:3224:3224) (3324:3324:3324)) - (PORT d[11] (1692:1692:1692) (1728:1728:1728)) - (PORT d[12] (1875:1875:1875) (1914:1914:1914)) - (PORT clk (1627:1627:1627) (1656:1656:1656)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1755:1755:1755) (1697:1697:1697)) - (PORT clk (1627:1627:1627) (1656:1656:1656)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1630:1630:1630) (1658:1658:1658)) - (PORT d[0] (2267:2267:2267) (2233:2233:2233)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1631:1631:1631) (1659:1659:1659)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1631:1631:1631) (1659:1659:1659)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1631:1631:1631) (1659:1659:1659)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1631:1631:1631) (1659:1659:1659)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1594:1594:1594) (1622:1622:1622)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (865:865:865) (869:869:869)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (866:866:866) (870:870:870)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (866:866:866) (870:870:870)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (866:866:866) (870:870:870)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1338:1338:1338) (1342:1342:1342)) - (PORT datab (1310:1310:1310) (1345:1345:1345)) - (PORT datac (1055:1055:1055) (1028:1028:1028)) - (PORT datad (1035:1035:1035) (1017:1017:1017)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1177:1177:1177) (1189:1189:1189)) - (PORT clk (1639:1639:1639) (1667:1667:1667)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2678:2678:2678) (2705:2705:2705)) - (PORT d[1] (2465:2465:2465) (2605:2605:2605)) - (PORT d[2] (1123:1123:1123) (1138:1138:1138)) - (PORT d[3] (1565:1565:1565) (1603:1603:1603)) - (PORT d[4] (2689:2689:2689) (2795:2795:2795)) - (PORT d[5] (2214:2214:2214) (2342:2342:2342)) - (PORT d[6] (1167:1167:1167) (1193:1193:1193)) - (PORT d[7] (1224:1224:1224) (1251:1251:1251)) - (PORT d[8] (1619:1619:1619) (1631:1631:1631)) - (PORT d[9] (1169:1169:1169) (1184:1184:1184)) - (PORT d[10] (2227:2227:2227) (2272:2272:2272)) - (PORT d[11] (2936:2936:2936) (3022:3022:3022)) - (PORT d[12] (2039:2039:2039) (2078:2078:2078)) - (PORT clk (1636:1636:1636) (1665:1665:1665)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1377:1377:1377) (1357:1357:1357)) - (PORT clk (1636:1636:1636) (1665:1665:1665)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1667:1667:1667)) - (PORT d[0] (1925:1925:1925) (1914:1914:1914)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1640:1640:1640) (1668:1668:1668)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1640:1640:1640) (1668:1668:1668)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1640:1640:1640) (1668:1668:1668)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1640:1640:1640) (1668:1668:1668)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1603:1603:1603) (1631:1631:1631)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (878:878:878)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (875:875:875) (879:879:879)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (875:875:875) (879:879:879)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (875:875:875) (879:879:879)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1045:1045:1045) (1054:1054:1054)) - (PORT datab (1569:1569:1569) (1585:1585:1585)) - (PORT datac (155:155:155) (185:185:185)) - (PORT datad (1315:1315:1315) (1322:1322:1322)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1492:1492:1492) (1530:1530:1530)) - (PORT clk (1638:1638:1638) (1665:1665:1665)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2957:2957:2957) (2968:2968:2968)) - (PORT d[1] (1859:1859:1859) (1960:1960:1960)) - (PORT d[2] (2024:2024:2024) (2042:2042:2042)) - (PORT d[3] (1726:1726:1726) (1784:1784:1784)) - (PORT d[4] (2308:2308:2308) (2357:2357:2357)) - (PORT d[5] (2072:2072:2072) (2153:2153:2153)) - (PORT d[6] (1595:1595:1595) (1605:1605:1605)) - (PORT d[7] (1567:1567:1567) (1598:1598:1598)) - (PORT d[8] (2423:2423:2423) (2497:2497:2497)) - (PORT d[9] (1817:1817:1817) (1859:1859:1859)) - (PORT d[10] (1866:1866:1866) (1904:1904:1904)) - (PORT d[11] (2253:2253:2253) (2298:2298:2298)) - (PORT d[12] (2364:2364:2364) (2372:2372:2372)) - (PORT clk (1635:1635:1635) (1663:1663:1663)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2369:2369:2369) (2331:2331:2331)) - (PORT clk (1635:1635:1635) (1663:1663:1663)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1638:1638:1638) (1665:1665:1665)) - (PORT d[0] (3638:3638:3638) (3625:3625:3625)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1666:1666:1666)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1666:1666:1666)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1666:1666:1666)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1666:1666:1666)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1597:1597:1597) (1595:1595:1595)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1613:1613:1613) (1560:1560:1560)) - (PORT clk (1605:1605:1605) (1602:1602:1602)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4091:4091:4091) (4004:4004:4004)) - (PORT d[1] (3942:3942:3942) (3858:3858:3858)) - (PORT d[2] (4035:4035:4035) (3940:3940:3940)) - (PORT d[3] (4359:4359:4359) (4253:4253:4253)) - (PORT d[4] (4055:4055:4055) (3927:3927:3927)) - (PORT d[5] (4299:4299:4299) (4223:4223:4223)) - (PORT d[6] (4408:4408:4408) (4355:4355:4355)) - (PORT d[7] (4042:4042:4042) (3983:3983:3983)) - (PORT d[8] (4110:4110:4110) (3989:3989:3989)) - (PORT d[9] (4148:4148:4148) (4218:4218:4218)) - (PORT d[10] (4304:4304:4304) (4166:4166:4166)) - (PORT d[11] (4107:4107:4107) (3994:3994:3994)) - (PORT d[12] (4188:4188:4188) (4201:4201:4201)) - (PORT clk (1602:1602:1602) (1599:1599:1599)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1605:1605:1605) (1602:1602:1602)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1606:1606:1606) (1603:1603:1603)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1606:1606:1606) (1603:1603:1603)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1606:1606:1606) (1603:1603:1603)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1606:1606:1606) (1603:1603:1603)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2654:2654:2654) (2677:2677:2677)) - (PORT d[1] (1605:1605:1605) (1701:1701:1701)) - (PORT d[2] (1805:1805:1805) (1844:1844:1844)) - (PORT d[3] (1758:1758:1758) (1811:1811:1811)) - (PORT d[4] (2545:2545:2545) (2597:2597:2597)) - (PORT d[5] (2062:2062:2062) (2158:2158:2158)) - (PORT d[6] (1833:1833:1833) (1844:1844:1844)) - (PORT d[7] (1979:1979:1979) (2050:2050:2050)) - (PORT d[8] (2211:2211:2211) (2278:2278:2278)) - (PORT d[9] (1831:1831:1831) (1863:1863:1863)) - (PORT d[10] (1561:1561:1561) (1568:1568:1568)) - (PORT d[11] (1894:1894:1894) (1910:1910:1910)) - (PORT d[12] (2323:2323:2323) (2341:2341:2341)) - (PORT clk (1642:1642:1642) (1671:1671:1671)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1642:1642:1642) (1671:1671:1671)) - (PORT d[0] (2518:2518:2518) (2506:2506:2506)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1643:1643:1643) (1672:1672:1672)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1609:1609:1609) (1637:1637:1637)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (880:880:880) (884:884:884)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (881:881:881) (885:885:885)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (881:881:881) (885:885:885)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (881:881:881) (885:885:885)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3650:3650:3650) (3721:3721:3721)) - (PORT d[1] (2659:2659:2659) (2780:2780:2780)) - (PORT d[2] (2501:2501:2501) (2532:2532:2532)) - (PORT d[3] (2111:2111:2111) (2186:2186:2186)) - (PORT d[4] (2332:2332:2332) (2410:2410:2410)) - (PORT d[5] (2343:2343:2343) (2420:2420:2420)) - (PORT d[6] (1758:1758:1758) (1814:1814:1814)) - (PORT d[7] (2110:2110:2110) (2124:2124:2124)) - (PORT d[8] (2878:2878:2878) (3013:3013:3013)) - (PORT d[9] (2488:2488:2488) (2560:2560:2560)) - (PORT d[10] (4188:4188:4188) (4256:4256:4256)) - (PORT d[11] (1794:1794:1794) (1865:1865:1865)) - (PORT d[12] (2232:2232:2232) (2284:2284:2284)) - (PORT clk (1643:1643:1643) (1671:1671:1671)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1643:1643:1643) (1671:1671:1671)) - (PORT d[0] (3251:3251:3251) (3306:3306:3306)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1644:1644:1644) (1672:1672:1672)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1610:1610:1610) (1637:1637:1637)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (881:881:881) (884:884:884)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (885:885:885)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (885:885:885)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (885:885:885)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1388:1388:1388) (1400:1400:1400)) - (PORT clk (1653:1653:1653) (1680:1680:1680)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2615:2615:2615) (2615:2615:2615)) - (PORT d[1] (1928:1928:1928) (2048:2048:2048)) - (PORT d[2] (2048:2048:2048) (2108:2108:2108)) - (PORT d[3] (2094:2094:2094) (2149:2149:2149)) - (PORT d[4] (2727:2727:2727) (2871:2871:2871)) - (PORT d[5] (2213:2213:2213) (2304:2304:2304)) - (PORT d[6] (1452:1452:1452) (1493:1493:1493)) - (PORT d[7] (1446:1446:1446) (1477:1477:1477)) - (PORT d[8] (2564:2564:2564) (2665:2665:2665)) - (PORT d[9] (1933:1933:1933) (1963:1963:1963)) - (PORT d[10] (1735:1735:1735) (1770:1770:1770)) - (PORT d[11] (2684:2684:2684) (2729:2729:2729)) - (PORT d[12] (1488:1488:1488) (1509:1509:1509)) - (PORT clk (1650:1650:1650) (1678:1678:1678)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2318:2318:2318) (2256:2256:2256)) - (PORT clk (1650:1650:1650) (1678:1678:1678)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1653:1653:1653) (1680:1680:1680)) - (PORT d[0] (2607:2607:2607) (2597:2597:2597)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1654:1654:1654) (1681:1681:1681)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1654:1654:1654) (1681:1681:1681)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1654:1654:1654) (1681:1681:1681)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1654:1654:1654) (1681:1681:1681)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1612:1612:1612) (1610:1610:1610)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2309:2309:2309) (2319:2319:2319)) - (PORT clk (1620:1620:1620) (1617:1617:1617)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4211:4211:4211) (4070:4070:4070)) - (PORT d[1] (3836:3836:3836) (3699:3699:3699)) - (PORT d[2] (4108:4108:4108) (3975:3975:3975)) - (PORT d[3] (4152:4152:4152) (4053:4053:4053)) - (PORT d[4] (4243:4243:4243) (4094:4094:4094)) - (PORT d[5] (4089:4089:4089) (4013:4013:4013)) - (PORT d[6] (4274:4274:4274) (4211:4211:4211)) - (PORT d[7] (3881:3881:3881) (3728:3728:3728)) - (PORT d[8] (4330:4330:4330) (4206:4206:4206)) - (PORT d[9] (4176:4176:4176) (4207:4207:4207)) - (PORT d[10] (4313:4313:4313) (4213:4213:4213)) - (PORT d[11] (4097:4097:4097) (3970:3970:3970)) - (PORT d[12] (4147:4147:4147) (4084:4084:4084)) - (PORT clk (1617:1617:1617) (1614:1614:1614)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1620:1620:1620) (1617:1617:1617)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1621:1621:1621) (1618:1618:1618)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1621:1621:1621) (1618:1618:1618)) - (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1621:1621:1621) (1618:1618:1618)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1621:1621:1621) (1618:1618:1618)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1613:1613:1613) (1611:1611:1611)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Mux2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1327:1327:1327) (1341:1341:1341)) - (PORT datab (908:908:908) (940:940:940)) - (PORT datac (1088:1088:1088) (1077:1077:1077)) - (PORT datad (1560:1560:1560) (1534:1534:1534)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Mux2\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1400:1400:1400) (1441:1441:1441)) - (PORT datab (909:909:909) (941:941:941)) - (PORT datac (1580:1580:1580) (1576:1576:1576)) - (PORT datad (157:157:157) (177:177:177)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[5\]\~110) - (DELAY - (ABSOLUTE - (PORT dataa (184:184:184) (221:221:221)) - (PORT datab (1130:1130:1130) (1141:1141:1141)) - (PORT datac (1529:1529:1529) (1526:1526:1526)) - (PORT datad (160:160:160) (182:182:182)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[5\]\~85) - (DELAY - (ABSOLUTE - (PORT dataa (1282:1282:1282) (1254:1254:1254)) - (PORT datab (1295:1295:1295) (1272:1272:1272)) - (PORT datac (787:787:787) (812:812:812)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[5\]\~99) - (DELAY - (ABSOLUTE - (PORT dataa (758:758:758) (752:752:752)) - (PORT datad (177:177:177) (198:198:198)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[5\]) - (DELAY - (ABSOLUTE - (PORT dataa (903:903:903) (945:945:945)) - (PORT datab (961:961:961) (952:952:952)) - (PORT datac (212:212:212) (261:261:261)) - (PORT datad (883:883:883) (890:890:890)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1347:1347:1347) (1358:1358:1358)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (763:763:763) (771:771:771)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[5\]\~14) - (DELAY - (ABSOLUTE - (PORT datab (656:656:656) (656:656:656)) - (PORT datac (212:212:212) (277:277:277)) - (PORT datad (327:327:327) (343:343:343)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[5\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (903:903:903) (903:903:903)) - (PORT datab (849:849:849) (863:863:863)) - (PORT datac (755:755:755) (734:734:734)) - (PORT datad (817:817:817) (825:825:825)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1366:1366:1366)) - (PORT asdata (535:535:535) (588:588:588)) - (PORT clrn (1390:1390:1390) (1361:1361:1361)) - (PORT ena (1363:1363:1363) (1319:1319:1319)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|SYNTHESIZED_WIRE_0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1109:1109:1109) (1188:1188:1188)) - (PORT datab (795:795:795) (797:797:797)) - (PORT datac (798:798:798) (786:786:786)) - (PORT datad (1753:1753:1753) (1750:1750:1750)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|DFFE_inst4) - (DELAY - (ABSOLUTE - (PORT clk (1348:1348:1348) (1369:1369:1369)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1407:1407:1407) (1373:1373:1373)) - (PORT ena (745:745:745) (752:752:752)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|use_ixiy) - (DELAY - (ABSOLUTE - (PORT dataa (895:895:895) (970:970:970)) - (PORT datac (852:852:852) (909:909:909)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~23) - (DELAY - (ABSOLUTE - (PORT dataa (1100:1100:1100) (1111:1111:1111)) - (PORT datab (918:918:918) (981:981:981)) - (PORT datac (602:602:602) (641:641:641)) - (PORT datad (1150:1150:1150) (1209:1209:1209)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~34) - (DELAY - (ABSOLUTE - (PORT dataa (817:817:817) (821:821:821)) - (PORT datab (613:613:613) (611:611:611)) - (PORT datac (833:833:833) (862:862:862)) - (PORT datad (334:334:334) (344:344:344)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~31) - (DELAY - (ABSOLUTE - (PORT dataa (1087:1087:1087) (1094:1094:1094)) - (PORT datab (1490:1490:1490) (1461:1461:1461)) - (PORT datac (568:568:568) (582:582:582)) - (PORT datad (1010:1010:1010) (1002:1002:1002)) - (IOPATH dataa combout (307:307:307) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~29) - (DELAY - (ABSOLUTE - (PORT dataa (1158:1158:1158) (1204:1204:1204)) - (PORT datab (424:424:424) (464:464:464)) - (PORT datac (1567:1567:1567) (1577:1577:1577)) - (PORT datad (239:239:239) (288:288:288)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~30) - (DELAY - (ABSOLUTE - (PORT dataa (366:366:366) (397:397:397)) - (PORT datab (182:182:182) (215:215:215)) - (PORT datac (998:998:998) (998:998:998)) - (PORT datad (184:184:184) (209:209:209)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~28) - (DELAY - (ABSOLUTE - (PORT dataa (1090:1090:1090) (1095:1095:1095)) - (PORT datab (533:533:533) (540:540:540)) - (PORT datac (1016:1016:1016) (1014:1014:1014)) - (PORT datad (295:295:295) (304:304:304)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~32) - (DELAY - (ABSOLUTE - (PORT dataa (786:786:786) (800:800:800)) - (PORT datab (181:181:181) (213:213:213)) - (PORT datac (542:542:542) (547:547:547)) - (PORT datad (161:161:161) (182:182:182)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~42) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (247:247:247)) - (PORT datab (598:598:598) (592:592:592)) - (PORT datac (175:175:175) (217:217:217)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~14) - (DELAY - (ABSOLUTE - (PORT dataa (816:816:816) (820:820:820)) - (PORT datab (1037:1037:1037) (1034:1034:1034)) - (PORT datac (1298:1298:1298) (1314:1314:1314)) - (PORT datad (830:830:830) (865:865:865)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~10) - (DELAY - (ABSOLUTE - (PORT dataa (819:819:819) (816:816:816)) - (PORT datab (871:871:871) (884:884:884)) - (PORT datac (882:882:882) (920:920:920)) - (PORT datad (1026:1026:1026) (1026:1026:1026)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~9) - (DELAY - (ABSOLUTE - (PORT dataa (818:818:818) (822:822:822)) - (PORT datab (806:806:806) (804:804:804)) - (PORT datac (1022:1022:1022) (1012:1012:1012)) - (PORT datad (307:307:307) (310:310:310)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1451:1451:1451) (1494:1494:1494)) - (PORT datab (188:188:188) (221:221:221)) - (PORT datac (1752:1752:1752) (1765:1765:1765)) - (PORT datad (158:158:158) (178:178:178)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1040:1040:1040) (1132:1132:1132)) - (PORT datab (922:922:922) (956:956:956)) - (PORT datac (1511:1511:1511) (1516:1516:1516)) - (PORT datad (1079:1079:1079) (1103:1103:1103)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1315:1315:1315) (1302:1302:1302)) - (PORT datab (1038:1038:1038) (1036:1036:1036)) - (PORT datac (967:967:967) (957:957:957)) - (PORT datad (309:309:309) (319:319:319)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~15) - (DELAY - (ABSOLUTE - (PORT dataa (184:184:184) (221:221:221)) - (PORT datab (180:180:180) (213:213:213)) - (PORT datac (156:156:156) (187:187:187)) - (PORT datad (550:550:550) (538:538:538)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~20) - (DELAY - (ABSOLUTE - (PORT dataa (580:580:580) (569:569:569)) - (PORT datab (965:965:965) (976:976:976)) - (PORT datac (533:533:533) (512:512:512)) - (PORT datad (553:553:553) (572:572:572)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~48) - (DELAY - (ABSOLUTE - (PORT dataa (821:821:821) (847:847:847)) - (PORT datab (1109:1109:1109) (1102:1102:1102)) - (PORT datac (1394:1394:1394) (1410:1410:1410)) - (PORT datad (622:622:622) (636:636:636)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~22) - (DELAY - (ABSOLUTE - (PORT dataa (1263:1263:1263) (1241:1241:1241)) - (PORT datab (792:792:792) (785:785:785)) - (PORT datac (992:992:992) (970:970:970)) - (PORT datad (177:177:177) (199:199:199)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (308:308:308) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~21) - (DELAY - (ABSOLUTE - (PORT dataa (802:802:802) (854:854:854)) - (PORT datab (867:867:867) (916:916:916)) - (PORT datac (1446:1446:1446) (1424:1424:1424)) - (PORT datad (1118:1118:1118) (1102:1102:1102)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~23) - (DELAY - (ABSOLUTE - (PORT dataa (808:808:808) (802:802:802)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (746:746:746) (736:736:736)) - (PORT datad (158:158:158) (180:180:180)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~26) - (DELAY - (ABSOLUTE - (PORT dataa (1902:1902:1902) (1935:1935:1935)) - (PORT datab (1116:1116:1116) (1117:1117:1117)) - (PORT datac (1048:1048:1048) (1072:1072:1072)) - (PORT datad (1067:1067:1067) (1091:1091:1091)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~25) - (DELAY - (ABSOLUTE - (PORT dataa (2313:2313:2313) (2349:2349:2349)) - (PORT datab (542:542:542) (526:526:526)) - (PORT datac (175:175:175) (206:206:206)) - (PORT datad (911:911:911) (916:916:916)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~27) - (DELAY - (ABSOLUTE - (PORT dataa (1541:1541:1541) (1491:1491:1491)) - (PORT datab (770:770:770) (809:809:809)) - (PORT datac (953:953:953) (981:981:981)) - (PORT datad (712:712:712) (733:733:733)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~33) - (DELAY - (ABSOLUTE - (PORT dataa (961:961:961) (932:932:932)) - (PORT datab (182:182:182) (216:216:216)) - (PORT datac (761:761:761) (783:783:783)) - (PORT datad (158:158:158) (180:180:180)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~35) - (DELAY - (ABSOLUTE - (PORT dataa (809:809:809) (801:801:801)) - (PORT datab (182:182:182) (213:213:213)) - (PORT datac (758:758:758) (780:780:780)) - (PORT datad (177:177:177) (198:198:198)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_re) - (DELAY - (ABSOLUTE - (PORT datab (907:907:907) (921:921:921)) - (PORT datac (885:885:885) (921:921:921)) - (PORT datad (167:167:167) (191:191:191)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (935:935:935) (965:965:965)) - (PORT clk (1646:1646:1646) (1674:1674:1674)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1102:1102:1102) (1088:1088:1088)) - (PORT d[1] (2237:2237:2237) (2392:2392:2392)) - (PORT d[2] (1622:1622:1622) (1627:1627:1627)) - (PORT d[3] (936:936:936) (958:958:958)) - (PORT d[4] (2428:2428:2428) (2538:2538:2538)) - (PORT d[5] (3242:3242:3242) (3357:3357:3357)) - (PORT d[6] (950:950:950) (981:981:981)) - (PORT d[7] (2952:2952:2952) (3001:3001:3001)) - (PORT d[8] (1157:1157:1157) (1143:1143:1143)) - (PORT d[9] (950:950:950) (974:974:974)) - (PORT d[10] (1217:1217:1217) (1248:1248:1248)) - (PORT d[11] (2323:2323:2323) (2395:2395:2395)) - (PORT d[12] (1207:1207:1207) (1237:1237:1237)) - (PORT clk (1643:1643:1643) (1672:1672:1672)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (863:863:863) (813:813:813)) - (PORT clk (1643:1643:1643) (1672:1672:1672)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1646:1646:1646) (1674:1674:1674)) - (PORT d[0] (1543:1543:1543) (1494:1494:1494)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1675:1675:1675)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1675:1675:1675)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1675:1675:1675)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1675:1675:1675)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1610:1610:1610) (1638:1638:1638)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (881:881:881) (885:885:885)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (886:886:886)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (886:886:886)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (886:886:886)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (659:659:659) (684:684:684)) - (PORT clk (1646:1646:1646) (1672:1672:1672)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (892:892:892) (908:908:908)) - (PORT d[1] (2746:2746:2746) (2901:2901:2901)) - (PORT d[2] (1143:1143:1143) (1158:1158:1158)) - (PORT d[3] (1198:1198:1198) (1236:1236:1236)) - (PORT d[4] (2401:2401:2401) (2505:2505:2505)) - (PORT d[5] (2764:2764:2764) (2904:2904:2904)) - (PORT d[6] (643:643:643) (644:644:644)) - (PORT d[7] (654:654:654) (659:659:659)) - (PORT d[8] (938:938:938) (949:949:949)) - (PORT d[9] (667:667:667) (672:672:672)) - (PORT d[10] (962:962:962) (987:987:987)) - (PORT d[11] (2364:2364:2364) (2465:2465:2465)) - (PORT d[12] (1168:1168:1168) (1176:1176:1176)) - (PORT clk (1643:1643:1643) (1670:1670:1670)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (885:885:885) (852:852:852)) - (PORT clk (1643:1643:1643) (1670:1670:1670)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1646:1646:1646) (1672:1672:1672)) - (PORT d[0] (1900:1900:1900) (1848:1848:1848)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1673:1673:1673)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1673:1673:1673)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1673:1673:1673)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1673:1673:1673)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1610:1610:1610) (1636:1636:1636)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (881:881:881) (883:883:883)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (884:884:884)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (884:884:884)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (884:884:884)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[1\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (632:632:632) (670:670:670)) - (PORT datab (626:626:626) (667:667:667)) - (PORT datac (735:735:735) (706:706:706)) - (PORT datad (796:796:796) (797:797:797)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (651:651:651) (672:672:672)) - (PORT clk (1646:1646:1646) (1672:1672:1672)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2935:2935:2935) (2963:2963:2963)) - (PORT d[1] (2718:2718:2718) (2863:2863:2863)) - (PORT d[2] (893:893:893) (888:888:888)) - (PORT d[3] (1235:1235:1235) (1270:1270:1270)) - (PORT d[4] (2431:2431:2431) (2549:2549:2549)) - (PORT d[5] (2464:2464:2464) (2593:2593:2593)) - (PORT d[6] (888:888:888) (891:891:891)) - (PORT d[7] (1176:1176:1176) (1191:1191:1191)) - (PORT d[8] (1345:1345:1345) (1346:1346:1346)) - (PORT d[9] (900:900:900) (906:906:906)) - (PORT d[10] (956:956:956) (956:956:956)) - (PORT d[11] (2665:2665:2665) (2768:2768:2768)) - (PORT d[12] (895:895:895) (910:910:910)) - (PORT clk (1643:1643:1643) (1670:1670:1670)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1141:1141:1141) (1101:1101:1101)) - (PORT clk (1643:1643:1643) (1670:1670:1670)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1646:1646:1646) (1672:1672:1672)) - (PORT d[0] (1845:1845:1845) (1794:1794:1794)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1673:1673:1673)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1673:1673:1673)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1673:1673:1673)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1673:1673:1673)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1610:1610:1610) (1636:1636:1636)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (881:881:881) (883:883:883)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (884:884:884)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (884:884:884)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (884:884:884)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (692:692:692) (704:704:704)) - (PORT clk (1645:1645:1645) (1672:1672:1672)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2955:2955:2955) (2983:2983:2983)) - (PORT d[1] (2482:2482:2482) (2633:2633:2633)) - (PORT d[2] (1195:1195:1195) (1176:1176:1176)) - (PORT d[3] (1239:1239:1239) (1274:1274:1274)) - (PORT d[4] (2434:2434:2434) (2550:2550:2550)) - (PORT d[5] (2483:2483:2483) (2619:2619:2619)) - (PORT d[6] (1142:1142:1142) (1146:1146:1146)) - (PORT d[7] (1054:1054:1054) (1040:1040:1040)) - (PORT d[8] (1372:1372:1372) (1377:1377:1377)) - (PORT d[9] (1432:1432:1432) (1452:1452:1452)) - (PORT d[10] (675:675:675) (689:689:689)) - (PORT d[11] (2649:2649:2649) (2760:2760:2760)) - (PORT d[12] (899:899:899) (923:923:923)) - (PORT clk (1642:1642:1642) (1670:1670:1670)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1127:1127:1127) (1106:1106:1106)) - (PORT clk (1642:1642:1642) (1670:1670:1670)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1645:1645:1645) (1672:1672:1672)) - (PORT d[0] (1644:1644:1644) (1629:1629:1629)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1646:1646:1646) (1673:1673:1673)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1646:1646:1646) (1673:1673:1673)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1646:1646:1646) (1673:1673:1673)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1646:1646:1646) (1673:1673:1673)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1609:1609:1609) (1636:1636:1636)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (880:880:880) (883:883:883)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (881:881:881) (884:884:884)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (881:881:881) (884:884:884)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (881:881:881) (884:884:884)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[1\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1145:1145:1145) (1184:1184:1184)) - (PORT datab (182:182:182) (215:215:215)) - (PORT datac (893:893:893) (908:908:908)) - (PORT datad (1017:1017:1017) (1005:1005:1005)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (695:695:695) (707:707:707)) - (PORT clk (1639:1639:1639) (1665:1665:1665)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2694:2694:2694) (2715:2715:2715)) - (PORT d[1] (2202:2202:2202) (2342:2342:2342)) - (PORT d[2] (1461:1461:1461) (1446:1446:1446)) - (PORT d[3] (1823:1823:1823) (1876:1876:1876)) - (PORT d[4] (2718:2718:2718) (2847:2847:2847)) - (PORT d[5] (2496:2496:2496) (2625:2625:2625)) - (PORT d[6] (1171:1171:1171) (1200:1200:1200)) - (PORT d[7] (1210:1210:1210) (1238:1238:1238)) - (PORT d[8] (1623:1623:1623) (1628:1628:1628)) - (PORT d[9] (1439:1439:1439) (1440:1440:1440)) - (PORT d[10] (2000:2000:2000) (2046:2046:2046)) - (PORT d[11] (3000:3000:3000) (3059:3059:3059)) - (PORT d[12] (1185:1185:1185) (1206:1206:1206)) - (PORT clk (1636:1636:1636) (1663:1663:1663)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2714:2714:2714) (2633:2633:2633)) - (PORT clk (1636:1636:1636) (1663:1663:1663)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1665:1665:1665)) - (PORT d[0] (2818:2818:2818) (2820:2820:2820)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1640:1640:1640) (1666:1666:1666)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1640:1640:1640) (1666:1666:1666)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1640:1640:1640) (1666:1666:1666)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1640:1640:1640) (1666:1666:1666)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1598:1598:1598) (1595:1595:1595)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1970:1970:1970) (1951:1951:1951)) - (PORT clk (1606:1606:1606) (1602:1602:1602)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4076:4076:4076) (3965:3965:3965)) - (PORT d[1] (3875:3875:3875) (3743:3743:3743)) - (PORT d[2] (3989:3989:3989) (3887:3887:3887)) - (PORT d[3] (4083:4083:4083) (3937:3937:3937)) - (PORT d[4] (4070:4070:4070) (3924:3924:3924)) - (PORT d[5] (4108:4108:4108) (3942:3942:3942)) - (PORT d[6] (4311:4311:4311) (4264:4264:4264)) - (PORT d[7] (4148:4148:4148) (3989:3989:3989)) - (PORT d[8] (4132:4132:4132) (3981:3981:3981)) - (PORT d[9] (4173:4173:4173) (4216:4216:4216)) - (PORT d[10] (4116:4116:4116) (4015:4015:4015)) - (PORT d[11] (4192:4192:4192) (4103:4103:4103)) - (PORT d[12] (4115:4115:4115) (4104:4104:4104)) - (PORT clk (1603:1603:1603) (1599:1599:1599)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1606:1606:1606) (1602:1602:1602)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1607:1607:1607) (1603:1603:1603)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1607:1607:1607) (1603:1603:1603)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1607:1607:1607) (1603:1603:1603)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1607:1607:1607) (1603:1603:1603)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2389:2389:2389) (2383:2383:2383)) - (PORT d[1] (1886:1886:1886) (1981:1981:1981)) - (PORT d[2] (2142:2142:2142) (2224:2224:2224)) - (PORT d[3] (2338:2338:2338) (2394:2394:2394)) - (PORT d[4] (2742:2742:2742) (2871:2871:2871)) - (PORT d[5] (2111:2111:2111) (2197:2197:2197)) - (PORT d[6] (1722:1722:1722) (1770:1770:1770)) - (PORT d[7] (2347:2347:2347) (2335:2335:2335)) - (PORT d[8] (2572:2572:2572) (2670:2670:2670)) - (PORT d[9] (1628:1628:1628) (1651:1651:1651)) - (PORT d[10] (1407:1407:1407) (1425:1425:1425)) - (PORT d[11] (3201:3201:3201) (3238:3238:3238)) - (PORT d[12] (1429:1429:1429) (1464:1464:1464)) - (PORT clk (1654:1654:1654) (1681:1681:1681)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1654:1654:1654) (1681:1681:1681)) - (PORT d[0] (2025:2025:2025) (2024:2024:2024)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1655:1655:1655) (1682:1682:1682)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1621:1621:1621) (1647:1647:1647)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (892:892:892) (894:894:894)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (893:893:893) (895:895:895)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (893:893:893) (895:895:895)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (893:893:893) (895:895:895)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1399:1399:1399) (1397:1397:1397)) - (PORT d[1] (2487:2487:2487) (2630:2630:2630)) - (PORT d[2] (915:915:915) (928:928:928)) - (PORT d[3] (1548:1548:1548) (1584:1584:1584)) - (PORT d[4] (2415:2415:2415) (2530:2530:2530)) - (PORT d[5] (2516:2516:2516) (2652:2652:2652)) - (PORT d[6] (901:901:901) (917:917:917)) - (PORT d[7] (894:894:894) (904:904:904)) - (PORT d[8] (1329:1329:1329) (1335:1335:1335)) - (PORT d[9] (1448:1448:1448) (1474:1474:1474)) - (PORT d[10] (2291:2291:2291) (2346:2346:2346)) - (PORT d[11] (2678:2678:2678) (2795:2795:2795)) - (PORT d[12] (1175:1175:1175) (1180:1180:1180)) - (PORT clk (1641:1641:1641) (1669:1669:1669)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1641:1641:1641) (1669:1669:1669)) - (PORT d[0] (779:779:779) (793:793:793)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1642:1642:1642) (1670:1670:1670)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1608:1608:1608) (1635:1635:1635)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (879:879:879) (882:882:882)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (880:880:880) (883:883:883)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (880:880:880) (883:883:883)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (880:880:880) (883:883:883)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (865:865:865) (830:830:830)) - (PORT clk (1642:1642:1642) (1669:1669:1669)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2940:2940:2940) (2959:2959:2959)) - (PORT d[1] (2474:2474:2474) (2624:2624:2624)) - (PORT d[2] (1461:1461:1461) (1436:1436:1436)) - (PORT d[3] (1564:1564:1564) (1602:1602:1602)) - (PORT d[4] (2707:2707:2707) (2850:2850:2850)) - (PORT d[5] (2515:2515:2515) (2652:2652:2652)) - (PORT d[6] (902:902:902) (918:918:918)) - (PORT d[7] (1429:1429:1429) (1432:1432:1432)) - (PORT d[8] (2832:2832:2832) (2949:2949:2949)) - (PORT d[9] (924:924:924) (939:939:939)) - (PORT d[10] (2294:2294:2294) (2352:2352:2352)) - (PORT d[11] (2654:2654:2654) (2768:2768:2768)) - (PORT d[12] (2065:2065:2065) (2107:2107:2107)) - (PORT clk (1639:1639:1639) (1667:1667:1667)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2843:2843:2843) (2788:2788:2788)) - (PORT clk (1639:1639:1639) (1667:1667:1667)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1642:1642:1642) (1669:1669:1669)) - (PORT d[0] (1605:1605:1605) (1615:1615:1615)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1643:1643:1643) (1670:1670:1670)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1643:1643:1643) (1670:1670:1670)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1643:1643:1643) (1670:1670:1670)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1643:1643:1643) (1670:1670:1670)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1601:1601:1601) (1599:1599:1599)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2235:2235:2235) (2216:2216:2216)) - (PORT clk (1609:1609:1609) (1606:1606:1606)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4297:4297:4297) (4178:4178:4178)) - (PORT d[1] (3968:3968:3968) (3900:3900:3900)) - (PORT d[2] (3965:3965:3965) (3856:3856:3856)) - (PORT d[3] (4092:4092:4092) (3987:3987:3987)) - (PORT d[4] (4044:4044:4044) (3897:3897:3897)) - (PORT d[5] (4223:4223:4223) (4114:4114:4114)) - (PORT d[6] (4401:4401:4401) (4356:4356:4356)) - (PORT d[7] (4190:4190:4190) (4089:4089:4089)) - (PORT d[8] (4127:4127:4127) (3976:3976:3976)) - (PORT d[9] (4184:4184:4184) (4235:4235:4235)) - (PORT d[10] (4172:4172:4172) (4085:4085:4085)) - (PORT d[11] (4109:4109:4109) (3983:3983:3983)) - (PORT d[12] (4090:4090:4090) (3988:3988:3988)) - (PORT clk (1606:1606:1606) (1603:1603:1603)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1609:1609:1609) (1606:1606:1606)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1610:1610:1610) (1607:1607:1607)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1610:1610:1610) (1607:1607:1607)) - (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1610:1610:1610) (1607:1607:1607)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1610:1610:1610) (1607:1607:1607)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1602:1602:1602) (1600:1600:1600)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Selector1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (619:619:619) (651:651:651)) - (PORT datab (1099:1099:1099) (1121:1121:1121)) - (PORT datac (777:777:777) (756:756:756)) - (PORT datad (820:820:820) (810:810:810)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Selector1\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1108:1108:1108) (1094:1094:1094)) - (PORT datab (1099:1099:1099) (1121:1121:1121)) - (PORT datac (1392:1392:1392) (1407:1407:1407)) - (PORT datad (157:157:157) (178:178:178)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~103) - (DELAY - (ABSOLUTE - (PORT dataa (1626:1626:1626) (1633:1633:1633)) - (PORT datab (1300:1300:1300) (1339:1339:1339)) - (PORT datac (595:595:595) (621:621:621)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_io_ibuf") (INSTANCE PS2_DAT\~input) @@ -36080,24 +28878,45 @@ ) ) (CELL - (CELLTYPE "cycloneive_clkctrl") - (INSTANCE reset\~clkctrl) + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE KEY\[0\]\~input) (DELAY (ABSOLUTE - (PORT inclk[0] (768:768:768) (767:767:767)) + (IOPATH i o (461:461:461) (708:708:708)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\~0) + (INSTANCE reset) (DELAY (ABSOLUTE - (PORT dataa (256:256:256) (347:347:347)) - (PORT datab (261:261:261) (345:345:345)) - (PORT datad (220:220:220) (289:289:289)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) + (PORT datac (1423:1423:1423) (1417:1417:1417)) + (PORT datad (757:757:757) (748:748:748)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE reset\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (521:521:521) (513:513:513)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\~3) + (DELAY + (ABSOLUTE + (PORT dataa (249:249:249) (337:337:337)) + (PORT datab (251:251:251) (339:339:339)) + (PORT datad (227:227:227) (297:297:297)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -36117,7 +28936,7 @@ (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[7\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (2920:2920:2920) (3165:3165:3165)) + (PORT datad (2762:2762:2762) (2941:2941:2941)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -36127,9 +28946,9 @@ (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[7\]) (DELAY (ABSOLUTE - (PORT clk (1334:1334:1334) (1352:1352:1352)) + (PORT clk (1331:1331:1331) (1349:1349:1349)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1386:1386:1386) (1368:1368:1368)) + (PORT clrn (1373:1373:1373) (1353:1353:1353)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -36143,7 +28962,7 @@ (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[6\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (204:204:204) (265:265:265)) + (PORT datad (205:205:205) (267:267:267)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -36153,9 +28972,9 @@ (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[6\]) (DELAY (ABSOLUTE - (PORT clk (1334:1334:1334) (1352:1352:1352)) + (PORT clk (1331:1331:1331) (1349:1349:1349)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1386:1386:1386) (1368:1368:1368)) + (PORT clrn (1373:1373:1373) (1353:1353:1353)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -36169,7 +28988,7 @@ (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[5\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (208:208:208) (270:270:270)) + (PORT datad (219:219:219) (277:277:277)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -36179,9 +28998,9 @@ (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[5\]) (DELAY (ABSOLUTE - (PORT clk (1334:1334:1334) (1352:1352:1352)) + (PORT clk (1331:1331:1331) (1349:1349:1349)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1386:1386:1386) (1368:1368:1368)) + (PORT clrn (1373:1373:1373) (1353:1353:1353)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -36195,7 +29014,7 @@ (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[4\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (218:218:218) (276:276:276)) + (PORT datad (204:204:204) (264:264:264)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -36205,9 +29024,9 @@ (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[4\]) (DELAY (ABSOLUTE - (PORT clk (1334:1334:1334) (1352:1352:1352)) + (PORT clk (1331:1331:1331) (1349:1349:1349)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1386:1386:1386) (1368:1368:1368)) + (PORT clrn (1373:1373:1373) (1353:1353:1353)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -36216,28 +29035,12 @@ (HOLD d (posedge clk) (144:144:144)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|Equal0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (230:230:230) (305:305:305)) - (PORT datab (229:229:229) (299:299:299)) - (PORT datac (352:352:352) (390:390:390)) - (PORT datad (206:206:206) (266:266:266)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[3\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (207:207:207) (267:267:267)) + (PORT datad (206:206:206) (269:269:269)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -36247,9 +29050,9 @@ (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[3\]) (DELAY (ABSOLUTE - (PORT clk (1334:1334:1334) (1352:1352:1352)) + (PORT clk (1331:1331:1331) (1349:1349:1349)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1386:1386:1386) (1368:1368:1368)) + (PORT clrn (1373:1373:1373) (1353:1353:1353)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -36263,7 +29066,7 @@ (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[2\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (208:208:208) (269:269:269)) + (PORT datad (206:206:206) (268:268:268)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -36273,9 +29076,9 @@ (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[2\]) (DELAY (ABSOLUTE - (PORT clk (1334:1334:1334) (1352:1352:1352)) + (PORT clk (1331:1331:1331) (1349:1349:1349)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1386:1386:1386) (1368:1368:1368)) + (PORT clrn (1373:1373:1373) (1353:1353:1353)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -36289,7 +29092,7 @@ (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[1\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (204:204:204) (266:266:266)) + (PORT datad (204:204:204) (264:264:264)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -36299,9 +29102,9 @@ (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[1\]) (DELAY (ABSOLUTE - (PORT clk (1334:1334:1334) (1352:1352:1352)) + (PORT clk (1331:1331:1331) (1349:1349:1349)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1386:1386:1386) (1368:1368:1368)) + (PORT clrn (1373:1373:1373) (1353:1353:1353)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -36310,17 +29113,33 @@ (HOLD d (posedge clk) (144:144:144)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (230:230:230) (306:306:306)) + (PORT datab (229:229:229) (300:300:300)) + (PORT datac (354:354:354) (394:394:394)) + (PORT datad (206:206:206) (266:266:266)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|ps2_keyboard_\|Equal0\~1) (DELAY (ABSOLUTE - (PORT dataa (185:185:185) (222:222:222)) - (PORT datab (230:230:230) (301:301:301)) - (PORT datac (203:203:203) (273:273:273)) - (PORT datad (207:207:207) (267:267:267)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) + (PORT dataa (231:231:231) (306:306:306)) + (PORT datab (231:231:231) (302:302:302)) + (PORT datac (204:204:204) (275:275:275)) + (PORT datad (160:160:160) (182:182:182)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -36331,7 +29150,7 @@ (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[0\]\~0) (DELAY (ABSOLUTE - (PORT datac (204:204:204) (275:275:275)) + (PORT datac (205:205:205) (276:276:276)) (IOPATH datac combout (218:218:218) (215:215:215)) ) ) @@ -36341,9 +29160,9 @@ (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[0\]) (DELAY (ABSOLUTE - (PORT clk (1334:1334:1334) (1352:1352:1352)) + (PORT clk (1331:1331:1331) (1349:1349:1349)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1386:1386:1386) (1368:1368:1368)) + (PORT clrn (1373:1373:1373) (1353:1353:1353)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -36357,9 +29176,9 @@ (INSTANCE ula_\|ps2_keyboard_\|ps2_clk_in\~0) (DELAY (ABSOLUTE - (PORT datab (189:189:189) (225:225:225)) + (PORT dataa (193:193:193) (233:233:233)) (PORT datad (207:207:207) (267:267:267)) - (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH dataa combout (318:318:318) (327:327:327)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -36370,9 +29189,9 @@ (INSTANCE ula_\|ps2_keyboard_\|ps2_clk_in) (DELAY (ABSOLUTE - (PORT clk (1334:1334:1334) (1352:1352:1352)) + (PORT clk (1331:1331:1331) (1349:1349:1349)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1386:1386:1386) (1368:1368:1368)) + (PORT clrn (1373:1373:1373) (1353:1353:1353)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -36386,10 +29205,10 @@ (INSTANCE ula_\|ps2_keyboard_\|clk_edge\~0) (DELAY (ABSOLUTE - (PORT datab (189:189:189) (226:226:226)) - (PORT datac (197:197:197) (265:265:265)) - (PORT datad (204:204:204) (263:263:263)) - (IOPATH datab combout (273:273:273) (275:275:275)) + (PORT dataa (194:194:194) (237:237:237)) + (PORT datac (196:196:196) (263:263:263)) + (PORT datad (208:208:208) (269:269:269)) + (IOPATH dataa combout (272:272:272) (269:269:269)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -36400,9 +29219,9 @@ (INSTANCE ula_\|ps2_keyboard_\|clk_edge) (DELAY (ABSOLUTE - (PORT clk (1334:1334:1334) (1352:1352:1352)) + (PORT clk (1331:1331:1331) (1349:1349:1349)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1386:1386:1386) (1368:1368:1368)) + (PORT clrn (1373:1373:1373) (1353:1353:1353)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -36413,13 +29232,13 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\[0\]) + (INSTANCE ula_\|ps2_keyboard_\|bit_count\[3\]) (DELAY (ABSOLUTE - (PORT clk (1343:1343:1343) (1361:1361:1361)) + (PORT clk (1328:1328:1328) (1347:1347:1347)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1388:1388:1388) (1369:1369:1369)) - (PORT ena (1851:1851:1851) (1843:1843:1843)) + (PORT clrn (1371:1371:1371) (1351:1351:1351)) + (PORT ena (2088:2088:2088) (2116:2116:2116)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -36434,9 +29253,9 @@ (INSTANCE ula_\|ps2_keyboard_\|bit_count\~1) (DELAY (ABSOLUTE - (PORT dataa (257:257:257) (347:347:347)) - (PORT datab (261:261:261) (345:345:345)) - (PORT datad (217:217:217) (282:282:282)) + (PORT dataa (247:247:247) (331:331:331)) + (PORT datab (254:254:254) (332:332:332)) + (PORT datad (228:228:228) (301:301:301)) (IOPATH dataa combout (272:272:272) (269:269:269)) (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (312:312:312) (325:325:325)) @@ -36449,43 +29268,10 @@ (INSTANCE ula_\|ps2_keyboard_\|bit_count\[2\]) (DELAY (ABSOLUTE - (PORT clk (1343:1343:1343) (1361:1361:1361)) + (PORT clk (1328:1328:1328) (1347:1347:1347)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1388:1388:1388) (1369:1369:1369)) - (PORT ena (1851:1851:1851) (1843:1843:1843)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\~3) - (DELAY - (ABSOLUTE - (PORT dataa (253:253:253) (343:343:343)) - (PORT datab (252:252:252) (332:332:332)) - (PORT datad (220:220:220) (286:286:286)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1343:1343:1343) (1361:1361:1361)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1388:1388:1388) (1369:1369:1369)) - (PORT ena (1851:1851:1851) (1843:1843:1843)) + (PORT clrn (1371:1371:1371) (1351:1351:1351)) + (PORT ena (2088:2088:2088) (2116:2116:2116)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -36500,9 +29286,9 @@ (INSTANCE ula_\|ps2_keyboard_\|bit_count\~2) (DELAY (ABSOLUTE - (PORT dataa (382:382:382) (424:424:424)) - (PORT datab (253:253:253) (334:334:334)) - (PORT datad (220:220:220) (287:287:287)) + (PORT dataa (248:248:248) (336:336:336)) + (PORT datab (250:250:250) (338:338:338)) + (PORT datad (224:224:224) (294:294:294)) (IOPATH dataa combout (318:318:318) (327:327:327)) (IOPATH datab combout (295:295:295) (285:285:285)) (IOPATH datac combout (312:312:312) (325:325:325)) @@ -36515,10 +29301,43 @@ (INSTANCE ula_\|ps2_keyboard_\|bit_count\[1\]) (DELAY (ABSOLUTE - (PORT clk (1343:1343:1343) (1361:1361:1361)) + (PORT clk (1328:1328:1328) (1347:1347:1347)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1388:1388:1388) (1369:1369:1369)) - (PORT ena (1851:1851:1851) (1843:1843:1843)) + (PORT clrn (1371:1371:1371) (1351:1351:1351)) + (PORT ena (2088:2088:2088) (2116:2116:2116)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\~0) + (DELAY + (ABSOLUTE + (PORT dataa (254:254:254) (337:337:337)) + (PORT datab (245:245:245) (331:331:331)) + (PORT datad (227:227:227) (297:297:297)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1328:1328:1328) (1347:1347:1347)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1371:1371:1371) (1351:1351:1351)) + (PORT ena (2088:2088:2088) (2116:2116:2116)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -36533,10 +29352,10 @@ (INSTANCE ula_\|ps2_keyboard_\|always1\~0) (DELAY (ABSOLUTE - (PORT dataa (250:250:250) (338:338:338)) - (PORT datab (257:257:257) (338:338:338)) - (PORT datac (2974:2974:2974) (3250:3250:3250)) - (PORT datad (226:226:226) (296:296:296)) + (PORT dataa (250:250:250) (334:334:334)) + (PORT datab (248:248:248) (336:336:336)) + (PORT datac (3607:3607:3607) (3911:3911:3911)) + (PORT datad (220:220:220) (289:289:289)) (IOPATH dataa combout (309:309:309) (326:326:326)) (IOPATH datab combout (309:309:309) (328:328:328)) (IOPATH datac combout (218:218:218) (215:215:215)) @@ -36549,11 +29368,11 @@ (INSTANCE ula_\|ps2_keyboard_\|LessThan0\~0) (DELAY (ABSOLUTE - (PORT datab (259:259:259) (343:343:343)) - (PORT datac (225:225:225) (310:310:310)) + (PORT dataa (251:251:251) (339:339:339)) + (PORT datab (247:247:247) (335:335:335)) (PORT datad (223:223:223) (292:292:292)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -36563,12 +29382,12 @@ (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[0\]\~0) (DELAY (ABSOLUTE - (PORT dataa (185:185:185) (222:222:222)) - (PORT datab (241:241:241) (316:316:316)) - (PORT datac (1265:1265:1265) (1274:1274:1274)) - (PORT datad (167:167:167) (191:191:191)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (295:295:295) (300:300:300)) + (PORT dataa (245:245:245) (329:329:329)) + (PORT datab (185:185:185) (218:218:218)) + (PORT datac (1501:1501:1501) (1553:1553:1553)) + (PORT datad (167:167:167) (190:190:190)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (300:300:300) (312:312:312)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -36579,10 +29398,10 @@ (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[8\]) (DELAY (ABSOLUTE - (PORT clk (1351:1351:1351) (1369:1369:1369)) - (PORT asdata (3472:3472:3472) (3720:3720:3720)) - (PORT clrn (1396:1396:1396) (1377:1377:1377)) - (PORT ena (1120:1120:1120) (1082:1082:1082)) + (PORT clk (1343:1343:1343) (1360:1360:1360)) + (PORT asdata (3621:3621:3621) (3902:3902:3902)) + (PORT clrn (1377:1377:1377) (1358:1358:1358)) + (PORT ena (1661:1661:1661) (1641:1641:1641)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -36592,21 +29411,31 @@ (HOLD ena (posedge clk) (144:144:144)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (200:200:200) (257:257:257)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[7\]) (DELAY (ABSOLUTE - (PORT clk (1351:1351:1351) (1369:1369:1369)) - (PORT asdata (506:506:506) (568:568:568)) - (PORT clrn (1396:1396:1396) (1377:1377:1377)) - (PORT ena (1120:1120:1120) (1082:1082:1082)) + (PORT clk (1343:1343:1343) (1360:1360:1360)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1377:1377:1377) (1358:1358:1358)) + (PORT ena (1661:1661:1661) (1641:1641:1641)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) + (HOLD d (posedge clk) (144:144:144)) (HOLD ena (posedge clk) (144:144:144)) ) ) @@ -36615,10 +29444,10 @@ (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[6\]) (DELAY (ABSOLUTE - (PORT clk (1351:1351:1351) (1369:1369:1369)) - (PORT asdata (540:540:540) (613:613:613)) - (PORT clrn (1396:1396:1396) (1377:1377:1377)) - (PORT ena (1120:1120:1120) (1082:1082:1082)) + (PORT clk (1343:1343:1343) (1360:1360:1360)) + (PORT asdata (564:564:564) (640:640:640)) + (PORT clrn (1377:1377:1377) (1358:1358:1358)) + (PORT ena (1661:1661:1661) (1641:1641:1641)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -36633,10 +29462,10 @@ (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[5\]) (DELAY (ABSOLUTE - (PORT clk (1351:1351:1351) (1369:1369:1369)) - (PORT asdata (530:530:530) (596:596:596)) - (PORT clrn (1396:1396:1396) (1377:1377:1377)) - (PORT ena (1120:1120:1120) (1082:1082:1082)) + (PORT clk (1343:1343:1343) (1360:1360:1360)) + (PORT asdata (945:945:945) (984:984:984)) + (PORT clrn (1377:1377:1377) (1358:1358:1358)) + (PORT ena (1661:1661:1661) (1641:1641:1641)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -36651,10 +29480,10 @@ (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[4\]) (DELAY (ABSOLUTE - (PORT clk (1351:1351:1351) (1369:1369:1369)) - (PORT asdata (875:875:875) (902:902:902)) - (PORT clrn (1396:1396:1396) (1377:1377:1377)) - (PORT ena (1102:1102:1102) (1092:1092:1092)) + (PORT clk (1343:1343:1343) (1360:1360:1360)) + (PORT asdata (727:727:727) (798:798:798)) + (PORT clrn (1377:1377:1377) (1358:1358:1358)) + (PORT ena (1661:1661:1661) (1641:1641:1641)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -36669,10 +29498,10 @@ (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[3\]) (DELAY (ABSOLUTE - (PORT clk (1351:1351:1351) (1369:1369:1369)) - (PORT asdata (887:887:887) (901:901:901)) - (PORT clrn (1396:1396:1396) (1377:1377:1377)) - (PORT ena (1120:1120:1120) (1082:1082:1082)) + (PORT clk (1338:1338:1338) (1356:1356:1356)) + (PORT asdata (1420:1420:1420) (1458:1458:1458)) + (PORT clrn (1380:1380:1380) (1360:1360:1360)) + (PORT ena (2108:2108:2108) (2071:2071:2071)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -36687,10 +29516,10 @@ (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[2\]) (DELAY (ABSOLUTE - (PORT clk (1351:1351:1351) (1369:1369:1369)) - (PORT asdata (872:872:872) (902:902:902)) - (PORT clrn (1396:1396:1396) (1377:1377:1377)) - (PORT ena (1102:1102:1102) (1092:1092:1092)) + (PORT clk (1342:1342:1342) (1359:1359:1359)) + (PORT asdata (1402:1402:1402) (1415:1415:1415)) + (PORT clrn (1376:1376:1376) (1357:1357:1357)) + (PORT ena (1822:1822:1822) (1776:1776:1776)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -36705,10 +29534,10 @@ (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[1\]) (DELAY (ABSOLUTE - (PORT clk (1351:1351:1351) (1369:1369:1369)) - (PORT asdata (694:694:694) (750:750:750)) - (PORT clrn (1396:1396:1396) (1377:1377:1377)) - (PORT ena (1102:1102:1102) (1092:1092:1092)) + (PORT clk (1342:1342:1342) (1359:1359:1359)) + (PORT asdata (543:543:543) (614:614:614)) + (PORT clrn (1376:1376:1376) (1357:1357:1357)) + (PORT ena (1822:1822:1822) (1776:1776:1776)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -36718,93 +29547,43 @@ (HOLD ena (posedge clk) (144:144:144)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1051:1051:1051) (1111:1111:1111)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[0\]) (DELAY (ABSOLUTE - (PORT clk (1351:1351:1351) (1369:1369:1369)) - (PORT asdata (705:705:705) (769:769:769)) - (PORT clrn (1396:1396:1396) (1377:1377:1377)) - (PORT ena (1102:1102:1102) (1092:1092:1092)) + (PORT clk (1331:1331:1331) (1350:1350:1350)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1374:1374:1374) (1354:1354:1354)) + (PORT ena (1160:1160:1160) (1151:1151:1151)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) + (HOLD d (posedge clk) (144:144:144)) (HOLD ena (posedge clk) (144:144:144)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Equal0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (909:909:909) (948:948:948)) - (PORT datab (620:620:620) (670:670:670)) - (PORT datac (696:696:696) (773:773:773)) - (PORT datad (707:707:707) (791:791:791)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Equal0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1301:1301:1301) (1379:1379:1379)) - (PORT datab (856:856:856) (908:908:908)) - (PORT datac (156:156:156) (187:187:187)) - (PORT datad (703:703:703) (782:782:782)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|extended\~0) - (DELAY - (ABSOLUTE - (PORT datab (980:980:980) (1034:1034:1034)) - (PORT datad (732:732:732) (716:716:716)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (620:620:620) (644:644:644)) - (PORT datab (259:259:259) (336:336:336)) - (PORT datad (770:770:770) (786:786:786)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~0) (DELAY (ABSOLUTE - (PORT dataa (670:670:670) (726:726:726)) - (PORT datab (617:617:617) (658:658:658)) - (PORT datac (597:597:597) (631:631:631)) - (PORT datad (407:407:407) (451:451:451)) + (PORT dataa (1070:1070:1070) (1141:1141:1141)) + (PORT datab (275:275:275) (369:369:369)) + (PORT datac (879:879:879) (928:928:928)) + (PORT datad (878:878:878) (919:919:919)) (IOPATH dataa combout (329:329:329) (332:332:332)) (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (220:220:220) (216:216:216)) @@ -36812,15 +29591,30 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (424:424:424) (499:499:499)) + (PORT datab (442:442:442) (524:524:524)) + (PORT datad (408:408:408) (444:444:444)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~2) (DELAY (ABSOLUTE - (PORT datab (621:621:621) (646:646:646)) - (PORT datac (323:323:323) (326:326:326)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH datab combout (325:325:325) (332:332:332)) + (PORT dataa (957:957:957) (1025:1025:1025)) + (PORT datac (158:158:158) (188:188:188)) + (PORT datad (715:715:715) (742:742:742)) + (IOPATH dataa combout (318:318:318) (327:327:327)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -36831,10 +29625,10 @@ (INSTANCE ula_\|ps2_keyboard_\|scan_code_ready\~0) (DELAY (ABSOLUTE - (PORT dataa (192:192:192) (230:230:230)) - (PORT datab (2992:2992:2992) (3284:3284:3284)) - (PORT datac (1265:1265:1265) (1274:1274:1274)) - (PORT datad (335:335:335) (348:348:348)) + (PORT dataa (3643:3643:3643) (3944:3944:3944)) + (PORT datab (1526:1526:1526) (1577:1577:1577)) + (PORT datac (579:579:579) (578:578:578)) + (PORT datad (166:166:166) (188:188:188)) (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) @@ -36847,9 +29641,9 @@ (INSTANCE ula_\|ps2_keyboard_\|scan_code_ready) (DELAY (ABSOLUTE - (PORT clk (1343:1343:1343) (1361:1361:1361)) + (PORT clk (1328:1328:1328) (1347:1347:1347)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1388:1388:1388) (1369:1369:1369)) + (PORT clrn (1371:1371:1371) (1351:1351:1351)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -36858,15 +29652,91 @@ (HOLD d (posedge clk) (144:144:144)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (406:406:406) (451:451:451)) + (PORT datab (906:906:906) (953:953:953)) + (PORT datac (853:853:853) (881:881:881)) + (PORT datad (622:622:622) (681:681:681)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (641:641:641) (692:692:692)) + (PORT datab (645:645:645) (675:675:675)) + (PORT datac (155:155:155) (185:185:185)) + (PORT datad (2024:2024:2024) (2055:2055:2055)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|released\~0) + (DELAY + (ABSOLUTE + (PORT dataa (262:262:262) (344:344:344)) + (PORT datab (1143:1143:1143) (1161:1161:1161)) + (PORT datad (313:313:313) (316:316:316)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|released) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1360:1360:1360)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1377:1377:1377) (1358:1358:1358)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|extended\~0) + (DELAY + (ABSOLUTE + (PORT dataa (337:337:337) (351:351:351)) + (PORT datad (873:873:873) (916:916:916)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|zx_keyboard_\|extended) (DELAY (ABSOLUTE - (PORT clk (1353:1353:1353) (1370:1370:1370)) + (PORT clk (1343:1343:1343) (1360:1360:1360)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1378:1378:1378)) - (PORT ena (1618:1618:1618) (1613:1613:1613)) + (PORT clrn (1376:1376:1376) (1357:1357:1357)) + (PORT ena (1679:1679:1679) (1696:1696:1696)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -36878,26 +29748,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~15) + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~21) (DELAY (ABSOLUTE - (PORT dataa (622:622:622) (660:660:660)) - (PORT datab (620:620:620) (628:628:628)) - (PORT datac (231:231:231) (309:309:309)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (445:445:445) (495:495:495)) - (PORT datac (1250:1250:1250) (1305:1305:1305)) - (PORT datad (782:782:782) (772:772:772)) + (PORT dataa (466:466:466) (519:519:519)) + (PORT datac (256:256:256) (334:334:334)) + (PORT datad (1106:1106:1106) (1126:1126:1126)) (IOPATH dataa combout (287:287:287) (280:280:280)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -36906,293 +29762,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~37) + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~22) (DELAY (ABSOLUTE - (PORT dataa (1087:1087:1087) (1146:1146:1146)) - (PORT datac (586:586:586) (609:609:609)) - (PORT datad (837:837:837) (881:881:881)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|shifted\~0) - (DELAY - (ABSOLUTE - (PORT dataa (370:370:370) (385:385:385)) - (PORT datac (565:565:565) (594:594:594)) - (PORT datad (673:673:673) (704:704:704)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|released\~0) - (DELAY - (ABSOLUTE - (PORT dataa (626:626:626) (648:648:648)) - (PORT datab (618:618:618) (630:630:630)) - (PORT datad (1230:1230:1230) (1225:1225:1225)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|released) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1369:1369:1369)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1396:1396:1396) (1377:1377:1377)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr17\~0) - (DELAY - (ABSOLUTE - (PORT dataa (435:435:435) (500:500:500)) - (PORT datab (607:607:607) (656:656:656)) - (PORT datac (560:560:560) (597:597:597)) - (PORT datad (236:236:236) (299:299:299)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|shifted\~2) - (DELAY - (ABSOLUTE - (PORT dataa (185:185:185) (223:223:223)) - (PORT datac (382:382:382) (444:444:444)) - (PORT datad (605:605:605) (640:640:640)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|shifted\~3) - (DELAY - (ABSOLUTE - (PORT dataa (553:553:553) (547:547:547)) - (PORT datab (394:394:394) (454:454:454)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|shifted) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1369:1369:1369)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1396:1396:1396) (1377:1377:1377)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (683:683:683) (747:747:747)) - (PORT datab (911:911:911) (954:954:954)) - (PORT datad (887:887:887) (928:928:928)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~38) - (DELAY - (ABSOLUTE - (PORT datab (690:690:690) (758:758:758)) - (PORT datac (684:684:684) (751:751:751)) - (PORT datad (679:679:679) (744:744:744)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~39) - (DELAY - (ABSOLUTE - (PORT dataa (328:328:328) (348:348:348)) - (PORT datab (185:185:185) (218:218:218)) - (PORT datad (161:161:161) (183:183:183)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1354:1354:1354) (1371:1371:1371)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1399:1399:1399) (1379:1379:1379)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]\~31) - (DELAY - (ABSOLUTE - (PORT datab (884:884:884) (934:934:934)) - (PORT datad (679:679:679) (743:743:743)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (682:682:682) (741:741:741)) - (PORT datab (259:259:259) (336:336:336)) - (PORT datac (596:596:596) (634:634:634)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~32) - (DELAY - (ABSOLUTE - (PORT datab (608:608:608) (641:641:641)) - (PORT datac (367:367:367) (415:415:415)) - (PORT datad (604:604:604) (638:638:638)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (352:352:352) (371:371:371)) - (PORT datab (201:201:201) (243:243:243)) - (PORT datac (599:599:599) (634:634:634)) - (PORT datad (402:402:402) (446:446:446)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (205:205:205) (243:243:243)) - (PORT datab (574:574:574) (597:597:597)) - (PORT datad (887:887:887) (926:926:926)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1354:1354:1354) (1371:1371:1371)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1399:1399:1399) (1379:1379:1379)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (1075:1075:1075) (1096:1096:1096)) - (PORT datab (220:220:220) (287:287:287)) - (PORT datac (195:195:195) (261:261:261)) - (PORT datad (511:511:511) (509:509:509)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (891:891:891) (924:924:924)) - (PORT datac (825:825:825) (873:873:873)) + (PORT dataa (621:621:621) (659:659:659)) + (PORT datac (234:234:234) (315:315:315)) (IOPATH dataa combout (307:307:307) (306:306:306)) (IOPATH datac combout (220:220:220) (216:216:216)) ) @@ -37200,29 +29774,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~28) + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]\~23) (DELAY (ABSOLUTE - (PORT dataa (1298:1298:1298) (1375:1375:1375)) - (PORT datab (636:636:636) (660:660:660)) - (PORT datac (882:882:882) (922:922:922)) - (PORT datad (171:171:171) (202:202:202)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~29) - (DELAY - (ABSOLUTE - (PORT datab (909:909:909) (952:952:952)) - (PORT datac (663:663:663) (734:734:734)) - (PORT datad (679:679:679) (745:745:745)) - (IOPATH datab combout (308:308:308) (300:300:300)) + (PORT dataa (780:780:780) (844:844:844)) + (PORT datab (926:926:926) (974:974:974)) + (PORT datac (765:765:765) (795:795:795)) + (PORT datad (1425:1425:1425) (1460:1460:1460)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -37230,73 +29790,26 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~30) + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]\~24) (DELAY (ABSOLUTE - (PORT dataa (729:729:729) (815:815:815)) - (PORT datab (615:615:615) (612:612:612)) - (PORT datad (468:468:468) (456:456:456)) - (IOPATH dataa combout (287:287:287) (289:289:289)) + (PORT dataa (685:685:685) (733:733:733)) + (PORT datab (877:877:877) (964:964:964)) + (PORT datad (180:180:180) (203:203:203)) + (IOPATH dataa combout (273:273:273) (269:269:269)) (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1371:1371:1371)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1379:1379:1379)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (1293:1293:1293) (1369:1369:1369)) - (PORT datab (194:194:194) (232:232:232)) - (PORT datac (608:608:608) (629:629:629)) - (PORT datad (706:706:706) (778:778:778)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]\~26) + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]\~25) (DELAY (ABSOLUTE - (PORT dataa (664:664:664) (731:731:731)) - (PORT datab (331:331:331) (353:353:353)) - (PORT datac (658:658:658) (726:726:726)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (1436:1436:1436) (1485:1485:1485)) - (PORT datab (909:909:909) (926:926:926)) - (PORT datad (485:485:485) (469:469:469)) + (PORT dataa (871:871:871) (910:910:910)) + (PORT datab (592:592:592) (642:642:642)) + (PORT datad (348:348:348) (363:363:363)) (IOPATH dataa combout (287:287:287) (289:289:289)) (IOPATH datab combout (295:295:295) (294:294:294)) (IOPATH datac combout (312:312:312) (325:325:325)) @@ -37309,9 +29822,9 @@ (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]) (DELAY (ABSOLUTE - (PORT clk (1353:1353:1353) (1370:1370:1370)) + (PORT clk (1338:1338:1338) (1357:1357:1357)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1397:1397:1397) (1378:1378:1378)) + (PORT clrn (1381:1381:1381) (1360:1360:1360)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -37325,23 +29838,374 @@ (INSTANCE ula_\|zx_keyboard_\|key_row\~0) (DELAY (ABSOLUTE - (PORT datab (1374:1374:1374) (1416:1416:1416)) - (PORT datac (846:846:846) (881:881:881)) - (PORT datad (198:198:198) (255:255:255)) + (PORT datab (2257:2257:2257) (2308:2308:2308)) + (PORT datac (1750:1750:1750) (1733:1733:1733)) + (PORT datad (197:197:197) (253:253:253)) (IOPATH datab combout (295:295:295) (285:285:285)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (780:780:780) (842:842:842)) + (PORT datab (931:931:931) (979:979:979)) + (PORT datac (764:764:764) (795:795:795)) + (PORT datad (833:833:833) (923:923:923)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (1222:1222:1222) (1269:1269:1269)) + (PORT datab (896:896:896) (945:945:945)) + (PORT datad (366:366:366) (420:420:420)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (560:560:560) (552:552:552)) + (PORT datab (882:882:882) (905:905:905)) + (PORT datad (169:169:169) (196:196:196)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1357:1357:1357)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1381:1381:1381) (1360:1360:1360)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[11\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1324:1324:1324) (1337:1337:1337)) + (PORT datab (1299:1299:1299) (1290:1290:1290)) + (PORT datad (285:285:285) (289:289:289)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1354:1354:1354)) + (PORT d (67:67:67) (78:78:78)) + (PORT asdata (900:900:900) (916:916:916)) + (PORT sload (1864:1864:1864) (1899:1899:1899)) + (PORT ena (2103:2103:2103) (2034:2034:2034)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sload (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[11\]\~19) + (DELAY + (ABSOLUTE + (PORT datac (1985:1985:1985) (1977:1977:1977)) + (PORT datad (1109:1109:1109) (1155:1155:1155)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (462:462:462) (513:513:513)) + (PORT datab (664:664:664) (710:710:710)) + (PORT datac (257:257:257) (339:339:339)) + (PORT datad (1106:1106:1106) (1124:1124:1124)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1107:1107:1107) (1146:1146:1146)) + (PORT datab (660:660:660) (700:700:700)) + (PORT datac (886:886:886) (945:945:945)) + (PORT datad (2043:2043:2043) (2068:2068:2068)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1378:1378:1378) (1430:1430:1430)) + (PORT datab (897:897:897) (915:915:915)) + (PORT datac (572:572:572) (566:566:566)) + (PORT datad (325:325:325) (327:327:327)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (714:714:714) (768:768:768)) + (PORT datad (160:160:160) (182:182:182)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1381:1381:1381) (1360:1360:1360)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[9\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1293:1293:1293) (1300:1300:1300)) + (PORT datab (811:811:811) (804:804:804)) + (PORT datad (165:165:165) (189:189:189)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1352:1352:1352)) + (PORT d (67:67:67) (78:78:78)) + (PORT asdata (524:524:524) (587:587:587)) + (PORT sload (1870:1870:1870) (1908:1908:1908)) + (PORT ena (1832:1832:1832) (1772:1772:1772)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sload (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[9\]\~17) + (DELAY + (ABSOLUTE + (PORT datab (238:238:238) (307:307:307)) + (PORT datac (2233:2233:2233) (2253:2253:2253)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~13) + (DELAY + (ABSOLUTE + (PORT datab (1143:1143:1143) (1158:1158:1158)) + (PORT datac (257:257:257) (338:338:338)) + (PORT datad (312:312:312) (315:315:315)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|shifted\~2) + (DELAY + (ABSOLUTE + (PORT datab (946:946:946) (996:996:996)) + (PORT datac (650:650:650) (682:682:682)) + (PORT datad (554:554:554) (551:551:551)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~14) (DELAY (ABSOLUTE - (PORT datab (391:391:391) (450:450:450)) - (PORT datac (1029:1029:1029) (1039:1039:1039)) - (PORT datad (605:605:605) (641:641:641)) + (PORT dataa (956:956:956) (1029:1029:1029)) + (PORT datab (276:276:276) (370:370:370)) + (PORT datac (877:877:877) (930:930:930)) + (PORT datad (874:874:874) (923:923:923)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (957:957:957) (1026:1026:1026)) + (PORT datab (183:183:183) (217:217:217)) + (PORT datac (882:882:882) (943:943:943)) + (PORT datad (1044:1044:1044) (1101:1101:1101)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr17\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1071:1071:1071) (1143:1143:1143)) + (PORT datab (276:276:276) (369:369:369)) + (PORT datac (879:879:879) (939:939:939)) + (PORT datad (844:844:844) (876:876:876)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|shifted\~5) + (DELAY + (ABSOLUTE + (PORT dataa (958:958:958) (1031:1031:1031)) + (PORT datab (902:902:902) (956:956:956)) + (PORT datac (298:298:298) (304:304:304)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|shifted\~4) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (219:219:219)) + (PORT datab (1080:1080:1080) (1096:1096:1096)) + (PORT datad (793:793:793) (792:792:792)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|shifted) + (DELAY + (ABSOLUTE + (PORT clk (1331:1331:1331) (1350:1350:1350)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1374:1374:1374) (1354:1354:1354)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~12) + (DELAY + (ABSOLUTE + (PORT datab (1083:1083:1083) (1100:1100:1100)) + (PORT datac (235:235:235) (304:304:304)) + (PORT datad (911:911:911) (983:983:983)) (IOPATH datab combout (308:308:308) (300:300:300)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -37353,43 +30217,11 @@ (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~16) (DELAY (ABSOLUTE - (PORT dataa (651:651:651) (689:689:689)) - (PORT datab (375:375:375) (438:438:438)) - (PORT datac (562:562:562) (598:598:598)) - (PORT datad (238:238:238) (303:303:303)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (436:436:436) (502:502:502)) - (PORT datab (608:608:608) (658:658:658)) - (PORT datac (463:463:463) (456:456:456)) - (PORT datad (609:609:609) (642:642:642)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (294:294:294)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (553:553:553) (546:546:546)) - (PORT datab (183:183:183) (215:215:215)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) + (PORT dataa (816:816:816) (829:829:829)) + (PORT datab (184:184:184) (218:218:218)) + (PORT datad (161:161:161) (183:183:183)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -37400,9 +30232,9 @@ (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]) (DELAY (ABSOLUTE - (PORT clk (1351:1351:1351) (1369:1369:1369)) + (PORT clk (1331:1331:1331) (1350:1350:1350)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1396:1396:1396) (1377:1377:1377)) + (PORT clrn (1374:1374:1374) (1354:1354:1354)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -37413,15 +30245,45 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~19) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[8\]\~8) (DELAY (ABSOLUTE - (PORT dataa (648:648:648) (680:680:680)) - (PORT datab (1141:1141:1141) (1156:1156:1156)) - (PORT datac (403:403:403) (453:453:453)) - (PORT datad (985:985:985) (970:970:970)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) + (PORT dataa (1291:1291:1291) (1297:1297:1297)) + (PORT datab (911:911:911) (915:915:915)) + (PORT datad (157:157:157) (178:178:178)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1352:1352:1352)) + (PORT d (67:67:67) (78:78:78)) + (PORT asdata (684:684:684) (717:717:717)) + (PORT sload (1870:1870:1870) (1908:1908:1908)) + (PORT ena (1832:1832:1832) (1772:1772:1772)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sload (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[8\]\~18) + (DELAY + (ABSOLUTE + (PORT datac (2228:2228:2228) (2277:2277:2277)) + (PORT datad (1347:1347:1347) (1357:1357:1357)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -37429,31 +30291,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~20) + (INSTANCE D\[1\]\~26) (DELAY (ABSOLUTE - (PORT dataa (697:697:697) (749:749:749)) - (PORT datab (1279:1279:1279) (1336:1336:1336)) - (PORT datac (842:842:842) (874:874:874)) - (PORT datad (796:796:796) (814:814:814)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (206:206:206) (254:254:254)) - (PORT datab (202:202:202) (236:236:236)) - (PORT datac (678:678:678) (745:745:745)) - (PORT datad (1423:1423:1423) (1456:1456:1456)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) + (PORT dataa (624:624:624) (677:677:677)) + (PORT datab (1051:1051:1051) (1007:1007:1007)) + (PORT datac (739:739:739) (800:800:800)) + (PORT datad (179:179:179) (202:202:202)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -37461,12 +30307,190 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]\~22) + (INSTANCE D\[1\]\~27) (DELAY (ABSOLUTE - (PORT datab (491:491:491) (476:476:476)) - (PORT datad (870:870:870) (892:892:892)) + (PORT dataa (184:184:184) (221:221:221)) + (PORT datab (361:361:361) (407:407:407)) + (PORT datac (983:983:983) (965:965:965)) + (PORT datad (157:157:157) (178:178:178)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[12\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1323:1323:1323) (1334:1334:1334)) + (PORT datab (314:314:314) (337:337:337)) + (PORT datad (521:521:521) (505:505:505)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1354:1354:1354)) + (PORT d (67:67:67) (78:78:78)) + (PORT asdata (531:531:531) (596:596:596)) + (PORT sload (1864:1864:1864) (1899:1899:1899)) + (PORT ena (2103:2103:2103) (2034:2034:2034)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sload (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[12\]\~21) + (DELAY + (ABSOLUTE + (PORT datac (2231:2231:2231) (2244:2244:2244)) + (PORT datad (918:918:918) (955:955:955)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|d1_out) + (DELAY + (ABSOLUTE + (PORT datab (358:358:358) (370:370:370)) + (PORT datad (375:375:375) (408:408:408)) (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[13\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1325:1325:1325) (1336:1336:1336)) + (PORT datab (180:180:180) (212:212:212)) + (PORT datad (176:176:176) (198:198:198)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1354:1354:1354)) + (PORT d (67:67:67) (78:78:78)) + (PORT asdata (893:893:893) (917:917:917)) + (PORT sload (1864:1864:1864) (1899:1899:1899)) + (PORT ena (2103:2103:2103) (2034:2034:2034)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sload (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[13\]\~20) + (DELAY + (ABSOLUTE + (PORT datab (2407:2407:2407) (2453:2453:2453)) + (PORT datad (2088:2088:2088) (2128:2128:2128)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (879:879:879) (905:905:905)) + (PORT datac (610:610:610) (663:663:663)) + (PORT datad (907:907:907) (968:968:968)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~34) + (DELAY + (ABSOLUTE + (PORT datab (656:656:656) (694:694:694)) + (PORT datac (650:650:650) (678:678:678)) + (PORT datad (555:555:555) (548:548:548)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (596:596:596) (604:604:604)) + (PORT datac (914:914:914) (947:947:947)) + (PORT datad (645:645:645) (691:691:691)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (1369:1369:1369) (1363:1363:1363)) + (PORT datab (663:663:663) (707:707:707)) + (PORT datad (842:842:842) (885:885:885)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (185:185:185) (221:221:221)) + (PORT datab (190:190:190) (225:225:225)) + (PORT datad (162:162:162) (183:183:183)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -37474,12 +30498,85 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]) + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]) (DELAY (ABSOLUTE - (PORT clk (1353:1353:1353) (1370:1370:1370)) + (PORT clk (1339:1339:1339) (1358:1358:1358)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1397:1397:1397) (1378:1378:1378)) + (PORT clrn (1382:1382:1382) (1362:1362:1362)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]\~29) + (DELAY + (ABSOLUTE + (PORT datac (876:876:876) (925:925:925)) + (PORT datad (611:611:611) (642:642:642)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (939:939:939) (977:977:977)) + (PORT datab (1140:1140:1140) (1182:1182:1182)) + (PORT datac (900:900:900) (958:958:958)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (383:383:383) (436:436:436)) + (PORT datab (607:607:607) (609:609:609)) + (PORT datac (321:321:321) (327:327:327)) + (PORT datad (861:861:861) (869:869:869)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (581:581:581) (599:599:599)) + (PORT datab (865:865:865) (914:914:914)) + (PORT datad (296:296:296) (306:306:306)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1358:1358:1358)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1382:1382:1382) (1362:1362:1362)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -37493,44 +30590,12 @@ (INSTANCE D\[1\]\~28) (DELAY (ABSOLUTE - (PORT dataa (617:617:617) (649:649:649)) - (PORT datab (1042:1042:1042) (1062:1062:1062)) - (PORT datac (587:587:587) (615:615:615)) - (PORT datad (197:197:197) (253:253:253)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (638:638:638) (676:676:676)) - (PORT datab (182:182:182) (215:215:215)) - (PORT datac (176:176:176) (208:208:208)) - (PORT datad (161:161:161) (182:182:182)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~41) - (DELAY - (ABSOLUTE - (PORT dataa (443:443:443) (492:492:492)) - (PORT datab (1139:1139:1139) (1158:1158:1158)) - (PORT datac (680:680:680) (750:750:750)) - (PORT datad (782:782:782) (771:771:771)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (273:273:273) (275:275:275)) + (PORT dataa (564:564:564) (564:564:564)) + (PORT datab (721:721:721) (712:712:712)) + (PORT datac (194:194:194) (259:259:259)) + (PORT datad (196:196:196) (253:253:253)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -37538,30 +30603,58 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~42) + (INSTANCE z80_\|address_pins_\|abus\[0\]\~16) (DELAY (ABSOLUTE - (PORT dataa (704:704:704) (774:774:774)) - (PORT datab (835:835:835) (872:872:872)) - (PORT datac (1026:1026:1026) (1029:1029:1029)) - (PORT datad (652:652:652) (707:707:707)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (285:285:285)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (PORT datab (887:887:887) (906:906:906)) + (PORT datac (2550:2550:2550) (2608:2608:2608)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~43) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[14\]\~14) (DELAY (ABSOLUTE - (PORT dataa (339:339:339) (354:354:354)) - (PORT datac (641:641:641) (699:699:699)) - (PORT datad (160:160:160) (182:182:182)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT dataa (1322:1322:1322) (1334:1334:1334)) + (PORT datab (200:200:200) (233:233:233)) + (PORT datad (288:288:288) (292:292:292)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1354:1354:1354)) + (PORT d (67:67:67) (78:78:78)) + (PORT asdata (526:526:526) (602:602:602)) + (PORT sload (1864:1864:1864) (1899:1899:1899)) + (PORT ena (2103:2103:2103) (2034:2034:2034)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sload (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[14\]\~23) + (DELAY + (ABSOLUTE + (PORT datac (2376:2376:2376) (2431:2431:2431)) + (PORT datad (1474:1474:1474) (1540:1540:1540)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -37571,23 +30664,71 @@ (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~40) (DELAY (ABSOLUTE - (PORT dataa (722:722:722) (779:779:779)) - (PORT datab (834:834:834) (870:870:870)) - (PORT datac (606:606:606) (657:657:657)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT dataa (911:911:911) (948:948:948)) + (PORT datab (1137:1137:1137) (1151:1151:1151)) + (PORT datad (1201:1201:1201) (1232:1232:1232)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~44) + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~41) (DELAY (ABSOLUTE - (PORT dataa (182:182:182) (218:218:218)) - (PORT datad (162:162:162) (183:183:183)) - (IOPATH dataa combout (318:318:318) (323:323:323)) + (PORT dataa (911:911:911) (955:955:955)) + (PORT datab (391:391:391) (452:452:452)) + (PORT datac (158:158:158) (189:189:189)) + (PORT datad (871:871:871) (910:910:910)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (714:714:714) (767:767:767)) + (PORT datab (687:687:687) (735:735:735)) + (PORT datac (532:532:532) (520:520:520)) + (PORT datad (392:392:392) (440:440:440)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (928:928:928) (937:937:937)) + (PORT datac (882:882:882) (916:916:916)) + (PORT datad (844:844:844) (869:869:869)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (185:185:185) (220:220:220)) + (PORT datab (600:600:600) (604:604:604)) + (PORT datad (160:160:160) (180:180:180)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -37598,9 +30739,9 @@ (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]) (DELAY (ABSOLUTE - (PORT clk (1353:1353:1353) (1370:1370:1370)) + (PORT clk (1338:1338:1338) (1357:1357:1357)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1397:1397:1397) (1378:1378:1378)) + (PORT clrn (1381:1381:1381) (1360:1360:1360)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -37611,13 +30752,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~45) + (INSTANCE ula_\|zx_keyboard_\|WideOr16\~4) (DELAY (ABSOLUTE - (PORT dataa (586:586:586) (628:628:628)) - (PORT datab (450:450:450) (517:517:517)) - (PORT datac (368:368:368) (413:413:413)) - (PORT datad (563:563:563) (566:566:566)) + (PORT dataa (1074:1074:1074) (1147:1147:1147)) + (PORT datab (276:276:276) (371:371:371)) + (PORT datac (878:878:878) (925:925:925)) + (PORT datad (875:875:875) (917:917:917)) (IOPATH dataa combout (318:318:318) (307:307:307)) (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (218:218:218) (215:215:215)) @@ -37625,48 +30766,16 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr16\~5) - (DELAY - (ABSOLUTE - (PORT dataa (755:755:755) (835:835:835)) - (PORT datab (859:859:859) (909:909:909)) - (PORT datac (697:697:697) (774:774:774)) - (PORT datad (704:704:704) (777:777:777)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|zx_keyboard_\|WideOr16\~2) (DELAY (ABSOLUTE - (PORT dataa (751:751:751) (830:830:830)) - (PORT datab (724:724:724) (796:796:796)) - (PORT datad (703:703:703) (783:783:783)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr16\~4) - (DELAY - (ABSOLUTE - (PORT dataa (753:753:753) (833:833:833)) - (PORT datab (856:856:856) (908:908:908)) - (PORT datac (696:696:696) (771:771:771)) - (PORT datad (703:703:703) (782:782:782)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (PORT datab (273:273:273) (364:364:364)) + (PORT datac (873:873:873) (925:925:925)) + (PORT datad (1050:1050:1050) (1109:1109:1109)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -37676,13 +30785,29 @@ (INSTANCE ula_\|zx_keyboard_\|WideOr16\~7) (DELAY (ABSOLUTE - (PORT dataa (211:211:211) (251:251:251)) - (PORT datab (860:860:860) (910:910:910)) - (PORT datac (294:294:294) (304:304:304)) - (PORT datad (1278:1278:1278) (1340:1340:1340)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT dataa (917:917:917) (973:973:973)) + (PORT datab (183:183:183) (216:216:216)) + (PORT datac (305:305:305) (315:315:315)) + (PORT datad (875:875:875) (919:919:919)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr16\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1072:1072:1072) (1144:1144:1144)) + (PORT datab (277:277:277) (369:369:369)) + (PORT datac (879:879:879) (927:927:927)) + (PORT datad (876:876:876) (919:919:919)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -37692,10 +30817,10 @@ (INSTANCE ula_\|zx_keyboard_\|WideOr16\~6) (DELAY (ABSOLUTE - (PORT dataa (1302:1302:1302) (1381:1381:1381)) - (PORT datab (182:182:182) (215:215:215)) - (PORT datac (858:858:858) (889:889:889)) - (PORT datad (486:486:486) (471:471:471)) + (PORT dataa (955:955:955) (1031:1031:1031)) + (PORT datab (184:184:184) (217:217:217)) + (PORT datac (878:878:878) (942:942:942)) + (PORT datad (335:335:335) (347:347:347)) (IOPATH dataa combout (300:300:300) (323:323:323)) (IOPATH datab combout (306:306:306) (324:324:324)) (IOPATH datac combout (218:218:218) (216:216:216)) @@ -37705,14 +30830,30 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~46) + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~43) (DELAY (ABSOLUTE - (PORT dataa (352:352:352) (358:358:358)) - (PORT datab (248:248:248) (320:320:320)) - (PORT datad (555:555:555) (562:562:562)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) + (PORT dataa (464:464:464) (518:518:518)) + (PORT datab (286:286:286) (367:367:367)) + (PORT datac (416:416:416) (497:497:497)) + (PORT datad (1103:1103:1103) (1125:1125:1125)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~44) + (DELAY + (ABSOLUTE + (PORT dataa (384:384:384) (398:398:398)) + (PORT datab (570:570:570) (584:584:584)) + (PORT datad (1003:1003:1003) (1021:1021:1021)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -37723,9 +30864,9 @@ (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]) (DELAY (ABSOLUTE - (PORT clk (1351:1351:1351) (1369:1369:1369)) + (PORT clk (1340:1340:1340) (1358:1358:1358)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1396:1396:1396) (1377:1377:1377)) + (PORT clrn (1383:1383:1383) (1362:1362:1362)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -37736,109 +30877,45 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~31) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[15\]\~15) (DELAY (ABSOLUTE - (PORT dataa (1286:1286:1286) (1286:1286:1286)) - (PORT datab (382:382:382) (420:420:420)) - (PORT datac (1267:1267:1267) (1269:1269:1269)) - (PORT datad (539:539:539) (559:559:559)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (729:729:729) (723:723:723)) - (PORT datab (3109:3109:3109) (3117:3117:3117)) - (PORT datac (155:155:155) (186:186:186)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (1571:1571:1571) (1565:1565:1565)) - (PORT datab (1140:1140:1140) (1173:1173:1173)) - (PORT datac (587:587:587) (604:604:604)) - (PORT datad (1059:1059:1059) (1058:1058:1058)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (1399:1399:1399) (1419:1419:1419)) - (PORT datab (1141:1141:1141) (1174:1174:1174)) - (PORT datac (155:155:155) (185:185:185)) - (PORT datad (1149:1149:1149) (1213:1213:1213)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[1\]) - (DELAY - (ABSOLUTE - (PORT dataa (898:898:898) (945:945:945)) - (PORT datab (598:598:598) (605:605:605)) - (PORT datac (212:212:212) (262:262:262)) - (PORT datad (1541:1541:1541) (1544:1544:1544)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT dataa (1324:1324:1324) (1337:1337:1337)) + (PORT datab (180:180:180) (213:213:213)) + (PORT datad (177:177:177) (199:199:199)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[1\]) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[15\]) (DELAY (ABSOLUTE - (PORT clk (1347:1347:1347) (1358:1358:1358)) + (PORT clk (1343:1343:1343) (1354:1354:1354)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (763:763:763) (771:771:771)) + (PORT asdata (650:650:650) (697:697:697)) + (PORT sload (1864:1864:1864) (1899:1899:1899)) + (PORT ena (2103:2103:2103) (2034:2034:2034)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) (TIMINGCHECK (HOLD d (posedge clk) (144:144:144)) + (HOLD sload (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) (HOLD ena (posedge clk) (144:144:144)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[1\]\~10) + (INSTANCE z80_\|address_pins_\|abus\[15\]\~22) (DELAY (ABSOLUTE - (PORT datab (846:846:846) (848:848:848)) - (PORT datac (872:872:872) (898:898:898)) - (PORT datad (200:200:200) (230:230:230)) - (IOPATH datab combout (275:275:275) (275:275:275)) + (PORT datac (2549:2549:2549) (2609:2609:2609)) + (PORT datad (1311:1311:1311) (1320:1320:1320)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -37846,938 +30923,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[1\]\~11) + (INSTANCE D\[1\]\~29) (DELAY (ABSOLUTE - (PORT dataa (228:228:228) (279:279:279)) - (PORT datab (656:656:656) (683:683:683)) - (PORT datac (154:154:154) (184:184:184)) - (PORT datad (188:188:188) (217:217:217)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|ir_\|opcode\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (178:178:178) (199:199:199)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1343:1343:1343) (1360:1360:1360)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1395:1395:1395) (1367:1367:1367)) - (PORT ena (1130:1130:1130) (1103:1103:1103)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal40\~0) - (DELAY - (ABSOLUTE - (PORT dataa (257:257:257) (345:345:345)) - (PORT datac (836:836:836) (862:862:862)) - (PORT datad (853:853:853) (877:877:877)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal21\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1308:1308:1308) (1362:1362:1362)) - (PORT datab (817:817:817) (820:820:820)) - (PORT datac (843:843:843) (887:887:887)) - (PORT datad (792:792:792) (800:800:800)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~26) - (DELAY - (ABSOLUTE - (PORT dataa (1453:1453:1453) (1518:1518:1518)) - (PORT datab (2173:2173:2173) (2172:2172:2172)) - (PORT datac (613:613:613) (644:644:644)) - (PORT datad (2549:2549:2549) (2541:2541:2541)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~28) - (DELAY - (ABSOLUTE - (PORT dataa (189:189:189) (228:228:228)) - (PORT datab (207:207:207) (255:255:255)) - (PORT datac (174:174:174) (213:213:213)) - (PORT datad (348:348:348) (354:354:354)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~3) - (DELAY - (ABSOLUTE - (PORT dataa (584:584:584) (576:576:576)) - (PORT datab (395:395:395) (417:417:417)) - (PORT datac (511:511:511) (505:505:505)) - (PORT datad (1080:1080:1080) (1089:1089:1089)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1376:1376:1376) (1411:1411:1411)) - (PORT datab (409:409:409) (421:421:421)) - (PORT datac (858:858:858) (881:881:881)) - (PORT datad (191:191:191) (220:220:220)) - (IOPATH dataa combout (307:307:307) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~5) - (DELAY - (ABSOLUTE - (PORT dataa (897:897:897) (927:927:927)) - (PORT datab (1034:1034:1034) (1042:1042:1042)) - (PORT datac (1148:1148:1148) (1192:1192:1192)) - (PORT datad (1252:1252:1252) (1251:1251:1251)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1017:1017:1017) (1011:1011:1011)) - (PORT datab (888:888:888) (937:937:937)) - (PORT datac (1150:1150:1150) (1193:1193:1193)) - (PORT datad (1112:1112:1112) (1148:1148:1148)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1399:1399:1399) (1353:1353:1353)) - (PORT datab (180:180:180) (212:212:212)) - (PORT datac (796:796:796) (768:768:768)) - (PORT datad (160:160:160) (182:182:182)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1484:1484:1484) (1470:1470:1470)) - (PORT datab (771:771:771) (770:770:770)) - (PORT datad (963:963:963) (922:922:922)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1446:1446:1446) (1433:1433:1433)) - (PORT datab (180:180:180) (213:213:213)) - (PORT datac (596:596:596) (611:611:611)) - (PORT datad (514:514:514) (514:514:514)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~9) - (DELAY - (ABSOLUTE - (PORT dataa (576:576:576) (594:594:594)) - (PORT datab (519:519:519) (506:506:506)) - (PORT datac (175:175:175) (207:207:207)) - (PORT datad (349:349:349) (349:349:349)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~21) - (DELAY - (ABSOLUTE - (PORT dataa (2085:2085:2085) (2088:2088:2088)) - (PORT datab (1436:1436:1436) (1471:1471:1471)) - (PORT datac (826:826:826) (842:842:842)) - (PORT datad (1068:1068:1068) (1049:1049:1049)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~12) - (DELAY - (ABSOLUTE - (PORT datab (205:205:205) (250:250:250)) - (PORT datac (317:317:317) (325:325:325)) - (PORT datad (346:346:346) (349:349:349)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1182:1182:1182) (1228:1228:1228)) - (PORT datab (862:862:862) (890:890:890)) - (PORT datac (1793:1793:1793) (1848:1848:1848)) - (PORT datad (1891:1891:1891) (1998:1998:1998)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~11) - (DELAY - (ABSOLUTE - (PORT dataa (793:793:793) (807:807:807)) - (PORT datab (206:206:206) (250:250:250)) - (PORT datac (175:175:175) (215:215:215)) - (PORT datad (347:347:347) (349:349:349)) - (IOPATH dataa combout (307:307:307) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1074:1074:1074) (1056:1056:1056)) - (PORT datab (181:181:181) (215:215:215)) - (PORT datac (157:157:157) (188:188:188)) - (PORT datad (161:161:161) (182:182:182)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~17) - (DELAY - (ABSOLUTE - (PORT dataa (190:190:190) (231:231:231)) - (PORT datab (199:199:199) (241:241:241)) - (PORT datac (180:180:180) (213:213:213)) - (PORT datad (202:202:202) (226:226:226)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~32) - (DELAY - (ABSOLUTE - (PORT dataa (1784:1784:1784) (1819:1819:1819)) - (PORT datab (2405:2405:2405) (2428:2428:2428)) - (PORT datad (1328:1328:1328) (1372:1372:1372)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~15) - (DELAY - (ABSOLUTE - (PORT dataa (616:616:616) (643:643:643)) - (PORT datab (640:640:640) (670:670:670)) - (PORT datac (1015:1015:1015) (996:996:996)) - (PORT datad (595:595:595) (619:619:619)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~16) - (DELAY - (ABSOLUTE - (PORT dataa (190:190:190) (229:229:229)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (567:567:567) (559:559:559)) - (PORT datad (727:727:727) (716:716:716)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~18) - (DELAY - (ABSOLUTE - (PORT dataa (788:788:788) (790:790:790)) - (PORT datab (309:309:309) (327:327:327)) - (PORT datac (348:348:348) (352:352:352)) - (PORT datad (565:565:565) (566:566:566)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1673:1673:1673) (1700:1700:1700)) - (PORT datab (850:850:850) (888:888:888)) - (PORT datac (842:842:842) (887:887:887)) - (PORT datad (395:395:395) (415:415:415)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (857:857:857) (859:859:859)) - (PORT datac (837:837:837) (829:829:829)) - (PORT datad (1282:1282:1282) (1295:1295:1295)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~1) - (DELAY - (ABSOLUTE - (PORT dataa (387:387:387) (399:399:399)) - (PORT datac (173:173:173) (204:204:204)) - (PORT datad (159:159:159) (181:181:181)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1072:1072:1072) (1102:1102:1102)) - (PORT datab (180:180:180) (213:213:213)) - (PORT datac (554:554:554) (559:559:559)) - (PORT datad (340:340:340) (356:356:356)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1073:1073:1073) (1100:1100:1100)) - (PORT datab (180:180:180) (212:212:212)) - (PORT datad (807:807:807) (826:826:826)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2) - (DELAY - (ABSOLUTE - (PORT clk (1332:1332:1332) (1350:1350:1350)) - (PORT d (67:67:67) (78:78:78)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~10) - (DELAY - (ABSOLUTE - (PORT dataa (2259:2259:2259) (2263:2263:2263)) - (PORT datab (1492:1492:1492) (1553:1553:1553)) - (PORT datac (1648:1648:1648) (1714:1714:1714)) - (PORT datad (1531:1531:1531) (1547:1547:1547)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1324:1324:1324) (1370:1370:1370)) - (PORT datab (181:181:181) (212:212:212)) - (PORT datac (970:970:970) (992:992:992)) - (PORT datad (1241:1241:1241) (1202:1202:1202)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1036:1036:1036) (1128:1128:1128)) - (PORT datac (822:822:822) (852:852:852)) - (PORT datad (882:882:882) (922:922:922)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~9) - (DELAY - (ABSOLUTE - (PORT dataa (841:841:841) (841:841:841)) - (PORT datab (867:867:867) (913:913:913)) - (PORT datac (549:549:549) (540:540:540)) - (PORT datad (502:502:502) (480:480:480)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~12) - (DELAY - (ABSOLUTE - (PORT dataa (184:184:184) (221:221:221)) - (PORT datab (783:783:783) (768:768:768)) - (PORT datac (154:154:154) (184:184:184)) - (PORT datad (175:175:175) (205:205:205)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1073:1073:1073) (1121:1121:1121)) - (PORT datab (233:233:233) (308:308:308)) - (PORT datac (194:194:194) (260:260:260)) - (PORT datad (540:540:540) (539:539:539)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~20) - (DELAY - (ABSOLUTE - (PORT dataa (538:538:538) (531:531:531)) - (PORT datab (183:183:183) (216:216:216)) - (PORT datac (550:550:550) (563:563:563)) - (PORT datad (561:561:561) (538:538:538)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1449:1449:1449) (1544:1544:1544)) - (PORT datab (2385:2385:2385) (2384:2384:2384)) - (PORT datac (987:987:987) (972:972:972)) - (PORT datad (794:794:794) (809:809:809)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1016:1016:1016) (1000:1000:1000)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (1096:1096:1096) (1117:1117:1117)) - (PORT datad (524:524:524) (510:510:510)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~5) - (DELAY - (ABSOLUTE - (PORT dataa (840:840:840) (823:823:823)) - (PORT datab (200:200:200) (234:234:234)) - (PORT datac (210:210:210) (251:251:251)) - (PORT datad (551:551:551) (547:547:547)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~6) - (DELAY - (ABSOLUTE - (PORT dataa (877:877:877) (913:913:913)) - (PORT datab (236:236:236) (278:278:278)) - (PORT datac (1287:1287:1287) (1301:1301:1301)) - (PORT datad (160:160:160) (182:182:182)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~7) - (DELAY - (ABSOLUTE - (PORT dataa (854:854:854) (851:851:851)) - (PORT datab (1045:1045:1045) (1074:1074:1074)) - (PORT datac (818:818:818) (827:827:827)) - (PORT datad (937:937:937) (906:906:906)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_set\~0) - (DELAY - (ABSOLUTE - (PORT dataa (441:441:441) (457:457:457)) - (PORT datab (831:831:831) (816:816:816)) - (PORT datac (841:841:841) (886:886:886)) - (PORT datad (374:374:374) (385:385:385)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~4) - (DELAY - (ABSOLUTE - (PORT datab (983:983:983) (967:967:967)) - (PORT datac (187:187:187) (227:227:227)) - (PORT datad (190:190:190) (217:217:217)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~9) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (483:483:483) (492:492:492)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|flags_cf) - (DELAY - (ABSOLUTE - (PORT dataa (181:181:181) (216:216:216)) - (PORT datab (550:550:550) (547:547:547)) - (PORT datac (155:155:155) (186:186:186)) - (PORT datad (531:531:531) (513:513:513)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[0\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (630:630:630) (657:657:657)) - (PORT datab (601:601:601) (632:632:632)) - (PORT datac (822:822:822) (816:816:816)) - (PORT datad (826:826:826) (831:831:831)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sw2_\|db_up\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT datac (1067:1067:1067) (1074:1074:1074)) - (PORT datad (577:577:577) (571:571:571)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[0\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (355:355:355) (363:363:363)) - (PORT datab (603:603:603) (604:604:604)) - (PORT datac (807:807:807) (813:813:813)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[0\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (655:655:655) (647:647:647)) - (PORT datab (880:880:880) (876:876:876)) - (PORT datac (157:157:157) (188:188:188)) - (PORT datad (193:193:193) (226:226:226)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~67) - (DELAY - (ABSOLUTE - (PORT dataa (632:632:632) (686:686:686)) - (PORT datac (1028:1028:1028) (1027:1027:1027)) - (PORT datad (680:680:680) (743:743:743)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~81) - (DELAY - (ABSOLUTE - (PORT dataa (706:706:706) (771:771:771)) - (PORT datab (665:665:665) (720:720:720)) - (PORT datac (1028:1028:1028) (1028:1028:1028)) - (PORT datad (653:653:653) (704:704:704)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~82) - (DELAY - (ABSOLUTE - (PORT dataa (184:184:184) (222:222:222)) - (PORT datab (837:837:837) (875:875:875)) - (PORT datac (1028:1028:1028) (1028:1028:1028)) - (PORT datad (313:313:313) (315:315:315)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~83) - (DELAY - (ABSOLUTE - (PORT dataa (194:194:194) (237:237:237)) - (PORT datab (183:183:183) (216:216:216)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1370:1370:1370)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1397:1397:1397) (1378:1378:1378)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~84) - (DELAY - (ABSOLUTE - (PORT dataa (673:673:673) (717:717:717)) - (PORT datab (908:908:908) (950:950:950)) - (PORT datac (664:664:664) (735:735:735)) - (PORT datad (679:679:679) (744:744:744)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~85) - (DELAY - (ABSOLUTE - (PORT dataa (729:729:729) (811:811:811)) - (PORT datab (672:672:672) (736:736:736)) - (PORT datac (658:658:658) (726:726:726)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~86) - (DELAY - (ABSOLUTE - (PORT dataa (328:328:328) (345:345:345)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datad (315:315:315) (314:314:314)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1354:1354:1354) (1371:1371:1371)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1399:1399:1399) (1379:1379:1379)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~49) - (DELAY - (ABSOLUTE - (PORT dataa (1075:1075:1075) (1095:1095:1095)) - (PORT datab (670:670:670) (717:717:717)) - (PORT datac (194:194:194) (261:261:261)) - (PORT datad (513:513:513) (512:512:512)) + (PORT dataa (1278:1278:1278) (1367:1367:1367)) + (PORT datab (814:814:814) (827:827:827)) + (PORT datac (601:601:601) (642:642:642)) + (PORT datad (554:554:554) (555:555:555)) (IOPATH dataa combout (300:300:300) (323:323:323)) (IOPATH datab combout (309:309:309) (328:328:328)) (IOPATH datac combout (218:218:218) (215:215:215)) @@ -38787,1987 +30939,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr4\~0) + (INSTANCE D\[1\]\~30) (DELAY (ABSOLUTE - (PORT dataa (870:870:870) (905:905:905)) - (PORT datab (714:714:714) (780:780:780)) - (PORT datac (1248:1248:1248) (1310:1310:1310)) - (PORT datad (1100:1100:1100) (1121:1121:1121)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\~76) - (DELAY - (ABSOLUTE - (PORT dataa (323:323:323) (337:337:337)) - (PORT datab (256:256:256) (326:326:326)) - (PORT datac (861:861:861) (853:853:853)) - (PORT datad (1380:1380:1380) (1419:1419:1419)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~73) - (DELAY - (ABSOLUTE - (PORT datac (680:680:680) (749:749:749)) - (PORT datad (1100:1100:1100) (1125:1125:1125)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~47) - (DELAY - (ABSOLUTE - (PORT dataa (703:703:703) (772:772:772)) - (PORT datab (668:668:668) (725:725:725)) - (PORT datac (808:808:808) (845:845:845)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (696:696:696) (748:748:748)) - (PORT datab (1393:1393:1393) (1427:1427:1427)) - (PORT datac (841:841:841) (877:877:877)) - (PORT datad (794:794:794) (812:812:812)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\~74) - (DELAY - (ABSOLUTE - (PORT dataa (547:547:547) (552:552:552)) - (PORT datab (320:320:320) (328:328:328)) - (PORT datac (1249:1249:1249) (1304:1304:1304)) - (PORT datad (1423:1423:1423) (1456:1456:1456)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~75) - (DELAY - (ABSOLUTE - (PORT dataa (185:185:185) (221:221:221)) - (PORT datab (184:184:184) (218:218:218)) - (PORT datac (407:407:407) (460:460:460)) - (PORT datad (782:782:782) (772:772:772)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~77) - (DELAY - (ABSOLUTE - (PORT dataa (527:527:527) (507:507:507)) - (PORT datab (311:311:311) (328:328:328)) - (PORT datad (678:678:678) (741:741:741)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1370:1370:1370)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1397:1397:1397) (1378:1378:1378)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]\~71) - (DELAY - (ABSOLUTE - (PORT dataa (698:698:698) (765:765:765)) - (PORT datab (673:673:673) (738:738:738)) - (PORT datac (304:304:304) (328:328:328)) - (PORT datad (1044:1044:1044) (1061:1061:1061)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]\~72) - (DELAY - (ABSOLUTE - (PORT datab (183:183:183) (216:216:216)) - (PORT datad (662:662:662) (728:728:728)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1370:1370:1370)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1378:1378:1378)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~47) - (DELAY - (ABSOLUTE - (PORT dataa (361:361:361) (406:406:406)) - (PORT datab (1045:1045:1045) (1066:1066:1066)) - (PORT datac (590:590:590) (619:619:619)) - (PORT datad (581:581:581) (606:606:606)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[0\]\~80) - (DELAY - (ABSOLUTE - (PORT dataa (1438:1438:1438) (1484:1484:1484)) - (PORT datab (907:907:907) (923:923:923)) - (PORT datad (482:482:482) (467:467:467)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1370:1370:1370)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1397:1397:1397) (1378:1378:1378)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]\~78) - (DELAY - (ABSOLUTE - (PORT dataa (435:435:435) (501:501:501)) - (PORT datac (561:561:561) (596:596:596)) - (PORT datad (237:237:237) (299:299:299)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]\~79) - (DELAY - (ABSOLUTE - (PORT dataa (375:375:375) (380:380:380)) - (PORT datab (785:785:785) (759:759:759)) - (PORT datad (676:676:676) (737:737:737)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1370:1370:1370)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1397:1397:1397) (1378:1378:1378)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|key_row\~1) - (DELAY - (ABSOLUTE - (PORT datab (1378:1378:1378) (1422:1422:1422)) - (PORT datac (321:321:321) (369:369:369)) - (PORT datad (844:844:844) (870:870:870)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~48) - (DELAY - (ABSOLUTE - (PORT dataa (184:184:184) (221:221:221)) - (PORT datab (201:201:201) (235:235:235)) - (PORT datac (194:194:194) (261:261:261)) - (PORT datad (157:157:157) (178:178:178)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|shifted\~1) - (DELAY - (ABSOLUTE - (PORT datac (985:985:985) (1045:1045:1045)) - (PORT datad (950:950:950) (998:998:998)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~90) - (DELAY - (ABSOLUTE - (PORT dataa (1296:1296:1296) (1372:1372:1372)) - (PORT datab (724:724:724) (795:795:795)) - (PORT datac (883:883:883) (919:919:919)) - (PORT datad (704:704:704) (784:784:784)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~91) - (DELAY - (ABSOLUTE - (PORT dataa (191:191:191) (231:231:231)) - (PORT datab (620:620:620) (630:630:630)) - (PORT datac (562:562:562) (552:552:552)) - (PORT datad (828:828:828) (861:861:861)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~92) - (DELAY - (ABSOLUTE - (PORT datab (889:889:889) (937:937:937)) - (PORT datad (161:161:161) (182:182:182)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1370:1370:1370)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1378:1378:1378)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~63) - (DELAY - (ABSOLUTE - (PORT datac (595:595:595) (633:633:633)) - (PORT datad (586:586:586) (621:621:621)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr16\~3) - (DELAY - (ABSOLUTE - (PORT datab (606:606:606) (639:639:639)) - (PORT datac (625:625:625) (684:684:684)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~87) - (DELAY - (ABSOLUTE - (PORT dataa (192:192:192) (233:233:233)) - (PORT datab (443:443:443) (484:484:484)) - (PORT datac (592:592:592) (619:619:619)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~132) - (DELAY - (ABSOLUTE - (PORT dataa (209:209:209) (250:250:250)) - (PORT datab (607:607:607) (657:657:657)) - (PORT datad (604:604:604) (646:646:646)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~88) - (DELAY - (ABSOLUTE - (PORT dataa (795:795:795) (829:829:829)) - (PORT datab (203:203:203) (237:237:237)) - (PORT datac (314:314:314) (325:325:325)) - (PORT datad (504:504:504) (497:497:497)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~89) - (DELAY - (ABSOLUTE - (PORT dataa (752:752:752) (731:731:731)) - (PORT datad (871:871:871) (888:888:888)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1370:1370:1370)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1397:1397:1397) (1378:1378:1378)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~50) - (DELAY - (ABSOLUTE - (PORT dataa (1287:1287:1287) (1283:1283:1283)) - (PORT datab (555:555:555) (582:582:582)) - (PORT datac (1267:1267:1267) (1266:1266:1266)) - (PORT datad (199:199:199) (256:256:256)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~51) - (DELAY - (ABSOLUTE - (PORT dataa (723:723:723) (722:722:722)) - (PORT datab (3110:3110:3110) (3118:3118:3118)) - (PORT datac (155:155:155) (186:186:186)) - (PORT datad (160:160:160) (182:182:182)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (827:827:827) (822:822:822)) - (PORT clk (1646:1646:1646) (1674:1674:1674)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1142:1142:1142) (1152:1152:1152)) - (PORT d[1] (912:912:912) (937:937:937)) - (PORT d[2] (890:890:890) (884:884:884)) - (PORT d[3] (943:943:943) (966:966:966)) - (PORT d[4] (2421:2421:2421) (2524:2524:2524)) - (PORT d[5] (955:955:955) (960:960:960)) - (PORT d[6] (919:919:919) (944:944:944)) - (PORT d[7] (883:883:883) (901:901:901)) - (PORT d[8] (969:969:969) (983:983:983)) - (PORT d[9] (923:923:923) (948:948:948)) - (PORT d[10] (973:973:973) (1007:1007:1007)) - (PORT d[11] (2392:2392:2392) (2487:2487:2487)) - (PORT d[12] (1206:1206:1206) (1236:1236:1236)) - (PORT clk (1643:1643:1643) (1672:1672:1672)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (871:871:871) (835:835:835)) - (PORT clk (1643:1643:1643) (1672:1672:1672)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1646:1646:1646) (1674:1674:1674)) - (PORT d[0] (1334:1334:1334) (1304:1304:1304)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1675:1675:1675)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1675:1675:1675)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1675:1675:1675)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1675:1675:1675)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1610:1610:1610) (1638:1638:1638)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (881:881:881) (885:885:885)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (886:886:886)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (886:886:886)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (886:886:886)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (905:905:905) (887:887:887)) - (PORT clk (1646:1646:1646) (1673:1673:1673)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (655:655:655) (654:654:654)) - (PORT d[1] (2216:2216:2216) (2370:2370:2370)) - (PORT d[2] (1386:1386:1386) (1401:1401:1401)) - (PORT d[3] (909:909:909) (925:925:925)) - (PORT d[4] (2407:2407:2407) (2520:2520:2520)) - (PORT d[5] (3216:3216:3216) (3328:3328:3328)) - (PORT d[6] (1174:1174:1174) (1189:1189:1189)) - (PORT d[7] (2944:2944:2944) (2982:2982:2982)) - (PORT d[8] (644:644:644) (645:645:645)) - (PORT d[9] (1480:1480:1480) (1519:1519:1519)) - (PORT d[10] (1247:1247:1247) (1289:1289:1289)) - (PORT d[11] (2074:2074:2074) (2159:2159:2159)) - (PORT d[12] (1446:1446:1446) (1472:1472:1472)) - (PORT clk (1643:1643:1643) (1671:1671:1671)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (612:612:612) (573:573:573)) - (PORT clk (1643:1643:1643) (1671:1671:1671)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1646:1646:1646) (1673:1673:1673)) - (PORT d[0] (1332:1332:1332) (1279:1279:1279)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1674:1674:1674)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1674:1674:1674)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1674:1674:1674)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1674:1674:1674)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1610:1610:1610) (1637:1637:1637)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (881:881:881) (884:884:884)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (885:885:885)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (885:885:885)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (885:885:885)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1018:1018:1018) (1000:1000:1000)) - (PORT clk (1645:1645:1645) (1672:1672:1672)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (908:908:908) (912:912:912)) - (PORT d[1] (3190:3190:3190) (3345:3345:3345)) - (PORT d[2] (1153:1153:1153) (1157:1157:1157)) - (PORT d[3] (1182:1182:1182) (1204:1204:1204)) - (PORT d[4] (2395:2395:2395) (2506:2506:2506)) - (PORT d[5] (3231:3231:3231) (3348:3348:3348)) - (PORT d[6] (1217:1217:1217) (1267:1267:1267)) - (PORT d[7] (1126:1126:1126) (1137:1137:1137)) - (PORT d[8] (929:929:929) (929:929:929)) - (PORT d[9] (1442:1442:1442) (1473:1473:1473)) - (PORT d[10] (1257:1257:1257) (1304:1304:1304)) - (PORT d[11] (2094:2094:2094) (2179:2179:2179)) - (PORT d[12] (1480:1480:1480) (1518:1518:1518)) - (PORT clk (1642:1642:1642) (1670:1670:1670)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (881:881:881) (829:829:829)) - (PORT clk (1642:1642:1642) (1670:1670:1670)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1645:1645:1645) (1672:1672:1672)) - (PORT d[0] (1526:1526:1526) (1472:1472:1472)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1646:1646:1646) (1673:1673:1673)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1646:1646:1646) (1673:1673:1673)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1646:1646:1646) (1673:1673:1673)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1646:1646:1646) (1673:1673:1673)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1609:1609:1609) (1636:1636:1636)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (880:880:880) (883:883:883)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (881:881:881) (884:884:884)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (881:881:881) (884:884:884)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (881:881:881) (884:884:884)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~55) - (DELAY - (ABSOLUTE - (PORT dataa (353:353:353) (362:362:362)) - (PORT datab (624:624:624) (664:664:664)) - (PORT datac (603:603:603) (641:641:641)) - (PORT datad (598:598:598) (583:583:583)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (285:285:285)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1105:1105:1105) (1088:1088:1088)) - (PORT clk (1637:1637:1637) (1665:1665:1665)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3379:3379:3379) (3446:3446:3446)) - (PORT d[1] (1268:1268:1268) (1347:1347:1347)) - (PORT d[2] (1861:1861:1861) (1882:1882:1882)) - (PORT d[3] (2267:2267:2267) (2330:2330:2330)) - (PORT d[4] (2046:2046:2046) (2106:2106:2106)) - (PORT d[5] (1246:1246:1246) (1306:1306:1306)) - (PORT d[6] (1355:1355:1355) (1373:1373:1373)) - (PORT d[7] (3098:3098:3098) (3120:3120:3120)) - (PORT d[8] (3347:3347:3347) (3464:3464:3464)) - (PORT d[9] (2928:2928:2928) (2995:2995:2995)) - (PORT d[10] (2921:2921:2921) (2980:2980:2980)) - (PORT d[11] (1660:1660:1660) (1694:1694:1694)) - (PORT d[12] (1319:1319:1319) (1343:1343:1343)) - (PORT clk (1634:1634:1634) (1663:1663:1663)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1505:1505:1505) (1437:1437:1437)) - (PORT clk (1634:1634:1634) (1663:1663:1663)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1637:1637:1637) (1665:1665:1665)) - (PORT d[0] (2529:2529:2529) (2495:2495:2495)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1638:1638:1638) (1666:1666:1666)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1638:1638:1638) (1666:1666:1666)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1638:1638:1638) (1666:1666:1666)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1638:1638:1638) (1666:1666:1666)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1601:1601:1601) (1629:1629:1629)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (872:872:872) (876:876:876)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (873:873:873) (877:877:877)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (873:873:873) (877:877:877)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (873:873:873) (877:877:877)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~56) - (DELAY - (ABSOLUTE - (PORT dataa (981:981:981) (936:936:936)) - (PORT datab (1299:1299:1299) (1349:1349:1349)) - (PORT datac (502:502:502) (483:483:483)) - (PORT datad (1089:1089:1089) (1062:1062:1062)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1522:1522:1522) (1552:1552:1552)) - (PORT clk (1643:1643:1643) (1671:1671:1671)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2671:2671:2671) (2689:2689:2689)) - (PORT d[1] (1867:1867:1867) (1957:1957:1957)) - (PORT d[2] (1810:1810:1810) (1839:1839:1839)) - (PORT d[3] (1758:1758:1758) (1816:1816:1816)) - (PORT d[4] (2803:2803:2803) (2841:2841:2841)) - (PORT d[5] (2060:2060:2060) (2153:2153:2153)) - (PORT d[6] (1591:1591:1591) (1614:1614:1614)) - (PORT d[7] (1980:1980:1980) (2023:2023:2023)) - (PORT d[8] (2256:2256:2256) (2327:2327:2327)) - (PORT d[9] (1564:1564:1564) (1597:1597:1597)) - (PORT d[10] (1345:1345:1345) (1361:1361:1361)) - (PORT d[11] (1607:1607:1607) (1625:1625:1625)) - (PORT d[12] (2124:2124:2124) (2140:2140:2140)) - (PORT clk (1640:1640:1640) (1669:1669:1669)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2368:2368:2368) (2344:2344:2344)) - (PORT clk (1640:1640:1640) (1669:1669:1669)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1643:1643:1643) (1671:1671:1671)) - (PORT d[0] (3338:3338:3338) (3343:3343:3343)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1644:1644:1644) (1672:1672:1672)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1644:1644:1644) (1672:1672:1672)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1644:1644:1644) (1672:1672:1672)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1644:1644:1644) (1672:1672:1672)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1602:1602:1602) (1601:1601:1601)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1885:1885:1885) (1823:1823:1823)) - (PORT clk (1610:1610:1610) (1608:1608:1608)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4094:4094:4094) (4004:4004:4004)) - (PORT d[1] (3872:3872:3872) (3773:3773:3773)) - (PORT d[2] (3969:3969:3969) (3885:3885:3885)) - (PORT d[3] (4229:4229:4229) (4158:4158:4158)) - (PORT d[4] (4027:4027:4027) (3879:3879:3879)) - (PORT d[5] (4301:4301:4301) (4209:4209:4209)) - (PORT d[6] (4101:4101:4101) (4071:4071:4071)) - (PORT d[7] (4030:4030:4030) (3869:3869:3869)) - (PORT d[8] (4251:4251:4251) (4163:4163:4163)) - (PORT d[9] (4115:4115:4115) (4191:4191:4191)) - (PORT d[10] (4389:4389:4389) (4323:4323:4323)) - (PORT d[11] (4066:4066:4066) (3954:3954:3954)) - (PORT d[12] (4192:4192:4192) (4207:4207:4207)) - (PORT clk (1607:1607:1607) (1605:1605:1605)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1610:1610:1610) (1608:1608:1608)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1611:1611:1611) (1609:1609:1609)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1611:1611:1611) (1609:1609:1609)) - (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1611:1611:1611) (1609:1609:1609)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1611:1611:1611) (1609:1609:1609)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1603:1603:1603) (1602:1602:1602)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2638:2638:2638) (2644:2644:2644)) - (PORT d[1] (1609:1609:1609) (1700:1700:1700)) - (PORT d[2] (1788:1788:1788) (1834:1834:1834)) - (PORT d[3] (1753:1753:1753) (1800:1800:1800)) - (PORT d[4] (2573:2573:2573) (2629:2629:2629)) - (PORT d[5] (2062:2062:2062) (2159:2159:2159)) - (PORT d[6] (1861:1861:1861) (1879:1879:1879)) - (PORT d[7] (1974:1974:1974) (2042:2042:2042)) - (PORT d[8] (2218:2218:2218) (2298:2298:2298)) - (PORT d[9] (1820:1820:1820) (1861:1861:1861)) - (PORT d[10] (1844:1844:1844) (1851:1851:1851)) - (PORT d[11] (1877:1877:1877) (1899:1899:1899)) - (PORT d[12] (2378:2378:2378) (2399:2399:2399)) - (PORT clk (1644:1644:1644) (1672:1672:1672)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1644:1644:1644) (1672:1672:1672)) - (PORT d[0] (2530:2530:2530) (2508:2508:2508)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1645:1645:1645) (1673:1673:1673)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1611:1611:1611) (1638:1638:1638)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (885:885:885)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (883:883:883) (886:886:886)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (883:883:883) (886:886:886)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (883:883:883) (886:886:886)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1503:1503:1503) (1531:1531:1531)) - (PORT clk (1641:1641:1641) (1669:1669:1669)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2666:2666:2666) (2687:2687:2687)) - (PORT d[1] (1897:1897:1897) (1996:1996:1996)) - (PORT d[2] (1753:1753:1753) (1779:1779:1779)) - (PORT d[3] (1747:1747:1747) (1800:1800:1800)) - (PORT d[4] (2818:2818:2818) (2858:2858:2858)) - (PORT d[5] (1809:1809:1809) (1901:1901:1901)) - (PORT d[6] (1611:1611:1611) (1617:1617:1617)) - (PORT d[7] (1692:1692:1692) (1718:1718:1718)) - (PORT d[8] (2251:2251:2251) (2328:2328:2328)) - (PORT d[9] (1828:1828:1828) (1861:1861:1861)) - (PORT d[10] (1856:1856:1856) (1882:1882:1882)) - (PORT d[11] (2347:2347:2347) (2365:2365:2365)) - (PORT d[12] (2075:2075:2075) (2105:2105:2105)) - (PORT clk (1638:1638:1638) (1667:1667:1667)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2330:2330:2330) (2279:2279:2279)) - (PORT clk (1638:1638:1638) (1667:1667:1667)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1641:1641:1641) (1669:1669:1669)) - (PORT d[0] (3368:3368:3368) (3356:3356:3356)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1642:1642:1642) (1670:1670:1670)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1642:1642:1642) (1670:1670:1670)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1642:1642:1642) (1670:1670:1670)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1642:1642:1642) (1670:1670:1670)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1600:1600:1600) (1599:1599:1599)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1887:1887:1887) (1819:1819:1819)) - (PORT clk (1608:1608:1608) (1606:1606:1606)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4135:4135:4135) (4045:4045:4045)) - (PORT d[1] (3941:3941:3941) (3838:3838:3838)) - (PORT d[2] (3995:3995:3995) (3898:3898:3898)) - (PORT d[3] (4226:4226:4226) (4152:4152:4152)) - (PORT d[4] (4046:4046:4046) (3907:3907:3907)) - (PORT d[5] (4290:4290:4290) (4190:4190:4190)) - (PORT d[6] (4375:4375:4375) (4339:4339:4339)) - (PORT d[7] (4037:4037:4037) (3866:3866:3866)) - (PORT d[8] (4167:4167:4167) (4039:4039:4039)) - (PORT d[9] (4129:4129:4129) (4216:4216:4216)) - (PORT d[10] (4314:4314:4314) (4238:4238:4238)) - (PORT d[11] (4075:4075:4075) (3952:3952:3952)) - (PORT d[12] (4191:4191:4191) (4206:4206:4206)) - (PORT clk (1605:1605:1605) (1603:1603:1603)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1608:1608:1608) (1606:1606:1606)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1609:1609:1609) (1607:1607:1607)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1609:1609:1609) (1607:1607:1607)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1609:1609:1609) (1607:1607:1607)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1609:1609:1609) (1607:1607:1607)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~52) - (DELAY - (ABSOLUTE - (PORT dataa (1129:1129:1129) (1172:1172:1172)) - (PORT datab (1335:1335:1335) (1318:1318:1318)) - (PORT datac (1047:1047:1047) (1062:1062:1062)) - (PORT datad (1324:1324:1324) (1319:1319:1319)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3372:3372:3372) (3445:3445:3445)) - (PORT d[1] (2443:2443:2443) (2564:2564:2564)) - (PORT d[2] (1520:1520:1520) (1542:1542:1542)) - (PORT d[3] (1998:1998:1998) (2040:2040:2040)) - (PORT d[4] (2014:2014:2014) (2036:2036:2036)) - (PORT d[5] (1537:1537:1537) (1604:1604:1604)) - (PORT d[6] (1058:1058:1058) (1070:1070:1070)) - (PORT d[7] (1084:1084:1084) (1098:1098:1098)) - (PORT d[8] (2012:2012:2012) (2097:2097:2097)) - (PORT d[9] (2103:2103:2103) (2157:2157:2157)) - (PORT d[10] (2374:2374:2374) (2416:2416:2416)) - (PORT d[11] (865:865:865) (853:853:853)) - (PORT d[12] (1628:1628:1628) (1646:1646:1646)) - (PORT clk (1634:1634:1634) (1662:1662:1662)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1634:1634:1634) (1662:1662:1662)) - (PORT d[0] (3098:3098:3098) (3083:3083:3083)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1635:1635:1635) (1663:1663:1663)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1601:1601:1601) (1628:1628:1628)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (872:872:872) (875:875:875)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (873:873:873) (876:876:876)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (873:873:873) (876:876:876)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (873:873:873) (876:876:876)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~53) - (DELAY - (ABSOLUTE - (PORT dataa (1118:1118:1118) (1097:1097:1097)) - (PORT datab (995:995:995) (975:975:975)) - (PORT datac (164:164:164) (198:198:198)) - (PORT datad (1280:1280:1280) (1263:1263:1263)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~54) - (DELAY - (ABSOLUTE - (PORT dataa (1401:1401:1401) (1430:1430:1430)) - (PORT datab (885:885:885) (897:897:897)) - (PORT datac (162:162:162) (196:196:196)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (285:285:285)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~106) - (DELAY - (ABSOLUTE - (PORT dataa (629:629:629) (693:693:693)) - (PORT datab (1093:1093:1093) (1105:1105:1105)) - (PORT datac (157:157:157) (187:187:187)) + (PORT dataa (945:945:945) (981:981:981)) + (PORT datab (340:340:340) (346:346:346)) + (PORT datac (2670:2670:2670) (2799:2799:2799)) (PORT datad (159:159:159) (179:179:179)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~57) - (DELAY - (ABSOLUTE - (PORT dataa (1837:1837:1837) (1832:1832:1832)) - (PORT datab (1053:1053:1053) (1081:1081:1081)) - (PORT datac (162:162:162) (196:196:196)) - (PORT datad (772:772:772) (778:778:778)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~58) - (DELAY - (ABSOLUTE - (PORT dataa (1840:1840:1840) (1833:1833:1833)) - (PORT datab (606:606:606) (628:628:628)) - (PORT datac (156:156:156) (186:186:186)) - (PORT datad (1526:1526:1526) (1471:1471:1471)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[0\]) - (DELAY - (ABSOLUTE - (PORT dataa (906:906:906) (945:945:945)) - (PORT datab (855:855:855) (862:862:862)) - (PORT datac (216:216:216) (266:266:266)) - (PORT datad (1460:1460:1460) (1444:1444:1444)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1347:1347:1347) (1358:1358:1358)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (763:763:763) (771:771:771)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[0\]\~16) - (DELAY - (ABSOLUTE - (PORT datab (359:359:359) (378:378:378)) - (PORT datac (376:376:376) (415:415:415)) - (PORT datad (621:621:621) (623:623:623)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[0\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (904:904:904) (903:903:903)) - (PORT datab (1282:1282:1282) (1230:1230:1230)) - (PORT datac (822:822:822) (840:840:840)) - (PORT datad (825:825:825) (819:819:819)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1341:1341:1341) (1358:1358:1358)) - (PORT asdata (1401:1401:1401) (1394:1394:1394)) - (PORT clrn (1395:1395:1395) (1365:1365:1365)) - (PORT ena (1378:1378:1378) (1338:1338:1338)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal63\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1846:1846:1846) (1909:1909:1909)) - (PORT datab (1410:1410:1410) (1459:1459:1459)) - (PORT datac (201:201:201) (246:246:246)) - (PORT datad (1020:1020:1020) (1031:1031:1031)) (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_daa) + (INSTANCE ExtRamWE\~0) (DELAY (ABSOLUTE - (PORT dataa (1375:1375:1375) (1453:1453:1453)) - (PORT datab (1351:1351:1351) (1420:1420:1420)) - (PORT datac (1699:1699:1699) (1699:1699:1699)) - (PORT datad (370:370:370) (391:391:391)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|SYNTHESIZED_WIRE_2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (327:327:327) (455:455:455)) - (PORT datab (660:660:660) (673:673:673)) - (PORT datac (1335:1335:1335) (1367:1367:1367)) - (PORT datad (1200:1200:1200) (1268:1268:1268)) + (PORT dataa (225:225:225) (277:277:277)) + (PORT datab (2583:2583:2583) (2647:2647:2647)) + (PORT datac (508:508:508) (506:506:506)) + (PORT datad (563:563:563) (564:564:564)) (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datab combout (273:273:273) (275:275:275)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -40775,2469 +30971,374 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~10) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode236w\[2\]) (DELAY (ABSOLUTE - (PORT dataa (622:622:622) (645:645:645)) - (PORT datac (1068:1068:1068) (1072:1072:1072)) - (PORT datad (842:842:842) (842:842:842)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (PORT dataa (1085:1085:1085) (1094:1094:1094)) + (PORT datab (214:214:214) (269:269:269)) + (PORT datac (531:531:531) (525:525:525)) + (PORT datad (1484:1484:1484) (1464:1464:1464)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~11) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|rden_decode\|w_anode284w\[2\]\~0) (DELAY (ABSOLUTE - (PORT dataa (181:181:181) (217:217:217)) - (PORT datab (601:601:601) (632:632:632)) - (PORT datac (807:807:807) (818:818:818)) - (IOPATH dataa combout (318:318:318) (307:307:307)) + (PORT datab (1513:1513:1513) (1581:1581:1581)) + (PORT datac (2377:2377:2377) (2432:2432:2432)) + (PORT datad (2088:2088:2088) (2133:2133:2133)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1160:1160:1160) (1182:1182:1182)) + (PORT datab (314:314:314) (330:330:330)) + (PORT datad (178:178:178) (199:199:199)) + (IOPATH dataa combout (329:329:329) (332:332:332)) (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[4\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (502:502:502) (496:496:496)) - (PORT datab (836:836:836) (845:845:845)) - (PORT datac (545:545:545) (540:540:540)) - (PORT datad (1067:1067:1067) (1073:1073:1073)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[4\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (615:615:615) (605:605:605)) - (PORT datab (879:879:879) (876:876:876)) - (PORT datac (585:585:585) (610:610:610)) - (PORT datad (158:158:158) (178:178:178)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[4\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (839:839:839) (838:838:838)) - (PORT datab (218:218:218) (262:262:262)) - (PORT datac (568:568:568) (598:598:598)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~119) - (DELAY - (ABSOLUTE - (PORT dataa (695:695:695) (761:761:761)) - (PORT datab (666:666:666) (734:734:734)) - (PORT datac (1056:1056:1056) (1114:1114:1114)) - (PORT datad (840:840:840) (880:880:880)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~120) - (DELAY - (ABSOLUTE - (PORT dataa (622:622:622) (643:643:643)) - (PORT datab (321:321:321) (330:330:330)) - (PORT datac (658:658:658) (727:727:727)) - (PORT datad (670:670:670) (741:741:741)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~95) - (DELAY - (ABSOLUTE - (PORT dataa (729:729:729) (811:811:811)) - (PORT datac (645:645:645) (709:709:709)) - (PORT datad (1063:1063:1063) (1109:1109:1109)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~121) - (DELAY - (ABSOLUTE - (PORT dataa (184:184:184) (219:219:219)) - (PORT datad (165:165:165) (189:189:189)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[1\]) (DELAY (ABSOLUTE - (PORT clk (1353:1353:1353) (1371:1371:1371)) + (PORT clk (1354:1354:1354) (1361:1361:1361)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1379:1379:1379)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~117) - (DELAY - (ABSOLUTE - (PORT dataa (406:406:406) (472:472:472)) - (PORT datab (606:606:606) (652:652:652)) - (PORT datad (670:670:670) (705:705:705)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~136) - (DELAY - (ABSOLUTE - (PORT dataa (531:531:531) (520:520:520)) - (PORT datab (419:419:419) (464:464:464)) - (PORT datad (605:605:605) (640:640:640)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~130) - (DELAY - (ABSOLUTE - (PORT dataa (624:624:624) (665:665:665)) - (PORT datab (618:618:618) (627:627:627)) - (PORT datad (770:770:770) (787:787:787)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~118) - (DELAY - (ABSOLUTE - (PORT dataa (731:731:731) (812:812:812)) - (PORT datab (589:589:589) (595:595:595)) - (PORT datad (570:570:570) (566:566:566)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1371:1371:1371)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1379:1379:1379)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~78) - (DELAY - (ABSOLUTE - (PORT dataa (836:836:836) (811:811:811)) - (PORT datab (817:817:817) (808:808:808)) - (PORT datac (568:568:568) (598:598:598)) - (PORT datad (599:599:599) (627:627:627)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~126) - (DELAY - (ABSOLUTE - (PORT dataa (752:752:752) (832:832:832)) - (PORT datab (636:636:636) (659:659:659)) - (PORT datac (882:882:882) (920:920:920)) - (PORT datad (1276:1276:1276) (1339:1339:1339)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~128) - (DELAY - (ABSOLUTE - (PORT dataa (893:893:893) (925:925:925)) - (PORT datab (723:723:723) (794:794:794)) - (PORT datac (826:826:826) (874:874:874)) - (PORT datad (707:707:707) (785:785:785)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~129) - (DELAY - (ABSOLUTE - (PORT dataa (328:328:328) (342:342:342)) - (PORT datab (182:182:182) (215:215:215)) - (PORT datad (839:839:839) (871:871:871)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1371:1371:1371)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1379:1379:1379)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~127) - (DELAY - (ABSOLUTE - (PORT dataa (560:560:560) (564:564:564)) - (PORT datab (885:885:885) (931:931:931)) - (PORT datad (530:530:530) (517:517:517)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1370:1370:1370)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1378:1378:1378)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Equal0\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1470:1470:1470) (1502:1502:1502)) - (PORT datac (684:684:684) (754:754:754)) - (PORT datad (654:654:654) (709:709:709)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~51) - (DELAY - (ABSOLUTE - (PORT dataa (649:649:649) (649:649:649)) - (PORT datab (1142:1142:1142) (1157:1157:1157)) - (PORT datac (845:845:845) (875:875:875)) - (PORT datad (305:305:305) (312:312:312)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~125) - (DELAY - (ABSOLUTE - (PORT dataa (193:193:193) (235:235:235)) - (PORT datab (886:886:886) (933:933:933)) - (PORT datad (329:329:329) (342:342:342)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1370:1370:1370)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1378:1378:1378)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~79) - (DELAY - (ABSOLUTE - (PORT dataa (1249:1249:1249) (1240:1240:1240)) - (PORT datab (1134:1134:1134) (1154:1154:1154)) - (PORT datac (196:196:196) (263:263:263)) - (PORT datad (198:198:198) (256:256:256)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~122) - (DELAY - (ABSOLUTE - (PORT dataa (409:409:409) (474:474:474)) - (PORT datab (603:603:603) (651:651:651)) - (PORT datad (672:672:672) (706:706:706)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~123) - (DELAY - (ABSOLUTE - (PORT dataa (546:546:546) (536:536:536)) - (PORT datab (668:668:668) (733:733:733)) - (PORT datac (1424:1424:1424) (1480:1480:1480)) - (PORT datad (544:544:544) (543:543:543)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~124) - (DELAY - (ABSOLUTE - (PORT dataa (606:606:606) (631:631:631)) - (PORT datab (688:688:688) (759:759:759)) - (PORT datad (160:160:160) (180:180:180)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1370:1370:1370)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1378:1378:1378)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|key_row\~3) - (DELAY - (ABSOLUTE - (PORT datab (1409:1409:1409) (1437:1437:1437)) - (PORT datac (813:813:813) (846:846:846)) - (PORT datad (199:199:199) (256:256:256)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~80) - (DELAY - (ABSOLUTE - (PORT dataa (350:350:350) (405:405:405)) - (PORT datab (580:580:580) (576:576:576)) - (PORT datac (1257:1257:1257) (1255:1255:1255)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~111) - (DELAY - (ABSOLUTE - (PORT dataa (730:730:730) (811:811:811)) - (PORT datac (639:639:639) (702:702:702)) - (PORT datad (1057:1057:1057) (1101:1101:1101)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~97) - (DELAY - (ABSOLUTE - (PORT dataa (1087:1087:1087) (1147:1147:1147)) - (PORT datab (670:670:670) (736:736:736)) - (PORT datac (586:586:586) (610:610:610)) - (PORT datad (836:836:836) (879:879:879)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~116) - (DELAY - (ABSOLUTE - (PORT dataa (358:358:358) (369:369:369)) - (PORT datab (202:202:202) (236:236:236)) - (PORT datad (166:166:166) (193:193:193)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1371:1371:1371)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1379:1379:1379)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]\~115) - (DELAY - (ABSOLUTE - (PORT dataa (545:545:545) (533:533:533)) - (PORT datab (332:332:332) (353:353:353)) - (PORT datad (661:661:661) (725:725:725)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1370:1370:1370)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1378:1378:1378)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~77) - (DELAY - (ABSOLUTE - (PORT dataa (1042:1042:1042) (1038:1038:1038)) - (PORT datab (1066:1066:1066) (1079:1079:1079)) - (PORT datac (590:590:590) (626:626:626)) - (PORT datad (199:199:199) (256:256:256)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~81) - (DELAY - (ABSOLUTE - (PORT dataa (1497:1497:1497) (1479:1479:1479)) - (PORT datab (181:181:181) (213:213:213)) - (PORT datac (157:157:157) (188:188:188)) - (PORT datad (157:157:157) (178:178:178)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3117:3117:3117) (3202:3202:3202)) - (PORT d[1] (1492:1492:1492) (1570:1570:1570)) - (PORT d[2] (2221:2221:2221) (2276:2276:2276)) - (PORT d[3] (1745:1745:1745) (1779:1779:1779)) - (PORT d[4] (1772:1772:1772) (1805:1805:1805)) - (PORT d[5] (1930:1930:1930) (2022:2022:2022)) - (PORT d[6] (2105:2105:2105) (2140:2140:2140)) - (PORT d[7] (2005:2005:2005) (2010:2010:2010)) - (PORT d[8] (2724:2724:2724) (2779:2779:2779)) - (PORT d[9] (2094:2094:2094) (2123:2123:2123)) - (PORT d[10] (3714:3714:3714) (3823:3823:3823)) - (PORT d[11] (1664:1664:1664) (1694:1694:1694)) - (PORT d[12] (2152:2152:2152) (2211:2211:2211)) - (PORT clk (1635:1635:1635) (1664:1664:1664)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1635:1635:1635) (1664:1664:1664)) - (PORT d[0] (2258:2258:2258) (2250:2250:2250)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1636:1636:1636) (1665:1665:1665)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1602:1602:1602) (1630:1630:1630)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (873:873:873) (877:877:877)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (878:878:878)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (878:878:878)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (878:878:878)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1398:1398:1398) (1418:1418:1418)) - (PORT clk (1634:1634:1634) (1662:1662:1662)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3220:3220:3220) (3238:3238:3238)) - (PORT d[1] (1562:1562:1562) (1647:1647:1647)) - (PORT d[2] (1668:1668:1668) (1669:1669:1669)) - (PORT d[3] (1976:1976:1976) (2007:2007:2007)) - (PORT d[4] (2050:2050:2050) (2095:2095:2095)) - (PORT d[5] (1525:1525:1525) (1602:1602:1602)) - (PORT d[6] (1345:1345:1345) (1352:1352:1352)) - (PORT d[7] (1353:1353:1353) (1377:1377:1377)) - (PORT d[8] (2698:2698:2698) (2781:2781:2781)) - (PORT d[9] (2098:2098:2098) (2149:2149:2149)) - (PORT d[10] (2137:2137:2137) (2175:2175:2175)) - (PORT d[11] (1988:1988:1988) (2028:2028:2028)) - (PORT d[12] (1876:1876:1876) (1897:1897:1897)) - (PORT clk (1631:1631:1631) (1660:1660:1660)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2643:2643:2643) (2613:2613:2613)) - (PORT clk (1631:1631:1631) (1660:1660:1660)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1634:1634:1634) (1662:1662:1662)) - (PORT d[0] (3917:3917:3917) (3913:3913:3913)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1635:1635:1635) (1663:1663:1663)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1635:1635:1635) (1663:1663:1663)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1635:1635:1635) (1663:1663:1663)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1635:1635:1635) (1663:1663:1663)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1593:1593:1593) (1592:1592:1592)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1614:1614:1614) (1543:1543:1543)) - (PORT clk (1601:1601:1601) (1599:1599:1599)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4103:4103:4103) (3997:3997:3997)) - (PORT d[1] (3955:3955:3955) (3883:3883:3883)) - (PORT d[2] (4006:4006:4006) (3895:3895:3895)) - (PORT d[3] (4212:4212:4212) (4117:4117:4117)) - (PORT d[4] (4315:4315:4315) (4187:4187:4187)) - (PORT d[5] (4021:4021:4021) (3945:3945:3945)) - (PORT d[6] (4378:4378:4378) (4355:4355:4355)) - (PORT d[7] (3996:3996:3996) (3938:3938:3938)) - (PORT d[8] (4192:4192:4192) (4072:4072:4072)) - (PORT d[9] (4141:4141:4141) (4229:4229:4229)) - (PORT d[10] (4080:4080:4080) (4007:4007:4007)) - (PORT d[11] (4096:4096:4096) (3973:3973:3973)) - (PORT d[12] (4047:4047:4047) (3950:3950:3950)) - (PORT clk (1598:1598:1598) (1596:1596:1596)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1601:1601:1601) (1599:1599:1599)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1602:1602:1602) (1600:1600:1600)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1602:1602:1602) (1600:1600:1600)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1602:1602:1602) (1600:1600:1600)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1602:1602:1602) (1600:1600:1600)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3890:3890:3890) (3959:3959:3959)) - (PORT d[1] (2668:2668:2668) (2802:2802:2802)) - (PORT d[2] (2492:2492:2492) (2533:2533:2533)) - (PORT d[3] (2120:2120:2120) (2205:2205:2205)) - (PORT d[4] (2339:2339:2339) (2426:2426:2426)) - (PORT d[5] (2353:2353:2353) (2440:2440:2440)) - (PORT d[6] (1749:1749:1749) (1794:1794:1794)) - (PORT d[7] (2139:2139:2139) (2164:2164:2164)) - (PORT d[8] (2895:2895:2895) (3020:3020:3020)) - (PORT d[9] (2427:2427:2427) (2496:2496:2496)) - (PORT d[10] (4456:4456:4456) (4549:4549:4549)) - (PORT d[11] (1768:1768:1768) (1835:1835:1835)) - (PORT d[12] (2036:2036:2036) (2099:2099:2099)) - (PORT clk (1642:1642:1642) (1670:1670:1670)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1642:1642:1642) (1670:1670:1670)) - (PORT d[0] (3246:3246:3246) (3296:3296:3296)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1643:1643:1643) (1671:1671:1671)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1609:1609:1609) (1636:1636:1636)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (880:880:880) (883:883:883)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (881:881:881) (884:884:884)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (881:881:881) (884:884:884)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (881:881:881) (884:884:884)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1457:1457:1457) (1477:1477:1477)) - (PORT clk (1635:1635:1635) (1662:1662:1662)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2802:2802:2802) (2864:2864:2864)) - (PORT d[1] (2141:2141:2141) (2242:2242:2242)) - (PORT d[2] (2014:2014:2014) (2042:2042:2042)) - (PORT d[3] (1762:1762:1762) (1815:1815:1815)) - (PORT d[4] (2261:2261:2261) (2299:2299:2299)) - (PORT d[5] (1802:1802:1802) (1892:1892:1892)) - (PORT d[6] (1621:1621:1621) (1629:1629:1629)) - (PORT d[7] (2205:2205:2205) (2254:2254:2254)) - (PORT d[8] (2686:2686:2686) (2758:2758:2758)) - (PORT d[9] (1843:1843:1843) (1889:1889:1889)) - (PORT d[10] (1872:1872:1872) (1913:1913:1913)) - (PORT d[11] (2261:2261:2261) (2308:2308:2308)) - (PORT d[12] (2373:2373:2373) (2396:2396:2396)) - (PORT clk (1632:1632:1632) (1660:1660:1660)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2375:2375:2375) (2364:2364:2364)) - (PORT clk (1632:1632:1632) (1660:1660:1660)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1635:1635:1635) (1662:1662:1662)) - (PORT d[0] (3627:3627:3627) (3623:3623:3623)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1636:1636:1636) (1663:1663:1663)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1636:1636:1636) (1663:1663:1663)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1636:1636:1636) (1663:1663:1663)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1636:1636:1636) (1663:1663:1663)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1594:1594:1594) (1592:1592:1592)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1898:1898:1898) (1812:1812:1812)) - (PORT clk (1602:1602:1602) (1599:1599:1599)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4101:4101:4101) (4000:4000:4000)) - (PORT d[1] (3952:3952:3952) (3866:3866:3866)) - (PORT d[2] (4011:4011:4011) (3918:3918:3918)) - (PORT d[3] (4159:4159:4159) (4067:4067:4067)) - (PORT d[4] (4060:4060:4060) (3935:3935:3935)) - (PORT d[5] (4328:4328:4328) (4228:4228:4228)) - (PORT d[6] (4144:4144:4144) (4120:4120:4120)) - (PORT d[7] (4041:4041:4041) (3982:3982:3982)) - (PORT d[8] (4200:4200:4200) (4067:4067:4067)) - (PORT d[9] (4128:4128:4128) (4213:4213:4213)) - (PORT d[10] (4041:4041:4041) (3946:3946:3946)) - (PORT d[11] (4367:4367:4367) (4242:4242:4242)) - (PORT d[12] (4125:4125:4125) (4113:4113:4113)) - (PORT clk (1599:1599:1599) (1596:1596:1596)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1602:1602:1602) (1599:1599:1599)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1603:1603:1603) (1600:1600:1600)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1603:1603:1603) (1600:1600:1600)) - (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1603:1603:1603) (1600:1600:1600)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1603:1603:1603) (1600:1600:1600)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1595:1595:1595) (1593:1593:1593)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Selector4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1084:1084:1084) (1099:1099:1099)) - (PORT datab (881:881:881) (891:891:891)) - (PORT datac (1292:1292:1292) (1266:1266:1266)) - (PORT datad (1335:1335:1335) (1322:1322:1322)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Selector4\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1213:1213:1213) (1224:1224:1224)) - (PORT datab (886:886:886) (898:898:898)) - (PORT datac (1327:1327:1327) (1349:1349:1349)) - (PORT datad (161:161:161) (182:182:182)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (851:851:851) (853:853:853)) - (PORT clk (1638:1638:1638) (1666:1666:1666)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3109:3109:3109) (3183:3183:3183)) - (PORT d[1] (1610:1610:1610) (1709:1709:1709)) - (PORT d[2] (1852:1852:1852) (1867:1867:1867)) - (PORT d[3] (2001:2001:2001) (2036:2036:2036)) - (PORT d[4] (1710:1710:1710) (1718:1718:1718)) - (PORT d[5] (1262:1262:1262) (1314:1314:1314)) - (PORT d[6] (1355:1355:1355) (1362:1362:1362)) - (PORT d[7] (3106:3106:3106) (3141:3141:3141)) - (PORT d[8] (2266:2266:2266) (2361:2361:2361)) - (PORT d[9] (3248:3248:3248) (3329:3329:3329)) - (PORT d[10] (2702:2702:2702) (2780:2780:2780)) - (PORT d[11] (1389:1389:1389) (1395:1395:1395)) - (PORT d[12] (1360:1360:1360) (1386:1386:1386)) - (PORT clk (1635:1635:1635) (1664:1664:1664)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3094:3094:3094) (3034:3034:3034)) - (PORT clk (1635:1635:1635) (1664:1664:1664)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1638:1638:1638) (1666:1666:1666)) - (PORT d[0] (1771:1771:1771) (1681:1681:1681)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1667:1667:1667)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1667:1667:1667)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1667:1667:1667)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1667:1667:1667)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1602:1602:1602) (1630:1630:1630)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (873:873:873) (877:877:877)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (878:878:878)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (878:878:878)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (878:878:878)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1374:1374:1374) (1380:1380:1380)) - (PORT clk (1626:1626:1626) (1655:1655:1655)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3408:3408:3408) (3498:3498:3498)) - (PORT d[1] (1569:1569:1569) (1663:1663:1663)) - (PORT d[2] (3026:3026:3026) (3089:3089:3089)) - (PORT d[3] (2000:2000:2000) (2020:2020:2020)) - (PORT d[4] (2357:2357:2357) (2411:2411:2411)) - (PORT d[5] (1547:1547:1547) (1619:1619:1619)) - (PORT d[6] (1669:1669:1669) (1713:1713:1713)) - (PORT d[7] (1572:1572:1572) (1598:1598:1598)) - (PORT d[8] (3085:3085:3085) (3197:3197:3197)) - (PORT d[9] (2632:2632:2632) (2690:2690:2690)) - (PORT d[10] (3216:3216:3216) (3306:3306:3306)) - (PORT d[11] (1667:1667:1667) (1701:1701:1701)) - (PORT d[12] (1605:1605:1605) (1642:1642:1642)) - (PORT clk (1623:1623:1623) (1653:1653:1653)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1801:1801:1801) (1740:1740:1740)) - (PORT clk (1623:1623:1623) (1653:1653:1653)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1626:1626:1626) (1655:1655:1655)) - (PORT d[0] (2539:2539:2539) (2489:2489:2489)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1627:1627:1627) (1656:1656:1656)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1627:1627:1627) (1656:1656:1656)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1627:1627:1627) (1656:1656:1656)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1627:1627:1627) (1656:1656:1656)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1590:1590:1590) (1619:1619:1619)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (861:861:861) (866:866:866)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (862:862:862) (867:867:867)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (862:862:862) (867:867:867)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (862:862:862) (867:867:867)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1169:1169:1169) (1177:1177:1177)) - (PORT clk (1638:1638:1638) (1666:1666:1666)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3109:3109:3109) (3181:3181:3181)) - (PORT d[1] (1236:1236:1236) (1300:1300:1300)) - (PORT d[2] (1799:1799:1799) (1833:1833:1833)) - (PORT d[3] (1433:1433:1433) (1450:1450:1450)) - (PORT d[4] (1740:1740:1740) (1757:1757:1757)) - (PORT d[5] (1521:1521:1521) (1560:1560:1560)) - (PORT d[6] (1100:1100:1100) (1121:1121:1121)) - (PORT d[7] (1350:1350:1350) (1384:1384:1384)) - (PORT d[8] (2320:2320:2320) (2418:2418:2418)) - (PORT d[9] (3238:3238:3238) (3316:3316:3316)) - (PORT d[10] (2664:2664:2664) (2731:2731:2731)) - (PORT d[11] (1162:1162:1162) (1161:1161:1161)) - (PORT d[12] (1034:1034:1034) (1044:1044:1044)) - (PORT clk (1635:1635:1635) (1664:1664:1664)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2652:2652:2652) (2627:2627:2627)) - (PORT clk (1635:1635:1635) (1664:1664:1664)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1638:1638:1638) (1666:1666:1666)) - (PORT d[0] (2959:2959:2959) (2958:2958:2958)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1667:1667:1667)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1667:1667:1667)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1667:1667:1667)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1667:1667:1667)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1602:1602:1602) (1630:1630:1630)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (873:873:873) (877:877:877)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (878:878:878)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (878:878:878)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (878:878:878)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1637:1637:1637) (1639:1639:1639)) - (PORT clk (1637:1637:1637) (1665:1665:1665)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3128:3128:3128) (3214:3214:3214)) - (PORT d[1] (1579:1579:1579) (1666:1666:1666)) - (PORT d[2] (2493:2493:2493) (2551:2551:2551)) - (PORT d[3] (1985:1985:1985) (2021:2021:2021)) - (PORT d[4] (2035:2035:2035) (2070:2070:2070)) - (PORT d[5] (2222:2222:2222) (2345:2345:2345)) - (PORT d[6] (1954:1954:1954) (2014:2014:2014)) - (PORT d[7] (2290:2290:2290) (2303:2303:2303)) - (PORT d[8] (2819:2819:2819) (2916:2916:2916)) - (PORT d[9] (2386:2386:2386) (2432:2432:2432)) - (PORT d[10] (3501:3501:3501) (3612:3612:3612)) - (PORT d[11] (1655:1655:1655) (1668:1668:1668)) - (PORT d[12] (2144:2144:2144) (2185:2185:2185)) - (PORT clk (1634:1634:1634) (1663:1663:1663)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2095:2095:2095) (2041:2041:2041)) - (PORT clk (1634:1634:1634) (1663:1663:1663)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1637:1637:1637) (1665:1665:1665)) - (PORT d[0] (2457:2457:2457) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1638:1638:1638) (1666:1666:1666)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1638:1638:1638) (1666:1666:1666)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1638:1638:1638) (1666:1666:1666)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1638:1638:1638) (1666:1666:1666)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1601:1601:1601) (1629:1629:1629)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (872:872:872) (876:876:876)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (873:873:873) (877:877:877)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (873:873:873) (877:877:877)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (873:873:873) (877:877:877)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1690:1690:1690) (1647:1647:1647)) - (PORT datab (1084:1084:1084) (1080:1080:1080)) - (PORT datad (1566:1566:1566) (1563:1563:1563)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1359:1359:1359) (1382:1382:1382)) - (PORT datab (1365:1365:1365) (1350:1350:1350)) - (PORT datac (1957:1957:1957) (1959:1959:1959)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~109) - (DELAY - (ABSOLUTE - (PORT dataa (631:631:631) (693:693:693)) - (PORT datab (1093:1093:1093) (1105:1105:1105)) - (PORT datac (157:157:157) (187:187:187)) - (PORT datad (158:158:158) (178:178:178)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~97) - (DELAY - (ABSOLUTE - (PORT dataa (820:820:820) (822:822:822)) - (PORT datab (1441:1441:1441) (1442:1442:1442)) - (PORT datac (1357:1357:1357) (1385:1385:1385)) - (PORT datad (167:167:167) (191:191:191)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~98) - (DELAY - (ABSOLUTE - (PORT dataa (1076:1076:1076) (1121:1121:1121)) - (PORT datab (1558:1558:1558) (1503:1503:1503)) - (PORT datac (1358:1358:1358) (1385:1385:1385)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[4\]) - (DELAY - (ABSOLUTE - (PORT dataa (899:899:899) (937:937:937)) - (PORT datab (1408:1408:1408) (1363:1363:1363)) - (PORT datac (209:209:209) (258:258:258)) - (PORT datad (1071:1071:1071) (1059:1059:1059)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1347:1347:1347) (1358:1358:1358)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (763:763:763) (771:771:771)) + (PORT asdata (900:900:900) (921:921:921)) + (PORT sload (1632:1632:1632) (1689:1689:1689)) + (PORT ena (1576:1576:1576) (1513:1513:1513)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) (TIMINGCHECK (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[4\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (365:365:365) (415:415:415)) - (PORT datab (355:355:355) (377:377:377)) - (PORT datad (619:619:619) (624:624:624)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[4\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (904:904:904) (906:906:906)) - (PORT datab (856:856:856) (848:848:848)) - (PORT datac (821:821:821) (838:838:838)) - (PORT datad (826:826:826) (841:841:841)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1345:1345:1345) (1366:1366:1366)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1390:1390:1390) (1361:1361:1361)) - (PORT ena (1363:1363:1363) (1319:1319:1319)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal21\~0) - (DELAY - (ABSOLUTE - (PORT datac (1315:1315:1315) (1385:1385:1385)) - (PORT datad (1349:1349:1349) (1412:1412:1412)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1284:1284:1284) (1279:1279:1279)) - (PORT datab (917:917:917) (931:931:931)) - (PORT datac (1485:1485:1485) (1580:1580:1580)) - (PORT datad (1131:1131:1131) (1161:1161:1161)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1184:1184:1184) (1229:1229:1229)) - (PORT datab (1408:1408:1408) (1433:1433:1433)) - (PORT datac (762:762:762) (748:748:748)) - (PORT datad (183:183:183) (207:207:207)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~3) - (DELAY - (ABSOLUTE - (PORT datab (1421:1421:1421) (1477:1477:1477)) - (PORT datac (1249:1249:1249) (1279:1279:1279)) - (PORT datad (2264:2264:2264) (2402:2402:2402)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~4) - (DELAY - (ABSOLUTE - (PORT dataa (801:801:801) (822:822:822)) - (PORT datab (856:856:856) (852:852:852)) - (PORT datac (1586:1586:1586) (1591:1591:1591)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~5) - (DELAY - (ABSOLUTE - (PORT dataa (397:397:397) (409:409:409)) - (PORT datab (1095:1095:1095) (1125:1125:1125)) - (PORT datac (156:156:156) (186:186:186)) - (PORT datad (333:333:333) (345:345:345)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~11) - (DELAY - (ABSOLUTE - (PORT dataa (854:854:854) (888:888:888)) - (PORT datab (574:574:574) (600:600:600)) - (PORT datac (820:820:820) (837:837:837)) - (PORT datad (822:822:822) (813:813:813)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1837:1837:1837) (1846:1846:1846)) - (PORT datab (1056:1056:1056) (1022:1022:1022)) - (PORT datac (788:788:788) (768:768:768)) - (PORT datad (591:591:591) (611:611:611)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~13) - (DELAY - (ABSOLUTE - (PORT dataa (184:184:184) (219:219:219)) - (PORT datab (559:559:559) (548:548:548)) - (PORT datac (497:497:497) (488:488:488)) - (PORT datad (165:165:165) (188:188:188)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1451:1451:1451) (1497:1497:1497)) - (PORT datab (800:800:800) (797:797:797)) - (PORT datac (1353:1353:1353) (1351:1351:1351)) - (PORT datad (989:989:989) (953:953:953)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~15) - (DELAY - (ABSOLUTE - (PORT dataa (592:592:592) (581:581:581)) - (PORT datab (809:809:809) (826:826:826)) - (PORT datac (793:793:793) (777:777:777)) - (PORT datad (1104:1104:1104) (1100:1100:1100)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|DFFE_mwr_ff1) - (DELAY - (ABSOLUTE - (PORT clk (1357:1357:1357) (1378:1378:1378)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1403:1403:1403) (1374:1374:1374)) - (PORT ena (1189:1189:1189) (1191:1191:1191)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|wait_mwr\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (200:200:200) (258:258:258)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|wait_mwr) - (DELAY - (ABSOLUTE - (PORT clk (1364:1364:1364) (1371:1371:1371)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1403:1403:1403) (1374:1374:1374)) - (PORT ena (1217:1217:1217) (1223:1223:1223)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|mwr_wr) - (DELAY - (ABSOLUTE - (PORT clk (1364:1364:1364) (1371:1371:1371)) - (PORT asdata (511:511:511) (578:578:578)) - (PORT clrn (1403:1403:1403) (1374:1374:1374)) - (PORT ena (1217:1217:1217) (1223:1223:1223)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK + (HOLD sload (posedge clk) (144:144:144)) (HOLD asdata (posedge clk) (144:144:144)) (HOLD ena (posedge clk) (144:144:144)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|nWR_out\~0) + (INSTANCE z80_\|address_pins_\|abus\[1\]\~25) (DELAY (ABSOLUTE - (PORT dataa (804:804:804) (796:796:796)) - (PORT datab (331:331:331) (348:348:348)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) + (PORT datab (558:558:558) (578:578:578)) + (PORT datac (1910:1910:1910) (1903:1903:1903)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[5\]\~84) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[2\]\~2) (DELAY (ABSOLUTE - (PORT dataa (1623:1623:1623) (1655:1655:1655)) - (PORT datab (1476:1476:1476) (1530:1530:1530)) - (PORT datac (1099:1099:1099) (1117:1117:1117)) - (PORT datad (1134:1134:1134) (1160:1160:1160)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (PORT dataa (1160:1160:1160) (1182:1182:1182)) + (PORT datab (360:360:360) (366:366:366)) + (PORT datad (296:296:296) (295:295:295)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1354:1354:1354) (1361:1361:1361)) + (PORT d (67:67:67) (78:78:78)) + (PORT asdata (530:530:530) (597:597:597)) + (PORT sload (1632:1632:1632) (1689:1689:1689)) + (PORT ena (1576:1576:1576) (1513:1513:1513)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sload (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[2\]\~26) + (DELAY + (ABSOLUTE + (PORT datac (1911:1911:1911) (1902:1902:1902)) + (PORT datad (216:216:216) (274:274:274)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[3\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (697:697:697) (683:683:683)) + (PORT datab (355:355:355) (359:359:359)) + (PORT datad (1115:1115:1115) (1143:1143:1143)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1354:1354:1354) (1361:1361:1361)) + (PORT d (67:67:67) (78:78:78)) + (PORT asdata (531:531:531) (596:596:596)) + (PORT sload (1632:1632:1632) (1689:1689:1689)) + (PORT ena (1576:1576:1576) (1513:1513:1513)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sload (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[3\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (371:371:371) (420:420:420)) + (PORT datac (1913:1913:1913) (1904:1904:1904)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[4\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1296:1296:1296) (1305:1305:1305)) + (PORT datab (864:864:864) (872:872:872)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1352:1352:1352)) + (PORT d (67:67:67) (78:78:78)) + (PORT asdata (655:655:655) (700:700:700)) + (PORT sload (1870:1870:1870) (1908:1908:1908)) + (PORT ena (1832:1832:1832) (1772:1772:1772)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sload (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[4\]\~28) + (DELAY + (ABSOLUTE + (PORT datac (2236:2236:2236) (2252:2252:2252)) + (PORT datad (216:216:216) (272:272:272)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[5\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1296:1296:1296) (1306:1306:1306)) + (PORT datab (875:875:875) (864:864:864)) + (PORT datad (304:304:304) (305:305:305)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1352:1352:1352)) + (PORT d (67:67:67) (78:78:78)) + (PORT asdata (525:525:525) (588:588:588)) + (PORT sload (1870:1870:1870) (1908:1908:1908)) + (PORT ena (1832:1832:1832) (1772:1772:1772)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sload (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[5\]\~29) + (DELAY + (ABSOLUTE + (PORT datac (2231:2231:2231) (2245:2245:2245)) + (PORT datad (216:216:216) (272:272:272)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[6\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1294:1294:1294) (1301:1301:1301)) + (PORT datab (834:834:834) (819:819:819)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1352:1352:1352)) + (PORT d (67:67:67) (78:78:78)) + (PORT asdata (663:663:663) (696:696:696)) + (PORT sload (1870:1870:1870) (1908:1908:1908)) + (PORT ena (1832:1832:1832) (1772:1772:1772)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sload (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[6\]\~30) + (DELAY + (ABSOLUTE + (PORT datab (239:239:239) (308:308:308)) + (PORT datac (2231:2231:2231) (2244:2244:2244)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[7\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1321:1321:1321) (1334:1334:1334)) + (PORT datab (539:539:539) (522:522:522)) + (PORT datad (1218:1218:1218) (1175:1175:1175)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1354:1354:1354)) + (PORT d (67:67:67) (78:78:78)) + (PORT asdata (669:669:669) (702:702:702)) + (PORT sload (1864:1864:1864) (1899:1899:1899)) + (PORT ena (2103:2103:2103) (2034:2034:2034)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sload (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[7\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (2558:2558:2558) (2590:2590:2590)) + (PORT datad (854:854:854) (892:892:892)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[10\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (2513:2513:2513) (2532:2532:2532)) + (PORT datad (1298:1298:1298) (1321:1321:1321)) + (IOPATH dataa combout (329:329:329) (332:332:332)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.datain_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1084:1084:1084) (1083:1083:1083)) - (PORT clk (1643:1643:1643) (1670:1670:1670)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3903:3903:3903) (3984:3984:3984)) - (PORT d[1] (2655:2655:2655) (2790:2790:2790)) - (PORT d[2] (2992:2992:2992) (3016:3016:3016)) - (PORT d[3] (2356:2356:2356) (2437:2437:2437)) - (PORT d[4] (2074:2074:2074) (2161:2161:2161)) - (PORT d[5] (2391:2391:2391) (2481:2481:2481)) - (PORT d[6] (1728:1728:1728) (1769:1769:1769)) - (PORT d[7] (2149:2149:2149) (2178:2178:2178)) - (PORT d[8] (2888:2888:2888) (3027:3027:3027)) - (PORT d[9] (2688:2688:2688) (2747:2747:2747)) - (PORT d[10] (4446:4446:4446) (4545:4545:4545)) - (PORT d[11] (2033:2033:2033) (2092:2092:2092)) - (PORT d[12] (2027:2027:2027) (2085:2085:2085)) - (PORT clk (1640:1640:1640) (1668:1668:1668)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1812:1812:1812) (1737:1737:1737)) - (PORT clk (1640:1640:1640) (1668:1668:1668)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1643:1643:1643) (1670:1670:1670)) - (PORT d[0] (2104:2104:2104) (2069:2069:2069)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1644:1644:1644) (1671:1671:1671)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1644:1644:1644) (1671:1671:1671)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1644:1644:1644) (1671:1671:1671)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1644:1644:1644) (1671:1671:1671)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1607:1607:1607) (1634:1634:1634)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (878:878:878) (881:881:881)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (879:879:879) (882:882:882)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (879:879:879) (882:882:882)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (879:879:879) (882:882:882)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1106:1106:1106) (1100:1100:1100)) + (PORT d[0] (883:883:883) (867:867:867)) (PORT clk (1644:1644:1644) (1670:1670:1670)) ) ) @@ -43247,22 +31348,22 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (3898:3898:3898) (3977:3977:3977)) - (PORT d[1] (2675:2675:2675) (2810:2810:2810)) - (PORT d[2] (2544:2544:2544) (2585:2585:2585)) - (PORT d[3] (2356:2356:2356) (2433:2433:2433)) - (PORT d[4] (2094:2094:2094) (2182:2182:2182)) - (PORT d[5] (2365:2365:2365) (2452:2452:2452)) - (PORT d[6] (1754:1754:1754) (1791:1791:1791)) - (PORT d[7] (2123:2123:2123) (2149:2149:2149)) - (PORT d[8] (2905:2905:2905) (3041:3041:3041)) - (PORT d[9] (2410:2410:2410) (2473:2473:2473)) - (PORT d[10] (4441:4441:4441) (4538:4538:4538)) - (PORT d[11] (1762:1762:1762) (1827:1827:1827)) - (PORT d[12] (2035:2035:2035) (2098:2098:2098)) + (PORT d[0] (3019:3019:3019) (3141:3141:3141)) + (PORT d[1] (1147:1147:1147) (1187:1187:1187)) + (PORT d[2] (2717:2717:2717) (2847:2847:2847)) + (PORT d[3] (669:669:669) (676:676:676)) + (PORT d[4] (1053:1053:1053) (1040:1040:1040)) + (PORT d[5] (1146:1146:1146) (1152:1152:1152)) + (PORT d[6] (914:914:914) (925:925:925)) + (PORT d[7] (2672:2672:2672) (2798:2798:2798)) + (PORT d[8] (1166:1166:1166) (1176:1176:1176)) + (PORT d[9] (898:898:898) (895:895:895)) + (PORT d[10] (1482:1482:1482) (1496:1496:1496)) + (PORT d[11] (1407:1407:1407) (1402:1402:1402)) + (PORT d[12] (2396:2396:2396) (2400:2400:2400)) (PORT clk (1641:1641:1641) (1668:1668:1668)) ) ) @@ -43272,10 +31373,10 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.we_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2200:2200:2200) (2122:2122:2122)) + (PORT d[0] (1820:1820:1820) (1771:1771:1771)) (PORT clk (1641:1641:1641) (1668:1668:1668)) ) ) @@ -43285,17 +31386,17 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) (DELAY (ABSOLUTE (PORT clk (1644:1644:1644) (1670:1670:1670)) - (PORT d[0] (2614:2614:2614) (2527:2527:2527)) + (PORT d[0] (2031:2031:2031) (1956:1956:1956)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_a) (DELAY (ABSOLUTE (PORT clk (1645:1645:1645) (1671:1671:1671)) @@ -43305,7 +31406,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) (DELAY (ABSOLUTE (PORT clk (1645:1645:1645) (1671:1671:1671)) @@ -43315,7 +31416,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_a) (DELAY (ABSOLUTE (PORT clk (1645:1645:1645) (1671:1671:1671)) @@ -43325,7 +31426,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_a) (DELAY (ABSOLUTE (PORT clk (1645:1645:1645) (1671:1671:1671)) @@ -43335,7 +31436,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) (DELAY (ABSOLUTE (PORT clk (1608:1608:1608) (1634:1634:1634)) @@ -43349,7 +31450,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) (DELAY (ABSOLUTE (PORT clk (879:879:879) (881:881:881)) @@ -43358,7 +31459,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) (DELAY (ABSOLUTE (PORT clk (880:880:880) (882:882:882)) @@ -43367,7 +31468,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) (DELAY (ABSOLUTE (PORT clk (880:880:880) (882:882:882)) @@ -43377,7 +31478,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) (DELAY (ABSOLUTE (PORT clk (880:880:880) (882:882:882)) @@ -43385,982 +31486,17 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (817:817:817) (820:820:820)) - (PORT clk (1638:1638:1638) (1665:1665:1665)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1228:1228:1228) (1255:1255:1255)) - (PORT d[1] (1897:1897:1897) (2022:2022:2022)) - (PORT d[2] (2775:2775:2775) (2823:2823:2823)) - (PORT d[3] (2397:2397:2397) (2495:2495:2495)) - (PORT d[4] (2384:2384:2384) (2480:2480:2480)) - (PORT d[5] (2636:2636:2636) (2730:2730:2730)) - (PORT d[6] (1805:1805:1805) (1869:1869:1869)) - (PORT d[7] (2410:2410:2410) (2444:2444:2444)) - (PORT d[8] (3147:3147:3147) (3288:3288:3288)) - (PORT d[9] (2709:2709:2709) (2776:2776:2776)) - (PORT d[10] (4723:4723:4723) (4808:4808:4808)) - (PORT d[11] (1794:1794:1794) (1853:1853:1853)) - (PORT d[12] (1761:1761:1761) (1812:1812:1812)) - (PORT clk (1635:1635:1635) (1663:1663:1663)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1125:1125:1125) (1096:1096:1096)) - (PORT clk (1635:1635:1635) (1663:1663:1663)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1638:1638:1638) (1665:1665:1665)) - (PORT d[0] (2299:2299:2299) (2237:2237:2237)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1666:1666:1666)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1666:1666:1666)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1666:1666:1666)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1639:1639:1639) (1666:1666:1666)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1602:1602:1602) (1629:1629:1629)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (873:873:873) (876:876:876)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (877:877:877)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (877:877:877)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (877:877:877)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~6) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode223w\[2\]) (DELAY (ABSOLUTE - (PORT dataa (1313:1313:1313) (1351:1351:1351)) - (PORT datab (897:897:897) (941:941:941)) - (PORT datac (1013:1013:1013) (988:988:988)) - (PORT datad (779:779:779) (758:758:758)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1106:1106:1106) (1110:1110:1110)) - (PORT clk (1636:1636:1636) (1662:1662:1662)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3118:3118:3118) (3206:3206:3206)) - (PORT d[1] (1574:1574:1574) (1682:1682:1682)) - (PORT d[2] (2764:2764:2764) (2820:2820:2820)) - (PORT d[3] (2036:2036:2036) (2067:2067:2067)) - (PORT d[4] (2319:2319:2319) (2363:2363:2363)) - (PORT d[5] (2234:2234:2234) (2357:2357:2357)) - (PORT d[6] (1950:1950:1950) (2007:2007:2007)) - (PORT d[7] (2300:2300:2300) (2311:2311:2311)) - (PORT d[8] (2804:2804:2804) (2907:2907:2907)) - (PORT d[9] (2345:2345:2345) (2391:2391:2391)) - (PORT d[10] (3492:3492:3492) (3594:3594:3594)) - (PORT d[11] (1620:1620:1620) (1617:1617:1617)) - (PORT d[12] (2158:2158:2158) (2197:2197:2197)) - (PORT clk (1633:1633:1633) (1660:1660:1660)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2044:2044:2044) (1984:1984:1984)) - (PORT clk (1633:1633:1633) (1660:1660:1660)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1636:1636:1636) (1662:1662:1662)) - (PORT d[0] (2515:2515:2515) (2442:2442:2442)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1637:1637:1637) (1663:1663:1663)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1637:1637:1637) (1663:1663:1663)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1637:1637:1637) (1663:1663:1663)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1637:1637:1637) (1663:1663:1663)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1600:1600:1600) (1626:1626:1626)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (871:871:871) (873:873:873)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (872:872:872) (874:874:874)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (872:872:872) (874:874:874)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (872:872:872) (874:874:874)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1341:1341:1341) (1343:1343:1343)) - (PORT datab (1065:1065:1065) (1048:1048:1048)) - (PORT datac (155:155:155) (184:184:184)) - (PORT datad (1316:1316:1316) (1315:1315:1315)) + (PORT dataa (1086:1086:1086) (1094:1094:1094)) + (PORT datab (210:210:210) (263:263:263)) + (PORT datac (530:530:530) (525:525:525)) + (PORT datad (1484:1484:1484) (1463:1463:1463)) (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1655:1655:1655) (1653:1653:1653)) - (PORT clk (1631:1631:1631) (1657:1657:1657)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3090:3090:3090) (3149:3149:3149)) - (PORT d[1] (2170:2170:2170) (2280:2280:2280)) - (PORT d[2] (2054:2054:2054) (2074:2074:2074)) - (PORT d[3] (1760:1760:1760) (1812:1812:1812)) - (PORT d[4] (2275:2275:2275) (2299:2299:2299)) - (PORT d[5] (1818:1818:1818) (1900:1900:1900)) - (PORT d[6] (1325:1325:1325) (1345:1345:1345)) - (PORT d[7] (1367:1367:1367) (1391:1391:1391)) - (PORT d[8] (2695:2695:2695) (2775:2775:2775)) - (PORT d[9] (1844:1844:1844) (1890:1890:1890)) - (PORT d[10] (1848:1848:1848) (1885:1885:1885)) - (PORT d[11] (1347:1347:1347) (1357:1357:1357)) - (PORT d[12] (1878:1878:1878) (1897:1897:1897)) - (PORT clk (1628:1628:1628) (1655:1655:1655)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2618:2618:2618) (2589:2589:2589)) - (PORT clk (1628:1628:1628) (1655:1655:1655)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1631:1631:1631) (1657:1657:1657)) - (PORT d[0] (3631:3631:3631) (3630:3630:3630)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1632:1632:1632) (1658:1658:1658)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1632:1632:1632) (1658:1658:1658)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1632:1632:1632) (1658:1658:1658)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1632:1632:1632) (1658:1658:1658)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1590:1590:1590) (1587:1587:1587)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1120:1120:1120) (1076:1076:1076)) - (PORT clk (1598:1598:1598) (1594:1594:1594)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4121:4121:4121) (4013:4013:4013)) - (PORT d[1] (3945:3945:3945) (3855:3855:3855)) - (PORT d[2] (4002:4002:4002) (3896:3896:3896)) - (PORT d[3] (4214:4214:4214) (4129:4129:4129)) - (PORT d[4] (4041:4041:4041) (3914:3914:3914)) - (PORT d[5] (4057:4057:4057) (3974:3974:3974)) - (PORT d[6] (4333:4333:4333) (4305:4305:4305)) - (PORT d[7] (4082:4082:4082) (4025:4025:4025)) - (PORT d[8] (4208:4208:4208) (4078:4078:4078)) - (PORT d[9] (4362:4362:4362) (4432:4432:4432)) - (PORT d[10] (4090:4090:4090) (4015:4015:4015)) - (PORT d[11] (4073:4073:4073) (3949:3949:3949)) - (PORT d[12] (4364:4364:4364) (4258:4258:4258)) - (PORT clk (1595:1595:1595) (1591:1591:1591)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1598:1598:1598) (1594:1594:1594)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1599:1599:1599) (1595:1595:1595)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1599:1599:1599) (1595:1595:1595)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1599:1599:1599) (1595:1595:1595)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1599:1599:1599) (1595:1595:1595)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2416:2416:2416) (2419:2419:2419)) - (PORT d[1] (1915:1915:1915) (2042:2042:2042)) - (PORT d[2] (2107:2107:2107) (2177:2177:2177)) - (PORT d[3] (2104:2104:2104) (2154:2154:2154)) - (PORT d[4] (2750:2750:2750) (2873:2873:2873)) - (PORT d[5] (1930:1930:1930) (2036:2036:2036)) - (PORT d[6] (1710:1710:1710) (1749:1749:1749)) - (PORT d[7] (2359:2359:2359) (2360:2360:2360)) - (PORT d[8] (2561:2561:2561) (2682:2682:2682)) - (PORT d[9] (1438:1438:1438) (1472:1472:1472)) - (PORT d[10] (1709:1709:1709) (1741:1741:1741)) - (PORT d[11] (2675:2675:2675) (2708:2708:2708)) - (PORT d[12] (1424:1424:1424) (1457:1457:1457)) - (PORT clk (1652:1652:1652) (1680:1680:1680)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1652:1652:1652) (1680:1680:1680)) - (PORT d[0] (2018:2018:2018) (2009:2009:2009)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1653:1653:1653) (1681:1681:1681)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1619:1619:1619) (1646:1646:1646)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (890:890:890) (893:893:893)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (891:891:891) (894:894:894)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (891:891:891) (894:894:894)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (891:891:891) (894:894:894)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3298:3298:3298) (3351:3351:3351)) - (PORT d[1] (1592:1592:1592) (1680:1680:1680)) - (PORT d[2] (2484:2484:2484) (2533:2533:2533)) - (PORT d[3] (1975:1975:1975) (2004:2004:2004)) - (PORT d[4] (1767:1767:1767) (1818:1818:1818)) - (PORT d[5] (2208:2208:2208) (2318:2318:2318)) - (PORT d[6] (2159:2159:2159) (2202:2202:2202)) - (PORT d[7] (2280:2280:2280) (2283:2283:2283)) - (PORT d[8] (2504:2504:2504) (2584:2584:2584)) - (PORT d[9] (2330:2330:2330) (2362:2362:2362)) - (PORT d[10] (3529:3529:3529) (3646:3646:3646)) - (PORT d[11] (1688:1688:1688) (1708:1708:1708)) - (PORT d[12] (2198:2198:2198) (2247:2247:2247)) - (PORT clk (1635:1635:1635) (1664:1664:1664)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1635:1635:1635) (1664:1664:1664)) - (PORT d[0] (2249:2249:2249) (2258:2258:2258)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1636:1636:1636) (1665:1665:1665)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1602:1602:1602) (1630:1630:1630)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (873:873:873) (877:877:877)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (878:878:878)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (878:878:878)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (878:878:878)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1532:1532:1532) (1559:1559:1559)) - (PORT clk (1646:1646:1646) (1673:1673:1673)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2702:2702:2702) (2726:2726:2726)) - (PORT d[1] (2194:2194:2194) (2333:2333:2333)) - (PORT d[2] (2394:2394:2394) (2459:2459:2459)) - (PORT d[3] (1855:1855:1855) (1909:1909:1909)) - (PORT d[4] (2716:2716:2716) (2843:2843:2843)) - (PORT d[5] (2202:2202:2202) (2319:2319:2319)) - (PORT d[6] (1727:1727:1727) (1746:1746:1746)) - (PORT d[7] (1517:1517:1517) (1555:1555:1555)) - (PORT d[8] (2811:2811:2811) (2896:2896:2896)) - (PORT d[9] (1130:1130:1130) (1151:1151:1151)) - (PORT d[10] (1994:1994:1994) (2037:2037:2037)) - (PORT d[11] (3422:3422:3422) (3471:3471:3471)) - (PORT d[12] (1753:1753:1753) (1782:1782:1782)) - (PORT clk (1643:1643:1643) (1671:1671:1671)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2584:2584:2584) (2522:2522:2522)) - (PORT clk (1643:1643:1643) (1671:1671:1671)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1646:1646:1646) (1673:1673:1673)) - (PORT d[0] (2819:2819:2819) (2825:2825:2825)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1674:1674:1674)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1674:1674:1674)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1674:1674:1674)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1647:1647:1647) (1674:1674:1674)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1605:1605:1605) (1603:1603:1603)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2024:2024:2024) (2022:2022:2022)) - (PORT clk (1613:1613:1613) (1610:1610:1610)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4286:4286:4286) (4176:4176:4176)) - (PORT d[1] (3889:3889:3889) (3754:3754:3754)) - (PORT d[2] (3922:3922:3922) (3831:3831:3831)) - (PORT d[3] (4387:4387:4387) (4236:4236:4236)) - (PORT d[4] (4059:4059:4059) (3930:3930:3930)) - (PORT d[5] (4137:4137:4137) (3982:3982:3982)) - (PORT d[6] (4314:4314:4314) (4255:4255:4255)) - (PORT d[7] (3900:3900:3900) (3727:3727:3727)) - (PORT d[8] (4378:4378:4378) (4223:4223:4223)) - (PORT d[9] (4245:4245:4245) (4309:4309:4309)) - (PORT d[10] (4110:4110:4110) (4007:4007:4007)) - (PORT d[11] (4188:4188:4188) (4097:4097:4097)) - (PORT d[12] (4162:4162:4162) (4084:4084:4084)) - (PORT clk (1610:1610:1610) (1607:1607:1607)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1613:1613:1613) (1610:1610:1610)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1614:1614:1614) (1611:1611:1611)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1614:1614:1614) (1611:1611:1611)) - (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1614:1614:1614) (1611:1611:1611)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1614:1614:1614) (1611:1611:1611)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1606:1606:1606) (1604:1604:1604)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Mux0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1324:1324:1324) (1337:1337:1337)) - (PORT datab (912:912:912) (946:946:946)) - (PORT datac (1320:1320:1320) (1311:1311:1311)) - (PORT datad (1291:1291:1291) (1297:1297:1297)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Mux0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1403:1403:1403) (1437:1437:1437)) - (PORT datab (910:910:910) (944:944:944)) - (PORT datac (1361:1361:1361) (1365:1365:1365)) - (PORT datad (159:159:159) (181:181:181)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datab combout (308:308:308) (281:281:281)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -44368,169 +31504,218 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[7\]\~112) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode223w\[2\]\~0) (DELAY (ABSOLUTE - (PORT dataa (1368:1368:1368) (1422:1422:1422)) - (PORT datab (1129:1129:1129) (1138:1138:1138)) - (PORT datac (157:157:157) (187:187:187)) - (PORT datad (159:159:159) (179:179:179)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT datab (1516:1516:1516) (1581:1581:1581)) + (PORT datac (2378:2378:2378) (2427:2427:2427)) + (PORT datad (2089:2089:2089) (2130:2130:2130)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[7\]\~94) + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register) (DELAY (ABSOLUTE - (PORT dataa (1282:1282:1282) (1254:1254:1254)) - (PORT datab (819:819:819) (858:858:858)) - (PORT datac (155:155:155) (185:185:185)) - (PORT datad (1259:1259:1259) (1238:1238:1238)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (PORT d[0] (691:691:691) (692:692:692)) + (PORT clk (1640:1640:1640) (1668:1668:1668)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2409:2409:2409) (2457:2457:2457)) + (PORT d[1] (893:893:893) (900:900:900)) + (PORT d[2] (2456:2456:2456) (2581:2581:2581)) + (PORT d[3] (926:926:926) (927:927:927)) + (PORT d[4] (656:656:656) (674:674:674)) + (PORT d[5] (624:624:624) (618:618:618)) + (PORT d[6] (621:621:621) (623:623:623)) + (PORT d[7] (2004:2004:2004) (2069:2069:2069)) + (PORT d[8] (1405:1405:1405) (1403:1403:1403)) + (PORT d[9] (621:621:621) (622:622:622)) + (PORT d[10] (2005:2005:2005) (1999:1999:1999)) + (PORT d[11] (1633:1633:1633) (1609:1609:1609)) + (PORT d[12] (2387:2387:2387) (2384:2384:2384)) + (PORT clk (1637:1637:1637) (1666:1666:1666)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1314:1314:1314) (1251:1251:1251)) + (PORT clk (1637:1637:1637) (1666:1666:1666)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1640:1640:1640) (1668:1668:1668)) + (PORT d[0] (1732:1732:1732) (1665:1665:1665)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1669:1669:1669)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1669:1669:1669)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1669:1669:1669)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1669:1669:1669)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1604:1604:1604) (1632:1632:1632)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (875:875:875) (879:879:879)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (880:880:880)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (880:880:880)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (880:880:880)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[7\]\~102) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[0\]\~feeder) (DELAY (ABSOLUTE - (PORT datac (173:173:173) (203:203:203)) - (PORT datad (735:735:735) (718:718:718)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[7\]) - (DELAY - (ABSOLUTE - (PORT dataa (903:903:903) (904:904:904)) - (PORT datab (208:208:208) (245:245:245)) - (PORT datac (211:211:211) (256:256:256)) - (PORT datad (796:796:796) (802:802:802)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT datad (1438:1438:1438) (1428:1428:1428)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[7\]) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[0\]) (DELAY (ABSOLUTE - (PORT clk (1347:1347:1347) (1358:1358:1358)) + (PORT clk (1337:1337:1337) (1356:1356:1356)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (763:763:763) (771:771:771)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) (TIMINGCHECK (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[7\]\~5) - (DELAY - (ABSOLUTE - (PORT datab (1079:1079:1079) (1089:1089:1089)) - (PORT datac (877:877:877) (911:911:911)) - (PORT datad (335:335:335) (347:347:347)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[7\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (243:243:243) (317:317:317)) - (PORT datab (659:659:659) (657:657:657)) - (PORT datac (811:811:811) (793:793:793)) - (PORT datad (158:158:158) (178:178:178)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[7\]) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]) (DELAY (ABSOLUTE - (PORT clk (1344:1344:1344) (1361:1361:1361)) - (PORT asdata (492:492:492) (524:524:524)) - (PORT clrn (1398:1398:1398) (1368:1368:1368)) - (PORT ena (1378:1378:1378) (1346:1346:1346)) + (PORT clk (1337:1337:1337) (1356:1356:1356)) + (PORT asdata (1363:1363:1363) (1353:1353:1353)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) ) (TIMINGCHECK (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal77\~0) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode244w\[2\]) (DELAY (ABSOLUTE - (PORT dataa (662:662:662) (730:730:730)) - (PORT datab (1151:1151:1151) (1204:1204:1204)) - (PORT datac (893:893:893) (932:932:932)) - (PORT datad (1224:1224:1224) (1307:1307:1307)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~5) - (DELAY - (ABSOLUTE - (PORT dataa (632:632:632) (668:668:668)) - (PORT datab (914:914:914) (979:979:979)) - (PORT datac (1059:1059:1059) (1078:1078:1078)) - (PORT datad (1084:1084:1084) (1127:1127:1127)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla31pla33M4T1_3) - (DELAY - (ABSOLUTE - (PORT dataa (666:666:666) (694:694:694)) - (PORT datab (350:350:350) (370:370:370)) - (PORT datac (1024:1024:1024) (1011:1011:1011)) - (PORT datad (1602:1602:1602) (1608:1608:1608)) + (PORT dataa (1090:1090:1090) (1102:1102:1102)) + (PORT datab (209:209:209) (262:262:262)) + (PORT datac (534:534:534) (527:527:527)) + (PORT datad (1486:1486:1486) (1465:1465:1465)) (IOPATH dataa combout (290:290:290) (306:306:306)) (IOPATH datab combout (295:295:295) (300:300:300)) (IOPATH datac combout (220:220:220) (215:215:215)) @@ -44540,645 +31725,24 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~3) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode244w\[2\]\~0) (DELAY (ABSOLUTE - (PORT dataa (916:916:916) (931:931:931)) - (PORT datab (1056:1056:1056) (1041:1041:1041)) - (PORT datac (1025:1025:1025) (1039:1039:1039)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH dataa combout (307:307:307) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1599:1599:1599) (1605:1605:1605)) - (PORT datab (978:978:978) (1056:1056:1056)) - (PORT datac (1110:1110:1110) (1156:1156:1156)) - (PORT datad (1056:1056:1056) (1063:1063:1063)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1596:1596:1596) (1601:1601:1601)) - (PORT datab (346:346:346) (372:372:372)) - (PORT datac (1391:1391:1391) (1462:1462:1462)) - (PORT datad (1019:1019:1019) (1003:1003:1003)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (308:308:308) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (210:210:210) (253:253:253)) - (PORT datab (953:953:953) (995:995:995)) - (PORT datac (1024:1024:1024) (1012:1012:1012)) - (PORT datad (997:997:997) (1023:1023:1023)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (819:819:819) (820:820:820)) - (PORT datab (1391:1391:1391) (1379:1379:1379)) - (PORT datac (770:770:770) (763:763:763)) - (PORT datad (803:803:803) (799:799:799)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (295:295:295) (285:285:285)) + (PORT datab (1906:1906:1906) (1975:1975:1975)) + (PORT datac (1204:1204:1204) (1299:1299:1299)) + (PORT datad (2832:2832:2832) (2881:2881:2881)) + (IOPATH datab combout (295:295:295) (294:294:294)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~7) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (181:181:181) (213:213:213)) - (PORT datac (156:156:156) (186:186:186)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]\~50) - (DELAY - (ABSOLUTE - (PORT datac (987:987:987) (1048:1048:1048)) - (PORT datad (950:950:950) (998:998:998)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]\~52) - (DELAY - (ABSOLUTE - (PORT dataa (376:376:376) (386:386:386)) - (PORT datab (889:889:889) (937:937:937)) - (PORT datad (160:160:160) (182:182:182)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1370:1370:1370)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1378:1378:1378)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]\~48) - (DELAY - (ABSOLUTE - (PORT dataa (205:205:205) (254:254:254)) - (PORT datab (711:711:711) (776:776:776)) - (PORT datac (1249:1249:1249) (1305:1305:1305)) - (PORT datad (1421:1421:1421) (1458:1458:1458)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[2\]\~49) - (DELAY - (ABSOLUTE - (PORT dataa (321:321:321) (341:341:341)) - (PORT datab (202:202:202) (235:235:235)) - (PORT datad (681:681:681) (739:739:739)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1370:1370:1370)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1397:1397:1397) (1378:1378:1378)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (2135:2135:2135) (2209:2209:2209)) - (PORT datab (220:220:220) (287:287:287)) - (PORT datac (536:536:536) (557:557:557)) - (PORT datad (1219:1219:1219) (1194:1194:1194)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~57) - (DELAY - (ABSOLUTE - (PORT datab (887:887:887) (941:941:941)) - (PORT datad (678:678:678) (747:747:747)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~58) - (DELAY - (ABSOLUTE - (PORT dataa (185:185:185) (222:222:222)) - (PORT datab (574:574:574) (596:596:596)) - (PORT datad (886:886:886) (928:928:928)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1354:1354:1354) (1371:1371:1371)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1399:1399:1399) (1379:1379:1379)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~59) - (DELAY - (ABSOLUTE - (PORT dataa (435:435:435) (501:501:501)) - (PORT datab (607:607:607) (656:656:656)) - (PORT datac (560:560:560) (595:595:595)) - (PORT datad (668:668:668) (700:700:700)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~131) - (DELAY - (ABSOLUTE - (PORT dataa (409:409:409) (475:475:475)) - (PORT datab (324:324:324) (338:338:338)) - (PORT datad (237:237:237) (302:302:302)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~60) - (DELAY - (ABSOLUTE - (PORT dataa (729:729:729) (815:815:815)) - (PORT datab (1010:1010:1010) (988:988:988)) - (PORT datad (570:570:570) (568:568:568)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1371:1371:1371)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1379:1379:1379)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (1071:1071:1071) (1090:1090:1090)) - (PORT datab (219:219:219) (286:286:286)) - (PORT datac (529:529:529) (551:551:551)) - (PORT datad (515:515:515) (511:511:511)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]\~53) - (DELAY - (ABSOLUTE - (PORT datac (987:987:987) (1045:1045:1045)) - (PORT datad (950:950:950) (994:994:994)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]\~55) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (259:259:259)) - (PORT datab (363:363:363) (370:370:370)) - (PORT datac (843:843:843) (874:874:874)) - (PORT datad (303:303:303) (310:310:310)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]\~56) - (DELAY - (ABSOLUTE - (PORT datab (890:890:890) (939:939:939)) - (PORT datad (315:315:315) (314:314:314)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1370:1370:1370)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1378:1378:1378)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]\~54) - (DELAY - (ABSOLUTE - (PORT dataa (378:378:378) (388:388:388)) - (PORT datab (890:890:890) (939:939:939)) - (PORT datad (178:178:178) (199:199:199)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1370:1370:1370)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1378:1378:1378)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (222:222:222) (294:294:294)) - (PORT datab (221:221:221) (290:290:290)) - (PORT datac (527:527:527) (527:527:527)) - (PORT datad (522:522:522) (510:510:510)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~68) - (DELAY - (ABSOLUTE - (PORT dataa (885:885:885) (918:918:918)) - (PORT datab (728:728:728) (803:803:803)) - (PORT datac (828:828:828) (877:877:877)) - (PORT datad (704:704:704) (778:778:778)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~69) - (DELAY - (ABSOLUTE - (PORT dataa (339:339:339) (354:354:354)) - (PORT datab (677:677:677) (738:738:738)) - (PORT datad (543:543:543) (537:537:537)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~70) - (DELAY - (ABSOLUTE - (PORT dataa (195:195:195) (238:238:238)) - (PORT datab (184:184:184) (218:218:218)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (312:312:312) (325:325:325)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1370:1370:1370)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1397:1397:1397) (1378:1378:1378)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~61) - (DELAY - (ABSOLUTE - (PORT datac (220:220:220) (290:290:290)) - (PORT datad (769:769:769) (789:789:789)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~62) - (DELAY - (ABSOLUTE - (PORT dataa (651:651:651) (681:681:681)) - (PORT datab (326:326:326) (337:337:337)) - (PORT datac (599:599:599) (636:636:636)) - (PORT datad (588:588:588) (618:618:618)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~64) - (DELAY - (ABSOLUTE - (PORT dataa (192:192:192) (233:233:233)) - (PORT datab (441:441:441) (481:481:481)) - (PORT datac (327:327:327) (340:340:340)) - (PORT datad (176:176:176) (209:209:209)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~65) - (DELAY - (ABSOLUTE - (PORT dataa (665:665:665) (724:724:724)) - (PORT datab (447:447:447) (513:513:513)) - (PORT datac (534:534:534) (537:537:537)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Selector13\~0) - (DELAY - (ABSOLUTE - (PORT dataa (685:685:685) (748:748:748)) - (PORT datab (714:714:714) (779:779:779)) - (PORT datad (884:884:884) (922:922:922)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~66) - (DELAY - (ABSOLUTE - (PORT dataa (320:320:320) (331:331:331)) - (PORT datad (579:579:579) (592:592:592)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1369:1369:1369)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1396:1396:1396) (1377:1377:1377)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~38) - (DELAY - (ABSOLUTE - (PORT dataa (1543:1543:1543) (1518:1518:1518)) - (PORT datab (574:574:574) (597:597:597)) - (PORT datac (982:982:982) (1004:1004:1004)) - (PORT datad (197:197:197) (253:253:253)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~39) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (590:590:590) (591:591:591)) - (PORT datac (156:156:156) (187:187:187)) - (PORT datad (546:546:546) (535:535:535)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~104) - (DELAY - (ABSOLUTE - (PORT datab (1135:1135:1135) (1151:1151:1151)) - (PORT datac (605:605:605) (649:649:649)) - (PORT datad (1287:1287:1287) (1270:1270:1270)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.datain_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (878:878:878) (882:882:882)) + (PORT d[0] (910:910:910) (913:913:913)) (PORT clk (1634:1634:1634) (1663:1663:1663)) ) ) @@ -45188,22 +31752,22 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.addr_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1228:1228:1228) (1255:1255:1255)) - (PORT d[1] (1824:1824:1824) (1948:1948:1948)) - (PORT d[2] (2820:2820:2820) (2872:2872:2872)) - (PORT d[3] (2632:2632:2632) (2723:2723:2723)) - (PORT d[4] (2364:2364:2364) (2459:2459:2459)) - (PORT d[5] (2640:2640:2640) (2736:2736:2736)) - (PORT d[6] (1780:1780:1780) (1841:1841:1841)) - (PORT d[7] (2392:2392:2392) (2429:2429:2429)) - (PORT d[8] (3173:3173:3173) (3316:3316:3316)) - (PORT d[9] (1484:1484:1484) (1527:1527:1527)) - (PORT d[10] (4703:4703:4703) (4804:4804:4804)) - (PORT d[11] (1778:1778:1778) (1847:1847:1847)) - (PORT d[12] (1760:1760:1760) (1812:1812:1812)) + (PORT d[0] (2406:2406:2406) (2451:2451:2451)) + (PORT d[1] (911:911:911) (936:936:936)) + (PORT d[2] (2451:2451:2451) (2573:2573:2573)) + (PORT d[3] (910:910:910) (913:913:913)) + (PORT d[4] (691:691:691) (715:715:715)) + (PORT d[5] (1117:1117:1117) (1115:1115:1115)) + (PORT d[6] (930:930:930) (942:942:942)) + (PORT d[7] (1992:1992:1992) (2049:2049:2049)) + (PORT d[8] (1134:1134:1134) (1136:1136:1136)) + (PORT d[9] (1168:1168:1168) (1162:1162:1162)) + (PORT d[10] (1052:1052:1052) (1030:1030:1030)) + (PORT d[11] (1393:1393:1393) (1380:1380:1380)) + (PORT d[12] (2124:2124:2124) (2120:2120:2120)) (PORT clk (1631:1631:1631) (1661:1661:1661)) ) ) @@ -45213,10 +31777,10 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.we_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1120:1120:1120) (1091:1091:1091)) + (PORT d[0] (2064:2064:2064) (2015:2015:2015)) (PORT clk (1631:1631:1631) (1661:1661:1661)) ) ) @@ -45226,17 +31790,17 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.active_core_port_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.active_core_port_a) (DELAY (ABSOLUTE (PORT clk (1634:1634:1634) (1663:1663:1663)) - (PORT d[0] (2292:2292:2292) (2214:2214:2214)) + (PORT d[0] (1739:1739:1739) (1687:1687:1687)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.wpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.wpgen_a) (DELAY (ABSOLUTE (PORT clk (1635:1635:1635) (1664:1664:1664)) @@ -45246,7 +31810,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rpgen_a) (DELAY (ABSOLUTE (PORT clk (1635:1635:1635) (1664:1664:1664)) @@ -45256,7 +31820,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.ftpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.ftpgen_a) (DELAY (ABSOLUTE (PORT clk (1635:1635:1635) (1664:1664:1664)) @@ -45266,7 +31830,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rwpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rwpgen_a) (DELAY (ABSOLUTE (PORT clk (1635:1635:1635) (1664:1664:1664)) @@ -45276,7 +31840,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.dataout_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.dataout_a_register) (DELAY (ABSOLUTE (PORT clk (1598:1598:1598) (1627:1627:1627)) @@ -45290,7 +31854,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.active_core_port_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.active_core_port_b) (DELAY (ABSOLUTE (PORT clk (869:869:869) (874:874:874)) @@ -45299,7 +31863,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rpgen_b) (DELAY (ABSOLUTE (PORT clk (870:870:870) (875:875:875)) @@ -45308,7 +31872,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.ftpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.ftpgen_b) (DELAY (ABSOLUTE (PORT clk (870:870:870) (875:875:875)) @@ -45318,7 +31882,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rwpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rwpgen_b) (DELAY (ABSOLUTE (PORT clk (870:870:870) (875:875:875)) @@ -45327,164 +31891,85 @@ ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.datain_a_register) + (CELLTYPE "dffeas") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[1\]) (DELAY (ABSOLUTE - (PORT d[0] (656:656:656) (645:645:645)) - (PORT clk (1644:1644:1644) (1670:1670:1670)) + (PORT clk (1344:1344:1344) (1361:1361:1361)) + (PORT asdata (1903:1903:1903) (1878:1878:1878)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) + (HOLD asdata (posedge clk) (144:144:144)) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) + (CELLTYPE "dffeas") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[1\]) (DELAY (ABSOLUTE - (PORT d[0] (1171:1171:1171) (1169:1169:1169)) - (PORT d[1] (1948:1948:1948) (2094:2094:2094)) - (PORT d[2] (1153:1153:1153) (1155:1155:1155)) - (PORT d[3] (1204:1204:1204) (1226:1226:1226)) - (PORT d[4] (2425:2425:2425) (2533:2533:2533)) - (PORT d[5] (3217:3217:3217) (3322:3322:3322)) - (PORT d[6] (1222:1222:1222) (1272:1272:1272)) - (PORT d[7] (2666:2666:2666) (2711:2711:2711)) - (PORT d[8] (913:913:913) (921:921:921)) - (PORT d[9] (1196:1196:1196) (1239:1239:1239)) - (PORT d[10] (1257:1257:1257) (1305:1305:1305)) - (PORT d[11] (2298:2298:2298) (2368:2368:2368)) - (PORT d[12] (1485:1485:1485) (1525:1525:1525)) - (PORT clk (1641:1641:1641) (1668:1668:1668)) + (PORT clk (1344:1344:1344) (1361:1361:1361)) + (PORT asdata (1850:1850:1850) (1865:1865:1865)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) + (HOLD asdata (posedge clk) (144:144:144)) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.we_a_register) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[1\]\~0) (DELAY (ABSOLUTE - (PORT d[0] (895:895:895) (859:859:859)) - (PORT clk (1641:1641:1641) (1668:1668:1668)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1644:1644:1644) (1670:1670:1670)) - (PORT d[0] (1342:1342:1342) (1309:1309:1309)) + (PORT dataa (563:563:563) (546:546:546)) + (PORT datab (1081:1081:1081) (1108:1108:1108)) + (PORT datac (798:798:798) (775:775:775)) + (PORT datad (1277:1277:1277) (1277:1277:1277)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_a) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode252w\[2\]) (DELAY (ABSOLUTE - (PORT clk (1645:1645:1645) (1671:1671:1671)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + (PORT dataa (1090:1090:1090) (1101:1101:1101)) + (PORT datab (212:212:212) (267:267:267)) + (PORT datac (534:534:534) (530:530:530)) + (PORT datad (1484:1484:1484) (1469:1469:1469)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode252w\[2\]\~0) (DELAY (ABSOLUTE - (PORT clk (1645:1645:1645) (1671:1671:1671)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1645:1645:1645) (1671:1671:1671)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1645:1645:1645) (1671:1671:1671)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + (PORT datab (1908:1908:1908) (1977:1977:1977)) + (PORT datac (1203:1203:1203) (1297:1297:1297)) + (PORT datad (2828:2828:2828) (2878:2878:2878)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.datain_a_register) (DELAY (ABSOLUTE - (PORT clk (1608:1608:1608) (1634:1634:1634)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (879:879:879) (881:881:881)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (880:880:880) (882:882:882)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (880:880:880) (882:882:882)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (880:880:880) (882:882:882)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (877:877:877) (875:875:875)) + (PORT d[0] (939:939:939) (943:943:943)) (PORT clk (1638:1638:1638) (1665:1665:1665)) ) ) @@ -45494,22 +31979,22 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.addr_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1236:1236:1236) (1266:1266:1266)) - (PORT d[1] (2925:2925:2925) (3075:3075:3075)) - (PORT d[2] (3248:3248:3248) (3283:3283:3283)) - (PORT d[3] (2633:2633:2633) (2727:2727:2727)) - (PORT d[4] (2375:2375:2375) (2474:2474:2474)) - (PORT d[5] (2666:2666:2666) (2765:2765:2765)) - (PORT d[6] (1549:1549:1549) (1579:1579:1579)) - (PORT d[7] (1389:1389:1389) (1407:1407:1407)) - (PORT d[8] (3197:3197:3197) (3346:3346:3346)) - (PORT d[9] (2980:2980:2980) (3056:3056:3056)) - (PORT d[10] (4704:4704:4704) (4809:4809:4809)) - (PORT d[11] (1809:1809:1809) (1884:1884:1884)) - (PORT d[12] (1752:1752:1752) (1799:1799:1799)) + (PORT d[0] (2153:2153:2153) (2193:2193:2193)) + (PORT d[1] (917:917:917) (937:937:937)) + (PORT d[2] (2442:2442:2442) (2555:2555:2555)) + (PORT d[3] (2611:2611:2611) (2693:2693:2693)) + (PORT d[4] (680:680:680) (698:698:698)) + (PORT d[5] (1152:1152:1152) (1164:1164:1164)) + (PORT d[6] (914:914:914) (919:919:919)) + (PORT d[7] (1765:1765:1765) (1827:1827:1827)) + (PORT d[8] (1122:1122:1122) (1134:1134:1134)) + (PORT d[9] (903:903:903) (907:907:907)) + (PORT d[10] (623:623:623) (625:625:625)) + (PORT d[11] (1398:1398:1398) (1390:1390:1390)) + (PORT d[12] (2134:2134:2134) (2128:2128:2128)) (PORT clk (1635:1635:1635) (1663:1663:1663)) ) ) @@ -45519,10 +32004,10 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.we_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1579:1579:1579) (1512:1512:1512)) + (PORT d[0] (1613:1613:1613) (1574:1574:1574)) (PORT clk (1635:1635:1635) (1663:1663:1663)) ) ) @@ -45532,17 +32017,17 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.active_core_port_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.active_core_port_a) (DELAY (ABSOLUTE (PORT clk (1638:1638:1638) (1665:1665:1665)) - (PORT d[0] (1851:1851:1851) (1816:1816:1816)) + (PORT d[0] (1733:1733:1733) (1682:1682:1682)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.wpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.wpgen_a) (DELAY (ABSOLUTE (PORT clk (1639:1639:1639) (1666:1666:1666)) @@ -45552,7 +32037,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rpgen_a) (DELAY (ABSOLUTE (PORT clk (1639:1639:1639) (1666:1666:1666)) @@ -45562,7 +32047,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.ftpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.ftpgen_a) (DELAY (ABSOLUTE (PORT clk (1639:1639:1639) (1666:1666:1666)) @@ -45572,7 +32057,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rwpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rwpgen_a) (DELAY (ABSOLUTE (PORT clk (1639:1639:1639) (1666:1666:1666)) @@ -45582,7 +32067,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.dataout_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.dataout_a_register) (DELAY (ABSOLUTE (PORT clk (1602:1602:1602) (1629:1629:1629)) @@ -45596,7 +32081,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.active_core_port_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.active_core_port_b) (DELAY (ABSOLUTE (PORT clk (873:873:873) (876:876:876)) @@ -45605,7 +32090,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rpgen_b) (DELAY (ABSOLUTE (PORT clk (874:874:874) (877:877:877)) @@ -45614,7 +32099,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.ftpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.ftpgen_b) (DELAY (ABSOLUTE (PORT clk (874:874:874) (877:877:877)) @@ -45624,7 +32109,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rwpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rwpgen_b) (DELAY (ABSOLUTE (PORT clk (874:874:874) (877:877:877)) @@ -45633,12 +32118,40 @@ ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[1\]\~1) (DELAY (ABSOLUTE - (PORT d[0] (1083:1083:1083) (1033:1033:1033)) - (PORT clk (1636:1636:1636) (1662:1662:1662)) + (PORT dataa (1056:1056:1056) (1028:1028:1028)) + (PORT datab (181:181:181) (213:213:213)) + (PORT datac (1466:1466:1466) (1493:1493:1493)) + (PORT datad (1094:1094:1094) (1075:1075:1075)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1877:1877:1877) (1908:1908:1908)) + (PORT d[1] (1542:1542:1542) (1560:1560:1560)) + (PORT d[2] (2224:2224:2224) (2271:2271:2271)) + (PORT d[3] (2526:2526:2526) (2576:2576:2576)) + (PORT d[4] (952:952:952) (990:990:990)) + (PORT d[5] (1435:1435:1435) (1452:1452:1452)) + (PORT d[6] (2969:2969:2969) (2902:2902:2902)) + (PORT d[7] (1714:1714:1714) (1755:1755:1755)) + (PORT d[8] (1444:1444:1444) (1459:1459:1459)) + (PORT d[9] (3160:3160:3160) (3308:3308:3308)) + (PORT d[10] (1150:1150:1150) (1157:1157:1157)) + (PORT d[11] (1365:1365:1365) (1343:1343:1343)) + (PORT d[12] (1838:1838:1838) (1814:1814:1814)) + (PORT clk (1643:1643:1643) (1671:1671:1671)) ) ) (TIMINGCHECK @@ -45647,98 +32160,30 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) (DELAY (ABSOLUTE - (PORT d[0] (3407:3407:3407) (3481:3481:3481)) - (PORT d[1] (1566:1566:1566) (1666:1666:1666)) - (PORT d[2] (1830:1830:1830) (1838:1838:1838)) - (PORT d[3] (1999:1999:1999) (2026:2026:2026)) - (PORT d[4] (2024:2024:2024) (2084:2084:2084)) - (PORT d[5] (1272:1272:1272) (1335:1335:1335)) - (PORT d[6] (1389:1389:1389) (1420:1420:1420)) - (PORT d[7] (1608:1608:1608) (1645:1645:1645)) - (PORT d[8] (3346:3346:3346) (3464:3464:3464)) - (PORT d[9] (2907:2907:2907) (2973:2973:2973)) - (PORT d[10] (2940:2940:2940) (3016:3016:3016)) - (PORT d[11] (1927:1927:1927) (1965:1965:1965)) - (PORT d[12] (1320:1320:1320) (1344:1344:1344)) - (PORT clk (1633:1633:1633) (1660:1660:1660)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1539:1539:1539) (1481:1481:1481)) - (PORT clk (1633:1633:1633) (1660:1660:1660)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1636:1636:1636) (1662:1662:1662)) - (PORT d[0] (2458:2458:2458) (2384:2384:2384)) + (PORT clk (1643:1643:1643) (1671:1671:1671)) + (PORT d[0] (2138:2138:2138) (2188:2188:2188)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1637:1637:1637) (1663:1663:1663)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1637:1637:1637) (1663:1663:1663)) + (PORT clk (1644:1644:1644) (1672:1672:1672)) (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) ) ) ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1637:1637:1637) (1663:1663:1663)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1637:1637:1637) (1663:1663:1663)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1600:1600:1600) (1626:1626:1626)) + (PORT clk (1610:1610:1610) (1637:1637:1637)) (IOPATH (posedge clk) q (268:268:268) (268:268:268)) ) ) @@ -45749,395 +32194,711 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (871:871:871) (873:873:873)) + (PORT clk (881:881:881) (884:884:884)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (872:872:872) (874:874:874)) + (PORT clk (882:882:882) (885:885:885)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (872:872:872) (874:874:874)) + (PORT clk (882:882:882) (885:885:885)) (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (872:872:872) (874:874:874)) + (PORT clk (882:882:882) (885:885:885)) (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1679:1679:1679) (1712:1712:1712)) + (PORT d[1] (2154:2154:2154) (2154:2154:2154)) + (PORT d[2] (1897:1897:1897) (1979:1979:1979)) + (PORT d[3] (1749:1749:1749) (1798:1798:1798)) + (PORT d[4] (2160:2160:2160) (2153:2153:2153)) + (PORT d[5] (1577:1577:1577) (1586:1586:1586)) + (PORT d[6] (1611:1611:1611) (1621:1621:1621)) + (PORT d[7] (1426:1426:1426) (1459:1459:1459)) + (PORT d[8] (2019:2019:2019) (2080:2080:2080)) + (PORT d[9] (2815:2815:2815) (2915:2915:2915)) + (PORT d[10] (1475:1475:1475) (1532:1532:1532)) + (PORT d[11] (1824:1824:1824) (1838:1838:1838)) + (PORT d[12] (1926:1926:1926) (1885:1885:1885)) + (PORT clk (1635:1635:1635) (1664:1664:1664)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1635:1635:1635) (1664:1664:1664)) + (PORT d[0] (2349:2349:2349) (2293:2293:2293)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1636:1636:1636) (1665:1665:1665)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1602:1602:1602) (1630:1630:1630)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (877:877:877)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (878:878:878)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (878:878:878)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (878:878:878)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE CLOCK_50\~inputclkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (133:133:133) (124:124:124)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~43) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|address_reg_a\[0\]\~feeder) (DELAY (ABSOLUTE - (PORT dataa (911:911:911) (936:936:936)) - (PORT datab (1093:1093:1093) (1105:1105:1105)) - (PORT datac (774:774:774) (756:756:756)) - (PORT datad (976:976:976) (927:927:927)) - (IOPATH dataa combout (307:307:307) (323:323:323)) + (PORT datad (1435:1435:1435) (1425:1425:1425)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|address_reg_a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1356:1356:1356)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1356:1356:1356)) + (PORT asdata (506:506:506) (568:568:568)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (240:240:240) (313:313:313)) + (PORT datab (2407:2407:2407) (2457:2457:2457)) + (PORT datad (1477:1477:1477) (1544:1544:1544)) + (IOPATH dataa combout (300:300:300) (323:323:323)) (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~44) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|decode2\|eq_node\[1\]\~0) (DELAY (ABSOLUTE - (PORT dataa (1086:1086:1086) (1054:1054:1054)) - (PORT datab (1477:1477:1477) (1526:1526:1526)) - (PORT datac (1073:1073:1073) (1031:1031:1031)) - (PORT datad (287:287:287) (294:294:294)) + (PORT dataa (1090:1090:1090) (1096:1096:1096)) + (PORT datab (210:210:210) (263:263:263)) + (PORT datac (534:534:534) (527:527:527)) + (PORT datad (1486:1486:1486) (1465:1465:1465)) (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vram_address\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (858:858:858) (894:894:894)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vram_address\~0) + (DELAY + (ABSOLUTE + (PORT dataa (696:696:696) (754:754:754)) + (PORT datab (680:680:680) (735:735:735)) + (PORT datac (1065:1065:1065) (1070:1070:1070)) + (PORT datad (635:635:635) (672:672:672)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (324:324:324)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[0\]) (DELAY (ABSOLUTE - (PORT d[0] (2822:2822:2822) (2879:2879:2879)) - (PORT d[1] (2681:2681:2681) (2799:2799:2799)) - (PORT d[2] (1535:1535:1535) (1571:1571:1571)) - (PORT d[3] (1402:1402:1402) (1421:1421:1421)) - (PORT d[4] (1732:1732:1732) (1763:1763:1763)) - (PORT d[5] (1242:1242:1242) (1306:1306:1306)) - (PORT d[6] (1064:1064:1064) (1065:1065:1065)) - (PORT d[7] (1371:1371:1371) (1406:1406:1406)) - (PORT d[8] (2287:2287:2287) (2382:2382:2382)) - (PORT d[9] (3533:3533:3533) (3626:3626:3626)) - (PORT d[10] (2388:2388:2388) (2442:2442:2442)) - (PORT d[11] (1677:1677:1677) (1703:1703:1703)) - (PORT d[12] (1891:1891:1891) (1909:1909:1909)) - (PORT clk (1635:1635:1635) (1663:1663:1663)) + (PORT clk (1358:1358:1358) (1374:1374:1374)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1095:1095:1095) (1060:1060:1060)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vram_address\[1\]\~feeder) (DELAY (ABSOLUTE - (PORT clk (1635:1635:1635) (1663:1663:1663)) - (PORT d[0] (1181:1181:1181) (1144:1144:1144)) + (PORT datad (837:837:837) (862:862:862)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[1\]) (DELAY (ABSOLUTE - (PORT clk (1636:1636:1636) (1664:1664:1664)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1602:1602:1602) (1629:1629:1629)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + (PORT clk (1358:1358:1358) (1374:1374:1374)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1095:1095:1095) (1060:1060:1060)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vram_address\[2\]\~4) (DELAY (ABSOLUTE - (PORT clk (873:873:873) (876:876:876)) + (PORT datac (682:682:682) (748:748:748)) + (IOPATH datac combout (218:218:218) (215:215:215)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[2\]) (DELAY (ABSOLUTE - (PORT clk (874:874:874) (877:877:877)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (877:877:877)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (877:877:877)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1503:1503:1503) (1520:1520:1520)) - (PORT clk (1652:1652:1652) (1679:1679:1679)) + (PORT clk (1358:1358:1358) (1374:1374:1374)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1095:1095:1095) (1060:1060:1060)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add3\~0) (DELAY (ABSOLUTE - (PORT d[0] (2412:2412:2412) (2426:2426:2426)) - (PORT d[1] (1923:1923:1923) (2051:2051:2051)) - (PORT d[2] (2374:2374:2374) (2419:2419:2419)) - (PORT d[3] (2086:2086:2086) (2133:2133:2133)) - (PORT d[4] (2745:2745:2745) (2877:2877:2877)) - (PORT d[5] (1944:1944:1944) (2061:2061:2061)) - (PORT d[6] (1451:1451:1451) (1492:1492:1492)) - (PORT d[7] (2608:2608:2608) (2591:2591:2591)) - (PORT d[8] (2597:2597:2597) (2711:2711:2711)) - (PORT d[9] (1918:1918:1918) (1943:1943:1943)) - (PORT d[10] (1715:1715:1715) (1750:1750:1750)) - (PORT d[11] (3415:3415:3415) (3446:3446:3446)) - (PORT d[12] (1742:1742:1742) (1761:1761:1761)) - (PORT clk (1649:1649:1649) (1677:1677:1677)) + (PORT datac (683:683:683) (749:749:749)) + (PORT datad (1042:1042:1042) (1062:1062:1062)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1358:1358:1358) (1374:1374:1374)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1095:1095:1095) (1060:1060:1060)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.we_a_register) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add3\~1) (DELAY (ABSOLUTE - (PORT d[0] (2934:2934:2934) (2838:2838:2838)) - (PORT clk (1649:1649:1649) (1677:1677:1677)) + (PORT dataa (884:884:884) (922:922:922)) + (PORT datac (682:682:682) (748:748:748)) + (PORT datad (1042:1042:1042) (1063:1063:1063)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1358:1358:1358) (1374:1374:1374)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1095:1095:1095) (1060:1060:1060)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~0) (DELAY (ABSOLUTE - (PORT clk (1652:1652:1652) (1679:1679:1679)) - (PORT d[0] (2618:2618:2618) (2605:2605:2605)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1653:1653:1653) (1680:1680:1680)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1653:1653:1653) (1680:1680:1680)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1653:1653:1653) (1680:1680:1680)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1653:1653:1653) (1680:1680:1680)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1611:1611:1611) (1609:1609:1609)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2009:2009:2009) (2009:2009:2009)) - (PORT clk (1619:1619:1619) (1616:1616:1616)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4228:4228:4228) (4049:4049:4049)) - (PORT d[1] (4048:4048:4048) (3926:3926:3926)) - (PORT d[2] (4235:4235:4235) (4146:4146:4146)) - (PORT d[3] (4160:4160:4160) (4050:4050:4050)) - (PORT d[4] (4027:4027:4027) (3872:3872:3872)) - (PORT d[5] (4063:4063:4063) (3983:3983:3983)) - (PORT d[6] (4304:4304:4304) (4248:4248:4248)) - (PORT d[7] (3871:3871:3871) (3708:3708:3708)) - (PORT d[8] (4136:4136:4136) (4016:4016:4016)) - (PORT d[9] (4278:4278:4278) (4341:4341:4341)) - (PORT d[10] (4175:4175:4175) (4089:4089:4089)) - (PORT d[11] (4347:4347:4347) (4198:4198:4198)) - (PORT d[12] (4172:4172:4172) (4111:4111:4111)) - (PORT clk (1616:1616:1616) (1613:1613:1613)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1619:1619:1619) (1616:1616:1616)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1620:1620:1620) (1617:1617:1617)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1620:1620:1620) (1617:1617:1617)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1620:1620:1620) (1617:1617:1617)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1620:1620:1620) (1617:1617:1617)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + (PORT dataa (864:864:864) (901:901:901)) + (PORT datab (1151:1151:1151) (1157:1157:1157)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH dataa cout (376:376:376) (275:275:275)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~40) + (INSTANCE ula_\|video_\|Add4\~2) (DELAY (ABSOLUTE - (PORT dataa (1253:1253:1253) (1237:1237:1237)) - (PORT datab (250:250:250) (328:328:328)) - (PORT datac (1247:1247:1247) (1214:1214:1214)) - (PORT datad (1361:1361:1361) (1371:1371:1371)) - (IOPATH dataa combout (318:318:318) (327:327:327)) + (PORT datab (912:912:912) (937:937:937)) (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~4) + (DELAY + (ABSOLUTE + (PORT datab (1082:1082:1082) (1086:1086:1086)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~6) + (DELAY + (ABSOLUTE + (PORT datab (705:705:705) (748:748:748)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1357:1357:1357) (1373:1373:1373)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1162:1162:1162) (1147:1147:1147)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~8) + (DELAY + (ABSOLUTE + (PORT datab (874:874:874) (900:900:900)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1357:1357:1357) (1373:1373:1373)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1162:1162:1162) (1147:1147:1147)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~10) + (DELAY + (ABSOLUTE + (PORT dataa (882:882:882) (919:919:919)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH dataa cout (376:376:376) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1357:1357:1357) (1373:1373:1373)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1162:1162:1162) (1147:1147:1147)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1051:1051:1051) (1063:1063:1063)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH dataa cout (376:376:376) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Selector6\~0) + (DELAY + (ABSOLUTE + (PORT datab (881:881:881) (906:906:906)) + (PORT datac (296:296:296) (308:308:308)) + (PORT datad (323:323:323) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vram_address\[9\]\~1) (DELAY (ABSOLUTE - (PORT d[0] (1461:1461:1461) (1472:1472:1472)) - (PORT clk (1656:1656:1656) (1683:1683:1683)) + (PORT dataa (691:691:691) (753:753:753)) + (PORT datab (679:679:679) (734:734:734)) + (PORT datac (1065:1065:1065) (1074:1074:1074)) + (PORT datad (636:636:636) (675:675:675)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1358:1358:1358) (1374:1374:1374)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1164:1164:1164) (1146:1146:1146)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~14) + (DELAY + (ABSOLUTE + (PORT datad (835:835:835) (865:865:865)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Selector5\~0) + (DELAY + (ABSOLUTE + (PORT datab (878:878:878) (906:906:906)) + (PORT datac (323:323:323) (328:328:328)) + (PORT datad (323:323:323) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1358:1358:1358) (1374:1374:1374)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1164:1164:1164) (1146:1146:1146)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vram_address\[10\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (692:692:692) (747:747:747)) + (PORT datab (676:676:676) (728:728:728)) + (PORT datac (1069:1069:1069) (1074:1074:1074)) + (PORT datad (640:640:640) (674:674:674)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vram_address\[10\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (698:698:698) (756:756:756)) + (PORT datab (577:577:577) (562:562:562)) + (PORT datad (161:161:161) (183:183:183)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1358:1358:1358) (1374:1374:1374)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Selector3\~0) + (DELAY + (ABSOLUTE + (PORT datac (849:849:849) (875:875:875)) + (PORT datad (327:327:327) (328:328:328)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1358:1358:1358) (1374:1374:1374)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1164:1164:1164) (1146:1146:1146)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Selector2\~0) + (DELAY + (ABSOLUTE + (PORT datac (849:849:849) (875:875:875)) + (PORT datad (325:325:325) (326:326:326)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1358:1358:1358) (1374:1374:1374)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1164:1164:1164) (1146:1146:1146)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1289:1289:1289) (1306:1306:1306)) + (PORT clk (1646:1646:1646) (1673:1673:1673)) ) ) (TIMINGCHECK @@ -46146,23 +32907,23 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2158:2158:2158) (2147:2147:2147)) - (PORT d[1] (1907:1907:1907) (2023:2023:2023)) - (PORT d[2] (2137:2137:2137) (2217:2217:2217)) - (PORT d[3] (2113:2113:2113) (2196:2196:2196)) - (PORT d[4] (2735:2735:2735) (2857:2857:2857)) - (PORT d[5] (2220:2220:2220) (2324:2324:2324)) - (PORT d[6] (1719:1719:1719) (1765:1765:1765)) - (PORT d[7] (2330:2330:2330) (2325:2325:2325)) - (PORT d[8] (2908:2908:2908) (3035:3035:3035)) - (PORT d[9] (1649:1649:1649) (1670:1670:1670)) - (PORT d[10] (1675:1675:1675) (1693:1693:1693)) - (PORT d[11] (2723:2723:2723) (2755:2755:2755)) - (PORT d[12] (1741:1741:1741) (1769:1769:1769)) - (PORT clk (1653:1653:1653) (1681:1681:1681)) + (PORT d[0] (2563:2563:2563) (2654:2654:2654)) + (PORT d[1] (2823:2823:2823) (2851:2851:2851)) + (PORT d[2] (1760:1760:1760) (1817:1817:1817)) + (PORT d[3] (2492:2492:2492) (2605:2605:2605)) + (PORT d[4] (2751:2751:2751) (2812:2812:2812)) + (PORT d[5] (3226:3226:3226) (3243:3243:3243)) + (PORT d[6] (2002:2002:2002) (2051:2051:2051)) + (PORT d[7] (1801:1801:1801) (1883:1883:1883)) + (PORT d[8] (2525:2525:2525) (2557:2557:2557)) + (PORT d[9] (2845:2845:2845) (2871:2871:2871)) + (PORT d[10] (3127:3127:3127) (3301:3301:3301)) + (PORT d[11] (2769:2769:2769) (2843:2843:2843)) + (PORT d[12] (1901:1901:1901) (1921:1921:1921)) + (PORT clk (1643:1643:1643) (1671:1671:1671)) ) ) (TIMINGCHECK @@ -46171,11 +32932,11 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.we_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2037:2037:2037) (1970:1970:1970)) - (PORT clk (1653:1653:1653) (1681:1681:1681)) + (PORT d[0] (2859:2859:2859) (2801:2801:2801)) + (PORT clk (1643:1643:1643) (1671:1671:1671)) ) ) (TIMINGCHECK @@ -46184,57 +32945,375 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1656:1656:1656) (1683:1683:1683)) - (PORT d[0] (2843:2843:2843) (2837:2837:2837)) + (PORT clk (1646:1646:1646) (1673:1673:1673)) + (PORT d[0] (3056:3056:3056) (3030:3030:3030)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1657:1657:1657) (1684:1684:1684)) + (PORT clk (1647:1647:1647) (1674:1674:1674)) (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1657:1657:1657) (1684:1684:1684)) + (PORT clk (1647:1647:1647) (1674:1674:1674)) (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1657:1657:1657) (1684:1684:1684)) + (PORT clk (1647:1647:1647) (1674:1674:1674)) (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1657:1657:1657) (1684:1684:1684)) + (PORT clk (1647:1647:1647) (1674:1674:1674)) (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1605:1605:1605) (1603:1603:1603)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2494:2494:2494) (2622:2622:2622)) + (PORT clk (1613:1613:1613) (1610:1610:1610)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3797:3797:3797) (3714:3714:3714)) + (PORT d[1] (3836:3836:3836) (3771:3771:3771)) + (PORT d[2] (3825:3825:3825) (3707:3707:3707)) + (PORT d[3] (3842:3842:3842) (3797:3797:3797)) + (PORT d[4] (3885:3885:3885) (3775:3775:3775)) + (PORT d[5] (4148:4148:4148) (4045:4045:4045)) + (PORT d[6] (3945:3945:3945) (3854:3854:3854)) + (PORT d[7] (3901:3901:3901) (3803:3803:3803)) + (PORT d[8] (3899:3899:3899) (3802:3802:3802)) + (PORT d[9] (3968:3968:3968) (3907:3907:3907)) + (PORT d[10] (3831:3831:3831) (3724:3724:3724)) + (PORT d[11] (4048:4048:4048) (3925:3925:3925)) + (PORT d[12] (3735:3735:3735) (3659:3659:3659)) + (PORT clk (1610:1610:1610) (1607:1607:1607)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1613:1613:1613) (1610:1610:1610)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1614:1614:1614) (1611:1611:1611)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1614:1614:1614) (1611:1611:1611)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1614:1614:1614) (1611:1611:1611)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1614:1614:1614) (1611:1611:1611)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|decode2\|eq_node\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1087:1087:1087) (1094:1094:1094)) + (PORT datab (213:213:213) (268:268:268)) + (PORT datac (531:531:531) (529:529:529)) + (PORT datad (1483:1483:1483) (1468:1468:1468)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1479:1479:1479) (1493:1493:1493)) + (PORT clk (1655:1655:1655) (1682:1682:1682)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2557:2557:2557) (2636:2636:2636)) + (PORT d[1] (2505:2505:2505) (2530:2530:2530)) + (PORT d[2] (2025:2025:2025) (2096:2096:2096)) + (PORT d[3] (2170:2170:2170) (2276:2276:2276)) + (PORT d[4] (2474:2474:2474) (2518:2518:2518)) + (PORT d[5] (2953:2953:2953) (2963:2963:2963)) + (PORT d[6] (2265:2265:2265) (2318:2318:2318)) + (PORT d[7] (1847:1847:1847) (1942:1942:1942)) + (PORT d[8] (2248:2248:2248) (2267:2267:2267)) + (PORT d[9] (2474:2474:2474) (2509:2509:2509)) + (PORT d[10] (3788:3788:3788) (4002:4002:4002)) + (PORT d[11] (2537:2537:2537) (2620:2620:2620)) + (PORT d[12] (2393:2393:2393) (2397:2397:2397)) + (PORT clk (1652:1652:1652) (1680:1680:1680)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2295:2295:2295) (2239:2239:2239)) + (PORT clk (1652:1652:1652) (1680:1680:1680)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1655:1655:1655) (1682:1682:1682)) + (PORT d[0] (3328:3328:3328) (3336:3336:3336)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1656:1656:1656) (1683:1683:1683)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1656:1656:1656) (1683:1683:1683)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1656:1656:1656) (1683:1683:1683)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1656:1656:1656) (1683:1683:1683)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1614:1614:1614) (1612:1612:1612)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2738:2738:2738) (2874:2874:2874)) + (PORT clk (1622:1622:1622) (1619:1619:1619)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3786:3786:3786) (3661:3661:3661)) + (PORT d[1] (3815:3815:3815) (3747:3747:3747)) + (PORT d[2] (3846:3846:3846) (3736:3736:3736)) + (PORT d[3] (3818:3818:3818) (3752:3752:3752)) + (PORT d[4] (3907:3907:3907) (3864:3864:3864)) + (PORT d[5] (3931:3931:3931) (3811:3811:3811)) + (PORT d[6] (4034:4034:4034) (3909:3909:3909)) + (PORT d[7] (3747:3747:3747) (3658:3658:3658)) + (PORT d[8] (4025:4025:4025) (3907:3907:3907)) + (PORT d[9] (3910:3910:3910) (3878:3878:3878)) + (PORT d[10] (3821:3821:3821) (3713:3713:3713)) + (PORT d[11] (3999:3999:3999) (3816:3816:3816)) + (PORT d[12] (3907:3907:3907) (3834:3834:3834)) + (PORT clk (1619:1619:1619) (1616:1616:1616)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1622:1622:1622) (1619:1619:1619)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1623:1623:1623) (1620:1620:1620)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1623:1623:1623) (1620:1620:1620)) + (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1623:1623:1623) (1620:1620:1620)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1623:1623:1623) (1620:1620:1620)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_b_register) (DELAY (ABSOLUTE (PORT clk (1615:1615:1615) (1613:1613:1613)) @@ -46246,245 +33325,47 @@ (HOLD d (posedge clk) (142:142:142)) ) ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2299:2299:2299) (2304:2304:2304)) - (PORT clk (1623:1623:1623) (1620:1620:1620)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4203:4203:4203) (4062:4062:4062)) - (PORT d[1] (3847:3847:3847) (3718:3718:3718)) - (PORT d[2] (4210:4210:4210) (4080:4080:4080)) - (PORT d[3] (4242:4242:4242) (4139:4139:4139)) - (PORT d[4] (4247:4247:4247) (4105:4105:4105)) - (PORT d[5] (4340:4340:4340) (4259:4259:4259)) - (PORT d[6] (4317:4317:4317) (4290:4290:4290)) - (PORT d[7] (3916:3916:3916) (3762:3762:3762)) - (PORT d[8] (4362:4362:4362) (4253:4253:4253)) - (PORT d[9] (4208:4208:4208) (4238:4238:4238)) - (PORT d[10] (4238:4238:4238) (4121:4121:4121)) - (PORT d[11] (4183:4183:4183) (4093:4093:4093)) - (PORT d[12] (4275:4275:4275) (4202:4202:4202)) - (PORT clk (1620:1620:1620) (1617:1617:1617)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1623:1623:1623) (1620:1620:1620)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1624:1624:1624) (1621:1621:1621)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1624:1624:1624) (1621:1621:1621)) - (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1624:1624:1624) (1621:1621:1621)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1624:1624:1624) (1621:1621:1621)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1616:1616:1616) (1614:1614:1614)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (911:911:911) (929:929:929)) - (PORT d[1] (916:916:916) (933:933:933)) - (PORT d[2] (1136:1136:1136) (1138:1138:1138)) - (PORT d[3] (1217:1217:1217) (1244:1244:1244)) - (PORT d[4] (2415:2415:2415) (2527:2527:2527)) - (PORT d[5] (2765:2765:2765) (2905:2905:2905)) - (PORT d[6] (908:908:908) (915:915:915)) - (PORT d[7] (1185:1185:1185) (1202:1202:1202)) - (PORT d[8] (958:958:958) (970:970:970)) - (PORT d[9] (901:901:901) (908:908:908)) - (PORT d[10] (1223:1223:1223) (1237:1237:1237)) - (PORT d[11] (2375:2375:2375) (2471:2471:2471)) - (PORT d[12] (1196:1196:1196) (1217:1217:1217)) - (PORT clk (1643:1643:1643) (1670:1670:1670)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1643:1643:1643) (1670:1670:1670)) - (PORT d[0] (515:515:515) (535:535:535)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1644:1644:1644) (1671:1671:1671)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1610:1610:1610) (1636:1636:1636)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (881:881:881) (883:883:883)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (884:884:884)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (884:884:884)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (882:882:882) (884:884:884)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~41) + (INSTANCE Selector1\~0) (DELAY (ABSOLUTE - (PORT dataa (1192:1192:1192) (1154:1154:1154)) - (PORT datab (816:816:816) (796:796:796)) - (PORT datac (802:802:802) (785:785:785)) - (PORT datad (166:166:166) (192:192:192)) + (PORT dataa (1282:1282:1282) (1369:1369:1369)) + (PORT datab (809:809:809) (800:800:800)) + (PORT datac (1334:1334:1334) (1340:1340:1340)) + (PORT datad (1340:1340:1340) (1339:1339:1339)) (IOPATH dataa combout (329:329:329) (332:332:332)) (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~42) + (INSTANCE Selector1\~1) (DELAY (ABSOLUTE - (PORT dataa (191:191:191) (230:230:230)) - (PORT datab (253:253:253) (331:331:331)) - (PORT datac (1507:1507:1507) (1487:1487:1487)) + (PORT dataa (1282:1282:1282) (1370:1370:1370)) + (PORT datab (1044:1044:1044) (1040:1040:1040)) + (PORT datac (1285:1285:1285) (1278:1278:1278)) (PORT datad (159:159:159) (179:179:179)) - (IOPATH dataa combout (307:307:307) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~105) + (INSTANCE D\[1\]\~81) (DELAY (ABSOLUTE - (PORT dataa (182:182:182) (218:218:218)) - (PORT datab (855:855:855) (894:894:894)) - (PORT datac (1100:1100:1100) (1115:1115:1115)) - (PORT datad (531:531:531) (535:535:535)) + (PORT dataa (185:185:185) (222:222:222)) + (PORT datab (1110:1110:1110) (1157:1157:1157)) + (PORT datac (2534:2534:2534) (2557:2557:2557)) + (PORT datad (285:285:285) (292:292:292)) (IOPATH dataa combout (318:318:318) (323:323:323)) (IOPATH datab combout (295:295:295) (300:300:300)) (IOPATH datac combout (218:218:218) (216:216:216)) @@ -46494,15 +33375,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~45) + (INSTANCE D\[1\]\~31) (DELAY (ABSOLUTE - (PORT dataa (344:344:344) (368:368:368)) - (PORT datab (210:210:210) (250:250:250)) - (PORT datac (163:163:163) (196:196:196)) - (PORT datad (168:168:168) (192:192:192)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (336:336:336) (337:337:337)) + (PORT dataa (827:827:827) (824:824:824)) + (PORT datab (833:833:833) (831:831:831)) + (PORT datac (318:318:318) (332:332:332)) + (PORT datad (165:165:165) (189:189:189)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (295:295:295) (300:300:300)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -46510,15 +33391,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~46) + (INSTANCE D\[1\]\~32) (DELAY (ABSOLUTE - (PORT dataa (385:385:385) (443:443:443)) - (PORT datab (210:210:210) (251:251:251)) - (PORT datac (1059:1059:1059) (1047:1047:1047)) - (PORT datad (157:157:157) (178:178:178)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) + (PORT dataa (827:827:827) (818:818:818)) + (PORT datab (880:880:880) (923:923:923)) + (PORT datac (1419:1419:1419) (1390:1390:1390)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -46526,28 +33407,60 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[2\]) + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[1\]) (DELAY (ABSOLUTE - (PORT dataa (902:902:902) (934:934:934)) - (PORT datab (593:593:593) (598:598:598)) - (PORT datac (552:552:552) (544:544:544)) - (PORT datad (177:177:177) (198:198:198)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT dataa (1317:1317:1317) (1315:1315:1315)) + (PORT datab (200:200:200) (234:234:234)) + (PORT datac (1054:1054:1054) (1036:1036:1036)) + (PORT datad (340:340:340) (351:351:351)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_re\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1123:1123:1123) (1150:1150:1150)) + (PORT datab (207:207:207) (245:245:245)) + (PORT datac (877:877:877) (912:912:912)) + (PORT datad (896:896:896) (933:933:933)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_2) + (DELAY + (ABSOLUTE + (PORT dataa (1318:1318:1318) (1313:1313:1313)) + (PORT datab (1010:1010:1010) (986:986:986)) + (PORT datac (1044:1044:1044) (1049:1049:1049)) + (PORT datad (703:703:703) (676:676:676)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[2\]) + (INSTANCE z80_\|data_pins_\|dout\[1\]) (DELAY (ABSOLUTE - (PORT clk (1346:1346:1346) (1357:1357:1357)) + (PORT clk (1348:1348:1348) (1359:1359:1359)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (1141:1141:1141) (1105:1105:1105)) + (PORT ena (744:744:744) (751:751:751)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -46558,13 +33471,77 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[2\]\~12) + (INSTANCE z80_\|bus_control_\|db\[1\]\~11) (DELAY (ABSOLUTE - (PORT datab (852:852:852) (848:848:848)) - (PORT datac (871:871:871) (900:900:900)) - (PORT datad (199:199:199) (229:229:229)) - (IOPATH datab combout (275:275:275) (275:275:275)) + (PORT dataa (375:375:375) (400:400:400)) + (PORT datab (183:183:183) (216:216:216)) + (PORT datac (215:215:215) (283:283:283)) + (PORT datad (544:544:544) (541:541:541)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1362:1362:1362)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1388:1388:1388) (1360:1360:1360)) + (PORT ena (1550:1550:1550) (1520:1520:1520)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal2\~0) + (DELAY + (ABSOLUTE + (PORT datab (1565:1565:1565) (1600:1600:1600)) + (PORT datac (606:606:606) (632:632:632)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~15) + (DELAY + (ABSOLUTE + (PORT dataa (2021:2021:2021) (2092:2092:2092)) + (PORT datab (898:898:898) (939:939:939)) + (PORT datac (1079:1079:1079) (1099:1099:1099)) + (PORT datad (824:824:824) (862:862:862)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~39) + (DELAY + (ABSOLUTE + (PORT dataa (938:938:938) (993:993:993)) + (PORT datab (1147:1147:1147) (1169:1169:1169)) + (PORT datac (822:822:822) (846:846:846)) + (PORT datad (917:917:917) (946:946:946)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -46572,15 +33549,93 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[2\]\~13) + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~36) (DELAY (ABSOLUTE - (PORT dataa (405:405:405) (449:449:449)) - (PORT datab (215:215:215) (253:253:253)) - (PORT datac (203:203:203) (251:251:251)) - (PORT datad (159:159:159) (180:180:180)) + (PORT datab (559:559:559) (573:573:573)) + (PORT datac (1084:1084:1084) (1089:1089:1089)) + (PORT datad (577:577:577) (587:587:587)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~4) + (DELAY + (ABSOLUTE + (PORT dataa (818:818:818) (839:839:839)) + (PORT datab (854:854:854) (867:867:867)) + (PORT datac (1484:1484:1484) (1560:1560:1560)) + (PORT datad (1488:1488:1488) (1548:1548:1548)) (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~16) + (DELAY + (ABSOLUTE + (PORT dataa (335:335:335) (351:351:351)) + (PORT datab (1934:1934:1934) (1971:1971:1971)) + (PORT datac (1342:1342:1342) (1355:1355:1355)) + (PORT datad (283:283:283) (288:288:288)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~17) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (218:218:218)) + (PORT datab (192:192:192) (230:230:230)) + (PORT datac (1225:1225:1225) (1188:1188:1188)) + (PORT datad (160:160:160) (182:182:182)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1827:1827:1827) (1875:1875:1875)) + (PORT datab (2075:2075:2075) (2116:2116:2116)) + (PORT datac (775:775:775) (802:802:802)) + (PORT datad (600:600:600) (612:612:612)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1054:1054:1054) (1055:1055:1055)) + (PORT datab (1923:1923:1923) (1964:1964:1964)) + (PORT datac (784:784:784) (791:791:791)) + (PORT datad (957:957:957) (962:962:962)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -46588,15 +33643,177 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[2\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1361:1361:1361)) + (PORT asdata (1724:1724:1724) (1745:1745:1745)) + (PORT ena (904:904:904) (889:889:889)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1361:1361:1361)) + (PORT asdata (1723:1723:1723) (1745:1745:1745)) + (PORT ena (735:735:735) (733:733:733)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~44) + (DELAY + (ABSOLUTE + (PORT dataa (220:220:220) (292:292:292)) + (PORT datab (227:227:227) (278:278:278)) + (PORT datad (211:211:211) (239:239:239)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1351:1351:1351) (1372:1372:1372)) + (PORT asdata (492:492:492) (522:522:522)) + (PORT ena (892:892:892) (882:882:882)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1351:1351:1351) (1372:1372:1372)) + (PORT asdata (491:491:491) (521:521:521)) + (PORT ena (893:893:893) (883:883:883)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~43) + (DELAY + (ABSOLUTE + (PORT dataa (382:382:382) (413:413:413)) + (PORT datab (400:400:400) (420:420:420)) + (PORT datad (198:198:198) (256:256:256)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1344:1344:1344) (1361:1361:1361)) + (PORT asdata (1145:1145:1145) (1143:1143:1143)) + (PORT ena (1175:1175:1175) (1148:1148:1148)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1362:1362:1362)) + (PORT asdata (1487:1487:1487) (1506:1506:1506)) + (PORT ena (1104:1104:1104) (1087:1087:1087)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (809:809:809) (834:834:834)) + (PORT datab (539:539:539) (547:547:547)) + (PORT datad (939:939:939) (913:913:913)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~47) + (DELAY + (ABSOLUTE + (PORT datab (881:881:881) (890:890:890)) + (PORT datad (587:587:587) (583:583:583)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1386:1386:1386) (1396:1396:1396)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[3\]) (DELAY (ABSOLUTE (PORT clk (1343:1343:1343) (1360:1360:1360)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1395:1395:1395) (1367:1367:1367)) - (PORT ena (1130:1130:1130) (1103:1103:1103)) + (PORT ena (716:716:716) (714:714:714)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) ) (TIMINGCHECK @@ -46605,242 +33822,31 @@ ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal3\~1) + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[3\]) (DELAY (ABSOLUTE - (PORT datac (1336:1336:1336) (1363:1363:1363)) - (PORT datad (2097:2097:2097) (2151:2151:2151)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (PORT clk (1343:1343:1343) (1360:1360:1360)) + (PORT asdata (1131:1131:1131) (1119:1119:1119)) + (PORT ena (1321:1321:1321) (1324:1324:1324)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal43\~0) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~49) (DELAY (ABSOLUTE - (PORT dataa (873:873:873) (871:871:871)) - (PORT datab (866:866:866) (898:898:898)) - (PORT datac (1486:1486:1486) (1580:1580:1580)) - (PORT datad (1135:1135:1135) (1165:1165:1165)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|test1\~2) - (DELAY - (ABSOLUTE - (PORT dataa (181:181:181) (217:217:217)) - (PORT datab (198:198:198) (231:231:231)) - (PORT datac (178:178:178) (213:213:213)) - (PORT datad (177:177:177) (199:199:199)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|test1\~3) - (DELAY - (ABSOLUTE - (PORT dataa (781:781:781) (779:779:779)) - (PORT datab (1913:1913:1913) (1971:1971:1971)) - (PORT datac (1168:1168:1168) (1229:1229:1229)) - (PORT datad (1001:1001:1001) (989:989:989)) + (PORT dataa (640:640:640) (683:683:683)) + (PORT datab (349:349:349) (397:397:397)) + (PORT datad (341:341:341) (353:353:353)) (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|in_nmi_ALTERA_SYNTHESIZED) - (DELAY - (ABSOLUTE - (PORT clk (1354:1354:1354) (1375:1375:1375)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1413:1413:1413) (1379:1379:1379)) - (PORT ena (1556:1556:1556) (1512:1512:1512)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|clk_delay_\|SYNTHESIZED_WIRE_4) - (DELAY - (ABSOLUTE - (PORT dataa (1132:1132:1132) (1162:1162:1162)) - (PORT datab (1910:1910:1910) (1969:1969:1969)) - (PORT datac (1180:1180:1180) (1261:1261:1261)) - (PORT datad (1734:1734:1734) (1725:1725:1725)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|clk_delay_\|SYNTHESIZED_WIRE_7) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1370:1370:1370)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1408:1408:1408) (1374:1374:1374)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|clk_delay_\|hold_clk_iorq) - (DELAY - (ABSOLUTE - (PORT datab (230:230:230) (301:301:301)) - (PORT datad (207:207:207) (267:267:267)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_T1_ff) - (DELAY - (ABSOLUTE - (PORT clk (1362:1362:1362) (1383:1383:1383)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1408:1408:1408) (1379:1379:1379)) - (PORT ena (1790:1790:1790) (1839:1839:1839)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_13) - (DELAY - (ABSOLUTE - (PORT dataa (242:242:242) (314:314:314)) - (PORT datac (1030:1030:1030) (1031:1031:1031)) - (PORT datad (1041:1041:1041) (1032:1032:1032)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_T2_ff) - (DELAY - (ABSOLUTE - (PORT clk (1362:1362:1362) (1383:1383:1383)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1408:1408:1408) (1379:1379:1379)) - (PORT ena (1790:1790:1790) (1839:1839:1839)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|resets_\|x3) - (DELAY - (ABSOLUTE - (PORT dataa (2203:2203:2203) (2261:2261:2261)) - (PORT datac (217:217:217) (284:284:284)) - (PORT datad (1256:1256:1256) (1355:1355:1355)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_12) - (DELAY - (ABSOLUTE - (PORT clk (1340:1340:1340) (1357:1357:1357)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1667:1667:1667) (1646:1646:1646)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_clkctrl") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_12\~clkctrl) - (DELAY - (ABSOLUTE - (PORT inclk[0] (1453:1453:1453) (1482:1482:1482)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_M1_ff) - (DELAY - (ABSOLUTE - (PORT clk (1362:1362:1362) (1383:1383:1383)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1408:1408:1408) (1379:1379:1379)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|DFFE_M2_ff\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1060:1060:1060) (1064:1064:1064)) - (PORT datab (255:255:255) (332:332:332)) - (PORT datad (1047:1047:1047) (1037:1037:1037)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -46848,339 +33854,117 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_M2_ff) + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[3\]) (DELAY (ABSOLUTE - (PORT clk (1362:1362:1362) (1383:1383:1383)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1408:1408:1408) (1379:1379:1379)) + (PORT clk (1350:1350:1350) (1371:1371:1371)) + (PORT asdata (870:870:870) (863:863:863)) + (PORT ena (1138:1138:1138) (1126:1126:1126)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (313:313:313) (319:319:319)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1350:1350:1350) (1371:1371:1371)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1110:1110:1110) (1080:1080:1080)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) ) (TIMINGCHECK (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~3) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~45) (DELAY (ABSOLUTE - (PORT datac (968:968:968) (1046:1046:1046)) - (PORT datad (1866:1866:1866) (1882:1882:1882)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT dataa (645:645:645) (674:674:674)) + (PORT datab (647:647:647) (664:664:664)) + (PORT datad (198:198:198) (255:255:255)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~11) + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[3\]) (DELAY (ABSOLUTE - (PORT dataa (1349:1349:1349) (1370:1370:1370)) - (PORT datab (785:785:785) (802:802:802)) - (PORT datac (735:735:735) (729:729:729)) - (PORT datad (611:611:611) (629:629:629)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (PORT clk (1344:1344:1344) (1361:1361:1361)) + (PORT asdata (1145:1145:1145) (1146:1146:1146)) + (PORT ena (1131:1131:1131) (1119:1119:1119)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1362:1362:1362)) + (PORT asdata (1488:1488:1488) (1507:1507:1507)) + (PORT ena (1115:1115:1115) (1103:1103:1103)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~8) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~48) (DELAY (ABSOLUTE - (PORT dataa (921:921:921) (957:957:957)) - (PORT datab (617:617:617) (624:624:624)) - (PORT datac (880:880:880) (892:892:892)) - (PORT datad (2085:2085:2085) (2090:2090:2090)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~9) - (DELAY - (ABSOLUTE - (PORT dataa (805:805:805) (809:809:809)) - (PORT datab (780:780:780) (771:771:771)) - (PORT datac (859:859:859) (884:884:884)) - (PORT datad (372:372:372) (382:382:382)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~10) - (DELAY - (ABSOLUTE - (PORT dataa (622:622:622) (644:644:644)) - (PORT datab (310:310:310) (327:327:327)) - (PORT datac (1356:1356:1356) (1374:1374:1374)) - (PORT datad (1918:1918:1918) (1931:1931:1931)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~12) - (DELAY - (ABSOLUTE - (PORT dataa (379:379:379) (380:380:380)) - (PORT datab (180:180:180) (213:213:213)) - (PORT datac (155:155:155) (185:185:185)) - (PORT datad (165:165:165) (190:190:190)) + (PORT dataa (589:589:589) (620:620:620)) + (PORT datab (677:677:677) (707:707:707)) + (PORT datad (620:620:620) (650:650:650)) (IOPATH dataa combout (309:309:309) (326:326:326)) (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~15) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~50) (DELAY (ABSOLUTE - (PORT dataa (1847:1847:1847) (1878:1878:1878)) - (PORT datab (798:798:798) (792:792:792)) - (PORT datac (1341:1341:1341) (1341:1341:1341)) - (PORT datad (165:165:165) (189:189:189)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~6) - (DELAY - (ABSOLUTE - (PORT dataa (209:209:209) (249:249:249)) - (PORT datab (212:212:212) (254:254:254)) - (PORT datac (326:326:326) (340:340:340)) - (PORT datad (982:982:982) (970:970:970)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~7) - (DELAY - (ABSOLUTE - (PORT dataa (210:210:210) (252:252:252)) - (PORT datab (181:181:181) (213:213:213)) - (PORT datac (915:915:915) (941:941:941)) - (PORT datad (730:730:730) (727:727:727)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~13) - (DELAY - (ABSOLUTE - (PORT datab (1021:1021:1021) (1030:1030:1030)) + (PORT dataa (568:568:568) (590:590:590)) + (PORT datab (597:597:597) (583:583:583)) (PORT datac (156:156:156) (187:187:187)) - (PORT datad (296:296:296) (297:297:297)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~39) - (DELAY - (ABSOLUTE - (PORT datac (715:715:715) (700:700:700)) - (PORT datad (563:563:563) (569:569:569)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~5) - (DELAY - (ABSOLUTE - (PORT dataa (189:189:189) (226:226:226)) - (PORT datab (1883:1883:1883) (1863:1863:1863)) - (PORT datac (580:580:580) (600:600:600)) - (PORT datad (316:316:316) (307:307:307)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~14) - (DELAY - (ABSOLUTE - (PORT dataa (776:776:776) (748:748:748)) - (PORT datab (808:808:808) (829:829:829)) - (PORT datac (950:950:950) (937:937:937)) - (PORT datad (496:496:496) (489:489:489)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_15) - (DELAY - (ABSOLUTE - (PORT datab (248:248:248) (320:320:320)) - (PORT datac (1029:1029:1029) (1026:1026:1026)) - (PORT datad (1051:1051:1051) (1039:1039:1039)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_T4_ff) - (DELAY - (ABSOLUTE - (PORT clk (1362:1362:1362) (1383:1383:1383)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1408:1408:1408) (1379:1379:1379)) - (PORT ena (1790:1790:1790) (1839:1839:1839)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_16) - (DELAY - (ABSOLUTE - (PORT dataa (1053:1053:1053) (1051:1051:1051)) - (PORT datac (222:222:222) (293:293:293)) - (PORT datad (1051:1051:1051) (1043:1043:1043)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_T5_ff) - (DELAY - (ABSOLUTE - (PORT clk (1362:1362:1362) (1383:1383:1383)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1408:1408:1408) (1379:1379:1379)) - (PORT ena (1790:1790:1790) (1839:1839:1839)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_17) - (DELAY - (ABSOLUTE - (PORT datab (241:241:241) (310:310:310)) - (PORT datac (1013:1013:1013) (1010:1010:1010)) - (PORT datad (1055:1055:1055) (1045:1045:1045)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|T6) - (DELAY - (ABSOLUTE - (PORT clk (1362:1362:1362) (1383:1383:1383)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1408:1408:1408) (1379:1379:1379)) - (PORT ena (1790:1790:1790) (1839:1839:1839)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~13) - (DELAY - (ABSOLUTE - (PORT dataa (564:564:564) (569:569:569)) - (PORT datab (816:816:816) (818:818:818)) - (PORT datac (549:549:549) (564:564:564)) - (PORT datad (849:849:849) (880:880:880)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal77\~1) - (DELAY - (ABSOLUTE - (PORT dataa (921:921:921) (1007:1007:1007)) - (PORT datab (1100:1100:1100) (1122:1122:1122)) - (PORT datac (599:599:599) (635:635:635)) - (PORT datad (1151:1151:1151) (1207:1207:1207)) + (PORT datad (560:560:560) (557:557:557)) (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) @@ -47190,421 +33974,43 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~12) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~51) (DELAY (ABSOLUTE - (PORT dataa (624:624:624) (639:639:639)) - (PORT datab (1532:1532:1532) (1512:1512:1512)) - (PORT datac (807:807:807) (801:801:801)) - (PORT datad (793:793:793) (792:792:792)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~14) - (DELAY - (ABSOLUTE - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (589:589:589) (602:602:602)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~41) - (DELAY - (ABSOLUTE - (PORT dataa (367:367:367) (398:398:398)) - (PORT datac (998:998:998) (981:981:981)) - (PORT datad (184:184:184) (208:208:208)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~42) - (DELAY - (ABSOLUTE - (PORT dataa (869:869:869) (887:887:887)) - (PORT datab (1013:1013:1013) (1053:1053:1053)) - (PORT datac (372:372:372) (402:402:402)) - (PORT datad (2321:2321:2321) (2343:2343:2343)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~43) - (DELAY - (ABSOLUTE - (PORT dataa (1847:1847:1847) (1918:1918:1918)) - (PORT datab (712:712:712) (752:752:752)) - (PORT datac (885:885:885) (901:901:901)) - (PORT datad (158:158:158) (178:178:178)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~44) - (DELAY - (ABSOLUTE - (PORT dataa (831:831:831) (838:838:838)) - (PORT datab (326:326:326) (348:348:348)) - (PORT datac (182:182:182) (216:216:216)) - (PORT datad (704:704:704) (684:684:684)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~50) - (DELAY - (ABSOLUTE - (PORT dataa (354:354:354) (361:361:361)) - (PORT datab (969:969:969) (965:965:965)) - (PORT datac (155:155:155) (186:186:186)) - (PORT datad (1210:1210:1210) (1195:1195:1195)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~51) - (DELAY - (ABSOLUTE - (PORT dataa (1039:1039:1039) (1043:1043:1043)) + (PORT dataa (551:551:551) (560:560:560)) (PORT datab (182:182:182) (215:215:215)) - (PORT datac (180:180:180) (214:214:214)) - (PORT datad (166:166:166) (193:193:193)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~6) - (DELAY - (ABSOLUTE - (PORT dataa (796:796:796) (780:780:780)) - (PORT datab (1460:1460:1460) (1549:1549:1549)) - (PORT datac (577:577:577) (576:576:576)) - (PORT datad (1557:1557:1557) (1605:1605:1605)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~7) - (DELAY - (ABSOLUTE - (PORT datab (794:794:794) (821:821:821)) - (PORT datac (823:823:823) (838:838:838)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1334:1334:1334) (1334:1334:1334)) - (PORT datab (803:803:803) (797:797:797)) - (PORT datac (811:811:811) (824:824:824)) - (PORT datad (577:577:577) (578:578:578)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1375:1375:1375) (1454:1454:1454)) - (PORT datab (1812:1812:1812) (1844:1844:1844)) - (PORT datac (1240:1240:1240) (1288:1288:1288)) - (PORT datad (1027:1027:1027) (1026:1026:1026)) - (IOPATH dataa combout (265:265:265) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~10) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (239:239:239)) - (PORT datab (1045:1045:1045) (1040:1040:1040)) - (PORT datac (478:478:478) (466:466:466)) - (PORT datad (591:591:591) (606:606:606)) + (PORT datad (320:320:320) (325:325:325)) (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~11) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (1127:1127:1127) (1133:1133:1133)) - (PORT datac (938:938:938) (948:948:948)) - (PORT datad (320:320:320) (321:321:321)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~17) - (DELAY - (ABSOLUTE - (PORT dataa (579:579:579) (601:601:601)) - (PORT datab (967:967:967) (963:963:963)) - (PORT datac (1852:1852:1852) (1836:1836:1836)) - (PORT datad (572:572:572) (581:581:581)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~31) - (DELAY - (ABSOLUTE - (PORT dataa (585:585:585) (588:588:588)) - (PORT datab (857:857:857) (877:877:877)) - (PORT datac (1676:1676:1676) (1729:1729:1729)) - (PORT datad (818:818:818) (827:827:827)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~28) - (DELAY - (ABSOLUTE - (PORT dataa (335:335:335) (357:357:357)) - (PORT datab (1132:1132:1132) (1137:1137:1137)) - (PORT datac (1298:1298:1298) (1315:1315:1315)) - (PORT datad (776:776:776) (761:761:761)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~30) - (DELAY - (ABSOLUTE - (PORT dataa (804:804:804) (811:811:811)) - (PORT datab (847:847:847) (854:854:854)) - (PORT datac (836:836:836) (830:830:830)) - (PORT datad (782:782:782) (783:783:783)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~32) - (DELAY - (ABSOLUTE - (PORT dataa (846:846:846) (882:882:882)) - (PORT datab (337:337:337) (351:351:351)) - (PORT datac (796:796:796) (810:810:810)) - (PORT datad (1018:1018:1018) (1013:1013:1013)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~33) - (DELAY - (ABSOLUTE - (PORT dataa (548:548:548) (548:548:548)) - (PORT datab (180:180:180) (212:212:212)) - (PORT datac (832:832:832) (844:844:844)) - (PORT datad (158:158:158) (178:178:178)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~25) - (DELAY - (ABSOLUTE - (PORT dataa (1041:1041:1041) (1098:1098:1098)) - (PORT datac (574:574:574) (578:578:578)) - (PORT datad (1463:1463:1463) (1509:1509:1509)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~26) - (DELAY - (ABSOLUTE - (PORT dataa (802:802:802) (826:826:826)) - (PORT datab (1442:1442:1442) (1485:1485:1485)) - (PORT datac (796:796:796) (808:808:808)) - (PORT datad (1033:1033:1033) (1055:1055:1055)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~24) - (DELAY - (ABSOLUTE - (PORT dataa (620:620:620) (642:642:642)) - (PORT datab (616:616:616) (622:622:622)) - (PORT datac (1876:1876:1876) (1825:1825:1825)) - (PORT datad (875:875:875) (914:914:914)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~27) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (220:220:220)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (591:591:591) (617:617:617)) - (PORT datad (618:618:618) (657:657:657)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~22) - (DELAY - (ABSOLUTE - (PORT dataa (856:856:856) (885:885:885)) - (PORT datab (835:835:835) (821:821:821)) - (PORT datac (818:818:818) (833:833:833)) - (PORT datad (573:573:573) (585:585:585)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1599:1599:1599) (1658:1658:1658)) - (PORT datab (1429:1429:1429) (1495:1495:1495)) - (PORT datac (1123:1123:1123) (1162:1162:1162)) - (PORT datad (1378:1378:1378) (1406:1406:1406)) - (IOPATH dataa combout (265:265:265) (273:273:273)) (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~53) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~52) (DELAY (ABSOLUTE - (PORT dataa (892:892:892) (922:922:922)) - (PORT datab (857:857:857) (886:886:886)) - (PORT datac (597:597:597) (611:611:611)) - (PORT datad (1199:1199:1199) (1205:1205:1205)) + (PORT dataa (793:793:793) (795:795:795)) + (PORT datab (319:319:319) (330:330:330)) + (PORT datac (565:565:565) (552:552:552)) + (PORT datad (184:184:184) (209:209:209)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_35) + (DELAY + (ABSOLUTE + (PORT dataa (802:802:802) (828:828:828)) + (PORT datab (323:323:323) (348:348:348)) + (PORT datac (1048:1048:1048) (1039:1039:1039)) + (PORT datad (584:584:584) (576:576:576)) (IOPATH dataa combout (300:300:300) (323:323:323)) (IOPATH datab combout (306:306:306) (324:324:324)) (IOPATH datac combout (218:218:218) (216:216:216)) @@ -47614,47 +34020,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~23) + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~15) (DELAY (ABSOLUTE - (PORT dataa (181:181:181) (216:216:216)) - (PORT datab (337:337:337) (357:357:357)) - (PORT datac (1413:1413:1413) (1418:1418:1418)) - (PORT datad (157:157:157) (177:177:177)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT dataa (1109:1109:1109) (1136:1136:1136)) + (PORT datab (1555:1555:1555) (1671:1671:1671)) + (PORT datac (1267:1267:1267) (1307:1307:1307)) + (PORT datad (754:754:754) (751:751:751)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~18) + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~16) (DELAY (ABSOLUTE - (PORT dataa (351:351:351) (367:367:367)) - (PORT datab (915:915:915) (914:914:914)) - (PORT datac (1406:1406:1406) (1456:1456:1456)) - (PORT datad (176:176:176) (198:198:198)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~19) - (DELAY - (ABSOLUTE - (PORT dataa (577:577:577) (576:576:576)) - (PORT datab (645:645:645) (668:668:668)) - (PORT datac (601:601:601) (626:626:626)) - (PORT datad (1213:1213:1213) (1266:1266:1266)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (275:275:275) (275:275:275)) + (PORT datab (181:181:181) (213:213:213)) + (PORT datac (163:163:163) (196:196:196)) + (PORT datad (179:179:179) (201:201:201)) + (IOPATH datab combout (273:273:273) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -47662,15 +34050,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~20) + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~17) (DELAY (ABSOLUTE - (PORT dataa (584:584:584) (615:615:615)) - (PORT datab (1087:1087:1087) (1081:1081:1081)) - (PORT datac (803:803:803) (828:828:828)) - (PORT datad (559:559:559) (573:573:573)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) + (PORT dataa (353:353:353) (359:359:359)) + (PORT datab (188:188:188) (225:225:225)) + (PORT datac (174:174:174) (206:206:206)) + (PORT datad (941:941:941) (910:910:910)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -47678,61 +34066,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~34) + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~18) (DELAY (ABSOLUTE - (PORT dataa (571:571:571) (580:580:580)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (287:287:287) (302:302:302)) - (PORT datad (159:159:159) (181:181:181)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~52) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (218:218:218)) - (PORT datab (181:181:181) (212:212:212)) - (PORT datac (294:294:294) (298:298:298)) - (PORT datad (896:896:896) (948:948:948)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) + (PORT dataa (1098:1098:1098) (1098:1098:1098)) + (PORT datab (183:183:183) (216:216:216)) + (PORT datac (596:596:596) (597:597:597)) + (PORT datad (544:544:544) (547:547:547)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_14) - (DELAY - (ABSOLUTE - (PORT dataa (1043:1043:1043) (1054:1054:1054)) - (PORT datac (221:221:221) (291:291:291)) - (PORT datad (1054:1054:1054) (1045:1045:1045)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_T3_ff) + (INSTANCE z80_\|alu_flags_\|flags_xf) (DELAY (ABSOLUTE - (PORT clk (1362:1362:1362) (1383:1383:1383)) + (PORT clk (1344:1344:1344) (1363:1363:1363)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1408:1408:1408) (1379:1379:1379)) - (PORT ena (1790:1790:1790) (1839:1839:1839)) + (PORT ena (1329:1329:1329) (1284:1284:1284)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) ) (TIMINGCHECK @@ -47742,87 +34098,28 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_1M1T3_3) + (INSTANCE z80_\|alu_control_\|db\[3\]\~33) (DELAY (ABSOLUTE - (PORT datac (910:910:910) (962:962:962)) - (PORT datad (1249:1249:1249) (1347:1347:1347)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|in_halt\~0) - (DELAY - (ABSOLUTE - (PORT dataa (329:329:329) (455:455:455)) - (PORT datac (1095:1095:1095) (1138:1138:1138)) - (PORT datad (248:248:248) (314:314:314)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|in_halt\~1) - (DELAY - (ABSOLUTE - (PORT dataa (596:596:596) (624:624:624)) - (PORT datab (1469:1469:1469) (1435:1435:1435)) - (PORT datad (583:583:583) (604:604:604)) - (IOPATH dataa combout (272:272:272) (269:269:269)) + (PORT datab (587:587:587) (575:575:575)) + (PORT datac (1015:1015:1015) (981:981:981)) + (PORT datad (199:199:199) (256:256:256)) (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|in_halt) - (DELAY - (ABSOLUTE - (PORT clk (1340:1340:1340) (1357:1357:1357)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1394:1394:1394) (1365:1365:1365)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~2) - (DELAY - (ABSOLUTE - (PORT dataa (916:916:916) (937:937:937)) - (PORT datab (1083:1083:1083) (1086:1086:1086)) - (PORT datac (627:627:627) (644:644:644)) - (PORT datad (584:584:584) (600:600:600)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~5) + (INSTANCE z80_\|sw1_\|db_down\[3\]\~2) (DELAY (ABSOLUTE - (PORT dataa (1034:1034:1034) (1114:1114:1114)) - (PORT datab (920:920:920) (954:954:954)) - (PORT datac (1064:1064:1064) (1070:1070:1070)) - (PORT datad (810:810:810) (834:834:834)) - (IOPATH dataa combout (318:318:318) (307:307:307)) + (PORT dataa (802:802:802) (819:819:819)) + (PORT datab (1278:1278:1278) (1238:1238:1238)) + (PORT datac (581:581:581) (620:620:620)) + (PORT datad (588:588:588) (611:611:611)) + (IOPATH dataa combout (329:329:329) (332:332:332)) (IOPATH datab combout (319:319:319) (307:307:307)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -47831,57 +34128,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~6) + (INSTANCE z80_\|alu_control_\|db\[3\]\~34) (DELAY (ABSOLUTE - (PORT dataa (374:374:374) (387:387:387)) - (PORT datab (634:634:634) (662:662:662)) - (PORT datac (824:824:824) (850:850:850)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~4) - (DELAY - (ABSOLUTE - (PORT datac (1009:1009:1009) (991:991:991)) - (PORT datad (598:598:598) (594:594:594)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (237:237:237)) - (PORT datab (879:879:879) (890:890:890)) - (PORT datac (592:592:592) (588:588:588)) - (PORT datad (158:158:158) (178:178:178)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[0\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (229:229:229) (278:278:278)) - (PORT datac (871:871:871) (897:897:897)) - (PORT datad (319:319:319) (319:319:319)) - (IOPATH dataa combout (272:272:272) (269:269:269)) + (PORT dataa (1188:1188:1188) (1208:1208:1208)) + (PORT datab (395:395:395) (403:403:403)) + (PORT datac (316:316:316) (323:323:323)) + (PORT datad (161:161:161) (182:182:182)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -47889,245 +34144,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]\~93) + (INSTANCE z80_\|alu_control_\|db\[3\]\~35) (DELAY (ABSOLUTE - (PORT dataa (208:208:208) (259:259:259)) - (PORT datab (715:715:715) (783:783:783)) - (PORT datac (1250:1250:1250) (1311:1311:1311)) - (PORT datad (524:524:524) (516:516:516)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]\~94) - (DELAY - (ABSOLUTE - (PORT dataa (578:578:578) (590:590:590)) - (PORT datab (676:676:676) (742:742:742)) - (PORT datad (662:662:662) (727:727:727)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1370:1370:1370)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1378:1378:1378)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]\~96) - (DELAY - (ABSOLUTE - (PORT dataa (686:686:686) (757:757:757)) - (PORT datab (1089:1089:1089) (1147:1147:1147)) - (PORT datac (667:667:667) (731:731:731)) - (PORT datad (673:673:673) (744:744:744)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]\~98) - (DELAY - (ABSOLUTE - (PORT dataa (187:187:187) (225:225:225)) - (PORT datab (191:191:191) (227:227:227)) - (PORT datad (169:169:169) (193:193:193)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1371:1371:1371)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1379:1379:1379)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~65) - (DELAY - (ABSOLUTE - (PORT dataa (1042:1042:1042) (1038:1038:1038)) - (PORT datab (1068:1068:1068) (1080:1080:1080)) - (PORT datac (195:195:195) (262:262:262)) - (PORT datad (332:332:332) (369:369:369)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]\~99) - (DELAY - (ABSOLUTE - (PORT dataa (705:705:705) (773:773:773)) - (PORT datab (669:669:669) (726:726:726)) - (PORT datac (809:809:809) (846:846:846)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]\~100) - (DELAY - (ABSOLUTE - (PORT dataa (318:318:318) (341:341:341)) - (PORT datab (184:184:184) (216:216:216)) - (PORT datad (677:677:677) (738:738:738)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1370:1370:1370)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1397:1397:1397) (1378:1378:1378)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~101) - (DELAY - (ABSOLUTE - (PORT dataa (683:683:683) (751:751:751)) - (PORT datab (911:911:911) (964:964:964)) - (PORT datad (861:861:861) (908:908:908)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~102) - (DELAY - (ABSOLUTE - (PORT dataa (686:686:686) (759:759:759)) - (PORT datab (668:668:668) (738:738:738)) - (PORT datac (1059:1059:1059) (1118:1118:1118)) - (PORT datad (838:838:838) (881:881:881)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~133) - (DELAY - (ABSOLUTE - (PORT dataa (620:620:620) (639:639:639)) - (PORT datab (184:184:184) (217:217:217)) - (PORT datac (668:668:668) (734:734:734)) - (PORT datad (668:668:668) (738:738:738)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (295:295:295) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~103) - (DELAY - (ABSOLUTE - (PORT dataa (184:184:184) (220:220:220)) - (PORT datad (303:303:303) (304:304:304)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1354:1354:1354) (1371:1371:1371)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1399:1399:1399) (1379:1379:1379)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~66) - (DELAY - (ABSOLUTE - (PORT dataa (566:566:566) (558:558:558)) - (PORT datab (394:394:394) (426:426:426)) - (PORT datac (525:525:525) (528:528:528)) - (PORT datad (576:576:576) (609:609:609)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (309:309:309) (328:328:328)) + (PORT dataa (185:185:185) (222:222:222)) + (PORT datab (354:354:354) (378:378:378)) + (PORT datac (782:782:782) (760:760:760)) + (PORT datad (200:200:200) (229:229:229)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -48135,76 +34160,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]\~104) + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]\~75) (DELAY (ABSOLUTE - (PORT dataa (662:662:662) (728:728:728)) - (PORT datab (672:672:672) (738:738:738)) - (PORT datac (660:660:660) (729:729:729)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]\~105) - (DELAY - (ABSOLUTE - (PORT dataa (185:185:185) (221:221:221)) - (PORT datab (335:335:335) (355:355:355)) - (PORT datad (661:661:661) (726:726:726)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1370:1370:1370)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1378:1378:1378)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~106) - (DELAY - (ABSOLUTE - (PORT dataa (1301:1301:1301) (1378:1378:1378)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (882:882:882) (920:920:920)) - (PORT datad (186:186:186) (212:212:212)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Selector5\~1) - (DELAY - (ABSOLUTE - (PORT dataa (662:662:662) (715:715:715)) - (PORT datab (613:613:613) (653:653:653)) - (PORT datac (599:599:599) (635:635:635)) - (PORT datad (402:402:402) (445:445:445)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) + (PORT dataa (972:972:972) (1025:1025:1025)) + (PORT datac (1090:1090:1090) (1107:1107:1107)) + (PORT datad (594:594:594) (624:624:624)) + (IOPATH dataa combout (287:287:287) (280:280:280)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -48215,56 +34177,88 @@ (INSTANCE ula_\|zx_keyboard_\|Selector5\~0) (DELAY (ABSOLUTE - (PORT dataa (210:210:210) (253:253:253)) - (PORT datab (374:374:374) (437:437:437)) - (PORT datac (577:577:577) (623:623:623)) - (PORT datad (374:374:374) (422:422:422)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (PORT dataa (623:623:623) (659:659:659)) + (PORT datab (759:759:759) (762:762:762)) + (PORT datac (414:414:414) (490:490:490)) + (PORT datad (399:399:399) (459:459:459)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~134) + (INSTANCE ula_\|zx_keyboard_\|Selector5\~1) (DELAY (ABSOLUTE - (PORT dataa (353:353:353) (360:360:360)) - (PORT datab (357:357:357) (355:355:355)) - (PORT datad (771:771:771) (785:785:785)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) + (PORT dataa (1073:1073:1073) (1146:1146:1146)) + (PORT datab (276:276:276) (371:371:371)) + (PORT datac (875:875:875) (931:931:931)) + (PORT datad (875:875:875) (923:923:923)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~132) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (219:219:219)) + (PORT datab (443:443:443) (522:522:522)) + (PORT datad (736:736:736) (762:762:762)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (273:273:273) (275:275:275)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~106) + (DELAY + (ABSOLUTE + (PORT dataa (425:425:425) (497:497:497)) + (PORT datab (1064:1064:1064) (1058:1058:1058)) + (PORT datac (414:414:414) (491:491:491)) + (PORT datad (180:180:180) (202:202:202)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~107) (DELAY (ABSOLUTE - (PORT dataa (683:683:683) (738:738:738)) - (PORT datab (563:563:563) (574:574:574)) - (PORT datac (574:574:574) (594:594:594)) - (PORT datad (490:490:490) (478:478:478)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT dataa (462:462:462) (514:514:514)) + (PORT datab (183:183:183) (217:217:217)) + (PORT datac (235:235:235) (312:312:312)) + (PORT datad (160:160:160) (182:182:182)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~135) + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~133) (DELAY (ABSOLUTE - (PORT dataa (680:680:680) (742:742:742)) - (PORT datab (248:248:248) (322:322:322)) - (PORT datad (1012:1012:1012) (1017:1017:1017)) + (PORT dataa (468:468:468) (517:517:517)) + (PORT datab (247:247:247) (321:321:321)) + (PORT datad (834:834:834) (899:899:899)) (IOPATH dataa combout (265:265:265) (273:273:273)) (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datac combout (312:312:312) (325:325:325)) @@ -48277,11 +34271,11 @@ (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~108) (DELAY (ABSOLUTE - (PORT dataa (185:185:185) (221:221:221)) - (PORT datab (344:344:344) (366:366:366)) - (PORT datad (161:161:161) (181:181:181)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) + (PORT dataa (184:184:184) (221:221:221)) + (PORT datab (183:183:183) (215:215:215)) + (PORT datad (179:179:179) (202:202:202)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -48292,9 +34286,9 @@ (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]) (DELAY (ABSOLUTE - (PORT clk (1351:1351:1351) (1369:1369:1369)) + (PORT clk (1343:1343:1343) (1360:1360:1360)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1396:1396:1396) (1377:1377:1377)) + (PORT clrn (1377:1377:1377) (1358:1358:1358)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -48305,13 +34299,285 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~67) + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]\~104) (DELAY (ABSOLUTE - (PORT dataa (221:221:221) (294:294:294)) - (PORT datab (1116:1116:1116) (1127:1127:1127)) - (PORT datac (580:580:580) (615:615:615)) - (PORT datad (725:725:725) (703:703:703)) + (PORT dataa (908:908:908) (940:940:940)) + (PORT datac (890:890:890) (948:948:948)) + (PORT datad (910:910:910) (963:963:963)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]\~105) + (DELAY + (ABSOLUTE + (PORT dataa (853:853:853) (848:848:848)) + (PORT datab (664:664:664) (715:715:715)) + (PORT datad (161:161:161) (182:182:182)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1362:1362:1362)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1381:1381:1381) (1360:1360:1360)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~55) + (DELAY + (ABSOLUTE + (PORT dataa (1040:1040:1040) (1016:1016:1016)) + (PORT datab (607:607:607) (648:648:648)) + (PORT datac (195:195:195) (262:262:262)) + (PORT datad (941:941:941) (935:935:935)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (776:776:776) (837:837:837)) + (PORT datab (934:934:934) (975:975:975)) + (PORT datac (591:591:591) (621:621:621)) + (PORT datad (836:836:836) (921:921:921)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~62) + (DELAY + (ABSOLUTE + (PORT datac (640:640:640) (689:689:689)) + (PORT datad (1424:1424:1424) (1459:1459:1459)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]\~102) + (DELAY + (ABSOLUTE + (PORT dataa (868:868:868) (915:915:915)) + (PORT datab (201:201:201) (235:235:235)) + (PORT datac (874:874:874) (916:916:916)) + (PORT datad (191:191:191) (224:224:224)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]\~103) + (DELAY + (ABSOLUTE + (PORT datab (662:662:662) (716:716:716)) + (PORT datad (772:772:772) (761:761:761)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1362:1362:1362)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1381:1381:1381) (1360:1360:1360)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~96) + (DELAY + (ABSOLUTE + (PORT dataa (602:602:602) (628:628:628)) + (PORT datab (1400:1400:1400) (1426:1426:1426)) + (PORT datac (885:885:885) (917:917:917)) + (PORT datad (1067:1067:1067) (1086:1086:1086)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~94) + (DELAY + (ABSOLUTE + (PORT dataa (927:927:927) (939:939:939)) + (PORT datab (883:883:883) (909:909:909)) + (PORT datad (1065:1065:1065) (1086:1086:1086)) + (IOPATH dataa combout (267:267:267) (273:273:273)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]\~95) + (DELAY + (ABSOLUTE + (PORT dataa (1468:1468:1468) (1497:1497:1497)) + (PORT datab (631:631:631) (675:675:675)) + (PORT datac (646:646:646) (692:692:692)) + (PORT datad (896:896:896) (941:941:941)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]\~97) + (DELAY + (ABSOLUTE + (PORT dataa (382:382:382) (384:384:384)) + (PORT datab (373:373:373) (371:371:371)) + (PORT datad (321:321:321) (335:335:335)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1357:1357:1357)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1381:1381:1381) (1360:1360:1360)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~45) + (DELAY + (ABSOLUTE + (PORT dataa (1106:1106:1106) (1143:1143:1143)) + (PORT datac (889:889:889) (943:943:943)) + (PORT datad (2043:2043:2043) (2065:2065:2065)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]\~92) + (DELAY + (ABSOLUTE + (PORT dataa (211:211:211) (253:253:253)) + (PORT datab (585:585:585) (581:581:581)) + (PORT datac (633:633:633) (674:674:674)) + (PORT datad (907:907:907) (959:959:959)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]\~93) + (DELAY + (ABSOLUTE + (PORT dataa (911:911:911) (943:943:943)) + (PORT datab (663:663:663) (716:716:716)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1362:1362:1362)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1381:1381:1381) (1360:1360:1360)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~53) + (DELAY + (ABSOLUTE + (PORT dataa (628:628:628) (672:672:672)) + (PORT datab (588:588:588) (594:594:594)) + (PORT datac (194:194:194) (260:260:260)) + (PORT datad (1002:1002:1002) (978:978:978)) (IOPATH dataa combout (309:309:309) (326:326:326)) (IOPATH datab combout (306:306:306) (324:324:324)) (IOPATH datac combout (218:218:218) (215:215:215)) @@ -48321,13 +34587,27 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]\~112) + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~99) (DELAY (ABSOLUTE - (PORT dataa (791:791:791) (792:792:792)) - (PORT datab (200:200:200) (243:243:243)) - (PORT datac (592:592:592) (617:617:617)) - (PORT datad (302:302:302) (303:303:303)) + (PORT datab (868:868:868) (954:954:954)) + (PORT datac (873:873:873) (911:911:911)) + (PORT datad (888:888:888) (939:939:939)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~100) + (DELAY + (ABSOLUTE + (PORT dataa (186:186:186) (224:224:224)) + (PORT datab (217:217:217) (258:258:258)) + (PORT datac (877:877:877) (917:917:917)) + (PORT datad (609:609:609) (644:644:644)) (IOPATH dataa combout (300:300:300) (323:323:323)) (IOPATH datab combout (306:306:306) (324:324:324)) (IOPATH datac combout (218:218:218) (216:216:216)) @@ -48337,15 +34617,88 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]\~113) + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~98) (DELAY (ABSOLUTE - (PORT dataa (664:664:664) (716:716:716)) - (PORT datab (184:184:184) (218:218:218)) - (PORT datac (531:531:531) (535:535:535)) - (PORT datad (420:420:420) (476:476:476)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (308:308:308) (281:281:281)) + (PORT dataa (924:924:924) (934:934:934)) + (PORT datac (885:885:885) (923:923:923)) + (PORT datad (848:848:848) (874:874:874)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~101) + (DELAY + (ABSOLUTE + (PORT dataa (603:603:603) (629:629:629)) + (PORT datab (586:586:586) (585:585:585)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1357:1357:1357)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1381:1381:1381) (1360:1360:1360)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\~3) + (DELAY + (ABSOLUTE + (PORT dataa (2513:2513:2513) (2532:2532:2532)) + (PORT datab (1335:1335:1335) (1357:1357:1357)) + (PORT datad (592:592:592) (632:632:632)) + (IOPATH dataa combout (267:267:267) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~54) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (295:295:295)) + (PORT datab (183:183:183) (217:217:217)) + (PORT datac (976:976:976) (946:946:946)) + (PORT datad (301:301:301) (302:302:302)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~109) + (DELAY + (ABSOLUTE + (PORT datab (879:879:879) (902:902:902)) + (PORT datac (911:911:911) (941:941:941)) + (PORT datad (1048:1048:1048) (1040:1040:1040)) + (IOPATH datab combout (308:308:308) (300:300:300)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -48353,12 +34706,56 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]\~114) + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~60) (DELAY (ABSOLUTE - (PORT datab (530:530:530) (510:510:510)) - (PORT datad (810:810:810) (810:810:810)) + (PORT datab (928:928:928) (982:982:982)) + (PORT datac (910:910:910) (941:941:941)) (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]\~110) + (DELAY + (ABSOLUTE + (PORT dataa (192:192:192) (234:234:234)) + (PORT datab (1141:1141:1141) (1182:1182:1182)) + (PORT datac (769:769:769) (777:777:777)) + (PORT datad (186:186:186) (211:211:211)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]\~111) + (DELAY + (ABSOLUTE + (PORT dataa (815:815:815) (810:810:810)) + (PORT datab (965:965:965) (1002:1002:1002)) + (PORT datac (294:294:294) (298:298:298)) + (PORT datad (678:678:678) (717:717:717)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]\~112) + (DELAY + (ABSOLUTE + (PORT dataa (204:204:204) (242:242:242)) + (PORT datad (159:159:159) (181:181:181)) + (IOPATH dataa combout (287:287:287) (289:289:289)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -48369,9 +34766,9 @@ (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]) (DELAY (ABSOLUTE - (PORT clk (1344:1344:1344) (1362:1362:1362)) + (PORT clk (1338:1338:1338) (1356:1356:1356)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1389:1389:1389) (1370:1370:1370)) + (PORT clrn (1380:1380:1380) (1360:1360:1360)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -48382,46 +34779,60 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~109) + (INSTANCE ula_\|zx_keyboard_\|Selector13\~0) (DELAY (ABSOLUTE - (PORT dataa (669:669:669) (719:719:719)) - (PORT datab (606:606:606) (639:639:639)) - (PORT datac (592:592:592) (618:618:618)) - (PORT datad (743:743:743) (755:755:755)) + (PORT dataa (1398:1398:1398) (1423:1423:1423)) + (PORT datab (849:849:849) (873:873:873)) + (PORT datad (847:847:847) (873:873:873)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~113) + (DELAY + (ABSOLUTE + (PORT dataa (939:939:939) (975:975:975)) + (PORT datab (1141:1141:1141) (1181:1181:1181)) + (PORT datac (900:900:900) (957:957:957)) + (PORT datad (675:675:675) (716:716:716)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~114) + (DELAY + (ABSOLUTE + (PORT dataa (185:185:185) (222:222:222)) + (PORT datab (714:714:714) (751:751:751)) + (PORT datac (321:321:321) (329:329:329)) + (PORT datad (875:875:875) (916:916:916)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~135) + (DELAY + (ABSOLUTE + (PORT dataa (813:813:813) (809:809:809)) + (PORT datab (963:963:963) (1000:1000:1000)) + (PORT datad (160:160:160) (181:181:181)) (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~110) - (DELAY - (ABSOLUTE - (PORT dataa (666:666:666) (719:719:719)) - (PORT datab (202:202:202) (246:246:246)) - (PORT datac (158:158:158) (189:189:189)) - (PORT datad (587:587:587) (622:622:622)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~137) - (DELAY - (ABSOLUTE - (PORT dataa (679:679:679) (735:735:735)) - (PORT datab (311:311:311) (328:328:328)) - (PORT datad (320:320:320) (332:332:332)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -48429,14 +34840,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~138) + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~136) (DELAY (ABSOLUTE - (PORT dataa (955:955:955) (1042:1042:1042)) - (PORT datab (617:617:617) (625:625:625)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (336:336:336) (337:337:337)) + (PORT dataa (330:330:330) (342:342:342)) + (PORT datab (183:183:183) (214:214:214)) + (PORT datad (861:861:861) (871:871:871)) + (IOPATH dataa combout (267:267:267) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -48447,9 +34858,9 @@ (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]) (DELAY (ABSOLUTE - (PORT clk (1351:1351:1351) (1369:1369:1369)) + (PORT clk (1338:1338:1338) (1356:1356:1356)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1396:1396:1396) (1377:1377:1377)) + (PORT clrn (1380:1380:1380) (1360:1360:1360)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -48460,13 +34871,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|key_row\~2) + (INSTANCE D\[3\]\~56) (DELAY (ABSOLUTE - (PORT datab (1289:1289:1289) (1294:1294:1294)) - (PORT datac (1505:1505:1505) (1522:1522:1522)) - (PORT datad (1100:1100:1100) (1138:1138:1138)) - (IOPATH datab combout (275:275:275) (275:275:275)) + (PORT dataa (1496:1496:1496) (1549:1549:1549)) + (PORT datab (220:220:220) (289:289:289)) + (PORT datac (196:196:196) (262:262:262)) + (PORT datad (575:575:575) (586:586:586)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -48474,43 +34887,27 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~68) + (INSTANCE D\[3\]\~57) (DELAY (ABSOLUTE - (PORT dataa (209:209:209) (250:250:250)) - (PORT datab (1109:1109:1109) (1116:1116:1116)) - (PORT datac (1094:1094:1094) (1124:1124:1124)) - (PORT datad (159:159:159) (179:179:179)) + (PORT dataa (184:184:184) (221:221:221)) + (PORT datab (181:181:181) (213:213:213)) + (PORT datac (794:794:794) (783:783:783)) + (PORT datad (541:541:541) (540:540:540)) (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~69) - (DELAY - (ABSOLUTE - (PORT dataa (1044:1044:1044) (1051:1051:1051)) - (PORT datab (3054:3054:3054) (3103:3103:3103)) - (PORT datac (1064:1064:1064) (1065:1065:1065)) - (PORT datad (522:522:522) (508:508:508)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.datain_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (980:980:980) (986:986:986)) - (PORT clk (1635:1635:1635) (1662:1662:1662)) + (PORT d[0] (951:951:951) (914:914:914)) + (PORT clk (1646:1646:1646) (1673:1673:1673)) ) ) (TIMINGCHECK @@ -48519,23 +34916,23 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.addr_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (3707:3707:3707) (3804:3804:3804)) - (PORT d[1] (1578:1578:1578) (1672:1672:1672)) - (PORT d[2] (1570:1570:1570) (1580:1580:1580)) - (PORT d[3] (1744:1744:1744) (1781:1781:1781)) - (PORT d[4] (2000:2000:2000) (2056:2056:2056)) - (PORT d[5] (1252:1252:1252) (1314:1314:1314)) - (PORT d[6] (1393:1393:1393) (1427:1427:1427)) - (PORT d[7] (3116:3116:3116) (3137:3137:3137)) - (PORT d[8] (3368:3368:3368) (3477:3477:3477)) - (PORT d[9] (1365:1365:1365) (1402:1402:1402)) - (PORT d[10] (2948:2948:2948) (3034:3034:3034)) - (PORT d[11] (1950:1950:1950) (1990:1990:1990)) - (PORT d[12] (1611:1611:1611) (1636:1636:1636)) - (PORT clk (1632:1632:1632) (1660:1660:1660)) + (PORT d[0] (2969:2969:2969) (3082:3082:3082)) + (PORT d[1] (1468:1468:1468) (1523:1523:1523)) + (PORT d[2] (921:921:921) (935:935:935)) + (PORT d[3] (3061:3061:3061) (3204:3204:3204)) + (PORT d[4] (938:938:938) (952:952:952)) + (PORT d[5] (1375:1375:1375) (1359:1359:1359)) + (PORT d[6] (927:927:927) (938:938:938)) + (PORT d[7] (2635:2635:2635) (2760:2760:2760)) + (PORT d[8] (3329:3329:3329) (3382:3382:3382)) + (PORT d[9] (1078:1078:1078) (1062:1062:1062)) + (PORT d[10] (3982:3982:3982) (4201:4201:4201)) + (PORT d[11] (3600:3600:3600) (3713:3713:3713)) + (PORT d[12] (1095:1095:1095) (1090:1090:1090)) + (PORT clk (1643:1643:1643) (1671:1671:1671)) ) ) (TIMINGCHECK @@ -48544,11 +34941,11 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.we_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2373:2373:2373) (2344:2344:2344)) - (PORT clk (1632:1632:1632) (1660:1660:1660)) + (PORT d[0] (1369:1369:1369) (1304:1304:1304)) + (PORT clk (1643:1643:1643) (1671:1671:1671)) ) ) (TIMINGCHECK @@ -48557,60 +34954,60 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.active_core_port_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1635:1635:1635) (1662:1662:1662)) - (PORT d[0] (2716:2716:2716) (2716:2716:2716)) + (PORT clk (1646:1646:1646) (1673:1673:1673)) + (PORT d[0] (2181:2181:2181) (2138:2138:2138)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.wpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1636:1636:1636) (1663:1663:1663)) + (PORT clk (1647:1647:1647) (1674:1674:1674)) (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1636:1636:1636) (1663:1663:1663)) + (PORT clk (1647:1647:1647) (1674:1674:1674)) (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.ftpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1636:1636:1636) (1663:1663:1663)) + (PORT clk (1647:1647:1647) (1674:1674:1674)) (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rwpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1636:1636:1636) (1663:1663:1663)) + (PORT clk (1647:1647:1647) (1674:1674:1674)) (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.dataout_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1599:1599:1599) (1626:1626:1626)) + (PORT clk (1610:1610:1610) (1637:1637:1637)) (IOPATH (posedge clk) q (268:268:268) (268:268:268)) ) ) @@ -48621,38 +35018,38 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.active_core_port_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (870:870:870) (873:873:873)) + (PORT clk (881:881:881) (884:884:884)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (871:871:871) (874:874:874)) + (PORT clk (882:882:882) (885:885:885)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.ftpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (871:871:871) (874:874:874)) + (PORT clk (882:882:882) (885:885:885)) (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rwpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (871:871:871) (874:874:874)) + (PORT clk (882:882:882) (885:885:885)) (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) @@ -48662,7 +35059,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (630:630:630) (628:628:628)) + (PORT d[0] (630:630:630) (642:642:642)) (PORT clk (1638:1638:1638) (1666:1666:1666)) ) ) @@ -48675,19 +35072,19 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2822:2822:2822) (2886:2886:2886)) - (PORT d[1] (1278:1278:1278) (1342:1342:1342)) - (PORT d[2] (1874:1874:1874) (1890:1890:1890)) - (PORT d[3] (2022:2022:2022) (2058:2058:2058)) - (PORT d[4] (1456:1456:1456) (1471:1471:1471)) - (PORT d[5] (1295:1295:1295) (1333:1333:1333)) - (PORT d[6] (1113:1113:1113) (1134:1134:1134)) - (PORT d[7] (3108:3108:3108) (3147:3147:3147)) - (PORT d[8] (2300:2300:2300) (2397:2397:2397)) - (PORT d[9] (3216:3216:3216) (3294:3294:3294)) - (PORT d[10] (2671:2671:2671) (2745:2745:2745)) - (PORT d[11] (1652:1652:1652) (1662:1662:1662)) - (PORT d[12] (1326:1326:1326) (1338:1338:1338)) + (PORT d[0] (1387:1387:1387) (1402:1402:1402)) + (PORT d[1] (4550:4550:4550) (4580:4580:4580)) + (PORT d[2] (2716:2716:2716) (2830:2830:2830)) + (PORT d[3] (1738:1738:1738) (1769:1769:1769)) + (PORT d[4] (1354:1354:1354) (1369:1369:1369)) + (PORT d[5] (1588:1588:1588) (1579:1579:1579)) + (PORT d[6] (1478:1478:1478) (1494:1494:1494)) + (PORT d[7] (2001:2001:2001) (2056:2056:2056)) + (PORT d[8] (2647:2647:2647) (2757:2757:2757)) + (PORT d[9] (2590:2590:2590) (2702:2702:2702)) + (PORT d[10] (2330:2330:2330) (2451:2451:2451)) + (PORT d[11] (2154:2154:2154) (2194:2194:2194)) + (PORT d[12] (2794:2794:2794) (2778:2778:2778)) (PORT clk (1635:1635:1635) (1664:1664:1664)) ) ) @@ -48700,7 +35097,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1816:1816:1816) (1750:1750:1750)) + (PORT d[0] (2119:2119:2119) (2089:2089:2089)) (PORT clk (1635:1635:1635) (1664:1664:1664)) ) ) @@ -48714,7 +35111,7 @@ (DELAY (ABSOLUTE (PORT clk (1638:1638:1638) (1666:1666:1666)) - (PORT d[0] (2737:2737:2737) (2658:2658:2658)) + (PORT d[0] (1786:1786:1786) (1740:1740:1740)) ) ) ) @@ -48810,13 +35207,181 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (872:872:872) (871:871:871)) + (PORT clk (1637:1637:1637) (1665:1665:1665)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1396:1396:1396) (1380:1380:1380)) + (PORT d[1] (1756:1756:1756) (1791:1791:1791)) + (PORT d[2] (1763:1763:1763) (1820:1820:1820)) + (PORT d[3] (1709:1709:1709) (1727:1727:1727)) + (PORT d[4] (1612:1612:1612) (1627:1627:1627)) + (PORT d[5] (1301:1301:1301) (1300:1300:1300)) + (PORT d[6] (1603:1603:1603) (1595:1595:1595)) + (PORT d[7] (1696:1696:1696) (1752:1752:1752)) + (PORT d[8] (2618:2618:2618) (2723:2723:2723)) + (PORT d[9] (2874:2874:2874) (2996:2996:2996)) + (PORT d[10] (1636:1636:1636) (1681:1681:1681)) + (PORT d[11] (2111:2111:2111) (2151:2151:2151)) + (PORT d[12] (2525:2525:2525) (2521:2521:2521)) + (PORT clk (1634:1634:1634) (1663:1663:1663)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1620:1620:1620) (1568:1568:1568)) + (PORT clk (1634:1634:1634) (1663:1663:1663)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1637:1637:1637) (1665:1665:1665)) + (PORT d[0] (1602:1602:1602) (1555:1555:1555)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1601:1601:1601) (1629:1629:1629)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (876:876:876)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (877:877:877)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (877:877:877)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (877:877:877)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[3\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (697:697:697) (750:750:750)) + (PORT datab (595:595:595) (582:582:582)) + (PORT datad (831:831:831) (799:799:799)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_ram_register") (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (922:922:922) (927:927:927)) - (PORT clk (1638:1638:1638) (1665:1665:1665)) + (PORT d[0] (896:896:896) (907:907:907)) + (PORT clk (1638:1638:1638) (1666:1666:1666)) ) ) (TIMINGCHECK @@ -48828,20 +35393,20 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2795:2795:2795) (2848:2848:2848)) - (PORT d[1] (1266:1266:1266) (1343:1343:1343)) - (PORT d[2] (1514:1514:1514) (1548:1548:1548)) - (PORT d[3] (1400:1400:1400) (1414:1414:1414)) - (PORT d[4] (1779:1779:1779) (1814:1814:1814)) - (PORT d[5] (1512:1512:1512) (1565:1565:1565)) - (PORT d[6] (1276:1276:1276) (1252:1252:1252)) - (PORT d[7] (1343:1343:1343) (1370:1370:1370)) - (PORT d[8] (1995:1995:1995) (2080:2080:2080)) - (PORT d[9] (3525:3525:3525) (3617:3617:3617)) - (PORT d[10] (2413:2413:2413) (2469:2469:2469)) - (PORT d[11] (1699:1699:1699) (1726:1726:1726)) - (PORT d[12] (1884:1884:1884) (1885:1885:1885)) - (PORT clk (1635:1635:1635) (1663:1663:1663)) + (PORT d[0] (1652:1652:1652) (1667:1667:1667)) + (PORT d[1] (4238:4238:4238) (4259:4259:4259)) + (PORT d[2] (1573:1573:1573) (1642:1642:1642)) + (PORT d[3] (2686:2686:2686) (2776:2776:2776)) + (PORT d[4] (3855:3855:3855) (3927:3927:3927)) + (PORT d[5] (1613:1613:1613) (1615:1615:1615)) + (PORT d[6] (3351:3351:3351) (3403:3403:3403)) + (PORT d[7] (2006:2006:2006) (2077:2077:2077)) + (PORT d[8] (2584:2584:2584) (2664:2664:2664)) + (PORT d[9] (2567:2567:2567) (2673:2673:2673)) + (PORT d[10] (2326:2326:2326) (2444:2444:2444)) + (PORT d[11] (1835:1835:1835) (1865:1865:1865)) + (PORT d[12] (3368:3368:3368) (3408:3408:3408)) + (PORT clk (1635:1635:1635) (1664:1664:1664)) ) ) (TIMINGCHECK @@ -48853,8 +35418,8 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1540:1540:1540) (1489:1489:1489)) - (PORT clk (1635:1635:1635) (1663:1663:1663)) + (PORT d[0] (1383:1383:1383) (1343:1343:1343)) + (PORT clk (1635:1635:1635) (1664:1664:1664)) ) ) (TIMINGCHECK @@ -48866,8 +35431,8 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1638:1638:1638) (1665:1665:1665)) - (PORT d[0] (2009:2009:2009) (1976:1976:1976)) + (PORT clk (1638:1638:1638) (1666:1666:1666)) + (PORT d[0] (2376:2376:2376) (2375:2375:2375)) ) ) ) @@ -48876,7 +35441,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1639:1639:1639) (1666:1666:1666)) + (PORT clk (1639:1639:1639) (1667:1667:1667)) (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) ) ) @@ -48886,7 +35451,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1639:1639:1639) (1666:1666:1666)) + (PORT clk (1639:1639:1639) (1667:1667:1667)) (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) ) ) @@ -48896,7 +35461,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1639:1639:1639) (1666:1666:1666)) + (PORT clk (1639:1639:1639) (1667:1667:1667)) (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) ) ) @@ -48906,7 +35471,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1639:1639:1639) (1666:1666:1666)) + (PORT clk (1639:1639:1639) (1667:1667:1667)) (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) ) ) @@ -48916,7 +35481,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1602:1602:1602) (1629:1629:1629)) + (PORT clk (1602:1602:1602) (1630:1630:1630)) (IOPATH (posedge clk) q (268:268:268) (268:268:268)) ) ) @@ -48930,7 +35495,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (873:873:873) (876:876:876)) + (PORT clk (873:873:873) (877:877:877)) ) ) ) @@ -48939,7 +35504,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (874:874:874) (877:877:877)) + (PORT clk (874:874:874) (878:878:878)) ) ) ) @@ -48948,7 +35513,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (874:874:874) (877:877:877)) + (PORT clk (874:874:874) (878:878:878)) (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) @@ -48958,505 +35523,22 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (874:874:874) (877:877:877)) + (PORT clk (874:874:874) (878:878:878)) (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~73) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[3\]\~7) (DELAY (ABSOLUTE - (PORT dataa (587:587:587) (583:583:583)) - (PORT datab (1241:1241:1241) (1253:1253:1253)) - (PORT datac (822:822:822) (826:826:826)) - (PORT datad (1069:1069:1069) (1093:1093:1093)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1194:1194:1194) (1213:1213:1213)) - (PORT clk (1635:1635:1635) (1662:1662:1662)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3401:3401:3401) (3484:3484:3484)) - (PORT d[1] (1574:1574:1574) (1681:1681:1681)) - (PORT d[2] (2794:2794:2794) (2844:2844:2844)) - (PORT d[3] (2020:2020:2020) (2045:2045:2045)) - (PORT d[4] (2098:2098:2098) (2151:2151:2151)) - (PORT d[5] (2235:2235:2235) (2358:2358:2358)) - (PORT d[6] (1916:1916:1916) (1960:1960:1960)) - (PORT d[7] (2559:2559:2559) (2570:2570:2570)) - (PORT d[8] (2818:2818:2818) (2924:2924:2924)) - (PORT d[9] (2371:2371:2371) (2420:2420:2420)) - (PORT d[10] (3473:3473:3473) (3560:3560:3560)) - (PORT d[11] (1678:1678:1678) (1707:1707:1707)) - (PORT d[12] (1889:1889:1889) (1941:1941:1941)) - (PORT clk (1632:1632:1632) (1660:1660:1660)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2582:2582:2582) (2504:2504:2504)) - (PORT clk (1632:1632:1632) (1660:1660:1660)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1635:1635:1635) (1662:1662:1662)) - (PORT d[0] (2502:2502:2502) (2419:2419:2419)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1636:1636:1636) (1663:1663:1663)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1636:1636:1636) (1663:1663:1663)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1636:1636:1636) (1663:1663:1663)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1636:1636:1636) (1663:1663:1663)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1599:1599:1599) (1626:1626:1626)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (870:870:870) (873:873:873)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (871:871:871) (874:874:874)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (871:871:871) (874:874:874)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (871:871:871) (874:874:874)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~74) - (DELAY - (ABSOLUTE - (PORT dataa (1118:1118:1118) (1126:1126:1126)) - (PORT datab (871:871:871) (890:890:890)) - (PORT datac (156:156:156) (187:187:187)) - (PORT datad (1322:1322:1322) (1324:1324:1324)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3379:3379:3379) (3440:3440:3440)) - (PORT d[1] (2405:2405:2405) (2528:2528:2528)) - (PORT d[2] (1530:1530:1530) (1562:1562:1562)) - (PORT d[3] (1999:1999:1999) (2040:2040:2040)) - (PORT d[4] (1736:1736:1736) (1773:1773:1773)) - (PORT d[5] (1249:1249:1249) (1314:1314:1314)) - (PORT d[6] (1072:1072:1072) (1078:1078:1078)) - (PORT d[7] (1356:1356:1356) (1369:1369:1369)) - (PORT d[8] (2015:2015:2015) (2100:2100:2100)) - (PORT d[9] (3546:3546:3546) (3640:3640:3640)) - (PORT d[10] (2382:2382:2382) (2434:2434:2434)) - (PORT d[11] (1950:1950:1950) (1977:1977:1977)) - (PORT d[12] (1872:1872:1872) (1878:1878:1878)) - (PORT clk (1635:1635:1635) (1662:1662:1662)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1635:1635:1635) (1662:1662:1662)) - (PORT d[0] (3104:3104:3104) (3115:3115:3115)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1636:1636:1636) (1663:1663:1663)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1602:1602:1602) (1628:1628:1628)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (873:873:873) (875:875:875)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (876:876:876)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (876:876:876)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (874:874:874) (876:876:876)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1369:1369:1369) (1374:1374:1374)) - (PORT clk (1631:1631:1631) (1660:1660:1660)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3108:3108:3108) (3171:3171:3171)) - (PORT d[1] (2132:2132:2132) (2244:2244:2244)) - (PORT d[2] (2028:2028:2028) (2054:2054:2054)) - (PORT d[3] (1703:1703:1703) (1741:1741:1741)) - (PORT d[4] (2005:2005:2005) (2050:2050:2050)) - (PORT d[5] (1526:1526:1526) (1603:1603:1603)) - (PORT d[6] (1381:1381:1381) (1387:1387:1387)) - (PORT d[7] (1387:1387:1387) (1412:1412:1412)) - (PORT d[8] (2698:2698:2698) (2780:2780:2780)) - (PORT d[9] (2115:2115:2115) (2160:2160:2160)) - (PORT d[10] (2120:2120:2120) (2141:2141:2141)) - (PORT d[11] (2296:2296:2296) (2349:2349:2349)) - (PORT d[12] (1833:1833:1833) (1854:1854:1854)) - (PORT clk (1628:1628:1628) (1658:1658:1658)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2623:2623:2623) (2592:2592:2592)) - (PORT clk (1628:1628:1628) (1658:1658:1658)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1631:1631:1631) (1660:1660:1660)) - (PORT d[0] (3652:3652:3652) (3652:3652:3652)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1632:1632:1632) (1661:1661:1661)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1632:1632:1632) (1661:1661:1661)) - (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1632:1632:1632) (1661:1661:1661)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1632:1632:1632) (1661:1661:1661)) - (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1590:1590:1590) (1590:1590:1590)) - (IOPATH (posedge clk) q (268:268:268) (268:268:268)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (42:42:42)) - (HOLD d (posedge clk) (142:142:142)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2131:2131:2131) (2069:2069:2069)) - (PORT clk (1598:1598:1598) (1597:1597:1597)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4055:4055:4055) (3966:3966:3966)) - (PORT d[1] (3960:3960:3960) (3871:3871:3871)) - (PORT d[2] (3972:3972:3972) (3879:3879:3879)) - (PORT d[3] (4222:4222:4222) (4150:4150:4150)) - (PORT d[4] (3999:3999:3999) (3860:3860:3860)) - (PORT d[5] (4046:4046:4046) (3954:3954:3954)) - (PORT d[6] (4173:4173:4173) (4155:4155:4155)) - (PORT d[7] (4052:4052:4052) (3984:3984:3984)) - (PORT d[8] (4288:4288:4288) (4117:4117:4117)) - (PORT d[9] (4142:4142:4142) (4230:4230:4230)) - (PORT d[10] (4065:4065:4065) (3987:3987:3987)) - (PORT d[11] (4060:4060:4060) (3947:3947:3947)) - (PORT d[12] (4312:4312:4312) (4202:4202:4202)) - (PORT clk (1595:1595:1595) (1594:1594:1594)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (169:169:169)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1598:1598:1598) (1597:1597:1597)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1599:1599:1599) (1598:1598:1598)) - (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1599:1599:1599) (1598:1598:1598)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1599:1599:1599) (1598:1598:1598)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1599:1599:1599) (1598:1598:1598)) - (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~70) - (DELAY - (ABSOLUTE - (PORT dataa (827:827:827) (847:847:847)) - (PORT datab (1559:1559:1559) (1578:1578:1578)) - (PORT datac (849:849:849) (860:860:860)) - (PORT datad (1100:1100:1100) (1108:1108:1108)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (325:325:325) (332:332:332)) + (PORT dataa (1434:1434:1434) (1498:1498:1498)) + (PORT datab (997:997:997) (960:960:960)) + (PORT datac (156:156:156) (186:186:186)) + (PORT datad (854:854:854) (840:840:840)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (295:295:295) (300:300:300)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -49467,20 +35549,20 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (3343:3343:3343) (3403:3403:3403)) - (PORT d[1] (2414:2414:2414) (2527:2527:2527)) - (PORT d[2] (1429:1429:1429) (1441:1441:1441)) - (PORT d[3] (1966:1966:1966) (2008:2008:2008)) - (PORT d[4] (2008:2008:2008) (2048:2048:2048)) - (PORT d[5] (1520:1520:1520) (1595:1595:1595)) - (PORT d[6] (1309:1309:1309) (1307:1307:1307)) - (PORT d[7] (1368:1368:1368) (1386:1386:1386)) - (PORT d[8] (1998:1998:1998) (2066:2066:2066)) - (PORT d[9] (2127:2127:2127) (2184:2184:2184)) - (PORT d[10] (2112:2112:2112) (2157:2157:2157)) - (PORT d[11] (1966:1966:1966) (2005:2005:2005)) - (PORT d[12] (2122:2122:2122) (2139:2139:2139)) - (PORT clk (1633:1633:1633) (1661:1661:1661)) + (PORT d[0] (3142:3142:3142) (3282:3282:3282)) + (PORT d[1] (3967:3967:3967) (3978:3978:3978)) + (PORT d[2] (2170:2170:2170) (2260:2260:2260)) + (PORT d[3] (2382:2382:2382) (2461:2461:2461)) + (PORT d[4] (3800:3800:3800) (3853:3853:3853)) + (PORT d[5] (1931:1931:1931) (1960:1960:1960)) + (PORT d[6] (3028:3028:3028) (3062:3062:3062)) + (PORT d[7] (3047:3047:3047) (3122:3122:3122)) + (PORT d[8] (2303:2303:2303) (2363:2363:2363)) + (PORT d[9] (2569:2569:2569) (2658:2658:2658)) + (PORT d[10] (2061:2061:2061) (2189:2189:2189)) + (PORT d[11] (2186:2186:2186) (2211:2211:2211)) + (PORT d[12] (3099:3099:3099) (3129:3129:3129)) + (PORT clk (1634:1634:1634) (1662:1662:1662)) ) ) (TIMINGCHECK @@ -49492,8 +35574,8 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1633:1633:1633) (1661:1661:1661)) - (PORT d[0] (3092:3092:3092) (3079:3079:3079)) + (PORT clk (1634:1634:1634) (1662:1662:1662)) + (PORT d[0] (4180:4180:4180) (4202:4202:4202)) ) ) ) @@ -49502,7 +35584,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1634:1634:1634) (1662:1662:1662)) + (PORT clk (1635:1635:1635) (1663:1663:1663)) (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) ) ) @@ -49512,7 +35594,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1600:1600:1600) (1627:1627:1627)) + (PORT clk (1601:1601:1601) (1628:1628:1628)) (IOPATH (posedge clk) q (268:268:268) (268:268:268)) ) ) @@ -49526,7 +35608,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (871:871:871) (874:874:874)) + (PORT clk (872:872:872) (875:875:875)) ) ) ) @@ -49535,7 +35617,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (872:872:872) (875:875:875)) + (PORT clk (873:873:873) (876:876:876)) ) ) ) @@ -49544,7 +35626,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (872:872:872) (875:875:875)) + (PORT clk (873:873:873) (876:876:876)) (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) @@ -49554,24 +35636,306 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (872:872:872) (875:875:875)) + (PORT clk (873:873:873) (876:876:876)) (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~71) + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) (DELAY (ABSOLUTE - (PORT dataa (209:209:209) (250:250:250)) - (PORT datab (847:847:847) (835:835:835)) - (PORT datac (1051:1051:1051) (1049:1049:1049)) - (PORT datad (164:164:164) (189:189:189)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (PORT d[0] (2394:2394:2394) (2434:2434:2434)) + (PORT d[1] (2672:2672:2672) (2672:2672:2672)) + (PORT d[2] (1881:1881:1881) (1944:1944:1944)) + (PORT d[3] (2283:2283:2283) (2334:2334:2334)) + (PORT d[4] (2192:2192:2192) (2241:2241:2241)) + (PORT d[5] (2228:2228:2228) (2259:2259:2259)) + (PORT d[6] (3010:3010:3010) (3035:3035:3035)) + (PORT d[7] (1929:1929:1929) (1959:1959:1959)) + (PORT d[8] (2238:2238:2238) (2254:2254:2254)) + (PORT d[9] (2787:2787:2787) (2887:2887:2887)) + (PORT d[10] (3599:3599:3599) (3764:3764:3764)) + (PORT d[11] (2151:2151:2151) (2171:2171:2171)) + (PORT d[12] (2506:2506:2506) (2507:2507:2507)) + (PORT clk (1646:1646:1646) (1674:1674:1674)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1674:1674:1674)) + (PORT d[0] (3365:3365:3365) (3316:3316:3316)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1675:1675:1675)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1613:1613:1613) (1640:1640:1640)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (884:884:884) (887:887:887)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (885:885:885) (888:888:888)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (885:885:885) (888:888:888)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (885:885:885) (888:888:888)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1503:1503:1503) (1539:1539:1539)) + (PORT clk (1634:1634:1634) (1662:1662:1662)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2906:2906:2906) (3037:3037:3037)) + (PORT d[1] (3692:3692:3692) (3703:3703:3703)) + (PORT d[2] (1911:1911:1911) (1992:1992:1992)) + (PORT d[3] (2069:2069:2069) (2136:2136:2136)) + (PORT d[4] (3550:3550:3550) (3598:3598:3598)) + (PORT d[5] (2202:2202:2202) (2238:2238:2238)) + (PORT d[6] (2795:2795:2795) (2832:2832:2832)) + (PORT d[7] (2799:2799:2799) (2869:2869:2869)) + (PORT d[8] (2281:2281:2281) (2323:2323:2323)) + (PORT d[9] (2292:2292:2292) (2373:2373:2373)) + (PORT d[10] (2725:2725:2725) (2843:2843:2843)) + (PORT d[11] (2152:2152:2152) (2176:2176:2176)) + (PORT d[12] (2837:2837:2837) (2854:2854:2854)) + (PORT clk (1631:1631:1631) (1660:1660:1660)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1893:1893:1893) (1837:1837:1837)) + (PORT clk (1631:1631:1631) (1660:1660:1660)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1634:1634:1634) (1662:1662:1662)) + (PORT d[0] (5023:5023:5023) (4998:4998:4998)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1635:1635:1635) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1635:1635:1635) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1635:1635:1635) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1635:1635:1635) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1593:1593:1593) (1592:1592:1592)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1957:1957:1957) (2081:2081:2081)) + (PORT clk (1601:1601:1601) (1599:1599:1599)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3872:3872:3872) (3842:3842:3842)) + (PORT d[1] (3976:3976:3976) (3952:3952:3952)) + (PORT d[2] (3830:3830:3830) (3771:3771:3771)) + (PORT d[3] (3949:3949:3949) (3932:3932:3932)) + (PORT d[4] (3814:3814:3814) (3807:3807:3807)) + (PORT d[5] (4059:4059:4059) (3992:3992:3992)) + (PORT d[6] (3823:3823:3823) (3706:3706:3706)) + (PORT d[7] (3790:3790:3790) (3733:3733:3733)) + (PORT d[8] (3947:3947:3947) (3842:3842:3842)) + (PORT d[9] (3826:3826:3826) (3811:3811:3811)) + (PORT d[10] (3897:3897:3897) (3851:3851:3851)) + (PORT d[11] (4016:4016:4016) (3932:3932:3932)) + (PORT d[12] (3912:3912:3912) (3823:3823:3823)) + (PORT clk (1598:1598:1598) (1596:1596:1596)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1601:1601:1601) (1599:1599:1599)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1602:1602:1602) (1600:1600:1600)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1602:1602:1602) (1600:1600:1600)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1602:1602:1602) (1600:1600:1600)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1602:1602:1602) (1600:1600:1600)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) ) @@ -49580,8 +35944,8 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1450:1450:1450) (1449:1449:1449)) - (PORT clk (1648:1648:1648) (1675:1675:1675)) + (PORT d[0] (1511:1511:1511) (1564:1564:1564)) + (PORT clk (1647:1647:1647) (1674:1674:1674)) ) ) (TIMINGCHECK @@ -49593,20 +35957,20 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2348:2348:2348) (2361:2361:2361)) - (PORT d[1] (1826:1826:1826) (1904:1904:1904)) - (PORT d[2] (1810:1810:1810) (1851:1851:1851)) - (PORT d[3] (1736:1736:1736) (1783:1783:1783)) - (PORT d[4] (2527:2527:2527) (2584:2584:2584)) - (PORT d[5] (2063:2063:2063) (2160:2160:2160)) - (PORT d[6] (1896:1896:1896) (1915:1915:1915)) - (PORT d[7] (2227:2227:2227) (2299:2299:2299)) - (PORT d[8] (2227:2227:2227) (2294:2294:2294)) - (PORT d[9] (1856:1856:1856) (1895:1895:1895)) - (PORT d[10] (1573:1573:1573) (1593:1593:1593)) - (PORT d[11] (1905:1905:1905) (1933:1933:1933)) - (PORT d[12] (2334:2334:2334) (2363:2363:2363)) - (PORT clk (1645:1645:1645) (1673:1673:1673)) + (PORT d[0] (2820:2820:2820) (2831:2831:2831)) + (PORT d[1] (3165:3165:3165) (3137:3137:3137)) + (PORT d[2] (2162:2162:2162) (2246:2246:2246)) + (PORT d[3] (2249:2249:2249) (2301:2301:2301)) + (PORT d[4] (2493:2493:2493) (2544:2544:2544)) + (PORT d[5] (2490:2490:2490) (2529:2529:2529)) + (PORT d[6] (3493:3493:3493) (3501:3501:3501)) + (PORT d[7] (1972:1972:1972) (2002:2002:2002)) + (PORT d[8] (2430:2430:2430) (2453:2453:2453)) + (PORT d[9] (2778:2778:2778) (2862:2862:2862)) + (PORT d[10] (3382:3382:3382) (3555:3555:3555)) + (PORT d[11] (2471:2471:2471) (2505:2505:2505)) + (PORT d[12] (2752:2752:2752) (2772:2772:2772)) + (PORT clk (1644:1644:1644) (1672:1672:1672)) ) ) (TIMINGCHECK @@ -49618,8 +35982,8 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2467:2467:2467) (2383:2383:2383)) - (PORT clk (1645:1645:1645) (1673:1673:1673)) + (PORT d[0] (2357:2357:2357) (2337:2337:2337)) + (PORT clk (1644:1644:1644) (1672:1672:1672)) ) ) (TIMINGCHECK @@ -49631,8 +35995,8 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1648:1648:1648) (1675:1675:1675)) - (PORT d[0] (3048:3048:3048) (3059:3059:3059)) + (PORT clk (1647:1647:1647) (1674:1674:1674)) + (PORT d[0] (4457:4457:4457) (4492:4492:4492)) ) ) ) @@ -49641,7 +36005,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1649:1649:1649) (1676:1676:1676)) + (PORT clk (1648:1648:1648) (1675:1675:1675)) (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) ) ) @@ -49651,7 +36015,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1649:1649:1649) (1676:1676:1676)) + (PORT clk (1648:1648:1648) (1675:1675:1675)) (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) ) ) @@ -49661,7 +36025,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1649:1649:1649) (1676:1676:1676)) + (PORT clk (1648:1648:1648) (1675:1675:1675)) (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) ) ) @@ -49671,7 +36035,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1649:1649:1649) (1676:1676:1676)) + (PORT clk (1648:1648:1648) (1675:1675:1675)) (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) ) ) @@ -49681,7 +36045,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1607:1607:1607) (1605:1605:1605)) + (PORT clk (1606:1606:1606) (1604:1604:1604)) (IOPATH (posedge clk) q (268:268:268) (268:268:268)) ) ) @@ -49695,8 +36059,8 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_b_register) (DELAY (ABSOLUTE - (PORT d[0] (1916:1916:1916) (1862:1862:1862)) - (PORT clk (1615:1615:1615) (1612:1612:1612)) + (PORT d[0] (939:939:939) (942:942:942)) + (PORT clk (1614:1614:1614) (1611:1611:1611)) ) ) (TIMINGCHECK @@ -49708,20 +36072,20 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_b_register) (DELAY (ABSOLUTE - (PORT d[0] (4316:4316:4316) (4210:4210:4210)) - (PORT d[1] (3963:3963:3963) (3872:3872:3872)) - (PORT d[2] (4234:4234:4234) (4138:4138:4138)) - (PORT d[3] (4142:4142:4142) (4039:4039:4039)) - (PORT d[4] (4033:4033:4033) (3901:3901:3901)) - (PORT d[5] (4276:4276:4276) (4177:4177:4177)) - (PORT d[6] (4393:4393:4393) (4366:4366:4366)) - (PORT d[7] (4261:4261:4261) (4171:4171:4171)) - (PORT d[8] (4248:4248:4248) (4146:4146:4146)) - (PORT d[9] (4156:4156:4156) (4242:4242:4242)) - (PORT d[10] (4088:4088:4088) (4006:4006:4006)) - (PORT d[11] (4322:4322:4322) (4216:4216:4216)) - (PORT d[12] (4272:4272:4272) (4307:4307:4307)) - (PORT clk (1612:1612:1612) (1609:1609:1609)) + (PORT d[0] (3921:3921:3921) (3811:3811:3811)) + (PORT d[1] (3928:3928:3928) (3888:3888:3888)) + (PORT d[2] (3912:3912:3912) (3835:3835:3835)) + (PORT d[3] (3857:3857:3857) (3790:3790:3790)) + (PORT d[4] (3842:3842:3842) (3816:3816:3816)) + (PORT d[5] (4034:4034:4034) (3955:3955:3955)) + (PORT d[6] (3896:3896:3896) (3795:3795:3795)) + (PORT d[7] (3789:3789:3789) (3732:3732:3732)) + (PORT d[8] (3965:3965:3965) (3957:3957:3957)) + (PORT d[9] (3792:3792:3792) (3772:3772:3772)) + (PORT d[10] (3922:3922:3922) (3874:3874:3874)) + (PORT d[11] (3913:3913:3913) (3770:3770:3770)) + (PORT d[12] (3933:3933:3933) (3866:3866:3866)) + (PORT clk (1611:1611:1611) (1608:1608:1608)) ) ) (TIMINGCHECK @@ -49733,7 +36097,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (1615:1615:1615) (1612:1612:1612)) + (PORT clk (1614:1614:1614) (1611:1611:1611)) ) ) ) @@ -49742,7 +36106,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_b) (DELAY (ABSOLUTE - (PORT clk (1616:1616:1616) (1613:1613:1613)) + (PORT clk (1615:1615:1615) (1612:1612:1612)) (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) ) ) @@ -49752,7 +36116,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1616:1616:1616) (1613:1613:1613)) + (PORT clk (1615:1615:1615) (1612:1612:1612)) (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178)) ) ) @@ -49762,7 +36126,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (1616:1616:1616) (1613:1613:1613)) + (PORT clk (1615:1615:1615) (1612:1612:1612)) (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) @@ -49772,7 +36136,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (1616:1616:1616) (1613:1613:1613)) + (PORT clk (1615:1615:1615) (1612:1612:1612)) (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) @@ -49782,7 +36146,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_b_register) (DELAY (ABSOLUTE - (PORT clk (1608:1608:1608) (1606:1606:1606)) + (PORT clk (1607:1607:1607) (1605:1605:1605)) (IOPATH (posedge clk) q (268:268:268) (268:268:268)) ) ) @@ -49793,15 +36157,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~72) + (INSTANCE Selector3\~1) (DELAY (ABSOLUTE - (PORT dataa (828:828:828) (850:850:850)) - (PORT datab (189:189:189) (224:224:224)) - (PORT datac (156:156:156) (187:187:187)) - (PORT datad (1365:1365:1365) (1368:1368:1368)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) + (PORT dataa (578:578:578) (598:598:598)) + (PORT datab (1624:1624:1624) (1602:1602:1602)) + (PORT datac (1153:1153:1153) (1178:1178:1178)) + (PORT datad (1407:1407:1407) (1424:1424:1424)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -49809,15 +36173,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~108) + (INSTANCE Selector3\~2) (DELAY (ABSOLUTE - (PORT dataa (1483:1483:1483) (1482:1482:1482)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (1506:1506:1506) (1523:1523:1523)) - (PORT datad (158:158:158) (179:179:179)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (319:319:319) (324:324:324)) + (PORT dataa (1221:1221:1221) (1227:1227:1227)) + (PORT datab (1622:1622:1622) (1602:1602:1602)) + (PORT datac (1602:1602:1602) (1587:1587:1587)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -49825,13 +36189,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~95) + (INSTANCE D\[3\]\~85) (DELAY (ABSOLUTE - (PORT dataa (191:191:191) (233:233:233)) - (PORT datab (1305:1305:1305) (1292:1292:1292)) - (PORT datac (1230:1230:1230) (1217:1217:1217)) - (PORT datad (316:316:316) (319:319:319)) + (PORT dataa (1747:1747:1747) (1826:1826:1826)) + (PORT datab (2886:2886:2886) (2927:2927:2927)) + (PORT datac (157:157:157) (188:188:188)) + (PORT datad (159:159:159) (181:181:181)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~73) + (DELAY + (ABSOLUTE + (PORT dataa (2057:2057:2057) (2057:2057:2057)) + (PORT datab (1536:1536:1536) (1514:1514:1514)) + (PORT datac (1037:1037:1037) (1065:1065:1065)) + (PORT datad (165:165:165) (187:187:187)) (IOPATH dataa combout (290:290:290) (306:306:306)) (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (220:220:220) (215:215:215)) @@ -49841,16 +36221,16 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~96) + (INSTANCE D\[3\]\~74) (DELAY (ABSOLUTE - (PORT dataa (1518:1518:1518) (1480:1480:1480)) - (PORT datab (1303:1303:1303) (1289:1289:1289)) - (PORT datac (1032:1032:1032) (1052:1052:1052)) - (PORT datad (298:298:298) (295:295:295)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT dataa (1824:1824:1824) (1806:1806:1806)) + (PORT datab (1535:1535:1535) (1513:1513:1513)) + (PORT datac (1516:1516:1516) (1494:1494:1494)) + (PORT datad (158:158:158) (179:179:179)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -49860,12 +36240,12 @@ (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[3\]) (DELAY (ABSOLUTE - (PORT dataa (904:904:904) (946:946:946)) - (PORT datab (1541:1541:1541) (1532:1532:1532)) - (PORT datac (211:211:211) (260:260:260)) - (PORT datad (820:820:820) (816:816:816)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) + (PORT dataa (1319:1319:1319) (1315:1315:1315)) + (PORT datab (364:364:364) (391:391:391)) + (PORT datac (768:768:768) (780:780:780)) + (PORT datad (1377:1377:1377) (1353:1353:1353)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -49876,9 +36256,9 @@ (INSTANCE z80_\|data_pins_\|dout\[3\]) (DELAY (ABSOLUTE - (PORT clk (1347:1347:1347) (1358:1358:1358)) + (PORT clk (1348:1348:1348) (1359:1359:1359)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (763:763:763) (771:771:771)) + (PORT ena (744:744:744) (751:751:751)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -49892,11 +36272,11 @@ (INSTANCE z80_\|bus_control_\|db\[3\]\~20) (DELAY (ABSOLUTE - (PORT dataa (227:227:227) (279:279:279)) - (PORT datab (604:604:604) (646:646:646)) - (PORT datad (194:194:194) (223:223:223)) - (IOPATH dataa combout (267:267:267) (273:273:273)) - (IOPATH datab combout (265:265:265) (275:275:275)) + (PORT datab (329:329:329) (359:359:359)) + (PORT datac (316:316:316) (331:331:331)) + (PORT datad (352:352:352) (385:385:385)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -49906,26 +36286,38 @@ (INSTANCE z80_\|bus_control_\|db\[3\]\~21) (DELAY (ABSOLUTE - (PORT dataa (907:907:907) (908:908:908)) - (PORT datab (837:837:837) (858:858:858)) - (PORT datac (817:817:817) (833:833:833)) - (PORT datad (850:850:850) (853:853:853)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT dataa (667:667:667) (694:694:694)) + (PORT datab (638:638:638) (658:658:658)) + (PORT datac (554:554:554) (573:573:573)) + (PORT datad (1547:1547:1547) (1514:1514:1514)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[3\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\~2) (DELAY (ABSOLUTE - (PORT clk (1345:1345:1345) (1366:1366:1366)) + (PORT datab (246:246:246) (297:297:297)) + (PORT datac (223:223:223) (284:284:284)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|interrupts_\|im2) + (DELAY + (ABSOLUTE + (PORT clk (1363:1363:1363) (1384:1384:1384)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1390:1390:1390) (1361:1361:1361)) - (PORT ena (1363:1363:1363) (1319:1319:1319)) + (PORT clrn (1388:1388:1388) (1362:1362:1362)) + (PORT ena (1359:1359:1359) (1330:1330:1330)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -49937,13 +36329,2008 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~4) + (INSTANCE z80_\|execute_\|ctl_mRead\~10) (DELAY (ABSOLUTE - (PORT dataa (1349:1349:1349) (1408:1408:1408)) - (PORT datab (1083:1083:1083) (1086:1086:1086)) - (PORT datac (1096:1096:1096) (1157:1157:1157)) - (PORT datad (1293:1293:1293) (1285:1285:1285)) + (PORT dataa (442:442:442) (510:510:510)) + (PORT datab (829:829:829) (850:850:850)) + (PORT datac (241:241:241) (320:320:320)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_mask543_en\~0) + (DELAY + (ABSOLUTE + (PORT dataa (446:446:446) (516:516:516)) + (PORT datab (201:201:201) (235:235:235)) + (PORT datac (567:567:567) (570:570:570)) + (PORT datad (827:827:827) (816:816:816)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[7\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1243:1243:1243) (1342:1342:1342)) + (PORT datab (549:549:549) (540:540:540)) + (PORT datac (767:767:767) (753:753:753)) + (PORT datad (511:511:511) (498:498:498)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[7\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (862:862:862) (860:860:860)) + (PORT datab (343:343:343) (349:349:349)) + (PORT datac (518:518:518) (519:519:519)) + (PORT datad (184:184:184) (208:208:208)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[7\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (790:790:790) (786:786:786)) + (PORT datab (629:629:629) (620:620:620)) + (PORT datac (370:370:370) (394:394:394)) + (PORT datad (158:158:158) (179:179:179)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[7\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (220:220:220)) + (PORT datad (338:338:338) (341:341:341)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[7\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1300:1300:1300) (1276:1276:1276)) + (PORT datab (331:331:331) (356:356:356)) + (PORT datad (1254:1254:1254) (1223:1223:1223)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[5\]\~67) + (DELAY + (ABSOLUTE + (PORT dataa (227:227:227) (278:278:278)) + (PORT datab (2582:2582:2582) (2638:2638:2638)) + (PORT datac (510:510:510) (510:510:510)) + (PORT datad (566:566:566) (564:564:564)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (406:406:406) (412:412:412)) + (PORT clk (1644:1644:1644) (1671:1671:1671)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3089:3089:3089) (3185:3185:3185)) + (PORT d[1] (1447:1447:1447) (1474:1474:1474)) + (PORT d[2] (1729:1729:1729) (1750:1750:1750)) + (PORT d[3] (2470:2470:2470) (2584:2584:2584)) + (PORT d[4] (3006:3006:3006) (3080:3080:3080)) + (PORT d[5] (3682:3682:3682) (3706:3706:3706)) + (PORT d[6] (1479:1479:1479) (1519:1519:1519)) + (PORT d[7] (2108:2108:2108) (2208:2208:2208)) + (PORT d[8] (2774:2774:2774) (2817:2817:2817)) + (PORT d[9] (1632:1632:1632) (1650:1650:1650)) + (PORT d[10] (3658:3658:3658) (3847:3847:3847)) + (PORT d[11] (3326:3326:3326) (3420:3420:3420)) + (PORT d[12] (1644:1644:1644) (1653:1653:1653)) + (PORT clk (1641:1641:1641) (1669:1669:1669)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1653:1653:1653) (1618:1618:1618)) + (PORT clk (1641:1641:1641) (1669:1669:1669)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1671:1671:1671)) + (PORT d[0] (2442:2442:2442) (2392:2392:2392)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1672:1672:1672)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1672:1672:1672)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1672:1672:1672)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1672:1672:1672)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1608:1608:1608) (1635:1635:1635)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (882:882:882)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (883:883:883)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (883:883:883)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (883:883:883)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (661:661:661) (662:662:662)) + (PORT clk (1645:1645:1645) (1672:1672:1672)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3353:3353:3353) (3446:3446:3446)) + (PORT d[1] (1472:1472:1472) (1498:1498:1498)) + (PORT d[2] (1464:1464:1464) (1509:1509:1509)) + (PORT d[3] (2734:2734:2734) (2853:2853:2853)) + (PORT d[4] (3275:3275:3275) (3336:3336:3336)) + (PORT d[5] (3709:3709:3709) (3736:3736:3736)) + (PORT d[6] (1478:1478:1478) (1510:1510:1510)) + (PORT d[7] (2134:2134:2134) (2237:2237:2237)) + (PORT d[8] (3048:3048:3048) (3090:3090:3090)) + (PORT d[9] (1660:1660:1660) (1680:1680:1680)) + (PORT d[10] (3661:3661:3661) (3852:3852:3852)) + (PORT d[11] (3331:3331:3331) (3426:3426:3426)) + (PORT d[12] (1612:1612:1612) (1623:1623:1623)) + (PORT clk (1642:1642:1642) (1670:1670:1670)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1698:1698:1698) (1650:1650:1650)) + (PORT clk (1642:1642:1642) (1670:1670:1670)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1672:1672:1672)) + (PORT d[0] (2336:2336:2336) (2312:2312:2312)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1636:1636:1636)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (883:883:883)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (884:884:884)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (884:884:884)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (884:884:884)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (768:768:768) (738:738:738)) + (PORT datab (1328:1328:1328) (1373:1373:1373)) + (PORT datac (811:811:811) (791:791:791)) + (PORT datad (1377:1377:1377) (1420:1420:1420)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (655:655:655) (677:677:677)) + (PORT clk (1646:1646:1646) (1672:1672:1672)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3367:3367:3367) (3470:3470:3470)) + (PORT d[1] (1191:1191:1191) (1214:1214:1214)) + (PORT d[2] (1183:1183:1183) (1204:1204:1204)) + (PORT d[3] (2778:2778:2778) (2899:2899:2899)) + (PORT d[4] (3264:3264:3264) (3340:3340:3340)) + (PORT d[5] (3952:3952:3952) (3969:3969:3969)) + (PORT d[6] (1223:1223:1223) (1256:1256:1256)) + (PORT d[7] (2373:2373:2373) (2488:2488:2488)) + (PORT d[8] (3068:3068:3068) (3117:3117:3117)) + (PORT d[9] (1902:1902:1902) (1891:1891:1891)) + (PORT d[10] (3693:3693:3693) (3893:3893:3893)) + (PORT d[11] (3319:3319:3319) (3419:3419:3419)) + (PORT d[12] (1395:1395:1395) (1401:1401:1401)) + (PORT clk (1643:1643:1643) (1670:1670:1670)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1369:1369:1369) (1332:1332:1332)) + (PORT clk (1643:1643:1643) (1670:1670:1670)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1672:1672:1672)) + (PORT d[0] (2441:2441:2441) (2403:2403:2403)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1610:1610:1610) (1636:1636:1636)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (883:883:883)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (884:884:884)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (884:884:884)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (884:884:884)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (940:940:940) (942:942:942)) + (PORT clk (1646:1646:1646) (1674:1674:1674)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2739:2739:2739) (2867:2867:2867)) + (PORT d[1] (1185:1185:1185) (1203:1203:1203)) + (PORT d[2] (1179:1179:1179) (1200:1200:1200)) + (PORT d[3] (3075:3075:3075) (3217:3217:3217)) + (PORT d[4] (3527:3527:3527) (3613:3613:3613)) + (PORT d[5] (1363:1363:1363) (1351:1351:1351)) + (PORT d[6] (1214:1214:1214) (1240:1240:1240)) + (PORT d[7] (2411:2411:2411) (2528:2528:2528)) + (PORT d[8] (3042:3042:3042) (3098:3098:3098)) + (PORT d[9] (1387:1387:1387) (1392:1392:1392)) + (PORT d[10] (3952:3952:3952) (4164:4164:4164)) + (PORT d[11] (3606:3606:3606) (3716:3716:3716)) + (PORT d[12] (1379:1379:1379) (1383:1383:1383)) + (PORT clk (1643:1643:1643) (1672:1672:1672)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1515:1515:1515) (1439:1439:1439)) + (PORT clk (1643:1643:1643) (1672:1672:1672)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1674:1674:1674)) + (PORT d[0] (2262:2262:2262) (2203:2203:2203)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1675:1675:1675)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1675:1675:1675)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1675:1675:1675)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1675:1675:1675)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1610:1610:1610) (1638:1638:1638)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (885:885:885)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (886:886:886)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (886:886:886)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (886:886:886)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (219:219:219)) + (PORT datab (1087:1087:1087) (1078:1078:1078)) + (PORT datac (1657:1657:1657) (1720:1720:1720)) + (PORT datad (1244:1244:1244) (1199:1199:1199)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2303:2303:2303) (2401:2401:2401)) + (PORT d[1] (2520:2520:2520) (2538:2538:2538)) + (PORT d[2] (2055:2055:2055) (2120:2120:2120)) + (PORT d[3] (2162:2162:2162) (2254:2254:2254)) + (PORT d[4] (2457:2457:2457) (2504:2504:2504)) + (PORT d[5] (2698:2698:2698) (2718:2718:2718)) + (PORT d[6] (2485:2485:2485) (2519:2519:2519)) + (PORT d[7] (1843:1843:1843) (1935:1935:1935)) + (PORT d[8] (2227:2227:2227) (2246:2246:2246)) + (PORT d[9] (2705:2705:2705) (2721:2721:2721)) + (PORT d[10] (3774:3774:3774) (3985:3985:3985)) + (PORT d[11] (2734:2734:2734) (2801:2801:2801)) + (PORT d[12] (2191:2191:2191) (2219:2219:2219)) + (PORT clk (1650:1650:1650) (1678:1678:1678)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1650:1650:1650) (1678:1678:1678)) + (PORT d[0] (2507:2507:2507) (2484:2484:2484)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1651:1651:1651) (1679:1679:1679)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1617:1617:1617) (1644:1644:1644)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (888:888:888) (891:891:891)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (889:889:889) (892:892:892)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (889:889:889) (892:892:892)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (889:889:889) (892:892:892)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1004:1004:1004) (975:975:975)) + (PORT clk (1639:1639:1639) (1667:1667:1667)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3104:3104:3104) (3198:3198:3198)) + (PORT d[1] (1791:1791:1791) (1824:1824:1824)) + (PORT d[2] (1760:1760:1760) (1814:1814:1814)) + (PORT d[3] (2743:2743:2743) (2845:2845:2845)) + (PORT d[4] (3015:3015:3015) (3073:3073:3073)) + (PORT d[5] (3424:3424:3424) (3438:3438:3438)) + (PORT d[6] (2996:2996:2996) (3032:3032:3032)) + (PORT d[7] (2088:2088:2088) (2180:2180:2180)) + (PORT d[8] (2761:2761:2761) (2794:2794:2794)) + (PORT d[9] (3134:3134:3134) (3148:3148:3148)) + (PORT d[10] (3659:3659:3659) (3832:3832:3832)) + (PORT d[11] (3063:3063:3063) (3152:3152:3152)) + (PORT d[12] (1901:1901:1901) (1913:1913:1913)) + (PORT clk (1636:1636:1636) (1665:1665:1665)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2860:2860:2860) (2809:2809:2809)) + (PORT clk (1636:1636:1636) (1665:1665:1665)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1667:1667:1667)) + (PORT d[0] (2777:2777:2777) (2742:2742:2742)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1640:1640:1640) (1668:1668:1668)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1640:1640:1640) (1668:1668:1668)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1640:1640:1640) (1668:1668:1668)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1640:1640:1640) (1668:1668:1668)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1598:1598:1598) (1597:1597:1597)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2246:2246:2246) (2362:2362:2362)) + (PORT clk (1606:1606:1606) (1604:1604:1604)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3938:3938:3938) (3833:3833:3833)) + (PORT d[1] (4051:4051:4051) (3970:3970:3970)) + (PORT d[2] (3872:3872:3872) (3760:3760:3760)) + (PORT d[3] (3859:3859:3859) (3798:3798:3798)) + (PORT d[4] (3818:3818:3818) (3800:3800:3800)) + (PORT d[5] (4019:4019:4019) (3954:3954:3954)) + (PORT d[6] (3901:3901:3901) (3802:3802:3802)) + (PORT d[7] (3741:3741:3741) (3700:3700:3700)) + (PORT d[8] (3998:3998:3998) (3866:3866:3866)) + (PORT d[9] (3992:3992:3992) (3935:3935:3935)) + (PORT d[10] (3950:3950:3950) (3904:3904:3904)) + (PORT d[11] (4005:4005:4005) (3927:3927:3927)) + (PORT d[12] (3896:3896:3896) (3803:3803:3803)) + (PORT clk (1603:1603:1603) (1601:1601:1601)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1606:1606:1606) (1604:1604:1604)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1607:1607:1607) (1605:1605:1605)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1607:1607:1607) (1605:1605:1605)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1607:1607:1607) (1605:1605:1605)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1607:1607:1607) (1605:1605:1605)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1127:1127:1127) (1103:1103:1103)) + (PORT clk (1639:1639:1639) (1665:1665:1665)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3074:3074:3074) (3157:3157:3157)) + (PORT d[1] (2767:2767:2767) (2799:2799:2799)) + (PORT d[2] (1753:1753:1753) (1809:1809:1809)) + (PORT d[3] (2180:2180:2180) (2283:2283:2283)) + (PORT d[4] (3007:3007:3007) (3062:3062:3062)) + (PORT d[5] (3423:3423:3423) (3437:3437:3437)) + (PORT d[6] (2173:2173:2173) (2195:2195:2195)) + (PORT d[7] (2038:2038:2038) (2101:2101:2101)) + (PORT d[8] (2485:2485:2485) (2490:2490:2490)) + (PORT d[9] (2083:2083:2083) (2097:2097:2097)) + (PORT d[10] (3389:3389:3389) (3572:3572:3572)) + (PORT d[11] (3044:3044:3044) (3111:3111:3111)) + (PORT d[12] (1887:1887:1887) (1907:1907:1907)) + (PORT clk (1636:1636:1636) (1663:1663:1663)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2023:2023:2023) (1960:1960:1960)) + (PORT clk (1636:1636:1636) (1663:1663:1663)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1665:1665:1665)) + (PORT d[0] (2747:2747:2747) (2775:2775:2775)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1640:1640:1640) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1640:1640:1640) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1640:1640:1640) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1640:1640:1640) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1598:1598:1598) (1595:1595:1595)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2479:2479:2479) (2595:2595:2595)) + (PORT clk (1606:1606:1606) (1602:1602:1602)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3910:3910:3910) (3793:3793:3793)) + (PORT d[1] (3839:3839:3839) (3776:3776:3776)) + (PORT d[2] (3982:3982:3982) (3914:3914:3914)) + (PORT d[3] (3858:3858:3858) (3795:3795:3795)) + (PORT d[4] (3805:3805:3805) (3800:3800:3800)) + (PORT d[5] (4078:4078:4078) (3965:3965:3965)) + (PORT d[6] (3948:3948:3948) (3855:3855:3855)) + (PORT d[7] (3869:3869:3869) (3772:3772:3772)) + (PORT d[8] (4010:4010:4010) (3897:3897:3897)) + (PORT d[9] (4011:4011:4011) (3958:3958:3958)) + (PORT d[10] (3935:3935:3935) (3885:3885:3885)) + (PORT d[11] (4009:4009:4009) (3933:3933:3933)) + (PORT d[12] (3799:3799:3799) (3747:3747:3747)) + (PORT clk (1603:1603:1603) (1599:1599:1599)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1606:1606:1606) (1602:1602:1602)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1607:1607:1607) (1603:1603:1603)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1607:1607:1607) (1603:1603:1603)) + (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1607:1607:1607) (1603:1603:1603)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1607:1607:1607) (1603:1603:1603)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1599:1599:1599) (1596:1596:1596)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Mux0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1581:1581:1581) (1664:1664:1664)) + (PORT datab (623:623:623) (636:636:636)) + (PORT datac (802:802:802) (786:786:786)) + (PORT datad (1127:1127:1127) (1165:1165:1165)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2570:2570:2570) (2667:2667:2667)) + (PORT d[1] (2280:2280:2280) (2286:2286:2286)) + (PORT d[2] (2272:2272:2272) (2332:2332:2332)) + (PORT d[3] (2431:2431:2431) (2534:2534:2534)) + (PORT d[4] (2222:2222:2222) (2255:2255:2255)) + (PORT d[5] (2434:2434:2434) (2446:2446:2446)) + (PORT d[6] (2267:2267:2267) (2325:2325:2325)) + (PORT d[7] (2076:2076:2076) (2170:2170:2170)) + (PORT d[8] (1970:1970:1970) (1968:1968:1968)) + (PORT d[9] (2712:2712:2712) (2748:2748:2748)) + (PORT d[10] (3517:3517:3517) (3728:3728:3728)) + (PORT d[11] (2395:2395:2395) (2375:2375:2375)) + (PORT d[12] (2565:2565:2565) (2562:2562:2562)) + (PORT clk (1654:1654:1654) (1681:1681:1681)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1681:1681:1681)) + (PORT d[0] (2512:2512:2512) (2523:2523:2523)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1655:1655:1655) (1682:1682:1682)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1621:1621:1621) (1647:1647:1647)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (892:892:892) (894:894:894)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (893:893:893) (895:895:895)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (893:893:893) (895:895:895)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (893:893:893) (895:895:895)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Mux0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1581:1581:1581) (1663:1663:1663)) + (PORT datab (1354:1354:1354) (1349:1349:1349)) + (PORT datac (156:156:156) (187:187:187)) + (PORT datad (1353:1353:1353) (1350:1350:1350)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[7\]\~89) + (DELAY + (ABSOLUTE + (PORT dataa (1912:1912:1912) (1902:1902:1902)) + (PORT datab (181:181:181) (213:213:213)) + (PORT datac (1562:1562:1562) (1581:1581:1581)) + (PORT datad (159:159:159) (179:179:179)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[7\]\~72) + (DELAY + (ABSOLUTE + (PORT dataa (1300:1300:1300) (1305:1305:1305)) + (PORT datab (1495:1495:1495) (1502:1502:1502)) + (PORT datac (155:155:155) (185:185:185)) + (PORT datad (1312:1312:1312) (1307:1307:1307)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~84) + (DELAY + (ABSOLUTE + (PORT dataa (538:538:538) (539:539:539)) + (PORT datab (2583:2583:2583) (2642:2642:2642)) + (PORT datac (544:544:544) (538:538:538)) + (PORT datad (564:564:564) (564:564:564)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[7\]\~80) + (DELAY + (ABSOLUTE + (PORT datac (176:176:176) (207:207:207)) + (PORT datad (1303:1303:1303) (1313:1313:1313)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[7\]) + (DELAY + (ABSOLUTE + (PORT dataa (1317:1317:1317) (1313:1313:1313)) + (PORT datab (200:200:200) (234:234:234)) + (PORT datac (1057:1057:1057) (1083:1083:1083)) + (PORT datad (340:340:340) (356:356:356)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1348:1348:1348) (1359:1359:1359)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (744:744:744) (751:751:751)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[7\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (374:374:374) (400:400:400)) + (PORT datab (342:342:342) (350:350:350)) + (PORT datac (553:553:553) (566:566:566)) + (PORT datad (543:543:543) (544:544:544)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1362:1362:1362)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1388:1388:1388) (1360:1360:1360)) + (PORT ena (1550:1550:1550) (1520:1520:1520)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (262:262:262) (348:348:348)) + (PORT datab (245:245:245) (317:317:317)) + (PORT datac (363:363:363) (418:418:418)) + (PORT datad (368:368:368) (406:406:406)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal12\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1447:1447:1447) (1533:1533:1533)) + (PORT datab (1443:1443:1443) (1473:1473:1473)) + (PORT datac (1261:1261:1261) (1373:1373:1373)) + (PORT datad (1414:1414:1414) (1455:1455:1455)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1855:1855:1855) (1996:1996:1996)) + (PORT datab (1126:1126:1126) (1157:1157:1157)) + (PORT datac (622:622:622) (637:637:637)) + (PORT datad (1172:1172:1172) (1209:1209:1209)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~24) + (DELAY + (ABSOLUTE + (PORT dataa (1263:1263:1263) (1249:1249:1249)) + (PORT datab (845:845:845) (859:859:859)) + (PORT datac (797:797:797) (813:813:813)) + (PORT datad (1539:1539:1539) (1534:1534:1534)) + (IOPATH dataa combout (307:307:307) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~25) + (DELAY + (ABSOLUTE + (PORT dataa (882:882:882) (919:919:919)) + (PORT datab (587:587:587) (585:585:585)) + (PORT datac (556:556:556) (565:565:565)) + (PORT datad (843:843:843) (859:859:859)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~21) + (DELAY + (ABSOLUTE + (PORT dataa (1599:1599:1599) (1614:1614:1614)) + (PORT datab (275:275:275) (363:363:363)) + (PORT datac (572:572:572) (599:599:599)) + (PORT datad (545:545:545) (535:535:535)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1909:1909:1909) (1953:1953:1953)) + (PORT datab (874:874:874) (886:886:886)) + (PORT datac (1061:1061:1061) (1036:1036:1036)) + (PORT datad (999:999:999) (986:986:986)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1092:1092:1092) (1096:1096:1096)) + (PORT datab (840:840:840) (852:852:852)) + (PORT datac (549:549:549) (568:568:568)) + (PORT datad (375:375:375) (400:400:400)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1910:1910:1910) (1953:1953:1953)) + (PORT datab (1632:1632:1632) (1644:1644:1644)) + (PORT datac (1992:1992:1992) (1987:1987:1987)) + (PORT datad (865:865:865) (859:859:859)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~12) + (DELAY + (ABSOLUTE + (PORT dataa (905:905:905) (923:923:923)) + (PORT datab (678:678:678) (703:703:703)) + (PORT datac (530:530:530) (527:527:527)) + (PORT datad (1036:1036:1036) (1045:1045:1045)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~11) + (DELAY + (ABSOLUTE + (PORT dataa (598:598:598) (585:585:585)) + (PORT datab (613:613:613) (628:628:628)) + (PORT datac (841:841:841) (852:852:852)) + (PORT datad (999:999:999) (986:986:986)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~13) + (DELAY + (ABSOLUTE + (PORT dataa (568:568:568) (581:581:581)) + (PORT datab (650:650:650) (680:680:680)) + (PORT datac (617:617:617) (620:620:620)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~17) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (218:218:218)) + (PORT datab (180:180:180) (212:212:212)) + (PORT datac (1142:1142:1142) (1154:1154:1154)) + (PORT datad (157:157:157) (178:178:178)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~22) + (DELAY + (ABSOLUTE + (PORT dataa (585:585:585) (603:603:603)) + (PORT datab (563:563:563) (576:576:576)) + (PORT datac (1074:1074:1074) (1077:1077:1077)) + (PORT datad (565:565:565) (568:568:568)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~27) + (DELAY + (ABSOLUTE + (PORT dataa (2089:2089:2089) (2076:2076:2076)) + (PORT datab (1341:1341:1341) (1356:1356:1356)) + (PORT datac (1078:1078:1078) (1055:1055:1055)) + (PORT datad (852:852:852) (848:848:848)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~37) + (DELAY + (ABSOLUTE + (PORT dataa (1409:1409:1409) (1407:1407:1407)) + (PORT datab (564:564:564) (573:573:573)) + (PORT datac (921:921:921) (949:949:949)) + (PORT datad (832:832:832) (841:841:841)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~31) + (DELAY + (ABSOLUTE + (PORT dataa (1069:1069:1069) (1055:1055:1055)) + (PORT datab (862:862:862) (856:856:856)) + (PORT datac (825:825:825) (806:806:806)) + (PORT datad (1216:1216:1216) (1196:1196:1196)) + (IOPATH dataa combout (307:307:307) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~29) + (DELAY + (ABSOLUTE + (PORT dataa (667:667:667) (718:718:718)) + (PORT datab (968:968:968) (1058:1058:1058)) + (PORT datac (1182:1182:1182) (1204:1204:1204)) + (PORT datad (924:924:924) (990:990:990)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~30) + (DELAY + (ABSOLUTE + (PORT dataa (1034:1034:1034) (1037:1037:1037)) + (PORT datab (206:206:206) (241:241:241)) + (PORT datac (832:832:832) (843:843:843)) + (PORT datad (863:863:863) (875:875:875)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (308:308:308) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~28) + (DELAY + (ABSOLUTE + (PORT dataa (854:854:854) (839:839:839)) + (PORT datab (1063:1063:1063) (1058:1058:1058)) + (PORT datac (1245:1245:1245) (1234:1234:1234)) + (PORT datad (876:876:876) (921:921:921)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~32) + (DELAY + (ABSOLUTE + (PORT dataa (190:190:190) (229:229:229)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (155:155:155) (186:186:186)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~33) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (220:220:220)) + (PORT datab (194:194:194) (234:234:234)) + (PORT datac (156:156:156) (187:187:187)) + (PORT datad (159:159:159) (181:181:181)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~23) + (DELAY + (ABSOLUTE + (PORT dataa (1352:1352:1352) (1359:1359:1359)) + (PORT datab (805:805:805) (798:798:798)) + (PORT datac (804:804:804) (810:810:810)) + (PORT datad (570:570:570) (584:584:584)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~34) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (220:220:220)) + (PORT datab (584:584:584) (572:572:572)) + (PORT datac (806:806:806) (806:806:806)) + (PORT datad (583:583:583) (593:593:593)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~35) + (DELAY + (ABSOLUTE + (PORT dataa (333:333:333) (366:366:366)) + (PORT datab (874:874:874) (887:887:887)) + (PORT datac (1036:1036:1036) (1021:1021:1021)) + (PORT datad (999:999:999) (983:983:983)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1438:1438:1438) (1477:1477:1477)) + (PORT datab (1095:1095:1095) (1190:1190:1190)) + (PORT datac (574:574:574) (598:598:598)) + (PORT datad (546:546:546) (539:539:539)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~36) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (219:219:219)) + (PORT datab (220:220:220) (264:264:264)) + (PORT datac (562:562:562) (567:567:567)) + (PORT datad (166:166:166) (190:190:190)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_re) + (DELAY + (ABSOLUTE + (PORT dataa (1076:1076:1076) (1081:1081:1081)) + (PORT datac (983:983:983) (959:959:959)) + (PORT datad (704:704:704) (676:676:676)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~118) + (DELAY + (ABSOLUTE + (PORT dataa (911:911:911) (952:952:952)) + (PORT datab (1398:1398:1398) (1426:1426:1426)) + (PORT datac (1059:1059:1059) (1070:1070:1070)) + (PORT datad (1065:1065:1065) (1087:1087:1087)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~119) + (DELAY + (ABSOLUTE + (PORT dataa (1222:1222:1222) (1266:1266:1266)) + (PORT datab (392:392:392) (449:449:449)) + (PORT datac (292:292:292) (295:295:295)) + (PORT datad (579:579:579) (593:593:593)) (IOPATH dataa combout (287:287:287) (289:289:289)) (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) @@ -49953,15 +38340,11438 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_apin_mux\~2) + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~120) (DELAY (ABSOLUTE - (PORT dataa (836:836:836) (868:868:868)) - (PORT datab (202:202:202) (236:236:236)) - (PORT datac (821:821:821) (822:822:822)) + (PORT dataa (182:182:182) (219:219:219)) + (PORT datad (180:180:180) (202:202:202)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1357:1357:1357)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1381:1381:1381) (1360:1360:1360)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~129) + (DELAY + (ABSOLUTE + (PORT dataa (407:407:407) (456:456:456)) + (PORT datab (1125:1125:1125) (1155:1155:1155)) + (PORT datac (311:311:311) (322:322:322)) + (PORT datad (621:621:621) (685:685:685)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~116) + (DELAY + (ABSOLUTE + (PORT dataa (717:717:717) (769:769:769)) + (PORT datab (412:412:412) (473:473:473)) + (PORT datad (928:928:928) (980:980:980)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~134) + (DELAY + (ABSOLUTE + (PORT dataa (913:913:913) (954:954:954)) + (PORT datab (1122:1122:1122) (1137:1137:1137)) + (PORT datad (291:291:291) (298:298:298)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~117) + (DELAY + (ABSOLUTE + (PORT dataa (592:592:592) (634:634:634)) + (PORT datab (317:317:317) (341:341:341)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1342:1342:1342) (1359:1359:1359)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1376:1376:1376) (1357:1357:1357)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~60) + (DELAY + (ABSOLUTE + (PORT dataa (1010:1010:1010) (996:996:996)) + (PORT datab (957:957:957) (1008:1008:1008)) + (PORT datac (363:363:363) (397:397:397)) + (PORT datad (783:783:783) (798:798:798)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|Equal0\~2) + (DELAY + (ABSOLUTE + (PORT datab (867:867:867) (954:954:954)) + (PORT datac (640:640:640) (689:689:689)) + (PORT datad (605:605:605) (637:637:637)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]\~121) + (DELAY + (ABSOLUTE + (PORT dataa (870:870:870) (908:908:908)) + (PORT datab (1425:1425:1425) (1438:1438:1438)) + (PORT datad (342:342:342) (356:356:356)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1357:1357:1357)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1381:1381:1381) (1360:1360:1360)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~115) + (DELAY + (ABSOLUTE + (PORT dataa (193:193:193) (233:233:233)) + (PORT datab (203:203:203) (237:237:237)) + (PORT datad (337:337:337) (337:337:337)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1357:1357:1357)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1381:1381:1381) (1360:1360:1360)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\~4) + (DELAY + (ABSOLUTE + (PORT dataa (403:403:403) (439:439:439)) + (PORT datac (2224:2224:2224) (2274:2274:2274)) + (PORT datad (1350:1350:1350) (1361:1361:1361)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~61) + (DELAY + (ABSOLUTE + (PORT dataa (184:184:184) (220:220:220)) + (PORT datab (1048:1048:1048) (1004:1004:1004)) + (PORT datac (195:195:195) (261:261:261)) + (PORT datad (161:161:161) (182:182:182)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~124) + (DELAY + (ABSOLUTE + (PORT datab (647:647:647) (688:688:688)) + (PORT datac (249:249:249) (327:327:327)) + (PORT datad (611:611:611) (646:646:646)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~125) + (DELAY + (ABSOLUTE + (PORT dataa (917:917:917) (957:957:957)) + (PORT datab (183:183:183) (216:216:216)) + (PORT datac (552:552:552) (544:544:544)) + (PORT datad (2028:2028:2028) (2059:2059:2059)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~126) + (DELAY + (ABSOLUTE + (PORT dataa (570:570:570) (564:564:564)) + (PORT datab (441:441:441) (490:490:490)) + (PORT datad (159:159:159) (179:179:179)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1360:1360:1360)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1376:1376:1376) (1357:1357:1357)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~122) + (DELAY + (ABSOLUTE + (PORT dataa (918:918:918) (957:957:957)) + (PORT datab (2065:2065:2065) (2094:2094:2094)) + (PORT datac (877:877:877) (929:929:929)) + (PORT datad (609:609:609) (643:643:643)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~123) + (DELAY + (ABSOLUTE + (PORT dataa (850:850:850) (833:833:833)) + (PORT datab (183:183:183) (217:217:217)) + (PORT datad (402:402:402) (457:457:457)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1360:1360:1360)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1376:1376:1376) (1357:1357:1357)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~62) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (293:293:293)) + (PORT datab (1924:1924:1924) (1886:1886:1886)) + (PORT datac (808:808:808) (793:793:793)) + (PORT datad (197:197:197) (253:253:253)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~49) + (DELAY + (ABSOLUTE + (PORT dataa (875:875:875) (868:868:868)) + (PORT datab (2081:2081:2081) (2100:2100:2100)) + (PORT datac (773:773:773) (762:762:762)) + (PORT datad (894:894:894) (911:911:911)) (IOPATH dataa combout (290:290:290) (306:306:306)) (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|shifted\~3) + (DELAY + (ABSOLUTE + (PORT datac (999:999:999) (1049:1049:1049)) + (PORT datad (1115:1115:1115) (1145:1145:1145)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~127) + (DELAY + (ABSOLUTE + (PORT dataa (718:718:718) (767:767:767)) + (PORT datab (335:335:335) (354:354:354)) + (PORT datad (181:181:181) (203:203:203)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1381:1381:1381) (1360:1360:1360)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~128) + (DELAY + (ABSOLUTE + (PORT dataa (715:715:715) (766:766:766)) + (PORT datab (816:816:816) (816:816:816)) + (PORT datad (323:323:323) (325:325:325)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1381:1381:1381) (1360:1360:1360)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~63) + (DELAY + (ABSOLUTE + (PORT dataa (786:786:786) (817:817:817)) + (PORT datab (579:579:579) (586:586:586)) + (PORT datac (1149:1149:1149) (1195:1195:1195)) + (PORT datad (1237:1237:1237) (1327:1327:1327)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~64) + (DELAY + (ABSOLUTE + (PORT dataa (793:793:793) (766:766:766)) + (PORT datab (913:913:913) (894:894:894)) + (PORT datac (2667:2667:2667) (2795:2795:2795)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (924:924:924) (928:928:928)) + (PORT clk (1643:1643:1643) (1670:1670:1670)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2146:2146:2146) (2183:2183:2183)) + (PORT d[1] (1183:1183:1183) (1213:1213:1213)) + (PORT d[2] (2003:2003:2003) (2055:2055:2055)) + (PORT d[3] (2303:2303:2303) (2381:2381:2381)) + (PORT d[4] (925:925:925) (960:960:960)) + (PORT d[5] (1164:1164:1164) (1174:1174:1174)) + (PORT d[6] (3251:3251:3251) (3206:3206:3206)) + (PORT d[7] (1760:1760:1760) (1819:1819:1819)) + (PORT d[8] (1153:1153:1153) (1170:1170:1170)) + (PORT d[9] (3195:3195:3195) (3343:3343:3343)) + (PORT d[10] (923:923:923) (938:938:938)) + (PORT d[11] (1410:1410:1410) (1401:1401:1401)) + (PORT d[12] (1876:1876:1876) (1866:1866:1866)) + (PORT clk (1640:1640:1640) (1668:1668:1668)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1357:1357:1357) (1317:1317:1317)) + (PORT clk (1640:1640:1640) (1668:1668:1668)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1670:1670:1670)) + (PORT d[0] (1962:1962:1962) (1903:1903:1903)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1671:1671:1671)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1671:1671:1671)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1671:1671:1671)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1671:1671:1671)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1607:1607:1607) (1634:1634:1634)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (881:881:881)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (882:882:882)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (882:882:882)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (882:882:882)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (915:915:915) (917:917:917)) + (PORT clk (1640:1640:1640) (1668:1668:1668)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2373:2373:2373) (2402:2402:2402)) + (PORT d[1] (1171:1171:1171) (1208:1208:1208)) + (PORT d[2] (2200:2200:2200) (2313:2313:2313)) + (PORT d[3] (2600:2600:2600) (2685:2685:2685)) + (PORT d[4] (689:689:689) (720:720:720)) + (PORT d[5] (1164:1164:1164) (1174:1174:1174)) + (PORT d[6] (3231:3231:3231) (3185:3185:3185)) + (PORT d[7] (1739:1739:1739) (1798:1798:1798)) + (PORT d[8] (1127:1127:1127) (1141:1141:1141)) + (PORT d[9] (3221:3221:3221) (3372:3372:3372)) + (PORT d[10] (919:919:919) (927:927:927)) + (PORT d[11] (1405:1405:1405) (1402:1402:1402)) + (PORT d[12] (2113:2113:2113) (2103:2103:2103)) + (PORT clk (1637:1637:1637) (1666:1666:1666)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1832:1832:1832) (1776:1776:1776)) + (PORT clk (1637:1637:1637) (1666:1666:1666)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1640:1640:1640) (1668:1668:1668)) + (PORT d[0] (1733:1733:1733) (1679:1679:1679)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1669:1669:1669)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1669:1669:1669)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1669:1669:1669)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1669:1669:1669)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1604:1604:1604) (1632:1632:1632)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (875:875:875) (879:879:879)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (880:880:880)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (880:880:880)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (880:880:880)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (903:903:903) (895:895:895)) + (PORT clk (1643:1643:1643) (1670:1670:1670)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2411:2411:2411) (2459:2459:2459)) + (PORT d[1] (1167:1167:1167) (1208:1208:1208)) + (PORT d[2] (2708:2708:2708) (2825:2825:2825)) + (PORT d[3] (916:916:916) (909:909:909)) + (PORT d[4] (686:686:686) (707:707:707)) + (PORT d[5] (1110:1110:1110) (1115:1115:1115)) + (PORT d[6] (905:905:905) (905:905:905)) + (PORT d[7] (2030:2030:2030) (2089:2089:2089)) + (PORT d[8] (1159:1159:1159) (1177:1177:1177)) + (PORT d[9] (895:895:895) (884:884:884)) + (PORT d[10] (4222:4222:4222) (4441:4441:4441)) + (PORT d[11] (1427:1427:1427) (1423:1423:1423)) + (PORT d[12] (2397:2397:2397) (2393:2393:2393)) + (PORT clk (1640:1640:1640) (1668:1668:1668)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (849:849:849) (787:787:787)) + (PORT clk (1640:1640:1640) (1668:1668:1668)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1670:1670:1670)) + (PORT d[0] (1977:1977:1977) (1897:1897:1897)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1671:1671:1671)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1671:1671:1671)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1671:1671:1671)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1671:1671:1671)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1607:1607:1607) (1634:1634:1634)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (881:881:881)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (882:882:882)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (882:882:882)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (882:882:882)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (693:693:693) (687:687:687)) + (PORT clk (1638:1638:1638) (1665:1665:1665)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2409:2409:2409) (2454:2454:2454)) + (PORT d[1] (886:886:886) (902:902:902)) + (PORT d[2] (2456:2456:2456) (2580:2580:2580)) + (PORT d[3] (930:930:930) (934:934:934)) + (PORT d[4] (661:661:661) (677:677:677)) + (PORT d[5] (833:833:833) (816:816:816)) + (PORT d[6] (1139:1139:1139) (1123:1123:1123)) + (PORT d[7] (2024:2024:2024) (2091:2091:2091)) + (PORT d[8] (865:865:865) (854:854:854)) + (PORT d[9] (895:895:895) (881:881:881)) + (PORT d[10] (2009:2009:2009) (2018:2018:2018)) + (PORT d[11] (1110:1110:1110) (1097:1097:1097)) + (PORT d[12] (2150:2150:2150) (2149:2149:2149)) + (PORT clk (1635:1635:1635) (1663:1663:1663)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1111:1111:1111) (1054:1054:1054)) + (PORT clk (1635:1635:1635) (1663:1663:1663)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1665:1665:1665)) + (PORT d[0] (1909:1909:1909) (1839:1839:1839)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1602:1602:1602) (1629:1629:1629)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (876:876:876)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (877:877:877)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (877:877:877)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (877:877:877)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (823:823:823) (853:853:853)) + (PORT datab (813:813:813) (772:772:772)) + (PORT datac (768:768:768) (741:741:741)) + (PORT datad (1278:1278:1278) (1277:1277:1277)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1035:1035:1035) (1018:1018:1018)) + (PORT datab (1030:1030:1030) (1008:1008:1008)) + (PORT datac (156:156:156) (187:187:187)) + (PORT datad (1609:1609:1609) (1662:1662:1662)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1897:1897:1897) (1919:1919:1919)) + (PORT d[1] (1511:1511:1511) (1534:1534:1534)) + (PORT d[2] (2057:2057:2057) (2127:2127:2127)) + (PORT d[3] (2564:2564:2564) (2634:2634:2634)) + (PORT d[4] (948:948:948) (980:980:980)) + (PORT d[5] (1433:1433:1433) (1446:1446:1446)) + (PORT d[6] (3234:3234:3234) (3182:3182:3182)) + (PORT d[7] (1725:1725:1725) (1792:1792:1792)) + (PORT d[8] (1424:1424:1424) (1457:1457:1457)) + (PORT d[9] (3203:3203:3203) (3340:3340:3340)) + (PORT d[10] (905:905:905) (919:919:919)) + (PORT d[11] (881:881:881) (886:886:886)) + (PORT d[12] (1848:1848:1848) (1835:1835:1835)) + (PORT clk (1642:1642:1642) (1670:1670:1670)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1642:1642:1642) (1670:1670:1670)) + (PORT d[0] (2147:2147:2147) (2094:2094:2094)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1671:1671:1671)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1636:1636:1636)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (883:883:883)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (884:884:884)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (884:884:884)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (884:884:884)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1473:1473:1473) (1505:1505:1505)) + (PORT clk (1649:1649:1649) (1677:1677:1677)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2421:2421:2421) (2532:2532:2532)) + (PORT d[1] (2246:2246:2246) (2283:2283:2283)) + (PORT d[2] (2044:2044:2044) (2111:2111:2111)) + (PORT d[3] (2461:2461:2461) (2562:2562:2562)) + (PORT d[4] (2742:2742:2742) (2789:2789:2789)) + (PORT d[5] (3413:3413:3413) (3396:3396:3396)) + (PORT d[6] (2732:2732:2732) (2772:2772:2772)) + (PORT d[7] (1846:1846:1846) (1917:1917:1917)) + (PORT d[8] (2491:2491:2491) (2511:2511:2511)) + (PORT d[9] (2427:2427:2427) (2457:2457:2457)) + (PORT d[10] (3367:3367:3367) (3525:3525:3525)) + (PORT d[11] (3029:3029:3029) (3092:3092:3092)) + (PORT d[12] (2226:2226:2226) (2259:2259:2259)) + (PORT clk (1646:1646:1646) (1675:1675:1675)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2588:2588:2588) (2535:2535:2535)) + (PORT clk (1646:1646:1646) (1675:1675:1675)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1649:1649:1649) (1677:1677:1677)) + (PORT d[0] (3082:3082:3082) (3060:3060:3060)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1650:1650:1650) (1678:1678:1678)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1650:1650:1650) (1678:1678:1678)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1650:1650:1650) (1678:1678:1678)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1650:1650:1650) (1678:1678:1678)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1608:1608:1608) (1607:1607:1607)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2495:2495:2495) (2623:2623:2623)) + (PORT clk (1616:1616:1616) (1614:1614:1614)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3778:3778:3778) (3694:3694:3694)) + (PORT d[1] (3818:3818:3818) (3716:3716:3716)) + (PORT d[2] (3837:3837:3837) (3712:3712:3712)) + (PORT d[3] (3865:3865:3865) (3782:3782:3782)) + (PORT d[4] (3955:3955:3955) (3914:3914:3914)) + (PORT d[5] (4154:4154:4154) (4063:4063:4063)) + (PORT d[6] (3925:3925:3925) (3834:3834:3834)) + (PORT d[7] (3796:3796:3796) (3683:3683:3683)) + (PORT d[8] (3896:3896:3896) (3795:3795:3795)) + (PORT d[9] (3924:3924:3924) (3879:3879:3879)) + (PORT d[10] (3822:3822:3822) (3714:3714:3714)) + (PORT d[11] (3977:3977:3977) (3817:3817:3817)) + (PORT d[12] (3800:3800:3800) (3758:3758:3758)) + (PORT clk (1613:1613:1613) (1611:1611:1611)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1616:1616:1616) (1614:1614:1614)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1617:1617:1617) (1615:1615:1615)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1617:1617:1617) (1615:1615:1615)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1617:1617:1617) (1615:1615:1615)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1617:1617:1617) (1615:1615:1615)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1581:1581:1581) (1646:1646:1646)) + (PORT clk (1631:1631:1631) (1657:1657:1657)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2894:2894:2894) (3027:3027:3027)) + (PORT d[1] (3697:3697:3697) (3698:3698:3698)) + (PORT d[2] (1905:1905:1905) (1993:1993:1993)) + (PORT d[3] (2019:2019:2019) (2070:2070:2070)) + (PORT d[4] (3272:3272:3272) (3316:3316:3316)) + (PORT d[5] (2172:2172:2172) (2205:2205:2205)) + (PORT d[6] (3024:3024:3024) (3033:3033:3033)) + (PORT d[7] (1524:1524:1524) (1565:1565:1565)) + (PORT d[8] (2032:2032:2032) (2084:2084:2084)) + (PORT d[9] (2332:2332:2332) (2359:2359:2359)) + (PORT d[10] (2462:2462:2462) (2622:2622:2622)) + (PORT d[11] (1864:1864:1864) (1881:1881:1881)) + (PORT d[12] (2803:2803:2803) (2819:2819:2819)) + (PORT clk (1628:1628:1628) (1655:1655:1655)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2918:2918:2918) (2903:2903:2903)) + (PORT clk (1628:1628:1628) (1655:1655:1655)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1631:1631:1631) (1657:1657:1657)) + (PORT d[0] (4725:4725:4725) (4747:4747:4747)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1632:1632:1632) (1658:1658:1658)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1632:1632:1632) (1658:1658:1658)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1632:1632:1632) (1658:1658:1658)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1632:1632:1632) (1658:1658:1658)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1590:1590:1590) (1587:1587:1587)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2213:2213:2213) (2332:2332:2332)) + (PORT clk (1598:1598:1598) (1594:1594:1594)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3910:3910:3910) (3858:3858:3858)) + (PORT d[1] (3963:3963:3963) (3928:3928:3928)) + (PORT d[2] (3809:3809:3809) (3769:3769:3769)) + (PORT d[3] (3983:3983:3983) (3979:3979:3979)) + (PORT d[4] (3821:3821:3821) (3799:3799:3799)) + (PORT d[5] (4016:4016:4016) (3943:3943:3943)) + (PORT d[6] (3860:3860:3860) (3743:3743:3743)) + (PORT d[7] (3786:3786:3786) (3726:3726:3726)) + (PORT d[8] (3990:3990:3990) (3872:3872:3872)) + (PORT d[9] (3798:3798:3798) (3777:3777:3777)) + (PORT d[10] (3964:3964:3964) (3922:3922:3922)) + (PORT d[11] (4028:4028:4028) (3953:3953:3953)) + (PORT d[12] (3888:3888:3888) (3784:3784:3784)) + (PORT clk (1595:1595:1595) (1591:1591:1591)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1598:1598:1598) (1594:1594:1594)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1599:1599:1599) (1595:1595:1595)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1599:1599:1599) (1595:1595:1595)) + (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1599:1599:1599) (1595:1595:1595)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1599:1599:1599) (1595:1595:1595)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1591:1591:1591) (1588:1588:1588)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1525:1525:1525) (1521:1521:1521)) + (PORT d[1] (1184:1184:1184) (1214:1214:1214)) + (PORT d[2] (2181:2181:2181) (2298:2298:2298)) + (PORT d[3] (2595:2595:2595) (2661:2661:2661)) + (PORT d[4] (928:928:928) (962:962:962)) + (PORT d[5] (1399:1399:1399) (1397:1397:1397)) + (PORT d[6] (3218:3218:3218) (3175:3175:3175)) + (PORT d[7] (1746:1746:1746) (1796:1796:1796)) + (PORT d[8] (1440:1440:1440) (1474:1474:1474)) + (PORT d[9] (3211:3211:3211) (3358:3358:3358)) + (PORT d[10] (885:885:885) (898:898:898)) + (PORT d[11] (1384:1384:1384) (1371:1371:1371)) + (PORT d[12] (1854:1854:1854) (1844:1844:1844)) + (PORT clk (1641:1641:1641) (1668:1668:1668)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1668:1668:1668)) + (PORT d[0] (2062:2062:2062) (2131:2131:2131)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1642:1642:1642) (1669:1669:1669)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1608:1608:1608) (1634:1634:1634)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (881:881:881)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (882:882:882)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (882:882:882)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (882:882:882)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1282:1282:1282) (1370:1370:1370)) + (PORT datab (810:810:810) (796:796:796)) + (PORT datac (1378:1378:1378) (1408:1408:1408)) + (PORT datad (1034:1034:1034) (1016:1016:1016)) + (IOPATH dataa combout (307:307:307) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector4\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1080:1080:1080) (1083:1083:1083)) + (PORT datab (991:991:991) (958:958:958)) + (PORT datac (1550:1550:1550) (1534:1534:1534)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~86) + (DELAY + (ABSOLUTE + (PORT dataa (2500:2500:2500) (2538:2538:2538)) + (PORT datab (1110:1110:1110) (1159:1159:1159)) + (PORT datac (156:156:156) (187:187:187)) + (PORT datad (295:295:295) (290:290:290)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~75) + (DELAY + (ABSOLUTE + (PORT dataa (826:826:826) (824:824:824)) + (PORT datab (325:325:325) (334:334:334)) + (PORT datac (804:804:804) (803:803:803)) + (PORT datad (165:165:165) (189:189:189)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~76) + (DELAY + (ABSOLUTE + (PORT dataa (827:827:827) (822:822:822)) + (PORT datab (891:891:891) (906:906:906)) + (PORT datac (1425:1425:1425) (1397:1397:1397)) + (PORT datad (159:159:159) (179:179:179)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[4\]) + (DELAY + (ABSOLUTE + (PORT dataa (644:644:644) (670:670:670)) + (PORT datab (362:362:362) (388:388:388)) + (PORT datac (1287:1287:1287) (1275:1275:1275)) + (PORT datad (776:776:776) (781:781:781)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1348:1348:1348) (1359:1359:1359)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (744:744:744) (751:751:751)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[4\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (527:527:527) (529:529:529)) + (PORT datab (352:352:352) (408:408:408)) + (PORT datad (543:543:543) (540:540:540)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[4\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (665:665:665) (690:690:690)) + (PORT datab (609:609:609) (627:627:627)) + (PORT datac (574:574:574) (593:593:593)) + (PORT datad (1550:1550:1550) (1517:1517:1517)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1363:1363:1363) (1384:1384:1384)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1388:1388:1388) (1362:1362:1362)) + (PORT ena (1285:1285:1285) (1246:1246:1246)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal32\~0) + (DELAY + (ABSOLUTE + (PORT datab (1124:1124:1124) (1154:1154:1154)) + (PORT datad (1178:1178:1178) (1209:1209:1209)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal41\~1) + (DELAY + (ABSOLUTE + (PORT dataa (446:446:446) (513:513:513)) + (PORT datab (449:449:449) (510:510:510)) + (PORT datac (858:858:858) (936:936:936)) + (PORT datad (906:906:906) (963:963:963)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal41\~2) + (DELAY + (ABSOLUTE + (PORT dataa (2337:2337:2337) (2423:2423:2423)) + (PORT datab (599:599:599) (612:612:612)) + (PORT datac (776:776:776) (752:752:752)) + (PORT datad (837:837:837) (848:848:848)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal36\~0) + (DELAY + (ABSOLUTE + (PORT dataa (717:717:717) (788:788:788)) + (PORT datab (1764:1764:1764) (1832:1832:1832)) + (PORT datac (1181:1181:1181) (1204:1204:1204)) + (PORT datad (802:802:802) (792:792:792)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_tbl_cb_set) + (DELAY + (ABSOLUTE + (PORT dataa (920:920:920) (956:956:956)) + (PORT datab (852:852:852) (843:843:843)) + (PORT datac (1170:1170:1170) (1170:1170:1170)) + (PORT datad (597:597:597) (615:615:615)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_tbl_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1534:1534:1534) (1561:1561:1561)) + (PORT datab (643:643:643) (682:682:682)) + (PORT datac (1169:1169:1169) (1170:1170:1170)) + (PORT datad (582:582:582) (625:625:625)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|decode_state_\|DFFE_instCB) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1362:1362:1362)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1388:1388:1388) (1361:1361:1361)) + (PORT ena (716:716:716) (714:714:714)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal52\~0) + (DELAY + (ABSOLUTE + (PORT dataa (956:956:956) (1025:1025:1025)) + (PORT datab (917:917:917) (988:988:988)) + (PORT datac (863:863:863) (940:940:940)) + (PORT datad (903:903:903) (961:961:961)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (682:682:682) (745:745:745)) + (PORT datab (521:521:521) (513:513:513)) + (PORT datac (1066:1066:1066) (1109:1109:1109)) + (PORT datad (1667:1667:1667) (1672:1672:1672)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_tbl_ed_set) + (DELAY + (ABSOLUTE + (PORT dataa (1562:1562:1562) (1583:1583:1583)) + (PORT datab (861:861:861) (893:893:893)) + (PORT datac (880:880:880) (922:922:922)) + (PORT datad (359:359:359) (400:400:400)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|decode_state_\|DFFE_instED) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1362:1362:1362)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1388:1388:1388) (1361:1361:1361)) + (PORT ena (716:716:716) (714:714:714)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|table_xx\~0) + (DELAY + (ABSOLUTE + (PORT dataa (261:261:261) (347:347:347)) + (PORT datad (354:354:354) (391:391:391)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal34\~0) + (DELAY + (ABSOLUTE + (PORT dataa (901:901:901) (939:939:939)) + (PORT datab (619:619:619) (603:603:603)) + (PORT datac (531:531:531) (533:533:533)) + (PORT datad (626:626:626) (654:654:654)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1084:1084:1084) (1080:1080:1080)) + (PORT datab (1577:1577:1577) (1560:1560:1560)) + (PORT datac (751:751:751) (724:724:724)) + (PORT datad (1197:1197:1197) (1234:1234:1234)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1228:1228:1228) (1280:1280:1280)) + (PORT datab (647:647:647) (666:666:666)) + (PORT datac (1027:1027:1027) (1023:1023:1023)) + (PORT datad (833:833:833) (859:859:859)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~4) + (DELAY + (ABSOLUTE + (PORT dataa (808:808:808) (813:813:813)) + (PORT datab (1161:1161:1161) (1189:1189:1189)) + (PORT datac (881:881:881) (883:883:883)) + (PORT datad (627:627:627) (643:643:643)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1222:1222:1222) (1274:1274:1274)) + (PORT datab (632:632:632) (668:668:668)) + (PORT datac (798:798:798) (791:791:791)) + (PORT datad (827:827:827) (829:829:829)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1526:1526:1526) (1495:1495:1495)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (878:878:878) (899:899:899)) + (PORT datad (1197:1197:1197) (1240:1240:1240)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~7) + (DELAY + (ABSOLUTE + (PORT dataa (181:181:181) (218:218:218)) + (PORT datab (183:183:183) (217:217:217)) + (PORT datac (554:554:554) (547:547:547)) + (PORT datad (159:159:159) (181:181:181)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~8) + (DELAY + (ABSOLUTE + (PORT dataa (768:768:768) (759:759:759)) + (PORT datab (1394:1394:1394) (1360:1360:1360)) + (PORT datac (844:844:844) (847:847:847)) + (PORT datad (628:628:628) (643:643:643)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1086:1086:1086) (1085:1085:1085)) + (PORT datab (857:857:857) (891:891:891)) + (PORT datac (582:582:582) (577:577:577)) + (PORT datad (1549:1549:1549) (1524:1524:1524)) + (IOPATH dataa combout (307:307:307) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1223:1223:1223) (1273:1273:1273)) + (PORT datab (186:186:186) (222:222:222)) + (PORT datac (156:156:156) (186:186:186)) + (PORT datad (1247:1247:1247) (1221:1221:1221)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~16) + (DELAY + (ABSOLUTE + (PORT dataa (799:799:799) (812:812:812)) + (PORT datab (1159:1159:1159) (1165:1165:1165)) + (PORT datac (1334:1334:1334) (1334:1334:1334)) + (PORT datad (178:178:178) (199:199:199)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~17) + (DELAY + (ABSOLUTE + (PORT dataa (901:901:901) (944:944:944)) + (PORT datab (1281:1281:1281) (1282:1282:1282)) + (PORT datac (184:184:184) (221:221:221)) + (PORT datad (605:605:605) (615:615:615)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1082:1082:1082) (1101:1101:1101)) + (PORT datab (221:221:221) (266:266:266)) + (PORT datac (803:803:803) (812:812:812)) + (PORT datad (164:164:164) (186:186:186)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~18) + (DELAY + (ABSOLUTE + (PORT dataa (322:322:322) (332:332:332)) + (PORT datab (1066:1066:1066) (1069:1069:1069)) + (PORT datac (175:175:175) (206:206:206)) + (PORT datad (549:549:549) (544:544:544)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1705:1705:1705) (1754:1754:1754)) + (PORT datab (1124:1124:1124) (1126:1126:1126)) + (PORT datac (1500:1500:1500) (1585:1585:1585)) + (PORT datad (1578:1578:1578) (1574:1574:1574)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_pc\~3) + (DELAY + (ABSOLUTE + (PORT dataa (617:617:617) (624:624:624)) + (PORT datab (1333:1333:1333) (1311:1311:1311)) + (PORT datac (788:788:788) (792:792:792)) + (PORT datad (588:588:588) (618:618:618)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_pc) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (217:217:217)) + (PORT datab (836:836:836) (838:838:838)) + (PORT datac (530:530:530) (530:530:530)) + (PORT datad (776:776:776) (774:774:774)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_72) + (DELAY + (ABSOLUTE + (PORT dataa (972:972:972) (955:955:955)) + (PORT datac (1019:1019:1019) (998:998:998)) + (PORT datad (825:825:825) (843:843:843)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (997:997:997) (983:983:983)) + (PORT datab (652:652:652) (677:677:677)) + (PORT datac (1252:1252:1252) (1254:1254:1254)) + (PORT datad (594:594:594) (612:612:612)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1342:1342:1342) (1359:1359:1359)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1154:1154:1154) (1149:1149:1149)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1342:1342:1342) (1359:1359:1359)) + (PORT asdata (485:485:485) (512:512:512)) + (PORT ena (1335:1335:1335) (1307:1307:1307)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (596:596:596) (613:613:613)) + (PORT datab (653:653:653) (675:675:675)) + (PORT datad (595:595:595) (610:610:610)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (998:998:998) (981:981:981)) + (PORT datab (347:347:347) (400:400:400)) + (PORT datad (158:158:158) (179:179:179)) + (IOPATH dataa combout (267:267:267) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (267:267:267)) + (PORT datab (612:612:612) (602:602:602)) + (PORT datac (1255:1255:1255) (1255:1255:1255)) + (PORT datad (158:158:158) (179:179:179)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1356:1356:1356)) + (PORT asdata (1265:1265:1265) (1294:1294:1294)) + (PORT ena (1132:1132:1132) (1119:1119:1119)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1356:1356:1356)) + (PORT asdata (1267:1267:1267) (1295:1295:1295)) + (PORT ena (744:744:744) (751:751:751)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~50) + (DELAY + (ABSOLUTE + (PORT dataa (653:653:653) (685:685:685)) + (PORT datab (221:221:221) (289:289:289)) + (PORT datad (212:212:212) (246:246:246)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1340:1340:1340) (1358:1358:1358)) + (PORT asdata (1080:1080:1080) (1075:1075:1075)) + (PORT ena (1109:1109:1109) (1079:1079:1079)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~53) + (DELAY + (ABSOLUTE + (PORT dataa (1083:1083:1083) (1111:1111:1111)) + (PORT datab (1070:1070:1070) (1044:1044:1044)) + (PORT datad (371:371:371) (394:394:394)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1340:1340:1340) (1358:1358:1358)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1376:1376:1376) (1350:1350:1350)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1340:1340:1340) (1358:1358:1358)) + (PORT asdata (856:856:856) (853:853:853)) + (PORT ena (1131:1131:1131) (1124:1124:1124)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~54) + (DELAY + (ABSOLUTE + (PORT dataa (646:646:646) (693:693:693)) + (PORT datab (221:221:221) (289:289:289)) + (PORT datad (646:646:646) (662:662:662)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1341:1341:1341) (1359:1359:1359)) + (PORT asdata (1330:1330:1330) (1315:1315:1315)) + (PORT ena (1132:1132:1132) (1121:1121:1121)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1341:1341:1341) (1359:1359:1359)) + (PORT asdata (1334:1334:1334) (1319:1319:1319)) + (PORT ena (1076:1076:1076) (1031:1031:1031)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~52) + (DELAY + (ABSOLUTE + (PORT dataa (634:634:634) (648:648:648)) + (PORT datab (237:237:237) (291:291:291)) + (PORT datad (198:198:198) (255:255:255)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1356:1356:1356)) + (PORT asdata (1104:1104:1104) (1091:1091:1091)) + (PORT ena (1322:1322:1322) (1264:1264:1264)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1356:1356:1356)) + (PORT asdata (1106:1106:1106) (1094:1094:1094)) + (PORT ena (1126:1126:1126) (1110:1110:1110)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (646:646:646) (686:686:686)) + (PORT datab (221:221:221) (291:291:291)) + (PORT datad (562:562:562) (570:570:570)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~55) + (DELAY + (ABSOLUTE + (PORT dataa (352:352:352) (358:358:358)) + (PORT datab (564:564:564) (563:563:563)) + (PORT datac (509:509:509) (491:491:491)) + (PORT datad (316:316:316) (316:316:316)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1357:1357:1357)) + (PORT asdata (848:848:848) (839:839:839)) + (PORT ena (716:716:716) (714:714:714)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[5\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1387:1387:1387) (1421:1421:1421)) + (PORT datab (1994:1994:1994) (1986:1986:1986)) + (PORT datad (1258:1258:1258) (1222:1222:1222)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1356:1356:1356)) + (PORT asdata (900:900:900) (896:896:896)) + (PORT ena (898:898:898) (891:891:891)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (544:544:544) (531:531:531)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1356:1356:1356)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1093:1093:1093) (1055:1055:1055)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~49) + (DELAY + (ABSOLUTE + (PORT dataa (624:624:624) (642:642:642)) + (PORT datab (632:632:632) (646:646:646)) + (PORT datad (198:198:198) (255:255:255)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~56) + (DELAY + (ABSOLUTE + (PORT dataa (754:754:754) (784:784:784)) + (PORT datab (899:899:899) (914:914:914)) + (PORT datac (494:494:494) (484:484:484)) + (PORT datad (318:318:318) (330:330:330)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~57) + (DELAY + (ABSOLUTE + (PORT dataa (606:606:606) (608:608:608)) + (PORT datab (849:849:849) (855:855:855)) + (PORT datac (1045:1045:1045) (1048:1048:1048)) + (PORT datad (518:518:518) (509:509:509)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[5\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (582:582:582) (593:593:593)) + (PORT datab (637:637:637) (641:641:641)) + (PORT datac (493:493:493) (488:488:488)) + (PORT datad (528:528:528) (523:523:523)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[5\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (326:326:326) (339:339:339)) + (PORT datab (587:587:587) (583:583:583)) + (PORT datac (194:194:194) (251:251:251)) + (PORT datad (629:629:629) (651:651:651)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sw1_\|db_down\[5\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (609:609:609) (648:648:648)) + (PORT datab (1280:1280:1280) (1238:1238:1238)) + (PORT datac (878:878:878) (884:884:884)) + (PORT datad (777:777:777) (778:778:778)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_36) + (DELAY + (ABSOLUTE + (PORT dataa (802:802:802) (826:826:826)) + (PORT datab (616:616:616) (614:614:614)) + (PORT datac (1047:1047:1047) (1036:1036:1036)) + (PORT datad (556:556:556) (549:549:549)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|flags_yf) + (DELAY + (ABSOLUTE + (PORT clk (1344:1344:1344) (1363:1363:1363)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1329:1329:1329) (1284:1284:1284)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[5\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (798:798:798) (788:788:788)) + (PORT datab (200:200:200) (239:239:239)) + (PORT datac (789:789:789) (794:794:794)) + (PORT datad (182:182:182) (205:205:205)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[5\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (187:187:187) (224:224:224)) + (PORT datab (557:557:557) (541:541:541)) + (PORT datac (1741:1741:1741) (1695:1695:1695)) + (PORT datad (355:355:355) (366:366:366)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[5\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (774:774:774) (755:755:755)) + (PORT datab (356:356:356) (381:381:381)) + (PORT datac (159:159:159) (190:190:190)) + (PORT datad (197:197:197) (226:226:226)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (697:697:697) (718:718:718)) + (PORT clk (1646:1646:1646) (1672:1672:1672)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3367:3367:3367) (3471:3471:3471)) + (PORT d[1] (1154:1154:1154) (1188:1188:1188)) + (PORT d[2] (1137:1137:1137) (1139:1139:1139)) + (PORT d[3] (3045:3045:3045) (3169:3169:3169)) + (PORT d[4] (3274:3274:3274) (3357:3357:3357)) + (PORT d[5] (3959:3959:3959) (3989:3989:3989)) + (PORT d[6] (1223:1223:1223) (1255:1255:1255)) + (PORT d[7] (2382:2382:2382) (2495:2495:2495)) + (PORT d[8] (3068:3068:3068) (3118:3118:3118)) + (PORT d[9] (1413:1413:1413) (1418:1418:1418)) + (PORT d[10] (3967:3967:3967) (4167:4167:4167)) + (PORT d[11] (3602:3602:3602) (3711:3711:3711)) + (PORT d[12] (1415:1415:1415) (1421:1421:1421)) + (PORT clk (1643:1643:1643) (1670:1670:1670)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1389:1389:1389) (1352:1352:1352)) + (PORT clk (1643:1643:1643) (1670:1670:1670)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1672:1672:1672)) + (PORT d[0] (2461:2461:2461) (2425:2425:2425)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1610:1610:1610) (1636:1636:1636)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (883:883:883)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (884:884:884)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (884:884:884)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (884:884:884)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1025:1025:1025) (1061:1061:1061)) + (PORT clk (1646:1646:1646) (1674:1674:1674)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2714:2714:2714) (2833:2833:2833)) + (PORT d[1] (912:912:912) (918:918:918)) + (PORT d[2] (1145:1145:1145) (1170:1170:1170)) + (PORT d[3] (3060:3060:3060) (3203:3203:3203)) + (PORT d[4] (958:958:958) (984:984:984)) + (PORT d[5] (1357:1357:1357) (1344:1344:1344)) + (PORT d[6] (1206:1206:1206) (1217:1217:1217)) + (PORT d[7] (2381:2381:2381) (2499:2499:2499)) + (PORT d[8] (3295:3295:3295) (3341:3341:3341)) + (PORT d[9] (1388:1388:1388) (1392:1392:1392)) + (PORT d[10] (3957:3957:3957) (4157:4157:4157)) + (PORT d[11] (3609:3609:3609) (3721:3721:3721)) + (PORT d[12] (1394:1394:1394) (1390:1390:1390)) + (PORT clk (1643:1643:1643) (1672:1672:1672)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1702:1702:1702) (1618:1618:1618)) + (PORT clk (1643:1643:1643) (1672:1672:1672)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1674:1674:1674)) + (PORT d[0] (2261:2261:2261) (2203:2203:2203)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1675:1675:1675)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1675:1675:1675)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1675:1675:1675)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1675:1675:1675)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1610:1610:1610) (1638:1638:1638)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (885:885:885)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (886:886:886)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (886:886:886)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (886:886:886)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (691:691:691) (709:709:709)) + (PORT clk (1646:1646:1646) (1672:1672:1672)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3383:3383:3383) (3485:3485:3485)) + (PORT d[1] (1174:1174:1174) (1206:1206:1206)) + (PORT d[2] (1440:1440:1440) (1465:1465:1465)) + (PORT d[3] (2777:2777:2777) (2897:2897:2897)) + (PORT d[4] (3259:3259:3259) (3338:3338:3338)) + (PORT d[5] (3709:3709:3709) (3737:3737:3737)) + (PORT d[6] (1467:1467:1467) (1490:1490:1490)) + (PORT d[7] (2109:2109:2109) (2216:2216:2216)) + (PORT d[8] (3057:3057:3057) (3110:3110:3110)) + (PORT d[9] (1653:1653:1653) (1667:1667:1667)) + (PORT d[10] (3687:3687:3687) (3872:3872:3872)) + (PORT d[11] (3331:3331:3331) (3427:3427:3427)) + (PORT d[12] (1628:1628:1628) (1631:1631:1631)) + (PORT clk (1643:1643:1643) (1670:1670:1670)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1401:1401:1401) (1362:1362:1362)) + (PORT clk (1643:1643:1643) (1670:1670:1670)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1672:1672:1672)) + (PORT d[0] (2812:2812:2812) (2760:2760:2760)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1610:1610:1610) (1636:1636:1636)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (883:883:883)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (884:884:884)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (884:884:884)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (884:884:884)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (659:659:659) (661:661:661)) + (PORT clk (1642:1642:1642) (1669:1669:1669)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3089:3089:3089) (3184:3184:3184)) + (PORT d[1] (1782:1782:1782) (1820:1820:1820)) + (PORT d[2] (1479:1479:1479) (1524:1524:1524)) + (PORT d[3] (2772:2772:2772) (2884:2884:2884)) + (PORT d[4] (2999:2999:2999) (3066:3066:3066)) + (PORT d[5] (3673:3673:3673) (3687:3687:3687)) + (PORT d[6] (1738:1738:1738) (1782:1782:1782)) + (PORT d[7] (2098:2098:2098) (2200:2200:2200)) + (PORT d[8] (2777:2777:2777) (2814:2814:2814)) + (PORT d[9] (1951:1951:1951) (1988:1988:1988)) + (PORT d[10] (3421:3421:3421) (3610:3610:3610)) + (PORT d[11] (3038:3038:3038) (3122:3122:3122)) + (PORT d[12] (1602:1602:1602) (1612:1612:1612)) + (PORT clk (1639:1639:1639) (1667:1667:1667)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1632:1632:1632) (1599:1599:1599)) + (PORT clk (1639:1639:1639) (1667:1667:1667)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1642:1642:1642) (1669:1669:1669)) + (PORT d[0] (2420:2420:2420) (2375:2375:2375)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1670:1670:1670)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1670:1670:1670)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1670:1670:1670)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1670:1670:1670)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1606:1606:1606) (1633:1633:1633)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (880:880:880)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (881:881:881)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (881:881:881)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (881:881:881)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (813:813:813) (789:789:789)) + (PORT datab (1328:1328:1328) (1370:1370:1370)) + (PORT datac (781:781:781) (746:746:746)) + (PORT datad (1380:1380:1380) (1422:1422:1422)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1137:1137:1137) (1120:1120:1120)) + (PORT datab (1152:1152:1152) (1146:1146:1146)) + (PORT datac (1659:1659:1659) (1721:1721:1721)) + (PORT datad (288:288:288) (292:292:292)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2549:2549:2549) (2643:2643:2643)) + (PORT d[1] (2054:2054:2054) (2081:2081:2081)) + (PORT d[2] (2251:2251:2251) (2292:2292:2292)) + (PORT d[3] (2401:2401:2401) (2478:2478:2478)) + (PORT d[4] (2464:2464:2464) (2498:2498:2498)) + (PORT d[5] (2709:2709:2709) (2719:2719:2719)) + (PORT d[6] (2722:2722:2722) (2755:2755:2755)) + (PORT d[7] (1827:1827:1827) (1922:1922:1922)) + (PORT d[8] (2214:2214:2214) (2221:2221:2221)) + (PORT d[9] (2898:2898:2898) (2911:2911:2911)) + (PORT d[10] (3740:3740:3740) (3937:3937:3937)) + (PORT d[11] (2881:2881:2881) (2953:2953:2953)) + (PORT d[12] (2543:2543:2543) (2540:2540:2540)) + (PORT clk (1653:1653:1653) (1681:1681:1681)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1681:1681:1681)) + (PORT d[0] (2522:2522:2522) (2511:2511:2511)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1682:1682:1682)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1620:1620:1620) (1647:1647:1647)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (891:891:891) (894:894:894)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (892:892:892) (895:895:895)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (892:892:892) (895:895:895)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (892:892:892) (895:895:895)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1838:1838:1838) (1846:1846:1846)) + (PORT d[1] (1475:1475:1475) (1504:1504:1504)) + (PORT d[2] (2220:2220:2220) (2273:2273:2273)) + (PORT d[3] (2323:2323:2323) (2385:2385:2385)) + (PORT d[4] (1148:1148:1148) (1166:1166:1166)) + (PORT d[5] (1436:1436:1436) (1453:1453:1453)) + (PORT d[6] (2446:2446:2446) (2402:2402:2402)) + (PORT d[7] (1717:1717:1717) (1764:1764:1764)) + (PORT d[8] (1469:1469:1469) (1487:1487:1487)) + (PORT d[9] (3101:3101:3101) (3220:3220:3220)) + (PORT d[10] (1147:1147:1147) (1161:1161:1161)) + (PORT d[11] (1117:1117:1117) (1098:1098:1098)) + (PORT d[12] (1541:1541:1541) (1516:1516:1516)) + (PORT clk (1643:1643:1643) (1672:1672:1672)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1672:1672:1672)) + (PORT d[0] (2090:2090:2090) (2147:2147:2147)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1610:1610:1610) (1638:1638:1638)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (885:885:885)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (886:886:886)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (886:886:886)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (886:886:886)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1081:1081:1081) (1058:1058:1058)) + (PORT clk (1643:1643:1643) (1670:1670:1670)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2807:2807:2807) (2890:2890:2890)) + (PORT d[1] (2817:2817:2817) (2853:2853:2853)) + (PORT d[2] (1770:1770:1770) (1821:1821:1821)) + (PORT d[3] (2179:2179:2179) (2282:2282:2282)) + (PORT d[4] (2734:2734:2734) (2792:2792:2792)) + (PORT d[5] (2969:2969:2969) (2997:2997:2997)) + (PORT d[6] (2182:2182:2182) (2206:2206:2206)) + (PORT d[7] (2088:2088:2088) (2154:2154:2154)) + (PORT d[8] (2504:2504:2504) (2536:2536:2536)) + (PORT d[9] (2430:2430:2430) (2455:2455:2455)) + (PORT d[10] (3405:3405:3405) (3580:3580:3580)) + (PORT d[11] (3044:3044:3044) (3110:3110:3110)) + (PORT d[12] (1921:1921:1921) (1941:1941:1941)) + (PORT clk (1640:1640:1640) (1668:1668:1668)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3110:3110:3110) (3051:3051:3051)) + (PORT clk (1640:1640:1640) (1668:1668:1668)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1670:1670:1670)) + (PORT d[0] (3046:3046:3046) (3010:3010:3010)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1671:1671:1671)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1671:1671:1671)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1671:1671:1671)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1671:1671:1671)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1602:1602:1602) (1600:1600:1600)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2509:2509:2509) (2636:2636:2636)) + (PORT clk (1610:1610:1610) (1607:1607:1607)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3934:3934:3934) (3806:3806:3806)) + (PORT d[1] (3924:3924:3924) (3876:3876:3876)) + (PORT d[2] (3841:3841:3841) (3729:3729:3729)) + (PORT d[3] (3897:3897:3897) (3829:3829:3829)) + (PORT d[4] (3844:3844:3844) (3829:3829:3829)) + (PORT d[5] (4051:4051:4051) (3940:3940:3940)) + (PORT d[6] (3918:3918:3918) (3802:3802:3802)) + (PORT d[7] (3744:3744:3744) (3706:3706:3706)) + (PORT d[8] (3923:3923:3923) (3827:3827:3827)) + (PORT d[9] (3945:3945:3945) (3902:3902:3902)) + (PORT d[10] (3961:3961:3961) (3914:3914:3914)) + (PORT d[11] (4035:4035:4035) (3953:3953:3953)) + (PORT d[12] (3722:3722:3722) (3640:3640:3640)) + (PORT clk (1607:1607:1607) (1604:1604:1604)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1610:1610:1610) (1607:1607:1607)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1611:1611:1611) (1608:1608:1608)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1611:1611:1611) (1608:1608:1608)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1611:1611:1611) (1608:1608:1608)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1611:1611:1611) (1608:1608:1608)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1154:1154:1154) (1149:1149:1149)) + (PORT clk (1652:1652:1652) (1679:1679:1679)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2646:2646:2646) (2730:2730:2730)) + (PORT d[1] (2514:2514:2514) (2540:2540:2540)) + (PORT d[2] (2308:2308:2308) (2365:2365:2365)) + (PORT d[3] (2162:2162:2162) (2268:2268:2268)) + (PORT d[4] (2731:2731:2731) (2773:2773:2773)) + (PORT d[5] (2724:2724:2724) (2748:2748:2748)) + (PORT d[6] (2743:2743:2743) (2773:2773:2773)) + (PORT d[7] (1813:1813:1813) (1893:1893:1893)) + (PORT d[8] (2227:2227:2227) (2247:2247:2247)) + (PORT d[9] (2202:2202:2202) (2241:2241:2241)) + (PORT d[10] (3346:3346:3346) (3495:3495:3495)) + (PORT d[11] (3035:3035:3035) (3103:3103:3103)) + (PORT d[12] (2412:2412:2412) (2398:2398:2398)) + (PORT clk (1649:1649:1649) (1677:1677:1677)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2278:2278:2278) (2220:2220:2220)) + (PORT clk (1649:1649:1649) (1677:1677:1677)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1679:1679:1679)) + (PORT d[0] (3043:3043:3043) (3059:3059:3059)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1680:1680:1680)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1680:1680:1680)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1680:1680:1680)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1680:1680:1680)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1611:1611:1611) (1609:1609:1609)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2770:2770:2770) (2890:2890:2890)) + (PORT clk (1619:1619:1619) (1616:1616:1616)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3794:3794:3794) (3664:3664:3664)) + (PORT d[1] (4043:4043:4043) (3963:3963:3963)) + (PORT d[2] (3890:3890:3890) (3812:3812:3812)) + (PORT d[3] (4037:4037:4037) (3944:3944:3944)) + (PORT d[4] (3904:3904:3904) (3829:3829:3829)) + (PORT d[5] (4355:4355:4355) (4250:4250:4250)) + (PORT d[6] (3891:3891:3891) (3811:3811:3811)) + (PORT d[7] (3898:3898:3898) (3808:3808:3808)) + (PORT d[8] (3923:3923:3923) (3831:3831:3831)) + (PORT d[9] (3962:3962:3962) (3919:3919:3919)) + (PORT d[10] (3782:3782:3782) (3675:3675:3675)) + (PORT d[11] (4016:4016:4016) (3894:3894:3894)) + (PORT d[12] (3914:3914:3914) (3820:3820:3820)) + (PORT clk (1616:1616:1616) (1613:1613:1613)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1619:1619:1619) (1616:1616:1616)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1620:1620:1620) (1617:1617:1617)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1620:1620:1620) (1617:1617:1617)) + (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1620:1620:1620) (1617:1617:1617)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1620:1620:1620) (1617:1617:1617)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1612:1612:1612) (1610:1610:1610)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Mux2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1172:1172:1172) (1208:1208:1208)) + (PORT datab (2039:2039:2039) (2094:2094:2094)) + (PORT datac (842:842:842) (831:831:831)) + (PORT datad (1017:1017:1017) (997:997:997)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Mux2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1580:1580:1580) (1660:1660:1660)) + (PORT datab (1303:1303:1303) (1280:1280:1280)) + (PORT datac (1287:1287:1287) (1301:1301:1301)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[5\]\~87) + (DELAY + (ABSOLUTE + (PORT dataa (1911:1911:1911) (1902:1902:1902)) + (PORT datab (182:182:182) (214:214:214)) + (PORT datac (157:157:157) (187:187:187)) + (PORT datad (1163:1163:1163) (1217:1217:1217)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[5\]\~68) + (DELAY + (ABSOLUTE + (PORT dataa (1296:1296:1296) (1300:1300:1300)) + (PORT datab (1156:1156:1156) (1192:1192:1192)) + (PORT datac (155:155:155) (184:184:184)) + (PORT datad (1311:1311:1311) (1304:1304:1304)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[5\]\~77) + (DELAY + (ABSOLUTE + (PORT datac (174:174:174) (206:206:206)) + (PORT datad (1302:1302:1302) (1313:1313:1313)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[5\]) + (DELAY + (ABSOLUTE + (PORT dataa (1559:1559:1559) (1514:1514:1514)) + (PORT datab (356:356:356) (358:358:358)) + (PORT datac (1262:1262:1262) (1242:1242:1242)) + (PORT datad (620:620:620) (640:640:640)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1348:1348:1348) (1359:1359:1359)) + (PORT asdata (607:607:607) (608:608:608)) + (PORT ena (744:744:744) (751:751:751)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[5\]\~14) + (DELAY + (ABSOLUTE + (PORT datab (580:580:580) (580:580:580)) + (PORT datac (502:502:502) (504:504:504)) + (PORT datad (216:216:216) (274:274:274)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[5\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (665:665:665) (694:694:694)) + (PORT datab (610:610:610) (631:631:631)) + (PORT datac (574:574:574) (592:592:592)) + (PORT datad (1547:1547:1547) (1517:1517:1517)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT asdata (867:867:867) (878:878:878)) + (PORT clrn (1389:1389:1389) (1362:1362:1362)) + (PORT ena (1532:1532:1532) (1497:1497:1497)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~8) + (DELAY + (ABSOLUTE + (PORT dataa (2340:2340:2340) (2424:2424:2424)) + (PORT datab (880:880:880) (890:890:890)) + (PORT datac (1102:1102:1102) (1114:1114:1114)) + (PORT datad (842:842:842) (862:862:862)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1223:1223:1223) (1295:1295:1295)) + (PORT datab (1165:1165:1165) (1157:1157:1157)) + (PORT datac (868:868:868) (913:913:913)) + (PORT datad (1222:1222:1222) (1259:1259:1259)) + (IOPATH dataa combout (307:307:307) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1660:1660:1660) (1673:1673:1673)) + (PORT datab (1119:1119:1119) (1106:1106:1106)) + (PORT datac (1577:1577:1577) (1593:1593:1593)) + (PORT datad (1142:1142:1142) (1168:1168:1168)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (184:184:184) (221:221:221)) + (PORT datab (1082:1082:1082) (1074:1074:1074)) + (PORT datac (173:173:173) (204:204:204)) + (PORT datad (1140:1140:1140) (1163:1163:1163)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla31pla33M4T1_3) + (DELAY + (ABSOLUTE + (PORT dataa (1096:1096:1096) (1114:1114:1114)) + (PORT datab (1899:1899:1899) (1962:1962:1962)) + (PORT datac (180:180:180) (216:216:216)) + (PORT datad (1544:1544:1544) (1560:1560:1560)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1403:1403:1403) (1391:1391:1391)) + (PORT datab (180:180:180) (212:212:212)) + (PORT datac (175:175:175) (206:206:206)) + (PORT datad (801:801:801) (784:784:784)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1615:1615:1615) (1622:1622:1622)) + (PORT datab (1532:1532:1532) (1572:1572:1572)) + (PORT datac (1138:1138:1138) (1132:1132:1132)) + (PORT datad (1039:1039:1039) (1037:1037:1037)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (308:308:308) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~7) + (DELAY + (ABSOLUTE + (PORT dataa (184:184:184) (221:221:221)) + (PORT datab (179:179:179) (212:212:212)) + (PORT datac (322:322:322) (332:332:332)) + (PORT datad (159:159:159) (181:181:181)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~66) + (DELAY + (ABSOLUTE + (PORT dataa (263:263:263) (347:347:347)) + (PORT datab (248:248:248) (323:323:323)) + (PORT datac (1237:1237:1237) (1255:1255:1255)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~80) + (DELAY + (ABSOLUTE + (PORT dataa (914:914:914) (953:953:953)) + (PORT datab (634:634:634) (659:659:659)) + (PORT datac (1092:1092:1092) (1110:1110:1110)) + (PORT datad (929:929:929) (985:985:985)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~81) + (DELAY + (ABSOLUTE + (PORT dataa (187:187:187) (225:225:225)) + (PORT datac (236:236:236) (313:313:313)) + (PORT datad (890:890:890) (911:911:911)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~82) + (DELAY + (ABSOLUTE + (PORT dataa (613:613:613) (614:614:614)) + (PORT datab (206:206:206) (243:243:243)) + (PORT datad (158:158:158) (179:179:179)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1342:1342:1342) (1359:1359:1359)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1376:1376:1376) (1357:1357:1357)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~84) + (DELAY + (ABSOLUTE + (PORT dataa (1366:1366:1366) (1361:1361:1361)) + (PORT datab (660:660:660) (706:706:706)) + (PORT datad (839:839:839) (884:884:884)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~83) + (DELAY + (ABSOLUTE + (PORT dataa (930:930:930) (1003:1003:1003)) + (PORT datab (1702:1702:1702) (1710:1710:1710)) + (PORT datac (1330:1330:1330) (1323:1323:1323)) + (PORT datad (614:614:614) (656:656:656)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~85) + (DELAY + (ABSOLUTE + (PORT dataa (185:185:185) (223:223:223)) + (PORT datab (184:184:184) (217:217:217)) + (PORT datad (167:167:167) (193:193:193)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1358:1358:1358)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1382:1382:1382) (1362:1362:1362)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (564:564:564) (566:566:566)) + (PORT datab (628:628:628) (662:662:662)) + (PORT datac (691:691:691) (682:682:682)) + (PORT datad (198:198:198) (255:255:255)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]\~78) + (DELAY + (ABSOLUTE + (PORT dataa (685:685:685) (726:726:726)) + (PORT datab (874:874:874) (962:962:962)) + (PORT datac (322:322:322) (327:327:327)) + (PORT datad (605:605:605) (637:637:637)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]\~79) + (DELAY + (ABSOLUTE + (PORT dataa (872:872:872) (907:907:907)) + (PORT datad (324:324:324) (337:337:337)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1357:1357:1357)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1381:1381:1381) (1360:1360:1360)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]\~76) + (DELAY + (ABSOLUTE + (PORT dataa (870:870:870) (910:910:910)) + (PORT datab (591:591:591) (589:589:589)) + (PORT datad (750:750:750) (738:738:738)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1357:1357:1357)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1381:1381:1381) (1360:1360:1360)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[0\]\~77) + (DELAY + (ABSOLUTE + (PORT dataa (870:870:870) (913:913:913)) + (PORT datab (593:593:593) (641:641:641)) + (PORT datad (345:345:345) (360:360:360)) + (IOPATH dataa combout (267:267:267) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1357:1357:1357)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1381:1381:1381) (1360:1360:1360)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (295:295:295)) + (PORT datab (956:956:956) (1007:1007:1007)) + (PORT datac (980:980:980) (962:962:962)) + (PORT datad (198:198:198) (255:255:255)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1224:1224:1224) (1269:1269:1269)) + (PORT datab (389:389:389) (449:449:449)) + (PORT datac (881:881:881) (920:920:920)) + (PORT datad (870:870:870) (906:906:906)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\~71) + (DELAY + (ABSOLUTE + (PORT dataa (212:212:212) (255:255:255)) + (PORT datab (660:660:660) (701:701:701)) + (PORT datac (874:874:874) (909:909:909)) + (PORT datad (565:565:565) (572:572:572)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~70) + (DELAY + (ABSOLUTE + (PORT dataa (1118:1118:1118) (1158:1158:1158)) + (PORT datad (912:912:912) (941:941:941)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~72) + (DELAY + (ABSOLUTE + (PORT dataa (272:272:272) (351:351:351)) + (PORT datab (618:618:618) (615:615:615)) + (PORT datac (528:528:528) (525:525:525)) + (PORT datad (564:564:564) (570:570:570)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (646:646:646) (722:722:722)) + (PORT datab (384:384:384) (442:442:442)) + (PORT datac (622:622:622) (664:664:664)) + (PORT datad (2026:2026:2026) (2060:2060:2060)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\~73) + (DELAY + (ABSOLUTE + (PORT dataa (274:274:274) (355:355:355)) + (PORT datab (202:202:202) (236:236:236)) + (PORT datac (853:853:853) (883:883:883)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~74) + (DELAY + (ABSOLUTE + (PORT dataa (185:185:185) (222:222:222)) + (PORT datab (183:183:183) (216:216:216)) + (PORT datad (399:399:399) (456:456:456)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1343:1343:1343) (1360:1360:1360)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1376:1376:1376) (1357:1357:1357)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\~2) + (DELAY + (ABSOLUTE + (PORT datab (649:649:649) (675:675:675)) + (PORT datac (2225:2225:2225) (2277:2277:2277)) + (PORT datad (1349:1349:1349) (1359:1359:1359)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~41) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (294:294:294)) + (PORT datab (182:182:182) (215:215:215)) + (PORT datac (156:156:156) (187:187:187)) + (PORT datad (1011:1011:1011) (971:971:971)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~89) + (DELAY + (ABSOLUTE + (PORT dataa (616:616:616) (652:652:652)) + (PORT datab (929:929:929) (981:981:981)) + (PORT datac (642:642:642) (693:693:693)) + (PORT datad (831:831:831) (922:922:922)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~90) + (DELAY + (ABSOLUTE + (PORT dataa (1471:1471:1471) (1502:1502:1502)) + (PORT datab (183:183:183) (216:216:216)) + (PORT datac (793:793:793) (775:775:775)) + (PORT datad (755:755:755) (803:803:803)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~91) + (DELAY + (ABSOLUTE + (PORT datab (962:962:962) (951:951:951)) + (PORT datad (852:852:852) (890:890:890)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1357:1357:1357)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1382:1382:1382) (1362:1362:1362)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~131) + (DELAY + (ABSOLUTE + (PORT dataa (621:621:621) (656:656:656)) + (PORT datab (758:758:758) (759:759:759)) + (PORT datad (401:401:401) (460:460:460)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr16\~3) + (DELAY + (ABSOLUTE + (PORT datac (873:873:873) (912:912:912)) + (PORT datad (888:888:888) (940:940:940)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~86) + (DELAY + (ABSOLUTE + (PORT dataa (867:867:867) (914:914:914)) + (PORT datab (216:216:216) (257:257:257)) + (PORT datac (157:157:157) (188:188:188)) + (PORT datad (604:604:604) (642:642:642)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~87) + (DELAY + (ABSOLUTE + (PORT dataa (776:776:776) (837:837:837)) + (PORT datab (762:762:762) (786:786:786)) + (PORT datac (327:327:327) (343:343:343)) + (PORT datad (836:836:836) (921:921:921)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~88) + (DELAY + (ABSOLUTE + (PORT dataa (823:823:823) (813:813:813)) + (PORT datad (854:854:854) (890:890:890)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1357:1357:1357)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1382:1382:1382) (1362:1362:1362)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~43) + (DELAY + (ABSOLUTE + (PORT dataa (1278:1278:1278) (1365:1365:1365)) + (PORT datab (221:221:221) (290:290:290)) + (PORT datac (194:194:194) (260:260:260)) + (PORT datad (554:554:554) (555:555:555)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~44) + (DELAY + (ABSOLUTE + (PORT dataa (310:310:310) (330:330:330)) + (PORT datab (773:773:773) (751:751:751)) + (PORT datac (2667:2667:2667) (2798:2798:2798)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (903:903:903) (908:908:908)) + (PORT clk (1638:1638:1638) (1665:1665:1665)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1640:1640:1640) (1664:1664:1664)) + (PORT d[1] (4181:4181:4181) (4192:4192:4192)) + (PORT d[2] (2446:2446:2446) (2547:2547:2547)) + (PORT d[3] (2682:2682:2682) (2771:2771:2771)) + (PORT d[4] (3872:3872:3872) (3944:3944:3944)) + (PORT d[5] (1892:1892:1892) (1908:1908:1908)) + (PORT d[6] (1773:1773:1773) (1798:1798:1798)) + (PORT d[7] (1990:1990:1990) (2061:2061:2061)) + (PORT d[8] (2574:2574:2574) (2639:2639:2639)) + (PORT d[9] (2589:2589:2589) (2696:2696:2696)) + (PORT d[10] (2315:2315:2315) (2418:2418:2418)) + (PORT d[11] (2483:2483:2483) (2516:2516:2516)) + (PORT d[12] (3389:3389:3389) (3419:3419:3419)) + (PORT clk (1635:1635:1635) (1663:1663:1663)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1612:1612:1612) (1572:1572:1572)) + (PORT clk (1635:1635:1635) (1663:1663:1663)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1665:1665:1665)) + (PORT d[0] (2078:2078:2078) (2025:2025:2025)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1602:1602:1602) (1629:1629:1629)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (876:876:876)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (877:877:877)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (877:877:877)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (877:877:877)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (922:922:922) (930:930:930)) + (PORT clk (1638:1638:1638) (1665:1665:1665)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3154:3154:3154) (3292:3292:3292)) + (PORT d[1] (4180:4180:4180) (4191:4191:4191)) + (PORT d[2] (2465:2465:2465) (2567:2567:2567)) + (PORT d[3] (2329:2329:2329) (2396:2396:2396)) + (PORT d[4] (3836:3836:3836) (3894:3894:3894)) + (PORT d[5] (1925:1925:1925) (1950:1950:1950)) + (PORT d[6] (3065:3065:3065) (3113:3113:3113)) + (PORT d[7] (3353:3353:3353) (3429:3429:3429)) + (PORT d[8] (2917:2917:2917) (3036:3036:3036)) + (PORT d[9] (2301:2301:2301) (2398:2398:2398)) + (PORT d[10] (2070:2070:2070) (2173:2173:2173)) + (PORT d[11] (2482:2482:2482) (2515:2515:2515)) + (PORT d[12] (3130:3130:3130) (3167:3167:3167)) + (PORT clk (1635:1635:1635) (1663:1663:1663)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1665:1665:1665) (1627:1627:1627)) + (PORT clk (1635:1635:1635) (1663:1663:1663)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1665:1665:1665)) + (PORT d[0] (2357:2357:2357) (2348:2348:2348)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1602:1602:1602) (1629:1629:1629)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (876:876:876)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (877:877:877)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (877:877:877)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (877:877:877)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (668:668:668) (667:667:667)) + (PORT clk (1638:1638:1638) (1666:1666:1666)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1368:1368:1368) (1391:1391:1391)) + (PORT d[1] (2120:2120:2120) (2147:2147:2147)) + (PORT d[2] (1751:1751:1751) (1808:1808:1808)) + (PORT d[3] (1483:1483:1483) (1528:1528:1528)) + (PORT d[4] (3828:3828:3828) (3902:3902:3902)) + (PORT d[5] (1577:1577:1577) (1583:1583:1583)) + (PORT d[6] (1753:1753:1753) (1766:1766:1766)) + (PORT d[7] (1984:1984:1984) (2048:2048:2048)) + (PORT d[8] (2563:2563:2563) (2642:2642:2642)) + (PORT d[9] (2597:2597:2597) (2707:2707:2707)) + (PORT d[10] (2330:2330:2330) (2450:2450:2450)) + (PORT d[11] (2120:2120:2120) (2149:2149:2149)) + (PORT d[12] (3406:3406:3406) (3452:3452:3452)) + (PORT clk (1635:1635:1635) (1664:1664:1664)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1351:1351:1351) (1296:1296:1296)) + (PORT clk (1635:1635:1635) (1664:1664:1664)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1666:1666:1666)) + (PORT d[0] (2038:2038:2038) (1966:1966:1966)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1667:1667:1667)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1667:1667:1667)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1667:1667:1667)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1667:1667:1667)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1602:1602:1602) (1630:1630:1630)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (877:877:877)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (878:878:878)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (878:878:878)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (878:878:878)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (961:961:961) (988:988:988)) + (PORT clk (1638:1638:1638) (1664:1664:1664)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3174:3174:3174) (3312:3312:3312)) + (PORT d[1] (4176:4176:4176) (4186:4186:4186)) + (PORT d[2] (2440:2440:2440) (2539:2539:2539)) + (PORT d[3] (2383:2383:2383) (2462:2462:2462)) + (PORT d[4] (3548:3548:3548) (3611:3611:3611)) + (PORT d[5] (1930:1930:1930) (1959:1959:1959)) + (PORT d[6] (3037:3037:3037) (3079:3079:3079)) + (PORT d[7] (3109:3109:3109) (3188:3188:3188)) + (PORT d[8] (3155:3155:3155) (3266:3266:3266)) + (PORT d[9] (2325:2325:2325) (2426:2426:2426)) + (PORT d[10] (2051:2051:2051) (2156:2156:2156)) + (PORT d[11] (2475:2475:2475) (2512:2512:2512)) + (PORT d[12] (3129:3129:3129) (3166:3166:3166)) + (PORT clk (1635:1635:1635) (1662:1662:1662)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1853:1853:1853) (1825:1825:1825)) + (PORT clk (1635:1635:1635) (1662:1662:1662)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1664:1664:1664)) + (PORT d[0] (2298:2298:2298) (2259:2259:2259)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1665:1665:1665)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1665:1665:1665)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1665:1665:1665)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1665:1665:1665)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1602:1602:1602) (1628:1628:1628)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (875:875:875)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (876:876:876)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (876:876:876)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (876:876:876)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (877:877:877) (871:871:871)) + (PORT datab (1172:1172:1172) (1188:1188:1188)) + (PORT datac (1409:1409:1409) (1470:1470:1470)) + (PORT datad (1259:1259:1259) (1225:1225:1225)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (285:285:285)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1078:1078:1078) (1072:1072:1072)) + (PORT datab (1101:1101:1101) (1083:1083:1083)) + (PORT datac (1680:1680:1680) (1633:1633:1633)) + (PORT datad (159:159:159) (178:178:178)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2739:2739:2739) (2862:2862:2862)) + (PORT d[1] (914:914:914) (926:926:926)) + (PORT d[2] (2719:2719:2719) (2853:2853:2853)) + (PORT d[3] (923:923:923) (917:917:917)) + (PORT d[4] (908:908:908) (913:913:913)) + (PORT d[5] (1121:1121:1121) (1125:1125:1125)) + (PORT d[6] (926:926:926) (937:937:937)) + (PORT d[7] (2646:2646:2646) (2769:2769:2769)) + (PORT d[8] (3306:3306:3306) (3368:3368:3368)) + (PORT d[9] (1088:1088:1088) (1073:1073:1073)) + (PORT d[10] (4239:4239:4239) (4440:4440:4440)) + (PORT d[11] (1387:1387:1387) (1381:1381:1381)) + (PORT d[12] (2376:2376:2376) (2380:2380:2380)) + (PORT clk (1642:1642:1642) (1670:1670:1670)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1642:1642:1642) (1670:1670:1670)) + (PORT d[0] (1146:1146:1146) (1080:1080:1080)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1671:1671:1671)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1636:1636:1636)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (883:883:883)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (884:884:884)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (884:884:884)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (884:884:884)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1457:1457:1457) (1476:1476:1476)) + (PORT clk (1643:1643:1643) (1671:1671:1671)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2584:2584:2584) (2602:2602:2602)) + (PORT d[1] (3183:3183:3183) (3172:3172:3172)) + (PORT d[2] (2410:2410:2410) (2495:2495:2495)) + (PORT d[3] (1973:1973:1973) (2019:2019:2019)) + (PORT d[4] (2497:2497:2497) (2551:2551:2551)) + (PORT d[5] (2522:2522:2522) (2561:2561:2561)) + (PORT d[6] (2756:2756:2756) (2777:2777:2777)) + (PORT d[7] (2218:2218:2218) (2264:2264:2264)) + (PORT d[8] (2423:2423:2423) (2446:2446:2446)) + (PORT d[9] (2524:2524:2524) (2620:2620:2620)) + (PORT d[10] (2875:2875:2875) (3075:3075:3075)) + (PORT d[11] (2136:2136:2136) (2161:2161:2161)) + (PORT d[12] (2789:2789:2789) (2812:2812:2812)) + (PORT clk (1640:1640:1640) (1669:1669:1669)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2605:2605:2605) (2594:2594:2594)) + (PORT clk (1640:1640:1640) (1669:1669:1669)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1671:1671:1671)) + (PORT d[0] (4445:4445:4445) (4479:4479:4479)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1672:1672:1672)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1672:1672:1672)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1672:1672:1672)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1672:1672:1672)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1602:1602:1602) (1601:1601:1601)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (934:934:934) (947:947:947)) + (PORT clk (1610:1610:1610) (1608:1608:1608)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3866:3866:3866) (3755:3755:3755)) + (PORT d[1] (3993:3993:3993) (3969:3969:3969)) + (PORT d[2] (3861:3861:3861) (3826:3826:3826)) + (PORT d[3] (3911:3911:3911) (3856:3856:3856)) + (PORT d[4] (3831:3831:3831) (3824:3824:3824)) + (PORT d[5] (4028:4028:4028) (3884:3884:3884)) + (PORT d[6] (3851:3851:3851) (3742:3742:3742)) + (PORT d[7] (3831:3831:3831) (3775:3775:3775)) + (PORT d[8] (3962:3962:3962) (3951:3951:3951)) + (PORT d[9] (3790:3790:3790) (3766:3766:3766)) + (PORT d[10] (3986:3986:3986) (3862:3862:3862)) + (PORT d[11] (3945:3945:3945) (3809:3809:3809)) + (PORT d[12] (3868:3868:3868) (3782:3782:3782)) + (PORT clk (1607:1607:1607) (1605:1605:1605)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1610:1610:1610) (1608:1608:1608)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1611:1611:1611) (1609:1609:1609)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1611:1611:1611) (1609:1609:1609)) + (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1611:1611:1611) (1609:1609:1609)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1611:1611:1611) (1609:1609:1609)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1603:1603:1603) (1602:1602:1602)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1231:1231:1231) (1251:1251:1251)) + (PORT clk (1636:1636:1636) (1663:1663:1663)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2852:2852:2852) (2987:2987:2987)) + (PORT d[1] (3713:3713:3713) (3725:3725:3725)) + (PORT d[2] (2189:2189:2189) (2281:2281:2281)) + (PORT d[3] (2348:2348:2348) (2424:2424:2424)) + (PORT d[4] (3804:3804:3804) (3853:3853:3853)) + (PORT d[5] (2168:2168:2168) (2192:2192:2192)) + (PORT d[6] (3024:3024:3024) (3041:3041:3041)) + (PORT d[7] (3070:3070:3070) (3148:3148:3148)) + (PORT d[8] (2293:2293:2293) (2339:2339:2339)) + (PORT d[9] (2284:2284:2284) (2366:2366:2366)) + (PORT d[10] (2474:2474:2474) (2602:2602:2602)) + (PORT d[11] (2190:2190:2190) (2217:2217:2217)) + (PORT d[12] (3090:3090:3090) (3108:3108:3108)) + (PORT clk (1633:1633:1633) (1661:1661:1661)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1863:1863:1863) (1802:1802:1802)) + (PORT clk (1633:1633:1633) (1661:1661:1661)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1636:1636:1636) (1663:1663:1663)) + (PORT d[0] (5027:5027:5027) (5000:5000:5000)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1637:1637:1637) (1664:1664:1664)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1637:1637:1637) (1664:1664:1664)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1637:1637:1637) (1664:1664:1664)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1637:1637:1637) (1664:1664:1664)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1595:1595:1595) (1593:1593:1593)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1930:1930:1930) (2052:2052:2052)) + (PORT clk (1603:1603:1603) (1600:1600:1600)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3921:3921:3921) (3883:3883:3883)) + (PORT d[1] (3976:3976:3976) (3952:3952:3952)) + (PORT d[2] (3859:3859:3859) (3812:3812:3812)) + (PORT d[3] (3955:3955:3955) (3929:3929:3929)) + (PORT d[4] (3882:3882:3882) (3908:3908:3908)) + (PORT d[5] (4084:4084:4084) (4028:4028:4028)) + (PORT d[6] (3842:3842:3842) (3751:3751:3751)) + (PORT d[7] (3798:3798:3798) (3754:3754:3754)) + (PORT d[8] (4048:4048:4048) (3913:3913:3913)) + (PORT d[9] (3866:3866:3866) (3795:3795:3795)) + (PORT d[10] (3939:3939:3939) (3877:3877:3877)) + (PORT d[11] (4045:4045:4045) (3958:3958:3958)) + (PORT d[12] (3935:3935:3935) (3866:3866:3866)) + (PORT clk (1600:1600:1600) (1597:1597:1597)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1603:1603:1603) (1600:1600:1600)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1604:1604:1604) (1601:1601:1601)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1604:1604:1604) (1601:1601:1601)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1604:1604:1604) (1601:1601:1601)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1604:1604:1604) (1601:1601:1601)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1117:1117:1117) (1115:1115:1115)) + (PORT datab (634:634:634) (639:639:639)) + (PORT datac (1592:1592:1592) (1572:1572:1572)) + (PORT datad (1097:1097:1097) (1108:1108:1108)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2381:2381:2381) (2421:2421:2421)) + (PORT d[1] (3169:3169:3169) (3137:3137:3137)) + (PORT d[2] (2119:2119:2119) (2184:2184:2184)) + (PORT d[3] (2261:2261:2261) (2311:2311:2311)) + (PORT d[4] (2484:2484:2484) (2525:2525:2525)) + (PORT d[5] (2480:2480:2480) (2509:2509:2509)) + (PORT d[6] (3010:3010:3010) (3034:3034:3034)) + (PORT d[7] (1973:1973:1973) (2019:2019:2019)) + (PORT d[8] (2424:2424:2424) (2438:2438:2438)) + (PORT d[9] (2786:2786:2786) (2882:2882:2882)) + (PORT d[10] (3250:3250:3250) (3458:3458:3458)) + (PORT d[11] (2437:2437:2437) (2459:2459:2459)) + (PORT d[12] (2523:2523:2523) (2544:2544:2544)) + (PORT clk (1645:1645:1645) (1673:1673:1673)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1673:1673:1673)) + (PORT d[0] (3588:3588:3588) (3641:3641:3641)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1674:1674:1674)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1612:1612:1612) (1639:1639:1639)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (883:883:883) (886:886:886)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (884:884:884) (887:887:887)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (884:884:884) (887:887:887)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (884:884:884) (887:887:887)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1301:1301:1301) (1272:1272:1272)) + (PORT datab (1625:1625:1625) (1606:1606:1606)) + (PORT datac (158:158:158) (189:189:189)) + (PORT datad (1615:1615:1615) (1629:1629:1629)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (285:285:285)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~83) + (DELAY + (ABSOLUTE + (PORT dataa (185:185:185) (222:222:222)) + (PORT datab (2883:2883:2883) (2923:2923:2923)) + (PORT datac (1707:1707:1707) (1786:1786:1786)) + (PORT datad (157:157:157) (178:178:178)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~45) + (DELAY + (ABSOLUTE + (PORT dataa (1074:1074:1074) (1095:1095:1095)) + (PORT datab (975:975:975) (971:971:971)) + (PORT datac (162:162:162) (196:196:196)) + (PORT datad (1496:1496:1496) (1476:1476:1476)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (1551:1551:1551) (1527:1527:1527)) + (PORT datab (1537:1537:1537) (1514:1514:1514)) + (PORT datac (156:156:156) (186:186:186)) + (PORT datad (1627:1627:1627) (1645:1645:1645)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[0\]) + (DELAY + (ABSOLUTE + (PORT dataa (1316:1316:1316) (1309:1309:1309)) + (PORT datab (2482:2482:2482) (2511:2511:2511)) + (PORT datac (316:316:316) (326:326:326)) + (PORT datad (336:336:336) (352:352:352)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1348:1348:1348) (1359:1359:1359)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (744:744:744) (751:751:751)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[0\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (562:562:562) (590:590:590)) + (PORT datab (331:331:331) (358:358:358)) + (PORT datac (315:315:315) (333:333:333)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[0\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1303:1303:1303) (1280:1280:1280)) + (PORT datab (604:604:604) (598:598:598)) + (PORT datac (175:175:175) (205:205:205)) + (PORT datad (158:158:158) (179:179:179)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1362:1362:1362)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1388:1388:1388) (1361:1361:1361)) + (PORT ena (1565:1565:1565) (1541:1541:1541)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal3\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1575:1575:1575) (1659:1659:1659)) + (PORT datab (1006:1006:1006) (1031:1031:1031)) + (PORT datac (562:562:562) (582:582:582)) + (PORT datad (1020:1020:1020) (1000:1000:1000)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal43\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1207:1207:1207) (1238:1238:1238)) + (PORT datab (825:825:825) (827:827:827)) + (PORT datac (676:676:676) (749:749:749)) + (PORT datad (1004:1004:1004) (995:995:995)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|test1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (767:767:767) (757:757:757)) + (PORT datab (180:180:180) (211:211:211)) + (PORT datac (168:168:168) (207:207:207)) + (PORT datad (178:178:178) (200:200:200)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|test1\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1021:1021:1021) (1083:1083:1083)) + (PORT datab (990:990:990) (1011:1011:1011)) + (PORT datac (583:583:583) (621:621:621)) + (PORT datad (834:834:834) (835:835:835)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|interrupts_\|in_nmi_ALTERA_SYNTHESIZED) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1362:1362:1362)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1388:1388:1388) (1361:1361:1361)) + (PORT ena (877:877:877) (871:871:871)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|clk_delay_\|SYNTHESIZED_WIRE_4) + (DELAY + (ABSOLUTE + (PORT dataa (584:584:584) (620:620:620)) + (PORT datab (1345:1345:1345) (1417:1417:1417)) + (PORT datac (1112:1112:1112) (1163:1163:1163)) + (PORT datad (787:787:787) (812:812:812)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|clk_delay_\|SYNTHESIZED_WIRE_7) + (DELAY + (ABSOLUTE + (PORT clk (1346:1346:1346) (1363:1363:1363)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1389:1389:1389) (1362:1362:1362)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|clk_delay_\|hold_clk_iorq) + (DELAY + (ABSOLUTE + (PORT dataa (1044:1044:1044) (1054:1054:1054)) + (PORT datab (1186:1186:1186) (1181:1181:1181)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_T4_ff) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1354:1354:1354)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1380:1380:1380) (1352:1352:1352)) + (PORT ena (1325:1325:1325) (1300:1300:1300)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_eval_cond\~0) + (DELAY + (ABSOLUTE + (PORT datac (1006:1006:1006) (1071:1071:1071)) + (PORT datad (1281:1281:1281) (1282:1282:1282)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~27) + (DELAY + (ABSOLUTE + (PORT dataa (928:928:928) (957:957:957)) + (PORT datab (1087:1087:1087) (1071:1071:1071)) + (PORT datac (578:578:578) (604:604:604)) + (PORT datad (576:576:576) (578:578:578)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~26) + (DELAY + (ABSOLUTE + (PORT datab (1031:1031:1031) (1086:1086:1086)) + (PORT datac (1726:1726:1726) (1734:1734:1734)) + (PORT datad (1684:1684:1684) (1742:1742:1742)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~28) + (DELAY + (ABSOLUTE + (PORT dataa (184:184:184) (220:220:220)) + (PORT datab (182:182:182) (214:214:214)) + (PORT datac (175:175:175) (205:205:205)) + (PORT datad (1338:1338:1338) (1334:1334:1334)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~6) + (DELAY + (ABSOLUTE + (PORT dataa (876:876:876) (899:899:899)) + (PORT datab (622:622:622) (623:623:623)) + (PORT datac (183:183:183) (220:220:220)) + (PORT datad (1169:1169:1169) (1169:1169:1169)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~7) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (220:220:220)) + (PORT datab (859:859:859) (891:891:891)) + (PORT datac (1036:1036:1036) (1062:1062:1062)) + (PORT datad (1265:1265:1265) (1261:1261:1261)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~8) + (DELAY + (ABSOLUTE + (PORT dataa (805:805:805) (797:797:797)) + (PORT datab (1002:1002:1002) (1036:1036:1036)) + (PORT datac (846:846:846) (870:870:870)) + (PORT datad (619:619:619) (648:648:648)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~9) + (DELAY + (ABSOLUTE + (PORT dataa (853:853:853) (873:873:873)) + (PORT datab (1352:1352:1352) (1373:1373:1373)) + (PORT datac (1010:1010:1010) (1054:1054:1054)) + (PORT datad (810:810:810) (798:798:798)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~10) + (DELAY + (ABSOLUTE + (PORT dataa (600:600:600) (596:596:596)) + (PORT datab (1234:1234:1234) (1207:1207:1207)) + (PORT datac (547:547:547) (545:545:545)) + (PORT datad (2215:2215:2215) (2215:2215:2215)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~12) + (DELAY + (ABSOLUTE + (PORT dataa (184:184:184) (222:222:222)) + (PORT datab (188:188:188) (226:226:226)) + (PORT datac (512:512:512) (499:499:499)) + (PORT datad (597:597:597) (616:616:616)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~15) + (DELAY + (ABSOLUTE + (PORT dataa (611:611:611) (607:607:607)) + (PORT datab (1792:1792:1792) (1816:1816:1816)) + (PORT datac (1360:1360:1360) (1420:1420:1420)) + (PORT datad (316:316:316) (334:334:334)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~13) + (DELAY + (ABSOLUTE + (PORT dataa (351:351:351) (358:358:358)) + (PORT datab (181:181:181) (213:213:213)) + (PORT datad (157:157:157) (178:178:178)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~41) + (DELAY + (ABSOLUTE + (PORT datab (199:199:199) (231:231:231)) + (PORT datac (1006:1006:1006) (981:981:981)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1207:1207:1207) (1261:1261:1261)) + (PORT datab (1114:1114:1114) (1210:1210:1210)) + (PORT datac (751:751:751) (759:759:759)) + (PORT datad (706:706:706) (730:730:730)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1135:1135:1135) (1195:1195:1195)) + (PORT datab (885:885:885) (905:905:905)) + (PORT datac (777:777:777) (783:783:783)) + (PORT datad (549:549:549) (535:535:535)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|ena_M) + (DELAY + (ABSOLUTE + (PORT datab (1065:1065:1065) (1105:1105:1105)) + (PORT datad (826:826:826) (883:883:883)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_T1_ff) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1354:1354:1354)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1380:1380:1380) (1352:1352:1352)) + (PORT ena (1325:1325:1325) (1300:1300:1300)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_13) + (DELAY + (ABSOLUTE + (PORT datab (248:248:248) (320:320:320)) + (PORT datac (1437:1437:1437) (1490:1490:1490)) + (PORT datad (829:829:829) (885:885:885)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_T2_ff) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1354:1354:1354)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1380:1380:1380) (1352:1352:1352)) + (PORT ena (1325:1325:1325) (1300:1300:1300)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_14) + (DELAY + (ABSOLUTE + (PORT datab (247:247:247) (322:322:322)) + (PORT datac (1438:1438:1438) (1490:1490:1490)) + (PORT datad (829:829:829) (884:884:884)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_T3_ff) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1354:1354:1354)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1380:1380:1380) (1352:1352:1352)) + (PORT ena (1325:1325:1325) (1300:1300:1300)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_1M1T3_3) + (DELAY + (ABSOLUTE + (PORT datac (1110:1110:1110) (1160:1160:1160)) + (PORT datad (1498:1498:1498) (1504:1504:1504)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_66_oe\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1325:1325:1325) (1322:1322:1322)) + (PORT datab (594:594:594) (618:618:618)) + (PORT datac (1198:1198:1198) (1230:1230:1230)) + (PORT datad (1531:1531:1531) (1615:1615:1615)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|interrupts_\|im1) + (DELAY + (ABSOLUTE + (PORT clk (1363:1363:1363) (1384:1384:1384)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1388:1388:1388) (1362:1362:1362)) + (PORT ena (1359:1359:1359) (1330:1330:1330)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_ff_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (263:263:263) (343:343:343)) + (PORT datab (832:832:832) (853:853:853)) + (PORT datac (773:773:773) (809:809:809)) + (PORT datad (1035:1035:1035) (1050:1050:1050)) + (IOPATH dataa combout (307:307:307) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_ff_oe\~1) + (DELAY + (ABSOLUTE + (PORT dataa (603:603:603) (614:614:614)) + (PORT datab (1075:1075:1075) (1088:1088:1088)) + (PORT datac (405:405:405) (476:476:476)) + (PORT datad (159:159:159) (181:181:181)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_zero_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1451:1451:1451) (1415:1415:1415)) + (PORT datab (1152:1152:1152) (1196:1196:1196)) + (PORT datac (1320:1320:1320) (1344:1344:1344)) + (PORT datad (833:833:833) (828:828:828)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (191:191:191) (232:232:232)) + (PORT datab (186:186:186) (224:224:224)) + (PORT datac (1279:1279:1279) (1249:1249:1249)) + (PORT datad (644:644:644) (695:695:695)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[6\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (523:523:523) (524:524:524)) + (PORT datac (1229:1229:1229) (1192:1192:1192)) + (PORT datad (550:550:550) (542:542:542)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (882:882:882) (890:890:890)) + (PORT clk (1630:1630:1630) (1658:1658:1658)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1380:1380:1380) (1391:1391:1391)) + (PORT d[1] (1728:1728:1728) (1746:1746:1746)) + (PORT d[2] (2046:2046:2046) (2120:2120:2120)) + (PORT d[3] (1735:1735:1735) (1772:1772:1772)) + (PORT d[4] (2139:2139:2139) (2140:2140:2140)) + (PORT d[5] (1346:1346:1346) (1349:1349:1349)) + (PORT d[6] (1326:1326:1326) (1323:1323:1323)) + (PORT d[7] (1414:1414:1414) (1457:1457:1457)) + (PORT d[8] (2283:2283:2283) (2366:2366:2366)) + (PORT d[9] (3183:3183:3183) (3319:3319:3319)) + (PORT d[10] (1198:1198:1198) (1208:1208:1208)) + (PORT d[11] (1554:1554:1554) (1550:1550:1550)) + (PORT d[12] (2215:2215:2215) (2196:2196:2196)) + (PORT clk (1627:1627:1627) (1656:1656:1656)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1382:1382:1382) (1337:1337:1337)) + (PORT clk (1627:1627:1627) (1656:1656:1656)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1630:1630:1630) (1658:1658:1658)) + (PORT d[0] (1592:1592:1592) (1556:1556:1556)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1631:1631:1631) (1659:1659:1659)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1631:1631:1631) (1659:1659:1659)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1631:1631:1631) (1659:1659:1659)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1631:1631:1631) (1659:1659:1659)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1594:1594:1594) (1622:1622:1622)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (865:865:865) (869:869:869)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (866:866:866) (870:870:870)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (866:866:866) (870:870:870)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (866:866:866) (870:870:870)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (957:957:957) (958:958:958)) + (PORT clk (1626:1626:1626) (1655:1655:1655)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1133:1133:1133) (1144:1144:1144)) + (PORT d[1] (1712:1712:1712) (1730:1730:1730)) + (PORT d[2] (1850:1850:1850) (1930:1930:1930)) + (PORT d[3] (1723:1723:1723) (1769:1769:1769)) + (PORT d[4] (2182:2182:2182) (2188:2188:2188)) + (PORT d[5] (1317:1317:1317) (1309:1309:1309)) + (PORT d[6] (1322:1322:1322) (1316:1316:1316)) + (PORT d[7] (1441:1441:1441) (1487:1487:1487)) + (PORT d[8] (2341:2341:2341) (2427:2427:2427)) + (PORT d[9] (3204:3204:3204) (3343:3343:3343)) + (PORT d[10] (1476:1476:1476) (1514:1514:1514)) + (PORT d[11] (1291:1291:1291) (1287:1287:1287)) + (PORT d[12] (2245:2245:2245) (2231:2231:2231)) + (PORT clk (1623:1623:1623) (1653:1653:1653)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1335:1335:1335) (1295:1295:1295)) + (PORT clk (1623:1623:1623) (1653:1653:1653)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1626:1626:1626) (1655:1655:1655)) + (PORT d[0] (1602:1602:1602) (1547:1547:1547)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1627:1627:1627) (1656:1656:1656)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1627:1627:1627) (1656:1656:1656)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1627:1627:1627) (1656:1656:1656)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1627:1627:1627) (1656:1656:1656)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1590:1590:1590) (1619:1619:1619)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (861:861:861) (866:866:866)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (862:862:862) (867:867:867)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (862:862:862) (867:867:867)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (862:862:862) (867:867:867)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (873:873:873) (864:864:864)) + (PORT clk (1635:1635:1635) (1662:1662:1662)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1112:1112:1112) (1110:1110:1110)) + (PORT d[1] (1710:1710:1710) (1741:1741:1741)) + (PORT d[2] (2967:2967:2967) (3087:3087:3087)) + (PORT d[3] (1456:1456:1456) (1484:1484:1484)) + (PORT d[4] (1845:1845:1845) (1863:1863:1863)) + (PORT d[5] (1296:1296:1296) (1293:1293:1293)) + (PORT d[6] (1592:1592:1592) (1585:1585:1585)) + (PORT d[7] (1164:1164:1164) (1189:1189:1189)) + (PORT d[8] (2381:2381:2381) (2482:2482:2482)) + (PORT d[9] (2921:2921:2921) (3057:3057:3057)) + (PORT d[10] (1218:1218:1218) (1249:1249:1249)) + (PORT d[11] (1580:1580:1580) (1582:1582:1582)) + (PORT d[12] (2493:2493:2493) (2484:2484:2484)) + (PORT clk (1632:1632:1632) (1660:1660:1660)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1922:1922:1922) (1875:1875:1875)) + (PORT clk (1632:1632:1632) (1660:1660:1660)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1635:1635:1635) (1662:1662:1662)) + (PORT d[0] (1772:1772:1772) (1702:1702:1702)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1636:1636:1636) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1636:1636:1636) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1636:1636:1636) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1636:1636:1636) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1599:1599:1599) (1626:1626:1626)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (873:873:873)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (874:874:874)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (874:874:874)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (874:874:874)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (658:658:658) (662:662:662)) + (PORT clk (1632:1632:1632) (1660:1660:1660)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1105:1105:1105) (1106:1106:1106)) + (PORT d[1] (2000:2000:2000) (2014:2014:2014)) + (PORT d[2] (1866:1866:1866) (1929:1929:1929)) + (PORT d[3] (1769:1769:1769) (1819:1819:1819)) + (PORT d[4] (1627:1627:1627) (1656:1656:1656)) + (PORT d[5] (1287:1287:1287) (1275:1275:1275)) + (PORT d[6] (1072:1072:1072) (1042:1042:1042)) + (PORT d[7] (1150:1150:1150) (1164:1164:1164)) + (PORT d[8] (2380:2380:2380) (2481:2481:2481)) + (PORT d[9] (2897:2897:2897) (3029:3029:3029)) + (PORT d[10] (1206:1206:1206) (1234:1234:1234)) + (PORT d[11] (1549:1549:1549) (1554:1554:1554)) + (PORT d[12] (1075:1075:1075) (1073:1073:1073)) + (PORT clk (1629:1629:1629) (1658:1658:1658)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2356:2356:2356) (2327:2327:2327)) + (PORT clk (1629:1629:1629) (1658:1658:1658)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1632:1632:1632) (1660:1660:1660)) + (PORT d[0] (1316:1316:1316) (1275:1275:1275)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1633:1633:1633) (1661:1661:1661)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1633:1633:1633) (1661:1661:1661)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1633:1633:1633) (1661:1661:1661)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1633:1633:1633) (1661:1661:1661)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1596:1596:1596) (1624:1624:1624)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (871:871:871)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (868:868:868) (872:872:872)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (868:868:868) (872:872:872)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (868:868:868) (872:872:872)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[6\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (839:839:839) (836:836:836)) + (PORT datab (631:631:631) (613:613:613)) + (PORT datac (1063:1063:1063) (1084:1084:1084)) + (PORT datad (1193:1193:1193) (1275:1275:1275)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[6\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1128:1128:1128) (1128:1128:1128)) + (PORT datab (1157:1157:1157) (1163:1163:1163)) + (PORT datac (295:295:295) (300:300:300)) + (PORT datad (1811:1811:1811) (1869:1869:1869)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1683:1683:1683) (1712:1712:1712)) + (PORT d[1] (1957:1957:1957) (1973:1973:1973)) + (PORT d[2] (1980:1980:1980) (2032:2032:2032)) + (PORT d[3] (1755:1755:1755) (1779:1779:1779)) + (PORT d[4] (2151:2151:2151) (2158:2158:2158)) + (PORT d[5] (1578:1578:1578) (1587:1587:1587)) + (PORT d[6] (1791:1791:1791) (1780:1780:1780)) + (PORT d[7] (1389:1389:1389) (1412:1412:1412)) + (PORT d[8] (2052:2052:2052) (2119:2119:2119)) + (PORT d[9] (3054:3054:3054) (3125:3125:3125)) + (PORT d[10] (1481:1481:1481) (1536:1536:1536)) + (PORT d[11] (1848:1848:1848) (1865:1865:1865)) + (PORT d[12] (1661:1661:1661) (1619:1619:1619)) + (PORT clk (1635:1635:1635) (1664:1664:1664)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1635:1635:1635) (1664:1664:1664)) + (PORT d[0] (2345:2345:2345) (2389:2389:2389)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1636:1636:1636) (1665:1665:1665)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1602:1602:1602) (1630:1630:1630)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (877:877:877)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (878:878:878)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (878:878:878)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (878:878:878)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1392:1392:1392) (1410:1410:1410)) + (PORT d[1] (2394:2394:2394) (2394:2394:2394)) + (PORT d[2] (2060:2060:2060) (2109:2109:2109)) + (PORT d[3] (1745:1745:1745) (1791:1791:1791)) + (PORT d[4] (2146:2146:2146) (2140:2140:2140)) + (PORT d[5] (1589:1589:1589) (1592:1592:1592)) + (PORT d[6] (1606:1606:1606) (1613:1613:1613)) + (PORT d[7] (1414:1414:1414) (1436:1436:1436)) + (PORT d[8] (2055:2055:2055) (2133:2133:2133)) + (PORT d[9] (3279:3279:3279) (3363:3363:3363)) + (PORT d[10] (1259:1259:1259) (1310:1310:1310)) + (PORT d[11] (1548:1548:1548) (1557:1557:1557)) + (PORT d[12] (1964:1964:1964) (1939:1939:1939)) + (PORT clk (1633:1633:1633) (1660:1660:1660)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1633:1633:1633) (1660:1660:1660)) + (PORT d[0] (1188:1188:1188) (1138:1138:1138)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1634:1634:1634) (1661:1661:1661)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1600:1600:1600) (1626:1626:1626)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (873:873:873)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (874:874:874)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (874:874:874)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (874:874:874)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1224:1224:1224) (1238:1238:1238)) + (PORT clk (1631:1631:1631) (1660:1660:1660)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2906:2906:2906) (3036:3036:3036)) + (PORT d[1] (3956:3956:3956) (3970:3970:3970)) + (PORT d[2] (2127:2127:2127) (2211:2211:2211)) + (PORT d[3] (2035:2035:2035) (2085:2085:2085)) + (PORT d[4] (3252:3252:3252) (3296:3296:3296)) + (PORT d[5] (2206:2206:2206) (2245:2245:2245)) + (PORT d[6] (3770:3770:3770) (3799:3799:3799)) + (PORT d[7] (2824:2824:2824) (2897:2897:2897)) + (PORT d[8] (2011:2011:2011) (2064:2064:2064)) + (PORT d[9] (2573:2573:2573) (2592:2592:2592)) + (PORT d[10] (2726:2726:2726) (2861:2861:2861)) + (PORT d[11] (2962:2962:2962) (2993:2993:2993)) + (PORT d[12] (2837:2837:2837) (2853:2853:2853)) + (PORT clk (1628:1628:1628) (1658:1658:1658)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2136:2136:2136) (2077:2077:2077)) + (PORT clk (1628:1628:1628) (1658:1658:1658)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1631:1631:1631) (1660:1660:1660)) + (PORT d[0] (5015:5015:5015) (4977:4977:4977)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1632:1632:1632) (1661:1661:1661)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1632:1632:1632) (1661:1661:1661)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1632:1632:1632) (1661:1661:1661)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1632:1632:1632) (1661:1661:1661)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1590:1590:1590) (1590:1590:1590)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1944:1944:1944) (2059:2059:2059)) + (PORT clk (1598:1598:1598) (1597:1597:1597)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3905:3905:3905) (3853:3853:3853)) + (PORT d[1] (3992:3992:3992) (3966:3966:3966)) + (PORT d[2] (3833:3833:3833) (3787:3787:3787)) + (PORT d[3] (3979:3979:3979) (3972:3972:3972)) + (PORT d[4] (3807:3807:3807) (3791:3791:3791)) + (PORT d[5] (4035:4035:4035) (3989:3989:3989)) + (PORT d[6] (3860:3860:3860) (3767:3767:3767)) + (PORT d[7] (3789:3789:3789) (3732:3732:3732)) + (PORT d[8] (3948:3948:3948) (3852:3852:3852)) + (PORT d[9] (3800:3800:3800) (3782:3782:3782)) + (PORT d[10] (3952:3952:3952) (3899:3899:3899)) + (PORT d[11] (4025:4025:4025) (3948:3948:3948)) + (PORT d[12] (3870:3870:3870) (3793:3793:3793)) + (PORT clk (1595:1595:1595) (1594:1594:1594)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1598:1598:1598) (1597:1597:1597)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1599:1599:1599) (1598:1598:1598)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1599:1599:1599) (1598:1598:1598)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1599:1599:1599) (1598:1598:1598)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1599:1599:1599) (1598:1598:1598)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1221:1221:1221) (1234:1234:1234)) + (PORT clk (1638:1638:1638) (1665:1665:1665)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2605:2605:2605) (2638:2638:2638)) + (PORT d[1] (3411:3411:3411) (3411:3411:3411)) + (PORT d[2] (2402:2402:2402) (2498:2498:2498)) + (PORT d[3] (1785:1785:1785) (1827:1827:1827)) + (PORT d[4] (3257:3257:3257) (3288:3288:3288)) + (PORT d[5] (2465:2465:2465) (2495:2495:2495)) + (PORT d[6] (3760:3760:3760) (3772:3772:3772)) + (PORT d[7] (2518:2518:2518) (2577:2577:2577)) + (PORT d[8] (2728:2728:2728) (2757:2757:2757)) + (PORT d[9] (2553:2553:2553) (2635:2635:2635)) + (PORT d[10] (3375:3375:3375) (3522:3522:3522)) + (PORT d[11] (2715:2715:2715) (2756:2756:2756)) + (PORT d[12] (2533:2533:2533) (2540:2540:2540)) + (PORT clk (1635:1635:1635) (1663:1663:1663)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2611:2611:2611) (2598:2598:2598)) + (PORT clk (1635:1635:1635) (1663:1663:1663)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1665:1665:1665)) + (PORT d[0] (4724:4724:4724) (4748:4748:4748)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1639:1639:1639) (1666:1666:1666)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1597:1597:1597) (1595:1595:1595)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1230:1230:1230) (1243:1243:1243)) + (PORT clk (1605:1605:1605) (1602:1602:1602)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4061:4061:4061) (3993:3993:3993)) + (PORT d[1] (3940:3940:3940) (3904:3904:3904)) + (PORT d[2] (3869:3869:3869) (3839:3839:3839)) + (PORT d[3] (3965:3965:3965) (3930:3930:3930)) + (PORT d[4] (3828:3828:3828) (3812:3812:3812)) + (PORT d[5] (4033:4033:4033) (3982:3982:3982)) + (PORT d[6] (3822:3822:3822) (3708:3708:3708)) + (PORT d[7] (3727:3727:3727) (3673:3673:3673)) + (PORT d[8] (3964:3964:3964) (3962:3962:3962)) + (PORT d[9] (3748:3748:3748) (3729:3729:3729)) + (PORT d[10] (3969:3969:3969) (3929:3929:3929)) + (PORT d[11] (3895:3895:3895) (3766:3766:3766)) + (PORT d[12] (3921:3921:3921) (3828:3828:3828)) + (PORT clk (1602:1602:1602) (1599:1599:1599)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1605:1605:1605) (1602:1602:1602)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1606:1606:1606) (1603:1603:1603)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1606:1606:1606) (1603:1603:1603)) + (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1606:1606:1606) (1603:1603:1603)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1606:1606:1606) (1603:1603:1603)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1598:1598:1598) (1596:1596:1596)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1503:1503:1503) (1530:1530:1530)) + (PORT datab (1010:1010:1010) (994:994:994)) + (PORT datac (1350:1350:1350) (1343:1343:1343)) + (PORT datad (1391:1391:1391) (1410:1410:1410)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector6\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1200:1200:1200) (1217:1217:1217)) + (PORT datab (368:368:368) (376:376:376)) + (PORT datac (1438:1438:1438) (1387:1387:1387)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~88) + (DELAY + (ABSOLUTE + (PORT dataa (1474:1474:1474) (1560:1560:1560)) + (PORT datab (2870:2870:2870) (2914:2914:2914)) + (PORT datac (156:156:156) (187:187:187)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE raw_loader_in\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (459:459:459) (708:708:708)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~69) + (DELAY + (ABSOLUTE + (PORT datab (2866:2866:2866) (2912:2912:2912)) + (PORT datac (1246:1246:1246) (1249:1249:1249)) + (PORT datad (1455:1455:1455) (1441:1441:1441)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~78) + (DELAY + (ABSOLUTE + (PORT dataa (1060:1060:1060) (1051:1051:1051)) + (PORT datab (1037:1037:1037) (1022:1022:1022)) + (PORT datac (161:161:161) (193:193:193)) + (PORT datad (167:167:167) (191:191:191)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~79) + (DELAY + (ABSOLUTE + (PORT dataa (1236:1236:1236) (1272:1272:1272)) + (PORT datab (1037:1037:1037) (1023:1023:1023)) + (PORT datac (1027:1027:1027) (1028:1028:1028)) + (PORT datad (158:158:158) (178:178:178)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[6\]) + (DELAY + (ABSOLUTE + (PORT dataa (1318:1318:1318) (1316:1316:1316)) + (PORT datab (364:364:364) (393:393:393)) + (PORT datac (1187:1187:1187) (1194:1194:1194)) + (PORT datad (178:178:178) (200:200:200)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1348:1348:1348) (1359:1359:1359)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (744:744:744) (751:751:751)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[6\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (373:373:373) (396:396:396)) + (PORT datab (354:354:354) (352:352:352)) + (PORT datac (341:341:341) (382:382:382)) + (PORT datad (543:543:543) (541:541:541)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1362:1362:1362)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1388:1388:1388) (1360:1360:1360)) + (PORT ena (1550:1550:1550) (1520:1520:1520)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~10) + (DELAY + (ABSOLUTE + (PORT dataa (948:948:948) (1025:1025:1025)) + (PORT datab (968:968:968) (1056:1056:1056)) + (PORT datac (636:636:636) (681:681:681)) + (PORT datad (1059:1059:1059) (1042:1042:1042)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (865:865:865) (894:894:894)) + (PORT datab (889:889:889) (886:886:886)) + (PORT datac (170:170:170) (209:209:209)) + (PORT datad (1518:1518:1518) (1524:1524:1524)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~4) + (DELAY + (ABSOLUTE + (PORT datac (1329:1329:1329) (1374:1374:1374)) + (PORT datad (1241:1241:1241) (1229:1229:1229)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~2) + (DELAY + (ABSOLUTE + (PORT dataa (189:189:189) (231:231:231)) + (PORT datab (188:188:188) (225:225:225)) + (PORT datac (1279:1279:1279) (1250:1250:1250)) + (PORT datad (647:647:647) (697:697:697)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~5) + (DELAY + (ABSOLUTE + (PORT dataa (392:392:392) (429:429:429)) + (PORT datab (555:555:555) (556:556:556)) + (PORT datac (544:544:544) (561:561:561)) + (PORT datad (561:561:561) (560:560:560)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~6) + (DELAY + (ABSOLUTE + (PORT dataa (905:905:905) (941:941:941)) + (PORT datab (179:179:179) (212:212:212)) + (PORT datac (1818:1818:1818) (1822:1822:1822)) + (PORT datad (1659:1659:1659) (1632:1632:1632)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (219:219:219)) + (PORT datab (324:324:324) (337:337:337)) + (PORT datac (1403:1403:1403) (1332:1332:1332)) + (PORT datad (787:787:787) (786:786:786)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (341:341:341) (362:362:362)) + (PORT datac (1261:1261:1261) (1239:1239:1239)) + (PORT datad (310:310:310) (317:317:317)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~61) + (DELAY + (ABSOLUTE + (PORT dataa (191:191:191) (231:231:231)) + (PORT datab (910:910:910) (949:949:949)) + (PORT datac (1113:1113:1113) (1150:1150:1150)) + (PORT datad (862:862:862) (870:870:870)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~63) + (DELAY + (ABSOLUTE + (PORT dataa (379:379:379) (432:432:432)) + (PORT datab (183:183:183) (216:216:216)) + (PORT datac (799:799:799) (807:807:807)) + (PORT datad (184:184:184) (207:207:207)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~64) + (DELAY + (ABSOLUTE + (PORT dataa (812:812:812) (806:806:806)) + (PORT datab (714:714:714) (748:748:748)) + (PORT datac (297:297:297) (303:303:303)) + (PORT datad (922:922:922) (961:961:961)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~65) + (DELAY + (ABSOLUTE + (PORT dataa (330:330:330) (341:341:341)) + (PORT datad (160:160:160) (182:182:182)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1338:1338:1338) (1356:1356:1356)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1380:1380:1380) (1360:1360:1360)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~67) + (DELAY + (ABSOLUTE + (PORT dataa (973:973:973) (1022:1022:1022)) + (PORT datab (635:635:635) (661:661:661)) + (PORT datad (889:889:889) (910:910:910)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~68) + (DELAY + (ABSOLUTE + (PORT dataa (914:914:914) (951:951:951)) + (PORT datab (1118:1118:1118) (1129:1129:1129)) + (PORT datac (233:233:233) (309:309:309)) + (PORT datad (159:159:159) (179:179:179)) + (IOPATH dataa combout (273:273:273) (273:273:273)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~69) + (DELAY + (ABSOLUTE + (PORT dataa (614:614:614) (616:616:616)) + (PORT datab (207:207:207) (246:246:246)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1342:1342:1342) (1359:1359:1359)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1376:1376:1376) (1357:1357:1357)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (602:602:602) (632:632:632)) + (PORT datab (357:357:357) (398:398:398)) + (PORT datac (996:996:996) (979:979:979)) + (PORT datad (577:577:577) (592:592:592)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~58) + (DELAY + (ABSOLUTE + (PORT dataa (717:717:717) (772:772:772)) + (PORT datab (412:412:412) (470:470:470)) + (PORT datac (1091:1091:1091) (1109:1109:1109)) + (PORT datad (595:595:595) (622:622:622)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~130) + (DELAY + (ABSOLUTE + (PORT dataa (914:914:914) (953:953:953)) + (PORT datab (524:524:524) (509:509:509)) + (PORT datac (234:234:234) (309:309:309)) + (PORT datad (927:927:927) (983:983:983)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~59) + (DELAY + (ABSOLUTE + (PORT dataa (591:591:591) (632:632:632)) + (PORT datab (318:318:318) (337:337:337)) + (PORT datad (467:467:467) (451:451:451)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1342:1342:1342) (1359:1359:1359)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1376:1376:1376) (1357:1357:1357)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~56) + (DELAY + (ABSOLUTE + (PORT datac (609:609:609) (661:661:661)) + (PORT datad (641:641:641) (687:687:687)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~57) + (DELAY + (ABSOLUTE + (PORT dataa (184:184:184) (222:222:222)) + (PORT datab (866:866:866) (917:917:917)) + (PORT datad (299:299:299) (307:307:307)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1358:1358:1358)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1382:1382:1382) (1362:1362:1362)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (1934:1934:1934) (1888:1888:1888)) + (PORT datab (391:391:391) (426:426:426)) + (PORT datac (811:811:811) (797:797:797)) + (PORT datad (619:619:619) (660:660:660)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]\~54) + (DELAY + (ABSOLUTE + (PORT datac (1002:1002:1002) (1054:1054:1054)) + (PORT datad (1114:1114:1114) (1146:1146:1146)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]\~55) + (DELAY + (ABSOLUTE + (PORT dataa (718:718:718) (772:772:772)) + (PORT datab (338:338:338) (357:357:357)) + (PORT datad (161:161:161) (182:182:182)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1381:1381:1381) (1360:1360:1360)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]\~50) + (DELAY + (ABSOLUTE + (PORT datac (1005:1005:1005) (1057:1057:1057)) + (PORT datad (1114:1114:1114) (1142:1142:1142)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (191:191:191) (231:231:231)) + (PORT datab (338:338:338) (357:357:357)) + (PORT datad (669:669:669) (727:727:727)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1381:1381:1381) (1360:1360:1360)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]\~52) + (DELAY + (ABSOLUTE + (PORT dataa (831:831:831) (842:842:842)) + (PORT datab (600:600:600) (595:595:595)) + (PORT datac (165:165:165) (202:202:202)) + (PORT datad (1785:1785:1785) (1812:1812:1812)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]\~53) + (DELAY + (ABSOLUTE + (PORT dataa (718:718:718) (767:767:767)) + (PORT datad (160:160:160) (180:180:180)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1381:1381:1381) (1360:1360:1360)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (359:359:359) (403:403:403)) + (PORT datab (385:385:385) (422:422:422)) + (PORT datac (976:976:976) (943:943:943)) + (PORT datad (786:786:786) (760:760:760)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[2\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (360:360:360)) + (PORT datab (818:818:818) (819:819:819)) + (PORT datac (1005:1005:1005) (1056:1056:1056)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[2\]\~48) + (DELAY + (ABSOLUTE + (PORT datab (182:182:182) (215:215:215)) + (PORT datad (667:667:667) (722:722:722)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1381:1381:1381) (1360:1360:1360)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\~1) + (DELAY + (ABSOLUTE + (PORT datab (1049:1049:1049) (1061:1061:1061)) + (PORT datac (2498:2498:2498) (2516:2516:2516)) + (PORT datad (199:199:199) (256:256:256)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (2150:2150:2150) (2251:2251:2251)) + (PORT datab (220:220:220) (288:288:288)) + (PORT datac (322:322:322) (324:324:324)) + (PORT datad (159:159:159) (181:181:181)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (184:184:184) (221:221:221)) + (PORT datab (340:340:340) (348:348:348)) + (PORT datac (707:707:707) (684:684:684)) + (PORT datad (798:798:798) (793:793:793)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (917:917:917) (931:931:931)) + (PORT clk (1632:1632:1632) (1660:1660:1660)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1437:1437:1437) (1459:1459:1459)) + (PORT d[1] (2427:2427:2427) (2426:2426:2426)) + (PORT d[2] (2022:2022:2022) (2098:2098:2098)) + (PORT d[3] (1724:1724:1724) (1752:1752:1752)) + (PORT d[4] (2151:2151:2151) (2144:2144:2144)) + (PORT d[5] (1305:1305:1305) (1306:1306:1306)) + (PORT d[6] (1327:1327:1327) (1324:1324:1324)) + (PORT d[7] (1430:1430:1430) (1466:1466:1466)) + (PORT d[8] (2101:2101:2101) (2190:2190:2190)) + (PORT d[9] (3109:3109:3109) (3227:3227:3227)) + (PORT d[10] (1232:1232:1232) (1258:1258:1258)) + (PORT d[11] (1542:1542:1542) (1548:1548:1548)) + (PORT d[12] (2206:2206:2206) (2177:2177:2177)) + (PORT clk (1629:1629:1629) (1658:1658:1658)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1669:1669:1669) (1611:1611:1611)) + (PORT clk (1629:1629:1629) (1658:1658:1658)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1632:1632:1632) (1660:1660:1660)) + (PORT d[0] (1796:1796:1796) (1741:1741:1741)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1633:1633:1633) (1661:1661:1661)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1633:1633:1633) (1661:1661:1661)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1633:1633:1633) (1661:1661:1661)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1633:1633:1633) (1661:1661:1661)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1596:1596:1596) (1624:1624:1624)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (871:871:871)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (868:868:868) (872:872:872)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (868:868:868) (872:872:872)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (868:868:868) (872:872:872)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (656:656:656) (658:658:658)) + (PORT clk (1630:1630:1630) (1658:1658:1658)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1152:1152:1152) (1166:1166:1166)) + (PORT d[1] (1715:1715:1715) (1726:1726:1726)) + (PORT d[2] (2005:2005:2005) (2064:2064:2064)) + (PORT d[3] (1748:1748:1748) (1796:1796:1796)) + (PORT d[4] (1903:1903:1903) (1927:1927:1927)) + (PORT d[5] (1020:1020:1020) (1007:1007:1007)) + (PORT d[6] (1313:1313:1313) (1296:1296:1296)) + (PORT d[7] (1421:1421:1421) (1466:1466:1466)) + (PORT d[8] (2349:2349:2349) (2445:2445:2445)) + (PORT d[9] (3149:3149:3149) (3272:3272:3272)) + (PORT d[10] (1233:1233:1233) (1268:1268:1268)) + (PORT d[11] (1563:1563:1563) (1562:1562:1562)) + (PORT d[12] (2246:2246:2246) (2232:2232:2232)) + (PORT clk (1627:1627:1627) (1656:1656:1656)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2389:2389:2389) (2362:2362:2362)) + (PORT clk (1627:1627:1627) (1656:1656:1656)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1630:1630:1630) (1658:1658:1658)) + (PORT d[0] (1564:1564:1564) (1517:1517:1517)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1631:1631:1631) (1659:1659:1659)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1631:1631:1631) (1659:1659:1659)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1631:1631:1631) (1659:1659:1659)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1631:1631:1631) (1659:1659:1659)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1594:1594:1594) (1622:1622:1622)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (865:865:865) (869:869:869)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (866:866:866) (870:870:870)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (866:866:866) (870:870:870)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (866:866:866) (870:870:870)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (898:898:898) (905:905:905)) + (PORT clk (1636:1636:1636) (1662:1662:1662)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1335:1335:1335) (1335:1335:1335)) + (PORT d[1] (1735:1735:1735) (1769:1769:1769)) + (PORT d[2] (1738:1738:1738) (1800:1800:1800)) + (PORT d[3] (1447:1447:1447) (1465:1465:1465)) + (PORT d[4] (1602:1602:1602) (1626:1626:1626)) + (PORT d[5] (1326:1326:1326) (1327:1327:1327)) + (PORT d[6] (1603:1603:1603) (1594:1594:1594)) + (PORT d[7] (1717:1717:1717) (1772:1772:1772)) + (PORT d[8] (2845:2845:2845) (2923:2923:2923)) + (PORT d[9] (2929:2929:2929) (3067:3067:3067)) + (PORT d[10] (1461:1461:1461) (1502:1502:1502)) + (PORT d[11] (2112:2112:2112) (2152:2152:2152)) + (PORT d[12] (2524:2524:2524) (2520:2520:2520)) + (PORT clk (1633:1633:1633) (1660:1660:1660)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1672:1672:1672) (1635:1635:1635)) + (PORT clk (1633:1633:1633) (1660:1660:1660)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1636:1636:1636) (1662:1662:1662)) + (PORT d[0] (2027:2027:2027) (1943:1943:1943)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1637:1637:1637) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1637:1637:1637) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1637:1637:1637) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1637:1637:1637) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1600:1600:1600) (1626:1626:1626)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (873:873:873)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (874:874:874)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (874:874:874)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (874:874:874)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[2\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (912:912:912) (945:945:945)) + (PORT datab (839:839:839) (866:866:866)) + (PORT datac (801:801:801) (774:774:774)) + (PORT datad (850:850:850) (833:833:833)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (917:917:917) (926:926:926)) + (PORT clk (1635:1635:1635) (1662:1662:1662)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1397:1397:1397) (1414:1414:1414)) + (PORT d[1] (2406:2406:2406) (2404:2404:2404)) + (PORT d[2] (1870:1870:1870) (1946:1946:1946)) + (PORT d[3] (1735:1735:1735) (1773:1773:1773)) + (PORT d[4] (1891:1891:1891) (1897:1897:1897)) + (PORT d[5] (1306:1306:1306) (1307:1307:1307)) + (PORT d[6] (1597:1597:1597) (1594:1594:1594)) + (PORT d[7] (1402:1402:1402) (1427:1427:1427)) + (PORT d[8] (2065:2065:2065) (2153:2153:2153)) + (PORT d[9] (3109:3109:3109) (3227:3227:3227)) + (PORT d[10] (1245:1245:1245) (1275:1275:1275)) + (PORT d[11] (1573:1573:1573) (1584:1584:1584)) + (PORT d[12] (1965:1965:1965) (1939:1939:1939)) + (PORT clk (1632:1632:1632) (1660:1660:1660)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1576:1576:1576) (1535:1535:1535)) + (PORT clk (1632:1632:1632) (1660:1660:1660)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1635:1635:1635) (1662:1662:1662)) + (PORT d[0] (1620:1620:1620) (1573:1573:1573)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1636:1636:1636) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1636:1636:1636) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1636:1636:1636) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1636:1636:1636) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1599:1599:1599) (1626:1626:1626)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (873:873:873)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (874:874:874)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (874:874:874)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (874:874:874)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[2\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (917:917:917) (911:911:911)) + (PORT datab (1219:1219:1219) (1308:1308:1308)) + (PORT datac (157:157:157) (187:187:187)) + (PORT datad (1111:1111:1111) (1090:1090:1090)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1664:1664:1664) (1686:1686:1686)) + (PORT d[1] (2200:2200:2200) (2204:2204:2204)) + (PORT d[2] (1820:1820:1820) (1898:1898:1898)) + (PORT d[3] (1749:1749:1749) (1797:1797:1797)) + (PORT d[4] (2141:2141:2141) (2132:2132:2132)) + (PORT d[5] (1574:1574:1574) (1581:1581:1581)) + (PORT d[6] (1610:1610:1610) (1620:1620:1620)) + (PORT d[7] (1444:1444:1444) (1482:1482:1482)) + (PORT d[8] (2032:2032:2032) (2110:2110:2110)) + (PORT d[9] (3113:3113:3113) (3227:3227:3227)) + (PORT d[10] (1472:1472:1472) (1512:1512:1512)) + (PORT d[11] (1837:1837:1837) (1843:1843:1843)) + (PORT d[12] (1934:1934:1934) (1903:1903:1903)) + (PORT clk (1634:1634:1634) (1663:1663:1663)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1634:1634:1634) (1663:1663:1663)) + (PORT d[0] (1173:1173:1173) (1128:1128:1128)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1635:1635:1635) (1664:1664:1664)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1601:1601:1601) (1629:1629:1629)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (876:876:876)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (877:877:877)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (877:877:877)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (877:877:877)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2127:2127:2127) (2173:2173:2173)) + (PORT d[1] (3201:3201:3201) (3182:3182:3182)) + (PORT d[2] (2124:2124:2124) (2210:2210:2210)) + (PORT d[3] (2258:2258:2258) (2301:2301:2301)) + (PORT d[4] (2476:2476:2476) (2529:2529:2529)) + (PORT d[5] (2526:2526:2526) (2567:2567:2567)) + (PORT d[6] (3012:3012:3012) (3032:3032:3032)) + (PORT d[7] (2221:2221:2221) (2270:2270:2270)) + (PORT d[8] (2443:2443:2443) (2466:2466:2466)) + (PORT d[9] (2528:2528:2528) (2625:2625:2625)) + (PORT d[10] (3398:3398:3398) (3570:3570:3570)) + (PORT d[11] (2428:2428:2428) (2462:2462:2462)) + (PORT d[12] (2245:2245:2245) (2241:2241:2241)) + (PORT clk (1642:1642:1642) (1671:1671:1671)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1642:1642:1642) (1671:1671:1671)) + (PORT d[0] (3619:3619:3619) (3657:3657:3657)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1672:1672:1672)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1637:1637:1637)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (884:884:884)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (885:885:885)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (885:885:885)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (885:885:885)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1446:1446:1446) (1466:1466:1466)) + (PORT clk (1635:1635:1635) (1662:1662:1662)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2584:2584:2584) (2707:2707:2707)) + (PORT d[1] (3432:3432:3432) (3433:3433:3433)) + (PORT d[2] (2128:2128:2128) (2203:2203:2203)) + (PORT d[3] (1780:1780:1780) (1826:1826:1826)) + (PORT d[4] (3246:3246:3246) (3287:3287:3287)) + (PORT d[5] (2572:2572:2572) (2593:2593:2593)) + (PORT d[6] (2761:2761:2761) (2779:2779:2779)) + (PORT d[7] (2514:2514:2514) (2571:2571:2571)) + (PORT d[8] (2023:2023:2023) (2065:2065:2065)) + (PORT d[9] (2688:2688:2688) (2748:2748:2748)) + (PORT d[10] (3126:3126:3126) (3312:3312:3312)) + (PORT d[11] (2147:2147:2147) (2166:2166:2166)) + (PORT d[12] (2794:2794:2794) (2799:2799:2799)) + (PORT clk (1632:1632:1632) (1660:1660:1660)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2149:2149:2149) (2099:2099:2099)) + (PORT clk (1632:1632:1632) (1660:1660:1660)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1635:1635:1635) (1662:1662:1662)) + (PORT d[0] (4753:4753:4753) (4721:4721:4721)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1636:1636:1636) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1636:1636:1636) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1636:1636:1636) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1636:1636:1636) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1594:1594:1594) (1592:1592:1592)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1260:1260:1260) (1283:1283:1283)) + (PORT clk (1602:1602:1602) (1599:1599:1599)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3880:3880:3880) (3824:3824:3824)) + (PORT d[1] (3944:3944:3944) (3903:3903:3903)) + (PORT d[2] (3818:3818:3818) (3775:3775:3775)) + (PORT d[3] (4005:4005:4005) (4001:4001:4001)) + (PORT d[4] (3840:3840:3840) (3816:3816:3816)) + (PORT d[5] (4053:4053:4053) (3969:3969:3969)) + (PORT d[6] (3878:3878:3878) (3766:3766:3766)) + (PORT d[7] (3778:3778:3778) (3709:3709:3709)) + (PORT d[8] (4086:4086:4086) (4007:4007:4007)) + (PORT d[9] (3813:3813:3813) (3788:3788:3788)) + (PORT d[10] (3968:3968:3968) (3928:3928:3928)) + (PORT d[11] (4029:4029:4029) (3954:3954:3954)) + (PORT d[12] (3858:3858:3858) (3815:3815:3815)) + (PORT clk (1599:1599:1599) (1596:1596:1596)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1602:1602:1602) (1599:1599:1599)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1603:1603:1603) (1600:1600:1600)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1603:1603:1603) (1600:1600:1600)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1603:1603:1603) (1600:1600:1600)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1603:1603:1603) (1600:1600:1600)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1521:1521:1521) (1577:1577:1577)) + (PORT clk (1641:1641:1641) (1669:1669:1669)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2580:2580:2580) (2603:2603:2603)) + (PORT d[1] (3410:3410:3410) (3398:3398:3398)) + (PORT d[2] (2440:2440:2440) (2534:2534:2534)) + (PORT d[3] (2065:2065:2065) (2104:2104:2104)) + (PORT d[4] (2987:2987:2987) (3019:3019:3019)) + (PORT d[5] (2687:2687:2687) (2714:2714:2714)) + (PORT d[6] (3510:3510:3510) (3539:3539:3539)) + (PORT d[7] (2505:2505:2505) (2564:2564:2564)) + (PORT d[8] (2217:2217:2217) (2228:2228:2228)) + (PORT d[9] (2453:2453:2453) (2509:2509:2509)) + (PORT d[10] (3171:3171:3171) (3329:3329:3329)) + (PORT d[11] (2157:2157:2157) (2182:2182:2182)) + (PORT d[12] (2764:2764:2764) (2793:2793:2793)) + (PORT clk (1638:1638:1638) (1667:1667:1667)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2610:2610:2610) (2597:2597:2597)) + (PORT clk (1638:1638:1638) (1667:1667:1667)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1669:1669:1669)) + (PORT d[0] (4718:4718:4718) (4744:4744:4744)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1642:1642:1642) (1670:1670:1670)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1642:1642:1642) (1670:1670:1670)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1642:1642:1642) (1670:1670:1670)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1642:1642:1642) (1670:1670:1670)) + (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1600:1600:1600) (1599:1599:1599)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (964:964:964) (986:986:986)) + (PORT clk (1608:1608:1608) (1606:1606:1606)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3872:3872:3872) (3829:3829:3829)) + (PORT d[1] (3990:3990:3990) (3963:3963:3963)) + (PORT d[2] (3881:3881:3881) (3847:3847:3847)) + (PORT d[3] (4077:4077:4077) (4004:4004:4004)) + (PORT d[4] (3845:3845:3845) (3830:3830:3830)) + (PORT d[5] (3978:3978:3978) (3901:3901:3901)) + (PORT d[6] (3802:3802:3802) (3738:3738:3738)) + (PORT d[7] (3800:3800:3800) (3736:3736:3736)) + (PORT d[8] (3985:3985:3985) (3976:3976:3976)) + (PORT d[9] (3782:3782:3782) (3745:3745:3745)) + (PORT d[10] (3987:3987:3987) (3859:3859:3859)) + (PORT d[11] (3957:3957:3957) (3802:3802:3802)) + (PORT d[12] (3921:3921:3921) (3835:3835:3835)) + (PORT clk (1605:1605:1605) (1603:1603:1603)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1608:1608:1608) (1606:1606:1606)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1607:1607:1607)) + (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1607:1607:1607)) + (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1607:1607:1607)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1607:1607:1607)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1601:1601:1601) (1600:1600:1600)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (597:597:597) (591:591:591)) + (PORT datab (593:593:593) (581:581:581)) + (PORT datac (1138:1138:1138) (1147:1147:1147)) + (PORT datad (1415:1415:1415) (1433:1433:1433)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1291:1291:1291) (1253:1253:1253)) + (PORT datab (1113:1113:1113) (1129:1129:1129)) + (PORT datac (1161:1161:1161) (1174:1174:1174)) + (PORT datad (158:158:158) (180:180:180)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~82) + (DELAY + (ABSOLUTE + (PORT dataa (1508:1508:1508) (1583:1583:1583)) + (PORT datab (2409:2409:2409) (2459:2459:2459)) + (PORT datac (157:157:157) (188:188:188)) + (PORT datad (158:158:158) (179:179:179)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (1521:1521:1521) (1522:1522:1522)) + (PORT datab (1043:1043:1043) (1027:1027:1027)) + (PORT datac (1145:1145:1145) (1157:1157:1157)) + (PORT datad (167:167:167) (191:191:191)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (1522:1522:1522) (1520:1520:1520)) + (PORT datab (1466:1466:1466) (1443:1443:1443)) + (PORT datac (1819:1819:1819) (1795:1795:1795)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[2\]) + (DELAY + (ABSOLUTE + (PORT dataa (1321:1321:1321) (1313:1313:1313)) + (PORT datab (198:198:198) (231:231:231)) + (PORT datac (1612:1612:1612) (1609:1609:1609)) + (PORT datad (341:341:341) (353:353:353)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1348:1348:1348) (1359:1359:1359)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (744:744:744) (751:751:751)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[2\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (527:527:527) (527:527:527)) + (PORT datac (323:323:323) (338:338:338)) + (PORT datad (1250:1250:1250) (1212:1212:1212)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[2\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (374:374:374) (397:397:397)) + (PORT datab (586:586:586) (581:581:581)) + (PORT datac (213:213:213) (280:280:280)) + (PORT datad (297:297:297) (297:297:297)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1345:1345:1345) (1362:1362:1362)) + (PORT asdata (662:662:662) (661:661:661)) + (PORT clrn (1388:1388:1388) (1361:1361:1361)) + (PORT ena (1565:1565:1565) (1541:1541:1541)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal1\~4) + (DELAY + (ABSOLUTE + (PORT datab (1567:1567:1567) (1602:1602:1602)) + (PORT datac (603:603:603) (628:628:628)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~26) + (DELAY + (ABSOLUTE + (PORT dataa (587:587:587) (612:612:612)) + (PORT datab (541:541:541) (548:548:548)) + (PORT datac (792:792:792) (791:791:791)) + (PORT datad (856:856:856) (897:897:897)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~45) + (DELAY + (ABSOLUTE + (PORT dataa (613:613:613) (641:641:641)) + (PORT datab (1234:1234:1234) (1282:1282:1282)) + (PORT datac (866:866:866) (889:889:889)) + (PORT datad (2196:2196:2196) (2202:2202:2202)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1096:1096:1096) (1094:1094:1094)) + (PORT datac (560:560:560) (557:557:557)) + (PORT datad (619:619:619) (644:644:644)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~18) + (DELAY + (ABSOLUTE + (PORT dataa (615:615:615) (643:643:643)) + (PORT datab (179:179:179) (211:211:211)) + (PORT datac (547:547:547) (549:549:549)) + (PORT datad (733:733:733) (723:723:723)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~11) + (DELAY + (ABSOLUTE + (PORT dataa (873:873:873) (909:909:909)) + (PORT datab (1565:1565:1565) (1600:1600:1600)) + (PORT datac (566:566:566) (556:556:556)) + (PORT datad (1497:1497:1497) (1453:1453:1453)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~10) + (DELAY + (ABSOLUTE + (PORT dataa (606:606:606) (644:644:644)) + (PORT datab (615:615:615) (625:625:625)) + (PORT datac (865:865:865) (891:891:891)) + (PORT datad (1569:1569:1569) (1548:1548:1548)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1162:1162:1162) (1211:1211:1211)) + (PORT datab (811:811:811) (789:789:789)) + (PORT datac (2028:2028:2028) (1972:1972:1972)) + (PORT datad (159:159:159) (181:181:181)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~8) + (DELAY + (ABSOLUTE + (PORT dataa (366:366:366) (386:386:386)) + (PORT datab (970:970:970) (1012:1012:1012)) + (PORT datac (1135:1135:1135) (1189:1189:1189)) + (PORT datad (1670:1670:1670) (1709:1709:1709)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1521:1521:1521) (1518:1518:1518)) + (PORT datab (985:985:985) (1047:1047:1047)) + (PORT datad (160:160:160) (182:182:182)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~13) + (DELAY + (ABSOLUTE + (PORT dataa (821:821:821) (818:818:818)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (1013:1013:1013) (980:980:980)) + (PORT datad (492:492:492) (477:477:477)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~15) + (DELAY + (ABSOLUTE + (PORT dataa (833:833:833) (812:812:812)) + (PORT datab (1346:1346:1346) (1325:1325:1325)) + (PORT datac (791:791:791) (787:787:787)) + (PORT datad (306:306:306) (301:301:301)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1036:1036:1036) (1017:1017:1017)) + (PORT datab (598:598:598) (599:599:599)) + (PORT datac (174:174:174) (205:205:205)) + (PORT datad (789:789:789) (796:796:796)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~16) + (DELAY + (ABSOLUTE + (PORT datab (871:871:871) (869:869:869)) + (PORT datac (504:504:504) (491:491:491)) + (PORT datad (157:157:157) (178:178:178)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1045:1045:1045) (1049:1049:1049)) + (PORT datab (592:592:592) (586:586:586)) + (PORT datac (359:359:359) (382:382:382)) + (PORT datad (1186:1186:1186) (1227:1227:1227)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~23) + (DELAY + (ABSOLUTE + (PORT dataa (1136:1136:1136) (1162:1162:1162)) + (PORT datab (599:599:599) (612:612:612)) + (PORT datac (299:299:299) (322:322:322)) + (PORT datad (574:574:574) (566:566:566)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~22) + (DELAY + (ABSOLUTE + (PORT dataa (1387:1387:1387) (1428:1428:1428)) + (PORT datab (611:611:611) (597:597:597)) + (PORT datac (1205:1205:1205) (1225:1225:1225)) + (PORT datad (1487:1487:1487) (1459:1459:1459)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~56) + (DELAY + (ABSOLUTE + (PORT dataa (261:261:261) (346:346:346)) + (PORT datab (243:243:243) (314:314:314)) + (PORT datac (365:365:365) (408:408:408)) + (PORT datad (160:160:160) (182:182:182)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~24) + (DELAY + (ABSOLUTE + (PORT dataa (912:912:912) (924:924:924)) + (PORT datab (660:660:660) (674:674:674)) + (PORT datac (630:630:630) (643:643:643)) + (PORT datad (316:316:316) (315:315:315)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~25) + (DELAY + (ABSOLUTE + (PORT dataa (804:804:804) (796:796:796)) + (PORT datab (873:873:873) (894:894:894)) + (PORT datac (547:547:547) (538:538:538)) + (PORT datad (809:809:809) (817:817:817)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~26) + (DELAY + (ABSOLUTE + (PORT dataa (1569:1569:1569) (1540:1540:1540)) + (PORT datab (1090:1090:1090) (1145:1145:1145)) + (PORT datac (793:793:793) (776:776:776)) + (PORT datad (184:184:184) (210:210:210)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~27) + (DELAY + (ABSOLUTE + (PORT dataa (847:847:847) (837:837:837)) + (PORT datab (900:900:900) (942:942:942)) + (PORT datac (815:815:815) (823:823:823)) + (PORT datad (1775:1775:1775) (1755:1755:1755)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~28) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (219:219:219)) + (PORT datab (200:200:200) (234:234:234)) + (PORT datac (536:536:536) (546:546:546)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~55) + (DELAY + (ABSOLUTE + (PORT dataa (1065:1065:1065) (1065:1065:1065)) + (PORT datab (436:436:436) (483:483:483)) + (PORT datac (391:391:391) (433:433:433)) + (PORT datad (1537:1537:1537) (1549:1549:1549)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~29) + (DELAY + (ABSOLUTE + (PORT dataa (670:670:670) (673:673:673)) + (PORT datab (579:579:579) (607:607:607)) + (PORT datac (817:817:817) (823:823:823)) + (PORT datad (577:577:577) (575:575:575)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~31) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (240:240:240)) + (PORT datab (1185:1185:1185) (1222:1222:1222)) + (PORT datac (155:155:155) (185:185:185)) + (PORT datad (536:536:536) (524:524:524)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~33) + (DELAY + (ABSOLUTE + (PORT dataa (1083:1083:1083) (1102:1102:1102)) + (PORT datab (1778:1778:1778) (1774:1774:1774)) + (PORT datac (569:569:569) (553:553:553)) + (PORT datad (1082:1082:1082) (1084:1084:1084)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~32) + (DELAY + (ABSOLUTE + (PORT dataa (777:777:777) (767:767:767)) + (PORT datab (659:659:659) (672:672:672)) + (PORT datac (561:561:561) (554:554:554)) + (PORT datad (1029:1029:1029) (1033:1033:1033)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~34) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (219:219:219)) + (PORT datab (180:180:180) (212:212:212)) + (PORT datac (2709:2709:2709) (2709:2709:2709)) + (PORT datad (160:160:160) (182:182:182)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~20) + (DELAY + (ABSOLUTE + (PORT dataa (817:817:817) (810:810:810)) + (PORT datab (878:878:878) (911:911:911)) + (PORT datac (184:184:184) (221:221:221)) + (PORT datad (1248:1248:1248) (1258:1258:1258)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~21) + (DELAY + (ABSOLUTE + (PORT dataa (566:566:566) (595:595:595)) + (PORT datab (901:901:901) (940:940:940)) + (PORT datac (1104:1104:1104) (1094:1094:1094)) + (PORT datad (522:522:522) (503:503:503)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~35) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (220:220:220)) + (PORT datab (180:180:180) (212:212:212)) + (PORT datac (154:154:154) (184:184:184)) + (PORT datad (161:161:161) (182:182:182)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~43) + (DELAY + (ABSOLUTE + (PORT datab (824:824:824) (847:847:847)) + (PORT datac (1169:1169:1169) (1164:1164:1164)) + (PORT datad (598:598:598) (626:626:626)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~44) + (DELAY + (ABSOLUTE + (PORT dataa (1016:1016:1016) (1006:1006:1006)) + (PORT datab (1135:1135:1135) (1173:1173:1173)) + (PORT datac (1537:1537:1537) (1530:1530:1530)) + (PORT datad (999:999:999) (1065:1065:1065)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~45) + (DELAY + (ABSOLUTE + (PORT dataa (1762:1762:1762) (1787:1787:1787)) + (PORT datab (182:182:182) (215:215:215)) + (PORT datac (2192:2192:2192) (2237:2237:2237)) + (PORT datad (334:334:334) (348:348:348)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~46) + (DELAY + (ABSOLUTE + (PORT dataa (766:766:766) (794:794:794)) + (PORT datab (888:888:888) (923:923:923)) + (PORT datac (591:591:591) (594:594:594)) + (PORT datad (171:171:171) (200:200:200)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~52) + (DELAY + (ABSOLUTE + (PORT dataa (1193:1193:1193) (1190:1190:1190)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (356:356:356) (377:377:377)) + (PORT datad (574:574:574) (582:582:582)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_17) + (DELAY + (ABSOLUTE + (PORT dataa (972:972:972) (996:996:996)) + (PORT datac (770:770:770) (839:839:839)) + (PORT datad (332:332:332) (354:354:354)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|T6) + (DELAY + (ABSOLUTE + (PORT clk (1344:1344:1344) (1361:1361:1361)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1386:1386:1386) (1360:1360:1360)) + (PORT ena (1092:1092:1092) (1067:1067:1067)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~53) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (219:219:219)) + (PORT datab (741:741:741) (763:763:763)) + (PORT datac (195:195:195) (260:260:260)) + (PORT datad (170:170:170) (197:197:197)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~54) + (DELAY + (ABSOLUTE + (PORT dataa (539:539:539) (534:534:534)) + (PORT datab (810:810:810) (789:789:789)) + (PORT datac (836:836:836) (859:859:859)) + (PORT datad (516:516:516) (510:510:510)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|DFFE_M1_ff\~0) + (DELAY + (ABSOLUTE + (PORT datab (1065:1065:1065) (1105:1105:1105)) + (PORT datad (828:828:828) (885:885:885)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_M1_ff) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1354:1354:1354)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1380:1380:1380) (1352:1352:1352)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|resets_\|x1\~0) + (DELAY + (ABSOLUTE + (PORT datad (179:179:179) (200:200:200)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|fpga_reset) + (DELAY + (ABSOLUTE + (PORT clk (1361:1361:1361) (1382:1382:1382)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE z80_\|fpga_reset\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (536:536:536) (574:574:574)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|resets_\|x1) + (DELAY + (ABSOLUTE + (PORT clk (1368:1368:1368) (1374:1374:1374)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1402:1402:1402) (1374:1374:1374)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|resets_\|x3) + (DELAY + (ABSOLUTE + (PORT datab (1936:1936:1936) (1945:1945:1945)) + (PORT datac (215:215:215) (283:283:283)) + (PORT datad (2288:2288:2288) (2232:2232:2232)) + (IOPATH datab combout (295:295:295) (285:285:285)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_12) + (DELAY + (ABSOLUTE + (PORT clk (1360:1360:1360) (1382:1382:1382)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1402:1402:1402) (1374:1374:1374)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_10\~0) + (DELAY + (ABSOLUTE + (PORT datad (1655:1655:1655) (1641:1641:1641)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_10) + (DELAY + (ABSOLUTE + (PORT clk (1342:1342:1342) (1353:1353:1353)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_9\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (204:204:204) (266:266:266)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_9) + (DELAY + (ABSOLUTE + (PORT clk (1342:1342:1342) (1353:1353:1353)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|resets_\|DFFE_intr_ff3) + (DELAY + (ABSOLUTE + (PORT clk (1342:1342:1342) (1353:1353:1353)) + (PORT asdata (513:513:513) (580:580:580)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|resets_\|clrpc_int\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1068:1068:1068) (1088:1088:1088)) + (PORT datab (1335:1335:1335) (1340:1340:1340)) + (PORT datad (1158:1158:1158) (1226:1226:1226)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (312:312:312)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|resets_\|clrpc_int) + (DELAY + (ABSOLUTE + (PORT clk (1342:1342:1342) (1353:1353:1353)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1382:1382:1382) (1354:1354:1354)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|resets_\|clrpc\~0) + (DELAY + (ABSOLUTE + (PORT dataa (229:229:229) (305:305:305)) + (PORT datab (228:228:228) (299:299:299)) + (PORT datad (199:199:199) (257:257:257)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[0\]) + (DELAY + (ABSOLUTE + (PORT datab (887:887:887) (884:884:884)) + (PORT datad (548:548:548) (546:546:546)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) @@ -49970,11 +49780,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[0\]\~0) (DELAY (ABSOLUTE - (PORT dataa (1294:1294:1294) (1268:1268:1268)) - (PORT datab (581:581:581) (603:603:603)) - (PORT datad (165:165:165) (189:189:189)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) + (PORT dataa (582:582:582) (568:568:568)) + (PORT datab (1138:1138:1138) (1152:1152:1152)) + (PORT datad (488:488:488) (473:473:473)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -49984,11 +49794,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[0\]) (DELAY (ABSOLUTE - (PORT clk (1349:1349:1349) (1358:1358:1358)) + (PORT clk (1354:1354:1354) (1361:1361:1361)) (PORT d (67:67:67) (78:78:78)) - (PORT asdata (524:524:524) (587:587:587)) - (PORT sload (1033:1033:1033) (1049:1049:1049)) - (PORT ena (735:735:735) (733:733:733)) + (PORT asdata (535:535:535) (605:605:605)) + (PORT sload (1632:1632:1632) (1689:1689:1689)) + (PORT ena (1576:1576:1576) (1513:1513:1513)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -50001,12 +49811,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~59) + (INSTANCE D\[0\]\~47) (DELAY (ABSOLUTE - (PORT dataa (818:818:818) (820:820:820)) - (PORT datab (1053:1053:1053) (1083:1083:1083)) - (PORT datac (162:162:162) (196:196:196)) + (PORT dataa (1071:1071:1071) (1098:1098:1098)) + (PORT datab (974:974:974) (974:974:974)) + (PORT datac (162:162:162) (195:195:195)) (IOPATH dataa combout (300:300:300) (323:323:323)) (IOPATH datab combout (306:306:306) (324:324:324)) (IOPATH datac combout (220:220:220) (216:216:216)) @@ -50015,15 +49825,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~60) + (INSTANCE D\[0\]\~48) (DELAY (ABSOLUTE - (PORT dataa (875:875:875) (889:889:889)) - (PORT datab (601:601:601) (626:626:626)) - (PORT datac (1532:1532:1532) (1518:1518:1518)) - (PORT datad (305:305:305) (310:310:310)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (308:308:308) (281:281:281)) + (PORT dataa (1219:1219:1219) (1242:1242:1242)) + (PORT datab (1213:1213:1213) (1190:1190:1190)) + (PORT datac (1267:1267:1267) (1253:1253:1253)) + (PORT datad (307:307:307) (314:314:314)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -50031,72 +49841,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~61) + (INSTANCE D\[1\]\~49) (DELAY (ABSOLUTE - (PORT dataa (1333:1333:1333) (1327:1327:1327)) - (PORT datac (767:767:767) (762:762:762)) - (PORT datad (179:179:179) (201:201:201)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~62) - (DELAY - (ABSOLUTE - (PORT dataa (1305:1305:1305) (1307:1307:1307)) - (PORT datab (871:871:871) (918:918:918)) - (PORT datac (894:894:894) (961:961:961)) - (PORT datad (159:159:159) (179:179:179)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~63) - (DELAY - (ABSOLUTE - (PORT dataa (344:344:344) (370:370:370)) - (PORT datac (162:162:162) (196:196:196)) - (PORT datad (165:165:165) (189:189:189)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~64) - (DELAY - (ABSOLUTE - (PORT dataa (384:384:384) (441:441:441)) - (PORT datab (209:209:209) (250:250:250)) - (PORT datac (1058:1058:1058) (1046:1046:1046)) - (PORT datad (159:159:159) (181:181:181)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~75) - (DELAY - (ABSOLUTE - (PORT dataa (193:193:193) (236:236:236)) - (PORT datac (1230:1230:1230) (1219:1219:1219)) - (PORT datad (180:180:180) (202:202:202)) + (PORT dataa (356:356:356) (367:367:367)) + (PORT datac (804:804:804) (802:802:802)) + (PORT datad (167:167:167) (190:190:190)) (IOPATH dataa combout (307:307:307) (306:306:306)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -50105,13 +49855,43 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~76) + (INSTANCE D\[1\]\~50) (DELAY (ABSOLUTE - (PORT dataa (1040:1040:1040) (1082:1082:1082)) - (PORT datab (1068:1068:1068) (1064:1064:1064)) - (PORT datac (1432:1432:1432) (1391:1391:1391)) - (PORT datad (304:304:304) (309:309:309)) + (PORT dataa (826:826:826) (823:823:823)) + (PORT datab (880:880:880) (925:925:925)) + (PORT datac (1424:1424:1424) (1396:1396:1396)) + (PORT datad (159:159:159) (181:181:181)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (1219:1219:1219) (1234:1234:1234)) + (PORT datac (1012:1012:1012) (997:997:997)) + (PORT datad (168:168:168) (192:192:192)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~52) + (DELAY + (ABSOLUTE + (PORT dataa (1056:1056:1056) (1079:1079:1079)) + (PORT datab (1037:1037:1037) (1021:1021:1021)) + (PORT datac (1029:1029:1029) (1031:1031:1031)) + (PORT datad (301:301:301) (305:305:305)) (IOPATH dataa combout (307:307:307) (280:280:280)) (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (218:218:218) (215:215:215)) @@ -50121,12 +49901,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~82) + (INSTANCE D\[3\]\~58) (DELAY (ABSOLUTE - (PORT dataa (820:820:820) (823:823:823)) - (PORT datab (1439:1439:1439) (1439:1439:1439)) - (PORT datad (166:166:166) (189:189:189)) + (PORT dataa (1072:1072:1072) (1098:1098:1098)) + (PORT datab (1586:1586:1586) (1570:1570:1570)) + (PORT datad (166:166:166) (190:190:190)) (IOPATH dataa combout (300:300:300) (323:323:323)) (IOPATH datab combout (306:306:306) (324:324:324)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -50135,13 +49915,43 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~83) + (INSTANCE D\[3\]\~59) (DELAY (ABSOLUTE - (PORT dataa (879:879:879) (895:895:895)) - (PORT datab (1330:1330:1330) (1350:1350:1350)) - (PORT datac (1533:1533:1533) (1516:1516:1516)) - (PORT datad (306:306:306) (314:314:314)) + (PORT dataa (1066:1066:1066) (1083:1083:1083)) + (PORT datab (1213:1213:1213) (1189:1189:1189)) + (PORT datac (1268:1268:1268) (1256:1256:1256)) + (PORT datad (288:288:288) (296:296:296)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~65) + (DELAY + (ABSOLUTE + (PORT datab (323:323:323) (331:331:331)) + (PORT datac (803:803:803) (798:798:798)) + (PORT datad (165:165:165) (187:187:187)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~66) + (DELAY + (ABSOLUTE + (PORT dataa (830:830:830) (822:822:822)) + (PORT datab (889:889:889) (905:905:905)) + (PORT datac (1424:1424:1424) (1397:1397:1397)) + (PORT datad (161:161:161) (182:182:182)) (IOPATH dataa combout (329:329:329) (332:332:332)) (IOPATH datab combout (308:308:308) (281:281:281)) (IOPATH datac combout (218:218:218) (215:215:215)) @@ -50151,13 +49961,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~92) + (INSTANCE D\[6\]\~70) (DELAY (ABSOLUTE - (PORT datab (1278:1278:1278) (1232:1232:1232)) - (PORT datac (162:162:162) (195:195:195)) - (PORT datad (165:165:165) (187:187:187)) - (IOPATH datab combout (325:325:325) (332:332:332)) + (PORT dataa (1064:1064:1064) (1056:1056:1056)) + (PORT datac (163:163:163) (197:197:197)) + (PORT datad (165:165:165) (189:189:189)) + (IOPATH dataa combout (318:318:318) (327:327:327)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -50165,15 +49975,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~93) + (INSTANCE D\[6\]\~71) (DELAY (ABSOLUTE - (PORT dataa (876:876:876) (893:893:893)) - (PORT datab (824:824:824) (860:860:860)) - (PORT datac (1532:1532:1532) (1521:1521:1521)) + (PORT dataa (1233:1233:1233) (1273:1273:1273)) + (PORT datab (1038:1038:1038) (1023:1023:1023)) + (PORT datac (1027:1027:1027) (1030:1030:1030)) (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -50184,11 +49994,11 @@ (INSTANCE z80_\|nM1_int\~3) (DELAY (ABSOLUTE - (PORT datab (1270:1270:1270) (1359:1359:1359)) - (PORT datac (2167:2167:2167) (2222:2222:2222)) - (PORT datad (516:516:516) (508:508:508)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT dataa (1605:1605:1605) (1656:1656:1656)) + (PORT datab (990:990:990) (1011:1011:1011)) + (PORT datad (403:403:403) (453:453:453)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -50198,10 +50008,10 @@ (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_16) (DELAY (ABSOLUTE - (PORT clk (1357:1357:1357) (1378:1378:1378)) + (PORT clk (1345:1345:1345) (1363:1363:1363)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1403:1403:1403) (1374:1374:1374)) - (PORT ena (1189:1189:1189) (1191:1191:1191)) + (PORT clrn (1389:1389:1389) (1361:1361:1361)) + (PORT ena (1576:1576:1576) (1521:1521:1521)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -50216,7 +50026,7 @@ (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_17\~feeder) (DELAY (ABSOLUTE - (PORT datad (220:220:220) (279:279:279)) + (PORT datad (627:627:627) (664:664:664)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -50226,10 +50036,10 @@ (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_17) (DELAY (ABSOLUTE - (PORT clk (1364:1364:1364) (1371:1371:1371)) + (PORT clk (1359:1359:1359) (1366:1366:1366)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1403:1403:1403) (1374:1374:1374)) - (PORT ena (1217:1217:1217) (1223:1223:1223)) + (PORT clrn (1399:1399:1399) (1369:1369:1369)) + (PORT ena (1312:1312:1312) (1277:1277:1277)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -50244,10 +50054,10 @@ (INSTANCE z80_\|memory_ifc_\|DFFE_mreq_ff2) (DELAY (ABSOLUTE - (PORT clk (1364:1364:1364) (1371:1371:1371)) + (PORT clk (1359:1359:1359) (1366:1366:1366)) (PORT asdata (511:511:511) (578:578:578)) - (PORT clrn (1403:1403:1403) (1374:1374:1374)) - (PORT ena (1217:1217:1217) (1223:1223:1223)) + (PORT clrn (1399:1399:1399) (1369:1369:1369)) + (PORT ena (1312:1312:1312) (1277:1277:1277)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -50262,9 +50072,9 @@ (INSTANCE z80_\|memory_ifc_\|nMREQ_out\~0) (DELAY (ABSOLUTE - (PORT dataa (227:227:227) (302:302:302)) - (PORT datab (228:228:228) (299:299:299)) - (PORT datad (197:197:197) (253:253:253)) + (PORT dataa (229:229:229) (305:305:305)) + (PORT datab (227:227:227) (299:299:299)) + (PORT datad (198:198:198) (256:256:256)) (IOPATH dataa combout (318:318:318) (307:307:307)) (IOPATH datab combout (319:319:319) (307:307:307)) (IOPATH datac combout (312:312:312) (325:325:325)) @@ -50277,9 +50087,9 @@ (INSTANCE z80_\|memory_ifc_\|nMREQ_out\~1) (DELAY (ABSOLUTE - (PORT dataa (850:850:850) (873:873:873)) - (PORT datab (184:184:184) (217:217:217)) - (PORT datad (167:167:167) (191:191:191)) + (PORT dataa (235:235:235) (313:313:313)) + (PORT datab (201:201:201) (235:235:235)) + (PORT datad (159:159:159) (181:181:181)) (IOPATH dataa combout (309:309:309) (326:326:326)) (IOPATH datab combout (309:309:309) (328:328:328)) (IOPATH datac combout (312:312:312) (325:325:325)) @@ -50310,9 +50120,9 @@ (INSTANCE ula_\|i2c_loader_\|divider\[0\]) (DELAY (ABSOLUTE - (PORT clk (1683:1683:1683) (1697:1697:1697)) + (PORT clk (1684:1684:1684) (1698:1698:1698)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1396:1396:1396) (1376:1376:1376)) + (PORT clrn (1387:1387:1387) (1365:1365:1365)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -50326,8 +50136,8 @@ (INSTANCE ula_\|i2c_loader_\|divider\[1\]\~5) (DELAY (ABSOLUTE - (PORT dataa (231:231:231) (309:309:309)) - (PORT datab (228:228:228) (301:301:301)) + (PORT dataa (233:233:233) (311:311:311)) + (PORT datab (225:225:225) (298:298:298)) (IOPATH dataa combout (300:300:300) (323:323:323)) (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datab combout (306:306:306) (324:324:324)) @@ -50341,9 +50151,9 @@ (INSTANCE ula_\|i2c_loader_\|divider\[1\]) (DELAY (ABSOLUTE - (PORT clk (1683:1683:1683) (1697:1697:1697)) + (PORT clk (1684:1684:1684) (1698:1698:1698)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1396:1396:1396) (1376:1376:1376)) + (PORT clrn (1387:1387:1387) (1365:1365:1365)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -50357,9 +50167,9 @@ (INSTANCE ula_\|i2c_loader_\|divider\[2\]\~7) (DELAY (ABSOLUTE - (PORT dataa (230:230:230) (306:306:306)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH dataa cout (376:376:376) (275:275:275)) + (PORT datab (227:227:227) (298:298:298)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) (IOPATH cin cout (50:50:50) (50:50:50)) @@ -50371,9 +50181,9 @@ (INSTANCE ula_\|i2c_loader_\|divider\[2\]) (DELAY (ABSOLUTE - (PORT clk (1683:1683:1683) (1697:1697:1697)) + (PORT clk (1684:1684:1684) (1698:1698:1698)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1396:1396:1396) (1376:1376:1376)) + (PORT clrn (1387:1387:1387) (1365:1365:1365)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -50387,7 +50197,7 @@ (INSTANCE ula_\|i2c_loader_\|divider\[3\]\~9) (DELAY (ABSOLUTE - (PORT datab (229:229:229) (301:301:301)) + (PORT datab (227:227:227) (298:298:298)) (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -50401,66 +50211,9 @@ (INSTANCE ula_\|i2c_loader_\|divider\[3\]) (DELAY (ABSOLUTE - (PORT clk (1683:1683:1683) (1697:1697:1697)) + (PORT clk (1684:1684:1684) (1698:1698:1698)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1396:1396:1396) (1376:1376:1376)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|divider\[4\]\~11) - (DELAY - (ABSOLUTE - (PORT datab (229:229:229) (301:301:301)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datab cout (385:385:385) (280:280:280)) - (IOPATH datad combout (119:119:119) (106:106:106)) - (IOPATH cin combout (408:408:408) (387:387:387)) - (IOPATH cin cout (50:50:50) (50:50:50)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|divider\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1683:1683:1683) (1697:1697:1697)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1396:1396:1396) (1376:1376:1376)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|divider\[5\]\~13) - (DELAY - (ABSOLUTE - (PORT datad (205:205:205) (267:267:267)) - (IOPATH datad combout (119:119:119) (106:106:106)) - (IOPATH cin combout (408:408:408) (387:387:387)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|divider\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1683:1683:1683) (1697:1697:1697)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1396:1396:1396) (1376:1376:1376)) + (PORT clrn (1387:1387:1387) (1365:1365:1365)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -50474,10 +50227,10 @@ (INSTANCE ula_\|i2c_loader_\|WideAnd0\~0) (DELAY (ABSOLUTE - (PORT dataa (230:230:230) (306:306:306)) - (PORT datab (229:229:229) (303:303:303)) - (PORT datac (201:201:201) (271:271:271)) - (PORT datad (205:205:205) (266:266:266)) + (PORT dataa (231:231:231) (310:310:310)) + (PORT datab (227:227:227) (300:300:300)) + (PORT datac (201:201:201) (272:272:272)) + (PORT datad (204:204:204) (265:265:265)) (IOPATH dataa combout (287:287:287) (289:289:289)) (IOPATH datab combout (295:295:295) (294:294:294)) (IOPATH datac combout (218:218:218) (215:215:215)) @@ -50485,16 +50238,73 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|divider\[4\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (229:229:229) (304:304:304)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH dataa cout (376:376:376) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|divider\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1684:1684:1684) (1698:1698:1698)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1387:1387:1387) (1365:1365:1365)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|divider\[5\]\~13) + (DELAY + (ABSOLUTE + (PORT datab (229:229:229) (300:300:300)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH cin combout (408:408:408) (387:387:387)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|divider\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1684:1684:1684) (1698:1698:1698)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1387:1387:1387) (1365:1365:1365)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2c_loader_\|WideAnd0) (DELAY (ABSOLUTE - (PORT datab (228:228:228) (298:298:298)) - (PORT datac (158:158:158) (188:188:188)) - (PORT datad (204:204:204) (264:264:264)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT dataa (185:185:185) (223:223:223)) + (PORT datac (203:203:203) (274:274:274)) + (PORT datad (207:207:207) (270:270:270)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -50504,10 +50314,10 @@ (INSTANCE ula_\|i2c_loader_\|state\.Idle) (DELAY (ABSOLUTE - (PORT clk (1352:1352:1352) (1369:1369:1369)) + (PORT clk (1351:1351:1351) (1369:1369:1369)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1379:1379:1379)) - (PORT ena (1273:1273:1273) (1300:1300:1300)) + (PORT clrn (1387:1387:1387) (1367:1367:1367)) + (PORT ena (1335:1335:1335) (1326:1326:1326)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -50522,7 +50332,7 @@ (INSTANCE ula_\|i2c_loader_\|phase\~0) (DELAY (ABSOLUTE - (PORT datad (223:223:223) (282:282:282)) + (PORT datad (248:248:248) (314:314:314)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -50533,10 +50343,10 @@ (INSTANCE ula_\|i2c_loader_\|phase\[0\]) (DELAY (ABSOLUTE - (PORT clk (1352:1352:1352) (1369:1369:1369)) + (PORT clk (1351:1351:1351) (1369:1369:1369)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1379:1379:1379)) - (PORT ena (1273:1273:1273) (1300:1300:1300)) + (PORT clrn (1387:1387:1387) (1367:1367:1367)) + (PORT ena (1335:1335:1335) (1326:1326:1326)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -50551,8 +50361,8 @@ (INSTANCE ula_\|i2c_loader_\|phase\~1) (DELAY (ABSOLUTE - (PORT datab (291:291:291) (392:392:392)) - (PORT datad (225:225:225) (285:285:285)) + (PORT datab (252:252:252) (329:329:329)) + (PORT datad (247:247:247) (314:314:314)) (IOPATH datab combout (295:295:295) (294:294:294)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -50564,10 +50374,10 @@ (INSTANCE ula_\|i2c_loader_\|phase\[1\]) (DELAY (ABSOLUTE - (PORT clk (1352:1352:1352) (1369:1369:1369)) + (PORT clk (1351:1351:1351) (1369:1369:1369)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1379:1379:1379)) - (PORT ena (1273:1273:1273) (1300:1300:1300)) + (PORT clrn (1387:1387:1387) (1367:1367:1367)) + (PORT ena (1335:1335:1335) (1326:1326:1326)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -50582,20 +50392,24 @@ (INSTANCE ula_\|i2c_loader_\|nbit\~5) (DELAY (ABSOLUTE - (PORT dataa (592:592:592) (633:633:633)) - (IOPATH dataa combout (318:318:318) (327:327:327)) + (PORT datad (612:612:612) (645:645:645)) (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|thisbyte\[0\]\~8) + (INSTANCE ula_\|i2c_loader_\|state\.Idle\~0) (DELAY (ABSOLUTE - (PORT datab (274:274:274) (356:356:356)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datab cout (385:385:385) (280:280:280)) + (PORT dataa (249:249:249) (327:327:327)) + (PORT datab (254:254:254) (328:328:328)) + (PORT datac (552:552:552) (577:577:577)) + (PORT datad (372:372:372) (412:412:412)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -50605,21 +50419,131 @@ (INSTANCE ula_\|i2c_loader_\|Mux42\~0) (DELAY (ABSOLUTE - (PORT datac (645:645:645) (686:686:686)) - (PORT datad (631:631:631) (667:667:667)) + (PORT datab (585:585:585) (623:623:623)) + (PORT datac (590:590:590) (626:626:626)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbit\~6) + (DELAY + (ABSOLUTE + (PORT datab (651:651:651) (681:681:681)) + (PORT datad (215:215:215) (284:284:284)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|nbit\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1351:1351:1351) (1367:1367:1367)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1387:1387:1387) (1365:1365:1365)) + (PORT ena (886:886:886) (878:878:878)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Done\~0) + (DELAY + (ABSOLUTE + (PORT dataa (231:231:231) (308:308:308)) + (PORT datab (243:243:243) (324:324:324)) + (PORT datac (783:783:783) (804:804:804)) + (PORT datad (215:215:215) (278:278:278)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Ack\~0) + (DELAY + (ABSOLUTE + (PORT dataa (321:321:321) (330:330:330)) + (PORT datab (365:365:365) (393:393:393)) + (PORT datac (323:323:323) (334:334:334)) + (PORT datad (379:379:379) (418:418:418)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Ack\~1) + (DELAY + (ABSOLUTE + (PORT dataa (597:597:597) (599:599:599)) + (PORT datab (580:580:580) (612:612:612)) + (PORT datad (159:159:159) (179:179:179)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|state\.Ack) + (DELAY + (ABSOLUTE + (PORT clk (1684:1684:1684) (1707:1707:1707)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1387:1387:1387) (1367:1367:1367)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (610:610:610) (637:637:637)) + (PORT datab (555:555:555) (589:589:589)) + (PORT datac (584:584:584) (616:616:616)) + (PORT datad (231:231:231) (300:300:300)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2c_loader_\|nbyte\~4) (DELAY (ABSOLUTE - (PORT dataa (259:259:259) (342:342:342)) - (PORT datab (294:294:294) (395:395:395)) - (PORT datad (591:591:591) (624:624:624)) + (PORT dataa (734:734:734) (731:731:731)) + (PORT datab (452:452:452) (498:498:498)) + (PORT datad (414:414:414) (453:453:453)) (IOPATH dataa combout (329:329:329) (332:332:332)) (IOPATH datab combout (319:319:319) (307:307:307)) (IOPATH datac combout (312:312:312) (325:325:325)) @@ -50632,8 +50556,8 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[0\]\~7) (DELAY (ABSOLUTE - (PORT datab (261:261:261) (338:338:338)) - (PORT datac (541:541:541) (554:554:554)) + (PORT datab (555:555:555) (586:586:586)) + (PORT datac (552:552:552) (586:586:586)) (IOPATH datab combout (308:308:308) (300:300:300)) (IOPATH datac combout (220:220:220) (216:216:216)) ) @@ -50653,10 +50577,10 @@ (INSTANCE ula_\|i2c_loader_\|nbyte\[0\]\~1) (DELAY (ABSOLUTE - (PORT dataa (258:258:258) (341:341:341)) - (PORT datab (246:246:246) (321:321:321)) - (PORT datac (262:262:262) (362:362:362)) - (PORT datad (473:473:473) (454:454:454)) + (PORT dataa (263:263:263) (347:347:347)) + (PORT datab (260:260:260) (343:343:343)) + (PORT datac (420:420:420) (468:468:468)) + (PORT datad (641:641:641) (594:594:594)) (IOPATH dataa combout (307:307:307) (280:280:280)) (IOPATH datab combout (308:308:308) (281:281:281)) (IOPATH datac combout (220:220:220) (215:215:215)) @@ -50669,10 +50593,10 @@ (INSTANCE ula_\|i2c_loader_\|nbyte\[0\]\~2) (DELAY (ABSOLUTE - (PORT dataa (615:615:615) (661:661:661)) - (PORT datab (608:608:608) (607:607:607)) - (PORT datac (157:157:157) (188:188:188)) - (PORT datad (160:160:160) (181:181:181)) + (PORT dataa (580:580:580) (610:610:610)) + (PORT datab (365:365:365) (397:397:397)) + (PORT datac (284:284:284) (297:297:297)) + (PORT datad (161:161:161) (182:182:182)) (IOPATH dataa combout (300:300:300) (323:323:323)) (IOPATH datab combout (306:306:306) (324:324:324)) (IOPATH datac combout (218:218:218) (216:216:216)) @@ -50685,11 +50609,11 @@ (INSTANCE ula_\|i2c_loader_\|nbyte\[0\]\~3) (DELAY (ABSOLUTE - (PORT datab (783:783:783) (753:753:753)) - (PORT datac (390:390:390) (436:436:436)) - (PORT datad (159:159:159) (179:179:179)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT datab (407:407:407) (454:454:454)) + (PORT datac (572:572:572) (579:579:579)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -50699,9 +50623,9 @@ (INSTANCE ula_\|i2c_loader_\|nbyte\[1\]) (DELAY (ABSOLUTE - (PORT clk (1352:1352:1352) (1369:1369:1369)) + (PORT clk (1351:1351:1351) (1369:1369:1369)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1379:1379:1379)) + (PORT clrn (1387:1387:1387) (1367:1367:1367)) (PORT ena (745:745:745) (752:752:752)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) @@ -50714,63 +50638,66 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Stop\~0) + (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~1) (DELAY (ABSOLUTE - (PORT dataa (624:624:624) (676:676:676)) - (PORT datab (653:653:653) (687:687:687)) - (PORT datac (227:227:227) (300:300:300)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT dataa (261:261:261) (342:342:342)) + (PORT datab (260:260:260) (343:343:343)) + (PORT datac (550:550:550) (582:582:582)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Stop\~1) + (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~3) (DELAY (ABSOLUTE - (PORT dataa (567:567:567) (548:548:548)) - (PORT datab (232:232:232) (282:282:282)) - (PORT datad (318:318:318) (318:318:318)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (312:312:312) (325:325:325)) + (PORT dataa (353:353:353) (359:359:359)) + (PORT datab (181:181:181) (214:214:214)) + (PORT datac (323:323:323) (335:335:335)) + (PORT datad (412:412:412) (452:452:452)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (187:187:187) (225:225:225)) + (PORT datab (369:369:369) (399:399:399)) + (PORT datac (572:572:572) (580:580:580)) + (PORT datad (382:382:382) (423:423:423)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|state\.Stop) + (INSTANCE ula_\|i2c_loader_\|nbit\[0\]) (DELAY (ABSOLUTE - (PORT clk (1351:1351:1351) (1367:1367:1367)) + (PORT clk (1685:1685:1685) (1706:1706:1706)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1397:1397:1397) (1377:1377:1377)) + (PORT clrn (1387:1387:1387) (1365:1365:1365)) + (PORT ena (857:857:857) (842:842:842)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) ) (TIMINGCHECK (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Idle\~0) - (DELAY - (ABSOLUTE - (PORT dataa (263:263:263) (348:348:348)) - (PORT datab (236:236:236) (312:312:312)) - (PORT datac (209:209:209) (285:285:285)) - (PORT datad (530:530:530) (549:549:549)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) + (HOLD ena (posedge clk) (144:144:144)) ) ) (CELL @@ -50778,9 +50705,9 @@ (INSTANCE ula_\|i2c_loader_\|nbit\~0) (DELAY (ABSOLUTE - (PORT dataa (593:593:593) (633:633:633)) - (PORT datab (243:243:243) (317:317:317)) - (PORT datad (214:214:214) (280:280:280)) + (PORT dataa (811:811:811) (838:838:838)) + (PORT datab (242:242:242) (322:322:322)) + (PORT datad (212:212:212) (275:275:275)) (IOPATH dataa combout (329:329:329) (332:332:332)) (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (312:312:312) (325:325:325)) @@ -50793,10 +50720,10 @@ (INSTANCE ula_\|i2c_loader_\|nbit\[2\]) (DELAY (ABSOLUTE - (PORT clk (1350:1350:1350) (1366:1366:1366)) + (PORT clk (1351:1351:1351) (1367:1367:1367)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1396:1396:1396) (1376:1376:1376)) - (PORT ena (1089:1089:1089) (1068:1068:1068)) + (PORT clrn (1387:1387:1387) (1365:1365:1365)) + (PORT ena (886:886:886) (878:878:878)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -50808,46 +50735,68 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Done\~0) + (INSTANCE ula_\|i2c_loader_\|state\.Done\~1) (DELAY (ABSOLUTE - (PORT dataa (236:236:236) (314:314:314)) - (PORT datab (226:226:226) (299:299:299)) - (PORT datac (561:561:561) (597:597:597)) - (PORT datad (216:216:216) (281:281:281)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (PORT dataa (230:230:230) (307:307:307)) + (PORT datab (243:243:243) (323:323:323)) + (PORT datad (214:214:214) (277:277:277)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Ack\~0) + (INSTANCE ula_\|i2c_loader_\|state\~27) (DELAY (ABSOLUTE - (PORT dataa (336:336:336) (357:357:357)) - (PORT datab (345:345:345) (352:352:352)) - (PORT datac (846:846:846) (866:866:866)) - (PORT datad (307:307:307) (310:310:310)) - (IOPATH dataa combout (307:307:307) (280:280:280)) + (PORT dataa (614:614:614) (642:642:642)) + (PORT datab (618:618:618) (655:655:655)) + (PORT datac (552:552:552) (556:556:556)) + (IOPATH dataa combout (318:318:318) (327:327:327)) (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (218:218:218) (215:215:215)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\~24) + (DELAY + (ABSOLUTE + (PORT datab (258:258:258) (341:341:341)) + (PORT datac (234:234:234) (315:315:315)) + (PORT datad (229:229:229) (294:294:294)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Ack\~1) + (INSTANCE ula_\|i2c_loader_\|state\~26) (DELAY (ABSOLUTE - (PORT dataa (185:185:185) (223:223:223)) - (PORT datab (526:526:526) (534:534:534)) - (PORT datad (406:406:406) (459:459:459)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (295:295:295) (300:300:300)) + (PORT datab (447:447:447) (491:491:491)) + (PORT datac (176:176:176) (207:207:207)) + (PORT datad (369:369:369) (404:404:404)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Data\~0) + (DELAY + (ABSOLUTE + (PORT datab (184:184:184) (218:218:218)) + (PORT datad (299:299:299) (300:300:300)) + (IOPATH datab combout (308:308:308) (300:300:300)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -50855,18 +50804,68 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|state\.Ack) + (INSTANCE ula_\|i2c_loader_\|state\.Data) (DELAY (ABSOLUTE - (PORT clk (1351:1351:1351) (1367:1367:1367)) + (PORT clk (1352:1352:1352) (1369:1369:1369)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1397:1397:1397) (1377:1377:1377)) + (PORT asdata (495:495:495) (526:526:526)) + (PORT clrn (1388:1388:1388) (1367:1367:1367)) + (PORT sload (1123:1123:1123) (1186:1186:1186)) + (PORT ena (1136:1136:1136) (1113:1113:1113)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) ) (TIMINGCHECK (HOLD d (posedge clk) (144:144:144)) + (HOLD sload (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Done\~2) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (246:246:246)) + (PORT datab (262:262:262) (340:340:340)) + (PORT datac (552:552:552) (554:554:554)) + (PORT datad (217:217:217) (275:275:275)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Pause\~1) + (DELAY + (ABSOLUTE + (PORT dataa (597:597:597) (633:633:633)) + (PORT datab (184:184:184) (217:217:217)) + (PORT datac (184:184:184) (219:219:219)) + (PORT datad (529:529:529) (547:547:547)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|thisbyte\[0\]\~8) + (DELAY + (ABSOLUTE + (PORT datab (262:262:262) (337:337:337)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) ) ) (CELL @@ -50874,13 +50873,13 @@ (INSTANCE ula_\|i2c_loader_\|nbyte\[1\]\~5) (DELAY (ABSOLUTE - (PORT dataa (259:259:259) (342:342:342)) - (PORT datab (245:245:245) (318:318:318)) - (PORT datac (263:263:263) (363:363:363)) - (PORT datad (474:474:474) (451:451:451)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (PORT dataa (631:631:631) (659:659:659)) + (PORT datab (570:570:570) (594:594:594)) + (PORT datac (528:528:528) (548:548:548)) + (PORT datad (656:656:656) (620:620:620)) + (IOPATH dataa combout (307:307:307) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -50890,10 +50889,10 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[0\]\~18) (DELAY (ABSOLUTE - (PORT dataa (388:388:388) (436:436:436)) - (PORT datab (551:551:551) (569:569:569)) - (PORT datac (792:792:792) (757:757:757)) - (PORT datad (289:289:289) (294:294:294)) + (PORT dataa (562:562:562) (587:587:587)) + (PORT datab (568:568:568) (593:593:593)) + (PORT datac (766:766:766) (753:753:753)) + (PORT datad (160:160:160) (182:182:182)) (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (215:215:215)) @@ -50906,12 +50905,12 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[0\]) (DELAY (ABSOLUTE - (PORT clk (1351:1351:1351) (1369:1369:1369)) + (PORT clk (1680:1680:1680) (1692:1692:1692)) (PORT d (67:67:67) (78:78:78)) - (PORT asdata (1044:1044:1044) (1030:1030:1030)) - (PORT clrn (1397:1397:1397) (1379:1379:1379)) - (PORT sload (959:959:959) (944:944:944)) - (PORT ena (721:721:721) (723:723:723)) + (PORT asdata (1737:1737:1737) (1788:1788:1788)) + (PORT clrn (1387:1387:1387) (1366:1366:1366)) + (PORT sload (1177:1177:1177) (1177:1177:1177)) + (PORT ena (745:745:745) (752:752:752)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -50928,7 +50927,7 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[1\]\~10) (DELAY (ABSOLUTE - (PORT datab (265:265:265) (350:350:350)) + (PORT datab (253:253:253) (331:331:331)) (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -50942,12 +50941,12 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[1\]) (DELAY (ABSOLUTE - (PORT clk (1351:1351:1351) (1369:1369:1369)) + (PORT clk (1680:1680:1680) (1692:1692:1692)) (PORT d (67:67:67) (78:78:78)) - (PORT asdata (1045:1045:1045) (1032:1032:1032)) - (PORT clrn (1397:1397:1397) (1379:1379:1379)) - (PORT sload (959:959:959) (944:944:944)) - (PORT ena (721:721:721) (723:723:723)) + (PORT asdata (1738:1738:1738) (1788:1788:1788)) + (PORT clrn (1387:1387:1387) (1366:1366:1366)) + (PORT sload (1177:1177:1177) (1177:1177:1177)) + (PORT ena (745:745:745) (752:752:752)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -50964,9 +50963,9 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[2\]\~12) (DELAY (ABSOLUTE - (PORT datab (261:261:261) (339:339:339)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datab cout (385:385:385) (280:280:280)) + (PORT dataa (262:262:262) (349:349:349)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) (IOPATH cin cout (50:50:50) (50:50:50)) @@ -50978,11 +50977,11 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[2\]) (DELAY (ABSOLUTE - (PORT clk (1351:1351:1351) (1369:1369:1369)) + (PORT clk (1680:1680:1680) (1692:1692:1692)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1397:1397:1397) (1379:1379:1379)) - (PORT sload (959:959:959) (944:944:944)) - (PORT ena (721:721:721) (723:723:723)) + (PORT clrn (1387:1387:1387) (1366:1366:1366)) + (PORT sload (1177:1177:1177) (1177:1177:1177)) + (PORT ena (745:745:745) (752:752:752)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -50999,7 +50998,7 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[3\]\~14) (DELAY (ABSOLUTE - (PORT datab (273:273:273) (360:360:360)) + (PORT datab (257:257:257) (337:337:337)) (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -51013,12 +51012,12 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[3\]) (DELAY (ABSOLUTE - (PORT clk (1351:1351:1351) (1369:1369:1369)) + (PORT clk (1680:1680:1680) (1692:1692:1692)) (PORT d (67:67:67) (78:78:78)) - (PORT asdata (1045:1045:1045) (1032:1032:1032)) - (PORT clrn (1397:1397:1397) (1379:1379:1379)) - (PORT sload (959:959:959) (944:944:944)) - (PORT ena (721:721:721) (723:723:723)) + (PORT asdata (1738:1738:1738) (1789:1789:1789)) + (PORT clrn (1387:1387:1387) (1366:1366:1366)) + (PORT sload (1177:1177:1177) (1177:1177:1177)) + (PORT ena (745:745:745) (752:752:752)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -51035,10 +51034,10 @@ (INSTANCE ula_\|i2c_loader_\|Equal2\~0) (DELAY (ABSOLUTE - (PORT dataa (400:400:400) (453:453:453)) - (PORT datab (266:266:266) (350:350:350)) - (PORT datac (245:245:245) (323:323:323)) - (PORT datad (248:248:248) (324:324:324)) + (PORT dataa (599:599:599) (628:628:628)) + (PORT datab (615:615:615) (638:638:638)) + (PORT datac (376:376:376) (421:421:421)) + (PORT datad (420:420:420) (463:463:463)) (IOPATH dataa combout (318:318:318) (307:307:307)) (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (218:218:218) (215:215:215)) @@ -51046,28 +51045,12 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Pause\~0) - (DELAY - (ABSOLUTE - (PORT dataa (660:660:660) (713:713:713)) - (PORT datab (237:237:237) (313:313:313)) - (PORT datac (649:649:649) (690:690:690)) - (PORT datad (234:234:234) (300:300:300)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2c_loader_\|thisbyte\[4\]\~16) (DELAY (ABSOLUTE - (PORT dataa (278:278:278) (369:369:369)) + (PORT dataa (261:261:261) (340:340:340)) (IOPATH dataa combout (329:329:329) (332:332:332)) (IOPATH cin combout (408:408:408) (387:387:387)) ) @@ -51078,11 +51061,11 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[4\]) (DELAY (ABSOLUTE - (PORT clk (1351:1351:1351) (1369:1369:1369)) + (PORT clk (1680:1680:1680) (1692:1692:1692)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1397:1397:1397) (1379:1379:1379)) - (PORT sload (959:959:959) (944:944:944)) - (PORT ena (721:721:721) (723:723:723)) + (PORT clrn (1387:1387:1387) (1366:1366:1366)) + (PORT sload (1177:1177:1177) (1177:1177:1177)) + (PORT ena (745:745:745) (752:752:752)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -51096,30 +51079,28 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Pause\~1) + (INSTANCE ula_\|i2c_loader_\|Equal2\~1) (DELAY (ABSOLUTE - (PORT datab (583:583:583) (569:569:569)) - (PORT datac (313:313:313) (323:323:323)) - (PORT datad (612:612:612) (632:632:632)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT datac (159:159:159) (190:190:190)) + (PORT datad (386:386:386) (425:425:425)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Done\~2) + (INSTANCE ula_\|i2c_loader_\|state\.Pause\~0) (DELAY (ABSOLUTE - (PORT dataa (203:203:203) (240:240:240)) - (PORT datab (258:258:258) (335:335:335)) - (PORT datac (208:208:208) (282:282:282)) - (PORT datad (461:461:461) (431:431:431)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT dataa (250:250:250) (328:328:328)) + (PORT datab (361:361:361) (391:391:391)) + (PORT datac (551:551:551) (583:583:583)) + (PORT datad (496:496:496) (485:485:485)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -51129,27 +51110,11 @@ (INSTANCE ula_\|i2c_loader_\|state\.Pause\~2) (DELAY (ABSOLUTE - (PORT dataa (321:321:321) (330:330:330)) - (PORT datab (234:234:234) (288:288:288)) - (PORT datac (236:236:236) (319:319:319)) - (PORT datad (385:385:385) (435:435:435)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Pause\~3) - (DELAY - (ABSOLUTE - (PORT dataa (321:321:321) (335:335:335)) - (PORT datab (554:554:554) (543:543:543)) - (PORT datad (160:160:160) (180:180:180)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) + (PORT dataa (184:184:184) (221:221:221)) + (PORT datab (597:597:597) (610:610:610)) + (PORT datad (314:314:314) (315:315:315)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (295:295:295) (300:300:300)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -51160,9 +51125,9 @@ (INSTANCE ula_\|i2c_loader_\|state\.Pause) (DELAY (ABSOLUTE - (PORT clk (1351:1351:1351) (1367:1367:1367)) + (PORT clk (1352:1352:1352) (1369:1369:1369)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1397:1397:1397) (1377:1377:1377)) + (PORT clrn (1388:1388:1388) (1367:1367:1367)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -51176,9 +51141,9 @@ (INSTANCE ula_\|i2c_loader_\|state\~25) (DELAY (ABSOLUTE - (PORT dataa (238:238:238) (315:315:315)) - (PORT datab (235:235:235) (289:289:289)) - (PORT datad (383:383:383) (431:431:431)) + (PORT dataa (555:555:555) (578:578:578)) + (PORT datab (541:541:541) (536:536:536)) + (PORT datad (239:239:239) (307:307:307)) (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (295:295:295) (294:294:294)) (IOPATH datac combout (312:312:312) (325:325:325)) @@ -51191,10 +51156,10 @@ (INSTANCE ula_\|i2c_loader_\|state\.Start) (DELAY (ABSOLUTE - (PORT clk (1351:1351:1351) (1367:1367:1367)) + (PORT clk (1351:1351:1351) (1369:1369:1369)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1397:1397:1397) (1377:1377:1377)) - (PORT ena (1069:1069:1069) (1069:1069:1069)) + (PORT clrn (1387:1387:1387) (1367:1367:1367)) + (PORT ena (1335:1335:1335) (1326:1326:1326)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -51209,8 +51174,8 @@ (INSTANCE ula_\|i2c_loader_\|nbyte\~0) (DELAY (ABSOLUTE - (PORT datab (290:290:290) (389:389:389)) - (PORT datad (587:587:587) (620:620:620)) + (PORT datab (448:448:448) (492:492:492)) + (PORT datad (418:418:418) (455:455:455)) (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -51222,9 +51187,9 @@ (INSTANCE ula_\|i2c_loader_\|nbyte\[0\]) (DELAY (ABSOLUTE - (PORT clk (1352:1352:1352) (1369:1369:1369)) + (PORT clk (1351:1351:1351) (1369:1369:1369)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1379:1379:1379)) + (PORT clrn (1387:1387:1387) (1367:1367:1367)) (PORT ena (745:745:745) (752:752:752)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) @@ -51237,13 +51202,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~1) + (INSTANCE ula_\|i2c_loader_\|state\.Stop\~0) (DELAY (ABSOLUTE - (PORT dataa (626:626:626) (670:670:670)) - (PORT datac (625:625:625) (655:655:655)) - (PORT datad (404:404:404) (459:459:459)) - (IOPATH dataa combout (329:329:329) (332:332:332)) + (PORT datab (259:259:259) (341:341:341)) + (PORT datac (236:236:236) (317:317:317)) + (PORT datad (231:231:231) (296:296:296)) + (IOPATH datab combout (295:295:295) (285:285:285)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -51251,165 +51216,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~2) + (INSTANCE ula_\|i2c_loader_\|state\.Stop\~1) (DELAY (ABSOLUTE - (PORT dataa (966:966:966) (966:966:966)) - (PORT datab (449:449:449) (502:502:502)) - (PORT datac (229:229:229) (302:302:302)) - (PORT datad (614:614:614) (648:648:648)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (184:184:184) (221:221:221)) - (PORT datab (181:181:181) (214:214:214)) - (PORT datac (547:547:547) (572:572:572)) - (PORT datad (305:305:305) (307:307:307)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (325:325:325) (342:342:342)) - (PORT datab (231:231:231) (283:283:283)) - (PORT datac (522:522:522) (513:513:513)) - (PORT datad (388:388:388) (434:434:434)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (273:273:273) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|nbit\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1683:1683:1683) (1697:1697:1697)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1396:1396:1396) (1376:1376:1376)) - (PORT ena (1060:1060:1060) (1026:1026:1026)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\~6) - (DELAY - (ABSOLUTE - (PORT dataa (590:590:590) (630:630:630)) - (PORT datad (218:218:218) (284:284:284)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|nbit\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1350:1350:1350) (1366:1366:1366)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1396:1396:1396) (1376:1376:1376)) - (PORT ena (1089:1089:1089) (1068:1068:1068)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Done\~1) - (DELAY - (ABSOLUTE - (PORT dataa (237:237:237) (317:317:317)) - (PORT datab (228:228:228) (302:302:302)) - (PORT datad (218:218:218) (284:284:284)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\~27) - (DELAY - (ABSOLUTE - (PORT dataa (657:657:657) (707:707:707)) - (PORT datac (646:646:646) (687:687:687)) - (PORT datad (460:460:460) (431:431:431)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\~24) - (DELAY - (ABSOLUTE - (PORT dataa (624:624:624) (675:675:675)) - (PORT datab (654:654:654) (686:686:686)) - (PORT datac (224:224:224) (296:296:296)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (308:308:308) (281:281:281)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\~26) - (DELAY - (ABSOLUTE - (PORT dataa (661:661:661) (712:712:712)) - (PORT datac (647:647:647) (689:689:689)) - (PORT datad (326:326:326) (325:325:325)) + (PORT dataa (185:185:185) (221:221:221)) + (PORT datab (600:600:600) (606:606:606)) + (PORT datad (343:343:343) (358:358:358)) (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Data\~0) - (DELAY - (ABSOLUTE - (PORT dataa (186:186:186) (224:224:224)) - (PORT datad (160:160:160) (180:180:180)) - (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (295:295:295) (285:285:285)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -51417,24 +51231,18 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|state\.Data) + (INSTANCE ula_\|i2c_loader_\|state\.Stop) (DELAY (ABSOLUTE - (PORT clk (1351:1351:1351) (1367:1367:1367)) + (PORT clk (1684:1684:1684) (1707:1707:1707)) (PORT d (67:67:67) (78:78:78)) - (PORT asdata (516:516:516) (563:563:563)) - (PORT clrn (1397:1397:1397) (1377:1377:1377)) - (PORT sload (789:789:789) (905:905:905)) - (PORT ena (1069:1069:1069) (1069:1069:1069)) + (PORT clrn (1387:1387:1387) (1367:1367:1367)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) ) (TIMINGCHECK (HOLD d (posedge clk) (144:144:144)) - (HOLD sload (posedge clk) (144:144:144)) - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) ) ) (CELL @@ -51442,11 +51250,11 @@ (INSTANCE ula_\|i2c_loader_\|scl_out\~0) (DELAY (ABSOLUTE - (PORT datab (261:261:261) (339:339:339)) - (PORT datac (570:570:570) (586:586:586)) - (PORT datad (209:209:209) (276:276:276)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT dataa (386:386:386) (431:431:431)) + (PORT datab (262:262:262) (340:340:340)) + (PORT datad (525:525:525) (551:551:551)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -51458,8 +51266,8 @@ (ABSOLUTE (PORT clk (1352:1352:1352) (1369:1369:1369)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1379:1379:1379)) - (PORT ena (1273:1273:1273) (1300:1300:1300)) + (PORT clrn (1388:1388:1388) (1367:1367:1367)) + (PORT ena (1136:1136:1136) (1113:1113:1113)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -51474,10 +51282,10 @@ (INSTANCE ula_\|i2c_loader_\|scl_out\~1) (DELAY (ABSOLUTE - (PORT dataa (614:614:614) (660:660:660)) - (PORT datab (290:290:290) (387:387:387)) - (PORT datac (232:232:232) (310:310:310)) - (PORT datad (199:199:199) (256:256:256)) + (PORT dataa (599:599:599) (634:634:634)) + (PORT datab (614:614:614) (648:648:648)) + (PORT datac (553:553:553) (587:587:587)) + (PORT datad (198:198:198) (255:255:255)) (IOPATH dataa combout (329:329:329) (332:332:332)) (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (220:220:220) (216:216:216)) @@ -51490,12 +51298,12 @@ (INSTANCE ula_\|i2c_loader_\|scl_out\~2) (DELAY (ABSOLUTE - (PORT dataa (597:597:597) (609:609:609)) - (PORT datab (183:183:183) (217:217:217)) - (PORT datad (586:586:586) (618:618:618)) + (PORT dataa (199:199:199) (245:245:245)) + (PORT datab (182:182:182) (214:214:214)) + (PORT datac (572:572:572) (602:602:602)) (IOPATH dataa combout (309:309:309) (326:326:326)) (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH datac combout (220:220:220) (216:216:216)) ) ) ) @@ -51505,9 +51313,9 @@ (DELAY (ABSOLUTE (PORT clk (1306:1306:1306) (1319:1319:1319)) - (PORT d (850:850:850) (915:915:915)) - (PORT aload (1507:1507:1507) (1553:1553:1553)) - (PORT ena (798:798:798) (813:813:813)) + (PORT d (853:853:853) (917:917:917)) + (PORT aload (1497:1497:1497) (1541:1541:1541)) + (PORT ena (626:626:626) (629:629:629)) (IOPATH (posedge clk) q (549:549:549) (552:552:552)) (IOPATH (posedge aload) q (455:455:455) (458:458:458)) ) @@ -51526,8 +51334,8 @@ (ABSOLUTE (PORT clk (1352:1352:1352) (1369:1369:1369)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1398:1398:1398) (1379:1379:1379)) - (PORT ena (1273:1273:1273) (1300:1300:1300)) + (PORT clrn (1388:1388:1388) (1367:1367:1367)) + (PORT ena (1136:1136:1136) (1113:1113:1113)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -51542,10 +51350,10 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\~4) (DELAY (ABSOLUTE - (PORT datac (811:811:811) (844:844:844)) - (PORT datad (569:569:569) (594:594:594)) + (PORT dataa (451:451:451) (502:502:502)) + (PORT datac (588:588:588) (627:627:627)) + (IOPATH dataa combout (329:329:329) (332:332:332)) (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) @@ -51554,10 +51362,10 @@ (INSTANCE ula_\|i2c_loader_\|Mux35\~0) (DELAY (ABSOLUTE - (PORT dataa (412:412:412) (464:464:464)) - (PORT datab (422:422:422) (464:464:464)) - (PORT datac (364:364:364) (401:401:401)) - (PORT datad (365:365:365) (408:408:408)) + (PORT dataa (599:599:599) (632:632:632)) + (PORT datab (610:610:610) (641:641:641)) + (PORT datac (373:373:373) (424:424:424)) + (PORT datad (417:417:417) (468:468:468)) (IOPATH dataa combout (273:273:273) (269:269:269)) (IOPATH datab combout (295:295:295) (294:294:294)) (IOPATH datac combout (218:218:218) (215:215:215)) @@ -51570,26 +51378,10 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\~13) (DELAY (ABSOLUTE - (PORT dataa (277:277:277) (366:366:366)) - (PORT datab (266:266:266) (347:347:347)) - (PORT datac (246:246:246) (327:327:327)) - (PORT datad (235:235:235) (302:302:302)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~14) - (DELAY - (ABSOLUTE - (PORT datac (248:248:248) (333:333:333)) - (PORT datad (236:236:236) (300:300:300)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (PORT dataa (265:265:265) (353:353:353)) + (PORT datac (235:235:235) (314:314:314)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datac combout (220:220:220) (216:216:216)) ) ) ) @@ -51598,12 +51390,92 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\~15) (DELAY (ABSOLUTE - (PORT dataa (186:186:186) (224:224:224)) - (PORT datab (274:274:274) (361:361:361)) - (PORT datac (246:246:246) (329:329:329)) - (PORT datad (180:180:180) (203:203:203)) + (PORT dataa (263:263:263) (350:350:350)) + (PORT datab (252:252:252) (329:329:329)) + (PORT datac (233:233:233) (311:311:311)) + (PORT datad (234:234:234) (305:305:305)) (IOPATH dataa combout (318:318:318) (323:323:323)) (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~16) + (DELAY + (ABSOLUTE + (PORT dataa (192:192:192) (235:235:235)) + (PORT datab (262:262:262) (343:343:343)) + (PORT datac (157:157:157) (188:188:188)) + (PORT datad (238:238:238) (306:306:306)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (319:319:319) (307:307:307)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~17) + (DELAY + (ABSOLUTE + (PORT dataa (564:564:564) (591:591:591)) + (PORT datab (454:454:454) (501:501:501)) + (PORT datac (373:373:373) (423:423:423)) + (PORT datad (572:572:572) (607:607:607)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~18) + (DELAY + (ABSOLUTE + (PORT dataa (185:185:185) (221:221:221)) + (PORT datab (418:418:418) (453:453:453)) + (PORT datac (492:492:492) (480:480:480)) + (PORT datad (417:417:417) (464:464:464)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (308:308:308) (294:294:294)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~20) + (DELAY + (ABSOLUTE + (PORT dataa (586:586:586) (612:612:612)) + (PORT datab (610:610:610) (636:636:636)) + (PORT datac (571:571:571) (600:600:600)) + (PORT datad (390:390:390) (428:428:428)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~21) + (DELAY + (ABSOLUTE + (PORT dataa (519:519:519) (510:510:510)) + (PORT datab (183:183:183) (215:215:215)) + (PORT datac (373:373:373) (421:421:421)) + (PORT datad (417:417:417) (463:463:463)) + (IOPATH dataa combout (307:307:307) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -51611,12 +51483,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~24) + (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~23) (DELAY (ABSOLUTE - (PORT datab (421:421:421) (464:464:464)) - (PORT datac (814:814:814) (846:846:846)) - (PORT datad (387:387:387) (428:428:428)) + (PORT datab (617:617:617) (646:646:646)) + (PORT datac (587:587:587) (626:626:626)) + (PORT datad (422:422:422) (470:470:470)) (IOPATH datab combout (295:295:295) (285:285:285)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -51628,10 +51500,12 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~6) (DELAY (ABSOLUTE - (PORT dataa (658:658:658) (710:710:710)) - (PORT datac (646:646:646) (690:690:690)) - (PORT datad (235:235:235) (304:304:304)) - (IOPATH dataa combout (287:287:287) (289:289:289)) + (PORT dataa (352:352:352) (364:364:364)) + (PORT datab (583:583:583) (618:618:618)) + (PORT datac (245:245:245) (318:318:318)) + (PORT datad (226:226:226) (286:286:286)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -51642,26 +51516,12 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~7) (DELAY (ABSOLUTE - (PORT dataa (266:266:266) (352:352:352)) - (PORT datab (231:231:231) (281:281:281)) - (PORT datac (157:157:157) (187:187:187)) - (PORT datad (329:329:329) (327:327:327)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~8) - (DELAY - (ABSOLUTE - (PORT datab (410:410:410) (470:470:470)) - (PORT datac (523:523:523) (517:517:517)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH datab combout (273:273:273) (275:275:275)) + (PORT dataa (186:186:186) (223:223:223)) + (PORT datab (253:253:253) (330:330:330)) + (PORT datac (757:757:757) (751:751:751)) + (PORT datad (246:246:246) (312:312:312)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -51672,11 +51532,11 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]) (DELAY (ABSOLUTE - (PORT clk (1351:1351:1351) (1369:1369:1369)) + (PORT clk (1351:1351:1351) (1368:1368:1368)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1397:1397:1397) (1379:1379:1379)) - (PORT sclr (1021:1021:1021) (1080:1080:1080)) - (PORT ena (1279:1279:1279) (1235:1235:1235)) + (PORT clrn (1387:1387:1387) (1366:1366:1366)) + (PORT sclr (864:864:864) (955:955:955)) + (PORT ena (842:842:842) (823:823:823)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -51687,48 +51547,32 @@ (HOLD ena (posedge clk) (144:144:144)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~21) - (DELAY - (ABSOLUTE - (PORT dataa (276:276:276) (365:365:365)) - (PORT datab (272:272:272) (355:355:355)) - (PORT datac (246:246:246) (327:327:327)) - (PORT datad (234:234:234) (302:302:302)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2c_loader_\|shiftreg\~22) (DELAY (ABSOLUTE - (PORT dataa (350:350:350) (358:358:358)) - (PORT datab (349:349:349) (357:357:357)) - (PORT datac (364:364:364) (400:400:400)) - (PORT datad (391:391:391) (431:431:431)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (308:308:308) (324:324:324)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (PORT datab (182:182:182) (214:214:214)) + (PORT datac (593:593:593) (634:634:634)) + (PORT datad (202:202:202) (260:260:260)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~23) + (INSTANCE ula_\|i2c_loader_\|shiftreg\[6\]\~9) (DELAY (ABSOLUTE - (PORT dataa (225:225:225) (298:298:298)) - (PORT datac (817:817:817) (848:848:848)) - (PORT datad (159:159:159) (180:180:180)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (PORT dataa (348:348:348) (363:363:363)) + (PORT datab (580:580:580) (613:613:613)) + (PORT datac (247:247:247) (323:323:323)) + (PORT datad (223:223:223) (283:283:283)) + (IOPATH dataa combout (272:272:272) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -51738,29 +51582,13 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[6\]\~10) (DELAY (ABSOLUTE - (PORT dataa (662:662:662) (692:692:692)) - (PORT datab (445:445:445) (501:501:501)) - (PORT datac (545:545:545) (575:575:575)) - (PORT datad (180:180:180) (202:202:202)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[6\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (966:966:966) (963:963:963)) - (PORT datab (525:525:525) (530:530:530)) - (PORT datac (847:847:847) (866:866:866)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT dataa (184:184:184) (222:222:222)) + (PORT datab (253:253:253) (331:331:331)) + (PORT datac (756:756:756) (753:753:753)) + (PORT datad (246:246:246) (313:313:313)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -51770,10 +51598,10 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[1\]) (DELAY (ABSOLUTE - (PORT clk (1351:1351:1351) (1369:1369:1369)) + (PORT clk (1351:1351:1351) (1368:1368:1368)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1397:1397:1397) (1379:1379:1379)) - (PORT ena (1112:1112:1112) (1084:1084:1084)) + (PORT clrn (1387:1387:1387) (1366:1366:1366)) + (PORT ena (917:917:917) (912:912:912)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -51783,49 +51611,17 @@ (HOLD ena (posedge clk) (144:144:144)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~18) - (DELAY - (ABSOLUTE - (PORT dataa (275:275:275) (366:366:366)) - (PORT datab (270:270:270) (356:356:356)) - (PORT datac (242:242:242) (322:322:322)) - (PORT datad (238:238:238) (311:311:311)) - (IOPATH dataa combout (290:290:290) (306:306:306)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2c_loader_\|shiftreg\~19) (DELAY (ABSOLUTE - (PORT dataa (416:416:416) (466:466:466)) - (PORT datab (388:388:388) (440:440:440)) - (PORT datac (286:286:286) (299:299:299)) - (PORT datad (179:179:179) (201:201:201)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~20) - (DELAY - (ABSOLUTE - (PORT dataa (226:226:226) (300:300:300)) - (PORT datac (811:811:811) (842:842:842)) - (PORT datad (161:161:161) (183:183:183)) - (IOPATH dataa combout (273:273:273) (269:269:269)) + (PORT dataa (186:186:186) (223:223:223)) + (PORT datab (225:225:225) (296:296:296)) + (PORT datac (589:589:589) (627:627:627)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (295:295:295) (300:300:300)) (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) @@ -51834,76 +51630,10 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[2\]) (DELAY (ABSOLUTE - (PORT clk (1351:1351:1351) (1369:1369:1369)) + (PORT clk (1351:1351:1351) (1368:1368:1368)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1397:1397:1397) (1379:1379:1379)) - (PORT ena (1112:1112:1112) (1084:1084:1084)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~16) - (DELAY - (ABSOLUTE - (PORT dataa (397:397:397) (450:450:450)) - (PORT datab (266:266:266) (347:347:347)) - (PORT datac (248:248:248) (332:332:332)) - (PORT datad (247:247:247) (319:319:319)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~17) - (DELAY - (ABSOLUTE - (PORT dataa (413:413:413) (470:470:470)) - (PORT datab (419:419:419) (462:462:462)) - (PORT datac (467:467:467) (451:451:451)) - (PORT datad (326:326:326) (334:334:334)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~26) - (DELAY - (ABSOLUTE - (PORT dataa (595:595:595) (630:630:630)) - (PORT datab (222:222:222) (291:291:291)) - (PORT datac (812:812:812) (843:843:843)) - (PORT datad (160:160:160) (181:181:181)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (220:220:220) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1351:1351:1351) (1369:1369:1369)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1397:1397:1397) (1379:1379:1379)) - (PORT ena (1112:1112:1112) (1084:1084:1084)) + (PORT clrn (1387:1387:1387) (1366:1366:1366)) + (PORT ena (917:917:917) (912:912:912)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -51918,12 +51648,12 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\~25) (DELAY (ABSOLUTE - (PORT dataa (184:184:184) (221:221:221)) - (PORT datab (626:626:626) (663:663:663)) - (PORT datac (571:571:571) (592:592:592)) - (PORT datad (340:340:340) (371:371:371)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) + (PORT dataa (457:457:457) (502:502:502)) + (PORT datab (620:620:620) (658:658:658)) + (PORT datac (298:298:298) (309:309:309)) + (PORT datad (199:199:199) (256:256:256)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -51931,13 +51661,13 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[4\]) + (INSTANCE ula_\|i2c_loader_\|shiftreg\[3\]) (DELAY (ABSOLUTE - (PORT clk (1351:1351:1351) (1369:1369:1369)) + (PORT clk (1351:1351:1351) (1368:1368:1368)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1397:1397:1397) (1379:1379:1379)) - (PORT ena (1301:1301:1301) (1268:1268:1268)) + (PORT clrn (1387:1387:1387) (1366:1366:1366)) + (PORT ena (917:917:917) (912:912:912)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -51952,9 +51682,75 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\~12) (DELAY (ABSOLUTE - (PORT dataa (516:516:516) (499:499:499)) - (PORT datab (451:451:451) (499:499:499)) - (PORT datad (334:334:334) (372:372:372)) + (PORT dataa (264:264:264) (351:351:351)) + (PORT datab (253:253:253) (331:331:331)) + (PORT datac (234:234:234) (312:312:312)) + (PORT datad (236:236:236) (303:303:303)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~14) + (DELAY + (ABSOLUTE + (PORT dataa (192:192:192) (232:232:232)) + (PORT datab (260:260:260) (340:340:340)) + (PORT datac (157:157:157) (186:186:186)) + (PORT datad (236:236:236) (302:302:302)) + (IOPATH dataa combout (265:265:265) (273:273:273)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~24) + (DELAY + (ABSOLUTE + (PORT dataa (457:457:457) (502:502:502)) + (PORT datab (223:223:223) (291:291:291)) + (PORT datac (589:589:589) (627:627:627)) + (PORT datad (298:298:298) (299:299:299)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|shiftreg\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1351:1351:1351) (1368:1368:1368)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1387:1387:1387) (1366:1366:1366)) + (PORT ena (917:917:917) (912:912:912)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~11) + (DELAY + (ABSOLUTE + (PORT dataa (341:341:341) (353:353:353)) + (PORT datab (584:584:584) (619:619:619)) + (PORT datad (342:342:342) (373:373:373)) (IOPATH dataa combout (318:318:318) (307:307:307)) (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -51966,10 +51762,10 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[5\]) (DELAY (ABSOLUTE - (PORT clk (1351:1351:1351) (1367:1367:1367)) + (PORT clk (1351:1351:1351) (1369:1369:1369)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1397:1397:1397) (1377:1377:1377)) - (PORT sload (1099:1099:1099) (1160:1160:1160)) + (PORT clrn (1387:1387:1387) (1367:1367:1367)) + (PORT sload (799:799:799) (908:908:908)) (PORT ena (735:735:735) (734:734:734)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) @@ -51984,12 +51780,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~9) + (INSTANCE ula_\|i2c_loader_\|shiftreg\~8) (DELAY (ABSOLUTE - (PORT datab (592:592:592) (640:640:640)) - (PORT datac (816:816:816) (848:848:848)) - (PORT datad (181:181:181) (203:203:203)) + (PORT datab (386:386:386) (425:425:425)) + (PORT datac (593:593:593) (633:633:633)) + (PORT datad (179:179:179) (201:201:201)) (IOPATH datab combout (308:308:308) (300:300:300)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -52001,11 +51797,11 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[6\]) (DELAY (ABSOLUTE - (PORT clk (1351:1351:1351) (1369:1369:1369)) + (PORT clk (1351:1351:1351) (1368:1368:1368)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1397:1397:1397) (1379:1379:1379)) - (PORT sclr (1021:1021:1021) (1080:1080:1080)) - (PORT ena (1112:1112:1112) (1084:1084:1084)) + (PORT clrn (1387:1387:1387) (1366:1366:1366)) + (PORT sclr (864:864:864) (955:955:955)) + (PORT ena (917:917:917) (912:912:912)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -52021,8 +51817,8 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[7\]\~5) (DELAY (ABSOLUTE - (PORT datac (811:811:811) (843:843:843)) - (PORT datad (199:199:199) (256:256:256)) + (PORT datac (592:592:592) (633:633:633)) + (PORT datad (200:200:200) (257:257:257)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -52033,11 +51829,11 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[7\]) (DELAY (ABSOLUTE - (PORT clk (1351:1351:1351) (1369:1369:1369)) + (PORT clk (1351:1351:1351) (1368:1368:1368)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1397:1397:1397) (1379:1379:1379)) - (PORT sclr (1021:1021:1021) (1080:1080:1080)) - (PORT ena (1279:1279:1279) (1235:1235:1235)) + (PORT clrn (1387:1387:1387) (1366:1366:1366)) + (PORT sclr (864:864:864) (955:955:955)) + (PORT ena (842:842:842) (823:823:823)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -52053,13 +51849,13 @@ (INSTANCE ula_\|i2c_loader_\|sda_out\~0) (DELAY (ABSOLUTE - (PORT dataa (633:633:633) (669:669:669)) - (PORT datab (384:384:384) (437:437:437)) - (PORT datac (523:523:523) (541:541:541)) - (PORT datad (357:357:357) (391:391:391)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT dataa (548:548:548) (568:568:568)) + (PORT datab (550:550:550) (583:583:583)) + (PORT datac (589:589:589) (625:625:625)) + (PORT datad (237:237:237) (307:307:307)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -52069,10 +51865,10 @@ (INSTANCE ula_\|i2c_loader_\|sda_out\~1) (DELAY (ABSOLUTE - (PORT dataa (508:508:508) (497:497:497)) - (PORT datab (286:286:286) (385:385:385)) - (PORT datac (324:324:324) (326:326:326)) - (PORT datad (473:473:473) (451:451:451)) + (PORT dataa (524:524:524) (514:514:514)) + (PORT datab (618:618:618) (655:655:655)) + (PORT datac (157:157:157) (188:188:188)) + (PORT datad (457:457:457) (435:435:435)) (IOPATH dataa combout (307:307:307) (280:280:280)) (IOPATH datab combout (308:308:308) (281:281:281)) (IOPATH datac combout (220:220:220) (216:216:216)) @@ -52085,13 +51881,13 @@ (INSTANCE ula_\|i2c_loader_\|sda_out\~2) (DELAY (ABSOLUTE - (PORT dataa (232:232:232) (308:308:308)) - (PORT datab (288:288:288) (386:386:386)) - (PORT datac (232:232:232) (308:308:308)) - (PORT datad (166:166:166) (188:188:188)) + (PORT dataa (231:231:231) (309:309:309)) + (PORT datab (582:582:582) (620:620:620)) + (PORT datac (587:587:587) (622:622:622)) + (PORT datad (166:166:166) (190:190:190)) (IOPATH dataa combout (329:329:329) (332:332:332)) (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -52101,13 +51897,13 @@ (INSTANCE ula_\|i2c_loader_\|sda_out\~3) (DELAY (ABSOLUTE - (PORT dataa (233:233:233) (312:312:312)) - (PORT datab (286:286:286) (382:382:382)) - (PORT datac (233:233:233) (308:308:308)) - (PORT datad (165:165:165) (188:188:188)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (319:319:319) (307:307:307)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT dataa (232:232:232) (310:310:310)) + (PORT datab (586:586:586) (624:624:624)) + (PORT datac (590:590:590) (626:626:626)) + (PORT datad (166:166:166) (188:188:188)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -52117,12 +51913,12 @@ (INSTANCE ula_\|i2c_loader_\|sda_out\~4) (DELAY (ABSOLUTE - (PORT dataa (616:616:616) (657:657:657)) - (PORT datab (746:746:746) (747:747:747)) - (PORT datac (157:157:157) (187:187:187)) + (PORT dataa (201:201:201) (248:248:248)) + (PORT datab (605:605:605) (618:618:618)) + (PORT datac (157:157:157) (188:188:188)) (PORT datad (161:161:161) (182:182:182)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH dataa combout (267:267:267) (273:273:273)) + (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -52134,9 +51930,9 @@ (DELAY (ABSOLUTE (PORT clk (1307:1307:1307) (1321:1321:1321)) - (PORT d (612:612:612) (666:666:666)) - (PORT aload (1521:1521:1521) (1568:1568:1568)) - (PORT ena (1129:1129:1129) (1199:1199:1199)) + (PORT d (616:616:616) (667:667:667)) + (PORT aload (1511:1511:1511) (1556:1556:1556)) + (PORT ena (772:772:772) (798:798:798)) (IOPATH (posedge clk) q (549:549:549) (552:552:552)) (IOPATH (posedge aload) q (455:455:455) (458:458:458)) ) @@ -52162,9 +51958,9 @@ (INSTANCE ula_\|i2s_intf_\|mclk_r\~_Duplicate_1) (DELAY (ABSOLUTE - (PORT clk (1675:1675:1675) (1695:1695:1695)) + (PORT clk (1706:1706:1706) (1726:1726:1726)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1392:1392:1392) (1374:1374:1374)) + (PORT clrn (1391:1391:1391) (1369:1369:1369)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -52179,8 +51975,8 @@ (DELAY (ABSOLUTE (PORT clk (1332:1332:1332) (1349:1349:1349)) - (PORT d (2140:2140:2140) (2106:2106:2106)) - (PORT clrn (1565:1565:1565) (1601:1601:1601)) + (PORT d (1114:1114:1114) (1175:1175:1175)) + (PORT clrn (1555:1555:1555) (1589:1589:1589)) (IOPATH (posedge clk) q (524:524:524) (534:534:534)) (IOPATH (negedge clrn) q (642:642:642) (652:652:652)) ) @@ -52195,7 +51991,7 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~1) (DELAY (ABSOLUTE - (PORT dataa (636:636:636) (678:678:678)) + (PORT dataa (374:374:374) (427:427:427)) (IOPATH dataa cout (376:376:376) (275:275:275)) ) ) @@ -52205,9 +52001,9 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~2) (DELAY (ABSOLUTE - (PORT datab (228:228:228) (301:301:301)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datab cout (385:385:385) (280:280:280)) + (PORT dataa (394:394:394) (438:438:438)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) (IOPATH cin cout (50:50:50) (50:50:50)) @@ -52219,8 +52015,8 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\~2) (DELAY (ABSOLUTE - (PORT dataa (209:209:209) (250:250:250)) - (PORT datac (158:158:158) (190:190:190)) + (PORT dataa (416:416:416) (439:439:439)) + (PORT datac (295:295:295) (308:308:308)) (IOPATH dataa combout (318:318:318) (327:327:327)) (IOPATH datac combout (220:220:220) (216:216:216)) ) @@ -52231,9 +52027,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[1\]) (DELAY (ABSOLUTE - (PORT clk (1674:1674:1674) (1694:1694:1694)) + (PORT clk (1714:1714:1714) (1735:1735:1735)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1391:1391:1391) (1373:1373:1373)) + (PORT clrn (1390:1390:1390) (1369:1369:1369)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -52247,9 +52043,9 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~4) (DELAY (ABSOLUTE - (PORT dataa (370:370:370) (423:423:423)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH dataa cout (376:376:376) (275:275:275)) + (PORT datab (360:360:360) (411:411:411)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) (IOPATH cin cout (50:50:50) (50:50:50)) @@ -52261,8 +52057,8 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[2\]\~8) (DELAY (ABSOLUTE - (PORT datad (304:304:304) (309:309:309)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (PORT datac (325:325:325) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) ) ) ) @@ -52271,9 +52067,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[2\]) (DELAY (ABSOLUTE - (PORT clk (1674:1674:1674) (1694:1694:1694)) + (PORT clk (1714:1714:1714) (1735:1735:1735)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1391:1391:1391) (1373:1373:1373)) + (PORT clrn (1390:1390:1390) (1369:1369:1369)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -52287,7 +52083,7 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~6) (DELAY (ABSOLUTE - (PORT datab (365:365:365) (408:408:408)) + (PORT datab (358:358:358) (409:409:409)) (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -52301,8 +52097,8 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[3\]\~7) (DELAY (ABSOLUTE - (PORT datac (324:324:324) (326:326:326)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT datad (518:518:518) (506:506:506)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) @@ -52311,9 +52107,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[3\]) (DELAY (ABSOLUTE - (PORT clk (1674:1674:1674) (1695:1695:1695)) + (PORT clk (1714:1714:1714) (1735:1735:1735)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1392:1392:1392) (1374:1374:1374)) + (PORT clrn (1390:1390:1390) (1369:1369:1369)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -52327,9 +52123,9 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~8) (DELAY (ABSOLUTE - (PORT datab (227:227:227) (301:301:301)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datab cout (385:385:385) (280:280:280)) + (PORT dataa (371:371:371) (418:418:418)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) (IOPATH cin cout (50:50:50) (50:50:50)) @@ -52341,10 +52137,10 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\~1) (DELAY (ABSOLUTE - (PORT dataa (211:211:211) (254:254:254)) - (PORT datac (156:156:156) (185:185:185)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT datac (378:378:378) (401:401:401)) + (PORT datad (295:295:295) (295:295:295)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) @@ -52353,9 +52149,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[4\]) (DELAY (ABSOLUTE - (PORT clk (1674:1674:1674) (1694:1694:1694)) + (PORT clk (1714:1714:1714) (1735:1735:1735)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1391:1391:1391) (1373:1373:1373)) + (PORT clrn (1390:1390:1390) (1369:1369:1369)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -52369,9 +52165,9 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~10) (DELAY (ABSOLUTE - (PORT datab (229:229:229) (301:301:301)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datab cout (385:385:385) (280:280:280)) + (PORT dataa (369:369:369) (415:415:415)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) (IOPATH cin cout (50:50:50) (50:50:50)) @@ -52383,7 +52179,7 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[5\]\~6) (DELAY (ABSOLUTE - (PORT datad (160:160:160) (182:182:182)) + (PORT datad (316:316:316) (317:317:317)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -52393,9 +52189,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[5\]) (DELAY (ABSOLUTE - (PORT clk (1674:1674:1674) (1694:1694:1694)) + (PORT clk (1714:1714:1714) (1735:1735:1735)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1391:1391:1391) (1373:1373:1373)) + (PORT clrn (1390:1390:1390) (1369:1369:1369)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -52409,12 +52205,12 @@ (INSTANCE ula_\|i2s_intf_\|Equal0\~1) (DELAY (ABSOLUTE - (PORT dataa (373:373:373) (424:424:424)) - (PORT datab (228:228:228) (302:302:302)) - (PORT datac (340:340:340) (382:382:382)) - (PORT datad (205:205:205) (268:268:268)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) + (PORT dataa (372:372:372) (419:419:419)) + (PORT datab (360:360:360) (412:412:412)) + (PORT datac (328:328:328) (380:380:380)) + (PORT datad (345:345:345) (376:376:376)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -52425,7 +52221,7 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~12) (DELAY (ABSOLUTE - (PORT dataa (396:396:396) (438:438:438)) + (PORT dataa (396:396:396) (440:440:440)) (IOPATH dataa combout (318:318:318) (327:327:327)) (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -52439,8 +52235,8 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[6\]\~5) (DELAY (ABSOLUTE - (PORT datad (316:316:316) (315:315:315)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (PORT datac (296:296:296) (304:304:304)) + (IOPATH datac combout (218:218:218) (215:215:215)) ) ) ) @@ -52449,9 +52245,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[6\]) (DELAY (ABSOLUTE - (PORT clk (1674:1674:1674) (1695:1695:1695)) + (PORT clk (1714:1714:1714) (1735:1735:1735)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1392:1392:1392) (1374:1374:1374)) + (PORT clrn (1390:1390:1390) (1369:1369:1369)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -52465,9 +52261,9 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~14) (DELAY (ABSOLUTE - (PORT dataa (411:411:411) (446:446:446)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH dataa cout (376:376:376) (275:275:275)) + (PORT datab (229:229:229) (300:300:300)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) (IOPATH cin cout (50:50:50) (50:50:50)) @@ -52479,8 +52275,8 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[7\]\~4) (DELAY (ABSOLUTE - (PORT datad (309:309:309) (315:315:315)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (PORT datac (158:158:158) (190:190:190)) + (IOPATH datac combout (218:218:218) (215:215:215)) ) ) ) @@ -52489,9 +52285,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[7\]) (DELAY (ABSOLUTE - (PORT clk (1674:1674:1674) (1694:1694:1694)) + (PORT clk (1706:1706:1706) (1726:1726:1726)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1391:1391:1391) (1373:1373:1373)) + (PORT clrn (1391:1391:1391) (1369:1369:1369)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -52505,9 +52301,9 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~16) (DELAY (ABSOLUTE - (PORT dataa (371:371:371) (416:416:416)) - (IOPATH dataa combout (307:307:307) (306:306:306)) - (IOPATH dataa cout (376:376:376) (275:275:275)) + (PORT datab (226:226:226) (299:299:299)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) (IOPATH cin cout (50:50:50) (50:50:50)) @@ -52519,8 +52315,8 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\~0) (DELAY (ABSOLUTE - (PORT datab (353:353:353) (353:353:353)) - (PORT datac (357:357:357) (365:365:365)) + (PORT datab (182:182:182) (214:214:214)) + (PORT datac (174:174:174) (206:206:206)) (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datac combout (218:218:218) (215:215:215)) ) @@ -52531,9 +52327,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[8\]) (DELAY (ABSOLUTE - (PORT clk (1674:1674:1674) (1695:1695:1695)) + (PORT clk (1706:1706:1706) (1726:1726:1726)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1392:1392:1392) (1374:1374:1374)) + (PORT clrn (1391:1391:1391) (1369:1369:1369)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -52547,8 +52343,8 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~18) (DELAY (ABSOLUTE - (PORT datad (353:353:353) (394:394:394)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (PORT datab (231:231:231) (303:303:303)) + (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH cin combout (408:408:408) (387:387:387)) ) ) @@ -52558,8 +52354,8 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[9\]\~3) (DELAY (ABSOLUTE - (PORT datad (314:314:314) (314:314:314)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (PORT datac (157:157:157) (189:189:189)) + (IOPATH datac combout (218:218:218) (215:215:215)) ) ) ) @@ -52568,9 +52364,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[9\]) (DELAY (ABSOLUTE - (PORT clk (1674:1674:1674) (1695:1695:1695)) + (PORT clk (1706:1706:1706) (1726:1726:1726)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1392:1392:1392) (1374:1374:1374)) + (PORT clrn (1391:1391:1391) (1369:1369:1369)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -52584,12 +52380,12 @@ (INSTANCE ula_\|i2s_intf_\|Equal0\~0) (DELAY (ABSOLUTE - (PORT dataa (372:372:372) (418:418:418)) - (PORT datab (394:394:394) (432:432:432)) - (PORT datac (361:361:361) (405:405:405)) - (PORT datad (361:361:361) (398:398:398)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) + (PORT dataa (393:393:393) (436:436:436)) + (PORT datab (227:227:227) (301:301:301)) + (PORT datac (199:199:199) (270:270:270)) + (PORT datad (202:202:202) (263:263:263)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -52600,35 +52396,25 @@ (INSTANCE ula_\|i2s_intf_\|Equal0\~2) (DELAY (ABSOLUTE - (PORT dataa (182:182:182) (219:219:219)) - (PORT datab (225:225:225) (297:297:297)) - (PORT datac (606:606:606) (644:644:644)) - (PORT datad (162:162:162) (183:183:183)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (295:295:295) (294:294:294)) + (PORT dataa (396:396:396) (442:442:442)) + (PORT datab (185:185:185) (219:219:219)) + (PORT datac (346:346:346) (395:395:395)) + (PORT datad (161:161:161) (183:183:183)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|lrclk_r\~_Duplicate_2feeder) - (DELAY - (ABSOLUTE - (PORT datad (180:180:180) (203:203:203)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|i2s_intf_\|lrclk_r\~_Duplicate_2) (DELAY (ABSOLUTE - (PORT clk (1347:1347:1347) (1364:1364:1364)) + (PORT clk (1705:1705:1705) (1725:1725:1725)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1393:1393:1393) (1374:1374:1374)) + (PORT clrn (1390:1390:1390) (1368:1368:1368)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -52642,10 +52428,9 @@ (INSTANCE ula_\|i2s_intf_\|lrclk_r\~0) (DELAY (ABSOLUTE - (PORT datab (826:826:826) (840:840:840)) - (PORT datad (213:213:213) (274:274:274)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (PORT datab (715:715:715) (753:753:753)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) ) ) ) @@ -52655,8 +52440,8 @@ (DELAY (ABSOLUTE (PORT clk (1330:1330:1330) (1348:1348:1348)) - (PORT d (2112:2112:2112) (2168:2168:2168)) - (PORT clrn (1563:1563:1563) (1599:1599:1599)) + (PORT d (1251:1251:1251) (1273:1273:1273)) + (PORT clrn (1553:1553:1553) (1587:1587:1587)) (IOPATH (posedge clk) q (524:524:524) (534:534:534)) (IOPATH (negedge clrn) q (642:642:642) (652:652:652)) ) @@ -52672,8 +52457,8 @@ (DELAY (ABSOLUTE (PORT clk (1331:1331:1331) (1348:1348:1348)) - (PORT d (2331:2331:2331) (2378:2378:2378)) - (PORT clrn (1564:1564:1564) (1600:1600:1600)) + (PORT d (1248:1248:1248) (1275:1275:1275)) + (PORT clrn (1554:1554:1554) (1588:1588:1588)) (IOPATH (posedge clk) q (524:524:524) (534:534:534)) (IOPATH (negedge clrn) q (642:642:642) (652:652:652)) ) @@ -52694,14 +52479,24 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|bclk_r\~_Duplicate_1feeder) + (DELAY + (ABSOLUTE + (PORT datad (177:177:177) (199:199:199)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|i2s_intf_\|bclk_r\~_Duplicate_1) (DELAY (ABSOLUTE - (PORT clk (1348:1348:1348) (1365:1365:1365)) + (PORT clk (1354:1354:1354) (1371:1371:1371)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1394:1394:1394) (1375:1375:1375)) + (PORT clrn (1390:1390:1390) (1369:1369:1369)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -52715,10 +52510,10 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[4\]\~15) (DELAY (ABSOLUTE - (PORT datab (208:208:208) (255:255:255)) - (PORT datac (805:805:805) (797:797:797)) - (PORT datad (220:220:220) (284:284:284)) - (IOPATH datab combout (319:319:319) (324:324:324)) + (PORT dataa (252:252:252) (338:338:338)) + (PORT datac (554:554:554) (552:552:552)) + (PORT datad (186:186:186) (209:209:209)) + (IOPATH dataa combout (287:287:287) (280:280:280)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -52729,12 +52524,12 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[0\]) (DELAY (ABSOLUTE - (PORT clk (1348:1348:1348) (1365:1365:1365)) + (PORT clk (1354:1354:1354) (1371:1371:1371)) (PORT d (67:67:67) (78:78:78)) - (PORT asdata (2512:2512:2512) (2492:2492:2492)) - (PORT clrn (1394:1394:1394) (1375:1375:1375)) - (PORT sload (1349:1349:1349) (1372:1372:1372)) - (PORT ena (716:716:716) (714:714:714)) + (PORT asdata (512:512:512) (549:549:549)) + (PORT clrn (1390:1390:1390) (1369:1369:1369)) + (PORT sload (1104:1104:1104) (1133:1133:1133)) + (PORT ena (721:721:721) (723:723:723)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -52751,9 +52546,9 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[1\]\~7) (DELAY (ABSOLUTE - (PORT datab (226:226:226) (297:297:297)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datab cout (385:385:385) (280:280:280)) + (PORT dataa (398:398:398) (441:441:441)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) (IOPATH cin cout (50:50:50) (50:50:50)) @@ -52765,12 +52560,12 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[1\]) (DELAY (ABSOLUTE - (PORT clk (1348:1348:1348) (1365:1365:1365)) + (PORT clk (1354:1354:1354) (1371:1371:1371)) (PORT d (67:67:67) (78:78:78)) - (PORT asdata (2511:2511:2511) (2491:2491:2491)) - (PORT clrn (1394:1394:1394) (1375:1375:1375)) - (PORT sload (1349:1349:1349) (1372:1372:1372)) - (PORT ena (716:716:716) (714:714:714)) + (PORT asdata (511:511:511) (549:549:549)) + (PORT clrn (1390:1390:1390) (1369:1369:1369)) + (PORT sload (1104:1104:1104) (1133:1133:1133)) + (PORT ena (721:721:721) (723:723:723)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -52801,12 +52596,12 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[2\]) (DELAY (ABSOLUTE - (PORT clk (1348:1348:1348) (1365:1365:1365)) + (PORT clk (1354:1354:1354) (1371:1371:1371)) (PORT d (67:67:67) (78:78:78)) - (PORT asdata (2510:2510:2510) (2491:2491:2491)) - (PORT clrn (1394:1394:1394) (1375:1375:1375)) - (PORT sload (1349:1349:1349) (1372:1372:1372)) - (PORT ena (716:716:716) (714:714:714)) + (PORT asdata (511:511:511) (547:547:547)) + (PORT clrn (1390:1390:1390) (1369:1369:1369)) + (PORT sload (1104:1104:1104) (1133:1133:1133)) + (PORT ena (721:721:721) (723:723:723)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -52823,7 +52618,7 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[3\]\~11) (DELAY (ABSOLUTE - (PORT dataa (230:230:230) (307:307:307)) + (PORT dataa (229:229:229) (304:304:304)) (IOPATH dataa combout (329:329:329) (332:332:332)) (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -52837,12 +52632,45 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[3\]) (DELAY (ABSOLUTE - (PORT clk (1348:1348:1348) (1365:1365:1365)) + (PORT clk (1354:1354:1354) (1371:1371:1371)) (PORT d (67:67:67) (78:78:78)) - (PORT asdata (2510:2510:2510) (2490:2490:2490)) - (PORT clrn (1394:1394:1394) (1375:1375:1375)) - (PORT sload (1349:1349:1349) (1372:1372:1372)) - (PORT ena (716:716:716) (714:714:714)) + (PORT asdata (511:511:511) (548:548:548)) + (PORT clrn (1390:1390:1390) (1369:1369:1369)) + (PORT sload (1104:1104:1104) (1133:1133:1133)) + (PORT ena (721:721:721) (723:723:723)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD sload (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|bitcount\[4\]\~13) + (DELAY + (ABSOLUTE + (PORT datab (241:241:241) (320:320:320)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH cin combout (408:408:408) (387:387:387)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|bitcount\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1354:1354:1354) (1371:1371:1371)) + (PORT d (67:67:67) (78:78:78)) + (PORT asdata (512:512:512) (548:548:548)) + (PORT clrn (1390:1390:1390) (1369:1369:1369)) + (PORT sload (1104:1104:1104) (1133:1133:1133)) + (PORT ena (721:721:721) (723:723:723)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -52859,10 +52687,10 @@ (INSTANCE ula_\|i2s_intf_\|LessThan0\~0) (DELAY (ABSOLUTE - (PORT dataa (229:229:229) (306:306:306)) + (PORT dataa (401:401:401) (445:445:445)) (PORT datab (229:229:229) (302:302:302)) - (PORT datac (201:201:201) (272:272:272)) - (PORT datad (205:205:205) (267:267:267)) + (PORT datac (202:202:202) (273:273:273)) + (PORT datad (206:206:206) (269:269:269)) (IOPATH dataa combout (300:300:300) (323:323:323)) (IOPATH datab combout (309:309:309) (328:328:328)) (IOPATH datac combout (220:220:220) (215:215:215)) @@ -52872,35 +52700,49 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|bitcount\[4\]\~13) + (INSTANCE ula_\|i2s_intf_\|shiftreg\[4\]\~1) (DELAY (ABSOLUTE - (PORT datab (241:241:241) (318:318:318)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH cin combout (408:408:408) (387:387:387)) + (PORT dataa (407:407:407) (446:446:446)) + (PORT datab (364:364:364) (370:370:370)) + (PORT datac (213:213:213) (293:293:293)) + (PORT datad (173:173:173) (202:202:202)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add2\~18) + (DELAY + (ABSOLUTE + (PORT dataa (433:433:433) (474:474:474)) + (PORT datab (355:355:355) (372:372:372)) + (PORT datad (200:200:200) (232:232:232)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|bitcount\[4\]) + (INSTANCE ula_\|i2s_intf_\|bdivider\[0\]) (DELAY (ABSOLUTE - (PORT clk (1348:1348:1348) (1365:1365:1365)) + (PORT clk (1354:1354:1354) (1371:1371:1371)) (PORT d (67:67:67) (78:78:78)) - (PORT asdata (2509:2509:2509) (2490:2490:2490)) - (PORT clrn (1394:1394:1394) (1375:1375:1375)) - (PORT sload (1349:1349:1349) (1372:1372:1372)) - (PORT ena (716:716:716) (714:714:714)) + (PORT clrn (1390:1390:1390) (1369:1369:1369)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) ) (TIMINGCHECK (HOLD d (posedge clk) (144:144:144)) - (HOLD sload (posedge clk) (144:144:144)) - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) ) ) (CELL @@ -52908,7 +52750,7 @@ (INSTANCE ula_\|i2s_intf_\|Add2\~7) (DELAY (ABSOLUTE - (PORT dataa (427:427:427) (477:477:477)) + (PORT dataa (262:262:262) (344:344:344)) (IOPATH dataa cout (376:376:376) (275:275:275)) ) ) @@ -52918,7 +52760,7 @@ (INSTANCE ula_\|i2s_intf_\|Add2\~8) (DELAY (ABSOLUTE - (PORT dataa (231:231:231) (308:308:308)) + (PORT dataa (230:230:230) (307:307:307)) (IOPATH dataa combout (329:329:329) (332:332:332)) (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -52932,12 +52774,12 @@ (INSTANCE ula_\|i2s_intf_\|Add2\~20) (DELAY (ABSOLUTE - (PORT dataa (429:429:429) (479:479:479)) - (PORT datab (826:826:826) (840:840:840)) - (PORT datac (184:184:184) (220:220:220)) - (PORT datad (160:160:160) (182:182:182)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) + (PORT dataa (265:265:265) (347:347:347)) + (PORT datab (184:184:184) (217:217:217)) + (PORT datac (398:398:398) (444:444:444)) + (PORT datad (197:197:197) (228:228:228)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -52948,9 +52790,9 @@ (INSTANCE ula_\|i2s_intf_\|bdivider\[1\]) (DELAY (ABSOLUTE - (PORT clk (1347:1347:1347) (1364:1364:1364)) + (PORT clk (1354:1354:1354) (1371:1371:1371)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1393:1393:1393) (1374:1374:1374)) + (PORT clrn (1390:1390:1390) (1369:1369:1369)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -52964,7 +52806,7 @@ (INSTANCE ula_\|i2s_intf_\|Add2\~10) (DELAY (ABSOLUTE - (PORT dataa (373:373:373) (418:418:418)) + (PORT dataa (230:230:230) (305:305:305)) (IOPATH dataa combout (318:318:318) (327:327:327)) (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -52978,12 +52820,12 @@ (INSTANCE ula_\|i2s_intf_\|Add2\~17) (DELAY (ABSOLUTE - (PORT dataa (207:207:207) (259:259:259)) - (PORT datab (208:208:208) (257:257:257)) - (PORT datac (805:805:805) (799:799:799)) - (PORT datad (315:315:315) (317:317:317)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) + (PORT dataa (437:437:437) (482:482:482)) + (PORT datab (209:209:209) (248:248:248)) + (PORT datac (329:329:329) (347:347:347)) + (PORT datad (161:161:161) (183:183:183)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (273:273:273) (275:275:275)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -52994,9 +52836,9 @@ (INSTANCE ula_\|i2s_intf_\|bdivider\[2\]) (DELAY (ABSOLUTE - (PORT clk (1348:1348:1348) (1365:1365:1365)) + (PORT clk (1354:1354:1354) (1371:1371:1371)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1394:1394:1394) (1375:1375:1375)) + (PORT clrn (1390:1390:1390) (1369:1369:1369)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -53010,7 +52852,7 @@ (INSTANCE ula_\|i2s_intf_\|Add2\~12) (DELAY (ABSOLUTE - (PORT datab (229:229:229) (304:304:304)) + (PORT datab (227:227:227) (299:299:299)) (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -53024,12 +52866,12 @@ (INSTANCE ula_\|i2s_intf_\|Add2\~19) (DELAY (ABSOLUTE - (PORT dataa (430:430:430) (479:479:479)) - (PORT datab (827:827:827) (841:841:841)) - (PORT datac (185:185:185) (221:221:221)) - (PORT datad (161:161:161) (182:182:182)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (295:295:295) (285:285:285)) + (PORT dataa (264:264:264) (347:347:347)) + (PORT datab (182:182:182) (215:215:215)) + (PORT datac (389:389:389) (428:428:428)) + (PORT datad (200:200:200) (232:232:232)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -53040,9 +52882,9 @@ (INSTANCE ula_\|i2s_intf_\|bdivider\[3\]) (DELAY (ABSOLUTE - (PORT clk (1347:1347:1347) (1364:1364:1364)) + (PORT clk (1354:1354:1354) (1371:1371:1371)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1393:1393:1393) (1374:1374:1374)) + (PORT clrn (1390:1390:1390) (1369:1369:1369)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -53056,7 +52898,7 @@ (INSTANCE ula_\|i2s_intf_\|Add2\~14) (DELAY (ABSOLUTE - (PORT datad (336:336:336) (373:373:373)) + (PORT datad (206:206:206) (269:269:269)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) ) @@ -53067,12 +52909,12 @@ (INSTANCE ula_\|i2s_intf_\|Add2\~16) (DELAY (ABSOLUTE - (PORT dataa (208:208:208) (260:260:260)) - (PORT datab (208:208:208) (260:260:260)) - (PORT datac (805:805:805) (800:800:800)) - (PORT datad (316:316:316) (317:317:317)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (336:336:336) (337:337:337)) + (PORT dataa (438:438:438) (483:483:483)) + (PORT datab (209:209:209) (249:249:249)) + (PORT datac (329:329:329) (347:347:347)) + (PORT datad (161:161:161) (182:182:182)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (273:273:273) (275:275:275)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -53083,9 +52925,9 @@ (INSTANCE ula_\|i2s_intf_\|bdivider\[4\]) (DELAY (ABSOLUTE - (PORT clk (1348:1348:1348) (1365:1365:1365)) + (PORT clk (1354:1354:1354) (1371:1371:1371)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1394:1394:1394) (1375:1375:1375)) + (PORT clrn (1390:1390:1390) (1369:1369:1369)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -53099,72 +52941,25 @@ (INSTANCE ula_\|i2s_intf_\|Equal1\~0) (DELAY (ABSOLUTE - (PORT dataa (231:231:231) (309:309:309)) - (PORT datab (229:229:229) (303:303:303)) - (PORT datac (345:345:345) (385:385:385)) - (PORT datad (335:335:335) (371:371:371)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT dataa (230:230:230) (307:307:307)) + (PORT datab (228:228:228) (299:299:299)) + (PORT datac (202:202:202) (273:273:273)) + (PORT datad (205:205:205) (267:267:267)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[4\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (242:242:242) (315:315:315)) - (PORT datab (195:195:195) (237:237:237)) - (PORT datac (215:215:215) (292:292:292)) - (PORT datad (350:350:350) (354:354:354)) - (IOPATH dataa combout (272:272:272) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~18) - (DELAY - (ABSOLUTE - (PORT dataa (834:834:834) (831:831:831)) - (PORT datab (208:208:208) (258:258:258)) - (PORT datad (352:352:352) (355:355:355)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|bdivider\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1348:1348:1348) (1365:1365:1365)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1394:1394:1394) (1375:1375:1375)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2s_intf_\|Equal1\~1) (DELAY (ABSOLUTE - (PORT datac (358:358:358) (401:401:401)) - (PORT datad (348:348:348) (351:351:351)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT datab (223:223:223) (262:262:262)) + (PORT datad (238:238:238) (309:309:309)) + (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -53174,12 +52969,12 @@ (INSTANCE ula_\|i2s_intf_\|bclk_r\~0) (DELAY (ABSOLUTE - (PORT datab (195:195:195) (237:237:237)) - (PORT datac (213:213:213) (291:291:291)) - (PORT datad (217:217:217) (281:281:281)) - (IOPATH datab combout (308:308:308) (300:300:300)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (PORT dataa (249:249:249) (335:335:335)) + (PORT datab (197:197:197) (234:234:234)) + (PORT datac (214:214:214) (293:293:293)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) ) ) ) @@ -53188,12 +52983,13 @@ (INSTANCE ula_\|i2s_intf_\|bclk_r\~1) (DELAY (ABSOLUTE - (PORT dataa (207:207:207) (258:258:258)) - (PORT datab (183:183:183) (216:216:216)) - (PORT datad (799:799:799) (786:786:786)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (312:312:312) (325:325:325)) + (PORT dataa (350:350:350) (361:361:361)) + (PORT datab (582:582:582) (579:579:579)) + (PORT datac (221:221:221) (304:304:304)) + (PORT datad (159:159:159) (179:179:179)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -53204,8 +53000,8 @@ (DELAY (ABSOLUTE (PORT clk (1330:1330:1330) (1347:1347:1347)) - (PORT d (2095:2095:2095) (2177:2177:2177)) - (PORT clrn (1562:1562:1562) (1599:1599:1599)) + (PORT d (1407:1407:1407) (1454:1454:1454)) + (PORT clrn (1552:1552:1552) (1587:1587:1587)) (IOPATH (posedge clk) q (524:524:524) (534:534:534)) (IOPATH (negedge clrn) q (642:642:642) (652:652:652)) ) @@ -53215,27 +53011,17 @@ (HOLD d (posedge clk) (86:86:86)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|pcm_outl\[13\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (795:795:795) (814:814:814)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|always0\~2) (DELAY (ABSOLUTE - (PORT dataa (1624:1624:1624) (1662:1662:1662)) - (PORT datab (1477:1477:1477) (1531:1531:1531)) - (PORT datac (1100:1100:1100) (1115:1115:1115)) - (IOPATH dataa combout (307:307:307) (280:280:280)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT dataa (538:538:538) (542:542:542)) + (PORT datab (2585:2585:2585) (2645:2645:2645)) + (PORT datad (564:564:564) (563:563:563)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) @@ -53244,12 +53030,12 @@ (INSTANCE ula_\|always0\~3) (DELAY (ABSOLUTE - (PORT dataa (634:634:634) (680:680:680)) - (PORT datab (1157:1157:1157) (1194:1194:1194)) - (PORT datac (1107:1107:1107) (1125:1125:1125)) - (PORT datad (160:160:160) (182:182:182)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (275:275:275) (275:275:275)) + (PORT dataa (224:224:224) (273:273:273)) + (PORT datab (889:889:889) (910:910:910)) + (PORT datac (2554:2554:2554) (2614:2614:2614)) + (PORT datad (488:488:488) (471:471:471)) + (IOPATH dataa combout (273:273:273) (269:269:269)) + (IOPATH datab combout (295:295:295) (294:294:294)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -53257,12 +53043,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|pcm_outl\[13\]) + (INSTANCE ula_\|pcm_outl\[14\]) (DELAY (ABSOLUTE - (PORT clk (1344:1344:1344) (1362:1362:1362)) + (PORT clk (1339:1339:1339) (1357:1357:1357)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (1849:1849:1849) (1846:1846:1846)) + (PORT ena (1776:1776:1776) (1721:1721:1721)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -53276,12 +53062,12 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[0\]\~19) (DELAY (ABSOLUTE - (PORT dataa (206:206:206) (254:254:254)) - (PORT datab (194:194:194) (234:234:234)) - (PORT datac (215:215:215) (292:292:292)) - (PORT datad (219:219:219) (283:283:283)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datab combout (295:295:295) (300:300:300)) + (PORT dataa (350:350:350) (362:362:362)) + (PORT datab (242:242:242) (321:321:321)) + (PORT datac (224:224:224) (306:306:306)) + (PORT datad (172:172:172) (201:201:201)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -53301,11 +53087,11 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[0\]\~20) (DELAY (ABSOLUTE - (PORT dataa (1260:1260:1260) (1257:1257:1257)) - (PORT datab (1218:1218:1218) (1254:1254:1254)) - (PORT datad (705:705:705) (672:672:672)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (295:295:295) (300:300:300)) + (PORT dataa (435:435:435) (479:479:479)) + (PORT datab (318:318:318) (330:330:330)) + (PORT datad (727:727:727) (702:702:702)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (300:300:300) (312:312:312)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -53316,9 +53102,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[0\]) (DELAY (ABSOLUTE - (PORT clk (1658:1658:1658) (1671:1671:1671)) + (PORT clk (1354:1354:1354) (1371:1371:1371)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1399:1399:1399) (1380:1380:1380)) + (PORT clrn (1390:1390:1390) (1369:1369:1369)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -53332,10 +53118,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~18) (DELAY (ABSOLUTE - (PORT datab (223:223:223) (291:291:291)) - (PORT datad (1171:1171:1171) (1205:1205:1205)) + (PORT datab (395:395:395) (429:429:429)) + (PORT datac (688:688:688) (729:729:729)) (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH datac combout (218:218:218) (215:215:215)) ) ) ) @@ -53344,10 +53130,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[4\]\~2) (DELAY (ABSOLUTE - (PORT datab (207:207:207) (255:255:255)) - (PORT datac (805:805:805) (796:796:796)) - (PORT datad (220:220:220) (284:284:284)) - (IOPATH datab combout (273:273:273) (275:275:275)) + (PORT dataa (247:247:247) (333:333:333)) + (PORT datac (554:554:554) (556:556:556)) + (PORT datad (187:187:187) (212:212:212)) + (IOPATH dataa combout (272:272:272) (269:269:269)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -53358,10 +53144,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[1\]) (DELAY (ABSOLUTE - (PORT clk (1687:1687:1687) (1708:1708:1708)) + (PORT clk (1354:1354:1354) (1370:1370:1370)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1399:1399:1399) (1380:1380:1380)) - (PORT ena (1950:1950:1950) (1961:1961:1961)) + (PORT clrn (1390:1390:1390) (1368:1368:1368)) + (PORT ena (1114:1114:1114) (1086:1086:1086)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -53376,10 +53162,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~17) (DELAY (ABSOLUTE - (PORT datac (196:196:196) (263:263:263)) - (PORT datad (1171:1171:1171) (1213:1213:1213)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (PORT datab (713:713:713) (767:767:767)) + (PORT datac (198:198:198) (265:265:265)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) ) ) ) @@ -53388,10 +53174,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[2\]) (DELAY (ABSOLUTE - (PORT clk (1687:1687:1687) (1708:1708:1708)) + (PORT clk (1354:1354:1354) (1370:1370:1370)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1399:1399:1399) (1380:1380:1380)) - (PORT ena (1950:1950:1950) (1961:1961:1961)) + (PORT clrn (1390:1390:1390) (1368:1368:1368)) + (PORT ena (1114:1114:1114) (1086:1086:1086)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -53406,9 +53192,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~16) (DELAY (ABSOLUTE - (PORT datab (223:223:223) (293:293:293)) - (PORT datad (1179:1179:1179) (1213:1213:1213)) - (IOPATH datab combout (319:319:319) (324:324:324)) + (PORT datac (683:683:683) (731:731:731)) + (PORT datad (200:200:200) (256:256:256)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -53418,10 +53204,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[3\]) (DELAY (ABSOLUTE - (PORT clk (1687:1687:1687) (1708:1708:1708)) + (PORT clk (1354:1354:1354) (1370:1370:1370)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1399:1399:1399) (1380:1380:1380)) - (PORT ena (1950:1950:1950) (1961:1961:1961)) + (PORT clrn (1390:1390:1390) (1368:1368:1368)) + (PORT ena (1114:1114:1114) (1086:1086:1086)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -53436,10 +53222,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~15) (DELAY (ABSOLUTE - (PORT datab (224:224:224) (294:294:294)) - (PORT datad (1188:1188:1188) (1224:1224:1224)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (PORT datab (717:717:717) (758:758:758)) + (PORT datac (198:198:198) (266:266:266)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) ) ) ) @@ -53448,10 +53234,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[4\]) (DELAY (ABSOLUTE - (PORT clk (1687:1687:1687) (1708:1708:1708)) + (PORT clk (1354:1354:1354) (1370:1370:1370)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1399:1399:1399) (1380:1380:1380)) - (PORT ena (1950:1950:1950) (1961:1961:1961)) + (PORT clrn (1390:1390:1390) (1368:1368:1368)) + (PORT ena (1114:1114:1114) (1086:1086:1086)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -53466,9 +53252,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~14) (DELAY (ABSOLUTE - (PORT datab (223:223:223) (293:293:293)) - (PORT datad (1187:1187:1187) (1223:1223:1223)) - (IOPATH datab combout (319:319:319) (324:324:324)) + (PORT datac (677:677:677) (732:732:732)) + (PORT datad (200:200:200) (257:257:257)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -53478,10 +53264,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[5\]) (DELAY (ABSOLUTE - (PORT clk (1687:1687:1687) (1708:1708:1708)) + (PORT clk (1354:1354:1354) (1370:1370:1370)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1399:1399:1399) (1380:1380:1380)) - (PORT ena (1950:1950:1950) (1961:1961:1961)) + (PORT clrn (1390:1390:1390) (1368:1368:1368)) + (PORT ena (1114:1114:1114) (1086:1086:1086)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -53496,10 +53282,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~13) (DELAY (ABSOLUTE - (PORT dataa (225:225:225) (298:298:298)) - (PORT datad (1181:1181:1181) (1219:1219:1219)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (PORT datab (719:719:719) (765:765:765)) + (PORT datac (197:197:197) (263:263:263)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) ) ) ) @@ -53508,10 +53294,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[6\]) (DELAY (ABSOLUTE - (PORT clk (1687:1687:1687) (1708:1708:1708)) + (PORT clk (1354:1354:1354) (1370:1370:1370)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1399:1399:1399) (1380:1380:1380)) - (PORT ena (1950:1950:1950) (1961:1961:1961)) + (PORT clrn (1390:1390:1390) (1368:1368:1368)) + (PORT ena (1114:1114:1114) (1086:1086:1086)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -53526,9 +53312,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~12) (DELAY (ABSOLUTE - (PORT datab (223:223:223) (292:292:292)) - (PORT datad (1168:1168:1168) (1206:1206:1206)) - (IOPATH datab combout (319:319:319) (324:324:324)) + (PORT datac (690:690:690) (730:730:730)) + (PORT datad (198:198:198) (255:255:255)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -53538,10 +53324,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[7\]) (DELAY (ABSOLUTE - (PORT clk (1687:1687:1687) (1708:1708:1708)) + (PORT clk (1354:1354:1354) (1370:1370:1370)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1399:1399:1399) (1380:1380:1380)) - (PORT ena (1950:1950:1950) (1961:1961:1961)) + (PORT clrn (1390:1390:1390) (1368:1368:1368)) + (PORT ena (1114:1114:1114) (1086:1086:1086)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -53556,10 +53342,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~11) (DELAY (ABSOLUTE - (PORT datac (195:195:195) (262:262:262)) - (PORT datad (1169:1169:1169) (1206:1206:1206)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (PORT datab (721:721:721) (766:766:766)) + (PORT datac (196:196:196) (264:264:264)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) ) ) ) @@ -53568,10 +53354,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[8\]) (DELAY (ABSOLUTE - (PORT clk (1687:1687:1687) (1708:1708:1708)) + (PORT clk (1354:1354:1354) (1370:1370:1370)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1399:1399:1399) (1380:1380:1380)) - (PORT ena (1950:1950:1950) (1961:1961:1961)) + (PORT clrn (1390:1390:1390) (1368:1368:1368)) + (PORT ena (1114:1114:1114) (1086:1086:1086)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -53586,9 +53372,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~10) (DELAY (ABSOLUTE - (PORT datab (223:223:223) (292:292:292)) - (PORT datad (1170:1170:1170) (1215:1215:1215)) - (IOPATH datab combout (319:319:319) (324:324:324)) + (PORT datac (680:680:680) (724:724:724)) + (PORT datad (200:200:200) (257:257:257)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -53598,10 +53384,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[9\]) (DELAY (ABSOLUTE - (PORT clk (1687:1687:1687) (1708:1708:1708)) + (PORT clk (1354:1354:1354) (1370:1370:1370)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1399:1399:1399) (1380:1380:1380)) - (PORT ena (1950:1950:1950) (1961:1961:1961)) + (PORT clrn (1390:1390:1390) (1368:1368:1368)) + (PORT ena (1114:1114:1114) (1086:1086:1086)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -53616,10 +53402,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~9) (DELAY (ABSOLUTE - (PORT datac (198:198:198) (265:265:265)) - (PORT datad (1186:1186:1186) (1225:1225:1225)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (PORT dataa (225:225:225) (298:298:298)) + (PORT datac (684:684:684) (732:732:732)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (218:218:218) (215:215:215)) ) ) ) @@ -53628,10 +53414,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[10\]) (DELAY (ABSOLUTE - (PORT clk (1687:1687:1687) (1708:1708:1708)) + (PORT clk (1354:1354:1354) (1370:1370:1370)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1399:1399:1399) (1380:1380:1380)) - (PORT ena (1950:1950:1950) (1961:1961:1961)) + (PORT clrn (1390:1390:1390) (1368:1368:1368)) + (PORT ena (1114:1114:1114) (1086:1086:1086)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -53646,9 +53432,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~8) (DELAY (ABSOLUTE - (PORT dataa (224:224:224) (297:297:297)) - (PORT datad (1188:1188:1188) (1223:1223:1223)) - (IOPATH dataa combout (318:318:318) (323:323:323)) + (PORT datac (685:685:685) (731:731:731)) + (PORT datad (199:199:199) (257:257:257)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -53658,10 +53444,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[11\]) (DELAY (ABSOLUTE - (PORT clk (1687:1687:1687) (1708:1708:1708)) + (PORT clk (1354:1354:1354) (1370:1370:1370)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1399:1399:1399) (1380:1380:1380)) - (PORT ena (1950:1950:1950) (1961:1961:1961)) + (PORT clrn (1390:1390:1390) (1368:1368:1368)) + (PORT ena (1114:1114:1114) (1086:1086:1086)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -53677,9 +53463,9 @@ (DELAY (ABSOLUTE (PORT datab (223:223:223) (292:292:292)) - (PORT datad (1185:1185:1185) (1226:1226:1226)) + (PORT datac (689:689:689) (729:729:729)) (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH datac combout (218:218:218) (215:215:215)) ) ) ) @@ -53688,10 +53474,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[12\]) (DELAY (ABSOLUTE - (PORT clk (1687:1687:1687) (1708:1708:1708)) + (PORT clk (1354:1354:1354) (1370:1370:1370)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1399:1399:1399) (1380:1380:1380)) - (PORT ena (1950:1950:1950) (1961:1961:1961)) + (PORT clrn (1390:1390:1390) (1368:1368:1368)) + (PORT ena (1114:1114:1114) (1086:1086:1086)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -53701,47 +53487,16 @@ (HOLD ena (posedge clk) (144:144:144)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|PCM_INR\[14\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1297:1297:1297) (1331:1331:1331)) - (PORT datab (821:821:821) (835:835:835)) - (PORT datad (212:212:212) (272:272:272)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|PCM_INR\[14\]) - (DELAY - (ABSOLUTE - (PORT clk (1347:1347:1347) (1364:1364:1364)) - (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1393:1393:1393) (1374:1374:1374)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2s_intf_\|PCM_INL\[14\]\~0) (DELAY (ABSOLUTE - (PORT dataa (1296:1296:1296) (1330:1330:1330)) - (PORT datab (821:821:821) (835:835:835)) - (PORT datad (212:212:212) (272:272:272)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) + (PORT dataa (438:438:438) (483:483:483)) + (PORT datab (543:543:543) (568:568:568)) + (PORT datad (357:357:357) (395:395:395)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (295:295:295) (300:300:300)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -53752,9 +53507,40 @@ (INSTANCE ula_\|i2s_intf_\|PCM_INL\[14\]) (DELAY (ABSOLUTE - (PORT clk (1347:1347:1347) (1364:1364:1364)) + (PORT clk (1354:1354:1354) (1371:1371:1371)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1393:1393:1393) (1374:1374:1374)) + (PORT clrn (1390:1390:1390) (1369:1369:1369)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|PCM_INR\[14\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (435:435:435) (478:478:478)) + (PORT datab (542:542:542) (566:566:566)) + (PORT datad (354:354:354) (393:393:393)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|PCM_INR\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1354:1354:1354) (1371:1371:1371)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1390:1390:1390) (1369:1369:1369)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -53768,8 +53554,8 @@ (INSTANCE ula_\|pcm_outr\~0) (DELAY (ABSOLUTE - (PORT datac (198:198:198) (266:266:266)) - (PORT datad (200:200:200) (258:258:258)) + (PORT datac (196:196:196) (263:263:263)) + (PORT datad (199:199:199) (255:255:255)) (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -53780,9 +53566,9 @@ (INSTANCE ula_\|pcm_outl\[12\]) (DELAY (ABSOLUTE - (PORT clk (1349:1349:1349) (1365:1365:1365)) + (PORT clk (1347:1347:1347) (1365:1365:1365)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (1939:1939:1939) (1935:1935:1935)) + (PORT ena (3269:3269:3269) (3239:3239:3239)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -53796,11 +53582,11 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~6) (DELAY (ABSOLUTE - (PORT datab (1224:1224:1224) (1262:1262:1262)) - (PORT datac (197:197:197) (264:264:264)) - (PORT datad (1242:1242:1242) (1258:1258:1258)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT datab (225:225:225) (295:295:295)) + (PORT datac (675:675:675) (729:729:729)) + (PORT datad (358:358:358) (394:394:394)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -53810,10 +53596,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[13\]) (DELAY (ABSOLUTE - (PORT clk (1687:1687:1687) (1708:1708:1708)) + (PORT clk (1354:1354:1354) (1370:1370:1370)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1399:1399:1399) (1380:1380:1380)) - (PORT ena (1950:1950:1950) (1961:1961:1961)) + (PORT clrn (1390:1390:1390) (1368:1368:1368)) + (PORT ena (1114:1114:1114) (1086:1086:1086)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -53823,16 +53609,32 @@ (HOLD ena (posedge clk) (144:144:144)) ) ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|pcm_outl\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1337:1337:1337) (1354:1354:1354)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (2199:2199:2199) (2172:2172:2172)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2s_intf_\|shiftreg\~5) (DELAY (ABSOLUTE - (PORT datab (1134:1134:1134) (1192:1192:1192)) - (PORT datac (196:196:196) (262:262:262)) - (PORT datad (1187:1187:1187) (1227:1227:1227)) - (IOPATH datab combout (275:275:275) (275:275:275)) - (IOPATH datac combout (220:220:220) (215:215:215)) + (PORT dataa (224:224:224) (297:297:297)) + (PORT datab (714:714:714) (759:759:759)) + (PORT datad (1808:1808:1808) (1848:1848:1848)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -53842,10 +53644,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[14\]) (DELAY (ABSOLUTE - (PORT clk (1687:1687:1687) (1708:1708:1708)) + (PORT clk (1354:1354:1354) (1370:1370:1370)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1399:1399:1399) (1380:1380:1380)) - (PORT ena (1950:1950:1950) (1961:1961:1961)) + (PORT clrn (1390:1390:1390) (1368:1368:1368)) + (PORT ena (1114:1114:1114) (1086:1086:1086)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -53855,33 +53657,17 @@ (HOLD ena (posedge clk) (144:144:144)) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|pcm_outl\[14\]) - (DELAY - (ABSOLUTE - (PORT clk (1346:1346:1346) (1363:1363:1363)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (2079:2079:2079) (2031:2031:2031)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2s_intf_\|shiftreg\~4) (DELAY (ABSOLUTE - (PORT dataa (1121:1121:1121) (1163:1163:1163)) - (PORT datac (903:903:903) (960:960:960)) - (PORT datad (609:609:609) (605:605:605)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (PORT dataa (2180:2180:2180) (2223:2223:2223)) + (PORT datab (241:241:241) (310:310:310)) + (PORT datac (682:682:682) (725:725:725)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (220:220:220) (216:216:216)) ) ) ) @@ -53890,10 +53676,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[15\]) (DELAY (ABSOLUTE - (PORT clk (1679:1679:1679) (1704:1704:1704)) + (PORT clk (1354:1354:1354) (1370:1370:1370)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1395:1395:1395) (1376:1376:1376)) - (PORT ena (1059:1059:1059) (1025:1025:1025)) + (PORT clrn (1390:1390:1390) (1368:1368:1368)) + (PORT ena (1114:1114:1114) (1086:1086:1086)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -53908,10 +53694,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~3) (DELAY (ABSOLUTE - (PORT datac (196:196:196) (262:262:262)) - (PORT datad (610:610:610) (609:609:609)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (PORT dataa (415:415:415) (436:436:436)) + (PORT datac (566:566:566) (594:594:594)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datac combout (220:220:220) (216:216:216)) ) ) ) @@ -53920,10 +53706,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[16\]) (DELAY (ABSOLUTE - (PORT clk (1349:1349:1349) (1366:1366:1366)) + (PORT clk (1686:1686:1686) (1704:1704:1704)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1395:1395:1395) (1376:1376:1376)) - (PORT ena (1094:1094:1094) (1068:1068:1068)) + (PORT clrn (1390:1390:1390) (1369:1369:1369)) + (PORT ena (1327:1327:1327) (1299:1299:1299)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -53938,10 +53724,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~0) (DELAY (ABSOLUTE - (PORT datab (221:221:221) (290:290:290)) - (PORT datad (606:606:606) (607:607:607)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (PORT dataa (223:223:223) (296:296:296)) + (PORT datac (380:380:380) (404:404:404)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (218:218:218) (215:215:215)) ) ) ) @@ -53951,9 +53737,9 @@ (DELAY (ABSOLUTE (PORT clk (1334:1334:1334) (1351:1351:1351)) - (PORT d (1371:1371:1371) (1418:1418:1418)) - (PORT clrn (1567:1567:1567) (1603:1603:1603)) - (PORT ena (1582:1582:1582) (1591:1591:1591)) + (PORT d (820:820:820) (854:854:854)) + (PORT clrn (1557:1557:1557) (1591:1591:1591)) + (PORT ena (808:808:808) (806:806:806)) (IOPATH (posedge clk) q (524:524:524) (534:534:534)) (IOPATH (negedge clrn) q (642:642:642) (652:652:652)) ) @@ -53967,16 +53753,57 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|LessThan2\~0) + (INSTANCE ula_\|border\[1\]\~feeder) (DELAY (ABSOLUTE - (PORT dataa (264:264:264) (341:341:341)) - (PORT datab (246:246:246) (316:316:316)) - (PORT datac (236:236:236) (305:305:305)) - (PORT datad (222:222:222) (283:283:283)) + (PORT datad (198:198:198) (220:220:220)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|border\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1339:1339:1339) (1357:1357:1357)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1776:1776:1776) (1721:1721:1721)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|LessThan4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (416:416:416) (455:455:455)) + (PORT datab (246:246:246) (319:319:319)) + (PORT datac (218:218:218) (289:289:289)) + (PORT datad (221:221:221) (279:279:279)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|screen_en\~0) + (DELAY + (ABSOLUTE + (PORT dataa (413:413:413) (457:457:457)) + (PORT datab (243:243:243) (314:314:314)) + (PORT datad (288:288:288) (295:295:295)) (IOPATH dataa combout (309:309:309) (326:326:326)) (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -53986,10 +53813,57 @@ (INSTANCE ula_\|video_\|LessThan6\~0) (DELAY (ABSOLUTE - (PORT dataa (239:239:239) (310:310:310)) + (PORT dataa (238:238:238) (310:310:310)) (PORT datab (237:237:237) (305:305:305)) - (PORT datac (230:230:230) (298:298:298)) - (PORT datad (216:216:216) (274:274:274)) + (PORT datad (217:217:217) (274:274:274)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|LessThan6\~1) + (DELAY + (ABSOLUTE + (PORT dataa (257:257:257) (331:331:331)) + (PORT datab (256:256:256) (325:325:325)) + (PORT datac (214:214:214) (281:281:281)) + (PORT datad (318:318:318) (315:315:315)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|screen_en\~1) + (DELAY + (ABSOLUTE + (PORT dataa (380:380:380) (436:436:436)) + (PORT datab (433:433:433) (463:463:463)) + (PORT datac (155:155:155) (186:186:186)) + (PORT datad (160:160:160) (179:179:179)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|LessThan2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (611:611:611) (643:643:643)) + (PORT datab (262:262:262) (336:336:336)) + (PORT datac (391:391:391) (434:434:434)) + (PORT datad (356:356:356) (396:396:396)) (IOPATH dataa combout (309:309:309) (326:326:326)) (IOPATH datab combout (309:309:309) (328:328:328)) (IOPATH datac combout (218:218:218) (215:215:215)) @@ -54002,12 +53876,12 @@ (INSTANCE ula_\|video_\|LessThan2\~1) (DELAY (ABSOLUTE - (PORT dataa (424:424:424) (479:479:479)) - (PORT datab (244:244:244) (316:316:316)) - (PORT datac (157:157:157) (188:188:188)) - (PORT datad (337:337:337) (335:335:335)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (295:295:295) (294:294:294)) + (PORT dataa (596:596:596) (626:626:626)) + (PORT datab (384:384:384) (442:442:442)) + (PORT datac (156:156:156) (187:187:187)) + (PORT datad (185:185:185) (212:212:212)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -54018,12 +53892,13 @@ (INSTANCE ula_\|video_\|LessThan3\~0) (DELAY (ABSOLUTE - (PORT dataa (265:265:265) (343:343:343)) - (PORT datab (220:220:220) (254:254:254)) - (PORT datad (178:178:178) (200:200:200)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) + (PORT dataa (580:580:580) (620:620:620)) + (PORT datab (208:208:208) (245:245:245)) + (PORT datac (576:576:576) (607:607:607)) + (PORT datad (176:176:176) (198:198:198)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -54033,11 +53908,10 @@ (INSTANCE ula_\|video_\|LessThan0\~0) (DELAY (ABSOLUTE - (PORT dataa (246:246:246) (323:323:323)) - (PORT datab (238:238:238) (306:306:306)) - (PORT datad (224:224:224) (287:287:287)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) + (PORT datab (243:243:243) (315:315:315)) + (PORT datad (224:224:224) (284:284:284)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -54047,11 +53921,11 @@ (INSTANCE ula_\|video_\|disp_enable\~0) (DELAY (ABSOLUTE - (PORT dataa (182:182:182) (218:218:218)) - (PORT datab (385:385:385) (430:430:430)) - (PORT datad (608:608:608) (642:642:642)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (319:319:319) (324:324:324)) + (PORT dataa (248:248:248) (324:324:324)) + (PORT datab (406:406:406) (448:448:448)) + (PORT datad (157:157:157) (178:178:178)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -54062,100 +53936,21 @@ (INSTANCE ula_\|video_\|disp_enable\~1) (DELAY (ABSOLUTE - (PORT dataa (193:193:193) (236:236:236)) - (PORT datab (189:189:189) (227:227:227)) - (PORT datad (324:324:324) (328:328:328)) + (PORT dataa (190:190:190) (230:230:230)) + (PORT datab (187:187:187) (223:223:223)) + (PORT datad (484:484:484) (469:469:469)) (IOPATH dataa combout (287:287:287) (289:289:289)) (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|border\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1349:1349:1349) (1365:1365:1365)) - (PORT asdata (485:485:485) (512:512:512)) - (PORT ena (1939:1939:1939) (1935:1935:1935)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|LessThan6\~1) + (INSTANCE ula_\|video_\|attr_prefetch\[7\]\~feeder) (DELAY (ABSOLUTE - (PORT dataa (421:421:421) (479:479:479)) - (PORT datab (429:429:429) (487:487:487)) - (PORT datac (394:394:394) (447:447:447)) - (PORT datad (384:384:384) (395:395:395)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH datab combout (336:336:336) (337:337:337)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|LessThan4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (246:246:246) (322:322:322)) - (PORT datab (248:248:248) (320:320:320)) - (PORT datad (214:214:214) (271:271:271)) - (IOPATH dataa combout (267:267:267) (269:269:269)) - (IOPATH datab combout (267:267:267) (275:275:275)) - (IOPATH datac combout (312:312:312) (325:325:325)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|screen_en\~0) - (DELAY - (ABSOLUTE - (PORT dataa (412:412:412) (463:463:463)) - (PORT datab (426:426:426) (480:480:480)) - (PORT datac (508:508:508) (501:501:501)) - (PORT datad (602:602:602) (632:632:632)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|screen_en\~1) - (DELAY - (ABSOLUTE - (PORT dataa (640:640:640) (667:667:667)) - (PORT datab (450:450:450) (495:495:495)) - (PORT datac (157:157:157) (187:187:187)) - (PORT datad (160:160:160) (180:180:180)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (295:295:295) (285:285:285)) - (IOPATH datac combout (218:218:218) (216:216:216)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|attr_prefetch\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1363:1363:1363) (1338:1338:1338)) + (PORT datad (1273:1273:1273) (1246:1246:1246)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -54165,10 +53960,10 @@ (INSTANCE ula_\|video_\|Decoder0\~1) (DELAY (ABSOLUTE - (PORT dataa (1152:1152:1152) (1187:1187:1187)) - (PORT datab (893:893:893) (951:951:951)) - (PORT datac (887:887:887) (938:938:938)) - (PORT datad (256:256:256) (324:324:324)) + (PORT dataa (696:696:696) (752:752:752)) + (PORT datab (679:679:679) (735:735:735)) + (PORT datac (1064:1064:1064) (1071:1071:1071)) + (PORT datad (635:635:635) (672:672:672)) (IOPATH dataa combout (290:290:290) (306:306:306)) (IOPATH datab combout (295:295:295) (300:300:300)) (IOPATH datac combout (220:220:220) (215:215:215)) @@ -54178,12 +53973,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr_prefetch\[1\]) + (INSTANCE ula_\|video_\|attr_prefetch\[7\]) (DELAY (ABSOLUTE - (PORT clk (1725:1725:1725) (1744:1744:1744)) + (PORT clk (1714:1714:1714) (1734:1734:1734)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (1341:1341:1341) (1316:1316:1316)) + (PORT ena (1280:1280:1280) (1242:1242:1242)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -54197,10 +53992,10 @@ (INSTANCE ula_\|video_\|Decoder0\~0) (DELAY (ABSOLUTE - (PORT dataa (1153:1153:1153) (1187:1187:1187)) - (PORT datab (894:894:894) (950:950:950)) - (PORT datac (887:887:887) (937:937:937)) - (PORT datad (256:256:256) (325:325:325)) + (PORT dataa (690:690:690) (745:745:745)) + (PORT datab (675:675:675) (727:727:727)) + (PORT datac (1069:1069:1069) (1079:1079:1079)) + (PORT datad (640:640:640) (679:679:679)) (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) @@ -54208,98 +54003,14 @@ ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1357:1357:1357) (1372:1372:1372)) - (PORT asdata (1649:1649:1649) (1651:1651:1651)) - (PORT ena (1303:1303:1303) (1280:1280:1280)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|attr_prefetch\[4\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1431:1431:1431) (1390:1390:1390)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr_prefetch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1725:1725:1725) (1744:1744:1744)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1341:1341:1341) (1316:1316:1316)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1357:1357:1357) (1372:1372:1372)) - (PORT asdata (929:929:929) (964:964:964)) - (PORT ena (1303:1303:1303) (1280:1280:1280)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|attr_prefetch\[7\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1117:1117:1117) (1124:1124:1124)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr_prefetch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1725:1725:1725) (1744:1744:1744)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1341:1341:1341) (1316:1316:1316)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|video_\|attr\[7\]) (DELAY (ABSOLUTE - (PORT clk (1357:1357:1357) (1373:1373:1373)) - (PORT asdata (927:927:927) (957:957:957)) - (PORT ena (1309:1309:1309) (1287:1287:1287)) + (PORT clk (1356:1356:1356) (1372:1372:1372)) + (PORT asdata (707:707:707) (745:745:745)) + (PORT ena (1325:1325:1325) (1285:1285:1285)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -54313,9 +54024,9 @@ (INSTANCE ula_\|video_\|frame\[0\]\~12) (DELAY (ABSOLUTE - (PORT dataa (577:577:577) (563:563:563)) - (IOPATH dataa combout (318:318:318) (327:327:327)) + (PORT datad (541:541:541) (537:537:537)) (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) @@ -54324,7 +54035,7 @@ (INSTANCE ula_\|video_\|frame\[0\]) (DELAY (ABSOLUTE - (PORT clk (1360:1360:1360) (1375:1375:1375)) + (PORT clk (1358:1358:1358) (1374:1374:1374)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -54338,8 +54049,8 @@ (INSTANCE ula_\|video_\|frame\[1\]\~4) (DELAY (ABSOLUTE - (PORT dataa (568:568:568) (589:589:589)) - (PORT datab (222:222:222) (290:290:290)) + (PORT dataa (782:782:782) (795:795:795)) + (PORT datab (222:222:222) (291:291:291)) (IOPATH dataa combout (300:300:300) (323:323:323)) (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datab combout (306:306:306) (324:324:324)) @@ -54355,7 +54066,7 @@ (ABSOLUTE (PORT clk (1359:1359:1359) (1375:1375:1375)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (1137:1137:1137) (1114:1114:1114)) + (PORT ena (1574:1574:1574) (1552:1552:1552)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -54369,9 +54080,9 @@ (INSTANCE ula_\|video_\|frame\[2\]\~6) (DELAY (ABSOLUTE - (PORT dataa (222:222:222) (295:295:295)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH dataa cout (376:376:376) (275:275:275)) + (PORT datab (222:222:222) (291:291:291)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) (IOPATH cin cout (50:50:50) (50:50:50)) @@ -54385,7 +54096,7 @@ (ABSOLUTE (PORT clk (1359:1359:1359) (1375:1375:1375)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (1137:1137:1137) (1114:1114:1114)) + (PORT ena (1574:1574:1574) (1552:1552:1552)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -54399,7 +54110,7 @@ (INSTANCE ula_\|video_\|frame\[3\]\~8) (DELAY (ABSOLUTE - (PORT datab (221:221:221) (290:290:290)) + (PORT datab (222:222:222) (291:291:291)) (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -54415,7 +54126,7 @@ (ABSOLUTE (PORT clk (1359:1359:1359) (1375:1375:1375)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (1137:1137:1137) (1114:1114:1114)) + (PORT ena (1574:1574:1574) (1552:1552:1552)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -54429,20 +54140,30 @@ (INSTANCE ula_\|video_\|frame\[4\]\~10) (DELAY (ABSOLUTE - (PORT dataa (241:241:241) (315:315:315)) - (IOPATH dataa combout (318:318:318) (327:327:327)) + (PORT datad (639:639:639) (663:663:663)) + (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|frame\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (501:501:501) (485:485:485)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|video_\|frame\[4\]) (DELAY (ABSOLUTE - (PORT clk (1359:1359:1359) (1375:1375:1375)) + (PORT clk (1356:1356:1356) (1372:1372:1372)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (1137:1137:1137) (1114:1114:1114)) + (PORT ena (1055:1055:1055) (1024:1024:1024)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -54456,7 +54177,7 @@ (INSTANCE ula_\|video_\|inverted) (DELAY (ABSOLUTE - (PORT datad (346:346:346) (380:380:380)) + (PORT datad (217:217:217) (275:275:275)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -54467,8 +54188,8 @@ (INSTANCE ula_\|video_\|bits_prefetch\[6\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (1072:1072:1072) (1077:1077:1077)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (PORT datac (1353:1353:1353) (1373:1373:1373)) + (IOPATH datac combout (220:220:220) (216:216:216)) ) ) ) @@ -54477,13 +54198,13 @@ (INSTANCE ula_\|video_\|Decoder0\~2) (DELAY (ABSOLUTE - (PORT dataa (1153:1153:1153) (1184:1184:1184)) - (PORT datab (895:895:895) (950:950:950)) - (PORT datac (886:886:886) (939:939:939)) - (PORT datad (254:254:254) (323:323:323)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT dataa (692:692:692) (753:753:753)) + (PORT datab (676:676:676) (731:731:731)) + (PORT datac (1064:1064:1064) (1078:1078:1078)) + (PORT datad (635:635:635) (678:678:678)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -54493,9 +54214,9 @@ (INSTANCE ula_\|video_\|bits_prefetch\[6\]) (DELAY (ABSOLUTE - (PORT clk (1697:1697:1697) (1712:1712:1712)) + (PORT clk (1686:1686:1686) (1702:1702:1702)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (1345:1345:1345) (1319:1319:1319)) + (PORT ena (1346:1346:1346) (1318:1318:1318)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -54504,29 +54225,19 @@ (HOLD ena (posedge clk) (144:144:144)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|bits\[6\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (568:568:568) (601:601:601)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|video_\|bits\[6\]) (DELAY (ABSOLUTE - (PORT clk (1357:1357:1357) (1373:1373:1373)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1309:1309:1309) (1287:1287:1287)) + (PORT clk (1356:1356:1356) (1372:1372:1372)) + (PORT asdata (861:861:861) (882:882:882)) + (PORT ena (1325:1325:1325) (1285:1285:1285)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) + (HOLD asdata (posedge clk) (144:144:144)) (HOLD ena (posedge clk) (144:144:144)) ) ) @@ -54535,7 +54246,7 @@ (INSTANCE ula_\|video_\|bits_prefetch\[4\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (1430:1430:1430) (1388:1388:1388)) + (PORT datad (1647:1647:1647) (1685:1685:1685)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -54545,9 +54256,9 @@ (INSTANCE ula_\|video_\|bits_prefetch\[4\]) (DELAY (ABSOLUTE - (PORT clk (1697:1697:1697) (1712:1712:1712)) + (PORT clk (1686:1686:1686) (1702:1702:1702)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (1345:1345:1345) (1319:1319:1319)) + (PORT ena (1346:1346:1346) (1318:1318:1318)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -54561,9 +54272,9 @@ (INSTANCE ula_\|video_\|bits\[4\]) (DELAY (ABSOLUTE - (PORT clk (1357:1357:1357) (1373:1373:1373)) - (PORT asdata (915:915:915) (943:943:943)) - (PORT ena (1309:1309:1309) (1287:1287:1287)) + (PORT clk (1356:1356:1356) (1372:1372:1372)) + (PORT asdata (676:676:676) (723:723:723)) + (PORT ena (1325:1325:1325) (1285:1285:1285)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -54577,7 +54288,7 @@ (INSTANCE ula_\|video_\|bits_prefetch\[5\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (876:876:876) (871:871:871)) + (PORT datad (766:766:766) (757:757:757)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -54587,9 +54298,9 @@ (INSTANCE ula_\|video_\|bits_prefetch\[5\]) (DELAY (ABSOLUTE - (PORT clk (1697:1697:1697) (1712:1712:1712)) + (PORT clk (1686:1686:1686) (1702:1702:1702)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (1345:1345:1345) (1319:1319:1319)) + (PORT ena (1346:1346:1346) (1318:1318:1318)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -54603,7 +54314,7 @@ (INSTANCE ula_\|video_\|bits\[5\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (600:600:600) (633:633:633)) + (PORT datad (388:388:388) (435:435:435)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -54613,9 +54324,9 @@ (INSTANCE ula_\|video_\|bits\[5\]) (DELAY (ABSOLUTE - (PORT clk (1357:1357:1357) (1373:1373:1373)) + (PORT clk (1356:1356:1356) (1372:1372:1372)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (1309:1309:1309) (1287:1287:1287)) + (PORT ena (1325:1325:1325) (1285:1285:1285)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -54629,7 +54340,7 @@ (INSTANCE ula_\|video_\|bits_prefetch\[7\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (1123:1123:1123) (1128:1128:1128)) + (PORT datad (1273:1273:1273) (1249:1249:1249)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -54639,9 +54350,9 @@ (INSTANCE ula_\|video_\|bits_prefetch\[7\]) (DELAY (ABSOLUTE - (PORT clk (1697:1697:1697) (1712:1712:1712)) + (PORT clk (1686:1686:1686) (1702:1702:1702)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (1345:1345:1345) (1319:1319:1319)) + (PORT ena (1346:1346:1346) (1318:1318:1318)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -54655,9 +54366,9 @@ (INSTANCE ula_\|video_\|bits\[7\]) (DELAY (ABSOLUTE - (PORT clk (1357:1357:1357) (1373:1373:1373)) - (PORT asdata (1123:1123:1123) (1142:1142:1142)) - (PORT ena (1309:1309:1309) (1287:1287:1287)) + (PORT clk (1356:1356:1356) (1372:1372:1372)) + (PORT asdata (706:706:706) (746:746:746)) + (PORT ena (1325:1325:1325) (1285:1285:1285)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -54671,11 +54382,11 @@ (INSTANCE ula_\|video_\|Mux0\~0) (DELAY (ABSOLUTE - (PORT dataa (362:362:362) (409:409:409)) - (PORT datab (258:258:258) (340:340:340)) - (PORT datad (592:592:592) (624:624:624)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (325:325:325) (332:332:332)) + (PORT dataa (222:222:222) (295:295:295)) + (PORT datab (572:572:572) (606:606:606)) + (PORT datad (565:565:565) (588:588:588)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -54686,9 +54397,9 @@ (INSTANCE ula_\|video_\|Mux0\~1) (DELAY (ABSOLUTE - (PORT dataa (222:222:222) (294:294:294)) - (PORT datab (255:255:255) (335:335:335)) - (PORT datad (161:161:161) (182:182:182)) + (PORT dataa (584:584:584) (620:620:620)) + (PORT datab (392:392:392) (444:444:444)) + (PORT datad (160:160:160) (179:179:179)) (IOPATH dataa combout (300:300:300) (323:323:323)) (IOPATH datab combout (306:306:306) (324:324:324)) (IOPATH datac combout (312:312:312) (325:325:325)) @@ -54701,7 +54412,7 @@ (INSTANCE ula_\|video_\|bits_prefetch\[2\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (817:817:817) (812:812:812)) + (PORT datad (1621:1621:1621) (1607:1607:1607)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -54711,9 +54422,9 @@ (INSTANCE ula_\|video_\|bits_prefetch\[2\]) (DELAY (ABSOLUTE - (PORT clk (1697:1697:1697) (1712:1712:1712)) + (PORT clk (1686:1686:1686) (1702:1702:1702)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (1345:1345:1345) (1319:1319:1319)) + (PORT ena (1346:1346:1346) (1318:1318:1318)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -54727,7 +54438,7 @@ (INSTANCE ula_\|video_\|bits\[2\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (590:590:590) (620:620:620)) + (PORT datad (544:544:544) (572:572:572)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -54737,9 +54448,9 @@ (INSTANCE ula_\|video_\|bits\[2\]) (DELAY (ABSOLUTE - (PORT clk (1357:1357:1357) (1373:1373:1373)) + (PORT clk (1356:1356:1356) (1372:1372:1372)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (1309:1309:1309) (1287:1287:1287)) + (PORT ena (1325:1325:1325) (1285:1285:1285)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -54753,7 +54464,7 @@ (INSTANCE ula_\|video_\|bits_prefetch\[0\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (1359:1359:1359) (1296:1296:1296)) + (PORT datad (1404:1404:1404) (1353:1353:1353)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -54763,9 +54474,9 @@ (INSTANCE ula_\|video_\|bits_prefetch\[0\]) (DELAY (ABSOLUTE - (PORT clk (1697:1697:1697) (1712:1712:1712)) + (PORT clk (1686:1686:1686) (1702:1702:1702)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (1345:1345:1345) (1319:1319:1319)) + (PORT ena (1346:1346:1346) (1318:1318:1318)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -54779,9 +54490,9 @@ (INSTANCE ula_\|video_\|bits\[0\]) (DELAY (ABSOLUTE - (PORT clk (1357:1357:1357) (1373:1373:1373)) - (PORT asdata (902:902:902) (926:926:926)) - (PORT ena (1309:1309:1309) (1287:1287:1287)) + (PORT clk (1356:1356:1356) (1372:1372:1372)) + (PORT asdata (1338:1338:1338) (1348:1348:1348)) + (PORT ena (1325:1325:1325) (1285:1285:1285)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -54795,7 +54506,7 @@ (INSTANCE ula_\|video_\|bits_prefetch\[1\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (1360:1360:1360) (1334:1334:1334)) + (PORT datad (803:803:803) (790:790:790)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -54805,9 +54516,9 @@ (INSTANCE ula_\|video_\|bits_prefetch\[1\]) (DELAY (ABSOLUTE - (PORT clk (1697:1697:1697) (1712:1712:1712)) + (PORT clk (1686:1686:1686) (1702:1702:1702)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (1345:1345:1345) (1319:1319:1319)) + (PORT ena (1346:1346:1346) (1318:1318:1318)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -54821,7 +54532,7 @@ (INSTANCE ula_\|video_\|bits\[1\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (591:591:591) (619:619:619)) + (PORT datad (375:375:375) (417:417:417)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -54831,9 +54542,9 @@ (INSTANCE ula_\|video_\|bits\[1\]) (DELAY (ABSOLUTE - (PORT clk (1357:1357:1357) (1373:1373:1373)) + (PORT clk (1356:1356:1356) (1372:1372:1372)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (1309:1309:1309) (1287:1287:1287)) + (PORT ena (1325:1325:1325) (1285:1285:1285)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -54847,7 +54558,7 @@ (INSTANCE ula_\|video_\|bits_prefetch\[3\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (1179:1179:1179) (1117:1117:1117)) + (PORT datad (1313:1313:1313) (1305:1305:1305)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -54857,9 +54568,9 @@ (INSTANCE ula_\|video_\|bits_prefetch\[3\]) (DELAY (ABSOLUTE - (PORT clk (1697:1697:1697) (1712:1712:1712)) + (PORT clk (1686:1686:1686) (1702:1702:1702)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (1345:1345:1345) (1319:1319:1319)) + (PORT ena (1346:1346:1346) (1318:1318:1318)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -54873,9 +54584,9 @@ (INSTANCE ula_\|video_\|bits\[3\]) (DELAY (ABSOLUTE - (PORT clk (1357:1357:1357) (1373:1373:1373)) - (PORT asdata (1335:1335:1335) (1311:1311:1311)) - (PORT ena (1309:1309:1309) (1287:1287:1287)) + (PORT clk (1356:1356:1356) (1372:1372:1372)) + (PORT asdata (676:676:676) (724:724:724)) + (PORT ena (1325:1325:1325) (1285:1285:1285)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -54889,11 +54600,11 @@ (INSTANCE ula_\|video_\|Mux0\~2) (DELAY (ABSOLUTE - (PORT dataa (221:221:221) (293:293:293)) - (PORT datab (255:255:255) (335:335:335)) - (PORT datad (589:589:589) (620:620:620)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (325:325:325) (332:332:332)) + (PORT dataa (585:585:585) (620:620:620)) + (PORT datab (221:221:221) (290:290:290)) + (PORT datad (553:553:553) (573:573:573)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -54904,9 +54615,9 @@ (INSTANCE ula_\|video_\|Mux0\~3) (DELAY (ABSOLUTE - (PORT dataa (221:221:221) (293:293:293)) - (PORT datab (258:258:258) (340:340:340)) - (PORT datad (161:161:161) (182:182:182)) + (PORT dataa (581:581:581) (618:618:618)) + (PORT datab (350:350:350) (404:404:404)) + (PORT datad (159:159:159) (181:181:181)) (IOPATH dataa combout (300:300:300) (323:323:323)) (IOPATH datab combout (306:306:306) (324:324:324)) (IOPATH datac combout (312:312:312) (325:325:325)) @@ -54919,25 +54630,109 @@ (INSTANCE ula_\|video_\|cindex\[1\]\~0) (DELAY (ABSOLUTE - (PORT dataa (377:377:377) (425:425:425)) - (PORT datab (181:181:181) (215:215:215)) + (PORT dataa (183:183:183) (220:220:220)) + (PORT datab (589:589:589) (628:628:628)) (PORT datac (157:157:157) (188:188:188)) - (PORT datad (158:158:158) (180:180:180)) - (IOPATH dataa combout (299:299:299) (306:306:306)) - (IOPATH datab combout (319:319:319) (324:324:324)) + (PORT datad (159:159:159) (180:180:180)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datab combout (300:300:300) (312:312:312)) (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|attr_prefetch\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1647:1647:1647) (1685:1685:1685)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr_prefetch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1714:1714:1714) (1734:1734:1734)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1280:1280:1280) (1242:1242:1242)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1357:1357:1357) (1373:1373:1373)) + (PORT asdata (901:901:901) (912:912:912)) + (PORT ena (1336:1336:1336) (1295:1295:1295)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|attr_prefetch\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (804:804:804) (793:793:793)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr_prefetch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1714:1714:1714) (1734:1734:1734)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1280:1280:1280) (1242:1242:1242)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1357:1357:1357) (1373:1373:1373)) + (PORT asdata (1414:1414:1414) (1434:1434:1434)) + (PORT ena (1336:1336:1336) (1295:1295:1295)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|cindex\[1\]\~1) (DELAY (ABSOLUTE - (PORT dataa (223:223:223) (296:296:296)) - (PORT datad (322:322:322) (326:326:326)) - (IOPATH dataa combout (273:273:273) (269:269:269)) + (PORT dataa (348:348:348) (365:365:365)) + (PORT datad (198:198:198) (255:255:255)) + (IOPATH dataa combout (318:318:318) (327:327:327)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -54948,13 +54743,13 @@ (INSTANCE ula_\|video_\|VGA_R\[0\]\~0) (DELAY (ABSOLUTE - (PORT dataa (372:372:372) (405:405:405)) - (PORT datab (1379:1379:1379) (1403:1403:1403)) - (PORT datac (212:212:212) (254:254:254)) - (PORT datad (165:165:165) (188:188:188)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT dataa (2432:2432:2432) (2470:2470:2470)) + (PORT datab (334:334:334) (362:362:362)) + (PORT datac (547:547:547) (534:534:534)) + (PORT datad (166:166:166) (188:188:188)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -54964,8 +54759,8 @@ (INSTANCE ula_\|video_\|attr_prefetch\[6\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (1074:1074:1074) (1080:1080:1080)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (PORT datac (1353:1353:1353) (1377:1377:1377)) + (IOPATH datac combout (220:220:220) (216:216:216)) ) ) ) @@ -54974,9 +54769,9 @@ (INSTANCE ula_\|video_\|attr_prefetch\[6\]) (DELAY (ABSOLUTE - (PORT clk (1725:1725:1725) (1744:1744:1744)) + (PORT clk (1714:1714:1714) (1734:1734:1734)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (1341:1341:1341) (1316:1316:1316)) + (PORT ena (1280:1280:1280) (1242:1242:1242)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -54990,9 +54785,9 @@ (INSTANCE ula_\|video_\|attr\[6\]) (DELAY (ABSOLUTE - (PORT clk (1353:1353:1353) (1369:1369:1369)) - (PORT asdata (1117:1117:1117) (1123:1123:1123)) - (PORT ena (1513:1513:1513) (1457:1457:1457)) + (PORT clk (1357:1357:1357) (1373:1373:1373)) + (PORT asdata (890:890:890) (922:922:922)) + (PORT ena (1336:1336:1336) (1295:1295:1295)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -55006,9 +54801,9 @@ (INSTANCE ula_\|video_\|VGA_B\[1\]\~0) (DELAY (ABSOLUTE - (PORT dataa (194:194:194) (237:237:237)) - (PORT datab (189:189:189) (228:228:228)) - (PORT datad (325:325:325) (328:328:328)) + (PORT dataa (191:191:191) (230:230:230)) + (PORT datab (188:188:188) (224:224:224)) + (PORT datad (484:484:484) (469:469:469)) (IOPATH dataa combout (287:287:287) (289:289:289)) (IOPATH datab combout (275:275:275) (275:275:275)) (IOPATH datac combout (312:312:312) (325:325:325)) @@ -55021,11 +54816,11 @@ (INSTANCE ula_\|video_\|VGA_R\[1\]\~1) (DELAY (ABSOLUTE - (PORT dataa (243:243:243) (290:290:290)) - (PORT datac (364:364:364) (382:382:382)) - (PORT datad (165:165:165) (187:187:187)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT dataa (1200:1200:1200) (1161:1161:1161)) + (PORT datab (202:202:202) (237:237:237)) + (PORT datad (166:166:166) (189:189:189)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -55035,51 +54830,9 @@ (INSTANCE ula_\|border\[2\]) (DELAY (ABSOLUTE - (PORT clk (1343:1343:1343) (1360:1360:1360)) - (PORT asdata (882:882:882) (867:867:867)) - (PORT ena (735:735:735) (734:734:734)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|attr_prefetch\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (817:817:817) (811:811:811)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr_prefetch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1725:1725:1725) (1744:1744:1744)) - (PORT d (67:67:67) (78:78:78)) - (PORT ena (1341:1341:1341) (1316:1316:1316)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - (HOLD ena (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1357:1357:1357) (1373:1373:1373)) - (PORT asdata (1104:1104:1104) (1120:1120:1120)) - (PORT ena (1309:1309:1309) (1287:1287:1287)) + (PORT clk (1339:1339:1339) (1357:1357:1357)) + (PORT asdata (1737:1737:1737) (1698:1698:1698)) + (PORT ena (1776:1776:1776) (1721:1721:1721)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -55093,7 +54846,7 @@ (INSTANCE ula_\|video_\|attr_prefetch\[5\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (874:874:874) (869:869:869)) + (PORT datad (765:765:765) (757:757:757)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -55103,9 +54856,9 @@ (INSTANCE ula_\|video_\|attr_prefetch\[5\]) (DELAY (ABSOLUTE - (PORT clk (1725:1725:1725) (1744:1744:1744)) + (PORT clk (1714:1714:1714) (1734:1734:1734)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (1341:1341:1341) (1316:1316:1316)) + (PORT ena (1280:1280:1280) (1242:1242:1242)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -55120,8 +54873,50 @@ (DELAY (ABSOLUTE (PORT clk (1357:1357:1357) (1373:1373:1373)) - (PORT asdata (910:910:910) (932:932:932)) - (PORT ena (1309:1309:1309) (1287:1287:1287)) + (PORT asdata (943:943:943) (983:983:983)) + (PORT ena (1336:1336:1336) (1295:1295:1295)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|attr_prefetch\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1623:1623:1623) (1608:1608:1608)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr_prefetch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1714:1714:1714) (1734:1734:1734)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (1280:1280:1280) (1242:1242:1242)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1357:1357:1357) (1373:1373:1373)) + (PORT asdata (1284:1284:1284) (1286:1286:1286)) + (PORT ena (1336:1336:1336) (1295:1295:1295)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -55135,9 +54930,9 @@ (INSTANCE ula_\|video_\|cindex\[2\]\~2) (DELAY (ABSOLUTE - (PORT datab (221:221:221) (290:290:290)) - (PORT datad (185:185:185) (209:209:209)) - (IOPATH datab combout (275:275:275) (275:275:275)) + (PORT dataa (347:347:347) (366:366:366)) + (PORT datad (198:198:198) (255:255:255)) + (IOPATH dataa combout (318:318:318) (327:327:327)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -55148,10 +54943,10 @@ (INSTANCE ula_\|video_\|VGA_G\[0\]\~0) (DELAY (ABSOLUTE - (PORT dataa (2150:2150:2150) (2222:2222:2222)) - (PORT datab (379:379:379) (407:407:407)) - (PORT datac (355:355:355) (376:376:376)) - (PORT datad (510:510:510) (500:500:500)) + (PORT dataa (2442:2442:2442) (2494:2494:2494)) + (PORT datab (335:335:335) (363:363:363)) + (PORT datac (547:547:547) (534:534:534)) + (PORT datad (165:165:165) (188:188:188)) (IOPATH dataa combout (307:307:307) (280:280:280)) (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datac combout (220:220:220) (216:216:216)) @@ -55164,9 +54959,9 @@ (INSTANCE ula_\|video_\|VGA_G\[1\]\~1) (DELAY (ABSOLUTE - (PORT dataa (594:594:594) (592:592:592)) - (PORT datab (202:202:202) (236:236:236)) - (PORT datad (352:352:352) (352:352:352)) + (PORT dataa (782:782:782) (755:755:755)) + (PORT datab (336:336:336) (367:367:367)) + (PORT datad (166:166:166) (190:190:190)) (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -55178,9 +54973,9 @@ (INSTANCE ula_\|border\[0\]) (DELAY (ABSOLUTE - (PORT clk (1349:1349:1349) (1365:1365:1365)) - (PORT asdata (1352:1352:1352) (1356:1356:1356)) - (PORT ena (1939:1939:1939) (1935:1935:1935)) + (PORT clk (1337:1337:1337) (1354:1354:1354)) + (PORT asdata (3092:3092:3092) (3171:3171:3171)) + (PORT ena (2199:2199:2199) (2172:2172:2172)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -55194,7 +54989,7 @@ (INSTANCE ula_\|video_\|attr_prefetch\[0\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (1358:1358:1358) (1299:1299:1299)) + (PORT datad (1407:1407:1407) (1354:1354:1354)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -55204,9 +54999,9 @@ (INSTANCE ula_\|video_\|attr_prefetch\[0\]) (DELAY (ABSOLUTE - (PORT clk (1725:1725:1725) (1744:1744:1744)) + (PORT clk (1714:1714:1714) (1734:1734:1734)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (1341:1341:1341) (1316:1316:1316)) + (PORT ena (1280:1280:1280) (1242:1242:1242)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -55220,7 +55015,7 @@ (INSTANCE ula_\|video_\|attr\[0\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (782:782:782) (789:789:789)) + (PORT datad (573:573:573) (610:610:610)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -55230,9 +55025,9 @@ (INSTANCE ula_\|video_\|attr\[0\]) (DELAY (ABSOLUTE - (PORT clk (1357:1357:1357) (1372:1372:1372)) + (PORT clk (1356:1356:1356) (1372:1372:1372)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (1303:1303:1303) (1280:1280:1280)) + (PORT ena (1325:1325:1325) (1285:1285:1285)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -55246,7 +55041,7 @@ (INSTANCE ula_\|video_\|attr_prefetch\[3\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (1179:1179:1179) (1118:1118:1118)) + (PORT datad (1315:1315:1315) (1305:1305:1305)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -55256,9 +55051,9 @@ (INSTANCE ula_\|video_\|attr_prefetch\[3\]) (DELAY (ABSOLUTE - (PORT clk (1725:1725:1725) (1744:1744:1744)) + (PORT clk (1714:1714:1714) (1734:1734:1734)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (1341:1341:1341) (1316:1316:1316)) + (PORT ena (1280:1280:1280) (1242:1242:1242)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -55272,9 +55067,9 @@ (INSTANCE ula_\|video_\|attr\[3\]) (DELAY (ABSOLUTE - (PORT clk (1357:1357:1357) (1373:1373:1373)) - (PORT asdata (884:884:884) (917:917:917)) - (PORT ena (1309:1309:1309) (1287:1287:1287)) + (PORT clk (1356:1356:1356) (1372:1372:1372)) + (PORT asdata (709:709:709) (752:752:752)) + (PORT ena (1325:1325:1325) (1285:1285:1285)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) @@ -55288,9 +55083,9 @@ (INSTANCE ula_\|video_\|cindex\[0\]\~3) (DELAY (ABSOLUTE - (PORT datab (358:358:358) (403:403:403)) - (PORT datad (186:186:186) (210:210:210)) - (IOPATH datab combout (275:275:275) (275:275:275)) + (PORT dataa (222:222:222) (295:295:295)) + (PORT datad (178:178:178) (200:200:200)) + (IOPATH dataa combout (273:273:273) (269:269:269)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -55301,13 +55096,13 @@ (INSTANCE ula_\|video_\|VGA_B\[0\]\~1) (DELAY (ABSOLUTE - (PORT dataa (372:372:372) (405:405:405)) - (PORT datab (1541:1541:1541) (1559:1559:1559)) - (PORT datac (210:210:210) (254:254:254)) - (PORT datad (311:311:311) (320:320:320)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH datab combout (306:306:306) (324:324:324)) - (IOPATH datac combout (218:218:218) (216:216:216)) + (PORT dataa (547:547:547) (548:548:548)) + (PORT datab (1937:1937:1937) (2040:2040:2040)) + (PORT datac (299:299:299) (303:303:303)) + (PORT datad (166:166:166) (189:189:189)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH datab combout (308:308:308) (281:281:281)) + (IOPATH datac combout (220:220:220) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -55317,9 +55112,9 @@ (INSTANCE ula_\|video_\|VGA_B\[1\]\~2) (DELAY (ABSOLUTE - (PORT dataa (243:243:243) (290:290:290)) - (PORT datac (364:364:364) (381:381:381)) - (PORT datad (316:316:316) (325:325:325)) + (PORT dataa (547:547:547) (545:545:545)) + (PORT datac (523:523:523) (517:517:517)) + (PORT datad (165:165:165) (188:188:188)) (IOPATH dataa combout (273:273:273) (269:269:269)) (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -55331,11 +55126,11 @@ (INSTANCE ula_\|video_\|Equal0\~2) (DELAY (ABSOLUTE - (PORT dataa (636:636:636) (662:662:662)) - (PORT datab (256:256:256) (325:325:325)) - (PORT datad (601:601:601) (629:629:629)) - (IOPATH dataa combout (318:318:318) (307:307:307)) - (IOPATH datab combout (336:336:336) (337:337:337)) + (PORT datab (620:620:620) (652:652:652)) + (PORT datac (1069:1069:1069) (1081:1081:1081)) + (PORT datad (901:901:901) (962:962:962)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -55345,7 +55140,7 @@ (INSTANCE ula_\|video_\|VGA_HS\~_Duplicate_1) (DELAY (ABSOLUTE - (PORT clk (1357:1357:1357) (1372:1372:1372)) + (PORT clk (1358:1358:1358) (1374:1374:1374)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -55359,11 +55154,11 @@ (INSTANCE ula_\|video_\|Selector0\~0) (DELAY (ABSOLUTE - (PORT dataa (946:946:946) (919:919:919)) - (PORT datab (207:207:207) (244:244:244)) - (PORT datad (529:529:529) (511:511:511)) - (IOPATH dataa combout (273:273:273) (269:269:269)) - (IOPATH datab combout (308:308:308) (300:300:300)) + (PORT dataa (184:184:184) (221:221:221)) + (PORT datab (540:540:540) (536:536:536)) + (PORT datad (310:310:310) (314:314:314)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -55375,7 +55170,7 @@ (DELAY (ABSOLUTE (PORT clk (1335:1335:1335) (1352:1352:1352)) - (PORT d (1573:1573:1573) (1534:1534:1534)) + (PORT d (1592:1592:1592) (1589:1589:1589)) (IOPATH (posedge clk) q (524:524:524) (534:534:534)) ) ) @@ -55389,7 +55184,7 @@ (INSTANCE ula_\|video_\|VGA_VS\~_Duplicate_1) (DELAY (ABSOLUTE - (PORT clk (1360:1360:1360) (1375:1375:1375)) + (PORT clk (1359:1359:1359) (1375:1375:1375)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -55403,11 +55198,11 @@ (INSTANCE ula_\|video_\|Selector1\~0) (DELAY (ABSOLUTE - (PORT dataa (576:576:576) (562:562:562)) - (PORT datab (1088:1088:1088) (1059:1059:1059)) - (PORT datad (635:635:635) (679:679:679)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH datab combout (273:273:273) (275:275:275)) + (PORT dataa (1024:1024:1024) (979:979:979)) + (PORT datab (1339:1339:1339) (1329:1329:1329)) + (PORT datad (1020:1020:1020) (1011:1011:1011)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -55419,7 +55214,7 @@ (DELAY (ABSOLUTE (PORT clk (1333:1333:1333) (1351:1351:1351)) - (PORT d (1652:1652:1652) (1646:1646:1646)) + (PORT d (1214:1214:1214) (1218:1218:1218)) (IOPATH (posedge clk) q (524:524:524) (534:534:534)) ) ) @@ -55433,7 +55228,7 @@ (INSTANCE z80_\|memory_ifc_\|q1\~feeder) (DELAY (ABSOLUTE - (PORT datad (576:576:576) (598:598:598)) + (PORT datad (229:229:229) (290:290:290)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -55443,10 +55238,10 @@ (INSTANCE z80_\|memory_ifc_\|q1) (DELAY (ABSOLUTE - (PORT clk (1359:1359:1359) (1380:1380:1380)) + (PORT clk (1345:1345:1345) (1363:1363:1363)) (PORT d (67:67:67) (78:78:78)) - (PORT clrn (1405:1405:1405) (1376:1376:1376)) - (PORT ena (1358:1358:1358) (1339:1339:1339)) + (PORT clrn (1389:1389:1389) (1361:1361:1361)) + (PORT ena (1576:1576:1576) (1521:1521:1521)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -55461,10 +55256,10 @@ (INSTANCE z80_\|memory_ifc_\|q2) (DELAY (ABSOLUTE - (PORT clk (1359:1359:1359) (1380:1380:1380)) - (PORT asdata (507:507:507) (569:569:569)) - (PORT clrn (1405:1405:1405) (1376:1376:1376)) - (PORT ena (1358:1358:1358) (1339:1339:1339)) + (PORT clk (1345:1345:1345) (1363:1363:1363)) + (PORT asdata (506:506:506) (568:568:568)) + (PORT clrn (1389:1389:1389) (1361:1361:1361)) + (PORT ena (1576:1576:1576) (1521:1521:1521)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) ) @@ -55479,7 +55274,7 @@ (INSTANCE z80_\|memory_ifc_\|nRFSH_out\~0) (DELAY (ABSOLUTE - (PORT datad (577:577:577) (598:598:598)) + (PORT datad (229:229:229) (291:291:291)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -55490,9 +55285,9 @@ (INSTANCE z80_\|memory_ifc_\|nM1_out) (DELAY (ABSOLUTE - (PORT datac (1191:1191:1191) (1223:1223:1223)) - (PORT datad (578:578:578) (601:601:601)) - (IOPATH datac combout (218:218:218) (215:215:215)) + (PORT dataa (2355:2355:2355) (2420:2420:2420)) + (PORT datad (229:229:229) (292:292:292)) + (IOPATH dataa combout (329:329:329) (332:332:332)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -55502,11 +55297,11 @@ (INSTANCE ula_\|beep\~0) (DELAY (ABSOLUTE - (PORT datab (1602:1602:1602) (1633:1633:1633)) - (PORT datac (2798:2798:2798) (3004:3004:3004)) - (PORT datad (1172:1172:1172) (1181:1181:1181)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datac combout (220:220:220) (216:216:216)) + (PORT dataa (3328:3328:3328) (3647:3647:3647)) + (PORT datab (1060:1060:1060) (1042:1042:1042)) + (PORT datad (1175:1175:1175) (1137:1137:1137)) + (IOPATH dataa combout (329:329:329) (332:332:332)) + (IOPATH datab combout (336:336:336) (337:337:337)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -55516,9 +55311,9 @@ (INSTANCE ula_\|beep) (DELAY (ABSOLUTE - (PORT clk (1337:1337:1337) (1355:1355:1355)) + (PORT clk (1330:1330:1330) (1349:1349:1349)) (PORT d (67:67:67) (78:78:78)) - (PORT ena (2376:2376:2376) (2363:2363:2363)) + (PORT ena (2265:2265:2265) (2193:2193:2193)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) ) diff --git a/simulation/modelsim/spectrum_6_1200mv_85c_slow.vo b/simulation/modelsim/spectrum_6_1200mv_85c_slow.vo index ef4a25d..5766d95 100644 --- a/simulation/modelsim/spectrum_6_1200mv_85c_slow.vo +++ b/simulation/modelsim/spectrum_6_1200mv_85c_slow.vo @@ -16,7 +16,7 @@ // PROGRAM "Quartus II 32-bit" // VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" -// DATE "04/01/2022 18:55:51" +// DATE "04/02/2022 15:53:43" // // Device: Altera EP4CE22F17C6 Package FBGA256 @@ -56,8 +56,8 @@ input CLOCK_50; input [1:0] KEY; input PS2_CLK; input PS2_DAT; -output I2C_SCLK; -output I2C_SDAT; +inout I2C_SCLK; +inout I2C_SDAT; output AUD_XCK; output AUD_ADCLRCK; output AUD_DACLRCK; @@ -178,786 +178,67 @@ wire \SW[2]~input_o ; wire \ula_|clocks_|clk_cpu~0_combout ; wire \ula_|clocks_|clk_cpu~q ; wire \ula_|clocks_|clk_cpu~clkctrl_outclk ; -wire \z80_|sequencer_|DFFE_M1_ff~0_combout ; -wire \z80_|sequencer_|ena_M~combout ; +wire \z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ; +wire \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ; wire \KEY[1]~input_o ; wire \z80_|interrupts_|nmi_armed~feeder_combout ; wire \z80_|interrupts_|SYNTHESIZED_WIRE_9~combout ; wire \z80_|interrupts_|nmi_armed~q ; wire \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder_combout ; -wire \z80_|execute_|ctl_eval_cond~0_combout ; -wire \z80_|execute_|ixy_d~4_combout ; +wire \z80_|sequencer_|DFFE_M2_ff~0_combout ; +wire \z80_|sequencer_|DFFE_M2_ff~q ; wire \z80_|sequencer_|DFFE_M3_ff~0_combout ; wire \z80_|sequencer_|DFFE_M3_ff~q ; -wire \z80_|execute_|fIOWrite~1_combout ; wire \z80_|sequencer_|DFFE_M4_ff~0_combout ; wire \z80_|sequencer_|DFFE_M4_ff~q ; -wire \z80_|pla_decode_|Equal32~0_combout ; -wire \z80_|resets_|SYNTHESIZED_WIRE_11~combout ; -wire \z80_|decode_state_|table_xx~0_combout ; -wire \z80_|pla_decode_|Equal1~7_combout ; -wire \z80_|pla_decode_|Equal2~0_combout ; -wire \z80_|pla_decode_|Equal36~0_combout ; -wire \z80_|execute_|ctl_state_tbl_cb_set~combout ; -wire \z80_|execute_|ctl_state_tbl_we~8_combout ; -wire \z80_|decode_state_|DFFE_instCB~q ; -wire \z80_|pla_decode_|Equal52~0_combout ; -wire \z80_|pla_decode_|Equal2~1_combout ; -wire \z80_|execute_|ctl_state_tbl_ed_set~combout ; -wire \z80_|decode_state_|DFFE_instED~q ; -wire \z80_|pla_decode_|Equal13~0_combout ; -wire \z80_|pla_decode_|Equal33~0_combout ; -wire \z80_|execute_|ctl_im_we~combout ; -wire \z80_|pla_decode_|Equal49~0_combout ; -wire \z80_|pla_decode_|Equal33~1_combout ; -wire \z80_|pla_decode_|Equal6~0_combout ; -wire \z80_|execute_|ctl_mRead~14_combout ; -wire \z80_|pla_decode_|Equal12~0_combout ; -wire \z80_|execute_|ctl_sw_1d~8_combout ; -wire \z80_|nM1_int~2_combout ; -wire \z80_|execute_|ctl_sw_1d~5_combout ; -wire \z80_|pla_decode_|Equal3~0_combout ; -wire \z80_|execute_|ctl_mRead~4_combout ; -wire \z80_|execute_|ixy_d~7_combout ; -wire \z80_|execute_|ctl_state_alu~4_combout ; -wire \z80_|execute_|ctl_sw_1d~4_combout ; -wire \z80_|pla_decode_|Equal40~1_combout ; -wire \z80_|pla_decode_|Equal39~0_combout ; -wire \z80_|execute_|ctl_bus_db_oe~1_combout ; -wire \z80_|pla_decode_|Equal13~1_combout ; -wire \z80_|pla_decode_|Equal13~2_combout ; -wire \z80_|pla_decode_|Equal3~2_combout ; -wire \z80_|execute_|ctl_state_iy_set~2_combout ; -wire \z80_|execute_|ixy_d~8_combout ; -wire \z80_|execute_|ixy_d~6_combout ; -wire \z80_|execute_|ixy_d~9_combout ; -wire \z80_|execute_|ixy_d~12_combout ; -wire \z80_|execute_|ixy_d~10_combout ; -wire \z80_|pla_decode_|Equal44~0_combout ; -wire \z80_|execute_|ixy_d~16_combout ; -wire \z80_|execute_|ixy_d~13_combout ; -wire \z80_|pla_decode_|Equal50~0_combout ; -wire \z80_|pla_decode_|Equal33~2_combout ; -wire \z80_|execute_|ixy_d~17_combout ; -wire \z80_|execute_|ixy_d~5_combout ; -wire \z80_|execute_|ixy_d~14_combout ; -wire \z80_|execute_|ixy_d~11_combout ; -wire \z80_|execute_|ixy_d~15_combout ; -wire \z80_|execute_|ctl_state_ixiy_we~2_combout ; -wire \z80_|decode_state_|DFFE_instIY1~q ; -wire \z80_|execute_|ctl_ir_we~5_combout ; -wire \z80_|execute_|ctl_ir_we~14_combout ; -wire \z80_|execute_|ctl_mWrite~2_combout ; -wire \z80_|execute_|ctl_mWrite~16_combout ; -wire \z80_|execute_|ctl_flags_alu~18_combout ; -wire \z80_|execute_|ctl_mRead~26_combout ; -wire \z80_|execute_|ctl_mRead~27_combout ; -wire \z80_|execute_|ctl_bus_db_oe~7_combout ; -wire \z80_|execute_|ctl_sw_2d~5_combout ; -wire \z80_|execute_|ctl_mRead~18_combout ; -wire \z80_|pla_decode_|Equal55~0_combout ; -wire \z80_|execute_|comb~1_combout ; -wire \z80_|execute_|ctl_mRead~15_combout ; -wire \z80_|execute_|ctl_mRead~17_combout ; -wire \z80_|execute_|ctl_reg_in_hi~5_combout ; -wire \z80_|execute_|ctl_mRead~9_combout ; -wire \z80_|pla_decode_|Equal9~0_combout ; -wire \z80_|execute_|ctl_mRead~10_combout ; -wire \z80_|execute_|ctl_mRead~8_combout ; -wire \z80_|execute_|ctl_mRead~20_combout ; -wire \z80_|pla_decode_|Equal12~1_combout ; -wire \z80_|pla_decode_|Equal9~1_combout ; -wire \z80_|pla_decode_|Equal25~0_combout ; -wire \z80_|execute_|ctl_mRead~21_combout ; -wire \z80_|execute_|ctl_state_alu~6_combout ; -wire \z80_|pla_decode_|Equal19~0_combout ; -wire \z80_|pla_decode_|Equal1~4_combout ; -wire \z80_|pla_decode_|Equal29~0_combout ; -wire \z80_|pla_decode_|Equal24~1_combout ; -wire \z80_|pla_decode_|Equal34~0_combout ; -wire \z80_|pla_decode_|Equal37~0_combout ; -wire \z80_|pla_decode_|Equal35~0_combout ; -wire \z80_|pla_decode_|Equal38~2_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~2_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~3_combout ; -wire \z80_|execute_|comb~0_combout ; -wire \z80_|pla_decode_|Equal47~0_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~4_combout ; -wire \z80_|execute_|ctl_mRead~22_combout ; -wire \z80_|execute_|ctl_mRead~24_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ; -wire \z80_|execute_|ctl_reg_in_hi~6_combout ; -wire \z80_|pla_decode_|Equal6~1_combout ; -wire \z80_|execute_|ctl_mRead~16_combout ; wire \z80_|sequencer_|M5~0_combout ; wire \z80_|sequencer_|M5~q ; -wire \z80_|execute_|ctl_reg_in_hi~2_combout ; -wire \z80_|execute_|setM1~29_combout ; -wire \z80_|execute_|ctl_mRead~25_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~6_combout ; -wire \z80_|execute_|ctl_ir_we~7_combout ; -wire \z80_|pla_decode_|Equal52~1_combout ; -wire \z80_|execute_|ctl_state_alu~14_combout ; -wire \z80_|execute_|ctl_state_alu~8_combout ; -wire \z80_|pla_decode_|Equal24~0_combout ; -wire \z80_|reg_control_|reg_sel_pc~0_combout ; -wire \z80_|reg_control_|reg_sel_pc~1_combout ; -wire \z80_|reg_control_|reg_sel_pc~2_combout ; -wire \z80_|execute_|fMRead~17_combout ; -wire \z80_|execute_|ctl_mRead~6_combout ; -wire \z80_|pla_decode_|Equal11~0_combout ; -wire \z80_|pla_decode_|Equal10~0_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~9_combout ; -wire \z80_|execute_|ctl_sw_2d~4_combout ; -wire \z80_|execute_|ctl_ir_we~15_combout ; -wire \z80_|execute_|fMRead~16_combout ; -wire \z80_|execute_|ctl_ir_we~9_combout ; -wire \z80_|pla_decode_|Equal46~0_combout ; -wire \z80_|execute_|ctl_ir_we~10_combout ; -wire \z80_|execute_|ctl_flags_alu~17_combout ; -wire \z80_|execute_|ctl_flags_alu~6_combout ; -wire \z80_|execute_|ctl_ir_we~6_combout ; -wire \z80_|execute_|ctl_ir_we~8_combout ; -wire \z80_|execute_|ctl_flags_alu~16_combout ; -wire \z80_|execute_|ctl_reg_in_hi~3_combout ; -wire \z80_|execute_|ctl_mWrite~8_combout ; -wire \z80_|execute_|fMRead~18_combout ; -wire \z80_|execute_|fMRead~19_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~16_combout ; -wire \z80_|execute_|ctl_mRead~36_combout ; -wire \z80_|execute_|ctl_alu_op_low~9_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~44_combout ; -wire \z80_|execute_|ctl_mRead~11_combout ; -wire \z80_|execute_|ctl_sw_2d~6_combout ; -wire \z80_|execute_|ctl_sw_2d~7_combout ; -wire \z80_|execute_|ctl_mWrite~7_combout ; -wire \z80_|execute_|ctl_ir_we~11_combout ; -wire \z80_|execute_|ctl_ir_we~12_combout ; -wire \z80_|execute_|ctl_flags_sz_we~0_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ; -wire \z80_|execute_|ctl_sw_2d~8_combout ; -wire \z80_|execute_|ctl_sw_2d~9_combout ; -wire \z80_|execute_|ctl_sw_1d~6_combout ; -wire \z80_|execute_|ctl_sw_1d~7_combout ; -wire \z80_|execute_|ctl_alu_op_low~8_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ; -wire \z80_|execute_|ctl_reg_out_hi~4_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~15_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~38_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_zero~combout ; -wire \z80_|alu_|db_low[2]~4_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~14_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ; -wire \z80_|execute_|ctl_sw_4u~1_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~5_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~30_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~29_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~31_combout ; -wire \z80_|pla_decode_|Equal69~0_combout ; -wire \z80_|pla_decode_|Equal1~5_combout ; -wire \z80_|execute_|ctl_alu_op_low~14_combout ; -wire \z80_|execute_|ctl_alu_op_low~12_combout ; -wire \z80_|pla_decode_|Equal56~0_combout ; -wire \z80_|execute_|ctl_alu_op_low~11_combout ; -wire \z80_|execute_|nextM~2_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~16_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~4_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~5_combout ; -wire \z80_|execute_|ctl_alu_oe~3_combout ; -wire \z80_|execute_|ctl_alu_op_low~15_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~8_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~9_combout ; -wire \z80_|execute_|ctl_alu_core_R~3_combout ; -wire \z80_|execute_|ctl_alu_core_R~4_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~10_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~11_combout ; -wire \z80_|pla_decode_|Equal48~0_combout ; -wire \z80_|execute_|ctl_flags_hf2_we~combout ; -wire \z80_|execute_|ctl_alu_shift_oe~41_combout ; -wire \z80_|execute_|ctl_flags_xy_we~18_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~17_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~19_combout ; -wire \z80_|execute_|ctl_iorw~10_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~18_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~20_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~13_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~9_combout ; -wire \z80_|execute_|ctl_bus_db_oe~3_combout ; -wire \z80_|pla_decode_|Equal20~0_combout ; -wire \z80_|pla_decode_|Equal68~2_combout ; -wire \z80_|execute_|ctl_flags_bus~14_combout ; -wire \z80_|execute_|ctl_alu_op_low~13_combout ; -wire \z80_|execute_|ctl_flags_bus~15_combout ; -wire \z80_|execute_|ctl_flags_bus~11_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~11_combout ; -wire \z80_|execute_|ctl_flags_bus~10_combout ; -wire \z80_|execute_|ctl_flags_bus~8_combout ; -wire \z80_|execute_|ctl_flags_bus~9_combout ; -wire \z80_|execute_|ctl_flags_bus~12_combout ; -wire \z80_|execute_|ctl_flags_xy_we~11_combout ; -wire \z80_|execute_|ctl_flags_xy_we~12_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~6_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~7_combout ; -wire \z80_|execute_|ctl_ir_we~4_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~8_combout ; -wire \z80_|execute_|ctl_bus_db_oe~0_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~12_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~13_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~14_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~15_combout ; -wire \z80_|execute_|ctl_66_oe~2_combout ; -wire \z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ; -wire \z80_|execute_|ctl_alu_op1_sel_zero~5_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_zero~4_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_zero~combout ; -wire \z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_lq~combout ; -wire \z80_|execute_|ctl_alu_op_low~10_combout ; -wire \z80_|execute_|fMWrite~11_combout ; -wire \z80_|execute_|ctl_alu_op_low~21_combout ; +wire \z80_|execute_|ixy_d~5_combout ; wire \z80_|execute_|ctl_alu_op_low~22_combout ; -wire \z80_|execute_|ctl_alu_op_low~16_combout ; -wire \z80_|execute_|ctl_alu_op_low~17_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ; -wire \z80_|execute_|ctl_reg_gp_sel~36_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~4_combout ; -wire \z80_|execute_|ctl_state_alu~5_combout ; -wire \z80_|execute_|ctl_alu_op_low~18_combout ; -wire \z80_|execute_|ctl_alu_op_low~19_combout ; -wire \z80_|execute_|ctl_alu_op_low~33_combout ; -wire \z80_|execute_|ctl_alu_op_low~20_combout ; -wire \z80_|execute_|ctl_alu_op_low~23_combout ; -wire \z80_|execute_|ctl_alu_op_low~24_combout ; -wire \z80_|execute_|ctl_alu_op_low~25_combout ; -wire \z80_|execute_|ctl_alu_op_low~34_combout ; -wire \z80_|execute_|ctl_alu_op_low~combout ; -wire \z80_|execute_|ctl_alu_shift_oe~40_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~37_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~39_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~46_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~42_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~21_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~45_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~22_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~23_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~24_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~25_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~14_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~26_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~27_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~28_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~10_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~11_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~32_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~33_combout ; -wire \z80_|execute_|ctl_reg_use_sp~0_combout ; -wire \z80_|execute_|ctl_reg_use_sp~1_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~12_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~47_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~34_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~35_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~36_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~43_combout ; -wire \z80_|execute_|ctl_reg_in_lo~9_combout ; -wire \z80_|execute_|ctl_alu_op1_oe~0_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ; -wire \z80_|execute_|ctl_alu_op1_oe~1_combout ; -wire \z80_|execute_|ctl_flags_xy_we~8_combout ; -wire \z80_|execute_|ctl_flags_xy_we~9_combout ; -wire \z80_|pla_decode_|Equal8~0_combout ; -wire \z80_|execute_|ctl_flags_alu~9_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~4_combout ; -wire \z80_|execute_|ctl_flags_sz_we~3_combout ; -wire \z80_|pla_decode_|Equal11~1_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ; -wire \z80_|execute_|ctl_flags_alu~10_combout ; -wire \z80_|execute_|ctl_flags_alu~11_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ; -wire \z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ; -wire \z80_|execute_|ctl_flags_use_cf2~13_combout ; -wire \z80_|execute_|ctl_flags_cf_we~7_combout ; -wire \z80_|execute_|ctl_pf_sel[0]~2_combout ; -wire \z80_|execute_|ctl_alu_oe~2_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~25_combout ; -wire \z80_|execute_|ctl_flags_hf_we~5_combout ; -wire \z80_|execute_|ctl_flags_pf_we~10_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ; -wire \z80_|execute_|ctl_flags_pf_we~2_combout ; -wire \z80_|execute_|ctl_flags_pf_we~3_combout ; -wire \z80_|execute_|ctl_flags_xy_we~17_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~5_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~6_combout ; -wire \z80_|execute_|ctl_flags_xy_we~10_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ; -wire \z80_|execute_|ctl_state_alu~7_combout ; -wire \z80_|execute_|ctl_flags_sz_we~1_combout ; -wire \z80_|execute_|ctl_flags_cf_we~2_combout ; -wire \z80_|execute_|ctl_alu_core_S~6_combout ; -wire \z80_|execute_|ctl_alu_core_S~7_combout ; -wire \z80_|execute_|ctl_alu_core_S~4_combout ; -wire \z80_|execute_|ctl_alu_core_S~5_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ; -wire \z80_|execute_|ctl_alu_res_oe~0_combout ; -wire \z80_|execute_|ctl_alu_oe~15_combout ; -wire \z80_|execute_|ctl_alu_res_oe~1_combout ; -wire \z80_|execute_|ctl_alu_res_oe~2_combout ; -wire \z80_|execute_|ctl_alu_op2_oe~0_combout ; -wire \z80_|alu_|db_high[3]~2_combout ; -wire \z80_|alu_|db_high[3]~3_combout ; -wire \z80_|alu_|db_low[2]~24_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~7_combout ; -wire \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ; -wire \z80_|execute_|ctl_reg_in_hi~8_combout ; -wire \z80_|execute_|ctl_alu_oe~8_combout ; -wire \z80_|execute_|ctl_alu_oe~4_combout ; -wire \z80_|execute_|ctl_mWrite~9_combout ; -wire \z80_|execute_|ctl_alu_core_S~10_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~43_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~26_combout ; -wire \z80_|execute_|ctl_bus_db_we~5_combout ; -wire \z80_|execute_|ctl_alu_oe~9_combout ; -wire \z80_|execute_|ctl_alu_oe~11_combout ; -wire \z80_|execute_|ctl_alu_oe~5_combout ; -wire \z80_|execute_|ctl_alu_core_S~11_combout ; -wire \z80_|execute_|ctl_alu_oe~6_combout ; -wire \z80_|execute_|ctl_alu_oe~7_combout ; -wire \z80_|execute_|ctl_alu_oe~12_combout ; -wire \z80_|execute_|ctl_alu_oe~13_combout ; -wire \z80_|execute_|ctl_alu_oe~14_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~24_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~27_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ; -wire \z80_|execute_|ctl_reg_out_hi~8_combout ; -wire \z80_|execute_|setM1~54_combout ; -wire \z80_|execute_|ctl_sw_2u~1_combout ; -wire \z80_|execute_|ctl_sw_2u~4_combout ; -wire \z80_|execute_|ctl_sw_2u~5_combout ; -wire \z80_|execute_|ctl_sw_2u~6_combout ; -wire \z80_|execute_|ctl_inc_cy~35_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ; -wire \z80_|execute_|ctl_mWrite~6_combout ; -wire \z80_|execute_|ctl_sw_2u~2_combout ; -wire \z80_|execute_|ctl_sw_2u~0_combout ; -wire \z80_|execute_|ctl_sw_2u~3_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ; -wire \z80_|execute_|ctl_reg_out_lo~2_combout ; -wire \z80_|execute_|rsel3~combout ; -wire \z80_|execute_|ctl_reg_out_hi~5_combout ; -wire \z80_|execute_|ctl_reg_out_hi~6_combout ; -wire \z80_|execute_|ctl_reg_out_hi~7_combout ; -wire \z80_|execute_|rsel0~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ; -wire \z80_|execute_|ctl_reg_out_lo~6_combout ; -wire \z80_|execute_|ctl_reg_out_lo~7_combout ; -wire \z80_|execute_|ctl_iorw~11_combout ; -wire \z80_|execute_|ctl_sw_2d~10_combout ; -wire \z80_|execute_|ctl_sw_2d~14_combout ; -wire \z80_|execute_|ctl_sw_2d~11_combout ; -wire \z80_|execute_|ctl_sw_2d~12_combout ; -wire \z80_|execute_|ctl_sw_2d~13_combout ; -wire \z80_|execute_|ctl_66_oe~combout ; -wire \z80_|execute_|ctl_inc_cy~34_combout ; -wire \z80_|execute_|ctl_apin_mux~0_combout ; -wire \z80_|execute_|ctl_sw_4u~5_combout ; -wire \z80_|execute_|ctl_inc_cy~75_combout ; -wire \z80_|execute_|ctl_inc_cy~76_combout ; -wire \z80_|pla_decode_|Equal4~0_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~48_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~46_combout ; -wire \z80_|execute_|ctl_inc_cy~53_combout ; -wire \z80_|execute_|ctl_inc_cy~92_combout ; -wire \z80_|pla_decode_|Equal19~1_combout ; -wire \z80_|execute_|ctl_sw_4u~0_combout ; -wire \z80_|execute_|ctl_inc_cy~38_combout ; -wire \z80_|execute_|ctl_inc_cy~93_combout ; -wire \z80_|execute_|ctl_inc_cy~39_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~24_combout ; -wire \z80_|execute_|ctl_reg_gp_we~1_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ; -wire \z80_|execute_|ctl_bus_inc_oe~44_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~5_combout ; -wire \z80_|execute_|ctl_reg_gp_we~0_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ; -wire \z80_|execute_|ctl_sw_4u~2_combout ; -wire \z80_|execute_|ctl_sw_4u~3_combout ; -wire \z80_|execute_|fMRead~3_combout ; -wire \z80_|execute_|ctl_sw_4u~4_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ; -wire \z80_|execute_|ctl_reg_sel_wz~15_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ; -wire \z80_|execute_|ctl_inc_cy~94_combout ; -wire \z80_|execute_|ctl_inc_cy~87_combout ; -wire \z80_|execute_|ctl_inc_cy~42_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~16_combout ; -wire \z80_|execute_|ctl_sw_4u~6_combout ; -wire \z80_|pla_decode_|Equal2~2_combout ; -wire \z80_|pla_decode_|Equal1~6_combout ; -wire \z80_|reg_control_|bank_exx~2_combout ; -wire \z80_|reg_control_|bank_exx~q ; -wire \z80_|reg_control_|bank_hl_de1~0_combout ; -wire \z80_|reg_control_|bank_hl_de1~q ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~10_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~11_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~12_combout ; -wire \z80_|execute_|ctl_mRead~7_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~9_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~37_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~13_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ; -wire \z80_|execute_|fMWrite~3_combout ; -wire \z80_|execute_|ctl_flags_bus~5_combout ; -wire \z80_|execute_|fMRead~2_combout ; -wire \z80_|execute_|ctl_mRead~19_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~7_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~8_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~14_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~16_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~15_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~17_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~19_combout ; -wire \z80_|execute_|ctl_reg_use_sp~2_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~47_combout ; -wire \z80_|execute_|ctl_reg_use_sp~3_combout ; -wire \z80_|execute_|ctl_sw_1d~9_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~21_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~20_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~22_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~18_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~23_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~28_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ; -wire \z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ; -wire \z80_|execute_|ctl_flags_hf_cpl~14_combout ; -wire \z80_|execute_|ctl_flags_hf_cpl~10_combout ; -wire \z80_|execute_|setM1~47_combout ; -wire \z80_|execute_|setM1~48_combout ; -wire \z80_|execute_|ctl_al_we~13_combout ; -wire \z80_|execute_|ctl_flags_oe~0_combout ; -wire \z80_|execute_|ctl_flags_oe~1_combout ; -wire \z80_|execute_|ctl_reg_in_hi~13_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~29_combout ; -wire \z80_|execute_|ctl_inc_cy~40_combout ; -wire \z80_|execute_|ctl_inc_dec~2_combout ; -wire \z80_|execute_|ctl_inc_dec~12_combout ; -wire \z80_|execute_|ctl_inc_cy~43_combout ; -wire \z80_|execute_|ctl_inc_dec~5_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~4_combout ; -wire \z80_|execute_|fMRead~6_combout ; -wire \z80_|execute_|fMRead~7_combout ; -wire \z80_|execute_|fMRead~8_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~26_combout ; -wire \z80_|execute_|ctl_state_alu~13_combout ; -wire \z80_|execute_|ctl_state_alu~10_combout ; -wire \z80_|execute_|ctl_state_alu~11_combout ; -wire \z80_|execute_|ctl_state_alu~9_combout ; -wire \z80_|pla_decode_|Equal62~2_combout ; -wire \z80_|execute_|ctl_flags_pf_we~4_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ; -wire \z80_|pla_decode_|Equal64~0_combout ; -wire \z80_|execute_|ctl_pf_sel[0]~3_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ; -wire \z80_|execute_|ctl_state_alu~15_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~25_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~30_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~31_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~33_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~34_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo~20_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~32_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ; -wire \z80_|reg_control_|reg_sel_de2~5_combout ; -wire \z80_|reg_control_|reg_sel_de2~6_combout ; -wire \z80_|reg_control_|reg_sel_hl~0_combout ; -wire \z80_|reg_control_|bank_hl_de2~0_combout ; -wire \z80_|reg_control_|bank_hl_de2~q ; -wire \z80_|reg_control_|reg_sel_hl2~0_combout ; -wire \z80_|execute_|ctl_reg_in_hi~7_combout ; -wire \z80_|execute_|ctl_reg_gp_we~4_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ; -wire \z80_|execute_|ctl_reg_gp_we~3_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~13_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5~combout ; -wire \z80_|execute_|ctl_reg_gp_we~2_combout ; -wire \z80_|execute_|ctl_reg_gp_we~5_combout ; -wire \z80_|execute_|ctl_reg_gp_we~6_combout ; -wire \z80_|execute_|ctl_al_we~14_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~32_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ; -wire \z80_|execute_|setM1~40_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~93_combout ; -wire \z80_|reg_control_|reg_sel_de~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ; -wire \z80_|execute_|ctl_reg_in_hi~9_combout ; -wire \z80_|execute_|ctl_reg_in_hi~10_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~19_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ; -wire \z80_|execute_|ctl_reg_in_lo~8_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~19_combout ; -wire \z80_|execute_|ctl_reg_use_sp~4_combout ; -wire \z80_|execute_|ctl_reg_use_sp~5_combout ; -wire \z80_|execute_|ctl_reg_use_sp~6_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ; -wire \z80_|pla_decode_|Equal21~2_combout ; -wire \z80_|reg_control_|bank_af~0_combout ; -wire \z80_|reg_control_|bank_af~q ; -wire \z80_|reg_control_|reg_sel_af~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ; -wire \z80_|reg_control_|reg_sel_af2~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ; -wire \z80_|execute_|ctl_reg_sel_wz~12_combout ; -wire \z80_|execute_|ctl_flags_bus~4_combout ; -wire \z80_|execute_|ctl_flags_bus~6_combout ; -wire \z80_|execute_|ctl_flags_bus~7_combout ; -wire \z80_|execute_|fMRead~24_combout ; -wire \z80_|execute_|ctl_flags_bus~13_combout ; -wire \z80_|execute_|ctl_flags_bus~combout ; -wire \z80_|execute_|ctl_inc_dec~3_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~2_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~3_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~6_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~5_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~4_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~7_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~8_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~9_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~10_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~29_combout ; -wire \z80_|execute_|ctl_mRead~13_combout ; -wire \z80_|execute_|pc_inc_hold~49_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~9_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ; -wire \z80_|execute_|pc_inc_hold~28_combout ; -wire \z80_|execute_|setM1~35_combout ; -wire \z80_|execute_|setM1~36_combout ; -wire \z80_|execute_|fMRead~5_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~31_combout ; -wire \z80_|execute_|pc_inc_hold~29_combout ; -wire \z80_|execute_|ctl_reg_sys_we~1_combout ; -wire \z80_|execute_|ctl_reg_sys_we~2_combout ; -wire \z80_|pla_decode_|Equal33~3_combout ; -wire \z80_|execute_|ctl_reg_sys_we~0_combout ; -wire \z80_|execute_|ctl_reg_sys_we~3_combout ; -wire \z80_|execute_|ctl_reg_sys_we_lo~2_combout ; -wire \z80_|execute_|ctl_reg_sys_we_lo~3_combout ; -wire \z80_|execute_|ctl_reg_sys_we_lo~4_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~combout ; -wire \z80_|execute_|ctl_reg_sel_ir~0_combout ; -wire \z80_|execute_|ctl_reg_sel_ir~1_combout ; -wire \z80_|execute_|ctl_reg_out_lo~9_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~36_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ; -wire \z80_|execute_|ctl_reg_in_hi~4_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~4_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ; -wire \z80_|execute_|ctl_reg_sel_wz~5_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~6_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~7_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo~16_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~11_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~12_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~13_combout ; -wire \z80_|execute_|ctl_al_we~4_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~38_combout ; -wire \z80_|execute_|fMRead~0_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ; -wire \z80_|execute_|ctl_inc_dec~4_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~9_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~8_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ; -wire \z80_|execute_|ctl_al_we~5_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~18_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[0]~37_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ; -wire \z80_|execute_|ctl_bus_inc_oe~38_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~39_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~30_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~45_combout ; -wire \z80_|execute_|fMRead~1_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~36_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~27_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~28_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~37_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~40_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~35_combout ; -wire \z80_|execute_|ctl_inc_cy~77_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~32_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~33_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~34_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~41_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~10_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~11_combout ; -wire \z80_|execute_|ctl_sw_4d~3_combout ; -wire \z80_|execute_|ctl_sw_4d~4_combout ; -wire \z80_|execute_|ctl_sw_4d~2_combout ; -wire \z80_|execute_|ctl_sw_4d~5_combout ; -wire \z80_|execute_|setM1~45_combout ; -wire \z80_|execute_|setM1~46_combout ; -wire \z80_|execute_|ctl_sw_4d~1_combout ; -wire \z80_|execute_|ctl_sw_4d~0_combout ; -wire \z80_|execute_|ctl_sw_4d~6_combout ; -wire \z80_|execute_|fMRead~4_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~16_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~14_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~20_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~15_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~17_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~18_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~19_combout ; -wire \z80_|reg_control_|reg_sel_pc~3_combout ; -wire \z80_|reg_control_|reg_sel_pc~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ; -wire \z80_|reg_file_|db_lo_as[0]~2_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ; -wire \z80_|reg_file_|db_lo_as[7]~22_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ; -wire \z80_|reg_file_|db_lo_as[7]~23_combout ; -wire \z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ; -wire \z80_|resets_|SYNTHESIZED_WIRE_10~q ; -wire \z80_|resets_|SYNTHESIZED_WIRE_9~q ; -wire \z80_|resets_|DFFE_intr_ff3~q ; -wire \ula_|pll_|altpll_component|auto_generated|wire_pll1_locked ; -wire \KEY[0]~input_o ; -wire \reset~combout ; -wire \z80_|resets_|x1~0_combout ; -wire \z80_|fpga_reset~feeder_combout ; -wire \z80_|fpga_reset~q ; -wire \z80_|fpga_reset~clkctrl_outclk ; -wire \z80_|resets_|x1~q ; -wire \z80_|resets_|clrpc_int~0_combout ; -wire \z80_|resets_|clrpc_int~q ; -wire \z80_|resets_|clrpc~0_combout ; -wire \z80_|execute_|ctl_apin_mux~1_combout ; -wire \z80_|execute_|ctl_al_we~6_combout ; -wire \z80_|execute_|ctl_al_we~7_combout ; -wire \z80_|execute_|ctl_al_we~8_combout ; -wire \z80_|execute_|ctl_alu_oe~10_combout ; -wire \z80_|execute_|ctl_al_we~9_combout ; -wire \z80_|execute_|ctl_al_we~10_combout ; -wire \z80_|execute_|ctl_al_we~11_combout ; -wire \z80_|execute_|ctl_al_we~12_combout ; -wire \z80_|execute_|ctl_inc_dec~6_combout ; -wire \z80_|execute_|fIOWrite~0_combout ; -wire \z80_|execute_|ctl_inc_dec~8_combout ; -wire \z80_|execute_|ctl_inc_dec~9_combout ; -wire \z80_|execute_|ctl_inc_dec~10_combout ; -wire \z80_|execute_|ctl_inc_dec~7_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~34_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ; -wire \z80_|reg_control_|reg_sel_de2~4_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~33_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~36_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~37_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~39_combout ; -wire \z80_|reg_control_|reg_sel_iy~2_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~38_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ; -wire \z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~35_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~40_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~41_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~42_combout ; -wire \z80_|reg_file_|db_lo_as[2]~7_combout ; -wire \z80_|reg_file_|db_lo_as[2]~8_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~10_combout ; -wire \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~11_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~15_combout ; -wire \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~14_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~16_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~12_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~13_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~17_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~22_combout ; -wire \z80_|reg_file_|db_lo_as[0]~0_combout ; -wire \z80_|reg_file_|db_lo_as[0]~1_combout ; -wire \z80_|execute_|ctl_inc_cy~72_combout ; +wire \z80_|resets_|SYNTHESIZED_WIRE_11~combout ; +wire \z80_|execute_|ctl_ir_we~4_combout ; +wire \z80_|execute_|ctl_state_iy_set~2_combout ; +wire \z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ; +wire \z80_|sequencer_|DFFE_T5_ff~q ; +wire \z80_|execute_|ctl_state_ixiy_we~2_combout ; +wire \z80_|decode_state_|DFFE_instIY1~q ; +wire \z80_|decode_state_|use_ixiy~combout ; +wire \z80_|execute_|ixy_d~4_combout ; +wire \z80_|execute_|ixy_d~11_combout ; +wire \z80_|execute_|ixy_d~9_combout ; +wire \z80_|execute_|ixy_d~7_combout ; +wire \z80_|execute_|ixy_d~6_combout ; +wire \z80_|execute_|ixy_d~8_combout ; +wire \z80_|execute_|ixy_d~12_combout ; +wire \z80_|pla_decode_|Equal33~0_combout ; +wire \z80_|pla_decode_|Equal33~1_combout ; +wire \z80_|pla_decode_|Equal33~2_combout ; +wire \z80_|pla_decode_|Equal21~0_combout ; +wire \z80_|pla_decode_|Equal77~0_combout ; +wire \z80_|pla_decode_|Equal77~1_combout ; +wire \z80_|pla_decode_|Equal1~7_combout ; +wire \z80_|pla_decode_|Equal79~0_combout ; +wire \z80_|interrupts_|iff1~0_combout ; +wire \z80_|interrupts_|DFFE_instIFF2~0_combout ; +wire \z80_|interrupts_|SYNTHESIZED_WIRE_12~combout ; +wire \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl_outclk ; +wire \z80_|interrupts_|DFFE_instIFF2~q ; +wire \z80_|pla_decode_|Equal13~0_combout ; +wire \z80_|pla_decode_|Equal38~2_combout ; +wire \z80_|interrupts_|iff1~1_combout ; +wire \z80_|interrupts_|SYNTHESIZED_WIRE_15~combout ; +wire \z80_|interrupts_|iff1~q ; wire \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ; -wire \ula_|video_|Add0~15 ; -wire \ula_|video_|Add0~16_combout ; -wire \ula_|video_|vga_hc~2_combout ; -wire \ula_|video_|Add0~17 ; -wire \ula_|video_|Add0~18_combout ; -wire \ula_|video_|vga_hc~1_combout ; wire \ula_|video_|Add0~0_combout ; wire \ula_|video_|vga_hc~3_combout ; wire \ula_|video_|Add0~1 ; wire \ula_|video_|Add0~2_combout ; -wire \ula_|video_|vga_hc[1]~feeder_combout ; wire \ula_|video_|Add0~3 ; wire \ula_|video_|Add0~4_combout ; wire \ula_|video_|Add0~5 ; wire \ula_|video_|Add0~6_combout ; -wire \ula_|video_|vga_hc[3]~feeder_combout ; wire \ula_|video_|Add0~7 ; wire \ula_|video_|Add0~8_combout ; -wire \ula_|video_|Equal0~0_combout ; -wire \ula_|video_|Equal0~1_combout ; -wire \ula_|video_|Equal1~0_combout ; wire \ula_|video_|Add0~9 ; wire \ula_|video_|Add0~10_combout ; wire \ula_|video_|vga_hc~0_combout ; @@ -965,10 +246,24 @@ wire \ula_|video_|Add0~11 ; wire \ula_|video_|Add0~12_combout ; wire \ula_|video_|Add0~13 ; wire \ula_|video_|Add0~14_combout ; +wire \ula_|video_|Add0~15 ; +wire \ula_|video_|Add0~16_combout ; +wire \ula_|video_|vga_hc~2_combout ; +wire \ula_|video_|Add0~17 ; +wire \ula_|video_|Add0~18_combout ; +wire \ula_|video_|vga_hc~1_combout ; +wire \ula_|video_|Equal0~0_combout ; +wire \ula_|video_|Equal0~1_combout ; +wire \ula_|video_|Equal1~0_combout ; wire \ula_|video_|Add1~0_combout ; +wire \ula_|video_|vga_vc[0]~0_combout ; +wire \ula_|video_|Add1~1 ; +wire \ula_|video_|Add1~2_combout ; +wire \ula_|video_|vga_vc[1]~1_combout ; wire \ula_|video_|Add1~3 ; wire \ula_|video_|Add1~4_combout ; wire \ula_|video_|vga_vc[2]~2_combout ; +wire \ula_|video_|vga_vc[2]~feeder_combout ; wire \ula_|video_|Add1~5 ; wire \ula_|video_|Add1~6_combout ; wire \ula_|video_|vga_vc[3]~3_combout ; @@ -976,8 +271,6 @@ wire \ula_|video_|Add1~7 ; wire \ula_|video_|Add1~8_combout ; wire \ula_|video_|vga_vc[4]~5_combout ; wire \ula_|video_|Add1~9 ; -wire \ula_|video_|Add1~10_combout ; -wire \ula_|video_|vga_vc[5]~8_combout ; wire \ula_|video_|Add1~11 ; wire \ula_|video_|Add1~12_combout ; wire \ula_|video_|vga_vc[6]~4_combout ; @@ -990,359 +283,1298 @@ wire \ula_|video_|vga_vc[8]~7_combout ; wire \ula_|video_|Add1~17 ; wire \ula_|video_|Add1~18_combout ; wire \ula_|video_|vga_vc[9]~9_combout ; -wire \ula_|video_|Equal2~0_combout ; wire \ula_|video_|Equal3~0_combout ; +wire \ula_|video_|Equal2~0_combout ; wire \ula_|video_|Equal3~1_combout ; -wire \ula_|video_|vga_vc[0]~0_combout ; -wire \ula_|video_|Add1~1 ; -wire \ula_|video_|Add1~2_combout ; -wire \ula_|video_|vga_vc[1]~1_combout ; -wire \SW[1]~input_o ; -wire \z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout ; -wire \z80_|pla_decode_|Equal79~0_combout ; -wire \z80_|interrupts_|DFFE_instIFF2~0_combout ; -wire \z80_|interrupts_|SYNTHESIZED_WIRE_12~combout ; -wire \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl_outclk ; -wire \z80_|interrupts_|DFFE_instIFF2~q ; -wire \z80_|interrupts_|iff1~0_combout ; -wire \z80_|interrupts_|iff1~1_combout ; -wire \z80_|interrupts_|SYNTHESIZED_WIRE_15~combout ; -wire \z80_|interrupts_|iff1~q ; +wire \ula_|video_|Add1~10_combout ; +wire \ula_|video_|vga_vc[5]~8_combout ; wire \ula_|video_|Equal2~1_combout ; wire \ula_|video_|Equal2~2_combout ; +wire \SW[1]~input_o ; +wire \z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout ; wire \z80_|interrupts_|SYNTHESIZED_WIRE_13~combout ; wire \z80_|interrupts_|int_armed~q ; +wire \z80_|interrupts_|DFFE_inst44~feeder_combout ; wire \z80_|interrupts_|DFFE_inst44~q ; -wire \z80_|execute_|pc_inc_hold~38_combout ; -wire \z80_|execute_|ctl_inc_cy~91_combout ; -wire \z80_|execute_|pc_inc_hold~45_combout ; -wire \z80_|execute_|pc_inc_hold~44_combout ; -wire \z80_|execute_|pc_inc_hold~46_combout ; -wire \z80_|execute_|pc_inc_hold~37_combout ; -wire \z80_|execute_|pc_inc_hold~50_combout ; -wire \z80_|execute_|pc_inc_hold~33_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ; -wire \z80_|execute_|pc_inc_hold~31_combout ; -wire \z80_|execute_|pc_inc_hold~32_combout ; -wire \z80_|execute_|pc_inc_hold~34_combout ; -wire \z80_|execute_|pc_inc_hold~51_combout ; -wire \z80_|execute_|pc_inc_hold~30_combout ; -wire \z80_|execute_|pc_inc_hold~52_combout ; -wire \z80_|execute_|pc_inc_hold~35_combout ; -wire \z80_|execute_|pc_inc_hold~36_combout ; -wire \z80_|execute_|ctl_inc_cy~44_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ; -wire \z80_|execute_|ctl_inc_cy~45_combout ; -wire \z80_|execute_|pc_inc_hold~43_combout ; -wire \z80_|execute_|ctl_inc_cy~71_combout ; -wire \z80_|execute_|ctl_inc_cy~73_combout ; -wire \z80_|execute_|ctl_inc_cy~46_combout ; -wire \z80_|execute_|pc_inc_hold~53_combout ; -wire \z80_|execute_|pc_inc_hold~39_combout ; -wire \z80_|execute_|pc_inc_hold~47_combout ; -wire \z80_|execute_|ctl_inc_cy~74_combout ; +wire \z80_|decode_state_|in_halt~0_combout ; +wire \z80_|decode_state_|in_halt~1_combout ; +wire \z80_|decode_state_|in_halt~q ; +wire \z80_|pla_decode_|Equal50~0_combout ; +wire \z80_|execute_|ixy_d~17_combout ; +wire \z80_|pla_decode_|Equal44~0_combout ; +wire \z80_|execute_|ixy_d~16_combout ; +wire \z80_|pla_decode_|Equal3~1_combout ; +wire \z80_|execute_|ixy_d~10_combout ; +wire \z80_|execute_|ixy_d~13_combout ; +wire \z80_|execute_|ixy_d~14_combout ; +wire \z80_|pla_decode_|Equal49~0_combout ; +wire \z80_|execute_|ixy_d~15_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ; +wire \z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout ; +wire \z80_|decode_state_|DFFE_inst4~q ; +wire \z80_|execute_|ctl_ir_we~5_combout ; +wire \z80_|execute_|ctl_ir_we~13_combout ; +wire \z80_|pla_decode_|Equal8~0_combout ; +wire \z80_|execute_|ctl_mRead~6_combout ; +wire \z80_|pla_decode_|Equal9~0_combout ; +wire \z80_|pla_decode_|Equal9~1_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ; +wire \z80_|pla_decode_|Equal13~1_combout ; +wire \z80_|pla_decode_|Equal69~0_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ; +wire \z80_|execute_|ctl_alu_op_low~27_combout ; +wire \z80_|execute_|ctl_reg_out_lo~2_combout ; +wire \z80_|execute_|rsel3~combout ; +wire \z80_|execute_|ctl_ir_we~12_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ; +wire \z80_|pla_decode_|Equal56~0_combout ; +wire \z80_|execute_|ctl_alu_op_low~24_combout ; +wire \z80_|execute_|ctl_alu_op_low~25_combout ; +wire \z80_|execute_|nextM~2_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~16_combout ; +wire \z80_|execute_|ctl_reg_out_lo~3_combout ; +wire \z80_|pla_decode_|Equal40~0_combout ; +wire \z80_|pla_decode_|Equal40~1_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ; +wire \z80_|pla_decode_|Equal3~0_combout ; +wire \z80_|pla_decode_|Equal39~0_combout ; +wire \z80_|execute_|ctl_reg_out_lo~4_combout ; +wire \z80_|execute_|ctl_alu_oe~0_combout ; +wire \z80_|execute_|comb~0_combout ; +wire \z80_|pla_decode_|Equal41~0_combout ; +wire \z80_|pla_decode_|Equal47~0_combout ; +wire \z80_|execute_|ctl_inc_cy~32_combout ; +wire \z80_|pla_decode_|Equal19~0_combout ; +wire \z80_|execute_|ctl_reg_out_lo~9_combout ; +wire \z80_|execute_|ctl_reg_out_lo~5_combout ; +wire \z80_|execute_|ctl_mWrite~4_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ; +wire \z80_|execute_|ctl_mRead~34_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ; +wire \z80_|execute_|ctl_mWrite~5_combout ; +wire \z80_|execute_|nextM~11_combout ; +wire \z80_|pla_decode_|Equal20~0_combout ; +wire \z80_|pla_decode_|Equal13~2_combout ; +wire \z80_|execute_|ctl_mRead~24_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~27_combout ; +wire \z80_|pla_decode_|Equal48~0_combout ; +wire \z80_|pla_decode_|Equal10~0_combout ; +wire \z80_|pla_decode_|Equal11~0_combout ; +wire \z80_|pla_decode_|Equal63~0_combout ; +wire \z80_|execute_|ctl_flags_hf2_we~combout ; +wire \z80_|execute_|ctl_alu_shift_oe~41_combout ; +wire \z80_|pla_decode_|Equal68~3_combout ; +wire \z80_|execute_|ctl_flags_bus~7_combout ; +wire \z80_|execute_|ctl_flags_bus~8_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~9_combout ; +wire \z80_|execute_|ctl_ir_we~6_combout ; +wire \z80_|execute_|ctl_ir_we~8_combout ; +wire \z80_|execute_|ctl_ir_we~14_combout ; +wire \z80_|execute_|ctl_flags_bus~4_combout ; +wire \z80_|execute_|ctl_flags_bus~5_combout ; +wire \z80_|execute_|ctl_mRead~4_combout ; +wire \z80_|execute_|ctl_flags_bus~6_combout ; +wire \z80_|execute_|ctl_flags_bus~9_combout ; +wire \z80_|execute_|ctl_iorw~11_combout ; +wire \z80_|execute_|ctl_mWrite~17_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~18_combout ; +wire \z80_|pla_decode_|Equal37~0_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~19_combout ; +wire \z80_|pla_decode_|Equal35~0_combout ; +wire \z80_|pla_decode_|Equal21~1_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~17_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~20_combout ; +wire \z80_|execute_|ctl_ir_we~9_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~11_combout ; +wire \z80_|execute_|ctl_ir_we~15_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~7_combout ; +wire \z80_|execute_|ctl_ir_we~7_combout ; +wire \z80_|pla_decode_|Equal46~0_combout ; +wire \z80_|execute_|ctl_ir_we~11_combout ; +wire \z80_|execute_|ctl_bus_db_oe~3_combout ; +wire \z80_|pla_decode_|Equal52~1_combout ; +wire \z80_|execute_|ctl_flags_xy_we~21_combout ; +wire \z80_|execute_|ctl_flags_xy_we~13_combout ; +wire \z80_|execute_|ctl_state_alu~6_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~14_combout ; +wire \z80_|execute_|ctl_flags_xy_we~14_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~24_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ; +wire \z80_|execute_|ctl_reg_gp_sel~7_combout ; +wire \z80_|execute_|rsel0~combout ; +wire \z80_|execute_|ctl_state_alu~3_combout ; +wire \z80_|execute_|ctl_reg_use_sp~0_combout ; +wire \z80_|execute_|ctl_state_alu~2_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ; +wire \z80_|execute_|ctl_reg_out_lo~6_combout ; +wire \z80_|execute_|ctl_state_alu~5_combout ; +wire \z80_|execute_|ctl_sw_2u~1_combout ; +wire \z80_|execute_|ctl_alu_oe~1_combout ; +wire \z80_|execute_|ctl_mWrite~7_combout ; +wire \z80_|execute_|ctl_sw_2u~4_combout ; +wire \z80_|execute_|setM1~57_combout ; +wire \z80_|execute_|ctl_sw_2u~5_combout ; +wire \z80_|execute_|ctl_reg_out_lo~7_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~0_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~41_combout ; +wire \z80_|execute_|ctl_inc_cy~86_combout ; +wire \z80_|execute_|ctl_inc_cy~88_combout ; +wire \z80_|execute_|ctl_inc_cy~36_combout ; +wire \z80_|execute_|ctl_inc_cy~87_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~26_combout ; +wire \z80_|execute_|ctl_mWrite~9_combout ; +wire \z80_|execute_|ctl_reg_sys_we~1_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~42_combout ; +wire \z80_|pla_decode_|Equal40~2_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~14_combout ; +wire \z80_|pla_decode_|Equal55~0_combout ; +wire \z80_|execute_|ctl_mRead~11_combout ; +wire \z80_|pla_decode_|Equal6~1_combout ; +wire \z80_|execute_|setM1~36_combout ; +wire \z80_|execute_|comb~1_combout ; +wire \z80_|execute_|ctl_mRead~13_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~11_combout ; +wire \z80_|pla_decode_|Equal24~0_combout ; +wire \z80_|execute_|pc_inc_hold~26_combout ; +wire \z80_|execute_|setM1~37_combout ; +wire \z80_|execute_|pc_inc_hold~6_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo~38_combout ; +wire \z80_|execute_|fMRead~7_combout ; +wire \z80_|execute_|ctl_mRead~12_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~31_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ; +wire \z80_|nM1_int~2_combout ; +wire \z80_|execute_|ctl_sw_4u~0_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ; +wire \z80_|execute_|fMRead~6_combout ; +wire \z80_|execute_|ctl_inc_dec~12_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ; +wire \z80_|pla_decode_|Equal25~0_combout ; +wire \z80_|pla_decode_|Equal12~1_combout ; +wire \z80_|execute_|ctl_inc_cy~38_combout ; +wire \z80_|execute_|ctl_inc_cy~82_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~16_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~32_combout ; +wire \z80_|execute_|ctl_inc_cy~77_combout ; +wire \z80_|pla_decode_|Equal29~0_combout ; wire \z80_|execute_|ctl_inc_cy~78_combout ; wire \z80_|execute_|ctl_inc_cy~79_combout ; -wire \z80_|execute_|ctl_inc_cy~80_combout ; -wire \z80_|execute_|ctl_inc_cy~81_combout ; -wire \z80_|execute_|ctl_inc_cy~82_combout ; -wire \z80_|execute_|ctl_inc_cy~83_combout ; -wire \z80_|execute_|ctl_inc_cy~84_combout ; -wire \z80_|execute_|pc_inc_hold~42_combout ; -wire \z80_|execute_|ctl_inc_cy~90_combout ; -wire \z80_|execute_|pc_inc_hold~41_combout ; -wire \z80_|execute_|ctl_inc_cy~66_combout ; -wire \z80_|execute_|ctl_inc_cy~67_combout ; -wire \z80_|execute_|ctl_inc_cy~68_combout ; -wire \z80_|execute_|ctl_inc_cy~64_combout ; -wire \z80_|execute_|ctl_inc_cy~63_combout ; -wire \z80_|execute_|ctl_inc_cy~65_combout ; -wire \z80_|execute_|ctl_inc_cy~69_combout ; +wire \z80_|execute_|ctl_mRead~14_combout ; wire \z80_|execute_|ctl_inc_cy~49_combout ; -wire \z80_|execute_|ctl_inc_cy~50_combout ; -wire \z80_|execute_|ctl_inc_cy~51_combout ; -wire \z80_|execute_|ctl_inc_cy~52_combout ; -wire \z80_|execute_|ctl_inc_cy~36_combout ; -wire \z80_|execute_|ctl_inc_cy~37_combout ; -wire \z80_|execute_|ctl_inc_cy~54_combout ; -wire \z80_|execute_|ctl_inc_cy~41_combout ; -wire \z80_|execute_|ctl_inc_cy~58_combout ; -wire \z80_|execute_|ctl_inc_cy~55_combout ; -wire \z80_|execute_|ctl_inc_cy~56_combout ; -wire \z80_|execute_|ctl_inc_cy~89_combout ; -wire \z80_|execute_|ctl_inc_cy~57_combout ; -wire \z80_|execute_|ctl_inc_cy~59_combout ; -wire \z80_|execute_|ctl_inc_cy~60_combout ; -wire \z80_|execute_|ctl_inc_cy~47_combout ; -wire \z80_|execute_|ctl_inc_cy~88_combout ; -wire \z80_|execute_|ctl_inc_cy~48_combout ; -wire \z80_|execute_|pc_inc_hold~40_combout ; -wire \z80_|execute_|ctl_inc_cy~61_combout ; -wire \z80_|execute_|ctl_inc_cy~62_combout ; -wire \z80_|execute_|ctl_inc_cy~70_combout ; -wire \z80_|execute_|ctl_inc_cy~85_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ; -wire \z80_|reg_file_|db_lo_as[0]~3_combout ; -wire \z80_|address_latch_|Q[0]~feeder_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ; -wire \z80_|reg_file_|db_lo_as[1]~4_combout ; -wire \z80_|reg_file_|db_lo_as[1]~5_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ; -wire \z80_|reg_file_|db_lo_as[1]~6_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ; -wire \z80_|reg_file_|db_lo_as[2]~9_combout ; -wire \z80_|address_latch_|Q[2]~feeder_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ; -wire \z80_|execute_|ctl_inc_cy~86_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ; -wire \z80_|execute_|ctl_inc_dec~11_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~45_combout ; -wire \z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~48_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~49_combout ; -wire \z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~5_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~40_combout ; +wire \z80_|execute_|ctl_mRead~5_combout ; wire \z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~40_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~41_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[3]~18_combout ; -wire \z80_|execute_|ctl_reg_in_hi~11_combout ; -wire \z80_|execute_|ctl_reg_in_hi~12_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~44_combout ; -wire \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~43_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ; -wire \z80_|reg_control_|reg_sys_we_hi~0_combout ; -wire \z80_|reg_control_|reg_sys_we_hi~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~45_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~42_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~46_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~47_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~17_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~18_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~19_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~16_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~20_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~8_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[1]~15_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~13_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~12_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~10_combout ; -wire \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~11_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~14_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~9_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~15_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~21_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ; -wire \z80_|reg_control_|reg_sw_4d_hi~0_combout ; -wire \z80_|reg_file_|db_hi_as[1]~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ; -wire \z80_|reg_file_|db_hi_as[1]~1_combout ; -wire \z80_|reg_file_|db_hi_as[0]~2_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~23_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~22_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~24_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~26_combout ; -wire \z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~25_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~27_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~28_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[0]~16_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~29_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~30_combout ; -wire \z80_|reg_file_|db_hi_as[0]~4_combout ; -wire \z80_|reg_file_|db_hi_as[0]~5_combout ; -wire \z80_|reg_file_|db_hi_as[0]~6_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ; -wire \z80_|reg_file_|db_hi_as[1]~3_combout ; -wire \z80_|address_latch_|Q[9]~feeder_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~32_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~35_combout ; -wire \z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~34_combout ; -wire \z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~33_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~36_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~37_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~31_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[2]~17_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~38_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~39_combout ; -wire \z80_|reg_file_|db_hi_as[2]~7_combout ; -wire \z80_|reg_file_|db_hi_as[2]~8_combout ; -wire \z80_|reg_file_|db_hi_as[2]~9_combout ; -wire \z80_|address_latch_|Q[10]~feeder_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ; -wire \z80_|reg_file_|db_hi_as[3]~10_combout ; -wire \z80_|reg_file_|db_hi_as[3]~11_combout ; -wire \z80_|reg_file_|db_hi_as[3]~12_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~48_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_low~combout ; -wire \z80_|alu_|alu_op1[3]~3_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~6_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~10_combout ; -wire \z80_|execute_|ctl_alu_core_R~0_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~5_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~7_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~8_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|ena~combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~6_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~20_combout ; -wire \z80_|execute_|ctl_state_alu~12_combout ; -wire \z80_|execute_|ctl_alu_core_hf~18_combout ; -wire \z80_|pla_decode_|Equal61~2_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~16_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~17_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~21_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~15_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~12_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~22_combout ; -wire \z80_|execute_|ctl_alu_core_hf~20_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~36_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~35_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~46_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~33_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~47_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ; +wire \z80_|execute_|ctl_bus_inc_oe~45_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~34_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ; +wire \z80_|execute_|ctl_mWrite~6_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~50_combout ; +wire \z80_|pla_decode_|Equal4~0_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~48_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~49_combout ; +wire \z80_|execute_|ctl_mRead~7_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~29_combout ; +wire \z80_|execute_|ctl_alu_core_S~11_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~27_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~44_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~28_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~30_combout ; +wire \z80_|execute_|ctl_mRead~3_combout ; +wire \z80_|execute_|fMRead~3_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~37_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~38_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~39_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~43_combout ; +wire \z80_|execute_|ctl_alu_oe~3_combout ; +wire \z80_|execute_|fMWrite~1_combout ; +wire \z80_|execute_|ctl_flags_bus~1_combout ; +wire \z80_|execute_|fMRead~5_combout ; +wire \z80_|execute_|ctl_mRead~17_combout ; +wire \z80_|execute_|ctl_iorw~10_combout ; +wire \z80_|execute_|setM1~47_combout ; +wire \z80_|execute_|ctl_mWrite~8_combout ; +wire \z80_|execute_|ctl_al_we~13_combout ; +wire \z80_|execute_|setM1~48_combout ; +wire \z80_|execute_|ctl_sw_4d~0_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ; +wire \z80_|execute_|ctl_mRead~9_combout ; +wire \z80_|execute_|ctl_flags_sz_we~3_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ; +wire \z80_|execute_|ctl_flags_alu~9_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~2_combout ; +wire \z80_|execute_|ctl_flags_alu~10_combout ; +wire \z80_|execute_|ctl_flags_xy_we~10_combout ; +wire \z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ; +wire \z80_|execute_|ctl_flags_xy_we~11_combout ; +wire \z80_|execute_|ctl_flags_alu~11_combout ; +wire \z80_|execute_|ctl_reg_use_sp~1_combout ; +wire \z80_|execute_|ctl_state_alu~4_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~9_combout ; +wire \z80_|execute_|ctl_sw_2d~4_combout ; +wire \z80_|execute_|ctl_flags_sz_we~0_combout ; wire \z80_|execute_|ctl_flags_sz_we~4_combout ; -wire \z80_|pla_decode_|Equal71~2_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ; +wire \z80_|execute_|ctl_alu_op_low~47_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~3_combout ; +wire \z80_|execute_|ctl_flags_alu~12_combout ; +wire \z80_|execute_|ctl_alu_op_low~23_combout ; +wire \z80_|execute_|ctl_flags_xy_we~19_combout ; +wire \z80_|execute_|ctl_flags_alu~13_combout ; +wire \z80_|execute_|ctl_reg_out_hi~4_combout ; +wire \z80_|execute_|ctl_sw_4u~1_combout ; +wire \z80_|execute_|ctl_alu_op_low~29_combout ; +wire \z80_|execute_|ctl_flags_alu~14_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ; +wire \z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ; +wire \z80_|execute_|ctl_flags_use_cf2~13_combout ; +wire \z80_|execute_|ctl_flags_cf_we~7_combout ; +wire \z80_|execute_|ctl_pf_sel[0]~2_combout ; +wire \z80_|execute_|ctl_flags_hf_we~5_combout ; +wire \z80_|execute_|ctl_flags_pf_we~10_combout ; +wire \z80_|pla_decode_|Equal68~2_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~13_combout ; +wire \z80_|execute_|ctl_flags_pf_we~2_combout ; +wire \z80_|execute_|ctl_alu_oe~4_combout ; +wire \z80_|execute_|ctl_flags_xy_we~8_combout ; +wire \z80_|execute_|ctl_flags_xy_we~20_combout ; +wire \z80_|execute_|ctl_flags_xy_we~9_combout ; +wire \z80_|execute_|ctl_flags_sz_we~1_combout ; +wire \z80_|execute_|ctl_bus_db_oe~1_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~10_combout ; +wire \z80_|execute_|ctl_flags_sz_we~2_combout ; +wire \z80_|execute_|ctl_flags_alu~17_combout ; +wire \z80_|execute_|ctl_flags_alu~18_combout ; +wire \z80_|execute_|ctl_flags_alu~6_combout ; +wire \z80_|execute_|ctl_flags_alu~19_combout ; +wire \z80_|pla_decode_|Equal1~5_combout ; +wire \z80_|execute_|ctl_alu_core_R~0_combout ; +wire \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ; +wire \z80_|execute_|ctl_alu_core_R~1_combout ; +wire \z80_|execute_|ctl_flags_alu~7_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~5_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~8_combout ; +wire \z80_|execute_|ctl_flags_alu~8_combout ; +wire \z80_|execute_|ctl_flags_alu~15_combout ; +wire \z80_|execute_|ctl_state_alu~7_combout ; +wire \z80_|execute_|ctl_state_alu~12_combout ; +wire \z80_|execute_|ctl_state_alu~9_combout ; +wire \z80_|execute_|ctl_state_alu~10_combout ; +wire \z80_|execute_|ctl_state_alu~8_combout ; +wire \z80_|pla_decode_|Equal64~0_combout ; +wire \z80_|execute_|ctl_pf_sel[0]~3_combout ; +wire \z80_|pla_decode_|Equal62~2_combout ; +wire \z80_|execute_|ctl_flags_pf_we~4_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~46_combout ; +wire \z80_|execute_|ctl_flags_pf_we~6_combout ; +wire \z80_|execute_|ctl_flags_pf_we~7_combout ; +wire \z80_|execute_|ctl_state_alu~11_combout ; +wire \z80_|pla_decode_|Equal62~3_combout ; +wire \z80_|execute_|ctl_flags_pf_we~5_combout ; +wire \z80_|execute_|ctl_flags_pf_we~3_combout ; +wire \z80_|execute_|ctl_flags_pf_we~8_combout ; +wire \z80_|execute_|ctl_flags_pf_we~9_combout ; +wire \z80_|execute_|ctl_alu_core_S~6_combout ; +wire \z80_|execute_|ctl_alu_core_S~7_combout ; +wire \z80_|execute_|ctl_alu_res_oe~1_combout ; +wire \z80_|execute_|ctl_alu_res_oe~0_combout ; +wire \z80_|execute_|ctl_alu_core_S~4_combout ; +wire \z80_|execute_|ctl_alu_core_S~5_combout ; +wire \z80_|execute_|ctl_alu_res_oe~2_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ; +wire \z80_|reg_control_|reg_sys_we_lo~6_combout ; +wire \z80_|execute_|ctl_flags_xy_we~12_combout ; +wire \z80_|execute_|ctl_flags_cf_we~2_combout ; +wire \z80_|execute_|ctl_alu_res_oe~3_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_high~combout ; +wire \z80_|execute_|ctl_alu_op1_sel_zero~4_combout ; +wire \z80_|execute_|ctl_alu_core_hf~12_combout ; +wire \z80_|pla_decode_|Equal61~2_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~4_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~13_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~14_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~18_combout ; +wire \z80_|execute_|ctl_flags_bus~10_combout ; +wire \z80_|execute_|ctl_flags_bus~2_combout ; +wire \z80_|execute_|ctl_flags_bus~0_combout ; +wire \z80_|execute_|ctl_flags_bus~3_combout ; +wire \z80_|execute_|fMRead~26_combout ; +wire \z80_|execute_|ctl_flags_bus~combout ; +wire \z80_|execute_|ctl_reg_in_lo~9_combout ; +wire \z80_|execute_|ctl_alu_op1_oe~0_combout ; +wire \z80_|execute_|ctl_alu_op1_oe~1_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~6_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~12_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~8_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~9_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~combout ; +wire \z80_|execute_|ctl_alu_op2_oe~0_combout ; +wire \z80_|alu_|db_high[3]~0_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla83M1T3_2~combout ; +wire \z80_|execute_|ctl_alu_shift_oe~15_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~38_combout ; +wire \z80_|execute_|ctl_alu_op_low~28_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~6_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~37_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~39_combout ; +wire \z80_|execute_|ctl_flags_cf2_sel_daa~combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~7_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~8_combout ; +wire \z80_|execute_|ctl_alu_op_low~30_combout ; wire \z80_|execute_|ctl_alu_op_low~31_combout ; +wire \z80_|execute_|ctl_mRead~25_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~40_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~42_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~4_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~47_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~34_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~35_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~36_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~28_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~44_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~29_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~16_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~27_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~10_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~31_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~30_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~32_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~33_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~21_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~45_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~22_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~23_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~24_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~25_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~26_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~43_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_low~combout ; +wire \z80_|execute_|ctl_alu_op1_sel_zero~5_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_zero~combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~13_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~17_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~14_combout ; +wire \z80_|execute_|ctl_alu_core_R~3_combout ; +wire \z80_|execute_|ctl_alu_core_R~4_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~9_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~10_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~11_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~12_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~15_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~6_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|ena~combout ; +wire \z80_|alu_|db_low[3]~15_combout ; +wire \z80_|alu_|db_low[3]~16_combout ; +wire \z80_|execute_|ctl_alu_op_low~33_combout ; +wire \z80_|execute_|ctl_alu_op_low~34_combout ; +wire \z80_|execute_|ctl_alu_op_low~48_combout ; +wire \z80_|execute_|ctl_alu_op_low~35_combout ; +wire \z80_|execute_|ctl_alu_op_low~36_combout ; +wire \z80_|execute_|ctl_alu_op_low~37_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ; +wire \z80_|execute_|ctl_alu_op_low~38_combout ; +wire \z80_|execute_|ctl_alu_op_low~39_combout ; +wire \z80_|execute_|ctl_alu_op_low~40_combout ; +wire \z80_|execute_|ctl_alu_op_low~41_combout ; +wire \z80_|execute_|ctl_alu_op_low~combout ; +wire \z80_|execute_|ctl_alu_oe~5_combout ; +wire \z80_|execute_|ctl_alu_oe~6_combout ; +wire \z80_|execute_|ctl_alu_oe~9_combout ; +wire \z80_|execute_|ctl_alu_core_S~12_combout ; +wire \z80_|execute_|ctl_alu_oe~10_combout ; +wire \z80_|execute_|ctl_alu_oe~2_combout ; +wire \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~15_combout ; +wire \z80_|execute_|ctl_reg_in_hi~8_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~7_combout ; +wire \z80_|execute_|ctl_alu_oe~7_combout ; +wire \z80_|execute_|ctl_mWrite~11_combout ; +wire \z80_|execute_|ctl_bus_db_we~5_combout ; +wire \z80_|execute_|ctl_alu_oe~8_combout ; +wire \z80_|execute_|ctl_flags_alu~16_combout ; +wire \z80_|execute_|ctl_alu_oe~11_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ; +wire \z80_|execute_|ctl_reg_out_hi~8_combout ; +wire \z80_|execute_|ctl_reg_out_hi~5_combout ; +wire \z80_|execute_|ctl_sw_2u~2_combout ; +wire \z80_|execute_|ctl_sw_2u~0_combout ; +wire \z80_|execute_|ctl_sw_2u~3_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ; +wire \z80_|execute_|ctl_inc_cy~33_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~37_combout ; +wire \z80_|execute_|ctl_sw_2u~6_combout ; +wire \z80_|execute_|ctl_reg_out_hi~6_combout ; +wire \z80_|execute_|ctl_reg_out_hi~7_combout ; +wire \z80_|execute_|ctl_mRead~2_combout ; +wire \z80_|execute_|ctl_sw_2d~6_combout ; +wire \z80_|execute_|ctl_sw_2d~7_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ; +wire \z80_|execute_|ctl_sw_2d~8_combout ; +wire \z80_|execute_|ctl_bus_db_oe~7_combout ; +wire \z80_|execute_|ctl_sw_2d~5_combout ; +wire \z80_|execute_|ctl_mRead~19_combout ; +wire \z80_|execute_|ctl_mRead~18_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~2_combout ; +wire \z80_|pla_decode_|Equal24~1_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~3_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~4_combout ; +wire \z80_|execute_|ctl_mRead~20_combout ; +wire \z80_|execute_|ctl_reg_in_hi~5_combout ; +wire \z80_|execute_|ctl_mRead~22_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ; +wire \z80_|execute_|ctl_reg_in_hi~6_combout ; +wire \z80_|execute_|ctl_reg_in_hi~2_combout ; +wire \z80_|execute_|setM1~30_combout ; +wire \z80_|execute_|ctl_mRead~23_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~6_combout ; +wire \z80_|execute_|ctl_reg_in_hi~3_combout ; +wire \z80_|execute_|ctl_mWrite~10_combout ; +wire \z80_|execute_|fMRead~18_combout ; +wire \z80_|reg_control_|reg_sel_pc~0_combout ; +wire \z80_|reg_control_|reg_sel_pc~1_combout ; +wire \z80_|reg_control_|reg_sel_pc~2_combout ; +wire \z80_|execute_|fMRead~19_combout ; +wire \z80_|execute_|fMRead~20_combout ; +wire \z80_|execute_|fMRead~21_combout ; +wire \z80_|execute_|ctl_sw_2d~9_combout ; +wire \z80_|execute_|ctl_sw_2d~14_combout ; +wire \z80_|execute_|ctl_sw_1d~8_combout ; +wire \z80_|execute_|ctl_sw_2d~10_combout ; +wire \z80_|execute_|ctl_sw_2d~11_combout ; +wire \z80_|execute_|ctl_sw_2d~12_combout ; +wire \z80_|execute_|ctl_sw_2d~13_combout ; +wire \z80_|alu_|db[7]~9_combout ; +wire \z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ; +wire \z80_|execute_|ctl_alu_op_low~32_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~2_combout ; +wire \z80_|execute_|ctl_flags_xy_we~22_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~3_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ; wire \z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ; +wire \z80_|execute_|ctl_alu_core_hf~15_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ; -wire \z80_|pla_decode_|Equal72~2_combout ; -wire \z80_|pla_decode_|Equal73~2_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~7_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~17_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ; +wire \z80_|execute_|ctl_flags_nf_we~3_combout ; wire \z80_|execute_|ctl_flags_nf_we~0_combout ; +wire \z80_|pla_decode_|Equal73~2_combout ; +wire \z80_|pla_decode_|Equal72~2_combout ; wire \z80_|execute_|ctl_flags_nf_we~1_combout ; wire \z80_|execute_|ctl_flags_nf_we~2_combout ; -wire \z80_|execute_|ctl_flags_nf_we~3_combout ; wire \z80_|execute_|ctl_flags_sz_we~5_combout ; wire \z80_|execute_|ctl_flags_sz_we~6_combout ; wire \z80_|execute_|ctl_flags_nf_we~4_combout ; -wire \z80_|execute_|setM1~15_combout ; -wire \z80_|execute_|setM1~16_combout ; -wire \z80_|execute_|ctl_flags_xy_we~6_combout ; -wire \z80_|execute_|ctl_flags_xy_we~7_combout ; -wire \z80_|execute_|ctl_flags_sz_we~2_combout ; -wire \z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ; -wire \z80_|execute_|ctl_alu_core_R~1_combout ; -wire \z80_|execute_|ctl_flags_alu~7_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~8_combout ; -wire \z80_|execute_|ctl_flags_alu~8_combout ; -wire \z80_|execute_|ctl_flags_xy_we~16_combout ; -wire \z80_|execute_|ctl_flags_alu~12_combout ; -wire \z80_|execute_|ctl_flags_alu~13_combout ; -wire \z80_|execute_|ctl_flags_alu~14_combout ; -wire \z80_|execute_|ctl_flags_alu~15_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~19_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~7_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~9_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~10_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_nf~q ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~7_combout ; -wire \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ; +wire \z80_|execute_|ctl_flags_hf_cpl~14_combout ; +wire \z80_|execute_|ctl_flags_hf_cpl~10_combout ; +wire \z80_|pla_decode_|Equal45~0_combout ; +wire \z80_|execute_|ctl_flags_hf_cpl~11_combout ; +wire \z80_|execute_|ctl_flags_hf_cpl~12_combout ; +wire \z80_|execute_|ctl_flags_hf_cpl~13_combout ; +wire \z80_|execute_|ctl_alu_core_S~8_combout ; +wire \z80_|execute_|ctl_alu_core_S~9_combout ; +wire \z80_|execute_|ctl_alu_core_S~10_combout ; +wire \z80_|execute_|ctl_alu_core_S~combout ; +wire \z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ; +wire \z80_|alu_|alu_op1[3]~2_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ; +wire \z80_|execute_|ctl_reg_sys_we_lo~2_combout ; +wire \z80_|execute_|ctl_reg_sys_we_lo~3_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~14_combout ; +wire \z80_|reg_control_|reg_sys_we_hi~0_combout ; +wire \z80_|pla_decode_|Equal33~3_combout ; +wire \z80_|execute_|ctl_reg_sys_we~0_combout ; +wire \z80_|execute_|ctl_reg_sys_we~2_combout ; +wire \z80_|execute_|ctl_reg_sys_we~3_combout ; +wire \z80_|execute_|ctl_reg_in_hi~4_combout ; +wire \z80_|reg_control_|reg_sys_we_hi~combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo~17_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~11_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~12_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~13_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ; +wire \z80_|execute_|ctl_reg_sel_wz~6_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~7_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~9_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~8_combout ; +wire \z80_|execute_|ctl_al_we~5_combout ; +wire \z80_|execute_|ctl_al_we~4_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~41_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~10_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo~21_combout ; +wire \z80_|execute_|ctl_inc_dec~3_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ; +wire \z80_|execute_|fMRead~2_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~20_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~29_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~13_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ; +wire \z80_|execute_|ctl_reg_sel_ir~0_combout ; +wire \z80_|execute_|ctl_reg_sel_ir~1_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ; +wire \z80_|execute_|ctl_reg_sys_we_lo~4_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~combout ; +wire \z80_|reg_control_|reg_sw_4d_hi~0_combout ; +wire \z80_|reg_file_|db_hi_as[3]~10_combout ; +wire \z80_|reg_file_|db_hi_as[3]~11_combout ; +wire \z80_|execute_|ctl_apin_mux~1_combout ; +wire \z80_|execute_|ctl_inc_cy~37_combout ; +wire \z80_|execute_|ctl_inc_dec~2_combout ; +wire \z80_|execute_|ctl_inc_cy~40_combout ; +wire \z80_|execute_|ctl_inc_dec~4_combout ; +wire \z80_|execute_|ctl_inc_dec~5_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~4_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ; +wire \z80_|execute_|setM1~42_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~12_combout ; +wire \z80_|execute_|ctl_sw_1d~4_combout ; +wire \z80_|execute_|ctl_sw_4d~3_combout ; +wire \z80_|execute_|fMRead~9_combout ; +wire \z80_|execute_|fMRead~10_combout ; +wire \z80_|execute_|fMRead~8_combout ; +wire \z80_|execute_|ctl_sw_4d~2_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~11_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~12_combout ; +wire \z80_|execute_|ctl_sw_4d~4_combout ; +wire \z80_|execute_|ctl_sw_4d~5_combout ; +wire \z80_|execute_|ctl_al_we~14_combout ; +wire \z80_|execute_|ctl_al_we~10_combout ; +wire \z80_|execute_|ctl_al_we~6_combout ; +wire \z80_|execute_|ctl_al_we~7_combout ; +wire \z80_|execute_|ctl_al_we~8_combout ; +wire \z80_|execute_|ctl_al_we~9_combout ; +wire \z80_|execute_|ctl_al_we~11_combout ; +wire \z80_|execute_|ctl_al_we~12_combout ; +wire \z80_|execute_|fIOWrite~0_combout ; +wire \z80_|execute_|ctl_inc_dec~8_combout ; +wire \z80_|execute_|ctl_reg_gp_we~2_combout ; +wire \z80_|execute_|ctl_inc_dec~9_combout ; +wire \z80_|execute_|ctl_apin_mux~0_combout ; +wire \z80_|execute_|ctl_inc_dec~6_combout ; +wire \z80_|execute_|ctl_inc_dec~7_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~21_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[0]~40_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~39_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[0]~13_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[0]~31_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ; +wire \z80_|execute_|setM1~49_combout ; +wire \z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ; +wire \z80_|execute_|setM1~50_combout ; +wire \z80_|execute_|ctl_flags_oe~0_combout ; +wire \z80_|execute_|ctl_flags_oe~1_combout ; +wire \z80_|execute_|ctl_reg_in_hi~13_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~12_combout ; +wire \z80_|execute_|ctl_reg_in_hi~7_combout ; +wire \z80_|execute_|ctl_state_alu~13_combout ; +wire \z80_|execute_|ctl_reg_gp_we~6_combout ; +wire \z80_|execute_|ctl_reg_gp_we~5_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~17_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ; wire \z80_|execute_|ctl_alu_sel_op2_neg~10_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~8_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~9_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~11_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~14_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~18_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_high~combout ; +wire \z80_|execute_|ctl_sw_1d~9_combout ; +wire \z80_|execute_|ctl_reg_gp_we~9_combout ; +wire \z80_|execute_|ctl_reg_gp_we~4_combout ; +wire \z80_|execute_|ctl_reg_gp_we~7_combout ; +wire \z80_|execute_|ctl_reg_gp_we~3_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~32_combout ; +wire \z80_|execute_|ctl_sw_4u~2_combout ; +wire \z80_|execute_|ctl_sw_4u~3_combout ; +wire \z80_|execute_|ctl_reg_gp_we~8_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~14_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~24_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~46_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~22_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~23_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~26_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~34_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~25_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~21_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ; +wire \z80_|pla_decode_|Equal2~2_combout ; +wire \z80_|pla_decode_|Equal1~6_combout ; +wire \z80_|reg_control_|bank_exx~2_combout ; +wire \z80_|reg_control_|bank_exx~q ; +wire \z80_|reg_control_|bank_hl_de1~0_combout ; +wire \z80_|reg_control_|bank_hl_de1~q ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~28_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~29_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~30_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~13_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ; +wire \z80_|execute_|ctl_reg_use_sp~2_combout ; +wire \z80_|execute_|ctl_reg_use_sp~3_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~14_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~32_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~33_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~16_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~34_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~20_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~21_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~22_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~18_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~37_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~19_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~23_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~16_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~17_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~11_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~36_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~8_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~9_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~10_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~15_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~31_combout ; +wire \z80_|reg_control_|reg_sel_de2~5_combout ; +wire \z80_|reg_control_|reg_sel_de2~6_combout ; +wire \z80_|reg_control_|reg_sel_de~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ; +wire \z80_|reg_control_|bank_hl_de2~0_combout ; +wire \z80_|reg_control_|bank_hl_de2~q ; +wire \z80_|reg_control_|reg_sel_de2~4_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~33_combout ; +wire \z80_|reg_control_|reg_sel_hl~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ; +wire \z80_|reg_control_|reg_sel_hl2~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~34_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~36_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~15_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~18_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~37_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ; +wire \z80_|reg_control_|reg_sel_iy~2_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~38_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ; +wire \z80_|execute_|ctl_reg_in_hi~9_combout ; +wire \z80_|execute_|ctl_reg_in_hi~10_combout ; +wire \z80_|execute_|ctl_reg_in_lo~8_combout ; +wire \z80_|reg_file_|b2v_latch_sp_lo|latch[2]~feeder_combout ; +wire \z80_|execute_|ctl_reg_use_sp~4_combout ; +wire \z80_|execute_|ctl_reg_use_sp~5_combout ; +wire \z80_|execute_|ctl_reg_use_sp~6_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ; +wire \z80_|execute_|ctl_sw_1d~5_combout ; +wire \z80_|execute_|ctl_im_we~combout ; +wire \z80_|execute_|ctl_sw_1d~6_combout ; +wire \z80_|execute_|ctl_sw_1d~7_combout ; +wire \z80_|reg_file_|db_lo_ds[2]~2_combout ; +wire \z80_|alu_control_|db[2]~28_combout ; +wire \z80_|execute_|ctl_reg_in_hi~11_combout ; +wire \z80_|execute_|ctl_reg_in_hi~12_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~18_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ; +wire \z80_|pla_decode_|Equal21~2_combout ; +wire \z80_|reg_control_|bank_af~0_combout ; +wire \z80_|reg_control_|bank_af~q ; +wire \z80_|reg_control_|reg_sel_af~0_combout ; +wire \z80_|reg_control_|reg_sel_af2~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~17_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~19_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~16_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~20_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~34_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~36_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~35_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~33_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~37_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ; +wire \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~31_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[2]~12_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~32_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~38_combout ; +wire \z80_|execute_|ctl_inc_dec~11_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ; +wire \z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ; +wire \z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ; +wire \z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~4_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~5_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~16_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~6_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~7_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~10_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~8_combout ; +wire \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ; +wire \z80_|execute_|ctl_alu_op_low~42_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~9_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ; +wire \z80_|execute_|ctl_mWrite~18_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~2_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ; +wire \z80_|execute_|ctl_flags_cf2_we~4_combout ; +wire \z80_|execute_|ctl_flags_cf2_we~2_combout ; +wire \z80_|execute_|ctl_flags_cf2_we~3_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_32~combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~81_combout ; +wire \z80_|alu_|db_high[2]~8_combout ; +wire \z80_|alu_|db_high[2]~9_combout ; +wire \z80_|alu_|db_high[2]~11_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_lq~combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~5_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~6_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~7_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~8_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_zero~combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|ena~combout ; +wire \z80_|alu_|db_high[2]~10_combout ; +wire \z80_|alu_|db_high[2]~12_combout ; +wire \z80_|alu_|db_high[3]~1_combout ; +wire \z80_|alu_|db_high[2]~13_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~78_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~79_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ; +wire \z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~75_combout ; +wire \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~76_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~77_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~80_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~74_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~73_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~81_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~19_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~18_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~20_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~92_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~21_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ; +wire \z80_|reg_file_|db_lo_as[0]~2_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~55_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~56_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~57_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~59_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~58_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~60_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~53_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~54_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~61_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~62_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ; +wire \z80_|reg_file_|db_lo_as[4]~13_combout ; +wire \z80_|reg_file_|db_lo_as[4]~14_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ; +wire \z80_|reg_file_|db_lo_as[4]~15_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~64_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~63_combout ; +wire \z80_|reg_file_|b2v_latch_af_lo|latch[5]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~65_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~69_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~68_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~66_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~67_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~70_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~71_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~72_combout ; +wire \z80_|reg_file_|db_lo_as[5]~16_combout ; +wire \z80_|reg_file_|db_lo_as[5]~17_combout ; +wire \z80_|reg_file_|db_lo_as[5]~18_combout ; +wire \z80_|execute_|ctl_inc_dec~10_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ; +wire \z80_|reg_file_|db_lo_as[6]~19_combout ; +wire \z80_|reg_file_|db_lo_as[6]~20_combout ; +wire \z80_|reg_file_|db_lo_as[6]~21_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~82_combout ; +wire \z80_|reg_file_|db_lo_ds[6]~0_combout ; +wire \z80_|sw1_|db_down[6]~1_combout ; +wire \z80_|execute_|ctl_66_oe~combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~4_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~2_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~3_combout ; wire \z80_|alu_|alu_op2[1]~1_combout ; wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ; -wire \z80_|execute_|ctl_alu_core_S~9_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8_combout ; -wire \z80_|alu_|alu_op2[0]~3_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~12_combout ; -wire \z80_|execute_|ctl_alu_core_S~8_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ; -wire \z80_|execute_|ctl_alu_core_hf~21_combout ; -wire \z80_|execute_|ctl_alu_core_hf~22_combout ; -wire \z80_|execute_|ctl_alu_core_hf~19_combout ; -wire \z80_|execute_|ctl_alu_op_low~27_combout ; -wire \z80_|execute_|ctl_alu_op_low~29_combout ; -wire \z80_|execute_|ctl_alu_core_hf~23_combout ; -wire \z80_|execute_|ctl_alu_core_hf~37_combout ; -wire \z80_|execute_|ctl_alu_core_hf~38_combout ; -wire \z80_|execute_|ctl_alu_core_hf~24_combout ; -wire \z80_|execute_|ctl_alu_core_hf~25_combout ; -wire \z80_|execute_|ctl_alu_core_hf~26_combout ; -wire \z80_|execute_|ctl_alu_core_hf~27_combout ; -wire \z80_|execute_|ctl_alu_core_hf~28_combout ; -wire \z80_|execute_|ctl_alu_op_low~30_combout ; -wire \z80_|execute_|ctl_alu_core_hf~34_combout ; -wire \z80_|execute_|ctl_alu_core_hf~32_combout ; -wire \z80_|execute_|ctl_alu_core_hf~43_combout ; -wire \z80_|execute_|ctl_alu_core_hf~33_combout ; -wire \z80_|execute_|ctl_alu_core_hf~42_combout ; -wire \z80_|execute_|ctl_alu_core_hf~35_combout ; -wire \z80_|execute_|ctl_alu_core_hf~41_combout ; -wire \z80_|execute_|ctl_alu_core_hf~30_combout ; -wire \z80_|execute_|ctl_mWrite~10_combout ; -wire \z80_|execute_|ctl_alu_core_hf~31_combout ; -wire \z80_|execute_|ctl_alu_core_hf~44_combout ; -wire \z80_|execute_|ctl_alu_core_hf~29_combout ; -wire \z80_|execute_|ctl_alu_core_hf~36_combout ; -wire \z80_|execute_|ctl_alu_core_hf~39_combout ; -wire \z80_|execute_|ctl_alu_core_hf~40_combout ; -wire \z80_|execute_|ctl_flags_hf_we~2_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ; +wire \z80_|execute_|ctl_alu_core_R~5_combout ; wire \z80_|execute_|ctl_alu_core_R~2_combout ; wire \z80_|execute_|ctl_alu_core_R~combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3_combout ; -wire \z80_|alu_|alu_op2[3]~2_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ; +wire \z80_|alu_|db_high[0]~20_combout ; +wire \z80_|alu_|db_high[0]~21_combout ; +wire \z80_|alu_|db_high[0]~22_combout ; +wire \z80_|alu_|db_high[0]~23_combout ; +wire \z80_|alu_|db_high[0]~24_combout ; +wire \z80_|alu_|db_low[0]~4_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~2_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~3_combout ; +wire \z80_|alu_|db_low[0]~5_combout ; +wire \z80_|alu_|db_low[0]~6_combout ; +wire \z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ; +wire \z80_|execute_|ctl_flags_hf_we~2_combout ; +wire \z80_|execute_|ctl_flags_cf_we~3_combout ; +wire \z80_|execute_|ctl_flags_cf_we~4_combout ; +wire \z80_|execute_|ctl_flags_cf_we~5_combout ; +wire \z80_|execute_|ctl_flags_cf_we~6_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf~q ; +wire \z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ; +wire \z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ; +wire \z80_|alu_|db_low[0]~2_combout ; +wire \z80_|alu_|db_low[0]~3_combout ; +wire \z80_|alu_|db_low[0]~24_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~0_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~1_combout ; +wire \z80_|alu_|alu_op2[0]~3_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla26M3T5_8~combout ; +wire \z80_|execute_|ctl_alu_core_hf~14_combout ; +wire \z80_|execute_|ctl_alu_core_hf~16_combout ; +wire \z80_|execute_|ctl_alu_core_hf~13_combout ; +wire \z80_|execute_|ctl_alu_core_hf~17_combout ; +wire \z80_|execute_|ctl_alu_op_low~44_combout ; +wire \z80_|execute_|ctl_alu_core_hf~20_combout ; +wire \z80_|execute_|ctl_alu_core_hf~21_combout ; +wire \z80_|execute_|ctl_alu_core_hf~18_combout ; +wire \z80_|execute_|ctl_alu_core_hf~19_combout ; +wire \z80_|execute_|ctl_alu_core_hf~22_combout ; +wire \z80_|execute_|ctl_alu_op_low~43_combout ; +wire \z80_|execute_|ctl_alu_core_hf~24_combout ; +wire \z80_|execute_|ctl_alu_core_hf~25_combout ; +wire \z80_|execute_|ctl_alu_core_hf~35_combout ; +wire \z80_|execute_|ctl_alu_core_hf~23_combout ; +wire \z80_|execute_|ctl_alu_core_hf~26_combout ; +wire \z80_|execute_|ctl_alu_core_hf~34_combout ; +wire \z80_|execute_|ctl_alu_core_hf~27_combout ; +wire \z80_|execute_|ctl_alu_core_hf~28_combout ; +wire \z80_|execute_|ctl_alu_core_hf~29_combout ; +wire \z80_|execute_|ctl_alu_core_hf~30_combout ; +wire \z80_|execute_|ctl_alu_core_hf~31_combout ; +wire \z80_|execute_|ctl_alu_core_hf~36_combout ; +wire \z80_|execute_|ctl_alu_core_hf~37_combout ; +wire \z80_|execute_|ctl_alu_core_hf~32_combout ; +wire \z80_|execute_|ctl_alu_core_hf~33_combout ; +wire \z80_|alu_control_|alu_core_cf_in~0_combout ; +wire \z80_|alu_|alu_op1[0]~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ; +wire \z80_|alu_|db_high[0]~25_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~6_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ; +wire \z80_|alu_|db_high[1]~14_combout ; +wire \z80_|alu_|db_high[1]~15_combout ; +wire \z80_|alu_|db_high[1]~16_combout ; +wire \z80_|alu_|db_high[1]~17_combout ; +wire \z80_|alu_|db_high[1]~18_combout ; +wire \z80_|alu_|db_high[1]~19_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ; +wire \z80_|alu_control_|out[6]~0_combout ; +wire \z80_|alu_control_|out[6]~1_combout ; +wire \z80_|alu_control_|out[6]~2_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ; +wire \z80_|execute_|ctl_flags_sz_we~7_combout ; +wire \z80_|execute_|ctl_flags_sz_we~8_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ; +wire \z80_|execute_|setM1~51_combout ; +wire \z80_|execute_|ctl_flags_oe~2_combout ; +wire \z80_|execute_|ctl_sw_2u~7_combout ; +wire \z80_|alu_control_|db[6]~20_combout ; +wire \z80_|alu_control_|db[6]~21_combout ; +wire \z80_|execute_|ctl_reg_out_lo~8_combout ; +wire \z80_|alu_control_|db[6]~10_combout ; +wire \z80_|alu_control_|db[6]~11_combout ; +wire \z80_|alu_control_|db[6]~22_combout ; +wire \z80_|alu_|db[6]~21_combout ; +wire \z80_|alu_|db[6]~22_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~80_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~79_combout ; +wire \z80_|reg_file_|b2v_latch_bc_hi|latch[6]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~78_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~82_combout ; +wire \z80_|reg_file_|b2v_latch_hl2_hi|db[6]~5_combout ; +wire \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~76_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~77_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~83_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~84_combout ; +wire \z80_|reg_file_|db_hi_as[6]~22_combout ; +wire \z80_|reg_file_|db_hi_as[6]~23_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~61_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~62_combout ; +wire \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~60_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~63_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~64_combout ; +wire \z80_|reg_file_|b2v_latch_hl2_hi|db[4]~4_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~58_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~59_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~65_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~66_combout ; +wire \z80_|reg_file_|db_hi_as[4]~16_combout ; +wire \z80_|reg_file_|db_hi_as[4]~17_combout ; +wire \z80_|reg_file_|db_hi_as[4]~18_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ; +wire \z80_|reg_file_|db_hi_as[6]~24_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|address[15]~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|address[15]~1_combout ; +wire \z80_|reg_file_|db_hi_as[7]~19_combout ; +wire \z80_|reg_file_|db_hi_as[7]~20_combout ; +wire \z80_|reg_file_|db_hi_as[7]~21_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[7]~15_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~72_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~71_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~70_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~69_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~73_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~68_combout ; +wire \z80_|reg_file_|b2v_latch_de_hi|latch[7]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~67_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~74_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~75_combout ; +wire \z80_|alu_|db[7]~11_combout ; +wire \z80_|alu_|db[7]~12_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf2~q ; +wire \z80_|execute_|ctl_flags_use_cf2~8_combout ; +wire \z80_|execute_|ctl_flags_use_cf2~9_combout ; +wire \z80_|execute_|ctl_flags_use_cf2~10_combout ; +wire \z80_|execute_|ctl_flags_use_cf2~11_combout ; +wire \z80_|execute_|ctl_flags_use_cf2~12_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ; +wire \z80_|execute_|ctl_alu_op_low~46_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~9_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~3_combout ; +wire \z80_|alu_flags_|flags_cf~combout ; +wire \z80_|sw2_|db_up[0]~0_combout ; +wire \z80_|alu_control_|db[0]~8_combout ; +wire \z80_|reg_file_|db_lo_as[0]~0_combout ; +wire \z80_|reg_file_|db_lo_as[0]~1_combout ; +wire \z80_|execute_|ctl_inc_cy~70_combout ; +wire \z80_|execute_|pc_inc_hold~28_combout ; +wire \z80_|execute_|pc_inc_hold~15_combout ; +wire \z80_|execute_|pc_inc_hold~27_combout ; +wire \z80_|execute_|pc_inc_hold~10_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ; +wire \z80_|execute_|pc_inc_hold~11_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ; +wire \z80_|execute_|pc_inc_hold~9_combout ; +wire \z80_|execute_|pc_inc_hold~12_combout ; +wire \z80_|execute_|pc_inc_hold~7_combout ; +wire \z80_|execute_|pc_inc_hold~8_combout ; +wire \z80_|execute_|pc_inc_hold~13_combout ; +wire \z80_|execute_|pc_inc_hold~14_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ; +wire \z80_|execute_|pc_inc_hold~16_combout ; +wire \z80_|execute_|pc_inc_hold~22_combout ; +wire \z80_|execute_|pc_inc_hold~23_combout ; +wire \z80_|execute_|pc_inc_hold~24_combout ; +wire \z80_|execute_|ctl_inc_cy~41_combout ; +wire \z80_|execute_|pc_inc_hold~21_combout ; +wire \z80_|execute_|pc_inc_hold~25_combout ; +wire \z80_|execute_|ctl_inc_cy~69_combout ; +wire \z80_|execute_|pc_inc_hold~17_combout ; +wire \z80_|execute_|ctl_inc_cy~71_combout ; +wire \z80_|execute_|ctl_inc_cy~44_combout ; +wire \z80_|execute_|ctl_inc_cy~42_combout ; +wire \z80_|execute_|ctl_inc_cy~43_combout ; +wire \z80_|execute_|ctl_inc_cy~57_combout ; +wire \z80_|execute_|ctl_inc_cy~54_combout ; +wire \z80_|execute_|ctl_inc_cy~58_combout ; +wire \z80_|execute_|pc_inc_hold~18_combout ; +wire \z80_|execute_|pc_inc_hold~19_combout ; +wire \z80_|execute_|ctl_inc_cy~45_combout ; +wire \z80_|execute_|ctl_inc_cy~34_combout ; +wire \z80_|execute_|ctl_inc_cy~35_combout ; +wire \z80_|execute_|ctl_inc_cy~46_combout ; +wire \z80_|execute_|ctl_inc_cy~47_combout ; +wire \z80_|execute_|ctl_inc_cy~48_combout ; +wire \z80_|execute_|ctl_inc_cy~50_combout ; +wire \z80_|execute_|ctl_inc_cy~51_combout ; +wire \z80_|execute_|ctl_inc_cy~85_combout ; +wire \z80_|execute_|ctl_inc_cy~63_combout ; +wire \z80_|execute_|ctl_inc_cy~64_combout ; +wire \z80_|execute_|ctl_inc_cy~65_combout ; +wire \z80_|execute_|ctl_inc_cy~59_combout ; +wire \z80_|execute_|ctl_inc_cy~60_combout ; +wire \z80_|execute_|ctl_inc_cy~61_combout ; +wire \z80_|execute_|ctl_inc_cy~62_combout ; +wire \z80_|execute_|ctl_inc_cy~66_combout ; +wire \z80_|execute_|ctl_inc_cy~53_combout ; +wire \z80_|execute_|ctl_inc_cy~52_combout ; +wire \z80_|execute_|ctl_inc_cy~84_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ; +wire \z80_|execute_|ctl_inc_cy~55_combout ; +wire \z80_|execute_|ctl_inc_cy~56_combout ; +wire \z80_|execute_|ctl_inc_cy~67_combout ; +wire \z80_|execute_|pc_inc_hold~20_combout ; +wire \z80_|execute_|ctl_inc_cy~83_combout ; +wire \z80_|execute_|ctl_inc_cy~68_combout ; +wire \z80_|address_latch_|Q[0]~feeder_combout ; +wire \z80_|execute_|ctl_inc_cy~72_combout ; +wire \z80_|execute_|ctl_inc_cy~73_combout ; +wire \z80_|execute_|ctl_inc_cy~74_combout ; +wire \z80_|execute_|ctl_inc_cy~75_combout ; +wire \z80_|execute_|ctl_inc_cy~76_combout ; +wire \z80_|execute_|ctl_inc_cy~80_combout ; +wire \z80_|execute_|ctl_inc_cy~81_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ; +wire \z80_|reg_file_|db_lo_as[0]~3_combout ; +wire \z80_|reg_file_|b2v_latch_af_lo|latch[0]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~13_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~12_combout ; +wire \z80_|reg_file_|b2v_latch_de_lo|latch[0]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~10_combout ; +wire \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~11_combout ; +wire \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~14_combout ; +wire \z80_|reg_file_|b2v_latch_sp_lo|latch[0]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~15_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~16_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~17_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~22_combout ; +wire \z80_|alu_control_|db[0]~9_combout ; +wire \z80_|alu_control_|db[0]~12_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~84_combout ; +wire \z80_|reg_file_|b2v_latch_de_lo|latch[7]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~83_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~88_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~86_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~87_combout ; +wire \z80_|reg_file_|b2v_latch_wz_lo|db[7]~0_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~89_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~85_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~90_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~91_combout ; +wire \z80_|reg_file_|db_lo_as[7]~22_combout ; +wire \z80_|reg_file_|db_lo_as[7]~23_combout ; +wire \z80_|reg_file_|db_lo_as[7]~24_combout ; +wire \z80_|address_latch_|Q[7]~feeder_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ; +wire \z80_|reg_file_|db_hi_as[0]~4_combout ; +wire \z80_|reg_file_|db_hi_as[0]~5_combout ; +wire \z80_|reg_file_|db_hi_as[0]~6_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~23_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~25_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~27_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~24_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~26_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~28_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[0]~11_combout ; +wire \z80_|reg_file_|b2v_latch_de_hi|latch[0]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~22_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~29_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~30_combout ; +wire \z80_|alu_|db[0]~13_combout ; +wire \z80_|alu_|db[0]~14_combout ; +wire \z80_|alu_|db_low[1]~10_combout ; +wire \z80_|alu_|db_low[1]~11_combout ; +wire \z80_|alu_|db_low[1]~8_combout ; +wire \z80_|alu_|db_low[1]~7_combout ; +wire \z80_|alu_|result_lo[1]~feeder_combout ; +wire \z80_|alu_|db_low[1]~9_combout ; +wire \z80_|alu_|db_low[1]~12_combout ; +wire \z80_|alu_|db[1]~8_combout ; +wire \z80_|alu_|db[1]~10_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~12_combout ; +wire \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~11_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~10_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~13_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~14_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[1]~10_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~9_combout ; +wire \z80_|reg_file_|b2v_latch_de_hi|latch[1]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~8_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~15_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~21_combout ; +wire \z80_|reg_file_|db_hi_as[1]~0_combout ; +wire \z80_|reg_file_|db_hi_as[1]~1_combout ; +wire \z80_|reg_file_|db_hi_as[1]~3_combout ; +wire \z80_|address_latch_|Q[9]~feeder_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ; +wire \z80_|reg_file_|db_hi_as[2]~7_combout ; +wire \z80_|reg_file_|db_hi_as[2]~8_combout ; +wire \z80_|reg_file_|db_hi_as[2]~9_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~39_combout ; +wire \z80_|alu_|db[2]~15_combout ; +wire \z80_|alu_|db[2]~16_combout ; +wire \z80_|alu_control_|db[2]~27_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ; +wire \z80_|alu_flags_|flags_hf2~0_combout ; +wire \z80_|alu_flags_|flags_hf2~q ; +wire \z80_|alu_control_|db[2]~23_combout ; +wire \z80_|alu_control_|db[2]~29_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~39_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~35_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~40_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~41_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~42_combout ; +wire \z80_|reg_file_|db_lo_as[2]~7_combout ; +wire \z80_|reg_file_|db_lo_as[2]~8_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ; +wire \z80_|reg_file_|db_lo_as[2]~9_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ; +wire \z80_|reg_file_|db_lo_as[3]~10_combout ; +wire \z80_|reg_file_|db_lo_as[3]~11_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ; +wire \z80_|reg_file_|db_lo_as[3]~12_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ; +wire \z80_|reg_file_|db_hi_as[3]~12_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~41_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~45_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~44_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~43_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~42_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~46_combout ; +wire \z80_|reg_file_|b2v_latch_de_hi|latch[3]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~40_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[3]~13_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~47_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~48_combout ; +wire \z80_|alu_|db[3]~19_combout ; +wire \z80_|alu_|db[3]~20_combout ; +wire \z80_|alu_|db_low[2]~21_combout ; +wire \z80_|alu_|db_low[2]~22_combout ; +wire \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~6_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~7_combout ; +wire \z80_|alu_|db_low[2]~18_combout ; +wire \z80_|alu_|db_low[2]~19_combout ; +wire \z80_|alu_|db_low[2]~20_combout ; +wire \z80_|alu_|db_low[2]~23_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~7_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~8_combout ; +wire \z80_|alu_|alu_op1[2]~1_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ; wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ; wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ; @@ -1350,449 +1582,292 @@ wire \z80_|execute_|ctl_flags_hf_we~3_combout ; wire \z80_|execute_|ctl_flags_hf_we~4_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_hf~q ; -wire \z80_|execute_|ctl_flags_hf_cpl~11_combout ; -wire \z80_|execute_|ctl_flags_hf_cpl~12_combout ; -wire \z80_|execute_|ctl_flags_hf_cpl~13_combout ; wire \z80_|alu_flags_|flags_hf~combout ; -wire \z80_|alu_control_|alu_core_cf_in~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ; -wire \z80_|alu_|db_high[0]~23_combout ; -wire \z80_|address_latch_|Q[12]~feeder_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ; -wire \z80_|reg_file_|db_hi_as[4]~16_combout ; -wire \z80_|reg_file_|db_hi_as[4]~17_combout ; -wire \z80_|reg_file_|db_hi_as[4]~18_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~62_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~63_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~61_combout ; -wire \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~60_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~64_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~59_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~58_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[4]~19_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~65_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~66_combout ; -wire \z80_|alu_|db[4]~16_combout ; -wire \z80_|alu_|db[7]~26_combout ; +wire \z80_|alu_control_|db[4]~30_combout ; +wire \z80_|alu_control_|db[4]~31_combout ; +wire \z80_|alu_control_|db[4]~32_combout ; wire \z80_|alu_|db[4]~17_combout ; -wire \z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ; -wire \z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ; -wire \z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ; -wire \z80_|alu_|db_high[0]~24_combout ; -wire \z80_|alu_|db_high[0]~21_combout ; -wire \z80_|alu_|db_high[0]~22_combout ; -wire \z80_|alu_|db_high[0]~25_combout ; -wire \z80_|alu_|db_high[0]~26_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|ena~combout ; -wire \z80_|alu_|alu_op1[0]~1_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ; -wire \z80_|alu_|alu_op1[1]~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ; -wire \z80_|alu_|alu_op1[2]~2_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ; -wire \z80_|execute_|ctl_alu_core_R~5_combout ; +wire \z80_|alu_|db[4]~18_combout ; +wire \z80_|alu_|db_low[3]~13_combout ; +wire \z80_|alu_|db_low[3]~14_combout ; +wire \z80_|alu_|db_low[3]~17_combout ; +wire \z80_|alu_|db_low[3]~25_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~4_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~5_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1_combout ; +wire \z80_|alu_|alu_op2[3]~2_combout ; wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout ; wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ; -wire \z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~69_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~70_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~72_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~71_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~73_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~67_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[7]~20_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~68_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~74_combout ; -wire \z80_|reg_file_|db_hi_as[7]~19_combout ; -wire \z80_|reg_file_|db_hi_as[7]~20_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~54_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~53_combout ; -wire \z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~51_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~52_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~55_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~49_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~50_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[5]~14_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~56_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~57_combout ; -wire \z80_|reg_file_|db_hi_as[5]~13_combout ; -wire \z80_|reg_file_|db_hi_as[5]~14_combout ; -wire \z80_|reg_file_|db_hi_as[5]~15_combout ; -wire \z80_|address_latch_|Q[13]~feeder_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~76_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~80_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~79_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~78_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~81_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~82_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~77_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[6]~21_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~83_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~84_combout ; -wire \z80_|reg_file_|db_hi_as[6]~22_combout ; -wire \z80_|reg_file_|db_hi_as[6]~23_combout ; -wire \z80_|reg_file_|db_hi_as[6]~24_combout ; -wire \z80_|address_latch_|Q[14]~feeder_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout ; -wire \z80_|reg_file_|db_hi_as[7]~21_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~75_combout ; -wire \z80_|alu_|db[7]~20_combout ; -wire \z80_|alu_|db[7]~21_combout ; -wire \z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ; -wire \z80_|execute_|ctl_flags_cf_we~4_combout ; -wire \z80_|execute_|ctl_flags_cf_we~5_combout ; -wire \z80_|execute_|ctl_flags_cf_we~3_combout ; -wire \z80_|execute_|ctl_flags_cf_we~6_combout ; -wire \z80_|execute_|ctl_flags_cf2_we~2_combout ; -wire \z80_|execute_|ctl_flags_cf2_we~4_combout ; -wire \z80_|execute_|ctl_flags_cf2_we~3_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf~q ; -wire \z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ; -wire \z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ; -wire \z80_|alu_|db_high[3]~5_combout ; -wire \z80_|alu_|db_high[3]~6_combout ; +wire \z80_|alu_|db_high[3]~3_combout ; wire \z80_|alu_|db_high[3]~4_combout ; -wire \z80_|alu_|db_high[3]~27_combout ; +wire \z80_|alu_|db_high[3]~5_combout ; +wire \z80_|alu_|db_high[3]~2_combout ; +wire \z80_|alu_|db_high[3]~6_combout ; wire \z80_|alu_|db_high[3]~7_combout ; -wire \z80_|alu_|db_high[3]~8_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4_combout ; -wire \z80_|alu_|db_low[3]~9_combout ; -wire \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ; -wire \z80_|alu_|db_low[3]~10_combout ; -wire \z80_|alu_|db_low[3]~7_combout ; -wire \z80_|alu_|db_low[3]~8_combout ; -wire \z80_|alu_|db_low[3]~11_combout ; -wire \z80_|alu_|db_low[3]~25_combout ; -wire \z80_|alu_|db[3]~10_combout ; -wire \z80_|alu_|db[3]~11_combout ; -wire \z80_|execute_|ctl_sw_2u~7_combout ; -wire \z80_|execute_|setM1~49_combout ; -wire \z80_|execute_|ctl_flags_oe~2_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ; -wire \z80_|execute_|ctl_flags_sz_we~7_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ; -wire \z80_|execute_|ctl_flags_xy_we~13_combout ; -wire \z80_|execute_|ctl_flags_xy_we~14_combout ; -wire \z80_|execute_|ctl_flags_xy_we~15_combout ; -wire \z80_|alu_flags_|flags_xf~q ; -wire \z80_|alu_control_|db[3]~33_combout ; -wire \z80_|execute_|ctl_reg_out_lo~3_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ; -wire \z80_|execute_|ctl_reg_out_lo~4_combout ; -wire \z80_|execute_|ctl_reg_out_lo~5_combout ; -wire \z80_|execute_|ctl_reg_out_lo~8_combout ; -wire \z80_|sw1_|db_down[3]~1_combout ; -wire \z80_|alu_control_|db[3]~34_combout ; -wire \z80_|alu_control_|db[3]~35_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~46_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~47_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~50_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~44_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~43_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~51_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~52_combout ; -wire \z80_|reg_file_|db_lo_as[3]~10_combout ; -wire \z80_|reg_file_|db_lo_as[3]~11_combout ; -wire \z80_|reg_file_|db_lo_as[3]~12_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~53_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~54_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~58_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~59_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~60_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~57_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~55_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~56_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~61_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~62_combout ; -wire \z80_|reg_file_|db_lo_as[4]~13_combout ; -wire \z80_|reg_file_|db_lo_as[4]~14_combout ; -wire \z80_|reg_file_|db_lo_as[4]~15_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~64_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~63_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~66_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~67_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~65_combout ; -wire \z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~69_combout ; -wire \z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~68_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~70_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~71_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~72_combout ; -wire \z80_|reg_file_|db_lo_as[5]~16_combout ; -wire \z80_|reg_file_|db_lo_as[5]~17_combout ; -wire \z80_|reg_file_|db_lo_as[5]~18_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout ; -wire \z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~74_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~73_combout ; -wire \z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~78_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~79_combout ; -wire \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~76_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~77_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~80_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~75_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~81_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~82_combout ; -wire \z80_|reg_file_|db_lo_as[6]~19_combout ; -wire \z80_|reg_file_|db_lo_as[6]~20_combout ; -wire \z80_|reg_file_|db_lo_as[6]~21_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ; -wire \z80_|reg_file_|db_lo_as[7]~24_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~83_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~84_combout ; -wire \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~88_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~86_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~87_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~85_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~89_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~90_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~91_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~92_combout ; -wire \z80_|reg_file_|db_lo_ds[7]~0_combout ; -wire \z80_|interrupts_|im2~q ; -wire \z80_|execute_|ctl_mRead~12_combout ; -wire \z80_|execute_|ctl_sw_mask543_en~0_combout ; -wire \z80_|alu_control_|db[7]~17_combout ; -wire \z80_|alu_control_|db[7]~16_combout ; -wire \z80_|alu_control_|db[7]~18_combout ; wire \z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ; -wire \z80_|execute_|ctl_flags_sz_we~8_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_sf~q ; -wire \z80_|pla_decode_|Equal62~3_combout ; -wire \z80_|execute_|ctl_flags_pf_we~5_combout ; -wire \z80_|execute_|ctl_flags_pf_we~6_combout ; -wire \z80_|execute_|ctl_flags_pf_we~7_combout ; -wire \z80_|execute_|ctl_flags_pf_we~8_combout ; -wire \z80_|execute_|ctl_flags_pf_we~9_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~5_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~7_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~6_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~8_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~11_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~12_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~15_combout ; +wire \z80_|alu_|alu_op2[2]~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ; +wire \z80_|alu_control_|DFFE_latch_pf_tmp~q ; +wire \z80_|alu_|alu_parity_out~0_combout ; +wire \z80_|alu_|alu_parity_out~1_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ; -wire \z80_|decode_state_|DFFE_instNonRep~0_combout ; -wire \z80_|decode_state_|DFFE_instNonRep~3_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~1_combout ; wire \z80_|decode_state_|DFFE_instNonRep~2_combout ; wire \z80_|decode_state_|DFFE_instNonRep~1_combout ; +wire \z80_|decode_state_|DFFE_instNonRep~3_combout ; +wire \z80_|decode_state_|DFFE_instNonRep~0_combout ; wire \z80_|decode_state_|DFFE_instNonRep~4_combout ; wire \z80_|decode_state_|DFFE_instNonRep~5_combout ; wire \z80_|decode_state_|DFFE_instNonRep~q ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~1_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ; -wire \z80_|alu_control_|DFFE_latch_pf_tmp~q ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ; -wire \z80_|alu_|alu_parity_out~0_combout ; -wire \z80_|alu_|alu_parity_out~combout ; wire \z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_pf~10_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_pf~q ; wire \z80_|alu_control_|sel[1]~0_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ; wire \z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ; wire \z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ; wire \z80_|alu_control_|flags_cond_true~0_combout ; wire \z80_|alu_control_|flags_cond_true~q ; -wire \z80_|execute_|ctl_reg_sel_wz~13_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~14_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~17_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~18_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~20_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~21_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~20_combout ; +wire \z80_|execute_|ctl_sw_4d~1_combout ; +wire \z80_|execute_|ctl_sw_4d~6_combout ; +wire \z80_|reg_file_|db_lo_as[1]~4_combout ; +wire \z80_|reg_file_|db_lo_as[1]~5_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ; +wire \z80_|reg_file_|db_lo_as[1]~6_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~29_combout ; wire \z80_|reg_file_|gdfx_temp0[1]~28_combout ; wire \z80_|reg_file_|gdfx_temp0[1]~26_combout ; wire \z80_|reg_file_|gdfx_temp0[1]~27_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~29_combout ; -wire \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~25_combout ; wire \z80_|reg_file_|gdfx_temp0[1]~30_combout ; -wire \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder_combout ; wire \z80_|reg_file_|gdfx_temp0[1]~24_combout ; wire \z80_|reg_file_|gdfx_temp0[1]~23_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~25_combout ; wire \z80_|reg_file_|gdfx_temp0[1]~31_combout ; wire \z80_|reg_file_|gdfx_temp0[1]~32_combout ; wire \z80_|reg_file_|db_lo_ds[1]~1_combout ; wire \z80_|alu_control_|db[1]~25_combout ; wire \z80_|alu_control_|db[1]~24_combout ; wire \z80_|alu_control_|db[1]~26_combout ; -wire \z80_|alu_|db[1]~12_combout ; -wire \z80_|alu_|db[1]~13_combout ; -wire \z80_|alu_|db_low[0]~21_combout ; -wire \z80_|alu_|db_low[0]~22_combout ; -wire \z80_|alu_|db_low[0]~18_combout ; -wire \z80_|alu_|db_low[0]~19_combout ; -wire \z80_|alu_|db_low[0]~20_combout ; -wire \z80_|alu_|db_low[0]~23_combout ; -wire \z80_|alu_|db[0]~18_combout ; -wire \z80_|alu_|db[0]~19_combout ; -wire \z80_|alu_|db_low[1]~15_combout ; -wire \z80_|alu_|db_low[1]~16_combout ; -wire \z80_|alu_|db_low[1]~12_combout ; -wire \z80_|alu_|db_low[1]~13_combout ; -wire \z80_|alu_|db_low[1]~14_combout ; -wire \z80_|alu_|db_low[1]~17_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6_combout ; -wire \z80_|alu_control_|out[6]~0_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ; -wire \z80_|alu_flags_|flags_hf2~0_combout ; -wire \z80_|alu_flags_|flags_hf2~q ; -wire \z80_|alu_control_|db[2]~23_combout ; -wire \z80_|reg_file_|db_lo_ds[2]~2_combout ; -wire \z80_|alu_control_|db[2]~28_combout ; -wire \z80_|alu_control_|db[2]~27_combout ; -wire \z80_|alu_control_|db[2]~29_combout ; -wire \z80_|alu_|db[2]~14_combout ; -wire \z80_|alu_|db[2]~15_combout ; -wire \z80_|alu_|db_low[2]~2_combout ; -wire \z80_|alu_|db_low[2]~3_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1_combout ; -wire \z80_|alu_|db_low[2]~5_combout ; -wire \z80_|alu_|db_low[2]~6_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4_combout ; -wire \z80_|alu_|alu_op2[2]~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ; -wire \z80_|alu_|db_high[2]~9_combout ; -wire \z80_|alu_|db_high[2]~11_combout ; -wire \z80_|alu_|db_high[2]~12_combout ; -wire \z80_|alu_|db_high[2]~10_combout ; -wire \z80_|alu_|db_high[2]~13_combout ; -wire \z80_|alu_|db_high[2]~14_combout ; -wire \z80_|alu_|db[6]~22_combout ; -wire \z80_|alu_|db[6]~23_combout ; -wire \z80_|alu_control_|out[6]~1_combout ; -wire \z80_|alu_control_|out[6]~2_combout ; -wire \z80_|alu_control_|db[6]~19_combout ; -wire \z80_|alu_control_|db[6]~20_combout ; -wire \z80_|alu_control_|db[6]~21_combout ; -wire \z80_|alu_control_|db[6]~22_combout ; -wire \z80_|execute_|ctl_bus_zero_oe~0_combout ; -wire \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ; -wire \z80_|interrupts_|im1~q ; -wire \z80_|execute_|ctl_bus_ff_oe~0_combout ; -wire \z80_|execute_|ctl_bus_ff_oe~1_combout ; -wire \z80_|bus_control_|db[0]~4_combout ; -wire \z80_|bus_control_|db[6]~8_combout ; -wire \z80_|execute_|ctl_mRead~37_combout ; -wire \z80_|execute_|ctl_mRead~28_combout ; -wire \z80_|execute_|ctl_mRead~29_combout ; -wire \z80_|execute_|ctl_mRead~30_combout ; -wire \z80_|execute_|setM1~37_combout ; -wire \z80_|execute_|setM1~55_combout ; -wire \z80_|execute_|setM1~38_combout ; -wire \z80_|execute_|ctl_mRead~34_combout ; -wire \z80_|execute_|nextM~3_combout ; -wire \z80_|execute_|ctl_mRead~31_combout ; -wire \z80_|execute_|ctl_mRead~32_combout ; -wire \z80_|execute_|ctl_mRead~33_combout ; -wire \z80_|execute_|ctl_mRead~35_combout ; -wire \z80_|memory_ifc_|DFFE_mrd_ff1~q ; -wire \z80_|memory_ifc_|wait_mrd~feeder_combout ; -wire \z80_|memory_ifc_|wait_mrd~q ; -wire \z80_|memory_ifc_|DFFE_mrd_ff3~q ; -wire \z80_|memory_ifc_|nRD_out~1_combout ; +wire \z80_|bus_control_|db[1]~10_combout ; wire \z80_|execute_|nextM~4_combout ; wire \z80_|execute_|ctl_iorw~12_combout ; wire \z80_|execute_|ctl_iorw~8_combout ; wire \z80_|execute_|ctl_iorw~9_combout ; wire \z80_|memory_ifc_|DFFE_iorq_ff1~q ; -wire \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder_combout ; wire \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ; +wire \z80_|memory_ifc_|wait_iorq~feeder_combout ; wire \z80_|memory_ifc_|wait_iorq~q ; wire \z80_|memory_ifc_|DFFE_iorq_ff4~q ; wire \z80_|memory_ifc_|iorq~0_combout ; -wire \z80_|execute_|fIORead~1_combout ; -wire \z80_|execute_|fIORead~2_combout ; -wire \z80_|execute_|fIORead~0_combout ; -wire \z80_|execute_|fIORead~3_combout ; wire \z80_|memory_ifc_|DFFE_m1_ff1~q ; wire \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout ; wire \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ; wire \z80_|memory_ifc_|DFFE_m1_ff3~q ; wire \z80_|memory_ifc_|nRD_out~0_combout ; +wire \z80_|execute_|fIORead~0_combout ; +wire \z80_|execute_|fIORead~1_combout ; +wire \z80_|execute_|fIORead~2_combout ; +wire \z80_|execute_|fIOWrite~1_combout ; +wire \z80_|execute_|fIORead~3_combout ; +wire \z80_|execute_|ctl_mRead~30_combout ; +wire \z80_|execute_|ctl_mRead~31_combout ; +wire \z80_|execute_|nextM~3_combout ; +wire \z80_|execute_|ctl_mRead~29_combout ; +wire \z80_|execute_|setM1~58_combout ; +wire \z80_|execute_|setM1~38_combout ; +wire \z80_|execute_|fMRead~4_combout ; +wire \z80_|execute_|setM1~39_combout ; +wire \z80_|execute_|setM1~40_combout ; +wire \z80_|execute_|ctl_mRead~32_combout ; +wire \z80_|execute_|ctl_mRead~33_combout ; +wire \z80_|memory_ifc_|DFFE_mrd_ff1~q ; +wire \z80_|memory_ifc_|wait_mrd~feeder_combout ; +wire \z80_|memory_ifc_|wait_mrd~q ; +wire \z80_|memory_ifc_|DFFE_mrd_ff3~q ; +wire \z80_|memory_ifc_|nRD_out~1_combout ; wire \z80_|memory_ifc_|nRD_out~2_combout ; +wire \z80_|execute_|fIOWrite~3_combout ; +wire \z80_|execute_|fIOWrite~4_combout ; +wire \z80_|execute_|fIOWrite~2_combout ; +wire \z80_|execute_|fIOWrite~5_combout ; +wire \z80_|execute_|ctl_mWrite~15_combout ; +wire \z80_|execute_|ctl_mWrite~12_combout ; +wire \z80_|execute_|ctl_mWrite~13_combout ; +wire \z80_|execute_|ctl_mWrite~14_combout ; +wire \z80_|execute_|ctl_mWrite~16_combout ; +wire \z80_|memory_ifc_|DFFE_mwr_ff1~q ; +wire \z80_|memory_ifc_|wait_mwr~feeder_combout ; +wire \z80_|memory_ifc_|wait_mwr~q ; +wire \z80_|memory_ifc_|mwr_wr~q ; +wire \z80_|memory_ifc_|nWR_out~0_combout ; wire \Equal2~1_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~0_combout ; -wire \z80_|execute_|fMWrite~5_combout ; -wire \z80_|execute_|fMWrite~6_combout ; -wire \z80_|execute_|fMWrite~2_combout ; +wire \z80_|execute_|fMWrite~3_combout ; wire \z80_|execute_|fMWrite~4_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~1_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~2_combout ; +wire \z80_|execute_|fMWrite~0_combout ; +wire \z80_|execute_|fMWrite~2_combout ; wire \z80_|pin_control_|bus_db_pin_oe~3_combout ; -wire \z80_|execute_|fMWrite~7_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~4_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~7_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~6_combout ; -wire \z80_|execute_|fMWrite~9_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~8_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~9_combout ; wire \z80_|execute_|fMWrite~8_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~5_combout ; +wire \z80_|execute_|fMWrite~7_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~16_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~8_combout ; +wire \z80_|execute_|fMWrite~6_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~9_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~7_combout ; wire \z80_|pin_control_|bus_db_pin_oe~10_combout ; -wire \z80_|execute_|fMWrite~10_combout ; wire \z80_|pin_control_|bus_db_pin_oe~11_combout ; +wire \z80_|execute_|fMWrite~5_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~6_combout ; wire \z80_|pin_control_|bus_db_pin_oe~12_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~4_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~5_combout ; wire \z80_|pin_control_|bus_db_pin_oe~13_combout ; wire \z80_|pin_control_|bus_db_pin_oe~14_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~2_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~15_combout ; wire \z80_|clk_delay_|DFF_inst5~feeder_combout ; wire \z80_|clk_delay_|DFF_inst5~q ; -wire \z80_|memory_ifc_|wait_iorqinta~feeder_combout ; wire \z80_|memory_ifc_|wait_iorqinta~q ; wire \z80_|memory_ifc_|DFFE_intr_ff3~q ; wire \z80_|memory_ifc_|nIORQ_out~0_combout ; wire \Equal2~0_combout ; -wire \ExtRamWE~0_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[13]~13_combout ; +wire \z80_|execute_|ctl_apin_mux~2_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[10]~10_combout ; wire \z80_|execute_|ctl_apin_mux2~0_combout ; -wire \z80_|pin_control_|bus_ab_pin_we~2_combout ; -wire \z80_|pin_control_|bus_ab_pin_we~3_combout ; +wire \z80_|pin_control_|bus_ab_pin_we~0_combout ; +wire \z80_|pin_control_|bus_ab_pin_we~1_combout ; +wire \PS2_DAT~input_o ; +wire \ula_|pll_|altpll_component|auto_generated|wire_pll1_locked ; +wire \KEY[0]~input_o ; +wire \reset~combout ; +wire \reset~clkctrl_outclk ; +wire \ula_|ps2_keyboard_|bit_count~3_combout ; +wire \PS2_CLK~input_o ; +wire \ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ; +wire \ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ; +wire \ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ; +wire \ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ; +wire \ula_|ps2_keyboard_|clk_filter[3]~feeder_combout ; +wire \ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ; +wire \ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ; +wire \ula_|ps2_keyboard_|Equal0~0_combout ; +wire \ula_|ps2_keyboard_|Equal0~1_combout ; +wire \ula_|ps2_keyboard_|clk_filter[0]~0_combout ; +wire \ula_|ps2_keyboard_|ps2_clk_in~0_combout ; +wire \ula_|ps2_keyboard_|ps2_clk_in~q ; +wire \ula_|ps2_keyboard_|clk_edge~0_combout ; +wire \ula_|ps2_keyboard_|clk_edge~q ; +wire \ula_|ps2_keyboard_|bit_count~1_combout ; +wire \ula_|ps2_keyboard_|bit_count~2_combout ; +wire \ula_|ps2_keyboard_|bit_count~0_combout ; +wire \ula_|ps2_keyboard_|always1~0_combout ; +wire \ula_|ps2_keyboard_|LessThan0~0_combout ; +wire \ula_|ps2_keyboard_|shiftreg[0]~0_combout ; +wire \ula_|ps2_keyboard_|shiftreg[7]~feeder_combout ; +wire \ula_|ps2_keyboard_|shiftreg[0]~feeder_combout ; +wire \ula_|ps2_keyboard_|WideXor0~0_combout ; +wire \ula_|ps2_keyboard_|WideXor0~1_combout ; +wire \ula_|ps2_keyboard_|WideXor0~2_combout ; +wire \ula_|ps2_keyboard_|scan_code_ready~0_combout ; +wire \ula_|ps2_keyboard_|scan_code_ready~q ; +wire \ula_|zx_keyboard_|Equal0~0_combout ; +wire \ula_|zx_keyboard_|Equal0~1_combout ; +wire \ula_|zx_keyboard_|released~0_combout ; +wire \ula_|zx_keyboard_|released~q ; +wire \ula_|zx_keyboard_|extended~0_combout ; +wire \ula_|zx_keyboard_|extended~q ; +wire \ula_|zx_keyboard_|keys[7][1]~21_combout ; +wire \ula_|zx_keyboard_|keys[5][4]~22_combout ; +wire \ula_|zx_keyboard_|keys[1][4]~23_combout ; +wire \ula_|zx_keyboard_|keys[2][1]~24_combout ; +wire \ula_|zx_keyboard_|keys[2][1]~25_combout ; +wire \ula_|zx_keyboard_|keys[2][1]~q ; +wire \ula_|zx_keyboard_|key_row~0_combout ; +wire \ula_|zx_keyboard_|keys[3][1]~26_combout ; +wire \ula_|zx_keyboard_|keys[3][1]~27_combout ; +wire \ula_|zx_keyboard_|keys[3][1]~28_combout ; +wire \ula_|zx_keyboard_|keys[3][1]~q ; +wire \z80_|address_pins_|DFFE_apin_latch[11]~11_combout ; +wire \z80_|address_pins_|abus[11]~19_combout ; +wire \ula_|zx_keyboard_|keys[7][4]~17_combout ; +wire \ula_|zx_keyboard_|keys[6][4]~18_combout ; +wire \ula_|zx_keyboard_|keys[1][1]~19_combout ; +wire \ula_|zx_keyboard_|keys[1][1]~20_combout ; +wire \ula_|zx_keyboard_|keys[1][1]~q ; +wire \z80_|address_pins_|DFFE_apin_latch[9]~9_combout ; +wire \z80_|address_pins_|abus[9]~17_combout ; +wire \ula_|zx_keyboard_|keys[0][0]~13_combout ; +wire \ula_|zx_keyboard_|shifted~2_combout ; +wire \ula_|zx_keyboard_|keys[0][1]~14_combout ; +wire \ula_|zx_keyboard_|keys[0][1]~15_combout ; +wire \ula_|zx_keyboard_|WideOr17~0_combout ; +wire \ula_|zx_keyboard_|shifted~5_combout ; +wire \ula_|zx_keyboard_|shifted~4_combout ; +wire \ula_|zx_keyboard_|shifted~q ; +wire \ula_|zx_keyboard_|keys[0][1]~12_combout ; +wire \ula_|zx_keyboard_|keys[0][1]~16_combout ; +wire \ula_|zx_keyboard_|keys[0][1]~q ; +wire \z80_|address_pins_|DFFE_apin_latch[8]~8_combout ; +wire \z80_|address_pins_|abus[8]~18_combout ; +wire \D[1]~26_combout ; +wire \D[1]~27_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[12]~12_combout ; +wire \z80_|address_pins_|abus[12]~21_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ; +wire \z80_|address_pins_|DFFE_apin_latch[13]~13_combout ; wire \z80_|address_pins_|abus[13]~20_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~36_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~34_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~35_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~33_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~37_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~q ; +wire \ula_|zx_keyboard_|keys[4][1]~29_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~30_combout ; +wire \ula_|zx_keyboard_|keys[5][2]~31_combout ; +wire \ula_|zx_keyboard_|keys[4][1]~32_combout ; +wire \ula_|zx_keyboard_|keys[4][1]~q ; +wire \D[1]~28_combout ; +wire \z80_|address_pins_|abus[0]~16_combout ; wire \z80_|address_pins_|DFFE_apin_latch[14]~14_combout ; wire \z80_|address_pins_|abus[14]~23_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~40_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~41_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~39_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~38_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~42_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~q ; +wire \ula_|zx_keyboard_|WideOr16~4_combout ; +wire \ula_|zx_keyboard_|WideOr16~2_combout ; +wire \ula_|zx_keyboard_|WideOr16~7_combout ; +wire \ula_|zx_keyboard_|WideOr16~5_combout ; +wire \ula_|zx_keyboard_|WideOr16~6_combout ; +wire \ula_|zx_keyboard_|keys[7][1]~43_combout ; +wire \ula_|zx_keyboard_|keys[7][1]~44_combout ; +wire \ula_|zx_keyboard_|keys[7][1]~q ; wire \z80_|address_pins_|DFFE_apin_latch[15]~15_combout ; wire \z80_|address_pins_|abus[15]~22_combout ; +wire \D[1]~29_combout ; +wire \D[1]~30_combout ; +wire \ExtRamWE~0_combout ; wire \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ; -wire \z80_|address_pins_|abus[0]~16_combout ; wire \z80_|address_pins_|DFFE_apin_latch[1]~1_combout ; wire \z80_|address_pins_|abus[1]~25_combout ; wire \z80_|address_pins_|DFFE_apin_latch[2]~2_combout ; @@ -1807,30 +1882,27 @@ wire \z80_|address_pins_|DFFE_apin_latch[6]~6_combout ; wire \z80_|address_pins_|abus[6]~30_combout ; wire \z80_|address_pins_|DFFE_apin_latch[7]~7_combout ; wire \z80_|address_pins_|abus[7]~31_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[8]~8_combout ; -wire \z80_|address_pins_|abus[8]~18_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[9]~9_combout ; -wire \z80_|address_pins_|abus[9]~17_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[10]~10_combout ; wire \z80_|address_pins_|abus[10]~24_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[11]~11_combout ; -wire \z80_|address_pins_|abus[11]~19_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[12]~12_combout ; -wire \z80_|address_pins_|abus[12]~21_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ; wire \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ; +wire \ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ; wire \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ; -wire \D[6]~90_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout ; wire \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ; -wire \D[6]~91_combout ; -wire \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ; wire \CLOCK_50~inputclkctrl_outclk ; +wire \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ; +wire \Selector3~0_combout ; +wire \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ; wire \~GND~combout ; wire \ula_|video_|vram_address[0]~feeder_combout ; wire \ula_|video_|vram_address~0_combout ; +wire \ula_|video_|vram_address[1]~feeder_combout ; wire \ula_|video_|vram_address[2]~4_combout ; wire \ula_|video_|Add3~0_combout ; wire \ula_|video_|Add3~1_combout ; @@ -1842,483 +1914,369 @@ wire \ula_|video_|Add4~7 ; wire \ula_|video_|Add4~8_combout ; wire \ula_|video_|Add4~9 ; wire \ula_|video_|Add4~10_combout ; +wire \ula_|video_|Add4~0_combout ; wire \ula_|video_|Add4~11 ; wire \ula_|video_|Add4~12_combout ; -wire \ula_|video_|Add4~0_combout ; wire \ula_|video_|Selector6~0_combout ; wire \ula_|video_|vram_address[9]~1_combout ; +wire \ula_|video_|Add4~2_combout ; wire \ula_|video_|Add4~13 ; wire \ula_|video_|Add4~14_combout ; -wire \ula_|video_|Add4~2_combout ; wire \ula_|video_|Selector5~0_combout ; wire \ula_|video_|Add4~4_combout ; wire \ula_|video_|vram_address[10]~2_combout ; wire \ula_|video_|vram_address[10]~3_combout ; wire \ula_|video_|Selector3~0_combout ; wire \ula_|video_|Selector2~0_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ; -wire \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ; -wire \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ; -wire \D[6]~87_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ; -wire \D[6]~88_combout ; -wire \D[6]~89_combout ; -wire \D[6]~111_combout ; -wire \raw_loader_in~input_o ; -wire \D[6]~86_combout ; -wire \D[6]~100_combout ; -wire \D[6]~101_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout ; +wire \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ; +wire \Selector1~0_combout ; +wire \Selector1~1_combout ; +wire \D[1]~81_combout ; +wire \D[1]~31_combout ; +wire \D[1]~32_combout ; wire \z80_|pin_control_|bus_db_pin_re~2_combout ; wire \z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ; -wire \z80_|bus_control_|db[6]~9_combout ; -wire \z80_|ir_|opcode[6]~feeder_combout ; -wire \z80_|execute_|ctl_ir_we~13_combout ; -wire \z80_|pla_decode_|Equal41~0_combout ; +wire \z80_|bus_control_|db[1]~11_combout ; +wire \z80_|pla_decode_|Equal2~0_combout ; +wire \z80_|execute_|ctl_mRead~15_combout ; +wire \z80_|execute_|ctl_inc_cy~39_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~36_combout ; +wire \z80_|execute_|ctl_sw_4u~4_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~16_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~17_combout ; +wire \z80_|execute_|ctl_sw_4u~5_combout ; +wire \z80_|execute_|ctl_sw_4u~6_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~44_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~43_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~46_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~47_combout ; +wire \z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~49_combout ; +wire \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~45_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~48_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~50_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~51_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~52_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ; +wire \z80_|execute_|ctl_flags_xy_we~15_combout ; +wire \z80_|execute_|ctl_flags_xy_we~16_combout ; +wire \z80_|execute_|ctl_flags_xy_we~17_combout ; +wire \z80_|execute_|ctl_flags_xy_we~18_combout ; +wire \z80_|alu_flags_|flags_xf~q ; +wire \z80_|alu_control_|db[3]~33_combout ; +wire \z80_|sw1_|db_down[3]~2_combout ; +wire \z80_|alu_control_|db[3]~34_combout ; +wire \z80_|alu_control_|db[3]~35_combout ; +wire \ula_|zx_keyboard_|keys[3][0]~75_combout ; +wire \ula_|zx_keyboard_|Selector5~0_combout ; +wire \ula_|zx_keyboard_|Selector5~1_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~132_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~106_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~107_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~133_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~108_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~q ; +wire \ula_|zx_keyboard_|keys[5][3]~104_combout ; +wire \ula_|zx_keyboard_|keys[5][3]~105_combout ; +wire \ula_|zx_keyboard_|keys[5][3]~q ; +wire \D[3]~55_combout ; +wire \ula_|zx_keyboard_|keys[6][4]~46_combout ; +wire \ula_|zx_keyboard_|keys[5][4]~62_combout ; +wire \ula_|zx_keyboard_|keys[3][3]~102_combout ; +wire \ula_|zx_keyboard_|keys[3][3]~103_combout ; +wire \ula_|zx_keyboard_|keys[3][3]~q ; +wire \ula_|zx_keyboard_|keys[0][4]~96_combout ; +wire \ula_|zx_keyboard_|keys[2][4]~94_combout ; +wire \ula_|zx_keyboard_|keys[0][3]~95_combout ; +wire \ula_|zx_keyboard_|keys[0][3]~97_combout ; +wire \ula_|zx_keyboard_|keys[0][3]~q ; +wire \ula_|zx_keyboard_|keys[6][4]~45_combout ; +wire \ula_|zx_keyboard_|keys[1][3]~92_combout ; +wire \ula_|zx_keyboard_|keys[1][3]~93_combout ; +wire \ula_|zx_keyboard_|keys[1][3]~q ; +wire \D[3]~53_combout ; +wire \ula_|zx_keyboard_|keys[2][3]~99_combout ; +wire \ula_|zx_keyboard_|keys[2][3]~100_combout ; +wire \ula_|zx_keyboard_|keys[2][3]~98_combout ; +wire \ula_|zx_keyboard_|keys[2][3]~101_combout ; +wire \ula_|zx_keyboard_|keys[2][3]~q ; +wire \ula_|zx_keyboard_|key_row~3_combout ; +wire \D[3]~54_combout ; +wire \ula_|zx_keyboard_|keys[0][4]~109_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~60_combout ; +wire \ula_|zx_keyboard_|keys[7][3]~110_combout ; +wire \ula_|zx_keyboard_|keys[7][3]~111_combout ; +wire \ula_|zx_keyboard_|keys[7][3]~112_combout ; +wire \ula_|zx_keyboard_|keys[7][3]~q ; +wire \ula_|zx_keyboard_|Selector13~0_combout ; +wire \ula_|zx_keyboard_|keys[6][3]~113_combout ; +wire \ula_|zx_keyboard_|keys[6][3]~114_combout ; +wire \ula_|zx_keyboard_|keys[6][3]~135_combout ; +wire \ula_|zx_keyboard_|keys[6][3]~136_combout ; +wire \ula_|zx_keyboard_|keys[6][3]~q ; +wire \D[3]~56_combout ; +wire \D[3]~57_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ; +wire \Selector3~1_combout ; +wire \Selector3~2_combout ; +wire \D[3]~85_combout ; +wire \D[3]~73_combout ; +wire \D[3]~74_combout ; +wire \z80_|bus_control_|db[3]~20_combout ; +wire \z80_|bus_control_|db[3]~21_combout ; +wire \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ; +wire \z80_|interrupts_|im2~q ; +wire \z80_|execute_|ctl_mRead~10_combout ; +wire \z80_|execute_|ctl_sw_mask543_en~0_combout ; +wire \z80_|alu_control_|db[7]~16_combout ; +wire \z80_|alu_control_|db[7]~17_combout ; +wire \z80_|alu_control_|db[7]~18_combout ; +wire \z80_|alu_control_|db[7]~19_combout ; +wire \z80_|bus_control_|db[7]~5_combout ; +wire \D[5]~67_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout ; +wire \Mux0~0_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ; +wire \Mux0~1_combout ; +wire \D[7]~89_combout ; +wire \D[7]~72_combout ; +wire \D[0]~84_combout ; +wire \D[7]~80_combout ; +wire \z80_|bus_control_|db[7]~7_combout ; +wire \z80_|pla_decode_|Equal6~0_combout ; +wire \z80_|pla_decode_|Equal12~0_combout ; +wire \z80_|execute_|ctl_mRead~16_combout ; +wire \z80_|execute_|fMRead~24_combout ; +wire \z80_|execute_|fMRead~25_combout ; +wire \z80_|execute_|ctl_mRead~21_combout ; +wire \z80_|execute_|fMRead~16_combout ; +wire \z80_|execute_|fMRead~14_combout ; +wire \z80_|execute_|fMRead~15_combout ; +wire \z80_|execute_|fMRead~12_combout ; +wire \z80_|execute_|fMRead~11_combout ; +wire \z80_|execute_|fMRead~13_combout ; +wire \z80_|execute_|fMRead~17_combout ; +wire \z80_|execute_|fMRead~22_combout ; +wire \z80_|execute_|fMRead~27_combout ; +wire \z80_|execute_|fMRead~37_combout ; +wire \z80_|execute_|fMRead~31_combout ; +wire \z80_|execute_|fMRead~29_combout ; +wire \z80_|execute_|fMRead~30_combout ; +wire \z80_|execute_|fMRead~28_combout ; +wire \z80_|execute_|fMRead~32_combout ; +wire \z80_|execute_|fMRead~33_combout ; +wire \z80_|execute_|fMRead~23_combout ; +wire \z80_|execute_|fMRead~34_combout ; +wire \z80_|execute_|fMRead~35_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~19_combout ; +wire \z80_|execute_|fMRead~36_combout ; +wire \z80_|pin_control_|bus_db_pin_re~combout ; +wire \ula_|zx_keyboard_|keys[2][4]~118_combout ; +wire \ula_|zx_keyboard_|keys[2][4]~119_combout ; +wire \ula_|zx_keyboard_|keys[2][4]~120_combout ; +wire \ula_|zx_keyboard_|keys[2][4]~q ; +wire \ula_|zx_keyboard_|keys[3][4]~129_combout ; +wire \ula_|zx_keyboard_|keys[3][4]~116_combout ; +wire \ula_|zx_keyboard_|keys[3][4]~134_combout ; +wire \ula_|zx_keyboard_|keys[3][4]~117_combout ; +wire \ula_|zx_keyboard_|keys[3][4]~q ; +wire \D[4]~60_combout ; +wire \ula_|zx_keyboard_|Equal0~2_combout ; +wire \ula_|zx_keyboard_|keys[1][4]~121_combout ; +wire \ula_|zx_keyboard_|keys[1][4]~q ; +wire \ula_|zx_keyboard_|keys[0][4]~115_combout ; +wire \ula_|zx_keyboard_|keys[0][4]~q ; +wire \ula_|zx_keyboard_|key_row~4_combout ; +wire \D[4]~61_combout ; +wire \ula_|zx_keyboard_|keys[4][4]~124_combout ; +wire \ula_|zx_keyboard_|keys[4][4]~125_combout ; +wire \ula_|zx_keyboard_|keys[4][4]~126_combout ; +wire \ula_|zx_keyboard_|keys[4][4]~q ; +wire \ula_|zx_keyboard_|keys[5][4]~122_combout ; +wire \ula_|zx_keyboard_|keys[5][4]~123_combout ; +wire \ula_|zx_keyboard_|keys[5][4]~q ; +wire \D[4]~62_combout ; +wire \ula_|zx_keyboard_|keys[7][4]~49_combout ; +wire \ula_|zx_keyboard_|shifted~3_combout ; +wire \ula_|zx_keyboard_|keys[7][4]~127_combout ; +wire \ula_|zx_keyboard_|keys[7][4]~q ; +wire \ula_|zx_keyboard_|keys[6][4]~128_combout ; +wire \ula_|zx_keyboard_|keys[6][4]~q ; +wire \D[4]~63_combout ; +wire \D[4]~64_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ; +wire \Selector4~0_combout ; +wire \Selector4~1_combout ; +wire \D[4]~86_combout ; +wire \D[4]~75_combout ; +wire \D[4]~76_combout ; +wire \z80_|bus_control_|db[4]~18_combout ; +wire \z80_|bus_control_|db[4]~19_combout ; +wire \z80_|pla_decode_|Equal32~0_combout ; wire \z80_|pla_decode_|Equal41~1_combout ; wire \z80_|pla_decode_|Equal41~2_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~combout ; -wire \z80_|alu_|db_high[1]~15_combout ; -wire \z80_|alu_|db_high[1]~16_combout ; -wire \z80_|alu_|db_high[1]~17_combout ; -wire \z80_|alu_|db_high[1]~18_combout ; -wire \z80_|alu_|db_high[1]~19_combout ; -wire \z80_|alu_|db_high[1]~20_combout ; +wire \z80_|pla_decode_|Equal36~0_combout ; +wire \z80_|execute_|ctl_state_tbl_cb_set~combout ; +wire \z80_|execute_|ctl_state_tbl_we~8_combout ; +wire \z80_|decode_state_|DFFE_instCB~q ; +wire \z80_|pla_decode_|Equal52~0_combout ; +wire \z80_|pla_decode_|Equal2~1_combout ; +wire \z80_|execute_|ctl_state_tbl_ed_set~combout ; +wire \z80_|decode_state_|DFFE_instED~q ; +wire \z80_|decode_state_|table_xx~0_combout ; +wire \z80_|pla_decode_|Equal34~0_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~6_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~5_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~4_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~2_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~3_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~7_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~8_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~9_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~10_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~16_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~17_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~15_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~18_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~19_combout ; +wire \z80_|reg_control_|reg_sel_pc~3_combout ; +wire \z80_|reg_control_|reg_sel_pc~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ; +wire \z80_|reg_file_|db_hi_as[0]~2_combout ; +wire \z80_|reg_file_|db_hi_as[5]~13_combout ; +wire \z80_|reg_file_|db_hi_as[5]~14_combout ; +wire \z80_|reg_file_|db_hi_as[5]~15_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~50_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~53_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~54_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~52_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~51_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~55_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[5]~14_combout ; +wire \z80_|reg_file_|b2v_latch_de_hi|latch[5]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~49_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~56_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~57_combout ; +wire \z80_|alu_|db[5]~23_combout ; wire \z80_|alu_|db[5]~24_combout ; -wire \z80_|alu_|db[5]~25_combout ; wire \z80_|sw1_|db_down[5]~0_combout ; wire \z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout ; wire \z80_|alu_flags_|flags_yf~q ; wire \z80_|alu_control_|db[5]~13_combout ; wire \z80_|alu_control_|db[5]~14_combout ; wire \z80_|alu_control_|db[5]~15_combout ; -wire \D[0]~107_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ; wire \ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ; wire \ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout ; wire \rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ; wire \rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout ; wire \Mux2~0_combout ; wire \Mux2~1_combout ; -wire \D[5]~110_combout ; -wire \D[5]~85_combout ; -wire \D[5]~99_combout ; +wire \D[5]~87_combout ; +wire \D[5]~68_combout ; +wire \D[5]~77_combout ; wire \z80_|bus_control_|db[5]~14_combout ; wire \z80_|bus_control_|db[5]~15_combout ; -wire \z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout ; -wire \z80_|decode_state_|DFFE_inst4~q ; -wire \z80_|decode_state_|use_ixiy~combout ; -wire \z80_|execute_|ctl_mRead~23_combout ; -wire \z80_|execute_|fMRead~34_combout ; -wire \z80_|execute_|fMRead~31_combout ; -wire \z80_|execute_|fMRead~29_combout ; -wire \z80_|execute_|fMRead~30_combout ; -wire \z80_|execute_|fMRead~28_combout ; -wire \z80_|execute_|fMRead~32_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~42_combout ; -wire \z80_|execute_|fMRead~14_combout ; -wire \z80_|execute_|fMRead~10_combout ; -wire \z80_|execute_|fMRead~9_combout ; -wire \z80_|execute_|fMRead~11_combout ; -wire \z80_|execute_|fMRead~12_combout ; -wire \z80_|execute_|fMRead~13_combout ; -wire \z80_|execute_|fMRead~15_combout ; -wire \z80_|execute_|fMRead~20_combout ; -wire \z80_|execute_|pc_inc_hold~48_combout ; -wire \z80_|execute_|fMRead~22_combout ; -wire \z80_|execute_|fMRead~21_combout ; -wire \z80_|execute_|fMRead~23_combout ; -wire \z80_|execute_|fMRead~26_combout ; -wire \z80_|execute_|fMRead~25_combout ; -wire \z80_|execute_|fMRead~27_combout ; -wire \z80_|execute_|fMRead~33_combout ; -wire \z80_|execute_|fMRead~35_combout ; -wire \z80_|pin_control_|bus_db_pin_re~combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ; -wire \Selector1~0_combout ; -wire \Selector1~1_combout ; -wire \D[1]~103_combout ; -wire \PS2_DAT~input_o ; -wire \reset~clkctrl_outclk ; -wire \ula_|ps2_keyboard_|bit_count~0_combout ; -wire \PS2_CLK~input_o ; -wire \ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ; -wire \ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ; -wire \ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ; -wire \ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ; -wire \ula_|ps2_keyboard_|Equal0~0_combout ; -wire \ula_|ps2_keyboard_|clk_filter[3]~feeder_combout ; -wire \ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ; -wire \ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ; -wire \ula_|ps2_keyboard_|Equal0~1_combout ; -wire \ula_|ps2_keyboard_|clk_filter[0]~0_combout ; -wire \ula_|ps2_keyboard_|ps2_clk_in~0_combout ; -wire \ula_|ps2_keyboard_|ps2_clk_in~q ; -wire \ula_|ps2_keyboard_|clk_edge~0_combout ; -wire \ula_|ps2_keyboard_|clk_edge~q ; -wire \ula_|ps2_keyboard_|bit_count~1_combout ; -wire \ula_|ps2_keyboard_|bit_count~3_combout ; -wire \ula_|ps2_keyboard_|bit_count~2_combout ; -wire \ula_|ps2_keyboard_|always1~0_combout ; -wire \ula_|ps2_keyboard_|LessThan0~0_combout ; -wire \ula_|ps2_keyboard_|shiftreg[0]~0_combout ; -wire \ula_|zx_keyboard_|Equal0~0_combout ; -wire \ula_|zx_keyboard_|Equal0~1_combout ; -wire \ula_|zx_keyboard_|extended~0_combout ; -wire \ula_|ps2_keyboard_|WideXor0~1_combout ; -wire \ula_|ps2_keyboard_|WideXor0~0_combout ; -wire \ula_|ps2_keyboard_|WideXor0~2_combout ; -wire \ula_|ps2_keyboard_|scan_code_ready~0_combout ; -wire \ula_|ps2_keyboard_|scan_code_ready~q ; -wire \ula_|zx_keyboard_|extended~q ; -wire \ula_|zx_keyboard_|keys[0][0]~15_combout ; -wire \ula_|zx_keyboard_|keys[5][1]~36_combout ; -wire \ula_|zx_keyboard_|keys[5][1]~37_combout ; -wire \ula_|zx_keyboard_|shifted~0_combout ; -wire \ula_|zx_keyboard_|released~0_combout ; -wire \ula_|zx_keyboard_|released~q ; -wire \ula_|zx_keyboard_|WideOr17~0_combout ; -wire \ula_|zx_keyboard_|shifted~2_combout ; -wire \ula_|zx_keyboard_|shifted~3_combout ; -wire \ula_|zx_keyboard_|shifted~q ; -wire \ula_|zx_keyboard_|keys[5][1]~35_combout ; -wire \ula_|zx_keyboard_|keys[5][1]~38_combout ; -wire \ula_|zx_keyboard_|keys[5][1]~39_combout ; -wire \ula_|zx_keyboard_|keys[5][1]~q ; -wire \ula_|zx_keyboard_|keys[4][1]~31_combout ; -wire \ula_|zx_keyboard_|keys[7][1]~23_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~32_combout ; -wire \ula_|zx_keyboard_|keys[5][2]~33_combout ; -wire \ula_|zx_keyboard_|keys[4][1]~34_combout ; -wire \ula_|zx_keyboard_|keys[4][1]~q ; -wire \D[1]~30_combout ; -wire \ula_|zx_keyboard_|keys[5][4]~24_combout ; -wire \ula_|zx_keyboard_|keys[3][1]~28_combout ; -wire \ula_|zx_keyboard_|keys[3][1]~29_combout ; -wire \ula_|zx_keyboard_|keys[3][1]~30_combout ; -wire \ula_|zx_keyboard_|keys[3][1]~q ; -wire \ula_|zx_keyboard_|keys[1][4]~25_combout ; -wire \ula_|zx_keyboard_|keys[2][1]~26_combout ; -wire \ula_|zx_keyboard_|keys[2][1]~27_combout ; -wire \ula_|zx_keyboard_|keys[2][1]~q ; -wire \ula_|zx_keyboard_|key_row~0_combout ; -wire \ula_|zx_keyboard_|keys[0][1]~14_combout ; -wire \ula_|zx_keyboard_|keys[0][1]~16_combout ; -wire \ula_|zx_keyboard_|keys[0][1]~17_combout ; -wire \ula_|zx_keyboard_|keys[0][1]~18_combout ; -wire \ula_|zx_keyboard_|keys[0][1]~q ; -wire \ula_|zx_keyboard_|keys[7][4]~19_combout ; -wire \ula_|zx_keyboard_|keys[6][4]~20_combout ; -wire \ula_|zx_keyboard_|keys[1][1]~21_combout ; -wire \ula_|zx_keyboard_|keys[1][1]~22_combout ; -wire \ula_|zx_keyboard_|keys[1][1]~q ; -wire \D[1]~28_combout ; -wire \D[1]~29_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~41_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~42_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~43_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~40_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~44_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~q ; -wire \ula_|zx_keyboard_|keys[7][1]~45_combout ; -wire \ula_|zx_keyboard_|WideOr16~5_combout ; -wire \ula_|zx_keyboard_|WideOr16~2_combout ; -wire \ula_|zx_keyboard_|WideOr16~4_combout ; -wire \ula_|zx_keyboard_|WideOr16~7_combout ; -wire \ula_|zx_keyboard_|WideOr16~6_combout ; -wire \ula_|zx_keyboard_|keys[7][1]~46_combout ; -wire \ula_|zx_keyboard_|keys[7][1]~q ; -wire \D[1]~31_combout ; -wire \D[1]~32_combout ; -wire \D[1]~33_combout ; -wire \D[1]~34_combout ; -wire \z80_|bus_control_|db[1]~10_combout ; -wire \z80_|bus_control_|db[1]~11_combout ; -wire \z80_|ir_|opcode[1]~feeder_combout ; -wire \z80_|pla_decode_|Equal40~0_combout ; -wire \z80_|pla_decode_|Equal21~1_combout ; -wire \z80_|execute_|ctl_alu_op_low~26_combout ; -wire \z80_|execute_|ctl_alu_op_low~28_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~3_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~2_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~21_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ; -wire \z80_|execute_|ctl_alu_op_low~32_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~19_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf2~q ; -wire \z80_|execute_|ctl_flags_use_cf2~10_combout ; -wire \z80_|execute_|ctl_flags_use_cf2~11_combout ; -wire \z80_|execute_|ctl_flags_use_cf2~8_combout ; -wire \z80_|execute_|ctl_flags_use_cf2~9_combout ; -wire \z80_|execute_|ctl_flags_use_cf2~12_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~20_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~10_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~8_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~5_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~6_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~7_combout ; -wire \z80_|execute_|ctl_flags_cf_set~0_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~4_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~9_combout ; -wire \z80_|alu_flags_|flags_cf~combout ; -wire \z80_|alu_control_|db[0]~8_combout ; -wire \z80_|sw2_|db_up[0]~0_combout ; -wire \z80_|alu_control_|db[0]~9_combout ; -wire \z80_|alu_control_|db[0]~12_combout ; -wire \ula_|zx_keyboard_|keys[5][0]~67_combout ; -wire \ula_|zx_keyboard_|keys[5][0]~81_combout ; -wire \ula_|zx_keyboard_|keys[5][0]~82_combout ; -wire \ula_|zx_keyboard_|keys[5][0]~83_combout ; -wire \ula_|zx_keyboard_|keys[5][0]~q ; -wire \ula_|zx_keyboard_|keys[4][0]~84_combout ; -wire \ula_|zx_keyboard_|keys[4][0]~85_combout ; -wire \ula_|zx_keyboard_|keys[4][0]~86_combout ; -wire \ula_|zx_keyboard_|keys[4][0]~q ; -wire \D[0]~49_combout ; -wire \ula_|zx_keyboard_|WideOr4~0_combout ; -wire \ula_|zx_keyboard_|keys~76_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~73_combout ; -wire \ula_|zx_keyboard_|keys[6][4]~47_combout ; -wire \ula_|zx_keyboard_|WideOr0~0_combout ; -wire \ula_|zx_keyboard_|keys~74_combout ; -wire \ula_|zx_keyboard_|keys[0][0]~75_combout ; -wire \ula_|zx_keyboard_|keys[0][0]~77_combout ; -wire \ula_|zx_keyboard_|keys[0][0]~q ; -wire \ula_|zx_keyboard_|keys[1][0]~71_combout ; -wire \ula_|zx_keyboard_|keys[1][0]~72_combout ; -wire \ula_|zx_keyboard_|keys[1][0]~q ; -wire \D[0]~47_combout ; -wire \ula_|zx_keyboard_|keys[2][0]~80_combout ; -wire \ula_|zx_keyboard_|keys[2][0]~q ; -wire \ula_|zx_keyboard_|keys[3][0]~78_combout ; -wire \ula_|zx_keyboard_|keys[3][0]~79_combout ; -wire \ula_|zx_keyboard_|keys[3][0]~q ; -wire \ula_|zx_keyboard_|key_row~1_combout ; -wire \D[0]~48_combout ; -wire \ula_|zx_keyboard_|shifted~1_combout ; -wire \ula_|zx_keyboard_|keys[6][0]~90_combout ; -wire \ula_|zx_keyboard_|keys[6][0]~91_combout ; -wire \ula_|zx_keyboard_|keys[6][0]~92_combout ; -wire \ula_|zx_keyboard_|keys[6][0]~q ; -wire \ula_|zx_keyboard_|keys[5][4]~63_combout ; -wire \ula_|zx_keyboard_|WideOr16~3_combout ; -wire \ula_|zx_keyboard_|keys[7][0]~87_combout ; -wire \ula_|zx_keyboard_|keys[7][0]~132_combout ; -wire \ula_|zx_keyboard_|keys[7][0]~88_combout ; -wire \ula_|zx_keyboard_|keys[7][0]~89_combout ; -wire \ula_|zx_keyboard_|keys[7][0]~q ; -wire \D[0]~50_combout ; -wire \D[0]~51_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ; -wire \D[0]~55_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ; -wire \D[0]~56_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ; -wire \D[0]~52_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ; -wire \D[0]~53_combout ; -wire \D[0]~54_combout ; -wire \D[0]~106_combout ; -wire \D[0]~57_combout ; -wire \D[0]~58_combout ; -wire \z80_|bus_control_|db[0]~16_combout ; -wire \z80_|bus_control_|db[0]~17_combout ; -wire \z80_|pla_decode_|Equal63~0_combout ; -wire \z80_|execute_|ctl_flags_cf2_sel_daa~combout ; -wire \z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ; -wire \z80_|alu_control_|db[6]~10_combout ; -wire \z80_|alu_control_|db[6]~11_combout ; -wire \z80_|alu_control_|db[4]~30_combout ; -wire \z80_|alu_control_|db[4]~31_combout ; -wire \z80_|alu_control_|db[4]~32_combout ; -wire \ula_|zx_keyboard_|keys[2][4]~119_combout ; -wire \ula_|zx_keyboard_|keys[2][4]~120_combout ; -wire \ula_|zx_keyboard_|keys[2][4]~95_combout ; -wire \ula_|zx_keyboard_|keys[2][4]~121_combout ; -wire \ula_|zx_keyboard_|keys[2][4]~q ; -wire \ula_|zx_keyboard_|keys[3][4]~117_combout ; -wire \ula_|zx_keyboard_|keys[3][4]~136_combout ; -wire \ula_|zx_keyboard_|keys[3][4]~130_combout ; -wire \ula_|zx_keyboard_|keys[3][4]~118_combout ; -wire \ula_|zx_keyboard_|keys[3][4]~q ; -wire \D[4]~78_combout ; -wire \ula_|zx_keyboard_|keys[6][4]~126_combout ; -wire \ula_|zx_keyboard_|keys[5][4]~128_combout ; -wire \ula_|zx_keyboard_|keys[5][4]~129_combout ; -wire \ula_|zx_keyboard_|keys[5][4]~q ; -wire \ula_|zx_keyboard_|keys[6][4]~127_combout ; -wire \ula_|zx_keyboard_|keys[6][4]~q ; -wire \ula_|zx_keyboard_|Equal0~2_combout ; -wire \ula_|zx_keyboard_|keys[7][4]~51_combout ; -wire \ula_|zx_keyboard_|keys[7][4]~125_combout ; -wire \ula_|zx_keyboard_|keys[7][4]~q ; -wire \D[4]~79_combout ; -wire \ula_|zx_keyboard_|keys[4][4]~122_combout ; -wire \ula_|zx_keyboard_|keys[4][4]~123_combout ; -wire \ula_|zx_keyboard_|keys[4][4]~124_combout ; -wire \ula_|zx_keyboard_|keys[4][4]~q ; -wire \ula_|zx_keyboard_|key_row~3_combout ; -wire \D[4]~80_combout ; -wire \ula_|zx_keyboard_|keys[0][4]~111_combout ; -wire \ula_|zx_keyboard_|keys[0][4]~97_combout ; -wire \ula_|zx_keyboard_|keys[0][4]~116_combout ; -wire \ula_|zx_keyboard_|keys[0][4]~q ; -wire \ula_|zx_keyboard_|keys[1][4]~115_combout ; -wire \ula_|zx_keyboard_|keys[1][4]~q ; -wire \D[4]~77_combout ; -wire \D[4]~81_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout ; -wire \Selector4~0_combout ; -wire \Selector4~1_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2_combout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3_combout ; -wire \D[4]~109_combout ; -wire \D[4]~97_combout ; -wire \D[4]~98_combout ; -wire \z80_|bus_control_|db[4]~18_combout ; -wire \z80_|bus_control_|db[4]~19_combout ; -wire \z80_|pla_decode_|Equal21~0_combout ; -wire \z80_|execute_|ctl_mRead~5_combout ; -wire \z80_|execute_|fIOWrite~2_combout ; -wire \z80_|execute_|fIOWrite~3_combout ; -wire \z80_|execute_|fIOWrite~4_combout ; -wire \z80_|execute_|fIOWrite~5_combout ; -wire \z80_|execute_|ctl_mWrite~11_combout ; -wire \z80_|execute_|ctl_mWrite~12_combout ; -wire \z80_|execute_|ctl_mWrite~13_combout ; -wire \z80_|execute_|ctl_mWrite~14_combout ; -wire \z80_|execute_|ctl_mWrite~15_combout ; -wire \z80_|memory_ifc_|DFFE_mwr_ff1~q ; -wire \z80_|memory_ifc_|wait_mwr~feeder_combout ; -wire \z80_|memory_ifc_|wait_mwr~q ; -wire \z80_|memory_ifc_|mwr_wr~q ; -wire \z80_|memory_ifc_|nWR_out~0_combout ; -wire \D[5]~84_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout ; -wire \Mux0~0_combout ; -wire \Mux0~1_combout ; -wire \D[7]~112_combout ; -wire \D[7]~94_combout ; -wire \D[7]~102_combout ; -wire \z80_|bus_control_|db[7]~5_combout ; -wire \z80_|bus_control_|db[7]~7_combout ; -wire \z80_|pla_decode_|Equal77~0_combout ; -wire \z80_|execute_|ctl_mWrite~5_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ; -wire \z80_|execute_|ctl_bus_db_we~3_combout ; +wire \z80_|execute_|ctl_mRead~8_combout ; wire \z80_|execute_|ctl_bus_db_we~8_combout ; -wire \z80_|execute_|ctl_bus_db_we~2_combout ; wire \z80_|execute_|ctl_bus_db_we~4_combout ; wire \z80_|execute_|ctl_bus_db_we~6_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ; +wire \z80_|execute_|ctl_bus_db_we~3_combout ; +wire \z80_|execute_|ctl_bus_db_we~2_combout ; wire \z80_|execute_|ctl_bus_db_we~7_combout ; -wire \ula_|zx_keyboard_|keys[0][2]~50_combout ; -wire \ula_|zx_keyboard_|keys[0][2]~52_combout ; -wire \ula_|zx_keyboard_|keys[0][2]~q ; -wire \ula_|zx_keyboard_|keys[3][3]~48_combout ; -wire \ula_|zx_keyboard_|keys[1][2]~49_combout ; -wire \ula_|zx_keyboard_|keys[1][2]~q ; -wire \D[2]~35_combout ; -wire \ula_|zx_keyboard_|keys[5][2]~57_combout ; -wire \ula_|zx_keyboard_|keys[5][2]~58_combout ; -wire \ula_|zx_keyboard_|keys[5][2]~q ; -wire \ula_|zx_keyboard_|keys[4][2]~59_combout ; -wire \ula_|zx_keyboard_|keys[4][2]~131_combout ; -wire \ula_|zx_keyboard_|keys[4][2]~60_combout ; -wire \ula_|zx_keyboard_|keys[4][2]~q ; -wire \D[2]~37_combout ; -wire \ula_|zx_keyboard_|keys[3][2]~53_combout ; -wire \ula_|zx_keyboard_|keys[2][2]~55_combout ; -wire \ula_|zx_keyboard_|keys[2][2]~56_combout ; -wire \ula_|zx_keyboard_|keys[2][2]~q ; -wire \ula_|zx_keyboard_|keys[3][2]~54_combout ; -wire \ula_|zx_keyboard_|keys[3][2]~q ; -wire \D[2]~36_combout ; -wire \ula_|zx_keyboard_|keys[6][2]~68_combout ; -wire \ula_|zx_keyboard_|keys[6][2]~69_combout ; -wire \ula_|zx_keyboard_|keys[6][2]~70_combout ; -wire \ula_|zx_keyboard_|keys[6][2]~q ; -wire \ula_|zx_keyboard_|keys[7][2]~61_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~62_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~64_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~65_combout ; -wire \ula_|zx_keyboard_|Selector13~0_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~66_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~q ; -wire \D[2]~38_combout ; -wire \D[2]~39_combout ; -wire \D[2]~104_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ; -wire \D[2]~43_combout ; -wire \D[2]~44_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout ; -wire \D[2]~40_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ; -wire \D[2]~41_combout ; -wire \D[2]~42_combout ; -wire \D[2]~105_combout ; -wire \D[2]~45_combout ; -wire \D[2]~46_combout ; -wire \z80_|bus_control_|db[2]~12_combout ; -wire \z80_|bus_control_|db[2]~13_combout ; -wire \z80_|pla_decode_|Equal3~1_combout ; +wire \ula_|zx_keyboard_|keys[5][0]~66_combout ; +wire \ula_|zx_keyboard_|keys[5][0]~80_combout ; +wire \ula_|zx_keyboard_|keys[5][0]~81_combout ; +wire \ula_|zx_keyboard_|keys[5][0]~82_combout ; +wire \ula_|zx_keyboard_|keys[5][0]~q ; +wire \ula_|zx_keyboard_|keys[4][0]~84_combout ; +wire \ula_|zx_keyboard_|keys[4][0]~83_combout ; +wire \ula_|zx_keyboard_|keys[4][0]~85_combout ; +wire \ula_|zx_keyboard_|keys[4][0]~q ; +wire \D[0]~42_combout ; +wire \ula_|zx_keyboard_|keys[1][0]~78_combout ; +wire \ula_|zx_keyboard_|keys[1][0]~79_combout ; +wire \ula_|zx_keyboard_|keys[1][0]~q ; +wire \ula_|zx_keyboard_|keys[3][0]~76_combout ; +wire \ula_|zx_keyboard_|keys[3][0]~q ; +wire \ula_|zx_keyboard_|keys[2][0]~77_combout ; +wire \ula_|zx_keyboard_|keys[2][0]~q ; +wire \D[0]~40_combout ; +wire \ula_|zx_keyboard_|WideOr0~0_combout ; +wire \ula_|zx_keyboard_|keys~71_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~70_combout ; +wire \ula_|zx_keyboard_|keys[0][0]~72_combout ; +wire \ula_|zx_keyboard_|WideOr4~0_combout ; +wire \ula_|zx_keyboard_|keys~73_combout ; +wire \ula_|zx_keyboard_|keys[0][0]~74_combout ; +wire \ula_|zx_keyboard_|keys[0][0]~q ; +wire \ula_|zx_keyboard_|key_row~2_combout ; +wire \D[0]~41_combout ; +wire \ula_|zx_keyboard_|keys[6][0]~89_combout ; +wire \ula_|zx_keyboard_|keys[6][0]~90_combout ; +wire \ula_|zx_keyboard_|keys[6][0]~91_combout ; +wire \ula_|zx_keyboard_|keys[6][0]~q ; +wire \ula_|zx_keyboard_|keys[7][0]~131_combout ; +wire \ula_|zx_keyboard_|WideOr16~3_combout ; +wire \ula_|zx_keyboard_|keys[7][0]~86_combout ; +wire \ula_|zx_keyboard_|keys[7][0]~87_combout ; +wire \ula_|zx_keyboard_|keys[7][0]~88_combout ; +wire \ula_|zx_keyboard_|keys[7][0]~q ; +wire \D[0]~43_combout ; +wire \D[0]~44_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4_combout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~5_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ; +wire \Selector2~0_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ; +wire \Selector2~1_combout ; +wire \D[0]~83_combout ; +wire \D[0]~45_combout ; +wire \D[0]~46_combout ; +wire \z80_|bus_control_|db[0]~16_combout ; +wire \z80_|bus_control_|db[0]~17_combout ; +wire \z80_|pla_decode_|Equal3~2_combout ; wire \z80_|pla_decode_|Equal43~0_combout ; wire \z80_|interrupts_|test1~2_combout ; wire \z80_|interrupts_|test1~3_combout ; @@ -2326,154 +2284,184 @@ wire \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ; wire \z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout ; wire \z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ; wire \z80_|clk_delay_|hold_clk_iorq~combout ; -wire \z80_|sequencer_|DFFE_T1_ff~q ; -wire \z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ; -wire \z80_|sequencer_|DFFE_T2_ff~q ; -wire \z80_|resets_|x3~combout ; -wire \z80_|resets_|SYNTHESIZED_WIRE_12~q ; -wire \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ; -wire \z80_|sequencer_|DFFE_M1_ff~q ; -wire \z80_|sequencer_|DFFE_M2_ff~0_combout ; -wire \z80_|sequencer_|DFFE_M2_ff~q ; -wire \z80_|execute_|ctl_mWrite~3_combout ; -wire \z80_|execute_|nextM~11_combout ; +wire \z80_|sequencer_|DFFE_T4_ff~q ; +wire \z80_|execute_|ctl_eval_cond~0_combout ; +wire \z80_|execute_|ctl_mRead~27_combout ; +wire \z80_|execute_|ctl_mRead~26_combout ; +wire \z80_|execute_|ctl_mRead~28_combout ; +wire \z80_|execute_|nextM~6_combout ; +wire \z80_|execute_|nextM~7_combout ; wire \z80_|execute_|nextM~8_combout ; wire \z80_|execute_|nextM~9_combout ; wire \z80_|execute_|nextM~10_combout ; wire \z80_|execute_|nextM~12_combout ; wire \z80_|execute_|nextM~15_combout ; -wire \z80_|execute_|nextM~6_combout ; -wire \z80_|execute_|nextM~7_combout ; wire \z80_|execute_|nextM~13_combout ; -wire \z80_|execute_|setM1~39_combout ; +wire \z80_|execute_|setM1~41_combout ; wire \z80_|execute_|nextM~5_combout ; wire \z80_|execute_|nextM~14_combout ; -wire \z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ; -wire \z80_|sequencer_|DFFE_T4_ff~q ; -wire \z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ; -wire \z80_|sequencer_|DFFE_T5_ff~q ; -wire \z80_|sequencer_|SYNTHESIZED_WIRE_17~combout ; -wire \z80_|sequencer_|T6~q ; -wire \z80_|execute_|setM1~13_combout ; -wire \z80_|pla_decode_|Equal77~1_combout ; -wire \z80_|execute_|setM1~12_combout ; -wire \z80_|execute_|setM1~14_combout ; -wire \z80_|execute_|setM1~41_combout ; -wire \z80_|execute_|setM1~42_combout ; -wire \z80_|execute_|setM1~43_combout ; -wire \z80_|execute_|setM1~44_combout ; -wire \z80_|execute_|setM1~50_combout ; -wire \z80_|execute_|setM1~51_combout ; -wire \z80_|execute_|setM1~6_combout ; -wire \z80_|execute_|setM1~7_combout ; -wire \z80_|execute_|setM1~8_combout ; -wire \z80_|execute_|setM1~9_combout ; -wire \z80_|execute_|setM1~10_combout ; -wire \z80_|execute_|setM1~11_combout ; -wire \z80_|execute_|setM1~17_combout ; -wire \z80_|execute_|setM1~31_combout ; -wire \z80_|execute_|setM1~28_combout ; -wire \z80_|execute_|setM1~30_combout ; -wire \z80_|execute_|setM1~32_combout ; -wire \z80_|execute_|setM1~33_combout ; -wire \z80_|execute_|setM1~25_combout ; -wire \z80_|execute_|setM1~26_combout ; -wire \z80_|execute_|setM1~24_combout ; -wire \z80_|execute_|setM1~27_combout ; -wire \z80_|execute_|setM1~22_combout ; -wire \z80_|execute_|setM1~21_combout ; -wire \z80_|execute_|setM1~53_combout ; -wire \z80_|execute_|setM1~23_combout ; -wire \z80_|execute_|setM1~18_combout ; -wire \z80_|execute_|setM1~19_combout ; -wire \z80_|execute_|setM1~20_combout ; -wire \z80_|execute_|setM1~34_combout ; -wire \z80_|execute_|setM1~52_combout ; +wire \z80_|sequencer_|ena_M~combout ; +wire \z80_|sequencer_|DFFE_T1_ff~q ; +wire \z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ; +wire \z80_|sequencer_|DFFE_T2_ff~q ; wire \z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ; wire \z80_|sequencer_|DFFE_T3_ff~q ; wire \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ; -wire \z80_|decode_state_|in_halt~0_combout ; -wire \z80_|decode_state_|in_halt~1_combout ; -wire \z80_|decode_state_|in_halt~q ; +wire \z80_|execute_|ctl_66_oe~2_combout ; +wire \z80_|interrupts_|im1~q ; +wire \z80_|execute_|ctl_bus_ff_oe~0_combout ; +wire \z80_|execute_|ctl_bus_ff_oe~1_combout ; +wire \z80_|execute_|ctl_bus_zero_oe~0_combout ; +wire \z80_|bus_control_|db[0]~4_combout ; +wire \z80_|bus_control_|db[6]~8_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ; +wire \Selector6~0_combout ; +wire \Selector6~1_combout ; +wire \D[6]~88_combout ; +wire \raw_loader_in~input_o ; +wire \D[6]~69_combout ; +wire \D[6]~78_combout ; +wire \D[6]~79_combout ; +wire \z80_|bus_control_|db[6]~9_combout ; +wire \z80_|execute_|ctl_ir_we~10_combout ; +wire \z80_|execute_|ctl_bus_db_oe~0_combout ; +wire \z80_|execute_|ctl_bus_db_oe~4_combout ; wire \z80_|execute_|ctl_bus_db_oe~2_combout ; wire \z80_|execute_|ctl_bus_db_oe~5_combout ; wire \z80_|execute_|ctl_bus_db_oe~6_combout ; -wire \z80_|execute_|ctl_bus_db_oe~4_combout ; wire \z80_|execute_|ctl_bus_db_oe~combout ; wire \z80_|bus_control_|db[0]~6_combout ; -wire \ula_|zx_keyboard_|keys[1][3]~93_combout ; -wire \ula_|zx_keyboard_|keys[1][3]~94_combout ; -wire \ula_|zx_keyboard_|keys[1][3]~q ; -wire \ula_|zx_keyboard_|keys[0][3]~96_combout ; -wire \ula_|zx_keyboard_|keys[0][3]~98_combout ; -wire \ula_|zx_keyboard_|keys[0][3]~q ; -wire \D[3]~65_combout ; -wire \ula_|zx_keyboard_|keys[3][3]~99_combout ; -wire \ula_|zx_keyboard_|keys[3][3]~100_combout ; -wire \ula_|zx_keyboard_|keys[3][3]~q ; -wire \ula_|zx_keyboard_|keys[2][3]~101_combout ; -wire \ula_|zx_keyboard_|keys[2][3]~102_combout ; -wire \ula_|zx_keyboard_|keys[2][3]~133_combout ; -wire \ula_|zx_keyboard_|keys[2][3]~103_combout ; -wire \ula_|zx_keyboard_|keys[2][3]~q ; -wire \D[3]~66_combout ; -wire \ula_|zx_keyboard_|keys[5][3]~104_combout ; -wire \ula_|zx_keyboard_|keys[5][3]~105_combout ; -wire \ula_|zx_keyboard_|keys[5][3]~q ; -wire \ula_|zx_keyboard_|keys[4][3]~106_combout ; -wire \ula_|zx_keyboard_|Selector5~1_combout ; -wire \ula_|zx_keyboard_|Selector5~0_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~134_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~107_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~135_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~108_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~q ; -wire \D[3]~67_combout ; -wire \ula_|zx_keyboard_|keys[7][3]~112_combout ; -wire \ula_|zx_keyboard_|keys[7][3]~113_combout ; -wire \ula_|zx_keyboard_|keys[7][3]~114_combout ; -wire \ula_|zx_keyboard_|keys[7][3]~q ; -wire \ula_|zx_keyboard_|keys[6][3]~109_combout ; -wire \ula_|zx_keyboard_|keys[6][3]~110_combout ; -wire \ula_|zx_keyboard_|keys[6][3]~137_combout ; -wire \ula_|zx_keyboard_|keys[6][3]~138_combout ; -wire \ula_|zx_keyboard_|keys[6][3]~q ; -wire \ula_|zx_keyboard_|key_row~2_combout ; -wire \D[3]~68_combout ; -wire \D[3]~69_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ; -wire \D[3]~73_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ; -wire \D[3]~74_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ; -wire \D[3]~70_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ; -wire \D[3]~71_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ; -wire \D[3]~72_combout ; -wire \D[3]~108_combout ; -wire \D[3]~95_combout ; -wire \D[3]~96_combout ; -wire \z80_|bus_control_|db[3]~20_combout ; -wire \z80_|bus_control_|db[3]~21_combout ; -wire \z80_|execute_|ctl_mWrite~4_combout ; -wire \z80_|execute_|ctl_apin_mux~2_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~61_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~63_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~64_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~65_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~q ; +wire \ula_|zx_keyboard_|keys[6][2]~67_combout ; +wire \ula_|zx_keyboard_|keys[6][2]~68_combout ; +wire \ula_|zx_keyboard_|keys[6][2]~69_combout ; +wire \ula_|zx_keyboard_|keys[6][2]~q ; +wire \D[2]~36_combout ; +wire \ula_|zx_keyboard_|keys[4][2]~58_combout ; +wire \ula_|zx_keyboard_|keys[4][2]~130_combout ; +wire \ula_|zx_keyboard_|keys[4][2]~59_combout ; +wire \ula_|zx_keyboard_|keys[4][2]~q ; +wire \ula_|zx_keyboard_|keys[5][2]~56_combout ; +wire \ula_|zx_keyboard_|keys[5][2]~57_combout ; +wire \ula_|zx_keyboard_|keys[5][2]~q ; +wire \D[2]~35_combout ; +wire \ula_|zx_keyboard_|keys[0][2]~54_combout ; +wire \ula_|zx_keyboard_|keys[0][2]~55_combout ; +wire \ula_|zx_keyboard_|keys[0][2]~q ; +wire \ula_|zx_keyboard_|keys[3][2]~50_combout ; +wire \ula_|zx_keyboard_|keys[3][2]~51_combout ; +wire \ula_|zx_keyboard_|keys[3][2]~q ; +wire \ula_|zx_keyboard_|keys[2][2]~52_combout ; +wire \ula_|zx_keyboard_|keys[2][2]~53_combout ; +wire \ula_|zx_keyboard_|keys[2][2]~q ; +wire \D[2]~33_combout ; +wire \ula_|zx_keyboard_|keys[1][2]~47_combout ; +wire \ula_|zx_keyboard_|keys[1][2]~48_combout ; +wire \ula_|zx_keyboard_|keys[1][2]~q ; +wire \ula_|zx_keyboard_|key_row~1_combout ; +wire \D[2]~34_combout ; +wire \D[2]~37_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~3_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ; +wire \Selector0~0_combout ; +wire \Selector0~1_combout ; +wire \D[2]~82_combout ; +wire \D[2]~38_combout ; +wire \D[2]~39_combout ; +wire \z80_|bus_control_|db[2]~12_combout ; +wire \z80_|bus_control_|db[2]~13_combout ; +wire \z80_|pla_decode_|Equal1~4_combout ; +wire \z80_|execute_|ctl_alu_op_low~26_combout ; +wire \z80_|execute_|ctl_alu_op_low~45_combout ; +wire \z80_|execute_|setM1~17_combout ; +wire \z80_|execute_|setM1~18_combout ; +wire \z80_|execute_|setM1~11_combout ; +wire \z80_|execute_|setM1~10_combout ; +wire \z80_|execute_|setM1~12_combout ; +wire \z80_|execute_|setM1~8_combout ; +wire \z80_|execute_|setM1~9_combout ; +wire \z80_|execute_|setM1~13_combout ; +wire \z80_|execute_|setM1~15_combout ; +wire \z80_|execute_|setM1~14_combout ; +wire \z80_|execute_|setM1~16_combout ; +wire \z80_|execute_|setM1~19_combout ; +wire \z80_|execute_|setM1~23_combout ; +wire \z80_|execute_|setM1~22_combout ; +wire \z80_|execute_|setM1~56_combout ; +wire \z80_|execute_|setM1~24_combout ; +wire \z80_|execute_|setM1~25_combout ; +wire \z80_|execute_|setM1~26_combout ; +wire \z80_|execute_|setM1~27_combout ; +wire \z80_|execute_|setM1~28_combout ; +wire \z80_|execute_|setM1~55_combout ; +wire \z80_|execute_|setM1~29_combout ; +wire \z80_|execute_|setM1~31_combout ; +wire \z80_|execute_|setM1~33_combout ; +wire \z80_|execute_|setM1~32_combout ; +wire \z80_|execute_|setM1~34_combout ; +wire \z80_|execute_|setM1~20_combout ; +wire \z80_|execute_|setM1~21_combout ; +wire \z80_|execute_|setM1~35_combout ; +wire \z80_|execute_|setM1~43_combout ; +wire \z80_|execute_|setM1~44_combout ; +wire \z80_|execute_|setM1~45_combout ; +wire \z80_|execute_|setM1~46_combout ; +wire \z80_|execute_|setM1~52_combout ; +wire \z80_|sequencer_|SYNTHESIZED_WIRE_17~combout ; +wire \z80_|sequencer_|T6~q ; +wire \z80_|execute_|setM1~53_combout ; +wire \z80_|execute_|setM1~54_combout ; +wire \z80_|sequencer_|DFFE_M1_ff~0_combout ; +wire \z80_|sequencer_|DFFE_M1_ff~q ; +wire \z80_|resets_|x1~0_combout ; +wire \z80_|fpga_reset~feeder_combout ; +wire \z80_|fpga_reset~q ; +wire \z80_|fpga_reset~clkctrl_outclk ; +wire \z80_|resets_|x1~q ; +wire \z80_|resets_|x3~combout ; +wire \z80_|resets_|SYNTHESIZED_WIRE_12~q ; +wire \z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ; +wire \z80_|resets_|SYNTHESIZED_WIRE_10~q ; +wire \z80_|resets_|SYNTHESIZED_WIRE_9~feeder_combout ; +wire \z80_|resets_|SYNTHESIZED_WIRE_9~q ; +wire \z80_|resets_|DFFE_intr_ff3~q ; +wire \z80_|resets_|clrpc_int~0_combout ; +wire \z80_|resets_|clrpc_int~q ; +wire \z80_|resets_|clrpc~0_combout ; wire \z80_|address_pins_|DFFE_apin_latch[0]~0_combout ; -wire \D[0]~59_combout ; -wire \D[0]~60_combout ; -wire \D[1]~61_combout ; -wire \D[1]~62_combout ; -wire \D[2]~63_combout ; -wire \D[2]~64_combout ; -wire \D[3]~75_combout ; -wire \D[3]~76_combout ; -wire \D[4]~82_combout ; -wire \D[4]~83_combout ; -wire \D[6]~92_combout ; -wire \D[6]~93_combout ; +wire \D[0]~47_combout ; +wire \D[0]~48_combout ; +wire \D[1]~49_combout ; +wire \D[1]~50_combout ; +wire \D[2]~51_combout ; +wire \D[2]~52_combout ; +wire \D[3]~58_combout ; +wire \D[3]~59_combout ; +wire \D[4]~65_combout ; +wire \D[4]~66_combout ; +wire \D[6]~70_combout ; +wire \D[6]~71_combout ; wire \z80_|nM1_int~3_combout ; wire \z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q ; wire \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder_combout ; @@ -2489,33 +2477,43 @@ wire \ula_|i2c_loader_|divider[1]~6 ; wire \ula_|i2c_loader_|divider[2]~7_combout ; wire \ula_|i2c_loader_|divider[2]~8 ; wire \ula_|i2c_loader_|divider[3]~9_combout ; +wire \ula_|i2c_loader_|WideAnd0~0_combout ; wire \ula_|i2c_loader_|divider[3]~10 ; wire \ula_|i2c_loader_|divider[4]~11_combout ; wire \ula_|i2c_loader_|divider[4]~12 ; wire \ula_|i2c_loader_|divider[5]~13_combout ; -wire \ula_|i2c_loader_|WideAnd0~0_combout ; wire \ula_|i2c_loader_|WideAnd0~combout ; wire \ula_|i2c_loader_|state.Idle~q ; wire \ula_|i2c_loader_|phase~0_combout ; wire \ula_|i2c_loader_|phase~1_combout ; wire \ula_|i2c_loader_|nbit~5_combout ; -wire \ula_|i2c_loader_|thisbyte[0]~8_combout ; +wire \ula_|i2c_loader_|state.Idle~0_combout ; wire \ula_|i2c_loader_|Mux42~0_combout ; +wire \ula_|i2c_loader_|nbit~6_combout ; +wire \ula_|i2c_loader_|state.Done~0_combout ; +wire \ula_|i2c_loader_|state.Ack~0_combout ; +wire \ula_|i2c_loader_|state.Ack~1_combout ; +wire \ula_|i2c_loader_|state.Ack~q ; +wire \ula_|i2c_loader_|nbit[0]~2_combout ; wire \ula_|i2c_loader_|nbyte~4_combout ; wire \ula_|i2c_loader_|thisbyte[0]~7_combout ; wire \I2C_SDAT~input_o ; wire \ula_|i2c_loader_|nbyte[0]~1_combout ; wire \ula_|i2c_loader_|nbyte[0]~2_combout ; wire \ula_|i2c_loader_|nbyte[0]~3_combout ; -wire \ula_|i2c_loader_|state.Stop~0_combout ; -wire \ula_|i2c_loader_|state.Stop~1_combout ; -wire \ula_|i2c_loader_|state.Stop~q ; -wire \ula_|i2c_loader_|state.Idle~0_combout ; +wire \ula_|i2c_loader_|nbit[0]~1_combout ; +wire \ula_|i2c_loader_|nbit[0]~3_combout ; +wire \ula_|i2c_loader_|nbit[0]~4_combout ; wire \ula_|i2c_loader_|nbit~0_combout ; -wire \ula_|i2c_loader_|state.Done~0_combout ; -wire \ula_|i2c_loader_|state.Ack~0_combout ; -wire \ula_|i2c_loader_|state.Ack~1_combout ; -wire \ula_|i2c_loader_|state.Ack~q ; +wire \ula_|i2c_loader_|state.Done~1_combout ; +wire \ula_|i2c_loader_|state~27_combout ; +wire \ula_|i2c_loader_|state~24_combout ; +wire \ula_|i2c_loader_|state~26_combout ; +wire \ula_|i2c_loader_|state.Data~0_combout ; +wire \ula_|i2c_loader_|state.Data~q ; +wire \ula_|i2c_loader_|state.Done~2_combout ; +wire \ula_|i2c_loader_|state.Pause~1_combout ; +wire \ula_|i2c_loader_|thisbyte[0]~8_combout ; wire \ula_|i2c_loader_|nbyte[1]~5_combout ; wire \ula_|i2c_loader_|thisbyte[0]~18_combout ; wire \ula_|i2c_loader_|thisbyte[0]~9 ; @@ -2525,28 +2523,18 @@ wire \ula_|i2c_loader_|thisbyte[2]~12_combout ; wire \ula_|i2c_loader_|thisbyte[2]~13 ; wire \ula_|i2c_loader_|thisbyte[3]~14_combout ; wire \ula_|i2c_loader_|Equal2~0_combout ; -wire \ula_|i2c_loader_|state.Pause~0_combout ; wire \ula_|i2c_loader_|thisbyte[3]~15 ; wire \ula_|i2c_loader_|thisbyte[4]~16_combout ; -wire \ula_|i2c_loader_|state.Pause~1_combout ; -wire \ula_|i2c_loader_|state.Done~2_combout ; +wire \ula_|i2c_loader_|Equal2~1_combout ; +wire \ula_|i2c_loader_|state.Pause~0_combout ; wire \ula_|i2c_loader_|state.Pause~2_combout ; -wire \ula_|i2c_loader_|state.Pause~3_combout ; wire \ula_|i2c_loader_|state.Pause~q ; wire \ula_|i2c_loader_|state~25_combout ; wire \ula_|i2c_loader_|state.Start~q ; wire \ula_|i2c_loader_|nbyte~0_combout ; -wire \ula_|i2c_loader_|nbit[0]~1_combout ; -wire \ula_|i2c_loader_|nbit[0]~2_combout ; -wire \ula_|i2c_loader_|nbit[0]~3_combout ; -wire \ula_|i2c_loader_|nbit[0]~4_combout ; -wire \ula_|i2c_loader_|nbit~6_combout ; -wire \ula_|i2c_loader_|state.Done~1_combout ; -wire \ula_|i2c_loader_|state~27_combout ; -wire \ula_|i2c_loader_|state~24_combout ; -wire \ula_|i2c_loader_|state~26_combout ; -wire \ula_|i2c_loader_|state.Data~0_combout ; -wire \ula_|i2c_loader_|state.Data~q ; +wire \ula_|i2c_loader_|state.Stop~0_combout ; +wire \ula_|i2c_loader_|state.Stop~1_combout ; +wire \ula_|i2c_loader_|state.Stop~q ; wire \ula_|i2c_loader_|scl_out~0_combout ; wire \ula_|i2c_loader_|scl_out~_Duplicate_1_q ; wire \ula_|i2c_loader_|scl_out~1_combout ; @@ -2556,26 +2544,25 @@ wire \ula_|i2c_loader_|sda_out~_Duplicate_1_q ; wire \ula_|i2c_loader_|shiftreg~4_combout ; wire \ula_|i2c_loader_|Mux35~0_combout ; wire \ula_|i2c_loader_|shiftreg~13_combout ; -wire \ula_|i2c_loader_|shiftreg~14_combout ; wire \ula_|i2c_loader_|shiftreg~15_combout ; -wire \ula_|i2c_loader_|shiftreg[0]~24_combout ; -wire \ula_|i2c_loader_|shiftreg[0]~6_combout ; -wire \ula_|i2c_loader_|shiftreg[0]~7_combout ; -wire \ula_|i2c_loader_|shiftreg[0]~8_combout ; -wire \ula_|i2c_loader_|shiftreg~21_combout ; -wire \ula_|i2c_loader_|shiftreg~22_combout ; -wire \ula_|i2c_loader_|shiftreg~23_combout ; -wire \ula_|i2c_loader_|shiftreg[6]~10_combout ; -wire \ula_|i2c_loader_|shiftreg[6]~11_combout ; -wire \ula_|i2c_loader_|shiftreg~18_combout ; -wire \ula_|i2c_loader_|shiftreg~19_combout ; -wire \ula_|i2c_loader_|shiftreg~20_combout ; wire \ula_|i2c_loader_|shiftreg~16_combout ; wire \ula_|i2c_loader_|shiftreg~17_combout ; -wire \ula_|i2c_loader_|shiftreg~26_combout ; +wire \ula_|i2c_loader_|shiftreg~18_combout ; +wire \ula_|i2c_loader_|shiftreg~20_combout ; +wire \ula_|i2c_loader_|shiftreg~21_combout ; +wire \ula_|i2c_loader_|shiftreg[0]~23_combout ; +wire \ula_|i2c_loader_|shiftreg[0]~6_combout ; +wire \ula_|i2c_loader_|shiftreg[0]~7_combout ; +wire \ula_|i2c_loader_|shiftreg~22_combout ; +wire \ula_|i2c_loader_|shiftreg[6]~9_combout ; +wire \ula_|i2c_loader_|shiftreg[6]~10_combout ; +wire \ula_|i2c_loader_|shiftreg~19_combout ; wire \ula_|i2c_loader_|shiftreg~25_combout ; wire \ula_|i2c_loader_|shiftreg~12_combout ; -wire \ula_|i2c_loader_|shiftreg~9_combout ; +wire \ula_|i2c_loader_|shiftreg~14_combout ; +wire \ula_|i2c_loader_|shiftreg~24_combout ; +wire \ula_|i2c_loader_|shiftreg~11_combout ; +wire \ula_|i2c_loader_|shiftreg~8_combout ; wire \ula_|i2c_loader_|shiftreg[7]~5_combout ; wire \ula_|i2c_loader_|sda_out~0_combout ; wire \ula_|i2c_loader_|sda_out~1_combout ; @@ -2616,12 +2603,12 @@ wire \ula_|i2s_intf_|Add0~18_combout ; wire \ula_|i2s_intf_|lrdivider[9]~3_combout ; wire \ula_|i2s_intf_|Equal0~0_combout ; wire \ula_|i2s_intf_|Equal0~2_combout ; -wire \ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder_combout ; wire \ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ; wire \ula_|i2s_intf_|lrclk_r~0_combout ; wire \ula_|i2s_intf_|lrclk_r~q ; wire \ula_|i2s_intf_|lrclk_r~_Duplicate_1_q ; wire \ula_|i2s_intf_|bitcount[0]~5_combout ; +wire \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder_combout ; wire \ula_|i2s_intf_|bclk_r~_Duplicate_1_q ; wire \ula_|i2s_intf_|bitcount[4]~15_combout ; wire \ula_|i2s_intf_|bitcount[0]~6 ; @@ -2630,9 +2617,11 @@ wire \ula_|i2s_intf_|bitcount[1]~8 ; wire \ula_|i2s_intf_|bitcount[2]~9_combout ; wire \ula_|i2s_intf_|bitcount[2]~10 ; wire \ula_|i2s_intf_|bitcount[3]~11_combout ; -wire \ula_|i2s_intf_|LessThan0~0_combout ; wire \ula_|i2s_intf_|bitcount[3]~12 ; wire \ula_|i2s_intf_|bitcount[4]~13_combout ; +wire \ula_|i2s_intf_|LessThan0~0_combout ; +wire \ula_|i2s_intf_|shiftreg[4]~1_combout ; +wire \ula_|i2s_intf_|Add2~18_combout ; wire \ula_|i2s_intf_|Add2~7_cout ; wire \ula_|i2s_intf_|Add2~8_combout ; wire \ula_|i2s_intf_|Add2~20_combout ; @@ -2646,13 +2635,10 @@ wire \ula_|i2s_intf_|Add2~13 ; wire \ula_|i2s_intf_|Add2~14_combout ; wire \ula_|i2s_intf_|Add2~16_combout ; wire \ula_|i2s_intf_|Equal1~0_combout ; -wire \ula_|i2s_intf_|shiftreg[4]~1_combout ; -wire \ula_|i2s_intf_|Add2~18_combout ; wire \ula_|i2s_intf_|Equal1~1_combout ; wire \ula_|i2s_intf_|bclk_r~0_combout ; wire \ula_|i2s_intf_|bclk_r~1_combout ; wire \ula_|i2s_intf_|bclk_r~q ; -wire \ula_|pcm_outl[13]~feeder_combout ; wire \ula_|always0~2_combout ; wire \ula_|always0~3_combout ; wire \ula_|i2s_intf_|shiftreg[0]~19_combout ; @@ -2671,33 +2657,30 @@ wire \ula_|i2s_intf_|shiftreg~10_combout ; wire \ula_|i2s_intf_|shiftreg~9_combout ; wire \ula_|i2s_intf_|shiftreg~8_combout ; wire \ula_|i2s_intf_|shiftreg~7_combout ; -wire \ula_|i2s_intf_|PCM_INR[14]~0_combout ; wire \ula_|i2s_intf_|PCM_INL[14]~0_combout ; +wire \ula_|i2s_intf_|PCM_INR[14]~0_combout ; wire \ula_|pcm_outr~0_combout ; wire \ula_|i2s_intf_|shiftreg~6_combout ; wire \ula_|i2s_intf_|shiftreg~5_combout ; wire \ula_|i2s_intf_|shiftreg~4_combout ; wire \ula_|i2s_intf_|shiftreg~3_combout ; wire \ula_|i2s_intf_|shiftreg~0_combout ; -wire \ula_|video_|LessThan2~0_combout ; +wire \ula_|border[1]~feeder_combout ; +wire \ula_|video_|LessThan4~0_combout ; +wire \ula_|video_|screen_en~0_combout ; wire \ula_|video_|LessThan6~0_combout ; +wire \ula_|video_|LessThan6~1_combout ; +wire \ula_|video_|screen_en~1_combout ; +wire \ula_|video_|LessThan2~0_combout ; wire \ula_|video_|LessThan2~1_combout ; wire \ula_|video_|LessThan3~0_combout ; wire \ula_|video_|LessThan0~0_combout ; wire \ula_|video_|disp_enable~0_combout ; wire \ula_|video_|disp_enable~1_combout ; -wire \ula_|video_|LessThan6~1_combout ; -wire \ula_|video_|LessThan4~0_combout ; -wire \ula_|video_|screen_en~0_combout ; -wire \ula_|video_|screen_en~1_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 ; -wire \ula_|video_|attr_prefetch[1]~feeder_combout ; -wire \ula_|video_|Decoder0~1_combout ; -wire \ula_|video_|Decoder0~0_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 ; -wire \ula_|video_|attr_prefetch[4]~feeder_combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 ; wire \ula_|video_|attr_prefetch[7]~feeder_combout ; +wire \ula_|video_|Decoder0~1_combout ; +wire \ula_|video_|Decoder0~0_combout ; wire \ula_|video_|frame[0]~12_combout ; wire \ula_|video_|frame[1]~4_combout ; wire \ula_|video_|frame[1]~5 ; @@ -2706,11 +2689,12 @@ wire \ula_|video_|frame[2]~7 ; wire \ula_|video_|frame[3]~8_combout ; wire \ula_|video_|frame[3]~9 ; wire \ula_|video_|frame[4]~10_combout ; +wire \ula_|video_|frame[4]~feeder_combout ; wire \ula_|video_|inverted~combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 ; wire \ula_|video_|bits_prefetch[6]~feeder_combout ; wire \ula_|video_|Decoder0~2_combout ; -wire \ula_|video_|bits[6]~feeder_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 ; wire \ula_|video_|bits_prefetch[4]~feeder_combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 ; wire \ula_|video_|bits_prefetch[5]~feeder_combout ; @@ -2723,6 +2707,7 @@ wire \ula_|video_|bits_prefetch[2]~feeder_combout ; wire \ula_|video_|bits[2]~feeder_combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 ; wire \ula_|video_|bits_prefetch[0]~feeder_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 ; wire \ula_|video_|bits_prefetch[1]~feeder_combout ; wire \ula_|video_|bits[1]~feeder_combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 ; @@ -2730,13 +2715,15 @@ wire \ula_|video_|bits_prefetch[3]~feeder_combout ; wire \ula_|video_|Mux0~2_combout ; wire \ula_|video_|Mux0~3_combout ; wire \ula_|video_|cindex[1]~0_combout ; +wire \ula_|video_|attr_prefetch[4]~feeder_combout ; +wire \ula_|video_|attr_prefetch[1]~feeder_combout ; wire \ula_|video_|cindex[1]~1_combout ; wire \ula_|video_|VGA_R[0]~0_combout ; wire \ula_|video_|attr_prefetch[6]~feeder_combout ; wire \ula_|video_|VGA_B[1]~0_combout ; wire \ula_|video_|VGA_R[1]~1_combout ; -wire \ula_|video_|attr_prefetch[2]~feeder_combout ; wire \ula_|video_|attr_prefetch[5]~feeder_combout ; +wire \ula_|video_|attr_prefetch[2]~feeder_combout ; wire \ula_|video_|cindex[2]~2_combout ; wire \ula_|video_|VGA_G[0]~0_combout ; wire \ula_|video_|VGA_G[1]~1_combout ; @@ -2761,42 +2748,24 @@ wire \z80_|memory_ifc_|nM1_out~combout ; wire \ula_|beep~0_combout ; wire \ula_|beep~q ; wire [0:0] \ram0|altsyncram_component|auto_generated|address_reg_a ; -wire [1:0] \ram1|altsyncram_component|auto_generated|address_reg_a ; wire [2:0] \ram1|altsyncram_component|auto_generated|decode3|w_anode244w ; -wire [2:0] \ram1|altsyncram_component|auto_generated|decode3|w_anode223w ; wire [2:0] \ula_|border ; wire [0:0] \ula_|clocks_|counter ; -wire [7:0] \ula_|i2c_loader_|shiftreg ; wire [1:0] \ula_|i2c_loader_|nbyte ; -wire [5:0] \ula_|i2c_loader_|divider ; -wire [17:0] \ula_|i2s_intf_|shiftreg ; wire [4:0] \ula_|i2s_intf_|bitcount ; -wire [15:0] \ula_|i2s_intf_|PCM_INR ; -wire [9:0] \ula_|video_|vga_vc ; wire [4:0] \ula_|video_|frame ; -wire [7:0] \ula_|video_|bits_prefetch ; wire [7:0] \ula_|video_|attr_prefetch ; -wire [7:0] \ula_|ps2_keyboard_|clk_filter ; -wire [7:0] \z80_|reg_file_|b2v_latch_af_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_bc2_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_bc_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_de2_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_de_lo|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_af_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_bc2_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_de2_hi|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_hl2_lo|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_hl_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_ir_lo|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_ix_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_iy_lo|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_pc_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_sp_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_wz_lo|latch ; -wire [3:0] \z80_|alu_|op2_low ; wire [3:0] \z80_|alu_|op1_low ; -wire [15:0] \z80_|address_latch_|Q ; -wire [15:0] \z80_|address_latch_|b2v_inst_inc_dec|address ; -wire [15:0] \z80_|address_pins_|DFFE_apin_latch ; -wire [7:0] \z80_|data_pins_|dout ; -wire [7:0] \z80_|ir_|opcode ; +wire [7:0] \z80_|reg_file_|b2v_latch_af2_hi|latch ; +wire [15:0] \z80_|address_latch_|abusz ; +wire [7:0] \z80_|data_pins_|SYNTHESIZED_WIRE_0 ; wire [0:0] \ram0|altsyncram_component|auto_generated|out_address_reg_a ; wire [1:0] \ram1|altsyncram_component|auto_generated|out_address_reg_a ; wire [2:0] \ram1|altsyncram_component|auto_generated|decode3|w_anode252w ; @@ -2815,13 +2784,11 @@ wire [7:0] \ula_|video_|bits ; wire [7:0] \ula_|video_|attr ; wire [8:0] \ula_|ps2_keyboard_|shiftreg ; wire [3:0] \ula_|ps2_keyboard_|bit_count ; -wire [7:0] \z80_|reg_file_|b2v_latch_af2_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_af_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_bc2_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_bc_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_de2_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_de_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_hl2_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_af_lo|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_bc2_lo|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_bc_lo|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_de2_lo|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_de_lo|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_hl_hi|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_ir_hi|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_ix_hi|latch ; @@ -2829,53 +2796,73 @@ wire [7:0] \z80_|reg_file_|b2v_latch_iy_hi|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_pc_hi|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_sp_hi|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_wz_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_wz_lo|latch ; wire [3:0] \z80_|alu_|result_lo ; wire [3:0] \z80_|alu_|op2_high ; wire [3:0] \z80_|alu_|op1_high ; wire [3:0] \z80_|alu_|b2v_op1_latch_mux_high|Q ; -wire [7:0] \z80_|reg_file_|b2v_latch_af2_hi|latch ; -wire [15:0] \z80_|address_latch_|abusz ; -wire [7:0] \z80_|data_pins_|SYNTHESIZED_WIRE_0 ; +wire [15:0] \z80_|address_latch_|Q ; +wire [15:0] \z80_|address_latch_|b2v_inst_inc_dec|address ; +wire [15:0] \z80_|address_pins_|DFFE_apin_latch ; +wire [7:0] \z80_|data_pins_|dout ; +wire [7:0] \z80_|ir_|opcode ; +wire [1:0] \ram1|altsyncram_component|auto_generated|address_reg_a ; +wire [2:0] \ram1|altsyncram_component|auto_generated|decode3|w_anode223w ; +wire [7:0] \ula_|i2c_loader_|shiftreg ; +wire [5:0] \ula_|i2c_loader_|divider ; +wire [17:0] \ula_|i2s_intf_|shiftreg ; +wire [15:0] \ula_|i2s_intf_|PCM_INR ; +wire [9:0] \ula_|video_|vga_vc ; +wire [7:0] \ula_|video_|bits_prefetch ; +wire [7:0] \ula_|ps2_keyboard_|clk_filter ; +wire [7:0] \z80_|reg_file_|b2v_latch_af2_lo|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_bc_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_de_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_hl2_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_ir_lo|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_iy_lo|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_sp_lo|latch ; +wire [3:0] \z80_|alu_|op2_low ; wire [4:0] \ula_|pll_|altpll_component|auto_generated|pll1_CLK_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a25_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ; -wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ; -wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; -wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; -wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; -wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a28_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ; @@ -2883,33 +2870,33 @@ wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_b wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a4_PORTBDATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ; -wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ; -wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a5_PORTBDATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a5_PORTBDATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ; -wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a31_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ; -wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ; -wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus ; assign \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk [0] = \ula_|pll_|altpll_component|auto_generated|pll1_CLK_bus [0]; assign \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk [1] = \ula_|pll_|altpll_component|auto_generated|pll1_CLK_bus [1]; @@ -2917,82 +2904,82 @@ assign \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk [2] = \ula_|pll_ assign \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk [3] = \ula_|pll_|altpll_component|auto_generated|pll1_CLK_bus [3]; assign \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk [4] = \ula_|pll_|altpll_component|auto_generated|pll1_CLK_bus [4]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus [0]; - assign \ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus [0]; + assign \ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0]; assign \ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a25_PORTADATAOUT_bus [0]; assign \rom|altsyncram_component|auto_generated|ram_block1a9~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a1~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [0]; + assign \ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a1~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus [0]; -assign \ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a10~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a10~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus [0]; -assign \ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a8~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus [0]; +assign \ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a8~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; -assign \ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus [0]; +assign \ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; - -assign \ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus [0]; - -assign \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus [0]; assign \ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus [0]; - assign \ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus [0]; assign \ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a28_PORTADATAOUT_bus [0]; @@ -3007,60 +2994,60 @@ assign \rom|altsyncram_component|auto_generated|ram_block1a4~portadataout = \ro assign \ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus [0]; - assign \ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus [0]; + assign \ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus [0]; assign \ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus [0]; assign \rom|altsyncram_component|auto_generated|ram_block1a13~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a5~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus [0]; + assign \ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a5_PORTBDATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a5~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus [0]; -assign \ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a14~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a6~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a14~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus [0]; - -assign \ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus [0]; - -assign \rom|altsyncram_component|auto_generated|ram_block1a6~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus [0]; assign \ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus [0]; - assign \ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus [0]; assign \ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a31_PORTADATAOUT_bus [0]; assign \rom|altsyncram_component|auto_generated|ram_block1a15~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus [0]; -assign \ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus [0]; - -assign \ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus [0]; - assign \rom|altsyncram_component|auto_generated|ram_block1a7~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus [0]; +assign \ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus [0]; + // Location: IOOBUF_X53_Y21_N23 cycloneive_io_obuf \GPIO_1[0]~output ( .i(\z80_|address_pins_|DFFE_apin_latch [0]), @@ -3271,8 +3258,8 @@ defparam \GPIO_1[15]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y11_N9 cycloneive_io_obuf \GPIO_1[16]~output ( - .i(\D[0]~60_combout ), - .oe(\D[0]~107_combout ), + .i(\D[0]~48_combout ), + .oe(\D[0]~84_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[16]), @@ -3284,8 +3271,8 @@ defparam \GPIO_1[16]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y12_N2 cycloneive_io_obuf \GPIO_1[17]~output ( - .i(\D[1]~62_combout ), - .oe(\D[0]~107_combout ), + .i(\D[1]~50_combout ), + .oe(\D[0]~84_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[17]), @@ -3297,8 +3284,8 @@ defparam \GPIO_1[17]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y8_N23 cycloneive_io_obuf \GPIO_1[18]~output ( - .i(\D[2]~64_combout ), - .oe(\D[0]~107_combout ), + .i(\D[2]~52_combout ), + .oe(\D[0]~84_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[18]), @@ -3310,8 +3297,8 @@ defparam \GPIO_1[18]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y11_N2 cycloneive_io_obuf \GPIO_1[19]~output ( - .i(\D[3]~76_combout ), - .oe(\D[0]~107_combout ), + .i(\D[3]~59_combout ), + .oe(\D[0]~84_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[19]), @@ -3323,8 +3310,8 @@ defparam \GPIO_1[19]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y6_N16 cycloneive_io_obuf \GPIO_1[20]~output ( - .i(\D[4]~83_combout ), - .oe(\D[0]~107_combout ), + .i(\D[4]~66_combout ), + .oe(\D[0]~84_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[20]), @@ -3336,8 +3323,8 @@ defparam \GPIO_1[20]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y7_N9 cycloneive_io_obuf \GPIO_1[21]~output ( - .i(\D[5]~85_combout ), - .oe(\D[0]~107_combout ), + .i(\D[5]~68_combout ), + .oe(\D[0]~84_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[21]), @@ -3349,8 +3336,8 @@ defparam \GPIO_1[21]~output .open_drain_output = "false"; // Location: IOOBUF_X49_Y0_N2 cycloneive_io_obuf \GPIO_1[22]~output ( - .i(\D[6]~93_combout ), - .oe(\D[0]~107_combout ), + .i(\D[6]~71_combout ), + .oe(\D[0]~84_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[22]), @@ -3362,8 +3349,8 @@ defparam \GPIO_1[22]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y9_N23 cycloneive_io_obuf \GPIO_1[23]~output ( - .i(\D[7]~94_combout ), - .oe(\D[0]~107_combout ), + .i(\D[7]~72_combout ), + .oe(\D[0]~84_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[23]), @@ -4024,7 +4011,7 @@ defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl .cl defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: LCCOMB_X25_Y33_N4 +// Location: LCCOMB_X25_Y33_N0 cycloneive_lcell_comb \ula_|clocks_|counter[0]~0 ( // Equation(s): // \ula_|clocks_|counter[0]~0_combout = !\ula_|clocks_|counter [0] @@ -4041,7 +4028,7 @@ defparam \ula_|clocks_|counter[0]~0 .lut_mask = 16'h0F0F; defparam \ula_|clocks_|counter[0]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X25_Y33_N5 +// Location: FF_X25_Y33_N1 dffeas \ula_|clocks_|counter[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), .d(\ula_|clocks_|counter[0]~0_combout ), @@ -4070,7 +4057,7 @@ defparam \SW[2]~input .bus_hold = "false"; defparam \SW[2]~input .simulate_z_as = "z"; // synopsys translate_on -// Location: LCCOMB_X25_Y33_N10 +// Location: LCCOMB_X25_Y33_N4 cycloneive_lcell_comb \ula_|clocks_|clk_cpu~0 ( // Equation(s): // \ula_|clocks_|clk_cpu~0_combout = \ula_|clocks_|clk_cpu~q $ (((\SW[2]~input_o ) # (!\ula_|clocks_|counter [0]))) @@ -4087,7 +4074,7 @@ defparam \ula_|clocks_|clk_cpu~0 .lut_mask = 16'h0FC3; defparam \ula_|clocks_|clk_cpu~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X25_Y33_N11 +// Location: FF_X25_Y33_N5 dffeas \ula_|clocks_|clk_cpu ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), .d(\ula_|clocks_|clk_cpu~0_combout ), @@ -4106,7 +4093,7 @@ defparam \ula_|clocks_|clk_cpu .is_wysiwyg = "true"; defparam \ula_|clocks_|clk_cpu .power_up = "low"; // synopsys translate_on -// Location: CLKCTRL_G14 +// Location: CLKCTRL_G12 cycloneive_clkctrl \ula_|clocks_|clk_cpu~clkctrl ( .ena(vcc), .inclk({vcc,vcc,vcc,\ula_|clocks_|clk_cpu~q }), @@ -4119,38 +4106,34 @@ defparam \ula_|clocks_|clk_cpu~clkctrl .clock_type = "global clock"; defparam \ula_|clocks_|clk_cpu~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: LCCOMB_X32_Y17_N20 -cycloneive_lcell_comb \z80_|sequencer_|DFFE_M1_ff~0 ( +// Location: LCCOMB_X26_Y13_N30 +cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_15 ( // Equation(s): -// \z80_|sequencer_|DFFE_M1_ff~0_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # (\z80_|execute_|nextM~14_combout ))) - - .dataa(\z80_|execute_|setM1~52_combout ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|DFFE_M1_ff~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_M1_ff~0 .lut_mask = 16'hAAA0; -defparam \z80_|sequencer_|DFFE_M1_ff~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N12 -cycloneive_lcell_comb \z80_|sequencer_|ena_M ( -// Equation(s): -// \z80_|sequencer_|ena_M~combout = (\z80_|execute_|setM1~52_combout & !\z80_|execute_|nextM~14_combout ) +// \z80_|sequencer_|SYNTHESIZED_WIRE_15~combout = (\z80_|execute_|setM1~54_combout & (\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|execute_|nextM~14_combout )) .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|setM1~52_combout ), + .datab(\z80_|execute_|setM1~54_combout ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), .datad(\z80_|execute_|nextM~14_combout ), .cin(gnd), - .combout(\z80_|sequencer_|ena_M~combout ), + .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ), .cout()); // synopsys translate_off -defparam \z80_|sequencer_|ena_M .lut_mask = 16'h00F0; -defparam \z80_|sequencer_|ena_M .sum_lutc_input = "datac"; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_15 .lut_mask = 16'h00C0; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: CLKCTRL_G9 +cycloneive_clkctrl \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\z80_|resets_|SYNTHESIZED_WIRE_12~q }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk )); +// synopsys translate_off +defparam \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl .clock_type = "global clock"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl .ena_register_mode = "none"; // synopsys translate_on // Location: IOIBUF_X0_Y16_N8 @@ -4163,7 +4146,7 @@ defparam \KEY[1]~input .bus_hold = "false"; defparam \KEY[1]~input .simulate_z_as = "z"; // synopsys translate_on -// Location: LCCOMB_X24_Y15_N6 +// Location: LCCOMB_X27_Y13_N8 cycloneive_lcell_comb \z80_|interrupts_|nmi_armed~feeder ( // Equation(s): // \z80_|interrupts_|nmi_armed~feeder_combout = VCC @@ -4180,24 +4163,24 @@ defparam \z80_|interrupts_|nmi_armed~feeder .lut_mask = 16'hFFFF; defparam \z80_|interrupts_|nmi_armed~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y15_N2 +// Location: LCCOMB_X27_Y13_N4 cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_9 ( // Equation(s): // \z80_|interrupts_|SYNTHESIZED_WIRE_9~combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .dataa(gnd), .datab(gnd), - .datac(gnd), + .datac(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .cin(gnd), .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_9~combout ), .cout()); // synopsys translate_off -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_9 .lut_mask = 16'hAAFF; +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_9 .lut_mask = 16'hF0FF; defparam \z80_|interrupts_|SYNTHESIZED_WIRE_9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y15_N7 +// Location: FF_X27_Y13_N9 dffeas \z80_|interrupts_|nmi_armed ( .clk(!\KEY[1]~input_o ), .d(\z80_|interrupts_|nmi_armed~feeder_combout ), @@ -4216,7 +4199,7 @@ defparam \z80_|interrupts_|nmi_armed .is_wysiwyg = "true"; defparam \z80_|interrupts_|nmi_armed .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y15_N12 +// Location: LCCOMB_X28_Y13_N0 cycloneive_lcell_comb \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder ( // Equation(s): // \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder_combout = \z80_|interrupts_|nmi_armed~q @@ -4233,58 +4216,60 @@ defparam \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder .lut_mask = 16'hFF00 defparam \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_eval_cond~0 ( +// Location: LCCOMB_X26_Y13_N22 +cycloneive_lcell_comb \z80_|sequencer_|DFFE_M2_ff~0 ( // Equation(s): -// \z80_|execute_|ctl_eval_cond~0_combout = (\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) +// \z80_|sequencer_|DFFE_M2_ff~0_combout = (\z80_|execute_|setM1~54_combout & ((\z80_|execute_|nextM~14_combout & (!\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|DFFE_M2_ff~q ))))) - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|execute_|setM1~54_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|execute_|nextM~14_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_eval_cond~0_combout ), + .combout(\z80_|sequencer_|DFFE_M2_ff~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_eval_cond~0 .lut_mask = 16'h00F0; -defparam \z80_|execute_|ctl_eval_cond~0 .sum_lutc_input = "datac"; +defparam \z80_|sequencer_|DFFE_M2_ff~0 .lut_mask = 16'h44C0; +defparam \z80_|sequencer_|DFFE_M2_ff~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X41_Y18_N0 -cycloneive_lcell_comb \z80_|execute_|ixy_d~4 ( -// Equation(s): -// \z80_|execute_|ixy_d~4_combout = (!\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~4_combout ), - .cout()); +// Location: FF_X26_Y13_N23 +dffeas \z80_|sequencer_|DFFE_M2_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|DFFE_M2_ff~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_M2_ff~q ), + .prn(vcc)); // synopsys translate_off -defparam \z80_|execute_|ixy_d~4 .lut_mask = 16'h1100; -defparam \z80_|execute_|ixy_d~4 .sum_lutc_input = "datac"; +defparam \z80_|sequencer_|DFFE_M2_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_M2_ff .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y17_N30 +// Location: LCCOMB_X26_Y13_N6 cycloneive_lcell_comb \z80_|sequencer_|DFFE_M3_ff~0 ( // Equation(s): -// \z80_|sequencer_|DFFE_M3_ff~0_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|DFFE_M3_ff~q ))))) +// \z80_|sequencer_|DFFE_M3_ff~0_combout = (\z80_|execute_|setM1~54_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|DFFE_M3_ff~q ))))) - .dataa(\z80_|execute_|setM1~52_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|execute_|setM1~54_combout ), .datac(\z80_|sequencer_|DFFE_M3_ff~q ), .datad(\z80_|execute_|nextM~14_combout ), .cin(gnd), .combout(\z80_|sequencer_|DFFE_M3_ff~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|sequencer_|DFFE_M3_ff~0 .lut_mask = 16'h88A0; +defparam \z80_|sequencer_|DFFE_M3_ff~0 .lut_mask = 16'h88C0; defparam \z80_|sequencer_|DFFE_M3_ff~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y17_N31 +// Location: FF_X26_Y13_N7 dffeas \z80_|sequencer_|DFFE_M3_ff ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|sequencer_|DFFE_M3_ff~0_combout ), @@ -4303,41 +4288,24 @@ defparam \z80_|sequencer_|DFFE_M3_ff .is_wysiwyg = "true"; defparam \z80_|sequencer_|DFFE_M3_ff .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X37_Y18_N12 -cycloneive_lcell_comb \z80_|execute_|fIOWrite~1 ( -// Equation(s): -// \z80_|execute_|fIOWrite~1_combout = (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|execute_|ixy_d~4_combout ))) - - .dataa(\z80_|execute_|ixy_d~4_combout ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|fIOWrite~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIOWrite~1 .lut_mask = 16'hD0D0; -defparam \z80_|execute_|fIOWrite~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N2 +// Location: LCCOMB_X26_Y13_N10 cycloneive_lcell_comb \z80_|sequencer_|DFFE_M4_ff~0 ( // Equation(s): -// \z80_|sequencer_|DFFE_M4_ff~0_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|DFFE_M4_ff~q ))))) +// \z80_|sequencer_|DFFE_M4_ff~0_combout = (\z80_|execute_|setM1~54_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|DFFE_M4_ff~q ))))) - .dataa(\z80_|execute_|setM1~52_combout ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|execute_|setM1~54_combout ), .datac(\z80_|sequencer_|DFFE_M4_ff~q ), .datad(\z80_|execute_|nextM~14_combout ), .cin(gnd), .combout(\z80_|sequencer_|DFFE_M4_ff~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|sequencer_|DFFE_M4_ff~0 .lut_mask = 16'h88A0; +defparam \z80_|sequencer_|DFFE_M4_ff~0 .lut_mask = 16'h88C0; defparam \z80_|sequencer_|DFFE_M4_ff~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y17_N3 +// Location: FF_X26_Y13_N11 dffeas \z80_|sequencer_|DFFE_M4_ff ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|sequencer_|DFFE_M4_ff~0_combout ), @@ -4356,1685 +4324,24 @@ defparam \z80_|sequencer_|DFFE_M4_ff .is_wysiwyg = "true"; defparam \z80_|sequencer_|DFFE_M4_ff .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y11_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal32~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal32~0_combout = (\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4]) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [3]), - .datac(gnd), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal32~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal32~0 .lut_mask = 16'h00CC; -defparam \z80_|pla_decode_|Equal32~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N14 -cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_11 ( -// Equation(s): -// \z80_|resets_|SYNTHESIZED_WIRE_11~combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_11 .lut_mask = 16'hFF33; -defparam \z80_|resets_|SYNTHESIZED_WIRE_11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N10 -cycloneive_lcell_comb \z80_|decode_state_|table_xx~0 ( -// Equation(s): -// \z80_|decode_state_|table_xx~0_combout = (\z80_|decode_state_|DFFE_instED~q ) # (\z80_|decode_state_|DFFE_instCB~q ) - - .dataa(\z80_|decode_state_|DFFE_instED~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|decode_state_|DFFE_instCB~q ), - .cin(gnd), - .combout(\z80_|decode_state_|table_xx~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|table_xx~0 .lut_mask = 16'hFFAA; -defparam \z80_|decode_state_|table_xx~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N10 -cycloneive_lcell_comb \z80_|pla_decode_|Equal1~7 ( -// Equation(s): -// \z80_|pla_decode_|Equal1~7_combout = (\z80_|ir_|opcode [7] & (!\z80_|decode_state_|table_xx~0_combout & (\z80_|ir_|opcode [0] & \z80_|ir_|opcode [6]))) - - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|decode_state_|table_xx~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|ir_|opcode [6]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal1~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal1~7 .lut_mask = 16'h2000; -defparam \z80_|pla_decode_|Equal1~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N20 -cycloneive_lcell_comb \z80_|pla_decode_|Equal2~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal2~0_combout = (!\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal2~0 .lut_mask = 16'h0F00; -defparam \z80_|pla_decode_|Equal2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N12 -cycloneive_lcell_comb \z80_|pla_decode_|Equal36~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal36~0_combout = (\z80_|pla_decode_|Equal1~7_combout & (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal32~0_combout & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~7_combout ), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|pla_decode_|Equal32~0_combout ), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal36~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal36~0 .lut_mask = 16'h2000; -defparam \z80_|pla_decode_|Equal36~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_cb_set ( -// Equation(s): -// \z80_|execute_|ctl_state_tbl_cb_set~combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|pla_decode_|Equal41~2_combout ) # ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal36~0_combout )))) # -// (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|pla_decode_|Equal36~0_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|pla_decode_|Equal41~2_combout ), - .datad(\z80_|pla_decode_|Equal36~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_tbl_cb_set~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_tbl_cb_set .lut_mask = 16'hB3A0; -defparam \z80_|execute_|ctl_state_tbl_cb_set .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_state_tbl_we~8_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # ((\z80_|sequencer_|DFFE_T3_ff~q & \z80_|pla_decode_|Equal41~2_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|pla_decode_|Equal41~2_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_tbl_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_tbl_we~8 .lut_mask = 16'h00EA; -defparam \z80_|execute_|ctl_state_tbl_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X41_Y17_N29 -dffeas \z80_|decode_state_|DFFE_instCB ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_state_tbl_cb_set~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_state_tbl_we~8_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|decode_state_|DFFE_instCB~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instCB .is_wysiwyg = "true"; -defparam \z80_|decode_state_|DFFE_instCB .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal52~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal52~0_combout = (\z80_|ir_|opcode [7] & (!\z80_|decode_state_|DFFE_instCB~q & (\z80_|ir_|opcode [6] & !\z80_|decode_state_|DFFE_instED~q ))) - - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|decode_state_|DFFE_instCB~q ), - .datac(\z80_|ir_|opcode [6]), - .datad(\z80_|decode_state_|DFFE_instED~q ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal52~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal52~0 .lut_mask = 16'h0020; -defparam \z80_|pla_decode_|Equal52~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal2~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal2~1_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal32~0_combout & \z80_|pla_decode_|Equal52~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|pla_decode_|Equal32~0_combout ), - .datad(\z80_|pla_decode_|Equal52~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal2~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal2~1 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal2~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_ed_set ( -// Equation(s): -// \z80_|execute_|ctl_state_tbl_ed_set~combout = (\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal2~1_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & !\z80_|ir_|opcode [1]))) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|pla_decode_|Equal2~1_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_tbl_ed_set~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_tbl_ed_set .lut_mask = 16'h0008; -defparam \z80_|execute_|ctl_state_tbl_ed_set .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X41_Y17_N17 -dffeas \z80_|decode_state_|DFFE_instED ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_state_tbl_ed_set~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_state_tbl_we~8_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|decode_state_|DFFE_instED~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instED .is_wysiwyg = "true"; -defparam \z80_|decode_state_|DFFE_instED .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal13~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal13~0_combout = (!\z80_|ir_|opcode [7] & (\z80_|ir_|opcode [6] & \z80_|decode_state_|DFFE_instED~q )) - - .dataa(\z80_|ir_|opcode [7]), - .datab(gnd), - .datac(\z80_|ir_|opcode [6]), - .datad(\z80_|decode_state_|DFFE_instED~q ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal13~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal13~0 .lut_mask = 16'h5000; -defparam \z80_|pla_decode_|Equal13~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal33~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal33~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1])) - - .dataa(\z80_|ir_|opcode [0]), - .datab(gnd), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal33~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal33~0 .lut_mask = 16'h5000; -defparam \z80_|pla_decode_|Equal33~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_im_we ( -// Equation(s): -// \z80_|execute_|ctl_im_we~combout = (\z80_|pla_decode_|Equal13~0_combout & (\z80_|sequencer_|DFFE_T3_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|pla_decode_|Equal33~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_im_we~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_im_we .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_im_we .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N18 -cycloneive_lcell_comb \z80_|pla_decode_|Equal49~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal49~0_combout = (!\z80_|decode_state_|in_halt~q & (\z80_|pla_decode_|Equal77~0_combout & \z80_|pla_decode_|Equal33~0_combout )) - - .dataa(gnd), - .datab(\z80_|decode_state_|in_halt~q ), - .datac(\z80_|pla_decode_|Equal77~0_combout ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal49~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal49~0 .lut_mask = 16'h3000; -defparam \z80_|pla_decode_|Equal49~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N2 -cycloneive_lcell_comb \z80_|pla_decode_|Equal33~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal33~1_combout = (\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [5] & !\z80_|ir_|opcode [3])) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|ir_|opcode [3]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal33~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal33~1 .lut_mask = 16'h0808; -defparam \z80_|pla_decode_|Equal33~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N30 -cycloneive_lcell_comb \z80_|pla_decode_|Equal6~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal6~0_combout = (!\z80_|ir_|opcode [7] & (!\z80_|decode_state_|DFFE_instCB~q & (!\z80_|ir_|opcode [6] & !\z80_|decode_state_|DFFE_instED~q ))) - - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|decode_state_|DFFE_instCB~q ), - .datac(\z80_|ir_|opcode [6]), - .datad(\z80_|decode_state_|DFFE_instED~q ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal6~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal6~0 .lut_mask = 16'h0001; -defparam \z80_|pla_decode_|Equal6~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~14 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~14_combout = (!\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal6~0_combout )) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~14 .lut_mask = 16'h4400; -defparam \z80_|execute_|ctl_mRead~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N18 -cycloneive_lcell_comb \z80_|pla_decode_|Equal12~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal12~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2]))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal12~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal12~0 .lut_mask = 16'h0040; -defparam \z80_|pla_decode_|Equal12~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~8 ( -// Equation(s): -// \z80_|execute_|ctl_sw_1d~8_combout = (((!\z80_|ir_|opcode [4] & \z80_|ir_|opcode [5])) # (!\z80_|pla_decode_|Equal12~0_combout )) # (!\z80_|ir_|opcode [3]) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal12~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~8 .lut_mask = 16'h4FFF; -defparam \z80_|execute_|ctl_sw_1d~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N12 -cycloneive_lcell_comb \z80_|nM1_int~2 ( -// Equation(s): -// \z80_|nM1_int~2_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|nM1_int~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|nM1_int~2 .lut_mask = 16'h0055; -defparam \z80_|nM1_int~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~5 ( -// Equation(s): -// \z80_|execute_|ctl_sw_1d~5_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal49~0_combout ) # ((\z80_|execute_|ctl_mRead~14_combout ) # (!\z80_|execute_|ctl_sw_1d~8_combout )))) - - .dataa(\z80_|pla_decode_|Equal49~0_combout ), - .datab(\z80_|execute_|ctl_mRead~14_combout ), - .datac(\z80_|execute_|ctl_sw_1d~8_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~5 .lut_mask = 16'hEF00; -defparam \z80_|execute_|ctl_sw_1d~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal3~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal3~0_combout = (\z80_|ir_|opcode [3] & \z80_|ir_|opcode [4]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal3~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal3~0 .lut_mask = 16'hF000; -defparam \z80_|pla_decode_|Equal3~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~4 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~4_combout = (\z80_|pla_decode_|Equal1~7_combout & (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal3~0_combout & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~7_combout ), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|pla_decode_|Equal3~0_combout ), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~4 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_mRead~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|ixy_d~7 ( -// Equation(s): -// \z80_|execute_|ixy_d~7_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M3_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~7 .lut_mask = 16'h0F00; -defparam \z80_|execute_|ixy_d~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~4 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~4_combout = (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~4 .lut_mask = 16'hA0A0; -defparam \z80_|execute_|ctl_state_alu~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~4 ( -// Equation(s): -// \z80_|execute_|ctl_sw_1d~4_combout = (\z80_|execute_|ctl_mRead~5_combout & (!\z80_|execute_|ctl_state_alu~4_combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|execute_|ctl_mRead~4_combout )))) # (!\z80_|execute_|ctl_mRead~5_combout & -// (((!\z80_|execute_|ixy_d~7_combout )) # (!\z80_|execute_|ctl_mRead~4_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~5_combout ), - .datab(\z80_|execute_|ctl_mRead~4_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~4 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_sw_1d~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N10 -cycloneive_lcell_comb \z80_|pla_decode_|Equal40~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal40~1_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal40~0_combout & \z80_|ir_|opcode [5])) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal40~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal40~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal40~1 .lut_mask = 16'h8080; -defparam \z80_|pla_decode_|Equal40~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal39~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal39~0_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal40~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal3~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal40~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal3~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal39~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal39~0 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal39~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~1 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~1_combout = (!\z80_|pla_decode_|Equal40~1_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal39~0_combout )) - - .dataa(\z80_|pla_decode_|Equal40~1_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~1 .lut_mask = 16'h0005; -defparam \z80_|execute_|ctl_bus_db_oe~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N26 -cycloneive_lcell_comb \z80_|pla_decode_|Equal13~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal13~1_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1])) - - .dataa(\z80_|ir_|opcode [0]), - .datab(gnd), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal13~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal13~1 .lut_mask = 16'hA000; -defparam \z80_|pla_decode_|Equal13~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal13~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal13~2_combout = (\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|pla_decode_|Equal13~1_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal13~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal13~2 .lut_mask = 16'h2000; -defparam \z80_|pla_decode_|Equal13~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal3~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal3~2_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal3~0_combout & \z80_|pla_decode_|Equal52~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|pla_decode_|Equal3~0_combout ), - .datad(\z80_|pla_decode_|Equal52~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal3~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal3~2 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal3~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_state_iy_set~2 ( -// Equation(s): -// \z80_|execute_|ctl_state_iy_set~2_combout = (\z80_|ir_|opcode [5] & (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal3~2_combout & \z80_|sequencer_|DFFE_T2_ff~q ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|pla_decode_|Equal3~2_combout ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_iy_set~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_iy_set~2 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_state_iy_set~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N26 -cycloneive_lcell_comb \z80_|execute_|ixy_d~8 ( -// Equation(s): -// \z80_|execute_|ixy_d~8_combout = (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T5_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|sequencer_|DFFE_T5_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~8 .lut_mask = 16'hC0C0; -defparam \z80_|execute_|ixy_d~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ixy_d~6 ( -// Equation(s): -// \z80_|execute_|ixy_d~6_combout = (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~6 .lut_mask = 16'hF000; -defparam \z80_|execute_|ixy_d~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N6 -cycloneive_lcell_comb \z80_|execute_|ixy_d~9 ( -// Equation(s): -// \z80_|execute_|ixy_d~9_combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_M3_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~9 .lut_mask = 16'hF000; -defparam \z80_|execute_|ixy_d~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N8 -cycloneive_lcell_comb \z80_|execute_|ixy_d~12 ( -// Equation(s): -// \z80_|execute_|ixy_d~12_combout = (!\z80_|execute_|ixy_d~7_combout & (!\z80_|execute_|ixy_d~8_combout & (!\z80_|execute_|ixy_d~6_combout & !\z80_|execute_|ixy_d~9_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ixy_d~8_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|execute_|ixy_d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~12 .lut_mask = 16'h0001; -defparam \z80_|execute_|ixy_d~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N22 -cycloneive_lcell_comb \z80_|execute_|ixy_d~10 ( -// Equation(s): -// \z80_|execute_|ixy_d~10_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|pla_decode_|Equal3~1_combout ), - .datac(\z80_|decode_state_|use_ixiy~combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~10 .lut_mask = 16'h8000; -defparam \z80_|execute_|ixy_d~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal44~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal44~0_combout = (\z80_|ir_|opcode [7] & (!\z80_|decode_state_|DFFE_instCB~q & (!\z80_|ir_|opcode [6] & !\z80_|decode_state_|DFFE_instED~q ))) - - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|decode_state_|DFFE_instCB~q ), - .datac(\z80_|ir_|opcode [6]), - .datad(\z80_|decode_state_|DFFE_instED~q ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal44~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal44~0 .lut_mask = 16'h0002; -defparam \z80_|pla_decode_|Equal44~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N0 -cycloneive_lcell_comb \z80_|execute_|ixy_d~16 ( -// Equation(s): -// \z80_|execute_|ixy_d~16_combout = (\z80_|pla_decode_|Equal44~0_combout & (\z80_|pla_decode_|Equal33~0_combout & ((\z80_|decode_state_|DFFE_inst4~q ) # (\z80_|decode_state_|DFFE_instIY1~q )))) - - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(\z80_|pla_decode_|Equal44~0_combout ), - .datac(\z80_|decode_state_|DFFE_instIY1~q ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~16 .lut_mask = 16'hC800; -defparam \z80_|execute_|ixy_d~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N28 -cycloneive_lcell_comb \z80_|execute_|ixy_d~13 ( -// Equation(s): -// \z80_|execute_|ixy_d~13_combout = (\z80_|pla_decode_|Equal41~2_combout ) # ((\z80_|execute_|ixy_d~10_combout ) # (\z80_|execute_|ixy_d~16_combout )) - - .dataa(gnd), - .datab(\z80_|pla_decode_|Equal41~2_combout ), - .datac(\z80_|execute_|ixy_d~10_combout ), - .datad(\z80_|execute_|ixy_d~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~13 .lut_mask = 16'hFFFC; -defparam \z80_|execute_|ixy_d~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal50~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal50~0_combout = (!\z80_|decode_state_|in_halt~q & (\z80_|pla_decode_|Equal77~0_combout & \z80_|pla_decode_|Equal33~1_combout )) - - .dataa(gnd), - .datab(\z80_|decode_state_|in_halt~q ), - .datac(\z80_|pla_decode_|Equal77~0_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal50~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal50~0 .lut_mask = 16'h3000; -defparam \z80_|pla_decode_|Equal50~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal33~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal33~2_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal6~0_combout )) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal33~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal33~2 .lut_mask = 16'h8800; -defparam \z80_|pla_decode_|Equal33~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N30 -cycloneive_lcell_comb \z80_|execute_|ixy_d~17 ( -// Equation(s): -// \z80_|execute_|ixy_d~17_combout = (\z80_|decode_state_|DFFE_inst4~q & (!\z80_|pla_decode_|Equal50~0_combout & ((!\z80_|pla_decode_|Equal33~2_combout )))) # (!\z80_|decode_state_|DFFE_inst4~q & (((!\z80_|pla_decode_|Equal50~0_combout & -// !\z80_|pla_decode_|Equal33~2_combout )) # (!\z80_|decode_state_|DFFE_instIY1~q ))) - - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(\z80_|pla_decode_|Equal50~0_combout ), - .datac(\z80_|decode_state_|DFFE_instIY1~q ), - .datad(\z80_|pla_decode_|Equal33~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~17 .lut_mask = 16'h0537; -defparam \z80_|execute_|ixy_d~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N16 -cycloneive_lcell_comb \z80_|execute_|ixy_d~5 ( -// Equation(s): -// \z80_|execute_|ixy_d~5_combout = (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_M3_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~5 .lut_mask = 16'hF000; -defparam \z80_|execute_|ixy_d~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N22 -cycloneive_lcell_comb \z80_|execute_|ixy_d~14 ( -// Equation(s): -// \z80_|execute_|ixy_d~14_combout = (\z80_|execute_|ixy_d~12_combout & (((!\z80_|execute_|ixy_d~13_combout & \z80_|execute_|ixy_d~17_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) # (!\z80_|execute_|ixy_d~12_combout & -// (!\z80_|execute_|ixy_d~13_combout & (\z80_|execute_|ixy_d~17_combout ))) - - .dataa(\z80_|execute_|ixy_d~12_combout ), - .datab(\z80_|execute_|ixy_d~13_combout ), - .datac(\z80_|execute_|ixy_d~17_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~14 .lut_mask = 16'h30BA; -defparam \z80_|execute_|ixy_d~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N18 -cycloneive_lcell_comb \z80_|execute_|ixy_d~11 ( -// Equation(s): -// \z80_|execute_|ixy_d~11_combout = (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T5_ff~q ) # ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|execute_|ixy_d~4_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|execute_|ixy_d~4_combout ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~11 .lut_mask = 16'hCC8C; -defparam \z80_|execute_|ixy_d~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N12 -cycloneive_lcell_comb \z80_|execute_|ixy_d~15 ( -// Equation(s): -// \z80_|execute_|ixy_d~15_combout = ((\z80_|pla_decode_|Equal49~0_combout & (\z80_|decode_state_|use_ixiy~combout & \z80_|execute_|ixy_d~11_combout ))) # (!\z80_|execute_|ixy_d~14_combout ) - - .dataa(\z80_|pla_decode_|Equal49~0_combout ), - .datab(\z80_|decode_state_|use_ixiy~combout ), - .datac(\z80_|execute_|ixy_d~14_combout ), - .datad(\z80_|execute_|ixy_d~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~15 .lut_mask = 16'h8F0F; -defparam \z80_|execute_|ixy_d~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_state_ixiy_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_state_ixiy_we~2_combout = (\z80_|sequencer_|DFFE_T5_ff~q & ((\z80_|execute_|ixy_d~15_combout ) # ((\z80_|sequencer_|DFFE_T2_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )))) # (!\z80_|sequencer_|DFFE_T5_ff~q & -// (\z80_|sequencer_|DFFE_T2_ff~q & ((!\z80_|sequencer_|DFFE_M1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|execute_|ixy_d~15_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_ixiy_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_ixiy_we~2 .lut_mask = 16'hA0EC; -defparam \z80_|execute_|ctl_state_ixiy_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y15_N23 -dffeas \z80_|decode_state_|DFFE_instIY1 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_state_iy_set~2_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_state_ixiy_we~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|decode_state_|DFFE_instIY1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instIY1 .is_wysiwyg = "true"; -defparam \z80_|decode_state_|DFFE_instIY1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~5_combout = (!\z80_|decode_state_|DFFE_inst4~q & (!\z80_|decode_state_|DFFE_instIY1~q & \z80_|decode_state_|DFFE_instCB~q )) - - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(gnd), - .datac(\z80_|decode_state_|DFFE_instIY1~q ), - .datad(\z80_|decode_state_|DFFE_instCB~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~5 .lut_mask = 16'h0500; -defparam \z80_|execute_|ctl_ir_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~14 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~14_combout = (!\z80_|ir_|opcode [6] & (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) - - .dataa(\z80_|ir_|opcode [6]), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|execute_|ctl_ir_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~14 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_ir_we~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~2 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~2_combout = (\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [6] & (\z80_|ir_|opcode [7] & \z80_|decode_state_|DFFE_instED~q ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|ir_|opcode [6]), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|decode_state_|DFFE_instED~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~2 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_mWrite~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~16 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~16_combout = (\z80_|ir_|opcode [1] & (\z80_|execute_|ctl_mWrite~2_combout & (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [0]))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~16 .lut_mask = 16'h0008; -defparam \z80_|execute_|ctl_mWrite~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~18 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~18_combout = (((!\z80_|execute_|ctl_ir_we~14_combout & !\z80_|execute_|ctl_mWrite~16_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|sequencer_|DFFE_T4_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|execute_|ctl_ir_we~14_combout ), - .datad(\z80_|execute_|ctl_mWrite~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~18 .lut_mask = 16'h777F; -defparam \z80_|execute_|ctl_flags_alu~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~26 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~26_combout = (\z80_|pla_decode_|Equal13~2_combout & !\z80_|ir_|opcode [3]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~26 .lut_mask = 16'h00F0; -defparam \z80_|execute_|ctl_mRead~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~27 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~27_combout = (\z80_|pla_decode_|Equal13~2_combout & \z80_|ir_|opcode [3]) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(gnd), - .datac(\z80_|ir_|opcode [3]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~27 .lut_mask = 16'hA0A0; -defparam \z80_|execute_|ctl_mRead~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~7 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~7_combout = (\z80_|execute_|ctl_flags_alu~18_combout & (((!\z80_|execute_|ctl_mRead~26_combout & !\z80_|execute_|ctl_mRead~27_combout )) # (!\z80_|execute_|ixy_d~9_combout ))) - - .dataa(\z80_|execute_|ctl_flags_alu~18_combout ), - .datab(\z80_|execute_|ctl_mRead~26_combout ), - .datac(\z80_|execute_|ctl_mRead~27_combout ), - .datad(\z80_|execute_|ixy_d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~7 .lut_mask = 16'h02AA; -defparam \z80_|execute_|ctl_bus_db_oe~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~5 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~5_combout = (\z80_|execute_|ctl_bus_db_oe~7_combout & (((\z80_|execute_|ctl_bus_db_oe~1_combout & !\z80_|pla_decode_|Equal13~2_combout )) # (!\z80_|execute_|ixy_d~7_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~5 .lut_mask = 16'h5D00; -defparam \z80_|execute_|ctl_sw_2d~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~18 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~18_combout = (!\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal12~0_combout ))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal12~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~18 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_mRead~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N12 -cycloneive_lcell_comb \z80_|pla_decode_|Equal55~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal55~0_combout = (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1])) - - .dataa(\z80_|ir_|opcode [0]), - .datab(gnd), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal55~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal55~0 .lut_mask = 16'h0500; -defparam \z80_|pla_decode_|Equal55~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|comb~1 ( -// Equation(s): -// \z80_|execute_|comb~1_combout = (\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4]) - - .dataa(\z80_|ir_|opcode [5]), - .datab(gnd), - .datac(\z80_|ir_|opcode [4]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|comb~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|comb~1 .lut_mask = 16'hA0A0; -defparam \z80_|execute_|comb~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~15 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~15_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [3] & \z80_|execute_|comb~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|execute_|comb~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~15 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_mRead~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~17 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~17_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~17 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_mRead~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~5_combout = ((!\z80_|execute_|ctl_mRead~18_combout & (!\z80_|execute_|ctl_mRead~15_combout & !\z80_|execute_|ctl_mRead~17_combout ))) # (!\z80_|execute_|ixy_d~6_combout ) - - .dataa(\z80_|execute_|ctl_mRead~18_combout ), - .datab(\z80_|execute_|ctl_mRead~15_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|execute_|ctl_mRead~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~5 .lut_mask = 16'h0F1F; -defparam \z80_|execute_|ctl_reg_in_hi~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~9 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~9_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal55~0_combout & \z80_|pla_decode_|Equal33~1_combout )) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~9 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_mRead~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal9~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal9~0_combout = (!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal9~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal9~0 .lut_mask = 16'h000F; -defparam \z80_|pla_decode_|Equal9~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~10 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~10_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal55~0_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal9~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal9~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~10 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_mRead~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~8 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~8_combout = (\z80_|pla_decode_|Equal13~0_combout & (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~8 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_mRead~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~20 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~20_combout = (\z80_|execute_|ctl_mRead~9_combout ) # ((\z80_|execute_|ctl_mRead~15_combout ) # ((\z80_|execute_|ctl_mRead~10_combout ) # (\z80_|execute_|ctl_mRead~8_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~9_combout ), - .datab(\z80_|execute_|ctl_mRead~15_combout ), - .datac(\z80_|execute_|ctl_mRead~10_combout ), - .datad(\z80_|execute_|ctl_mRead~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~20 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_mRead~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal12~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal12~1_combout = (\z80_|pla_decode_|Equal55~0_combout & (!\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal6~0_combout )) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal12~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal12~1 .lut_mask = 16'h2200; -defparam \z80_|pla_decode_|Equal12~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N10 -cycloneive_lcell_comb \z80_|pla_decode_|Equal9~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal9~1_combout = (\z80_|pla_decode_|Equal9~0_combout & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal1~7_combout ))) - - .dataa(\z80_|pla_decode_|Equal9~0_combout ), - .datab(\z80_|pla_decode_|Equal2~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal1~7_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal9~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal9~1 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal9~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal25~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal25~0_combout = (\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal55~0_combout & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal25~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal25~0 .lut_mask = 16'h2000; -defparam \z80_|pla_decode_|Equal25~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~21 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~21_combout = (\z80_|pla_decode_|Equal9~1_combout ) # ((\z80_|execute_|ctl_mRead~17_combout ) # ((!\z80_|pla_decode_|Equal12~1_combout & \z80_|pla_decode_|Equal25~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal12~1_combout ), - .datab(\z80_|pla_decode_|Equal9~1_combout ), - .datac(\z80_|execute_|ctl_mRead~17_combout ), - .datad(\z80_|pla_decode_|Equal25~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~21 .lut_mask = 16'hFDFC; -defparam \z80_|execute_|ctl_mRead~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~6 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~6_combout = (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_M4_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~6 .lut_mask = 16'hA0A0; -defparam \z80_|execute_|ctl_state_alu~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal19~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal19~0_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal32~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal1~7_combout ))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|pla_decode_|Equal32~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal1~7_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal19~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal19~0 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal19~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N30 -cycloneive_lcell_comb \z80_|pla_decode_|Equal1~4 ( -// Equation(s): -// \z80_|pla_decode_|Equal1~4_combout = (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [1]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal1~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal1~4 .lut_mask = 16'h000F; -defparam \z80_|pla_decode_|Equal1~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N2 -cycloneive_lcell_comb \z80_|pla_decode_|Equal29~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal29~0_combout = (\z80_|pla_decode_|Equal1~7_combout & (\z80_|pla_decode_|Equal1~4_combout & (\z80_|pla_decode_|Equal32~0_combout & !\z80_|ir_|opcode [5]))) - - .dataa(\z80_|pla_decode_|Equal1~7_combout ), - .datab(\z80_|pla_decode_|Equal1~4_combout ), - .datac(\z80_|pla_decode_|Equal32~0_combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal29~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal29~0 .lut_mask = 16'h0080; -defparam \z80_|pla_decode_|Equal29~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N20 -cycloneive_lcell_comb \z80_|pla_decode_|Equal24~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal24~1_combout = (\z80_|pla_decode_|Equal9~0_combout & (\z80_|pla_decode_|Equal2~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal1~7_combout ))) - - .dataa(\z80_|pla_decode_|Equal9~0_combout ), - .datab(\z80_|pla_decode_|Equal2~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal1~7_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal24~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal24~1 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal24~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N18 -cycloneive_lcell_comb \z80_|pla_decode_|Equal34~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal34~0_combout = (!\z80_|ir_|opcode [0] & (!\z80_|decode_state_|table_xx~0_combout & (\z80_|pla_decode_|Equal3~1_combout & \z80_|pla_decode_|Equal41~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|decode_state_|table_xx~0_combout ), - .datac(\z80_|pla_decode_|Equal3~1_combout ), - .datad(\z80_|pla_decode_|Equal41~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal34~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal34~0 .lut_mask = 16'h1000; -defparam \z80_|pla_decode_|Equal34~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal37~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal37~0_combout = (\z80_|pla_decode_|Equal41~0_combout & (!\z80_|decode_state_|table_xx~0_combout & (!\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal1~4_combout ))) - - .dataa(\z80_|pla_decode_|Equal41~0_combout ), - .datab(\z80_|decode_state_|table_xx~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal1~4_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal37~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal37~0 .lut_mask = 16'h0200; -defparam \z80_|pla_decode_|Equal37~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N12 -cycloneive_lcell_comb \z80_|pla_decode_|Equal35~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal35~0_combout = (\z80_|pla_decode_|Equal41~0_combout & (!\z80_|decode_state_|table_xx~0_combout & (!\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal41~0_combout ), - .datab(\z80_|decode_state_|table_xx~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal35~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal35~0 .lut_mask = 16'h0200; -defparam \z80_|pla_decode_|Equal35~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N14 -cycloneive_lcell_comb \z80_|pla_decode_|Equal38~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal38~2_combout = (!\z80_|ir_|opcode [1] & (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [2] & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal38~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal38~2 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal38~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N14 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~2 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~2_combout = (\z80_|pla_decode_|Equal34~0_combout ) # ((\z80_|pla_decode_|Equal37~0_combout ) # ((\z80_|pla_decode_|Equal35~0_combout ) # (\z80_|pla_decode_|Equal38~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal34~0_combout ), - .datab(\z80_|pla_decode_|Equal37~0_combout ), - .datac(\z80_|pla_decode_|Equal35~0_combout ), - .datad(\z80_|pla_decode_|Equal38~2_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~2 .lut_mask = 16'hFFFE; -defparam \z80_|reg_control_|reg_sys_we_lo~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N22 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~3 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~3_combout = (\z80_|pla_decode_|Equal19~0_combout ) # ((\z80_|pla_decode_|Equal29~0_combout ) # ((\z80_|pla_decode_|Equal24~1_combout ) # (\z80_|reg_control_|reg_sys_we_lo~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal19~0_combout ), - .datab(\z80_|pla_decode_|Equal29~0_combout ), - .datac(\z80_|pla_decode_|Equal24~1_combout ), - .datad(\z80_|reg_control_|reg_sys_we_lo~2_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~3 .lut_mask = 16'hFFFE; -defparam \z80_|reg_control_|reg_sys_we_lo~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N4 -cycloneive_lcell_comb \z80_|execute_|comb~0 ( -// Equation(s): -// \z80_|execute_|comb~0_combout = (\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1]) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [2]), - .datac(\z80_|ir_|opcode [1]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|comb~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|comb~0 .lut_mask = 16'hC0C0; -defparam \z80_|execute_|comb~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N30 -cycloneive_lcell_comb \z80_|pla_decode_|Equal47~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal47~0_combout = (\z80_|pla_decode_|Equal41~0_combout & (!\z80_|decode_state_|table_xx~0_combout & (\z80_|ir_|opcode [0] & \z80_|execute_|comb~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal41~0_combout ), - .datab(\z80_|decode_state_|table_xx~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|execute_|comb~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal47~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal47~0 .lut_mask = 16'h2000; -defparam \z80_|pla_decode_|Equal47~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N8 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~4 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~4_combout = (\z80_|execute_|ctl_state_alu~6_combout & (!\z80_|pla_decode_|Equal47~0_combout & ((!\z80_|reg_control_|reg_sys_we_lo~3_combout ) # (!\z80_|execute_|ctl_state_alu~4_combout )))) # -// (!\z80_|execute_|ctl_state_alu~6_combout & (((!\z80_|reg_control_|reg_sys_we_lo~3_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~6_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|reg_control_|reg_sys_we_lo~3_combout ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~4 .lut_mask = 16'h153F; -defparam \z80_|reg_control_|reg_sys_we_lo~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~22 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~22_combout = (\z80_|reg_control_|reg_sys_we_lo~4_combout & (((!\z80_|execute_|ctl_mRead~20_combout & !\z80_|execute_|ctl_mRead~21_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~20_combout ), - .datab(\z80_|execute_|ctl_mRead~21_combout ), - .datac(\z80_|reg_control_|reg_sys_we_lo~4_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~22 .lut_mask = 16'h10F0; -defparam \z80_|execute_|ctl_mRead~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~24 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~24_combout = (\z80_|execute_|ctl_reg_in_hi~5_combout & (\z80_|execute_|ctl_mRead~22_combout & ((!\z80_|execute_|ctl_state_alu~6_combout ) # (!\z80_|execute_|ctl_mRead~18_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~18_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~5_combout ), - .datac(\z80_|execute_|ctl_mRead~22_combout ), - .datad(\z80_|execute_|ctl_state_alu~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~24 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_mRead~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout = (\z80_|pla_decode_|Equal52~0_combout & (!\z80_|ir_|opcode [0] & (\z80_|execute_|ixy_d~6_combout & \z80_|pla_decode_|Equal3~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal52~0_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|pla_decode_|Equal3~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~6_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & (((!\z80_|pla_decode_|Equal19~0_combout & !\z80_|pla_decode_|Equal35~0_combout )) # (!\z80_|execute_|ixy_d~6_combout ))) - - .dataa(\z80_|pla_decode_|Equal19~0_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|pla_decode_|Equal35~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~6 .lut_mask = 16'h0313; -defparam \z80_|execute_|ctl_reg_in_hi~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N20 -cycloneive_lcell_comb \z80_|pla_decode_|Equal6~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal6~1_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal1~4_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal1~4_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal6~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal6~1 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal6~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~16 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~16_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal1~4_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal52~0_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal1~4_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal52~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~16 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_mRead~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N16 +// Location: LCCOMB_X26_Y13_N0 cycloneive_lcell_comb \z80_|sequencer_|M5~0 ( // Equation(s): -// \z80_|sequencer_|M5~0_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|M5~q ))))) +// \z80_|sequencer_|M5~0_combout = (\z80_|execute_|setM1~54_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|M5~q ))))) - .dataa(\z80_|execute_|setM1~52_combout ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|execute_|setM1~54_combout ), .datac(\z80_|sequencer_|M5~q ), .datad(\z80_|execute_|nextM~14_combout ), .cin(gnd), .combout(\z80_|sequencer_|M5~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|sequencer_|M5~0 .lut_mask = 16'h88A0; +defparam \z80_|sequencer_|M5~0 .lut_mask = 16'h88C0; defparam \z80_|sequencer_|M5~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y17_N17 +// Location: FF_X26_Y13_N1 dffeas \z80_|sequencer_|M5 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|sequencer_|M5~0_combout ), @@ -6053,12847 +4360,427 @@ defparam \z80_|sequencer_|M5 .is_wysiwyg = "true"; defparam \z80_|sequencer_|M5 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X38_Y17_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~2 ( +// Location: LCCOMB_X24_Y11_N10 +cycloneive_lcell_comb \z80_|execute_|ixy_d~5 ( // Equation(s): -// \z80_|execute_|ctl_reg_in_hi~2_combout = (\z80_|sequencer_|M5~q & \z80_|sequencer_|DFFE_T3_ff~q ) +// \z80_|execute_|ixy_d~5_combout = (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ) .dataa(gnd), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), .datad(gnd), .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .combout(\z80_|execute_|ixy_d~5_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~2 .lut_mask = 16'hC0C0; -defparam \z80_|execute_|ctl_reg_in_hi~2 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ixy_d~5 .lut_mask = 16'hC0C0; +defparam \z80_|execute_|ixy_d~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|setM1~29 ( -// Equation(s): -// \z80_|execute_|setM1~29_combout = (\z80_|execute_|ctl_mRead~16_combout & (!\z80_|execute_|ixy_d~6_combout & ((!\z80_|execute_|ctl_mRead~17_combout ) # (!\z80_|execute_|ctl_reg_in_hi~2_combout )))) # (!\z80_|execute_|ctl_mRead~16_combout & -// (((!\z80_|execute_|ctl_mRead~17_combout ) # (!\z80_|execute_|ctl_reg_in_hi~2_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~16_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datad(\z80_|execute_|ctl_mRead~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~29 .lut_mask = 16'h0777; -defparam \z80_|execute_|setM1~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~25 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~25_combout = (\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|execute_|ctl_mRead~16_combout & ((!\z80_|execute_|ctl_state_alu~6_combout ) # (!\z80_|execute_|ctl_mRead~17_combout )))) # (!\z80_|execute_|ctl_state_alu~4_combout -// & (((!\z80_|execute_|ctl_state_alu~6_combout )) # (!\z80_|execute_|ctl_mRead~17_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_mRead~17_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_mRead~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~25 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_mRead~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~6_combout = (\z80_|execute_|setM1~29_combout & (\z80_|execute_|ctl_mRead~25_combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|pla_decode_|Equal6~1_combout )))) - - .dataa(\z80_|pla_decode_|Equal6~1_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|execute_|setM1~29_combout ), - .datad(\z80_|execute_|ctl_mRead~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~6 .lut_mask = 16'h7000; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~7_combout = (!\z80_|ir_|opcode [6] & (\z80_|pla_decode_|Equal33~0_combout & (\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) - - .dataa(\z80_|ir_|opcode [6]), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|execute_|ctl_ir_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~7 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_ir_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N2 -cycloneive_lcell_comb \z80_|pla_decode_|Equal52~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal52~1_combout = (!\z80_|decode_state_|DFFE_instED~q & (\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal41~0_combout & !\z80_|decode_state_|DFFE_instCB~q ))) - - .dataa(\z80_|decode_state_|DFFE_instED~q ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|pla_decode_|Equal41~0_combout ), - .datad(\z80_|decode_state_|DFFE_instCB~q ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal52~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal52~1 .lut_mask = 16'h0040; -defparam \z80_|pla_decode_|Equal52~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~14 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~14_combout = (!\z80_|decode_state_|DFFE_inst4~q & (\z80_|pla_decode_|Equal44~0_combout & (!\z80_|decode_state_|DFFE_instIY1~q & \z80_|pla_decode_|Equal33~0_combout ))) - - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(\z80_|pla_decode_|Equal44~0_combout ), - .datac(\z80_|decode_state_|DFFE_instIY1~q ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~14 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_state_alu~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~8 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~8_combout = (\z80_|execute_|ctl_state_alu~4_combout & (((!\z80_|pla_decode_|Equal52~1_combout & !\z80_|execute_|ctl_state_alu~14_combout )))) # (!\z80_|execute_|ctl_state_alu~4_combout & -// (((!\z80_|execute_|ctl_state_alu~14_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_state_alu~6_combout ), - .datac(\z80_|pla_decode_|Equal52~1_combout ), - .datad(\z80_|execute_|ctl_state_alu~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~8 .lut_mask = 16'h115F; -defparam \z80_|execute_|ctl_state_alu~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N20 -cycloneive_lcell_comb \z80_|pla_decode_|Equal24~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal24~0_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|pla_decode_|Equal52~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal24~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal24~0 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal24~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N0 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_pc~0_combout = ((!\z80_|pla_decode_|Equal37~0_combout & ((!\z80_|pla_decode_|Equal9~0_combout ) # (!\z80_|pla_decode_|Equal24~0_combout )))) # (!\z80_|execute_|ixy_d~6_combout ) - - .dataa(\z80_|pla_decode_|Equal24~0_combout ), - .datab(\z80_|pla_decode_|Equal37~0_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|pla_decode_|Equal9~0_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_pc~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_pc~0 .lut_mask = 16'h1F3F; -defparam \z80_|reg_control_|reg_sel_pc~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N26 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~1 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_pc~1_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ctl_reg_in_hi~2_combout & ((!\z80_|pla_decode_|Equal29~0_combout ) # (!\z80_|execute_|ixy_d~6_combout )))) # (!\z80_|pla_decode_|Equal47~0_combout & -// (((!\z80_|pla_decode_|Equal29~0_combout )) # (!\z80_|execute_|ixy_d~6_combout ))) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datad(\z80_|pla_decode_|Equal29~0_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_pc~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_pc~1 .lut_mask = 16'h135F; -defparam \z80_|reg_control_|reg_sel_pc~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N12 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~2 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_pc~2_combout = (\z80_|reg_control_|reg_sel_pc~0_combout & (\z80_|reg_control_|reg_sel_pc~1_combout & ((!\z80_|pla_decode_|Equal38~2_combout ) # (!\z80_|execute_|ixy_d~6_combout )))) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|reg_control_|reg_sel_pc~0_combout ), - .datac(\z80_|reg_control_|reg_sel_pc~1_combout ), - .datad(\z80_|pla_decode_|Equal38~2_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_pc~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_pc~2 .lut_mask = 16'h40C0; -defparam \z80_|reg_control_|reg_sel_pc~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|fMRead~17 ( -// Equation(s): -// \z80_|execute_|fMRead~17_combout = (\z80_|execute_|ctl_state_alu~8_combout & (\z80_|reg_control_|reg_sel_pc~2_combout & ((!\z80_|execute_|ctl_ir_we~7_combout ) # (!\z80_|execute_|ctl_state_alu~4_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_ir_we~7_combout ), - .datac(\z80_|execute_|ctl_state_alu~8_combout ), - .datad(\z80_|reg_control_|reg_sel_pc~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~17 .lut_mask = 16'h7000; -defparam \z80_|execute_|fMRead~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~6 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~6_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal3~1_combout & (!\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|pla_decode_|Equal3~1_combout ), - .datac(\z80_|decode_state_|use_ixiy~combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~6 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_mRead~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal11~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal11~0_combout = (!\z80_|ir_|opcode [1] & (\z80_|execute_|ctl_mWrite~2_combout & (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [0]))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal11~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal11~0 .lut_mask = 16'h0004; -defparam \z80_|pla_decode_|Equal11~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal10~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal10~0_combout = (!\z80_|ir_|opcode [1] & (\z80_|execute_|ctl_mWrite~2_combout & (!\z80_|ir_|opcode [2] & \z80_|ir_|opcode [0]))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal10~0 .lut_mask = 16'h0400; -defparam \z80_|pla_decode_|Equal10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~9_combout = (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|pla_decode_|Equal10~0_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(\z80_|pla_decode_|Equal11~0_combout ), - .datab(\z80_|pla_decode_|Equal10~0_combout ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~9 .lut_mask = 16'h1FFF; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~4 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~4_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & (((!\z80_|execute_|ctl_state_alu~4_combout & !\z80_|execute_|ctl_state_alu~6_combout )) # (!\z80_|execute_|ctl_mRead~6_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_state_alu~6_combout ), - .datac(\z80_|execute_|ctl_mRead~6_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~4 .lut_mask = 16'h1F00; -defparam \z80_|execute_|ctl_sw_2d~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~15 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~15_combout = (\z80_|ir_|opcode [6] & (\z80_|pla_decode_|Equal33~0_combout & (\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) - - .dataa(\z80_|ir_|opcode [6]), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|execute_|ctl_ir_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~15 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_ir_we~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|fMRead~16 ( -// Equation(s): -// \z80_|execute_|fMRead~16_combout = (\z80_|execute_|ctl_reg_in_hi~2_combout & (!\z80_|execute_|ctl_mRead~18_combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_ir_we~15_combout )))) # (!\z80_|execute_|ctl_reg_in_hi~2_combout & -// (((!\z80_|execute_|ctl_state_alu~4_combout )) # (!\z80_|execute_|ctl_ir_we~15_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_mRead~18_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~16 .lut_mask = 16'h135F; -defparam \z80_|execute_|fMRead~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~9 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~9_combout = (\z80_|execute_|ctl_ir_we~5_combout & (\z80_|pla_decode_|Equal41~0_combout & ((!\z80_|decode_state_|DFFE_instCB~q ) # (!\z80_|pla_decode_|Equal33~0_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~5_combout ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|pla_decode_|Equal41~0_combout ), - .datad(\z80_|decode_state_|DFFE_instCB~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~9 .lut_mask = 16'h20A0; -defparam \z80_|execute_|ctl_ir_we~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N22 -cycloneive_lcell_comb \z80_|pla_decode_|Equal46~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal46~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [1] & (\z80_|ir_|opcode [2] & \z80_|decode_state_|DFFE_instCB~q ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [1]), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|decode_state_|DFFE_instCB~q ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal46~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal46~0 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal46~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~10 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~10_combout = (!\z80_|ir_|opcode [6] & (!\z80_|pla_decode_|Equal46~0_combout & (\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) - - .dataa(\z80_|ir_|opcode [6]), - .datab(\z80_|pla_decode_|Equal46~0_combout ), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|execute_|ctl_ir_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~10 .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_ir_we~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~17 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~17_combout = (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|execute_|ctl_ir_we~7_combout ), - .datad(\z80_|execute_|ctl_ir_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~17 .lut_mask = 16'h777F; -defparam \z80_|execute_|ctl_flags_alu~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~6_combout = (\z80_|execute_|ctl_flags_alu~17_combout & (((!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~9_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~15_combout ), - .datab(\z80_|execute_|ctl_ir_we~9_combout ), - .datac(\z80_|execute_|ctl_flags_alu~17_combout ), - .datad(\z80_|execute_|ctl_state_alu~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~6 .lut_mask = 16'h10F0; -defparam \z80_|execute_|ctl_flags_alu~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~6_combout = (!\z80_|ir_|opcode [6] & !\z80_|ir_|opcode [7]) - - .dataa(\z80_|ir_|opcode [6]), - .datab(gnd), - .datac(\z80_|ir_|opcode [7]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~6 .lut_mask = 16'h0505; -defparam \z80_|execute_|ctl_ir_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~8_combout = (\z80_|execute_|ctl_ir_we~5_combout & (\z80_|execute_|ctl_ir_we~6_combout & ((!\z80_|decode_state_|DFFE_instCB~q ) # (!\z80_|pla_decode_|Equal33~0_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~5_combout ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|execute_|ctl_ir_we~6_combout ), - .datad(\z80_|decode_state_|DFFE_instCB~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~8 .lut_mask = 16'h20A0; -defparam \z80_|execute_|ctl_ir_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~16 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~16_combout = (((!\z80_|execute_|ctl_ir_we~8_combout & !\z80_|execute_|ctl_ir_we~14_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M4_ff~q ) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|execute_|ctl_ir_we~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~16 .lut_mask = 16'h3F7F; -defparam \z80_|execute_|ctl_flags_alu~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~3_combout = ((!\z80_|execute_|ctl_mRead~8_combout & (!\z80_|execute_|ctl_mRead~10_combout & !\z80_|execute_|ctl_mRead~9_combout ))) # (!\z80_|execute_|ixy_d~6_combout ) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|execute_|ctl_mRead~8_combout ), - .datac(\z80_|execute_|ctl_mRead~10_combout ), - .datad(\z80_|execute_|ctl_mRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~3 .lut_mask = 16'h5557; -defparam \z80_|execute_|ctl_reg_in_hi~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~8 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~8_combout = (\z80_|execute_|ctl_flags_alu~6_combout & (\z80_|execute_|ctl_flags_alu~16_combout & \z80_|execute_|ctl_reg_in_hi~3_combout )) - - .dataa(\z80_|execute_|ctl_flags_alu~6_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_flags_alu~16_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~8 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_mWrite~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|fMRead~18 ( -// Equation(s): -// \z80_|execute_|fMRead~18_combout = (\z80_|execute_|fMRead~17_combout & (\z80_|execute_|ctl_sw_2d~4_combout & (\z80_|execute_|fMRead~16_combout & \z80_|execute_|ctl_mWrite~8_combout ))) - - .dataa(\z80_|execute_|fMRead~17_combout ), - .datab(\z80_|execute_|ctl_sw_2d~4_combout ), - .datac(\z80_|execute_|fMRead~16_combout ), - .datad(\z80_|execute_|ctl_mWrite~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~18 .lut_mask = 16'h8000; -defparam \z80_|execute_|fMRead~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N26 -cycloneive_lcell_comb \z80_|execute_|fMRead~19 ( -// Equation(s): -// \z80_|execute_|fMRead~19_combout = (\z80_|execute_|ctl_mRead~24_combout & (\z80_|execute_|ctl_reg_in_hi~6_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~6_combout & \z80_|execute_|fMRead~18_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~24_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~6_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), - .datad(\z80_|execute_|fMRead~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~19 .lut_mask = 16'h8000; -defparam \z80_|execute_|fMRead~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~16 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~16_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|execute_|ixy_d~15_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~16 .lut_mask = 16'h0F00; -defparam \z80_|execute_|ctl_alu_shift_oe~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~36 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~36_combout = (\z80_|ir_|opcode [1] & (\z80_|execute_|ctl_mWrite~2_combout & (!\z80_|ir_|opcode [2] & \z80_|ir_|opcode [0]))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~36 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_mRead~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~9_combout = (\z80_|pla_decode_|Equal1~4_combout & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [0] & \z80_|execute_|ctl_mWrite~3_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~4_combout ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|execute_|ctl_mWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~9 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_alu_op_low~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~44 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~44_combout = (!\z80_|execute_|ctl_alu_op_low~9_combout & (((!\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|execute_|ctl_mRead~36_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|execute_|ctl_mRead~36_combout ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|execute_|ctl_alu_op_low~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~44 .lut_mask = 16'h007F; -defparam \z80_|execute_|ctl_alu_shift_oe~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~11 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~11_combout = (\z80_|sequencer_|DFFE_T5_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~11 .lut_mask = 16'h00AA; -defparam \z80_|execute_|ctl_mRead~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~6 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~6_combout = (\z80_|execute_|ixy_d~6_combout & (!\z80_|pla_decode_|Equal9~1_combout & ((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_mRead~11_combout )))) # (!\z80_|execute_|ixy_d~6_combout & -// (((!\z80_|pla_decode_|Equal47~0_combout )) # (!\z80_|execute_|ctl_mRead~11_combout ))) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|execute_|ctl_mRead~11_combout ), - .datac(\z80_|pla_decode_|Equal47~0_combout ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~6 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_sw_2d~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~7 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~7_combout = (\z80_|execute_|ctl_sw_2d~6_combout & (((!\z80_|execute_|ctl_mRead~4_combout & !\z80_|pla_decode_|Equal6~1_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_sw_2d~6_combout ), - .datab(\z80_|execute_|ctl_mRead~4_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal6~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~7 .lut_mask = 16'h0A2A; -defparam \z80_|execute_|ctl_sw_2d~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~7 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~7_combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_M4_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|sequencer_|DFFE_M4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~7 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_mWrite~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~11 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~11_combout = (\z80_|ir_|opcode [6] & (!\z80_|pla_decode_|Equal46~0_combout & (!\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) - - .dataa(\z80_|ir_|opcode [6]), - .datab(\z80_|pla_decode_|Equal46~0_combout ), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|execute_|ctl_ir_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~11 .lut_mask = 16'h0200; -defparam \z80_|execute_|ctl_ir_we~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~12 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~12_combout = (\z80_|ir_|opcode [6] & (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) - - .dataa(\z80_|ir_|opcode [6]), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|execute_|ctl_ir_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~12 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_ir_we~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~0 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~0_combout = (\z80_|execute_|ctl_mWrite~7_combout & (!\z80_|execute_|ctl_ir_we~11_combout & ((!\z80_|execute_|ctl_ir_we~12_combout )))) # (!\z80_|execute_|ctl_mWrite~7_combout & (((!\z80_|execute_|ctl_ir_we~12_combout ) # -// (!\z80_|execute_|ctl_mWrite~3_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~7_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_mWrite~3_combout ), - .datad(\z80_|execute_|ctl_ir_we~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~0 .lut_mask = 16'h0577; -defparam \z80_|execute_|ctl_flags_sz_we~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout = (\z80_|pla_decode_|Equal1~4_combout & (!\z80_|ir_|opcode [0] & (\z80_|nM1_int~2_combout & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~4_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~8 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~8_combout = (\z80_|execute_|ctl_alu_shift_oe~44_combout & (\z80_|execute_|ctl_sw_2d~7_combout & (\z80_|execute_|ctl_flags_sz_we~0_combout & !\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~44_combout ), - .datab(\z80_|execute_|ctl_sw_2d~7_combout ), - .datac(\z80_|execute_|ctl_flags_sz_we~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~8 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_sw_2d~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~9 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~9_combout = (\z80_|execute_|ctl_sw_2d~5_combout & (\z80_|execute_|fMRead~19_combout & (!\z80_|execute_|ctl_alu_shift_oe~16_combout & \z80_|execute_|ctl_sw_2d~8_combout ))) - - .dataa(\z80_|execute_|ctl_sw_2d~5_combout ), - .datab(\z80_|execute_|fMRead~19_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~16_combout ), - .datad(\z80_|execute_|ctl_sw_2d~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~9 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_sw_2d~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~6 ( -// Equation(s): -// \z80_|execute_|ctl_sw_1d~6_combout = (!\z80_|execute_|ctl_im_we~combout & (!\z80_|execute_|ctl_sw_1d~5_combout & (\z80_|execute_|ctl_sw_1d~4_combout & \z80_|execute_|ctl_sw_2d~9_combout ))) - - .dataa(\z80_|execute_|ctl_im_we~combout ), - .datab(\z80_|execute_|ctl_sw_1d~5_combout ), - .datac(\z80_|execute_|ctl_sw_1d~4_combout ), - .datad(\z80_|execute_|ctl_sw_2d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~6 .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_sw_1d~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~7 ( -// Equation(s): -// \z80_|execute_|ctl_sw_1d~7_combout = ((!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & \z80_|pla_decode_|Equal47~0_combout ))) # (!\z80_|execute_|ctl_sw_1d~6_combout ) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|execute_|ctl_sw_1d~6_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~7 .lut_mask = 16'h7333; -defparam \z80_|execute_|ctl_sw_1d~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y18_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~8_combout = (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~8 .lut_mask = 16'hC0C0; -defparam \z80_|execute_|ctl_alu_op_low~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y18_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout = (\z80_|execute_|ctl_mWrite~2_combout & (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal2~0_combout & \z80_|execute_|ctl_alu_op_low~8_combout ))) - - .dataa(\z80_|execute_|ctl_mWrite~2_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|pla_decode_|Equal2~0_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|execute_|ixy_d~15_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~39 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~39_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout & (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & ((!\z80_|execute_|ctl_mRead~36_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_mRead~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~39 .lut_mask = 16'h0111; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|pla_decode_|Equal21~1_combout & !\z80_|sequencer_|DFFE_M1_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|pla_decode_|Equal21~1_combout ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 .lut_mask = 16'h0088; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_hi~4_combout = ((!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal40~1_combout & !\z80_|pla_decode_|Equal39~0_combout ))) # (!\z80_|execute_|ixy_d~9_combout ) - - .dataa(\z80_|execute_|ixy_d~9_combout ), - .datab(\z80_|pla_decode_|Equal21~1_combout ), - .datac(\z80_|pla_decode_|Equal40~1_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_hi~4 .lut_mask = 16'h5557; -defparam \z80_|execute_|ctl_reg_out_hi~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~15 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~15_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal6~0_combout & (!\z80_|pla_decode_|Equal33~1_combout & \z80_|pla_decode_|Equal3~1_combout ))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|pla_decode_|Equal33~1_combout ), - .datad(\z80_|pla_decode_|Equal3~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~15 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_alu_shift_oe~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~38 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~38_combout = (!\z80_|execute_|ctl_alu_shift_oe~15_combout & (((!\z80_|execute_|ctl_state_alu~4_combout & !\z80_|execute_|ctl_state_alu~6_combout )) # (!\z80_|execute_|ctl_mRead~6_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~38 .lut_mask = 16'h0037; -defparam \z80_|execute_|ctl_alu_shift_oe~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_zero ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_zero~combout = ((\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~38_combout ) # (!\z80_|execute_|ctl_reg_out_hi~4_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), - .datac(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_zero .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_alu_op2_sel_zero .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N14 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~4 ( -// Equation(s): -// \z80_|alu_|db_low[2]~4_combout = ((\z80_|bus_control_|db[4]~19_combout & (!\z80_|bus_control_|db[5]~15_combout & !\z80_|bus_control_|db[3]~21_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datab(\z80_|bus_control_|db[4]~19_combout ), - .datac(\z80_|bus_control_|db[5]~15_combout ), - .datad(\z80_|bus_control_|db[3]~21_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~4 .lut_mask = 16'h555D; -defparam \z80_|alu_|db_low[2]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~14_combout = (\z80_|sequencer_|DFFE_M4_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~14 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_alu_shift_oe~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~11 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[0]~11_combout = ((!\z80_|pla_decode_|Equal40~1_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal39~0_combout ))) # (!\z80_|execute_|ixy_d~5_combout ) - - .dataa(\z80_|pla_decode_|Equal40~1_combout ), - .datab(\z80_|pla_decode_|Equal21~1_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~11 .lut_mask = 16'h0F1F; -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~1 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~1_combout = (\z80_|execute_|ctl_reg_out_hi~4_combout & \z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~1 .lut_mask = 16'hCC00; -defparam \z80_|execute_|ctl_sw_4u~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~5_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout & (((!\z80_|pla_decode_|Equal21~1_combout & !\z80_|execute_|ctl_mRead~36_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), - .datab(\z80_|pla_decode_|Equal21~1_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_mRead~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~5 .lut_mask = 16'h0515; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~30 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~30_combout = (\z80_|execute_|ctl_sw_4u~1_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~5_combout & ((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|execute_|ctl_sw_4u~1_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~30 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_alu_shift_oe~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~29 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~29_combout = (\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|execute_|ctl_mRead~36_combout & ((!\z80_|execute_|ctl_mWrite~3_combout ) # (!\z80_|execute_|ctl_mWrite~16_combout )))) # -// (!\z80_|execute_|ctl_state_alu~4_combout & (((!\z80_|execute_|ctl_mWrite~3_combout )) # (!\z80_|execute_|ctl_mWrite~16_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_mWrite~16_combout ), - .datac(\z80_|execute_|ctl_mRead~36_combout ), - .datad(\z80_|execute_|ctl_mWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~29 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_alu_shift_oe~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~31 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~31_combout = (\z80_|execute_|ctl_alu_shift_oe~30_combout & (\z80_|execute_|ctl_alu_shift_oe~29_combout & ((!\z80_|execute_|ctl_mRead~11_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~30_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~29_combout ), - .datad(\z80_|execute_|ctl_mRead~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~31 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_alu_shift_oe~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal69~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal69~0_combout = (!\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|pla_decode_|Equal13~1_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal69~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal69~0 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal69~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N24 -cycloneive_lcell_comb \z80_|pla_decode_|Equal1~5 ( -// Equation(s): -// \z80_|pla_decode_|Equal1~5_combout = (\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [5]) - - .dataa(\z80_|ir_|opcode [4]), - .datab(gnd), - .datac(gnd), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal1~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal1~5 .lut_mask = 16'h00AA; -defparam \z80_|pla_decode_|Equal1~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~14_combout = (\z80_|pla_decode_|Equal1~5_combout & (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~5_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|pla_decode_|Equal13~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~14 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_op_low~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~12 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~12_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal2~0_combout & (!\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal2~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~12 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_alu_op_low~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal56~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal56~0_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal1~4_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal1~4_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal56~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal56~0 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal56~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~11_combout = (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~11 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_alu_op_low~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|nextM~2 ( -// Equation(s): -// \z80_|execute_|nextM~2_combout = (!\z80_|execute_|ctl_alu_op_low~12_combout & (!\z80_|pla_decode_|Equal56~0_combout & !\z80_|execute_|ctl_alu_op_low~11_combout )) - - .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_alu_op_low~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~2 .lut_mask = 16'h0011; -defparam \z80_|execute_|nextM~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~16 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~16_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # ((\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T3_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|execute_|nextM~2_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~16 .lut_mask = 16'h0F08; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~4_combout = (!\z80_|execute_|ctl_alu_op_low~14_combout & (!\z80_|execute_|ctl_alu_op1_sel_bus~16_combout & ((!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # (!\z80_|pla_decode_|Equal69~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal69~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~4 .lut_mask = 16'h0103; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~5_combout = (\z80_|execute_|ctl_alu_shift_oe~38_combout & \z80_|execute_|ctl_alu_op1_sel_bus~4_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~5 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~3 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~3_combout = (\z80_|pla_decode_|Equal77~0_combout & ((\z80_|decode_state_|in_halt~q ) # ((!\z80_|pla_decode_|Equal33~1_combout & !\z80_|pla_decode_|Equal33~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|decode_state_|in_halt~q ), - .datac(\z80_|pla_decode_|Equal77~0_combout ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~3 .lut_mask = 16'hC0D0; -defparam \z80_|execute_|ctl_alu_oe~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~15 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~15_combout = ((!\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|execute_|ixy_d~15_combout ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|execute_|ixy_d~15_combout ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~15 .lut_mask = 16'h0F3F; -defparam \z80_|execute_|ctl_alu_op_low~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~8_combout = (\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|execute_|ctl_ir_we~7_combout & ((!\z80_|execute_|ctl_ir_we~10_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) # -// (!\z80_|execute_|ctl_state_alu~4_combout & (((!\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_ir_we~7_combout ), - .datad(\z80_|execute_|ctl_ir_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~8 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~9_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~8_combout & (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_ir_we~10_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~9 .lut_mask = 16'h1F00; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~3 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~3_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|execute_|ctl_ir_we~9_combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_ir_we~15_combout )))) # -// (!\z80_|execute_|ctl_eval_cond~0_combout & (((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_ir_we~15_combout )))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|ctl_ir_we~9_combout ), - .datac(\z80_|execute_|ctl_ir_we~15_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~3 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_alu_core_R~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~4_combout = (\z80_|execute_|ctl_alu_core_R~3_combout & (((!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~9_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~15_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~3_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_ir_we~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~4 .lut_mask = 16'h0C4C; -defparam \z80_|execute_|ctl_alu_core_R~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|execute_|ctl_ir_we~11_combout )) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|execute_|ctl_ir_we~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 .lut_mask = 16'h3000; -defparam \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~10_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~9_combout & (\z80_|execute_|ctl_flags_sz_we~0_combout & (\z80_|execute_|ctl_alu_core_R~4_combout & !\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout -// ))) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~0_combout ), - .datac(\z80_|execute_|ctl_alu_core_R~4_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~10 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~11_combout = (((\z80_|execute_|ctl_alu_oe~3_combout & \z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~10_combout )) # (!\z80_|execute_|ctl_alu_op_low~15_combout ) - - .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~15_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~11 .lut_mask = 16'h8FFF; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal48~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal48~0_combout = (!\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|pla_decode_|Equal13~1_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal48~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal48~0 .lut_mask = 16'h1000; -defparam \z80_|pla_decode_|Equal48~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf2_we ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf2_we~combout = (\z80_|pla_decode_|Equal63~0_combout & (!\z80_|ir_|opcode [4] & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & !\z80_|ir_|opcode [3]))) - - .dataa(\z80_|pla_decode_|Equal63~0_combout ), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf2_we~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf2_we .lut_mask = 16'h0020; -defparam \z80_|execute_|ctl_flags_hf2_we .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~41 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~41_combout = (!\z80_|execute_|ctl_flags_hf2_we~combout & (((!\z80_|pla_decode_|Equal10~0_combout & !\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|execute_|ctl_flags_hf2_we~combout ), - .datad(\z80_|pla_decode_|Equal11~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~41 .lut_mask = 16'h0307; -defparam \z80_|execute_|ctl_alu_shift_oe~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~18 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~18_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|pla_decode_|Equal44~0_combout & !\z80_|pla_decode_|Equal52~1_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|pla_decode_|Equal44~0_combout ), - .datad(\z80_|pla_decode_|Equal52~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~18 .lut_mask = 16'hBBBF; -defparam \z80_|execute_|ctl_flags_xy_we~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~17 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~17_combout = ((!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal35~0_combout & !\z80_|pla_decode_|Equal39~0_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|pla_decode_|Equal21~1_combout ), - .datac(\z80_|pla_decode_|Equal35~0_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~17 .lut_mask = 16'h5557; -defparam \z80_|execute_|ctl_alu_shift_oe~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~19 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~19_combout = (\z80_|pla_decode_|Equal40~1_combout ) # ((\z80_|pla_decode_|Equal37~0_combout ) # ((\z80_|pla_decode_|Equal41~2_combout ) # (\z80_|pla_decode_|Equal34~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal40~1_combout ), - .datab(\z80_|pla_decode_|Equal37~0_combout ), - .datac(\z80_|pla_decode_|Equal41~2_combout ), - .datad(\z80_|pla_decode_|Equal34~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~19 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_alu_shift_oe~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_iorw~10 ( -// Equation(s): -// \z80_|execute_|ctl_iorw~10_combout = (!\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [2] & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_iorw~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_iorw~10 .lut_mask = 16'h0100; -defparam \z80_|execute_|ctl_iorw~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~18 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~18_combout = ((!\z80_|execute_|ctl_mWrite~16_combout & (!\z80_|execute_|ctl_mRead~36_combout & !\z80_|execute_|ctl_iorw~10_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) - - .dataa(\z80_|execute_|ctl_mWrite~16_combout ), - .datab(\z80_|execute_|ctl_mRead~36_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_iorw~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~18 .lut_mask = 16'h0F1F; -defparam \z80_|execute_|ctl_alu_shift_oe~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~20 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~20_combout = (\z80_|execute_|ctl_alu_shift_oe~17_combout & (\z80_|execute_|ctl_alu_shift_oe~18_combout & ((!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # (!\z80_|execute_|ctl_alu_shift_oe~19_combout )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~17_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~19_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~20 .lut_mask = 16'h2A00; -defparam \z80_|execute_|ctl_alu_shift_oe~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~13 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~13_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~12_combout ))) # (!\z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|execute_|ctl_ir_we~9_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|ctl_ir_we~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~13 .lut_mask = 16'hF5F7; -defparam \z80_|execute_|ctl_alu_bs_oe~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~9_combout = (\z80_|execute_|ctl_alu_bs_oe~13_combout & (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|execute_|ctl_alu_bs_oe~13_combout ), - .datac(\z80_|execute_|ctl_ir_we~10_combout ), - .datad(\z80_|execute_|ctl_ir_we~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~9 .lut_mask = 16'h444C; -defparam \z80_|execute_|ctl_alu_bs_oe~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~3 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~3_combout = (\z80_|execute_|ctl_alu_bs_oe~9_combout & (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~11_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~9_combout ), - .datad(\z80_|execute_|ctl_ir_we~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~3 .lut_mask = 16'h3070; -defparam \z80_|execute_|ctl_bus_db_oe~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N26 -cycloneive_lcell_comb \z80_|pla_decode_|Equal20~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal20~0_combout = (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [5] & (\z80_|execute_|comb~0_combout & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|execute_|comb~0_combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal20~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal20~0 .lut_mask = 16'h2000; -defparam \z80_|pla_decode_|Equal20~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal68~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal68~2_combout = (!\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [2] & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal68~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal68~2 .lut_mask = 16'h1000; -defparam \z80_|pla_decode_|Equal68~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~14 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~14_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal20~0_combout & !\z80_|pla_decode_|Equal68~2_combout ))) # (!\z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|pla_decode_|Equal20~0_combout ), - .datab(\z80_|pla_decode_|Equal68~2_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~14 .lut_mask = 16'hFF1F; -defparam \z80_|execute_|ctl_flags_bus~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~13 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~13_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal3~1_combout & ((!\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal21~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal21~0_combout ), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|pla_decode_|Equal3~1_combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~13 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_alu_op_low~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~15 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~15_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|execute_|ctl_alu_op_low~13_combout & !\z80_|execute_|ctl_alu_op_low~12_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|execute_|ctl_alu_op_low~13_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~15 .lut_mask = 16'hBBBF; -defparam \z80_|execute_|ctl_flags_bus~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~11_combout = (\z80_|execute_|ctl_flags_bus~15_combout & (((!\z80_|execute_|ctl_ir_we~14_combout & !\z80_|execute_|ctl_ir_we~8_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|execute_|ctl_ir_we~14_combout ), - .datac(\z80_|execute_|ctl_ir_we~8_combout ), - .datad(\z80_|execute_|ctl_flags_bus~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~11 .lut_mask = 16'h5700; -defparam \z80_|execute_|ctl_flags_bus~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N20 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~11 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~11_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|pla_decode_|Equal56~0_combout & !\z80_|execute_|ctl_alu_op_low~11_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|execute_|ctl_alu_op_low~11_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~11 .lut_mask = 16'hAFBF; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~10_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~11_combout & (((!\z80_|pla_decode_|Equal21~0_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )) # (!\z80_|pla_decode_|Equal63~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal63~0_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~11_combout ), - .datad(\z80_|pla_decode_|Equal21~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~10 .lut_mask = 16'h70F0; -defparam \z80_|execute_|ctl_flags_bus~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~8_combout = (\z80_|execute_|ixy_d~10_combout ) # ((\z80_|pla_decode_|Equal63~0_combout & ((\z80_|pla_decode_|Equal3~0_combout ) # (\z80_|pla_decode_|Equal32~0_combout )))) - - .dataa(\z80_|execute_|ixy_d~10_combout ), - .datab(\z80_|pla_decode_|Equal63~0_combout ), - .datac(\z80_|pla_decode_|Equal3~0_combout ), - .datad(\z80_|pla_decode_|Equal32~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~8 .lut_mask = 16'hEEEA; -defparam \z80_|execute_|ctl_flags_bus~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~9_combout = ((!\z80_|pla_decode_|Equal13~2_combout & (!\z80_|execute_|ctl_mRead~6_combout & !\z80_|execute_|ctl_flags_bus~8_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|execute_|ctl_mRead~6_combout ), - .datad(\z80_|execute_|ctl_flags_bus~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~9 .lut_mask = 16'h3337; -defparam \z80_|execute_|ctl_flags_bus~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~12 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~12_combout = (\z80_|execute_|ctl_flags_bus~14_combout & (\z80_|execute_|ctl_flags_bus~11_combout & (\z80_|execute_|ctl_flags_bus~10_combout & \z80_|execute_|ctl_flags_bus~9_combout ))) - - .dataa(\z80_|execute_|ctl_flags_bus~14_combout ), - .datab(\z80_|execute_|ctl_flags_bus~11_combout ), - .datac(\z80_|execute_|ctl_flags_bus~10_combout ), - .datad(\z80_|execute_|ctl_flags_bus~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~12 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_bus~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~11_combout = (\z80_|execute_|ctl_flags_xy_we~18_combout & (\z80_|execute_|ctl_alu_shift_oe~20_combout & (\z80_|execute_|ctl_bus_db_oe~3_combout & \z80_|execute_|ctl_flags_bus~12_combout ))) - - .dataa(\z80_|execute_|ctl_flags_xy_we~18_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~20_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~3_combout ), - .datad(\z80_|execute_|ctl_flags_bus~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~11 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_xy_we~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~12 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~12_combout = (\z80_|execute_|ctl_alu_shift_oe~41_combout & (\z80_|execute_|ctl_flags_xy_we~11_combout & ((!\z80_|execute_|ctl_state_alu~14_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~41_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~11_combout ), - .datad(\z80_|execute_|ctl_state_alu~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~12 .lut_mask = 16'h20A0; -defparam \z80_|execute_|ctl_flags_xy_we~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~6_combout = (\z80_|execute_|ctl_mWrite~3_combout & (!\z80_|execute_|ctl_ir_we~14_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|execute_|ctl_ir_we~8_combout )))) # -// (!\z80_|execute_|ctl_mWrite~3_combout & (((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|execute_|ctl_ir_we~8_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~3_combout ), - .datab(\z80_|execute_|ctl_ir_we~14_combout ), - .datac(\z80_|execute_|ctl_ir_we~8_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~6 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~7 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~7_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~6_combout & (\z80_|execute_|ctl_flags_alu~16_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal20~0_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ), - .datac(\z80_|execute_|ctl_flags_alu~16_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~7 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~4_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M4_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~4 .lut_mask = 16'h3030; -defparam \z80_|execute_|ctl_ir_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~8_combout = ((!\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~9_combout ))) # (!\z80_|execute_|ctl_ir_we~4_combout ) - - .dataa(\z80_|execute_|ctl_ir_we~12_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_ir_we~9_combout ), - .datad(\z80_|execute_|ctl_ir_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~8 .lut_mask = 16'h01FF; -defparam \z80_|execute_|ctl_alu_bs_oe~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~0_combout = (\z80_|execute_|ctl_alu_bs_oe~8_combout & (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_ir_we~10_combout ), - .datad(\z80_|execute_|ctl_alu_bs_oe~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~0 .lut_mask = 16'h3700; -defparam \z80_|execute_|ctl_bus_db_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~12 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~12_combout = (!\z80_|execute_|ctl_alu_op_low~9_combout & (((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|pla_decode_|Equal41~2_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~9_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|pla_decode_|Equal41~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~12 .lut_mask = 16'h0515; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~13 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~13_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~7_combout & (\z80_|execute_|ctl_bus_db_oe~0_combout & \z80_|execute_|ctl_alu_op1_sel_bus~12_combout )) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_bus_db_oe~0_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~13 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~14_combout = (\z80_|execute_|ctl_flags_xy_we~12_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~13_combout & ((!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # (!\z80_|pla_decode_|Equal48~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal48~0_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~12_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~14 .lut_mask = 16'h4C00; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~15 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~15_combout = (((\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ) # (!\z80_|execute_|ctl_alu_op1_sel_bus~14_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~5_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~31_combout ) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~31_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~5_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~15 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_66_oe~2 ( -// Equation(s): -// \z80_|execute_|ctl_66_oe~2_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|execute_|comb~0_combout & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal52~0_combout ), - .datac(\z80_|execute_|comb~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_66_oe~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_66_oe~2 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_66_oe~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla11M1T1_11 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|pla_decode_|Equal10~0_combout )) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal10~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel_pla11M1T1_11 .lut_mask = 16'h1100; -defparam \z80_|execute_|ctl_pf_sel_pla11M1T1_11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_zero~5_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal63~0_combout & (\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4]))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|pla_decode_|Equal63~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_zero~5 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_alu_op1_sel_zero~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_zero~4_combout = (\z80_|pla_decode_|Equal3~1_combout & (!\z80_|ir_|opcode [0] & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_zero~4 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_alu_op1_sel_zero~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_zero~combout = (\z80_|execute_|ctl_66_oe~2_combout ) # ((\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ) # (\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ))) - - .dataa(\z80_|execute_|ctl_66_oe~2_combout ), - .datab(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_zero .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_alu_op1_sel_zero .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N16 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[2] ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_high|Q [2] = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & (\z80_|alu_|db_high[2]~14_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .datac(\z80_|alu_|db_high[2]~14_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [2]), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[2] .lut_mask = 16'h00C0; -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N2 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|ena~0 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ) # (\z80_|execute_|ctl_alu_op1_sel_zero~combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_high|ena~0 .lut_mask = 16'hFFF0; -defparam \z80_|alu_|b2v_op1_latch_mux_high|ena~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y10_N17 -dffeas \z80_|alu_|op1_high[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [2]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_high [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_high[2] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_high[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_lq ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_lq~combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ixy_d~7_combout ) # ((\z80_|execute_|ixy_d~6_combout & !\z80_|ir_|opcode [3])))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|pla_decode_|Equal13~2_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_lq .lut_mask = 16'h88C8; -defparam \z80_|execute_|ctl_alu_op2_sel_lq .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~10_combout = (((!\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [3])) # (!\z80_|pla_decode_|Equal63~0_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal63~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~10 .lut_mask = 16'h1FFF; -defparam \z80_|execute_|ctl_alu_op_low~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N28 -cycloneive_lcell_comb \z80_|execute_|fMWrite~11 ( -// Equation(s): -// \z80_|execute_|fMWrite~11_combout = ((!\z80_|pla_decode_|Equal13~2_combout ) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|pla_decode_|Equal13~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~11 .lut_mask = 16'h5FFF; -defparam \z80_|execute_|fMWrite~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~21 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~21_combout = ((\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # (\z80_|execute_|ctl_alu_op_low~9_combout ))) # (!\z80_|execute_|fMWrite~11_combout ) - - .dataa(\z80_|execute_|fMWrite~11_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~21 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_alu_op_low~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N4 +// Location: LCCOMB_X21_Y12_N24 cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~22 ( // Equation(s): -// \z80_|execute_|ctl_alu_op_low~22_combout = ((\z80_|execute_|ctl_alu_op_low~21_combout ) # (!\z80_|execute_|ctl_alu_op1_sel_bus~10_combout )) # (!\z80_|execute_|ctl_alu_op_low~10_combout ) +// \z80_|execute_|ctl_alu_op_low~22_combout = (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ) - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op_low~10_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~21_combout ), + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), .cin(gnd), .combout(\z80_|execute_|ctl_alu_op_low~22_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~22 .lut_mask = 16'hFF3F; +defparam \z80_|execute_|ctl_alu_op_low~22 .lut_mask = 16'hAA00; defparam \z80_|execute_|ctl_alu_op_low~22 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y14_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~16 ( +// Location: LCCOMB_X26_Y16_N30 +cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_11 ( // Equation(s): -// \z80_|execute_|ctl_alu_op_low~16_combout = ((!\z80_|execute_|ixy_d~7_combout & ((\z80_|ir_|opcode [3]) # (!\z80_|execute_|ixy_d~6_combout )))) # (!\z80_|pla_decode_|Equal13~2_combout ) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|pla_decode_|Equal13~2_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~16 .lut_mask = 16'h7737; -defparam \z80_|execute_|ctl_alu_op_low~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~17 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~17_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~7_combout & (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & \z80_|execute_|ctl_alu_op_low~16_combout )) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), - .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_alu_op_low~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~17 .lut_mask = 16'h2200; -defparam \z80_|execute_|ctl_alu_op_low~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout = (!\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal44~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T4_ff~q ))) - - .dataa(\z80_|pla_decode_|Equal33~0_combout ), - .datab(\z80_|pla_decode_|Equal44~0_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel~36 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel~36_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|sequencer_|DFFE_T4_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|pla_decode_|Equal52~0_combout ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel~36 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_gp_sel~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~4_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout & (\z80_|execute_|ctl_state_alu~8_combout & (!\z80_|execute_|ctl_reg_gp_sel~36_combout & \z80_|execute_|ctl_alu_op2_sel_bus~9_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), - .datab(\z80_|execute_|ctl_state_alu~8_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel~36_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~4 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~5 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~5_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ) +// \z80_|resets_|SYNTHESIZED_WIRE_11~combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T2_ff~q ) .dataa(gnd), .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~5 .lut_mask = 16'h0F00; -defparam \z80_|execute_|ctl_state_alu~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~18 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~18_combout = (\z80_|execute_|ctl_mWrite~3_combout & ((\z80_|pla_decode_|Equal56~0_combout ) # ((\z80_|execute_|ctl_alu_op_low~11_combout )))) # (!\z80_|execute_|ctl_mWrite~3_combout & -// (\z80_|execute_|ctl_state_alu~5_combout & ((\z80_|pla_decode_|Equal56~0_combout ) # (\z80_|execute_|ctl_alu_op_low~11_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~3_combout ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|execute_|ctl_state_alu~5_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~18 .lut_mask = 16'hFAC8; -defparam \z80_|execute_|ctl_alu_op_low~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~19 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~19_combout = ((\z80_|execute_|ctl_alu_op_low~14_combout ) # ((\z80_|execute_|ctl_alu_op_low~18_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~38_combout ))) # (!\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~19 .lut_mask = 16'hFFDF; -defparam \z80_|execute_|ctl_alu_op_low~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~33 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~33_combout = (((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|execute_|ctl_alu_op_low~12_combout ) - - .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~33 .lut_mask = 16'h77F7; -defparam \z80_|execute_|ctl_alu_op_low~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~20 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~20_combout = (\z80_|execute_|ctl_alu_op_low~19_combout ) # (!\z80_|execute_|ctl_alu_op_low~33_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_op_low~19_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~33_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~20 .lut_mask = 16'hF0FF; -defparam \z80_|execute_|ctl_alu_op_low~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~23 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~23_combout = (\z80_|execute_|ctl_mRead~36_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout )))) # (!\z80_|execute_|ctl_mRead~36_combout & (\z80_|execute_|ixy_d~5_combout & -// ((\z80_|pla_decode_|Equal39~0_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~36_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~23 .lut_mask = 16'hECA8; -defparam \z80_|execute_|ctl_alu_op_low~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~24 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~24_combout = (\z80_|execute_|ctl_alu_op_low~22_combout ) # (((\z80_|execute_|ctl_alu_op_low~20_combout ) # (\z80_|execute_|ctl_alu_op_low~23_combout )) # (!\z80_|execute_|ctl_alu_op_low~17_combout )) - - .dataa(\z80_|execute_|ctl_alu_op_low~22_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~20_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~23_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~24 .lut_mask = 16'hFFFB; -defparam \z80_|execute_|ctl_alu_op_low~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~25 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~25_combout = (\z80_|execute_|ixy_d~9_combout & (((\z80_|pla_decode_|Equal40~1_combout ) # (\z80_|pla_decode_|Equal39~0_combout )))) # (!\z80_|execute_|ixy_d~9_combout & (\z80_|execute_|ixy_d~5_combout & -// (\z80_|pla_decode_|Equal40~1_combout ))) - - .dataa(\z80_|execute_|ixy_d~9_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|pla_decode_|Equal40~1_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~25 .lut_mask = 16'hEAE0; -defparam \z80_|execute_|ctl_alu_op_low~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~34 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~34_combout = (\z80_|execute_|ctl_alu_op_low~25_combout ) # ((\z80_|pla_decode_|Equal21~1_combout & (\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ))) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|ctl_alu_op_low~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~34 .lut_mask = 16'hFF08; -defparam \z80_|execute_|ctl_alu_op_low~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~combout = ((\z80_|execute_|ctl_alu_op_low~24_combout ) # ((\z80_|execute_|ctl_alu_op_low~34_combout ) # (\z80_|execute_|ctl_alu_op_low~26_combout ))) # (!\z80_|execute_|ctl_alu_op_low~15_combout ) - - .dataa(\z80_|execute_|ctl_alu_op_low~15_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~24_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~34_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~26_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_alu_op_low .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~40 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~40_combout = ((\z80_|execute_|ixy_d~9_combout & ((\z80_|execute_|ctl_mRead~26_combout ) # (\z80_|execute_|ctl_mRead~27_combout )))) # (!\z80_|execute_|ctl_flags_xy_we~18_combout ) - - .dataa(\z80_|execute_|ctl_mRead~26_combout ), - .datab(\z80_|execute_|ctl_mRead~27_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~18_combout ), - .datad(\z80_|execute_|ixy_d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~40 .lut_mask = 16'hEF0F; -defparam \z80_|execute_|ctl_alu_shift_oe~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~37 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~37_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_alu_oe~3_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) - - .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~37 .lut_mask = 16'hAE00; -defparam \z80_|execute_|ctl_alu_shift_oe~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~39 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~39_combout = (\z80_|execute_|ctl_alu_shift_oe~37_combout ) # (((\z80_|execute_|ctl_state_alu~14_combout & \z80_|execute_|ctl_alu_shift_oe~14_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~5_combout )) - - .dataa(\z80_|execute_|ctl_state_alu~14_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~37_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~39 .lut_mask = 16'hECFF; -defparam \z80_|execute_|ctl_alu_shift_oe~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~46 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~46_combout = (\z80_|execute_|ctl_alu_shift_oe~41_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|pla_decode_|Equal48~0_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~41_combout ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|pla_decode_|Equal48~0_combout ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), .datad(\z80_|sequencer_|DFFE_M1_ff~q ), .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~46_combout ), + .combout(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~46 .lut_mask = 16'hAA2A; -defparam \z80_|execute_|ctl_alu_shift_oe~46 .sum_lutc_input = "datac"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_11 .lut_mask = 16'hFF0F; +defparam \z80_|resets_|SYNTHESIZED_WIRE_11 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X40_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~42 ( +// Location: LCCOMB_X31_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~4 ( // Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~42_combout = (\z80_|execute_|ctl_alu_shift_oe~40_combout ) # (((\z80_|execute_|ctl_alu_shift_oe~39_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~46_combout )) # (!\z80_|execute_|ctl_alu_op_low~17_combout )) +// \z80_|execute_|ctl_ir_we~4_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M4_ff~q ) - .dataa(\z80_|execute_|ctl_alu_shift_oe~40_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~39_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~46_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~42 .lut_mask = 16'hFBFF; -defparam \z80_|execute_|ctl_alu_shift_oe~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~21 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~21_combout = (\z80_|execute_|ctl_ir_we~15_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # ((\z80_|execute_|ctl_state_alu~6_combout & !\z80_|execute_|ctl_ir_we~4_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~6_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_ir_we~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~21 .lut_mask = 16'hF200; -defparam \z80_|execute_|ctl_alu_shift_oe~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~45 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~45_combout = (\z80_|execute_|ctl_alu_shift_oe~21_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|execute_|ctl_alu_shift_oe~21_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|ctl_ir_we~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~45 .lut_mask = 16'hC4CC; -defparam \z80_|execute_|ctl_alu_shift_oe~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~22 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~22_combout = (\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_state_alu~6_combout ) # (\z80_|execute_|ctl_alu_shift_oe~45_combout )))) # -// (!\z80_|execute_|ctl_ir_we~9_combout & (((\z80_|execute_|ctl_alu_shift_oe~45_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~6_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_ir_we~9_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~45_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~22 .lut_mask = 16'h3F20; -defparam \z80_|execute_|ctl_alu_shift_oe~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~23 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~23_combout = (\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # (\z80_|execute_|ctl_alu_shift_oe~22_combout )))) # -// (!\z80_|execute_|ctl_ir_we~9_combout & (((\z80_|execute_|ctl_alu_shift_oe~22_combout )))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~22_combout ), - .datac(\z80_|execute_|ctl_ir_we~9_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~23 .lut_mask = 16'h0CEC; -defparam \z80_|execute_|ctl_alu_shift_oe~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~24 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~24_combout = (\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_mWrite~7_combout ) # (\z80_|execute_|ctl_alu_shift_oe~23_combout )))) # -// (!\z80_|execute_|ctl_ir_we~12_combout & (((\z80_|execute_|ctl_alu_shift_oe~23_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~7_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~23_combout ), - .datad(\z80_|execute_|ctl_ir_we~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~24 .lut_mask = 16'h32F0; -defparam \z80_|execute_|ctl_alu_shift_oe~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~25 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~25_combout = (\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|execute_|ctl_alu_shift_oe~24_combout ) # (\z80_|execute_|ctl_mWrite~3_combout )))) # -// (!\z80_|execute_|ctl_ir_we~12_combout & (\z80_|execute_|ctl_alu_shift_oe~24_combout )) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~24_combout ), - .datab(\z80_|execute_|ctl_ir_we~12_combout ), - .datac(\z80_|execute_|ctl_mWrite~3_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~25 .lut_mask = 16'h22EA; -defparam \z80_|execute_|ctl_alu_shift_oe~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~14_combout = (\z80_|execute_|ctl_ir_we~11_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # ((\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~14 .lut_mask = 16'hC0C8; -defparam \z80_|execute_|ctl_alu_bs_oe~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~26 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~26_combout = (!\z80_|execute_|ctl_alu_bs_oe~14_combout & ((\z80_|execute_|ctl_alu_shift_oe~25_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout & \z80_|execute_|ctl_mWrite~7_combout )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~25_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_mWrite~7_combout ), - .datad(\z80_|execute_|ctl_alu_bs_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~26 .lut_mask = 16'h00EA; -defparam \z80_|execute_|ctl_alu_shift_oe~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~27 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~27_combout = (\z80_|execute_|ctl_ir_we~7_combout & ((\z80_|execute_|ctl_state_alu~6_combout ) # ((\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ctl_bus_db_oe~1_combout )))) # (!\z80_|execute_|ctl_ir_we~7_combout & -// (\z80_|execute_|ixy_d~7_combout & ((!\z80_|execute_|ctl_bus_db_oe~1_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~27 .lut_mask = 16'hA0EC; -defparam \z80_|execute_|ctl_alu_shift_oe~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~28 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~28_combout = ((\z80_|execute_|ctl_alu_shift_oe~27_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~20_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~44_combout ) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~44_combout ), + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), .datab(gnd), - .datac(\z80_|execute_|ctl_alu_shift_oe~20_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~27_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~28 .lut_mask = 16'hFF5F; -defparam \z80_|execute_|ctl_alu_shift_oe~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~10_combout = (\z80_|execute_|ctl_ir_we~7_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) # (!\z80_|execute_|ctl_ir_we~7_combout & (\z80_|execute_|ctl_ir_we~4_combout -// & (\z80_|execute_|ctl_ir_we~10_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_ir_we~10_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~10 .lut_mask = 16'hEAC8; -defparam \z80_|execute_|ctl_alu_bs_oe~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~11_combout = (\z80_|execute_|ctl_alu_bs_oe~10_combout ) # ((\z80_|execute_|ctl_alu_bs_oe~14_combout ) # ((!\z80_|execute_|ctl_alu_bs_oe~8_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~9_combout ))) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~10_combout ), - .datab(\z80_|execute_|ctl_alu_bs_oe~14_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~9_combout ), - .datad(\z80_|execute_|ctl_alu_bs_oe~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~11 .lut_mask = 16'hEFFF; -defparam \z80_|execute_|ctl_alu_bs_oe~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~32 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~32_combout = (!\z80_|execute_|ctl_alu_bs_oe~11_combout & ((\z80_|execute_|ctl_alu_shift_oe~28_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~31_combout ))) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_shift_oe~28_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~31_combout ), - .datad(\z80_|execute_|ctl_alu_bs_oe~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~32 .lut_mask = 16'h00CF; -defparam \z80_|execute_|ctl_alu_shift_oe~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~33 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~33_combout = (\z80_|execute_|ctl_alu_shift_oe~32_combout ) # ((!\z80_|execute_|ctl_alu_bs_oe~combout & ((\z80_|execute_|ctl_alu_shift_oe~16_combout ) # (!\z80_|execute_|ctl_alu_op_low~15_combout )))) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datab(\z80_|execute_|ctl_alu_op_low~15_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~16_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~33 .lut_mask = 16'hFF51; -defparam \z80_|execute_|ctl_alu_shift_oe~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~0_combout = ((!\z80_|execute_|ctl_alu_op_low~12_combout & (!\z80_|execute_|ctl_alu_op_low~11_combout & !\z80_|pla_decode_|Equal56~0_combout ))) # (!\z80_|execute_|ctl_state_alu~5_combout ) - - .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~11_combout ), - .datac(\z80_|execute_|ctl_state_alu~5_combout ), - .datad(\z80_|pla_decode_|Equal56~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~0 .lut_mask = 16'h0F1F; -defparam \z80_|execute_|ctl_reg_use_sp~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~1 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~1_combout = (\z80_|execute_|ctl_reg_use_sp~0_combout & \z80_|execute_|nextM~11_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_use_sp~0_combout ), .datac(gnd), - .datad(\z80_|execute_|nextM~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~1 .lut_mask = 16'hCC00; -defparam \z80_|execute_|ctl_reg_use_sp~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~12 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~12_combout = (\z80_|execute_|ctl_alu_bs_oe~14_combout ) # ((!\z80_|execute_|ctl_alu_bs_oe~8_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~9_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_bs_oe~14_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~9_combout ), - .datad(\z80_|execute_|ctl_alu_bs_oe~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~12 .lut_mask = 16'hCFFF; -defparam \z80_|execute_|ctl_alu_bs_oe~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~47 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~47_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|sequencer_|DFFE_M1_ff~q & \z80_|execute_|ctl_ir_we~7_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|ctl_ir_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~47 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_shift_oe~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~34 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~34_combout = (\z80_|execute_|ctl_ir_we~10_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_state_alu~6_combout ) # (\z80_|execute_|ctl_alu_shift_oe~47_combout )))) # -// (!\z80_|execute_|ctl_ir_we~10_combout & (((\z80_|execute_|ctl_alu_shift_oe~47_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~6_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_ir_we~10_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~47_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~34 .lut_mask = 16'h3F20; -defparam \z80_|execute_|ctl_alu_shift_oe~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~35 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~35_combout = (!\z80_|execute_|ctl_alu_bs_oe~12_combout & ((\z80_|execute_|ctl_alu_shift_oe~34_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & \z80_|execute_|ctl_ir_we~10_combout )))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|ctl_ir_we~10_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~12_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~34_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~35 .lut_mask = 16'h0F08; -defparam \z80_|execute_|ctl_alu_shift_oe~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~36 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~36_combout = (((\z80_|execute_|ctl_alu_shift_oe~35_combout ) # (!\z80_|execute_|ctl_reg_use_sp~1_combout )) # (!\z80_|execute_|ctl_flags_bus~12_combout )) # (!\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ), - .datab(\z80_|execute_|ctl_flags_bus~12_combout ), - .datac(\z80_|execute_|ctl_reg_use_sp~1_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~35_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~36 .lut_mask = 16'hFF7F; -defparam \z80_|execute_|ctl_alu_shift_oe~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~43 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~43_combout = (\z80_|execute_|ctl_alu_shift_oe~42_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~26_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~33_combout ) # (\z80_|execute_|ctl_alu_shift_oe~36_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~42_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~26_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~33_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~43 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_alu_shift_oe~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_lo~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_lo~9_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q ))) # (!\z80_|pla_decode_|Equal47~0_combout ) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|M5~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_lo~9 .lut_mask = 16'hF5F7; -defparam \z80_|execute_|ctl_reg_in_lo~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_oe~0_combout = ((\z80_|execute_|ctl_66_oe~2_combout ) # ((\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_alu_shift_oe~14_combout ))) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ) - - .dataa(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datab(\z80_|execute_|ctl_66_oe~2_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_oe~0 .lut_mask = 16'hFDDD; -defparam \z80_|execute_|ctl_alu_op1_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout = (\z80_|pla_decode_|Equal48~0_combout & (\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )) - - .dataa(\z80_|pla_decode_|Equal48~0_combout ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 .lut_mask = 16'h0088; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_oe~1 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_oe~1_combout = (\z80_|execute_|ctl_alu_op1_oe~0_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ) # ((\z80_|execute_|ctl_alu_oe~3_combout & \z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_alu_op1_oe~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_oe~1 .lut_mask = 16'hFFF8; -defparam \z80_|execute_|ctl_alu_op1_oe~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~8_combout = (((!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4])) # (!\z80_|pla_decode_|Equal63~0_combout )) # (!\z80_|nM1_int~2_combout ) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal63~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~8 .lut_mask = 16'h777F; -defparam \z80_|execute_|ctl_flags_xy_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~9_combout = (!\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout & (\z80_|execute_|ctl_flags_xy_we~8_combout & ((!\z80_|sequencer_|DFFE_T5_ff~q ) # (!\z80_|execute_|ixy_d~15_combout )))) - - .dataa(\z80_|execute_|ixy_d~15_combout ), - .datab(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .datac(\z80_|sequencer_|DFFE_T5_ff~q ), - .datad(\z80_|execute_|ctl_flags_xy_we~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~9 .lut_mask = 16'h1300; -defparam \z80_|execute_|ctl_flags_xy_we~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N18 -cycloneive_lcell_comb \z80_|pla_decode_|Equal8~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal8~0_combout = (\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [2] & \z80_|ir_|opcode [0])) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [1]), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal8~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal8~0 .lut_mask = 16'h0C00; -defparam \z80_|pla_decode_|Equal8~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~9_combout = (((!\z80_|nM1_int~2_combout & !\z80_|execute_|ixy_d~6_combout )) # (!\z80_|execute_|ctl_mWrite~2_combout )) # (!\z80_|pla_decode_|Equal8~0_combout ) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal8~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~2_combout ), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~9 .lut_mask = 16'h3F7F; -defparam \z80_|execute_|ctl_flags_alu~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~4_combout = ((!\z80_|pla_decode_|Equal40~1_combout & (!\z80_|pla_decode_|Equal39~0_combout & !\z80_|pla_decode_|Equal21~1_combout ))) # (!\z80_|execute_|ixy_d~8_combout ) - - .dataa(\z80_|pla_decode_|Equal40~1_combout ), - .datab(\z80_|pla_decode_|Equal39~0_combout ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|execute_|ixy_d~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~4 .lut_mask = 16'h01FF; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~3_combout = (\z80_|pla_decode_|Equal21~1_combout & (!\z80_|execute_|ctl_mRead~11_combout & ((!\z80_|pla_decode_|Equal10~0_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) # (!\z80_|pla_decode_|Equal21~1_combout & -// (((!\z80_|pla_decode_|Equal10~0_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|execute_|ctl_mRead~11_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|pla_decode_|Equal10~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~3 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_flags_sz_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal11~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal11~1_combout = (!\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [0]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal11~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal11~1 .lut_mask = 16'h000F; -defparam \z80_|pla_decode_|Equal11~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout = (\z80_|execute_|ixy_d~7_combout & (\z80_|execute_|ctl_mWrite~2_combout & (!\z80_|ir_|opcode [2] & \z80_|pla_decode_|Equal11~1_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|pla_decode_|Equal11~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~10_combout = (\z80_|execute_|ctl_flags_alu~9_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~4_combout & (\z80_|execute_|ctl_flags_sz_we~3_combout & !\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ))) - - .dataa(\z80_|execute_|ctl_flags_alu~9_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), - .datac(\z80_|execute_|ctl_flags_sz_we~3_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~10 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_flags_alu~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~11_combout = (\z80_|execute_|ctl_flags_xy_we~9_combout & (\z80_|execute_|ctl_flags_alu~10_combout & ((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|execute_|ixy_d~15_combout )))) - - .dataa(\z80_|execute_|ixy_d~15_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~9_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|execute_|ctl_flags_alu~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~11 .lut_mask = 16'h4C00; -defparam \z80_|execute_|ctl_flags_alu~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout = (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal63~0_combout & (!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4]))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal63~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 .lut_mask = 16'h0008; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla82M1T1_16 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout = (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [0] & (\z80_|nM1_int~2_combout & \z80_|pla_decode_|Equal3~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal3~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel_pla82M1T1_16 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_pf_sel_pla82M1T1_16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~13 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~13_combout = (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|execute_|ctl_mRead~6_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|execute_|ctl_mRead~6_combout ), .datad(\z80_|sequencer_|DFFE_M4_ff~q ), .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~13_combout ), + .combout(\z80_|execute_|ctl_ir_we~4_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~13 .lut_mask = 16'h3F7F; -defparam \z80_|execute_|ctl_flags_use_cf2~13 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_ir_we~4 .lut_mask = 16'h5500; +defparam \z80_|execute_|ctl_ir_we~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~7 ( +// Location: LCCOMB_X26_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_state_iy_set~2 ( // Equation(s): -// \z80_|execute_|ctl_flags_cf_we~7_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # (((!\z80_|pla_decode_|Equal55~0_combout ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|pla_decode_|Equal13~0_combout )) +// \z80_|execute_|ctl_state_iy_set~2_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal3~2_combout ))) - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|pla_decode_|Equal55~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~7 .lut_mask = 16'hBFFF; -defparam \z80_|execute_|ctl_flags_cf_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel[0]~2 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel[0]~2_combout = (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (\z80_|execute_|ctl_flags_use_cf2~13_combout & \z80_|execute_|ctl_flags_cf_we~7_combout )) - - .dataa(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .datab(\z80_|execute_|ctl_flags_use_cf2~13_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_flags_cf_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel[0]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel[0]~2 .lut_mask = 16'h4400; -defparam \z80_|execute_|ctl_pf_sel[0]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~2 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~2_combout = (\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_T1_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~2 .lut_mask = 16'h00F0; -defparam \z80_|execute_|ctl_alu_oe~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~25 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~25_combout = (\z80_|execute_|ctl_ir_we~14_combout & (!\z80_|execute_|ixy_d~7_combout & ((!\z80_|execute_|ctl_alu_oe~2_combout )))) # (!\z80_|execute_|ctl_ir_we~14_combout & (((!\z80_|execute_|ctl_alu_oe~2_combout ) # -// (!\z80_|execute_|ctl_ir_we~8_combout )))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_ir_we~14_combout ), - .datac(\z80_|execute_|ctl_ir_we~8_combout ), - .datad(\z80_|execute_|ctl_alu_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~25 .lut_mask = 16'h0377; -defparam \z80_|execute_|ctl_bus_inc_oe~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_we~5_combout = (\z80_|execute_|ctl_bus_inc_oe~25_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|execute_|ctl_ir_we~8_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|execute_|ctl_bus_inc_oe~25_combout ), - .datac(\z80_|execute_|ctl_ir_we~8_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_we~5 .lut_mask = 16'hCC8C; -defparam \z80_|execute_|ctl_flags_hf_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~10_combout = (\z80_|execute_|ctl_flags_hf_we~5_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|pla_decode_|Equal13~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(\z80_|execute_|ctl_flags_hf_we~5_combout ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~10 .lut_mask = 16'hCCC4; -defparam \z80_|execute_|ctl_flags_pf_we~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~48 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~48_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|execute_|ctl_alu_op_low~13_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~13_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~48 .lut_mask = 16'h3331; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~2_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout & (\z80_|execute_|ctl_pf_sel[0]~2_combout & (\z80_|execute_|ctl_flags_pf_we~10_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .datab(\z80_|execute_|ctl_pf_sel[0]~2_combout ), - .datac(\z80_|execute_|ctl_flags_pf_we~10_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~2 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_flags_pf_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~3_combout = (\z80_|execute_|ctl_flags_pf_we~2_combout & (((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_ir_we~12_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_flags_pf_we~2_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_ir_we~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~3 .lut_mask = 16'h0A2A; -defparam \z80_|execute_|ctl_flags_pf_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y19_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~17 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~17_combout = (((!\z80_|pla_decode_|Equal13~0_combout ) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|pla_decode_|Equal55~0_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~17 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_flags_xy_we~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N6 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~5 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~5_combout = ((!\z80_|pla_decode_|Equal40~1_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal39~0_combout ))) # (!\z80_|execute_|ixy_d~6_combout ) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|pla_decode_|Equal40~1_combout ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~5 .lut_mask = 16'h5557; -defparam \z80_|reg_control_|reg_sys_we_lo~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N26 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~6 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~6_combout = (\z80_|execute_|ctl_flags_xy_we~17_combout & (\z80_|reg_control_|reg_sys_we_lo~5_combout & ((!\z80_|execute_|ctl_alu_op_low~8_combout ) # (!\z80_|pla_decode_|Equal56~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal56~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~17_combout ), - .datad(\z80_|reg_control_|reg_sys_we_lo~5_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~6 .lut_mask = 16'h7000; -defparam \z80_|reg_control_|reg_sys_we_lo~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~10_combout = (\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ixy_d~7_combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) # (!\z80_|pla_decode_|Equal56~0_combout & -// (((!\z80_|nM1_int~2_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal56~0_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|pla_decode_|Equal20~0_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~10 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_flags_xy_we~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout = (\z80_|execute_|ctl_mWrite~2_combout & (\z80_|execute_|ctl_state_alu~4_combout & (\z80_|pla_decode_|Equal2~0_combout & !\z80_|ir_|opcode [0]))) - - .dataa(\z80_|execute_|ctl_mWrite~2_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|pla_decode_|Equal2~0_combout ), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~7 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~7_combout = (\z80_|ir_|opcode [7] & (!\z80_|pla_decode_|Equal33~0_combout & (!\z80_|ir_|opcode [6] & !\z80_|decode_state_|table_xx~0_combout ))) - - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|ir_|opcode [6]), - .datad(\z80_|decode_state_|table_xx~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~7 .lut_mask = 16'h0002; -defparam \z80_|execute_|ctl_state_alu~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~1 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~1_combout = ((!\z80_|execute_|ctl_state_alu~14_combout & (!\z80_|execute_|ctl_state_alu~7_combout & !\z80_|pla_decode_|Equal52~1_combout ))) # (!\z80_|nM1_int~2_combout ) - - .dataa(\z80_|execute_|ctl_state_alu~14_combout ), - .datab(\z80_|execute_|ctl_state_alu~7_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal52~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~1 .lut_mask = 16'h0F1F; -defparam \z80_|execute_|ctl_flags_sz_we~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~2_combout = (\z80_|reg_control_|reg_sys_we_lo~6_combout & (\z80_|execute_|ctl_flags_xy_we~10_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout & \z80_|execute_|ctl_flags_sz_we~1_combout ))) - - .dataa(\z80_|reg_control_|reg_sys_we_lo~6_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~10_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), - .datad(\z80_|execute_|ctl_flags_sz_we~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~2 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_flags_cf_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~6_combout = (\z80_|nM1_int~2_combout & (!\z80_|execute_|ctl_ir_we~9_combout & ((!\z80_|execute_|ctl_mWrite~3_combout ) # (!\z80_|execute_|ctl_ir_we~15_combout )))) # (!\z80_|nM1_int~2_combout & -// (((!\z80_|execute_|ctl_mWrite~3_combout )) # (!\z80_|execute_|ctl_ir_we~15_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_ir_we~9_combout ), - .datad(\z80_|execute_|ctl_mWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~6 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_alu_core_S~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~7 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~7_combout = (\z80_|execute_|ctl_alu_core_S~6_combout & (((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_alu_oe~2_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~9_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_alu_core_S~6_combout ), - .datad(\z80_|execute_|ctl_alu_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~7 .lut_mask = 16'h10F0; -defparam \z80_|execute_|ctl_alu_core_S~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~4_combout = (\z80_|execute_|ctl_ir_we~7_combout & (!\z80_|execute_|ctl_mWrite~3_combout & ((!\z80_|execute_|ctl_ir_we~10_combout ) # (!\z80_|nM1_int~2_combout )))) # (!\z80_|execute_|ctl_ir_we~7_combout & -// (((!\z80_|execute_|ctl_ir_we~10_combout ) # (!\z80_|nM1_int~2_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_mWrite~3_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_ir_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~4 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_alu_core_S~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~5_combout = (\z80_|execute_|ctl_alu_core_S~4_combout & (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~7_combout )) # (!\z80_|execute_|ctl_alu_oe~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_S~4_combout ), - .datab(\z80_|execute_|ctl_ir_we~10_combout ), - .datac(\z80_|execute_|ctl_ir_we~7_combout ), - .datad(\z80_|execute_|ctl_alu_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~5 .lut_mask = 16'h02AA; -defparam \z80_|execute_|ctl_alu_core_S~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout = (\z80_|execute_|ctl_mWrite~2_combout & (\z80_|pla_decode_|Equal8~0_combout & (\z80_|sequencer_|DFFE_T5_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ))) - - .dataa(\z80_|execute_|ctl_mWrite~2_combout ), - .datab(\z80_|pla_decode_|Equal8~0_combout ), - .datac(\z80_|sequencer_|DFFE_T5_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_alu_res_oe~0_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout & (((!\z80_|pla_decode_|Equal69~0_combout & !\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal69~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_res_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_res_oe~0 .lut_mask = 16'h0133; -defparam \z80_|execute_|ctl_alu_res_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~15 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~15_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_mWrite~2_combout & !\z80_|sequencer_|DFFE_M1_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~2_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~15 .lut_mask = 16'h0040; -defparam \z80_|execute_|ctl_alu_oe~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~1 ( -// Equation(s): -// \z80_|execute_|ctl_alu_res_oe~1_combout = (\z80_|execute_|ctl_alu_core_S~7_combout & (\z80_|execute_|ctl_alu_core_S~5_combout & (\z80_|execute_|ctl_alu_res_oe~0_combout & !\z80_|execute_|ctl_alu_oe~15_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_S~7_combout ), - .datab(\z80_|execute_|ctl_alu_core_S~5_combout ), - .datac(\z80_|execute_|ctl_alu_res_oe~0_combout ), - .datad(\z80_|execute_|ctl_alu_oe~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_res_oe~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_res_oe~1 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_alu_res_oe~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~2 ( -// Equation(s): -// \z80_|execute_|ctl_alu_res_oe~2_combout = (\z80_|execute_|ctl_flags_alu~11_combout & (\z80_|execute_|ctl_flags_pf_we~3_combout & (\z80_|execute_|ctl_flags_cf_we~2_combout & \z80_|execute_|ctl_alu_res_oe~1_combout ))) - - .dataa(\z80_|execute_|ctl_flags_alu~11_combout ), - .datab(\z80_|execute_|ctl_flags_pf_we~3_combout ), - .datac(\z80_|execute_|ctl_flags_cf_we~2_combout ), - .datad(\z80_|execute_|ctl_alu_res_oe~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_res_oe~2 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_res_oe~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_oe~0_combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # ((!\z80_|ir_|opcode [3] & \z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|pla_decode_|Equal13~2_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_oe~0 .lut_mask = 16'h8C88; -defparam \z80_|execute_|ctl_alu_op2_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N4 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~2 ( -// Equation(s): -// \z80_|alu_|db_high[3]~2_combout = (\z80_|execute_|ctl_alu_bs_oe~combout ) # ((\z80_|execute_|ctl_alu_op1_oe~1_combout ) # ((\z80_|execute_|ctl_alu_op2_oe~0_combout ) # (!\z80_|execute_|ctl_alu_res_oe~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~2 .lut_mask = 16'hFFEF; -defparam \z80_|alu_|db_high[3]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N0 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~3 ( -// Equation(s): -// \z80_|alu_|db_high[3]~3_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout ) # (\z80_|alu_|db_high[3]~2_combout ) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datab(gnd), - .datac(\z80_|alu_|db_high[3]~2_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~3 .lut_mask = 16'hFAFA; -defparam \z80_|alu_|db_high[3]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N20 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~24 ( -// Equation(s): -// \z80_|alu_|db_low[2]~24_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout & (\z80_|alu_|db_low[2]~3_combout & (\z80_|alu_|db_low[2]~6_combout ))) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout & (((\z80_|alu_|db_low[2]~3_combout & -// \z80_|alu_|db_low[2]~6_combout )) # (!\z80_|alu_|db_high[3]~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datab(\z80_|alu_|db_low[2]~3_combout ), - .datac(\z80_|alu_|db_low[2]~6_combout ), - .datad(\z80_|alu_|db_high[3]~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~24 .lut_mask = 16'hC0D5; -defparam \z80_|alu_|db_low[2]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N24 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~7 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~7_combout = (\z80_|reg_control_|reg_sys_we_lo~6_combout & ((!\z80_|execute_|ixy_d~15_combout ) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(\z80_|reg_control_|reg_sys_we_lo~6_combout ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~7 .lut_mask = 16'h0AAA; -defparam \z80_|reg_control_|reg_sys_we_lo~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout = (!\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|nM1_int~2_combout & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|pla_decode_|Equal3~1_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~19 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout = ((!\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_ir_we~8_combout & !\z80_|execute_|ctl_ir_we~10_combout ))) # (!\z80_|nM1_int~2_combout ) - - .dataa(\z80_|execute_|ctl_ir_we~9_combout ), - .datab(\z80_|execute_|ctl_ir_we~8_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_ir_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~19 .lut_mask = 16'h0F1F; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~8_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout & (\z80_|execute_|ctl_flags_sz_we~1_combout & (!\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout & \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~1_combout ), - .datac(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~8 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_reg_in_hi~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~8_combout = (\z80_|reg_control_|reg_sys_we_lo~7_combout & (\z80_|execute_|ctl_reg_in_hi~8_combout & ((!\z80_|execute_|ctl_ir_we~4_combout ) # (!\z80_|pla_decode_|Equal13~2_combout )))) - - .dataa(\z80_|reg_control_|reg_sys_we_lo~7_combout ), - .datab(\z80_|pla_decode_|Equal13~2_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~8 .lut_mask = 16'h2A00; -defparam \z80_|execute_|ctl_alu_oe~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~4_combout = ((!\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_alu_op_low~12_combout & !\z80_|execute_|ctl_alu_op_low~11_combout ))) # (!\z80_|execute_|ixy_d~7_combout ) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~12_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~4 .lut_mask = 16'h5557; -defparam \z80_|execute_|ctl_alu_oe~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~9 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~9_combout = (\z80_|execute_|ctl_flags_use_cf2~13_combout & (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_mWrite~3_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_flags_use_cf2~13_combout ), - .datad(\z80_|execute_|ctl_mWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~9 .lut_mask = 16'h10F0; -defparam \z80_|execute_|ctl_mWrite~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~10_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~9_combout ))) # (!\z80_|sequencer_|M5~q ) - - .dataa(\z80_|sequencer_|M5~q ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_ir_we~9_combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~10 .lut_mask = 16'hFF57; -defparam \z80_|execute_|ctl_alu_core_S~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~43 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~43_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~7_combout ))) # (!\z80_|sequencer_|M5~q ) - - .dataa(\z80_|sequencer_|M5~q ), - .datab(\z80_|execute_|ctl_ir_we~10_combout ), - .datac(\z80_|execute_|ctl_ir_we~7_combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~43 .lut_mask = 16'hFF57; -defparam \z80_|execute_|ctl_bus_inc_oe~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~26 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~26_combout = (\z80_|execute_|ctl_alu_core_S~10_combout & (\z80_|execute_|ctl_bus_inc_oe~43_combout & \z80_|execute_|ctl_bus_inc_oe~25_combout )) - - .dataa(\z80_|execute_|ctl_alu_core_S~10_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~26 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_bus_inc_oe~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_we~5_combout = (\z80_|execute_|ctl_mWrite~9_combout & (\z80_|execute_|ctl_bus_inc_oe~26_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|execute_|ctl_mRead~26_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~9_combout ), - .datab(\z80_|execute_|ctl_mRead~26_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~26_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~5 .lut_mask = 16'h20A0; -defparam \z80_|execute_|ctl_bus_db_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~9_combout = (\z80_|execute_|ctl_alu_oe~8_combout & (\z80_|execute_|ctl_alu_oe~4_combout & (\z80_|execute_|ctl_reg_in_lo~9_combout & \z80_|execute_|ctl_bus_db_we~5_combout ))) - - .dataa(\z80_|execute_|ctl_alu_oe~8_combout ), - .datab(\z80_|execute_|ctl_alu_oe~4_combout ), - .datac(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datad(\z80_|execute_|ctl_bus_db_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~9 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_oe~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~11_combout = (\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_alu_oe~3_combout ) # ((\z80_|pla_decode_|Equal69~0_combout ) # (\z80_|execute_|ctl_mWrite~16_combout )))) - - .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), - .datab(\z80_|pla_decode_|Equal69~0_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_mWrite~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~11 .lut_mask = 16'hF0E0; -defparam \z80_|execute_|ctl_alu_oe~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~5_combout = (\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|execute_|ctl_mWrite~16_combout & ((!\z80_|execute_|ctl_mRead~11_combout ) # (!\z80_|execute_|ctl_mRead~36_combout )))) # (!\z80_|execute_|ctl_state_alu~4_combout & -// (((!\z80_|execute_|ctl_mRead~11_combout ) # (!\z80_|execute_|ctl_mRead~36_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_mWrite~16_combout ), - .datac(\z80_|execute_|ctl_mRead~36_combout ), - .datad(\z80_|execute_|ctl_mRead~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~5 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_alu_oe~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~11_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_ir_we~12_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~11_combout ), - .datab(\z80_|execute_|ctl_ir_we~12_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~11 .lut_mask = 16'hFFF1; -defparam \z80_|execute_|ctl_alu_core_S~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~6_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout & (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal20~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~6 .lut_mask = 16'h0013; -defparam \z80_|execute_|ctl_alu_oe~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~7 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~7_combout = (\z80_|execute_|ctl_alu_oe~6_combout & (((!\z80_|execute_|ctl_mRead~27_combout & !\z80_|execute_|ctl_mRead~26_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_mRead~27_combout ), - .datac(\z80_|execute_|ctl_mRead~26_combout ), - .datad(\z80_|execute_|ctl_alu_oe~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~7 .lut_mask = 16'h5700; -defparam \z80_|execute_|ctl_alu_oe~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~12 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~12_combout = (\z80_|execute_|ctl_alu_oe~11_combout ) # (((!\z80_|execute_|ctl_alu_oe~7_combout ) # (!\z80_|execute_|ctl_alu_core_S~11_combout )) # (!\z80_|execute_|ctl_alu_oe~5_combout )) - - .dataa(\z80_|execute_|ctl_alu_oe~11_combout ), - .datab(\z80_|execute_|ctl_alu_oe~5_combout ), - .datac(\z80_|execute_|ctl_alu_core_S~11_combout ), - .datad(\z80_|execute_|ctl_alu_oe~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~12 .lut_mask = 16'hBFFF; -defparam \z80_|execute_|ctl_alu_oe~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~13 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~13_combout = (\z80_|execute_|ctl_alu_oe~12_combout ) # (((\z80_|execute_|ctl_66_oe~2_combout ) # (!\z80_|execute_|ctl_flags_alu~10_combout )) # (!\z80_|execute_|ctl_flags_xy_we~9_combout )) - - .dataa(\z80_|execute_|ctl_alu_oe~12_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~9_combout ), - .datac(\z80_|execute_|ctl_66_oe~2_combout ), - .datad(\z80_|execute_|ctl_flags_alu~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~13 .lut_mask = 16'hFBFF; -defparam \z80_|execute_|ctl_alu_oe~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~14_combout = (\z80_|execute_|ctl_alu_oe~13_combout ) # (!\z80_|execute_|ctl_alu_oe~9_combout ) - - .dataa(\z80_|execute_|ctl_alu_oe~9_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_oe~13_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~14 .lut_mask = 16'hF5F5; -defparam \z80_|execute_|ctl_alu_oe~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~24 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~24_combout = (\z80_|execute_|ctl_flags_xy_we~12_combout & (((!\z80_|pla_decode_|Equal48~0_combout & !\z80_|pla_decode_|Equal69~0_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|pla_decode_|Equal48~0_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~12_combout ), - .datad(\z80_|pla_decode_|Equal69~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~24 .lut_mask = 16'h3070; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~27 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~27_combout = (\z80_|pla_decode_|Equal20~0_combout & (!\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ixy_d~6_combout ) # (!\z80_|execute_|ctl_mRead~26_combout )))) # (!\z80_|pla_decode_|Equal20~0_combout & -// (((!\z80_|execute_|ixy_d~6_combout )) # (!\z80_|execute_|ctl_mRead~26_combout ))) - - .dataa(\z80_|pla_decode_|Equal20~0_combout ), - .datab(\z80_|execute_|ctl_mRead~26_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~27 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~40 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~40_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~24_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~27_combout & \z80_|execute_|nextM~11_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~27_combout ), - .datad(\z80_|execute_|nextM~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~40 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~53 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~53_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal21~1_combout ) # (!\z80_|sequencer_|DFFE_T4_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), - .datad(\z80_|pla_decode_|Equal21~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~53 .lut_mask = 16'hB0F0; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_hi~8_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & ((\z80_|execute_|ctl_ir_we~12_combout ) # (!\z80_|execute_|nextM~2_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~12_combout ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|execute_|nextM~2_combout ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_hi~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_hi~8 .lut_mask = 16'h8C00; -defparam \z80_|execute_|ctl_reg_out_hi~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|setM1~54 ( -// Equation(s): -// \z80_|execute_|setM1~54_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|execute_|ctl_ir_we~9_combout ), - .datac(\z80_|execute_|ctl_ir_we~10_combout ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~54_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~54 .lut_mask = 16'hABFF; -defparam \z80_|execute_|setM1~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~1 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~1_combout = ((!\z80_|execute_|ctl_ir_we~8_combout & (!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_state_alu~7_combout ))) # (!\z80_|execute_|ctl_eval_cond~0_combout ) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_state_alu~7_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~1 .lut_mask = 16'h01FF; -defparam \z80_|execute_|ctl_sw_2u~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~4 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~4_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|execute_|ctl_mWrite~5_combout & ((!\z80_|execute_|ctl_alu_oe~3_combout )))) # (!\z80_|execute_|ctl_eval_cond~0_combout & (((!\z80_|execute_|ctl_ir_we~4_combout )) # -// (!\z80_|execute_|ctl_mWrite~5_combout ))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|ctl_mWrite~5_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|execute_|ctl_alu_oe~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~4 .lut_mask = 16'h1537; -defparam \z80_|execute_|ctl_sw_2u~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~5 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~5_combout = (\z80_|execute_|setM1~54_combout & (\z80_|execute_|ctl_sw_2u~1_combout & \z80_|execute_|ctl_sw_2u~4_combout )) - - .dataa(\z80_|execute_|setM1~54_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_sw_2u~1_combout ), - .datad(\z80_|execute_|ctl_sw_2u~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~5 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_sw_2u~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~6 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~6_combout = (\z80_|execute_|ctl_reg_gp_sel~36_combout & (\z80_|execute_|comb~0_combout $ ((!\z80_|ir_|opcode [0])))) # (!\z80_|execute_|ctl_reg_gp_sel~36_combout & (!\z80_|execute_|ctl_sw_2u~5_combout & -// (\z80_|execute_|comb~0_combout $ (!\z80_|ir_|opcode [0])))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel~36_combout ), - .datab(\z80_|execute_|comb~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|execute_|ctl_sw_2u~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~6 .lut_mask = 16'h82C3; -defparam \z80_|execute_|ctl_sw_2u~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~35 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~35_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ctl_state_alu~5_combout & ((!\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|pla_decode_|Equal47~0_combout & -// (((!\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|pla_decode_|Equal34~0_combout ), - .datad(\z80_|execute_|ctl_state_alu~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~35 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_inc_cy~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~35 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~35_combout = (\z80_|execute_|ctl_inc_cy~35_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|sequencer_|DFFE_M4_ff~q ) # (!\z80_|pla_decode_|Equal19~0_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|pla_decode_|Equal19~0_combout ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|execute_|ctl_inc_cy~35_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~35 .lut_mask = 16'hBF00; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~6 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~6_combout = (\z80_|pla_decode_|Equal55~0_combout & (!\z80_|ir_|opcode [3] & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~6 .lut_mask = 16'h0200; -defparam \z80_|execute_|ctl_mWrite~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~2 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~2_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|execute_|ctl_mWrite~6_combout & ((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|execute_|ctl_eval_cond~0_combout & -// (((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|ctl_mWrite~6_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|execute_|ctl_mRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~2 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_sw_2u~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~0 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~0_combout = (\z80_|pla_decode_|Equal9~1_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((!\z80_|execute_|ctl_mWrite~4_combout ) # (!\z80_|execute_|ctl_state_alu~5_combout )))) # (!\z80_|pla_decode_|Equal9~1_combout & -// (((!\z80_|execute_|ctl_mWrite~4_combout ) # (!\z80_|execute_|ctl_state_alu~5_combout )))) - - .dataa(\z80_|pla_decode_|Equal9~1_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_state_alu~5_combout ), - .datad(\z80_|execute_|ctl_mWrite~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~0 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_sw_2u~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~3 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~3_combout = (\z80_|execute_|ctl_sw_2u~2_combout & (\z80_|execute_|ctl_sw_2u~0_combout & ((!\z80_|execute_|ctl_alu_oe~2_combout ) # (!\z80_|execute_|ctl_mRead~8_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~8_combout ), - .datab(\z80_|execute_|ctl_sw_2u~2_combout ), - .datac(\z80_|execute_|ctl_sw_2u~0_combout ), - .datad(\z80_|execute_|ctl_alu_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~3 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_sw_2u~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~52 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~52_combout = (\z80_|execute_|ctl_sw_2u~3_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|sequencer_|M5~q )) # (!\z80_|execute_|ctl_mRead~10_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|execute_|ctl_sw_2u~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~52 .lut_mask = 16'hDF00; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout = (\z80_|pla_decode_|Equal1~4_combout & (\z80_|ir_|opcode [0] & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~4_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~2_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|pla_decode_|Equal69~0_combout ) # (\z80_|execute_|ctl_alu_op_low~13_combout )))) - - .dataa(\z80_|pla_decode_|Equal69~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~13_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~2 .lut_mask = 16'hFEF0; -defparam \z80_|execute_|ctl_reg_out_lo~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N18 -cycloneive_lcell_comb \z80_|execute_|rsel3 ( -// Equation(s): -// \z80_|execute_|rsel3~combout = \z80_|ir_|opcode [3] $ (((\z80_|ir_|opcode [4] & \z80_|ir_|opcode [5]))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|ir_|opcode [3]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|rsel3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|rsel3 .lut_mask = 16'h7878; -defparam \z80_|execute_|rsel3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_hi~5_combout = (\z80_|execute_|ctl_mRead~5_combout & (!\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|rsel3~combout ) # (!\z80_|execute_|ctl_reg_out_lo~2_combout )))) # (!\z80_|execute_|ctl_mRead~5_combout & -// (((\z80_|execute_|rsel3~combout ) # (!\z80_|execute_|ctl_reg_out_lo~2_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~5_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|execute_|ctl_reg_out_lo~2_combout ), - .datad(\z80_|execute_|rsel3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_hi~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_hi~5 .lut_mask = 16'h7707; -defparam \z80_|execute_|ctl_reg_out_hi~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_hi~6_combout = (!\z80_|execute_|ctl_sw_2u~6_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout & \z80_|execute_|ctl_reg_out_hi~5_combout ))) - - .dataa(\z80_|execute_|ctl_sw_2u~6_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ), - .datad(\z80_|execute_|ctl_reg_out_hi~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_hi~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_hi~6 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_out_hi~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_hi~7_combout = ((\z80_|execute_|ctl_reg_out_hi~8_combout ) # ((!\z80_|execute_|ctl_reg_out_hi~6_combout ) # (!\z80_|execute_|ctl_reg_out_hi~4_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ), - .datab(\z80_|execute_|ctl_reg_out_hi~8_combout ), - .datac(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .datad(\z80_|execute_|ctl_reg_out_hi~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_hi~7 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_reg_out_hi~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N28 -cycloneive_lcell_comb \z80_|execute_|rsel0 ( -// Equation(s): -// \z80_|execute_|rsel0~combout = \z80_|ir_|opcode [0] $ (((\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1]))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(gnd), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|execute_|rsel0~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|rsel0 .lut_mask = 16'h5AAA; -defparam \z80_|execute_|rsel0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout = (\z80_|execute_|ixy_d~15_combout & \z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(gnd), - .datab(\z80_|execute_|ixy_d~15_combout ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 .lut_mask = 16'hC0C0; -defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~33 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~33_combout = (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout & (\z80_|execute_|ctl_reg_use_sp~0_combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_mRead~36_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), - .datab(\z80_|execute_|ctl_reg_use_sp~0_combout ), - .datac(\z80_|execute_|ctl_mRead~36_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~33 .lut_mask = 16'h0444; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~6_combout = (\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout & ((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~6 .lut_mask = 16'h0888; -defparam \z80_|execute_|ctl_reg_out_lo~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~7_combout = (\z80_|execute_|ctl_reg_out_lo~6_combout & (((!\z80_|execute_|ctl_reg_gp_sel~36_combout & \z80_|execute_|ctl_sw_2u~5_combout )) # (!\z80_|execute_|rsel0~combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel~36_combout ), - .datab(\z80_|execute_|rsel0~combout ), - .datac(\z80_|execute_|ctl_reg_out_lo~6_combout ), - .datad(\z80_|execute_|ctl_sw_2u~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~7 .lut_mask = 16'h7030; -defparam \z80_|execute_|ctl_reg_out_lo~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_iorw~11 ( -// Equation(s): -// \z80_|execute_|ctl_iorw~11_combout = (!\z80_|ir_|opcode [1] & (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [2] & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_iorw~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_iorw~11 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_iorw~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~10 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~10_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (((\z80_|execute_|rsel3~combout & \z80_|execute_|ctl_iorw~11_combout )) # (!\z80_|execute_|nextM~2_combout ))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|rsel3~combout ), - .datac(\z80_|execute_|nextM~2_combout ), - .datad(\z80_|execute_|ctl_iorw~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~10 .lut_mask = 16'h8A0A; -defparam \z80_|execute_|ctl_sw_2d~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~14 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~14_combout = (!\z80_|execute_|ctl_mRead~14_combout & (((\z80_|decode_state_|in_halt~q ) # (!\z80_|pla_decode_|Equal33~0_combout )) # (!\z80_|pla_decode_|Equal77~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal77~0_combout ), - .datab(\z80_|decode_state_|in_halt~q ), - .datac(\z80_|execute_|ctl_mRead~14_combout ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~14 .lut_mask = 16'h0D0F; -defparam \z80_|execute_|ctl_sw_2d~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~11 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~11_combout = (\z80_|execute_|ctl_sw_2d~10_combout ) # ((\z80_|nM1_int~2_combout & ((!\z80_|execute_|ctl_sw_1d~8_combout ) # (!\z80_|execute_|ctl_sw_2d~14_combout )))) - - .dataa(\z80_|execute_|ctl_sw_2d~10_combout ), - .datab(\z80_|execute_|ctl_sw_2d~14_combout ), - .datac(\z80_|execute_|ctl_sw_1d~8_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~11 .lut_mask = 16'hBFAA; -defparam \z80_|execute_|ctl_sw_2d~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~12 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~12_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|execute_|rsel3~combout & ((\z80_|execute_|ctl_alu_op_low~14_combout ) # (\z80_|execute_|ctl_alu_shift_oe~15_combout )))) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .datad(\z80_|execute_|rsel3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~12 .lut_mask = 16'hFEAA; -defparam \z80_|execute_|ctl_sw_2d~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~13 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~13_combout = ((\z80_|execute_|ctl_sw_2d~11_combout ) # ((\z80_|execute_|ctl_sw_2d~12_combout ) # (!\z80_|execute_|ctl_sw_2d~9_combout ))) # (!\z80_|execute_|ctl_reg_out_lo~7_combout ) - - .dataa(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .datab(\z80_|execute_|ctl_sw_2d~11_combout ), - .datac(\z80_|execute_|ctl_sw_2d~12_combout ), - .datad(\z80_|execute_|ctl_sw_2d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~13 .lut_mask = 16'hFDFF; -defparam \z80_|execute_|ctl_sw_2d~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_66_oe ( -// Equation(s): -// \z80_|execute_|ctl_66_oe~combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|sequencer_|DFFE_T3_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|pla_decode_|Equal47~0_combout ))) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_66_oe~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_66_oe .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_66_oe .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~34 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~34_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|pla_decode_|Equal47~0_combout & ((!\z80_|execute_|ctl_alu_oe~2_combout ) # (!\z80_|pla_decode_|Equal34~0_combout )))) # (!\z80_|execute_|ixy_d~7_combout & -// (((!\z80_|execute_|ctl_alu_oe~2_combout )) # (!\z80_|pla_decode_|Equal34~0_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|pla_decode_|Equal34~0_combout ), - .datac(\z80_|pla_decode_|Equal47~0_combout ), - .datad(\z80_|execute_|ctl_alu_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~34 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_inc_cy~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~0 ( -// Equation(s): -// \z80_|execute_|ctl_apin_mux~0_combout = (\z80_|execute_|ctl_inc_cy~34_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout & ((!\z80_|execute_|ctl_alu_oe~2_combout ) # (!\z80_|pla_decode_|Equal19~0_combout )))) - - .dataa(\z80_|execute_|ctl_inc_cy~34_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), - .datac(\z80_|pla_decode_|Equal19~0_combout ), - .datad(\z80_|execute_|ctl_alu_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_apin_mux~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_apin_mux~0 .lut_mask = 16'h0888; -defparam \z80_|execute_|ctl_apin_mux~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~5 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~5_combout = (\z80_|execute_|ctl_alu_op_low~14_combout ) # (((\z80_|execute_|ctl_alu_shift_oe~14_combout & \z80_|pla_decode_|Equal47~0_combout )) # (!\z80_|execute_|ctl_sw_4u~1_combout )) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ctl_sw_4u~1_combout ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~5 .lut_mask = 16'hEFCF; -defparam \z80_|execute_|ctl_sw_4u~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~75 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~75_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & (!\z80_|pla_decode_|Equal38~2_combout & ((!\z80_|pla_decode_|Equal37~0_combout )))) # (!\z80_|execute_|ctl_alu_op_low~8_combout & (((!\z80_|pla_decode_|Equal38~2_combout -// & !\z80_|pla_decode_|Equal37~0_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datab(\z80_|pla_decode_|Equal38~2_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|pla_decode_|Equal37~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~75_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~75 .lut_mask = 16'h0537; -defparam \z80_|execute_|ctl_inc_cy~75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~76 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~76_combout = (\z80_|execute_|ctl_inc_cy~75_combout & (((!\z80_|execute_|ctl_alu_op_low~8_combout & !\z80_|execute_|ixy_d~5_combout )) # (!\z80_|pla_decode_|Equal29~0_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~75_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|pla_decode_|Equal29~0_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~76_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~76 .lut_mask = 16'h0A2A; -defparam \z80_|execute_|ctl_inc_cy~76 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal4~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal4~0_combout = (\z80_|execute_|comb~1_combout & (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal1~7_combout & \z80_|pla_decode_|Equal1~4_combout ))) - - .dataa(\z80_|execute_|comb~1_combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|pla_decode_|Equal1~7_combout ), - .datad(\z80_|pla_decode_|Equal1~4_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal4~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal4~0 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y19_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~48 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~48_combout = (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|execute_|ctl_mWrite~4_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|execute_|ctl_mWrite~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~48 .lut_mask = 16'h1FFF; -defparam \z80_|execute_|ctl_bus_inc_oe~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~46 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~46_combout = (\z80_|execute_|ctl_bus_inc_oe~48_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T5_ff~q )) # (!\z80_|pla_decode_|Equal4~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal4~0_combout ), + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|execute_|ctl_bus_inc_oe~48_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal3~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_iy_set~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_iy_set~2 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_state_iy_set~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N18 +cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_16 ( +// Equation(s): +// \z80_|sequencer_|SYNTHESIZED_WIRE_16~combout = (\z80_|execute_|setM1~54_combout & (\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|execute_|nextM~14_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|setM1~54_combout ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_16 .lut_mask = 16'h00C0; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y13_N19 +dffeas \z80_|sequencer_|DFFE_T5_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_T5_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_T5_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_T5_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_state_ixiy_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_state_ixiy_we~2_combout = (\z80_|execute_|ixy_d~15_combout & ((\z80_|sequencer_|DFFE_T5_ff~q ) # ((!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T2_ff~q )))) # (!\z80_|execute_|ixy_d~15_combout & +// (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|execute_|ixy_d~15_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), .datad(\z80_|sequencer_|DFFE_T5_ff~q ), .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~46_combout ), + .combout(\z80_|execute_|ctl_state_ixiy_we~2_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~46 .lut_mask = 16'hD0F0; -defparam \z80_|execute_|ctl_bus_inc_oe~46 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_state_ixiy_we~2 .lut_mask = 16'hBA30; +defparam \z80_|execute_|ctl_state_ixiy_we~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y18_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~53 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~53_combout = (\z80_|execute_|ctl_mRead~16_combout & (!\z80_|execute_|ctl_alu_op_low~8_combout & ((!\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|execute_|ctl_mRead~16_combout & (((!\z80_|execute_|ctl_alu_op_low~8_combout & -// !\z80_|execute_|ixy_d~5_combout )) # (!\z80_|pla_decode_|Equal9~1_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~16_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~53_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~53 .lut_mask = 16'h0537; -defparam \z80_|execute_|ctl_inc_cy~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~92 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~92_combout = (((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|pla_decode_|Equal9~1_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|sequencer_|DFFE_M4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~92_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~92 .lut_mask = 16'h5F7F; -defparam \z80_|execute_|ctl_inc_cy~92 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal19~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal19~1_combout = (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal32~0_combout & \z80_|pla_decode_|Equal52~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|pla_decode_|Equal32~0_combout ), - .datad(\z80_|pla_decode_|Equal52~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal19~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal19~1 .lut_mask = 16'h2000; -defparam \z80_|pla_decode_|Equal19~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~0 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~0_combout = (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|M5~q ) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|sequencer_|M5~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~0 .lut_mask = 16'hAA00; -defparam \z80_|execute_|ctl_sw_4u~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~38 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~38_combout = (((!\z80_|execute_|ctl_alu_shift_oe~14_combout & !\z80_|execute_|ctl_sw_4u~0_combout )) # (!\z80_|pla_decode_|Equal3~1_combout )) # (!\z80_|pla_decode_|Equal19~1_combout ) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|pla_decode_|Equal19~1_combout ), - .datac(\z80_|execute_|ctl_sw_4u~0_combout ), - .datad(\z80_|pla_decode_|Equal3~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~38 .lut_mask = 16'h37FF; -defparam \z80_|execute_|ctl_inc_cy~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~93 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~93_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|pla_decode_|Equal34~0_combout ) - - .dataa(\z80_|pla_decode_|Equal34~0_combout ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~93_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~93 .lut_mask = 16'h57FF; -defparam \z80_|execute_|ctl_inc_cy~93 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~39 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~39_combout = (\z80_|execute_|ctl_inc_cy~93_combout & (((!\z80_|execute_|ctl_alu_op_low~8_combout & !\z80_|execute_|ixy_d~5_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|execute_|ctl_inc_cy~93_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~39 .lut_mask = 16'h444C; -defparam \z80_|execute_|ctl_inc_cy~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~24 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~24_combout = (\z80_|execute_|ctl_inc_cy~92_combout & (\z80_|execute_|ctl_inc_cy~38_combout & \z80_|execute_|ctl_inc_cy~39_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_inc_cy~92_combout ), - .datac(\z80_|execute_|ctl_inc_cy~38_combout ), - .datad(\z80_|execute_|ctl_inc_cy~39_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~24 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_bus_inc_oe~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~1 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~1_combout = (\z80_|execute_|ctl_inc_cy~76_combout & (\z80_|execute_|ctl_bus_inc_oe~46_combout & (\z80_|execute_|ctl_inc_cy~53_combout & \z80_|execute_|ctl_bus_inc_oe~24_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~76_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~46_combout ), - .datac(\z80_|execute_|ctl_inc_cy~53_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~1 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_we~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T5_ff~q & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal8~0_combout ))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T5_ff~q ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|pla_decode_|Equal8~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~44 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~44_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout & (((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|pla_decode_|Equal11~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal11~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~44 .lut_mask = 16'h1333; -defparam \z80_|execute_|ctl_bus_inc_oe~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~5_combout = ((!\z80_|pla_decode_|Equal10~0_combout & (!\z80_|pla_decode_|Equal11~0_combout & !\z80_|execute_|ctl_mRead~36_combout ))) # (!\z80_|execute_|ctl_alu_op_low~8_combout ) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|execute_|ctl_mRead~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~5 .lut_mask = 16'h3337; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~0_combout = (\z80_|execute_|ctl_bus_inc_oe~44_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~5_combout & ((!\z80_|execute_|ctl_mWrite~16_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_mWrite~16_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~0 .lut_mask = 16'h2A00; -defparam \z80_|execute_|ctl_reg_gp_we~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|sequencer_|M5~q & \z80_|pla_decode_|Equal9~1_combout )) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~35 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~35_combout = (\z80_|execute_|ctl_reg_gp_we~0_combout & (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout & ((!\z80_|pla_decode_|Equal10~0_combout ) # (!\z80_|execute_|ixy_d~9_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_we~0_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), - .datad(\z80_|pla_decode_|Equal10~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~35 .lut_mask = 16'h020A; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~2 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~2_combout = (\z80_|execute_|ixy_d~5_combout & (\z80_|execute_|nextM~2_combout & ((!\z80_|execute_|ixy_d~9_combout ) # (!\z80_|pla_decode_|Equal11~0_combout )))) # (!\z80_|execute_|ixy_d~5_combout & -// (((!\z80_|execute_|ixy_d~9_combout )) # (!\z80_|pla_decode_|Equal11~0_combout ))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|execute_|nextM~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~2 .lut_mask = 16'h3F15; -defparam \z80_|execute_|ctl_sw_4u~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~3 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~3_combout = (\z80_|execute_|ctl_reg_gp_we~1_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout & \z80_|execute_|ctl_sw_4u~2_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~1_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ), - .datad(\z80_|execute_|ctl_sw_4u~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~3 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_sw_4u~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N0 -cycloneive_lcell_comb \z80_|execute_|fMRead~3 ( -// Equation(s): -// \z80_|execute_|fMRead~3_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & (!\z80_|execute_|ctl_state_alu~14_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_mRead~15_combout )))) # -// (!\z80_|execute_|ctl_alu_op_low~8_combout & (((!\z80_|execute_|ctl_alu_shift_oe~14_combout )) # (!\z80_|execute_|ctl_mRead~15_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datab(\z80_|execute_|ctl_mRead~15_combout ), - .datac(\z80_|execute_|ctl_state_alu~14_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~3 .lut_mask = 16'h135F; -defparam \z80_|execute_|fMRead~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~4 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~4_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal55~0_combout & (!\z80_|ir_|opcode [5] & \z80_|execute_|ctl_alu_op_low~8_combout ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~4 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_sw_4u~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout = (\z80_|execute_|ctl_alu_shift_oe~14_combout & (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~15 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~15_combout = (!\z80_|execute_|ctl_sw_4u~4_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_ir_we~12_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~12_combout ), - .datab(\z80_|execute_|ctl_sw_4u~4_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~15 .lut_mask = 16'h0013; -defparam \z80_|execute_|ctl_reg_sel_wz~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~8_combout = (\z80_|execute_|ctl_mRead~10_combout & (!\z80_|execute_|ctl_alu_shift_oe~14_combout & ((!\z80_|execute_|ctl_sw_4u~0_combout )))) # (!\z80_|execute_|ctl_mRead~10_combout & -// (((!\z80_|execute_|ctl_alu_shift_oe~14_combout & !\z80_|execute_|ctl_sw_4u~0_combout )) # (!\z80_|execute_|ctl_mRead~8_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datac(\z80_|execute_|ctl_mRead~8_combout ), - .datad(\z80_|execute_|ctl_sw_4u~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~8 .lut_mask = 16'h0537; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~94 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~94_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|execute_|ctl_mRead~17_combout ) - - .dataa(\z80_|execute_|ctl_mRead~17_combout ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~94_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~94 .lut_mask = 16'h57FF; -defparam \z80_|execute_|ctl_inc_cy~94 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~87 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~87_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|pla_decode_|Equal13~2_combout ) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~87_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~87 .lut_mask = 16'h5FFF; -defparam \z80_|execute_|ctl_inc_cy~87 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~42 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~42_combout = (\z80_|pla_decode_|Equal12~1_combout ) # (((!\z80_|execute_|ctl_sw_4u~0_combout & !\z80_|execute_|ctl_alu_shift_oe~14_combout )) # (!\z80_|pla_decode_|Equal25~0_combout )) - - .dataa(\z80_|execute_|ctl_sw_4u~0_combout ), - .datab(\z80_|pla_decode_|Equal12~1_combout ), - .datac(\z80_|pla_decode_|Equal25~0_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~42 .lut_mask = 16'hCFDF; -defparam \z80_|execute_|ctl_inc_cy~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~34 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~34_combout = (\z80_|execute_|ctl_inc_cy~94_combout & (\z80_|execute_|ctl_inc_cy~87_combout & \z80_|execute_|ctl_inc_cy~42_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_inc_cy~94_combout ), - .datac(\z80_|execute_|ctl_inc_cy~87_combout ), - .datad(\z80_|execute_|ctl_inc_cy~42_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~34 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~16 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~16_combout = (\z80_|execute_|fMRead~3_combout & (\z80_|execute_|ctl_reg_sel_wz~15_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ))) - - .dataa(\z80_|execute_|fMRead~3_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~15_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~16 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sel_wz~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~6 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~6_combout = ((\z80_|execute_|ctl_sw_4u~5_combout ) # ((!\z80_|execute_|ctl_reg_sel_wz~16_combout ) # (!\z80_|execute_|ctl_sw_4u~3_combout ))) # (!\z80_|execute_|ctl_apin_mux~0_combout ) - - .dataa(\z80_|execute_|ctl_apin_mux~0_combout ), - .datab(\z80_|execute_|ctl_sw_4u~5_combout ), - .datac(\z80_|execute_|ctl_sw_4u~3_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~6 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_sw_4u~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N22 -cycloneive_lcell_comb \z80_|pla_decode_|Equal2~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal2~2_combout = (\z80_|pla_decode_|Equal1~7_combout & (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal32~0_combout & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~7_combout ), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|pla_decode_|Equal32~0_combout ), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal2~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal2~2 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal2~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal1~6 ( -// Equation(s): -// \z80_|pla_decode_|Equal1~6_combout = (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal1~5_combout & (\z80_|pla_decode_|Equal1~7_combout & \z80_|pla_decode_|Equal1~4_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal1~5_combout ), - .datac(\z80_|pla_decode_|Equal1~7_combout ), - .datad(\z80_|pla_decode_|Equal1~4_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal1~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal1~6 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal1~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N22 -cycloneive_lcell_comb \z80_|reg_control_|bank_exx~2 ( -// Equation(s): -// \z80_|reg_control_|bank_exx~2_combout = \z80_|reg_control_|bank_exx~q $ (((!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal1~6_combout & \z80_|sequencer_|DFFE_T2_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|pla_decode_|Equal1~6_combout ), - .datac(\z80_|reg_control_|bank_exx~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|reg_control_|bank_exx~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|bank_exx~2 .lut_mask = 16'hB4F0; -defparam \z80_|reg_control_|bank_exx~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y13_N23 -dffeas \z80_|reg_control_|bank_exx ( +// Location: FF_X26_Y16_N7 +dffeas \z80_|decode_state_|DFFE_instIY1 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_control_|bank_exx~2_combout ), + .d(\z80_|execute_|ctl_state_iy_set~2_combout ), .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(vcc), + .ena(\z80_|execute_|ctl_state_ixiy_we~2_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|reg_control_|bank_exx~q ), + .q(\z80_|decode_state_|DFFE_instIY1~q ), .prn(vcc)); // synopsys translate_off -defparam \z80_|reg_control_|bank_exx .is_wysiwyg = "true"; -defparam \z80_|reg_control_|bank_exx .power_up = "low"; +defparam \z80_|decode_state_|DFFE_instIY1 .is_wysiwyg = "true"; +defparam \z80_|decode_state_|DFFE_instIY1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y15_N26 -cycloneive_lcell_comb \z80_|reg_control_|bank_hl_de1~0 ( +// Location: LCCOMB_X25_Y16_N10 +cycloneive_lcell_comb \z80_|decode_state_|use_ixiy ( // Equation(s): -// \z80_|reg_control_|bank_hl_de1~0_combout = \z80_|reg_control_|bank_hl_de1~q $ (((\z80_|pla_decode_|Equal2~2_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & !\z80_|reg_control_|bank_exx~q )))) - - .dataa(\z80_|pla_decode_|Equal2~2_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|reg_control_|bank_hl_de1~q ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_control_|bank_hl_de1~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|bank_hl_de1~0 .lut_mask = 16'hF0D2; -defparam \z80_|reg_control_|bank_hl_de1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y15_N27 -dffeas \z80_|reg_control_|bank_hl_de1 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_control_|bank_hl_de1~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_control_|bank_hl_de1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_control_|bank_hl_de1 .is_wysiwyg = "true"; -defparam \z80_|reg_control_|bank_hl_de1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~10 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~10_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|pla_decode_|Equal4~0_combout ) # ((\z80_|pla_decode_|Equal2~1_combout & \z80_|pla_decode_|Equal1~4_combout )))) - - .dataa(\z80_|pla_decode_|Equal4~0_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|pla_decode_|Equal2~1_combout ), - .datad(\z80_|pla_decode_|Equal1~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~10 .lut_mask = 16'hC888; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~11 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~11_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout ) # (\z80_|execute_|ctl_state_alu~4_combout )))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|nextM~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~11 .lut_mask = 16'h00FE; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~12 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~12_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ) # ((\z80_|execute_|ctl_state_alu~4_combout & \z80_|execute_|ctl_mRead~36_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_mRead~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~12 .lut_mask = 16'hFEEE; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~7 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~7_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|decode_state_|use_ixiy~combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~7 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_mRead~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~9_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mRead~5_combout ) # ((\z80_|execute_|ctl_mRead~7_combout ) # (\z80_|execute_|ctl_mWrite~16_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~5_combout ), - .datab(\z80_|execute_|ctl_mRead~7_combout ), - .datac(\z80_|execute_|ctl_mWrite~16_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~9 .lut_mask = 16'hFE00; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~37 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~37_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~5_combout & (((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|execute_|ctl_mWrite~16_combout ))) - - .dataa(\z80_|execute_|ctl_mWrite~16_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~37 .lut_mask = 16'h4CCC; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~13 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~13_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~12_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~9_combout ) # ((\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ) # (!\z80_|execute_|ctl_reg_gp_sel[1]~37_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~12_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~9_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~37_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~13 .lut_mask = 16'hFFEF; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~47 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~47_combout = (\z80_|decode_state_|DFFE_inst4~q ) # ((\z80_|decode_state_|DFFE_instIY1~q ) # ((!\z80_|pla_decode_|Equal50~0_combout & !\z80_|pla_decode_|Equal49~0_combout ))) - - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(\z80_|decode_state_|DFFE_instIY1~q ), - .datac(\z80_|pla_decode_|Equal50~0_combout ), - .datad(\z80_|pla_decode_|Equal49~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~47 .lut_mask = 16'hEEEF; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|fMWrite~3 ( -// Equation(s): -// \z80_|execute_|fMWrite~3_combout = (!\z80_|execute_|ctl_ir_we~15_combout & (!\z80_|execute_|ctl_ir_we~14_combout & (!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_mRead~6_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~15_combout ), - .datab(\z80_|execute_|ctl_ir_we~14_combout ), - .datac(\z80_|execute_|ctl_ir_we~7_combout ), - .datad(\z80_|execute_|ctl_mRead~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~3 .lut_mask = 16'h0001; -defparam \z80_|execute_|fMWrite~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~5_combout = (\z80_|ir_|opcode [2]) # ((\z80_|ir_|opcode [1]) # (!\z80_|execute_|ctl_mWrite~2_combout )) - - .dataa(\z80_|ir_|opcode [2]), - .datab(gnd), - .datac(\z80_|execute_|ctl_mWrite~2_combout ), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~5 .lut_mask = 16'hFFAF; -defparam \z80_|execute_|ctl_flags_bus~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N26 -cycloneive_lcell_comb \z80_|execute_|fMRead~2 ( -// Equation(s): -// \z80_|execute_|fMRead~2_combout = (!\z80_|pla_decode_|Equal13~2_combout & (!\z80_|execute_|ctl_state_alu~14_combout & \z80_|execute_|ctl_flags_bus~5_combout )) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(\z80_|execute_|ctl_state_alu~14_combout ), - .datac(\z80_|execute_|ctl_flags_bus~5_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|fMRead~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~2 .lut_mask = 16'h1010; -defparam \z80_|execute_|fMRead~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~19 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~19_combout = (\z80_|execute_|fMWrite~3_combout & (\z80_|execute_|fMRead~2_combout & !\z80_|execute_|ctl_ir_we~12_combout )) +// \z80_|decode_state_|use_ixiy~combout = (\z80_|decode_state_|DFFE_inst4~q ) # (\z80_|decode_state_|DFFE_instIY1~q ) .dataa(gnd), - .datab(\z80_|execute_|fMWrite~3_combout ), - .datac(\z80_|execute_|fMRead~2_combout ), - .datad(\z80_|execute_|ctl_ir_we~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~19 .lut_mask = 16'h00C0; -defparam \z80_|execute_|ctl_mRead~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~7_combout = (\z80_|execute_|ctl_state_alu~5_combout & (((\z80_|execute_|ctl_mRead~36_combout ) # (!\z80_|execute_|ctl_mRead~19_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), - .datab(\z80_|execute_|ctl_state_alu~5_combout ), - .datac(\z80_|execute_|ctl_mRead~36_combout ), - .datad(\z80_|execute_|ctl_mRead~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~7 .lut_mask = 16'hC4CC; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~8_combout = (\z80_|ir_|opcode [2] & ((!\z80_|execute_|ctl_sw_2u~5_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), - .datab(gnd), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|execute_|ctl_sw_2u~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~8 .lut_mask = 16'h50F0; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~14 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~14_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~13_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~7_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~8_combout ) # (!\z80_|execute_|ctl_alu_op_low~15_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~13_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~7_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~15_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~14 .lut_mask = 16'hFFEF; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~16 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~16_combout = (\z80_|ir_|opcode [3] & (((\z80_|sequencer_|DFFE_T3_ff~q )))) # (!\z80_|ir_|opcode [3] & (((\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|pla_decode_|Equal12~0_combout )) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal12~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~16 .lut_mask = 16'hC5CD; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~15 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~15_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|ir_|opcode [3] & (\z80_|ir_|opcode [7] & \z80_|ir_|opcode [6]))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|ir_|opcode [6]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~15 .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~17 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~17_combout = (\z80_|ir_|opcode [0] & (((\z80_|execute_|ctl_reg_gp_sel[1]~15_combout )))) # (!\z80_|ir_|opcode [0] & (\z80_|execute_|ctl_reg_gp_sel[1]~16_combout & ((\z80_|execute_|ctl_ir_we~6_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~16_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|execute_|ctl_ir_we~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~17 .lut_mask = 16'hCAC0; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~19 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~19_combout = (!\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2])) - - .dataa(\z80_|ir_|opcode [4]), - .datab(gnd), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~19 .lut_mask = 16'h0050; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~2_combout = (((!\z80_|execute_|ctl_mRead~11_combout & !\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal8~0_combout )) # (!\z80_|pla_decode_|Equal6~0_combout ) - - .dataa(\z80_|execute_|ctl_mRead~11_combout ), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal8~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~2 .lut_mask = 16'h37FF; -defparam \z80_|execute_|ctl_reg_use_sp~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~47 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~47_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q ))) # (!\z80_|execute_|ctl_mRead~8_combout ) - - .dataa(\z80_|sequencer_|M5~q ), - .datab(\z80_|execute_|ctl_mRead~8_combout ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~47 .lut_mask = 16'hFF37; -defparam \z80_|execute_|ctl_bus_inc_oe~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~3_combout = (\z80_|execute_|ctl_reg_use_sp~2_combout & (\z80_|execute_|ctl_reg_use_sp~0_combout & (\z80_|execute_|ctl_bus_inc_oe~47_combout & \z80_|execute_|nextM~11_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~2_combout ), - .datab(\z80_|execute_|ctl_reg_use_sp~0_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~47_combout ), - .datad(\z80_|execute_|nextM~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~3 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_use_sp~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~9 ( -// Equation(s): -// \z80_|execute_|ctl_sw_1d~9_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal6~1_combout & !\z80_|sequencer_|DFFE_M1_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal6~1_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~9 .lut_mask = 16'h0050; -defparam \z80_|execute_|ctl_sw_1d~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~21 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~21_combout = (!\z80_|execute_|ctl_sw_1d~9_combout & (((!\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ctl_state_alu~5_combout )) # (!\z80_|execute_|ctl_mWrite~4_combout ))) - - .dataa(\z80_|execute_|ctl_mWrite~4_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|execute_|ctl_state_alu~5_combout ), - .datad(\z80_|execute_|ctl_sw_1d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~21 .lut_mask = 16'h0057; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~20 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~20_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout & ((\z80_|pla_decode_|Equal33~1_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~15_combout & -// !\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~20 .lut_mask = 16'hAB00; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~20 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~20_combout = (!\z80_|execute_|ctl_alu_oe~3_combout & (!\z80_|execute_|ctl_mRead~14_combout & !\z80_|pla_decode_|Equal49~0_combout )) - - .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), - .datab(\z80_|execute_|ctl_mRead~14_combout ), - .datac(\z80_|pla_decode_|Equal49~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~20 .lut_mask = 16'h0101; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~49 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~49_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((\z80_|execute_|ctl_reg_gp_sel[0]~20_combout ) # (\z80_|sequencer_|DFFE_M1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~20_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~49 .lut_mask = 16'hCCC8; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~22 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~22_combout = (\z80_|execute_|ctl_reg_use_sp~3_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~21_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~6_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~3_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[0]~21_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~22 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~18 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~18_combout = (!\z80_|decode_state_|DFFE_instED~q & (!\z80_|decode_state_|DFFE_instCB~q & ((\z80_|sequencer_|M5~q ) # (\z80_|sequencer_|DFFE_M4_ff~q )))) - - .dataa(\z80_|sequencer_|M5~q ), - .datab(\z80_|decode_state_|DFFE_instED~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|decode_state_|DFFE_instCB~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~18 .lut_mask = 16'h0032; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~23 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~23_combout = ((\z80_|execute_|ctl_reg_gp_sel[1]~17_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~19_combout & \z80_|execute_|ctl_reg_gp_sel[1]~18_combout ))) # (!\z80_|execute_|ctl_reg_gp_sel[0]~22_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~17_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~22_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~23 .lut_mask = 16'h8F0F; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~28 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~28_combout = (\z80_|execute_|ctl_sw_2u~2_combout & !\z80_|execute_|ctl_reg_gp_sel~36_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_sw_2u~2_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_gp_sel~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~28 .lut_mask = 16'h00CC; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~23 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~23_combout = (\z80_|execute_|ctl_sw_1d~4_combout & (((!\z80_|pla_decode_|Equal69~0_combout & \z80_|execute_|ctl_sw_1d~8_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_sw_1d~4_combout ), - .datab(\z80_|pla_decode_|Equal69~0_combout ), - .datac(\z80_|execute_|ctl_sw_1d~8_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~23 .lut_mask = 16'h20AA; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_sel_shift~2_combout = (!\z80_|execute_|ctl_ir_we~8_combout & !\z80_|pla_decode_|Equal20~0_combout ) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal20~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~2 .lut_mask = 16'h0505; -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~14 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_cpl~14_combout = (\z80_|ir_|opcode [4]) # (!\z80_|pla_decode_|Equal63~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|pla_decode_|Equal63~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_cpl~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_cpl~14 .lut_mask = 16'hF0FF; -defparam \z80_|execute_|ctl_flags_hf_cpl~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_cpl~10_combout = (!\z80_|pla_decode_|Equal68~2_combout & (!\z80_|execute_|ctl_state_alu~7_combout & (\z80_|execute_|ctl_flags_hf_cpl~14_combout & !\z80_|execute_|ctl_alu_op_low~13_combout ))) - - .dataa(\z80_|pla_decode_|Equal68~2_combout ), - .datab(\z80_|execute_|ctl_state_alu~7_combout ), - .datac(\z80_|execute_|ctl_flags_hf_cpl~14_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_cpl~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_cpl~10 .lut_mask = 16'h0010; -defparam \z80_|execute_|ctl_flags_hf_cpl~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N22 -cycloneive_lcell_comb \z80_|execute_|setM1~47 ( -// Equation(s): -// \z80_|execute_|setM1~47_combout = (!\z80_|execute_|ctl_ir_we~11_combout & (!\z80_|pla_decode_|Equal69~0_combout & ((!\z80_|pla_decode_|Equal21~0_combout ) # (!\z80_|pla_decode_|Equal63~0_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~11_combout ), - .datab(\z80_|pla_decode_|Equal63~0_combout ), - .datac(\z80_|pla_decode_|Equal21~0_combout ), - .datad(\z80_|pla_decode_|Equal69~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~47 .lut_mask = 16'h0015; -defparam \z80_|execute_|setM1~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|setM1~48 ( -// Equation(s): -// \z80_|execute_|setM1~48_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & (\z80_|execute_|ctl_flags_hf_cpl~10_combout & (\z80_|execute_|setM1~47_combout & \z80_|execute_|nextM~2_combout ))) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), - .datab(\z80_|execute_|ctl_flags_hf_cpl~10_combout ), - .datac(\z80_|execute_|setM1~47_combout ), - .datad(\z80_|execute_|nextM~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~48 .lut_mask = 16'h8000; -defparam \z80_|execute_|setM1~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~13 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~13_combout = (\z80_|ir_|opcode [2]) # ((!\z80_|ir_|opcode [1]) # (!\z80_|execute_|ctl_mWrite~2_combout )) - - .dataa(\z80_|ir_|opcode [2]), - .datab(gnd), - .datac(\z80_|execute_|ctl_mWrite~2_combout ), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~13 .lut_mask = 16'hAFFF; -defparam \z80_|execute_|ctl_al_we~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_flags_oe~0_combout = (!\z80_|execute_|ctl_ir_we~14_combout & (!\z80_|execute_|ctl_mRead~6_combout & (!\z80_|execute_|ctl_ir_we~12_combout & !\z80_|execute_|ctl_iorw~10_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~14_combout ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|execute_|ctl_iorw~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_oe~0 .lut_mask = 16'h0001; -defparam \z80_|execute_|ctl_flags_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~1 ( -// Equation(s): -// \z80_|execute_|ctl_flags_oe~1_combout = (\z80_|execute_|ctl_al_we~13_combout & (\z80_|execute_|ctl_flags_bus~5_combout & (!\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_flags_oe~0_combout ))) - - .dataa(\z80_|execute_|ctl_al_we~13_combout ), - .datab(\z80_|execute_|ctl_flags_bus~5_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|ctl_flags_oe~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_oe~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_oe~1 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_flags_oe~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~13 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~13_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & ((!\z80_|execute_|ctl_flags_oe~1_combout ) # (!\z80_|execute_|setM1~48_combout )))) - - .dataa(\z80_|execute_|setM1~48_combout ), - .datab(\z80_|execute_|ctl_flags_oe~1_combout ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~13 .lut_mask = 16'h0070; -defparam \z80_|execute_|ctl_reg_in_hi~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~29 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~29_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~28_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~27_combout & !\z80_|execute_|ctl_reg_in_hi~13_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~28_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~27_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~29 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~40 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~40_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ctl_state_alu~4_combout & ((!\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ctl_state_alu~6_combout )))) # (!\z80_|pla_decode_|Equal47~0_combout & -// (((!\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|execute_|ctl_state_alu~6_combout ), - .datac(\z80_|pla_decode_|Equal34~0_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~40 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_inc_cy~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~2 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~2_combout = (\z80_|execute_|ctl_inc_cy~40_combout & (((!\z80_|pla_decode_|Equal19~0_combout & !\z80_|pla_decode_|Equal9~1_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~40_combout ), - .datab(\z80_|pla_decode_|Equal19~0_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~2 .lut_mask = 16'h0A2A; -defparam \z80_|execute_|ctl_inc_dec~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~12 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~12_combout = (\z80_|execute_|ctl_inc_dec~2_combout & (((!\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|pla_decode_|Equal9~1_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|execute_|ctl_inc_dec~2_combout ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~12 .lut_mask = 16'h4CCC; -defparam \z80_|execute_|ctl_inc_dec~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~43 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~43_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ctl_mRead~11_combout & ((!\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ixy_d~9_combout )))) # (!\z80_|pla_decode_|Equal47~0_combout & -// (((!\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|execute_|ixy_d~9_combout ))) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|pla_decode_|Equal34~0_combout ), - .datad(\z80_|execute_|ctl_mRead~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~43 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_inc_cy~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~5 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~5_combout = (\z80_|execute_|ctl_inc_dec~12_combout & (\z80_|execute_|ctl_inc_cy~43_combout & ((!\z80_|execute_|ixy_d~9_combout ) # (!\z80_|pla_decode_|Equal19~0_combout )))) - - .dataa(\z80_|execute_|ctl_inc_dec~12_combout ), - .datab(\z80_|pla_decode_|Equal19~0_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|execute_|ctl_inc_cy~43_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~5 .lut_mask = 16'h2A00; -defparam \z80_|execute_|ctl_inc_dec~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~4_combout = (\z80_|execute_|ctl_inc_dec~5_combout & (((!\z80_|execute_|ctl_mRead~11_combout & !\z80_|execute_|ctl_state_alu~4_combout )) # (!\z80_|execute_|ctl_mWrite~4_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~11_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_inc_dec~5_combout ), - .datad(\z80_|execute_|ctl_mWrite~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~4 .lut_mask = 16'h10F0; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|fMRead~6 ( -// Equation(s): -// \z80_|execute_|fMRead~6_combout = (\z80_|pla_decode_|Equal29~0_combout & (!\z80_|execute_|ctl_state_alu~5_combout & (!\z80_|execute_|ixy_d~7_combout ))) # (!\z80_|pla_decode_|Equal29~0_combout & (((!\z80_|execute_|ctl_state_alu~5_combout & -// !\z80_|execute_|ixy_d~7_combout )) # (!\z80_|pla_decode_|Equal9~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal29~0_combout ), - .datab(\z80_|execute_|ctl_state_alu~5_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~6 .lut_mask = 16'h0357; -defparam \z80_|execute_|fMRead~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|fMRead~7 ( -// Equation(s): -// \z80_|execute_|fMRead~7_combout = (\z80_|execute_|ctl_state_alu~5_combout & (((!\z80_|pla_decode_|Equal37~0_combout & !\z80_|execute_|ctl_mRead~16_combout )))) # (!\z80_|execute_|ctl_state_alu~5_combout & (((!\z80_|pla_decode_|Equal37~0_combout & -// !\z80_|execute_|ctl_mRead~16_combout )) # (!\z80_|execute_|ixy_d~7_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~5_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|pla_decode_|Equal37~0_combout ), - .datad(\z80_|execute_|ctl_mRead~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~7 .lut_mask = 16'h111F; -defparam \z80_|execute_|fMRead~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N26 -cycloneive_lcell_comb \z80_|execute_|fMRead~8 ( -// Equation(s): -// \z80_|execute_|fMRead~8_combout = (\z80_|execute_|fMRead~7_combout & (((!\z80_|execute_|ctl_state_alu~5_combout & !\z80_|execute_|ixy_d~7_combout )) # (!\z80_|pla_decode_|Equal38~2_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~5_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|execute_|fMRead~7_combout ), - .datad(\z80_|pla_decode_|Equal38~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~8 .lut_mask = 16'h10F0; -defparam \z80_|execute_|fMRead~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~26 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~26_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~4_combout & (\z80_|execute_|ctl_reg_gp_we~1_combout & (\z80_|execute_|fMRead~6_combout & \z80_|execute_|fMRead~8_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~1_combout ), - .datac(\z80_|execute_|fMRead~6_combout ), - .datad(\z80_|execute_|fMRead~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~26 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~13 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~13_combout = (\z80_|execute_|ctl_state_alu~8_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|pla_decode_|Equal52~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal52~1_combout ), - .datab(\z80_|execute_|ctl_state_alu~8_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~13 .lut_mask = 16'hC4CC; -defparam \z80_|execute_|ctl_state_alu~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~10 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~10_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~10 .lut_mask = 16'h3331; -defparam \z80_|execute_|ctl_state_alu~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~11 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~11_combout = (\z80_|execute_|ctl_state_alu~5_combout & ((\z80_|pla_decode_|Equal52~1_combout ) # ((\z80_|execute_|ctl_state_alu~10_combout & \z80_|execute_|ctl_state_alu~7_combout )))) # -// (!\z80_|execute_|ctl_state_alu~5_combout & (((\z80_|execute_|ctl_state_alu~10_combout & \z80_|execute_|ctl_state_alu~7_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~5_combout ), - .datab(\z80_|pla_decode_|Equal52~1_combout ), - .datac(\z80_|execute_|ctl_state_alu~10_combout ), - .datad(\z80_|execute_|ctl_state_alu~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~11 .lut_mask = 16'hF888; -defparam \z80_|execute_|ctl_state_alu~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~9 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~9_combout = (\z80_|execute_|ctl_state_alu~14_combout & (((\z80_|nM1_int~2_combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) # (!\z80_|execute_|ctl_state_alu~14_combout & (\z80_|pla_decode_|Equal52~1_combout & -// ((\z80_|nM1_int~2_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~14_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal52~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~9 .lut_mask = 16'hF3A2; -defparam \z80_|execute_|ctl_state_alu~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N14 -cycloneive_lcell_comb \z80_|pla_decode_|Equal62~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal62~2_combout = (\z80_|ir_|opcode [5] & (((\z80_|execute_|ctl_state_alu~11_combout ) # (\z80_|execute_|ctl_state_alu~9_combout )) # (!\z80_|execute_|ctl_state_alu~13_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~13_combout ), - .datab(\z80_|execute_|ctl_state_alu~11_combout ), - .datac(\z80_|execute_|ctl_state_alu~9_combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal62~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal62~2 .lut_mask = 16'hFD00; -defparam \z80_|pla_decode_|Equal62~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~4_combout = (((\z80_|ir_|opcode [3] & \z80_|ir_|opcode [4])) # (!\z80_|nM1_int~2_combout )) # (!\z80_|pla_decode_|Equal62~2_combout ) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|pla_decode_|Equal62~2_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~4 .lut_mask = 16'h8FFF; -defparam \z80_|execute_|ctl_flags_pf_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~21 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~21_combout = ((!\z80_|execute_|ctl_mRead~4_combout & ((!\z80_|pla_decode_|Equal63~0_combout ) # (!\z80_|pla_decode_|Equal32~0_combout )))) # (!\z80_|nM1_int~2_combout ) - - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_mRead~4_combout ), - .datad(\z80_|pla_decode_|Equal63~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~21 .lut_mask = 16'h373F; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal64~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal64~0_combout = (!\z80_|ir_|opcode [5] & (((\z80_|execute_|ctl_state_alu~11_combout ) # (\z80_|execute_|ctl_state_alu~9_combout )) # (!\z80_|execute_|ctl_state_alu~13_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~13_combout ), - .datab(\z80_|execute_|ctl_state_alu~11_combout ), - .datac(\z80_|execute_|ctl_state_alu~9_combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal64~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal64~0 .lut_mask = 16'h00FD; -defparam \z80_|pla_decode_|Equal64~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel[0]~3 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel[0]~3_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # ((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|pla_decode_|Equal64~0_combout )) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal64~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel[0]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel[0]~3 .lut_mask = 16'hEEFF; -defparam \z80_|execute_|ctl_pf_sel[0]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~22 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~22_combout = (\z80_|execute_|ctl_flags_pf_we~4_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout & (\z80_|execute_|ctl_alu_oe~7_combout & \z80_|execute_|ctl_pf_sel[0]~3_combout ))) - - .dataa(\z80_|execute_|ctl_flags_pf_we~4_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ), - .datac(\z80_|execute_|ctl_alu_oe~7_combout ), - .datad(\z80_|execute_|ctl_pf_sel[0]~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~22 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~15 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~15_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|execute_|ctl_state_alu~14_combout & !\z80_|pla_decode_|Equal52~1_combout ))) # (!\z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(\z80_|execute_|ctl_state_alu~14_combout ), - .datab(\z80_|pla_decode_|Equal52~1_combout ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~15 .lut_mask = 16'hFF1F; -defparam \z80_|execute_|ctl_state_alu~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout = (\z80_|ir_|opcode [4] & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal63~0_combout ))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal63~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~25 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~25_combout = (\z80_|execute_|ctl_state_alu~15_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~24_combout & !\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout )) - - .dataa(\z80_|execute_|ctl_state_alu~15_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~25 .lut_mask = 16'h00A0; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~30 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~30_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~29_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~26_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout & \z80_|execute_|ctl_reg_gp_sel[0]~25_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~29_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~30 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~31 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~31_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~14_combout ) # (((\z80_|execute_|ctl_reg_gp_sel[1]~23_combout & \z80_|ir_|opcode [5])) # (!\z80_|execute_|ctl_reg_gp_sel[0]~30_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~14_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~31 .lut_mask = 16'hEFAF; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~33 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~33_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|pla_decode_|Equal11~0_combout ) # ((\z80_|execute_|ctl_mRead~5_combout )))) # (!\z80_|execute_|ixy_d~7_combout & (\z80_|pla_decode_|Equal11~0_combout & -// ((\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ctl_mRead~5_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~33 .lut_mask = 16'hECA8; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~34 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~34_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ) # ((\z80_|ir_|opcode [1] & ((!\z80_|execute_|ctl_sw_2u~5_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), - .datab(\z80_|execute_|ctl_sw_2u~5_combout ), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~34 .lut_mask = 16'hFF70; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo~20 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo~20_combout = ((\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal55~0_combout )) # (!\z80_|pla_decode_|Equal6~0_combout ) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo~20 .lut_mask = 16'hF7F7; -defparam \z80_|execute_|ctl_reg_sys_hilo~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~32 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~32_combout = (\z80_|ir_|opcode [4] & (((\z80_|execute_|ctl_state_alu~5_combout & !\z80_|execute_|ctl_reg_sys_hilo~20_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~22_combout ))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|execute_|ctl_reg_gp_sel[0]~22_combout ), - .datac(\z80_|execute_|ctl_state_alu~5_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~32 .lut_mask = 16'h22A2; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~35 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~35_combout = ((\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ) # (\z80_|execute_|ctl_reg_gp_sel[0]~32_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~35 .lut_mask = 16'hFFF3; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N18 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~5 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_de2~5_combout = (!\z80_|decode_state_|DFFE_instIY1~q & (!\z80_|decode_state_|DFFE_inst4~q & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|decode_state_|DFFE_instIY1~q ), .datab(\z80_|decode_state_|DFFE_inst4~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_de2~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_de2~5 .lut_mask = 16'h0010; -defparam \z80_|reg_control_|reg_sel_de2~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N24 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~6 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_de2~6_combout = (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & ((\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[0]~30_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_de2~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_de2~6 .lut_mask = 16'h0F0B; -defparam \z80_|reg_control_|reg_sel_de2~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N0 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_hl~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_hl~0_combout = (!\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de1~q & ((\z80_|reg_control_|reg_sel_de2~6_combout ))) # (!\z80_|reg_control_|bank_hl_de1~q & (\z80_|reg_control_|reg_sel_de2~5_combout )))) - - .dataa(\z80_|reg_control_|bank_hl_de1~q ), - .datab(\z80_|reg_control_|reg_sel_de2~5_combout ), - .datac(\z80_|reg_control_|reg_sel_de2~6_combout ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_hl~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_hl~0 .lut_mask = 16'h00E4; -defparam \z80_|reg_control_|reg_sel_hl~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N14 -cycloneive_lcell_comb \z80_|reg_control_|bank_hl_de2~0 ( -// Equation(s): -// \z80_|reg_control_|bank_hl_de2~0_combout = \z80_|reg_control_|bank_hl_de2~q $ (((\z80_|pla_decode_|Equal2~2_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|reg_control_|bank_exx~q )))) - - .dataa(\z80_|pla_decode_|Equal2~2_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|reg_control_|bank_hl_de2~q ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_control_|bank_hl_de2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|bank_hl_de2~0 .lut_mask = 16'hD2F0; -defparam \z80_|reg_control_|bank_hl_de2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y15_N15 -dffeas \z80_|reg_control_|bank_hl_de2 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_control_|bank_hl_de2~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_control_|bank_hl_de2~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_control_|bank_hl_de2 .is_wysiwyg = "true"; -defparam \z80_|reg_control_|bank_hl_de2 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N30 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_hl2~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_hl2~0_combout = (\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de2~q & (\z80_|reg_control_|reg_sel_de2~6_combout )) # (!\z80_|reg_control_|bank_hl_de2~q & ((\z80_|reg_control_|reg_sel_de2~5_combout ))))) - - .dataa(\z80_|reg_control_|reg_sel_de2~6_combout ), - .datab(\z80_|reg_control_|reg_sel_de2~5_combout ), - .datac(\z80_|reg_control_|bank_hl_de2~q ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_hl2~0 .lut_mask = 16'hAC00; -defparam \z80_|reg_control_|reg_sel_hl2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~7_combout = (\z80_|nM1_int~2_combout & (((\z80_|pla_decode_|Equal69~0_combout ) # (!\z80_|execute_|ctl_sw_1d~8_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~20_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~20_combout ), - .datab(\z80_|pla_decode_|Equal69~0_combout ), - .datac(\z80_|execute_|ctl_sw_1d~8_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~7 .lut_mask = 16'hDF00; -defparam \z80_|execute_|ctl_reg_in_hi~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~4_combout = (!\z80_|execute_|ctl_reg_in_hi~7_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout & \z80_|execute_|ctl_state_alu~15_combout )) - - .dataa(\z80_|execute_|ctl_reg_in_hi~7_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), .datac(gnd), - .datad(\z80_|execute_|ctl_state_alu~15_combout ), + .datad(\z80_|decode_state_|DFFE_instIY1~q ), .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~4_combout ), + .combout(\z80_|decode_state_|use_ixiy~combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~4 .lut_mask = 16'h1100; -defparam \z80_|execute_|ctl_reg_gp_we~4 .sum_lutc_input = "datac"; +defparam \z80_|decode_state_|use_ixiy .lut_mask = 16'hFFCC; +defparam \z80_|decode_state_|use_ixiy .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 ( +// Location: LCCOMB_X28_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ixy_d~4 ( // Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M4_ff~q & (\z80_|pla_decode_|Equal25~0_combout & !\z80_|pla_decode_|Equal12~1_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|pla_decode_|Equal25~0_combout ), - .datad(\z80_|pla_decode_|Equal12~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~3_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~6_combout & (!\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout & ((!\z80_|execute_|ctl_iorw~10_combout ) # (!\z80_|nM1_int~2_combout )))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), - .datac(\z80_|execute_|ctl_iorw~10_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~3 .lut_mask = 16'h004C; -defparam \z80_|execute_|ctl_reg_gp_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~13 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~13_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout & ((!\z80_|pla_decode_|Equal21~1_combout ) # (!\z80_|execute_|ctl_mRead~11_combout -// )))) - - .dataa(\z80_|execute_|ctl_mRead~11_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~13 .lut_mask = 16'h0013; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5~combout = (\z80_|execute_|ctl_reg_in_hi~2_combout & (\z80_|pla_decode_|Equal25~0_combout & ((\z80_|ir_|opcode [3]) # (!\z80_|pla_decode_|Equal12~0_combout )))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datab(\z80_|pla_decode_|Equal12~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal25~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5 .lut_mask = 16'hA200; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~2_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~13_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5~combout & !\z80_|execute_|ctl_sw_1d~9_combout ))) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5~combout ), - .datad(\z80_|execute_|ctl_sw_1d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~2 .lut_mask = 16'h0008; -defparam \z80_|execute_|ctl_reg_gp_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~5_combout = (!\z80_|execute_|ctl_reg_in_hi~13_combout & (\z80_|execute_|ctl_reg_gp_we~4_combout & (\z80_|execute_|ctl_reg_gp_we~3_combout & \z80_|execute_|ctl_reg_gp_we~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~13_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~4_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~3_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~5 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_gp_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~6_combout = (((\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout )) # (!\z80_|execute_|ctl_sw_4u~3_combout )) # (!\z80_|execute_|ctl_reg_gp_we~5_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_we~5_combout ), - .datab(\z80_|execute_|ctl_sw_4u~3_combout ), - .datac(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~6 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|ctl_reg_gp_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~14 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~14_combout = (!\z80_|execute_|ctl_mRead~7_combout & (((\z80_|ir_|opcode [2]) # (!\z80_|execute_|ctl_mWrite~2_combout )) # (!\z80_|ir_|opcode [1]))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|execute_|ctl_mRead~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~14 .lut_mask = 16'h00F7; -defparam \z80_|execute_|ctl_al_we~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~50 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~50_combout = (!\z80_|execute_|ctl_flags_oe~1_combout & (((!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|execute_|ctl_flags_oe~1_combout ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~50 .lut_mask = 16'h1033; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~26 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~26_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ) # ((\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mWrite~4_combout ) # (!\z80_|execute_|ctl_al_we~14_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~4_combout ), - .datab(\z80_|execute_|ctl_al_we~14_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~26 .lut_mask = 16'hFBF0; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~27 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~27_combout = (\z80_|execute_|rsel3~combout & (((!\z80_|execute_|ctl_reg_gp_sel[0]~20_combout & \z80_|nM1_int~2_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~20_combout ), - .datab(\z80_|execute_|rsel3~combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~27 .lut_mask = 16'h40CC; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~28 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~28_combout = (((\z80_|execute_|ctl_ir_we~7_combout ) # (\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo~20_combout ) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), - .datac(\z80_|execute_|ctl_ir_we~7_combout ), - .datad(\z80_|execute_|ctl_ir_we~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~28 .lut_mask = 16'hFFF7; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~29 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~29_combout = (\z80_|execute_|ctl_state_alu~5_combout & ((\z80_|execute_|ctl_iorw~11_combout ) # ((\z80_|execute_|ctl_state_alu~14_combout ) # (\z80_|execute_|ctl_reg_gp_hilo[0]~28_combout )))) - - .dataa(\z80_|execute_|ctl_iorw~11_combout ), - .datab(\z80_|execute_|ctl_state_alu~5_combout ), - .datac(\z80_|execute_|ctl_state_alu~14_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~29 .lut_mask = 16'hCCC8; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal9~1_combout & \z80_|sequencer_|M5~q )) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|pla_decode_|Equal9~1_combout ), - .datac(gnd), - .datad(\z80_|sequencer_|M5~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 .lut_mask = 16'h4400; -defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~31 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~31_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout & (((!\z80_|execute_|ctl_mRead~8_combout & !\z80_|execute_|ctl_mRead~10_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~8_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), - .datad(\z80_|execute_|ctl_mRead~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~31 .lut_mask = 16'h0307; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~51 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~51_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # ((\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T2_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|execute_|nextM~2_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~51 .lut_mask = 16'h0F08; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~30 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~30_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ) # (((\z80_|pla_decode_|Equal6~1_combout & \z80_|execute_|ixy_d~7_combout )) # (!\z80_|execute_|ctl_mRead~25_combout )) - - .dataa(\z80_|pla_decode_|Equal6~1_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_mRead~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~30 .lut_mask = 16'hECFF; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~32 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~32_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ) # ((\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ) # -// (!\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~32 .lut_mask = 16'hFFEF; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~34 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~34_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ) # (((\z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ) # (\z80_|execute_|ctl_reg_gp_hilo[0]~32_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~34 .lut_mask = 16'hFFFB; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~24 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout = ((\z80_|execute_|ctl_reg_gp_sel~36_combout ) # (!\z80_|execute_|ctl_sw_2u~5_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_sel~36_combout ), - .datad(\z80_|execute_|ctl_sw_2u~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~24 .lut_mask = 16'hF5FF; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~25 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~25_combout = (\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|execute_|rsel0~combout & ((\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout )))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & -// (((\z80_|execute_|rsel0~combout & \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout )) # (!\z80_|execute_|setM1~48_combout ))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|execute_|rsel0~combout ), - .datac(\z80_|execute_|setM1~48_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~25 .lut_mask = 16'hCD05; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~36 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~36_combout = (\z80_|pla_decode_|Equal11~0_combout & (!\z80_|execute_|ixy_d~6_combout & (!\z80_|execute_|ixy_d~9_combout ))) # (!\z80_|pla_decode_|Equal11~0_combout & (((!\z80_|pla_decode_|Equal10~0_combout )) # -// (!\z80_|execute_|ixy_d~6_combout ))) - - .dataa(\z80_|pla_decode_|Equal11~0_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|pla_decode_|Equal10~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~36 .lut_mask = 16'h1357; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout = (!\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal2~1_combout & (\z80_|execute_|ctl_eval_cond~0_combout & !\z80_|ir_|opcode [1]))) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|pla_decode_|Equal2~1_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 .lut_mask = 16'h0040; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N4 -cycloneive_lcell_comb \z80_|execute_|setM1~40 ( -// Equation(s): -// \z80_|execute_|setM1~40_combout = (!\z80_|pla_decode_|Equal4~0_combout & ((!\z80_|pla_decode_|Equal8~0_combout ) # (!\z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal4~0_combout ), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal8~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~40 .lut_mask = 16'h1155; -defparam \z80_|execute_|setM1~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~18 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout & (!\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout & ((\z80_|execute_|setM1~40_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|setM1~40_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~18 .lut_mask = 16'h1101; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~37 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~37_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout & \z80_|execute_|ctl_reg_gp_sel[1]~26_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~37 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~38 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ) # ((!\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~38 .lut_mask = 16'hEFFF; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~93 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~93_combout = (!\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & ((\z80_|reg_control_|reg_sel_hl~0_combout ) # (\z80_|reg_control_|reg_sel_hl2~0_combout )))) - - .dataa(\z80_|reg_control_|reg_sel_hl~0_combout ), - .datab(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~93_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~93 .lut_mask = 16'h0E00; -defparam \z80_|reg_file_|gdfx_temp0[0]~93 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N28 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_de~0_combout = (!\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de1~q & (\z80_|reg_control_|reg_sel_de2~5_combout )) # (!\z80_|reg_control_|bank_hl_de1~q & ((\z80_|reg_control_|reg_sel_de2~6_combout ))))) - - .dataa(\z80_|reg_control_|bank_hl_de1~q ), - .datab(\z80_|reg_control_|reg_sel_de2~5_combout ), - .datac(\z80_|reg_control_|reg_sel_de2~6_combout ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_de~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_de~0 .lut_mask = 16'h00D8; -defparam \z80_|reg_control_|reg_sel_de~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N0 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_50 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_50~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_de~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_de~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_50 .lut_mask = 16'h0C00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N0 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout = (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 .lut_mask = 16'h0F00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N18 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout = (\z80_|decode_state_|DFFE_inst4~q & (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 .lut_mask = 16'h0080; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N30 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|reg_control_|bank_exx~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 .lut_mask = 16'h0400; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N12 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|reg_control_|bank_exx~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 .lut_mask = 16'h0100; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~9_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|execute_|ctl_mRead~4_combout )))) # (!\z80_|pla_decode_|Equal47~0_combout -// & (((!\z80_|execute_|ixy_d~7_combout )) # (!\z80_|execute_|ctl_mRead~4_combout ))) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|execute_|ctl_mRead~4_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~9 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_reg_in_hi~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~10 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~10_combout = (\z80_|execute_|ctl_reg_in_hi~9_combout & (\z80_|execute_|ctl_reg_in_hi~8_combout & \z80_|execute_|ctl_reg_gp_we~5_combout )) - - .dataa(\z80_|execute_|ctl_reg_in_hi~9_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~8_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_gp_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~10 .lut_mask = 16'h8800; -defparam \z80_|execute_|ctl_reg_in_hi~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~19 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~19_combout = (\z80_|execute_|ctl_mRead~22_combout & (\z80_|reg_control_|reg_sys_we_lo~6_combout & ((!\z80_|execute_|ixy_d~15_combout ) # (!\z80_|sequencer_|DFFE_T3_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|execute_|ctl_mRead~22_combout ), - .datac(\z80_|reg_control_|reg_sys_we_lo~6_combout ), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~19 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_reg_sel_wz~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout = (\z80_|pla_decode_|Equal24~0_combout & (\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|ir_|opcode [3] & \z80_|ir_|opcode [4]))) - - .dataa(\z80_|pla_decode_|Equal24~0_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_lo~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_lo~8_combout = (((\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ) # (!\z80_|execute_|ctl_reg_sel_wz~19_combout )) # (!\z80_|execute_|ctl_reg_in_hi~10_combout )) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ) - - .dataa(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~10_combout ), - .datac(\z80_|execute_|ctl_reg_sel_wz~19_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_lo~8 .lut_mask = 16'hFF7F; -defparam \z80_|execute_|ctl_reg_in_lo~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y12_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~19 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~19_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ) # ((\z80_|execute_|ctl_sw_4u~6_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ) # (\z80_|execute_|ctl_reg_in_lo~8_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|execute_|ctl_sw_4u~6_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .datad(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~19 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp0[0]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~4_combout = (\z80_|pla_decode_|Equal6~1_combout & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_M1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|pla_decode_|Equal6~1_combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~4 .lut_mask = 16'h00B0; -defparam \z80_|execute_|ctl_reg_use_sp~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~5_combout = (\z80_|execute_|ctl_reg_use_sp~4_combout ) # ((\z80_|execute_|ctl_mRead~17_combout & ((\z80_|execute_|ctl_reg_in_hi~2_combout ) # (\z80_|execute_|ctl_state_alu~6_combout )))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datab(\z80_|execute_|ctl_reg_use_sp~4_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_mRead~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~5 .lut_mask = 16'hFECC; -defparam \z80_|execute_|ctl_reg_use_sp~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~6_combout = (\z80_|execute_|ctl_reg_use_sp~5_combout ) # ((!\z80_|execute_|ctl_reg_use_sp~3_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[1]~26_combout )) - - .dataa(\z80_|execute_|ctl_reg_use_sp~5_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), - .datad(\z80_|execute_|ctl_reg_use_sp~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~6 .lut_mask = 16'hAFFF; -defparam \z80_|execute_|ctl_reg_use_sp~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N2 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout = (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal21~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal21~2_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal40~0_combout & !\z80_|ir_|opcode [5])) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal40~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal21~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal21~2 .lut_mask = 16'h0808; -defparam \z80_|pla_decode_|Equal21~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N20 -cycloneive_lcell_comb \z80_|reg_control_|bank_af~0 ( -// Equation(s): -// \z80_|reg_control_|bank_af~0_combout = \z80_|reg_control_|bank_af~q $ (((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|pla_decode_|Equal21~2_combout & \z80_|pla_decode_|Equal32~0_combout )))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|pla_decode_|Equal21~2_combout ), - .datac(\z80_|reg_control_|bank_af~q ), - .datad(\z80_|pla_decode_|Equal32~0_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|bank_af~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|bank_af~0 .lut_mask = 16'hB4F0; -defparam \z80_|reg_control_|bank_af~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y12_N21 -dffeas \z80_|reg_control_|bank_af ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_control_|bank_af~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_control_|bank_af~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_control_|bank_af .is_wysiwyg = "true"; -defparam \z80_|reg_control_|bank_af .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N28 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_af~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_af~0_combout = (!\z80_|execute_|ctl_reg_use_sp~6_combout & (!\z80_|reg_control_|bank_af~q & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datab(\z80_|reg_control_|bank_af~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_af~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_af~0 .lut_mask = 16'h1000; -defparam \z80_|reg_control_|reg_sel_af~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N4 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_34 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_34~combout = (\z80_|reg_control_|reg_sel_af~0_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & !\z80_|execute_|ctl_reg_gp_we~6_combout )) - - .dataa(\z80_|reg_control_|reg_sel_af~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_34 .lut_mask = 16'h0088; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N10 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_af2~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_af2~0_combout = (!\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|reg_control_|bank_af~q & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datab(\z80_|reg_control_|bank_af~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_af2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_af2~0 .lut_mask = 16'h4000; -defparam \z80_|reg_control_|reg_sel_af2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N18 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_30 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_30~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_af2~0_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datac(gnd), - .datad(\z80_|reg_control_|reg_sel_af2~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_30 .lut_mask = 16'h2200; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~12 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~12_combout = (\z80_|execute_|ixy_d~6_combout & (!\z80_|pla_decode_|Equal19~0_combout & ((!\z80_|pla_decode_|Equal9~1_combout )))) # (!\z80_|execute_|ixy_d~6_combout & (((!\z80_|pla_decode_|Equal9~1_combout ) # -// (!\z80_|execute_|ctl_reg_in_hi~2_combout )))) - - .dataa(\z80_|pla_decode_|Equal19~0_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~12 .lut_mask = 16'h035F; -defparam \z80_|execute_|ctl_reg_sel_wz~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~4_combout = (\z80_|ir_|opcode [5]) # ((!\z80_|pla_decode_|Equal13~1_combout ) # (!\z80_|pla_decode_|Equal13~0_combout )) - - .dataa(\z80_|ir_|opcode [5]), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|pla_decode_|Equal13~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~4 .lut_mask = 16'hAFFF; -defparam \z80_|execute_|ctl_flags_bus~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~6_combout = (\z80_|pla_decode_|Equal44~0_combout ) # ((\z80_|pla_decode_|Equal52~0_combout & \z80_|pla_decode_|Equal33~0_combout )) - - .dataa(\z80_|pla_decode_|Equal52~0_combout ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|pla_decode_|Equal44~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~6 .lut_mask = 16'hF8F8; -defparam \z80_|execute_|ctl_flags_bus~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~7_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (((\z80_|execute_|ctl_flags_bus~6_combout ) # (!\z80_|execute_|ctl_flags_bus~5_combout )) # (!\z80_|execute_|ctl_flags_bus~4_combout ))) - - .dataa(\z80_|execute_|ctl_flags_bus~4_combout ), - .datab(\z80_|execute_|ctl_flags_bus~5_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_flags_bus~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~7 .lut_mask = 16'hF070; -defparam \z80_|execute_|ctl_flags_bus~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N22 -cycloneive_lcell_comb \z80_|execute_|fMRead~24 ( -// Equation(s): -// \z80_|execute_|fMRead~24_combout = (\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_state_alu~4_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_state_alu~14_combout )))) # -// (!\z80_|execute_|ctl_ir_we~12_combout & (((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_state_alu~14_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~12_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_state_alu~14_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~24 .lut_mask = 16'h0777; -defparam \z80_|execute_|fMRead~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~13 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~13_combout = (\z80_|execute_|ctl_alu_shift_oe~20_combout & (\z80_|execute_|ctl_bus_db_oe~3_combout & \z80_|execute_|ctl_flags_bus~12_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_shift_oe~20_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~3_combout ), - .datad(\z80_|execute_|ctl_flags_bus~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~13 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_flags_bus~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~combout = (\z80_|execute_|ctl_flags_bus~7_combout ) # (((\z80_|execute_|ctl_flags_hf2_we~combout ) # (!\z80_|execute_|ctl_flags_bus~13_combout )) # (!\z80_|execute_|fMRead~24_combout )) - - .dataa(\z80_|execute_|ctl_flags_bus~7_combout ), - .datab(\z80_|execute_|fMRead~24_combout ), - .datac(\z80_|execute_|ctl_flags_hf2_we~combout ), - .datad(\z80_|execute_|ctl_flags_bus~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus .lut_mask = 16'hFBFF; -defparam \z80_|execute_|ctl_flags_bus .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~3 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~3_combout = ((!\z80_|pla_decode_|Equal11~0_combout & ((!\z80_|execute_|ctl_mWrite~2_combout ) # (!\z80_|pla_decode_|Equal55~0_combout )))) # (!\z80_|execute_|ctl_mWrite~7_combout ) - - .dataa(\z80_|pla_decode_|Equal11~0_combout ), - .datab(\z80_|execute_|ctl_mWrite~7_combout ), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|execute_|ctl_mWrite~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~3 .lut_mask = 16'h3777; -defparam \z80_|execute_|ctl_inc_dec~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~14 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~14_combout = (\z80_|execute_|ctl_inc_dec~3_combout & (!\z80_|nM1_int~2_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout & \z80_|execute_|fMRead~3_combout ))) - - .dataa(\z80_|execute_|ctl_inc_dec~3_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), - .datad(\z80_|execute_|fMRead~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~14 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~2_combout = ((!\z80_|execute_|ctl_mRead~15_combout & ((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout )))) # (!\z80_|execute_|ixy_d~5_combout ) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|ctl_mRead~15_combout ), - .datac(\z80_|pla_decode_|Equal25~0_combout ), - .datad(\z80_|pla_decode_|Equal12~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~2 .lut_mask = 16'h7757; -defparam \z80_|execute_|ctl_reg_sel_pc~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~3_combout = (\z80_|execute_|ctl_reg_sel_pc~2_combout & (((!\z80_|execute_|ctl_mRead~10_combout & !\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~2_combout ), - .datac(\z80_|pla_decode_|Equal19~0_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~3 .lut_mask = 16'h04CC; -defparam \z80_|execute_|ctl_reg_sel_pc~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~6_combout = (\z80_|pla_decode_|Equal34~0_combout & (!\z80_|execute_|ixy_d~5_combout & ((!\z80_|execute_|ctl_alu_op_low~8_combout ) # (!\z80_|execute_|ixy_d~16_combout )))) # (!\z80_|pla_decode_|Equal34~0_combout & -// (((!\z80_|execute_|ctl_alu_op_low~8_combout )) # (!\z80_|execute_|ixy_d~16_combout ))) - - .dataa(\z80_|pla_decode_|Equal34~0_combout ), - .datab(\z80_|execute_|ixy_d~16_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~6 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_reg_sel_pc~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~5_combout = ((!\z80_|execute_|ctl_mRead~8_combout & (!\z80_|execute_|ctl_mRead~17_combout & !\z80_|execute_|ctl_mRead~9_combout ))) # (!\z80_|execute_|ixy_d~5_combout ) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|ctl_mRead~8_combout ), - .datac(\z80_|execute_|ctl_mRead~17_combout ), - .datad(\z80_|execute_|ctl_mRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~5 .lut_mask = 16'h5557; -defparam \z80_|execute_|ctl_reg_sel_pc~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~4_combout = ((!\z80_|execute_|ixy_d~10_combout & ((!\z80_|pla_decode_|Equal21~0_combout ) # (!\z80_|pla_decode_|Equal24~0_combout )))) # (!\z80_|execute_|ctl_alu_op_low~8_combout ) - - .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datab(\z80_|pla_decode_|Equal24~0_combout ), - .datac(\z80_|pla_decode_|Equal21~0_combout ), - .datad(\z80_|execute_|ixy_d~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~4 .lut_mask = 16'h557F; -defparam \z80_|execute_|ctl_reg_sel_pc~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~7_combout = (\z80_|execute_|ctl_reg_sel_pc~3_combout & (\z80_|execute_|ctl_reg_sel_pc~6_combout & (\z80_|execute_|ctl_reg_sel_pc~5_combout & \z80_|execute_|ctl_reg_sel_pc~4_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~3_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~6_combout ), - .datac(\z80_|execute_|ctl_reg_sel_pc~5_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~7 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sel_pc~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~8_combout = (\z80_|pla_decode_|Equal3~0_combout & ((\z80_|pla_decode_|Equal24~0_combout ) # ((\z80_|pla_decode_|Equal25~0_combout & !\z80_|pla_decode_|Equal12~1_combout )))) # (!\z80_|pla_decode_|Equal3~0_combout & -// (((\z80_|pla_decode_|Equal25~0_combout & !\z80_|pla_decode_|Equal12~1_combout )))) - - .dataa(\z80_|pla_decode_|Equal3~0_combout ), - .datab(\z80_|pla_decode_|Equal24~0_combout ), - .datac(\z80_|pla_decode_|Equal25~0_combout ), - .datad(\z80_|pla_decode_|Equal12~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~8 .lut_mask = 16'h88F8; -defparam \z80_|execute_|ctl_reg_sel_pc~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~9_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & ((\z80_|pla_decode_|Equal34~0_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~8_combout ) # (\z80_|execute_|ctl_mRead~17_combout )))) - - .dataa(\z80_|pla_decode_|Equal34~0_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~8_combout ), - .datac(\z80_|execute_|ctl_mRead~17_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~9 .lut_mask = 16'hFE00; -defparam \z80_|execute_|ctl_reg_sel_pc~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~10 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~10_combout = (\z80_|execute_|ctl_reg_sel_pc~7_combout & (!\z80_|execute_|ctl_reg_sel_pc~9_combout & ((!\z80_|pla_decode_|Equal41~2_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~7_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~9_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|pla_decode_|Equal41~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~10 .lut_mask = 16'h0222; -defparam \z80_|execute_|ctl_reg_sel_pc~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~13 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~13_combout = (\z80_|execute_|ctl_reg_sel_pc~10_combout & (\z80_|execute_|ctl_inc_cy~94_combout & (\z80_|execute_|ctl_inc_cy~87_combout & \z80_|execute_|ctl_inc_cy~42_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~10_combout ), - .datab(\z80_|execute_|ctl_inc_cy~94_combout ), - .datac(\z80_|execute_|ctl_inc_cy~87_combout ), - .datad(\z80_|execute_|ctl_inc_cy~42_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~13 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~15 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~15_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout & -// !\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~15 .lut_mask = 16'h0020; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~29 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~29_combout = (!\z80_|execute_|ctl_mRead~14_combout & ((\z80_|ir_|opcode [5]) # ((\z80_|ir_|opcode [3]) # (!\z80_|pla_decode_|Equal12~0_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~14_combout ), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal12~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~29 .lut_mask = 16'h5455; -defparam \z80_|execute_|ctl_bus_inc_oe~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~13 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~13_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|ir_|opcode [3] & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~13 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_mRead~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N8 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~49 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~49_combout = (!\z80_|pla_decode_|Equal35~0_combout & (((\z80_|ir_|opcode [3]) # (\z80_|ir_|opcode [4])) # (!\z80_|pla_decode_|Equal24~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal24~0_combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|pla_decode_|Equal35~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~49 .lut_mask = 16'h00FD; -defparam \z80_|execute_|pc_inc_hold~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~9_combout = (!\z80_|execute_|ctl_mRead~10_combout & (!\z80_|execute_|ctl_mRead~15_combout & (!\z80_|pla_decode_|Equal41~2_combout & !\z80_|execute_|ctl_mRead~8_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|execute_|ctl_mRead~15_combout ), - .datac(\z80_|pla_decode_|Equal41~2_combout ), - .datad(\z80_|execute_|ctl_mRead~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~9 .lut_mask = 16'h0001; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~10 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~10_combout = (\z80_|execute_|pc_inc_hold~49_combout & (!\z80_|pla_decode_|Equal19~0_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~9_combout )) - - .dataa(\z80_|execute_|pc_inc_hold~49_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal19~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~10 .lut_mask = 16'h0A00; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~28 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~28_combout = (!\z80_|pla_decode_|Equal33~2_combout & (((!\z80_|pla_decode_|Equal49~0_combout & !\z80_|pla_decode_|Equal50~0_combout )) # (!\z80_|decode_state_|use_ixiy~combout ))) - - .dataa(\z80_|pla_decode_|Equal33~2_combout ), - .datab(\z80_|pla_decode_|Equal49~0_combout ), - .datac(\z80_|decode_state_|use_ixiy~combout ), - .datad(\z80_|pla_decode_|Equal50~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~28 .lut_mask = 16'h0515; -defparam \z80_|execute_|pc_inc_hold~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|setM1~35 ( -// Equation(s): -// \z80_|execute_|setM1~35_combout = (!\z80_|pla_decode_|Equal6~1_combout & (!\z80_|pla_decode_|Equal39~0_combout & !\z80_|pla_decode_|Equal40~1_combout )) - - .dataa(gnd), - .datab(\z80_|pla_decode_|Equal6~1_combout ), - .datac(\z80_|pla_decode_|Equal39~0_combout ), - .datad(\z80_|pla_decode_|Equal40~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~35 .lut_mask = 16'h0003; -defparam \z80_|execute_|setM1~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N16 -cycloneive_lcell_comb \z80_|execute_|setM1~36 ( -// Equation(s): -// \z80_|execute_|setM1~36_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout & (!\z80_|execute_|ctl_mRead~9_combout & (\z80_|execute_|pc_inc_hold~28_combout & \z80_|execute_|setM1~35_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), - .datab(\z80_|execute_|ctl_mRead~9_combout ), - .datac(\z80_|execute_|pc_inc_hold~28_combout ), - .datad(\z80_|execute_|setM1~35_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~36 .lut_mask = 16'h2000; -defparam \z80_|execute_|setM1~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y18_N2 -cycloneive_lcell_comb \z80_|execute_|fMRead~5 ( -// Equation(s): -// \z80_|execute_|fMRead~5_combout = (!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|execute_|ctl_mRead~13_combout & (!\z80_|pla_decode_|Equal52~1_combout & \z80_|execute_|setM1~36_combout ))) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|execute_|ctl_mRead~13_combout ), - .datac(\z80_|pla_decode_|Equal52~1_combout ), - .datad(\z80_|execute_|setM1~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~5 .lut_mask = 16'h0100; -defparam \z80_|execute_|fMRead~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y18_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~31 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~31_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout & (((\z80_|execute_|ctl_bus_inc_oe~29_combout & \z80_|execute_|fMRead~5_combout )) # (!\z80_|execute_|ctl_alu_op_low~8_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~29_combout ), - .datad(\z80_|execute_|fMRead~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~31 .lut_mask = 16'hA222; -defparam \z80_|execute_|ctl_bus_inc_oe~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N20 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~29 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~29_combout = (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T4_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~29 .lut_mask = 16'hC8C8; -defparam \z80_|execute_|pc_inc_hold~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~1 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we~1_combout = (\z80_|execute_|pc_inc_hold~29_combout & ((\z80_|pla_decode_|Equal10~0_combout ) # (\z80_|execute_|ctl_mRead~36_combout ))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|execute_|ctl_mRead~36_combout ), - .datac(gnd), - .datad(\z80_|execute_|pc_inc_hold~29_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we~1 .lut_mask = 16'hEE00; -defparam \z80_|execute_|ctl_reg_sys_we~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we~2_combout = (!\z80_|execute_|ctl_reg_sys_we~1_combout & (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|execute_|ctl_mWrite~16_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|execute_|ctl_reg_sys_we~1_combout ), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|execute_|ctl_mWrite~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we~2 .lut_mask = 16'h1113; -defparam \z80_|execute_|ctl_reg_sys_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N14 -cycloneive_lcell_comb \z80_|pla_decode_|Equal33~3 ( -// Equation(s): -// \z80_|pla_decode_|Equal33~3_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal33~0_combout & (\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|decode_state_|use_ixiy~combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal33~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal33~3 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal33~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we~0_combout = (\z80_|execute_|ixy_d~5_combout & ((\z80_|pla_decode_|Equal33~3_combout ) # ((\z80_|pla_decode_|Equal6~1_combout ) # (!\z80_|execute_|pc_inc_hold~49_combout )))) - - .dataa(\z80_|pla_decode_|Equal33~3_combout ), - .datab(\z80_|execute_|pc_inc_hold~49_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|pla_decode_|Equal6~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we~0 .lut_mask = 16'hF0B0; -defparam \z80_|execute_|ctl_reg_sys_we~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we~3_combout = (((\z80_|execute_|ctl_reg_sys_we~0_combout ) # (\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout )) # (!\z80_|execute_|ctl_reg_sys_we~2_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~31_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~31_combout ), - .datab(\z80_|execute_|ctl_reg_sys_we~2_combout ), - .datac(\z80_|execute_|ctl_reg_sys_we~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we~3 .lut_mask = 16'hFFF7; -defparam \z80_|execute_|ctl_reg_sys_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we_lo~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we_lo~2_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal55~0_combout & \z80_|pla_decode_|Equal6~0_combout )) - - .dataa(\z80_|ir_|opcode [5]), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we_lo~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we_lo~2 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_reg_sys_we_lo~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we_lo~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we_lo~3_combout = (\z80_|execute_|ctl_reg_sys_we_lo~2_combout ) # ((\z80_|pla_decode_|Equal9~1_combout ) # ((\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal8~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|pla_decode_|Equal8~0_combout ), - .datac(\z80_|execute_|ctl_reg_sys_we_lo~2_combout ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we_lo~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we_lo~3 .lut_mask = 16'hFFF8; -defparam \z80_|execute_|ctl_reg_sys_we_lo~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we_lo~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we_lo~4_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|execute_|ctl_reg_sys_we_lo~3_combout & \z80_|sequencer_|DFFE_M2_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|execute_|ctl_reg_sys_we_lo~3_combout ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we_lo~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we_lo~4 .lut_mask = 16'h8080; -defparam \z80_|execute_|ctl_reg_sys_we_lo~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N20 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~combout = (\z80_|execute_|ctl_reg_sys_we~3_combout ) # ((\z80_|execute_|ctl_reg_sys_we_lo~4_combout ) # ((!\z80_|reg_control_|reg_sys_we_lo~7_combout ) # (!\z80_|reg_control_|reg_sys_we_lo~4_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_we~3_combout ), - .datab(\z80_|execute_|ctl_reg_sys_we_lo~4_combout ), - .datac(\z80_|reg_control_|reg_sys_we_lo~4_combout ), - .datad(\z80_|reg_control_|reg_sys_we_lo~7_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo .lut_mask = 16'hEFFF; -defparam \z80_|reg_control_|reg_sys_we_lo .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_ir~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_ir~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_ir~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_ir~0 .lut_mask = 16'h3330; -defparam \z80_|execute_|ctl_reg_sel_ir~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_ir~1 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_ir~1_combout = ((\z80_|execute_|ctl_reg_sel_ir~0_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & !\z80_|execute_|ctl_flags_bus~4_combout ))) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ) - - .dataa(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_flags_bus~4_combout ), - .datad(\z80_|execute_|ctl_reg_sel_ir~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_ir~1 .lut_mask = 16'hFF5D; -defparam \z80_|execute_|ctl_reg_sel_ir~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~9_combout = (\z80_|execute_|ctl_inc_cy~34_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|sequencer_|M5~q ) # (!\z80_|pla_decode_|Equal19~0_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|execute_|ctl_inc_cy~34_combout ), - .datac(\z80_|pla_decode_|Equal19~0_combout ), - .datad(\z80_|sequencer_|M5~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~9 .lut_mask = 16'h8CCC; -defparam \z80_|execute_|ctl_reg_out_lo~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~36 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~36_combout = (\z80_|execute_|ctl_alu_op_low~14_combout ) # ((\z80_|sequencer_|DFFE_T4_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|pla_decode_|Equal48~0_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|pla_decode_|Equal48~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~36 .lut_mask = 16'hF2F0; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~12 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[0]~12_combout = (((\z80_|ir_|opcode [3] & \z80_|execute_|ctl_reg_sys_hilo[1]~36_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout )) # (!\z80_|execute_|ctl_reg_out_lo~9_combout ) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|execute_|ctl_reg_out_lo~9_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~12 .lut_mask = 16'hBF3F; -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout = (\z80_|sequencer_|DFFE_T5_ff~q & \z80_|execute_|ixy_d~15_combout ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T5_ff~q ), - .datac(gnd), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 .lut_mask = 16'hCC00; -defparam \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~4_combout = (\z80_|reg_control_|reg_sel_pc~2_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~4_combout & (\z80_|execute_|ctl_alu_oe~4_combout & !\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ))) - - .dataa(\z80_|reg_control_|reg_sel_pc~2_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), - .datac(\z80_|execute_|ctl_alu_oe~4_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~4 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_in_hi~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~4_combout = ((!\z80_|pla_decode_|Equal34~0_combout & ((!\z80_|pla_decode_|Equal3~1_combout ) # (!\z80_|pla_decode_|Equal19~1_combout )))) # (!\z80_|execute_|ctl_reg_in_hi~2_combout ) - - .dataa(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datab(\z80_|pla_decode_|Equal34~0_combout ), - .datac(\z80_|pla_decode_|Equal19~1_combout ), - .datad(\z80_|pla_decode_|Equal3~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~4 .lut_mask = 16'h5777; -defparam \z80_|execute_|ctl_reg_sel_wz~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|execute_|comb~0_combout & \z80_|execute_|ixy_d~6_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal52~0_combout ), - .datac(\z80_|execute_|comb~0_combout ), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~5_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & (((!\z80_|execute_|ctl_mRead~10_combout & !\z80_|execute_|ctl_mRead~8_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|execute_|ctl_mRead~8_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~5 .lut_mask = 16'h001F; -defparam \z80_|execute_|ctl_reg_sel_wz~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~6_combout = (\z80_|execute_|ctl_reg_sel_wz~4_combout & \z80_|execute_|ctl_reg_sel_wz~5_combout ) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~4_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_sel_wz~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~6 .lut_mask = 16'hAA00; -defparam \z80_|execute_|ctl_reg_sel_wz~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~7_combout = (\z80_|execute_|ctl_bus_db_oe~0_combout & (\z80_|execute_|ctl_reg_in_hi~4_combout & (\z80_|execute_|ctl_reg_in_hi~3_combout & \z80_|execute_|ctl_reg_sel_wz~6_combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_oe~0_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~4_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~3_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~7 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sel_wz~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo~16 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo~16_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|execute_|ctl_mRead~14_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|execute_|ctl_mRead~14_combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo~16 .lut_mask = 16'h80C0; -defparam \z80_|execute_|ctl_reg_sys_hilo~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~11 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~11_combout = (!\z80_|execute_|ctl_reg_sys_hilo~16_combout & (((!\z80_|execute_|ctl_mRead~36_combout & !\z80_|pla_decode_|Equal10~0_combout )) # (!\z80_|execute_|ctl_mWrite~7_combout ))) - - .dataa(\z80_|execute_|ctl_mWrite~7_combout ), - .datab(\z80_|execute_|ctl_mRead~36_combout ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~11 .lut_mask = 16'h0057; -defparam \z80_|execute_|ctl_reg_sel_pc~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~17 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~17_combout = (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~17 .lut_mask = 16'hE0F0; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~12 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~12_combout = (\z80_|execute_|ctl_reg_sel_pc~11_combout & (((\z80_|execute_|ctl_flags_bus~5_combout & \z80_|execute_|ctl_al_we~13_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~11_combout ), - .datab(\z80_|execute_|ctl_flags_bus~5_combout ), - .datac(\z80_|execute_|ctl_al_we~13_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~12 .lut_mask = 16'h80AA; -defparam \z80_|execute_|ctl_reg_sel_pc~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~13 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~13_combout = (\z80_|execute_|ctl_reg_sel_pc~12_combout & (\z80_|execute_|setM1~52_combout & ((!\z80_|pla_decode_|Equal6~1_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~12_combout ), - .datac(\z80_|execute_|setM1~52_combout ), - .datad(\z80_|pla_decode_|Equal6~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~13 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_reg_sel_pc~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~4_combout = (!\z80_|execute_|ctl_mRead~4_combout & (!\z80_|execute_|ixy_d~16_combout & (!\z80_|execute_|ixy_d~10_combout & !\z80_|execute_|ctl_mRead~5_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~4_combout ), - .datab(\z80_|execute_|ixy_d~16_combout ), - .datac(\z80_|execute_|ixy_d~10_combout ), - .datad(\z80_|execute_|ctl_mRead~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~4 .lut_mask = 16'h0001; -defparam \z80_|execute_|ctl_al_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~38 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~38_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ctl_al_we~4_combout )))) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|pla_decode_|Equal34~0_combout ), - .datad(\z80_|execute_|ctl_al_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~38 .lut_mask = 16'h2022; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y18_N24 -cycloneive_lcell_comb \z80_|execute_|fMRead~0 ( -// Equation(s): -// \z80_|execute_|fMRead~0_combout = ((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|fMRead~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~0 .lut_mask = 16'h5D5D; -defparam \z80_|execute_|fMRead~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~24 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~24_combout = (!\z80_|pla_decode_|Equal6~1_combout & (\z80_|execute_|ctl_bus_db_oe~1_combout & !\z80_|pla_decode_|Equal52~1_combout )) - - .dataa(gnd), - .datab(\z80_|pla_decode_|Equal6~1_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .datad(\z80_|pla_decode_|Equal52~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~24 .lut_mask = 16'h0030; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~25 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~25_combout = (!\z80_|execute_|fMRead~0_combout & ((!\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), - .datab(gnd), - .datac(\z80_|execute_|fMRead~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~25 .lut_mask = 16'h050F; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~4 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~4_combout = ((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~4 .lut_mask = 16'h0FAF; -defparam \z80_|execute_|ctl_inc_dec~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~21 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~21_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & (\z80_|execute_|ctl_reg_sys_hilo~20_combout & ((\z80_|execute_|ctl_inc_dec~4_combout ) # (!\z80_|pla_decode_|Equal33~3_combout )))) # -// (!\z80_|execute_|ctl_alu_op_low~8_combout & (((\z80_|execute_|ctl_inc_dec~4_combout ) # (!\z80_|pla_decode_|Equal33~3_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), - .datac(\z80_|execute_|ctl_inc_dec~4_combout ), - .datad(\z80_|pla_decode_|Equal33~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~21 .lut_mask = 16'hD0DD; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~9_combout = (!\z80_|execute_|ctl_ir_we~8_combout & (!\z80_|execute_|ctl_mRead~15_combout & !\z80_|execute_|ctl_ir_we~14_combout )) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_mRead~15_combout ), - .datad(\z80_|execute_|ctl_ir_we~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~9 .lut_mask = 16'h0005; -defparam \z80_|execute_|ctl_reg_sel_wz~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|execute_|ctl_ir_we~12_combout & \z80_|sequencer_|DFFE_M2_ff~q )) +// \z80_|execute_|ixy_d~4_combout = (!\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) .dataa(gnd), .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~22 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~22_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~21_combout & (!\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout & ((\z80_|execute_|ctl_reg_sel_wz~9_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout -// )))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ), - .datac(\z80_|execute_|ctl_reg_sel_wz~9_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~22 .lut_mask = 16'h00C4; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~23 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~23_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout & (((\z80_|execute_|pc_inc_hold~49_combout & !\z80_|pla_decode_|Equal6~1_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~49_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ), - .datac(\z80_|pla_decode_|Equal6~1_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~23 .lut_mask = 16'h08CC; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~8_combout = (!\z80_|execute_|ctl_mRead~17_combout & ((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~17_combout ), - .datab(\z80_|pla_decode_|Equal12~1_combout ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal25~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~8 .lut_mask = 16'h4455; -defparam \z80_|execute_|ctl_reg_sel_wz~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~18 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~18_combout = (!\z80_|execute_|ctl_reg_sel_wz~8_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # ((\z80_|execute_|ctl_state_alu~5_combout ) # (\z80_|execute_|ctl_alu_oe~2_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~8_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_state_alu~5_combout ), - .datad(\z80_|execute_|ctl_alu_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~18 .lut_mask = 16'h5554; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~19 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~19_combout = (!\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout & ((\z80_|execute_|fMRead~0_combout ) # ((!\z80_|execute_|ctl_mRead~9_combout & \z80_|execute_|pc_inc_hold~28_combout )))) - - .dataa(\z80_|execute_|fMRead~0_combout ), - .datab(\z80_|execute_|ctl_mRead~9_combout ), - .datac(\z80_|execute_|pc_inc_hold~28_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~19 .lut_mask = 16'h00BA; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~26 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~26_combout = (!\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout & (\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~26 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~5_combout = (\z80_|execute_|ctl_reg_sel_wz~8_combout & (!\z80_|pla_decode_|Equal34~0_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout & !\z80_|execute_|ctl_mRead~9_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~8_combout ), - .datab(\z80_|pla_decode_|Equal34~0_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), - .datad(\z80_|execute_|ctl_mRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~5 .lut_mask = 16'h0020; -defparam \z80_|execute_|ctl_al_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~27 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~27_combout = (!\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout & ((\z80_|execute_|ctl_al_we~5_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_al_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~27 .lut_mask = 16'h4404; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~28 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~28_combout = (\z80_|execute_|ctl_reg_sel_wz~7_combout & (\z80_|execute_|ctl_reg_sel_pc~13_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~7_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~13_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~28 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~18 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~18_combout = (\z80_|alu_control_|flags_cond_true~q & (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|pla_decode_|Equal35~0_combout ))) - - .dataa(\z80_|alu_control_|flags_cond_true~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|pla_decode_|Equal35~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~18 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sel_wz~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~37 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[0]~37_combout = (\z80_|execute_|ctl_reg_sel_wz~18_combout ) # ((\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|M5~q & \z80_|pla_decode_|Equal9~1_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~37 .lut_mask = 16'hFF80; -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~29 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[0]~29_combout = (\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ) # (((\z80_|execute_|ctl_reg_sys_hilo[0]~37_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~19_combout )) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~19_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~37_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~29 .lut_mask = 16'hFFBF; -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N12 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_62 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_62~combout = (!\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|execute_|ctl_reg_sel_ir~1_combout & \z80_|execute_|ctl_reg_sys_hilo[0]~29_combout )) - - .dataa(gnd), - .datab(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datac(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_62 .lut_mask = 16'h3000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_62 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~38 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~38_combout = ((\z80_|execute_|ctl_ir_we~11_combout ) # ((\z80_|execute_|ctl_mRead~6_combout ) # (\z80_|execute_|ctl_mRead~7_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_mRead~6_combout ), - .datad(\z80_|execute_|ctl_mRead~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~38 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_bus_inc_oe~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~39 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~39_combout = (\z80_|execute_|ctl_mRead~10_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~38_combout ) # ((\z80_|pla_decode_|Equal13~2_combout ) # (\z80_|execute_|ctl_state_alu~14_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~38_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|ctl_state_alu~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~39 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_bus_inc_oe~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~30 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~30_combout = (\z80_|execute_|pc_inc_hold~49_combout & (!\z80_|pla_decode_|Equal6~1_combout & ((!\z80_|pla_decode_|Equal33~2_combout ) # (!\z80_|decode_state_|use_ixiy~combout )))) - - .dataa(\z80_|execute_|pc_inc_hold~49_combout ), - .datab(\z80_|pla_decode_|Equal6~1_combout ), - .datac(\z80_|decode_state_|use_ixiy~combout ), - .datad(\z80_|pla_decode_|Equal33~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~30 .lut_mask = 16'h0222; -defparam \z80_|execute_|ctl_bus_inc_oe~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~45 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~45_combout = (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & ((!\z80_|execute_|nextM~2_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~30_combout )))) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~30_combout ), - .datab(\z80_|execute_|nextM~2_combout ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~45 .lut_mask = 16'h7000; -defparam \z80_|execute_|ctl_bus_inc_oe~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N12 -cycloneive_lcell_comb \z80_|execute_|fMRead~1 ( -// Equation(s): -// \z80_|execute_|fMRead~1_combout = ((!\z80_|pla_decode_|Equal33~0_combout ) # (!\z80_|ir_|opcode [7])) # (!\z80_|execute_|ctl_ir_we~5_combout ) - - .dataa(\z80_|execute_|ctl_ir_we~5_combout ), - .datab(gnd), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~1 .lut_mask = 16'h5FFF; -defparam \z80_|execute_|fMRead~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~36 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~36_combout = (\z80_|execute_|ixy_d~7_combout & (((\z80_|execute_|ctl_mRead~6_combout ) # (\z80_|execute_|ctl_mRead~5_combout )) # (!\z80_|execute_|fMRead~1_combout ))) - - .dataa(\z80_|execute_|fMRead~1_combout ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_mRead~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~36 .lut_mask = 16'hF0D0; -defparam \z80_|execute_|ctl_bus_inc_oe~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~27 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~27_combout = (\z80_|execute_|ctl_ir_we~4_combout & (!\z80_|execute_|ctl_mRead~9_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|execute_|ctl_mWrite~16_combout )))) # (!\z80_|execute_|ctl_ir_we~4_combout & -// (((!\z80_|execute_|ixy_d~5_combout )) # (!\z80_|execute_|ctl_mWrite~16_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ctl_mWrite~16_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|execute_|ctl_mRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~27 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_bus_inc_oe~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~28 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~28_combout = (\z80_|execute_|ctl_bus_inc_oe~47_combout & (\z80_|execute_|ctl_bus_inc_oe~26_combout & \z80_|execute_|ctl_bus_inc_oe~27_combout )) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~47_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_bus_inc_oe~26_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~27_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~28 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_bus_inc_oe~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~37 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~37_combout = (\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ) # ((\z80_|execute_|ctl_bus_inc_oe~36_combout ) # ((!\z80_|execute_|ctl_bus_inc_oe~28_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~46_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~36_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~46_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~28_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~37 .lut_mask = 16'hEFFF; -defparam \z80_|execute_|ctl_bus_inc_oe~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~40 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~40_combout = (\z80_|execute_|ctl_bus_inc_oe~45_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~37_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~39_combout & \z80_|execute_|ctl_ir_we~4_combout ))) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~39_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~45_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~37_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~40 .lut_mask = 16'hFFEC; -defparam \z80_|execute_|ctl_bus_inc_oe~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~35 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~35_combout = ((\z80_|execute_|ctl_alu_oe~2_combout & ((\z80_|execute_|ctl_mRead~6_combout ) # (\z80_|execute_|ctl_mRead~10_combout )))) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout ) - - .dataa(\z80_|execute_|ctl_mRead~6_combout ), - .datab(\z80_|execute_|ctl_alu_oe~2_combout ), - .datac(\z80_|execute_|ctl_mRead~10_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~35 .lut_mask = 16'hC8FF; -defparam \z80_|execute_|ctl_bus_inc_oe~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~77 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~77_combout = (\z80_|execute_|ctl_inc_cy~76_combout & (((!\z80_|execute_|ctl_alu_shift_oe~14_combout & !\z80_|execute_|ctl_sw_4u~0_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|execute_|ctl_sw_4u~0_combout ), - .datac(\z80_|execute_|ctl_inc_cy~76_combout ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~77_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~77 .lut_mask = 16'h10F0; -defparam \z80_|execute_|ctl_inc_cy~77 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~32 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~32_combout = (\z80_|execute_|ixy_d~9_combout & (!\z80_|pla_decode_|Equal11~0_combout & ((!\z80_|pla_decode_|Equal10~0_combout )))) # (!\z80_|execute_|ixy_d~9_combout & (((!\z80_|execute_|ctl_alu_shift_oe~14_combout )) # -// (!\z80_|pla_decode_|Equal11~0_combout ))) - - .dataa(\z80_|execute_|ixy_d~9_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datad(\z80_|pla_decode_|Equal10~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~32 .lut_mask = 16'h1537; -defparam \z80_|execute_|ctl_bus_inc_oe~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M4_ff~q & (\z80_|execute_|ctl_mWrite~2_combout & \z80_|pla_decode_|Equal55~0_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|execute_|ctl_mWrite~2_combout ), - .datad(\z80_|pla_decode_|Equal55~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~33 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~33_combout = (!\z80_|execute_|ctl_reg_sys_we~1_combout & (\z80_|execute_|ctl_bus_inc_oe~32_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout & \z80_|execute_|ctl_bus_inc_oe~24_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_we~1_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~32_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~33 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_bus_inc_oe~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~34 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~34_combout = (((!\z80_|execute_|ctl_bus_inc_oe~33_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[1]~5_combout )) # (!\z80_|execute_|ctl_inc_cy~77_combout )) # (!\z80_|execute_|ctl_inc_cy~53_combout ) - - .dataa(\z80_|execute_|ctl_inc_cy~53_combout ), - .datab(\z80_|execute_|ctl_inc_cy~77_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~34 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_bus_inc_oe~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~41 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~41_combout = (\z80_|execute_|ctl_bus_inc_oe~40_combout ) # (((\z80_|execute_|ctl_bus_inc_oe~35_combout ) # (\z80_|execute_|ctl_bus_inc_oe~34_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~31_combout )) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~40_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~31_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~35_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~34_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~41 .lut_mask = 16'hFFFB; -defparam \z80_|execute_|ctl_bus_inc_oe~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~10 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~10_combout = (\z80_|execute_|ctl_reg_sel_wz~8_combout & ((\z80_|execute_|ctl_reg_sel_wz~9_combout ) # ((!\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|execute_|ctl_reg_sel_wz~8_combout & -// (((!\z80_|execute_|ctl_alu_oe~2_combout & !\z80_|execute_|ctl_ir_we~4_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~9_combout ), - .datab(\z80_|execute_|ctl_alu_oe~2_combout ), - .datac(\z80_|execute_|ctl_reg_sel_wz~8_combout ), - .datad(\z80_|execute_|ctl_ir_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~10 .lut_mask = 16'hA0F3; -defparam \z80_|execute_|ctl_reg_sel_wz~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~11 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~11_combout = (\z80_|execute_|ctl_reg_sel_wz~7_combout & \z80_|execute_|ctl_reg_sel_wz~10_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_sel_wz~7_combout ), - .datac(\z80_|execute_|ctl_reg_sel_wz~10_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~11 .lut_mask = 16'hC0C0; -defparam \z80_|execute_|ctl_reg_sel_wz~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~3 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~3_combout = (\z80_|execute_|ctl_sw_1d~4_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~4_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout )) - - .dataa(\z80_|execute_|ctl_sw_1d~4_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~3 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_sw_4d~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~4 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~4_combout = (\z80_|execute_|ctl_flags_bus~5_combout & (((!\z80_|execute_|ctl_reg_in_hi~2_combout )) # (!\z80_|pla_decode_|Equal9~1_combout ))) # (!\z80_|execute_|ctl_flags_bus~5_combout & (!\z80_|execute_|ixy_d~6_combout & -// ((!\z80_|execute_|ctl_reg_in_hi~2_combout ) # (!\z80_|pla_decode_|Equal9~1_combout )))) - - .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), - .datab(\z80_|pla_decode_|Equal9~1_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~4 .lut_mask = 16'h2A3F; -defparam \z80_|execute_|ctl_sw_4d~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~2 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~2_combout = (\z80_|execute_|ctl_reg_in_lo~9_combout & (\z80_|execute_|fMRead~6_combout & \z80_|execute_|fMRead~8_combout )) - - .dataa(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datab(gnd), - .datac(\z80_|execute_|fMRead~6_combout ), - .datad(\z80_|execute_|fMRead~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~2 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_sw_4d~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~5 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~5_combout = (\z80_|execute_|ctl_reg_sel_wz~11_combout & (\z80_|execute_|ctl_sw_4d~3_combout & (\z80_|execute_|ctl_sw_4d~4_combout & \z80_|execute_|ctl_sw_4d~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~11_combout ), - .datab(\z80_|execute_|ctl_sw_4d~3_combout ), - .datac(\z80_|execute_|ctl_sw_4d~4_combout ), - .datad(\z80_|execute_|ctl_sw_4d~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~5 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_sw_4d~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|setM1~45 ( -// Equation(s): -// \z80_|execute_|setM1~45_combout = (!\z80_|execute_|ctl_iorw~11_combout & (\z80_|execute_|ctl_mRead~19_combout & (!\z80_|execute_|ctl_mRead~13_combout & !\z80_|execute_|ctl_iorw~10_combout ))) - - .dataa(\z80_|execute_|ctl_iorw~11_combout ), - .datab(\z80_|execute_|ctl_mRead~19_combout ), - .datac(\z80_|execute_|ctl_mRead~13_combout ), - .datad(\z80_|execute_|ctl_iorw~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~45 .lut_mask = 16'h0004; -defparam \z80_|execute_|setM1~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N12 -cycloneive_lcell_comb \z80_|execute_|setM1~46 ( -// Equation(s): -// \z80_|execute_|setM1~46_combout = (\z80_|execute_|ctl_al_we~13_combout & (\z80_|execute_|setM1~45_combout & !\z80_|execute_|ctl_mWrite~6_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_al_we~13_combout ), - .datac(\z80_|execute_|setM1~45_combout ), - .datad(\z80_|execute_|ctl_mWrite~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~46 .lut_mask = 16'h00C0; -defparam \z80_|execute_|setM1~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~1 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~1_combout = ((!\z80_|decode_state_|use_ixiy~combout & ((\z80_|pla_decode_|Equal50~0_combout ) # (\z80_|pla_decode_|Equal49~0_combout )))) # (!\z80_|execute_|setM1~46_combout ) - - .dataa(\z80_|pla_decode_|Equal50~0_combout ), - .datab(\z80_|decode_state_|use_ixiy~combout ), - .datac(\z80_|pla_decode_|Equal49~0_combout ), - .datad(\z80_|execute_|setM1~46_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~1 .lut_mask = 16'h32FF; -defparam \z80_|execute_|ctl_sw_4d~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~0 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~0_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ) # ((\z80_|execute_|ctl_reg_sel_wz~18_combout ) # ((\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ctl_al_we~14_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|execute_|ctl_al_we~14_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~0 .lut_mask = 16'hFFAE; -defparam \z80_|execute_|ctl_sw_4d~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~6 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~6_combout = ((\z80_|execute_|ctl_sw_4d~0_combout ) # ((\z80_|execute_|ctl_sw_4d~1_combout & \z80_|execute_|ctl_state_alu~5_combout ))) # (!\z80_|execute_|ctl_sw_4d~5_combout ) - - .dataa(\z80_|execute_|ctl_sw_4d~5_combout ), - .datab(\z80_|execute_|ctl_sw_4d~1_combout ), - .datac(\z80_|execute_|ctl_state_alu~5_combout ), - .datad(\z80_|execute_|ctl_sw_4d~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~6 .lut_mask = 16'hFFD5; -defparam \z80_|execute_|ctl_sw_4d~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N18 -cycloneive_lcell_comb \z80_|execute_|fMRead~4 ( -// Equation(s): -// \z80_|execute_|fMRead~4_combout = (\z80_|execute_|ctl_reg_sel_wz~8_combout & (!\z80_|pla_decode_|Equal34~0_combout & \z80_|execute_|ctl_al_we~4_combout )) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~8_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal34~0_combout ), - .datad(\z80_|execute_|ctl_al_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~4 .lut_mask = 16'h0A00; -defparam \z80_|execute_|fMRead~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~16 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~16_combout = (((\z80_|execute_|ctl_state_alu~5_combout & !\z80_|execute_|fMRead~4_combout )) # (!\z80_|execute_|ctl_reg_sel_pc~10_combout )) # (!\z80_|execute_|ctl_apin_mux~0_combout ) - - .dataa(\z80_|execute_|ctl_apin_mux~0_combout ), - .datab(\z80_|execute_|ctl_state_alu~5_combout ), - .datac(\z80_|execute_|fMRead~4_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~16 .lut_mask = 16'h5DFF; -defparam \z80_|execute_|ctl_reg_sel_pc~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~14 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~14_combout = (!\z80_|pla_decode_|Equal21~1_combout & (((\z80_|decode_state_|table_xx~0_combout ) # (!\z80_|pla_decode_|Equal33~0_combout )) # (!\z80_|pla_decode_|Equal41~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal41~0_combout ), - .datab(\z80_|decode_state_|table_xx~0_combout ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|pla_decode_|Equal21~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~14 .lut_mask = 16'h00DF; -defparam \z80_|execute_|ctl_reg_sel_pc~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~20 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~20_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|pla_decode_|Equal33~3_combout ) # (!\z80_|execute_|ctl_al_we~5_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|execute_|ctl_al_we~5_combout ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|pla_decode_|Equal33~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~20 .lut_mask = 16'h5010; -defparam \z80_|execute_|ctl_reg_sel_pc~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y18_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~15 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~15_combout = (\z80_|execute_|ctl_reg_sel_pc~20_combout ) # ((!\z80_|execute_|fMRead~0_combout & ((!\z80_|execute_|setM1~36_combout ) # (!\z80_|execute_|ctl_reg_sel_pc~14_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~14_combout ), - .datab(\z80_|execute_|setM1~36_combout ), - .datac(\z80_|execute_|ctl_reg_sel_pc~20_combout ), - .datad(\z80_|execute_|fMRead~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~15 .lut_mask = 16'hF0F7; -defparam \z80_|execute_|ctl_reg_sel_pc~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~17 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~17_combout = (!\z80_|nM1_int~2_combout & (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|execute_|ctl_mWrite~16_combout )) # (!\z80_|execute_|ctl_mWrite~7_combout ))) - - .dataa(\z80_|pla_decode_|Equal11~0_combout ), - .datab(\z80_|execute_|ctl_mWrite~7_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_mWrite~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~17 .lut_mask = 16'h0307; -defparam \z80_|execute_|ctl_reg_sel_pc~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~18 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~18_combout = (((!\z80_|execute_|ctl_bus_inc_oe~30_combout & \z80_|execute_|ixy_d~5_combout )) # (!\z80_|execute_|ctl_reg_sel_pc~17_combout )) # (!\z80_|execute_|ctl_sw_4u~1_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~30_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_sw_4u~1_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~18 .lut_mask = 16'h4FFF; -defparam \z80_|execute_|ctl_reg_sel_pc~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~19 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~19_combout = ((\z80_|execute_|ctl_reg_sel_pc~16_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~15_combout ) # (\z80_|execute_|ctl_reg_sel_pc~18_combout ))) # (!\z80_|execute_|ctl_reg_sel_pc~13_combout ) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~13_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~16_combout ), - .datac(\z80_|execute_|ctl_reg_sel_pc~15_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~19 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_reg_sel_pc~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N24 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~3 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_pc~3_combout = (\z80_|reg_control_|reg_sel_pc~2_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~4_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout & \z80_|execute_|ctl_reg_sel_wz~4_combout ))) - - .dataa(\z80_|reg_control_|reg_sel_pc~2_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~4_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_pc~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_pc~3 .lut_mask = 16'h0800; -defparam \z80_|reg_control_|reg_sel_pc~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N18 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc ( -// Equation(s): -// \z80_|reg_control_|reg_sel_pc~combout = (!\z80_|execute_|ctl_reg_sel_wz~18_combout & (\z80_|execute_|ctl_reg_sel_pc~19_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & \z80_|reg_control_|reg_sel_pc~3_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~18_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~19_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .datad(\z80_|reg_control_|reg_sel_pc~3_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_pc~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_pc .lut_mask = 16'h0400; -defparam \z80_|reg_control_|reg_sel_pc .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N8 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_74 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_74~combout = (\z80_|reg_control_|reg_sel_pc~combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout & !\z80_|reg_control_|reg_sys_we_lo~combout )) - - .dataa(gnd), - .datab(\z80_|reg_control_|reg_sel_pc~combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .datad(\z80_|reg_control_|reg_sys_we_lo~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_74 .lut_mask = 16'h00C0; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N22 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~2 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[0]~2_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ) # ((\z80_|execute_|ctl_bus_inc_oe~41_combout ) # ((\z80_|execute_|ctl_sw_4d~6_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|execute_|ctl_sw_4d~6_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[0]~2 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|db_lo_as[0]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N18 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_75 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_75~combout = (\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout & (\z80_|reg_control_|reg_sel_pc~combout & \z80_|reg_control_|reg_sys_we_lo~combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .datac(\z80_|reg_control_|reg_sel_pc~combout ), - .datad(\z80_|reg_control_|reg_sys_we_lo~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_75 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N3 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[7]~24_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N2 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~22 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[7]~22_combout = (\z80_|reg_file_|gdfx_temp0[7]~92_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) # (!\z80_|reg_file_|gdfx_temp0[7]~92_combout & -// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [7]), - .datad(\z80_|execute_|ctl_sw_4d~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[7]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[7]~22 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_lo_as[7]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N28 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_63 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_63~combout = (\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|execute_|ctl_reg_sel_ir~1_combout & \z80_|execute_|ctl_reg_sys_hilo[0]~29_combout )) - - .dataa(gnd), - .datab(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datac(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_63 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y17_N25 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[7]~24_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N14 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~23 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[7]~23_combout = (\z80_|reg_file_|db_lo_as[7]~22_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datac(\z80_|reg_file_|db_lo_as[7]~22_combout ), - .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[7]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[7]~23 .lut_mask = 16'hF030; -defparam \z80_|reg_file_|db_lo_as[7]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N26 -cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_10~0 ( -// Equation(s): -// \z80_|resets_|SYNTHESIZED_WIRE_10~0_combout = !\z80_|resets_|SYNTHESIZED_WIRE_12~q - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h0F0F; -defparam \z80_|resets_|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y17_N27 -dffeas \z80_|resets_|SYNTHESIZED_WIRE_10 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_10 .is_wysiwyg = "true"; -defparam \z80_|resets_|SYNTHESIZED_WIRE_10 .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y17_N9 -dffeas \z80_|resets_|SYNTHESIZED_WIRE_9 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_9 .is_wysiwyg = "true"; -defparam \z80_|resets_|SYNTHESIZED_WIRE_9 .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y17_N29 -dffeas \z80_|resets_|DFFE_intr_ff3 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|resets_|DFFE_intr_ff3~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|resets_|DFFE_intr_ff3 .is_wysiwyg = "true"; -defparam \z80_|resets_|DFFE_intr_ff3 .power_up = "low"; -// synopsys translate_on - -// Location: IOIBUF_X53_Y14_N1 -cycloneive_io_ibuf \KEY[0]~input ( - .i(KEY[0]), - .ibar(gnd), - .o(\KEY[0]~input_o )); -// synopsys translate_off -defparam \KEY[0]~input .bus_hold = "false"; -defparam \KEY[0]~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: LCCOMB_X52_Y14_N4 -cycloneive_lcell_comb reset( -// Equation(s): -// \reset~combout = (!\KEY[0]~input_o ) # (!\ula_|pll_|altpll_component|auto_generated|wire_pll1_locked ) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|pll_|altpll_component|auto_generated|wire_pll1_locked ), - .datad(\KEY[0]~input_o ), - .cin(gnd), - .combout(\reset~combout ), - .cout()); -// synopsys translate_off -defparam reset.lut_mask = 16'h0FFF; -defparam reset.sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N26 -cycloneive_lcell_comb \z80_|resets_|x1~0 ( -// Equation(s): -// \z80_|resets_|x1~0_combout = !\reset~combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\reset~combout ), - .cin(gnd), - .combout(\z80_|resets_|x1~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|resets_|x1~0 .lut_mask = 16'h00FF; -defparam \z80_|resets_|x1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y33_N0 -cycloneive_lcell_comb \z80_|fpga_reset~feeder ( -// Equation(s): -// \z80_|fpga_reset~feeder_combout = VCC - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(gnd), - .cin(gnd), - .combout(\z80_|fpga_reset~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|fpga_reset~feeder .lut_mask = 16'hFFFF; -defparam \z80_|fpga_reset~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y33_N1 -dffeas \z80_|fpga_reset ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|fpga_reset~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|fpga_reset~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|fpga_reset .is_wysiwyg = "true"; -defparam \z80_|fpga_reset .power_up = "low"; -// synopsys translate_on - -// Location: CLKCTRL_G12 -cycloneive_clkctrl \z80_|fpga_reset~clkctrl ( - .ena(vcc), - .inclk({vcc,vcc,vcc,\z80_|fpga_reset~q }), - .clkselect(2'b00), - .devclrn(devclrn), - .devpor(devpor), - .outclk(\z80_|fpga_reset~clkctrl_outclk )); -// synopsys translate_off -defparam \z80_|fpga_reset~clkctrl .clock_type = "global clock"; -defparam \z80_|fpga_reset~clkctrl .ena_register_mode = "none"; -// synopsys translate_on - -// Location: FF_X35_Y13_N27 -dffeas \z80_|resets_|x1 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|resets_|x1~0_combout ), - .asdata(vcc), - .clrn(\z80_|fpga_reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|resets_|x1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|resets_|x1 .is_wysiwyg = "true"; -defparam \z80_|resets_|x1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N18 -cycloneive_lcell_comb \z80_|resets_|clrpc_int~0 ( -// Equation(s): -// \z80_|resets_|clrpc_int~0_combout = (\z80_|sequencer_|DFFE_M1_ff~q & (((\z80_|resets_|clrpc_int~q )))) # (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|resets_|clrpc_int~q & !\z80_|resets_|x1~q )) # -// (!\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|resets_|clrpc_int~q )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|resets_|clrpc_int~q ), - .datad(\z80_|resets_|x1~q ), - .cin(gnd), - .combout(\z80_|resets_|clrpc_int~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|resets_|clrpc_int~0 .lut_mask = 16'hB0B4; -defparam \z80_|resets_|clrpc_int~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y17_N19 -dffeas \z80_|resets_|clrpc_int ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|resets_|clrpc_int~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|resets_|clrpc_int~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|resets_|clrpc_int .is_wysiwyg = "true"; -defparam \z80_|resets_|clrpc_int .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N28 -cycloneive_lcell_comb \z80_|resets_|clrpc~0 ( -// Equation(s): -// \z80_|resets_|clrpc~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_10~q ) # ((\z80_|resets_|SYNTHESIZED_WIRE_9~q ) # ((\z80_|resets_|DFFE_intr_ff3~q ) # (\z80_|resets_|clrpc_int~q ))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), - .datac(\z80_|resets_|DFFE_intr_ff3~q ), - .datad(\z80_|resets_|clrpc_int~q ), - .cin(gnd), - .combout(\z80_|resets_|clrpc~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|resets_|clrpc~0 .lut_mask = 16'hFFFE; -defparam \z80_|resets_|clrpc~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N4 -cycloneive_lcell_comb \z80_|address_latch_|abusz[7] ( -// Equation(s): -// \z80_|address_latch_|abusz [7] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[7]~24_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(\z80_|reg_file_|db_lo_as[7]~24_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [7]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[7] .lut_mask = 16'h0F00; -defparam \z80_|address_latch_|abusz[7] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~1 ( -// Equation(s): -// \z80_|execute_|ctl_apin_mux~1_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (\z80_|sequencer_|DFFE_M2_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_apin_mux~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_apin_mux~1 .lut_mask = 16'h5550; -defparam \z80_|execute_|ctl_apin_mux~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~6_combout = (\z80_|execute_|ctl_apin_mux~1_combout & (((\z80_|pla_decode_|Equal33~3_combout ) # (!\z80_|execute_|ctl_al_we~14_combout )) # (!\z80_|execute_|ctl_al_we~5_combout ))) - - .dataa(\z80_|execute_|ctl_apin_mux~1_combout ), - .datab(\z80_|execute_|ctl_al_we~5_combout ), - .datac(\z80_|execute_|ctl_al_we~14_combout ), - .datad(\z80_|pla_decode_|Equal33~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~6 .lut_mask = 16'hAA2A; -defparam \z80_|execute_|ctl_al_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~7_combout = (\z80_|execute_|ctl_state_alu~6_combout & (((!\z80_|execute_|ctl_flags_bus~5_combout ) # (!\z80_|execute_|ctl_al_we~13_combout )))) # (!\z80_|execute_|ctl_state_alu~6_combout & (\z80_|execute_|ctl_ir_we~4_combout & -// ((!\z80_|execute_|ctl_flags_bus~5_combout ) # (!\z80_|execute_|ctl_al_we~13_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~6_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_al_we~13_combout ), - .datad(\z80_|execute_|ctl_flags_bus~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~7 .lut_mask = 16'h0EEE; -defparam \z80_|execute_|ctl_al_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~8_combout = ((\z80_|execute_|ctl_al_we~7_combout ) # ((\z80_|execute_|ixy_d~6_combout & \z80_|pla_decode_|Equal35~0_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|execute_|ctl_al_we~7_combout ), - .datad(\z80_|pla_decode_|Equal35~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~8 .lut_mask = 16'hFBF3; -defparam \z80_|execute_|ctl_al_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~10_combout = (\z80_|decode_state_|in_halt~q ) # (((!\z80_|pla_decode_|Equal33~1_combout & !\z80_|pla_decode_|Equal33~0_combout )) # (!\z80_|pla_decode_|Equal77~0_combout )) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|decode_state_|in_halt~q ), - .datac(\z80_|pla_decode_|Equal77~0_combout ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~10 .lut_mask = 16'hCFDF; -defparam \z80_|execute_|ctl_alu_oe~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~9 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~9_combout = (((!\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~29_combout )) # (!\z80_|execute_|ctl_al_we~4_combout )) # (!\z80_|execute_|ctl_alu_oe~10_combout ) - - .dataa(\z80_|execute_|ctl_alu_oe~10_combout ), - .datab(\z80_|execute_|ctl_al_we~4_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~29_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~9 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_al_we~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~10 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~10_combout = (\z80_|execute_|ctl_al_we~8_combout ) # ((\z80_|execute_|ctl_state_alu~5_combout & ((\z80_|execute_|ctl_al_we~9_combout ) # (!\z80_|execute_|setM1~45_combout )))) - - .dataa(\z80_|execute_|ctl_al_we~8_combout ), - .datab(\z80_|execute_|ctl_state_alu~5_combout ), - .datac(\z80_|execute_|setM1~45_combout ), - .datad(\z80_|execute_|ctl_al_we~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~10 .lut_mask = 16'hEEAE; -defparam \z80_|execute_|ctl_al_we~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~11 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~11_combout = (\z80_|execute_|ctl_al_we~6_combout ) # ((\z80_|execute_|ctl_al_we~10_combout ) # (!\z80_|execute_|ctl_sw_4d~5_combout )) - - .dataa(\z80_|execute_|ctl_al_we~6_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_sw_4d~5_combout ), - .datad(\z80_|execute_|ctl_al_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~11 .lut_mask = 16'hFFAF; -defparam \z80_|execute_|ctl_al_we~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~12 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~12_combout = (\z80_|execute_|ctl_al_we~11_combout ) # (((\z80_|execute_|ixy_d~7_combout & \z80_|pla_decode_|Equal6~1_combout )) # (!\z80_|execute_|setM1~52_combout )) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_al_we~11_combout ), - .datac(\z80_|execute_|setM1~52_combout ), - .datad(\z80_|pla_decode_|Equal6~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~12 .lut_mask = 16'hEFCF; -defparam \z80_|execute_|ctl_al_we~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y16_N5 -dffeas \z80_|address_latch_|Q[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [7]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[7] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~6 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~6_combout = (\z80_|execute_|ctl_apin_mux~0_combout & (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout & ((!\z80_|execute_|ctl_ir_we~4_combout ) # (!\z80_|pla_decode_|Equal9~1_combout )))) - - .dataa(\z80_|execute_|ctl_apin_mux~0_combout ), - .datab(\z80_|pla_decode_|Equal9~1_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), - .datad(\z80_|execute_|ctl_ir_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~6 .lut_mask = 16'h020A; -defparam \z80_|execute_|ctl_inc_dec~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N24 -cycloneive_lcell_comb \z80_|execute_|fIOWrite~0 ( -// Equation(s): -// \z80_|execute_|fIOWrite~0_combout = ((!\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q ))) # (!\z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), .datac(\z80_|sequencer_|DFFE_T1_ff~q ), .datad(\z80_|sequencer_|DFFE_T2_ff~q ), .cin(gnd), - .combout(\z80_|execute_|fIOWrite~0_combout ), + .combout(\z80_|execute_|ixy_d~4_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fIOWrite~0 .lut_mask = 16'h3373; -defparam \z80_|execute_|fIOWrite~0 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ixy_d~4 .lut_mask = 16'h0030; +defparam \z80_|execute_|ixy_d~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y18_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~8 ( +// Location: LCCOMB_X21_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|ixy_d~11 ( // Equation(s): -// \z80_|execute_|ctl_inc_dec~8_combout = (\z80_|execute_|ctl_mWrite~4_combout & (((\z80_|execute_|ctl_mRead~11_combout ) # (!\z80_|execute_|fIOWrite~0_combout )) # (!\z80_|execute_|ctl_inc_dec~4_combout ))) +// \z80_|execute_|ixy_d~11_combout = (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # ((\z80_|sequencer_|DFFE_T5_ff~q ) # (!\z80_|execute_|ixy_d~4_combout )))) - .dataa(\z80_|execute_|ctl_inc_dec~4_combout ), - .datab(\z80_|execute_|fIOWrite~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|execute_|ctl_mRead~11_combout ), + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T5_ff~q ), + .datad(\z80_|execute_|ixy_d~4_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~8_combout ), + .combout(\z80_|execute_|ixy_d~11_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~8 .lut_mask = 16'hF070; -defparam \z80_|execute_|ctl_inc_dec~8 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ixy_d~11 .lut_mask = 16'hC8CC; +defparam \z80_|execute_|ixy_d~11 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y18_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~9 ( +// Location: LCCOMB_X21_Y14_N6 +cycloneive_lcell_comb \z80_|execute_|ixy_d~9 ( // Equation(s): -// \z80_|execute_|ctl_inc_dec~9_combout = ((\z80_|execute_|ctl_inc_dec~8_combout ) # ((!\z80_|execute_|ctl_reg_gp_we~0_combout & \z80_|ir_|opcode [3]))) # (!\z80_|execute_|ctl_inc_dec~3_combout ) +// \z80_|execute_|ixy_d~9_combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_M3_ff~q ) - .dataa(\z80_|execute_|ctl_reg_gp_we~0_combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|execute_|ctl_inc_dec~3_combout ), - .datad(\z80_|execute_|ctl_inc_dec~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~9 .lut_mask = 16'hFF4F; -defparam \z80_|execute_|ctl_inc_dec~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~10 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~10_combout = (\z80_|execute_|ctl_inc_dec~9_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_inc_dec~6_combout ), - .datac(\z80_|execute_|ctl_inc_dec~9_combout ), + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), .datad(gnd), .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~10_combout ), + .combout(\z80_|execute_|ixy_d~9_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~10 .lut_mask = 16'hF3F3; -defparam \z80_|execute_|ctl_inc_dec~10 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ixy_d~9 .lut_mask = 16'hA0A0; +defparam \z80_|execute_|ixy_d~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y17_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~7 ( +// Location: LCCOMB_X26_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|ixy_d~7 ( // Equation(s): -// \z80_|execute_|ctl_inc_dec~7_combout = (!\z80_|execute_|ctl_bus_inc_oe~33_combout ) # (!\z80_|execute_|ctl_inc_dec~5_combout ) +// \z80_|execute_|ixy_d~7_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M3_ff~q ) - .dataa(\z80_|execute_|ctl_inc_dec~5_combout ), + .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~7_combout ), + .combout(\z80_|execute_|ixy_d~7_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~7 .lut_mask = 16'h55FF; -defparam \z80_|execute_|ctl_inc_dec~7 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ixy_d~7 .lut_mask = 16'h0F00; +defparam \z80_|execute_|ixy_d~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y17_N17 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[2]~9_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [2]), - .prn(vcc)); +// Location: LCCOMB_X24_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|ixy_d~6 ( +// Equation(s): +// \z80_|execute_|ixy_d~6_combout = (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_M3_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~6_combout ), + .cout()); // synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[2] .power_up = "low"; +defparam \z80_|execute_|ixy_d~6 .lut_mask = 16'hA0A0; +defparam \z80_|execute_|ixy_d~6 .sum_lutc_input = "datac"; // synopsys translate_on // Location: LCCOMB_X26_Y13_N8 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_54 ( +cycloneive_lcell_comb \z80_|execute_|ixy_d~8 ( // Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_54~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl2~0_combout )) +// \z80_|execute_|ixy_d~8_combout = (\z80_|sequencer_|DFFE_T5_ff~q & \z80_|sequencer_|DFFE_M3_ff~q ) .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_54 .lut_mask = 16'h0C00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N22 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_58 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_58~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_58 .lut_mask = 16'h0C00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N26 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_55 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_55~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl2~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_55 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y9_N1 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N0 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_59 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_59~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_59 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_59 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y9_N3 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~34 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~34_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (\z80_|reg_file_|b2v_latch_hl2_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (((\z80_|reg_file_|b2v_latch_hl_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]), - .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [2]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~34 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[2]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N28 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_51 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_51~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_de~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_de~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_51 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y13_N11 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N12 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~4 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_de2~4_combout = (\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de2~q & ((\z80_|reg_control_|reg_sel_de2~5_combout ))) # (!\z80_|reg_control_|bank_hl_de2~q & (\z80_|reg_control_|reg_sel_de2~6_combout )))) - - .dataa(\z80_|reg_control_|reg_sel_de2~6_combout ), - .datab(\z80_|reg_control_|reg_sel_de2~5_combout ), - .datac(\z80_|reg_control_|bank_hl_de2~q ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_de2~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_de2~4 .lut_mask = 16'hCA00; -defparam \z80_|reg_control_|reg_sel_de2~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N2 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_46 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_46~combout = (!\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|reg_control_|reg_sel_de2~4_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datac(\z80_|reg_control_|reg_sel_de2~4_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_46 .lut_mask = 16'h3000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N14 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_47 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_47~combout = (\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|reg_control_|reg_sel_de2~4_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datac(\z80_|reg_control_|reg_sel_de2~4_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_47 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y13_N17 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~33 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~33_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [2] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [2] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [2]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~33 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[2]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N26 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 .lut_mask = 16'hF000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N14 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & !\z80_|reg_control_|bank_exx~q ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 .lut_mask = 16'h0010; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y11_N15 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N8 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & \z80_|reg_control_|bank_exx~q ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 .lut_mask = 16'h1000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y11_N25 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~36 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~36_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [2]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [2]), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~36 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[2]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N30 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_83 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_83~combout = (\z80_|execute_|ctl_reg_sel_wz~17_combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout & \z80_|reg_control_|reg_sys_we_lo~combout )) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~17_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), + .datab(\z80_|sequencer_|DFFE_T5_ff~q ), .datac(gnd), - .datad(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .combout(\z80_|execute_|ixy_d~8_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_83 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_83 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ixy_d~8 .lut_mask = 16'hCC00; +defparam \z80_|execute_|ixy_d~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y10_N13 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~37 ( +// Location: LCCOMB_X27_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|ixy_d~12 ( // Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~37_combout = (\z80_|reg_file_|gdfx_temp0[2]~36_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) +// \z80_|execute_|ixy_d~12_combout = (!\z80_|execute_|ixy_d~9_combout & (!\z80_|execute_|ixy_d~7_combout & (!\z80_|execute_|ixy_d~6_combout & !\z80_|execute_|ixy_d~8_combout ))) - .dataa(\z80_|reg_file_|gdfx_temp0[2]~36_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [2]), - .datad(gnd), + .dataa(\z80_|execute_|ixy_d~9_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ixy_d~8_combout ), .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~37_combout ), + .combout(\z80_|execute_|ixy_d~12_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~37 .lut_mask = 16'hA2A2; -defparam \z80_|reg_file_|gdfx_temp0[2]~37 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ixy_d~12 .lut_mask = 16'h0001; +defparam \z80_|execute_|ixy_d~12 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y12_N6 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 ( +// Location: LCCOMB_X29_Y13_N24 +cycloneive_lcell_comb \z80_|pla_decode_|Equal33~0 ( // Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout = (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) +// \z80_|pla_decode_|Equal33~0_combout = (\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [0] & \z80_|ir_|opcode [1])) - .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|ir_|opcode [0]), + .datac(gnd), + .datad(\z80_|ir_|opcode [1]), .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .combout(\z80_|pla_decode_|Equal33~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal33~0 .lut_mask = 16'h2200; +defparam \z80_|pla_decode_|Equal33~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y10_N25 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~39 ( +// Location: LCCOMB_X20_Y17_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal33~1 ( // Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~39_combout = (\z80_|alu_control_|db[2]~29_combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [2]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) # (!\z80_|alu_control_|db[2]~29_combout & -// (!\z80_|execute_|ctl_reg_in_lo~8_combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) +// \z80_|pla_decode_|Equal33~1_combout = (\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [3])) - .dataa(\z80_|alu_control_|db[2]~29_combout ), - .datab(\z80_|reg_file_|b2v_latch_sp_lo|latch [2]), - .datac(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|ir_|opcode [4]), + .datac(gnd), + .datad(\z80_|ir_|opcode [3]), .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~39_combout ), + .combout(\z80_|pla_decode_|Equal33~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~39 .lut_mask = 16'h8CAF; -defparam \z80_|reg_file_|gdfx_temp0[2]~39 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal33~1 .lut_mask = 16'h0088; +defparam \z80_|pla_decode_|Equal33~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y15_N22 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_iy~2 ( +// Location: LCCOMB_X24_Y15_N24 +cycloneive_lcell_comb \z80_|pla_decode_|Equal33~2 ( // Equation(s): -// \z80_|reg_control_|reg_sel_iy~2_combout = (\z80_|decode_state_|DFFE_instIY1~q & (!\z80_|decode_state_|DFFE_inst4~q & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) +// \z80_|pla_decode_|Equal33~2_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal33~1_combout )) - .dataa(\z80_|decode_state_|DFFE_instIY1~q ), - .datab(\z80_|decode_state_|DFFE_inst4~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal33~1_combout ), .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_iy~2_combout ), + .combout(\z80_|pla_decode_|Equal33~2_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_control_|reg_sel_iy~2 .lut_mask = 16'h0020; -defparam \z80_|reg_control_|reg_sel_iy~2 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal33~2 .lut_mask = 16'h8800; +defparam \z80_|pla_decode_|Equal33~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y10_N26 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_70 ( +// Location: LCCOMB_X28_Y19_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal21~0 ( // Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_70~combout = (!\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & \z80_|reg_control_|reg_sel_iy~2_combout )) +// \z80_|pla_decode_|Equal21~0_combout = (\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [3]) .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datad(\z80_|reg_control_|reg_sel_iy~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70 .lut_mask = 16'h3000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N16 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout = (\z80_|decode_state_|DFFE_inst4~q & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 .lut_mask = 16'h0080; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y10_N31 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N24 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_71 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_71~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (\z80_|reg_control_|reg_sel_iy~2_combout & \z80_|execute_|ctl_reg_gp_we~6_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datab(\z80_|reg_control_|reg_sel_iy~2_combout ), + .datab(\z80_|ir_|opcode [4]), .datac(gnd), - .datad(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datad(\z80_|ir_|opcode [3]), .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .combout(\z80_|pla_decode_|Equal21~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal21~0 .lut_mask = 16'h00CC; +defparam \z80_|pla_decode_|Equal21~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y10_N15 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~38 ( +// Location: LCCOMB_X25_Y16_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal77~0 ( // Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~38_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) +// \z80_|pla_decode_|Equal77~0_combout = (!\z80_|decode_state_|DFFE_instCB~q & (!\z80_|decode_state_|DFFE_instED~q & (!\z80_|ir_|opcode [7] & \z80_|ir_|opcode [6]))) - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [2]), - .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [2]), + .dataa(\z80_|decode_state_|DFFE_instCB~q ), + .datab(\z80_|decode_state_|DFFE_instED~q ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|ir_|opcode [6]), .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~38_combout ), + .combout(\z80_|pla_decode_|Equal77~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~38 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[2]~38 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal77~0 .lut_mask = 16'h0100; +defparam \z80_|pla_decode_|Equal77~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y10_N10 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_31 ( +// Location: LCCOMB_X28_Y16_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal77~1 ( // Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_31~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_af2~0_combout )) +// \z80_|pla_decode_|Equal77~1_combout = (\z80_|pla_decode_|Equal21~0_combout & (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal77~0_combout ))) - .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datac(gnd), - .datad(\z80_|reg_control_|reg_sel_af2~0_combout ), + .dataa(\z80_|pla_decode_|Equal21~0_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|pla_decode_|Equal77~0_combout ), .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .combout(\z80_|pla_decode_|Equal77~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_31 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_31 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal77~1 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal77~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y10_N23 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N28 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder ( +// Location: LCCOMB_X28_Y13_N26 +cycloneive_lcell_comb \z80_|pla_decode_|Equal1~7 ( // Equation(s): -// \z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp0[2]~42_combout +// \z80_|pla_decode_|Equal1~7_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [6] & (!\z80_|decode_state_|table_xx~0_combout & \z80_|ir_|opcode [7]))) - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [6]), + .datac(\z80_|decode_state_|table_xx~0_combout ), + .datad(\z80_|ir_|opcode [7]), .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder_combout ), + .combout(\z80_|pla_decode_|Equal1~7_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal1~7 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal1~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y14_N8 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_35 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_35~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_af~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_af~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_35 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N29 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~35 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~35_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [2]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [2]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~35 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[2]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~40 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~40_combout = (\z80_|reg_file_|gdfx_temp0[2]~37_combout & (\z80_|reg_file_|gdfx_temp0[2]~39_combout & (\z80_|reg_file_|gdfx_temp0[2]~38_combout & \z80_|reg_file_|gdfx_temp0[2]~35_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[2]~37_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[2]~39_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[2]~38_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[2]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~40 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[2]~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~41 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~41_combout = (\z80_|reg_file_|gdfx_temp0[2]~34_combout & (\z80_|reg_file_|gdfx_temp0[2]~33_combout & \z80_|reg_file_|gdfx_temp0[2]~40_combout )) - - .dataa(\z80_|reg_file_|gdfx_temp0[2]~34_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[2]~33_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[2]~40_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~41 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|gdfx_temp0[2]~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~42 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~42_combout = ((\z80_|reg_file_|gdfx_temp0[2]~41_combout & ((\z80_|reg_file_|db_lo_as[2]~9_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .datac(\z80_|execute_|ctl_sw_4u~6_combout ), - .datad(\z80_|reg_file_|db_lo_as[2]~9_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~42 .lut_mask = 16'hBB3B; -defparam \z80_|reg_file_|gdfx_temp0[2]~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N21 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[2]~9_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N20 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~7 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[2]~7_combout = (\z80_|reg_file_|gdfx_temp0[2]~42_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # (!\z80_|reg_file_|gdfx_temp0[2]~42_combout & -// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .datab(\z80_|execute_|ctl_sw_4d~6_combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[2]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[2]~7 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|db_lo_as[2]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N26 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~8 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[2]~8_combout = (\z80_|reg_file_|db_lo_as[2]~7_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_lo|latch [2]), - .datad(\z80_|reg_file_|db_lo_as[2]~7_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[2]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[2]~8 .lut_mask = 16'hF300; -defparam \z80_|reg_file_|db_lo_as[2]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y17_N9 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[0]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y13_N13 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y13_N19 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~10 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~10_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [0] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [0] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [0]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~10 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[0]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y13_N29 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N28 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]) # (!\z80_|reg_control_|reg_sel_hl2~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]), - .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y9_N9 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~11 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~11_combout = (\z80_|reg_file_|gdfx_temp0[0]~10_combout & (\z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0_combout & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[0]~10_combout ), - .datab(\z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_hl_lo|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~11 .lut_mask = 16'h8088; -defparam \z80_|reg_file_|gdfx_temp0[0]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y10_N21 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y10_N19 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~15 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~15_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_sp_lo|latch [0]), - .datac(\z80_|reg_file_|b2v_latch_iy_lo|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~15 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp0[0]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y11_N19 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N30 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder_combout = \z80_|reg_file_|gdfx_temp0[0]~22_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y11_N31 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y11_N1 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~14 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~14_combout = (\z80_|reg_file_|b2v_latch_bc_lo|latch [0] & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # (!\z80_|reg_file_|b2v_latch_bc_lo|latch [0] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc_lo|latch [0]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~14 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[0]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~16 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~16_combout = (\z80_|reg_file_|gdfx_temp0[0]~15_combout & (\z80_|reg_file_|gdfx_temp0[0]~14_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[0]~15_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [0]), - .datad(\z80_|reg_file_|gdfx_temp0[0]~14_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~16 .lut_mask = 16'hA200; -defparam \z80_|reg_file_|gdfx_temp0[0]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y11_N1 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~12 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~12_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [0] & ((\z80_|alu_control_|db[0]~12_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (((\z80_|alu_control_|db[0]~12_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [0]), - .datad(\z80_|alu_control_|db[0]~12_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~12 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[0]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N7 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y10_N13 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~13 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~13_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [0]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [0]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~13 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[0]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~17 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~17_combout = (\z80_|reg_file_|gdfx_temp0[0]~11_combout & (\z80_|reg_file_|gdfx_temp0[0]~16_combout & (\z80_|reg_file_|gdfx_temp0[0]~12_combout & \z80_|reg_file_|gdfx_temp0[0]~13_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[0]~11_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~16_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[0]~12_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[0]~13_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~17 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[0]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~22 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~22_combout = ((\z80_|reg_file_|gdfx_temp0[0]~17_combout & ((\z80_|reg_file_|db_lo_as[0]~3_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~17_combout ), - .datac(\z80_|reg_file_|db_lo_as[0]~3_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~22 .lut_mask = 16'hC4FF; -defparam \z80_|reg_file_|gdfx_temp0[0]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N25 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[0]~3_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N24 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~0 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[0]~0_combout = (\z80_|reg_file_|gdfx_temp0[0]~22_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) # (!\z80_|reg_file_|gdfx_temp0[0]~22_combout & -// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [0]), - .datad(\z80_|execute_|ctl_sw_4d~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[0]~0 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_lo_as[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N22 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~1 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[0]~1_combout = (\z80_|reg_file_|db_lo_as[0]~0_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|b2v_latch_ir_lo|latch [0]), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datad(\z80_|reg_file_|db_lo_as[0]~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[0]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[0]~1 .lut_mask = 16'hCF00; -defparam \z80_|reg_file_|db_lo_as[0]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~72 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~72_combout = (!\z80_|nM1_int~2_combout & (((!\z80_|execute_|ctl_alu_op_low~8_combout & !\z80_|execute_|ixy_d~5_combout )) # (!\z80_|pla_decode_|Equal41~2_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|pla_decode_|Equal41~2_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~72_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~72 .lut_mask = 16'h0515; -defparam \z80_|execute_|ctl_inc_cy~72 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: CLKCTRL_G18 -cycloneive_clkctrl \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl ( - .ena(vcc), - .inclk({vcc,vcc,vcc,\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk [0]}), - .clkselect(2'b00), - .devclrn(devclrn), - .devpor(devpor), - .outclk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk )); -// synopsys translate_off -defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .clock_type = "global clock"; -defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .ena_register_mode = "none"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N16 -cycloneive_lcell_comb \ula_|video_|Add0~14 ( -// Equation(s): -// \ula_|video_|Add0~14_combout = (\ula_|video_|vga_hc [7] & (!\ula_|video_|Add0~13 )) # (!\ula_|video_|vga_hc [7] & ((\ula_|video_|Add0~13 ) # (GND))) -// \ula_|video_|Add0~15 = CARRY((!\ula_|video_|Add0~13 ) # (!\ula_|video_|vga_hc [7])) - - .dataa(gnd), - .datab(\ula_|video_|vga_hc [7]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add0~13 ), - .combout(\ula_|video_|Add0~14_combout ), - .cout(\ula_|video_|Add0~15 )); -// synopsys translate_off -defparam \ula_|video_|Add0~14 .lut_mask = 16'h3C3F; -defparam \ula_|video_|Add0~14 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N18 -cycloneive_lcell_comb \ula_|video_|Add0~16 ( -// Equation(s): -// \ula_|video_|Add0~16_combout = (\ula_|video_|vga_hc [8] & (\ula_|video_|Add0~15 $ (GND))) # (!\ula_|video_|vga_hc [8] & (!\ula_|video_|Add0~15 & VCC)) -// \ula_|video_|Add0~17 = CARRY((\ula_|video_|vga_hc [8] & !\ula_|video_|Add0~15 )) - - .dataa(\ula_|video_|vga_hc [8]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add0~15 ), - .combout(\ula_|video_|Add0~16_combout ), - .cout(\ula_|video_|Add0~17 )); -// synopsys translate_off -defparam \ula_|video_|Add0~16 .lut_mask = 16'hA50A; -defparam \ula_|video_|Add0~16 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N26 -cycloneive_lcell_comb \ula_|video_|vga_hc~2 ( -// Equation(s): -// \ula_|video_|vga_hc~2_combout = (\ula_|video_|Equal1~0_combout & \ula_|video_|Add0~16_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|video_|Equal1~0_combout ), - .datad(\ula_|video_|Add0~16_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_hc~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_hc~2 .lut_mask = 16'hF000; -defparam \ula_|video_|vga_hc~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y33_N27 -dffeas \ula_|video_|vga_hc[8] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_hc~2_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_hc [8]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_hc[8] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_hc[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N20 -cycloneive_lcell_comb \ula_|video_|Add0~18 ( -// Equation(s): -// \ula_|video_|Add0~18_combout = \ula_|video_|Add0~17 $ (\ula_|video_|vga_hc [9]) - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|vga_hc [9]), - .cin(\ula_|video_|Add0~17 ), - .combout(\ula_|video_|Add0~18_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Add0~18 .lut_mask = 16'h0FF0; -defparam \ula_|video_|Add0~18 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y33_N20 -cycloneive_lcell_comb \ula_|video_|vga_hc~1 ( -// Equation(s): -// \ula_|video_|vga_hc~1_combout = (\ula_|video_|Equal1~0_combout & \ula_|video_|Add0~18_combout ) - - .dataa(gnd), - .datab(\ula_|video_|Equal1~0_combout ), - .datac(gnd), - .datad(\ula_|video_|Add0~18_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_hc~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_hc~1 .lut_mask = 16'hCC00; -defparam \ula_|video_|vga_hc~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y33_N21 -dffeas \ula_|video_|vga_hc[9] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_hc~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_hc [9]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_hc[9] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_hc[9] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N2 -cycloneive_lcell_comb \ula_|video_|Add0~0 ( -// Equation(s): -// \ula_|video_|Add0~0_combout = \ula_|video_|vga_hc [0] $ (VCC) -// \ula_|video_|Add0~1 = CARRY(\ula_|video_|vga_hc [0]) - - .dataa(gnd), - .datab(\ula_|video_|vga_hc [0]), - .datac(gnd), - .datad(vcc), - .cin(gnd), - .combout(\ula_|video_|Add0~0_combout ), - .cout(\ula_|video_|Add0~1 )); -// synopsys translate_off -defparam \ula_|video_|Add0~0 .lut_mask = 16'h33CC; -defparam \ula_|video_|Add0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N0 -cycloneive_lcell_comb \ula_|video_|vga_hc~3 ( -// Equation(s): -// \ula_|video_|vga_hc~3_combout = (\ula_|video_|Add0~0_combout & \ula_|video_|Equal1~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|video_|Add0~0_combout ), - .datad(\ula_|video_|Equal1~0_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_hc~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_hc~3 .lut_mask = 16'hF000; -defparam \ula_|video_|vga_hc~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y31_N1 -dffeas \ula_|video_|vga_hc[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_hc~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_hc [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_hc[0] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_hc[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N4 -cycloneive_lcell_comb \ula_|video_|Add0~2 ( -// Equation(s): -// \ula_|video_|Add0~2_combout = (\ula_|video_|vga_hc [1] & (!\ula_|video_|Add0~1 )) # (!\ula_|video_|vga_hc [1] & ((\ula_|video_|Add0~1 ) # (GND))) -// \ula_|video_|Add0~3 = CARRY((!\ula_|video_|Add0~1 ) # (!\ula_|video_|vga_hc [1])) - - .dataa(gnd), - .datab(\ula_|video_|vga_hc [1]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add0~1 ), - .combout(\ula_|video_|Add0~2_combout ), - .cout(\ula_|video_|Add0~3 )); -// synopsys translate_off -defparam \ula_|video_|Add0~2 .lut_mask = 16'h3C3F; -defparam \ula_|video_|Add0~2 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y33_N16 -cycloneive_lcell_comb \ula_|video_|vga_hc[1]~feeder ( -// Equation(s): -// \ula_|video_|vga_hc[1]~feeder_combout = \ula_|video_|Add0~2_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|Add0~2_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_hc[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_hc[1]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|vga_hc[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y33_N17 -dffeas \ula_|video_|vga_hc[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_hc[1]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_hc [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_hc[1] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_hc[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N6 -cycloneive_lcell_comb \ula_|video_|Add0~4 ( -// Equation(s): -// \ula_|video_|Add0~4_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|Add0~3 $ (GND))) # (!\ula_|video_|vga_hc [2] & (!\ula_|video_|Add0~3 & VCC)) -// \ula_|video_|Add0~5 = CARRY((\ula_|video_|vga_hc [2] & !\ula_|video_|Add0~3 )) - - .dataa(gnd), - .datab(\ula_|video_|vga_hc [2]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add0~3 ), - .combout(\ula_|video_|Add0~4_combout ), - .cout(\ula_|video_|Add0~5 )); -// synopsys translate_off -defparam \ula_|video_|Add0~4 .lut_mask = 16'hC30C; -defparam \ula_|video_|Add0~4 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y33_N23 -dffeas \ula_|video_|vga_hc[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|Add0~4_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_hc [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_hc[2] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_hc[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N8 -cycloneive_lcell_comb \ula_|video_|Add0~6 ( -// Equation(s): -// \ula_|video_|Add0~6_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|Add0~5 )) # (!\ula_|video_|vga_hc [3] & ((\ula_|video_|Add0~5 ) # (GND))) -// \ula_|video_|Add0~7 = CARRY((!\ula_|video_|Add0~5 ) # (!\ula_|video_|vga_hc [3])) - - .dataa(gnd), - .datab(\ula_|video_|vga_hc [3]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add0~5 ), - .combout(\ula_|video_|Add0~6_combout ), - .cout(\ula_|video_|Add0~7 )); -// synopsys translate_off -defparam \ula_|video_|Add0~6 .lut_mask = 16'h3C3F; -defparam \ula_|video_|Add0~6 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y33_N8 -cycloneive_lcell_comb \ula_|video_|vga_hc[3]~feeder ( -// Equation(s): -// \ula_|video_|vga_hc[3]~feeder_combout = \ula_|video_|Add0~6_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|Add0~6_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_hc[3]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_hc[3]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|vga_hc[3]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y33_N9 -dffeas \ula_|video_|vga_hc[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_hc[3]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_hc [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_hc[3] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_hc[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N10 -cycloneive_lcell_comb \ula_|video_|Add0~8 ( -// Equation(s): -// \ula_|video_|Add0~8_combout = (\ula_|video_|vga_hc [4] & (\ula_|video_|Add0~7 $ (GND))) # (!\ula_|video_|vga_hc [4] & (!\ula_|video_|Add0~7 & VCC)) -// \ula_|video_|Add0~9 = CARRY((\ula_|video_|vga_hc [4] & !\ula_|video_|Add0~7 )) - - .dataa(\ula_|video_|vga_hc [4]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add0~7 ), - .combout(\ula_|video_|Add0~8_combout ), - .cout(\ula_|video_|Add0~9 )); -// synopsys translate_off -defparam \ula_|video_|Add0~8 .lut_mask = 16'hA50A; -defparam \ula_|video_|Add0~8 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y33_N31 -dffeas \ula_|video_|vga_hc[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|Add0~8_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_hc [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_hc[4] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_hc[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N18 -cycloneive_lcell_comb \ula_|video_|Equal0~0 ( -// Equation(s): -// \ula_|video_|Equal0~0_combout = (!\ula_|video_|vga_hc [2] & (!\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [1] & !\ula_|video_|vga_hc [0]))) - - .dataa(\ula_|video_|vga_hc [2]), - .datab(\ula_|video_|vga_hc [3]), - .datac(\ula_|video_|vga_hc [1]), - .datad(\ula_|video_|vga_hc [0]), - .cin(gnd), - .combout(\ula_|video_|Equal0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Equal0~0 .lut_mask = 16'h0001; -defparam \ula_|video_|Equal0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N30 -cycloneive_lcell_comb \ula_|video_|Equal0~1 ( -// Equation(s): -// \ula_|video_|Equal0~1_combout = (\ula_|video_|vga_hc [5] & (!\ula_|video_|vga_hc [7] & (!\ula_|video_|vga_hc [4] & \ula_|video_|Equal0~0_combout ))) - - .dataa(\ula_|video_|vga_hc [5]), - .datab(\ula_|video_|vga_hc [7]), - .datac(\ula_|video_|vga_hc [4]), - .datad(\ula_|video_|Equal0~0_combout ), - .cin(gnd), - .combout(\ula_|video_|Equal0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Equal0~1 .lut_mask = 16'h0200; -defparam \ula_|video_|Equal0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y33_N16 -cycloneive_lcell_comb \ula_|video_|Equal1~0 ( -// Equation(s): -// \ula_|video_|Equal1~0_combout = (((\ula_|video_|vga_hc [6]) # (!\ula_|video_|Equal0~1_combout )) # (!\ula_|video_|vga_hc [8])) # (!\ula_|video_|vga_hc [9]) - - .dataa(\ula_|video_|vga_hc [9]), - .datab(\ula_|video_|vga_hc [8]), - .datac(\ula_|video_|vga_hc [6]), - .datad(\ula_|video_|Equal0~1_combout ), - .cin(gnd), - .combout(\ula_|video_|Equal1~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Equal1~0 .lut_mask = 16'hF7FF; -defparam \ula_|video_|Equal1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N12 -cycloneive_lcell_comb \ula_|video_|Add0~10 ( -// Equation(s): -// \ula_|video_|Add0~10_combout = (\ula_|video_|vga_hc [5] & (!\ula_|video_|Add0~9 )) # (!\ula_|video_|vga_hc [5] & ((\ula_|video_|Add0~9 ) # (GND))) -// \ula_|video_|Add0~11 = CARRY((!\ula_|video_|Add0~9 ) # (!\ula_|video_|vga_hc [5])) - - .dataa(\ula_|video_|vga_hc [5]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add0~9 ), - .combout(\ula_|video_|Add0~10_combout ), - .cout(\ula_|video_|Add0~11 )); -// synopsys translate_off -defparam \ula_|video_|Add0~10 .lut_mask = 16'h5A5F; -defparam \ula_|video_|Add0~10 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N0 -cycloneive_lcell_comb \ula_|video_|vga_hc~0 ( -// Equation(s): -// \ula_|video_|vga_hc~0_combout = (\ula_|video_|Equal1~0_combout & \ula_|video_|Add0~10_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|video_|Equal1~0_combout ), - .datad(\ula_|video_|Add0~10_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_hc~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_hc~0 .lut_mask = 16'hF000; -defparam \ula_|video_|vga_hc~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y33_N1 -dffeas \ula_|video_|vga_hc[5] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_hc~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_hc [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_hc[5] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_hc[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N14 -cycloneive_lcell_comb \ula_|video_|Add0~12 ( -// Equation(s): -// \ula_|video_|Add0~12_combout = (\ula_|video_|vga_hc [6] & (\ula_|video_|Add0~11 $ (GND))) # (!\ula_|video_|vga_hc [6] & (!\ula_|video_|Add0~11 & VCC)) -// \ula_|video_|Add0~13 = CARRY((\ula_|video_|vga_hc [6] & !\ula_|video_|Add0~11 )) - - .dataa(\ula_|video_|vga_hc [6]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add0~11 ), - .combout(\ula_|video_|Add0~12_combout ), - .cout(\ula_|video_|Add0~13 )); -// synopsys translate_off -defparam \ula_|video_|Add0~12 .lut_mask = 16'hA50A; -defparam \ula_|video_|Add0~12 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y33_N29 -dffeas \ula_|video_|vga_hc[6] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|Add0~12_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_hc [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_hc[6] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_hc[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X39_Y33_N25 -dffeas \ula_|video_|vga_hc[7] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|Add0~14_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_hc [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_hc[7] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_hc[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y33_N0 -cycloneive_lcell_comb \ula_|video_|Add1~0 ( -// Equation(s): -// \ula_|video_|Add1~0_combout = \ula_|video_|vga_vc [0] $ (VCC) -// \ula_|video_|Add1~1 = CARRY(\ula_|video_|vga_vc [0]) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [0]), - .datac(gnd), - .datad(vcc), - .cin(gnd), - .combout(\ula_|video_|Add1~0_combout ), - .cout(\ula_|video_|Add1~1 )); -// synopsys translate_off -defparam \ula_|video_|Add1~0 .lut_mask = 16'h33CC; -defparam \ula_|video_|Add1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y33_N2 -cycloneive_lcell_comb \ula_|video_|Add1~2 ( -// Equation(s): -// \ula_|video_|Add1~2_combout = (\ula_|video_|vga_vc [1] & (!\ula_|video_|Add1~1 )) # (!\ula_|video_|vga_vc [1] & ((\ula_|video_|Add1~1 ) # (GND))) -// \ula_|video_|Add1~3 = CARRY((!\ula_|video_|Add1~1 ) # (!\ula_|video_|vga_vc [1])) - - .dataa(\ula_|video_|vga_vc [1]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add1~1 ), - .combout(\ula_|video_|Add1~2_combout ), - .cout(\ula_|video_|Add1~3 )); -// synopsys translate_off -defparam \ula_|video_|Add1~2 .lut_mask = 16'h5A5F; -defparam \ula_|video_|Add1~2 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y33_N4 -cycloneive_lcell_comb \ula_|video_|Add1~4 ( -// Equation(s): -// \ula_|video_|Add1~4_combout = (\ula_|video_|vga_vc [2] & (\ula_|video_|Add1~3 $ (GND))) # (!\ula_|video_|vga_vc [2] & (!\ula_|video_|Add1~3 & VCC)) -// \ula_|video_|Add1~5 = CARRY((\ula_|video_|vga_vc [2] & !\ula_|video_|Add1~3 )) - - .dataa(\ula_|video_|vga_vc [2]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add1~3 ), - .combout(\ula_|video_|Add1~4_combout ), - .cout(\ula_|video_|Add1~5 )); -// synopsys translate_off -defparam \ula_|video_|Add1~4 .lut_mask = 16'hA50A; -defparam \ula_|video_|Add1~4 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N12 -cycloneive_lcell_comb \ula_|video_|vga_vc[2]~2 ( -// Equation(s): -// \ula_|video_|vga_vc[2]~2_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [2]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~4_combout )))) - - .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Add1~4_combout ), - .datac(\ula_|video_|vga_vc [2]), - .datad(\ula_|video_|Equal3~1_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[2]~2 .lut_mask = 16'h00E4; -defparam \ula_|video_|vga_vc[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y33_N13 -dffeas \ula_|video_|vga_vc[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[2]~2_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[2] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y33_N6 -cycloneive_lcell_comb \ula_|video_|Add1~6 ( -// Equation(s): -// \ula_|video_|Add1~6_combout = (\ula_|video_|vga_vc [3] & (!\ula_|video_|Add1~5 )) # (!\ula_|video_|vga_vc [3] & ((\ula_|video_|Add1~5 ) # (GND))) -// \ula_|video_|Add1~7 = CARRY((!\ula_|video_|Add1~5 ) # (!\ula_|video_|vga_vc [3])) - - .dataa(\ula_|video_|vga_vc [3]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add1~5 ), - .combout(\ula_|video_|Add1~6_combout ), - .cout(\ula_|video_|Add1~7 )); -// synopsys translate_off -defparam \ula_|video_|Add1~6 .lut_mask = 16'h5A5F; -defparam \ula_|video_|Add1~6 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y33_N20 -cycloneive_lcell_comb \ula_|video_|vga_vc[3]~3 ( -// Equation(s): -// \ula_|video_|vga_vc[3]~3_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [3])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~6_combout ))))) - - .dataa(\ula_|video_|Equal3~1_combout ), - .datab(\ula_|video_|Equal1~0_combout ), - .datac(\ula_|video_|vga_vc [3]), - .datad(\ula_|video_|Add1~6_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[3]~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[3]~3 .lut_mask = 16'h5140; -defparam \ula_|video_|vga_vc[3]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y33_N3 -dffeas \ula_|video_|vga_vc[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|vga_vc[3]~3_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[3] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y33_N8 -cycloneive_lcell_comb \ula_|video_|Add1~8 ( -// Equation(s): -// \ula_|video_|Add1~8_combout = (\ula_|video_|vga_vc [4] & (\ula_|video_|Add1~7 $ (GND))) # (!\ula_|video_|vga_vc [4] & (!\ula_|video_|Add1~7 & VCC)) -// \ula_|video_|Add1~9 = CARRY((\ula_|video_|vga_vc [4] & !\ula_|video_|Add1~7 )) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [4]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add1~7 ), - .combout(\ula_|video_|Add1~8_combout ), - .cout(\ula_|video_|Add1~9 )); -// synopsys translate_off -defparam \ula_|video_|Add1~8 .lut_mask = 16'hC30C; -defparam \ula_|video_|Add1~8 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N20 -cycloneive_lcell_comb \ula_|video_|vga_vc[4]~5 ( -// Equation(s): -// \ula_|video_|vga_vc[4]~5_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [4]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~8_combout )))) - - .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Add1~8_combout ), - .datac(\ula_|video_|vga_vc [4]), - .datad(\ula_|video_|Equal3~1_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[4]~5_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[4]~5 .lut_mask = 16'h00E4; -defparam \ula_|video_|vga_vc[4]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y33_N21 -dffeas \ula_|video_|vga_vc[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[4]~5_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[4] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y33_N10 -cycloneive_lcell_comb \ula_|video_|Add1~10 ( -// Equation(s): -// \ula_|video_|Add1~10_combout = (\ula_|video_|vga_vc [5] & (!\ula_|video_|Add1~9 )) # (!\ula_|video_|vga_vc [5] & ((\ula_|video_|Add1~9 ) # (GND))) -// \ula_|video_|Add1~11 = CARRY((!\ula_|video_|Add1~9 ) # (!\ula_|video_|vga_vc [5])) - - .dataa(\ula_|video_|vga_vc [5]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add1~9 ), - .combout(\ula_|video_|Add1~10_combout ), - .cout(\ula_|video_|Add1~11 )); -// synopsys translate_off -defparam \ula_|video_|Add1~10 .lut_mask = 16'h5A5F; -defparam \ula_|video_|Add1~10 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y33_N22 -cycloneive_lcell_comb \ula_|video_|vga_vc[5]~8 ( -// Equation(s): -// \ula_|video_|vga_vc[5]~8_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [5])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~10_combout ))))) - - .dataa(\ula_|video_|Equal3~1_combout ), - .datab(\ula_|video_|Equal1~0_combout ), - .datac(\ula_|video_|vga_vc [5]), - .datad(\ula_|video_|Add1~10_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[5]~8_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[5]~8 .lut_mask = 16'h5140; -defparam \ula_|video_|vga_vc[5]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y33_N17 -dffeas \ula_|video_|vga_vc[5] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|vga_vc[5]~8_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[5] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y33_N12 -cycloneive_lcell_comb \ula_|video_|Add1~12 ( -// Equation(s): -// \ula_|video_|Add1~12_combout = (\ula_|video_|vga_vc [6] & (\ula_|video_|Add1~11 $ (GND))) # (!\ula_|video_|vga_vc [6] & (!\ula_|video_|Add1~11 & VCC)) -// \ula_|video_|Add1~13 = CARRY((\ula_|video_|vga_vc [6] & !\ula_|video_|Add1~11 )) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [6]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add1~11 ), - .combout(\ula_|video_|Add1~12_combout ), - .cout(\ula_|video_|Add1~13 )); -// synopsys translate_off -defparam \ula_|video_|Add1~12 .lut_mask = 16'hC30C; -defparam \ula_|video_|Add1~12 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N6 -cycloneive_lcell_comb \ula_|video_|vga_vc[6]~4 ( -// Equation(s): -// \ula_|video_|vga_vc[6]~4_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [6]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~12_combout )))) - - .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Add1~12_combout ), - .datac(\ula_|video_|vga_vc [6]), - .datad(\ula_|video_|Equal3~1_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[6]~4_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[6]~4 .lut_mask = 16'h00E4; -defparam \ula_|video_|vga_vc[6]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y33_N7 -dffeas \ula_|video_|vga_vc[6] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[6]~4_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[6] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y33_N14 -cycloneive_lcell_comb \ula_|video_|Add1~14 ( -// Equation(s): -// \ula_|video_|Add1~14_combout = (\ula_|video_|vga_vc [7] & (!\ula_|video_|Add1~13 )) # (!\ula_|video_|vga_vc [7] & ((\ula_|video_|Add1~13 ) # (GND))) -// \ula_|video_|Add1~15 = CARRY((!\ula_|video_|Add1~13 ) # (!\ula_|video_|vga_vc [7])) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [7]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add1~13 ), - .combout(\ula_|video_|Add1~14_combout ), - .cout(\ula_|video_|Add1~15 )); -// synopsys translate_off -defparam \ula_|video_|Add1~14 .lut_mask = 16'h3C3F; -defparam \ula_|video_|Add1~14 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N14 -cycloneive_lcell_comb \ula_|video_|vga_vc[7]~6 ( -// Equation(s): -// \ula_|video_|vga_vc[7]~6_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [7]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~14_combout )))) - - .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Add1~14_combout ), - .datac(\ula_|video_|vga_vc [7]), - .datad(\ula_|video_|Equal3~1_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[7]~6_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[7]~6 .lut_mask = 16'h00E4; -defparam \ula_|video_|vga_vc[7]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y33_N15 -dffeas \ula_|video_|vga_vc[7] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[7]~6_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[7] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y33_N16 -cycloneive_lcell_comb \ula_|video_|Add1~16 ( -// Equation(s): -// \ula_|video_|Add1~16_combout = (\ula_|video_|vga_vc [8] & (\ula_|video_|Add1~15 $ (GND))) # (!\ula_|video_|vga_vc [8] & (!\ula_|video_|Add1~15 & VCC)) -// \ula_|video_|Add1~17 = CARRY((\ula_|video_|vga_vc [8] & !\ula_|video_|Add1~15 )) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [8]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add1~15 ), - .combout(\ula_|video_|Add1~16_combout ), - .cout(\ula_|video_|Add1~17 )); -// synopsys translate_off -defparam \ula_|video_|Add1~16 .lut_mask = 16'hC30C; -defparam \ula_|video_|Add1~16 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N24 -cycloneive_lcell_comb \ula_|video_|vga_vc[8]~7 ( -// Equation(s): -// \ula_|video_|vga_vc[8]~7_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [8]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~16_combout )))) - - .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Add1~16_combout ), - .datac(\ula_|video_|vga_vc [8]), - .datad(\ula_|video_|Equal3~1_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[8]~7_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[8]~7 .lut_mask = 16'h00E4; -defparam \ula_|video_|vga_vc[8]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y33_N25 -dffeas \ula_|video_|vga_vc[8] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[8]~7_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [8]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[8] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y33_N18 -cycloneive_lcell_comb \ula_|video_|Add1~18 ( -// Equation(s): -// \ula_|video_|Add1~18_combout = \ula_|video_|Add1~17 $ (\ula_|video_|vga_vc [9]) - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|vga_vc [9]), - .cin(\ula_|video_|Add1~17 ), - .combout(\ula_|video_|Add1~18_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Add1~18 .lut_mask = 16'h0FF0; -defparam \ula_|video_|Add1~18 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N10 -cycloneive_lcell_comb \ula_|video_|vga_vc[9]~9 ( -// Equation(s): -// \ula_|video_|vga_vc[9]~9_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [9]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~18_combout )))) - - .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Add1~18_combout ), - .datac(\ula_|video_|vga_vc [9]), - .datad(\ula_|video_|Equal3~1_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[9]~9_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[9]~9 .lut_mask = 16'h00E4; -defparam \ula_|video_|vga_vc[9]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y33_N11 -dffeas \ula_|video_|vga_vc[9] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[9]~9_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [9]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[9] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[9] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N18 -cycloneive_lcell_comb \ula_|video_|Equal2~0 ( -// Equation(s): -// \ula_|video_|Equal2~0_combout = (!\ula_|video_|vga_vc [6] & (!\ula_|video_|vga_vc [4] & (!\ula_|video_|vga_vc [7] & !\ula_|video_|vga_vc [8]))) - - .dataa(\ula_|video_|vga_vc [6]), - .datab(\ula_|video_|vga_vc [4]), - .datac(\ula_|video_|vga_vc [7]), - .datad(\ula_|video_|vga_vc [8]), - .cin(gnd), - .combout(\ula_|video_|Equal2~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Equal2~0 .lut_mask = 16'h0001; -defparam \ula_|video_|Equal2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y33_N30 -cycloneive_lcell_comb \ula_|video_|Equal3~0 ( -// Equation(s): -// \ula_|video_|Equal3~0_combout = (\ula_|video_|vga_vc [3] & (\ula_|video_|vga_vc [2] & (!\ula_|video_|vga_vc [1] & \ula_|video_|vga_vc [0]))) - - .dataa(\ula_|video_|vga_vc [3]), - .datab(\ula_|video_|vga_vc [2]), - .datac(\ula_|video_|vga_vc [1]), - .datad(\ula_|video_|vga_vc [0]), - .cin(gnd), - .combout(\ula_|video_|Equal3~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Equal3~0 .lut_mask = 16'h0800; -defparam \ula_|video_|Equal3~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y33_N18 -cycloneive_lcell_comb \ula_|video_|Equal3~1 ( -// Equation(s): -// \ula_|video_|Equal3~1_combout = (!\ula_|video_|vga_vc [5] & (\ula_|video_|vga_vc [9] & (\ula_|video_|Equal2~0_combout & \ula_|video_|Equal3~0_combout ))) - - .dataa(\ula_|video_|vga_vc [5]), - .datab(\ula_|video_|vga_vc [9]), - .datac(\ula_|video_|Equal2~0_combout ), - .datad(\ula_|video_|Equal3~0_combout ), - .cin(gnd), - .combout(\ula_|video_|Equal3~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Equal3~1 .lut_mask = 16'h4000; -defparam \ula_|video_|Equal3~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N28 -cycloneive_lcell_comb \ula_|video_|vga_vc[0]~0 ( -// Equation(s): -// \ula_|video_|vga_vc[0]~0_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [0]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~0_combout )))) - - .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Add1~0_combout ), - .datac(\ula_|video_|vga_vc [0]), - .datad(\ula_|video_|Equal3~1_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[0]~0 .lut_mask = 16'h00E4; -defparam \ula_|video_|vga_vc[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y33_N29 -dffeas \ula_|video_|vga_vc[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[0]~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[0] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N22 -cycloneive_lcell_comb \ula_|video_|vga_vc[1]~1 ( -// Equation(s): -// \ula_|video_|vga_vc[1]~1_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [1]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~2_combout )))) - - .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Add1~2_combout ), - .datac(\ula_|video_|vga_vc [1]), - .datad(\ula_|video_|Equal3~1_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[1]~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[1]~1 .lut_mask = 16'h00E4; -defparam \ula_|video_|vga_vc[1]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y33_N23 -dffeas \ula_|video_|vga_vc[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[1]~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[1] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[1] .power_up = "low"; -// synopsys translate_on - -// Location: IOIBUF_X27_Y0_N15 -cycloneive_io_ibuf \SW[1]~input ( - .i(SW[1]), - .ibar(gnd), - .o(\SW[1]~input_o )); -// synopsys translate_off -defparam \SW[1]~input .bus_hold = "false"; -defparam \SW[1]~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N30 -cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_13~0 ( -// Equation(s): -// \z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout = (!\ula_|video_|vga_hc [8] & (!\ula_|video_|vga_vc [1] & (!\SW[1]~input_o & !\ula_|video_|vga_hc [9]))) - - .dataa(\ula_|video_|vga_hc [8]), - .datab(\ula_|video_|vga_vc [1]), - .datac(\SW[1]~input_o ), - .datad(\ula_|video_|vga_hc [9]), - .cin(gnd), - .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13~0 .lut_mask = 16'h0001; -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N30 +// Location: LCCOMB_X29_Y17_N26 cycloneive_lcell_comb \z80_|pla_decode_|Equal79~0 ( // Equation(s): -// \z80_|pla_decode_|Equal79~0_combout = (\z80_|pla_decode_|Equal1~7_combout & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4]))) +// \z80_|pla_decode_|Equal79~0_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal1~7_combout & \z80_|ir_|opcode [4]))) - .dataa(\z80_|pla_decode_|Equal1~7_combout ), + .dataa(\z80_|ir_|opcode [5]), .datab(\z80_|pla_decode_|Equal2~0_combout ), - .datac(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal1~7_combout ), .datad(\z80_|ir_|opcode [4]), .cin(gnd), .combout(\z80_|pla_decode_|Equal79~0_combout ), @@ -18903,38 +4790,56 @@ defparam \z80_|pla_decode_|Equal79~0 .lut_mask = 16'h8000; defparam \z80_|pla_decode_|Equal79~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y17_N16 +// Location: LCCOMB_X29_Y17_N12 +cycloneive_lcell_comb \z80_|interrupts_|iff1~0 ( +// Equation(s): +// \z80_|interrupts_|iff1~0_combout = (\z80_|pla_decode_|Equal79~0_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|ir_|opcode [3]))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|interrupts_|iff1~q )))) # +// (!\z80_|pla_decode_|Equal79~0_combout & (((\z80_|interrupts_|iff1~q )))) + + .dataa(\z80_|pla_decode_|Equal79~0_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|interrupts_|iff1~q ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|interrupts_|iff1~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|iff1~0 .lut_mask = 16'hF870; +defparam \z80_|interrupts_|iff1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N30 cycloneive_lcell_comb \z80_|interrupts_|DFFE_instIFF2~0 ( // Equation(s): -// \z80_|interrupts_|DFFE_instIFF2~0_combout = (\z80_|pla_decode_|Equal79~0_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|ir_|opcode [3])) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|interrupts_|DFFE_instIFF2~q -// ))))) # (!\z80_|pla_decode_|Equal79~0_combout & (((\z80_|interrupts_|DFFE_instIFF2~q )))) +// \z80_|interrupts_|DFFE_instIFF2~0_combout = (\z80_|pla_decode_|Equal79~0_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|ir_|opcode [3]))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|interrupts_|DFFE_instIFF2~q +// )))) # (!\z80_|pla_decode_|Equal79~0_combout & (((\z80_|interrupts_|DFFE_instIFF2~q )))) - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal79~0_combout ), + .dataa(\z80_|pla_decode_|Equal79~0_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), .datac(\z80_|interrupts_|DFFE_instIFF2~q ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|ir_|opcode [3]), .cin(gnd), .combout(\z80_|interrupts_|DFFE_instIFF2~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|interrupts_|DFFE_instIFF2~0 .lut_mask = 16'hB8F0; +defparam \z80_|interrupts_|DFFE_instIFF2~0 .lut_mask = 16'hF870; defparam \z80_|interrupts_|DFFE_instIFF2~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y15_N28 +// Location: LCCOMB_X27_Y11_N24 cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_12 ( // Equation(s): -// \z80_|interrupts_|SYNTHESIZED_WIRE_12~combout = ((!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & \z80_|interrupts_|DFFE_inst44~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) +// \z80_|interrupts_|SYNTHESIZED_WIRE_12~combout = ((\z80_|interrupts_|DFFE_inst44~q & !\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|interrupts_|DFFE_inst44~q ), .datac(gnd), - .datad(\z80_|interrupts_|DFFE_inst44~q ), + .datad(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), .cin(gnd), .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_12~combout ), .cout()); // synopsys translate_off -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12 .lut_mask = 16'h7733; +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12 .lut_mask = 16'h55DD; defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12 .sum_lutc_input = "datac"; // synopsys translate_on @@ -18951,7 +4856,7 @@ defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl .clock_type = "global clo defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: FF_X35_Y17_N17 +// Location: FF_X29_Y17_N31 dffeas \z80_|interrupts_|DFFE_instIFF2 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|interrupts_|DFFE_instIFF2~0_combout ), @@ -18970,60 +4875,76 @@ defparam \z80_|interrupts_|DFFE_instIFF2 .is_wysiwyg = "true"; defparam \z80_|interrupts_|DFFE_instIFF2 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X35_Y17_N2 -cycloneive_lcell_comb \z80_|interrupts_|iff1~0 ( +// Location: LCCOMB_X29_Y13_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal13~0 ( // Equation(s): -// \z80_|interrupts_|iff1~0_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|pla_decode_|Equal79~0_combout & ((\z80_|ir_|opcode [3]))) # (!\z80_|pla_decode_|Equal79~0_combout & (\z80_|interrupts_|iff1~q )))) # -// (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|interrupts_|iff1~q )) +// \z80_|pla_decode_|Equal13~0_combout = (\z80_|decode_state_|DFFE_instED~q & (!\z80_|ir_|opcode [7] & \z80_|ir_|opcode [6])) - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|interrupts_|iff1~q ), - .datac(\z80_|pla_decode_|Equal79~0_combout ), - .datad(\z80_|ir_|opcode [3]), + .dataa(\z80_|decode_state_|DFFE_instED~q ), + .datab(gnd), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|ir_|opcode [6]), .cin(gnd), - .combout(\z80_|interrupts_|iff1~0_combout ), + .combout(\z80_|pla_decode_|Equal13~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|interrupts_|iff1~0 .lut_mask = 16'hEC4C; -defparam \z80_|interrupts_|iff1~0 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal13~0 .lut_mask = 16'h0A00; +defparam \z80_|pla_decode_|Equal13~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y17_N18 +// Location: LCCOMB_X21_Y16_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal38~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal38~2_combout = (\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [1] & \z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal38~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal38~2 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal38~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N0 cycloneive_lcell_comb \z80_|interrupts_|iff1~1 ( // Equation(s): -// \z80_|interrupts_|iff1~1_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|pla_decode_|Equal38~2_combout & (\z80_|interrupts_|DFFE_instIFF2~q )) # (!\z80_|pla_decode_|Equal38~2_combout & ((\z80_|interrupts_|iff1~0_combout ))))) # -// (!\z80_|execute_|ctl_eval_cond~0_combout & (((\z80_|interrupts_|iff1~0_combout )))) +// \z80_|interrupts_|iff1~1_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|pla_decode_|Equal38~2_combout & ((\z80_|interrupts_|DFFE_instIFF2~q ))) # (!\z80_|pla_decode_|Equal38~2_combout & (\z80_|interrupts_|iff1~0_combout )))) # +// (!\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|interrupts_|iff1~0_combout )) - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|interrupts_|DFFE_instIFF2~q ), - .datac(\z80_|pla_decode_|Equal38~2_combout ), - .datad(\z80_|interrupts_|iff1~0_combout ), + .dataa(\z80_|interrupts_|iff1~0_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|interrupts_|DFFE_instIFF2~q ), + .datad(\z80_|pla_decode_|Equal38~2_combout ), .cin(gnd), .combout(\z80_|interrupts_|iff1~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|interrupts_|iff1~1 .lut_mask = 16'hDF80; +defparam \z80_|interrupts_|iff1~1 .lut_mask = 16'hE2AA; defparam \z80_|interrupts_|iff1~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y18_N12 +// Location: LCCOMB_X28_Y13_N20 cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_15 ( // Equation(s): -// \z80_|interrupts_|SYNTHESIZED_WIRE_15~combout = ((\z80_|interrupts_|DFFE_inst44~q ) # (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) +// \z80_|interrupts_|SYNTHESIZED_WIRE_15~combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # ((\z80_|interrupts_|DFFE_inst44~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(gnd), .datac(\z80_|interrupts_|DFFE_inst44~q ), - .datad(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .cin(gnd), .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_15~combout ), .cout()); // synopsys translate_off -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_15 .lut_mask = 16'hFFF3; +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_15 .lut_mask = 16'hFAFF; defparam \z80_|interrupts_|SYNTHESIZED_WIRE_15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X35_Y17_N19 +// Location: FF_X29_Y17_N1 dffeas \z80_|interrupts_|iff1 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|interrupts_|iff1~1_combout ), @@ -19042,14 +4963,1122 @@ defparam \z80_|interrupts_|iff1 .is_wysiwyg = "true"; defparam \z80_|interrupts_|iff1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X37_Y33_N4 -cycloneive_lcell_comb \ula_|video_|Equal2~1 ( +// Location: CLKCTRL_G18 +cycloneive_clkctrl \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk [0]}), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk )); +// synopsys translate_off +defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .clock_type = "global clock"; +defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y32_N6 +cycloneive_lcell_comb \ula_|video_|Add0~0 ( // Equation(s): -// \ula_|video_|Equal2~1_combout = (!\ula_|video_|vga_vc [3] & (!\ula_|video_|vga_vc [2] & (!\ula_|video_|vga_vc [9] & !\ula_|video_|vga_vc [0]))) +// \ula_|video_|Add0~0_combout = \ula_|video_|vga_hc [0] $ (VCC) +// \ula_|video_|Add0~1 = CARRY(\ula_|video_|vga_hc [0]) + + .dataa(gnd), + .datab(\ula_|video_|vga_hc [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\ula_|video_|Add0~0_combout ), + .cout(\ula_|video_|Add0~1 )); +// synopsys translate_off +defparam \ula_|video_|Add0~0 .lut_mask = 16'h33CC; +defparam \ula_|video_|Add0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y32_N28 +cycloneive_lcell_comb \ula_|video_|vga_hc~3 ( +// Equation(s): +// \ula_|video_|vga_hc~3_combout = (\ula_|video_|Add0~0_combout & \ula_|video_|Equal1~0_combout ) + + .dataa(gnd), + .datab(\ula_|video_|Add0~0_combout ), + .datac(gnd), + .datad(\ula_|video_|Equal1~0_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_hc~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_hc~3 .lut_mask = 16'hCC00; +defparam \ula_|video_|vga_hc~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y32_N13 +dffeas \ula_|video_|vga_hc[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|vga_hc~3_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_hc [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_hc[0] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_hc[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y32_N8 +cycloneive_lcell_comb \ula_|video_|Add0~2 ( +// Equation(s): +// \ula_|video_|Add0~2_combout = (\ula_|video_|vga_hc [1] & (!\ula_|video_|Add0~1 )) # (!\ula_|video_|vga_hc [1] & ((\ula_|video_|Add0~1 ) # (GND))) +// \ula_|video_|Add0~3 = CARRY((!\ula_|video_|Add0~1 ) # (!\ula_|video_|vga_hc [1])) + + .dataa(gnd), + .datab(\ula_|video_|vga_hc [1]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add0~1 ), + .combout(\ula_|video_|Add0~2_combout ), + .cout(\ula_|video_|Add0~3 )); +// synopsys translate_off +defparam \ula_|video_|Add0~2 .lut_mask = 16'h3C3F; +defparam \ula_|video_|Add0~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X35_Y32_N25 +dffeas \ula_|video_|vga_hc[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|Add0~2_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_hc [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_hc[1] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_hc[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y32_N10 +cycloneive_lcell_comb \ula_|video_|Add0~4 ( +// Equation(s): +// \ula_|video_|Add0~4_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|Add0~3 $ (GND))) # (!\ula_|video_|vga_hc [2] & (!\ula_|video_|Add0~3 & VCC)) +// \ula_|video_|Add0~5 = CARRY((\ula_|video_|vga_hc [2] & !\ula_|video_|Add0~3 )) + + .dataa(gnd), + .datab(\ula_|video_|vga_hc [2]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add0~3 ), + .combout(\ula_|video_|Add0~4_combout ), + .cout(\ula_|video_|Add0~5 )); +// synopsys translate_off +defparam \ula_|video_|Add0~4 .lut_mask = 16'hC30C; +defparam \ula_|video_|Add0~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X35_Y32_N3 +dffeas \ula_|video_|vga_hc[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|Add0~4_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_hc [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_hc[2] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_hc[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y32_N12 +cycloneive_lcell_comb \ula_|video_|Add0~6 ( +// Equation(s): +// \ula_|video_|Add0~6_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|Add0~5 )) # (!\ula_|video_|vga_hc [3] & ((\ula_|video_|Add0~5 ) # (GND))) +// \ula_|video_|Add0~7 = CARRY((!\ula_|video_|Add0~5 ) # (!\ula_|video_|vga_hc [3])) + + .dataa(\ula_|video_|vga_hc [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add0~5 ), + .combout(\ula_|video_|Add0~6_combout ), + .cout(\ula_|video_|Add0~7 )); +// synopsys translate_off +defparam \ula_|video_|Add0~6 .lut_mask = 16'h5A5F; +defparam \ula_|video_|Add0~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X34_Y32_N21 +dffeas \ula_|video_|vga_hc[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|Add0~6_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_hc [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_hc[3] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_hc[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y32_N14 +cycloneive_lcell_comb \ula_|video_|Add0~8 ( +// Equation(s): +// \ula_|video_|Add0~8_combout = (\ula_|video_|vga_hc [4] & (\ula_|video_|Add0~7 $ (GND))) # (!\ula_|video_|vga_hc [4] & (!\ula_|video_|Add0~7 & VCC)) +// \ula_|video_|Add0~9 = CARRY((\ula_|video_|vga_hc [4] & !\ula_|video_|Add0~7 )) + + .dataa(\ula_|video_|vga_hc [4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add0~7 ), + .combout(\ula_|video_|Add0~8_combout ), + .cout(\ula_|video_|Add0~9 )); +// synopsys translate_off +defparam \ula_|video_|Add0~8 .lut_mask = 16'hA50A; +defparam \ula_|video_|Add0~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X34_Y32_N3 +dffeas \ula_|video_|vga_hc[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|Add0~8_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_hc [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_hc[4] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_hc[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y32_N16 +cycloneive_lcell_comb \ula_|video_|Add0~10 ( +// Equation(s): +// \ula_|video_|Add0~10_combout = (\ula_|video_|vga_hc [5] & (!\ula_|video_|Add0~9 )) # (!\ula_|video_|vga_hc [5] & ((\ula_|video_|Add0~9 ) # (GND))) +// \ula_|video_|Add0~11 = CARRY((!\ula_|video_|Add0~9 ) # (!\ula_|video_|vga_hc [5])) + + .dataa(gnd), + .datab(\ula_|video_|vga_hc [5]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add0~9 ), + .combout(\ula_|video_|Add0~10_combout ), + .cout(\ula_|video_|Add0~11 )); +// synopsys translate_off +defparam \ula_|video_|Add0~10 .lut_mask = 16'h3C3F; +defparam \ula_|video_|Add0~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y32_N26 +cycloneive_lcell_comb \ula_|video_|vga_hc~0 ( +// Equation(s): +// \ula_|video_|vga_hc~0_combout = (\ula_|video_|Add0~10_combout & \ula_|video_|Equal1~0_combout ) + + .dataa(gnd), + .datab(\ula_|video_|Add0~10_combout ), + .datac(gnd), + .datad(\ula_|video_|Equal1~0_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_hc~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_hc~0 .lut_mask = 16'hCC00; +defparam \ula_|video_|vga_hc~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y32_N29 +dffeas \ula_|video_|vga_hc[5] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|vga_hc~0_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_hc [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_hc[5] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_hc[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y32_N18 +cycloneive_lcell_comb \ula_|video_|Add0~12 ( +// Equation(s): +// \ula_|video_|Add0~12_combout = (\ula_|video_|vga_hc [6] & (\ula_|video_|Add0~11 $ (GND))) # (!\ula_|video_|vga_hc [6] & (!\ula_|video_|Add0~11 & VCC)) +// \ula_|video_|Add0~13 = CARRY((\ula_|video_|vga_hc [6] & !\ula_|video_|Add0~11 )) + + .dataa(\ula_|video_|vga_hc [6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add0~11 ), + .combout(\ula_|video_|Add0~12_combout ), + .cout(\ula_|video_|Add0~13 )); +// synopsys translate_off +defparam \ula_|video_|Add0~12 .lut_mask = 16'hA50A; +defparam \ula_|video_|Add0~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X34_Y32_N5 +dffeas \ula_|video_|vga_hc[6] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|Add0~12_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_hc [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_hc[6] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_hc[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y32_N20 +cycloneive_lcell_comb \ula_|video_|Add0~14 ( +// Equation(s): +// \ula_|video_|Add0~14_combout = (\ula_|video_|vga_hc [7] & (!\ula_|video_|Add0~13 )) # (!\ula_|video_|vga_hc [7] & ((\ula_|video_|Add0~13 ) # (GND))) +// \ula_|video_|Add0~15 = CARRY((!\ula_|video_|Add0~13 ) # (!\ula_|video_|vga_hc [7])) + + .dataa(gnd), + .datab(\ula_|video_|vga_hc [7]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add0~13 ), + .combout(\ula_|video_|Add0~14_combout ), + .cout(\ula_|video_|Add0~15 )); +// synopsys translate_off +defparam \ula_|video_|Add0~14 .lut_mask = 16'h3C3F; +defparam \ula_|video_|Add0~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X34_Y32_N27 +dffeas \ula_|video_|vga_hc[7] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|Add0~14_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_hc [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_hc[7] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_hc[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y32_N22 +cycloneive_lcell_comb \ula_|video_|Add0~16 ( +// Equation(s): +// \ula_|video_|Add0~16_combout = (\ula_|video_|vga_hc [8] & (\ula_|video_|Add0~15 $ (GND))) # (!\ula_|video_|vga_hc [8] & (!\ula_|video_|Add0~15 & VCC)) +// \ula_|video_|Add0~17 = CARRY((\ula_|video_|vga_hc [8] & !\ula_|video_|Add0~15 )) + + .dataa(gnd), + .datab(\ula_|video_|vga_hc [8]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add0~15 ), + .combout(\ula_|video_|Add0~16_combout ), + .cout(\ula_|video_|Add0~17 )); +// synopsys translate_off +defparam \ula_|video_|Add0~16 .lut_mask = 16'hC30C; +defparam \ula_|video_|Add0~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y32_N2 +cycloneive_lcell_comb \ula_|video_|vga_hc~2 ( +// Equation(s): +// \ula_|video_|vga_hc~2_combout = (\ula_|video_|Add0~16_combout & \ula_|video_|Equal1~0_combout ) + + .dataa(gnd), + .datab(\ula_|video_|Add0~16_combout ), + .datac(gnd), + .datad(\ula_|video_|Equal1~0_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_hc~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_hc~2 .lut_mask = 16'hCC00; +defparam \ula_|video_|vga_hc~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y32_N27 +dffeas \ula_|video_|vga_hc[8] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|vga_hc~2_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_hc [8]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_hc[8] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_hc[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y32_N24 +cycloneive_lcell_comb \ula_|video_|Add0~18 ( +// Equation(s): +// \ula_|video_|Add0~18_combout = \ula_|video_|Add0~17 $ (\ula_|video_|vga_hc [9]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|vga_hc [9]), + .cin(\ula_|video_|Add0~17 ), + .combout(\ula_|video_|Add0~18_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Add0~18 .lut_mask = 16'h0FF0; +defparam \ula_|video_|Add0~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y32_N4 +cycloneive_lcell_comb \ula_|video_|vga_hc~1 ( +// Equation(s): +// \ula_|video_|vga_hc~1_combout = (\ula_|video_|Add0~18_combout & \ula_|video_|Equal1~0_combout ) + + .dataa(\ula_|video_|Add0~18_combout ), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|Equal1~0_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_hc~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_hc~1 .lut_mask = 16'hAA00; +defparam \ula_|video_|vga_hc~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y32_N1 +dffeas \ula_|video_|vga_hc[9] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|vga_hc~1_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_hc [9]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_hc[9] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_hc[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y31_N14 +cycloneive_lcell_comb \ula_|video_|Equal0~0 ( +// Equation(s): +// \ula_|video_|Equal0~0_combout = (!\ula_|video_|vga_hc [1] & (!\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [2] & !\ula_|video_|vga_hc [0]))) + + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|vga_hc [3]), + .datac(\ula_|video_|vga_hc [2]), + .datad(\ula_|video_|vga_hc [0]), + .cin(gnd), + .combout(\ula_|video_|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Equal0~0 .lut_mask = 16'h0001; +defparam \ula_|video_|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y31_N24 +cycloneive_lcell_comb \ula_|video_|Equal0~1 ( +// Equation(s): +// \ula_|video_|Equal0~1_combout = (!\ula_|video_|vga_hc [4] & (!\ula_|video_|vga_hc [7] & (\ula_|video_|Equal0~0_combout & \ula_|video_|vga_hc [5]))) + + .dataa(\ula_|video_|vga_hc [4]), + .datab(\ula_|video_|vga_hc [7]), + .datac(\ula_|video_|Equal0~0_combout ), + .datad(\ula_|video_|vga_hc [5]), + .cin(gnd), + .combout(\ula_|video_|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Equal0~1 .lut_mask = 16'h1000; +defparam \ula_|video_|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y31_N8 +cycloneive_lcell_comb \ula_|video_|Equal1~0 ( +// Equation(s): +// \ula_|video_|Equal1~0_combout = ((\ula_|video_|vga_hc [6]) # ((!\ula_|video_|Equal0~1_combout ) # (!\ula_|video_|vga_hc [8]))) # (!\ula_|video_|vga_hc [9]) + + .dataa(\ula_|video_|vga_hc [9]), + .datab(\ula_|video_|vga_hc [6]), + .datac(\ula_|video_|vga_hc [8]), + .datad(\ula_|video_|Equal0~1_combout ), + .cin(gnd), + .combout(\ula_|video_|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Equal1~0 .lut_mask = 16'hDFFF; +defparam \ula_|video_|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y31_N2 +cycloneive_lcell_comb \ula_|video_|Add1~0 ( +// Equation(s): +// \ula_|video_|Add1~0_combout = \ula_|video_|vga_vc [0] $ (VCC) +// \ula_|video_|Add1~1 = CARRY(\ula_|video_|vga_vc [0]) + + .dataa(\ula_|video_|vga_vc [0]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\ula_|video_|Add1~0_combout ), + .cout(\ula_|video_|Add1~1 )); +// synopsys translate_off +defparam \ula_|video_|Add1~0 .lut_mask = 16'h55AA; +defparam \ula_|video_|Add1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y31_N28 +cycloneive_lcell_comb \ula_|video_|vga_vc[0]~0 ( +// Equation(s): +// \ula_|video_|vga_vc[0]~0_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [0]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~0_combout )))) + + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Equal3~1_combout ), + .datac(\ula_|video_|Add1~0_combout ), + .datad(\ula_|video_|vga_vc [0]), + .cin(gnd), + .combout(\ula_|video_|vga_vc[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[0]~0 .lut_mask = 16'h3210; +defparam \ula_|video_|vga_vc[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y32_N29 +dffeas \ula_|video_|vga_vc[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|vga_vc[0]~0_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[0] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y31_N4 +cycloneive_lcell_comb \ula_|video_|Add1~2 ( +// Equation(s): +// \ula_|video_|Add1~2_combout = (\ula_|video_|vga_vc [1] & (!\ula_|video_|Add1~1 )) # (!\ula_|video_|vga_vc [1] & ((\ula_|video_|Add1~1 ) # (GND))) +// \ula_|video_|Add1~3 = CARRY((!\ula_|video_|Add1~1 ) # (!\ula_|video_|vga_vc [1])) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [1]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add1~1 ), + .combout(\ula_|video_|Add1~2_combout ), + .cout(\ula_|video_|Add1~3 )); +// synopsys translate_off +defparam \ula_|video_|Add1~2 .lut_mask = 16'h3C3F; +defparam \ula_|video_|Add1~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y32_N10 +cycloneive_lcell_comb \ula_|video_|vga_vc[1]~1 ( +// Equation(s): +// \ula_|video_|vga_vc[1]~1_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [1]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~2_combout )))) + + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Add1~2_combout ), + .datac(\ula_|video_|vga_vc [1]), + .datad(\ula_|video_|Equal3~1_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[1]~1 .lut_mask = 16'h00E4; +defparam \ula_|video_|vga_vc[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y32_N11 +dffeas \ula_|video_|vga_vc[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[1]~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[1] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y31_N6 +cycloneive_lcell_comb \ula_|video_|Add1~4 ( +// Equation(s): +// \ula_|video_|Add1~4_combout = (\ula_|video_|vga_vc [2] & (\ula_|video_|Add1~3 $ (GND))) # (!\ula_|video_|vga_vc [2] & (!\ula_|video_|Add1~3 & VCC)) +// \ula_|video_|Add1~5 = CARRY((\ula_|video_|vga_vc [2] & !\ula_|video_|Add1~3 )) + + .dataa(\ula_|video_|vga_vc [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add1~3 ), + .combout(\ula_|video_|Add1~4_combout ), + .cout(\ula_|video_|Add1~5 )); +// synopsys translate_off +defparam \ula_|video_|Add1~4 .lut_mask = 16'hA50A; +defparam \ula_|video_|Add1~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y31_N22 +cycloneive_lcell_comb \ula_|video_|vga_vc[2]~2 ( +// Equation(s): +// \ula_|video_|vga_vc[2]~2_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [2])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~4_combout ))))) + + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Equal3~1_combout ), + .datac(\ula_|video_|vga_vc [2]), + .datad(\ula_|video_|Add1~4_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[2]~2 .lut_mask = 16'h3120; +defparam \ula_|video_|vga_vc[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y32_N24 +cycloneive_lcell_comb \ula_|video_|vga_vc[2]~feeder ( +// Equation(s): +// \ula_|video_|vga_vc[2]~feeder_combout = \ula_|video_|vga_vc[2]~2_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|vga_vc[2]~2_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[2]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|vga_vc[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y32_N25 +dffeas \ula_|video_|vga_vc[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[2] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y31_N8 +cycloneive_lcell_comb \ula_|video_|Add1~6 ( +// Equation(s): +// \ula_|video_|Add1~6_combout = (\ula_|video_|vga_vc [3] & (!\ula_|video_|Add1~5 )) # (!\ula_|video_|vga_vc [3] & ((\ula_|video_|Add1~5 ) # (GND))) +// \ula_|video_|Add1~7 = CARRY((!\ula_|video_|Add1~5 ) # (!\ula_|video_|vga_vc [3])) .dataa(\ula_|video_|vga_vc [3]), - .datab(\ula_|video_|vga_vc [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add1~5 ), + .combout(\ula_|video_|Add1~6_combout ), + .cout(\ula_|video_|Add1~7 )); +// synopsys translate_off +defparam \ula_|video_|Add1~6 .lut_mask = 16'h5A5F; +defparam \ula_|video_|Add1~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y31_N24 +cycloneive_lcell_comb \ula_|video_|vga_vc[3]~3 ( +// Equation(s): +// \ula_|video_|vga_vc[3]~3_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [3])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~6_combout ))))) + + .dataa(\ula_|video_|vga_vc [3]), + .datab(\ula_|video_|Equal3~1_combout ), + .datac(\ula_|video_|Add1~6_combout ), + .datad(\ula_|video_|Equal1~0_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[3]~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[3]~3 .lut_mask = 16'h2230; +defparam \ula_|video_|vga_vc[3]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y32_N31 +dffeas \ula_|video_|vga_vc[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|vga_vc[3]~3_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[3] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y31_N10 +cycloneive_lcell_comb \ula_|video_|Add1~8 ( +// Equation(s): +// \ula_|video_|Add1~8_combout = (\ula_|video_|vga_vc [4] & (\ula_|video_|Add1~7 $ (GND))) # (!\ula_|video_|vga_vc [4] & (!\ula_|video_|Add1~7 & VCC)) +// \ula_|video_|Add1~9 = CARRY((\ula_|video_|vga_vc [4] & !\ula_|video_|Add1~7 )) + + .dataa(\ula_|video_|vga_vc [4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add1~7 ), + .combout(\ula_|video_|Add1~8_combout ), + .cout(\ula_|video_|Add1~9 )); +// synopsys translate_off +defparam \ula_|video_|Add1~8 .lut_mask = 16'hA50A; +defparam \ula_|video_|Add1~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y32_N6 +cycloneive_lcell_comb \ula_|video_|vga_vc[4]~5 ( +// Equation(s): +// \ula_|video_|vga_vc[4]~5_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [4]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~8_combout )))) + + .dataa(\ula_|video_|Equal3~1_combout ), + .datab(\ula_|video_|Add1~8_combout ), + .datac(\ula_|video_|vga_vc [4]), + .datad(\ula_|video_|Equal1~0_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[4]~5_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[4]~5 .lut_mask = 16'h5044; +defparam \ula_|video_|vga_vc[4]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y32_N7 +dffeas \ula_|video_|vga_vc[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[4]~5_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[4] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y31_N12 +cycloneive_lcell_comb \ula_|video_|Add1~10 ( +// Equation(s): +// \ula_|video_|Add1~10_combout = (\ula_|video_|vga_vc [5] & (!\ula_|video_|Add1~9 )) # (!\ula_|video_|vga_vc [5] & ((\ula_|video_|Add1~9 ) # (GND))) +// \ula_|video_|Add1~11 = CARRY((!\ula_|video_|Add1~9 ) # (!\ula_|video_|vga_vc [5])) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [5]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add1~9 ), + .combout(\ula_|video_|Add1~10_combout ), + .cout(\ula_|video_|Add1~11 )); +// synopsys translate_off +defparam \ula_|video_|Add1~10 .lut_mask = 16'h3C3F; +defparam \ula_|video_|Add1~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y31_N14 +cycloneive_lcell_comb \ula_|video_|Add1~12 ( +// Equation(s): +// \ula_|video_|Add1~12_combout = (\ula_|video_|vga_vc [6] & (\ula_|video_|Add1~11 $ (GND))) # (!\ula_|video_|vga_vc [6] & (!\ula_|video_|Add1~11 & VCC)) +// \ula_|video_|Add1~13 = CARRY((\ula_|video_|vga_vc [6] & !\ula_|video_|Add1~11 )) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [6]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add1~11 ), + .combout(\ula_|video_|Add1~12_combout ), + .cout(\ula_|video_|Add1~13 )); +// synopsys translate_off +defparam \ula_|video_|Add1~12 .lut_mask = 16'hC30C; +defparam \ula_|video_|Add1~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y32_N0 +cycloneive_lcell_comb \ula_|video_|vga_vc[6]~4 ( +// Equation(s): +// \ula_|video_|vga_vc[6]~4_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [6]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~12_combout )))) + + .dataa(\ula_|video_|Equal3~1_combout ), + .datab(\ula_|video_|Add1~12_combout ), + .datac(\ula_|video_|vga_vc [6]), + .datad(\ula_|video_|Equal1~0_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[6]~4_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[6]~4 .lut_mask = 16'h5044; +defparam \ula_|video_|vga_vc[6]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y32_N1 +dffeas \ula_|video_|vga_vc[6] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[6]~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[6] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y31_N16 +cycloneive_lcell_comb \ula_|video_|Add1~14 ( +// Equation(s): +// \ula_|video_|Add1~14_combout = (\ula_|video_|vga_vc [7] & (!\ula_|video_|Add1~13 )) # (!\ula_|video_|vga_vc [7] & ((\ula_|video_|Add1~13 ) # (GND))) +// \ula_|video_|Add1~15 = CARRY((!\ula_|video_|Add1~13 ) # (!\ula_|video_|vga_vc [7])) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [7]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add1~13 ), + .combout(\ula_|video_|Add1~14_combout ), + .cout(\ula_|video_|Add1~15 )); +// synopsys translate_off +defparam \ula_|video_|Add1~14 .lut_mask = 16'h3C3F; +defparam \ula_|video_|Add1~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y32_N8 +cycloneive_lcell_comb \ula_|video_|vga_vc[7]~6 ( +// Equation(s): +// \ula_|video_|vga_vc[7]~6_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [7]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~14_combout )))) + + .dataa(\ula_|video_|Equal3~1_combout ), + .datab(\ula_|video_|Add1~14_combout ), + .datac(\ula_|video_|vga_vc [7]), + .datad(\ula_|video_|Equal1~0_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[7]~6_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[7]~6 .lut_mask = 16'h5044; +defparam \ula_|video_|vga_vc[7]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y32_N9 +dffeas \ula_|video_|vga_vc[7] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[7]~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[7] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y31_N18 +cycloneive_lcell_comb \ula_|video_|Add1~16 ( +// Equation(s): +// \ula_|video_|Add1~16_combout = (\ula_|video_|vga_vc [8] & (\ula_|video_|Add1~15 $ (GND))) # (!\ula_|video_|vga_vc [8] & (!\ula_|video_|Add1~15 & VCC)) +// \ula_|video_|Add1~17 = CARRY((\ula_|video_|vga_vc [8] & !\ula_|video_|Add1~15 )) + + .dataa(\ula_|video_|vga_vc [8]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add1~15 ), + .combout(\ula_|video_|Add1~16_combout ), + .cout(\ula_|video_|Add1~17 )); +// synopsys translate_off +defparam \ula_|video_|Add1~16 .lut_mask = 16'hA50A; +defparam \ula_|video_|Add1~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y32_N0 +cycloneive_lcell_comb \ula_|video_|vga_vc[8]~7 ( +// Equation(s): +// \ula_|video_|vga_vc[8]~7_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [8]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~16_combout )))) + + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Add1~16_combout ), + .datac(\ula_|video_|vga_vc [8]), + .datad(\ula_|video_|Equal3~1_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[8]~7_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[8]~7 .lut_mask = 16'h00E4; +defparam \ula_|video_|vga_vc[8]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y32_N1 +dffeas \ula_|video_|vga_vc[8] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[8]~7_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [8]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[8] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y31_N20 +cycloneive_lcell_comb \ula_|video_|Add1~18 ( +// Equation(s): +// \ula_|video_|Add1~18_combout = \ula_|video_|Add1~17 $ (\ula_|video_|vga_vc [9]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|vga_vc [9]), + .cin(\ula_|video_|Add1~17 ), + .combout(\ula_|video_|Add1~18_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Add1~18 .lut_mask = 16'h0FF0; +defparam \ula_|video_|Add1~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y32_N28 +cycloneive_lcell_comb \ula_|video_|vga_vc[9]~9 ( +// Equation(s): +// \ula_|video_|vga_vc[9]~9_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [9]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~18_combout )))) + + .dataa(\ula_|video_|Add1~18_combout ), + .datab(\ula_|video_|Equal1~0_combout ), .datac(\ula_|video_|vga_vc [9]), + .datad(\ula_|video_|Equal3~1_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[9]~9_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[9]~9 .lut_mask = 16'h00E2; +defparam \ula_|video_|vga_vc[9]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y32_N29 +dffeas \ula_|video_|vga_vc[9] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[9]~9_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [9]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[9] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y30_N0 +cycloneive_lcell_comb \ula_|video_|Equal3~0 ( +// Equation(s): +// \ula_|video_|Equal3~0_combout = (\ula_|video_|vga_vc [0] & (\ula_|video_|vga_vc [3] & (\ula_|video_|vga_vc [2] & !\ula_|video_|vga_vc [1]))) + + .dataa(\ula_|video_|vga_vc [0]), + .datab(\ula_|video_|vga_vc [3]), + .datac(\ula_|video_|vga_vc [2]), + .datad(\ula_|video_|vga_vc [1]), + .cin(gnd), + .combout(\ula_|video_|Equal3~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Equal3~0 .lut_mask = 16'h0080; +defparam \ula_|video_|Equal3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y32_N2 +cycloneive_lcell_comb \ula_|video_|Equal2~0 ( +// Equation(s): +// \ula_|video_|Equal2~0_combout = (!\ula_|video_|vga_vc [6] & (!\ula_|video_|vga_vc [8] & (!\ula_|video_|vga_vc [4] & !\ula_|video_|vga_vc [7]))) + + .dataa(\ula_|video_|vga_vc [6]), + .datab(\ula_|video_|vga_vc [8]), + .datac(\ula_|video_|vga_vc [4]), + .datad(\ula_|video_|vga_vc [7]), + .cin(gnd), + .combout(\ula_|video_|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Equal2~0 .lut_mask = 16'h0001; +defparam \ula_|video_|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y32_N10 +cycloneive_lcell_comb \ula_|video_|Equal3~1 ( +// Equation(s): +// \ula_|video_|Equal3~1_combout = (!\ula_|video_|vga_vc [5] & (\ula_|video_|vga_vc [9] & (\ula_|video_|Equal3~0_combout & \ula_|video_|Equal2~0_combout ))) + + .dataa(\ula_|video_|vga_vc [5]), + .datab(\ula_|video_|vga_vc [9]), + .datac(\ula_|video_|Equal3~0_combout ), + .datad(\ula_|video_|Equal2~0_combout ), + .cin(gnd), + .combout(\ula_|video_|Equal3~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Equal3~1 .lut_mask = 16'h4000; +defparam \ula_|video_|Equal3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y32_N30 +cycloneive_lcell_comb \ula_|video_|vga_vc[5]~8 ( +// Equation(s): +// \ula_|video_|vga_vc[5]~8_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [5]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~10_combout )))) + + .dataa(\ula_|video_|Equal3~1_combout ), + .datab(\ula_|video_|Add1~10_combout ), + .datac(\ula_|video_|vga_vc [5]), + .datad(\ula_|video_|Equal1~0_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[5]~8_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[5]~8 .lut_mask = 16'h5044; +defparam \ula_|video_|vga_vc[5]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y32_N31 +dffeas \ula_|video_|vga_vc[5] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[5]~8_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[5] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y31_N26 +cycloneive_lcell_comb \ula_|video_|Equal2~1 ( +// Equation(s): +// \ula_|video_|Equal2~1_combout = (!\ula_|video_|vga_vc [2] & (!\ula_|video_|vga_vc [9] & (!\ula_|video_|vga_vc [3] & !\ula_|video_|vga_vc [0]))) + + .dataa(\ula_|video_|vga_vc [2]), + .datab(\ula_|video_|vga_vc [9]), + .datac(\ula_|video_|vga_vc [3]), .datad(\ula_|video_|vga_vc [0]), .cin(gnd), .combout(\ula_|video_|Equal2~1_combout ), @@ -19059,41 +6088,68 @@ defparam \ula_|video_|Equal2~1 .lut_mask = 16'h0001; defparam \ula_|video_|Equal2~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y33_N14 +// Location: LCCOMB_X35_Y32_N24 cycloneive_lcell_comb \ula_|video_|Equal2~2 ( // Equation(s): -// \ula_|video_|Equal2~2_combout = (\ula_|video_|Equal2~1_combout & (\ula_|video_|Equal2~0_combout & !\ula_|video_|vga_vc [5])) +// \ula_|video_|Equal2~2_combout = (!\ula_|video_|vga_vc [5] & (\ula_|video_|Equal2~1_combout & \ula_|video_|Equal2~0_combout )) - .dataa(gnd), + .dataa(\ula_|video_|vga_vc [5]), .datab(\ula_|video_|Equal2~1_combout ), - .datac(\ula_|video_|Equal2~0_combout ), - .datad(\ula_|video_|vga_vc [5]), + .datac(gnd), + .datad(\ula_|video_|Equal2~0_combout ), .cin(gnd), .combout(\ula_|video_|Equal2~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Equal2~2 .lut_mask = 16'h00C0; +defparam \ula_|video_|Equal2~2 .lut_mask = 16'h4400; defparam \ula_|video_|Equal2~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y31_N28 +// Location: IOIBUF_X27_Y0_N15 +cycloneive_io_ibuf \SW[1]~input ( + .i(SW[1]), + .ibar(gnd), + .o(\SW[1]~input_o )); +// synopsys translate_off +defparam \SW[1]~input .bus_hold = "false"; +defparam \SW[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y33_N2 +cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_13~0 ( +// Equation(s): +// \z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout = (!\ula_|video_|vga_vc [1] & (!\ula_|video_|vga_hc [8] & (!\ula_|video_|vga_hc [9] & !\SW[1]~input_o ))) + + .dataa(\ula_|video_|vga_vc [1]), + .datab(\ula_|video_|vga_hc [8]), + .datac(\ula_|video_|vga_hc [9]), + .datad(\SW[1]~input_o ), + .cin(gnd), + .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13~0 .lut_mask = 16'h0001; +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y33_N20 cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_13 ( // Equation(s): -// \z80_|interrupts_|SYNTHESIZED_WIRE_13~combout = (!\ula_|video_|vga_hc [7] & (\z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout & (\z80_|interrupts_|iff1~q & \ula_|video_|Equal2~2_combout ))) +// \z80_|interrupts_|SYNTHESIZED_WIRE_13~combout = (\z80_|interrupts_|iff1~q & (\ula_|video_|Equal2~2_combout & (!\ula_|video_|vga_hc [7] & \z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout ))) - .dataa(\ula_|video_|vga_hc [7]), - .datab(\z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout ), - .datac(\z80_|interrupts_|iff1~q ), - .datad(\ula_|video_|Equal2~2_combout ), + .dataa(\z80_|interrupts_|iff1~q ), + .datab(\ula_|video_|Equal2~2_combout ), + .datac(\ula_|video_|vga_hc [7]), + .datad(\z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout ), .cin(gnd), .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_13~combout ), .cout()); // synopsys translate_off -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13 .lut_mask = 16'h4000; +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13 .lut_mask = 16'h0800; defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X35_Y31_N29 +// Location: FF_X35_Y33_N21 dffeas \z80_|interrupts_|int_armed ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|interrupts_|SYNTHESIZED_WIRE_13~combout ), @@ -19112,15 +6168,32 @@ defparam \z80_|interrupts_|int_armed .is_wysiwyg = "true"; defparam \z80_|interrupts_|int_armed .power_up = "low"; // synopsys translate_on -// Location: FF_X32_Y15_N11 +// Location: LCCOMB_X28_Y13_N30 +cycloneive_lcell_comb \z80_|interrupts_|DFFE_inst44~feeder ( +// Equation(s): +// \z80_|interrupts_|DFFE_inst44~feeder_combout = \z80_|interrupts_|int_armed~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|interrupts_|int_armed~q ), + .cin(gnd), + .combout(\z80_|interrupts_|DFFE_inst44~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|DFFE_inst44~feeder .lut_mask = 16'hFF00; +defparam \z80_|interrupts_|DFFE_inst44~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y13_N31 dffeas \z80_|interrupts_|DFFE_inst44 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|interrupts_|int_armed~q ), + .d(\z80_|interrupts_|DFFE_inst44~feeder_combout ), + .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), - .sload(vcc), + .sload(gnd), .ena(\z80_|interrupts_|test1~3_combout ), .devclrn(devclrn), .devpor(devpor), @@ -19131,14509 +6204,44 @@ defparam \z80_|interrupts_|DFFE_inst44 .is_wysiwyg = "true"; defparam \z80_|interrupts_|DFFE_inst44 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~38 ( +// Location: LCCOMB_X28_Y13_N4 +cycloneive_lcell_comb \z80_|decode_state_|in_halt~0 ( // Equation(s): -// \z80_|execute_|pc_inc_hold~38_combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # ((\z80_|decode_state_|in_halt~q ) # (\z80_|interrupts_|DFFE_inst44~q )) +// \z80_|decode_state_|in_halt~0_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (!\z80_|interrupts_|DFFE_inst44~q & \z80_|decode_state_|in_halt~q )) .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), .datab(gnd), - .datac(\z80_|decode_state_|in_halt~q ), - .datad(\z80_|interrupts_|DFFE_inst44~q ), + .datac(\z80_|interrupts_|DFFE_inst44~q ), + .datad(\z80_|decode_state_|in_halt~q ), .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~38_combout ), + .combout(\z80_|decode_state_|in_halt~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~38 .lut_mask = 16'hFFFA; -defparam \z80_|execute_|pc_inc_hold~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~91 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~91_combout = (((!\z80_|sequencer_|DFFE_M3_ff~q & !\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|pla_decode_|Equal34~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~91_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~91 .lut_mask = 16'h57FF; -defparam \z80_|execute_|ctl_inc_cy~91 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~45 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~45_combout = (\z80_|pla_decode_|Equal19~0_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ctl_mRead~36_combout & \z80_|execute_|pc_inc_hold~29_combout )))) # (!\z80_|pla_decode_|Equal19~0_combout & -// (((\z80_|execute_|ctl_mRead~36_combout & \z80_|execute_|pc_inc_hold~29_combout )))) - - .dataa(\z80_|pla_decode_|Equal19~0_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_mRead~36_combout ), - .datad(\z80_|execute_|pc_inc_hold~29_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~45 .lut_mask = 16'hF888; -defparam \z80_|execute_|pc_inc_hold~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~44 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~44_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & ((\z80_|pla_decode_|Equal19~0_combout ) # ((!\z80_|execute_|pc_inc_hold~49_combout ) # (!\z80_|execute_|ctl_bus_db_oe~1_combout )))) - - .dataa(\z80_|pla_decode_|Equal19~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .datad(\z80_|execute_|pc_inc_hold~49_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~44 .lut_mask = 16'h8CCC; -defparam \z80_|execute_|pc_inc_hold~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N2 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~46 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~46_combout = (\z80_|execute_|pc_inc_hold~45_combout ) # ((\z80_|execute_|pc_inc_hold~44_combout ) # ((\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|pc_inc_hold~49_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~45_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|pc_inc_hold~44_combout ), - .datad(\z80_|execute_|pc_inc_hold~49_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~46 .lut_mask = 16'hFAFE; -defparam \z80_|execute_|pc_inc_hold~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N18 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~37 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~37_combout = (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|execute_|pc_inc_hold~29_combout ) # ((\z80_|pla_decode_|Equal52~1_combout & \z80_|execute_|ctl_alu_op_low~8_combout )))) # (!\z80_|pla_decode_|Equal10~0_combout & -// (\z80_|pla_decode_|Equal52~1_combout & (\z80_|execute_|ctl_alu_op_low~8_combout ))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|pla_decode_|Equal52~1_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datad(\z80_|execute_|pc_inc_hold~29_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~37 .lut_mask = 16'hEAC0; -defparam \z80_|execute_|pc_inc_hold~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N12 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~50 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~50_combout = (\z80_|execute_|pc_inc_hold~37_combout ) # ((\z80_|execute_|ixy_d~16_combout & (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ))) - - .dataa(\z80_|execute_|ixy_d~16_combout ), - .datab(\z80_|execute_|pc_inc_hold~37_combout ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~50 .lut_mask = 16'hECCC; -defparam \z80_|execute_|pc_inc_hold~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N22 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~33 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~33_combout = (\z80_|execute_|ctl_mRead~10_combout & (((\z80_|execute_|ctl_alu_op_low~8_combout ) # (\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|execute_|ctl_mRead~10_combout & (\z80_|pla_decode_|Equal6~1_combout & -// ((\z80_|execute_|ctl_alu_op_low~8_combout ) # (\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|pla_decode_|Equal6~1_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~33 .lut_mask = 16'hEEE0; -defparam \z80_|execute_|pc_inc_hold~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|execute_|ixy_d~5_combout & (\z80_|pla_decode_|Equal55~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal33~2_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|decode_state_|use_ixiy~combout ), - .datad(\z80_|pla_decode_|Equal33~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N26 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~31 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~31_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ) # ((\z80_|execute_|ctl_alu_op_low~8_combout & ((\z80_|execute_|ctl_mRead~14_combout ) # (!\z80_|execute_|pc_inc_hold~28_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ), - .datac(\z80_|execute_|ctl_mRead~14_combout ), - .datad(\z80_|execute_|pc_inc_hold~28_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~31 .lut_mask = 16'hECEE; -defparam \z80_|execute_|pc_inc_hold~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N12 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~32 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~32_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & (((\z80_|execute_|ctl_mRead~9_combout ) # (\z80_|execute_|ctl_mRead~15_combout )))) # (!\z80_|execute_|ctl_alu_op_low~8_combout & (\z80_|execute_|ixy_d~5_combout & -// ((\z80_|execute_|ctl_mRead~15_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_mRead~9_combout ), - .datad(\z80_|execute_|ctl_mRead~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~32 .lut_mask = 16'hEEA0; -defparam \z80_|execute_|pc_inc_hold~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N16 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~34 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~34_combout = (\z80_|execute_|pc_inc_hold~33_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ) # ((\z80_|execute_|pc_inc_hold~31_combout ) # (\z80_|execute_|pc_inc_hold~32_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~33_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ), - .datac(\z80_|execute_|pc_inc_hold~31_combout ), - .datad(\z80_|execute_|pc_inc_hold~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~34 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|pc_inc_hold~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N28 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~51 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~51_combout = (((!\z80_|sequencer_|DFFE_M3_ff~q & !\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|execute_|ctl_mRead~17_combout ) - - .dataa(\z80_|execute_|ctl_mRead~17_combout ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~51_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~51 .lut_mask = 16'h57FF; -defparam \z80_|execute_|pc_inc_hold~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N22 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~30 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~30_combout = (\z80_|pla_decode_|Equal12~1_combout ) # (((!\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ctl_alu_op_low~8_combout )) # (!\z80_|pla_decode_|Equal25~0_combout )) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|pla_decode_|Equal12~1_combout ), - .datac(\z80_|pla_decode_|Equal25~0_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~30 .lut_mask = 16'hCFDF; -defparam \z80_|execute_|pc_inc_hold~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N6 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~52 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~52_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|execute_|ctl_mRead~8_combout & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (\z80_|sequencer_|DFFE_M2_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|execute_|ctl_mRead~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~52_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~52 .lut_mask = 16'hA800; -defparam \z80_|execute_|pc_inc_hold~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N8 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~35 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~35_combout = (!\z80_|execute_|pc_inc_hold~34_combout & (\z80_|execute_|pc_inc_hold~51_combout & (\z80_|execute_|pc_inc_hold~30_combout & !\z80_|execute_|pc_inc_hold~52_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~34_combout ), - .datab(\z80_|execute_|pc_inc_hold~51_combout ), - .datac(\z80_|execute_|pc_inc_hold~30_combout ), - .datad(\z80_|execute_|pc_inc_hold~52_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~35 .lut_mask = 16'h0040; -defparam \z80_|execute_|pc_inc_hold~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N4 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~36 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~36_combout = ((\z80_|pla_decode_|Equal11~0_combout & ((\z80_|execute_|ctl_mWrite~7_combout ) # (\z80_|execute_|ctl_alu_shift_oe~14_combout )))) # (!\z80_|execute_|pc_inc_hold~35_combout ) - - .dataa(\z80_|execute_|ctl_mWrite~7_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|pc_inc_hold~35_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~36 .lut_mask = 16'hCF8F; -defparam \z80_|execute_|pc_inc_hold~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~44 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~44_combout = (((!\z80_|pla_decode_|Equal21~0_combout & !\z80_|pla_decode_|Equal3~0_combout )) # (!\z80_|pla_decode_|Equal24~0_combout )) # (!\z80_|execute_|ctl_alu_op_low~8_combout ) - - .dataa(\z80_|pla_decode_|Equal21~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|pla_decode_|Equal3~0_combout ), - .datad(\z80_|pla_decode_|Equal24~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~44 .lut_mask = 16'h37FF; -defparam \z80_|execute_|ctl_inc_cy~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|execute_|ixy_d~10_combout )) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(gnd), - .datad(\z80_|execute_|ixy_d~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 .lut_mask = 16'h8800; -defparam \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~45 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~45_combout = (!\z80_|execute_|pc_inc_hold~50_combout & (!\z80_|execute_|pc_inc_hold~36_combout & (\z80_|execute_|ctl_inc_cy~44_combout & !\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~50_combout ), - .datab(\z80_|execute_|pc_inc_hold~36_combout ), - .datac(\z80_|execute_|ctl_inc_cy~44_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~45 .lut_mask = 16'h0010; -defparam \z80_|execute_|ctl_inc_cy~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~43 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~43_combout = (\z80_|execute_|ctl_mWrite~2_combout & (\z80_|pla_decode_|Equal55~0_combout & ((\z80_|execute_|ctl_mWrite~7_combout ) # (\z80_|execute_|ctl_alu_shift_oe~14_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~7_combout ), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~43 .lut_mask = 16'hC080; -defparam \z80_|execute_|pc_inc_hold~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~71 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~71_combout = (\z80_|execute_|ctl_inc_cy~91_combout & (!\z80_|execute_|pc_inc_hold~46_combout & (\z80_|execute_|ctl_inc_cy~45_combout & !\z80_|execute_|pc_inc_hold~43_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~91_combout ), - .datab(\z80_|execute_|pc_inc_hold~46_combout ), - .datac(\z80_|execute_|ctl_inc_cy~45_combout ), - .datad(\z80_|execute_|pc_inc_hold~43_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~71_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~71 .lut_mask = 16'h0020; -defparam \z80_|execute_|ctl_inc_cy~71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~73 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~73_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (((\z80_|execute_|ctl_inc_cy~72_combout & \z80_|execute_|ctl_inc_cy~71_combout )) # (!\z80_|execute_|pc_inc_hold~38_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|execute_|ctl_inc_cy~72_combout ), - .datac(\z80_|execute_|pc_inc_hold~38_combout ), - .datad(\z80_|execute_|ctl_inc_cy~71_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~73_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~73 .lut_mask = 16'h8A0A; -defparam \z80_|execute_|ctl_inc_cy~73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~46 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~46_combout = (\z80_|execute_|ixy_d~5_combout & (\z80_|execute_|ctl_mWrite~16_combout & ((\z80_|execute_|ctl_inc_cy~45_combout ) # (!\z80_|execute_|pc_inc_hold~38_combout )))) - - .dataa(\z80_|execute_|ctl_inc_cy~45_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|pc_inc_hold~38_combout ), - .datad(\z80_|execute_|ctl_mWrite~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~46 .lut_mask = 16'h8C00; -defparam \z80_|execute_|ctl_inc_cy~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N24 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~53 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~53_combout = (\z80_|pla_decode_|Equal11~0_combout & (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T4_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|sequencer_|DFFE_M4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~53_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~53 .lut_mask = 16'hE000; -defparam \z80_|execute_|pc_inc_hold~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N0 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~39 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~39_combout = (!\z80_|execute_|pc_inc_hold~50_combout & (!\z80_|execute_|pc_inc_hold~53_combout & (\z80_|execute_|pc_inc_hold~35_combout & !\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~50_combout ), - .datab(\z80_|execute_|pc_inc_hold~53_combout ), - .datac(\z80_|execute_|pc_inc_hold~35_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~39 .lut_mask = 16'h0010; -defparam \z80_|execute_|pc_inc_hold~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N10 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~47 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~47_combout = (\z80_|execute_|pc_inc_hold~46_combout ) # ((\z80_|execute_|pc_inc_hold~43_combout ) # ((!\z80_|execute_|ctl_inc_cy~44_combout ) # (!\z80_|execute_|pc_inc_hold~39_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~46_combout ), - .datab(\z80_|execute_|pc_inc_hold~43_combout ), - .datac(\z80_|execute_|pc_inc_hold~39_combout ), - .datad(\z80_|execute_|ctl_inc_cy~44_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~47 .lut_mask = 16'hEFFF; -defparam \z80_|execute_|pc_inc_hold~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~74 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~74_combout = (((!\z80_|execute_|ctl_inc_cy~40_combout ) # (!\z80_|execute_|ctl_inc_cy~34_combout )) # (!\z80_|execute_|ctl_inc_cy~35_combout )) # (!\z80_|execute_|ctl_inc_cy~43_combout ) - - .dataa(\z80_|execute_|ctl_inc_cy~43_combout ), - .datab(\z80_|execute_|ctl_inc_cy~35_combout ), - .datac(\z80_|execute_|ctl_inc_cy~34_combout ), - .datad(\z80_|execute_|ctl_inc_cy~40_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~74_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~74 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_inc_cy~74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~78 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~78_combout = ((\z80_|execute_|ctl_inc_cy~74_combout ) # (!\z80_|execute_|ctl_inc_cy~77_combout )) # (!\z80_|execute_|ctl_inc_cy~39_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_inc_cy~39_combout ), - .datac(\z80_|execute_|ctl_inc_cy~77_combout ), - .datad(\z80_|execute_|ctl_inc_cy~74_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~78_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~78 .lut_mask = 16'hFF3F; -defparam \z80_|execute_|ctl_inc_cy~78 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~79 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~79_combout = (\z80_|execute_|ctl_inc_cy~78_combout & (((!\z80_|execute_|pc_inc_hold~47_combout & \z80_|execute_|ctl_inc_cy~91_combout )) # (!\z80_|execute_|pc_inc_hold~38_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~47_combout ), - .datab(\z80_|execute_|ctl_inc_cy~78_combout ), - .datac(\z80_|execute_|pc_inc_hold~38_combout ), - .datad(\z80_|execute_|ctl_inc_cy~91_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~79_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~79 .lut_mask = 16'h4C0C; -defparam \z80_|execute_|ctl_inc_cy~79 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~80 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~80_combout = (\z80_|execute_|ctl_inc_cy~45_combout & (\z80_|execute_|ctl_alu_op_low~8_combout & (\z80_|execute_|ctl_mRead~36_combout & !\z80_|execute_|pc_inc_hold~43_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~45_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|execute_|ctl_mRead~36_combout ), - .datad(\z80_|execute_|pc_inc_hold~43_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~80_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~80 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_inc_cy~80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~81 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~81_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal19~1_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # (\z80_|execute_|ixy_d~9_combout )))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|pla_decode_|Equal19~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~81_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~81 .lut_mask = 16'hA800; -defparam \z80_|execute_|ctl_inc_cy~81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~82 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~82_combout = (\z80_|execute_|ctl_inc_cy~81_combout ) # ((\z80_|pla_decode_|Equal19~0_combout & ((\z80_|execute_|ctl_state_alu~6_combout ) # (\z80_|execute_|ctl_alu_oe~2_combout )))) - - .dataa(\z80_|execute_|ctl_inc_cy~81_combout ), - .datab(\z80_|pla_decode_|Equal19~0_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_alu_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~82_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~82 .lut_mask = 16'hEEEA; -defparam \z80_|execute_|ctl_inc_cy~82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~83 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~83_combout = (\z80_|execute_|pc_inc_hold~47_combout & (!\z80_|execute_|pc_inc_hold~38_combout & ((\z80_|execute_|ctl_inc_cy~82_combout ) # (!\z80_|execute_|ctl_inc_cy~38_combout )))) # (!\z80_|execute_|pc_inc_hold~47_combout -// & ((\z80_|execute_|ctl_inc_cy~82_combout ) # ((!\z80_|execute_|ctl_inc_cy~38_combout )))) - - .dataa(\z80_|execute_|pc_inc_hold~47_combout ), - .datab(\z80_|execute_|ctl_inc_cy~82_combout ), - .datac(\z80_|execute_|pc_inc_hold~38_combout ), - .datad(\z80_|execute_|ctl_inc_cy~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~83_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~83 .lut_mask = 16'h4C5F; -defparam \z80_|execute_|ctl_inc_cy~83 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~84 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~84_combout = (\z80_|execute_|ctl_inc_cy~79_combout ) # ((\z80_|execute_|ctl_inc_cy~80_combout ) # (\z80_|execute_|ctl_inc_cy~83_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_inc_cy~79_combout ), - .datac(\z80_|execute_|ctl_inc_cy~80_combout ), - .datad(\z80_|execute_|ctl_inc_cy~83_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~84_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~84 .lut_mask = 16'hFFFC; -defparam \z80_|execute_|ctl_inc_cy~84 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N10 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~42 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~42_combout = ((\z80_|execute_|pc_inc_hold~34_combout ) # (\z80_|execute_|pc_inc_hold~52_combout )) # (!\z80_|execute_|pc_inc_hold~30_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|pc_inc_hold~30_combout ), - .datac(\z80_|execute_|pc_inc_hold~34_combout ), - .datad(\z80_|execute_|pc_inc_hold~52_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~42 .lut_mask = 16'hFFF3; -defparam \z80_|execute_|pc_inc_hold~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~90 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~90_combout = (((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|execute_|ctl_mRead~8_combout ) - - .dataa(\z80_|sequencer_|M5~q ), - .datab(\z80_|execute_|ctl_mRead~8_combout ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~90_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~90 .lut_mask = 16'h37FF; -defparam \z80_|execute_|ctl_inc_cy~90 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N2 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~41 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~41_combout = (\z80_|execute_|pc_inc_hold~31_combout ) # ((\z80_|execute_|pc_inc_hold~32_combout ) # ((\z80_|execute_|ixy_d~5_combout & \z80_|execute_|ctl_mRead~9_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~31_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_mRead~9_combout ), - .datad(\z80_|execute_|pc_inc_hold~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~41 .lut_mask = 16'hFFEA; -defparam \z80_|execute_|pc_inc_hold~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~66 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~66_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|execute_|ctl_mRead~14_combout & (!\z80_|decode_state_|in_halt~q & !\z80_|interrupts_|DFFE_inst44~q ))) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|execute_|ctl_mRead~14_combout ), - .datac(\z80_|decode_state_|in_halt~q ), - .datad(\z80_|interrupts_|DFFE_inst44~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~66_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~66 .lut_mask = 16'h0004; -defparam \z80_|execute_|ctl_inc_cy~66 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~67 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~67_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & ((\z80_|execute_|ctl_inc_cy~66_combout ) # ((!\z80_|execute_|ctl_reg_sys_hilo~20_combout & !\z80_|execute_|pc_inc_hold~31_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), - .datac(\z80_|execute_|pc_inc_hold~31_combout ), - .datad(\z80_|execute_|ctl_inc_cy~66_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~67_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~67 .lut_mask = 16'hAA02; -defparam \z80_|execute_|ctl_inc_cy~67 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~68 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~68_combout = (\z80_|execute_|ctl_inc_cy~67_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~14_combout & (!\z80_|execute_|pc_inc_hold~41_combout & \z80_|execute_|ctl_mRead~15_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|execute_|pc_inc_hold~41_combout ), - .datac(\z80_|execute_|ctl_inc_cy~67_combout ), - .datad(\z80_|execute_|ctl_mRead~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~68_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~68 .lut_mask = 16'hF2F0; -defparam \z80_|execute_|ctl_inc_cy~68 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~64 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~64_combout = (!\z80_|execute_|pc_inc_hold~31_combout & (((!\z80_|execute_|ctl_alu_op_low~8_combout & !\z80_|execute_|ixy_d~5_combout )) # (!\z80_|execute_|ctl_mRead~9_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datab(\z80_|execute_|ctl_mRead~9_combout ), - .datac(\z80_|execute_|pc_inc_hold~31_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~64_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~64 .lut_mask = 16'h0307; -defparam \z80_|execute_|ctl_inc_cy~64 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~63 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~63_combout = (\z80_|execute_|ctl_mRead~10_combout & (!\z80_|execute_|pc_inc_hold~34_combout & ((\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (\z80_|execute_|ctl_sw_4u~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|execute_|ctl_mRead~10_combout ), - .datac(\z80_|execute_|pc_inc_hold~34_combout ), - .datad(\z80_|execute_|ctl_sw_4u~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~63_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~63 .lut_mask = 16'h0C08; -defparam \z80_|execute_|ctl_inc_cy~63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~65 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~65_combout = (\z80_|execute_|ctl_inc_cy~63_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & ((\z80_|execute_|ctl_inc_cy~64_combout ) # (!\z80_|execute_|pc_inc_hold~38_combout )))) - - .dataa(\z80_|execute_|pc_inc_hold~38_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), - .datac(\z80_|execute_|ctl_inc_cy~64_combout ), - .datad(\z80_|execute_|ctl_inc_cy~63_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~65_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~65 .lut_mask = 16'hFFC4; -defparam \z80_|execute_|ctl_inc_cy~65 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~69 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~69_combout = (\z80_|execute_|ctl_inc_cy~68_combout ) # ((\z80_|execute_|ctl_inc_cy~65_combout ) # ((!\z80_|execute_|pc_inc_hold~42_combout & !\z80_|execute_|ctl_inc_cy~90_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~42_combout ), - .datab(\z80_|execute_|ctl_inc_cy~90_combout ), - .datac(\z80_|execute_|ctl_inc_cy~68_combout ), - .datad(\z80_|execute_|ctl_inc_cy~65_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~69_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~69 .lut_mask = 16'hFFF1; -defparam \z80_|execute_|ctl_inc_cy~69 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~49 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~49_combout = ((\z80_|pla_decode_|Equal9~1_combout & ((\z80_|execute_|ixy_d~9_combout ) # (\z80_|execute_|ctl_state_alu~6_combout )))) # (!\z80_|execute_|ctl_inc_cy~92_combout ) - - .dataa(\z80_|execute_|ixy_d~9_combout ), - .datab(\z80_|execute_|ctl_state_alu~6_combout ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|execute_|ctl_inc_cy~92_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~49 .lut_mask = 16'hE0FF; -defparam \z80_|execute_|ctl_inc_cy~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~50 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~50_combout = (\z80_|execute_|ixy_d~9_combout & ((\z80_|pla_decode_|Equal11~0_combout ) # ((\z80_|execute_|ctl_mWrite~4_combout & \z80_|execute_|ixy_d~7_combout )))) # (!\z80_|execute_|ixy_d~9_combout & -// (((\z80_|execute_|ctl_mWrite~4_combout & \z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|execute_|ixy_d~9_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~50 .lut_mask = 16'hF888; -defparam \z80_|execute_|ctl_inc_cy~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~51 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~51_combout = (\z80_|execute_|ctl_inc_cy~50_combout ) # (((\z80_|execute_|ctl_mWrite~4_combout & \z80_|execute_|ctl_mRead~11_combout )) # (!\z80_|execute_|ctl_inc_cy~94_combout )) - - .dataa(\z80_|execute_|ctl_inc_cy~50_combout ), - .datab(\z80_|execute_|ctl_mWrite~4_combout ), - .datac(\z80_|execute_|ctl_inc_cy~94_combout ), - .datad(\z80_|execute_|ctl_mRead~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~51_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~51 .lut_mask = 16'hEFAF; -defparam \z80_|execute_|ctl_inc_cy~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~52 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~52_combout = (\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ) # ((\z80_|execute_|ctl_inc_cy~51_combout ) # ((\z80_|execute_|ctl_alu_op_low~8_combout & \z80_|pla_decode_|Equal11~0_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|execute_|ctl_inc_cy~51_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~52_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~52 .lut_mask = 16'hFFEA; -defparam \z80_|execute_|ctl_inc_cy~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~36 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~36_combout = ((!\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|execute_|ctl_alu_op_low~8_combout & !\z80_|execute_|ixy_d~5_combout ))) # (!\z80_|execute_|ctl_mWrite~4_combout ) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|execute_|ctl_mWrite~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~36 .lut_mask = 16'h01FF; -defparam \z80_|execute_|ctl_inc_cy~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~37 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~37_combout = (\z80_|execute_|ctl_sw_2u~0_combout & (\z80_|execute_|ctl_inc_cy~36_combout & ((!\z80_|pla_decode_|Equal11~0_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ctl_sw_2u~0_combout ), - .datad(\z80_|execute_|ctl_inc_cy~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~37 .lut_mask = 16'h7000; -defparam \z80_|execute_|ctl_inc_cy~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~54 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~54_combout = ((\z80_|execute_|ctl_inc_cy~49_combout ) # ((\z80_|execute_|ctl_inc_cy~52_combout ) # (!\z80_|execute_|ctl_inc_cy~37_combout ))) # (!\z80_|execute_|ctl_inc_cy~53_combout ) - - .dataa(\z80_|execute_|ctl_inc_cy~53_combout ), - .datab(\z80_|execute_|ctl_inc_cy~49_combout ), - .datac(\z80_|execute_|ctl_inc_cy~52_combout ), - .datad(\z80_|execute_|ctl_inc_cy~37_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~54_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~54 .lut_mask = 16'hFDFF; -defparam \z80_|execute_|ctl_inc_cy~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~41 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~41_combout = (!\z80_|execute_|ctl_mRead~17_combout & (!\z80_|pla_decode_|Equal34~0_combout & ((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~17_combout ), - .datab(\z80_|pla_decode_|Equal12~1_combout ), - .datac(\z80_|pla_decode_|Equal25~0_combout ), - .datad(\z80_|pla_decode_|Equal34~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~41 .lut_mask = 16'h0045; -defparam \z80_|execute_|ctl_inc_cy~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~58 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~58_combout = (\z80_|execute_|ctl_mRead~4_combout ) # ((\z80_|execute_|ctl_mWrite~6_combout ) # (!\z80_|execute_|ctl_inc_cy~41_combout )) - - .dataa(\z80_|execute_|ctl_mRead~4_combout ), - .datab(\z80_|execute_|ctl_mWrite~6_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_inc_cy~41_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~58_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~58 .lut_mask = 16'hEEFF; -defparam \z80_|execute_|ctl_inc_cy~58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~55 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~55_combout = (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|execute_|ctl_alu_op_low~8_combout ) # ((\z80_|execute_|ixy_d~9_combout )))) # (!\z80_|pla_decode_|Equal10~0_combout & (\z80_|execute_|ctl_alu_op_low~8_combout & -// ((\z80_|execute_|ctl_mRead~36_combout )))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|execute_|ctl_mRead~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~55_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~55 .lut_mask = 16'hECA8; -defparam \z80_|execute_|ctl_inc_cy~55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~56 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~56_combout = (((!\z80_|execute_|ctl_reg_sys_we~2_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout )) # (!\z80_|execute_|ctl_reg_sel_pc~17_combout )) # (!\z80_|execute_|fMRead~3_combout ) - - .dataa(\z80_|execute_|fMRead~3_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~17_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), - .datad(\z80_|execute_|ctl_reg_sys_we~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~56_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~56 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_inc_cy~56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~89 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~89_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|pla_decode_|Equal41~2_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~30_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|execute_|ctl_bus_inc_oe~30_combout ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|pla_decode_|Equal41~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~89_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~89 .lut_mask = 16'hA020; -defparam \z80_|execute_|ctl_inc_cy~89 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~57 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~57_combout = ((\z80_|execute_|ctl_inc_cy~55_combout ) # ((\z80_|execute_|ctl_inc_cy~56_combout ) # (\z80_|execute_|ctl_inc_cy~89_combout ))) # (!\z80_|execute_|ctl_reg_sel_pc~7_combout ) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~7_combout ), - .datab(\z80_|execute_|ctl_inc_cy~55_combout ), - .datac(\z80_|execute_|ctl_inc_cy~56_combout ), - .datad(\z80_|execute_|ctl_inc_cy~89_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~57_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~57 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_inc_cy~57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~59 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~59_combout = (\z80_|execute_|ctl_inc_cy~57_combout ) # ((\z80_|execute_|ctl_alu_op_low~8_combout & ((\z80_|execute_|ctl_inc_cy~58_combout ) # (!\z80_|execute_|fMRead~5_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datab(\z80_|execute_|ctl_inc_cy~58_combout ), - .datac(\z80_|execute_|fMRead~5_combout ), - .datad(\z80_|execute_|ctl_inc_cy~57_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~59_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~59 .lut_mask = 16'hFF8A; -defparam \z80_|execute_|ctl_inc_cy~59 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~60 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~60_combout = (\z80_|execute_|pc_inc_hold~38_combout & (\z80_|execute_|pc_inc_hold~35_combout & (\z80_|execute_|ctl_inc_cy~54_combout ))) # (!\z80_|execute_|pc_inc_hold~38_combout & (((\z80_|execute_|ctl_inc_cy~54_combout ) # -// (\z80_|execute_|ctl_inc_cy~59_combout )))) - - .dataa(\z80_|execute_|pc_inc_hold~38_combout ), - .datab(\z80_|execute_|pc_inc_hold~35_combout ), - .datac(\z80_|execute_|ctl_inc_cy~54_combout ), - .datad(\z80_|execute_|ctl_inc_cy~59_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~60_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~60 .lut_mask = 16'hD5D0; -defparam \z80_|execute_|ctl_inc_cy~60 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~47 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~47_combout = (\z80_|execute_|ctl_state_alu~14_combout & (!\z80_|execute_|pc_inc_hold~36_combout & (\z80_|execute_|ctl_alu_op_low~8_combout & !\z80_|execute_|pc_inc_hold~50_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~14_combout ), - .datab(\z80_|execute_|pc_inc_hold~36_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datad(\z80_|execute_|pc_inc_hold~50_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~47 .lut_mask = 16'h0020; -defparam \z80_|execute_|ctl_inc_cy~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~88 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~88_combout = (\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ) # ((\z80_|pla_decode_|Equal13~2_combout & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ))) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~88_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~88 .lut_mask = 16'hECCC; -defparam \z80_|execute_|ctl_inc_cy~88 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~48 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~48_combout = (\z80_|execute_|ctl_inc_cy~47_combout ) # ((\z80_|execute_|ctl_inc_cy~88_combout & ((\z80_|execute_|pc_inc_hold~39_combout ) # (!\z80_|execute_|pc_inc_hold~38_combout )))) - - .dataa(\z80_|execute_|pc_inc_hold~39_combout ), - .datab(\z80_|execute_|ctl_inc_cy~47_combout ), - .datac(\z80_|execute_|ctl_inc_cy~88_combout ), - .datad(\z80_|execute_|pc_inc_hold~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~48 .lut_mask = 16'hECFC; -defparam \z80_|execute_|ctl_inc_cy~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N18 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~40 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~40_combout = (\z80_|execute_|pc_inc_hold~30_combout & !\z80_|execute_|pc_inc_hold~34_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|pc_inc_hold~30_combout ), - .datac(\z80_|execute_|pc_inc_hold~34_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~40 .lut_mask = 16'h0C0C; -defparam \z80_|execute_|pc_inc_hold~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~61 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~61_combout = (!\z80_|execute_|pc_inc_hold~36_combout & (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|execute_|ixy_d~9_combout ) # (\z80_|execute_|ctl_alu_op_low~8_combout )))) - - .dataa(\z80_|execute_|ixy_d~9_combout ), - .datab(\z80_|execute_|pc_inc_hold~36_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datad(\z80_|pla_decode_|Equal10~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~61_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~61 .lut_mask = 16'h3200; -defparam \z80_|execute_|ctl_inc_cy~61 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~62 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~62_combout = (\z80_|execute_|ctl_inc_cy~61_combout ) # ((!\z80_|execute_|ctl_inc_cy~42_combout & ((\z80_|execute_|pc_inc_hold~40_combout ) # (!\z80_|execute_|pc_inc_hold~38_combout )))) - - .dataa(\z80_|execute_|pc_inc_hold~38_combout ), - .datab(\z80_|execute_|pc_inc_hold~40_combout ), - .datac(\z80_|execute_|ctl_inc_cy~61_combout ), - .datad(\z80_|execute_|ctl_inc_cy~42_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~62_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~62 .lut_mask = 16'hF0FD; -defparam \z80_|execute_|ctl_inc_cy~62 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~70 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~70_combout = (\z80_|execute_|ctl_inc_cy~69_combout ) # ((\z80_|execute_|ctl_inc_cy~60_combout ) # ((\z80_|execute_|ctl_inc_cy~48_combout ) # (\z80_|execute_|ctl_inc_cy~62_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~69_combout ), - .datab(\z80_|execute_|ctl_inc_cy~60_combout ), - .datac(\z80_|execute_|ctl_inc_cy~48_combout ), - .datad(\z80_|execute_|ctl_inc_cy~62_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~70_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~70 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_inc_cy~70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~85 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~85_combout = (\z80_|execute_|ctl_inc_cy~73_combout ) # ((\z80_|execute_|ctl_inc_cy~46_combout ) # ((\z80_|execute_|ctl_inc_cy~84_combout ) # (\z80_|execute_|ctl_inc_cy~70_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~73_combout ), - .datab(\z80_|execute_|ctl_inc_cy~46_combout ), - .datac(\z80_|execute_|ctl_inc_cy~84_combout ), - .datad(\z80_|execute_|ctl_inc_cy~70_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~85_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~85 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_inc_cy~85 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N28 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout = \z80_|address_latch_|Q [0] $ (\z80_|execute_|ctl_inc_cy~85_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|address_latch_|Q [0]), - .datad(\z80_|execute_|ctl_inc_cy~85_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out .lut_mask = 16'h0FF0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N8 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~3 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[0]~3_combout = ((\z80_|reg_file_|db_lo_as[0]~1_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[0]~1_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[0]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[0]~3 .lut_mask = 16'hAF2F; -defparam \z80_|reg_file_|db_lo_as[0]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N28 -cycloneive_lcell_comb \z80_|address_latch_|abusz[0] ( -// Equation(s): -// \z80_|address_latch_|abusz [0] = (\z80_|reg_file_|db_lo_as[0]~3_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|reg_file_|db_lo_as[0]~3_combout ), - .datad(\z80_|resets_|clrpc~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [0]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[0] .lut_mask = 16'h00F0; -defparam \z80_|address_latch_|abusz[0] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N22 -cycloneive_lcell_comb \z80_|address_latch_|Q[0]~feeder ( -// Equation(s): -// \z80_|address_latch_|Q[0]~feeder_combout = \z80_|address_latch_|abusz [0] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [0]), - .cin(gnd), - .combout(\z80_|address_latch_|Q[0]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|Q[0]~feeder .lut_mask = 16'hFF00; -defparam \z80_|address_latch_|Q[0]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N23 -dffeas \z80_|address_latch_|Q[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|Q[0]~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[0] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N4 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout = \z80_|address_latch_|Q [0] $ (((\z80_|execute_|ctl_inc_dec~9_combout ) # ((\z80_|execute_|ctl_inc_dec~7_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout )))) - - .dataa(\z80_|execute_|ctl_inc_dec~9_combout ), - .datab(\z80_|execute_|ctl_inc_dec~6_combout ), - .datac(\z80_|address_latch_|Q [0]), - .datad(\z80_|execute_|ctl_inc_dec~7_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 .lut_mask = 16'h0F4B; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y17_N5 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[1]~6_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X31_Y13_N23 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[1]~6_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N22 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~4 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[1]~4_combout = (\z80_|reg_file_|gdfx_temp0[1]~32_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) # (!\z80_|reg_file_|gdfx_temp0[1]~32_combout & -// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [1]), - .datad(\z80_|execute_|ctl_sw_4d~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[1]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[1]~4 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_lo_as[1]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N26 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~5 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[1]~5_combout = (\z80_|reg_file_|db_lo_as[1]~4_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_lo|latch [1]), - .datad(\z80_|reg_file_|db_lo_as[1]~4_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[1]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[1]~5 .lut_mask = 16'hF300; -defparam \z80_|reg_file_|db_lo_as[1]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N24 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout = \z80_|address_latch_|Q [1] $ (((\z80_|execute_|ctl_inc_cy~85_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ))) - - .dataa(\z80_|address_latch_|Q [1]), - .datab(\z80_|execute_|ctl_inc_cy~85_combout ), - .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out .lut_mask = 16'h6A6A; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N4 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~6 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[1]~6_combout = ((\z80_|reg_file_|db_lo_as[1]~5_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[1]~5_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[1]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[1]~6 .lut_mask = 16'hAF2F; -defparam \z80_|reg_file_|db_lo_as[1]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N14 -cycloneive_lcell_comb \z80_|address_latch_|abusz[1] ( -// Equation(s): -// \z80_|address_latch_|abusz [1] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[1]~6_combout ) - - .dataa(gnd), - .datab(\z80_|resets_|clrpc~0_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|db_lo_as[1]~6_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [1]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[1] .lut_mask = 16'h3300; -defparam \z80_|address_latch_|abusz[1] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y17_N19 -dffeas \z80_|address_latch_|Q[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|address_latch_|abusz [1]), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[1] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N6 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout = \z80_|address_latch_|Q [1] $ ((((\z80_|execute_|ctl_inc_dec~10_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )) # (!\z80_|execute_|ctl_inc_dec~5_combout ))) - - .dataa(\z80_|execute_|ctl_inc_dec~5_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .datac(\z80_|address_latch_|Q [1]), - .datad(\z80_|execute_|ctl_inc_dec~10_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4 .lut_mask = 16'h0F87; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N22 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout = \z80_|address_latch_|Q [2] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout & (\z80_|execute_|ctl_inc_cy~85_combout & -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout )))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), - .datab(\z80_|execute_|ctl_inc_cy~85_combout ), - .datac(\z80_|address_latch_|Q [2]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out .lut_mask = 16'h78F0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N16 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~9 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[2]~9_combout = ((\z80_|reg_file_|db_lo_as[2]~8_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|reg_file_|db_lo_as[2]~8_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[2]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[2]~9 .lut_mask = 16'hF575; -defparam \z80_|reg_file_|db_lo_as[2]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N12 -cycloneive_lcell_comb \z80_|address_latch_|abusz[2] ( -// Equation(s): -// \z80_|address_latch_|abusz [2] = (\z80_|reg_file_|db_lo_as[2]~9_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[2]~9_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|resets_|clrpc~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [2]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[2] .lut_mask = 16'h00AA; -defparam \z80_|address_latch_|abusz[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N14 -cycloneive_lcell_comb \z80_|address_latch_|Q[2]~feeder ( -// Equation(s): -// \z80_|address_latch_|Q[2]~feeder_combout = \z80_|address_latch_|abusz [2] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [2]), - .cin(gnd), - .combout(\z80_|address_latch_|Q[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|Q[2]~feeder .lut_mask = 16'hFF00; -defparam \z80_|address_latch_|Q[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y17_N15 -dffeas \z80_|address_latch_|Q[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|Q[2]~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[2] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N2 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout = \z80_|address_latch_|Q [2] $ (((\z80_|execute_|ctl_inc_dec~10_combout ) # ((!\z80_|execute_|ctl_inc_dec~5_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) - - .dataa(\z80_|execute_|ctl_inc_dec~10_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .datac(\z80_|execute_|ctl_inc_dec~5_combout ), - .datad(\z80_|address_latch_|Q [2]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42 .lut_mask = 16'h40BF; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~86 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~86_combout = (\z80_|execute_|ctl_inc_cy~73_combout ) # ((\z80_|execute_|ctl_inc_cy~79_combout ) # ((\z80_|execute_|ctl_inc_cy~80_combout ) # (\z80_|execute_|ctl_inc_cy~83_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~73_combout ), - .datab(\z80_|execute_|ctl_inc_cy~79_combout ), - .datac(\z80_|execute_|ctl_inc_cy~80_combout ), - .datad(\z80_|execute_|ctl_inc_cy~83_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~86_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~86 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_inc_cy~86 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N0 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout & ((\z80_|execute_|ctl_inc_cy~46_combout ) # ((\z80_|execute_|ctl_inc_cy~86_combout ) # -// (\z80_|execute_|ctl_inc_cy~70_combout )))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), - .datab(\z80_|execute_|ctl_inc_cy~46_combout ), - .datac(\z80_|execute_|ctl_inc_cy~86_combout ), - .datad(\z80_|execute_|ctl_inc_cy~70_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'hAAA8; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~11 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~11_combout = (\z80_|execute_|ctl_inc_dec~9_combout ) # (((!\z80_|execute_|ctl_bus_inc_oe~33_combout ) # (!\z80_|execute_|ctl_inc_dec~5_combout )) # (!\z80_|execute_|ctl_inc_dec~6_combout )) - - .dataa(\z80_|execute_|ctl_inc_dec~9_combout ), - .datab(\z80_|execute_|ctl_inc_dec~6_combout ), - .datac(\z80_|execute_|ctl_inc_dec~5_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~11 .lut_mask = 16'hBFFF; -defparam \z80_|execute_|ctl_inc_dec~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N0 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout = (\z80_|execute_|ctl_inc_cy~85_combout & ((\z80_|address_latch_|Q [1] & (!\z80_|execute_|ctl_inc_dec~11_combout & \z80_|address_latch_|Q [0])) # (!\z80_|address_latch_|Q -// [1] & (\z80_|execute_|ctl_inc_dec~11_combout & !\z80_|address_latch_|Q [0])))) - - .dataa(\z80_|address_latch_|Q [1]), - .datab(\z80_|execute_|ctl_inc_dec~11_combout ), - .datac(\z80_|address_latch_|Q [0]), - .datad(\z80_|execute_|ctl_inc_cy~85_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0 .lut_mask = 16'h2400; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N10 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout = \z80_|address_latch_|Q [3] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout -// ))) - - .dataa(gnd), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ), - .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ), - .datad(\z80_|address_latch_|Q [3]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out .lut_mask = 16'h3FC0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N15 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y10_N21 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~45 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~45_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [3]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [3]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~45 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[3]~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N26 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp0[3]~52_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y11_N27 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y11_N11 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~48 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~48_combout = (\z80_|reg_file_|b2v_latch_ix_lo|latch [3] & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # (!\z80_|reg_file_|b2v_latch_ix_lo|latch [3] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_ix_lo|latch [3]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc_lo|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~48 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[3]~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y10_N5 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y10_N11 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~49 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~49_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [3]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_iy_lo|latch [3]), - .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~49 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[3]~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N12 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp0[3]~52_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y11_N13 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y11_N27 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~41 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~41_combout = ((!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ), - .datac(\z80_|execute_|nextM~2_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~41 .lut_mask = 16'h3F3B; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~42 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~42_combout = ((\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mRead~5_combout ) # (!\z80_|execute_|ctl_al_we~14_combout )))) # (!\z80_|execute_|setM1~29_combout ) - - .dataa(\z80_|execute_|ctl_mRead~5_combout ), - .datab(\z80_|execute_|setM1~29_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_al_we~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~42 .lut_mask = 16'hB3F3; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~43 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~43_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ) # ((!\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout & !\z80_|execute_|rsel3~combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ), - .datab(\z80_|execute_|rsel3~combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~43 .lut_mask = 16'hFFF1; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~44 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~44_combout = ((\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ) # ((!\z80_|execute_|rsel0~combout & \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ), - .datab(\z80_|execute_|rsel0~combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~44 .lut_mask = 16'hF7F5; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~45 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~45_combout = ((\z80_|execute_|ctl_state_alu~5_combout & ((!\z80_|execute_|setM1~46_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout )))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), - .datab(\z80_|execute_|ctl_state_alu~5_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), - .datad(\z80_|execute_|setM1~46_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~45 .lut_mask = 16'h5DDD; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~46 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout = ((\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ) # (!\z80_|execute_|ctl_reg_gp_we~2_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~46 .lut_mask = 16'hFDFF; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N14 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_48 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_48~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_de~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_de~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_48 .lut_mask = 16'h0C00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N20 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_44 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_44~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_de2~4_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_de2~4_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_44 .lut_mask = 16'h0C00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N4 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_45 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_45~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_de2~4_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_de2~4_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_45 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y13_N15 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N6 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_49 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_49~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_de~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_de~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_49 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y13_N1 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~40 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~40_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [3]), - .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [3]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~40 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[3]~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N12 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_52 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_52~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl2~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_52 .lut_mask = 16'h0C00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N18 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_57 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_57~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_57 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N9 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N16 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_53 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_53~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl2~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_53 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N19 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N30 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_56 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_56~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_56 .lut_mask = 16'h0C00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~41 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~41_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [3]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [3]), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~41 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp1[3]~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N26 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_33 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_33~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_af~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_af~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_33 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y14_N5 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N4 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[3]~18 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[3]~18_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [3]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [3]), - .datad(\z80_|reg_control_|reg_sel_af~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[3]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[3]~18 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[3]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~11 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~11_combout = (((\z80_|pla_decode_|Equal9~1_combout & \z80_|execute_|ixy_d~6_combout )) # (!\z80_|execute_|ctl_reg_in_hi~5_combout )) # (!\z80_|execute_|ctl_reg_in_hi~6_combout ) - - .dataa(\z80_|pla_decode_|Equal9~1_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~6_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~11 .lut_mask = 16'hB3FF; -defparam \z80_|execute_|ctl_reg_in_hi~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~12 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~12_combout = (\z80_|execute_|ctl_reg_in_hi~11_combout ) # (((!\z80_|execute_|ctl_reg_in_hi~4_combout ) # (!\z80_|execute_|ctl_reg_in_hi~3_combout )) # (!\z80_|execute_|ctl_reg_in_hi~10_combout )) - - .dataa(\z80_|execute_|ctl_reg_in_hi~11_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~10_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~3_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~12 .lut_mask = 16'hBFFF; -defparam \z80_|execute_|ctl_reg_in_hi~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N12 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_29 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_29~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_af2~0_combout & \z80_|execute_|ctl_reg_gp_we~6_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datab(gnd), - .datac(\z80_|reg_control_|reg_sel_af2~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_29 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y11_N19 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N2 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_28 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_28~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_af2~0_combout & !\z80_|execute_|ctl_reg_gp_we~6_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datab(gnd), - .datac(\z80_|reg_control_|reg_sel_af2~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_28 .lut_mask = 16'h00A0; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~44 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~44_combout = (\z80_|alu_|db[3]~11_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[3]~11_combout & (!\z80_|execute_|ctl_reg_in_hi~12_combout & -// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|alu_|db[3]~11_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~44 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[3]~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N8 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp1[3]~48_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N12 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_69 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_69~combout = (\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & \z80_|reg_control_|reg_sel_iy~2_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datad(\z80_|reg_control_|reg_sel_iy~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y12_N9 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N24 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout = (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(gnd), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 .lut_mask = 16'h4444; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N2 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|decode_state_|DFFE_inst4~q & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|decode_state_|DFFE_inst4~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 .lut_mask = 16'h4000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N8 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & \z80_|execute_|ctl_reg_gp_we~6_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 .lut_mask = 16'hF000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N4 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout = (\z80_|decode_state_|DFFE_inst4~q & (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 .lut_mask = 16'h0080; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y12_N29 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N14 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_68 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_68~combout = (!\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & \z80_|reg_control_|reg_sel_iy~2_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datad(\z80_|reg_control_|reg_sel_iy~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68 .lut_mask = 16'h3000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~43 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~43_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [3] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [3] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [3]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~43 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[3]~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N20 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N22 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout = (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y15_N23 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~31 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~31_combout = (!\z80_|ir_|opcode [3] & ((\z80_|execute_|ctl_alu_op_low~14_combout ) # ((\z80_|pla_decode_|Equal48~0_combout & \z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal48~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~31 .lut_mask = 16'h5450; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~30 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~30_combout = ((\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ) # ((\z80_|pla_decode_|Equal35~0_combout & \z80_|execute_|ixy_d~6_combout ))) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ) - - .dataa(\z80_|pla_decode_|Equal35~0_combout ), - .datab(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~30 .lut_mask = 16'hFFB3; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~32 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~32_combout = (((\z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ) # (\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout )) # (!\z80_|execute_|ctl_reg_out_hi~4_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), - .datab(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~32 .lut_mask = 16'hFFF7; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~33 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~33_combout = ((\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ) # ((!\z80_|execute_|ctl_reg_in_hi~5_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ))) # (!\z80_|execute_|ctl_reg_sel_wz~12_combout ) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~12_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~33 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N30 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_hi~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_hi~0_combout = ((\z80_|execute_|ixy_d~6_combout & ((\z80_|pla_decode_|Equal19~0_combout ) # (\z80_|execute_|ctl_reg_sys_we_lo~3_combout )))) # (!\z80_|execute_|ctl_reg_sel_wz~13_combout ) - - .dataa(\z80_|pla_decode_|Equal19~0_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~13_combout ), - .datac(\z80_|execute_|ctl_reg_sys_we_lo~3_combout ), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_hi~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_hi~0 .lut_mask = 16'hFB33; -defparam \z80_|reg_control_|reg_sys_we_hi~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N14 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_hi ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_hi~combout = ((\z80_|reg_control_|reg_sys_we_hi~0_combout ) # (\z80_|execute_|ctl_reg_sys_we~3_combout )) # (!\z80_|execute_|ctl_reg_in_hi~4_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_in_hi~4_combout ), - .datac(\z80_|reg_control_|reg_sys_we_hi~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_we~3_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_hi~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_hi .lut_mask = 16'hFFF3; -defparam \z80_|reg_control_|reg_sys_we_hi .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N4 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_81 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_81~combout = (\z80_|execute_|ctl_reg_sel_wz~17_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & \z80_|reg_control_|reg_sys_we_hi~combout )) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~17_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_81 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y12_N27 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N22 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_80 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_80~combout = (\z80_|execute_|ctl_reg_sel_wz~17_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & !\z80_|reg_control_|reg_sys_we_hi~combout )) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~17_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_80 .lut_mask = 16'h00A0; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~45 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~45_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [3]), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~45 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[3]~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N6 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & (!\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), - .datab(\z80_|reg_control_|bank_exx~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 .lut_mask = 16'h0002; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y13_N1 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N10 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|reg_control_|bank_exx~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 .lut_mask = 16'h0400; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N16 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & (\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), - .datab(\z80_|reg_control_|bank_exx~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 .lut_mask = 16'h0008; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y13_N3 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N4 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|reg_control_|bank_exx~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 .lut_mask = 16'h0100; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~42 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~42_combout = (\z80_|reg_file_|b2v_latch_bc_hi|latch [3] & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_hi|latch [3] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc_hi|latch [3]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~42 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[3]~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~46 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~46_combout = (\z80_|reg_file_|gdfx_temp1[3]~44_combout & (\z80_|reg_file_|gdfx_temp1[3]~43_combout & (\z80_|reg_file_|gdfx_temp1[3]~45_combout & \z80_|reg_file_|gdfx_temp1[3]~42_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[3]~44_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[3]~43_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[3]~45_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[3]~42_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~46 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[3]~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~47 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~47_combout = (\z80_|reg_file_|gdfx_temp1[3]~40_combout & (\z80_|reg_file_|gdfx_temp1[3]~41_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[3]~18_combout & \z80_|reg_file_|gdfx_temp1[3]~46_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[3]~40_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[3]~41_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|db[3]~18_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[3]~46_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~47 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[3]~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~17 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~17_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ) # ((\z80_|reg_control_|reg_sel_af~0_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) - - .dataa(\z80_|reg_control_|reg_sel_af~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~17 .lut_mask = 16'hFFF8; -defparam \z80_|reg_file_|gdfx_temp1[0]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~18 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~18_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~18 .lut_mask = 16'hFEFE; -defparam \z80_|reg_file_|gdfx_temp1[0]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~19 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~19_combout = (\z80_|reg_file_|gdfx_temp1[0]~17_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ) # ((\z80_|reg_file_|gdfx_temp1[0]~18_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~17_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[0]~18_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~19 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp1[0]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~16 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~16_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~16 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp1[0]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~20 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~20_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout ) # ((\z80_|reg_file_|gdfx_temp1[0]~19_combout ) # ((\z80_|execute_|ctl_sw_4u~6_combout ) # (\z80_|reg_file_|gdfx_temp1[0]~16_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~19_combout ), - .datac(\z80_|execute_|ctl_sw_4u~6_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[0]~16_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~20 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp1[0]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N10 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_73 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_73~combout = (\z80_|reg_control_|reg_sel_pc~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & \z80_|reg_control_|reg_sys_we_hi~combout )) - - .dataa(\z80_|reg_control_|reg_sel_pc~combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_73 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N13 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[1]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y13_N19 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y13_N25 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~8 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~8_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [1]), - .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [1]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~8 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[1]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y14_N3 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N2 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[1]~15 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[1]~15_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [1]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [1]), - .datad(\z80_|reg_control_|reg_sel_af~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[1]~15 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y15_N9 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y12_N11 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~13 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~13_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [1]), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~13 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[1]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y11_N21 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~12 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~12_combout = (\z80_|alu_|db[1]~13_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[1]~13_combout & (!\z80_|execute_|ctl_reg_in_hi~12_combout & -// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|alu_|db[1]~13_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~12 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[1]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y13_N5 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y13_N31 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~10 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~10_combout = (\z80_|reg_file_|b2v_latch_bc_hi|latch [1] & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_hi|latch [1] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc_hi|latch [1]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~10 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[1]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y12_N21 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N28 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder_combout = \z80_|reg_file_|gdfx_temp1[1]~21_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y12_N29 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~11 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~11_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [1]), - .datad(\z80_|reg_file_|b2v_latch_iy_hi|latch [1]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~11 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[1]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~14 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~14_combout = (\z80_|reg_file_|gdfx_temp1[1]~13_combout & (\z80_|reg_file_|gdfx_temp1[1]~12_combout & (\z80_|reg_file_|gdfx_temp1[1]~10_combout & \z80_|reg_file_|gdfx_temp1[1]~11_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[1]~13_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[1]~12_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[1]~10_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[1]~11_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~14 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[1]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N15 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y14_N17 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~9 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~9_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [1]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [1]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~9 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[1]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~15 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~15_combout = (\z80_|reg_file_|gdfx_temp1[1]~8_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[1]~15_combout & (\z80_|reg_file_|gdfx_temp1[1]~14_combout & \z80_|reg_file_|gdfx_temp1[1]~9_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[1]~8_combout ), - .datab(\z80_|reg_file_|b2v_latch_af_hi|db[1]~15_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[1]~14_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[1]~9_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~15 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~21 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~21_combout = ((\z80_|reg_file_|gdfx_temp1[1]~15_combout & ((\z80_|reg_file_|db_hi_as[1]~3_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[1]~15_combout ), - .datac(\z80_|reg_file_|db_hi_as[1]~3_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~21 .lut_mask = 16'hD5DD; -defparam \z80_|reg_file_|gdfx_temp1[1]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N28 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_60 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_60~combout = (!\z80_|reg_control_|reg_sys_we_hi~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & \z80_|execute_|ctl_reg_sel_ir~1_combout )) - - .dataa(\z80_|reg_control_|reg_sys_we_hi~combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datad(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_60 .lut_mask = 16'h5000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_60 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N16 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_61 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_61~combout = (\z80_|reg_control_|reg_sys_we_hi~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & \z80_|execute_|ctl_reg_sel_ir~1_combout )) - - .dataa(\z80_|reg_control_|reg_sys_we_hi~combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datad(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_61 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_61 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y15_N17 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[1]~3_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N6 -cycloneive_lcell_comb \z80_|reg_control_|reg_sw_4d_hi~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sw_4d_hi~0_combout = (\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_control_|reg_sys_we_lo~combout ) # ((!\z80_|execute_|ctl_reg_sel_ir~1_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout )))) - - .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), - .datab(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datad(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sw_4d_hi~0 .lut_mask = 16'h8AAA; -defparam \z80_|reg_control_|reg_sw_4d_hi~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N16 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~0 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[1]~0_combout = (\z80_|reg_file_|gdfx_temp1[1]~21_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) # (!\z80_|reg_file_|gdfx_temp1[1]~21_combout & -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [1]), - .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[1]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[1]~0 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_hi_as[1]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N12 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_72 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_72~combout = (\z80_|reg_control_|reg_sel_pc~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & !\z80_|reg_control_|reg_sys_we_hi~combout )) - - .dataa(\z80_|reg_control_|reg_sel_pc~combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_72 .lut_mask = 16'h00A0; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_72 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N10 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~1 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[1]~1_combout = (\z80_|reg_file_|db_hi_as[1]~0_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|b2v_latch_pc_hi|latch [1]), - .datab(gnd), - .datac(\z80_|reg_file_|db_hi_as[1]~0_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[1]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[1]~1 .lut_mask = 16'hA0F0; -defparam \z80_|reg_file_|db_hi_as[1]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N30 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~2 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[0]~2_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ) # ((\z80_|execute_|ctl_bus_inc_oe~41_combout ) # (\z80_|reg_control_|reg_sw_4d_hi~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[0]~2 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|db_hi_as[0]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N2 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout = \z80_|address_latch_|Q [8] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout & (\z80_|address_latch_|Q [7] $ (\z80_|execute_|ctl_inc_dec~11_combout ))))) - - .dataa(\z80_|address_latch_|Q [7]), - .datab(\z80_|address_latch_|Q [8]), - .datac(\z80_|execute_|ctl_inc_dec~11_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out .lut_mask = 16'h96CC; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y15_N27 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[0]~6_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y14_N3 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y14_N1 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~23 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~23_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [0]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [0]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~23 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[0]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y13_N7 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y13_N29 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~22 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~22_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [0]), - .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [0]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~22 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[0]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y13_N21 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y13_N7 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~24 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~24_combout = (\z80_|reg_file_|b2v_latch_bc2_hi|latch [0] & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # (!\z80_|reg_file_|b2v_latch_bc2_hi|latch [0] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc_hi|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~24 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[0]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y11_N15 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~26 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~26_combout = (\z80_|alu_|db[0]~19_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[0]~19_combout & (!\z80_|execute_|ctl_reg_in_hi~12_combout & -// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|alu_|db[0]~19_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~26 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[0]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N26 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder_combout = \z80_|reg_file_|gdfx_temp1[0]~30_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y12_N27 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y12_N5 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~25 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~25_combout = (\z80_|reg_file_|b2v_latch_ix_hi|latch [0] & (((\z80_|reg_file_|b2v_latch_iy_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ))) # (!\z80_|reg_file_|b2v_latch_ix_hi|latch [0] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & ((\z80_|reg_file_|b2v_latch_iy_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_ix_hi|latch [0]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datac(\z80_|reg_file_|b2v_latch_iy_hi|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~25 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[0]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y14_N13 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X26_Y14_N7 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~27 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~27_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (\z80_|reg_file_|b2v_latch_wz_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (((\z80_|reg_file_|b2v_latch_sp_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_sp_hi|latch [0]), - .datad(\z80_|reg_file_|b2v_latch_wz_hi|latch [0]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~27 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[0]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~28 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~28_combout = (\z80_|reg_file_|gdfx_temp1[0]~24_combout & (\z80_|reg_file_|gdfx_temp1[0]~26_combout & (\z80_|reg_file_|gdfx_temp1[0]~25_combout & \z80_|reg_file_|gdfx_temp1[0]~27_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~24_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~26_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[0]~25_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[0]~27_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~28 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[0]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y14_N29 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N28 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[0]~16 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[0]~16_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [0]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [0]), - .datad(\z80_|reg_control_|reg_sel_af~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[0]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[0]~16 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[0]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~29 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~29_combout = (\z80_|reg_file_|gdfx_temp1[0]~23_combout & (\z80_|reg_file_|gdfx_temp1[0]~22_combout & (\z80_|reg_file_|gdfx_temp1[0]~28_combout & \z80_|reg_file_|b2v_latch_af_hi|db[0]~16_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~23_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~22_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[0]~28_combout ), - .datad(\z80_|reg_file_|b2v_latch_af_hi|db[0]~16_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~29 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[0]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~30 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~30_combout = ((\z80_|reg_file_|gdfx_temp1[0]~29_combout & ((\z80_|reg_file_|db_hi_as[0]~6_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|db_hi_as[0]~6_combout ), - .datab(\z80_|execute_|ctl_sw_4u~6_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[0]~29_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~30 .lut_mask = 16'hBF0F; -defparam \z80_|reg_file_|gdfx_temp1[0]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y15_N21 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[0]~6_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N20 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~4 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[0]~4_combout = (\z80_|reg_control_|reg_sw_4d_hi~0_combout & (\z80_|reg_file_|gdfx_temp1[0]~30_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) - - .dataa(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[0]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[0]~4 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|db_hi_as[0]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N24 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~5 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[0]~5_combout = (\z80_|reg_file_|db_hi_as[0]~4_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datab(gnd), - .datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [0]), - .datad(\z80_|reg_file_|db_hi_as[0]~4_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[0]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[0]~5 .lut_mask = 16'hF500; -defparam \z80_|reg_file_|db_hi_as[0]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N26 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~6 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[0]~6_combout = ((\z80_|reg_file_|db_hi_as[0]~5_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), - .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datad(\z80_|reg_file_|db_hi_as[0]~5_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[0]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[0]~6 .lut_mask = 16'hDF0F; -defparam \z80_|reg_file_|db_hi_as[0]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N8 -cycloneive_lcell_comb \z80_|address_latch_|abusz[8] ( -// Equation(s): -// \z80_|address_latch_|abusz [8] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[0]~6_combout ) - - .dataa(\z80_|resets_|clrpc~0_combout ), - .datab(gnd), - .datac(\z80_|reg_file_|db_hi_as[0]~6_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [8]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[8] .lut_mask = 16'h5050; -defparam \z80_|address_latch_|abusz[8] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y16_N9 -dffeas \z80_|address_latch_|Q[8] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [8]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [8]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[8] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N18 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout & ((\z80_|address_latch_|Q [7] & (\z80_|address_latch_|Q [8] & !\z80_|execute_|ctl_inc_dec~11_combout -// )) # (!\z80_|address_latch_|Q [7] & (!\z80_|address_latch_|Q [8] & \z80_|execute_|ctl_inc_dec~11_combout )))) - - .dataa(\z80_|address_latch_|Q [7]), - .datab(\z80_|address_latch_|Q [8]), - .datac(\z80_|execute_|ctl_inc_dec~11_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 .lut_mask = 16'h1800; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N20 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout = \z80_|address_latch_|Q [9] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|address_latch_|Q [9]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out .lut_mask = 16'h0FF0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N12 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~3 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[1]~3_combout = ((\z80_|reg_file_|db_hi_as[1]~1_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_hi_as[1]~1_combout ), - .datab(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[1]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[1]~3 .lut_mask = 16'hBB3B; -defparam \z80_|reg_file_|db_hi_as[1]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N24 -cycloneive_lcell_comb \z80_|address_latch_|abusz[9] ( -// Equation(s): -// \z80_|address_latch_|abusz [9] = (\z80_|reg_file_|db_hi_as[1]~3_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(gnd), - .datab(\z80_|reg_file_|db_hi_as[1]~3_combout ), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [9]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[9] .lut_mask = 16'h0C0C; -defparam \z80_|address_latch_|abusz[9] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N4 -cycloneive_lcell_comb \z80_|address_latch_|Q[9]~feeder ( -// Equation(s): -// \z80_|address_latch_|Q[9]~feeder_combout = \z80_|address_latch_|abusz [9] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [9]), - .cin(gnd), - .combout(\z80_|address_latch_|Q[9]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|Q[9]~feeder .lut_mask = 16'hFF00; -defparam \z80_|address_latch_|Q[9]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N5 -dffeas \z80_|address_latch_|Q[9] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|Q[9]~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [9]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[9] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[9] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N30 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout = \z80_|address_latch_|Q [10] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout & (\z80_|address_latch_|Q [9] $ -// (\z80_|execute_|ctl_inc_dec~11_combout ))))) - - .dataa(\z80_|address_latch_|Q [10]), - .datab(\z80_|address_latch_|Q [9]), - .datac(\z80_|execute_|ctl_inc_dec~11_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out .lut_mask = 16'h96AA; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N7 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y14_N13 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~32 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~32_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [2]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [2]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~32 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[2]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y11_N25 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~35 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~35_combout = (\z80_|alu_|db[2]~15_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[2]~15_combout & (!\z80_|execute_|ctl_reg_in_hi~12_combout & -// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|alu_|db[2]~15_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~35 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[2]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y12_N19 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N18 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp1[2]~39_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y12_N19 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~34 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~34_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [2]), - .datad(\z80_|reg_file_|b2v_latch_iy_hi|latch [2]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~34 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[2]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N16 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp1[2]~39_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y13_N17 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y13_N15 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~33 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~33_combout = (\z80_|reg_file_|b2v_latch_bc_hi|latch [2] & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_hi|latch [2] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc_hi|latch [2]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~33 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[2]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y15_N21 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y12_N1 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~36 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~36_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [2]), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~36 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[2]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~37 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~37_combout = (\z80_|reg_file_|gdfx_temp1[2]~35_combout & (\z80_|reg_file_|gdfx_temp1[2]~34_combout & (\z80_|reg_file_|gdfx_temp1[2]~33_combout & \z80_|reg_file_|gdfx_temp1[2]~36_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[2]~35_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[2]~34_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[2]~33_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[2]~36_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~37 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[2]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y13_N5 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y13_N31 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~31 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~31_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datab(\z80_|reg_file_|b2v_latch_de_hi|latch [2]), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~31 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[2]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y14_N23 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N22 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[2]~17 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[2]~17_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [2]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [2]), - .datad(\z80_|reg_control_|reg_sel_af~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[2]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[2]~17 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[2]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y12_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~38 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~38_combout = (\z80_|reg_file_|gdfx_temp1[2]~32_combout & (\z80_|reg_file_|gdfx_temp1[2]~37_combout & (\z80_|reg_file_|gdfx_temp1[2]~31_combout & \z80_|reg_file_|b2v_latch_af_hi|db[2]~17_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[2]~32_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[2]~37_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[2]~31_combout ), - .datad(\z80_|reg_file_|b2v_latch_af_hi|db[2]~17_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~38 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[2]~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~39 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~39_combout = ((\z80_|reg_file_|gdfx_temp1[2]~38_combout & ((\z80_|reg_file_|db_hi_as[2]~9_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[2]~38_combout ), - .datab(\z80_|reg_file_|db_hi_as[2]~9_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~39 .lut_mask = 16'h8FAF; -defparam \z80_|reg_file_|gdfx_temp1[2]~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y15_N19 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[2]~9_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N18 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~7 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[2]~7_combout = (\z80_|reg_file_|gdfx_temp1[2]~39_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) # (!\z80_|reg_file_|gdfx_temp1[2]~39_combout & -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [2]), - .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[2]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[2]~7 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_hi_as[2]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y15_N9 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[2]~9_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N2 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~8 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[2]~8_combout = (\z80_|reg_file_|db_hi_as[2]~7_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datab(\z80_|reg_file_|db_hi_as[2]~7_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|b2v_latch_pc_hi|latch [2]), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[2]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[2]~8 .lut_mask = 16'hCC44; -defparam \z80_|reg_file_|db_hi_as[2]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N8 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~9 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[2]~9_combout = ((\z80_|reg_file_|db_hi_as[2]~8_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), - .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datad(\z80_|reg_file_|db_hi_as[2]~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[2]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[2]~9 .lut_mask = 16'hDF0F; -defparam \z80_|reg_file_|db_hi_as[2]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N0 -cycloneive_lcell_comb \z80_|address_latch_|abusz[10] ( -// Equation(s): -// \z80_|address_latch_|abusz [10] = (\z80_|reg_file_|db_hi_as[2]~9_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|reg_file_|db_hi_as[2]~9_combout ), - .datad(\z80_|resets_|clrpc~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [10]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[10] .lut_mask = 16'h00F0; -defparam \z80_|address_latch_|abusz[10] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N26 -cycloneive_lcell_comb \z80_|address_latch_|Q[10]~feeder ( -// Equation(s): -// \z80_|address_latch_|Q[10]~feeder_combout = \z80_|address_latch_|abusz [10] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [10]), - .cin(gnd), - .combout(\z80_|address_latch_|Q[10]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|Q[10]~feeder .lut_mask = 16'hFF00; -defparam \z80_|address_latch_|Q[10]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N27 -dffeas \z80_|address_latch_|Q[10] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|Q[10]~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [10]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[10] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[10] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N10 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout & ((\z80_|address_latch_|Q [10] & (\z80_|address_latch_|Q [9] & -// !\z80_|execute_|ctl_inc_dec~11_combout )) # (!\z80_|address_latch_|Q [10] & (!\z80_|address_latch_|Q [9] & \z80_|execute_|ctl_inc_dec~11_combout )))) - - .dataa(\z80_|address_latch_|Q [10]), - .datab(\z80_|address_latch_|Q [9]), - .datac(\z80_|execute_|ctl_inc_dec~11_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 .lut_mask = 16'h1800; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N14 -cycloneive_lcell_comb \z80_|address_latch_|abusz[11] ( -// Equation(s): -// \z80_|address_latch_|abusz [11] = (\z80_|reg_file_|db_hi_as[3]~12_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(gnd), - .datab(\z80_|reg_file_|db_hi_as[3]~12_combout ), - .datac(gnd), - .datad(\z80_|resets_|clrpc~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [11]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[11] .lut_mask = 16'h00CC; -defparam \z80_|address_latch_|abusz[11] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N15 -dffeas \z80_|address_latch_|Q[11] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [11]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [11]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[11] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[11] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N12 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[11] ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|address [11] = \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout $ (\z80_|address_latch_|Q [11]) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), - .datab(gnd), - .datac(\z80_|address_latch_|Q [11]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[11] .lut_mask = 16'h5A5A; -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[11] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N31 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[3]~12_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y15_N31 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[3]~12_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N30 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~10 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[3]~10_combout = (\z80_|reg_file_|gdfx_temp1[3]~48_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) # (!\z80_|reg_file_|gdfx_temp1[3]~48_combout & -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [3]), - .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[3]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[3]~10 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_hi_as[3]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N0 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~11 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[3]~11_combout = (\z80_|reg_file_|db_hi_as[3]~10_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|b2v_latch_pc_hi|latch [3]), - .datab(gnd), - .datac(\z80_|reg_file_|db_hi_as[3]~10_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[3]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[3]~11 .lut_mask = 16'hA0F0; -defparam \z80_|reg_file_|db_hi_as[3]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N30 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~12 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[3]~12_combout = ((\z80_|reg_file_|db_hi_as[3]~11_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [11]) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datad(\z80_|reg_file_|db_hi_as[3]~11_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[3]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[3]~12 .lut_mask = 16'hBF0F; -defparam \z80_|reg_file_|db_hi_as[3]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~48 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~48_combout = ((\z80_|reg_file_|gdfx_temp1[3]~47_combout & ((\z80_|reg_file_|db_hi_as[3]~12_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[3]~47_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datac(\z80_|reg_file_|db_hi_as[3]~12_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~48 .lut_mask = 16'hB3BB; -defparam \z80_|reg_file_|gdfx_temp1[3]~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N16 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & ((\z80_|alu_|db_low[3]~11_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~43_combout & !\z80_|alu_|db_high[3]~2_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .datab(\z80_|alu_|db_low[3]~11_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datad(\z80_|alu_|db_high[3]~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9 .lut_mask = 16'h888A; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_low ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_low~combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ixy_d~9_combout ) # ((\z80_|execute_|ixy_d~7_combout & !\z80_|ir_|opcode [3])))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_low .lut_mask = 16'hC0E0; -defparam \z80_|execute_|ctl_alu_op1_sel_low .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N6 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[3] ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_high|Q [3] = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & (\z80_|alu_|db_high[3]~8_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .datac(\z80_|alu_|db_high[3]~8_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [3]), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[3] .lut_mask = 16'h00C0; -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[3] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y10_N7 -dffeas \z80_|alu_|op1_high[3] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [3]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_high [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_high[3] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_high[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N10 -cycloneive_lcell_comb \z80_|alu_|alu_op1[3]~3 ( -// Equation(s): -// \z80_|alu_|alu_op1[3]~3_combout = (\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [3]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [3])) - - .dataa(gnd), - .datab(\z80_|alu_|op1_high [3]), - .datac(\z80_|alu_|op1_low [3]), - .datad(\z80_|execute_|ctl_alu_op_low~combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_op1[3]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op1[3]~3 .lut_mask = 16'hF0CC; -defparam \z80_|alu_|alu_op1[3]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N16 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout = (!\z80_|alu_|alu_op2[2]~0_combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_low [2]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_high -// [2])))) - - .dataa(\z80_|alu_|op1_high [2]), - .datab(\z80_|alu_|op1_low [2]), - .datac(\z80_|alu_|alu_op2[2]~0_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h0305; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~6_combout = ((\z80_|pla_decode_|Equal8~0_combout & (\z80_|execute_|ixy_d~5_combout & \z80_|execute_|ctl_mWrite~2_combout ))) # (!\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ) - - .dataa(\z80_|pla_decode_|Equal8~0_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ), - .datad(\z80_|execute_|ctl_mWrite~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~6 .lut_mask = 16'h8F0F; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~10_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ixy_d~15_combout & ((\z80_|execute_|ctl_bus_db_oe~1_combout ) # (!\z80_|sequencer_|DFFE_M3_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~10 .lut_mask = 16'hAAFB; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~0 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~0_combout = (\z80_|pla_decode_|Equal1~5_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~5_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|pla_decode_|Equal13~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~0 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_alu_core_R~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~5_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|execute_|ctl_alu_core_R~0_combout & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T3_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datad(\z80_|execute_|ctl_alu_core_R~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~5 .lut_mask = 16'hFEF0; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~7 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~7_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ) # (((\z80_|execute_|ctl_alu_op2_sel_bus~5_combout ) # (!\z80_|execute_|ctl_reg_use_sp~1_combout )) # (!\z80_|execute_|ctl_alu_op2_sel_bus~10_combout )) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), - .datab(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), - .datac(\z80_|execute_|ctl_reg_use_sp~1_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~7 .lut_mask = 16'hFFBF; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~8_combout = ((\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ) # ((\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_alu_shift_oe~14_combout ))) # (!\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~8 .lut_mask = 16'hFF8F; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N4 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout = (\z80_|alu_|db_low[1]~17_combout & ((\z80_|execute_|ctl_alu_op2_sel_lq~combout ) # ((\z80_|alu_|db_high[1]~20_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) # -// (!\z80_|alu_|db_low[1]~17_combout & (((\z80_|alu_|db_high[1]~20_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) - - .dataa(\z80_|alu_|db_low[1]~17_combout ), - .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datac(\z80_|alu_|db_high[1]~20_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5 .lut_mask = 16'hF888; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N0 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout ) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datab(gnd), - .datac(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6 .lut_mask = 16'h5050; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N16 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|ena ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|ena~combout = (\z80_|execute_|ctl_alu_op2_sel_zero~combout ) # ((\z80_|execute_|ctl_alu_op2_sel_lq~combout ) # (\z80_|execute_|ctl_alu_op2_sel_bus~8_combout )) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|ena .lut_mask = 16'hFFFA; -defparam \z80_|alu_|b2v_op2_latch_mux_high|ena .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y10_N1 -dffeas \z80_|alu_|op2_high[1] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_high [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_high[1] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_high[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N22 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[1] ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_high|Q [1] = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & (\z80_|alu_|db_high[1]~20_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .datac(\z80_|alu_|db_high[1]~20_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [1]), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[1] .lut_mask = 16'h00C0; -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[1] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y10_N23 -dffeas \z80_|alu_|op1_high[1] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [1]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_high [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_high[1] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_high[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N28 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [1])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [1]))))) - - .dataa(\z80_|alu_|op1_low [1]), - .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datac(\z80_|execute_|ctl_alu_op_low~combout ), - .datad(\z80_|alu_|op1_high [1]), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 .lut_mask = 16'h8C80; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N20 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ) # ((\z80_|alu_|db_low[1]~17_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datab(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ), - .datac(\z80_|alu_|db_low[1]~17_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 .lut_mask = 16'h5444; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y10_N21 -dffeas \z80_|alu_|op2_low[1] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_low [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_low[1] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_low[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~6_combout = (((!\z80_|nM1_int~2_combout & !\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal63~0_combout )) # (!\z80_|pla_decode_|Equal32~0_combout ) - - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal63~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~6 .lut_mask = 16'h57FF; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~20 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~20_combout = (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|pla_decode_|Equal68~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal68~2_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~20 .lut_mask = 16'h0D0F; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~12 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~12_combout = (\z80_|execute_|ctl_state_alu~9_combout ) # ((\z80_|execute_|ctl_reg_gp_sel~36_combout ) # ((\z80_|execute_|ctl_state_alu~11_combout ) # (!\z80_|execute_|ctl_state_alu~8_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~9_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel~36_combout ), - .datac(\z80_|execute_|ctl_state_alu~11_combout ), - .datad(\z80_|execute_|ctl_state_alu~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~12 .lut_mask = 16'hFEFF; -defparam \z80_|execute_|ctl_state_alu~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~18 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~18_combout = ((!\z80_|pla_decode_|Equal3~0_combout & ((\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal21~0_combout )))) # (!\z80_|execute_|ctl_state_alu~12_combout ) - - .dataa(\z80_|execute_|ctl_state_alu~12_combout ), - .datab(\z80_|pla_decode_|Equal3~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal21~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~18 .lut_mask = 16'h7577; -defparam \z80_|execute_|ctl_alu_core_hf~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N0 -cycloneive_lcell_comb \z80_|pla_decode_|Equal61~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal61~2_combout = (\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal6~0_combout & (!\z80_|ir_|opcode [1] & \z80_|ir_|opcode [0]))) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal61~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal61~2 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal61~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~16 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~16_combout = (\z80_|pla_decode_|Equal61~2_combout & ((\z80_|sequencer_|DFFE_M2_ff~q ) # (\z80_|sequencer_|DFFE_M4_ff~q ))) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|pla_decode_|Equal61~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~16 .lut_mask = 16'hFC00; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~17 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~17_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~6_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~20_combout & (\z80_|execute_|ctl_alu_core_hf~18_combout & !\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ))) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~20_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~18_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~17 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~21 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~21_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~17_combout & (((!\z80_|execute_|ctl_mWrite~16_combout ) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|execute_|ctl_mWrite~16_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~21 .lut_mask = 16'h7F00; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~15 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~15_combout = (((\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ) # (\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout )) # (!\z80_|execute_|ctl_alu_sel_op2_neg~4_combout )) # (!\z80_|execute_|ctl_reg_out_hi~4_combout -// ) - - .dataa(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~15 .lut_mask = 16'hFFF7; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~12 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~12_combout = (\z80_|execute_|ctl_flags_alu~17_combout & (\z80_|execute_|ctl_bus_inc_oe~43_combout & (\z80_|execute_|ctl_alu_core_S~4_combout & \z80_|execute_|ctl_alu_op1_sel_bus~8_combout ))) - - .dataa(\z80_|execute_|ctl_flags_alu~17_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .datac(\z80_|execute_|ctl_alu_core_S~4_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~12 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N6 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~22 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~22_combout = (\z80_|execute_|ctl_alu_shift_oe~38_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|execute_|ctl_ir_we~11_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~11_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~22 .lut_mask = 16'hC4CC; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~20 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~20_combout = ((\z80_|ir_|opcode [5]) # ((!\z80_|pla_decode_|Equal32~0_combout & !\z80_|pla_decode_|Equal9~0_combout ))) # (!\z80_|execute_|ctl_state_alu~12_combout ) - - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|pla_decode_|Equal9~0_combout ), - .datac(\z80_|execute_|ctl_state_alu~12_combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~20 .lut_mask = 16'hFF1F; -defparam \z80_|execute_|ctl_alu_core_hf~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~4_combout = (\z80_|execute_|ctl_flags_sz_we~0_combout & (((!\z80_|execute_|ctl_ir_we~12_combout & !\z80_|execute_|ctl_ir_we~11_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_flags_sz_we~0_combout ), - .datab(\z80_|execute_|ctl_ir_we~12_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_ir_we~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~4 .lut_mask = 16'h0A2A; -defparam \z80_|execute_|ctl_flags_sz_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N2 -cycloneive_lcell_comb \z80_|pla_decode_|Equal71~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal71~2_combout = (!\z80_|ir_|opcode [3] & (!\z80_|ir_|opcode [4] & (\z80_|execute_|ctl_state_alu~12_combout & \z80_|ir_|opcode [5]))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|execute_|ctl_state_alu~12_combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal71~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal71~2 .lut_mask = 16'h1000; -defparam \z80_|pla_decode_|Equal71~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N18 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~8 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~8_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~22_combout & (\z80_|execute_|ctl_alu_core_hf~20_combout & (\z80_|execute_|ctl_flags_sz_we~4_combout & !\z80_|pla_decode_|Equal71~2_combout ))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~22_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~20_combout ), - .datac(\z80_|execute_|ctl_flags_sz_we~4_combout ), - .datad(\z80_|pla_decode_|Equal71~2_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~8 .lut_mask = 16'h0080; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~31 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~31_combout = (!\z80_|execute_|ctl_alu_op_low~9_combout & (((!\z80_|sequencer_|DFFE_M4_ff~q ) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|pla_decode_|Equal13~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~9_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_M4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~31 .lut_mask = 16'h1333; -defparam \z80_|execute_|ctl_alu_op_low~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N22 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~4 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~4_combout = (\z80_|pla_decode_|Equal21~0_combout & ((\z80_|nM1_int~2_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout )))) # (!\z80_|pla_decode_|Equal21~0_combout & (\z80_|pla_decode_|Equal3~0_combout & -// ((\z80_|nM1_int~2_combout ) # (\z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal21~0_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal3~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~4 .lut_mask = 16'hFCA8; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout = (\z80_|pla_decode_|Equal13~1_combout & (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal6~0_combout & !\z80_|ir_|opcode [5]))) - - .dataa(\z80_|pla_decode_|Equal13~1_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N16 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~5 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~5_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout & \z80_|pla_decode_|Equal63~0_combout -// ))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), - .datac(\z80_|pla_decode_|Equal63~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~5 .lut_mask = 16'hFFEC; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N26 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~6 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~6_combout = (\z80_|execute_|ctl_alu_op_low~31_combout & (\z80_|execute_|ctl_flags_pf_we~10_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~7_combout & !\z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~31_combout ), - .datab(\z80_|execute_|ctl_flags_pf_we~10_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~6 .lut_mask = 16'h0080; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal72~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal72~2_combout = (\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [3] & \z80_|execute_|ctl_state_alu~12_combout ))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|execute_|ctl_state_alu~12_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal72~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal72~2 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal72~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y9_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal73~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal73~2_combout = (\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [3] & (!\z80_|ir_|opcode [4] & \z80_|execute_|ctl_state_alu~12_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|execute_|ctl_state_alu~12_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal73~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal73~2 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal73~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~0 ( -// Equation(s): -// \z80_|execute_|ctl_flags_nf_we~0_combout = (\z80_|pla_decode_|Equal61~2_combout & (!\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|execute_|ctl_mRead~36_combout )))) # (!\z80_|pla_decode_|Equal61~2_combout & -// (((!\z80_|execute_|ixy_d~5_combout )) # (!\z80_|execute_|ctl_mRead~36_combout ))) - - .dataa(\z80_|pla_decode_|Equal61~2_combout ), - .datab(\z80_|execute_|ctl_mRead~36_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_nf_we~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_nf_we~0 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_flags_nf_we~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~1 ( -// Equation(s): -// \z80_|execute_|ctl_flags_nf_we~1_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout & (!\z80_|pla_decode_|Equal72~2_combout & (!\z80_|pla_decode_|Equal73~2_combout & \z80_|execute_|ctl_flags_nf_we~0_combout ))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ), - .datab(\z80_|pla_decode_|Equal72~2_combout ), - .datac(\z80_|pla_decode_|Equal73~2_combout ), - .datad(\z80_|execute_|ctl_flags_nf_we~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_nf_we~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_nf_we~1 .lut_mask = 16'h0200; -defparam \z80_|execute_|ctl_flags_nf_we~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_nf_we~2_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal10~0_combout ) # ((\z80_|pla_decode_|Equal11~0_combout ) # (\z80_|pla_decode_|Equal61~2_combout )))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal61~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_nf_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_nf_we~2 .lut_mask = 16'hF0E0; -defparam \z80_|execute_|ctl_flags_nf_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_nf_we~3_combout = ((\z80_|execute_|ctl_flags_nf_we~2_combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~21_combout )) # (!\z80_|execute_|ctl_flags_nf_we~1_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_flags_nf_we~1_combout ), - .datac(\z80_|execute_|ctl_flags_nf_we~2_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~21_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_nf_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_nf_we~3 .lut_mask = 16'hF3FF; -defparam \z80_|execute_|ctl_flags_nf_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~5_combout = (\z80_|sequencer_|DFFE_T4_ff~q ) # ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~5 .lut_mask = 16'hFAFF; -defparam \z80_|execute_|ctl_flags_sz_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~6_combout = (\z80_|pla_decode_|Equal48~0_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # ((\z80_|execute_|ctl_flags_sz_we~5_combout & \z80_|execute_|ctl_alu_core_R~0_combout )))) # -// (!\z80_|pla_decode_|Equal48~0_combout & (\z80_|execute_|ctl_flags_sz_we~5_combout & ((\z80_|execute_|ctl_alu_core_R~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal48~0_combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~5_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_alu_core_R~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~6 .lut_mask = 16'hECA0; -defparam \z80_|execute_|ctl_flags_sz_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_nf_we~4_combout = (((\z80_|execute_|ctl_flags_nf_we~3_combout ) # (\z80_|execute_|ctl_flags_sz_we~6_combout )) # (!\z80_|execute_|ctl_flags_xy_we~12_combout )) # (!\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~12_combout ), - .datac(\z80_|execute_|ctl_flags_nf_we~3_combout ), - .datad(\z80_|execute_|ctl_flags_sz_we~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_nf_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_nf_we~4 .lut_mask = 16'hFFF7; -defparam \z80_|execute_|ctl_flags_nf_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y9_N12 -cycloneive_lcell_comb \z80_|execute_|setM1~15 ( -// Equation(s): -// \z80_|execute_|setM1~15_combout = (!\z80_|execute_|ctl_alu_shift_oe~15_combout & (\z80_|execute_|ctl_sw_2u~1_combout & \z80_|execute_|ctl_state_alu~8_combout )) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_sw_2u~1_combout ), - .datad(\z80_|execute_|ctl_state_alu~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~15 .lut_mask = 16'h5000; -defparam \z80_|execute_|setM1~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|setM1~16 ( -// Equation(s): -// \z80_|execute_|setM1~16_combout = (\z80_|execute_|setM1~15_combout & (!\z80_|execute_|ctl_alu_op1_sel_zero~4_combout & (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & \z80_|execute_|ctl_alu_op_low~31_combout ))) - - .dataa(\z80_|execute_|setM1~15_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datad(\z80_|execute_|ctl_alu_op_low~31_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~16 .lut_mask = 16'h0200; -defparam \z80_|execute_|setM1~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~6_combout = (!\z80_|execute_|ctl_reg_gp_sel~36_combout & \z80_|execute_|setM1~16_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_sel~36_combout ), - .datad(\z80_|execute_|setM1~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~6 .lut_mask = 16'h0F00; -defparam \z80_|execute_|ctl_flags_xy_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~7_combout = (\z80_|execute_|ctl_flags_pf_we~2_combout & (\z80_|execute_|ctl_flags_xy_we~17_combout & (\z80_|execute_|ctl_flags_xy_we~6_combout & \z80_|execute_|ctl_alu_oe~5_combout ))) - - .dataa(\z80_|execute_|ctl_flags_pf_we~2_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~17_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~6_combout ), - .datad(\z80_|execute_|ctl_alu_oe~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~7 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_xy_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~2_combout = (\z80_|execute_|ctl_flags_sz_we~1_combout & (\z80_|execute_|ctl_flags_xy_we~7_combout & \z80_|execute_|ctl_alu_op2_sel_bus~10_combout )) - - .dataa(\z80_|execute_|ctl_flags_sz_we~1_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~7_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~2 .lut_mask = 16'h8800; -defparam \z80_|execute_|ctl_flags_sz_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla12M1T1_12~0 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout = (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal11~1_combout & (!\z80_|ir_|opcode [2] & \z80_|execute_|ctl_mWrite~2_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal11~1_combout ), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|execute_|ctl_mWrite~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel_pla12M1T1_12~0 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_pf_sel_pla12M1T1_12~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~1 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~1_combout = (\z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ) # ((\z80_|execute_|ctl_alu_core_R~0_combout & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|execute_|ctl_alu_core_R~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~1 .lut_mask = 16'hFBAA; -defparam \z80_|execute_|ctl_alu_core_R~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~7_combout = (\z80_|execute_|ctl_alu_core_R~1_combout ) # (((\z80_|execute_|ixy_d~7_combout & \z80_|pla_decode_|Equal56~0_combout )) # (!\z80_|execute_|ctl_flags_alu~18_combout )) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~1_combout ), - .datac(\z80_|pla_decode_|Equal56~0_combout ), - .datad(\z80_|execute_|ctl_flags_alu~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~7 .lut_mask = 16'hECFF; -defparam \z80_|execute_|ctl_flags_alu~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N24 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~8 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~8_combout = (\z80_|reg_control_|reg_sys_we_lo~5_combout & (((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|pla_decode_|Equal56~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal56~0_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|reg_control_|reg_sys_we_lo~5_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~8 .lut_mask = 16'h7F00; -defparam \z80_|reg_control_|reg_sys_we_lo~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~8_combout = ((\z80_|execute_|ctl_flags_alu~7_combout ) # ((!\z80_|reg_control_|reg_sys_we_lo~8_combout ) # (!\z80_|execute_|ctl_flags_alu~16_combout ))) # (!\z80_|execute_|ctl_flags_alu~6_combout ) - - .dataa(\z80_|execute_|ctl_flags_alu~6_combout ), - .datab(\z80_|execute_|ctl_flags_alu~7_combout ), - .datac(\z80_|execute_|ctl_flags_alu~16_combout ), - .datad(\z80_|reg_control_|reg_sys_we_lo~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~8 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_flags_alu~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~16 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~16_combout = (\z80_|execute_|ctl_alu_op_low~10_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|pla_decode_|Equal20~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal20~0_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|execute_|ctl_alu_op_low~10_combout ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~16 .lut_mask = 16'hD0F0; -defparam \z80_|execute_|ctl_flags_xy_we~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~12 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~12_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~5_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout & ((!\z80_|execute_|ctl_mRead~36_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|ctl_mRead~36_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~12 .lut_mask = 16'h0070; -defparam \z80_|execute_|ctl_flags_alu~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~13 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~13_combout = (\z80_|execute_|ctl_flags_sz_we~4_combout & (\z80_|execute_|ctl_flags_xy_we~16_combout & (\z80_|execute_|ctl_sw_2d~4_combout & \z80_|execute_|ctl_flags_alu~12_combout ))) - - .dataa(\z80_|execute_|ctl_flags_sz_we~4_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~16_combout ), - .datac(\z80_|execute_|ctl_sw_2d~4_combout ), - .datad(\z80_|execute_|ctl_flags_alu~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~13 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_alu~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~14 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~14_combout = (\z80_|execute_|ctl_reg_use_sp~1_combout & (\z80_|execute_|ctl_alu_op_low~15_combout & (\z80_|execute_|ctl_sw_4u~1_combout & \z80_|execute_|ctl_flags_alu~13_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~1_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~15_combout ), - .datac(\z80_|execute_|ctl_sw_4u~1_combout ), - .datad(\z80_|execute_|ctl_flags_alu~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~14 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_alu~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~15 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~15_combout = ((\z80_|execute_|ctl_flags_alu~8_combout ) # ((!\z80_|execute_|ctl_flags_alu~11_combout ) # (!\z80_|execute_|ctl_flags_alu~14_combout ))) # (!\z80_|execute_|ctl_flags_sz_we~2_combout ) - - .dataa(\z80_|execute_|ctl_flags_sz_we~2_combout ), - .datab(\z80_|execute_|ctl_flags_alu~8_combout ), - .datac(\z80_|execute_|ctl_flags_alu~14_combout ), - .datad(\z80_|execute_|ctl_flags_alu~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~15 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_flags_alu~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [3] & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N12 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout = (\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ) # ((\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal10~0_combout ) # (\z80_|pla_decode_|Equal61~2_combout )))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal61~2_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 .lut_mask = 16'hFCEC; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~19 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~19_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal3~1_combout ))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal3~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~19 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N30 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ) # ((\z80_|execute_|ctl_alu_sel_op2_neg~19_combout ) # ((\z80_|alu_control_|db[1]~26_combout & \z80_|execute_|ctl_flags_bus~combout ))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~19_combout ), - .datac(\z80_|alu_control_|db[1]~26_combout ), - .datad(\z80_|execute_|ctl_flags_bus~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 .lut_mask = 16'hFEEE; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N20 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout = ((\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ) # ((\z80_|execute_|ctl_flags_alu~15_combout & \z80_|alu_|db_high[3]~8_combout ))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ) - - .dataa(\z80_|execute_|ctl_flags_alu~15_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), - .datac(\z80_|alu_|db_high[3]~8_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 .lut_mask = 16'hFFB3; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N20 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~7 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~7_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout & (((!\z80_|pla_decode_|Equal32~0_combout & !\z80_|pla_decode_|Equal21~0_combout )) # (!\z80_|pla_decode_|Equal62~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|pla_decode_|Equal62~2_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ), - .datad(\z80_|pla_decode_|Equal21~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~7 .lut_mask = 16'h3070; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N6 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~9 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~9_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~7_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~11_combout & (!\z80_|execute_|ctl_alu_core_R~1_combout & \z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~7_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~11_combout ), - .datac(\z80_|execute_|ctl_alu_core_R~1_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~9 .lut_mask = 16'h0800; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N26 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~10 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~10_combout = (\z80_|execute_|ctl_flags_nf_we~4_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout & ((\z80_|alu_flags_|DFFE_inst_latch_nf~9_combout )))) # (!\z80_|execute_|ctl_flags_nf_we~4_combout & -// (((\z80_|alu_flags_|DFFE_inst_latch_nf~q )))) - - .dataa(\z80_|execute_|ctl_flags_nf_we~4_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~9_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~10 .lut_mask = 16'hD850; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y9_N27 -dffeas \z80_|alu_flags_|DFFE_inst_latch_nf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|DFFE_inst_latch_nf~10_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~7 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~7_combout = ((\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # (\z80_|execute_|ctl_flags_cf2_sel_daa~combout )))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~7 .lut_mask = 16'hE0FF; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [3] & \z80_|execute_|ixy_d~7_combout ))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~10_combout = (\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ) # ((\z80_|pla_decode_|Equal61~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # (\z80_|nM1_int~2_combout )))) - - .dataa(\z80_|pla_decode_|Equal61~2_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~10 .lut_mask = 16'hFFA8; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~8_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (!\z80_|sequencer_|DFFE_T3_ff~q & ((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|sequencer_|DFFE_M3_ff~q )))) # (!\z80_|sequencer_|DFFE_M2_ff~q & -// (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|sequencer_|DFFE_M3_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~8 .lut_mask = 16'h7707; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~9_combout = ((\z80_|pla_decode_|Equal10~0_combout & ((\z80_|nM1_int~2_combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~8_combout )))) # (!\z80_|execute_|ctl_alu_op_low~33_combout ) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~33_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~9 .lut_mask = 16'hB3BB; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~11_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ) # ((\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ) # ((\z80_|execute_|ctl_alu_op_low~8_combout & \z80_|execute_|ctl_alu_op_low~12_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~12_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~11 .lut_mask = 16'hFFEC; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~14_combout = (((\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ) # (\z80_|execute_|ctl_alu_sel_op2_neg~11_combout )) # (!\z80_|execute_|ctl_alu_sel_op2_neg~12_combout )) # (!\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~14 .lut_mask = 16'hFFF7; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~18 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~18_combout = ((\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ) # ((\z80_|execute_|ctl_alu_sel_op2_neg~15_combout & \z80_|alu_flags_|DFFE_inst_latch_sf~q ))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~21_combout ) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~21_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~18 .lut_mask = 16'hFDF5; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_high ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_high~combout = ((\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|pla_decode_|Equal13~2_combout & \z80_|sequencer_|DFFE_M3_ff~q ))) # (!\z80_|execute_|ctl_alu_res_oe~2_combout ) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|pla_decode_|Equal13~2_combout ), - .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_high .lut_mask = 16'h8F0F; -defparam \z80_|execute_|ctl_alu_sel_op2_high .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N6 -cycloneive_lcell_comb \z80_|alu_|alu_op2[1]~1 ( -// Equation(s): -// \z80_|alu_|alu_op2[1]~1_combout = \z80_|execute_|ctl_alu_sel_op2_neg~18_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_high [1])) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_low [1]))))) - - .dataa(\z80_|alu_|op2_high [1]), - .datab(\z80_|alu_|op2_low [1]), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_op2[1]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op2[1]~1 .lut_mask = 16'h5A3C; -defparam \z80_|alu_|alu_op2[1]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N30 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout = (!\z80_|alu_|alu_op2[1]~1_combout & ((\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_low [1])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_high -// [1]))))) - - .dataa(\z80_|alu_|alu_op2[1]~1_combout ), - .datab(\z80_|alu_|op1_low [1]), - .datac(\z80_|execute_|ctl_alu_op_low~combout ), - .datad(\z80_|alu_|op1_high [1]), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'h1015; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~9_combout = (((\z80_|pla_decode_|Equal71~2_combout ) # (!\z80_|execute_|ctl_alu_core_S~11_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~10_combout )) # (!\z80_|execute_|ctl_alu_core_S~5_combout ) - - .dataa(\z80_|execute_|ctl_alu_core_S~5_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), - .datac(\z80_|execute_|ctl_alu_core_S~11_combout ), - .datad(\z80_|pla_decode_|Equal71~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~9 .lut_mask = 16'hFF7F; -defparam \z80_|execute_|ctl_alu_core_S~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N22 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout = (\z80_|alu_|db_high[0]~26_combout & ((\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ) # ((\z80_|alu_|db_low[0]~23_combout & \z80_|execute_|ctl_alu_op2_sel_lq~combout )))) # -// (!\z80_|alu_|db_high[0]~26_combout & (\z80_|alu_|db_low[0]~23_combout & (\z80_|execute_|ctl_alu_op2_sel_lq~combout ))) - - .dataa(\z80_|alu_|db_high[0]~26_combout ), - .datab(\z80_|alu_|db_low[0]~23_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7 .lut_mask = 16'hEAC0; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N6 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8_combout = (\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout & !\z80_|execute_|ctl_alu_op2_sel_zero~combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8 .lut_mask = 16'h00F0; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y10_N7 -dffeas \z80_|alu_|op2_high[0] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_high [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_high[0] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_high[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N2 -cycloneive_lcell_comb \z80_|alu_|alu_op2[0]~3 ( -// Equation(s): -// \z80_|alu_|alu_op2[0]~3_combout = \z80_|execute_|ctl_alu_sel_op2_neg~18_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [0]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [0])))) - - .dataa(\z80_|alu_|op2_low [0]), - .datab(\z80_|alu_|op2_high [0]), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_op2[0]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op2[0]~3 .lut_mask = 16'h3C5A; -defparam \z80_|alu_|alu_op2[0]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N0 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~12 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~12_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout & ((\z80_|ir_|opcode [3]) # ((!\z80_|ir_|opcode [4]) # (!\z80_|pla_decode_|Equal62~2_combout )))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal62~2_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~12 .lut_mask = 16'hB0F0; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~8_combout = (!\z80_|execute_|ctl_alu_core_R~1_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~6_combout & \z80_|execute_|ctl_alu_core_S~7_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_R~1_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~8 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_alu_core_S~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N2 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout = (((!\z80_|execute_|ctl_alu_core_S~9_combout & !\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout )) # (!\z80_|execute_|ctl_alu_core_S~8_combout )) # -// (!\z80_|execute_|ctl_alu_core_R~4_combout ) - - .dataa(\z80_|execute_|ctl_alu_core_S~9_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~4_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 .lut_mask = 16'h37FF; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~21 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~21_combout = (\z80_|execute_|ctl_alu_core_hf~20_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # ((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|execute_|ixy_d~15_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|execute_|ixy_d~15_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~20_combout ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~21 .lut_mask = 16'hB0F0; -defparam \z80_|execute_|ctl_alu_core_hf~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~22 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~22_combout = (((\z80_|execute_|ixy_d~8_combout & \z80_|pla_decode_|Equal21~1_combout )) # (!\z80_|execute_|ctl_alu_core_hf~21_combout )) # (!\z80_|execute_|ctl_alu_core_hf~18_combout ) - - .dataa(\z80_|execute_|ctl_alu_core_hf~18_combout ), - .datab(\z80_|execute_|ixy_d~8_combout ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~21_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~22 .lut_mask = 16'hD5FF; -defparam \z80_|execute_|ctl_alu_core_hf~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~19 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~19_combout = (\z80_|pla_decode_|Equal21~1_combout & ((\z80_|execute_|ctl_mRead~11_combout ) # ((\z80_|execute_|ixy_d~6_combout & !\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~11_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~19 .lut_mask = 16'hA0E0; -defparam \z80_|execute_|ctl_alu_core_hf~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~27 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~27_combout = (\z80_|execute_|ctl_alu_op_low~19_combout ) # (((\z80_|execute_|ctl_alu_op_low~22_combout ) # (!\z80_|execute_|ctl_alu_op_low~33_combout )) # (!\z80_|execute_|ctl_alu_op_low~17_combout )) - - .dataa(\z80_|execute_|ctl_alu_op_low~19_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~22_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~33_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~27 .lut_mask = 16'hFBFF; -defparam \z80_|execute_|ctl_alu_op_low~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~29 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~29_combout = (\z80_|execute_|ctl_alu_op_low~23_combout ) # ((\z80_|execute_|ctl_alu_op_low~34_combout ) # (\z80_|execute_|ctl_alu_op_low~27_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op_low~23_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~34_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~29 .lut_mask = 16'hFFFC; -defparam \z80_|execute_|ctl_alu_op_low~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~23 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~23_combout = (\z80_|execute_|ctl_alu_core_hf~22_combout & (((\z80_|execute_|ctl_alu_core_hf~19_combout & !\z80_|execute_|ctl_alu_op_low~29_combout )) # (!\z80_|execute_|ctl_alu_op_low~28_combout ))) # -// (!\z80_|execute_|ctl_alu_core_hf~22_combout & (\z80_|execute_|ctl_alu_core_hf~19_combout & (!\z80_|execute_|ctl_alu_op_low~29_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~22_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~19_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~29_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~28_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~23 .lut_mask = 16'h0CAE; -defparam \z80_|execute_|ctl_alu_core_hf~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~37 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~37_combout = (\z80_|pla_decode_|Equal39~0_combout ) # ((!\z80_|execute_|ixy_d~5_combout & \z80_|pla_decode_|Equal40~1_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|pla_decode_|Equal40~1_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~37 .lut_mask = 16'hFF30; -defparam \z80_|execute_|ctl_alu_core_hf~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~38 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~38_combout = (\z80_|execute_|ctl_alu_core_hf~37_combout & ((\z80_|execute_|ixy_d~6_combout ) # ((\z80_|execute_|ixy_d~8_combout & !\z80_|execute_|ixy_d~9_combout )))) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|execute_|ixy_d~8_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~37_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~38 .lut_mask = 16'hAE00; -defparam \z80_|execute_|ctl_alu_core_hf~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~24 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~24_combout = (\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (((!\z80_|pla_decode_|Equal32~0_combout ) # (!\z80_|pla_decode_|Equal63~0_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|pla_decode_|Equal63~0_combout ), - .datac(\z80_|pla_decode_|Equal32~0_combout ), - .datad(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~24 .lut_mask = 16'h7F00; -defparam \z80_|execute_|ctl_alu_core_hf~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~25 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~25_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # ((\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ) # ((!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & \z80_|execute_|ctl_alu_core_hf~24_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .datab(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~25 .lut_mask = 16'hEFEE; -defparam \z80_|execute_|ctl_alu_core_hf~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~26 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~26_combout = (\z80_|execute_|ctl_mRead~36_combout & ((\z80_|execute_|ctl_mRead~11_combout ) # ((\z80_|execute_|ixy_d~6_combout & !\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~36_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|execute_|ctl_mRead~11_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~26 .lut_mask = 16'hA0A8; -defparam \z80_|execute_|ctl_alu_core_hf~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~27 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~27_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ) # ((\z80_|execute_|ctl_alu_core_hf~26_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|execute_|ctl_mRead~36_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~36_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~26_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~27 .lut_mask = 16'hDFCC; -defparam \z80_|execute_|ctl_alu_core_hf~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~28 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~28_combout = (\z80_|execute_|ctl_alu_core_hf~25_combout & (((\z80_|execute_|ctl_alu_core_hf~27_combout & !\z80_|execute_|ctl_alu_op_low~27_combout )) # (!\z80_|execute_|ctl_alu_op_low~20_combout ))) # -// (!\z80_|execute_|ctl_alu_core_hf~25_combout & (((\z80_|execute_|ctl_alu_core_hf~27_combout & !\z80_|execute_|ctl_alu_op_low~27_combout )))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~25_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~20_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~27_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~28 .lut_mask = 16'h22F2; -defparam \z80_|execute_|ctl_alu_core_hf~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~30 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~30_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ) # (((\z80_|execute_|ctl_alu_op_low~14_combout ) # (!\z80_|execute_|ctl_alu_op2_sel_bus~9_combout )) # (!\z80_|execute_|ctl_state_alu~13_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), - .datab(\z80_|execute_|ctl_state_alu~13_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~30 .lut_mask = 16'hFBFF; -defparam \z80_|execute_|ctl_alu_op_low~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~34 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~34_combout = (\z80_|execute_|ctl_mRead~6_combout & ((\z80_|execute_|ctl_mWrite~3_combout ) # ((\z80_|execute_|ctl_mWrite~7_combout & !\z80_|execute_|ctl_state_alu~6_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~3_combout ), - .datab(\z80_|execute_|ctl_mWrite~7_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_mRead~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~34 .lut_mask = 16'hAE00; -defparam \z80_|execute_|ctl_alu_core_hf~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~32 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~32_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & (((\z80_|execute_|ctl_alu_op_low~11_combout )))) # (!\z80_|execute_|ctl_alu_op_low~8_combout & (\z80_|execute_|ixy_d~7_combout & -// ((!\z80_|execute_|ctl_mWrite~3_combout )))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~11_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datad(\z80_|execute_|ctl_mWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~32 .lut_mask = 16'hC0CA; -defparam \z80_|execute_|ctl_alu_core_hf~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~43 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~43_combout = (\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|execute_|ctl_mRead~6_combout & (\z80_|execute_|ctl_state_alu~6_combout ))) # (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M2_ff~q ) # -// ((\z80_|execute_|ctl_mRead~6_combout & \z80_|execute_|ctl_state_alu~6_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~43 .lut_mask = 16'hD5C0; -defparam \z80_|execute_|ctl_alu_core_hf~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~33 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~33_combout = (!\z80_|execute_|ctl_alu_core_hf~43_combout & ((\z80_|execute_|ctl_alu_core_hf~32_combout & ((\z80_|pla_decode_|Equal56~0_combout ) # (\z80_|execute_|ctl_alu_op_low~8_combout ))) # -// (!\z80_|execute_|ctl_alu_core_hf~32_combout & (\z80_|pla_decode_|Equal56~0_combout & \z80_|execute_|ctl_alu_op_low~8_combout )))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~32_combout ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~43_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~33 .lut_mask = 16'h00E8; -defparam \z80_|execute_|ctl_alu_core_hf~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~42 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~42_combout = (!\z80_|execute_|ctl_alu_shift_oe~15_combout & (((!\z80_|sequencer_|DFFE_M2_ff~q ) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|execute_|ctl_mRead~6_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~42 .lut_mask = 16'h1555; -defparam \z80_|execute_|ctl_alu_core_hf~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~35 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~35_combout = (\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # ((\z80_|execute_|ctl_alu_core_hf~42_combout & ((\z80_|execute_|ctl_alu_core_hf~34_combout ) # (\z80_|execute_|ctl_alu_core_hf~33_combout )))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~34_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~33_combout ), - .datac(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~42_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~35 .lut_mask = 16'hFEF0; -defparam \z80_|execute_|ctl_alu_core_hf~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~41 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~41_combout = (!\z80_|execute_|ctl_state_alu~4_combout & (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|pla_decode_|Equal10~0_combout & !\z80_|sequencer_|DFFE_T1_ff~q ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~41 .lut_mask = 16'h0040; -defparam \z80_|execute_|ctl_alu_core_hf~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~30 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~30_combout = (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|nM1_int~2_combout ) # ((\z80_|pla_decode_|Equal11~0_combout & !\z80_|execute_|ctl_alu_sel_op2_neg~8_combout )))) # (!\z80_|pla_decode_|Equal10~0_combout & -// (\z80_|pla_decode_|Equal11~0_combout & ((!\z80_|execute_|ctl_alu_sel_op2_neg~8_combout )))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~30 .lut_mask = 16'hA0EC; -defparam \z80_|execute_|ctl_alu_core_hf~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~10 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~10_combout = (!\z80_|ir_|opcode [2] & (\z80_|execute_|ctl_state_alu~4_combout & (\z80_|pla_decode_|Equal11~1_combout & \z80_|execute_|ctl_mWrite~2_combout ))) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|pla_decode_|Equal11~1_combout ), - .datad(\z80_|execute_|ctl_mWrite~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~10 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_mWrite~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~31 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~31_combout = (!\z80_|execute_|ctl_alu_op_low~14_combout & (!\z80_|execute_|ctl_mWrite~10_combout & ((\z80_|execute_|ctl_alu_core_hf~41_combout ) # (\z80_|execute_|ctl_alu_core_hf~30_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~41_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~30_combout ), - .datad(\z80_|execute_|ctl_mWrite~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~31 .lut_mask = 16'h0054; -defparam \z80_|execute_|ctl_alu_core_hf~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~44 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~44_combout = (\z80_|execute_|ctl_alu_op_low~12_combout & (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~44 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_core_hf~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~29 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~29_combout = (!\z80_|execute_|ctl_alu_op_low~19_combout & ((\z80_|execute_|ctl_alu_core_hf~44_combout ) # ((\z80_|execute_|ctl_alu_op_low~11_combout & \z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~44_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~11_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~19_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~29 .lut_mask = 16'h0E0A; -defparam \z80_|execute_|ctl_alu_core_hf~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~36 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~36_combout = (\z80_|execute_|ctl_alu_core_hf~31_combout ) # ((\z80_|execute_|ctl_alu_core_hf~29_combout ) # ((!\z80_|execute_|ctl_alu_op_low~30_combout & \z80_|execute_|ctl_alu_core_hf~35_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~30_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~35_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~31_combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~29_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~36 .lut_mask = 16'hFFF4; -defparam \z80_|execute_|ctl_alu_core_hf~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~39 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~39_combout = (\z80_|execute_|ctl_alu_core_hf~28_combout ) # ((\z80_|execute_|ctl_alu_core_hf~36_combout ) # ((\z80_|execute_|ctl_alu_core_hf~38_combout & !\z80_|execute_|ctl_alu_op_low~24_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~38_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~28_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~36_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~39 .lut_mask = 16'hFCFE; -defparam \z80_|execute_|ctl_alu_core_hf~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~40 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~40_combout = (\z80_|execute_|ctl_alu_core_hf~23_combout ) # ((\z80_|execute_|ctl_alu_core_hf~39_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout & !\z80_|execute_|ctl_alu_op_low~combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~23_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), - .datac(\z80_|execute_|ctl_alu_op_low~combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~39_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~40 .lut_mask = 16'hFFAE; -defparam \z80_|execute_|ctl_alu_core_hf~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_we~2_combout = (\z80_|execute_|ctl_flags_xy_we~11_combout & (\z80_|execute_|ctl_flags_hf_we~5_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_state_alu~14_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~14_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~11_combout ), - .datad(\z80_|execute_|ctl_flags_hf_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_we~2 .lut_mask = 16'h7000; -defparam \z80_|execute_|ctl_flags_hf_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~2 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~2_combout = (\z80_|nM1_int~2_combout & (\z80_|execute_|ctl_mWrite~2_combout & ((\z80_|pla_decode_|Equal55~0_combout ) # (\z80_|pla_decode_|Equal8~0_combout )))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~2_combout ), - .datad(\z80_|pla_decode_|Equal8~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~2 .lut_mask = 16'hA080; -defparam \z80_|execute_|ctl_alu_core_R~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~combout = (\z80_|execute_|ctl_alu_core_R~2_combout ) # (((\z80_|pla_decode_|Equal73~2_combout ) # (!\z80_|execute_|ctl_alu_core_S~8_combout )) # (!\z80_|execute_|ctl_alu_core_R~4_combout )) - - .dataa(\z80_|execute_|ctl_alu_core_R~2_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~4_combout ), - .datac(\z80_|pla_decode_|Equal73~2_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R .lut_mask = 16'hFBFF; -defparam \z80_|execute_|ctl_alu_core_R .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N2 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|alu_|db_low[3]~11_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~43_combout & !\z80_|alu_|db_high[3]~2_combout )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datab(\z80_|alu_|db_low[3]~11_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datad(\z80_|alu_|db_high[3]~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9 .lut_mask = 16'hC0D0; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N8 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~8_combout & \z80_|alu_|db_high[3]~8_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datab(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .datac(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9_combout ), - .datad(\z80_|alu_|db_high[3]~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2 .lut_mask = 16'h5450; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y10_N9 -dffeas \z80_|alu_|op2_high[3] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_high [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_high[3] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_high[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N2 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [3]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [3])))) - - .dataa(\z80_|alu_|op1_high [3]), - .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datac(\z80_|execute_|ctl_alu_op_low~combout ), - .datad(\z80_|alu_|op1_low [3]), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2 .lut_mask = 16'hC808; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N18 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2_combout ) # ((\z80_|alu_|db_low[3]~25_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datab(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2_combout ), - .datac(\z80_|alu_|db_low[3]~25_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3 .lut_mask = 16'h5444; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y10_N19 -dffeas \z80_|alu_|op2_low[3] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_low [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_low[3] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_low[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N26 -cycloneive_lcell_comb \z80_|alu_|alu_op2[3]~2 ( -// Equation(s): -// \z80_|alu_|alu_op2[3]~2_combout = \z80_|execute_|ctl_alu_sel_op2_neg~18_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_high [3])) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_low [3]))))) - - .dataa(\z80_|alu_|op2_high [3]), - .datab(\z80_|alu_|op2_low [3]), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_op2[3]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op2[3]~2 .lut_mask = 16'h5A3C; -defparam \z80_|alu_|alu_op2[3]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N4 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout = (\z80_|execute_|ctl_alu_core_S~9_combout ) # (((\z80_|alu_|alu_op1[3]~3_combout & \z80_|alu_|alu_op2[3]~2_combout )) # (!\z80_|execute_|ctl_alu_core_S~8_combout )) - - .dataa(\z80_|alu_|alu_op1[3]~3_combout ), - .datab(\z80_|execute_|ctl_alu_core_S~9_combout ), - .datac(\z80_|alu_|alu_op2[3]~2_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hECFF; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N16 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout = (!\z80_|alu_|alu_op2[3]~2_combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_low [3]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_high -// [3])))) - - .dataa(\z80_|alu_|alu_op2[3]~2_combout ), - .datab(\z80_|alu_|op1_high [3]), - .datac(\z80_|alu_|op1_low [3]), - .datad(\z80_|execute_|ctl_alu_op_low~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h0511; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N30 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ) # -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_core_R~combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0 .lut_mask = 16'hAFAE; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N2 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_hf~0 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_hf~0_combout = (\z80_|execute_|ctl_flags_bus~combout & ((\z80_|alu_control_|db[4]~32_combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & \z80_|execute_|ctl_flags_alu~15_combout )))) # -// (!\z80_|execute_|ctl_flags_bus~combout & (((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & \z80_|execute_|ctl_flags_alu~15_combout )))) - - .dataa(\z80_|execute_|ctl_flags_bus~combout ), - .datab(\z80_|alu_control_|db[4]~32_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), - .datad(\z80_|execute_|ctl_flags_alu~15_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_hf~0 .lut_mask = 16'h8F88; -defparam \z80_|alu_flags_|DFFE_inst_latch_hf~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_we~3_combout = (\z80_|pla_decode_|Equal11~0_combout & ((\z80_|nM1_int~2_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) # (!\z80_|pla_decode_|Equal11~0_combout & (((\z80_|pla_decode_|Equal10~0_combout & -// \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_we~3 .lut_mask = 16'hFC88; -defparam \z80_|execute_|ctl_flags_hf_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_we~4_combout = ((\z80_|execute_|ctl_flags_sz_we~6_combout ) # ((\z80_|execute_|ctl_flags_hf_we~3_combout ) # (!\z80_|execute_|ctl_flags_xy_we~6_combout ))) # (!\z80_|execute_|ctl_flags_alu~14_combout ) - - .dataa(\z80_|execute_|ctl_flags_alu~14_combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~6_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~6_combout ), - .datad(\z80_|execute_|ctl_flags_hf_we~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_we~4 .lut_mask = 16'hFFDF; -defparam \z80_|execute_|ctl_flags_hf_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N6 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_hf~1 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_hf~1_combout = (\z80_|execute_|ctl_flags_hf_we~2_combout & ((\z80_|execute_|ctl_flags_hf_we~4_combout & (\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout )) # (!\z80_|execute_|ctl_flags_hf_we~4_combout & -// ((\z80_|alu_flags_|DFFE_inst_latch_hf~q ))))) # (!\z80_|execute_|ctl_flags_hf_we~2_combout & (\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout )) - - .dataa(\z80_|execute_|ctl_flags_hf_we~2_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), - .datad(\z80_|execute_|ctl_flags_hf_we~4_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_hf~1 .lut_mask = 16'hCCE4; -defparam \z80_|alu_flags_|DFFE_inst_latch_hf~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y11_N7 -dffeas \z80_|alu_flags_|DFFE_inst_latch_hf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_hf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_hf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_cpl~11_combout = (\z80_|execute_|ctl_mRead~6_combout ) # ((\z80_|pla_decode_|Equal52~1_combout ) # (\z80_|execute_|ctl_state_alu~14_combout )) - - .dataa(\z80_|execute_|ctl_mRead~6_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal52~1_combout ), - .datad(\z80_|execute_|ctl_state_alu~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_cpl~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_cpl~11 .lut_mask = 16'hFFFA; -defparam \z80_|execute_|ctl_flags_hf_cpl~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~12 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_cpl~12_combout = ((\z80_|execute_|ctl_flags_hf_cpl~11_combout ) # ((\z80_|pla_decode_|Equal10~0_combout ) # (\z80_|execute_|ctl_alu_op_low~12_combout ))) # (!\z80_|execute_|ctl_flags_hf_cpl~10_combout ) - - .dataa(\z80_|execute_|ctl_flags_hf_cpl~10_combout ), - .datab(\z80_|execute_|ctl_flags_hf_cpl~11_combout ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_cpl~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_cpl~12 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_flags_hf_cpl~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~13 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_cpl~13_combout = (\z80_|execute_|ctl_flags_hf_cpl~12_combout & (\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|alu_flags_|DFFE_inst_latch_nf~q ))) - - .dataa(\z80_|execute_|ctl_flags_hf_cpl~12_combout ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_cpl~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_cpl~13 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_flags_hf_cpl~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N8 -cycloneive_lcell_comb \z80_|alu_flags_|flags_hf ( -// Equation(s): -// \z80_|alu_flags_|flags_hf~combout = \z80_|alu_flags_|DFFE_inst_latch_hf~q $ (((\z80_|execute_|ctl_flags_hf_cpl~13_combout ) # ((!\z80_|alu_flags_|flags_cf~combout & \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout )))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), - .datab(\z80_|alu_flags_|flags_cf~combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .datad(\z80_|execute_|ctl_flags_hf_cpl~13_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|flags_hf~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_hf .lut_mask = 16'h559A; -defparam \z80_|alu_flags_|flags_hf .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N30 -cycloneive_lcell_comb \z80_|alu_control_|alu_core_cf_in~0 ( -// Equation(s): -// \z80_|alu_control_|alu_core_cf_in~0_combout = (\z80_|execute_|ctl_alu_core_hf~40_combout & ((\z80_|alu_flags_|flags_hf~combout ))) # (!\z80_|execute_|ctl_alu_core_hf~40_combout & (\z80_|alu_flags_|flags_cf~combout )) - - .dataa(\z80_|execute_|ctl_alu_core_hf~40_combout ), - .datab(\z80_|alu_flags_|flags_cf~combout ), - .datac(gnd), - .datad(\z80_|alu_flags_|flags_hf~combout ), - .cin(gnd), - .combout(\z80_|alu_control_|alu_core_cf_in~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|alu_core_cf_in~0 .lut_mask = 16'hEE44; -defparam \z80_|alu_control_|alu_core_cf_in~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N20 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout = (\z80_|alu_|alu_op2[0]~3_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ) # ((\z80_|alu_control_|alu_core_cf_in~0_combout & \z80_|alu_|alu_op1[0]~1_combout )))) -// # (!\z80_|alu_|alu_op2[0]~3_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_control_|alu_core_cf_in~0_combout ) # (\z80_|alu_|alu_op1[0]~1_combout )))) - - .dataa(\z80_|alu_|alu_op2[0]~3_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ), - .datac(\z80_|alu_control_|alu_core_cf_in~0_combout ), - .datad(\z80_|alu_|alu_op1[0]~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 .lut_mask = 16'hECC8; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N12 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~23 ( -// Equation(s): -// \z80_|alu_|db_high[0]~23_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[5]~25_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[3]~11_combout )) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|alu_|db[3]~11_combout ), - .datac(\z80_|alu_|db[5]~25_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~23 .lut_mask = 16'hE4E4; -defparam \z80_|alu_|db_high[0]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N8 -cycloneive_lcell_comb \z80_|address_latch_|abusz[12] ( -// Equation(s): -// \z80_|address_latch_|abusz [12] = (\z80_|reg_file_|db_hi_as[4]~18_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(gnd), - .datab(\z80_|reg_file_|db_hi_as[4]~18_combout ), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [12]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[12] .lut_mask = 16'h0C0C; -defparam \z80_|address_latch_|abusz[12] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N14 -cycloneive_lcell_comb \z80_|address_latch_|Q[12]~feeder ( -// Equation(s): -// \z80_|address_latch_|Q[12]~feeder_combout = \z80_|address_latch_|abusz [12] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [12]), - .cin(gnd), - .combout(\z80_|address_latch_|Q[12]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|Q[12]~feeder .lut_mask = 16'hFF00; -defparam \z80_|address_latch_|Q[12]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N15 -dffeas \z80_|address_latch_|Q[12] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|Q[12]~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [12]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[12] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[12] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N30 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout = \z80_|address_latch_|Q [12] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout & (\z80_|execute_|ctl_inc_dec~11_combout $ -// (\z80_|address_latch_|Q [11]))))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), - .datab(\z80_|execute_|ctl_inc_dec~11_combout ), - .datac(\z80_|address_latch_|Q [12]), - .datad(\z80_|address_latch_|Q [11]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out .lut_mask = 16'hD278; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N5 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[4]~18_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y15_N7 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[4]~18_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N6 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~16 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[4]~16_combout = (\z80_|reg_control_|reg_sw_4d_hi~0_combout & (\z80_|reg_file_|gdfx_temp1[4]~66_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) - - .dataa(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [4]), - .datad(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[4]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[4]~16 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|db_hi_as[4]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N18 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~17 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[4]~17_combout = (\z80_|reg_file_|db_hi_as[4]~16_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datab(gnd), - .datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [4]), - .datad(\z80_|reg_file_|db_hi_as[4]~16_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[4]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[4]~17 .lut_mask = 16'hF500; -defparam \z80_|reg_file_|db_hi_as[4]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N4 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~18 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[4]~18_combout = ((\z80_|reg_file_|db_hi_as[4]~17_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datad(\z80_|reg_file_|db_hi_as[4]~17_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[4]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[4]~18 .lut_mask = 16'hBF0F; -defparam \z80_|reg_file_|db_hi_as[4]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y11_N11 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~62 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~62_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (\z80_|reg_file_|b2v_latch_af2_hi|latch [4] & ((\z80_|alu_|db[4]~17_combout ) # (!\z80_|execute_|ctl_reg_in_hi~12_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (((\z80_|alu_|db[4]~17_combout )) # (!\z80_|execute_|ctl_reg_in_hi~12_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [4]), - .datad(\z80_|alu_|db[4]~17_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~62_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~62 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[4]~62 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y15_N13 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y11_N29 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~63 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~63_combout = (\z80_|reg_file_|b2v_latch_sp_hi|latch [4] & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ))) # (!\z80_|reg_file_|b2v_latch_sp_hi|latch [4] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_sp_hi|latch [4]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~63_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~63 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[4]~63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y12_N23 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y12_N21 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~61 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~61_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (\z80_|reg_file_|b2v_latch_ix_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_iy_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (((\z80_|reg_file_|b2v_latch_iy_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_iy_hi|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~61_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~61 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[4]~61 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N24 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder_combout = \z80_|reg_file_|gdfx_temp1[4]~66_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y13_N25 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y13_N23 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~60 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~60_combout = (\z80_|reg_file_|b2v_latch_bc_hi|latch [4] & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_hi|latch [4] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc_hi|latch [4]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~60_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~60 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[4]~60 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~64 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~64_combout = (\z80_|reg_file_|gdfx_temp1[4]~62_combout & (\z80_|reg_file_|gdfx_temp1[4]~63_combout & (\z80_|reg_file_|gdfx_temp1[4]~61_combout & \z80_|reg_file_|gdfx_temp1[4]~60_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[4]~62_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[4]~63_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[4]~61_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[4]~60_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~64_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~64 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[4]~64 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N31 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y14_N29 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~59 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~59_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~59_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~59 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[4]~59 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y13_N23 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y13_N13 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~58 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~58_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~58_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~58 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[4]~58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y14_N19 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N18 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[4]~19 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[4]~19_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [4]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [4]), - .datad(\z80_|reg_control_|reg_sel_af~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[4]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[4]~19 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[4]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~65 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~65_combout = (\z80_|reg_file_|gdfx_temp1[4]~64_combout & (\z80_|reg_file_|gdfx_temp1[4]~59_combout & (\z80_|reg_file_|gdfx_temp1[4]~58_combout & \z80_|reg_file_|b2v_latch_af_hi|db[4]~19_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[4]~64_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[4]~59_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[4]~58_combout ), - .datad(\z80_|reg_file_|b2v_latch_af_hi|db[4]~19_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~65_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~65 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[4]~65 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~66 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~66_combout = ((\z80_|reg_file_|gdfx_temp1[4]~65_combout & ((\z80_|reg_file_|db_hi_as[4]~18_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datab(\z80_|reg_file_|db_hi_as[4]~18_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[4]~65_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~66 .lut_mask = 16'hD5F5; -defparam \z80_|reg_file_|gdfx_temp1[4]~66 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N26 -cycloneive_lcell_comb \z80_|alu_|db[4]~16 ( -// Equation(s): -// \z80_|alu_|db[4]~16_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[4]~66_combout & ((\z80_|alu_control_|db[4]~32_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & -// (((\z80_|alu_control_|db[4]~32_combout )) # (!\z80_|execute_|ctl_sw_2d~13_combout ))) - - .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datab(\z80_|execute_|ctl_sw_2d~13_combout ), - .datac(\z80_|alu_control_|db[4]~32_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[4]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[4]~16 .lut_mask = 16'hF351; -defparam \z80_|alu_|db[4]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N2 -cycloneive_lcell_comb \z80_|alu_|db[7]~26 ( -// Equation(s): -// \z80_|alu_|db[7]~26_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout ) # ((\z80_|execute_|ctl_alu_oe~13_combout ) # ((\z80_|execute_|ctl_sw_2d~13_combout ) # (!\z80_|execute_|ctl_alu_oe~9_combout ))) - - .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datab(\z80_|execute_|ctl_alu_oe~13_combout ), - .datac(\z80_|execute_|ctl_alu_oe~9_combout ), - .datad(\z80_|execute_|ctl_sw_2d~13_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[7]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[7]~26 .lut_mask = 16'hFFEF; -defparam \z80_|alu_|db[7]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N0 -cycloneive_lcell_comb \z80_|alu_|db[4]~17 ( -// Equation(s): -// \z80_|alu_|db[4]~17_combout = ((\z80_|alu_|db[4]~16_combout & ((\z80_|alu_|db_high[0]~26_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~26_combout ) - - .dataa(\z80_|alu_|db[4]~16_combout ), - .datab(\z80_|alu_|db[7]~26_combout ), - .datac(\z80_|alu_|db_high[0]~26_combout ), - .datad(\z80_|execute_|ctl_alu_oe~14_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[4]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[4]~17 .lut_mask = 16'hB3BB; -defparam \z80_|alu_|db[4]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_sel_shift~3_combout = (\z80_|execute_|ctl_state_alu~6_combout ) # ((\z80_|pla_decode_|Equal33~0_combout & (\z80_|execute_|ctl_mWrite~3_combout & \z80_|decode_state_|DFFE_instCB~q ))) - - .dataa(\z80_|execute_|ctl_state_alu~6_combout ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~3_combout ), - .datad(\z80_|decode_state_|DFFE_instCB~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~3 .lut_mask = 16'hEAAA; -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_sel_shift~5_combout = (\z80_|sequencer_|DFFE_T4_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|execute_|ctl_ir_we~8_combout ) # (\z80_|pla_decode_|Equal20~0_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|pla_decode_|Equal20~0_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~5 .lut_mask = 16'h00C8; -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_sel_shift~4_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ) # ((\z80_|execute_|ctl_ir_we~6_combout & (\z80_|execute_|ctl_flags_cf2_sel_shift~3_combout & \z80_|execute_|ctl_ir_we~5_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~6_combout ), - .datab(\z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ), - .datac(\z80_|execute_|ctl_ir_we~5_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~4 .lut_mask = 16'hFF80; -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N10 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~24 ( -// Equation(s): -// \z80_|alu_|db_high[0]~24_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_high[0]~23_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[4]~17_combout ))) - - .dataa(\z80_|alu_|db_high[0]~23_combout ), - .datab(gnd), - .datac(\z80_|alu_|db[4]~17_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~24 .lut_mask = 16'hAAF0; -defparam \z80_|alu_|db_high[0]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N4 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~21 ( -// Equation(s): -// \z80_|alu_|db_high[0]~21_combout = ((!\z80_|bus_control_|db[4]~19_combout & (\z80_|bus_control_|db[5]~15_combout & !\z80_|bus_control_|db[3]~21_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datab(\z80_|bus_control_|db[4]~19_combout ), - .datac(\z80_|bus_control_|db[5]~15_combout ), - .datad(\z80_|bus_control_|db[3]~21_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~21 .lut_mask = 16'h5575; -defparam \z80_|alu_|db_high[0]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N20 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[0] ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_high|Q [0] = (\z80_|alu_|db_high[0]~26_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) - - .dataa(gnd), - .datab(\z80_|alu_|db_high[0]~26_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [0]), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[0] .lut_mask = 16'h00C0; -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[0] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y10_N21 -dffeas \z80_|alu_|op1_high[0] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [0]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_high [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_high[0] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_high[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N8 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~22 ( -// Equation(s): -// \z80_|alu_|db_high[0]~22_combout = (\z80_|alu_|op1_high [0] & (((\z80_|alu_|op2_high [0]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|alu_|op1_high [0] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_high [0]) # -// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) - - .dataa(\z80_|alu_|op1_high [0]), - .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datac(\z80_|alu_|op2_high [0]), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~22 .lut_mask = 16'hB0BB; -defparam \z80_|alu_|db_high[0]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N4 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~25 ( -// Equation(s): -// \z80_|alu_|db_high[0]~25_combout = (\z80_|alu_|db_high[0]~21_combout & (\z80_|alu_|db_high[0]~22_combout & ((\z80_|alu_|db_high[0]~24_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) - - .dataa(\z80_|alu_|db_high[0]~24_combout ), - .datab(\z80_|alu_|db_high[0]~21_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datad(\z80_|alu_|db_high[0]~22_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~25 .lut_mask = 16'h8C00; -defparam \z80_|alu_|db_high[0]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N22 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~26 ( -// Equation(s): -// \z80_|alu_|db_high[0]~26_combout = ((\z80_|alu_|db_high[0]~25_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) # (!\z80_|alu_|db_high[3]~3_combout ) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), - .datab(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datac(\z80_|alu_|db_high[0]~25_combout ), - .datad(\z80_|alu_|db_high[3]~3_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~26 .lut_mask = 16'hE0FF; -defparam \z80_|alu_|db_high[0]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N4 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout = (\z80_|alu_|db_low[0]~23_combout & ((\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_low~combout & \z80_|alu_|db_high[0]~26_combout )))) # -// (!\z80_|alu_|db_low[0]~23_combout & (((\z80_|execute_|ctl_alu_op1_sel_low~combout & \z80_|alu_|db_high[0]~26_combout )))) - - .dataa(\z80_|alu_|db_low[0]~23_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .datad(\z80_|alu_|db_high[0]~26_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 .lut_mask = 16'hF888; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N30 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8_combout = (\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8 .lut_mask = 16'h00F0; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N12 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|ena ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|ena~combout = (\z80_|execute_|ctl_alu_op1_sel_low~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~combout ) # (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout )) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|ena .lut_mask = 16'hFEFE; -defparam \z80_|alu_|b2v_op1_latch_mux_low|ena .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y10_N31 -dffeas \z80_|alu_|op1_low[0] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_low [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_low[0] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_low[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N12 -cycloneive_lcell_comb \z80_|alu_|alu_op1[0]~1 ( -// Equation(s): -// \z80_|alu_|alu_op1[0]~1_combout = (\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [0])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [0]))) - - .dataa(\z80_|execute_|ctl_alu_op_low~combout ), - .datab(\z80_|alu_|op1_low [0]), - .datac(\z80_|alu_|op1_high [0]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|alu_op1[0]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op1[0]~1 .lut_mask = 16'hD8D8; -defparam \z80_|alu_|alu_op1[0]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N30 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout = (\z80_|alu_|alu_op1[0]~1_combout & ((\z80_|execute_|ctl_alu_op2_sel_lq~combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~8_combout & \z80_|alu_|db_low[0]~23_combout )))) # -// (!\z80_|alu_|alu_op1[0]~1_combout & (\z80_|execute_|ctl_alu_op2_sel_bus~8_combout & ((\z80_|alu_|db_low[0]~23_combout )))) - - .dataa(\z80_|alu_|alu_op1[0]~1_combout ), - .datab(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datad(\z80_|alu_|db_low[0]~23_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 .lut_mask = 16'hECA0; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N14 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datab(gnd), - .datac(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 .lut_mask = 16'h5050; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y10_N15 -dffeas \z80_|alu_|op2_low[0] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_low [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_low[0] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_low[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N12 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout = (\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [0]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [0])) - - .dataa(\z80_|alu_|op2_low [0]), - .datab(gnd), - .datac(\z80_|alu_|op2_high [0]), - .datad(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'hF0AA; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N14 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout = (\z80_|alu_control_|alu_core_cf_in~0_combout & ((\z80_|alu_|alu_op1[0]~1_combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout $ -// (\z80_|execute_|ctl_alu_sel_op2_neg~18_combout )))) # (!\z80_|alu_control_|alu_core_cf_in~0_combout & (\z80_|alu_|alu_op1[0]~1_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout $ -// (\z80_|execute_|ctl_alu_sel_op2_neg~18_combout )))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), - .datac(\z80_|alu_control_|alu_core_cf_in~0_combout ), - .datad(\z80_|alu_|alu_op1[0]~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hF660; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N28 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|execute_|ctl_alu_core_S~9_combout & (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout & -// \z80_|execute_|ctl_alu_core_S~8_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_S~9_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), - .datac(\z80_|execute_|ctl_alu_core_R~combout ), - .datad(\z80_|execute_|ctl_alu_core_S~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 .lut_mask = 16'hF1F0; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N26 -cycloneive_lcell_comb \z80_|alu_|alu_op1[1]~0 ( -// Equation(s): -// \z80_|alu_|alu_op1[1]~0_combout = (\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [1])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [1]))) - - .dataa(\z80_|execute_|ctl_alu_op_low~combout ), - .datab(\z80_|alu_|op1_low [1]), - .datac(gnd), - .datad(\z80_|alu_|op1_high [1]), - .cin(gnd), - .combout(\z80_|alu_|alu_op1[1]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op1[1]~0 .lut_mask = 16'hDD88; -defparam \z80_|alu_|alu_op1[1]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N0 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout = (\z80_|execute_|ctl_alu_core_S~9_combout ) # (((\z80_|alu_|alu_op1[1]~0_combout & \z80_|alu_|alu_op2[1]~1_combout )) # (!\z80_|execute_|ctl_alu_core_S~8_combout )) - - .dataa(\z80_|execute_|ctl_alu_core_S~9_combout ), - .datab(\z80_|execute_|ctl_alu_core_S~8_combout ), - .datac(\z80_|alu_|alu_op1[1]~0_combout ), - .datad(\z80_|alu_|alu_op2[1]~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'hFBBB; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N24 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout = (!\z80_|execute_|ctl_alu_core_R~combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ) # -// ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout & !\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout )))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), - .datac(\z80_|execute_|ctl_alu_core_R~combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 .lut_mask = 16'h0F01; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N26 -cycloneive_lcell_comb \z80_|alu_|alu_op1[2]~2 ( -// Equation(s): -// \z80_|alu_|alu_op1[2]~2_combout = (\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [2]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [2])) - - .dataa(\z80_|alu_|op1_high [2]), - .datab(\z80_|execute_|ctl_alu_op_low~combout ), - .datac(gnd), - .datad(\z80_|alu_|op1_low [2]), - .cin(gnd), - .combout(\z80_|alu_|alu_op1[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op1[2]~2 .lut_mask = 16'hEE22; -defparam \z80_|alu_|alu_op1[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N8 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout = (\z80_|execute_|ctl_alu_core_S~9_combout ) # (((\z80_|alu_|alu_op2[2]~0_combout & \z80_|alu_|alu_op1[2]~2_combout )) # (!\z80_|execute_|ctl_alu_core_S~8_combout )) - - .dataa(\z80_|alu_|alu_op2[2]~0_combout ), - .datab(\z80_|execute_|ctl_alu_core_S~9_combout ), - .datac(\z80_|alu_|alu_op1[2]~2_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hECFF; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N2 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ) # -// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), - .datad(\z80_|execute_|ctl_alu_core_R~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 .lut_mask = 16'hFF0B; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~5_combout = (\z80_|execute_|ctl_alu_core_R~4_combout & \z80_|execute_|ctl_alu_core_S~8_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_core_R~4_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~5 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_alu_core_R~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N6 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ) # -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout )))) # (!\z80_|execute_|ctl_alu_core_R~5_combout ) - - .dataa(\z80_|execute_|ctl_alu_core_R~5_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1 .lut_mask = 16'h5F5D; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N14 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout = (\z80_|alu_|alu_op1[3]~3_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout & -// \z80_|alu_|alu_op2[3]~2_combout )))) # (!\z80_|alu_|alu_op1[3]~3_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_|alu_op2[3]~2_combout ) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout )))) - - .dataa(\z80_|alu_|alu_op1[3]~3_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), - .datac(\z80_|alu_|alu_op2[3]~2_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 .lut_mask = 16'hFB20; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N12 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder_combout = \z80_|reg_file_|gdfx_temp1[7]~75_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y13_N13 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y13_N19 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~69 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~69_combout = (\z80_|reg_file_|b2v_latch_bc_hi|latch [7] & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_hi|latch [7] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc_hi|latch [7]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~69_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~69 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[7]~69 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y12_N3 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y12_N25 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~70 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~70_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (\z80_|reg_file_|b2v_latch_ix_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_iy_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (((\z80_|reg_file_|b2v_latch_iy_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_iy_hi|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~70_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~70 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[7]~70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y15_N11 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y11_N27 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~72 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~72_combout = (\z80_|reg_file_|b2v_latch_sp_hi|latch [7] & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ))) # (!\z80_|reg_file_|b2v_latch_sp_hi|latch [7] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_sp_hi|latch [7]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~72_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~72 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[7]~72 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y11_N17 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~71 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~71_combout = (\z80_|alu_|db[7]~21_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[7]~21_combout & (!\z80_|execute_|ctl_reg_in_hi~12_combout & -// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|alu_|db[7]~21_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~71_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~71 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[7]~71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~73 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~73_combout = (\z80_|reg_file_|gdfx_temp1[7]~69_combout & (\z80_|reg_file_|gdfx_temp1[7]~70_combout & (\z80_|reg_file_|gdfx_temp1[7]~72_combout & \z80_|reg_file_|gdfx_temp1[7]~71_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[7]~69_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[7]~70_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[7]~72_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[7]~71_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~73_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~73 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[7]~73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y13_N27 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y13_N17 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~67 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~67_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~67_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~67 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[7]~67 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y14_N15 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N14 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[7]~20 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[7]~20_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [7]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [7]), - .datad(\z80_|reg_control_|reg_sel_af~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[7]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[7]~20 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[7]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N11 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y14_N21 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~68 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~68_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~68_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~68 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[7]~68 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y11_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~74 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~74_combout = (\z80_|reg_file_|gdfx_temp1[7]~73_combout & (\z80_|reg_file_|gdfx_temp1[7]~67_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[7]~20_combout & \z80_|reg_file_|gdfx_temp1[7]~68_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[7]~73_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[7]~67_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|db[7]~20_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[7]~68_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~74_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~74 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[7]~74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y15_N29 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[7]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N28 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~19 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[7]~19_combout = (\z80_|reg_file_|gdfx_temp1[7]~75_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) # (!\z80_|reg_file_|gdfx_temp1[7]~75_combout & -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [7]), - .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[7]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[7]~19 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_hi_as[7]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N27 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[7]~21_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N28 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~20 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[7]~20_combout = (\z80_|reg_file_|db_hi_as[7]~19_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|db_hi_as[7]~19_combout ), - .datab(gnd), - .datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[7]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[7]~20 .lut_mask = 16'hA0AA; -defparam \z80_|reg_file_|db_hi_as[7]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N2 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout & ((\z80_|execute_|ctl_inc_dec~11_combout & (!\z80_|address_latch_|Q [12] & -// !\z80_|address_latch_|Q [11])) # (!\z80_|execute_|ctl_inc_dec~11_combout & (\z80_|address_latch_|Q [12] & \z80_|address_latch_|Q [11])))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), - .datab(\z80_|execute_|ctl_inc_dec~11_combout ), - .datac(\z80_|address_latch_|Q [12]), - .datad(\z80_|address_latch_|Q [11]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'h2008; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N8 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout = \z80_|address_latch_|Q [13] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|address_latch_|Q [13]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out .lut_mask = 16'h0FF0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y12_N13 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y15_N5 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~54 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~54_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [5]), - .datad(\z80_|reg_file_|b2v_latch_sp_hi|latch [5]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~54_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~54 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[5]~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y11_N1 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~53 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~53_combout = (\z80_|alu_|db[5]~25_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[5]~25_combout & (!\z80_|execute_|ctl_reg_in_hi~12_combout & -// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|alu_|db[5]~25_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~53_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~53 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[5]~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N8 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder_combout = \z80_|reg_file_|gdfx_temp1[5]~57_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y13_N9 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y13_N11 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~51 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~51_combout = (\z80_|reg_file_|b2v_latch_bc_hi|latch [5] & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_hi|latch [5] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc_hi|latch [5]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~51_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~51 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[5]~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y12_N11 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y12_N3 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~52 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~52_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [5] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [5] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [5]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~52_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~52 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[5]~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~55 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~55_combout = (\z80_|reg_file_|gdfx_temp1[5]~54_combout & (\z80_|reg_file_|gdfx_temp1[5]~53_combout & (\z80_|reg_file_|gdfx_temp1[5]~51_combout & \z80_|reg_file_|gdfx_temp1[5]~52_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[5]~54_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[5]~53_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[5]~51_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[5]~52_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~55_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~55 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[5]~55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y13_N9 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y13_N3 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~49 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~49_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datab(\z80_|reg_file_|b2v_latch_de_hi|latch [5]), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~49 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[5]~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N5 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y14_N27 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~50 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~50_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [5]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [5]), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~50 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp1[5]~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y14_N21 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N20 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[5]~14 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[5]~14_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [5]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [5]), - .datad(\z80_|reg_control_|reg_sel_af~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[5]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[5]~14 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[5]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~56 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~56_combout = (\z80_|reg_file_|gdfx_temp1[5]~55_combout & (\z80_|reg_file_|gdfx_temp1[5]~49_combout & (\z80_|reg_file_|gdfx_temp1[5]~50_combout & \z80_|reg_file_|b2v_latch_af_hi|db[5]~14_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[5]~55_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[5]~49_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[5]~50_combout ), - .datad(\z80_|reg_file_|b2v_latch_af_hi|db[5]~14_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~56_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~56 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[5]~56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~57 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~57_combout = ((\z80_|reg_file_|gdfx_temp1[5]~56_combout & ((\z80_|reg_file_|db_hi_as[5]~15_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[5]~56_combout ), - .datac(\z80_|reg_file_|db_hi_as[5]~15_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~57 .lut_mask = 16'hD5DD; -defparam \z80_|reg_file_|gdfx_temp1[5]~57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y15_N1 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[5]~15_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N0 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~13 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[5]~13_combout = (\z80_|reg_control_|reg_sw_4d_hi~0_combout & (\z80_|reg_file_|gdfx_temp1[5]~57_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) - - .dataa(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[5]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[5]~13 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|db_hi_as[5]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N23 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[5]~15_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N16 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~14 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[5]~14_combout = (\z80_|reg_file_|db_hi_as[5]~13_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datab(\z80_|reg_file_|db_hi_as[5]~13_combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [5]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[5]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[5]~14 .lut_mask = 16'hC4C4; -defparam \z80_|reg_file_|db_hi_as[5]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N22 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~15 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[5]~15_combout = ((\z80_|reg_file_|db_hi_as[5]~14_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datad(\z80_|reg_file_|db_hi_as[5]~14_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[5]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[5]~15 .lut_mask = 16'hBF0F; -defparam \z80_|reg_file_|db_hi_as[5]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N2 -cycloneive_lcell_comb \z80_|address_latch_|abusz[13] ( -// Equation(s): -// \z80_|address_latch_|abusz [13] = (\z80_|reg_file_|db_hi_as[5]~15_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(gnd), - .datab(\z80_|reg_file_|db_hi_as[5]~15_combout ), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [13]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[13] .lut_mask = 16'h0C0C; -defparam \z80_|address_latch_|abusz[13] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N22 -cycloneive_lcell_comb \z80_|address_latch_|Q[13]~feeder ( -// Equation(s): -// \z80_|address_latch_|Q[13]~feeder_combout = \z80_|address_latch_|abusz [13] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [13]), - .cin(gnd), - .combout(\z80_|address_latch_|Q[13]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|Q[13]~feeder .lut_mask = 16'hFF00; -defparam \z80_|address_latch_|Q[13]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N23 -dffeas \z80_|address_latch_|Q[13] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|Q[13]~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [13]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[13] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[13] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N6 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout = \z80_|address_latch_|Q [13] $ (\z80_|execute_|ctl_inc_dec~11_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|address_latch_|Q [13]), - .datad(\z80_|execute_|ctl_inc_dec~11_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 .lut_mask = 16'h0FF0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N26 -cycloneive_lcell_comb \z80_|address_latch_|abusz[15] ( -// Equation(s): -// \z80_|address_latch_|abusz [15] = (\z80_|reg_file_|db_hi_as[7]~21_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|reg_file_|db_hi_as[7]~21_combout ), - .datad(\z80_|resets_|clrpc~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [15]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[15] .lut_mask = 16'h00F0; -defparam \z80_|address_latch_|abusz[15] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N27 -dffeas \z80_|address_latch_|Q[15] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [15]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [15]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[15] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[15] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N20 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[14] ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|address [14] = \z80_|address_latch_|Q [14] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout & (\z80_|address_latch_|Q [13] $ (\z80_|execute_|ctl_inc_dec~11_combout ))))) - - .dataa(\z80_|address_latch_|Q [13]), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), - .datac(\z80_|address_latch_|Q [14]), - .datad(\z80_|execute_|ctl_inc_dec~11_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[14] .lut_mask = 16'hB478; -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[14] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N7 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[6]~24_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y13_N11 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y13_N21 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~76 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~76_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~76_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~76 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[6]~76 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y11_N23 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~80 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~80_combout = (\z80_|alu_|db[6]~23_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[6]~23_combout & (!\z80_|execute_|ctl_reg_in_hi~12_combout & -// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|alu_|db[6]~23_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~80_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~80 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[6]~80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y12_N17 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y12_N9 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~79 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~79_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [6] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [6] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [6]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~79_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~79 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[6]~79 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y13_N27 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y13_N29 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~78 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~78_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (\z80_|reg_file_|b2v_latch_bc2_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_bc_hi|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~78_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~78 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[6]~78 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y15_N25 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y12_N7 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~81 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~81_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [6]), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~81_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~81 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[6]~81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~82 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~82_combout = (\z80_|reg_file_|gdfx_temp1[6]~80_combout & (\z80_|reg_file_|gdfx_temp1[6]~79_combout & (\z80_|reg_file_|gdfx_temp1[6]~78_combout & \z80_|reg_file_|gdfx_temp1[6]~81_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[6]~80_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[6]~79_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[6]~78_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[6]~81_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~82_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~82 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[6]~82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N23 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y14_N25 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~77 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~77_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~77_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~77 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[6]~77 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y14_N13 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N12 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[6]~21 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[6]~21_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [6]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [6]), - .datad(\z80_|reg_control_|reg_sel_af~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[6]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[6]~21 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[6]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~83 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~83_combout = (\z80_|reg_file_|gdfx_temp1[6]~76_combout & (\z80_|reg_file_|gdfx_temp1[6]~82_combout & (\z80_|reg_file_|gdfx_temp1[6]~77_combout & \z80_|reg_file_|b2v_latch_af_hi|db[6]~21_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[6]~76_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[6]~82_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[6]~77_combout ), - .datad(\z80_|reg_file_|b2v_latch_af_hi|db[6]~21_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~83_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~83 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[6]~83 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~84 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~84_combout = ((\z80_|reg_file_|gdfx_temp1[6]~83_combout & ((\z80_|reg_file_|db_hi_as[6]~24_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[6]~83_combout ), - .datac(\z80_|reg_file_|db_hi_as[6]~24_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~84 .lut_mask = 16'hD5DD; -defparam \z80_|reg_file_|gdfx_temp1[6]~84 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y15_N19 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[6]~24_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N18 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~22 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[6]~22_combout = (\z80_|reg_control_|reg_sw_4d_hi~0_combout & (\z80_|reg_file_|gdfx_temp1[6]~84_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) - - .dataa(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[6]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[6]~22 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|db_hi_as[6]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N20 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~23 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[6]~23_combout = (\z80_|reg_file_|db_hi_as[6]~22_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|b2v_latch_pc_hi|latch [6]), - .datab(\z80_|reg_file_|db_hi_as[6]~22_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[6]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[6]~23 .lut_mask = 16'h88CC; -defparam \z80_|reg_file_|db_hi_as[6]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N6 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~24 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[6]~24_combout = ((\z80_|reg_file_|db_hi_as[6]~23_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [14]) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), - .datab(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datad(\z80_|reg_file_|db_hi_as[6]~23_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[6]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[6]~24 .lut_mask = 16'hBF33; -defparam \z80_|reg_file_|db_hi_as[6]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N14 -cycloneive_lcell_comb \z80_|address_latch_|abusz[14] ( -// Equation(s): -// \z80_|address_latch_|abusz [14] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[6]~24_combout ) - - .dataa(\z80_|resets_|clrpc~0_combout ), - .datab(gnd), - .datac(\z80_|reg_file_|db_hi_as[6]~24_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [14]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[14] .lut_mask = 16'h5050; -defparam \z80_|address_latch_|abusz[14] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N4 -cycloneive_lcell_comb \z80_|address_latch_|Q[14]~feeder ( -// Equation(s): -// \z80_|address_latch_|Q[14]~feeder_combout = \z80_|address_latch_|abusz [14] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [14]), - .cin(gnd), - .combout(\z80_|address_latch_|Q[14]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|Q[14]~feeder .lut_mask = 16'hFF00; -defparam \z80_|address_latch_|Q[14]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N5 -dffeas \z80_|address_latch_|Q[14] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|Q[14]~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [14]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[14] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[14] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y16_N4 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout = \z80_|address_latch_|Q [14] $ (((\z80_|execute_|ctl_inc_dec~9_combout ) # ((\z80_|execute_|ctl_inc_dec~7_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout )))) - - .dataa(\z80_|execute_|ctl_inc_dec~9_combout ), - .datab(\z80_|address_latch_|Q [14]), - .datac(\z80_|execute_|ctl_inc_dec~6_combout ), - .datad(\z80_|execute_|ctl_inc_dec~7_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16 .lut_mask = 16'h3363; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N12 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[15] ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|address [15] = \z80_|address_latch_|Q [15] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout & -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout )))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), - .datac(\z80_|address_latch_|Q [15]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [15]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[15] .lut_mask = 16'h78F0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[15] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N26 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~21 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[7]~21_combout = ((\z80_|reg_file_|db_hi_as[7]~20_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [15]) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_hi_as[7]~20_combout ), - .datab(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|address [15]), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[7]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[7]~21 .lut_mask = 16'hBB3B; -defparam \z80_|reg_file_|db_hi_as[7]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~75 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~75_combout = ((\z80_|reg_file_|gdfx_temp1[7]~74_combout & ((\z80_|reg_file_|db_hi_as[7]~21_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[7]~74_combout ), - .datac(\z80_|reg_file_|db_hi_as[7]~21_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~75 .lut_mask = 16'hD5DD; -defparam \z80_|reg_file_|gdfx_temp1[7]~75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N6 -cycloneive_lcell_comb \z80_|alu_|db[7]~20 ( -// Equation(s): -// \z80_|alu_|db[7]~20_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[7]~75_combout & ((\z80_|alu_control_|db[7]~18_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & -// (((\z80_|alu_control_|db[7]~18_combout )) # (!\z80_|execute_|ctl_sw_2d~13_combout ))) - - .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datab(\z80_|execute_|ctl_sw_2d~13_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .datad(\z80_|alu_control_|db[7]~18_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[7]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[7]~20 .lut_mask = 16'hF531; -defparam \z80_|alu_|db[7]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N24 -cycloneive_lcell_comb \z80_|alu_|db[7]~21 ( -// Equation(s): -// \z80_|alu_|db[7]~21_combout = ((\z80_|alu_|db[7]~20_combout & ((\z80_|alu_|db_high[3]~8_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~26_combout ) - - .dataa(\z80_|alu_|db[7]~20_combout ), - .datab(\z80_|alu_|db[7]~26_combout ), - .datac(\z80_|alu_|db_high[3]~8_combout ), - .datad(\z80_|execute_|ctl_alu_oe~14_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[7]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[7]~21 .lut_mask = 16'hB3BB; -defparam \z80_|alu_|db[7]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N22 -cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~1 ( -// Equation(s): -// \z80_|alu_control_|b2v_inst_shift_mux|out~1_combout = (\z80_|ir_|opcode [5] & (\z80_|alu_|db[7]~21_combout & ((\z80_|ir_|opcode [3])))) # (!\z80_|ir_|opcode [5] & ((\z80_|ir_|opcode [3] & ((\z80_|alu_|db[0]~19_combout ))) # (!\z80_|ir_|opcode [3] & -// (\z80_|alu_|db[7]~21_combout )))) - - .dataa(\z80_|alu_|db[7]~21_combout ), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|alu_|db[0]~19_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~1 .lut_mask = 16'hB822; -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N4 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~0 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf~0_combout = (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & (\z80_|alu_control_|db[0]~12_combout & (\z80_|execute_|ctl_flags_bus~combout ))) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & -// ((\z80_|execute_|ctl_flags_alu~15_combout ) # ((\z80_|alu_control_|db[0]~12_combout & \z80_|execute_|ctl_flags_bus~combout )))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), - .datab(\z80_|alu_control_|db[0]~12_combout ), - .datac(\z80_|execute_|ctl_flags_bus~combout ), - .datad(\z80_|execute_|ctl_flags_alu~15_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~0 .lut_mask = 16'hD5C0; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~4_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # ((\z80_|execute_|ixy_d~6_combout & \z80_|execute_|ctl_mRead~36_combout ))) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|execute_|ctl_mRead~36_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~4 .lut_mask = 16'hFFF8; -defparam \z80_|execute_|ctl_flags_cf_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~5_combout = ((\z80_|execute_|ctl_flags_cf_we~4_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # (\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ))) # (!\z80_|execute_|ctl_flags_cf_we~7_combout ) - - .dataa(\z80_|execute_|ctl_flags_cf_we~7_combout ), - .datab(\z80_|execute_|ctl_flags_cf_we~4_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .datad(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~5 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_flags_cf_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~3_combout = (\z80_|execute_|ctl_flags_hf2_we~combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((!\z80_|execute_|ctl_flags_bus~5_combout ) # (!\z80_|execute_|ctl_flags_bus~4_combout )))) - - .dataa(\z80_|execute_|ctl_flags_bus~4_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|execute_|ctl_flags_hf2_we~combout ), - .datad(\z80_|execute_|ctl_flags_bus~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~3 .lut_mask = 16'hF4FC; -defparam \z80_|execute_|ctl_flags_cf_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~6_combout = ((\z80_|execute_|ctl_flags_cf_we~5_combout ) # ((\z80_|execute_|ctl_flags_cf_we~3_combout ) # (!\z80_|execute_|ctl_flags_cf_we~2_combout ))) # (!\z80_|execute_|ctl_flags_hf_we~2_combout ) - - .dataa(\z80_|execute_|ctl_flags_hf_we~2_combout ), - .datab(\z80_|execute_|ctl_flags_cf_we~5_combout ), - .datac(\z80_|execute_|ctl_flags_cf_we~3_combout ), - .datad(\z80_|execute_|ctl_flags_cf_we~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~6 .lut_mask = 16'hFDFF; -defparam \z80_|execute_|ctl_flags_cf_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_we~2_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~38_combout ) # (!\z80_|execute_|ctl_alu_op1_sel_bus~7_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_we~2 .lut_mask = 16'hCFFF; -defparam \z80_|execute_|ctl_flags_cf2_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_we~4_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & ((\z80_|pla_decode_|Equal11~0_combout ) # (\z80_|pla_decode_|Equal10~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal11~0_combout ), - .datab(\z80_|pla_decode_|Equal10~0_combout ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_we~4 .lut_mask = 16'hE000; -defparam \z80_|execute_|ctl_flags_cf2_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_we~3_combout = (\z80_|execute_|ctl_flags_cf2_we~2_combout ) # ((\z80_|execute_|ctl_flags_cf2_we~4_combout ) # ((\z80_|sequencer_|DFFE_T3_ff~q & \z80_|execute_|ixy_d~15_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|execute_|ctl_flags_cf2_we~2_combout ), - .datac(\z80_|execute_|ixy_d~15_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_we~3 .lut_mask = 16'hFFEC; -defparam \z80_|execute_|ctl_flags_cf2_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N2 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~1 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf~1_combout = (\z80_|execute_|ctl_flags_cf_we~6_combout & ((\z80_|execute_|ctl_flags_cf2_we~3_combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf~q ))) # (!\z80_|execute_|ctl_flags_cf2_we~3_combout & -// (\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout )))) # (!\z80_|execute_|ctl_flags_cf_we~6_combout & (((\z80_|alu_flags_|DFFE_inst_latch_cf~q )))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ), - .datab(\z80_|execute_|ctl_flags_cf_we~6_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), - .datad(\z80_|execute_|ctl_flags_cf2_we~3_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~1 .lut_mask = 16'hF0B8; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y9_N3 -dffeas \z80_|alu_flags_|DFFE_inst_latch_cf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N0 -cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~0 ( -// Equation(s): -// \z80_|alu_control_|b2v_inst_shift_mux|out~0_combout = (\z80_|ir_|opcode [4] & ((\z80_|ir_|opcode [5] & ((!\z80_|ir_|opcode [3]))) # (!\z80_|ir_|opcode [5] & (\z80_|alu_flags_|DFFE_inst_latch_cf~q )))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~0 .lut_mask = 16'h0A88; -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N4 -cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~2 ( -// Equation(s): -// \z80_|alu_control_|b2v_inst_shift_mux|out~2_combout = (\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ) # ((\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout & !\z80_|ir_|opcode [4])) - - .dataa(\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ), - .datab(\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ), - .datac(gnd), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~2 .lut_mask = 16'hCCEE; -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N14 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~5 ( -// Equation(s): -// \z80_|alu_|db_high[3]~5_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[6]~23_combout ))) - - .dataa(gnd), - .datab(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), - .datac(\z80_|alu_|db[6]~23_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~5 .lut_mask = 16'hCCF0; -defparam \z80_|alu_|db_high[3]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N20 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~6 ( -// Equation(s): -// \z80_|alu_|db_high[3]~6_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_high[3]~5_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[7]~21_combout ))) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .datab(\z80_|alu_|db_high[3]~5_combout ), - .datac(\z80_|alu_|db[7]~21_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~6 .lut_mask = 16'hD8D8; -defparam \z80_|alu_|db_high[3]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N28 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~4 ( -// Equation(s): -// \z80_|alu_|db_high[3]~4_combout = (\z80_|alu_|op2_high [3] & (((\z80_|alu_|op1_high [3])) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout ))) # (!\z80_|alu_|op2_high [3] & (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_high [3]) # -// (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) - - .dataa(\z80_|alu_|op2_high [3]), - .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datac(\z80_|alu_|op1_high [3]), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~4 .lut_mask = 16'hA2F3; -defparam \z80_|alu_|db_high[3]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N30 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~27 ( -// Equation(s): -// \z80_|alu_|db_high[3]~27_combout = ((\z80_|bus_control_|db[4]~19_combout & (\z80_|bus_control_|db[5]~15_combout & \z80_|bus_control_|db[3]~21_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datab(\z80_|bus_control_|db[4]~19_combout ), - .datac(\z80_|bus_control_|db[5]~15_combout ), - .datad(\z80_|bus_control_|db[3]~21_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~27 .lut_mask = 16'hD555; -defparam \z80_|alu_|db_high[3]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N6 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~7 ( -// Equation(s): -// \z80_|alu_|db_high[3]~7_combout = (\z80_|alu_|db_high[3]~4_combout & (\z80_|alu_|db_high[3]~27_combout & ((\z80_|alu_|db_high[3]~6_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) - - .dataa(\z80_|alu_|db_high[3]~6_combout ), - .datab(\z80_|alu_|db_high[3]~4_combout ), - .datac(\z80_|alu_|db_high[3]~27_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~7 .lut_mask = 16'h80C0; -defparam \z80_|alu_|db_high[3]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N28 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~8 ( -// Equation(s): -// \z80_|alu_|db_high[3]~8_combout = ((\z80_|alu_|db_high[3]~7_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) # (!\z80_|alu_|db_high[3]~3_combout ) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), - .datab(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datac(\z80_|alu_|db_high[3]~7_combout ), - .datad(\z80_|alu_|db_high[3]~3_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~8 .lut_mask = 16'hE0FF; -defparam \z80_|alu_|db_high[3]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N14 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & ((\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_low~combout & \z80_|alu_|db_high[3]~8_combout )))) - - .dataa(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .datac(\z80_|alu_|db_high[3]~8_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4 .lut_mask = 16'h00EA; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y10_N15 -dffeas \z80_|alu_|op1_low[3] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_low [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_low[3] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_low[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N0 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~9 ( -// Equation(s): -// \z80_|alu_|db_low[3]~9_combout = (\z80_|alu_|op1_low [3] & (((\z80_|alu_|op2_low [3]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|alu_|op1_low [3] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_low [3]) # -// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) - - .dataa(\z80_|alu_|op1_low [3]), - .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datac(\z80_|alu_|op2_low [3]), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~9 .lut_mask = 16'hB0BB; -defparam \z80_|alu_|db_low[3]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N10 -cycloneive_lcell_comb \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 ( -// Equation(s): -// \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout = (\z80_|bus_control_|db[4]~19_combout & \z80_|bus_control_|db[3]~21_combout ) - - .dataa(gnd), - .datab(\z80_|bus_control_|db[4]~19_combout ), - .datac(gnd), - .datad(\z80_|bus_control_|db[3]~21_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 .lut_mask = 16'hCC00; -defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N24 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~10 ( -// Equation(s): -// \z80_|alu_|db_low[3]~10_combout = (\z80_|alu_|db_low[3]~9_combout & (((!\z80_|bus_control_|db[5]~15_combout & \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout )) # (!\z80_|execute_|ctl_alu_bs_oe~combout ))) - - .dataa(\z80_|bus_control_|db[5]~15_combout ), - .datab(\z80_|alu_|db_low[3]~9_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datad(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~10 .lut_mask = 16'h4C0C; -defparam \z80_|alu_|db_low[3]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y10_N15 -dffeas \z80_|alu_|result_lo[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_alu_op_low~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|result_lo [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|result_lo[3] .is_wysiwyg = "true"; -defparam \z80_|alu_|result_lo[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N14 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~7 ( -// Equation(s): -// \z80_|alu_|db_low[3]~7_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[4]~17_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[2]~15_combout ))) - - .dataa(\z80_|alu_|db[4]~17_combout ), - .datab(gnd), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|alu_|db[2]~15_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~7 .lut_mask = 16'hAFA0; -defparam \z80_|alu_|db_low[3]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N28 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~8 ( -// Equation(s): -// \z80_|alu_|db_low[3]~8_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_low[3]~7_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[3]~11_combout ))) # -// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) - - .dataa(\z80_|alu_|db[3]~11_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datac(\z80_|alu_|db_low[3]~7_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~8 .lut_mask = 16'hF3BB; -defparam \z80_|alu_|db_low[3]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N8 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~11 ( -// Equation(s): -// \z80_|alu_|db_low[3]~11_combout = (\z80_|alu_|db_low[3]~10_combout & (\z80_|alu_|db_low[3]~8_combout & ((\z80_|alu_|result_lo [3]) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) - - .dataa(\z80_|alu_|db_low[3]~10_combout ), - .datab(\z80_|alu_|result_lo [3]), - .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datad(\z80_|alu_|db_low[3]~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~11 .lut_mask = 16'hA800; -defparam \z80_|alu_|db_low[3]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N6 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~25 ( -// Equation(s): -// \z80_|alu_|db_low[3]~25_combout = (\z80_|alu_|db_low[3]~11_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~43_combout & !\z80_|alu_|db_high[3]~2_combout )) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datab(\z80_|alu_|db_high[3]~2_combout ), - .datac(\z80_|alu_|db_low[3]~11_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~25 .lut_mask = 16'hF1F1; -defparam \z80_|alu_|db_low[3]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N12 -cycloneive_lcell_comb \z80_|alu_|db[3]~10 ( -// Equation(s): -// \z80_|alu_|db[3]~10_combout = (\z80_|execute_|ctl_alu_oe~14_combout & (\z80_|alu_|db_low[3]~25_combout & ((\z80_|reg_file_|gdfx_temp1[3]~48_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) # (!\z80_|execute_|ctl_alu_oe~14_combout & -// (((\z80_|reg_file_|gdfx_temp1[3]~48_combout )) # (!\z80_|execute_|ctl_reg_out_hi~7_combout ))) - - .dataa(\z80_|execute_|ctl_alu_oe~14_combout ), - .datab(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .datad(\z80_|alu_|db_low[3]~25_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[3]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[3]~10 .lut_mask = 16'hF351; -defparam \z80_|alu_|db[3]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N12 -cycloneive_lcell_comb \z80_|alu_|db[3]~11 ( -// Equation(s): -// \z80_|alu_|db[3]~11_combout = ((\z80_|alu_|db[3]~10_combout & ((\z80_|alu_control_|db[3]~35_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|alu_|db[7]~26_combout ) - - .dataa(\z80_|alu_|db[3]~10_combout ), - .datab(\z80_|execute_|ctl_sw_2d~13_combout ), - .datac(\z80_|alu_control_|db[3]~35_combout ), - .datad(\z80_|alu_|db[7]~26_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[3]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[3]~11 .lut_mask = 16'hA2FF; -defparam \z80_|alu_|db[3]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~7 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~7_combout = (((\z80_|nM1_int~2_combout & \z80_|execute_|ctl_alu_oe~3_combout )) # (!\z80_|execute_|ctl_reg_out_hi~6_combout )) # (!\z80_|execute_|ctl_alu_oe~9_combout ) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_alu_oe~3_combout ), - .datac(\z80_|execute_|ctl_alu_oe~9_combout ), - .datad(\z80_|execute_|ctl_reg_out_hi~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~7 .lut_mask = 16'h8FFF; -defparam \z80_|execute_|ctl_sw_2u~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|setM1~49 ( -// Equation(s): -// \z80_|execute_|setM1~49_combout = (\z80_|execute_|setM1~48_combout & (!\z80_|pla_decode_|Equal52~1_combout & ((!\z80_|pla_decode_|Equal63~0_combout ) # (!\z80_|pla_decode_|Equal3~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal3~0_combout ), - .datab(\z80_|pla_decode_|Equal63~0_combout ), - .datac(\z80_|execute_|setM1~48_combout ), - .datad(\z80_|pla_decode_|Equal52~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~49 .lut_mask = 16'h0070; -defparam \z80_|execute_|setM1~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_oe~2_combout = (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_state_alu~14_combout ) # ((!\z80_|execute_|ctl_flags_oe~1_combout ) # (!\z80_|execute_|setM1~49_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~14_combout ), - .datab(\z80_|execute_|setM1~49_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|execute_|ctl_flags_oe~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_oe~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_oe~2 .lut_mask = 16'h0B0F; -defparam \z80_|execute_|ctl_flags_oe~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N30 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_35 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout = (\z80_|alu_|db_low[3]~25_combout & ((\z80_|execute_|ctl_flags_alu~15_combout ) # ((\z80_|alu_control_|db[3]~35_combout & \z80_|execute_|ctl_flags_bus~combout )))) # (!\z80_|alu_|db_low[3]~25_combout & -// (\z80_|alu_control_|db[3]~35_combout & (\z80_|execute_|ctl_flags_bus~combout ))) - - .dataa(\z80_|alu_|db_low[3]~25_combout ), - .datab(\z80_|alu_control_|db[3]~35_combout ), - .datac(\z80_|execute_|ctl_flags_bus~combout ), - .datad(\z80_|execute_|ctl_flags_alu~15_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_35 .lut_mask = 16'hEAC0; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~7_combout = (\z80_|execute_|ctl_flags_xy_we~12_combout & !\z80_|execute_|ctl_flags_sz_we~6_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_flags_xy_we~12_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_flags_sz_we~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~7 .lut_mask = 16'h00CC; -defparam \z80_|execute_|ctl_flags_sz_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout = (\z80_|pla_decode_|Equal56~0_combout & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T2_ff~q )) - - .dataa(\z80_|pla_decode_|Equal56~0_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3 .lut_mask = 16'h8080; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~13 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~13_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ) # ((\z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ) # -// (!\z80_|execute_|ctl_flags_xy_we~10_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ), - .datab(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), - .datad(\z80_|execute_|ctl_flags_xy_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~13 .lut_mask = 16'hFEFF; -defparam \z80_|execute_|ctl_flags_xy_we~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~14 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~14_combout = (((\z80_|execute_|ctl_flags_xy_we~13_combout ) # (!\z80_|execute_|ctl_flags_xy_we~7_combout )) # (!\z80_|execute_|ctl_flags_xy_we~9_combout )) # (!\z80_|execute_|ctl_flags_xy_we~16_combout ) - - .dataa(\z80_|execute_|ctl_flags_xy_we~16_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~9_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~13_combout ), - .datad(\z80_|execute_|ctl_flags_xy_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~14 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|ctl_flags_xy_we~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~15 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~15_combout = (((\z80_|execute_|ctl_flags_xy_we~14_combout ) # (!\z80_|execute_|ctl_flags_pf_we~4_combout )) # (!\z80_|execute_|ctl_flags_sz_we~7_combout )) # (!\z80_|execute_|ctl_pf_sel[0]~3_combout ) - - .dataa(\z80_|execute_|ctl_pf_sel[0]~3_combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~7_combout ), - .datac(\z80_|execute_|ctl_flags_pf_we~4_combout ), - .datad(\z80_|execute_|ctl_flags_xy_we~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~15 .lut_mask = 16'hFF7F; -defparam \z80_|execute_|ctl_flags_xy_we~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y11_N31 -dffeas \z80_|alu_flags_|flags_xf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_flags_xy_we~15_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|flags_xf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_xf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|flags_xf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N8 -cycloneive_lcell_comb \z80_|alu_control_|db[3]~33 ( -// Equation(s): -// \z80_|alu_control_|db[3]~33_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & ((\z80_|alu_flags_|flags_xf~q ) # (!\z80_|execute_|ctl_flags_oe~2_combout ))) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_flags_oe~2_combout ), - .datac(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .datad(\z80_|alu_flags_|flags_xf~q ), - .cin(gnd), - .combout(\z80_|alu_control_|db[3]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[3]~33 .lut_mask = 16'hF030; -defparam \z80_|alu_control_|db[3]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~3_combout = (\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ) # ((\z80_|execute_|ctl_reg_out_lo~2_combout & \z80_|execute_|rsel3~combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), - .datab(\z80_|execute_|ctl_reg_out_lo~2_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), - .datad(\z80_|execute_|rsel3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~3 .lut_mask = 16'hFEFA; -defparam \z80_|execute_|ctl_reg_out_lo~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout = (\z80_|pla_decode_|Equal1~7_combout & (\z80_|execute_|ixy_d~7_combout & (!\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal3~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~7_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal3~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~4_combout = (\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ) # ((\z80_|execute_|ixy_d~9_combout & ((\z80_|pla_decode_|Equal40~1_combout ) # (\z80_|pla_decode_|Equal39~0_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ), - .datab(\z80_|pla_decode_|Equal40~1_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~4 .lut_mask = 16'hFAEA; -defparam \z80_|execute_|ctl_reg_out_lo~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~5_combout = (\z80_|execute_|ctl_reg_out_lo~3_combout ) # (((\z80_|execute_|ctl_reg_out_lo~4_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout )) # (!\z80_|execute_|ctl_reg_out_lo~9_combout )) - - .dataa(\z80_|execute_|ctl_reg_out_lo~3_combout ), - .datab(\z80_|execute_|ctl_reg_out_lo~9_combout ), - .datac(\z80_|execute_|ctl_reg_out_lo~4_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~5 .lut_mask = 16'hFBFF; -defparam \z80_|execute_|ctl_reg_out_lo~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~8_combout = ((\z80_|execute_|ctl_reg_out_lo~5_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout )) # (!\z80_|execute_|ctl_reg_out_lo~7_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), - .datad(\z80_|execute_|ctl_reg_out_lo~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~8 .lut_mask = 16'hFF3F; -defparam \z80_|execute_|ctl_reg_out_lo~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N16 -cycloneive_lcell_comb \z80_|sw1_|db_down[3]~1 ( -// Equation(s): -// \z80_|sw1_|db_down[3]~1_combout = (\z80_|bus_control_|db[3]~21_combout ) # ((\z80_|execute_|ctl_sw_1d~6_combout & ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|execute_|ctl_66_oe~2_combout )))) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|execute_|ctl_sw_1d~6_combout ), - .datac(\z80_|execute_|ctl_66_oe~2_combout ), - .datad(\z80_|bus_control_|db[3]~21_combout ), - .cin(gnd), - .combout(\z80_|sw1_|db_down[3]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sw1_|db_down[3]~1 .lut_mask = 16'hFF8C; -defparam \z80_|sw1_|db_down[3]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N10 -cycloneive_lcell_comb \z80_|alu_control_|db[3]~34 ( -// Equation(s): -// \z80_|alu_control_|db[3]~34_combout = (\z80_|alu_control_|db[3]~33_combout & (\z80_|sw1_|db_down[3]~1_combout & ((\z80_|reg_file_|gdfx_temp0[3]~52_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .datab(\z80_|alu_control_|db[3]~33_combout ), - .datac(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datad(\z80_|sw1_|db_down[3]~1_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[3]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[3]~34 .lut_mask = 16'h8C00; -defparam \z80_|alu_control_|db[3]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N0 -cycloneive_lcell_comb \z80_|alu_control_|db[3]~35 ( -// Equation(s): -// \z80_|alu_control_|db[3]~35_combout = ((\z80_|alu_control_|db[3]~34_combout & ((\z80_|alu_|db[3]~11_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|alu_|db[3]~11_combout ), - .datab(\z80_|alu_control_|db[6]~11_combout ), - .datac(\z80_|execute_|ctl_sw_2u~7_combout ), - .datad(\z80_|alu_control_|db[3]~34_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[3]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[3]~35 .lut_mask = 16'hBF33; -defparam \z80_|alu_control_|db[3]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~46 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~46_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [3] & ((\z80_|alu_control_|db[3]~35_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (((\z80_|alu_control_|db[3]~35_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [3]), - .datad(\z80_|alu_control_|db[3]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~46 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[3]~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~47 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~47_combout = (\z80_|reg_file_|gdfx_temp0[3]~46_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(\z80_|reg_file_|b2v_latch_wz_lo|latch [3]), - .datab(gnd), - .datac(\z80_|reg_file_|gdfx_temp0[3]~46_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~47 .lut_mask = 16'hA0F0; -defparam \z80_|reg_file_|gdfx_temp0[3]~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~50 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~50_combout = (\z80_|reg_file_|gdfx_temp0[3]~48_combout & (\z80_|reg_file_|gdfx_temp0[3]~49_combout & \z80_|reg_file_|gdfx_temp0[3]~47_combout )) - - .dataa(gnd), - .datab(\z80_|reg_file_|gdfx_temp0[3]~48_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[3]~49_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[3]~47_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~50 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|gdfx_temp0[3]~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y9_N31 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y9_N5 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~44 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~44_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [3] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [3] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [3]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~44 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[3]~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y13_N7 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y13_N5 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~43 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~43_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [3] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [3] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [3]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~43 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[3]~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~51 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~51_combout = (\z80_|reg_file_|gdfx_temp0[3]~45_combout & (\z80_|reg_file_|gdfx_temp0[3]~50_combout & (\z80_|reg_file_|gdfx_temp0[3]~44_combout & \z80_|reg_file_|gdfx_temp0[3]~43_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[3]~45_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[3]~50_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[3]~44_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[3]~43_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~51 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[3]~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~52 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~52_combout = ((\z80_|reg_file_|gdfx_temp0[3]~51_combout & ((\z80_|reg_file_|db_lo_as[3]~12_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[3]~12_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~52 .lut_mask = 16'h8FCF; -defparam \z80_|reg_file_|gdfx_temp0[3]~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N13 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[3]~12_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N12 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~10 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[3]~10_combout = (\z80_|reg_file_|gdfx_temp0[3]~52_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) # (!\z80_|reg_file_|gdfx_temp0[3]~52_combout & -// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [3]), - .datad(\z80_|execute_|ctl_sw_4d~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[3]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[3]~10 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_lo_as[3]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y17_N3 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[3]~12_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N20 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~11 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[3]~11_combout = (\z80_|reg_file_|db_lo_as[3]~10_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(\z80_|reg_file_|db_lo_as[3]~10_combout ), - .datab(gnd), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [3]), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[3]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[3]~11 .lut_mask = 16'hAA0A; -defparam \z80_|reg_file_|db_lo_as[3]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N2 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~12 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[3]~12_combout = ((\z80_|reg_file_|db_lo_as[3]~11_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datad(\z80_|reg_file_|db_lo_as[3]~11_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[3]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[3]~12 .lut_mask = 16'hBF0F; -defparam \z80_|reg_file_|db_lo_as[3]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N2 -cycloneive_lcell_comb \z80_|address_latch_|abusz[3] ( -// Equation(s): -// \z80_|address_latch_|abusz [3] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[3]~12_combout ) - - .dataa(gnd), - .datab(\z80_|resets_|clrpc~0_combout ), - .datac(\z80_|reg_file_|db_lo_as[3]~12_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [3]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[3] .lut_mask = 16'h3030; -defparam \z80_|address_latch_|abusz[3] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y17_N17 -dffeas \z80_|address_latch_|Q[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|address_latch_|abusz [3]), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[3] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N20 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout = \z80_|address_latch_|Q [3] $ (((\z80_|execute_|ctl_inc_dec~10_combout ) # ((!\z80_|execute_|ctl_inc_dec~5_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) - - .dataa(\z80_|execute_|ctl_inc_dec~10_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .datac(\z80_|execute_|ctl_inc_dec~5_combout ), - .datad(\z80_|address_latch_|Q [3]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4 .lut_mask = 16'h40BF; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N6 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout & -// (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout ))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ), - .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 .lut_mask = 16'h8000; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N12 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout = \z80_|address_latch_|Q [4] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout & -// (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout )))) - - .dataa(\z80_|address_latch_|Q [4]), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ), - .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out .lut_mask = 16'h6AAA; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y13_N27 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y13_N9 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~53 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~53_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [4] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [4] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [4]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~53_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~53 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[4]~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~54 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~54_combout = (\z80_|reg_file_|gdfx_temp0[4]~53_combout & ((\z80_|alu_control_|db[4]~32_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) - - .dataa(\z80_|alu_control_|db[4]~32_combout ), - .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[4]~53_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~54_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~54 .lut_mask = 16'hBB00; -defparam \z80_|reg_file_|gdfx_temp0[4]~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N27 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y10_N1 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~58 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~58_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~58_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~58 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[4]~58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y11_N31 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y11_N23 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y11_N21 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~59 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~59_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_bc_lo|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~59_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~59 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[4]~59 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~60 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~60_combout = (\z80_|reg_file_|gdfx_temp0[4]~58_combout & (\z80_|reg_file_|gdfx_temp0[4]~59_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[4]~58_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [4]), - .datad(\z80_|reg_file_|gdfx_temp0[4]~59_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~60_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~60 .lut_mask = 16'hA200; -defparam \z80_|reg_file_|gdfx_temp0[4]~60 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y9_N21 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y9_N11 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~57 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~57_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (\z80_|reg_file_|b2v_latch_hl2_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (((\z80_|reg_file_|b2v_latch_hl_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~57_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~57 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[4]~57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y10_N1 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y10_N7 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~55 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~55_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datac(\z80_|reg_file_|b2v_latch_iy_lo|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_sp_lo|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~55_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~55 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[4]~55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y11_N21 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~56 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~56_combout = (\z80_|reg_file_|gdfx_temp0[4]~55_combout & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[4]~55_combout ), - .datab(gnd), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~56_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~56 .lut_mask = 16'hA0AA; -defparam \z80_|reg_file_|gdfx_temp0[4]~56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~61 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~61_combout = (\z80_|reg_file_|gdfx_temp0[4]~54_combout & (\z80_|reg_file_|gdfx_temp0[4]~60_combout & (\z80_|reg_file_|gdfx_temp0[4]~57_combout & \z80_|reg_file_|gdfx_temp0[4]~56_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[4]~54_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[4]~60_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[4]~57_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[4]~56_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~61 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[4]~61 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~62 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~62_combout = ((\z80_|reg_file_|gdfx_temp0[4]~61_combout & ((\z80_|reg_file_|db_lo_as[4]~15_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .datac(\z80_|reg_file_|db_lo_as[4]~15_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~62 .lut_mask = 16'hB3BB; -defparam \z80_|reg_file_|gdfx_temp0[4]~62 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N7 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[4]~15_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N6 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~13 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[4]~13_combout = (\z80_|reg_file_|gdfx_temp0[4]~62_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # (!\z80_|reg_file_|gdfx_temp0[4]~62_combout & -// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .datab(\z80_|execute_|ctl_sw_4d~6_combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[4]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[4]~13 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|db_lo_as[4]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y17_N7 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[4]~15_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N12 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~14 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[4]~14_combout = (\z80_|reg_file_|db_lo_as[4]~13_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|db_lo_as[4]~13_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[4]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[4]~14 .lut_mask = 16'hCC0C; -defparam \z80_|reg_file_|db_lo_as[4]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N6 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~15 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[4]~15_combout = ((\z80_|reg_file_|db_lo_as[4]~14_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datad(\z80_|reg_file_|db_lo_as[4]~14_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[4]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[4]~15 .lut_mask = 16'hBF0F; -defparam \z80_|reg_file_|db_lo_as[4]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N16 -cycloneive_lcell_comb \z80_|address_latch_|abusz[4] ( -// Equation(s): -// \z80_|address_latch_|abusz [4] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[4]~15_combout ) - - .dataa(gnd), - .datab(\z80_|resets_|clrpc~0_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|db_lo_as[4]~15_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [4]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[4] .lut_mask = 16'h3300; -defparam \z80_|address_latch_|abusz[4] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y17_N23 -dffeas \z80_|address_latch_|Q[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|address_latch_|abusz [4]), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[4] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N22 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout = \z80_|address_latch_|Q [4] $ (((\z80_|execute_|ctl_inc_dec~9_combout ) # ((\z80_|execute_|ctl_inc_dec~7_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout )))) - - .dataa(\z80_|execute_|ctl_inc_dec~9_combout ), - .datab(\z80_|execute_|ctl_inc_dec~6_combout ), - .datac(\z80_|address_latch_|Q [4]), - .datad(\z80_|execute_|ctl_inc_dec~7_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 .lut_mask = 16'h0F4B; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N28 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout = \z80_|address_latch_|Q [5] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout & \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout -// ))) - - .dataa(\z80_|address_latch_|Q [5]), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out .lut_mask = 16'h6A6A; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y9_N23 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y9_N13 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~64 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~64_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [5] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [5] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [5]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~64_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~64 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[5]~64 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y9_N21 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y9_N23 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~63 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~63_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (\z80_|reg_file_|b2v_latch_de2_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_de_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & ((\z80_|reg_file_|b2v_latch_de_lo|latch [5]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datab(\z80_|reg_file_|b2v_latch_de_lo|latch [5]), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~63_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~63 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[5]~63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y11_N9 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y11_N5 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~66 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~66_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [5] & ((\z80_|alu_control_|db[5]~15_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (((\z80_|alu_control_|db[5]~15_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [5]), - .datad(\z80_|alu_control_|db[5]~15_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~66_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~66 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[5]~66 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~67 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~67_combout = (\z80_|reg_file_|gdfx_temp0[5]~66_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [5]), - .datad(\z80_|reg_file_|gdfx_temp0[5]~66_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~67_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~67 .lut_mask = 16'hF300; -defparam \z80_|reg_file_|gdfx_temp0[5]~67 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N31 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y10_N17 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~65 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~65_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [5]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [5]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~65_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~65 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[5]~65 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y10_N31 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N28 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder_combout = \z80_|reg_file_|gdfx_temp0[5]~72_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y10_N29 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~69 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~69_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [5]), - .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [5]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~69_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~69 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[5]~69 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N6 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder_combout = \z80_|reg_file_|gdfx_temp0[5]~72_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y11_N7 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y11_N3 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~68 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~68_combout = (\z80_|reg_file_|b2v_latch_ix_lo|latch [5] & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # (!\z80_|reg_file_|b2v_latch_ix_lo|latch [5] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_ix_lo|latch [5]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc_lo|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~68_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~68 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[5]~68 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~70 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~70_combout = (\z80_|reg_file_|gdfx_temp0[5]~67_combout & (\z80_|reg_file_|gdfx_temp0[5]~65_combout & (\z80_|reg_file_|gdfx_temp0[5]~69_combout & \z80_|reg_file_|gdfx_temp0[5]~68_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[5]~67_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[5]~65_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[5]~69_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[5]~68_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~70_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~70 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[5]~70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~71 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~71_combout = (\z80_|reg_file_|gdfx_temp0[5]~64_combout & (\z80_|reg_file_|gdfx_temp0[5]~63_combout & \z80_|reg_file_|gdfx_temp0[5]~70_combout )) - - .dataa(\z80_|reg_file_|gdfx_temp0[5]~64_combout ), - .datab(gnd), - .datac(\z80_|reg_file_|gdfx_temp0[5]~63_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[5]~70_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~71 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|gdfx_temp0[5]~71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~72 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~72_combout = ((\z80_|reg_file_|gdfx_temp0[5]~71_combout & ((\z80_|reg_file_|db_lo_as[5]~18_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .datab(\z80_|reg_file_|db_lo_as[5]~18_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~72 .lut_mask = 16'hD5F5; -defparam \z80_|reg_file_|gdfx_temp0[5]~72 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N5 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[5]~18_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N4 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~16 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[5]~16_combout = (\z80_|reg_file_|gdfx_temp0[5]~72_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # (!\z80_|reg_file_|gdfx_temp0[5]~72_combout & -// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .datab(\z80_|execute_|ctl_sw_4d~6_combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[5]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[5]~16 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|db_lo_as[5]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y15_N25 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[5]~18_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N2 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~17 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[5]~17_combout = (\z80_|reg_file_|db_lo_as[5]~16_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datab(gnd), - .datac(\z80_|reg_file_|db_lo_as[5]~16_combout ), - .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [5]), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[5]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[5]~17 .lut_mask = 16'hF050; -defparam \z80_|reg_file_|db_lo_as[5]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N24 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~18 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[5]~18_combout = ((\z80_|reg_file_|db_lo_as[5]~17_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datad(\z80_|reg_file_|db_lo_as[5]~17_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[5]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[5]~18 .lut_mask = 16'hBF0F; -defparam \z80_|reg_file_|db_lo_as[5]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N26 -cycloneive_lcell_comb \z80_|address_latch_|abusz[5] ( -// Equation(s): -// \z80_|address_latch_|abusz [5] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[5]~18_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(\z80_|reg_file_|db_lo_as[5]~18_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [5]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[5] .lut_mask = 16'h0F00; -defparam \z80_|address_latch_|abusz[5] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y16_N27 -dffeas \z80_|address_latch_|Q[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [5]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[5] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N26 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout = \z80_|address_latch_|Q [5] $ ((((\z80_|execute_|ctl_inc_dec~10_combout ) # (!\z80_|execute_|ctl_inc_dec~5_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout ))) - - .dataa(\z80_|address_latch_|Q [5]), - .datab(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .datac(\z80_|execute_|ctl_inc_dec~5_combout ), - .datad(\z80_|execute_|ctl_inc_dec~10_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4 .lut_mask = 16'h5595; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N16 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[6] ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|address [6] = \z80_|address_latch_|Q [6] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout & -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout )))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|address_latch_|Q [6]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[6] .lut_mask = 16'h78F0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[6] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y17_N11 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[6]~21_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y9_N17 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N6 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder_combout = \z80_|reg_file_|gdfx_temp0[6]~82_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y9_N7 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~74 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~74_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (\z80_|reg_file_|b2v_latch_hl2_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (((\z80_|reg_file_|b2v_latch_hl_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~74_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~74 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[6]~74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y9_N19 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y9_N5 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~73 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~73_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (\z80_|reg_file_|b2v_latch_de2_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_de_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & ((\z80_|reg_file_|b2v_latch_de_lo|latch [6]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datab(\z80_|reg_file_|b2v_latch_de_lo|latch [6]), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~73_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~73 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[6]~73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y10_N19 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N2 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder_combout = \z80_|reg_file_|gdfx_temp0[6]~82_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y10_N3 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~78 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~78_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~78_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~78 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[6]~78 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N29 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~79 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~79_combout = (\z80_|reg_file_|b2v_latch_sp_lo|latch [6] & (((\z80_|alu_control_|db[6]~22_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) # (!\z80_|reg_file_|b2v_latch_sp_lo|latch [6] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|alu_control_|db[6]~22_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_sp_lo|latch [6]), - .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datac(\z80_|alu_control_|db[6]~22_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~79_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~79 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[6]~79 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y10_N17 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N16 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder_combout = \z80_|reg_file_|gdfx_temp0[6]~82_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y11_N17 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y11_N19 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~76 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~76_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [6]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [6]), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~76_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~76 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[6]~76 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~77 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~77_combout = (\z80_|reg_file_|gdfx_temp0[6]~76_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [6]), - .datad(\z80_|reg_file_|gdfx_temp0[6]~76_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~77_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~77 .lut_mask = 16'hF300; -defparam \z80_|reg_file_|gdfx_temp0[6]~77 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~80 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~80_combout = (\z80_|reg_file_|gdfx_temp0[6]~78_combout & (\z80_|reg_file_|gdfx_temp0[6]~79_combout & \z80_|reg_file_|gdfx_temp0[6]~77_combout )) - - .dataa(gnd), - .datab(\z80_|reg_file_|gdfx_temp0[6]~78_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[6]~79_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[6]~77_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~80 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|gdfx_temp0[6]~80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N5 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y14_N25 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~75 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~75_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~75_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~75 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[6]~75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~81 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~81_combout = (\z80_|reg_file_|gdfx_temp0[6]~74_combout & (\z80_|reg_file_|gdfx_temp0[6]~73_combout & (\z80_|reg_file_|gdfx_temp0[6]~80_combout & \z80_|reg_file_|gdfx_temp0[6]~75_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[6]~74_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[6]~73_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[6]~75_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~81_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~81 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[6]~81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~82 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~82_combout = ((\z80_|reg_file_|gdfx_temp0[6]~81_combout & ((\z80_|reg_file_|db_lo_as[6]~21_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp0[6]~81_combout ), - .datab(\z80_|reg_file_|db_lo_as[6]~21_combout ), - .datac(\z80_|execute_|ctl_sw_4u~6_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~82 .lut_mask = 16'h8AFF; -defparam \z80_|reg_file_|gdfx_temp0[6]~82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N19 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[6]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N18 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~19 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[6]~19_combout = (\z80_|reg_file_|gdfx_temp0[6]~82_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # (!\z80_|reg_file_|gdfx_temp0[6]~82_combout & -// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .datab(\z80_|execute_|ctl_sw_4d~6_combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[6]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[6]~19 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|db_lo_as[6]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N16 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~20 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[6]~20_combout = (\z80_|reg_file_|db_lo_as[6]~19_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_lo|latch [6]), - .datad(\z80_|reg_file_|db_lo_as[6]~19_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[6]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[6]~20 .lut_mask = 16'hF300; -defparam \z80_|reg_file_|db_lo_as[6]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N10 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~21 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[6]~21_combout = ((\z80_|reg_file_|db_lo_as[6]~20_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [6]) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), - .datac(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datad(\z80_|reg_file_|db_lo_as[6]~20_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[6]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[6]~21 .lut_mask = 16'hDF55; -defparam \z80_|reg_file_|db_lo_as[6]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N22 -cycloneive_lcell_comb \z80_|address_latch_|abusz[6] ( -// Equation(s): -// \z80_|address_latch_|abusz [6] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[6]~21_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(\z80_|reg_file_|db_lo_as[6]~21_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [6]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[6] .lut_mask = 16'h0F00; -defparam \z80_|address_latch_|abusz[6] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y16_N23 -dffeas \z80_|address_latch_|Q[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [6]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[6] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N6 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout = (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|address_latch_|Q [6] $ (((\z80_|execute_|ctl_inc_dec~10_combout ) # (\z80_|execute_|ctl_inc_dec~7_combout ))))) - - .dataa(\z80_|execute_|ctl_inc_dec~10_combout ), - .datab(\z80_|execute_|ctl_inc_dec~7_combout ), - .datac(\z80_|address_latch_|Q [6]), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 .lut_mask = 16'h001E; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N0 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout & -// (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout ))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 .lut_mask = 16'h8000; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N24 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout = \z80_|address_latch_|Q [7] $ (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ) - - .dataa(\z80_|address_latch_|Q [7]), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out .lut_mask = 16'h55AA; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N24 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~24 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[7]~24_combout = ((\z80_|reg_file_|db_lo_as[7]~23_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|reg_file_|db_lo_as[7]~23_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[7]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[7]~24 .lut_mask = 16'hF575; -defparam \z80_|reg_file_|db_lo_as[7]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y9_N25 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y9_N11 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~83 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~83_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (\z80_|reg_file_|b2v_latch_de2_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_de_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & ((\z80_|reg_file_|b2v_latch_de_lo|latch [7]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datab(\z80_|reg_file_|b2v_latch_de_lo|latch [7]), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~83_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~83 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[7]~83 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y9_N29 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y9_N19 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~84 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~84_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (\z80_|reg_file_|b2v_latch_hl2_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (((\z80_|reg_file_|b2v_latch_hl_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~84_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~84 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[7]~84 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y10_N11 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N12 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder_combout = \z80_|reg_file_|gdfx_temp0[7]~92_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y10_N13 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~88 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~88_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~88_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~88 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[7]~88 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y10_N21 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y11_N9 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y11_N7 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~86 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~86_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [7]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [7]), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~86_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~86 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[7]~86 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~87 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~87_combout = (\z80_|reg_file_|gdfx_temp0[7]~86_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [7]), - .datad(\z80_|reg_file_|gdfx_temp0[7]~86_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~87_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~87 .lut_mask = 16'hF300; -defparam \z80_|reg_file_|gdfx_temp0[7]~87 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N25 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y10_N19 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~85 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~85_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~85_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~85 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[7]~85 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N15 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~89 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~89_combout = (\z80_|reg_file_|b2v_latch_sp_lo|latch [7] & (((\z80_|alu_control_|db[7]~18_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) # (!\z80_|reg_file_|b2v_latch_sp_lo|latch [7] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|alu_control_|db[7]~18_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_sp_lo|latch [7]), - .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datac(\z80_|alu_control_|db[7]~18_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~89_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~89 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[7]~89 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~90 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~90_combout = (\z80_|reg_file_|gdfx_temp0[7]~88_combout & (\z80_|reg_file_|gdfx_temp0[7]~87_combout & (\z80_|reg_file_|gdfx_temp0[7]~85_combout & \z80_|reg_file_|gdfx_temp0[7]~89_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[7]~88_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[7]~87_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[7]~85_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[7]~89_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~90 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[7]~90 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~91 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~91_combout = (\z80_|reg_file_|gdfx_temp0[7]~83_combout & (\z80_|reg_file_|gdfx_temp0[7]~84_combout & \z80_|reg_file_|gdfx_temp0[7]~90_combout )) - - .dataa(\z80_|reg_file_|gdfx_temp0[7]~83_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[7]~84_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~91 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|gdfx_temp0[7]~91 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~92 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~92_combout = ((\z80_|reg_file_|gdfx_temp0[7]~91_combout & ((\z80_|reg_file_|db_lo_as[7]~24_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[7]~24_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), - .datac(\z80_|execute_|ctl_sw_4u~6_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~92 .lut_mask = 16'h8CFF; -defparam \z80_|reg_file_|gdfx_temp0[7]~92 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N6 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[7]~0 ( -// Equation(s): -// \z80_|reg_file_|db_lo_ds[7]~0_combout = (\z80_|reg_file_|gdfx_temp0[7]~92_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout & (\z80_|execute_|ctl_reg_out_lo~7_combout & !\z80_|execute_|ctl_reg_out_lo~5_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), - .datab(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .datad(\z80_|execute_|ctl_reg_out_lo~5_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_ds[7]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_ds[7]~0 .lut_mask = 16'hF0F8; -defparam \z80_|reg_file_|db_lo_ds[7]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y10_N11 -dffeas \z80_|interrupts_|im2 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_im_we~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|interrupts_|im2~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|interrupts_|im2 .is_wysiwyg = "true"; -defparam \z80_|interrupts_|im2 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~12 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~12_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|interrupts_|im2~q & \z80_|interrupts_|DFFE_inst44~q )) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(gnd), - .datac(\z80_|interrupts_|im2~q ), - .datad(\z80_|interrupts_|DFFE_inst44~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~12 .lut_mask = 16'h5000; -defparam \z80_|execute_|ctl_mRead~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_mask543_en~0 ( -// Equation(s): -// \z80_|execute_|ctl_sw_mask543_en~0_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (!\z80_|execute_|ctl_mRead~12_combout & \z80_|pla_decode_|Equal47~0_combout ))) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|execute_|ctl_mRead~12_combout ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_mask543_en~0 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_sw_mask543_en~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N12 -cycloneive_lcell_comb \z80_|alu_control_|db[7]~17 ( -// Equation(s): -// \z80_|alu_control_|db[7]~17_combout = (\z80_|reg_file_|db_lo_ds[7]~0_combout & (((!\z80_|execute_|ctl_sw_mask543_en~0_combout & \z80_|bus_control_|db[7]~7_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) - - .dataa(\z80_|reg_file_|db_lo_ds[7]~0_combout ), - .datab(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .datac(\z80_|execute_|ctl_sw_1d~7_combout ), - .datad(\z80_|bus_control_|db[7]~7_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[7]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[7]~17 .lut_mask = 16'h2A0A; -defparam \z80_|alu_control_|db[7]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N16 -cycloneive_lcell_comb \z80_|alu_control_|db[7]~16 ( -// Equation(s): -// \z80_|alu_control_|db[7]~16_combout = (\z80_|execute_|ctl_flags_oe~2_combout & (((\z80_|execute_|ctl_sw_2u~7_combout & !\z80_|alu_|db[7]~21_combout )) # (!\z80_|alu_flags_|DFFE_inst_latch_sf~q ))) # (!\z80_|execute_|ctl_flags_oe~2_combout & -// (\z80_|execute_|ctl_sw_2u~7_combout & (!\z80_|alu_|db[7]~21_combout ))) - - .dataa(\z80_|execute_|ctl_flags_oe~2_combout ), - .datab(\z80_|execute_|ctl_sw_2u~7_combout ), - .datac(\z80_|alu_|db[7]~21_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), - .cin(gnd), - .combout(\z80_|alu_control_|db[7]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[7]~16 .lut_mask = 16'h0CAE; -defparam \z80_|alu_control_|db[7]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N14 -cycloneive_lcell_comb \z80_|alu_control_|db[7]~18 ( -// Equation(s): -// \z80_|alu_control_|db[7]~18_combout = ((\z80_|alu_control_|db[7]~17_combout & (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & !\z80_|alu_control_|db[7]~16_combout ))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|alu_control_|db[7]~17_combout ), - .datab(\z80_|alu_control_|db[6]~11_combout ), - .datac(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .datad(\z80_|alu_control_|db[7]~16_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[7]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[7]~18 .lut_mask = 16'h33B3; -defparam \z80_|alu_control_|db[7]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N8 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_34 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout = (\z80_|execute_|ctl_flags_bus~combout & ((\z80_|alu_control_|db[7]~18_combout ) # ((\z80_|alu_|db_high[3]~8_combout & \z80_|execute_|ctl_flags_alu~15_combout )))) # (!\z80_|execute_|ctl_flags_bus~combout -// & (((\z80_|alu_|db_high[3]~8_combout & \z80_|execute_|ctl_flags_alu~15_combout )))) - - .dataa(\z80_|execute_|ctl_flags_bus~combout ), - .datab(\z80_|alu_control_|db[7]~18_combout ), - .datac(\z80_|alu_|db_high[3]~8_combout ), - .datad(\z80_|execute_|ctl_flags_alu~15_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_34 .lut_mask = 16'hF888; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~8_combout = (((!\z80_|execute_|ctl_flags_sz_we~7_combout ) # (!\z80_|execute_|ctl_flags_sz_we~2_combout )) # (!\z80_|execute_|ctl_flags_sz_we~4_combout )) # (!\z80_|execute_|ctl_flags_sz_we~3_combout ) - - .dataa(\z80_|execute_|ctl_flags_sz_we~3_combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~4_combout ), - .datac(\z80_|execute_|ctl_flags_sz_we~2_combout ), - .datad(\z80_|execute_|ctl_flags_sz_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~8 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_flags_sz_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y9_N9 -dffeas \z80_|alu_flags_|DFFE_inst_latch_sf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_flags_sz_we~8_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_sf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_sf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N26 -cycloneive_lcell_comb \z80_|pla_decode_|Equal62~3 ( -// Equation(s): -// \z80_|pla_decode_|Equal62~3_combout = (\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [3] & \z80_|execute_|ctl_state_alu~12_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|execute_|ctl_state_alu~12_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal62~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal62~3 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal62~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~5_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal62~3_combout ) # ((\z80_|execute_|ctl_mWrite~16_combout ) # (\z80_|pla_decode_|Equal11~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal62~3_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_mWrite~16_combout ), - .datad(\z80_|pla_decode_|Equal11~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~5 .lut_mask = 16'hCCC8; -defparam \z80_|execute_|ctl_flags_pf_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~6_combout = (\z80_|pla_decode_|Equal69~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|pla_decode_|Equal69~0_combout ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~6 .lut_mask = 16'h008C; -defparam \z80_|execute_|ctl_flags_pf_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~7_combout = (\z80_|execute_|ctl_flags_pf_we~6_combout ) # ((\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # ((\z80_|nM1_int~2_combout & \z80_|execute_|ctl_mRead~36_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_mRead~36_combout ), - .datac(\z80_|execute_|ctl_flags_pf_we~6_combout ), - .datad(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~7 .lut_mask = 16'hFFF8; -defparam \z80_|execute_|ctl_flags_pf_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~8_combout = (((\z80_|execute_|ctl_flags_pf_we~5_combout ) # (\z80_|execute_|ctl_flags_pf_we~7_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~46_combout )) # (!\z80_|execute_|ctl_flags_pf_we~3_combout ) - - .dataa(\z80_|execute_|ctl_flags_pf_we~3_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~46_combout ), - .datac(\z80_|execute_|ctl_flags_pf_we~5_combout ), - .datad(\z80_|execute_|ctl_flags_pf_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~8 .lut_mask = 16'hFFF7; -defparam \z80_|execute_|ctl_flags_pf_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~9_combout = ((\z80_|execute_|ctl_flags_pf_we~8_combout ) # ((!\z80_|execute_|ctl_pf_sel[0]~3_combout ) # (!\z80_|execute_|ctl_flags_pf_we~4_combout ))) # (!\z80_|execute_|ctl_flags_xy_we~11_combout ) - - .dataa(\z80_|execute_|ctl_flags_xy_we~11_combout ), - .datab(\z80_|execute_|ctl_flags_pf_we~8_combout ), - .datac(\z80_|execute_|ctl_flags_pf_we~4_combout ), - .datad(\z80_|execute_|ctl_pf_sel[0]~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~9 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_flags_pf_we~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N10 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~0 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~0_combout = (\z80_|execute_|ctl_flags_pf_we~9_combout & (\z80_|execute_|ctl_flags_bus~combout & (\z80_|alu_control_|db[2]~29_combout ))) # (!\z80_|execute_|ctl_flags_pf_we~9_combout & -// (((\z80_|alu_flags_|DFFE_inst_latch_pf~q )))) - - .dataa(\z80_|execute_|ctl_flags_bus~combout ), - .datab(\z80_|alu_control_|db[2]~29_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), - .datad(\z80_|execute_|ctl_flags_pf_we~9_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~0 .lut_mask = 16'h88F0; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N22 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~4 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~4_combout = (\z80_|execute_|ctl_pf_sel[0]~2_combout & (((!\z80_|pla_decode_|Equal62~3_combout & !\z80_|execute_|ctl_alu_op_low~13_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal62~3_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_pf_sel[0]~2_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~13_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~4 .lut_mask = 16'h3070; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N28 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~5 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~5_combout = (\z80_|execute_|ctl_pf_sel[0]~3_combout & (!\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout $ -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout )))) # (!\z80_|execute_|ctl_pf_sel[0]~3_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout $ (((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ))))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), - .datab(\z80_|execute_|ctl_pf_sel[0]~3_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~5 .lut_mask = 16'h152A; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N26 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~6 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~6_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout & (((\z80_|execute_|ctl_flags_bus~5_combout & !\z80_|pla_decode_|Equal69~0_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|pla_decode_|Equal69~0_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~6 .lut_mask = 16'h3B00; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~6 .sum_lutc_input = "datac"; +defparam \z80_|decode_state_|in_halt~0 .lut_mask = 16'h0500; +defparam \z80_|decode_state_|in_halt~0 .sum_lutc_input = "datac"; // synopsys translate_on // Location: LCCOMB_X28_Y16_N24 -cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~0 ( +cycloneive_lcell_comb \z80_|decode_state_|in_halt~1 ( // Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~0_combout = (!\z80_|address_latch_|Q [14] & (!\z80_|address_latch_|Q [12] & (!\z80_|address_latch_|Q [15] & !\z80_|address_latch_|Q [13]))) +// \z80_|decode_state_|in_halt~1_combout = (\z80_|decode_state_|in_halt~0_combout ) # ((\z80_|pla_decode_|Equal77~1_combout & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & !\z80_|decode_state_|in_halt~q ))) - .dataa(\z80_|address_latch_|Q [14]), - .datab(\z80_|address_latch_|Q [12]), - .datac(\z80_|address_latch_|Q [15]), - .datad(\z80_|address_latch_|Q [13]), + .dataa(\z80_|pla_decode_|Equal77~1_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|decode_state_|in_halt~q ), + .datad(\z80_|decode_state_|in_halt~0_combout ), .cin(gnd), - .combout(\z80_|decode_state_|DFFE_instNonRep~0_combout ), + .combout(\z80_|decode_state_|in_halt~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep~0 .lut_mask = 16'h0001; -defparam \z80_|decode_state_|DFFE_instNonRep~0 .sum_lutc_input = "datac"; +defparam \z80_|decode_state_|in_halt~1 .lut_mask = 16'hFF08; +defparam \z80_|decode_state_|in_halt~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y17_N16 -cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~3 ( -// Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~3_combout = (!\z80_|address_latch_|Q [1] & (\z80_|address_latch_|Q [0] & (!\z80_|address_latch_|Q [3] & !\z80_|address_latch_|Q [2]))) - - .dataa(\z80_|address_latch_|Q [1]), - .datab(\z80_|address_latch_|Q [0]), - .datac(\z80_|address_latch_|Q [3]), - .datad(\z80_|address_latch_|Q [2]), - .cin(gnd), - .combout(\z80_|decode_state_|DFFE_instNonRep~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep~3 .lut_mask = 16'h0004; -defparam \z80_|decode_state_|DFFE_instNonRep~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N14 -cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~2 ( -// Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~2_combout = (!\z80_|address_latch_|Q [7] & (!\z80_|address_latch_|Q [6] & (!\z80_|address_latch_|Q [5] & !\z80_|address_latch_|Q [4]))) - - .dataa(\z80_|address_latch_|Q [7]), - .datab(\z80_|address_latch_|Q [6]), - .datac(\z80_|address_latch_|Q [5]), - .datad(\z80_|address_latch_|Q [4]), - .cin(gnd), - .combout(\z80_|decode_state_|DFFE_instNonRep~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep~2 .lut_mask = 16'h0001; -defparam \z80_|decode_state_|DFFE_instNonRep~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N8 -cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~1 ( -// Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~1_combout = (!\z80_|address_latch_|Q [10] & (!\z80_|address_latch_|Q [11] & (!\z80_|address_latch_|Q [9] & !\z80_|address_latch_|Q [8]))) - - .dataa(\z80_|address_latch_|Q [10]), - .datab(\z80_|address_latch_|Q [11]), - .datac(\z80_|address_latch_|Q [9]), - .datad(\z80_|address_latch_|Q [8]), - .cin(gnd), - .combout(\z80_|decode_state_|DFFE_instNonRep~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep~1 .lut_mask = 16'h0001; -defparam \z80_|decode_state_|DFFE_instNonRep~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N18 -cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~4 ( -// Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~4_combout = (\z80_|decode_state_|DFFE_instNonRep~0_combout & (\z80_|decode_state_|DFFE_instNonRep~3_combout & (\z80_|decode_state_|DFFE_instNonRep~2_combout & \z80_|decode_state_|DFFE_instNonRep~1_combout ))) - - .dataa(\z80_|decode_state_|DFFE_instNonRep~0_combout ), - .datab(\z80_|decode_state_|DFFE_instNonRep~3_combout ), - .datac(\z80_|decode_state_|DFFE_instNonRep~2_combout ), - .datad(\z80_|decode_state_|DFFE_instNonRep~1_combout ), - .cin(gnd), - .combout(\z80_|decode_state_|DFFE_instNonRep~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep~4 .lut_mask = 16'h8000; -defparam \z80_|decode_state_|DFFE_instNonRep~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N16 -cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~5 ( -// Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~5_combout = (\z80_|execute_|ctl_flags_bus~5_combout & (((\z80_|decode_state_|DFFE_instNonRep~q )))) # (!\z80_|execute_|ctl_flags_bus~5_combout & ((\z80_|execute_|ixy_d~9_combout & -// ((\z80_|decode_state_|DFFE_instNonRep~4_combout ))) # (!\z80_|execute_|ixy_d~9_combout & (\z80_|decode_state_|DFFE_instNonRep~q )))) - - .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|decode_state_|DFFE_instNonRep~q ), - .datad(\z80_|decode_state_|DFFE_instNonRep~4_combout ), - .cin(gnd), - .combout(\z80_|decode_state_|DFFE_instNonRep~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep~5 .lut_mask = 16'hF4B0; -defparam \z80_|decode_state_|DFFE_instNonRep~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y16_N17 -dffeas \z80_|decode_state_|DFFE_instNonRep ( +// Location: FF_X28_Y16_N25 +dffeas \z80_|decode_state_|in_halt ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|decode_state_|DFFE_instNonRep~5_combout ), + .d(\z80_|decode_state_|in_halt~1_combout ), .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), @@ -33642,7153 +6250,203 @@ dffeas \z80_|decode_state_|DFFE_instNonRep ( .ena(vcc), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|decode_state_|DFFE_instNonRep~q ), + .q(\z80_|decode_state_|in_halt~q ), .prn(vcc)); // synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep .is_wysiwyg = "true"; -defparam \z80_|decode_state_|DFFE_instNonRep .power_up = "low"; +defparam \z80_|decode_state_|in_halt .is_wysiwyg = "true"; +defparam \z80_|decode_state_|in_halt .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y16_N12 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~1 ( +// Location: LCCOMB_X28_Y16_N8 +cycloneive_lcell_comb \z80_|pla_decode_|Equal50~0 ( // Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~1_combout = (!\z80_|pla_decode_|Equal62~3_combout & (\z80_|execute_|ctl_pf_sel[0]~3_combout & (\z80_|execute_|ctl_pf_sel[0]~2_combout & !\z80_|execute_|ctl_alu_op_low~13_combout ))) - - .dataa(\z80_|pla_decode_|Equal62~3_combout ), - .datab(\z80_|execute_|ctl_pf_sel[0]~3_combout ), - .datac(\z80_|execute_|ctl_pf_sel[0]~2_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~13_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~1 .lut_mask = 16'h0040; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N10 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~2 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~2_combout = (\z80_|pla_decode_|Equal69~0_combout & ((\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout & (\z80_|interrupts_|DFFE_instIFF2~q )) # (!\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout & -// ((!\z80_|decode_state_|DFFE_instNonRep~q ))))) - - .dataa(\z80_|interrupts_|DFFE_instIFF2~q ), - .datab(\z80_|decode_state_|DFFE_instNonRep~q ), - .datac(\z80_|pla_decode_|Equal69~0_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~2 .lut_mask = 16'hA030; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N24 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~3 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~3_combout = (\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_flags_bus~5_combout & (\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout )) # (!\z80_|execute_|ctl_flags_bus~5_combout & -// ((!\z80_|decode_state_|DFFE_instNonRep~q ))))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_flags_bus~5_combout ), - .datad(\z80_|decode_state_|DFFE_instNonRep~q ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~3 .lut_mask = 16'h808C; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y10_N23 -dffeas \z80_|alu_control_|DFFE_latch_pf_tmp ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|alu_parity_out~combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_alu_op_low~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_control_|DFFE_latch_pf_tmp~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_control_|DFFE_latch_pf_tmp .is_wysiwyg = "true"; -defparam \z80_|alu_control_|DFFE_latch_pf_tmp .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N16 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ) # -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout )))) # (!\z80_|execute_|ctl_alu_core_R~5_combout ) - - .dataa(\z80_|execute_|ctl_alu_core_R~5_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 .lut_mask = 16'h55FD; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N22 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout = (\z80_|alu_|alu_op2[1]~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout & -// \z80_|alu_|alu_op1[1]~0_combout )))) # (!\z80_|alu_|alu_op2[1]~1_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_|alu_op1[1]~0_combout ) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout )))) - - .dataa(\z80_|alu_|alu_op2[1]~1_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), - .datac(\z80_|alu_|alu_op1[1]~0_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 .lut_mask = 16'hFB20; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N28 -cycloneive_lcell_comb \z80_|alu_|alu_parity_out~0 ( -// Equation(s): -// \z80_|alu_|alu_parity_out~0_combout = \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout $ (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout $ (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout )) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), - .datab(gnd), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_parity_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_parity_out~0 .lut_mask = 16'hA55A; -defparam \z80_|alu_|alu_parity_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N22 -cycloneive_lcell_comb \z80_|alu_|alu_parity_out ( -// Equation(s): -// \z80_|alu_|alu_parity_out~combout = \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout $ (\z80_|alu_|alu_parity_out~0_combout $ (((\z80_|execute_|ctl_alu_op_low~combout ) # (\z80_|alu_control_|DFFE_latch_pf_tmp~q )))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~combout ), - .datac(\z80_|alu_control_|DFFE_latch_pf_tmp~q ), - .datad(\z80_|alu_|alu_parity_out~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_parity_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_parity_out .lut_mask = 16'hA956; -defparam \z80_|alu_|alu_parity_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N20 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~7 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~7_combout = (\z80_|pla_decode_|Equal62~3_combout ) # ((\z80_|pla_decode_|Equal69~0_combout ) # ((\z80_|execute_|ctl_alu_op_low~13_combout ) # (!\z80_|execute_|ctl_flags_bus~5_combout ))) - - .dataa(\z80_|pla_decode_|Equal62~3_combout ), - .datab(\z80_|pla_decode_|Equal69~0_combout ), - .datac(\z80_|execute_|ctl_flags_bus~5_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~13_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~7 .lut_mask = 16'hFFEF; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N2 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~8 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~8_combout = (\z80_|execute_|ctl_pf_sel[0]~2_combout & (\z80_|execute_|ctl_pf_sel[0]~3_combout & ((!\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ) # (!\z80_|nM1_int~2_combout )))) - - .dataa(\z80_|execute_|ctl_pf_sel[0]~2_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_pf_sel[0]~3_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~8 .lut_mask = 16'h20A0; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N4 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~9 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~9_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ) # ((\z80_|alu_|alu_parity_out~combout & \z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ), - .datac(\z80_|alu_|alu_parity_out~combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~9 .lut_mask = 16'hFEEE; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N14 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~10 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~10_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ) # ((\z80_|execute_|ctl_flags_pf_we~9_combout & (\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout & \z80_|execute_|ctl_flags_alu~15_combout ))) - - .dataa(\z80_|execute_|ctl_flags_pf_we~9_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ), - .datad(\z80_|execute_|ctl_flags_alu~15_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~10 .lut_mask = 16'hECCC; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y11_N15 -dffeas \z80_|alu_flags_|DFFE_inst_latch_pf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|DFFE_inst_latch_pf~10_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N14 -cycloneive_lcell_comb \z80_|alu_control_|sel[1]~0 ( -// Equation(s): -// \z80_|alu_control_|sel[1]~0_combout = (\z80_|ir_|opcode [5] & (((!\z80_|pla_decode_|Equal40~0_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal40~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|sel[1]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|sel[1]~0 .lut_mask = 16'h70F0; -defparam \z80_|alu_control_|sel[1]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N18 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout = (!\z80_|alu_|db_high[1]~20_combout & (!\z80_|alu_|db_high[3]~8_combout & (!\z80_|alu_|db_high[2]~14_combout & !\z80_|alu_|db_high[0]~26_combout ))) - - .dataa(\z80_|alu_|db_high[1]~20_combout ), - .datab(\z80_|alu_|db_high[3]~8_combout ), - .datac(\z80_|alu_|db_high[2]~14_combout ), - .datad(\z80_|alu_|db_high[0]~26_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2 .lut_mask = 16'h0001; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N4 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_12 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout = (\z80_|alu_control_|db[6]~22_combout & \z80_|execute_|ctl_flags_bus~combout ) - - .dataa(\z80_|alu_control_|db[6]~22_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|execute_|ctl_flags_bus~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_12 .lut_mask = 16'hAA00; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N14 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout = (!\z80_|alu_|db_low[3]~11_combout & (\z80_|alu_|db_high[3]~3_combout & ((!\z80_|alu_|db_low[2]~3_combout ) # (!\z80_|alu_|db_low[2]~6_combout )))) - - .dataa(\z80_|alu_|db_low[2]~6_combout ), - .datab(\z80_|alu_|db_low[3]~11_combout ), - .datac(\z80_|alu_|db_low[2]~3_combout ), - .datad(\z80_|alu_|db_high[3]~3_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 .lut_mask = 16'h1300; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N8 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout = (!\z80_|alu_|db_low[1]~17_combout & (\z80_|execute_|ctl_flags_alu~15_combout & (!\z80_|alu_|db_low[0]~23_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ))) - - .dataa(\z80_|alu_|db_low[1]~17_combout ), - .datab(\z80_|execute_|ctl_flags_alu~15_combout ), - .datac(\z80_|alu_|db_low[0]~23_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 .lut_mask = 16'h0400; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N2 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout = (((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ) # (!\z80_|execute_|ixy_d~7_combout )) # (!\z80_|pla_decode_|Equal13~0_combout )) # (!\z80_|pla_decode_|Equal55~0_combout ) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 .lut_mask = 16'hF7FF; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N26 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout & ((\z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout )))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 .lut_mask = 16'hEC00; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y13_N27 -dffeas \z80_|alu_flags_|SYNTHESIZED_WIRE_39 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_flags_sz_we~8_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_39 .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_39 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N28 -cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_cond_mux|out~0 ( -// Equation(s): -// \z80_|alu_control_|b2v_inst_cond_mux|out~0_combout = (\z80_|alu_control_|sel[1]~0_combout & (((\z80_|ir_|opcode [4])))) # (!\z80_|alu_control_|sel[1]~0_combout & ((\z80_|ir_|opcode [4] & ((\z80_|alu_flags_|flags_cf~combout ))) # (!\z80_|ir_|opcode [4] -// & (\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q )))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .datab(\z80_|alu_flags_|flags_cf~combout ), - .datac(\z80_|alu_control_|sel[1]~0_combout ), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|b2v_inst_cond_mux|out~0 .lut_mask = 16'hFC0A; -defparam \z80_|alu_control_|b2v_inst_cond_mux|out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N18 -cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_cond_mux|out~1 ( -// Equation(s): -// \z80_|alu_control_|b2v_inst_cond_mux|out~1_combout = (\z80_|alu_control_|sel[1]~0_combout & ((\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout & (\z80_|alu_flags_|DFFE_inst_latch_sf~q )) # (!\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout & -// ((\z80_|alu_flags_|DFFE_inst_latch_pf~q ))))) # (!\z80_|alu_control_|sel[1]~0_combout & (((\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout )))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), - .datac(\z80_|alu_control_|sel[1]~0_combout ), - .datad(\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|b2v_inst_cond_mux|out~1 .lut_mask = 16'hAFC0; -defparam \z80_|alu_control_|b2v_inst_cond_mux|out~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N20 -cycloneive_lcell_comb \z80_|alu_control_|flags_cond_true~0 ( -// Equation(s): -// \z80_|alu_control_|flags_cond_true~0_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|ir_|opcode [3] $ (((!\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ))))) # (!\z80_|execute_|ctl_eval_cond~0_combout & -// (((\z80_|alu_control_|flags_cond_true~q )))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|alu_control_|flags_cond_true~q ), - .datad(\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|flags_cond_true~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|flags_cond_true~0 .lut_mask = 16'hB874; -defparam \z80_|alu_control_|flags_cond_true~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y11_N21 -dffeas \z80_|alu_control_|flags_cond_true ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_control_|flags_cond_true~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_control_|flags_cond_true~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_control_|flags_cond_true .is_wysiwyg = "true"; -defparam \z80_|alu_control_|flags_cond_true .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~13 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~13_combout = (((!\z80_|pla_decode_|Equal35~0_combout & !\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|execute_|ixy_d~6_combout )) # (!\z80_|alu_control_|flags_cond_true~q ) - - .dataa(\z80_|pla_decode_|Equal35~0_combout ), - .datab(\z80_|alu_control_|flags_cond_true~q ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|pla_decode_|Equal34~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~13 .lut_mask = 16'h3F7F; -defparam \z80_|execute_|ctl_reg_sel_wz~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~14 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~14_combout = (((\z80_|execute_|ctl_66_oe~2_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~13_combout )) # (!\z80_|execute_|ctl_reg_in_hi~5_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~12_combout ) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~12_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~5_combout ), - .datac(\z80_|execute_|ctl_66_oe~2_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~14 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|ctl_reg_sel_wz~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~17 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~17_combout = (\z80_|execute_|ctl_reg_sel_wz~14_combout ) # (((!\z80_|execute_|ctl_reg_sel_wz~16_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~19_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~11_combout )) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~14_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~11_combout ), - .datac(\z80_|execute_|ctl_reg_sel_wz~19_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~17 .lut_mask = 16'hBFFF; -defparam \z80_|execute_|ctl_reg_sel_wz~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N16 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_82 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_82~combout = (\z80_|execute_|ctl_reg_sel_wz~17_combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout & !\z80_|reg_control_|reg_sys_we_lo~combout )) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~17_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .datac(gnd), - .datad(\z80_|reg_control_|reg_sys_we_lo~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_82 .lut_mask = 16'h0088; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~18 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~18_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~18 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp0[0]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y12_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~20 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~20_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ) # ((\z80_|reg_file_|gdfx_temp0[0]~19_combout ) # ((\z80_|reg_file_|gdfx_temp0[0]~18_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~19_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[0]~18_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~20 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp0[0]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~21 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~21_combout = (\z80_|reg_file_|gdfx_temp0[0]~93_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ) # ((\z80_|reg_file_|gdfx_temp0[0]~20_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[0]~93_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .datac(\z80_|reg_file_|gdfx_temp0[0]~20_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~21 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp0[0]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y10_N23 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X31_Y10_N27 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~28 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~28_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datab(\z80_|reg_file_|b2v_latch_iy_lo|latch [1]), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~28 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp0[1]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y10_N25 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y11_N13 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y12_N25 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~26 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~26_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [1]), - .datad(\z80_|reg_file_|b2v_latch_bc_lo|latch [1]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~26 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[1]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~27 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~27_combout = (\z80_|reg_file_|gdfx_temp0[1]~26_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) +// \z80_|pla_decode_|Equal50~0_combout = (!\z80_|decode_state_|in_halt~q & (\z80_|pla_decode_|Equal33~1_combout & \z80_|pla_decode_|Equal77~0_combout )) .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [1]), - .datad(\z80_|reg_file_|gdfx_temp0[1]~26_combout ), + .datab(\z80_|decode_state_|in_halt~q ), + .datac(\z80_|pla_decode_|Equal33~1_combout ), + .datad(\z80_|pla_decode_|Equal77~0_combout ), .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~27_combout ), + .combout(\z80_|pla_decode_|Equal50~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~27 .lut_mask = 16'hF300; -defparam \z80_|reg_file_|gdfx_temp0[1]~27 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal50~0 .lut_mask = 16'h3000; +defparam \z80_|pla_decode_|Equal50~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y10_N17 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~29 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~29_combout = (\z80_|reg_file_|b2v_latch_sp_lo|latch [1] & (((\z80_|alu_control_|db[1]~26_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) # (!\z80_|reg_file_|b2v_latch_sp_lo|latch [1] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|alu_control_|db[1]~26_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_sp_lo|latch [1]), - .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datac(\z80_|alu_control_|db[1]~26_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~29 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[1]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N3 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N8 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout = \z80_|reg_file_|gdfx_temp0[1]~32_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N9 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~25 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~25_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [1]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [1]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~25 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[1]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~30 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~30_combout = (\z80_|reg_file_|gdfx_temp0[1]~28_combout & (\z80_|reg_file_|gdfx_temp0[1]~27_combout & (\z80_|reg_file_|gdfx_temp0[1]~29_combout & \z80_|reg_file_|gdfx_temp0[1]~25_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[1]~28_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[1]~27_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[1]~29_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[1]~25_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~30 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[1]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N26 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder_combout = \z80_|reg_file_|gdfx_temp0[1]~32_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y9_N27 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y9_N25 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~24 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~24_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [1] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [1] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [1]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~24 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[1]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y13_N23 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y13_N25 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~23 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~23_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [1] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [1] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [1]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~23 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[1]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~31 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~31_combout = (\z80_|reg_file_|gdfx_temp0[1]~30_combout & (\z80_|reg_file_|gdfx_temp0[1]~24_combout & \z80_|reg_file_|gdfx_temp0[1]~23_combout )) - - .dataa(\z80_|reg_file_|gdfx_temp0[1]~30_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[1]~24_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[1]~23_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~31 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|gdfx_temp0[1]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~32 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~32_combout = ((\z80_|reg_file_|gdfx_temp0[1]~31_combout & ((\z80_|reg_file_|db_lo_as[1]~6_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .datac(\z80_|reg_file_|db_lo_as[1]~6_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[1]~31_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~32 .lut_mask = 16'hF733; -defparam \z80_|reg_file_|gdfx_temp0[1]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N12 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[1]~1 ( -// Equation(s): -// \z80_|reg_file_|db_lo_ds[1]~1_combout = (\z80_|reg_file_|gdfx_temp0[1]~32_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout & (\z80_|execute_|ctl_reg_out_lo~7_combout & !\z80_|execute_|ctl_reg_out_lo~5_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), - .datab(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .datad(\z80_|execute_|ctl_reg_out_lo~5_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_ds[1]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_ds[1]~1 .lut_mask = 16'hF0F8; -defparam \z80_|reg_file_|db_lo_ds[1]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N30 -cycloneive_lcell_comb \z80_|alu_control_|db[1]~25 ( -// Equation(s): -// \z80_|alu_control_|db[1]~25_combout = (\z80_|reg_file_|db_lo_ds[1]~1_combout & (((\z80_|bus_control_|db[1]~11_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) - - .dataa(\z80_|bus_control_|db[1]~11_combout ), - .datab(\z80_|reg_file_|db_lo_ds[1]~1_combout ), - .datac(\z80_|execute_|ctl_sw_1d~7_combout ), - .datad(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[1]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[1]~25 .lut_mask = 16'h0C8C; -defparam \z80_|alu_control_|db[1]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N28 -cycloneive_lcell_comb \z80_|alu_control_|db[1]~24 ( -// Equation(s): -// \z80_|alu_control_|db[1]~24_combout = (\z80_|execute_|ctl_flags_oe~2_combout & (((\z80_|execute_|ctl_sw_2u~7_combout & !\z80_|alu_|db[1]~13_combout )) # (!\z80_|alu_flags_|DFFE_inst_latch_nf~q ))) # (!\z80_|execute_|ctl_flags_oe~2_combout & -// (\z80_|execute_|ctl_sw_2u~7_combout & ((!\z80_|alu_|db[1]~13_combout )))) - - .dataa(\z80_|execute_|ctl_flags_oe~2_combout ), - .datab(\z80_|execute_|ctl_sw_2u~7_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .datad(\z80_|alu_|db[1]~13_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[1]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[1]~24 .lut_mask = 16'h0ACE; -defparam \z80_|alu_control_|db[1]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N20 -cycloneive_lcell_comb \z80_|alu_control_|db[1]~26 ( -// Equation(s): -// \z80_|alu_control_|db[1]~26_combout = ((\z80_|alu_control_|db[1]~25_combout & (\z80_|alu_control_|db[2]~23_combout & !\z80_|alu_control_|db[1]~24_combout ))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|alu_control_|db[1]~25_combout ), - .datab(\z80_|alu_control_|db[2]~23_combout ), - .datac(\z80_|alu_control_|db[6]~11_combout ), - .datad(\z80_|alu_control_|db[1]~24_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[1]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[1]~26 .lut_mask = 16'h0F8F; -defparam \z80_|alu_control_|db[1]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N22 -cycloneive_lcell_comb \z80_|alu_|db[1]~12 ( -// Equation(s): -// \z80_|alu_|db[1]~12_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[1]~21_combout & ((\z80_|alu_control_|db[1]~26_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & -// ((\z80_|alu_control_|db[1]~26_combout ) # ((!\z80_|execute_|ctl_sw_2d~13_combout )))) - - .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datab(\z80_|alu_control_|db[1]~26_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .datad(\z80_|execute_|ctl_sw_2d~13_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[1]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[1]~12 .lut_mask = 16'hC4F5; -defparam \z80_|alu_|db[1]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N8 -cycloneive_lcell_comb \z80_|alu_|db[1]~13 ( -// Equation(s): -// \z80_|alu_|db[1]~13_combout = ((\z80_|alu_|db[1]~12_combout & ((\z80_|alu_|db_low[1]~17_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~26_combout ) - - .dataa(\z80_|alu_|db[1]~12_combout ), - .datab(\z80_|execute_|ctl_alu_oe~14_combout ), - .datac(\z80_|alu_|db_low[1]~17_combout ), - .datad(\z80_|alu_|db[7]~26_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[1]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[1]~13 .lut_mask = 16'hA2FF; -defparam \z80_|alu_|db[1]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N18 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~21 ( -// Equation(s): -// \z80_|alu_|db_low[0]~21_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[1]~13_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(gnd), - .datac(\z80_|alu_|db[1]~13_combout ), - .datad(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~21 .lut_mask = 16'hF5A0; -defparam \z80_|alu_|db_low[0]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N0 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~22 ( -// Equation(s): -// \z80_|alu_|db_low[0]~22_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_low[0]~21_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[0]~19_combout ))) - - .dataa(gnd), - .datab(\z80_|alu_|db_low[0]~21_combout ), - .datac(\z80_|alu_|db[0]~19_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~22 .lut_mask = 16'hCCF0; -defparam \z80_|alu_|db_low[0]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N16 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~18 ( -// Equation(s): -// \z80_|alu_|db_low[0]~18_combout = ((!\z80_|bus_control_|db[4]~19_combout & (!\z80_|bus_control_|db[5]~15_combout & !\z80_|bus_control_|db[3]~21_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datab(\z80_|bus_control_|db[4]~19_combout ), - .datac(\z80_|bus_control_|db[5]~15_combout ), - .datad(\z80_|bus_control_|db[3]~21_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~18 .lut_mask = 16'h5557; -defparam \z80_|alu_|db_low[0]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N20 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~19 ( -// Equation(s): -// \z80_|alu_|db_low[0]~19_combout = (\z80_|alu_|op2_low [0] & (((\z80_|alu_|op1_low [0])) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout ))) # (!\z80_|alu_|op2_low [0] & (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_low [0]) # -// (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) - - .dataa(\z80_|alu_|op2_low [0]), - .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datac(\z80_|alu_|op1_low [0]), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~19 .lut_mask = 16'hA2F3; -defparam \z80_|alu_|db_low[0]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y10_N25 -dffeas \z80_|alu_|result_lo[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_alu_op_low~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|result_lo [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|result_lo[0] .is_wysiwyg = "true"; -defparam \z80_|alu_|result_lo[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N24 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~20 ( -// Equation(s): -// \z80_|alu_|db_low[0]~20_combout = (\z80_|alu_|db_low[0]~18_combout & (\z80_|alu_|db_low[0]~19_combout & ((\z80_|alu_|result_lo [0]) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) - - .dataa(\z80_|alu_|db_low[0]~18_combout ), - .datab(\z80_|alu_|db_low[0]~19_combout ), - .datac(\z80_|alu_|result_lo [0]), - .datad(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~20 .lut_mask = 16'h8880; -defparam \z80_|alu_|db_low[0]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N22 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~23 ( -// Equation(s): -// \z80_|alu_|db_low[0]~23_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout & (\z80_|alu_|db_low[0]~22_combout & ((\z80_|alu_|db_low[0]~20_combout )))) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout & (((\z80_|alu_|db_low[0]~20_combout ) # -// (!\z80_|alu_|db_high[3]~2_combout )))) - - .dataa(\z80_|alu_|db_low[0]~22_combout ), - .datab(\z80_|alu_|db_high[3]~2_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datad(\z80_|alu_|db_low[0]~20_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~23 .lut_mask = 16'hAF03; -defparam \z80_|alu_|db_low[0]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N10 -cycloneive_lcell_comb \z80_|alu_|db[0]~18 ( -// Equation(s): -// \z80_|alu_|db[0]~18_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[0]~30_combout & ((\z80_|alu_|db_low[0]~23_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & -// ((\z80_|alu_|db_low[0]~23_combout ) # ((!\z80_|execute_|ctl_alu_oe~14_combout )))) - - .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datab(\z80_|alu_|db_low[0]~23_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .datad(\z80_|execute_|ctl_alu_oe~14_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[0]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[0]~18 .lut_mask = 16'hC4F5; -defparam \z80_|alu_|db[0]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N16 -cycloneive_lcell_comb \z80_|alu_|db[0]~19 ( -// Equation(s): -// \z80_|alu_|db[0]~19_combout = ((\z80_|alu_|db[0]~18_combout & ((\z80_|alu_control_|db[0]~12_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|alu_|db[7]~26_combout ) - - .dataa(\z80_|alu_|db[0]~18_combout ), - .datab(\z80_|execute_|ctl_sw_2d~13_combout ), - .datac(\z80_|alu_control_|db[0]~12_combout ), - .datad(\z80_|alu_|db[7]~26_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[0]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[0]~19 .lut_mask = 16'hA2FF; -defparam \z80_|alu_|db[0]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N30 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~15 ( -// Equation(s): -// \z80_|alu_|db_low[1]~15_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[2]~15_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[0]~19_combout )) - - .dataa(\z80_|alu_|db[0]~19_combout ), - .datab(gnd), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|alu_|db[2]~15_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~15 .lut_mask = 16'hFA0A; -defparam \z80_|alu_|db_low[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N16 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~16 ( -// Equation(s): -// \z80_|alu_|db_low[1]~16_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_low[1]~15_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[1]~13_combout ))) - - .dataa(\z80_|alu_|db_low[1]~15_combout ), - .datab(gnd), - .datac(\z80_|alu_|db[1]~13_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~16 .lut_mask = 16'hAAF0; -defparam \z80_|alu_|db_low[1]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N6 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~12 ( -// Equation(s): -// \z80_|alu_|db_low[1]~12_combout = ((!\z80_|bus_control_|db[4]~19_combout & (!\z80_|bus_control_|db[5]~15_combout & \z80_|bus_control_|db[3]~21_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datab(\z80_|bus_control_|db[4]~19_combout ), - .datac(\z80_|bus_control_|db[5]~15_combout ), - .datad(\z80_|bus_control_|db[3]~21_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~12 .lut_mask = 16'h5755; -defparam \z80_|alu_|db_low[1]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N18 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~13 ( -// Equation(s): -// \z80_|alu_|db_low[1]~13_combout = (\z80_|alu_|op2_low [1] & (((\z80_|alu_|op1_low [1])) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout ))) # (!\z80_|alu_|op2_low [1] & (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_low [1]) # -// (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) - - .dataa(\z80_|alu_|op2_low [1]), - .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datac(\z80_|alu_|op1_low [1]), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~13 .lut_mask = 16'hA2F3; -defparam \z80_|alu_|db_low[1]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y10_N21 -dffeas \z80_|alu_|result_lo[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_alu_op_low~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|result_lo [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|result_lo[1] .is_wysiwyg = "true"; -defparam \z80_|alu_|result_lo[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N20 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~14 ( -// Equation(s): -// \z80_|alu_|db_low[1]~14_combout = (\z80_|alu_|db_low[1]~12_combout & (\z80_|alu_|db_low[1]~13_combout & ((\z80_|alu_|result_lo [1]) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) - - .dataa(\z80_|alu_|db_low[1]~12_combout ), - .datab(\z80_|alu_|db_low[1]~13_combout ), - .datac(\z80_|alu_|result_lo [1]), - .datad(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~14 .lut_mask = 16'h8880; -defparam \z80_|alu_|db_low[1]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N18 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~17 ( -// Equation(s): -// \z80_|alu_|db_low[1]~17_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout & (((\z80_|alu_|db_low[1]~16_combout & \z80_|alu_|db_low[1]~14_combout )))) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout & (((\z80_|alu_|db_low[1]~14_combout )) # -// (!\z80_|alu_|db_high[3]~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datab(\z80_|alu_|db_high[3]~2_combout ), - .datac(\z80_|alu_|db_low[1]~16_combout ), - .datad(\z80_|alu_|db_low[1]~14_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~17 .lut_mask = 16'hF511; -defparam \z80_|alu_|db_low[1]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N26 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout = (\z80_|alu_|db_low[1]~17_combout & ((\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ) # ((\z80_|alu_|db_high[1]~20_combout & \z80_|execute_|ctl_alu_op1_sel_low~combout )))) # -// (!\z80_|alu_|db_low[1]~17_combout & (((\z80_|alu_|db_high[1]~20_combout & \z80_|execute_|ctl_alu_op1_sel_low~combout )))) - - .dataa(\z80_|alu_|db_low[1]~17_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .datac(\z80_|alu_|db_high[1]~20_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 .lut_mask = 16'hF888; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N0 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6_combout = (\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6 .lut_mask = 16'h00F0; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y10_N1 -dffeas \z80_|alu_|op1_low[1] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_low [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_low[1] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_low[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N28 -cycloneive_lcell_comb \z80_|alu_control_|out[6]~0 ( -// Equation(s): -// \z80_|alu_control_|out[6]~0_combout = (\z80_|alu_|op1_low [3] & ((\z80_|alu_|op1_low [1]) # (\z80_|alu_|op1_low [2]))) - - .dataa(gnd), - .datab(\z80_|alu_|op1_low [1]), - .datac(\z80_|alu_|op1_low [3]), - .datad(\z80_|alu_|op1_low [2]), - .cin(gnd), - .combout(\z80_|alu_control_|out[6]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|out[6]~0 .lut_mask = 16'hF0C0; -defparam \z80_|alu_control_|out[6]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N18 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~2 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf~2_combout = (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & \z80_|execute_|ctl_flags_alu~15_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), - .datad(\z80_|execute_|ctl_flags_alu~15_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~2 .lut_mask = 16'h0F00; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N8 -cycloneive_lcell_comb \z80_|alu_flags_|flags_hf2~0 ( -// Equation(s): -// \z80_|alu_flags_|flags_hf2~0_combout = (\z80_|execute_|ctl_flags_hf2_we~combout & ((\z80_|alu_control_|db[4]~32_combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout )))) # (!\z80_|execute_|ctl_flags_hf2_we~combout & -// (((\z80_|alu_flags_|flags_hf2~q )))) - - .dataa(\z80_|alu_control_|db[4]~32_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ), - .datac(\z80_|alu_flags_|flags_hf2~q ), - .datad(\z80_|execute_|ctl_flags_hf2_we~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|flags_hf2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_hf2~0 .lut_mask = 16'hEEF0; -defparam \z80_|alu_flags_|flags_hf2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y11_N9 -dffeas \z80_|alu_flags_|flags_hf2 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|flags_hf2~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|flags_hf2~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_hf2 .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|flags_hf2 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N12 -cycloneive_lcell_comb \z80_|alu_control_|db[2]~23 ( -// Equation(s): -// \z80_|alu_control_|db[2]~23_combout = (\z80_|execute_|ctl_66_oe~combout ) # ((\z80_|alu_control_|out[6]~0_combout ) # ((\z80_|alu_flags_|flags_hf2~q ) # (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout ))) - - .dataa(\z80_|execute_|ctl_66_oe~combout ), - .datab(\z80_|alu_control_|out[6]~0_combout ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datad(\z80_|alu_flags_|flags_hf2~q ), - .cin(gnd), - .combout(\z80_|alu_control_|db[2]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[2]~23 .lut_mask = 16'hFFEF; -defparam \z80_|alu_control_|db[2]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N26 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[2]~2 ( -// Equation(s): -// \z80_|reg_file_|db_lo_ds[2]~2_combout = (\z80_|reg_file_|gdfx_temp0[2]~42_combout ) # ((!\z80_|execute_|ctl_reg_out_lo~5_combout & (\z80_|execute_|ctl_reg_out_lo~7_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ))) - - .dataa(\z80_|execute_|ctl_reg_out_lo~5_combout ), - .datab(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_ds[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_ds[2]~2 .lut_mask = 16'hFF40; -defparam \z80_|reg_file_|db_lo_ds[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N16 -cycloneive_lcell_comb \z80_|alu_control_|db[2]~28 ( -// Equation(s): -// \z80_|alu_control_|db[2]~28_combout = (\z80_|reg_file_|db_lo_ds[2]~2_combout & (((\z80_|bus_control_|db[2]~13_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) - - .dataa(\z80_|bus_control_|db[2]~13_combout ), - .datab(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .datac(\z80_|execute_|ctl_sw_1d~7_combout ), - .datad(\z80_|reg_file_|db_lo_ds[2]~2_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[2]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[2]~28 .lut_mask = 16'h2F00; -defparam \z80_|alu_control_|db[2]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N28 -cycloneive_lcell_comb \z80_|alu_control_|db[2]~27 ( -// Equation(s): -// \z80_|alu_control_|db[2]~27_combout = (\z80_|execute_|ctl_flags_oe~2_combout & (((!\z80_|alu_|db[2]~15_combout & \z80_|execute_|ctl_sw_2u~7_combout )) # (!\z80_|alu_flags_|DFFE_inst_latch_pf~q ))) # (!\z80_|execute_|ctl_flags_oe~2_combout & -// (!\z80_|alu_|db[2]~15_combout & ((\z80_|execute_|ctl_sw_2u~7_combout )))) - - .dataa(\z80_|execute_|ctl_flags_oe~2_combout ), - .datab(\z80_|alu_|db[2]~15_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), - .datad(\z80_|execute_|ctl_sw_2u~7_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[2]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[2]~27 .lut_mask = 16'h3B0A; -defparam \z80_|alu_control_|db[2]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N22 -cycloneive_lcell_comb \z80_|alu_control_|db[2]~29 ( -// Equation(s): -// \z80_|alu_control_|db[2]~29_combout = ((\z80_|alu_control_|db[2]~23_combout & (\z80_|alu_control_|db[2]~28_combout & !\z80_|alu_control_|db[2]~27_combout ))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|alu_control_|db[6]~11_combout ), - .datab(\z80_|alu_control_|db[2]~23_combout ), - .datac(\z80_|alu_control_|db[2]~28_combout ), - .datad(\z80_|alu_control_|db[2]~27_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[2]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[2]~29 .lut_mask = 16'h55D5; -defparam \z80_|alu_control_|db[2]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N30 -cycloneive_lcell_comb \z80_|alu_|db[2]~14 ( -// Equation(s): -// \z80_|alu_|db[2]~14_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[2]~39_combout & ((\z80_|alu_control_|db[2]~29_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & -// (((\z80_|alu_control_|db[2]~29_combout )) # (!\z80_|execute_|ctl_sw_2d~13_combout ))) - - .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datab(\z80_|execute_|ctl_sw_2d~13_combout ), - .datac(\z80_|alu_control_|db[2]~29_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[2]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[2]~14 .lut_mask = 16'hF351; -defparam \z80_|alu_|db[2]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N4 -cycloneive_lcell_comb \z80_|alu_|db[2]~15 ( -// Equation(s): -// \z80_|alu_|db[2]~15_combout = ((\z80_|alu_|db[2]~14_combout & ((\z80_|alu_|db_low[2]~24_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~26_combout ) - - .dataa(\z80_|alu_|db_low[2]~24_combout ), - .datab(\z80_|execute_|ctl_alu_oe~14_combout ), - .datac(\z80_|alu_|db[2]~14_combout ), - .datad(\z80_|alu_|db[7]~26_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[2]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[2]~15 .lut_mask = 16'hB0FF; -defparam \z80_|alu_|db[2]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N4 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~2 ( -// Equation(s): -// \z80_|alu_|db_low[2]~2_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[3]~11_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[1]~13_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|alu_|db[3]~11_combout ), - .datac(\z80_|alu_|db[1]~13_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~2 .lut_mask = 16'hD8D8; -defparam \z80_|alu_|db_low[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N8 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~3 ( -// Equation(s): -// \z80_|alu_|db_low[2]~3_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_low[2]~2_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[2]~15_combout ))) # -// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) - - .dataa(\z80_|alu_|db[2]~15_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datac(\z80_|alu_|db_low[2]~2_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~3 .lut_mask = 16'hF3BB; -defparam \z80_|alu_|db_low[2]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N18 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & (((\z80_|alu_|db_low[2]~6_combout & \z80_|alu_|db_low[2]~3_combout )) # (!\z80_|alu_|db_high[3]~3_combout ))) - - .dataa(\z80_|alu_|db_low[2]~6_combout ), - .datab(\z80_|alu_|db_high[3]~3_combout ), - .datac(\z80_|alu_|db_low[2]~3_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2 .lut_mask = 16'hB300; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N24 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & ((\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout ) # ((\z80_|alu_|db_high[2]~14_combout & \z80_|execute_|ctl_alu_op1_sel_low~combout )))) - - .dataa(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .datac(\z80_|alu_|db_high[2]~14_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 .lut_mask = 16'h3222; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y10_N25 -dffeas \z80_|alu_|op1_low[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_low [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_low[2] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_low[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N24 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [2]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [2])))) - - .dataa(\z80_|alu_|op1_high [2]), - .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datac(\z80_|execute_|ctl_alu_op_low~combout ), - .datad(\z80_|alu_|op1_low [2]), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0 .lut_mask = 16'hC808; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N12 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0_combout ) # ((\z80_|alu_|db_low[2]~24_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datab(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0_combout ), - .datac(\z80_|alu_|db_low[2]~24_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1 .lut_mask = 16'h5444; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y10_N13 -dffeas \z80_|alu_|op2_low[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_low [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_low[2] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_low[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N30 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~5 ( -// Equation(s): -// \z80_|alu_|db_low[2]~5_combout = (\z80_|alu_|op2_low [2] & ((\z80_|alu_|op1_low [2]) # ((!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) # (!\z80_|alu_|op2_low [2] & (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_low [2]) # -// (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) - - .dataa(\z80_|alu_|op2_low [2]), - .datab(\z80_|alu_|op1_low [2]), - .datac(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~5 .lut_mask = 16'h8ACF; -defparam \z80_|alu_|db_low[2]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y10_N13 -dffeas \z80_|alu_|result_lo[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_alu_op_low~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|result_lo [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|result_lo[2] .is_wysiwyg = "true"; -defparam \z80_|alu_|result_lo[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N30 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~6 ( -// Equation(s): -// \z80_|alu_|db_low[2]~6_combout = (\z80_|alu_|db_low[2]~4_combout & (\z80_|alu_|db_low[2]~5_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|result_lo [2])))) - - .dataa(\z80_|alu_|db_low[2]~4_combout ), - .datab(\z80_|alu_|db_low[2]~5_combout ), - .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datad(\z80_|alu_|result_lo [2]), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~6 .lut_mask = 16'h8880; -defparam \z80_|alu_|db_low[2]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N24 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & (((\z80_|alu_|db_low[2]~6_combout & \z80_|alu_|db_low[2]~3_combout )) # (!\z80_|alu_|db_high[3]~3_combout ))) - - .dataa(\z80_|alu_|db_low[2]~6_combout ), - .datab(\z80_|alu_|db_low[2]~3_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datad(\z80_|alu_|db_high[3]~3_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 .lut_mask = 16'h80F0; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N26 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ) # ((\z80_|alu_|db_high[2]~14_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datab(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ), - .datac(\z80_|alu_|db_high[2]~14_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4 .lut_mask = 16'h5444; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y10_N27 -dffeas \z80_|alu_|op2_high[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_high [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_high[2] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_high[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N14 -cycloneive_lcell_comb \z80_|alu_|alu_op2[2]~0 ( -// Equation(s): -// \z80_|alu_|alu_op2[2]~0_combout = \z80_|execute_|ctl_alu_sel_op2_neg~18_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_high [2])) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_low [2]))))) - - .dataa(\z80_|alu_|op2_high [2]), - .datab(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), - .datad(\z80_|alu_|op2_low [2]), - .cin(gnd), - .combout(\z80_|alu_|alu_op2[2]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op2[2]~0 .lut_mask = 16'h4B78; -defparam \z80_|alu_|alu_op2[2]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N0 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ) # -// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) # (!\z80_|execute_|ctl_alu_core_R~5_combout ) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), - .datad(\z80_|execute_|ctl_alu_core_R~5_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 .lut_mask = 16'h0BFF; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N12 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout = (\z80_|alu_|alu_op2[2]~0_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ) # ((\z80_|alu_|alu_op1[2]~2_combout & -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) # (!\z80_|alu_|alu_op2[2]~0_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_|alu_op1[2]~2_combout ) # -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) - - .dataa(\z80_|alu_|alu_op2[2]~0_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ), - .datac(\z80_|alu_|alu_op1[2]~2_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 .lut_mask = 16'hECC8; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N26 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~9 ( -// Equation(s): -// \z80_|alu_|db_high[2]~9_combout = ((\z80_|bus_control_|db[4]~19_combout & (\z80_|bus_control_|db[5]~15_combout & !\z80_|bus_control_|db[3]~21_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datab(\z80_|bus_control_|db[4]~19_combout ), - .datac(\z80_|bus_control_|db[5]~15_combout ), - .datad(\z80_|bus_control_|db[3]~21_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~9 .lut_mask = 16'h55D5; -defparam \z80_|alu_|db_high[2]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N24 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~11 ( -// Equation(s): -// \z80_|alu_|db_high[2]~11_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[7]~21_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[5]~25_combout )) - - .dataa(\z80_|ir_|opcode [3]), - .datab(gnd), - .datac(\z80_|alu_|db[5]~25_combout ), - .datad(\z80_|alu_|db[7]~21_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~11 .lut_mask = 16'hFA50; -defparam \z80_|alu_|db_high[2]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N22 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~12 ( -// Equation(s): -// \z80_|alu_|db_high[2]~12_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_high[2]~11_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[6]~23_combout ))) - - .dataa(gnd), - .datab(\z80_|alu_|db_high[2]~11_combout ), - .datac(\z80_|alu_|db[6]~23_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~12 .lut_mask = 16'hCCF0; -defparam \z80_|alu_|db_high[2]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N24 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~10 ( -// Equation(s): -// \z80_|alu_|db_high[2]~10_combout = (\z80_|alu_|op1_high [2] & (((\z80_|alu_|op2_high [2]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|alu_|op1_high [2] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_high [2]) # -// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) - - .dataa(\z80_|alu_|op1_high [2]), - .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datac(\z80_|alu_|op2_high [2]), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~10 .lut_mask = 16'hB0BB; -defparam \z80_|alu_|db_high[2]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N20 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~13 ( -// Equation(s): -// \z80_|alu_|db_high[2]~13_combout = (\z80_|alu_|db_high[2]~9_combout & (\z80_|alu_|db_high[2]~10_combout & ((\z80_|alu_|db_high[2]~12_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) - - .dataa(\z80_|alu_|db_high[2]~9_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datac(\z80_|alu_|db_high[2]~12_combout ), - .datad(\z80_|alu_|db_high[2]~10_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~13 .lut_mask = 16'hA200; -defparam \z80_|alu_|db_high[2]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N10 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~14 ( -// Equation(s): -// \z80_|alu_|db_high[2]~14_combout = ((\z80_|alu_|db_high[2]~13_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) # (!\z80_|alu_|db_high[3]~3_combout ) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), - .datab(\z80_|alu_|db_high[3]~3_combout ), - .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datad(\z80_|alu_|db_high[2]~13_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~14 .lut_mask = 16'hFB33; -defparam \z80_|alu_|db_high[2]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N18 -cycloneive_lcell_comb \z80_|alu_|db[6]~22 ( -// Equation(s): -// \z80_|alu_|db[6]~22_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[6]~84_combout & ((\z80_|alu_control_|db[6]~22_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & -// (((\z80_|alu_control_|db[6]~22_combout )) # (!\z80_|execute_|ctl_sw_2d~13_combout ))) - - .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datab(\z80_|execute_|ctl_sw_2d~13_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .datad(\z80_|alu_control_|db[6]~22_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[6]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[6]~22 .lut_mask = 16'hF531; -defparam \z80_|alu_|db[6]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N20 -cycloneive_lcell_comb \z80_|alu_|db[6]~23 ( -// Equation(s): -// \z80_|alu_|db[6]~23_combout = ((\z80_|alu_|db[6]~22_combout & ((\z80_|alu_|db_high[2]~14_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~26_combout ) - - .dataa(\z80_|alu_|db_high[2]~14_combout ), - .datab(\z80_|execute_|ctl_alu_oe~14_combout ), - .datac(\z80_|alu_|db[6]~22_combout ), - .datad(\z80_|alu_|db[7]~26_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[6]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[6]~23 .lut_mask = 16'hB0FF; -defparam \z80_|alu_|db[6]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N10 -cycloneive_lcell_comb \z80_|alu_control_|out[6]~1 ( -// Equation(s): -// \z80_|alu_control_|out[6]~1_combout = (\z80_|alu_|op1_high [2]) # ((\z80_|alu_|op1_high [1]) # ((\z80_|alu_|op1_high [0] & \z80_|alu_control_|out[6]~0_combout ))) - - .dataa(\z80_|alu_|op1_high [2]), - .datab(\z80_|alu_|op1_high [0]), - .datac(\z80_|alu_|op1_high [1]), - .datad(\z80_|alu_control_|out[6]~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|out[6]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|out[6]~1 .lut_mask = 16'hFEFA; -defparam \z80_|alu_control_|out[6]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N26 -cycloneive_lcell_comb \z80_|alu_control_|out[6]~2 ( -// Equation(s): -// \z80_|alu_control_|out[6]~2_combout = (\z80_|execute_|ctl_66_oe~combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_cf~q ) # ((\z80_|alu_control_|out[6]~1_combout & \z80_|alu_|op1_high [3]))) - - .dataa(\z80_|execute_|ctl_66_oe~combout ), - .datab(\z80_|alu_control_|out[6]~1_combout ), - .datac(\z80_|alu_|op1_high [3]), - .datad(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), - .cin(gnd), - .combout(\z80_|alu_control_|out[6]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|out[6]~2 .lut_mask = 16'hFFEA; -defparam \z80_|alu_control_|out[6]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N12 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~19 ( -// Equation(s): -// \z80_|alu_control_|db[6]~19_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & ((\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ) # ((\z80_|alu_control_|out[6]~2_combout )))) # (!\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & -// (!\z80_|execute_|ctl_flags_oe~2_combout & ((\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ) # (\z80_|alu_control_|out[6]~2_combout )))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .datab(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .datac(\z80_|execute_|ctl_flags_oe~2_combout ), - .datad(\z80_|alu_control_|out[6]~2_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~19 .lut_mask = 16'hAF8C; -defparam \z80_|alu_control_|db[6]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N26 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~20 ( -// Equation(s): -// \z80_|alu_control_|db[6]~20_combout = (\z80_|alu_control_|db[6]~19_combout & ((\z80_|alu_|db[6]~23_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout ))) - - .dataa(gnd), - .datab(\z80_|alu_|db[6]~23_combout ), - .datac(\z80_|execute_|ctl_sw_2u~7_combout ), - .datad(\z80_|alu_control_|db[6]~19_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~20 .lut_mask = 16'hCF00; -defparam \z80_|alu_control_|db[6]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N24 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~21 ( -// Equation(s): -// \z80_|alu_control_|db[6]~21_combout = (\z80_|alu_control_|db[6]~20_combout & (((\z80_|bus_control_|db[6]~9_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) - - .dataa(\z80_|bus_control_|db[6]~9_combout ), - .datab(\z80_|execute_|ctl_sw_1d~7_combout ), - .datac(\z80_|alu_control_|db[6]~20_combout ), - .datad(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~21 .lut_mask = 16'h30B0; -defparam \z80_|alu_control_|db[6]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N6 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~22 ( -// Equation(s): -// \z80_|alu_control_|db[6]~22_combout = ((\z80_|alu_control_|db[6]~21_combout & ((\z80_|reg_file_|gdfx_temp0[6]~82_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|alu_control_|db[6]~11_combout ), - .datab(\z80_|alu_control_|db[6]~21_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .datad(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~22 .lut_mask = 16'hD5DD; -defparam \z80_|alu_control_|db[6]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_zero_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_bus_zero_oe~0_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal33~1_combout & ((\z80_|execute_|ctl_alu_op_low~13_combout ) # (\z80_|execute_|ctl_iorw~11_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~13_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_iorw~11_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_zero_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_zero_oe~0 .lut_mask = 16'hC800; -defparam \z80_|execute_|ctl_bus_zero_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N8 -cycloneive_lcell_comb \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 ( -// Equation(s): -// \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout = (\z80_|bus_control_|db[4]~19_combout & !\z80_|bus_control_|db[3]~21_combout ) - - .dataa(gnd), - .datab(\z80_|bus_control_|db[4]~19_combout ), - .datac(gnd), - .datad(\z80_|bus_control_|db[3]~21_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 .lut_mask = 16'h00CC; -defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y10_N9 -dffeas \z80_|interrupts_|im1 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_im_we~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|interrupts_|im1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|interrupts_|im1 .is_wysiwyg = "true"; -defparam \z80_|interrupts_|im1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_ff_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_bus_ff_oe~0_combout = (\z80_|interrupts_|DFFE_inst44~q & ((\z80_|interrupts_|im1~q ) # ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|interrupts_|im2~q )))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|interrupts_|im1~q ), - .datac(\z80_|interrupts_|im2~q ), - .datad(\z80_|interrupts_|DFFE_inst44~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_ff_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_ff_oe~0 .lut_mask = 16'hDC00; -defparam \z80_|execute_|ctl_bus_ff_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_ff_oe~1 ( -// Equation(s): -// \z80_|execute_|ctl_bus_ff_oe~1_combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) # (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|execute_|ctl_bus_ff_oe~0_combout & -// ((\z80_|execute_|ctl_66_oe~2_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|execute_|ctl_bus_ff_oe~0_combout ), - .datac(\z80_|execute_|ctl_66_oe~2_combout ), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_ff_oe~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_ff_oe~1 .lut_mask = 16'h40EE; -defparam \z80_|execute_|ctl_bus_ff_oe~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N0 -cycloneive_lcell_comb \z80_|bus_control_|db[0]~4 ( -// Equation(s): -// \z80_|bus_control_|db[0]~4_combout = (\z80_|execute_|ctl_bus_ff_oe~1_combout ) # ((!\z80_|execute_|ctl_bus_zero_oe~0_combout & ((\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) # (!\z80_|decode_state_|in_halt~q )))) - - .dataa(\z80_|decode_state_|in_halt~q ), - .datab(\z80_|execute_|ctl_bus_zero_oe~0_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|execute_|ctl_bus_ff_oe~1_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[0]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[0]~4 .lut_mask = 16'hFF31; -defparam \z80_|bus_control_|db[0]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N6 -cycloneive_lcell_comb \z80_|bus_control_|db[6]~8 ( -// Equation(s): -// \z80_|bus_control_|db[6]~8_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[6]~22_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) - - .dataa(gnd), - .datab(\z80_|alu_control_|db[6]~22_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|bus_control_|db[0]~4_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[6]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[6]~8 .lut_mask = 16'hCF00; -defparam \z80_|bus_control_|db[6]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~37 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~37_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal37~0_combout & !\z80_|execute_|ctl_mRead~36_combout ))) # (!\z80_|sequencer_|DFFE_T5_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|pla_decode_|Equal37~0_combout ), - .datad(\z80_|execute_|ctl_mRead~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~37 .lut_mask = 16'hDDDF; -defparam \z80_|execute_|ctl_mRead~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~28 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~28_combout = (\z80_|execute_|ctl_mRead~37_combout & (!\z80_|execute_|ctl_reg_gp_sel~36_combout & ((!\z80_|pla_decode_|Equal38~2_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~37_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel~36_combout ), - .datad(\z80_|pla_decode_|Equal38~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~28 .lut_mask = 16'h020A; -defparam \z80_|execute_|ctl_mRead~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~29 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~29_combout = (\z80_|execute_|ctl_mRead~28_combout & (\z80_|execute_|ctl_mRead~25_combout & ((!\z80_|pla_decode_|Equal21~1_combout ) # (!\z80_|execute_|ctl_mRead~11_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~28_combout ), - .datab(\z80_|execute_|ctl_mRead~11_combout ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|execute_|ctl_mRead~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~29 .lut_mask = 16'h2A00; -defparam \z80_|execute_|ctl_mRead~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~30 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~30_combout = (\z80_|execute_|ctl_mRead~29_combout & (\z80_|execute_|ctl_reg_in_hi~5_combout & (\z80_|execute_|ctl_mRead~22_combout & !\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ))) - - .dataa(\z80_|execute_|ctl_mRead~29_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~5_combout ), - .datac(\z80_|execute_|ctl_mRead~22_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~30 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_mRead~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y18_N0 -cycloneive_lcell_comb \z80_|execute_|setM1~37 ( -// Equation(s): -// \z80_|execute_|setM1~37_combout = (!\z80_|pla_decode_|Equal9~1_combout & (!\z80_|pla_decode_|Equal29~0_combout & (\z80_|execute_|ctl_al_we~4_combout & \z80_|execute_|ctl_inc_cy~41_combout ))) - - .dataa(\z80_|pla_decode_|Equal9~1_combout ), - .datab(\z80_|pla_decode_|Equal29~0_combout ), - .datac(\z80_|execute_|ctl_al_we~4_combout ), - .datad(\z80_|execute_|ctl_inc_cy~41_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~37 .lut_mask = 16'h1000; -defparam \z80_|execute_|setM1~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N10 -cycloneive_lcell_comb \z80_|execute_|setM1~55 ( +// Location: LCCOMB_X25_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|ixy_d~17 ( // Equation(s): -// \z80_|execute_|setM1~55_combout = (!\z80_|execute_|ctl_mRead~14_combout & ((\z80_|decode_state_|DFFE_instIY1~q ) # ((\z80_|decode_state_|DFFE_inst4~q ) # (!\z80_|pla_decode_|Equal49~0_combout )))) +// \z80_|execute_|ixy_d~17_combout = (\z80_|decode_state_|DFFE_instIY1~q & (((!\z80_|pla_decode_|Equal33~2_combout & !\z80_|pla_decode_|Equal50~0_combout )))) # (!\z80_|decode_state_|DFFE_instIY1~q & (((!\z80_|pla_decode_|Equal33~2_combout & +// !\z80_|pla_decode_|Equal50~0_combout )) # (!\z80_|decode_state_|DFFE_inst4~q ))) .dataa(\z80_|decode_state_|DFFE_instIY1~q ), - .datab(\z80_|execute_|ctl_mRead~14_combout ), - .datac(\z80_|decode_state_|DFFE_inst4~q ), - .datad(\z80_|pla_decode_|Equal49~0_combout ), + .datab(\z80_|decode_state_|DFFE_inst4~q ), + .datac(\z80_|pla_decode_|Equal33~2_combout ), + .datad(\z80_|pla_decode_|Equal50~0_combout ), .cin(gnd), - .combout(\z80_|execute_|setM1~55_combout ), + .combout(\z80_|execute_|ixy_d~17_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|setM1~55 .lut_mask = 16'h3233; -defparam \z80_|execute_|setM1~55 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ixy_d~17 .lut_mask = 16'h111F; +defparam \z80_|execute_|ixy_d~17 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y18_N30 -cycloneive_lcell_comb \z80_|execute_|setM1~38 ( +// Location: LCCOMB_X25_Y16_N0 +cycloneive_lcell_comb \z80_|pla_decode_|Equal44~0 ( // Equation(s): -// \z80_|execute_|setM1~38_combout = (!\z80_|execute_|ctl_mRead~16_combout & (\z80_|execute_|setM1~37_combout & (\z80_|execute_|setM1~55_combout & \z80_|execute_|setM1~36_combout ))) +// \z80_|pla_decode_|Equal44~0_combout = (!\z80_|decode_state_|DFFE_instCB~q & (!\z80_|decode_state_|DFFE_instED~q & (\z80_|ir_|opcode [7] & !\z80_|ir_|opcode [6]))) - .dataa(\z80_|execute_|ctl_mRead~16_combout ), - .datab(\z80_|execute_|setM1~37_combout ), - .datac(\z80_|execute_|setM1~55_combout ), - .datad(\z80_|execute_|setM1~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~38 .lut_mask = 16'h4000; -defparam \z80_|execute_|setM1~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~34 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~34_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (((\z80_|execute_|ctl_mRead~13_combout ) # (!\z80_|execute_|ctl_mRead~19_combout )) # (!\z80_|execute_|setM1~38_combout ))) - - .dataa(\z80_|execute_|setM1~38_combout ), - .datab(\z80_|execute_|ctl_mRead~13_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_mRead~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~34 .lut_mask = 16'hD0F0; -defparam \z80_|execute_|ctl_mRead~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N2 -cycloneive_lcell_comb \z80_|execute_|nextM~3 ( -// Equation(s): -// \z80_|execute_|nextM~3_combout = (!\z80_|pla_decode_|Equal41~2_combout & (!\z80_|execute_|ixy_d~10_combout & !\z80_|execute_|ixy_d~16_combout )) - - .dataa(gnd), - .datab(\z80_|pla_decode_|Equal41~2_combout ), - .datac(\z80_|execute_|ixy_d~10_combout ), - .datad(\z80_|execute_|ixy_d~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~3 .lut_mask = 16'h0003; -defparam \z80_|execute_|nextM~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~31 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~31_combout = (\z80_|execute_|ixy_d~8_combout & (((\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal49~0_combout )) # (!\z80_|execute_|nextM~3_combout ))) - - .dataa(\z80_|execute_|ixy_d~8_combout ), - .datab(\z80_|decode_state_|use_ixiy~combout ), - .datac(\z80_|execute_|nextM~3_combout ), - .datad(\z80_|pla_decode_|Equal49~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~31 .lut_mask = 16'h8A0A; -defparam \z80_|execute_|ctl_mRead~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~32 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~32_combout = (\z80_|execute_|ctl_state_alu~4_combout & ((\z80_|pla_decode_|Equal33~3_combout ) # ((\z80_|pla_decode_|Equal6~1_combout ) # (\z80_|pla_decode_|Equal41~2_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|pla_decode_|Equal33~3_combout ), - .datac(\z80_|pla_decode_|Equal6~1_combout ), - .datad(\z80_|pla_decode_|Equal41~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~32 .lut_mask = 16'hAAA8; -defparam \z80_|execute_|ctl_mRead~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~33 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~33_combout = (\z80_|execute_|ctl_mRead~32_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & \z80_|execute_|ctl_mRead~12_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .datac(\z80_|execute_|ctl_mRead~12_combout ), - .datad(\z80_|execute_|ctl_mRead~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~33 .lut_mask = 16'hFFC0; -defparam \z80_|execute_|ctl_mRead~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~35 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~35_combout = ((\z80_|execute_|ctl_mRead~34_combout ) # ((\z80_|execute_|ctl_mRead~31_combout ) # (\z80_|execute_|ctl_mRead~33_combout ))) # (!\z80_|execute_|ctl_mRead~30_combout ) - - .dataa(\z80_|execute_|ctl_mRead~30_combout ), - .datab(\z80_|execute_|ctl_mRead~34_combout ), - .datac(\z80_|execute_|ctl_mRead~31_combout ), - .datad(\z80_|execute_|ctl_mRead~33_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~35 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_mRead~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X43_Y17_N23 -dffeas \z80_|memory_ifc_|DFFE_mrd_ff1 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_mRead~35_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_mrd_ff1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_mrd_ff1 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_mrd_ff1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y15_N24 -cycloneive_lcell_comb \z80_|memory_ifc_|wait_mrd~feeder ( -// Equation(s): -// \z80_|memory_ifc_|wait_mrd~feeder_combout = \z80_|memory_ifc_|DFFE_mrd_ff1~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|memory_ifc_|DFFE_mrd_ff1~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|wait_mrd~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_mrd~feeder .lut_mask = 16'hFF00; -defparam \z80_|memory_ifc_|wait_mrd~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X46_Y15_N25 -dffeas \z80_|memory_ifc_|wait_mrd ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|memory_ifc_|wait_mrd~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|wait_mrd~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_mrd .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|wait_mrd .power_up = "low"; -// synopsys translate_on - -// Location: FF_X43_Y17_N3 -dffeas \z80_|memory_ifc_|DFFE_mrd_ff3 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|memory_ifc_|wait_mrd~q ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_mrd_ff3~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_mrd_ff3 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_mrd_ff3 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N8 -cycloneive_lcell_comb \z80_|memory_ifc_|nRD_out~1 ( -// Equation(s): -// \z80_|memory_ifc_|nRD_out~1_combout = (!\z80_|memory_ifc_|wait_mrd~q & !\z80_|memory_ifc_|DFFE_mrd_ff3~q ) - - .dataa(\z80_|memory_ifc_|wait_mrd~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|memory_ifc_|DFFE_mrd_ff3~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|nRD_out~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|nRD_out~1 .lut_mask = 16'h0055; -defparam \z80_|memory_ifc_|nRD_out~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N30 -cycloneive_lcell_comb \z80_|execute_|nextM~4 ( -// Equation(s): -// \z80_|execute_|nextM~4_combout = ((!\z80_|execute_|ctl_mRead~36_combout & ((!\z80_|pla_decode_|Equal24~0_combout ) # (!\z80_|pla_decode_|Equal21~0_combout )))) # (!\z80_|execute_|ctl_state_alu~4_combout ) - - .dataa(\z80_|pla_decode_|Equal21~0_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_mRead~36_combout ), - .datad(\z80_|pla_decode_|Equal24~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~4 .lut_mask = 16'h373F; -defparam \z80_|execute_|nextM~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_iorw~12 ( -// Equation(s): -// \z80_|execute_|ctl_iorw~12_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2]))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|execute_|ctl_iorw~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_iorw~12 .lut_mask = 16'h0008; -defparam \z80_|execute_|ctl_iorw~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_iorw~8 ( -// Equation(s): -// \z80_|execute_|ctl_iorw~8_combout = (\z80_|execute_|ctl_iorw~12_combout ) # ((\z80_|pla_decode_|Equal24~0_combout & (\z80_|pla_decode_|Equal3~0_combout & \z80_|execute_|ctl_state_alu~4_combout ))) - - .dataa(\z80_|pla_decode_|Equal24~0_combout ), - .datab(\z80_|execute_|ctl_iorw~12_combout ), - .datac(\z80_|pla_decode_|Equal3~0_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_iorw~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_iorw~8 .lut_mask = 16'hECCC; -defparam \z80_|execute_|ctl_iorw~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_iorw~9 ( -// Equation(s): -// \z80_|execute_|ctl_iorw~9_combout = ((\z80_|execute_|ctl_iorw~8_combout ) # ((\z80_|execute_|ctl_mRead~11_combout & \z80_|execute_|ctl_mWrite~16_combout ))) # (!\z80_|execute_|nextM~4_combout ) - - .dataa(\z80_|execute_|nextM~4_combout ), - .datab(\z80_|execute_|ctl_mRead~11_combout ), - .datac(\z80_|execute_|ctl_mWrite~16_combout ), - .datad(\z80_|execute_|ctl_iorw~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_iorw~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_iorw~9 .lut_mask = 16'hFFD5; -defparam \z80_|execute_|ctl_iorw~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X43_Y17_N7 -dffeas \z80_|memory_ifc_|DFFE_iorq_ff1 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_iorw~9_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_iorq_ff1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_iorq_ff1 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_iorq_ff1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N26 -cycloneive_lcell_comb \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder ( -// Equation(s): -// \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder_combout = \z80_|memory_ifc_|DFFE_iorq_ff1~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|memory_ifc_|DFFE_iorq_ff1~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder .lut_mask = 16'hFF00; -defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X43_Y17_N27 -dffeas \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 .power_up = "low"; -// synopsys translate_on - -// Location: FF_X43_Y17_N9 -dffeas \z80_|memory_ifc_|wait_iorq ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|wait_iorq~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_iorq .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|wait_iorq .power_up = "low"; -// synopsys translate_on - -// Location: FF_X43_Y17_N13 -dffeas \z80_|memory_ifc_|DFFE_iorq_ff4 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|memory_ifc_|wait_iorq~q ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_iorq_ff4~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_iorq_ff4 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_iorq_ff4 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N12 -cycloneive_lcell_comb \z80_|memory_ifc_|iorq~0 ( -// Equation(s): -// \z80_|memory_ifc_|iorq~0_combout = (\z80_|memory_ifc_|wait_iorq~q ) # ((\z80_|memory_ifc_|DFFE_iorq_ff4~q ) # (\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q )) - - .dataa(gnd), - .datab(\z80_|memory_ifc_|wait_iorq~q ), - .datac(\z80_|memory_ifc_|DFFE_iorq_ff4~q ), - .datad(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|iorq~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|iorq~0 .lut_mask = 16'hFFFC; -defparam \z80_|memory_ifc_|iorq~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|fIORead~1 ( -// Equation(s): -// \z80_|execute_|fIORead~1_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_mWrite~2_combout & ((\z80_|execute_|ctl_state_alu~5_combout ) # (\z80_|execute_|ctl_mWrite~3_combout )))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|execute_|ctl_state_alu~5_combout ), - .datac(\z80_|execute_|ctl_mWrite~3_combout ), - .datad(\z80_|execute_|ctl_mWrite~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIORead~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIORead~1 .lut_mask = 16'hA800; -defparam \z80_|execute_|fIORead~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N18 -cycloneive_lcell_comb \z80_|execute_|fIORead~2 ( -// Equation(s): -// \z80_|execute_|fIORead~2_combout = (\z80_|execute_|fIORead~1_combout ) # ((\z80_|execute_|ctl_alu_op_low~9_combout ) # ((\z80_|execute_|ctl_iorw~10_combout & !\z80_|execute_|fIOWrite~0_combout ))) - - .dataa(\z80_|execute_|ctl_iorw~10_combout ), - .datab(\z80_|execute_|fIOWrite~0_combout ), - .datac(\z80_|execute_|fIORead~1_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIORead~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIORead~2 .lut_mask = 16'hFFF2; -defparam \z80_|execute_|fIORead~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y18_N6 -cycloneive_lcell_comb \z80_|execute_|fIORead~0 ( -// Equation(s): -// \z80_|execute_|fIORead~0_combout = (\z80_|execute_|ctl_mWrite~2_combout & (\z80_|pla_decode_|Equal55~0_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ctl_alu_op_low~8_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~2_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIORead~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIORead~0 .lut_mask = 16'hA080; -defparam \z80_|execute_|fIORead~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N6 -cycloneive_lcell_comb \z80_|execute_|fIORead~3 ( -// Equation(s): -// \z80_|execute_|fIORead~3_combout = (\z80_|execute_|fIORead~2_combout ) # ((\z80_|execute_|fIORead~0_combout ) # ((\z80_|execute_|fIOWrite~1_combout & \z80_|execute_|ctl_mRead~4_combout ))) - - .dataa(\z80_|execute_|fIOWrite~1_combout ), - .datab(\z80_|execute_|fIORead~2_combout ), - .datac(\z80_|execute_|ctl_mRead~4_combout ), - .datad(\z80_|execute_|fIORead~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIORead~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIORead~3 .lut_mask = 16'hFFEC; -defparam \z80_|execute_|fIORead~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X41_Y17_N25 -dffeas \z80_|memory_ifc_|DFFE_m1_ff1 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|setM1~52_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_m1_ff1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_m1_ff1 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_m1_ff1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N14 -cycloneive_lcell_comb \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0 ( -// Equation(s): -// \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout = !\z80_|memory_ifc_|DFFE_m1_ff1~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|memory_ifc_|DFFE_m1_ff1~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0 .lut_mask = 16'h00FF; -defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X43_Y17_N15 -dffeas \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 .power_up = "low"; -// synopsys translate_on - -// Location: FF_X43_Y17_N21 -dffeas \z80_|memory_ifc_|DFFE_m1_ff3 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_m1_ff3~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_m1_ff3 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_m1_ff3 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N20 -cycloneive_lcell_comb \z80_|memory_ifc_|nRD_out~0 ( -// Equation(s): -// \z80_|memory_ifc_|nRD_out~0_combout = (\z80_|interrupts_|DFFE_inst44~q & (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & ((\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ) # (\z80_|memory_ifc_|DFFE_m1_ff3~q )))) # (!\z80_|interrupts_|DFFE_inst44~q & -// ((\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ) # ((\z80_|memory_ifc_|DFFE_m1_ff3~q )))) - - .dataa(\z80_|interrupts_|DFFE_inst44~q ), - .datab(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ), - .datac(\z80_|memory_ifc_|DFFE_m1_ff3~q ), - .datad(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|nRD_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|nRD_out~0 .lut_mask = 16'hFC54; -defparam \z80_|memory_ifc_|nRD_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N18 -cycloneive_lcell_comb \z80_|memory_ifc_|nRD_out~2 ( -// Equation(s): -// \z80_|memory_ifc_|nRD_out~2_combout = ((\z80_|memory_ifc_|nRD_out~0_combout ) # ((\z80_|memory_ifc_|iorq~0_combout & \z80_|execute_|fIORead~3_combout ))) # (!\z80_|memory_ifc_|nRD_out~1_combout ) - - .dataa(\z80_|memory_ifc_|nRD_out~1_combout ), - .datab(\z80_|memory_ifc_|iorq~0_combout ), - .datac(\z80_|execute_|fIORead~3_combout ), - .datad(\z80_|memory_ifc_|nRD_out~0_combout ), - .cin(gnd), - .combout(\z80_|memory_ifc_|nRD_out~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|nRD_out~2 .lut_mask = 16'hFFD5; -defparam \z80_|memory_ifc_|nRD_out~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N24 -cycloneive_lcell_comb \Equal2~1 ( -// Equation(s): -// \Equal2~1_combout = (!\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|memory_ifc_|nRD_out~2_combout & \z80_|resets_|SYNTHESIZED_WIRE_12~q )) - - .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), - .datab(\z80_|memory_ifc_|nRD_out~2_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(gnd), - .cin(gnd), - .combout(\Equal2~1_combout ), - .cout()); -// synopsys translate_off -defparam \Equal2~1 .lut_mask = 16'h4040; -defparam \Equal2~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N30 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~0 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~0_combout = (\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~0 .lut_mask = 16'hFFAA; -defparam \z80_|pin_control_|bus_db_pin_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y18_N10 -cycloneive_lcell_comb \z80_|execute_|fMWrite~5 ( -// Equation(s): -// \z80_|execute_|fMWrite~5_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|sequencer_|DFFE_M4_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~5 .lut_mask = 16'h3F33; -defparam \z80_|execute_|fMWrite~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N8 -cycloneive_lcell_comb \z80_|execute_|fMWrite~6 ( -// Equation(s): -// \z80_|execute_|fMWrite~6_combout = (!\z80_|execute_|fMWrite~5_combout & ((\z80_|execute_|ctl_mRead~7_combout ) # ((\z80_|pla_decode_|Equal13~2_combout ) # (\z80_|execute_|ctl_mWrite~5_combout )))) - - .dataa(\z80_|execute_|fMWrite~5_combout ), - .datab(\z80_|execute_|ctl_mRead~7_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|ctl_mWrite~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~6 .lut_mask = 16'h5554; -defparam \z80_|execute_|fMWrite~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N30 -cycloneive_lcell_comb \z80_|execute_|fMWrite~2 ( -// Equation(s): -// \z80_|execute_|fMWrite~2_combout = ((!\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|M5~q ) - - .dataa(\z80_|sequencer_|M5~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~2 .lut_mask = 16'h555F; -defparam \z80_|execute_|fMWrite~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N2 -cycloneive_lcell_comb \z80_|execute_|fMWrite~4 ( -// Equation(s): -// \z80_|execute_|fMWrite~4_combout = (!\z80_|execute_|fMWrite~3_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ixy_d~6_combout ) # (!\z80_|execute_|fMWrite~2_combout )))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|execute_|fMWrite~2_combout ), - .datad(\z80_|execute_|fMWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~4 .lut_mask = 16'h00EF; -defparam \z80_|execute_|fMWrite~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N20 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~1 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~1_combout = (\z80_|execute_|ctl_bus_inc_oe~24_combout & (!\z80_|execute_|fIOWrite~5_combout & (!\z80_|execute_|fMWrite~6_combout & !\z80_|execute_|fMWrite~4_combout ))) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~24_combout ), - .datab(\z80_|execute_|fIOWrite~5_combout ), - .datac(\z80_|execute_|fMWrite~6_combout ), - .datad(\z80_|execute_|fMWrite~4_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~1 .lut_mask = 16'h0002; -defparam \z80_|pin_control_|bus_db_pin_oe~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N30 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~2 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~2_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|pla_decode_|Equal11~0_combout & ((!\z80_|execute_|ctl_mRead~8_combout ) # (!\z80_|execute_|ctl_reg_in_hi~2_combout )))) # (!\z80_|execute_|ixy_d~7_combout & -// (((!\z80_|execute_|ctl_mRead~8_combout )) # (!\z80_|execute_|ctl_reg_in_hi~2_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|execute_|ctl_mRead~8_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~2 .lut_mask = 16'h135F; -defparam \z80_|pin_control_|bus_db_pin_oe~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N24 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~3 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~3_combout = (\z80_|pin_control_|bus_db_pin_oe~2_combout & (((\z80_|execute_|ixy_d~4_combout ) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|execute_|ctl_mWrite~5_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~2_combout ), - .datab(\z80_|execute_|ctl_mWrite~5_combout ), - .datac(\z80_|execute_|ixy_d~4_combout ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~3 .lut_mask = 16'hA2AA; -defparam \z80_|pin_control_|bus_db_pin_oe~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N8 -cycloneive_lcell_comb \z80_|execute_|fMWrite~7 ( -// Equation(s): -// \z80_|execute_|fMWrite~7_combout = (!\z80_|execute_|ctl_mWrite~16_combout & (!\z80_|execute_|ctl_mWrite~4_combout & !\z80_|execute_|ctl_mRead~7_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_mWrite~16_combout ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|execute_|ctl_mRead~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~7 .lut_mask = 16'h0003; -defparam \z80_|execute_|fMWrite~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N30 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~4 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~4_combout = (\z80_|execute_|ctl_inc_dec~2_combout & ((\z80_|execute_|fMWrite~7_combout ) # ((!\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ixy_d~6_combout )))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|fMWrite~7_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|execute_|ctl_inc_dec~2_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~4 .lut_mask = 16'hCD00; -defparam \z80_|pin_control_|bus_db_pin_oe~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N10 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~7 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~7_combout = (\z80_|execute_|ctl_ir_we~4_combout & (!\z80_|execute_|ctl_mRead~10_combout & ((!\z80_|execute_|ctl_mRead~7_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|execute_|ctl_ir_we~4_combout & -// (((!\z80_|execute_|ctl_mRead~7_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ctl_mRead~10_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|execute_|ctl_mRead~7_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~7 .lut_mask = 16'h0777; -defparam \z80_|pin_control_|bus_db_pin_oe~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N4 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~6 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~6_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|execute_|ctl_mRead~6_combout & ((\z80_|execute_|fMRead~1_combout )))) # (!\z80_|execute_|ixy_d~7_combout & (((!\z80_|execute_|ctl_alu_oe~2_combout )) # -// (!\z80_|execute_|ctl_mRead~6_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|execute_|ctl_alu_oe~2_combout ), - .datad(\z80_|execute_|fMRead~1_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~6 .lut_mask = 16'h3715; -defparam \z80_|pin_control_|bus_db_pin_oe~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|fMWrite~9 ( -// Equation(s): -// \z80_|execute_|fMWrite~9_combout = (\z80_|pla_decode_|Equal46~0_combout ) # (((\z80_|ir_|opcode [6] & !\z80_|ir_|opcode [7])) # (!\z80_|execute_|ctl_ir_we~5_combout )) - - .dataa(\z80_|ir_|opcode [6]), - .datab(\z80_|pla_decode_|Equal46~0_combout ), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|execute_|ctl_ir_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~9 .lut_mask = 16'hCEFF; -defparam \z80_|execute_|fMWrite~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N22 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~8 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~8_combout = (\z80_|execute_|ctl_mWrite~6_combout & (\z80_|execute_|fIOWrite~0_combout & ((\z80_|execute_|fMWrite~2_combout ) # (\z80_|execute_|fMWrite~9_combout )))) # (!\z80_|execute_|ctl_mWrite~6_combout & -// (((\z80_|execute_|fMWrite~2_combout ) # (\z80_|execute_|fMWrite~9_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~6_combout ), - .datab(\z80_|execute_|fIOWrite~0_combout ), - .datac(\z80_|execute_|fMWrite~2_combout ), - .datad(\z80_|execute_|fMWrite~9_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~8 .lut_mask = 16'hDDD0; -defparam \z80_|pin_control_|bus_db_pin_oe~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N0 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~9 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~9_combout = (\z80_|pin_control_|bus_db_pin_oe~8_combout & (\z80_|execute_|fMWrite~11_combout & !\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout )) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~8_combout ), - .datab(\z80_|execute_|fMWrite~11_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~9 .lut_mask = 16'h0808; -defparam \z80_|pin_control_|bus_db_pin_oe~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N26 -cycloneive_lcell_comb \z80_|execute_|fMWrite~8 ( -// Equation(s): -// \z80_|execute_|fMWrite~8_combout = (\z80_|execute_|ctl_state_alu~6_combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # ((\z80_|execute_|ctl_mRead~7_combout ) # (\z80_|execute_|ctl_mRead~9_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~5_combout ), - .datab(\z80_|execute_|ctl_mRead~7_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_mRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~8 .lut_mask = 16'hF0E0; -defparam \z80_|execute_|fMWrite~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N26 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~5 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~5_combout = (\z80_|execute_|ctl_reg_sel_wz~4_combout & (\z80_|execute_|ctl_reg_sel_wz~5_combout & (!\z80_|execute_|fMWrite~8_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~4_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~5_combout ), - .datac(\z80_|execute_|fMWrite~8_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~5 .lut_mask = 16'h0800; -defparam \z80_|pin_control_|bus_db_pin_oe~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N20 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~10 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~10_combout = (\z80_|pin_control_|bus_db_pin_oe~7_combout & (\z80_|pin_control_|bus_db_pin_oe~6_combout & (\z80_|pin_control_|bus_db_pin_oe~9_combout & \z80_|pin_control_|bus_db_pin_oe~5_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~7_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~6_combout ), - .datac(\z80_|pin_control_|bus_db_pin_oe~9_combout ), - .datad(\z80_|pin_control_|bus_db_pin_oe~5_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~10 .lut_mask = 16'h8000; -defparam \z80_|pin_control_|bus_db_pin_oe~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N22 -cycloneive_lcell_comb \z80_|execute_|fMWrite~10 ( -// Equation(s): -// \z80_|execute_|fMWrite~10_combout = (\z80_|execute_|ctl_reg_in_hi~2_combout & ((\z80_|pla_decode_|Equal9~1_combout ) # ((\z80_|execute_|ctl_mRead~10_combout )))) # (!\z80_|execute_|ctl_reg_in_hi~2_combout & (\z80_|execute_|ctl_alu_oe~2_combout & -// ((\z80_|pla_decode_|Equal9~1_combout ) # (\z80_|execute_|ctl_mRead~10_combout )))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datab(\z80_|pla_decode_|Equal9~1_combout ), - .datac(\z80_|execute_|ctl_alu_oe~2_combout ), - .datad(\z80_|execute_|ctl_mRead~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~10 .lut_mask = 16'hFAC8; -defparam \z80_|execute_|fMWrite~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N0 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~11 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~11_combout = (\z80_|pin_control_|bus_db_pin_oe~4_combout & (\z80_|pin_control_|bus_db_pin_oe~10_combout & (!\z80_|execute_|fMWrite~10_combout & \z80_|execute_|ctl_bus_inc_oe~28_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~4_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~10_combout ), - .datac(\z80_|execute_|fMWrite~10_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~28_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~11 .lut_mask = 16'h0800; -defparam \z80_|pin_control_|bus_db_pin_oe~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N26 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~12 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~12_combout = (\z80_|pin_control_|bus_db_pin_oe~3_combout & (\z80_|pin_control_|bus_db_pin_oe~11_combout & ((!\z80_|execute_|ixy_d~6_combout ) # (!\z80_|pla_decode_|Equal11~0_combout )))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~3_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|pin_control_|bus_db_pin_oe~11_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~12 .lut_mask = 16'h2A00; -defparam \z80_|pin_control_|bus_db_pin_oe~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N22 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~13 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~13_combout = (\z80_|execute_|ctl_apin_mux~0_combout & (\z80_|pin_control_|bus_db_pin_oe~1_combout & (\z80_|pin_control_|bus_db_pin_oe~12_combout & \z80_|execute_|ctl_inc_cy~37_combout ))) - - .dataa(\z80_|execute_|ctl_apin_mux~0_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~1_combout ), - .datac(\z80_|pin_control_|bus_db_pin_oe~12_combout ), - .datad(\z80_|execute_|ctl_inc_cy~37_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~13 .lut_mask = 16'h8000; -defparam \z80_|pin_control_|bus_db_pin_oe~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N28 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~14 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~14_combout = (\z80_|pin_control_|bus_db_pin_oe~0_combout & (((\z80_|sequencer_|DFFE_T4_ff~q & \z80_|execute_|fIOWrite~5_combout )) # (!\z80_|pin_control_|bus_db_pin_oe~13_combout ))) # -// (!\z80_|pin_control_|bus_db_pin_oe~0_combout & (((\z80_|sequencer_|DFFE_T4_ff~q & \z80_|execute_|fIOWrite~5_combout )))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~0_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~13_combout ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|execute_|fIOWrite~5_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~14 .lut_mask = 16'hF222; -defparam \z80_|pin_control_|bus_db_pin_oe~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N0 -cycloneive_lcell_comb \z80_|clk_delay_|DFF_inst5~feeder ( -// Equation(s): -// \z80_|clk_delay_|DFF_inst5~feeder_combout = \z80_|clk_delay_|SYNTHESIZED_WIRE_7~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ), - .cin(gnd), - .combout(\z80_|clk_delay_|DFF_inst5~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|clk_delay_|DFF_inst5~feeder .lut_mask = 16'hFF00; -defparam \z80_|clk_delay_|DFF_inst5~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X43_Y15_N1 -dffeas \z80_|clk_delay_|DFF_inst5 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|clk_delay_|DFF_inst5~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|clk_delay_|DFF_inst5~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|clk_delay_|DFF_inst5 .is_wysiwyg = "true"; -defparam \z80_|clk_delay_|DFF_inst5 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N22 -cycloneive_lcell_comb \z80_|memory_ifc_|wait_iorqinta~feeder ( -// Equation(s): -// \z80_|memory_ifc_|wait_iorqinta~feeder_combout = \z80_|clk_delay_|DFF_inst5~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|clk_delay_|DFF_inst5~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|wait_iorqinta~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_iorqinta~feeder .lut_mask = 16'hFF00; -defparam \z80_|memory_ifc_|wait_iorqinta~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X43_Y15_N23 -dffeas \z80_|memory_ifc_|wait_iorqinta ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|memory_ifc_|wait_iorqinta~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|wait_iorqinta~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_iorqinta .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|wait_iorqinta .power_up = "low"; -// synopsys translate_on - -// Location: FF_X43_Y15_N13 -dffeas \z80_|memory_ifc_|DFFE_intr_ff3 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|memory_ifc_|wait_iorqinta~q ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_intr_ff3~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_intr_ff3 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_intr_ff3 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N12 -cycloneive_lcell_comb \z80_|memory_ifc_|nIORQ_out~0 ( -// Equation(s): -// \z80_|memory_ifc_|nIORQ_out~0_combout = (\z80_|memory_ifc_|wait_iorqinta~q ) # ((\z80_|memory_ifc_|DFFE_intr_ff3~q ) # (\z80_|memory_ifc_|iorq~0_combout )) - - .dataa(\z80_|memory_ifc_|wait_iorqinta~q ), - .datab(gnd), - .datac(\z80_|memory_ifc_|DFFE_intr_ff3~q ), - .datad(\z80_|memory_ifc_|iorq~0_combout ), - .cin(gnd), - .combout(\z80_|memory_ifc_|nIORQ_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|nIORQ_out~0 .lut_mask = 16'hFFFA; -defparam \z80_|memory_ifc_|nIORQ_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N18 -cycloneive_lcell_comb \Equal2~0 ( -// Equation(s): -// \Equal2~0_combout = (!\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|memory_ifc_|nRD_out~2_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \z80_|memory_ifc_|nIORQ_out~0_combout ))) - - .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), - .datab(\z80_|memory_ifc_|nRD_out~2_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|memory_ifc_|nIORQ_out~0_combout ), - .cin(gnd), - .combout(\Equal2~0_combout ), - .cout()); -// synopsys translate_off -defparam \Equal2~0 .lut_mask = 16'h4000; -defparam \Equal2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N22 -cycloneive_lcell_comb \ExtRamWE~0 ( -// Equation(s): -// \ExtRamWE~0_combout = (\z80_|memory_ifc_|nWR_out~0_combout & (!\z80_|memory_ifc_|nRD_out~2_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|memory_ifc_|nIORQ_out~0_combout ))) - - .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), - .datab(\z80_|memory_ifc_|nRD_out~2_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|memory_ifc_|nIORQ_out~0_combout ), - .cin(gnd), - .combout(\ExtRamWE~0_combout ), - .cout()); -// synopsys translate_off -defparam \ExtRamWE~0 .lut_mask = 16'h0020; -defparam \ExtRamWE~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N18 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[13]~13 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[13]~13_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [13]))) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [13]), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[13]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[13]~13 .lut_mask = 16'hDD88; -defparam \z80_|address_pins_|DFFE_apin_latch[13]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux2~0 ( -// Equation(s): -// \z80_|execute_|ctl_apin_mux2~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_apin_mux2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_apin_mux2~0 .lut_mask = 16'h0B0B; -defparam \z80_|execute_|ctl_apin_mux2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N28 -cycloneive_lcell_comb \z80_|pin_control_|bus_ab_pin_we~2 ( -// Equation(s): -// \z80_|pin_control_|bus_ab_pin_we~2_combout = (((\z80_|execute_|fMRead~35_combout ) # (\z80_|execute_|fIORead~3_combout )) # (!\z80_|pin_control_|bus_db_pin_oe~13_combout )) # (!\z80_|sequencer_|DFFE_M1_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|pin_control_|bus_db_pin_oe~13_combout ), - .datac(\z80_|execute_|fMRead~35_combout ), - .datad(\z80_|execute_|fIORead~3_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_ab_pin_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_ab_pin_we~2 .lut_mask = 16'hFFF7; -defparam \z80_|pin_control_|bus_ab_pin_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N2 -cycloneive_lcell_comb \z80_|pin_control_|bus_ab_pin_we~3 ( -// Equation(s): -// \z80_|pin_control_|bus_ab_pin_we~3_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (((!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|pin_control_|bus_ab_pin_we~2_combout )) # (!\z80_|sequencer_|DFFE_M1_ff~q ))) # (!\z80_|sequencer_|DFFE_T3_ff~q & -// (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|pin_control_|bus_ab_pin_we~2_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|pin_control_|bus_ab_pin_we~2_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_ab_pin_we~3 .lut_mask = 16'h3B0A; -defparam \z80_|pin_control_|bus_ab_pin_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N19 -dffeas \z80_|address_pins_|DFFE_apin_latch[13] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[13]~13_combout ), - .asdata(\z80_|address_latch_|Q [13]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [13]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[13] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[13] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N0 -cycloneive_lcell_comb \z80_|address_pins_|abus[13]~20 ( -// Equation(s): -// \z80_|address_pins_|abus[13]~20_combout = (\z80_|address_pins_|DFFE_apin_latch [13]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [13]), - .datab(gnd), - .datac(gnd), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\z80_|address_pins_|abus[13]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[13]~20 .lut_mask = 16'hAAFF; -defparam \z80_|address_pins_|abus[13]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N28 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[14]~14 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[14]~14_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|address [14])) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [14]))) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [14]), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[14]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[14]~14 .lut_mask = 16'hDD88; -defparam \z80_|address_pins_|DFFE_apin_latch[14]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N29 -dffeas \z80_|address_pins_|DFFE_apin_latch[14] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[14]~14_combout ), - .asdata(\z80_|address_latch_|Q [14]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [14]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[14] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[14] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N4 -cycloneive_lcell_comb \z80_|address_pins_|abus[14]~23 ( -// Equation(s): -// \z80_|address_pins_|abus[14]~23_combout = (\z80_|address_pins_|DFFE_apin_latch [14]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(gnd), - .datad(\z80_|address_pins_|DFFE_apin_latch [14]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[14]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[14]~23 .lut_mask = 16'hFF33; -defparam \z80_|address_pins_|abus[14]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N10 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[15]~15 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[15]~15_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [15]))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [15])) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|abusz [15]), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|address [15]), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[15]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[15]~15 .lut_mask = 16'hEE44; -defparam \z80_|address_pins_|DFFE_apin_latch[15]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N11 -dffeas \z80_|address_pins_|DFFE_apin_latch[15] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[15]~15_combout ), - .asdata(\z80_|address_latch_|Q [15]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [15]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[15] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[15] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y15_N12 -cycloneive_lcell_comb \z80_|address_pins_|abus[15]~22 ( -// Equation(s): -// \z80_|address_pins_|abus[15]~22_combout = (\z80_|address_pins_|DFFE_apin_latch [15]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [15]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_pins_|abus[15]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[15]~22 .lut_mask = 16'hF3F3; -defparam \z80_|address_pins_|abus[15]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N8 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2] = (\ExtRamWE~0_combout & (\z80_|address_pins_|abus[13]~20_combout & (!\z80_|address_pins_|abus[14]~23_combout & \z80_|address_pins_|abus[15]~22_combout ))) - - .dataa(\ExtRamWE~0_combout ), - .datab(\z80_|address_pins_|abus[13]~20_combout ), - .datac(\z80_|address_pins_|abus[14]~23_combout ), - .datad(\z80_|address_pins_|abus[15]~22_combout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] .lut_mask = 16'h0800; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N22 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\z80_|address_pins_|DFFE_apin_latch [13] & !\z80_|address_pins_|DFFE_apin_latch [14])) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [13]), - .datad(\z80_|address_pins_|DFFE_apin_latch [14]), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 .lut_mask = 16'h00C0; -defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N0 -cycloneive_lcell_comb \z80_|address_pins_|abus[0]~16 ( -// Equation(s): -// \z80_|address_pins_|abus[0]~16_combout = (\z80_|address_pins_|DFFE_apin_latch [0]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [0]), - .datab(gnd), - .datac(gnd), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\z80_|address_pins_|abus[0]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[0]~16 .lut_mask = 16'hAAFF; -defparam \z80_|address_pins_|abus[0]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N28 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[1]~1 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[1]~1_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [1]))) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [1]), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[1]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[1]~1 .lut_mask = 16'hDD88; -defparam \z80_|address_pins_|DFFE_apin_latch[1]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y17_N29 -dffeas \z80_|address_pins_|DFFE_apin_latch[1] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[1]~1_combout ), - .asdata(\z80_|address_latch_|Q [1]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[1] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y18_N20 -cycloneive_lcell_comb \z80_|address_pins_|abus[1]~25 ( -// Equation(s): -// \z80_|address_pins_|abus[1]~25_combout = (\z80_|address_pins_|DFFE_apin_latch [1]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_pins_|DFFE_apin_latch [1]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[1]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[1]~25 .lut_mask = 16'hFF55; -defparam \z80_|address_pins_|abus[1]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N18 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[2]~2 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[2]~2_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [2])) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|abusz [2]), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[2]~2 .lut_mask = 16'hEE44; -defparam \z80_|address_pins_|DFFE_apin_latch[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y17_N19 -dffeas \z80_|address_pins_|DFFE_apin_latch[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[2]~2_combout ), - .asdata(\z80_|address_latch_|Q [2]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[2] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y18_N26 -cycloneive_lcell_comb \z80_|address_pins_|abus[2]~26 ( -// Equation(s): -// \z80_|address_pins_|abus[2]~26_combout = (\z80_|address_pins_|DFFE_apin_latch [2]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|address_pins_|DFFE_apin_latch [2]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[2]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[2]~26 .lut_mask = 16'hFF0F; -defparam \z80_|address_pins_|abus[2]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N0 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[3]~3 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[3]~3_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [3])) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|abusz [3]), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[3]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[3]~3 .lut_mask = 16'hEE44; -defparam \z80_|address_pins_|DFFE_apin_latch[3]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y17_N1 -dffeas \z80_|address_pins_|DFFE_apin_latch[3] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[3]~3_combout ), - .asdata(\z80_|address_latch_|Q [3]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[3] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y18_N12 -cycloneive_lcell_comb \z80_|address_pins_|abus[3]~27 ( -// Equation(s): -// \z80_|address_pins_|abus[3]~27_combout = (\z80_|address_pins_|DFFE_apin_latch [3]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|address_pins_|DFFE_apin_latch [3]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[3]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[3]~27 .lut_mask = 16'hFF0F; -defparam \z80_|address_pins_|abus[3]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N30 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[4]~4 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[4]~4_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [4])) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|abusz [4]), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[4]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[4]~4 .lut_mask = 16'hEE44; -defparam \z80_|address_pins_|DFFE_apin_latch[4]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y17_N31 -dffeas \z80_|address_pins_|DFFE_apin_latch[4] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[4]~4_combout ), - .asdata(\z80_|address_latch_|Q [4]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[4] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y18_N2 -cycloneive_lcell_comb \z80_|address_pins_|abus[4]~28 ( -// Equation(s): -// \z80_|address_pins_|abus[4]~28_combout = (\z80_|address_pins_|DFFE_apin_latch [4]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|address_pins_|DFFE_apin_latch [4]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[4]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[4]~28 .lut_mask = 16'hFF0F; -defparam \z80_|address_pins_|abus[4]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N12 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[5]~5 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[5]~5_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [5])) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|abusz [5]), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[5]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[5]~5 .lut_mask = 16'hEE44; -defparam \z80_|address_pins_|DFFE_apin_latch[5]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y16_N13 -dffeas \z80_|address_pins_|DFFE_apin_latch[5] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[5]~5_combout ), - .asdata(\z80_|address_latch_|Q [5]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[5] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N20 -cycloneive_lcell_comb \z80_|address_pins_|abus[5]~29 ( -// Equation(s): -// \z80_|address_pins_|abus[5]~29_combout = (\z80_|address_pins_|DFFE_apin_latch [5]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [5]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_pins_|abus[5]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[5]~29 .lut_mask = 16'hF3F3; -defparam \z80_|address_pins_|abus[5]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N10 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[6]~6 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[6]~6_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [6]))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [6])) - - .dataa(\z80_|address_latch_|abusz [6]), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), - .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[6]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[6]~6 .lut_mask = 16'hCCAA; -defparam \z80_|address_pins_|DFFE_apin_latch[6]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y16_N11 -dffeas \z80_|address_pins_|DFFE_apin_latch[6] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[6]~6_combout ), - .asdata(\z80_|address_latch_|Q [6]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[6] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y18_N28 -cycloneive_lcell_comb \z80_|address_pins_|abus[6]~30 ( -// Equation(s): -// \z80_|address_pins_|abus[6]~30_combout = (\z80_|address_pins_|DFFE_apin_latch [6]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|address_pins_|DFFE_apin_latch [6]), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_pins_|abus[6]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[6]~30 .lut_mask = 16'hCFCF; -defparam \z80_|address_pins_|abus[6]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N30 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[7]~7 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[7]~7_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [7])) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|abusz [7]), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[7]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[7]~7 .lut_mask = 16'hEE44; -defparam \z80_|address_pins_|DFFE_apin_latch[7]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y16_N31 -dffeas \z80_|address_pins_|DFFE_apin_latch[7] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[7]~7_combout ), - .asdata(\z80_|address_latch_|Q [7]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[7] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y18_N22 -cycloneive_lcell_comb \z80_|address_pins_|abus[7]~31 ( -// Equation(s): -// \z80_|address_pins_|abus[7]~31_combout = (\z80_|address_pins_|DFFE_apin_latch [7]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|address_pins_|DFFE_apin_latch [7]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[7]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[7]~31 .lut_mask = 16'hFF0F; -defparam \z80_|address_pins_|abus[7]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N20 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[8]~8 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[8]~8_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [8])) - - .dataa(\z80_|address_latch_|abusz [8]), - .datab(\z80_|execute_|ctl_apin_mux~2_combout ), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[8]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[8]~8 .lut_mask = 16'hEE22; -defparam \z80_|address_pins_|DFFE_apin_latch[8]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y16_N21 -dffeas \z80_|address_pins_|DFFE_apin_latch[8] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[8]~8_combout ), - .asdata(\z80_|address_latch_|Q [8]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [8]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[8] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N30 -cycloneive_lcell_comb \z80_|address_pins_|abus[8]~18 ( -// Equation(s): -// \z80_|address_pins_|abus[8]~18_combout = (\z80_|address_pins_|DFFE_apin_latch [8]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|address_pins_|DFFE_apin_latch [8]), - .datac(gnd), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\z80_|address_pins_|abus[8]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[8]~18 .lut_mask = 16'hCCFF; -defparam \z80_|address_pins_|abus[8]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N16 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[9]~9 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[9]~9_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [9]))) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [9]), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[9]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[9]~9 .lut_mask = 16'hDD88; -defparam \z80_|address_pins_|DFFE_apin_latch[9]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N17 -dffeas \z80_|address_pins_|DFFE_apin_latch[9] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[9]~9_combout ), - .asdata(\z80_|address_latch_|Q [9]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [9]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[9] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[9] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y18_N4 -cycloneive_lcell_comb \z80_|address_pins_|abus[9]~17 ( -// Equation(s): -// \z80_|address_pins_|abus[9]~17_combout = (\z80_|address_pins_|DFFE_apin_latch [9]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|address_pins_|DFFE_apin_latch [9]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[9]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[9]~17 .lut_mask = 16'hFF0F; -defparam \z80_|address_pins_|abus[9]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N24 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[10]~10 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[10]~10_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [10]))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), - .datab(\z80_|address_latch_|abusz [10]), - .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[10]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[10]~10 .lut_mask = 16'hAACC; -defparam \z80_|address_pins_|DFFE_apin_latch[10]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N25 -dffeas \z80_|address_pins_|DFFE_apin_latch[10] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[10]~10_combout ), - .asdata(\z80_|address_latch_|Q [10]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [10]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[10] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[10] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N24 -cycloneive_lcell_comb \z80_|address_pins_|abus[10]~24 ( -// Equation(s): -// \z80_|address_pins_|abus[10]~24_combout = (\z80_|address_pins_|DFFE_apin_latch [10]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|address_pins_|DFFE_apin_latch [10]), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\z80_|address_pins_|abus[10]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[10]~24 .lut_mask = 16'hF0FF; -defparam \z80_|address_pins_|abus[10]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N6 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[11]~11 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[11]~11_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|address [11])) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [11]))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), - .datab(\z80_|address_latch_|abusz [11]), - .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[11]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[11]~11 .lut_mask = 16'hAACC; -defparam \z80_|address_pins_|DFFE_apin_latch[11]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N7 -dffeas \z80_|address_pins_|DFFE_apin_latch[11] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[11]~11_combout ), - .asdata(\z80_|address_latch_|Q [11]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [11]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[11] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[11] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N8 -cycloneive_lcell_comb \z80_|address_pins_|abus[11]~19 ( -// Equation(s): -// \z80_|address_pins_|abus[11]~19_combout = (\z80_|address_pins_|DFFE_apin_latch [11]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [11]), - .datab(gnd), - .datac(gnd), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\z80_|address_pins_|abus[11]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[11]~19 .lut_mask = 16'hAAFF; -defparam \z80_|address_pins_|abus[11]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N16 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[12]~12 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[12]~12_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [12])) - - .dataa(\z80_|address_latch_|abusz [12]), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[12]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[12]~12 .lut_mask = 16'hCCAA; -defparam \z80_|address_pins_|DFFE_apin_latch[12]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N17 -dffeas \z80_|address_pins_|DFFE_apin_latch[12] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[12]~12_combout ), - .asdata(\z80_|address_latch_|Q [12]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [12]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[12] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[12] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y18_N30 -cycloneive_lcell_comb \z80_|address_pins_|abus[12]~21 ( -// Equation(s): -// \z80_|address_pins_|abus[12]~21_combout = (\z80_|address_pins_|DFFE_apin_latch [12]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_pins_|DFFE_apin_latch [12]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[12]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[12]~21 .lut_mask = 16'hFF55; -defparam \z80_|address_pins_|abus[12]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y11_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a14 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~101_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: FF_X32_Y14_N31 -dffeas \ram1|altsyncram_component|auto_generated|address_reg_a[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|address_pins_|abus[13]~20_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram1|altsyncram_component|auto_generated|address_reg_a [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true"; -defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X32_Y14_N1 -dffeas \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ram1|altsyncram_component|auto_generated|address_reg_a [0]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true"; -defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N12 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2] = (\ExtRamWE~0_combout & (!\z80_|address_pins_|abus[13]~20_combout & (!\z80_|address_pins_|abus[14]~23_combout & \z80_|address_pins_|abus[15]~22_combout ))) - - .dataa(\ExtRamWE~0_combout ), - .datab(\z80_|address_pins_|abus[13]~20_combout ), - .datac(\z80_|address_pins_|abus[14]~23_combout ), - .datad(\z80_|address_pins_|abus[15]~22_combout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] .lut_mask = 16'h0200; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N18 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (!\z80_|address_pins_|DFFE_apin_latch [13] & !\z80_|address_pins_|DFFE_apin_latch [14])) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [13]), - .datad(\z80_|address_pins_|DFFE_apin_latch [14]), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 .lut_mask = 16'h000C; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y10_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a6 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~101_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; -// synopsys translate_on - -// Location: FF_X29_Y14_N5 -dffeas \ram1|altsyncram_component|auto_generated|address_reg_a[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|address_pins_|abus[14]~23_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram1|altsyncram_component|auto_generated|address_reg_a [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1] .is_wysiwyg = "true"; -defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y14_N21 -dffeas \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ram1|altsyncram_component|auto_generated|address_reg_a [1]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] .is_wysiwyg = "true"; -defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N24 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2] = (\ExtRamWE~0_combout & (!\z80_|address_pins_|abus[13]~20_combout & (\z80_|address_pins_|abus[14]~23_combout & \z80_|address_pins_|abus[15]~22_combout ))) - - .dataa(\ExtRamWE~0_combout ), - .datab(\z80_|address_pins_|abus[13]~20_combout ), - .datac(\z80_|address_pins_|abus[14]~23_combout ), - .datad(\z80_|address_pins_|abus[15]~22_combout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] .lut_mask = 16'h2000; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N26 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (!\z80_|address_pins_|DFFE_apin_latch [13] & \z80_|address_pins_|DFFE_apin_latch [14])) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [13]), - .datad(\z80_|address_pins_|DFFE_apin_latch [14]), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 .lut_mask = 16'h0C00; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y10_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a22 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~101_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_first_bit_number = 6; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N10 -cycloneive_lcell_comb \D[6]~90 ( -// Equation(s): -// \D[6]~90_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ) # (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout & ((!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ), - .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .cin(gnd), - .combout(\D[6]~90_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~90 .lut_mask = 16'hCCE2; -defparam \D[6]~90 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N20 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2] = (\ExtRamWE~0_combout & (\z80_|address_pins_|abus[13]~20_combout & (\z80_|address_pins_|abus[14]~23_combout & \z80_|address_pins_|abus[15]~22_combout ))) - - .dataa(\ExtRamWE~0_combout ), - .datab(\z80_|address_pins_|abus[13]~20_combout ), - .datac(\z80_|address_pins_|abus[14]~23_combout ), - .datad(\z80_|address_pins_|abus[15]~22_combout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] .lut_mask = 16'h8000; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N6 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout = ((\z80_|address_pins_|DFFE_apin_latch [13] & \z80_|address_pins_|DFFE_apin_latch [14])) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [13]), - .datad(\z80_|address_pins_|DFFE_apin_latch [14]), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 .lut_mask = 16'hF333; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y6_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a30 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~101_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_first_bit_number = 6; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N16 -cycloneive_lcell_comb \D[6]~91 ( -// Equation(s): -// \D[6]~91_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[6]~90_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ))) # (!\D[6]~90_combout & -// (\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[6]~90_combout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\D[6]~90_combout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ), - .cin(gnd), - .combout(\D[6]~91_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~91 .lut_mask = 16'hF838; -defparam \D[6]~91 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N2 -cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0 ( -// Equation(s): -// \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout = (\ExtRamWE~0_combout & (!\z80_|address_pins_|abus[13]~20_combout & (\z80_|address_pins_|abus[14]~23_combout & !\z80_|address_pins_|abus[15]~22_combout ))) - - .dataa(\ExtRamWE~0_combout ), - .datab(\z80_|address_pins_|abus[13]~20_combout ), - .datac(\z80_|address_pins_|abus[14]~23_combout ), - .datad(\z80_|address_pins_|abus[15]~22_combout ), - .cin(gnd), - .combout(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0 .lut_mask = 16'h0020; -defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: CLKCTRL_G15 -cycloneive_clkctrl \CLOCK_50~inputclkctrl ( - .ena(vcc), - .inclk({vcc,vcc,vcc,\CLOCK_50~input_o }), - .clkselect(2'b00), - .devclrn(devclrn), - .devpor(devpor), - .outclk(\CLOCK_50~inputclkctrl_outclk )); -// synopsys translate_off -defparam \CLOCK_50~inputclkctrl .clock_type = "global clock"; -defparam \CLOCK_50~inputclkctrl .ena_register_mode = "none"; -// synopsys translate_on - -// Location: LCCOMB_X5_Y24_N16 -cycloneive_lcell_comb \~GND ( -// Equation(s): -// \~GND~combout = GND - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(gnd), - .cin(gnd), - .combout(\~GND~combout ), - .cout()); -// synopsys translate_off -defparam \~GND .lut_mask = 16'h0000; -defparam \~GND .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N20 -cycloneive_lcell_comb \ula_|video_|vram_address[0]~feeder ( -// Equation(s): -// \ula_|video_|vram_address[0]~feeder_combout = \ula_|video_|vga_hc [4] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|vga_hc [4]), - .cin(gnd), - .combout(\ula_|video_|vram_address[0]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address[0]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|vram_address[0]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N4 -cycloneive_lcell_comb \ula_|video_|vram_address~0 ( -// Equation(s): -// \ula_|video_|vram_address~0_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [2] $ (\ula_|video_|vga_hc [1])))) - - .dataa(\ula_|video_|vga_hc [2]), - .datab(\ula_|video_|vga_hc [3]), - .datac(\ula_|video_|vga_hc [1]), - .datad(\ula_|video_|vga_hc [0]), - .cin(gnd), - .combout(\ula_|video_|vram_address~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address~0 .lut_mask = 16'h0048; -defparam \ula_|video_|vram_address~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y33_N21 -dffeas \ula_|video_|vram_address[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vram_address[0]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[0] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X34_Y33_N19 -dffeas \ula_|video_|vram_address[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|vga_hc [5]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[1] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N0 -cycloneive_lcell_comb \ula_|video_|vram_address[2]~4 ( -// Equation(s): -// \ula_|video_|vram_address[2]~4_combout = !\ula_|video_|vga_hc [6] - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|video_|vga_hc [6]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|video_|vram_address[2]~4_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address[2]~4 .lut_mask = 16'h0F0F; -defparam \ula_|video_|vram_address[2]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y33_N1 -dffeas \ula_|video_|vram_address[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vram_address[2]~4_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[2] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N26 -cycloneive_lcell_comb \ula_|video_|Add3~0 ( -// Equation(s): -// \ula_|video_|Add3~0_combout = \ula_|video_|vga_hc [6] $ (\ula_|video_|vga_hc [7]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|video_|vga_hc [6]), - .datad(\ula_|video_|vga_hc [7]), - .cin(gnd), - .combout(\ula_|video_|Add3~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Add3~0 .lut_mask = 16'h0FF0; -defparam \ula_|video_|Add3~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y33_N27 -dffeas \ula_|video_|vram_address[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Add3~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[3] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N28 -cycloneive_lcell_comb \ula_|video_|Add3~1 ( -// Equation(s): -// \ula_|video_|Add3~1_combout = \ula_|video_|vga_hc [8] $ (((!\ula_|video_|vga_hc [7]) # (!\ula_|video_|vga_hc [6]))) - - .dataa(\ula_|video_|vga_hc [6]), - .datab(gnd), - .datac(\ula_|video_|vga_hc [8]), - .datad(\ula_|video_|vga_hc [7]), - .cin(gnd), - .combout(\ula_|video_|Add3~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Add3~1 .lut_mask = 16'hA50F; -defparam \ula_|video_|Add3~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y33_N29 -dffeas \ula_|video_|vram_address[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Add3~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[4] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N2 -cycloneive_lcell_comb \ula_|video_|Add4~0 ( -// Equation(s): -// \ula_|video_|Add4~0_combout = (\ula_|video_|vga_vc [0] & (\ula_|video_|vga_vc [1] $ (VCC))) # (!\ula_|video_|vga_vc [0] & (\ula_|video_|vga_vc [1] & VCC)) -// \ula_|video_|Add4~1 = CARRY((\ula_|video_|vga_vc [0] & \ula_|video_|vga_vc [1])) - - .dataa(\ula_|video_|vga_vc [0]), - .datab(\ula_|video_|vga_vc [1]), - .datac(gnd), - .datad(vcc), - .cin(gnd), - .combout(\ula_|video_|Add4~0_combout ), - .cout(\ula_|video_|Add4~1 )); -// synopsys translate_off -defparam \ula_|video_|Add4~0 .lut_mask = 16'h6688; -defparam \ula_|video_|Add4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N4 -cycloneive_lcell_comb \ula_|video_|Add4~2 ( -// Equation(s): -// \ula_|video_|Add4~2_combout = (\ula_|video_|vga_vc [2] & (\ula_|video_|Add4~1 & VCC)) # (!\ula_|video_|vga_vc [2] & (!\ula_|video_|Add4~1 )) -// \ula_|video_|Add4~3 = CARRY((!\ula_|video_|vga_vc [2] & !\ula_|video_|Add4~1 )) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [2]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~1 ), - .combout(\ula_|video_|Add4~2_combout ), - .cout(\ula_|video_|Add4~3 )); -// synopsys translate_off -defparam \ula_|video_|Add4~2 .lut_mask = 16'hC303; -defparam \ula_|video_|Add4~2 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N6 -cycloneive_lcell_comb \ula_|video_|Add4~4 ( -// Equation(s): -// \ula_|video_|Add4~4_combout = (\ula_|video_|vga_vc [3] & ((GND) # (!\ula_|video_|Add4~3 ))) # (!\ula_|video_|vga_vc [3] & (\ula_|video_|Add4~3 $ (GND))) -// \ula_|video_|Add4~5 = CARRY((\ula_|video_|vga_vc [3]) # (!\ula_|video_|Add4~3 )) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [3]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~3 ), - .combout(\ula_|video_|Add4~4_combout ), - .cout(\ula_|video_|Add4~5 )); -// synopsys translate_off -defparam \ula_|video_|Add4~4 .lut_mask = 16'h3CCF; -defparam \ula_|video_|Add4~4 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N8 -cycloneive_lcell_comb \ula_|video_|Add4~6 ( -// Equation(s): -// \ula_|video_|Add4~6_combout = (\ula_|video_|vga_vc [4] & (!\ula_|video_|Add4~5 )) # (!\ula_|video_|vga_vc [4] & ((\ula_|video_|Add4~5 ) # (GND))) -// \ula_|video_|Add4~7 = CARRY((!\ula_|video_|Add4~5 ) # (!\ula_|video_|vga_vc [4])) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [4]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~5 ), - .combout(\ula_|video_|Add4~6_combout ), - .cout(\ula_|video_|Add4~7 )); -// synopsys translate_off -defparam \ula_|video_|Add4~6 .lut_mask = 16'h3C3F; -defparam \ula_|video_|Add4~6 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X34_Y33_N9 -dffeas \ula_|video_|vram_address[5] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Add4~6_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[5] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N10 -cycloneive_lcell_comb \ula_|video_|Add4~8 ( -// Equation(s): -// \ula_|video_|Add4~8_combout = (\ula_|video_|vga_vc [5] & ((GND) # (!\ula_|video_|Add4~7 ))) # (!\ula_|video_|vga_vc [5] & (\ula_|video_|Add4~7 $ (GND))) -// \ula_|video_|Add4~9 = CARRY((\ula_|video_|vga_vc [5]) # (!\ula_|video_|Add4~7 )) - - .dataa(\ula_|video_|vga_vc [5]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~7 ), - .combout(\ula_|video_|Add4~8_combout ), - .cout(\ula_|video_|Add4~9 )); -// synopsys translate_off -defparam \ula_|video_|Add4~8 .lut_mask = 16'h5AAF; -defparam \ula_|video_|Add4~8 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X34_Y33_N11 -dffeas \ula_|video_|vram_address[6] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Add4~8_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[6] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N12 -cycloneive_lcell_comb \ula_|video_|Add4~10 ( -// Equation(s): -// \ula_|video_|Add4~10_combout = (\ula_|video_|vga_vc [6] & (!\ula_|video_|Add4~9 )) # (!\ula_|video_|vga_vc [6] & ((\ula_|video_|Add4~9 ) # (GND))) -// \ula_|video_|Add4~11 = CARRY((!\ula_|video_|Add4~9 ) # (!\ula_|video_|vga_vc [6])) - - .dataa(\ula_|video_|vga_vc [6]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~9 ), - .combout(\ula_|video_|Add4~10_combout ), - .cout(\ula_|video_|Add4~11 )); -// synopsys translate_off -defparam \ula_|video_|Add4~10 .lut_mask = 16'h5A5F; -defparam \ula_|video_|Add4~10 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X34_Y33_N13 -dffeas \ula_|video_|vram_address[7] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Add4~10_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[7] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N14 -cycloneive_lcell_comb \ula_|video_|Add4~12 ( -// Equation(s): -// \ula_|video_|Add4~12_combout = (\ula_|video_|vga_vc [7] & ((GND) # (!\ula_|video_|Add4~11 ))) # (!\ula_|video_|vga_vc [7] & (\ula_|video_|Add4~11 $ (GND))) -// \ula_|video_|Add4~13 = CARRY((\ula_|video_|vga_vc [7]) # (!\ula_|video_|Add4~11 )) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [7]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~11 ), - .combout(\ula_|video_|Add4~12_combout ), - .cout(\ula_|video_|Add4~13 )); -// synopsys translate_off -defparam \ula_|video_|Add4~12 .lut_mask = 16'h3CCF; -defparam \ula_|video_|Add4~12 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N22 -cycloneive_lcell_comb \ula_|video_|Selector6~0 ( -// Equation(s): -// \ula_|video_|Selector6~0_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|Add4~12_combout )) # (!\ula_|video_|vga_hc [2] & ((\ula_|video_|Add4~0_combout ))) - - .dataa(gnd), - .datab(\ula_|video_|Add4~12_combout ), - .datac(\ula_|video_|Add4~0_combout ), - .datad(\ula_|video_|vga_hc [2]), - .cin(gnd), - .combout(\ula_|video_|Selector6~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Selector6~0 .lut_mask = 16'hCCF0; -defparam \ula_|video_|Selector6~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N14 -cycloneive_lcell_comb \ula_|video_|vram_address[9]~1 ( -// Equation(s): -// \ula_|video_|vram_address[9]~1_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [2] $ (\ula_|video_|vga_hc [1])))) - - .dataa(\ula_|video_|vga_hc [2]), - .datab(\ula_|video_|vga_hc [3]), - .datac(\ula_|video_|vga_hc [1]), - .datad(\ula_|video_|vga_hc [0]), - .cin(gnd), - .combout(\ula_|video_|vram_address[9]~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address[9]~1 .lut_mask = 16'h0048; -defparam \ula_|video_|vram_address[9]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y31_N23 -dffeas \ula_|video_|vram_address[8] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Selector6~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address[9]~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [8]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[8] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N16 -cycloneive_lcell_comb \ula_|video_|Add4~14 ( -// Equation(s): -// \ula_|video_|Add4~14_combout = \ula_|video_|Add4~13 $ (!\ula_|video_|vga_vc [8]) - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|vga_vc [8]), - .cin(\ula_|video_|Add4~13 ), - .combout(\ula_|video_|Add4~14_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Add4~14 .lut_mask = 16'hF00F; -defparam \ula_|video_|Add4~14 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N20 -cycloneive_lcell_comb \ula_|video_|Selector5~0 ( -// Equation(s): -// \ula_|video_|Selector5~0_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|Add4~14_combout )) # (!\ula_|video_|vga_hc [2] & ((\ula_|video_|Add4~2_combout ))) - - .dataa(\ula_|video_|Add4~14_combout ), - .datab(gnd), - .datac(\ula_|video_|Add4~2_combout ), - .datad(\ula_|video_|vga_hc [2]), - .cin(gnd), - .combout(\ula_|video_|Selector5~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Selector5~0 .lut_mask = 16'hAAF0; -defparam \ula_|video_|Selector5~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y31_N21 -dffeas \ula_|video_|vram_address[9] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Selector5~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address[9]~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [9]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[9] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[9] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N28 -cycloneive_lcell_comb \ula_|video_|vram_address[10]~2 ( -// Equation(s): -// \ula_|video_|vram_address[10]~2_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [2] $ (\ula_|video_|vga_hc [1])))) - - .dataa(\ula_|video_|vga_hc [2]), - .datab(\ula_|video_|vga_hc [3]), - .datac(\ula_|video_|vga_hc [1]), - .datad(\ula_|video_|vga_hc [0]), - .cin(gnd), - .combout(\ula_|video_|vram_address[10]~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address[10]~2 .lut_mask = 16'h0048; -defparam \ula_|video_|vram_address[10]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N30 -cycloneive_lcell_comb \ula_|video_|vram_address[10]~3 ( -// Equation(s): -// \ula_|video_|vram_address[10]~3_combout = (\ula_|video_|vram_address[10]~2_combout & (\ula_|video_|Add4~4_combout & (\ula_|video_|vga_hc [1]))) # (!\ula_|video_|vram_address[10]~2_combout & (((\ula_|video_|vram_address [10])))) - - .dataa(\ula_|video_|Add4~4_combout ), - .datab(\ula_|video_|vga_hc [1]), - .datac(\ula_|video_|vram_address [10]), - .datad(\ula_|video_|vram_address[10]~2_combout ), - .cin(gnd), - .combout(\ula_|video_|vram_address[10]~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address[10]~3 .lut_mask = 16'h88F0; -defparam \ula_|video_|vram_address[10]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y31_N31 -dffeas \ula_|video_|vram_address[10] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vram_address[10]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [10]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[10] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[10] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N16 -cycloneive_lcell_comb \ula_|video_|Selector3~0 ( -// Equation(s): -// \ula_|video_|Selector3~0_combout = (\ula_|video_|Add4~12_combout ) # (\ula_|video_|vga_hc [2]) - - .dataa(gnd), - .datab(\ula_|video_|Add4~12_combout ), - .datac(gnd), - .datad(\ula_|video_|vga_hc [2]), - .cin(gnd), - .combout(\ula_|video_|Selector3~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Selector3~0 .lut_mask = 16'hFFCC; -defparam \ula_|video_|Selector3~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y31_N17 -dffeas \ula_|video_|vram_address[11] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Selector3~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address[9]~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [11]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[11] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[11] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N26 -cycloneive_lcell_comb \ula_|video_|Selector2~0 ( -// Equation(s): -// \ula_|video_|Selector2~0_combout = (\ula_|video_|Add4~14_combout ) # (\ula_|video_|vga_hc [2]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|video_|Add4~14_combout ), - .datad(\ula_|video_|vga_hc [2]), - .cin(gnd), - .combout(\ula_|video_|Selector2~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Selector2~0 .lut_mask = 16'hFFF0; -defparam \ula_|video_|Selector2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y31_N27 -dffeas \ula_|video_|vram_address[12] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Selector2~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address[9]~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [12]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[12] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[12] .power_up = "low"; -// synopsys translate_on - -// Location: M9K_X33_Y27_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a6 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~101_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_first_bit_number = 6; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFFFFFEBFFFFFFFFFFFFFFFFFFFFFFFBFFFFFFFFFFFFFFFFFDFFFFFFFFFFFFFBFFFFFFFFFEFFFFFFFDFFFFFFFFFFFFFEFFFFFFFDF8FFFFFFF9FFFFFFFFFFFFFFFF3FFFFFFE7FFFFFFFFFFFFFFFF; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000380001887600094C977486989000000000000000000000000FFFFFFFFC0810205C00018C36DC09CF97749EDCD00000000000000000000000000000001FFFFFFFDC004000B6D028BF17749ED8100000000000000000000000000000001BF7EFDF9400404A96D8289B57549FFC10000000000000000000000003F7EFDF90000000140041EB16D8298357DC9F7410000000000000000000000007FFFFFFD8000000340043AB160021E757DC9134100000000000000000000000040810207BFFFFFFF5FE430497702760D60099349000000000000000000000000408102073FFFFFFD5FE40E49774240C96009735D; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h5FE8334948F827C15FF88F8169A80ECB609EAD417A698FC178F33E8171F72A915FE836E948F807C95FF88F81E9A80FC7639E1FC17B2BBEC170730F8D70F7B0C1400826E548B807C95FF88F95E8280FCB63C6BCC17B3B3FC171AB3E81708734C1400826ED58F8258159F88B8168280FC161629DC17A3B3F41738B3F8150AF16E9400826ED581805C151D88A8160682FC1422297C17A2A39C162FB378550CF10A1400826ED58182581D1580B8761EC2FC14232B7C179AA39C5627B7781D0CF10D3400826E158182D81F0488A4B61EC0DC143789FC17BBB39C1610B7F81D45F11D34008A7E958080D01F0088A4160B42DD143689FC17B9B398561837F81D41702B1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h50DF086350368F0151C688016801460157EDE81148F310013FFFFFFF40810103D2D70D4B50168F0141D6C8116C01462153EDA90148F31D01BFFFFFFF40810107D2D7296354D68501403EC0016C01482173FDA08148F11F01800000037FFFFFFD4297893154DE81054022D2116C014D6153FCA00148D10F01000000013F7EFEF9429F810150CEC10143E042016C014C09537DA00148D11F01BF7EFEF900000001469F833150168D0543E04A116F014DA15379B181C8511F03FFFFFFFD00000001449AAB2155368D01482046016F416CA15079B001C8513E03C0810105FFFFFFFF403A8B0155C685014800461167476CA15039B08180413E0500000007FFFFFFFF; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N22 -cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder ( -// Equation(s): -// \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout = \z80_|address_pins_|abus[13]~20_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_pins_|abus[13]~20_combout ), - .cin(gnd), - .combout(\ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder .lut_mask = 16'hFF00; -defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y14_N23 -dffeas \ram0|altsyncram_component|auto_generated|address_reg_a[0] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram0|altsyncram_component|auto_generated|address_reg_a [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true"; -defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y14_N1 -dffeas \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(gnd), - .asdata(\ram0|altsyncram_component|auto_generated|address_reg_a [0]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true"; -defparam \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N10 -cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1 ( -// Equation(s): -// \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout = (\ExtRamWE~0_combout & (\z80_|address_pins_|abus[13]~20_combout & (\z80_|address_pins_|abus[14]~23_combout & !\z80_|address_pins_|abus[15]~22_combout ))) - - .dataa(\ExtRamWE~0_combout ), - .datab(\z80_|address_pins_|abus[13]~20_combout ), - .datac(\z80_|address_pins_|abus[14]~23_combout ), - .datad(\z80_|address_pins_|abus[15]~22_combout ), - .cin(gnd), - .combout(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .cout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1 .lut_mask = 16'h0080; -defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y25_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a14 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(gnd), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~101_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_first_bit_number = 6; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y33_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a14 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h4200420000441C443C0C3C00480018FC387C7C000000007E180038300000204880084204004204423E1E3E02247E3C7E3C7E7E7E7E30007E3C7E7E7E3C7E7C3C0400000000000C34023C2E302464003C00000000000000000020460024000000FF991E65536D2D8D9C9B4DB081C83A5A881B0DFDE2D72DF0FA08FCD6F664173D989098D02025E0F6043B4B9080F4923880C3A3B02D269E730C3DCC423386DCB98B4AD0C5C8D6119602E5121008325B7457090E914F4876EC8A18C664210A4C2392C7658400073421047C75FBE7BE73FDFFF05FEE07BF8AEF7F1378B359E8C61F8F692C2218C98A4A8748531986E7C770D984E0000C02060C000C0DF50F68A580; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h0100046606572583002086010800054C0F2DE8371AC0000A9003E024840C7C0806F6612D770080980A40D293FEC069F16CB2164CA033C539F69B37741AEF1CE3662FF5DF9CB107BB23A39EF7B95E7372200448DBDC18F9C0DE0EF379BF49480657781E91788044213E091339886F337D0612CA646CD48FC58EE77EDD7ECEC466C744FD00E1A7F9E9FBFE4777FD50ABD11F0E57FF4808802282200888A20AA88000000008800AC11D556264251ECFA68C056FBCCB040C614A6850222300D2F6FF59F878FCF5689FCFEF34BFD52FA2422A56A3C113409F7813007F8D6B5F80FE9D7FB1E62675F7C2CBE01032DCA16BADC570C1CBF7ECBC4E7E6C54A5D4550BE1A8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'hE33CB578DEBFAFAEDFD530DE8FA1992072F31B116644B18C72F9F44116C79ADF2F3982C7BE09AD4A32196807648A2495ADF98FD2B16CC096A5E25F5BC811C953CEC3000F432029B3FE3F211712944CA54D1940F193204C199C9F49666CC11B38C23B9D130CA49818913D3A2C1FBF71C5B0C774336F903C677D976189D98CA127AAAD6B6AF36195DA637C6EFA3E36E8FE97FA02EC26EB46198AD8DAD8C11260AF499D7BD86619EE5574CD27C80D39F71E653FDCF1B366737233CBB98D1E7B330F7DCCFC5939C4EC79CF0E1CD43BA7AFC716900A21BDB9DD0FCC7ECE1063238407C7E1B221EA10E38F64EF31CEBF3368E1C712BB1B33781134CFE54C2123349A6E; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h5F9CB25A3631964C20007FF5754FC631A97D4F93986C30CF24394625658DE9A7C228A2050470925E29A35D8D06242712CD25C9241898204D85A710947C802013E1265727652C8F0C422BA8C28A0FBB893B0881E00403DDD8843B2D8EB929D0D8CB76E03779E019E2C4E4028219C38C202C9384E0D24E569C2E4D4D60B670CE37414D536A41D144B6C4624A2B00366D8CF6734A4A2DC465B308462CCBD1BF9CB863FC93EDB2CA5DC61B01639318985C88F01680E307C42311C0124700B28BF9B4FF7CCCEFE1996DE3ED6D8CFBF1871BD98EE7646242664EB2E338BD009838637124C921BB3332DC66D9C1706B6C48C3129639A3BA4088EDB496EDBBBFC2CC40B6; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N2 -cycloneive_lcell_comb \D[6]~87 ( -// Equation(s): -// \D[6]~87_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))) # (!\z80_|address_pins_|abus[14]~23_combout -// & (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout )))) - - .dataa(\z80_|address_pins_|abus[14]~23_combout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout ), - .datad(\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ), - .cin(gnd), - .combout(\D[6]~87_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~87 .lut_mask = 16'hE6A2; -defparam \D[6]~87 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y1_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a6 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h3C766E63DB6481CB39BC8C68831C724633186CC1BAE9D608A5DEF0FF219C28C1EFF4FDE394D0E19B6FD89186C23CF071E6F1CC8F7FC4F1E48756B0DCD8ED6D0C3DA139003D7A86B2F878DD99DAFB70DE1A19F3FB7DB3B8EF2633007664CB19992E43664448EFF06072648DBA32EDB76E26439BCCEF2DFBF664594B04FBAE72A84A3E508B49DC6BEAAB4F3F0CCCF6D8F568F2DA00EB384A7F53249323198000100408002024010408824080002008011482ED5615E40012EE630C3B2CDB2C13A736DB5B7BD2850018CF936621C6863095A73F7BE7442CB13110B9C0BBB96EEF16CE618EEDCFB393738178C476C367909F71307F6803F677575763DB2D8C3118E4; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h881331ED7AC4EFD38DFACDBB236790005719AEA2FAECCF0D126A30A27222D61BBA428334561F4EDB60C6BF8DB6E267BC56CB69BBCE636CCCB3B2B4B103CC46D5CEEC06DAECB0001569589D5F267AFE086C8FED5DE41DFEFF027DFDFF7FFBFBFDFFDFFF6FFFBDFFDFFF57FF7F7FB7FBBDFBDFFDBFF78FFDBFFEDDFFFDFFFEFF6FF7F7FDDFFEDFF6FF7FFEEFFEFEFC4E51EC0888848E1F2044B47B66608D8A3B3919B9466E6D60D27565964244B218B48AD83430D996068EC908D9E112096996041D77401A0C0CCF5DEEE561F7F7E68CBE72E48E570B047C772CBACC33753080E32EB0B348C0B62337739B1BC73192392592C84E37B7AC141CFE65EE76D83C9083; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h1C5CF062CA6F13854A59BDEEEA07E3C6559EBB3618111895CBBACCBCD512B5F07D361CCE72B925658DBE1F7C4707E195C5C665B8118C3C31B196C261DA85A5E11889D25CB816ACC6627802052C61A4099B7B0EC923971DB3B9F9204BDBCCFA457EE296E8986E64C6DC99E59436641567648CB84DEB7D7937F974F038D838274F3D3CF1BE8C84DDB000565880A776E5C0E13166E49F47119A4CA1311CF97B965E7CBBCB2CB384BD0D92ED105D0617856E80441124B31DE58B8C001607FEE668899693E3EFF8FBF1FCEEFBCF7CF9BA6C37640DDF7FFE6187B19ACF089D4C038F6607B78D38001FE67E56CCE399DE36D7DDBD699D5CFC5B6D7A1421CE06FE40DB6E; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h0776C62C316FF94B0BC3A0288DE6A62B14D6C1A2DADF9BDF85B2CCB02CE1DB2D96632C3232C3974CDC1172E1779D8C6738251819975DB8146067301E0C0277B6B657485DCD62AC0662C8C005DDE7494C9CA13AAE3234BB0EE1B708A23A2F48AC4C3838641E940620F9CDDCCA14BCC07104C112BCC9032C48E925594CB886A604C9F7627EB100872A52FB5141D65111E6C8DA0ADB6CEC6004461D0E366B20DCCDB607E624499300E4DF6D95CB62F62FB75403E400EFBC3BD34080FC9CDCFCFCFFFFFFFFFFFFFFFFFFFFF7BFFFFFFFFFFFFFFFFFFFFFFFFFFFCF9FFFFFEFFFF81FFDDFFFFFFFFFFFFFF7FFBFFFBFDC0A6DBE6F8BE5BB7FE7A39B3DA3F3BE13B679; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N6 -cycloneive_lcell_comb \D[6]~88 ( -// Equation(s): -// \D[6]~88_combout = (\z80_|address_pins_|abus[15]~22_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout $ (((\D[6]~87_combout ))))) # (!\z80_|address_pins_|abus[15]~22_combout & -// (((\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout & !\D[6]~87_combout )))) - - .dataa(\z80_|address_pins_|abus[15]~22_combout ), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ), - .datad(\D[6]~87_combout ), - .cin(gnd), - .combout(\D[6]~88_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~88 .lut_mask = 16'h22D8; -defparam \D[6]~88 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N20 -cycloneive_lcell_comb \D[6]~89 ( -// Equation(s): -// \D[6]~89_combout = (\D[6]~87_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout & !\D[6]~88_combout )))) # (!\D[6]~87_combout & -// (((!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & \D[6]~88_combout )))) - - .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ), - .datab(\D[6]~87_combout ), - .datac(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datad(\D[6]~88_combout ), - .cin(gnd), - .combout(\D[6]~89_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~89 .lut_mask = 16'hC3C8; -defparam \D[6]~89 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N14 -cycloneive_lcell_comb \D[6]~111 ( -// Equation(s): -// \D[6]~111_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [15] & (\D[6]~91_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\D[6]~89_combout ))))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & -// (\D[6]~91_combout )) - - .dataa(\D[6]~91_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [15]), - .datad(\D[6]~89_combout ), - .cin(gnd), - .combout(\D[6]~111_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~111 .lut_mask = 16'hAEA2; -defparam \D[6]~111 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: IOIBUF_X16_Y34_N8 -cycloneive_io_ibuf \raw_loader_in~input ( - .i(raw_loader_in), - .ibar(gnd), - .o(\raw_loader_in~input_o )); -// synopsys translate_off -defparam \raw_loader_in~input .bus_hold = "false"; -defparam \raw_loader_in~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N18 -cycloneive_lcell_comb \D[6]~86 ( -// Equation(s): -// \D[6]~86_combout = (\z80_|address_pins_|DFFE_apin_latch [0]) # ((\raw_loader_in~input_o ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [0]), - .datab(gnd), - .datac(\raw_loader_in~input_o ), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\D[6]~86_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~86 .lut_mask = 16'hFAFF; -defparam \D[6]~86 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N28 -cycloneive_lcell_comb \D[6]~100 ( -// Equation(s): -// \D[6]~100_combout = ((\Equal2~0_combout & ((\D[6]~86_combout ))) # (!\Equal2~0_combout & (\D[6]~111_combout ))) # (!\Equal2~1_combout ) - - .dataa(\Equal2~1_combout ), - .datab(\Equal2~0_combout ), - .datac(\D[6]~111_combout ), - .datad(\D[6]~86_combout ), - .cin(gnd), - .combout(\D[6]~100_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~100 .lut_mask = 16'hFD75; -defparam \D[6]~100 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N4 -cycloneive_lcell_comb \D[6]~101 ( -// Equation(s): -// \D[6]~101_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\z80_|data_pins_|dout [6] & \D[6]~100_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\D[6]~100_combout )) # (!\Equal2~1_combout ))) - - .dataa(\Equal2~1_combout ), - .datab(\z80_|data_pins_|dout [6]), - .datac(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datad(\D[6]~100_combout ), - .cin(gnd), - .combout(\D[6]~101_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~101 .lut_mask = 16'hCF05; -defparam \D[6]~101 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N12 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [6] = (\z80_|pin_control_|bus_db_pin_re~combout & ((\D[6]~101_combout ) # ((\z80_|execute_|ctl_bus_db_we~7_combout & \z80_|bus_control_|db[6]~9_combout )))) # (!\z80_|pin_control_|bus_db_pin_re~combout & -// (((\z80_|execute_|ctl_bus_db_we~7_combout & \z80_|bus_control_|db[6]~9_combout )))) - - .dataa(\z80_|pin_control_|bus_db_pin_re~combout ), - .datab(\D[6]~101_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|bus_control_|db[6]~9_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [6]), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] .lut_mask = 16'hF888; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N10 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_re~2 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_re~2_combout = (\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & ((\z80_|execute_|fIORead~3_combout )))) # (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # -// ((\z80_|sequencer_|DFFE_T3_ff~q & \z80_|execute_|fIORead~3_combout )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|execute_|fIORead~3_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_re~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_re~2 .lut_mask = 16'hDC50; -defparam \z80_|pin_control_|bus_db_pin_re~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N16 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_2 ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_2~combout = (\z80_|execute_|ctl_bus_db_we~7_combout ) # ((\z80_|pin_control_|bus_db_pin_re~2_combout ) # ((\z80_|execute_|fMRead~35_combout & \z80_|sequencer_|DFFE_T2_ff~q ))) - - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(\z80_|execute_|fMRead~35_combout ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|pin_control_|bus_db_pin_re~2_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_2 .lut_mask = 16'hFFEA; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y13_N13 -dffeas \z80_|data_pins_|dout[6] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [6]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|data_pins_|dout [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|data_pins_|dout[6] .is_wysiwyg = "true"; -defparam \z80_|data_pins_|dout[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N16 -cycloneive_lcell_comb \z80_|bus_control_|db[6]~9 ( -// Equation(s): -// \z80_|bus_control_|db[6]~9_combout = ((\z80_|bus_control_|db[6]~8_combout & ((\z80_|data_pins_|dout [6]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - - .dataa(\z80_|bus_control_|db[6]~8_combout ), - .datab(\z80_|data_pins_|dout [6]), - .datac(\z80_|execute_|ctl_bus_db_oe~combout ), - .datad(\z80_|bus_control_|db[0]~6_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[6]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[6]~9 .lut_mask = 16'h8AFF; -defparam \z80_|bus_control_|db[6]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N8 -cycloneive_lcell_comb \z80_|ir_|opcode[6]~feeder ( -// Equation(s): -// \z80_|ir_|opcode[6]~feeder_combout = \z80_|bus_control_|db[6]~9_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|bus_control_|db[6]~9_combout ), - .cin(gnd), - .combout(\z80_|ir_|opcode[6]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|ir_|opcode[6]~feeder .lut_mask = 16'hFF00; -defparam \z80_|ir_|opcode[6]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~13 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~13_combout = ((\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_ir_we~5_combout ) # (\z80_|pla_decode_|Equal41~2_combout )))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) - - .dataa(\z80_|execute_|ctl_ir_we~5_combout ), - .datab(\z80_|pla_decode_|Equal41~2_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~13 .lut_mask = 16'hE0FF; -defparam \z80_|execute_|ctl_ir_we~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y12_N9 -dffeas \z80_|ir_|opcode[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|ir_|opcode[6]~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|ir_|opcode [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|ir_|opcode[6] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal41~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal41~0_combout = (\z80_|ir_|opcode [7] & \z80_|ir_|opcode [6]) - - .dataa(gnd), - .datab(gnd), + .dataa(\z80_|decode_state_|DFFE_instCB~q ), + .datab(\z80_|decode_state_|DFFE_instED~q ), .datac(\z80_|ir_|opcode [7]), .datad(\z80_|ir_|opcode [6]), .cin(gnd), - .combout(\z80_|pla_decode_|Equal41~0_combout ), + .combout(\z80_|pla_decode_|Equal44~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal41~0 .lut_mask = 16'hF000; -defparam \z80_|pla_decode_|Equal41~0 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal44~0 .lut_mask = 16'h0010; +defparam \z80_|pla_decode_|Equal44~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y16_N22 -cycloneive_lcell_comb \z80_|pla_decode_|Equal41~1 ( +// Location: LCCOMB_X25_Y16_N20 +cycloneive_lcell_comb \z80_|execute_|ixy_d~16 ( // Equation(s): -// \z80_|pla_decode_|Equal41~1_combout = (!\z80_|ir_|opcode [2] & (\z80_|ir_|opcode [1] & (\z80_|ir_|opcode [0] & !\z80_|ir_|opcode [5]))) +// \z80_|execute_|ixy_d~16_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal44~0_combout & ((\z80_|decode_state_|DFFE_instIY1~q ) # (\z80_|decode_state_|DFFE_inst4~q )))) - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|ir_|opcode [1]), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|ir_|opcode [5]), + .dataa(\z80_|decode_state_|DFFE_instIY1~q ), + .datab(\z80_|decode_state_|DFFE_inst4~q ), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|pla_decode_|Equal44~0_combout ), .cin(gnd), - .combout(\z80_|pla_decode_|Equal41~1_combout ), + .combout(\z80_|execute_|ixy_d~16_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal41~1 .lut_mask = 16'h0040; -defparam \z80_|pla_decode_|Equal41~1 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ixy_d~16 .lut_mask = 16'hE000; +defparam \z80_|execute_|ixy_d~16 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y16_N24 -cycloneive_lcell_comb \z80_|pla_decode_|Equal41~2 ( +// Location: LCCOMB_X23_Y13_N24 +cycloneive_lcell_comb \z80_|pla_decode_|Equal3~1 ( // Equation(s): -// \z80_|pla_decode_|Equal41~2_combout = (\z80_|pla_decode_|Equal41~0_combout & (\z80_|pla_decode_|Equal32~0_combout & (\z80_|pla_decode_|Equal41~1_combout & \z80_|decode_state_|use_ixiy~combout ))) - - .dataa(\z80_|pla_decode_|Equal41~0_combout ), - .datab(\z80_|pla_decode_|Equal32~0_combout ), - .datac(\z80_|pla_decode_|Equal41~1_combout ), - .datad(\z80_|decode_state_|use_ixiy~combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal41~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal41~2 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal41~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~combout = (\z80_|execute_|ctl_alu_bs_oe~11_combout ) # ((\z80_|sequencer_|DFFE_M4_ff~q & (\z80_|pla_decode_|Equal41~2_combout & !\z80_|sequencer_|DFFE_T1_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|pla_decode_|Equal41~2_combout ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|execute_|ctl_alu_bs_oe~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe .lut_mask = 16'hFF08; -defparam \z80_|execute_|ctl_alu_bs_oe .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N2 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~15 ( -// Equation(s): -// \z80_|alu_|db_high[1]~15_combout = ((!\z80_|bus_control_|db[4]~19_combout & (\z80_|bus_control_|db[5]~15_combout & \z80_|bus_control_|db[3]~21_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datab(\z80_|bus_control_|db[4]~19_combout ), - .datac(\z80_|bus_control_|db[5]~15_combout ), - .datad(\z80_|bus_control_|db[3]~21_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~15 .lut_mask = 16'h7555; -defparam \z80_|alu_|db_high[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N10 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~16 ( -// Equation(s): -// \z80_|alu_|db_high[1]~16_combout = (\z80_|alu_|op1_high [1] & (((\z80_|alu_|op2_high [1]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|alu_|op1_high [1] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_high [1]) # -// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) - - .dataa(\z80_|alu_|op1_high [1]), - .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datac(\z80_|alu_|op2_high [1]), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~16 .lut_mask = 16'hB0BB; -defparam \z80_|alu_|db_high[1]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N20 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~17 ( -// Equation(s): -// \z80_|alu_|db_high[1]~17_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[6]~23_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[4]~17_combout ))) - - .dataa(\z80_|alu_|db[6]~23_combout ), - .datab(gnd), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|alu_|db[4]~17_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~17 .lut_mask = 16'hAFA0; -defparam \z80_|alu_|db_high[1]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N26 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~18 ( -// Equation(s): -// \z80_|alu_|db_high[1]~18_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_high[1]~17_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[5]~25_combout ))) +// \z80_|pla_decode_|Equal3~1_combout = (\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [1]) .dataa(gnd), - .datab(\z80_|alu_|db_high[1]~17_combout ), - .datac(\z80_|alu_|db[5]~25_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~18 .lut_mask = 16'hCCF0; -defparam \z80_|alu_|db_high[1]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N12 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~19 ( -// Equation(s): -// \z80_|alu_|db_high[1]~19_combout = (\z80_|alu_|db_high[1]~15_combout & (\z80_|alu_|db_high[1]~16_combout & ((\z80_|alu_|db_high[1]~18_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) - - .dataa(\z80_|alu_|db_high[1]~15_combout ), - .datab(\z80_|alu_|db_high[1]~16_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datad(\z80_|alu_|db_high[1]~18_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~19 .lut_mask = 16'h8808; -defparam \z80_|alu_|db_high[1]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N26 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~20 ( -// Equation(s): -// \z80_|alu_|db_high[1]~20_combout = ((\z80_|alu_|db_high[1]~19_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout )))) # (!\z80_|alu_|db_high[3]~3_combout ) - - .dataa(\z80_|alu_|db_high[1]~19_combout ), - .datab(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), - .datad(\z80_|alu_|db_high[3]~3_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~20 .lut_mask = 16'hA8FF; -defparam \z80_|alu_|db_high[1]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N14 -cycloneive_lcell_comb \z80_|alu_|db[5]~24 ( -// Equation(s): -// \z80_|alu_|db[5]~24_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[5]~57_combout & ((\z80_|alu_control_|db[5]~15_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & -// ((\z80_|alu_control_|db[5]~15_combout ) # ((!\z80_|execute_|ctl_sw_2d~13_combout )))) - - .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datab(\z80_|alu_control_|db[5]~15_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .datad(\z80_|execute_|ctl_sw_2d~13_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[5]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[5]~24 .lut_mask = 16'hC4F5; -defparam \z80_|alu_|db[5]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N28 -cycloneive_lcell_comb \z80_|alu_|db[5]~25 ( -// Equation(s): -// \z80_|alu_|db[5]~25_combout = ((\z80_|alu_|db[5]~24_combout & ((\z80_|alu_|db_high[1]~20_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~26_combout ) - - .dataa(\z80_|alu_|db_high[1]~20_combout ), - .datab(\z80_|alu_|db[7]~26_combout ), - .datac(\z80_|alu_|db[5]~24_combout ), - .datad(\z80_|execute_|ctl_alu_oe~14_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[5]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[5]~25 .lut_mask = 16'hB3F3; -defparam \z80_|alu_|db[5]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N14 -cycloneive_lcell_comb \z80_|sw1_|db_down[5]~0 ( -// Equation(s): -// \z80_|sw1_|db_down[5]~0_combout = (\z80_|bus_control_|db[5]~15_combout ) # ((\z80_|execute_|ctl_sw_1d~6_combout & ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|execute_|ctl_66_oe~2_combout )))) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|bus_control_|db[5]~15_combout ), - .datac(\z80_|execute_|ctl_66_oe~2_combout ), - .datad(\z80_|execute_|ctl_sw_1d~6_combout ), - .cin(gnd), - .combout(\z80_|sw1_|db_down[5]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sw1_|db_down[5]~0 .lut_mask = 16'hEFCC; -defparam \z80_|sw1_|db_down[5]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N22 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_36 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout = (\z80_|alu_control_|db[5]~15_combout & ((\z80_|execute_|ctl_flags_bus~combout ) # ((\z80_|alu_|db_high[1]~20_combout & \z80_|execute_|ctl_flags_alu~15_combout )))) # (!\z80_|alu_control_|db[5]~15_combout -// & (\z80_|alu_|db_high[1]~20_combout & ((\z80_|execute_|ctl_flags_alu~15_combout )))) - - .dataa(\z80_|alu_control_|db[5]~15_combout ), - .datab(\z80_|alu_|db_high[1]~20_combout ), - .datac(\z80_|execute_|ctl_flags_bus~combout ), - .datad(\z80_|execute_|ctl_flags_alu~15_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_36 .lut_mask = 16'hECA0; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y11_N23 -dffeas \z80_|alu_flags_|flags_yf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_flags_xy_we~15_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|flags_yf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_yf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|flags_yf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N2 -cycloneive_lcell_comb \z80_|alu_control_|db[5]~13 ( -// Equation(s): -// \z80_|alu_control_|db[5]~13_combout = (\z80_|alu_flags_|flags_yf~q & ((\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ) # ((\z80_|alu_control_|out[6]~2_combout )))) # (!\z80_|alu_flags_|flags_yf~q & (!\z80_|execute_|ctl_flags_oe~2_combout & -// ((\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ) # (\z80_|alu_control_|out[6]~2_combout )))) - - .dataa(\z80_|alu_flags_|flags_yf~q ), - .datab(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .datac(\z80_|execute_|ctl_flags_oe~2_combout ), - .datad(\z80_|alu_control_|out[6]~2_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[5]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[5]~13 .lut_mask = 16'hAF8C; -defparam \z80_|alu_control_|db[5]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N0 -cycloneive_lcell_comb \z80_|alu_control_|db[5]~14 ( -// Equation(s): -// \z80_|alu_control_|db[5]~14_combout = (\z80_|sw1_|db_down[5]~0_combout & (\z80_|alu_control_|db[5]~13_combout & ((\z80_|reg_file_|gdfx_temp0[5]~72_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) - - .dataa(\z80_|sw1_|db_down[5]~0_combout ), - .datab(\z80_|alu_control_|db[5]~13_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .datad(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[5]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[5]~14 .lut_mask = 16'h8088; -defparam \z80_|alu_control_|db[5]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N10 -cycloneive_lcell_comb \z80_|alu_control_|db[5]~15 ( -// Equation(s): -// \z80_|alu_control_|db[5]~15_combout = ((\z80_|alu_control_|db[5]~14_combout & ((\z80_|alu_|db[5]~25_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|alu_control_|db[6]~11_combout ), - .datab(\z80_|alu_|db[5]~25_combout ), - .datac(\z80_|execute_|ctl_sw_2u~7_combout ), - .datad(\z80_|alu_control_|db[5]~14_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[5]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[5]~15 .lut_mask = 16'hDF55; -defparam \z80_|alu_control_|db[5]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N10 -cycloneive_lcell_comb \D[0]~107 ( -// Equation(s): -// \D[0]~107_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout ) # ((!\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \z80_|memory_ifc_|nRD_out~2_combout ))) - - .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|memory_ifc_|nRD_out~2_combout ), - .datad(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .cin(gnd), - .combout(\D[0]~107_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~107 .lut_mask = 16'hFF40; -defparam \D[0]~107 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y6_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a21 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[5]~99_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_first_bit_number = 5; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y9_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a5 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[5]~99_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_bit_number = 5; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024; -// synopsys translate_on - -// Location: M9K_X22_Y7_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a13 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[5]~99_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_bit_number = 5; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N8 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4 .lut_mask = 16'hDC98; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y23_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a29 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[5]~99_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_first_bit_number = 5; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N6 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4_combout & -// ((\ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout )))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4_combout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4_combout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5 .lut_mask = 16'hF838; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y26_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a13 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(gnd), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[5]~99_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_bit_number = 5; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_first_bit_number = 5; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y29_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a13 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_bit_number = 5; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init3 = 2048'h990442000864A0284030400454782424440404007E404808A4005448387E547C8004420800620824402040024A1242124204044008404208420A4A42424A1242020028008000524A024A4A284252446240001000101042000054265C7E0600007FAF5CA001C181BE0C02418447B1D88BAA85409896BC7C0E5FAC2529CB69A4038E2564731F88FE730045956C357C5ECF7EF8591DF2A8ACFFBFEEF268CD9B51238594AF691A9B8640983B7F76AAB97209EA6257389992FFE684926E0B19FA338B8489D73811171D5C9FF3DCFFFFFF8002000780101F3F4035A0CDED99F79A4775854F179F7D7DBBCF81B2F6421FF684CA6AF85894D29B9D3ACCBA3F27D9DC9911; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init2 = 2048'h5B438D714D4E3DD115E8BD1286EAB5FA1D71BD8F4508BD4BDC8838F9D27B552259BCEFFBB68A6FF529B3B0D92970010BBB6C7D872421210E190E1CCC47A485EAD2F8735647315839EF6F683C64773FC73464D5FE354936D50823A5DAEBEBDBCC6CAFF2622B8D518F63C6030424188FD357718970D25A30CD0731E532DB23002D02C12B12378356DE2C52041CA7A320C51E0D7CA9F5D575775D57FD75DDFDF75FFFDFFFD75F145247F03A0AE7F1E1EB2D5A99D2444108C6A5979B7CC26ABCC241EA4C912568003BB493CE04FF086C188980052BF6ABAAA2FD5D658000011277EB924C10EFAF3CB9B62486512344C61ADE6F15AB67F335A52513FF05AFAEEE8400; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 2048'h0C840083AD485153ACD3C035591630199B8C096CE4DC557D6D55FCCD738573D6E0948817C496E9DE8EA1F88F627B7460106691CC452DB9799E59A5D003733C4EA1BCE33AD2D8BE40A4E5BB7D7BBEC2CEADBBC8B6F87A4A56FBE0B891DE57E4C64EF9AD87727C49CFE7C5DE942B72AC7F6D97DE18920777FDDEE9EB11122A4E18F5569FDE08906765428FB9E6F89FBF0DEAA6064637BCA63FD02E273E5557F0548662C97BC2E8D3FFDB26D23E87BFD97E635A6560CFD93F8EED26E30C70DE8633D6B97C86DF7D9BEDFB99E36B6658F16C6DEFBDD5DF728D6209C852C37FE67CFF32EE4CCCECC64F7E6225FC99EC64C3B6DD7DED0FD7CCEA3BF09A006ECDD1009E; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'hA9C9CE3AECF7BE27C000000A8ABA95251B309A60B9DDC19EC3E391458CBB53CA00A85E3C5AAE2C49DDC2F6C7B013DACB319A769818A1081A7389F711D76A09BCBED23D9A99FF9B77183697955D76BF0E0008822742DA45B883C9193DAF09424501859565800698515E10A8189EE9B323E35CE7388D73C6E7A50D0DE6739C73AC538D134115D860ADA57B5B868E54393B1E31E762062577697D57E8464340420E9434CCA34CC9A1CB1FAACC56168071EAC113F5265D5F6A45A098D604A820508C4EA47F9A7E46083716911B0D585CE937B530218E8D2AD3777EE7D3B4BC56C29ADB46809D15D185F8809229B150C29C8081174CA6173B99703DA466629005C604; -// synopsys translate_on - -// Location: M9K_X33_Y2_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a5 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_bit_number = 5; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init3 = 2048'hE10F8B8C100323720BEBBDEBB81DF13FF97B252E2CB4F27BA091FBD0002D1A611E1EDBBC716D44D2912B80041C44558060CFCF15955C0D780DD5E71393920844F25E16C87C5D0308EEC52C011514BBC13AFA1028924D0C7CE738105BD47A10AA5B5C1D9D4193E4339F492B0E1A64E13AE35BE6B67AC8057BDACC155F14E906A017A1841358335450D4B26CD2A21B3D8F2211080B81EC040D7FA0B51CD48008112508062020A02490900092D2040259108806A328F4006D2AA514B42FB006ECCCCB9A360865678449975A8AE72B5C0F7BA800C1B5DC55D7D6FE2EF4EED85D00AB111821321BA426A4FE4956B43595832C271E83E060341AE5F2023FC808177383; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init2 = 2048'h1A2955372D510AC266A5445146E27000020C320FAE1557E37154040A13202DC6F40B840FB9A59B6DBB296562CB6220EFBE99D2776A202044D9101006FD221D305519198C859000004012AFF4FB060307C92BB732203BFDFEFFFFFFDFFF87FCFFFBFFEFF03FFE0FFFBFAFE0FF80787FFF7FFF83F7F87003FFBFFFFBFFFBFF0FFC0FF81FFF7FFBFFDFFFBFFFE1FF0086F3141AAB6005810A0621595A893F9D85983B9254954341968BAC8C141C90938C05B2C9CD267E11650407375FEDD6A2FEB346AAF6CFDC0791AA97B741995A3B3981E06D1A44D3711955197BB9910FCA20744915C84D6C24BAF53929814CA8A4697E8F4201145AE7415DC122A5F010436107; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048'h02E84F969E3C800AC610D276182020227809001A50DDDBA3487BB6AE802BA06509312DA0E620656EAF24D57C08FFB14D289613DC32083803B84DC6415FD5EDC000300A8D128FA20030ACCBAFA237B7024504D36A4BA26081137F059E78991154FE2AC2A884A8CC7FBBB21C851CC92B12E15593C0C020FFEE066558590E882D5B67459F1A8C3240FE4E6A8D028C0C088FCF471D400A19B38211004DD122212288B111114514CB11840E04828849C621392041163C00808C67223422F00110201DD18FCFFFF3FFE7F9FFFFFFF82C0B422D214711E08904524A069491774E663F48F665955B4E2C63DAC0078652D10120900298F7EE380092442AFD400BEC43C003; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'hB5D49EA9D7036A45AA9E870B8E8016720C7C3102AE925262492C84584942D209042216E0216C85B8912250B7157D5955AD406CB685BBF071B47D5193363C1CECAFE59E91BF11498940A0944996D47EE8D7E3A4EAE611AE19A965D01BA86B55E9C52A6A379A382C6C265FB0DA01396D0800C0046405C06F466DD18C4DD7655CD4E7622EC485808C841D64B737041FF68813B149A41531A0A692FB14AE2E5B49D49CDCADCF90E7BD88125BCE706BF6D04AABFC1C001163DC6EFF7FD3230303030000000000000000000008400000000000000000000000000030600000100007E00220000000000000080040004023AD496997B8C0077B886EEF161CF2298A091B; -// synopsys translate_on - -// Location: M9K_X33_Y29_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a5 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[5]~99_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a5_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_bit_number = 5; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_first_bit_number = 5; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init3 = 2048'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF80000001C000000160F000FF70C0007F78C00000F05001007870010010000000000800000038000000F000000070000000300000006000000000000040000000F00000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000000001D108000BEDA9FA9698A000000000000000000000000FFFFFFFF408102048004188297E014DA9FA9E9CA00000000000000000000000000000000FFFFFFFC800400CA972208DA9FA9CD8E00000000000000000000000000000000FFFFFFFC8004046A97A289FA9FA9CDC20000000000000000000000007FFFFFFC8000000280040E2A97A2997A9DA9CFC20000000000000000000000007FFFFFFE8000000280042EB28002BE369DA9274200000000000000000000000040810206BFFFFFFE9FE430A29D82AC3E8009E34A000000000000000000000000000000023FFFFFFC9FE4B1829FA2800E8009436A; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048'h9FE8334E88F827C697F88D1600A80A44809E8FC2B86999C2B85B3A82B1D32A869FE8336A88F807CA97F88F96A0A80EC2838E8D42B9E98FC2B86B3B82B0D7B2D2800832E288F827CA97F88B82A0080EC683869542B939B8C2B1AB0F8290B730C2800826EA8878078297F88AD2A0280EC283E694C2B83A3BC2A3AB3E8291A316AA800826EE881807C69DE8ABD6A0280BC282209CD2BA2A3D42A2737F82918314E2800806E6981805C69D48AED6A1E80BCA82709FC2BB223DC2A07B7F8295DF11C2800886E6980805869848AAC6A1E42DC281789DC2BBAA3DC6A02B7582955F00928008A6EE98082D9618088AC8A0F40FC289E89DC2BBCA3DC2A18B7782154F02F0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'h174F0870801C870281E2C982A801460297E5AC0288F318023FFFFFFC0000000297DF094A8094870281D6C082AC01460293FDA89288D31902BFFFFFFE40810106879F8D228C8685028016C082AC014642B3FCA80288D10F02800000027FFFFFFE879F893284DEC9028000408AAC014C02937DA00288D10F02800000027FFFFFFC841FA902804E81068BC04292AC0145E29379B00288D11F02FFFFFFFC0000000084FE89328166C1028BE05282AE4144829179B20288511F02FFFFFFFC0000000084F283328516850A88204602874364829179B08280513E0240810104FFFFFFFF843A8302853685828800560287476C928039B00200413E0000000000FFFFFFFF; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N0 -cycloneive_lcell_comb \Mux2~0 ( -// Equation(s): -// \Mux2~0_combout = (\z80_|address_pins_|abus[14]~23_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout )))) # (!\z80_|address_pins_|abus[14]~23_combout & -// (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ))) - - .dataa(\z80_|address_pins_|abus[14]~23_combout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout ), - .cin(gnd), - .combout(\Mux2~0_combout ), - .cout()); -// synopsys translate_off -defparam \Mux2~0 .lut_mask = 16'hBA98; -defparam \Mux2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N2 -cycloneive_lcell_comb \Mux2~1 ( -// Equation(s): -// \Mux2~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Mux2~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout )) # (!\Mux2~0_combout & -// ((\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Mux2~0_combout )))) - - .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ), - .datad(\Mux2~0_combout ), - .cin(gnd), - .combout(\Mux2~1_combout ), - .cout()); -// synopsys translate_off -defparam \Mux2~1 .lut_mask = 16'hBBC0; -defparam \Mux2~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N20 -cycloneive_lcell_comb \D[5]~110 ( -// Equation(s): -// \D[5]~110_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [15] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\Mux2~1_combout ))))) # -// (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout )) - - .dataa(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [15]), - .datad(\Mux2~1_combout ), - .cin(gnd), - .combout(\D[5]~110_combout ), - .cout()); -// synopsys translate_off -defparam \D[5]~110 .lut_mask = 16'hAEA2; -defparam \D[5]~110 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N28 -cycloneive_lcell_comb \D[5]~85 ( -// Equation(s): -// \D[5]~85_combout = (\D[5]~84_combout & (\D[5]~110_combout & ((\z80_|data_pins_|dout [5]) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) # (!\D[5]~84_combout & (((\z80_|data_pins_|dout [5])) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout ))) - - .dataa(\D[5]~84_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datac(\z80_|data_pins_|dout [5]), - .datad(\D[5]~110_combout ), - .cin(gnd), - .combout(\D[5]~85_combout ), - .cout()); -// synopsys translate_off -defparam \D[5]~85 .lut_mask = 16'hF351; -defparam \D[5]~85 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N24 -cycloneive_lcell_comb \D[5]~99 ( -// Equation(s): -// \D[5]~99_combout = (\D[5]~85_combout ) # (!\D[0]~107_combout ) - - .dataa(\D[0]~107_combout ), .datab(gnd), - .datac(gnd), - .datad(\D[5]~85_combout ), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [1]), .cin(gnd), - .combout(\D[5]~99_combout ), + .combout(\z80_|pla_decode_|Equal3~1_combout ), .cout()); // synopsys translate_off -defparam \D[5]~99 .lut_mask = 16'hFF55; -defparam \D[5]~99 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal3~1 .lut_mask = 16'h00F0; +defparam \z80_|pla_decode_|Equal3~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y13_N14 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[5] ( +// Location: LCCOMB_X24_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|ixy_d~10 ( // Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [5] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[5]~15_combout ) # ((\D[5]~99_combout & \z80_|pin_control_|bus_db_pin_re~combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & -// (\D[5]~99_combout & (\z80_|pin_control_|bus_db_pin_re~combout ))) +// \z80_|execute_|ixy_d~10_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal6~0_combout ))) - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(\D[5]~99_combout ), - .datac(\z80_|pin_control_|bus_db_pin_re~combout ), - .datad(\z80_|bus_control_|db[5]~15_combout ), + .dataa(\z80_|pla_decode_|Equal33~1_combout ), + .datab(\z80_|pla_decode_|Equal3~1_combout ), + .datac(\z80_|decode_state_|use_ixiy~combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [5]), + .combout(\z80_|execute_|ixy_d~10_combout ), .cout()); // synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[5] .lut_mask = 16'hEAC0; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[5] .sum_lutc_input = "datac"; +defparam \z80_|execute_|ixy_d~10 .lut_mask = 16'h8000; +defparam \z80_|execute_|ixy_d~10 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y13_N15 -dffeas \z80_|data_pins_|dout[5] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [5]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|data_pins_|dout [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|data_pins_|dout[5] .is_wysiwyg = "true"; -defparam \z80_|data_pins_|dout[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N22 -cycloneive_lcell_comb \z80_|bus_control_|db[5]~14 ( +// Location: LCCOMB_X24_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|ixy_d~13 ( // Equation(s): -// \z80_|bus_control_|db[5]~14_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [5]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) +// \z80_|execute_|ixy_d~13_combout = (\z80_|execute_|ixy_d~16_combout ) # ((\z80_|execute_|ixy_d~10_combout ) # (\z80_|pla_decode_|Equal41~2_combout )) + + .dataa(\z80_|execute_|ixy_d~16_combout ), + .datab(\z80_|execute_|ixy_d~10_combout ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~13 .lut_mask = 16'hFEFE; +defparam \z80_|execute_|ixy_d~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|ixy_d~14 ( +// Equation(s): +// \z80_|execute_|ixy_d~14_combout = (\z80_|execute_|ixy_d~12_combout & (((\z80_|execute_|ixy_d~17_combout & !\z80_|execute_|ixy_d~13_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) # (!\z80_|execute_|ixy_d~12_combout & +// (((\z80_|execute_|ixy_d~17_combout & !\z80_|execute_|ixy_d~13_combout )))) + + .dataa(\z80_|execute_|ixy_d~12_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ixy_d~17_combout ), + .datad(\z80_|execute_|ixy_d~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~14 .lut_mask = 16'h22F2; +defparam \z80_|execute_|ixy_d~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N10 +cycloneive_lcell_comb \z80_|pla_decode_|Equal49~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal49~0_combout = (!\z80_|decode_state_|in_halt~q & (\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal77~0_combout )) .dataa(gnd), - .datab(\z80_|execute_|ctl_bus_db_oe~combout ), - .datac(\z80_|data_pins_|dout [5]), - .datad(\z80_|bus_control_|db[0]~4_combout ), + .datab(\z80_|decode_state_|in_halt~q ), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|pla_decode_|Equal77~0_combout ), .cin(gnd), - .combout(\z80_|bus_control_|db[5]~14_combout ), + .combout(\z80_|pla_decode_|Equal49~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[5]~14 .lut_mask = 16'hF300; -defparam \z80_|bus_control_|db[5]~14 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal49~0 .lut_mask = 16'h3000; +defparam \z80_|pla_decode_|Equal49~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y10_N22 -cycloneive_lcell_comb \z80_|bus_control_|db[5]~15 ( +// Location: LCCOMB_X24_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ixy_d~15 ( // Equation(s): -// \z80_|bus_control_|db[5]~15_combout = ((\z80_|bus_control_|db[5]~14_combout & ((\z80_|alu_control_|db[5]~15_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) +// \z80_|execute_|ixy_d~15_combout = ((\z80_|decode_state_|use_ixiy~combout & (\z80_|execute_|ixy_d~11_combout & \z80_|pla_decode_|Equal49~0_combout ))) # (!\z80_|execute_|ixy_d~14_combout ) - .dataa(\z80_|bus_control_|db[0]~6_combout ), - .datab(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datac(\z80_|alu_control_|db[5]~15_combout ), - .datad(\z80_|bus_control_|db[5]~14_combout ), + .dataa(\z80_|decode_state_|use_ixiy~combout ), + .datab(\z80_|execute_|ixy_d~11_combout ), + .datac(\z80_|execute_|ixy_d~14_combout ), + .datad(\z80_|pla_decode_|Equal49~0_combout ), .cin(gnd), - .combout(\z80_|bus_control_|db[5]~15_combout ), + .combout(\z80_|execute_|ixy_d~15_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[5]~15 .lut_mask = 16'hF755; -defparam \z80_|bus_control_|db[5]~15 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ixy_d~15 .lut_mask = 16'h8F0F; +defparam \z80_|execute_|ixy_d~15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X34_Y10_N13 -dffeas \z80_|ir_|opcode[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|bus_control_|db[5]~15_combout ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|ir_|opcode [5]), - .prn(vcc)); +// Location: LCCOMB_X28_Y18_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout = (\z80_|execute_|ixy_d~15_combout & \z80_|sequencer_|DFFE_T5_ff~q ) + + .dataa(gnd), + .datab(\z80_|execute_|ixy_d~15_combout ), + .datac(\z80_|sequencer_|DFFE_T5_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), + .cout()); // synopsys translate_off -defparam \z80_|ir_|opcode[5] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[5] .power_up = "low"; +defparam \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 .lut_mask = 16'hC0C0; +defparam \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y15_N20 +// Location: LCCOMB_X26_Y16_N28 cycloneive_lcell_comb \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 ( // Equation(s): // \z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (((!\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout )))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (!\z80_|ir_|opcode [5] & @@ -40796,17 +6454,17 @@ cycloneive_lcell_comb \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 ( .dataa(\z80_|ir_|opcode [5]), .datab(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), - .datac(\z80_|pla_decode_|Equal3~2_combout ), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|pla_decode_|Equal3~2_combout ), .cin(gnd), .combout(\z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'h3350; +defparam \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'h3530; defparam \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X37_Y15_N21 +// Location: FF_X26_Y16_N29 dffeas \z80_|decode_state_|DFFE_inst4 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout ), @@ -40825,525 +6483,32592 @@ defparam \z80_|decode_state_|DFFE_inst4 .is_wysiwyg = "true"; defparam \z80_|decode_state_|DFFE_inst4 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X40_Y18_N4 -cycloneive_lcell_comb \z80_|decode_state_|use_ixiy ( +// Location: LCCOMB_X25_Y16_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~5 ( // Equation(s): -// \z80_|decode_state_|use_ixiy~combout = (\z80_|decode_state_|DFFE_inst4~q ) # (\z80_|decode_state_|DFFE_instIY1~q ) +// \z80_|execute_|ctl_ir_we~5_combout = (\z80_|decode_state_|DFFE_instCB~q & (!\z80_|decode_state_|DFFE_inst4~q & !\z80_|decode_state_|DFFE_instIY1~q )) - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(gnd), - .datac(\z80_|decode_state_|DFFE_instIY1~q ), - .datad(gnd), + .dataa(\z80_|decode_state_|DFFE_instCB~q ), + .datab(\z80_|decode_state_|DFFE_inst4~q ), + .datac(gnd), + .datad(\z80_|decode_state_|DFFE_instIY1~q ), .cin(gnd), - .combout(\z80_|decode_state_|use_ixiy~combout ), + .combout(\z80_|execute_|ctl_ir_we~5_combout ), .cout()); // synopsys translate_off -defparam \z80_|decode_state_|use_ixiy .lut_mask = 16'hFAFA; -defparam \z80_|decode_state_|use_ixiy .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_ir_we~5 .lut_mask = 16'h0022; +defparam \z80_|execute_|ctl_ir_we~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y17_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~23 ( +// Location: LCCOMB_X24_Y17_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~13 ( // Equation(s): -// \z80_|execute_|ctl_mRead~23_combout = (!\z80_|decode_state_|use_ixiy~combout & (!\z80_|decode_state_|in_halt~q & (\z80_|pla_decode_|Equal77~0_combout & \z80_|pla_decode_|Equal33~0_combout ))) +// \z80_|execute_|ctl_ir_we~13_combout = ((\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|pla_decode_|Equal41~2_combout ) # (\z80_|execute_|ctl_ir_we~5_combout )))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) - .dataa(\z80_|decode_state_|use_ixiy~combout ), - .datab(\z80_|decode_state_|in_halt~q ), - .datac(\z80_|pla_decode_|Equal77~0_combout ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~23 .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_mRead~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N16 -cycloneive_lcell_comb \z80_|execute_|fMRead~34 ( -// Equation(s): -// \z80_|execute_|fMRead~34_combout = (\z80_|execute_|ctl_mRead~23_combout ) # (((\z80_|execute_|ctl_ir_we~12_combout ) # (!\z80_|execute_|fMRead~5_combout )) # (!\z80_|execute_|fMWrite~3_combout )) - - .dataa(\z80_|execute_|ctl_mRead~23_combout ), - .datab(\z80_|execute_|fMWrite~3_combout ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|execute_|fMRead~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~34 .lut_mask = 16'hFBFF; -defparam \z80_|execute_|fMRead~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N14 -cycloneive_lcell_comb \z80_|execute_|fMRead~31 ( -// Equation(s): -// \z80_|execute_|fMRead~31_combout = (\z80_|execute_|ixy_d~6_combout & ((\z80_|pla_decode_|Equal33~3_combout ) # ((\z80_|pla_decode_|Equal6~1_combout )))) # (!\z80_|execute_|ixy_d~6_combout & (\z80_|execute_|ixy_d~5_combout & -// ((\z80_|pla_decode_|Equal33~3_combout ) # (\z80_|pla_decode_|Equal6~1_combout )))) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|pla_decode_|Equal33~3_combout ), - .datac(\z80_|pla_decode_|Equal6~1_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~31 .lut_mask = 16'hFCA8; -defparam \z80_|execute_|fMRead~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|fMRead~29 ( -// Equation(s): -// \z80_|execute_|fMRead~29_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|execute_|ctl_ir_we~5_combout & ((\z80_|ir_|opcode [6]) # (\z80_|ir_|opcode [7])))) - - .dataa(\z80_|ir_|opcode [6]), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|ir_|opcode [7]), + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|pla_decode_|Equal41~2_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), .datad(\z80_|execute_|ctl_ir_we~5_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~29_combout ), + .combout(\z80_|execute_|ctl_ir_we~13_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~29 .lut_mask = 16'hC800; -defparam \z80_|execute_|fMRead~29 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_ir_we~13 .lut_mask = 16'hF5D5; +defparam \z80_|execute_|ctl_ir_we~13 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y16_N14 -cycloneive_lcell_comb \z80_|execute_|fMRead~30 ( +// Location: FF_X30_Y17_N31 +dffeas \z80_|ir_|opcode[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|bus_control_|db[3]~21_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|ir_|opcode [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|ir_|opcode[3] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y16_N26 +cycloneive_lcell_comb \z80_|pla_decode_|Equal8~0 ( // Equation(s): -// \z80_|execute_|fMRead~30_combout = (\z80_|execute_|ctl_alu_shift_oe~14_combout & ((\z80_|execute_|ctl_ir_we~9_combout ) # ((\z80_|execute_|fMRead~29_combout ) # (\z80_|execute_|ctl_ir_we~10_combout )))) +// \z80_|pla_decode_|Equal8~0_combout = (!\z80_|ir_|opcode [2] & (\z80_|ir_|opcode [1] & \z80_|ir_|opcode [0])) + + .dataa(\z80_|ir_|opcode [2]), + .datab(gnd), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal8~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal8~0 .lut_mask = 16'h5000; +defparam \z80_|pla_decode_|Equal8~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~6 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~6_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal8~0_combout & \z80_|pla_decode_|Equal13~0_combout )) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|pla_decode_|Equal8~0_combout ), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~6 .lut_mask = 16'h3000; +defparam \z80_|execute_|ctl_mRead~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N10 +cycloneive_lcell_comb \z80_|pla_decode_|Equal9~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal9~0_combout = (!\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [3]) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [4]), + .datac(gnd), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal9~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal9~0 .lut_mask = 16'h0033; +defparam \z80_|pla_decode_|Equal9~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal9~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal9~1_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal1~7_combout & \z80_|pla_decode_|Equal9~0_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal2~0_combout ), + .datac(\z80_|pla_decode_|Equal1~7_combout ), + .datad(\z80_|pla_decode_|Equal9~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal9~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal9~1 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal9~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal9~1_combout & \z80_|sequencer_|M5~q )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|pla_decode_|Equal9~1_combout ), + .datad(\z80_|sequencer_|M5~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 .lut_mask = 16'h3000; +defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~28 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~28_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout & (((!\z80_|execute_|ctl_mRead~8_combout & !\z80_|execute_|ctl_mRead~6_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|execute_|ctl_mRead~8_combout ), + .datac(\z80_|execute_|ctl_mRead~6_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~28 .lut_mask = 16'h0057; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y16_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal13~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal13~1_combout = (\z80_|ir_|opcode [2] & (\z80_|ir_|opcode [1] & \z80_|ir_|opcode [0])) + + .dataa(\z80_|ir_|opcode [2]), + .datab(gnd), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal13~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal13~1 .lut_mask = 16'hA000; +defparam \z80_|pla_decode_|Equal13~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y17_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal69~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal69~0_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|ir_|opcode [4] & \z80_|pla_decode_|Equal13~1_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|pla_decode_|Equal13~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal69~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal69~0 .lut_mask = 16'h4000; +defparam \z80_|pla_decode_|Equal69~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout = (\z80_|pla_decode_|Equal1~4_combout & (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal13~0_combout & \z80_|ir_|opcode [0]))) + + .dataa(\z80_|pla_decode_|Equal1~4_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~27 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~27_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal6~0_combout & ((!\z80_|pla_decode_|Equal21~0_combout ) # (!\z80_|ir_|opcode [5])))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal3~1_combout ), + .datac(\z80_|pla_decode_|Equal21~0_combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~27 .lut_mask = 16'h4C00; +defparam \z80_|execute_|ctl_alu_op_low~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~2_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|pla_decode_|Equal69~0_combout ) # (\z80_|execute_|ctl_alu_op_low~27_combout )))) + + .dataa(\z80_|pla_decode_|Equal69~0_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~2 .lut_mask = 16'hFCF8; +defparam \z80_|execute_|ctl_reg_out_lo~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|rsel3 ( +// Equation(s): +// \z80_|execute_|rsel3~combout = \z80_|ir_|opcode [3] $ (((\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4]))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(gnd), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|rsel3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|rsel3 .lut_mask = 16'h5FA0; +defparam \z80_|execute_|rsel3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~12 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~12_combout = (\z80_|execute_|ctl_ir_we~5_combout & (!\z80_|ir_|opcode [7] & (\z80_|pla_decode_|Equal33~0_combout & \z80_|ir_|opcode [6]))) + + .dataa(\z80_|execute_|ctl_ir_we~5_combout ), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~12 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_ir_we~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|execute_|ctl_ir_we~12_combout & \z80_|sequencer_|DFFE_T3_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(gnd), + .datac(\z80_|execute_|ctl_ir_we~12_combout ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal56~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal56~0_combout = (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal1~4_combout & \z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|pla_decode_|Equal1~4_combout ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal56~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal56~0 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal56~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~24 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~24_combout = (\z80_|pla_decode_|Equal2~0_combout & (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|ir_|opcode [3]))) + + .dataa(\z80_|pla_decode_|Equal2~0_combout ), + .datab(\z80_|ir_|opcode [0]), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~24 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_alu_op_low~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~25 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~25_combout = (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|ir_|opcode [3]))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal2~0_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~25 .lut_mask = 16'h0040; +defparam \z80_|execute_|ctl_alu_op_low~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N16 +cycloneive_lcell_comb \z80_|execute_|nextM~2 ( +// Equation(s): +// \z80_|execute_|nextM~2_combout = (!\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_alu_op_low~24_combout & !\z80_|execute_|ctl_alu_op_low~25_combout )) + + .dataa(\z80_|pla_decode_|Equal56~0_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op_low~24_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~2 .lut_mask = 16'h0005; +defparam \z80_|execute_|nextM~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~16 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~16_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # ((\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T3_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|execute_|nextM~2_combout ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~16 .lut_mask = 16'h3320; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~3_combout = (\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ) # ((\z80_|execute_|ctl_reg_out_lo~2_combout & \z80_|execute_|rsel3~combout ))) + + .dataa(\z80_|execute_|ctl_reg_out_lo~2_combout ), + .datab(\z80_|execute_|rsel3~combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~3 .lut_mask = 16'hFFF8; +defparam \z80_|execute_|ctl_reg_out_lo~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y13_N22 +cycloneive_lcell_comb \z80_|pla_decode_|Equal40~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal40~0_combout = (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [1])) + + .dataa(\z80_|ir_|opcode [0]), + .datab(gnd), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal40~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal40~0 .lut_mask = 16'h0005; +defparam \z80_|pla_decode_|Equal40~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y13_N18 +cycloneive_lcell_comb \z80_|pla_decode_|Equal40~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal40~1_combout = (\z80_|pla_decode_|Equal40~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|ir_|opcode [5])) + + .dataa(\z80_|pla_decode_|Equal40~0_combout ), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(gnd), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal40~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal40~1 .lut_mask = 16'h8800; +defparam \z80_|pla_decode_|Equal40~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|execute_|ixy_d~7_combout & \z80_|pla_decode_|Equal1~7_combout ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal3~1_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|pla_decode_|Equal1~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y17_N24 +cycloneive_lcell_comb \z80_|pla_decode_|Equal3~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal3~0_combout = (\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3]) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [4]), + .datac(gnd), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal3~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal3~0 .lut_mask = 16'hCC00; +defparam \z80_|pla_decode_|Equal3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y13_N20 +cycloneive_lcell_comb \z80_|pla_decode_|Equal39~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal39~0_combout = (\z80_|pla_decode_|Equal40~0_combout & (\z80_|pla_decode_|Equal6~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal3~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal40~0_combout ), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal3~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal39~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal39~0 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal39~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~4_combout = (\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ) # ((\z80_|execute_|ixy_d~9_combout & ((\z80_|pla_decode_|Equal40~1_combout ) # (\z80_|pla_decode_|Equal39~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal40~1_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ), + .datac(\z80_|pla_decode_|Equal39~0_combout ), + .datad(\z80_|execute_|ixy_d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~4 .lut_mask = 16'hFECC; +defparam \z80_|execute_|ctl_reg_out_lo~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y18_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~0_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|M5~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|M5~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~0 .lut_mask = 16'h0F00; +defparam \z80_|execute_|ctl_alu_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|comb~0 ( +// Equation(s): +// \z80_|execute_|comb~0_combout = (\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|execute_|comb~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|comb~0 .lut_mask = 16'hF000; +defparam \z80_|execute_|comb~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N28 +cycloneive_lcell_comb \z80_|pla_decode_|Equal41~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal41~0_combout = (\z80_|ir_|opcode [6] & \z80_|ir_|opcode [7]) + + .dataa(\z80_|ir_|opcode [6]), + .datab(gnd), + .datac(gnd), + .datad(\z80_|ir_|opcode [7]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal41~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal41~0 .lut_mask = 16'hAA00; +defparam \z80_|pla_decode_|Equal41~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N30 +cycloneive_lcell_comb \z80_|pla_decode_|Equal47~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal47~0_combout = (\z80_|ir_|opcode [0] & (!\z80_|decode_state_|table_xx~0_combout & (\z80_|execute_|comb~0_combout & \z80_|pla_decode_|Equal41~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|decode_state_|table_xx~0_combout ), + .datac(\z80_|execute_|comb~0_combout ), + .datad(\z80_|pla_decode_|Equal41~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal47~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal47~0 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal47~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y18_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~32 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~32_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|pla_decode_|Equal47~0_combout & ((!\z80_|execute_|ctl_alu_oe~0_combout ) # (!\z80_|pla_decode_|Equal34~0_combout )))) # (!\z80_|execute_|ixy_d~7_combout & +// (((!\z80_|execute_|ctl_alu_oe~0_combout )) # (!\z80_|pla_decode_|Equal34~0_combout ))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|pla_decode_|Equal34~0_combout ), + .datac(\z80_|execute_|ctl_alu_oe~0_combout ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~32 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_inc_cy~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N22 +cycloneive_lcell_comb \z80_|pla_decode_|Equal19~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal19~0_combout = (\z80_|pla_decode_|Equal1~7_combout & (\z80_|pla_decode_|Equal32~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal3~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal1~7_combout ), + .datab(\z80_|pla_decode_|Equal32~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal3~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal19~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal19~0 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal19~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~9_combout = (\z80_|execute_|ctl_inc_cy~32_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|sequencer_|M5~q )) # (!\z80_|pla_decode_|Equal19~0_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~32_combout ), + .datab(\z80_|pla_decode_|Equal19~0_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|M5~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~9 .lut_mask = 16'hA2AA; +defparam \z80_|execute_|ctl_reg_out_lo~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~5_combout = ((\z80_|execute_|ctl_reg_out_lo~3_combout ) # ((\z80_|execute_|ctl_reg_out_lo~4_combout ) # (!\z80_|execute_|ctl_reg_out_lo~9_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~3_combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~4_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~5 .lut_mask = 16'hFDFF; +defparam \z80_|execute_|ctl_reg_out_lo~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~4 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~4_combout = (\z80_|decode_state_|DFFE_instED~q & (\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [7] & !\z80_|ir_|opcode [6]))) + + .dataa(\z80_|decode_state_|DFFE_instED~q ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~4 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_mWrite~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout = (\z80_|pla_decode_|Equal2~0_combout & (\z80_|execute_|ctl_mWrite~4_combout & (!\z80_|ir_|opcode [0] & \z80_|execute_|ctl_alu_op_low~22_combout ))) + + .dataa(\z80_|pla_decode_|Equal2~0_combout ), + .datab(\z80_|execute_|ctl_mWrite~4_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|execute_|ctl_alu_op_low~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~34 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~34_combout = (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [2] & (\z80_|ir_|opcode [1] & \z80_|execute_|ctl_mWrite~4_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|execute_|ctl_mWrite~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~34 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_mRead~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|execute_|ixy_d~15_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|execute_|ixy_d~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y17_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~36 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~36_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout & (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|execute_|ctl_mRead~34_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~36 .lut_mask = 16'h0015; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~5 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~5_combout = (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T4_ff~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~5 .lut_mask = 16'hC0C0; +defparam \z80_|execute_|ctl_mWrite~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N6 +cycloneive_lcell_comb \z80_|execute_|nextM~11 ( +// Equation(s): +// \z80_|execute_|nextM~11_combout = ((!\z80_|execute_|ctl_alu_op_low~25_combout & (!\z80_|execute_|ctl_alu_op_low~24_combout & !\z80_|pla_decode_|Equal56~0_combout ))) # (!\z80_|execute_|ctl_mWrite~5_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~25_combout ), + .datab(\z80_|execute_|ctl_mWrite~5_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~24_combout ), + .datad(\z80_|pla_decode_|Equal56~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~11 .lut_mask = 16'h3337; +defparam \z80_|execute_|nextM~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N26 +cycloneive_lcell_comb \z80_|pla_decode_|Equal20~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal20~0_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|execute_|comb~0_combout & !\z80_|ir_|opcode [5]))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|execute_|comb~0_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal20~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal20~0 .lut_mask = 16'h0080; +defparam \z80_|pla_decode_|Equal20~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y17_N10 +cycloneive_lcell_comb \z80_|pla_decode_|Equal13~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal13~2_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [4] & \z80_|pla_decode_|Equal13~1_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|pla_decode_|Equal13~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal13~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal13~2 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal13~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~24 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~24_combout = (\z80_|pla_decode_|Equal13~2_combout & !\z80_|ir_|opcode [3]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~24 .lut_mask = 16'h00F0; +defparam \z80_|execute_|ctl_mRead~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~27 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~27_combout = (\z80_|pla_decode_|Equal20~0_combout & (!\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ctl_mRead~24_combout ) # (!\z80_|execute_|ixy_d~6_combout )))) # (!\z80_|pla_decode_|Equal20~0_combout & +// (((!\z80_|execute_|ctl_mRead~24_combout ) # (!\z80_|execute_|ixy_d~6_combout )))) + + .dataa(\z80_|pla_decode_|Equal20~0_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ctl_mRead~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~27 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y17_N20 +cycloneive_lcell_comb \z80_|pla_decode_|Equal48~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal48~0_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [4] & \z80_|pla_decode_|Equal13~1_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|pla_decode_|Equal13~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal48~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal48~0 .lut_mask = 16'h0400; +defparam \z80_|pla_decode_|Equal48~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y16_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal10~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal10~0_combout = (!\z80_|ir_|opcode [1] & (\z80_|execute_|ctl_mWrite~4_combout & (!\z80_|ir_|opcode [2] & \z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [1]), + .datab(\z80_|execute_|ctl_mWrite~4_combout ), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal10~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal10~0 .lut_mask = 16'h0400; +defparam \z80_|pla_decode_|Equal10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y16_N0 +cycloneive_lcell_comb \z80_|pla_decode_|Equal11~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal11~0_combout = (!\z80_|ir_|opcode [1] & (\z80_|execute_|ctl_mWrite~4_combout & (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [1]), + .datab(\z80_|execute_|ctl_mWrite~4_combout ), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal11~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal11~0 .lut_mask = 16'h0004; +defparam \z80_|pla_decode_|Equal11~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N24 +cycloneive_lcell_comb \z80_|pla_decode_|Equal63~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal63~0_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|execute_|comb~0_combout & \z80_|ir_|opcode [5]))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|execute_|comb~0_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal63~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal63~0 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal63~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf2_we ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf2_we~combout = (\z80_|pla_decode_|Equal63~0_combout & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (!\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [3]))) + + .dataa(\z80_|pla_decode_|Equal63~0_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf2_we~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf2_we .lut_mask = 16'h0008; +defparam \z80_|execute_|ctl_flags_hf2_we .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~41 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~41_combout = (!\z80_|execute_|ctl_flags_hf2_we~combout & (((!\z80_|pla_decode_|Equal10~0_combout & !\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|execute_|ctl_flags_hf2_we~combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~41 .lut_mask = 16'h010F; +defparam \z80_|execute_|ctl_alu_shift_oe~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y13_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal68~3 ( +// Equation(s): +// \z80_|pla_decode_|Equal68~3_combout = (\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [1] & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal68~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal68~3 .lut_mask = 16'h0020; +defparam \z80_|pla_decode_|Equal68~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~7_combout = (\z80_|execute_|ctl_alu_op_low~27_combout ) # ((\z80_|pla_decode_|Equal68~3_combout ) # ((\z80_|pla_decode_|Equal21~0_combout & \z80_|pla_decode_|Equal63~0_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~27_combout ), + .datab(\z80_|pla_decode_|Equal68~3_combout ), + .datac(\z80_|pla_decode_|Equal21~0_combout ), + .datad(\z80_|pla_decode_|Equal63~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~7 .lut_mask = 16'hFEEE; +defparam \z80_|execute_|ctl_flags_bus~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~8_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|execute_|ctl_alu_op_low~25_combout ) # ((\z80_|execute_|ctl_flags_bus~7_combout ) # (\z80_|pla_decode_|Equal20~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~25_combout ), + .datab(\z80_|execute_|ctl_flags_bus~7_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|pla_decode_|Equal20~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~8 .lut_mask = 16'hF0E0; +defparam \z80_|execute_|ctl_flags_bus~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N18 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~9 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~9_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|execute_|ctl_alu_op_low~24_combout & !\z80_|pla_decode_|Equal56~0_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) + + .dataa(\z80_|execute_|ctl_alu_op_low~24_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|pla_decode_|Equal56~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~9 .lut_mask = 16'hCFDF; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~6_combout = (!\z80_|ir_|opcode [6] & !\z80_|ir_|opcode [7]) + + .dataa(\z80_|ir_|opcode [6]), + .datab(gnd), + .datac(gnd), + .datad(\z80_|ir_|opcode [7]), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~6 .lut_mask = 16'h0055; +defparam \z80_|execute_|ctl_ir_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~8_combout = (\z80_|execute_|ctl_ir_we~5_combout & (\z80_|execute_|ctl_ir_we~6_combout & ((!\z80_|decode_state_|DFFE_instCB~q ) # (!\z80_|pla_decode_|Equal33~0_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~5_combout ), + .datab(\z80_|execute_|ctl_ir_we~6_combout ), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|decode_state_|DFFE_instCB~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~8 .lut_mask = 16'h0888; +defparam \z80_|execute_|ctl_ir_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~14 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~14_combout = (\z80_|execute_|ctl_ir_we~5_combout & (!\z80_|ir_|opcode [7] & (\z80_|pla_decode_|Equal33~0_combout & !\z80_|ir_|opcode [6]))) + + .dataa(\z80_|execute_|ctl_ir_we~5_combout ), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~14 .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_ir_we~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~4_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~8_combout & !\z80_|execute_|ctl_ir_we~14_combout ))) # (!\z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|execute_|ctl_ir_we~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~4 .lut_mask = 16'hF3F7; +defparam \z80_|execute_|ctl_flags_bus~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~5_combout = (\z80_|execute_|ixy_d~10_combout ) # ((\z80_|pla_decode_|Equal63~0_combout & ((\z80_|pla_decode_|Equal32~0_combout ) # (\z80_|pla_decode_|Equal3~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal32~0_combout ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|execute_|ixy_d~10_combout ), + .datad(\z80_|pla_decode_|Equal3~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~5 .lut_mask = 16'hFCF8; +defparam \z80_|execute_|ctl_flags_bus~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~4 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~4_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal3~1_combout & (!\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~1_combout ), + .datab(\z80_|pla_decode_|Equal3~1_combout ), + .datac(\z80_|decode_state_|use_ixiy~combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~4 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_mRead~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~6_combout = ((!\z80_|execute_|ctl_flags_bus~5_combout & (!\z80_|pla_decode_|Equal13~2_combout & !\z80_|execute_|ctl_mRead~4_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) + + .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), + .datab(\z80_|pla_decode_|Equal13~2_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|execute_|ctl_mRead~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~6 .lut_mask = 16'h0F1F; +defparam \z80_|execute_|ctl_flags_bus~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~9 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~9_combout = (!\z80_|execute_|ctl_flags_bus~8_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~9_combout & (\z80_|execute_|ctl_flags_bus~4_combout & \z80_|execute_|ctl_flags_bus~6_combout ))) + + .dataa(\z80_|execute_|ctl_flags_bus~8_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~9_combout ), + .datac(\z80_|execute_|ctl_flags_bus~4_combout ), + .datad(\z80_|execute_|ctl_flags_bus~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~9 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_flags_bus~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_iorw~11 ( +// Equation(s): +// \z80_|execute_|ctl_iorw~11_combout = (!\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_iorw~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_iorw~11 .lut_mask = 16'h0004; +defparam \z80_|execute_|ctl_iorw~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y16_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~17 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~17_combout = (\z80_|ir_|opcode [1] & (\z80_|execute_|ctl_mWrite~4_combout & (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [1]), + .datab(\z80_|execute_|ctl_mWrite~4_combout ), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~17 .lut_mask = 16'h0008; +defparam \z80_|execute_|ctl_mWrite~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y14_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~18 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~18_combout = ((!\z80_|execute_|ctl_iorw~11_combout & (!\z80_|execute_|ctl_mWrite~17_combout & !\z80_|execute_|ctl_mRead~34_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) + + .dataa(\z80_|execute_|ctl_iorw~11_combout ), + .datab(\z80_|execute_|ctl_mWrite~17_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~18 .lut_mask = 16'h01FF; +defparam \z80_|execute_|ctl_alu_shift_oe~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N14 +cycloneive_lcell_comb \z80_|pla_decode_|Equal37~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal37~0_combout = (!\z80_|ir_|opcode [0] & (!\z80_|decode_state_|table_xx~0_combout & (\z80_|pla_decode_|Equal1~4_combout & \z80_|pla_decode_|Equal41~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|decode_state_|table_xx~0_combout ), + .datac(\z80_|pla_decode_|Equal1~4_combout ), + .datad(\z80_|pla_decode_|Equal41~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal37~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal37~0 .lut_mask = 16'h1000; +defparam \z80_|pla_decode_|Equal37~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~19 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~19_combout = (\z80_|pla_decode_|Equal41~2_combout ) # ((\z80_|pla_decode_|Equal37~0_combout ) # ((\z80_|pla_decode_|Equal40~1_combout ) # (\z80_|pla_decode_|Equal34~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal41~2_combout ), + .datab(\z80_|pla_decode_|Equal37~0_combout ), + .datac(\z80_|pla_decode_|Equal40~1_combout ), + .datad(\z80_|pla_decode_|Equal34~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~19 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_alu_shift_oe~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N0 +cycloneive_lcell_comb \z80_|pla_decode_|Equal35~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal35~0_combout = (!\z80_|ir_|opcode [0] & (!\z80_|decode_state_|table_xx~0_combout & (\z80_|pla_decode_|Equal2~0_combout & \z80_|pla_decode_|Equal41~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|decode_state_|table_xx~0_combout ), + .datac(\z80_|pla_decode_|Equal2~0_combout ), + .datad(\z80_|pla_decode_|Equal41~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal35~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal35~0 .lut_mask = 16'h1000; +defparam \z80_|pla_decode_|Equal35~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y13_N0 +cycloneive_lcell_comb \z80_|pla_decode_|Equal21~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal21~1_combout = (\z80_|pla_decode_|Equal40~0_combout & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal21~0_combout & !\z80_|ir_|opcode [5]))) + + .dataa(\z80_|pla_decode_|Equal40~0_combout ), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|pla_decode_|Equal21~0_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal21~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal21~1 .lut_mask = 16'h0080; +defparam \z80_|pla_decode_|Equal21~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~17 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~17_combout = ((!\z80_|pla_decode_|Equal39~0_combout & (!\z80_|pla_decode_|Equal35~0_combout & !\z80_|pla_decode_|Equal21~1_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) + + .dataa(\z80_|pla_decode_|Equal39~0_combout ), + .datab(\z80_|pla_decode_|Equal35~0_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|pla_decode_|Equal21~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~17 .lut_mask = 16'h0F1F; +defparam \z80_|execute_|ctl_alu_shift_oe~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~20 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~20_combout = (\z80_|execute_|ctl_alu_shift_oe~18_combout & (\z80_|execute_|ctl_alu_shift_oe~17_combout & ((!\z80_|execute_|ctl_alu_shift_oe~19_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~19_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~20 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_alu_shift_oe~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~9 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~9_combout = (\z80_|pla_decode_|Equal41~0_combout & (\z80_|execute_|ctl_ir_we~5_combout & ((!\z80_|decode_state_|DFFE_instCB~q ) # (!\z80_|pla_decode_|Equal33~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|pla_decode_|Equal41~0_combout ), + .datac(\z80_|execute_|ctl_ir_we~5_combout ), + .datad(\z80_|decode_state_|DFFE_instCB~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~9 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_ir_we~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y20_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~11_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|execute_|ctl_ir_we~12_combout & !\z80_|execute_|ctl_ir_we~9_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) + + .dataa(\z80_|execute_|ctl_ir_we~12_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|execute_|ctl_ir_we~9_combout ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~11 .lut_mask = 16'hCDFF; +defparam \z80_|execute_|ctl_alu_bs_oe~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~15 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~15_combout = (\z80_|execute_|ctl_ir_we~5_combout & (\z80_|ir_|opcode [7] & (\z80_|pla_decode_|Equal33~0_combout & \z80_|ir_|opcode [6]))) + + .dataa(\z80_|execute_|ctl_ir_we~5_combout ), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~15 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_ir_we~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y20_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~7_combout = (\z80_|execute_|ctl_alu_bs_oe~11_combout & (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|execute_|ctl_ir_we~10_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~11_combout ), + .datad(\z80_|execute_|ctl_ir_we~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~7 .lut_mask = 16'h5070; +defparam \z80_|execute_|ctl_alu_bs_oe~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~7_combout = (\z80_|execute_|ctl_ir_we~5_combout & (\z80_|ir_|opcode [7] & (\z80_|pla_decode_|Equal33~0_combout & !\z80_|ir_|opcode [6]))) + + .dataa(\z80_|execute_|ctl_ir_we~5_combout ), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~7 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_ir_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N4 +cycloneive_lcell_comb \z80_|pla_decode_|Equal46~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal46~0_combout = (\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [0] & (\z80_|decode_state_|DFFE_instCB~q & \z80_|ir_|opcode [1]))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|ir_|opcode [0]), + .datac(\z80_|decode_state_|DFFE_instCB~q ), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal46~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal46~0 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal46~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~11 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~11_combout = (\z80_|ir_|opcode [6] & (!\z80_|ir_|opcode [7] & (\z80_|execute_|ctl_ir_we~5_combout & !\z80_|pla_decode_|Equal46~0_combout ))) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|execute_|ctl_ir_we~5_combout ), + .datad(\z80_|pla_decode_|Equal46~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~11 .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_ir_we~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~3 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~3_combout = (\z80_|execute_|ctl_alu_bs_oe~7_combout & (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~11_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~7_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_ir_we~7_combout ), + .datad(\z80_|execute_|ctl_ir_we~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~3 .lut_mask = 16'h222A; +defparam \z80_|execute_|ctl_bus_db_oe~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal52~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal52~1_combout = (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|decode_state_|DFFE_instED~q & (\z80_|pla_decode_|Equal41~0_combout & !\z80_|decode_state_|DFFE_instCB~q ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|decode_state_|DFFE_instED~q ), + .datac(\z80_|pla_decode_|Equal41~0_combout ), + .datad(\z80_|decode_state_|DFFE_instCB~q ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal52~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal52~1 .lut_mask = 16'h0020; +defparam \z80_|pla_decode_|Equal52~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~21 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~21_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal44~0_combout & !\z80_|pla_decode_|Equal52~1_combout ))) # (!\z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|pla_decode_|Equal44~0_combout ), + .datad(\z80_|pla_decode_|Equal52~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~21 .lut_mask = 16'hDDDF; +defparam \z80_|execute_|ctl_flags_xy_we~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~13 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~13_combout = (\z80_|execute_|ctl_flags_bus~9_combout & (\z80_|execute_|ctl_alu_shift_oe~20_combout & (\z80_|execute_|ctl_bus_db_oe~3_combout & \z80_|execute_|ctl_flags_xy_we~21_combout ))) + + .dataa(\z80_|execute_|ctl_flags_bus~9_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~20_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~3_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~13 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_flags_xy_we~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~6 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~6_combout = (!\z80_|decode_state_|DFFE_instIY1~q & (!\z80_|decode_state_|DFFE_inst4~q & (\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal44~0_combout ))) + + .dataa(\z80_|decode_state_|DFFE_instIY1~q ), + .datab(\z80_|decode_state_|DFFE_inst4~q ), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|pla_decode_|Equal44~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~6 .lut_mask = 16'h1000; +defparam \z80_|execute_|ctl_state_alu~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~14 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~14_combout = (\z80_|sequencer_|DFFE_M4_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~14 .lut_mask = 16'hA0A0; +defparam \z80_|execute_|ctl_alu_shift_oe~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~14 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~14_combout = (\z80_|execute_|ctl_alu_shift_oe~41_combout & (\z80_|execute_|ctl_flags_xy_we~13_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_state_alu~6_combout )))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~41_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~13_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~14 .lut_mask = 16'h0888; +defparam \z80_|execute_|ctl_flags_xy_we~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y19_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~24 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~24_combout = (\z80_|execute_|ctl_flags_xy_we~14_combout & (((!\z80_|pla_decode_|Equal48~0_combout & !\z80_|pla_decode_|Equal69~0_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|pla_decode_|Equal48~0_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|pla_decode_|Equal69~0_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~24 .lut_mask = 16'h3700; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y19_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~37 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~37_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout & (\z80_|execute_|nextM~11_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~27_combout & \z80_|execute_|ctl_reg_gp_sel[0]~24_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ), + .datab(\z80_|execute_|nextM~11_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~27_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~37 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel~7_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|decode_state_|table_xx~0_combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal41~0_combout ))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|decode_state_|table_xx~0_combout ), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|pla_decode_|Equal41~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel~7 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_reg_gp_sel~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|rsel0 ( +// Equation(s): +// \z80_|execute_|rsel0~combout = \z80_|ir_|opcode [0] $ (((\z80_|ir_|opcode [1] & \z80_|ir_|opcode [2]))) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|rsel0~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|rsel0 .lut_mask = 16'h3FC0; +defparam \z80_|execute_|rsel0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~3 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~3_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~3 .lut_mask = 16'h5050; +defparam \z80_|execute_|ctl_state_alu~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~0_combout = ((!\z80_|execute_|ctl_alu_op_low~24_combout & (!\z80_|execute_|ctl_alu_op_low~25_combout & !\z80_|pla_decode_|Equal56~0_combout ))) # (!\z80_|execute_|ctl_state_alu~3_combout ) + + .dataa(\z80_|execute_|ctl_state_alu~3_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~24_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~25_combout ), + .datad(\z80_|pla_decode_|Equal56~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~0 .lut_mask = 16'h5557; +defparam \z80_|execute_|ctl_reg_use_sp~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~2 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~2_combout = (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~2 .lut_mask = 16'hCC00; +defparam \z80_|execute_|ctl_state_alu~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout = (\z80_|execute_|ixy_d~15_combout & \z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|execute_|ixy_d~15_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 .lut_mask = 16'hAA00; +defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~30 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~30_combout = (\z80_|execute_|ctl_reg_use_sp~0_combout & (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout & ((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|ctl_mRead~34_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~34_combout ), + .datab(\z80_|execute_|ctl_reg_use_sp~0_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~30 .lut_mask = 16'h004C; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~12 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[0]~12_combout = ((!\z80_|pla_decode_|Equal39~0_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal40~1_combout ))) # (!\z80_|execute_|ixy_d~5_combout ) + + .dataa(\z80_|pla_decode_|Equal39~0_combout ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|pla_decode_|Equal40~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~12 .lut_mask = 16'h0F1F; +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~6_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~30_combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ), + .datab(\z80_|pla_decode_|Equal47~0_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~6 .lut_mask = 16'h20A0; +defparam \z80_|execute_|ctl_reg_out_lo~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~5 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~5_combout = (!\z80_|decode_state_|table_xx~0_combout & (!\z80_|pla_decode_|Equal33~0_combout & (\z80_|ir_|opcode [7] & !\z80_|ir_|opcode [6]))) + + .dataa(\z80_|decode_state_|table_xx~0_combout ), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~5 .lut_mask = 16'h0010; +defparam \z80_|execute_|ctl_state_alu~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~1 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~1_combout = ((!\z80_|execute_|ctl_ir_we~8_combout & (!\z80_|execute_|ctl_state_alu~5_combout & !\z80_|execute_|ctl_ir_we~11_combout ))) # (!\z80_|execute_|ctl_eval_cond~0_combout ) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_state_alu~5_combout ), + .datad(\z80_|execute_|ctl_ir_we~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~1 .lut_mask = 16'h3337; +defparam \z80_|execute_|ctl_sw_2u~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~1 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~1_combout = (\z80_|pla_decode_|Equal77~0_combout & ((\z80_|decode_state_|in_halt~q ) # ((!\z80_|pla_decode_|Equal33~0_combout & !\z80_|pla_decode_|Equal33~1_combout )))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|decode_state_|in_halt~q ), + .datac(\z80_|pla_decode_|Equal33~1_combout ), + .datad(\z80_|pla_decode_|Equal77~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~1 .lut_mask = 16'hCD00; +defparam \z80_|execute_|ctl_alu_oe~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~7 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~7_combout = (\z80_|pla_decode_|Equal77~0_combout & (\z80_|pla_decode_|Equal33~1_combout & (!\z80_|decode_state_|use_ixiy~combout & !\z80_|decode_state_|in_halt~q ))) + + .dataa(\z80_|pla_decode_|Equal77~0_combout ), + .datab(\z80_|pla_decode_|Equal33~1_combout ), + .datac(\z80_|decode_state_|use_ixiy~combout ), + .datad(\z80_|decode_state_|in_halt~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~7 .lut_mask = 16'h0008; +defparam \z80_|execute_|ctl_mWrite~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~4 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~4_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|execute_|ctl_alu_oe~1_combout & (!\z80_|execute_|ctl_mWrite~7_combout ))) # (!\z80_|execute_|ctl_eval_cond~0_combout & (((!\z80_|execute_|ctl_ir_we~4_combout ) # +// (!\z80_|execute_|ctl_mWrite~7_combout )))) + + .dataa(\z80_|execute_|ctl_alu_oe~1_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~7_combout ), + .datad(\z80_|execute_|ctl_ir_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~4 .lut_mask = 16'h0737; +defparam \z80_|execute_|ctl_sw_2u~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|setM1~57 ( +// Equation(s): +// \z80_|execute_|setM1~57_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~10_combout ))) # (!\z80_|sequencer_|DFFE_T4_ff~q ) .dataa(\z80_|execute_|ctl_ir_we~9_combout ), - .datab(\z80_|execute_|fMRead~29_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datad(\z80_|execute_|ctl_ir_we~10_combout ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|execute_|ctl_ir_we~10_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), .cin(gnd), - .combout(\z80_|execute_|fMRead~30_combout ), + .combout(\z80_|execute_|setM1~57_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~30 .lut_mask = 16'hF0E0; -defparam \z80_|execute_|fMRead~30 .sum_lutc_input = "datac"; +defparam \z80_|execute_|setM1~57 .lut_mask = 16'hFF37; +defparam \z80_|execute_|setM1~57 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X41_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|fMRead~28 ( +// Location: LCCOMB_X29_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~5 ( // Equation(s): -// \z80_|execute_|fMRead~28_combout = ((\z80_|execute_|ixy_d~6_combout & ((\z80_|pla_decode_|Equal41~2_combout ) # (\z80_|pla_decode_|Equal9~1_combout )))) # (!\z80_|execute_|nextM~4_combout ) +// \z80_|execute_|ctl_sw_2u~5_combout = (\z80_|execute_|ctl_sw_2u~1_combout & (\z80_|execute_|ctl_sw_2u~4_combout & \z80_|execute_|setM1~57_combout )) - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|pla_decode_|Equal41~2_combout ), + .dataa(gnd), + .datab(\z80_|execute_|ctl_sw_2u~1_combout ), + .datac(\z80_|execute_|ctl_sw_2u~4_combout ), + .datad(\z80_|execute_|setM1~57_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~5 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_sw_2u~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~7_combout = (\z80_|execute_|ctl_reg_out_lo~6_combout & (((!\z80_|execute_|ctl_reg_gp_sel~7_combout & \z80_|execute_|ctl_sw_2u~5_combout )) # (!\z80_|execute_|rsel0~combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel~7_combout ), + .datab(\z80_|execute_|rsel0~combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~6_combout ), + .datad(\z80_|execute_|ctl_sw_2u~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~7 .lut_mask = 16'h7030; +defparam \z80_|execute_|ctl_reg_out_lo~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~0_combout = (\z80_|execute_|ctl_alu_shift_oe~14_combout & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|execute_|ctl_mWrite~4_combout & !\z80_|ir_|opcode [0]))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datab(\z80_|pla_decode_|Equal2~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~0 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~41 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~41_combout = (\z80_|execute_|ixy_d~9_combout & (((!\z80_|pla_decode_|Equal10~0_combout & !\z80_|pla_decode_|Equal11~0_combout )))) # (!\z80_|execute_|ixy_d~9_combout & (((!\z80_|pla_decode_|Equal11~0_combout )) # +// (!\z80_|execute_|ctl_alu_shift_oe~14_combout ))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datab(\z80_|execute_|ixy_d~9_combout ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|pla_decode_|Equal11~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~41 .lut_mask = 16'h113F; +defparam \z80_|execute_|ctl_bus_inc_oe~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~86 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~86_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|pla_decode_|Equal19~0_combout ) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|pla_decode_|Equal19~0_combout ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|sequencer_|M5~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~86_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~86 .lut_mask = 16'h3F7F; +defparam \z80_|execute_|ctl_inc_cy~86 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y18_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~88 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~88_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|pla_decode_|Equal34~0_combout ) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|pla_decode_|Equal34~0_combout ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~88_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~88 .lut_mask = 16'h37FF; +defparam \z80_|execute_|ctl_inc_cy~88 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~36 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~36_combout = (\z80_|execute_|ctl_inc_cy~88_combout & (((!\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ctl_alu_op_low~22_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|pla_decode_|Equal47~0_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datad(\z80_|execute_|ctl_inc_cy~88_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~36 .lut_mask = 16'h3700; +defparam \z80_|execute_|ctl_inc_cy~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~87 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~87_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|pla_decode_|Equal9~1_combout ) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|sequencer_|M5~q ), .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|execute_|nextM~4_combout ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), .cin(gnd), - .combout(\z80_|execute_|fMRead~28_combout ), + .combout(\z80_|execute_|ctl_inc_cy~87_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~28 .lut_mask = 16'hA8FF; -defparam \z80_|execute_|fMRead~28 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~87 .lut_mask = 16'h1FFF; +defparam \z80_|execute_|ctl_inc_cy~87 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X41_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|fMRead~32 ( +// Location: LCCOMB_X20_Y18_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~26 ( // Equation(s): -// \z80_|execute_|fMRead~32_combout = ((\z80_|execute_|fMRead~31_combout ) # ((\z80_|execute_|fMRead~30_combout ) # (\z80_|execute_|fMRead~28_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ) +// \z80_|execute_|ctl_bus_inc_oe~26_combout = (\z80_|execute_|ctl_inc_cy~86_combout & (\z80_|execute_|ctl_inc_cy~36_combout & \z80_|execute_|ctl_inc_cy~87_combout )) - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ), - .datab(\z80_|execute_|fMRead~31_combout ), - .datac(\z80_|execute_|fMRead~30_combout ), - .datad(\z80_|execute_|fMRead~28_combout ), + .dataa(\z80_|execute_|ctl_inc_cy~86_combout ), + .datab(\z80_|execute_|ctl_inc_cy~36_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_inc_cy~87_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~32_combout ), + .combout(\z80_|execute_|ctl_bus_inc_oe~26_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~32 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|fMRead~32 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_inc_oe~26 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_bus_inc_oe~26 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y18_N30 +// Location: LCCOMB_X30_Y19_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~9 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~9_combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_M4_ff~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~9 .lut_mask = 16'hC0C0; +defparam \z80_|execute_|ctl_mWrite~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y18_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~1 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we~1_combout = (\z80_|pla_decode_|Equal10~0_combout & (((\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (\z80_|execute_|ctl_mWrite~9_combout )))) # (!\z80_|pla_decode_|Equal10~0_combout & (\z80_|execute_|ctl_mRead~34_combout +// & ((\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (\z80_|execute_|ctl_mWrite~9_combout )))) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datad(\z80_|execute_|ctl_mWrite~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we~1 .lut_mask = 16'hEEE0; +defparam \z80_|execute_|ctl_reg_sys_we~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y18_N20 cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~42 ( // Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~42_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~5_combout & (\z80_|execute_|ctl_inc_cy~77_combout & \z80_|execute_|ctl_inc_cy~53_combout )) +// \z80_|execute_|ctl_bus_inc_oe~42_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~0_combout & (\z80_|execute_|ctl_bus_inc_oe~41_combout & (\z80_|execute_|ctl_bus_inc_oe~26_combout & !\z80_|execute_|ctl_reg_sys_we~1_combout ))) - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), - .datab(\z80_|execute_|ctl_inc_cy~77_combout ), - .datac(\z80_|execute_|ctl_inc_cy~53_combout ), - .datad(gnd), + .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~0_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~26_combout ), + .datad(\z80_|execute_|ctl_reg_sys_we~1_combout ), .cin(gnd), .combout(\z80_|execute_|ctl_bus_inc_oe~42_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~42 .lut_mask = 16'h8080; +defparam \z80_|execute_|ctl_bus_inc_oe~42 .lut_mask = 16'h0040; defparam \z80_|execute_|ctl_bus_inc_oe~42 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y18_N12 -cycloneive_lcell_comb \z80_|execute_|fMRead~14 ( +// Location: LCCOMB_X21_Y16_N22 +cycloneive_lcell_comb \z80_|pla_decode_|Equal40~2 ( // Equation(s): -// \z80_|execute_|fMRead~14_combout = (\z80_|execute_|ctl_mRead~23_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout ) # ((\z80_|execute_|ctl_mRead~15_combout ) # (\z80_|execute_|ctl_ir_we~12_combout ))) +// \z80_|pla_decode_|Equal40~2_combout = (!\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal6~0_combout & (!\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [0]))) - .dataa(\z80_|execute_|ctl_mRead~23_combout ), + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal40~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal40~2 .lut_mask = 16'h0004; +defparam \z80_|pla_decode_|Equal40~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~14 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~14_combout = (!\z80_|pla_decode_|Equal52~1_combout & (((\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal40~2_combout )) # (!\z80_|pla_decode_|Equal21~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal52~1_combout ), + .datab(\z80_|pla_decode_|Equal21~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal40~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~14 .lut_mask = 16'h5155; +defparam \z80_|execute_|ctl_reg_sel_pc~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y16_N28 +cycloneive_lcell_comb \z80_|pla_decode_|Equal55~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal55~0_combout = (!\z80_|ir_|opcode [2] & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [0])) + + .dataa(\z80_|ir_|opcode [2]), + .datab(gnd), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal55~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal55~0 .lut_mask = 16'h0050; +defparam \z80_|pla_decode_|Equal55~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~11 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~11_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal55~0_combout & \z80_|ir_|opcode [3]))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~11 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_mRead~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N4 +cycloneive_lcell_comb \z80_|pla_decode_|Equal6~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal6~1_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal1~4_combout & \z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|pla_decode_|Equal1~4_combout ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal6~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal6~1 .lut_mask = 16'h4000; +defparam \z80_|pla_decode_|Equal6~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|setM1~36 ( +// Equation(s): +// \z80_|execute_|setM1~36_combout = (!\z80_|pla_decode_|Equal6~1_combout & (((!\z80_|ir_|opcode [5] & !\z80_|pla_decode_|Equal3~0_combout )) # (!\z80_|pla_decode_|Equal40~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal6~1_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal3~0_combout ), + .datad(\z80_|pla_decode_|Equal40~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~36 .lut_mask = 16'h0155; +defparam \z80_|execute_|setM1~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|comb~1 ( +// Equation(s): +// \z80_|execute_|comb~1_combout = (\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4]) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [5]), + .datac(gnd), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|comb~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|comb~1 .lut_mask = 16'hCC00; +defparam \z80_|execute_|comb~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~13 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~13_combout = (\z80_|execute_|comb~1_combout & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal55~0_combout ))) + + .dataa(\z80_|execute_|comb~1_combout ), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~13 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_mRead~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~11 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~11_combout = (!\z80_|pla_decode_|Equal41~2_combout & (!\z80_|execute_|ctl_mRead~13_combout & (!\z80_|execute_|ctl_mRead~8_combout & !\z80_|execute_|ctl_mRead~6_combout ))) + + .dataa(\z80_|pla_decode_|Equal41~2_combout ), + .datab(\z80_|execute_|ctl_mRead~13_combout ), + .datac(\z80_|execute_|ctl_mRead~8_combout ), + .datad(\z80_|execute_|ctl_mRead~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~11 .lut_mask = 16'h0001; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N28 +cycloneive_lcell_comb \z80_|pla_decode_|Equal24~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal24~0_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|pla_decode_|Equal2~0_combout & !\z80_|ir_|opcode [5]))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal52~0_combout ), + .datac(\z80_|pla_decode_|Equal2~0_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal24~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal24~0 .lut_mask = 16'h0080; +defparam \z80_|pla_decode_|Equal24~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N12 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~26 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~26_combout = (!\z80_|pla_decode_|Equal35~0_combout & ((\z80_|ir_|opcode [4]) # ((\z80_|ir_|opcode [3]) # (!\z80_|pla_decode_|Equal24~0_combout )))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|pla_decode_|Equal35~0_combout ), + .datad(\z80_|pla_decode_|Equal24~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~26 .lut_mask = 16'h0E0F; +defparam \z80_|execute_|pc_inc_hold~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|setM1~37 ( +// Equation(s): +// \z80_|execute_|setM1~37_combout = (!\z80_|pla_decode_|Equal19~0_combout & (\z80_|execute_|setM1~36_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~11_combout & \z80_|execute_|pc_inc_hold~26_combout ))) + + .dataa(\z80_|pla_decode_|Equal19~0_combout ), + .datab(\z80_|execute_|setM1~36_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~11_combout ), + .datad(\z80_|execute_|pc_inc_hold~26_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~37 .lut_mask = 16'h4000; +defparam \z80_|execute_|setM1~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~6 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~6_combout = (!\z80_|pla_decode_|Equal33~2_combout & (((!\z80_|pla_decode_|Equal50~0_combout & !\z80_|pla_decode_|Equal49~0_combout )) # (!\z80_|decode_state_|use_ixiy~combout ))) + + .dataa(\z80_|decode_state_|use_ixiy~combout ), + .datab(\z80_|pla_decode_|Equal50~0_combout ), + .datac(\z80_|pla_decode_|Equal33~2_combout ), + .datad(\z80_|pla_decode_|Equal49~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~6 .lut_mask = 16'h0507; +defparam \z80_|execute_|pc_inc_hold~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo~38 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo~38_combout = (\z80_|execute_|pc_inc_hold~6_combout & (((!\z80_|pla_decode_|Equal33~1_combout ) # (!\z80_|pla_decode_|Equal6~0_combout )) # (!\z80_|pla_decode_|Equal55~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|pla_decode_|Equal33~1_combout ), + .datad(\z80_|execute_|pc_inc_hold~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo~38 .lut_mask = 16'h7F00; +defparam \z80_|execute_|ctl_reg_sys_hilo~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|fMRead~7 ( +// Equation(s): +// \z80_|execute_|fMRead~7_combout = (\z80_|execute_|ctl_reg_sel_pc~14_combout & (!\z80_|execute_|ctl_mRead~11_combout & (\z80_|execute_|setM1~37_combout & \z80_|execute_|ctl_reg_sys_hilo~38_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~14_combout ), + .datab(\z80_|execute_|ctl_mRead~11_combout ), + .datac(\z80_|execute_|setM1~37_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo~38_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~7 .lut_mask = 16'h2000; +defparam \z80_|execute_|fMRead~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~12 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~12_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal6~0_combout & !\z80_|pla_decode_|Equal33~1_combout )) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~12 .lut_mask = 16'h0088; +defparam \z80_|execute_|ctl_mRead~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~31 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~31_combout = (!\z80_|execute_|ctl_mRead~12_combout & ((\z80_|ir_|opcode [3]) # ((\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal12~0_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~12_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|pla_decode_|Equal12~0_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~31 .lut_mask = 16'h5545; +defparam \z80_|execute_|ctl_bus_inc_oe~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_alu_shift_oe~14_combout & \z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~1_combout ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N12 +cycloneive_lcell_comb \z80_|nM1_int~2 ( +// Equation(s): +// \z80_|nM1_int~2_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|nM1_int~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|nM1_int~2 .lut_mask = 16'h000F; +defparam \z80_|nM1_int~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~0 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~0_combout = (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|M5~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(gnd), + .datad(\z80_|sequencer_|M5~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~0 .lut_mask = 16'hCC00; +defparam \z80_|execute_|ctl_sw_4u~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~10 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~10_combout = (\z80_|execute_|ctl_mRead~8_combout & (!\z80_|execute_|ctl_alu_shift_oe~14_combout & (!\z80_|execute_|ctl_sw_4u~0_combout ))) # (!\z80_|execute_|ctl_mRead~8_combout & +// (((!\z80_|execute_|ctl_alu_shift_oe~14_combout & !\z80_|execute_|ctl_sw_4u~0_combout )) # (!\z80_|execute_|ctl_mRead~6_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~8_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datac(\z80_|execute_|ctl_sw_4u~0_combout ), + .datad(\z80_|execute_|ctl_mRead~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~10 .lut_mask = 16'h0357; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|fMRead~6 ( +// Equation(s): +// \z80_|execute_|fMRead~6_combout = (\z80_|execute_|ctl_mRead~13_combout & (!\z80_|execute_|ctl_alu_shift_oe~14_combout & ((!\z80_|execute_|ctl_alu_op_low~22_combout ) # (!\z80_|execute_|ctl_state_alu~6_combout )))) # +// (!\z80_|execute_|ctl_mRead~13_combout & (((!\z80_|execute_|ctl_alu_op_low~22_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~13_combout ), + .datab(\z80_|execute_|ctl_state_alu~6_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~6 .lut_mask = 16'h153F; +defparam \z80_|execute_|fMRead~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~12 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~12_combout = (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|execute_|ctl_mWrite~17_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|sequencer_|DFFE_M4_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|execute_|ctl_mWrite~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~12 .lut_mask = 16'h5F7F; +defparam \z80_|execute_|ctl_inc_dec~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~15 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~15_combout = (!\z80_|nM1_int~2_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout & (\z80_|execute_|fMRead~6_combout & \z80_|execute_|ctl_inc_dec~12_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), + .datac(\z80_|execute_|fMRead~6_combout ), + .datad(\z80_|execute_|ctl_inc_dec~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~15 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N28 +cycloneive_lcell_comb \z80_|pla_decode_|Equal25~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal25~0_combout = (!\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal55~0_combout ))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal25~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal25~0 .lut_mask = 16'h4000; +defparam \z80_|pla_decode_|Equal25~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal12~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal12~1_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal2~0_combout & !\z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|pla_decode_|Equal2~0_combout ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal12~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal12~1 .lut_mask = 16'h0040; +defparam \z80_|pla_decode_|Equal12~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~38 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~38_combout = ((\z80_|pla_decode_|Equal12~1_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~14_combout & !\z80_|execute_|ctl_sw_4u~0_combout ))) # (!\z80_|pla_decode_|Equal25~0_combout ) + + .dataa(\z80_|pla_decode_|Equal25~0_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datac(\z80_|pla_decode_|Equal12~1_combout ), + .datad(\z80_|execute_|ctl_sw_4u~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~38 .lut_mask = 16'hF5F7; +defparam \z80_|execute_|ctl_inc_cy~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~82 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~82_combout = ((!\z80_|sequencer_|DFFE_M2_ff~q ) # (!\z80_|pla_decode_|Equal13~2_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|pla_decode_|Equal13~2_combout ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~82_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~82 .lut_mask = 16'h77FF; +defparam \z80_|execute_|ctl_inc_cy~82 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~14 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~14_combout = (\z80_|execute_|ctl_inc_cy~38_combout & (\z80_|execute_|ctl_inc_cy~39_combout & (\z80_|execute_|ctl_reg_sel_pc~10_combout & \z80_|execute_|ctl_inc_cy~82_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~38_combout ), + .datab(\z80_|execute_|ctl_inc_cy~39_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~10_combout ), + .datad(\z80_|execute_|ctl_inc_cy~82_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~14 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~16 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~16_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout & +// \z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~16 .lut_mask = 16'h1000; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~32 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~32_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~16_combout & (((\z80_|execute_|fMRead~7_combout & \z80_|execute_|ctl_bus_inc_oe~31_combout )) # (!\z80_|execute_|ctl_alu_op_low~22_combout ))) + + .dataa(\z80_|execute_|fMRead~7_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~31_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~32 .lut_mask = 16'hB300; +defparam \z80_|execute_|ctl_bus_inc_oe~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~77 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~77_combout = (\z80_|execute_|ixy_d~5_combout & (((!\z80_|pla_decode_|Equal37~0_combout & !\z80_|pla_decode_|Equal38~2_combout )))) # (!\z80_|execute_|ixy_d~5_combout & (((!\z80_|pla_decode_|Equal37~0_combout & +// !\z80_|pla_decode_|Equal38~2_combout )) # (!\z80_|execute_|ctl_alu_op_low~22_combout ))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datac(\z80_|pla_decode_|Equal37~0_combout ), + .datad(\z80_|pla_decode_|Equal38~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~77_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~77 .lut_mask = 16'h111F; +defparam \z80_|execute_|ctl_inc_cy~77 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N4 +cycloneive_lcell_comb \z80_|pla_decode_|Equal29~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal29~0_combout = (\z80_|pla_decode_|Equal1~7_combout & (\z80_|pla_decode_|Equal32~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal1~4_combout ))) + + .dataa(\z80_|pla_decode_|Equal1~7_combout ), + .datab(\z80_|pla_decode_|Equal32~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal1~4_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal29~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal29~0 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal29~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~78 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~78_combout = (\z80_|execute_|ctl_inc_cy~77_combout & (((!\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ctl_alu_op_low~22_combout )) # (!\z80_|pla_decode_|Equal29~0_combout ))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datac(\z80_|execute_|ctl_inc_cy~77_combout ), + .datad(\z80_|pla_decode_|Equal29~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~78_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~78 .lut_mask = 16'h10F0; +defparam \z80_|execute_|ctl_inc_cy~78 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~79 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~79_combout = (\z80_|execute_|ctl_inc_cy~78_combout & (((!\z80_|execute_|ctl_sw_4u~0_combout & !\z80_|execute_|ctl_alu_shift_oe~14_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) + + .dataa(\z80_|execute_|ctl_sw_4u~0_combout ), + .datab(\z80_|pla_decode_|Equal47~0_combout ), + .datac(\z80_|execute_|ctl_inc_cy~78_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~79_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~79 .lut_mask = 16'h3070; +defparam \z80_|execute_|ctl_inc_cy~79 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~14 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~14_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal1~4_combout ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal52~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal1~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~14 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_mRead~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y18_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~49 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~49_combout = (\z80_|execute_|ixy_d~5_combout & (!\z80_|pla_decode_|Equal9~1_combout & (!\z80_|execute_|ctl_mRead~14_combout ))) # (!\z80_|execute_|ixy_d~5_combout & (((!\z80_|pla_decode_|Equal9~1_combout & +// !\z80_|execute_|ctl_mRead~14_combout )) # (!\z80_|execute_|ctl_alu_op_low~22_combout ))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|pla_decode_|Equal9~1_combout ), + .datac(\z80_|execute_|ctl_mRead~14_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~49_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~49 .lut_mask = 16'h0357; +defparam \z80_|execute_|ctl_inc_cy~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y18_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~5_combout = ((!\z80_|pla_decode_|Equal11~0_combout & (!\z80_|execute_|ctl_mRead~34_combout & !\z80_|pla_decode_|Equal10~0_combout ))) # (!\z80_|execute_|ctl_alu_op_low~22_combout ) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~5 .lut_mask = 16'h01FF; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y18_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~40 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~40_combout = (\z80_|execute_|ctl_inc_cy~79_combout & (\z80_|execute_|ctl_inc_cy~49_combout & \z80_|execute_|ctl_reg_gp_sel[1]~5_combout )) + + .dataa(\z80_|execute_|ctl_inc_cy~79_combout ), + .datab(\z80_|execute_|ctl_inc_cy~49_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~40 .lut_mask = 16'h8080; +defparam \z80_|execute_|ctl_bus_inc_oe~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~5 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~5_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal33~1_combout & (!\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|pla_decode_|Equal33~1_combout ), + .datac(\z80_|decode_state_|use_ixiy~combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~5 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_mRead~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~44 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~44_combout = (\z80_|decode_state_|DFFE_inst4~q ) # ((\z80_|decode_state_|DFFE_instIY1~q ) # ((!\z80_|pla_decode_|Equal49~0_combout & !\z80_|pla_decode_|Equal50~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal49~0_combout ), + .datab(\z80_|decode_state_|DFFE_inst4~q ), + .datac(\z80_|pla_decode_|Equal50~0_combout ), + .datad(\z80_|decode_state_|DFFE_instIY1~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~44 .lut_mask = 16'hFFCD; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~36 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~36_combout = (\z80_|execute_|ctl_mRead~5_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout ) # ((\z80_|execute_|ctl_mRead~4_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~5_combout ), .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_mRead~15_combout ), - .datad(\z80_|execute_|ctl_ir_we~12_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ), + .datad(\z80_|execute_|ctl_mRead~4_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~14_combout ), + .combout(\z80_|execute_|ctl_bus_inc_oe~36_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~14 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|fMRead~14 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_inc_oe~36 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|ctl_bus_inc_oe~36 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y18_N18 -cycloneive_lcell_comb \z80_|execute_|fMRead~10 ( +// Location: LCCOMB_X21_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~35 ( // Equation(s): -// \z80_|execute_|fMRead~10_combout = (!\z80_|execute_|ctl_mRead~4_combout & (!\z80_|pla_decode_|Equal6~1_combout & (!\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_bus_db_oe~1_combout ))) +// \z80_|execute_|ctl_bus_inc_oe~35_combout = (\z80_|execute_|ctl_state_alu~6_combout ) # ((\z80_|pla_decode_|Equal13~2_combout ) # (\z80_|execute_|ctl_mRead~8_combout )) - .dataa(\z80_|execute_|ctl_mRead~4_combout ), - .datab(\z80_|pla_decode_|Equal6~1_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .dataa(\z80_|execute_|ctl_state_alu~6_combout ), + .datab(\z80_|pla_decode_|Equal13~2_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_mRead~8_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~10_combout ), + .combout(\z80_|execute_|ctl_bus_inc_oe~35_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~10 .lut_mask = 16'h0100; -defparam \z80_|execute_|fMRead~10 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_inc_oe~35 .lut_mask = 16'hFFEE; +defparam \z80_|execute_|ctl_bus_inc_oe~35 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y18_N28 -cycloneive_lcell_comb \z80_|execute_|fMRead~9 ( +// Location: LCCOMB_X21_Y17_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~46 ( // Equation(s): -// \z80_|execute_|fMRead~9_combout = (\z80_|execute_|ctl_mRead~23_combout ) # (((\z80_|execute_|ctl_mRead~13_combout ) # (!\z80_|execute_|nextM~3_combout )) # (!\z80_|execute_|pc_inc_hold~28_combout )) +// \z80_|execute_|ctl_bus_inc_oe~46_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|execute_|ctl_bus_inc_oe~36_combout ) # (\z80_|execute_|ctl_bus_inc_oe~35_combout )))) - .dataa(\z80_|execute_|ctl_mRead~23_combout ), - .datab(\z80_|execute_|pc_inc_hold~28_combout ), - .datac(\z80_|execute_|ctl_mRead~13_combout ), - .datad(\z80_|execute_|nextM~3_combout ), + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|execute_|ctl_bus_inc_oe~36_combout ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|execute_|ctl_bus_inc_oe~35_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~9_combout ), + .combout(\z80_|execute_|ctl_bus_inc_oe~46_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~9 .lut_mask = 16'hFBFF; -defparam \z80_|execute_|fMRead~9 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_inc_oe~46 .lut_mask = 16'h5040; +defparam \z80_|execute_|ctl_bus_inc_oe~46 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y18_N24 -cycloneive_lcell_comb \z80_|execute_|fMRead~11 ( +// Location: LCCOMB_X24_Y11_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~33 ( // Equation(s): -// \z80_|execute_|fMRead~11_combout = (\z80_|execute_|ctl_state_alu~4_combout & (((\z80_|execute_|ctl_ir_we~14_combout ) # (\z80_|execute_|fMRead~9_combout )) # (!\z80_|execute_|fMRead~10_combout ))) +// \z80_|execute_|ctl_bus_inc_oe~33_combout = (\z80_|execute_|pc_inc_hold~26_combout & (!\z80_|pla_decode_|Equal6~1_combout & ((!\z80_|pla_decode_|Equal33~2_combout ) # (!\z80_|decode_state_|use_ixiy~combout )))) - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|fMRead~10_combout ), - .datac(\z80_|execute_|ctl_ir_we~14_combout ), - .datad(\z80_|execute_|fMRead~9_combout ), + .dataa(\z80_|decode_state_|use_ixiy~combout ), + .datab(\z80_|execute_|pc_inc_hold~26_combout ), + .datac(\z80_|pla_decode_|Equal6~1_combout ), + .datad(\z80_|pla_decode_|Equal33~2_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~11_combout ), + .combout(\z80_|execute_|ctl_bus_inc_oe~33_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~11 .lut_mask = 16'hAAA2; -defparam \z80_|execute_|fMRead~11 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_inc_oe~33 .lut_mask = 16'h040C; +defparam \z80_|execute_|ctl_bus_inc_oe~33 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|fMRead~12 ( +// Location: LCCOMB_X21_Y17_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~47 ( // Equation(s): -// \z80_|execute_|fMRead~12_combout = (\z80_|execute_|ctl_ir_we~8_combout ) # ((\z80_|execute_|ctl_ir_we~14_combout ) # ((\z80_|pla_decode_|Equal49~0_combout & !\z80_|decode_state_|use_ixiy~combout ))) +// \z80_|execute_|ctl_bus_inc_oe~47_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & ((!\z80_|execute_|ctl_bus_inc_oe~33_combout ) # (!\z80_|execute_|nextM~2_combout )))) - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|execute_|nextM~2_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~47 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_bus_inc_oe~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal8~0_combout & (\z80_|sequencer_|DFFE_T5_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ))) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|pla_decode_|Equal8~0_combout ), + .datac(\z80_|sequencer_|DFFE_T5_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~45 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~45_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout & (((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|pla_decode_|Equal11~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~45 .lut_mask = 16'h070F; +defparam \z80_|execute_|ctl_bus_inc_oe~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~34 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~34_combout = ((\z80_|execute_|ctl_alu_oe~0_combout & ((\z80_|execute_|ctl_mRead~4_combout ) # (\z80_|execute_|ctl_mRead~8_combout )))) # (!\z80_|execute_|ctl_bus_inc_oe~45_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~45_combout ), + .datab(\z80_|execute_|ctl_mRead~4_combout ), + .datac(\z80_|execute_|ctl_alu_oe~0_combout ), + .datad(\z80_|execute_|ctl_mRead~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~34 .lut_mask = 16'hF5D5; +defparam \z80_|execute_|ctl_bus_inc_oe~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout = (\z80_|pla_decode_|Equal9~1_combout & (\z80_|sequencer_|M5~q & \z80_|sequencer_|DFFE_T4_ff~q )) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(gnd), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~6 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~6_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal52~0_combout & \z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal3~1_combout ), + .datac(\z80_|pla_decode_|Equal52~0_combout ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~6 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_mWrite~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~50 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~50_combout = (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|execute_|ctl_mWrite~6_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|execute_|ctl_mWrite~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~50_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~50 .lut_mask = 16'h37FF; +defparam \z80_|execute_|ctl_bus_inc_oe~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal4~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal4~0_combout = (\z80_|pla_decode_|Equal1~4_combout & (\z80_|pla_decode_|Equal1~7_combout & (\z80_|ir_|opcode [3] & \z80_|execute_|comb~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal1~4_combout ), + .datab(\z80_|pla_decode_|Equal1~7_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|execute_|comb~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal4~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal4~0 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~48 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~48_combout = (\z80_|execute_|ctl_bus_inc_oe~50_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|pla_decode_|Equal4~0_combout )) # (!\z80_|sequencer_|DFFE_T5_ff~q ))) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~50_combout ), + .datab(\z80_|sequencer_|DFFE_T5_ff~q ), + .datac(\z80_|pla_decode_|Equal4~0_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~48 .lut_mask = 16'hAA2A; +defparam \z80_|execute_|ctl_bus_inc_oe~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~49 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~49_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q ))) # (!\z80_|execute_|ctl_mRead~6_combout ) + + .dataa(\z80_|sequencer_|M5~q ), + .datab(\z80_|execute_|ctl_mRead~6_combout ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~49_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~49 .lut_mask = 16'hFF37; +defparam \z80_|execute_|ctl_bus_inc_oe~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~7 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~7_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal55~0_combout & \z80_|pla_decode_|Equal6~0_combout )) + + .dataa(\z80_|pla_decode_|Equal33~1_combout ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~7 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_mRead~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~29 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~29_combout = (\z80_|execute_|ixy_d~5_combout & (!\z80_|execute_|ctl_mWrite~17_combout & ((!\z80_|execute_|ctl_ir_we~4_combout ) # (!\z80_|execute_|ctl_mRead~7_combout )))) # (!\z80_|execute_|ixy_d~5_combout & +// (((!\z80_|execute_|ctl_ir_we~4_combout )) # (!\z80_|execute_|ctl_mRead~7_combout ))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_mRead~7_combout ), + .datac(\z80_|execute_|ctl_mWrite~17_combout ), + .datad(\z80_|execute_|ctl_ir_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~29 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_bus_inc_oe~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~11_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # (((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|sequencer_|M5~q )) + + .dataa(\z80_|execute_|ctl_ir_we~9_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|M5~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~11 .lut_mask = 16'hF1FF; +defparam \z80_|execute_|ctl_alu_core_S~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y17_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~27 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~27_combout = (\z80_|execute_|ctl_alu_oe~0_combout & (!\z80_|execute_|ctl_ir_we~14_combout & ((!\z80_|execute_|ctl_ir_we~8_combout )))) # (!\z80_|execute_|ctl_alu_oe~0_combout & (((!\z80_|execute_|ixy_d~7_combout )) # +// (!\z80_|execute_|ctl_ir_we~14_combout ))) + + .dataa(\z80_|execute_|ctl_alu_oe~0_combout ), .datab(\z80_|execute_|ctl_ir_we~14_combout ), - .datac(\z80_|pla_decode_|Equal49~0_combout ), - .datad(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ctl_ir_we~8_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~12_combout ), + .combout(\z80_|execute_|ctl_bus_inc_oe~27_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~12 .lut_mask = 16'hEEFE; -defparam \z80_|execute_|fMRead~12 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_inc_oe~27 .lut_mask = 16'h1537; +defparam \z80_|execute_|ctl_bus_inc_oe~27 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y18_N14 -cycloneive_lcell_comb \z80_|execute_|fMRead~13 ( +// Location: LCCOMB_X23_Y19_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~44 ( // Equation(s): -// \z80_|execute_|fMRead~13_combout = (!\z80_|execute_|fMWrite~5_combout & ((\z80_|execute_|fMRead~12_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout ) # (\z80_|execute_|ctl_mRead~6_combout )))) +// \z80_|execute_|ctl_bus_inc_oe~44_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~7_combout )) # (!\z80_|sequencer_|M5~q )) - .dataa(\z80_|execute_|fMRead~12_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_mRead~6_combout ), - .datad(\z80_|execute_|fMWrite~5_combout ), + .dataa(\z80_|execute_|ctl_ir_we~10_combout ), + .datab(\z80_|execute_|ctl_ir_we~7_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|M5~q ), .cin(gnd), - .combout(\z80_|execute_|fMRead~13_combout ), + .combout(\z80_|execute_|ctl_bus_inc_oe~44_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~13 .lut_mask = 16'h00FE; -defparam \z80_|execute_|fMRead~13 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_inc_oe~44 .lut_mask = 16'hF1FF; +defparam \z80_|execute_|ctl_bus_inc_oe~44 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y18_N30 -cycloneive_lcell_comb \z80_|execute_|fMRead~15 ( +// Location: LCCOMB_X25_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~28 ( // Equation(s): -// \z80_|execute_|fMRead~15_combout = (\z80_|execute_|fMRead~11_combout ) # ((\z80_|execute_|fMRead~13_combout ) # ((\z80_|execute_|fMRead~14_combout & \z80_|execute_|ctl_state_alu~6_combout ))) +// \z80_|execute_|ctl_bus_inc_oe~28_combout = (\z80_|execute_|ctl_alu_core_S~11_combout & (\z80_|execute_|ctl_bus_inc_oe~27_combout & \z80_|execute_|ctl_bus_inc_oe~44_combout )) - .dataa(\z80_|execute_|fMRead~14_combout ), - .datab(\z80_|execute_|fMRead~11_combout ), - .datac(\z80_|execute_|fMRead~13_combout ), - .datad(\z80_|execute_|ctl_state_alu~6_combout ), + .dataa(\z80_|execute_|ctl_alu_core_S~11_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~27_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_bus_inc_oe~44_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~15_combout ), + .combout(\z80_|execute_|ctl_bus_inc_oe~28_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~15 .lut_mask = 16'hFEFC; -defparam \z80_|execute_|fMRead~15 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_inc_oe~28 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_bus_inc_oe~28 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y17_N2 -cycloneive_lcell_comb \z80_|execute_|fMRead~20 ( +// Location: LCCOMB_X23_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~30 ( // Equation(s): -// \z80_|execute_|fMRead~20_combout = (((\z80_|execute_|fMRead~15_combout ) # (!\z80_|execute_|ctl_sw_4d~2_combout )) # (!\z80_|execute_|fMRead~19_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~42_combout ) +// \z80_|execute_|ctl_bus_inc_oe~30_combout = (\z80_|execute_|ctl_bus_inc_oe~49_combout & (\z80_|execute_|ctl_bus_inc_oe~29_combout & \z80_|execute_|ctl_bus_inc_oe~28_combout )) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~49_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~29_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_bus_inc_oe~28_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~30 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_bus_inc_oe~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~3 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~3_combout = (\z80_|pla_decode_|Equal1~7_combout & (\z80_|pla_decode_|Equal2~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal21~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal1~7_combout ), + .datab(\z80_|pla_decode_|Equal2~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal21~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~3 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_mRead~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|fMRead~3 ( +// Equation(s): +// \z80_|execute_|fMRead~3_combout = ((!\z80_|pla_decode_|Equal33~0_combout ) # (!\z80_|ir_|opcode [7])) # (!\z80_|execute_|ctl_ir_we~5_combout ) + + .dataa(\z80_|execute_|ctl_ir_we~5_combout ), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|fMRead~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~3 .lut_mask = 16'h7F7F; +defparam \z80_|execute_|fMRead~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~37 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~37_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mRead~3_combout ) # ((\z80_|execute_|ctl_mRead~4_combout ) # (!\z80_|execute_|fMRead~3_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~3_combout ), + .datab(\z80_|execute_|ctl_mRead~4_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|fMRead~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~37 .lut_mask = 16'hE0F0; +defparam \z80_|execute_|ctl_bus_inc_oe~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~38 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~38_combout = (\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ) # (((\z80_|execute_|ctl_bus_inc_oe~37_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~30_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~48_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~48_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~30_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~37_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~38 .lut_mask = 16'hFFBF; +defparam \z80_|execute_|ctl_bus_inc_oe~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~39 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~39_combout = (\z80_|execute_|ctl_bus_inc_oe~46_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~47_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~34_combout ) # (\z80_|execute_|ctl_bus_inc_oe~38_combout ))) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~46_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~47_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~34_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~38_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~39 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_bus_inc_oe~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~43 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~43_combout = (((\z80_|execute_|ctl_bus_inc_oe~39_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~40_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~32_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~42_combout ) .dataa(\z80_|execute_|ctl_bus_inc_oe~42_combout ), - .datab(\z80_|execute_|fMRead~19_combout ), - .datac(\z80_|execute_|fMRead~15_combout ), - .datad(\z80_|execute_|ctl_sw_4d~2_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~32_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~40_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~39_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~20_combout ), + .combout(\z80_|execute_|ctl_bus_inc_oe~43_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~20 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|fMRead~20 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_inc_oe~43 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_bus_inc_oe~43 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~48 ( +// Location: LCCOMB_X28_Y16_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~3 ( // Equation(s): -// \z80_|execute_|pc_inc_hold~48_combout = (\z80_|execute_|ixy_d~5_combout & ((\z80_|pla_decode_|Equal35~0_combout ) # ((\z80_|pla_decode_|Equal24~0_combout & \z80_|pla_decode_|Equal9~0_combout )))) +// \z80_|execute_|ctl_alu_oe~3_combout = (\z80_|decode_state_|in_halt~q ) # (((!\z80_|pla_decode_|Equal33~0_combout & !\z80_|pla_decode_|Equal33~1_combout )) # (!\z80_|pla_decode_|Equal77~0_combout )) - .dataa(\z80_|pla_decode_|Equal24~0_combout ), - .datab(\z80_|pla_decode_|Equal35~0_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|pla_decode_|Equal9~0_combout ), + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|decode_state_|in_halt~q ), + .datac(\z80_|pla_decode_|Equal33~1_combout ), + .datad(\z80_|pla_decode_|Equal77~0_combout ), .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~48_combout ), + .combout(\z80_|execute_|ctl_alu_oe~3_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~48 .lut_mask = 16'hE0C0; -defparam \z80_|execute_|pc_inc_hold~48 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_alu_oe~3 .lut_mask = 16'hCDFF; +defparam \z80_|execute_|ctl_alu_oe~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X41_Y16_N30 -cycloneive_lcell_comb \z80_|execute_|fMRead~22 ( +// Location: LCCOMB_X25_Y14_N8 +cycloneive_lcell_comb \z80_|execute_|fMWrite~1 ( // Equation(s): -// \z80_|execute_|fMRead~22_combout = (\z80_|execute_|ctl_mRead~17_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # ((\z80_|execute_|ctl_alu_oe~2_combout )))) # (!\z80_|execute_|ctl_mRead~17_combout & (\z80_|execute_|ctl_mRead~18_combout & -// ((\z80_|execute_|ctl_ir_we~4_combout ) # (\z80_|execute_|ctl_alu_oe~2_combout )))) +// \z80_|execute_|fMWrite~1_combout = (!\z80_|execute_|ctl_ir_we~15_combout & (!\z80_|execute_|ctl_mRead~4_combout & (!\z80_|execute_|ctl_ir_we~14_combout & !\z80_|execute_|ctl_ir_we~7_combout ))) - .dataa(\z80_|execute_|ctl_mRead~17_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_mRead~18_combout ), - .datad(\z80_|execute_|ctl_alu_oe~2_combout ), + .dataa(\z80_|execute_|ctl_ir_we~15_combout ), + .datab(\z80_|execute_|ctl_mRead~4_combout ), + .datac(\z80_|execute_|ctl_ir_we~14_combout ), + .datad(\z80_|execute_|ctl_ir_we~7_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~22_combout ), + .combout(\z80_|execute_|fMWrite~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~22 .lut_mask = 16'hFAC8; -defparam \z80_|execute_|fMRead~22 .sum_lutc_input = "datac"; +defparam \z80_|execute_|fMWrite~1 .lut_mask = 16'h0001; +defparam \z80_|execute_|fMWrite~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y15_N2 -cycloneive_lcell_comb \z80_|execute_|fMRead~21 ( +// Location: LCCOMB_X24_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~1 ( // Equation(s): -// \z80_|execute_|fMRead~21_combout = (\z80_|execute_|ctl_state_alu~5_combout & (((\z80_|execute_|ctl_mRead~36_combout ) # (!\z80_|execute_|fMRead~4_combout )) # (!\z80_|execute_|fMRead~2_combout ))) +// \z80_|execute_|ctl_flags_bus~1_combout = ((\z80_|ir_|opcode [2]) # (\z80_|ir_|opcode [1])) # (!\z80_|execute_|ctl_mWrite~4_combout ) - .dataa(\z80_|execute_|fMRead~2_combout ), - .datab(\z80_|execute_|ctl_mRead~36_combout ), - .datac(\z80_|execute_|ctl_state_alu~5_combout ), - .datad(\z80_|execute_|fMRead~4_combout ), + .dataa(gnd), + .datab(\z80_|execute_|ctl_mWrite~4_combout ), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [1]), .cin(gnd), - .combout(\z80_|execute_|fMRead~21_combout ), + .combout(\z80_|execute_|ctl_flags_bus~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~21 .lut_mask = 16'hD0F0; -defparam \z80_|execute_|fMRead~21 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_flags_bus~1 .lut_mask = 16'hFFF3; +defparam \z80_|execute_|ctl_flags_bus~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y15_N10 -cycloneive_lcell_comb \z80_|execute_|fMRead~23 ( +// Location: LCCOMB_X25_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|fMRead~5 ( // Equation(s): -// \z80_|execute_|fMRead~23_combout = ((\z80_|execute_|pc_inc_hold~48_combout ) # ((\z80_|execute_|fMRead~22_combout ) # (\z80_|execute_|fMRead~21_combout ))) # (!\z80_|execute_|ctl_bus_db_oe~0_combout ) +// \z80_|execute_|fMRead~5_combout = (!\z80_|pla_decode_|Equal13~2_combout & (\z80_|execute_|ctl_flags_bus~1_combout & !\z80_|execute_|ctl_state_alu~6_combout )) - .dataa(\z80_|execute_|ctl_bus_db_oe~0_combout ), - .datab(\z80_|execute_|pc_inc_hold~48_combout ), - .datac(\z80_|execute_|fMRead~22_combout ), - .datad(\z80_|execute_|fMRead~21_combout ), + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(\z80_|execute_|ctl_flags_bus~1_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(gnd), .cin(gnd), - .combout(\z80_|execute_|fMRead~23_combout ), + .combout(\z80_|execute_|fMRead~5_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~23 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|fMRead~23 .sum_lutc_input = "datac"; +defparam \z80_|execute_|fMRead~5 .lut_mask = 16'h0404; +defparam \z80_|execute_|fMRead~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y12_N8 +// Location: LCCOMB_X25_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~17 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~17_combout = (\z80_|execute_|fMWrite~1_combout & (!\z80_|execute_|ctl_ir_we~12_combout & \z80_|execute_|fMRead~5_combout )) + + .dataa(\z80_|execute_|fMWrite~1_combout ), + .datab(\z80_|execute_|ctl_ir_we~12_combout ), + .datac(gnd), + .datad(\z80_|execute_|fMRead~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~17 .lut_mask = 16'h2200; +defparam \z80_|execute_|ctl_mRead~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_iorw~10 ( +// Equation(s): +// \z80_|execute_|ctl_iorw~10_combout = (!\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [1] & \z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_iorw~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_iorw~10 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_iorw~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|setM1~47 ( +// Equation(s): +// \z80_|execute_|setM1~47_combout = (!\z80_|execute_|ctl_iorw~11_combout & (!\z80_|execute_|ctl_mRead~11_combout & (\z80_|execute_|ctl_mRead~17_combout & !\z80_|execute_|ctl_iorw~10_combout ))) + + .dataa(\z80_|execute_|ctl_iorw~11_combout ), + .datab(\z80_|execute_|ctl_mRead~11_combout ), + .datac(\z80_|execute_|ctl_mRead~17_combout ), + .datad(\z80_|execute_|ctl_iorw~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~47 .lut_mask = 16'h0010; +defparam \z80_|execute_|setM1~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~8 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~8_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal6~0_combout & (!\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal55~0_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~8 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_mWrite~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~13 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~13_combout = ((\z80_|ir_|opcode [2]) # (!\z80_|ir_|opcode [1])) # (!\z80_|execute_|ctl_mWrite~4_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_mWrite~4_combout ), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~13 .lut_mask = 16'hF3FF; +defparam \z80_|execute_|ctl_al_we~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|setM1~48 ( +// Equation(s): +// \z80_|execute_|setM1~48_combout = (\z80_|execute_|setM1~47_combout & (!\z80_|execute_|ctl_mWrite~8_combout & \z80_|execute_|ctl_al_we~13_combout )) + + .dataa(\z80_|execute_|setM1~47_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_mWrite~8_combout ), + .datad(\z80_|execute_|ctl_al_we~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~48 .lut_mask = 16'h0A00; +defparam \z80_|execute_|setM1~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~0 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~0_combout = (\z80_|execute_|ctl_state_alu~3_combout & (((!\z80_|decode_state_|use_ixiy~combout & !\z80_|execute_|ctl_alu_oe~3_combout )) # (!\z80_|execute_|setM1~48_combout ))) + + .dataa(\z80_|decode_state_|use_ixiy~combout ), + .datab(\z80_|execute_|ctl_state_alu~3_combout ), + .datac(\z80_|execute_|ctl_alu_oe~3_combout ), + .datad(\z80_|execute_|setM1~48_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~0 .lut_mask = 16'h04CC; +defparam \z80_|execute_|ctl_sw_4d~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|pla_decode_|Equal48~0_combout & !\z80_|sequencer_|DFFE_M1_ff~q )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|pla_decode_|Equal48~0_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 .lut_mask = 16'h00C0; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~9 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~9_combout = (\z80_|sequencer_|DFFE_T5_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T5_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~9 .lut_mask = 16'h00F0; +defparam \z80_|execute_|ctl_mRead~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~3_combout = (\z80_|pla_decode_|Equal10~0_combout & (!\z80_|execute_|ixy_d~7_combout & ((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|pla_decode_|Equal21~1_combout )))) # (!\z80_|pla_decode_|Equal10~0_combout & +// (((!\z80_|execute_|ctl_mRead~9_combout )) # (!\z80_|pla_decode_|Equal21~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|execute_|ctl_mRead~9_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~3 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_flags_sz_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout = (\z80_|pla_decode_|Equal11~0_combout & (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M3_ff~q )) + + .dataa(gnd), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 .lut_mask = 16'h0C00; +defparam \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~9 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~9_combout = (((!\z80_|execute_|ixy_d~6_combout & !\z80_|nM1_int~2_combout )) # (!\z80_|execute_|ctl_mWrite~4_combout )) # (!\z80_|pla_decode_|Equal8~0_combout ) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|pla_decode_|Equal8~0_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_mWrite~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~9 .lut_mask = 16'h37FF; +defparam \z80_|execute_|ctl_flags_alu~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~2 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~2_combout = ((!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal39~0_combout & !\z80_|pla_decode_|Equal40~1_combout ))) # (!\z80_|execute_|ixy_d~8_combout ) + + .dataa(\z80_|execute_|ixy_d~8_combout ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|pla_decode_|Equal39~0_combout ), + .datad(\z80_|pla_decode_|Equal40~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~2 .lut_mask = 16'h5557; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~10_combout = (\z80_|execute_|ctl_flags_sz_we~3_combout & (!\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout & (\z80_|execute_|ctl_flags_alu~9_combout & \z80_|execute_|ctl_alu_sel_op2_neg~2_combout ))) + + .dataa(\z80_|execute_|ctl_flags_sz_we~3_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), + .datac(\z80_|execute_|ctl_flags_alu~9_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~10 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_flags_alu~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~10_combout = (((!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4])) # (!\z80_|nM1_int~2_combout )) # (!\z80_|pla_decode_|Equal63~0_combout ) + + .dataa(\z80_|pla_decode_|Equal63~0_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~10 .lut_mask = 16'h777F; +defparam \z80_|execute_|ctl_flags_xy_we~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla11M1T1_11 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|pla_decode_|Equal10~0_combout )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|pla_decode_|Equal10~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel_pla11M1T1_11 .lut_mask = 16'h0300; +defparam \z80_|execute_|ctl_pf_sel_pla11M1T1_11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~11 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~11_combout = (\z80_|execute_|ctl_flags_xy_we~10_combout & (!\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout & ((!\z80_|sequencer_|DFFE_T5_ff~q ) # (!\z80_|execute_|ixy_d~15_combout )))) + + .dataa(\z80_|execute_|ctl_flags_xy_we~10_combout ), + .datab(\z80_|execute_|ixy_d~15_combout ), + .datac(\z80_|sequencer_|DFFE_T5_ff~q ), + .datad(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~11 .lut_mask = 16'h002A; +defparam \z80_|execute_|ctl_flags_xy_we~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~11 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~11_combout = (\z80_|execute_|ctl_flags_alu~10_combout & (\z80_|execute_|ctl_flags_xy_we~11_combout & ((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|execute_|ixy_d~15_combout )))) + + .dataa(\z80_|execute_|ctl_flags_alu~10_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~11_combout ), + .datac(\z80_|execute_|ixy_d~15_combout ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~11 .lut_mask = 16'h0888; +defparam \z80_|execute_|ctl_flags_alu~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~1 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~1_combout = (\z80_|execute_|ctl_reg_use_sp~0_combout & \z80_|execute_|nextM~11_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_use_sp~0_combout ), + .datad(\z80_|execute_|nextM~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~1 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_reg_use_sp~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~4 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~4_combout = (\z80_|sequencer_|DFFE_M4_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~4 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_state_alu~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~9_combout = (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|pla_decode_|Equal10~0_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|pla_decode_|Equal10~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~9 .lut_mask = 16'h777F; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~4 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~4_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & (((!\z80_|execute_|ctl_state_alu~4_combout & !\z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|execute_|ctl_mRead~4_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|ctl_mRead~4_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~4 .lut_mask = 16'h3700; +defparam \z80_|execute_|ctl_sw_2d~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~0 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~0_combout = (\z80_|execute_|ctl_mWrite~9_combout & (((!\z80_|execute_|ctl_ir_we~12_combout & !\z80_|execute_|ctl_ir_we~11_combout )))) # (!\z80_|execute_|ctl_mWrite~9_combout & (((!\z80_|execute_|ctl_ir_we~12_combout )) +// # (!\z80_|execute_|ctl_mWrite~5_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~5_combout ), + .datab(\z80_|execute_|ctl_mWrite~9_combout ), + .datac(\z80_|execute_|ctl_ir_we~12_combout ), + .datad(\z80_|execute_|ctl_ir_we~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~0 .lut_mask = 16'h131F; +defparam \z80_|execute_|ctl_flags_sz_we~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~4_combout = (\z80_|execute_|ctl_flags_sz_we~0_combout & (((!\z80_|execute_|ctl_ir_we~12_combout & !\z80_|execute_|ctl_ir_we~11_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .datab(\z80_|execute_|ctl_ir_we~12_combout ), + .datac(\z80_|execute_|ctl_ir_we~11_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~4 .lut_mask = 16'h02AA; +defparam \z80_|execute_|ctl_flags_sz_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y16_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~47 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~47_combout = (\z80_|pla_decode_|Equal8~0_combout & (\z80_|execute_|ctl_mWrite~4_combout & (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_M3_ff~q ))) + + .dataa(\z80_|pla_decode_|Equal8~0_combout ), + .datab(\z80_|execute_|ctl_mWrite~4_combout ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~47 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_op_low~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~3 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~3_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout & (((!\z80_|pla_decode_|Equal21~1_combout & !\z80_|execute_|ctl_mRead~34_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal21~1_combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~3 .lut_mask = 16'h001F; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~12 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~12_combout = (!\z80_|execute_|ctl_alu_op_low~47_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~3_combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~47_combout ), + .datab(\z80_|pla_decode_|Equal20~0_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~12 .lut_mask = 16'h1050; +defparam \z80_|execute_|ctl_flags_alu~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~23 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~23_combout = (((!\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [3])) # (!\z80_|pla_decode_|Equal63~0_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|pla_decode_|Equal63~0_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~23 .lut_mask = 16'h5F7F; +defparam \z80_|execute_|ctl_alu_op_low~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~19 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~19_combout = (\z80_|execute_|ctl_alu_op_low~23_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|pla_decode_|Equal20~0_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|execute_|ctl_alu_op_low~23_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|pla_decode_|Equal20~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~19 .lut_mask = 16'hC4CC; +defparam \z80_|execute_|ctl_flags_xy_we~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~13 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~13_combout = (\z80_|execute_|ctl_sw_2d~4_combout & (\z80_|execute_|ctl_flags_sz_we~4_combout & (\z80_|execute_|ctl_flags_alu~12_combout & \z80_|execute_|ctl_flags_xy_we~19_combout ))) + + .dataa(\z80_|execute_|ctl_sw_2d~4_combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~4_combout ), + .datac(\z80_|execute_|ctl_flags_alu~12_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~13 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_flags_alu~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_hi~4_combout = ((!\z80_|pla_decode_|Equal40~1_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal39~0_combout ))) # (!\z80_|execute_|ixy_d~9_combout ) + + .dataa(\z80_|pla_decode_|Equal40~1_combout ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|pla_decode_|Equal39~0_combout ), + .datad(\z80_|execute_|ixy_d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_hi~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_hi~4 .lut_mask = 16'h01FF; +defparam \z80_|execute_|ctl_reg_out_hi~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~1 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~1_combout = (\z80_|execute_|ctl_reg_out_hi~4_combout & \z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_out_hi~4_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~1 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_sw_4u~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~29 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~29_combout = ((!\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|execute_|ixy_d~15_combout ) + + .dataa(\z80_|execute_|ixy_d~15_combout ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~29 .lut_mask = 16'h555F; +defparam \z80_|execute_|ctl_alu_op_low~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~14 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~14_combout = (\z80_|execute_|ctl_reg_use_sp~1_combout & (\z80_|execute_|ctl_flags_alu~13_combout & (\z80_|execute_|ctl_sw_4u~1_combout & \z80_|execute_|ctl_alu_op_low~29_combout ))) + + .dataa(\z80_|execute_|ctl_reg_use_sp~1_combout ), + .datab(\z80_|execute_|ctl_flags_alu~13_combout ), + .datac(\z80_|execute_|ctl_sw_4u~1_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~29_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~14 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_flags_alu~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout = (\z80_|pla_decode_|Equal63~0_combout & (\z80_|nM1_int~2_combout & (!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4]))) + + .dataa(\z80_|pla_decode_|Equal63~0_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 .lut_mask = 16'h0008; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla82M1T1_16 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout = (!\z80_|ir_|opcode [0] & (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal3~1_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|pla_decode_|Equal3~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel_pla82M1T1_16 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_pf_sel_pla82M1T1_16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~13 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~13_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|execute_|ctl_mRead~4_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|execute_|ctl_mRead~4_combout ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~13 .lut_mask = 16'h777F; +defparam \z80_|execute_|ctl_flags_use_cf2~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~7_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|pla_decode_|Equal13~0_combout ) # (!\z80_|pla_decode_|Equal55~0_combout ))) # (!\z80_|sequencer_|DFFE_M3_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~7 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_flags_cf_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel[0]~2 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel[0]~2_combout = (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (\z80_|execute_|ctl_flags_use_cf2~13_combout & \z80_|execute_|ctl_flags_cf_we~7_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .datac(\z80_|execute_|ctl_flags_use_cf2~13_combout ), + .datad(\z80_|execute_|ctl_flags_cf_we~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel[0]~2 .lut_mask = 16'h3000; +defparam \z80_|execute_|ctl_pf_sel[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_we~5_combout = (\z80_|execute_|ctl_bus_inc_oe~27_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|execute_|ctl_ir_we~8_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|execute_|ctl_bus_inc_oe~27_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_we~5 .lut_mask = 16'hFD00; +defparam \z80_|execute_|ctl_flags_hf_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~10_combout = (\z80_|execute_|ctl_flags_hf_we~5_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|pla_decode_|Equal13~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|execute_|ctl_flags_hf_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~10 .lut_mask = 16'hFD00; +defparam \z80_|execute_|ctl_flags_pf_we~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N8 +cycloneive_lcell_comb \z80_|pla_decode_|Equal68~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal68~2_combout = (\z80_|ir_|opcode [6] & (\z80_|decode_state_|DFFE_instED~q & (!\z80_|ir_|opcode [7] & !\z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|decode_state_|DFFE_instED~q ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal68~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal68~2 .lut_mask = 16'h0008; +defparam \z80_|pla_decode_|Equal68~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~13 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~13_combout = ((!\z80_|execute_|ctl_alu_op_low~27_combout & ((!\z80_|pla_decode_|Equal68~2_combout ) # (!\z80_|pla_decode_|Equal1~4_combout )))) # (!\z80_|nM1_int~2_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~27_combout ), + .datab(\z80_|pla_decode_|Equal1~4_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal68~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~13 .lut_mask = 16'h1F5F; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~2_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout & (\z80_|execute_|ctl_pf_sel[0]~2_combout & (\z80_|execute_|ctl_flags_pf_we~10_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~13_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .datab(\z80_|execute_|ctl_pf_sel[0]~2_combout ), + .datac(\z80_|execute_|ctl_flags_pf_we~10_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~2 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_flags_pf_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~4_combout = (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|execute_|ctl_mWrite~17_combout & ((!\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|ctl_mRead~9_combout )))) # (!\z80_|execute_|ctl_state_alu~2_combout & +// (((!\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|ctl_mRead~9_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ctl_mWrite~17_combout ), + .datac(\z80_|execute_|ctl_mRead~9_combout ), + .datad(\z80_|execute_|ctl_mRead~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~4 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_alu_oe~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y18_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~8_combout = (!\z80_|execute_|ctl_reg_gp_sel~7_combout & \z80_|execute_|setM1~18_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_sel~7_combout ), + .datab(gnd), + .datac(\z80_|execute_|setM1~18_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~8 .lut_mask = 16'h5050; +defparam \z80_|execute_|ctl_flags_xy_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y19_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~20 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~20_combout = (((!\z80_|pla_decode_|Equal13~0_combout ) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|pla_decode_|Equal55~0_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~20 .lut_mask = 16'h7FFF; +defparam \z80_|execute_|ctl_flags_xy_we~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~9 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~9_combout = (\z80_|execute_|ctl_flags_pf_we~2_combout & (\z80_|execute_|ctl_alu_oe~4_combout & (\z80_|execute_|ctl_flags_xy_we~8_combout & \z80_|execute_|ctl_flags_xy_we~20_combout ))) + + .dataa(\z80_|execute_|ctl_flags_pf_we~2_combout ), + .datab(\z80_|execute_|ctl_alu_oe~4_combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~8_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~9 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_flags_xy_we~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~1 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~1_combout = ((!\z80_|execute_|ctl_state_alu~5_combout & (!\z80_|execute_|ctl_state_alu~6_combout & !\z80_|pla_decode_|Equal52~1_combout ))) # (!\z80_|nM1_int~2_combout ) + + .dataa(\z80_|execute_|ctl_state_alu~5_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|pla_decode_|Equal52~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~1 .lut_mask = 16'h3337; +defparam \z80_|execute_|ctl_flags_sz_we~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~1 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~1_combout = (!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal39~0_combout & !\z80_|pla_decode_|Equal40~1_combout )) + + .dataa(gnd), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|pla_decode_|Equal39~0_combout ), + .datad(\z80_|pla_decode_|Equal40~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~1 .lut_mask = 16'h0003; +defparam \z80_|execute_|ctl_bus_db_oe~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~10_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ixy_d~15_combout & ((\z80_|execute_|ctl_bus_db_oe~1_combout ) # (!\z80_|sequencer_|DFFE_M3_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|execute_|ixy_d~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~10 .lut_mask = 16'hF0FD; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~2_combout = (\z80_|execute_|ctl_flags_xy_we~9_combout & (\z80_|execute_|ctl_flags_sz_we~1_combout & \z80_|execute_|ctl_alu_op2_sel_bus~10_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_flags_xy_we~9_combout ), + .datac(\z80_|execute_|ctl_flags_sz_we~1_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~2 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_flags_sz_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y17_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~17 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~17_combout = (((!\z80_|execute_|ctl_ir_we~14_combout & !\z80_|execute_|ctl_ir_we~8_combout )) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|execute_|ctl_ir_we~14_combout ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|execute_|ctl_ir_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~17 .lut_mask = 16'h5F7F; +defparam \z80_|execute_|ctl_flags_alu~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~18 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~18_combout = (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|execute_|ctl_ir_we~7_combout ), + .datad(\z80_|execute_|ctl_ir_we~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~18 .lut_mask = 16'h777F; +defparam \z80_|execute_|ctl_flags_alu~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~6_combout = (\z80_|execute_|ctl_flags_alu~18_combout & (((!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~9_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~15_combout ), + .datab(\z80_|execute_|ctl_flags_alu~18_combout ), + .datac(\z80_|execute_|ctl_ir_we~9_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~6 .lut_mask = 16'h04CC; +defparam \z80_|execute_|ctl_flags_alu~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~19 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~19_combout = (((!\z80_|execute_|ctl_ir_we~14_combout & !\z80_|execute_|ctl_mWrite~17_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|sequencer_|DFFE_T4_ff~q ) + + .dataa(\z80_|execute_|ctl_ir_we~14_combout ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|execute_|ctl_mWrite~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~19 .lut_mask = 16'h3F7F; +defparam \z80_|execute_|ctl_flags_alu~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N24 +cycloneive_lcell_comb \z80_|pla_decode_|Equal1~5 ( +// Equation(s): +// \z80_|pla_decode_|Equal1~5_combout = (!\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal1~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal1~5 .lut_mask = 16'h0F00; +defparam \z80_|pla_decode_|Equal1~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y19_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~0 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~0_combout = (\z80_|pla_decode_|Equal1~5_combout & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|pla_decode_|Equal13~1_combout & !\z80_|sequencer_|DFFE_M1_ff~q ))) + + .dataa(\z80_|pla_decode_|Equal1~5_combout ), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|pla_decode_|Equal13~1_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~0 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_alu_core_R~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|pla_decode_|Equal11~0_combout )) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2 .lut_mask = 16'h1010; +defparam \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~1 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~1_combout = (\z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ) # ((\z80_|execute_|ctl_alu_core_R~0_combout & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|execute_|ctl_alu_core_R~0_combout ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~1 .lut_mask = 16'hFAF2; +defparam \z80_|execute_|ctl_alu_core_R~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~7_combout = ((\z80_|execute_|ctl_alu_core_R~1_combout ) # ((\z80_|pla_decode_|Equal56~0_combout & \z80_|execute_|ixy_d~7_combout ))) # (!\z80_|execute_|ctl_flags_alu~19_combout ) + + .dataa(\z80_|execute_|ctl_flags_alu~19_combout ), + .datab(\z80_|pla_decode_|Equal56~0_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ctl_alu_core_R~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~7 .lut_mask = 16'hFFD5; +defparam \z80_|execute_|ctl_flags_alu~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N12 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~5 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~5_combout = ((!\z80_|pla_decode_|Equal39~0_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal40~1_combout ))) # (!\z80_|execute_|ixy_d~6_combout ) + + .dataa(\z80_|pla_decode_|Equal39~0_combout ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|pla_decode_|Equal40~1_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~5 .lut_mask = 16'h0F1F; +defparam \z80_|reg_control_|reg_sys_we_lo~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N28 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~8 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~8_combout = (\z80_|reg_control_|reg_sys_we_lo~5_combout & (((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|pla_decode_|Equal56~0_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|pla_decode_|Equal56~0_combout ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|reg_control_|reg_sys_we_lo~5_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~8 .lut_mask = 16'h7F00; +defparam \z80_|reg_control_|reg_sys_we_lo~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~8_combout = (((\z80_|execute_|ctl_flags_alu~7_combout ) # (!\z80_|reg_control_|reg_sys_we_lo~8_combout )) # (!\z80_|execute_|ctl_flags_alu~6_combout )) # (!\z80_|execute_|ctl_flags_alu~17_combout ) + + .dataa(\z80_|execute_|ctl_flags_alu~17_combout ), + .datab(\z80_|execute_|ctl_flags_alu~6_combout ), + .datac(\z80_|execute_|ctl_flags_alu~7_combout ), + .datad(\z80_|reg_control_|reg_sys_we_lo~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~8 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|ctl_flags_alu~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~15 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~15_combout = (((\z80_|execute_|ctl_flags_alu~8_combout ) # (!\z80_|execute_|ctl_flags_sz_we~2_combout )) # (!\z80_|execute_|ctl_flags_alu~14_combout )) # (!\z80_|execute_|ctl_flags_alu~11_combout ) + + .dataa(\z80_|execute_|ctl_flags_alu~11_combout ), + .datab(\z80_|execute_|ctl_flags_alu~14_combout ), + .datac(\z80_|execute_|ctl_flags_sz_we~2_combout ), + .datad(\z80_|execute_|ctl_flags_alu~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~15 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_flags_alu~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~7 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~7_combout = (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|execute_|ctl_state_alu~6_combout & ((!\z80_|pla_decode_|Equal52~1_combout )))) # (!\z80_|execute_|ctl_state_alu~2_combout & +// (((!\z80_|execute_|ctl_state_alu~4_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ctl_state_alu~6_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|pla_decode_|Equal52~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~7 .lut_mask = 16'h1537; +defparam \z80_|execute_|ctl_state_alu~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~12 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~12_combout = (\z80_|execute_|ctl_state_alu~7_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|pla_decode_|Equal52~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal52~1_combout ), + .datab(\z80_|execute_|ctl_state_alu~7_combout ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~12 .lut_mask = 16'hCC4C; +defparam \z80_|execute_|ctl_state_alu~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~9 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~9_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # ((\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~9 .lut_mask = 16'h00EF; +defparam \z80_|execute_|ctl_state_alu~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~10 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~10_combout = (\z80_|execute_|ctl_state_alu~9_combout & ((\z80_|execute_|ctl_state_alu~5_combout ) # ((\z80_|pla_decode_|Equal52~1_combout & \z80_|execute_|ctl_state_alu~3_combout )))) # +// (!\z80_|execute_|ctl_state_alu~9_combout & (((\z80_|pla_decode_|Equal52~1_combout & \z80_|execute_|ctl_state_alu~3_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~9_combout ), + .datab(\z80_|execute_|ctl_state_alu~5_combout ), + .datac(\z80_|pla_decode_|Equal52~1_combout ), + .datad(\z80_|execute_|ctl_state_alu~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~10 .lut_mask = 16'hF888; +defparam \z80_|execute_|ctl_state_alu~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~8 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~8_combout = (\z80_|pla_decode_|Equal52~1_combout & (((\z80_|nM1_int~2_combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) # (!\z80_|pla_decode_|Equal52~1_combout & (\z80_|execute_|ctl_state_alu~6_combout & +// ((\z80_|nM1_int~2_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) + + .dataa(\z80_|pla_decode_|Equal52~1_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~8 .lut_mask = 16'hFA32; +defparam \z80_|execute_|ctl_state_alu~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal64~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal64~0_combout = (!\z80_|ir_|opcode [5] & (((\z80_|execute_|ctl_state_alu~10_combout ) # (\z80_|execute_|ctl_state_alu~8_combout )) # (!\z80_|execute_|ctl_state_alu~12_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|execute_|ctl_state_alu~12_combout ), + .datac(\z80_|execute_|ctl_state_alu~10_combout ), + .datad(\z80_|execute_|ctl_state_alu~8_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal64~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal64~0 .lut_mask = 16'h5551; +defparam \z80_|pla_decode_|Equal64~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel[0]~3 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel[0]~3_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # (\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|pla_decode_|Equal64~0_combout ) + + .dataa(\z80_|pla_decode_|Equal64~0_combout ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel[0]~3 .lut_mask = 16'hFDFD; +defparam \z80_|execute_|ctl_pf_sel[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N22 +cycloneive_lcell_comb \z80_|pla_decode_|Equal62~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal62~2_combout = (\z80_|ir_|opcode [5] & (((\z80_|execute_|ctl_state_alu~10_combout ) # (\z80_|execute_|ctl_state_alu~8_combout )) # (!\z80_|execute_|ctl_state_alu~12_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|execute_|ctl_state_alu~12_combout ), + .datac(\z80_|execute_|ctl_state_alu~10_combout ), + .datad(\z80_|execute_|ctl_state_alu~8_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal62~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal62~2 .lut_mask = 16'hAAA2; +defparam \z80_|pla_decode_|Equal62~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~4_combout = (((\z80_|ir_|opcode [3] & \z80_|ir_|opcode [4])) # (!\z80_|nM1_int~2_combout )) # (!\z80_|pla_decode_|Equal62~2_combout ) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|pla_decode_|Equal62~2_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~4 .lut_mask = 16'h8FFF; +defparam \z80_|execute_|ctl_flags_pf_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~46 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~46_combout = (\z80_|execute_|ctl_alu_shift_oe~41_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|pla_decode_|Equal48~0_combout )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|pla_decode_|Equal48~0_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~41_combout ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~46 .lut_mask = 16'hB0F0; +defparam \z80_|execute_|ctl_alu_shift_oe~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~6_combout = (\z80_|pla_decode_|Equal69~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|pla_decode_|Equal69~0_combout ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~6 .lut_mask = 16'h080A; +defparam \z80_|execute_|ctl_flags_pf_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~7_combout = (\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # ((\z80_|execute_|ctl_flags_pf_we~6_combout ) # ((\z80_|execute_|ctl_mRead~34_combout & \z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~34_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .datad(\z80_|execute_|ctl_flags_pf_we~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~7 .lut_mask = 16'hFFF8; +defparam \z80_|execute_|ctl_flags_pf_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~11 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~11_combout = ((\z80_|execute_|ctl_state_alu~10_combout ) # ((\z80_|execute_|ctl_reg_gp_sel~7_combout ) # (\z80_|execute_|ctl_state_alu~8_combout ))) # (!\z80_|execute_|ctl_state_alu~7_combout ) + + .dataa(\z80_|execute_|ctl_state_alu~7_combout ), + .datab(\z80_|execute_|ctl_state_alu~10_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel~7_combout ), + .datad(\z80_|execute_|ctl_state_alu~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~11 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_state_alu~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y17_N26 +cycloneive_lcell_comb \z80_|pla_decode_|Equal62~3 ( +// Equation(s): +// \z80_|pla_decode_|Equal62~3_combout = (\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [4] & (\z80_|execute_|ctl_state_alu~11_combout & \z80_|ir_|opcode [3]))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|execute_|ctl_state_alu~11_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal62~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal62~3 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal62~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~5_combout = (\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_mWrite~17_combout ) # ((\z80_|pla_decode_|Equal11~0_combout ) # (\z80_|pla_decode_|Equal62~3_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~17_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|pla_decode_|Equal62~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~5 .lut_mask = 16'hCCC8; +defparam \z80_|execute_|ctl_flags_pf_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~3_combout = (\z80_|execute_|ctl_flags_pf_we~2_combout & (((!\z80_|execute_|ctl_ir_we~12_combout & !\z80_|execute_|ctl_ir_we~11_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_ir_we~12_combout ), + .datac(\z80_|execute_|ctl_flags_pf_we~2_combout ), + .datad(\z80_|execute_|ctl_ir_we~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~3 .lut_mask = 16'h5070; +defparam \z80_|execute_|ctl_flags_pf_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~8_combout = ((\z80_|execute_|ctl_flags_pf_we~7_combout ) # ((\z80_|execute_|ctl_flags_pf_we~5_combout ) # (!\z80_|execute_|ctl_flags_pf_we~3_combout ))) # (!\z80_|execute_|ctl_alu_shift_oe~46_combout ) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~46_combout ), + .datab(\z80_|execute_|ctl_flags_pf_we~7_combout ), + .datac(\z80_|execute_|ctl_flags_pf_we~5_combout ), + .datad(\z80_|execute_|ctl_flags_pf_we~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~8 .lut_mask = 16'hFDFF; +defparam \z80_|execute_|ctl_flags_pf_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~9 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~9_combout = (((\z80_|execute_|ctl_flags_pf_we~8_combout ) # (!\z80_|execute_|ctl_flags_pf_we~4_combout )) # (!\z80_|execute_|ctl_pf_sel[0]~3_combout )) # (!\z80_|execute_|ctl_flags_xy_we~13_combout ) + + .dataa(\z80_|execute_|ctl_flags_xy_we~13_combout ), + .datab(\z80_|execute_|ctl_pf_sel[0]~3_combout ), + .datac(\z80_|execute_|ctl_flags_pf_we~4_combout ), + .datad(\z80_|execute_|ctl_flags_pf_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~9 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_flags_pf_we~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y20_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~6_combout = (\z80_|execute_|ctl_ir_we~15_combout & (!\z80_|execute_|ctl_mWrite~5_combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|execute_|ctl_ir_we~9_combout )))) # (!\z80_|execute_|ctl_ir_we~15_combout & +// (((!\z80_|nM1_int~2_combout ) # (!\z80_|execute_|ctl_ir_we~9_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~15_combout ), + .datab(\z80_|execute_|ctl_mWrite~5_combout ), + .datac(\z80_|execute_|ctl_ir_we~9_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~6 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_alu_core_S~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y20_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~7_combout = (\z80_|execute_|ctl_alu_core_S~6_combout & (((!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~9_combout )) # (!\z80_|execute_|ctl_alu_oe~0_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~15_combout ), + .datab(\z80_|execute_|ctl_alu_oe~0_combout ), + .datac(\z80_|execute_|ctl_ir_we~9_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~7 .lut_mask = 16'h3700; +defparam \z80_|execute_|ctl_alu_core_S~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~1 ( +// Equation(s): +// \z80_|execute_|ctl_alu_res_oe~1_combout = (\z80_|execute_|ctl_alu_core_S~7_combout & (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|pla_decode_|Equal69~0_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|pla_decode_|Equal69~0_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_res_oe~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_res_oe~1 .lut_mask = 16'h5700; +defparam \z80_|execute_|ctl_alu_res_oe~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_alu_res_oe~0_combout = (\z80_|pla_decode_|Equal8~0_combout & ((\z80_|execute_|ctl_mRead~9_combout ) # ((\z80_|nM1_int~2_combout & \z80_|pla_decode_|Equal55~0_combout )))) # (!\z80_|pla_decode_|Equal8~0_combout & +// (((\z80_|nM1_int~2_combout & \z80_|pla_decode_|Equal55~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal8~0_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_res_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_res_oe~0 .lut_mask = 16'hF888; +defparam \z80_|execute_|ctl_alu_res_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y20_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~4_combout = (\z80_|execute_|ctl_ir_we~7_combout & (!\z80_|execute_|ctl_mWrite~5_combout & ((!\z80_|execute_|ctl_ir_we~10_combout ) # (!\z80_|nM1_int~2_combout )))) # (!\z80_|execute_|ctl_ir_we~7_combout & +// (((!\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~7_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|execute_|ctl_mWrite~5_combout ), + .datad(\z80_|execute_|ctl_ir_we~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~4 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_alu_core_S~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y20_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~5_combout = (\z80_|execute_|ctl_alu_core_S~4_combout & (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|execute_|ctl_alu_oe~0_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~7_combout ), + .datab(\z80_|execute_|ctl_ir_we~10_combout ), + .datac(\z80_|execute_|ctl_alu_oe~0_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~5 .lut_mask = 16'h1F00; +defparam \z80_|execute_|ctl_alu_core_S~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~2 ( +// Equation(s): +// \z80_|execute_|ctl_alu_res_oe~2_combout = (\z80_|execute_|ctl_alu_res_oe~1_combout & (\z80_|execute_|ctl_alu_core_S~5_combout & ((!\z80_|execute_|ctl_mWrite~4_combout ) # (!\z80_|execute_|ctl_alu_res_oe~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_res_oe~1_combout ), + .datab(\z80_|execute_|ctl_alu_res_oe~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_res_oe~2 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_alu_res_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y17_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout = (\z80_|pla_decode_|Equal2~0_combout & (\z80_|execute_|ctl_mWrite~4_combout & (!\z80_|ir_|opcode [0] & \z80_|execute_|ctl_state_alu~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal2~0_combout ), + .datab(\z80_|execute_|ctl_mWrite~4_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|execute_|ctl_state_alu~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N18 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~6 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~6_combout = (\z80_|reg_control_|reg_sys_we_lo~5_combout & (\z80_|execute_|ctl_flags_xy_we~20_combout & ((!\z80_|pla_decode_|Equal56~0_combout ) # (!\z80_|execute_|ctl_alu_op_low~22_combout )))) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~5_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datac(\z80_|pla_decode_|Equal56~0_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~20_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~6 .lut_mask = 16'h2A00; +defparam \z80_|reg_control_|reg_sys_we_lo~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~12 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~12_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|pla_decode_|Equal56~0_combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) # (!\z80_|execute_|ixy_d~7_combout & +// (((!\z80_|nM1_int~2_combout )) # (!\z80_|pla_decode_|Equal20~0_combout ))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|pla_decode_|Equal20~0_combout ), + .datac(\z80_|pla_decode_|Equal56~0_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~12 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_flags_xy_we~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~2_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout & (\z80_|reg_control_|reg_sys_we_lo~6_combout & (\z80_|execute_|ctl_flags_sz_we~1_combout & \z80_|execute_|ctl_flags_xy_we~12_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), + .datab(\z80_|reg_control_|reg_sys_we_lo~6_combout ), + .datac(\z80_|execute_|ctl_flags_sz_we~1_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~2 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_flags_cf_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~3 ( +// Equation(s): +// \z80_|execute_|ctl_alu_res_oe~3_combout = (\z80_|execute_|ctl_flags_alu~11_combout & (\z80_|execute_|ctl_alu_res_oe~2_combout & (\z80_|execute_|ctl_flags_cf_we~2_combout & \z80_|execute_|ctl_flags_pf_we~3_combout ))) + + .dataa(\z80_|execute_|ctl_flags_alu~11_combout ), + .datab(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datac(\z80_|execute_|ctl_flags_cf_we~2_combout ), + .datad(\z80_|execute_|ctl_flags_pf_we~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_res_oe~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_res_oe~3 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_res_oe~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_high ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_high~combout = ((\z80_|pla_decode_|Equal13~2_combout & (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_M3_ff~q ))) # (!\z80_|execute_|ctl_alu_res_oe~3_combout ) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|execute_|ctl_alu_res_oe~3_combout ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_high .lut_mask = 16'h8F0F; +defparam \z80_|execute_|ctl_alu_sel_op2_high .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_zero~4_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|ir_|opcode [0]))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|pla_decode_|Equal3~1_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_zero~4 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_alu_op1_sel_zero~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~12_combout = ((!\z80_|pla_decode_|Equal3~0_combout & ((\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal21~0_combout )))) # (!\z80_|execute_|ctl_state_alu~11_combout ) + + .dataa(\z80_|pla_decode_|Equal3~0_combout ), + .datab(\z80_|pla_decode_|Equal21~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|execute_|ctl_state_alu~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~12 .lut_mask = 16'h51FF; +defparam \z80_|execute_|ctl_alu_core_hf~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y16_N10 +cycloneive_lcell_comb \z80_|pla_decode_|Equal61~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal61~2_combout = (\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal6~0_combout & (!\z80_|ir_|opcode [1] & \z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal61~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal61~2 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal61~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~4_combout = (((!\z80_|execute_|ctl_eval_cond~0_combout & !\z80_|nM1_int~2_combout )) # (!\z80_|pla_decode_|Equal32~0_combout )) # (!\z80_|pla_decode_|Equal63~0_combout ) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|pla_decode_|Equal63~0_combout ), + .datad(\z80_|pla_decode_|Equal32~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~4 .lut_mask = 16'h1FFF; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~13 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~13_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~4_combout & (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|pla_decode_|Equal61~2_combout ))) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|pla_decode_|Equal61~2_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~13 .lut_mask = 16'h3070; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y20_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~14 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~14_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~4_combout & (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (\z80_|execute_|ctl_alu_core_hf~12_combout & \z80_|execute_|ctl_alu_sel_op2_neg~13_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .datab(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~12_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~14 .lut_mask = 16'h1000; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~18 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~18_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~14_combout & (((!\z80_|execute_|ctl_mWrite~17_combout ) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|execute_|ctl_mWrite~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~18 .lut_mask = 16'h2AAA; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~10_combout = (\z80_|execute_|ctl_flags_bus~9_combout & (\z80_|execute_|ctl_alu_shift_oe~20_combout & \z80_|execute_|ctl_bus_db_oe~3_combout )) + + .dataa(\z80_|execute_|ctl_flags_bus~9_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~20_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~3_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~10 .lut_mask = 16'h8080; +defparam \z80_|execute_|ctl_flags_bus~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~2_combout = (\z80_|pla_decode_|Equal44~0_combout ) # ((\z80_|pla_decode_|Equal52~0_combout & \z80_|pla_decode_|Equal33~0_combout )) + + .dataa(gnd), + .datab(\z80_|pla_decode_|Equal44~0_combout ), + .datac(\z80_|pla_decode_|Equal52~0_combout ), + .datad(\z80_|pla_decode_|Equal33~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~2 .lut_mask = 16'hFCCC; +defparam \z80_|execute_|ctl_flags_bus~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y17_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~0 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~0_combout = (\z80_|ir_|opcode [5]) # ((!\z80_|pla_decode_|Equal13~1_combout ) # (!\z80_|pla_decode_|Equal13~0_combout )) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal13~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~0 .lut_mask = 16'hBBFF; +defparam \z80_|execute_|ctl_flags_bus~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~3_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|execute_|ctl_flags_bus~2_combout ) # ((!\z80_|execute_|ctl_flags_bus~0_combout ) # (!\z80_|execute_|ctl_flags_bus~1_combout )))) + + .dataa(\z80_|execute_|ctl_flags_bus~2_combout ), + .datab(\z80_|execute_|ctl_flags_bus~1_combout ), + .datac(\z80_|execute_|ctl_flags_bus~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~3 .lut_mask = 16'hBF00; +defparam \z80_|execute_|ctl_flags_bus~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N10 cycloneive_lcell_comb \z80_|execute_|fMRead~26 ( // Equation(s): -// \z80_|execute_|fMRead~26_combout = (\z80_|execute_|ctl_mRead~15_combout ) # ((\z80_|pla_decode_|Equal44~0_combout & (\z80_|pla_decode_|Equal33~0_combout & !\z80_|decode_state_|use_ixiy~combout ))) +// \z80_|execute_|fMRead~26_combout = (\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_state_alu~2_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_state_alu~6_combout )))) # (!\z80_|execute_|ctl_ir_we~12_combout +// & (((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_state_alu~6_combout )))) - .dataa(\z80_|pla_decode_|Equal44~0_combout ), - .datab(\z80_|execute_|ctl_mRead~15_combout ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|decode_state_|use_ixiy~combout ), + .dataa(\z80_|execute_|ctl_ir_we~12_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), .cin(gnd), .combout(\z80_|execute_|fMRead~26_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~26 .lut_mask = 16'hCCEC; +defparam \z80_|execute_|fMRead~26 .lut_mask = 16'h0777; defparam \z80_|execute_|fMRead~26 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y19_N20 -cycloneive_lcell_comb \z80_|execute_|fMRead~25 ( +// Location: LCCOMB_X29_Y19_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus ( // Equation(s): -// \z80_|execute_|fMRead~25_combout = ((\z80_|sequencer_|DFFE_M2_ff~q & (!\z80_|execute_|ixy_d~4_combout & \z80_|execute_|ctl_mRead~14_combout ))) # (!\z80_|execute_|fMRead~24_combout ) +// \z80_|execute_|ctl_flags_bus~combout = ((\z80_|execute_|ctl_flags_bus~3_combout ) # ((\z80_|execute_|ctl_flags_hf2_we~combout ) # (!\z80_|execute_|fMRead~26_combout ))) # (!\z80_|execute_|ctl_flags_bus~10_combout ) - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|execute_|ixy_d~4_combout ), - .datac(\z80_|execute_|fMRead~24_combout ), - .datad(\z80_|execute_|ctl_mRead~14_combout ), + .dataa(\z80_|execute_|ctl_flags_bus~10_combout ), + .datab(\z80_|execute_|ctl_flags_bus~3_combout ), + .datac(\z80_|execute_|ctl_flags_hf2_we~combout ), + .datad(\z80_|execute_|fMRead~26_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~25_combout ), + .combout(\z80_|execute_|ctl_flags_bus~combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~25 .lut_mask = 16'h2F0F; -defparam \z80_|execute_|fMRead~25 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_flags_bus .lut_mask = 16'hFDFF; +defparam \z80_|execute_|ctl_flags_bus .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|fMRead~27 ( +// Location: LCCOMB_X26_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_lo~9 ( // Equation(s): -// \z80_|execute_|fMRead~27_combout = ((\z80_|execute_|fMRead~25_combout ) # ((\z80_|execute_|fMRead~26_combout & \z80_|execute_|ctl_ir_we~4_combout ))) # (!\z80_|execute_|fMRead~3_combout ) +// \z80_|execute_|ctl_reg_in_lo~9_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q ))) # (!\z80_|pla_decode_|Equal47~0_combout ) - .dataa(\z80_|execute_|fMRead~26_combout ), - .datab(\z80_|execute_|fMRead~3_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|execute_|fMRead~25_combout ), + .dataa(\z80_|pla_decode_|Equal47~0_combout ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|M5~q ), .cin(gnd), - .combout(\z80_|execute_|fMRead~27_combout ), + .combout(\z80_|execute_|ctl_reg_in_lo~9_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~27 .lut_mask = 16'hFFB3; -defparam \z80_|execute_|fMRead~27 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_reg_in_lo~9 .lut_mask = 16'hF5F7; +defparam \z80_|execute_|ctl_reg_in_lo~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y17_N18 -cycloneive_lcell_comb \z80_|execute_|fMRead~33 ( +// Location: LCCOMB_X30_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_oe~0 ( // Equation(s): -// \z80_|execute_|fMRead~33_combout = (\z80_|execute_|fMRead~32_combout ) # ((\z80_|execute_|fMRead~20_combout ) # ((\z80_|execute_|fMRead~23_combout ) # (\z80_|execute_|fMRead~27_combout ))) +// \z80_|execute_|ctl_alu_op1_oe~0_combout = ((\z80_|execute_|ctl_66_oe~2_combout ) # ((\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_alu_shift_oe~14_combout ))) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ) - .dataa(\z80_|execute_|fMRead~32_combout ), - .datab(\z80_|execute_|fMRead~20_combout ), - .datac(\z80_|execute_|fMRead~23_combout ), - .datad(\z80_|execute_|fMRead~27_combout ), + .dataa(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .datab(\z80_|execute_|ctl_66_oe~2_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~33_combout ), + .combout(\z80_|execute_|ctl_alu_op1_oe~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~33 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|fMRead~33 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_alu_op1_oe~0 .lut_mask = 16'hFDDD; +defparam \z80_|execute_|ctl_alu_op1_oe~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y17_N8 -cycloneive_lcell_comb \z80_|execute_|fMRead~35 ( +// Location: LCCOMB_X30_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_oe~1 ( // Equation(s): -// \z80_|execute_|fMRead~35_combout = (\z80_|execute_|fMRead~33_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~20_combout ) # ((\z80_|execute_|fMRead~34_combout & !\z80_|execute_|fMRead~0_combout ))) +// \z80_|execute_|ctl_alu_op1_oe~1_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ) # ((\z80_|execute_|ctl_alu_op1_oe~0_combout ) # ((\z80_|nM1_int~2_combout & \z80_|execute_|ctl_alu_oe~1_combout ))) - .dataa(\z80_|execute_|fMRead~34_combout ), - .datab(\z80_|execute_|fMRead~33_combout ), - .datac(\z80_|execute_|fMRead~0_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~20_combout ), + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_alu_oe~1_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), + .datad(\z80_|execute_|ctl_alu_op1_oe~0_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~35_combout ), + .combout(\z80_|execute_|ctl_alu_op1_oe~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~35 .lut_mask = 16'hFFCE; -defparam \z80_|execute_|fMRead~35 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_alu_op1_oe~1 .lut_mask = 16'hFFF8; +defparam \z80_|execute_|ctl_alu_op1_oe~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y13_N30 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_re ( +// Location: LCCOMB_X23_Y19_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~6 ( // Equation(s): -// \z80_|pin_control_|bus_db_pin_re~combout = (\z80_|pin_control_|bus_db_pin_re~2_combout ) # ((\z80_|execute_|fMRead~35_combout & \z80_|sequencer_|DFFE_T2_ff~q )) +// \z80_|execute_|ctl_alu_bs_oe~6_combout = ((!\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~15_combout ))) # (!\z80_|execute_|ctl_ir_we~4_combout ) + + .dataa(\z80_|execute_|ctl_ir_we~12_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ctl_ir_we~9_combout ), + .datad(\z80_|execute_|ctl_ir_we~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~6 .lut_mask = 16'h3337; +defparam \z80_|execute_|ctl_alu_bs_oe~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~12_combout = (\z80_|execute_|ctl_ir_we~11_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # ((!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M4_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|execute_|ctl_ir_we~11_combout ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~12 .lut_mask = 16'hCC40; +defparam \z80_|execute_|ctl_alu_bs_oe~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~8_combout = ((\z80_|execute_|ctl_alu_bs_oe~12_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~7_combout )) # (!\z80_|execute_|ctl_alu_bs_oe~6_combout ) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~6_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_bs_oe~12_combout ), + .datad(\z80_|execute_|ctl_alu_bs_oe~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~8 .lut_mask = 16'hF5FF; +defparam \z80_|execute_|ctl_alu_bs_oe~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~9_combout = (\z80_|execute_|ctl_ir_we~7_combout & (((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # (\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|execute_|ctl_ir_we~7_combout & (\z80_|execute_|ctl_ir_we~10_combout +// & ((\z80_|execute_|ctl_ir_we~4_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~10_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_ir_we~7_combout ), + .datad(\z80_|execute_|ctl_ir_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~9 .lut_mask = 16'hFAC0; +defparam \z80_|execute_|ctl_alu_bs_oe~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~combout = (\z80_|execute_|ctl_alu_bs_oe~8_combout ) # ((\z80_|execute_|ctl_alu_bs_oe~9_combout ) # ((\z80_|execute_|ctl_ir_we~4_combout & \z80_|pla_decode_|Equal41~2_combout ))) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~8_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(\z80_|execute_|ctl_alu_bs_oe~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe .lut_mask = 16'hFFEA; +defparam \z80_|execute_|ctl_alu_bs_oe .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_oe~0_combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # ((!\z80_|ir_|opcode [3] & \z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_oe~0 .lut_mask = 16'hB0A0; +defparam \z80_|execute_|ctl_alu_op2_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N12 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~0 ( +// Equation(s): +// \z80_|alu_|db_high[3]~0_combout = (\z80_|execute_|ctl_alu_op1_oe~1_combout ) # ((\z80_|execute_|ctl_alu_bs_oe~combout ) # ((\z80_|execute_|ctl_alu_op2_oe~0_combout ) # (!\z80_|execute_|ctl_alu_res_oe~3_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datab(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datac(\z80_|execute_|ctl_alu_res_oe~3_combout ), + .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~0 .lut_mask = 16'hFFEF; +defparam \z80_|alu_|db_high[3]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y19_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla83M1T3_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla83M1T3_2~combout = (\z80_|pla_decode_|Equal1~5_combout & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|pla_decode_|Equal13~1_combout & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal1~5_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|pla_decode_|Equal13~1_combout ), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla83M1T3_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla83M1T3_2 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla83M1T3_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~15 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~15_combout = (!\z80_|pla_decode_|Equal33~1_combout & (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal3~1_combout & \z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~1_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|pla_decode_|Equal3~1_combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~15 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_alu_shift_oe~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~38 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~38_combout = (!\z80_|execute_|ctl_alu_shift_oe~15_combout & (((!\z80_|execute_|ctl_state_alu~4_combout & !\z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|execute_|ctl_mRead~4_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|ctl_mRead~4_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~38 .lut_mask = 16'h0037; +defparam \z80_|execute_|ctl_alu_shift_oe~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y19_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~28 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~28_combout = (\z80_|pla_decode_|Equal1~5_combout & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|pla_decode_|Equal13~1_combout & \z80_|execute_|ctl_eval_cond~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal1~5_combout ), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|pla_decode_|Equal13~1_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~28 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_op_low~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y19_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~6_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla83M1T3_2~combout & (!\z80_|execute_|ctl_alu_op1_sel_bus~16_combout & (\z80_|execute_|ctl_alu_shift_oe~38_combout & !\z80_|execute_|ctl_alu_op_low~28_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla83M1T3_2~combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~38_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~28_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~6 .lut_mask = 16'h0010; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~37 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~37_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_alu_oe~1_combout ) # ((!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & \z80_|execute_|ctl_ir_we~11_combout )))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_ir_we~11_combout ), + .datad(\z80_|execute_|ctl_alu_oe~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~37 .lut_mask = 16'hAA20; +defparam \z80_|execute_|ctl_alu_shift_oe~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~39 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~39_combout = ((\z80_|execute_|ctl_alu_shift_oe~37_combout ) # ((\z80_|execute_|ctl_state_alu~6_combout & \z80_|execute_|ctl_alu_shift_oe~14_combout ))) # (!\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ) + + .dataa(\z80_|execute_|ctl_state_alu~6_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~37_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~39 .lut_mask = 16'hFBF3; +defparam \z80_|execute_|ctl_alu_shift_oe~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_daa ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_sel_daa~combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal63~0_combout & (!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4]))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_sel_daa .lut_mask = 16'h0008; +defparam \z80_|execute_|ctl_flags_cf2_sel_daa .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y17_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~7_combout = (\z80_|execute_|ctl_ir_we~8_combout & (!\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ctl_mWrite~5_combout ) # (!\z80_|execute_|ctl_ir_we~14_combout )))) # (!\z80_|execute_|ctl_ir_we~8_combout +// & (((!\z80_|execute_|ctl_mWrite~5_combout )) # (!\z80_|execute_|ctl_ir_we~14_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|execute_|ctl_ir_we~14_combout ), + .datac(\z80_|execute_|ctl_mWrite~5_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~7 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y17_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~8_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~7_combout & (\z80_|execute_|ctl_flags_alu~17_combout & ((!\z80_|pla_decode_|Equal20~0_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|pla_decode_|Equal20~0_combout ), + .datad(\z80_|execute_|ctl_flags_alu~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~8 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~30 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~30_combout = ((!\z80_|execute_|ixy_d~7_combout & ((\z80_|ir_|opcode [3]) # (!\z80_|execute_|ixy_d~6_combout )))) # (!\z80_|pla_decode_|Equal13~2_combout ) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~30 .lut_mask = 16'h7757; +defparam \z80_|execute_|ctl_alu_op_low~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y18_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~31 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~31_combout = (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (\z80_|execute_|ctl_alu_op1_sel_bus~8_combout & \z80_|execute_|ctl_alu_op_low~30_combout )) .dataa(gnd), - .datab(\z80_|execute_|fMRead~35_combout ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|pin_control_|bus_db_pin_re~2_combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~30_combout ), .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_re~combout ), + .combout(\z80_|execute_|ctl_alu_op_low~31_combout ), .cout()); // synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_re .lut_mask = 16'hFFC0; -defparam \z80_|pin_control_|bus_db_pin_re .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_alu_op_low~31 .lut_mask = 16'h3000; +defparam \z80_|execute_|ctl_alu_op_low~31 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X33_Y15_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a1 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[1]~34_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), +// Location: LCCOMB_X27_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~25 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~25_combout = (\z80_|pla_decode_|Equal13~2_combout & \z80_|ir_|opcode [3]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~25 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_mRead~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~40 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~40_combout = ((\z80_|execute_|ixy_d~9_combout & ((\z80_|execute_|ctl_mRead~25_combout ) # (\z80_|execute_|ctl_mRead~24_combout )))) # (!\z80_|execute_|ctl_flags_xy_we~21_combout ) + + .dataa(\z80_|execute_|ctl_mRead~25_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~21_combout ), + .datac(\z80_|execute_|ixy_d~9_combout ), + .datad(\z80_|execute_|ctl_mRead~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~40 .lut_mask = 16'hF3B3; +defparam \z80_|execute_|ctl_alu_shift_oe~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~42 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~42_combout = ((\z80_|execute_|ctl_alu_shift_oe~39_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~40_combout ) # (!\z80_|execute_|ctl_alu_op_low~31_combout ))) # (!\z80_|execute_|ctl_alu_shift_oe~46_combout ) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~46_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~39_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~31_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~40_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~42 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|ctl_alu_shift_oe~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout = (!\z80_|pla_decode_|Equal33~0_combout & (\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|pla_decode_|Equal44~0_combout & !\z80_|sequencer_|DFFE_M1_ff~q ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|pla_decode_|Equal44~0_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 .lut_mask = 16'h0040; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y18_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~4_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & (\z80_|execute_|ctl_state_alu~7_combout & (!\z80_|execute_|ctl_reg_gp_sel~7_combout & !\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ))) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), + .datab(\z80_|execute_|ctl_state_alu~7_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel~7_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~4 .lut_mask = 16'h0008; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~47 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~47_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|execute_|ctl_ir_we~7_combout & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_M1_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|execute_|ctl_ir_we~7_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~47 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_shift_oe~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~34 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~34_combout = (\z80_|execute_|ctl_ir_we~10_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ctl_alu_shift_oe~47_combout )))) # +// (!\z80_|execute_|ctl_ir_we~10_combout & (((\z80_|execute_|ctl_alu_shift_oe~47_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~10_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~47_combout ), + .datad(\z80_|execute_|ctl_ir_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~34 .lut_mask = 16'h50F8; +defparam \z80_|execute_|ctl_alu_shift_oe~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~35 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~35_combout = (!\z80_|execute_|ctl_alu_bs_oe~8_combout & ((\z80_|execute_|ctl_alu_shift_oe~34_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & \z80_|execute_|ctl_ir_we~10_combout )))) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~8_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~34_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_ir_we~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~35 .lut_mask = 16'h5444; +defparam \z80_|execute_|ctl_alu_shift_oe~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~36 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~36_combout = (((\z80_|execute_|ctl_alu_shift_oe~35_combout ) # (!\z80_|execute_|ctl_flags_bus~9_combout )) # (!\z80_|execute_|ctl_reg_use_sp~1_combout )) # (!\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ), + .datab(\z80_|execute_|ctl_reg_use_sp~1_combout ), + .datac(\z80_|execute_|ctl_flags_bus~9_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~35_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~36 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_alu_shift_oe~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~28 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~28_combout = (\z80_|execute_|ctl_state_alu~4_combout & ((\z80_|execute_|ctl_ir_we~7_combout ) # ((\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ctl_bus_db_oe~1_combout )))) # (!\z80_|execute_|ctl_state_alu~4_combout +// & (\z80_|execute_|ixy_d~7_combout & ((!\z80_|execute_|ctl_bus_db_oe~1_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|execute_|ctl_ir_we~7_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~28 .lut_mask = 16'hA0EC; +defparam \z80_|execute_|ctl_alu_shift_oe~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~44 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~44_combout = (!\z80_|execute_|ctl_alu_op_low~26_combout & (((!\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~26_combout ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|execute_|ctl_mRead~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~44 .lut_mask = 16'h1555; +defparam \z80_|execute_|ctl_alu_shift_oe~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~29 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~29_combout = (\z80_|execute_|ctl_alu_shift_oe~28_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~44_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~20_combout )) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~28_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_shift_oe~20_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~44_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~29 .lut_mask = 16'hAFFF; +defparam \z80_|execute_|ctl_alu_shift_oe~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~16 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~16_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|execute_|ixy_d~15_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|execute_|ixy_d~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~16 .lut_mask = 16'h0F00; +defparam \z80_|execute_|ctl_alu_shift_oe~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~27 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~27_combout = (!\z80_|execute_|ctl_alu_bs_oe~combout & ((\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ) # (\z80_|execute_|ctl_alu_shift_oe~16_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), + .datab(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~27 .lut_mask = 16'h3332; +defparam \z80_|execute_|ctl_alu_shift_oe~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~10_combout = ((\z80_|execute_|ctl_alu_bs_oe~9_combout ) # ((\z80_|execute_|ctl_alu_bs_oe~12_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~7_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~6_combout ) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~6_combout ), + .datab(\z80_|execute_|ctl_alu_bs_oe~9_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~12_combout ), + .datad(\z80_|execute_|ctl_alu_bs_oe~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~10 .lut_mask = 16'hFDFF; +defparam \z80_|execute_|ctl_alu_bs_oe~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~31 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~31_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~3_combout & (\z80_|execute_|ctl_sw_4u~1_combout & ((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout )))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datab(\z80_|pla_decode_|Equal47~0_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), + .datad(\z80_|execute_|ctl_sw_4u~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~31 .lut_mask = 16'h7000; +defparam \z80_|execute_|ctl_alu_shift_oe~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~30 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~30_combout = (\z80_|execute_|ctl_mWrite~5_combout & (!\z80_|execute_|ctl_mWrite~17_combout & ((!\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|ctl_state_alu~2_combout )))) # +// (!\z80_|execute_|ctl_mWrite~5_combout & (((!\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|ctl_state_alu~2_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~5_combout ), + .datab(\z80_|execute_|ctl_mWrite~17_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_mRead~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~30 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_alu_shift_oe~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~32 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~32_combout = (\z80_|execute_|ctl_alu_shift_oe~31_combout & (\z80_|execute_|ctl_alu_shift_oe~30_combout & ((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_mRead~9_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~9_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~31_combout ), + .datac(\z80_|pla_decode_|Equal47~0_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~30_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~32 .lut_mask = 16'h4C00; +defparam \z80_|execute_|ctl_alu_shift_oe~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~33 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~33_combout = (\z80_|execute_|ctl_alu_shift_oe~27_combout ) # ((!\z80_|execute_|ctl_alu_bs_oe~10_combout & ((\z80_|execute_|ctl_alu_shift_oe~29_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~32_combout )))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~29_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~27_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~10_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~32_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~33 .lut_mask = 16'hCECF; +defparam \z80_|execute_|ctl_alu_shift_oe~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y20_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~21 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~21_combout = (\z80_|execute_|ctl_ir_we~15_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # ((!\z80_|execute_|ctl_ir_we~4_combout & \z80_|execute_|ctl_state_alu~4_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~15_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|ctl_state_alu~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~21 .lut_mask = 16'hAA20; +defparam \z80_|execute_|ctl_alu_shift_oe~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y20_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~45 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~45_combout = (\z80_|execute_|ctl_alu_shift_oe~21_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|execute_|ctl_alu_shift_oe~21_combout ), + .datad(\z80_|execute_|ctl_ir_we~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~45 .lut_mask = 16'hD0F0; +defparam \z80_|execute_|ctl_alu_shift_oe~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y20_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~22 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~22_combout = (\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_alu_shift_oe~45_combout ) # (\z80_|execute_|ctl_state_alu~4_combout )))) # +// (!\z80_|execute_|ctl_ir_we~9_combout & (\z80_|execute_|ctl_alu_shift_oe~45_combout )) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~45_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ctl_ir_we~9_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~22 .lut_mask = 16'h3A2A; +defparam \z80_|execute_|ctl_alu_shift_oe~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y20_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~23 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~23_combout = (\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|execute_|ctl_alu_shift_oe~22_combout ) # (\z80_|execute_|ctl_eval_cond~0_combout )))) # +// (!\z80_|execute_|ctl_ir_we~9_combout & (\z80_|execute_|ctl_alu_shift_oe~22_combout )) + + .dataa(\z80_|execute_|ctl_ir_we~9_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~22_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~23 .lut_mask = 16'h44EC; +defparam \z80_|execute_|ctl_alu_shift_oe~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y20_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~24 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~24_combout = (\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_mWrite~9_combout ) # (\z80_|execute_|ctl_alu_shift_oe~23_combout )))) # +// (!\z80_|execute_|ctl_ir_we~12_combout & (((\z80_|execute_|ctl_alu_shift_oe~23_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~12_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ctl_mWrite~9_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~23_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~24 .lut_mask = 16'h7720; +defparam \z80_|execute_|ctl_alu_shift_oe~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y20_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~25 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~25_combout = (\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # (\z80_|execute_|ctl_alu_shift_oe~24_combout )))) # +// (!\z80_|execute_|ctl_ir_we~12_combout & (((\z80_|execute_|ctl_alu_shift_oe~24_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|execute_|ctl_mWrite~5_combout ), + .datac(\z80_|execute_|ctl_ir_we~12_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~25 .lut_mask = 16'h5F40; +defparam \z80_|execute_|ctl_alu_shift_oe~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~26 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~26_combout = (!\z80_|execute_|ctl_alu_bs_oe~12_combout & ((\z80_|execute_|ctl_alu_shift_oe~25_combout ) # ((\z80_|execute_|ctl_mWrite~9_combout & \z80_|execute_|ctl_ir_we~11_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~9_combout ), + .datab(\z80_|execute_|ctl_ir_we~11_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~25_combout ), + .datad(\z80_|execute_|ctl_alu_bs_oe~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~26 .lut_mask = 16'h00F8; +defparam \z80_|execute_|ctl_alu_shift_oe~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~43 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~43_combout = (\z80_|execute_|ctl_alu_shift_oe~42_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~36_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~33_combout ) # (\z80_|execute_|ctl_alu_shift_oe~26_combout ))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~42_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~36_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~33_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~26_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~43 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_alu_shift_oe~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_low ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_low~combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ixy_d~9_combout ) # ((\z80_|execute_|ixy_d~7_combout & !\z80_|ir_|opcode [3])))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ixy_d~9_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_low .lut_mask = 16'hC0E0; +defparam \z80_|execute_|ctl_alu_op1_sel_low .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_zero~5_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal63~0_combout & !\z80_|ir_|opcode [4]))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|pla_decode_|Equal63~0_combout ), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_zero~5 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_alu_op1_sel_zero~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y17_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_zero~combout = (\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # ((\z80_|execute_|ctl_66_oe~2_combout ) # ((\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # (\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .datab(\z80_|execute_|ctl_66_oe~2_combout ), + .datac(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_zero .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_alu_op1_sel_zero .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y17_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~13 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~13_combout = (!\z80_|execute_|ctl_alu_op_low~26_combout & (((!\z80_|pla_decode_|Equal41~2_combout & !\z80_|execute_|ctl_ir_we~11_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~26_combout ), + .datab(\z80_|pla_decode_|Equal41~2_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|execute_|ctl_ir_we~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~13 .lut_mask = 16'h0515; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y19_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~17 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~17_combout = (\z80_|execute_|ctl_flags_xy_we~14_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|pla_decode_|Equal48~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal48~0_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~14_combout ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~17 .lut_mask = 16'hCC4C; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y19_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~14 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~14_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~13_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~17_combout & (\z80_|execute_|ctl_bus_db_oe~0_combout & \z80_|execute_|ctl_alu_op1_sel_bus~8_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~13_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~17_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~0_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~14 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y20_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~3 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~3_combout = (\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ctl_ir_we~15_combout ) # (!\z80_|execute_|ctl_state_alu~2_combout )))) # (!\z80_|execute_|ctl_ir_we~9_combout +// & (((!\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_state_alu~2_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~9_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_ir_we~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~3 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_alu_core_R~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y20_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~4_combout = (\z80_|execute_|ctl_alu_core_R~3_combout & (((!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~9_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~15_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_ir_we~9_combout ), + .datad(\z80_|execute_|ctl_alu_core_R~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~4 .lut_mask = 16'h3700; +defparam \z80_|execute_|ctl_alu_core_R~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|execute_|ctl_ir_we~11_combout & \z80_|sequencer_|DFFE_T4_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|execute_|ctl_ir_we~11_combout ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 .lut_mask = 16'h4400; +defparam \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y20_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~9_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|execute_|ctl_ir_we~10_combout & ((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|ctl_ir_we~7_combout )))) # +// (!\z80_|execute_|ctl_eval_cond~0_combout & (((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|ctl_ir_we~7_combout )))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|ctl_ir_we~10_combout ), + .datac(\z80_|execute_|ctl_ir_we~7_combout ), + .datad(\z80_|execute_|ctl_state_alu~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~9 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~10_combout = (!\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout & (\z80_|execute_|ctl_flags_sz_we~0_combout & (\z80_|execute_|ctl_flags_alu~18_combout & \z80_|execute_|ctl_alu_op1_sel_bus~9_combout +// ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .datac(\z80_|execute_|ctl_flags_alu~18_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~10 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~11_combout = (((\z80_|execute_|ctl_alu_oe~1_combout & \z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~10_combout )) # (!\z80_|execute_|ctl_alu_core_R~4_combout ) + + .dataa(\z80_|execute_|ctl_alu_oe~1_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_alu_core_R~4_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~11 .lut_mask = 16'h8FFF; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~12_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ) # ((\z80_|execute_|ixy_d~15_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T4_ff~q )))) + + .dataa(\z80_|execute_|ixy_d~15_combout ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~12 .lut_mask = 16'hFFA8; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~15 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~15_combout = ((\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~32_combout ) # (!\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ))) # (!\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~32_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~15 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N6 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & ((\z80_|alu_|db_low[3]~17_combout ) # ((!\z80_|alu_|db_high[3]~0_combout & !\z80_|execute_|ctl_alu_shift_oe~43_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datab(\z80_|alu_|db_high[3]~0_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datad(\z80_|alu_|db_low[3]~17_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9 .lut_mask = 16'hAA02; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N4 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~6 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~6_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & ((\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ) # ((\z80_|alu_|db_high[3]~7_combout & \z80_|execute_|ctl_alu_op1_sel_low~combout )))) + + .dataa(\z80_|alu_|db_high[3]~7_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .datad(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~6 .lut_mask = 16'h0F08; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N30 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|ena ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|ena~combout = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~combout ) # (\z80_|execute_|ctl_alu_op1_sel_low~combout )) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|ena .lut_mask = 16'hFFFA; +defparam \z80_|alu_|b2v_op1_latch_mux_low|ena .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y17_N5 +dffeas \z80_|alu_|op1_low[3] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), .devclrn(devclrn), .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), - .portbdataout()); + .q(\z80_|alu_|op1_low [3]), + .prn(vcc)); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; +defparam \z80_|alu_|op1_low[3] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_low[3] .power_up = "low"; // synopsys translate_on -// Location: M9K_X33_Y18_N0 +// Location: LCCOMB_X31_Y17_N4 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~15 ( +// Equation(s): +// \z80_|alu_|db_low[3]~15_combout = (\z80_|execute_|ctl_alu_op2_oe~0_combout & (\z80_|alu_|op2_low [3] & ((\z80_|alu_|op1_low [3]) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout & (((\z80_|alu_|op1_low [3])) +// # (!\z80_|execute_|ctl_alu_op1_oe~1_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datac(\z80_|alu_|op2_low [3]), + .datad(\z80_|alu_|op1_low [3]), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~15 .lut_mask = 16'hF531; +defparam \z80_|alu_|db_low[3]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N24 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~16 ( +// Equation(s): +// \z80_|alu_|db_low[3]~16_combout = (\z80_|alu_|db_low[3]~15_combout & (((\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout & !\z80_|bus_control_|db[5]~15_combout )) # (!\z80_|execute_|ctl_alu_bs_oe~combout ))) + + .dataa(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), + .datab(\z80_|bus_control_|db[5]~15_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datad(\z80_|alu_|db_low[3]~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~16 .lut_mask = 16'h2F00; +defparam \z80_|alu_|db_low[3]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~33 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~33_combout = (\z80_|execute_|ctl_state_alu~3_combout & (((\z80_|execute_|ctl_alu_op_low~24_combout ) # (\z80_|pla_decode_|Equal56~0_combout )))) # (!\z80_|execute_|ctl_state_alu~3_combout & +// (\z80_|execute_|ctl_mWrite~5_combout & ((\z80_|execute_|ctl_alu_op_low~24_combout ) # (\z80_|pla_decode_|Equal56~0_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~3_combout ), + .datab(\z80_|execute_|ctl_mWrite~5_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~24_combout ), + .datad(\z80_|pla_decode_|Equal56~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~33 .lut_mask = 16'hEEE0; +defparam \z80_|execute_|ctl_alu_op_low~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y20_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~34 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~34_combout = (\z80_|execute_|ctl_alu_op_low~33_combout ) # (((\z80_|execute_|ctl_alu_op_low~28_combout ) # (!\z80_|execute_|ctl_alu_op2_sel_bus~4_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~38_combout )) + + .dataa(\z80_|execute_|ctl_alu_op_low~33_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~38_combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~28_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~34 .lut_mask = 16'hFFBF; +defparam \z80_|execute_|ctl_alu_op_low~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~48 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~48_combout = (((!\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|execute_|ctl_alu_op_low~25_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|execute_|ctl_alu_op_low~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~48 .lut_mask = 16'h73FF; +defparam \z80_|execute_|ctl_alu_op_low~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~35 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~35_combout = (\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # (((\z80_|execute_|ctl_alu_op_low~22_combout & \z80_|execute_|ctl_mWrite~17_combout )) # (!\z80_|execute_|ctl_alu_op_low~45_combout )) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~45_combout ), + .datad(\z80_|execute_|ctl_mWrite~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~35 .lut_mask = 16'hEFAF; +defparam \z80_|execute_|ctl_alu_op_low~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~36 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~36_combout = (((\z80_|execute_|ctl_alu_op_low~35_combout ) # (!\z80_|execute_|ctl_alu_core_R~4_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~10_combout )) # (!\z80_|execute_|ctl_alu_op_low~23_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~23_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), + .datac(\z80_|execute_|ctl_alu_core_R~4_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~35_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~36 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_alu_op_low~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y20_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~37 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~37_combout = (\z80_|execute_|ctl_alu_op_low~34_combout ) # (((\z80_|execute_|ctl_alu_op_low~36_combout ) # (!\z80_|execute_|ctl_alu_op_low~48_combout )) # (!\z80_|execute_|ctl_alu_op_low~31_combout )) + + .dataa(\z80_|execute_|ctl_alu_op_low~34_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~31_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~48_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~36_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~37 .lut_mask = 16'hFFBF; +defparam \z80_|execute_|ctl_alu_op_low~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|pla_decode_|Equal21~1_combout & !\z80_|sequencer_|DFFE_M1_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 .lut_mask = 16'h0088; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y20_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~38 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~38_combout = (\z80_|execute_|ixy_d~5_combout & (((\z80_|execute_|ctl_mRead~34_combout ) # (\z80_|pla_decode_|Equal39~0_combout )))) # (!\z80_|execute_|ixy_d~5_combout & (\z80_|execute_|ctl_eval_cond~0_combout & +// (\z80_|execute_|ctl_mRead~34_combout ))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|pla_decode_|Equal39~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~38 .lut_mask = 16'hECE0; +defparam \z80_|execute_|ctl_alu_op_low~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~39 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~39_combout = (\z80_|execute_|ixy_d~9_combout & ((\z80_|pla_decode_|Equal39~0_combout ) # ((\z80_|pla_decode_|Equal40~1_combout )))) # (!\z80_|execute_|ixy_d~9_combout & (((\z80_|execute_|ixy_d~5_combout & +// \z80_|pla_decode_|Equal40~1_combout )))) + + .dataa(\z80_|pla_decode_|Equal39~0_combout ), + .datab(\z80_|execute_|ixy_d~9_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|pla_decode_|Equal40~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~39 .lut_mask = 16'hFC88; +defparam \z80_|execute_|ctl_alu_op_low~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y20_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~40 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~40_combout = (\z80_|execute_|ctl_alu_op_low~37_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ) # ((\z80_|execute_|ctl_alu_op_low~38_combout ) # (\z80_|execute_|ctl_alu_op_low~39_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~37_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), + .datac(\z80_|execute_|ctl_alu_op_low~38_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~39_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~40 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_alu_op_low~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~41 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~41_combout = (\z80_|execute_|ctl_alu_op_low~40_combout ) # ((\z80_|pla_decode_|Equal21~1_combout & ((\z80_|execute_|ixy_d~5_combout ) # (\z80_|execute_|ixy_d~9_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|execute_|ixy_d~9_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~40_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~41 .lut_mask = 16'hFFC8; +defparam \z80_|execute_|ctl_alu_op_low~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~combout = (\z80_|execute_|ctl_alu_op_low~41_combout ) # ((\z80_|execute_|ixy_d~15_combout & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|execute_|ctl_alu_op_low~41_combout ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|execute_|ixy_d~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low .lut_mask = 16'hFECC; +defparam \z80_|execute_|ctl_alu_op_low .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y16_N25 +dffeas \z80_|alu_|result_lo[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_alu_op_low~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|result_lo [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|result_lo[3] .is_wysiwyg = "true"; +defparam \z80_|alu_|result_lo[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~5_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout & (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal20~0_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .datac(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~5 .lut_mask = 16'h0103; +defparam \z80_|execute_|ctl_alu_oe~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~6_combout = (\z80_|execute_|ctl_alu_oe~5_combout & (((!\z80_|execute_|ctl_mRead~24_combout & !\z80_|execute_|ctl_mRead~25_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~24_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|execute_|ctl_alu_oe~5_combout ), + .datad(\z80_|execute_|ctl_mRead~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~6 .lut_mask = 16'h3070; +defparam \z80_|execute_|ctl_alu_oe~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~9_combout = (\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_mWrite~17_combout ) # ((\z80_|execute_|ctl_alu_oe~1_combout ) # (\z80_|pla_decode_|Equal69~0_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~17_combout ), + .datab(\z80_|execute_|ctl_alu_oe~1_combout ), + .datac(\z80_|pla_decode_|Equal69~0_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~9 .lut_mask = 16'hFE00; +defparam \z80_|execute_|ctl_alu_oe~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~12_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~12_combout & !\z80_|execute_|ctl_ir_we~11_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~12_combout ), + .datab(\z80_|execute_|ctl_ir_we~11_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~12 .lut_mask = 16'hFFF1; +defparam \z80_|execute_|ctl_alu_core_S~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~10_combout = ((\z80_|execute_|ctl_alu_oe~9_combout ) # ((!\z80_|execute_|ctl_alu_core_S~12_combout ) # (!\z80_|execute_|ctl_alu_oe~4_combout ))) # (!\z80_|execute_|ctl_alu_oe~6_combout ) + + .dataa(\z80_|execute_|ctl_alu_oe~6_combout ), + .datab(\z80_|execute_|ctl_alu_oe~9_combout ), + .datac(\z80_|execute_|ctl_alu_oe~4_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~10 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_alu_oe~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~2 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~2_combout = ((!\z80_|execute_|ctl_alu_op_low~25_combout & (!\z80_|execute_|ctl_alu_op_low~24_combout & !\z80_|pla_decode_|Equal56~0_combout ))) # (!\z80_|execute_|ixy_d~7_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~25_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~24_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|pla_decode_|Equal56~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~2 .lut_mask = 16'h0F1F; +defparam \z80_|execute_|ctl_alu_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout = (!\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|nM1_int~2_combout & \z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~1_combout ), + .datab(\z80_|pla_decode_|Equal3~1_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~15 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~15_combout = ((!\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_ir_we~8_combout & !\z80_|execute_|ctl_ir_we~10_combout ))) # (!\z80_|nM1_int~2_combout ) + + .dataa(\z80_|execute_|ctl_ir_we~9_combout ), + .datab(\z80_|execute_|ctl_ir_we~8_combout ), + .datac(\z80_|execute_|ctl_ir_we~10_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~15 .lut_mask = 16'h01FF; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~8_combout = (!\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~15_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout & \z80_|execute_|ctl_flags_sz_we~1_combout ))) + + .dataa(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~15_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), + .datad(\z80_|execute_|ctl_flags_sz_we~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~8 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_reg_in_hi~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N6 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~7 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~7_combout = (\z80_|reg_control_|reg_sys_we_lo~6_combout & ((!\z80_|execute_|ixy_d~15_combout ) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|reg_control_|reg_sys_we_lo~6_combout ), + .datac(\z80_|execute_|ixy_d~15_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~7 .lut_mask = 16'h4C4C; +defparam \z80_|reg_control_|reg_sys_we_lo~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~7_combout = (\z80_|execute_|ctl_reg_in_hi~8_combout & (\z80_|reg_control_|reg_sys_we_lo~7_combout & ((!\z80_|pla_decode_|Equal13~2_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~8_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|reg_control_|reg_sys_we_lo~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~7 .lut_mask = 16'h4C00; +defparam \z80_|execute_|ctl_alu_oe~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y17_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~11 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~11_combout = (\z80_|execute_|ctl_flags_use_cf2~13_combout & (((!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~7_combout )) # (!\z80_|execute_|ctl_mWrite~5_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~5_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|execute_|ctl_ir_we~7_combout ), + .datad(\z80_|execute_|ctl_flags_use_cf2~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~11 .lut_mask = 16'h5700; +defparam \z80_|execute_|ctl_mWrite~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_we~5_combout = (\z80_|execute_|ctl_bus_inc_oe~28_combout & (\z80_|execute_|ctl_mWrite~11_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|execute_|ctl_mRead~24_combout )))) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~28_combout ), + .datab(\z80_|execute_|ctl_mRead~24_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|execute_|ctl_mWrite~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_we~5 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_bus_db_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~8_combout = (\z80_|execute_|ctl_reg_in_lo~9_combout & (\z80_|execute_|ctl_alu_oe~2_combout & (\z80_|execute_|ctl_alu_oe~7_combout & \z80_|execute_|ctl_bus_db_we~5_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .datab(\z80_|execute_|ctl_alu_oe~2_combout ), + .datac(\z80_|execute_|ctl_alu_oe~7_combout ), + .datad(\z80_|execute_|ctl_bus_db_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~8 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_oe~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~16 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~16_combout = (\z80_|execute_|ctl_flags_alu~10_combout & (!\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout & (\z80_|execute_|ctl_flags_xy_we~10_combout & !\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ))) + + .dataa(\z80_|execute_|ctl_flags_alu~10_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~10_combout ), + .datad(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~16 .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_flags_alu~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~11_combout = (\z80_|execute_|ctl_alu_oe~10_combout ) # (((\z80_|execute_|ctl_66_oe~2_combout ) # (!\z80_|execute_|ctl_flags_alu~16_combout )) # (!\z80_|execute_|ctl_alu_oe~8_combout )) + + .dataa(\z80_|execute_|ctl_alu_oe~10_combout ), + .datab(\z80_|execute_|ctl_alu_oe~8_combout ), + .datac(\z80_|execute_|ctl_flags_alu~16_combout ), + .datad(\z80_|execute_|ctl_66_oe~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~11 .lut_mask = 16'hFFBF; +defparam \z80_|execute_|ctl_alu_oe~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y19_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~48 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~48_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|pla_decode_|Equal21~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal21~1_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~48 .lut_mask = 16'hD0F0; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_hi~8_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & ((\z80_|execute_|ctl_ir_we~12_combout ) # (!\z80_|execute_|nextM~2_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|execute_|nextM~2_combout ), + .datac(\z80_|execute_|ctl_ir_we~12_combout ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_hi~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_hi~8 .lut_mask = 16'hA200; +defparam \z80_|execute_|ctl_reg_out_hi~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_hi~5_combout = (\z80_|execute_|ctl_reg_out_lo~2_combout & (\z80_|execute_|rsel3~combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|execute_|ctl_mRead~3_combout )))) # (!\z80_|execute_|ctl_reg_out_lo~2_combout & +// (((!\z80_|execute_|ixy_d~7_combout )) # (!\z80_|execute_|ctl_mRead~3_combout ))) + + .dataa(\z80_|execute_|ctl_reg_out_lo~2_combout ), + .datab(\z80_|execute_|ctl_mRead~3_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|rsel3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_hi~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_hi~5 .lut_mask = 16'h3F15; +defparam \z80_|execute_|ctl_reg_out_hi~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~2 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~2_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|execute_|ctl_mWrite~8_combout & ((!\z80_|execute_|ctl_mRead~7_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|execute_|ctl_eval_cond~0_combout & +// (((!\z80_|execute_|ctl_mRead~7_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|ctl_mWrite~8_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|execute_|ctl_mRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~2 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_sw_2u~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~0 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~0_combout = (\z80_|execute_|ctl_state_alu~3_combout & (!\z80_|execute_|ctl_mWrite~6_combout & ((!\z80_|pla_decode_|Equal9~1_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|execute_|ctl_state_alu~3_combout & +// (((!\z80_|pla_decode_|Equal9~1_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~3_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|pla_decode_|Equal9~1_combout ), + .datad(\z80_|execute_|ctl_mWrite~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~0 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_sw_2u~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~3 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~3_combout = (\z80_|execute_|ctl_sw_2u~2_combout & (\z80_|execute_|ctl_sw_2u~0_combout & ((!\z80_|execute_|ctl_mRead~6_combout ) # (!\z80_|execute_|ctl_alu_oe~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_oe~0_combout ), + .datab(\z80_|execute_|ctl_mRead~6_combout ), + .datac(\z80_|execute_|ctl_sw_2u~2_combout ), + .datad(\z80_|execute_|ctl_sw_2u~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~3 .lut_mask = 16'h7000; +defparam \z80_|execute_|ctl_sw_2u~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y15_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~47 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~47_combout = (\z80_|execute_|ctl_sw_2u~3_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|execute_|ctl_mRead~8_combout )) # (!\z80_|sequencer_|M5~q ))) + + .dataa(\z80_|sequencer_|M5~q ), + .datab(\z80_|execute_|ctl_sw_2u~3_combout ), + .datac(\z80_|execute_|ctl_mRead~8_combout ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~47 .lut_mask = 16'hCC4C; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y18_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~33 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~33_combout = (\z80_|execute_|ctl_state_alu~3_combout & (!\z80_|pla_decode_|Equal47~0_combout & ((!\z80_|execute_|ctl_ir_we~4_combout ) # (!\z80_|pla_decode_|Equal34~0_combout )))) # (!\z80_|execute_|ctl_state_alu~3_combout & +// (((!\z80_|execute_|ctl_ir_we~4_combout )) # (!\z80_|pla_decode_|Equal34~0_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~3_combout ), + .datab(\z80_|pla_decode_|Equal34~0_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~33 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_inc_cy~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~37 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~37_combout = (\z80_|execute_|ctl_inc_cy~33_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|sequencer_|DFFE_M4_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|pla_decode_|Equal19~0_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|execute_|ctl_inc_cy~33_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~37 .lut_mask = 16'hF700; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~6 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~6_combout = (\z80_|execute_|ctl_reg_gp_sel~7_combout & (\z80_|ir_|opcode [0] $ ((!\z80_|execute_|comb~0_combout )))) # (!\z80_|execute_|ctl_reg_gp_sel~7_combout & (!\z80_|execute_|ctl_sw_2u~5_combout & (\z80_|ir_|opcode [0] $ +// (!\z80_|execute_|comb~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel~7_combout ), + .datab(\z80_|ir_|opcode [0]), + .datac(\z80_|execute_|comb~0_combout ), + .datad(\z80_|execute_|ctl_sw_2u~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~6 .lut_mask = 16'h82C3; +defparam \z80_|execute_|ctl_sw_2u~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_hi~6_combout = (\z80_|execute_|ctl_reg_out_hi~5_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~37_combout & !\z80_|execute_|ctl_sw_2u~6_combout ))) + + .dataa(\z80_|execute_|ctl_reg_out_hi~5_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~37_combout ), + .datad(\z80_|execute_|ctl_sw_2u~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_hi~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_hi~6 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_out_hi~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_hi~7_combout = (((\z80_|execute_|ctl_reg_out_hi~8_combout ) # (!\z80_|execute_|ctl_reg_out_hi~6_combout )) # (!\z80_|execute_|ctl_reg_out_hi~4_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), + .datab(\z80_|execute_|ctl_reg_out_hi~4_combout ), + .datac(\z80_|execute_|ctl_reg_out_hi~8_combout ), + .datad(\z80_|execute_|ctl_reg_out_hi~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_hi~7 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|ctl_reg_out_hi~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~2 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~2_combout = (\z80_|pla_decode_|Equal3~0_combout & (\z80_|pla_decode_|Equal1~7_combout & (\z80_|pla_decode_|Equal2~0_combout & !\z80_|ir_|opcode [5]))) + + .dataa(\z80_|pla_decode_|Equal3~0_combout ), + .datab(\z80_|pla_decode_|Equal1~7_combout ), + .datac(\z80_|pla_decode_|Equal2~0_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~2 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_mRead~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~6 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~6_combout = (\z80_|pla_decode_|Equal9~1_combout & (!\z80_|execute_|ixy_d~6_combout & ((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) # (!\z80_|pla_decode_|Equal9~1_combout & +// (((!\z80_|execute_|ctl_mRead~9_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|pla_decode_|Equal47~0_combout ), + .datac(\z80_|execute_|ctl_mRead~9_combout ), + .datad(\z80_|execute_|ixy_d~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~6 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_sw_2d~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~7 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~7_combout = (\z80_|execute_|ctl_sw_2d~6_combout & (((!\z80_|execute_|ctl_mRead~2_combout & !\z80_|pla_decode_|Equal6~1_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_mRead~2_combout ), + .datac(\z80_|pla_decode_|Equal6~1_combout ), + .datad(\z80_|execute_|ctl_sw_2d~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~7 .lut_mask = 16'h5700; +defparam \z80_|execute_|ctl_sw_2d~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout = (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal1~4_combout & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|ir_|opcode [0]))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|pla_decode_|Equal1~4_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~8 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~8_combout = (\z80_|execute_|ctl_flags_sz_we~0_combout & (\z80_|execute_|ctl_sw_2d~7_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout & \z80_|execute_|ctl_alu_shift_oe~44_combout ))) + + .dataa(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .datab(\z80_|execute_|ctl_sw_2d~7_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~44_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~8 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_sw_2d~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~7 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~7_combout = (\z80_|execute_|ctl_flags_alu~19_combout & (((!\z80_|execute_|ctl_mRead~25_combout & !\z80_|execute_|ctl_mRead~24_combout )) # (!\z80_|execute_|ixy_d~9_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~25_combout ), + .datab(\z80_|execute_|ctl_flags_alu~19_combout ), + .datac(\z80_|execute_|ixy_d~9_combout ), + .datad(\z80_|execute_|ctl_mRead~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~7 .lut_mask = 16'h0C4C; +defparam \z80_|execute_|ctl_bus_db_oe~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~5 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~5_combout = (\z80_|execute_|ctl_bus_db_oe~7_combout & (((!\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_bus_db_oe~1_combout )) # (!\z80_|execute_|ixy_d~7_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(\z80_|execute_|ctl_bus_db_oe~7_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~5 .lut_mask = 16'h4C0C; +defparam \z80_|execute_|ctl_sw_2d~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~19 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~19_combout = (\z80_|execute_|ctl_mRead~15_combout ) # ((\z80_|pla_decode_|Equal9~1_combout ) # ((!\z80_|pla_decode_|Equal12~1_combout & \z80_|pla_decode_|Equal25~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal12~1_combout ), + .datab(\z80_|execute_|ctl_mRead~15_combout ), + .datac(\z80_|pla_decode_|Equal9~1_combout ), + .datad(\z80_|pla_decode_|Equal25~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~19 .lut_mask = 16'hFDFC; +defparam \z80_|execute_|ctl_mRead~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~18 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~18_combout = (\z80_|execute_|ctl_mRead~8_combout ) # ((\z80_|execute_|ctl_mRead~13_combout ) # ((\z80_|execute_|ctl_mRead~7_combout ) # (\z80_|execute_|ctl_mRead~6_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~8_combout ), + .datab(\z80_|execute_|ctl_mRead~13_combout ), + .datac(\z80_|execute_|ctl_mRead~7_combout ), + .datad(\z80_|execute_|ctl_mRead~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~18 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_mRead~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N26 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~2 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~2_combout = (\z80_|pla_decode_|Equal35~0_combout ) # ((\z80_|pla_decode_|Equal34~0_combout ) # ((\z80_|pla_decode_|Equal37~0_combout ) # (\z80_|pla_decode_|Equal38~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal35~0_combout ), + .datab(\z80_|pla_decode_|Equal34~0_combout ), + .datac(\z80_|pla_decode_|Equal37~0_combout ), + .datad(\z80_|pla_decode_|Equal38~2_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~2 .lut_mask = 16'hFFFE; +defparam \z80_|reg_control_|reg_sys_we_lo~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal24~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal24~1_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal1~7_combout & \z80_|pla_decode_|Equal9~0_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal2~0_combout ), + .datac(\z80_|pla_decode_|Equal1~7_combout ), + .datad(\z80_|pla_decode_|Equal9~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal24~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal24~1 .lut_mask = 16'h4000; +defparam \z80_|pla_decode_|Equal24~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N12 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~3 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~3_combout = (\z80_|pla_decode_|Equal29~0_combout ) # ((\z80_|pla_decode_|Equal19~0_combout ) # ((\z80_|reg_control_|reg_sys_we_lo~2_combout ) # (\z80_|pla_decode_|Equal24~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal29~0_combout ), + .datab(\z80_|pla_decode_|Equal19~0_combout ), + .datac(\z80_|reg_control_|reg_sys_we_lo~2_combout ), + .datad(\z80_|pla_decode_|Equal24~1_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~3 .lut_mask = 16'hFFFE; +defparam \z80_|reg_control_|reg_sys_we_lo~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N2 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~4 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~4_combout = (\z80_|reg_control_|reg_sys_we_lo~3_combout & (!\z80_|execute_|ctl_state_alu~2_combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) # +// (!\z80_|reg_control_|reg_sys_we_lo~3_combout & (((!\z80_|execute_|ctl_state_alu~4_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~3_combout ), + .datab(\z80_|pla_decode_|Equal47~0_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~4 .lut_mask = 16'h135F; +defparam \z80_|reg_control_|reg_sys_we_lo~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~20 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~20_combout = (\z80_|reg_control_|reg_sys_we_lo~4_combout & (((!\z80_|execute_|ctl_mRead~19_combout & !\z80_|execute_|ctl_mRead~18_combout )) # (!\z80_|execute_|ctl_state_alu~2_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~19_combout ), + .datab(\z80_|execute_|ctl_mRead~18_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|reg_control_|reg_sys_we_lo~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~20 .lut_mask = 16'h1F00; +defparam \z80_|execute_|ctl_mRead~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~5_combout = ((!\z80_|execute_|ctl_mRead~13_combout & (!\z80_|execute_|ctl_mRead~15_combout & !\z80_|execute_|ctl_mRead~16_combout ))) # (!\z80_|execute_|ixy_d~6_combout ) + + .dataa(\z80_|execute_|ctl_mRead~13_combout ), + .datab(\z80_|execute_|ctl_mRead~15_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ctl_mRead~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~5 .lut_mask = 16'h0F1F; +defparam \z80_|execute_|ctl_reg_in_hi~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y17_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~22 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~22_combout = (\z80_|execute_|ctl_mRead~20_combout & (\z80_|execute_|ctl_reg_in_hi~5_combout & ((!\z80_|execute_|ctl_mRead~16_combout ) # (!\z80_|execute_|ctl_state_alu~4_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|ctl_mRead~20_combout ), + .datac(\z80_|execute_|ctl_mRead~16_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~22 .lut_mask = 16'h4C00; +defparam \z80_|execute_|ctl_mRead~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout = (\z80_|execute_|ixy_d~6_combout & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal52~0_combout & !\z80_|ir_|opcode [0]))) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|pla_decode_|Equal3~1_combout ), + .datac(\z80_|pla_decode_|Equal52~0_combout ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~6_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & (((!\z80_|pla_decode_|Equal35~0_combout & !\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|execute_|ixy_d~6_combout ))) + + .dataa(\z80_|pla_decode_|Equal35~0_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~6 .lut_mask = 16'h0037; +defparam \z80_|execute_|ctl_reg_in_hi~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~2_combout = (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|M5~q ) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|sequencer_|M5~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~2 .lut_mask = 16'hAA00; +defparam \z80_|execute_|ctl_reg_in_hi~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|setM1~30 ( +// Equation(s): +// \z80_|execute_|setM1~30_combout = (\z80_|execute_|ixy_d~6_combout & (!\z80_|execute_|ctl_mRead~14_combout & ((!\z80_|execute_|ctl_mRead~15_combout ) # (!\z80_|execute_|ctl_reg_in_hi~2_combout )))) # (!\z80_|execute_|ixy_d~6_combout & +// (((!\z80_|execute_|ctl_mRead~15_combout )) # (!\z80_|execute_|ctl_reg_in_hi~2_combout ))) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datac(\z80_|execute_|ctl_mRead~14_combout ), + .datad(\z80_|execute_|ctl_mRead~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~30 .lut_mask = 16'h135F; +defparam \z80_|execute_|setM1~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~23 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~23_combout = (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|execute_|ctl_mRead~14_combout & ((!\z80_|execute_|ctl_mRead~15_combout ) # (!\z80_|execute_|ctl_state_alu~4_combout )))) # (!\z80_|execute_|ctl_state_alu~2_combout +// & (((!\z80_|execute_|ctl_mRead~15_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_mRead~14_combout ), + .datad(\z80_|execute_|ctl_mRead~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~23 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_mRead~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~6_combout = (\z80_|execute_|setM1~30_combout & (\z80_|execute_|ctl_mRead~23_combout & ((!\z80_|pla_decode_|Equal6~1_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) + + .dataa(\z80_|execute_|setM1~30_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|execute_|ctl_mRead~23_combout ), + .datad(\z80_|pla_decode_|Equal6~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~6 .lut_mask = 16'h20A0; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~3_combout = ((!\z80_|execute_|ctl_mRead~7_combout & (!\z80_|execute_|ctl_mRead~8_combout & !\z80_|execute_|ctl_mRead~6_combout ))) # (!\z80_|execute_|ixy_d~6_combout ) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|execute_|ctl_mRead~7_combout ), + .datac(\z80_|execute_|ctl_mRead~8_combout ), + .datad(\z80_|execute_|ctl_mRead~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~3 .lut_mask = 16'h5557; +defparam \z80_|execute_|ctl_reg_in_hi~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~10 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~10_combout = (\z80_|execute_|ctl_flags_alu~17_combout & (\z80_|execute_|ctl_flags_alu~6_combout & \z80_|execute_|ctl_reg_in_hi~3_combout )) + + .dataa(\z80_|execute_|ctl_flags_alu~17_combout ), + .datab(\z80_|execute_|ctl_flags_alu~6_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_in_hi~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~10 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_mWrite~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y18_N26 +cycloneive_lcell_comb \z80_|execute_|fMRead~18 ( +// Equation(s): +// \z80_|execute_|fMRead~18_combout = (\z80_|execute_|ctl_ir_we~15_combout & (!\z80_|execute_|ctl_state_alu~2_combout & ((!\z80_|execute_|ctl_mRead~16_combout ) # (!\z80_|execute_|ctl_reg_in_hi~2_combout )))) # (!\z80_|execute_|ctl_ir_we~15_combout & +// (((!\z80_|execute_|ctl_mRead~16_combout )) # (!\z80_|execute_|ctl_reg_in_hi~2_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~15_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_mRead~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~18 .lut_mask = 16'h135F; +defparam \z80_|execute_|fMRead~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N14 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_pc~0_combout = ((!\z80_|pla_decode_|Equal37~0_combout & ((!\z80_|pla_decode_|Equal24~0_combout ) # (!\z80_|pla_decode_|Equal9~0_combout )))) # (!\z80_|execute_|ixy_d~6_combout ) + + .dataa(\z80_|pla_decode_|Equal37~0_combout ), + .datab(\z80_|pla_decode_|Equal9~0_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|pla_decode_|Equal24~0_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_pc~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_pc~0 .lut_mask = 16'h1F5F; +defparam \z80_|reg_control_|reg_sel_pc~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N8 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~1 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_pc~1_combout = (\z80_|pla_decode_|Equal29~0_combout & (!\z80_|execute_|ixy_d~6_combout & ((!\z80_|execute_|ctl_reg_in_hi~2_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) # (!\z80_|pla_decode_|Equal29~0_combout & +// (((!\z80_|execute_|ctl_reg_in_hi~2_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal29~0_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|pla_decode_|Equal47~0_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_pc~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_pc~1 .lut_mask = 16'h0777; +defparam \z80_|reg_control_|reg_sel_pc~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N18 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~2 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_pc~2_combout = (\z80_|reg_control_|reg_sel_pc~0_combout & (\z80_|reg_control_|reg_sel_pc~1_combout & ((!\z80_|pla_decode_|Equal38~2_combout ) # (!\z80_|execute_|ixy_d~6_combout )))) + + .dataa(\z80_|reg_control_|reg_sel_pc~0_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|reg_control_|reg_sel_pc~1_combout ), + .datad(\z80_|pla_decode_|Equal38~2_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_pc~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_pc~2 .lut_mask = 16'h20A0; +defparam \z80_|reg_control_|reg_sel_pc~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y18_N18 +cycloneive_lcell_comb \z80_|execute_|fMRead~19 ( +// Equation(s): +// \z80_|execute_|fMRead~19_combout = (\z80_|reg_control_|reg_sel_pc~2_combout & (\z80_|execute_|ctl_state_alu~7_combout & ((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|ctl_ir_we~7_combout )))) + + .dataa(\z80_|reg_control_|reg_sel_pc~2_combout ), + .datab(\z80_|execute_|ctl_ir_we~7_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_state_alu~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~19 .lut_mask = 16'h2A00; +defparam \z80_|execute_|fMRead~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|fMRead~20 ( +// Equation(s): +// \z80_|execute_|fMRead~20_combout = (\z80_|execute_|ctl_mWrite~10_combout & (\z80_|execute_|ctl_sw_2d~4_combout & (\z80_|execute_|fMRead~18_combout & \z80_|execute_|fMRead~19_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~10_combout ), + .datab(\z80_|execute_|ctl_sw_2d~4_combout ), + .datac(\z80_|execute_|fMRead~18_combout ), + .datad(\z80_|execute_|fMRead~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~20 .lut_mask = 16'h8000; +defparam \z80_|execute_|fMRead~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|fMRead~21 ( +// Equation(s): +// \z80_|execute_|fMRead~21_combout = (\z80_|execute_|ctl_mRead~22_combout & (\z80_|execute_|ctl_reg_in_hi~6_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~6_combout & \z80_|execute_|fMRead~20_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~22_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~6_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), + .datad(\z80_|execute_|fMRead~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~21 .lut_mask = 16'h8000; +defparam \z80_|execute_|fMRead~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~9 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~9_combout = (\z80_|execute_|ctl_sw_2d~8_combout & (\z80_|execute_|ctl_sw_2d~5_combout & (!\z80_|execute_|ctl_alu_shift_oe~16_combout & \z80_|execute_|fMRead~21_combout ))) + + .dataa(\z80_|execute_|ctl_sw_2d~8_combout ), + .datab(\z80_|execute_|ctl_sw_2d~5_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~16_combout ), + .datad(\z80_|execute_|fMRead~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~9 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_sw_2d~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~14 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~14_combout = (!\z80_|execute_|ctl_mRead~12_combout & (((\z80_|decode_state_|in_halt~q ) # (!\z80_|pla_decode_|Equal77~0_combout )) # (!\z80_|pla_decode_|Equal33~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|decode_state_|in_halt~q ), + .datac(\z80_|execute_|ctl_mRead~12_combout ), + .datad(\z80_|pla_decode_|Equal77~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~14 .lut_mask = 16'h0D0F; +defparam \z80_|execute_|ctl_sw_2d~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~8 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~8_combout = (((\z80_|ir_|opcode [5] & !\z80_|ir_|opcode [4])) # (!\z80_|ir_|opcode [3])) # (!\z80_|pla_decode_|Equal12~0_combout ) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|pla_decode_|Equal12~0_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~8 .lut_mask = 16'h2FFF; +defparam \z80_|execute_|ctl_sw_1d~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~10 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~10_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (((\z80_|execute_|rsel3~combout & \z80_|execute_|ctl_iorw~10_combout )) # (!\z80_|execute_|nextM~2_combout ))) + + .dataa(\z80_|execute_|rsel3~combout ), + .datab(\z80_|execute_|ctl_iorw~10_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|nextM~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~10 .lut_mask = 16'h80F0; +defparam \z80_|execute_|ctl_sw_2d~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~11 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~11_combout = (\z80_|execute_|ctl_sw_2d~10_combout ) # ((\z80_|nM1_int~2_combout & ((!\z80_|execute_|ctl_sw_1d~8_combout ) # (!\z80_|execute_|ctl_sw_2d~14_combout )))) + + .dataa(\z80_|execute_|ctl_sw_2d~14_combout ), + .datab(\z80_|execute_|ctl_sw_1d~8_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_sw_2d~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~11 .lut_mask = 16'hFF70; +defparam \z80_|execute_|ctl_sw_2d~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~12 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~12_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|execute_|rsel3~combout & ((\z80_|execute_|ctl_alu_shift_oe~15_combout ) # (\z80_|execute_|ctl_alu_op_low~28_combout )))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~15_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~28_combout ), + .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datad(\z80_|execute_|rsel3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~12 .lut_mask = 16'hFEF0; +defparam \z80_|execute_|ctl_sw_2d~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~13 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~13_combout = ((\z80_|execute_|ctl_sw_2d~11_combout ) # ((\z80_|execute_|ctl_sw_2d~12_combout ) # (!\z80_|execute_|ctl_reg_out_lo~7_combout ))) # (!\z80_|execute_|ctl_sw_2d~9_combout ) + + .dataa(\z80_|execute_|ctl_sw_2d~9_combout ), + .datab(\z80_|execute_|ctl_sw_2d~11_combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .datad(\z80_|execute_|ctl_sw_2d~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~13 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|ctl_sw_2d~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N8 +cycloneive_lcell_comb \z80_|alu_|db[7]~9 ( +// Equation(s): +// \z80_|alu_|db[7]~9_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout ) # ((\z80_|execute_|ctl_sw_2d~13_combout ) # (\z80_|execute_|ctl_alu_oe~11_combout )) + + .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_sw_2d~13_combout ), + .datad(\z80_|execute_|ctl_alu_oe~11_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[7]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[7]~9 .lut_mask = 16'hFFFA; +defparam \z80_|alu_|db[7]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N0 +cycloneive_lcell_comb \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 ( +// Equation(s): +// \z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout = (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )) # (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ))) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 .lut_mask = 16'h1333; +defparam \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout = (\z80_|ir_|opcode [3] & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|pla_decode_|Equal63~0_combout & \z80_|ir_|opcode [4]))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|pla_decode_|Equal63~0_combout ), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~32 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~32_combout = (((!\z80_|pla_decode_|Equal3~0_combout & !\z80_|pla_decode_|Equal21~0_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal63~0_combout ) + + .dataa(\z80_|pla_decode_|Equal63~0_combout ), + .datab(\z80_|pla_decode_|Equal3~0_combout ), + .datac(\z80_|pla_decode_|Equal21~0_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~32 .lut_mask = 16'h57FF; +defparam \z80_|execute_|ctl_alu_op_low~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N2 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~2 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~2_combout = ((!\z80_|pla_decode_|Equal20~0_combout & ((!\z80_|pla_decode_|Equal68~2_combout ) # (!\z80_|pla_decode_|Equal1~4_combout )))) # (!\z80_|nM1_int~2_combout ) + + .dataa(\z80_|pla_decode_|Equal20~0_combout ), + .datab(\z80_|pla_decode_|Equal1~4_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal68~2_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~2 .lut_mask = 16'h1F5F; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~22 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~22_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|ir_|opcode [4])) # (!\z80_|pla_decode_|Equal63~0_combout )) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~22 .lut_mask = 16'hFBFF; +defparam \z80_|execute_|ctl_flags_xy_we~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N28 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~3 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~3_combout = (\z80_|execute_|ctl_alu_op_low~32_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~2_combout & \z80_|execute_|ctl_flags_xy_we~22_combout )) + + .dataa(\z80_|execute_|ctl_alu_op_low~32_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~2_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_flags_xy_we~22_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~3 .lut_mask = 16'h8800; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y18_N2 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~4 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~4_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~3_combout & (\z80_|execute_|ctl_flags_pf_we~10_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~8_combout & \z80_|execute_|ctl_alu_op_low~45_combout ))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~3_combout ), + .datab(\z80_|execute_|ctl_flags_pf_we~10_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~45_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~4 .lut_mask = 16'h8000; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N16 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~5 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~5_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout & (((!\z80_|pla_decode_|Equal21~0_combout & !\z80_|pla_decode_|Equal32~0_combout )) # (!\z80_|pla_decode_|Equal62~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal21~0_combout ), + .datab(\z80_|pla_decode_|Equal32~0_combout ), + .datac(\z80_|pla_decode_|Equal62~2_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~5 .lut_mask = 16'h1F00; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N8 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout = (\z80_|execute_|ctl_alu_shift_oe~38_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|execute_|ctl_ir_we~11_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|execute_|ctl_alu_shift_oe~38_combout ), + .datac(\z80_|execute_|ctl_ir_we~11_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 .lut_mask = 16'hCC4C; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N2 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout & (\z80_|execute_|ctl_flags_sz_we~4_combout & ((!\z80_|pla_decode_|Equal62~2_combout ) # (!\z80_|pla_decode_|Equal9~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal9~0_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ), + .datac(\z80_|pla_decode_|Equal62~2_combout ), + .datad(\z80_|execute_|ctl_flags_sz_we~4_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 .lut_mask = 16'h4C00; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~15 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~15_combout = (\z80_|ir_|opcode [5]) # (((!\z80_|pla_decode_|Equal32~0_combout & !\z80_|pla_decode_|Equal9~0_combout )) # (!\z80_|execute_|ctl_state_alu~11_combout )) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|execute_|ctl_state_alu~11_combout ), + .datac(\z80_|pla_decode_|Equal32~0_combout ), + .datad(\z80_|pla_decode_|Equal9~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~15 .lut_mask = 16'hBBBF; +defparam \z80_|execute_|ctl_alu_core_hf~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N8 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~6 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~6_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout & \z80_|execute_|ctl_alu_core_hf~15_combout ) + + .dataa(gnd), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~15_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~6 .lut_mask = 16'hC0C0; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N10 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~7 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~7_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~5_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~9_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout & !\z80_|execute_|ctl_alu_core_R~1_combout ))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~9_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ), + .datad(\z80_|execute_|ctl_alu_core_R~1_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~7 .lut_mask = 16'h0080; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|ir_|opcode [3]))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N20 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout = (\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ) # ((\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal10~0_combout ) # (\z80_|pla_decode_|Equal61~2_combout )))) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal61~2_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 .lut_mask = 16'hFCEC; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~17 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~17_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal3~1_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~17 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N18 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ) # ((\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ) # ((\z80_|alu_control_|db[1]~26_combout & \z80_|execute_|ctl_flags_bus~combout ))) + + .dataa(\z80_|alu_control_|db[1]~26_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ), + .datac(\z80_|execute_|ctl_flags_bus~combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 .lut_mask = 16'hFFEC; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N4 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout = ((\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ) # ((\z80_|alu_|db_high[3]~7_combout & \z80_|execute_|ctl_flags_alu~15_combout ))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ) + + .dataa(\z80_|alu_|db_high[3]~7_combout ), + .datab(\z80_|execute_|ctl_flags_alu~15_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 .lut_mask = 16'hFF8F; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_nf_we~3_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal10~0_combout ) # ((\z80_|pla_decode_|Equal11~0_combout ) # (\z80_|pla_decode_|Equal61~2_combout )))) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal61~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_nf_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_nf_we~3 .lut_mask = 16'hF0E0; +defparam \z80_|execute_|ctl_flags_nf_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y20_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~0 ( +// Equation(s): +// \z80_|execute_|ctl_flags_nf_we~0_combout = (\z80_|pla_decode_|Equal61~2_combout & (!\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|execute_|ctl_mRead~34_combout )))) # (!\z80_|pla_decode_|Equal61~2_combout & +// (((!\z80_|execute_|ixy_d~5_combout )) # (!\z80_|execute_|ctl_mRead~34_combout ))) + + .dataa(\z80_|pla_decode_|Equal61~2_combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_nf_we~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_nf_we~0 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_flags_nf_we~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y17_N0 +cycloneive_lcell_comb \z80_|pla_decode_|Equal73~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal73~2_combout = (\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [4] & (\z80_|execute_|ctl_state_alu~11_combout & \z80_|ir_|opcode [3]))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|execute_|ctl_state_alu~11_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal73~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal73~2 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal73~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N26 +cycloneive_lcell_comb \z80_|pla_decode_|Equal72~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal72~2_combout = (\z80_|ir_|opcode [5] & (\z80_|execute_|ctl_state_alu~11_combout & (\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [3]))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|execute_|ctl_state_alu~11_combout ), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal72~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal72~2 .lut_mask = 16'h0080; +defparam \z80_|pla_decode_|Equal72~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y20_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~1 ( +// Equation(s): +// \z80_|execute_|ctl_flags_nf_we~1_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout & (\z80_|execute_|ctl_flags_nf_we~0_combout & (!\z80_|pla_decode_|Equal73~2_combout & !\z80_|pla_decode_|Equal72~2_combout ))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ), + .datab(\z80_|execute_|ctl_flags_nf_we~0_combout ), + .datac(\z80_|pla_decode_|Equal73~2_combout ), + .datad(\z80_|pla_decode_|Equal72~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_nf_we~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_nf_we~1 .lut_mask = 16'h0008; +defparam \z80_|execute_|ctl_flags_nf_we~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_nf_we~2_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~18_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout & (\z80_|execute_|ctl_alu_core_hf~15_combout & \z80_|execute_|ctl_flags_nf_we~1_combout ))) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~15_combout ), + .datad(\z80_|execute_|ctl_flags_nf_we~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_nf_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_nf_we~2 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_flags_nf_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~5_combout = (\z80_|sequencer_|DFFE_T4_ff~q ) # ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~5 .lut_mask = 16'hFFBB; +defparam \z80_|execute_|ctl_flags_sz_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~6_combout = (\z80_|execute_|ctl_flags_sz_we~5_combout & ((\z80_|execute_|ctl_alu_core_R~0_combout ) # ((\z80_|pla_decode_|Equal48~0_combout & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) # +// (!\z80_|execute_|ctl_flags_sz_we~5_combout & (((\z80_|pla_decode_|Equal48~0_combout & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) + + .dataa(\z80_|execute_|ctl_flags_sz_we~5_combout ), + .datab(\z80_|execute_|ctl_alu_core_R~0_combout ), + .datac(\z80_|pla_decode_|Equal48~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~6 .lut_mask = 16'hF888; +defparam \z80_|execute_|ctl_flags_sz_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_nf_we~4_combout = (\z80_|execute_|ctl_flags_nf_we~3_combout ) # (((\z80_|execute_|ctl_flags_sz_we~6_combout ) # (!\z80_|execute_|ctl_flags_xy_we~14_combout )) # (!\z80_|execute_|ctl_flags_nf_we~2_combout )) + + .dataa(\z80_|execute_|ctl_flags_nf_we~3_combout ), + .datab(\z80_|execute_|ctl_flags_nf_we~2_combout ), + .datac(\z80_|execute_|ctl_flags_sz_we~6_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_nf_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_nf_we~4 .lut_mask = 16'hFBFF; +defparam \z80_|execute_|ctl_flags_nf_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N24 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~8 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~8_combout = (\z80_|execute_|ctl_flags_nf_we~4_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~7_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ))) # (!\z80_|execute_|ctl_flags_nf_we~4_combout & +// (((\z80_|alu_flags_|DFFE_inst_latch_nf~q )))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~7_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .datad(\z80_|execute_|ctl_flags_nf_we~4_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~8 .lut_mask = 16'h88F0; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y19_N25 +dffeas \z80_|alu_flags_|DFFE_inst_latch_nf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~14 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_cpl~14_combout = (\z80_|ir_|opcode [4]) # (!\z80_|pla_decode_|Equal63~0_combout ) + + .dataa(gnd), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(gnd), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_cpl~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_cpl~14 .lut_mask = 16'hFF33; +defparam \z80_|execute_|ctl_flags_hf_cpl~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_cpl~10_combout = (\z80_|execute_|ctl_flags_hf_cpl~14_combout & (!\z80_|execute_|ctl_alu_op_low~27_combout & (!\z80_|execute_|ctl_state_alu~5_combout & !\z80_|pla_decode_|Equal68~3_combout ))) + + .dataa(\z80_|execute_|ctl_flags_hf_cpl~14_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~27_combout ), + .datac(\z80_|execute_|ctl_state_alu~5_combout ), + .datad(\z80_|pla_decode_|Equal68~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_cpl~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_cpl~10 .lut_mask = 16'h0002; +defparam \z80_|execute_|ctl_flags_hf_cpl~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal45~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal45~0_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [1] & \z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~1_combout ), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal45~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal45~0 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal45~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~11 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_cpl~11_combout = (\z80_|execute_|ctl_state_alu~6_combout ) # ((\z80_|pla_decode_|Equal52~1_combout ) # ((\z80_|pla_decode_|Equal45~0_combout & !\z80_|decode_state_|use_ixiy~combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~6_combout ), + .datab(\z80_|pla_decode_|Equal45~0_combout ), + .datac(\z80_|decode_state_|use_ixiy~combout ), + .datad(\z80_|pla_decode_|Equal52~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_cpl~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_cpl~11 .lut_mask = 16'hFFAE; +defparam \z80_|execute_|ctl_flags_hf_cpl~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~12 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_cpl~12_combout = ((\z80_|execute_|ctl_alu_op_low~25_combout ) # ((\z80_|pla_decode_|Equal10~0_combout ) # (\z80_|execute_|ctl_flags_hf_cpl~11_combout ))) # (!\z80_|execute_|ctl_flags_hf_cpl~10_combout ) + + .dataa(\z80_|execute_|ctl_flags_hf_cpl~10_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~25_combout ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|execute_|ctl_flags_hf_cpl~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_cpl~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_cpl~12 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_flags_hf_cpl~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~13 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_cpl~13_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~q & (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|execute_|ctl_flags_hf_cpl~12_combout & \z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|execute_|ctl_flags_hf_cpl~12_combout ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_cpl~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_cpl~13 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_flags_hf_cpl~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y17_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~8_combout = (\z80_|execute_|ctl_alu_core_S~6_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~4_combout & (\z80_|execute_|ctl_alu_core_S~11_combout & !\z80_|execute_|ctl_alu_core_R~1_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_S~6_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), + .datac(\z80_|execute_|ctl_alu_core_S~11_combout ), + .datad(\z80_|execute_|ctl_alu_core_R~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~8 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_alu_core_S~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y20_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~9_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout & (\z80_|execute_|ctl_alu_core_S~8_combout & !\z80_|pla_decode_|Equal72~2_combout )) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_core_S~8_combout ), + .datad(\z80_|pla_decode_|Equal72~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~9 .lut_mask = 16'h00A0; +defparam \z80_|execute_|ctl_alu_core_S~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~10_combout = (((!\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ) # (!\z80_|execute_|ctl_alu_core_S~12_combout )) # (!\z80_|execute_|ctl_alu_core_R~4_combout )) # (!\z80_|execute_|ctl_alu_core_S~5_combout ) + + .dataa(\z80_|execute_|ctl_alu_core_S~5_combout ), + .datab(\z80_|execute_|ctl_alu_core_R~4_combout ), + .datac(\z80_|execute_|ctl_alu_core_S~12_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~10 .lut_mask = 16'h7FFF; +defparam \z80_|execute_|ctl_alu_core_S~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y20_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~combout = ((\z80_|execute_|ctl_alu_core_S~10_combout ) # ((\z80_|pla_decode_|Equal9~0_combout & \z80_|pla_decode_|Equal62~2_combout ))) # (!\z80_|execute_|ctl_alu_core_S~9_combout ) + + .dataa(\z80_|pla_decode_|Equal9~0_combout ), + .datab(\z80_|execute_|ctl_alu_core_S~9_combout ), + .datac(\z80_|execute_|ctl_alu_core_S~10_combout ), + .datad(\z80_|pla_decode_|Equal62~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S .lut_mask = 16'hFBF3; +defparam \z80_|execute_|ctl_alu_core_S .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N12 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[3] ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_high|Q [3] = (\z80_|alu_|db_high[3]~7_combout & (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & \z80_|execute_|ctl_alu_op1_sel_bus~15_combout )) + + .dataa(\z80_|alu_|db_high[3]~7_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [3]), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[3] .lut_mask = 16'h0A00; +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[3] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N8 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|ena~0 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ) # (\z80_|execute_|ctl_alu_op1_sel_zero~combout ) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_high|ena~0 .lut_mask = 16'hFAFA; +defparam \z80_|alu_|b2v_op1_latch_mux_high|ena~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y17_N13 +dffeas \z80_|alu_|op1_high[3] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [3]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_high [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_high[3] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_high[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N14 +cycloneive_lcell_comb \z80_|alu_|alu_op1[3]~2 ( +// Equation(s): +// \z80_|alu_|alu_op1[3]~2_combout = (\z80_|execute_|ctl_alu_op_low~41_combout & (((\z80_|alu_|op1_low [3])))) # (!\z80_|execute_|ctl_alu_op_low~41_combout & ((\z80_|execute_|ctl_alu_op_low~29_combout & (\z80_|alu_|op1_high [3])) # +// (!\z80_|execute_|ctl_alu_op_low~29_combout & ((\z80_|alu_|op1_low [3]))))) + + .dataa(\z80_|execute_|ctl_alu_op_low~41_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~29_combout ), + .datac(\z80_|alu_|op1_high [3]), + .datad(\z80_|alu_|op1_low [3]), + .cin(gnd), + .combout(\z80_|alu_|alu_op1[3]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op1[3]~2 .lut_mask = 16'hFB40; +defparam \z80_|alu_|alu_op1[3]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N12 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout = (\z80_|execute_|ctl_alu_core_S~combout ) # ((\z80_|alu_|alu_op1[3]~2_combout & \z80_|alu_|alu_op2[3]~2_combout )) + + .dataa(\z80_|execute_|ctl_alu_core_S~combout ), + .datab(gnd), + .datac(\z80_|alu_|alu_op1[3]~2_combout ), + .datad(\z80_|alu_|alu_op2[3]~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hFAAA; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we_lo~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we_lo~2_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|ir_|opcode [5])) + + .dataa(gnd), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we_lo~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we_lo~2 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_reg_sys_we_lo~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we_lo~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we_lo~3_combout = (\z80_|pla_decode_|Equal9~1_combout ) # ((\z80_|execute_|ctl_reg_sys_we_lo~2_combout ) # ((\z80_|pla_decode_|Equal8~0_combout & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal8~0_combout ), + .datab(\z80_|pla_decode_|Equal9~1_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_we_lo~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we_lo~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we_lo~3 .lut_mask = 16'hFFEC; +defparam \z80_|execute_|ctl_reg_sys_we_lo~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~14 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~14_combout = (((!\z80_|pla_decode_|Equal35~0_combout & !\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|alu_control_|flags_cond_true~q )) # (!\z80_|execute_|ixy_d~6_combout ) + + .dataa(\z80_|pla_decode_|Equal35~0_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|pla_decode_|Equal34~0_combout ), + .datad(\z80_|alu_control_|flags_cond_true~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~14 .lut_mask = 16'h37FF; +defparam \z80_|execute_|ctl_reg_sel_wz~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N8 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_hi~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_hi~0_combout = ((\z80_|execute_|ixy_d~6_combout & ((\z80_|execute_|ctl_reg_sys_we_lo~3_combout ) # (\z80_|pla_decode_|Equal19~0_combout )))) # (!\z80_|execute_|ctl_reg_sel_wz~14_combout ) + + .dataa(\z80_|execute_|ctl_reg_sys_we_lo~3_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~14_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_hi~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_hi~0 .lut_mask = 16'hC8FF; +defparam \z80_|reg_control_|reg_sys_we_hi~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N20 +cycloneive_lcell_comb \z80_|pla_decode_|Equal33~3 ( +// Equation(s): +// \z80_|pla_decode_|Equal33~3_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal33~1_combout & (\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|pla_decode_|Equal33~1_combout ), + .datac(\z80_|decode_state_|use_ixiy~combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal33~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal33~3 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal33~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we~0_combout = (\z80_|execute_|ixy_d~5_combout & ((\z80_|pla_decode_|Equal33~3_combout ) # ((\z80_|pla_decode_|Equal6~1_combout ) # (!\z80_|execute_|pc_inc_hold~26_combout )))) + + .dataa(\z80_|pla_decode_|Equal33~3_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|pla_decode_|Equal6~1_combout ), + .datad(\z80_|execute_|pc_inc_hold~26_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we~0 .lut_mask = 16'hC8CC; +defparam \z80_|execute_|ctl_reg_sys_we~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we~2_combout = (!\z80_|execute_|ctl_reg_sys_we~1_combout & (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|execute_|ctl_mWrite~17_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout ))) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|execute_|ctl_reg_sys_we~1_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datad(\z80_|execute_|ctl_mWrite~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we~2 .lut_mask = 16'h0313; +defparam \z80_|execute_|ctl_reg_sys_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we~3_combout = (\z80_|execute_|ctl_reg_sys_we~0_combout ) # (((\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ) # (!\z80_|execute_|ctl_reg_sys_we~2_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~32_combout )) + + .dataa(\z80_|execute_|ctl_reg_sys_we~0_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~32_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), + .datad(\z80_|execute_|ctl_reg_sys_we~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we~3 .lut_mask = 16'hFBFF; +defparam \z80_|execute_|ctl_reg_sys_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~4_combout = (\z80_|reg_control_|reg_sel_pc~2_combout & (\z80_|execute_|ctl_alu_oe~2_combout & (!\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout & \z80_|execute_|ctl_alu_sel_op2_neg~2_combout ))) + + .dataa(\z80_|reg_control_|reg_sel_pc~2_combout ), + .datab(\z80_|execute_|ctl_alu_oe~2_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~4 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_in_hi~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N4 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_hi ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_hi~combout = (\z80_|reg_control_|reg_sys_we_hi~0_combout ) # ((\z80_|execute_|ctl_reg_sys_we~3_combout ) # (!\z80_|execute_|ctl_reg_in_hi~4_combout )) + + .dataa(\z80_|reg_control_|reg_sys_we_hi~0_combout ), + .datab(\z80_|execute_|ctl_reg_sys_we~3_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_in_hi~4_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_hi~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_hi .lut_mask = 16'hEEFF; +defparam \z80_|reg_control_|reg_sys_we_hi .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~18 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~18_combout = (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # ((\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~18 .lut_mask = 16'hF0B0; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo~17 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo~17_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|execute_|ctl_mRead~12_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|execute_|ctl_mRead~12_combout ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo~17 .lut_mask = 16'h80C0; +defparam \z80_|execute_|ctl_reg_sys_hilo~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~11 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~11_combout = (!\z80_|execute_|ctl_reg_sys_hilo~17_combout & (((!\z80_|execute_|ctl_mRead~34_combout & !\z80_|pla_decode_|Equal10~0_combout )) # (!\z80_|execute_|ctl_mWrite~9_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~9_combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~11 .lut_mask = 16'h0057; +defparam \z80_|execute_|ctl_reg_sel_pc~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~12 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~12_combout = (\z80_|execute_|ctl_reg_sel_pc~11_combout & (((\z80_|execute_|ctl_flags_bus~1_combout & \z80_|execute_|ctl_al_we~13_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ), + .datab(\z80_|execute_|ctl_flags_bus~1_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~11_combout ), + .datad(\z80_|execute_|ctl_al_we~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~12 .lut_mask = 16'hD050; +defparam \z80_|execute_|ctl_reg_sel_pc~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~13 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~13_combout = (\z80_|execute_|setM1~54_combout & (\z80_|execute_|ctl_reg_sel_pc~12_combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|pla_decode_|Equal6~1_combout )))) + + .dataa(\z80_|execute_|setM1~54_combout ), + .datab(\z80_|pla_decode_|Equal6~1_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~12_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~13 .lut_mask = 16'h20A0; +defparam \z80_|execute_|ctl_reg_sel_pc~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout = (\z80_|execute_|ixy_d~6_combout & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|execute_|comb~0_combout & \z80_|ir_|opcode [0]))) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|pla_decode_|Equal52~0_combout ), + .datac(\z80_|execute_|comb~0_combout ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~6_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & (((!\z80_|execute_|ctl_mRead~8_combout & !\z80_|execute_|ctl_mRead~6_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~8_combout ), + .datab(\z80_|execute_|ctl_mRead~6_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~6 .lut_mask = 16'h010F; +defparam \z80_|execute_|ctl_reg_sel_wz~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~7_combout = (\z80_|execute_|ctl_reg_sel_wz~6_combout & (((!\z80_|pla_decode_|Equal34~0_combout & !\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|execute_|ctl_reg_in_hi~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal34~0_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~7 .lut_mask = 16'h3700; +defparam \z80_|execute_|ctl_reg_sel_wz~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~9_combout = (\z80_|execute_|ctl_bus_db_oe~0_combout & (\z80_|execute_|ctl_reg_in_hi~3_combout & (\z80_|execute_|ctl_reg_sel_wz~7_combout & \z80_|execute_|ctl_reg_in_hi~4_combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_oe~0_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~3_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~7_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~9 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sel_wz~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~25 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~25_combout = (!\z80_|pla_decode_|Equal35~0_combout & (!\z80_|pla_decode_|Equal24~1_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~11_combout & !\z80_|pla_decode_|Equal19~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal35~0_combout ), + .datab(\z80_|pla_decode_|Equal24~1_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~11_combout ), + .datad(\z80_|pla_decode_|Equal19~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~25 .lut_mask = 16'h0010; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~8_combout = (!\z80_|execute_|ctl_mRead~15_combout & ((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~15_combout ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal12~1_combout ), + .datad(\z80_|pla_decode_|Equal25~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~8 .lut_mask = 16'h5055; +defparam \z80_|execute_|ctl_reg_sel_wz~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~5_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout & (!\z80_|pla_decode_|Equal34~0_combout & (\z80_|execute_|ctl_reg_sel_wz~8_combout & !\z80_|execute_|ctl_mRead~7_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ), + .datab(\z80_|pla_decode_|Equal34~0_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~8_combout ), + .datad(\z80_|execute_|ctl_mRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~5 .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_al_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~4_combout = (!\z80_|execute_|ctl_mRead~2_combout & (!\z80_|execute_|ixy_d~10_combout & (!\z80_|execute_|ixy_d~16_combout & !\z80_|execute_|ctl_mRead~3_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~2_combout ), + .datab(\z80_|execute_|ixy_d~10_combout ), + .datac(\z80_|execute_|ixy_d~16_combout ), + .datad(\z80_|execute_|ctl_mRead~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~4 .lut_mask = 16'h0001; +defparam \z80_|execute_|ctl_al_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~41 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~41_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ctl_al_we~4_combout )))) + + .dataa(\z80_|pla_decode_|Equal34~0_combout ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|execute_|ctl_al_we~4_combout ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~41 .lut_mask = 16'h008C; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~10 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~10_combout = (!\z80_|execute_|ctl_ir_we~8_combout & (!\z80_|execute_|ctl_mRead~13_combout & !\z80_|execute_|ctl_ir_we~14_combout )) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_mRead~13_combout ), + .datad(\z80_|execute_|ctl_ir_we~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~10 .lut_mask = 16'h0005; +defparam \z80_|execute_|ctl_reg_sel_wz~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo~21 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo~21_combout = (\z80_|ir_|opcode [5]) # ((!\z80_|pla_decode_|Equal6~0_combout ) # (!\z80_|pla_decode_|Equal55~0_combout )) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo~21 .lut_mask = 16'hBBFF; +defparam \z80_|execute_|ctl_reg_sys_hilo~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~3 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~3_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~3 .lut_mask = 16'h7755; +defparam \z80_|execute_|ctl_inc_dec~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~22 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~22_combout = (\z80_|execute_|ctl_reg_sys_hilo~21_combout & (((\z80_|execute_|ctl_inc_dec~3_combout ) # (!\z80_|pla_decode_|Equal33~3_combout )))) # (!\z80_|execute_|ctl_reg_sys_hilo~21_combout & +// (!\z80_|execute_|ctl_alu_op_low~22_combout & ((\z80_|execute_|ctl_inc_dec~3_combout ) # (!\z80_|pla_decode_|Equal33~3_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo~21_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datac(\z80_|pla_decode_|Equal33~3_combout ), + .datad(\z80_|execute_|ctl_inc_dec~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~22 .lut_mask = 16'hBB0B; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~23 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~23_combout = (!\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout & ((\z80_|execute_|ctl_reg_sel_wz~10_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout +// )))) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~10_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~23 .lut_mask = 16'h2300; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~24 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~24_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout & (((!\z80_|pla_decode_|Equal6~1_combout & \z80_|execute_|pc_inc_hold~26_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) + + .dataa(\z80_|pla_decode_|Equal6~1_combout ), + .datab(\z80_|execute_|pc_inc_hold~26_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~24 .lut_mask = 16'h4F00; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~19 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~19_combout = (!\z80_|execute_|ctl_reg_sel_wz~8_combout & ((\z80_|execute_|ctl_state_alu~3_combout ) # ((\z80_|execute_|ctl_alu_oe~0_combout ) # (\z80_|execute_|ctl_ir_we~4_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~3_combout ), + .datab(\z80_|execute_|ctl_alu_oe~0_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~19 .lut_mask = 16'h00FE; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N28 +cycloneive_lcell_comb \z80_|execute_|fMRead~2 ( +// Equation(s): +// \z80_|execute_|fMRead~2_combout = ((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~2 .lut_mask = 16'h0AFF; +defparam \z80_|execute_|fMRead~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~20 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~20_combout = (!\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout & ((\z80_|execute_|fMRead~2_combout ) # ((\z80_|execute_|pc_inc_hold~6_combout & !\z80_|execute_|ctl_mRead~7_combout )))) + + .dataa(\z80_|execute_|pc_inc_hold~6_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ), + .datac(\z80_|execute_|ctl_mRead~7_combout ), + .datad(\z80_|execute_|fMRead~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~20 .lut_mask = 16'h3302; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~26 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~26_combout = (!\z80_|pla_decode_|Equal52~1_combout & (!\z80_|pla_decode_|Equal6~1_combout & \z80_|execute_|ctl_bus_db_oe~1_combout )) + + .dataa(\z80_|pla_decode_|Equal52~1_combout ), + .datab(\z80_|pla_decode_|Equal6~1_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~26 .lut_mask = 16'h1100; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~27 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~27_combout = (!\z80_|execute_|fMRead~2_combout & ((!\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ), + .datab(\z80_|execute_|fMRead~2_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~27 .lut_mask = 16'h1133; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~28 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~28_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~20_combout & (!\z80_|execute_|ctl_reg_sys_hilo[1]~27_combout & \z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~20_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~28 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~29 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~29_combout = (!\z80_|execute_|ctl_reg_sys_hilo[1]~41_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout & ((\z80_|execute_|ctl_al_we~5_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) + + .dataa(\z80_|execute_|ctl_al_we~5_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~41_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~29 .lut_mask = 16'h2300; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~30 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~30_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~16_combout & (\z80_|execute_|ctl_reg_sel_pc~13_combout & (\z80_|execute_|ctl_reg_sel_wz~9_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~29_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~16_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~13_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~9_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~29_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~30 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~13 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~13_combout = (\z80_|pla_decode_|Equal9~1_combout & (!\z80_|execute_|ixy_d~6_combout & ((!\z80_|execute_|ctl_reg_in_hi~2_combout )))) # (!\z80_|pla_decode_|Equal9~1_combout & (((!\z80_|pla_decode_|Equal19~0_combout )) # +// (!\z80_|execute_|ixy_d~6_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~13 .lut_mask = 16'h1537; +defparam \z80_|execute_|ctl_reg_sel_wz~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~32 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~32_combout = ((\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ) # ((\z80_|pla_decode_|Equal35~0_combout & \z80_|execute_|ixy_d~6_combout ))) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ) + + .dataa(\z80_|pla_decode_|Equal35~0_combout ), + .datab(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~32 .lut_mask = 16'hFFB3; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y19_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~33 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~33_combout = (!\z80_|ir_|opcode [3] & ((\z80_|execute_|ctl_alu_op_low~28_combout ) # ((\z80_|pla_decode_|Equal48~0_combout & \z80_|execute_|ctl_eval_cond~0_combout )))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|execute_|ctl_alu_op_low~28_combout ), + .datac(\z80_|pla_decode_|Equal48~0_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~33 .lut_mask = 16'h5444; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y19_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~34 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~34_combout = (((\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ) # (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout )) # (!\z80_|execute_|ctl_reg_out_hi~4_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~37_combout ) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~37_combout ), + .datab(\z80_|execute_|ctl_reg_out_hi~4_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~34 .lut_mask = 16'hFFF7; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~35 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~35_combout = (((\z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~13_combout )) # (!\z80_|execute_|ctl_reg_in_hi~5_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~5_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~13_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~35 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N22 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_73 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_73~combout = (\z80_|reg_control_|reg_sel_pc~combout & (\z80_|reg_control_|reg_sys_we_hi~combout & \z80_|execute_|ctl_reg_sys_hilo[1]~35_combout )) + + .dataa(\z80_|reg_control_|reg_sel_pc~combout ), + .datab(gnd), + .datac(\z80_|reg_control_|reg_sys_we_hi~combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_73 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_73 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y14_N5 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[3]~12_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_ir~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_ir~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_ir~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_ir~0 .lut_mask = 16'h0F0C; +defparam \z80_|execute_|ctl_reg_sel_ir~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_ir~1 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_ir~1_combout = (\z80_|execute_|ctl_reg_sel_ir~0_combout ) # (((\z80_|execute_|ctl_eval_cond~0_combout & !\z80_|execute_|ctl_flags_bus~0_combout )) # (!\z80_|execute_|ctl_reg_in_lo~9_combout )) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|ctl_flags_bus~0_combout ), + .datac(\z80_|execute_|ctl_reg_sel_ir~0_combout ), + .datad(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_ir~1 .lut_mask = 16'hF2FF; +defparam \z80_|execute_|ctl_reg_sel_ir~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N16 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_60 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_60~combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout & (!\z80_|reg_control_|reg_sys_we_hi~combout & \z80_|execute_|ctl_reg_sel_ir~1_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), + .datac(\z80_|reg_control_|reg_sys_we_hi~combout ), + .datad(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_60 .lut_mask = 16'h0C00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_60 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N20 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_61 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_61~combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout & (\z80_|reg_control_|reg_sys_we_hi~combout & \z80_|execute_|ctl_reg_sel_ir~1_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), + .datac(\z80_|reg_control_|reg_sys_we_hi~combout ), + .datad(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_61 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_61 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y14_N15 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[3]~12_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we_lo~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we_lo~4_combout = (\z80_|execute_|ctl_reg_sys_we_lo~3_combout & (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_M2_ff~q )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_sys_we_lo~3_combout ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we_lo~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we_lo~4 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_reg_sys_we_lo~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N22 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~combout = ((\z80_|execute_|ctl_reg_sys_we_lo~4_combout ) # ((\z80_|execute_|ctl_reg_sys_we~3_combout ) # (!\z80_|reg_control_|reg_sys_we_lo~4_combout ))) # (!\z80_|reg_control_|reg_sys_we_lo~7_combout ) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~7_combout ), + .datab(\z80_|execute_|ctl_reg_sys_we_lo~4_combout ), + .datac(\z80_|reg_control_|reg_sys_we_lo~4_combout ), + .datad(\z80_|execute_|ctl_reg_sys_we~3_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo .lut_mask = 16'hFFDF; +defparam \z80_|reg_control_|reg_sys_we_lo .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N2 +cycloneive_lcell_comb \z80_|reg_control_|reg_sw_4d_hi~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sw_4d_hi~0_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_control_|reg_sys_we_lo~combout ) # (!\z80_|execute_|ctl_reg_sel_ir~1_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ))) + + .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), + .datac(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datad(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sw_4d_hi~0 .lut_mask = 16'hA2AA; +defparam \z80_|reg_control_|reg_sw_4d_hi~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N14 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~10 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[3]~10_combout = (\z80_|reg_file_|gdfx_temp1[3]~48_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) # (!\z80_|reg_file_|gdfx_temp1[3]~48_combout & +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [3]), + .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[3]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[3]~10 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|db_hi_as[3]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N26 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~11 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[3]~11_combout = (\z80_|reg_file_|db_hi_as[3]~10_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [3]), + .datad(\z80_|reg_file_|db_hi_as[3]~10_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[3]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[3]~11 .lut_mask = 16'hF300; +defparam \z80_|reg_file_|db_hi_as[3]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N14 +cycloneive_lcell_comb \z80_|address_latch_|abusz[11] ( +// Equation(s): +// \z80_|address_latch_|abusz [11] = (\z80_|reg_file_|db_hi_as[3]~12_combout & !\z80_|resets_|clrpc~0_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[3]~12_combout ), + .datab(gnd), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [11]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[11] .lut_mask = 16'h0A0A; +defparam \z80_|address_latch_|abusz[11] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~1 ( +// Equation(s): +// \z80_|execute_|ctl_apin_mux~1_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (\z80_|sequencer_|DFFE_M2_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_apin_mux~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_apin_mux~1 .lut_mask = 16'h3232; +defparam \z80_|execute_|ctl_apin_mux~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~37 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~37_combout = (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|pla_decode_|Equal47~0_combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|pla_decode_|Equal34~0_combout )))) # (!\z80_|execute_|ctl_state_alu~2_combout +// & (((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|pla_decode_|Equal34~0_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|pla_decode_|Equal47~0_combout ), + .datac(\z80_|pla_decode_|Equal34~0_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~37 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_inc_cy~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~2 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~2_combout = (\z80_|execute_|ctl_inc_cy~37_combout & (((!\z80_|pla_decode_|Equal9~1_combout & !\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|execute_|ctl_inc_cy~37_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~2 .lut_mask = 16'h3700; +defparam \z80_|execute_|ctl_inc_dec~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~40 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~40_combout = (\z80_|pla_decode_|Equal34~0_combout & (!\z80_|execute_|ixy_d~9_combout & ((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) # (!\z80_|pla_decode_|Equal34~0_combout & +// (((!\z80_|execute_|ctl_mRead~9_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal34~0_combout ), + .datab(\z80_|pla_decode_|Equal47~0_combout ), + .datac(\z80_|execute_|ctl_mRead~9_combout ), + .datad(\z80_|execute_|ixy_d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~40 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_inc_cy~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~4 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~4_combout = (\z80_|execute_|ctl_inc_cy~40_combout & (((!\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|sequencer_|DFFE_M3_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|execute_|ctl_inc_cy~40_combout ), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~4 .lut_mask = 16'h4CCC; +defparam \z80_|execute_|ctl_inc_dec~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~5 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~5_combout = (\z80_|execute_|ctl_inc_dec~2_combout & (\z80_|execute_|ctl_inc_dec~4_combout & ((!\z80_|execute_|ixy_d~9_combout ) # (!\z80_|pla_decode_|Equal9~1_combout )))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ctl_inc_dec~2_combout ), + .datac(\z80_|execute_|ctl_inc_dec~4_combout ), + .datad(\z80_|execute_|ixy_d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~5 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_inc_dec~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~4_combout = (\z80_|execute_|ctl_inc_dec~5_combout & (((!\z80_|execute_|ctl_state_alu~2_combout & !\z80_|execute_|ctl_mRead~9_combout )) # (!\z80_|execute_|ctl_mWrite~6_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datac(\z80_|execute_|ctl_inc_dec~5_combout ), + .datad(\z80_|execute_|ctl_mRead~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~4 .lut_mask = 16'h3070; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal2~1_combout & (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [1]))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|pla_decode_|Equal2~1_combout ), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 .lut_mask = 16'h0008; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|setM1~42 ( +// Equation(s): +// \z80_|execute_|setM1~42_combout = (!\z80_|pla_decode_|Equal4~0_combout & ((!\z80_|pla_decode_|Equal8~0_combout ) # (!\z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal4~0_combout ), + .datad(\z80_|pla_decode_|Equal8~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~42 .lut_mask = 16'h050F; +defparam \z80_|execute_|setM1~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~12 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~12_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout & (!\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout & ((\z80_|execute_|setM1~42_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ), + .datab(\z80_|execute_|setM1~42_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~12 .lut_mask = 16'h0405; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~4 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~4_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|execute_|ctl_mRead~2_combout & ((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|ctl_mRead~3_combout )))) # (!\z80_|execute_|ixy_d~7_combout & +// (((!\z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|execute_|ctl_mRead~3_combout ))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ctl_mRead~3_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_mRead~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~4 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_sw_1d~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~3 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~3_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~4_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~12_combout & \z80_|execute_|ctl_sw_1d~4_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~12_combout ), + .datad(\z80_|execute_|ctl_sw_1d~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~3 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_sw_4d~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N8 +cycloneive_lcell_comb \z80_|execute_|fMRead~9 ( +// Equation(s): +// \z80_|execute_|fMRead~9_combout = (\z80_|execute_|ctl_mRead~14_combout & (((!\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ctl_state_alu~3_combout )))) # (!\z80_|execute_|ctl_mRead~14_combout & (((!\z80_|execute_|ixy_d~7_combout & +// !\z80_|execute_|ctl_state_alu~3_combout )) # (!\z80_|pla_decode_|Equal37~0_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~14_combout ), + .datab(\z80_|pla_decode_|Equal37~0_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ctl_state_alu~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~9 .lut_mask = 16'h111F; +defparam \z80_|execute_|fMRead~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N2 +cycloneive_lcell_comb \z80_|execute_|fMRead~10 ( +// Equation(s): +// \z80_|execute_|fMRead~10_combout = (\z80_|execute_|fMRead~9_combout & (((!\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ctl_state_alu~3_combout )) # (!\z80_|pla_decode_|Equal38~2_combout ))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|fMRead~9_combout ), + .datac(\z80_|pla_decode_|Equal38~2_combout ), + .datad(\z80_|execute_|ctl_state_alu~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~10 .lut_mask = 16'h0C4C; +defparam \z80_|execute_|fMRead~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|fMRead~8 ( +// Equation(s): +// \z80_|execute_|fMRead~8_combout = (\z80_|pla_decode_|Equal9~1_combout & (!\z80_|execute_|ctl_state_alu~3_combout & (!\z80_|execute_|ixy_d~7_combout ))) # (!\z80_|pla_decode_|Equal9~1_combout & (((!\z80_|execute_|ctl_state_alu~3_combout & +// !\z80_|execute_|ixy_d~7_combout )) # (!\z80_|pla_decode_|Equal29~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ctl_state_alu~3_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|pla_decode_|Equal29~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~8 .lut_mask = 16'h0357; +defparam \z80_|execute_|fMRead~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~2 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~2_combout = (\z80_|execute_|fMRead~10_combout & (\z80_|execute_|fMRead~8_combout & \z80_|execute_|ctl_reg_in_lo~9_combout )) + + .dataa(\z80_|execute_|fMRead~10_combout ), + .datab(\z80_|execute_|fMRead~8_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~2 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_sw_4d~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~11 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~11_combout = (\z80_|execute_|ctl_reg_sel_wz~8_combout & (((\z80_|execute_|ctl_reg_sel_wz~10_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|execute_|ctl_reg_sel_wz~8_combout & +// (!\z80_|execute_|ctl_alu_oe~0_combout & (!\z80_|execute_|ctl_ir_we~4_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~8_combout ), + .datab(\z80_|execute_|ctl_alu_oe~0_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~11 .lut_mask = 16'hAB0B; +defparam \z80_|execute_|ctl_reg_sel_wz~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~12 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~12_combout = (\z80_|execute_|ctl_reg_sel_wz~9_combout & \z80_|execute_|ctl_reg_sel_wz~11_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_sel_wz~9_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~12 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_reg_sel_wz~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~4 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~4_combout = (\z80_|pla_decode_|Equal9~1_combout & (!\z80_|execute_|ctl_reg_in_hi~2_combout & ((\z80_|execute_|ctl_flags_bus~1_combout ) # (!\z80_|execute_|ixy_d~6_combout )))) # (!\z80_|pla_decode_|Equal9~1_combout & +// (((\z80_|execute_|ctl_flags_bus~1_combout )) # (!\z80_|execute_|ixy_d~6_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|execute_|ctl_flags_bus~1_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~4 .lut_mask = 16'h51F3; +defparam \z80_|execute_|ctl_sw_4d~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~5 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~5_combout = (\z80_|execute_|ctl_sw_4d~3_combout & (\z80_|execute_|ctl_sw_4d~2_combout & (\z80_|execute_|ctl_reg_sel_wz~12_combout & \z80_|execute_|ctl_sw_4d~4_combout ))) + + .dataa(\z80_|execute_|ctl_sw_4d~3_combout ), + .datab(\z80_|execute_|ctl_sw_4d~2_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~12_combout ), + .datad(\z80_|execute_|ctl_sw_4d~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~5 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_sw_4d~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~14 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~14_combout = (!\z80_|execute_|ctl_mRead~5_combout & ((\z80_|ir_|opcode [2]) # ((!\z80_|ir_|opcode [1]) # (!\z80_|execute_|ctl_mWrite~4_combout )))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|execute_|ctl_mWrite~4_combout ), + .datac(\z80_|execute_|ctl_mRead~5_combout ), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~14 .lut_mask = 16'h0B0F; +defparam \z80_|execute_|ctl_al_we~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~10 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~10_combout = ((\z80_|pla_decode_|Equal33~3_combout ) # (!\z80_|execute_|ctl_al_we~5_combout )) # (!\z80_|execute_|ctl_al_we~14_combout ) + + .dataa(\z80_|execute_|ctl_al_we~14_combout ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal33~3_combout ), + .datad(\z80_|execute_|ctl_al_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~10 .lut_mask = 16'hF5FF; +defparam \z80_|execute_|ctl_al_we~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~6_combout = (\z80_|execute_|ctl_ir_we~4_combout & (((!\z80_|execute_|ctl_al_we~13_combout )) # (!\z80_|execute_|ctl_flags_bus~1_combout ))) # (!\z80_|execute_|ctl_ir_we~4_combout & (\z80_|execute_|ctl_state_alu~4_combout & +// ((!\z80_|execute_|ctl_al_we~13_combout ) # (!\z80_|execute_|ctl_flags_bus~1_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|execute_|ctl_flags_bus~1_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|ctl_al_we~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~6 .lut_mask = 16'h32FA; +defparam \z80_|execute_|ctl_al_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~7_combout = ((\z80_|execute_|ctl_al_we~6_combout ) # ((\z80_|pla_decode_|Equal35~0_combout & \z80_|execute_|ixy_d~6_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|execute_|ctl_al_we~6_combout ), + .datac(\z80_|pla_decode_|Equal35~0_combout ), + .datad(\z80_|execute_|ixy_d~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~7 .lut_mask = 16'hFDDD; +defparam \z80_|execute_|ctl_al_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~8_combout = (((!\z80_|execute_|ctl_al_we~4_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~31_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout )) # (!\z80_|execute_|ctl_alu_oe~3_combout ) + + .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~31_combout ), + .datad(\z80_|execute_|ctl_al_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~8 .lut_mask = 16'h7FFF; +defparam \z80_|execute_|ctl_al_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~9 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~9_combout = (\z80_|execute_|ctl_al_we~7_combout ) # ((\z80_|execute_|ctl_state_alu~3_combout & ((\z80_|execute_|ctl_al_we~8_combout ) # (!\z80_|execute_|setM1~47_combout )))) + + .dataa(\z80_|execute_|ctl_al_we~7_combout ), + .datab(\z80_|execute_|ctl_state_alu~3_combout ), + .datac(\z80_|execute_|setM1~47_combout ), + .datad(\z80_|execute_|ctl_al_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~9 .lut_mask = 16'hEEAE; +defparam \z80_|execute_|ctl_al_we~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~11 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~11_combout = ((\z80_|execute_|ctl_al_we~9_combout ) # ((\z80_|execute_|ctl_apin_mux~1_combout & \z80_|execute_|ctl_al_we~10_combout ))) # (!\z80_|execute_|ctl_sw_4d~5_combout ) + + .dataa(\z80_|execute_|ctl_apin_mux~1_combout ), + .datab(\z80_|execute_|ctl_sw_4d~5_combout ), + .datac(\z80_|execute_|ctl_al_we~10_combout ), + .datad(\z80_|execute_|ctl_al_we~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~11 .lut_mask = 16'hFFB3; +defparam \z80_|execute_|ctl_al_we~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~12 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~12_combout = ((\z80_|execute_|ctl_al_we~11_combout ) # ((\z80_|pla_decode_|Equal6~1_combout & \z80_|execute_|ixy_d~7_combout ))) # (!\z80_|execute_|setM1~54_combout ) + + .dataa(\z80_|execute_|setM1~54_combout ), + .datab(\z80_|pla_decode_|Equal6~1_combout ), + .datac(\z80_|execute_|ctl_al_we~11_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~12 .lut_mask = 16'hFDF5; +defparam \z80_|execute_|ctl_al_we~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y13_N15 +dffeas \z80_|address_latch_|Q[11] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [11]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [11]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[11] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N24 +cycloneive_lcell_comb \z80_|execute_|fIOWrite~0 ( +// Equation(s): +// \z80_|execute_|fIOWrite~0_combout = ((\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q ))) # (!\z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|fIOWrite~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIOWrite~0 .lut_mask = 16'h0F2F; +defparam \z80_|execute_|fIOWrite~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~8 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~8_combout = (\z80_|execute_|ctl_mWrite~6_combout & ((\z80_|execute_|ctl_mRead~9_combout ) # ((!\z80_|execute_|ctl_inc_dec~3_combout ) # (!\z80_|execute_|fIOWrite~0_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~9_combout ), + .datab(\z80_|execute_|fIOWrite~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~6_combout ), + .datad(\z80_|execute_|ctl_inc_dec~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~8 .lut_mask = 16'hB0F0; +defparam \z80_|execute_|ctl_inc_dec~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y18_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~2_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~5_combout & (\z80_|execute_|ctl_bus_inc_oe~45_combout & ((!\z80_|execute_|ctl_mWrite~17_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~45_combout ), + .datad(\z80_|execute_|ctl_mWrite~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~2 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_reg_gp_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~9 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~9_combout = ((\z80_|execute_|ctl_inc_dec~8_combout ) # ((!\z80_|execute_|ctl_reg_gp_we~2_combout & \z80_|ir_|opcode [3]))) # (!\z80_|execute_|ctl_inc_dec~12_combout ) + + .dataa(\z80_|execute_|ctl_inc_dec~12_combout ), + .datab(\z80_|execute_|ctl_inc_dec~8_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~2_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~9 .lut_mask = 16'hDFDD; +defparam \z80_|execute_|ctl_inc_dec~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N22 +cycloneive_lcell_comb \z80_|address_latch_|abusz[1] ( +// Equation(s): +// \z80_|address_latch_|abusz [1] = (\z80_|reg_file_|db_lo_as[1]~6_combout & !\z80_|resets_|clrpc~0_combout ) + + .dataa(\z80_|reg_file_|db_lo_as[1]~6_combout ), + .datab(gnd), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [1]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[1] .lut_mask = 16'h0A0A; +defparam \z80_|address_latch_|abusz[1] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y11_N23 +dffeas \z80_|address_latch_|Q[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [1]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[1] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~0 ( +// Equation(s): +// \z80_|execute_|ctl_apin_mux~0_combout = (\z80_|execute_|ctl_inc_cy~32_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~37_combout & ((!\z80_|pla_decode_|Equal19~0_combout ) # (!\z80_|execute_|ctl_alu_oe~0_combout )))) + + .dataa(\z80_|execute_|ctl_inc_cy~32_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~37_combout ), + .datac(\z80_|execute_|ctl_alu_oe~0_combout ), + .datad(\z80_|pla_decode_|Equal19~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_apin_mux~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_apin_mux~0 .lut_mask = 16'h0888; +defparam \z80_|execute_|ctl_apin_mux~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~6 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~6_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout & (\z80_|execute_|ctl_apin_mux~0_combout & ((!\z80_|pla_decode_|Equal9~1_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|pla_decode_|Equal9~1_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), + .datad(\z80_|execute_|ctl_apin_mux~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~6 .lut_mask = 16'h0700; +defparam \z80_|execute_|ctl_inc_dec~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~7 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~7_combout = (!\z80_|execute_|ctl_bus_inc_oe~42_combout ) # (!\z80_|execute_|ctl_inc_dec~5_combout ) + + .dataa(\z80_|execute_|ctl_inc_dec~5_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_bus_inc_oe~42_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~7 .lut_mask = 16'h5F5F; +defparam \z80_|execute_|ctl_inc_dec~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N6 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout = \z80_|address_latch_|Q [1] $ (((\z80_|execute_|ctl_inc_dec~9_combout ) # ((\z80_|execute_|ctl_inc_dec~7_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout )))) + + .dataa(\z80_|execute_|ctl_inc_dec~9_combout ), + .datab(\z80_|address_latch_|Q [1]), + .datac(\z80_|execute_|ctl_inc_dec~6_combout ), + .datad(\z80_|execute_|ctl_inc_dec~7_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0 .lut_mask = 16'h3363; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~21 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~21_combout = (\z80_|reg_control_|reg_sys_we_lo~6_combout & (\z80_|execute_|ctl_mRead~20_combout & ((!\z80_|execute_|ixy_d~15_combout ) # (!\z80_|sequencer_|DFFE_T3_ff~q )))) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~6_combout ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|execute_|ixy_d~15_combout ), + .datad(\z80_|execute_|ctl_mRead~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~21 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_reg_sel_wz~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~40 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[0]~40_combout = (\z80_|execute_|ctl_reg_sel_wz~20_combout ) # ((\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|M5~q & \z80_|pla_decode_|Equal9~1_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|M5~q ), + .datac(\z80_|execute_|ctl_reg_sel_wz~20_combout ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~40 .lut_mask = 16'hF8F0; +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y19_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~39 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~39_combout = (\z80_|execute_|ctl_alu_op_low~28_combout ) # ((\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|pla_decode_|Equal48~0_combout & !\z80_|sequencer_|DFFE_M1_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|execute_|ctl_alu_op_low~28_combout ), + .datac(\z80_|pla_decode_|Equal48~0_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~39 .lut_mask = 16'hCCEC; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y19_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~13 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[0]~13_combout = (((\z80_|execute_|ctl_reg_sys_hilo[1]~39_combout & \z80_|ir_|opcode [3])) # (!\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout )) # (!\z80_|execute_|ctl_reg_out_lo~9_combout ) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~39_combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~9_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~13 .lut_mask = 16'hBF3F; +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~31 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[0]~31_combout = (((\z80_|execute_|ctl_reg_sys_hilo[0]~40_combout ) # (\z80_|execute_|ctl_reg_sys_hilo[0]~13_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~21_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~21_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[0]~40_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~31 .lut_mask = 16'hFFF7; +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N12 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_63 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_63~combout = (\z80_|execute_|ctl_reg_sys_hilo[0]~31_combout & (\z80_|reg_control_|reg_sys_we_lo~combout & \z80_|execute_|ctl_reg_sel_ir~1_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~31_combout ), + .datac(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datad(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_63 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y12_N9 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[2]~9_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|setM1~49 ( +// Equation(s): +// \z80_|execute_|setM1~49_combout = (!\z80_|execute_|ctl_ir_we~11_combout & (!\z80_|pla_decode_|Equal69~0_combout & ((!\z80_|pla_decode_|Equal63~0_combout ) # (!\z80_|pla_decode_|Equal21~0_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~11_combout ), + .datab(\z80_|pla_decode_|Equal21~0_combout ), + .datac(\z80_|pla_decode_|Equal69~0_combout ), + .datad(\z80_|pla_decode_|Equal63~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~49_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~49 .lut_mask = 16'h0105; +defparam \z80_|execute_|setM1~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_sel_shift~2_combout = (!\z80_|pla_decode_|Equal20~0_combout & !\z80_|execute_|ctl_ir_we~8_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal20~0_combout ), + .datad(\z80_|execute_|ctl_ir_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~2 .lut_mask = 16'h000F; +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|setM1~50 ( +// Equation(s): +// \z80_|execute_|setM1~50_combout = (\z80_|execute_|ctl_flags_hf_cpl~10_combout & (\z80_|execute_|nextM~2_combout & (\z80_|execute_|setM1~49_combout & \z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ))) + + .dataa(\z80_|execute_|ctl_flags_hf_cpl~10_combout ), + .datab(\z80_|execute_|nextM~2_combout ), + .datac(\z80_|execute_|setM1~49_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~50_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~50 .lut_mask = 16'h8000; +defparam \z80_|execute_|setM1~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_flags_oe~0_combout = (!\z80_|execute_|ctl_iorw~11_combout & (!\z80_|execute_|ctl_mRead~4_combout & (!\z80_|execute_|ctl_ir_we~14_combout & !\z80_|execute_|ctl_ir_we~12_combout ))) + + .dataa(\z80_|execute_|ctl_iorw~11_combout ), + .datab(\z80_|execute_|ctl_mRead~4_combout ), + .datac(\z80_|execute_|ctl_ir_we~14_combout ), + .datad(\z80_|execute_|ctl_ir_we~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_oe~0 .lut_mask = 16'h0001; +defparam \z80_|execute_|ctl_flags_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~1 ( +// Equation(s): +// \z80_|execute_|ctl_flags_oe~1_combout = (\z80_|execute_|ctl_al_we~13_combout & (\z80_|execute_|ctl_flags_bus~1_combout & (\z80_|execute_|ctl_flags_oe~0_combout & !\z80_|pla_decode_|Equal13~2_combout ))) + + .dataa(\z80_|execute_|ctl_al_we~13_combout ), + .datab(\z80_|execute_|ctl_flags_bus~1_combout ), + .datac(\z80_|execute_|ctl_flags_oe~0_combout ), + .datad(\z80_|pla_decode_|Equal13~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_oe~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_oe~1 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_flags_oe~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~13 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~13_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & ((!\z80_|execute_|ctl_flags_oe~1_combout ) # (!\z80_|execute_|setM1~50_combout )))) + + .dataa(\z80_|execute_|setM1~50_combout ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|execute_|ctl_flags_oe~1_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~13 .lut_mask = 16'h004C; +defparam \z80_|execute_|ctl_reg_in_hi~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~12 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~12_combout = (!\z80_|execute_|ctl_mRead~12_combout & (!\z80_|execute_|ctl_alu_oe~1_combout & !\z80_|pla_decode_|Equal49~0_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_mRead~12_combout ), + .datac(\z80_|execute_|ctl_alu_oe~1_combout ), + .datad(\z80_|pla_decode_|Equal49~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~12 .lut_mask = 16'h0003; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~7_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal69~0_combout ) # ((!\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ) # (!\z80_|execute_|ctl_sw_1d~8_combout )))) + + .dataa(\z80_|pla_decode_|Equal69~0_combout ), + .datab(\z80_|execute_|ctl_sw_1d~8_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~7 .lut_mask = 16'hBF00; +defparam \z80_|execute_|ctl_reg_in_hi~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~13 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~13_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|execute_|ctl_state_alu~6_combout & !\z80_|pla_decode_|Equal52~1_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|pla_decode_|Equal52~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~13 .lut_mask = 16'hBBBF; +defparam \z80_|execute_|ctl_state_alu~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~6_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout & (!\z80_|execute_|ctl_reg_in_hi~13_combout & (!\z80_|execute_|ctl_reg_in_hi~7_combout & \z80_|execute_|ctl_state_alu~13_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~13_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~7_combout ), + .datad(\z80_|execute_|ctl_state_alu~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~6 .lut_mask = 16'h0100; +defparam \z80_|execute_|ctl_reg_gp_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~5_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout & (((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|pla_decode_|Equal12~1_combout ), + .datad(\z80_|pla_decode_|Equal25~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~5 .lut_mask = 16'h5155; +defparam \z80_|execute_|ctl_reg_gp_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~17 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~17_combout = ((!\z80_|execute_|ctl_mRead~2_combout & ((!\z80_|pla_decode_|Equal32~0_combout ) # (!\z80_|pla_decode_|Equal63~0_combout )))) # (!\z80_|nM1_int~2_combout ) + + .dataa(\z80_|pla_decode_|Equal63~0_combout ), + .datab(\z80_|execute_|ctl_mRead~2_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal32~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~17 .lut_mask = 16'h1F3F; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~18 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~17_combout & (\z80_|execute_|ctl_pf_sel[0]~3_combout & (\z80_|execute_|ctl_flags_pf_we~4_combout & \z80_|execute_|ctl_alu_oe~6_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~17_combout ), + .datab(\z80_|execute_|ctl_pf_sel[0]~3_combout ), + .datac(\z80_|execute_|ctl_flags_pf_we~4_combout ), + .datad(\z80_|execute_|ctl_alu_oe~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~18 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y17_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~10_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout & (((!\z80_|execute_|ctl_mRead~34_combout & !\z80_|pla_decode_|Equal21~1_combout )) # (!\z80_|execute_|ctl_mRead~9_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|execute_|ctl_mRead~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~10 .lut_mask = 16'h0155; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~9 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~9_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|pla_decode_|Equal6~1_combout )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|pla_decode_|Equal6~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~9 .lut_mask = 16'h0300; +defparam \z80_|execute_|ctl_sw_1d~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~9_combout = (!\z80_|execute_|ctl_sw_1d~9_combout & (((!\z80_|execute_|ctl_mRead~16_combout ) # (!\z80_|sequencer_|M5~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|M5~q ), + .datac(\z80_|execute_|ctl_sw_1d~9_combout ), + .datad(\z80_|execute_|ctl_mRead~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~9 .lut_mask = 16'h070F; +defparam \z80_|execute_|ctl_reg_gp_we~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~4_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~10_combout & \z80_|execute_|ctl_reg_gp_we~9_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_gp_we~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~4 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_reg_gp_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~7_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~6_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|execute_|ctl_reg_gp_we~5_combout & \z80_|execute_|ctl_reg_gp_we~4_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~5_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~7 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~3_combout = (\z80_|execute_|ctl_inc_cy~78_combout & (\z80_|execute_|ctl_bus_inc_oe~48_combout & (\z80_|execute_|ctl_bus_inc_oe~26_combout & \z80_|execute_|ctl_inc_cy~49_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~78_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~48_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~26_combout ), + .datad(\z80_|execute_|ctl_inc_cy~49_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~3 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~32 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~32_combout = (\z80_|execute_|ctl_reg_gp_we~2_combout & (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout & ((!\z80_|execute_|ixy_d~9_combout ) # (!\z80_|pla_decode_|Equal10~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~2_combout ), + .datac(\z80_|execute_|ixy_d~9_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~32 .lut_mask = 16'h004C; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~2 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~2_combout = (\z80_|execute_|nextM~2_combout & (((!\z80_|execute_|ixy_d~9_combout )) # (!\z80_|pla_decode_|Equal11~0_combout ))) # (!\z80_|execute_|nextM~2_combout & (!\z80_|execute_|ixy_d~5_combout & +// ((!\z80_|execute_|ixy_d~9_combout ) # (!\z80_|pla_decode_|Equal11~0_combout )))) + + .dataa(\z80_|execute_|nextM~2_combout ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|execute_|ixy_d~9_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~2 .lut_mask = 16'h2A3F; +defparam \z80_|execute_|ctl_sw_4u~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~3 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~3_combout = (\z80_|execute_|ctl_reg_gp_we~3_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout & \z80_|execute_|ctl_sw_4u~2_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~3_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout ), + .datac(\z80_|execute_|ctl_sw_4u~2_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~3 .lut_mask = 16'h8080; +defparam \z80_|execute_|ctl_sw_4u~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~8_combout = (\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # (((!\z80_|execute_|ctl_reg_gp_hilo[1]~15_combout ) # (!\z80_|execute_|ctl_sw_4u~3_combout )) # (!\z80_|execute_|ctl_reg_gp_we~7_combout )) + + .dataa(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datac(\z80_|execute_|ctl_sw_4u~3_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~8 .lut_mask = 16'hBFFF; +defparam \z80_|execute_|ctl_reg_gp_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~14 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~14_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~13_combout & ((\z80_|pla_decode_|Equal33~1_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~15_combout & +// !\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~13_combout ), + .datab(\z80_|pla_decode_|Equal33~1_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~15_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~14 .lut_mask = 16'h888A; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~24 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~24_combout = (\z80_|execute_|rsel3~combout & (((\z80_|nM1_int~2_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~12_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~14_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~14_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ), + .datad(\z80_|execute_|rsel3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~24 .lut_mask = 16'h5D00; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout = (\z80_|sequencer_|DFFE_M4_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & (!\z80_|pla_decode_|Equal12~1_combout & \z80_|pla_decode_|Equal25~0_combout ))) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|pla_decode_|Equal12~1_combout ), + .datad(\z80_|pla_decode_|Equal25~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~25 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~25_combout = (\z80_|execute_|ctl_ir_we~7_combout ) # ((\z80_|execute_|ctl_ir_we~15_combout ) # ((!\z80_|execute_|ctl_reg_sys_hilo~21_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~7_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~25 .lut_mask = 16'hEFFF; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~26 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~26_combout = (\z80_|execute_|ctl_state_alu~3_combout & ((\z80_|execute_|ctl_iorw~10_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ) # (\z80_|execute_|ctl_state_alu~6_combout )))) + + .dataa(\z80_|execute_|ctl_iorw~10_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|ctl_state_alu~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~26 .lut_mask = 16'hFE00; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~46 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~46_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # ((\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T2_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|nextM~2_combout ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~46 .lut_mask = 16'h0E0C; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~27 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~27_combout = ((\z80_|execute_|ctl_reg_gp_hilo[0]~46_combout ) # ((\z80_|pla_decode_|Equal6~1_combout & \z80_|execute_|ixy_d~7_combout ))) # (!\z80_|execute_|ctl_mRead~23_combout ) + + .dataa(\z80_|execute_|ctl_mRead~23_combout ), + .datab(\z80_|pla_decode_|Equal6~1_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~46_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~27 .lut_mask = 16'hFDF5; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~29 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~29_combout = (\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ) # +// (!\z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~29 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~22 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~22_combout = (\z80_|execute_|ixy_d~7_combout & (((\z80_|execute_|ctl_mWrite~6_combout ) # (\z80_|execute_|ctl_mRead~5_combout )) # (!\z80_|execute_|ctl_al_we~13_combout ))) + + .dataa(\z80_|execute_|ctl_al_we~13_combout ), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datac(\z80_|execute_|ctl_mRead~5_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~22 .lut_mask = 16'hFD00; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~23 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~23_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~22_combout ) # ((!\z80_|execute_|ctl_flags_oe~1_combout & ((\z80_|execute_|ctl_state_alu~3_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~3_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|execute_|ctl_flags_oe~1_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~23 .lut_mask = 16'hFF0B; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~31 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~31_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~24_combout ) # (((\z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ) # (\z80_|execute_|ctl_reg_gp_hilo[0]~23_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~30_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~24_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~23_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~31 .lut_mask = 16'hFFFB; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~33 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~33_combout = (\z80_|execute_|ixy_d~6_combout & (((!\z80_|pla_decode_|Equal10~0_combout & !\z80_|pla_decode_|Equal11~0_combout )))) # (!\z80_|execute_|ixy_d~6_combout & (((!\z80_|pla_decode_|Equal11~0_combout )) # +// (!\z80_|execute_|ixy_d~9_combout ))) + + .dataa(\z80_|execute_|ixy_d~9_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|pla_decode_|Equal11~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~33 .lut_mask = 16'h113F; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~26 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~26_combout = (\z80_|execute_|ctl_reg_gp_we~3_combout & (\z80_|execute_|fMRead~8_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~4_combout & \z80_|execute_|fMRead~10_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_we~3_combout ), + .datab(\z80_|execute_|fMRead~8_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), + .datad(\z80_|execute_|fMRead~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~26 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~34 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~34_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~12_combout & \z80_|execute_|ctl_reg_gp_sel[1]~26_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~12_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~34 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~25 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~25_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout & (\z80_|execute_|ctl_state_alu~13_combout & \z80_|execute_|ctl_reg_gp_sel[0]~24_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .datab(\z80_|execute_|ctl_state_alu~13_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~25 .lut_mask = 16'h4040; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~20 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~20_combout = (\z80_|execute_|ctl_reg_gp_sel~7_combout ) # ((!\z80_|execute_|ctl_reg_gp_hilo[1]~15_combout ) # (!\z80_|execute_|ctl_sw_2u~5_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_sel~7_combout ), + .datab(\z80_|execute_|ctl_sw_2u~5_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~20 .lut_mask = 16'hBBFF; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~21 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~21_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout & ((\z80_|execute_|rsel0~combout ) # ((!\z80_|execute_|setM1~50_combout & !\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) # +// (!\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout & (((!\z80_|execute_|setM1~50_combout & !\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), + .datab(\z80_|execute_|rsel0~combout ), + .datac(\z80_|execute_|setM1~50_combout ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~21 .lut_mask = 16'h888F; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~35 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~35_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ) # (((\z80_|execute_|ctl_reg_gp_hilo[0]~21_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[0]~25_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~34_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~34_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~35 .lut_mask = 16'hFFBF; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N14 +cycloneive_lcell_comb \z80_|pla_decode_|Equal2~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal2~2_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal1~7_combout & \z80_|pla_decode_|Equal32~0_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal2~0_combout ), + .datac(\z80_|pla_decode_|Equal1~7_combout ), + .datad(\z80_|pla_decode_|Equal32~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal2~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal2~2 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N14 +cycloneive_lcell_comb \z80_|pla_decode_|Equal1~6 ( +// Equation(s): +// \z80_|pla_decode_|Equal1~6_combout = (\z80_|pla_decode_|Equal1~4_combout & (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal1~5_combout & \z80_|pla_decode_|Equal1~7_combout ))) + + .dataa(\z80_|pla_decode_|Equal1~4_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|pla_decode_|Equal1~5_combout ), + .datad(\z80_|pla_decode_|Equal1~7_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal1~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal1~6 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal1~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N20 +cycloneive_lcell_comb \z80_|reg_control_|bank_exx~2 ( +// Equation(s): +// \z80_|reg_control_|bank_exx~2_combout = \z80_|reg_control_|bank_exx~q $ (((\z80_|pla_decode_|Equal1~6_combout & (\z80_|sequencer_|DFFE_T2_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )))) + + .dataa(\z80_|pla_decode_|Equal1~6_combout ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|reg_control_|bank_exx~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|reg_control_|bank_exx~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|bank_exx~2 .lut_mask = 16'hF078; +defparam \z80_|reg_control_|bank_exx~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y15_N21 +dffeas \z80_|reg_control_|bank_exx ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_control_|bank_exx~2_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_control_|bank_exx~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_control_|bank_exx .is_wysiwyg = "true"; +defparam \z80_|reg_control_|bank_exx .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N6 +cycloneive_lcell_comb \z80_|reg_control_|bank_hl_de1~0 ( +// Equation(s): +// \z80_|reg_control_|bank_hl_de1~0_combout = \z80_|reg_control_|bank_hl_de1~q $ (((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|pla_decode_|Equal2~2_combout & !\z80_|reg_control_|bank_exx~q )))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|pla_decode_|Equal2~2_combout ), + .datac(\z80_|reg_control_|bank_hl_de1~q ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_control_|bank_hl_de1~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|bank_hl_de1~0 .lut_mask = 16'hF0B4; +defparam \z80_|reg_control_|bank_hl_de1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y15_N7 +dffeas \z80_|reg_control_|bank_hl_de1 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_control_|bank_hl_de1~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_control_|bank_hl_de1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_control_|bank_hl_de1 .is_wysiwyg = "true"; +defparam \z80_|reg_control_|bank_hl_de1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~19 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout = (\z80_|execute_|ctl_sw_1d~4_combout & (((\z80_|execute_|ctl_sw_1d~8_combout & !\z80_|pla_decode_|Equal69~0_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_sw_1d~4_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|execute_|ctl_sw_1d~8_combout ), + .datad(\z80_|pla_decode_|Equal69~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~19 .lut_mask = 16'h22A2; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~28 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~28_combout = (!\z80_|execute_|ctl_reg_gp_sel~7_combout & \z80_|execute_|ctl_sw_2u~2_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_sel~7_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_sw_2u~2_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~28 .lut_mask = 16'h5050; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~29 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~29_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~28_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~27_combout & !\z80_|execute_|ctl_reg_in_hi~13_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~28_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~27_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~29 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~30 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~30_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~25_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~29_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~26_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~29_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~30 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y15_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~13 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~13_combout = (!\z80_|execute_|ctl_sw_1d~9_combout & (((!\z80_|execute_|ctl_state_alu~3_combout & !\z80_|execute_|ixy_d~7_combout )) # (!\z80_|execute_|ctl_mWrite~6_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~3_combout ), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ctl_sw_1d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~13 .lut_mask = 16'h0037; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~45 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~45_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~14_combout & ((\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ) # ((\z80_|sequencer_|DFFE_M1_ff~q ) # (\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~14_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~45 .lut_mask = 16'hAAA8; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~2_combout = (((!\z80_|execute_|ctl_mRead~9_combout & !\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal6~0_combout )) # (!\z80_|pla_decode_|Equal8~0_combout ) + + .dataa(\z80_|execute_|ctl_mRead~9_combout ), + .datab(\z80_|pla_decode_|Equal8~0_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~2 .lut_mask = 16'h3F7F; +defparam \z80_|execute_|ctl_reg_use_sp~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~3_combout = (\z80_|execute_|nextM~11_combout & (\z80_|execute_|ctl_bus_inc_oe~49_combout & (\z80_|execute_|ctl_reg_use_sp~0_combout & \z80_|execute_|ctl_reg_use_sp~2_combout ))) + + .dataa(\z80_|execute_|nextM~11_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~49_combout ), + .datac(\z80_|execute_|ctl_reg_use_sp~0_combout ), + .datad(\z80_|execute_|ctl_reg_use_sp~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~3 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_use_sp~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~14 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~14_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~13_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~45_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~6_combout & \z80_|execute_|ctl_reg_use_sp~3_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~13_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), + .datad(\z80_|execute_|ctl_reg_use_sp~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~14 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~32 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~32_combout = (\z80_|ir_|opcode [4] & (((!\z80_|execute_|ctl_reg_sys_hilo~21_combout & \z80_|execute_|ctl_state_alu~3_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|execute_|ctl_reg_sys_hilo~21_combout ), + .datad(\z80_|execute_|ctl_state_alu~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~32 .lut_mask = 16'h4C44; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~33 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~33_combout = (\z80_|execute_|ixy_d~7_combout & (((\z80_|execute_|ctl_mRead~3_combout ) # (\z80_|pla_decode_|Equal11~0_combout )))) # (!\z80_|execute_|ixy_d~7_combout & (\z80_|execute_|ixy_d~5_combout & +// ((\z80_|pla_decode_|Equal11~0_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_mRead~3_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|pla_decode_|Equal11~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~33 .lut_mask = 16'hFAC0; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~16 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~16_combout = (\z80_|execute_|setM1~57_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~15_combout & (\z80_|execute_|ctl_sw_2u~4_combout & \z80_|execute_|ctl_sw_2u~1_combout ))) + + .dataa(\z80_|execute_|setM1~57_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~15_combout ), + .datac(\z80_|execute_|ctl_sw_2u~4_combout ), + .datad(\z80_|execute_|ctl_sw_2u~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~16 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~34 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~34_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ) # ((!\z80_|execute_|ctl_reg_gp_hilo[1]~16_combout & \z80_|ir_|opcode [1])) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~16_combout ), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~34 .lut_mask = 16'hCFCC; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~35 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~35_combout = ((\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ) # (\z80_|execute_|ctl_reg_gp_sel[0]~34_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~35 .lut_mask = 16'hFFF5; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~20 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~20_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|pla_decode_|Equal4~0_combout ) # ((\z80_|pla_decode_|Equal1~4_combout & \z80_|pla_decode_|Equal2~1_combout )))) + + .dataa(\z80_|pla_decode_|Equal4~0_combout ), + .datab(\z80_|pla_decode_|Equal1~4_combout ), + .datac(\z80_|pla_decode_|Equal2~1_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~20 .lut_mask = 16'hEA00; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~21 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~21_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout ) # (\z80_|execute_|ctl_state_alu~2_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|nextM~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~21 .lut_mask = 16'h00FE; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~22 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~22_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~20_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~21_combout ) # ((\z80_|execute_|ctl_mRead~34_combout & \z80_|execute_|ctl_state_alu~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~20_combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~22 .lut_mask = 16'hFFEA; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~18 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~18_combout = (\z80_|execute_|ctl_mWrite~17_combout ) # ((\z80_|execute_|ctl_mRead~5_combout ) # ((\z80_|pla_decode_|Equal21~0_combout & \z80_|pla_decode_|Equal24~0_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~17_combout ), + .datab(\z80_|pla_decode_|Equal21~0_combout ), + .datac(\z80_|execute_|ctl_mRead~5_combout ), + .datad(\z80_|pla_decode_|Equal24~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~18 .lut_mask = 16'hFEFA; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~37 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~37_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~5_combout & (((!\z80_|execute_|ctl_mWrite~17_combout ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), + .datad(\z80_|execute_|ctl_mWrite~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~37 .lut_mask = 16'h70F0; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~19 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~19_combout = ((\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~18_combout & \z80_|execute_|ixy_d~7_combout ))) # (!\z80_|execute_|ctl_reg_gp_sel[1]~37_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~18_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~37_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~19 .lut_mask = 16'hFF8F; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~23 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~23_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~22_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ) # ((!\z80_|execute_|ctl_reg_gp_hilo[1]~16_combout & \z80_|ir_|opcode [2]))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~22_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~16_combout ), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~23 .lut_mask = 16'hEFEE; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y14_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~16 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~16_combout = (\z80_|execute_|ctl_state_alu~3_combout & (((\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout )) # (!\z80_|execute_|ctl_mRead~17_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~17_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|ctl_state_alu~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~16 .lut_mask = 16'hF700; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~17 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~17_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~16_combout ) # ((\z80_|execute_|ixy_d~15_combout & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~16_combout ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|execute_|ixy_d~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~17 .lut_mask = 16'hFECC; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~11 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~11_combout = (!\z80_|decode_state_|DFFE_instCB~q & (!\z80_|decode_state_|DFFE_instED~q & ((\z80_|sequencer_|DFFE_M4_ff~q ) # (\z80_|sequencer_|M5~q )))) + + .dataa(\z80_|decode_state_|DFFE_instCB~q ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|decode_state_|DFFE_instED~q ), + .datad(\z80_|sequencer_|M5~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~11 .lut_mask = 16'h0504; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~36 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~36_combout = (\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [2] & (\z80_|execute_|ctl_reg_gp_sel[1]~11_combout & !\z80_|ir_|opcode [4]))) + + .dataa(\z80_|ir_|opcode [1]), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~36 .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~8_combout = (\z80_|ir_|opcode [7] & (!\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|ir_|opcode [3] & \z80_|ir_|opcode [6]))) + + .dataa(\z80_|ir_|opcode [7]), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~8 .lut_mask = 16'h0200; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~9_combout = (\z80_|ir_|opcode [3] & (((\z80_|sequencer_|DFFE_T3_ff~q )))) # (!\z80_|ir_|opcode [3] & (((!\z80_|pla_decode_|Equal12~0_combout & \z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal12~0_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~9 .lut_mask = 16'hBF05; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~10 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~10_combout = (\z80_|ir_|opcode [0] & (\z80_|execute_|ctl_reg_gp_sel[1]~8_combout )) # (!\z80_|ir_|opcode [0] & (((\z80_|execute_|ctl_reg_gp_sel[1]~9_combout & \z80_|execute_|ctl_ir_we~6_combout )))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~8_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~9_combout ), + .datad(\z80_|execute_|ctl_ir_we~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~10 .lut_mask = 16'hD888; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~15 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~15_combout = (\z80_|ir_|opcode [5] & (((\z80_|execute_|ctl_reg_gp_sel[1]~36_combout & \z80_|execute_|ctl_reg_gp_sel[1]~10_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~15 .lut_mask = 16'hA222; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~31 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~31_combout = ((\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~17_combout ) # (\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ))) # (!\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~17_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~31 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N24 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~5 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_de2~5_combout = (!\z80_|decode_state_|DFFE_instIY1~q & (!\z80_|decode_state_|DFFE_inst4~q & (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & \z80_|execute_|ctl_reg_gp_sel[1]~31_combout ))) + + .dataa(\z80_|decode_state_|DFFE_instIY1~q ), + .datab(\z80_|decode_state_|DFFE_inst4~q ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_de2~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_de2~5 .lut_mask = 16'h0100; +defparam \z80_|reg_control_|reg_sel_de2~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N28 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~6 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_de2~6_combout = (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (((\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ) # (\z80_|execute_|ctl_reg_gp_sel[0]~32_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_de2~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_de2~6 .lut_mask = 16'h00FD; +defparam \z80_|reg_control_|reg_sel_de2~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N24 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_de~0_combout = (!\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de1~q & (\z80_|reg_control_|reg_sel_de2~5_combout )) # (!\z80_|reg_control_|bank_hl_de1~q & ((\z80_|reg_control_|reg_sel_de2~6_combout ))))) + + .dataa(\z80_|reg_control_|bank_hl_de1~q ), + .datab(\z80_|reg_control_|bank_exx~q ), + .datac(\z80_|reg_control_|reg_sel_de2~5_combout ), + .datad(\z80_|reg_control_|reg_sel_de2~6_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_de~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_de~0 .lut_mask = 16'h3120; +defparam \z80_|reg_control_|reg_sel_de~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N14 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_50 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_50~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout & \z80_|reg_control_|reg_sel_de~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .datad(\z80_|reg_control_|reg_sel_de~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_50 .lut_mask = 16'h5000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N22 +cycloneive_lcell_comb \z80_|reg_control_|bank_hl_de2~0 ( +// Equation(s): +// \z80_|reg_control_|bank_hl_de2~0_combout = \z80_|reg_control_|bank_hl_de2~q $ (((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|pla_decode_|Equal2~2_combout & \z80_|reg_control_|bank_exx~q )))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|pla_decode_|Equal2~2_combout ), + .datac(\z80_|reg_control_|bank_hl_de2~q ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_control_|bank_hl_de2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|bank_hl_de2~0 .lut_mask = 16'hB4F0; +defparam \z80_|reg_control_|bank_hl_de2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y15_N23 +dffeas \z80_|reg_control_|bank_hl_de2 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_control_|bank_hl_de2~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_control_|bank_hl_de2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_control_|bank_hl_de2 .is_wysiwyg = "true"; +defparam \z80_|reg_control_|bank_hl_de2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N16 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~4 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_de2~4_combout = (\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de2~q & (\z80_|reg_control_|reg_sel_de2~5_combout )) # (!\z80_|reg_control_|bank_hl_de2~q & ((\z80_|reg_control_|reg_sel_de2~6_combout ))))) + + .dataa(\z80_|reg_control_|bank_hl_de2~q ), + .datab(\z80_|reg_control_|bank_exx~q ), + .datac(\z80_|reg_control_|reg_sel_de2~5_combout ), + .datad(\z80_|reg_control_|reg_sel_de2~6_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_de2~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_de2~4 .lut_mask = 16'hC480; +defparam \z80_|reg_control_|reg_sel_de2~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N24 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_46 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_46~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout & \z80_|reg_control_|reg_sel_de2~4_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .datad(\z80_|reg_control_|reg_sel_de2~4_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_46 .lut_mask = 16'h5000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N22 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_47 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_47~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout & \z80_|reg_control_|reg_sel_de2~4_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .datad(\z80_|reg_control_|reg_sel_de2~4_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_47 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y11_N1 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N16 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_51 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_51~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout & \z80_|reg_control_|reg_sel_de~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .datad(\z80_|reg_control_|reg_sel_de~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_51 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y11_N7 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~33 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~33_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [2]), + .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~33 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[2]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N8 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_hl~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_hl~0_combout = (!\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de1~q & ((\z80_|reg_control_|reg_sel_de2~6_combout ))) # (!\z80_|reg_control_|bank_hl_de1~q & (\z80_|reg_control_|reg_sel_de2~5_combout )))) + + .dataa(\z80_|reg_control_|bank_hl_de1~q ), + .datab(\z80_|reg_control_|bank_exx~q ), + .datac(\z80_|reg_control_|reg_sel_de2~5_combout ), + .datad(\z80_|reg_control_|reg_sel_de2~6_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_hl~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_hl~0 .lut_mask = 16'h3210; +defparam \z80_|reg_control_|reg_sel_hl~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N26 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_59 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_59~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout & (\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|reg_control_|reg_sel_hl~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_59 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y12_N31 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N30 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_hl2~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_hl2~0_combout = (\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de2~q & ((\z80_|reg_control_|reg_sel_de2~6_combout ))) # (!\z80_|reg_control_|bank_hl_de2~q & (\z80_|reg_control_|reg_sel_de2~5_combout )))) + + .dataa(\z80_|reg_control_|bank_hl_de2~q ), + .datab(\z80_|reg_control_|bank_exx~q ), + .datac(\z80_|reg_control_|reg_sel_de2~5_combout ), + .datad(\z80_|reg_control_|reg_sel_de2~6_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_hl2~0 .lut_mask = 16'hC840; +defparam \z80_|reg_control_|reg_sel_hl2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N4 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_54 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_54~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout & (!\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|reg_control_|reg_sel_hl2~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_54 .lut_mask = 16'h2200; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N18 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_55 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_55~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout & (\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|reg_control_|reg_sel_hl2~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_55 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y12_N25 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N20 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_58 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_58~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout & (!\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|reg_control_|reg_sel_hl~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_58 .lut_mask = 16'h0A00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~34 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~34_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [2] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [2] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [2]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~34 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp0[2]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N2 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout & !\z80_|execute_|ctl_reg_gp_we~8_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 .lut_mask = 16'h0C0C; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N0 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout = (\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & !\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ))) + + .dataa(\z80_|reg_control_|bank_exx~q ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 .lut_mask = 16'h0020; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N22 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout & \z80_|execute_|ctl_reg_gp_we~8_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 .lut_mask = 16'hC0C0; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N18 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout = (!\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & !\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ))) + + .dataa(\z80_|reg_control_|bank_exx~q ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 .lut_mask = 16'h0010; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y14_N29 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N12 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout = (\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & !\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ))) + + .dataa(\z80_|reg_control_|bank_exx~q ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 .lut_mask = 16'h0020; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y14_N7 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N16 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout = (!\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & !\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ))) + + .dataa(\z80_|reg_control_|bank_exx~q ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 .lut_mask = 16'h0010; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~36 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~36_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [2]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [2]), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~36 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[2]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~15 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~15_combout = (((\z80_|execute_|ctl_66_oe~2_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~14_combout )) # (!\z80_|execute_|ctl_reg_in_hi~5_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~13_combout ) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~13_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~5_combout ), + .datac(\z80_|execute_|ctl_66_oe~2_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~15 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|ctl_reg_sel_wz~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~18 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~18_combout = (((\z80_|execute_|ctl_reg_sel_wz~15_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~12_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~21_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~17_combout ) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~17_combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~21_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~12_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~18 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_reg_sel_wz~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N0 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_83 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_83~combout = (\z80_|execute_|ctl_reg_sel_wz~18_combout & (\z80_|reg_control_|reg_sys_we_lo~combout & \z80_|execute_|ctl_reg_sys_hilo[0]~31_combout )) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~18_combout ), + .datab(gnd), + .datac(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_83 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_83 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y13_N5 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N8 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_82 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_82~combout = (\z80_|execute_|ctl_reg_sel_wz~18_combout & (!\z80_|reg_control_|reg_sys_we_lo~combout & \z80_|execute_|ctl_reg_sys_hilo[0]~31_combout )) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~18_combout ), + .datab(gnd), + .datac(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_82 .lut_mask = 16'h0A00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_82 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~37 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~37_combout = (\z80_|reg_file_|gdfx_temp0[2]~36_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|gdfx_temp0[2]~36_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~37 .lut_mask = 16'hC0CC; +defparam \z80_|reg_file_|gdfx_temp0[2]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N6 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & (\z80_|decode_state_|DFFE_inst4~q & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), + .datab(\z80_|decode_state_|DFFE_inst4~q ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 .lut_mask = 16'h0080; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N14 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_iy~2 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_iy~2_combout = (\z80_|decode_state_|DFFE_instIY1~q & (!\z80_|decode_state_|DFFE_inst4~q & (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & \z80_|execute_|ctl_reg_gp_sel[1]~31_combout ))) + + .dataa(\z80_|decode_state_|DFFE_instIY1~q ), + .datab(\z80_|decode_state_|DFFE_inst4~q ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_iy~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_iy~2 .lut_mask = 16'h0200; +defparam \z80_|reg_control_|reg_sel_iy~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N10 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_71 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_71~combout = (\z80_|reg_control_|reg_sel_iy~2_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout & \z80_|execute_|ctl_reg_gp_we~8_combout )) + + .dataa(gnd), + .datab(\z80_|reg_control_|reg_sel_iy~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y12_N3 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N28 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|decode_state_|DFFE_inst4~q ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|decode_state_|DFFE_inst4~q ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 .lut_mask = 16'h2000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y12_N1 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N12 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_70 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_70~combout = (\z80_|reg_control_|reg_sel_iy~2_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout & !\z80_|execute_|ctl_reg_gp_we~8_combout )) + + .dataa(gnd), + .datab(\z80_|reg_control_|reg_sel_iy~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70 .lut_mask = 16'h00C0; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~38 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~38_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (\z80_|reg_file_|b2v_latch_ix_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [2]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_iy_lo|latch [2]), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~38 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[2]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout = (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|ir_|opcode [3] & (\z80_|ir_|opcode [4] & \z80_|pla_decode_|Equal24~0_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|pla_decode_|Equal24~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~9_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|execute_|ctl_mRead~2_combout )))) # (!\z80_|pla_decode_|Equal47~0_combout +// & (((!\z80_|execute_|ixy_d~7_combout )) # (!\z80_|execute_|ctl_mRead~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal47~0_combout ), + .datab(\z80_|execute_|ctl_mRead~2_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~9 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_reg_in_hi~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~10 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~10_combout = (\z80_|execute_|ctl_reg_gp_we~7_combout & (\z80_|execute_|ctl_reg_in_hi~8_combout & \z80_|execute_|ctl_reg_in_hi~9_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_in_hi~8_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~10 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_reg_in_hi~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_lo~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_lo~8_combout = (\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ) # (((!\z80_|execute_|ctl_reg_in_hi~10_combout ) # (!\z80_|execute_|ctl_reg_in_lo~9_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~21_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~21_combout ), + .datac(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_lo~8 .lut_mask = 16'hBFFF; +defparam \z80_|execute_|ctl_reg_in_lo~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N0 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_sp_lo|latch[2]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_sp_lo|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp0[2]~42_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_sp_lo|latch[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[2]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~4_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal6~1_combout & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_M1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|pla_decode_|Equal6~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~4 .lut_mask = 16'h0D00; +defparam \z80_|execute_|ctl_reg_use_sp~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~5_combout = (\z80_|execute_|ctl_reg_use_sp~4_combout ) # ((\z80_|execute_|ctl_mRead~15_combout & ((\z80_|execute_|ctl_reg_in_hi~2_combout ) # (\z80_|execute_|ctl_state_alu~4_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~15_combout ), + .datab(\z80_|execute_|ctl_reg_use_sp~4_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~5 .lut_mask = 16'hEEEC; +defparam \z80_|execute_|ctl_reg_use_sp~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~6_combout = (\z80_|execute_|ctl_reg_use_sp~5_combout ) # ((!\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ) # (!\z80_|execute_|ctl_reg_use_sp~3_combout )) + + .dataa(\z80_|execute_|ctl_reg_use_sp~5_combout ), + .datab(\z80_|execute_|ctl_reg_use_sp~3_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~6 .lut_mask = 16'hBFBF; +defparam \z80_|execute_|ctl_reg_use_sp~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N14 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout = (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & \z80_|execute_|ctl_reg_gp_sel[1]~31_combout ))) + + .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y12_N1 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_sp_lo|latch[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~5 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~5_combout = (\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_mRead~12_combout ) # ((\z80_|pla_decode_|Equal49~0_combout ) # (!\z80_|execute_|ctl_sw_1d~8_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~12_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|execute_|ctl_sw_1d~8_combout ), + .datad(\z80_|pla_decode_|Equal49~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~5 .lut_mask = 16'hCC8C; +defparam \z80_|execute_|ctl_sw_1d~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y19_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_im_we ( +// Equation(s): +// \z80_|execute_|ctl_im_we~combout = (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_im_we~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_im_we .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_im_we .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~6 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~6_combout = (\z80_|execute_|ctl_sw_1d~4_combout & (!\z80_|execute_|ctl_sw_1d~5_combout & (\z80_|execute_|ctl_sw_2d~9_combout & !\z80_|execute_|ctl_im_we~combout ))) + + .dataa(\z80_|execute_|ctl_sw_1d~4_combout ), + .datab(\z80_|execute_|ctl_sw_1d~5_combout ), + .datac(\z80_|execute_|ctl_sw_2d~9_combout ), + .datad(\z80_|execute_|ctl_im_we~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~6 .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_sw_1d~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~7 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~7_combout = ((\z80_|execute_|ctl_66_oe~2_combout & !\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q )) # (!\z80_|execute_|ctl_sw_1d~6_combout ) + + .dataa(\z80_|execute_|ctl_66_oe~2_combout ), + .datab(\z80_|execute_|ctl_sw_1d~6_combout ), + .datac(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~7 .lut_mask = 16'h3B3B; +defparam \z80_|execute_|ctl_sw_1d~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N18 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[2]~2 ( +// Equation(s): +// \z80_|reg_file_|db_lo_ds[2]~2_combout = (\z80_|reg_file_|gdfx_temp0[2]~42_combout ) # ((!\z80_|execute_|ctl_reg_out_lo~5_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout & \z80_|execute_|ctl_reg_out_lo~7_combout ))) + + .dataa(\z80_|execute_|ctl_reg_out_lo~5_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_ds[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_ds[2]~2 .lut_mask = 16'hFF40; +defparam \z80_|reg_file_|db_lo_ds[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N8 +cycloneive_lcell_comb \z80_|alu_control_|db[2]~28 ( +// Equation(s): +// \z80_|alu_control_|db[2]~28_combout = (\z80_|reg_file_|db_lo_ds[2]~2_combout & (((!\z80_|execute_|ctl_sw_mask543_en~0_combout & \z80_|bus_control_|db[2]~13_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) + + .dataa(\z80_|execute_|ctl_sw_mask543_en~0_combout ), + .datab(\z80_|bus_control_|db[2]~13_combout ), + .datac(\z80_|execute_|ctl_sw_1d~7_combout ), + .datad(\z80_|reg_file_|db_lo_ds[2]~2_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[2]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[2]~28 .lut_mask = 16'h4F00; +defparam \z80_|alu_control_|db[2]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~11 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~11_combout = (((\z80_|execute_|ixy_d~6_combout & \z80_|pla_decode_|Equal9~1_combout )) # (!\z80_|execute_|ctl_reg_in_hi~5_combout )) # (!\z80_|execute_|ctl_reg_in_hi~6_combout ) + + .dataa(\z80_|execute_|ctl_reg_in_hi~6_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~5_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~11 .lut_mask = 16'hF777; +defparam \z80_|execute_|ctl_reg_in_hi~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~12 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~12_combout = (((\z80_|execute_|ctl_reg_in_hi~11_combout ) # (!\z80_|execute_|ctl_reg_in_hi~4_combout )) # (!\z80_|execute_|ctl_reg_in_hi~3_combout )) # (!\z80_|execute_|ctl_reg_in_hi~10_combout ) + + .dataa(\z80_|execute_|ctl_reg_in_hi~10_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~3_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~11_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~12 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|ctl_reg_in_hi~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~42 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~42_combout = ((\z80_|execute_|ctl_state_alu~3_combout & ((!\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ) # (!\z80_|execute_|setM1~48_combout )))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~34_combout ) + + .dataa(\z80_|execute_|setM1~48_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ), + .datac(\z80_|execute_|ctl_state_alu~3_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~42 .lut_mask = 16'h70FF; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~39 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~39_combout = ((\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mRead~3_combout ) # (!\z80_|execute_|ctl_al_we~14_combout )))) # (!\z80_|execute_|setM1~30_combout ) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|setM1~30_combout ), + .datac(\z80_|execute_|ctl_mRead~3_combout ), + .datad(\z80_|execute_|ctl_al_we~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~39 .lut_mask = 16'hB3BB; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~38 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~38_combout = ((!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ixy_d~5_combout ) # (\z80_|execute_|ctl_state_alu~2_combout )))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), + .datad(\z80_|execute_|nextM~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~38 .lut_mask = 16'h0FEF; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~40 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~40_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ) # ((!\z80_|execute_|rsel3~combout & !\z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ), + .datab(\z80_|execute_|rsel3~combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~40 .lut_mask = 16'hFAFB; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~41 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~41_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ) # (((!\z80_|execute_|rsel0~combout & \z80_|execute_|ctl_reg_gp_hilo[1]~20_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), + .datab(\z80_|execute_|rsel0~combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~41 .lut_mask = 16'hBFAF; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~43 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~43_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ) # (((\z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ) # (!\z80_|execute_|ctl_reg_gp_we~4_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~43 .lut_mask = 16'hFBFF; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N12 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout & !\z80_|execute_|ctl_reg_gp_we~8_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 .lut_mask = 16'h00F0; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N14 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout & (\z80_|decode_state_|DFFE_inst4~q & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .datac(\z80_|decode_state_|DFFE_inst4~q ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 .lut_mask = 16'h0080; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N30 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|execute_|ctl_reg_use_sp~6_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datac(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N14 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_68 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_68~combout = (\z80_|reg_control_|reg_sel_iy~2_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout & !\z80_|execute_|ctl_reg_gp_we~8_combout )) + + .dataa(gnd), + .datab(\z80_|reg_control_|reg_sel_iy~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68 .lut_mask = 16'h00C0; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N0 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout = (!\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) + + .dataa(\z80_|reg_control_|bank_exx~q ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 .lut_mask = 16'h0010; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N8 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout = (\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) + + .dataa(\z80_|reg_control_|bank_exx~q ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 .lut_mask = 16'h0200; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~18 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~18_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~18 .lut_mask = 16'hFEFE; +defparam \z80_|reg_file_|gdfx_temp1[0]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N26 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_80 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_80~combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout & (!\z80_|reg_control_|reg_sys_we_hi~combout & \z80_|execute_|ctl_reg_sel_wz~18_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), + .datac(\z80_|reg_control_|reg_sys_we_hi~combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~18_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_80 .lut_mask = 16'h0C00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y13_N14 +cycloneive_lcell_comb \z80_|pla_decode_|Equal21~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal21~2_combout = (\z80_|pla_decode_|Equal40~0_combout & (\z80_|pla_decode_|Equal6~0_combout & !\z80_|ir_|opcode [5])) + + .dataa(\z80_|pla_decode_|Equal40~0_combout ), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(gnd), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal21~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal21~2 .lut_mask = 16'h0088; +defparam \z80_|pla_decode_|Equal21~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N4 +cycloneive_lcell_comb \z80_|reg_control_|bank_af~0 ( +// Equation(s): +// \z80_|reg_control_|bank_af~0_combout = \z80_|reg_control_|bank_af~q $ (((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|pla_decode_|Equal32~0_combout & \z80_|pla_decode_|Equal21~2_combout )))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|pla_decode_|Equal32~0_combout ), + .datac(\z80_|reg_control_|bank_af~q ), + .datad(\z80_|pla_decode_|Equal21~2_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|bank_af~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|bank_af~0 .lut_mask = 16'hB4F0; +defparam \z80_|reg_control_|bank_af~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y13_N5 +dffeas \z80_|reg_control_|bank_af ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_control_|bank_af~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_control_|bank_af~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_control_|bank_af .is_wysiwyg = "true"; +defparam \z80_|reg_control_|bank_af .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N24 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_af~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_af~0_combout = (!\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (!\z80_|reg_control_|bank_af~q & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) + + .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datac(\z80_|reg_control_|bank_af~q ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_af~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_af~0 .lut_mask = 16'h0400; +defparam \z80_|reg_control_|reg_sel_af~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N10 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_af2~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_af2~0_combout = (!\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_control_|bank_af~q & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) + + .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datac(\z80_|reg_control_|bank_af~q ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_af2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_af2~0 .lut_mask = 16'h4000; +defparam \z80_|reg_control_|reg_sel_af2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N4 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_28 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_28~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout & (\z80_|reg_control_|reg_sel_af2~0_combout & !\z80_|execute_|ctl_reg_gp_we~8_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datab(gnd), + .datac(\z80_|reg_control_|reg_sel_af2~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_28 .lut_mask = 16'h00A0; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~17 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~17_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout & \z80_|reg_control_|reg_sel_af~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .datac(\z80_|reg_control_|reg_sel_af~0_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~17 .lut_mask = 16'hFFEA; +defparam \z80_|reg_file_|gdfx_temp1[0]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~19 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~19_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ) # ((\z80_|reg_file_|gdfx_temp1[0]~18_combout ) # (\z80_|reg_file_|gdfx_temp1[0]~17_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~18_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[0]~17_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~19 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp1[0]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N0 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_52 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_52~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout & (!\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|reg_control_|reg_sel_hl2~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_52 .lut_mask = 16'h0A00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N28 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_44 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_44~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout & \z80_|reg_control_|reg_sel_de2~4_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datad(\z80_|reg_control_|reg_sel_de2~4_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_44 .lut_mask = 16'h5000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N30 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_48 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_48~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout & \z80_|reg_control_|reg_sel_de~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datad(\z80_|reg_control_|reg_sel_de~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_48 .lut_mask = 16'h5000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N20 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_56 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_56~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout & \z80_|reg_control_|reg_sel_hl~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_56 .lut_mask = 16'h5000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~16 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~16_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~16 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp1[0]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~20 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~20_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout ) # ((\z80_|reg_file_|gdfx_temp1[0]~19_combout ) # ((\z80_|reg_file_|gdfx_temp1[0]~16_combout ) # (\z80_|execute_|ctl_sw_4u~6_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[0]~19_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~16_combout ), + .datad(\z80_|execute_|ctl_sw_4u~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~20 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp1[0]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N6 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout & \z80_|execute_|ctl_reg_gp_we~8_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 .lut_mask = 16'hF000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N4 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & (\z80_|decode_state_|DFFE_inst4~q & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), + .datab(\z80_|decode_state_|DFFE_inst4~q ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 .lut_mask = 16'h0080; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y16_N7 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N8 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_69 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_69~combout = (\z80_|reg_control_|reg_sel_iy~2_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout & \z80_|execute_|ctl_reg_gp_we~8_combout )) + + .dataa(gnd), + .datab(\z80_|reg_control_|reg_sel_iy~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y16_N25 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~34 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~34_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [2]), + .datad(\z80_|reg_file_|b2v_latch_iy_hi|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~34 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[2]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N2 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|execute_|ctl_reg_use_sp~6_combout & \z80_|execute_|ctl_reg_gp_sel[1]~31_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datac(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y15_N15 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N30 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_81 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_81~combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout & (\z80_|reg_control_|reg_sys_we_hi~combout & \z80_|execute_|ctl_reg_sel_wz~18_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), + .datac(\z80_|reg_control_|reg_sys_we_hi~combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~18_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_81 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_81 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y15_N9 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~36 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~36_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (\z80_|reg_file_|b2v_latch_wz_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [2]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [2]), + .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~36 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp1[2]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N18 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_29 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_29~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout & (\z80_|reg_control_|reg_sel_af2~0_combout & \z80_|execute_|ctl_reg_gp_we~8_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datab(gnd), + .datac(\z80_|reg_control_|reg_sel_af2~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_29 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y16_N25 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~35 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~35_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout & (\z80_|alu_|db[2]~16_combout & ((\z80_|reg_file_|b2v_latch_af2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # +// (!\z80_|execute_|ctl_reg_in_hi~12_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .datab(\z80_|alu_|db[2]~16_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~35 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[2]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N22 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout = (\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ))) + + .dataa(\z80_|reg_control_|bank_exx~q ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 .lut_mask = 16'h0200; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y16_N31 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N20 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout = (!\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ))) + + .dataa(\z80_|reg_control_|bank_exx~q ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 .lut_mask = 16'h0100; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y16_N13 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~33 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~33_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (\z80_|reg_file_|b2v_latch_bc2_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]), + .datad(\z80_|reg_file_|b2v_latch_bc_hi|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~33 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[2]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~37 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~37_combout = (\z80_|reg_file_|gdfx_temp1[2]~34_combout & (\z80_|reg_file_|gdfx_temp1[2]~36_combout & (\z80_|reg_file_|gdfx_temp1[2]~35_combout & \z80_|reg_file_|gdfx_temp1[2]~33_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[2]~34_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[2]~36_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[2]~35_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[2]~33_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~37 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[2]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N20 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_45 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_45~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout & \z80_|reg_control_|reg_sel_de2~4_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sel_de2~4_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_45 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y15_N31 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N12 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp1[2]~39_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N24 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_49 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_49~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout & \z80_|reg_control_|reg_sel_de~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datad(\z80_|reg_control_|reg_sel_de~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_49 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y15_N13 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~31 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~31_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [2]), + .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~31 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[2]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N2 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_33 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_33~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout & \z80_|reg_control_|reg_sel_af~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_33 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y15_N31 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N30 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[2]~12 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[2]~12_combout = (\z80_|execute_|ctl_reg_gp_we~8_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [2]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [2]), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[2]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[2]~12 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[2]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N26 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_57 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_57~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout & \z80_|reg_control_|reg_sel_hl~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_57 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y14_N21 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N2 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_53 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_53~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout & (\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|reg_control_|reg_sel_hl2~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_53 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y14_N7 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~32 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~32_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (\z80_|reg_file_|b2v_latch_hl_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_hl2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (((\z80_|reg_file_|b2v_latch_hl2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [2]), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~32 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[2]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~38 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~38_combout = (\z80_|reg_file_|gdfx_temp1[2]~37_combout & (\z80_|reg_file_|gdfx_temp1[2]~31_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[2]~12_combout & \z80_|reg_file_|gdfx_temp1[2]~32_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[2]~37_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[2]~31_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|db[2]~12_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[2]~32_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~38 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[2]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~11 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~11_combout = (((\z80_|execute_|ctl_inc_dec~9_combout ) # (!\z80_|execute_|ctl_inc_dec~5_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~42_combout )) # (!\z80_|execute_|ctl_inc_dec~6_combout ) + + .dataa(\z80_|execute_|ctl_inc_dec~6_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~42_combout ), + .datac(\z80_|execute_|ctl_inc_dec~5_combout ), + .datad(\z80_|execute_|ctl_inc_dec~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~11 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_inc_dec~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N8 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout = \z80_|address_latch_|Q [9] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ) + + .dataa(\z80_|address_latch_|Q [9]), + .datab(gnd), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out .lut_mask = 16'h5A5A; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y14_N31 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[1]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y17_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_sel_shift~5_combout = (\z80_|sequencer_|DFFE_T4_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|pla_decode_|Equal20~0_combout ) # (\z80_|execute_|ctl_ir_we~8_combout )))) + + .dataa(\z80_|pla_decode_|Equal20~0_combout ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|execute_|ctl_ir_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~5 .lut_mask = 16'h0C08; +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_sel_shift~3_combout = (\z80_|execute_|ctl_state_alu~4_combout ) # ((\z80_|decode_state_|DFFE_instCB~q & (\z80_|pla_decode_|Equal33~0_combout & \z80_|execute_|ctl_mWrite~5_combout ))) + + .dataa(\z80_|decode_state_|DFFE_instCB~q ), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~5_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~3 .lut_mask = 16'hFF80; +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_sel_shift~4_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ) # ((\z80_|execute_|ctl_ir_we~6_combout & (\z80_|execute_|ctl_ir_we~5_combout & \z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ))) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ), + .datab(\z80_|execute_|ctl_ir_we~6_combout ), + .datac(\z80_|execute_|ctl_ir_we~5_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~4 .lut_mask = 16'hEAAA; +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~4_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [0] & !\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) + + .dataa(\z80_|pla_decode_|Equal3~1_combout ), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~4 .lut_mask = 16'h0008; +defparam \z80_|execute_|ctl_flags_cf_cpl~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~5_combout = ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_state_alu~5_combout ) # (\z80_|execute_|ctl_alu_op_low~25_combout )))) # (!\z80_|execute_|ctl_state_alu~13_combout ) + + .dataa(\z80_|execute_|ctl_state_alu~5_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|execute_|ctl_alu_op_low~25_combout ), + .datad(\z80_|execute_|ctl_state_alu~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~5 .lut_mask = 16'h32FF; +defparam \z80_|execute_|ctl_flags_cf_cpl~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~16 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~16_combout = (\z80_|pla_decode_|Equal9~0_combout & (\z80_|pla_decode_|Equal63~0_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # (\z80_|nM1_int~2_combout )))) + + .dataa(\z80_|pla_decode_|Equal9~0_combout ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~16 .lut_mask = 16'h8880; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~6_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_flags_cf_cpl~4_combout ) # ((\z80_|execute_|ctl_flags_cf_cpl~5_combout )))) # (!\z80_|alu_flags_|DFFE_inst_latch_nf~q & +// (((\z80_|execute_|ctl_alu_sel_op2_neg~16_combout )))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .datab(\z80_|execute_|ctl_flags_cf_cpl~4_combout ), + .datac(\z80_|execute_|ctl_flags_cf_cpl~5_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~6 .lut_mask = 16'hFDA8; +defparam \z80_|execute_|ctl_flags_cf_cpl~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~7_combout = (\z80_|execute_|ctl_flags_cf_cpl~6_combout ) # ((\z80_|pla_decode_|Equal9~0_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal62~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~0_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|pla_decode_|Equal62~2_combout ), + .datad(\z80_|execute_|ctl_flags_cf_cpl~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~7 .lut_mask = 16'hFF20; +defparam \z80_|execute_|ctl_flags_cf_cpl~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y20_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~10_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ) # ((!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|execute_|ctl_alu_op_low~25_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|execute_|ctl_alu_op_low~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~10 .lut_mask = 16'hDCCC; +defparam \z80_|execute_|ctl_flags_cf_cpl~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y20_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~8_combout = (\z80_|execute_|ctl_flags_cf_cpl~10_combout ) # ((\z80_|execute_|ctl_alu_op_low~34_combout & (\z80_|execute_|ctl_alu_op_low~25_combout & \z80_|execute_|ctl_alu_op_low~22_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~34_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~25_combout ), + .datac(\z80_|execute_|ctl_flags_cf_cpl~10_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~8 .lut_mask = 16'hF8F0; +defparam \z80_|execute_|ctl_flags_cf_cpl~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ixy_d~7_combout & (!\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y20_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~42 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~42_combout = (\z80_|execute_|ctl_alu_op_low~34_combout ) # (!\z80_|execute_|ctl_alu_op_low~48_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op_low~48_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~42 .lut_mask = 16'hFF0F; +defparam \z80_|execute_|ctl_alu_op_low~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y20_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~9 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~9_combout = (\z80_|execute_|ctl_flags_cf_cpl~7_combout ) # ((\z80_|execute_|ctl_flags_cf_cpl~8_combout ) # ((\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout & \z80_|execute_|ctl_alu_op_low~42_combout ))) + + .dataa(\z80_|execute_|ctl_flags_cf_cpl~7_combout ), + .datab(\z80_|execute_|ctl_flags_cf_cpl~8_combout ), + .datac(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), + .datad(\z80_|execute_|ctl_alu_op_low~42_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~9 .lut_mask = 16'hFEEE; +defparam \z80_|execute_|ctl_flags_cf_cpl~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y17_N12 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout = (\z80_|execute_|ctl_alu_op_low~40_combout & (\z80_|pla_decode_|Equal21~1_combout & ((\z80_|execute_|ixy_d~6_combout ) # (\z80_|execute_|ctl_mRead~9_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~40_combout ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ctl_mRead~9_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 .lut_mask = 16'h8880; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y20_N24 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout = ((!\z80_|pla_decode_|Equal39~0_combout & ((!\z80_|pla_decode_|Equal40~2_combout ) # (!\z80_|ir_|opcode [5])))) # (!\z80_|execute_|ixy_d~6_combout ) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal40~2_combout ), + .datad(\z80_|pla_decode_|Equal39~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 .lut_mask = 16'h557F; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y20_N22 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout = (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout & ((\z80_|execute_|ctl_alu_op_low~37_combout ) # (\z80_|execute_|ctl_alu_op_low~38_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~37_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~38_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 .lut_mask = 16'h3232; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~18 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~18_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|pla_decode_|Equal11~0_combout & \z80_|sequencer_|DFFE_T3_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~18 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_mWrite~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N14 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1_combout = (!\z80_|execute_|ctl_mWrite~18_combout & (((!\z80_|execute_|ctl_mWrite~17_combout & !\z80_|pla_decode_|Equal61~2_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~17_combout ), + .datab(\z80_|pla_decode_|Equal61~2_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_mWrite~18_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1 .lut_mask = 16'h001F; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y20_N16 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2_combout = (\z80_|nM1_int~2_combout & (!\z80_|execute_|ctl_mRead~34_combout & ((!\z80_|pla_decode_|Equal56~0_combout ) # (!\z80_|execute_|ctl_state_alu~3_combout )))) # (!\z80_|nM1_int~2_combout & +// (((!\z80_|pla_decode_|Equal56~0_combout ) # (!\z80_|execute_|ctl_state_alu~3_combout )))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|execute_|ctl_state_alu~3_combout ), + .datad(\z80_|pla_decode_|Equal56~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2 .lut_mask = 16'h0777; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y20_N10 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3_combout = (\z80_|execute_|ctl_alu_core_R~4_combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~1_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_R~4_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~1_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~2_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3 .lut_mask = 16'h8000; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y20_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~2_combout = (\z80_|execute_|ctl_alu_op_low~37_combout & (((\z80_|execute_|ctl_mRead~34_combout & \z80_|execute_|ixy_d~6_combout )) # (!\z80_|execute_|ctl_alu_oe~4_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~37_combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ctl_alu_oe~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~2 .lut_mask = 16'h80AA; +defparam \z80_|execute_|ctl_flags_cf_cpl~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y20_N2 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~3_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~13_combout & (\z80_|execute_|ctl_alu_core_S~7_combout & !\z80_|execute_|ctl_alu_core_R~1_combout ))) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), + .datac(\z80_|execute_|ctl_alu_core_S~7_combout ), + .datad(\z80_|execute_|ctl_alu_core_R~1_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'h0080; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y20_N6 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~3_combout & (!\z80_|execute_|ctl_flags_cf_cpl~2_combout & (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0_combout ))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~3_combout ), + .datab(\z80_|execute_|ctl_flags_cf_cpl~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 .lut_mask = 16'h0200; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y20_N12 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout = (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout & (\z80_|execute_|ctl_flags_nf_we~1_combout & (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ), + .datab(\z80_|execute_|ctl_flags_nf_we~1_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 .lut_mask = 16'h0400; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_we~4_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & ((\z80_|pla_decode_|Equal11~0_combout ) # (\z80_|pla_decode_|Equal10~0_combout )))) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|pla_decode_|Equal10~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_we~4 .lut_mask = 16'h8880; +defparam \z80_|execute_|ctl_flags_cf2_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y18_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_we~2_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~38_combout ) # (!\z80_|execute_|ctl_alu_op1_sel_bus~8_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~38_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_we~2 .lut_mask = 16'hCFFF; +defparam \z80_|execute_|ctl_flags_cf2_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_we~3_combout = (\z80_|execute_|ctl_flags_cf2_we~4_combout ) # ((\z80_|execute_|ctl_flags_cf2_we~2_combout ) # ((\z80_|execute_|ixy_d~15_combout & \z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(\z80_|execute_|ctl_flags_cf2_we~4_combout ), + .datab(\z80_|execute_|ixy_d~15_combout ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|execute_|ctl_flags_cf2_we~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_we~3 .lut_mask = 16'hFFEA; +defparam \z80_|execute_|ctl_flags_cf2_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y15_N13 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N8 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_32 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_32~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout & \z80_|reg_control_|reg_sel_af~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_32~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_32 .lut_mask = 16'h4400; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y15_N21 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X35_Y15_N27 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~81 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~81_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (\z80_|reg_file_|b2v_latch_wz_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (((\z80_|reg_file_|b2v_latch_sp_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .datab(\z80_|reg_file_|b2v_latch_wz_hi|latch [6]), + .datac(\z80_|reg_file_|b2v_latch_sp_hi|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~81_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~81 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[6]~81 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N22 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~8 ( +// Equation(s): +// \z80_|alu_|db_high[2]~8_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[7]~12_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[5]~24_combout )) + + .dataa(gnd), + .datab(\z80_|alu_|db[5]~24_combout ), + .datac(\z80_|alu_|db[7]~12_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|alu_|db_high[2]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[2]~8 .lut_mask = 16'hF0CC; +defparam \z80_|alu_|db_high[2]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N28 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~9 ( +// Equation(s): +// \z80_|alu_|db_high[2]~9_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_high[2]~8_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[6]~22_combout ))) # +// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) + + .dataa(\z80_|alu_|db[6]~22_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datac(\z80_|alu_|db_high[2]~8_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[2]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[2]~9 .lut_mask = 16'hF3BB; +defparam \z80_|alu_|db_high[2]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N14 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~11 ( +// Equation(s): +// \z80_|alu_|db_high[2]~11_combout = (\z80_|bus_control_|db[4]~19_combout & (!\z80_|bus_control_|db[3]~21_combout & \z80_|bus_control_|db[5]~15_combout )) + + .dataa(gnd), + .datab(\z80_|bus_control_|db[4]~19_combout ), + .datac(\z80_|bus_control_|db[3]~21_combout ), + .datad(\z80_|bus_control_|db[5]~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[2]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[2]~11 .lut_mask = 16'h0C00; +defparam \z80_|alu_|db_high[2]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N18 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[2] ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_high|Q [2] = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & (\z80_|alu_|db_high[2]~13_combout & \z80_|execute_|ctl_alu_op1_sel_bus~15_combout )) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .datab(gnd), + .datac(\z80_|alu_|db_high[2]~13_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [2]), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[2] .lut_mask = 16'h5000; +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y17_N19 +dffeas \z80_|alu_|op1_high[2] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [2]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_high [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_high[2] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_high[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_lq ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_lq~combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ixy_d~7_combout ) # ((\z80_|execute_|ixy_d~6_combout & !\z80_|ir_|opcode [3])))) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_lq .lut_mask = 16'h88A8; +defparam \z80_|execute_|ctl_alu_op2_sel_lq .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N6 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & \z80_|alu_|db_low[2]~23_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datad(\z80_|alu_|db_low[2]~23_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2 .lut_mask = 16'hF000; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~5_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|execute_|ctl_alu_core_R~0_combout & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T3_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datad(\z80_|execute_|ctl_alu_core_R~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~5 .lut_mask = 16'hFEF0; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~6_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~5_combout ) # ((\z80_|execute_|ctl_alu_op_low~47_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~14_combout & \z80_|pla_decode_|Equal13~2_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~5_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~47_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~6 .lut_mask = 16'hFFEA; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~7_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~4_combout & (\z80_|execute_|ctl_reg_use_sp~0_combout & \z80_|execute_|nextM~11_combout )) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_use_sp~0_combout ), + .datad(\z80_|execute_|nextM~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~7 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~8_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ) # (((!\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ) # (!\z80_|execute_|ctl_alu_op1_sel_bus~14_combout )) # (!\z80_|execute_|ctl_alu_op2_sel_bus~10_combout )) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~8 .lut_mask = 16'hBFFF; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y19_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_zero ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_zero~combout = (((\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ) # (!\z80_|execute_|ctl_alu_shift_oe~38_combout )) # (!\z80_|execute_|ctl_reg_out_hi~4_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ), + .datab(\z80_|execute_|ctl_reg_out_hi~4_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~38_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_zero .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_alu_op2_sel_zero .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N10 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2_combout ) # ((\z80_|alu_|db_high[2]~13_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) + + .dataa(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2_combout ), + .datab(\z80_|alu_|db_high[2]~13_combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 .lut_mask = 16'h00EA; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N0 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|ena ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|ena~combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout ) # ((\z80_|execute_|ctl_alu_op2_sel_zero~combout ) # (\z80_|execute_|ctl_alu_op2_sel_bus~8_combout )) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|ena .lut_mask = 16'hFEFE; +defparam \z80_|alu_|b2v_op2_latch_mux_high|ena .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y18_N11 +dffeas \z80_|alu_|op2_high[2] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_high [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_high[2] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_high[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N28 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~10 ( +// Equation(s): +// \z80_|alu_|db_high[2]~10_combout = (\z80_|alu_|op1_high [2] & (((\z80_|alu_|op2_high [2]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|alu_|op1_high [2] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_high [2]) # +// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) + + .dataa(\z80_|alu_|op1_high [2]), + .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datac(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datad(\z80_|alu_|op2_high [2]), + .cin(gnd), + .combout(\z80_|alu_|db_high[2]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[2]~10 .lut_mask = 16'hBB0B; +defparam \z80_|alu_|db_high[2]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N16 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~12 ( +// Equation(s): +// \z80_|alu_|db_high[2]~12_combout = (\z80_|alu_|db_high[2]~9_combout & (\z80_|alu_|db_high[2]~10_combout & ((\z80_|alu_|db_high[2]~11_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~combout )))) + + .dataa(\z80_|alu_|db_high[2]~9_combout ), + .datab(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datac(\z80_|alu_|db_high[2]~11_combout ), + .datad(\z80_|alu_|db_high[2]~10_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[2]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[2]~12 .lut_mask = 16'hA200; +defparam \z80_|alu_|db_high[2]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N6 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~1 ( +// Equation(s): +// \z80_|alu_|db_high[3]~1_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout ) # (\z80_|alu_|db_high[3]~0_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datac(gnd), + .datad(\z80_|alu_|db_high[3]~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~1 .lut_mask = 16'hFFCC; +defparam \z80_|alu_|db_high[3]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N0 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~13 ( +// Equation(s): +// \z80_|alu_|db_high[2]~13_combout = ((\z80_|alu_|db_high[2]~12_combout & ((\z80_|execute_|ctl_alu_res_oe~3_combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout )))) # (!\z80_|alu_|db_high[3]~1_combout ) + + .dataa(\z80_|execute_|ctl_alu_res_oe~3_combout ), + .datab(\z80_|alu_|db_high[2]~12_combout ), + .datac(\z80_|alu_|db_high[3]~1_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[2]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[2]~13 .lut_mask = 16'hCF8F; +defparam \z80_|alu_|db_high[2]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y12_N29 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X31_Y12_N19 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~78 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~78_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (\z80_|reg_file_|b2v_latch_ix_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [6]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_iy_lo|latch [6]), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~78_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~78 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[6]~78 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N26 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout = (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & \z80_|execute_|ctl_reg_gp_sel[1]~31_combout ))) + + .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y12_N5 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~79 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~79_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [6] & ((\z80_|alu_control_|db[6]~22_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|alu_control_|db[6]~22_combout ) # ((!\z80_|execute_|ctl_reg_in_lo~8_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datab(\z80_|alu_control_|db[6]~22_combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [6]), + .datad(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~79_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~79 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[6]~79 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N10 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_34 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_34~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_af~0_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~35_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(gnd), + .datac(\z80_|reg_control_|reg_sel_af~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_34 .lut_mask = 16'h5000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N18 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder_combout = \z80_|reg_file_|gdfx_temp0[6]~82_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N0 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_35 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_35~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_af~0_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~35_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(gnd), + .datac(\z80_|reg_control_|reg_sel_af~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_35 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y13_N19 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N14 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_31 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_31~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout & \z80_|reg_control_|reg_sel_af2~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .datac(\z80_|reg_control_|reg_sel_af2~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_31 .lut_mask = 16'h8080; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y13_N21 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N28 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_30 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_30~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout & \z80_|reg_control_|reg_sel_af2~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .datac(\z80_|reg_control_|reg_sel_af2~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_30 .lut_mask = 16'h4040; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~75 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~75_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (\z80_|reg_file_|b2v_latch_af_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_af2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (((\z80_|reg_file_|b2v_latch_af2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datab(\z80_|reg_file_|b2v_latch_af_lo|latch [6]), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~75_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~75 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp0[6]~75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N20 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder_combout = \z80_|reg_file_|gdfx_temp0[6]~82_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y14_N21 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X32_Y14_N31 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~76 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~76_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [6]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [6]), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~76_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~76 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[6]~76 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y13_N21 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~77 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~77_combout = (\z80_|reg_file_|gdfx_temp0[6]~76_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[6]~76_combout ), + .datab(gnd), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~77_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~77 .lut_mask = 16'hA0AA; +defparam \z80_|reg_file_|gdfx_temp0[6]~77 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~80 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~80_combout = (\z80_|reg_file_|gdfx_temp0[6]~78_combout & (\z80_|reg_file_|gdfx_temp0[6]~79_combout & (\z80_|reg_file_|gdfx_temp0[6]~75_combout & \z80_|reg_file_|gdfx_temp0[6]~77_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[6]~78_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[6]~79_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[6]~75_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[6]~77_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~80 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[6]~80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y12_N1 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y12_N3 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~74 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~74_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (\z80_|reg_file_|b2v_latch_hl_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl_lo|latch [6]), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~74_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~74 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp0[6]~74 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y11_N13 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y11_N11 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~73 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~73_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [6] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [6] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [6]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~73_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~73 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp0[6]~73 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~81 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~81_combout = (\z80_|reg_file_|gdfx_temp0[6]~80_combout & (\z80_|reg_file_|gdfx_temp0[6]~74_combout & \z80_|reg_file_|gdfx_temp0[6]~73_combout )) + + .dataa(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[6]~74_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[6]~73_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~81_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~81 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|gdfx_temp0[6]~81 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~19 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~19_combout = (\z80_|execute_|ctl_sw_4u~6_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ) # (\z80_|execute_|ctl_reg_in_lo~8_combout ))) + + .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datad(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~19 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp0[0]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~18 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~18_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~18 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp0[0]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~20 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~20_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ) # ((\z80_|reg_file_|gdfx_temp0[0]~19_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ) # (\z80_|reg_file_|gdfx_temp0[0]~18_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~19_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~18_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~20 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp0[0]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~92 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~92_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout & (!\z80_|execute_|ctl_reg_gp_we~8_combout & ((\z80_|reg_control_|reg_sel_hl2~0_combout ) # (\z80_|reg_control_|reg_sel_hl~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .datab(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~92_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~92 .lut_mask = 16'h0A08; +defparam \z80_|reg_file_|gdfx_temp0[0]~92 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~21 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~21_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ) # ((\z80_|reg_file_|gdfx_temp0[0]~20_combout ) # (\z80_|reg_file_|gdfx_temp0[0]~92_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datac(\z80_|reg_file_|gdfx_temp0[0]~20_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~92_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~21 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp0[0]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N4 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_74 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_74~combout = (\z80_|reg_control_|reg_sel_pc~combout & (!\z80_|reg_control_|reg_sys_we_lo~combout & \z80_|execute_|ctl_reg_sys_hilo[0]~31_combout )) + + .dataa(\z80_|reg_control_|reg_sel_pc~combout ), + .datab(gnd), + .datac(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_74 .lut_mask = 16'h0A00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_74 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N6 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_62 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_62~combout = (\z80_|execute_|ctl_reg_sys_hilo[0]~31_combout & (!\z80_|reg_control_|reg_sys_we_lo~combout & \z80_|execute_|ctl_reg_sel_ir~1_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~31_combout ), + .datac(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datad(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_62 .lut_mask = 16'h0C00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N26 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~2 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[0]~2_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ) # ((\z80_|execute_|ctl_sw_4d~6_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~43_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .datab(\z80_|execute_|ctl_sw_4d~6_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[0]~2 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|db_lo_as[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y12_N13 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[4]~15_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X31_Y12_N9 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X32_Y12_N3 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~55 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~55_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_sp_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_iy_lo|latch [4]), + .datad(\z80_|reg_file_|b2v_latch_sp_lo|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~55_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~55 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[4]~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y12_N23 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~56 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~56_combout = (\z80_|reg_file_|gdfx_temp0[4]~55_combout & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|gdfx_temp0[4]~55_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~56_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~56 .lut_mask = 16'hC0CC; +defparam \z80_|reg_file_|gdfx_temp0[4]~56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y12_N13 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y12_N23 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~57 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~57_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [4] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [4] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [4]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~57_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~57 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp0[4]~57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y14_N5 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X32_Y14_N11 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~59 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~59_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [4]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [4]), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~59_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~59 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[4]~59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y13_N17 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X31_Y13_N31 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~58 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~58_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (\z80_|reg_file_|b2v_latch_af_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_af2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (((\z80_|reg_file_|b2v_latch_af2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datab(\z80_|reg_file_|b2v_latch_af_lo|latch [4]), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~58_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~58 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp0[4]~58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y13_N1 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~60 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~60_combout = (\z80_|reg_file_|gdfx_temp0[4]~59_combout & (\z80_|reg_file_|gdfx_temp0[4]~58_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp0[4]~59_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[4]~58_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~60_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~60 .lut_mask = 16'h8088; +defparam \z80_|reg_file_|gdfx_temp0[4]~60 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y11_N23 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X31_Y11_N17 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~53 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~53_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [4]), + .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~53_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~53 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[4]~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~54 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~54_combout = (\z80_|reg_file_|gdfx_temp0[4]~53_combout & ((\z80_|alu_control_|db[4]~32_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datab(gnd), + .datac(\z80_|alu_control_|db[4]~32_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[4]~53_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~54_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~54 .lut_mask = 16'hF500; +defparam \z80_|reg_file_|gdfx_temp0[4]~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~61 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~61_combout = (\z80_|reg_file_|gdfx_temp0[4]~56_combout & (\z80_|reg_file_|gdfx_temp0[4]~57_combout & (\z80_|reg_file_|gdfx_temp0[4]~60_combout & \z80_|reg_file_|gdfx_temp0[4]~54_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[4]~56_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[4]~57_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[4]~60_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[4]~54_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~61 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[4]~61 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~62 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~62_combout = ((\z80_|reg_file_|gdfx_temp0[4]~61_combout & ((\z80_|reg_file_|db_lo_as[4]~15_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .datac(\z80_|execute_|ctl_sw_4u~6_combout ), + .datad(\z80_|reg_file_|db_lo_as[4]~15_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~62 .lut_mask = 16'hBB3B; +defparam \z80_|reg_file_|gdfx_temp0[4]~62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N10 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_75 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_75~combout = (\z80_|reg_control_|reg_sel_pc~combout & (\z80_|reg_control_|reg_sys_we_lo~combout & \z80_|execute_|ctl_reg_sys_hilo[0]~31_combout )) + + .dataa(\z80_|reg_control_|reg_sel_pc~combout ), + .datab(gnd), + .datac(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_75 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y12_N3 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[4]~15_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N2 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~13 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[4]~13_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[4]~62_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # +// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[4]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[4]~13 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_lo_as[4]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N18 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~14 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[4]~14_combout = (\z80_|reg_file_|db_lo_as[4]~13_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_ir_lo|latch [4]), + .datab(\z80_|reg_file_|db_lo_as[4]~13_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[4]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[4]~14 .lut_mask = 16'h88CC; +defparam \z80_|reg_file_|db_lo_as[4]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N16 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout = \z80_|address_latch_|Q [4] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|address_latch_|Q [4]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out .lut_mask = 16'h0FF0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N12 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~15 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[4]~15_combout = ((\z80_|reg_file_|db_lo_as[4]~14_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .datab(\z80_|reg_file_|db_lo_as[4]~14_combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), + .datad(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[4]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[4]~15 .lut_mask = 16'hC4FF; +defparam \z80_|reg_file_|db_lo_as[4]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N12 +cycloneive_lcell_comb \z80_|address_latch_|abusz[4] ( +// Equation(s): +// \z80_|address_latch_|abusz [4] = (\z80_|reg_file_|db_lo_as[4]~15_combout & !\z80_|resets_|clrpc~0_combout ) + + .dataa(gnd), + .datab(\z80_|reg_file_|db_lo_as[4]~15_combout ), + .datac(gnd), + .datad(\z80_|resets_|clrpc~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [4]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[4] .lut_mask = 16'h00CC; +defparam \z80_|address_latch_|abusz[4] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y10_N13 +dffeas \z80_|address_latch_|Q[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [4]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[4] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N20 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout = \z80_|address_latch_|Q [5] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout & (\z80_|execute_|ctl_inc_dec~11_combout $ (\z80_|address_latch_|Q +// [4]))))) + + .dataa(\z80_|execute_|ctl_inc_dec~11_combout ), + .datab(\z80_|address_latch_|Q [4]), + .datac(\z80_|address_latch_|Q [5]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out .lut_mask = 16'h96F0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y12_N29 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[5]~18_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y12_N17 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y12_N15 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~64 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~64_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [5] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [5] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [5]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~64_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~64 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp0[5]~64 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y11_N27 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X31_Y11_N25 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~63 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~63_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [5]), + .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [5]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~63_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~63 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[5]~63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y11_N17 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N18 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[5]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_lo|latch[5]~feeder_combout = \z80_|reg_file_|gdfx_temp0[5]~72_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[5]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y11_N19 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_af_lo|latch[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~65 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~65_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [5]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [5]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~65_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~65 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[5]~65 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y12_N21 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X32_Y12_N23 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~69 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~69_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [5]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_iy_lo|latch [5]), + .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~69_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~69 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[5]~69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y13_N29 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X32_Y14_N27 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~68 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~68_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (\z80_|reg_file_|b2v_latch_ix_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_ix_lo|latch [5]), + .datac(\z80_|reg_file_|b2v_latch_bc_lo|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~68_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~68 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp0[5]~68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y13_N3 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X32_Y14_N17 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~66 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~66_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [5] & ((\z80_|alu_control_|db[5]~15_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|alu_control_|db[5]~15_combout ) # ((!\z80_|execute_|ctl_reg_in_lo~8_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datab(\z80_|alu_control_|db[5]~15_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [5]), + .datad(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~66_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~66 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[5]~66 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~67 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~67_combout = (\z80_|reg_file_|gdfx_temp0[5]~66_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [5]), + .datad(\z80_|reg_file_|gdfx_temp0[5]~66_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~67_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~67 .lut_mask = 16'hF300; +defparam \z80_|reg_file_|gdfx_temp0[5]~67 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~70 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~70_combout = (\z80_|reg_file_|gdfx_temp0[5]~65_combout & (\z80_|reg_file_|gdfx_temp0[5]~69_combout & (\z80_|reg_file_|gdfx_temp0[5]~68_combout & \z80_|reg_file_|gdfx_temp0[5]~67_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[5]~65_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[5]~69_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[5]~68_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[5]~67_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~70_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~70 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[5]~70 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~71 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~71_combout = (\z80_|reg_file_|gdfx_temp0[5]~64_combout & (\z80_|reg_file_|gdfx_temp0[5]~63_combout & \z80_|reg_file_|gdfx_temp0[5]~70_combout )) + + .dataa(\z80_|reg_file_|gdfx_temp0[5]~64_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[5]~63_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[5]~70_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~71 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|gdfx_temp0[5]~71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~72 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~72_combout = ((\z80_|reg_file_|gdfx_temp0[5]~71_combout & ((\z80_|reg_file_|db_lo_as[5]~18_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), + .datab(\z80_|reg_file_|db_lo_as[5]~18_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .datad(\z80_|execute_|ctl_sw_4u~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~72 .lut_mask = 16'h8FAF; +defparam \z80_|reg_file_|gdfx_temp0[5]~72 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y12_N7 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[5]~18_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N6 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~16 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[5]~16_combout = (\z80_|reg_file_|gdfx_temp0[5]~72_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # (!\z80_|reg_file_|gdfx_temp0[5]~72_combout & +// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .datab(\z80_|execute_|ctl_sw_4d~6_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[5]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[5]~16 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|db_lo_as[5]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N14 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~17 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[5]~17_combout = (\z80_|reg_file_|db_lo_as[5]~16_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|b2v_latch_ir_lo|latch [5]), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .datad(\z80_|reg_file_|db_lo_as[5]~16_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[5]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[5]~17 .lut_mask = 16'hCF00; +defparam \z80_|reg_file_|db_lo_as[5]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N28 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~18 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[5]~18_combout = ((\z80_|reg_file_|db_lo_as[5]~17_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), + .datac(\z80_|reg_file_|db_lo_as[5]~17_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[5]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[5]~18 .lut_mask = 16'hD5F5; +defparam \z80_|reg_file_|db_lo_as[5]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N8 +cycloneive_lcell_comb \z80_|address_latch_|abusz[5] ( +// Equation(s): +// \z80_|address_latch_|abusz [5] = (\z80_|reg_file_|db_lo_as[5]~18_combout & !\z80_|resets_|clrpc~0_combout ) + + .dataa(gnd), + .datab(\z80_|reg_file_|db_lo_as[5]~18_combout ), + .datac(gnd), + .datad(\z80_|resets_|clrpc~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [5]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[5] .lut_mask = 16'h00CC; +defparam \z80_|address_latch_|abusz[5] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y10_N9 +dffeas \z80_|address_latch_|Q[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [5]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[5] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~10 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~10_combout = (\z80_|execute_|ctl_inc_dec~9_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_inc_dec~6_combout ), + .datad(\z80_|execute_|ctl_inc_dec~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~10 .lut_mask = 16'hFF0F; +defparam \z80_|execute_|ctl_inc_dec~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N30 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout = \z80_|address_latch_|Q [5] $ ((((\z80_|execute_|ctl_inc_dec~10_combout ) # (!\z80_|execute_|ctl_inc_dec~5_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~42_combout ))) + + .dataa(\z80_|address_latch_|Q [5]), + .datab(\z80_|execute_|ctl_bus_inc_oe~42_combout ), + .datac(\z80_|execute_|ctl_inc_dec~10_combout ), + .datad(\z80_|execute_|ctl_inc_dec~5_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4 .lut_mask = 16'h5955; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N8 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout = \z80_|address_latch_|Q [4] $ ((((\z80_|execute_|ctl_inc_dec~10_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~42_combout )) # (!\z80_|execute_|ctl_inc_dec~5_combout ))) + + .dataa(\z80_|execute_|ctl_inc_dec~5_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~42_combout ), + .datac(\z80_|execute_|ctl_inc_dec~10_combout ), + .datad(\z80_|address_latch_|Q [4]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 .lut_mask = 16'h08F7; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N20 +cycloneive_lcell_comb \z80_|address_latch_|abusz[6] ( +// Equation(s): +// \z80_|address_latch_|abusz [6] = (\z80_|reg_file_|db_lo_as[6]~21_combout & !\z80_|resets_|clrpc~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|reg_file_|db_lo_as[6]~21_combout ), + .datad(\z80_|resets_|clrpc~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [6]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[6] .lut_mask = 16'h00F0; +defparam \z80_|address_latch_|abusz[6] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y10_N21 +dffeas \z80_|address_latch_|Q[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [6]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[6] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N20 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[6] ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|address [6] = \z80_|address_latch_|Q [6] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout & +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout )))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), + .datac(\z80_|address_latch_|Q [6]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[6] .lut_mask = 16'h78F0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[6] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y12_N25 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[6]~21_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X36_Y12_N11 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[6]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N10 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~19 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[6]~19_combout = (\z80_|reg_file_|gdfx_temp0[6]~82_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # (!\z80_|reg_file_|gdfx_temp0[6]~82_combout & +// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .datab(\z80_|execute_|ctl_sw_4d~6_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[6]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[6]~19 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|db_lo_as[6]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N22 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~20 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[6]~20_combout = (\z80_|reg_file_|db_lo_as[6]~19_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|b2v_latch_ir_lo|latch [6]), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .datad(\z80_|reg_file_|db_lo_as[6]~19_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[6]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[6]~20 .lut_mask = 16'hCF00; +defparam \z80_|reg_file_|db_lo_as[6]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N24 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~21 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[6]~21_combout = ((\z80_|reg_file_|db_lo_as[6]~20_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [6]) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), + .datac(\z80_|reg_file_|db_lo_as[6]~20_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[6]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[6]~21 .lut_mask = 16'hD5F5; +defparam \z80_|reg_file_|db_lo_as[6]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~82 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~82_combout = ((\z80_|reg_file_|gdfx_temp0[6]~81_combout & ((\z80_|reg_file_|db_lo_as[6]~21_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[6]~81_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .datad(\z80_|reg_file_|db_lo_as[6]~21_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~82 .lut_mask = 16'hCF4F; +defparam \z80_|reg_file_|gdfx_temp0[6]~82 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N10 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[6]~0 ( +// Equation(s): +// \z80_|reg_file_|db_lo_ds[6]~0_combout = (\z80_|reg_file_|gdfx_temp0[6]~82_combout ) # ((!\z80_|execute_|ctl_reg_out_lo~5_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout & \z80_|execute_|ctl_reg_out_lo~7_combout ))) + + .dataa(\z80_|execute_|ctl_reg_out_lo~5_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_ds[6]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_ds[6]~0 .lut_mask = 16'hFF40; +defparam \z80_|reg_file_|db_lo_ds[6]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N28 +cycloneive_lcell_comb \z80_|sw1_|db_down[6]~1 ( +// Equation(s): +// \z80_|sw1_|db_down[6]~1_combout = ((\z80_|bus_control_|db[6]~9_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ) + + .dataa(gnd), + .datab(\z80_|bus_control_|db[6]~9_combout ), + .datac(\z80_|execute_|ctl_sw_1d~7_combout ), + .datad(\z80_|execute_|ctl_sw_mask543_en~0_combout ), + .cin(gnd), + .combout(\z80_|sw1_|db_down[6]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sw1_|db_down[6]~1 .lut_mask = 16'h0FCF; +defparam \z80_|sw1_|db_down[6]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_66_oe ( +// Equation(s): +// \z80_|execute_|ctl_66_oe~combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & \z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(\z80_|pla_decode_|Equal47~0_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_66_oe~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_66_oe .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_66_oe .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N24 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[1] ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_high|Q [1] = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & \z80_|alu_|db_high[1]~19_combout )) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .datad(\z80_|alu_|db_high[1]~19_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [1]), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[1] .lut_mask = 16'h0A00; +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[1] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y17_N25 +dffeas \z80_|alu_|op1_high[1] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [1]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_high [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_high[1] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_high[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N8 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~4 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~4_combout = (\z80_|alu_|db_low[1]~12_combout & \z80_|execute_|ctl_alu_op2_sel_lq~combout ) + + .dataa(gnd), + .datab(\z80_|alu_|db_low[1]~12_combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~4 .lut_mask = 16'hC0C0; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N16 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~4_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~8_combout & \z80_|alu_|db_high[1]~19_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .datab(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~4_combout ), + .datac(\z80_|alu_|db_high[1]~19_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5 .lut_mask = 16'h00EC; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y18_N17 +dffeas \z80_|alu_|op2_high[1] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_high [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_high[1] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_high[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N18 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~2 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~2_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [1]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [1])))) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datab(\z80_|alu_|op1_high [1]), + .datac(\z80_|execute_|ctl_alu_op_low~combout ), + .datad(\z80_|alu_|op1_low [1]), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~2 .lut_mask = 16'hA808; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N14 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~3 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~3_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~2_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~8_combout & \z80_|alu_|db_low[1]~12_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datac(\z80_|alu_|db_low[1]~12_combout ), + .datad(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~3 .lut_mask = 16'h3320; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y18_N15 +dffeas \z80_|alu_|op2_low[1] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_low [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_low[1] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_low[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N16 +cycloneive_lcell_comb \z80_|alu_|alu_op2[1]~1 ( +// Equation(s): +// \z80_|alu_|alu_op2[1]~1_combout = \z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_high [1])) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_low [1]))))) + + .dataa(\z80_|alu_|op2_high [1]), + .datab(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), + .datad(\z80_|alu_|op2_low [1]), + .cin(gnd), + .combout(\z80_|alu_|alu_op2[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op2[1]~1 .lut_mask = 16'h4B78; +defparam \z80_|alu_|alu_op2[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N0 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout = (!\z80_|alu_|alu_op2[1]~1_combout & ((\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_low [1])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_high +// [1]))))) + + .dataa(\z80_|alu_|op1_low [1]), + .datab(\z80_|alu_|op1_high [1]), + .datac(\z80_|execute_|ctl_alu_op_low~combout ), + .datad(\z80_|alu_|alu_op2[1]~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'h0053; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N30 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout = (\z80_|alu_|alu_op2[1]~1_combout & ((\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [1])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [1]))))) + + .dataa(\z80_|alu_|op1_low [1]), + .datab(\z80_|alu_|op1_high [1]), + .datac(\z80_|execute_|ctl_alu_op_low~combout ), + .datad(\z80_|alu_|alu_op2[1]~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0 .lut_mask = 16'hAC00; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N14 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout = (\z80_|execute_|ctl_alu_core_S~combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_core_S~combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'hFFF0; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y20_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~5_combout = (\z80_|execute_|ctl_alu_core_S~8_combout & (\z80_|execute_|ctl_alu_core_R~4_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout & !\z80_|pla_decode_|Equal72~2_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_S~8_combout ), + .datab(\z80_|execute_|ctl_alu_core_R~4_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ), + .datad(\z80_|pla_decode_|Equal72~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~5 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_alu_core_R~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~2 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~2_combout = (\z80_|execute_|ctl_mWrite~4_combout & (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal8~0_combout ) # (\z80_|pla_decode_|Equal55~0_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~4_combout ), + .datab(\z80_|pla_decode_|Equal8~0_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~2 .lut_mask = 16'hA080; +defparam \z80_|execute_|ctl_alu_core_R~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y20_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~combout = (((\z80_|pla_decode_|Equal73~2_combout ) # (\z80_|execute_|ctl_alu_core_R~2_combout )) # (!\z80_|execute_|ctl_alu_core_S~9_combout )) # (!\z80_|execute_|ctl_alu_core_R~4_combout ) + + .dataa(\z80_|execute_|ctl_alu_core_R~4_combout ), + .datab(\z80_|execute_|ctl_alu_core_S~9_combout ), + .datac(\z80_|pla_decode_|Equal73~2_combout ), + .datad(\z80_|execute_|ctl_alu_core_R~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R .lut_mask = 16'hFFF7; +defparam \z80_|execute_|ctl_alu_core_R .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N8 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~20 ( +// Equation(s): +// \z80_|alu_|db_high[0]~20_combout = ((!\z80_|bus_control_|db[3]~21_combout & (\z80_|bus_control_|db[5]~15_combout & !\z80_|bus_control_|db[4]~19_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) + + .dataa(\z80_|bus_control_|db[3]~21_combout ), + .datab(\z80_|bus_control_|db[5]~15_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datad(\z80_|bus_control_|db[4]~19_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~20 .lut_mask = 16'h0F4F; +defparam \z80_|alu_|db_high[0]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N26 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[0] ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_high|Q [0] = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & \z80_|alu_|db_high[0]~25_combout )) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .datad(\z80_|alu_|db_high[0]~25_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [0]), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[0] .lut_mask = 16'h0A00; +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[0] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y17_N27 +dffeas \z80_|alu_|op1_high[0] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [0]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_high [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_high[0] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_high[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N30 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~21 ( +// Equation(s): +// \z80_|alu_|db_high[0]~21_combout = (\z80_|execute_|ctl_alu_op1_oe~1_combout & (\z80_|alu_|op1_high [0] & ((\z80_|alu_|op2_high [0]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout & (((\z80_|alu_|op2_high +// [0]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datab(\z80_|alu_|op1_high [0]), + .datac(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datad(\z80_|alu_|op2_high [0]), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~21 .lut_mask = 16'hDD0D; +defparam \z80_|alu_|db_high[0]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N2 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~22 ( +// Equation(s): +// \z80_|alu_|db_high[0]~22_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[5]~24_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[3]~20_combout )) + + .dataa(gnd), + .datab(\z80_|alu_|db[3]~20_combout ), + .datac(\z80_|alu_|db[5]~24_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~22 .lut_mask = 16'hF0CC; +defparam \z80_|alu_|db_high[0]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N20 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~23 ( +// Equation(s): +// \z80_|alu_|db_high[0]~23_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_high[0]~22_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[4]~18_combout )) + + .dataa(\z80_|alu_|db[4]~18_combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .datac(gnd), + .datad(\z80_|alu_|db_high[0]~22_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~23 .lut_mask = 16'hEE22; +defparam \z80_|alu_|db_high[0]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N26 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~24 ( +// Equation(s): +// \z80_|alu_|db_high[0]~24_combout = (\z80_|alu_|db_high[0]~20_combout & (\z80_|alu_|db_high[0]~21_combout & ((\z80_|alu_|db_high[0]~23_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) + + .dataa(\z80_|alu_|db_high[0]~20_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datac(\z80_|alu_|db_high[0]~21_combout ), + .datad(\z80_|alu_|db_high[0]~23_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~24 .lut_mask = 16'hA020; +defparam \z80_|alu_|db_high[0]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N4 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~4 ( +// Equation(s): +// \z80_|alu_|db_low[0]~4_combout = ((!\z80_|bus_control_|db[3]~21_combout & (!\z80_|bus_control_|db[5]~15_combout & !\z80_|bus_control_|db[4]~19_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) + + .dataa(\z80_|bus_control_|db[3]~21_combout ), + .datab(\z80_|bus_control_|db[5]~15_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datad(\z80_|bus_control_|db[4]~19_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~4 .lut_mask = 16'h0F1F; +defparam \z80_|alu_|db_low[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y18_N27 +dffeas \z80_|alu_|result_lo[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_alu_op_low~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|result_lo [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|result_lo[0] .is_wysiwyg = "true"; +defparam \z80_|alu_|result_lo[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N20 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~2 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~2_combout = (\z80_|alu_|db_low[0]~24_combout & ((\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ) # ((\z80_|alu_|db_high[0]~25_combout & \z80_|execute_|ctl_alu_op1_sel_low~combout )))) # +// (!\z80_|alu_|db_low[0]~24_combout & (\z80_|alu_|db_high[0]~25_combout & ((\z80_|execute_|ctl_alu_op1_sel_low~combout )))) + + .dataa(\z80_|alu_|db_low[0]~24_combout ), + .datab(\z80_|alu_|db_high[0]~25_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~2 .lut_mask = 16'hECA0; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N0 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~3 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~3_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .datad(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~3 .lut_mask = 16'h0F00; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y17_N1 +dffeas \z80_|alu_|op1_low[0] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_low [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_low[0] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_low[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N24 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~5 ( +// Equation(s): +// \z80_|alu_|db_low[0]~5_combout = (\z80_|execute_|ctl_alu_op1_oe~1_combout & (\z80_|alu_|op1_low [0] & ((\z80_|alu_|op2_low [0]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout & (((\z80_|alu_|op2_low [0]) # +// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datab(\z80_|alu_|op1_low [0]), + .datac(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datad(\z80_|alu_|op2_low [0]), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~5 .lut_mask = 16'hDD0D; +defparam \z80_|alu_|db_low[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N26 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~6 ( +// Equation(s): +// \z80_|alu_|db_low[0]~6_combout = (\z80_|alu_|db_low[0]~4_combout & (\z80_|alu_|db_low[0]~5_combout & ((\z80_|execute_|ctl_alu_res_oe~3_combout ) # (\z80_|alu_|result_lo [0])))) + + .dataa(\z80_|execute_|ctl_alu_res_oe~3_combout ), + .datab(\z80_|alu_|db_low[0]~4_combout ), + .datac(\z80_|alu_|result_lo [0]), + .datad(\z80_|alu_|db_low[0]~5_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~6 .lut_mask = 16'hC800; +defparam \z80_|alu_|db_low[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N30 +cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~1 ( +// Equation(s): +// \z80_|alu_control_|b2v_inst_shift_mux|out~1_combout = (\z80_|ir_|opcode [5] & (\z80_|alu_|db[7]~12_combout & (\z80_|ir_|opcode [3]))) # (!\z80_|ir_|opcode [5] & ((\z80_|ir_|opcode [3] & ((\z80_|alu_|db[0]~14_combout ))) # (!\z80_|ir_|opcode [3] & +// (\z80_|alu_|db[7]~12_combout )))) + + .dataa(\z80_|alu_|db[7]~12_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|alu_|db[0]~14_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~1 .lut_mask = 16'hB282; +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_we~2_combout = (\z80_|execute_|ctl_flags_hf_we~5_combout & (\z80_|execute_|ctl_flags_xy_we~13_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_state_alu~6_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~6_combout ), + .datab(\z80_|execute_|ctl_flags_hf_we~5_combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~13_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_we~2 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_flags_hf_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~3_combout = (\z80_|execute_|ctl_flags_hf2_we~combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((!\z80_|execute_|ctl_flags_bus~1_combout ) # (!\z80_|execute_|ctl_flags_bus~0_combout )))) + + .dataa(\z80_|execute_|ctl_flags_bus~0_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_flags_hf2_we~combout ), + .datad(\z80_|execute_|ctl_flags_bus~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~3 .lut_mask = 16'hF4FC; +defparam \z80_|execute_|ctl_flags_cf_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~4_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # ((\z80_|execute_|ixy_d~6_combout & \z80_|execute_|ctl_mRead~34_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~4 .lut_mask = 16'hFFEA; +defparam \z80_|execute_|ctl_flags_cf_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~5_combout = ((\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # (\z80_|execute_|ctl_flags_cf_we~4_combout ))) # (!\z80_|execute_|ctl_flags_cf_we~7_combout ) + + .dataa(\z80_|execute_|ctl_flags_cf_we~7_combout ), + .datab(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .datad(\z80_|execute_|ctl_flags_cf_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~5 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_flags_cf_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~6_combout = (((\z80_|execute_|ctl_flags_cf_we~3_combout ) # (\z80_|execute_|ctl_flags_cf_we~5_combout )) # (!\z80_|execute_|ctl_flags_hf_we~2_combout )) # (!\z80_|execute_|ctl_flags_cf_we~2_combout ) + + .dataa(\z80_|execute_|ctl_flags_cf_we~2_combout ), + .datab(\z80_|execute_|ctl_flags_hf_we~2_combout ), + .datac(\z80_|execute_|ctl_flags_cf_we~3_combout ), + .datad(\z80_|execute_|ctl_flags_cf_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~6 .lut_mask = 16'hFFF7; +defparam \z80_|execute_|ctl_flags_cf_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N16 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~0 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf~0_combout = (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & (\z80_|execute_|ctl_flags_bus~combout & ((\z80_|alu_control_|db[0]~12_combout )))) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout +// & ((\z80_|execute_|ctl_flags_alu~15_combout ) # ((\z80_|execute_|ctl_flags_bus~combout & \z80_|alu_control_|db[0]~12_combout )))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), + .datab(\z80_|execute_|ctl_flags_bus~combout ), + .datac(\z80_|execute_|ctl_flags_alu~15_combout ), + .datad(\z80_|alu_control_|db[0]~12_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~0 .lut_mask = 16'hDC50; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N18 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~1 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf~1_combout = (\z80_|execute_|ctl_flags_cf_we~6_combout & ((\z80_|execute_|ctl_flags_cf2_we~3_combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf~q ))) # (!\z80_|execute_|ctl_flags_cf2_we~3_combout & +// (\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout )))) # (!\z80_|execute_|ctl_flags_cf_we~6_combout & (((\z80_|alu_flags_|DFFE_inst_latch_cf~q )))) + + .dataa(\z80_|execute_|ctl_flags_cf_we~6_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), + .datad(\z80_|execute_|ctl_flags_cf2_we~3_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~1 .lut_mask = 16'hF0D8; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y18_N19 +dffeas \z80_|alu_flags_|DFFE_inst_latch_cf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N4 +cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~0 ( +// Equation(s): +// \z80_|alu_control_|b2v_inst_shift_mux|out~0_combout = (\z80_|ir_|opcode [4] & ((\z80_|ir_|opcode [5] & ((!\z80_|ir_|opcode [3]))) # (!\z80_|ir_|opcode [5] & (\z80_|alu_flags_|DFFE_inst_latch_cf~q )))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~0 .lut_mask = 16'h20A8; +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N8 +cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~2 ( +// Equation(s): +// \z80_|alu_control_|b2v_inst_shift_mux|out~2_combout = (\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ) # ((\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout & !\z80_|ir_|opcode [4])) + + .dataa(\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ), + .datab(\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ), + .datac(\z80_|ir_|opcode [4]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~2 .lut_mask = 16'hCECE; +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N14 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~2 ( +// Equation(s): +// \z80_|alu_|db_low[0]~2_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[1]~10_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ))) + + .dataa(\z80_|alu_|db[1]~10_combout ), + .datab(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), + .datac(gnd), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~2 .lut_mask = 16'hAACC; +defparam \z80_|alu_|db_low[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N20 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~3 ( +// Equation(s): +// \z80_|alu_|db_low[0]~3_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_low[0]~2_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[0]~14_combout )))) # +// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .datac(\z80_|alu_|db_low[0]~2_combout ), + .datad(\z80_|alu_|db[0]~14_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~3 .lut_mask = 16'hF7D5; +defparam \z80_|alu_|db_low[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N16 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~24 ( +// Equation(s): +// \z80_|alu_|db_low[0]~24_combout = (\z80_|alu_|db_low[0]~6_combout & ((\z80_|alu_|db_low[0]~3_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~43_combout & !\z80_|alu_|db_high[3]~0_combout )))) # (!\z80_|alu_|db_low[0]~6_combout & +// (((!\z80_|execute_|ctl_alu_shift_oe~43_combout & !\z80_|alu_|db_high[3]~0_combout )))) + + .dataa(\z80_|alu_|db_low[0]~6_combout ), + .datab(\z80_|alu_|db_low[0]~3_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datad(\z80_|alu_|db_high[3]~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~24 .lut_mask = 16'h888F; +defparam \z80_|alu_|db_low[0]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N2 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~0 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~0_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [0]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [0])))) + + .dataa(\z80_|execute_|ctl_alu_op_low~combout ), + .datab(\z80_|alu_|op1_high [0]), + .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datad(\z80_|alu_|op1_low [0]), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~0 .lut_mask = 16'hE040; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N4 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~1 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~1_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~0_combout ) # ((\z80_|alu_|db_low[0]~24_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) + + .dataa(\z80_|alu_|db_low[0]~24_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .datad(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~1 .lut_mask = 16'h3320; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y18_N5 +dffeas \z80_|alu_|op2_low[0] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_low [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_low[0] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_low[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N6 +cycloneive_lcell_comb \z80_|alu_|alu_op2[0]~3 ( +// Equation(s): +// \z80_|alu_|alu_op2[0]~3_combout = \z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_high [0])) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_low [0]))))) + + .dataa(\z80_|alu_|op2_high [0]), + .datab(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), + .datad(\z80_|alu_|op2_low [0]), + .cin(gnd), + .combout(\z80_|alu_|alu_op2[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op2[0]~3 .lut_mask = 16'h4B78; +defparam \z80_|alu_|alu_op2[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N0 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout = ((!\z80_|execute_|ctl_alu_core_S~combout & !\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout )) # (!\z80_|execute_|ctl_alu_core_R~5_combout ) + + .dataa(\z80_|execute_|ctl_alu_core_S~combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_core_R~5_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 .lut_mask = 16'h0F5F; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla26M3T5_8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla26M3T5_8~combout = (\z80_|sequencer_|DFFE_T5_ff~q & (\z80_|pla_decode_|Equal21~1_combout & \z80_|sequencer_|DFFE_M3_ff~q )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T5_ff~q ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla26M3T5_8~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla26M3T5_8 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla26M3T5_8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~14 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~14_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla26M3T5_8~combout ) # ((\z80_|sequencer_|DFFE_T3_ff~q & (!\z80_|sequencer_|DFFE_T2_ff~q & \z80_|execute_|ixy_d~15_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla26M3T5_8~combout ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|execute_|ixy_d~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~14 .lut_mask = 16'hCECC; +defparam \z80_|execute_|ctl_alu_core_hf~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~16 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~16_combout = ((\z80_|execute_|ctl_alu_core_hf~14_combout ) # (!\z80_|execute_|ctl_alu_core_hf~15_combout )) # (!\z80_|execute_|ctl_alu_core_hf~12_combout ) + + .dataa(\z80_|execute_|ctl_alu_core_hf~12_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_core_hf~15_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~16 .lut_mask = 16'hFF5F; +defparam \z80_|execute_|ctl_alu_core_hf~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~13 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~13_combout = (\z80_|pla_decode_|Equal21~1_combout & ((\z80_|execute_|ctl_mRead~9_combout ) # ((!\z80_|execute_|ixy_d~5_combout & \z80_|execute_|ixy_d~6_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ctl_mRead~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~13 .lut_mask = 16'hCC40; +defparam \z80_|execute_|ctl_alu_core_hf~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~17 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~17_combout = (\z80_|execute_|ctl_alu_core_hf~16_combout & (((\z80_|execute_|ctl_alu_core_hf~13_combout & !\z80_|execute_|ctl_alu_op_low~40_combout )) # (!\z80_|execute_|ctl_alu_op_low~41_combout ))) # +// (!\z80_|execute_|ctl_alu_core_hf~16_combout & (\z80_|execute_|ctl_alu_core_hf~13_combout & ((!\z80_|execute_|ctl_alu_op_low~40_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~16_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~13_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~41_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~40_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~17 .lut_mask = 16'h0ACE; +defparam \z80_|execute_|ctl_alu_core_hf~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y20_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~44 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~44_combout = (\z80_|execute_|ctl_alu_op_low~38_combout ) # ((\z80_|execute_|ctl_alu_op_low~42_combout ) # ((\z80_|execute_|ctl_alu_op_low~36_combout ) # (!\z80_|execute_|ctl_alu_op_low~31_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~38_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~42_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~31_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~36_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~44 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|ctl_alu_op_low~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~20 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~20_combout = (\z80_|execute_|ctl_mRead~34_combout & ((\z80_|execute_|ctl_mRead~9_combout ) # ((!\z80_|execute_|ixy_d~5_combout & \z80_|execute_|ixy_d~6_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ctl_mRead~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~20 .lut_mask = 16'hCC40; +defparam \z80_|execute_|ctl_alu_core_hf~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y17_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~21 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~21_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ) # ((\z80_|execute_|ctl_alu_core_hf~20_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|execute_|ctl_mRead~34_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~21 .lut_mask = 16'hBFAA; +defparam \z80_|execute_|ctl_alu_core_hf~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~18 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~18_combout = (\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (((!\z80_|pla_decode_|Equal32~0_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal63~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal63~0_combout ), + .datab(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|pla_decode_|Equal32~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~18 .lut_mask = 16'h4CCC; +defparam \z80_|execute_|ctl_alu_core_hf~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~19 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~19_combout = (\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # ((\z80_|execute_|ctl_alu_core_hf~18_combout & !\z80_|execute_|ctl_flags_cf2_sel_daa~combout ))) + + .dataa(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~18_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~19 .lut_mask = 16'hEEFE; +defparam \z80_|execute_|ctl_alu_core_hf~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y20_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~22 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~22_combout = (\z80_|execute_|ctl_alu_op_low~37_combout & (!\z80_|execute_|ctl_alu_op_low~42_combout & ((\z80_|execute_|ctl_alu_core_hf~19_combout )))) # (!\z80_|execute_|ctl_alu_op_low~37_combout & +// ((\z80_|execute_|ctl_alu_core_hf~21_combout ) # ((!\z80_|execute_|ctl_alu_op_low~42_combout & \z80_|execute_|ctl_alu_core_hf~19_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~37_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~42_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~21_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~22 .lut_mask = 16'h7350; +defparam \z80_|execute_|ctl_alu_core_hf~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~43 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~43_combout = ((\z80_|execute_|ctl_alu_op_low~28_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ) # (!\z80_|execute_|ctl_state_alu~12_combout ))) # (!\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~28_combout ), + .datac(\z80_|execute_|ctl_state_alu~12_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~43 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|ctl_alu_op_low~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y20_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~24 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~24_combout = (\z80_|execute_|ctl_state_alu~2_combout & (\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|execute_|ctl_state_alu~2_combout & (\z80_|execute_|ixy_d~7_combout & ((\z80_|pla_decode_|Equal11~0_combout ) # +// (\z80_|pla_decode_|Equal10~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|execute_|ctl_state_alu~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~24 .lut_mask = 16'hAAC8; +defparam \z80_|execute_|ctl_alu_core_hf~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y20_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~25 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~25_combout = (!\z80_|execute_|ctl_alu_op_low~28_combout & (!\z80_|execute_|ctl_mWrite~18_combout & ((\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # (\z80_|execute_|ctl_alu_core_hf~24_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~28_combout ), + .datab(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .datac(\z80_|execute_|ctl_mWrite~18_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~25 .lut_mask = 16'h0504; +defparam \z80_|execute_|ctl_alu_core_hf~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~35 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~35_combout = (\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|execute_|ctl_alu_op_low~25_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|execute_|ctl_alu_op_low~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~35 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_core_hf~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y20_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~23 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~23_combout = (!\z80_|execute_|ctl_alu_op_low~34_combout & ((\z80_|execute_|ctl_alu_core_hf~35_combout ) # ((\z80_|execute_|ixy_d~7_combout & \z80_|execute_|ctl_alu_op_low~24_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~34_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~35_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~23 .lut_mask = 16'h5450; +defparam \z80_|execute_|ctl_alu_core_hf~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~26 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~26_combout = (!\z80_|execute_|ctl_alu_shift_oe~15_combout & (((\z80_|decode_state_|use_ixiy~combout ) # (!\z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|pla_decode_|Equal45~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal45~0_combout ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~26 .lut_mask = 16'h00DF; +defparam \z80_|execute_|ctl_alu_core_hf~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~34 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~34_combout = (\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|execute_|ctl_mRead~4_combout & ((\z80_|execute_|ctl_state_alu~4_combout )))) # (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M2_ff~q ) # +// ((\z80_|execute_|ctl_mRead~4_combout & \z80_|execute_|ctl_state_alu~4_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|execute_|ctl_mRead~4_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~34 .lut_mask = 16'hDC50; +defparam \z80_|execute_|ctl_alu_core_hf~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~27 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~27_combout = (\z80_|execute_|ctl_alu_op_low~22_combout & (((\z80_|execute_|ctl_alu_op_low~24_combout )))) # (!\z80_|execute_|ctl_alu_op_low~22_combout & (\z80_|execute_|ixy_d~7_combout & +// (!\z80_|execute_|ctl_mWrite~5_combout ))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ctl_mWrite~5_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~24_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~27 .lut_mask = 16'hF022; +defparam \z80_|execute_|ctl_alu_core_hf~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~28 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~28_combout = (!\z80_|execute_|ctl_alu_core_hf~34_combout & ((\z80_|pla_decode_|Equal56~0_combout & ((\z80_|execute_|ctl_alu_core_hf~27_combout ) # (\z80_|execute_|ctl_alu_op_low~22_combout ))) # +// (!\z80_|pla_decode_|Equal56~0_combout & (\z80_|execute_|ctl_alu_core_hf~27_combout & \z80_|execute_|ctl_alu_op_low~22_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~34_combout ), + .datab(\z80_|pla_decode_|Equal56~0_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~27_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~28 .lut_mask = 16'h5440; +defparam \z80_|execute_|ctl_alu_core_hf~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~29 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~29_combout = (\z80_|execute_|ctl_mRead~4_combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # ((!\z80_|execute_|ctl_state_alu~4_combout & \z80_|execute_|ctl_mWrite~9_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|ctl_mWrite~9_combout ), + .datac(\z80_|execute_|ctl_mRead~4_combout ), + .datad(\z80_|execute_|ctl_mWrite~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~29 .lut_mask = 16'hF040; +defparam \z80_|execute_|ctl_alu_core_hf~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~30 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~30_combout = (\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # ((\z80_|execute_|ctl_alu_core_hf~26_combout & ((\z80_|execute_|ctl_alu_core_hf~28_combout ) # (\z80_|execute_|ctl_alu_core_hf~29_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~26_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~28_combout ), + .datac(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~29_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~30 .lut_mask = 16'hFAF8; +defparam \z80_|execute_|ctl_alu_core_hf~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y20_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~31 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~31_combout = (\z80_|execute_|ctl_alu_core_hf~25_combout ) # ((\z80_|execute_|ctl_alu_core_hf~23_combout ) # ((!\z80_|execute_|ctl_alu_op_low~43_combout & \z80_|execute_|ctl_alu_core_hf~30_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~43_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~25_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~23_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~30_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~31 .lut_mask = 16'hFDFC; +defparam \z80_|execute_|ctl_alu_core_hf~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~36 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~36_combout = (\z80_|execute_|ixy_d~6_combout ) # ((\z80_|execute_|ixy_d~8_combout & !\z80_|execute_|ixy_d~9_combout )) + + .dataa(\z80_|execute_|ixy_d~8_combout ), + .datab(gnd), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ixy_d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~36 .lut_mask = 16'hF0FA; +defparam \z80_|execute_|ctl_alu_core_hf~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~37 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~37_combout = (\z80_|execute_|ctl_alu_core_hf~36_combout & ((\z80_|pla_decode_|Equal39~0_combout ) # ((!\z80_|execute_|ixy_d~5_combout & \z80_|pla_decode_|Equal40~1_combout )))) + + .dataa(\z80_|pla_decode_|Equal39~0_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~36_combout ), + .datad(\z80_|pla_decode_|Equal40~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~37 .lut_mask = 16'hB0A0; +defparam \z80_|execute_|ctl_alu_core_hf~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y20_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~32 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~32_combout = (\z80_|execute_|ctl_alu_core_hf~22_combout ) # ((\z80_|execute_|ctl_alu_core_hf~31_combout ) # ((!\z80_|execute_|ctl_alu_op_low~44_combout & \z80_|execute_|ctl_alu_core_hf~37_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~44_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~22_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~31_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~37_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~32 .lut_mask = 16'hFDFC; +defparam \z80_|execute_|ctl_alu_core_hf~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~33 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~33_combout = (\z80_|execute_|ctl_alu_core_hf~17_combout ) # ((\z80_|execute_|ctl_alu_core_hf~32_combout ) # ((!\z80_|execute_|ctl_alu_op_low~combout & \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~17_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~32_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~33 .lut_mask = 16'hFFF4; +defparam \z80_|execute_|ctl_alu_core_hf~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y14_N22 +cycloneive_lcell_comb \z80_|alu_control_|alu_core_cf_in~0 ( +// Equation(s): +// \z80_|alu_control_|alu_core_cf_in~0_combout = (\z80_|execute_|ctl_alu_core_hf~33_combout & (\z80_|alu_flags_|flags_hf~combout )) # (!\z80_|execute_|ctl_alu_core_hf~33_combout & ((\z80_|alu_flags_|flags_cf~combout ))) + + .dataa(\z80_|alu_flags_|flags_hf~combout ), + .datab(\z80_|alu_flags_|flags_cf~combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~33_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_control_|alu_core_cf_in~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|alu_core_cf_in~0 .lut_mask = 16'hACAC; +defparam \z80_|alu_control_|alu_core_cf_in~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N12 +cycloneive_lcell_comb \z80_|alu_|alu_op1[0]~0 ( +// Equation(s): +// \z80_|alu_|alu_op1[0]~0_combout = (\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [0]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [0])) + + .dataa(\z80_|execute_|ctl_alu_op_low~combout ), + .datab(\z80_|alu_|op1_high [0]), + .datac(gnd), + .datad(\z80_|alu_|op1_low [0]), + .cin(gnd), + .combout(\z80_|alu_|alu_op1[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op1[0]~0 .lut_mask = 16'hEE44; +defparam \z80_|alu_|alu_op1[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N8 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout = (\z80_|alu_|alu_op2[0]~3_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ) # ((\z80_|alu_control_|alu_core_cf_in~0_combout & \z80_|alu_|alu_op1[0]~0_combout )))) +// # (!\z80_|alu_|alu_op2[0]~3_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_control_|alu_core_cf_in~0_combout ) # (\z80_|alu_|alu_op1[0]~0_combout )))) + + .dataa(\z80_|alu_|alu_op2[0]~3_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ), + .datac(\z80_|alu_control_|alu_core_cf_in~0_combout ), + .datad(\z80_|alu_|alu_op1[0]~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 .lut_mask = 16'hECC8; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N30 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~25 ( +// Equation(s): +// \z80_|alu_|db_high[0]~25_combout = ((\z80_|alu_|db_high[0]~24_combout & ((\z80_|execute_|ctl_alu_res_oe~3_combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout )))) # (!\z80_|alu_|db_high[3]~1_combout ) + + .dataa(\z80_|alu_|db_high[0]~24_combout ), + .datab(\z80_|alu_|db_high[3]~1_combout ), + .datac(\z80_|execute_|ctl_alu_res_oe~3_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~25 .lut_mask = 16'hBBB3; +defparam \z80_|alu_|db_high[0]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N26 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~6 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~6_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|alu_|db_low[0]~24_combout ) # ((\z80_|alu_|db_high[0]~25_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) # +// (!\z80_|execute_|ctl_alu_op2_sel_lq~combout & (\z80_|alu_|db_high[0]~25_combout & (\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datab(\z80_|alu_|db_high[0]~25_combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .datad(\z80_|alu_|db_low[0]~24_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~6 .lut_mask = 16'hEAC0; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N2 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~6_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datac(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~6_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7 .lut_mask = 16'h3030; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y18_N3 +dffeas \z80_|alu_|op2_high[0] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_high [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_high[0] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_high[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N18 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout = (\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_high [0])) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_low [0]))) + + .dataa(\z80_|alu_|op2_high [0]), + .datab(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .datac(gnd), + .datad(\z80_|alu_|op2_low [0]), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'hBB88; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N16 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout = (\z80_|alu_control_|alu_core_cf_in~0_combout & ((\z80_|alu_|alu_op1[0]~0_combout ) # (\z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout )))) # (!\z80_|alu_control_|alu_core_cf_in~0_combout & (\z80_|alu_|alu_op1[0]~0_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ), + .datac(\z80_|alu_control_|alu_core_cf_in~0_combout ), + .datad(\z80_|alu_|alu_op1[0]~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hF660; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N10 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|execute_|ctl_alu_core_S~combout & !\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_core_R~combout ), + .datac(\z80_|execute_|ctl_alu_core_S~combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 .lut_mask = 16'hCCCF; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N22 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ) # +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout )))) # (!\z80_|execute_|ctl_alu_core_R~5_combout ) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), + .datac(\z80_|execute_|ctl_alu_core_R~5_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 .lut_mask = 16'h3F2F; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N28 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout = (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout & (((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout )) # +// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ))) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout & (((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout & +// !\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout )))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 .lut_mask = 16'h50FC; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N6 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~14 ( +// Equation(s): +// \z80_|alu_|db_high[1]~14_combout = ((\z80_|bus_control_|db[3]~21_combout & (\z80_|bus_control_|db[5]~15_combout & !\z80_|bus_control_|db[4]~19_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) + + .dataa(\z80_|bus_control_|db[3]~21_combout ), + .datab(\z80_|bus_control_|db[5]~15_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datad(\z80_|bus_control_|db[4]~19_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~14 .lut_mask = 16'h0F8F; +defparam \z80_|alu_|db_high[1]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N18 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~15 ( +// Equation(s): +// \z80_|alu_|db_high[1]~15_combout = (\z80_|execute_|ctl_alu_op2_oe~0_combout & (\z80_|alu_|op2_high [1] & ((\z80_|alu_|op1_high [1]) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_high +// [1]) # ((!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datab(\z80_|alu_|op1_high [1]), + .datac(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datad(\z80_|alu_|op2_high [1]), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~15 .lut_mask = 16'hCF45; +defparam \z80_|alu_|db_high[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N18 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~16 ( +// Equation(s): +// \z80_|alu_|db_high[1]~16_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[6]~22_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[4]~18_combout ))) + + .dataa(\z80_|alu_|db[6]~22_combout ), + .datab(gnd), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|alu_|db[4]~18_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~16 .lut_mask = 16'hAFA0; +defparam \z80_|alu_|db_high[1]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N12 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~17 ( +// Equation(s): +// \z80_|alu_|db_high[1]~17_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_high[1]~16_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[5]~24_combout )) + + .dataa(\z80_|alu_|db[5]~24_combout ), + .datab(\z80_|alu_|db_high[1]~16_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~17 .lut_mask = 16'hCCAA; +defparam \z80_|alu_|db_high[1]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N6 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~18 ( +// Equation(s): +// \z80_|alu_|db_high[1]~18_combout = (\z80_|alu_|db_high[1]~14_combout & (\z80_|alu_|db_high[1]~15_combout & ((\z80_|alu_|db_high[1]~17_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) + + .dataa(\z80_|alu_|db_high[1]~14_combout ), + .datab(\z80_|alu_|db_high[1]~15_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datad(\z80_|alu_|db_high[1]~17_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~18 .lut_mask = 16'h8808; +defparam \z80_|alu_|db_high[1]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N8 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~19 ( +// Equation(s): +// \z80_|alu_|db_high[1]~19_combout = ((\z80_|alu_|db_high[1]~18_combout & ((\z80_|execute_|ctl_alu_res_oe~3_combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout )))) # (!\z80_|alu_|db_high[3]~1_combout ) + + .dataa(\z80_|execute_|ctl_alu_res_oe~3_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), + .datac(\z80_|alu_|db_high[3]~1_combout ), + .datad(\z80_|alu_|db_high[1]~18_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~19 .lut_mask = 16'hEF0F; +defparam \z80_|alu_|db_high[1]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N16 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & ((\z80_|alu_|db_low[1]~12_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_low~combout & \z80_|alu_|db_high[1]~19_combout )))) # +// (!\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & (\z80_|execute_|ctl_alu_op1_sel_low~combout & ((\z80_|alu_|db_high[1]~19_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .datac(\z80_|alu_|db_low[1]~12_combout ), + .datad(\z80_|alu_|db_high[1]~19_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4 .lut_mask = 16'hECA0; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N22 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .datad(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 .lut_mask = 16'h0F00; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y17_N23 +dffeas \z80_|alu_|op1_low[1] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_low [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_low[1] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_low[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N14 +cycloneive_lcell_comb \z80_|alu_control_|out[6]~0 ( +// Equation(s): +// \z80_|alu_control_|out[6]~0_combout = (\z80_|alu_|op1_low [3] & ((\z80_|alu_|op1_low [1]) # (\z80_|alu_|op1_low [2]))) + + .dataa(\z80_|alu_|op1_low [1]), + .datab(gnd), + .datac(\z80_|alu_|op1_low [3]), + .datad(\z80_|alu_|op1_low [2]), + .cin(gnd), + .combout(\z80_|alu_control_|out[6]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|out[6]~0 .lut_mask = 16'hF0A0; +defparam \z80_|alu_control_|out[6]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N22 +cycloneive_lcell_comb \z80_|alu_control_|out[6]~1 ( +// Equation(s): +// \z80_|alu_control_|out[6]~1_combout = (\z80_|alu_|op1_high [2]) # ((\z80_|alu_|op1_high [1]) # ((\z80_|alu_control_|out[6]~0_combout & \z80_|alu_|op1_high [0]))) + + .dataa(\z80_|alu_|op1_high [2]), + .datab(\z80_|alu_control_|out[6]~0_combout ), + .datac(\z80_|alu_|op1_high [0]), + .datad(\z80_|alu_|op1_high [1]), + .cin(gnd), + .combout(\z80_|alu_control_|out[6]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|out[6]~1 .lut_mask = 16'hFFEA; +defparam \z80_|alu_control_|out[6]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N4 +cycloneive_lcell_comb \z80_|alu_control_|out[6]~2 ( +// Equation(s): +// \z80_|alu_control_|out[6]~2_combout = (\z80_|execute_|ctl_66_oe~combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_cf~q ) # ((\z80_|alu_control_|out[6]~1_combout & \z80_|alu_|op1_high [3]))) + + .dataa(\z80_|alu_control_|out[6]~1_combout ), + .datab(\z80_|execute_|ctl_66_oe~combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), + .datad(\z80_|alu_|op1_high [3]), + .cin(gnd), + .combout(\z80_|alu_control_|out[6]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|out[6]~2 .lut_mask = 16'hFEFC; +defparam \z80_|alu_control_|out[6]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N6 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_12 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout = (\z80_|alu_control_|db[6]~22_combout & \z80_|execute_|ctl_flags_bus~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|alu_control_|db[6]~22_combout ), + .datad(\z80_|execute_|ctl_flags_bus~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_12 .lut_mask = 16'hF000; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N0 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ) # (((!\z80_|pla_decode_|Equal13~0_combout ) # (!\z80_|execute_|ixy_d~7_combout )) # (!\z80_|pla_decode_|Equal55~0_combout )) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 .lut_mask = 16'hBFFF; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N28 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout = (!\z80_|alu_|db_high[3]~7_combout & (!\z80_|alu_|db_high[0]~25_combout & (!\z80_|alu_|db_high[2]~13_combout & !\z80_|alu_|db_high[1]~19_combout ))) + + .dataa(\z80_|alu_|db_high[3]~7_combout ), + .datab(\z80_|alu_|db_high[0]~25_combout ), + .datac(\z80_|alu_|db_high[2]~13_combout ), + .datad(\z80_|alu_|db_high[1]~19_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2 .lut_mask = 16'h0001; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N4 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout = (\z80_|alu_|db_high[3]~1_combout & (!\z80_|alu_|db_low[1]~12_combout & ((!\z80_|alu_|db_low[0]~3_combout ) # (!\z80_|alu_|db_low[0]~6_combout )))) + + .dataa(\z80_|alu_|db_low[0]~6_combout ), + .datab(\z80_|alu_|db_high[3]~1_combout ), + .datac(\z80_|alu_|db_low[1]~12_combout ), + .datad(\z80_|alu_|db_low[0]~3_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 .lut_mask = 16'h040C; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N24 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout = (!\z80_|alu_|db_low[2]~23_combout & (\z80_|execute_|ctl_flags_alu~15_combout & (!\z80_|alu_|db_low[3]~25_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ))) + + .dataa(\z80_|alu_|db_low[2]~23_combout ), + .datab(\z80_|execute_|ctl_flags_alu~15_combout ), + .datac(\z80_|alu_|db_low[3]~25_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 .lut_mask = 16'h0400; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N12 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout & ((\z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout )))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 .lut_mask = 16'hC888; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~7_combout = (!\z80_|execute_|ctl_flags_sz_we~6_combout & \z80_|execute_|ctl_flags_xy_we~14_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_flags_sz_we~6_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~7 .lut_mask = 16'h0F00; +defparam \z80_|execute_|ctl_flags_sz_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~8_combout = (((!\z80_|execute_|ctl_flags_sz_we~3_combout ) # (!\z80_|execute_|ctl_flags_sz_we~2_combout )) # (!\z80_|execute_|ctl_flags_sz_we~4_combout )) # (!\z80_|execute_|ctl_flags_sz_we~7_combout ) + + .dataa(\z80_|execute_|ctl_flags_sz_we~7_combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~4_combout ), + .datac(\z80_|execute_|ctl_flags_sz_we~2_combout ), + .datad(\z80_|execute_|ctl_flags_sz_we~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~8 .lut_mask = 16'h7FFF; +defparam \z80_|execute_|ctl_flags_sz_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y16_N13 +dffeas \z80_|alu_flags_|SYNTHESIZED_WIRE_39 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_flags_sz_we~8_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_39 .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_39 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N20 +cycloneive_lcell_comb \z80_|execute_|setM1~51 ( +// Equation(s): +// \z80_|execute_|setM1~51_combout = (\z80_|execute_|setM1~50_combout & (!\z80_|pla_decode_|Equal52~1_combout & ((!\z80_|pla_decode_|Equal63~0_combout ) # (!\z80_|pla_decode_|Equal3~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal3~0_combout ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|execute_|setM1~50_combout ), + .datad(\z80_|pla_decode_|Equal52~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~51_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~51 .lut_mask = 16'h0070; +defparam \z80_|execute_|setM1~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_oe~2_combout = (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (((\z80_|execute_|ctl_state_alu~6_combout ) # (!\z80_|execute_|ctl_flags_oe~1_combout )) # (!\z80_|execute_|setM1~51_combout ))) + + .dataa(\z80_|execute_|setM1~51_combout ), + .datab(\z80_|execute_|ctl_flags_oe~1_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_oe~2 .lut_mask = 16'h00F7; +defparam \z80_|execute_|ctl_flags_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~7 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~7_combout = (((\z80_|execute_|ctl_alu_oe~1_combout & \z80_|nM1_int~2_combout )) # (!\z80_|execute_|ctl_alu_oe~8_combout )) # (!\z80_|execute_|ctl_reg_out_hi~6_combout ) + + .dataa(\z80_|execute_|ctl_alu_oe~1_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|execute_|ctl_reg_out_hi~6_combout ), + .datad(\z80_|execute_|ctl_alu_oe~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~7 .lut_mask = 16'h8FFF; +defparam \z80_|execute_|ctl_sw_2u~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N10 +cycloneive_lcell_comb \z80_|alu_control_|db[6]~20 ( +// Equation(s): +// \z80_|alu_control_|db[6]~20_combout = (\z80_|alu_|db[6]~22_combout & (!\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & (\z80_|execute_|ctl_flags_oe~2_combout ))) # (!\z80_|alu_|db[6]~22_combout & ((\z80_|execute_|ctl_sw_2u~7_combout ) # +// ((!\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & \z80_|execute_|ctl_flags_oe~2_combout )))) + + .dataa(\z80_|alu_|db[6]~22_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datac(\z80_|execute_|ctl_flags_oe~2_combout ), + .datad(\z80_|execute_|ctl_sw_2u~7_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[6]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[6]~20 .lut_mask = 16'h7530; +defparam \z80_|alu_control_|db[6]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N16 +cycloneive_lcell_comb \z80_|alu_control_|db[6]~21 ( +// Equation(s): +// \z80_|alu_control_|db[6]~21_combout = (!\z80_|alu_control_|db[6]~20_combout & ((\z80_|alu_control_|out[6]~2_combout ) # ((!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & !\z80_|execute_|ctl_66_oe~combout )))) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datab(\z80_|execute_|ctl_66_oe~combout ), + .datac(\z80_|alu_control_|out[6]~2_combout ), + .datad(\z80_|alu_control_|db[6]~20_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[6]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[6]~21 .lut_mask = 16'h00F1; +defparam \z80_|alu_control_|db[6]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~8_combout = (\z80_|execute_|ctl_reg_out_lo~5_combout ) # ((!\z80_|execute_|ctl_reg_out_lo~7_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout )) + + .dataa(\z80_|execute_|ctl_reg_out_lo~5_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~8 .lut_mask = 16'hBFBF; +defparam \z80_|execute_|ctl_reg_out_lo~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N2 +cycloneive_lcell_comb \z80_|alu_control_|db[6]~10 ( +// Equation(s): +// \z80_|alu_control_|db[6]~10_combout = (\z80_|execute_|ctl_flags_oe~2_combout ) # ((\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|execute_|ctl_66_oe~2_combout & \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ))) + + .dataa(\z80_|execute_|ctl_66_oe~2_combout ), + .datab(\z80_|execute_|ctl_flags_oe~2_combout ), + .datac(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[6]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[6]~10 .lut_mask = 16'hFFEC; +defparam \z80_|alu_control_|db[6]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N28 +cycloneive_lcell_comb \z80_|alu_control_|db[6]~11 ( +// Equation(s): +// \z80_|alu_control_|db[6]~11_combout = (\z80_|execute_|ctl_sw_1d~7_combout ) # ((\z80_|execute_|ctl_reg_out_lo~8_combout ) # ((\z80_|execute_|ctl_sw_2u~7_combout ) # (\z80_|alu_control_|db[6]~10_combout ))) + + .dataa(\z80_|execute_|ctl_sw_1d~7_combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .datac(\z80_|execute_|ctl_sw_2u~7_combout ), + .datad(\z80_|alu_control_|db[6]~10_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[6]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[6]~11 .lut_mask = 16'hFFFE; +defparam \z80_|alu_control_|db[6]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N20 +cycloneive_lcell_comb \z80_|alu_control_|db[6]~22 ( +// Equation(s): +// \z80_|alu_control_|db[6]~22_combout = ((\z80_|reg_file_|db_lo_ds[6]~0_combout & (\z80_|sw1_|db_down[6]~1_combout & \z80_|alu_control_|db[6]~21_combout ))) # (!\z80_|alu_control_|db[6]~11_combout ) + + .dataa(\z80_|reg_file_|db_lo_ds[6]~0_combout ), + .datab(\z80_|sw1_|db_down[6]~1_combout ), + .datac(\z80_|alu_control_|db[6]~21_combout ), + .datad(\z80_|alu_control_|db[6]~11_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[6]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[6]~22 .lut_mask = 16'h80FF; +defparam \z80_|alu_control_|db[6]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N10 +cycloneive_lcell_comb \z80_|alu_|db[6]~21 ( +// Equation(s): +// \z80_|alu_|db[6]~21_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[6]~84_combout & ((\z80_|alu_control_|db[6]~22_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & +// ((\z80_|alu_control_|db[6]~22_combout ) # ((!\z80_|execute_|ctl_sw_2d~13_combout )))) + + .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .datab(\z80_|alu_control_|db[6]~22_combout ), + .datac(\z80_|execute_|ctl_sw_2d~13_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[6]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[6]~21 .lut_mask = 16'hCF45; +defparam \z80_|alu_|db[6]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N24 +cycloneive_lcell_comb \z80_|alu_|db[6]~22 ( +// Equation(s): +// \z80_|alu_|db[6]~22_combout = ((\z80_|alu_|db[6]~21_combout & ((\z80_|alu_|db_high[2]~13_combout ) # (!\z80_|execute_|ctl_alu_oe~11_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|execute_|ctl_alu_oe~11_combout ), + .datab(\z80_|alu_|db[7]~9_combout ), + .datac(\z80_|alu_|db_high[2]~13_combout ), + .datad(\z80_|alu_|db[6]~21_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[6]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[6]~22 .lut_mask = 16'hF733; +defparam \z80_|alu_|db[6]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y16_N3 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~80 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~80_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout & (\z80_|alu_|db[6]~22_combout & ((\z80_|reg_file_|b2v_latch_af2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # +// (!\z80_|execute_|ctl_reg_in_hi~12_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .datab(\z80_|alu_|db[6]~22_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~80_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~80 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[6]~80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y16_N23 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y16_N1 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~79 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~79_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [6]), + .datad(\z80_|reg_file_|b2v_latch_iy_hi|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~79_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~79 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[6]~79 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y16_N23 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N20 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_hi|latch[6]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_bc_hi|latch[6]~feeder_combout = \z80_|reg_file_|gdfx_temp1[6]~84_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_bc_hi|latch[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[6]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y16_N21 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_bc_hi|latch[6]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~78 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~78_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (\z80_|reg_file_|b2v_latch_bc2_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]), + .datad(\z80_|reg_file_|b2v_latch_bc_hi|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~78_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~78 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[6]~78 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y16_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~82 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~82_combout = (\z80_|reg_file_|gdfx_temp1[6]~81_combout & (\z80_|reg_file_|gdfx_temp1[6]~80_combout & (\z80_|reg_file_|gdfx_temp1[6]~79_combout & \z80_|reg_file_|gdfx_temp1[6]~78_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[6]~81_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[6]~80_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[6]~79_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[6]~78_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~82_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~82 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[6]~82 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y14_N19 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N18 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl2_hi|db[6]~5 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_hl2_hi|db[6]~5_combout = (\z80_|execute_|ctl_reg_gp_we~8_combout ) # (((\z80_|reg_file_|b2v_latch_hl2_hi|latch [6]) # (!\z80_|reg_control_|reg_sel_hl2~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [6]), + .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_hl2_hi|db[6]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|db[6]~5 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|db[6]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y15_N7 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X37_Y15_N19 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N24 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder_combout = \z80_|reg_file_|gdfx_temp1[6]~84_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y15_N25 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~76 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~76_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [6]), + .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~76_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~76 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[6]~76 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~77 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~77_combout = (\z80_|reg_file_|b2v_latch_hl2_hi|db[6]~5_combout & (\z80_|reg_file_|gdfx_temp1[6]~76_combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl2_hi|db[6]~5_combout ), + .datac(\z80_|reg_file_|b2v_latch_hl_hi|latch [6]), + .datad(\z80_|reg_file_|gdfx_temp1[6]~76_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~77_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~77 .lut_mask = 16'hC400; +defparam \z80_|reg_file_|gdfx_temp1[6]~77 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~83 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~83_combout = (\z80_|reg_file_|gdfx_temp1[6]~82_combout & (\z80_|reg_file_|gdfx_temp1[6]~77_combout & ((\z80_|reg_file_|b2v_latch_af_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_32~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_af_hi|latch [6]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_32~combout ), + .datac(\z80_|reg_file_|gdfx_temp1[6]~82_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[6]~77_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~83_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~83 .lut_mask = 16'hB000; +defparam \z80_|reg_file_|gdfx_temp1[6]~83 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~84 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~84_combout = ((\z80_|reg_file_|gdfx_temp1[6]~83_combout & ((\z80_|reg_file_|db_hi_as[6]~24_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[6]~83_combout ), + .datac(\z80_|reg_file_|db_hi_as[6]~24_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~84 .lut_mask = 16'hC4FF; +defparam \z80_|reg_file_|gdfx_temp1[6]~84 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y14_N19 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[6]~24_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N18 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~22 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[6]~22_combout = (\z80_|reg_control_|reg_sw_4d_hi~0_combout & (\z80_|reg_file_|gdfx_temp1[6]~84_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[6]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[6]~22 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_hi_as[6]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y14_N17 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[6]~24_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N26 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~23 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[6]~23_combout = (\z80_|reg_file_|db_hi_as[6]~22_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|db_hi_as[6]~22_combout ), + .datab(\z80_|reg_file_|b2v_latch_pc_hi|latch [6]), + .datac(gnd), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[6]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[6]~23 .lut_mask = 16'h88AA; +defparam \z80_|reg_file_|db_hi_as[6]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N14 +cycloneive_lcell_comb \z80_|address_latch_|abusz[13] ( +// Equation(s): +// \z80_|address_latch_|abusz [13] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[5]~15_combout ) + + .dataa(\z80_|resets_|clrpc~0_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|db_hi_as[5]~15_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [13]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[13] .lut_mask = 16'h5500; +defparam \z80_|address_latch_|abusz[13] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y13_N15 +dffeas \z80_|address_latch_|Q[13] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [13]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [13]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[13] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N18 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout = \z80_|address_latch_|Q [12] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout & (\z80_|address_latch_|Q [11] $ +// (\z80_|execute_|ctl_inc_dec~11_combout ))))) + + .dataa(\z80_|address_latch_|Q [11]), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), + .datac(\z80_|execute_|ctl_inc_dec~11_combout ), + .datad(\z80_|address_latch_|Q [12]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out .lut_mask = 16'hB748; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y16_N31 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y16_N29 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~61 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~61_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [4]), + .datad(\z80_|reg_file_|b2v_latch_iy_hi|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~61_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~61 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[4]~61 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y16_N15 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~62 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~62_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout & (\z80_|alu_|db[4]~18_combout & ((\z80_|reg_file_|b2v_latch_af2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # +// (!\z80_|execute_|ctl_reg_in_hi~12_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .datab(\z80_|alu_|db[4]~18_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~62_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~62 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[4]~62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y16_N3 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N0 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder_combout = \z80_|reg_file_|gdfx_temp1[4]~66_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y16_N1 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~60 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~60_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (\z80_|reg_file_|b2v_latch_bc2_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]), + .datad(\z80_|reg_file_|b2v_latch_bc_hi|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~60_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~60 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[4]~60 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y15_N29 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X35_Y15_N23 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~63 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~63_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (\z80_|reg_file_|b2v_latch_wz_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (((\z80_|reg_file_|b2v_latch_sp_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .datab(\z80_|reg_file_|b2v_latch_wz_hi|latch [4]), + .datac(\z80_|reg_file_|b2v_latch_sp_hi|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~63_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~63 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[4]~63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~64 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~64_combout = (\z80_|reg_file_|gdfx_temp1[4]~61_combout & (\z80_|reg_file_|gdfx_temp1[4]~62_combout & (\z80_|reg_file_|gdfx_temp1[4]~60_combout & \z80_|reg_file_|gdfx_temp1[4]~63_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[4]~61_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[4]~62_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[4]~60_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[4]~63_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~64_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~64 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[4]~64 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y15_N5 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X37_Y14_N5 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N4 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl2_hi|db[4]~4 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_hl2_hi|db[4]~4_combout = (\z80_|execute_|ctl_reg_gp_we~8_combout ) # (((\z80_|reg_file_|b2v_latch_hl2_hi|latch [4]) # (!\z80_|reg_control_|reg_sel_hl2~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [4]), + .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_hl2_hi|db[4]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|db[4]~4 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|db[4]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y15_N1 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X37_Y15_N5 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X37_Y15_N23 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~58 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~58_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datab(\z80_|reg_file_|b2v_latch_de_hi|latch [4]), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~58_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~58 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[4]~58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~59 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~59_combout = (\z80_|reg_file_|b2v_latch_hl2_hi|db[4]~4_combout & (\z80_|reg_file_|gdfx_temp1[4]~58_combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl2_hi|db[4]~4_combout ), + .datac(\z80_|reg_file_|b2v_latch_hl_hi|latch [4]), + .datad(\z80_|reg_file_|gdfx_temp1[4]~58_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~59_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~59 .lut_mask = 16'hC400; +defparam \z80_|reg_file_|gdfx_temp1[4]~59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~65 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~65_combout = (\z80_|reg_file_|gdfx_temp1[4]~64_combout & (\z80_|reg_file_|gdfx_temp1[4]~59_combout & ((\z80_|reg_file_|b2v_latch_af_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_32~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[4]~64_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_32~combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [4]), + .datad(\z80_|reg_file_|gdfx_temp1[4]~59_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~65_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~65 .lut_mask = 16'hA200; +defparam \z80_|reg_file_|gdfx_temp1[4]~65 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~66 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~66_combout = ((\z80_|reg_file_|gdfx_temp1[4]~65_combout & ((\z80_|reg_file_|db_hi_as[4]~18_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), + .datab(\z80_|reg_file_|db_hi_as[4]~18_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[4]~65_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~66 .lut_mask = 16'hD0FF; +defparam \z80_|reg_file_|gdfx_temp1[4]~66 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y14_N11 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[4]~18_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N10 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~16 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[4]~16_combout = (\z80_|reg_control_|reg_sw_4d_hi~0_combout & (\z80_|reg_file_|gdfx_temp1[4]~66_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[4]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[4]~16 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_hi_as[4]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y14_N25 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[4]~18_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N2 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~17 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[4]~17_combout = (\z80_|reg_file_|db_hi_as[4]~16_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|db_hi_as[4]~16_combout ), + .datab(\z80_|reg_file_|b2v_latch_pc_hi|latch [4]), + .datac(gnd), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[4]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[4]~17 .lut_mask = 16'h88AA; +defparam \z80_|reg_file_|db_hi_as[4]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N24 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~18 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[4]~18_combout = ((\z80_|reg_file_|db_hi_as[4]~17_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), + .datab(\z80_|reg_file_|db_hi_as[4]~17_combout ), + .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[4]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[4]~18 .lut_mask = 16'h8FCF; +defparam \z80_|reg_file_|db_hi_as[4]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N22 +cycloneive_lcell_comb \z80_|address_latch_|abusz[12] ( +// Equation(s): +// \z80_|address_latch_|abusz [12] = (\z80_|reg_file_|db_hi_as[4]~18_combout & !\z80_|resets_|clrpc~0_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[4]~18_combout ), + .datab(gnd), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [12]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[12] .lut_mask = 16'h0A0A; +defparam \z80_|address_latch_|abusz[12] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y13_N23 +dffeas \z80_|address_latch_|Q[12] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [12]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [12]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[12] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N20 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout & ((\z80_|address_latch_|Q [11] & (!\z80_|execute_|ctl_inc_dec~11_combout & +// \z80_|address_latch_|Q [12])) # (!\z80_|address_latch_|Q [11] & (\z80_|execute_|ctl_inc_dec~11_combout & !\z80_|address_latch_|Q [12])))) + + .dataa(\z80_|address_latch_|Q [11]), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), + .datac(\z80_|execute_|ctl_inc_dec~11_combout ), + .datad(\z80_|address_latch_|Q [12]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'h0840; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N24 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[14] ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|address [14] = \z80_|address_latch_|Q [14] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout & (\z80_|address_latch_|Q [13] $ (\z80_|execute_|ctl_inc_dec~11_combout ))))) + + .dataa(\z80_|address_latch_|Q [13]), + .datab(\z80_|execute_|ctl_inc_dec~11_combout ), + .datac(\z80_|address_latch_|Q [14]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[14] .lut_mask = 16'h96F0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[14] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N16 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~24 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[6]~24_combout = ((\z80_|reg_file_|db_hi_as[6]~23_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [14]) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .datab(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datac(\z80_|reg_file_|db_hi_as[6]~23_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[6]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[6]~24 .lut_mask = 16'hF373; +defparam \z80_|reg_file_|db_hi_as[6]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N30 +cycloneive_lcell_comb \z80_|address_latch_|abusz[14] ( +// Equation(s): +// \z80_|address_latch_|abusz [14] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[6]~24_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(\z80_|reg_file_|db_hi_as[6]~24_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [14]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[14] .lut_mask = 16'h0F00; +defparam \z80_|address_latch_|abusz[14] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y13_N31 +dffeas \z80_|address_latch_|Q[14] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [14]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [14]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[14] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N4 +cycloneive_lcell_comb \z80_|address_latch_|abusz[15] ( +// Equation(s): +// \z80_|address_latch_|abusz [15] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[7]~21_combout ) + + .dataa(\z80_|resets_|clrpc~0_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|db_hi_as[7]~21_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [15]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[15] .lut_mask = 16'h5500; +defparam \z80_|address_latch_|abusz[15] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y13_N5 +dffeas \z80_|address_latch_|Q[15] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [15]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [15]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[15] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N2 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[15]~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|address[15]~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout & (\z80_|address_latch_|Q [13] $ (((\z80_|execute_|ctl_inc_dec~10_combout ) # +// (\z80_|execute_|ctl_inc_dec~7_combout ))))) + + .dataa(\z80_|execute_|ctl_inc_dec~10_combout ), + .datab(\z80_|execute_|ctl_inc_dec~7_combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), + .datad(\z80_|address_latch_|Q [13]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|address[15]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[15]~0 .lut_mask = 16'h10E0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[15]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N0 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[15]~1 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|address[15]~1_combout = \z80_|address_latch_|Q [15] $ (((\z80_|address_latch_|b2v_inst_inc_dec|address[15]~0_combout & (\z80_|address_latch_|Q [14] $ (\z80_|execute_|ctl_inc_dec~11_combout ))))) + + .dataa(\z80_|address_latch_|Q [14]), + .datab(\z80_|execute_|ctl_inc_dec~11_combout ), + .datac(\z80_|address_latch_|Q [15]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|address[15]~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|address[15]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[15]~1 .lut_mask = 16'h96F0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[15]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y14_N7 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[7]~21_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X35_Y14_N21 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[7]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N20 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~19 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[7]~19_combout = (\z80_|reg_control_|reg_sw_4d_hi~0_combout & (\z80_|reg_file_|gdfx_temp1[7]~75_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) + + .dataa(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [7]), + .datad(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[7]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[7]~19 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|db_hi_as[7]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N12 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~20 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[7]~20_combout = (\z80_|reg_file_|db_hi_as[7]~19_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_pc_hi|latch [7]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datac(gnd), + .datad(\z80_|reg_file_|db_hi_as[7]~19_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[7]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[7]~20 .lut_mask = 16'hBB00; +defparam \z80_|reg_file_|db_hi_as[7]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N6 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~21 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[7]~21_combout = ((\z80_|reg_file_|db_hi_as[7]~20_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address[15]~1_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|address[15]~1_combout ), + .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datad(\z80_|reg_file_|db_hi_as[7]~20_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[7]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[7]~21 .lut_mask = 16'hDF0F; +defparam \z80_|reg_file_|db_hi_as[7]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y15_N29 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N28 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[7]~15 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[7]~15_combout = (\z80_|execute_|ctl_reg_gp_we~8_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [7]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [7]), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[7]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[7]~15 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[7]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y15_N31 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X35_Y15_N25 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~72 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~72_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (\z80_|reg_file_|b2v_latch_wz_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [7]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [7]), + .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~72_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~72 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp1[7]~72 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y16_N17 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~71 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~71_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout & (\z80_|alu_|db[7]~12_combout & ((\z80_|reg_file_|b2v_latch_af2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # +// (!\z80_|execute_|ctl_reg_in_hi~12_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .datab(\z80_|alu_|db[7]~12_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~71_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~71 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[7]~71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y16_N11 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y16_N13 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~70 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~70_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [7]), + .datad(\z80_|reg_file_|b2v_latch_iy_hi|latch [7]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~70_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~70 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[7]~70 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y16_N15 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X37_Y16_N29 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~69 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~69_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (\z80_|reg_file_|b2v_latch_bc2_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]), + .datad(\z80_|reg_file_|b2v_latch_bc_hi|latch [7]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~69_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~69 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[7]~69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y16_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~73 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~73_combout = (\z80_|reg_file_|gdfx_temp1[7]~72_combout & (\z80_|reg_file_|gdfx_temp1[7]~71_combout & (\z80_|reg_file_|gdfx_temp1[7]~70_combout & \z80_|reg_file_|gdfx_temp1[7]~69_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[7]~72_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[7]~71_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[7]~70_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[7]~69_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~73_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~73 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[7]~73 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y14_N15 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X37_Y14_N25 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~68 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~68_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (\z80_|reg_file_|b2v_latch_hl_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_hl2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (((\z80_|reg_file_|b2v_latch_hl2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [7]), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~68_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~68 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[7]~68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y15_N3 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N0 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_hi|latch[7]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_de_hi|latch[7]~feeder_combout = \z80_|reg_file_|gdfx_temp1[7]~75_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_de_hi|latch[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[7]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y15_N1 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_de_hi|latch[7]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~67 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~67_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [7]), + .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [7]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~67_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~67 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[7]~67 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y15_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~74 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~74_combout = (\z80_|reg_file_|b2v_latch_af_hi|db[7]~15_combout & (\z80_|reg_file_|gdfx_temp1[7]~73_combout & (\z80_|reg_file_|gdfx_temp1[7]~68_combout & \z80_|reg_file_|gdfx_temp1[7]~67_combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_af_hi|db[7]~15_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[7]~73_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[7]~68_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[7]~67_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~74_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~74 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[7]~74 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~75 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~75_combout = ((\z80_|reg_file_|gdfx_temp1[7]~74_combout & ((\z80_|reg_file_|db_hi_as[7]~21_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[7]~21_combout ), + .datab(\z80_|execute_|ctl_sw_4u~6_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[7]~74_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~75 .lut_mask = 16'hBF0F; +defparam \z80_|reg_file_|gdfx_temp1[7]~75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N0 +cycloneive_lcell_comb \z80_|alu_|db[7]~11 ( +// Equation(s): +// \z80_|alu_|db[7]~11_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[7]~75_combout & ((\z80_|alu_control_|db[7]~19_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & +// ((\z80_|alu_control_|db[7]~19_combout ) # ((!\z80_|execute_|ctl_sw_2d~13_combout )))) + + .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .datab(\z80_|alu_control_|db[7]~19_combout ), + .datac(\z80_|execute_|ctl_sw_2d~13_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[7]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[7]~11 .lut_mask = 16'hCF45; +defparam \z80_|alu_|db[7]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N30 +cycloneive_lcell_comb \z80_|alu_|db[7]~12 ( +// Equation(s): +// \z80_|alu_|db[7]~12_combout = ((\z80_|alu_|db[7]~11_combout & ((\z80_|alu_|db_high[3]~7_combout ) # (!\z80_|execute_|ctl_alu_oe~11_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|execute_|ctl_alu_oe~11_combout ), + .datab(\z80_|alu_|db[7]~9_combout ), + .datac(\z80_|alu_|db_high[3]~7_combout ), + .datad(\z80_|alu_|db[7]~11_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[7]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[7]~12 .lut_mask = 16'hF733; +defparam \z80_|alu_|db[7]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N28 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~0 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[0]~14_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[7]~12_combout ))) + + .dataa(\z80_|alu_|db[0]~14_combout ), + .datab(gnd), + .datac(\z80_|alu_|db[7]~12_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~0 .lut_mask = 16'hAAF0; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N2 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~1 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_control_|out[6]~2_combout ))) + + .dataa(gnd), + .datab(\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ), + .datac(\z80_|alu_control_|out[6]~2_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~1 .lut_mask = 16'hCCF0; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N20 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~2 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (((\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout & !\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout )))) # (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout +// & ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((!\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout )))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ), + .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~2 .lut_mask = 16'h03CA; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N8 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~3 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout = (\z80_|execute_|ctl_flags_cf2_we~3_combout & (\z80_|execute_|ctl_flags_cf2_sel_daa~combout $ (((!\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ))))) # (!\z80_|execute_|ctl_flags_cf2_we~3_combout & +// ((\z80_|alu_flags_|DFFE_inst_latch_cf2~q ) # ((\z80_|execute_|ctl_flags_cf2_sel_daa~combout & \z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout )))) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datab(\z80_|execute_|ctl_flags_cf2_we~3_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~3 .lut_mask = 16'hBA74; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y14_N9 +dffeas \z80_|alu_flags_|DFFE_inst_latch_cf2 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2 .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~8_combout = (\z80_|pla_decode_|Equal20~0_combout ) # ((\z80_|execute_|ctl_ir_we~14_combout ) # (\z80_|execute_|ctl_ir_we~8_combout )) + + .dataa(\z80_|pla_decode_|Equal20~0_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_ir_we~14_combout ), + .datad(\z80_|execute_|ctl_ir_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~8 .lut_mask = 16'hFFFA; +defparam \z80_|execute_|ctl_flags_use_cf2~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~9 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~9_combout = (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_flags_use_cf2~8_combout ) # ((\z80_|pla_decode_|Equal63~0_combout & \z80_|pla_decode_|Equal9~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal63~0_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|execute_|ctl_flags_use_cf2~8_combout ), + .datad(\z80_|pla_decode_|Equal9~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~9 .lut_mask = 16'h3230; +defparam \z80_|execute_|ctl_flags_use_cf2~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~10_combout = (\z80_|pla_decode_|Equal11~0_combout & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_M1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~10 .lut_mask = 16'h0C04; +defparam \z80_|execute_|ctl_flags_use_cf2~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~11 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~11_combout = (\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # ((\z80_|execute_|ctl_flags_use_cf2~10_combout ) # ((\z80_|execute_|ixy_d~7_combout & \z80_|pla_decode_|Equal10~0_combout ))) + + .dataa(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|execute_|ctl_flags_use_cf2~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~11 .lut_mask = 16'hFFEA; +defparam \z80_|execute_|ctl_flags_use_cf2~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~12 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~12_combout = ((\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # ((\z80_|execute_|ctl_flags_use_cf2~9_combout ) # (\z80_|execute_|ctl_flags_use_cf2~11_combout ))) # (!\z80_|execute_|ctl_flags_use_cf2~13_combout ) + + .dataa(\z80_|execute_|ctl_flags_use_cf2~13_combout ), + .datab(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .datac(\z80_|execute_|ctl_flags_use_cf2~9_combout ), + .datad(\z80_|execute_|ctl_flags_use_cf2~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~12 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_flags_use_cf2~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N28 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout = (\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & (\z80_|alu_flags_|DFFE_inst_latch_cf2~q )) # (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & ((\z80_|execute_|ctl_flags_use_cf2~12_combout & +// (\z80_|alu_flags_|DFFE_inst_latch_cf2~q )) # (!\z80_|execute_|ctl_flags_use_cf2~12_combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf~q ))))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), + .datac(\z80_|execute_|ctl_flags_use_cf2~12_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 .lut_mask = 16'hABA8; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~46 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~46_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|pla_decode_|Equal10~0_combout & \z80_|sequencer_|DFFE_T3_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|pla_decode_|Equal10~0_combout ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~46 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_alu_op_low~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~9_combout = (\z80_|execute_|ctl_alu_core_S~4_combout & (\z80_|execute_|ctl_bus_inc_oe~44_combout & (\z80_|execute_|ctl_flags_alu~18_combout & \z80_|execute_|ctl_alu_op1_sel_bus~9_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_S~4_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .datac(\z80_|execute_|ctl_flags_alu~18_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~9 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N28 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|pla_decode_|Equal63~0_combout & (\z80_|pla_decode_|Equal21~0_combout & !\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) + + .dataa(\z80_|pla_decode_|Equal63~0_combout ), + .datab(\z80_|pla_decode_|Equal21~0_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 .lut_mask = 16'hFF08; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N10 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout = (\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # ((\z80_|execute_|ctl_alu_op_low~46_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~46_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 .lut_mask = 16'hFFEF; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N16 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout = ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ) # ((\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & \z80_|execute_|ctl_alu_op_low~42_combout ))) # (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ) + + .dataa(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~42_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 .lut_mask = 16'hFBF3; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y17_N16 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout = (\z80_|execute_|ctl_state_alu~11_combout & ((\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3])) # (!\z80_|ir_|opcode [5] & ((!\z80_|ir_|opcode [3]))))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|execute_|ctl_state_alu~11_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 .lut_mask = 16'h8050; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N22 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ) # ((\z80_|execute_|ctl_alu_op_low~41_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~41_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 .lut_mask = 16'hFEFA; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~3_combout = (\z80_|execute_|ctl_alu_op_low~41_combout & (\z80_|pla_decode_|Equal64~0_combout & ((\z80_|pla_decode_|Equal9~0_combout ) # (\z80_|pla_decode_|Equal3~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~41_combout ), + .datab(\z80_|pla_decode_|Equal9~0_combout ), + .datac(\z80_|pla_decode_|Equal64~0_combout ), + .datad(\z80_|pla_decode_|Equal3~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~3 .lut_mask = 16'hA080; +defparam \z80_|execute_|ctl_flags_cf_cpl~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N20 +cycloneive_lcell_comb \z80_|alu_flags_|flags_cf ( +// Equation(s): +// \z80_|alu_flags_|flags_cf~combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout $ (((\z80_|execute_|ctl_flags_cf_cpl~9_combout ) # (\z80_|execute_|ctl_flags_cf_cpl~3_combout ))))) + + .dataa(\z80_|execute_|ctl_flags_cf_cpl~9_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ), + .datad(\z80_|execute_|ctl_flags_cf_cpl~3_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|flags_cf~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|flags_cf .lut_mask = 16'h0C48; +defparam \z80_|alu_flags_|flags_cf .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N14 +cycloneive_lcell_comb \z80_|sw2_|db_up[0]~0 ( +// Equation(s): +// \z80_|sw2_|db_up[0]~0_combout = (\z80_|alu_|db[0]~14_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|alu_|db[0]~14_combout ), + .datad(\z80_|execute_|ctl_sw_2u~7_combout ), + .cin(gnd), + .combout(\z80_|sw2_|db_up[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sw2_|db_up[0]~0 .lut_mask = 16'hF0FF; +defparam \z80_|sw2_|db_up[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N14 +cycloneive_lcell_comb \z80_|alu_control_|db[0]~8 ( +// Equation(s): +// \z80_|alu_control_|db[0]~8_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & (((!\z80_|execute_|ctl_sw_mask543_en~0_combout & \z80_|bus_control_|db[0]~17_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) + + .dataa(\z80_|execute_|ctl_sw_mask543_en~0_combout ), + .datab(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .datac(\z80_|execute_|ctl_sw_1d~7_combout ), + .datad(\z80_|bus_control_|db[0]~17_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[0]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[0]~8 .lut_mask = 16'h4C0C; +defparam \z80_|alu_control_|db[0]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y12_N11 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[0]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y12_N5 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[0]~3_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N4 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~0 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[0]~0_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[0]~22_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # +// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[0]~0 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_lo_as[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N0 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~1 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[0]~1_combout = (\z80_|reg_file_|db_lo_as[0]~0_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_ir_lo|latch [0]), + .datab(gnd), + .datac(\z80_|reg_file_|db_lo_as[0]~0_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[0]~1 .lut_mask = 16'hA0F0; +defparam \z80_|reg_file_|db_lo_as[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~70 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~70_combout = (!\z80_|nM1_int~2_combout & (((!\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ctl_alu_op_low~22_combout )) # (!\z80_|pla_decode_|Equal41~2_combout ))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|pla_decode_|Equal41~2_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~70_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~70 .lut_mask = 16'h0307; +defparam \z80_|execute_|ctl_inc_cy~70 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N8 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~28 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~28_combout = (\z80_|pla_decode_|Equal10~0_combout & (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|pla_decode_|Equal10~0_combout ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~28 .lut_mask = 16'hC080; +defparam \z80_|execute_|pc_inc_hold~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N10 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~15 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~15_combout = (\z80_|execute_|pc_inc_hold~28_combout ) # ((\z80_|execute_|ctl_alu_op_low~22_combout & ((\z80_|pla_decode_|Equal52~1_combout ) # (\z80_|execute_|ixy_d~16_combout )))) + + .dataa(\z80_|pla_decode_|Equal52~1_combout ), + .datab(\z80_|execute_|ixy_d~16_combout ), + .datac(\z80_|execute_|pc_inc_hold~28_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~15 .lut_mask = 16'hFEF0; +defparam \z80_|execute_|pc_inc_hold~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N18 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~27 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~27_combout = (\z80_|pla_decode_|Equal11~0_combout & (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~27 .lut_mask = 16'hC080; +defparam \z80_|execute_|pc_inc_hold~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~10 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~10_combout = (\z80_|execute_|ctl_alu_op_low~22_combout & (((\z80_|execute_|ctl_mRead~7_combout ) # (\z80_|execute_|ctl_mRead~13_combout )))) # (!\z80_|execute_|ctl_alu_op_low~22_combout & (\z80_|execute_|ixy_d~5_combout & +// ((\z80_|execute_|ctl_mRead~13_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_mRead~7_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datad(\z80_|execute_|ctl_mRead~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~10 .lut_mask = 16'hFAC0; +defparam \z80_|execute_|pc_inc_hold~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout = (\z80_|execute_|ixy_d~5_combout & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal55~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~11 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~11_combout = (\z80_|execute_|ctl_alu_op_low~22_combout & ((\z80_|pla_decode_|Equal6~1_combout ) # ((\z80_|execute_|ctl_mRead~8_combout )))) # (!\z80_|execute_|ctl_alu_op_low~22_combout & (\z80_|execute_|ixy_d~5_combout & +// ((\z80_|pla_decode_|Equal6~1_combout ) # (\z80_|execute_|ctl_mRead~8_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datab(\z80_|pla_decode_|Equal6~1_combout ), + .datac(\z80_|execute_|ctl_mRead~8_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~11 .lut_mask = 16'hFCA8; +defparam \z80_|execute_|pc_inc_hold~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout = (\z80_|decode_state_|use_ixiy~combout & (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|pla_decode_|Equal33~2_combout ))) + + .dataa(\z80_|decode_state_|use_ixiy~combout ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|pla_decode_|Equal33~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~9 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~9_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ) # ((\z80_|execute_|ctl_alu_op_low~22_combout & ((\z80_|execute_|ctl_mRead~12_combout ) # (!\z80_|execute_|pc_inc_hold~6_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datac(\z80_|execute_|ctl_mRead~12_combout ), + .datad(\z80_|execute_|pc_inc_hold~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~9 .lut_mask = 16'hEAEE; +defparam \z80_|execute_|pc_inc_hold~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~12 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~12_combout = (\z80_|execute_|pc_inc_hold~10_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ) # ((\z80_|execute_|pc_inc_hold~11_combout ) # (\z80_|execute_|pc_inc_hold~9_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~10_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ), + .datac(\z80_|execute_|pc_inc_hold~11_combout ), + .datad(\z80_|execute_|pc_inc_hold~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~12 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|pc_inc_hold~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~7 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~7_combout = ((\z80_|pla_decode_|Equal12~1_combout ) # ((!\z80_|execute_|ctl_alu_op_low~22_combout & !\z80_|execute_|ixy_d~5_combout ))) # (!\z80_|pla_decode_|Equal25~0_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datab(\z80_|pla_decode_|Equal25~0_combout ), + .datac(\z80_|pla_decode_|Equal12~1_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~7 .lut_mask = 16'hF3F7; +defparam \z80_|execute_|pc_inc_hold~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y14_N8 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~8 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~8_combout = (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|execute_|ctl_mRead~15_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|execute_|ctl_mRead~15_combout ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~8 .lut_mask = 16'h5F7F; +defparam \z80_|execute_|pc_inc_hold~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~13 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~13_combout = (\z80_|execute_|ctl_mRead~6_combout & (\z80_|sequencer_|DFFE_T2_ff~q & ((\z80_|sequencer_|DFFE_M2_ff~q ) # (\z80_|sequencer_|DFFE_M3_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|execute_|ctl_mRead~6_combout ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~13 .lut_mask = 16'hE000; +defparam \z80_|execute_|pc_inc_hold~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y14_N14 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~14 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~14_combout = (!\z80_|execute_|pc_inc_hold~12_combout & (\z80_|execute_|pc_inc_hold~7_combout & (\z80_|execute_|pc_inc_hold~8_combout & !\z80_|execute_|pc_inc_hold~13_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~12_combout ), + .datab(\z80_|execute_|pc_inc_hold~7_combout ), + .datac(\z80_|execute_|pc_inc_hold~8_combout ), + .datad(\z80_|execute_|pc_inc_hold~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~14 .lut_mask = 16'h0040; +defparam \z80_|execute_|pc_inc_hold~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal45~0_combout & \z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|pla_decode_|Equal45~0_combout ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y14_N16 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~16 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~16_combout = (!\z80_|execute_|pc_inc_hold~15_combout & (!\z80_|execute_|pc_inc_hold~27_combout & (\z80_|execute_|pc_inc_hold~14_combout & !\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~15_combout ), + .datab(\z80_|execute_|pc_inc_hold~27_combout ), + .datac(\z80_|execute_|pc_inc_hold~14_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~16 .lut_mask = 16'h0010; +defparam \z80_|execute_|pc_inc_hold~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N8 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~22 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~22_combout = (\z80_|execute_|ctl_mRead~34_combout & (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q )))) + + .dataa(\z80_|execute_|ctl_mRead~34_combout ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~22 .lut_mask = 16'h8880; +defparam \z80_|execute_|pc_inc_hold~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~23 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~23_combout = (\z80_|execute_|pc_inc_hold~26_combout & (!\z80_|pla_decode_|Equal19~0_combout & ((\z80_|execute_|ctl_bus_db_oe~1_combout ) # (!\z80_|execute_|ctl_alu_op_low~22_combout )))) + + .dataa(\z80_|execute_|pc_inc_hold~26_combout ), + .datab(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~23 .lut_mask = 16'h080A; +defparam \z80_|execute_|pc_inc_hold~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~24 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~24_combout = (\z80_|execute_|pc_inc_hold~22_combout ) # ((!\z80_|execute_|pc_inc_hold~23_combout & ((\z80_|execute_|ixy_d~5_combout ) # (\z80_|execute_|ctl_alu_op_low~22_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|pc_inc_hold~22_combout ), + .datac(\z80_|execute_|pc_inc_hold~23_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~24 .lut_mask = 16'hCFCE; +defparam \z80_|execute_|pc_inc_hold~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~41 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~41_combout = (((!\z80_|pla_decode_|Equal3~0_combout & !\z80_|pla_decode_|Equal21~0_combout )) # (!\z80_|pla_decode_|Equal24~0_combout )) # (!\z80_|execute_|ctl_alu_op_low~22_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datab(\z80_|pla_decode_|Equal3~0_combout ), + .datac(\z80_|pla_decode_|Equal21~0_combout ), + .datad(\z80_|pla_decode_|Equal24~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~41 .lut_mask = 16'h57FF; +defparam \z80_|execute_|ctl_inc_cy~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~21 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~21_combout = (\z80_|execute_|ctl_mWrite~4_combout & (\z80_|pla_decode_|Equal55~0_combout & ((\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (\z80_|execute_|ctl_mWrite~9_combout )))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datab(\z80_|execute_|ctl_mWrite~4_combout ), + .datac(\z80_|execute_|ctl_mWrite~9_combout ), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~21 .lut_mask = 16'hC800; +defparam \z80_|execute_|pc_inc_hold~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y15_N8 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~25 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~25_combout = ((\z80_|execute_|pc_inc_hold~24_combout ) # ((\z80_|execute_|pc_inc_hold~21_combout ) # (!\z80_|execute_|ctl_inc_cy~41_combout ))) # (!\z80_|execute_|pc_inc_hold~16_combout ) + + .dataa(\z80_|execute_|pc_inc_hold~16_combout ), + .datab(\z80_|execute_|pc_inc_hold~24_combout ), + .datac(\z80_|execute_|ctl_inc_cy~41_combout ), + .datad(\z80_|execute_|pc_inc_hold~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~25 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|pc_inc_hold~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~69 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~69_combout = (!\z80_|execute_|pc_inc_hold~25_combout & (((!\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ctl_alu_op_low~22_combout )) # (!\z80_|pla_decode_|Equal34~0_combout ))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datac(\z80_|execute_|pc_inc_hold~25_combout ), + .datad(\z80_|pla_decode_|Equal34~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~69_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~69 .lut_mask = 16'h010F; +defparam \z80_|execute_|ctl_inc_cy~69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~17 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~17_combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # ((\z80_|interrupts_|DFFE_inst44~q ) # (\z80_|decode_state_|in_halt~q )) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(gnd), + .datac(\z80_|interrupts_|DFFE_inst44~q ), + .datad(\z80_|decode_state_|in_halt~q ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~17 .lut_mask = 16'hFFFA; +defparam \z80_|execute_|pc_inc_hold~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~71 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~71_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (((\z80_|execute_|ctl_inc_cy~70_combout & \z80_|execute_|ctl_inc_cy~69_combout )) # (!\z80_|execute_|pc_inc_hold~17_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|execute_|ctl_inc_cy~70_combout ), + .datac(\z80_|execute_|ctl_inc_cy~69_combout ), + .datad(\z80_|execute_|pc_inc_hold~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~71_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~71 .lut_mask = 16'h80AA; +defparam \z80_|execute_|ctl_inc_cy~71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~44 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~44_combout = (\z80_|execute_|ctl_inc_cy~82_combout & (\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout & ((\z80_|execute_|pc_inc_hold~16_combout ) # (!\z80_|execute_|pc_inc_hold~17_combout )))) # +// (!\z80_|execute_|ctl_inc_cy~82_combout & (((\z80_|execute_|pc_inc_hold~16_combout ) # (!\z80_|execute_|pc_inc_hold~17_combout )))) + + .dataa(\z80_|execute_|ctl_inc_cy~82_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), + .datac(\z80_|execute_|pc_inc_hold~16_combout ), + .datad(\z80_|execute_|pc_inc_hold~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~44 .lut_mask = 16'hD0DD; +defparam \z80_|execute_|ctl_inc_cy~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~42 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~42_combout = (\z80_|execute_|pc_inc_hold~16_combout & \z80_|execute_|ctl_inc_cy~41_combout ) + + .dataa(\z80_|execute_|pc_inc_hold~16_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_inc_cy~41_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~42 .lut_mask = 16'hA0A0; +defparam \z80_|execute_|ctl_inc_cy~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~43 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~43_combout = (\z80_|execute_|ctl_mWrite~17_combout & (\z80_|execute_|ixy_d~5_combout & ((\z80_|execute_|ctl_inc_cy~42_combout ) # (!\z80_|execute_|pc_inc_hold~17_combout )))) + + .dataa(\z80_|execute_|pc_inc_hold~17_combout ), + .datab(\z80_|execute_|ctl_inc_cy~42_combout ), + .datac(\z80_|execute_|ctl_mWrite~17_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~43 .lut_mask = 16'hD000; +defparam \z80_|execute_|ctl_inc_cy~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~57 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~57_combout = (\z80_|execute_|ctl_inc_cy~38_combout ) # ((\z80_|execute_|pc_inc_hold~17_combout & ((\z80_|execute_|pc_inc_hold~12_combout ) # (!\z80_|execute_|pc_inc_hold~7_combout )))) + + .dataa(\z80_|execute_|ctl_inc_cy~38_combout ), + .datab(\z80_|execute_|pc_inc_hold~17_combout ), + .datac(\z80_|execute_|pc_inc_hold~7_combout ), + .datad(\z80_|execute_|pc_inc_hold~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~57_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~57 .lut_mask = 16'hEEAE; +defparam \z80_|execute_|ctl_inc_cy~57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~54 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~54_combout = ((!\z80_|execute_|ctl_alu_op_low~22_combout & ((!\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_T4_ff~q )))) # (!\z80_|pla_decode_|Equal10~0_combout ) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~54_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~54 .lut_mask = 16'h0F7F; +defparam \z80_|execute_|ctl_inc_cy~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~58 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~58_combout = ((!\z80_|execute_|pc_inc_hold~27_combout & (\z80_|execute_|pc_inc_hold~14_combout & !\z80_|execute_|ctl_inc_cy~54_combout ))) # (!\z80_|execute_|ctl_inc_cy~57_combout ) + + .dataa(\z80_|execute_|ctl_inc_cy~57_combout ), + .datab(\z80_|execute_|pc_inc_hold~27_combout ), + .datac(\z80_|execute_|pc_inc_hold~14_combout ), + .datad(\z80_|execute_|ctl_inc_cy~54_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~58_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~58 .lut_mask = 16'h5575; +defparam \z80_|execute_|ctl_inc_cy~58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~18 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~18_combout = (\z80_|execute_|pc_inc_hold~10_combout ) # ((\z80_|execute_|pc_inc_hold~9_combout ) # ((\z80_|execute_|ixy_d~5_combout & \z80_|execute_|ctl_mRead~7_combout ))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_mRead~7_combout ), + .datac(\z80_|execute_|pc_inc_hold~10_combout ), + .datad(\z80_|execute_|pc_inc_hold~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~18 .lut_mask = 16'hFFF8; +defparam \z80_|execute_|pc_inc_hold~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y14_N30 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~19 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~19_combout = (\z80_|execute_|pc_inc_hold~18_combout ) # ((\z80_|execute_|pc_inc_hold~13_combout ) # ((\z80_|execute_|pc_inc_hold~11_combout ) # (!\z80_|execute_|pc_inc_hold~7_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~18_combout ), + .datab(\z80_|execute_|pc_inc_hold~13_combout ), + .datac(\z80_|execute_|pc_inc_hold~7_combout ), + .datad(\z80_|execute_|pc_inc_hold~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~19 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|pc_inc_hold~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~45 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~45_combout = ((\z80_|pla_decode_|Equal9~1_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ixy_d~9_combout )))) # (!\z80_|execute_|ctl_inc_cy~87_combout ) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_inc_cy~87_combout ), + .datad(\z80_|execute_|ixy_d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~45 .lut_mask = 16'hAF8F; +defparam \z80_|execute_|ctl_inc_cy~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~34 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~34_combout = ((!\z80_|execute_|ctl_alu_op_low~22_combout & (!\z80_|execute_|ctl_state_alu~2_combout & !\z80_|execute_|ixy_d~5_combout ))) # (!\z80_|execute_|ctl_mWrite~6_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~34 .lut_mask = 16'h3337; +defparam \z80_|execute_|ctl_inc_cy~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~35 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~35_combout = (\z80_|execute_|ctl_sw_2u~0_combout & (\z80_|execute_|ctl_inc_cy~34_combout & ((!\z80_|pla_decode_|Equal11~0_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_sw_2u~0_combout ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|execute_|ctl_inc_cy~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~35 .lut_mask = 16'h4C00; +defparam \z80_|execute_|ctl_inc_cy~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~46 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~46_combout = (\z80_|pla_decode_|Equal11~0_combout & ((\z80_|execute_|ixy_d~9_combout ) # ((\z80_|execute_|ctl_mWrite~6_combout & \z80_|execute_|ixy_d~7_combout )))) # (!\z80_|pla_decode_|Equal11~0_combout & +// (\z80_|execute_|ctl_mWrite~6_combout & (\z80_|execute_|ixy_d~7_combout ))) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ixy_d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~46 .lut_mask = 16'hEAC0; +defparam \z80_|execute_|ctl_inc_cy~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~47 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~47_combout = ((\z80_|execute_|ctl_inc_cy~46_combout ) # ((\z80_|execute_|ctl_mWrite~6_combout & \z80_|execute_|ctl_mRead~9_combout ))) # (!\z80_|execute_|ctl_inc_cy~39_combout ) + + .dataa(\z80_|execute_|ctl_inc_cy~39_combout ), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datac(\z80_|execute_|ctl_mRead~9_combout ), + .datad(\z80_|execute_|ctl_inc_cy~46_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~47 .lut_mask = 16'hFFD5; +defparam \z80_|execute_|ctl_inc_cy~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~48 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~48_combout = (\z80_|execute_|ctl_inc_cy~47_combout ) # ((\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ) # ((\z80_|pla_decode_|Equal11~0_combout & \z80_|execute_|ctl_alu_op_low~22_combout ))) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datac(\z80_|execute_|ctl_inc_cy~47_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~48 .lut_mask = 16'hFFF8; +defparam \z80_|execute_|ctl_inc_cy~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y18_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~50 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~50_combout = (\z80_|execute_|ctl_inc_cy~45_combout ) # (((\z80_|execute_|ctl_inc_cy~48_combout ) # (!\z80_|execute_|ctl_inc_cy~35_combout )) # (!\z80_|execute_|ctl_inc_cy~49_combout )) + + .dataa(\z80_|execute_|ctl_inc_cy~45_combout ), + .datab(\z80_|execute_|ctl_inc_cy~49_combout ), + .datac(\z80_|execute_|ctl_inc_cy~35_combout ), + .datad(\z80_|execute_|ctl_inc_cy~48_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~50_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~50 .lut_mask = 16'hFFBF; +defparam \z80_|execute_|ctl_inc_cy~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y14_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~51 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~51_combout = (\z80_|execute_|ctl_inc_cy~50_combout & (((!\z80_|execute_|pc_inc_hold~19_combout & \z80_|execute_|pc_inc_hold~8_combout )) # (!\z80_|execute_|pc_inc_hold~17_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~19_combout ), + .datab(\z80_|execute_|pc_inc_hold~17_combout ), + .datac(\z80_|execute_|pc_inc_hold~8_combout ), + .datad(\z80_|execute_|ctl_inc_cy~50_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~51_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~51 .lut_mask = 16'h7300; +defparam \z80_|execute_|ctl_inc_cy~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y14_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~85 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~85_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|execute_|ctl_mRead~6_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|execute_|ctl_mRead~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~85_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~85 .lut_mask = 16'h57FF; +defparam \z80_|execute_|ctl_inc_cy~85 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~63 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~63_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (!\z80_|interrupts_|DFFE_inst44~q & (\z80_|execute_|ctl_mRead~12_combout & !\z80_|decode_state_|in_halt~q ))) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|interrupts_|DFFE_inst44~q ), + .datac(\z80_|execute_|ctl_mRead~12_combout ), + .datad(\z80_|decode_state_|in_halt~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~63_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~63 .lut_mask = 16'h0010; +defparam \z80_|execute_|ctl_inc_cy~63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~64 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~64_combout = (\z80_|execute_|ctl_alu_op_low~22_combout & ((\z80_|execute_|ctl_inc_cy~63_combout ) # ((!\z80_|execute_|ctl_reg_sys_hilo~21_combout & !\z80_|execute_|pc_inc_hold~9_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo~21_combout ), + .datab(\z80_|execute_|ctl_inc_cy~63_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datad(\z80_|execute_|pc_inc_hold~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~64_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~64 .lut_mask = 16'hC0D0; +defparam \z80_|execute_|ctl_inc_cy~64 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~65 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~65_combout = (\z80_|execute_|ctl_inc_cy~64_combout ) # ((\z80_|execute_|ctl_mRead~13_combout & (\z80_|execute_|ctl_alu_shift_oe~14_combout & !\z80_|execute_|pc_inc_hold~18_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~13_combout ), + .datab(\z80_|execute_|ctl_inc_cy~64_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datad(\z80_|execute_|pc_inc_hold~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~65_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~65 .lut_mask = 16'hCCEC; +defparam \z80_|execute_|ctl_inc_cy~65 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~59 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~59_combout = (((!\z80_|pla_decode_|Equal55~0_combout ) # (!\z80_|execute_|ctl_alu_op_low~22_combout )) # (!\z80_|pla_decode_|Equal6~0_combout )) # (!\z80_|pla_decode_|Equal33~1_combout ) + + .dataa(\z80_|pla_decode_|Equal33~1_combout ), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~59_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~59 .lut_mask = 16'h7FFF; +defparam \z80_|execute_|ctl_inc_cy~59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~60 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~60_combout = ((\z80_|execute_|ctl_inc_cy~59_combout & (!\z80_|execute_|pc_inc_hold~9_combout & !\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ))) # (!\z80_|execute_|pc_inc_hold~17_combout ) + + .dataa(\z80_|execute_|ctl_inc_cy~59_combout ), + .datab(\z80_|execute_|pc_inc_hold~9_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ), + .datad(\z80_|execute_|pc_inc_hold~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~60_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~60 .lut_mask = 16'h02FF; +defparam \z80_|execute_|ctl_inc_cy~60 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~61 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~61_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|execute_|ctl_mRead~8_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|execute_|ctl_mRead~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~61_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~61 .lut_mask = 16'h57FF; +defparam \z80_|execute_|ctl_inc_cy~61 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y14_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~62 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~62_combout = (\z80_|execute_|pc_inc_hold~12_combout & (\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & (\z80_|execute_|ctl_inc_cy~60_combout ))) # (!\z80_|execute_|pc_inc_hold~12_combout & +// (((\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & \z80_|execute_|ctl_inc_cy~60_combout )) # (!\z80_|execute_|ctl_inc_cy~61_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~12_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), + .datac(\z80_|execute_|ctl_inc_cy~60_combout ), + .datad(\z80_|execute_|ctl_inc_cy~61_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~62_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~62 .lut_mask = 16'hC0D5; +defparam \z80_|execute_|ctl_inc_cy~62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y14_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~66 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~66_combout = (\z80_|execute_|ctl_inc_cy~65_combout ) # ((\z80_|execute_|ctl_inc_cy~62_combout ) # ((!\z80_|execute_|ctl_inc_cy~85_combout & !\z80_|execute_|pc_inc_hold~19_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~85_combout ), + .datab(\z80_|execute_|ctl_inc_cy~65_combout ), + .datac(\z80_|execute_|pc_inc_hold~19_combout ), + .datad(\z80_|execute_|ctl_inc_cy~62_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~66_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~66 .lut_mask = 16'hFFCD; +defparam \z80_|execute_|ctl_inc_cy~66 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~53 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~53_combout = ((\z80_|execute_|ixy_d~5_combout & ((\z80_|pla_decode_|Equal41~2_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) # (!\z80_|execute_|ctl_reg_sel_pc~7_combout ) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~7_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datad(\z80_|pla_decode_|Equal41~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~53_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~53 .lut_mask = 16'hBB3B; +defparam \z80_|execute_|ctl_inc_cy~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~52 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~52_combout = (\z80_|execute_|ctl_mRead~2_combout ) # ((\z80_|execute_|ctl_mWrite~8_combout ) # ((\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~8_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~2_combout ), + .datab(\z80_|execute_|ctl_mWrite~8_combout ), + .datac(\z80_|pla_decode_|Equal34~0_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~52_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~52 .lut_mask = 16'hFEFF; +defparam \z80_|execute_|ctl_inc_cy~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~84 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~84_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & ((\z80_|execute_|ctl_inc_cy~52_combout ) # (!\z80_|execute_|fMRead~7_combout )))) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|execute_|ctl_inc_cy~52_combout ), + .datac(\z80_|execute_|fMRead~7_combout ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~84_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~84 .lut_mask = 16'h8A00; +defparam \z80_|execute_|ctl_inc_cy~84 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|pla_decode_|Equal8~0_combout & \z80_|execute_|ctl_mWrite~4_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|pla_decode_|Equal8~0_combout ), + .datad(\z80_|execute_|ctl_mWrite~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~55 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~55_combout = ((\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ) # ((!\z80_|execute_|ctl_inc_cy~54_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ))) # (!\z80_|execute_|ctl_reg_sys_we~2_combout ) + + .dataa(\z80_|execute_|ctl_reg_sys_we~2_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), + .datad(\z80_|execute_|ctl_inc_cy~54_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~55_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~55 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_inc_cy~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y14_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~56 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~56_combout = (!\z80_|execute_|pc_inc_hold~17_combout & ((\z80_|execute_|ctl_inc_cy~53_combout ) # ((\z80_|execute_|ctl_inc_cy~84_combout ) # (\z80_|execute_|ctl_inc_cy~55_combout )))) + + .dataa(\z80_|execute_|ctl_inc_cy~53_combout ), + .datab(\z80_|execute_|ctl_inc_cy~84_combout ), + .datac(\z80_|execute_|pc_inc_hold~17_combout ), + .datad(\z80_|execute_|ctl_inc_cy~55_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~56_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~56 .lut_mask = 16'h0F0E; +defparam \z80_|execute_|ctl_inc_cy~56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~67 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~67_combout = (\z80_|execute_|ctl_inc_cy~58_combout ) # ((\z80_|execute_|ctl_inc_cy~51_combout ) # ((\z80_|execute_|ctl_inc_cy~66_combout ) # (\z80_|execute_|ctl_inc_cy~56_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~58_combout ), + .datab(\z80_|execute_|ctl_inc_cy~51_combout ), + .datac(\z80_|execute_|ctl_inc_cy~66_combout ), + .datad(\z80_|execute_|ctl_inc_cy~56_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~67_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~67 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_inc_cy~67 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y14_N20 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~20 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~20_combout = (\z80_|execute_|pc_inc_hold~19_combout ) # ((\z80_|execute_|pc_inc_hold~27_combout ) # ((\z80_|execute_|pc_inc_hold~15_combout ) # (!\z80_|execute_|pc_inc_hold~8_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~19_combout ), + .datab(\z80_|execute_|pc_inc_hold~27_combout ), + .datac(\z80_|execute_|pc_inc_hold~8_combout ), + .datad(\z80_|execute_|pc_inc_hold~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~20 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|pc_inc_hold~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y15_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~83 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~83_combout = (\z80_|execute_|ctl_state_alu~6_combout & (\z80_|sequencer_|DFFE_M2_ff~q & (!\z80_|execute_|pc_inc_hold~20_combout & \z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|execute_|ctl_state_alu~6_combout ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|execute_|pc_inc_hold~20_combout ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~83_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~83 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_inc_cy~83 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~68 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~68_combout = (\z80_|execute_|ctl_inc_cy~44_combout ) # ((\z80_|execute_|ctl_inc_cy~43_combout ) # ((\z80_|execute_|ctl_inc_cy~67_combout ) # (\z80_|execute_|ctl_inc_cy~83_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~44_combout ), + .datab(\z80_|execute_|ctl_inc_cy~43_combout ), + .datac(\z80_|execute_|ctl_inc_cy~67_combout ), + .datad(\z80_|execute_|ctl_inc_cy~83_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~68_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~68 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_inc_cy~68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N30 +cycloneive_lcell_comb \z80_|address_latch_|Q[0]~feeder ( +// Equation(s): +// \z80_|address_latch_|Q[0]~feeder_combout = \z80_|address_latch_|abusz [0] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [0]), + .cin(gnd), + .combout(\z80_|address_latch_|Q[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|Q[0]~feeder .lut_mask = 16'hFF00; +defparam \z80_|address_latch_|Q[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y11_N31 +dffeas \z80_|address_latch_|Q[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|Q[0]~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[0] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~72 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~72_combout = (\z80_|execute_|pc_inc_hold~16_combout & (\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout & (\z80_|execute_|ctl_inc_cy~41_combout & !\z80_|execute_|pc_inc_hold~21_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~16_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ), + .datac(\z80_|execute_|ctl_inc_cy~41_combout ), + .datad(\z80_|execute_|pc_inc_hold~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~72_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~72 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_inc_cy~72 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y18_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~73 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~73_combout = (\z80_|execute_|ixy_d~9_combout ) # ((\z80_|execute_|ctl_alu_oe~0_combout ) # ((\z80_|sequencer_|DFFE_M4_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|execute_|ixy_d~9_combout ), + .datac(\z80_|execute_|ctl_alu_oe~0_combout ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~73_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~73 .lut_mask = 16'hFEFC; +defparam \z80_|execute_|ctl_inc_cy~73 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y18_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~74 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~74_combout = ((\z80_|pla_decode_|Equal19~0_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # (\z80_|execute_|ctl_inc_cy~73_combout )))) # (!\z80_|execute_|ctl_inc_cy~86_combout ) + + .dataa(\z80_|execute_|ctl_inc_cy~86_combout ), + .datab(\z80_|pla_decode_|Equal19~0_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|execute_|ctl_inc_cy~73_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~74_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~74 .lut_mask = 16'hDDD5; +defparam \z80_|execute_|ctl_inc_cy~74 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~75 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~75_combout = (\z80_|execute_|ctl_inc_cy~72_combout ) # ((\z80_|execute_|ctl_inc_cy~74_combout & ((!\z80_|execute_|pc_inc_hold~17_combout ) # (!\z80_|execute_|pc_inc_hold~25_combout )))) + + .dataa(\z80_|execute_|ctl_inc_cy~72_combout ), + .datab(\z80_|execute_|pc_inc_hold~25_combout ), + .datac(\z80_|execute_|ctl_inc_cy~74_combout ), + .datad(\z80_|execute_|pc_inc_hold~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~75_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~75 .lut_mask = 16'hBAFA; +defparam \z80_|execute_|ctl_inc_cy~75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~76 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~76_combout = (((!\z80_|execute_|ctl_inc_cy~40_combout ) # (!\z80_|execute_|ctl_inc_cy~37_combout )) # (!\z80_|execute_|ctl_inc_cy~33_combout )) # (!\z80_|execute_|ctl_inc_cy~32_combout ) + + .dataa(\z80_|execute_|ctl_inc_cy~32_combout ), + .datab(\z80_|execute_|ctl_inc_cy~33_combout ), + .datac(\z80_|execute_|ctl_inc_cy~37_combout ), + .datad(\z80_|execute_|ctl_inc_cy~40_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~76_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~76 .lut_mask = 16'h7FFF; +defparam \z80_|execute_|ctl_inc_cy~76 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y18_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~80 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~80_combout = (\z80_|execute_|ctl_inc_cy~76_combout ) # ((!\z80_|execute_|ctl_inc_cy~36_combout ) # (!\z80_|execute_|ctl_inc_cy~79_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_inc_cy~76_combout ), + .datac(\z80_|execute_|ctl_inc_cy~79_combout ), + .datad(\z80_|execute_|ctl_inc_cy~36_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~80_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~80 .lut_mask = 16'hCFFF; +defparam \z80_|execute_|ctl_inc_cy~80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~81 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~81_combout = (\z80_|execute_|ctl_inc_cy~75_combout ) # ((\z80_|execute_|ctl_inc_cy~80_combout & ((\z80_|execute_|ctl_inc_cy~69_combout ) # (!\z80_|execute_|pc_inc_hold~17_combout )))) + + .dataa(\z80_|execute_|pc_inc_hold~17_combout ), + .datab(\z80_|execute_|ctl_inc_cy~69_combout ), + .datac(\z80_|execute_|ctl_inc_cy~75_combout ), + .datad(\z80_|execute_|ctl_inc_cy~80_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~81_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~81 .lut_mask = 16'hFDF0; +defparam \z80_|execute_|ctl_inc_cy~81 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N20 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout = \z80_|address_latch_|Q [0] $ (((\z80_|execute_|ctl_inc_cy~71_combout ) # ((\z80_|execute_|ctl_inc_cy~68_combout ) # (\z80_|execute_|ctl_inc_cy~81_combout )))) + + .dataa(\z80_|execute_|ctl_inc_cy~71_combout ), + .datab(\z80_|execute_|ctl_inc_cy~68_combout ), + .datac(\z80_|address_latch_|Q [0]), + .datad(\z80_|execute_|ctl_inc_cy~81_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out .lut_mask = 16'h0F1E; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N10 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~3 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[0]~3_combout = ((\z80_|reg_file_|db_lo_as[0]~1_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .datab(\z80_|reg_file_|db_lo_as[0]~1_combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), + .datad(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[0]~3 .lut_mask = 16'hC4FF; +defparam \z80_|reg_file_|db_lo_as[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y11_N1 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N10 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[0]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_lo|latch[0]~feeder_combout = \z80_|reg_file_|gdfx_temp0[0]~22_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[0]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y11_N11 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_af_lo|latch[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~13 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~13_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [0]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~13 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[0]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y14_N9 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~12 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~12_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [0] & ((\z80_|alu_control_|db[0]~12_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|alu_control_|db[0]~12_combout ) # ((!\z80_|execute_|ctl_reg_in_lo~8_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datab(\z80_|alu_control_|db[0]~12_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [0]), + .datad(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~12 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[0]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N8 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_lo|latch[0]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_de_lo|latch[0]~feeder_combout = \z80_|reg_file_|gdfx_temp0[0]~22_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_de_lo|latch[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[0]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y11_N9 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_de_lo|latch[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y11_N27 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~10 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~10_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [0] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [0] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [0]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~10 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp0[0]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y12_N3 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N2 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0_combout = ((\z80_|execute_|ctl_reg_gp_we~8_combout ) # ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]) # (!\z80_|reg_control_|reg_sel_hl2~0_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]), + .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0 .lut_mask = 16'hFDFF; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y12_N9 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~11 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~11_combout = (\z80_|reg_file_|gdfx_temp0[0]~10_combout & (\z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0_combout & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp0[0]~10_combout ), + .datab(\z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_hl_lo|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~11 .lut_mask = 16'h8088; +defparam \z80_|reg_file_|gdfx_temp0[0]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N2 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder_combout = \z80_|reg_file_|gdfx_temp0[0]~22_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y14_N3 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X32_Y13_N13 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~14 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~14_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (\z80_|reg_file_|b2v_latch_ix_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [0]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [0]), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~14 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[0]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y13_N11 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N20 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_sp_lo|latch[0]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_sp_lo|latch[0]~feeder_combout = \z80_|reg_file_|gdfx_temp0[0]~22_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_sp_lo|latch[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[0]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y12_N21 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_sp_lo|latch[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X31_Y12_N17 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~15 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~15_combout = (\z80_|reg_file_|b2v_latch_sp_lo|latch [0] & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # (!\z80_|reg_file_|b2v_latch_sp_lo|latch [0] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_sp_lo|latch [0]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_iy_lo|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~15 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp0[0]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~16 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~16_combout = (\z80_|reg_file_|gdfx_temp0[0]~14_combout & (\z80_|reg_file_|gdfx_temp0[0]~15_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp0[0]~14_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [0]), + .datad(\z80_|reg_file_|gdfx_temp0[0]~15_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~16 .lut_mask = 16'hA200; +defparam \z80_|reg_file_|gdfx_temp0[0]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~17 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~17_combout = (\z80_|reg_file_|gdfx_temp0[0]~13_combout & (\z80_|reg_file_|gdfx_temp0[0]~12_combout & (\z80_|reg_file_|gdfx_temp0[0]~11_combout & \z80_|reg_file_|gdfx_temp0[0]~16_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[0]~13_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~12_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[0]~11_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~16_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~17 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[0]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~22 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~22_combout = ((\z80_|reg_file_|gdfx_temp0[0]~17_combout & ((\z80_|reg_file_|db_lo_as[0]~3_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .datac(\z80_|reg_file_|db_lo_as[0]~3_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~17_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~22 .lut_mask = 16'hF733; +defparam \z80_|reg_file_|gdfx_temp0[0]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N22 +cycloneive_lcell_comb \z80_|alu_control_|db[0]~9 ( +// Equation(s): +// \z80_|alu_control_|db[0]~9_combout = (\z80_|sw2_|db_up[0]~0_combout & (\z80_|alu_control_|db[0]~8_combout & ((\z80_|reg_file_|gdfx_temp0[0]~22_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) + + .dataa(\z80_|sw2_|db_up[0]~0_combout ), + .datab(\z80_|alu_control_|db[0]~8_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[0]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[0]~9 .lut_mask = 16'h8088; +defparam \z80_|alu_control_|db[0]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N0 +cycloneive_lcell_comb \z80_|alu_control_|db[0]~12 ( +// Equation(s): +// \z80_|alu_control_|db[0]~12_combout = ((\z80_|alu_control_|db[0]~9_combout & ((\z80_|alu_flags_|flags_cf~combout ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) + + .dataa(\z80_|alu_flags_|flags_cf~combout ), + .datab(\z80_|execute_|ctl_flags_oe~2_combout ), + .datac(\z80_|alu_control_|db[0]~9_combout ), + .datad(\z80_|alu_control_|db[6]~11_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[0]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[0]~12 .lut_mask = 16'hB0FF; +defparam \z80_|alu_control_|db[0]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N2 +cycloneive_lcell_comb \z80_|address_latch_|abusz[8] ( +// Equation(s): +// \z80_|address_latch_|abusz [8] = (\z80_|reg_file_|db_hi_as[0]~6_combout & !\z80_|resets_|clrpc~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|reg_file_|db_hi_as[0]~6_combout ), + .datad(\z80_|resets_|clrpc~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [8]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[8] .lut_mask = 16'h00F0; +defparam \z80_|address_latch_|abusz[8] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y10_N3 +dffeas \z80_|address_latch_|Q[8] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [8]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [8]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[8] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N4 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout = \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout $ (\z80_|address_latch_|Q [7]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), + .datad(\z80_|address_latch_|Q [7]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out .lut_mask = 16'h0FF0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y12_N21 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y12_N11 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~84 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~84_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (\z80_|reg_file_|b2v_latch_hl_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl_lo|latch [7]), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~84_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~84 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp0[7]~84 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N20 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_lo|latch[7]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_de_lo|latch[7]~feeder_combout = \z80_|reg_file_|gdfx_temp0[7]~91_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_de_lo|latch[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[7]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y11_N21 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_de_lo|latch[7]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y11_N7 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~83 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~83_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [7] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [7] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [7]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~83_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~83 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp0[7]~83 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y12_N29 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~88 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~88_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [7] & ((\z80_|alu_control_|db[7]~19_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|alu_control_|db[7]~19_combout ) # ((!\z80_|execute_|ctl_reg_in_lo~8_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datab(\z80_|alu_control_|db[7]~19_combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [7]), + .datad(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~88_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~88 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[7]~88 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y14_N25 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X32_Y14_N23 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~86 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~86_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [7]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [7]), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~86_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~86 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[7]~86 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y12_N25 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X31_Y12_N27 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~87 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~87_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (\z80_|reg_file_|b2v_latch_ix_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [7]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_iy_lo|latch [7]), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~87_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~87 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[7]~87 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y12_N29 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N28 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_wz_lo|db[7]~0 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_wz_lo|db[7]~0_combout = (\z80_|reg_control_|reg_sys_we_lo~combout ) # (((\z80_|reg_file_|b2v_latch_wz_lo|latch [7]) # (!\z80_|execute_|ctl_reg_sel_wz~18_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[0]~31_combout )) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~31_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [7]), + .datad(\z80_|execute_|ctl_reg_sel_wz~18_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_wz_lo|db[7]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|db[7]~0 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_wz_lo|db[7]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~89 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~89_combout = (\z80_|reg_file_|gdfx_temp0[7]~88_combout & (\z80_|reg_file_|gdfx_temp0[7]~86_combout & (\z80_|reg_file_|gdfx_temp0[7]~87_combout & \z80_|reg_file_|b2v_latch_wz_lo|db[7]~0_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[7]~88_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[7]~86_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[7]~87_combout ), + .datad(\z80_|reg_file_|b2v_latch_wz_lo|db[7]~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~89_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~89 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[7]~89 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y11_N29 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X32_Y11_N7 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~85 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~85_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [7]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [7]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~85_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~85 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[7]~85 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~90 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~90_combout = (\z80_|reg_file_|gdfx_temp0[7]~84_combout & (\z80_|reg_file_|gdfx_temp0[7]~83_combout & (\z80_|reg_file_|gdfx_temp0[7]~89_combout & \z80_|reg_file_|gdfx_temp0[7]~85_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[7]~84_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[7]~83_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[7]~89_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[7]~85_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~90 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[7]~90 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~91 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~91_combout = ((\z80_|reg_file_|gdfx_temp0[7]~90_combout & ((\z80_|reg_file_|db_lo_as[7]~24_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .datac(\z80_|execute_|ctl_sw_4u~6_combout ), + .datad(\z80_|reg_file_|db_lo_as[7]~24_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~91 .lut_mask = 16'hBB3B; +defparam \z80_|reg_file_|gdfx_temp0[7]~91 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y12_N15 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[7]~24_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N14 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~22 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[7]~22_combout = (\z80_|reg_file_|gdfx_temp0[7]~91_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) # (!\z80_|reg_file_|gdfx_temp0[7]~91_combout & +// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [7]), + .datad(\z80_|execute_|ctl_sw_4d~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[7]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[7]~22 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|db_lo_as[7]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y12_N13 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[7]~24_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N18 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~23 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[7]~23_combout = (\z80_|reg_file_|db_lo_as[7]~22_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(\z80_|reg_file_|db_lo_as[7]~22_combout ), + .datab(gnd), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [7]), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[7]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[7]~23 .lut_mask = 16'hAA0A; +defparam \z80_|reg_file_|db_lo_as[7]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N12 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~24 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[7]~24_combout = ((\z80_|reg_file_|db_lo_as[7]~23_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), + .datab(\z80_|reg_file_|db_lo_as[7]~23_combout ), + .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[7]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[7]~24 .lut_mask = 16'h8FCF; +defparam \z80_|reg_file_|db_lo_as[7]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N6 +cycloneive_lcell_comb \z80_|address_latch_|abusz[7] ( +// Equation(s): +// \z80_|address_latch_|abusz [7] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[7]~24_combout ) + + .dataa(\z80_|resets_|clrpc~0_combout ), + .datab(gnd), + .datac(\z80_|reg_file_|db_lo_as[7]~24_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [7]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[7] .lut_mask = 16'h5050; +defparam \z80_|address_latch_|abusz[7] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N16 +cycloneive_lcell_comb \z80_|address_latch_|Q[7]~feeder ( +// Equation(s): +// \z80_|address_latch_|Q[7]~feeder_combout = \z80_|address_latch_|abusz [7] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [7]), + .cin(gnd), + .combout(\z80_|address_latch_|Q[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|Q[7]~feeder .lut_mask = 16'hFF00; +defparam \z80_|address_latch_|Q[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y13_N17 +dffeas \z80_|address_latch_|Q[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|Q[7]~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[7] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N10 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout = \z80_|address_latch_|Q [8] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout & (\z80_|execute_|ctl_inc_dec~11_combout $ (\z80_|address_latch_|Q [7]))))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), + .datab(\z80_|address_latch_|Q [8]), + .datac(\z80_|execute_|ctl_inc_dec~11_combout ), + .datad(\z80_|address_latch_|Q [7]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out .lut_mask = 16'hC66C; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y14_N23 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[0]~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X35_Y14_N29 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[0]~6_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N28 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~4 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[0]~4_combout = (\z80_|reg_control_|reg_sw_4d_hi~0_combout & (\z80_|reg_file_|gdfx_temp1[0]~30_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) + + .dataa(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [0]), + .datad(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[0]~4 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|db_hi_as[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N0 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~5 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[0]~5_combout = (\z80_|reg_file_|db_hi_as[0]~4_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [0]), + .datad(\z80_|reg_file_|db_hi_as[0]~4_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[0]~5 .lut_mask = 16'hF300; +defparam \z80_|reg_file_|db_hi_as[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N22 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~6 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[0]~6_combout = ((\z80_|reg_file_|db_hi_as[0]~5_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), + .datab(\z80_|reg_file_|db_hi_as[0]~5_combout ), + .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[0]~6 .lut_mask = 16'h8FCF; +defparam \z80_|reg_file_|db_hi_as[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y14_N27 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X37_Y14_N13 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~23 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~23_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (\z80_|reg_file_|b2v_latch_hl_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_hl2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (((\z80_|reg_file_|b2v_latch_hl2_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [0]), + .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~23 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[0]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y16_N27 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X35_Y16_N5 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~25 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~25_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_iy_hi|latch [0]), + .datad(\z80_|reg_file_|b2v_latch_ix_hi|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~25 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[0]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y15_N11 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X35_Y15_N13 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~27 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~27_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (\z80_|reg_file_|b2v_latch_wz_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (((\z80_|reg_file_|b2v_latch_sp_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .datab(\z80_|reg_file_|b2v_latch_wz_hi|latch [0]), + .datac(\z80_|reg_file_|b2v_latch_sp_hi|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~27 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[0]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y16_N27 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X37_Y16_N25 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~24 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~24_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (\z80_|reg_file_|b2v_latch_bc2_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc_hi|latch [0]), + .datad(\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~24 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[0]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y16_N27 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~26 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~26_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout & (\z80_|alu_|db[0]~14_combout & ((\z80_|reg_file_|b2v_latch_af2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # +// (!\z80_|execute_|ctl_reg_in_hi~12_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .datab(\z80_|alu_|db[0]~14_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~26 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[0]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~28 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~28_combout = (\z80_|reg_file_|gdfx_temp1[0]~25_combout & (\z80_|reg_file_|gdfx_temp1[0]~27_combout & (\z80_|reg_file_|gdfx_temp1[0]~24_combout & \z80_|reg_file_|gdfx_temp1[0]~26_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~25_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[0]~27_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~24_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[0]~26_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~28 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[0]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y15_N17 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N16 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[0]~11 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[0]~11_combout = (\z80_|execute_|ctl_reg_gp_we~8_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [0]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [0]), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[0]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[0]~11 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[0]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y15_N11 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N16 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_hi|latch[0]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_de_hi|latch[0]~feeder_combout = \z80_|reg_file_|gdfx_temp1[0]~30_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_de_hi|latch[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[0]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y15_N17 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_de_hi|latch[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~22 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~22_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [0]), + .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~22 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[0]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~29 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~29_combout = (\z80_|reg_file_|gdfx_temp1[0]~23_combout & (\z80_|reg_file_|gdfx_temp1[0]~28_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[0]~11_combout & \z80_|reg_file_|gdfx_temp1[0]~22_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~23_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[0]~28_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|db[0]~11_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[0]~22_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~29 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[0]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~30 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~30_combout = ((\z80_|reg_file_|gdfx_temp1[0]~29_combout & ((\z80_|reg_file_|db_hi_as[0]~6_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[0]~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[0]~29_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datad(\z80_|execute_|ctl_sw_4u~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~30 .lut_mask = 16'h8FCF; +defparam \z80_|reg_file_|gdfx_temp1[0]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N12 +cycloneive_lcell_comb \z80_|alu_|db[0]~13 ( +// Equation(s): +// \z80_|alu_|db[0]~13_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[0]~30_combout & ((\z80_|alu_|db_low[0]~24_combout ) # (!\z80_|execute_|ctl_alu_oe~11_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & +// (((\z80_|alu_|db_low[0]~24_combout ) # (!\z80_|execute_|ctl_alu_oe~11_combout )))) + + .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .datac(\z80_|alu_|db_low[0]~24_combout ), + .datad(\z80_|execute_|ctl_alu_oe~11_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[0]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[0]~13 .lut_mask = 16'hD0DD; +defparam \z80_|alu_|db[0]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N22 +cycloneive_lcell_comb \z80_|alu_|db[0]~14 ( +// Equation(s): +// \z80_|alu_|db[0]~14_combout = ((\z80_|alu_|db[0]~13_combout & ((\z80_|alu_control_|db[0]~12_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|alu_control_|db[0]~12_combout ), + .datab(\z80_|alu_|db[7]~9_combout ), + .datac(\z80_|execute_|ctl_sw_2d~13_combout ), + .datad(\z80_|alu_|db[0]~13_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[0]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[0]~14 .lut_mask = 16'hBF33; +defparam \z80_|alu_|db[0]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N12 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~10 ( +// Equation(s): +// \z80_|alu_|db_low[1]~10_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[2]~16_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[0]~14_combout ))) + + .dataa(\z80_|alu_|db[2]~16_combout ), + .datab(\z80_|alu_|db[0]~14_combout ), + .datac(gnd), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~10 .lut_mask = 16'hAACC; +defparam \z80_|alu_|db_low[1]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N10 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~11 ( +// Equation(s): +// \z80_|alu_|db_low[1]~11_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_low[1]~10_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[1]~10_combout )) + + .dataa(\z80_|alu_|db[1]~10_combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .datac(gnd), + .datad(\z80_|alu_|db_low[1]~10_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~11 .lut_mask = 16'hEE22; +defparam \z80_|alu_|db_low[1]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N22 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~8 ( +// Equation(s): +// \z80_|alu_|db_low[1]~8_combout = (\z80_|execute_|ctl_alu_op2_oe~0_combout & (\z80_|alu_|op2_low [1] & ((\z80_|alu_|op1_low [1]) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout & (((\z80_|alu_|op1_low [1]) # +// (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datab(\z80_|alu_|op2_low [1]), + .datac(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datad(\z80_|alu_|op1_low [1]), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~8 .lut_mask = 16'hDD0D; +defparam \z80_|alu_|db_low[1]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N2 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~7 ( +// Equation(s): +// \z80_|alu_|db_low[1]~7_combout = ((\z80_|bus_control_|db[3]~21_combout & (!\z80_|bus_control_|db[5]~15_combout & !\z80_|bus_control_|db[4]~19_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) + + .dataa(\z80_|bus_control_|db[3]~21_combout ), + .datab(\z80_|bus_control_|db[5]~15_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datad(\z80_|bus_control_|db[4]~19_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~7 .lut_mask = 16'h0F2F; +defparam \z80_|alu_|db_low[1]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N4 +cycloneive_lcell_comb \z80_|alu_|result_lo[1]~feeder ( +// Equation(s): +// \z80_|alu_|result_lo[1]~feeder_combout = \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|result_lo[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|result_lo[1]~feeder .lut_mask = 16'hFF00; +defparam \z80_|alu_|result_lo[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y18_N5 +dffeas \z80_|alu_|result_lo[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|result_lo[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_alu_op_low~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|result_lo [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|result_lo[1] .is_wysiwyg = "true"; +defparam \z80_|alu_|result_lo[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N4 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~9 ( +// Equation(s): +// \z80_|alu_|db_low[1]~9_combout = (\z80_|alu_|db_low[1]~8_combout & (\z80_|alu_|db_low[1]~7_combout & ((\z80_|execute_|ctl_alu_res_oe~3_combout ) # (\z80_|alu_|result_lo [1])))) + + .dataa(\z80_|alu_|db_low[1]~8_combout ), + .datab(\z80_|alu_|db_low[1]~7_combout ), + .datac(\z80_|execute_|ctl_alu_res_oe~3_combout ), + .datad(\z80_|alu_|result_lo [1]), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~9 .lut_mask = 16'h8880; +defparam \z80_|alu_|db_low[1]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N26 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~12 ( +// Equation(s): +// \z80_|alu_|db_low[1]~12_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout & (\z80_|alu_|db_low[1]~11_combout & ((\z80_|alu_|db_low[1]~9_combout )))) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout & (((\z80_|alu_|db_low[1]~9_combout ) # +// (!\z80_|alu_|db_high[3]~0_combout )))) + + .dataa(\z80_|alu_|db_low[1]~11_combout ), + .datab(\z80_|alu_|db_high[3]~0_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datad(\z80_|alu_|db_low[1]~9_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~12 .lut_mask = 16'hAF03; +defparam \z80_|alu_|db_low[1]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N2 +cycloneive_lcell_comb \z80_|alu_|db[1]~8 ( +// Equation(s): +// \z80_|alu_|db[1]~8_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[1]~21_combout & ((\z80_|alu_control_|db[1]~26_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & +// (((\z80_|alu_control_|db[1]~26_combout )) # (!\z80_|execute_|ctl_sw_2d~13_combout ))) + + .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .datab(\z80_|execute_|ctl_sw_2d~13_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .datad(\z80_|alu_control_|db[1]~26_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[1]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[1]~8 .lut_mask = 16'hF531; +defparam \z80_|alu_|db[1]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N18 +cycloneive_lcell_comb \z80_|alu_|db[1]~10 ( +// Equation(s): +// \z80_|alu_|db[1]~10_combout = ((\z80_|alu_|db[1]~8_combout & ((\z80_|alu_|db_low[1]~12_combout ) # (!\z80_|execute_|ctl_alu_oe~11_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|execute_|ctl_alu_oe~11_combout ), + .datab(\z80_|alu_|db[7]~9_combout ), + .datac(\z80_|alu_|db_low[1]~12_combout ), + .datad(\z80_|alu_|db[1]~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[1]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[1]~10 .lut_mask = 16'hF733; +defparam \z80_|alu_|db[1]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y16_N11 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~12 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~12_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout & (\z80_|alu_|db[1]~10_combout & ((\z80_|reg_file_|b2v_latch_af2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # +// (!\z80_|execute_|ctl_reg_in_hi~12_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .datab(\z80_|alu_|db[1]~10_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~12 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[1]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N4 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder_combout = \z80_|reg_file_|gdfx_temp1[1]~21_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y16_N5 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X35_Y16_N1 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~11 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~11_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datab(\z80_|reg_file_|b2v_latch_iy_hi|latch [1]), + .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~11 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[1]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y16_N11 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X37_Y16_N17 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~10 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~10_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (\z80_|reg_file_|b2v_latch_bc2_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]), + .datad(\z80_|reg_file_|b2v_latch_bc_hi|latch [1]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~10 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[1]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y15_N3 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X35_Y15_N1 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~13 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~13_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (\z80_|reg_file_|b2v_latch_wz_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [1]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [1]), + .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~13 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp1[1]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~14 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~14_combout = (\z80_|reg_file_|gdfx_temp1[1]~12_combout & (\z80_|reg_file_|gdfx_temp1[1]~11_combout & (\z80_|reg_file_|gdfx_temp1[1]~10_combout & \z80_|reg_file_|gdfx_temp1[1]~13_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[1]~12_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[1]~11_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[1]~10_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[1]~13_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~14 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[1]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y15_N25 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N24 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[1]~10 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[1]~10_combout = (\z80_|execute_|ctl_reg_gp_we~8_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [1]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [1]), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[1]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[1]~10 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[1]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y14_N29 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X37_Y14_N11 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~9 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~9_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (\z80_|reg_file_|b2v_latch_hl_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_hl2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (((\z80_|reg_file_|b2v_latch_hl2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [1]), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~9 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[1]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y15_N7 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N20 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_hi|latch[1]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_de_hi|latch[1]~feeder_combout = \z80_|reg_file_|gdfx_temp1[1]~21_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_de_hi|latch[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[1]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y15_N21 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_de_hi|latch[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~8 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~8_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [1]), + .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [1]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~8 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[1]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~15 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~15_combout = (\z80_|reg_file_|gdfx_temp1[1]~14_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[1]~10_combout & (\z80_|reg_file_|gdfx_temp1[1]~9_combout & \z80_|reg_file_|gdfx_temp1[1]~8_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[1]~14_combout ), + .datab(\z80_|reg_file_|b2v_latch_af_hi|db[1]~10_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[1]~9_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[1]~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~15 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~21 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~21_combout = ((\z80_|reg_file_|gdfx_temp1[1]~15_combout & ((\z80_|reg_file_|db_hi_as[1]~3_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[1]~15_combout ), + .datac(\z80_|reg_file_|db_hi_as[1]~3_combout ), + .datad(\z80_|execute_|ctl_sw_4u~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~21 .lut_mask = 16'hD5DD; +defparam \z80_|reg_file_|gdfx_temp1[1]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y14_N25 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[1]~3_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N24 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~0 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[1]~0_combout = (\z80_|reg_file_|gdfx_temp1[1]~21_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # (!\z80_|reg_file_|gdfx_temp1[1]~21_combout & +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[1]~0 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|db_hi_as[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N20 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~1 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[1]~1_combout = (\z80_|reg_file_|db_hi_as[1]~0_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_pc_hi|latch [1]), + .datab(\z80_|reg_file_|db_hi_as[1]~0_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[1]~1 .lut_mask = 16'h88CC; +defparam \z80_|reg_file_|db_hi_as[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N30 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~3 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[1]~3_combout = ((\z80_|reg_file_|db_hi_as[1]~1_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), + .datab(\z80_|reg_file_|db_hi_as[1]~1_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .datad(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[1]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[1]~3 .lut_mask = 16'h8CFF; +defparam \z80_|reg_file_|db_hi_as[1]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N24 +cycloneive_lcell_comb \z80_|address_latch_|abusz[9] ( +// Equation(s): +// \z80_|address_latch_|abusz [9] = (\z80_|reg_file_|db_hi_as[1]~3_combout & !\z80_|resets_|clrpc~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|reg_file_|db_hi_as[1]~3_combout ), + .datad(\z80_|resets_|clrpc~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [9]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[9] .lut_mask = 16'h00F0; +defparam \z80_|address_latch_|abusz[9] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N22 +cycloneive_lcell_comb \z80_|address_latch_|Q[9]~feeder ( +// Equation(s): +// \z80_|address_latch_|Q[9]~feeder_combout = \z80_|address_latch_|abusz [9] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [9]), + .cin(gnd), + .combout(\z80_|address_latch_|Q[9]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|Q[9]~feeder .lut_mask = 16'hFF00; +defparam \z80_|address_latch_|Q[9]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y10_N23 +dffeas \z80_|address_latch_|Q[9] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|Q[9]~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [9]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[9] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N26 +cycloneive_lcell_comb \z80_|address_latch_|abusz[10] ( +// Equation(s): +// \z80_|address_latch_|abusz [10] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[2]~9_combout ) + + .dataa(\z80_|resets_|clrpc~0_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|db_hi_as[2]~9_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [10]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[10] .lut_mask = 16'h5500; +defparam \z80_|address_latch_|abusz[10] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y13_N27 +dffeas \z80_|address_latch_|Q[10] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [10]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [10]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[10] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N12 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout = \z80_|address_latch_|Q [10] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout & (\z80_|execute_|ctl_inc_dec~11_combout $ +// (\z80_|address_latch_|Q [9]))))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), + .datab(\z80_|execute_|ctl_inc_dec~11_combout ), + .datac(\z80_|address_latch_|Q [9]), + .datad(\z80_|address_latch_|Q [10]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out .lut_mask = 16'hD728; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y14_N13 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[2]~9_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N12 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~7 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[2]~7_combout = (\z80_|reg_file_|gdfx_temp1[2]~39_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # (!\z80_|reg_file_|gdfx_temp1[2]~39_combout & +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[2]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[2]~7 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|db_hi_as[2]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y14_N19 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[2]~9_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N8 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~8 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[2]~8_combout = (\z80_|reg_file_|db_hi_as[2]~7_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|db_hi_as[2]~7_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datac(gnd), + .datad(\z80_|reg_file_|b2v_latch_pc_hi|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[2]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[2]~8 .lut_mask = 16'hAA22; +defparam \z80_|reg_file_|db_hi_as[2]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N18 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~9 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[2]~9_combout = ((\z80_|reg_file_|db_hi_as[2]~8_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .datac(\z80_|reg_file_|db_hi_as[2]~8_combout ), + .datad(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[2]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[2]~9 .lut_mask = 16'hB0FF; +defparam \z80_|reg_file_|db_hi_as[2]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~39 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~39_combout = ((\z80_|reg_file_|gdfx_temp1[2]~38_combout & ((\z80_|reg_file_|db_hi_as[2]~9_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[2]~38_combout ), + .datac(\z80_|reg_file_|db_hi_as[2]~9_combout ), + .datad(\z80_|execute_|ctl_sw_4u~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~39 .lut_mask = 16'hD5DD; +defparam \z80_|reg_file_|gdfx_temp1[2]~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N24 +cycloneive_lcell_comb \z80_|alu_|db[2]~15 ( +// Equation(s): +// \z80_|alu_|db[2]~15_combout = (\z80_|execute_|ctl_sw_2d~13_combout & (\z80_|alu_control_|db[2]~29_combout & ((\z80_|reg_file_|gdfx_temp1[2]~39_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) # (!\z80_|execute_|ctl_sw_2d~13_combout & +// ((\z80_|reg_file_|gdfx_temp1[2]~39_combout ) # ((!\z80_|execute_|ctl_reg_out_hi~7_combout )))) + + .dataa(\z80_|execute_|ctl_sw_2d~13_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .datac(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .datad(\z80_|alu_control_|db[2]~29_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[2]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[2]~15 .lut_mask = 16'hCF45; +defparam \z80_|alu_|db[2]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N4 +cycloneive_lcell_comb \z80_|alu_|db[2]~16 ( +// Equation(s): +// \z80_|alu_|db[2]~16_combout = ((\z80_|alu_|db[2]~15_combout & ((\z80_|alu_|db_low[2]~23_combout ) # (!\z80_|execute_|ctl_alu_oe~11_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|execute_|ctl_alu_oe~11_combout ), + .datab(\z80_|alu_|db[2]~15_combout ), + .datac(\z80_|alu_|db[7]~9_combout ), + .datad(\z80_|alu_|db_low[2]~23_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[2]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[2]~16 .lut_mask = 16'hCF4F; +defparam \z80_|alu_|db[2]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N24 +cycloneive_lcell_comb \z80_|alu_control_|db[2]~27 ( +// Equation(s): +// \z80_|alu_control_|db[2]~27_combout = (\z80_|alu_|db[2]~16_combout & (!\z80_|alu_flags_|DFFE_inst_latch_pf~q & ((\z80_|execute_|ctl_flags_oe~2_combout )))) # (!\z80_|alu_|db[2]~16_combout & ((\z80_|execute_|ctl_sw_2u~7_combout ) # +// ((!\z80_|alu_flags_|DFFE_inst_latch_pf~q & \z80_|execute_|ctl_flags_oe~2_combout )))) + + .dataa(\z80_|alu_|db[2]~16_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), + .datac(\z80_|execute_|ctl_sw_2u~7_combout ), + .datad(\z80_|execute_|ctl_flags_oe~2_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[2]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[2]~27 .lut_mask = 16'h7350; +defparam \z80_|alu_control_|db[2]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N0 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~2 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf~2_combout = (\z80_|execute_|ctl_flags_alu~15_combout & !\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_flags_alu~15_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~2 .lut_mask = 16'h0C0C; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N26 +cycloneive_lcell_comb \z80_|alu_flags_|flags_hf2~0 ( +// Equation(s): +// \z80_|alu_flags_|flags_hf2~0_combout = (\z80_|execute_|ctl_flags_hf2_we~combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ) # ((\z80_|alu_control_|db[4]~32_combout )))) # (!\z80_|execute_|ctl_flags_hf2_we~combout & +// (((\z80_|alu_flags_|flags_hf2~q )))) + + .dataa(\z80_|execute_|ctl_flags_hf2_we~combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ), + .datac(\z80_|alu_flags_|flags_hf2~q ), + .datad(\z80_|alu_control_|db[4]~32_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|flags_hf2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|flags_hf2~0 .lut_mask = 16'hFAD8; +defparam \z80_|alu_flags_|flags_hf2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y18_N27 +dffeas \z80_|alu_flags_|flags_hf2 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|flags_hf2~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|flags_hf2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|flags_hf2 .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|flags_hf2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N30 +cycloneive_lcell_comb \z80_|alu_control_|db[2]~23 ( +// Equation(s): +// \z80_|alu_control_|db[2]~23_combout = ((\z80_|alu_flags_|flags_hf2~q ) # ((\z80_|alu_control_|out[6]~0_combout ) # (\z80_|execute_|ctl_66_oe~combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datab(\z80_|alu_flags_|flags_hf2~q ), + .datac(\z80_|alu_control_|out[6]~0_combout ), + .datad(\z80_|execute_|ctl_66_oe~combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[2]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[2]~23 .lut_mask = 16'hFFFD; +defparam \z80_|alu_control_|db[2]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N30 +cycloneive_lcell_comb \z80_|alu_control_|db[2]~29 ( +// Equation(s): +// \z80_|alu_control_|db[2]~29_combout = ((\z80_|alu_control_|db[2]~28_combout & (!\z80_|alu_control_|db[2]~27_combout & \z80_|alu_control_|db[2]~23_combout ))) # (!\z80_|alu_control_|db[6]~11_combout ) + + .dataa(\z80_|alu_control_|db[2]~28_combout ), + .datab(\z80_|alu_control_|db[2]~27_combout ), + .datac(\z80_|alu_control_|db[2]~23_combout ), + .datad(\z80_|alu_control_|db[6]~11_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[2]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[2]~29 .lut_mask = 16'h20FF; +defparam \z80_|alu_control_|db[2]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~39 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~39_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout & (\z80_|alu_control_|db[2]~29_combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) # +// (!\z80_|execute_|ctl_reg_in_lo~8_combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [2]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datab(\z80_|reg_file_|b2v_latch_sp_lo|latch [2]), + .datac(\z80_|alu_control_|db[2]~29_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~39 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[2]~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y11_N3 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X32_Y11_N21 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~35 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~35_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [2]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~35 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[2]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~40 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~40_combout = (\z80_|reg_file_|gdfx_temp0[2]~37_combout & (\z80_|reg_file_|gdfx_temp0[2]~38_combout & (\z80_|reg_file_|gdfx_temp0[2]~39_combout & \z80_|reg_file_|gdfx_temp0[2]~35_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[2]~37_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[2]~38_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[2]~39_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[2]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~40 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[2]~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~41 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~41_combout = (\z80_|reg_file_|gdfx_temp0[2]~33_combout & (\z80_|reg_file_|gdfx_temp0[2]~34_combout & \z80_|reg_file_|gdfx_temp0[2]~40_combout )) + + .dataa(\z80_|reg_file_|gdfx_temp0[2]~33_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[2]~34_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[2]~40_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~41 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|gdfx_temp0[2]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~42 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~42_combout = ((\z80_|reg_file_|gdfx_temp0[2]~41_combout & ((\z80_|reg_file_|db_lo_as[2]~9_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .datad(\z80_|reg_file_|db_lo_as[2]~9_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~42 .lut_mask = 16'hCF4F; +defparam \z80_|reg_file_|gdfx_temp0[2]~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y12_N15 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[2]~9_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N14 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~7 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[2]~7_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[2]~42_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # +// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[2]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[2]~7 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_lo_as[2]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N6 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~8 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[2]~8_combout = (\z80_|reg_file_|db_lo_as[2]~7_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_ir_lo|latch [2]), + .datab(gnd), + .datac(\z80_|reg_file_|db_lo_as[2]~7_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[2]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[2]~8 .lut_mask = 16'hA0F0; +defparam \z80_|reg_file_|db_lo_as[2]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N4 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout = \z80_|address_latch_|Q [0] $ (((\z80_|execute_|ctl_inc_dec~9_combout ) # ((\z80_|execute_|ctl_inc_dec~7_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout )))) + + .dataa(\z80_|execute_|ctl_inc_dec~9_combout ), + .datab(\z80_|address_latch_|Q [0]), + .datac(\z80_|execute_|ctl_inc_dec~6_combout ), + .datad(\z80_|execute_|ctl_inc_dec~7_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 .lut_mask = 16'h3363; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N26 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout & ((\z80_|execute_|ctl_inc_cy~71_combout ) # ((\z80_|execute_|ctl_inc_cy~81_combout ) # +// (\z80_|execute_|ctl_inc_cy~68_combout )))) + + .dataa(\z80_|execute_|ctl_inc_cy~71_combout ), + .datab(\z80_|execute_|ctl_inc_cy~81_combout ), + .datac(\z80_|execute_|ctl_inc_cy~68_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'hFE00; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N0 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout = \z80_|address_latch_|Q [2] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout & +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout ))) + + .dataa(\z80_|address_latch_|Q [2]), + .datab(gnd), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out .lut_mask = 16'h5AAA; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N8 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~9 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[2]~9_combout = ((\z80_|reg_file_|db_lo_as[2]~8_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|reg_file_|db_lo_as[2]~8_combout ), + .datab(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[2]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[2]~9 .lut_mask = 16'hBB3B; +defparam \z80_|reg_file_|db_lo_as[2]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N8 +cycloneive_lcell_comb \z80_|address_latch_|abusz[2] ( +// Equation(s): +// \z80_|address_latch_|abusz [2] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[2]~9_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(\z80_|reg_file_|db_lo_as[2]~9_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [2]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[2] .lut_mask = 16'h0F00; +defparam \z80_|address_latch_|abusz[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y11_N9 +dffeas \z80_|address_latch_|Q[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [2]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[2] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N18 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout = \z80_|address_latch_|Q [2] $ ((((\z80_|execute_|ctl_inc_dec~10_combout ) # (!\z80_|execute_|ctl_inc_dec~5_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~42_combout ))) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~42_combout ), + .datab(\z80_|address_latch_|Q [2]), + .datac(\z80_|execute_|ctl_inc_dec~10_combout ), + .datad(\z80_|execute_|ctl_inc_dec~5_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42 .lut_mask = 16'h3933; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y12_N25 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[3]~12_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N24 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~10 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[3]~10_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[3]~52_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # +// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[3]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[3]~10 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_lo_as[3]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y12_N31 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[3]~12_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N28 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~11 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[3]~11_combout = (\z80_|reg_file_|db_lo_as[3]~10_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .datab(\z80_|reg_file_|db_lo_as[3]~10_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [3]), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[3]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[3]~11 .lut_mask = 16'hCC44; +defparam \z80_|reg_file_|db_lo_as[3]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N26 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout = \z80_|address_latch_|Q [3] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout & +// (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout )))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout ), + .datab(\z80_|address_latch_|Q [3]), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out .lut_mask = 16'h6CCC; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N30 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~12 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[3]~12_combout = ((\z80_|reg_file_|db_lo_as[3]~11_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .datab(\z80_|reg_file_|db_lo_as[3]~11_combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), + .datad(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[3]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[3]~12 .lut_mask = 16'hC4FF; +defparam \z80_|reg_file_|db_lo_as[3]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N14 +cycloneive_lcell_comb \z80_|address_latch_|abusz[3] ( +// Equation(s): +// \z80_|address_latch_|abusz [3] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[3]~12_combout ) + + .dataa(gnd), + .datab(\z80_|resets_|clrpc~0_combout ), + .datac(\z80_|reg_file_|db_lo_as[3]~12_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [3]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[3] .lut_mask = 16'h3030; +defparam \z80_|address_latch_|abusz[3] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y11_N15 +dffeas \z80_|address_latch_|Q[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [3]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[3] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N24 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout = \z80_|address_latch_|Q [3] $ ((((\z80_|execute_|ctl_inc_dec~10_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~42_combout )) # (!\z80_|execute_|ctl_inc_dec~5_combout ))) + + .dataa(\z80_|execute_|ctl_inc_dec~5_combout ), + .datab(\z80_|address_latch_|Q [3]), + .datac(\z80_|execute_|ctl_inc_dec~10_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~42_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4 .lut_mask = 16'h3933; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N10 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout & +// (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout ))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 .lut_mask = 16'h8000; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N16 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout = (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|address_latch_|Q [6] $ (((\z80_|execute_|ctl_inc_dec~7_combout ) # (\z80_|execute_|ctl_inc_dec~10_combout ))))) + + .dataa(\z80_|address_latch_|Q [6]), + .datab(\z80_|execute_|ctl_inc_dec~7_combout ), + .datac(\z80_|execute_|ctl_inc_dec~10_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 .lut_mask = 16'h0056; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N14 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout & +// (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 .lut_mask = 16'h8000; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N22 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout & ((\z80_|address_latch_|Q [8] & (!\z80_|execute_|ctl_inc_dec~11_combout & \z80_|address_latch_|Q +// [7])) # (!\z80_|address_latch_|Q [8] & (\z80_|execute_|ctl_inc_dec~11_combout & !\z80_|address_latch_|Q [7])))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), + .datab(\z80_|address_latch_|Q [8]), + .datac(\z80_|execute_|ctl_inc_dec~11_combout ), + .datad(\z80_|address_latch_|Q [7]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 .lut_mask = 16'h0820; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N28 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout & ((\z80_|execute_|ctl_inc_dec~11_combout & (!\z80_|address_latch_|Q [9] & +// !\z80_|address_latch_|Q [10])) # (!\z80_|execute_|ctl_inc_dec~11_combout & (\z80_|address_latch_|Q [9] & \z80_|address_latch_|Q [10])))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), + .datab(\z80_|execute_|ctl_inc_dec~11_combout ), + .datac(\z80_|address_latch_|Q [9]), + .datad(\z80_|address_latch_|Q [10]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 .lut_mask = 16'h2008; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N26 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[11] ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|address [11] = \z80_|address_latch_|Q [11] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|address_latch_|Q [11]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[11] .lut_mask = 16'h0FF0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[11] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N4 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~12 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[3]~12_combout = ((\z80_|reg_file_|db_hi_as[3]~11_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [11]) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .datac(\z80_|reg_file_|db_hi_as[3]~11_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[3]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[3]~12 .lut_mask = 16'hF575; +defparam \z80_|reg_file_|db_hi_as[3]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y14_N17 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X37_Y14_N31 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~41 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~41_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (\z80_|reg_file_|b2v_latch_hl_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_hl2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (((\z80_|reg_file_|b2v_latch_hl2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [3]), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~41 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[3]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y15_N5 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X35_Y15_N7 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~45 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~45_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (\z80_|reg_file_|b2v_latch_wz_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (((\z80_|reg_file_|b2v_latch_sp_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [3]), + .datad(\z80_|reg_file_|b2v_latch_sp_hi|latch [3]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~45 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[3]~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y16_N23 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~44 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~44_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout & (\z80_|alu_|db[3]~20_combout & ((\z80_|reg_file_|b2v_latch_af2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # +// (!\z80_|execute_|ctl_reg_in_hi~12_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .datab(\z80_|alu_|db[3]~20_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~44 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[3]~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y16_N19 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y16_N9 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~43 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~43_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [3]), + .datad(\z80_|reg_file_|b2v_latch_iy_hi|latch [3]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~43 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[3]~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y16_N9 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X37_Y16_N7 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~42 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~42_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (\z80_|reg_file_|b2v_latch_bc2_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [3]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_bc_hi|latch [3]), + .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~42 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp1[3]~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~46 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~46_combout = (\z80_|reg_file_|gdfx_temp1[3]~45_combout & (\z80_|reg_file_|gdfx_temp1[3]~44_combout & (\z80_|reg_file_|gdfx_temp1[3]~43_combout & \z80_|reg_file_|gdfx_temp1[3]~42_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[3]~45_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[3]~44_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[3]~43_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[3]~42_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~46 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[3]~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N8 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_hi|latch[3]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_de_hi|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp1[3]~48_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_de_hi|latch[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[3]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y15_N9 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_de_hi|latch[3]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X37_Y15_N27 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~40 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~40_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datab(\z80_|reg_file_|b2v_latch_de_hi|latch [3]), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~40 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[3]~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y15_N21 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N10 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[3]~13 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[3]~13_combout = (\z80_|execute_|ctl_reg_gp_we~8_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [3]) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout )) # (!\z80_|reg_control_|reg_sel_af~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(\z80_|reg_control_|reg_sel_af~0_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datad(\z80_|reg_file_|b2v_latch_af_hi|latch [3]), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[3]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[3]~13 .lut_mask = 16'hFFBF; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[3]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~47 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~47_combout = (\z80_|reg_file_|gdfx_temp1[3]~41_combout & (\z80_|reg_file_|gdfx_temp1[3]~46_combout & (\z80_|reg_file_|gdfx_temp1[3]~40_combout & \z80_|reg_file_|b2v_latch_af_hi|db[3]~13_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[3]~41_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[3]~46_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[3]~40_combout ), + .datad(\z80_|reg_file_|b2v_latch_af_hi|db[3]~13_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~47 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[3]~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~48 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~48_combout = ((\z80_|reg_file_|gdfx_temp1[3]~47_combout & ((\z80_|reg_file_|db_hi_as[3]~12_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[3]~12_combout ), + .datab(\z80_|execute_|ctl_sw_4u~6_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[3]~47_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~48 .lut_mask = 16'hBF0F; +defparam \z80_|reg_file_|gdfx_temp1[3]~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N6 +cycloneive_lcell_comb \z80_|alu_|db[3]~19 ( +// Equation(s): +// \z80_|alu_|db[3]~19_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[3]~48_combout & ((\z80_|alu_|db_low[3]~25_combout ) # (!\z80_|execute_|ctl_alu_oe~11_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & +// ((\z80_|alu_|db_low[3]~25_combout ) # ((!\z80_|execute_|ctl_alu_oe~11_combout )))) + + .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .datab(\z80_|alu_|db_low[3]~25_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .datad(\z80_|execute_|ctl_alu_oe~11_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[3]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[3]~19 .lut_mask = 16'hC4F5; +defparam \z80_|alu_|db[3]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N28 +cycloneive_lcell_comb \z80_|alu_|db[3]~20 ( +// Equation(s): +// \z80_|alu_|db[3]~20_combout = ((\z80_|alu_|db[3]~19_combout & ((\z80_|alu_control_|db[3]~35_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|alu_control_|db[3]~35_combout ), + .datab(\z80_|alu_|db[7]~9_combout ), + .datac(\z80_|execute_|ctl_sw_2d~13_combout ), + .datad(\z80_|alu_|db[3]~19_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[3]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[3]~20 .lut_mask = 16'hBF33; +defparam \z80_|alu_|db[3]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N18 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~21 ( +// Equation(s): +// \z80_|alu_|db_low[2]~21_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[3]~20_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[1]~10_combout ))) + + .dataa(\z80_|alu_|db[3]~20_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(gnd), + .datad(\z80_|alu_|db[1]~10_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[2]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[2]~21 .lut_mask = 16'hBB88; +defparam \z80_|alu_|db_low[2]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N12 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~22 ( +// Equation(s): +// \z80_|alu_|db_low[2]~22_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_low[2]~21_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[2]~16_combout ))) + + .dataa(gnd), + .datab(\z80_|alu_|db_low[2]~21_combout ), + .datac(\z80_|alu_|db[2]~16_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[2]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[2]~22 .lut_mask = 16'hCCF0; +defparam \z80_|alu_|db_low[2]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y17_N1 +dffeas \z80_|alu_|result_lo[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_alu_op_low~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|result_lo [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|result_lo[2] .is_wysiwyg = "true"; +defparam \z80_|alu_|result_lo[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N10 +cycloneive_lcell_comb \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 ( +// Equation(s): +// \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout = (\z80_|bus_control_|db[4]~19_combout & !\z80_|bus_control_|db[3]~21_combout ) + + .dataa(gnd), + .datab(\z80_|bus_control_|db[4]~19_combout ), + .datac(\z80_|bus_control_|db[3]~21_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 .lut_mask = 16'h0C0C; +defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N22 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~6 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~6_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [2])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [2]))))) + + .dataa(\z80_|alu_|op1_low [2]), + .datab(\z80_|execute_|ctl_alu_op_low~combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datad(\z80_|alu_|op1_high [2]), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~6 .lut_mask = 16'hB080; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N30 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~7 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~7_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~6_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~8_combout & \z80_|alu_|db_low[2]~23_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datac(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~6_combout ), + .datad(\z80_|alu_|db_low[2]~23_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~7 .lut_mask = 16'h3230; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y18_N31 +dffeas \z80_|alu_|op2_low[2] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~7_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_low [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_low[2] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_low[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N6 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~18 ( +// Equation(s): +// \z80_|alu_|db_low[2]~18_combout = (\z80_|execute_|ctl_alu_op2_oe~0_combout & (\z80_|alu_|op2_low [2] & ((\z80_|alu_|op1_low [2]) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_low [2]) # +// ((!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datab(\z80_|alu_|op1_low [2]), + .datac(\z80_|alu_|op2_low [2]), + .datad(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[2]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[2]~18 .lut_mask = 16'hC4F5; +defparam \z80_|alu_|db_low[2]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N22 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~19 ( +// Equation(s): +// \z80_|alu_|db_low[2]~19_combout = (\z80_|alu_|db_low[2]~18_combout & (((\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout & !\z80_|bus_control_|db[5]~15_combout )) # (!\z80_|execute_|ctl_alu_bs_oe~combout ))) + + .dataa(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), + .datab(\z80_|bus_control_|db[5]~15_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datad(\z80_|alu_|db_low[2]~18_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[2]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[2]~19 .lut_mask = 16'h2F00; +defparam \z80_|alu_|db_low[2]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N0 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~20 ( +// Equation(s): +// \z80_|alu_|db_low[2]~20_combout = (\z80_|alu_|db_low[2]~19_combout & ((\z80_|execute_|ctl_alu_res_oe~3_combout ) # (\z80_|alu_|result_lo [2]))) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_res_oe~3_combout ), + .datac(\z80_|alu_|result_lo [2]), + .datad(\z80_|alu_|db_low[2]~19_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[2]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[2]~20 .lut_mask = 16'hFC00; +defparam \z80_|alu_|db_low[2]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N2 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~23 ( +// Equation(s): +// \z80_|alu_|db_low[2]~23_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout & (\z80_|alu_|db_low[2]~22_combout & ((\z80_|alu_|db_low[2]~20_combout )))) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout & (((\z80_|alu_|db_low[2]~20_combout ) # +// (!\z80_|alu_|db_high[3]~0_combout )))) + + .dataa(\z80_|alu_|db_low[2]~22_combout ), + .datab(\z80_|alu_|db_high[3]~0_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datad(\z80_|alu_|db_low[2]~20_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[2]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[2]~23 .lut_mask = 16'hAF03; +defparam \z80_|alu_|db_low[2]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N2 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~7 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~7_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & ((\z80_|alu_|db_low[2]~23_combout ) # ((\z80_|alu_|db_high[2]~13_combout & \z80_|execute_|ctl_alu_op1_sel_low~combout )))) # +// (!\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & (((\z80_|alu_|db_high[2]~13_combout & \z80_|execute_|ctl_alu_op1_sel_low~combout )))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datab(\z80_|alu_|db_low[2]~23_combout ), + .datac(\z80_|alu_|db_high[2]~13_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~7 .lut_mask = 16'hF888; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N10 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~8 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~8_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~7_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .datad(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~7_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~8 .lut_mask = 16'h0F00; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y17_N11 +dffeas \z80_|alu_|op1_low[2] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~8_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_low [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_low[2] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_low[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N26 +cycloneive_lcell_comb \z80_|alu_|alu_op1[2]~1 ( +// Equation(s): +// \z80_|alu_|alu_op1[2]~1_combout = (\z80_|execute_|ctl_alu_op_low~41_combout & (\z80_|alu_|op1_low [2])) # (!\z80_|execute_|ctl_alu_op_low~41_combout & ((\z80_|execute_|ctl_alu_op_low~29_combout & ((\z80_|alu_|op1_high [2]))) # +// (!\z80_|execute_|ctl_alu_op_low~29_combout & (\z80_|alu_|op1_low [2])))) + + .dataa(\z80_|alu_|op1_low [2]), + .datab(\z80_|execute_|ctl_alu_op_low~41_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~29_combout ), + .datad(\z80_|alu_|op1_high [2]), + .cin(gnd), + .combout(\z80_|alu_|alu_op1[2]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op1[2]~1 .lut_mask = 16'hBA8A; +defparam \z80_|alu_|alu_op1[2]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N30 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout = (\z80_|execute_|ctl_alu_core_S~combout ) # ((\z80_|alu_|alu_op1[2]~1_combout & \z80_|alu_|alu_op2[2]~0_combout )) + + .dataa(\z80_|alu_|alu_op1[2]~1_combout ), + .datab(gnd), + .datac(\z80_|alu_|alu_op2[2]~0_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hFFA0; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N8 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout = (!\z80_|alu_|alu_op2[2]~0_combout & ((\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_low [2])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_high +// [2]))))) + + .dataa(\z80_|alu_|alu_op2[2]~0_combout ), + .datab(\z80_|alu_|op1_low [2]), + .datac(\z80_|alu_|op1_high [2]), + .datad(\z80_|execute_|ctl_alu_op_low~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h1105; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N20 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout = (!\z80_|execute_|ctl_alu_core_R~combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ) # +// ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout & !\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout )))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), + .datab(\z80_|execute_|ctl_alu_core_R~combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 .lut_mask = 16'h3031; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N16 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ) # +// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), + .datab(\z80_|execute_|ctl_alu_core_R~combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 .lut_mask = 16'hDCDD; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N20 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout = (!\z80_|alu_|alu_op2[3]~2_combout & ((\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_low [3])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_high +// [3]))))) + + .dataa(\z80_|alu_|op1_low [3]), + .datab(\z80_|alu_|alu_op2[3]~2_combout ), + .datac(\z80_|alu_|op1_high [3]), + .datad(\z80_|execute_|ctl_alu_op_low~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h1103; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N10 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ) # +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout )))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .datac(\z80_|execute_|ctl_alu_core_R~combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0 .lut_mask = 16'hF5F4; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N6 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_hf~0 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_hf~0_combout = (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & (\z80_|execute_|ctl_flags_bus~combout & ((\z80_|alu_control_|db[4]~32_combout )))) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout +// & ((\z80_|execute_|ctl_flags_alu~15_combout ) # ((\z80_|execute_|ctl_flags_bus~combout & \z80_|alu_control_|db[4]~32_combout )))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), + .datab(\z80_|execute_|ctl_flags_bus~combout ), + .datac(\z80_|execute_|ctl_flags_alu~15_combout ), + .datad(\z80_|alu_control_|db[4]~32_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_hf~0 .lut_mask = 16'hDC50; +defparam \z80_|alu_flags_|DFFE_inst_latch_hf~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_we~3_combout = (\z80_|pla_decode_|Equal11~0_combout & (((\z80_|nM1_int~2_combout ) # (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) # (!\z80_|pla_decode_|Equal11~0_combout & (\z80_|pla_decode_|Equal10~0_combout & +// ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_we~3 .lut_mask = 16'hEEC0; +defparam \z80_|execute_|ctl_flags_hf_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_we~4_combout = ((\z80_|execute_|ctl_flags_sz_we~6_combout ) # ((\z80_|execute_|ctl_flags_hf_we~3_combout ) # (!\z80_|execute_|ctl_flags_alu~14_combout ))) # (!\z80_|execute_|ctl_flags_xy_we~8_combout ) + + .dataa(\z80_|execute_|ctl_flags_xy_we~8_combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~6_combout ), + .datac(\z80_|execute_|ctl_flags_alu~14_combout ), + .datad(\z80_|execute_|ctl_flags_hf_we~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_we~4 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|ctl_flags_hf_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N28 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_hf~1 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_hf~1_combout = (\z80_|execute_|ctl_flags_hf_we~2_combout & ((\z80_|execute_|ctl_flags_hf_we~4_combout & (\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout )) # (!\z80_|execute_|ctl_flags_hf_we~4_combout & +// ((\z80_|alu_flags_|DFFE_inst_latch_hf~q ))))) # (!\z80_|execute_|ctl_flags_hf_we~2_combout & (\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout )) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ), + .datab(\z80_|execute_|ctl_flags_hf_we~2_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), + .datad(\z80_|execute_|ctl_flags_hf_we~4_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_hf~1 .lut_mask = 16'hAAE2; +defparam \z80_|alu_flags_|DFFE_inst_latch_hf~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y18_N29 +dffeas \z80_|alu_flags_|DFFE_inst_latch_hf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_hf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_hf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N16 +cycloneive_lcell_comb \z80_|alu_flags_|flags_hf ( +// Equation(s): +// \z80_|alu_flags_|flags_hf~combout = \z80_|alu_flags_|DFFE_inst_latch_hf~q $ (((\z80_|execute_|ctl_flags_hf_cpl~13_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout & !\z80_|alu_flags_|flags_cf~combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .datab(\z80_|execute_|ctl_flags_hf_cpl~13_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), + .datad(\z80_|alu_flags_|flags_cf~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|flags_hf~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|flags_hf .lut_mask = 16'h3C1E; +defparam \z80_|alu_flags_|flags_hf .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N16 +cycloneive_lcell_comb \z80_|alu_control_|db[4]~30 ( +// Equation(s): +// \z80_|alu_control_|db[4]~30_combout = (\z80_|alu_|db[4]~18_combout & (!\z80_|reg_file_|gdfx_temp0[4]~62_combout & ((\z80_|execute_|ctl_reg_out_lo~8_combout )))) # (!\z80_|alu_|db[4]~18_combout & ((\z80_|execute_|ctl_sw_2u~7_combout ) # +// ((!\z80_|reg_file_|gdfx_temp0[4]~62_combout & \z80_|execute_|ctl_reg_out_lo~8_combout )))) + + .dataa(\z80_|alu_|db[4]~18_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .datac(\z80_|execute_|ctl_sw_2u~7_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[4]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[4]~30 .lut_mask = 16'h7350; +defparam \z80_|alu_control_|db[4]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N10 +cycloneive_lcell_comb \z80_|alu_control_|db[4]~31 ( +// Equation(s): +// \z80_|alu_control_|db[4]~31_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & (!\z80_|alu_control_|db[4]~30_combout & ((\z80_|alu_flags_|flags_hf~combout ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) + + .dataa(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .datab(\z80_|alu_flags_|flags_hf~combout ), + .datac(\z80_|execute_|ctl_flags_oe~2_combout ), + .datad(\z80_|alu_control_|db[4]~30_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[4]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[4]~31 .lut_mask = 16'h008A; +defparam \z80_|alu_control_|db[4]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N2 +cycloneive_lcell_comb \z80_|alu_control_|db[4]~32 ( +// Equation(s): +// \z80_|alu_control_|db[4]~32_combout = ((\z80_|alu_control_|db[4]~31_combout & ((\z80_|bus_control_|db[4]~19_combout ) # (!\z80_|execute_|ctl_sw_1d~7_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) + + .dataa(\z80_|bus_control_|db[4]~19_combout ), + .datab(\z80_|alu_control_|db[4]~31_combout ), + .datac(\z80_|execute_|ctl_sw_1d~7_combout ), + .datad(\z80_|alu_control_|db[6]~11_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[4]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[4]~32 .lut_mask = 16'h8CFF; +defparam \z80_|alu_control_|db[4]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N26 +cycloneive_lcell_comb \z80_|alu_|db[4]~17 ( +// Equation(s): +// \z80_|alu_|db[4]~17_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[4]~66_combout & ((\z80_|alu_control_|db[4]~32_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & +// ((\z80_|alu_control_|db[4]~32_combout ) # ((!\z80_|execute_|ctl_sw_2d~13_combout )))) + + .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .datab(\z80_|alu_control_|db[4]~32_combout ), + .datac(\z80_|execute_|ctl_sw_2d~13_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[4]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[4]~17 .lut_mask = 16'hCF45; +defparam \z80_|alu_|db[4]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N16 +cycloneive_lcell_comb \z80_|alu_|db[4]~18 ( +// Equation(s): +// \z80_|alu_|db[4]~18_combout = ((\z80_|alu_|db[4]~17_combout & ((\z80_|alu_|db_high[0]~25_combout ) # (!\z80_|execute_|ctl_alu_oe~11_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|execute_|ctl_alu_oe~11_combout ), + .datab(\z80_|alu_|db[7]~9_combout ), + .datac(\z80_|alu_|db[4]~17_combout ), + .datad(\z80_|alu_|db_high[0]~25_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[4]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[4]~18 .lut_mask = 16'hF373; +defparam \z80_|alu_|db[4]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N16 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~13 ( +// Equation(s): +// \z80_|alu_|db_low[3]~13_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[4]~18_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[2]~16_combout ))) + + .dataa(\z80_|alu_|db[4]~18_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(gnd), + .datad(\z80_|alu_|db[2]~16_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~13 .lut_mask = 16'hBB88; +defparam \z80_|alu_|db_low[3]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N10 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~14 ( +// Equation(s): +// \z80_|alu_|db_low[3]~14_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_low[3]~13_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[3]~20_combout )))) # +// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) + + .dataa(\z80_|alu_|db_low[3]~13_combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datad(\z80_|alu_|db[3]~20_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~14 .lut_mask = 16'hBF8F; +defparam \z80_|alu_|db_low[3]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N24 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~17 ( +// Equation(s): +// \z80_|alu_|db_low[3]~17_combout = (\z80_|alu_|db_low[3]~16_combout & (\z80_|alu_|db_low[3]~14_combout & ((\z80_|execute_|ctl_alu_res_oe~3_combout ) # (\z80_|alu_|result_lo [3])))) + + .dataa(\z80_|execute_|ctl_alu_res_oe~3_combout ), + .datab(\z80_|alu_|db_low[3]~16_combout ), + .datac(\z80_|alu_|result_lo [3]), + .datad(\z80_|alu_|db_low[3]~14_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~17 .lut_mask = 16'hC800; +defparam \z80_|alu_|db_low[3]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N14 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~25 ( +// Equation(s): +// \z80_|alu_|db_low[3]~25_combout = (\z80_|alu_|db_low[3]~17_combout ) # ((!\z80_|alu_|db_high[3]~0_combout & !\z80_|execute_|ctl_alu_shift_oe~43_combout )) + + .dataa(gnd), + .datab(\z80_|alu_|db_high[3]~0_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datad(\z80_|alu_|db_low[3]~17_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~25 .lut_mask = 16'hFF03; +defparam \z80_|alu_|db_low[3]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N24 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~4 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~4_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [3]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [3])))) + + .dataa(\z80_|alu_|op1_high [3]), + .datab(\z80_|execute_|ctl_alu_op_low~combout ), + .datac(\z80_|alu_|op1_low [3]), + .datad(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~4 .lut_mask = 16'hE200; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N28 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~5 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~5_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~4_combout ) # ((\z80_|alu_|db_low[3]~25_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) + + .dataa(\z80_|alu_|db_low[3]~25_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .datad(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~4_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~5 .lut_mask = 16'h3320; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y18_N29 +dffeas \z80_|alu_|op2_low[3] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~5_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_low [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_low[3] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_low[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N12 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~8_combout & ((\z80_|alu_|db_high[3]~7_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_lq~combout & \z80_|alu_|db_low[3]~25_combout )))) # +// (!\z80_|execute_|ctl_alu_op2_sel_bus~8_combout & (\z80_|execute_|ctl_alu_op2_sel_lq~combout & (\z80_|alu_|db_low[3]~25_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datac(\z80_|alu_|db_low[3]~25_combout ), + .datad(\z80_|alu_|db_high[3]~7_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0 .lut_mask = 16'hEAC0; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N20 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datac(gnd), + .datad(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1 .lut_mask = 16'h3300; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y18_N21 +dffeas \z80_|alu_|op2_high[3] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_high [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_high[3] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_high[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N2 +cycloneive_lcell_comb \z80_|alu_|alu_op2[3]~2 ( +// Equation(s): +// \z80_|alu_|alu_op2[3]~2_combout = \z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [3]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [3])))) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .datab(\z80_|alu_|op2_low [3]), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), + .datad(\z80_|alu_|op2_high [3]), + .cin(gnd), + .combout(\z80_|alu_|alu_op2[3]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op2[3]~2 .lut_mask = 16'h1EB4; +defparam \z80_|alu_|alu_op2[3]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N22 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ) # +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout )))) # (!\z80_|execute_|ctl_alu_core_R~5_combout ) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), + .datac(\z80_|execute_|ctl_alu_core_R~5_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1 .lut_mask = 16'h5F4F; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N20 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout = (\z80_|alu_|alu_op2[3]~2_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout ) # ((\z80_|alu_|alu_op1[3]~2_combout & +// !\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout )))) # (!\z80_|alu_|alu_op2[3]~2_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_|alu_op1[3]~2_combout ) # +// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout )))) + + .dataa(\z80_|alu_|alu_op2[3]~2_combout ), + .datab(\z80_|alu_|alu_op1[3]~2_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 .lut_mask = 16'hEF08; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N14 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~3 ( +// Equation(s): +// \z80_|alu_|db_high[3]~3_combout = (\z80_|execute_|ctl_alu_op2_oe~0_combout & (\z80_|alu_|op2_high [3] & ((\z80_|alu_|op1_high [3]) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout & (((\z80_|alu_|op1_high +// [3]) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datab(\z80_|alu_|op2_high [3]), + .datac(\z80_|alu_|op1_high [3]), + .datad(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~3 .lut_mask = 16'hD0DD; +defparam \z80_|alu_|db_high[3]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N18 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~4 ( +// Equation(s): +// \z80_|alu_|db_high[3]~4_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[6]~22_combout )) + + .dataa(\z80_|alu_|db[6]~22_combout ), + .datab(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), + .datac(gnd), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~4 .lut_mask = 16'hCCAA; +defparam \z80_|alu_|db_high[3]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N28 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~5 ( +// Equation(s): +// \z80_|alu_|db_high[3]~5_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_high[3]~4_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[7]~12_combout )) + + .dataa(\z80_|alu_|db[7]~12_combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .datac(gnd), + .datad(\z80_|alu_|db_high[3]~4_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~5 .lut_mask = 16'hEE22; +defparam \z80_|alu_|db_high[3]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N28 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~2 ( +// Equation(s): +// \z80_|alu_|db_high[3]~2_combout = ((\z80_|bus_control_|db[3]~21_combout & (\z80_|bus_control_|db[5]~15_combout & \z80_|bus_control_|db[4]~19_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) + + .dataa(\z80_|bus_control_|db[3]~21_combout ), + .datab(\z80_|bus_control_|db[5]~15_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datad(\z80_|bus_control_|db[4]~19_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~2 .lut_mask = 16'h8F0F; +defparam \z80_|alu_|db_high[3]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N0 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~6 ( +// Equation(s): +// \z80_|alu_|db_high[3]~6_combout = (\z80_|alu_|db_high[3]~3_combout & (\z80_|alu_|db_high[3]~2_combout & ((\z80_|alu_|db_high[3]~5_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) + + .dataa(\z80_|alu_|db_high[3]~3_combout ), + .datab(\z80_|alu_|db_high[3]~5_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datad(\z80_|alu_|db_high[3]~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~6 .lut_mask = 16'h8A00; +defparam \z80_|alu_|db_high[3]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N22 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~7 ( +// Equation(s): +// \z80_|alu_|db_high[3]~7_combout = ((\z80_|alu_|db_high[3]~6_combout & ((\z80_|execute_|ctl_alu_res_oe~3_combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout )))) # (!\z80_|alu_|db_high[3]~1_combout ) + + .dataa(\z80_|execute_|ctl_alu_res_oe~3_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), + .datac(\z80_|alu_|db_high[3]~1_combout ), + .datad(\z80_|alu_|db_high[3]~6_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~7 .lut_mask = 16'hEF0F; +defparam \z80_|alu_|db_high[3]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N24 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_34 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout = (\z80_|execute_|ctl_flags_bus~combout & ((\z80_|alu_control_|db[7]~19_combout ) # ((\z80_|alu_|db_high[3]~7_combout & \z80_|execute_|ctl_flags_alu~15_combout )))) # (!\z80_|execute_|ctl_flags_bus~combout +// & (((\z80_|alu_|db_high[3]~7_combout & \z80_|execute_|ctl_flags_alu~15_combout )))) + + .dataa(\z80_|execute_|ctl_flags_bus~combout ), + .datab(\z80_|alu_control_|db[7]~19_combout ), + .datac(\z80_|alu_|db_high[3]~7_combout ), + .datad(\z80_|execute_|ctl_flags_alu~15_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_34 .lut_mask = 16'hF888; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y16_N25 +dffeas \z80_|alu_flags_|DFFE_inst_latch_sf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_flags_sz_we~8_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_sf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_sf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~5_combout = ((\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # (\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout )))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~5 .lut_mask = 16'hEF0F; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~7_combout = (\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ) # ((\z80_|pla_decode_|Equal61~2_combout & ((\z80_|nM1_int~2_combout ) # (\z80_|execute_|ctl_eval_cond~0_combout )))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), + .datac(\z80_|pla_decode_|Equal61~2_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~7 .lut_mask = 16'hFCEC; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout = (\z80_|pla_decode_|Equal13~0_combout & (\z80_|execute_|ctl_alu_op_low~22_combout & (\z80_|pla_decode_|Equal55~0_combout & !\z80_|ir_|opcode [3]))) + + .dataa(\z80_|pla_decode_|Equal13~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~6_combout = (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # ((\z80_|execute_|ixy_d~7_combout ) # (\z80_|nM1_int~2_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~6 .lut_mask = 16'hF0E0; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~8_combout = ((\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ) # (\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ))) # (!\z80_|execute_|ctl_alu_op_low~48_combout +// ) + + .dataa(\z80_|execute_|ctl_alu_op_low~48_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~8 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~11_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ) # (((\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~10_combout )) # (!\z80_|execute_|ctl_alu_sel_op2_neg~9_combout )) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~11 .lut_mask = 16'hFFBF; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~12_combout = (((\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ) # (\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout )) # (!\z80_|execute_|ctl_alu_sel_op2_neg~2_combout )) # (!\z80_|execute_|ctl_reg_out_hi~4_combout +// ) + + .dataa(\z80_|execute_|ctl_reg_out_hi~4_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~12 .lut_mask = 16'hFFF7; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~15 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~15_combout = ((\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_sf~q & \z80_|execute_|ctl_alu_sel_op2_neg~12_combout ))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~15 .lut_mask = 16'hFDF5; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N26 +cycloneive_lcell_comb \z80_|alu_|alu_op2[2]~0 ( +// Equation(s): +// \z80_|alu_|alu_op2[2]~0_combout = \z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [2]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [2])))) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), + .datac(\z80_|alu_|op2_low [2]), + .datad(\z80_|alu_|op2_high [2]), + .cin(gnd), + .combout(\z80_|alu_|alu_op2[2]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op2[2]~0 .lut_mask = 16'h369C; +defparam \z80_|alu_|alu_op2[2]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N18 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ) # +// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) # (!\z80_|execute_|ctl_alu_core_R~5_combout ) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), + .datac(\z80_|execute_|ctl_alu_core_R~5_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 .lut_mask = 16'h4F5F; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N24 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout = (\z80_|alu_|alu_op2[2]~0_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ) # ((\z80_|alu_|alu_op1[2]~1_combout & +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) # (!\z80_|alu_|alu_op2[2]~0_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_|alu_op1[2]~1_combout ) # +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) + + .dataa(\z80_|alu_|alu_op2[2]~0_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ), + .datac(\z80_|alu_|alu_op1[2]~1_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 .lut_mask = 16'hECC8; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y17_N11 +dffeas \z80_|alu_control_|DFFE_latch_pf_tmp ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|alu_parity_out~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_alu_op_low~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_control_|DFFE_latch_pf_tmp~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_control_|DFFE_latch_pf_tmp .is_wysiwyg = "true"; +defparam \z80_|alu_control_|DFFE_latch_pf_tmp .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N8 +cycloneive_lcell_comb \z80_|alu_|alu_parity_out~0 ( +// Equation(s): +// \z80_|alu_|alu_parity_out~0_combout = \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout $ (((\z80_|execute_|ctl_alu_op_low~29_combout & (!\z80_|alu_control_|DFFE_latch_pf_tmp~q & !\z80_|execute_|ctl_alu_op_low~41_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~29_combout ), + .datab(\z80_|alu_control_|DFFE_latch_pf_tmp~q ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~41_combout ), + .cin(gnd), + .combout(\z80_|alu_|alu_parity_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_parity_out~0 .lut_mask = 16'hF0D2; +defparam \z80_|alu_|alu_parity_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N10 +cycloneive_lcell_comb \z80_|alu_|alu_parity_out~1 ( +// Equation(s): +// \z80_|alu_|alu_parity_out~1_combout = \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout $ (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout $ (\z80_|alu_|alu_parity_out~0_combout $ +// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), + .datac(\z80_|alu_|alu_parity_out~0_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|alu_parity_out~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_parity_out~1 .lut_mask = 16'h9669; +defparam \z80_|alu_|alu_parity_out~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N24 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~4 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~4_combout = (\z80_|execute_|ctl_pf_sel[0]~2_combout & (((!\z80_|pla_decode_|Equal62~3_combout & !\z80_|execute_|ctl_alu_op_low~27_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_pf_sel[0]~2_combout ), + .datab(\z80_|pla_decode_|Equal62~3_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~4 .lut_mask = 16'h0A2A; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N18 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~5 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~5_combout = (\z80_|execute_|ctl_pf_sel[0]~3_combout & (!\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout $ +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout )))) # (!\z80_|execute_|ctl_pf_sel[0]~3_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout $ ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout )))) + + .dataa(\z80_|execute_|ctl_pf_sel[0]~3_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~5 .lut_mask = 16'h143C; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N16 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~6 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~6_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout & (((!\z80_|pla_decode_|Equal69~0_combout & \z80_|execute_|ctl_flags_bus~1_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal69~0_combout ), + .datab(\z80_|execute_|ctl_flags_bus~1_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~6 .lut_mask = 16'h4F00; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N6 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~1 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~1_combout = (\z80_|execute_|ctl_pf_sel[0]~3_combout & (!\z80_|execute_|ctl_alu_op_low~27_combout & (\z80_|execute_|ctl_pf_sel[0]~2_combout & !\z80_|pla_decode_|Equal62~3_combout ))) + + .dataa(\z80_|execute_|ctl_pf_sel[0]~3_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~27_combout ), + .datac(\z80_|execute_|ctl_pf_sel[0]~2_combout ), + .datad(\z80_|pla_decode_|Equal62~3_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~1 .lut_mask = 16'h0020; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N30 +cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~2 ( +// Equation(s): +// \z80_|decode_state_|DFFE_instNonRep~2_combout = (!\z80_|address_latch_|Q [6] & (!\z80_|address_latch_|Q [5] & (!\z80_|address_latch_|Q [4] & !\z80_|address_latch_|Q [7]))) + + .dataa(\z80_|address_latch_|Q [6]), + .datab(\z80_|address_latch_|Q [5]), + .datac(\z80_|address_latch_|Q [4]), + .datad(\z80_|address_latch_|Q [7]), + .cin(gnd), + .combout(\z80_|decode_state_|DFFE_instNonRep~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep~2 .lut_mask = 16'h0001; +defparam \z80_|decode_state_|DFFE_instNonRep~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N0 +cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~1 ( +// Equation(s): +// \z80_|decode_state_|DFFE_instNonRep~1_combout = (!\z80_|address_latch_|Q [9] & (!\z80_|address_latch_|Q [8] & (!\z80_|address_latch_|Q [11] & !\z80_|address_latch_|Q [10]))) + + .dataa(\z80_|address_latch_|Q [9]), + .datab(\z80_|address_latch_|Q [8]), + .datac(\z80_|address_latch_|Q [11]), + .datad(\z80_|address_latch_|Q [10]), + .cin(gnd), + .combout(\z80_|decode_state_|DFFE_instNonRep~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep~1 .lut_mask = 16'h0001; +defparam \z80_|decode_state_|DFFE_instNonRep~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N4 +cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~3 ( +// Equation(s): +// \z80_|decode_state_|DFFE_instNonRep~3_combout = (\z80_|address_latch_|Q [0] & (!\z80_|address_latch_|Q [2] & (!\z80_|address_latch_|Q [3] & !\z80_|address_latch_|Q [1]))) + + .dataa(\z80_|address_latch_|Q [0]), + .datab(\z80_|address_latch_|Q [2]), + .datac(\z80_|address_latch_|Q [3]), + .datad(\z80_|address_latch_|Q [1]), + .cin(gnd), + .combout(\z80_|decode_state_|DFFE_instNonRep~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep~3 .lut_mask = 16'h0002; +defparam \z80_|decode_state_|DFFE_instNonRep~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N28 +cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~0 ( +// Equation(s): +// \z80_|decode_state_|DFFE_instNonRep~0_combout = (!\z80_|address_latch_|Q [14] & (!\z80_|address_latch_|Q [15] & (!\z80_|address_latch_|Q [12] & !\z80_|address_latch_|Q [13]))) + + .dataa(\z80_|address_latch_|Q [14]), + .datab(\z80_|address_latch_|Q [15]), + .datac(\z80_|address_latch_|Q [12]), + .datad(\z80_|address_latch_|Q [13]), + .cin(gnd), + .combout(\z80_|decode_state_|DFFE_instNonRep~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep~0 .lut_mask = 16'h0001; +defparam \z80_|decode_state_|DFFE_instNonRep~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N24 +cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~4 ( +// Equation(s): +// \z80_|decode_state_|DFFE_instNonRep~4_combout = (\z80_|decode_state_|DFFE_instNonRep~2_combout & (\z80_|decode_state_|DFFE_instNonRep~1_combout & (\z80_|decode_state_|DFFE_instNonRep~3_combout & \z80_|decode_state_|DFFE_instNonRep~0_combout ))) + + .dataa(\z80_|decode_state_|DFFE_instNonRep~2_combout ), + .datab(\z80_|decode_state_|DFFE_instNonRep~1_combout ), + .datac(\z80_|decode_state_|DFFE_instNonRep~3_combout ), + .datad(\z80_|decode_state_|DFFE_instNonRep~0_combout ), + .cin(gnd), + .combout(\z80_|decode_state_|DFFE_instNonRep~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep~4 .lut_mask = 16'h8000; +defparam \z80_|decode_state_|DFFE_instNonRep~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N20 +cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~5 ( +// Equation(s): +// \z80_|decode_state_|DFFE_instNonRep~5_combout = (\z80_|execute_|ctl_flags_bus~1_combout & (((\z80_|decode_state_|DFFE_instNonRep~q )))) # (!\z80_|execute_|ctl_flags_bus~1_combout & ((\z80_|execute_|ixy_d~9_combout & +// (\z80_|decode_state_|DFFE_instNonRep~4_combout )) # (!\z80_|execute_|ixy_d~9_combout & ((\z80_|decode_state_|DFFE_instNonRep~q ))))) + + .dataa(\z80_|decode_state_|DFFE_instNonRep~4_combout ), + .datab(\z80_|execute_|ctl_flags_bus~1_combout ), + .datac(\z80_|decode_state_|DFFE_instNonRep~q ), + .datad(\z80_|execute_|ixy_d~9_combout ), + .cin(gnd), + .combout(\z80_|decode_state_|DFFE_instNonRep~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep~5 .lut_mask = 16'hE2F0; +defparam \z80_|decode_state_|DFFE_instNonRep~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y15_N21 +dffeas \z80_|decode_state_|DFFE_instNonRep ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|decode_state_|DFFE_instNonRep~5_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|decode_state_|DFFE_instNonRep~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep .is_wysiwyg = "true"; +defparam \z80_|decode_state_|DFFE_instNonRep .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N12 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~2 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~2_combout = (\z80_|pla_decode_|Equal69~0_combout & ((\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout & ((\z80_|interrupts_|DFFE_instIFF2~q ))) # (!\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout & +// (!\z80_|decode_state_|DFFE_instNonRep~q )))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout ), + .datab(\z80_|decode_state_|DFFE_instNonRep~q ), + .datac(\z80_|interrupts_|DFFE_instIFF2~q ), + .datad(\z80_|pla_decode_|Equal69~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~2 .lut_mask = 16'hB100; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N14 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~3 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~3_combout = (\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_flags_bus~1_combout & (\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout )) # (!\z80_|execute_|ctl_flags_bus~1_combout & +// ((!\z80_|decode_state_|DFFE_instNonRep~q ))))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|decode_state_|DFFE_instNonRep~q ), + .datad(\z80_|execute_|ctl_flags_bus~1_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~3 .lut_mask = 16'h880C; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N2 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~7 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~7_combout = (\z80_|pla_decode_|Equal69~0_combout ) # (((\z80_|pla_decode_|Equal62~3_combout ) # (\z80_|execute_|ctl_alu_op_low~27_combout )) # (!\z80_|execute_|ctl_flags_bus~1_combout )) + + .dataa(\z80_|pla_decode_|Equal69~0_combout ), + .datab(\z80_|execute_|ctl_flags_bus~1_combout ), + .datac(\z80_|pla_decode_|Equal62~3_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~7 .lut_mask = 16'hFFFB; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N0 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~8 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~8_combout = (\z80_|execute_|ctl_pf_sel[0]~2_combout & (\z80_|execute_|ctl_pf_sel[0]~3_combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout )))) + + .dataa(\z80_|execute_|ctl_pf_sel[0]~2_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_pf_sel[0]~3_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~8 .lut_mask = 16'h2A00; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N26 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~9 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~9_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ) # ((\z80_|alu_|alu_parity_out~1_combout & \z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ))) + + .dataa(\z80_|alu_|alu_parity_out~1_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~9 .lut_mask = 16'hFEFC; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N0 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~0 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~0_combout = (\z80_|execute_|ctl_flags_pf_we~9_combout & (\z80_|execute_|ctl_flags_bus~combout & ((\z80_|alu_control_|db[2]~29_combout )))) # (!\z80_|execute_|ctl_flags_pf_we~9_combout & +// (((\z80_|alu_flags_|DFFE_inst_latch_pf~q )))) + + .dataa(\z80_|execute_|ctl_flags_bus~combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), + .datac(\z80_|execute_|ctl_flags_pf_we~9_combout ), + .datad(\z80_|alu_control_|db[2]~29_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~0 .lut_mask = 16'hAC0C; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N16 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~10 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~10_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ) # ((\z80_|execute_|ctl_flags_alu~15_combout & (\z80_|execute_|ctl_flags_pf_we~9_combout & \z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ))) + + .dataa(\z80_|execute_|ctl_flags_alu~15_combout ), + .datab(\z80_|execute_|ctl_flags_pf_we~9_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~10 .lut_mask = 16'hFF80; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y15_N17 +dffeas \z80_|alu_flags_|DFFE_inst_latch_pf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|DFFE_inst_latch_pf~10_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y13_N6 +cycloneive_lcell_comb \z80_|alu_control_|sel[1]~0 ( +// Equation(s): +// \z80_|alu_control_|sel[1]~0_combout = (\z80_|ir_|opcode [5] & (((!\z80_|pla_decode_|Equal6~0_combout ) # (!\z80_|pla_decode_|Equal40~0_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal40~0_combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|sel[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|sel[1]~0 .lut_mask = 16'h4CCC; +defparam \z80_|alu_control_|sel[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N18 +cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_cond_mux|out~0 ( +// Equation(s): +// \z80_|alu_control_|b2v_inst_cond_mux|out~0_combout = (\z80_|alu_control_|sel[1]~0_combout & (((\z80_|ir_|opcode [4])))) # (!\z80_|alu_control_|sel[1]~0_combout & ((\z80_|ir_|opcode [4] & ((\z80_|alu_flags_|flags_cf~combout ))) # (!\z80_|ir_|opcode [4] +// & (\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q )))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datab(\z80_|alu_flags_|flags_cf~combout ), + .datac(\z80_|alu_control_|sel[1]~0_combout ), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|b2v_inst_cond_mux|out~0 .lut_mask = 16'hFC0A; +defparam \z80_|alu_control_|b2v_inst_cond_mux|out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N16 +cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_cond_mux|out~1 ( +// Equation(s): +// \z80_|alu_control_|b2v_inst_cond_mux|out~1_combout = (\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout & (((\z80_|alu_flags_|DFFE_inst_latch_sf~q ) # (!\z80_|alu_control_|sel[1]~0_combout )))) # (!\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout & +// (\z80_|alu_flags_|DFFE_inst_latch_pf~q & (\z80_|alu_control_|sel[1]~0_combout ))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), + .datab(\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ), + .datac(\z80_|alu_control_|sel[1]~0_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), + .cin(gnd), + .combout(\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|b2v_inst_cond_mux|out~1 .lut_mask = 16'hEC2C; +defparam \z80_|alu_control_|b2v_inst_cond_mux|out~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N26 +cycloneive_lcell_comb \z80_|alu_control_|flags_cond_true~0 ( +// Equation(s): +// \z80_|alu_control_|flags_cond_true~0_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|ir_|opcode [3] $ (((!\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ))))) # (!\z80_|execute_|ctl_eval_cond~0_combout & +// (((\z80_|alu_control_|flags_cond_true~q )))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|alu_control_|flags_cond_true~q ), + .datad(\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|flags_cond_true~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|flags_cond_true~0 .lut_mask = 16'hD872; +defparam \z80_|alu_control_|flags_cond_true~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y16_N27 +dffeas \z80_|alu_control_|flags_cond_true ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_control_|flags_cond_true~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_control_|flags_cond_true~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_control_|flags_cond_true .is_wysiwyg = "true"; +defparam \z80_|alu_control_|flags_cond_true .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~20 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~20_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|pla_decode_|Equal35~0_combout & \z80_|alu_control_|flags_cond_true~q ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|pla_decode_|Equal35~0_combout ), + .datad(\z80_|alu_control_|flags_cond_true~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~20 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sel_wz~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~1 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~1_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ) # ((\z80_|execute_|ctl_reg_sel_wz~20_combout ) # ((\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ctl_al_we~14_combout ))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~20_combout ), + .datad(\z80_|execute_|ctl_al_we~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~1 .lut_mask = 16'hFCFE; +defparam \z80_|execute_|ctl_sw_4d~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~6 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~6_combout = (\z80_|execute_|ctl_sw_4d~0_combout ) # ((\z80_|execute_|ctl_sw_4d~1_combout ) # (!\z80_|execute_|ctl_sw_4d~5_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_sw_4d~0_combout ), + .datac(\z80_|execute_|ctl_sw_4d~1_combout ), + .datad(\z80_|execute_|ctl_sw_4d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~6 .lut_mask = 16'hFCFF; +defparam \z80_|execute_|ctl_sw_4d~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y12_N17 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[1]~6_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N16 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~4 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[1]~4_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[1]~32_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # +// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[1]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[1]~4 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_lo_as[1]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y12_N23 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[1]~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N20 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~5 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[1]~5_combout = (\z80_|reg_file_|db_lo_as[1]~4_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|db_lo_as[1]~4_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_lo|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[1]~5 .lut_mask = 16'hC0CC; +defparam \z80_|reg_file_|db_lo_as[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N18 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout = \z80_|address_latch_|Q [1] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ) + + .dataa(\z80_|address_latch_|Q [1]), + .datab(gnd), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out .lut_mask = 16'h5A5A; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N22 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~6 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[1]~6_combout = ((\z80_|reg_file_|db_lo_as[1]~5_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .datab(\z80_|reg_file_|db_lo_as[1]~5_combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), + .datad(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[1]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[1]~6 .lut_mask = 16'hC4FF; +defparam \z80_|reg_file_|db_lo_as[1]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y12_N7 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~29 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~29_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [1] & ((\z80_|alu_control_|db[1]~26_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (((\z80_|alu_control_|db[1]~26_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [1]), + .datad(\z80_|alu_control_|db[1]~26_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~29 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[1]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y12_N15 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X31_Y12_N5 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~28 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~28_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datab(\z80_|reg_file_|b2v_latch_iy_lo|latch [1]), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~28 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp0[1]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y14_N1 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X32_Y14_N19 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~26 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~26_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [1]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [1]), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~26 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[1]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y13_N19 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~27 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~27_combout = (\z80_|reg_file_|gdfx_temp0[1]~26_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|gdfx_temp0[1]~26_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~27 .lut_mask = 16'hC0CC; +defparam \z80_|reg_file_|gdfx_temp0[1]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~30 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~30_combout = (\z80_|reg_file_|gdfx_temp0[1]~29_combout & (\z80_|reg_file_|gdfx_temp0[1]~28_combout & \z80_|reg_file_|gdfx_temp0[1]~27_combout )) + + .dataa(\z80_|reg_file_|gdfx_temp0[1]~29_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[1]~28_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[1]~27_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~30 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|gdfx_temp0[1]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y12_N7 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y12_N1 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~24 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~24_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [1] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [1] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [1]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~24 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp0[1]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y11_N5 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X31_Y11_N19 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~23 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~23_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [1]), + .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [1]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~23 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[1]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y11_N23 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X32_Y11_N25 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~25 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~25_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [1]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [1]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~25 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[1]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~31 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~31_combout = (\z80_|reg_file_|gdfx_temp0[1]~30_combout & (\z80_|reg_file_|gdfx_temp0[1]~24_combout & (\z80_|reg_file_|gdfx_temp0[1]~23_combout & \z80_|reg_file_|gdfx_temp0[1]~25_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[1]~30_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[1]~24_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[1]~23_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[1]~25_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~31 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[1]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~32 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~32_combout = ((\z80_|reg_file_|gdfx_temp0[1]~31_combout & ((\z80_|reg_file_|db_lo_as[1]~6_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), + .datab(\z80_|reg_file_|db_lo_as[1]~6_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[1]~31_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~32 .lut_mask = 16'hD0FF; +defparam \z80_|reg_file_|gdfx_temp0[1]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N30 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[1]~1 ( +// Equation(s): +// \z80_|reg_file_|db_lo_ds[1]~1_combout = (\z80_|reg_file_|gdfx_temp0[1]~32_combout ) # ((!\z80_|execute_|ctl_reg_out_lo~5_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout & \z80_|execute_|ctl_reg_out_lo~7_combout ))) + + .dataa(\z80_|execute_|ctl_reg_out_lo~5_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_ds[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_ds[1]~1 .lut_mask = 16'hFF40; +defparam \z80_|reg_file_|db_lo_ds[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N16 +cycloneive_lcell_comb \z80_|alu_control_|db[1]~25 ( +// Equation(s): +// \z80_|alu_control_|db[1]~25_combout = (\z80_|reg_file_|db_lo_ds[1]~1_combout & (((\z80_|bus_control_|db[1]~11_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) + + .dataa(\z80_|reg_file_|db_lo_ds[1]~1_combout ), + .datab(\z80_|bus_control_|db[1]~11_combout ), + .datac(\z80_|execute_|ctl_sw_1d~7_combout ), + .datad(\z80_|execute_|ctl_sw_mask543_en~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[1]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[1]~25 .lut_mask = 16'h0A8A; +defparam \z80_|alu_control_|db[1]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N4 +cycloneive_lcell_comb \z80_|alu_control_|db[1]~24 ( +// Equation(s): +// \z80_|alu_control_|db[1]~24_combout = (\z80_|execute_|ctl_flags_oe~2_combout & (((!\z80_|alu_|db[1]~10_combout & \z80_|execute_|ctl_sw_2u~7_combout )) # (!\z80_|alu_flags_|DFFE_inst_latch_nf~q ))) # (!\z80_|execute_|ctl_flags_oe~2_combout & +// (!\z80_|alu_|db[1]~10_combout & (\z80_|execute_|ctl_sw_2u~7_combout ))) + + .dataa(\z80_|execute_|ctl_flags_oe~2_combout ), + .datab(\z80_|alu_|db[1]~10_combout ), + .datac(\z80_|execute_|ctl_sw_2u~7_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .cin(gnd), + .combout(\z80_|alu_control_|db[1]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[1]~24 .lut_mask = 16'h30BA; +defparam \z80_|alu_control_|db[1]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N18 +cycloneive_lcell_comb \z80_|alu_control_|db[1]~26 ( +// Equation(s): +// \z80_|alu_control_|db[1]~26_combout = ((\z80_|alu_control_|db[1]~25_combout & (!\z80_|alu_control_|db[1]~24_combout & \z80_|alu_control_|db[2]~23_combout ))) # (!\z80_|alu_control_|db[6]~11_combout ) + + .dataa(\z80_|alu_control_|db[1]~25_combout ), + .datab(\z80_|alu_control_|db[1]~24_combout ), + .datac(\z80_|alu_control_|db[2]~23_combout ), + .datad(\z80_|alu_control_|db[6]~11_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[1]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[1]~26 .lut_mask = 16'h20FF; +defparam \z80_|alu_control_|db[1]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N2 +cycloneive_lcell_comb \z80_|bus_control_|db[1]~10 ( +// Equation(s): +// \z80_|bus_control_|db[1]~10_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[1]~26_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) + + .dataa(\z80_|bus_control_|db[0]~4_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datad(\z80_|alu_control_|db[1]~26_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[1]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[1]~10 .lut_mask = 16'hAA0A; +defparam \z80_|bus_control_|db[1]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|nextM~4 ( +// Equation(s): +// \z80_|execute_|nextM~4_combout = ((!\z80_|execute_|ctl_mRead~34_combout & ((!\z80_|pla_decode_|Equal24~0_combout ) # (!\z80_|pla_decode_|Equal21~0_combout )))) # (!\z80_|execute_|ctl_state_alu~2_combout ) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|pla_decode_|Equal21~0_combout ), + .datad(\z80_|pla_decode_|Equal24~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~4 .lut_mask = 16'h5777; +defparam \z80_|execute_|nextM~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_iorw~12 ( +// Equation(s): +// \z80_|execute_|ctl_iorw~12_combout = (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [2] & \z80_|execute_|ctl_eval_cond~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~0_combout ), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_iorw~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_iorw~12 .lut_mask = 16'h0200; +defparam \z80_|execute_|ctl_iorw~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_iorw~8 ( +// Equation(s): +// \z80_|execute_|ctl_iorw~8_combout = (\z80_|execute_|ctl_iorw~12_combout ) # ((\z80_|execute_|ctl_state_alu~2_combout & (\z80_|pla_decode_|Equal3~0_combout & \z80_|pla_decode_|Equal24~0_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ctl_iorw~12_combout ), + .datac(\z80_|pla_decode_|Equal3~0_combout ), + .datad(\z80_|pla_decode_|Equal24~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_iorw~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_iorw~8 .lut_mask = 16'hECCC; +defparam \z80_|execute_|ctl_iorw~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_iorw~9 ( +// Equation(s): +// \z80_|execute_|ctl_iorw~9_combout = ((\z80_|execute_|ctl_iorw~8_combout ) # ((\z80_|execute_|ctl_mWrite~17_combout & \z80_|execute_|ctl_mRead~9_combout ))) # (!\z80_|execute_|nextM~4_combout ) + + .dataa(\z80_|execute_|ctl_mWrite~17_combout ), + .datab(\z80_|execute_|nextM~4_combout ), + .datac(\z80_|execute_|ctl_mRead~9_combout ), + .datad(\z80_|execute_|ctl_iorw~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_iorw~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_iorw~9 .lut_mask = 16'hFFB3; +defparam \z80_|execute_|ctl_iorw~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y11_N29 +dffeas \z80_|memory_ifc_|DFFE_iorq_ff1 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|execute_|ctl_iorw~9_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_iorq_ff1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_iorq_ff1 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_iorq_ff1 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y11_N25 +dffeas \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|memory_ifc_|DFFE_iorq_ff1~q ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N14 +cycloneive_lcell_comb \z80_|memory_ifc_|wait_iorq~feeder ( +// Equation(s): +// \z80_|memory_ifc_|wait_iorq~feeder_combout = \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|wait_iorq~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_iorq~feeder .lut_mask = 16'hFF00; +defparam \z80_|memory_ifc_|wait_iorq~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y11_N15 +dffeas \z80_|memory_ifc_|wait_iorq ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|memory_ifc_|wait_iorq~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|wait_iorq~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_iorq .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|wait_iorq .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y11_N9 +dffeas \z80_|memory_ifc_|DFFE_iorq_ff4 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|memory_ifc_|wait_iorq~q ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_iorq_ff4~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_iorq_ff4 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_iorq_ff4 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N8 +cycloneive_lcell_comb \z80_|memory_ifc_|iorq~0 ( +// Equation(s): +// \z80_|memory_ifc_|iorq~0_combout = (\z80_|memory_ifc_|wait_iorq~q ) # ((\z80_|memory_ifc_|DFFE_iorq_ff4~q ) # (\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q )) + + .dataa(gnd), + .datab(\z80_|memory_ifc_|wait_iorq~q ), + .datac(\z80_|memory_ifc_|DFFE_iorq_ff4~q ), + .datad(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|iorq~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|iorq~0 .lut_mask = 16'hFFFC; +defparam \z80_|memory_ifc_|iorq~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y11_N3 +dffeas \z80_|memory_ifc_|DFFE_m1_ff1 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|execute_|setM1~54_combout ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_m1_ff1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_m1_ff1 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_m1_ff1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N26 +cycloneive_lcell_comb \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0 ( +// Equation(s): +// \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout = !\z80_|memory_ifc_|DFFE_m1_ff1~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|memory_ifc_|DFFE_m1_ff1~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0 .lut_mask = 16'h00FF; +defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y11_N27 +dffeas \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y11_N19 +dffeas \z80_|memory_ifc_|DFFE_m1_ff3 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_m1_ff3~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_m1_ff3 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_m1_ff3 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N18 +cycloneive_lcell_comb \z80_|memory_ifc_|nRD_out~0 ( +// Equation(s): +// \z80_|memory_ifc_|nRD_out~0_combout = (\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q & (((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q )) # (!\z80_|interrupts_|DFFE_inst44~q ))) # (!\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q & +// (\z80_|memory_ifc_|DFFE_m1_ff3~q & ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|interrupts_|DFFE_inst44~q )))) + + .dataa(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ), + .datab(\z80_|interrupts_|DFFE_inst44~q ), + .datac(\z80_|memory_ifc_|DFFE_m1_ff3~q ), + .datad(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|nRD_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|nRD_out~0 .lut_mask = 16'hFA32; +defparam \z80_|memory_ifc_|nRD_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|fIORead~0 ( +// Equation(s): +// \z80_|execute_|fIORead~0_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_mWrite~4_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # (\z80_|execute_|ctl_alu_op_low~22_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIORead~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIORead~0 .lut_mask = 16'hC080; +defparam \z80_|execute_|fIORead~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N22 +cycloneive_lcell_comb \z80_|execute_|fIORead~1 ( +// Equation(s): +// \z80_|execute_|fIORead~1_combout = (\z80_|pla_decode_|Equal68~2_combout & (\z80_|pla_decode_|Equal1~4_combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # (!\z80_|execute_|fIOWrite~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal68~2_combout ), + .datab(\z80_|pla_decode_|Equal1~4_combout ), + .datac(\z80_|execute_|ctl_mWrite~5_combout ), + .datad(\z80_|execute_|fIOWrite~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIORead~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIORead~1 .lut_mask = 16'h8088; +defparam \z80_|execute_|fIORead~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N30 +cycloneive_lcell_comb \z80_|execute_|fIORead~2 ( +// Equation(s): +// \z80_|execute_|fIORead~2_combout = (\z80_|execute_|fIORead~1_combout ) # ((\z80_|execute_|ctl_mWrite~17_combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # (\z80_|execute_|ctl_state_alu~3_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~5_combout ), + .datab(\z80_|execute_|ctl_state_alu~3_combout ), + .datac(\z80_|execute_|fIORead~1_combout ), + .datad(\z80_|execute_|ctl_mWrite~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIORead~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIORead~2 .lut_mask = 16'hFEF0; +defparam \z80_|execute_|fIORead~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|fIOWrite~1 ( +// Equation(s): +// \z80_|execute_|fIOWrite~1_combout = (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|execute_|ixy_d~4_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|execute_|ixy_d~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIOWrite~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIOWrite~1 .lut_mask = 16'hA0F0; +defparam \z80_|execute_|fIOWrite~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|fIORead~3 ( +// Equation(s): +// \z80_|execute_|fIORead~3_combout = (\z80_|execute_|fIORead~0_combout ) # ((\z80_|execute_|fIORead~2_combout ) # ((\z80_|execute_|ctl_mRead~2_combout & \z80_|execute_|fIOWrite~1_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~2_combout ), + .datab(\z80_|execute_|fIORead~0_combout ), + .datac(\z80_|execute_|fIORead~2_combout ), + .datad(\z80_|execute_|fIOWrite~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIORead~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIORead~3 .lut_mask = 16'hFEFC; +defparam \z80_|execute_|fIORead~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~30 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~30_combout = (\z80_|execute_|ctl_state_alu~2_combout & ((\z80_|pla_decode_|Equal33~3_combout ) # ((\z80_|pla_decode_|Equal41~2_combout ) # (\z80_|pla_decode_|Equal6~1_combout )))) + + .dataa(\z80_|pla_decode_|Equal33~3_combout ), + .datab(\z80_|pla_decode_|Equal41~2_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|pla_decode_|Equal6~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~30 .lut_mask = 16'hF0E0; +defparam \z80_|execute_|ctl_mRead~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~31 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~31_combout = (\z80_|execute_|ctl_mRead~30_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & \z80_|execute_|ctl_mRead~10_combout )) + + .dataa(\z80_|execute_|ctl_mRead~30_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .datad(\z80_|execute_|ctl_mRead~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~31 .lut_mask = 16'hFAAA; +defparam \z80_|execute_|ctl_mRead~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|nextM~3 ( +// Equation(s): +// \z80_|execute_|nextM~3_combout = (!\z80_|execute_|ixy_d~16_combout & (!\z80_|execute_|ixy_d~10_combout & !\z80_|pla_decode_|Equal41~2_combout )) + + .dataa(\z80_|execute_|ixy_d~16_combout ), + .datab(\z80_|execute_|ixy_d~10_combout ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|nextM~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~3 .lut_mask = 16'h0101; +defparam \z80_|execute_|nextM~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~29 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~29_combout = (\z80_|execute_|ixy_d~8_combout & (((\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal49~0_combout )) # (!\z80_|execute_|nextM~3_combout ))) + + .dataa(\z80_|execute_|nextM~3_combout ), + .datab(\z80_|execute_|ixy_d~8_combout ), + .datac(\z80_|decode_state_|use_ixiy~combout ), + .datad(\z80_|pla_decode_|Equal49~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~29 .lut_mask = 16'hC444; +defparam \z80_|execute_|ctl_mRead~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N26 +cycloneive_lcell_comb \z80_|execute_|setM1~58 ( +// Equation(s): +// \z80_|execute_|setM1~58_combout = (!\z80_|execute_|ctl_mRead~12_combout & ((\z80_|decode_state_|DFFE_instIY1~q ) # ((\z80_|decode_state_|DFFE_inst4~q ) # (!\z80_|pla_decode_|Equal49~0_combout )))) + + .dataa(\z80_|decode_state_|DFFE_instIY1~q ), + .datab(\z80_|decode_state_|DFFE_inst4~q ), + .datac(\z80_|pla_decode_|Equal49~0_combout ), + .datad(\z80_|execute_|ctl_mRead~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~58_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~58 .lut_mask = 16'h00EF; +defparam \z80_|execute_|setM1~58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|setM1~38 ( +// Equation(s): +// \z80_|execute_|setM1~38_combout = (\z80_|execute_|setM1~37_combout & \z80_|execute_|ctl_reg_sys_hilo~38_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|setM1~37_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo~38_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~38 .lut_mask = 16'hF000; +defparam \z80_|execute_|setM1~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|fMRead~4 ( +// Equation(s): +// \z80_|execute_|fMRead~4_combout = (\z80_|execute_|ctl_al_we~4_combout & (\z80_|execute_|ctl_reg_sel_wz~8_combout & !\z80_|pla_decode_|Equal34~0_combout )) + + .dataa(\z80_|execute_|ctl_al_we~4_combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~8_combout ), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal34~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~4 .lut_mask = 16'h0088; +defparam \z80_|execute_|fMRead~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N14 +cycloneive_lcell_comb \z80_|execute_|setM1~39 ( +// Equation(s): +// \z80_|execute_|setM1~39_combout = (!\z80_|pla_decode_|Equal29~0_combout & (\z80_|execute_|fMRead~4_combout & !\z80_|pla_decode_|Equal9~1_combout )) + + .dataa(\z80_|pla_decode_|Equal29~0_combout ), + .datab(gnd), + .datac(\z80_|execute_|fMRead~4_combout ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~39 .lut_mask = 16'h0050; +defparam \z80_|execute_|setM1~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N4 +cycloneive_lcell_comb \z80_|execute_|setM1~40 ( +// Equation(s): +// \z80_|execute_|setM1~40_combout = (\z80_|execute_|setM1~58_combout & (\z80_|execute_|setM1~38_combout & (\z80_|execute_|setM1~39_combout & !\z80_|execute_|ctl_mRead~14_combout ))) + + .dataa(\z80_|execute_|setM1~58_combout ), + .datab(\z80_|execute_|setM1~38_combout ), + .datac(\z80_|execute_|setM1~39_combout ), + .datad(\z80_|execute_|ctl_mRead~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~40 .lut_mask = 16'h0080; +defparam \z80_|execute_|setM1~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y14_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~32 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~32_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (((\z80_|execute_|ctl_mRead~11_combout ) # (!\z80_|execute_|setM1~40_combout )) # (!\z80_|execute_|ctl_mRead~17_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~17_combout ), + .datab(\z80_|execute_|ctl_mRead~11_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|setM1~40_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~32 .lut_mask = 16'hD0F0; +defparam \z80_|execute_|ctl_mRead~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y14_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~33 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~33_combout = (\z80_|execute_|ctl_mRead~31_combout ) # (((\z80_|execute_|ctl_mRead~29_combout ) # (\z80_|execute_|ctl_mRead~32_combout )) # (!\z80_|execute_|ctl_mRead~28_combout )) + + .dataa(\z80_|execute_|ctl_mRead~31_combout ), + .datab(\z80_|execute_|ctl_mRead~28_combout ), + .datac(\z80_|execute_|ctl_mRead~29_combout ), + .datad(\z80_|execute_|ctl_mRead~32_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~33 .lut_mask = 16'hFFFB; +defparam \z80_|execute_|ctl_mRead~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y14_N17 +dffeas \z80_|memory_ifc_|DFFE_mrd_ff1 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|execute_|ctl_mRead~33_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_mrd_ff1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_mrd_ff1 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_mrd_ff1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N30 +cycloneive_lcell_comb \z80_|memory_ifc_|wait_mrd~feeder ( +// Equation(s): +// \z80_|memory_ifc_|wait_mrd~feeder_combout = \z80_|memory_ifc_|DFFE_mrd_ff1~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|memory_ifc_|DFFE_mrd_ff1~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|wait_mrd~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_mrd~feeder .lut_mask = 16'hFF00; +defparam \z80_|memory_ifc_|wait_mrd~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y11_N31 +dffeas \z80_|memory_ifc_|wait_mrd ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|memory_ifc_|wait_mrd~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|wait_mrd~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_mrd .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|wait_mrd .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y11_N17 +dffeas \z80_|memory_ifc_|DFFE_mrd_ff3 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|memory_ifc_|wait_mrd~q ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_mrd_ff3~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_mrd_ff3 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_mrd_ff3 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N12 +cycloneive_lcell_comb \z80_|memory_ifc_|nRD_out~1 ( +// Equation(s): +// \z80_|memory_ifc_|nRD_out~1_combout = (!\z80_|memory_ifc_|wait_mrd~q & !\z80_|memory_ifc_|DFFE_mrd_ff3~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|memory_ifc_|wait_mrd~q ), + .datad(\z80_|memory_ifc_|DFFE_mrd_ff3~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|nRD_out~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|nRD_out~1 .lut_mask = 16'h000F; +defparam \z80_|memory_ifc_|nRD_out~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N20 +cycloneive_lcell_comb \z80_|memory_ifc_|nRD_out~2 ( +// Equation(s): +// \z80_|memory_ifc_|nRD_out~2_combout = (\z80_|memory_ifc_|nRD_out~0_combout ) # (((\z80_|memory_ifc_|iorq~0_combout & \z80_|execute_|fIORead~3_combout )) # (!\z80_|memory_ifc_|nRD_out~1_combout )) + + .dataa(\z80_|memory_ifc_|iorq~0_combout ), + .datab(\z80_|memory_ifc_|nRD_out~0_combout ), + .datac(\z80_|execute_|fIORead~3_combout ), + .datad(\z80_|memory_ifc_|nRD_out~1_combout ), + .cin(gnd), + .combout(\z80_|memory_ifc_|nRD_out~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|nRD_out~2 .lut_mask = 16'hECFF; +defparam \z80_|memory_ifc_|nRD_out~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|fIOWrite~3 ( +// Equation(s): +// \z80_|execute_|fIOWrite~3_combout = ((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|fIOWrite~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIOWrite~3 .lut_mask = 16'h0FCF; +defparam \z80_|execute_|fIOWrite~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|fIOWrite~4 ( +// Equation(s): +// \z80_|execute_|fIOWrite~4_combout = (\z80_|execute_|ctl_mRead~34_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ixy_d~6_combout ) # (!\z80_|execute_|fIOWrite~3_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|execute_|fIOWrite~3_combout ), + .datad(\z80_|execute_|ixy_d~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIOWrite~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIOWrite~4 .lut_mask = 16'hCC8C; +defparam \z80_|execute_|fIOWrite~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N22 +cycloneive_lcell_comb \z80_|execute_|fIOWrite~2 ( +// Equation(s): +// \z80_|execute_|fIOWrite~2_combout = (\z80_|execute_|ctl_iorw~10_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # ((\z80_|execute_|ctl_mWrite~5_combout ) # (!\z80_|execute_|fMRead~2_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ctl_iorw~10_combout ), + .datac(\z80_|execute_|ctl_mWrite~5_combout ), + .datad(\z80_|execute_|fMRead~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIOWrite~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIOWrite~2 .lut_mask = 16'hC8CC; +defparam \z80_|execute_|fIOWrite~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|fIOWrite~5 ( +// Equation(s): +// \z80_|execute_|fIOWrite~5_combout = (\z80_|execute_|fIOWrite~4_combout ) # ((\z80_|execute_|fIOWrite~2_combout ) # ((\z80_|execute_|ctl_mRead~3_combout & \z80_|execute_|fIOWrite~1_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~3_combout ), + .datab(\z80_|execute_|fIOWrite~4_combout ), + .datac(\z80_|execute_|fIOWrite~2_combout ), + .datad(\z80_|execute_|fIOWrite~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIOWrite~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIOWrite~5 .lut_mask = 16'hFEFC; +defparam \z80_|execute_|fIOWrite~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~15 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~15_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_mWrite~7_combout ) # ((\z80_|execute_|ctl_state_alu~2_combout & \z80_|execute_|ctl_mRead~5_combout )))) # (!\z80_|execute_|ctl_eval_cond~0_combout & +// (((\z80_|execute_|ctl_state_alu~2_combout & \z80_|execute_|ctl_mRead~5_combout )))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|ctl_mWrite~7_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_mRead~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~15 .lut_mask = 16'hF888; +defparam \z80_|execute_|ctl_mWrite~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~12 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~12_combout = (!\z80_|execute_|ctl_mWrite~18_combout & (((!\z80_|execute_|ctl_mRead~6_combout & !\z80_|execute_|ctl_mRead~8_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|ctl_mWrite~18_combout ), + .datac(\z80_|execute_|ctl_mRead~6_combout ), + .datad(\z80_|execute_|ctl_mRead~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~12 .lut_mask = 16'h1113; +defparam \z80_|execute_|ctl_mWrite~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~13 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~13_combout = (\z80_|execute_|ctl_mWrite~12_combout & (\z80_|execute_|ctl_mWrite~10_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|execute_|ctl_mWrite~8_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~8_combout ), + .datab(\z80_|execute_|ctl_mWrite~12_combout ), + .datac(\z80_|execute_|ctl_mWrite~10_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~13 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_mWrite~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~14 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~14_combout = (\z80_|execute_|ctl_mWrite~11_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~4_combout & (\z80_|execute_|ctl_mWrite~13_combout & \z80_|execute_|ctl_bus_db_oe~7_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~11_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), + .datac(\z80_|execute_|ctl_mWrite~13_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~14 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_mWrite~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~16 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~16_combout = (\z80_|execute_|ctl_mWrite~15_combout ) # (((\z80_|execute_|ixy_d~8_combout & !\z80_|execute_|ixy_d~17_combout )) # (!\z80_|execute_|ctl_mWrite~14_combout )) + + .dataa(\z80_|execute_|ctl_mWrite~15_combout ), + .datab(\z80_|execute_|ixy_d~8_combout ), + .datac(\z80_|execute_|ixy_d~17_combout ), + .datad(\z80_|execute_|ctl_mWrite~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~16 .lut_mask = 16'hAEFF; +defparam \z80_|execute_|ctl_mWrite~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y11_N7 +dffeas \z80_|memory_ifc_|DFFE_mwr_ff1 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|execute_|ctl_mWrite~16_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_mwr_ff1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_mwr_ff1 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_mwr_ff1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N22 +cycloneive_lcell_comb \z80_|memory_ifc_|wait_mwr~feeder ( +// Equation(s): +// \z80_|memory_ifc_|wait_mwr~feeder_combout = \z80_|memory_ifc_|DFFE_mwr_ff1~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|memory_ifc_|DFFE_mwr_ff1~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|wait_mwr~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_mwr~feeder .lut_mask = 16'hFF00; +defparam \z80_|memory_ifc_|wait_mwr~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y11_N23 +dffeas \z80_|memory_ifc_|wait_mwr ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|memory_ifc_|wait_mwr~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|wait_mwr~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_mwr .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|wait_mwr .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y11_N21 +dffeas \z80_|memory_ifc_|mwr_wr ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|memory_ifc_|wait_mwr~q ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|mwr_wr~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|mwr_wr .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|mwr_wr .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N20 +cycloneive_lcell_comb \z80_|memory_ifc_|nWR_out~0 ( +// Equation(s): +// \z80_|memory_ifc_|nWR_out~0_combout = (\z80_|memory_ifc_|mwr_wr~q ) # ((\z80_|execute_|fIOWrite~5_combout & \z80_|memory_ifc_|iorq~0_combout )) + + .dataa(\z80_|execute_|fIOWrite~5_combout ), + .datab(\z80_|memory_ifc_|iorq~0_combout ), + .datac(\z80_|memory_ifc_|mwr_wr~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|memory_ifc_|nWR_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|nWR_out~0 .lut_mask = 16'hF8F8; +defparam \z80_|memory_ifc_|nWR_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N16 +cycloneive_lcell_comb \Equal2~1 ( +// Equation(s): +// \Equal2~1_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\z80_|memory_ifc_|nRD_out~2_combout & !\z80_|memory_ifc_|nWR_out~0_combout )) + + .dataa(gnd), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|memory_ifc_|nRD_out~2_combout ), + .datad(\z80_|memory_ifc_|nWR_out~0_combout ), + .cin(gnd), + .combout(\Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \Equal2~1 .lut_mask = 16'h00C0; +defparam \Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|fMWrite~3 ( +// Equation(s): +// \z80_|execute_|fMWrite~3_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|sequencer_|DFFE_M4_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~3 .lut_mask = 16'h7373; +defparam \z80_|execute_|fMWrite~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|fMWrite~4 ( +// Equation(s): +// \z80_|execute_|fMWrite~4_combout = (!\z80_|execute_|fMWrite~3_combout & ((\z80_|execute_|ctl_mWrite~7_combout ) # ((\z80_|pla_decode_|Equal13~2_combout ) # (\z80_|execute_|ctl_mRead~5_combout )))) + + .dataa(\z80_|execute_|fMWrite~3_combout ), + .datab(\z80_|execute_|ctl_mWrite~7_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|execute_|ctl_mRead~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~4 .lut_mask = 16'h5554; +defparam \z80_|execute_|fMWrite~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N24 +cycloneive_lcell_comb \z80_|execute_|fMWrite~0 ( +// Equation(s): +// \z80_|execute_|fMWrite~0_combout = ((!\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|M5~q ) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~0 .lut_mask = 16'h0F5F; +defparam \z80_|execute_|fMWrite~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|fMWrite~2 ( +// Equation(s): +// \z80_|execute_|fMWrite~2_combout = (!\z80_|execute_|fMWrite~1_combout & (((\z80_|execute_|ixy_d~6_combout ) # (\z80_|execute_|ixy_d~5_combout )) # (!\z80_|execute_|fMWrite~0_combout ))) + + .dataa(\z80_|execute_|fMWrite~1_combout ), + .datab(\z80_|execute_|fMWrite~0_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~2 .lut_mask = 16'h5551; +defparam \z80_|execute_|fMWrite~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N8 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~3 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~3_combout = (\z80_|execute_|ctl_bus_inc_oe~26_combout & (!\z80_|execute_|fMWrite~4_combout & (!\z80_|execute_|fMWrite~2_combout & !\z80_|execute_|fIOWrite~5_combout ))) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~26_combout ), + .datab(\z80_|execute_|fMWrite~4_combout ), + .datac(\z80_|execute_|fMWrite~2_combout ), + .datad(\z80_|execute_|fIOWrite~5_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~3 .lut_mask = 16'h0002; +defparam \z80_|pin_control_|bus_db_pin_oe~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|fMWrite~8 ( +// Equation(s): +// \z80_|execute_|fMWrite~8_combout = (\z80_|pla_decode_|Equal9~1_combout & (((\z80_|execute_|ctl_alu_oe~0_combout ) # (\z80_|execute_|ctl_reg_in_hi~2_combout )))) # (!\z80_|pla_decode_|Equal9~1_combout & (\z80_|execute_|ctl_mRead~8_combout & +// ((\z80_|execute_|ctl_alu_oe~0_combout ) # (\z80_|execute_|ctl_reg_in_hi~2_combout )))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ctl_mRead~8_combout ), + .datac(\z80_|execute_|ctl_alu_oe~0_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~8 .lut_mask = 16'hEEE0; +defparam \z80_|execute_|fMWrite~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|fMWrite~7 ( +// Equation(s): +// \z80_|execute_|fMWrite~7_combout = (\z80_|execute_|ctl_state_alu~4_combout & ((\z80_|execute_|ctl_mRead~5_combout ) # ((\z80_|execute_|ctl_mWrite~7_combout ) # (\z80_|execute_|ctl_mRead~7_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~5_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_mWrite~7_combout ), + .datad(\z80_|execute_|ctl_mRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~7 .lut_mask = 16'hCCC8; +defparam \z80_|execute_|fMWrite~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N26 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~16 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~16_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & (((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|pla_decode_|Equal13~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), + .datab(\z80_|pla_decode_|Equal13~2_combout ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~16 .lut_mask = 16'h1555; +defparam \z80_|pin_control_|bus_db_pin_oe~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N14 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~8 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~8_combout = (\z80_|execute_|ixy_d~5_combout & (!\z80_|execute_|ctl_mRead~5_combout & ((!\z80_|execute_|ctl_ir_we~4_combout ) # (!\z80_|execute_|ctl_mRead~8_combout )))) # (!\z80_|execute_|ixy_d~5_combout & +// (((!\z80_|execute_|ctl_ir_we~4_combout )) # (!\z80_|execute_|ctl_mRead~8_combout ))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_mRead~8_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|execute_|ctl_mRead~5_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~8 .lut_mask = 16'h153F; +defparam \z80_|pin_control_|bus_db_pin_oe~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|fMWrite~6 ( +// Equation(s): +// \z80_|execute_|fMWrite~6_combout = ((\z80_|pla_decode_|Equal46~0_combout ) # ((\z80_|ir_|opcode [6] & !\z80_|ir_|opcode [7]))) # (!\z80_|execute_|ctl_ir_we~5_combout ) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|execute_|ctl_ir_we~5_combout ), + .datad(\z80_|pla_decode_|Equal46~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~6 .lut_mask = 16'hFF2F; +defparam \z80_|execute_|fMWrite~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N8 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~9 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~9_combout = (\z80_|execute_|fMWrite~6_combout & (((\z80_|execute_|fIOWrite~0_combout )) # (!\z80_|execute_|ctl_mWrite~8_combout ))) # (!\z80_|execute_|fMWrite~6_combout & (\z80_|execute_|fMWrite~0_combout & +// ((\z80_|execute_|fIOWrite~0_combout ) # (!\z80_|execute_|ctl_mWrite~8_combout )))) + + .dataa(\z80_|execute_|fMWrite~6_combout ), + .datab(\z80_|execute_|ctl_mWrite~8_combout ), + .datac(\z80_|execute_|fIOWrite~0_combout ), + .datad(\z80_|execute_|fMWrite~0_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~9 .lut_mask = 16'hF3A2; +defparam \z80_|pin_control_|bus_db_pin_oe~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N28 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~7 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~7_combout = (\z80_|execute_|ixy_d~7_combout & (((\z80_|execute_|fMRead~3_combout & !\z80_|execute_|ctl_mRead~4_combout )))) # (!\z80_|execute_|ixy_d~7_combout & (((!\z80_|execute_|ctl_mRead~4_combout )) # +// (!\z80_|execute_|ctl_alu_oe~0_combout ))) + + .dataa(\z80_|execute_|ctl_alu_oe~0_combout ), + .datab(\z80_|execute_|fMRead~3_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ctl_mRead~4_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~7 .lut_mask = 16'h05CF; +defparam \z80_|pin_control_|bus_db_pin_oe~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N10 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~10 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~10_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (\z80_|pin_control_|bus_db_pin_oe~8_combout & (\z80_|pin_control_|bus_db_pin_oe~9_combout & \z80_|pin_control_|bus_db_pin_oe~7_combout ))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~8_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~9_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~7_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~10 .lut_mask = 16'h8000; +defparam \z80_|pin_control_|bus_db_pin_oe~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N20 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~11 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~11_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout & (!\z80_|execute_|fMWrite~7_combout & (\z80_|execute_|ctl_reg_sel_wz~7_combout & \z80_|pin_control_|bus_db_pin_oe~10_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), + .datab(\z80_|execute_|fMWrite~7_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~7_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~10_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~11 .lut_mask = 16'h2000; +defparam \z80_|pin_control_|bus_db_pin_oe~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N6 +cycloneive_lcell_comb \z80_|execute_|fMWrite~5 ( +// Equation(s): +// \z80_|execute_|fMWrite~5_combout = (!\z80_|execute_|ctl_mWrite~17_combout & (!\z80_|execute_|ctl_mWrite~6_combout & !\z80_|execute_|ctl_mRead~5_combout )) + + .dataa(\z80_|execute_|ctl_mWrite~17_combout ), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datac(\z80_|execute_|ctl_mRead~5_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~5 .lut_mask = 16'h0101; +defparam \z80_|execute_|fMWrite~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N28 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~6 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~6_combout = (\z80_|execute_|ctl_inc_dec~2_combout & ((\z80_|execute_|fMWrite~5_combout ) # ((!\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ixy_d~6_combout )))) + + .dataa(\z80_|execute_|fMWrite~5_combout ), + .datab(\z80_|execute_|ctl_inc_dec~2_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ixy_d~6_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~6 .lut_mask = 16'h888C; +defparam \z80_|pin_control_|bus_db_pin_oe~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N26 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~12 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~12_combout = (!\z80_|execute_|fMWrite~8_combout & (\z80_|pin_control_|bus_db_pin_oe~11_combout & (\z80_|execute_|ctl_bus_inc_oe~30_combout & \z80_|pin_control_|bus_db_pin_oe~6_combout ))) + + .dataa(\z80_|execute_|fMWrite~8_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~11_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~30_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~6_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~12 .lut_mask = 16'h4000; +defparam \z80_|pin_control_|bus_db_pin_oe~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y16_N20 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~4 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~4_combout = (\z80_|pla_decode_|Equal11~0_combout & (!\z80_|execute_|ixy_d~7_combout & ((!\z80_|execute_|ctl_mRead~6_combout ) # (!\z80_|execute_|ctl_reg_in_hi~2_combout )))) # (!\z80_|pla_decode_|Equal11~0_combout & +// (((!\z80_|execute_|ctl_mRead~6_combout )) # (!\z80_|execute_|ctl_reg_in_hi~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datac(\z80_|execute_|ctl_mRead~6_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~4 .lut_mask = 16'h153F; +defparam \z80_|pin_control_|bus_db_pin_oe~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N30 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~5 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~5_combout = (\z80_|pin_control_|bus_db_pin_oe~4_combout & (((\z80_|execute_|ixy_d~4_combout ) # (!\z80_|execute_|ctl_mWrite~7_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|execute_|ctl_mWrite~7_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~4_combout ), + .datad(\z80_|execute_|ixy_d~4_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~5 .lut_mask = 16'hF070; +defparam \z80_|pin_control_|bus_db_pin_oe~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N24 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~13 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~13_combout = (\z80_|pin_control_|bus_db_pin_oe~12_combout & (\z80_|pin_control_|bus_db_pin_oe~5_combout & ((!\z80_|execute_|ixy_d~6_combout ) # (!\z80_|pla_decode_|Equal11~0_combout )))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~12_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~5_combout ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|execute_|ixy_d~6_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~13 .lut_mask = 16'h0888; +defparam \z80_|pin_control_|bus_db_pin_oe~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y18_N12 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~14 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~14_combout = (\z80_|pin_control_|bus_db_pin_oe~3_combout & (\z80_|execute_|ctl_inc_cy~35_combout & (\z80_|execute_|ctl_apin_mux~0_combout & \z80_|pin_control_|bus_db_pin_oe~13_combout ))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~3_combout ), + .datab(\z80_|execute_|ctl_inc_cy~35_combout ), + .datac(\z80_|execute_|ctl_apin_mux~0_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~13_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~14 .lut_mask = 16'h8000; +defparam \z80_|pin_control_|bus_db_pin_oe~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N4 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~2 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~2_combout = (\z80_|sequencer_|DFFE_T3_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~2 .lut_mask = 16'hFFCC; +defparam \z80_|pin_control_|bus_db_pin_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N14 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~15 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~15_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout & (\z80_|execute_|fIOWrite~5_combout & ((\z80_|sequencer_|DFFE_T4_ff~q )))) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout & +// ((\z80_|pin_control_|bus_db_pin_oe~2_combout ) # ((\z80_|execute_|fIOWrite~5_combout & \z80_|sequencer_|DFFE_T4_ff~q )))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .datab(\z80_|execute_|fIOWrite~5_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~2_combout ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~15 .lut_mask = 16'hDC50; +defparam \z80_|pin_control_|bus_db_pin_oe~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N12 +cycloneive_lcell_comb \z80_|clk_delay_|DFF_inst5~feeder ( +// Equation(s): +// \z80_|clk_delay_|DFF_inst5~feeder_combout = \z80_|clk_delay_|SYNTHESIZED_WIRE_7~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ), + .cin(gnd), + .combout(\z80_|clk_delay_|DFF_inst5~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|clk_delay_|DFF_inst5~feeder .lut_mask = 16'hFF00; +defparam \z80_|clk_delay_|DFF_inst5~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X38_Y11_N13 +dffeas \z80_|clk_delay_|DFF_inst5 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|clk_delay_|DFF_inst5~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|clk_delay_|DFF_inst5~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|clk_delay_|DFF_inst5 .is_wysiwyg = "true"; +defparam \z80_|clk_delay_|DFF_inst5 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y11_N15 +dffeas \z80_|memory_ifc_|wait_iorqinta ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|clk_delay_|DFF_inst5~q ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|wait_iorqinta~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_iorqinta .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|wait_iorqinta .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y11_N31 +dffeas \z80_|memory_ifc_|DFFE_intr_ff3 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|memory_ifc_|wait_iorqinta~q ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_intr_ff3~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_intr_ff3 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_intr_ff3 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N30 +cycloneive_lcell_comb \z80_|memory_ifc_|nIORQ_out~0 ( +// Equation(s): +// \z80_|memory_ifc_|nIORQ_out~0_combout = (\z80_|memory_ifc_|iorq~0_combout ) # ((\z80_|memory_ifc_|wait_iorqinta~q ) # (\z80_|memory_ifc_|DFFE_intr_ff3~q )) + + .dataa(\z80_|memory_ifc_|iorq~0_combout ), + .datab(\z80_|memory_ifc_|wait_iorqinta~q ), + .datac(\z80_|memory_ifc_|DFFE_intr_ff3~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|memory_ifc_|nIORQ_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|nIORQ_out~0 .lut_mask = 16'hFEFE; +defparam \z80_|memory_ifc_|nIORQ_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N28 +cycloneive_lcell_comb \Equal2~0 ( +// Equation(s): +// \Equal2~0_combout = (\z80_|memory_ifc_|nIORQ_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\z80_|memory_ifc_|nRD_out~2_combout & !\z80_|memory_ifc_|nWR_out~0_combout ))) + + .dataa(\z80_|memory_ifc_|nIORQ_out~0_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|memory_ifc_|nRD_out~2_combout ), + .datad(\z80_|memory_ifc_|nWR_out~0_combout ), + .cin(gnd), + .combout(\Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \Equal2~0 .lut_mask = 16'h0080; +defparam \Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~2 ( +// Equation(s): +// \z80_|execute_|ctl_apin_mux~2_combout = ((\z80_|execute_|ctl_apin_mux~1_combout & \z80_|execute_|ctl_mWrite~6_combout )) # (!\z80_|execute_|ctl_inc_dec~6_combout ) + + .dataa(\z80_|execute_|ctl_apin_mux~1_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_inc_dec~6_combout ), + .datad(\z80_|execute_|ctl_mWrite~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_apin_mux~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_apin_mux~2 .lut_mask = 16'hAF0F; +defparam \z80_|execute_|ctl_apin_mux~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N8 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[10]~10 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[10]~10_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [10]))) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [10]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[10]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[10]~10 .lut_mask = 16'hDD88; +defparam \z80_|address_pins_|DFFE_apin_latch[10]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux2~0 ( +// Equation(s): +// \z80_|execute_|ctl_apin_mux2~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_apin_mux2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_apin_mux2~0 .lut_mask = 16'h4545; +defparam \z80_|execute_|ctl_apin_mux2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N24 +cycloneive_lcell_comb \z80_|pin_control_|bus_ab_pin_we~0 ( +// Equation(s): +// \z80_|pin_control_|bus_ab_pin_we~0_combout = ((\z80_|execute_|fIORead~3_combout ) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout )) # (!\z80_|sequencer_|DFFE_M1_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|execute_|fIORead~3_combout ), + .datac(gnd), + .datad(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_ab_pin_we~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_ab_pin_we~0 .lut_mask = 16'hDDFF; +defparam \z80_|pin_control_|bus_ab_pin_we~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N26 +cycloneive_lcell_comb \z80_|pin_control_|bus_ab_pin_we~1 ( +// Equation(s): +// \z80_|pin_control_|bus_ab_pin_we~1_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # ((!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|execute_|fMRead~36_combout ) # (\z80_|pin_control_|bus_ab_pin_we~0_combout )))) + + .dataa(\z80_|execute_|fMRead~36_combout ), + .datab(\z80_|pin_control_|bus_ab_pin_we~0_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_ab_pin_we~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_ab_pin_we~1 .lut_mask = 16'hFF0E; +defparam \z80_|pin_control_|bus_ab_pin_we~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y13_N9 +dffeas \z80_|address_pins_|DFFE_apin_latch[10] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[10]~10_combout ), + .asdata(\z80_|address_latch_|Q [10]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [10]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[10] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[10] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X18_Y34_N1 +cycloneive_io_ibuf \PS2_DAT~input ( + .i(PS2_DAT), + .ibar(gnd), + .o(\PS2_DAT~input_o )); +// synopsys translate_off +defparam \PS2_DAT~input .bus_hold = "false"; +defparam \PS2_DAT~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X53_Y14_N1 +cycloneive_io_ibuf \KEY[0]~input ( + .i(KEY[0]), + .ibar(gnd), + .o(\KEY[0]~input_o )); +// synopsys translate_off +defparam \KEY[0]~input .bus_hold = "false"; +defparam \KEY[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X52_Y17_N6 +cycloneive_lcell_comb reset( +// Equation(s): +// \reset~combout = (!\KEY[0]~input_o ) # (!\ula_|pll_|altpll_component|auto_generated|wire_pll1_locked ) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|pll_|altpll_component|auto_generated|wire_pll1_locked ), + .datad(\KEY[0]~input_o ), + .cin(gnd), + .combout(\reset~combout ), + .cout()); +// synopsys translate_off +defparam reset.lut_mask = 16'h0FFF; +defparam reset.sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: CLKCTRL_G8 +cycloneive_clkctrl \reset~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\reset~combout }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\reset~clkctrl_outclk )); +// synopsys translate_off +defparam \reset~clkctrl .clock_type = "global clock"; +defparam \reset~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y10_N0 +cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~3 ( +// Equation(s): +// \ula_|ps2_keyboard_|bit_count~3_combout = (\ula_|ps2_keyboard_|bit_count [2] & (\ula_|ps2_keyboard_|bit_count [0] & (!\ula_|ps2_keyboard_|bit_count [3] & \ula_|ps2_keyboard_|bit_count [1]))) # (!\ula_|ps2_keyboard_|bit_count [2] & +// (((\ula_|ps2_keyboard_|bit_count [3] & !\ula_|ps2_keyboard_|bit_count [1])))) + + .dataa(\ula_|ps2_keyboard_|bit_count [0]), + .datab(\ula_|ps2_keyboard_|bit_count [2]), + .datac(\ula_|ps2_keyboard_|bit_count [3]), + .datad(\ula_|ps2_keyboard_|bit_count [1]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|bit_count~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count~3 .lut_mask = 16'h0830; +defparam \ula_|ps2_keyboard_|bit_count~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X9_Y34_N8 +cycloneive_io_ibuf \PS2_CLK~input ( + .i(PS2_CLK), + .ibar(gnd), + .o(\PS2_CLK~input_o )); +// synopsys translate_off +defparam \PS2_CLK~input .bus_hold = "false"; +defparam \PS2_CLK~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y26_N20 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[7]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[7]~feeder_combout = \PS2_CLK~input_o + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\PS2_CLK~input_o ), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[7]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y26_N21 +dffeas \ula_|ps2_keyboard_|clk_filter[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[7] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y26_N18 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[6]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[6]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [7] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [7]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[6]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y26_N19 +dffeas \ula_|ps2_keyboard_|clk_filter[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[6] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y26_N0 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[5]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[5]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [6] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [6]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[5]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y26_N1 +dffeas \ula_|ps2_keyboard_|clk_filter[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[5] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y26_N6 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[4]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[4]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [5]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[4]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y26_N7 +dffeas \ula_|ps2_keyboard_|clk_filter[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[4] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y26_N10 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[3]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[3]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [4] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [4]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[3]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y26_N11 +dffeas \ula_|ps2_keyboard_|clk_filter[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[3]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[3] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y26_N24 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[2]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[2]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [3] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [3]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[2]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y26_N25 +dffeas \ula_|ps2_keyboard_|clk_filter[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[2] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y26_N26 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[1]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[1]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [2]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[1]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y26_N27 +dffeas \ula_|ps2_keyboard_|clk_filter[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[1] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y26_N16 +cycloneive_lcell_comb \ula_|ps2_keyboard_|Equal0~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|Equal0~0_combout = (!\ula_|ps2_keyboard_|clk_filter [4] & (!\ula_|ps2_keyboard_|clk_filter [7] & (!\ula_|ps2_keyboard_|clk_filter [6] & !\ula_|ps2_keyboard_|clk_filter [5]))) + + .dataa(\ula_|ps2_keyboard_|clk_filter [4]), + .datab(\ula_|ps2_keyboard_|clk_filter [7]), + .datac(\ula_|ps2_keyboard_|clk_filter [6]), + .datad(\ula_|ps2_keyboard_|clk_filter [5]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|Equal0~0 .lut_mask = 16'h0001; +defparam \ula_|ps2_keyboard_|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y26_N12 +cycloneive_lcell_comb \ula_|ps2_keyboard_|Equal0~1 ( +// Equation(s): +// \ula_|ps2_keyboard_|Equal0~1_combout = (!\ula_|ps2_keyboard_|clk_filter [3] & (!\ula_|ps2_keyboard_|clk_filter [2] & (!\ula_|ps2_keyboard_|clk_filter [1] & \ula_|ps2_keyboard_|Equal0~0_combout ))) + + .dataa(\ula_|ps2_keyboard_|clk_filter [3]), + .datab(\ula_|ps2_keyboard_|clk_filter [2]), + .datac(\ula_|ps2_keyboard_|clk_filter [1]), + .datad(\ula_|ps2_keyboard_|Equal0~0_combout ), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|Equal0~1 .lut_mask = 16'h0100; +defparam \ula_|ps2_keyboard_|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y26_N2 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[0]~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[0]~0_combout = !\ula_|ps2_keyboard_|clk_filter [1] + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|clk_filter [1]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[0]~0 .lut_mask = 16'h0F0F; +defparam \ula_|ps2_keyboard_|clk_filter[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y26_N3 +dffeas \ula_|ps2_keyboard_|clk_filter[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[0]~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[0] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y26_N22 +cycloneive_lcell_comb \ula_|ps2_keyboard_|ps2_clk_in~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|ps2_clk_in~0_combout = (\ula_|ps2_keyboard_|Equal0~1_combout & ((\ula_|ps2_keyboard_|clk_filter [0]))) # (!\ula_|ps2_keyboard_|Equal0~1_combout & (\ula_|ps2_keyboard_|ps2_clk_in~q )) + + .dataa(\ula_|ps2_keyboard_|Equal0~1_combout ), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|ps2_clk_in~q ), + .datad(\ula_|ps2_keyboard_|clk_filter [0]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|ps2_clk_in~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|ps2_clk_in~0 .lut_mask = 16'hFA50; +defparam \ula_|ps2_keyboard_|ps2_clk_in~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y26_N23 +dffeas \ula_|ps2_keyboard_|ps2_clk_in ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|ps2_clk_in~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|ps2_clk_in~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|ps2_clk_in .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|ps2_clk_in .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y26_N28 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_edge~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_edge~0_combout = (\ula_|ps2_keyboard_|Equal0~1_combout & (!\ula_|ps2_keyboard_|ps2_clk_in~q & \ula_|ps2_keyboard_|clk_filter [0])) + + .dataa(\ula_|ps2_keyboard_|Equal0~1_combout ), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|ps2_clk_in~q ), + .datad(\ula_|ps2_keyboard_|clk_filter [0]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_edge~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_edge~0 .lut_mask = 16'h0A00; +defparam \ula_|ps2_keyboard_|clk_edge~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y26_N29 +dffeas \ula_|ps2_keyboard_|clk_edge ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_edge~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_edge~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_edge .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_edge .power_up = "low"; +// synopsys translate_on + +// Location: FF_X21_Y10_N1 +dffeas \ula_|ps2_keyboard_|bit_count[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|bit_count~3_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|clk_edge~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|bit_count [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count[3] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|bit_count[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y10_N28 +cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~1 ( +// Equation(s): +// \ula_|ps2_keyboard_|bit_count~1_combout = (!\ula_|ps2_keyboard_|bit_count [3] & (\ula_|ps2_keyboard_|bit_count [2] $ (((\ula_|ps2_keyboard_|bit_count [0] & \ula_|ps2_keyboard_|bit_count [1]))))) + + .dataa(\ula_|ps2_keyboard_|bit_count [0]), + .datab(\ula_|ps2_keyboard_|bit_count [3]), + .datac(\ula_|ps2_keyboard_|bit_count [2]), + .datad(\ula_|ps2_keyboard_|bit_count [1]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|bit_count~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count~1 .lut_mask = 16'h1230; +defparam \ula_|ps2_keyboard_|bit_count~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y10_N29 +dffeas \ula_|ps2_keyboard_|bit_count[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|bit_count~1_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|clk_edge~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|bit_count [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count[2] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|bit_count[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y10_N10 +cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~2 ( +// Equation(s): +// \ula_|ps2_keyboard_|bit_count~2_combout = (\ula_|ps2_keyboard_|bit_count [0] & (!\ula_|ps2_keyboard_|bit_count [1] & ((!\ula_|ps2_keyboard_|bit_count [3]) # (!\ula_|ps2_keyboard_|bit_count [2])))) # (!\ula_|ps2_keyboard_|bit_count [0] & +// (((\ula_|ps2_keyboard_|bit_count [1] & !\ula_|ps2_keyboard_|bit_count [3])))) + + .dataa(\ula_|ps2_keyboard_|bit_count [0]), + .datab(\ula_|ps2_keyboard_|bit_count [2]), + .datac(\ula_|ps2_keyboard_|bit_count [1]), + .datad(\ula_|ps2_keyboard_|bit_count [3]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|bit_count~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count~2 .lut_mask = 16'h025A; +defparam \ula_|ps2_keyboard_|bit_count~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y10_N11 +dffeas \ula_|ps2_keyboard_|bit_count[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|bit_count~2_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|clk_edge~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|bit_count [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count[1] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|bit_count[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y10_N22 +cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|bit_count~0_combout = (!\ula_|ps2_keyboard_|bit_count [0] & (((!\ula_|ps2_keyboard_|bit_count [1] & !\ula_|ps2_keyboard_|bit_count [2])) # (!\ula_|ps2_keyboard_|bit_count [3]))) + + .dataa(\ula_|ps2_keyboard_|bit_count [1]), + .datab(\ula_|ps2_keyboard_|bit_count [2]), + .datac(\ula_|ps2_keyboard_|bit_count [0]), + .datad(\ula_|ps2_keyboard_|bit_count [3]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|bit_count~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count~0 .lut_mask = 16'h010F; +defparam \ula_|ps2_keyboard_|bit_count~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y10_N23 +dffeas \ula_|ps2_keyboard_|bit_count[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|bit_count~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|clk_edge~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|bit_count [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count[0] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|bit_count[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y10_N2 +cycloneive_lcell_comb \ula_|ps2_keyboard_|always1~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|always1~0_combout = (!\ula_|ps2_keyboard_|bit_count [1] & (!\ula_|ps2_keyboard_|bit_count [2] & (!\PS2_DAT~input_o & !\ula_|ps2_keyboard_|bit_count [3]))) + + .dataa(\ula_|ps2_keyboard_|bit_count [1]), + .datab(\ula_|ps2_keyboard_|bit_count [2]), + .datac(\PS2_DAT~input_o ), + .datad(\ula_|ps2_keyboard_|bit_count [3]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|always1~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|always1~0 .lut_mask = 16'h0001; +defparam \ula_|ps2_keyboard_|always1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y10_N12 +cycloneive_lcell_comb \ula_|ps2_keyboard_|LessThan0~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|LessThan0~0_combout = (\ula_|ps2_keyboard_|bit_count [3] & ((\ula_|ps2_keyboard_|bit_count [1]) # (\ula_|ps2_keyboard_|bit_count [2]))) + + .dataa(\ula_|ps2_keyboard_|bit_count [1]), + .datab(\ula_|ps2_keyboard_|bit_count [2]), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|bit_count [3]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|LessThan0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|LessThan0~0 .lut_mask = 16'hEE00; +defparam \ula_|ps2_keyboard_|LessThan0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y10_N26 +cycloneive_lcell_comb \ula_|ps2_keyboard_|shiftreg[0]~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|shiftreg[0]~0_combout = (\ula_|ps2_keyboard_|clk_edge~q & (!\ula_|ps2_keyboard_|LessThan0~0_combout & ((\ula_|ps2_keyboard_|bit_count [0]) # (!\ula_|ps2_keyboard_|always1~0_combout )))) + + .dataa(\ula_|ps2_keyboard_|bit_count [0]), + .datab(\ula_|ps2_keyboard_|always1~0_combout ), + .datac(\ula_|ps2_keyboard_|clk_edge~q ), + .datad(\ula_|ps2_keyboard_|LessThan0~0_combout ), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[0]~0 .lut_mask = 16'h00B0; +defparam \ula_|ps2_keyboard_|shiftreg[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y8_N17 +dffeas \ula_|ps2_keyboard_|shiftreg[8] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\PS2_DAT~input_o ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [8]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[8] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N14 +cycloneive_lcell_comb \ula_|ps2_keyboard_|shiftreg[7]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|shiftreg[7]~feeder_combout = \ula_|ps2_keyboard_|shiftreg [8] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [8]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|shiftreg[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[7]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|shiftreg[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y8_N15 +dffeas \ula_|ps2_keyboard_|shiftreg[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|shiftreg[7]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[7] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y8_N9 +dffeas \ula_|ps2_keyboard_|shiftreg[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [7]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[6] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y8_N5 +dffeas \ula_|ps2_keyboard_|shiftreg[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [6]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[5] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y8_N23 +dffeas \ula_|ps2_keyboard_|shiftreg[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [5]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[4] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y9_N17 +dffeas \ula_|ps2_keyboard_|shiftreg[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [4]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[3] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y8_N23 +dffeas \ula_|ps2_keyboard_|shiftreg[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [3]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[2] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y8_N21 +dffeas \ula_|ps2_keyboard_|shiftreg[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [2]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[1] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N18 +cycloneive_lcell_comb \ula_|ps2_keyboard_|shiftreg[0]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|shiftreg[0]~feeder_combout = \ula_|ps2_keyboard_|shiftreg [1] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|shiftreg[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[0]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|shiftreg[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y10_N19 +dffeas \ula_|ps2_keyboard_|shiftreg[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|shiftreg[0]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[0] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N4 +cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|WideXor0~0_combout = \ula_|ps2_keyboard_|shiftreg [1] $ (\ula_|ps2_keyboard_|shiftreg [0] $ (\ula_|ps2_keyboard_|shiftreg [3] $ (\ula_|ps2_keyboard_|shiftreg [2]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|WideXor0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|WideXor0~0 .lut_mask = 16'h6996; +defparam \ula_|ps2_keyboard_|WideXor0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N16 +cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~1 ( +// Equation(s): +// \ula_|ps2_keyboard_|WideXor0~1_combout = \ula_|ps2_keyboard_|shiftreg [6] $ (\ula_|ps2_keyboard_|shiftreg [5] $ (\ula_|ps2_keyboard_|shiftreg [8] $ (\ula_|ps2_keyboard_|shiftreg [7]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|ps2_keyboard_|shiftreg [8]), + .datad(\ula_|ps2_keyboard_|shiftreg [7]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|WideXor0~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|WideXor0~1 .lut_mask = 16'h6996; +defparam \ula_|ps2_keyboard_|WideXor0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N22 +cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~2 ( +// Equation(s): +// \ula_|ps2_keyboard_|WideXor0~2_combout = \ula_|ps2_keyboard_|shiftreg [4] $ (\ula_|ps2_keyboard_|WideXor0~0_combout $ (\ula_|ps2_keyboard_|WideXor0~1_combout )) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|WideXor0~0_combout ), + .datad(\ula_|ps2_keyboard_|WideXor0~1_combout ), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|WideXor0~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|WideXor0~2 .lut_mask = 16'hA55A; +defparam \ula_|ps2_keyboard_|WideXor0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y10_N4 +cycloneive_lcell_comb \ula_|ps2_keyboard_|scan_code_ready~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|scan_code_ready~0_combout = (\PS2_DAT~input_o & (\ula_|ps2_keyboard_|clk_edge~q & (\ula_|ps2_keyboard_|WideXor0~2_combout & \ula_|ps2_keyboard_|LessThan0~0_combout ))) + + .dataa(\PS2_DAT~input_o ), + .datab(\ula_|ps2_keyboard_|clk_edge~q ), + .datac(\ula_|ps2_keyboard_|WideXor0~2_combout ), + .datad(\ula_|ps2_keyboard_|LessThan0~0_combout ), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|scan_code_ready~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|scan_code_ready~0 .lut_mask = 16'h8000; +defparam \ula_|ps2_keyboard_|scan_code_ready~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y10_N5 +dffeas \ula_|ps2_keyboard_|scan_code_ready ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|scan_code_ready~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|scan_code_ready~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|scan_code_ready .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|scan_code_ready .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~0 ( +// Equation(s): +// \ula_|zx_keyboard_|Equal0~0_combout = (\ula_|ps2_keyboard_|shiftreg [7] & (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [7]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|Equal0~0 .lut_mask = 16'h0200; +defparam \ula_|zx_keyboard_|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~1 ( +// Equation(s): +// \ula_|zx_keyboard_|Equal0~1_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|Equal0~0_combout & !\ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|zx_keyboard_|Equal0~0_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|Equal0~1 .lut_mask = 16'h0020; +defparam \ula_|zx_keyboard_|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|released~0 ( +// Equation(s): +// \ula_|zx_keyboard_|released~0_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (\ula_|zx_keyboard_|Equal0~1_combout & ((\ula_|ps2_keyboard_|shiftreg [4]) # (\ula_|zx_keyboard_|released~q )))) # (!\ula_|ps2_keyboard_|scan_code_ready~q & +// (((\ula_|zx_keyboard_|released~q )))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|scan_code_ready~q ), + .datac(\ula_|zx_keyboard_|released~q ), + .datad(\ula_|zx_keyboard_|Equal0~1_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|released~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|released~0 .lut_mask = 16'hF830; +defparam \ula_|zx_keyboard_|released~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y8_N25 +dffeas \ula_|zx_keyboard_|released ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|released~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|released~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|released .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|released .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|extended~0 ( +// Equation(s): +// \ula_|zx_keyboard_|extended~0_combout = (\ula_|zx_keyboard_|Equal0~1_combout & ((\ula_|zx_keyboard_|extended~q ) # (!\ula_|ps2_keyboard_|shiftreg [4]))) + + .dataa(\ula_|zx_keyboard_|Equal0~1_combout ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|extended~q ), + .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|extended~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|extended~0 .lut_mask = 16'hA0AA; +defparam \ula_|zx_keyboard_|extended~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y8_N31 +dffeas \ula_|zx_keyboard_|extended ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|extended~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|scan_code_ready~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|extended~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|extended .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|extended .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~21 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][1]~21_combout = (!\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [7] & \ula_|ps2_keyboard_|scan_code_ready~q )) + + .dataa(\ula_|zx_keyboard_|extended~q ), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [7]), + .datad(\ula_|ps2_keyboard_|scan_code_ready~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][1]~21_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][1]~21 .lut_mask = 16'h0500; +defparam \ula_|zx_keyboard_|keys[7][1]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~22 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][4]~22_combout = (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [4]) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][4]~22_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][4]~22 .lut_mask = 16'hA0A0; +defparam \ula_|zx_keyboard_|keys[5][4]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][4]~23 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][4]~23_combout = (\ula_|zx_keyboard_|keys[7][1]~21_combout & (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[5][4]~22_combout & !\ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|zx_keyboard_|keys[7][1]~21_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|zx_keyboard_|keys[5][4]~22_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][4]~23_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][4]~23 .lut_mask = 16'h0020; +defparam \ula_|zx_keyboard_|keys[1][4]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][1]~24 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][1]~24_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[1][4]~23_combout )) + + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(gnd), + .datad(\ula_|zx_keyboard_|keys[1][4]~23_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][1]~24_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][1]~24 .lut_mask = 16'h2200; +defparam \ula_|zx_keyboard_|keys[2][1]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][1]~25 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][1]~25_combout = (\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[2][1]~24_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[2][1]~24_combout & ((\ula_|zx_keyboard_|keys[2][1]~q ))))) # +// (!\ula_|ps2_keyboard_|shiftreg [3] & (((\ula_|zx_keyboard_|keys[2][1]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|zx_keyboard_|keys[2][1]~q ), + .datad(\ula_|zx_keyboard_|keys[2][1]~24_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][1]~25_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][1]~25 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[2][1]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y9_N21 +dffeas \ula_|zx_keyboard_|keys[2][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[2][1]~25_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[2][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[2][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~0 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row~0_combout = ((\z80_|address_pins_|DFFE_apin_latch [10]) # (!\ula_|zx_keyboard_|keys[2][1]~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [10]), + .datad(\ula_|zx_keyboard_|keys[2][1]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row~0 .lut_mask = 16'hF3FF; +defparam \ula_|zx_keyboard_|key_row~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~26 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][1]~26_combout = (\ula_|zx_keyboard_|keys[7][1]~21_combout & (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[5][4]~22_combout & !\ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|zx_keyboard_|keys[7][1]~21_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|zx_keyboard_|keys[5][4]~22_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][1]~26_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][1]~26 .lut_mask = 16'h0020; +defparam \ula_|zx_keyboard_|keys[3][1]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~27 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][1]~27_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [3])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][1]~27_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][1]~27 .lut_mask = 16'h2200; +defparam \ula_|zx_keyboard_|keys[3][1]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~28 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][1]~28_combout = (\ula_|zx_keyboard_|keys[3][1]~26_combout & ((\ula_|zx_keyboard_|keys[3][1]~27_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][1]~27_combout & ((\ula_|zx_keyboard_|keys[3][1]~q +// ))))) # (!\ula_|zx_keyboard_|keys[3][1]~26_combout & (((\ula_|zx_keyboard_|keys[3][1]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[3][1]~26_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[3][1]~q ), + .datad(\ula_|zx_keyboard_|keys[3][1]~27_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][1]~28_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][1]~28 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[3][1]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y9_N29 +dffeas \ula_|zx_keyboard_|keys[3][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[3][1]~28_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[3][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[3][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N12 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[11]~11 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[11]~11_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|address [11])) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [11]))) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [11]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[11]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[11]~11 .lut_mask = 16'hDD88; +defparam \z80_|address_pins_|DFFE_apin_latch[11]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y13_N13 +dffeas \z80_|address_pins_|DFFE_apin_latch[11] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[11]~11_combout ), + .asdata(\z80_|address_latch_|Q [11]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [11]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[11] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y6_N16 +cycloneive_lcell_comb \z80_|address_pins_|abus[11]~19 ( +// Equation(s): +// \z80_|address_pins_|abus[11]~19_combout = (\z80_|address_pins_|DFFE_apin_latch [11]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [11]), + .cin(gnd), + .combout(\z80_|address_pins_|abus[11]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[11]~19 .lut_mask = 16'hFF0F; +defparam \z80_|address_pins_|abus[11]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~17 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][4]~17_combout = (!\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [7] & \ula_|ps2_keyboard_|scan_code_ready~q ))) + + .dataa(\ula_|zx_keyboard_|extended~q ), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [7]), + .datad(\ula_|ps2_keyboard_|scan_code_ready~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][4]~17_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][4]~17 .lut_mask = 16'h0100; +defparam \ula_|zx_keyboard_|keys[7][4]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~18 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][4]~18_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][4]~18_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][4]~18 .lut_mask = 16'h4000; +defparam \ula_|zx_keyboard_|keys[6][4]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][1]~19 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][1]~19_combout = (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[7][4]~17_combout & \ula_|zx_keyboard_|keys[6][4]~18_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|zx_keyboard_|keys[7][4]~17_combout ), + .datad(\ula_|zx_keyboard_|keys[6][4]~18_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][1]~19_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][1]~19 .lut_mask = 16'h4000; +defparam \ula_|zx_keyboard_|keys[1][1]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][1]~20 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][1]~20_combout = (\ula_|zx_keyboard_|keys[1][1]~19_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[1][1]~19_combout & ((\ula_|zx_keyboard_|keys[1][1]~q ))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[1][1]~q ), + .datad(\ula_|zx_keyboard_|keys[1][1]~19_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][1]~20_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][1]~20 .lut_mask = 16'h55F0; +defparam \ula_|zx_keyboard_|keys[1][1]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y7_N17 +dffeas \ula_|zx_keyboard_|keys[1][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[1][1]~20_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[1][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[1][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N4 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[9]~9 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[9]~9_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [9]))) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [9]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[9]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[9]~9 .lut_mask = 16'hDD88; +defparam \z80_|address_pins_|DFFE_apin_latch[9]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y10_N5 +dffeas \z80_|address_pins_|DFFE_apin_latch[9] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[9]~9_combout ), + .asdata(\z80_|address_latch_|Q [9]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [9]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[9] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N10 +cycloneive_lcell_comb \z80_|address_pins_|abus[9]~17 ( +// Equation(s): +// \z80_|address_pins_|abus[9]~17_combout = (\z80_|address_pins_|DFFE_apin_latch [9]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [9]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_pins_|abus[9]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[9]~17 .lut_mask = 16'hCFCF; +defparam \z80_|address_pins_|abus[9]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~13 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][0]~13_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (!\ula_|ps2_keyboard_|shiftreg [7] & !\ula_|zx_keyboard_|Equal0~1_combout )) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|scan_code_ready~q ), + .datac(\ula_|ps2_keyboard_|shiftreg [7]), + .datad(\ula_|zx_keyboard_|Equal0~1_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][0]~13_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][0]~13 .lut_mask = 16'h000C; +defparam \ula_|zx_keyboard_|keys[0][0]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~2 ( +// Equation(s): +// \ula_|zx_keyboard_|shifted~2_combout = (!\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|zx_keyboard_|extended~q & \ula_|zx_keyboard_|keys[0][0]~13_combout )) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|zx_keyboard_|extended~q ), + .datad(\ula_|zx_keyboard_|keys[0][0]~13_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|shifted~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|shifted~2 .lut_mask = 16'h0300; +defparam \ula_|zx_keyboard_|shifted~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~14 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][1]~14_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [4] $ (\ula_|ps2_keyboard_|shiftreg [2])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][1]~14_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][1]~14 .lut_mask = 16'h1020; +defparam \ula_|zx_keyboard_|keys[0][1]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~15 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][1]~15_combout = (\ula_|zx_keyboard_|keys[0][1]~14_combout & ((\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [1])) # (!\ula_|ps2_keyboard_|shiftreg [4] & +// (\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [1])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|zx_keyboard_|keys[0][1]~14_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][1]~15 .lut_mask = 16'h0840; +defparam \ula_|zx_keyboard_|keys[0][1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr17~0 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr17~0_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [3]))) # (!\ula_|ps2_keyboard_|shiftreg [1] & +// (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [3]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr17~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr17~0 .lut_mask = 16'h4002; +defparam \ula_|zx_keyboard_|WideOr17~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~5 ( +// Equation(s): +// \ula_|zx_keyboard_|shifted~5_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|zx_keyboard_|WideOr17~0_combout )) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|zx_keyboard_|WideOr17~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|shifted~5_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|shifted~5 .lut_mask = 16'h2020; +defparam \ula_|zx_keyboard_|shifted~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~4 ( +// Equation(s): +// \ula_|zx_keyboard_|shifted~4_combout = (\ula_|zx_keyboard_|shifted~5_combout & ((\ula_|zx_keyboard_|shifted~2_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|shifted~2_combout & ((\ula_|zx_keyboard_|shifted~q ))))) # +// (!\ula_|zx_keyboard_|shifted~5_combout & (((\ula_|zx_keyboard_|shifted~q )))) + + .dataa(\ula_|zx_keyboard_|shifted~5_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|shifted~q ), + .datad(\ula_|zx_keyboard_|shifted~2_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|shifted~4_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|shifted~4 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|shifted~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y10_N27 +dffeas \ula_|zx_keyboard_|shifted ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|shifted~4_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|shifted~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|shifted .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|shifted .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~12 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][1]~12_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & !\ula_|ps2_keyboard_|shiftreg [4])) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|shifted~q ), + .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][1]~12_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][1]~12 .lut_mask = 16'hCCCF; +defparam \ula_|zx_keyboard_|keys[0][1]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~16 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][1]~16_combout = (\ula_|zx_keyboard_|shifted~2_combout & ((\ula_|zx_keyboard_|keys[0][1]~15_combout & ((!\ula_|zx_keyboard_|keys[0][1]~12_combout ))) # (!\ula_|zx_keyboard_|keys[0][1]~15_combout & +// (\ula_|zx_keyboard_|keys[0][1]~q )))) # (!\ula_|zx_keyboard_|shifted~2_combout & (((\ula_|zx_keyboard_|keys[0][1]~q )))) + + .dataa(\ula_|zx_keyboard_|shifted~2_combout ), + .datab(\ula_|zx_keyboard_|keys[0][1]~15_combout ), + .datac(\ula_|zx_keyboard_|keys[0][1]~q ), + .datad(\ula_|zx_keyboard_|keys[0][1]~12_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][1]~16_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][1]~16 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[0][1]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y10_N21 +dffeas \ula_|zx_keyboard_|keys[0][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[0][1]~16_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[0][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[0][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N0 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[8]~8 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[8]~8_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [8]))) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [8]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[8]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[8]~8 .lut_mask = 16'hDD88; +defparam \z80_|address_pins_|DFFE_apin_latch[8]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y10_N1 +dffeas \z80_|address_pins_|DFFE_apin_latch[8] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[8]~8_combout ), + .asdata(\z80_|address_latch_|Q [8]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [8]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[8] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N24 +cycloneive_lcell_comb \z80_|address_pins_|abus[8]~18 ( +// Equation(s): +// \z80_|address_pins_|abus[8]~18_combout = (\z80_|address_pins_|DFFE_apin_latch [8]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [8]), + .cin(gnd), + .combout(\z80_|address_pins_|abus[8]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[8]~18 .lut_mask = 16'hFF0F; +defparam \z80_|address_pins_|abus[8]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N2 +cycloneive_lcell_comb \D[1]~26 ( +// Equation(s): +// \D[1]~26_combout = (\ula_|zx_keyboard_|keys[1][1]~q & (\z80_|address_pins_|abus[9]~17_combout & ((\z80_|address_pins_|abus[8]~18_combout ) # (!\ula_|zx_keyboard_|keys[0][1]~q )))) # (!\ula_|zx_keyboard_|keys[1][1]~q & +// (((\z80_|address_pins_|abus[8]~18_combout ) # (!\ula_|zx_keyboard_|keys[0][1]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[1][1]~q ), + .datab(\z80_|address_pins_|abus[9]~17_combout ), + .datac(\ula_|zx_keyboard_|keys[0][1]~q ), + .datad(\z80_|address_pins_|abus[8]~18_combout ), + .cin(gnd), + .combout(\D[1]~26_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~26 .lut_mask = 16'hDD0D; +defparam \D[1]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N4 +cycloneive_lcell_comb \D[1]~27 ( +// Equation(s): +// \D[1]~27_combout = (\ula_|zx_keyboard_|key_row~0_combout & (\D[1]~26_combout & ((\z80_|address_pins_|abus[11]~19_combout ) # (!\ula_|zx_keyboard_|keys[3][1]~q )))) + + .dataa(\ula_|zx_keyboard_|key_row~0_combout ), + .datab(\ula_|zx_keyboard_|keys[3][1]~q ), + .datac(\z80_|address_pins_|abus[11]~19_combout ), + .datad(\D[1]~26_combout ), + .cin(gnd), + .combout(\D[1]~27_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~27 .lut_mask = 16'hA200; +defparam \D[1]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N16 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[12]~12 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[12]~12_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [12]))) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [12]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[12]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[12]~12 .lut_mask = 16'hDD88; +defparam \z80_|address_pins_|DFFE_apin_latch[12]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y13_N17 +dffeas \z80_|address_pins_|DFFE_apin_latch[12] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[12]~12_combout ), + .asdata(\z80_|address_latch_|Q [12]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [12]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[12] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N28 +cycloneive_lcell_comb \z80_|address_pins_|abus[12]~21 ( +// Equation(s): +// \z80_|address_pins_|abus[12]~21_combout = (\z80_|address_pins_|DFFE_apin_latch [12]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [12]), + .cin(gnd), + .combout(\z80_|address_pins_|abus[12]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[12]~21 .lut_mask = 16'hFF0F; +defparam \z80_|address_pins_|abus[12]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N2 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout = \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout $ (\z80_|address_latch_|Q [13]) + + .dataa(gnd), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), + .datac(gnd), + .datad(\z80_|address_latch_|Q [13]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out .lut_mask = 16'h33CC; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N6 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[13]~13 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[13]~13_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [13])) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|abusz [13]), + .datac(gnd), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[13]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[13]~13 .lut_mask = 16'hEE44; +defparam \z80_|address_pins_|DFFE_apin_latch[13]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y13_N7 +dffeas \z80_|address_pins_|DFFE_apin_latch[13] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[13]~13_combout ), + .asdata(\z80_|address_latch_|Q [13]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [13]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[13] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N6 +cycloneive_lcell_comb \z80_|address_pins_|abus[13]~20 ( +// Equation(s): +// \z80_|address_pins_|abus[13]~20_combout = (\z80_|address_pins_|DFFE_apin_latch [13]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(gnd), + .datad(\z80_|address_pins_|DFFE_apin_latch [13]), + .cin(gnd), + .combout(\z80_|address_pins_|abus[13]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[13]~20 .lut_mask = 16'hFF33; +defparam \z80_|address_pins_|abus[13]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~36 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][1]~36_combout = (!\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [5])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][1]~36_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1]~36 .lut_mask = 16'h0005; +defparam \ula_|zx_keyboard_|keys[5][1]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~34 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][1]~34_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|zx_keyboard_|extended~q & \ula_|zx_keyboard_|keys[0][0]~13_combout )) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|zx_keyboard_|extended~q ), + .datad(\ula_|zx_keyboard_|keys[0][0]~13_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][1]~34_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1]~34 .lut_mask = 16'h0300; +defparam \ula_|zx_keyboard_|keys[5][1]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~35 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][1]~35_combout = (\ula_|zx_keyboard_|keys[5][1]~34_combout & (\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [2])) + + .dataa(\ula_|zx_keyboard_|keys[5][1]~34_combout ), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][1]~35_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1]~35 .lut_mask = 16'hA000; +defparam \ula_|zx_keyboard_|keys[5][1]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~33 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][1]~33_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [3] & \ula_|zx_keyboard_|shifted~q )) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|zx_keyboard_|shifted~q ), + .datac(gnd), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][1]~33_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1]~33 .lut_mask = 16'hFF88; +defparam \ula_|zx_keyboard_|keys[5][1]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~37 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][1]~37_combout = (\ula_|zx_keyboard_|keys[5][1]~36_combout & ((\ula_|zx_keyboard_|keys[5][1]~35_combout & ((!\ula_|zx_keyboard_|keys[5][1]~33_combout ))) # (!\ula_|zx_keyboard_|keys[5][1]~35_combout & +// (\ula_|zx_keyboard_|keys[5][1]~q )))) # (!\ula_|zx_keyboard_|keys[5][1]~36_combout & (((\ula_|zx_keyboard_|keys[5][1]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][1]~36_combout ), + .datab(\ula_|zx_keyboard_|keys[5][1]~35_combout ), + .datac(\ula_|zx_keyboard_|keys[5][1]~q ), + .datad(\ula_|zx_keyboard_|keys[5][1]~33_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][1]~37_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1]~37 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[5][1]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y10_N23 +dffeas \ula_|zx_keyboard_|keys[5][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[5][1]~37_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[5][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[5][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][1]~29 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][1]~29_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [2]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][1]~29_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][1]~29 .lut_mask = 16'h0F00; +defparam \ula_|zx_keyboard_|keys[4][1]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~30 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][2]~30_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [5])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][2]~30_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2]~30 .lut_mask = 16'h0202; +defparam \ula_|zx_keyboard_|keys[7][2]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~31 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][2]~31_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[7][1]~21_combout & (\ula_|zx_keyboard_|keys[7][2]~30_combout & \ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|zx_keyboard_|keys[7][1]~21_combout ), + .datac(\ula_|zx_keyboard_|keys[7][2]~30_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][2]~31_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][2]~31 .lut_mask = 16'h4000; +defparam \ula_|zx_keyboard_|keys[5][2]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][1]~32 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][1]~32_combout = (\ula_|zx_keyboard_|keys[4][1]~29_combout & ((\ula_|zx_keyboard_|keys[5][2]~31_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[5][2]~31_combout & ((\ula_|zx_keyboard_|keys[4][1]~q +// ))))) # (!\ula_|zx_keyboard_|keys[4][1]~29_combout & (((\ula_|zx_keyboard_|keys[4][1]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[4][1]~29_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[4][1]~q ), + .datad(\ula_|zx_keyboard_|keys[5][2]~31_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][1]~32_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][1]~32 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[4][1]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y10_N25 +dffeas \ula_|zx_keyboard_|keys[4][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[4][1]~32_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[4][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[4][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N28 +cycloneive_lcell_comb \D[1]~28 ( +// Equation(s): +// \D[1]~28_combout = (\z80_|address_pins_|abus[12]~21_combout & ((\z80_|address_pins_|abus[13]~20_combout ) # ((!\ula_|zx_keyboard_|keys[5][1]~q )))) # (!\z80_|address_pins_|abus[12]~21_combout & (!\ula_|zx_keyboard_|keys[4][1]~q & +// ((\z80_|address_pins_|abus[13]~20_combout ) # (!\ula_|zx_keyboard_|keys[5][1]~q )))) + + .dataa(\z80_|address_pins_|abus[12]~21_combout ), + .datab(\z80_|address_pins_|abus[13]~20_combout ), + .datac(\ula_|zx_keyboard_|keys[5][1]~q ), + .datad(\ula_|zx_keyboard_|keys[4][1]~q ), + .cin(gnd), + .combout(\D[1]~28_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~28 .lut_mask = 16'h8ACF; +defparam \D[1]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N6 +cycloneive_lcell_comb \z80_|address_pins_|abus[0]~16 ( +// Equation(s): +// \z80_|address_pins_|abus[0]~16_combout = (\z80_|address_pins_|DFFE_apin_latch [0]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [0]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_pins_|abus[0]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[0]~16 .lut_mask = 16'hCFCF; +defparam \z80_|address_pins_|abus[0]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N18 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[14]~14 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[14]~14_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|address [14])) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [14]))) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [14]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[14]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[14]~14 .lut_mask = 16'hDD88; +defparam \z80_|address_pins_|DFFE_apin_latch[14]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y13_N19 +dffeas \z80_|address_pins_|DFFE_apin_latch[14] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[14]~14_combout ), + .asdata(\z80_|address_latch_|Q [14]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [14]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[14] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N20 +cycloneive_lcell_comb \z80_|address_pins_|abus[14]~23 ( +// Equation(s): +// \z80_|address_pins_|abus[14]~23_combout = (\z80_|address_pins_|DFFE_apin_latch [14]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [14]), + .cin(gnd), + .combout(\z80_|address_pins_|abus[14]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[14]~23 .lut_mask = 16'hFF0F; +defparam \z80_|address_pins_|abus[14]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~40 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][1]~40_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [1])) # (!\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [4] & +// \ula_|ps2_keyboard_|shiftreg [1])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][1]~40_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1]~40 .lut_mask = 16'h1188; +defparam \ula_|zx_keyboard_|keys[6][1]~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~41 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][1]~41_combout = (\ula_|zx_keyboard_|keys[6][1]~40_combout & (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [2] $ (\ula_|ps2_keyboard_|shiftreg [3])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|zx_keyboard_|keys[6][1]~40_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][1]~41_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1]~41 .lut_mask = 16'h6000; +defparam \ula_|zx_keyboard_|keys[6][1]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~39 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][1]~39_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|zx_keyboard_|keys[0][0]~13_combout & !\ula_|zx_keyboard_|extended~q ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|zx_keyboard_|keys[0][0]~13_combout ), + .datad(\ula_|zx_keyboard_|extended~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][1]~39_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1]~39 .lut_mask = 16'h0020; +defparam \ula_|zx_keyboard_|keys[6][1]~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~38 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][1]~38_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [2])) + + .dataa(\ula_|zx_keyboard_|shifted~q ), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][1]~38_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1]~38 .lut_mask = 16'hFFA0; +defparam \ula_|zx_keyboard_|keys[6][1]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~42 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][1]~42_combout = (\ula_|zx_keyboard_|keys[6][1]~41_combout & ((\ula_|zx_keyboard_|keys[6][1]~39_combout & ((!\ula_|zx_keyboard_|keys[6][1]~38_combout ))) # (!\ula_|zx_keyboard_|keys[6][1]~39_combout & +// (\ula_|zx_keyboard_|keys[6][1]~q )))) # (!\ula_|zx_keyboard_|keys[6][1]~41_combout & (((\ula_|zx_keyboard_|keys[6][1]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[6][1]~41_combout ), + .datab(\ula_|zx_keyboard_|keys[6][1]~39_combout ), + .datac(\ula_|zx_keyboard_|keys[6][1]~q ), + .datad(\ula_|zx_keyboard_|keys[6][1]~38_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][1]~42_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1]~42 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[6][1]~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y9_N23 +dffeas \ula_|zx_keyboard_|keys[6][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[6][1]~42_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[6][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[6][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~4 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~4_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [2])) # (!\ula_|ps2_keyboard_|shiftreg [1] & +// (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [2])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~4_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~4 .lut_mask = 16'h0402; +defparam \ula_|zx_keyboard_|WideOr16~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~2 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~2_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [1])) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~2 .lut_mask = 16'h000C; +defparam \ula_|zx_keyboard_|WideOr16~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~7 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~7_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|WideOr16~4_combout )) # (!\ula_|ps2_keyboard_|shiftreg [6] & (((\ula_|zx_keyboard_|WideOr16~2_combout & !\ula_|ps2_keyboard_|shiftreg [2])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|zx_keyboard_|WideOr16~4_combout ), + .datac(\ula_|zx_keyboard_|WideOr16~2_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~7_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~7 .lut_mask = 16'h88D8; +defparam \ula_|zx_keyboard_|WideOr16~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~5 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~5_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [1] & ((!\ula_|ps2_keyboard_|shiftreg [2])))) # (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & +// ((\ula_|ps2_keyboard_|shiftreg [1]) # (\ula_|ps2_keyboard_|shiftreg [2])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~5_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~5 .lut_mask = 16'h3064; +defparam \ula_|zx_keyboard_|WideOr16~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~6 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~6_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|zx_keyboard_|WideOr16~7_combout )) # (!\ula_|ps2_keyboard_|shiftreg [4] & (((\ula_|ps2_keyboard_|shiftreg [6] & \ula_|zx_keyboard_|WideOr16~5_combout )))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|zx_keyboard_|WideOr16~7_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(\ula_|zx_keyboard_|WideOr16~5_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~6_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~6 .lut_mask = 16'hD888; +defparam \ula_|zx_keyboard_|WideOr16~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~43 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][1]~43_combout = (!\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [7] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|scan_code_ready~q ))) + + .dataa(\ula_|zx_keyboard_|extended~q ), + .datab(\ula_|ps2_keyboard_|shiftreg [7]), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|ps2_keyboard_|scan_code_ready~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][1]~43_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][1]~43 .lut_mask = 16'h0100; +defparam \ula_|zx_keyboard_|keys[7][1]~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~44 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][1]~44_combout = (\ula_|zx_keyboard_|WideOr16~6_combout & ((\ula_|zx_keyboard_|keys[7][1]~43_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[7][1]~43_combout & (\ula_|zx_keyboard_|keys[7][1]~q )))) +// # (!\ula_|zx_keyboard_|WideOr16~6_combout & (((\ula_|zx_keyboard_|keys[7][1]~q )))) + + .dataa(\ula_|zx_keyboard_|WideOr16~6_combout ), + .datab(\ula_|zx_keyboard_|keys[7][1]~43_combout ), + .datac(\ula_|zx_keyboard_|keys[7][1]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][1]~44_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][1]~44 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[7][1]~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y10_N25 +dffeas \ula_|zx_keyboard_|keys[7][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[7][1]~44_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[7][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[7][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N10 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[15]~15 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[15]~15_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address[15]~1_combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [15])) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|abusz [15]), + .datac(gnd), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|address[15]~1_combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[15]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[15]~15 .lut_mask = 16'hEE44; +defparam \z80_|address_pins_|DFFE_apin_latch[15]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y13_N11 +dffeas \z80_|address_pins_|DFFE_apin_latch[15] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[15]~15_combout ), + .asdata(\z80_|address_latch_|Q [15]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [15]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[15] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N8 +cycloneive_lcell_comb \z80_|address_pins_|abus[15]~22 ( +// Equation(s): +// \z80_|address_pins_|abus[15]~22_combout = (\z80_|address_pins_|DFFE_apin_latch [15]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [15]), + .cin(gnd), + .combout(\z80_|address_pins_|abus[15]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[15]~22 .lut_mask = 16'hFF0F; +defparam \z80_|address_pins_|abus[15]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N16 +cycloneive_lcell_comb \D[1]~29 ( +// Equation(s): +// \D[1]~29_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\z80_|address_pins_|abus[15]~22_combout ) # (!\ula_|zx_keyboard_|keys[7][1]~q )))) # (!\z80_|address_pins_|abus[14]~23_combout & (!\ula_|zx_keyboard_|keys[6][1]~q & +// ((\z80_|address_pins_|abus[15]~22_combout ) # (!\ula_|zx_keyboard_|keys[7][1]~q )))) + + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\ula_|zx_keyboard_|keys[6][1]~q ), + .datac(\ula_|zx_keyboard_|keys[7][1]~q ), + .datad(\z80_|address_pins_|abus[15]~22_combout ), + .cin(gnd), + .combout(\D[1]~29_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~29 .lut_mask = 16'hBB0B; +defparam \D[1]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N26 +cycloneive_lcell_comb \D[1]~30 ( +// Equation(s): +// \D[1]~30_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[1]~27_combout & (\D[1]~28_combout & \D[1]~29_combout ))) + + .dataa(\D[1]~27_combout ), + .datab(\D[1]~28_combout ), + .datac(\z80_|address_pins_|abus[0]~16_combout ), + .datad(\D[1]~29_combout ), + .cin(gnd), + .combout(\D[1]~30_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~30 .lut_mask = 16'hF8F0; +defparam \D[1]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N20 +cycloneive_lcell_comb \ExtRamWE~0 ( +// Equation(s): +// \ExtRamWE~0_combout = (!\z80_|memory_ifc_|nIORQ_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (!\z80_|memory_ifc_|nRD_out~2_combout & \z80_|memory_ifc_|nWR_out~0_combout ))) + + .dataa(\z80_|memory_ifc_|nIORQ_out~0_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|memory_ifc_|nRD_out~2_combout ), + .datad(\z80_|memory_ifc_|nWR_out~0_combout ), + .cin(gnd), + .combout(\ExtRamWE~0_combout ), + .cout()); +// synopsys translate_off +defparam \ExtRamWE~0 .lut_mask = 16'h0400; +defparam \ExtRamWE~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N0 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2] = (!\z80_|address_pins_|abus[14]~23_combout & (\ExtRamWE~0_combout & (\z80_|address_pins_|abus[15]~22_combout & \z80_|address_pins_|abus[13]~20_combout ))) + + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\ExtRamWE~0_combout ), + .datac(\z80_|address_pins_|abus[15]~22_combout ), + .datad(\z80_|address_pins_|abus[13]~20_combout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] .lut_mask = 16'h4000; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N10 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout = (!\z80_|address_pins_|DFFE_apin_latch [14] & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \z80_|address_pins_|DFFE_apin_latch [13])) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [14]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [13]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 .lut_mask = 16'h3000; +defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N6 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[1]~1 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[1]~1_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [1])) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|abusz [1]), + .datac(gnd), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[1]~1 .lut_mask = 16'hEE44; +defparam \z80_|address_pins_|DFFE_apin_latch[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y11_N7 +dffeas \z80_|address_pins_|DFFE_apin_latch[1] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[1]~1_combout ), + .asdata(\z80_|address_latch_|Q [1]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[1] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N10 +cycloneive_lcell_comb \z80_|address_pins_|abus[1]~25 ( +// Equation(s): +// \z80_|address_pins_|abus[1]~25_combout = (\z80_|address_pins_|DFFE_apin_latch [1]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [1]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_pins_|abus[1]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[1]~25 .lut_mask = 16'hCFCF; +defparam \z80_|address_pins_|abus[1]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N12 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[2]~2 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[2]~2_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [2]))) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [2]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[2]~2 .lut_mask = 16'hDD88; +defparam \z80_|address_pins_|DFFE_apin_latch[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y11_N13 +dffeas \z80_|address_pins_|DFFE_apin_latch[2] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[2]~2_combout ), + .asdata(\z80_|address_latch_|Q [2]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[2] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N16 +cycloneive_lcell_comb \z80_|address_pins_|abus[2]~26 ( +// Equation(s): +// \z80_|address_pins_|abus[2]~26_combout = (\z80_|address_pins_|DFFE_apin_latch [2]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [2]), + .cin(gnd), + .combout(\z80_|address_pins_|abus[2]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[2]~26 .lut_mask = 16'hFF0F; +defparam \z80_|address_pins_|abus[2]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N28 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[3]~3 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[3]~3_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [3])) + + .dataa(\z80_|address_latch_|abusz [3]), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_apin_mux~2_combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[3]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[3]~3 .lut_mask = 16'hCCAA; +defparam \z80_|address_pins_|DFFE_apin_latch[3]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y11_N29 +dffeas \z80_|address_pins_|DFFE_apin_latch[3] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[3]~3_combout ), + .asdata(\z80_|address_latch_|Q [3]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[3] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N0 +cycloneive_lcell_comb \z80_|address_pins_|abus[3]~27 ( +// Equation(s): +// \z80_|address_pins_|abus[3]~27_combout = (\z80_|address_pins_|DFFE_apin_latch [3]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [3]), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_pins_|abus[3]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[3]~27 .lut_mask = 16'hAFAF; +defparam \z80_|address_pins_|abus[3]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N16 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[4]~4 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[4]~4_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [4]))) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [4]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[4]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[4]~4 .lut_mask = 16'hDD88; +defparam \z80_|address_pins_|DFFE_apin_latch[4]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y10_N17 +dffeas \z80_|address_pins_|DFFE_apin_latch[4] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[4]~4_combout ), + .asdata(\z80_|address_latch_|Q [4]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[4] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N6 +cycloneive_lcell_comb \z80_|address_pins_|abus[4]~28 ( +// Equation(s): +// \z80_|address_pins_|abus[4]~28_combout = (\z80_|address_pins_|DFFE_apin_latch [4]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [4]), + .cin(gnd), + .combout(\z80_|address_pins_|abus[4]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[4]~28 .lut_mask = 16'hFF0F; +defparam \z80_|address_pins_|abus[4]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N18 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[5]~5 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[5]~5_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [5]))) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [5]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[5]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[5]~5 .lut_mask = 16'hDD88; +defparam \z80_|address_pins_|DFFE_apin_latch[5]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y10_N19 +dffeas \z80_|address_pins_|DFFE_apin_latch[5] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[5]~5_combout ), + .asdata(\z80_|address_latch_|Q [5]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[5] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N30 +cycloneive_lcell_comb \z80_|address_pins_|abus[5]~29 ( +// Equation(s): +// \z80_|address_pins_|abus[5]~29_combout = (\z80_|address_pins_|DFFE_apin_latch [5]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [5]), + .cin(gnd), + .combout(\z80_|address_pins_|abus[5]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[5]~29 .lut_mask = 16'hFF0F; +defparam \z80_|address_pins_|abus[5]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N14 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[6]~6 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[6]~6_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|address [6])) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [6]))) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [6]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[6]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[6]~6 .lut_mask = 16'hDD88; +defparam \z80_|address_pins_|DFFE_apin_latch[6]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y10_N15 +dffeas \z80_|address_pins_|DFFE_apin_latch[6] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[6]~6_combout ), + .asdata(\z80_|address_latch_|Q [6]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[6] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N26 +cycloneive_lcell_comb \z80_|address_pins_|abus[6]~30 ( +// Equation(s): +// \z80_|address_pins_|abus[6]~30_combout = (\z80_|address_pins_|DFFE_apin_latch [6]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [6]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_pins_|abus[6]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[6]~30 .lut_mask = 16'hCFCF; +defparam \z80_|address_pins_|abus[6]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N20 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[7]~7 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[7]~7_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [7])) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|abusz [7]), + .datac(gnd), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[7]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[7]~7 .lut_mask = 16'hEE44; +defparam \z80_|address_pins_|DFFE_apin_latch[7]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y13_N21 +dffeas \z80_|address_pins_|DFFE_apin_latch[7] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[7]~7_combout ), + .asdata(\z80_|address_latch_|Q [7]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[7] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N24 +cycloneive_lcell_comb \z80_|address_pins_|abus[7]~31 ( +// Equation(s): +// \z80_|address_pins_|abus[7]~31_combout = (\z80_|address_pins_|DFFE_apin_latch [7]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_pins_|DFFE_apin_latch [7]), + .cin(gnd), + .combout(\z80_|address_pins_|abus[7]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[7]~31 .lut_mask = 16'hFF55; +defparam \z80_|address_pins_|abus[7]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N0 +cycloneive_lcell_comb \z80_|address_pins_|abus[10]~24 ( +// Equation(s): +// \z80_|address_pins_|abus[10]~24_combout = (\z80_|address_pins_|DFFE_apin_latch [10]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_pins_|DFFE_apin_latch [10]), + .cin(gnd), + .combout(\z80_|address_pins_|abus[10]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[10]~24 .lut_mask = 16'hFF55; +defparam \z80_|address_pins_|abus[10]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y12_N0 cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a9 ( .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), .portare(vcc), @@ -41359,7 +39084,7 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a9 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[1]~34_combout }), + .portadatain({\D[1]~32_combout }), .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , \z80_|address_pins_|abus[0]~16_combout }), @@ -41400,26 +39125,187 @@ defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 204 defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: LCCOMB_X32_Y14_N28 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0 ( +// Location: LCCOMB_X29_Y11_N4 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] ( // Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout )))) +// \ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2] = (!\z80_|address_pins_|abus[14]~23_combout & (\ExtRamWE~0_combout & (\z80_|address_pins_|abus[15]~22_combout & !\z80_|address_pins_|abus[13]~20_combout ))) - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ), + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\ExtRamWE~0_combout ), + .datac(\z80_|address_pins_|abus[15]~22_combout ), + .datad(\z80_|address_pins_|abus[13]~20_combout ), .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout ), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), .cout()); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0 .lut_mask = 16'hDC98; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0 .sum_lutc_input = "datac"; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] .lut_mask = 16'h0040; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X33_Y19_N0 +// Location: LCCOMB_X23_Y10_N0 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout = (!\z80_|address_pins_|DFFE_apin_latch [14] & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|address_pins_|DFFE_apin_latch [13])) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [14]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [13]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 .lut_mask = 16'h0030; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y10_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a1 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[1]~32_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N22 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout = \z80_|address_pins_|abus[13]~20_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_pins_|abus[13]~20_combout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder .lut_mask = 16'hFF00; +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y10_N23 +dffeas \ram1|altsyncram_component|auto_generated|address_reg_a[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram1|altsyncram_component|auto_generated|address_reg_a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true"; +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X23_Y10_N7 +dffeas \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ram1|altsyncram_component|auto_generated|address_reg_a [0]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true"; +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N24 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2] = (\z80_|address_pins_|abus[14]~23_combout & (\ExtRamWE~0_combout & (\z80_|address_pins_|abus[15]~22_combout & !\z80_|address_pins_|abus[13]~20_combout ))) + + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\ExtRamWE~0_combout ), + .datac(\z80_|address_pins_|abus[15]~22_combout ), + .datad(\z80_|address_pins_|abus[13]~20_combout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] .lut_mask = 16'h0080; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y10_N12 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout = (!\z80_|address_pins_|DFFE_apin_latch [13] & (\z80_|address_pins_|DFFE_apin_latch [14] & \z80_|resets_|SYNTHESIZED_WIRE_12~q )) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [13]), + .datac(\z80_|address_pins_|DFFE_apin_latch [14]), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 .lut_mask = 16'h3000; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y8_N0 cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a17 ( .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), .portare(vcc), @@ -41435,7 +39321,7 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a17 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[1]~34_combout }), + .portadatain({\D[1]~32_combout }), .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , \z80_|address_pins_|abus[0]~16_combout }), @@ -41476,7 +39362,98 @@ defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init1 = 20 defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: M9K_X33_Y20_N0 +// Location: FF_X23_Y14_N5 +dffeas \ram1|altsyncram_component|auto_generated|address_reg_a[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|address_pins_|abus[14]~23_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram1|altsyncram_component|auto_generated|address_reg_a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1] .is_wysiwyg = "true"; +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X23_Y14_N27 +dffeas \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ram1|altsyncram_component|auto_generated|address_reg_a [1]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] .is_wysiwyg = "true"; +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N8 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0 .lut_mask = 16'hFC22; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N18 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2] = (\z80_|address_pins_|abus[14]~23_combout & (\ExtRamWE~0_combout & (\z80_|address_pins_|abus[15]~22_combout & \z80_|address_pins_|abus[13]~20_combout ))) + + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\ExtRamWE~0_combout ), + .datac(\z80_|address_pins_|abus[15]~22_combout ), + .datad(\z80_|address_pins_|abus[13]~20_combout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] .lut_mask = 16'h8000; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y10_N30 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout = ((\z80_|address_pins_|DFFE_apin_latch [13] & \z80_|address_pins_|DFFE_apin_latch [14])) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [13]), + .datac(\z80_|address_pins_|DFFE_apin_latch [14]), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 .lut_mask = 16'hC0FF; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y7_N0 cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a25 ( .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), .portare(vcc), @@ -41492,7 +39469,7 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a25 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[1]~34_combout }), + .portadatain({\D[1]~32_combout }), .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , \z80_|address_pins_|abus[0]~16_combout }), @@ -41533,28 +39510,875 @@ defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init1 = 20 defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: LCCOMB_X32_Y14_N16 +// Location: LCCOMB_X31_Y10_N6 cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1 ( // Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout & -// ((\ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout )))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout )) +// \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout = (\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout & (((\ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout & +// (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]))) - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ), .datab(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout ), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), .datad(\ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ), .cin(gnd), .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ), .cout()); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1 .lut_mask = 16'hEC64; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1 .lut_mask = 16'hEC2C; defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X33_Y24_N0 +// Location: M9K_X33_Y2_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a1 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h35C65240B61076066A23CE4CFC5E76063A1C2AE07DF555007338BDC080EA0C23082C891C76A4845096304A0D8502080C1198911998821D09C29CA830C337499236E0548D65FF9125A765F0220F6EB9D1B318244CC6CA2CBC9CEC6979C14EB28DE2E0440C6CBD61341FC178649A852D4A2A0627C688D905B882524E191E7951EAEF30312A73337CBAD4838F42A3293859CD169240D8E652F6D72D8D19D56DD7675939FC47C933E1B0AEF12A484454C247B00A6BEC5402AA08B5106E3065602454C80CEC08A7F5F85CE65326632B4C4F3920019A35AE2AEB321131046EE45B81D4EFD5995634050D4CFEC166B032B6415553AF0358304080D9DD0A2E5948593830; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h376E511217E00B624A46BA2E4CC10B729C326F710F24CFE78C5E63F3024B17CC5E1380C938A0A16C9B696272DE7A2948BE8AFE81310146B8AAE5E549FA27EFBE27929938B8E10530250877A4998D0DF0004852125C20CA8D4279881E41208B14198817644F293AC1946061117122A39D8841818C1389D51BDAC549181902516571163594CEC5863F0F56625E221D6B8180848C6B2BE24AA0AEEE5D187201CAAE6AA394A8644314895565192AE415630A42894D6EF21343903B348EED8642F2310644C9567C0BF9911B870B989C59330089AA4C8065AB1B11132213EE0FD830817DE6C2ED45D76325CA2A8E198859334553AB02945CAB1F17C142288008073004; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h20721F982534A8179F13E2C6328CDE7D2A73087D3A9314419022103DFF7677769FE2D1F27443253D58403577C801AE23371F00290A17E1C4A40258BFD204230EE9969472A81B83113144528F831AA6C3221E137C1E9C670E26809A894013828D9E2DBCBF62498A769893D7218899245CD18AE49F0146517422EE475D520029ED39BCEF6BF4D23532957455F1C80115524179D59C4C4534DF7296991146CE24508366123AA809AB30B47977571C5D70397A93C723106D0A2C254714359DC7C9E13AE624C94932927924D20024CD638A05C8620023319662D80E05805625BC4A4006C78011F78D8B82E59F0CD4B32D6801669BE3EB0B96960DFF152005EC7C16CB; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h9C8CA06AA05B63C89A59A3E4E80807B27A70B0006624C4AC4A0595CCD8CA20824CA272352720BCD900A6D79BFD9D0595EC0D044ABC8CC28E9AE946E3D2000A4EFA4F91915C6AC9D8570C292F10848189906127BCBE06FFE92DAFB4AAFB240D88DDBB7B207EFA1709B05E1C4801BD45625A36BB62220506E171891964A31BED2215408676F600F490FAA59B488C7998CC8CCC28922AC62644EEBB432EEECB51B16CDEE7468681D6C31E4991CA3736E9ACB7531EC6D8BBCD453718101EA25D79278C6AC955A8A6140421573E413CF5A80AA1436D8B4C31A2AB26D2A61CE834248BAD5751BD429B4F61318427560CE39D49299002165212181064E24FF0093B997B; +// synopsys translate_on + +// Location: M9K_X22_Y2_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a9 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h420000004200000000000000000080000000000000000000000000000030004480000000424202423E1E3E02304C3C0C3C7E7E40403E427E3402421824347C1C0400280000003C3406303220344C403C0400100010100000005062742400000091991809FB3BD9084A1241F5015988B3C506031934089E0E1FA8043DDAF2CC07D94A6F2B1D133C211222B22C787D430E45D4C53282288077DFC0F704AAD55127A2BEAEA114958D2817AB1213183A4E1A15E3690A08A33B429284A202011A1243D49CACA1C0A441405A720D21A0921294045F746229E287B95E956AA3DE0CA3B7A019C8039C4DDA6BC99371248CC6008A54CB84503442C4F91309238ECB252072; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h81F3167814687CBD683E54D44555E6C95B5F2A72C0C193C6110C0221A448D0C9A0D8E36A84D5C61285128845215F8F8821C308E368283D8E2B42989C04A8B51354E09A38775020189010680840800297C31282442326D008D1F2351A89FFD7C16087F8B130F04418C0A1C082FC005843F5B42CADD9455ADBD328C13219110DE100D988737BBB44C414210118C673B0C1BDF76C499226F78FF41A0AF7AFD3308AAA0AAA22B1C70003F542A66FD1F1CF9D4578315F8C1C6FEC3EDB9B322CB204821A94A248414CE030020F207BF040A06A3DF993DEA3823423F405294A52014565100E0A7211342DF02958046899EEBE6E491299A09312778193FEBD7FFABA8000; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h2C05EF54A3C0F7F5F017E03F5800377CCF6E493C84E8F56441831087370A084801DEC1A54696B9912E8B0705C8587D4F7D36C8638947A620554CC77819B55B7A12D552A8A0496EFE3AAC6F34739A94E798101823148D811212E9A349CC219049527CCD419525AD29AB7D372C0B56AA0A065F8BDC905346478059EC82801920687FF29C990C9E66273CC78041192D03081CC62A8A0D8CB4D9CF2F2558131A78B8A807C3A1110211AFCA2A142F0BA928156D142250438143D339E4E2079F298493C08C4847914664518E27EF7EB9C870A226AFC35BEDB651840466400D4B3C0F877740114D6B08228BCC693FB12CECCCD2461586069445ACFC910B1241434622B6; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h5FFE6AD3343986C4103935236B6E6E11B940EF46A8FC06E6872A6929D50DCDB75621E625522D34519BF2C353F8AA030B9109C2F9686AD3AF57AF3016D9160354C0BED5FBD379F904A41BAFB6BE4EE9F208058229DD0C354F034A6C4D8B6C16A29F0120108829220B230F44550832C1022530CC13C4C30D8254ECA5200A1941266EE48A1CA6430860DE613153615CAF4C8D191004CE9C6105D8C6795B6484467D21D9DC46029B8376E97F2C7BF8C3A218EE79DDBCF886B2BBDE702F71B38AEC6914E5DCCAFE50CC13922A5B149C598A621F80C24D215291228844E7F33F9763C6639303AE5376F664C7125632C1A280CECD5740C77849D937472B202579964F60; +// synopsys translate_on + +// Location: CLKCTRL_G15 +cycloneive_clkctrl \CLOCK_50~inputclkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\CLOCK_50~input_o }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\CLOCK_50~inputclkctrl_outclk )); +// synopsys translate_off +defparam \CLOCK_50~inputclkctrl .clock_type = "global clock"; +defparam \CLOCK_50~inputclkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N4 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout = \z80_|address_pins_|abus[13]~20_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_pins_|abus[13]~20_combout ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder .lut_mask = 16'hFF00; +defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y10_N5 +dffeas \ram0|altsyncram_component|auto_generated|address_reg_a[0] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram0|altsyncram_component|auto_generated|address_reg_a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true"; +defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X23_Y10_N15 +dffeas \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(gnd), + .asdata(\ram0|altsyncram_component|auto_generated|address_reg_a [0]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true"; +defparam \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N14 +cycloneive_lcell_comb \Selector3~0 ( +// Equation(s): +// \Selector3~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [14] & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))) # (!\z80_|address_pins_|DFFE_apin_latch [14] & +// (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0])))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\z80_|address_pins_|DFFE_apin_latch [14]), + .cin(gnd), + .combout(\Selector3~0_combout ), + .cout()); +// synopsys translate_off +defparam \Selector3~0 .lut_mask = 16'hF0B8; +defparam \Selector3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N22 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout = (\z80_|address_pins_|abus[14]~23_combout & (\ExtRamWE~0_combout & (!\z80_|address_pins_|abus[15]~22_combout & \z80_|address_pins_|abus[13]~20_combout ))) + + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\ExtRamWE~0_combout ), + .datac(\z80_|address_pins_|abus[15]~22_combout ), + .datad(\z80_|address_pins_|abus[13]~20_combout ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0 .lut_mask = 16'h0800; +defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y31_N14 +cycloneive_lcell_comb \~GND ( +// Equation(s): +// \~GND~combout = GND + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\~GND~combout ), + .cout()); +// synopsys translate_off +defparam \~GND .lut_mask = 16'h0000; +defparam \~GND .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y30_N24 +cycloneive_lcell_comb \ula_|video_|vram_address[0]~feeder ( +// Equation(s): +// \ula_|video_|vram_address[0]~feeder_combout = \ula_|video_|vga_hc [4] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|vga_hc [4]), + .cin(gnd), + .combout(\ula_|video_|vram_address[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address[0]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|vram_address[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y31_N26 +cycloneive_lcell_comb \ula_|video_|vram_address~0 ( +// Equation(s): +// \ula_|video_|vram_address~0_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [1] $ (\ula_|video_|vga_hc [2])))) + + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|vga_hc [3]), + .datac(\ula_|video_|vga_hc [2]), + .datad(\ula_|video_|vga_hc [0]), + .cin(gnd), + .combout(\ula_|video_|vram_address~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address~0 .lut_mask = 16'h0048; +defparam \ula_|video_|vram_address~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y30_N25 +dffeas \ula_|video_|vram_address[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vram_address[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[0] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y30_N22 +cycloneive_lcell_comb \ula_|video_|vram_address[1]~feeder ( +// Equation(s): +// \ula_|video_|vram_address[1]~feeder_combout = \ula_|video_|vga_hc [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|vga_hc [5]), + .cin(gnd), + .combout(\ula_|video_|vram_address[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address[1]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|vram_address[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y30_N23 +dffeas \ula_|video_|vram_address[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vram_address[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[1] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y30_N20 +cycloneive_lcell_comb \ula_|video_|vram_address[2]~4 ( +// Equation(s): +// \ula_|video_|vram_address[2]~4_combout = !\ula_|video_|vga_hc [6] + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|video_|vga_hc [6]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|video_|vram_address[2]~4_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address[2]~4 .lut_mask = 16'h0F0F; +defparam \ula_|video_|vram_address[2]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y30_N21 +dffeas \ula_|video_|vram_address[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vram_address[2]~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[2] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y30_N30 +cycloneive_lcell_comb \ula_|video_|Add3~0 ( +// Equation(s): +// \ula_|video_|Add3~0_combout = \ula_|video_|vga_hc [6] $ (\ula_|video_|vga_hc [7]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|video_|vga_hc [6]), + .datad(\ula_|video_|vga_hc [7]), + .cin(gnd), + .combout(\ula_|video_|Add3~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Add3~0 .lut_mask = 16'h0FF0; +defparam \ula_|video_|Add3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y30_N31 +dffeas \ula_|video_|vram_address[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Add3~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[3] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y30_N16 +cycloneive_lcell_comb \ula_|video_|Add3~1 ( +// Equation(s): +// \ula_|video_|Add3~1_combout = \ula_|video_|vga_hc [8] $ (((!\ula_|video_|vga_hc [7]) # (!\ula_|video_|vga_hc [6]))) + + .dataa(\ula_|video_|vga_hc [8]), + .datab(gnd), + .datac(\ula_|video_|vga_hc [6]), + .datad(\ula_|video_|vga_hc [7]), + .cin(gnd), + .combout(\ula_|video_|Add3~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Add3~1 .lut_mask = 16'hA555; +defparam \ula_|video_|Add3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y30_N17 +dffeas \ula_|video_|vram_address[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Add3~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[4] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y30_N10 +cycloneive_lcell_comb \ula_|video_|Add4~0 ( +// Equation(s): +// \ula_|video_|Add4~0_combout = (\ula_|video_|vga_vc [0] & (\ula_|video_|vga_vc [1] $ (VCC))) # (!\ula_|video_|vga_vc [0] & (\ula_|video_|vga_vc [1] & VCC)) +// \ula_|video_|Add4~1 = CARRY((\ula_|video_|vga_vc [0] & \ula_|video_|vga_vc [1])) + + .dataa(\ula_|video_|vga_vc [0]), + .datab(\ula_|video_|vga_vc [1]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\ula_|video_|Add4~0_combout ), + .cout(\ula_|video_|Add4~1 )); +// synopsys translate_off +defparam \ula_|video_|Add4~0 .lut_mask = 16'h6688; +defparam \ula_|video_|Add4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y30_N12 +cycloneive_lcell_comb \ula_|video_|Add4~2 ( +// Equation(s): +// \ula_|video_|Add4~2_combout = (\ula_|video_|vga_vc [2] & (\ula_|video_|Add4~1 & VCC)) # (!\ula_|video_|vga_vc [2] & (!\ula_|video_|Add4~1 )) +// \ula_|video_|Add4~3 = CARRY((!\ula_|video_|vga_vc [2] & !\ula_|video_|Add4~1 )) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [2]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~1 ), + .combout(\ula_|video_|Add4~2_combout ), + .cout(\ula_|video_|Add4~3 )); +// synopsys translate_off +defparam \ula_|video_|Add4~2 .lut_mask = 16'hC303; +defparam \ula_|video_|Add4~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y30_N14 +cycloneive_lcell_comb \ula_|video_|Add4~4 ( +// Equation(s): +// \ula_|video_|Add4~4_combout = (\ula_|video_|vga_vc [3] & ((GND) # (!\ula_|video_|Add4~3 ))) # (!\ula_|video_|vga_vc [3] & (\ula_|video_|Add4~3 $ (GND))) +// \ula_|video_|Add4~5 = CARRY((\ula_|video_|vga_vc [3]) # (!\ula_|video_|Add4~3 )) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [3]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~3 ), + .combout(\ula_|video_|Add4~4_combout ), + .cout(\ula_|video_|Add4~5 )); +// synopsys translate_off +defparam \ula_|video_|Add4~4 .lut_mask = 16'h3CCF; +defparam \ula_|video_|Add4~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y30_N16 +cycloneive_lcell_comb \ula_|video_|Add4~6 ( +// Equation(s): +// \ula_|video_|Add4~6_combout = (\ula_|video_|vga_vc [4] & (!\ula_|video_|Add4~5 )) # (!\ula_|video_|vga_vc [4] & ((\ula_|video_|Add4~5 ) # (GND))) +// \ula_|video_|Add4~7 = CARRY((!\ula_|video_|Add4~5 ) # (!\ula_|video_|vga_vc [4])) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [4]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~5 ), + .combout(\ula_|video_|Add4~6_combout ), + .cout(\ula_|video_|Add4~7 )); +// synopsys translate_off +defparam \ula_|video_|Add4~6 .lut_mask = 16'h3C3F; +defparam \ula_|video_|Add4~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X35_Y30_N17 +dffeas \ula_|video_|vram_address[5] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Add4~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[5] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y30_N18 +cycloneive_lcell_comb \ula_|video_|Add4~8 ( +// Equation(s): +// \ula_|video_|Add4~8_combout = (\ula_|video_|vga_vc [5] & ((GND) # (!\ula_|video_|Add4~7 ))) # (!\ula_|video_|vga_vc [5] & (\ula_|video_|Add4~7 $ (GND))) +// \ula_|video_|Add4~9 = CARRY((\ula_|video_|vga_vc [5]) # (!\ula_|video_|Add4~7 )) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [5]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~7 ), + .combout(\ula_|video_|Add4~8_combout ), + .cout(\ula_|video_|Add4~9 )); +// synopsys translate_off +defparam \ula_|video_|Add4~8 .lut_mask = 16'h3CCF; +defparam \ula_|video_|Add4~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X35_Y30_N19 +dffeas \ula_|video_|vram_address[6] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Add4~8_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[6] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y30_N20 +cycloneive_lcell_comb \ula_|video_|Add4~10 ( +// Equation(s): +// \ula_|video_|Add4~10_combout = (\ula_|video_|vga_vc [6] & (!\ula_|video_|Add4~9 )) # (!\ula_|video_|vga_vc [6] & ((\ula_|video_|Add4~9 ) # (GND))) +// \ula_|video_|Add4~11 = CARRY((!\ula_|video_|Add4~9 ) # (!\ula_|video_|vga_vc [6])) + + .dataa(\ula_|video_|vga_vc [6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~9 ), + .combout(\ula_|video_|Add4~10_combout ), + .cout(\ula_|video_|Add4~11 )); +// synopsys translate_off +defparam \ula_|video_|Add4~10 .lut_mask = 16'h5A5F; +defparam \ula_|video_|Add4~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X35_Y30_N21 +dffeas \ula_|video_|vram_address[7] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Add4~10_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[7] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y30_N22 +cycloneive_lcell_comb \ula_|video_|Add4~12 ( +// Equation(s): +// \ula_|video_|Add4~12_combout = (\ula_|video_|vga_vc [7] & ((GND) # (!\ula_|video_|Add4~11 ))) # (!\ula_|video_|vga_vc [7] & (\ula_|video_|Add4~11 $ (GND))) +// \ula_|video_|Add4~13 = CARRY((\ula_|video_|vga_vc [7]) # (!\ula_|video_|Add4~11 )) + + .dataa(\ula_|video_|vga_vc [7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~11 ), + .combout(\ula_|video_|Add4~12_combout ), + .cout(\ula_|video_|Add4~13 )); +// synopsys translate_off +defparam \ula_|video_|Add4~12 .lut_mask = 16'h5AAF; +defparam \ula_|video_|Add4~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y30_N26 +cycloneive_lcell_comb \ula_|video_|Selector6~0 ( +// Equation(s): +// \ula_|video_|Selector6~0_combout = (\ula_|video_|vga_hc [2] & ((\ula_|video_|Add4~12_combout ))) # (!\ula_|video_|vga_hc [2] & (\ula_|video_|Add4~0_combout )) + + .dataa(gnd), + .datab(\ula_|video_|vga_hc [2]), + .datac(\ula_|video_|Add4~0_combout ), + .datad(\ula_|video_|Add4~12_combout ), + .cin(gnd), + .combout(\ula_|video_|Selector6~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Selector6~0 .lut_mask = 16'hFC30; +defparam \ula_|video_|Selector6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y31_N16 +cycloneive_lcell_comb \ula_|video_|vram_address[9]~1 ( +// Equation(s): +// \ula_|video_|vram_address[9]~1_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [1] $ (\ula_|video_|vga_hc [2])))) + + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|vga_hc [3]), + .datac(\ula_|video_|vga_hc [2]), + .datad(\ula_|video_|vga_hc [0]), + .cin(gnd), + .combout(\ula_|video_|vram_address[9]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address[9]~1 .lut_mask = 16'h0048; +defparam \ula_|video_|vram_address[9]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y30_N27 +dffeas \ula_|video_|vram_address[8] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Selector6~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address[9]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [8]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[8] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y30_N24 +cycloneive_lcell_comb \ula_|video_|Add4~14 ( +// Equation(s): +// \ula_|video_|Add4~14_combout = \ula_|video_|Add4~13 $ (!\ula_|video_|vga_vc [8]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|vga_vc [8]), + .cin(\ula_|video_|Add4~13 ), + .combout(\ula_|video_|Add4~14_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Add4~14 .lut_mask = 16'hF00F; +defparam \ula_|video_|Add4~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y30_N12 +cycloneive_lcell_comb \ula_|video_|Selector5~0 ( +// Equation(s): +// \ula_|video_|Selector5~0_combout = (\ula_|video_|vga_hc [2] & ((\ula_|video_|Add4~14_combout ))) # (!\ula_|video_|vga_hc [2] & (\ula_|video_|Add4~2_combout )) + + .dataa(gnd), + .datab(\ula_|video_|vga_hc [2]), + .datac(\ula_|video_|Add4~2_combout ), + .datad(\ula_|video_|Add4~14_combout ), + .cin(gnd), + .combout(\ula_|video_|Selector5~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Selector5~0 .lut_mask = 16'hFC30; +defparam \ula_|video_|Selector5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y30_N13 +dffeas \ula_|video_|vram_address[9] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Selector5~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address[9]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [9]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[9] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y31_N6 +cycloneive_lcell_comb \ula_|video_|vram_address[10]~2 ( +// Equation(s): +// \ula_|video_|vram_address[10]~2_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [1] $ (\ula_|video_|vga_hc [2])))) + + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|vga_hc [3]), + .datac(\ula_|video_|vga_hc [2]), + .datad(\ula_|video_|vga_hc [0]), + .cin(gnd), + .combout(\ula_|video_|vram_address[10]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address[10]~2 .lut_mask = 16'h0048; +defparam \ula_|video_|vram_address[10]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y31_N28 +cycloneive_lcell_comb \ula_|video_|vram_address[10]~3 ( +// Equation(s): +// \ula_|video_|vram_address[10]~3_combout = (\ula_|video_|vram_address[10]~2_combout & (\ula_|video_|vga_hc [1] & (\ula_|video_|Add4~4_combout ))) # (!\ula_|video_|vram_address[10]~2_combout & (((\ula_|video_|vram_address [10])))) + + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|Add4~4_combout ), + .datac(\ula_|video_|vram_address [10]), + .datad(\ula_|video_|vram_address[10]~2_combout ), + .cin(gnd), + .combout(\ula_|video_|vram_address[10]~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address[10]~3 .lut_mask = 16'h88F0; +defparam \ula_|video_|vram_address[10]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y31_N29 +dffeas \ula_|video_|vram_address[10] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vram_address[10]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [10]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[10] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y30_N6 +cycloneive_lcell_comb \ula_|video_|Selector3~0 ( +// Equation(s): +// \ula_|video_|Selector3~0_combout = (\ula_|video_|vga_hc [2]) # (\ula_|video_|Add4~12_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|video_|vga_hc [2]), + .datad(\ula_|video_|Add4~12_combout ), + .cin(gnd), + .combout(\ula_|video_|Selector3~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Selector3~0 .lut_mask = 16'hFFF0; +defparam \ula_|video_|Selector3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y30_N7 +dffeas \ula_|video_|vram_address[11] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Selector3~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address[9]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [11]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[11] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y30_N8 +cycloneive_lcell_comb \ula_|video_|Selector2~0 ( +// Equation(s): +// \ula_|video_|Selector2~0_combout = (\ula_|video_|vga_hc [2]) # (\ula_|video_|Add4~14_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|video_|vga_hc [2]), + .datad(\ula_|video_|Add4~14_combout ), + .cin(gnd), + .combout(\ula_|video_|Selector2~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Selector2~0 .lut_mask = 16'hFFF0; +defparam \ula_|video_|Selector2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y30_N9 +dffeas \ula_|video_|vram_address[12] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Selector2~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address[9]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [12]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[12] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[12] .power_up = "low"; +// synopsys translate_on + +// Location: M9K_X33_Y26_N0 cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a9 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), @@ -41568,7 +40392,7 @@ cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a9 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[1]~34_combout }), + .portadatain({\D[1]~32_combout }), .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , \z80_|address_pins_|abus[0]~16_combout }), @@ -41625,125 +40449,26 @@ defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 204 defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: M9K_X33_Y32_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a9 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), - .portbdataout()); +// Location: LCCOMB_X29_Y11_N10 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout = (\z80_|address_pins_|abus[14]~23_combout & (\ExtRamWE~0_combout & (!\z80_|address_pins_|abus[15]~22_combout & !\z80_|address_pins_|abus[13]~20_combout ))) + + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\ExtRamWE~0_combout ), + .datac(\z80_|address_pins_|abus[15]~22_combout ), + .datad(\z80_|address_pins_|abus[13]~20_combout ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ), + .cout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h420000004200000000000000000080000000000000000000000000000030004480000000424202423E1E3E02304C3C0C3C7E7E40403E427E3402421824347C1C0400280000003C3406303220344C403C0400100010100000005062742400000091991809FB3BD9084A1241F5015988B3C506031934089E0E1FA8043DDAF2CC07D94A6F2B1D133C211222B22C787D430E45D4C53282288077DFC0F704AAD55127A2BEAEA114958D2817AB1213183A4E1A15E3690A08A33B429284A202011A1243D49CACA1C0A441405A720D21A0921294045F746229E287B95E956AA3DE0CA3B7A019C8039C4DDA6BC99371248CC6008A54CB84503442C4F91309238ECB252072; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h81F3167814687CBD683E54D44555E6C95B5F2A72C0C193C6110C0221A448D0C9A0D8E36A84D5C61285128845215F8F8821C308E368283D8E2B42989C04A8B51354E09A38775020189010680840800297C31282442326D008D1F2351A89FFD7C16087F8B130F04418C0A1C082FC005843F5B42CADD9455ADBD328C13219110DE100D988737BBB44C414210118C673B0C1BDF76C499226F78FF41A0AF7AFD3308AAA0AAA22B1C70003F542A66FD1F1CF9D4578315F8C1C6FEC3EDB9B322CB204821A94A248414CE030020F207BF040A06A3DF993DEA3823423F405294A52014565100E0A7211342DF02958046899EEBE6E491299A09312778193FEBD7FFABA8000; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h2C05EF54A3C0F7F5F017E03F5800377CCF6E493C84E8F56441831087370A084801DEC1A54696B9912E8B0705C8587D4F7D36C8638947A620554CC77819B55B7A12D552A8A0496EFE3AAC6F34739A94E798101823148D811212E9A349CC219049527CCD419525AD29AB7D372C0B56AA0A065F8BDC905346478059EC82801920687FF29C990C9E66273CC78041192D03081CC62A8A0D8CB4D9CF2F2558131A78B8A807C3A1110211AFCA2A142F0BA928156D142250438143D339E4E2079F298493C08C4847914664518E27EF7EB9C870A226AFC35BEDB651840466400D4B3C0F877740114D6B08228BCC693FB12CECCCD2461586069445ACFC910B1241434622B6; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h5FFE6AD3343986C4103935236B6E6E11B940EF46A8FC06E6872A6929D50DCDB75621E625522D34519BF2C353F8AA030B9109C2F9686AD3AF57AF3016D9160354C0BED5FBD379F904A41BAFB6BE4EE9F208058229DD0C354F034A6C4D8B6C16A29F0120108829220B230F44550832C1022530CC13C4C30D8254ECA5200A1941266EE48A1CA6430860DE613153615CAF4C8D191004CE9C6105D8C6795B6484467D21D9DC46029B8376E97F2C7BF8C3A218EE79DDBCF886B2BBDE702F71B38AEC6914E5DCCAFE50CC13922A5B149C598A621F80C24D215291228844E7F33F9763C6639303AE5376F664C7125632C1A280CECD5740C77849D937472B202579964F60; +defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1 .lut_mask = 16'h0008; +defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X33_Y21_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a1 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h35C65240B61076066A23CE4CFC5E76063A1C2AE07DF555007338BDC080EA0C23082C891C76A4845096304A0D8502080C1198911998821D09C29CA830C337499236E0548D65FF9125A765F0220F6EB9D1B318244CC6CA2CBC9CEC6979C14EB28DE2E0440C6CBD61341FC178649A852D4A2A0627C688D905B882524E191E7951EAEF30312A73337CBAD4838F42A3293859CD169240D8E652F6D72D8D19D56DD7675939FC47C933E1B0AEF12A484454C247B00A6BEC5402AA08B5106E3065602454C80CEC08A7F5F85CE65326632B4C4F3920019A35AE2AEB321131046EE45B81D4EFD5995634050D4CFEC166B032B6415553AF0358304080D9DD0A2E5948593830; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h376E511217E00B624A46BA2E4CC10B729C326F710F24CFE78C5E63F3024B17CC5E1380C938A0A16C9B696272DE7A2948BE8AFE81310146B8AAE5E549FA27EFBE27929938B8E10530250877A4998D0DF0004852125C20CA8D4279881E41208B14198817644F293AC1946061117122A39D8841818C1389D51BDAC549181902516571163594CEC5863F0F56625E221D6B8180848C6B2BE24AA0AEEE5D187201CAAE6AA394A8644314895565192AE415630A42894D6EF21343903B348EED8642F2310644C9567C0BF9911B870B989C59330089AA4C8065AB1B11132213EE0FD830817DE6C2ED45D76325CA2A8E198859334553AB02945CAB1F17C142288008073004; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h20721F982534A8179F13E2C6328CDE7D2A73087D3A9314419022103DFF7677769FE2D1F27443253D58403577C801AE23371F00290A17E1C4A40258BFD204230EE9969472A81B83113144528F831AA6C3221E137C1E9C670E26809A894013828D9E2DBCBF62498A769893D7218899245CD18AE49F0146517422EE475D520029ED39BCEF6BF4D23532957455F1C80115524179D59C4C4534DF7296991146CE24508366123AA809AB30B47977571C5D70397A93C723106D0A2C254714359DC7C9E13AE624C94932927924D20024CD638A05C8620023319662D80E05805625BC4A4006C78011F78D8B82E59F0CD4B32D6801669BE3EB0B96960DFF152005EC7C16CB; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h9C8CA06AA05B63C89A59A3E4E80807B27A70B0006624C4AC4A0595CCD8CA20824CA272352720BCD900A6D79BFD9D0595EC0D044ABC8CC28E9AE946E3D2000A4EFA4F91915C6AC9D8570C292F10848189906127BCBE06FFE92DAFB4AAFB240D88DDBB7B207EFA1709B05E1C4801BD45625A36BB62220506E171891964A31BED2215408676F600F490FAA59B488C7998CC8CCC28922AC62644EEBB432EEECB51B16CDEE7468681D6C31E4991CA3736E9ACB7531EC6D8BBCD453718101EA25D79278C6AC955A8A6140421573E413CF5A80AA1436D8B4C31A2AB26D2A61CE834248BAD5751BD429B4F61318427560CE39D49299002165212181064E24FF0093B997B; -// synopsys translate_on - -// Location: M9K_X33_Y22_N0 +// Location: M9K_X33_Y30_N0 cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a1 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), @@ -41757,7 +40482,7 @@ cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a1 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[1]~34_combout }), + .portadatain({\D[1]~32_combout }), .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , \z80_|address_pins_|abus[0]~16_combout }), @@ -41813,2095 +40538,104 @@ defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 204 defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'hCB9C84F288C855028DE04086AC0122869175A48288D30882FFFFFFFCC0000002CB9C80B78DD447828DE440828C0126829175840280D10B82FFFFFFFDE0408082C8D480838FD45582881C4482840160028179800280510B82C0000001BFFFFFFE8AD480BA8F844182880860828601660A8179900280510B02800000009FBF7F7C8B90A1328C8401828BE0608A86836E1281791012805107029FBF7F7D800000008B9883228C9405828BE0728286832E0281799042C0500F43BFFFFFFF80000000889081128FD400828A0066828782288281199002C0401F03A0408083FFFFFFFF888881128FE440828800268287D22CE280199022A0003F00E0408080FFFFFFFF; // synopsys translate_on -// Location: LCCOMB_X32_Y18_N0 +// Location: LCCOMB_X30_Y10_N20 cycloneive_lcell_comb \Selector1~0 ( // Equation(s): -// \Selector1~0_combout = (\z80_|address_pins_|abus[14]~23_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout )))) # (!\z80_|address_pins_|abus[14]~23_combout -// & (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ))) +// \Selector1~0_combout = (\z80_|address_pins_|abus[14]~23_combout & ((\Selector3~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout )) # (!\Selector3~0_combout & +// ((\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ))))) # (!\z80_|address_pins_|abus[14]~23_combout & (\Selector3~0_combout )) .dataa(\z80_|address_pins_|abus[14]~23_combout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ), + .datab(\Selector3~0_combout ), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout ), .datad(\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ), .cin(gnd), .combout(\Selector1~0_combout ), .cout()); // synopsys translate_off -defparam \Selector1~0 .lut_mask = 16'hBA98; +defparam \Selector1~0 .lut_mask = 16'hE6C4; defparam \Selector1~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y18_N2 +// Location: LCCOMB_X30_Y10_N22 cycloneive_lcell_comb \Selector1~1 ( // Equation(s): -// \Selector1~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Selector1~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout )) # (!\Selector1~0_combout & -// ((\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Selector1~0_combout )))) +// \Selector1~1_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\Selector1~0_combout )))) # (!\z80_|address_pins_|abus[14]~23_combout & ((\Selector1~0_combout & ((\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ))) # +// (!\Selector1~0_combout & (\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout )))) - .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ), .datac(\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ), .datad(\Selector1~0_combout ), .cin(gnd), .combout(\Selector1~1_combout ), .cout()); // synopsys translate_off -defparam \Selector1~1 .lut_mask = 16'hBBC0; +defparam \Selector1~1 .lut_mask = 16'hFA44; defparam \Selector1~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y18_N12 -cycloneive_lcell_comb \D[1]~103 ( +// Location: LCCOMB_X31_Y10_N28 +cycloneive_lcell_comb \D[1]~81 ( // Equation(s): -// \D[1]~103_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [15] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\Selector1~1_combout -// ))))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout )))) +// \D[1]~81_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\Selector1~1_combout ))) +// # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout )))) - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .dataa(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ), .datab(\z80_|address_pins_|DFFE_apin_latch [15]), - .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .datad(\Selector1~1_combout ), .cin(gnd), - .combout(\D[1]~103_combout ), + .combout(\D[1]~81_combout ), .cout()); // synopsys translate_off -defparam \D[1]~103 .lut_mask = 16'hF2D0; -defparam \D[1]~103 .sum_lutc_input = "datac"; +defparam \D[1]~81 .lut_mask = 16'hBA8A; +defparam \D[1]~81 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: IOIBUF_X18_Y34_N1 -cycloneive_io_ibuf \PS2_DAT~input ( - .i(PS2_DAT), - .ibar(gnd), - .o(\PS2_DAT~input_o )); -// synopsys translate_off -defparam \PS2_DAT~input .bus_hold = "false"; -defparam \PS2_DAT~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: CLKCTRL_G5 -cycloneive_clkctrl \reset~clkctrl ( - .ena(vcc), - .inclk({vcc,vcc,vcc,\reset~combout }), - .clkselect(2'b00), - .devclrn(devclrn), - .devpor(devpor), - .outclk(\reset~clkctrl_outclk )); -// synopsys translate_off -defparam \reset~clkctrl .clock_type = "global clock"; -defparam \reset~clkctrl .ena_register_mode = "none"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y21_N2 -cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|bit_count~0_combout = (!\ula_|ps2_keyboard_|bit_count [0] & (((!\ula_|ps2_keyboard_|bit_count [1] & !\ula_|ps2_keyboard_|bit_count [2])) # (!\ula_|ps2_keyboard_|bit_count [3]))) - - .dataa(\ula_|ps2_keyboard_|bit_count [1]), - .datab(\ula_|ps2_keyboard_|bit_count [3]), - .datac(\ula_|ps2_keyboard_|bit_count [0]), - .datad(\ula_|ps2_keyboard_|bit_count [2]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|bit_count~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count~0 .lut_mask = 16'h0307; -defparam \ula_|ps2_keyboard_|bit_count~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: IOIBUF_X9_Y34_N8 -cycloneive_io_ibuf \PS2_CLK~input ( - .i(PS2_CLK), - .ibar(gnd), - .o(\PS2_CLK~input_o )); -// synopsys translate_off -defparam \PS2_CLK~input .bus_hold = "false"; -defparam \PS2_CLK~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N0 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[7]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[7]~feeder_combout = \PS2_CLK~input_o - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\PS2_CLK~input_o ), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[7]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[7]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y26_N1 -dffeas \ula_|ps2_keyboard_|clk_filter[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[7] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N6 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[6]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[6]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [7] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [7]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[6]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[6]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y26_N7 -dffeas \ula_|ps2_keyboard_|clk_filter[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[6] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N20 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[5]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[5]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [6] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [6]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[5]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[5]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y26_N21 -dffeas \ula_|ps2_keyboard_|clk_filter[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[5] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N18 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[4]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[4]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [5] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [5]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[4]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[4]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y26_N19 -dffeas \ula_|ps2_keyboard_|clk_filter[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[4] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N12 -cycloneive_lcell_comb \ula_|ps2_keyboard_|Equal0~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|Equal0~0_combout = (!\ula_|ps2_keyboard_|clk_filter [6] & (!\ula_|ps2_keyboard_|clk_filter [7] & (!\ula_|ps2_keyboard_|clk_filter [5] & !\ula_|ps2_keyboard_|clk_filter [4]))) - - .dataa(\ula_|ps2_keyboard_|clk_filter [6]), - .datab(\ula_|ps2_keyboard_|clk_filter [7]), - .datac(\ula_|ps2_keyboard_|clk_filter [5]), - .datad(\ula_|ps2_keyboard_|clk_filter [4]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|Equal0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|Equal0~0 .lut_mask = 16'h0001; -defparam \ula_|ps2_keyboard_|Equal0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N2 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[3]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[3]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [4] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [4]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[3]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[3]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[3]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y26_N3 -dffeas \ula_|ps2_keyboard_|clk_filter[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[3]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[3] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N28 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[2]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[2]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [3] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [3]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[2]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y26_N29 -dffeas \ula_|ps2_keyboard_|clk_filter[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[2] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N22 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[1]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[1]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [2] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [2]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[1]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y26_N23 -dffeas \ula_|ps2_keyboard_|clk_filter[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[1] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N16 -cycloneive_lcell_comb \ula_|ps2_keyboard_|Equal0~1 ( -// Equation(s): -// \ula_|ps2_keyboard_|Equal0~1_combout = (\ula_|ps2_keyboard_|Equal0~0_combout & (!\ula_|ps2_keyboard_|clk_filter [2] & (!\ula_|ps2_keyboard_|clk_filter [1] & !\ula_|ps2_keyboard_|clk_filter [3]))) - - .dataa(\ula_|ps2_keyboard_|Equal0~0_combout ), - .datab(\ula_|ps2_keyboard_|clk_filter [2]), - .datac(\ula_|ps2_keyboard_|clk_filter [1]), - .datad(\ula_|ps2_keyboard_|clk_filter [3]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|Equal0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|Equal0~1 .lut_mask = 16'h0002; -defparam \ula_|ps2_keyboard_|Equal0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N10 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[0]~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[0]~0_combout = !\ula_|ps2_keyboard_|clk_filter [1] - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|clk_filter [1]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[0]~0 .lut_mask = 16'h0F0F; -defparam \ula_|ps2_keyboard_|clk_filter[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y26_N11 -dffeas \ula_|ps2_keyboard_|clk_filter[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[0]~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[0] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N26 -cycloneive_lcell_comb \ula_|ps2_keyboard_|ps2_clk_in~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|ps2_clk_in~0_combout = (\ula_|ps2_keyboard_|Equal0~1_combout & ((\ula_|ps2_keyboard_|clk_filter [0]))) # (!\ula_|ps2_keyboard_|Equal0~1_combout & (\ula_|ps2_keyboard_|ps2_clk_in~q )) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|Equal0~1_combout ), - .datac(\ula_|ps2_keyboard_|ps2_clk_in~q ), - .datad(\ula_|ps2_keyboard_|clk_filter [0]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|ps2_clk_in~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|ps2_clk_in~0 .lut_mask = 16'hFC30; -defparam \ula_|ps2_keyboard_|ps2_clk_in~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y26_N27 -dffeas \ula_|ps2_keyboard_|ps2_clk_in ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|ps2_clk_in~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|ps2_clk_in~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|ps2_clk_in .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|ps2_clk_in .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N4 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_edge~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_edge~0_combout = (\ula_|ps2_keyboard_|Equal0~1_combout & (!\ula_|ps2_keyboard_|ps2_clk_in~q & \ula_|ps2_keyboard_|clk_filter [0])) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|Equal0~1_combout ), - .datac(\ula_|ps2_keyboard_|ps2_clk_in~q ), - .datad(\ula_|ps2_keyboard_|clk_filter [0]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_edge~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_edge~0 .lut_mask = 16'h0C00; -defparam \ula_|ps2_keyboard_|clk_edge~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y26_N5 -dffeas \ula_|ps2_keyboard_|clk_edge ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_edge~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_edge~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_edge .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_edge .power_up = "low"; -// synopsys translate_on - -// Location: FF_X26_Y21_N3 -dffeas \ula_|ps2_keyboard_|bit_count[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|bit_count~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|ps2_keyboard_|clk_edge~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|bit_count [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count[0] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|bit_count[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y21_N0 -cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~1 ( -// Equation(s): -// \ula_|ps2_keyboard_|bit_count~1_combout = (!\ula_|ps2_keyboard_|bit_count [3] & (\ula_|ps2_keyboard_|bit_count [2] $ (((\ula_|ps2_keyboard_|bit_count [1] & \ula_|ps2_keyboard_|bit_count [0]))))) - - .dataa(\ula_|ps2_keyboard_|bit_count [1]), - .datab(\ula_|ps2_keyboard_|bit_count [3]), - .datac(\ula_|ps2_keyboard_|bit_count [2]), - .datad(\ula_|ps2_keyboard_|bit_count [0]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|bit_count~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count~1 .lut_mask = 16'h1230; -defparam \ula_|ps2_keyboard_|bit_count~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y21_N1 -dffeas \ula_|ps2_keyboard_|bit_count[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|bit_count~1_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|ps2_keyboard_|clk_edge~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|bit_count [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count[2] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|bit_count[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y21_N16 -cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~3 ( -// Equation(s): -// \ula_|ps2_keyboard_|bit_count~3_combout = (\ula_|ps2_keyboard_|bit_count [1] & (\ula_|ps2_keyboard_|bit_count [2] & (!\ula_|ps2_keyboard_|bit_count [3] & \ula_|ps2_keyboard_|bit_count [0]))) # (!\ula_|ps2_keyboard_|bit_count [1] & -// (!\ula_|ps2_keyboard_|bit_count [2] & (\ula_|ps2_keyboard_|bit_count [3]))) - - .dataa(\ula_|ps2_keyboard_|bit_count [1]), - .datab(\ula_|ps2_keyboard_|bit_count [2]), - .datac(\ula_|ps2_keyboard_|bit_count [3]), - .datad(\ula_|ps2_keyboard_|bit_count [0]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|bit_count~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count~3 .lut_mask = 16'h1810; -defparam \ula_|ps2_keyboard_|bit_count~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y21_N17 -dffeas \ula_|ps2_keyboard_|bit_count[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|bit_count~3_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|ps2_keyboard_|clk_edge~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|bit_count [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count[3] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|bit_count[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y21_N26 -cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~2 ( -// Equation(s): -// \ula_|ps2_keyboard_|bit_count~2_combout = (\ula_|ps2_keyboard_|bit_count [3] & (!\ula_|ps2_keyboard_|bit_count [2] & (!\ula_|ps2_keyboard_|bit_count [1] & \ula_|ps2_keyboard_|bit_count [0]))) # (!\ula_|ps2_keyboard_|bit_count [3] & -// ((\ula_|ps2_keyboard_|bit_count [1] $ (\ula_|ps2_keyboard_|bit_count [0])))) - - .dataa(\ula_|ps2_keyboard_|bit_count [3]), - .datab(\ula_|ps2_keyboard_|bit_count [2]), - .datac(\ula_|ps2_keyboard_|bit_count [1]), - .datad(\ula_|ps2_keyboard_|bit_count [0]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|bit_count~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count~2 .lut_mask = 16'h0750; -defparam \ula_|ps2_keyboard_|bit_count~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y21_N27 -dffeas \ula_|ps2_keyboard_|bit_count[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|bit_count~2_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|ps2_keyboard_|clk_edge~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|bit_count [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count[1] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|bit_count[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y21_N22 -cycloneive_lcell_comb \ula_|ps2_keyboard_|always1~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|always1~0_combout = (!\ula_|ps2_keyboard_|bit_count [1] & (!\ula_|ps2_keyboard_|bit_count [3] & (!\PS2_DAT~input_o & !\ula_|ps2_keyboard_|bit_count [2]))) - - .dataa(\ula_|ps2_keyboard_|bit_count [1]), - .datab(\ula_|ps2_keyboard_|bit_count [3]), - .datac(\PS2_DAT~input_o ), - .datad(\ula_|ps2_keyboard_|bit_count [2]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|always1~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|always1~0 .lut_mask = 16'h0001; -defparam \ula_|ps2_keyboard_|always1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y21_N12 -cycloneive_lcell_comb \ula_|ps2_keyboard_|LessThan0~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|LessThan0~0_combout = (\ula_|ps2_keyboard_|bit_count [3] & ((\ula_|ps2_keyboard_|bit_count [1]) # (\ula_|ps2_keyboard_|bit_count [2]))) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|bit_count [3]), - .datac(\ula_|ps2_keyboard_|bit_count [1]), - .datad(\ula_|ps2_keyboard_|bit_count [2]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|LessThan0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|LessThan0~0 .lut_mask = 16'hCCC0; -defparam \ula_|ps2_keyboard_|LessThan0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y21_N6 -cycloneive_lcell_comb \ula_|ps2_keyboard_|shiftreg[0]~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|shiftreg[0]~0_combout = (\ula_|ps2_keyboard_|clk_edge~q & (!\ula_|ps2_keyboard_|LessThan0~0_combout & ((\ula_|ps2_keyboard_|bit_count [0]) # (!\ula_|ps2_keyboard_|always1~0_combout )))) - - .dataa(\ula_|ps2_keyboard_|always1~0_combout ), - .datab(\ula_|ps2_keyboard_|bit_count [0]), - .datac(\ula_|ps2_keyboard_|clk_edge~q ), - .datad(\ula_|ps2_keyboard_|LessThan0~0_combout ), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[0]~0 .lut_mask = 16'h00D0; -defparam \ula_|ps2_keyboard_|shiftreg[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y21_N9 -dffeas \ula_|ps2_keyboard_|shiftreg[8] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\PS2_DAT~input_o ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [8]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[8] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[8] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y21_N15 -dffeas \ula_|ps2_keyboard_|shiftreg[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [8]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[7] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y21_N5 -dffeas \ula_|ps2_keyboard_|shiftreg[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [7]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[6] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y21_N11 -dffeas \ula_|ps2_keyboard_|shiftreg[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [6]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[5] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y21_N11 -dffeas \ula_|ps2_keyboard_|shiftreg[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [5]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[4] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y21_N25 -dffeas \ula_|ps2_keyboard_|shiftreg[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [4]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[3] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y21_N29 -dffeas \ula_|ps2_keyboard_|shiftreg[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [3]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[2] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y21_N1 -dffeas \ula_|ps2_keyboard_|shiftreg[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [2]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[1] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y21_N17 -dffeas \ula_|ps2_keyboard_|shiftreg[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [1]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[0] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~0 ( -// Equation(s): -// \ula_|zx_keyboard_|Equal0~0_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [7] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [5]), - .datab(\ula_|ps2_keyboard_|shiftreg [7]), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|Equal0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|Equal0~0 .lut_mask = 16'h0008; -defparam \ula_|zx_keyboard_|Equal0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~1 ( -// Equation(s): -// \ula_|zx_keyboard_|Equal0~1_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|Equal0~0_combout & !\ula_|ps2_keyboard_|shiftreg [1]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|zx_keyboard_|Equal0~0_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|Equal0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|Equal0~1 .lut_mask = 16'h0020; -defparam \ula_|zx_keyboard_|Equal0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|extended~0 ( -// Equation(s): -// \ula_|zx_keyboard_|extended~0_combout = (\ula_|zx_keyboard_|Equal0~1_combout & ((\ula_|zx_keyboard_|extended~q ) # (!\ula_|ps2_keyboard_|shiftreg [4]))) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [4]), - .datac(\ula_|zx_keyboard_|extended~q ), - .datad(\ula_|zx_keyboard_|Equal0~1_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|extended~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|extended~0 .lut_mask = 16'hF300; -defparam \ula_|zx_keyboard_|extended~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y21_N8 -cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~1 ( -// Equation(s): -// \ula_|ps2_keyboard_|WideXor0~1_combout = \ula_|ps2_keyboard_|shiftreg [6] $ (\ula_|ps2_keyboard_|shiftreg [7] $ (\ula_|ps2_keyboard_|shiftreg [8] $ (\ula_|ps2_keyboard_|shiftreg [5]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|ps2_keyboard_|shiftreg [7]), - .datac(\ula_|ps2_keyboard_|shiftreg [8]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|WideXor0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|WideXor0~1 .lut_mask = 16'h6996; -defparam \ula_|ps2_keyboard_|WideXor0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y21_N0 -cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|WideXor0~0_combout = \ula_|ps2_keyboard_|shiftreg [2] $ (\ula_|ps2_keyboard_|shiftreg [0] $ (\ula_|ps2_keyboard_|shiftreg [1] $ (\ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|WideXor0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|WideXor0~0 .lut_mask = 16'h6996; -defparam \ula_|ps2_keyboard_|WideXor0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y21_N6 -cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~2 ( -// Equation(s): -// \ula_|ps2_keyboard_|WideXor0~2_combout = \ula_|ps2_keyboard_|shiftreg [4] $ (\ula_|ps2_keyboard_|WideXor0~1_combout $ (\ula_|ps2_keyboard_|WideXor0~0_combout )) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [4]), - .datac(\ula_|ps2_keyboard_|WideXor0~1_combout ), - .datad(\ula_|ps2_keyboard_|WideXor0~0_combout ), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|WideXor0~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|WideXor0~2 .lut_mask = 16'hC33C; -defparam \ula_|ps2_keyboard_|WideXor0~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y21_N8 -cycloneive_lcell_comb \ula_|ps2_keyboard_|scan_code_ready~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|scan_code_ready~0_combout = (\ula_|ps2_keyboard_|LessThan0~0_combout & (\PS2_DAT~input_o & (\ula_|ps2_keyboard_|clk_edge~q & \ula_|ps2_keyboard_|WideXor0~2_combout ))) - - .dataa(\ula_|ps2_keyboard_|LessThan0~0_combout ), - .datab(\PS2_DAT~input_o ), - .datac(\ula_|ps2_keyboard_|clk_edge~q ), - .datad(\ula_|ps2_keyboard_|WideXor0~2_combout ), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|scan_code_ready~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|scan_code_ready~0 .lut_mask = 16'h8000; -defparam \ula_|ps2_keyboard_|scan_code_ready~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y21_N9 -dffeas \ula_|ps2_keyboard_|scan_code_ready ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|scan_code_ready~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|scan_code_ready~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|scan_code_ready .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|scan_code_ready .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y20_N1 -dffeas \ula_|zx_keyboard_|extended ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|extended~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|ps2_keyboard_|scan_code_ready~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|extended~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|extended .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|extended .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y21_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~15 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][0]~15_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (!\ula_|zx_keyboard_|Equal0~1_combout & !\ula_|ps2_keyboard_|shiftreg [7])) - - .dataa(\ula_|ps2_keyboard_|scan_code_ready~q ), - .datab(\ula_|zx_keyboard_|Equal0~1_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [7]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][0]~15 .lut_mask = 16'h0202; -defparam \ula_|zx_keyboard_|keys[0][0]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~36 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][1]~36_combout = (!\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[0][0]~15_combout )) - - .dataa(\ula_|zx_keyboard_|extended~q ), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][1]~36_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1]~36 .lut_mask = 16'h0500; -defparam \ula_|zx_keyboard_|keys[5][1]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~37 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][1]~37_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[5][1]~36_combout & \ula_|ps2_keyboard_|shiftreg [2])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[5][1]~36_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][1]~37_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1]~37 .lut_mask = 16'hA000; -defparam \ula_|zx_keyboard_|keys[5][1]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~0 ( -// Equation(s): -// \ula_|zx_keyboard_|shifted~0_combout = (\ula_|zx_keyboard_|keys[0][0]~15_combout & (!\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|zx_keyboard_|extended~q )) - - .dataa(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|zx_keyboard_|extended~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|shifted~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|shifted~0 .lut_mask = 16'h000A; -defparam \ula_|zx_keyboard_|shifted~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y21_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|released~0 ( -// Equation(s): -// \ula_|zx_keyboard_|released~0_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (\ula_|zx_keyboard_|Equal0~1_combout & ((\ula_|ps2_keyboard_|shiftreg [4]) # (\ula_|zx_keyboard_|released~q )))) # (!\ula_|ps2_keyboard_|scan_code_ready~q & -// (((\ula_|zx_keyboard_|released~q )))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|zx_keyboard_|Equal0~1_combout ), - .datac(\ula_|zx_keyboard_|released~q ), - .datad(\ula_|ps2_keyboard_|scan_code_ready~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|released~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|released~0 .lut_mask = 16'hC8F0; -defparam \ula_|zx_keyboard_|released~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y21_N19 -dffeas \ula_|zx_keyboard_|released ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|released~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|released~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|released .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|released .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr17~0 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr17~0_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [0]))) # (!\ula_|ps2_keyboard_|shiftreg [1] & -// (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [0]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr17~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr17~0 .lut_mask = 16'h4002; -defparam \ula_|zx_keyboard_|WideOr17~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~2 ( -// Equation(s): -// \ula_|zx_keyboard_|shifted~2_combout = (\ula_|zx_keyboard_|WideOr17~0_combout & (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [4])) - - .dataa(\ula_|zx_keyboard_|WideOr17~0_combout ), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|shifted~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|shifted~2 .lut_mask = 16'h0A00; -defparam \ula_|zx_keyboard_|shifted~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~3 ( -// Equation(s): -// \ula_|zx_keyboard_|shifted~3_combout = (\ula_|zx_keyboard_|shifted~0_combout & ((\ula_|zx_keyboard_|shifted~2_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|shifted~2_combout & ((\ula_|zx_keyboard_|shifted~q ))))) # -// (!\ula_|zx_keyboard_|shifted~0_combout & (((\ula_|zx_keyboard_|shifted~q )))) - - .dataa(\ula_|zx_keyboard_|shifted~0_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|shifted~q ), - .datad(\ula_|zx_keyboard_|shifted~2_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|shifted~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|shifted~3 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|shifted~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y21_N3 -dffeas \ula_|zx_keyboard_|shifted ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|shifted~3_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|shifted~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|shifted .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|shifted .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~35 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][1]~35_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [3])) - - .dataa(\ula_|zx_keyboard_|shifted~q ), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(gnd), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][1]~35_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1]~35 .lut_mask = 16'hFF88; -defparam \ula_|zx_keyboard_|keys[5][1]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~38 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][1]~38_combout = (!\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [0])) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][1]~38_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1]~38 .lut_mask = 16'h0003; -defparam \ula_|zx_keyboard_|keys[5][1]~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~39 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][1]~39_combout = (\ula_|zx_keyboard_|keys[5][1]~37_combout & ((\ula_|zx_keyboard_|keys[5][1]~38_combout & (!\ula_|zx_keyboard_|keys[5][1]~35_combout )) # (!\ula_|zx_keyboard_|keys[5][1]~38_combout & -// ((\ula_|zx_keyboard_|keys[5][1]~q ))))) # (!\ula_|zx_keyboard_|keys[5][1]~37_combout & (((\ula_|zx_keyboard_|keys[5][1]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[5][1]~37_combout ), - .datab(\ula_|zx_keyboard_|keys[5][1]~35_combout ), - .datac(\ula_|zx_keyboard_|keys[5][1]~q ), - .datad(\ula_|zx_keyboard_|keys[5][1]~38_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][1]~39_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1]~39 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[5][1]~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y18_N19 -dffeas \ula_|zx_keyboard_|keys[5][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[5][1]~39_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[5][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[5][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][1]~31 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][1]~31_combout = (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [0]) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][1]~31_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][1]~31 .lut_mask = 16'h00CC; -defparam \ula_|zx_keyboard_|keys[4][1]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y21_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~23 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][1]~23_combout = (!\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [7] & \ula_|ps2_keyboard_|scan_code_ready~q )) - - .dataa(\ula_|zx_keyboard_|extended~q ), - .datab(\ula_|ps2_keyboard_|shiftreg [7]), - .datac(\ula_|ps2_keyboard_|scan_code_ready~q ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][1]~23_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][1]~23 .lut_mask = 16'h1010; -defparam \ula_|zx_keyboard_|keys[7][1]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y21_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~32 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~32_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [4])) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~32_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~32 .lut_mask = 16'h000C; -defparam \ula_|zx_keyboard_|keys[7][2]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y21_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~33 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][2]~33_combout = (\ula_|zx_keyboard_|keys[7][1]~23_combout & (\ula_|zx_keyboard_|keys[7][2]~32_combout & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|zx_keyboard_|keys[7][1]~23_combout ), - .datab(\ula_|zx_keyboard_|keys[7][2]~32_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][2]~33_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][2]~33 .lut_mask = 16'h0080; -defparam \ula_|zx_keyboard_|keys[5][2]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][1]~34 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][1]~34_combout = (\ula_|zx_keyboard_|keys[4][1]~31_combout & ((\ula_|zx_keyboard_|keys[5][2]~33_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[5][2]~33_combout & (\ula_|zx_keyboard_|keys[4][1]~q -// )))) # (!\ula_|zx_keyboard_|keys[4][1]~31_combout & (((\ula_|zx_keyboard_|keys[4][1]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[4][1]~31_combout ), - .datab(\ula_|zx_keyboard_|keys[5][2]~33_combout ), - .datac(\ula_|zx_keyboard_|keys[4][1]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][1]~34_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][1]~34 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[4][1]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y18_N9 -dffeas \ula_|zx_keyboard_|keys[4][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[4][1]~34_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[4][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[4][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N24 -cycloneive_lcell_comb \D[1]~30 ( -// Equation(s): -// \D[1]~30_combout = (\z80_|address_pins_|abus[13]~20_combout & (((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][1]~q )))) # (!\z80_|address_pins_|abus[13]~20_combout & (!\ula_|zx_keyboard_|keys[5][1]~q & -// ((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][1]~q )))) - - .dataa(\z80_|address_pins_|abus[13]~20_combout ), - .datab(\ula_|zx_keyboard_|keys[5][1]~q ), - .datac(\ula_|zx_keyboard_|keys[4][1]~q ), - .datad(\z80_|address_pins_|abus[12]~21_combout ), - .cin(gnd), - .combout(\D[1]~30_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~30 .lut_mask = 16'hBB0B; -defparam \D[1]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~24 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][4]~24_combout = (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [2]) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][4]~24_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][4]~24 .lut_mask = 16'hA0A0; -defparam \ula_|zx_keyboard_|keys[5][4]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~28 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][1]~28_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[7][1]~23_combout & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[5][4]~24_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|zx_keyboard_|keys[7][1]~23_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|zx_keyboard_|keys[5][4]~24_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][1]~28_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][1]~28 .lut_mask = 16'h0400; -defparam \ula_|zx_keyboard_|keys[3][1]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~29 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][1]~29_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [0])) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][1]~29_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][1]~29 .lut_mask = 16'h00C0; -defparam \ula_|zx_keyboard_|keys[3][1]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~30 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][1]~30_combout = (\ula_|zx_keyboard_|keys[3][1]~28_combout & ((\ula_|zx_keyboard_|keys[3][1]~29_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][1]~29_combout & ((\ula_|zx_keyboard_|keys[3][1]~q -// ))))) # (!\ula_|zx_keyboard_|keys[3][1]~28_combout & (((\ula_|zx_keyboard_|keys[3][1]~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[3][1]~28_combout ), - .datac(\ula_|zx_keyboard_|keys[3][1]~q ), - .datad(\ula_|zx_keyboard_|keys[3][1]~29_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][1]~30_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][1]~30 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[3][1]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y18_N17 -dffeas \ula_|zx_keyboard_|keys[3][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[3][1]~30_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[3][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[3][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][4]~25 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][4]~25_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[5][4]~24_combout & (\ula_|zx_keyboard_|keys[7][1]~23_combout & !\ula_|ps2_keyboard_|shiftreg [1]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|zx_keyboard_|keys[5][4]~24_combout ), - .datac(\ula_|zx_keyboard_|keys[7][1]~23_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][4]~25_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][4]~25 .lut_mask = 16'h0040; -defparam \ula_|zx_keyboard_|keys[1][4]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][1]~26 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][1]~26_combout = (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|zx_keyboard_|keys[1][4]~25_combout & \ula_|ps2_keyboard_|shiftreg [0])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [5]), - .datab(\ula_|zx_keyboard_|keys[1][4]~25_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][1]~26_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][1]~26 .lut_mask = 16'h4040; -defparam \ula_|zx_keyboard_|keys[2][1]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][1]~27 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][1]~27_combout = (\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[2][1]~26_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[2][1]~26_combout & ((\ula_|zx_keyboard_|keys[2][1]~q ))))) # -// (!\ula_|ps2_keyboard_|shiftreg [3] & (((\ula_|zx_keyboard_|keys[2][1]~q )))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[2][1]~q ), - .datad(\ula_|zx_keyboard_|keys[2][1]~26_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][1]~27_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][1]~27 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[2][1]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y20_N17 -dffeas \ula_|zx_keyboard_|keys[2][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[2][1]~27_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[2][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[2][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~0 ( -// Equation(s): -// \ula_|zx_keyboard_|key_row~0_combout = ((\z80_|address_pins_|DFFE_apin_latch [10]) # (!\ula_|zx_keyboard_|keys[2][1]~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [10]), - .datad(\ula_|zx_keyboard_|keys[2][1]~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|key_row~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|key_row~0 .lut_mask = 16'hF3FF; -defparam \ula_|zx_keyboard_|key_row~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~14 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][1]~14_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & !\ula_|ps2_keyboard_|shiftreg [4])) - - .dataa(gnd), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|shifted~q ), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][1]~14_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][1]~14 .lut_mask = 16'hCCCF; -defparam \ula_|zx_keyboard_|keys[0][1]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~16 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][1]~16_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [4] $ (\ula_|ps2_keyboard_|shiftreg [2])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][1]~16_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][1]~16 .lut_mask = 16'h0060; -defparam \ula_|zx_keyboard_|keys[0][1]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~17 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][1]~17_combout = (\ula_|zx_keyboard_|keys[0][1]~16_combout & ((\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [4])) # (!\ula_|ps2_keyboard_|shiftreg [1] & -// (\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [4])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|zx_keyboard_|keys[0][1]~16_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][1]~17_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][1]~17 .lut_mask = 16'h2040; -defparam \ula_|zx_keyboard_|keys[0][1]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~18 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][1]~18_combout = (\ula_|zx_keyboard_|shifted~0_combout & ((\ula_|zx_keyboard_|keys[0][1]~17_combout & (!\ula_|zx_keyboard_|keys[0][1]~14_combout )) # (!\ula_|zx_keyboard_|keys[0][1]~17_combout & -// ((\ula_|zx_keyboard_|keys[0][1]~q ))))) # (!\ula_|zx_keyboard_|shifted~0_combout & (((\ula_|zx_keyboard_|keys[0][1]~q )))) - - .dataa(\ula_|zx_keyboard_|shifted~0_combout ), - .datab(\ula_|zx_keyboard_|keys[0][1]~14_combout ), - .datac(\ula_|zx_keyboard_|keys[0][1]~q ), - .datad(\ula_|zx_keyboard_|keys[0][1]~17_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][1]~18_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][1]~18 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[0][1]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y21_N7 -dffeas \ula_|zx_keyboard_|keys[0][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[0][1]~18_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[0][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[0][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~19 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][4]~19_combout = (!\ula_|ps2_keyboard_|shiftreg [7] & (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|zx_keyboard_|extended~q & \ula_|ps2_keyboard_|scan_code_ready~q ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [7]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|zx_keyboard_|extended~q ), - .datad(\ula_|ps2_keyboard_|scan_code_ready~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][4]~19_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][4]~19 .lut_mask = 16'h0100; -defparam \ula_|zx_keyboard_|keys[7][4]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~20 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][4]~20_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [2]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [0]), - .datab(\ula_|ps2_keyboard_|shiftreg [4]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][4]~20_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][4]~20 .lut_mask = 16'h0080; -defparam \ula_|zx_keyboard_|keys[6][4]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][1]~21 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][1]~21_combout = (\ula_|zx_keyboard_|keys[7][4]~19_combout & (\ula_|zx_keyboard_|keys[6][4]~20_combout & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|zx_keyboard_|keys[7][4]~19_combout ), - .datab(\ula_|zx_keyboard_|keys[6][4]~20_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][1]~21_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][1]~21 .lut_mask = 16'h0800; -defparam \ula_|zx_keyboard_|keys[1][1]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][1]~22 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][1]~22_combout = (\ula_|zx_keyboard_|keys[1][1]~21_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[1][1]~21_combout & (\ula_|zx_keyboard_|keys[1][1]~q )) - - .dataa(gnd), - .datab(\ula_|zx_keyboard_|keys[1][1]~21_combout ), - .datac(\ula_|zx_keyboard_|keys[1][1]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][1]~22_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][1]~22 .lut_mask = 16'h30FC; -defparam \ula_|zx_keyboard_|keys[1][1]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y20_N13 -dffeas \ula_|zx_keyboard_|keys[1][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[1][1]~22_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[1][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[1][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N2 -cycloneive_lcell_comb \D[1]~28 ( -// Equation(s): -// \D[1]~28_combout = (\ula_|zx_keyboard_|keys[0][1]~q & (\z80_|address_pins_|abus[8]~18_combout & ((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][1]~q )))) # (!\ula_|zx_keyboard_|keys[0][1]~q & -// (((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][1]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[0][1]~q ), - .datab(\z80_|address_pins_|abus[8]~18_combout ), - .datac(\z80_|address_pins_|abus[9]~17_combout ), - .datad(\ula_|zx_keyboard_|keys[1][1]~q ), - .cin(gnd), - .combout(\D[1]~28_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~28 .lut_mask = 16'hD0DD; -defparam \D[1]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N26 -cycloneive_lcell_comb \D[1]~29 ( -// Equation(s): -// \D[1]~29_combout = (\ula_|zx_keyboard_|key_row~0_combout & (\D[1]~28_combout & ((\z80_|address_pins_|abus[11]~19_combout ) # (!\ula_|zx_keyboard_|keys[3][1]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[3][1]~q ), - .datab(\ula_|zx_keyboard_|key_row~0_combout ), - .datac(\z80_|address_pins_|abus[11]~19_combout ), - .datad(\D[1]~28_combout ), - .cin(gnd), - .combout(\D[1]~29_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~29 .lut_mask = 16'hC400; -defparam \D[1]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~41 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][1]~41_combout = (!\ula_|zx_keyboard_|extended~q & (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[0][0]~15_combout ))) - - .dataa(\ula_|zx_keyboard_|extended~q ), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][1]~41_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1]~41 .lut_mask = 16'h0400; -defparam \ula_|zx_keyboard_|keys[6][1]~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~42 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][1]~42_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [3]))) # (!\ula_|ps2_keyboard_|shiftreg [1] & -// (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][1]~42_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1]~42 .lut_mask = 16'h0240; -defparam \ula_|zx_keyboard_|keys[6][1]~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~43 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][1]~43_combout = (\ula_|zx_keyboard_|keys[6][1]~41_combout & (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|zx_keyboard_|keys[6][1]~42_combout )) - - .dataa(\ula_|zx_keyboard_|keys[6][1]~41_combout ), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|zx_keyboard_|keys[6][1]~42_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][1]~43_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1]~43 .lut_mask = 16'hA000; -defparam \ula_|zx_keyboard_|keys[6][1]~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~40 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][1]~40_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [2] & \ula_|zx_keyboard_|shifted~q )) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|zx_keyboard_|shifted~q ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][1]~40_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1]~40 .lut_mask = 16'hEAEA; -defparam \ula_|zx_keyboard_|keys[6][1]~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~44 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][1]~44_combout = (\ula_|zx_keyboard_|keys[6][1]~43_combout & ((!\ula_|zx_keyboard_|keys[6][1]~40_combout ))) # (!\ula_|zx_keyboard_|keys[6][1]~43_combout & (\ula_|zx_keyboard_|keys[6][1]~q )) - - .dataa(\ula_|zx_keyboard_|keys[6][1]~43_combout ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[6][1]~q ), - .datad(\ula_|zx_keyboard_|keys[6][1]~40_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][1]~44_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1]~44 .lut_mask = 16'h50FA; -defparam \ula_|zx_keyboard_|keys[6][1]~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y20_N25 -dffeas \ula_|zx_keyboard_|keys[6][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[6][1]~44_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[6][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[6][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y21_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~45 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][1]~45_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (!\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [7]))) - - .dataa(\ula_|ps2_keyboard_|scan_code_ready~q ), - .datab(\ula_|zx_keyboard_|extended~q ), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|ps2_keyboard_|shiftreg [7]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][1]~45_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][1]~45 .lut_mask = 16'h0002; -defparam \ula_|zx_keyboard_|keys[7][1]~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~5 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~5_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (((!\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [1])))) # (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & -// ((\ula_|ps2_keyboard_|shiftreg [2]) # (\ula_|ps2_keyboard_|shiftreg [1])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~5_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~5 .lut_mask = 16'h0A38; -defparam \ula_|zx_keyboard_|WideOr16~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~2 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~2_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~2 .lut_mask = 16'h0044; -defparam \ula_|zx_keyboard_|WideOr16~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~4 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~4_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1])) # (!\ula_|ps2_keyboard_|shiftreg [2] & -// (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [1])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~4_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~4 .lut_mask = 16'h0140; -defparam \ula_|zx_keyboard_|WideOr16~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~7 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~7_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (((\ula_|zx_keyboard_|WideOr16~4_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|WideOr16~2_combout & (!\ula_|ps2_keyboard_|shiftreg [2]))) - - .dataa(\ula_|zx_keyboard_|WideOr16~2_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|zx_keyboard_|WideOr16~4_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~7_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~7 .lut_mask = 16'hF022; -defparam \ula_|zx_keyboard_|WideOr16~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~6 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~6_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (((\ula_|zx_keyboard_|WideOr16~7_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|WideOr16~5_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|zx_keyboard_|WideOr16~5_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|WideOr16~7_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~6_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~6 .lut_mask = 16'hF808; -defparam \ula_|zx_keyboard_|WideOr16~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y21_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~46 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][1]~46_combout = (\ula_|zx_keyboard_|keys[7][1]~45_combout & ((\ula_|zx_keyboard_|WideOr16~6_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|WideOr16~6_combout & ((\ula_|zx_keyboard_|keys[7][1]~q ))))) # -// (!\ula_|zx_keyboard_|keys[7][1]~45_combout & (((\ula_|zx_keyboard_|keys[7][1]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[7][1]~45_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[7][1]~q ), - .datad(\ula_|zx_keyboard_|WideOr16~6_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][1]~46_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][1]~46 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[7][1]~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y21_N31 -dffeas \ula_|zx_keyboard_|keys[7][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[7][1]~46_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[7][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[7][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N20 +// Location: LCCOMB_X31_Y10_N20 cycloneive_lcell_comb \D[1]~31 ( // Equation(s): -// \D[1]~31_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\z80_|address_pins_|abus[15]~22_combout ) # (!\ula_|zx_keyboard_|keys[7][1]~q )))) # (!\z80_|address_pins_|abus[14]~23_combout & (!\ula_|zx_keyboard_|keys[6][1]~q & -// ((\z80_|address_pins_|abus[15]~22_combout ) # (!\ula_|zx_keyboard_|keys[7][1]~q )))) +// \D[1]~31_combout = ((\Equal2~0_combout & (\D[1]~30_combout )) # (!\Equal2~0_combout & ((\D[1]~81_combout )))) # (!\Equal2~1_combout ) - .dataa(\z80_|address_pins_|abus[14]~23_combout ), - .datab(\ula_|zx_keyboard_|keys[6][1]~q ), - .datac(\z80_|address_pins_|abus[15]~22_combout ), - .datad(\ula_|zx_keyboard_|keys[7][1]~q ), + .dataa(\Equal2~1_combout ), + .datab(\Equal2~0_combout ), + .datac(\D[1]~30_combout ), + .datad(\D[1]~81_combout ), .cin(gnd), .combout(\D[1]~31_combout ), .cout()); // synopsys translate_off -defparam \D[1]~31 .lut_mask = 16'hB0BB; +defparam \D[1]~31 .lut_mask = 16'hF7D5; defparam \D[1]~31 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y20_N18 +// Location: LCCOMB_X31_Y10_N2 cycloneive_lcell_comb \D[1]~32 ( // Equation(s): -// \D[1]~32_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[1]~30_combout & (\D[1]~29_combout & \D[1]~31_combout ))) +// \D[1]~32_combout = (\z80_|pin_control_|bus_db_pin_oe~15_combout & (((\z80_|data_pins_|dout [1] & \D[1]~31_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout & (((\D[1]~31_combout )) # (!\Equal2~1_combout ))) - .dataa(\D[1]~30_combout ), - .datab(\z80_|address_pins_|abus[0]~16_combout ), - .datac(\D[1]~29_combout ), + .dataa(\Equal2~1_combout ), + .datab(\z80_|data_pins_|dout [1]), + .datac(\z80_|pin_control_|bus_db_pin_oe~15_combout ), .datad(\D[1]~31_combout ), .cin(gnd), .combout(\D[1]~32_combout ), .cout()); // synopsys translate_off -defparam \D[1]~32 .lut_mask = 16'hECCC; +defparam \D[1]~32 .lut_mask = 16'hCF05; defparam \D[1]~32 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y22_N4 -cycloneive_lcell_comb \D[1]~33 ( -// Equation(s): -// \D[1]~33_combout = ((\Equal2~0_combout & ((\D[1]~32_combout ))) # (!\Equal2~0_combout & (\D[1]~103_combout ))) # (!\Equal2~1_combout ) - - .dataa(\Equal2~0_combout ), - .datab(\Equal2~1_combout ), - .datac(\D[1]~103_combout ), - .datad(\D[1]~32_combout ), - .cin(gnd), - .combout(\D[1]~33_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~33 .lut_mask = 16'hFB73; -defparam \D[1]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y22_N8 -cycloneive_lcell_comb \D[1]~34 ( -// Equation(s): -// \D[1]~34_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\D[1]~33_combout & \z80_|data_pins_|dout [1])))) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\D[1]~33_combout )) # (!\Equal2~1_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datab(\Equal2~1_combout ), - .datac(\D[1]~33_combout ), - .datad(\z80_|data_pins_|dout [1]), - .cin(gnd), - .combout(\D[1]~34_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~34 .lut_mask = 16'hF151; -defparam \D[1]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N18 +// Location: LCCOMB_X30_Y13_N14 cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] ( // Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [1] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[1]~11_combout ) # ((\z80_|pin_control_|bus_db_pin_re~combout & \D[1]~34_combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & -// (((\z80_|pin_control_|bus_db_pin_re~combout & \D[1]~34_combout )))) +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [1] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[1]~11_combout ) # ((\D[1]~32_combout & \z80_|pin_control_|bus_db_pin_re~combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & +// (((\D[1]~32_combout & \z80_|pin_control_|bus_db_pin_re~combout )))) .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), .datab(\z80_|bus_control_|db[1]~11_combout ), - .datac(\z80_|pin_control_|bus_db_pin_re~combout ), - .datad(\D[1]~34_combout ), + .datac(\D[1]~32_combout ), + .datad(\z80_|pin_control_|bus_db_pin_re~combout ), .cin(gnd), .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [1]), .cout()); @@ -43910,7 +40644,42 @@ defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] .lut_mask = 16'hF888; defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y13_N19 +// Location: LCCOMB_X28_Y12_N16 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_re~2 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_re~2_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (((\z80_|execute_|fIORead~3_combout & \z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M1_ff~q ))) # (!\z80_|sequencer_|DFFE_T2_ff~q & +// (\z80_|execute_|fIORead~3_combout & ((\z80_|sequencer_|DFFE_T3_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|execute_|fIORead~3_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_re~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_re~2 .lut_mask = 16'hCE0A; +defparam \z80_|pin_control_|bus_db_pin_re~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N8 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_2 ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_2~combout = (\z80_|execute_|ctl_bus_db_we~7_combout ) # ((\z80_|pin_control_|bus_db_pin_re~2_combout ) # ((\z80_|execute_|fMRead~36_combout & \z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datab(\z80_|execute_|fMRead~36_combout ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|pin_control_|bus_db_pin_re~2_combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_2 .lut_mask = 16'hFFEA; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y13_N15 dffeas \z80_|data_pins_|dout[1] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [1]), @@ -43929,61 +40698,27 @@ defparam \z80_|data_pins_|dout[1] .is_wysiwyg = "true"; defparam \z80_|data_pins_|dout[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N30 -cycloneive_lcell_comb \z80_|bus_control_|db[1]~10 ( -// Equation(s): -// \z80_|bus_control_|db[1]~10_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[1]~26_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) - - .dataa(gnd), - .datab(\z80_|alu_control_|db[1]~26_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|bus_control_|db[0]~4_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[1]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[1]~10 .lut_mask = 16'hCF00; -defparam \z80_|bus_control_|db[1]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N24 +// Location: LCCOMB_X30_Y13_N28 cycloneive_lcell_comb \z80_|bus_control_|db[1]~11 ( // Equation(s): // \z80_|bus_control_|db[1]~11_combout = ((\z80_|bus_control_|db[1]~10_combout & ((\z80_|data_pins_|dout [1]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - .dataa(\z80_|execute_|ctl_bus_db_oe~combout ), - .datab(\z80_|data_pins_|dout [1]), - .datac(\z80_|bus_control_|db[1]~10_combout ), - .datad(\z80_|bus_control_|db[0]~6_combout ), + .dataa(\z80_|bus_control_|db[0]~6_combout ), + .datab(\z80_|bus_control_|db[1]~10_combout ), + .datac(\z80_|data_pins_|dout [1]), + .datad(\z80_|execute_|ctl_bus_db_oe~combout ), .cin(gnd), .combout(\z80_|bus_control_|db[1]~11_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[1]~11 .lut_mask = 16'hD0FF; +defparam \z80_|bus_control_|db[1]~11 .lut_mask = 16'hD5DD; defparam \z80_|bus_control_|db[1]~11 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N14 -cycloneive_lcell_comb \z80_|ir_|opcode[1]~feeder ( -// Equation(s): -// \z80_|ir_|opcode[1]~feeder_combout = \z80_|bus_control_|db[1]~11_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|bus_control_|db[1]~11_combout ), - .cin(gnd), - .combout(\z80_|ir_|opcode[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|ir_|opcode[1]~feeder .lut_mask = 16'hFF00; -defparam \z80_|ir_|opcode[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y12_N15 +// Location: FF_X30_Y13_N29 dffeas \z80_|ir_|opcode[1] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|ir_|opcode[1]~feeder_combout ), + .d(\z80_|bus_control_|db[1]~11_combout ), .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), @@ -43999,8110 +40734,848 @@ defparam \z80_|ir_|opcode[1] .is_wysiwyg = "true"; defparam \z80_|ir_|opcode[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y13_N18 -cycloneive_lcell_comb \z80_|pla_decode_|Equal40~0 ( +// Location: LCCOMB_X27_Y13_N0 +cycloneive_lcell_comb \z80_|pla_decode_|Equal2~0 ( // Equation(s): -// \z80_|pla_decode_|Equal40~0_combout = (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [1])) +// \z80_|pla_decode_|Equal2~0_combout = (!\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1]) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|ir_|opcode [1]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal2~0 .lut_mask = 16'h3030; +defparam \z80_|pla_decode_|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~15 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~15_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal13~0_combout & \z80_|ir_|opcode [3]))) .dataa(\z80_|ir_|opcode [0]), - .datab(gnd), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal40~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal40~0 .lut_mask = 16'h0005; -defparam \z80_|pla_decode_|Equal40~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N24 -cycloneive_lcell_comb \z80_|pla_decode_|Equal21~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal21~1_combout = (\z80_|pla_decode_|Equal21~0_combout & (\z80_|pla_decode_|Equal40~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal21~0_combout ), - .datab(\z80_|pla_decode_|Equal40~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal21~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal21~1 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal21~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~26 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~26_combout = (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|pla_decode_|Equal21~1_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T4_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~26 .lut_mask = 16'hC080; -defparam \z80_|execute_|ctl_alu_op_low~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~28 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~28_combout = (\z80_|execute_|ctl_alu_op_low~26_combout ) # ((\z80_|execute_|ctl_alu_op_low~23_combout ) # ((\z80_|execute_|ctl_alu_op_low~34_combout ) # (\z80_|execute_|ctl_alu_op_low~27_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~26_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~23_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~34_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~28 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_alu_op_low~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~3_combout = (\z80_|execute_|ctl_alu_op_low~28_combout & (\z80_|pla_decode_|Equal64~0_combout & ((\z80_|pla_decode_|Equal9~0_combout ) # (\z80_|pla_decode_|Equal3~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~28_combout ), - .datab(\z80_|pla_decode_|Equal9~0_combout ), - .datac(\z80_|pla_decode_|Equal64~0_combout ), - .datad(\z80_|pla_decode_|Equal3~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~3 .lut_mask = 16'hA080; -defparam \z80_|execute_|ctl_flags_cf_cpl~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~2_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ) # ((\z80_|execute_|ctl_mRead~36_combout & ((\z80_|execute_|ixy_d~6_combout ) # (\z80_|execute_|ctl_mRead~11_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~36_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|execute_|ctl_mRead~11_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~2 .lut_mask = 16'hFFA8; -defparam \z80_|execute_|ctl_flags_cf_cpl~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N20 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout = (!\z80_|execute_|ctl_mWrite~10_combout & (((!\z80_|pla_decode_|Equal61~2_combout & !\z80_|execute_|ctl_mWrite~16_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal61~2_combout ), - .datab(\z80_|execute_|ctl_mWrite~16_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_mWrite~10_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 .lut_mask = 16'h001F; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N2 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout = (\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_state_alu~5_combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|execute_|ctl_mRead~36_combout )))) # (!\z80_|pla_decode_|Equal56~0_combout & -// (((!\z80_|nM1_int~2_combout )) # (!\z80_|execute_|ctl_mRead~36_combout ))) - - .dataa(\z80_|pla_decode_|Equal56~0_combout ), - .datab(\z80_|execute_|ctl_mRead~36_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_state_alu~5_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 .lut_mask = 16'h153F; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N28 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout = (\z80_|execute_|ctl_alu_core_R~4_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_R~4_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 .lut_mask = 16'h8000; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N16 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~6_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~5_combout & !\z80_|execute_|ctl_alu_sel_op2_neg~16_combout )) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 .lut_mask = 16'h0088; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N22 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout = (!\z80_|execute_|ctl_alu_core_R~1_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout & (\z80_|execute_|ctl_alu_core_S~7_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_R~1_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ), - .datac(\z80_|execute_|ctl_alu_core_S~7_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 .lut_mask = 16'h4000; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N18 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout & (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout & ((!\z80_|execute_|ctl_alu_op_low~27_combout ) # (!\z80_|execute_|ctl_flags_cf_cpl~2_combout )))) - - .dataa(\z80_|execute_|ctl_flags_cf_cpl~2_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), - .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 .lut_mask = 16'h040C; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N30 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~21 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~21_combout = (((!\z80_|pla_decode_|Equal40~1_combout & !\z80_|pla_decode_|Equal39~0_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|pla_decode_|Equal40~1_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~21 .lut_mask = 16'h777F; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N26 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout = (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~21_combout & ((\z80_|execute_|ctl_alu_op_low~23_combout ) # (\z80_|execute_|ctl_alu_op_low~27_combout ))) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op_low~23_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~21_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 .lut_mask = 16'h0F0C; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N4 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout = (\z80_|pla_decode_|Equal21~1_combout & ((\z80_|execute_|ixy_d~6_combout ) # ((\z80_|sequencer_|DFFE_T5_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 .lut_mask = 16'hC0E0; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N28 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout & ((\z80_|execute_|ctl_alu_op_low~23_combout ) # ((\z80_|execute_|ctl_alu_op_low~34_combout ) # (\z80_|execute_|ctl_alu_op_low~27_combout )))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~23_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~34_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 .lut_mask = 16'hAAA8; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N0 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout = (\z80_|execute_|ctl_flags_nf_we~1_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout & (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout & !\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ))) - - .dataa(\z80_|execute_|ctl_flags_nf_we~1_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 .lut_mask = 16'h0008; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N22 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~22_combout & (\z80_|execute_|ctl_flags_sz_we~4_combout & ((!\z80_|pla_decode_|Equal9~0_combout ) # (!\z80_|pla_decode_|Equal62~2_combout )))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~22_combout ), - .datab(\z80_|pla_decode_|Equal62~2_combout ), - .datac(\z80_|execute_|ctl_flags_sz_we~4_combout ), - .datad(\z80_|pla_decode_|Equal9~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17 .lut_mask = 16'h20A0; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~32 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~32_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|pla_decode_|Equal10~0_combout )) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal10~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~32 .lut_mask = 16'h8800; -defparam \z80_|execute_|ctl_alu_op_low~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N18 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|pla_decode_|Equal21~0_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal63~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal21~0_combout ), - .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|pla_decode_|Equal63~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 .lut_mask = 16'hCECC; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N20 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout = (\z80_|execute_|ctl_alu_op_low~32_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~32_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 .lut_mask = 16'hFFEF; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N24 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout = ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ) # ((\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & \z80_|execute_|ctl_alu_op_low~20_combout ))) # (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ) - - .dataa(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~20_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18 .lut_mask = 16'hFFB3; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N0 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~19 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~19_combout = (\z80_|execute_|ctl_state_alu~12_combout & ((\z80_|ir_|opcode [3] & (\z80_|ir_|opcode [4] & \z80_|ir_|opcode [5])) # (!\z80_|ir_|opcode [3] & ((!\z80_|ir_|opcode [5]))))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|execute_|ctl_state_alu~12_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~19 .lut_mask = 16'h8500; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N10 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~0 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[0]~19_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[7]~21_combout )) - - .dataa(\z80_|alu_|db[7]~21_combout ), - .datab(gnd), - .datac(\z80_|alu_|db[0]~19_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~0 .lut_mask = 16'hF0AA; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N28 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~1 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_control_|out[6]~2_combout )) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .datab(gnd), - .datac(\z80_|alu_control_|out[6]~2_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~1 .lut_mask = 16'hFA50; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N18 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~2 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout & ((!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout )))) # (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout -// & ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (!\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ))))) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~2 .lut_mask = 16'h11D8; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N30 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~3 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout = (\z80_|execute_|ctl_flags_cf2_we~3_combout & (\z80_|execute_|ctl_flags_cf2_sel_daa~combout $ ((!\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout )))) # (!\z80_|execute_|ctl_flags_cf2_we~3_combout & -// ((\z80_|alu_flags_|DFFE_inst_latch_cf2~q ) # ((\z80_|execute_|ctl_flags_cf2_sel_daa~combout & \z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout )))) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), - .datad(\z80_|execute_|ctl_flags_cf2_we~3_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~3 .lut_mask = 16'h99F8; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y9_N31 -dffeas \z80_|alu_flags_|DFFE_inst_latch_cf2 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2 .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~10_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal11~0_combout & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_M1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|pla_decode_|Equal11~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~10 .lut_mask = 16'h0B00; -defparam \z80_|execute_|ctl_flags_use_cf2~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~11_combout = (\z80_|execute_|ctl_flags_use_cf2~10_combout ) # ((\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # ((\z80_|pla_decode_|Equal10~0_combout & \z80_|execute_|ixy_d~7_combout ))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|execute_|ctl_flags_use_cf2~10_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~11 .lut_mask = 16'hFFEC; -defparam \z80_|execute_|ctl_flags_use_cf2~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~8_combout = (\z80_|execute_|ctl_ir_we~8_combout ) # ((\z80_|pla_decode_|Equal20~0_combout ) # (\z80_|execute_|ctl_ir_we~14_combout )) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal20~0_combout ), - .datad(\z80_|execute_|ctl_ir_we~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~8 .lut_mask = 16'hFFFA; -defparam \z80_|execute_|ctl_flags_use_cf2~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~9_combout = (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_flags_use_cf2~8_combout ) # ((\z80_|pla_decode_|Equal9~0_combout & \z80_|pla_decode_|Equal63~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal9~0_combout ), - .datab(\z80_|pla_decode_|Equal63~0_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|execute_|ctl_flags_use_cf2~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~9 .lut_mask = 16'h0F08; -defparam \z80_|execute_|ctl_flags_use_cf2~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~12 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~12_combout = (\z80_|execute_|ctl_flags_use_cf2~11_combout ) # (((\z80_|execute_|ctl_flags_use_cf2~9_combout ) # (\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout )) # (!\z80_|execute_|ctl_flags_use_cf2~13_combout )) - - .dataa(\z80_|execute_|ctl_flags_use_cf2~11_combout ), - .datab(\z80_|execute_|ctl_flags_use_cf2~13_combout ), - .datac(\z80_|execute_|ctl_flags_use_cf2~9_combout ), - .datad(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~12 .lut_mask = 16'hFFFB; -defparam \z80_|execute_|ctl_flags_use_cf2~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N16 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout = (\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & (((\z80_|alu_flags_|DFFE_inst_latch_cf2~q )))) # (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & ((\z80_|execute_|ctl_flags_use_cf2~12_combout & -// ((\z80_|alu_flags_|DFFE_inst_latch_cf2~q ))) # (!\z80_|execute_|ctl_flags_use_cf2~12_combout & (\z80_|alu_flags_|DFFE_inst_latch_cf~q )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), - .datad(\z80_|execute_|ctl_flags_use_cf2~12_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 .lut_mask = 16'hF0E4; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N22 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~20 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~20_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~19_combout & \z80_|execute_|ctl_alu_op_low~28_combout ))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~19_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~28_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~20 .lut_mask = 16'hFEFA; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~10_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ) # ((!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|execute_|ctl_alu_op_low~12_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|execute_|ctl_alu_op_low~12_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~10 .lut_mask = 16'hFF40; -defparam \z80_|execute_|ctl_flags_cf_cpl~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~8_combout = (\z80_|execute_|ctl_flags_cf_cpl~10_combout ) # ((\z80_|execute_|ctl_alu_op_low~12_combout & (\z80_|execute_|ctl_alu_op_low~8_combout & \z80_|execute_|ctl_alu_op_low~19_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), - .datab(\z80_|execute_|ctl_flags_cf_cpl~10_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~8 .lut_mask = 16'hECCC; -defparam \z80_|execute_|ctl_flags_cf_cpl~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~5_combout = ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_alu_op_low~12_combout ) # (\z80_|execute_|ctl_state_alu~7_combout )))) # (!\z80_|execute_|ctl_state_alu~15_combout ) - - .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), - .datab(\z80_|execute_|ctl_state_alu~15_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|execute_|ctl_state_alu~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~5 .lut_mask = 16'h3F3B; -defparam \z80_|execute_|ctl_flags_cf_cpl~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~6_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_flags_cf_cpl~5_combout ) # ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal68~2_combout )))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|pla_decode_|Equal68~2_combout ), - .datad(\z80_|execute_|ctl_flags_cf_cpl~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~6 .lut_mask = 16'hAA20; -defparam \z80_|execute_|ctl_flags_cf_cpl~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~7_combout = (\z80_|execute_|ctl_flags_cf_cpl~6_combout ) # ((!\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # (\z80_|execute_|ctl_flags_cf2_sel_daa~combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datad(\z80_|execute_|ctl_flags_cf_cpl~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~7 .lut_mask = 16'hFF32; -defparam \z80_|execute_|ctl_flags_cf_cpl~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_set~0 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_set~0_combout = (\z80_|execute_|ctl_state_alu~12_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal9~0_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~12_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal9~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_set~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_set~0 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_flags_cf_set~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~4_combout = (\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout & ((\z80_|execute_|ctl_alu_op_low~19_combout ) # (!\z80_|execute_|ctl_alu_op_low~33_combout ))) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), - .datac(\z80_|execute_|ctl_alu_op_low~19_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~33_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~4 .lut_mask = 16'hC0CC; -defparam \z80_|execute_|ctl_flags_cf_cpl~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~9_combout = (\z80_|execute_|ctl_flags_cf_cpl~8_combout ) # ((\z80_|execute_|ctl_flags_cf_cpl~7_combout ) # ((\z80_|execute_|ctl_flags_cf_set~0_combout ) # (\z80_|execute_|ctl_flags_cf_cpl~4_combout ))) - - .dataa(\z80_|execute_|ctl_flags_cf_cpl~8_combout ), - .datab(\z80_|execute_|ctl_flags_cf_cpl~7_combout ), - .datac(\z80_|execute_|ctl_flags_cf_set~0_combout ), - .datad(\z80_|execute_|ctl_flags_cf_cpl~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~9 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_flags_cf_cpl~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N4 -cycloneive_lcell_comb \z80_|alu_flags_|flags_cf ( -// Equation(s): -// \z80_|alu_flags_|flags_cf~combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~20_combout $ (((\z80_|execute_|ctl_flags_cf_cpl~3_combout ) # (\z80_|execute_|ctl_flags_cf_cpl~9_combout ))))) - - .dataa(\z80_|execute_|ctl_flags_cf_cpl~3_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~20_combout ), - .datad(\z80_|execute_|ctl_flags_cf_cpl~9_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|flags_cf~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_cf .lut_mask = 16'h0C48; -defparam \z80_|alu_flags_|flags_cf .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N2 -cycloneive_lcell_comb \z80_|alu_control_|db[0]~8 ( -// Equation(s): -// \z80_|alu_control_|db[0]~8_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & (((\z80_|bus_control_|db[0]~17_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) - - .dataa(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .datab(\z80_|execute_|ctl_sw_1d~7_combout ), - .datac(\z80_|bus_control_|db[0]~17_combout ), - .datad(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[0]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[0]~8 .lut_mask = 16'h22A2; -defparam \z80_|alu_control_|db[0]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N20 -cycloneive_lcell_comb \z80_|sw2_|db_up[0]~0 ( -// Equation(s): -// \z80_|sw2_|db_up[0]~0_combout = (\z80_|alu_|db[0]~19_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_sw_2u~7_combout ), - .datad(\z80_|alu_|db[0]~19_combout ), - .cin(gnd), - .combout(\z80_|sw2_|db_up[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sw2_|db_up[0]~0 .lut_mask = 16'hFF0F; -defparam \z80_|sw2_|db_up[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N4 -cycloneive_lcell_comb \z80_|alu_control_|db[0]~9 ( -// Equation(s): -// \z80_|alu_control_|db[0]~9_combout = (\z80_|alu_control_|db[0]~8_combout & (\z80_|sw2_|db_up[0]~0_combout & ((\z80_|reg_file_|gdfx_temp0[0]~22_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) - - .dataa(\z80_|alu_control_|db[0]~8_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .datac(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datad(\z80_|sw2_|db_up[0]~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[0]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[0]~9 .lut_mask = 16'h8A00; -defparam \z80_|alu_control_|db[0]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N26 -cycloneive_lcell_comb \z80_|alu_control_|db[0]~12 ( -// Equation(s): -// \z80_|alu_control_|db[0]~12_combout = ((\z80_|alu_control_|db[0]~9_combout & ((\z80_|alu_flags_|flags_cf~combout ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|alu_flags_|flags_cf~combout ), - .datab(\z80_|execute_|ctl_flags_oe~2_combout ), - .datac(\z80_|alu_control_|db[0]~9_combout ), - .datad(\z80_|alu_control_|db[6]~11_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[0]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[0]~12 .lut_mask = 16'hB0FF; -defparam \z80_|alu_control_|db[0]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~67 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][0]~67_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [4])) - - .dataa(\ula_|zx_keyboard_|shifted~q ), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][0]~67_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][0]~67 .lut_mask = 16'hFF50; -defparam \ula_|zx_keyboard_|keys[5][0]~67 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~81 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][0]~81_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [3]))) # (!\ula_|ps2_keyboard_|shiftreg [1] & -// (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][0]~81_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][0]~81 .lut_mask = 16'h0420; -defparam \ula_|zx_keyboard_|keys[5][0]~81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~82 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][0]~82_combout = (\ula_|zx_keyboard_|keys[5][0]~81_combout & (\ula_|zx_keyboard_|keys[6][1]~41_combout & (\ula_|ps2_keyboard_|shiftreg [2] $ (\ula_|ps2_keyboard_|shiftreg [4])))) - - .dataa(\ula_|zx_keyboard_|keys[5][0]~81_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|keys[6][1]~41_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][0]~82_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][0]~82 .lut_mask = 16'h2800; -defparam \ula_|zx_keyboard_|keys[5][0]~82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~83 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][0]~83_combout = (\ula_|zx_keyboard_|keys[5][0]~82_combout & (!\ula_|zx_keyboard_|keys[5][0]~67_combout )) # (!\ula_|zx_keyboard_|keys[5][0]~82_combout & ((\ula_|zx_keyboard_|keys[5][0]~q ))) - - .dataa(\ula_|zx_keyboard_|keys[5][0]~67_combout ), - .datab(\ula_|zx_keyboard_|keys[5][0]~82_combout ), - .datac(\ula_|zx_keyboard_|keys[5][0]~q ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][0]~83_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][0]~83 .lut_mask = 16'h7474; -defparam \ula_|zx_keyboard_|keys[5][0]~83 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y20_N11 -dffeas \ula_|zx_keyboard_|keys[5][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[5][0]~83_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[5][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[5][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~84 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][0]~84_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [5] $ (\ula_|ps2_keyboard_|shiftreg [3])))) # (!\ula_|ps2_keyboard_|shiftreg [1] & -// (!\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [0]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [5]), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][0]~84_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][0]~84 .lut_mask = 16'h0160; -defparam \ula_|zx_keyboard_|keys[4][0]~84 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~85 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][0]~85_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [3])) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|shifted~q ), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][0]~85_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][0]~85 .lut_mask = 16'hBABA; -defparam \ula_|zx_keyboard_|keys[4][0]~85 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~86 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][0]~86_combout = (\ula_|zx_keyboard_|keys[5][1]~37_combout & ((\ula_|zx_keyboard_|keys[4][0]~84_combout & ((!\ula_|zx_keyboard_|keys[4][0]~85_combout ))) # (!\ula_|zx_keyboard_|keys[4][0]~84_combout & -// (\ula_|zx_keyboard_|keys[4][0]~q )))) # (!\ula_|zx_keyboard_|keys[5][1]~37_combout & (((\ula_|zx_keyboard_|keys[4][0]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[5][1]~37_combout ), - .datab(\ula_|zx_keyboard_|keys[4][0]~84_combout ), - .datac(\ula_|zx_keyboard_|keys[4][0]~q ), - .datad(\ula_|zx_keyboard_|keys[4][0]~85_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][0]~86_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][0]~86 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[4][0]~86 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y18_N27 -dffeas \ula_|zx_keyboard_|keys[4][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[4][0]~86_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[4][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[4][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N20 -cycloneive_lcell_comb \D[0]~49 ( -// Equation(s): -// \D[0]~49_combout = (\z80_|address_pins_|abus[13]~20_combout & (((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][0]~q )))) # (!\z80_|address_pins_|abus[13]~20_combout & (!\ula_|zx_keyboard_|keys[5][0]~q & -// ((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][0]~q )))) - - .dataa(\z80_|address_pins_|abus[13]~20_combout ), - .datab(\ula_|zx_keyboard_|keys[5][0]~q ), - .datac(\ula_|zx_keyboard_|keys[4][0]~q ), - .datad(\z80_|address_pins_|abus[12]~21_combout ), - .cin(gnd), - .combout(\D[0]~49_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~49 .lut_mask = 16'hBB0B; -defparam \D[0]~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr4~0 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr4~0_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [5] & ((\ula_|ps2_keyboard_|shiftreg [6])))) # (!\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [5] & -// (\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [6]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr4~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr4~0 .lut_mask = 16'h8810; -defparam \ula_|zx_keyboard_|WideOr4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys~76 ( -// Equation(s): -// \ula_|zx_keyboard_|keys~76_combout = (!\ula_|zx_keyboard_|extended~q & (((\ula_|ps2_keyboard_|shiftreg [3]) # (!\ula_|zx_keyboard_|keys[4][1]~31_combout )) # (!\ula_|zx_keyboard_|WideOr4~0_combout ))) - - .dataa(\ula_|zx_keyboard_|WideOr4~0_combout ), - .datab(\ula_|zx_keyboard_|extended~q ), - .datac(\ula_|zx_keyboard_|keys[4][1]~31_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys~76_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys~76 .lut_mask = 16'h3313; -defparam \ula_|zx_keyboard_|keys~76 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~73 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~73_combout = (\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [6]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][3]~73_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~73 .lut_mask = 16'hF000; -defparam \ula_|zx_keyboard_|keys[4][3]~73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~47 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][4]~47_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [2])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][4]~47_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][4]~47 .lut_mask = 16'h0808; -defparam \ula_|zx_keyboard_|keys[6][4]~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr0~0 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr0~0_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [2])) # (!\ula_|ps2_keyboard_|shiftreg [1] & -// ((\ula_|ps2_keyboard_|shiftreg [2]))))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [0]), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr0~0 .lut_mask = 16'h0310; -defparam \ula_|zx_keyboard_|WideOr0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys~74 ( -// Equation(s): -// \ula_|zx_keyboard_|keys~74_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (((!\ula_|zx_keyboard_|WideOr0~0_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [4] & (((!\ula_|ps2_keyboard_|shiftreg [3])) # (!\ula_|zx_keyboard_|keys[6][4]~47_combout ))) - - .dataa(\ula_|zx_keyboard_|keys[6][4]~47_combout ), - .datab(\ula_|zx_keyboard_|WideOr0~0_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys~74_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys~74 .lut_mask = 16'h353F; -defparam \ula_|zx_keyboard_|keys~74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~75 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][0]~75_combout = (\ula_|zx_keyboard_|keys[0][0]~15_combout & (((\ula_|zx_keyboard_|keys[4][3]~73_combout & !\ula_|zx_keyboard_|keys~74_combout )) # (!\ula_|zx_keyboard_|extended~q ))) - - .dataa(\ula_|zx_keyboard_|keys[4][3]~73_combout ), - .datab(\ula_|zx_keyboard_|keys~74_combout ), - .datac(\ula_|zx_keyboard_|extended~q ), - .datad(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][0]~75_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][0]~75 .lut_mask = 16'h2F00; -defparam \ula_|zx_keyboard_|keys[0][0]~75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~77 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][0]~77_combout = (\ula_|zx_keyboard_|keys~76_combout & (((\ula_|zx_keyboard_|keys[0][0]~q )))) # (!\ula_|zx_keyboard_|keys~76_combout & ((\ula_|zx_keyboard_|keys[0][0]~75_combout & ((!\ula_|zx_keyboard_|released~q ))) # -// (!\ula_|zx_keyboard_|keys[0][0]~75_combout & (\ula_|zx_keyboard_|keys[0][0]~q )))) - - .dataa(\ula_|zx_keyboard_|keys~76_combout ), - .datab(\ula_|zx_keyboard_|keys[0][0]~75_combout ), - .datac(\ula_|zx_keyboard_|keys[0][0]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][0]~77_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][0]~77 .lut_mask = 16'hB0F4; -defparam \ula_|zx_keyboard_|keys[0][0]~77 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y20_N15 -dffeas \ula_|zx_keyboard_|keys[0][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[0][0]~77_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[0][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[0][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][0]~71 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][0]~71_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[1][4]~25_combout & !\ula_|ps2_keyboard_|shiftreg [5]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [0]), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|zx_keyboard_|keys[1][4]~25_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][0]~71_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][0]~71 .lut_mask = 16'h0040; -defparam \ula_|zx_keyboard_|keys[1][0]~71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][0]~72 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][0]~72_combout = (\ula_|zx_keyboard_|keys[1][0]~71_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[1][0]~71_combout & (\ula_|zx_keyboard_|keys[1][0]~q )) - - .dataa(gnd), - .datab(\ula_|zx_keyboard_|keys[1][0]~71_combout ), - .datac(\ula_|zx_keyboard_|keys[1][0]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][0]~72_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][0]~72 .lut_mask = 16'h30FC; -defparam \ula_|zx_keyboard_|keys[1][0]~72 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y19_N17 -dffeas \ula_|zx_keyboard_|keys[1][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[1][0]~72_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[1][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[1][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N30 -cycloneive_lcell_comb \D[0]~47 ( -// Equation(s): -// \D[0]~47_combout = (\ula_|zx_keyboard_|keys[0][0]~q & (\z80_|address_pins_|abus[8]~18_combout & ((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][0]~q )))) # (!\ula_|zx_keyboard_|keys[0][0]~q & -// (((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][0]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[0][0]~q ), - .datab(\z80_|address_pins_|abus[8]~18_combout ), - .datac(\z80_|address_pins_|abus[9]~17_combout ), - .datad(\ula_|zx_keyboard_|keys[1][0]~q ), - .cin(gnd), - .combout(\D[0]~47_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~47 .lut_mask = 16'hD0DD; -defparam \D[0]~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][0]~80 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][0]~80_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (((\ula_|zx_keyboard_|keys[2][0]~q )))) # (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[2][1]~26_combout & (!\ula_|zx_keyboard_|released~q )) # -// (!\ula_|zx_keyboard_|keys[2][1]~26_combout & ((\ula_|zx_keyboard_|keys[2][0]~q ))))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[2][0]~q ), - .datad(\ula_|zx_keyboard_|keys[2][1]~26_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][0]~80_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][0]~80 .lut_mask = 16'hB1F0; -defparam \ula_|zx_keyboard_|keys[2][0]~80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y20_N23 -dffeas \ula_|zx_keyboard_|keys[2][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[2][0]~80_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[2][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[2][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][0]~78 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][0]~78_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [0])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][0]~78_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][0]~78 .lut_mask = 16'h000A; -defparam \ula_|zx_keyboard_|keys[3][0]~78 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][0]~79 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][0]~79_combout = (\ula_|zx_keyboard_|keys[3][0]~78_combout & ((\ula_|zx_keyboard_|keys[3][1]~28_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[3][1]~28_combout & (\ula_|zx_keyboard_|keys[3][0]~q -// )))) # (!\ula_|zx_keyboard_|keys[3][0]~78_combout & (((\ula_|zx_keyboard_|keys[3][0]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[3][0]~78_combout ), - .datab(\ula_|zx_keyboard_|keys[3][1]~28_combout ), - .datac(\ula_|zx_keyboard_|keys[3][0]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][0]~79_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][0]~79 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[3][0]~79 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y20_N5 -dffeas \ula_|zx_keyboard_|keys[3][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[3][0]~79_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[3][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[3][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~1 ( -// Equation(s): -// \ula_|zx_keyboard_|key_row~1_combout = ((\z80_|address_pins_|DFFE_apin_latch [11]) # (!\ula_|zx_keyboard_|keys[3][0]~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\ula_|zx_keyboard_|keys[3][0]~q ), - .datad(\z80_|address_pins_|DFFE_apin_latch [11]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|key_row~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|key_row~1 .lut_mask = 16'hFF3F; -defparam \ula_|zx_keyboard_|key_row~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N4 -cycloneive_lcell_comb \D[0]~48 ( -// Equation(s): -// \D[0]~48_combout = (\D[0]~47_combout & (\ula_|zx_keyboard_|key_row~1_combout & ((\z80_|address_pins_|abus[10]~24_combout ) # (!\ula_|zx_keyboard_|keys[2][0]~q )))) - - .dataa(\D[0]~47_combout ), - .datab(\z80_|address_pins_|abus[10]~24_combout ), - .datac(\ula_|zx_keyboard_|keys[2][0]~q ), - .datad(\ula_|zx_keyboard_|key_row~1_combout ), - .cin(gnd), - .combout(\D[0]~48_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~48 .lut_mask = 16'h8A00; -defparam \D[0]~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~1 ( -// Equation(s): -// \ula_|zx_keyboard_|shifted~1_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [4]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|shifted~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|shifted~1 .lut_mask = 16'h0F00; -defparam \ula_|zx_keyboard_|shifted~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~90 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][0]~90_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][0]~90_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][0]~90 .lut_mask = 16'h0200; -defparam \ula_|zx_keyboard_|keys[6][0]~90 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~91 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][0]~91_combout = (\ula_|zx_keyboard_|shifted~1_combout & (\ula_|zx_keyboard_|keys[7][1]~23_combout & (\ula_|zx_keyboard_|keys[6][0]~90_combout & \ula_|ps2_keyboard_|shiftreg [1]))) - - .dataa(\ula_|zx_keyboard_|shifted~1_combout ), - .datab(\ula_|zx_keyboard_|keys[7][1]~23_combout ), - .datac(\ula_|zx_keyboard_|keys[6][0]~90_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][0]~91_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][0]~91 .lut_mask = 16'h8000; -defparam \ula_|zx_keyboard_|keys[6][0]~91 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~92 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][0]~92_combout = (\ula_|zx_keyboard_|keys[6][0]~91_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[6][0]~91_combout & ((\ula_|zx_keyboard_|keys[6][0]~q ))) - - .dataa(gnd), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[6][0]~q ), - .datad(\ula_|zx_keyboard_|keys[6][0]~91_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][0]~92_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][0]~92 .lut_mask = 16'h33F0; -defparam \ula_|zx_keyboard_|keys[6][0]~92 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y20_N21 -dffeas \ula_|zx_keyboard_|keys[6][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[6][0]~92_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[6][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[6][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y21_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~63 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][4]~63_combout = (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [0]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][4]~63_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][4]~63 .lut_mask = 16'h0F00; -defparam \ula_|zx_keyboard_|keys[5][4]~63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y21_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~3 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~3_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [2]) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~3 .lut_mask = 16'h0303; -defparam \ula_|zx_keyboard_|WideOr16~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y21_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~87 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][0]~87_combout = (\ula_|zx_keyboard_|keys[5][4]~63_combout & (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|WideOr16~3_combout ))) - - .dataa(\ula_|zx_keyboard_|keys[5][4]~63_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|WideOr16~3_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][0]~87_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][0]~87 .lut_mask = 16'h0800; -defparam \ula_|zx_keyboard_|keys[7][0]~87 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~132 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][0]~132_combout = (\ula_|zx_keyboard_|keys[3][0]~78_combout & (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [4]))) - - .dataa(\ula_|zx_keyboard_|keys[3][0]~78_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][0]~132_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][0]~132 .lut_mask = 16'h8000; -defparam \ula_|zx_keyboard_|keys[7][0]~132 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y21_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~88 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][0]~88_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|zx_keyboard_|keys[7][1]~23_combout & ((\ula_|zx_keyboard_|keys[7][0]~87_combout ) # (\ula_|zx_keyboard_|keys[7][0]~132_combout )))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [5]), - .datab(\ula_|zx_keyboard_|keys[7][1]~23_combout ), - .datac(\ula_|zx_keyboard_|keys[7][0]~87_combout ), - .datad(\ula_|zx_keyboard_|keys[7][0]~132_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][0]~88_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][0]~88 .lut_mask = 16'h8880; -defparam \ula_|zx_keyboard_|keys[7][0]~88 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~89 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][0]~89_combout = (\ula_|zx_keyboard_|keys[7][0]~88_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[7][0]~88_combout & (\ula_|zx_keyboard_|keys[7][0]~q )) - - .dataa(\ula_|zx_keyboard_|keys[7][0]~88_combout ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[7][0]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][0]~89_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][0]~89 .lut_mask = 16'h50FA; -defparam \ula_|zx_keyboard_|keys[7][0]~89 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y20_N7 -dffeas \ula_|zx_keyboard_|keys[7][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[7][0]~89_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[7][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[7][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N28 -cycloneive_lcell_comb \D[0]~50 ( -// Equation(s): -// \D[0]~50_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\z80_|address_pins_|abus[15]~22_combout ) # (!\ula_|zx_keyboard_|keys[7][0]~q )))) # (!\z80_|address_pins_|abus[14]~23_combout & (!\ula_|zx_keyboard_|keys[6][0]~q & -// ((\z80_|address_pins_|abus[15]~22_combout ) # (!\ula_|zx_keyboard_|keys[7][0]~q )))) - - .dataa(\z80_|address_pins_|abus[14]~23_combout ), - .datab(\ula_|zx_keyboard_|keys[6][0]~q ), - .datac(\z80_|address_pins_|abus[15]~22_combout ), - .datad(\ula_|zx_keyboard_|keys[7][0]~q ), - .cin(gnd), - .combout(\D[0]~50_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~50 .lut_mask = 16'hB0BB; -defparam \D[0]~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N10 -cycloneive_lcell_comb \D[0]~51 ( -// Equation(s): -// \D[0]~51_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[0]~49_combout & (\D[0]~48_combout & \D[0]~50_combout ))) - - .dataa(\D[0]~49_combout ), - .datab(\z80_|address_pins_|abus[0]~16_combout ), - .datac(\D[0]~48_combout ), - .datad(\D[0]~50_combout ), - .cin(gnd), - .combout(\D[0]~51_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~51 .lut_mask = 16'hECCC; -defparam \D[0]~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y16_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a24 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[0]~58_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_first_bit_number = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y14_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a16 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[0]~58_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_first_bit_number = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y13_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a0 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[0]~58_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N14 -cycloneive_lcell_comb \D[0]~55 ( -// Equation(s): -// \D[0]~55_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & -// ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout )) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & -// ((\ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ))))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ), - .cin(gnd), - .combout(\D[0]~55_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~55 .lut_mask = 16'hE3E0; -defparam \D[0]~55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y13_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a8 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[0]~58_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N22 -cycloneive_lcell_comb \D[0]~56 ( -// Equation(s): -// \D[0]~56_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[0]~55_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout )) # (!\D[0]~55_combout & -// ((\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ))))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[0]~55_combout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\D[0]~55_combout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ), - .cin(gnd), - .combout(\D[0]~56_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~56 .lut_mask = 16'hBCB0; -defparam \D[0]~56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y28_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a0 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[0]~58_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_bit_number = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF0000000000000000000000003FF03FFC20107FFC3FF00B9C3FF007FC18000FFC3FF03FD42FF43FFC2FFC3FE01FFE7FE81FFE3FDC07FE3FFC07FE2FFC07FE0F0807FE1F18207F0F3030FD8C30383300600000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h000000000000000000000000FFFFFFFFE0408103E004044390120EAA803920C6000000000000000000000000FFFFFFFFE0408103A004005A84723CEA813930C2000000000000000000000000800000009FBF7EFD8004027A8572358A813950EA000000000000000000000000800000009FBF7EFC8005157A85733F0A8139518E0000000000000000000000009FBF7EFC800000008006113A8C73330A813919EA0000000000000000000000009FBF7EFC8000000080060022801333A2813973EA00000000000000000000000080000000DFFFFFFD9FF6022A84730366801913FE000000000000000000000000E0408102FFFFFFFD9FF60ABA84730426901913EE; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h9FF81326887812F28FF0D7C2CC6856E3894C8B62980099E28988BFC2B9EC79829FE81362887842E68FF0C7C2CCE056E2896C89E2888098E28AA8BBC299FC1AC280081372887842E69EE0C7CA8CE046E289E089E289C899E28AA8BEC2993C1AE28008837E882852C69EE0874288E046E2886099E289689FCE8AD8BFC2999C09F680088376880846C69CA88382880042A289D08DE289F098C28AF8BFC289FC88F280088376880857C29CA893C2888043A289508DE288F0D9428BF0AFC289F4888A800883F2880857829C2891C3889047F2898885E2899081428990AF8289FC8BE3800893F6880847C2DC0894E389944F62888899668918914289803582CB8C8AF3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'hCBAC80F38DA845828DF44582840124029375A4A288D108A2FFFFFFFDE0408082CAEC80968DF855828CE4408284012006917194C280510B82DFFFFFFC8000000288EC84A28FFC4586880C648A860124128179900280510F82800000009FBF7F7C8BA080BA8FEC40828808618286012C028179901280510702800000009FBF7F7C8BB081BA8CAC408289E0618286812C1281791002805007029FBF7F7C8000000089B881828CB440828BE07782868322028139909280400F029FBF7F7D8000000089A4C3928FF444828A00260A8792227281199022A0001F03E0408081FFFFFFFF89A0C1928FD440828800260687B720C280199002E0001F03E0408083FFFFFFFF; -// synopsys translate_on - -// Location: M9K_X22_Y30_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a8 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h3C00000000000000000000000000000000000000000000000000000000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005DB824E17CAAE881C1908A79F24B7D1B4857A981A6AF39DFF5A2FEE9141EB33592D8E9B82471FDDA6791810A1C29D415CC1A8FA03444DF0083F83506BA93E8D1A1856A768D73A08418BFB25A40001DD4833DAF33BD311BB45F39667627407EF59ED569C483EB3BE1B10551B1428A6169579293ED063CAA9C6ADB0433CFC15C33AFF04C710408C20AC28B5909A229CD7D1DB4EB9A44CE0EEDBBBD391D3128AAA3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'hDDE6FC8EBE3F9F3C3DFC6E8F07BFD31D50660B1E0B2506A533CE0E340C7C745CAEC4837C2A5FECBB94C1C969FFDDFF79BFFAAFDCA8D748399ABF75558ADD02F56F6DFFF29CB70FFD25A59DFFFED7B3F7E8B4CE6FFF3EF9CEC6BAE57ABFFFCEE647B2AFF5B87AA26AFFDD317DEDCFBDFFE1A0CAD3B58877DD2F647F7DF748E7CF4693FD3C1238FFAFBD7FDF567FA8FEF024F33AFD3AABC6B105EA80272D64895FFF9FFF6E3881C81AFDCF2257FD4F8ED5257D0E9B800726B6564D2B05012F76DF636CDEB4BDFCAEEFC61DFFEFB7E26262DEF2CB9F71565824FEBF3F7BDDEABB593F1BF746FBFFC353E37263FF38A796EF39E3FD7DFEBA7FFEFFBD97ABAF09E909; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'hE629BDF93D7F5B5BAF92FBAB477E9B315DB5A310CFACC7408DF9A544B1E57AF6EFEF92C2FA4D8D4E4AC86C277338FA37BCDD9D47782DB75EFF80781BCD23D0AFCAE30B9FE6AA29FFF6F72DA73DFE4F7ACD39687B9E69C5359E9B991F0246EFFBC5595561AC64787878F5CE14C664CF9EB0CDAFFBABEF1E83358371B9ED96E5069555AFBBD3AEBFCABFBBED7A5C5FE9BD0E6A91C6E7610042695EEB08D8881B1D735AF87DAE59FABBD7DEAF8717F2B72F428F5E37E5D6E13157B99CBD2D73B9C73C563C8B02C8CC39C64DDCEA1BEEB5E7353F93786145598FE634EF1000179B345725EA43CE18F187A1DE4DAABEA97963E3A7A96B8B7CBC095BEB7CE46274D9AF; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h4ED4AE2B1650D21EAFE01E7099EFCA3094FD4D705CF6B84AE21583E13385F8650004406BD60A023AB063D4E5966EA41AA997F5A49BFCB0657A9732D28EB8217E65F627A15E1057ADEE7B9E27122A58FB2B98B1EA560390C7E87715861814E04DCB76FAB179E9619BC7E7E9C9FD801CF87DBA1EA496E829D4E62861E1AF436A7585287860729C77B6C68CAEA3033A6E84D67249B594C407B39C68B4C1C97FDEFC6BAD12FDBB525EF4F87F4A23EC13CBC0262D8899A3A290F04F41C1324045B9FCEEC890579E95D5A0A546CCCDD48577558ABE7CA36EF67A70F6A8758BDA052D5B95DE707778B17C2379847A23AE5D4BB01F36F3F44A8162566D9FB15DE7CC83F7; -// synopsys translate_on - -// Location: M9K_X22_Y27_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a8 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(gnd), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[0]~58_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_first_bit_number = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N4 -cycloneive_lcell_comb \D[0]~52 ( -// Equation(s): -// \D[0]~52_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\z80_|address_pins_|abus[14]~23_combout & ((\ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ))) # (!\z80_|address_pins_|abus[14]~23_combout & -// (\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\z80_|address_pins_|abus[14]~23_combout )))) - - .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ), - .datac(\z80_|address_pins_|abus[14]~23_combout ), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ), - .cin(gnd), - .combout(\D[0]~52_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~52 .lut_mask = 16'hF858; -defparam \D[0]~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y20_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a0 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h1EEA3633EFEA856D05BA968C1B3C30CA1788DD95D16B8F914DDDFC3EE5C69945DF7D7BF31C6072BFA7993996AB7DD2F3EE4009844CC9D6CF9E583AEC48A52F2904B57D8E0D755851232838F9B5348838530D7AF95411555D263B8CA86A5D29D7CE4B65409D6F04C5709A56C241C3BCEF07459A416EB4E8F3D73CC714F4333AFE605D53A5C955D5D1412F8361617A54446971FD187442A60FB04457857BECC3120A01FDC7FE2CBF038A61DEE5FCE2D10C8F35FBF80C05ABFF4B6935287B125E8D56F9FDFE7D64C1F4E1F5641845CD17E836B97780400C702523FA8E7C7BBD6F0666591A35ADD26B6B7E33CA56E9AB329EFA7E68F98AE7CE9507755C74C430286A; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h88537A811D4EF6CD9668CCD3E2E7A8041788DCA5F7E08AF52AF5276078304DEB75B74BB9AC3C1A492952F7EEAA0E7CF9FBEDD0FB47EEFDCC3734B816F355C913CD2E1AF14C30545297A91BED3AEAEFF8F696B5F4FC80BC6B1A2559492E9198E4A5875745B625C6CA7A7292332492D139728A689DA1AE78B6B44CE4F4A4EA5A22F331598B364EF27516CC49A4662C5E5C92ED140D96373678F833AE434698237599716B8CBAE2D3D061F2C3D6337AB435B5C2144AB6FA2F8BB51357801066B6589467DA6C480E6D19CEEA8451CEFA88FD70E7925B0302F877F87FA833FBD147E937309C08305A10187707E3D57DDE4931F1D9E97A8F378981ABBF8D7B6B7539C3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h763DD7AA7EED3F4AD4EA7491ADE6F14E6DBADD0F090A8DF34D7BAD35DD2275F0BCCF19EEF299751C919C9C13C6FB9ED711AC4DA7D947CC79E9B6323EF6CE62638CEBCB187AE5D44ECA689C9BD4E5AE544DEA7E90D186B9F335F3323877AAD54196CE81973CB555904419599375501366EC343561BCF83357F8823671393B278C1C387A7970C7F3E688673CF5975EE3E5FF105CFCCFAB725D698FB088B063063C7833830C7B2C7AFB8A8D203C312306DA0E72641FFB93D59B5EC84F44AD55F4B884735325ACC969B2EAE10A1478D866F667DDEF7BBF75E6958B6D02DC6D0F807660A229B98541E6FE734DE2280A9B57FCD5A9BEFEF7CDA5ABEB44FD73D2794D56; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'hD0734B461A36980411EB2A6C1BE76029258777EF227A8F6E84F74C4436098F67BA611013110188547995B108BB2DAE76F423A0D98845F9248BDFA45E10CA403A5E2B1A3E16869E1D37BCE906B82F401CBD467617DB34D9E0C80B5E6E10063EC4BD52921D249E377D95CFAAA309EEDAA57DA85F55DBB7048A69A4C801013948B617F7F5724D40707E6FF30002982023020449B4680C45D1CE6D8EB30A061DB8FEDD6E630C15271E48CA801988654FB501D5393392EE765C1EC95C1E4D86F18A965372B72B484E2F2664B735B69A5AB532B086BA4C62AD6D56EECBDB6984B251454845BD5B243DAED2B2489B313A35C50252AFD3E0B76FEF342335C7F1321D92FF; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N28 -cycloneive_lcell_comb \D[0]~53 ( -// Equation(s): -// \D[0]~53_combout = (\z80_|address_pins_|abus[15]~22_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout $ ((\D[0]~52_combout )))) # (!\z80_|address_pins_|abus[15]~22_combout & (((!\D[0]~52_combout & -// \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ), - .datab(\z80_|address_pins_|abus[15]~22_combout ), - .datac(\D[0]~52_combout ), - .datad(\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ), - .cin(gnd), - .combout(\D[0]~53_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~53 .lut_mask = 16'h4B48; -defparam \D[0]~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N16 -cycloneive_lcell_comb \D[0]~54 ( -// Equation(s): -// \D[0]~54_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[0]~52_combout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[0]~52_combout & -// (\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout & !\D[0]~53_combout )) # (!\D[0]~52_combout & ((\D[0]~53_combout ))))) - - .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\D[0]~52_combout ), - .datad(\D[0]~53_combout ), - .cin(gnd), - .combout(\D[0]~54_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~54 .lut_mask = 16'hC3E0; -defparam \D[0]~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N8 -cycloneive_lcell_comb \D[0]~106 ( -// Equation(s): -// \D[0]~106_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\D[0]~56_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\D[0]~54_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & -// (\D[0]~56_combout )))) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\D[0]~56_combout ), - .datad(\D[0]~54_combout ), - .cin(gnd), - .combout(\D[0]~106_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~106 .lut_mask = 16'hF4B0; -defparam \D[0]~106 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N14 -cycloneive_lcell_comb \D[0]~57 ( -// Equation(s): -// \D[0]~57_combout = ((\Equal2~0_combout & (\D[0]~51_combout )) # (!\Equal2~0_combout & ((\D[0]~106_combout )))) # (!\Equal2~1_combout ) - - .dataa(\Equal2~1_combout ), - .datab(\D[0]~51_combout ), - .datac(\D[0]~106_combout ), - .datad(\Equal2~0_combout ), - .cin(gnd), - .combout(\D[0]~57_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~57 .lut_mask = 16'hDDF5; -defparam \D[0]~57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N0 -cycloneive_lcell_comb \D[0]~58 ( -// Equation(s): -// \D[0]~58_combout = (\D[0]~57_combout & (((\z80_|data_pins_|dout [0]) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) # (!\D[0]~57_combout & (!\Equal2~1_combout & ((!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) - - .dataa(\Equal2~1_combout ), - .datab(\z80_|data_pins_|dout [0]), - .datac(\D[0]~57_combout ), - .datad(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .cin(gnd), - .combout(\D[0]~58_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~58 .lut_mask = 16'hC0F5; -defparam \D[0]~58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N0 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [0] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[0]~17_combout ) # ((\z80_|pin_control_|bus_db_pin_re~combout & \D[0]~58_combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & -// (((\z80_|pin_control_|bus_db_pin_re~combout & \D[0]~58_combout )))) - - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(\z80_|bus_control_|db[0]~17_combout ), - .datac(\z80_|pin_control_|bus_db_pin_re~combout ), - .datad(\D[0]~58_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [0]), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] .lut_mask = 16'hF888; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y13_N1 -dffeas \z80_|data_pins_|dout[0] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [0]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|data_pins_|dout [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|data_pins_|dout[0] .is_wysiwyg = "true"; -defparam \z80_|data_pins_|dout[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N4 -cycloneive_lcell_comb \z80_|bus_control_|db[0]~16 ( -// Equation(s): -// \z80_|bus_control_|db[0]~16_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [0]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) - - .dataa(gnd), - .datab(\z80_|bus_control_|db[0]~4_combout ), - .datac(\z80_|data_pins_|dout [0]), - .datad(\z80_|execute_|ctl_bus_db_oe~combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[0]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[0]~16 .lut_mask = 16'hC0CC; -defparam \z80_|bus_control_|db[0]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N28 -cycloneive_lcell_comb \z80_|bus_control_|db[0]~17 ( -// Equation(s): -// \z80_|bus_control_|db[0]~17_combout = ((\z80_|bus_control_|db[0]~16_combout & ((\z80_|alu_control_|db[0]~12_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - - .dataa(\z80_|bus_control_|db[0]~6_combout ), - .datab(\z80_|alu_control_|db[0]~12_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|bus_control_|db[0]~16_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[0]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[0]~17 .lut_mask = 16'hDF55; -defparam \z80_|bus_control_|db[0]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y13_N27 -dffeas \z80_|ir_|opcode[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|bus_control_|db[0]~17_combout ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|ir_|opcode [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|ir_|opcode[0] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal63~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal63~0_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [5] & (\z80_|execute_|comb~0_combout & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|execute_|comb~0_combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal63~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal63~0 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal63~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_daa ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_sel_daa~combout = (!\z80_|ir_|opcode [4] & (!\z80_|ir_|opcode [3] & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal63~0_combout ))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal63~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_sel_daa .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_flags_cf2_sel_daa .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N20 -cycloneive_lcell_comb \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 ( -// Equation(s): -// \z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout = (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )) # (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ))) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 .lut_mask = 16'h070F; -defparam \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N22 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~10 ( -// Equation(s): -// \z80_|alu_control_|db[6]~10_combout = ((\z80_|execute_|ctl_sw_2u~7_combout ) # (\z80_|execute_|ctl_flags_oe~2_combout )) # (!\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ) - - .dataa(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_sw_2u~7_combout ), - .datad(\z80_|execute_|ctl_flags_oe~2_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~10 .lut_mask = 16'hFFF5; -defparam \z80_|alu_control_|db[6]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N28 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~11 ( -// Equation(s): -// \z80_|alu_control_|db[6]~11_combout = (\z80_|alu_control_|db[6]~10_combout ) # ((\z80_|execute_|ctl_sw_1d~7_combout ) # (\z80_|execute_|ctl_reg_out_lo~8_combout )) - - .dataa(\z80_|alu_control_|db[6]~10_combout ), - .datab(\z80_|execute_|ctl_sw_1d~7_combout ), - .datac(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~11 .lut_mask = 16'hFEFE; -defparam \z80_|alu_control_|db[6]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N18 -cycloneive_lcell_comb \z80_|alu_control_|db[4]~30 ( -// Equation(s): -// \z80_|alu_control_|db[4]~30_combout = (\z80_|alu_|db[4]~17_combout & (\z80_|execute_|ctl_reg_out_lo~8_combout & (!\z80_|reg_file_|gdfx_temp0[4]~62_combout ))) # (!\z80_|alu_|db[4]~17_combout & ((\z80_|execute_|ctl_sw_2u~7_combout ) # -// ((\z80_|execute_|ctl_reg_out_lo~8_combout & !\z80_|reg_file_|gdfx_temp0[4]~62_combout )))) - - .dataa(\z80_|alu_|db[4]~17_combout ), - .datab(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .datad(\z80_|execute_|ctl_sw_2u~7_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[4]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[4]~30 .lut_mask = 16'h5D0C; -defparam \z80_|alu_control_|db[4]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N24 -cycloneive_lcell_comb \z80_|alu_control_|db[4]~31 ( -// Equation(s): -// \z80_|alu_control_|db[4]~31_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & (!\z80_|alu_control_|db[4]~30_combout & ((\z80_|alu_flags_|flags_hf~combout ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) - - .dataa(\z80_|alu_flags_|flags_hf~combout ), - .datab(\z80_|execute_|ctl_flags_oe~2_combout ), - .datac(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .datad(\z80_|alu_control_|db[4]~30_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[4]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[4]~31 .lut_mask = 16'h00B0; -defparam \z80_|alu_control_|db[4]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N6 -cycloneive_lcell_comb \z80_|alu_control_|db[4]~32 ( -// Equation(s): -// \z80_|alu_control_|db[4]~32_combout = ((\z80_|alu_control_|db[4]~31_combout & ((\z80_|bus_control_|db[4]~19_combout ) # (!\z80_|execute_|ctl_sw_1d~7_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|bus_control_|db[4]~19_combout ), - .datab(\z80_|alu_control_|db[6]~11_combout ), - .datac(\z80_|execute_|ctl_sw_1d~7_combout ), - .datad(\z80_|alu_control_|db[4]~31_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[4]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[4]~32 .lut_mask = 16'hBF33; -defparam \z80_|alu_control_|db[4]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~119 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][4]~119_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [2]))) # (!\ula_|ps2_keyboard_|shiftreg [0] & -// (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [2]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [0]), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][4]~119_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][4]~119 .lut_mask = 16'h0420; -defparam \ula_|zx_keyboard_|keys[2][4]~119 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~120 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][4]~120_combout = (\ula_|zx_keyboard_|keys[5][1]~36_combout & (\ula_|zx_keyboard_|keys[2][4]~119_combout & (\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [1]))) - - .dataa(\ula_|zx_keyboard_|keys[5][1]~36_combout ), - .datab(\ula_|zx_keyboard_|keys[2][4]~119_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][4]~120_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][4]~120 .lut_mask = 16'h0080; -defparam \ula_|zx_keyboard_|keys[2][4]~120 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~95 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][4]~95_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [6])) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|shifted~q ), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][4]~95_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][4]~95 .lut_mask = 16'hAFAA; -defparam \ula_|zx_keyboard_|keys[2][4]~95 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~121 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][4]~121_combout = (\ula_|zx_keyboard_|keys[2][4]~120_combout & ((!\ula_|zx_keyboard_|keys[2][4]~95_combout ))) # (!\ula_|zx_keyboard_|keys[2][4]~120_combout & (\ula_|zx_keyboard_|keys[2][4]~q )) - - .dataa(\ula_|zx_keyboard_|keys[2][4]~120_combout ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[2][4]~q ), - .datad(\ula_|zx_keyboard_|keys[2][4]~95_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][4]~121_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][4]~121 .lut_mask = 16'h50FA; -defparam \ula_|zx_keyboard_|keys[2][4]~121 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y18_N23 -dffeas \ula_|zx_keyboard_|keys[2][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[2][4]~121_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[2][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[2][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~117 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][4]~117_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|zx_keyboard_|extended~q ))) # (!\ula_|ps2_keyboard_|shiftreg [2] & -// (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|zx_keyboard_|extended~q ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|zx_keyboard_|extended~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][4]~117_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][4]~117 .lut_mask = 16'h4002; -defparam \ula_|zx_keyboard_|keys[3][4]~117 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~136 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][4]~136_combout = (\ula_|zx_keyboard_|keys[3][4]~117_combout & (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [4]))) - - .dataa(\ula_|zx_keyboard_|keys[3][4]~117_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][4]~136_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][4]~136 .lut_mask = 16'h0080; -defparam \ula_|zx_keyboard_|keys[3][4]~136 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y21_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~130 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][4]~130_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (!\ula_|zx_keyboard_|Equal0~1_combout & (!\ula_|ps2_keyboard_|shiftreg [7] & \ula_|ps2_keyboard_|shiftreg [5]))) - - .dataa(\ula_|ps2_keyboard_|scan_code_ready~q ), - .datab(\ula_|zx_keyboard_|Equal0~1_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [7]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][4]~130_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][4]~130 .lut_mask = 16'h0200; -defparam \ula_|zx_keyboard_|keys[3][4]~130 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~118 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][4]~118_combout = (\ula_|zx_keyboard_|keys[3][4]~136_combout & ((\ula_|zx_keyboard_|keys[3][4]~130_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][4]~130_combout & ((\ula_|zx_keyboard_|keys[3][4]~q -// ))))) # (!\ula_|zx_keyboard_|keys[3][4]~136_combout & (((\ula_|zx_keyboard_|keys[3][4]~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[3][4]~136_combout ), - .datac(\ula_|zx_keyboard_|keys[3][4]~q ), - .datad(\ula_|zx_keyboard_|keys[3][4]~130_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][4]~118_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][4]~118 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[3][4]~118 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y18_N9 -dffeas \ula_|zx_keyboard_|keys[3][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[3][4]~118_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[3][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[3][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N18 -cycloneive_lcell_comb \D[4]~78 ( -// Equation(s): -// \D[4]~78_combout = (\z80_|address_pins_|abus[11]~19_combout & ((\z80_|address_pins_|abus[10]~24_combout ) # ((!\ula_|zx_keyboard_|keys[2][4]~q )))) # (!\z80_|address_pins_|abus[11]~19_combout & (!\ula_|zx_keyboard_|keys[3][4]~q & -// ((\z80_|address_pins_|abus[10]~24_combout ) # (!\ula_|zx_keyboard_|keys[2][4]~q )))) - - .dataa(\z80_|address_pins_|abus[11]~19_combout ), - .datab(\z80_|address_pins_|abus[10]~24_combout ), - .datac(\ula_|zx_keyboard_|keys[2][4]~q ), - .datad(\ula_|zx_keyboard_|keys[3][4]~q ), - .cin(gnd), - .combout(\D[4]~78_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~78 .lut_mask = 16'h8ACF; -defparam \D[4]~78 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~126 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][4]~126_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[7][1]~23_combout & (\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [6]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|zx_keyboard_|keys[7][1]~23_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][4]~126_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][4]~126 .lut_mask = 16'h0040; -defparam \ula_|zx_keyboard_|keys[6][4]~126 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~128 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][4]~128_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [1]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][4]~128_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][4]~128 .lut_mask = 16'h0080; -defparam \ula_|zx_keyboard_|keys[5][4]~128 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~129 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][4]~129_combout = (\ula_|zx_keyboard_|keys[6][4]~126_combout & ((\ula_|zx_keyboard_|keys[5][4]~128_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[5][4]~128_combout & -// (\ula_|zx_keyboard_|keys[5][4]~q )))) # (!\ula_|zx_keyboard_|keys[6][4]~126_combout & (((\ula_|zx_keyboard_|keys[5][4]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[6][4]~126_combout ), - .datab(\ula_|zx_keyboard_|keys[5][4]~128_combout ), - .datac(\ula_|zx_keyboard_|keys[5][4]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][4]~129_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][4]~129 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[5][4]~129 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y19_N9 -dffeas \ula_|zx_keyboard_|keys[5][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[5][4]~129_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[5][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[5][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~127 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][4]~127_combout = (\ula_|zx_keyboard_|keys[6][4]~126_combout & ((\ula_|zx_keyboard_|keys[6][4]~20_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[6][4]~20_combout & ((\ula_|zx_keyboard_|keys[6][4]~q -// ))))) # (!\ula_|zx_keyboard_|keys[6][4]~126_combout & (((\ula_|zx_keyboard_|keys[6][4]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[6][4]~126_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[6][4]~q ), - .datad(\ula_|zx_keyboard_|keys[6][4]~20_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][4]~127_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][4]~127 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[6][4]~127 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y20_N5 -dffeas \ula_|zx_keyboard_|keys[6][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[6][4]~127_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[6][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[6][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~2 ( -// Equation(s): -// \ula_|zx_keyboard_|Equal0~2_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [0])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|Equal0~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|Equal0~2 .lut_mask = 16'h0050; -defparam \ula_|zx_keyboard_|Equal0~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~51 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][4]~51_combout = (\ula_|zx_keyboard_|keys[7][1]~23_combout & (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [1] & \ula_|zx_keyboard_|Equal0~2_combout ))) - - .dataa(\ula_|zx_keyboard_|keys[7][1]~23_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|zx_keyboard_|Equal0~2_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][4]~51_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][4]~51 .lut_mask = 16'h2000; -defparam \ula_|zx_keyboard_|keys[7][4]~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~125 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][4]~125_combout = (\ula_|zx_keyboard_|shifted~1_combout & ((\ula_|zx_keyboard_|keys[7][4]~51_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[7][4]~51_combout & ((\ula_|zx_keyboard_|keys[7][4]~q ))))) -// # (!\ula_|zx_keyboard_|shifted~1_combout & (((\ula_|zx_keyboard_|keys[7][4]~q )))) - - .dataa(\ula_|zx_keyboard_|shifted~1_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[7][4]~q ), - .datad(\ula_|zx_keyboard_|keys[7][4]~51_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][4]~125_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][4]~125 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[7][4]~125 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y20_N11 -dffeas \ula_|zx_keyboard_|keys[7][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[7][4]~125_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[7][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[7][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N30 -cycloneive_lcell_comb \D[4]~79 ( -// Equation(s): -// \D[4]~79_combout = (\z80_|address_pins_|abus[15]~22_combout & ((\z80_|address_pins_|abus[14]~23_combout ) # ((!\ula_|zx_keyboard_|keys[6][4]~q )))) # (!\z80_|address_pins_|abus[15]~22_combout & (!\ula_|zx_keyboard_|keys[7][4]~q & -// ((\z80_|address_pins_|abus[14]~23_combout ) # (!\ula_|zx_keyboard_|keys[6][4]~q )))) - - .dataa(\z80_|address_pins_|abus[15]~22_combout ), - .datab(\z80_|address_pins_|abus[14]~23_combout ), - .datac(\ula_|zx_keyboard_|keys[6][4]~q ), - .datad(\ula_|zx_keyboard_|keys[7][4]~q ), - .cin(gnd), - .combout(\D[4]~79_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~79 .lut_mask = 16'h8ACF; -defparam \D[4]~79 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~122 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][4]~122_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|zx_keyboard_|extended~q )) # (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [6] & -// \ula_|zx_keyboard_|extended~q )) - - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(gnd), - .datad(\ula_|zx_keyboard_|extended~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][4]~122_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][4]~122 .lut_mask = 16'h4422; -defparam \ula_|zx_keyboard_|keys[4][4]~122 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~123 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][4]~123_combout = (\ula_|zx_keyboard_|Equal0~2_combout & (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[4][4]~122_combout ))) - - .dataa(\ula_|zx_keyboard_|Equal0~2_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|keys[4][4]~122_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][4]~123_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][4]~123 .lut_mask = 16'h8000; -defparam \ula_|zx_keyboard_|keys[4][4]~123 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~124 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][4]~124_combout = (\ula_|zx_keyboard_|keys[0][0]~15_combout & ((\ula_|zx_keyboard_|keys[4][4]~123_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[4][4]~123_combout & ((\ula_|zx_keyboard_|keys[4][4]~q -// ))))) # (!\ula_|zx_keyboard_|keys[0][0]~15_combout & (((\ula_|zx_keyboard_|keys[4][4]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[4][4]~q ), - .datad(\ula_|zx_keyboard_|keys[4][4]~123_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][4]~124_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][4]~124 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[4][4]~124 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y19_N25 -dffeas \ula_|zx_keyboard_|keys[4][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[4][4]~124_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[4][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[4][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~3 ( -// Equation(s): -// \ula_|zx_keyboard_|key_row~3_combout = ((\z80_|address_pins_|DFFE_apin_latch [12]) # (!\ula_|zx_keyboard_|keys[4][4]~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [12]), - .datad(\ula_|zx_keyboard_|keys[4][4]~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|key_row~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|key_row~3 .lut_mask = 16'hF3FF; -defparam \ula_|zx_keyboard_|key_row~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N8 -cycloneive_lcell_comb \D[4]~80 ( -// Equation(s): -// \D[4]~80_combout = (\D[4]~79_combout & (\ula_|zx_keyboard_|key_row~3_combout & ((\z80_|address_pins_|abus[13]~20_combout ) # (!\ula_|zx_keyboard_|keys[5][4]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[5][4]~q ), - .datab(\D[4]~79_combout ), - .datac(\z80_|address_pins_|abus[13]~20_combout ), - .datad(\ula_|zx_keyboard_|key_row~3_combout ), - .cin(gnd), - .combout(\D[4]~80_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~80 .lut_mask = 16'hC400; -defparam \D[4]~80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~111 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][4]~111_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [6])) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|shifted~q ), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][4]~111_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][4]~111 .lut_mask = 16'hFAAA; -defparam \ula_|zx_keyboard_|keys[0][4]~111 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~97 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][4]~97_combout = (\ula_|zx_keyboard_|keys[5][1]~36_combout & (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [6] $ (\ula_|ps2_keyboard_|shiftreg [5])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|zx_keyboard_|keys[5][1]~36_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][4]~97_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][4]~97 .lut_mask = 16'h0060; -defparam \ula_|zx_keyboard_|keys[0][4]~97 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~116 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][4]~116_combout = (\ula_|zx_keyboard_|keys[3][1]~29_combout & ((\ula_|zx_keyboard_|keys[0][4]~97_combout & (!\ula_|zx_keyboard_|keys[0][4]~111_combout )) # (!\ula_|zx_keyboard_|keys[0][4]~97_combout & -// ((\ula_|zx_keyboard_|keys[0][4]~q ))))) # (!\ula_|zx_keyboard_|keys[3][1]~29_combout & (((\ula_|zx_keyboard_|keys[0][4]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[3][1]~29_combout ), - .datab(\ula_|zx_keyboard_|keys[0][4]~111_combout ), - .datac(\ula_|zx_keyboard_|keys[0][4]~q ), - .datad(\ula_|zx_keyboard_|keys[0][4]~97_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][4]~116_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][4]~116 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[0][4]~116 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y18_N11 -dffeas \ula_|zx_keyboard_|keys[0][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[0][4]~116_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[0][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[0][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][4]~115 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][4]~115_combout = (\ula_|zx_keyboard_|Equal0~2_combout & ((\ula_|zx_keyboard_|keys[1][4]~25_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[1][4]~25_combout & (\ula_|zx_keyboard_|keys[1][4]~q )))) # -// (!\ula_|zx_keyboard_|Equal0~2_combout & (((\ula_|zx_keyboard_|keys[1][4]~q )))) - - .dataa(\ula_|zx_keyboard_|Equal0~2_combout ), - .datab(\ula_|zx_keyboard_|keys[1][4]~25_combout ), - .datac(\ula_|zx_keyboard_|keys[1][4]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][4]~115_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][4]~115 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[1][4]~115 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y19_N7 -dffeas \ula_|zx_keyboard_|keys[1][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[1][4]~115_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[1][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[1][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N28 -cycloneive_lcell_comb \D[4]~77 ( -// Equation(s): -// \D[4]~77_combout = (\z80_|address_pins_|abus[9]~17_combout & ((\z80_|address_pins_|abus[8]~18_combout ) # ((!\ula_|zx_keyboard_|keys[0][4]~q )))) # (!\z80_|address_pins_|abus[9]~17_combout & (!\ula_|zx_keyboard_|keys[1][4]~q & -// ((\z80_|address_pins_|abus[8]~18_combout ) # (!\ula_|zx_keyboard_|keys[0][4]~q )))) - - .dataa(\z80_|address_pins_|abus[9]~17_combout ), - .datab(\z80_|address_pins_|abus[8]~18_combout ), - .datac(\ula_|zx_keyboard_|keys[0][4]~q ), - .datad(\ula_|zx_keyboard_|keys[1][4]~q ), - .cin(gnd), - .combout(\D[4]~77_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~77 .lut_mask = 16'h8ACF; -defparam \D[4]~77 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N26 -cycloneive_lcell_comb \D[4]~81 ( -// Equation(s): -// \D[4]~81_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[4]~78_combout & (\D[4]~80_combout & \D[4]~77_combout ))) - - .dataa(\z80_|address_pins_|abus[0]~16_combout ), - .datab(\D[4]~78_combout ), - .datac(\D[4]~80_combout ), - .datad(\D[4]~77_combout ), - .cin(gnd), - .combout(\D[4]~81_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~81 .lut_mask = 16'hEAAA; -defparam \D[4]~81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y1_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a12 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'hA50276000854A0103840403E540424244404783E18807A08A47C54484448544A807E7E10005270182040407E4A1252124208084008404208420A4A42424A125A024428106448524A624A4A24425242522060108010543C00044A105424005E0031ED1E0529E507AE2F6FF1CD51D4C772A648E65F6532C28022061303F06C36CDBD319B55CB8E626C20E46C93C1463A0B1CE594F0ED3B62330C104DECE46CA6CD966B1386612C7B43980349408F36FB64C14342DAE26CE4D8D5E791388729D743B09A27AB81D71A14AB3D24E385B602248476D00249239514B58D3098504ACD119B99E9021B650A69494C22600667473128DA5010D2195982823226DED0ADFCB8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h5861917919344A4685CC0990862A11324792E761B6D41C0FCC0838C1C27211A2453FDC2219C225E421B320085A8FBFD0C42135B16448DFC226E09B3438A740C352979565817114DE46462844A57F7958873FC4B255C8AE549BDD1A87415D5018F88D5002628FFD13203066C850F10649F21319109208387641120B362124803F0678522BA2812C1454A502ED1A59CBD76A034756F5765DF7555F57575F7F57FFFF7FFF7D5712524D4A30723514B2B3064A84B4742D48415281863DDFAA9D9B7E7BB16DDB96B7845371C30B55DB96C8F6EB4B453242FF6A4DF84A76B5AEDC88A68DC6A06905054C8C36E4199E74638E6532965218A965909BA456000451343351; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'hE2975A2686A7AE0288F140141B698E2A82A835F478453A1D722CFCED12859FD735188757AC5A42DEB501FE010586249AC1EA60D08F74CFA5086EC78FC9190C056059E332C311521E6522901852D484B423A98816C9B26A08C92368E9FF05524502288A804612A2A0A102A418CBDFBA554499541660F8124640110101263142892A086B442661015380041594608092D9CB919250100A37DDA3919A1427F660963C251301FB2CA45562245308885131119115C652B2493252340201101942D26000CC60799124A8520C08050122171281808058018C38A645D07931896B39ED259A22242CB58413089465B246231330D806105010035100B08761A08506094160; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h1228D91C352915424000000AA0088F63153A8AD81B945C8789F01C86548D12CEAB6AA38578BD55CEC9AA28082C285B8C0201104838AD502AC160C13C70620B818249144AB52CED94200A0202A885100E0D938A30A34512C0CEC98F08A98900F2093E11673256B3169C12284980E92A034141E0782507800F8100009C403C07867000000030082004A17800828F090A0C318CE120012172286317922341A2A12840B6C18040682080125C75401AEC44E8C01A8D40D1412B25A09F7600B0C6FEC65BFE5CE861A20F71E8032916A78F29CC546518461522E4E14998DD54BC0E40B64B710C9DC948F06010DF01D880E2044BE8854062D10DD93F30A62AA7FD227C4C; -// synopsys translate_on - -// Location: M9K_X22_Y22_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a12 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(gnd), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[4]~98_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_first_bit_number = 4; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y3_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a4 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h35861A00A6112A1481AF1A50A6004A05291627227FF08229B87389E08119A28A7888672DC999B7046A61E60810A7434450E3D33E330F321A18E8A120D1EDC8623DA2C64840C2CCE811522B42008095E5A456C98F4B25EAEA410610545024640CF10410AC463BF9349074917E9A74A12830EFA280EBD3131E484A255D0191C6852730A263DBCCAAA88712242B3BE49AA5338990229B391158C726BC7EB4ECC32308980020680249882691A680488292310B4313CE87FFCD5329A64B708CAC8533316412C4900F646A36630261DA093053D98F19D2C5B653165D4A71AA5682B29B89B6054CC727D292805705A93268676A31111371390B240EC3CC85D331813EB1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h1AA1C248D293110CB951445117D9B6AA500F65068B8CC508BD00184F8705B010A0CC46CC9302649242CE08191634113154562B149100204551178DE805D98EC8A2E5A64B241400267194CD524499BC01D31058CD18684A817A5800B65143281C1310B00A49902C0104004C654E0582040001103654011012021912281216B000C653A0510A1B00C36AC88058CAC126E14E198DFB07E81C3F41510BB08F8F851C3B9AF0147BC1F730B4E91D9D11C3A8F1B82DF19988ACC44072FDB17B4D81882E9DD952B29003D7767BA581A68BC41C2B16AD6EB57F1D048CD4E464190D25ADF2C194E3598360AFB031A1690F4625BB628363B4C90A400E3A04DAA70DA0CC4776; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'hC82B30671933680037A65978674DDEC2D30EEEDA78F5F2A1DEE660FFEA11B175DCB42E9277212A58842051A078007109A0D820166B881042600284403143048295D23A0E191EBC2134B833D53D37E42B05018289A10300A188E315CE98640F548A370D60A0AA3E7288A0B0869FA5E703D1AE17C0EC276B2AFB747B550A8B41021620D1A60A901095D12A0973B95E20838001330138951361967847D42901910A3488480610A91A851E84FF08783F81AEA52D2FDC2200BD2FE81C0357FBEC1D875686C6CA41B2224C88D8456C1DBF20D820A6649774CB11B69933246E9739C998470542C2E3C783A4C24767084C52DC209D60E95DBC096D9A0171A12D5AB99BAB; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h17A24D2C636ED2478B5AE1C99D40761B1E7AA6A89DDD1BBD8DBD223E70531BCDE90C8E38C8E0478AD8B388F94891C9673A50BC32478E083074657E8E0EA53BEE861F8BC1993560946D92D1C0C7F046A245B5849CB751FF15B97FCD50BC7B8524C13E7C640F3645082248D1CC14296E30DEA3057B35C641762CD00D40DABC27472251A60725008AAA056591C4000BB48C0BC29B8034A03400027B84769B520D9196968460CA3388A03ECB45F2C4B70F1829221000FFFC7FEC346F079F13079798EC2A08157331C6CC0E30884244916A0DE26D4D22454091290404A492016887E2111F830F9851184101370588A06D3BF9AE621A5F4E632A6799C83EFAAE06769D; -// synopsys translate_on - -// Location: M9K_X22_Y25_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a4 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[4]~98_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a4_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_first_bit_number = 4; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFFF0000003E0000003E0000C83F0000D83F0000F03F0000303E0000303E0000003F0010003F0010203F0010F03F0010703F0018303F001C603D800C003CFE26003C7F0F803FFFFFFFFFFFFFFFF; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF00000000000008108000BDF288E9688E000000000000000000000000FFFFFFFF0000000000041D989EA296D29EE969CA000000000000000000000000000000007FFFFFFC8004198A9AA298929EE9498A00000000000000000000000000000000FFFFFFFE800400CA9AA2AADA8AE949CE0000000000000000000000007FFFFFFEC00000028004046A9F22BA5A9EE90FC20000000000000000000000007FFFFFFE8000000280040FEA8002AA7A9EE12742000000000000000000000000000000023FFFFFFC9FE42BA298E2293A80096742000000000000000000000000000000003FFFFFFC9FE4B19298E3181E8009436A; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'h9FE8234A88F836EE9FF8BD4208282BC080DE87C2B84199C2B85E37C2B05B3A829FE8236688F837CE9FF8898208A82A44808A87CAB9C19DC2B80E3AC2927F2AC2800833E288F837C69FE8AB9688882E4283248DC2B9D188C2ABAE2F8291371092800832EA887807C69FE8AB8688080AC283E49D42B914BFC2A3BF1E82910712EA800802EA883807869DE88E8688080AC68BC4BDC2BB1439C2A27F5F82910314E2800886E6880807C69CC89A8681800BC289549CC2AB0C3942A04B7F82953315E2800886EE900805C61C089FC081E415C289D89DC2AB4E3142A1233D8217330090800086EE900805821C08BEC080D407C289C89DC2AADE3142A13B7F82176300F0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h076B0A5083288F028370C182A801468297E5AC1288D308023FFFFFFC00000000072BA9608BA08D028BF4D182AC015682937CA80288D308023FFFFFFC00000002872B892A8FA08F028A14509AAC0166B2B37DA80288D10D02800000027FFFFFFE852BAD128E388D028A004082AC0166C2937DA00288D10F02C00000027FFFFFFE846289368968C90289E0528A8C016CA29379B20280510F02FFFFFFFE0000000085E2A922816089828BE0428286416C829179B00280511F027FFFFFFC0000000087EA8B32872089828800569287436CA28179B20200513F0000000000FFFFFFFF8768A3028610858288004682874364828019900200403E0000000000FFFFFFFF; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N2 -cycloneive_lcell_comb \Selector4~0 ( -// Equation(s): -// \Selector4~0_combout = (\z80_|address_pins_|abus[14]~23_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout )))) # (!\z80_|address_pins_|abus[14]~23_combout -// & (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ))) - - .dataa(\z80_|address_pins_|abus[14]~23_combout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout ), - .cin(gnd), - .combout(\Selector4~0_combout ), - .cout()); -// synopsys translate_off -defparam \Selector4~0 .lut_mask = 16'hBA98; -defparam \Selector4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N26 -cycloneive_lcell_comb \Selector4~1 ( -// Equation(s): -// \Selector4~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Selector4~0_combout & ((\ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ))) # (!\Selector4~0_combout & -// (\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Selector4~0_combout )))) - - .dataa(\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ), - .datad(\Selector4~0_combout ), - .cin(gnd), - .combout(\Selector4~1_combout ), - .cout()); -// synopsys translate_off -defparam \Selector4~1 .lut_mask = 16'hF388; -defparam \Selector4~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y14_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a28 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[4]~98_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a28_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_first_bit_number = 4; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y8_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a12 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[4]~98_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y16_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a20 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[4]~98_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_first_bit_number = 4; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y3_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a4 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[4]~98_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N20 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout )) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ))))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout ), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2 .lut_mask = 16'hE5E0; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N10 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2_combout & -// (\ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout )) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ))))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2_combout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2_combout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3 .lut_mask = 16'hAFC0; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N6 -cycloneive_lcell_comb \D[4]~109 ( -// Equation(s): -// \D[4]~109_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\Selector4~1_combout -// )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3_combout ))))) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\Selector4~1_combout ), - .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3_combout ), - .cin(gnd), - .combout(\D[4]~109_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~109 .lut_mask = 16'hFB40; -defparam \D[4]~109 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N18 -cycloneive_lcell_comb \D[4]~97 ( -// Equation(s): -// \D[4]~97_combout = ((\Equal2~0_combout & (\D[4]~81_combout )) # (!\Equal2~0_combout & ((\D[4]~109_combout )))) # (!\Equal2~1_combout ) - - .dataa(\Equal2~0_combout ), - .datab(\D[4]~81_combout ), - .datac(\Equal2~1_combout ), - .datad(\D[4]~109_combout ), - .cin(gnd), - .combout(\D[4]~97_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~97 .lut_mask = 16'hDF8F; -defparam \D[4]~97 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N30 -cycloneive_lcell_comb \D[4]~98 ( -// Equation(s): -// \D[4]~98_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout & (\z80_|data_pins_|dout [4] & ((\D[4]~97_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\D[4]~97_combout ) # (!\Equal2~1_combout )))) - - .dataa(\z80_|data_pins_|dout [4]), - .datab(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datac(\Equal2~1_combout ), - .datad(\D[4]~97_combout ), - .cin(gnd), - .combout(\D[4]~98_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~98 .lut_mask = 16'hBB03; -defparam \D[4]~98 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N24 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[4] ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [4] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[4]~19_combout ) # ((\D[4]~98_combout & \z80_|pin_control_|bus_db_pin_re~combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & -// (\D[4]~98_combout & (\z80_|pin_control_|bus_db_pin_re~combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(\D[4]~98_combout ), - .datac(\z80_|pin_control_|bus_db_pin_re~combout ), - .datad(\z80_|bus_control_|db[4]~19_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [4]), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[4] .lut_mask = 16'hEAC0; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[4] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y13_N25 -dffeas \z80_|data_pins_|dout[4] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [4]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|data_pins_|dout [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|data_pins_|dout[4] .is_wysiwyg = "true"; -defparam \z80_|data_pins_|dout[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N20 -cycloneive_lcell_comb \z80_|bus_control_|db[4]~18 ( -// Equation(s): -// \z80_|bus_control_|db[4]~18_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [4]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) - - .dataa(\z80_|data_pins_|dout [4]), - .datab(\z80_|bus_control_|db[0]~4_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_bus_db_oe~combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[4]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[4]~18 .lut_mask = 16'h88CC; -defparam \z80_|bus_control_|db[4]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N18 -cycloneive_lcell_comb \z80_|bus_control_|db[4]~19 ( -// Equation(s): -// \z80_|bus_control_|db[4]~19_combout = ((\z80_|bus_control_|db[4]~18_combout & ((\z80_|alu_control_|db[4]~32_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - - .dataa(\z80_|bus_control_|db[0]~6_combout ), - .datab(\z80_|alu_control_|db[4]~32_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|bus_control_|db[4]~18_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[4]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[4]~19 .lut_mask = 16'hDF55; -defparam \z80_|bus_control_|db[4]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y10_N19 -dffeas \z80_|ir_|opcode[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|bus_control_|db[4]~19_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|ir_|opcode [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|ir_|opcode[4] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal21~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal21~0_combout = (!\z80_|ir_|opcode [3] & \z80_|ir_|opcode [4]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal21~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal21~0 .lut_mask = 16'h0F00; -defparam \z80_|pla_decode_|Equal21~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~5 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~5_combout = (\z80_|pla_decode_|Equal21~0_combout & (\z80_|pla_decode_|Equal2~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal1~7_combout ))) - - .dataa(\z80_|pla_decode_|Equal21~0_combout ), .datab(\z80_|pla_decode_|Equal2~0_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~15 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_mRead~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~39 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~39_combout = (((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|execute_|ctl_mRead~15_combout ) + + .dataa(\z80_|sequencer_|M5~q ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|execute_|ctl_mRead~15_combout ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~39 .lut_mask = 16'h1FFF; +defparam \z80_|execute_|ctl_inc_cy~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~36 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~36_combout = (\z80_|execute_|ctl_inc_cy~39_combout & (\z80_|execute_|ctl_inc_cy~38_combout & \z80_|execute_|ctl_inc_cy~82_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_inc_cy~39_combout ), + .datac(\z80_|execute_|ctl_inc_cy~38_combout ), + .datad(\z80_|execute_|ctl_inc_cy~82_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~36 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~4 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~4_combout = (\z80_|execute_|ctl_alu_op_low~22_combout & (\z80_|pla_decode_|Equal55~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal1~7_combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~5_combout ), + .combout(\z80_|execute_|ctl_sw_4u~4_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mRead~5 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_mRead~5 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_sw_4u~4 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_sw_4u~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y18_N22 -cycloneive_lcell_comb \z80_|execute_|fIOWrite~2 ( +// Location: LCCOMB_X21_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~16 ( // Equation(s): -// \z80_|execute_|fIOWrite~2_combout = (\z80_|execute_|ctl_iorw~11_combout & ((\z80_|execute_|ctl_mWrite~3_combout ) # ((\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|fMRead~0_combout )))) +// \z80_|execute_|ctl_reg_sel_wz~16_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & (!\z80_|execute_|ctl_sw_4u~4_combout & ((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|ctl_ir_we~12_combout )))) - .dataa(\z80_|execute_|ctl_mWrite~3_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_iorw~11_combout ), - .datad(\z80_|execute_|fMRead~0_combout ), + .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), + .datab(\z80_|execute_|ctl_ir_we~12_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_sw_4u~4_combout ), .cin(gnd), - .combout(\z80_|execute_|fIOWrite~2_combout ), + .combout(\z80_|execute_|ctl_reg_sel_wz~16_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fIOWrite~2 .lut_mask = 16'hE0F0; -defparam \z80_|execute_|fIOWrite~2 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_reg_sel_wz~16 .lut_mask = 16'h0015; +defparam \z80_|execute_|ctl_reg_sel_wz~16 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y18_N16 -cycloneive_lcell_comb \z80_|execute_|fIOWrite~3 ( +// Location: LCCOMB_X21_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~17 ( // Equation(s): -// \z80_|execute_|fIOWrite~3_combout = ((!\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ) +// \z80_|execute_|ctl_reg_sel_wz~17_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~36_combout & (\z80_|execute_|fMRead~6_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout & \z80_|execute_|ctl_reg_sel_wz~16_combout ))) - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~36_combout ), + .datab(\z80_|execute_|fMRead~6_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~16_combout ), .cin(gnd), - .combout(\z80_|execute_|fIOWrite~3_combout ), + .combout(\z80_|execute_|ctl_reg_sel_wz~17_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fIOWrite~3 .lut_mask = 16'h3F0F; -defparam \z80_|execute_|fIOWrite~3 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_reg_sel_wz~17 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sel_wz~17 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y18_N2 -cycloneive_lcell_comb \z80_|execute_|fIOWrite~4 ( +// Location: LCCOMB_X27_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~5 ( // Equation(s): -// \z80_|execute_|fIOWrite~4_combout = (\z80_|execute_|ctl_mRead~36_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ixy_d~6_combout ) # (!\z80_|execute_|fIOWrite~3_combout )))) +// \z80_|execute_|ctl_sw_4u~5_combout = (\z80_|execute_|ctl_alu_op_low~28_combout ) # (((\z80_|execute_|ctl_alu_shift_oe~14_combout & \z80_|pla_decode_|Equal47~0_combout )) # (!\z80_|execute_|ctl_sw_4u~1_combout )) - .dataa(\z80_|execute_|ctl_mRead~36_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|execute_|fIOWrite~3_combout ), + .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datab(\z80_|pla_decode_|Equal47~0_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~28_combout ), + .datad(\z80_|execute_|ctl_sw_4u~1_combout ), .cin(gnd), - .combout(\z80_|execute_|fIOWrite~4_combout ), + .combout(\z80_|execute_|ctl_sw_4u~5_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fIOWrite~4 .lut_mask = 16'hA8AA; -defparam \z80_|execute_|fIOWrite~4 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_sw_4u~5 .lut_mask = 16'hF8FF; +defparam \z80_|execute_|ctl_sw_4u~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y18_N4 -cycloneive_lcell_comb \z80_|execute_|fIOWrite~5 ( +// Location: LCCOMB_X29_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~6 ( // Equation(s): -// \z80_|execute_|fIOWrite~5_combout = (\z80_|execute_|fIOWrite~2_combout ) # ((\z80_|execute_|fIOWrite~4_combout ) # ((\z80_|execute_|fIOWrite~1_combout & \z80_|execute_|ctl_mRead~5_combout ))) +// \z80_|execute_|ctl_sw_4u~6_combout = (((\z80_|execute_|ctl_sw_4u~5_combout ) # (!\z80_|execute_|ctl_sw_4u~3_combout )) # (!\z80_|execute_|ctl_apin_mux~0_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~17_combout ) - .dataa(\z80_|execute_|fIOWrite~1_combout ), - .datab(\z80_|execute_|ctl_mRead~5_combout ), - .datac(\z80_|execute_|fIOWrite~2_combout ), - .datad(\z80_|execute_|fIOWrite~4_combout ), + .dataa(\z80_|execute_|ctl_reg_sel_wz~17_combout ), + .datab(\z80_|execute_|ctl_apin_mux~0_combout ), + .datac(\z80_|execute_|ctl_sw_4u~3_combout ), + .datad(\z80_|execute_|ctl_sw_4u~5_combout ), .cin(gnd), - .combout(\z80_|execute_|fIOWrite~5_combout ), + .combout(\z80_|execute_|ctl_sw_4u~6_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fIOWrite~5 .lut_mask = 16'hFFF8; -defparam \z80_|execute_|fIOWrite~5 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_sw_4u~6 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_sw_4u~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y17_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~11 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~11_combout = (!\z80_|execute_|ctl_mWrite~10_combout & (((!\z80_|execute_|ctl_mRead~10_combout & !\z80_|execute_|ctl_mRead~8_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|execute_|ctl_mWrite~10_combout ), - .datac(\z80_|execute_|ctl_mRead~8_combout ), - .datad(\z80_|execute_|ctl_state_alu~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~11 .lut_mask = 16'h0133; -defparam \z80_|execute_|ctl_mWrite~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~12 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~12_combout = (\z80_|execute_|ctl_mWrite~8_combout & (\z80_|execute_|ctl_mWrite~11_combout & ((!\z80_|execute_|ctl_mWrite~6_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|ctl_mWrite~8_combout ), - .datac(\z80_|execute_|ctl_mWrite~6_combout ), - .datad(\z80_|execute_|ctl_mWrite~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~12 .lut_mask = 16'h4C00; -defparam \z80_|execute_|ctl_mWrite~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~13 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~13_combout = (\z80_|execute_|ctl_mWrite~12_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~4_combout & (\z80_|execute_|ctl_mWrite~9_combout & \z80_|execute_|ctl_bus_db_oe~7_combout ))) - - .dataa(\z80_|execute_|ctl_mWrite~12_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), - .datac(\z80_|execute_|ctl_mWrite~9_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~13 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_mWrite~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~14 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~14_combout = (\z80_|execute_|ctl_state_alu~4_combout & ((\z80_|execute_|ctl_mRead~7_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & \z80_|execute_|ctl_mWrite~5_combout )))) # (!\z80_|execute_|ctl_state_alu~4_combout & -// (((\z80_|execute_|ctl_eval_cond~0_combout & \z80_|execute_|ctl_mWrite~5_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_mRead~7_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_mWrite~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~14 .lut_mask = 16'hF888; -defparam \z80_|execute_|ctl_mWrite~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~15 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~15_combout = ((\z80_|execute_|ctl_mWrite~14_combout ) # ((!\z80_|execute_|ixy_d~17_combout & \z80_|execute_|ixy_d~8_combout ))) # (!\z80_|execute_|ctl_mWrite~13_combout ) - - .dataa(\z80_|execute_|ixy_d~17_combout ), - .datab(\z80_|execute_|ctl_mWrite~13_combout ), - .datac(\z80_|execute_|ctl_mWrite~14_combout ), - .datad(\z80_|execute_|ixy_d~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~15 .lut_mask = 16'hF7F3; -defparam \z80_|execute_|ctl_mWrite~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X43_Y17_N29 -dffeas \z80_|memory_ifc_|DFFE_mwr_ff1 ( +// Location: FF_X30_Y12_N27 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[3] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_mWrite~15_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_mwr_ff1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_mwr_ff1 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_mwr_ff1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N4 -cycloneive_lcell_comb \z80_|memory_ifc_|wait_mwr~feeder ( -// Equation(s): -// \z80_|memory_ifc_|wait_mwr~feeder_combout = \z80_|memory_ifc_|DFFE_mwr_ff1~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|memory_ifc_|DFFE_mwr_ff1~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|wait_mwr~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_mwr~feeder .lut_mask = 16'hFF00; -defparam \z80_|memory_ifc_|wait_mwr~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X43_Y17_N5 -dffeas \z80_|memory_ifc_|wait_mwr ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|memory_ifc_|wait_mwr~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|wait_mwr~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_mwr .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|wait_mwr .power_up = "low"; -// synopsys translate_on - -// Location: FF_X43_Y17_N17 -dffeas \z80_|memory_ifc_|mwr_wr ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), - .asdata(\z80_|memory_ifc_|wait_mwr~q ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|mwr_wr~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|mwr_wr .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|mwr_wr .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N16 -cycloneive_lcell_comb \z80_|memory_ifc_|nWR_out~0 ( -// Equation(s): -// \z80_|memory_ifc_|nWR_out~0_combout = (\z80_|memory_ifc_|mwr_wr~q ) # ((\z80_|execute_|fIOWrite~5_combout & \z80_|memory_ifc_|iorq~0_combout )) - - .dataa(\z80_|execute_|fIOWrite~5_combout ), - .datab(\z80_|memory_ifc_|iorq~0_combout ), - .datac(\z80_|memory_ifc_|mwr_wr~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|memory_ifc_|nWR_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|nWR_out~0 .lut_mask = 16'hF8F8; -defparam \z80_|memory_ifc_|nWR_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N4 -cycloneive_lcell_comb \D[5]~84 ( -// Equation(s): -// \D[5]~84_combout = (!\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|memory_ifc_|nRD_out~2_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|memory_ifc_|nIORQ_out~0_combout ))) - - .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), - .datab(\z80_|memory_ifc_|nRD_out~2_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|memory_ifc_|nIORQ_out~0_combout ), - .cin(gnd), - .combout(\D[5]~84_combout ), - .cout()); -// synopsys translate_off -defparam \D[5]~84 .lut_mask = 16'h0040; -defparam \D[5]~84 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y5_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a23 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[7]~102_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_first_bit_number = 7; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y4_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a7 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[7]~102_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081; -// synopsys translate_on - -// Location: M9K_X33_Y7_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a15 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[7]~102_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N14 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]) # -// ((\ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & -// (\ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6 .lut_mask = 16'hBA98; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y4_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a31 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[7]~102_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a31_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_first_bit_number = 7; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N4 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6_combout & -// ((\ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout )))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6_combout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout ), - .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6_combout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7 .lut_mask = 16'hF858; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y24_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a15 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(gnd), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[7]~102_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_first_bit_number = 7; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y30_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a15 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h3C0000000000000000000000000000000000000000000000000000000000000080000000000002000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFB91060128E2D09899B4D10A148392808351AD282E76190E029FDC286449331D89080802222C0D04D1121484041D21084C223B0A12EBE72083D81421B93CA9589A04864A853089602E536320C2A5944831907110C246020089C76EE701A4E23964C6586008731635460418000008202040C300110000FCE7E12403749F8C6AB8F69167210EF8A4B8228710884C5C47A9986E8840C02862C088C36E19CF1D315; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h03020CCE064769B15020A6030880234C64E9BEF8E98A81489083A026140D648906E5AD6C882882990A40D293FED064710CB226CDA0330D7B189B344442EC35E3763C75FA1DB107B865E5B8F7B95E77F222244C6BDC1879C0562EF779BE0009465775469089F04C623E19317B486F653C1C22CA642CD685C10EE47EDD66C8C226C7C57F084106FB3B8B1E47463C0088D11104F23C180222A0AA22A22882A202A00000000288964258156302504F5F660C054DEDCA20CC201A4074192601E376C9596CD8B4B568A4DFEF3DBF8027A3422A56A2C003E514582104BF8D6B5D80BB397FBBEC46E8B3CAEBE0100275A1092081D0C1E5716DF09CFEEC00AD800529E1A8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h873CB568FC3F09080F4400DAC600092017210911A6081DCC4979244124815884AE6302C4BE6BA8C22A084803225A0855ABBBC528B1CA2456A4951A53C1209153CFC3000F43632B49C39723270C604B184D1940F1B2A04459BEB088666843BB38C23A8D170CED981891256A2C1D9B31C0F040202103900E6765976089DB8DE16E0001022EC10015E263787F7E581EF83F062200C626EC4E19021840D9C112400C4B987A78AE1BF80005EF370C0739371E0D3E5CF1E3677332370BB98D1831B30F7D8CDC0131C444798F040DC0116E2C4336B0166109A15D1FCC7EDE31EB23862203C11245EE31E38E6DEF2188BE2068F3C716E10317783020D8EF5C256774BA0E; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h1B9CE2DA363196DC20007FF5554FC631286DC716B048384C26510685218DF9E6C629E6050C619658692170C1022C2232C965C92C189020C705873084858910322166D72DC524870C422BBFFD4808A7032B088DE3000B853800736C8E9968C19A4B72C08871D2413188E4829219C38C2025920480D64856902E4D4D60B640C833C14D536A45D144B244C24A290076E58CC2E64E4A2DC4C5939C4C2DDBD1B918B231248625B2C0DD0F07A27A111CB80A48808C7C21C205029100010400228BB3BDFF7DCCEF40196C8381658D8840043B119B86A46247665810E2203000141023C366CB633B3376DC625DA8A0856C484392B779E1BA4088EDB4A6CDB9BD46DCC0B2; -// synopsys translate_on - -// Location: M9K_X22_Y2_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a7 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h7C762E21DB2481CB6BB88C68811C76C63B18ECC1BACDC6110DCC70BC20940800C71478E35468600B01A93082C63DD073AE4181844449C08D8D56B0DCC881251C202139803D3000B2E0209DB9101160989A5916381001B0446631006064DB1B996E436E644CF6C8606F124DA230E9B66E2F46BB466E2CE068661B4B05F02F7D00CB3E518948104042F84F1840401018406877D800A00000F5122597005DA4411000800020249004081008924124080114000000020BFFFFEC638C31207B6C321407D901787004001C459326210CCE00C6AF707B84440C313110B8C4D13B2C6E06C4C088B1A9B24BEB0178C4D6C18230DF72B07A28063647CC4721026D8C711864; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h881B30810845E6D18622EC9B6236A000030986A4F0644601226000A2F220D40310438334E51C28000400B18422CA60FC42C9C03F066366ECBBB010B00B004807CC0E00DAEC3000194A52B80C606262092D84A1102410000001400010002000800200080020000800200008000800400040002004000040002000020002000801000010004002001000200008000AEE708008880C86112251B45B36C0048833B319B4C2CE6660D2C0619246C4B208BC0AD00202001E104FC30911410804201E92102B400E8004C40AD6E4614466308ABC7165AA57060A3A736A188ABB300200A10BB04344008422327B1393C43396A931B8C8C87227A6141C0E2DCC76D830B082; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h101CC0024A6C32005CCB31908842211604D8B326101118B54B188CB4D502F5F02DA65C2472B824F109BC594C2401209C01A0E59830002C73B396C6015B85A163184B56183004204267600220A061A004893E1D609106BDBB553920A011AA5AE581E08228382D54C2989BC59535528176240438C9AA757917F95C7428981A26470D1C3E528444D9B00E561C40973AE1806031C464834F03D34A11233A34B34A1D1A55A50C3384B549B64C381920140D4008004020B119D5834C10064000006001169808000200040100000002F8986E37654DDFF88E20860382DC089D4C239F6E4C3C8D784218667F524CE209881213DC91099C14744901620044C802DA414966; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h84724A241226DB4809C9A1100DE6A63984D651A2624A09420496DDC12CC10964B6E370363701B41848117683379C8422106D001BB41FB8248067301E1002C636A276585D5273AC87206840415DA74B4E9D213CAE3234B308E19608AA38250844883838649E1442A0D983F4A9094A5AD4A52D56C5D80CAC58D9645944A230091549F30426B100842A12B25160D6D991E6C8C81AFB4C644004C2140A342020D84C9001624489A10045D16C944B02763FF55405E400BADFE5BFFFFFF00000000011042250089108884888410924041204444209102084241104204108824114455292225124929249248894408541300A6DB00791E5B12FEF24037181F1901B007B; -// synopsys translate_on - -// Location: M9K_X33_Y26_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a7 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[7]~102_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_first_bit_number = 7; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h000000000000000000000000FFFFFFFFC0810207C0001A176020155177486D89000000000000000000000000FFFFFFFF80000003C0000217724019F17748EDC900000000000000000000000000000001BF7EFDF9400406B17A400BF57748AD81000000000000000000000000000000013F7EFDF940041EB1724218157749A7910000000000000000000000003F7EFDF90000000140042AF97B426C157DC9B7590000000000000000000000003F7EFDF90000000140042069600246057DC95351000000000000000000000000408102053FFFFFF95FE4084175C246896009F35100000000000000000000000040810207BFFFFFFF7FE4147177C2004960291759; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h7FE8374958F827C15FF88F91E9A80DC3629A9FC172033EC170FB0E8173F792815FE826E158F805C95FF8AF8169A80DC3629A1EC17B033BC1706B3E8173FFB0C1400826E558F805C15DF8AF9169A82DD163C21BC17B133BC1716B3781723F14C1400826E958D825815DD8AF8168482DC161229BC17A133FC171AB3781723F16E9400826E95818058179582F9160480FC162229FC17ACA39C172FB3F8152CF10A1400826E958180D8179580F05614C0DC162329BC171EB398173537F8152E310D1400826E158180D81F8580FD1612C0F41631293C173BB398D63037F81D22313D1400827E958080F01F8188FCB60A40F41435083C1723B198161834F01D67300E3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'hD4FB0D2352268F0151E680016803440977EDE98148F31101BFFFFFFF4081010750FB094B52728F0151FEC0016C034C0153EDA90148F31F013FFFFFFB4081010152F3096156DA8901503ED2016C03480173FDA00148F11F01000000013F7EFEF952E3017156DA85015022C2016C034C0153FCA00148F10F01000000013F7EFEF956B3A9115052850543C2C2116C014D2153FDA12148D11F013F7EFEF900000001469F8B3150728D0143C05A016D014C81537DA00148D11E01BF7EFEF900000001528F8F2156628D0140004E016F054481513DA181C8513E0580000007FFFFFFFF528E8B2156E28C0148024E0167676C415139B041C8513E07C0810107FFFFFFFF; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N18 -cycloneive_lcell_comb \Mux0~0 ( -// Equation(s): -// \Mux0~0_combout = (\z80_|address_pins_|abus[14]~23_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout )))) # (!\z80_|address_pins_|abus[14]~23_combout & -// (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ))) - - .dataa(\z80_|address_pins_|abus[14]~23_combout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout ), - .cin(gnd), - .combout(\Mux0~0_combout ), - .cout()); -// synopsys translate_off -defparam \Mux0~0 .lut_mask = 16'hBA98; -defparam \Mux0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N12 -cycloneive_lcell_comb \Mux0~1 ( -// Equation(s): -// \Mux0~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Mux0~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout )) # (!\Mux0~0_combout & -// ((\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Mux0~0_combout )))) - - .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ), - .datad(\Mux0~0_combout ), - .cin(gnd), - .combout(\Mux0~1_combout ), - .cout()); -// synopsys translate_off -defparam \Mux0~1 .lut_mask = 16'hBBC0; -defparam \Mux0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N22 -cycloneive_lcell_comb \D[7]~112 ( -// Equation(s): -// \D[7]~112_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\Mux0~1_combout ))) -// # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout )))) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout ), - .datad(\Mux0~1_combout ), - .cin(gnd), - .combout(\D[7]~112_combout ), - .cout()); -// synopsys translate_off -defparam \D[7]~112 .lut_mask = 16'hF4B0; -defparam \D[7]~112 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N30 -cycloneive_lcell_comb \D[7]~94 ( -// Equation(s): -// \D[7]~94_combout = (\D[5]~84_combout & (\D[7]~112_combout & ((\z80_|data_pins_|dout [7]) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) # (!\D[5]~84_combout & ((\z80_|data_pins_|dout [7]) # ((!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) - - .dataa(\D[5]~84_combout ), - .datab(\z80_|data_pins_|dout [7]), - .datac(\D[7]~112_combout ), - .datad(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .cin(gnd), - .combout(\D[7]~94_combout ), - .cout()); -// synopsys translate_off -defparam \D[7]~94 .lut_mask = 16'hC4F5; -defparam \D[7]~94 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N26 -cycloneive_lcell_comb \D[7]~102 ( -// Equation(s): -// \D[7]~102_combout = (\D[7]~94_combout ) # (!\D[0]~107_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\D[7]~94_combout ), - .datad(\D[0]~107_combout ), - .cin(gnd), - .combout(\D[7]~102_combout ), - .cout()); -// synopsys translate_off -defparam \D[7]~102 .lut_mask = 16'hF0FF; -defparam \D[7]~102 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N26 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [7] = (\D[7]~102_combout & ((\z80_|pin_control_|bus_db_pin_re~combout ) # ((\z80_|bus_control_|db[7]~7_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\D[7]~102_combout & (\z80_|bus_control_|db[7]~7_combout -// & ((\z80_|execute_|ctl_bus_db_we~7_combout )))) - - .dataa(\D[7]~102_combout ), - .datab(\z80_|bus_control_|db[7]~7_combout ), - .datac(\z80_|pin_control_|bus_db_pin_re~combout ), - .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [7]), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] .lut_mask = 16'hECA0; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y13_N27 -dffeas \z80_|data_pins_|dout[7] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [7]), - .asdata(vcc), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), - .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|data_pins_|dout [7]), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [3]), .prn(vcc)); // synopsys translate_off -defparam \z80_|data_pins_|dout[7] .is_wysiwyg = "true"; -defparam \z80_|data_pins_|dout[7] .power_up = "low"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y13_N2 -cycloneive_lcell_comb \z80_|bus_control_|db[7]~5 ( -// Equation(s): -// \z80_|bus_control_|db[7]~5_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[7]~18_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) - - .dataa(gnd), - .datab(\z80_|alu_control_|db[7]~18_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|bus_control_|db[0]~4_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[7]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[7]~5 .lut_mask = 16'hCF00; -defparam \z80_|bus_control_|db[7]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N8 -cycloneive_lcell_comb \z80_|bus_control_|db[7]~7 ( -// Equation(s): -// \z80_|bus_control_|db[7]~7_combout = ((\z80_|bus_control_|db[7]~5_combout & ((\z80_|data_pins_|dout [7]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - - .dataa(\z80_|data_pins_|dout [7]), - .datab(\z80_|execute_|ctl_bus_db_oe~combout ), - .datac(\z80_|bus_control_|db[0]~6_combout ), - .datad(\z80_|bus_control_|db[7]~5_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[7]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[7]~7 .lut_mask = 16'hBF0F; -defparam \z80_|bus_control_|db[7]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y13_N21 -dffeas \z80_|ir_|opcode[7] ( +// Location: FF_X30_Y12_N29 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), - .asdata(\z80_|bus_control_|db[7]~7_combout ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(vcc), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|ir_|opcode [7]), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]), .prn(vcc)); // synopsys translate_off -defparam \z80_|ir_|opcode[7] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[7] .power_up = "low"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y13_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal77~0 ( +// Location: LCCOMB_X30_Y12_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~44 ( // Equation(s): -// \z80_|pla_decode_|Equal77~0_combout = (!\z80_|ir_|opcode [7] & (!\z80_|decode_state_|DFFE_instCB~q & (\z80_|ir_|opcode [6] & !\z80_|decode_state_|DFFE_instED~q ))) +// \z80_|reg_file_|gdfx_temp0[3]~44_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [3] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [3] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|decode_state_|DFFE_instCB~q ), - .datac(\z80_|ir_|opcode [6]), - .datad(\z80_|decode_state_|DFFE_instED~q ), + .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [3]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), .cin(gnd), - .combout(\z80_|pla_decode_|Equal77~0_combout ), + .combout(\z80_|reg_file_|gdfx_temp0[3]~44_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal77~0 .lut_mask = 16'h0010; -defparam \z80_|pla_decode_|Equal77~0 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|gdfx_temp0[3]~44 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp0[3]~44 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~5 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~5_combout = (\z80_|pla_decode_|Equal77~0_combout & (!\z80_|decode_state_|in_halt~q & (!\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal33~1_combout ))) +// Location: FF_X31_Y11_N21 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[3] .power_up = "low"; +// synopsys translate_on - .dataa(\z80_|pla_decode_|Equal77~0_combout ), - .datab(\z80_|decode_state_|in_halt~q ), - .datac(\z80_|decode_state_|use_ixiy~combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), +// Location: FF_X31_Y11_N11 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~43 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~43_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [3]), + .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [3]), .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~5_combout ), + .combout(\z80_|reg_file_|gdfx_temp0[3]~43_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~5 .lut_mask = 16'h0200; -defparam \z80_|execute_|ctl_mWrite~5 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|gdfx_temp0[3]~43 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[3]~43 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout = (\z80_|pla_decode_|Equal13~0_combout & (\z80_|execute_|ctl_ir_we~4_combout & (\z80_|pla_decode_|Equal8~0_combout & !\z80_|ir_|opcode [3]))) +// Location: FF_X32_Y13_N7 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3] .power_up = "low"; +// synopsys translate_on - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|pla_decode_|Equal8~0_combout ), - .datad(\z80_|ir_|opcode [3]), +// Location: FF_X32_Y14_N13 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~46 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~46_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [3] & ((\z80_|alu_control_|db[3]~35_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (((\z80_|alu_control_|db[3]~35_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [3]), + .datad(\z80_|alu_control_|db[3]~35_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ), + .combout(\z80_|reg_file_|gdfx_temp0[3]~46_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|gdfx_temp0[3]~46 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[3]~46 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y16_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~3 ( +// Location: LCCOMB_X32_Y13_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~47 ( // Equation(s): -// \z80_|execute_|ctl_bus_db_we~3_combout = (\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # (\z80_|execute_|ctl_iorw~11_combout )))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|ctl_mWrite~5_combout ), - .datac(\z80_|execute_|ctl_iorw~11_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~3 .lut_mask = 16'hFFA8; -defparam \z80_|execute_|ctl_bus_db_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_we~8_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|M5~q & ((\z80_|execute_|ctl_mRead~10_combout ) # (\z80_|pla_decode_|Equal9~1_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~8 .lut_mask = 16'h3020; -defparam \z80_|execute_|ctl_bus_db_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_we~2_combout = (\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_mRead~10_combout ) # ((\z80_|pla_decode_|Equal13~2_combout ) # (\z80_|execute_|ctl_mWrite~5_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|ctl_mWrite~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~2 .lut_mask = 16'hCCC8; -defparam \z80_|execute_|ctl_bus_db_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_we~4_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mWrite~4_combout ) # ((\z80_|pla_decode_|Equal21~0_combout & \z80_|pla_decode_|Equal24~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal21~0_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|pla_decode_|Equal24~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~4 .lut_mask = 16'hC8C0; -defparam \z80_|execute_|ctl_bus_db_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_we~6_combout = (((\z80_|execute_|ctl_bus_db_we~4_combout ) # (!\z80_|execute_|ctl_sw_2u~3_combout )) # (!\z80_|execute_|ctl_bus_db_we~5_combout )) # (!\z80_|execute_|ctl_apin_mux~0_combout ) - - .dataa(\z80_|execute_|ctl_apin_mux~0_combout ), - .datab(\z80_|execute_|ctl_bus_db_we~5_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~4_combout ), - .datad(\z80_|execute_|ctl_sw_2u~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~6 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|ctl_bus_db_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_we~7_combout = (\z80_|execute_|ctl_bus_db_we~3_combout ) # ((\z80_|execute_|ctl_bus_db_we~8_combout ) # ((\z80_|execute_|ctl_bus_db_we~2_combout ) # (\z80_|execute_|ctl_bus_db_we~6_combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_we~3_combout ), - .datab(\z80_|execute_|ctl_bus_db_we~8_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~2_combout ), - .datad(\z80_|execute_|ctl_bus_db_we~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~7 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_bus_db_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][2]~50 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][2]~50_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [4]) +// \z80_|reg_file_|gdfx_temp0[3]~47_combout = (\z80_|reg_file_|gdfx_temp0[3]~46_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) .dataa(gnd), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [3]), + .datad(\z80_|reg_file_|gdfx_temp0[3]~46_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][2]~50_combout ), + .combout(\z80_|reg_file_|gdfx_temp0[3]~47_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][2]~50 .lut_mask = 16'h000F; -defparam \ula_|zx_keyboard_|keys[0][2]~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][2]~52 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][2]~52_combout = (\ula_|zx_keyboard_|keys[7][4]~51_combout & ((\ula_|zx_keyboard_|keys[0][2]~50_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[0][2]~50_combout & ((\ula_|zx_keyboard_|keys[0][2]~q -// ))))) # (!\ula_|zx_keyboard_|keys[7][4]~51_combout & (((\ula_|zx_keyboard_|keys[0][2]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[7][4]~51_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[0][2]~q ), - .datad(\ula_|zx_keyboard_|keys[0][2]~50_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][2]~52_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][2]~52 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[0][2]~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y20_N17 -dffeas \ula_|zx_keyboard_|keys[0][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[0][2]~52_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[0][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[0][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][3]~48 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][3]~48_combout = (\ula_|zx_keyboard_|keys[7][4]~19_combout & (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|zx_keyboard_|keys[7][4]~19_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][3]~48_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][3]~48 .lut_mask = 16'h0008; -defparam \ula_|zx_keyboard_|keys[3][3]~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][2]~49 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][2]~49_combout = (\ula_|zx_keyboard_|keys[3][3]~48_combout & ((\ula_|zx_keyboard_|keys[6][4]~47_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[6][4]~47_combout & (\ula_|zx_keyboard_|keys[1][2]~q -// )))) # (!\ula_|zx_keyboard_|keys[3][3]~48_combout & (((\ula_|zx_keyboard_|keys[1][2]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[3][3]~48_combout ), - .datab(\ula_|zx_keyboard_|keys[6][4]~47_combout ), - .datac(\ula_|zx_keyboard_|keys[1][2]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][2]~49_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][2]~49 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[1][2]~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y20_N23 -dffeas \ula_|zx_keyboard_|keys[1][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[1][2]~49_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[1][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[1][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N22 -cycloneive_lcell_comb \D[2]~35 ( -// Equation(s): -// \D[2]~35_combout = (\z80_|address_pins_|abus[8]~18_combout & (((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][2]~q )))) # (!\z80_|address_pins_|abus[8]~18_combout & (!\ula_|zx_keyboard_|keys[0][2]~q & -// ((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][2]~q )))) - - .dataa(\z80_|address_pins_|abus[8]~18_combout ), - .datab(\ula_|zx_keyboard_|keys[0][2]~q ), - .datac(\ula_|zx_keyboard_|keys[1][2]~q ), - .datad(\z80_|address_pins_|abus[9]~17_combout ), - .cin(gnd), - .combout(\D[2]~35_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~35 .lut_mask = 16'hBB0B; -defparam \D[2]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~57 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][2]~57_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [0]) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][2]~57_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][2]~57 .lut_mask = 16'h3300; -defparam \ula_|zx_keyboard_|keys[5][2]~57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~58 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][2]~58_combout = (\ula_|zx_keyboard_|keys[5][2]~57_combout & ((\ula_|zx_keyboard_|keys[5][2]~33_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[5][2]~33_combout & (\ula_|zx_keyboard_|keys[5][2]~q -// )))) # (!\ula_|zx_keyboard_|keys[5][2]~57_combout & (((\ula_|zx_keyboard_|keys[5][2]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[5][2]~57_combout ), - .datab(\ula_|zx_keyboard_|keys[5][2]~33_combout ), - .datac(\ula_|zx_keyboard_|keys[5][2]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][2]~58_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][2]~58 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[5][2]~58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y18_N15 -dffeas \ula_|zx_keyboard_|keys[5][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[5][2]~58_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[5][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[5][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~59 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][2]~59_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|zx_keyboard_|extended~q ))) # (!\ula_|ps2_keyboard_|shiftreg [1] & -// (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|zx_keyboard_|extended~q ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|zx_keyboard_|extended~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][2]~59_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][2]~59 .lut_mask = 16'h0420; -defparam \ula_|zx_keyboard_|keys[4][2]~59 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~131 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][2]~131_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|keys[4][2]~59_combout & (\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [0]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|zx_keyboard_|keys[4][2]~59_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][2]~131_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][2]~131 .lut_mask = 16'h0080; -defparam \ula_|zx_keyboard_|keys[4][2]~131 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~60 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][2]~60_combout = (\ula_|zx_keyboard_|keys[4][2]~131_combout & ((\ula_|zx_keyboard_|keys[3][4]~130_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][4]~130_combout & ((\ula_|zx_keyboard_|keys[4][2]~q -// ))))) # (!\ula_|zx_keyboard_|keys[4][2]~131_combout & (((\ula_|zx_keyboard_|keys[4][2]~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[4][2]~131_combout ), - .datac(\ula_|zx_keyboard_|keys[4][2]~q ), - .datad(\ula_|zx_keyboard_|keys[3][4]~130_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][2]~60_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][2]~60 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[4][2]~60 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y18_N15 -dffeas \ula_|zx_keyboard_|keys[4][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[4][2]~60_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[4][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[4][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N4 -cycloneive_lcell_comb \D[2]~37 ( -// Equation(s): -// \D[2]~37_combout = (\z80_|address_pins_|abus[13]~20_combout & (((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][2]~q )))) # (!\z80_|address_pins_|abus[13]~20_combout & (!\ula_|zx_keyboard_|keys[5][2]~q & -// ((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][2]~q )))) - - .dataa(\z80_|address_pins_|abus[13]~20_combout ), - .datab(\ula_|zx_keyboard_|keys[5][2]~q ), - .datac(\ula_|zx_keyboard_|keys[4][2]~q ), - .datad(\z80_|address_pins_|abus[12]~21_combout ), - .cin(gnd), - .combout(\D[2]~37_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~37 .lut_mask = 16'hBB0B; -defparam \D[2]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][2]~53 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][2]~53_combout = (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [4]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][2]~53_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][2]~53 .lut_mask = 16'h00F0; -defparam \ula_|zx_keyboard_|keys[3][2]~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][2]~55 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][2]~55_combout = (\ula_|zx_keyboard_|keys[7][4]~19_combout & (\ula_|zx_keyboard_|keys[3][2]~53_combout & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|zx_keyboard_|Equal0~2_combout ))) - - .dataa(\ula_|zx_keyboard_|keys[7][4]~19_combout ), - .datab(\ula_|zx_keyboard_|keys[3][2]~53_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|zx_keyboard_|Equal0~2_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][2]~55_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][2]~55 .lut_mask = 16'h0800; -defparam \ula_|zx_keyboard_|keys[2][2]~55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][2]~56 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][2]~56_combout = (\ula_|zx_keyboard_|keys[2][2]~55_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[2][2]~55_combout & ((\ula_|zx_keyboard_|keys[2][2]~q ))) - - .dataa(gnd), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[2][2]~q ), - .datad(\ula_|zx_keyboard_|keys[2][2]~55_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][2]~56_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][2]~56 .lut_mask = 16'h33F0; -defparam \ula_|zx_keyboard_|keys[2][2]~56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y20_N27 -dffeas \ula_|zx_keyboard_|keys[2][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[2][2]~56_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[2][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[2][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][2]~54 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][2]~54_combout = (\ula_|zx_keyboard_|keys[7][4]~51_combout & ((\ula_|zx_keyboard_|keys[3][2]~53_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][2]~53_combout & ((\ula_|zx_keyboard_|keys[3][2]~q -// ))))) # (!\ula_|zx_keyboard_|keys[7][4]~51_combout & (((\ula_|zx_keyboard_|keys[3][2]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[7][4]~51_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[3][2]~q ), - .datad(\ula_|zx_keyboard_|keys[3][2]~53_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][2]~54_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][2]~54 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[3][2]~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y20_N29 -dffeas \ula_|zx_keyboard_|keys[3][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[3][2]~54_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[3][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[3][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N8 -cycloneive_lcell_comb \D[2]~36 ( -// Equation(s): -// \D[2]~36_combout = (\ula_|zx_keyboard_|keys[2][2]~q & (\z80_|address_pins_|abus[10]~24_combout & ((\z80_|address_pins_|abus[11]~19_combout ) # (!\ula_|zx_keyboard_|keys[3][2]~q )))) # (!\ula_|zx_keyboard_|keys[2][2]~q & -// (((\z80_|address_pins_|abus[11]~19_combout )) # (!\ula_|zx_keyboard_|keys[3][2]~q ))) - - .dataa(\ula_|zx_keyboard_|keys[2][2]~q ), - .datab(\ula_|zx_keyboard_|keys[3][2]~q ), - .datac(\z80_|address_pins_|abus[10]~24_combout ), - .datad(\z80_|address_pins_|abus[11]~19_combout ), - .cin(gnd), - .combout(\D[2]~36_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~36 .lut_mask = 16'hF531; -defparam \D[2]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~68 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][2]~68_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [1]))) # (!\ula_|ps2_keyboard_|shiftreg [4] & -// (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [1]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][2]~68_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][2]~68 .lut_mask = 16'h0180; -defparam \ula_|zx_keyboard_|keys[6][2]~68 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~69 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][2]~69_combout = (\ula_|zx_keyboard_|keys[6][1]~41_combout & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|zx_keyboard_|keys[6][2]~68_combout )) - - .dataa(\ula_|zx_keyboard_|keys[6][1]~41_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(gnd), - .datad(\ula_|zx_keyboard_|keys[6][2]~68_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][2]~69_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][2]~69 .lut_mask = 16'h2200; -defparam \ula_|zx_keyboard_|keys[6][2]~69 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~70 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][2]~70_combout = (\ula_|zx_keyboard_|keys[6][2]~69_combout & (!\ula_|zx_keyboard_|keys[5][0]~67_combout )) # (!\ula_|zx_keyboard_|keys[6][2]~69_combout & ((\ula_|zx_keyboard_|keys[6][2]~q ))) - - .dataa(\ula_|zx_keyboard_|keys[5][0]~67_combout ), - .datab(\ula_|zx_keyboard_|keys[6][2]~69_combout ), - .datac(\ula_|zx_keyboard_|keys[6][2]~q ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][2]~70_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][2]~70 .lut_mask = 16'h7474; -defparam \ula_|zx_keyboard_|keys[6][2]~70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y20_N1 -dffeas \ula_|zx_keyboard_|keys[6][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[6][2]~70_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[6][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[6][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y21_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~61 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~61_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [5]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~61_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~61 .lut_mask = 16'h0F00; -defparam \ula_|zx_keyboard_|keys[7][2]~61 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y21_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~62 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~62_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|zx_keyboard_|keys[7][2]~61_combout & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [0]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|zx_keyboard_|keys[7][2]~61_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~62_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~62 .lut_mask = 16'h0080; -defparam \ula_|zx_keyboard_|keys[7][2]~62 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y21_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~64 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~64_combout = (\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[7][2]~62_combout ) # ((\ula_|zx_keyboard_|keys[5][4]~63_combout & \ula_|zx_keyboard_|keys[7][2]~32_combout )))) - - .dataa(\ula_|zx_keyboard_|keys[5][4]~63_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|zx_keyboard_|keys[7][2]~62_combout ), - .datad(\ula_|zx_keyboard_|keys[7][2]~32_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~64_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~64 .lut_mask = 16'hC8C0; -defparam \ula_|zx_keyboard_|keys[7][2]~64 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y21_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~65 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~65_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|zx_keyboard_|extended~q & (\ula_|zx_keyboard_|keys[0][0]~15_combout & \ula_|zx_keyboard_|keys[7][2]~64_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|zx_keyboard_|extended~q ), - .datac(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .datad(\ula_|zx_keyboard_|keys[7][2]~64_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~65_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~65 .lut_mask = 16'h1000; -defparam \ula_|zx_keyboard_|keys[7][2]~65 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|Selector13~0 ( -// Equation(s): -// \ula_|zx_keyboard_|Selector13~0_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & !\ula_|ps2_keyboard_|shiftreg [5])) - - .dataa(\ula_|zx_keyboard_|shifted~q ), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(gnd), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|Selector13~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|Selector13~0 .lut_mask = 16'hFF22; -defparam \ula_|zx_keyboard_|Selector13~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y21_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~66 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~66_combout = (\ula_|zx_keyboard_|keys[7][2]~65_combout & ((!\ula_|zx_keyboard_|Selector13~0_combout ))) # (!\ula_|zx_keyboard_|keys[7][2]~65_combout & (\ula_|zx_keyboard_|keys[7][2]~q )) - - .dataa(\ula_|zx_keyboard_|keys[7][2]~65_combout ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[7][2]~q ), - .datad(\ula_|zx_keyboard_|Selector13~0_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~66_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~66 .lut_mask = 16'h50FA; -defparam \ula_|zx_keyboard_|keys[7][2]~66 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y21_N13 -dffeas \ula_|zx_keyboard_|keys[7][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[7][2]~66_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[7][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[7][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y21_N0 -cycloneive_lcell_comb \D[2]~38 ( -// Equation(s): -// \D[2]~38_combout = (\z80_|address_pins_|abus[15]~22_combout & (((\z80_|address_pins_|abus[14]~23_combout )) # (!\ula_|zx_keyboard_|keys[6][2]~q ))) # (!\z80_|address_pins_|abus[15]~22_combout & (!\ula_|zx_keyboard_|keys[7][2]~q & -// ((\z80_|address_pins_|abus[14]~23_combout ) # (!\ula_|zx_keyboard_|keys[6][2]~q )))) - - .dataa(\z80_|address_pins_|abus[15]~22_combout ), - .datab(\ula_|zx_keyboard_|keys[6][2]~q ), - .datac(\z80_|address_pins_|abus[14]~23_combout ), - .datad(\ula_|zx_keyboard_|keys[7][2]~q ), - .cin(gnd), - .combout(\D[2]~38_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~38 .lut_mask = 16'hA2F3; -defparam \D[2]~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N14 -cycloneive_lcell_comb \D[2]~39 ( -// Equation(s): -// \D[2]~39_combout = (\D[2]~35_combout & (\D[2]~37_combout & (\D[2]~36_combout & \D[2]~38_combout ))) - - .dataa(\D[2]~35_combout ), - .datab(\D[2]~37_combout ), - .datac(\D[2]~36_combout ), - .datad(\D[2]~38_combout ), - .cin(gnd), - .combout(\D[2]~39_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~39 .lut_mask = 16'h8000; -defparam \D[2]~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N14 -cycloneive_lcell_comb \D[2]~104 ( -// Equation(s): -// \D[2]~104_combout = ((\z80_|address_pins_|DFFE_apin_latch [0]) # (\D[2]~39_combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [0]), - .datad(\D[2]~39_combout ), - .cin(gnd), - .combout(\D[2]~104_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~104 .lut_mask = 16'hFFF3; -defparam \D[2]~104 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y8_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a26 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[2]~46_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_first_bit_number = 2; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y12_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a10 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[2]~46_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y9_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a18 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[2]~46_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_first_bit_number = 2; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y12_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a2 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[2]~46_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N8 -cycloneive_lcell_comb \D[2]~43 ( -// Equation(s): -// \D[2]~43_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout )))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ), - .cin(gnd), - .combout(\D[2]~43_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~43 .lut_mask = 16'hB9A8; -defparam \D[2]~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N6 -cycloneive_lcell_comb \D[2]~44 ( -// Equation(s): -// \D[2]~44_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[2]~43_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout )) # (!\D[2]~43_combout & -// ((\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ))))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[2]~43_combout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ), - .datad(\D[2]~43_combout ), - .cin(gnd), - .combout(\D[2]~44_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~44 .lut_mask = 16'hBBC0; -defparam \D[2]~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y17_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a10 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h8102080042447C443C0C3C402004FC1838787840407A00707C02487E444878428008004042460424402040024A3242124220044022404208520A4A24424A125A0A1028440000524A0A4A4A204A5240460800100010540042002064547E0600001FA9BE02B828694B8A82CB8C8158226808198E9EC6B021F07A2098D5E0ECB639D2B1908129B6A2D646516192D87593189D8B2B26CD6E16234C1CC90AD9831EBD89EAD271ECC39A80507716BB49626B743DFFCF99576C3FAC889860E46618ACB79EC30EEDE42EB1E31F3976CA23243179FAA96DCD66D51535351770D410DC8531866136E6184518410368288C446EC63A4FEE425019C244097049C2B2DC8D93C4; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'hA111466C9493A2A7CA2204102414CC798BF0EEC2995A4814580BD07585585ED92E5172E82E845070000A846100500E84EA1803B8B07B99E1DC75BE6419674597B38F54EB9091AE3320201EE395AD63902282A031CE3E87CC902954AA515D5D6B6A855EC94CFEC4E0172C59A7D054F8F9F4356C312C204E40B05E2059407C8DC84683814663FB910969D1D631A952B381B7F635A33FD38D5CF15DF47D057F7FF555B555C2278100000A24804D7D98EB98602733818A12094F281287422CB40002464C92242004E0AE8518E001D124A7628010115D23C30462FC00A014A12133582A191E00538FC8A5004036A959ACB7A463D23E419EA06B744005385455A71250; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h6C60009CA281AEACDC1762945981B869F93D683EAF4AC7EE52412E85B60B91CD03AD0025F0D509F63202D877ECD8BF8005451F7BD346CF9E17B36F1850A7D80A8CF14A288EAE3BFE00FB2DB45080D4A50C58263A3B398DD51AB9CB554ECAA7B2E73D9D6D2C265859DB844C2C1952AD10241100174FE0444E6707D80A098D8585AAAC4802B74190FB007C0C0206186AFC1B3A2A46864F26118ED1D03ACB1062B7315502751655F60070E6B2C50609369611365AD1E3352327320331A51818030C7D8C4C59396600DC0C420495A0D987501490002BAD38012E20620D556A230B1796450B74E95A860FF3E434C65F1308F16F92395816B914F0CE870C1323347A4E; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h7FC8531A7A319F3EBFC1383FFCDB0E09BD288288B078B4AD220B6FA934CF6187D972662C0D31E34E63B31CFC6EB4B35A69B67D85489E62EA99899A94F6800FDBA5D31B86A0288D29CE2EAAFF86A6A9F7000082293E6BB54F06E98ECCB199973EDA00FADB1D3A630BA18050635DE7DCB13B9B86E0CE6E08DC46331A352F716E3C441A0CC068A0823F8668A00621B779DE35FEC004050469F34866AEE766743D8C00FDF3B9F8DE7B76E97F8D32F0F39E4CAC68D9BBB68EA3915F6225F932CAAFDAD6E60DC661155EC9E80F8CEE659F19CC554B2C67C33EDCDA63BAD91B7D1842A7177AF49DF118FE47ACE3344964EBCADCFBB543F7729CCB340866D1157B6CCDDB; -// synopsys translate_on - -// Location: M9K_X33_Y28_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a10 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(gnd), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[2]~46_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_first_bit_number = 2; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N12 -cycloneive_lcell_comb \D[2]~40 ( -// Equation(s): -// \D[2]~40_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))) # (!\z80_|address_pins_|abus[14]~23_combout -// & (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ))) - - .dataa(\z80_|address_pins_|abus[14]~23_combout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout ), - .cin(gnd), - .combout(\D[2]~40_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~40 .lut_mask = 16'hEA62; -defparam \D[2]~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y31_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a2 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[2]~46_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_bit_number = 2; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF00000000FFFFFFFFFFFFFFFFFFF68003FFF38003FFF9F403FFF8B003D8F87003FFF8F01BEDFC701FEBFEA01FDBFDC00FDBFDC01FC7FDC0FFC7FDE87FC7FCDC8FC7FCF89FC07071FFC0F873F3E0303FE7FFFFFFFFFFFFFFFF; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000000040078400234B1474928D1000000000000000000000000FFFFFFFF204081024004027153423DA5474928DD000000000000000000000000000000003FFFFFFF40041CB14162378547495999000000000000000000000000000000003FFFFFFF4004189141623485474959F90000000000000000000000003FFFFFFE40000001400400815B6223C15FC913DD0000000000000000000000007FFFFFFE40000001400402E9400333715FC973E5000000000000000000000000604081027FFFFFFD5FE60AE95763353540091361000000000000000000000000400000003FFFFFFC5FE60AE95763081D40011361; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h5FE0236948F816F55FE897C10C28028041DC8DE178059BC16900BB4173E47AC15FE8236148E806F55FE891054CA80E8148288DE179E597C169903AC153F13A8140080365486806D55FE891D548080A8148608FE159E493C16BB03FD152BD1AE14008037D482017D15FE881C548A00AC148E08FE159FC9AC16AA02FC15AAF18F1400083F1482007C15EE882C148E00A4148B08FE148F88D4168E436915ABB01E9400092F9480007815C2882C148E00B6149B49F614868FD41436476814AFA42A1400892FD480807C15C0883C149800FE149DC9FE14A60BD41431C3F914AEA01C1400882F1480817C11C0883C041940FE549CC9EE54860BDC143BC7D8108D2C4D0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h0B928870484885014DE84481680162815375AC0148D308813FFFFFFC400000004B9288314DC0970149FC44856C0166815375AC8140D108817FFFFFFD6040808249D0A2094F908581481C40814C016099417DA88140D10B01400000017FFFFFFE48D083394B9085814A085081440166814179900140510F01400000013FFFFFFE4A508335498001814BE0608146016E8941799041405107413FFFFFFF000000004B98812149C005814BE0628146836E814179100140510F013FFFFFFF000000004B98A1114BE801814A00668147832C814119904140401F4120408082FFFFFFFF48D881154EA801854800768147C22CC14019900100003E0000000000FFFFFFFF; -// synopsys translate_on - -// Location: M9K_X33_Y17_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a2 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h77A47C739FF6A22B8B5CDC49E748E9C739BDE6756DB4D22437E74183E12400CBF7D3C6CC8C7841AB49CC538E8A72F2E73C64D3DF3662B19C07D7D299CBEDEF3E7DA5F4A8458A9451315B681ADA9AB0D63218DFB77D3353C32837E954604B9D98144A4566F47B71715BE6CDB8BA64D536762E9224D70F9A5C374B4D1CAB8DF527027170C5DBCC2B6AD72B8E4CCC94DAA139D8BA64E3384337426E7F274CC88A373AB1F9007B8A7F2936D16274F9BF8B6BABD48FCE74047C1E738C5B303E815BA720C76D6362915156A7671331CE657011862E594E46A6D99392E2D640D766869389A4D43867379AB880C1ACE279E451CB3A9063A0B320F65E536B8EEF9CBB9C76; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h9A2921ED6AA0CC8387B267B9E7A182720833CEE061E6450C8E4A72E3C043F21A0AD007E832124E92429C091D167806C10041AF32DDE13A669990457D098CC2FE3AC884B1E69101135CD080022451F20884CCB9CD203C141402A5AD293C3BABA95ADFAF6726384795A7656B753D2369B9EB5595BAA722012DF8DCFBF15BF46D6EB755D1CBF0DCF6FD40BEEC16EAB4A6D16839C98CBE9DBB437C69FB709F8E79993B9DDFE4F823D6E124B75BCE9B29F799F926619184B6C1178389F07349210436293A130C900FBA4EA70D2BA25B343C5B026D8E8766A4E4267CDAEC99E830D2307D94E6ED80D6722F3989B91E31C63B64C363DCE71A861C14382E270FC02868C7; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h386BA04E797A3F8551DAD9D24A8D259A03ECFF5AB81B1C31DFDAE10100544F8CF1A8CCFC0C7A15BD9E7C2557CB00BF2584E16AAD13D7EDB525A85ABF90C0136DD195D748900C29DF7F381280A9738CDC3BF5BBF937D3A4D99CE2BCCD97CEF2C7F00030AFDB7F22E68CBAA4D9BE7633D3B53E90E4B124422A2A4454BACA5A8DC9352CD1DAFC910CC504334DF9E6F1F4F30161A36293CC5CCF1CA13994ED29D34A5699692496359B8E67A7E74D9A0FC504C8465638CF74A0AF9185921A7D2629893091900604017933442359491FBAB63F346F0C5EC8E3A531984B09E605A30A0627271C28420E47B8DEC74738FC3EDF9FBD40EC09FC7B4D3A1475BE433705FB5F; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h973FED2E9BEDBA474B70B121A8D60F3B4EE3F1A238FB3B730EDEEE74EC632DB4D7779D7B79D1C75DF87378E98719C1AF38B1B801C71D180CE86370AE9C2BF38CF84DBBB9878C55457324E92D3DAE91D729AC76BBAD4C6EECA74DAB5EE9A175EE34ABEB9DFAA48538A57E3E5C158947081CA41402E8E65478737F73BB629AAE2EE51D405CAF70F622DD4599602D7910DCAC8214B2A42025110593202C8B164C8DF6369572C3BB8AA1984A8D12F776E224ECEEB21F97FCD6C0CF17A044EC2BBF0571A553CCDD8ABA79BD27B7AF735ED2D34F1EF3A81A160C9ECB1B1FAE6EDEEFF99E28CC30C7C2553DED3378D655AD194B2E6C1BCBED700F6713D960F33E4C361A; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N16 -cycloneive_lcell_comb \D[2]~41 ( -// Equation(s): -// \D[2]~41_combout = (\z80_|address_pins_|abus[15]~22_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout $ (\D[2]~40_combout )))) # (!\z80_|address_pins_|abus[15]~22_combout & -// (\rom|altsyncram_component|auto_generated|ram_block1a2~portadataout & ((!\D[2]~40_combout )))) - - .dataa(\z80_|address_pins_|abus[15]~22_combout ), - .datab(\rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ), - .datad(\D[2]~40_combout ), - .cin(gnd), - .combout(\D[2]~41_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~41 .lut_mask = 16'h0AE4; -defparam \D[2]~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N30 -cycloneive_lcell_comb \D[2]~42 ( -// Equation(s): -// \D[2]~42_combout = (\D[2]~40_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout & !\D[2]~41_combout )))) # (!\D[2]~40_combout & -// (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[2]~41_combout )))) - - .dataa(\D[2]~40_combout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ), - .datad(\D[2]~41_combout ), - .cin(gnd), - .combout(\D[2]~42_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~42 .lut_mask = 16'h99A8; -defparam \D[2]~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N0 -cycloneive_lcell_comb \D[2]~105 ( -// Equation(s): -// \D[2]~105_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (\D[2]~44_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\D[2]~42_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & -// (\D[2]~44_combout )))) - - .dataa(\D[2]~44_combout ), - .datab(\z80_|address_pins_|DFFE_apin_latch [15]), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\D[2]~42_combout ), - .cin(gnd), - .combout(\D[2]~105_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~105 .lut_mask = 16'hBA8A; -defparam \D[2]~105 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N28 -cycloneive_lcell_comb \D[2]~45 ( -// Equation(s): -// \D[2]~45_combout = ((\Equal2~0_combout & (\D[2]~104_combout )) # (!\Equal2~0_combout & ((\D[2]~105_combout )))) # (!\Equal2~1_combout ) - - .dataa(\Equal2~0_combout ), - .datab(\Equal2~1_combout ), - .datac(\D[2]~104_combout ), - .datad(\D[2]~105_combout ), - .cin(gnd), - .combout(\D[2]~45_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~45 .lut_mask = 16'hF7B3; -defparam \D[2]~45 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|gdfx_temp0[3]~47 .lut_mask = 16'hF300; +defparam \z80_|reg_file_|gdfx_temp0[3]~47 .sum_lutc_input = "datac"; // synopsys translate_on // Location: LCCOMB_X31_Y12_N30 -cycloneive_lcell_comb \D[2]~46 ( +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder ( // Equation(s): -// \D[2]~46_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout & (\z80_|data_pins_|dout [2] & ((\D[2]~45_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\D[2]~45_combout ) # (!\Equal2~1_combout )))) +// \z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp0[3]~52_combout - .dataa(\z80_|data_pins_|dout [2]), - .datab(\Equal2~1_combout ), - .datac(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datad(\D[2]~45_combout ), + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), .cin(gnd), - .combout(\D[2]~46_combout ), + .combout(\z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder_combout ), .cout()); // synopsys translate_off -defparam \D[2]~46 .lut_mask = 16'hAF03; -defparam \D[2]~46 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N2 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [2] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[2]~13_combout ) # ((\z80_|pin_control_|bus_db_pin_re~combout & \D[2]~46_combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & -// (\z80_|pin_control_|bus_db_pin_re~combout & (\D[2]~46_combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(\z80_|pin_control_|bus_db_pin_re~combout ), - .datac(\D[2]~46_combout ), - .datad(\z80_|bus_control_|db[2]~13_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [2]), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] .lut_mask = 16'hEAC0; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y12_N3 -dffeas \z80_|data_pins_|dout[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [2]), +// Location: FF_X31_Y12_N31 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|data_pins_|dout [2]), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [3]), .prn(vcc)); // synopsys translate_off -defparam \z80_|data_pins_|dout[2] .is_wysiwyg = "true"; -defparam \z80_|data_pins_|dout[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N18 -cycloneive_lcell_comb \z80_|bus_control_|db[2]~12 ( -// Equation(s): -// \z80_|bus_control_|db[2]~12_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[2]~29_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) - - .dataa(gnd), - .datab(\z80_|alu_control_|db[2]~29_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|bus_control_|db[0]~4_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[2]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[2]~12 .lut_mask = 16'hCF00; -defparam \z80_|bus_control_|db[2]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N12 -cycloneive_lcell_comb \z80_|bus_control_|db[2]~13 ( -// Equation(s): -// \z80_|bus_control_|db[2]~13_combout = ((\z80_|bus_control_|db[2]~12_combout & ((\z80_|data_pins_|dout [2]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - - .dataa(\z80_|data_pins_|dout [2]), - .datab(\z80_|bus_control_|db[0]~6_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~combout ), - .datad(\z80_|bus_control_|db[2]~12_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[2]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[2]~13 .lut_mask = 16'hBF33; -defparam \z80_|bus_control_|db[2]~13 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[3] .power_up = "low"; // synopsys translate_on // Location: FF_X32_Y12_N13 -dffeas \z80_|ir_|opcode[2] ( +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[3] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|bus_control_|db[2]~13_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|ir_|opcode [2]), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [3]), .prn(vcc)); // synopsys translate_off -defparam \z80_|ir_|opcode[2] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[2] .power_up = "low"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X38_Y16_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal3~1 ( +// Location: LCCOMB_X32_Y12_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~49 ( // Equation(s): -// \z80_|pla_decode_|Equal3~1_combout = (\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [1]) +// \z80_|reg_file_|gdfx_temp0[3]~49_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [3]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_iy_lo|latch [3]), + .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~49_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~49 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[3]~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y11_N27 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N12 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp0[3]~52_combout .dataa(gnd), .datab(gnd), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal3~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal3~1 .lut_mask = 16'h00F0; -defparam \z80_|pla_decode_|Equal3~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N26 -cycloneive_lcell_comb \z80_|pla_decode_|Equal43~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal43~0_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal32~0_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal1~7_combout ))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|pla_decode_|Equal32~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal1~7_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal43~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal43~0 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal43~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N24 -cycloneive_lcell_comb \z80_|interrupts_|test1~2 ( -// Equation(s): -// \z80_|interrupts_|test1~2_combout = (!\z80_|pla_decode_|Equal43~0_combout & (!\z80_|pla_decode_|Equal3~2_combout & (!\z80_|pla_decode_|Equal79~0_combout & !\z80_|pla_decode_|Equal36~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal43~0_combout ), - .datab(\z80_|pla_decode_|Equal3~2_combout ), - .datac(\z80_|pla_decode_|Equal79~0_combout ), - .datad(\z80_|pla_decode_|Equal36~0_combout ), - .cin(gnd), - .combout(\z80_|interrupts_|test1~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|interrupts_|test1~2 .lut_mask = 16'h0001; -defparam \z80_|interrupts_|test1~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N26 -cycloneive_lcell_comb \z80_|interrupts_|test1~3 ( -// Equation(s): -// \z80_|interrupts_|test1~3_combout = (!\z80_|execute_|setM1~52_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((\z80_|interrupts_|test1~2_combout ) # (!\z80_|sequencer_|DFFE_T4_ff~q )))) - - .dataa(\z80_|execute_|setM1~52_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|interrupts_|test1~2_combout ), - .cin(gnd), - .combout(\z80_|interrupts_|test1~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|interrupts_|test1~3 .lut_mask = 16'h5545; -defparam \z80_|interrupts_|test1~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y15_N13 -dffeas \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|interrupts_|test1~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED .is_wysiwyg = "true"; -defparam \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N2 -cycloneive_lcell_comb \z80_|clk_delay_|SYNTHESIZED_WIRE_4 ( -// Equation(s): -// \z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (!\z80_|sequencer_|DFFE_M1_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|interrupts_|DFFE_inst44~q ))) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|interrupts_|DFFE_inst44~q ), - .cin(gnd), - .combout(\z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_4 .lut_mask = 16'h0100; -defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X43_Y15_N3 -dffeas \z80_|clk_delay_|SYNTHESIZED_WIRE_7 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_7 .is_wysiwyg = "true"; -defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_7 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N20 -cycloneive_lcell_comb \z80_|clk_delay_|hold_clk_iorq ( -// Equation(s): -// \z80_|clk_delay_|hold_clk_iorq~combout = (!\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q & !\z80_|clk_delay_|DFF_inst5~q ) - - .dataa(gnd), - .datab(\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ), .datac(gnd), - .datad(\z80_|clk_delay_|DFF_inst5~q ), + .datad(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), .cin(gnd), - .combout(\z80_|clk_delay_|hold_clk_iorq~combout ), + .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder_combout ), .cout()); // synopsys translate_off -defparam \z80_|clk_delay_|hold_clk_iorq .lut_mask = 16'h0033; -defparam \z80_|clk_delay_|hold_clk_iorq .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y17_N13 -dffeas \z80_|sequencer_|DFFE_T1_ff ( +// Location: FF_X32_Y11_N13 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[3] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|ena_M~combout ), + .d(\z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder_combout ), .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|sequencer_|DFFE_T1_ff~q ), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [3]), .prn(vcc)); // synopsys translate_off -defparam \z80_|sequencer_|DFFE_T1_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_T1_ff .power_up = "low"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y17_N4 -cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_13 ( +// Location: LCCOMB_X32_Y11_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~45 ( // Equation(s): -// \z80_|sequencer_|SYNTHESIZED_WIRE_13~combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|execute_|setM1~52_combout & !\z80_|execute_|nextM~14_combout )) +// \z80_|reg_file_|gdfx_temp0[3]~45_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(gnd), - .datac(\z80_|execute_|setM1~52_combout ), - .datad(\z80_|execute_|nextM~14_combout ), + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [3]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [3]), .cin(gnd), - .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ), + .combout(\z80_|reg_file_|gdfx_temp0[3]~45_combout ), .cout()); // synopsys translate_off -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_13 .lut_mask = 16'h0050; -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_13 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|gdfx_temp0[3]~45 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[3]~45 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y17_N5 -dffeas \z80_|sequencer_|DFFE_T2_ff ( +// Location: FF_X32_Y13_N17 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[3] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|sequencer_|DFFE_T2_ff~q ), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [3]), .prn(vcc)); // synopsys translate_off -defparam \z80_|sequencer_|DFFE_T2_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_T2_ff .power_up = "low"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X35_Y13_N10 -cycloneive_lcell_comb \z80_|resets_|x3 ( -// Equation(s): -// \z80_|resets_|x3~combout = (\z80_|resets_|x1~q ) # ((\z80_|sequencer_|DFFE_T2_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )) +// Location: FF_X32_Y14_N15 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[3] .power_up = "low"; +// synopsys translate_on - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(gnd), - .datac(\z80_|resets_|x1~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), +// Location: LCCOMB_X32_Y14_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~48 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~48_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (\z80_|reg_file_|b2v_latch_ix_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_ix_lo|latch [3]), + .datac(\z80_|reg_file_|b2v_latch_bc_lo|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), .cin(gnd), - .combout(\z80_|resets_|x3~combout ), + .combout(\z80_|reg_file_|gdfx_temp0[3]~48_combout ), .cout()); // synopsys translate_off -defparam \z80_|resets_|x3 .lut_mask = 16'hF0FA; -defparam \z80_|resets_|x3 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|gdfx_temp0[3]~48 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp0[3]~48 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X35_Y13_N11 -dffeas \z80_|resets_|SYNTHESIZED_WIRE_12 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|resets_|x3~combout ), - .asdata(vcc), - .clrn(\z80_|fpga_reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_12 .is_wysiwyg = "true"; -defparam \z80_|resets_|SYNTHESIZED_WIRE_12 .power_up = "low"; -// synopsys translate_on - -// Location: CLKCTRL_G7 -cycloneive_clkctrl \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl ( - .ena(vcc), - .inclk({vcc,vcc,vcc,\z80_|resets_|SYNTHESIZED_WIRE_12~q }), - .clkselect(2'b00), - .devclrn(devclrn), - .devpor(devpor), - .outclk(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk )); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl .clock_type = "global clock"; -defparam \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl .ena_register_mode = "none"; -// synopsys translate_on - -// Location: FF_X32_Y17_N21 -dffeas \z80_|sequencer_|DFFE_M1_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|DFFE_M1_ff~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|DFFE_M1_ff~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_M1_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_M1_ff .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N10 -cycloneive_lcell_comb \z80_|sequencer_|DFFE_M2_ff~0 ( +// Location: LCCOMB_X32_Y11_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~50 ( // Equation(s): -// \z80_|sequencer_|DFFE_M2_ff~0_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|execute_|nextM~14_combout & (!\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|DFFE_M2_ff~q ))))) +// \z80_|reg_file_|gdfx_temp0[3]~50_combout = (\z80_|reg_file_|gdfx_temp0[3]~47_combout & (\z80_|reg_file_|gdfx_temp0[3]~49_combout & (\z80_|reg_file_|gdfx_temp0[3]~45_combout & \z80_|reg_file_|gdfx_temp0[3]~48_combout ))) - .dataa(\z80_|execute_|setM1~52_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|execute_|nextM~14_combout ), + .dataa(\z80_|reg_file_|gdfx_temp0[3]~47_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[3]~49_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[3]~45_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[3]~48_combout ), .cin(gnd), - .combout(\z80_|sequencer_|DFFE_M2_ff~0_combout ), + .combout(\z80_|reg_file_|gdfx_temp0[3]~50_combout ), .cout()); // synopsys translate_off -defparam \z80_|sequencer_|DFFE_M2_ff~0 .lut_mask = 16'h22A0; -defparam \z80_|sequencer_|DFFE_M2_ff~0 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|gdfx_temp0[3]~50 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[3]~50 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y17_N11 -dffeas \z80_|sequencer_|DFFE_M2_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|DFFE_M2_ff~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|DFFE_M2_ff~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_M2_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_M2_ff .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~3 ( +// Location: LCCOMB_X31_Y11_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~51 ( // Equation(s): -// \z80_|execute_|ctl_mWrite~3_combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ) +// \z80_|reg_file_|gdfx_temp0[3]~51_combout = (\z80_|reg_file_|gdfx_temp0[3]~44_combout & (\z80_|reg_file_|gdfx_temp0[3]~43_combout & \z80_|reg_file_|gdfx_temp0[3]~50_combout )) + + .dataa(\z80_|reg_file_|gdfx_temp0[3]~44_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[3]~43_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[3]~50_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~51 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|gdfx_temp0[3]~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~52 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~52_combout = ((\z80_|reg_file_|gdfx_temp0[3]~51_combout & ((\z80_|reg_file_|db_lo_as[3]~12_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), + .datac(\z80_|reg_file_|db_lo_as[3]~12_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~52 .lut_mask = 16'hC4FF; +defparam \z80_|reg_file_|gdfx_temp0[3]~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N20 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_35 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout = (\z80_|execute_|ctl_flags_bus~combout & ((\z80_|alu_control_|db[3]~35_combout ) # ((\z80_|execute_|ctl_flags_alu~15_combout & \z80_|alu_|db_low[3]~25_combout )))) # (!\z80_|execute_|ctl_flags_bus~combout +// & (((\z80_|execute_|ctl_flags_alu~15_combout & \z80_|alu_|db_low[3]~25_combout )))) + + .dataa(\z80_|execute_|ctl_flags_bus~combout ), + .datab(\z80_|alu_control_|db[3]~35_combout ), + .datac(\z80_|execute_|ctl_flags_alu~15_combout ), + .datad(\z80_|alu_|db_low[3]~25_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_35 .lut_mask = 16'hF888; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~15 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~15_combout = (\z80_|execute_|ctl_state_alu~2_combout & ((\z80_|execute_|ctl_ir_we~12_combout ) # ((\z80_|execute_|ctl_alu_op_low~22_combout & \z80_|pla_decode_|Equal56~0_combout )))) # +// (!\z80_|execute_|ctl_state_alu~2_combout & (\z80_|execute_|ctl_alu_op_low~22_combout & (\z80_|pla_decode_|Equal56~0_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datac(\z80_|pla_decode_|Equal56~0_combout ), + .datad(\z80_|execute_|ctl_ir_we~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~15 .lut_mask = 16'hEAC0; +defparam \z80_|execute_|ctl_flags_xy_we~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~16 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~16_combout = (\z80_|execute_|ctl_flags_xy_we~15_combout ) # ((\z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ) # (!\z80_|execute_|ctl_flags_xy_we~12_combout )) .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|execute_|ctl_flags_xy_we~15_combout ), + .datac(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~12_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~3_combout ), + .combout(\z80_|execute_|ctl_flags_xy_we~16_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~3 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_mWrite~3 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_flags_xy_we~16 .lut_mask = 16'hFCFF; +defparam \z80_|execute_|ctl_flags_xy_we~16 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X41_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|nextM~11 ( +// Location: LCCOMB_X28_Y18_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~17 ( // Equation(s): -// \z80_|execute_|nextM~11_combout = ((!\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_alu_op_low~12_combout & !\z80_|execute_|ctl_alu_op_low~11_combout ))) # (!\z80_|execute_|ctl_mWrite~3_combout ) +// \z80_|execute_|ctl_flags_xy_we~17_combout = (\z80_|execute_|ctl_flags_xy_we~16_combout ) # (((!\z80_|execute_|ctl_flags_xy_we~19_combout ) # (!\z80_|execute_|ctl_flags_xy_we~9_combout )) # (!\z80_|execute_|ctl_flags_xy_we~11_combout )) - .dataa(\z80_|execute_|ctl_mWrite~3_combout ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~12_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~11_combout ), + .dataa(\z80_|execute_|ctl_flags_xy_we~16_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~11_combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~9_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~19_combout ), .cin(gnd), - .combout(\z80_|execute_|nextM~11_combout ), + .combout(\z80_|execute_|ctl_flags_xy_we~17_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|nextM~11 .lut_mask = 16'h5557; -defparam \z80_|execute_|nextM~11 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_flags_xy_we~17 .lut_mask = 16'hBFFF; +defparam \z80_|execute_|ctl_flags_xy_we~17 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X40_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|nextM~8 ( +// Location: LCCOMB_X28_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~18 ( // Equation(s): -// \z80_|execute_|nextM~8_combout = (\z80_|alu_control_|flags_cond_true~q & (((\z80_|execute_|ixy_d~8_combout & !\z80_|execute_|ctl_flags_bus~5_combout )))) # (!\z80_|alu_control_|flags_cond_true~q & ((\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout -// ) # ((\z80_|execute_|ixy_d~8_combout & !\z80_|execute_|ctl_flags_bus~5_combout )))) +// \z80_|execute_|ctl_flags_xy_we~18_combout = ((\z80_|execute_|ctl_flags_xy_we~17_combout ) # ((!\z80_|execute_|ctl_flags_pf_we~4_combout ) # (!\z80_|execute_|ctl_pf_sel[0]~3_combout ))) # (!\z80_|execute_|ctl_flags_sz_we~7_combout ) - .dataa(\z80_|alu_control_|flags_cond_true~q ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), - .datac(\z80_|execute_|ixy_d~8_combout ), - .datad(\z80_|execute_|ctl_flags_bus~5_combout ), + .dataa(\z80_|execute_|ctl_flags_sz_we~7_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~17_combout ), + .datac(\z80_|execute_|ctl_pf_sel[0]~3_combout ), + .datad(\z80_|execute_|ctl_flags_pf_we~4_combout ), .cin(gnd), - .combout(\z80_|execute_|nextM~8_combout ), + .combout(\z80_|execute_|ctl_flags_xy_we~18_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|nextM~8 .lut_mask = 16'h44F4; -defparam \z80_|execute_|nextM~8 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_flags_xy_we~18 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_flags_xy_we~18 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|nextM~9 ( -// Equation(s): -// \z80_|execute_|nextM~9_combout = (\z80_|execute_|ctl_mWrite~2_combout & (\z80_|pla_decode_|Equal55~0_combout & ((\z80_|execute_|ctl_mRead~11_combout ) # (\z80_|execute_|ixy_d~6_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~2_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|execute_|ctl_mRead~11_combout ), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~9 .lut_mask = 16'h8880; -defparam \z80_|execute_|nextM~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|nextM~10 ( -// Equation(s): -// \z80_|execute_|nextM~10_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ) # ((\z80_|execute_|nextM~9_combout ) # ((\z80_|execute_|ctl_mRead~36_combout & \z80_|execute_|ixy_d~9_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .datab(\z80_|execute_|nextM~9_combout ), - .datac(\z80_|execute_|ctl_mRead~36_combout ), - .datad(\z80_|execute_|ixy_d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~10 .lut_mask = 16'hFEEE; -defparam \z80_|execute_|nextM~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|nextM~12 ( -// Equation(s): -// \z80_|execute_|nextM~12_combout = ((\z80_|execute_|nextM~8_combout ) # ((\z80_|execute_|nextM~10_combout ) # (\z80_|execute_|ctl_alu_op_low~32_combout ))) # (!\z80_|execute_|nextM~11_combout ) - - .dataa(\z80_|execute_|nextM~11_combout ), - .datab(\z80_|execute_|nextM~8_combout ), - .datac(\z80_|execute_|nextM~10_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~12 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|nextM~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N22 -cycloneive_lcell_comb \z80_|execute_|nextM~15 ( -// Equation(s): -// \z80_|execute_|nextM~15_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & ((\z80_|execute_|ctl_mRead~7_combout ) # (!\z80_|execute_|fMRead~10_combout )))) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|execute_|ctl_mRead~7_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|execute_|fMRead~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~15 .lut_mask = 16'h80A0; -defparam \z80_|execute_|nextM~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N8 -cycloneive_lcell_comb \z80_|execute_|nextM~6 ( -// Equation(s): -// \z80_|execute_|nextM~6_combout = (((\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal49~0_combout )) # (!\z80_|execute_|nextM~3_combout )) # (!\z80_|execute_|ixy_d~17_combout ) - - .dataa(\z80_|execute_|ixy_d~17_combout ), - .datab(\z80_|decode_state_|use_ixiy~combout ), - .datac(\z80_|execute_|nextM~3_combout ), - .datad(\z80_|pla_decode_|Equal49~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~6 .lut_mask = 16'hDF5F; -defparam \z80_|execute_|nextM~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N6 -cycloneive_lcell_comb \z80_|execute_|nextM~7 ( -// Equation(s): -// \z80_|execute_|nextM~7_combout = ((\z80_|execute_|nextM~6_combout & ((\z80_|execute_|ixy_d~8_combout ) # (\z80_|execute_|ctl_state_alu~4_combout )))) # (!\z80_|execute_|nextM~4_combout ) - - .dataa(\z80_|execute_|ixy_d~8_combout ), - .datab(\z80_|execute_|nextM~6_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|nextM~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~7 .lut_mask = 16'hC8FF; -defparam \z80_|execute_|nextM~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N6 -cycloneive_lcell_comb \z80_|execute_|nextM~13 ( -// Equation(s): -// \z80_|execute_|nextM~13_combout = (\z80_|execute_|nextM~12_combout ) # ((\z80_|execute_|nextM~15_combout ) # (\z80_|execute_|nextM~7_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|nextM~12_combout ), - .datac(\z80_|execute_|nextM~15_combout ), - .datad(\z80_|execute_|nextM~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~13 .lut_mask = 16'hFFFC; -defparam \z80_|execute_|nextM~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N12 -cycloneive_lcell_comb \z80_|execute_|setM1~39 ( -// Equation(s): -// \z80_|execute_|setM1~39_combout = (!\z80_|execute_|ctl_mWrite~5_combout & \z80_|execute_|setM1~38_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_mWrite~5_combout ), - .datad(\z80_|execute_|setM1~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~39 .lut_mask = 16'h0F00; -defparam \z80_|execute_|setM1~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N6 -cycloneive_lcell_comb \z80_|execute_|nextM~5 ( -// Equation(s): -// \z80_|execute_|nextM~5_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (((!\z80_|execute_|setM1~45_combout ) # (!\z80_|execute_|nextM~2_combout )) # (!\z80_|execute_|setM1~39_combout ))) - - .dataa(\z80_|execute_|setM1~39_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|nextM~2_combout ), - .datad(\z80_|execute_|setM1~45_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~5 .lut_mask = 16'h4CCC; -defparam \z80_|execute_|nextM~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|nextM~14 ( -// Equation(s): -// \z80_|execute_|nextM~14_combout = (\z80_|execute_|nextM~13_combout ) # (((\z80_|execute_|nextM~5_combout ) # (!\z80_|execute_|ctl_mRead~30_combout )) # (!\z80_|execute_|ctl_mWrite~13_combout )) - - .dataa(\z80_|execute_|nextM~13_combout ), - .datab(\z80_|execute_|ctl_mWrite~13_combout ), - .datac(\z80_|execute_|ctl_mRead~30_combout ), - .datad(\z80_|execute_|nextM~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~14 .lut_mask = 16'hFFBF; -defparam \z80_|execute_|nextM~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N14 -cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_15 ( -// Equation(s): -// \z80_|sequencer_|SYNTHESIZED_WIRE_15~combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|execute_|setM1~52_combout & !\z80_|execute_|nextM~14_combout )) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|execute_|setM1~52_combout ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_15 .lut_mask = 16'h00C0; -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y17_N15 -dffeas \z80_|sequencer_|DFFE_T4_ff ( +// Location: FF_X31_Y15_N21 +dffeas \z80_|alu_flags_|flags_xf ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ), + .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ), .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .ena(\z80_|execute_|ctl_flags_xy_we~18_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|sequencer_|DFFE_T4_ff~q ), + .q(\z80_|alu_flags_|flags_xf~q ), .prn(vcc)); // synopsys translate_off -defparam \z80_|sequencer_|DFFE_T4_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_T4_ff .power_up = "low"; +defparam \z80_|alu_flags_|flags_xf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|flags_xf .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y17_N18 -cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_16 ( +// Location: LCCOMB_X31_Y15_N30 +cycloneive_lcell_comb \z80_|alu_control_|db[3]~33 ( // Equation(s): -// \z80_|sequencer_|SYNTHESIZED_WIRE_16~combout = (\z80_|execute_|setM1~52_combout & (\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|execute_|nextM~14_combout )) - - .dataa(\z80_|execute_|setM1~52_combout ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_16 .lut_mask = 16'h00A0; -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y17_N19 -dffeas \z80_|sequencer_|DFFE_T5_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|DFFE_T5_ff~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_T5_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_T5_ff .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N26 -cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_17 ( -// Equation(s): -// \z80_|sequencer_|SYNTHESIZED_WIRE_17~combout = (\z80_|sequencer_|DFFE_T5_ff~q & (\z80_|execute_|setM1~52_combout & !\z80_|execute_|nextM~14_combout )) +// \z80_|alu_control_|db[3]~33_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & ((\z80_|alu_flags_|flags_xf~q ) # (!\z80_|execute_|ctl_flags_oe~2_combout ))) .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T5_ff~q ), - .datac(\z80_|execute_|setM1~52_combout ), - .datad(\z80_|execute_|nextM~14_combout ), + .datab(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .datac(\z80_|execute_|ctl_flags_oe~2_combout ), + .datad(\z80_|alu_flags_|flags_xf~q ), .cin(gnd), - .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_17~combout ), + .combout(\z80_|alu_control_|db[3]~33_combout ), .cout()); // synopsys translate_off -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_17 .lut_mask = 16'h00C0; -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_17 .sum_lutc_input = "datac"; +defparam \z80_|alu_control_|db[3]~33 .lut_mask = 16'hCC0C; +defparam \z80_|alu_control_|db[3]~33 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y17_N27 -dffeas \z80_|sequencer_|T6 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|SYNTHESIZED_WIRE_17~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|T6~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|T6 .is_wysiwyg = "true"; -defparam \z80_|sequencer_|T6 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|setM1~13 ( +// Location: LCCOMB_X31_Y14_N20 +cycloneive_lcell_comb \z80_|sw1_|db_down[3]~2 ( // Equation(s): -// \z80_|execute_|setM1~13_combout = (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|pla_decode_|Equal33~0_combout & ((!\z80_|pla_decode_|Equal32~0_combout ) # (!\z80_|pla_decode_|Equal21~2_combout )))) # (!\z80_|pla_decode_|Equal13~0_combout & -// (((!\z80_|pla_decode_|Equal32~0_combout )) # (!\z80_|pla_decode_|Equal21~2_combout ))) +// \z80_|sw1_|db_down[3]~2_combout = (\z80_|bus_control_|db[3]~21_combout ) # ((\z80_|execute_|ctl_sw_1d~6_combout & ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|execute_|ctl_66_oe~2_combout )))) - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|pla_decode_|Equal21~2_combout ), - .datac(\z80_|pla_decode_|Equal32~0_combout ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~13 .lut_mask = 16'h153F; -defparam \z80_|execute_|setM1~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal77~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal77~1_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal21~0_combout & (\z80_|pla_decode_|Equal77~0_combout & \z80_|pla_decode_|Equal33~0_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|pla_decode_|Equal21~0_combout ), - .datac(\z80_|pla_decode_|Equal77~0_combout ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal77~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal77~1 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal77~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|setM1~12 ( -// Equation(s): -// \z80_|execute_|setM1~12_combout = (!\z80_|pla_decode_|Equal77~1_combout & (!\z80_|execute_|ctl_alu_oe~3_combout & (!\z80_|pla_decode_|Equal1~6_combout & !\z80_|pla_decode_|Equal2~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal77~1_combout ), - .datab(\z80_|execute_|ctl_alu_oe~3_combout ), - .datac(\z80_|pla_decode_|Equal1~6_combout ), - .datad(\z80_|pla_decode_|Equal2~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~12 .lut_mask = 16'h0001; -defparam \z80_|execute_|setM1~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|setM1~14 ( -// Equation(s): -// \z80_|execute_|setM1~14_combout = (\z80_|execute_|setM1~13_combout & (\z80_|interrupts_|test1~2_combout & \z80_|execute_|setM1~12_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|setM1~13_combout ), - .datac(\z80_|interrupts_|test1~2_combout ), - .datad(\z80_|execute_|setM1~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~14 .lut_mask = 16'hC000; -defparam \z80_|execute_|setM1~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|setM1~41 ( -// Equation(s): -// \z80_|execute_|setM1~41_combout = (!\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_mWrite~4_combout & !\z80_|execute_|ctl_ir_we~10_combout )) - - .dataa(\z80_|execute_|ctl_ir_we~9_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|execute_|ctl_ir_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~41 .lut_mask = 16'h0005; -defparam \z80_|execute_|setM1~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|setM1~42 ( -// Equation(s): -// \z80_|execute_|setM1~42_combout = (!\z80_|pla_decode_|Equal38~2_combout & (!\z80_|pla_decode_|Equal37~0_combout & (!\z80_|pla_decode_|Equal47~0_combout & \z80_|sequencer_|DFFE_T4_ff~q ))) - - .dataa(\z80_|pla_decode_|Equal38~2_combout ), - .datab(\z80_|pla_decode_|Equal37~0_combout ), - .datac(\z80_|pla_decode_|Equal47~0_combout ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~42 .lut_mask = 16'h0100; -defparam \z80_|execute_|setM1~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|setM1~43 ( -// Equation(s): -// \z80_|execute_|setM1~43_combout = (!\z80_|pla_decode_|Equal21~1_combout & (\z80_|execute_|setM1~41_combout & (!\z80_|pla_decode_|Equal48~0_combout & \z80_|execute_|setM1~42_combout ))) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|execute_|setM1~41_combout ), - .datac(\z80_|pla_decode_|Equal48~0_combout ), - .datad(\z80_|execute_|setM1~42_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~43 .lut_mask = 16'h0400; -defparam \z80_|execute_|setM1~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N26 -cycloneive_lcell_comb \z80_|execute_|setM1~44 ( -// Equation(s): -// \z80_|execute_|setM1~44_combout = (\z80_|execute_|setM1~43_combout & (\z80_|execute_|setM1~40_combout & ((!\z80_|pla_decode_|Equal2~1_combout ) # (!\z80_|pla_decode_|Equal1~4_combout )))) - - .dataa(\z80_|execute_|setM1~43_combout ), - .datab(\z80_|pla_decode_|Equal1~4_combout ), - .datac(\z80_|execute_|setM1~40_combout ), - .datad(\z80_|pla_decode_|Equal2~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~44 .lut_mask = 16'h20A0; -defparam \z80_|execute_|setM1~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N20 -cycloneive_lcell_comb \z80_|execute_|setM1~50 ( -// Equation(s): -// \z80_|execute_|setM1~50_combout = (\z80_|execute_|setM1~46_combout & (\z80_|execute_|setM1~14_combout & (\z80_|execute_|setM1~44_combout & \z80_|execute_|setM1~49_combout ))) - - .dataa(\z80_|execute_|setM1~46_combout ), - .datab(\z80_|execute_|setM1~14_combout ), - .datac(\z80_|execute_|setM1~44_combout ), - .datad(\z80_|execute_|setM1~49_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~50 .lut_mask = 16'h8000; -defparam \z80_|execute_|setM1~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|setM1~51 ( -// Equation(s): -// \z80_|execute_|setM1~51_combout = (\z80_|sequencer_|T6~q & (((\z80_|execute_|setM1~50_combout & \z80_|execute_|setM1~39_combout )) # (!\z80_|execute_|setM1~40_combout ))) # (!\z80_|sequencer_|T6~q & (\z80_|execute_|setM1~50_combout & -// ((\z80_|execute_|setM1~39_combout )))) - - .dataa(\z80_|sequencer_|T6~q ), - .datab(\z80_|execute_|setM1~50_combout ), - .datac(\z80_|execute_|setM1~40_combout ), - .datad(\z80_|execute_|setM1~39_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~51_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~51 .lut_mask = 16'hCE0A; -defparam \z80_|execute_|setM1~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N2 -cycloneive_lcell_comb \z80_|execute_|setM1~6 ( -// Equation(s): -// \z80_|execute_|setM1~6_combout = (\z80_|execute_|ctl_al_we~13_combout & (\z80_|sequencer_|M5~q & (\z80_|pla_decode_|Equal9~1_combout ))) # (!\z80_|execute_|ctl_al_we~13_combout & ((\z80_|sequencer_|DFFE_M4_ff~q ) # ((\z80_|sequencer_|M5~q & -// \z80_|pla_decode_|Equal9~1_combout )))) - - .dataa(\z80_|execute_|ctl_al_we~13_combout ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|sequencer_|DFFE_M4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~6 .lut_mask = 16'hD5C0; -defparam \z80_|execute_|setM1~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N12 -cycloneive_lcell_comb \z80_|execute_|setM1~7 ( -// Equation(s): -// \z80_|execute_|setM1~7_combout = ((\z80_|sequencer_|DFFE_T5_ff~q & \z80_|execute_|setM1~6_combout )) # (!\z80_|execute_|ctl_flags_xy_we~16_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_flags_xy_we~16_combout ), - .datac(\z80_|sequencer_|DFFE_T5_ff~q ), - .datad(\z80_|execute_|setM1~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~7 .lut_mask = 16'hF333; -defparam \z80_|execute_|setM1~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N0 -cycloneive_lcell_comb \z80_|execute_|setM1~8 ( -// Equation(s): -// \z80_|execute_|setM1~8_combout = (\z80_|execute_|ctl_mWrite~4_combout ) # ((\z80_|execute_|ctl_mRead~7_combout ) # ((\z80_|pla_decode_|Equal6~1_combout ) # (!\z80_|execute_|fMWrite~3_combout ))) - - .dataa(\z80_|execute_|ctl_mWrite~4_combout ), - .datab(\z80_|execute_|ctl_mRead~7_combout ), - .datac(\z80_|pla_decode_|Equal6~1_combout ), - .datad(\z80_|execute_|fMWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~8 .lut_mask = 16'hFEFF; -defparam \z80_|execute_|setM1~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N10 -cycloneive_lcell_comb \z80_|execute_|setM1~9 ( -// Equation(s): -// \z80_|execute_|setM1~9_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ) # ((!\z80_|ir_|opcode [4] & (!\z80_|ir_|opcode [2] & \z80_|execute_|ctl_mWrite~2_combout ))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [2]), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .datad(\z80_|execute_|ctl_mWrite~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~9 .lut_mask = 16'hF1F0; -defparam \z80_|execute_|setM1~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N10 -cycloneive_lcell_comb \z80_|execute_|setM1~10 ( -// Equation(s): -// \z80_|execute_|setM1~10_combout = ((\z80_|execute_|setM1~8_combout ) # ((\z80_|execute_|ctl_mWrite~16_combout & \z80_|execute_|setM1~9_combout ))) # (!\z80_|execute_|nextM~2_combout ) - - .dataa(\z80_|execute_|ctl_mWrite~16_combout ), - .datab(\z80_|execute_|nextM~2_combout ), - .datac(\z80_|execute_|setM1~8_combout ), - .datad(\z80_|execute_|setM1~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~10 .lut_mask = 16'hFBF3; -defparam \z80_|execute_|setM1~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N26 -cycloneive_lcell_comb \z80_|execute_|setM1~11 ( -// Equation(s): -// \z80_|execute_|setM1~11_combout = (\z80_|execute_|setM1~7_combout ) # (((\z80_|execute_|ixy_d~6_combout & \z80_|execute_|setM1~10_combout )) # (!\z80_|reg_control_|reg_sel_pc~3_combout )) - - .dataa(\z80_|execute_|setM1~7_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|execute_|setM1~10_combout ), - .datad(\z80_|reg_control_|reg_sel_pc~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~11 .lut_mask = 16'hEAFF; -defparam \z80_|execute_|setM1~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|setM1~17 ( -// Equation(s): -// \z80_|execute_|setM1~17_combout = ((\z80_|execute_|setM1~11_combout ) # ((!\z80_|execute_|setM1~14_combout & \z80_|execute_|ctl_eval_cond~0_combout ))) # (!\z80_|execute_|setM1~16_combout ) - - .dataa(\z80_|execute_|setM1~16_combout ), - .datab(\z80_|execute_|setM1~14_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|setM1~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~17 .lut_mask = 16'hFF75; -defparam \z80_|execute_|setM1~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N16 -cycloneive_lcell_comb \z80_|execute_|setM1~31 ( -// Equation(s): -// \z80_|execute_|setM1~31_combout = (\z80_|pla_decode_|Equal35~0_combout & ((\z80_|execute_|ixy_d~6_combout ) # ((\z80_|execute_|ctl_reg_in_hi~2_combout & \z80_|execute_|ctl_mRead~18_combout )))) # (!\z80_|pla_decode_|Equal35~0_combout & -// (\z80_|execute_|ctl_reg_in_hi~2_combout & ((\z80_|execute_|ctl_mRead~18_combout )))) - - .dataa(\z80_|pla_decode_|Equal35~0_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|execute_|ctl_mRead~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~31 .lut_mask = 16'hECA0; -defparam \z80_|execute_|setM1~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N2 -cycloneive_lcell_comb \z80_|execute_|setM1~28 ( -// Equation(s): -// \z80_|execute_|setM1~28_combout = ((\z80_|execute_|ctl_mRead~9_combout ) # ((\z80_|execute_|ctl_mRead~15_combout ) # (\z80_|execute_|ctl_mRead~7_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), - .datab(\z80_|execute_|ctl_mRead~9_combout ), - .datac(\z80_|execute_|ctl_mRead~15_combout ), - .datad(\z80_|execute_|ctl_mRead~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~28 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|setM1~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|setM1~30 ( -// Equation(s): -// \z80_|execute_|setM1~30_combout = (((\z80_|execute_|ctl_state_alu~6_combout & \z80_|execute_|setM1~28_combout )) # (!\z80_|execute_|setM1~29_combout )) # (!\z80_|execute_|setM1~54_combout ) - - .dataa(\z80_|execute_|setM1~54_combout ), - .datab(\z80_|execute_|setM1~29_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|setM1~28_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~30 .lut_mask = 16'hF777; -defparam \z80_|execute_|setM1~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N10 -cycloneive_lcell_comb \z80_|execute_|setM1~32 ( -// Equation(s): -// \z80_|execute_|setM1~32_combout = (\z80_|execute_|ctl_mRead~5_combout ) # ((\z80_|execute_|ctl_mRead~4_combout ) # ((\z80_|execute_|setM1~9_combout & \z80_|execute_|ctl_mRead~36_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~5_combout ), - .datab(\z80_|execute_|setM1~9_combout ), - .datac(\z80_|execute_|ctl_mRead~36_combout ), - .datad(\z80_|execute_|ctl_mRead~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~32 .lut_mask = 16'hFFEA; -defparam \z80_|execute_|setM1~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N8 -cycloneive_lcell_comb \z80_|execute_|setM1~33 ( -// Equation(s): -// \z80_|execute_|setM1~33_combout = (\z80_|execute_|setM1~31_combout ) # ((\z80_|execute_|setM1~30_combout ) # ((\z80_|execute_|ixy_d~9_combout & \z80_|execute_|setM1~32_combout ))) - - .dataa(\z80_|execute_|setM1~31_combout ), - .datab(\z80_|execute_|setM1~30_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|execute_|setM1~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~33 .lut_mask = 16'hFEEE; -defparam \z80_|execute_|setM1~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|setM1~25 ( -// Equation(s): -// \z80_|execute_|setM1~25_combout = ((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & \z80_|pla_decode_|Equal21~1_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), - .datad(\z80_|pla_decode_|Equal21~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~25 .lut_mask = 16'hAF0F; -defparam \z80_|execute_|setM1~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|setM1~26 ( -// Equation(s): -// \z80_|execute_|setM1~26_combout = ((\z80_|execute_|ctl_mRead~13_combout ) # ((!\z80_|alu_control_|flags_cond_true~q & \z80_|pla_decode_|Equal40~1_combout ))) # (!\z80_|execute_|ctl_bus_inc_oe~29_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~29_combout ), - .datab(\z80_|alu_control_|flags_cond_true~q ), - .datac(\z80_|execute_|ctl_mRead~13_combout ), - .datad(\z80_|pla_decode_|Equal40~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~26 .lut_mask = 16'hF7F5; -defparam \z80_|execute_|setM1~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|setM1~24 ( -// Equation(s): -// \z80_|execute_|setM1~24_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & (((\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & !\z80_|alu_control_|flags_cond_true~q )) # (!\z80_|execute_|ctl_mRead~12_combout ))) # -// (!\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & (\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & ((!\z80_|alu_control_|flags_cond_true~q )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), - .datac(\z80_|execute_|ctl_mRead~12_combout ), - .datad(\z80_|alu_control_|flags_cond_true~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~24 .lut_mask = 16'h0ACE; -defparam \z80_|execute_|setM1~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N18 -cycloneive_lcell_comb \z80_|execute_|setM1~27 ( -// Equation(s): -// \z80_|execute_|setM1~27_combout = (\z80_|execute_|setM1~24_combout ) # ((\z80_|execute_|ctl_state_alu~4_combout & ((\z80_|execute_|setM1~25_combout ) # (\z80_|execute_|setM1~26_combout )))) - - .dataa(\z80_|execute_|setM1~25_combout ), - .datab(\z80_|execute_|setM1~26_combout ), - .datac(\z80_|execute_|setM1~24_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~27 .lut_mask = 16'hFEF0; -defparam \z80_|execute_|setM1~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N6 -cycloneive_lcell_comb \z80_|execute_|setM1~22 ( -// Equation(s): -// \z80_|execute_|setM1~22_combout = (!\z80_|execute_|ctl_mRead~10_combout & (\z80_|execute_|fMWrite~9_combout & (!\z80_|execute_|ctl_mRead~8_combout & \z80_|execute_|fMWrite~3_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|execute_|fMWrite~9_combout ), - .datac(\z80_|execute_|ctl_mRead~8_combout ), - .datad(\z80_|execute_|fMWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~22 .lut_mask = 16'h0400; -defparam \z80_|execute_|setM1~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N26 -cycloneive_lcell_comb \z80_|execute_|setM1~21 ( -// Equation(s): -// \z80_|execute_|setM1~21_combout = (\z80_|decode_state_|DFFE_instNonRep~q ) # ((!\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [4] & \z80_|execute_|ctl_mWrite~2_combout ))) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|decode_state_|DFFE_instNonRep~q ), - .datad(\z80_|execute_|ctl_mWrite~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~21 .lut_mask = 16'hF1F0; -defparam \z80_|execute_|setM1~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N2 -cycloneive_lcell_comb \z80_|execute_|setM1~53 ( -// Equation(s): -// \z80_|execute_|setM1~53_combout = (\z80_|sequencer_|DFFE_T5_ff~q & ((\z80_|sequencer_|DFFE_M4_ff~q ) # ((\z80_|execute_|setM1~21_combout & \z80_|sequencer_|DFFE_M3_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|sequencer_|DFFE_T5_ff~q ), - .datac(\z80_|execute_|setM1~21_combout ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~53_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~53 .lut_mask = 16'hC888; -defparam \z80_|execute_|setM1~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N4 -cycloneive_lcell_comb \z80_|execute_|setM1~23 ( -// Equation(s): -// \z80_|execute_|setM1~23_combout = (\z80_|execute_|setM1~22_combout & (((!\z80_|execute_|ctl_flags_bus~5_combout & \z80_|execute_|setM1~53_combout )))) # (!\z80_|execute_|setM1~22_combout & ((\z80_|execute_|ctl_reg_in_hi~2_combout ) # -// ((!\z80_|execute_|ctl_flags_bus~5_combout & \z80_|execute_|setM1~53_combout )))) - - .dataa(\z80_|execute_|setM1~22_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datac(\z80_|execute_|ctl_flags_bus~5_combout ), - .datad(\z80_|execute_|setM1~53_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~23 .lut_mask = 16'h4F44; -defparam \z80_|execute_|setM1~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N6 -cycloneive_lcell_comb \z80_|execute_|setM1~18 ( -// Equation(s): -// \z80_|execute_|setM1~18_combout = (\z80_|execute_|ctl_mRead~11_combout & (((\z80_|pla_decode_|Equal37~0_combout & !\z80_|alu_control_|flags_cond_true~q )) # (!\z80_|execute_|ctl_flags_bus~4_combout ))) - - .dataa(\z80_|pla_decode_|Equal37~0_combout ), - .datab(\z80_|execute_|ctl_mRead~11_combout ), - .datac(\z80_|alu_control_|flags_cond_true~q ), - .datad(\z80_|execute_|ctl_flags_bus~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~18 .lut_mask = 16'h08CC; -defparam \z80_|execute_|setM1~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|setM1~19 ( -// Equation(s): -// \z80_|execute_|setM1~19_combout = (\z80_|execute_|setM1~18_combout ) # ((\z80_|execute_|ixy_d~8_combout & (\z80_|pla_decode_|Equal10~0_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ))) - - .dataa(\z80_|execute_|setM1~18_combout ), - .datab(\z80_|execute_|ixy_d~8_combout ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~19 .lut_mask = 16'hEAAA; -defparam \z80_|execute_|setM1~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|setM1~20 ( -// Equation(s): -// \z80_|execute_|setM1~20_combout = ((\z80_|execute_|setM1~19_combout ) # ((\z80_|execute_|ctl_iorw~11_combout & \z80_|execute_|ctl_mWrite~3_combout ))) # (!\z80_|execute_|ctl_flags_sz_we~0_combout ) - - .dataa(\z80_|execute_|ctl_iorw~11_combout ), - .datab(\z80_|execute_|ctl_mWrite~3_combout ), - .datac(\z80_|execute_|ctl_flags_sz_we~0_combout ), - .datad(\z80_|execute_|setM1~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~20 .lut_mask = 16'hFF8F; -defparam \z80_|execute_|setM1~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N16 -cycloneive_lcell_comb \z80_|execute_|setM1~34 ( -// Equation(s): -// \z80_|execute_|setM1~34_combout = (\z80_|execute_|setM1~33_combout ) # ((\z80_|execute_|setM1~27_combout ) # ((\z80_|execute_|setM1~23_combout ) # (\z80_|execute_|setM1~20_combout ))) - - .dataa(\z80_|execute_|setM1~33_combout ), - .datab(\z80_|execute_|setM1~27_combout ), - .datac(\z80_|execute_|setM1~23_combout ), - .datad(\z80_|execute_|setM1~20_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~34 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|setM1~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|setM1~52 ( -// Equation(s): -// \z80_|execute_|setM1~52_combout = (!\z80_|execute_|setM1~17_combout & (!\z80_|execute_|setM1~34_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|execute_|setM1~51_combout )))) - - .dataa(\z80_|execute_|setM1~51_combout ), - .datab(\z80_|execute_|setM1~17_combout ), - .datac(\z80_|execute_|setM1~34_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~52_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~52 .lut_mask = 16'h0301; -defparam \z80_|execute_|setM1~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N24 -cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_14 ( -// Equation(s): -// \z80_|sequencer_|SYNTHESIZED_WIRE_14~combout = (\z80_|execute_|setM1~52_combout & (\z80_|sequencer_|DFFE_T2_ff~q & !\z80_|execute_|nextM~14_combout )) - - .dataa(\z80_|execute_|setM1~52_combout ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_14 .lut_mask = 16'h00A0; -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y17_N25 -dffeas \z80_|sequencer_|DFFE_T3_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|DFFE_T3_ff~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_T3_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_T3_ff .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout = (\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 .lut_mask = 16'h00F0; -defparam \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N24 -cycloneive_lcell_comb \z80_|decode_state_|in_halt~0 ( -// Equation(s): -// \z80_|decode_state_|in_halt~0_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|decode_state_|in_halt~q & !\z80_|interrupts_|DFFE_inst44~q )) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(gnd), - .datac(\z80_|decode_state_|in_halt~q ), - .datad(\z80_|interrupts_|DFFE_inst44~q ), - .cin(gnd), - .combout(\z80_|decode_state_|in_halt~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|in_halt~0 .lut_mask = 16'h0050; -defparam \z80_|decode_state_|in_halt~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N24 -cycloneive_lcell_comb \z80_|decode_state_|in_halt~1 ( -// Equation(s): -// \z80_|decode_state_|in_halt~1_combout = (\z80_|decode_state_|in_halt~0_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (!\z80_|decode_state_|in_halt~q & \z80_|pla_decode_|Equal77~1_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|decode_state_|in_halt~0_combout ), - .datac(\z80_|decode_state_|in_halt~q ), - .datad(\z80_|pla_decode_|Equal77~1_combout ), - .cin(gnd), - .combout(\z80_|decode_state_|in_halt~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|in_halt~1 .lut_mask = 16'hCECC; -defparam \z80_|decode_state_|in_halt~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y13_N25 -dffeas \z80_|decode_state_|in_halt ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|decode_state_|in_halt~1_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|decode_state_|in_halt~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|decode_state_|in_halt .is_wysiwyg = "true"; -defparam \z80_|decode_state_|in_halt .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~2 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~2_combout = (!\z80_|execute_|ctl_bus_zero_oe~0_combout & (!\z80_|execute_|ctl_bus_ff_oe~1_combout & ((\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) # (!\z80_|decode_state_|in_halt~q )))) - - .dataa(\z80_|decode_state_|in_halt~q ), - .datab(\z80_|execute_|ctl_bus_zero_oe~0_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|execute_|ctl_bus_ff_oe~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~2 .lut_mask = 16'h0031; -defparam \z80_|execute_|ctl_bus_db_oe~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~5 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~5_combout = (\z80_|execute_|ctl_ir_we~8_combout ) # ((\z80_|execute_|ctl_ir_we~14_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout ) # (\z80_|pla_decode_|Equal41~2_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(\z80_|execute_|ctl_ir_we~14_combout ), - .datac(\z80_|execute_|ctl_ir_we~11_combout ), - .datad(\z80_|pla_decode_|Equal41~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~5 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_bus_db_oe~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~6 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~6_combout = ((\z80_|execute_|ctl_66_oe~2_combout ) # ((\z80_|execute_|ctl_ir_we~4_combout & \z80_|execute_|ctl_bus_db_oe~5_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_66_oe~2_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~6 .lut_mask = 16'hFDF5; -defparam \z80_|execute_|ctl_bus_db_oe~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~4 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~4_combout = (!\z80_|execute_|ctl_bus_db_oe~3_combout ) # (!\z80_|execute_|ctl_bus_db_oe~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_bus_db_oe~0_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~4 .lut_mask = 16'h0FFF; -defparam \z80_|execute_|ctl_bus_db_oe~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~combout = (\z80_|execute_|ctl_bus_db_oe~2_combout & (((\z80_|execute_|ctl_bus_db_oe~6_combout ) # (\z80_|execute_|ctl_bus_db_oe~4_combout )) # (!\z80_|execute_|ctl_sw_1d~6_combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_oe~2_combout ), + .dataa(\z80_|execute_|ctl_66_oe~2_combout ), .datab(\z80_|execute_|ctl_sw_1d~6_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~6_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~4_combout ), + .datac(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datad(\z80_|bus_control_|db[3]~21_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~combout ), + .combout(\z80_|sw1_|db_down[3]~2_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe .lut_mask = 16'hAAA2; -defparam \z80_|execute_|ctl_bus_db_oe .sum_lutc_input = "datac"; +defparam \z80_|sw1_|db_down[3]~2 .lut_mask = 16'hFFC4; +defparam \z80_|sw1_|db_down[3]~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N28 -cycloneive_lcell_comb \z80_|bus_control_|db[0]~6 ( +// Location: LCCOMB_X31_Y14_N6 +cycloneive_lcell_comb \z80_|alu_control_|db[3]~34 ( // Equation(s): -// \z80_|bus_control_|db[0]~6_combout = (\z80_|execute_|ctl_bus_db_oe~combout ) # ((\z80_|execute_|ctl_bus_db_we~7_combout ) # (!\z80_|execute_|ctl_bus_db_oe~2_combout )) +// \z80_|alu_control_|db[3]~34_combout = (\z80_|alu_control_|db[3]~33_combout & (\z80_|sw1_|db_down[3]~2_combout & ((\z80_|reg_file_|gdfx_temp0[3]~52_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) - .dataa(\z80_|execute_|ctl_bus_db_oe~combout ), + .dataa(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .datac(\z80_|alu_control_|db[3]~33_combout ), + .datad(\z80_|sw1_|db_down[3]~2_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[3]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[3]~34 .lut_mask = 16'hB000; +defparam \z80_|alu_control_|db[3]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N0 +cycloneive_lcell_comb \z80_|alu_control_|db[3]~35 ( +// Equation(s): +// \z80_|alu_control_|db[3]~35_combout = ((\z80_|alu_control_|db[3]~34_combout & ((\z80_|alu_|db[3]~20_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) + + .dataa(\z80_|alu_control_|db[3]~34_combout ), + .datab(\z80_|execute_|ctl_sw_2u~7_combout ), + .datac(\z80_|alu_|db[3]~20_combout ), + .datad(\z80_|alu_control_|db[6]~11_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[3]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[3]~35 .lut_mask = 16'hA2FF; +defparam \z80_|alu_control_|db[3]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][0]~75 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][0]~75_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [1])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), .datab(gnd), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~2_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[0]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[0]~6 .lut_mask = 16'hFAFF; -defparam \z80_|bus_control_|db[0]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][3]~93 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][3]~93_combout = (\ula_|zx_keyboard_|keys[7][4]~19_combout & (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[6][4]~47_combout ))) - - .dataa(\ula_|zx_keyboard_|keys[7][4]~19_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|keys[6][4]~47_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][3]~93_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][3]~93 .lut_mask = 16'h0800; -defparam \ula_|zx_keyboard_|keys[1][3]~93 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][3]~94 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][3]~94_combout = (\ula_|zx_keyboard_|keys[1][3]~93_combout & ((\ula_|ps2_keyboard_|shiftreg [3] & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[1][3]~q )))) # -// (!\ula_|zx_keyboard_|keys[1][3]~93_combout & (((\ula_|zx_keyboard_|keys[1][3]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[1][3]~93_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|zx_keyboard_|keys[1][3]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][3]~94_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][3]~94 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[1][3]~94 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y19_N31 -dffeas \ula_|zx_keyboard_|keys[1][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[1][3]~94_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[1][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[1][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][3]~96 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][3]~96_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [1]))) # (!\ula_|ps2_keyboard_|shiftreg [3] & -// (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), .datad(\ula_|ps2_keyboard_|shiftreg [1]), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][3]~96_combout ), + .combout(\ula_|zx_keyboard_|keys[3][0]~75_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][3]~96 .lut_mask = 16'h0810; -defparam \ula_|zx_keyboard_|keys[0][3]~96 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[3][0]~75 .lut_mask = 16'h0500; +defparam \ula_|zx_keyboard_|keys[3][0]~75 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y18_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][3]~98 ( +// Location: LCCOMB_X27_Y8_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|Selector5~0 ( // Equation(s): -// \ula_|zx_keyboard_|keys[0][3]~98_combout = (\ula_|zx_keyboard_|keys[0][3]~96_combout & ((\ula_|zx_keyboard_|keys[0][4]~97_combout & ((!\ula_|zx_keyboard_|keys[2][4]~95_combout ))) # (!\ula_|zx_keyboard_|keys[0][4]~97_combout & -// (\ula_|zx_keyboard_|keys[0][3]~q )))) # (!\ula_|zx_keyboard_|keys[0][3]~96_combout & (((\ula_|zx_keyboard_|keys[0][3]~q )))) +// \ula_|zx_keyboard_|Selector5~0_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|keys[3][0]~75_combout & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [6]))) - .dataa(\ula_|zx_keyboard_|keys[0][3]~96_combout ), - .datab(\ula_|zx_keyboard_|keys[0][4]~97_combout ), - .datac(\ula_|zx_keyboard_|keys[0][3]~q ), - .datad(\ula_|zx_keyboard_|keys[2][4]~95_combout ), + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|zx_keyboard_|keys[3][0]~75_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][3]~98_combout ), + .combout(\ula_|zx_keyboard_|Selector5~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][3]~98 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[0][3]~98 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|Selector5~0 .lut_mask = 16'h0400; +defparam \ula_|zx_keyboard_|Selector5~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X29_Y18_N1 -dffeas \ula_|zx_keyboard_|keys[0][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[0][3]~98_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[0][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[0][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N4 -cycloneive_lcell_comb \D[3]~65 ( +// Location: LCCOMB_X26_Y10_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|Selector5~1 ( // Equation(s): -// \D[3]~65_combout = (\z80_|address_pins_|abus[9]~17_combout & ((\z80_|address_pins_|abus[8]~18_combout ) # ((!\ula_|zx_keyboard_|keys[0][3]~q )))) # (!\z80_|address_pins_|abus[9]~17_combout & (!\ula_|zx_keyboard_|keys[1][3]~q & -// ((\z80_|address_pins_|abus[8]~18_combout ) # (!\ula_|zx_keyboard_|keys[0][3]~q )))) - - .dataa(\z80_|address_pins_|abus[9]~17_combout ), - .datab(\z80_|address_pins_|abus[8]~18_combout ), - .datac(\ula_|zx_keyboard_|keys[1][3]~q ), - .datad(\ula_|zx_keyboard_|keys[0][3]~q ), - .cin(gnd), - .combout(\D[3]~65_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~65 .lut_mask = 16'h8CAF; -defparam \D[3]~65 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][3]~99 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][3]~99_combout = (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [2])) +// \ula_|zx_keyboard_|Selector5~1_combout = (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [2]))) .dataa(\ula_|ps2_keyboard_|shiftreg [1]), .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][3]~99_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][3]~99 .lut_mask = 16'h4040; -defparam \ula_|zx_keyboard_|keys[3][3]~99 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][3]~100 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][3]~100_combout = (\ula_|zx_keyboard_|keys[3][3]~48_combout & ((\ula_|zx_keyboard_|keys[3][3]~99_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[3][3]~99_combout & (\ula_|zx_keyboard_|keys[3][3]~q -// )))) # (!\ula_|zx_keyboard_|keys[3][3]~48_combout & (((\ula_|zx_keyboard_|keys[3][3]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[3][3]~48_combout ), - .datab(\ula_|zx_keyboard_|keys[3][3]~99_combout ), - .datac(\ula_|zx_keyboard_|keys[3][3]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][3]~100_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][3]~100 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[3][3]~100 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y20_N9 -dffeas \ula_|zx_keyboard_|keys[3][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[3][3]~100_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[3][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[3][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~101 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][3]~101_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & !\ula_|ps2_keyboard_|shiftreg [2])) - - .dataa(\ula_|zx_keyboard_|shifted~q ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), .datad(\ula_|ps2_keyboard_|shiftreg [2]), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][3]~101_combout ), + .combout(\ula_|zx_keyboard_|Selector5~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][3]~101 .lut_mask = 16'hCCDD; -defparam \ula_|zx_keyboard_|keys[2][3]~101 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|Selector5~1 .lut_mask = 16'h4000; +defparam \ula_|zx_keyboard_|Selector5~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y18_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~102 ( +// Location: LCCOMB_X27_Y8_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~132 ( // Equation(s): -// \ula_|zx_keyboard_|keys[2][3]~102_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [2]))) # (!\ula_|ps2_keyboard_|shiftreg [3] & -// (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [2]))) +// \ula_|zx_keyboard_|keys[4][3]~132_combout = (\ula_|zx_keyboard_|Selector5~0_combout ) # ((\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|zx_keyboard_|Selector5~1_combout ))) - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .dataa(\ula_|zx_keyboard_|Selector5~0_combout ), .datab(\ula_|ps2_keyboard_|shiftreg [5]), .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|zx_keyboard_|Selector5~1_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][3]~102_combout ), + .combout(\ula_|zx_keyboard_|keys[4][3]~132_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][3]~102 .lut_mask = 16'h0810; -defparam \ula_|zx_keyboard_|keys[2][3]~102 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[4][3]~132 .lut_mask = 16'hAEAA; +defparam \ula_|zx_keyboard_|keys[4][3]~132 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y18_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~133 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][3]~133_combout = (\ula_|zx_keyboard_|keys[5][1]~36_combout & (\ula_|zx_keyboard_|keys[2][3]~102_combout & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1]))) - - .dataa(\ula_|zx_keyboard_|keys[5][1]~36_combout ), - .datab(\ula_|zx_keyboard_|keys[2][3]~102_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][3]~133_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][3]~133 .lut_mask = 16'h0080; -defparam \ula_|zx_keyboard_|keys[2][3]~133 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~103 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][3]~103_combout = (\ula_|zx_keyboard_|keys[2][3]~133_combout & (!\ula_|zx_keyboard_|keys[2][3]~101_combout )) # (!\ula_|zx_keyboard_|keys[2][3]~133_combout & ((\ula_|zx_keyboard_|keys[2][3]~q ))) - - .dataa(\ula_|zx_keyboard_|keys[2][3]~101_combout ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[2][3]~q ), - .datad(\ula_|zx_keyboard_|keys[2][3]~133_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][3]~103_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][3]~103 .lut_mask = 16'h55F0; -defparam \ula_|zx_keyboard_|keys[2][3]~103 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y18_N3 -dffeas \ula_|zx_keyboard_|keys[2][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[2][3]~103_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[2][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[2][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N28 -cycloneive_lcell_comb \D[3]~66 ( -// Equation(s): -// \D[3]~66_combout = (\z80_|address_pins_|abus[11]~19_combout & (((\z80_|address_pins_|abus[10]~24_combout ) # (!\ula_|zx_keyboard_|keys[2][3]~q )))) # (!\z80_|address_pins_|abus[11]~19_combout & (!\ula_|zx_keyboard_|keys[3][3]~q & -// ((\z80_|address_pins_|abus[10]~24_combout ) # (!\ula_|zx_keyboard_|keys[2][3]~q )))) - - .dataa(\z80_|address_pins_|abus[11]~19_combout ), - .datab(\ula_|zx_keyboard_|keys[3][3]~q ), - .datac(\z80_|address_pins_|abus[10]~24_combout ), - .datad(\ula_|zx_keyboard_|keys[2][3]~q ), - .cin(gnd), - .combout(\D[3]~66_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~66 .lut_mask = 16'hB0BB; -defparam \D[3]~66 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][3]~104 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][3]~104_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [0])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [5]), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][3]~104_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][3]~104 .lut_mask = 16'h0808; -defparam \ula_|zx_keyboard_|keys[5][3]~104 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][3]~105 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][3]~105_combout = (\ula_|zx_keyboard_|keys[5][3]~104_combout & ((\ula_|zx_keyboard_|keys[1][4]~25_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[1][4]~25_combout & (\ula_|zx_keyboard_|keys[5][3]~q -// )))) # (!\ula_|zx_keyboard_|keys[5][3]~104_combout & (((\ula_|zx_keyboard_|keys[5][3]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[5][3]~104_combout ), - .datab(\ula_|zx_keyboard_|keys[1][4]~25_combout ), - .datac(\ula_|zx_keyboard_|keys[5][3]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][3]~105_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][3]~105 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[5][3]~105 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y19_N23 -dffeas \ula_|zx_keyboard_|keys[5][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[5][3]~105_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[5][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[5][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N16 +// Location: LCCOMB_X27_Y8_N10 cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~106 ( // Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~106_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[5][4]~24_combout & (\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|WideOr16~2_combout ))) +// \ula_|zx_keyboard_|keys[4][3]~106_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|WideOr16~2_combout & (\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[5][4]~22_combout ))) .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|zx_keyboard_|keys[5][4]~24_combout ), + .datab(\ula_|zx_keyboard_|WideOr16~2_combout ), .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|zx_keyboard_|WideOr16~2_combout ), + .datad(\ula_|zx_keyboard_|keys[5][4]~22_combout ), .cin(gnd), .combout(\ula_|zx_keyboard_|keys[4][3]~106_combout ), .cout()); @@ -52111,110 +41584,59 @@ defparam \ula_|zx_keyboard_|keys[4][3]~106 .lut_mask = 16'h8000; defparam \ula_|zx_keyboard_|keys[4][3]~106 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X27_Y21_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|Selector5~1 ( -// Equation(s): -// \ula_|zx_keyboard_|Selector5~1_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|Selector5~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|Selector5~1 .lut_mask = 16'h0800; -defparam \ula_|zx_keyboard_|Selector5~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|Selector5~0 ( -// Equation(s): -// \ula_|zx_keyboard_|Selector5~0_combout = (\ula_|zx_keyboard_|keys[3][0]~78_combout & (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [5]))) - - .dataa(\ula_|zx_keyboard_|keys[3][0]~78_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|Selector5~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|Selector5~0 .lut_mask = 16'h0020; -defparam \ula_|zx_keyboard_|Selector5~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y21_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~134 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~134_combout = (\ula_|zx_keyboard_|Selector5~0_combout ) # ((\ula_|zx_keyboard_|Selector5~1_combout & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [5]))) - - .dataa(\ula_|zx_keyboard_|Selector5~1_combout ), - .datab(\ula_|zx_keyboard_|Selector5~0_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][3]~134_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~134 .lut_mask = 16'hCECC; -defparam \ula_|zx_keyboard_|keys[4][3]~134 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y21_N6 +// Location: LCCOMB_X27_Y8_N26 cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~107 ( // Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~107_combout = (\ula_|zx_keyboard_|extended~q & (\ula_|zx_keyboard_|keys[4][3]~106_combout )) # (!\ula_|zx_keyboard_|extended~q & (((\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[4][3]~134_combout )))) +// \ula_|zx_keyboard_|keys[4][3]~107_combout = (\ula_|zx_keyboard_|extended~q & (((\ula_|zx_keyboard_|keys[4][3]~106_combout )))) # (!\ula_|zx_keyboard_|extended~q & (\ula_|zx_keyboard_|keys[4][3]~132_combout & (\ula_|ps2_keyboard_|shiftreg [4]))) .dataa(\ula_|zx_keyboard_|extended~q ), - .datab(\ula_|zx_keyboard_|keys[4][3]~106_combout ), + .datab(\ula_|zx_keyboard_|keys[4][3]~132_combout ), .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|keys[4][3]~134_combout ), + .datad(\ula_|zx_keyboard_|keys[4][3]~106_combout ), .cin(gnd), .combout(\ula_|zx_keyboard_|keys[4][3]~107_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~107 .lut_mask = 16'hD888; +defparam \ula_|zx_keyboard_|keys[4][3]~107 .lut_mask = 16'hEA40; defparam \ula_|zx_keyboard_|keys[4][3]~107 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y21_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~135 ( +// Location: LCCOMB_X27_Y8_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~133 ( // Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~135_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|shifted~q ))) +// \ula_|zx_keyboard_|keys[4][3]~133_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|shifted~q ))) .dataa(\ula_|zx_keyboard_|extended~q ), .datab(\ula_|zx_keyboard_|released~q ), .datac(\ula_|ps2_keyboard_|shiftreg [5]), .datad(\ula_|zx_keyboard_|shifted~q ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][3]~135_combout ), + .combout(\ula_|zx_keyboard_|keys[4][3]~133_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~135 .lut_mask = 16'hCDCC; -defparam \ula_|zx_keyboard_|keys[4][3]~135 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[4][3]~133 .lut_mask = 16'hCDCC; +defparam \ula_|zx_keyboard_|keys[4][3]~133 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y21_N22 +// Location: LCCOMB_X27_Y8_N6 cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~108 ( // Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~108_combout = (\ula_|zx_keyboard_|keys[4][3]~107_combout & ((\ula_|zx_keyboard_|keys[0][0]~15_combout & ((!\ula_|zx_keyboard_|keys[4][3]~135_combout ))) # (!\ula_|zx_keyboard_|keys[0][0]~15_combout & -// (\ula_|zx_keyboard_|keys[4][3]~q )))) # (!\ula_|zx_keyboard_|keys[4][3]~107_combout & (((\ula_|zx_keyboard_|keys[4][3]~q )))) +// \ula_|zx_keyboard_|keys[4][3]~108_combout = (\ula_|zx_keyboard_|keys[4][3]~107_combout & ((\ula_|zx_keyboard_|keys[0][0]~13_combout & (!\ula_|zx_keyboard_|keys[4][3]~133_combout )) # (!\ula_|zx_keyboard_|keys[0][0]~13_combout & +// ((\ula_|zx_keyboard_|keys[4][3]~q ))))) # (!\ula_|zx_keyboard_|keys[4][3]~107_combout & (((\ula_|zx_keyboard_|keys[4][3]~q )))) .dataa(\ula_|zx_keyboard_|keys[4][3]~107_combout ), - .datab(\ula_|zx_keyboard_|keys[0][0]~15_combout ), + .datab(\ula_|zx_keyboard_|keys[4][3]~133_combout ), .datac(\ula_|zx_keyboard_|keys[4][3]~q ), - .datad(\ula_|zx_keyboard_|keys[4][3]~135_combout ), + .datad(\ula_|zx_keyboard_|keys[0][0]~13_combout ), .cin(gnd), .combout(\ula_|zx_keyboard_|keys[4][3]~108_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~108 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[4][3]~108 .lut_mask = 16'h72F0; defparam \ula_|zx_keyboard_|keys[4][3]~108 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y21_N23 +// Location: FF_X27_Y8_N7 dffeas \ula_|zx_keyboard_|keys[4][3] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\ula_|zx_keyboard_|keys[4][3]~108_combout ), @@ -52233,79 +41655,555 @@ defparam \ula_|zx_keyboard_|keys[4][3] .is_wysiwyg = "true"; defparam \ula_|zx_keyboard_|keys[4][3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y19_N20 -cycloneive_lcell_comb \D[3]~67 ( +// Location: LCCOMB_X28_Y7_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][3]~104 ( // Equation(s): -// \D[3]~67_combout = (\ula_|zx_keyboard_|keys[5][3]~q & (\z80_|address_pins_|abus[13]~20_combout & ((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][3]~q )))) # (!\ula_|zx_keyboard_|keys[5][3]~q & -// (((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][3]~q )))) +// \ula_|zx_keyboard_|keys[5][3]~104_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [5])) - .dataa(\ula_|zx_keyboard_|keys[5][3]~q ), - .datab(\z80_|address_pins_|abus[13]~20_combout ), - .datac(\ula_|zx_keyboard_|keys[4][3]~q ), - .datad(\z80_|address_pins_|abus[12]~21_combout ), + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), .cin(gnd), - .combout(\D[3]~67_combout ), + .combout(\ula_|zx_keyboard_|keys[5][3]~104_combout ), .cout()); // synopsys translate_off -defparam \D[3]~67 .lut_mask = 16'hDD0D; -defparam \D[3]~67 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[5][3]~104 .lut_mask = 16'h0A00; +defparam \ula_|zx_keyboard_|keys[5][3]~104 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X27_Y21_N4 +// Location: LCCOMB_X28_Y7_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][3]~105 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][3]~105_combout = (\ula_|zx_keyboard_|keys[1][4]~23_combout & ((\ula_|zx_keyboard_|keys[5][3]~104_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[5][3]~104_combout & ((\ula_|zx_keyboard_|keys[5][3]~q +// ))))) # (!\ula_|zx_keyboard_|keys[1][4]~23_combout & (((\ula_|zx_keyboard_|keys[5][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[1][4]~23_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[5][3]~q ), + .datad(\ula_|zx_keyboard_|keys[5][3]~104_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][3]~105_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][3]~105 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[5][3]~105 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y7_N23 +dffeas \ula_|zx_keyboard_|keys[5][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[5][3]~105_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[5][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[5][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N12 +cycloneive_lcell_comb \D[3]~55 ( +// Equation(s): +// \D[3]~55_combout = (\z80_|address_pins_|abus[12]~21_combout & (((\z80_|address_pins_|abus[13]~20_combout ) # (!\ula_|zx_keyboard_|keys[5][3]~q )))) # (!\z80_|address_pins_|abus[12]~21_combout & (!\ula_|zx_keyboard_|keys[4][3]~q & +// ((\z80_|address_pins_|abus[13]~20_combout ) # (!\ula_|zx_keyboard_|keys[5][3]~q )))) + + .dataa(\z80_|address_pins_|abus[12]~21_combout ), + .datab(\ula_|zx_keyboard_|keys[4][3]~q ), + .datac(\ula_|zx_keyboard_|keys[5][3]~q ), + .datad(\z80_|address_pins_|abus[13]~20_combout ), + .cin(gnd), + .combout(\D[3]~55_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~55 .lut_mask = 16'hBB0B; +defparam \D[3]~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~46 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][4]~46_combout = (\ula_|zx_keyboard_|keys[7][1]~21_combout & (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|zx_keyboard_|keys[7][1]~21_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][4]~46_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][4]~46 .lut_mask = 16'h0200; +defparam \ula_|zx_keyboard_|keys[6][4]~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~62 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][4]~62_combout = (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][4]~62_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][4]~62 .lut_mask = 16'h00F0; +defparam \ula_|zx_keyboard_|keys[5][4]~62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][3]~102 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][3]~102_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|zx_keyboard_|keys[6][4]~46_combout & (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|zx_keyboard_|keys[5][4]~62_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|zx_keyboard_|keys[6][4]~46_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|zx_keyboard_|keys[5][4]~62_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][3]~102_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][3]~102 .lut_mask = 16'h4000; +defparam \ula_|zx_keyboard_|keys[3][3]~102 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][3]~103 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][3]~103_combout = (\ula_|zx_keyboard_|keys[3][3]~102_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][3]~102_combout & ((\ula_|zx_keyboard_|keys[3][3]~q ))) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[3][3]~q ), + .datad(\ula_|zx_keyboard_|keys[3][3]~102_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][3]~103_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][3]~103 .lut_mask = 16'h33F0; +defparam \ula_|zx_keyboard_|keys[3][3]~103 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y7_N11 +dffeas \ula_|zx_keyboard_|keys[3][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[3][3]~103_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[3][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[3][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~96 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][4]~96_combout = (\ula_|zx_keyboard_|keys[5][1]~34_combout & (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [5] $ (\ula_|ps2_keyboard_|shiftreg [6])))) + + .dataa(\ula_|zx_keyboard_|keys[5][1]~34_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][4]~96_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][4]~96 .lut_mask = 16'h0208; +defparam \ula_|zx_keyboard_|keys[0][4]~96 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~94 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][4]~94_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [6])) + + .dataa(\ula_|zx_keyboard_|shifted~q ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][4]~94_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][4]~94 .lut_mask = 16'hDDCC; +defparam \ula_|zx_keyboard_|keys[2][4]~94 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][3]~95 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][3]~95_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [6]))) # (!\ula_|ps2_keyboard_|shiftreg [1] & +// (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [6]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][3]~95_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][3]~95 .lut_mask = 16'h0810; +defparam \ula_|zx_keyboard_|keys[0][3]~95 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][3]~97 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][3]~97_combout = (\ula_|zx_keyboard_|keys[0][4]~96_combout & ((\ula_|zx_keyboard_|keys[0][3]~95_combout & (!\ula_|zx_keyboard_|keys[2][4]~94_combout )) # (!\ula_|zx_keyboard_|keys[0][3]~95_combout & +// ((\ula_|zx_keyboard_|keys[0][3]~q ))))) # (!\ula_|zx_keyboard_|keys[0][4]~96_combout & (((\ula_|zx_keyboard_|keys[0][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[0][4]~96_combout ), + .datab(\ula_|zx_keyboard_|keys[2][4]~94_combout ), + .datac(\ula_|zx_keyboard_|keys[0][3]~q ), + .datad(\ula_|zx_keyboard_|keys[0][3]~95_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][3]~97_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][3]~97 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[0][3]~97 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y9_N19 +dffeas \ula_|zx_keyboard_|keys[0][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[0][3]~97_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[0][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[0][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~45 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][4]~45_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [1])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][4]~45_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][4]~45 .lut_mask = 16'h5000; +defparam \ula_|zx_keyboard_|keys[6][4]~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][3]~92 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][3]~92_combout = (\ula_|zx_keyboard_|keys[6][4]~45_combout & (\ula_|zx_keyboard_|keys[7][4]~17_combout & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|zx_keyboard_|keys[6][4]~45_combout ), + .datab(\ula_|zx_keyboard_|keys[7][4]~17_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][3]~92_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][3]~92 .lut_mask = 16'h0800; +defparam \ula_|zx_keyboard_|keys[1][3]~92 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][3]~93 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][3]~93_combout = (\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[1][3]~92_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[1][3]~92_combout & ((\ula_|zx_keyboard_|keys[1][3]~q ))))) # +// (!\ula_|ps2_keyboard_|shiftreg [3] & (((\ula_|zx_keyboard_|keys[1][3]~q )))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[1][3]~q ), + .datad(\ula_|zx_keyboard_|keys[1][3]~92_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][3]~93_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][3]~93 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[1][3]~93 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y7_N15 +dffeas \ula_|zx_keyboard_|keys[1][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[1][3]~93_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[1][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[1][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N0 +cycloneive_lcell_comb \D[3]~53 ( +// Equation(s): +// \D[3]~53_combout = (\ula_|zx_keyboard_|keys[0][3]~q & (\z80_|address_pins_|abus[8]~18_combout & ((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][3]~q )))) # (!\ula_|zx_keyboard_|keys[0][3]~q & +// (((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[0][3]~q ), + .datab(\z80_|address_pins_|abus[8]~18_combout ), + .datac(\ula_|zx_keyboard_|keys[1][3]~q ), + .datad(\z80_|address_pins_|abus[9]~17_combout ), + .cin(gnd), + .combout(\D[3]~53_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~53 .lut_mask = 16'hDD0D; +defparam \D[3]~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~99 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][3]~99_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [6])) # (!\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [2] & +// \ula_|ps2_keyboard_|shiftreg [6])) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][3]~99_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][3]~99 .lut_mask = 16'h03C0; +defparam \ula_|zx_keyboard_|keys[2][3]~99 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~100 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][3]~100_combout = (\ula_|zx_keyboard_|keys[2][3]~99_combout & (\ula_|zx_keyboard_|keys[5][4]~62_combout & (\ula_|ps2_keyboard_|shiftreg [2] $ (!\ula_|ps2_keyboard_|shiftreg [3])))) + + .dataa(\ula_|zx_keyboard_|keys[2][3]~99_combout ), + .datab(\ula_|zx_keyboard_|keys[5][4]~62_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][3]~100_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][3]~100 .lut_mask = 16'h8008; +defparam \ula_|zx_keyboard_|keys[2][3]~100 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~98 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][3]~98_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & !\ula_|ps2_keyboard_|shiftreg [2])) + + .dataa(\ula_|zx_keyboard_|shifted~q ), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][3]~98_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][3]~98 .lut_mask = 16'hFF05; +defparam \ula_|zx_keyboard_|keys[2][3]~98 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~101 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][3]~101_combout = (\ula_|zx_keyboard_|keys[5][1]~34_combout & ((\ula_|zx_keyboard_|keys[2][3]~100_combout & ((!\ula_|zx_keyboard_|keys[2][3]~98_combout ))) # (!\ula_|zx_keyboard_|keys[2][3]~100_combout & +// (\ula_|zx_keyboard_|keys[2][3]~q )))) # (!\ula_|zx_keyboard_|keys[5][1]~34_combout & (((\ula_|zx_keyboard_|keys[2][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][1]~34_combout ), + .datab(\ula_|zx_keyboard_|keys[2][3]~100_combout ), + .datac(\ula_|zx_keyboard_|keys[2][3]~q ), + .datad(\ula_|zx_keyboard_|keys[2][3]~98_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][3]~101_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][3]~101 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[2][3]~101 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y9_N9 +dffeas \ula_|zx_keyboard_|keys[2][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[2][3]~101_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[2][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[2][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~3 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row~3_combout = ((\z80_|address_pins_|DFFE_apin_latch [10]) # (!\ula_|zx_keyboard_|keys[2][3]~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|address_pins_|DFFE_apin_latch [10]), + .datac(gnd), + .datad(\ula_|zx_keyboard_|keys[2][3]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row~3 .lut_mask = 16'hDDFF; +defparam \ula_|zx_keyboard_|key_row~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N20 +cycloneive_lcell_comb \D[3]~54 ( +// Equation(s): +// \D[3]~54_combout = (\D[3]~53_combout & (\ula_|zx_keyboard_|key_row~3_combout & ((\z80_|address_pins_|abus[11]~19_combout ) # (!\ula_|zx_keyboard_|keys[3][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[3][3]~q ), + .datab(\D[3]~53_combout ), + .datac(\z80_|address_pins_|abus[11]~19_combout ), + .datad(\ula_|zx_keyboard_|key_row~3_combout ), + .cin(gnd), + .combout(\D[3]~54_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~54 .lut_mask = 16'hC400; +defparam \D[3]~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~109 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][4]~109_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [6])) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|shifted~q ), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][4]~109_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][4]~109 .lut_mask = 16'hFFC0; +defparam \ula_|zx_keyboard_|keys[0][4]~109 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~60 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][2]~60_combout = (\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [6]) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][2]~60_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2]~60 .lut_mask = 16'h0C0C; +defparam \ula_|zx_keyboard_|keys[7][2]~60 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][3]~110 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][3]~110_combout = (\ula_|zx_keyboard_|WideOr16~2_combout & ((\ula_|zx_keyboard_|keys[7][2]~30_combout ) # ((\ula_|zx_keyboard_|keys[7][2]~60_combout & \ula_|ps2_keyboard_|shiftreg [4])))) + + .dataa(\ula_|zx_keyboard_|keys[7][2]~60_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|zx_keyboard_|WideOr16~2_combout ), + .datad(\ula_|zx_keyboard_|keys[7][2]~30_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][3]~110_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][3]~110 .lut_mask = 16'hF080; +defparam \ula_|zx_keyboard_|keys[7][3]~110 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][3]~111 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][3]~111_combout = (\ula_|zx_keyboard_|keys[0][0]~13_combout & (!\ula_|zx_keyboard_|extended~q & (\ula_|zx_keyboard_|keys[7][3]~110_combout & !\ula_|ps2_keyboard_|shiftreg [2]))) + + .dataa(\ula_|zx_keyboard_|keys[0][0]~13_combout ), + .datab(\ula_|zx_keyboard_|extended~q ), + .datac(\ula_|zx_keyboard_|keys[7][3]~110_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][3]~111_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][3]~111 .lut_mask = 16'h0020; +defparam \ula_|zx_keyboard_|keys[7][3]~111 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N14 cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][3]~112 ( // Equation(s): -// \ula_|zx_keyboard_|keys[7][3]~112_combout = (\ula_|zx_keyboard_|WideOr16~2_combout & ((\ula_|zx_keyboard_|keys[7][2]~32_combout ) # ((\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[7][2]~61_combout )))) +// \ula_|zx_keyboard_|keys[7][3]~112_combout = (\ula_|zx_keyboard_|keys[7][3]~111_combout & (!\ula_|zx_keyboard_|keys[0][4]~109_combout )) # (!\ula_|zx_keyboard_|keys[7][3]~111_combout & ((\ula_|zx_keyboard_|keys[7][3]~q ))) - .dataa(\ula_|zx_keyboard_|WideOr16~2_combout ), - .datab(\ula_|zx_keyboard_|keys[7][2]~32_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|keys[7][2]~61_combout ), + .dataa(\ula_|zx_keyboard_|keys[0][4]~109_combout ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[7][3]~q ), + .datad(\ula_|zx_keyboard_|keys[7][3]~111_combout ), .cin(gnd), .combout(\ula_|zx_keyboard_|keys[7][3]~112_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][3]~112 .lut_mask = 16'hA888; +defparam \ula_|zx_keyboard_|keys[7][3]~112 .lut_mask = 16'h55F0; defparam \ula_|zx_keyboard_|keys[7][3]~112 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X27_Y21_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][3]~113 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][3]~113_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|keys[7][3]~112_combout & (\ula_|zx_keyboard_|keys[0][0]~15_combout & !\ula_|zx_keyboard_|extended~q ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|zx_keyboard_|keys[7][3]~112_combout ), - .datac(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .datad(\ula_|zx_keyboard_|extended~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][3]~113_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][3]~113 .lut_mask = 16'h0040; -defparam \ula_|zx_keyboard_|keys[7][3]~113 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y20_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][3]~114 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][3]~114_combout = (\ula_|zx_keyboard_|keys[7][3]~113_combout & ((!\ula_|zx_keyboard_|keys[0][4]~111_combout ))) # (!\ula_|zx_keyboard_|keys[7][3]~113_combout & (\ula_|zx_keyboard_|keys[7][3]~q )) - - .dataa(gnd), - .datab(\ula_|zx_keyboard_|keys[7][3]~113_combout ), - .datac(\ula_|zx_keyboard_|keys[7][3]~q ), - .datad(\ula_|zx_keyboard_|keys[0][4]~111_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][3]~114_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][3]~114 .lut_mask = 16'h30FC; -defparam \ula_|zx_keyboard_|keys[7][3]~114 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y20_N9 +// Location: FF_X29_Y9_N15 dffeas \ula_|zx_keyboard_|keys[7][3] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[7][3]~114_combout ), + .d(\ula_|zx_keyboard_|keys[7][3]~112_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -52321,79 +42219,96 @@ defparam \ula_|zx_keyboard_|keys[7][3] .is_wysiwyg = "true"; defparam \ula_|zx_keyboard_|keys[7][3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X27_Y21_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~109 ( +// Location: LCCOMB_X28_Y9_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|Selector13~0 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][3]~109_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [5]))) +// \ula_|zx_keyboard_|Selector13~0_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|shifted~q )) - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), + .datab(\ula_|zx_keyboard_|shifted~q ), + .datac(gnd), + .datad(\ula_|zx_keyboard_|released~q ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][3]~109_combout ), + .combout(\ula_|zx_keyboard_|Selector13~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][3]~109 .lut_mask = 16'h1000; -defparam \ula_|zx_keyboard_|keys[6][3]~109 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|Selector13~0 .lut_mask = 16'hFF44; +defparam \ula_|zx_keyboard_|Selector13~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X27_Y21_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~110 ( +// Location: LCCOMB_X29_Y9_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~113 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][3]~110_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (((\ula_|zx_keyboard_|keys[6][3]~109_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|keys[7][2]~32_combout ))) +// \ula_|zx_keyboard_|keys[6][3]~113_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [2]))) - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|zx_keyboard_|keys[7][2]~32_combout ), - .datac(\ula_|zx_keyboard_|keys[6][3]~109_combout ), + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][3]~113_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][3]~113 .lut_mask = 16'h0040; +defparam \ula_|zx_keyboard_|keys[6][3]~113 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~114 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][3]~114_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|zx_keyboard_|keys[6][3]~113_combout )) # (!\ula_|ps2_keyboard_|shiftreg [0] & (((\ula_|ps2_keyboard_|shiftreg [2] & \ula_|zx_keyboard_|keys[7][2]~30_combout )))) + + .dataa(\ula_|zx_keyboard_|keys[6][3]~113_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|zx_keyboard_|keys[7][2]~30_combout ), .datad(\ula_|ps2_keyboard_|shiftreg [0]), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][3]~110_combout ), + .combout(\ula_|zx_keyboard_|keys[6][3]~114_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][3]~110 .lut_mask = 16'hF088; -defparam \ula_|zx_keyboard_|keys[6][3]~110 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[6][3]~114 .lut_mask = 16'hAAC0; +defparam \ula_|zx_keyboard_|keys[6][3]~114 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y21_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~137 ( +// Location: LCCOMB_X29_Y9_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~135 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][3]~137_combout = (\ula_|zx_keyboard_|extended~q ) # (((!\ula_|zx_keyboard_|keys[0][0]~15_combout ) # (!\ula_|ps2_keyboard_|shiftreg [3])) # (!\ula_|zx_keyboard_|keys[6][3]~110_combout )) +// \ula_|zx_keyboard_|keys[6][3]~135_combout = ((\ula_|zx_keyboard_|extended~q ) # ((!\ula_|zx_keyboard_|keys[6][3]~114_combout ) # (!\ula_|ps2_keyboard_|shiftreg [3]))) # (!\ula_|zx_keyboard_|keys[0][0]~13_combout ) - .dataa(\ula_|zx_keyboard_|extended~q ), - .datab(\ula_|zx_keyboard_|keys[6][3]~110_combout ), + .dataa(\ula_|zx_keyboard_|keys[0][0]~13_combout ), + .datab(\ula_|zx_keyboard_|extended~q ), .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|zx_keyboard_|keys[0][0]~15_combout ), + .datad(\ula_|zx_keyboard_|keys[6][3]~114_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][3]~137_combout ), + .combout(\ula_|zx_keyboard_|keys[6][3]~135_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][3]~137 .lut_mask = 16'hBFFF; -defparam \ula_|zx_keyboard_|keys[6][3]~137 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[6][3]~135 .lut_mask = 16'hDFFF; +defparam \ula_|zx_keyboard_|keys[6][3]~135 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y21_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~138 ( +// Location: LCCOMB_X29_Y9_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~136 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][3]~138_combout = (\ula_|ps2_keyboard_|shiftreg [1] & ((\ula_|zx_keyboard_|keys[6][3]~137_combout & ((\ula_|zx_keyboard_|keys[6][3]~q ))) # (!\ula_|zx_keyboard_|keys[6][3]~137_combout & -// (!\ula_|zx_keyboard_|Selector13~0_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [1] & (((\ula_|zx_keyboard_|keys[6][3]~q )))) +// \ula_|zx_keyboard_|keys[6][3]~136_combout = (\ula_|zx_keyboard_|keys[6][3]~135_combout & (((\ula_|zx_keyboard_|keys[6][3]~q )))) # (!\ula_|zx_keyboard_|keys[6][3]~135_combout & ((\ula_|ps2_keyboard_|shiftreg [1] & +// (!\ula_|zx_keyboard_|Selector13~0_combout )) # (!\ula_|ps2_keyboard_|shiftreg [1] & ((\ula_|zx_keyboard_|keys[6][3]~q ))))) - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|zx_keyboard_|Selector13~0_combout ), + .dataa(\ula_|zx_keyboard_|Selector13~0_combout ), + .datab(\ula_|zx_keyboard_|keys[6][3]~135_combout ), .datac(\ula_|zx_keyboard_|keys[6][3]~q ), - .datad(\ula_|zx_keyboard_|keys[6][3]~137_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][3]~138_combout ), + .combout(\ula_|zx_keyboard_|keys[6][3]~136_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][3]~138 .lut_mask = 16'hF072; -defparam \ula_|zx_keyboard_|keys[6][3]~138 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[6][3]~136 .lut_mask = 16'hD1F0; +defparam \ula_|zx_keyboard_|keys[6][3]~136 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y21_N29 +// Location: FF_X29_Y9_N9 dffeas \ula_|zx_keyboard_|keys[6][3] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[6][3]~138_combout ), + .d(\ula_|zx_keyboard_|keys[6][3]~136_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -52409,247 +42324,42 @@ defparam \ula_|zx_keyboard_|keys[6][3] .is_wysiwyg = "true"; defparam \ula_|zx_keyboard_|keys[6][3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~2 ( +// Location: LCCOMB_X29_Y9_N30 +cycloneive_lcell_comb \D[3]~56 ( // Equation(s): -// \ula_|zx_keyboard_|key_row~2_combout = (\z80_|address_pins_|DFFE_apin_latch [14]) # ((!\ula_|zx_keyboard_|keys[6][3]~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) +// \D[3]~56_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\z80_|address_pins_|abus[15]~22_combout )) # (!\ula_|zx_keyboard_|keys[7][3]~q ))) # (!\z80_|address_pins_|abus[14]~23_combout & (!\ula_|zx_keyboard_|keys[6][3]~q & +// ((\z80_|address_pins_|abus[15]~22_combout ) # (!\ula_|zx_keyboard_|keys[7][3]~q )))) - .dataa(gnd), - .datab(\z80_|address_pins_|DFFE_apin_latch [14]), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\ula_|zx_keyboard_|keys[6][3]~q ), + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\ula_|zx_keyboard_|keys[7][3]~q ), + .datac(\ula_|zx_keyboard_|keys[6][3]~q ), + .datad(\z80_|address_pins_|abus[15]~22_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|key_row~2_combout ), + .combout(\D[3]~56_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|key_row~2 .lut_mask = 16'hCFFF; -defparam \ula_|zx_keyboard_|key_row~2 .sum_lutc_input = "datac"; +defparam \D[3]~56 .lut_mask = 16'hAF23; +defparam \D[3]~56 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N8 -cycloneive_lcell_comb \D[3]~68 ( +// Location: LCCOMB_X28_Y7_N30 +cycloneive_lcell_comb \D[3]~57 ( // Equation(s): -// \D[3]~68_combout = (\D[3]~67_combout & (\ula_|zx_keyboard_|key_row~2_combout & ((\z80_|address_pins_|abus[15]~22_combout ) # (!\ula_|zx_keyboard_|keys[7][3]~q )))) +// \D[3]~57_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[3]~55_combout & (\D[3]~54_combout & \D[3]~56_combout ))) - .dataa(\z80_|address_pins_|abus[15]~22_combout ), - .datab(\D[3]~67_combout ), - .datac(\ula_|zx_keyboard_|keys[7][3]~q ), - .datad(\ula_|zx_keyboard_|key_row~2_combout ), + .dataa(\D[3]~55_combout ), + .datab(\D[3]~54_combout ), + .datac(\z80_|address_pins_|abus[0]~16_combout ), + .datad(\D[3]~56_combout ), .cin(gnd), - .combout(\D[3]~68_combout ), + .combout(\D[3]~57_combout ), .cout()); // synopsys translate_off -defparam \D[3]~68 .lut_mask = 16'h8C00; -defparam \D[3]~68 .sum_lutc_input = "datac"; +defparam \D[3]~57 .lut_mask = 16'hF8F0; +defparam \D[3]~57 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N30 -cycloneive_lcell_comb \D[3]~69 ( -// Equation(s): -// \D[3]~69_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[3]~65_combout & (\D[3]~66_combout & \D[3]~68_combout ))) - - .dataa(\D[3]~65_combout ), - .datab(\z80_|address_pins_|abus[0]~16_combout ), - .datac(\D[3]~66_combout ), - .datad(\D[3]~68_combout ), - .cin(gnd), - .combout(\D[3]~69_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~69 .lut_mask = 16'hECCC; -defparam \D[3]~69 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y11_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a19 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[3]~96_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_first_bit_number = 3; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y15_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a3 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[3]~96_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; -// synopsys translate_on - -// Location: M9K_X22_Y18_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a11 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[3]~96_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X23_Y15_N14 -cycloneive_lcell_comb \D[3]~73 ( -// Equation(s): -// \D[3]~73_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ) # (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout & ((!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ), - .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .cin(gnd), - .combout(\D[3]~73_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~73 .lut_mask = 16'hCCE2; -defparam \D[3]~73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y5_N0 +// Location: M9K_X33_Y14_N0 cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a27 ( .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), .portare(vcc), @@ -52665,7 +42375,7 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a27 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[3]~96_combout }), + .portadatain({\D[3]~74_combout }), .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , \z80_|address_pins_|abus[0]~16_combout }), @@ -52706,25 +42416,274 @@ defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init1 = 20 defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N16 -cycloneive_lcell_comb \D[3]~74 ( -// Equation(s): -// \D[3]~74_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\D[3]~73_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ))) # (!\D[3]~73_combout & -// (\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\D[3]~73_combout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ), - .datac(\D[3]~73_combout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ), - .cin(gnd), - .combout(\D[3]~74_combout ), - .cout()); +// Location: M9K_X22_Y14_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a3 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[3]~74_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), + .portbdataout()); // synopsys translate_off -defparam \D[3]~74 .lut_mask = 16'hF858; -defparam \D[3]~74 .sum_lutc_input = "datac"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; // synopsys translate_on -// Location: M9K_X22_Y19_N0 +// Location: M9K_X22_Y13_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a19 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[3]~74_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_first_bit_number = 3; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X23_Y14_N26 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6 .lut_mask = 16'hF4A4; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y16_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a11 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[3]~74_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X23_Y14_N22 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout & +// (\ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout )) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ))))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7 .lut_mask = 16'hDAD0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y20_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a3 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h7BBD7F79FFE0AB8FC33758D1C1145DDD6311CF69FFFDF62EDD236FC6A0358FA2B4B15EB89456517DFF58F68BDADB95B5F764CAE7E7C7E7D70CADB8FFD8F9A72BFBB9EB400590D7F939FF5A70A29817DC2CC29B679B2D7146BD21D47EF06F7D5EAF72F66DC666B0726D66FD941AD9BC6D758D5EC24DFEBA64871D6B86D37DF1DFBFF05FBD6AD8CA62C6CBE43BDBFD99E9EB6DD724D235FBEA9FE7D6767D811C40681A00AF8D864D8BB6D2A0916C8A93250A76B8A977F82E8FDFBE68F8E0F8DF237CA976FE488D1069D687A6F1D68A70F37CAAA367A74CBB75D3A6FFB4B1E8D4B7F7F22D2FE1509BDF80E6DD7B717D7E9C6531C3A86BE9F1D7A6AFD5BFB7A37A60; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h8AB3B7FDEE7B9CC735FCCE93E3AC1AAAA691AD6350E57F1F5773302B6F36F63D130E0574D6BB44B2C0D7A907702A748D0BA50F8FA5437ACD3B343C35039F44D19CD4E55E6CB00410842B02A7FD105706DF9E2A1FA025005632A0CC080400D280CCCA0665222D038CC873351A21B23939A98CC08803282189C8440D40CD40462421A40982C046D22C10146484345CAF7BC828BFE79DFBE3C631CBF660C487EBB759BD7F8DE9E0F27A65DE5245BEB8F7829C36F0D136168F97C2BD77D649A39EB4DDB3A42AC80797FDEF4DE3EEF7ED8C7307E4CE6A6317F7BF25D077BBF03AEA3363B065F7D671322D6BFB2B8759433929CEC27E3FD7741292A4A5AF02703CC4E3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'hFD5CB07B6C729B510A78BEC5F7C7A1E7809F1976D0DD3615C1D27D2DF596BFE7A8BCDC2E6655185CC45008B39EFD1FA6E9F5E816114F93E1E7A2A27C72C7349F3497229CB9044B6E7A7861A04A712AAF29EFBD393727F1F3FC2AA1E6CF571457F0A09C47F23F20FE2AABF5FD3ABE6167E5FD36E1D9735BBD5375C1F79BD0424ECF133BF47B9D3DA46DD6DBF3A8ADCDD3DF1176D2FE23447DFC65E1DD7BF3BE5E1C9DCD8EBB9D36AF570CF25CDD16F645D1DE9F9EE575E3A2B91D5659FC131CE3DCD4560015805B13AC0290001EF8261B7E4EB867C828D9777FFF47B6903008DDD7D77EF5E2C6D7220BE64B3C6E9EF22AFDFCC8005C2FFFFA3AB9AD1ADFC0AFE7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h06ABC52D5DBEF57EEB3311A9D85D253B44E250E1566BED57C6DBEB2ABFD1ADF6FF4DEBFBDEB376DF68D5EEDB5EB4D5AB5B79745D76CD8ADC59CB30C8AA33E1551D2FCA8DCB43C5356BAE638588C302868CE1161CACADFEF7696F8C3AA82EC16F47A8EA413A2DCF09B996582318DBF3C4711871B3BC0404EC45252A485234A663C1FFFB3487617BE24FD79501DE05F1A341B89EC82FD5702497FD866639C0DE08B383E6E7C3B310E1F7FF595C5DF6F0E9A9FFFBE16D3FFBE82C1E0051F1E060D500812F408CC6501331852531B04480021D9220D4903A41404312032840153FE9CC8070206B8245AC240020752EBC2BEF3E74AB288F360C239C4AFAE93F68775A; +// synopsys translate_on + +// Location: M9K_X22_Y32_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a11 ( .portawe(vcc), .portare(vcc), @@ -52732,7 +42691,7 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a11 ( .portbwe(gnd), .portbre(vcc), .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .clk1(gnd), .ena0(\z80_|address_pins_|abus[13]~20_combout ), .ena1(vcc), @@ -52782,9 +42741,9 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 204 defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h420539B476E305B8200E47DFAAE8D5D1D0724DCC3FD72C4F8DE54622A1DD1BA78CA3CE9F24BEFA9E2BB9D89B423C327C8E050114401A62FDCD2054E166C0005F7941B61372AC884EE60A372057B59CFF30A6020B875C06E7C5FBDF9A91F8F0588ED67F67AA66B0674CD240410F613700B8DFE7F8837F88FF4520002E4BFD7FA2768008002000002624793100811F43BC315A6004052671392B47FEB7F5DC90E62175C7B8FC48FCC916D46F9315DFDECBE43E5F03D7D27F97E09E4700AA694552A1FF3BE5E159FFDDEB2FBECAEB87BBCC5FCF6E23D77E4DD4C9DEBC93C10F636326FAFE3BE30DFAF7B9E7A5FFE44BF314DAA1C1529CDBFFE9D94EB11A9F68D4DF; // synopsys translate_on -// Location: M9K_X22_Y23_N0 +// Location: M9K_X22_Y22_N0 cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a11 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), @@ -52798,7 +42757,7 @@ cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a11 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[3]~96_combout }), + .portadatain({\D[3]~74_combout }), .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , \z80_|address_pins_|abus[0]~16_combout }), @@ -52855,103 +42814,9 @@ defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 20 defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N24 -cycloneive_lcell_comb \D[3]~70 ( -// Equation(s): -// \D[3]~70_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\z80_|address_pins_|abus[14]~23_combout & ((\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ))) # (!\z80_|address_pins_|abus[14]~23_combout & -// (\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\z80_|address_pins_|abus[14]~23_combout )) - - .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\z80_|address_pins_|abus[14]~23_combout ), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ), - .cin(gnd), - .combout(\D[3]~70_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~70 .lut_mask = 16'hEC64; -defparam \D[3]~70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y21_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a3 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h7BBD7F79FFE0AB8FC33758D1C1145DDD6311CF69FFFDF62EDD236FC6A0358FA2B4B15EB89456517DFF58F68BDADB95B5F764CAE7E7C7E7D70CADB8FFD8F9A72BFBB9EB400590D7F939FF5A70A29817DC2CC29B679B2D7146BD21D47EF06F7D5EAF72F66DC666B0726D66FD941AD9BC6D758D5EC24DFEBA64871D6B86D37DF1DFBFF05FBD6AD8CA62C6CBE43BDBFD99E9EB6DD724D235FBEA9FE7D6767D811C40681A00AF8D864D8BB6D2A0916C8A93250A76B8A977F82E8FDFBE68F8E0F8DF237CA976FE488D1069D687A6F1D68A70F37CAAA367A74CBB75D3A6FFB4B1E8D4B7F7F22D2FE1509BDF80E6DD7B717D7E9C6531C3A86BE9F1D7A6AFD5BFB7A37A60; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h8AB3B7FDEE7B9CC735FCCE93E3AC1AAAA691AD6350E57F1F5773302B6F36F63D130E0574D6BB44B2C0D7A907702A748D0BA50F8FA5437ACD3B343C35039F44D19CD4E55E6CB00410842B02A7FD105706DF9E2A1FA025005632A0CC080400D280CCCA0665222D038CC873351A21B23939A98CC08803282189C8440D40CD40462421A40982C046D22C10146484345CAF7BC828BFE79DFBE3C631CBF660C487EBB759BD7F8DE9E0F27A65DE5245BEB8F7829C36F0D136168F97C2BD77D649A39EB4DDB3A42AC80797FDEF4DE3EEF7ED8C7307E4CE6A6317F7BF25D077BBF03AEA3363B065F7D671322D6BFB2B8759433929CEC27E3FD7741292A4A5AF02703CC4E3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'hFD5CB07B6C729B510A78BEC5F7C7A1E7809F1976D0DD3615C1D27D2DF596BFE7A8BCDC2E6655185CC45008B39EFD1FA6E9F5E816114F93E1E7A2A27C72C7349F3497229CB9044B6E7A7861A04A712AAF29EFBD393727F1F3FC2AA1E6CF571457F0A09C47F23F20FE2AABF5FD3ABE6167E5FD36E1D9735BBD5375C1F79BD0424ECF133BF47B9D3DA46DD6DBF3A8ADCDD3DF1176D2FE23447DFC65E1DD7BF3BE5E1C9DCD8EBB9D36AF570CF25CDD16F645D1DE9F9EE575E3A2B91D5659FC131CE3DCD4560015805B13AC0290001EF8261B7E4EB867C828D9777FFF47B6903008DDD7D77EF5E2C6D7220BE64B3C6E9EF22AFDFCC8005C2FFFFA3AB9AD1ADFC0AFE7; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h06ABC52D5DBEF57EEB3311A9D85D253B44E250E1566BED57C6DBEB2ABFD1ADF6FF4DEBFBDEB376DF68D5EEDB5EB4D5AB5B79745D76CD8ADC59CB30C8AA33E1551D2FCA8DCB43C5356BAE638588C302868CE1161CACADFEF7696F8C3AA82EC16F47A8EA413A2DCF09B996582318DBF3C4711871B3BC0404EC45252A485234A663C1FFFB3487617BE24FD79501DE05F1A341B89EC82FD5702497FD866639C0DE08B383E6E7C3B310E1F7FF595C5DF6F0E9A9FFFBE16D3FFBE82C1E0051F1E060D500812F408CC6501331852531B04480021D9220D4903A41404312032840153FE9CC8070206B8245AC240020752EBC2BEF3E74AB288F360C239C4AFAE93F68775A; -// synopsys translate_on - -// Location: LCCOMB_X23_Y15_N22 -cycloneive_lcell_comb \D[3]~71 ( -// Equation(s): -// \D[3]~71_combout = (\z80_|address_pins_|abus[15]~22_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout $ (((\D[3]~70_combout ))))) # (!\z80_|address_pins_|abus[15]~22_combout & -// (((\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout & !\D[3]~70_combout )))) - - .dataa(\z80_|address_pins_|abus[15]~22_combout ), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ), - .datad(\D[3]~70_combout ), - .cin(gnd), - .combout(\D[3]~71_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~71 .lut_mask = 16'h22D8; -defparam \D[3]~71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y31_N0 +// Location: M9K_X22_Y30_N0 cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a3 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), @@ -52965,7 +42830,7 @@ cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a3 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[3]~96_combout }), + .portadatain({\D[3]~74_combout }), .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , \z80_|address_pins_|abus[0]~16_combout }), @@ -53021,95 +42886,113 @@ defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 204 defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h022388704B6887014BD84185680166815764AC0148D308813FFFFFFC0000000003228A304BA085014BFC40816C0166915375AC0140D308013FFFFFFC40000000432289294EB08F014A1C40816C016681537DA80140D10E01400000017FFFFFFE406281154FB08D014A0040894C016299437DB00140D10F01400000037FFFFFFE4062A13149A88D814BE0429146016EA14179B001405107017FFFFFFF0000000043E0812549C889814BE0528146016C814179924140511F413FFFFFFE0000000043E881314EE881814A00468147436C814159100100513F0000000000FFFFFFFF4B6883014EA881814800668147C22C814019900100003E0000000000FFFFFFFF; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N20 -cycloneive_lcell_comb \D[3]~72 ( +// Location: LCCOMB_X23_Y14_N24 +cycloneive_lcell_comb \Selector3~1 ( // Equation(s): -// \D[3]~72_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\D[3]~70_combout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[3]~70_combout & (!\D[3]~71_combout & -// \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout )) # (!\D[3]~70_combout & (\D[3]~71_combout )))) +// \Selector3~1_combout = (\Selector3~0_combout & (((\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout )) # (!\z80_|address_pins_|abus[14]~23_combout ))) # (!\Selector3~0_combout & (\z80_|address_pins_|abus[14]~23_combout & +// ((\ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout )))) - .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\D[3]~70_combout ), - .datac(\D[3]~71_combout ), + .dataa(\Selector3~0_combout ), + .datab(\z80_|address_pins_|abus[14]~23_combout ), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ), .datad(\ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ), .cin(gnd), - .combout(\D[3]~72_combout ), + .combout(\Selector3~1_combout ), .cout()); // synopsys translate_off -defparam \D[3]~72 .lut_mask = 16'h9C98; -defparam \D[3]~72 .sum_lutc_input = "datac"; +defparam \Selector3~1 .lut_mask = 16'hE6A2; +defparam \Selector3~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N28 -cycloneive_lcell_comb \D[3]~108 ( +// Location: LCCOMB_X23_Y14_N16 +cycloneive_lcell_comb \Selector3~2 ( // Equation(s): -// \D[3]~108_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (\D[3]~74_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\D[3]~72_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & -// (\D[3]~74_combout )))) +// \Selector3~2_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\Selector3~1_combout )))) # (!\z80_|address_pins_|abus[14]~23_combout & ((\Selector3~1_combout & ((\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ))) # +// (!\Selector3~1_combout & (\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout )))) + + .dataa(\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ), + .datab(\z80_|address_pins_|abus[14]~23_combout ), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ), + .datad(\Selector3~1_combout ), + .cin(gnd), + .combout(\Selector3~2_combout ), + .cout()); +// synopsys translate_off +defparam \Selector3~2 .lut_mask = 16'hFC22; +defparam \Selector3~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y14_N10 +cycloneive_lcell_comb \D[3]~85 ( +// Equation(s): +// \D[3]~85_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\Selector3~2_combout +// ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout )))) .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), - .datab(\D[3]~74_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\D[3]~72_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout ), + .datad(\Selector3~2_combout ), .cin(gnd), - .combout(\D[3]~108_combout ), + .combout(\D[3]~85_combout ), .cout()); // synopsys translate_off -defparam \D[3]~108 .lut_mask = 16'hDC8C; -defparam \D[3]~108 .sum_lutc_input = "datac"; +defparam \D[3]~85 .lut_mask = 16'hF4B0; +defparam \D[3]~85 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N4 -cycloneive_lcell_comb \D[3]~95 ( +// Location: LCCOMB_X23_Y14_N2 +cycloneive_lcell_comb \D[3]~73 ( // Equation(s): -// \D[3]~95_combout = ((\Equal2~0_combout & (\D[3]~69_combout )) # (!\Equal2~0_combout & ((\D[3]~108_combout )))) # (!\Equal2~1_combout ) +// \D[3]~73_combout = ((\Equal2~0_combout & (\D[3]~57_combout )) # (!\Equal2~0_combout & ((\D[3]~85_combout )))) # (!\Equal2~1_combout ) - .dataa(\D[3]~69_combout ), + .dataa(\D[3]~57_combout ), .datab(\Equal2~1_combout ), .datac(\Equal2~0_combout ), - .datad(\D[3]~108_combout ), + .datad(\D[3]~85_combout ), .cin(gnd), - .combout(\D[3]~95_combout ), + .combout(\D[3]~73_combout ), .cout()); // synopsys translate_off -defparam \D[3]~95 .lut_mask = 16'hBFB3; -defparam \D[3]~95 .sum_lutc_input = "datac"; +defparam \D[3]~73 .lut_mask = 16'hBFB3; +defparam \D[3]~73 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N26 -cycloneive_lcell_comb \D[3]~96 ( +// Location: LCCOMB_X23_Y14_N8 +cycloneive_lcell_comb \D[3]~74 ( // Equation(s): -// \D[3]~96_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\z80_|data_pins_|dout [3] & \D[3]~95_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\D[3]~95_combout )) # (!\Equal2~1_combout ))) +// \D[3]~74_combout = (\z80_|pin_control_|bus_db_pin_oe~15_combout & (\z80_|data_pins_|dout [3] & ((\D[3]~73_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout & (((\D[3]~73_combout ) # (!\Equal2~1_combout )))) - .dataa(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .dataa(\z80_|data_pins_|dout [3]), .datab(\Equal2~1_combout ), - .datac(\z80_|data_pins_|dout [3]), - .datad(\D[3]~95_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .datad(\D[3]~73_combout ), .cin(gnd), - .combout(\D[3]~96_combout ), + .combout(\D[3]~74_combout ), .cout()); // synopsys translate_off -defparam \D[3]~96 .lut_mask = 16'hF511; -defparam \D[3]~96 .sum_lutc_input = "datac"; +defparam \D[3]~74 .lut_mask = 16'hAF03; +defparam \D[3]~74 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y13_N6 +// Location: LCCOMB_X30_Y13_N16 cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] ( // Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [3] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[3]~21_combout ) # ((\D[3]~96_combout & \z80_|pin_control_|bus_db_pin_re~combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & -// (\D[3]~96_combout & (\z80_|pin_control_|bus_db_pin_re~combout ))) +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [3] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[3]~21_combout ) # ((\z80_|pin_control_|bus_db_pin_re~combout & \D[3]~74_combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & +// (\z80_|pin_control_|bus_db_pin_re~combout & ((\D[3]~74_combout )))) .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(\D[3]~96_combout ), - .datac(\z80_|pin_control_|bus_db_pin_re~combout ), - .datad(\z80_|bus_control_|db[3]~21_combout ), + .datab(\z80_|pin_control_|bus_db_pin_re~combout ), + .datac(\z80_|bus_control_|db[3]~21_combout ), + .datad(\D[3]~74_combout ), .cin(gnd), .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [3]), .cout()); // synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] .lut_mask = 16'hEAC0; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] .lut_mask = 16'hECA0; defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y13_N7 +// Location: FF_X30_Y13_N17 dffeas \z80_|data_pins_|dout[3] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [3]), @@ -53128,44 +43011,903 @@ defparam \z80_|data_pins_|dout[3] .is_wysiwyg = "true"; defparam \z80_|data_pins_|dout[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N4 +// Location: LCCOMB_X29_Y13_N20 cycloneive_lcell_comb \z80_|bus_control_|db[3]~20 ( // Equation(s): // \z80_|bus_control_|db[3]~20_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [3]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) - .dataa(\z80_|execute_|ctl_bus_db_oe~combout ), - .datab(\z80_|data_pins_|dout [3]), - .datac(gnd), - .datad(\z80_|bus_control_|db[0]~4_combout ), + .dataa(gnd), + .datab(\z80_|bus_control_|db[0]~4_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~combout ), + .datad(\z80_|data_pins_|dout [3]), .cin(gnd), .combout(\z80_|bus_control_|db[3]~20_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[3]~20 .lut_mask = 16'hDD00; +defparam \z80_|bus_control_|db[3]~20 .lut_mask = 16'hCC0C; defparam \z80_|bus_control_|db[3]~20 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y10_N0 +// Location: LCCOMB_X30_Y17_N30 cycloneive_lcell_comb \z80_|bus_control_|db[3]~21 ( // Equation(s): // \z80_|bus_control_|db[3]~21_combout = ((\z80_|bus_control_|db[3]~20_combout & ((\z80_|alu_control_|db[3]~35_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) .dataa(\z80_|bus_control_|db[0]~6_combout ), - .datab(\z80_|bus_control_|db[3]~20_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|alu_control_|db[3]~35_combout ), + .datab(\z80_|alu_control_|db[3]~35_combout ), + .datac(\z80_|bus_control_|db[3]~20_combout ), + .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), .cin(gnd), .combout(\z80_|bus_control_|db[3]~21_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[3]~21 .lut_mask = 16'hDD5D; +defparam \z80_|bus_control_|db[3]~21 .lut_mask = 16'hD5F5; defparam \z80_|bus_control_|db[3]~21 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X34_Y10_N1 -dffeas \z80_|ir_|opcode[3] ( +// Location: LCCOMB_X30_Y17_N12 +cycloneive_lcell_comb \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 ( +// Equation(s): +// \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout = (\z80_|bus_control_|db[4]~19_combout & \z80_|bus_control_|db[3]~21_combout ) + + .dataa(gnd), + .datab(\z80_|bus_control_|db[4]~19_combout ), + .datac(\z80_|bus_control_|db[3]~21_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 .lut_mask = 16'hC0C0; +defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y17_N13 +dffeas \z80_|interrupts_|im2 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|bus_control_|db[3]~21_combout ), + .d(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_im_we~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|interrupts_|im2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|interrupts_|im2 .is_wysiwyg = "true"; +defparam \z80_|interrupts_|im2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~10 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~10_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|interrupts_|im2~q & \z80_|interrupts_|DFFE_inst44~q )) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|interrupts_|im2~q ), + .datac(\z80_|interrupts_|DFFE_inst44~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~10 .lut_mask = 16'h4040; +defparam \z80_|execute_|ctl_mRead~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_mask543_en~0 ( +// Equation(s): +// \z80_|execute_|ctl_sw_mask543_en~0_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (!\z80_|execute_|ctl_mRead~10_combout & (\z80_|pla_decode_|Equal47~0_combout & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|execute_|ctl_mRead~10_combout ), + .datac(\z80_|pla_decode_|Equal47~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_mask543_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_mask543_en~0 .lut_mask = 16'h1000; +defparam \z80_|execute_|ctl_sw_mask543_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N24 +cycloneive_lcell_comb \z80_|alu_control_|db[7]~16 ( +// Equation(s): +// \z80_|alu_control_|db[7]~16_combout = (\z80_|alu_flags_|DFFE_inst_latch_sf~q & (!\z80_|alu_|db[7]~12_combout & ((\z80_|execute_|ctl_sw_2u~7_combout )))) # (!\z80_|alu_flags_|DFFE_inst_latch_sf~q & ((\z80_|execute_|ctl_flags_oe~2_combout ) # +// ((!\z80_|alu_|db[7]~12_combout & \z80_|execute_|ctl_sw_2u~7_combout )))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), + .datab(\z80_|alu_|db[7]~12_combout ), + .datac(\z80_|execute_|ctl_flags_oe~2_combout ), + .datad(\z80_|execute_|ctl_sw_2u~7_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[7]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[7]~16 .lut_mask = 16'h7350; +defparam \z80_|alu_control_|db[7]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N6 +cycloneive_lcell_comb \z80_|alu_control_|db[7]~17 ( +// Equation(s): +// \z80_|alu_control_|db[7]~17_combout = (!\z80_|alu_control_|db[7]~16_combout & (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & ((\z80_|reg_file_|gdfx_temp0[7]~91_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), + .datab(\z80_|alu_control_|db[7]~16_combout ), + .datac(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[7]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[7]~17 .lut_mask = 16'h2030; +defparam \z80_|alu_control_|db[7]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N12 +cycloneive_lcell_comb \z80_|alu_control_|db[7]~18 ( +// Equation(s): +// \z80_|alu_control_|db[7]~18_combout = (\z80_|alu_control_|db[7]~17_combout & (((!\z80_|execute_|ctl_sw_mask543_en~0_combout & \z80_|bus_control_|db[7]~7_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) + + .dataa(\z80_|execute_|ctl_sw_mask543_en~0_combout ), + .datab(\z80_|bus_control_|db[7]~7_combout ), + .datac(\z80_|execute_|ctl_sw_1d~7_combout ), + .datad(\z80_|alu_control_|db[7]~17_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[7]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[7]~18 .lut_mask = 16'h4F00; +defparam \z80_|alu_control_|db[7]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N26 +cycloneive_lcell_comb \z80_|alu_control_|db[7]~19 ( +// Equation(s): +// \z80_|alu_control_|db[7]~19_combout = (\z80_|alu_control_|db[7]~18_combout ) # (!\z80_|alu_control_|db[6]~11_combout ) + + .dataa(\z80_|alu_control_|db[7]~18_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|alu_control_|db[6]~11_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[7]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[7]~19 .lut_mask = 16'hAAFF; +defparam \z80_|alu_control_|db[7]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N28 +cycloneive_lcell_comb \z80_|bus_control_|db[7]~5 ( +// Equation(s): +// \z80_|bus_control_|db[7]~5_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[7]~19_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datab(\z80_|bus_control_|db[0]~4_combout ), + .datac(gnd), + .datad(\z80_|alu_control_|db[7]~19_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[7]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[7]~5 .lut_mask = 16'hCC44; +defparam \z80_|bus_control_|db[7]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N2 +cycloneive_lcell_comb \D[5]~67 ( +// Equation(s): +// \D[5]~67_combout = (!\z80_|memory_ifc_|nIORQ_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\z80_|memory_ifc_|nRD_out~2_combout & !\z80_|memory_ifc_|nWR_out~0_combout ))) + + .dataa(\z80_|memory_ifc_|nIORQ_out~0_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|memory_ifc_|nRD_out~2_combout ), + .datad(\z80_|memory_ifc_|nWR_out~0_combout ), + .cin(gnd), + .combout(\D[5]~67_combout ), + .cout()); +// synopsys translate_off +defparam \D[5]~67 .lut_mask = 16'h0040; +defparam \D[5]~67 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y21_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a7 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[7]~80_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081; +// synopsys translate_on + +// Location: M9K_X33_Y20_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a23 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[7]~80_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_first_bit_number = 7; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N10 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout ) # +// (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout & +// ((!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14 .lut_mask = 16'hCCE2; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y18_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a31 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[7]~80_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a31_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_first_bit_number = 7; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y16_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a15 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[7]~80_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N24 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15_combout = (\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ) # +// ((!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14_combout & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & +// \ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14_combout ), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15 .lut_mask = 16'hDA8A; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y29_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a15 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h3C0000000000000000000000000000000000000000000000000000000000000080000000000002000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFB91060128E2D09899B4D10A148392808351AD282E76190E029FDC286449331D89080802222C0D04D1121484041D21084C223B0A12EBE72083D81421B93CA9589A04864A853089602E536320C2A5944831907110C246020089C76EE701A4E23964C6586008731635460418000008202040C300110000FCE7E12403749F8C6AB8F69167210EF8A4B8228710884C5C47A9986E8840C02862C088C36E19CF1D315; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h03020CCE064769B15020A6030880234C64E9BEF8E98A81489083A026140D648906E5AD6C882882990A40D293FED064710CB226CDA0330D7B189B344442EC35E3763C75FA1DB107B865E5B8F7B95E77F222244C6BDC1879C0562EF779BE0009465775469089F04C623E19317B486F653C1C22CA642CD685C10EE47EDD66C8C226C7C57F084106FB3B8B1E47463C0088D11104F23C180222A0AA22A22882A202A00000000288964258156302504F5F660C054DEDCA20CC201A4074192601E376C9596CD8B4B568A4DFEF3DBF8027A3422A56A2C003E514582104BF8D6B5D80BB397FBBEC46E8B3CAEBE0100275A1092081D0C1E5716DF09CFEEC00AD800529E1A8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h873CB568FC3F09080F4400DAC600092017210911A6081DCC4979244124815884AE6302C4BE6BA8C22A084803225A0855ABBBC528B1CA2456A4951A53C1209153CFC3000F43632B49C39723270C604B184D1940F1B2A04459BEB088666843BB38C23A8D170CED981891256A2C1D9B31C0F040202103900E6765976089DB8DE16E0001022EC10015E263787F7E581EF83F062200C626EC4E19021840D9C112400C4B987A78AE1BF80005EF370C0739371E0D3E5CF1E3677332370BB98D1831B30F7D8CDC0131C444798F040DC0116E2C4336B0166109A15D1FCC7EDE31EB23862203C11245EE31E38E6DEF2188BE2068F3C716E10317783020D8EF5C256774BA0E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h1B9CE2DA363196DC20007FF5554FC631286DC716B048384C26510685218DF9E6C629E6050C619658692170C1022C2232C965C92C189020C705873084858910322166D72DC524870C422BBFFD4808A7032B088DE3000B853800736C8E9968C19A4B72C08871D2413188E4829219C38C2025920480D64856902E4D4D60B640C833C14D536A45D144B244C24A290076E58CC2E64E4A2DC4C5939C4C2DDBD1B918B231248625B2C0DD0F07A27A111CB80A48808C7C21C205029100010400228BB3BDFF7DCCEF40196C8381658D8840043B119B86A46247665810E2203000141023C366CB633B3376DC625DA8A0856C484392B779E1BA4088EDB4A6CDB9BD46DCC0B2; +// synopsys translate_on + +// Location: M9K_X33_Y23_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a15 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(gnd), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[7]~80_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_first_bit_number = 7; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y24_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a7 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[7]~80_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_first_bit_number = 7; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h000000000000000000000000FFFFFFFFC0810207C0001A176020155177486D89000000000000000000000000FFFFFFFF80000003C0000217724019F17748EDC900000000000000000000000000000001BF7EFDF9400406B17A400BF57748AD81000000000000000000000000000000013F7EFDF940041EB1724218157749A7910000000000000000000000003F7EFDF90000000140042AF97B426C157DC9B7590000000000000000000000003F7EFDF90000000140042069600246057DC95351000000000000000000000000408102053FFFFFF95FE4084175C246896009F35100000000000000000000000040810207BFFFFFFF7FE4147177C2004960291759; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h7FE8374958F827C15FF88F91E9A80DC3629A9FC172033EC170FB0E8173F792815FE826E158F805C95FF8AF8169A80DC3629A1EC17B033BC1706B3E8173FFB0C1400826E558F805C15DF8AF9169A82DD163C21BC17B133BC1716B3781723F14C1400826E958D825815DD8AF8168482DC161229BC17A133FC171AB3781723F16E9400826E95818058179582F9160480FC162229FC17ACA39C172FB3F8152CF10A1400826E958180D8179580F05614C0DC162329BC171EB398173537F8152E310D1400826E158180D81F8580FD1612C0F41631293C173BB398D63037F81D22313D1400827E958080F01F8188FCB60A40F41435083C1723B198161834F01D67300E3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'hD4FB0D2352268F0151E680016803440977EDE98148F31101BFFFFFFF4081010750FB094B52728F0151FEC0016C034C0153EDA90148F31F013FFFFFFB4081010152F3096156DA8901503ED2016C03480173FDA00148F11F01000000013F7EFEF952E3017156DA85015022C2016C034C0153FCA00148F10F01000000013F7EFEF956B3A9115052850543C2C2116C014D2153FDA12148D11F013F7EFEF900000001469F8B3150728D0143C05A016D014C81537DA00148D11E01BF7EFEF900000001528F8F2156628D0140004E016F054481513DA181C8513E0580000007FFFFFFFF528E8B2156E28C0148024E0167676C415139B041C8513E07C0810107FFFFFFFF; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N14 +cycloneive_lcell_comb \Mux0~0 ( +// Equation(s): +// \Mux0~0_combout = (\z80_|address_pins_|abus[14]~23_combout & ((\Selector3~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout )) # (!\Selector3~0_combout & +// ((\ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout ))))) # (!\z80_|address_pins_|abus[14]~23_combout & (((\Selector3~0_combout )))) + + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout ), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout ), + .datad(\Selector3~0_combout ), + .cin(gnd), + .combout(\Mux0~0_combout ), + .cout()); +// synopsys translate_off +defparam \Mux0~0 .lut_mask = 16'hDDA0; +defparam \Mux0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y32_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a7 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h7C762E21DB2481CB6BB88C68811C76C63B18ECC1BACDC6110DCC70BC20940800C71478E35468600B01A93082C63DD073AE4181844449C08D8D56B0DCC881251C202139803D3000B2E0209DB9101160989A5916381001B0446631006064DB1B996E436E644CF6C8606F124DA230E9B66E2F46BB466E2CE068661B4B05F02F7D00CB3E518948104042F84F1840401018406877D800A00000F5122597005DA4411000800020249004081008924124080114000000020BFFFFEC638C31207B6C321407D901787004001C459326210CCE00C6AF707B84440C313110B8C4D13B2C6E06C4C088B1A9B24BEB0178C4D6C18230DF72B07A28063647CC4721026D8C711864; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h881B30810845E6D18622EC9B6236A000030986A4F0644601226000A2F220D40310438334E51C28000400B18422CA60FC42C9C03F066366ECBBB010B00B004807CC0E00DAEC3000194A52B80C606262092D84A1102410000001400010002000800200080020000800200008000800400040002004000040002000020002000801000010004002001000200008000AEE708008880C86112251B45B36C0048833B319B4C2CE6660D2C0619246C4B208BC0AD00202001E104FC30911410804201E92102B400E8004C40AD6E4614466308ABC7165AA57060A3A736A188ABB300200A10BB04344008422327B1393C43396A931B8C8C87227A6141C0E2DCC76D830B082; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h101CC0024A6C32005CCB31908842211604D8B326101118B54B188CB4D502F5F02DA65C2472B824F109BC594C2401209C01A0E59830002C73B396C6015B85A163184B56183004204267600220A061A004893E1D609106BDBB553920A011AA5AE581E08228382D54C2989BC59535528176240438C9AA757917F95C7428981A26470D1C3E528444D9B00E561C40973AE1806031C464834F03D34A11233A34B34A1D1A55A50C3384B549B64C381920140D4008004020B119D5834C10064000006001169808000200040100000002F8986E37654DDFF88E20860382DC089D4C239F6E4C3C8D784218667F524CE209881213DC91099C14744901620044C802DA414966; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h84724A241226DB4809C9A1100DE6A63984D651A2624A09420496DDC12CC10964B6E370363701B41848117683379C8422106D001BB41FB8248067301E1002C636A276585D5273AC87206840415DA74B4E9D213CAE3234B308E19608AA38250844883838649E1442A0D983F4A9094A5AD4A52D56C5D80CAC58D9645944A230091549F30426B100842A12B25160D6D991E6C8C81AFB4C644004C2140A342020D84C9001624489A10045D16C944B02763FF55405E400BADFE5BFFFFFF00000000011042250089108884888410924041204444209102084241104204108824114455292225124929249248894408541300A6DB00791E5B12FEF24037181F1901B007B; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N16 +cycloneive_lcell_comb \Mux0~1 ( +// Equation(s): +// \Mux0~1_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\Mux0~0_combout )))) # (!\z80_|address_pins_|abus[14]~23_combout & ((\Mux0~0_combout & (\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout )) # (!\Mux0~0_combout & +// ((\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ))))) + + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ), + .datac(\Mux0~0_combout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ), + .cin(gnd), + .combout(\Mux0~1_combout ), + .cout()); +// synopsys translate_off +defparam \Mux0~1 .lut_mask = 16'hE5E0; +defparam \Mux0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N22 +cycloneive_lcell_comb \D[7]~89 ( +// Equation(s): +// \D[7]~89_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [15] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\Mux0~1_combout ))))) # +// (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15_combout )) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15_combout ), + .datac(\z80_|address_pins_|DFFE_apin_latch [15]), + .datad(\Mux0~1_combout ), + .cin(gnd), + .combout(\D[7]~89_combout ), + .cout()); +// synopsys translate_off +defparam \D[7]~89 .lut_mask = 16'hCEC4; +defparam \D[7]~89 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N30 +cycloneive_lcell_comb \D[7]~72 ( +// Equation(s): +// \D[7]~72_combout = (\D[5]~67_combout & (\D[7]~89_combout & ((\z80_|data_pins_|dout [7]) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout )))) # (!\D[5]~67_combout & ((\z80_|data_pins_|dout [7]) # ((!\z80_|pin_control_|bus_db_pin_oe~15_combout )))) + + .dataa(\D[5]~67_combout ), + .datab(\z80_|data_pins_|dout [7]), + .datac(\D[7]~89_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .cin(gnd), + .combout(\D[7]~72_combout ), + .cout()); +// synopsys translate_off +defparam \D[7]~72 .lut_mask = 16'hC4F5; +defparam \D[7]~72 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N12 +cycloneive_lcell_comb \D[0]~84 ( +// Equation(s): +// \D[0]~84_combout = (\z80_|pin_control_|bus_db_pin_oe~15_combout ) # ((\z80_|memory_ifc_|nRD_out~2_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|memory_ifc_|nWR_out~0_combout ))) + + .dataa(\z80_|memory_ifc_|nRD_out~2_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .datad(\z80_|memory_ifc_|nWR_out~0_combout ), + .cin(gnd), + .combout(\D[0]~84_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~84 .lut_mask = 16'hF0F8; +defparam \D[0]~84 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N6 +cycloneive_lcell_comb \D[7]~80 ( +// Equation(s): +// \D[7]~80_combout = (\D[7]~72_combout ) # (!\D[0]~84_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\D[7]~72_combout ), + .datad(\D[0]~84_combout ), + .cin(gnd), + .combout(\D[7]~80_combout ), + .cout()); +// synopsys translate_off +defparam \D[7]~80 .lut_mask = 16'hF0FF; +defparam \D[7]~80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N12 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [7] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[7]~7_combout ) # ((\D[7]~80_combout & \z80_|pin_control_|bus_db_pin_re~combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & +// (((\D[7]~80_combout & \z80_|pin_control_|bus_db_pin_re~combout )))) + + .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datab(\z80_|bus_control_|db[7]~7_combout ), + .datac(\D[7]~80_combout ), + .datad(\z80_|pin_control_|bus_db_pin_re~combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [7]), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] .lut_mask = 16'hF888; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y13_N13 +dffeas \z80_|data_pins_|dout[7] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [7]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|data_pins_|dout [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|data_pins_|dout[7] .is_wysiwyg = "true"; +defparam \z80_|data_pins_|dout[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N20 +cycloneive_lcell_comb \z80_|bus_control_|db[7]~7 ( +// Equation(s): +// \z80_|bus_control_|db[7]~7_combout = ((\z80_|bus_control_|db[7]~5_combout & ((\z80_|data_pins_|dout [7]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) + + .dataa(\z80_|bus_control_|db[0]~6_combout ), + .datab(\z80_|bus_control_|db[7]~5_combout ), + .datac(\z80_|data_pins_|dout [7]), + .datad(\z80_|execute_|ctl_bus_db_oe~combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[7]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[7]~7 .lut_mask = 16'hD5DD; +defparam \z80_|bus_control_|db[7]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y13_N21 +dffeas \z80_|ir_|opcode[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|bus_control_|db[7]~7_combout ), .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), @@ -53174,65 +43916,9090 @@ dffeas \z80_|ir_|opcode[3] ( .ena(\z80_|execute_|ctl_ir_we~13_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|ir_|opcode [3]), + .q(\z80_|ir_|opcode [7]), .prn(vcc)); // synopsys translate_off -defparam \z80_|ir_|opcode[3] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[3] .power_up = "low"; +defparam \z80_|ir_|opcode[7] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X40_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~4 ( +// Location: LCCOMB_X29_Y13_N30 +cycloneive_lcell_comb \z80_|pla_decode_|Equal6~0 ( // Equation(s): -// \z80_|execute_|ctl_mWrite~4_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal52~0_combout ))) +// \z80_|pla_decode_|Equal6~0_combout = (!\z80_|decode_state_|DFFE_instED~q & (!\z80_|decode_state_|DFFE_instCB~q & (!\z80_|ir_|opcode [7] & !\z80_|ir_|opcode [6]))) - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal3~1_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal52~0_combout ), + .dataa(\z80_|decode_state_|DFFE_instED~q ), + .datab(\z80_|decode_state_|DFFE_instCB~q ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|ir_|opcode [6]), .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~4_combout ), + .combout(\z80_|pla_decode_|Equal6~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~4 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_mWrite~4 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal6~0 .lut_mask = 16'h0001; +defparam \z80_|pla_decode_|Equal6~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y17_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~2 ( +// Location: LCCOMB_X21_Y16_N4 +cycloneive_lcell_comb \z80_|pla_decode_|Equal12~0 ( // Equation(s): -// \z80_|execute_|ctl_apin_mux~2_combout = ((\z80_|execute_|ctl_mWrite~4_combout & \z80_|execute_|ctl_apin_mux~1_combout )) # (!\z80_|execute_|ctl_inc_dec~6_combout ) +// \z80_|pla_decode_|Equal12~0_combout = (!\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [0]))) - .dataa(\z80_|execute_|ctl_mWrite~4_combout ), - .datab(\z80_|execute_|ctl_apin_mux~1_combout ), - .datac(\z80_|execute_|ctl_inc_dec~6_combout ), + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal12~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal12~0 .lut_mask = 16'h0040; +defparam \z80_|pla_decode_|Equal12~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~16 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~16_combout = (\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal12~0_combout & \z80_|ir_|opcode [3]))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|pla_decode_|Equal12~0_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~16 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_mRead~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|fMRead~24 ( +// Equation(s): +// \z80_|execute_|fMRead~24_combout = (\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_mRead~16_combout ) # ((\z80_|execute_|ctl_mRead~15_combout )))) # (!\z80_|execute_|ctl_ir_we~4_combout & (\z80_|execute_|ctl_alu_oe~0_combout & +// ((\z80_|execute_|ctl_mRead~16_combout ) # (\z80_|execute_|ctl_mRead~15_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|execute_|ctl_mRead~16_combout ), + .datac(\z80_|execute_|ctl_mRead~15_combout ), + .datad(\z80_|execute_|ctl_alu_oe~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~24 .lut_mask = 16'hFCA8; +defparam \z80_|execute_|fMRead~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N12 +cycloneive_lcell_comb \z80_|execute_|fMRead~25 ( +// Equation(s): +// \z80_|execute_|fMRead~25_combout = ((\z80_|execute_|fMRead~24_combout ) # ((\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|pc_inc_hold~26_combout ))) # (!\z80_|execute_|ctl_bus_db_oe~0_combout ) + + .dataa(\z80_|execute_|ctl_bus_db_oe~0_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|fMRead~24_combout ), + .datad(\z80_|execute_|pc_inc_hold~26_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~25 .lut_mask = 16'hF5FD; +defparam \z80_|execute_|fMRead~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~21 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~21_combout = (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|decode_state_|in_halt~q & (!\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal77~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|decode_state_|in_halt~q ), + .datac(\z80_|decode_state_|use_ixiy~combout ), + .datad(\z80_|pla_decode_|Equal77~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~21 .lut_mask = 16'h0200; +defparam \z80_|execute_|ctl_mRead~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|fMRead~16 ( +// Equation(s): +// \z80_|execute_|fMRead~16_combout = (\z80_|execute_|ctl_ir_we~11_combout ) # ((\z80_|execute_|ctl_ir_we~12_combout ) # ((\z80_|execute_|ctl_mRead~13_combout ) # (\z80_|execute_|ctl_mRead~21_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~11_combout ), + .datab(\z80_|execute_|ctl_ir_we~12_combout ), + .datac(\z80_|execute_|ctl_mRead~13_combout ), + .datad(\z80_|execute_|ctl_mRead~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~16 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|fMRead~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|fMRead~14 ( +// Equation(s): +// \z80_|execute_|fMRead~14_combout = (\z80_|execute_|ctl_ir_we~14_combout ) # ((\z80_|execute_|ctl_ir_we~8_combout ) # ((!\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal49~0_combout ))) + + .dataa(\z80_|decode_state_|use_ixiy~combout ), + .datab(\z80_|pla_decode_|Equal49~0_combout ), + .datac(\z80_|execute_|ctl_ir_we~14_combout ), + .datad(\z80_|execute_|ctl_ir_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~14 .lut_mask = 16'hFFF4; +defparam \z80_|execute_|fMRead~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y14_N2 +cycloneive_lcell_comb \z80_|execute_|fMRead~15 ( +// Equation(s): +// \z80_|execute_|fMRead~15_combout = (!\z80_|execute_|fMWrite~3_combout & ((\z80_|execute_|ctl_ir_we~11_combout ) # ((\z80_|execute_|ctl_mRead~4_combout ) # (\z80_|execute_|fMRead~14_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~11_combout ), + .datab(\z80_|execute_|ctl_mRead~4_combout ), + .datac(\z80_|execute_|fMRead~14_combout ), + .datad(\z80_|execute_|fMWrite~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~15 .lut_mask = 16'h00FE; +defparam \z80_|execute_|fMRead~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|fMRead~12 ( +// Equation(s): +// \z80_|execute_|fMRead~12_combout = (!\z80_|pla_decode_|Equal13~2_combout & (!\z80_|execute_|ctl_mRead~2_combout & (!\z80_|pla_decode_|Equal6~1_combout & \z80_|execute_|ctl_bus_db_oe~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(\z80_|execute_|ctl_mRead~2_combout ), + .datac(\z80_|pla_decode_|Equal6~1_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~12 .lut_mask = 16'h0100; +defparam \z80_|execute_|fMRead~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y14_N18 +cycloneive_lcell_comb \z80_|execute_|fMRead~11 ( +// Equation(s): +// \z80_|execute_|fMRead~11_combout = (((\z80_|execute_|ctl_mRead~11_combout ) # (\z80_|execute_|ctl_mRead~21_combout )) # (!\z80_|execute_|pc_inc_hold~6_combout )) # (!\z80_|execute_|nextM~3_combout ) + + .dataa(\z80_|execute_|nextM~3_combout ), + .datab(\z80_|execute_|pc_inc_hold~6_combout ), + .datac(\z80_|execute_|ctl_mRead~11_combout ), + .datad(\z80_|execute_|ctl_mRead~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~11 .lut_mask = 16'hFFF7; +defparam \z80_|execute_|fMRead~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|fMRead~13 ( +// Equation(s): +// \z80_|execute_|fMRead~13_combout = (\z80_|execute_|ctl_state_alu~2_combout & (((\z80_|execute_|ctl_ir_we~14_combout ) # (\z80_|execute_|fMRead~11_combout )) # (!\z80_|execute_|fMRead~12_combout ))) + + .dataa(\z80_|execute_|fMRead~12_combout ), + .datab(\z80_|execute_|ctl_ir_we~14_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|fMRead~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~13 .lut_mask = 16'hF0D0; +defparam \z80_|execute_|fMRead~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y14_N6 +cycloneive_lcell_comb \z80_|execute_|fMRead~17 ( +// Equation(s): +// \z80_|execute_|fMRead~17_combout = (\z80_|execute_|fMRead~15_combout ) # ((\z80_|execute_|fMRead~13_combout ) # ((\z80_|execute_|fMRead~16_combout & \z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|execute_|fMRead~16_combout ), + .datab(\z80_|execute_|fMRead~15_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|fMRead~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~17 .lut_mask = 16'hFFEC; +defparam \z80_|execute_|fMRead~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|fMRead~22 ( +// Equation(s): +// \z80_|execute_|fMRead~22_combout = (\z80_|execute_|fMRead~17_combout ) # (((!\z80_|execute_|fMRead~21_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~40_combout )) # (!\z80_|execute_|ctl_sw_4d~2_combout )) + + .dataa(\z80_|execute_|fMRead~17_combout ), + .datab(\z80_|execute_|ctl_sw_4d~2_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~40_combout ), + .datad(\z80_|execute_|fMRead~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~22 .lut_mask = 16'hBFFF; +defparam \z80_|execute_|fMRead~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|fMRead~27 ( +// Equation(s): +// \z80_|execute_|fMRead~27_combout = ((\z80_|sequencer_|DFFE_M2_ff~q & (!\z80_|execute_|ixy_d~4_combout & \z80_|execute_|ctl_mRead~12_combout ))) # (!\z80_|execute_|fMRead~26_combout ) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|execute_|fMRead~26_combout ), + .datac(\z80_|execute_|ixy_d~4_combout ), + .datad(\z80_|execute_|ctl_mRead~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~27 .lut_mask = 16'h3B33; +defparam \z80_|execute_|fMRead~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|fMRead~37 ( +// Equation(s): +// \z80_|execute_|fMRead~37_combout = (\z80_|sequencer_|DFFE_M4_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|execute_|ctl_mRead~13_combout ) # (\z80_|execute_|ctl_state_alu~6_combout )))) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|execute_|ctl_mRead~13_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|execute_|ctl_state_alu~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~37 .lut_mask = 16'h0A08; +defparam \z80_|execute_|fMRead~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|fMRead~31 ( +// Equation(s): +// \z80_|execute_|fMRead~31_combout = (\z80_|pla_decode_|Equal33~3_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ixy_d~6_combout )))) # (!\z80_|pla_decode_|Equal33~3_combout & (\z80_|pla_decode_|Equal6~1_combout & +// ((\z80_|execute_|ixy_d~5_combout ) # (\z80_|execute_|ixy_d~6_combout )))) + + .dataa(\z80_|pla_decode_|Equal33~3_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|pla_decode_|Equal6~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~31 .lut_mask = 16'hFCA8; +defparam \z80_|execute_|fMRead~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N14 +cycloneive_lcell_comb \z80_|execute_|fMRead~29 ( +// Equation(s): +// \z80_|execute_|fMRead~29_combout = (\z80_|execute_|ctl_ir_we~5_combout & (\z80_|pla_decode_|Equal33~0_combout & ((\z80_|ir_|opcode [7]) # (\z80_|ir_|opcode [6])))) + + .dataa(\z80_|execute_|ctl_ir_we~5_combout ), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|execute_|fMRead~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~29 .lut_mask = 16'hA080; +defparam \z80_|execute_|fMRead~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|fMRead~30 ( +// Equation(s): +// \z80_|execute_|fMRead~30_combout = (\z80_|execute_|ctl_alu_shift_oe~14_combout & ((\z80_|execute_|ctl_ir_we~9_combout ) # ((\z80_|execute_|fMRead~29_combout ) # (\z80_|execute_|ctl_ir_we~10_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~9_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datac(\z80_|execute_|fMRead~29_combout ), + .datad(\z80_|execute_|ctl_ir_we~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~30 .lut_mask = 16'hCCC8; +defparam \z80_|execute_|fMRead~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|fMRead~28 ( +// Equation(s): +// \z80_|execute_|fMRead~28_combout = ((\z80_|execute_|ixy_d~6_combout & ((\z80_|pla_decode_|Equal41~2_combout ) # (\z80_|pla_decode_|Equal9~1_combout )))) # (!\z80_|execute_|nextM~4_combout ) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|execute_|nextM~4_combout ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~28 .lut_mask = 16'hBBB3; +defparam \z80_|execute_|fMRead~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|fMRead~32 ( +// Equation(s): +// \z80_|execute_|fMRead~32_combout = ((\z80_|execute_|fMRead~31_combout ) # ((\z80_|execute_|fMRead~30_combout ) # (\z80_|execute_|fMRead~28_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ), + .datab(\z80_|execute_|fMRead~31_combout ), + .datac(\z80_|execute_|fMRead~30_combout ), + .datad(\z80_|execute_|fMRead~28_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~32 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|fMRead~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|fMRead~33 ( +// Equation(s): +// \z80_|execute_|fMRead~33_combout = (\z80_|execute_|fMRead~27_combout ) # (((\z80_|execute_|fMRead~37_combout ) # (\z80_|execute_|fMRead~32_combout )) # (!\z80_|execute_|fMRead~6_combout )) + + .dataa(\z80_|execute_|fMRead~27_combout ), + .datab(\z80_|execute_|fMRead~6_combout ), + .datac(\z80_|execute_|fMRead~37_combout ), + .datad(\z80_|execute_|fMRead~32_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~33 .lut_mask = 16'hFFFB; +defparam \z80_|execute_|fMRead~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|fMRead~23 ( +// Equation(s): +// \z80_|execute_|fMRead~23_combout = (\z80_|execute_|ctl_state_alu~3_combout & (((\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|fMRead~5_combout )) # (!\z80_|execute_|fMRead~4_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~3_combout ), + .datab(\z80_|execute_|fMRead~4_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|fMRead~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~23 .lut_mask = 16'hA2AA; +defparam \z80_|execute_|fMRead~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N26 +cycloneive_lcell_comb \z80_|execute_|fMRead~34 ( +// Equation(s): +// \z80_|execute_|fMRead~34_combout = (\z80_|execute_|fMRead~25_combout ) # ((\z80_|execute_|fMRead~22_combout ) # ((\z80_|execute_|fMRead~33_combout ) # (\z80_|execute_|fMRead~23_combout ))) + + .dataa(\z80_|execute_|fMRead~25_combout ), + .datab(\z80_|execute_|fMRead~22_combout ), + .datac(\z80_|execute_|fMRead~33_combout ), + .datad(\z80_|execute_|fMRead~23_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~34 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|fMRead~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y14_N14 +cycloneive_lcell_comb \z80_|execute_|fMRead~35 ( +// Equation(s): +// \z80_|execute_|fMRead~35_combout = ((\z80_|execute_|ctl_ir_we~12_combout ) # ((\z80_|execute_|ctl_mRead~21_combout ) # (!\z80_|execute_|fMRead~7_combout ))) # (!\z80_|execute_|fMWrite~1_combout ) + + .dataa(\z80_|execute_|fMWrite~1_combout ), + .datab(\z80_|execute_|ctl_ir_we~12_combout ), + .datac(\z80_|execute_|fMRead~7_combout ), + .datad(\z80_|execute_|ctl_mRead~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~35 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|fMRead~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~19 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~19_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|pla_decode_|Equal33~3_combout ) # (!\z80_|execute_|ctl_al_we~5_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|pla_decode_|Equal33~3_combout ), + .datad(\z80_|execute_|ctl_al_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~19 .lut_mask = 16'h4044; +defparam \z80_|execute_|ctl_reg_sel_pc~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N16 +cycloneive_lcell_comb \z80_|execute_|fMRead~36 ( +// Equation(s): +// \z80_|execute_|fMRead~36_combout = (\z80_|execute_|fMRead~34_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~19_combout ) # ((!\z80_|execute_|fMRead~2_combout & \z80_|execute_|fMRead~35_combout ))) + + .dataa(\z80_|execute_|fMRead~34_combout ), + .datab(\z80_|execute_|fMRead~2_combout ), + .datac(\z80_|execute_|fMRead~35_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~36 .lut_mask = 16'hFFBA; +defparam \z80_|execute_|fMRead~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N22 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_re ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_re~combout = (\z80_|pin_control_|bus_db_pin_re~2_combout ) # ((\z80_|sequencer_|DFFE_T2_ff~q & \z80_|execute_|fMRead~36_combout )) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(gnd), + .datac(\z80_|execute_|fMRead~36_combout ), + .datad(\z80_|pin_control_|bus_db_pin_re~2_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_re~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_re .lut_mask = 16'hFFA0; +defparam \z80_|pin_control_|bus_db_pin_re .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~118 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][4]~118_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [6]))) # (!\ula_|ps2_keyboard_|shiftreg [2] & +// (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [6]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][4]~118_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][4]~118 .lut_mask = 16'h1008; +defparam \ula_|zx_keyboard_|keys[2][4]~118 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~119 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][4]~119_combout = (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[2][4]~118_combout & \ula_|zx_keyboard_|keys[5][1]~34_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|zx_keyboard_|keys[2][4]~118_combout ), + .datad(\ula_|zx_keyboard_|keys[5][1]~34_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][4]~119_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][4]~119 .lut_mask = 16'h4000; +defparam \ula_|zx_keyboard_|keys[2][4]~119 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~120 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][4]~120_combout = (\ula_|zx_keyboard_|keys[2][4]~119_combout & ((!\ula_|zx_keyboard_|keys[2][4]~94_combout ))) # (!\ula_|zx_keyboard_|keys[2][4]~119_combout & (\ula_|zx_keyboard_|keys[2][4]~q )) + + .dataa(\ula_|zx_keyboard_|keys[2][4]~119_combout ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[2][4]~q ), + .datad(\ula_|zx_keyboard_|keys[2][4]~94_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][4]~120_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][4]~120 .lut_mask = 16'h50FA; +defparam \ula_|zx_keyboard_|keys[2][4]~120 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y9_N1 +dffeas \ula_|zx_keyboard_|keys[2][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[2][4]~120_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[2][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[2][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~129 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][4]~129_combout = (!\ula_|ps2_keyboard_|shiftreg [7] & (\ula_|ps2_keyboard_|scan_code_ready~q & (!\ula_|zx_keyboard_|Equal0~1_combout & \ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [7]), + .datab(\ula_|ps2_keyboard_|scan_code_ready~q ), + .datac(\ula_|zx_keyboard_|Equal0~1_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][4]~129_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][4]~129 .lut_mask = 16'h0400; +defparam \ula_|zx_keyboard_|keys[3][4]~129 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~116 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][4]~116_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [0]))) # (!\ula_|ps2_keyboard_|shiftreg [6] & +// (!\ula_|zx_keyboard_|extended~q & (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [0]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|zx_keyboard_|extended~q ), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][4]~116_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][4]~116 .lut_mask = 16'h0810; +defparam \ula_|zx_keyboard_|keys[3][4]~116 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~134 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][4]~134_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [1] & \ula_|zx_keyboard_|keys[3][4]~116_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|zx_keyboard_|keys[3][4]~116_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][4]~134_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][4]~134 .lut_mask = 16'h4000; +defparam \ula_|zx_keyboard_|keys[3][4]~134 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~117 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][4]~117_combout = (\ula_|zx_keyboard_|keys[3][4]~129_combout & ((\ula_|zx_keyboard_|keys[3][4]~134_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][4]~134_combout & ((\ula_|zx_keyboard_|keys[3][4]~q +// ))))) # (!\ula_|zx_keyboard_|keys[3][4]~129_combout & (((\ula_|zx_keyboard_|keys[3][4]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[3][4]~129_combout ), + .datac(\ula_|zx_keyboard_|keys[3][4]~q ), + .datad(\ula_|zx_keyboard_|keys[3][4]~134_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][4]~117_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][4]~117 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[3][4]~117 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y8_N19 +dffeas \ula_|zx_keyboard_|keys[3][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[3][4]~117_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[3][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[3][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N6 +cycloneive_lcell_comb \D[4]~60 ( +// Equation(s): +// \D[4]~60_combout = (\z80_|address_pins_|abus[11]~19_combout & ((\z80_|address_pins_|abus[10]~24_combout ) # ((!\ula_|zx_keyboard_|keys[2][4]~q )))) # (!\z80_|address_pins_|abus[11]~19_combout & (!\ula_|zx_keyboard_|keys[3][4]~q & +// ((\z80_|address_pins_|abus[10]~24_combout ) # (!\ula_|zx_keyboard_|keys[2][4]~q )))) + + .dataa(\z80_|address_pins_|abus[11]~19_combout ), + .datab(\z80_|address_pins_|abus[10]~24_combout ), + .datac(\ula_|zx_keyboard_|keys[2][4]~q ), + .datad(\ula_|zx_keyboard_|keys[3][4]~q ), + .cin(gnd), + .combout(\D[4]~60_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~60 .lut_mask = 16'h8ACF; +defparam \D[4]~60 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~2 ( +// Equation(s): +// \ula_|zx_keyboard_|Equal0~2_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [3])) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|Equal0~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|Equal0~2 .lut_mask = 16'h000C; +defparam \ula_|zx_keyboard_|Equal0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][4]~121 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][4]~121_combout = (\ula_|zx_keyboard_|keys[1][4]~23_combout & ((\ula_|zx_keyboard_|Equal0~2_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|Equal0~2_combout & ((\ula_|zx_keyboard_|keys[1][4]~q ))))) # +// (!\ula_|zx_keyboard_|keys[1][4]~23_combout & (((\ula_|zx_keyboard_|keys[1][4]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[1][4]~23_combout ), + .datac(\ula_|zx_keyboard_|keys[1][4]~q ), + .datad(\ula_|zx_keyboard_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][4]~121_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][4]~121 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[1][4]~121 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y9_N9 +dffeas \ula_|zx_keyboard_|keys[1][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[1][4]~121_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[1][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[1][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~115 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][4]~115_combout = (\ula_|zx_keyboard_|keys[3][1]~27_combout & ((\ula_|zx_keyboard_|keys[0][4]~96_combout & ((!\ula_|zx_keyboard_|keys[0][4]~109_combout ))) # (!\ula_|zx_keyboard_|keys[0][4]~96_combout & +// (\ula_|zx_keyboard_|keys[0][4]~q )))) # (!\ula_|zx_keyboard_|keys[3][1]~27_combout & (((\ula_|zx_keyboard_|keys[0][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[3][1]~27_combout ), + .datab(\ula_|zx_keyboard_|keys[0][4]~96_combout ), + .datac(\ula_|zx_keyboard_|keys[0][4]~q ), + .datad(\ula_|zx_keyboard_|keys[0][4]~109_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][4]~115_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][4]~115 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[0][4]~115 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y9_N31 +dffeas \ula_|zx_keyboard_|keys[0][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[0][4]~115_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[0][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[0][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~4 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row~4_combout = ((\z80_|address_pins_|DFFE_apin_latch [8]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) # (!\ula_|zx_keyboard_|keys[0][4]~q ) + + .dataa(\ula_|zx_keyboard_|keys[0][4]~q ), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [8]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row~4_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row~4 .lut_mask = 16'hFF5F; +defparam \ula_|zx_keyboard_|key_row~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N22 +cycloneive_lcell_comb \D[4]~61 ( +// Equation(s): +// \D[4]~61_combout = (\D[4]~60_combout & (\ula_|zx_keyboard_|key_row~4_combout & ((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][4]~q )))) + + .dataa(\D[4]~60_combout ), + .datab(\z80_|address_pins_|abus[9]~17_combout ), + .datac(\ula_|zx_keyboard_|keys[1][4]~q ), + .datad(\ula_|zx_keyboard_|key_row~4_combout ), + .cin(gnd), + .combout(\D[4]~61_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~61 .lut_mask = 16'h8A00; +defparam \D[4]~61 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~124 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][4]~124_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|extended~q & !\ula_|ps2_keyboard_|shiftreg [2])) # (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|zx_keyboard_|extended~q & \ula_|ps2_keyboard_|shiftreg +// [2])) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|zx_keyboard_|extended~q ), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][4]~124_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][4]~124 .lut_mask = 16'h03C0; +defparam \ula_|zx_keyboard_|keys[4][4]~124 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~125 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][4]~125_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|zx_keyboard_|keys[4][4]~124_combout & (\ula_|zx_keyboard_|Equal0~2_combout & \ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|zx_keyboard_|keys[4][4]~124_combout ), + .datac(\ula_|zx_keyboard_|Equal0~2_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][4]~125_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][4]~125 .lut_mask = 16'h8000; +defparam \ula_|zx_keyboard_|keys[4][4]~125 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~126 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][4]~126_combout = (\ula_|zx_keyboard_|keys[0][0]~13_combout & ((\ula_|zx_keyboard_|keys[4][4]~125_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[4][4]~125_combout & ((\ula_|zx_keyboard_|keys[4][4]~q +// ))))) # (!\ula_|zx_keyboard_|keys[0][0]~13_combout & (((\ula_|zx_keyboard_|keys[4][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[0][0]~13_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[4][4]~q ), + .datad(\ula_|zx_keyboard_|keys[4][4]~125_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][4]~126_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][4]~126 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[4][4]~126 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y8_N7 +dffeas \ula_|zx_keyboard_|keys[4][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[4][4]~126_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[4][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[4][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~122 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][4]~122_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [2]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][4]~122_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][4]~122 .lut_mask = 16'h2000; +defparam \ula_|zx_keyboard_|keys[5][4]~122 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~123 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][4]~123_combout = (\ula_|zx_keyboard_|keys[6][4]~46_combout & ((\ula_|zx_keyboard_|keys[5][4]~122_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[5][4]~122_combout & (\ula_|zx_keyboard_|keys[5][4]~q +// )))) # (!\ula_|zx_keyboard_|keys[6][4]~46_combout & (((\ula_|zx_keyboard_|keys[5][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[6][4]~46_combout ), + .datab(\ula_|zx_keyboard_|keys[5][4]~122_combout ), + .datac(\ula_|zx_keyboard_|keys[5][4]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][4]~123_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][4]~123 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[5][4]~123 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y8_N1 +dffeas \ula_|zx_keyboard_|keys[5][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[5][4]~123_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[5][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[5][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N8 +cycloneive_lcell_comb \D[4]~62 ( +// Equation(s): +// \D[4]~62_combout = (\ula_|zx_keyboard_|keys[4][4]~q & (\z80_|address_pins_|abus[12]~21_combout & ((\z80_|address_pins_|abus[13]~20_combout ) # (!\ula_|zx_keyboard_|keys[5][4]~q )))) # (!\ula_|zx_keyboard_|keys[4][4]~q & +// ((\z80_|address_pins_|abus[13]~20_combout ) # ((!\ula_|zx_keyboard_|keys[5][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[4][4]~q ), + .datab(\z80_|address_pins_|abus[13]~20_combout ), + .datac(\z80_|address_pins_|abus[12]~21_combout ), + .datad(\ula_|zx_keyboard_|keys[5][4]~q ), + .cin(gnd), + .combout(\D[4]~62_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~62 .lut_mask = 16'hC4F5; +defparam \D[4]~62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~49 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][4]~49_combout = (\ula_|zx_keyboard_|keys[7][1]~21_combout & (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|zx_keyboard_|Equal0~2_combout & !\ula_|ps2_keyboard_|shiftreg [6]))) + + .dataa(\ula_|zx_keyboard_|keys[7][1]~21_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\ula_|zx_keyboard_|Equal0~2_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][4]~49_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][4]~49 .lut_mask = 16'h0080; +defparam \ula_|zx_keyboard_|keys[7][4]~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~3 ( +// Equation(s): +// \ula_|zx_keyboard_|shifted~3_combout = (\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [2]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|shifted~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|shifted~3 .lut_mask = 16'h00F0; +defparam \ula_|zx_keyboard_|shifted~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~127 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][4]~127_combout = (\ula_|zx_keyboard_|keys[7][4]~49_combout & ((\ula_|zx_keyboard_|shifted~3_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|shifted~3_combout & ((\ula_|zx_keyboard_|keys[7][4]~q ))))) # +// (!\ula_|zx_keyboard_|keys[7][4]~49_combout & (((\ula_|zx_keyboard_|keys[7][4]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[7][4]~49_combout ), + .datac(\ula_|zx_keyboard_|keys[7][4]~q ), + .datad(\ula_|zx_keyboard_|shifted~3_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][4]~127_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][4]~127 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[7][4]~127 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y7_N23 +dffeas \ula_|zx_keyboard_|keys[7][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[7][4]~127_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[7][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[7][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~128 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][4]~128_combout = (\ula_|zx_keyboard_|keys[6][4]~46_combout & ((\ula_|zx_keyboard_|keys[6][4]~18_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[6][4]~18_combout & ((\ula_|zx_keyboard_|keys[6][4]~q +// ))))) # (!\ula_|zx_keyboard_|keys[6][4]~46_combout & (((\ula_|zx_keyboard_|keys[6][4]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[6][4]~46_combout ), + .datac(\ula_|zx_keyboard_|keys[6][4]~q ), + .datad(\ula_|zx_keyboard_|keys[6][4]~18_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][4]~128_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][4]~128 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[6][4]~128 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y7_N9 +dffeas \ula_|zx_keyboard_|keys[6][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[6][4]~128_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[6][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[6][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N28 +cycloneive_lcell_comb \D[4]~63 ( +// Equation(s): +// \D[4]~63_combout = (\ula_|zx_keyboard_|keys[7][4]~q & (\z80_|address_pins_|abus[15]~22_combout & ((\z80_|address_pins_|abus[14]~23_combout ) # (!\ula_|zx_keyboard_|keys[6][4]~q )))) # (!\ula_|zx_keyboard_|keys[7][4]~q & +// (((\z80_|address_pins_|abus[14]~23_combout ) # (!\ula_|zx_keyboard_|keys[6][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[7][4]~q ), + .datab(\z80_|address_pins_|abus[15]~22_combout ), + .datac(\ula_|zx_keyboard_|keys[6][4]~q ), + .datad(\z80_|address_pins_|abus[14]~23_combout ), + .cin(gnd), + .combout(\D[4]~63_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~63 .lut_mask = 16'hDD0D; +defparam \D[4]~63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N6 +cycloneive_lcell_comb \D[4]~64 ( +// Equation(s): +// \D[4]~64_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[4]~61_combout & (\D[4]~62_combout & \D[4]~63_combout ))) + + .dataa(\D[4]~61_combout ), + .datab(\D[4]~62_combout ), + .datac(\z80_|address_pins_|abus[0]~16_combout ), + .datad(\D[4]~63_combout ), + .cin(gnd), + .combout(\D[4]~64_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~64 .lut_mask = 16'hF8F0; +defparam \D[4]~64 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y5_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a28 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[4]~76_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a28_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_first_bit_number = 4; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y6_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a20 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[4]~76_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_first_bit_number = 4; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y11_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a12 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[4]~76_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y9_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a4 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[4]~76_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N4 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ) # +// ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout & +// !\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8 .lut_mask = 16'hAAD8; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N14 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout = (\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ) # +// ((!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout & (((\ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout & +// \ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout ), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9 .lut_mask = 16'hACF0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y3_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a12 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'hA50276000854A0103840403E540424244404783E18807A08A47C54484448544A807E7E10005270182040407E4A1252124208084008404208420A4A42424A125A024428106448524A624A4A24425242522060108010543C00044A105424005E0031ED1E0529E507AE2F6FF1CD51D4C772A648E65F6532C28022061303F06C36CDBD319B55CB8E626C20E46C93C1463A0B1CE594F0ED3B62330C104DECE46CA6CD966B1386612C7B43980349408F36FB64C14342DAE26CE4D8D5E791388729D743B09A27AB81D71A14AB3D24E385B602248476D00249239514B58D3098504ACD119B99E9021B650A69494C22600667473128DA5010D2195982823226DED0ADFCB8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h5861917919344A4685CC0990862A11324792E761B6D41C0FCC0838C1C27211A2453FDC2219C225E421B320085A8FBFD0C42135B16448DFC226E09B3438A740C352979565817114DE46462844A57F7958873FC4B255C8AE549BDD1A87415D5018F88D5002628FFD13203066C850F10649F21319109208387641120B362124803F0678522BA2812C1454A502ED1A59CBD76A034756F5765DF7555F57575F7F57FFFF7FFF7D5712524D4A30723514B2B3064A84B4742D48415281863DDFAA9D9B7E7BB16DDB96B7845371C30B55DB96C8F6EB4B453242FF6A4DF84A76B5AEDC88A68DC6A06905054C8C36E4199E74638E6532965218A965909BA456000451343351; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'hE2975A2686A7AE0288F140141B698E2A82A835F478453A1D722CFCED12859FD735188757AC5A42DEB501FE010586249AC1EA60D08F74CFA5086EC78FC9190C056059E332C311521E6522901852D484B423A98816C9B26A08C92368E9FF05524502288A804612A2A0A102A418CBDFBA554499541660F8124640110101263142892A086B442661015380041594608092D9CB919250100A37DDA3919A1427F660963C251301FB2CA45562245308885131119115C652B2493252340201101942D26000CC60799124A8520C08050122171281808058018C38A645D07931896B39ED259A22242CB58413089465B246231330D806105010035100B08761A08506094160; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h1228D91C352915424000000AA0088F63153A8AD81B945C8789F01C86548D12CEAB6AA38578BD55CEC9AA28082C285B8C0201104838AD502AC160C13C70620B818249144AB52CED94200A0202A885100E0D938A30A34512C0CEC98F08A98900F2093E11673256B3169C12284980E92A034141E0782507800F8100009C403C07867000000030082004A17800828F090A0C318CE120012172286317922341A2A12840B6C18040682080125C75401AEC44E8C01A8D40D1412B25A09F7600B0C6FEC65BFE5CE861A20F71E8032916A78F29CC546518461522E4E14998DD54BC0E40B64B710C9DC948F06010DF01D880E2044BE8854062D10DD93F30A62AA7FD227C4C; +// synopsys translate_on + +// Location: M9K_X33_Y27_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a12 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(gnd), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[4]~76_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_first_bit_number = 4; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y24_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a4 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[4]~76_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a4_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_first_bit_number = 4; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFFF0000003E0000003E0000C83F0000D83F0000F03F0000303E0000303E0000003F0010003F0010203F0010F03F0010703F0018303F001C603D800C003CFE26003C7F0F803FFFFFFFFFFFFFFFF; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF00000000000008108000BDF288E9688E000000000000000000000000FFFFFFFF0000000000041D989EA296D29EE969CA000000000000000000000000000000007FFFFFFC8004198A9AA298929EE9498A00000000000000000000000000000000FFFFFFFE800400CA9AA2AADA8AE949CE0000000000000000000000007FFFFFFEC00000028004046A9F22BA5A9EE90FC20000000000000000000000007FFFFFFE8000000280040FEA8002AA7A9EE12742000000000000000000000000000000023FFFFFFC9FE42BA298E2293A80096742000000000000000000000000000000003FFFFFFC9FE4B19298E3181E8009436A; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'h9FE8234A88F836EE9FF8BD4208282BC080DE87C2B84199C2B85E37C2B05B3A829FE8236688F837CE9FF8898208A82A44808A87CAB9C19DC2B80E3AC2927F2AC2800833E288F837C69FE8AB9688882E4283248DC2B9D188C2ABAE2F8291371092800832EA887807C69FE8AB8688080AC283E49D42B914BFC2A3BF1E82910712EA800802EA883807869DE88E8688080AC68BC4BDC2BB1439C2A27F5F82910314E2800886E6880807C69CC89A8681800BC289549CC2AB0C3942A04B7F82953315E2800886EE900805C61C089FC081E415C289D89DC2AB4E3142A1233D8217330090800086EE900805821C08BEC080D407C289C89DC2AADE3142A13B7F82176300F0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h076B0A5083288F028370C182A801468297E5AC1288D308023FFFFFFC00000000072BA9608BA08D028BF4D182AC015682937CA80288D308023FFFFFFC00000002872B892A8FA08F028A14509AAC0166B2B37DA80288D10D02800000027FFFFFFE852BAD128E388D028A004082AC0166C2937DA00288D10F02C00000027FFFFFFE846289368968C90289E0528A8C016CA29379B20280510F02FFFFFFFE0000000085E2A922816089828BE0428286416C829179B00280511F027FFFFFFC0000000087EA8B32872089828800569287436CA28179B20200513F0000000000FFFFFFFF8768A3028610858288004682874364828019900200403E0000000000FFFFFFFF; +// synopsys translate_on + +// Location: M9K_X33_Y4_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a4 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h35861A00A6112A1481AF1A50A6004A05291627227FF08229B87389E08119A28A7888672DC999B7046A61E60810A7434450E3D33E330F321A18E8A120D1EDC8623DA2C64840C2CCE811522B42008095E5A456C98F4B25EAEA410610545024640CF10410AC463BF9349074917E9A74A12830EFA280EBD3131E484A255D0191C6852730A263DBCCAAA88712242B3BE49AA5338990229B391158C726BC7EB4ECC32308980020680249882691A680488292310B4313CE87FFCD5329A64B708CAC8533316412C4900F646A36630261DA093053D98F19D2C5B653165D4A71AA5682B29B89B6054CC727D292805705A93268676A31111371390B240EC3CC85D331813EB1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h1AA1C248D293110CB951445117D9B6AA500F65068B8CC508BD00184F8705B010A0CC46CC9302649242CE08191634113154562B149100204551178DE805D98EC8A2E5A64B241400267194CD524499BC01D31058CD18684A817A5800B65143281C1310B00A49902C0104004C654E0582040001103654011012021912281216B000C653A0510A1B00C36AC88058CAC126E14E198DFB07E81C3F41510BB08F8F851C3B9AF0147BC1F730B4E91D9D11C3A8F1B82DF19988ACC44072FDB17B4D81882E9DD952B29003D7767BA581A68BC41C2B16AD6EB57F1D048CD4E464190D25ADF2C194E3598360AFB031A1690F4625BB628363B4C90A400E3A04DAA70DA0CC4776; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'hC82B30671933680037A65978674DDEC2D30EEEDA78F5F2A1DEE660FFEA11B175DCB42E9277212A58842051A078007109A0D820166B881042600284403143048295D23A0E191EBC2134B833D53D37E42B05018289A10300A188E315CE98640F548A370D60A0AA3E7288A0B0869FA5E703D1AE17C0EC276B2AFB747B550A8B41021620D1A60A901095D12A0973B95E20838001330138951361967847D42901910A3488480610A91A851E84FF08783F81AEA52D2FDC2200BD2FE81C0357FBEC1D875686C6CA41B2224C88D8456C1DBF20D820A6649774CB11B69933246E9739C998470542C2E3C783A4C24767084C52DC209D60E95DBC096D9A0171A12D5AB99BAB; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h17A24D2C636ED2478B5AE1C99D40761B1E7AA6A89DDD1BBD8DBD223E70531BCDE90C8E38C8E0478AD8B388F94891C9673A50BC32478E083074657E8E0EA53BEE861F8BC1993560946D92D1C0C7F046A245B5849CB751FF15B97FCD50BC7B8524C13E7C640F3645082248D1CC14296E30DEA3057B35C641762CD00D40DABC27472251A60725008AAA056591C4000BB48C0BC29B8034A03400027B84769B520D9196968460CA3388A03ECB45F2C4B70F1829221000FFFC7FEC346F079F13079798EC2A08157331C6CC0E30884244916A0DE26D4D22454091290404A492016887E2111F830F9851184101370588A06D3BF9AE621A5F4E632A6799C83EFAAE06769D; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N24 +cycloneive_lcell_comb \Selector4~0 ( +// Equation(s): +// \Selector4~0_combout = (\z80_|address_pins_|abus[14]~23_combout & ((\Selector3~0_combout ) # ((\ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout )))) # (!\z80_|address_pins_|abus[14]~23_combout & (!\Selector3~0_combout & +// ((\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout )))) + + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\Selector3~0_combout ), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ), + .cin(gnd), + .combout(\Selector4~0_combout ), + .cout()); +// synopsys translate_off +defparam \Selector4~0 .lut_mask = 16'hB9A8; +defparam \Selector4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N14 +cycloneive_lcell_comb \Selector4~1 ( +// Equation(s): +// \Selector4~1_combout = (\Selector3~0_combout & ((\Selector4~0_combout & ((\ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ))) # (!\Selector4~0_combout & (\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout )))) # +// (!\Selector3~0_combout & (((\Selector4~0_combout )))) + + .dataa(\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ), + .datab(\Selector3~0_combout ), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ), + .datad(\Selector4~0_combout ), + .cin(gnd), + .combout(\Selector4~1_combout ), + .cout()); +// synopsys translate_off +defparam \Selector4~1 .lut_mask = 16'hF388; +defparam \Selector4~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N10 +cycloneive_lcell_comb \D[4]~86 ( +// Equation(s): +// \D[4]~86_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [15] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\Selector4~1_combout +// ))))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout )))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|address_pins_|DFFE_apin_latch [15]), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout ), + .datad(\Selector4~1_combout ), + .cin(gnd), + .combout(\D[4]~86_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~86 .lut_mask = 16'hF2D0; +defparam \D[4]~86 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N16 +cycloneive_lcell_comb \D[4]~75 ( +// Equation(s): +// \D[4]~75_combout = ((\Equal2~0_combout & (\D[4]~64_combout )) # (!\Equal2~0_combout & ((\D[4]~86_combout )))) # (!\Equal2~1_combout ) + + .dataa(\Equal2~1_combout ), + .datab(\D[4]~64_combout ), + .datac(\Equal2~0_combout ), + .datad(\D[4]~86_combout ), + .cin(gnd), + .combout(\D[4]~75_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~75 .lut_mask = 16'hDFD5; +defparam \D[4]~75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N30 +cycloneive_lcell_comb \D[4]~76 ( +// Equation(s): +// \D[4]~76_combout = (\z80_|pin_control_|bus_db_pin_oe~15_combout & (((\z80_|data_pins_|dout [4] & \D[4]~75_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout & (((\D[4]~75_combout )) # (!\Equal2~1_combout ))) + + .dataa(\Equal2~1_combout ), + .datab(\z80_|data_pins_|dout [4]), + .datac(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .datad(\D[4]~75_combout ), + .cin(gnd), + .combout(\D[4]~76_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~76 .lut_mask = 16'hCF05; +defparam \D[4]~76 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N30 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[4] ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [4] = (\z80_|bus_control_|db[4]~19_combout & ((\z80_|execute_|ctl_bus_db_we~7_combout ) # ((\z80_|pin_control_|bus_db_pin_re~combout & \D[4]~76_combout )))) # (!\z80_|bus_control_|db[4]~19_combout & +// (\z80_|pin_control_|bus_db_pin_re~combout & ((\D[4]~76_combout )))) + + .dataa(\z80_|bus_control_|db[4]~19_combout ), + .datab(\z80_|pin_control_|bus_db_pin_re~combout ), + .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datad(\D[4]~76_combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [4]), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[4] .lut_mask = 16'hECA0; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[4] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y13_N31 +dffeas \z80_|data_pins_|dout[4] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [4]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|data_pins_|dout [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|data_pins_|dout[4] .is_wysiwyg = "true"; +defparam \z80_|data_pins_|dout[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N24 +cycloneive_lcell_comb \z80_|bus_control_|db[4]~18 ( +// Equation(s): +// \z80_|bus_control_|db[4]~18_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [4]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) + + .dataa(\z80_|bus_control_|db[0]~4_combout ), + .datab(\z80_|data_pins_|dout [4]), + .datac(gnd), + .datad(\z80_|execute_|ctl_bus_db_oe~combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[4]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[4]~18 .lut_mask = 16'h88AA; +defparam \z80_|bus_control_|db[4]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N0 +cycloneive_lcell_comb \z80_|bus_control_|db[4]~19 ( +// Equation(s): +// \z80_|bus_control_|db[4]~19_combout = ((\z80_|bus_control_|db[4]~18_combout & ((\z80_|alu_control_|db[4]~32_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) + + .dataa(\z80_|bus_control_|db[0]~6_combout ), + .datab(\z80_|bus_control_|db[4]~18_combout ), + .datac(\z80_|alu_control_|db[4]~32_combout ), + .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[4]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[4]~19 .lut_mask = 16'hD5DD; +defparam \z80_|bus_control_|db[4]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y17_N1 +dffeas \z80_|ir_|opcode[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|bus_control_|db[4]~19_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|ir_|opcode [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|ir_|opcode[4] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y17_N18 +cycloneive_lcell_comb \z80_|pla_decode_|Equal32~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal32~0_combout = (!\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3]) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [4]), + .datac(gnd), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal32~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal32~0 .lut_mask = 16'h3300; +defparam \z80_|pla_decode_|Equal32~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N18 +cycloneive_lcell_comb \z80_|pla_decode_|Equal41~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal41~1_combout = (\z80_|ir_|opcode [7] & (\z80_|ir_|opcode [6] & ((\z80_|decode_state_|DFFE_instIY1~q ) # (\z80_|decode_state_|DFFE_inst4~q )))) + + .dataa(\z80_|decode_state_|DFFE_instIY1~q ), + .datab(\z80_|decode_state_|DFFE_inst4~q ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal41~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal41~1 .lut_mask = 16'hE000; +defparam \z80_|pla_decode_|Equal41~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal41~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal41~2_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal32~0_combout & (\z80_|pla_decode_|Equal41~1_combout & \z80_|pla_decode_|Equal8~0_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal32~0_combout ), + .datac(\z80_|pla_decode_|Equal41~1_combout ), + .datad(\z80_|pla_decode_|Equal8~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal41~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal41~2 .lut_mask = 16'h4000; +defparam \z80_|pla_decode_|Equal41~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal36~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal36~0_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal1~7_combout & \z80_|pla_decode_|Equal32~0_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal2~0_combout ), + .datac(\z80_|pla_decode_|Equal1~7_combout ), + .datad(\z80_|pla_decode_|Equal32~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal36~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal36~0 .lut_mask = 16'h4000; +defparam \z80_|pla_decode_|Equal36~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_cb_set ( +// Equation(s): +// \z80_|execute_|ctl_state_tbl_cb_set~combout = (\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|pla_decode_|Equal41~2_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & +// ((\z80_|pla_decode_|Equal36~0_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & \z80_|pla_decode_|Equal41~2_combout )))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(\z80_|pla_decode_|Equal36~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_tbl_cb_set~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_tbl_cb_set .lut_mask = 16'hD5C0; +defparam \z80_|execute_|ctl_state_tbl_cb_set .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_state_tbl_we~8_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # ((\z80_|sequencer_|DFFE_T3_ff~q & \z80_|pla_decode_|Equal41~2_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_tbl_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_tbl_we~8 .lut_mask = 16'h00EC; +defparam \z80_|execute_|ctl_state_tbl_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y13_N9 +dffeas \z80_|decode_state_|DFFE_instCB ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|execute_|ctl_state_tbl_cb_set~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_state_tbl_we~8_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|decode_state_|DFFE_instCB~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instCB .is_wysiwyg = "true"; +defparam \z80_|decode_state_|DFFE_instCB .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal52~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal52~0_combout = (!\z80_|decode_state_|DFFE_instCB~q & (!\z80_|decode_state_|DFFE_instED~q & (\z80_|ir_|opcode [7] & \z80_|ir_|opcode [6]))) + + .dataa(\z80_|decode_state_|DFFE_instCB~q ), + .datab(\z80_|decode_state_|DFFE_instED~q ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal52~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal52~0 .lut_mask = 16'h1000; +defparam \z80_|pla_decode_|Equal52~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal2~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal2~1_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal32~0_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal52~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal32~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal2~1 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_ed_set ( +// Equation(s): +// \z80_|execute_|ctl_state_tbl_ed_set~combout = (\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal2~1_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & !\z80_|ir_|opcode [1]))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|pla_decode_|Equal2~1_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_tbl_ed_set~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_tbl_ed_set .lut_mask = 16'h0008; +defparam \z80_|execute_|ctl_state_tbl_ed_set .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y13_N13 +dffeas \z80_|decode_state_|DFFE_instED ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|execute_|ctl_state_tbl_ed_set~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_state_tbl_we~8_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|decode_state_|DFFE_instED~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instED .is_wysiwyg = "true"; +defparam \z80_|decode_state_|DFFE_instED .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N26 +cycloneive_lcell_comb \z80_|decode_state_|table_xx~0 ( +// Equation(s): +// \z80_|decode_state_|table_xx~0_combout = (\z80_|decode_state_|DFFE_instED~q ) # (\z80_|decode_state_|DFFE_instCB~q ) + + .dataa(\z80_|decode_state_|DFFE_instED~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|decode_state_|DFFE_instCB~q ), + .cin(gnd), + .combout(\z80_|decode_state_|table_xx~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|table_xx~0 .lut_mask = 16'hFFAA; +defparam \z80_|decode_state_|table_xx~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N24 +cycloneive_lcell_comb \z80_|pla_decode_|Equal34~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal34~0_combout = (!\z80_|ir_|opcode [0] & (!\z80_|decode_state_|table_xx~0_combout & (\z80_|pla_decode_|Equal3~1_combout & \z80_|pla_decode_|Equal41~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|decode_state_|table_xx~0_combout ), + .datac(\z80_|pla_decode_|Equal3~1_combout ), + .datad(\z80_|pla_decode_|Equal41~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal34~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal34~0 .lut_mask = 16'h1000; +defparam \z80_|pla_decode_|Equal34~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~6_combout = (\z80_|execute_|ctl_alu_op_low~22_combout & (!\z80_|execute_|ixy_d~16_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|pla_decode_|Equal34~0_combout )))) # (!\z80_|execute_|ctl_alu_op_low~22_combout & +// (((!\z80_|execute_|ixy_d~5_combout )) # (!\z80_|pla_decode_|Equal34~0_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datab(\z80_|pla_decode_|Equal34~0_combout ), + .datac(\z80_|execute_|ixy_d~16_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~6 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_reg_sel_pc~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~5_combout = ((!\z80_|execute_|ctl_mRead~6_combout & (!\z80_|execute_|ctl_mRead~7_combout & !\z80_|execute_|ctl_mRead~15_combout ))) # (!\z80_|execute_|ixy_d~5_combout ) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_mRead~6_combout ), + .datac(\z80_|execute_|ctl_mRead~7_combout ), + .datad(\z80_|execute_|ctl_mRead~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~5 .lut_mask = 16'h5557; +defparam \z80_|execute_|ctl_reg_sel_pc~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~4_combout = ((!\z80_|execute_|ixy_d~10_combout & ((!\z80_|pla_decode_|Equal24~0_combout ) # (!\z80_|pla_decode_|Equal21~0_combout )))) # (!\z80_|execute_|ctl_alu_op_low~22_combout ) + + .dataa(\z80_|execute_|ixy_d~10_combout ), + .datab(\z80_|pla_decode_|Equal21~0_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datad(\z80_|pla_decode_|Equal24~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~4 .lut_mask = 16'h1F5F; +defparam \z80_|execute_|ctl_reg_sel_pc~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~2_combout = ((!\z80_|execute_|ctl_mRead~13_combout & ((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout )))) # (!\z80_|execute_|ixy_d~5_combout ) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_mRead~13_combout ), + .datac(\z80_|pla_decode_|Equal12~1_combout ), + .datad(\z80_|pla_decode_|Equal25~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~2 .lut_mask = 16'h7577; +defparam \z80_|execute_|ctl_reg_sel_pc~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~3_combout = (\z80_|execute_|ctl_reg_sel_pc~2_combout & (((!\z80_|pla_decode_|Equal19~0_combout & !\z80_|execute_|ctl_mRead~8_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) + + .dataa(\z80_|pla_decode_|Equal19~0_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~2_combout ), + .datac(\z80_|execute_|ctl_mRead~8_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~3 .lut_mask = 16'h04CC; +defparam \z80_|execute_|ctl_reg_sel_pc~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~7_combout = (\z80_|execute_|ctl_reg_sel_pc~6_combout & (\z80_|execute_|ctl_reg_sel_pc~5_combout & (\z80_|execute_|ctl_reg_sel_pc~4_combout & \z80_|execute_|ctl_reg_sel_pc~3_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~6_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~5_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~4_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~7 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sel_pc~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~8_combout = (\z80_|pla_decode_|Equal12~1_combout & (((\z80_|pla_decode_|Equal3~0_combout & \z80_|pla_decode_|Equal24~0_combout )))) # (!\z80_|pla_decode_|Equal12~1_combout & ((\z80_|pla_decode_|Equal25~0_combout ) # +// ((\z80_|pla_decode_|Equal3~0_combout & \z80_|pla_decode_|Equal24~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal12~1_combout ), + .datab(\z80_|pla_decode_|Equal25~0_combout ), + .datac(\z80_|pla_decode_|Equal3~0_combout ), + .datad(\z80_|pla_decode_|Equal24~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~8 .lut_mask = 16'hF444; +defparam \z80_|execute_|ctl_reg_sel_pc~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~9_combout = (\z80_|execute_|ctl_alu_op_low~22_combout & ((\z80_|execute_|ctl_mRead~15_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~8_combout ) # (\z80_|pla_decode_|Equal34~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datab(\z80_|execute_|ctl_mRead~15_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~8_combout ), + .datad(\z80_|pla_decode_|Equal34~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~9 .lut_mask = 16'hAAA8; +defparam \z80_|execute_|ctl_reg_sel_pc~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~10 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~10_combout = (\z80_|execute_|ctl_reg_sel_pc~7_combout & (!\z80_|execute_|ctl_reg_sel_pc~9_combout & ((!\z80_|pla_decode_|Equal41~2_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~7_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~9_combout ), + .datad(\z80_|pla_decode_|Equal41~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~10 .lut_mask = 16'h040C; +defparam \z80_|execute_|ctl_reg_sel_pc~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~16 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~16_combout = (((\z80_|execute_|ctl_state_alu~3_combout & !\z80_|execute_|fMRead~4_combout )) # (!\z80_|execute_|ctl_apin_mux~0_combout )) # (!\z80_|execute_|ctl_reg_sel_pc~10_combout ) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~10_combout ), + .datab(\z80_|execute_|ctl_apin_mux~0_combout ), + .datac(\z80_|execute_|ctl_state_alu~3_combout ), + .datad(\z80_|execute_|fMRead~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~16 .lut_mask = 16'h77F7; +defparam \z80_|execute_|ctl_reg_sel_pc~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~17 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~17_combout = (\z80_|nM1_int~2_combout ) # ((\z80_|execute_|ctl_reg_sys_we~0_combout ) # ((!\z80_|execute_|ctl_sw_4u~1_combout ) # (!\z80_|execute_|ctl_inc_dec~12_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_reg_sys_we~0_combout ), + .datac(\z80_|execute_|ctl_inc_dec~12_combout ), + .datad(\z80_|execute_|ctl_sw_4u~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~17 .lut_mask = 16'hEFFF; +defparam \z80_|execute_|ctl_reg_sel_pc~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~15 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~15_combout = (\z80_|execute_|ctl_reg_sel_pc~19_combout ) # ((!\z80_|execute_|fMRead~2_combout & ((!\z80_|execute_|ctl_reg_sel_pc~14_combout ) # (!\z80_|execute_|setM1~38_combout )))) + + .dataa(\z80_|execute_|setM1~38_combout ), + .datab(\z80_|execute_|fMRead~2_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~14_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~15 .lut_mask = 16'hFF13; +defparam \z80_|execute_|ctl_reg_sel_pc~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~18 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~18_combout = (\z80_|execute_|ctl_reg_sel_pc~16_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~17_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~15_combout ) # (!\z80_|execute_|ctl_reg_sel_pc~13_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~16_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~17_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~13_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~18 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|ctl_reg_sel_pc~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~19 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~19_combout = (((!\z80_|pla_decode_|Equal19~0_combout & !\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|sequencer_|M5~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|pla_decode_|Equal19~0_combout ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|pla_decode_|Equal34~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~19 .lut_mask = 16'h5F7F; +defparam \z80_|execute_|ctl_reg_sel_wz~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N20 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~3 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_pc~3_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout & (\z80_|execute_|ctl_reg_sel_wz~19_combout & (\z80_|reg_control_|reg_sel_pc~2_combout & \z80_|execute_|ctl_alu_sel_op2_neg~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~19_combout ), + .datac(\z80_|reg_control_|reg_sel_pc~2_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_pc~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_pc~3 .lut_mask = 16'h4000; +defparam \z80_|reg_control_|reg_sel_pc~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N24 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc ( +// Equation(s): +// \z80_|reg_control_|reg_sel_pc~combout = (\z80_|execute_|ctl_reg_sel_pc~18_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & (!\z80_|execute_|ctl_reg_sel_wz~20_combout & \z80_|reg_control_|reg_sel_pc~3_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~18_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~20_combout ), + .datad(\z80_|reg_control_|reg_sel_pc~3_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_pc~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_pc .lut_mask = 16'h0200; +defparam \z80_|reg_control_|reg_sel_pc .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N24 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_72 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_72~combout = (\z80_|reg_control_|reg_sel_pc~combout & (!\z80_|reg_control_|reg_sys_we_hi~combout & \z80_|execute_|ctl_reg_sys_hilo[1]~35_combout )) + + .dataa(\z80_|reg_control_|reg_sel_pc~combout ), + .datab(gnd), + .datac(\z80_|reg_control_|reg_sys_we_hi~combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_72 .lut_mask = 16'h0A00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_72 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N10 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~2 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[0]~2_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ) # ((\z80_|reg_control_|reg_sw_4d_hi~0_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~43_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[0]~2 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|db_hi_as[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y14_N23 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[5]~15_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y14_N17 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[5]~15_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N16 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~13 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[5]~13_combout = (\z80_|reg_file_|gdfx_temp1[5]~57_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # (!\z80_|reg_file_|gdfx_temp1[5]~57_combout & +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[5]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[5]~13 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|db_hi_as[5]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N28 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~14 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[5]~14_combout = (\z80_|reg_file_|db_hi_as[5]~13_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datab(\z80_|reg_file_|b2v_latch_pc_hi|latch [5]), + .datac(gnd), + .datad(\z80_|reg_file_|db_hi_as[5]~13_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[5]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[5]~14 .lut_mask = 16'hDD00; +defparam \z80_|reg_file_|db_hi_as[5]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N22 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~15 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[5]~15_combout = ((\z80_|reg_file_|db_hi_as[5]~14_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .datad(\z80_|reg_file_|db_hi_as[5]~14_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[5]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[5]~15 .lut_mask = 16'hDF55; +defparam \z80_|reg_file_|db_hi_as[5]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y14_N9 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X37_Y14_N23 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~50 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~50_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (\z80_|reg_file_|b2v_latch_hl_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_hl2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (((\z80_|reg_file_|b2v_latch_hl2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [5]), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~50_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~50 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[5]~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y16_N13 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~53 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~53_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout & (\z80_|alu_|db[5]~24_combout & ((\z80_|reg_file_|b2v_latch_af2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # +// (!\z80_|execute_|ctl_reg_in_hi~12_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .datab(\z80_|alu_|db[5]~24_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~53_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~53 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[5]~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y15_N19 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X35_Y15_N17 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~54 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~54_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (\z80_|reg_file_|b2v_latch_wz_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [5]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [5]), + .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~54_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~54 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp1[5]~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y16_N3 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y16_N21 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~52 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~52_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [5]), + .datad(\z80_|reg_file_|b2v_latch_iy_hi|latch [5]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~52_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~52 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[5]~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y16_N5 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X37_Y16_N19 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~51 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~51_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (\z80_|reg_file_|b2v_latch_bc2_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [5]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_bc_hi|latch [5]), + .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~51_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~51 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp1[5]~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~55 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~55_combout = (\z80_|reg_file_|gdfx_temp1[5]~53_combout & (\z80_|reg_file_|gdfx_temp1[5]~54_combout & (\z80_|reg_file_|gdfx_temp1[5]~52_combout & \z80_|reg_file_|gdfx_temp1[5]~51_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[5]~53_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[5]~54_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[5]~52_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[5]~51_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~55_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~55 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[5]~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y15_N27 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N26 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[5]~14 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[5]~14_combout = (\z80_|execute_|ctl_reg_gp_we~8_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [5]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [5]), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[5]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[5]~14 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[5]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y15_N15 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N28 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_hi|latch[5]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_de_hi|latch[5]~feeder_combout = \z80_|reg_file_|gdfx_temp1[5]~57_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_de_hi|latch[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[5]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y15_N29 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_de_hi|latch[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~49 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~49_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [5]), + .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [5]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~49_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~49 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[5]~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y15_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~56 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~56_combout = (\z80_|reg_file_|gdfx_temp1[5]~50_combout & (\z80_|reg_file_|gdfx_temp1[5]~55_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[5]~14_combout & \z80_|reg_file_|gdfx_temp1[5]~49_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[5]~50_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[5]~55_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|db[5]~14_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[5]~49_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~56_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~56 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[5]~56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~57 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~57_combout = ((\z80_|reg_file_|gdfx_temp1[5]~56_combout & ((\z80_|reg_file_|db_hi_as[5]~15_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[5]~15_combout ), + .datab(\z80_|execute_|ctl_sw_4u~6_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[5]~56_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~57 .lut_mask = 16'hBF0F; +defparam \z80_|reg_file_|gdfx_temp1[5]~57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N14 +cycloneive_lcell_comb \z80_|alu_|db[5]~23 ( +// Equation(s): +// \z80_|alu_|db[5]~23_combout = (\z80_|alu_control_|db[5]~15_combout & ((\z80_|reg_file_|gdfx_temp1[5]~57_combout ) # ((!\z80_|execute_|ctl_reg_out_hi~7_combout )))) # (!\z80_|alu_control_|db[5]~15_combout & (!\z80_|execute_|ctl_sw_2d~13_combout & +// ((\z80_|reg_file_|gdfx_temp1[5]~57_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) + + .dataa(\z80_|alu_control_|db[5]~15_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .datac(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .datad(\z80_|execute_|ctl_sw_2d~13_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[5]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[5]~23 .lut_mask = 16'h8ACF; +defparam \z80_|alu_|db[5]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N14 +cycloneive_lcell_comb \z80_|alu_|db[5]~24 ( +// Equation(s): +// \z80_|alu_|db[5]~24_combout = ((\z80_|alu_|db[5]~23_combout & ((\z80_|alu_|db_high[1]~19_combout ) # (!\z80_|execute_|ctl_alu_oe~11_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|alu_|db[5]~23_combout ), + .datab(\z80_|alu_|db_high[1]~19_combout ), + .datac(\z80_|alu_|db[7]~9_combout ), + .datad(\z80_|execute_|ctl_alu_oe~11_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[5]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[5]~24 .lut_mask = 16'h8FAF; +defparam \z80_|alu_|db[5]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N26 +cycloneive_lcell_comb \z80_|sw1_|db_down[5]~0 ( +// Equation(s): +// \z80_|sw1_|db_down[5]~0_combout = (\z80_|bus_control_|db[5]~15_combout ) # ((\z80_|execute_|ctl_sw_1d~6_combout & ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|execute_|ctl_66_oe~2_combout )))) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|execute_|ctl_sw_1d~6_combout ), + .datac(\z80_|bus_control_|db[5]~15_combout ), + .datad(\z80_|execute_|ctl_66_oe~2_combout ), + .cin(gnd), + .combout(\z80_|sw1_|db_down[5]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sw1_|db_down[5]~0 .lut_mask = 16'hF8FC; +defparam \z80_|sw1_|db_down[5]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N22 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_36 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout = (\z80_|execute_|ctl_flags_bus~combout & ((\z80_|alu_control_|db[5]~15_combout ) # ((\z80_|alu_|db_high[1]~19_combout & \z80_|execute_|ctl_flags_alu~15_combout )))) # (!\z80_|execute_|ctl_flags_bus~combout +// & (\z80_|alu_|db_high[1]~19_combout & (\z80_|execute_|ctl_flags_alu~15_combout ))) + + .dataa(\z80_|execute_|ctl_flags_bus~combout ), + .datab(\z80_|alu_|db_high[1]~19_combout ), + .datac(\z80_|execute_|ctl_flags_alu~15_combout ), + .datad(\z80_|alu_control_|db[5]~15_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_36 .lut_mask = 16'hEAC0; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y15_N23 +dffeas \z80_|alu_flags_|flags_yf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_flags_xy_we~18_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|flags_yf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|flags_yf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|flags_yf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N26 +cycloneive_lcell_comb \z80_|alu_control_|db[5]~13 ( +// Equation(s): +// \z80_|alu_control_|db[5]~13_combout = (\z80_|execute_|ctl_flags_oe~2_combout & (\z80_|alu_flags_|flags_yf~q & ((\z80_|alu_control_|out[6]~2_combout ) # (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout )))) # (!\z80_|execute_|ctl_flags_oe~2_combout & +// ((\z80_|alu_control_|out[6]~2_combout ) # ((\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout )))) + + .dataa(\z80_|execute_|ctl_flags_oe~2_combout ), + .datab(\z80_|alu_control_|out[6]~2_combout ), + .datac(\z80_|alu_flags_|flags_yf~q ), + .datad(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[5]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[5]~13 .lut_mask = 16'hF5C4; +defparam \z80_|alu_control_|db[5]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N8 +cycloneive_lcell_comb \z80_|alu_control_|db[5]~14 ( +// Equation(s): +// \z80_|alu_control_|db[5]~14_combout = (\z80_|sw1_|db_down[5]~0_combout & (\z80_|alu_control_|db[5]~13_combout & ((\z80_|reg_file_|gdfx_temp0[5]~72_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) + + .dataa(\z80_|sw1_|db_down[5]~0_combout ), + .datab(\z80_|alu_control_|db[5]~13_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[5]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[5]~14 .lut_mask = 16'h8088; +defparam \z80_|alu_control_|db[5]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N14 +cycloneive_lcell_comb \z80_|alu_control_|db[5]~15 ( +// Equation(s): +// \z80_|alu_control_|db[5]~15_combout = ((\z80_|alu_control_|db[5]~14_combout & ((\z80_|alu_|db[5]~24_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) + + .dataa(\z80_|alu_|db[5]~24_combout ), + .datab(\z80_|execute_|ctl_sw_2u~7_combout ), + .datac(\z80_|alu_control_|db[5]~14_combout ), + .datad(\z80_|alu_control_|db[6]~11_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[5]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[5]~15 .lut_mask = 16'hB0FF; +defparam \z80_|alu_control_|db[5]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y17_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a29 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[5]~77_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_first_bit_number = 5; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y15_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a13 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[5]~77_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_bit_number = 5; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y19_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a21 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[5]~77_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_first_bit_number = 5; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y22_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a5 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[5]~77_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_bit_number = 5; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N28 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ) # +// ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout & +// !\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10 .lut_mask = 16'hCCB8; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N18 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout & +// (\ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout )) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ))))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11 .lut_mask = 16'hAFC0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y31_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a13 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_bit_number = 5; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init3 = 2048'h990442000864A0284030400454782424440404007E404808A4005448387E547C8004420800620824402040024A1242124204044008404208420A4A42424A1242020028008000524A024A4A284252446240001000101042000054265C7E0600007FAF5CA001C181BE0C02418447B1D88BAA85409896BC7C0E5FAC2529CB69A4038E2564731F88FE730045956C357C5ECF7EF8591DF2A8ACFFBFEEF268CD9B51238594AF691A9B8640983B7F76AAB97209EA6257389992FFE684926E0B19FA338B8489D73811171D5C9FF3DCFFFFFF8002000780101F3F4035A0CDED99F79A4775854F179F7D7DBBCF81B2F6421FF684CA6AF85894D29B9D3ACCBA3F27D9DC9911; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init2 = 2048'h5B438D714D4E3DD115E8BD1286EAB5FA1D71BD8F4508BD4BDC8838F9D27B552259BCEFFBB68A6FF529B3B0D92970010BBB6C7D872421210E190E1CCC47A485EAD2F8735647315839EF6F683C64773FC73464D5FE354936D50823A5DAEBEBDBCC6CAFF2622B8D518F63C6030424188FD357718970D25A30CD0731E532DB23002D02C12B12378356DE2C52041CA7A320C51E0D7CA9F5D575775D57FD75DDFDF75FFFDFFFD75F145247F03A0AE7F1E1EB2D5A99D2444108C6A5979B7CC26ABCC241EA4C912568003BB493CE04FF086C188980052BF6ABAAA2FD5D658000011277EB924C10EFAF3CB9B62486512344C61ADE6F15AB67F335A52513FF05AFAEEE8400; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 2048'h0C840083AD485153ACD3C035591630199B8C096CE4DC557D6D55FCCD738573D6E0948817C496E9DE8EA1F88F627B7460106691CC452DB9799E59A5D003733C4EA1BCE33AD2D8BE40A4E5BB7D7BBEC2CEADBBC8B6F87A4A56FBE0B891DE57E4C64EF9AD87727C49CFE7C5DE942B72AC7F6D97DE18920777FDDEE9EB11122A4E18F5569FDE08906765428FB9E6F89FBF0DEAA6064637BCA63FD02E273E5557F0548662C97BC2E8D3FFDB26D23E87BFD97E635A6560CFD93F8EED26E30C70DE8633D6B97C86DF7D9BEDFB99E36B6658F16C6DEFBDD5DF728D6209C852C37FE67CFF32EE4CCCECC64F7E6225FC99EC64C3B6DD7DED0FD7CCEA3BF09A006ECDD1009E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'hA9C9CE3AECF7BE27C000000A8ABA95251B309A60B9DDC19EC3E391458CBB53CA00A85E3C5AAE2C49DDC2F6C7B013DACB319A769818A1081A7389F711D76A09BCBED23D9A99FF9B77183697955D76BF0E0008822742DA45B883C9193DAF09424501859565800698515E10A8189EE9B323E35CE7388D73C6E7A50D0DE6739C73AC538D134115D860ADA57B5B868E54393B1E31E762062577697D57E8464340420E9434CCA34CC9A1CB1FAACC56168071EAC113F5265D5F6A45A098D604A820508C4EA47F9A7E46083716911B0D585CE937B530218E8D2AD3777EE7D3B4BC56C29ADB46809D15D185F8809229B150C29C8081174CA6173B99703DA466629005C604; +// synopsys translate_on + +// Location: M9K_X33_Y1_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a5 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_bit_number = 5; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init3 = 2048'hE10F8B8C100323720BEBBDEBB81DF13FF97B252E2CB4F27BA091FBD0002D1A611E1EDBBC716D44D2912B80041C44558060CFCF15955C0D780DD5E71393920844F25E16C87C5D0308EEC52C011514BBC13AFA1028924D0C7CE738105BD47A10AA5B5C1D9D4193E4339F492B0E1A64E13AE35BE6B67AC8057BDACC155F14E906A017A1841358335450D4B26CD2A21B3D8F2211080B81EC040D7FA0B51CD48008112508062020A02490900092D2040259108806A328F4006D2AA514B42FB006ECCCCB9A360865678449975A8AE72B5C0F7BA800C1B5DC55D7D6FE2EF4EED85D00AB111821321BA426A4FE4956B43595832C271E83E060341AE5F2023FC808177383; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init2 = 2048'h1A2955372D510AC266A5445146E27000020C320FAE1557E37154040A13202DC6F40B840FB9A59B6DBB296562CB6220EFBE99D2776A202044D9101006FD221D305519198C859000004012AFF4FB060307C92BB732203BFDFEFFFFFFDFFF87FCFFFBFFEFF03FFE0FFFBFAFE0FF80787FFF7FFF83F7F87003FFBFFFFBFFFBFF0FFC0FF81FFF7FFBFFDFFFBFFFE1FF0086F3141AAB6005810A0621595A893F9D85983B9254954341968BAC8C141C90938C05B2C9CD267E11650407375FEDD6A2FEB346AAF6CFDC0791AA97B741995A3B3981E06D1A44D3711955197BB9910FCA20744915C84D6C24BAF53929814CA8A4697E8F4201145AE7415DC122A5F010436107; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048'h02E84F969E3C800AC610D276182020227809001A50DDDBA3487BB6AE802BA06509312DA0E620656EAF24D57C08FFB14D289613DC32083803B84DC6415FD5EDC000300A8D128FA20030ACCBAFA237B7024504D36A4BA26081137F059E78991154FE2AC2A884A8CC7FBBB21C851CC92B12E15593C0C020FFEE066558590E882D5B67459F1A8C3240FE4E6A8D028C0C088FCF471D400A19B38211004DD122212288B111114514CB11840E04828849C621392041163C00808C67223422F00110201DD18FCFFFF3FFE7F9FFFFFFF82C0B422D214711E08904524A069491774E663F48F665955B4E2C63DAC0078652D10120900298F7EE380092442AFD400BEC43C003; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'hB5D49EA9D7036A45AA9E870B8E8016720C7C3102AE925262492C84584942D209042216E0216C85B8912250B7157D5955AD406CB685BBF071B47D5193363C1CECAFE59E91BF11498940A0944996D47EE8D7E3A4EAE611AE19A965D01BA86B55E9C52A6A379A382C6C265FB0DA01396D0800C0046405C06F466DD18C4DD7655CD4E7622EC485808C841D64B737041FF68813B149A41531A0A692FB14AE2E5B49D49CDCADCF90E7BD88125BCE706BF6D04AABFC1C001163DC6EFF7FD3230303030000000000000000000008400000000000000000000000000030600000100007E00220000000000000080040004023AD496997B8C0077B886EEF161CF2298A091B; +// synopsys translate_on + +// Location: M9K_X33_Y25_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a13 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(gnd), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[5]~77_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_bit_number = 5; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_first_bit_number = 5; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y28_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a5 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[5]~77_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a5_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_bit_number = 5; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_first_bit_number = 5; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init3 = 2048'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF80000001C000000160F000FF70C0007F78C00000F05001007870010010000000000800000038000000F000000070000000300000006000000000000040000000F00000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000000001D108000BEDA9FA9698A000000000000000000000000FFFFFFFF408102048004188297E014DA9FA9E9CA00000000000000000000000000000000FFFFFFFC800400CA972208DA9FA9CD8E00000000000000000000000000000000FFFFFFFC8004046A97A289FA9FA9CDC20000000000000000000000007FFFFFFC8000000280040E2A97A2997A9DA9CFC20000000000000000000000007FFFFFFE8000000280042EB28002BE369DA9274200000000000000000000000040810206BFFFFFFE9FE430A29D82AC3E8009E34A000000000000000000000000000000023FFFFFFC9FE4B1829FA2800E8009436A; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048'h9FE8334E88F827C697F88D1600A80A44809E8FC2B86999C2B85B3A82B1D32A869FE8336A88F807CA97F88F96A0A80EC2838E8D42B9E98FC2B86B3B82B0D7B2D2800832E288F827CA97F88B82A0080EC683869542B939B8C2B1AB0F8290B730C2800826EA8878078297F88AD2A0280EC283E694C2B83A3BC2A3AB3E8291A316AA800826EE881807C69DE8ABD6A0280BC282209CD2BA2A3D42A2737F82918314E2800806E6981805C69D48AED6A1E80BCA82709FC2BB223DC2A07B7F8295DF11C2800886E6980805869848AAC6A1E42DC281789DC2BBAA3DC6A02B7582955F00928008A6EE98082D9618088AC8A0F40FC289E89DC2BBCA3DC2A18B7782154F02F0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'h174F0870801C870281E2C982A801460297E5AC0288F318023FFFFFFC0000000297DF094A8094870281D6C082AC01460293FDA89288D31902BFFFFFFE40810106879F8D228C8685028016C082AC014642B3FCA80288D10F02800000027FFFFFFE879F893284DEC9028000408AAC014C02937DA00288D10F02800000027FFFFFFC841FA902804E81068BC04292AC0145E29379B00288D11F02FFFFFFFC0000000084FE89328166C1028BE05282AE4144829179B20288511F02FFFFFFFC0000000084F283328516850A88204602874364829179B08280513E0240810104FFFFFFFF843A8302853685828800560287476C928039B00200413E0000000000FFFFFFFF; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N20 +cycloneive_lcell_comb \Mux2~0 ( +// Equation(s): +// \Mux2~0_combout = (\Selector3~0_combout & (((\ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout )) # (!\z80_|address_pins_|abus[14]~23_combout ))) # (!\Selector3~0_combout & (\z80_|address_pins_|abus[14]~23_combout & +// ((\ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout )))) + + .dataa(\Selector3~0_combout ), + .datab(\z80_|address_pins_|abus[14]~23_combout ), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout ), + .cin(gnd), + .combout(\Mux2~0_combout ), + .cout()); +// synopsys translate_off +defparam \Mux2~0 .lut_mask = 16'hE6A2; +defparam \Mux2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N26 +cycloneive_lcell_comb \Mux2~1 ( +// Equation(s): +// \Mux2~1_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\Mux2~0_combout )))) # (!\z80_|address_pins_|abus[14]~23_combout & ((\Mux2~0_combout & (\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout )) # (!\Mux2~0_combout & +// ((\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ))))) + + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ), + .datad(\Mux2~0_combout ), + .cin(gnd), + .combout(\Mux2~1_combout ), + .cout()); +// synopsys translate_off +defparam \Mux2~1 .lut_mask = 16'hEE50; +defparam \Mux2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N8 +cycloneive_lcell_comb \D[5]~87 ( +// Equation(s): +// \D[5]~87_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [15] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\Mux2~1_combout ))))) # +// (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout )) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout ), + .datac(\Mux2~1_combout ), + .datad(\z80_|address_pins_|DFFE_apin_latch [15]), + .cin(gnd), + .combout(\D[5]~87_combout ), + .cout()); +// synopsys translate_off +defparam \D[5]~87 .lut_mask = 16'hCCE4; +defparam \D[5]~87 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N4 +cycloneive_lcell_comb \D[5]~68 ( +// Equation(s): +// \D[5]~68_combout = (\D[5]~67_combout & (\D[5]~87_combout & ((\z80_|data_pins_|dout [5]) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout )))) # (!\D[5]~67_combout & ((\z80_|data_pins_|dout [5]) # ((!\z80_|pin_control_|bus_db_pin_oe~15_combout )))) + + .dataa(\D[5]~67_combout ), + .datab(\z80_|data_pins_|dout [5]), + .datac(\D[5]~87_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .cin(gnd), + .combout(\D[5]~68_combout ), + .cout()); +// synopsys translate_off +defparam \D[5]~68 .lut_mask = 16'hC4F5; +defparam \D[5]~68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N12 +cycloneive_lcell_comb \D[5]~77 ( +// Equation(s): +// \D[5]~77_combout = (\D[5]~68_combout ) # (!\D[0]~84_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\D[5]~68_combout ), + .datad(\D[0]~84_combout ), + .cin(gnd), + .combout(\D[5]~77_combout ), + .cout()); +// synopsys translate_off +defparam \D[5]~77 .lut_mask = 16'hF0FF; +defparam \D[5]~77 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N16 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[5] ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [5] = (\D[5]~77_combout & ((\z80_|pin_control_|bus_db_pin_re~combout ) # ((\z80_|execute_|ctl_bus_db_we~7_combout & \z80_|bus_control_|db[5]~15_combout )))) # (!\D[5]~77_combout & +// (((\z80_|execute_|ctl_bus_db_we~7_combout & \z80_|bus_control_|db[5]~15_combout )))) + + .dataa(\D[5]~77_combout ), + .datab(\z80_|pin_control_|bus_db_pin_re~combout ), + .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datad(\z80_|bus_control_|db[5]~15_combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [5]), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[5] .lut_mask = 16'hF888; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[5] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y13_N25 +dffeas \z80_|data_pins_|dout[5] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [5]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|data_pins_|dout [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|data_pins_|dout[5] .is_wysiwyg = "true"; +defparam \z80_|data_pins_|dout[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N10 +cycloneive_lcell_comb \z80_|bus_control_|db[5]~14 ( +// Equation(s): +// \z80_|bus_control_|db[5]~14_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [5]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_bus_db_oe~combout ), + .datac(\z80_|bus_control_|db[0]~4_combout ), + .datad(\z80_|data_pins_|dout [5]), + .cin(gnd), + .combout(\z80_|bus_control_|db[5]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[5]~14 .lut_mask = 16'hF030; +defparam \z80_|bus_control_|db[5]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N18 +cycloneive_lcell_comb \z80_|bus_control_|db[5]~15 ( +// Equation(s): +// \z80_|bus_control_|db[5]~15_combout = ((\z80_|bus_control_|db[5]~14_combout & ((\z80_|alu_control_|db[5]~15_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) + + .dataa(\z80_|bus_control_|db[0]~6_combout ), + .datab(\z80_|alu_control_|db[5]~15_combout ), + .datac(\z80_|bus_control_|db[5]~14_combout ), + .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[5]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[5]~15 .lut_mask = 16'hD5F5; +defparam \z80_|bus_control_|db[5]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y16_N17 +dffeas \z80_|ir_|opcode[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|bus_control_|db[5]~15_combout ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|ir_|opcode [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|ir_|opcode[5] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~8 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~8_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal9~0_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal9~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~8 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_mRead~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_we~8_combout = (\z80_|sequencer_|M5~q & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|execute_|ctl_mRead~8_combout ) # (\z80_|pla_decode_|Equal9~1_combout )))) + + .dataa(\z80_|sequencer_|M5~q ), + .datab(\z80_|execute_|ctl_mRead~8_combout ), + .datac(\z80_|pla_decode_|Equal9~1_combout ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_we~8 .lut_mask = 16'h00A8; +defparam \z80_|execute_|ctl_bus_db_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y15_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_we~4_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mWrite~6_combout ) # ((\z80_|pla_decode_|Equal21~0_combout & \z80_|pla_decode_|Equal24~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal21~0_combout ), + .datab(\z80_|pla_decode_|Equal24~0_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ctl_mWrite~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_we~4 .lut_mask = 16'hF080; +defparam \z80_|execute_|ctl_bus_db_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_we~6_combout = (\z80_|execute_|ctl_bus_db_we~4_combout ) # (((!\z80_|execute_|ctl_apin_mux~0_combout ) # (!\z80_|execute_|ctl_sw_2u~3_combout )) # (!\z80_|execute_|ctl_bus_db_we~5_combout )) + + .dataa(\z80_|execute_|ctl_bus_db_we~4_combout ), + .datab(\z80_|execute_|ctl_bus_db_we~5_combout ), + .datac(\z80_|execute_|ctl_sw_2u~3_combout ), + .datad(\z80_|execute_|ctl_apin_mux~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_we~6 .lut_mask = 16'hBFFF; +defparam \z80_|execute_|ctl_bus_db_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout = (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal8~0_combout & \z80_|execute_|ctl_ir_we~4_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~0_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|pla_decode_|Equal8~0_combout ), + .datad(\z80_|execute_|ctl_ir_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_we~3_combout = (\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_iorw~10_combout ) # (\z80_|execute_|ctl_mWrite~7_combout )))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ), + .datac(\z80_|execute_|ctl_iorw~10_combout ), + .datad(\z80_|execute_|ctl_mWrite~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_we~3 .lut_mask = 16'hEEEC; +defparam \z80_|execute_|ctl_bus_db_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_we~2_combout = (\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|pla_decode_|Equal13~2_combout ) # ((\z80_|execute_|ctl_mRead~8_combout ) # (\z80_|execute_|ctl_mWrite~7_combout )))) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ctl_mRead~8_combout ), + .datad(\z80_|execute_|ctl_mWrite~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_we~2 .lut_mask = 16'hCCC8; +defparam \z80_|execute_|ctl_bus_db_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_we~7_combout = (\z80_|execute_|ctl_bus_db_we~8_combout ) # ((\z80_|execute_|ctl_bus_db_we~6_combout ) # ((\z80_|execute_|ctl_bus_db_we~3_combout ) # (\z80_|execute_|ctl_bus_db_we~2_combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_we~8_combout ), + .datab(\z80_|execute_|ctl_bus_db_we~6_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~3_combout ), + .datad(\z80_|execute_|ctl_bus_db_we~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_we~7 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_bus_db_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~66 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][0]~66_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|zx_keyboard_|shifted~q )) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|shifted~q ), .datad(gnd), .cin(gnd), - .combout(\z80_|execute_|ctl_apin_mux~2_combout ), + .combout(\ula_|zx_keyboard_|keys[5][0]~66_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_apin_mux~2 .lut_mask = 16'h8F8F; -defparam \z80_|execute_|ctl_apin_mux~2 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[5][0]~66 .lut_mask = 16'hCECE; +defparam \ula_|zx_keyboard_|keys[5][0]~66 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y16_N18 +// Location: LCCOMB_X29_Y8_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~80 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][0]~80_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [0]))) # (!\ula_|ps2_keyboard_|shiftreg [4] & +// (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [0]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][0]~80_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][0]~80 .lut_mask = 16'h1008; +defparam \ula_|zx_keyboard_|keys[5][0]~80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~81 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][0]~81_combout = (\ula_|zx_keyboard_|keys[5][0]~80_combout & (\ula_|ps2_keyboard_|shiftreg [2] $ (\ula_|ps2_keyboard_|shiftreg [4]))) + + .dataa(\ula_|zx_keyboard_|keys[5][0]~80_combout ), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][0]~81_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][0]~81 .lut_mask = 16'h0AA0; +defparam \ula_|zx_keyboard_|keys[5][0]~81 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~82 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][0]~82_combout = (\ula_|zx_keyboard_|keys[6][1]~39_combout & ((\ula_|zx_keyboard_|keys[5][0]~81_combout & (!\ula_|zx_keyboard_|keys[5][0]~66_combout )) # (!\ula_|zx_keyboard_|keys[5][0]~81_combout & +// ((\ula_|zx_keyboard_|keys[5][0]~q ))))) # (!\ula_|zx_keyboard_|keys[6][1]~39_combout & (((\ula_|zx_keyboard_|keys[5][0]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][0]~66_combout ), + .datab(\ula_|zx_keyboard_|keys[6][1]~39_combout ), + .datac(\ula_|zx_keyboard_|keys[5][0]~q ), + .datad(\ula_|zx_keyboard_|keys[5][0]~81_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][0]~82_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][0]~82 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[5][0]~82 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y8_N5 +dffeas \ula_|zx_keyboard_|keys[5][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[5][0]~82_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[5][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[5][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~84 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][0]~84_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|zx_keyboard_|shifted~q )) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|zx_keyboard_|shifted~q ), + .datac(gnd), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][0]~84_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][0]~84 .lut_mask = 16'hFF22; +defparam \ula_|zx_keyboard_|keys[4][0]~84 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~83 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][0]~83_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [5] $ (\ula_|ps2_keyboard_|shiftreg [3])))) # (!\ula_|ps2_keyboard_|shiftreg [1] & +// (!\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [0]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][0]~83_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][0]~83 .lut_mask = 16'h0148; +defparam \ula_|zx_keyboard_|keys[4][0]~83 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~85 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][0]~85_combout = (\ula_|zx_keyboard_|keys[4][0]~83_combout & ((\ula_|zx_keyboard_|keys[5][1]~35_combout & (!\ula_|zx_keyboard_|keys[4][0]~84_combout )) # (!\ula_|zx_keyboard_|keys[5][1]~35_combout & +// ((\ula_|zx_keyboard_|keys[4][0]~q ))))) # (!\ula_|zx_keyboard_|keys[4][0]~83_combout & (((\ula_|zx_keyboard_|keys[4][0]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[4][0]~84_combout ), + .datab(\ula_|zx_keyboard_|keys[4][0]~83_combout ), + .datac(\ula_|zx_keyboard_|keys[4][0]~q ), + .datad(\ula_|zx_keyboard_|keys[5][1]~35_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][0]~85_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][0]~85 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[4][0]~85 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y10_N21 +dffeas \ula_|zx_keyboard_|keys[4][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[4][0]~85_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[4][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[4][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N14 +cycloneive_lcell_comb \D[0]~42 ( +// Equation(s): +// \D[0]~42_combout = (\z80_|address_pins_|abus[12]~21_combout & (((\z80_|address_pins_|abus[13]~20_combout )) # (!\ula_|zx_keyboard_|keys[5][0]~q ))) # (!\z80_|address_pins_|abus[12]~21_combout & (!\ula_|zx_keyboard_|keys[4][0]~q & +// ((\z80_|address_pins_|abus[13]~20_combout ) # (!\ula_|zx_keyboard_|keys[5][0]~q )))) + + .dataa(\z80_|address_pins_|abus[12]~21_combout ), + .datab(\ula_|zx_keyboard_|keys[5][0]~q ), + .datac(\z80_|address_pins_|abus[13]~20_combout ), + .datad(\ula_|zx_keyboard_|keys[4][0]~q ), + .cin(gnd), + .combout(\D[0]~42_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~42 .lut_mask = 16'hA2F3; +defparam \D[0]~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][0]~78 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][0]~78_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|zx_keyboard_|keys[1][4]~23_combout & \ula_|ps2_keyboard_|shiftreg [3]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|zx_keyboard_|keys[1][4]~23_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][0]~78_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][0]~78 .lut_mask = 16'h1000; +defparam \ula_|zx_keyboard_|keys[1][0]~78 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][0]~79 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][0]~79_combout = (\ula_|zx_keyboard_|keys[1][0]~78_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[1][0]~78_combout & ((\ula_|zx_keyboard_|keys[1][0]~q ))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[1][0]~q ), + .datad(\ula_|zx_keyboard_|keys[1][0]~78_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][0]~79_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][0]~79 .lut_mask = 16'h55F0; +defparam \ula_|zx_keyboard_|keys[1][0]~79 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y9_N27 +dffeas \ula_|zx_keyboard_|keys[1][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[1][0]~79_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[1][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[1][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][0]~76 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][0]~76_combout = (\ula_|zx_keyboard_|keys[3][1]~26_combout & ((\ula_|zx_keyboard_|keys[3][0]~75_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][0]~75_combout & ((\ula_|zx_keyboard_|keys[3][0]~q +// ))))) # (!\ula_|zx_keyboard_|keys[3][1]~26_combout & (((\ula_|zx_keyboard_|keys[3][0]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[3][1]~26_combout ), + .datac(\ula_|zx_keyboard_|keys[3][0]~q ), + .datad(\ula_|zx_keyboard_|keys[3][0]~75_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][0]~76_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][0]~76 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[3][0]~76 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y9_N13 +dffeas \ula_|zx_keyboard_|keys[3][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[3][0]~76_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[3][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[3][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][0]~77 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][0]~77_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (((\ula_|zx_keyboard_|keys[2][0]~q )))) # (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[2][1]~24_combout & (!\ula_|zx_keyboard_|released~q )) # +// (!\ula_|zx_keyboard_|keys[2][1]~24_combout & ((\ula_|zx_keyboard_|keys[2][0]~q ))))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|zx_keyboard_|keys[2][0]~q ), + .datad(\ula_|zx_keyboard_|keys[2][1]~24_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][0]~77_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][0]~77 .lut_mask = 16'hD1F0; +defparam \ula_|zx_keyboard_|keys[2][0]~77 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y9_N11 +dffeas \ula_|zx_keyboard_|keys[2][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[2][0]~77_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[2][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[2][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N28 +cycloneive_lcell_comb \D[0]~40 ( +// Equation(s): +// \D[0]~40_combout = (\ula_|zx_keyboard_|keys[3][0]~q & (\z80_|address_pins_|abus[11]~19_combout & ((\z80_|address_pins_|abus[10]~24_combout ) # (!\ula_|zx_keyboard_|keys[2][0]~q )))) # (!\ula_|zx_keyboard_|keys[3][0]~q & +// ((\z80_|address_pins_|abus[10]~24_combout ) # ((!\ula_|zx_keyboard_|keys[2][0]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[3][0]~q ), + .datab(\z80_|address_pins_|abus[10]~24_combout ), + .datac(\z80_|address_pins_|abus[11]~19_combout ), + .datad(\ula_|zx_keyboard_|keys[2][0]~q ), + .cin(gnd), + .combout(\D[0]~40_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~40 .lut_mask = 16'hC4F5; +defparam \D[0]~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr0~0 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr0~0_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [0])) # (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg +// [2])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr0~0 .lut_mask = 16'h1012; +defparam \ula_|zx_keyboard_|WideOr0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys~71 ( +// Equation(s): +// \ula_|zx_keyboard_|keys~71_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (((!\ula_|zx_keyboard_|WideOr0~0_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [4] & (((!\ula_|ps2_keyboard_|shiftreg [3])) # (!\ula_|zx_keyboard_|keys[6][4]~45_combout ))) + + .dataa(\ula_|zx_keyboard_|keys[6][4]~45_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|zx_keyboard_|WideOr0~0_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys~71_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys~71 .lut_mask = 16'h13DF; +defparam \ula_|zx_keyboard_|keys~71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~70 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][3]~70_combout = (\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [6]) + + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][3]~70_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][3]~70 .lut_mask = 16'hAA00; +defparam \ula_|zx_keyboard_|keys[4][3]~70 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~72 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][0]~72_combout = (\ula_|zx_keyboard_|keys[0][0]~13_combout & (((!\ula_|zx_keyboard_|keys~71_combout & \ula_|zx_keyboard_|keys[4][3]~70_combout )) # (!\ula_|zx_keyboard_|extended~q ))) + + .dataa(\ula_|zx_keyboard_|extended~q ), + .datab(\ula_|zx_keyboard_|keys~71_combout ), + .datac(\ula_|zx_keyboard_|keys[0][0]~13_combout ), + .datad(\ula_|zx_keyboard_|keys[4][3]~70_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][0]~72_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][0]~72 .lut_mask = 16'h7050; +defparam \ula_|zx_keyboard_|keys[0][0]~72 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr4~0 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr4~0_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (((\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [1])))) # (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [4] & +// (!\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr4~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr4~0 .lut_mask = 16'hA004; +defparam \ula_|zx_keyboard_|WideOr4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys~73 ( +// Equation(s): +// \ula_|zx_keyboard_|keys~73_combout = (!\ula_|zx_keyboard_|extended~q & (((\ula_|ps2_keyboard_|shiftreg [3]) # (!\ula_|zx_keyboard_|WideOr4~0_combout )) # (!\ula_|zx_keyboard_|keys[4][1]~29_combout ))) + + .dataa(\ula_|zx_keyboard_|extended~q ), + .datab(\ula_|zx_keyboard_|keys[4][1]~29_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|zx_keyboard_|WideOr4~0_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys~73_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys~73 .lut_mask = 16'h5155; +defparam \ula_|zx_keyboard_|keys~73 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~74 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][0]~74_combout = (\ula_|zx_keyboard_|keys[0][0]~72_combout & ((\ula_|zx_keyboard_|keys~73_combout & (\ula_|zx_keyboard_|keys[0][0]~q )) # (!\ula_|zx_keyboard_|keys~73_combout & ((!\ula_|zx_keyboard_|released~q ))))) # +// (!\ula_|zx_keyboard_|keys[0][0]~72_combout & (((\ula_|zx_keyboard_|keys[0][0]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[0][0]~72_combout ), + .datab(\ula_|zx_keyboard_|keys~73_combout ), + .datac(\ula_|zx_keyboard_|keys[0][0]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][0]~74_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][0]~74 .lut_mask = 16'hD0F2; +defparam \ula_|zx_keyboard_|keys[0][0]~74 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y8_N11 +dffeas \ula_|zx_keyboard_|keys[0][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[0][0]~74_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[0][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[0][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~2 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row~2_combout = ((\z80_|address_pins_|DFFE_apin_latch [8]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) # (!\ula_|zx_keyboard_|keys[0][0]~q ) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|keys[0][0]~q ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [8]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row~2 .lut_mask = 16'hFF3F; +defparam \ula_|zx_keyboard_|key_row~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N16 +cycloneive_lcell_comb \D[0]~41 ( +// Equation(s): +// \D[0]~41_combout = (\D[0]~40_combout & (\ula_|zx_keyboard_|key_row~2_combout & ((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][0]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[1][0]~q ), + .datab(\D[0]~40_combout ), + .datac(\ula_|zx_keyboard_|key_row~2_combout ), + .datad(\z80_|address_pins_|abus[9]~17_combout ), + .cin(gnd), + .combout(\D[0]~41_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~41 .lut_mask = 16'hC040; +defparam \D[0]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~89 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][0]~89_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][0]~89_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][0]~89 .lut_mask = 16'h0008; +defparam \ula_|zx_keyboard_|keys[6][0]~89 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~90 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][0]~90_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|zx_keyboard_|keys[6][0]~89_combout & (\ula_|zx_keyboard_|shifted~3_combout & \ula_|zx_keyboard_|keys[7][1]~21_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|zx_keyboard_|keys[6][0]~89_combout ), + .datac(\ula_|zx_keyboard_|shifted~3_combout ), + .datad(\ula_|zx_keyboard_|keys[7][1]~21_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][0]~90_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][0]~90 .lut_mask = 16'h8000; +defparam \ula_|zx_keyboard_|keys[6][0]~90 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~91 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][0]~91_combout = (\ula_|zx_keyboard_|keys[6][0]~90_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[6][0]~90_combout & (\ula_|zx_keyboard_|keys[6][0]~q )) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|keys[6][0]~90_combout ), + .datac(\ula_|zx_keyboard_|keys[6][0]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][0]~91_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][0]~91 .lut_mask = 16'h30FC; +defparam \ula_|zx_keyboard_|keys[6][0]~91 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y10_N19 +dffeas \ula_|zx_keyboard_|keys[6][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[6][0]~91_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[6][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[6][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~131 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][0]~131_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|keys[3][0]~75_combout & (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [6]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|zx_keyboard_|keys[3][0]~75_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][0]~131_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][0]~131 .lut_mask = 16'h8000; +defparam \ula_|zx_keyboard_|keys[7][0]~131 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~3 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~3_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [6]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~3 .lut_mask = 16'h000F; +defparam \ula_|zx_keyboard_|WideOr16~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~86 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][0]~86_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|zx_keyboard_|keys[5][4]~62_combout & (\ula_|zx_keyboard_|WideOr16~3_combout & \ula_|ps2_keyboard_|shiftreg [3]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|zx_keyboard_|keys[5][4]~62_combout ), + .datac(\ula_|zx_keyboard_|WideOr16~3_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][0]~86_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][0]~86 .lut_mask = 16'h4000; +defparam \ula_|zx_keyboard_|keys[7][0]~86 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~87 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][0]~87_combout = (\ula_|zx_keyboard_|keys[7][1]~21_combout & (\ula_|ps2_keyboard_|shiftreg [5] & ((\ula_|zx_keyboard_|keys[7][0]~131_combout ) # (\ula_|zx_keyboard_|keys[7][0]~86_combout )))) + + .dataa(\ula_|zx_keyboard_|keys[7][1]~21_combout ), + .datab(\ula_|zx_keyboard_|keys[7][0]~131_combout ), + .datac(\ula_|zx_keyboard_|keys[7][0]~86_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][0]~87_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][0]~87 .lut_mask = 16'hA800; +defparam \ula_|zx_keyboard_|keys[7][0]~87 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~88 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][0]~88_combout = (\ula_|zx_keyboard_|keys[7][0]~87_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[7][0]~87_combout & (\ula_|zx_keyboard_|keys[7][0]~q )) + + .dataa(\ula_|zx_keyboard_|keys[7][0]~87_combout ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[7][0]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][0]~88_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][0]~88 .lut_mask = 16'h50FA; +defparam \ula_|zx_keyboard_|keys[7][0]~88 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y10_N5 +dffeas \ula_|zx_keyboard_|keys[7][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[7][0]~88_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[7][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[7][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N12 +cycloneive_lcell_comb \D[0]~43 ( +// Equation(s): +// \D[0]~43_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\z80_|address_pins_|abus[15]~22_combout ) # (!\ula_|zx_keyboard_|keys[7][0]~q )))) # (!\z80_|address_pins_|abus[14]~23_combout & (!\ula_|zx_keyboard_|keys[6][0]~q & +// ((\z80_|address_pins_|abus[15]~22_combout ) # (!\ula_|zx_keyboard_|keys[7][0]~q )))) + + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\ula_|zx_keyboard_|keys[6][0]~q ), + .datac(\ula_|zx_keyboard_|keys[7][0]~q ), + .datad(\z80_|address_pins_|abus[15]~22_combout ), + .cin(gnd), + .combout(\D[0]~43_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~43 .lut_mask = 16'hBB0B; +defparam \D[0]~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N10 +cycloneive_lcell_comb \D[0]~44 ( +// Equation(s): +// \D[0]~44_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[0]~42_combout & (\D[0]~41_combout & \D[0]~43_combout ))) + + .dataa(\D[0]~42_combout ), + .datab(\D[0]~41_combout ), + .datac(\z80_|address_pins_|abus[0]~16_combout ), + .datad(\D[0]~43_combout ), + .cin(gnd), + .combout(\D[0]~44_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~44 .lut_mask = 16'hF8F0; +defparam \D[0]~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y17_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a24 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[0]~46_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_first_bit_number = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y18_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a16 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[0]~46_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_first_bit_number = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y15_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a8 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[0]~46_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y19_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a0 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[0]~46_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081; +// synopsys translate_on + +// Location: LCCOMB_X23_Y14_N12 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout )) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ))))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4 .lut_mask = 16'hE3E0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y14_N6 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~5 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~5_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4_combout & +// (\ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout )) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout ))))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4_combout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~5 .lut_mask = 16'hAFC0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y13_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a8 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h3C00000000000000000000000000000000000000000000000000000000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005DB824E17CAAE881C1908A79F24B7D1B4857A981A6AF39DFF5A2FEE9141EB33592D8E9B82471FDDA6791810A1C29D415CC1A8FA03444DF0083F83506BA93E8D1A1856A768D73A08418BFB25A40001DD4833DAF33BD311BB45F39667627407EF59ED569C483EB3BE1B10551B1428A6169579293ED063CAA9C6ADB0433CFC15C33AFF04C710408C20AC28B5909A229CD7D1DB4EB9A44CE0EEDBBBD391D3128AAA3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'hDDE6FC8EBE3F9F3C3DFC6E8F07BFD31D50660B1E0B2506A533CE0E340C7C745CAEC4837C2A5FECBB94C1C969FFDDFF79BFFAAFDCA8D748399ABF75558ADD02F56F6DFFF29CB70FFD25A59DFFFED7B3F7E8B4CE6FFF3EF9CEC6BAE57ABFFFCEE647B2AFF5B87AA26AFFDD317DEDCFBDFFE1A0CAD3B58877DD2F647F7DF748E7CF4693FD3C1238FFAFBD7FDF567FA8FEF024F33AFD3AABC6B105EA80272D64895FFF9FFF6E3881C81AFDCF2257FD4F8ED5257D0E9B800726B6564D2B05012F76DF636CDEB4BDFCAEEFC61DFFEFB7E26262DEF2CB9F71565824FEBF3F7BDDEABB593F1BF746FBFFC353E37263FF38A796EF39E3FD7DFEBA7FFEFFBD97ABAF09E909; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'hE629BDF93D7F5B5BAF92FBAB477E9B315DB5A310CFACC7408DF9A544B1E57AF6EFEF92C2FA4D8D4E4AC86C277338FA37BCDD9D47782DB75EFF80781BCD23D0AFCAE30B9FE6AA29FFF6F72DA73DFE4F7ACD39687B9E69C5359E9B991F0246EFFBC5595561AC64787878F5CE14C664CF9EB0CDAFFBABEF1E83358371B9ED96E5069555AFBBD3AEBFCABFBBED7A5C5FE9BD0E6A91C6E7610042695EEB08D8881B1D735AF87DAE59FABBD7DEAF8717F2B72F428F5E37E5D6E13157B99CBD2D73B9C73C563C8B02C8CC39C64DDCEA1BEEB5E7353F93786145598FE634EF1000179B345725EA43CE18F187A1DE4DAABEA97963E3A7A96B8B7CBC095BEB7CE46274D9AF; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h4ED4AE2B1650D21EAFE01E7099EFCA3094FD4D705CF6B84AE21583E13385F8650004406BD60A023AB063D4E5966EA41AA997F5A49BFCB0657A9732D28EB8217E65F627A15E1057ADEE7B9E27122A58FB2B98B1EA560390C7E87715861814E04DCB76FAB179E9619BC7E7E9C9FD801CF87DBA1EA496E829D4E62861E1AF436A7585287860729C77B6C68CAEA3033A6E84D67249B594C407B39C68B4C1C97FDEFC6BAD12FDBB525EF4F87F4A23EC13CBC0262D8899A3A290F04F41C1324045B9FCEEC890579E95D5A0A546CCCDD48577558ABE7CA36EF67A70F6A8758BDA052D5B95DE707778B17C2379847A23AE5D4BB01F36F3F44A8162566D9FB15DE7CC83F7; +// synopsys translate_on + +// Location: M9K_X22_Y28_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a0 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[0]~46_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_bit_number = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF0000000000000000000000003FF03FFC20107FFC3FF00B9C3FF007FC18000FFC3FF03FD42FF43FFC2FFC3FE01FFE7FE81FFE3FDC07FE3FFC07FE2FFC07FE0F0807FE1F18207F0F3030FD8C30383300600000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h000000000000000000000000FFFFFFFFE0408103E004044390120EAA803920C6000000000000000000000000FFFFFFFFE0408103A004005A84723CEA813930C2000000000000000000000000800000009FBF7EFD8004027A8572358A813950EA000000000000000000000000800000009FBF7EFC8005157A85733F0A8139518E0000000000000000000000009FBF7EFC800000008006113A8C73330A813919EA0000000000000000000000009FBF7EFC8000000080060022801333A2813973EA00000000000000000000000080000000DFFFFFFD9FF6022A84730366801913FE000000000000000000000000E0408102FFFFFFFD9FF60ABA84730426901913EE; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h9FF81326887812F28FF0D7C2CC6856E3894C8B62980099E28988BFC2B9EC79829FE81362887842E68FF0C7C2CCE056E2896C89E2888098E28AA8BBC299FC1AC280081372887842E69EE0C7CA8CE046E289E089E289C899E28AA8BEC2993C1AE28008837E882852C69EE0874288E046E2886099E289689FCE8AD8BFC2999C09F680088376880846C69CA88382880042A289D08DE289F098C28AF8BFC289FC88F280088376880857C29CA893C2888043A289508DE288F0D9428BF0AFC289F4888A800883F2880857829C2891C3889047F2898885E2899081428990AF8289FC8BE3800893F6880847C2DC0894E389944F62888899668918914289803582CB8C8AF3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'hCBAC80F38DA845828DF44582840124029375A4A288D108A2FFFFFFFDE0408082CAEC80968DF855828CE4408284012006917194C280510B82DFFFFFFC8000000288EC84A28FFC4586880C648A860124128179900280510F82800000009FBF7F7C8BA080BA8FEC40828808618286012C028179901280510702800000009FBF7F7C8BB081BA8CAC408289E0618286812C1281791002805007029FBF7F7C8000000089B881828CB440828BE07782868322028139909280400F029FBF7F7D8000000089A4C3928FF444828A00260A8792227281199022A0001F03E0408081FFFFFFFF89A0C1928FD440828800260687B720C280199002E0001F03E0408083FFFFFFFF; +// synopsys translate_on + +// Location: M9K_X22_Y21_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a8 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(gnd), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[0]~46_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_first_bit_number = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X23_Y14_N4 +cycloneive_lcell_comb \Selector2~0 ( +// Equation(s): +// \Selector2~0_combout = (\Selector3~0_combout & (((\ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ) # (!\z80_|address_pins_|abus[14]~23_combout )))) # (!\Selector3~0_combout & +// (\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout & (\z80_|address_pins_|abus[14]~23_combout ))) + + .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ), + .datab(\Selector3~0_combout ), + .datac(\z80_|address_pins_|abus[14]~23_combout ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ), + .cin(gnd), + .combout(\Selector2~0_combout ), + .cout()); +// synopsys translate_off +defparam \Selector2~0 .lut_mask = 16'hEC2C; +defparam \Selector2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y31_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a0 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h1EEA3633EFEA856D05BA968C1B3C30CA1788DD95D16B8F914DDDFC3EE5C69945DF7D7BF31C6072BFA7993996AB7DD2F3EE4009844CC9D6CF9E583AEC48A52F2904B57D8E0D755851232838F9B5348838530D7AF95411555D263B8CA86A5D29D7CE4B65409D6F04C5709A56C241C3BCEF07459A416EB4E8F3D73CC714F4333AFE605D53A5C955D5D1412F8361617A54446971FD187442A60FB04457857BECC3120A01FDC7FE2CBF038A61DEE5FCE2D10C8F35FBF80C05ABFF4B6935287B125E8D56F9FDFE7D64C1F4E1F5641845CD17E836B97780400C702523FA8E7C7BBD6F0666591A35ADD26B6B7E33CA56E9AB329EFA7E68F98AE7CE9507755C74C430286A; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h88537A811D4EF6CD9668CCD3E2E7A8041788DCA5F7E08AF52AF5276078304DEB75B74BB9AC3C1A492952F7EEAA0E7CF9FBEDD0FB47EEFDCC3734B816F355C913CD2E1AF14C30545297A91BED3AEAEFF8F696B5F4FC80BC6B1A2559492E9198E4A5875745B625C6CA7A7292332492D139728A689DA1AE78B6B44CE4F4A4EA5A22F331598B364EF27516CC49A4662C5E5C92ED140D96373678F833AE434698237599716B8CBAE2D3D061F2C3D6337AB435B5C2144AB6FA2F8BB51357801066B6589467DA6C480E6D19CEEA8451CEFA88FD70E7925B0302F877F87FA833FBD147E937309C08305A10187707E3D57DDE4931F1D9E97A8F378981ABBF8D7B6B7539C3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h763DD7AA7EED3F4AD4EA7491ADE6F14E6DBADD0F090A8DF34D7BAD35DD2275F0BCCF19EEF299751C919C9C13C6FB9ED711AC4DA7D947CC79E9B6323EF6CE62638CEBCB187AE5D44ECA689C9BD4E5AE544DEA7E90D186B9F335F3323877AAD54196CE81973CB555904419599375501366EC343561BCF83357F8823671393B278C1C387A7970C7F3E688673CF5975EE3E5FF105CFCCFAB725D698FB088B063063C7833830C7B2C7AFB8A8D203C312306DA0E72641FFB93D59B5EC84F44AD55F4B884735325ACC969B2EAE10A1478D866F667DDEF7BBF75E6958B6D02DC6D0F807660A229B98541E6FE734DE2280A9B57FCD5A9BEFEF7CDA5ABEB44FD73D2794D56; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'hD0734B461A36980411EB2A6C1BE76029258777EF227A8F6E84F74C4436098F67BA611013110188547995B108BB2DAE76F423A0D98845F9248BDFA45E10CA403A5E2B1A3E16869E1D37BCE906B82F401CBD467617DB34D9E0C80B5E6E10063EC4BD52921D249E377D95CFAAA309EEDAA57DA85F55DBB7048A69A4C801013948B617F7F5724D40707E6FF30002982023020449B4680C45D1CE6D8EB30A061DB8FEDD6E630C15271E48CA801988654FB501D5393392EE765C1EC95C1E4D86F18A965372B72B484E2F2664B735B69A5AB532B086BA4C62AD6D56EECBDB6984B251454845BD5B243DAED2B2489B313A35C50252AFD3E0B76FEF342335C7F1321D92FF; +// synopsys translate_on + +// Location: LCCOMB_X23_Y14_N28 +cycloneive_lcell_comb \Selector2~1 ( +// Equation(s): +// \Selector2~1_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\Selector2~0_combout )))) # (!\z80_|address_pins_|abus[14]~23_combout & ((\Selector2~0_combout & (\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout )) # +// (!\Selector2~0_combout & ((\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ))))) + + .dataa(\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ), + .datab(\z80_|address_pins_|abus[14]~23_combout ), + .datac(\Selector2~0_combout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ), + .cin(gnd), + .combout(\Selector2~1_combout ), + .cout()); +// synopsys translate_off +defparam \Selector2~1 .lut_mask = 16'hE3E0; +defparam \Selector2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y14_N30 +cycloneive_lcell_comb \D[0]~83 ( +// Equation(s): +// \D[0]~83_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [15] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~5_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\Selector2~1_combout +// ))))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~5_combout )) + + .dataa(\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~5_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [15]), + .datad(\Selector2~1_combout ), + .cin(gnd), + .combout(\D[0]~83_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~83 .lut_mask = 16'hAEA2; +defparam \D[0]~83 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y14_N14 +cycloneive_lcell_comb \D[0]~45 ( +// Equation(s): +// \D[0]~45_combout = ((\Equal2~0_combout & (\D[0]~44_combout )) # (!\Equal2~0_combout & ((\D[0]~83_combout )))) # (!\Equal2~1_combout ) + + .dataa(\Equal2~0_combout ), + .datab(\D[0]~44_combout ), + .datac(\D[0]~83_combout ), + .datad(\Equal2~1_combout ), + .cin(gnd), + .combout(\D[0]~45_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~45 .lut_mask = 16'hD8FF; +defparam \D[0]~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y14_N0 +cycloneive_lcell_comb \D[0]~46 ( +// Equation(s): +// \D[0]~46_combout = (\z80_|pin_control_|bus_db_pin_oe~15_combout & (((\D[0]~45_combout & \z80_|data_pins_|dout [0])))) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout & (((\D[0]~45_combout )) # (!\Equal2~1_combout ))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .datab(\Equal2~1_combout ), + .datac(\D[0]~45_combout ), + .datad(\z80_|data_pins_|dout [0]), + .cin(gnd), + .combout(\D[0]~46_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~46 .lut_mask = 16'hF151; +defparam \D[0]~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N26 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [0] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[0]~17_combout ) # ((\D[0]~46_combout & \z80_|pin_control_|bus_db_pin_re~combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & +// (\D[0]~46_combout & ((\z80_|pin_control_|bus_db_pin_re~combout )))) + + .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datab(\D[0]~46_combout ), + .datac(\z80_|bus_control_|db[0]~17_combout ), + .datad(\z80_|pin_control_|bus_db_pin_re~combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [0]), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] .lut_mask = 16'hECA0; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y13_N27 +dffeas \z80_|data_pins_|dout[0] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [0]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|data_pins_|dout [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|data_pins_|dout[0] .is_wysiwyg = "true"; +defparam \z80_|data_pins_|dout[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N10 +cycloneive_lcell_comb \z80_|bus_control_|db[0]~16 ( +// Equation(s): +// \z80_|bus_control_|db[0]~16_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [0]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) + + .dataa(\z80_|data_pins_|dout [0]), + .datab(\z80_|bus_control_|db[0]~4_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|bus_control_|db[0]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[0]~16 .lut_mask = 16'h8C8C; +defparam \z80_|bus_control_|db[0]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N0 +cycloneive_lcell_comb \z80_|bus_control_|db[0]~17 ( +// Equation(s): +// \z80_|bus_control_|db[0]~17_combout = ((\z80_|bus_control_|db[0]~16_combout & ((\z80_|alu_control_|db[0]~12_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) + + .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datab(\z80_|alu_control_|db[0]~12_combout ), + .datac(\z80_|bus_control_|db[0]~6_combout ), + .datad(\z80_|bus_control_|db[0]~16_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[0]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[0]~17 .lut_mask = 16'hDF0F; +defparam \z80_|bus_control_|db[0]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y13_N1 +dffeas \z80_|ir_|opcode[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|bus_control_|db[0]~17_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|ir_|opcode [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|ir_|opcode[0] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal3~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal3~2_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal52~0_combout & \z80_|pla_decode_|Equal3~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal3~1_combout ), + .datac(\z80_|pla_decode_|Equal52~0_combout ), + .datad(\z80_|pla_decode_|Equal3~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal3~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal3~2 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal3~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal43~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal43~0_combout = (\z80_|pla_decode_|Equal1~7_combout & (\z80_|pla_decode_|Equal32~0_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal3~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal1~7_combout ), + .datab(\z80_|pla_decode_|Equal32~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal3~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal43~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal43~0 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal43~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N24 +cycloneive_lcell_comb \z80_|interrupts_|test1~2 ( +// Equation(s): +// \z80_|interrupts_|test1~2_combout = (!\z80_|pla_decode_|Equal3~2_combout & (!\z80_|pla_decode_|Equal43~0_combout & (!\z80_|pla_decode_|Equal79~0_combout & !\z80_|pla_decode_|Equal36~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal3~2_combout ), + .datab(\z80_|pla_decode_|Equal43~0_combout ), + .datac(\z80_|pla_decode_|Equal79~0_combout ), + .datad(\z80_|pla_decode_|Equal36~0_combout ), + .cin(gnd), + .combout(\z80_|interrupts_|test1~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|test1~2 .lut_mask = 16'h0001; +defparam \z80_|interrupts_|test1~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N22 +cycloneive_lcell_comb \z80_|interrupts_|test1~3 ( +// Equation(s): +// \z80_|interrupts_|test1~3_combout = (!\z80_|execute_|setM1~54_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (\z80_|interrupts_|test1~2_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|execute_|setM1~54_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|interrupts_|test1~2_combout ), + .cin(gnd), + .combout(\z80_|interrupts_|test1~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|test1~3 .lut_mask = 16'h3331; +defparam \z80_|interrupts_|test1~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y13_N1 +dffeas \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|interrupts_|test1~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED .is_wysiwyg = "true"; +defparam \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N6 +cycloneive_lcell_comb \z80_|clk_delay_|SYNTHESIZED_WIRE_4 ( +// Equation(s): +// \z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (!\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|interrupts_|DFFE_inst44~q ))) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|interrupts_|DFFE_inst44~q ), + .cin(gnd), + .combout(\z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_4 .lut_mask = 16'h0100; +defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y14_N7 +dffeas \z80_|clk_delay_|SYNTHESIZED_WIRE_7 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_7 .is_wysiwyg = "true"; +defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_7 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N12 +cycloneive_lcell_comb \z80_|clk_delay_|hold_clk_iorq ( +// Equation(s): +// \z80_|clk_delay_|hold_clk_iorq~combout = (!\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q & !\z80_|clk_delay_|DFF_inst5~q ) + + .dataa(\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ), + .datab(\z80_|clk_delay_|DFF_inst5~q ), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\z80_|clk_delay_|hold_clk_iorq~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|clk_delay_|hold_clk_iorq .lut_mask = 16'h1111; +defparam \z80_|clk_delay_|hold_clk_iorq .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y13_N31 +dffeas \z80_|sequencer_|DFFE_T4_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_T4_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_T4_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_T4_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_eval_cond~0 ( +// Equation(s): +// \z80_|execute_|ctl_eval_cond~0_combout = (\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_eval_cond~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_eval_cond~0 .lut_mask = 16'h00F0; +defparam \z80_|execute_|ctl_eval_cond~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~27 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~27_combout = (\z80_|execute_|ctl_mRead~23_combout & (((!\z80_|pla_decode_|Equal38~2_combout & !\z80_|pla_decode_|Equal52~1_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|pla_decode_|Equal38~2_combout ), + .datac(\z80_|execute_|ctl_mRead~23_combout ), + .datad(\z80_|pla_decode_|Equal52~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~27 .lut_mask = 16'h5070; +defparam \z80_|execute_|ctl_mRead~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~26 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~26_combout = (\z80_|execute_|ctl_mRead~34_combout ) # ((\z80_|pla_decode_|Equal21~1_combout ) # (\z80_|pla_decode_|Equal37~0_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|pla_decode_|Equal37~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~26 .lut_mask = 16'hFFFC; +defparam \z80_|execute_|ctl_mRead~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y17_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~28 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~28_combout = (\z80_|execute_|ctl_mRead~27_combout & (\z80_|execute_|ctl_mRead~22_combout & ((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|execute_|ctl_mRead~26_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~27_combout ), + .datab(\z80_|execute_|ctl_mRead~26_combout ), + .datac(\z80_|execute_|ctl_mRead~22_combout ), + .datad(\z80_|execute_|ctl_mRead~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~28 .lut_mask = 16'h20A0; +defparam \z80_|execute_|ctl_mRead~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|nextM~6 ( +// Equation(s): +// \z80_|execute_|nextM~6_combout = (((\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal49~0_combout )) # (!\z80_|execute_|nextM~3_combout )) # (!\z80_|execute_|ixy_d~17_combout ) + + .dataa(\z80_|decode_state_|use_ixiy~combout ), + .datab(\z80_|execute_|ixy_d~17_combout ), + .datac(\z80_|execute_|nextM~3_combout ), + .datad(\z80_|pla_decode_|Equal49~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~6 .lut_mask = 16'hBF3F; +defparam \z80_|execute_|nextM~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N10 +cycloneive_lcell_comb \z80_|execute_|nextM~7 ( +// Equation(s): +// \z80_|execute_|nextM~7_combout = ((\z80_|execute_|nextM~6_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # (\z80_|execute_|ixy_d~8_combout )))) # (!\z80_|execute_|nextM~4_combout ) + + .dataa(\z80_|execute_|nextM~6_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|execute_|ixy_d~8_combout ), + .datad(\z80_|execute_|nextM~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~7 .lut_mask = 16'hA8FF; +defparam \z80_|execute_|nextM~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|nextM~8 ( +// Equation(s): +// \z80_|execute_|nextM~8_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & (((\z80_|execute_|ixy_d~8_combout & !\z80_|execute_|ctl_flags_bus~1_combout )) # (!\z80_|alu_control_|flags_cond_true~q ))) # +// (!\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & (\z80_|execute_|ixy_d~8_combout & ((!\z80_|execute_|ctl_flags_bus~1_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), + .datab(\z80_|execute_|ixy_d~8_combout ), + .datac(\z80_|alu_control_|flags_cond_true~q ), + .datad(\z80_|execute_|ctl_flags_bus~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~8 .lut_mask = 16'h0ACE; +defparam \z80_|execute_|nextM~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|nextM~9 ( +// Equation(s): +// \z80_|execute_|nextM~9_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_mWrite~4_combout & ((\z80_|execute_|ctl_mRead~9_combout ) # (\z80_|execute_|ixy_d~6_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~9_combout ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ctl_mWrite~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~9 .lut_mask = 16'hC800; +defparam \z80_|execute_|nextM~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|nextM~10 ( +// Equation(s): +// \z80_|execute_|nextM~10_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ) # ((\z80_|execute_|nextM~9_combout ) # ((\z80_|execute_|ctl_mRead~34_combout & \z80_|execute_|ixy_d~9_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|execute_|nextM~9_combout ), + .datad(\z80_|execute_|ixy_d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~10 .lut_mask = 16'hFEFA; +defparam \z80_|execute_|nextM~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N20 +cycloneive_lcell_comb \z80_|execute_|nextM~12 ( +// Equation(s): +// \z80_|execute_|nextM~12_combout = (\z80_|execute_|nextM~8_combout ) # ((\z80_|execute_|ctl_alu_op_low~46_combout ) # ((\z80_|execute_|nextM~10_combout ) # (!\z80_|execute_|nextM~11_combout ))) + + .dataa(\z80_|execute_|nextM~8_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~46_combout ), + .datac(\z80_|execute_|nextM~10_combout ), + .datad(\z80_|execute_|nextM~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~12 .lut_mask = 16'hFEFF; +defparam \z80_|execute_|nextM~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|nextM~15 ( +// Equation(s): +// \z80_|execute_|nextM~15_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & ((\z80_|execute_|ctl_mRead~5_combout ) # (!\z80_|execute_|fMRead~12_combout )))) + + .dataa(\z80_|execute_|fMRead~12_combout ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|execute_|ctl_mRead~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~15 .lut_mask = 16'hC040; +defparam \z80_|execute_|nextM~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|nextM~13 ( +// Equation(s): +// \z80_|execute_|nextM~13_combout = (\z80_|execute_|nextM~7_combout ) # ((\z80_|execute_|nextM~12_combout ) # (\z80_|execute_|nextM~15_combout )) + + .dataa(\z80_|execute_|nextM~7_combout ), + .datab(\z80_|execute_|nextM~12_combout ), + .datac(gnd), + .datad(\z80_|execute_|nextM~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~13 .lut_mask = 16'hFFEE; +defparam \z80_|execute_|nextM~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N6 +cycloneive_lcell_comb \z80_|execute_|setM1~41 ( +// Equation(s): +// \z80_|execute_|setM1~41_combout = (\z80_|execute_|setM1~40_combout & !\z80_|execute_|ctl_mWrite~7_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|setM1~40_combout ), + .datac(\z80_|execute_|ctl_mWrite~7_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|setM1~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~41 .lut_mask = 16'h0C0C; +defparam \z80_|execute_|setM1~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|nextM~5 ( +// Equation(s): +// \z80_|execute_|nextM~5_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (((!\z80_|execute_|setM1~41_combout ) # (!\z80_|execute_|setM1~47_combout )) # (!\z80_|execute_|nextM~2_combout ))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|nextM~2_combout ), + .datac(\z80_|execute_|setM1~47_combout ), + .datad(\z80_|execute_|setM1~41_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~5 .lut_mask = 16'h2AAA; +defparam \z80_|execute_|nextM~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N0 +cycloneive_lcell_comb \z80_|execute_|nextM~14 ( +// Equation(s): +// \z80_|execute_|nextM~14_combout = (((\z80_|execute_|nextM~13_combout ) # (\z80_|execute_|nextM~5_combout )) # (!\z80_|execute_|ctl_mWrite~14_combout )) # (!\z80_|execute_|ctl_mRead~28_combout ) + + .dataa(\z80_|execute_|ctl_mRead~28_combout ), + .datab(\z80_|execute_|ctl_mWrite~14_combout ), + .datac(\z80_|execute_|nextM~13_combout ), + .datad(\z80_|execute_|nextM~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~14 .lut_mask = 16'hFFF7; +defparam \z80_|execute_|nextM~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N24 +cycloneive_lcell_comb \z80_|sequencer_|ena_M ( +// Equation(s): +// \z80_|sequencer_|ena_M~combout = (\z80_|execute_|setM1~54_combout & !\z80_|execute_|nextM~14_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|setM1~54_combout ), + .datac(gnd), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|ena_M~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|ena_M .lut_mask = 16'h00CC; +defparam \z80_|sequencer_|ena_M .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y13_N25 +dffeas \z80_|sequencer_|DFFE_T1_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|ena_M~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_T1_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_T1_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_T1_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N20 +cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_13 ( +// Equation(s): +// \z80_|sequencer_|SYNTHESIZED_WIRE_13~combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|execute_|setM1~54_combout & !\z80_|execute_|nextM~14_combout )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|execute_|setM1~54_combout ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_13 .lut_mask = 16'h0030; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y13_N21 +dffeas \z80_|sequencer_|DFFE_T2_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_T2_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_T2_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_T2_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N16 +cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_14 ( +// Equation(s): +// \z80_|sequencer_|SYNTHESIZED_WIRE_14~combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|execute_|setM1~54_combout & !\z80_|execute_|nextM~14_combout )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|execute_|setM1~54_combout ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_14 .lut_mask = 16'h00C0; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y13_N17 +dffeas \z80_|sequencer_|DFFE_T3_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_T3_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_T3_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_T3_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout = (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 .lut_mask = 16'h0F00; +defparam \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_66_oe~2 ( +// Equation(s): +// \z80_|execute_|ctl_66_oe~2_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|execute_|comb~0_combout & \z80_|ir_|opcode [0]))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|pla_decode_|Equal52~0_combout ), + .datac(\z80_|execute_|comb~0_combout ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_66_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_66_oe~2 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_66_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y17_N11 +dffeas \z80_|interrupts_|im1 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_im_we~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|interrupts_|im1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|interrupts_|im1 .is_wysiwyg = "true"; +defparam \z80_|interrupts_|im1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_ff_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_bus_ff_oe~0_combout = (\z80_|interrupts_|DFFE_inst44~q & ((\z80_|interrupts_|im1~q ) # ((\z80_|interrupts_|im2~q & !\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) + + .dataa(\z80_|interrupts_|DFFE_inst44~q ), + .datab(\z80_|interrupts_|im2~q ), + .datac(\z80_|interrupts_|im1~q ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_ff_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_ff_oe~0 .lut_mask = 16'hA0A8; +defparam \z80_|execute_|ctl_bus_ff_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_ff_oe~1 ( +// Equation(s): +// \z80_|execute_|ctl_bus_ff_oe~1_combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) # (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|execute_|ctl_bus_ff_oe~0_combout & +// ((\z80_|execute_|ctl_66_oe~2_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) + + .dataa(\z80_|execute_|ctl_66_oe~2_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datad(\z80_|execute_|ctl_bus_ff_oe~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_ff_oe~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_ff_oe~1 .lut_mask = 16'h3B30; +defparam \z80_|execute_|ctl_bus_ff_oe~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_zero_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_bus_zero_oe~0_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_iorw~10_combout ) # (\z80_|execute_|ctl_alu_op_low~27_combout )))) + + .dataa(\z80_|pla_decode_|Equal33~1_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_iorw~10_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_zero_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_zero_oe~0 .lut_mask = 16'h8880; +defparam \z80_|execute_|ctl_bus_zero_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N18 +cycloneive_lcell_comb \z80_|bus_control_|db[0]~4 ( +// Equation(s): +// \z80_|bus_control_|db[0]~4_combout = (\z80_|execute_|ctl_bus_ff_oe~1_combout ) # ((!\z80_|execute_|ctl_bus_zero_oe~0_combout & ((\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) # (!\z80_|decode_state_|in_halt~q )))) + + .dataa(\z80_|execute_|ctl_bus_ff_oe~1_combout ), + .datab(\z80_|execute_|ctl_bus_zero_oe~0_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|decode_state_|in_halt~q ), + .cin(gnd), + .combout(\z80_|bus_control_|db[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[0]~4 .lut_mask = 16'hBABB; +defparam \z80_|bus_control_|db[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N24 +cycloneive_lcell_comb \z80_|bus_control_|db[6]~8 ( +// Equation(s): +// \z80_|bus_control_|db[6]~8_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[6]~22_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) + + .dataa(\z80_|bus_control_|db[0]~4_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datad(\z80_|alu_control_|db[6]~22_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[6]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[6]~8 .lut_mask = 16'hAA0A; +defparam \z80_|bus_control_|db[6]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y7_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a22 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~79_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_first_bit_number = 6; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y8_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a30 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~79_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_first_bit_number = 6; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y11_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a14 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~79_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y10_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a6 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~79_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N16 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ) # +// ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout & +// !\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12 .lut_mask = 16'hF0AC; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y10_N22 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13_combout = (\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout & (((\ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout & +// ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout ), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13 .lut_mask = 16'hCAF0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y1_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a6 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h3C766E63DB6481CB39BC8C68831C724633186CC1BAE9D608A5DEF0FF219C28C1EFF4FDE394D0E19B6FD89186C23CF071E6F1CC8F7FC4F1E48756B0DCD8ED6D0C3DA139003D7A86B2F878DD99DAFB70DE1A19F3FB7DB3B8EF2633007664CB19992E43664448EFF06072648DBA32EDB76E26439BCCEF2DFBF664594B04FBAE72A84A3E508B49DC6BEAAB4F3F0CCCF6D8F568F2DA00EB384A7F53249323198000100408002024010408824080002008011482ED5615E40012EE630C3B2CDB2C13A736DB5B7BD2850018CF936621C6863095A73F7BE7442CB13110B9C0BBB96EEF16CE618EEDCFB393738178C476C367909F71307F6803F677575763DB2D8C3118E4; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h881331ED7AC4EFD38DFACDBB236790005719AEA2FAECCF0D126A30A27222D61BBA428334561F4EDB60C6BF8DB6E267BC56CB69BBCE636CCCB3B2B4B103CC46D5CEEC06DAECB0001569589D5F267AFE086C8FED5DE41DFEFF027DFDFF7FFBFBFDFFDFFF6FFFBDFFDFFF57FF7F7FB7FBBDFBDFFDBFF78FFDBFFEDDFFFDFFFEFF6FF7F7FDDFFEDFF6FF7FFEEFFEFEFC4E51EC0888848E1F2044B47B66608D8A3B3919B9466E6D60D27565964244B218B48AD83430D996068EC908D9E112096996041D77401A0C0CCF5DEEE561F7F7E68CBE72E48E570B047C772CBACC33753080E32EB0B348C0B62337739B1BC73192392592C84E37B7AC141CFE65EE76D83C9083; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h1C5CF062CA6F13854A59BDEEEA07E3C6559EBB3618111895CBBACCBCD512B5F07D361CCE72B925658DBE1F7C4707E195C5C665B8118C3C31B196C261DA85A5E11889D25CB816ACC6627802052C61A4099B7B0EC923971DB3B9F9204BDBCCFA457EE296E8986E64C6DC99E59436641567648CB84DEB7D7937F974F038D838274F3D3CF1BE8C84DDB000565880A776E5C0E13166E49F47119A4CA1311CF97B965E7CBBCB2CB384BD0D92ED105D0617856E80441124B31DE58B8C001607FEE668899693E3EFF8FBF1FCEEFBCF7CF9BA6C37640DDF7FFE6187B19ACF089D4C038F6607B78D38001FE67E56CCE399DE36D7DDBD699D5CFC5B6D7A1421CE06FE40DB6E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h0776C62C316FF94B0BC3A0288DE6A62B14D6C1A2DADF9BDF85B2CCB02CE1DB2D96632C3232C3974CDC1172E1779D8C6738251819975DB8146067301E0C0277B6B657485DCD62AC0662C8C005DDE7494C9CA13AAE3234BB0EE1B708A23A2F48AC4C3838641E940620F9CDDCCA14BCC07104C112BCC9032C48E925594CB886A604C9F7627EB100872A52FB5141D65111E6C8DA0ADB6CEC6004461D0E366B20DCCDB607E624499300E4DF6D95CB62F62FB75403E400EFBC3BD34080FC9CDCFCFCFFFFFFFFFFFFFFFFFFFFF7BFFFFFFFFFFFFFFFFFFFFFFFFFFFCF9FFFFFEFFFF81FFDDFFFFFFFFFFFFFF7FFBFFFBFDC0A6DBE6F8BE5BB7FE7A39B3DA3F3BE13B679; +// synopsys translate_on + +// Location: M9K_X22_Y4_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a14 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h4200420000441C443C0C3C00480018FC387C7C000000007E180038300000204880084204004204423E1E3E02247E3C7E3C7E7E7E7E30007E3C7E7E7E3C7E7C3C0400000000000C34023C2E302464003C00000000000000000020460024000000FF991E65536D2D8D9C9B4DB081C83A5A881B0DFDE2D72DF0FA08FCD6F664173D989098D02025E0F6043B4B9080F4923880C3A3B02D269E730C3DCC423386DCB98B4AD0C5C8D6119602E5121008325B7457090E914F4876EC8A18C664210A4C2392C7658400073421047C75FBE7BE73FDFFF05FEE07BF8AEF7F1378B359E8C61F8F692C2218C98A4A8748531986E7C770D984E0000C02060C000C0DF50F68A580; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h0100046606572583002086010800054C0F2DE8371AC0000A9003E024840C7C0806F6612D770080980A40D293FEC069F16CB2164CA033C539F69B37741AEF1CE3662FF5DF9CB107BB23A39EF7B95E7372200448DBDC18F9C0DE0EF379BF49480657781E91788044213E091339886F337D0612CA646CD48FC58EE77EDD7ECEC466C744FD00E1A7F9E9FBFE4777FD50ABD11F0E57FF4808802282200888A20AA88000000008800AC11D556264251ECFA68C056FBCCB040C614A6850222300D2F6FF59F878FCF5689FCFEF34BFD52FA2422A56A3C113409F7813007F8D6B5F80FE9D7FB1E62675F7C2CBE01032DCA16BADC570C1CBF7ECBC4E7E6C54A5D4550BE1A8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'hE33CB578DEBFAFAEDFD530DE8FA1992072F31B116644B18C72F9F44116C79ADF2F3982C7BE09AD4A32196807648A2495ADF98FD2B16CC096A5E25F5BC811C953CEC3000F432029B3FE3F211712944CA54D1940F193204C199C9F49666CC11B38C23B9D130CA49818913D3A2C1FBF71C5B0C774336F903C677D976189D98CA127AAAD6B6AF36195DA637C6EFA3E36E8FE97FA02EC26EB46198AD8DAD8C11260AF499D7BD86619EE5574CD27C80D39F71E653FDCF1B366737233CBB98D1E7B330F7DCCFC5939C4EC79CF0E1CD43BA7AFC716900A21BDB9DD0FCC7ECE1063238407C7E1B221EA10E38F64EF31CEBF3368E1C712BB1B33781134CFE54C2123349A6E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h5F9CB25A3631964C20007FF5754FC631A97D4F93986C30CF24394625658DE9A7C228A2050470925E29A35D8D06242712CD25C9241898204D85A710947C802013E1265727652C8F0C422BA8C28A0FBB893B0881E00403DDD8843B2D8EB929D0D8CB76E03779E019E2C4E4028219C38C202C9384E0D24E569C2E4D4D60B670CE37414D536A41D144B6C4624A2B00366D8CF6734A4A2DC465B308462CCBD1BF9CB863FC93EDB2CA5DC61B01639318985C88F01680E307C42311C0124700B28BF9B4FF7CCCEFE1996DE3ED6D8CFBF1871BD98EE7646242664EB2E338BD009838637124C921BB3332DC66D9C1706B6C48C3129639A3BA4088EDB496EDBBBFC2CC40B6; +// synopsys translate_on + +// Location: M9K_X22_Y23_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a14 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(gnd), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~79_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_first_bit_number = 6; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y26_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a6 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~79_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_first_bit_number = 6; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFFFFFEBFFFFFFFFFFFFFFFFFFFFFFFBFFFFFFFFFFFFFFFFFDFFFFFFFFFFFFFBFFFFFFFFFEFFFFFFFDFFFFFFFFFFFFFEFFFFFFFDF8FFFFFFF9FFFFFFFFFFFFFFFF3FFFFFFE7FFFFFFFFFFFFFFFF; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000380001887600094C977486989000000000000000000000000FFFFFFFFC0810205C00018C36DC09CF97749EDCD00000000000000000000000000000001FFFFFFFDC004000B6D028BF17749ED8100000000000000000000000000000001BF7EFDF9400404A96D8289B57549FFC10000000000000000000000003F7EFDF90000000140041EB16D8298357DC9F7410000000000000000000000007FFFFFFD8000000340043AB160021E757DC9134100000000000000000000000040810207BFFFFFFF5FE430497702760D60099349000000000000000000000000408102073FFFFFFD5FE40E49774240C96009735D; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h5FE8334948F827C15FF88F8169A80ECB609EAD417A698FC178F33E8171F72A915FE836E948F807C95FF88F81E9A80FC7639E1FC17B2BBEC170730F8D70F7B0C1400826E548B807C95FF88F95E8280FCB63C6BCC17B3B3FC171AB3E81708734C1400826ED58F8258159F88B8168280FC161629DC17A3B3F41738B3F8150AF16E9400826ED581805C151D88A8160682FC1422297C17A2A39C162FB378550CF10A1400826ED58182581D1580B8761EC2FC14232B7C179AA39C5627B7781D0CF10D3400826E158182D81F0488A4B61EC0DC143789FC17BBB39C1610B7F81D45F11D34008A7E958080D01F0088A4160B42DD143689FC17B9B398561837F81D41702B1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h50DF086350368F0151C688016801460157EDE81148F310013FFFFFFF40810103D2D70D4B50168F0141D6C8116C01462153EDA90148F31D01BFFFFFFF40810107D2D7296354D68501403EC0016C01482173FDA08148F11F01800000037FFFFFFD4297893154DE81054022D2116C014D6153FCA00148D10F01000000013F7EFEF9429F810150CEC10143E042016C014C09537DA00148D11F01BF7EFEF900000001469F833150168D0543E04A116F014DA15379B181C8511F03FFFFFFFD00000001449AAB2155368D01482046016F416CA15079B001C8513E03C0810105FFFFFFFF403A8B0155C685014800461167476CA15039B08180413E0500000007FFFFFFFF; +// synopsys translate_on + +// Location: LCCOMB_X24_Y10_N16 +cycloneive_lcell_comb \Selector6~0 ( +// Equation(s): +// \Selector6~0_combout = (\z80_|address_pins_|abus[14]~23_combout & ((\Selector3~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout )) # (!\Selector3~0_combout & +// ((\ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ))))) # (!\z80_|address_pins_|abus[14]~23_combout & (\Selector3~0_combout )) + + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\Selector3~0_combout ), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ), + .cin(gnd), + .combout(\Selector6~0_combout ), + .cout()); +// synopsys translate_off +defparam \Selector6~0 .lut_mask = 16'hE6C4; +defparam \Selector6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y10_N18 +cycloneive_lcell_comb \Selector6~1 ( +// Equation(s): +// \Selector6~1_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\Selector6~0_combout )))) # (!\z80_|address_pins_|abus[14]~23_combout & ((\Selector6~0_combout & ((\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ))) # +// (!\Selector6~0_combout & (\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout )))) + + .dataa(\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ), + .datab(\z80_|address_pins_|abus[14]~23_combout ), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .datad(\Selector6~0_combout ), + .cin(gnd), + .combout(\Selector6~1_combout ), + .cout()); +// synopsys translate_off +defparam \Selector6~1 .lut_mask = 16'hFC22; +defparam \Selector6~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y10_N4 +cycloneive_lcell_comb \D[6]~88 ( +// Equation(s): +// \D[6]~88_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\Selector6~1_combout +// ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13_combout )))) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13_combout ), + .datad(\Selector6~1_combout ), + .cin(gnd), + .combout(\D[6]~88_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~88 .lut_mask = 16'hF4B0; +defparam \D[6]~88 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X16_Y34_N8 +cycloneive_io_ibuf \raw_loader_in~input ( + .i(raw_loader_in), + .ibar(gnd), + .o(\raw_loader_in~input_o )); +// synopsys translate_off +defparam \raw_loader_in~input .bus_hold = "false"; +defparam \raw_loader_in~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y10_N24 +cycloneive_lcell_comb \D[6]~69 ( +// Equation(s): +// \D[6]~69_combout = ((\z80_|address_pins_|DFFE_apin_latch [0]) # (\raw_loader_in~input_o )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [0]), + .datad(\raw_loader_in~input_o ), + .cin(gnd), + .combout(\D[6]~69_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~69 .lut_mask = 16'hFFF3; +defparam \D[6]~69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y10_N0 +cycloneive_lcell_comb \D[6]~78 ( +// Equation(s): +// \D[6]~78_combout = ((\Equal2~0_combout & ((\D[6]~69_combout ))) # (!\Equal2~0_combout & (\D[6]~88_combout ))) # (!\Equal2~1_combout ) + + .dataa(\Equal2~0_combout ), + .datab(\Equal2~1_combout ), + .datac(\D[6]~88_combout ), + .datad(\D[6]~69_combout ), + .cin(gnd), + .combout(\D[6]~78_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~78 .lut_mask = 16'hFB73; +defparam \D[6]~78 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y10_N6 +cycloneive_lcell_comb \D[6]~79 ( +// Equation(s): +// \D[6]~79_combout = (\z80_|pin_control_|bus_db_pin_oe~15_combout & (\z80_|data_pins_|dout [6] & ((\D[6]~78_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout & (((\D[6]~78_combout ) # (!\Equal2~1_combout )))) + + .dataa(\z80_|data_pins_|dout [6]), + .datab(\Equal2~1_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .datad(\D[6]~78_combout ), + .cin(gnd), + .combout(\D[6]~79_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~79 .lut_mask = 16'hAF03; +defparam \D[6]~79 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N18 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [6] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[6]~9_combout ) # ((\z80_|pin_control_|bus_db_pin_re~combout & \D[6]~79_combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & +// (\z80_|pin_control_|bus_db_pin_re~combout & (\D[6]~79_combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datab(\z80_|pin_control_|bus_db_pin_re~combout ), + .datac(\D[6]~79_combout ), + .datad(\z80_|bus_control_|db[6]~9_combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [6]), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] .lut_mask = 16'hEAC0; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y13_N19 +dffeas \z80_|data_pins_|dout[6] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [6]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|data_pins_|dout [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|data_pins_|dout[6] .is_wysiwyg = "true"; +defparam \z80_|data_pins_|dout[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N6 +cycloneive_lcell_comb \z80_|bus_control_|db[6]~9 ( +// Equation(s): +// \z80_|bus_control_|db[6]~9_combout = ((\z80_|bus_control_|db[6]~8_combout & ((\z80_|data_pins_|dout [6]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) + + .dataa(\z80_|bus_control_|db[0]~6_combout ), + .datab(\z80_|bus_control_|db[6]~8_combout ), + .datac(\z80_|data_pins_|dout [6]), + .datad(\z80_|execute_|ctl_bus_db_oe~combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[6]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[6]~9 .lut_mask = 16'hD5DD; +defparam \z80_|bus_control_|db[6]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y13_N7 +dffeas \z80_|ir_|opcode[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|bus_control_|db[6]~9_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|ir_|opcode [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|ir_|opcode[6] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~10 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~10_combout = (!\z80_|ir_|opcode [6] & (\z80_|ir_|opcode [7] & (\z80_|execute_|ctl_ir_we~5_combout & !\z80_|pla_decode_|Equal46~0_combout ))) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|execute_|ctl_ir_we~5_combout ), + .datad(\z80_|pla_decode_|Equal46~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~10 .lut_mask = 16'h0040; +defparam \z80_|execute_|ctl_ir_we~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~0_combout = (\z80_|execute_|ctl_alu_bs_oe~6_combout & (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~7_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~10_combout ), + .datab(\z80_|execute_|ctl_ir_we~7_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~6_combout ), + .datad(\z80_|execute_|ctl_ir_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~0 .lut_mask = 16'h10F0; +defparam \z80_|execute_|ctl_bus_db_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~4 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~4_combout = (!\z80_|execute_|ctl_bus_db_oe~3_combout ) # (!\z80_|execute_|ctl_bus_db_oe~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_bus_db_oe~0_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~4 .lut_mask = 16'h0FFF; +defparam \z80_|execute_|ctl_bus_db_oe~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~2 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~2_combout = (!\z80_|execute_|ctl_bus_ff_oe~1_combout & (!\z80_|execute_|ctl_bus_zero_oe~0_combout & ((\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) # (!\z80_|decode_state_|in_halt~q )))) + + .dataa(\z80_|execute_|ctl_bus_ff_oe~1_combout ), + .datab(\z80_|execute_|ctl_bus_zero_oe~0_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|decode_state_|in_halt~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~2 .lut_mask = 16'h1011; +defparam \z80_|execute_|ctl_bus_db_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y17_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~5 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~5_combout = (\z80_|execute_|ctl_ir_we~8_combout ) # ((\z80_|pla_decode_|Equal41~2_combout ) # ((\z80_|execute_|ctl_ir_we~14_combout ) # (\z80_|execute_|ctl_ir_we~11_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|pla_decode_|Equal41~2_combout ), + .datac(\z80_|execute_|ctl_ir_we~14_combout ), + .datad(\z80_|execute_|ctl_ir_we~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~5 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_bus_db_oe~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~6 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~6_combout = ((\z80_|execute_|ctl_66_oe~2_combout ) # ((\z80_|execute_|ctl_bus_db_oe~5_combout & \z80_|execute_|ctl_ir_we~4_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|execute_|ctl_bus_db_oe~5_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|execute_|ctl_66_oe~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~6 .lut_mask = 16'hFFD5; +defparam \z80_|execute_|ctl_bus_db_oe~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~combout = (\z80_|execute_|ctl_bus_db_oe~2_combout & ((\z80_|execute_|ctl_bus_db_oe~4_combout ) # ((\z80_|execute_|ctl_bus_db_oe~6_combout ) # (!\z80_|execute_|ctl_sw_1d~6_combout )))) + + .dataa(\z80_|execute_|ctl_bus_db_oe~4_combout ), + .datab(\z80_|execute_|ctl_bus_db_oe~2_combout ), + .datac(\z80_|execute_|ctl_sw_1d~6_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe .lut_mask = 16'hCC8C; +defparam \z80_|execute_|ctl_bus_db_oe .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N14 +cycloneive_lcell_comb \z80_|bus_control_|db[0]~6 ( +// Equation(s): +// \z80_|bus_control_|db[0]~6_combout = (\z80_|execute_|ctl_bus_db_oe~combout ) # ((\z80_|execute_|ctl_bus_db_we~7_combout ) # (!\z80_|execute_|ctl_bus_db_oe~2_combout )) + + .dataa(\z80_|execute_|ctl_bus_db_oe~combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~2_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[0]~6 .lut_mask = 16'hFAFF; +defparam \z80_|bus_control_|db[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~61 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][2]~61_combout = (\ula_|zx_keyboard_|keys[7][2]~60_combout & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|zx_keyboard_|keys[7][2]~60_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][2]~61_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2]~61 .lut_mask = 16'h2000; +defparam \ula_|zx_keyboard_|keys[7][2]~61 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~63 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][2]~63_combout = (\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[7][2]~61_combout ) # ((\ula_|zx_keyboard_|keys[5][4]~62_combout & \ula_|zx_keyboard_|keys[7][2]~30_combout )))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|zx_keyboard_|keys[7][2]~61_combout ), + .datac(\ula_|zx_keyboard_|keys[5][4]~62_combout ), + .datad(\ula_|zx_keyboard_|keys[7][2]~30_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][2]~63_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2]~63 .lut_mask = 16'hA888; +defparam \ula_|zx_keyboard_|keys[7][2]~63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~64 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][2]~64_combout = (\ula_|zx_keyboard_|keys[0][0]~13_combout & (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|keys[7][2]~63_combout & !\ula_|zx_keyboard_|extended~q ))) + + .dataa(\ula_|zx_keyboard_|keys[0][0]~13_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|zx_keyboard_|keys[7][2]~63_combout ), + .datad(\ula_|zx_keyboard_|extended~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][2]~64_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2]~64 .lut_mask = 16'h0020; +defparam \ula_|zx_keyboard_|keys[7][2]~64 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~65 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][2]~65_combout = (\ula_|zx_keyboard_|keys[7][2]~64_combout & (!\ula_|zx_keyboard_|Selector13~0_combout )) # (!\ula_|zx_keyboard_|keys[7][2]~64_combout & ((\ula_|zx_keyboard_|keys[7][2]~q ))) + + .dataa(\ula_|zx_keyboard_|Selector13~0_combout ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[7][2]~q ), + .datad(\ula_|zx_keyboard_|keys[7][2]~64_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][2]~65_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2]~65 .lut_mask = 16'h55F0; +defparam \ula_|zx_keyboard_|keys[7][2]~65 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y9_N5 +dffeas \ula_|zx_keyboard_|keys[7][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[7][2]~65_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[7][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[7][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~67 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][2]~67_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [4])) # (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [1] & +// !\ula_|ps2_keyboard_|shiftreg [4])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][2]~67_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][2]~67 .lut_mask = 16'h2244; +defparam \ula_|zx_keyboard_|keys[6][2]~67 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~68 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][2]~68_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[6][2]~67_combout & (\ula_|ps2_keyboard_|shiftreg [4] $ (!\ula_|ps2_keyboard_|shiftreg [2])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|zx_keyboard_|keys[6][2]~67_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][2]~68_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][2]~68 .lut_mask = 16'h2100; +defparam \ula_|zx_keyboard_|keys[6][2]~68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~69 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][2]~69_combout = (\ula_|zx_keyboard_|keys[6][1]~39_combout & ((\ula_|zx_keyboard_|keys[6][2]~68_combout & (!\ula_|zx_keyboard_|keys[5][0]~66_combout )) # (!\ula_|zx_keyboard_|keys[6][2]~68_combout & +// ((\ula_|zx_keyboard_|keys[6][2]~q ))))) # (!\ula_|zx_keyboard_|keys[6][1]~39_combout & (((\ula_|zx_keyboard_|keys[6][2]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][0]~66_combout ), + .datab(\ula_|zx_keyboard_|keys[6][1]~39_combout ), + .datac(\ula_|zx_keyboard_|keys[6][2]~q ), + .datad(\ula_|zx_keyboard_|keys[6][2]~68_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][2]~69_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][2]~69 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[6][2]~69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y8_N11 +dffeas \ula_|zx_keyboard_|keys[6][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[6][2]~69_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[6][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[6][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N12 +cycloneive_lcell_comb \D[2]~36 ( +// Equation(s): +// \D[2]~36_combout = (\ula_|zx_keyboard_|keys[7][2]~q & (\z80_|address_pins_|abus[15]~22_combout & ((\z80_|address_pins_|abus[14]~23_combout ) # (!\ula_|zx_keyboard_|keys[6][2]~q )))) # (!\ula_|zx_keyboard_|keys[7][2]~q & +// (((\z80_|address_pins_|abus[14]~23_combout )) # (!\ula_|zx_keyboard_|keys[6][2]~q ))) + + .dataa(\ula_|zx_keyboard_|keys[7][2]~q ), + .datab(\ula_|zx_keyboard_|keys[6][2]~q ), + .datac(\z80_|address_pins_|abus[14]~23_combout ), + .datad(\z80_|address_pins_|abus[15]~22_combout ), + .cin(gnd), + .combout(\D[2]~36_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~36 .lut_mask = 16'hF351; +defparam \D[2]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~58 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][2]~58_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [1]))) # (!\ula_|ps2_keyboard_|shiftreg [6] & +// (!\ula_|zx_keyboard_|extended~q & (\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|zx_keyboard_|extended~q ), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][2]~58_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][2]~58 .lut_mask = 16'h1008; +defparam \ula_|zx_keyboard_|keys[4][2]~58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~130 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][2]~130_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|zx_keyboard_|keys[4][2]~58_combout & (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [0]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|zx_keyboard_|keys[4][2]~58_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][2]~130_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][2]~130 .lut_mask = 16'h0080; +defparam \ula_|zx_keyboard_|keys[4][2]~130 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~59 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][2]~59_combout = (\ula_|zx_keyboard_|keys[3][4]~129_combout & ((\ula_|zx_keyboard_|keys[4][2]~130_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[4][2]~130_combout & ((\ula_|zx_keyboard_|keys[4][2]~q +// ))))) # (!\ula_|zx_keyboard_|keys[3][4]~129_combout & (((\ula_|zx_keyboard_|keys[4][2]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[3][4]~129_combout ), + .datac(\ula_|zx_keyboard_|keys[4][2]~q ), + .datad(\ula_|zx_keyboard_|keys[4][2]~130_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][2]~59_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][2]~59 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[4][2]~59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y8_N25 +dffeas \ula_|zx_keyboard_|keys[4][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[4][2]~59_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[4][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[4][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~56 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][2]~56_combout = (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [2]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][2]~56_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][2]~56 .lut_mask = 16'h00F0; +defparam \ula_|zx_keyboard_|keys[5][2]~56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~57 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][2]~57_combout = (\ula_|zx_keyboard_|keys[5][2]~56_combout & ((\ula_|zx_keyboard_|keys[5][2]~31_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[5][2]~31_combout & ((\ula_|zx_keyboard_|keys[5][2]~q +// ))))) # (!\ula_|zx_keyboard_|keys[5][2]~56_combout & (((\ula_|zx_keyboard_|keys[5][2]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][2]~56_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[5][2]~q ), + .datad(\ula_|zx_keyboard_|keys[5][2]~31_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][2]~57_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][2]~57 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[5][2]~57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y10_N19 +dffeas \ula_|zx_keyboard_|keys[5][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[5][2]~57_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[5][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[5][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N24 +cycloneive_lcell_comb \D[2]~35 ( +// Equation(s): +// \D[2]~35_combout = (\z80_|address_pins_|abus[13]~20_combout & (((\z80_|address_pins_|abus[12]~21_combout )) # (!\ula_|zx_keyboard_|keys[4][2]~q ))) # (!\z80_|address_pins_|abus[13]~20_combout & (!\ula_|zx_keyboard_|keys[5][2]~q & +// ((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][2]~q )))) + + .dataa(\z80_|address_pins_|abus[13]~20_combout ), + .datab(\ula_|zx_keyboard_|keys[4][2]~q ), + .datac(\z80_|address_pins_|abus[12]~21_combout ), + .datad(\ula_|zx_keyboard_|keys[5][2]~q ), + .cin(gnd), + .combout(\D[2]~35_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~35 .lut_mask = 16'hA2F3; +defparam \D[2]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][2]~54 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][2]~54_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [2]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][2]~54_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][2]~54 .lut_mask = 16'h000F; +defparam \ula_|zx_keyboard_|keys[0][2]~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][2]~55 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][2]~55_combout = (\ula_|zx_keyboard_|keys[7][4]~49_combout & ((\ula_|zx_keyboard_|keys[0][2]~54_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[0][2]~54_combout & ((\ula_|zx_keyboard_|keys[0][2]~q +// ))))) # (!\ula_|zx_keyboard_|keys[7][4]~49_combout & (((\ula_|zx_keyboard_|keys[0][2]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[7][4]~49_combout ), + .datac(\ula_|zx_keyboard_|keys[0][2]~q ), + .datad(\ula_|zx_keyboard_|keys[0][2]~54_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][2]~55_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][2]~55 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[0][2]~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y7_N19 +dffeas \ula_|zx_keyboard_|keys[0][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[0][2]~55_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[0][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[0][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][2]~50 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][2]~50_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [2]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][2]~50_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][2]~50 .lut_mask = 16'h0F00; +defparam \ula_|zx_keyboard_|keys[3][2]~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][2]~51 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][2]~51_combout = (\ula_|zx_keyboard_|keys[3][2]~50_combout & ((\ula_|zx_keyboard_|keys[7][4]~49_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[7][4]~49_combout & (\ula_|zx_keyboard_|keys[3][2]~q +// )))) # (!\ula_|zx_keyboard_|keys[3][2]~50_combout & (((\ula_|zx_keyboard_|keys[3][2]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[3][2]~50_combout ), + .datab(\ula_|zx_keyboard_|keys[7][4]~49_combout ), + .datac(\ula_|zx_keyboard_|keys[3][2]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][2]~51_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][2]~51 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[3][2]~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y7_N15 +dffeas \ula_|zx_keyboard_|keys[3][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[3][2]~51_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[3][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[3][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][2]~52 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][2]~52_combout = (\ula_|zx_keyboard_|Equal0~2_combout & (\ula_|zx_keyboard_|keys[7][4]~17_combout & (\ula_|zx_keyboard_|keys[3][2]~50_combout & !\ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|zx_keyboard_|Equal0~2_combout ), + .datab(\ula_|zx_keyboard_|keys[7][4]~17_combout ), + .datac(\ula_|zx_keyboard_|keys[3][2]~50_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][2]~52_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][2]~52 .lut_mask = 16'h0080; +defparam \ula_|zx_keyboard_|keys[2][2]~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][2]~53 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][2]~53_combout = (\ula_|zx_keyboard_|keys[2][2]~52_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[2][2]~52_combout & ((\ula_|zx_keyboard_|keys[2][2]~q ))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[2][2]~q ), + .datad(\ula_|zx_keyboard_|keys[2][2]~52_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][2]~53_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][2]~53 .lut_mask = 16'h55F0; +defparam \ula_|zx_keyboard_|keys[2][2]~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y7_N25 +dffeas \ula_|zx_keyboard_|keys[2][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[2][2]~53_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[2][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[2][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N8 +cycloneive_lcell_comb \D[2]~33 ( +// Equation(s): +// \D[2]~33_combout = (\ula_|zx_keyboard_|keys[3][2]~q & (\z80_|address_pins_|abus[11]~19_combout & ((\z80_|address_pins_|abus[10]~24_combout ) # (!\ula_|zx_keyboard_|keys[2][2]~q )))) # (!\ula_|zx_keyboard_|keys[3][2]~q & +// (((\z80_|address_pins_|abus[10]~24_combout )) # (!\ula_|zx_keyboard_|keys[2][2]~q ))) + + .dataa(\ula_|zx_keyboard_|keys[3][2]~q ), + .datab(\ula_|zx_keyboard_|keys[2][2]~q ), + .datac(\z80_|address_pins_|abus[11]~19_combout ), + .datad(\z80_|address_pins_|abus[10]~24_combout ), + .cin(gnd), + .combout(\D[2]~33_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~33 .lut_mask = 16'hF531; +defparam \D[2]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][2]~47 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][2]~47_combout = (\ula_|zx_keyboard_|keys[6][4]~45_combout & (\ula_|zx_keyboard_|keys[6][4]~46_combout & !\ula_|ps2_keyboard_|shiftreg [4])) + + .dataa(\ula_|zx_keyboard_|keys[6][4]~45_combout ), + .datab(\ula_|zx_keyboard_|keys[6][4]~46_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][2]~47_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][2]~47 .lut_mask = 16'h0808; +defparam \ula_|zx_keyboard_|keys[1][2]~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][2]~48 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][2]~48_combout = (\ula_|zx_keyboard_|keys[1][2]~47_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[1][2]~47_combout & (\ula_|zx_keyboard_|keys[1][2]~q )) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|keys[1][2]~47_combout ), + .datac(\ula_|zx_keyboard_|keys[1][2]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][2]~48_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][2]~48 .lut_mask = 16'h30FC; +defparam \ula_|zx_keyboard_|keys[1][2]~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y7_N7 +dffeas \ula_|zx_keyboard_|keys[1][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[1][2]~48_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[1][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[1][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~1 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row~1_combout = (\z80_|address_pins_|DFFE_apin_latch [9]) # ((!\ula_|zx_keyboard_|keys[1][2]~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [9]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\ula_|zx_keyboard_|keys[1][2]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row~1 .lut_mask = 16'hCFFF; +defparam \ula_|zx_keyboard_|key_row~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N4 +cycloneive_lcell_comb \D[2]~34 ( +// Equation(s): +// \D[2]~34_combout = (\D[2]~33_combout & (\ula_|zx_keyboard_|key_row~1_combout & ((\z80_|address_pins_|abus[8]~18_combout ) # (!\ula_|zx_keyboard_|keys[0][2]~q )))) + + .dataa(\z80_|address_pins_|abus[8]~18_combout ), + .datab(\ula_|zx_keyboard_|keys[0][2]~q ), + .datac(\D[2]~33_combout ), + .datad(\ula_|zx_keyboard_|key_row~1_combout ), + .cin(gnd), + .combout(\D[2]~34_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~34 .lut_mask = 16'hB000; +defparam \D[2]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N28 +cycloneive_lcell_comb \D[2]~37 ( +// Equation(s): +// \D[2]~37_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[2]~36_combout & (\D[2]~35_combout & \D[2]~34_combout ))) + + .dataa(\D[2]~36_combout ), + .datab(\D[2]~35_combout ), + .datac(\D[2]~34_combout ), + .datad(\z80_|address_pins_|abus[0]~16_combout ), + .cin(gnd), + .combout(\D[2]~37_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~37 .lut_mask = 16'hFF80; +defparam \D[2]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y6_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a18 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[2]~39_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_first_bit_number = 2; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y9_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a2 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[2]~39_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024; +// synopsys translate_on + +// Location: M9K_X22_Y12_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a10 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[2]~39_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N26 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2 .lut_mask = 16'hDC98; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y5_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a26 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[2]~39_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_first_bit_number = 2; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N8 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~3 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~3_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout & +// ((\ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout )))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~3_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~3 .lut_mask = 16'hF838; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y3_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a10 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h8102080042447C443C0C3C402004FC1838787840407A00707C02487E444878428008004042460424402040024A3242124220044022404208520A4A24424A125A0A1028440000524A0A4A4A204A5240460800100010540042002064547E0600001FA9BE02B828694B8A82CB8C8158226808198E9EC6B021F07A2098D5E0ECB639D2B1908129B6A2D646516192D87593189D8B2B26CD6E16234C1CC90AD9831EBD89EAD271ECC39A80507716BB49626B743DFFCF99576C3FAC889860E46618ACB79EC30EEDE42EB1E31F3976CA23243179FAA96DCD66D51535351770D410DC8531866136E6184518410368288C446EC63A4FEE425019C244097049C2B2DC8D93C4; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'hA111466C9493A2A7CA2204102414CC798BF0EEC2995A4814580BD07585585ED92E5172E82E845070000A846100500E84EA1803B8B07B99E1DC75BE6419674597B38F54EB9091AE3320201EE395AD63902282A031CE3E87CC902954AA515D5D6B6A855EC94CFEC4E0172C59A7D054F8F9F4356C312C204E40B05E2059407C8DC84683814663FB910969D1D631A952B381B7F635A33FD38D5CF15DF47D057F7FF555B555C2278100000A24804D7D98EB98602733818A12094F281287422CB40002464C92242004E0AE8518E001D124A7628010115D23C30462FC00A014A12133582A191E00538FC8A5004036A959ACB7A463D23E419EA06B744005385455A71250; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h6C60009CA281AEACDC1762945981B869F93D683EAF4AC7EE52412E85B60B91CD03AD0025F0D509F63202D877ECD8BF8005451F7BD346CF9E17B36F1850A7D80A8CF14A288EAE3BFE00FB2DB45080D4A50C58263A3B398DD51AB9CB554ECAA7B2E73D9D6D2C265859DB844C2C1952AD10241100174FE0444E6707D80A098D8585AAAC4802B74190FB007C0C0206186AFC1B3A2A46864F26118ED1D03ACB1062B7315502751655F60070E6B2C50609369611365AD1E3352327320331A51818030C7D8C4C59396600DC0C420495A0D987501490002BAD38012E20620D556A230B1796450B74E95A860FF3E434C65F1308F16F92395816B914F0CE870C1323347A4E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h7FC8531A7A319F3EBFC1383FFCDB0E09BD288288B078B4AD220B6FA934CF6187D972662C0D31E34E63B31CFC6EB4B35A69B67D85489E62EA99899A94F6800FDBA5D31B86A0288D29CE2EAAFF86A6A9F7000082293E6BB54F06E98ECCB199973EDA00FADB1D3A630BA18050635DE7DCB13B9B86E0CE6E08DC46331A352F716E3C441A0CC068A0823F8668A00621B779DE35FEC004050469F34866AEE766743D8C00FDF3B9F8DE7B76E97F8D32F0F39E4CAC68D9BBB68EA3915F6225F932CAAFDAD6E60DC661155EC9E80F8CEE659F19CC554B2C67C33EDCDA63BAD91B7D1842A7177AF49DF118FE47ACE3344964EBCADCFBB543F7729CCB340866D1157B6CCDDB; +// synopsys translate_on + +// Location: M9K_X22_Y29_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a2 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h77A47C739FF6A22B8B5CDC49E748E9C739BDE6756DB4D22437E74183E12400CBF7D3C6CC8C7841AB49CC538E8A72F2E73C64D3DF3662B19C07D7D299CBEDEF3E7DA5F4A8458A9451315B681ADA9AB0D63218DFB77D3353C32837E954604B9D98144A4566F47B71715BE6CDB8BA64D536762E9224D70F9A5C374B4D1CAB8DF527027170C5DBCC2B6AD72B8E4CCC94DAA139D8BA64E3384337426E7F274CC88A373AB1F9007B8A7F2936D16274F9BF8B6BABD48FCE74047C1E738C5B303E815BA720C76D6362915156A7671331CE657011862E594E46A6D99392E2D640D766869389A4D43867379AB880C1ACE279E451CB3A9063A0B320F65E536B8EEF9CBB9C76; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h9A2921ED6AA0CC8387B267B9E7A182720833CEE061E6450C8E4A72E3C043F21A0AD007E832124E92429C091D167806C10041AF32DDE13A669990457D098CC2FE3AC884B1E69101135CD080022451F20884CCB9CD203C141402A5AD293C3BABA95ADFAF6726384795A7656B753D2369B9EB5595BAA722012DF8DCFBF15BF46D6EB755D1CBF0DCF6FD40BEEC16EAB4A6D16839C98CBE9DBB437C69FB709F8E79993B9DDFE4F823D6E124B75BCE9B29F799F926619184B6C1178389F07349210436293A130C900FBA4EA70D2BA25B343C5B026D8E8766A4E4267CDAEC99E830D2307D94E6ED80D6722F3989B91E31C63B64C363DCE71A861C14382E270FC02868C7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h386BA04E797A3F8551DAD9D24A8D259A03ECFF5AB81B1C31DFDAE10100544F8CF1A8CCFC0C7A15BD9E7C2557CB00BF2584E16AAD13D7EDB525A85ABF90C0136DD195D748900C29DF7F381280A9738CDC3BF5BBF937D3A4D99CE2BCCD97CEF2C7F00030AFDB7F22E68CBAA4D9BE7633D3B53E90E4B124422A2A4454BACA5A8DC9352CD1DAFC910CC504334DF9E6F1F4F30161A36293CC5CCF1CA13994ED29D34A5699692496359B8E67A7E74D9A0FC504C8465638CF74A0AF9185921A7D2629893091900604017933442359491FBAB63F346F0C5EC8E3A531984B09E605A30A0627271C28420E47B8DEC74738FC3EDF9FBD40EC09FC7B4D3A1475BE433705FB5F; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h973FED2E9BEDBA474B70B121A8D60F3B4EE3F1A238FB3B730EDEEE74EC632DB4D7779D7B79D1C75DF87378E98719C1AF38B1B801C71D180CE86370AE9C2BF38CF84DBBB9878C55457324E92D3DAE91D729AC76BBAD4C6EECA74DAB5EE9A175EE34ABEB9DFAA48538A57E3E5C158947081CA41402E8E65478737F73BB629AAE2EE51D405CAF70F622DD4599602D7910DCAC8214B2A42025110593202C8B164C8DF6369572C3BB8AA1984A8D12F776E224ECEEB21F97FCD6C0CF17A044EC2BBF0571A553CCDD8ABA79BD27B7AF735ED2D34F1EF3A81A160C9ECB1B1FAE6EDEEFF99E28CC30C7C2553DED3378D655AD194B2E6C1BCBED700F6713D960F33E4C361A; +// synopsys translate_on + +// Location: M9K_X22_Y25_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a10 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(gnd), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[2]~39_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_first_bit_number = 2; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y27_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a2 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[2]~39_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_bit_number = 2; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF00000000FFFFFFFFFFFFFFFFFFF68003FFF38003FFF9F403FFF8B003D8F87003FFF8F01BEDFC701FEBFEA01FDBFDC00FDBFDC01FC7FDC0FFC7FDE87FC7FCDC8FC7FCF89FC07071FFC0F873F3E0303FE7FFFFFFFFFFFFFFFF; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000000040078400234B1474928D1000000000000000000000000FFFFFFFF204081024004027153423DA5474928DD000000000000000000000000000000003FFFFFFF40041CB14162378547495999000000000000000000000000000000003FFFFFFF4004189141623485474959F90000000000000000000000003FFFFFFE40000001400400815B6223C15FC913DD0000000000000000000000007FFFFFFE40000001400402E9400333715FC973E5000000000000000000000000604081027FFFFFFD5FE60AE95763353540091361000000000000000000000000400000003FFFFFFC5FE60AE95763081D40011361; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h5FE0236948F816F55FE897C10C28028041DC8DE178059BC16900BB4173E47AC15FE8236148E806F55FE891054CA80E8148288DE179E597C169903AC153F13A8140080365486806D55FE891D548080A8148608FE159E493C16BB03FD152BD1AE14008037D482017D15FE881C548A00AC148E08FE159FC9AC16AA02FC15AAF18F1400083F1482007C15EE882C148E00A4148B08FE148F88D4168E436915ABB01E9400092F9480007815C2882C148E00B6149B49F614868FD41436476814AFA42A1400892FD480807C15C0883C149800FE149DC9FE14A60BD41431C3F914AEA01C1400882F1480817C11C0883C041940FE549CC9EE54860BDC143BC7D8108D2C4D0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h0B928870484885014DE84481680162815375AC0148D308813FFFFFFC400000004B9288314DC0970149FC44856C0166815375AC8140D108817FFFFFFD6040808249D0A2094F908581481C40814C016099417DA88140D10B01400000017FFFFFFE48D083394B9085814A085081440166814179900140510F01400000013FFFFFFE4A508335498001814BE0608146016E8941799041405107413FFFFFFF000000004B98812149C005814BE0628146836E814179100140510F013FFFFFFF000000004B98A1114BE801814A00668147832C814119904140401F4120408082FFFFFFFF48D881154EA801854800768147C22CC14019900100003E0000000000FFFFFFFF; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N24 +cycloneive_lcell_comb \Selector0~0 ( +// Equation(s): +// \Selector0~0_combout = (\Selector3~0_combout & (((\ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout )) # (!\z80_|address_pins_|abus[14]~23_combout ))) # (!\Selector3~0_combout & (\z80_|address_pins_|abus[14]~23_combout & +// ((\ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout )))) + + .dataa(\Selector3~0_combout ), + .datab(\z80_|address_pins_|abus[14]~23_combout ), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ), + .cin(gnd), + .combout(\Selector0~0_combout ), + .cout()); +// synopsys translate_off +defparam \Selector0~0 .lut_mask = 16'hE6A2; +defparam \Selector0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N18 +cycloneive_lcell_comb \Selector0~1 ( +// Equation(s): +// \Selector0~1_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\Selector0~0_combout )))) # (!\z80_|address_pins_|abus[14]~23_combout & ((\Selector0~0_combout & (\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout )) # +// (!\Selector0~0_combout & ((\rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ))))) + + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ), + .datad(\Selector0~0_combout ), + .cin(gnd), + .combout(\Selector0~1_combout ), + .cout()); +// synopsys translate_off +defparam \Selector0~1 .lut_mask = 16'hEE50; +defparam \Selector0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N28 +cycloneive_lcell_comb \D[2]~82 ( +// Equation(s): +// \D[2]~82_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~3_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\Selector0~1_combout +// ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~3_combout )))) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~3_combout ), + .datad(\Selector0~1_combout ), + .cin(gnd), + .combout(\D[2]~82_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~82 .lut_mask = 16'hF4B0; +defparam \D[2]~82 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N12 +cycloneive_lcell_comb \D[2]~38 ( +// Equation(s): +// \D[2]~38_combout = ((\Equal2~0_combout & (\D[2]~37_combout )) # (!\Equal2~0_combout & ((\D[2]~82_combout )))) # (!\Equal2~1_combout ) + + .dataa(\Equal2~1_combout ), + .datab(\Equal2~0_combout ), + .datac(\D[2]~37_combout ), + .datad(\D[2]~82_combout ), + .cin(gnd), + .combout(\D[2]~38_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~38 .lut_mask = 16'hF7D5; +defparam \D[2]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N30 +cycloneive_lcell_comb \D[2]~39 ( +// Equation(s): +// \D[2]~39_combout = (\z80_|pin_control_|bus_db_pin_oe~15_combout & (((\z80_|data_pins_|dout [2] & \D[2]~38_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout & (((\D[2]~38_combout )) # (!\Equal2~1_combout ))) + + .dataa(\Equal2~1_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .datac(\z80_|data_pins_|dout [2]), + .datad(\D[2]~38_combout ), + .cin(gnd), + .combout(\D[2]~39_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~39 .lut_mask = 16'hF311; +defparam \D[2]~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N4 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [2] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[2]~13_combout ) # ((\D[2]~39_combout & \z80_|pin_control_|bus_db_pin_re~combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & +// (((\D[2]~39_combout & \z80_|pin_control_|bus_db_pin_re~combout )))) + + .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datab(\z80_|bus_control_|db[2]~13_combout ), + .datac(\D[2]~39_combout ), + .datad(\z80_|pin_control_|bus_db_pin_re~combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [2]), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] .lut_mask = 16'hF888; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y13_N5 +dffeas \z80_|data_pins_|dout[2] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [2]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|data_pins_|dout [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|data_pins_|dout[2] .is_wysiwyg = "true"; +defparam \z80_|data_pins_|dout[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N6 +cycloneive_lcell_comb \z80_|bus_control_|db[2]~12 ( +// Equation(s): +// \z80_|bus_control_|db[2]~12_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[2]~29_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) + + .dataa(\z80_|bus_control_|db[0]~4_combout ), + .datab(gnd), + .datac(\z80_|alu_control_|db[2]~29_combout ), + .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[2]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[2]~12 .lut_mask = 16'hA0AA; +defparam \z80_|bus_control_|db[2]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N0 +cycloneive_lcell_comb \z80_|bus_control_|db[2]~13 ( +// Equation(s): +// \z80_|bus_control_|db[2]~13_combout = ((\z80_|bus_control_|db[2]~12_combout & ((\z80_|data_pins_|dout [2]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) + + .dataa(\z80_|bus_control_|db[0]~6_combout ), + .datab(\z80_|execute_|ctl_bus_db_oe~combout ), + .datac(\z80_|data_pins_|dout [2]), + .datad(\z80_|bus_control_|db[2]~12_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[2]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[2]~13 .lut_mask = 16'hF755; +defparam \z80_|bus_control_|db[2]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y13_N27 +dffeas \z80_|ir_|opcode[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|bus_control_|db[2]~13_combout ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|ir_|opcode [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|ir_|opcode[2] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N18 +cycloneive_lcell_comb \z80_|pla_decode_|Equal1~4 ( +// Equation(s): +// \z80_|pla_decode_|Equal1~4_combout = (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [1]) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|ir_|opcode [1]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal1~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal1~4 .lut_mask = 16'h0303; +defparam \z80_|pla_decode_|Equal1~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~26 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~26_combout = (\z80_|pla_decode_|Equal1~4_combout & (\z80_|execute_|ctl_mWrite~5_combout & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|ir_|opcode [0]))) + + .dataa(\z80_|pla_decode_|Equal1~4_combout ), + .datab(\z80_|execute_|ctl_mWrite~5_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~26 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_alu_op_low~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~45 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~45_combout = (!\z80_|execute_|ctl_alu_op_low~26_combout & (((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|pla_decode_|Equal13~2_combout )) # (!\z80_|sequencer_|DFFE_M4_ff~q ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~26_combout ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~45 .lut_mask = 16'h1555; +defparam \z80_|execute_|ctl_alu_op_low~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|setM1~17 ( +// Equation(s): +// \z80_|execute_|setM1~17_combout = (!\z80_|execute_|ctl_alu_shift_oe~15_combout & (\z80_|execute_|ctl_sw_2u~1_combout & \z80_|execute_|ctl_state_alu~7_combout )) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~15_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_sw_2u~1_combout ), + .datad(\z80_|execute_|ctl_state_alu~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~17 .lut_mask = 16'h5000; +defparam \z80_|execute_|setM1~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|setM1~18 ( +// Equation(s): +// \z80_|execute_|setM1~18_combout = (\z80_|execute_|ctl_alu_op_low~45_combout & (\z80_|execute_|setM1~17_combout & (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & !\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~45_combout ), + .datab(\z80_|execute_|setM1~17_combout ), + .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~18 .lut_mask = 16'h0008; +defparam \z80_|execute_|setM1~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|setM1~11 ( +// Equation(s): +// \z80_|execute_|setM1~11_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ) # ((!\z80_|ir_|opcode [2] & (\z80_|execute_|ctl_mWrite~4_combout & !\z80_|ir_|opcode [4]))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|setM1~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~11 .lut_mask = 16'hAABA; +defparam \z80_|execute_|setM1~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|setM1~10 ( +// Equation(s): +// \z80_|execute_|setM1~10_combout = (\z80_|execute_|ctl_mRead~5_combout ) # (((\z80_|execute_|ctl_mWrite~6_combout ) # (\z80_|pla_decode_|Equal6~1_combout )) # (!\z80_|execute_|fMWrite~1_combout )) + + .dataa(\z80_|execute_|ctl_mRead~5_combout ), + .datab(\z80_|execute_|fMWrite~1_combout ), + .datac(\z80_|execute_|ctl_mWrite~6_combout ), + .datad(\z80_|pla_decode_|Equal6~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~10 .lut_mask = 16'hFFFB; +defparam \z80_|execute_|setM1~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|setM1~12 ( +// Equation(s): +// \z80_|execute_|setM1~12_combout = ((\z80_|execute_|setM1~10_combout ) # ((\z80_|execute_|setM1~11_combout & \z80_|execute_|ctl_mWrite~17_combout ))) # (!\z80_|execute_|nextM~2_combout ) + + .dataa(\z80_|execute_|nextM~2_combout ), + .datab(\z80_|execute_|setM1~11_combout ), + .datac(\z80_|execute_|ctl_mWrite~17_combout ), + .datad(\z80_|execute_|setM1~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~12 .lut_mask = 16'hFFD5; +defparam \z80_|execute_|setM1~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|setM1~8 ( +// Equation(s): +// \z80_|execute_|setM1~8_combout = (\z80_|execute_|ctl_al_we~13_combout & (\z80_|sequencer_|M5~q & ((\z80_|pla_decode_|Equal9~1_combout )))) # (!\z80_|execute_|ctl_al_we~13_combout & ((\z80_|sequencer_|DFFE_M4_ff~q ) # ((\z80_|sequencer_|M5~q & +// \z80_|pla_decode_|Equal9~1_combout )))) + + .dataa(\z80_|execute_|ctl_al_we~13_combout ), + .datab(\z80_|sequencer_|M5~q ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~8 .lut_mask = 16'hDC50; +defparam \z80_|execute_|setM1~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|setM1~9 ( +// Equation(s): +// \z80_|execute_|setM1~9_combout = ((\z80_|sequencer_|DFFE_T5_ff~q & \z80_|execute_|setM1~8_combout )) # (!\z80_|execute_|ctl_flags_xy_we~19_combout ) + + .dataa(\z80_|execute_|ctl_flags_xy_we~19_combout ), + .datab(\z80_|sequencer_|DFFE_T5_ff~q ), + .datac(gnd), + .datad(\z80_|execute_|setM1~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~9 .lut_mask = 16'hDD55; +defparam \z80_|execute_|setM1~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|setM1~13 ( +// Equation(s): +// \z80_|execute_|setM1~13_combout = ((\z80_|execute_|setM1~9_combout ) # ((\z80_|execute_|setM1~12_combout & \z80_|execute_|ixy_d~6_combout ))) # (!\z80_|reg_control_|reg_sel_pc~3_combout ) + + .dataa(\z80_|reg_control_|reg_sel_pc~3_combout ), + .datab(\z80_|execute_|setM1~12_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|setM1~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~13 .lut_mask = 16'hFFD5; +defparam \z80_|execute_|setM1~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|setM1~15 ( +// Equation(s): +// \z80_|execute_|setM1~15_combout = (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|pla_decode_|Equal13~0_combout & ((!\z80_|pla_decode_|Equal21~2_combout ) # (!\z80_|pla_decode_|Equal32~0_combout )))) # (!\z80_|pla_decode_|Equal33~0_combout & +// (((!\z80_|pla_decode_|Equal21~2_combout )) # (!\z80_|pla_decode_|Equal32~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|pla_decode_|Equal32~0_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|pla_decode_|Equal21~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~15 .lut_mask = 16'h135F; +defparam \z80_|execute_|setM1~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|setM1~14 ( +// Equation(s): +// \z80_|execute_|setM1~14_combout = (!\z80_|execute_|ctl_alu_oe~1_combout & (!\z80_|pla_decode_|Equal77~1_combout & (!\z80_|pla_decode_|Equal1~6_combout & !\z80_|pla_decode_|Equal2~2_combout ))) + + .dataa(\z80_|execute_|ctl_alu_oe~1_combout ), + .datab(\z80_|pla_decode_|Equal77~1_combout ), + .datac(\z80_|pla_decode_|Equal1~6_combout ), + .datad(\z80_|pla_decode_|Equal2~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~14 .lut_mask = 16'h0001; +defparam \z80_|execute_|setM1~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|setM1~16 ( +// Equation(s): +// \z80_|execute_|setM1~16_combout = (\z80_|interrupts_|test1~2_combout & (\z80_|execute_|setM1~15_combout & \z80_|execute_|setM1~14_combout )) + + .dataa(gnd), + .datab(\z80_|interrupts_|test1~2_combout ), + .datac(\z80_|execute_|setM1~15_combout ), + .datad(\z80_|execute_|setM1~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~16 .lut_mask = 16'hC000; +defparam \z80_|execute_|setM1~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|setM1~19 ( +// Equation(s): +// \z80_|execute_|setM1~19_combout = ((\z80_|execute_|setM1~13_combout ) # ((!\z80_|execute_|setM1~16_combout & \z80_|execute_|ctl_eval_cond~0_combout ))) # (!\z80_|execute_|setM1~18_combout ) + + .dataa(\z80_|execute_|setM1~18_combout ), + .datab(\z80_|execute_|setM1~13_combout ), + .datac(\z80_|execute_|setM1~16_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~19 .lut_mask = 16'hDFDD; +defparam \z80_|execute_|setM1~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N16 +cycloneive_lcell_comb \z80_|execute_|setM1~23 ( +// Equation(s): +// \z80_|execute_|setM1~23_combout = (\z80_|execute_|fMWrite~1_combout & (!\z80_|execute_|ctl_mRead~8_combout & (!\z80_|execute_|ctl_mRead~6_combout & \z80_|execute_|fMWrite~6_combout ))) + + .dataa(\z80_|execute_|fMWrite~1_combout ), + .datab(\z80_|execute_|ctl_mRead~8_combout ), + .datac(\z80_|execute_|ctl_mRead~6_combout ), + .datad(\z80_|execute_|fMWrite~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~23 .lut_mask = 16'h0200; +defparam \z80_|execute_|setM1~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|setM1~22 ( +// Equation(s): +// \z80_|execute_|setM1~22_combout = (\z80_|decode_state_|DFFE_instNonRep~q ) # ((!\z80_|ir_|opcode [2] & (\z80_|execute_|ctl_mWrite~4_combout & !\z80_|ir_|opcode [4]))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|execute_|ctl_mWrite~4_combout ), + .datac(\z80_|decode_state_|DFFE_instNonRep~q ), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|setM1~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~22 .lut_mask = 16'hF0F4; +defparam \z80_|execute_|setM1~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|setM1~56 ( +// Equation(s): +// \z80_|execute_|setM1~56_combout = (\z80_|sequencer_|DFFE_T5_ff~q & ((\z80_|sequencer_|DFFE_M4_ff~q ) # ((\z80_|sequencer_|DFFE_M3_ff~q & \z80_|execute_|setM1~22_combout )))) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|sequencer_|DFFE_T5_ff~q ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|execute_|setM1~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~56_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~56 .lut_mask = 16'hC8C0; +defparam \z80_|execute_|setM1~56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|setM1~24 ( +// Equation(s): +// \z80_|execute_|setM1~24_combout = (\z80_|execute_|setM1~23_combout & (!\z80_|execute_|ctl_flags_bus~1_combout & ((\z80_|execute_|setM1~56_combout )))) # (!\z80_|execute_|setM1~23_combout & ((\z80_|execute_|ctl_reg_in_hi~2_combout ) # +// ((!\z80_|execute_|ctl_flags_bus~1_combout & \z80_|execute_|setM1~56_combout )))) + + .dataa(\z80_|execute_|setM1~23_combout ), + .datab(\z80_|execute_|ctl_flags_bus~1_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datad(\z80_|execute_|setM1~56_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~24 .lut_mask = 16'h7350; +defparam \z80_|execute_|setM1~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|setM1~25 ( +// Equation(s): +// \z80_|execute_|setM1~25_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & (((\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & !\z80_|execute_|ctl_mRead~10_combout )) # (!\z80_|alu_control_|flags_cond_true~q ))) # +// (!\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & (((\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & !\z80_|execute_|ctl_mRead~10_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), + .datab(\z80_|alu_control_|flags_cond_true~q ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .datad(\z80_|execute_|ctl_mRead~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~25 .lut_mask = 16'h22F2; +defparam \z80_|execute_|setM1~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|setM1~26 ( +// Equation(s): +// \z80_|execute_|setM1~26_combout = ((\z80_|execute_|ctl_mRead~11_combout ) # ((!\z80_|alu_control_|flags_cond_true~q & \z80_|pla_decode_|Equal40~1_combout ))) # (!\z80_|execute_|ctl_bus_inc_oe~31_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~31_combout ), + .datab(\z80_|alu_control_|flags_cond_true~q ), + .datac(\z80_|pla_decode_|Equal40~1_combout ), + .datad(\z80_|execute_|ctl_mRead~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~26 .lut_mask = 16'hFF75; +defparam \z80_|execute_|setM1~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|setM1~27 ( +// Equation(s): +// \z80_|execute_|setM1~27_combout = (\z80_|execute_|setM1~26_combout ) # (((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & \z80_|pla_decode_|Equal21~1_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout )) + + .dataa(\z80_|execute_|setM1~26_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ), + .datad(\z80_|pla_decode_|Equal21~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~27 .lut_mask = 16'hEFAF; +defparam \z80_|execute_|setM1~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|setM1~28 ( +// Equation(s): +// \z80_|execute_|setM1~28_combout = (\z80_|execute_|setM1~24_combout ) # ((\z80_|execute_|setM1~25_combout ) # ((\z80_|execute_|ctl_state_alu~2_combout & \z80_|execute_|setM1~27_combout ))) + + .dataa(\z80_|execute_|setM1~24_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|execute_|setM1~25_combout ), + .datad(\z80_|execute_|setM1~27_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~28 .lut_mask = 16'hFEFA; +defparam \z80_|execute_|setM1~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|setM1~55 ( +// Equation(s): +// \z80_|execute_|setM1~55_combout = ((\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|execute_|ctl_iorw~10_combout ))) # (!\z80_|execute_|ctl_flags_sz_we~0_combout ) + + .dataa(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|execute_|ctl_iorw~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~55_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~55 .lut_mask = 16'hD555; +defparam \z80_|execute_|setM1~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|setM1~29 ( +// Equation(s): +// \z80_|execute_|setM1~29_combout = (\z80_|execute_|ctl_mRead~13_combout ) # ((\z80_|execute_|ctl_mRead~5_combout ) # ((\z80_|execute_|ctl_mRead~7_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~13_combout ), + .datab(\z80_|execute_|ctl_mRead~5_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ), + .datad(\z80_|execute_|ctl_mRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~29 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|setM1~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|setM1~31 ( +// Equation(s): +// \z80_|execute_|setM1~31_combout = (((\z80_|execute_|ctl_state_alu~4_combout & \z80_|execute_|setM1~29_combout )) # (!\z80_|execute_|setM1~57_combout )) # (!\z80_|execute_|setM1~30_combout ) + + .dataa(\z80_|execute_|setM1~30_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|setM1~29_combout ), + .datad(\z80_|execute_|setM1~57_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~31 .lut_mask = 16'hD5FF; +defparam \z80_|execute_|setM1~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|setM1~33 ( +// Equation(s): +// \z80_|execute_|setM1~33_combout = (\z80_|execute_|ctl_mRead~2_combout ) # ((\z80_|execute_|ctl_mRead~3_combout ) # ((\z80_|execute_|ctl_mRead~34_combout & \z80_|execute_|setM1~11_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~2_combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|execute_|setM1~11_combout ), + .datad(\z80_|execute_|ctl_mRead~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~33 .lut_mask = 16'hFFEA; +defparam \z80_|execute_|setM1~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|setM1~32 ( +// Equation(s): +// \z80_|execute_|setM1~32_combout = (\z80_|pla_decode_|Equal35~0_combout & ((\z80_|execute_|ixy_d~6_combout ) # ((\z80_|execute_|ctl_reg_in_hi~2_combout & \z80_|execute_|ctl_mRead~16_combout )))) # (!\z80_|pla_decode_|Equal35~0_combout & +// (\z80_|execute_|ctl_reg_in_hi~2_combout & ((\z80_|execute_|ctl_mRead~16_combout )))) + + .dataa(\z80_|pla_decode_|Equal35~0_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ctl_mRead~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~32 .lut_mask = 16'hECA0; +defparam \z80_|execute_|setM1~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|setM1~34 ( +// Equation(s): +// \z80_|execute_|setM1~34_combout = (\z80_|execute_|setM1~31_combout ) # ((\z80_|execute_|setM1~32_combout ) # ((\z80_|execute_|setM1~33_combout & \z80_|execute_|ixy_d~9_combout ))) + + .dataa(\z80_|execute_|setM1~31_combout ), + .datab(\z80_|execute_|setM1~33_combout ), + .datac(\z80_|execute_|ixy_d~9_combout ), + .datad(\z80_|execute_|setM1~32_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~34 .lut_mask = 16'hFFEA; +defparam \z80_|execute_|setM1~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|setM1~20 ( +// Equation(s): +// \z80_|execute_|setM1~20_combout = (\z80_|execute_|ctl_mRead~9_combout & (((\z80_|pla_decode_|Equal37~0_combout & !\z80_|alu_control_|flags_cond_true~q )) # (!\z80_|execute_|ctl_flags_bus~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal37~0_combout ), + .datab(\z80_|alu_control_|flags_cond_true~q ), + .datac(\z80_|execute_|ctl_mRead~9_combout ), + .datad(\z80_|execute_|ctl_flags_bus~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~20 .lut_mask = 16'h20F0; +defparam \z80_|execute_|setM1~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|setM1~21 ( +// Equation(s): +// \z80_|execute_|setM1~21_combout = (\z80_|execute_|setM1~20_combout ) # ((\z80_|execute_|ixy_d~8_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & \z80_|pla_decode_|Equal10~0_combout ))) + + .dataa(\z80_|execute_|ixy_d~8_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|execute_|setM1~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~21 .lut_mask = 16'hFF80; +defparam \z80_|execute_|setM1~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|setM1~35 ( +// Equation(s): +// \z80_|execute_|setM1~35_combout = (\z80_|execute_|setM1~28_combout ) # ((\z80_|execute_|setM1~55_combout ) # ((\z80_|execute_|setM1~34_combout ) # (\z80_|execute_|setM1~21_combout ))) + + .dataa(\z80_|execute_|setM1~28_combout ), + .datab(\z80_|execute_|setM1~55_combout ), + .datac(\z80_|execute_|setM1~34_combout ), + .datad(\z80_|execute_|setM1~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~35 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|setM1~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|setM1~43 ( +// Equation(s): +// \z80_|execute_|setM1~43_combout = (!\z80_|execute_|ctl_mWrite~6_combout & (!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~9_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datac(\z80_|execute_|ctl_ir_we~10_combout ), + .datad(\z80_|execute_|ctl_ir_we~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~43 .lut_mask = 16'h0003; +defparam \z80_|execute_|setM1~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N6 +cycloneive_lcell_comb \z80_|execute_|setM1~44 ( +// Equation(s): +// \z80_|execute_|setM1~44_combout = (!\z80_|pla_decode_|Equal47~0_combout & (!\z80_|pla_decode_|Equal37~0_combout & (!\z80_|pla_decode_|Equal38~2_combout & \z80_|sequencer_|DFFE_T4_ff~q ))) + + .dataa(\z80_|pla_decode_|Equal47~0_combout ), + .datab(\z80_|pla_decode_|Equal37~0_combout ), + .datac(\z80_|pla_decode_|Equal38~2_combout ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|setM1~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~44 .lut_mask = 16'h0100; +defparam \z80_|execute_|setM1~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N18 +cycloneive_lcell_comb \z80_|execute_|setM1~45 ( +// Equation(s): +// \z80_|execute_|setM1~45_combout = (!\z80_|pla_decode_|Equal21~1_combout & (\z80_|execute_|setM1~43_combout & (!\z80_|pla_decode_|Equal48~0_combout & \z80_|execute_|setM1~44_combout ))) + + .dataa(\z80_|pla_decode_|Equal21~1_combout ), + .datab(\z80_|execute_|setM1~43_combout ), + .datac(\z80_|pla_decode_|Equal48~0_combout ), + .datad(\z80_|execute_|setM1~44_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~45 .lut_mask = 16'h0400; +defparam \z80_|execute_|setM1~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|setM1~46 ( +// Equation(s): +// \z80_|execute_|setM1~46_combout = (\z80_|execute_|setM1~45_combout & (\z80_|execute_|setM1~42_combout & ((!\z80_|pla_decode_|Equal1~4_combout ) # (!\z80_|pla_decode_|Equal2~1_combout )))) + + .dataa(\z80_|execute_|setM1~45_combout ), + .datab(\z80_|pla_decode_|Equal2~1_combout ), + .datac(\z80_|pla_decode_|Equal1~4_combout ), + .datad(\z80_|execute_|setM1~42_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~46 .lut_mask = 16'h2A00; +defparam \z80_|execute_|setM1~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|setM1~52 ( +// Equation(s): +// \z80_|execute_|setM1~52_combout = (\z80_|execute_|setM1~48_combout & (\z80_|execute_|setM1~46_combout & (\z80_|execute_|setM1~16_combout & \z80_|execute_|setM1~51_combout ))) + + .dataa(\z80_|execute_|setM1~48_combout ), + .datab(\z80_|execute_|setM1~46_combout ), + .datac(\z80_|execute_|setM1~16_combout ), + .datad(\z80_|execute_|setM1~51_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~52_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~52 .lut_mask = 16'h8000; +defparam \z80_|execute_|setM1~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N4 +cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_17 ( +// Equation(s): +// \z80_|sequencer_|SYNTHESIZED_WIRE_17~combout = (\z80_|execute_|setM1~54_combout & (\z80_|sequencer_|DFFE_T5_ff~q & !\z80_|execute_|nextM~14_combout )) + + .dataa(\z80_|execute_|setM1~54_combout ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T5_ff~q ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_17~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_17 .lut_mask = 16'h00A0; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y12_N5 +dffeas \z80_|sequencer_|T6 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|SYNTHESIZED_WIRE_17~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|T6~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|T6 .is_wysiwyg = "true"; +defparam \z80_|sequencer_|T6 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|setM1~53 ( +// Equation(s): +// \z80_|execute_|setM1~53_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|execute_|setM1~41_combout ) # ((\z80_|sequencer_|T6~q & !\z80_|execute_|setM1~42_combout )))) # (!\z80_|execute_|setM1~52_combout & (((\z80_|sequencer_|T6~q & +// !\z80_|execute_|setM1~42_combout )))) + + .dataa(\z80_|execute_|setM1~52_combout ), + .datab(\z80_|execute_|setM1~41_combout ), + .datac(\z80_|sequencer_|T6~q ), + .datad(\z80_|execute_|setM1~42_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~53_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~53 .lut_mask = 16'h88F8; +defparam \z80_|execute_|setM1~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|setM1~54 ( +// Equation(s): +// \z80_|execute_|setM1~54_combout = (!\z80_|execute_|setM1~19_combout & (!\z80_|execute_|setM1~35_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|execute_|setM1~53_combout )))) + + .dataa(\z80_|execute_|setM1~19_combout ), + .datab(\z80_|execute_|setM1~35_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|execute_|setM1~53_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~54_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~54 .lut_mask = 16'h1011; +defparam \z80_|execute_|setM1~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N28 +cycloneive_lcell_comb \z80_|sequencer_|DFFE_M1_ff~0 ( +// Equation(s): +// \z80_|sequencer_|DFFE_M1_ff~0_combout = (\z80_|execute_|setM1~54_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # (\z80_|execute_|nextM~14_combout ))) + + .dataa(gnd), + .datab(\z80_|execute_|setM1~54_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|DFFE_M1_ff~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_M1_ff~0 .lut_mask = 16'hCCC0; +defparam \z80_|sequencer_|DFFE_M1_ff~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y13_N29 +dffeas \z80_|sequencer_|DFFE_M1_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|DFFE_M1_ff~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_M1_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_M1_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_M1_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X52_Y17_N4 +cycloneive_lcell_comb \z80_|resets_|x1~0 ( +// Equation(s): +// \z80_|resets_|x1~0_combout = !\reset~combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\reset~combout ), + .cin(gnd), + .combout(\z80_|resets_|x1~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|resets_|x1~0 .lut_mask = 16'h00FF; +defparam \z80_|resets_|x1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y16_N16 +cycloneive_lcell_comb \z80_|fpga_reset~feeder ( +// Equation(s): +// \z80_|fpga_reset~feeder_combout = VCC + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\z80_|fpga_reset~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|fpga_reset~feeder .lut_mask = 16'hFFFF; +defparam \z80_|fpga_reset~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X1_Y16_N17 +dffeas \z80_|fpga_reset ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|fpga_reset~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|fpga_reset~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|fpga_reset .is_wysiwyg = "true"; +defparam \z80_|fpga_reset .power_up = "low"; +// synopsys translate_on + +// Location: CLKCTRL_G2 +cycloneive_clkctrl \z80_|fpga_reset~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\z80_|fpga_reset~q }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\z80_|fpga_reset~clkctrl_outclk )); +// synopsys translate_off +defparam \z80_|fpga_reset~clkctrl .clock_type = "global clock"; +defparam \z80_|fpga_reset~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: FF_X52_Y17_N5 +dffeas \z80_|resets_|x1 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|resets_|x1~0_combout ), + .asdata(vcc), + .clrn(\z80_|fpga_reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|resets_|x1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|resets_|x1 .is_wysiwyg = "true"; +defparam \z80_|resets_|x1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X52_Y17_N12 +cycloneive_lcell_comb \z80_|resets_|x3 ( +// Equation(s): +// \z80_|resets_|x3~combout = (\z80_|resets_|x1~q ) # ((!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T2_ff~q )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|resets_|x1~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|resets_|x3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|resets_|x3 .lut_mask = 16'hF3F0; +defparam \z80_|resets_|x3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X52_Y17_N13 +dffeas \z80_|resets_|SYNTHESIZED_WIRE_12 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|resets_|x3~combout ), + .asdata(vcc), + .clrn(\z80_|fpga_reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|resets_|SYNTHESIZED_WIRE_12 .is_wysiwyg = "true"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_12 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N28 +cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_10~0 ( +// Equation(s): +// \z80_|resets_|SYNTHESIZED_WIRE_10~0_combout = !\z80_|resets_|SYNTHESIZED_WIRE_12~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .cin(gnd), + .combout(\z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|resets_|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h00FF; +defparam \z80_|resets_|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y13_N29 +dffeas \z80_|resets_|SYNTHESIZED_WIRE_10 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|resets_|SYNTHESIZED_WIRE_10 .is_wysiwyg = "true"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_10 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N22 +cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_9~feeder ( +// Equation(s): +// \z80_|resets_|SYNTHESIZED_WIRE_9~feeder_combout = \z80_|resets_|SYNTHESIZED_WIRE_10~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), + .cin(gnd), + .combout(\z80_|resets_|SYNTHESIZED_WIRE_9~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|resets_|SYNTHESIZED_WIRE_9~feeder .lut_mask = 16'hFF00; +defparam \z80_|resets_|SYNTHESIZED_WIRE_9~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y13_N23 +dffeas \z80_|resets_|SYNTHESIZED_WIRE_9 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|resets_|SYNTHESIZED_WIRE_9~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|resets_|SYNTHESIZED_WIRE_9 .is_wysiwyg = "true"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_9 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X36_Y13_N19 +dffeas \z80_|resets_|DFFE_intr_ff3 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|resets_|DFFE_intr_ff3~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|resets_|DFFE_intr_ff3 .is_wysiwyg = "true"; +defparam \z80_|resets_|DFFE_intr_ff3 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N0 +cycloneive_lcell_comb \z80_|resets_|clrpc_int~0 ( +// Equation(s): +// \z80_|resets_|clrpc_int~0_combout = (\z80_|sequencer_|DFFE_M1_ff~q & (((\z80_|resets_|clrpc_int~q )))) # (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|resets_|clrpc_int~q & !\z80_|resets_|x1~q )) # +// (!\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|resets_|clrpc_int~q )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|resets_|clrpc_int~q ), + .datad(\z80_|resets_|x1~q ), + .cin(gnd), + .combout(\z80_|resets_|clrpc_int~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|resets_|clrpc_int~0 .lut_mask = 16'hB0B4; +defparam \z80_|resets_|clrpc_int~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y13_N1 +dffeas \z80_|resets_|clrpc_int ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|resets_|clrpc_int~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|resets_|clrpc_int~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|resets_|clrpc_int .is_wysiwyg = "true"; +defparam \z80_|resets_|clrpc_int .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N18 +cycloneive_lcell_comb \z80_|resets_|clrpc~0 ( +// Equation(s): +// \z80_|resets_|clrpc~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_9~q ) # ((\z80_|resets_|SYNTHESIZED_WIRE_10~q ) # ((\z80_|resets_|DFFE_intr_ff3~q ) # (\z80_|resets_|clrpc_int~q ))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), + .datac(\z80_|resets_|DFFE_intr_ff3~q ), + .datad(\z80_|resets_|clrpc_int~q ), + .cin(gnd), + .combout(\z80_|resets_|clrpc~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|resets_|clrpc~0 .lut_mask = 16'hFFFE; +defparam \z80_|resets_|clrpc~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N2 +cycloneive_lcell_comb \z80_|address_latch_|abusz[0] ( +// Equation(s): +// \z80_|address_latch_|abusz [0] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[0]~3_combout ) + + .dataa(gnd), + .datab(\z80_|resets_|clrpc~0_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|db_lo_as[0]~3_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [0]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[0] .lut_mask = 16'h3300; +defparam \z80_|address_latch_|abusz[0] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N24 cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[0]~0 ( // Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[0]~0_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [0]))) +// \z80_|address_pins_|DFFE_apin_latch[0]~0_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [0])) - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), + .dataa(\z80_|address_latch_|abusz [0]), + .datab(\z80_|execute_|ctl_apin_mux~2_combout ), .datac(gnd), - .datad(\z80_|address_latch_|abusz [0]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), .cin(gnd), .combout(\z80_|address_pins_|DFFE_apin_latch[0]~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[0]~0 .lut_mask = 16'hDD88; +defparam \z80_|address_pins_|DFFE_apin_latch[0]~0 .lut_mask = 16'hEE22; defparam \z80_|address_pins_|DFFE_apin_latch[0]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y16_N19 +// Location: FF_X34_Y11_N25 dffeas \z80_|address_pins_|DFFE_apin_latch[0] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|address_pins_|DFFE_apin_latch[0]~0_combout ), @@ -53241,7 +53008,7 @@ dffeas \z80_|address_pins_|DFFE_apin_latch[0] ( .aload(gnd), .sclr(gnd), .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~1_combout ), .devclrn(devclrn), .devpor(devpor), .q(\z80_|address_pins_|DFFE_apin_latch [0]), @@ -53251,228 +53018,228 @@ defparam \z80_|address_pins_|DFFE_apin_latch[0] .is_wysiwyg = "true"; defparam \z80_|address_pins_|DFFE_apin_latch[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y14_N12 -cycloneive_lcell_comb \D[0]~59 ( +// Location: LCCOMB_X23_Y14_N20 +cycloneive_lcell_comb \D[0]~47 ( // Equation(s): -// \D[0]~59_combout = (\Equal2~0_combout & (\D[0]~51_combout )) # (!\Equal2~0_combout & ((\D[0]~106_combout ))) +// \D[0]~47_combout = (\Equal2~0_combout & (\D[0]~44_combout )) # (!\Equal2~0_combout & ((\D[0]~83_combout ))) .dataa(\Equal2~0_combout ), - .datab(\D[0]~51_combout ), - .datac(\D[0]~106_combout ), + .datab(\D[0]~44_combout ), + .datac(\D[0]~83_combout ), .datad(gnd), .cin(gnd), - .combout(\D[0]~59_combout ), + .combout(\D[0]~47_combout ), .cout()); // synopsys translate_off -defparam \D[0]~59 .lut_mask = 16'hD8D8; -defparam \D[0]~59 .sum_lutc_input = "datac"; +defparam \D[0]~47 .lut_mask = 16'hD8D8; +defparam \D[0]~47 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N8 -cycloneive_lcell_comb \D[0]~60 ( +// Location: LCCOMB_X24_Y14_N24 +cycloneive_lcell_comb \D[0]~48 ( // Equation(s): -// \D[0]~60_combout = (\Equal2~1_combout & (\D[0]~59_combout & ((\z80_|data_pins_|dout [0]) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) # (!\Equal2~1_combout & ((\z80_|data_pins_|dout [0]) # ((!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) +// \D[0]~48_combout = (\z80_|data_pins_|dout [0] & (((\D[0]~47_combout ) # (!\Equal2~1_combout )))) # (!\z80_|data_pins_|dout [0] & (!\z80_|pin_control_|bus_db_pin_oe~15_combout & ((\D[0]~47_combout ) # (!\Equal2~1_combout )))) + + .dataa(\z80_|data_pins_|dout [0]), + .datab(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .datac(\Equal2~1_combout ), + .datad(\D[0]~47_combout ), + .cin(gnd), + .combout(\D[0]~48_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~48 .lut_mask = 16'hBB0B; +defparam \D[0]~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N12 +cycloneive_lcell_comb \D[1]~49 ( +// Equation(s): +// \D[1]~49_combout = (\Equal2~0_combout & (\D[1]~30_combout )) # (!\Equal2~0_combout & ((\D[1]~81_combout ))) + + .dataa(\D[1]~30_combout ), + .datab(gnd), + .datac(\Equal2~0_combout ), + .datad(\D[1]~81_combout ), + .cin(gnd), + .combout(\D[1]~49_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~49 .lut_mask = 16'hAFA0; +defparam \D[1]~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N18 +cycloneive_lcell_comb \D[1]~50 ( +// Equation(s): +// \D[1]~50_combout = (\Equal2~1_combout & (\D[1]~49_combout & ((\z80_|data_pins_|dout [1]) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout )))) # (!\Equal2~1_combout & ((\z80_|data_pins_|dout [1]) # ((!\z80_|pin_control_|bus_db_pin_oe~15_combout )))) .dataa(\Equal2~1_combout ), - .datab(\z80_|data_pins_|dout [0]), - .datac(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datad(\D[0]~59_combout ), + .datab(\z80_|data_pins_|dout [1]), + .datac(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .datad(\D[1]~49_combout ), .cin(gnd), - .combout(\D[0]~60_combout ), + .combout(\D[1]~50_combout ), .cout()); // synopsys translate_off -defparam \D[0]~60 .lut_mask = 16'hCF45; -defparam \D[0]~60 .sum_lutc_input = "datac"; +defparam \D[1]~50 .lut_mask = 16'hCF45; +defparam \D[1]~50 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y18_N20 -cycloneive_lcell_comb \D[1]~61 ( +// Location: LCCOMB_X23_Y10_N2 +cycloneive_lcell_comb \D[2]~51 ( // Equation(s): -// \D[1]~61_combout = (\Equal2~0_combout & (\D[1]~32_combout )) # (!\Equal2~0_combout & ((\D[1]~103_combout ))) +// \D[2]~51_combout = (\Equal2~0_combout & (\D[2]~37_combout )) # (!\Equal2~0_combout & ((\D[2]~82_combout ))) - .dataa(\Equal2~0_combout ), + .dataa(\D[2]~37_combout ), .datab(gnd), - .datac(\D[1]~32_combout ), - .datad(\D[1]~103_combout ), + .datac(\Equal2~0_combout ), + .datad(\D[2]~82_combout ), .cin(gnd), - .combout(\D[1]~61_combout ), + .combout(\D[2]~51_combout ), .cout()); // synopsys translate_off -defparam \D[1]~61 .lut_mask = 16'hF5A0; -defparam \D[1]~61 .sum_lutc_input = "datac"; +defparam \D[2]~51 .lut_mask = 16'hAFA0; +defparam \D[2]~51 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y18_N22 -cycloneive_lcell_comb \D[1]~62 ( +// Location: LCCOMB_X24_Y10_N2 +cycloneive_lcell_comb \D[2]~52 ( // Equation(s): -// \D[1]~62_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout & (\z80_|data_pins_|dout [1] & ((\D[1]~61_combout ) # (!\Equal2~1_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\D[1]~61_combout )) # (!\Equal2~1_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datab(\Equal2~1_combout ), - .datac(\z80_|data_pins_|dout [1]), - .datad(\D[1]~61_combout ), - .cin(gnd), - .combout(\D[1]~62_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~62 .lut_mask = 16'hF531; -defparam \D[1]~62 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N12 -cycloneive_lcell_comb \D[2]~63 ( -// Equation(s): -// \D[2]~63_combout = (\Equal2~0_combout & (\D[2]~104_combout )) # (!\Equal2~0_combout & ((\D[2]~105_combout ))) - - .dataa(\Equal2~0_combout ), - .datab(gnd), - .datac(\D[2]~104_combout ), - .datad(\D[2]~105_combout ), - .cin(gnd), - .combout(\D[2]~63_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~63 .lut_mask = 16'hF5A0; -defparam \D[2]~63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N26 -cycloneive_lcell_comb \D[2]~64 ( -// Equation(s): -// \D[2]~64_combout = (\z80_|data_pins_|dout [2] & (((\D[2]~63_combout )) # (!\Equal2~1_combout ))) # (!\z80_|data_pins_|dout [2] & (!\z80_|pin_control_|bus_db_pin_oe~14_combout & ((\D[2]~63_combout ) # (!\Equal2~1_combout )))) +// \D[2]~52_combout = (\z80_|data_pins_|dout [2] & (((\D[2]~51_combout )) # (!\Equal2~1_combout ))) # (!\z80_|data_pins_|dout [2] & (!\z80_|pin_control_|bus_db_pin_oe~15_combout & ((\D[2]~51_combout ) # (!\Equal2~1_combout )))) .dataa(\z80_|data_pins_|dout [2]), .datab(\Equal2~1_combout ), - .datac(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datad(\D[2]~63_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .datad(\D[2]~51_combout ), .cin(gnd), - .combout(\D[2]~64_combout ), + .combout(\D[2]~52_combout ), .cout()); // synopsys translate_off -defparam \D[2]~64 .lut_mask = 16'hAF23; -defparam \D[2]~64 .sum_lutc_input = "datac"; +defparam \D[2]~52 .lut_mask = 16'hAF23; +defparam \D[2]~52 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N2 -cycloneive_lcell_comb \D[3]~75 ( +// Location: LCCOMB_X23_Y14_N18 +cycloneive_lcell_comb \D[3]~58 ( // Equation(s): -// \D[3]~75_combout = (\Equal2~0_combout & (\D[3]~69_combout )) # (!\Equal2~0_combout & ((\D[3]~108_combout ))) - - .dataa(\D[3]~69_combout ), - .datab(gnd), - .datac(\Equal2~0_combout ), - .datad(\D[3]~108_combout ), - .cin(gnd), - .combout(\D[3]~75_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~75 .lut_mask = 16'hAFA0; -defparam \D[3]~75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y15_N20 -cycloneive_lcell_comb \D[3]~76 ( -// Equation(s): -// \D[3]~76_combout = (\z80_|data_pins_|dout [3] & (((\D[3]~75_combout )) # (!\Equal2~1_combout ))) # (!\z80_|data_pins_|dout [3] & (!\z80_|pin_control_|bus_db_pin_oe~14_combout & ((\D[3]~75_combout ) # (!\Equal2~1_combout )))) - - .dataa(\z80_|data_pins_|dout [3]), - .datab(\Equal2~1_combout ), - .datac(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datad(\D[3]~75_combout ), - .cin(gnd), - .combout(\D[3]~76_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~76 .lut_mask = 16'hAF23; -defparam \D[3]~76 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N24 -cycloneive_lcell_comb \D[4]~82 ( -// Equation(s): -// \D[4]~82_combout = (\Equal2~0_combout & (\D[4]~81_combout )) # (!\Equal2~0_combout & ((\D[4]~109_combout ))) +// \D[3]~58_combout = (\Equal2~0_combout & (\D[3]~57_combout )) # (!\Equal2~0_combout & ((\D[3]~85_combout ))) .dataa(\Equal2~0_combout ), - .datab(\D[4]~81_combout ), + .datab(\D[3]~57_combout ), .datac(gnd), - .datad(\D[4]~109_combout ), + .datad(\D[3]~85_combout ), .cin(gnd), - .combout(\D[4]~82_combout ), + .combout(\D[3]~58_combout ), .cout()); // synopsys translate_off -defparam \D[4]~82 .lut_mask = 16'hDD88; -defparam \D[4]~82 .sum_lutc_input = "datac"; +defparam \D[3]~58 .lut_mask = 16'hDD88; +defparam \D[3]~58 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N26 -cycloneive_lcell_comb \D[4]~83 ( +// Location: LCCOMB_X24_Y14_N18 +cycloneive_lcell_comb \D[3]~59 ( // Equation(s): -// \D[4]~83_combout = (\Equal2~1_combout & (\D[4]~82_combout & ((\z80_|data_pins_|dout [4]) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) # (!\Equal2~1_combout & ((\z80_|data_pins_|dout [4]) # ((!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) +// \D[3]~59_combout = (\z80_|data_pins_|dout [3] & (((\D[3]~58_combout ) # (!\Equal2~1_combout )))) # (!\z80_|data_pins_|dout [3] & (!\z80_|pin_control_|bus_db_pin_oe~15_combout & ((\D[3]~58_combout ) # (!\Equal2~1_combout )))) + + .dataa(\z80_|data_pins_|dout [3]), + .datab(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .datac(\Equal2~1_combout ), + .datad(\D[3]~58_combout ), + .cin(gnd), + .combout(\D[3]~59_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~59 .lut_mask = 16'hBB0B; +defparam \D[3]~59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N0 +cycloneive_lcell_comb \D[4]~65 ( +// Equation(s): +// \D[4]~65_combout = (\Equal2~0_combout & (\D[4]~64_combout )) # (!\Equal2~0_combout & ((\D[4]~86_combout ))) + + .dataa(gnd), + .datab(\D[4]~64_combout ), + .datac(\Equal2~0_combout ), + .datad(\D[4]~86_combout ), + .cin(gnd), + .combout(\D[4]~65_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~65 .lut_mask = 16'hCFC0; +defparam \D[4]~65 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N22 +cycloneive_lcell_comb \D[4]~66 ( +// Equation(s): +// \D[4]~66_combout = (\Equal2~1_combout & (\D[4]~65_combout & ((\z80_|data_pins_|dout [4]) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout )))) # (!\Equal2~1_combout & ((\z80_|data_pins_|dout [4]) # ((!\z80_|pin_control_|bus_db_pin_oe~15_combout )))) .dataa(\Equal2~1_combout ), .datab(\z80_|data_pins_|dout [4]), - .datac(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datad(\D[4]~82_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .datad(\D[4]~65_combout ), .cin(gnd), - .combout(\D[4]~83_combout ), + .combout(\D[4]~66_combout ), .cout()); // synopsys translate_off -defparam \D[4]~83 .lut_mask = 16'hCF45; -defparam \D[4]~83 .sum_lutc_input = "datac"; +defparam \D[4]~66 .lut_mask = 16'hCF45; +defparam \D[4]~66 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N24 -cycloneive_lcell_comb \D[6]~92 ( +// Location: LCCOMB_X24_Y10_N20 +cycloneive_lcell_comb \D[6]~70 ( // Equation(s): -// \D[6]~92_combout = (\Equal2~0_combout & ((\D[6]~86_combout ))) # (!\Equal2~0_combout & (\D[6]~111_combout )) +// \D[6]~70_combout = (\Equal2~0_combout & ((\D[6]~69_combout ))) # (!\Equal2~0_combout & (\D[6]~88_combout )) - .dataa(gnd), - .datab(\Equal2~0_combout ), - .datac(\D[6]~111_combout ), - .datad(\D[6]~86_combout ), + .dataa(\Equal2~0_combout ), + .datab(gnd), + .datac(\D[6]~88_combout ), + .datad(\D[6]~69_combout ), .cin(gnd), - .combout(\D[6]~92_combout ), + .combout(\D[6]~70_combout ), .cout()); // synopsys translate_off -defparam \D[6]~92 .lut_mask = 16'hFC30; -defparam \D[6]~92 .sum_lutc_input = "datac"; +defparam \D[6]~70 .lut_mask = 16'hFA50; +defparam \D[6]~70 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N10 -cycloneive_lcell_comb \D[6]~93 ( +// Location: LCCOMB_X24_Y10_N10 +cycloneive_lcell_comb \D[6]~71 ( // Equation(s): -// \D[6]~93_combout = (\Equal2~1_combout & (\D[6]~92_combout & ((\z80_|data_pins_|dout [6]) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) # (!\Equal2~1_combout & ((\z80_|data_pins_|dout [6]) # ((!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) +// \D[6]~71_combout = (\z80_|data_pins_|dout [6] & (((\D[6]~70_combout )) # (!\Equal2~1_combout ))) # (!\z80_|data_pins_|dout [6] & (!\z80_|pin_control_|bus_db_pin_oe~15_combout & ((\D[6]~70_combout ) # (!\Equal2~1_combout )))) - .dataa(\Equal2~1_combout ), - .datab(\z80_|data_pins_|dout [6]), - .datac(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datad(\D[6]~92_combout ), + .dataa(\z80_|data_pins_|dout [6]), + .datab(\Equal2~1_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .datad(\D[6]~70_combout ), .cin(gnd), - .combout(\D[6]~93_combout ), + .combout(\D[6]~71_combout ), .cout()); // synopsys translate_off -defparam \D[6]~93 .lut_mask = 16'hCF45; -defparam \D[6]~93 .sum_lutc_input = "datac"; +defparam \D[6]~71 .lut_mask = 16'hAF23; +defparam \D[6]~71 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X43_Y17_N0 +// Location: LCCOMB_X27_Y13_N28 cycloneive_lcell_comb \z80_|nM1_int~3 ( // Equation(s): -// \z80_|nM1_int~3_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # (\z80_|sequencer_|DFFE_M1_ff~q ))) +// \z80_|nM1_int~3_combout = (\z80_|execute_|setM1~54_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # (\z80_|sequencer_|DFFE_M1_ff~q ))) - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|setM1~52_combout ), + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|execute_|setM1~54_combout ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), .cin(gnd), .combout(\z80_|nM1_int~3_combout ), .cout()); // synopsys translate_off -defparam \z80_|nM1_int~3 .lut_mask = 16'hFC00; +defparam \z80_|nM1_int~3 .lut_mask = 16'hCC88; defparam \z80_|nM1_int~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X43_Y17_N1 +// Location: FF_X27_Y13_N29 dffeas \z80_|memory_ifc_|SYNTHESIZED_WIRE_16 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|nM1_int~3_combout ), @@ -53491,7 +53258,7 @@ defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_16 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_16 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X43_Y17_N30 +// Location: LCCOMB_X27_Y11_N4 cycloneive_lcell_comb \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder ( // Equation(s): // \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder_combout = \z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q @@ -53508,7 +53275,7 @@ defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder .lut_mask = 16'hFF00; defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X43_Y17_N31 +// Location: FF_X27_Y11_N5 dffeas \z80_|memory_ifc_|SYNTHESIZED_WIRE_17 ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder_combout ), @@ -53527,7 +53294,7 @@ defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_17 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_17 .power_up = "low"; // synopsys translate_on -// Location: FF_X43_Y17_N25 +// Location: FF_X27_Y11_N11 dffeas \z80_|memory_ifc_|DFFE_mreq_ff2 ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), @@ -53546,32 +53313,32 @@ defparam \z80_|memory_ifc_|DFFE_mreq_ff2 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|DFFE_mreq_ff2 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X43_Y17_N24 +// Location: LCCOMB_X27_Y11_N10 cycloneive_lcell_comb \z80_|memory_ifc_|nMREQ_out~0 ( // Equation(s): // \z80_|memory_ifc_|nMREQ_out~0_combout = (\z80_|memory_ifc_|wait_mwr~q ) # ((\z80_|memory_ifc_|mwr_wr~q ) # ((\z80_|memory_ifc_|SYNTHESIZED_WIRE_17~q & !\z80_|memory_ifc_|DFFE_mreq_ff2~q ))) - .dataa(\z80_|memory_ifc_|SYNTHESIZED_WIRE_17~q ), - .datab(\z80_|memory_ifc_|wait_mwr~q ), + .dataa(\z80_|memory_ifc_|wait_mwr~q ), + .datab(\z80_|memory_ifc_|SYNTHESIZED_WIRE_17~q ), .datac(\z80_|memory_ifc_|DFFE_mreq_ff2~q ), .datad(\z80_|memory_ifc_|mwr_wr~q ), .cin(gnd), .combout(\z80_|memory_ifc_|nMREQ_out~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|memory_ifc_|nMREQ_out~0 .lut_mask = 16'hFFCE; +defparam \z80_|memory_ifc_|nMREQ_out~0 .lut_mask = 16'hFFAE; defparam \z80_|memory_ifc_|nMREQ_out~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X43_Y17_N2 +// Location: LCCOMB_X27_Y11_N16 cycloneive_lcell_comb \z80_|memory_ifc_|nMREQ_out~1 ( // Equation(s): -// \z80_|memory_ifc_|nMREQ_out~1_combout = (!\z80_|memory_ifc_|wait_mrd~q & (!\z80_|memory_ifc_|nMREQ_out~0_combout & (!\z80_|memory_ifc_|DFFE_mrd_ff3~q & !\z80_|memory_ifc_|nRD_out~0_combout ))) +// \z80_|memory_ifc_|nMREQ_out~1_combout = (!\z80_|memory_ifc_|wait_mrd~q & (!\z80_|memory_ifc_|nRD_out~0_combout & (!\z80_|memory_ifc_|DFFE_mrd_ff3~q & !\z80_|memory_ifc_|nMREQ_out~0_combout ))) .dataa(\z80_|memory_ifc_|wait_mrd~q ), - .datab(\z80_|memory_ifc_|nMREQ_out~0_combout ), + .datab(\z80_|memory_ifc_|nRD_out~0_combout ), .datac(\z80_|memory_ifc_|DFFE_mrd_ff3~q ), - .datad(\z80_|memory_ifc_|nRD_out~0_combout ), + .datad(\z80_|memory_ifc_|nMREQ_out~0_combout ), .cin(gnd), .combout(\z80_|memory_ifc_|nMREQ_out~1_combout ), .cout()); @@ -53593,7 +53360,7 @@ defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl .cl defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N0 +// Location: LCCOMB_X3_Y23_N28 cycloneive_lcell_comb \ula_|i2c_loader_|state.Idle~feeder ( // Equation(s): // \ula_|i2c_loader_|state.Idle~feeder_combout = VCC @@ -53610,7 +53377,7 @@ defparam \ula_|i2c_loader_|state.Idle~feeder .lut_mask = 16'hFFFF; defparam \ula_|i2c_loader_|state.Idle~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X4_Y24_N0 +// Location: LCCOMB_X1_Y24_N22 cycloneive_lcell_comb \ula_|i2c_loader_|divider[0]~15 ( // Equation(s): // \ula_|i2c_loader_|divider[0]~15_combout = !\ula_|i2c_loader_|divider [0] @@ -53627,7 +53394,7 @@ defparam \ula_|i2c_loader_|divider[0]~15 .lut_mask = 16'h0F0F; defparam \ula_|i2c_loader_|divider[0]~15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X4_Y24_N1 +// Location: FF_X1_Y24_N23 dffeas \ula_|i2c_loader_|divider[0] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[0]~15_combout ), @@ -53646,14 +53413,14 @@ defparam \ula_|i2c_loader_|divider[0] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X4_Y24_N10 +// Location: LCCOMB_X1_Y24_N0 cycloneive_lcell_comb \ula_|i2c_loader_|divider[1]~5 ( // Equation(s): -// \ula_|i2c_loader_|divider[1]~5_combout = (\ula_|i2c_loader_|divider [1] & (\ula_|i2c_loader_|divider [0] $ (VCC))) # (!\ula_|i2c_loader_|divider [1] & (\ula_|i2c_loader_|divider [0] & VCC)) -// \ula_|i2c_loader_|divider[1]~6 = CARRY((\ula_|i2c_loader_|divider [1] & \ula_|i2c_loader_|divider [0])) +// \ula_|i2c_loader_|divider[1]~5_combout = (\ula_|i2c_loader_|divider [0] & (\ula_|i2c_loader_|divider [1] $ (VCC))) # (!\ula_|i2c_loader_|divider [0] & (\ula_|i2c_loader_|divider [1] & VCC)) +// \ula_|i2c_loader_|divider[1]~6 = CARRY((\ula_|i2c_loader_|divider [0] & \ula_|i2c_loader_|divider [1])) - .dataa(\ula_|i2c_loader_|divider [1]), - .datab(\ula_|i2c_loader_|divider [0]), + .dataa(\ula_|i2c_loader_|divider [0]), + .datab(\ula_|i2c_loader_|divider [1]), .datac(gnd), .datad(vcc), .cin(gnd), @@ -53664,7 +53431,7 @@ defparam \ula_|i2c_loader_|divider[1]~5 .lut_mask = 16'h6688; defparam \ula_|i2c_loader_|divider[1]~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X4_Y24_N11 +// Location: FF_X1_Y24_N1 dffeas \ula_|i2c_loader_|divider[1] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[1]~5_combout ), @@ -53683,25 +53450,25 @@ defparam \ula_|i2c_loader_|divider[1] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X4_Y24_N12 +// Location: LCCOMB_X1_Y24_N2 cycloneive_lcell_comb \ula_|i2c_loader_|divider[2]~7 ( // Equation(s): // \ula_|i2c_loader_|divider[2]~7_combout = (\ula_|i2c_loader_|divider [2] & (!\ula_|i2c_loader_|divider[1]~6 )) # (!\ula_|i2c_loader_|divider [2] & ((\ula_|i2c_loader_|divider[1]~6 ) # (GND))) // \ula_|i2c_loader_|divider[2]~8 = CARRY((!\ula_|i2c_loader_|divider[1]~6 ) # (!\ula_|i2c_loader_|divider [2])) - .dataa(\ula_|i2c_loader_|divider [2]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|i2c_loader_|divider [2]), .datac(gnd), .datad(vcc), .cin(\ula_|i2c_loader_|divider[1]~6 ), .combout(\ula_|i2c_loader_|divider[2]~7_combout ), .cout(\ula_|i2c_loader_|divider[2]~8 )); // synopsys translate_off -defparam \ula_|i2c_loader_|divider[2]~7 .lut_mask = 16'h5A5F; +defparam \ula_|i2c_loader_|divider[2]~7 .lut_mask = 16'h3C3F; defparam \ula_|i2c_loader_|divider[2]~7 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X4_Y24_N13 +// Location: FF_X1_Y24_N3 dffeas \ula_|i2c_loader_|divider[2] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[2]~7_combout ), @@ -53720,7 +53487,7 @@ defparam \ula_|i2c_loader_|divider[2] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X4_Y24_N14 +// Location: LCCOMB_X1_Y24_N4 cycloneive_lcell_comb \ula_|i2c_loader_|divider[3]~9 ( // Equation(s): // \ula_|i2c_loader_|divider[3]~9_combout = (\ula_|i2c_loader_|divider [3] & (\ula_|i2c_loader_|divider[2]~8 $ (GND))) # (!\ula_|i2c_loader_|divider [3] & (!\ula_|i2c_loader_|divider[2]~8 & VCC)) @@ -53738,7 +53505,7 @@ defparam \ula_|i2c_loader_|divider[3]~9 .lut_mask = 16'hC30C; defparam \ula_|i2c_loader_|divider[3]~9 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X4_Y24_N15 +// Location: FF_X1_Y24_N5 dffeas \ula_|i2c_loader_|divider[3] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[3]~9_combout ), @@ -53757,25 +53524,42 @@ defparam \ula_|i2c_loader_|divider[3] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X4_Y24_N16 +// Location: LCCOMB_X1_Y24_N12 +cycloneive_lcell_comb \ula_|i2c_loader_|WideAnd0~0 ( +// Equation(s): +// \ula_|i2c_loader_|WideAnd0~0_combout = (((!\ula_|i2c_loader_|divider [2]) # (!\ula_|i2c_loader_|divider [3])) # (!\ula_|i2c_loader_|divider [1])) # (!\ula_|i2c_loader_|divider [0]) + + .dataa(\ula_|i2c_loader_|divider [0]), + .datab(\ula_|i2c_loader_|divider [1]), + .datac(\ula_|i2c_loader_|divider [3]), + .datad(\ula_|i2c_loader_|divider [2]), + .cin(gnd), + .combout(\ula_|i2c_loader_|WideAnd0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|WideAnd0~0 .lut_mask = 16'h7FFF; +defparam \ula_|i2c_loader_|WideAnd0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y24_N6 cycloneive_lcell_comb \ula_|i2c_loader_|divider[4]~11 ( // Equation(s): // \ula_|i2c_loader_|divider[4]~11_combout = (\ula_|i2c_loader_|divider [4] & (!\ula_|i2c_loader_|divider[3]~10 )) # (!\ula_|i2c_loader_|divider [4] & ((\ula_|i2c_loader_|divider[3]~10 ) # (GND))) // \ula_|i2c_loader_|divider[4]~12 = CARRY((!\ula_|i2c_loader_|divider[3]~10 ) # (!\ula_|i2c_loader_|divider [4])) - .dataa(gnd), - .datab(\ula_|i2c_loader_|divider [4]), + .dataa(\ula_|i2c_loader_|divider [4]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\ula_|i2c_loader_|divider[3]~10 ), .combout(\ula_|i2c_loader_|divider[4]~11_combout ), .cout(\ula_|i2c_loader_|divider[4]~12 )); // synopsys translate_off -defparam \ula_|i2c_loader_|divider[4]~11 .lut_mask = 16'h3C3F; +defparam \ula_|i2c_loader_|divider[4]~11 .lut_mask = 16'h5A5F; defparam \ula_|i2c_loader_|divider[4]~11 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X4_Y24_N17 +// Location: FF_X1_Y24_N7 dffeas \ula_|i2c_loader_|divider[4] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[4]~11_combout ), @@ -53794,24 +53578,24 @@ defparam \ula_|i2c_loader_|divider[4] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X4_Y24_N18 +// Location: LCCOMB_X1_Y24_N8 cycloneive_lcell_comb \ula_|i2c_loader_|divider[5]~13 ( // Equation(s): -// \ula_|i2c_loader_|divider[5]~13_combout = \ula_|i2c_loader_|divider[4]~12 $ (!\ula_|i2c_loader_|divider [5]) +// \ula_|i2c_loader_|divider[5]~13_combout = \ula_|i2c_loader_|divider [5] $ (!\ula_|i2c_loader_|divider[4]~12 ) .dataa(gnd), - .datab(gnd), + .datab(\ula_|i2c_loader_|divider [5]), .datac(gnd), - .datad(\ula_|i2c_loader_|divider [5]), + .datad(gnd), .cin(\ula_|i2c_loader_|divider[4]~12 ), .combout(\ula_|i2c_loader_|divider[5]~13_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|divider[5]~13 .lut_mask = 16'hF00F; +defparam \ula_|i2c_loader_|divider[5]~13 .lut_mask = 16'hC3C3; defparam \ula_|i2c_loader_|divider[5]~13 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X4_Y24_N19 +// Location: FF_X1_Y24_N9 dffeas \ula_|i2c_loader_|divider[5] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[5]~13_combout ), @@ -53830,41 +53614,24 @@ defparam \ula_|i2c_loader_|divider[5] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X4_Y24_N22 -cycloneive_lcell_comb \ula_|i2c_loader_|WideAnd0~0 ( -// Equation(s): -// \ula_|i2c_loader_|WideAnd0~0_combout = (((!\ula_|i2c_loader_|divider [2]) # (!\ula_|i2c_loader_|divider [3])) # (!\ula_|i2c_loader_|divider [0])) # (!\ula_|i2c_loader_|divider [1]) - - .dataa(\ula_|i2c_loader_|divider [1]), - .datab(\ula_|i2c_loader_|divider [0]), - .datac(\ula_|i2c_loader_|divider [3]), - .datad(\ula_|i2c_loader_|divider [2]), - .cin(gnd), - .combout(\ula_|i2c_loader_|WideAnd0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|WideAnd0~0 .lut_mask = 16'h7FFF; -defparam \ula_|i2c_loader_|WideAnd0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y24_N8 +// Location: LCCOMB_X1_Y24_N30 cycloneive_lcell_comb \ula_|i2c_loader_|WideAnd0 ( // Equation(s): -// \ula_|i2c_loader_|WideAnd0~combout = ((\ula_|i2c_loader_|WideAnd0~0_combout ) # (!\ula_|i2c_loader_|divider [4])) # (!\ula_|i2c_loader_|divider [5]) +// \ula_|i2c_loader_|WideAnd0~combout = (\ula_|i2c_loader_|WideAnd0~0_combout ) # ((!\ula_|i2c_loader_|divider [4]) # (!\ula_|i2c_loader_|divider [5])) - .dataa(gnd), - .datab(\ula_|i2c_loader_|divider [5]), - .datac(\ula_|i2c_loader_|WideAnd0~0_combout ), + .dataa(\ula_|i2c_loader_|WideAnd0~0_combout ), + .datab(gnd), + .datac(\ula_|i2c_loader_|divider [5]), .datad(\ula_|i2c_loader_|divider [4]), .cin(gnd), .combout(\ula_|i2c_loader_|WideAnd0~combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|WideAnd0 .lut_mask = 16'hF3FF; +defparam \ula_|i2c_loader_|WideAnd0 .lut_mask = 16'hAFFF; defparam \ula_|i2c_loader_|WideAnd0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X1_Y23_N1 +// Location: FF_X3_Y23_N29 dffeas \ula_|i2c_loader_|state.Idle ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|state.Idle~feeder_combout ), @@ -53883,7 +53650,7 @@ defparam \ula_|i2c_loader_|state.Idle .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|state.Idle .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N4 +// Location: LCCOMB_X3_Y23_N0 cycloneive_lcell_comb \ula_|i2c_loader_|phase~0 ( // Equation(s): // \ula_|i2c_loader_|phase~0_combout = (!\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|state.Idle~q ) @@ -53900,7 +53667,7 @@ defparam \ula_|i2c_loader_|phase~0 .lut_mask = 16'h0F00; defparam \ula_|i2c_loader_|phase~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X1_Y23_N5 +// Location: FF_X3_Y23_N1 dffeas \ula_|i2c_loader_|phase[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|phase~0_combout ), @@ -53919,7 +53686,7 @@ defparam \ula_|i2c_loader_|phase[0] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|phase[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N14 +// Location: LCCOMB_X3_Y23_N2 cycloneive_lcell_comb \ula_|i2c_loader_|phase~1 ( // Equation(s): // \ula_|i2c_loader_|phase~1_combout = (\ula_|i2c_loader_|state.Idle~q & (\ula_|i2c_loader_|phase [0] $ (\ula_|i2c_loader_|phase [1]))) @@ -53936,7 +53703,7 @@ defparam \ula_|i2c_loader_|phase~1 .lut_mask = 16'h3C00; defparam \ula_|i2c_loader_|phase~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X1_Y23_N15 +// Location: FF_X3_Y23_N3 dffeas \ula_|i2c_loader_|phase[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|phase~1_combout ), @@ -53955,59 +53722,182 @@ defparam \ula_|i2c_loader_|phase[1] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|phase[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y24_N2 +// Location: LCCOMB_X2_Y24_N2 cycloneive_lcell_comb \ula_|i2c_loader_|nbit~5 ( // Equation(s): -// \ula_|i2c_loader_|nbit~5_combout = (!\ula_|i2c_loader_|nbit [0]) # (!\ula_|i2c_loader_|state.Data~q ) +// \ula_|i2c_loader_|nbit~5_combout = (!\ula_|i2c_loader_|state.Data~q ) # (!\ula_|i2c_loader_|nbit [0]) - .dataa(\ula_|i2c_loader_|state.Data~q ), + .dataa(gnd), .datab(gnd), .datac(\ula_|i2c_loader_|nbit [0]), - .datad(gnd), + .datad(\ula_|i2c_loader_|state.Data~q ), .cin(gnd), .combout(\ula_|i2c_loader_|nbit~5_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|nbit~5 .lut_mask = 16'h5F5F; +defparam \ula_|i2c_loader_|nbit~5 .lut_mask = 16'h0FFF; defparam \ula_|i2c_loader_|nbit~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N14 -cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[0]~8 ( +// Location: LCCOMB_X2_Y23_N16 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Idle~0 ( // Equation(s): -// \ula_|i2c_loader_|thisbyte[0]~8_combout = \ula_|i2c_loader_|thisbyte [0] $ (VCC) -// \ula_|i2c_loader_|thisbyte[0]~9 = CARRY(\ula_|i2c_loader_|thisbyte [0]) +// \ula_|i2c_loader_|state.Idle~0_combout = (!\ula_|i2c_loader_|state.Stop~q & (!\ula_|i2c_loader_|state.Ack~q & (!\ula_|i2c_loader_|state.Start~q & !\ula_|i2c_loader_|state.Pause~q ))) - .dataa(gnd), - .datab(\ula_|i2c_loader_|thisbyte [0]), - .datac(gnd), - .datad(vcc), + .dataa(\ula_|i2c_loader_|state.Stop~q ), + .datab(\ula_|i2c_loader_|state.Ack~q ), + .datac(\ula_|i2c_loader_|state.Start~q ), + .datad(\ula_|i2c_loader_|state.Pause~q ), .cin(gnd), - .combout(\ula_|i2c_loader_|thisbyte[0]~8_combout ), - .cout(\ula_|i2c_loader_|thisbyte[0]~9 )); + .combout(\ula_|i2c_loader_|state.Idle~0_combout ), + .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[0]~8 .lut_mask = 16'h33CC; -defparam \ula_|i2c_loader_|thisbyte[0]~8 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|state.Idle~0 .lut_mask = 16'h0001; +defparam \ula_|i2c_loader_|state.Idle~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N8 +// Location: LCCOMB_X1_Y23_N30 cycloneive_lcell_comb \ula_|i2c_loader_|Mux42~0 ( // Equation(s): -// \ula_|i2c_loader_|Mux42~0_combout = (\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|phase [1]) +// \ula_|i2c_loader_|Mux42~0_combout = (\ula_|i2c_loader_|phase [1] & \ula_|i2c_loader_|phase [0]) .dataa(gnd), - .datab(gnd), + .datab(\ula_|i2c_loader_|phase [1]), .datac(\ula_|i2c_loader_|phase [0]), - .datad(\ula_|i2c_loader_|phase [1]), + .datad(gnd), .cin(gnd), .combout(\ula_|i2c_loader_|Mux42~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|Mux42~0 .lut_mask = 16'hF000; +defparam \ula_|i2c_loader_|Mux42~0 .lut_mask = 16'hC0C0; defparam \ula_|i2c_loader_|Mux42~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N28 +// Location: LCCOMB_X2_Y24_N0 +cycloneive_lcell_comb \ula_|i2c_loader_|nbit~6 ( +// Equation(s): +// \ula_|i2c_loader_|nbit~6_combout = (\ula_|i2c_loader_|nbit [1] $ (!\ula_|i2c_loader_|nbit [0])) # (!\ula_|i2c_loader_|state.Data~q ) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|state.Data~q ), + .datac(\ula_|i2c_loader_|nbit [1]), + .datad(\ula_|i2c_loader_|nbit [0]), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbit~6_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit~6 .lut_mask = 16'hF33F; +defparam \ula_|i2c_loader_|nbit~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y24_N1 +dffeas \ula_|i2c_loader_|nbit[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|nbit~6_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2c_loader_|nbit[0]~4_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|nbit [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit[1] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|nbit[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y24_N30 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Done~0 ( +// Equation(s): +// \ula_|i2c_loader_|state.Done~0_combout = (!\ula_|i2c_loader_|nbit [2] & (!\ula_|i2c_loader_|nbit [0] & (\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|nbit [1]))) + + .dataa(\ula_|i2c_loader_|nbit [2]), + .datab(\ula_|i2c_loader_|nbit [0]), + .datac(\ula_|i2c_loader_|state.Data~q ), + .datad(\ula_|i2c_loader_|nbit [1]), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Done~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Done~0 .lut_mask = 16'h0010; +defparam \ula_|i2c_loader_|state.Done~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N18 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Ack~0 ( +// Equation(s): +// \ula_|i2c_loader_|state.Ack~0_combout = ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Done~0_combout ) # (!\ula_|i2c_loader_|state.Idle~0_combout )))) # (!\ula_|i2c_loader_|state.Idle~q ) + + .dataa(\ula_|i2c_loader_|state.Idle~0_combout ), + .datab(\ula_|i2c_loader_|Mux42~0_combout ), + .datac(\ula_|i2c_loader_|state.Done~0_combout ), + .datad(\ula_|i2c_loader_|state.Idle~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Ack~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Ack~0 .lut_mask = 16'hC4FF; +defparam \ula_|i2c_loader_|state.Ack~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N24 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Ack~1 ( +// Equation(s): +// \ula_|i2c_loader_|state.Ack~1_combout = (\ula_|i2c_loader_|WideAnd0~combout & (((\ula_|i2c_loader_|state.Ack~q )))) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|state.Ack~0_combout & (\ula_|i2c_loader_|state.Data~q )) # +// (!\ula_|i2c_loader_|state.Ack~0_combout & ((\ula_|i2c_loader_|state.Ack~q ))))) + + .dataa(\ula_|i2c_loader_|WideAnd0~combout ), + .datab(\ula_|i2c_loader_|state.Data~q ), + .datac(\ula_|i2c_loader_|state.Ack~q ), + .datad(\ula_|i2c_loader_|state.Ack~0_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Ack~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Ack~1 .lut_mask = 16'hE4F0; +defparam \ula_|i2c_loader_|state.Ack~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y23_N25 +dffeas \ula_|i2c_loader_|state.Ack ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|state.Ack~1_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|state.Ack~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Ack .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|state.Ack .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N2 +cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~2 ( +// Equation(s): +// \ula_|i2c_loader_|nbit[0]~2_combout = (\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|phase [0])) # (!\ula_|i2c_loader_|phase [1]))) # (!\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|state.Ack~q )))) + + .dataa(\ula_|i2c_loader_|phase [1]), + .datab(\ula_|i2c_loader_|state.Ack~q ), + .datac(\ula_|i2c_loader_|phase [0]), + .datad(\ula_|i2c_loader_|state.Data~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbit[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit[0]~2 .lut_mask = 16'h5F33; +defparam \ula_|i2c_loader_|nbit[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N26 cycloneive_lcell_comb \ula_|i2c_loader_|nbyte~4 ( // Equation(s): // \ula_|i2c_loader_|nbyte~4_combout = (\ula_|i2c_loader_|state.Start~q ) # ((\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|nbyte [0] $ (!\ula_|i2c_loader_|nbyte [1])))) @@ -54024,14 +53914,14 @@ defparam \ula_|i2c_loader_|nbyte~4 .lut_mask = 16'hFF84; defparam \ula_|i2c_loader_|nbyte~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N26 +// Location: LCCOMB_X1_Y23_N4 cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[0]~7 ( // Equation(s): -// \ula_|i2c_loader_|thisbyte[0]~7_combout = (\ula_|i2c_loader_|phase [1] & \ula_|i2c_loader_|state.Ack~q ) +// \ula_|i2c_loader_|thisbyte[0]~7_combout = (\ula_|i2c_loader_|state.Ack~q & \ula_|i2c_loader_|phase [1]) .dataa(gnd), - .datab(\ula_|i2c_loader_|phase [1]), - .datac(\ula_|i2c_loader_|state.Ack~q ), + .datab(\ula_|i2c_loader_|state.Ack~q ), + .datac(\ula_|i2c_loader_|phase [1]), .datad(gnd), .cin(gnd), .combout(\ula_|i2c_loader_|thisbyte[0]~7_combout ), @@ -54051,13 +53941,13 @@ defparam \I2C_SDAT~input .bus_hold = "false"; defparam \I2C_SDAT~input .simulate_z_as = "z"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N20 +// Location: LCCOMB_X2_Y23_N20 cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~1 ( // Equation(s): -// \ula_|i2c_loader_|nbyte[0]~1_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|nbyte [0]) # ((\ula_|i2c_loader_|nbyte [1])))) # (!\ula_|i2c_loader_|phase [0] & (((\I2C_SDAT~input_o )))) +// \ula_|i2c_loader_|nbyte[0]~1_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|nbyte [1]) # ((\ula_|i2c_loader_|nbyte [0])))) # (!\ula_|i2c_loader_|phase [0] & (((\I2C_SDAT~input_o )))) - .dataa(\ula_|i2c_loader_|nbyte [0]), - .datab(\ula_|i2c_loader_|nbyte [1]), + .dataa(\ula_|i2c_loader_|nbyte [1]), + .datab(\ula_|i2c_loader_|nbyte [0]), .datac(\ula_|i2c_loader_|phase [0]), .datad(\I2C_SDAT~input_o ), .cin(gnd), @@ -54068,7 +53958,7 @@ defparam \ula_|i2c_loader_|nbyte[0]~1 .lut_mask = 16'hEFE0; defparam \ula_|i2c_loader_|nbyte[0]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N18 +// Location: LCCOMB_X2_Y23_N10 cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~2 ( // Equation(s): // \ula_|i2c_loader_|nbyte[0]~2_combout = (\ula_|i2c_loader_|state.Start~q & (\ula_|i2c_loader_|Mux42~0_combout )) # (!\ula_|i2c_loader_|state.Start~q & (((\ula_|i2c_loader_|thisbyte[0]~7_combout & \ula_|i2c_loader_|nbyte[0]~1_combout )))) @@ -54085,24 +53975,24 @@ defparam \ula_|i2c_loader_|nbyte[0]~2 .lut_mask = 16'hD888; defparam \ula_|i2c_loader_|nbyte[0]~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N24 +// Location: LCCOMB_X2_Y23_N8 cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~3 ( // Equation(s): -// \ula_|i2c_loader_|nbyte[0]~3_combout = (!\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|state.Idle~q & \ula_|i2c_loader_|nbyte[0]~2_combout )) +// \ula_|i2c_loader_|nbyte[0]~3_combout = (\ula_|i2c_loader_|state.Idle~q & (!\ula_|i2c_loader_|WideAnd0~combout & \ula_|i2c_loader_|nbyte[0]~2_combout )) .dataa(gnd), - .datab(\ula_|i2c_loader_|WideAnd0~combout ), - .datac(\ula_|i2c_loader_|state.Idle~q ), + .datab(\ula_|i2c_loader_|state.Idle~q ), + .datac(\ula_|i2c_loader_|WideAnd0~combout ), .datad(\ula_|i2c_loader_|nbyte[0]~2_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|nbyte[0]~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|nbyte[0]~3 .lut_mask = 16'h3000; +defparam \ula_|i2c_loader_|nbyte[0]~3 .lut_mask = 16'h0C00; defparam \ula_|i2c_loader_|nbyte[0]~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X1_Y23_N29 +// Location: FF_X2_Y23_N27 dffeas \ula_|i2c_loader_|nbyte[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|nbyte~4_combout ), @@ -54121,632 +54011,41 @@ defparam \ula_|i2c_loader_|nbyte[1] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|nbyte[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N18 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Stop~0 ( -// Equation(s): -// \ula_|i2c_loader_|state.Stop~0_combout = (!\ula_|i2c_loader_|nbyte [0] & (!\ula_|i2c_loader_|nbyte [1] & \ula_|i2c_loader_|state.Ack~q )) - - .dataa(\ula_|i2c_loader_|nbyte [0]), - .datab(\ula_|i2c_loader_|nbyte [1]), - .datac(\ula_|i2c_loader_|state.Ack~q ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Stop~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Stop~0 .lut_mask = 16'h1010; -defparam \ula_|i2c_loader_|state.Stop~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y24_N2 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Stop~1 ( -// Equation(s): -// \ula_|i2c_loader_|state.Stop~1_combout = (\ula_|i2c_loader_|WideAnd0~combout & (((\ula_|i2c_loader_|state.Stop~q )))) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Stop~0_combout ))) # -// (!\ula_|i2c_loader_|Mux42~0_combout & (\ula_|i2c_loader_|state.Stop~q )))) - - .dataa(\ula_|i2c_loader_|WideAnd0~combout ), - .datab(\ula_|i2c_loader_|Mux42~0_combout ), - .datac(\ula_|i2c_loader_|state.Stop~q ), - .datad(\ula_|i2c_loader_|state.Stop~0_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Stop~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Stop~1 .lut_mask = 16'hF4B0; -defparam \ula_|i2c_loader_|state.Stop~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X1_Y24_N3 -dffeas \ula_|i2c_loader_|state.Stop ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|state.Stop~1_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|state.Stop~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Stop .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|state.Stop .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y24_N20 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Idle~0 ( -// Equation(s): -// \ula_|i2c_loader_|state.Idle~0_combout = (!\ula_|i2c_loader_|state.Start~q & (!\ula_|i2c_loader_|state.Stop~q & (!\ula_|i2c_loader_|state.Pause~q & !\ula_|i2c_loader_|state.Ack~q ))) - - .dataa(\ula_|i2c_loader_|state.Start~q ), - .datab(\ula_|i2c_loader_|state.Stop~q ), - .datac(\ula_|i2c_loader_|state.Pause~q ), - .datad(\ula_|i2c_loader_|state.Ack~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Idle~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Idle~0 .lut_mask = 16'h0001; -defparam \ula_|i2c_loader_|state.Idle~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y24_N0 -cycloneive_lcell_comb \ula_|i2c_loader_|nbit~0 ( -// Equation(s): -// \ula_|i2c_loader_|nbit~0_combout = (\ula_|i2c_loader_|nbit [2] $ (((!\ula_|i2c_loader_|nbit [0] & !\ula_|i2c_loader_|nbit [1])))) # (!\ula_|i2c_loader_|state.Data~q ) - - .dataa(\ula_|i2c_loader_|state.Data~q ), - .datab(\ula_|i2c_loader_|nbit [0]), - .datac(\ula_|i2c_loader_|nbit [2]), - .datad(\ula_|i2c_loader_|nbit [1]), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbit~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit~0 .lut_mask = 16'hF5D7; -defparam \ula_|i2c_loader_|nbit~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X3_Y24_N1 -dffeas \ula_|i2c_loader_|nbit[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|nbit~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2c_loader_|nbit[0]~4_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|nbit [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit[2] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|nbit[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y24_N6 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Done~0 ( -// Equation(s): -// \ula_|i2c_loader_|state.Done~0_combout = (!\ula_|i2c_loader_|nbit [1] & (!\ula_|i2c_loader_|nbit [2] & (\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|nbit [0]))) - - .dataa(\ula_|i2c_loader_|nbit [1]), - .datab(\ula_|i2c_loader_|nbit [2]), - .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|nbit [0]), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Done~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Done~0 .lut_mask = 16'h0010; -defparam \ula_|i2c_loader_|state.Done~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N12 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Ack~0 ( -// Equation(s): -// \ula_|i2c_loader_|state.Ack~0_combout = ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Done~0_combout ) # (!\ula_|i2c_loader_|state.Idle~0_combout )))) # (!\ula_|i2c_loader_|state.Idle~q ) - - .dataa(\ula_|i2c_loader_|Mux42~0_combout ), - .datab(\ula_|i2c_loader_|state.Idle~0_combout ), - .datac(\ula_|i2c_loader_|state.Idle~q ), - .datad(\ula_|i2c_loader_|state.Done~0_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Ack~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Ack~0 .lut_mask = 16'hAF2F; -defparam \ula_|i2c_loader_|state.Ack~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N30 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Ack~1 ( -// Equation(s): -// \ula_|i2c_loader_|state.Ack~1_combout = (\ula_|i2c_loader_|state.Ack~0_combout & ((\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|state.Ack~q )) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|state.Data~q ))))) # -// (!\ula_|i2c_loader_|state.Ack~0_combout & (((\ula_|i2c_loader_|state.Ack~q )))) - - .dataa(\ula_|i2c_loader_|state.Ack~0_combout ), - .datab(\ula_|i2c_loader_|WideAnd0~combout ), - .datac(\ula_|i2c_loader_|state.Ack~q ), - .datad(\ula_|i2c_loader_|state.Data~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Ack~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Ack~1 .lut_mask = 16'hF2D0; -defparam \ula_|i2c_loader_|state.Ack~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X2_Y24_N31 -dffeas \ula_|i2c_loader_|state.Ack ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|state.Ack~1_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|state.Ack~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Ack .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|state.Ack .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N30 -cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[1]~5 ( -// Equation(s): -// \ula_|i2c_loader_|nbyte[1]~5_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|nbyte [0]) # ((\ula_|i2c_loader_|nbyte [1])))) # (!\ula_|i2c_loader_|phase [0] & (((\I2C_SDAT~input_o )))) - - .dataa(\ula_|i2c_loader_|nbyte [0]), - .datab(\ula_|i2c_loader_|nbyte [1]), - .datac(\ula_|i2c_loader_|phase [0]), - .datad(\I2C_SDAT~input_o ), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbyte[1]~5_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbyte[1]~5 .lut_mask = 16'hEFE0; -defparam \ula_|i2c_loader_|nbyte[1]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N8 -cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[0]~18 ( -// Equation(s): -// \ula_|i2c_loader_|thisbyte[0]~18_combout = (\ula_|i2c_loader_|phase [1] & (\ula_|i2c_loader_|state.Ack~q & (!\ula_|i2c_loader_|WideAnd0~combout & \ula_|i2c_loader_|nbyte[1]~5_combout ))) - - .dataa(\ula_|i2c_loader_|phase [1]), - .datab(\ula_|i2c_loader_|state.Ack~q ), - .datac(\ula_|i2c_loader_|WideAnd0~combout ), - .datad(\ula_|i2c_loader_|nbyte[1]~5_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|thisbyte[0]~18_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[0]~18 .lut_mask = 16'h0800; -defparam \ula_|i2c_loader_|thisbyte[0]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X2_Y23_N15 -dffeas \ula_|i2c_loader_|thisbyte[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|thisbyte[0]~8_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(!\ula_|i2c_loader_|phase [0]), - .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|thisbyte [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[0] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|thisbyte[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N16 -cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[1]~10 ( -// Equation(s): -// \ula_|i2c_loader_|thisbyte[1]~10_combout = (\ula_|i2c_loader_|thisbyte [1] & (!\ula_|i2c_loader_|thisbyte[0]~9 )) # (!\ula_|i2c_loader_|thisbyte [1] & ((\ula_|i2c_loader_|thisbyte[0]~9 ) # (GND))) -// \ula_|i2c_loader_|thisbyte[1]~11 = CARRY((!\ula_|i2c_loader_|thisbyte[0]~9 ) # (!\ula_|i2c_loader_|thisbyte [1])) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|thisbyte [1]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2c_loader_|thisbyte[0]~9 ), - .combout(\ula_|i2c_loader_|thisbyte[1]~10_combout ), - .cout(\ula_|i2c_loader_|thisbyte[1]~11 )); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[1]~10 .lut_mask = 16'h3C3F; -defparam \ula_|i2c_loader_|thisbyte[1]~10 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X2_Y23_N17 -dffeas \ula_|i2c_loader_|thisbyte[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|thisbyte[1]~10_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(!\ula_|i2c_loader_|phase [0]), - .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|thisbyte [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[1] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|thisbyte[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N18 -cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[2]~12 ( -// Equation(s): -// \ula_|i2c_loader_|thisbyte[2]~12_combout = (\ula_|i2c_loader_|thisbyte [2] & (\ula_|i2c_loader_|thisbyte[1]~11 $ (GND))) # (!\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte[1]~11 & VCC)) -// \ula_|i2c_loader_|thisbyte[2]~13 = CARRY((\ula_|i2c_loader_|thisbyte [2] & !\ula_|i2c_loader_|thisbyte[1]~11 )) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|thisbyte [2]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2c_loader_|thisbyte[1]~11 ), - .combout(\ula_|i2c_loader_|thisbyte[2]~12_combout ), - .cout(\ula_|i2c_loader_|thisbyte[2]~13 )); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[2]~12 .lut_mask = 16'hC30C; -defparam \ula_|i2c_loader_|thisbyte[2]~12 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X2_Y23_N19 -dffeas \ula_|i2c_loader_|thisbyte[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|thisbyte[2]~12_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(!\ula_|i2c_loader_|phase [0]), - .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|thisbyte [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[2] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|thisbyte[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N20 -cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[3]~14 ( -// Equation(s): -// \ula_|i2c_loader_|thisbyte[3]~14_combout = (\ula_|i2c_loader_|thisbyte [3] & (!\ula_|i2c_loader_|thisbyte[2]~13 )) # (!\ula_|i2c_loader_|thisbyte [3] & ((\ula_|i2c_loader_|thisbyte[2]~13 ) # (GND))) -// \ula_|i2c_loader_|thisbyte[3]~15 = CARRY((!\ula_|i2c_loader_|thisbyte[2]~13 ) # (!\ula_|i2c_loader_|thisbyte [3])) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|thisbyte [3]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2c_loader_|thisbyte[2]~13 ), - .combout(\ula_|i2c_loader_|thisbyte[3]~14_combout ), - .cout(\ula_|i2c_loader_|thisbyte[3]~15 )); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[3]~14 .lut_mask = 16'h3C3F; -defparam \ula_|i2c_loader_|thisbyte[3]~14 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X2_Y23_N21 -dffeas \ula_|i2c_loader_|thisbyte[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|thisbyte[3]~14_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(!\ula_|i2c_loader_|phase [0]), - .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|thisbyte [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[3] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|thisbyte[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N2 -cycloneive_lcell_comb \ula_|i2c_loader_|Equal2~0 ( -// Equation(s): -// \ula_|i2c_loader_|Equal2~0_combout = (\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte [1] & (!\ula_|i2c_loader_|thisbyte [0] & !\ula_|i2c_loader_|thisbyte [3]))) - - .dataa(\ula_|i2c_loader_|thisbyte [2]), - .datab(\ula_|i2c_loader_|thisbyte [1]), - .datac(\ula_|i2c_loader_|thisbyte [0]), - .datad(\ula_|i2c_loader_|thisbyte [3]), - .cin(gnd), - .combout(\ula_|i2c_loader_|Equal2~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|Equal2~0 .lut_mask = 16'h0002; -defparam \ula_|i2c_loader_|Equal2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y24_N26 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~0 ( -// Equation(s): -// \ula_|i2c_loader_|state.Pause~0_combout = (\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|phase [0])) # (!\ula_|i2c_loader_|phase [1]))) # (!\ula_|i2c_loader_|state.Data~q & (((\ula_|i2c_loader_|state.Stop~q )))) - - .dataa(\ula_|i2c_loader_|phase [1]), - .datab(\ula_|i2c_loader_|state.Stop~q ), - .datac(\ula_|i2c_loader_|phase [0]), - .datad(\ula_|i2c_loader_|state.Data~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Pause~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Pause~0 .lut_mask = 16'h5FCC; -defparam \ula_|i2c_loader_|state.Pause~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N22 -cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[4]~16 ( -// Equation(s): -// \ula_|i2c_loader_|thisbyte[4]~16_combout = \ula_|i2c_loader_|thisbyte [4] $ (!\ula_|i2c_loader_|thisbyte[3]~15 ) - - .dataa(\ula_|i2c_loader_|thisbyte [4]), - .datab(gnd), - .datac(gnd), - .datad(gnd), - .cin(\ula_|i2c_loader_|thisbyte[3]~15 ), - .combout(\ula_|i2c_loader_|thisbyte[4]~16_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[4]~16 .lut_mask = 16'hA5A5; -defparam \ula_|i2c_loader_|thisbyte[4]~16 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X2_Y23_N23 -dffeas \ula_|i2c_loader_|thisbyte[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|thisbyte[4]~16_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(!\ula_|i2c_loader_|phase [0]), - .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|thisbyte [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[4] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|thisbyte[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N20 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~1 ( -// Equation(s): -// \ula_|i2c_loader_|state.Pause~1_combout = (\ula_|i2c_loader_|state.Pause~0_combout & ((!\ula_|i2c_loader_|thisbyte [4]) # (!\ula_|i2c_loader_|Equal2~0_combout ))) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|Equal2~0_combout ), - .datac(\ula_|i2c_loader_|state.Pause~0_combout ), - .datad(\ula_|i2c_loader_|thisbyte [4]), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Pause~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Pause~1 .lut_mask = 16'h30F0; -defparam \ula_|i2c_loader_|state.Pause~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y24_N24 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Done~2 ( -// Equation(s): -// \ula_|i2c_loader_|state.Done~2_combout = (\ula_|i2c_loader_|scl_out~0_combout & (((\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|state.Done~1_combout )) # (!\ula_|i2c_loader_|state.Pause~q ))) # (!\ula_|i2c_loader_|scl_out~0_combout & -// (\ula_|i2c_loader_|state.Data~q & ((!\ula_|i2c_loader_|state.Done~1_combout )))) - - .dataa(\ula_|i2c_loader_|scl_out~0_combout ), - .datab(\ula_|i2c_loader_|state.Data~q ), - .datac(\ula_|i2c_loader_|state.Pause~q ), - .datad(\ula_|i2c_loader_|state.Done~1_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Done~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Done~2 .lut_mask = 16'h0ACE; -defparam \ula_|i2c_loader_|state.Done~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y24_N18 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~2 ( -// Equation(s): -// \ula_|i2c_loader_|state.Pause~2_combout = ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Start~q ) # (!\ula_|i2c_loader_|state.Done~2_combout )))) # (!\ula_|i2c_loader_|state.Idle~q ) - - .dataa(\ula_|i2c_loader_|state.Done~2_combout ), - .datab(\ula_|i2c_loader_|Mux42~0_combout ), - .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|state.Idle~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Pause~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Pause~2 .lut_mask = 16'hC4FF; -defparam \ula_|i2c_loader_|state.Pause~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y24_N22 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~3 ( -// Equation(s): -// \ula_|i2c_loader_|state.Pause~3_combout = (\ula_|i2c_loader_|WideAnd0~combout & (((\ula_|i2c_loader_|state.Pause~q )))) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|state.Pause~2_combout & (\ula_|i2c_loader_|state.Pause~1_combout )) # -// (!\ula_|i2c_loader_|state.Pause~2_combout & ((\ula_|i2c_loader_|state.Pause~q ))))) - - .dataa(\ula_|i2c_loader_|state.Pause~1_combout ), - .datab(\ula_|i2c_loader_|WideAnd0~combout ), - .datac(\ula_|i2c_loader_|state.Pause~q ), - .datad(\ula_|i2c_loader_|state.Pause~2_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Pause~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Pause~3 .lut_mask = 16'hE2F0; -defparam \ula_|i2c_loader_|state.Pause~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X1_Y24_N23 -dffeas \ula_|i2c_loader_|state.Pause ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|state.Pause~3_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|state.Pause~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Pause .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|state.Pause .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y24_N30 -cycloneive_lcell_comb \ula_|i2c_loader_|state~25 ( -// Equation(s): -// \ula_|i2c_loader_|state~25_combout = ((\ula_|i2c_loader_|Mux42~0_combout & (\ula_|i2c_loader_|state.Pause~q & !\ula_|i2c_loader_|state.Start~q )) # (!\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Start~q )))) # -// (!\ula_|i2c_loader_|state.Idle~q ) - - .dataa(\ula_|i2c_loader_|state.Pause~q ), - .datab(\ula_|i2c_loader_|Mux42~0_combout ), - .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|state.Idle~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state~25_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state~25 .lut_mask = 16'h38FF; -defparam \ula_|i2c_loader_|state~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X1_Y24_N31 -dffeas \ula_|i2c_loader_|state.Start ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|state~25_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(!\ula_|i2c_loader_|WideAnd0~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|state.Start~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Start .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|state.Start .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N10 -cycloneive_lcell_comb \ula_|i2c_loader_|nbyte~0 ( -// Equation(s): -// \ula_|i2c_loader_|nbyte~0_combout = (\ula_|i2c_loader_|phase [0] & (!\ula_|i2c_loader_|nbyte [0] & !\ula_|i2c_loader_|state.Start~q )) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|phase [0]), - .datac(\ula_|i2c_loader_|nbyte [0]), - .datad(\ula_|i2c_loader_|state.Start~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbyte~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbyte~0 .lut_mask = 16'h000C; -defparam \ula_|i2c_loader_|nbyte~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X1_Y23_N11 -dffeas \ula_|i2c_loader_|nbyte[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|nbyte~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2c_loader_|nbyte[0]~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|nbyte [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbyte[0] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|nbyte[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N22 +// Location: LCCOMB_X2_Y23_N28 cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~1 ( // Equation(s): -// \ula_|i2c_loader_|nbit[0]~1_combout = (!\ula_|i2c_loader_|nbyte [0] & (!\ula_|i2c_loader_|nbyte [1] & !\ula_|i2c_loader_|state.Data~q )) +// \ula_|i2c_loader_|nbit[0]~1_combout = (!\ula_|i2c_loader_|nbyte [1] & (!\ula_|i2c_loader_|nbyte [0] & !\ula_|i2c_loader_|state.Data~q )) - .dataa(\ula_|i2c_loader_|nbyte [0]), - .datab(gnd), - .datac(\ula_|i2c_loader_|nbyte [1]), - .datad(\ula_|i2c_loader_|state.Data~q ), + .dataa(\ula_|i2c_loader_|nbyte [1]), + .datab(\ula_|i2c_loader_|nbyte [0]), + .datac(\ula_|i2c_loader_|state.Data~q ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2c_loader_|nbit[0]~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|nbit[0]~1 .lut_mask = 16'h0005; +defparam \ula_|i2c_loader_|nbit[0]~1 .lut_mask = 16'h0101; defparam \ula_|i2c_loader_|nbit[0]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N0 -cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~2 ( -// Equation(s): -// \ula_|i2c_loader_|nbit[0]~2_combout = (\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|phase [1])) # (!\ula_|i2c_loader_|phase [0]))) # (!\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|state.Ack~q )))) - - .dataa(\ula_|i2c_loader_|phase [0]), - .datab(\ula_|i2c_loader_|state.Data~q ), - .datac(\ula_|i2c_loader_|state.Ack~q ), - .datad(\ula_|i2c_loader_|phase [1]), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbit[0]~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit[0]~2 .lut_mask = 16'h47CF; -defparam \ula_|i2c_loader_|nbit[0]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N6 +// Location: LCCOMB_X2_Y23_N30 cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~3 ( // Equation(s): -// \ula_|i2c_loader_|nbit[0]~3_combout = (!\ula_|i2c_loader_|state.Start~q & ((\ula_|i2c_loader_|nbit[0]~1_combout ) # ((\ula_|i2c_loader_|nbit[0]~2_combout ) # (\ula_|i2c_loader_|state.Done~0_combout )))) +// \ula_|i2c_loader_|nbit[0]~3_combout = (!\ula_|i2c_loader_|state.Start~q & ((\ula_|i2c_loader_|nbit[0]~2_combout ) # ((\ula_|i2c_loader_|nbit[0]~1_combout ) # (\ula_|i2c_loader_|state.Done~0_combout )))) - .dataa(\ula_|i2c_loader_|nbit[0]~1_combout ), - .datab(\ula_|i2c_loader_|nbit[0]~2_combout ), - .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|state.Done~0_combout ), + .dataa(\ula_|i2c_loader_|nbit[0]~2_combout ), + .datab(\ula_|i2c_loader_|nbit[0]~1_combout ), + .datac(\ula_|i2c_loader_|state.Done~0_combout ), + .datad(\ula_|i2c_loader_|state.Start~q ), .cin(gnd), .combout(\ula_|i2c_loader_|nbit[0]~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|nbit[0]~3 .lut_mask = 16'h0F0E; +defparam \ula_|i2c_loader_|nbit[0]~3 .lut_mask = 16'h00FE; defparam \ula_|i2c_loader_|nbit[0]~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N4 +// Location: LCCOMB_X2_Y23_N0 cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~4 ( // Equation(s): // \ula_|i2c_loader_|nbit[0]~4_combout = (!\ula_|i2c_loader_|nbit[0]~3_combout & (\ula_|i2c_loader_|Mux42~0_combout & (!\ula_|i2c_loader_|WideAnd0~combout & \ula_|i2c_loader_|state.Idle~q ))) @@ -54763,7 +54062,7 @@ defparam \ula_|i2c_loader_|nbit[0]~4 .lut_mask = 16'h0400; defparam \ula_|i2c_loader_|nbit[0]~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y24_N3 +// Location: FF_X2_Y24_N3 dffeas \ula_|i2c_loader_|nbit[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|nbit~5_combout ), @@ -54782,27 +54081,27 @@ defparam \ula_|i2c_loader_|nbit[0] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|nbit[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y24_N12 -cycloneive_lcell_comb \ula_|i2c_loader_|nbit~6 ( +// Location: LCCOMB_X2_Y24_N12 +cycloneive_lcell_comb \ula_|i2c_loader_|nbit~0 ( // Equation(s): -// \ula_|i2c_loader_|nbit~6_combout = (\ula_|i2c_loader_|nbit [1] $ (!\ula_|i2c_loader_|nbit [0])) # (!\ula_|i2c_loader_|state.Data~q ) +// \ula_|i2c_loader_|nbit~0_combout = (\ula_|i2c_loader_|nbit [2] $ (((!\ula_|i2c_loader_|nbit [0] & !\ula_|i2c_loader_|nbit [1])))) # (!\ula_|i2c_loader_|state.Data~q ) .dataa(\ula_|i2c_loader_|state.Data~q ), - .datab(gnd), - .datac(\ula_|i2c_loader_|nbit [1]), - .datad(\ula_|i2c_loader_|nbit [0]), + .datab(\ula_|i2c_loader_|nbit [0]), + .datac(\ula_|i2c_loader_|nbit [2]), + .datad(\ula_|i2c_loader_|nbit [1]), .cin(gnd), - .combout(\ula_|i2c_loader_|nbit~6_combout ), + .combout(\ula_|i2c_loader_|nbit~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|nbit~6 .lut_mask = 16'hF55F; -defparam \ula_|i2c_loader_|nbit~6 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|nbit~0 .lut_mask = 16'hF5D7; +defparam \ula_|i2c_loader_|nbit~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y24_N13 -dffeas \ula_|i2c_loader_|nbit[1] ( +// Location: FF_X2_Y24_N13 +dffeas \ula_|i2c_loader_|nbit[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|nbit~6_combout ), + .d(\ula_|i2c_loader_|nbit~0_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -54811,22 +54110,22 @@ dffeas \ula_|i2c_loader_|nbit[1] ( .ena(\ula_|i2c_loader_|nbit[0]~4_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\ula_|i2c_loader_|nbit [1]), + .q(\ula_|i2c_loader_|nbit [2]), .prn(vcc)); // synopsys translate_off -defparam \ula_|i2c_loader_|nbit[1] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|nbit[1] .power_up = "low"; +defparam \ula_|i2c_loader_|nbit[2] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|nbit[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y24_N16 +// Location: LCCOMB_X2_Y24_N28 cycloneive_lcell_comb \ula_|i2c_loader_|state.Done~1 ( // Equation(s): -// \ula_|i2c_loader_|state.Done~1_combout = (!\ula_|i2c_loader_|nbit [1] & (!\ula_|i2c_loader_|nbit [2] & !\ula_|i2c_loader_|nbit [0])) +// \ula_|i2c_loader_|state.Done~1_combout = (!\ula_|i2c_loader_|nbit [2] & (!\ula_|i2c_loader_|nbit [0] & !\ula_|i2c_loader_|nbit [1])) - .dataa(\ula_|i2c_loader_|nbit [1]), - .datab(\ula_|i2c_loader_|nbit [2]), + .dataa(\ula_|i2c_loader_|nbit [2]), + .datab(\ula_|i2c_loader_|nbit [0]), .datac(gnd), - .datad(\ula_|i2c_loader_|nbit [0]), + .datad(\ula_|i2c_loader_|nbit [1]), .cin(gnd), .combout(\ula_|i2c_loader_|state.Done~1_combout ), .cout()); @@ -54835,75 +54134,75 @@ defparam \ula_|i2c_loader_|state.Done~1 .lut_mask = 16'h0011; defparam \ula_|i2c_loader_|state.Done~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N6 +// Location: LCCOMB_X1_Y23_N18 cycloneive_lcell_comb \ula_|i2c_loader_|state~27 ( // Equation(s): // \ula_|i2c_loader_|state~27_combout = ((!\ula_|i2c_loader_|state.Done~1_combout ) # (!\ula_|i2c_loader_|phase [0])) # (!\ula_|i2c_loader_|phase [1]) .dataa(\ula_|i2c_loader_|phase [1]), - .datab(gnd), - .datac(\ula_|i2c_loader_|phase [0]), - .datad(\ula_|i2c_loader_|state.Done~1_combout ), + .datab(\ula_|i2c_loader_|phase [0]), + .datac(\ula_|i2c_loader_|state.Done~1_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2c_loader_|state~27_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|state~27 .lut_mask = 16'h5FFF; +defparam \ula_|i2c_loader_|state~27 .lut_mask = 16'h7F7F; defparam \ula_|i2c_loader_|state~27 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N28 +// Location: LCCOMB_X2_Y23_N14 cycloneive_lcell_comb \ula_|i2c_loader_|state~24 ( // Equation(s): // \ula_|i2c_loader_|state~24_combout = (\ula_|i2c_loader_|state.Ack~q & ((\ula_|i2c_loader_|nbyte [0]) # (\ula_|i2c_loader_|nbyte [1]))) - .dataa(\ula_|i2c_loader_|nbyte [0]), - .datab(\ula_|i2c_loader_|nbyte [1]), - .datac(\ula_|i2c_loader_|state.Ack~q ), - .datad(gnd), + .dataa(gnd), + .datab(\ula_|i2c_loader_|nbyte [0]), + .datac(\ula_|i2c_loader_|nbyte [1]), + .datad(\ula_|i2c_loader_|state.Ack~q ), .cin(gnd), .combout(\ula_|i2c_loader_|state~24_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|state~24 .lut_mask = 16'hE0E0; +defparam \ula_|i2c_loader_|state~24 .lut_mask = 16'hFC00; defparam \ula_|i2c_loader_|state~24 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N16 +// Location: LCCOMB_X2_Y23_N2 cycloneive_lcell_comb \ula_|i2c_loader_|state~26 ( // Equation(s): -// \ula_|i2c_loader_|state~26_combout = (\ula_|i2c_loader_|phase [1] & (\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|state~24_combout )) +// \ula_|i2c_loader_|state~26_combout = (\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|state~24_combout & \ula_|i2c_loader_|phase [1])) - .dataa(\ula_|i2c_loader_|phase [1]), - .datab(gnd), - .datac(\ula_|i2c_loader_|phase [0]), - .datad(\ula_|i2c_loader_|state~24_combout ), + .dataa(gnd), + .datab(\ula_|i2c_loader_|phase [0]), + .datac(\ula_|i2c_loader_|state~24_combout ), + .datad(\ula_|i2c_loader_|phase [1]), .cin(gnd), .combout(\ula_|i2c_loader_|state~26_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|state~26 .lut_mask = 16'hA000; +defparam \ula_|i2c_loader_|state~26 .lut_mask = 16'hC000; defparam \ula_|i2c_loader_|state~26 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N28 +// Location: LCCOMB_X1_Y23_N0 cycloneive_lcell_comb \ula_|i2c_loader_|state.Data~0 ( // Equation(s): // \ula_|i2c_loader_|state.Data~0_combout = (\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|state~27_combout )) # (!\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|state~26_combout ))) - .dataa(\ula_|i2c_loader_|state~27_combout ), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|i2c_loader_|state~27_combout ), .datac(\ula_|i2c_loader_|state.Data~q ), .datad(\ula_|i2c_loader_|state~26_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|state.Data~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|state.Data~0 .lut_mask = 16'hAFA0; +defparam \ula_|i2c_loader_|state.Data~0 .lut_mask = 16'hCFC0; defparam \ula_|i2c_loader_|state.Data~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X1_Y24_N29 +// Location: FF_X1_Y23_N1 dffeas \ula_|i2c_loader_|state.Data ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|state.Data~0_combout ), @@ -54922,24 +54221,492 @@ defparam \ula_|i2c_loader_|state.Data .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|state.Data .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N12 -cycloneive_lcell_comb \ula_|i2c_loader_|scl_out~0 ( +// Location: LCCOMB_X1_Y23_N16 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Done~2 ( // Equation(s): -// \ula_|i2c_loader_|scl_out~0_combout = (!\ula_|i2c_loader_|state.Data~q & (!\ula_|i2c_loader_|state.Ack~q & !\ula_|i2c_loader_|state.Stop~q )) +// \ula_|i2c_loader_|state.Done~2_combout = (\ula_|i2c_loader_|scl_out~0_combout & (((\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|state.Done~1_combout )) # (!\ula_|i2c_loader_|state.Pause~q ))) # (!\ula_|i2c_loader_|scl_out~0_combout & +// (\ula_|i2c_loader_|state.Data~q & (!\ula_|i2c_loader_|state.Done~1_combout ))) + + .dataa(\ula_|i2c_loader_|scl_out~0_combout ), + .datab(\ula_|i2c_loader_|state.Data~q ), + .datac(\ula_|i2c_loader_|state.Done~1_combout ), + .datad(\ula_|i2c_loader_|state.Pause~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Done~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Done~2 .lut_mask = 16'h0CAE; +defparam \ula_|i2c_loader_|state.Done~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N10 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~1 ( +// Equation(s): +// \ula_|i2c_loader_|state.Pause~1_combout = ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Start~q ) # (!\ula_|i2c_loader_|state.Done~2_combout )))) # (!\ula_|i2c_loader_|state.Idle~q ) + + .dataa(\ula_|i2c_loader_|state.Start~q ), + .datab(\ula_|i2c_loader_|state.Done~2_combout ), + .datac(\ula_|i2c_loader_|Mux42~0_combout ), + .datad(\ula_|i2c_loader_|state.Idle~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Pause~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Pause~1 .lut_mask = 16'hB0FF; +defparam \ula_|i2c_loader_|state.Pause~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X5_Y23_N18 +cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[0]~8 ( +// Equation(s): +// \ula_|i2c_loader_|thisbyte[0]~8_combout = \ula_|i2c_loader_|thisbyte [0] $ (VCC) +// \ula_|i2c_loader_|thisbyte[0]~9 = CARRY(\ula_|i2c_loader_|thisbyte [0]) .dataa(gnd), + .datab(\ula_|i2c_loader_|thisbyte [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\ula_|i2c_loader_|thisbyte[0]~8_combout ), + .cout(\ula_|i2c_loader_|thisbyte[0]~9 )); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[0]~8 .lut_mask = 16'h33CC; +defparam \ula_|i2c_loader_|thisbyte[0]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X5_Y23_N28 +cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[1]~5 ( +// Equation(s): +// \ula_|i2c_loader_|nbyte[1]~5_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|nbyte [0]) # ((\ula_|i2c_loader_|nbyte [1])))) # (!\ula_|i2c_loader_|phase [0] & (((\I2C_SDAT~input_o )))) + + .dataa(\ula_|i2c_loader_|phase [0]), + .datab(\ula_|i2c_loader_|nbyte [0]), + .datac(\ula_|i2c_loader_|nbyte [1]), + .datad(\I2C_SDAT~input_o ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbyte[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbyte[1]~5 .lut_mask = 16'hFDA8; +defparam \ula_|i2c_loader_|nbyte[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X5_Y23_N16 +cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[0]~18 ( +// Equation(s): +// \ula_|i2c_loader_|thisbyte[0]~18_combout = (\ula_|i2c_loader_|state.Ack~q & (\ula_|i2c_loader_|phase [1] & (!\ula_|i2c_loader_|WideAnd0~combout & \ula_|i2c_loader_|nbyte[1]~5_combout ))) + + .dataa(\ula_|i2c_loader_|state.Ack~q ), + .datab(\ula_|i2c_loader_|phase [1]), + .datac(\ula_|i2c_loader_|WideAnd0~combout ), + .datad(\ula_|i2c_loader_|nbyte[1]~5_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|thisbyte[0]~18_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[0]~18 .lut_mask = 16'h0800; +defparam \ula_|i2c_loader_|thisbyte[0]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X5_Y23_N19 +dffeas \ula_|i2c_loader_|thisbyte[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|thisbyte[0]~8_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\ula_|i2c_loader_|phase [0]), + .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|thisbyte [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[0] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|thisbyte[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X5_Y23_N20 +cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[1]~10 ( +// Equation(s): +// \ula_|i2c_loader_|thisbyte[1]~10_combout = (\ula_|i2c_loader_|thisbyte [1] & (!\ula_|i2c_loader_|thisbyte[0]~9 )) # (!\ula_|i2c_loader_|thisbyte [1] & ((\ula_|i2c_loader_|thisbyte[0]~9 ) # (GND))) +// \ula_|i2c_loader_|thisbyte[1]~11 = CARRY((!\ula_|i2c_loader_|thisbyte[0]~9 ) # (!\ula_|i2c_loader_|thisbyte [1])) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|thisbyte [1]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2c_loader_|thisbyte[0]~9 ), + .combout(\ula_|i2c_loader_|thisbyte[1]~10_combout ), + .cout(\ula_|i2c_loader_|thisbyte[1]~11 )); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[1]~10 .lut_mask = 16'h3C3F; +defparam \ula_|i2c_loader_|thisbyte[1]~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X5_Y23_N21 +dffeas \ula_|i2c_loader_|thisbyte[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|thisbyte[1]~10_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\ula_|i2c_loader_|phase [0]), + .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|thisbyte [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[1] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|thisbyte[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X5_Y23_N22 +cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[2]~12 ( +// Equation(s): +// \ula_|i2c_loader_|thisbyte[2]~12_combout = (\ula_|i2c_loader_|thisbyte [2] & (\ula_|i2c_loader_|thisbyte[1]~11 $ (GND))) # (!\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte[1]~11 & VCC)) +// \ula_|i2c_loader_|thisbyte[2]~13 = CARRY((\ula_|i2c_loader_|thisbyte [2] & !\ula_|i2c_loader_|thisbyte[1]~11 )) + + .dataa(\ula_|i2c_loader_|thisbyte [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2c_loader_|thisbyte[1]~11 ), + .combout(\ula_|i2c_loader_|thisbyte[2]~12_combout ), + .cout(\ula_|i2c_loader_|thisbyte[2]~13 )); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[2]~12 .lut_mask = 16'hA50A; +defparam \ula_|i2c_loader_|thisbyte[2]~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X5_Y23_N23 +dffeas \ula_|i2c_loader_|thisbyte[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|thisbyte[2]~12_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\ula_|i2c_loader_|phase [0]), + .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|thisbyte [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[2] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|thisbyte[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X5_Y23_N24 +cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[3]~14 ( +// Equation(s): +// \ula_|i2c_loader_|thisbyte[3]~14_combout = (\ula_|i2c_loader_|thisbyte [3] & (!\ula_|i2c_loader_|thisbyte[2]~13 )) # (!\ula_|i2c_loader_|thisbyte [3] & ((\ula_|i2c_loader_|thisbyte[2]~13 ) # (GND))) +// \ula_|i2c_loader_|thisbyte[3]~15 = CARRY((!\ula_|i2c_loader_|thisbyte[2]~13 ) # (!\ula_|i2c_loader_|thisbyte [3])) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|thisbyte [3]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2c_loader_|thisbyte[2]~13 ), + .combout(\ula_|i2c_loader_|thisbyte[3]~14_combout ), + .cout(\ula_|i2c_loader_|thisbyte[3]~15 )); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[3]~14 .lut_mask = 16'h3C3F; +defparam \ula_|i2c_loader_|thisbyte[3]~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X5_Y23_N25 +dffeas \ula_|i2c_loader_|thisbyte[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|thisbyte[3]~14_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\ula_|i2c_loader_|phase [0]), + .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|thisbyte [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[3] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|thisbyte[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y23_N4 +cycloneive_lcell_comb \ula_|i2c_loader_|Equal2~0 ( +// Equation(s): +// \ula_|i2c_loader_|Equal2~0_combout = (\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte [3] & (!\ula_|i2c_loader_|thisbyte [1] & !\ula_|i2c_loader_|thisbyte [0]))) + + .dataa(\ula_|i2c_loader_|thisbyte [2]), + .datab(\ula_|i2c_loader_|thisbyte [3]), + .datac(\ula_|i2c_loader_|thisbyte [1]), + .datad(\ula_|i2c_loader_|thisbyte [0]), + .cin(gnd), + .combout(\ula_|i2c_loader_|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|Equal2~0 .lut_mask = 16'h0002; +defparam \ula_|i2c_loader_|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X5_Y23_N26 +cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[4]~16 ( +// Equation(s): +// \ula_|i2c_loader_|thisbyte[4]~16_combout = \ula_|i2c_loader_|thisbyte [4] $ (!\ula_|i2c_loader_|thisbyte[3]~15 ) + + .dataa(\ula_|i2c_loader_|thisbyte [4]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\ula_|i2c_loader_|thisbyte[3]~15 ), + .combout(\ula_|i2c_loader_|thisbyte[4]~16_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[4]~16 .lut_mask = 16'hA5A5; +defparam \ula_|i2c_loader_|thisbyte[4]~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X5_Y23_N27 +dffeas \ula_|i2c_loader_|thisbyte[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|thisbyte[4]~16_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\ula_|i2c_loader_|phase [0]), + .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|thisbyte [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[4] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|thisbyte[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y23_N30 +cycloneive_lcell_comb \ula_|i2c_loader_|Equal2~1 ( +// Equation(s): +// \ula_|i2c_loader_|Equal2~1_combout = (\ula_|i2c_loader_|Equal2~0_combout & \ula_|i2c_loader_|thisbyte [4]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|i2c_loader_|Equal2~0_combout ), + .datad(\ula_|i2c_loader_|thisbyte [4]), + .cin(gnd), + .combout(\ula_|i2c_loader_|Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|Equal2~1 .lut_mask = 16'hF000; +defparam \ula_|i2c_loader_|Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N22 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~0 ( +// Equation(s): +// \ula_|i2c_loader_|state.Pause~0_combout = (!\ula_|i2c_loader_|Equal2~1_combout & ((\ula_|i2c_loader_|state.Data~q & ((!\ula_|i2c_loader_|Mux42~0_combout ))) # (!\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|state.Stop~q )))) + + .dataa(\ula_|i2c_loader_|state.Stop~q ), + .datab(\ula_|i2c_loader_|Mux42~0_combout ), + .datac(\ula_|i2c_loader_|state.Data~q ), + .datad(\ula_|i2c_loader_|Equal2~1_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Pause~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Pause~0 .lut_mask = 16'h003A; +defparam \ula_|i2c_loader_|state.Pause~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N24 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~2 ( +// Equation(s): +// \ula_|i2c_loader_|state.Pause~2_combout = (\ula_|i2c_loader_|state.Pause~1_combout & ((\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|state.Pause~q )) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|state.Pause~0_combout ))))) # +// (!\ula_|i2c_loader_|state.Pause~1_combout & (((\ula_|i2c_loader_|state.Pause~q )))) + + .dataa(\ula_|i2c_loader_|state.Pause~1_combout ), + .datab(\ula_|i2c_loader_|WideAnd0~combout ), + .datac(\ula_|i2c_loader_|state.Pause~q ), + .datad(\ula_|i2c_loader_|state.Pause~0_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Pause~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Pause~2 .lut_mask = 16'hF2D0; +defparam \ula_|i2c_loader_|state.Pause~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X1_Y23_N25 +dffeas \ula_|i2c_loader_|state.Pause ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|state.Pause~2_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|state.Pause~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Pause .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|state.Pause .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y23_N26 +cycloneive_lcell_comb \ula_|i2c_loader_|state~25 ( +// Equation(s): +// \ula_|i2c_loader_|state~25_combout = ((\ula_|i2c_loader_|Mux42~0_combout & (\ula_|i2c_loader_|state.Pause~q & !\ula_|i2c_loader_|state.Start~q )) # (!\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Start~q )))) # +// (!\ula_|i2c_loader_|state.Idle~q ) + + .dataa(\ula_|i2c_loader_|state.Pause~q ), + .datab(\ula_|i2c_loader_|Mux42~0_combout ), + .datac(\ula_|i2c_loader_|state.Start~q ), + .datad(\ula_|i2c_loader_|state.Idle~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state~25_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state~25 .lut_mask = 16'h38FF; +defparam \ula_|i2c_loader_|state~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X3_Y23_N27 +dffeas \ula_|i2c_loader_|state.Start ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|state~25_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(!\ula_|i2c_loader_|WideAnd0~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|state.Start~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Start .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|state.Start .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N4 +cycloneive_lcell_comb \ula_|i2c_loader_|nbyte~0 ( +// Equation(s): +// \ula_|i2c_loader_|nbyte~0_combout = (\ula_|i2c_loader_|phase [0] & (!\ula_|i2c_loader_|nbyte [0] & !\ula_|i2c_loader_|state.Start~q )) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|phase [0]), + .datac(\ula_|i2c_loader_|nbyte [0]), + .datad(\ula_|i2c_loader_|state.Start~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbyte~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbyte~0 .lut_mask = 16'h000C; +defparam \ula_|i2c_loader_|nbyte~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y23_N5 +dffeas \ula_|i2c_loader_|nbyte[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|nbyte~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2c_loader_|nbyte[0]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|nbyte [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbyte[0] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|nbyte[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N12 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Stop~0 ( +// Equation(s): +// \ula_|i2c_loader_|state.Stop~0_combout = (!\ula_|i2c_loader_|nbyte [0] & (!\ula_|i2c_loader_|nbyte [1] & \ula_|i2c_loader_|state.Ack~q )) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|nbyte [0]), + .datac(\ula_|i2c_loader_|nbyte [1]), + .datad(\ula_|i2c_loader_|state.Ack~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Stop~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Stop~0 .lut_mask = 16'h0300; +defparam \ula_|i2c_loader_|state.Stop~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N6 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Stop~1 ( +// Equation(s): +// \ula_|i2c_loader_|state.Stop~1_combout = (\ula_|i2c_loader_|WideAnd0~combout & (((\ula_|i2c_loader_|state.Stop~q )))) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|Mux42~0_combout & (\ula_|i2c_loader_|state.Stop~0_combout )) # +// (!\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Stop~q ))))) + + .dataa(\ula_|i2c_loader_|state.Stop~0_combout ), + .datab(\ula_|i2c_loader_|WideAnd0~combout ), + .datac(\ula_|i2c_loader_|state.Stop~q ), + .datad(\ula_|i2c_loader_|Mux42~0_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Stop~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Stop~1 .lut_mask = 16'hE2F0; +defparam \ula_|i2c_loader_|state.Stop~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y23_N7 +dffeas \ula_|i2c_loader_|state.Stop ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|state.Stop~1_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|state.Stop~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Stop .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|state.Stop .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N22 +cycloneive_lcell_comb \ula_|i2c_loader_|scl_out~0 ( +// Equation(s): +// \ula_|i2c_loader_|scl_out~0_combout = (!\ula_|i2c_loader_|state.Stop~q & (!\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|state.Ack~q )) + + .dataa(\ula_|i2c_loader_|state.Stop~q ), .datab(\ula_|i2c_loader_|state.Data~q ), - .datac(\ula_|i2c_loader_|state.Ack~q ), - .datad(\ula_|i2c_loader_|state.Stop~q ), + .datac(gnd), + .datad(\ula_|i2c_loader_|state.Ack~q ), .cin(gnd), .combout(\ula_|i2c_loader_|scl_out~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|scl_out~0 .lut_mask = 16'h0003; +defparam \ula_|i2c_loader_|scl_out~0 .lut_mask = 16'h0011; defparam \ula_|i2c_loader_|scl_out~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X1_Y23_N13 +// Location: FF_X1_Y23_N7 dffeas \ula_|i2c_loader_|scl_out~_Duplicate_1 ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|scl_out~2_combout ), @@ -54958,7 +54725,7 @@ defparam \ula_|i2c_loader_|scl_out~_Duplicate_1 .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|scl_out~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N16 +// Location: LCCOMB_X1_Y23_N8 cycloneive_lcell_comb \ula_|i2c_loader_|scl_out~1 ( // Equation(s): // \ula_|i2c_loader_|scl_out~1_combout = (\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|state.Start~q $ (((!\ula_|i2c_loader_|scl_out~_Duplicate_1_q ))))) # (!\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|phase [1]) # @@ -54976,20 +54743,20 @@ defparam \ula_|i2c_loader_|scl_out~1 .lut_mask = 16'hBA74; defparam \ula_|i2c_loader_|scl_out~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N12 +// Location: LCCOMB_X1_Y23_N6 cycloneive_lcell_comb \ula_|i2c_loader_|scl_out~2 ( // Equation(s): // \ula_|i2c_loader_|scl_out~2_combout = (\ula_|i2c_loader_|scl_out~1_combout & ((\ula_|i2c_loader_|state.Start~q ))) # (!\ula_|i2c_loader_|scl_out~1_combout & (!\ula_|i2c_loader_|scl_out~0_combout & !\ula_|i2c_loader_|state.Start~q )) .dataa(\ula_|i2c_loader_|scl_out~0_combout ), .datab(\ula_|i2c_loader_|scl_out~1_combout ), - .datac(gnd), - .datad(\ula_|i2c_loader_|state.Start~q ), + .datac(\ula_|i2c_loader_|state.Start~q ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2c_loader_|scl_out~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|scl_out~2 .lut_mask = 16'hCC11; +defparam \ula_|i2c_loader_|scl_out~2 .lut_mask = 16'hC1C1; defparam \ula_|i2c_loader_|scl_out~2 .sum_lutc_input = "datac"; // synopsys translate_on @@ -55012,7 +54779,7 @@ defparam \ula_|i2c_loader_|scl_out .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|scl_out .power_up = "high"; // synopsys translate_on -// Location: FF_X1_Y23_N23 +// Location: FF_X1_Y23_N13 dffeas \ula_|i2c_loader_|sda_out~_Duplicate_1 ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|sda_out~4_combout ), @@ -55031,32 +54798,32 @@ defparam \ula_|i2c_loader_|sda_out~_Duplicate_1 .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|sda_out~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N10 +// Location: LCCOMB_X4_Y23_N10 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~4 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~4_combout = (!\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|state.Start~q ) +// \ula_|i2c_loader_|shiftreg~4_combout = (!\ula_|i2c_loader_|state.Start~q & !\ula_|i2c_loader_|state.Data~q ) - .dataa(gnd), + .dataa(\ula_|i2c_loader_|state.Start~q ), .datab(gnd), .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|state.Start~q ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg~4_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~4 .lut_mask = 16'h000F; +defparam \ula_|i2c_loader_|shiftreg~4 .lut_mask = 16'h0505; defparam \ula_|i2c_loader_|shiftreg~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N0 +// Location: LCCOMB_X4_Y23_N20 cycloneive_lcell_comb \ula_|i2c_loader_|Mux35~0 ( // Equation(s): -// \ula_|i2c_loader_|Mux35~0_combout = (\ula_|i2c_loader_|thisbyte [0] & (\ula_|i2c_loader_|thisbyte [2] & ((!\ula_|i2c_loader_|thisbyte [1]) # (!\ula_|i2c_loader_|thisbyte [3])))) +// \ula_|i2c_loader_|Mux35~0_combout = (\ula_|i2c_loader_|thisbyte [2] & (\ula_|i2c_loader_|thisbyte [0] & ((!\ula_|i2c_loader_|thisbyte [1]) # (!\ula_|i2c_loader_|thisbyte [3])))) - .dataa(\ula_|i2c_loader_|thisbyte [0]), + .dataa(\ula_|i2c_loader_|thisbyte [2]), .datab(\ula_|i2c_loader_|thisbyte [3]), .datac(\ula_|i2c_loader_|thisbyte [1]), - .datad(\ula_|i2c_loader_|thisbyte [2]), + .datad(\ula_|i2c_loader_|thisbyte [0]), .cin(gnd), .combout(\ula_|i2c_loader_|Mux35~0_combout ), .cout()); @@ -55065,135 +54832,186 @@ defparam \ula_|i2c_loader_|Mux35~0 .lut_mask = 16'h2A00; defparam \ula_|i2c_loader_|Mux35~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N30 +// Location: LCCOMB_X5_Y23_N12 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~13 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~13_combout = (!\ula_|i2c_loader_|thisbyte [2] & ((\ula_|i2c_loader_|thisbyte [4] & ((!\ula_|i2c_loader_|thisbyte [0]))) # (!\ula_|i2c_loader_|thisbyte [4] & (!\ula_|i2c_loader_|thisbyte [1] & \ula_|i2c_loader_|thisbyte [0])))) +// \ula_|i2c_loader_|shiftreg~13_combout = (!\ula_|i2c_loader_|thisbyte [2] & \ula_|i2c_loader_|thisbyte [4]) - .dataa(\ula_|i2c_loader_|thisbyte [4]), - .datab(\ula_|i2c_loader_|thisbyte [1]), - .datac(\ula_|i2c_loader_|thisbyte [0]), - .datad(\ula_|i2c_loader_|thisbyte [2]), + .dataa(\ula_|i2c_loader_|thisbyte [2]), + .datab(gnd), + .datac(\ula_|i2c_loader_|thisbyte [4]), + .datad(gnd), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg~13_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~13 .lut_mask = 16'h001A; +defparam \ula_|i2c_loader_|shiftreg~13 .lut_mask = 16'h5050; defparam \ula_|i2c_loader_|shiftreg~13 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N24 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~14 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~14_combout = (\ula_|i2c_loader_|thisbyte [4] & !\ula_|i2c_loader_|thisbyte [2]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2c_loader_|thisbyte [4]), - .datad(\ula_|i2c_loader_|thisbyte [2]), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~14_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~14 .lut_mask = 16'h00F0; -defparam \ula_|i2c_loader_|shiftreg~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N10 +// Location: LCCOMB_X5_Y23_N4 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~15 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~15_combout = (\ula_|i2c_loader_|shiftreg~13_combout ) # ((!\ula_|i2c_loader_|thisbyte [3] & (\ula_|i2c_loader_|thisbyte [0] & !\ula_|i2c_loader_|shiftreg~14_combout ))) +// \ula_|i2c_loader_|shiftreg~15_combout = (\ula_|i2c_loader_|thisbyte [2] & (((!\ula_|i2c_loader_|thisbyte [3])))) # (!\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte [1] & (\ula_|i2c_loader_|thisbyte [4]))) - .dataa(\ula_|i2c_loader_|shiftreg~13_combout ), - .datab(\ula_|i2c_loader_|thisbyte [3]), - .datac(\ula_|i2c_loader_|thisbyte [0]), - .datad(\ula_|i2c_loader_|shiftreg~14_combout ), + .dataa(\ula_|i2c_loader_|thisbyte [2]), + .datab(\ula_|i2c_loader_|thisbyte [1]), + .datac(\ula_|i2c_loader_|thisbyte [4]), + .datad(\ula_|i2c_loader_|thisbyte [3]), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg~15_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~15 .lut_mask = 16'hAABA; +defparam \ula_|i2c_loader_|shiftreg~15 .lut_mask = 16'h10BA; defparam \ula_|i2c_loader_|shiftreg~15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N12 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~24 ( +// Location: LCCOMB_X5_Y23_N10 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~16 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg[0]~24_combout = (!\ula_|i2c_loader_|thisbyte [3] & (!\ula_|i2c_loader_|state.Data~q & \ula_|i2c_loader_|thisbyte [0])) +// \ula_|i2c_loader_|shiftreg~16_combout = (\ula_|i2c_loader_|thisbyte [0] & (((\ula_|i2c_loader_|shiftreg~15_combout )))) # (!\ula_|i2c_loader_|thisbyte [0] & (!\ula_|i2c_loader_|shiftreg~13_combout & (\ula_|i2c_loader_|thisbyte [3]))) + + .dataa(\ula_|i2c_loader_|shiftreg~13_combout ), + .datab(\ula_|i2c_loader_|thisbyte [3]), + .datac(\ula_|i2c_loader_|shiftreg~15_combout ), + .datad(\ula_|i2c_loader_|thisbyte [0]), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~16_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~16 .lut_mask = 16'hF044; +defparam \ula_|i2c_loader_|shiftreg~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y23_N12 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~17 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~17_combout = (\ula_|i2c_loader_|thisbyte [0] & ((\ula_|i2c_loader_|thisbyte [4] & (!\ula_|i2c_loader_|thisbyte [1])) # (!\ula_|i2c_loader_|thisbyte [4] & ((!\ula_|i2c_loader_|thisbyte [3]))))) + + .dataa(\ula_|i2c_loader_|thisbyte [4]), + .datab(\ula_|i2c_loader_|thisbyte [0]), + .datac(\ula_|i2c_loader_|thisbyte [1]), + .datad(\ula_|i2c_loader_|thisbyte [3]), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~17_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~17 .lut_mask = 16'h084C; +defparam \ula_|i2c_loader_|shiftreg~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y23_N22 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~18 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~18_combout = ((\ula_|i2c_loader_|thisbyte [2] & ((!\ula_|i2c_loader_|thisbyte [0]))) # (!\ula_|i2c_loader_|thisbyte [2] & (\ula_|i2c_loader_|shiftreg~17_combout ))) # (!\ula_|i2c_loader_|shiftreg~4_combout ) + + .dataa(\ula_|i2c_loader_|shiftreg~17_combout ), + .datab(\ula_|i2c_loader_|thisbyte [2]), + .datac(\ula_|i2c_loader_|shiftreg~4_combout ), + .datad(\ula_|i2c_loader_|thisbyte [0]), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~18_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~18 .lut_mask = 16'h2FEF; +defparam \ula_|i2c_loader_|shiftreg~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y23_N14 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~20 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~20_combout = (\ula_|i2c_loader_|thisbyte [0] & ((\ula_|i2c_loader_|thisbyte [3] & (\ula_|i2c_loader_|thisbyte [2])) # (!\ula_|i2c_loader_|thisbyte [3] & (!\ula_|i2c_loader_|thisbyte [2] & !\ula_|i2c_loader_|thisbyte [4])))) + + .dataa(\ula_|i2c_loader_|thisbyte [0]), + .datab(\ula_|i2c_loader_|thisbyte [3]), + .datac(\ula_|i2c_loader_|thisbyte [2]), + .datad(\ula_|i2c_loader_|thisbyte [4]), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~20_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~20 .lut_mask = 16'h8082; +defparam \ula_|i2c_loader_|shiftreg~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y23_N24 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~21 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~21_combout = (\ula_|i2c_loader_|shiftreg~4_combout & ((\ula_|i2c_loader_|shiftreg~20_combout ) # ((\ula_|i2c_loader_|thisbyte [1] & !\ula_|i2c_loader_|thisbyte [0])))) + + .dataa(\ula_|i2c_loader_|shiftreg~4_combout ), + .datab(\ula_|i2c_loader_|shiftreg~20_combout ), + .datac(\ula_|i2c_loader_|thisbyte [1]), + .datad(\ula_|i2c_loader_|thisbyte [0]), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~21_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~21 .lut_mask = 16'h88A8; +defparam \ula_|i2c_loader_|shiftreg~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y23_N0 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~23 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg[0]~23_combout = (!\ula_|i2c_loader_|thisbyte [3] & (!\ula_|i2c_loader_|state.Data~q & \ula_|i2c_loader_|thisbyte [0])) .dataa(gnd), .datab(\ula_|i2c_loader_|thisbyte [3]), .datac(\ula_|i2c_loader_|state.Data~q ), .datad(\ula_|i2c_loader_|thisbyte [0]), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg[0]~24_combout ), + .combout(\ula_|i2c_loader_|shiftreg[0]~23_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[0]~24 .lut_mask = 16'h0300; -defparam \ula_|i2c_loader_|shiftreg[0]~24 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg[0]~23 .lut_mask = 16'h0300; +defparam \ula_|i2c_loader_|shiftreg[0]~23 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N14 +// Location: LCCOMB_X3_Y23_N30 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~6 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg[0]~6_combout = (!\ula_|i2c_loader_|phase [1] & (\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|state.Data~q )) +// \ula_|i2c_loader_|shiftreg[0]~6_combout = (\ula_|i2c_loader_|phase [1] & ((\ula_|i2c_loader_|state~24_combout ) # ((\ula_|i2c_loader_|state.Start~q )))) # (!\ula_|i2c_loader_|phase [1] & (((\ula_|i2c_loader_|state.Data~q )))) - .dataa(\ula_|i2c_loader_|phase [1]), - .datab(gnd), - .datac(\ula_|i2c_loader_|phase [0]), - .datad(\ula_|i2c_loader_|state.Data~q ), + .dataa(\ula_|i2c_loader_|state~24_combout ), + .datab(\ula_|i2c_loader_|state.Data~q ), + .datac(\ula_|i2c_loader_|state.Start~q ), + .datad(\ula_|i2c_loader_|phase [1]), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg[0]~6_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[0]~6 .lut_mask = 16'h5000; +defparam \ula_|i2c_loader_|shiftreg[0]~6 .lut_mask = 16'hFACC; defparam \ula_|i2c_loader_|shiftreg[0]~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N0 +// Location: LCCOMB_X3_Y23_N8 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~7 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg[0]~7_combout = (\ula_|i2c_loader_|shiftreg[0]~6_combout ) # ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Start~q ) # (\ula_|i2c_loader_|state~24_combout )))) +// \ula_|i2c_loader_|shiftreg[0]~7_combout = (\ula_|i2c_loader_|shiftreg[0]~6_combout & (\ula_|i2c_loader_|phase [0] & (!\ula_|i2c_loader_|WideAnd0~combout & \ula_|i2c_loader_|state.Idle~q ))) - .dataa(\ula_|i2c_loader_|state.Start~q ), - .datab(\ula_|i2c_loader_|Mux42~0_combout ), - .datac(\ula_|i2c_loader_|shiftreg[0]~6_combout ), - .datad(\ula_|i2c_loader_|state~24_combout ), + .dataa(\ula_|i2c_loader_|shiftreg[0]~6_combout ), + .datab(\ula_|i2c_loader_|phase [0]), + .datac(\ula_|i2c_loader_|WideAnd0~combout ), + .datad(\ula_|i2c_loader_|state.Idle~q ), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg[0]~7_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[0]~7 .lut_mask = 16'hFCF8; +defparam \ula_|i2c_loader_|shiftreg[0]~7 .lut_mask = 16'h0800; defparam \ula_|i2c_loader_|shiftreg[0]~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N10 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~8 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg[0]~8_combout = (\ula_|i2c_loader_|state.Idle~q & (!\ula_|i2c_loader_|WideAnd0~combout & \ula_|i2c_loader_|shiftreg[0]~7_combout )) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|state.Idle~q ), - .datac(\ula_|i2c_loader_|WideAnd0~combout ), - .datad(\ula_|i2c_loader_|shiftreg[0]~7_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg[0]~8_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[0]~8 .lut_mask = 16'h0C00; -defparam \ula_|i2c_loader_|shiftreg[0]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X3_Y23_N13 +// Location: FF_X4_Y23_N1 dffeas \ula_|i2c_loader_|shiftreg[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|shiftreg[0]~24_combout ), + .d(\ula_|i2c_loader_|shiftreg[0]~23_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(\ula_|i2c_loader_|state.Start~q ), .sload(gnd), - .ena(\ula_|i2c_loader_|shiftreg[0]~8_combout ), + .ena(\ula_|i2c_loader_|shiftreg[0]~7_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [0]), @@ -55203,102 +55021,68 @@ defparam \ula_|i2c_loader_|shiftreg[0] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N26 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~21 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~21_combout = (\ula_|i2c_loader_|thisbyte [0] & ((\ula_|i2c_loader_|thisbyte [3] & ((\ula_|i2c_loader_|thisbyte [2]))) # (!\ula_|i2c_loader_|thisbyte [3] & (!\ula_|i2c_loader_|thisbyte [4] & !\ula_|i2c_loader_|thisbyte [2])))) - - .dataa(\ula_|i2c_loader_|thisbyte [4]), - .datab(\ula_|i2c_loader_|thisbyte [3]), - .datac(\ula_|i2c_loader_|thisbyte [0]), - .datad(\ula_|i2c_loader_|thisbyte [2]), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~21_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~21 .lut_mask = 16'hC010; -defparam \ula_|i2c_loader_|shiftreg~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y23_N28 +// Location: LCCOMB_X4_Y23_N28 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~22 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~22_combout = (\ula_|i2c_loader_|shiftreg~4_combout & ((\ula_|i2c_loader_|shiftreg~21_combout ) # ((\ula_|i2c_loader_|thisbyte [1] & !\ula_|i2c_loader_|thisbyte [0])))) +// \ula_|i2c_loader_|shiftreg~22_combout = (\ula_|i2c_loader_|shiftreg~21_combout ) # ((\ula_|i2c_loader_|state.Data~q & \ula_|i2c_loader_|shiftreg [0])) - .dataa(\ula_|i2c_loader_|shiftreg~21_combout ), - .datab(\ula_|i2c_loader_|shiftreg~4_combout ), - .datac(\ula_|i2c_loader_|thisbyte [1]), - .datad(\ula_|i2c_loader_|thisbyte [0]), + .dataa(gnd), + .datab(\ula_|i2c_loader_|shiftreg~21_combout ), + .datac(\ula_|i2c_loader_|state.Data~q ), + .datad(\ula_|i2c_loader_|shiftreg [0]), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg~22_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~22 .lut_mask = 16'h88C8; +defparam \ula_|i2c_loader_|shiftreg~22 .lut_mask = 16'hFCCC; defparam \ula_|i2c_loader_|shiftreg~22 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N22 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~23 ( +// Location: LCCOMB_X3_Y23_N10 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[6]~9 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~23_combout = (\ula_|i2c_loader_|shiftreg~22_combout ) # ((\ula_|i2c_loader_|shiftreg [0] & \ula_|i2c_loader_|state.Data~q )) +// \ula_|i2c_loader_|shiftreg[6]~9_combout = (\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|state.Start~q $ (!\ula_|i2c_loader_|phase [1])))) # (!\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|phase [1] & ((\ula_|i2c_loader_|state~24_combout +// ) # (\ula_|i2c_loader_|state.Start~q )))) - .dataa(\ula_|i2c_loader_|shiftreg [0]), - .datab(gnd), - .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|shiftreg~22_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~23_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~23 .lut_mask = 16'hFFA0; -defparam \ula_|i2c_loader_|shiftreg~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N10 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[6]~10 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg[6]~10_combout = (\ula_|i2c_loader_|phase [1] & ((\ula_|i2c_loader_|state.Start~q ) # ((!\ula_|i2c_loader_|state.Data~q & \ula_|i2c_loader_|state~24_combout )))) # (!\ula_|i2c_loader_|phase [1] & (\ula_|i2c_loader_|state.Data~q -// & (!\ula_|i2c_loader_|state.Start~q ))) - - .dataa(\ula_|i2c_loader_|phase [1]), + .dataa(\ula_|i2c_loader_|state~24_combout ), .datab(\ula_|i2c_loader_|state.Data~q ), .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|state~24_combout ), + .datad(\ula_|i2c_loader_|phase [1]), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg[6]~9_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg[6]~9 .lut_mask = 16'hF20C; +defparam \ula_|i2c_loader_|shiftreg[6]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y23_N12 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[6]~10 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg[6]~10_combout = (\ula_|i2c_loader_|shiftreg[6]~9_combout & (\ula_|i2c_loader_|phase [0] & (!\ula_|i2c_loader_|WideAnd0~combout & \ula_|i2c_loader_|state.Idle~q ))) + + .dataa(\ula_|i2c_loader_|shiftreg[6]~9_combout ), + .datab(\ula_|i2c_loader_|phase [0]), + .datac(\ula_|i2c_loader_|WideAnd0~combout ), + .datad(\ula_|i2c_loader_|state.Idle~q ), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg[6]~10_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[6]~10 .lut_mask = 16'hA6A4; +defparam \ula_|i2c_loader_|shiftreg[6]~10 .lut_mask = 16'h0800; defparam \ula_|i2c_loader_|shiftreg[6]~10 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N24 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[6]~11 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg[6]~11_combout = (\ula_|i2c_loader_|phase [0] & (!\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|state.Idle~q & \ula_|i2c_loader_|shiftreg[6]~10_combout ))) - - .dataa(\ula_|i2c_loader_|phase [0]), - .datab(\ula_|i2c_loader_|WideAnd0~combout ), - .datac(\ula_|i2c_loader_|state.Idle~q ), - .datad(\ula_|i2c_loader_|shiftreg[6]~10_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg[6]~11_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[6]~11 .lut_mask = 16'h2000; -defparam \ula_|i2c_loader_|shiftreg[6]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X3_Y23_N23 +// Location: FF_X4_Y23_N29 dffeas \ula_|i2c_loader_|shiftreg[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|shiftreg~23_combout ), + .d(\ula_|i2c_loader_|shiftreg~22_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2c_loader_|shiftreg[6]~11_combout ), + .ena(\ula_|i2c_loader_|shiftreg[6]~10_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [1]), @@ -55308,67 +55092,33 @@ defparam \ula_|i2c_loader_|shiftreg[1] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N4 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~18 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~18_combout = (\ula_|i2c_loader_|thisbyte [0] & ((\ula_|i2c_loader_|thisbyte [4] & ((!\ula_|i2c_loader_|thisbyte [1]))) # (!\ula_|i2c_loader_|thisbyte [4] & (!\ula_|i2c_loader_|thisbyte [3])))) - - .dataa(\ula_|i2c_loader_|thisbyte [4]), - .datab(\ula_|i2c_loader_|thisbyte [3]), - .datac(\ula_|i2c_loader_|thisbyte [0]), - .datad(\ula_|i2c_loader_|thisbyte [1]), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~18_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~18 .lut_mask = 16'h10B0; -defparam \ula_|i2c_loader_|shiftreg~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y23_N24 +// Location: LCCOMB_X4_Y23_N2 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~19 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~19_combout = ((\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte [0])) # (!\ula_|i2c_loader_|thisbyte [2] & ((\ula_|i2c_loader_|shiftreg~18_combout )))) # (!\ula_|i2c_loader_|shiftreg~4_combout ) +// \ula_|i2c_loader_|shiftreg~19_combout = (\ula_|i2c_loader_|shiftreg~18_combout & ((\ula_|i2c_loader_|shiftreg [1]) # (!\ula_|i2c_loader_|state.Data~q ))) - .dataa(\ula_|i2c_loader_|thisbyte [0]), - .datab(\ula_|i2c_loader_|thisbyte [2]), - .datac(\ula_|i2c_loader_|shiftreg~18_combout ), - .datad(\ula_|i2c_loader_|shiftreg~4_combout ), + .dataa(\ula_|i2c_loader_|shiftreg~18_combout ), + .datab(\ula_|i2c_loader_|shiftreg [1]), + .datac(\ula_|i2c_loader_|state.Data~q ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg~19_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~19 .lut_mask = 16'h74FF; +defparam \ula_|i2c_loader_|shiftreg~19 .lut_mask = 16'h8A8A; defparam \ula_|i2c_loader_|shiftreg~19 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N2 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~20 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~20_combout = (\ula_|i2c_loader_|shiftreg~19_combout & ((\ula_|i2c_loader_|shiftreg [1]) # (!\ula_|i2c_loader_|state.Data~q ))) - - .dataa(\ula_|i2c_loader_|shiftreg [1]), - .datab(gnd), - .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|shiftreg~19_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~20_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~20 .lut_mask = 16'hAF00; -defparam \ula_|i2c_loader_|shiftreg~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X3_Y23_N3 +// Location: FF_X4_Y23_N3 dffeas \ula_|i2c_loader_|shiftreg[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|shiftreg~20_combout ), + .d(\ula_|i2c_loader_|shiftreg~19_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2c_loader_|shiftreg[6]~11_combout ), + .ena(\ula_|i2c_loader_|shiftreg[6]~10_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [2]), @@ -55378,67 +55128,33 @@ defparam \ula_|i2c_loader_|shiftreg[2] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N28 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~16 ( +// Location: LCCOMB_X4_Y23_N8 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~25 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~16_combout = (\ula_|i2c_loader_|thisbyte [2] & (((!\ula_|i2c_loader_|thisbyte [3])))) # (!\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte [1] & (\ula_|i2c_loader_|thisbyte [4]))) - - .dataa(\ula_|i2c_loader_|thisbyte [2]), - .datab(\ula_|i2c_loader_|thisbyte [1]), - .datac(\ula_|i2c_loader_|thisbyte [4]), - .datad(\ula_|i2c_loader_|thisbyte [3]), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~16_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~16 .lut_mask = 16'h10BA; -defparam \ula_|i2c_loader_|shiftreg~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y23_N20 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~17 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~17_combout = (\ula_|i2c_loader_|thisbyte [0] & (((\ula_|i2c_loader_|shiftreg~16_combout )))) # (!\ula_|i2c_loader_|thisbyte [0] & (\ula_|i2c_loader_|thisbyte [3] & ((!\ula_|i2c_loader_|shiftreg~14_combout )))) - - .dataa(\ula_|i2c_loader_|thisbyte [0]), - .datab(\ula_|i2c_loader_|thisbyte [3]), - .datac(\ula_|i2c_loader_|shiftreg~16_combout ), - .datad(\ula_|i2c_loader_|shiftreg~14_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~17_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~17 .lut_mask = 16'hA0E4; -defparam \ula_|i2c_loader_|shiftreg~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y23_N6 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~26 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~26_combout = (\ula_|i2c_loader_|state.Data~q & (((\ula_|i2c_loader_|shiftreg [2])))) # (!\ula_|i2c_loader_|state.Data~q & (!\ula_|i2c_loader_|state.Start~q & ((\ula_|i2c_loader_|shiftreg~17_combout )))) +// \ula_|i2c_loader_|shiftreg~25_combout = (\ula_|i2c_loader_|state.Data~q & (((\ula_|i2c_loader_|shiftreg [2])))) # (!\ula_|i2c_loader_|state.Data~q & (!\ula_|i2c_loader_|state.Start~q & (\ula_|i2c_loader_|shiftreg~16_combout ))) .dataa(\ula_|i2c_loader_|state.Start~q ), - .datab(\ula_|i2c_loader_|shiftreg [2]), - .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|shiftreg~17_combout ), + .datab(\ula_|i2c_loader_|state.Data~q ), + .datac(\ula_|i2c_loader_|shiftreg~16_combout ), + .datad(\ula_|i2c_loader_|shiftreg [2]), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~26_combout ), + .combout(\ula_|i2c_loader_|shiftreg~25_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~26 .lut_mask = 16'hC5C0; -defparam \ula_|i2c_loader_|shiftreg~26 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg~25 .lut_mask = 16'hDC10; +defparam \ula_|i2c_loader_|shiftreg~25 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y23_N7 +// Location: FF_X4_Y23_N9 dffeas \ula_|i2c_loader_|shiftreg[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|shiftreg~26_combout ), + .d(\ula_|i2c_loader_|shiftreg~25_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2c_loader_|shiftreg[6]~11_combout ), + .ena(\ula_|i2c_loader_|shiftreg[6]~10_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [3]), @@ -55448,33 +55164,67 @@ defparam \ula_|i2c_loader_|shiftreg[3] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N0 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~25 ( +// Location: LCCOMB_X5_Y23_N14 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~12 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~25_combout = (\ula_|i2c_loader_|state.Data~q & (((\ula_|i2c_loader_|shiftreg [3])))) # (!\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|shiftreg~15_combout ) # ((\ula_|i2c_loader_|state.Start~q )))) +// \ula_|i2c_loader_|shiftreg~12_combout = (!\ula_|i2c_loader_|thisbyte [2] & ((\ula_|i2c_loader_|thisbyte [4] & ((!\ula_|i2c_loader_|thisbyte [0]))) # (!\ula_|i2c_loader_|thisbyte [4] & (!\ula_|i2c_loader_|thisbyte [1] & \ula_|i2c_loader_|thisbyte [0])))) - .dataa(\ula_|i2c_loader_|shiftreg~15_combout ), - .datab(\ula_|i2c_loader_|state.Data~q ), - .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|shiftreg [3]), + .dataa(\ula_|i2c_loader_|thisbyte [2]), + .datab(\ula_|i2c_loader_|thisbyte [1]), + .datac(\ula_|i2c_loader_|thisbyte [4]), + .datad(\ula_|i2c_loader_|thisbyte [0]), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~25_combout ), + .combout(\ula_|i2c_loader_|shiftreg~12_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~25 .lut_mask = 16'hFE32; -defparam \ula_|i2c_loader_|shiftreg~25 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg~12 .lut_mask = 16'h0150; +defparam \ula_|i2c_loader_|shiftreg~12 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X2_Y23_N1 +// Location: LCCOMB_X5_Y23_N6 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~14 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~14_combout = (\ula_|i2c_loader_|shiftreg~12_combout ) # ((!\ula_|i2c_loader_|shiftreg~13_combout & (!\ula_|i2c_loader_|thisbyte [3] & \ula_|i2c_loader_|thisbyte [0]))) + + .dataa(\ula_|i2c_loader_|shiftreg~13_combout ), + .datab(\ula_|i2c_loader_|thisbyte [3]), + .datac(\ula_|i2c_loader_|shiftreg~12_combout ), + .datad(\ula_|i2c_loader_|thisbyte [0]), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~14_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~14 .lut_mask = 16'hF1F0; +defparam \ula_|i2c_loader_|shiftreg~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y23_N6 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~24 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~24_combout = (\ula_|i2c_loader_|state.Data~q & (((\ula_|i2c_loader_|shiftreg [3])))) # (!\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|state.Start~q ) # ((\ula_|i2c_loader_|shiftreg~14_combout )))) + + .dataa(\ula_|i2c_loader_|state.Start~q ), + .datab(\ula_|i2c_loader_|shiftreg [3]), + .datac(\ula_|i2c_loader_|state.Data~q ), + .datad(\ula_|i2c_loader_|shiftreg~14_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~24_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~24 .lut_mask = 16'hCFCA; +defparam \ula_|i2c_loader_|shiftreg~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X4_Y23_N7 dffeas \ula_|i2c_loader_|shiftreg[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|shiftreg~25_combout ), + .d(\ula_|i2c_loader_|shiftreg~24_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2c_loader_|shiftreg[6]~11_combout ), + .ena(\ula_|i2c_loader_|shiftreg[6]~10_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [4]), @@ -55484,33 +55234,33 @@ defparam \ula_|i2c_loader_|shiftreg[4] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N4 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~12 ( +// Location: LCCOMB_X3_Y23_N24 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~11 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~12_combout = (\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|shiftreg [4]))) # (!\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|Mux35~0_combout )) +// \ula_|i2c_loader_|shiftreg~11_combout = (\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|shiftreg [4]))) # (!\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|Mux35~0_combout )) .dataa(\ula_|i2c_loader_|Mux35~0_combout ), .datab(\ula_|i2c_loader_|state.Data~q ), .datac(gnd), .datad(\ula_|i2c_loader_|shiftreg [4]), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~12_combout ), + .combout(\ula_|i2c_loader_|shiftreg~11_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~12 .lut_mask = 16'hEE22; -defparam \ula_|i2c_loader_|shiftreg~12 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg~11 .lut_mask = 16'hEE22; +defparam \ula_|i2c_loader_|shiftreg~11 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X2_Y24_N5 +// Location: FF_X3_Y23_N25 dffeas \ula_|i2c_loader_|shiftreg[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|shiftreg~12_combout ), + .d(\ula_|i2c_loader_|shiftreg~11_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(\ula_|i2c_loader_|state.Start~q ), - .ena(\ula_|i2c_loader_|shiftreg[6]~11_combout ), + .ena(\ula_|i2c_loader_|shiftreg[6]~10_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [5]), @@ -55520,33 +55270,33 @@ defparam \ula_|i2c_loader_|shiftreg[5] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N18 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~9 ( +// Location: LCCOMB_X4_Y23_N18 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~8 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~9_combout = (\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|shiftreg [5])) # (!\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|Mux35~0_combout ))) +// \ula_|i2c_loader_|shiftreg~8_combout = (\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|shiftreg [5])) # (!\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|Mux35~0_combout ))) .dataa(gnd), .datab(\ula_|i2c_loader_|shiftreg [5]), .datac(\ula_|i2c_loader_|state.Data~q ), .datad(\ula_|i2c_loader_|Mux35~0_combout ), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~9_combout ), + .combout(\ula_|i2c_loader_|shiftreg~8_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~9 .lut_mask = 16'hCFC0; -defparam \ula_|i2c_loader_|shiftreg~9 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg~8 .lut_mask = 16'hCFC0; +defparam \ula_|i2c_loader_|shiftreg~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y23_N19 +// Location: FF_X4_Y23_N19 dffeas \ula_|i2c_loader_|shiftreg[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|shiftreg~9_combout ), + .d(\ula_|i2c_loader_|shiftreg~8_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(\ula_|i2c_loader_|state.Start~q ), .sload(gnd), - .ena(\ula_|i2c_loader_|shiftreg[6]~11_combout ), + .ena(\ula_|i2c_loader_|shiftreg[6]~10_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [6]), @@ -55556,7 +55306,7 @@ defparam \ula_|i2c_loader_|shiftreg[6] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N4 +// Location: LCCOMB_X4_Y23_N16 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[7]~5 ( // Equation(s): // \ula_|i2c_loader_|shiftreg[7]~5_combout = (\ula_|i2c_loader_|state.Data~q & \ula_|i2c_loader_|shiftreg [6]) @@ -55573,7 +55323,7 @@ defparam \ula_|i2c_loader_|shiftreg[7]~5 .lut_mask = 16'hF000; defparam \ula_|i2c_loader_|shiftreg[7]~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y23_N5 +// Location: FF_X4_Y23_N17 dffeas \ula_|i2c_loader_|shiftreg[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|shiftreg[7]~5_combout ), @@ -55582,7 +55332,7 @@ dffeas \ula_|i2c_loader_|shiftreg[7] ( .aload(gnd), .sclr(\ula_|i2c_loader_|state.Start~q ), .sload(gnd), - .ena(\ula_|i2c_loader_|shiftreg[0]~8_combout ), + .ena(\ula_|i2c_loader_|shiftreg[0]~7_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [7]), @@ -55592,25 +55342,25 @@ defparam \ula_|i2c_loader_|shiftreg[7] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N12 +// Location: LCCOMB_X1_Y23_N26 cycloneive_lcell_comb \ula_|i2c_loader_|sda_out~0 ( // Equation(s): -// \ula_|i2c_loader_|sda_out~0_combout = (\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|shiftreg [7]))) # (!\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|state.Ack~q )))) # (!\ula_|i2c_loader_|state.Data~q & +// \ula_|i2c_loader_|sda_out~0_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|shiftreg [7])) # (!\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|state.Ack~q ))))) # (!\ula_|i2c_loader_|phase [0] & // (((\ula_|i2c_loader_|state.Ack~q )))) - .dataa(\ula_|i2c_loader_|state.Data~q ), - .datab(\ula_|i2c_loader_|phase [0]), - .datac(\ula_|i2c_loader_|state.Ack~q ), - .datad(\ula_|i2c_loader_|shiftreg [7]), + .dataa(\ula_|i2c_loader_|shiftreg [7]), + .datab(\ula_|i2c_loader_|state.Ack~q ), + .datac(\ula_|i2c_loader_|phase [0]), + .datad(\ula_|i2c_loader_|state.Data~q ), .cin(gnd), .combout(\ula_|i2c_loader_|sda_out~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|sda_out~0 .lut_mask = 16'hF870; +defparam \ula_|i2c_loader_|sda_out~0 .lut_mask = 16'hACCC; defparam \ula_|i2c_loader_|sda_out~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N6 +// Location: LCCOMB_X1_Y23_N20 cycloneive_lcell_comb \ula_|i2c_loader_|sda_out~1 ( // Equation(s): // \ula_|i2c_loader_|sda_out~1_combout = (\ula_|i2c_loader_|sda_out~0_combout & ((\ula_|i2c_loader_|phase [0]) # ((\ula_|i2c_loader_|shiftreg~4_combout & !\I2C_SDAT~input_o )))) @@ -55627,55 +55377,55 @@ defparam \ula_|i2c_loader_|sda_out~1 .lut_mask = 16'hC0E0; defparam \ula_|i2c_loader_|sda_out~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N8 +// Location: LCCOMB_X1_Y23_N14 cycloneive_lcell_comb \ula_|i2c_loader_|sda_out~2 ( // Equation(s): // \ula_|i2c_loader_|sda_out~2_combout = (!\ula_|i2c_loader_|sda_out~_Duplicate_1_q & ((\ula_|i2c_loader_|phase [0]) # ((\ula_|i2c_loader_|phase [1] & !\ula_|i2c_loader_|sda_out~1_combout )))) .dataa(\ula_|i2c_loader_|sda_out~_Duplicate_1_q ), - .datab(\ula_|i2c_loader_|phase [0]), - .datac(\ula_|i2c_loader_|phase [1]), + .datab(\ula_|i2c_loader_|phase [1]), + .datac(\ula_|i2c_loader_|phase [0]), .datad(\ula_|i2c_loader_|sda_out~1_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|sda_out~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|sda_out~2 .lut_mask = 16'h4454; +defparam \ula_|i2c_loader_|sda_out~2 .lut_mask = 16'h5054; defparam \ula_|i2c_loader_|sda_out~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N2 +// Location: LCCOMB_X1_Y23_N28 cycloneive_lcell_comb \ula_|i2c_loader_|sda_out~3 ( // Equation(s): -// \ula_|i2c_loader_|sda_out~3_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|phase [1] & (\ula_|i2c_loader_|sda_out~_Duplicate_1_q )) # (!\ula_|i2c_loader_|phase [1] & ((!\ula_|i2c_loader_|sda_out~1_combout ))))) # (!\ula_|i2c_loader_|phase -// [0] & ((\ula_|i2c_loader_|sda_out~_Duplicate_1_q ) # ((\ula_|i2c_loader_|phase [1] & \ula_|i2c_loader_|sda_out~1_combout )))) +// \ula_|i2c_loader_|sda_out~3_combout = (\ula_|i2c_loader_|phase [1] & ((\ula_|i2c_loader_|sda_out~_Duplicate_1_q ) # ((!\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|sda_out~1_combout )))) # (!\ula_|i2c_loader_|phase [1] & ((\ula_|i2c_loader_|phase [0] +// & ((!\ula_|i2c_loader_|sda_out~1_combout ))) # (!\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|sda_out~_Duplicate_1_q )))) .dataa(\ula_|i2c_loader_|sda_out~_Duplicate_1_q ), - .datab(\ula_|i2c_loader_|phase [0]), - .datac(\ula_|i2c_loader_|phase [1]), + .datab(\ula_|i2c_loader_|phase [1]), + .datac(\ula_|i2c_loader_|phase [0]), .datad(\ula_|i2c_loader_|sda_out~1_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|sda_out~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|sda_out~3 .lut_mask = 16'hB2AE; +defparam \ula_|i2c_loader_|sda_out~3 .lut_mask = 16'h8EBA; defparam \ula_|i2c_loader_|sda_out~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N22 +// Location: LCCOMB_X1_Y23_N12 cycloneive_lcell_comb \ula_|i2c_loader_|sda_out~4 ( // Equation(s): // \ula_|i2c_loader_|sda_out~4_combout = (\ula_|i2c_loader_|state.Start~q & (((!\ula_|i2c_loader_|sda_out~2_combout )))) # (!\ula_|i2c_loader_|state.Start~q & (!\ula_|i2c_loader_|scl_out~0_combout & ((\ula_|i2c_loader_|sda_out~3_combout )))) - .dataa(\ula_|i2c_loader_|state.Start~q ), - .datab(\ula_|i2c_loader_|scl_out~0_combout ), + .dataa(\ula_|i2c_loader_|scl_out~0_combout ), + .datab(\ula_|i2c_loader_|state.Start~q ), .datac(\ula_|i2c_loader_|sda_out~2_combout ), .datad(\ula_|i2c_loader_|sda_out~3_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|sda_out~4_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|sda_out~4 .lut_mask = 16'h1B0A; +defparam \ula_|i2c_loader_|sda_out~4 .lut_mask = 16'h1D0C; defparam \ula_|i2c_loader_|sda_out~4 .sum_lutc_input = "datac"; // synopsys translate_on @@ -55698,7 +55448,7 @@ defparam \ula_|i2c_loader_|sda_out .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|sda_out .power_up = "high"; // synopsys translate_on -// Location: LCCOMB_X27_Y23_N16 +// Location: LCCOMB_X25_Y32_N20 cycloneive_lcell_comb \ula_|i2s_intf_|mclk_r~0 ( // Equation(s): // \ula_|i2s_intf_|mclk_r~0_combout = !\ula_|i2s_intf_|mclk_r~_Duplicate_1_q @@ -55715,7 +55465,7 @@ defparam \ula_|i2s_intf_|mclk_r~0 .lut_mask = 16'h0F0F; defparam \ula_|i2s_intf_|mclk_r~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X27_Y23_N17 +// Location: FF_X25_Y32_N21 dffeas \ula_|i2s_intf_|mclk_r~_Duplicate_1 ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|mclk_r~0_combout ), @@ -55753,7 +55503,7 @@ defparam \ula_|i2s_intf_|mclk_r .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|mclk_r .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N6 +// Location: LCCOMB_X24_Y32_N8 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~1 ( // Equation(s): // \ula_|i2s_intf_|Add0~1_cout = CARRY(!\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ) @@ -55770,25 +55520,25 @@ defparam \ula_|i2s_intf_|Add0~1 .lut_mask = 16'h0055; defparam \ula_|i2s_intf_|Add0~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N8 +// Location: LCCOMB_X24_Y32_N10 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~2 ( // Equation(s): // \ula_|i2s_intf_|Add0~2_combout = (\ula_|i2s_intf_|lrdivider [1] & (\ula_|i2s_intf_|Add0~1_cout & VCC)) # (!\ula_|i2s_intf_|lrdivider [1] & (!\ula_|i2s_intf_|Add0~1_cout )) // \ula_|i2s_intf_|Add0~3 = CARRY((!\ula_|i2s_intf_|lrdivider [1] & !\ula_|i2s_intf_|Add0~1_cout )) - .dataa(gnd), - .datab(\ula_|i2s_intf_|lrdivider [1]), + .dataa(\ula_|i2s_intf_|lrdivider [1]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\ula_|i2s_intf_|Add0~1_cout ), .combout(\ula_|i2s_intf_|Add0~2_combout ), .cout(\ula_|i2s_intf_|Add0~3 )); // synopsys translate_off -defparam \ula_|i2s_intf_|Add0~2 .lut_mask = 16'hC303; +defparam \ula_|i2s_intf_|Add0~2 .lut_mask = 16'hA505; defparam \ula_|i2s_intf_|Add0~2 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N28 +// Location: LCCOMB_X23_Y32_N10 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider~2 ( // Equation(s): // \ula_|i2s_intf_|lrdivider~2_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|Add0~2_combout ) @@ -55805,7 +55555,7 @@ defparam \ula_|i2s_intf_|lrdivider~2 .lut_mask = 16'h5050; defparam \ula_|i2s_intf_|lrdivider~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X29_Y23_N29 +// Location: FF_X23_Y32_N11 dffeas \ula_|i2s_intf_|lrdivider[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider~2_combout ), @@ -55824,42 +55574,42 @@ defparam \ula_|i2s_intf_|lrdivider[1] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N10 +// Location: LCCOMB_X24_Y32_N12 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~4 ( // Equation(s): // \ula_|i2s_intf_|Add0~4_combout = (\ula_|i2s_intf_|lrdivider [2] & (\ula_|i2s_intf_|Add0~3 $ (GND))) # (!\ula_|i2s_intf_|lrdivider [2] & ((GND) # (!\ula_|i2s_intf_|Add0~3 ))) // \ula_|i2s_intf_|Add0~5 = CARRY((!\ula_|i2s_intf_|Add0~3 ) # (!\ula_|i2s_intf_|lrdivider [2])) - .dataa(\ula_|i2s_intf_|lrdivider [2]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|i2s_intf_|lrdivider [2]), .datac(gnd), .datad(vcc), .cin(\ula_|i2s_intf_|Add0~3 ), .combout(\ula_|i2s_intf_|Add0~4_combout ), .cout(\ula_|i2s_intf_|Add0~5 )); // synopsys translate_off -defparam \ula_|i2s_intf_|Add0~4 .lut_mask = 16'hA55F; +defparam \ula_|i2s_intf_|Add0~4 .lut_mask = 16'hC33F; defparam \ula_|i2s_intf_|Add0~4 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X30_Y23_N6 +// Location: LCCOMB_X23_Y32_N22 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[2]~8 ( // Equation(s): // \ula_|i2s_intf_|lrdivider[2]~8_combout = !\ula_|i2s_intf_|Add0~4_combout .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|Add0~4_combout ), + .datac(\ula_|i2s_intf_|Add0~4_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|lrdivider[2]~8_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[2]~8 .lut_mask = 16'h00FF; +defparam \ula_|i2s_intf_|lrdivider[2]~8 .lut_mask = 16'h0F0F; defparam \ula_|i2s_intf_|lrdivider[2]~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y23_N7 +// Location: FF_X23_Y32_N23 dffeas \ula_|i2s_intf_|lrdivider[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider[2]~8_combout ), @@ -55878,7 +55628,7 @@ defparam \ula_|i2s_intf_|lrdivider[2] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N12 +// Location: LCCOMB_X24_Y32_N14 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~6 ( // Equation(s): // \ula_|i2s_intf_|Add0~6_combout = (\ula_|i2s_intf_|lrdivider [3] & (!\ula_|i2s_intf_|Add0~5 )) # (!\ula_|i2s_intf_|lrdivider [3] & (\ula_|i2s_intf_|Add0~5 & VCC)) @@ -55896,24 +55646,24 @@ defparam \ula_|i2s_intf_|Add0~6 .lut_mask = 16'h3C0C; defparam \ula_|i2s_intf_|Add0~6 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X28_Y23_N6 +// Location: LCCOMB_X23_Y32_N4 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[3]~7 ( // Equation(s): // \ula_|i2s_intf_|lrdivider[3]~7_combout = !\ula_|i2s_intf_|Add0~6_combout .dataa(gnd), .datab(gnd), - .datac(\ula_|i2s_intf_|Add0~6_combout ), - .datad(gnd), + .datac(gnd), + .datad(\ula_|i2s_intf_|Add0~6_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|lrdivider[3]~7_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[3]~7 .lut_mask = 16'h0F0F; +defparam \ula_|i2s_intf_|lrdivider[3]~7 .lut_mask = 16'h00FF; defparam \ula_|i2s_intf_|lrdivider[3]~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y23_N7 +// Location: FF_X23_Y32_N5 dffeas \ula_|i2s_intf_|lrdivider[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider[3]~7_combout ), @@ -55932,42 +55682,42 @@ defparam \ula_|i2s_intf_|lrdivider[3] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N14 +// Location: LCCOMB_X24_Y32_N16 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~8 ( // Equation(s): // \ula_|i2s_intf_|Add0~8_combout = (\ula_|i2s_intf_|lrdivider [4] & ((GND) # (!\ula_|i2s_intf_|Add0~7 ))) # (!\ula_|i2s_intf_|lrdivider [4] & (\ula_|i2s_intf_|Add0~7 $ (GND))) // \ula_|i2s_intf_|Add0~9 = CARRY((\ula_|i2s_intf_|lrdivider [4]) # (!\ula_|i2s_intf_|Add0~7 )) - .dataa(gnd), - .datab(\ula_|i2s_intf_|lrdivider [4]), + .dataa(\ula_|i2s_intf_|lrdivider [4]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\ula_|i2s_intf_|Add0~7 ), .combout(\ula_|i2s_intf_|Add0~8_combout ), .cout(\ula_|i2s_intf_|Add0~9 )); // synopsys translate_off -defparam \ula_|i2s_intf_|Add0~8 .lut_mask = 16'h3CCF; +defparam \ula_|i2s_intf_|Add0~8 .lut_mask = 16'h5AAF; defparam \ula_|i2s_intf_|Add0~8 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N4 +// Location: LCCOMB_X23_Y32_N16 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider~1 ( // Equation(s): // \ula_|i2s_intf_|lrdivider~1_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|Add0~8_combout ) - .dataa(\ula_|i2s_intf_|Equal0~2_combout ), + .dataa(gnd), .datab(gnd), - .datac(\ula_|i2s_intf_|Add0~8_combout ), - .datad(gnd), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|Add0~8_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|lrdivider~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider~1 .lut_mask = 16'h5050; +defparam \ula_|i2s_intf_|lrdivider~1 .lut_mask = 16'h0F00; defparam \ula_|i2s_intf_|lrdivider~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X29_Y23_N5 +// Location: FF_X23_Y32_N17 dffeas \ula_|i2s_intf_|lrdivider[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider~1_combout ), @@ -55986,25 +55736,25 @@ defparam \ula_|i2s_intf_|lrdivider[4] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N16 +// Location: LCCOMB_X24_Y32_N18 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~10 ( // Equation(s): // \ula_|i2s_intf_|Add0~10_combout = (\ula_|i2s_intf_|lrdivider [5] & (!\ula_|i2s_intf_|Add0~9 )) # (!\ula_|i2s_intf_|lrdivider [5] & (\ula_|i2s_intf_|Add0~9 & VCC)) // \ula_|i2s_intf_|Add0~11 = CARRY((\ula_|i2s_intf_|lrdivider [5] & !\ula_|i2s_intf_|Add0~9 )) - .dataa(gnd), - .datab(\ula_|i2s_intf_|lrdivider [5]), + .dataa(\ula_|i2s_intf_|lrdivider [5]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\ula_|i2s_intf_|Add0~9 ), .combout(\ula_|i2s_intf_|Add0~10_combout ), .cout(\ula_|i2s_intf_|Add0~11 )); // synopsys translate_off -defparam \ula_|i2s_intf_|Add0~10 .lut_mask = 16'h3C0C; +defparam \ula_|i2s_intf_|Add0~10 .lut_mask = 16'h5A0A; defparam \ula_|i2s_intf_|Add0~10 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N2 +// Location: LCCOMB_X23_Y32_N14 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[5]~6 ( // Equation(s): // \ula_|i2s_intf_|lrdivider[5]~6_combout = !\ula_|i2s_intf_|Add0~10_combout @@ -56021,7 +55771,7 @@ defparam \ula_|i2s_intf_|lrdivider[5]~6 .lut_mask = 16'h00FF; defparam \ula_|i2s_intf_|lrdivider[5]~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X29_Y23_N3 +// Location: FF_X23_Y32_N15 dffeas \ula_|i2s_intf_|lrdivider[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider[5]~6_combout ), @@ -56040,24 +55790,24 @@ defparam \ula_|i2s_intf_|lrdivider[5] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N26 +// Location: LCCOMB_X24_Y32_N0 cycloneive_lcell_comb \ula_|i2s_intf_|Equal0~1 ( // Equation(s): -// \ula_|i2s_intf_|Equal0~1_combout = (\ula_|i2s_intf_|lrdivider [2] & (!\ula_|i2s_intf_|lrdivider [4] & (\ula_|i2s_intf_|lrdivider [3] & \ula_|i2s_intf_|lrdivider [5]))) +// \ula_|i2s_intf_|Equal0~1_combout = (!\ula_|i2s_intf_|lrdivider [4] & (\ula_|i2s_intf_|lrdivider [2] & (\ula_|i2s_intf_|lrdivider [3] & \ula_|i2s_intf_|lrdivider [5]))) - .dataa(\ula_|i2s_intf_|lrdivider [2]), - .datab(\ula_|i2s_intf_|lrdivider [4]), + .dataa(\ula_|i2s_intf_|lrdivider [4]), + .datab(\ula_|i2s_intf_|lrdivider [2]), .datac(\ula_|i2s_intf_|lrdivider [3]), .datad(\ula_|i2s_intf_|lrdivider [5]), .cin(gnd), .combout(\ula_|i2s_intf_|Equal0~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|Equal0~1 .lut_mask = 16'h2000; +defparam \ula_|i2s_intf_|Equal0~1 .lut_mask = 16'h4000; defparam \ula_|i2s_intf_|Equal0~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N18 +// Location: LCCOMB_X24_Y32_N20 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~12 ( // Equation(s): // \ula_|i2s_intf_|Add0~12_combout = (\ula_|i2s_intf_|lrdivider [6] & (\ula_|i2s_intf_|Add0~11 $ (GND))) # (!\ula_|i2s_intf_|lrdivider [6] & ((GND) # (!\ula_|i2s_intf_|Add0~11 ))) @@ -56075,24 +55825,24 @@ defparam \ula_|i2s_intf_|Add0~12 .lut_mask = 16'hA55F; defparam \ula_|i2s_intf_|Add0~12 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X28_Y23_N26 +// Location: LCCOMB_X23_Y32_N0 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[6]~5 ( // Equation(s): // \ula_|i2s_intf_|lrdivider[6]~5_combout = !\ula_|i2s_intf_|Add0~12_combout .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|Add0~12_combout ), + .datac(\ula_|i2s_intf_|Add0~12_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|lrdivider[6]~5_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[6]~5 .lut_mask = 16'h00FF; +defparam \ula_|i2s_intf_|lrdivider[6]~5 .lut_mask = 16'h0F0F; defparam \ula_|i2s_intf_|lrdivider[6]~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y23_N27 +// Location: FF_X23_Y32_N1 dffeas \ula_|i2s_intf_|lrdivider[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider[6]~5_combout ), @@ -56111,42 +55861,42 @@ defparam \ula_|i2s_intf_|lrdivider[6] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N20 +// Location: LCCOMB_X24_Y32_N22 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~14 ( // Equation(s): // \ula_|i2s_intf_|Add0~14_combout = (\ula_|i2s_intf_|lrdivider [7] & (!\ula_|i2s_intf_|Add0~13 )) # (!\ula_|i2s_intf_|lrdivider [7] & (\ula_|i2s_intf_|Add0~13 & VCC)) // \ula_|i2s_intf_|Add0~15 = CARRY((\ula_|i2s_intf_|lrdivider [7] & !\ula_|i2s_intf_|Add0~13 )) - .dataa(\ula_|i2s_intf_|lrdivider [7]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|i2s_intf_|lrdivider [7]), .datac(gnd), .datad(vcc), .cin(\ula_|i2s_intf_|Add0~13 ), .combout(\ula_|i2s_intf_|Add0~14_combout ), .cout(\ula_|i2s_intf_|Add0~15 )); // synopsys translate_off -defparam \ula_|i2s_intf_|Add0~14 .lut_mask = 16'h5A0A; +defparam \ula_|i2s_intf_|Add0~14 .lut_mask = 16'h3C0C; defparam \ula_|i2s_intf_|Add0~14 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X30_Y23_N4 +// Location: LCCOMB_X24_Y32_N2 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[7]~4 ( // Equation(s): // \ula_|i2s_intf_|lrdivider[7]~4_combout = !\ula_|i2s_intf_|Add0~14_combout .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|Add0~14_combout ), + .datac(\ula_|i2s_intf_|Add0~14_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|lrdivider[7]~4_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[7]~4 .lut_mask = 16'h00FF; +defparam \ula_|i2s_intf_|lrdivider[7]~4 .lut_mask = 16'h0F0F; defparam \ula_|i2s_intf_|lrdivider[7]~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y23_N5 +// Location: FF_X24_Y32_N3 dffeas \ula_|i2s_intf_|lrdivider[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider[7]~4_combout ), @@ -56165,25 +55915,25 @@ defparam \ula_|i2s_intf_|lrdivider[7] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N22 +// Location: LCCOMB_X24_Y32_N24 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~16 ( // Equation(s): // \ula_|i2s_intf_|Add0~16_combout = (\ula_|i2s_intf_|lrdivider [8] & ((GND) # (!\ula_|i2s_intf_|Add0~15 ))) # (!\ula_|i2s_intf_|lrdivider [8] & (\ula_|i2s_intf_|Add0~15 $ (GND))) // \ula_|i2s_intf_|Add0~17 = CARRY((\ula_|i2s_intf_|lrdivider [8]) # (!\ula_|i2s_intf_|Add0~15 )) - .dataa(\ula_|i2s_intf_|lrdivider [8]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|i2s_intf_|lrdivider [8]), .datac(gnd), .datad(vcc), .cin(\ula_|i2s_intf_|Add0~15 ), .combout(\ula_|i2s_intf_|Add0~16_combout ), .cout(\ula_|i2s_intf_|Add0~17 )); // synopsys translate_off -defparam \ula_|i2s_intf_|Add0~16 .lut_mask = 16'h5AAF; +defparam \ula_|i2s_intf_|Add0~16 .lut_mask = 16'h3CCF; defparam \ula_|i2s_intf_|Add0~16 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X28_Y23_N16 +// Location: LCCOMB_X24_Y32_N28 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider~0 ( // Equation(s): // \ula_|i2s_intf_|lrdivider~0_combout = (\ula_|i2s_intf_|Add0~16_combout & !\ula_|i2s_intf_|Equal0~2_combout ) @@ -56200,7 +55950,7 @@ defparam \ula_|i2s_intf_|lrdivider~0 .lut_mask = 16'h0C0C; defparam \ula_|i2s_intf_|lrdivider~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y23_N17 +// Location: FF_X24_Y32_N29 dffeas \ula_|i2s_intf_|lrdivider[8] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider~0_combout ), @@ -56219,41 +55969,41 @@ defparam \ula_|i2s_intf_|lrdivider[8] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[8] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N24 +// Location: LCCOMB_X24_Y32_N26 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~18 ( // Equation(s): -// \ula_|i2s_intf_|Add0~18_combout = \ula_|i2s_intf_|Add0~17 $ (\ula_|i2s_intf_|lrdivider [9]) +// \ula_|i2s_intf_|Add0~18_combout = \ula_|i2s_intf_|lrdivider [9] $ (\ula_|i2s_intf_|Add0~17 ) .dataa(gnd), - .datab(gnd), + .datab(\ula_|i2s_intf_|lrdivider [9]), .datac(gnd), - .datad(\ula_|i2s_intf_|lrdivider [9]), + .datad(gnd), .cin(\ula_|i2s_intf_|Add0~17 ), .combout(\ula_|i2s_intf_|Add0~18_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|Add0~18 .lut_mask = 16'h0FF0; +defparam \ula_|i2s_intf_|Add0~18 .lut_mask = 16'h3C3C; defparam \ula_|i2s_intf_|Add0~18 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X28_Y23_N24 +// Location: LCCOMB_X24_Y32_N4 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[9]~3 ( // Equation(s): // \ula_|i2s_intf_|lrdivider[9]~3_combout = !\ula_|i2s_intf_|Add0~18_combout .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|Add0~18_combout ), + .datac(\ula_|i2s_intf_|Add0~18_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|lrdivider[9]~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[9]~3 .lut_mask = 16'h00FF; +defparam \ula_|i2s_intf_|lrdivider[9]~3 .lut_mask = 16'h0F0F; defparam \ula_|i2s_intf_|lrdivider[9]~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y23_N25 +// Location: FF_X24_Y32_N5 dffeas \ula_|i2s_intf_|lrdivider[9] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider[9]~3_combout ), @@ -56272,61 +56022,44 @@ defparam \ula_|i2s_intf_|lrdivider[9] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[9] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N0 +// Location: LCCOMB_X24_Y32_N6 cycloneive_lcell_comb \ula_|i2s_intf_|Equal0~0 ( // Equation(s): -// \ula_|i2s_intf_|Equal0~0_combout = (!\ula_|i2s_intf_|lrdivider [8] & (\ula_|i2s_intf_|lrdivider [9] & (\ula_|i2s_intf_|lrdivider [6] & \ula_|i2s_intf_|lrdivider [7]))) +// \ula_|i2s_intf_|Equal0~0_combout = (\ula_|i2s_intf_|lrdivider [6] & (!\ula_|i2s_intf_|lrdivider [8] & (\ula_|i2s_intf_|lrdivider [9] & \ula_|i2s_intf_|lrdivider [7]))) - .dataa(\ula_|i2s_intf_|lrdivider [8]), - .datab(\ula_|i2s_intf_|lrdivider [9]), - .datac(\ula_|i2s_intf_|lrdivider [6]), + .dataa(\ula_|i2s_intf_|lrdivider [6]), + .datab(\ula_|i2s_intf_|lrdivider [8]), + .datac(\ula_|i2s_intf_|lrdivider [9]), .datad(\ula_|i2s_intf_|lrdivider [7]), .cin(gnd), .combout(\ula_|i2s_intf_|Equal0~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|Equal0~0 .lut_mask = 16'h4000; +defparam \ula_|i2s_intf_|Equal0~0 .lut_mask = 16'h2000; defparam \ula_|i2s_intf_|Equal0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N30 +// Location: LCCOMB_X24_Y32_N30 cycloneive_lcell_comb \ula_|i2s_intf_|Equal0~2 ( // Equation(s): -// \ula_|i2s_intf_|Equal0~2_combout = (\ula_|i2s_intf_|Equal0~1_combout & (!\ula_|i2s_intf_|lrdivider [1] & (\ula_|i2s_intf_|mclk_r~_Duplicate_1_q & \ula_|i2s_intf_|Equal0~0_combout ))) +// \ula_|i2s_intf_|Equal0~2_combout = (!\ula_|i2s_intf_|lrdivider [1] & (\ula_|i2s_intf_|Equal0~1_combout & (\ula_|i2s_intf_|mclk_r~_Duplicate_1_q & \ula_|i2s_intf_|Equal0~0_combout ))) - .dataa(\ula_|i2s_intf_|Equal0~1_combout ), - .datab(\ula_|i2s_intf_|lrdivider [1]), + .dataa(\ula_|i2s_intf_|lrdivider [1]), + .datab(\ula_|i2s_intf_|Equal0~1_combout ), .datac(\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ), .datad(\ula_|i2s_intf_|Equal0~0_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|Equal0~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|Equal0~2 .lut_mask = 16'h2000; +defparam \ula_|i2s_intf_|Equal0~2 .lut_mask = 16'h4000; defparam \ula_|i2s_intf_|Equal0~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y22_N24 -cycloneive_lcell_comb \ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder ( -// Equation(s): -// \ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder_combout = \ula_|i2s_intf_|lrclk_r~0_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|lrclk_r~0_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder .lut_mask = 16'hFF00; -defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y22_N25 +// Location: FF_X23_Y31_N5 dffeas \ula_|i2s_intf_|lrclk_r~_Duplicate_2 ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder_combout ), + .d(\ula_|i2s_intf_|lrclk_r~0_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -56342,20 +56075,20 @@ defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_2 .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_2 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y22_N0 +// Location: LCCOMB_X23_Y31_N4 cycloneive_lcell_comb \ula_|i2s_intf_|lrclk_r~0 ( // Equation(s): // \ula_|i2s_intf_|lrclk_r~0_combout = \ula_|i2s_intf_|Equal0~2_combout $ (\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ) .dataa(gnd), .datab(\ula_|i2s_intf_|Equal0~2_combout ), - .datac(gnd), - .datad(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), + .datac(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|lrclk_r~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrclk_r~0 .lut_mask = 16'h33CC; +defparam \ula_|i2s_intf_|lrclk_r~0 .lut_mask = 16'h3C3C; defparam \ula_|i2s_intf_|lrclk_r~0 .sum_lutc_input = "datac"; // synopsys translate_on @@ -56397,7 +56130,7 @@ defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_1 .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y22_N0 +// Location: LCCOMB_X25_Y31_N0 cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[0]~5 ( // Equation(s): // \ula_|i2s_intf_|bitcount[0]~5_combout = !\ula_|i2s_intf_|bitcount [0] @@ -56415,10 +56148,27 @@ defparam \ula_|i2s_intf_|bitcount[0]~5 .lut_mask = 16'h3333; defparam \ula_|i2s_intf_|bitcount[0]~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y22_N11 +// Location: LCCOMB_X25_Y31_N26 +cycloneive_lcell_comb \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder ( +// Equation(s): +// \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder_combout = \ula_|i2s_intf_|bclk_r~1_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|i2s_intf_|bclk_r~1_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|bclk_r~_Duplicate_1feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder .lut_mask = 16'hFF00; +defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y31_N27 dffeas \ula_|i2s_intf_|bclk_r~_Duplicate_1 ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|bclk_r~1_combout ), + .d(\ula_|i2s_intf_|bclk_r~_Duplicate_1feeder_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -56434,24 +56184,24 @@ defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1 .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y22_N28 +// Location: LCCOMB_X25_Y31_N22 cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[4]~15 ( // Equation(s): -// \ula_|i2s_intf_|bitcount[4]~15_combout = (\ula_|i2s_intf_|Equal0~2_combout ) # ((\ula_|i2s_intf_|shiftreg[4]~1_combout & !\ula_|i2s_intf_|bclk_r~_Duplicate_1_q )) +// \ula_|i2s_intf_|bitcount[4]~15_combout = (\ula_|i2s_intf_|Equal0~2_combout ) # ((!\ula_|i2s_intf_|bclk_r~_Duplicate_1_q & \ula_|i2s_intf_|shiftreg[4]~1_combout )) - .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg[4]~1_combout ), + .dataa(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .datab(gnd), .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .datad(\ula_|i2s_intf_|shiftreg[4]~1_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|bitcount[4]~15_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[4]~15 .lut_mask = 16'hF0FC; +defparam \ula_|i2s_intf_|bitcount[4]~15 .lut_mask = 16'hF5F0; defparam \ula_|i2s_intf_|bitcount[4]~15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y22_N1 +// Location: FF_X25_Y31_N1 dffeas \ula_|i2s_intf_|bitcount[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|bitcount[0]~5_combout ), @@ -56470,25 +56220,25 @@ defparam \ula_|i2s_intf_|bitcount[0] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|bitcount[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y22_N2 +// Location: LCCOMB_X25_Y31_N2 cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[1]~7 ( // Equation(s): // \ula_|i2s_intf_|bitcount[1]~7_combout = (\ula_|i2s_intf_|bitcount [1] & (\ula_|i2s_intf_|bitcount[0]~6 & VCC)) # (!\ula_|i2s_intf_|bitcount [1] & (!\ula_|i2s_intf_|bitcount[0]~6 )) // \ula_|i2s_intf_|bitcount[1]~8 = CARRY((!\ula_|i2s_intf_|bitcount [1] & !\ula_|i2s_intf_|bitcount[0]~6 )) - .dataa(gnd), - .datab(\ula_|i2s_intf_|bitcount [1]), + .dataa(\ula_|i2s_intf_|bitcount [1]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\ula_|i2s_intf_|bitcount[0]~6 ), .combout(\ula_|i2s_intf_|bitcount[1]~7_combout ), .cout(\ula_|i2s_intf_|bitcount[1]~8 )); // synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[1]~7 .lut_mask = 16'hC303; +defparam \ula_|i2s_intf_|bitcount[1]~7 .lut_mask = 16'hA505; defparam \ula_|i2s_intf_|bitcount[1]~7 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y22_N3 +// Location: FF_X25_Y31_N3 dffeas \ula_|i2s_intf_|bitcount[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|bitcount[1]~7_combout ), @@ -56507,7 +56257,7 @@ defparam \ula_|i2s_intf_|bitcount[1] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|bitcount[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y22_N4 +// Location: LCCOMB_X25_Y31_N4 cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[2]~9 ( // Equation(s): // \ula_|i2s_intf_|bitcount[2]~9_combout = (\ula_|i2s_intf_|bitcount [2] & ((GND) # (!\ula_|i2s_intf_|bitcount[1]~8 ))) # (!\ula_|i2s_intf_|bitcount [2] & (\ula_|i2s_intf_|bitcount[1]~8 $ (GND))) @@ -56525,7 +56275,7 @@ defparam \ula_|i2s_intf_|bitcount[2]~9 .lut_mask = 16'h3CCF; defparam \ula_|i2s_intf_|bitcount[2]~9 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y22_N5 +// Location: FF_X25_Y31_N5 dffeas \ula_|i2s_intf_|bitcount[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|bitcount[2]~9_combout ), @@ -56544,7 +56294,7 @@ defparam \ula_|i2s_intf_|bitcount[2] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|bitcount[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y22_N6 +// Location: LCCOMB_X25_Y31_N6 cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[3]~11 ( // Equation(s): // \ula_|i2s_intf_|bitcount[3]~11_combout = (\ula_|i2s_intf_|bitcount [3] & (\ula_|i2s_intf_|bitcount[2]~10 & VCC)) # (!\ula_|i2s_intf_|bitcount [3] & (!\ula_|i2s_intf_|bitcount[2]~10 )) @@ -56562,7 +56312,7 @@ defparam \ula_|i2s_intf_|bitcount[3]~11 .lut_mask = 16'hA505; defparam \ula_|i2s_intf_|bitcount[3]~11 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y22_N7 +// Location: FF_X25_Y31_N7 dffeas \ula_|i2s_intf_|bitcount[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|bitcount[3]~11_combout ), @@ -56581,24 +56331,7 @@ defparam \ula_|i2s_intf_|bitcount[3] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|bitcount[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y22_N24 -cycloneive_lcell_comb \ula_|i2s_intf_|LessThan0~0 ( -// Equation(s): -// \ula_|i2s_intf_|LessThan0~0_combout = (\ula_|i2s_intf_|bitcount [3]) # (((\ula_|i2s_intf_|bitcount [2]) # (\ula_|i2s_intf_|bitcount [1])) # (!\ula_|i2s_intf_|bitcount [0])) - - .dataa(\ula_|i2s_intf_|bitcount [3]), - .datab(\ula_|i2s_intf_|bitcount [0]), - .datac(\ula_|i2s_intf_|bitcount [2]), - .datad(\ula_|i2s_intf_|bitcount [1]), - .cin(gnd), - .combout(\ula_|i2s_intf_|LessThan0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|LessThan0~0 .lut_mask = 16'hFFFB; -defparam \ula_|i2s_intf_|LessThan0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y22_N8 +// Location: LCCOMB_X25_Y31_N8 cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[4]~13 ( // Equation(s): // \ula_|i2s_intf_|bitcount[4]~13_combout = \ula_|i2s_intf_|bitcount [4] $ (\ula_|i2s_intf_|bitcount[3]~12 ) @@ -56615,7 +56348,7 @@ defparam \ula_|i2s_intf_|bitcount[4]~13 .lut_mask = 16'h3C3C; defparam \ula_|i2s_intf_|bitcount[4]~13 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y22_N9 +// Location: FF_X25_Y31_N9 dffeas \ula_|i2s_intf_|bitcount[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|bitcount[4]~13_combout ), @@ -56634,273 +56367,41 @@ defparam \ula_|i2s_intf_|bitcount[4] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|bitcount[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y22_N14 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~7 ( +// Location: LCCOMB_X25_Y31_N20 +cycloneive_lcell_comb \ula_|i2s_intf_|LessThan0~0 ( // Equation(s): -// \ula_|i2s_intf_|Add2~7_cout = CARRY(!\ula_|i2s_intf_|bdivider [0]) +// \ula_|i2s_intf_|LessThan0~0_combout = (\ula_|i2s_intf_|bitcount [1]) # (((\ula_|i2s_intf_|bitcount [2]) # (\ula_|i2s_intf_|bitcount [3])) # (!\ula_|i2s_intf_|bitcount [0])) - .dataa(\ula_|i2s_intf_|bdivider [0]), - .datab(gnd), - .datac(gnd), - .datad(vcc), + .dataa(\ula_|i2s_intf_|bitcount [1]), + .datab(\ula_|i2s_intf_|bitcount [0]), + .datac(\ula_|i2s_intf_|bitcount [2]), + .datad(\ula_|i2s_intf_|bitcount [3]), .cin(gnd), - .combout(), - .cout(\ula_|i2s_intf_|Add2~7_cout )); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~7 .lut_mask = 16'h0055; -defparam \ula_|i2s_intf_|Add2~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y22_N16 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~8 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~8_combout = (\ula_|i2s_intf_|bdivider [1] & (\ula_|i2s_intf_|Add2~7_cout & VCC)) # (!\ula_|i2s_intf_|bdivider [1] & (!\ula_|i2s_intf_|Add2~7_cout )) -// \ula_|i2s_intf_|Add2~9 = CARRY((!\ula_|i2s_intf_|bdivider [1] & !\ula_|i2s_intf_|Add2~7_cout )) - - .dataa(\ula_|i2s_intf_|bdivider [1]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|Add2~7_cout ), - .combout(\ula_|i2s_intf_|Add2~8_combout ), - .cout(\ula_|i2s_intf_|Add2~9 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~8 .lut_mask = 16'hA505; -defparam \ula_|i2s_intf_|Add2~8 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y22_N12 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~20 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~20_combout = (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|Add2~8_combout & ((!\ula_|i2s_intf_|Equal1~0_combout ) # (!\ula_|i2s_intf_|bdivider [0])))) - - .dataa(\ula_|i2s_intf_|bdivider [0]), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), - .datac(\ula_|i2s_intf_|Equal1~0_combout ), - .datad(\ula_|i2s_intf_|Add2~8_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|Add2~20_combout ), + .combout(\ula_|i2s_intf_|LessThan0~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|Add2~20 .lut_mask = 16'h1300; -defparam \ula_|i2s_intf_|Add2~20 .sum_lutc_input = "datac"; +defparam \ula_|i2s_intf_|LessThan0~0 .lut_mask = 16'hFFFB; +defparam \ula_|i2s_intf_|LessThan0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y22_N13 -dffeas \ula_|i2s_intf_|bdivider[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|Add2~20_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bdivider [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bdivider[1] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bdivider[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y22_N18 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~10 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~10_combout = (\ula_|i2s_intf_|bdivider [2] & (\ula_|i2s_intf_|Add2~9 $ (GND))) # (!\ula_|i2s_intf_|bdivider [2] & ((GND) # (!\ula_|i2s_intf_|Add2~9 ))) -// \ula_|i2s_intf_|Add2~11 = CARRY((!\ula_|i2s_intf_|Add2~9 ) # (!\ula_|i2s_intf_|bdivider [2])) - - .dataa(\ula_|i2s_intf_|bdivider [2]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|Add2~9 ), - .combout(\ula_|i2s_intf_|Add2~10_combout ), - .cout(\ula_|i2s_intf_|Add2~11 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~10 .lut_mask = 16'hA55F; -defparam \ula_|i2s_intf_|Add2~10 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y22_N16 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~17 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~17_combout = (!\ula_|i2s_intf_|shiftreg[4]~1_combout & (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~1_combout ) # (!\ula_|i2s_intf_|Add2~10_combout )))) - - .dataa(\ula_|i2s_intf_|Equal1~1_combout ), - .datab(\ula_|i2s_intf_|shiftreg[4]~1_combout ), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|Add2~10_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|Add2~17_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~17 .lut_mask = 16'h0203; -defparam \ula_|i2s_intf_|Add2~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y22_N17 -dffeas \ula_|i2s_intf_|bdivider[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|Add2~17_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bdivider [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bdivider[2] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bdivider[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y22_N20 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~12 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~12_combout = (\ula_|i2s_intf_|bdivider [3] & (\ula_|i2s_intf_|Add2~11 & VCC)) # (!\ula_|i2s_intf_|bdivider [3] & (!\ula_|i2s_intf_|Add2~11 )) -// \ula_|i2s_intf_|Add2~13 = CARRY((!\ula_|i2s_intf_|bdivider [3] & !\ula_|i2s_intf_|Add2~11 )) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|bdivider [3]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|Add2~11 ), - .combout(\ula_|i2s_intf_|Add2~12_combout ), - .cout(\ula_|i2s_intf_|Add2~13 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~12 .lut_mask = 16'hC303; -defparam \ula_|i2s_intf_|Add2~12 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y22_N2 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~19 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~19_combout = (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|Add2~12_combout & ((!\ula_|i2s_intf_|Equal1~0_combout ) # (!\ula_|i2s_intf_|bdivider [0])))) - - .dataa(\ula_|i2s_intf_|bdivider [0]), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), - .datac(\ula_|i2s_intf_|Equal1~0_combout ), - .datad(\ula_|i2s_intf_|Add2~12_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|Add2~19_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~19 .lut_mask = 16'h1300; -defparam \ula_|i2s_intf_|Add2~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y22_N3 -dffeas \ula_|i2s_intf_|bdivider[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|Add2~19_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bdivider [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bdivider[3] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bdivider[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y22_N22 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~14 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~14_combout = \ula_|i2s_intf_|Add2~13 $ (!\ula_|i2s_intf_|bdivider [4]) - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|bdivider [4]), - .cin(\ula_|i2s_intf_|Add2~13 ), - .combout(\ula_|i2s_intf_|Add2~14_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~14 .lut_mask = 16'hF00F; -defparam \ula_|i2s_intf_|Add2~14 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y22_N18 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~16 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~16_combout = (!\ula_|i2s_intf_|shiftreg[4]~1_combout & (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~1_combout ) # (!\ula_|i2s_intf_|Add2~14_combout )))) - - .dataa(\ula_|i2s_intf_|Equal1~1_combout ), - .datab(\ula_|i2s_intf_|shiftreg[4]~1_combout ), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|Add2~14_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|Add2~16_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~16 .lut_mask = 16'h0203; -defparam \ula_|i2s_intf_|Add2~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y22_N19 -dffeas \ula_|i2s_intf_|bdivider[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|Add2~16_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bdivider [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bdivider[4] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bdivider[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y22_N26 -cycloneive_lcell_comb \ula_|i2s_intf_|Equal1~0 ( -// Equation(s): -// \ula_|i2s_intf_|Equal1~0_combout = (!\ula_|i2s_intf_|bdivider [1] & (!\ula_|i2s_intf_|bdivider [3] & (\ula_|i2s_intf_|bdivider [2] & \ula_|i2s_intf_|bdivider [4]))) - - .dataa(\ula_|i2s_intf_|bdivider [1]), - .datab(\ula_|i2s_intf_|bdivider [3]), - .datac(\ula_|i2s_intf_|bdivider [2]), - .datad(\ula_|i2s_intf_|bdivider [4]), - .cin(gnd), - .combout(\ula_|i2s_intf_|Equal1~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Equal1~0 .lut_mask = 16'h1000; -defparam \ula_|i2s_intf_|Equal1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y22_N20 +// Location: LCCOMB_X25_Y31_N10 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[4]~1 ( // Equation(s): // \ula_|i2s_intf_|shiftreg[4]~1_combout = (\ula_|i2s_intf_|bdivider [0] & (\ula_|i2s_intf_|Equal1~0_combout & ((\ula_|i2s_intf_|LessThan0~0_combout ) # (!\ula_|i2s_intf_|bitcount [4])))) .dataa(\ula_|i2s_intf_|bdivider [0]), - .datab(\ula_|i2s_intf_|LessThan0~0_combout ), + .datab(\ula_|i2s_intf_|Equal1~0_combout ), .datac(\ula_|i2s_intf_|bitcount [4]), - .datad(\ula_|i2s_intf_|Equal1~0_combout ), + .datad(\ula_|i2s_intf_|LessThan0~0_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg[4]~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[4]~1 .lut_mask = 16'h8A00; +defparam \ula_|i2s_intf_|shiftreg[4]~1 .lut_mask = 16'h8808; defparam \ula_|i2s_intf_|shiftreg[4]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y22_N12 +// Location: LCCOMB_X24_Y31_N12 cycloneive_lcell_comb \ula_|i2s_intf_|Add2~18 ( // Equation(s): // \ula_|i2s_intf_|Add2~18_combout = (!\ula_|i2s_intf_|Equal0~2_combout & (!\ula_|i2s_intf_|shiftreg[4]~1_combout & ((\ula_|i2s_intf_|Equal1~0_combout ) # (!\ula_|i2s_intf_|bdivider [0])))) @@ -56917,7 +56418,7 @@ defparam \ula_|i2s_intf_|Add2~18 .lut_mask = 16'h1101; defparam \ula_|i2s_intf_|Add2~18 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y22_N13 +// Location: FF_X24_Y31_N13 dffeas \ula_|i2s_intf_|bdivider[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|Add2~18_combout ), @@ -56936,54 +56437,303 @@ defparam \ula_|i2s_intf_|bdivider[0] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|bdivider[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y22_N22 -cycloneive_lcell_comb \ula_|i2s_intf_|Equal1~1 ( +// Location: LCCOMB_X24_Y31_N2 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~7 ( // Equation(s): -// \ula_|i2s_intf_|Equal1~1_combout = (\ula_|i2s_intf_|bdivider [0] & \ula_|i2s_intf_|Equal1~0_combout ) +// \ula_|i2s_intf_|Add2~7_cout = CARRY(!\ula_|i2s_intf_|bdivider [0]) + + .dataa(\ula_|i2s_intf_|bdivider [0]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(), + .cout(\ula_|i2s_intf_|Add2~7_cout )); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~7 .lut_mask = 16'h0055; +defparam \ula_|i2s_intf_|Add2~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y31_N4 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~8 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~8_combout = (\ula_|i2s_intf_|bdivider [1] & (\ula_|i2s_intf_|Add2~7_cout & VCC)) # (!\ula_|i2s_intf_|bdivider [1] & (!\ula_|i2s_intf_|Add2~7_cout )) +// \ula_|i2s_intf_|Add2~9 = CARRY((!\ula_|i2s_intf_|bdivider [1] & !\ula_|i2s_intf_|Add2~7_cout )) + + .dataa(\ula_|i2s_intf_|bdivider [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|Add2~7_cout ), + .combout(\ula_|i2s_intf_|Add2~8_combout ), + .cout(\ula_|i2s_intf_|Add2~9 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~8 .lut_mask = 16'hA505; +defparam \ula_|i2s_intf_|Add2~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y31_N22 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~20 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~20_combout = (\ula_|i2s_intf_|Add2~8_combout & (!\ula_|i2s_intf_|Equal0~2_combout & ((!\ula_|i2s_intf_|Equal1~0_combout ) # (!\ula_|i2s_intf_|bdivider [0])))) + + .dataa(\ula_|i2s_intf_|bdivider [0]), + .datab(\ula_|i2s_intf_|Add2~8_combout ), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|Equal1~0_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|Add2~20_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~20 .lut_mask = 16'h040C; +defparam \ula_|i2s_intf_|Add2~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y31_N23 +dffeas \ula_|i2s_intf_|bdivider[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|Add2~20_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bdivider [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bdivider[1] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bdivider[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y31_N6 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~10 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~10_combout = (\ula_|i2s_intf_|bdivider [2] & (\ula_|i2s_intf_|Add2~9 $ (GND))) # (!\ula_|i2s_intf_|bdivider [2] & ((GND) # (!\ula_|i2s_intf_|Add2~9 ))) +// \ula_|i2s_intf_|Add2~11 = CARRY((!\ula_|i2s_intf_|Add2~9 ) # (!\ula_|i2s_intf_|bdivider [2])) + + .dataa(\ula_|i2s_intf_|bdivider [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|Add2~9 ), + .combout(\ula_|i2s_intf_|Add2~10_combout ), + .cout(\ula_|i2s_intf_|Add2~11 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~10 .lut_mask = 16'hA55F; +defparam \ula_|i2s_intf_|Add2~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y31_N26 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~17 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~17_combout = (!\ula_|i2s_intf_|Equal0~2_combout & (!\ula_|i2s_intf_|shiftreg[4]~1_combout & ((\ula_|i2s_intf_|Equal1~1_combout ) # (!\ula_|i2s_intf_|Add2~10_combout )))) + + .dataa(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(\ula_|i2s_intf_|Equal1~1_combout ), + .datac(\ula_|i2s_intf_|shiftreg[4]~1_combout ), + .datad(\ula_|i2s_intf_|Add2~10_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|Add2~17_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~17 .lut_mask = 16'h0405; +defparam \ula_|i2s_intf_|Add2~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y31_N27 +dffeas \ula_|i2s_intf_|bdivider[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|Add2~17_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bdivider [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bdivider[2] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bdivider[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y31_N8 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~12 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~12_combout = (\ula_|i2s_intf_|bdivider [3] & (\ula_|i2s_intf_|Add2~11 & VCC)) # (!\ula_|i2s_intf_|bdivider [3] & (!\ula_|i2s_intf_|Add2~11 )) +// \ula_|i2s_intf_|Add2~13 = CARRY((!\ula_|i2s_intf_|bdivider [3] & !\ula_|i2s_intf_|Add2~11 )) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|bdivider [3]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|Add2~11 ), + .combout(\ula_|i2s_intf_|Add2~12_combout ), + .cout(\ula_|i2s_intf_|Add2~13 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~12 .lut_mask = 16'hC303; +defparam \ula_|i2s_intf_|Add2~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y31_N0 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~19 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~19_combout = (\ula_|i2s_intf_|Add2~12_combout & (!\ula_|i2s_intf_|Equal0~2_combout & ((!\ula_|i2s_intf_|Equal1~0_combout ) # (!\ula_|i2s_intf_|bdivider [0])))) + + .dataa(\ula_|i2s_intf_|bdivider [0]), + .datab(\ula_|i2s_intf_|Add2~12_combout ), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|Equal1~0_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|Add2~19_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~19 .lut_mask = 16'h040C; +defparam \ula_|i2s_intf_|Add2~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y31_N1 +dffeas \ula_|i2s_intf_|bdivider[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|Add2~19_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bdivider [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bdivider[3] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bdivider[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y31_N10 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~14 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~14_combout = \ula_|i2s_intf_|Add2~13 $ (!\ula_|i2s_intf_|bdivider [4]) .dataa(gnd), .datab(gnd), - .datac(\ula_|i2s_intf_|bdivider [0]), - .datad(\ula_|i2s_intf_|Equal1~0_combout ), + .datac(gnd), + .datad(\ula_|i2s_intf_|bdivider [4]), + .cin(\ula_|i2s_intf_|Add2~13 ), + .combout(\ula_|i2s_intf_|Add2~14_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~14 .lut_mask = 16'hF00F; +defparam \ula_|i2s_intf_|Add2~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y31_N28 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~16 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~16_combout = (!\ula_|i2s_intf_|Equal0~2_combout & (!\ula_|i2s_intf_|shiftreg[4]~1_combout & ((\ula_|i2s_intf_|Equal1~1_combout ) # (!\ula_|i2s_intf_|Add2~14_combout )))) + + .dataa(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(\ula_|i2s_intf_|Equal1~1_combout ), + .datac(\ula_|i2s_intf_|shiftreg[4]~1_combout ), + .datad(\ula_|i2s_intf_|Add2~14_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|Add2~16_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~16 .lut_mask = 16'h0405; +defparam \ula_|i2s_intf_|Add2~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y31_N29 +dffeas \ula_|i2s_intf_|bdivider[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|Add2~16_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bdivider [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bdivider[4] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bdivider[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y31_N20 +cycloneive_lcell_comb \ula_|i2s_intf_|Equal1~0 ( +// Equation(s): +// \ula_|i2s_intf_|Equal1~0_combout = (!\ula_|i2s_intf_|bdivider [1] & (\ula_|i2s_intf_|bdivider [4] & (\ula_|i2s_intf_|bdivider [2] & !\ula_|i2s_intf_|bdivider [3]))) + + .dataa(\ula_|i2s_intf_|bdivider [1]), + .datab(\ula_|i2s_intf_|bdivider [4]), + .datac(\ula_|i2s_intf_|bdivider [2]), + .datad(\ula_|i2s_intf_|bdivider [3]), + .cin(gnd), + .combout(\ula_|i2s_intf_|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Equal1~0 .lut_mask = 16'h0040; +defparam \ula_|i2s_intf_|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y31_N14 +cycloneive_lcell_comb \ula_|i2s_intf_|Equal1~1 ( +// Equation(s): +// \ula_|i2s_intf_|Equal1~1_combout = (\ula_|i2s_intf_|Equal1~0_combout & \ula_|i2s_intf_|bdivider [0]) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|Equal1~0_combout ), + .datac(gnd), + .datad(\ula_|i2s_intf_|bdivider [0]), .cin(gnd), .combout(\ula_|i2s_intf_|Equal1~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|Equal1~1 .lut_mask = 16'hF000; +defparam \ula_|i2s_intf_|Equal1~1 .lut_mask = 16'hCC00; defparam \ula_|i2s_intf_|Equal1~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y22_N14 +// Location: LCCOMB_X25_Y31_N18 cycloneive_lcell_comb \ula_|i2s_intf_|bclk_r~0 ( // Equation(s): // \ula_|i2s_intf_|bclk_r~0_combout = \ula_|i2s_intf_|bclk_r~_Duplicate_1_q $ (((\ula_|i2s_intf_|LessThan0~0_combout ) # (!\ula_|i2s_intf_|bitcount [4]))) - .dataa(gnd), + .dataa(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), .datab(\ula_|i2s_intf_|LessThan0~0_combout ), .datac(\ula_|i2s_intf_|bitcount [4]), - .datad(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|bclk_r~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|bclk_r~0 .lut_mask = 16'h30CF; +defparam \ula_|i2s_intf_|bclk_r~0 .lut_mask = 16'h6565; defparam \ula_|i2s_intf_|bclk_r~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y22_N10 +// Location: LCCOMB_X25_Y31_N24 cycloneive_lcell_comb \ula_|i2s_intf_|bclk_r~1 ( // Equation(s): -// \ula_|i2s_intf_|bclk_r~1_combout = (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~1_combout & (\ula_|i2s_intf_|bclk_r~0_combout )) # (!\ula_|i2s_intf_|Equal1~1_combout & ((\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ))))) +// \ula_|i2s_intf_|bclk_r~1_combout = (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~1_combout & ((\ula_|i2s_intf_|bclk_r~0_combout ))) # (!\ula_|i2s_intf_|Equal1~1_combout & (\ula_|i2s_intf_|bclk_r~_Duplicate_1_q )))) .dataa(\ula_|i2s_intf_|Equal1~1_combout ), - .datab(\ula_|i2s_intf_|bclk_r~0_combout ), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), .datac(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|bclk_r~0_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|bclk_r~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|bclk_r~1 .lut_mask = 16'h00D8; +defparam \ula_|i2s_intf_|bclk_r~1 .lut_mask = 16'h3210; defparam \ula_|i2s_intf_|bclk_r~1 .sum_lutc_input = "datac"; // synopsys translate_on @@ -57006,61 +56756,44 @@ defparam \ula_|i2s_intf_|bclk_r .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|bclk_r .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y19_N24 -cycloneive_lcell_comb \ula_|pcm_outl[13]~feeder ( -// Equation(s): -// \ula_|pcm_outl[13]~feeder_combout = \D[3]~96_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\D[3]~96_combout ), - .cin(gnd), - .combout(\ula_|pcm_outl[13]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|pcm_outl[13]~feeder .lut_mask = 16'hFF00; -defparam \ula_|pcm_outl[13]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N2 +// Location: LCCOMB_X29_Y11_N14 cycloneive_lcell_comb \ula_|always0~2 ( // Equation(s): -// \ula_|always0~2_combout = (\z80_|memory_ifc_|nWR_out~0_combout & (!\z80_|memory_ifc_|nRD_out~2_combout & \z80_|resets_|SYNTHESIZED_WIRE_12~q )) +// \ula_|always0~2_combout = (!\z80_|memory_ifc_|nRD_out~2_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \z80_|memory_ifc_|nWR_out~0_combout )) - .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), - .datab(\z80_|memory_ifc_|nRD_out~2_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(gnd), + .dataa(\z80_|memory_ifc_|nRD_out~2_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(gnd), + .datad(\z80_|memory_ifc_|nWR_out~0_combout ), .cin(gnd), .combout(\ula_|always0~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|always0~2 .lut_mask = 16'h2020; +defparam \ula_|always0~2 .lut_mask = 16'h4400; defparam \ula_|always0~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y12_N20 +// Location: LCCOMB_X29_Y11_N26 cycloneive_lcell_comb \ula_|always0~3 ( // Equation(s): -// \ula_|always0~3_combout = (!\z80_|address_pins_|DFFE_apin_latch [0] & (\z80_|memory_ifc_|nIORQ_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \ula_|always0~2_combout ))) +// \ula_|always0~3_combout = (\z80_|memory_ifc_|nIORQ_out~0_combout & (!\z80_|address_pins_|DFFE_apin_latch [0] & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \ula_|always0~2_combout ))) - .dataa(\z80_|address_pins_|DFFE_apin_latch [0]), - .datab(\z80_|memory_ifc_|nIORQ_out~0_combout ), + .dataa(\z80_|memory_ifc_|nIORQ_out~0_combout ), + .datab(\z80_|address_pins_|DFFE_apin_latch [0]), .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .datad(\ula_|always0~2_combout ), .cin(gnd), .combout(\ula_|always0~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|always0~3 .lut_mask = 16'h4000; +defparam \ula_|always0~3 .lut_mask = 16'h2000; defparam \ula_|always0~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y19_N25 -dffeas \ula_|pcm_outl[13] ( +// Location: FF_X31_Y10_N31 +dffeas \ula_|pcm_outl[14] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|pcm_outl[13]~feeder_combout ), + .d(\D[4]~76_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -57069,27 +56802,27 @@ dffeas \ula_|pcm_outl[13] ( .ena(\ula_|always0~3_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\ula_|pcm_outl [13]), + .q(\ula_|pcm_outl [14]), .prn(vcc)); // synopsys translate_off -defparam \ula_|pcm_outl[13] .is_wysiwyg = "true"; -defparam \ula_|pcm_outl[13] .power_up = "low"; +defparam \ula_|pcm_outl[14] .is_wysiwyg = "true"; +defparam \ula_|pcm_outl[14] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y22_N26 +// Location: LCCOMB_X25_Y31_N16 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[0]~19 ( // Equation(s): // \ula_|i2s_intf_|shiftreg[0]~19_combout = (\ula_|i2s_intf_|Equal1~1_combout & (!\ula_|i2s_intf_|bclk_r~_Duplicate_1_q & ((\ula_|i2s_intf_|LessThan0~0_combout ) # (!\ula_|i2s_intf_|bitcount [4])))) .dataa(\ula_|i2s_intf_|Equal1~1_combout ), - .datab(\ula_|i2s_intf_|LessThan0~0_combout ), - .datac(\ula_|i2s_intf_|bitcount [4]), - .datad(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .datab(\ula_|i2s_intf_|bitcount [4]), + .datac(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .datad(\ula_|i2s_intf_|LessThan0~0_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg[0]~19_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[0]~19 .lut_mask = 16'h008A; +defparam \ula_|i2s_intf_|shiftreg[0]~19 .lut_mask = 16'h0A02; defparam \ula_|i2s_intf_|shiftreg[0]~19 .sum_lutc_input = "datac"; // synopsys translate_on @@ -57103,25 +56836,25 @@ defparam \AUD_ADCDAT~input .bus_hold = "false"; defparam \AUD_ADCDAT~input .simulate_z_as = "z"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N20 +// Location: LCCOMB_X24_Y31_N18 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[0]~20 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg[0]~20_combout = (\ula_|i2s_intf_|shiftreg[0]~19_combout & ((\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|shiftreg [0])) # (!\ula_|i2s_intf_|Equal0~2_combout & ((\AUD_ADCDAT~input_o ))))) # -// (!\ula_|i2s_intf_|shiftreg[0]~19_combout & (((\ula_|i2s_intf_|shiftreg [0])))) +// \ula_|i2s_intf_|shiftreg[0]~20_combout = (\ula_|i2s_intf_|Equal0~2_combout & (((\ula_|i2s_intf_|shiftreg [0])))) # (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|shiftreg[0]~19_combout & ((\AUD_ADCDAT~input_o ))) # +// (!\ula_|i2s_intf_|shiftreg[0]~19_combout & (\ula_|i2s_intf_|shiftreg [0])))) - .dataa(\ula_|i2s_intf_|shiftreg[0]~19_combout ), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .dataa(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(\ula_|i2s_intf_|shiftreg[0]~19_combout ), .datac(\ula_|i2s_intf_|shiftreg [0]), .datad(\AUD_ADCDAT~input_o ), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg[0]~20_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[0]~20 .lut_mask = 16'hF2D0; +defparam \ula_|i2s_intf_|shiftreg[0]~20 .lut_mask = 16'hF4B0; defparam \ula_|i2s_intf_|shiftreg[0]~20 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N21 +// Location: FF_X24_Y31_N19 dffeas \ula_|i2s_intf_|shiftreg[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg[0]~20_combout ), @@ -57140,41 +56873,41 @@ defparam \ula_|i2s_intf_|shiftreg[0] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N26 +// Location: LCCOMB_X23_Y31_N26 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~18 ( // Equation(s): // \ula_|i2s_intf_|shiftreg~18_combout = (\ula_|i2s_intf_|shiftreg [0] & !\ula_|i2s_intf_|Equal0~2_combout ) .dataa(gnd), .datab(\ula_|i2s_intf_|shiftreg [0]), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~18_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~18 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~18 .lut_mask = 16'h0C0C; defparam \ula_|i2s_intf_|shiftreg~18 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y22_N30 +// Location: LCCOMB_X25_Y31_N28 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[4]~2 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg[4]~2_combout = (\ula_|i2s_intf_|Equal0~2_combout ) # ((\ula_|i2s_intf_|shiftreg[4]~1_combout & \ula_|i2s_intf_|bclk_r~_Duplicate_1_q )) +// \ula_|i2s_intf_|shiftreg[4]~2_combout = (\ula_|i2s_intf_|Equal0~2_combout ) # ((\ula_|i2s_intf_|bclk_r~_Duplicate_1_q & \ula_|i2s_intf_|shiftreg[4]~1_combout )) - .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg[4]~1_combout ), + .dataa(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .datab(gnd), .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .datad(\ula_|i2s_intf_|shiftreg[4]~1_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg[4]~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[4]~2 .lut_mask = 16'hFCF0; +defparam \ula_|i2s_intf_|shiftreg[4]~2 .lut_mask = 16'hFAF0; defparam \ula_|i2s_intf_|shiftreg[4]~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N27 +// Location: FF_X23_Y31_N27 dffeas \ula_|i2s_intf_|shiftreg[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~18_combout ), @@ -57193,24 +56926,24 @@ defparam \ula_|i2s_intf_|shiftreg[1] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N24 +// Location: LCCOMB_X23_Y31_N12 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~17 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~17_combout = (\ula_|i2s_intf_|shiftreg [1] & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|shiftreg~17_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [1]) .dataa(gnd), - .datab(gnd), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), .datac(\ula_|i2s_intf_|shiftreg [1]), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~17_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~17 .lut_mask = 16'h00F0; +defparam \ula_|i2s_intf_|shiftreg~17 .lut_mask = 16'h3030; defparam \ula_|i2s_intf_|shiftreg~17 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N25 +// Location: FF_X23_Y31_N13 dffeas \ula_|i2s_intf_|shiftreg[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~17_combout ), @@ -57229,24 +56962,24 @@ defparam \ula_|i2s_intf_|shiftreg[2] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N18 +// Location: LCCOMB_X23_Y31_N22 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~16 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~16_combout = (\ula_|i2s_intf_|shiftreg [2] & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|shiftreg~16_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [2]) .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg [2]), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(gnd), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|shiftreg [2]), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~16_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~16 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~16 .lut_mask = 16'h0F00; defparam \ula_|i2s_intf_|shiftreg~16 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N19 +// Location: FF_X23_Y31_N23 dffeas \ula_|i2s_intf_|shiftreg[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~16_combout ), @@ -57265,24 +56998,24 @@ defparam \ula_|i2s_intf_|shiftreg[3] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N0 +// Location: LCCOMB_X23_Y31_N0 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~15 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~15_combout = (\ula_|i2s_intf_|shiftreg [3] & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|shiftreg~15_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [3]) .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg [3]), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|shiftreg [3]), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~15_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~15 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~15 .lut_mask = 16'h3030; defparam \ula_|i2s_intf_|shiftreg~15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N1 +// Location: FF_X23_Y31_N1 dffeas \ula_|i2s_intf_|shiftreg[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~15_combout ), @@ -57301,24 +57034,24 @@ defparam \ula_|i2s_intf_|shiftreg[4] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N10 +// Location: LCCOMB_X23_Y31_N14 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~14 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~14_combout = (\ula_|i2s_intf_|shiftreg [4] & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|shiftreg~14_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [4]) .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg [4]), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(gnd), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|shiftreg [4]), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~14_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~14 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~14 .lut_mask = 16'h0F00; defparam \ula_|i2s_intf_|shiftreg~14 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N11 +// Location: FF_X23_Y31_N15 dffeas \ula_|i2s_intf_|shiftreg[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~14_combout ), @@ -57337,24 +57070,24 @@ defparam \ula_|i2s_intf_|shiftreg[5] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N16 +// Location: LCCOMB_X23_Y31_N24 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~13 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~13_combout = (\ula_|i2s_intf_|shiftreg [5] & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|shiftreg~13_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [5]) - .dataa(\ula_|i2s_intf_|shiftreg [5]), - .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .dataa(gnd), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|shiftreg [5]), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~13_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~13 .lut_mask = 16'h00AA; +defparam \ula_|i2s_intf_|shiftreg~13 .lut_mask = 16'h3030; defparam \ula_|i2s_intf_|shiftreg~13 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N17 +// Location: FF_X23_Y31_N25 dffeas \ula_|i2s_intf_|shiftreg[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~13_combout ), @@ -57373,24 +57106,24 @@ defparam \ula_|i2s_intf_|shiftreg[6] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N30 +// Location: LCCOMB_X23_Y31_N30 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~12 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~12_combout = (\ula_|i2s_intf_|shiftreg [6] & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|shiftreg~12_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [6]) .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg [6]), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(gnd), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|shiftreg [6]), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~12_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~12 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~12 .lut_mask = 16'h0F00; defparam \ula_|i2s_intf_|shiftreg~12 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N31 +// Location: FF_X23_Y31_N31 dffeas \ula_|i2s_intf_|shiftreg[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~12_combout ), @@ -57409,24 +57142,24 @@ defparam \ula_|i2s_intf_|shiftreg[7] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N28 +// Location: LCCOMB_X23_Y31_N20 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~11 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~11_combout = (\ula_|i2s_intf_|shiftreg [7] & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|shiftreg~11_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [7]) .dataa(gnd), - .datab(gnd), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), .datac(\ula_|i2s_intf_|shiftreg [7]), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~11_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~11 .lut_mask = 16'h00F0; +defparam \ula_|i2s_intf_|shiftreg~11 .lut_mask = 16'h3030; defparam \ula_|i2s_intf_|shiftreg~11 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N29 +// Location: FF_X23_Y31_N21 dffeas \ula_|i2s_intf_|shiftreg[8] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~11_combout ), @@ -57445,24 +57178,24 @@ defparam \ula_|i2s_intf_|shiftreg[8] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[8] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N22 +// Location: LCCOMB_X23_Y31_N6 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~10 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~10_combout = (\ula_|i2s_intf_|shiftreg [8] & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|shiftreg~10_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [8]) .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg [8]), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(gnd), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|shiftreg [8]), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~10_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~10 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~10 .lut_mask = 16'h0F00; defparam \ula_|i2s_intf_|shiftreg~10 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N23 +// Location: FF_X23_Y31_N7 dffeas \ula_|i2s_intf_|shiftreg[9] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~10_combout ), @@ -57481,24 +57214,24 @@ defparam \ula_|i2s_intf_|shiftreg[9] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[9] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N12 +// Location: LCCOMB_X23_Y31_N16 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~9 ( // Equation(s): // \ula_|i2s_intf_|shiftreg~9_combout = (\ula_|i2s_intf_|shiftreg [9] & !\ula_|i2s_intf_|Equal0~2_combout ) - .dataa(gnd), + .dataa(\ula_|i2s_intf_|shiftreg [9]), .datab(gnd), - .datac(\ula_|i2s_intf_|shiftreg [9]), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~9_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~9 .lut_mask = 16'h00F0; +defparam \ula_|i2s_intf_|shiftreg~9 .lut_mask = 16'h0A0A; defparam \ula_|i2s_intf_|shiftreg~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N13 +// Location: FF_X23_Y31_N17 dffeas \ula_|i2s_intf_|shiftreg[10] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~9_combout ), @@ -57517,24 +57250,24 @@ defparam \ula_|i2s_intf_|shiftreg[10] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[10] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N2 +// Location: LCCOMB_X23_Y31_N18 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~8 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~8_combout = (\ula_|i2s_intf_|shiftreg [10] & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|shiftreg~8_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [10]) - .dataa(\ula_|i2s_intf_|shiftreg [10]), + .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|shiftreg [10]), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~8_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~8 .lut_mask = 16'h00AA; +defparam \ula_|i2s_intf_|shiftreg~8 .lut_mask = 16'h0F00; defparam \ula_|i2s_intf_|shiftreg~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N3 +// Location: FF_X23_Y31_N19 dffeas \ula_|i2s_intf_|shiftreg[11] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~8_combout ), @@ -57553,24 +57286,24 @@ defparam \ula_|i2s_intf_|shiftreg[11] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[11] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N8 +// Location: LCCOMB_X23_Y31_N28 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~7 ( // Equation(s): // \ula_|i2s_intf_|shiftreg~7_combout = (\ula_|i2s_intf_|shiftreg [11] & !\ula_|i2s_intf_|Equal0~2_combout ) .dataa(gnd), .datab(\ula_|i2s_intf_|shiftreg [11]), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~7_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~7 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~7 .lut_mask = 16'h0C0C; defparam \ula_|i2s_intf_|shiftreg~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N9 +// Location: FF_X23_Y31_N29 dffeas \ula_|i2s_intf_|shiftreg[12] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~7_combout ), @@ -57589,62 +57322,25 @@ defparam \ula_|i2s_intf_|shiftreg[12] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[12] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y22_N30 -cycloneive_lcell_comb \ula_|i2s_intf_|PCM_INR[14]~0 ( -// Equation(s): -// \ula_|i2s_intf_|PCM_INR[14]~0_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & (\ula_|i2s_intf_|shiftreg [14])) # (!\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & ((\ula_|i2s_intf_|PCM_INR [14]))))) # -// (!\ula_|i2s_intf_|Equal0~2_combout & (((\ula_|i2s_intf_|PCM_INR [14])))) - - .dataa(\ula_|i2s_intf_|shiftreg [14]), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), - .datac(\ula_|i2s_intf_|PCM_INR [14]), - .datad(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), - .cin(gnd), - .combout(\ula_|i2s_intf_|PCM_INR[14]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|PCM_INR[14]~0 .lut_mask = 16'hB8F0; -defparam \ula_|i2s_intf_|PCM_INR[14]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y22_N31 -dffeas \ula_|i2s_intf_|PCM_INR[14] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|PCM_INR[14]~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|PCM_INR [14]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|PCM_INR[14] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|PCM_INR[14] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y22_N28 +// Location: LCCOMB_X24_Y31_N30 cycloneive_lcell_comb \ula_|i2s_intf_|PCM_INL[14]~0 ( // Equation(s): -// \ula_|i2s_intf_|PCM_INL[14]~0_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & ((\ula_|i2s_intf_|PCM_INL [14]))) # (!\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & (\ula_|i2s_intf_|shiftreg [14])))) # +// \ula_|i2s_intf_|PCM_INL[14]~0_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & (\ula_|i2s_intf_|PCM_INL [14])) # (!\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & ((\ula_|i2s_intf_|shiftreg [14]))))) # // (!\ula_|i2s_intf_|Equal0~2_combout & (((\ula_|i2s_intf_|PCM_INL [14])))) - .dataa(\ula_|i2s_intf_|shiftreg [14]), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .dataa(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), .datac(\ula_|i2s_intf_|PCM_INL [14]), - .datad(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), + .datad(\ula_|i2s_intf_|shiftreg [14]), .cin(gnd), .combout(\ula_|i2s_intf_|PCM_INL[14]~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|PCM_INL[14]~0 .lut_mask = 16'hF0B8; +defparam \ula_|i2s_intf_|PCM_INL[14]~0 .lut_mask = 16'hF2D0; defparam \ula_|i2s_intf_|PCM_INL[14]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y22_N29 +// Location: FF_X24_Y31_N31 dffeas \ula_|i2s_intf_|PCM_INL[14] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|PCM_INL[14]~0_combout ), @@ -57663,15 +57359,52 @@ defparam \ula_|i2s_intf_|PCM_INL[14] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|PCM_INL[14] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y22_N6 +// Location: LCCOMB_X24_Y31_N16 +cycloneive_lcell_comb \ula_|i2s_intf_|PCM_INR[14]~0 ( +// Equation(s): +// \ula_|i2s_intf_|PCM_INR[14]~0_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & ((\ula_|i2s_intf_|shiftreg [14]))) # (!\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & (\ula_|i2s_intf_|PCM_INR [14])))) # +// (!\ula_|i2s_intf_|Equal0~2_combout & (((\ula_|i2s_intf_|PCM_INR [14])))) + + .dataa(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), + .datac(\ula_|i2s_intf_|PCM_INR [14]), + .datad(\ula_|i2s_intf_|shiftreg [14]), + .cin(gnd), + .combout(\ula_|i2s_intf_|PCM_INR[14]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|PCM_INR[14]~0 .lut_mask = 16'hF870; +defparam \ula_|i2s_intf_|PCM_INR[14]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y31_N17 +dffeas \ula_|i2s_intf_|PCM_INR[14] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|PCM_INR[14]~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|PCM_INR [14]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|PCM_INR[14] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|PCM_INR[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y31_N24 cycloneive_lcell_comb \ula_|pcm_outr~0 ( // Equation(s): -// \ula_|pcm_outr~0_combout = (\ula_|i2s_intf_|PCM_INR [14]) # (\ula_|i2s_intf_|PCM_INL [14]) +// \ula_|pcm_outr~0_combout = (\ula_|i2s_intf_|PCM_INL [14]) # (\ula_|i2s_intf_|PCM_INR [14]) .dataa(gnd), .datab(gnd), - .datac(\ula_|i2s_intf_|PCM_INR [14]), - .datad(\ula_|i2s_intf_|PCM_INL [14]), + .datac(\ula_|i2s_intf_|PCM_INL [14]), + .datad(\ula_|i2s_intf_|PCM_INR [14]), .cin(gnd), .combout(\ula_|pcm_outr~0_combout ), .cout()); @@ -57680,7 +57413,7 @@ defparam \ula_|pcm_outr~0 .lut_mask = 16'hFFF0; defparam \ula_|pcm_outr~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y22_N7 +// Location: FF_X24_Y31_N25 dffeas \ula_|pcm_outl[12] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\ula_|pcm_outr~0_combout ), @@ -57699,24 +57432,24 @@ defparam \ula_|pcm_outl[12] .is_wysiwyg = "true"; defparam \ula_|pcm_outl[12] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N14 +// Location: LCCOMB_X23_Y31_N10 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~6 ( // Equation(s): // \ula_|i2s_intf_|shiftreg~6_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|pcm_outl [12]))) # (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|shiftreg [12])) .dataa(gnd), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), - .datac(\ula_|i2s_intf_|shiftreg [12]), + .datab(\ula_|i2s_intf_|shiftreg [12]), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), .datad(\ula_|pcm_outl [12]), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~6_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~6 .lut_mask = 16'hFC30; +defparam \ula_|i2s_intf_|shiftreg~6 .lut_mask = 16'hFC0C; defparam \ula_|i2s_intf_|shiftreg~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N15 +// Location: FF_X23_Y31_N11 dffeas \ula_|i2s_intf_|shiftreg[13] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~6_combout ), @@ -57735,24 +57468,43 @@ defparam \ula_|i2s_intf_|shiftreg[13] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[13] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N4 +// Location: FF_X23_Y14_N9 +dffeas \ula_|pcm_outl[13] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\D[3]~74_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|always0~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|pcm_outl [13]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|pcm_outl[13] .is_wysiwyg = "true"; +defparam \ula_|pcm_outl[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y31_N8 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~5 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~5_combout = (\ula_|i2s_intf_|Equal0~2_combout & (\ula_|pcm_outl [13])) # (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|shiftreg [13]))) +// \ula_|i2s_intf_|shiftreg~5_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|pcm_outl [13]))) # (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|shiftreg [13])) - .dataa(gnd), - .datab(\ula_|pcm_outl [13]), - .datac(\ula_|i2s_intf_|shiftreg [13]), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .dataa(\ula_|i2s_intf_|shiftreg [13]), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(gnd), + .datad(\ula_|pcm_outl [13]), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~5_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~5 .lut_mask = 16'hCCF0; +defparam \ula_|i2s_intf_|shiftreg~5 .lut_mask = 16'hEE22; defparam \ula_|i2s_intf_|shiftreg~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N5 +// Location: FF_X23_Y31_N9 dffeas \ula_|i2s_intf_|shiftreg[14] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~5_combout ), @@ -57771,43 +57523,24 @@ defparam \ula_|i2s_intf_|shiftreg[14] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[14] .power_up = "low"; // synopsys translate_on -// Location: FF_X29_Y14_N31 -dffeas \ula_|pcm_outl[14] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\D[4]~98_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|always0~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|pcm_outl [14]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|pcm_outl[14] .is_wysiwyg = "true"; -defparam \ula_|pcm_outl[14] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y22_N4 +// Location: LCCOMB_X23_Y31_N2 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~4 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~4_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|pcm_outl [14]))) # (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|shiftreg [14])) +// \ula_|i2s_intf_|shiftreg~4_combout = (\ula_|i2s_intf_|Equal0~2_combout & (\ula_|pcm_outl [14])) # (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|shiftreg [14]))) - .dataa(\ula_|i2s_intf_|shiftreg [14]), - .datab(gnd), - .datac(\ula_|pcm_outl [14]), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .dataa(\ula_|pcm_outl [14]), + .datab(\ula_|i2s_intf_|shiftreg [14]), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~4_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~4 .lut_mask = 16'hF0AA; +defparam \ula_|i2s_intf_|shiftreg~4 .lut_mask = 16'hACAC; defparam \ula_|i2s_intf_|shiftreg~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y22_N5 +// Location: FF_X23_Y31_N3 dffeas \ula_|i2s_intf_|shiftreg[15] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~4_combout ), @@ -57826,24 +57559,24 @@ defparam \ula_|i2s_intf_|shiftreg[15] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[15] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y22_N0 +// Location: LCCOMB_X23_Y32_N12 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~3 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~3_combout = (\ula_|i2s_intf_|shiftreg [15] & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|shiftreg~3_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [15]) - .dataa(gnd), + .dataa(\ula_|i2s_intf_|Equal0~2_combout ), .datab(gnd), .datac(\ula_|i2s_intf_|shiftreg [15]), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~3 .lut_mask = 16'h00F0; +defparam \ula_|i2s_intf_|shiftreg~3 .lut_mask = 16'h5050; defparam \ula_|i2s_intf_|shiftreg~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y22_N1 +// Location: FF_X23_Y32_N13 dffeas \ula_|i2s_intf_|shiftreg[16] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~3_combout ), @@ -57862,20 +57595,20 @@ defparam \ula_|i2s_intf_|shiftreg[16] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[16] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y22_N10 +// Location: LCCOMB_X23_Y32_N2 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~0 ( // Equation(s): // \ula_|i2s_intf_|shiftreg~0_combout = (\ula_|i2s_intf_|shiftreg [16] & !\ula_|i2s_intf_|Equal0~2_combout ) - .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg [16]), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .dataa(\ula_|i2s_intf_|shiftreg [16]), + .datab(gnd), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~0 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~0 .lut_mask = 16'h0A0A; defparam \ula_|i2s_intf_|shiftreg~0 .sum_lutc_input = "datac"; // synopsys translate_on @@ -57898,32 +57631,85 @@ defparam \ula_|i2s_intf_|shiftreg[17] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[17] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X38_Y33_N8 -cycloneive_lcell_comb \ula_|video_|LessThan2~0 ( +// Location: LCCOMB_X31_Y10_N24 +cycloneive_lcell_comb \ula_|border[1]~feeder ( // Equation(s): -// \ula_|video_|LessThan2~0_combout = (!\ula_|video_|vga_vc [9] & (!\ula_|video_|vga_vc [8] & (!\ula_|video_|vga_vc [7] & !\ula_|video_|vga_vc [6]))) +// \ula_|border[1]~feeder_combout = \D[1]~32_combout - .dataa(\ula_|video_|vga_vc [9]), - .datab(\ula_|video_|vga_vc [8]), - .datac(\ula_|video_|vga_vc [7]), - .datad(\ula_|video_|vga_vc [6]), + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\D[1]~32_combout ), .cin(gnd), - .combout(\ula_|video_|LessThan2~0_combout ), + .combout(\ula_|border[1]~feeder_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|LessThan2~0 .lut_mask = 16'h0001; -defparam \ula_|video_|LessThan2~0 .sum_lutc_input = "datac"; +defparam \ula_|border[1]~feeder .lut_mask = 16'hFF00; +defparam \ula_|border[1]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y33_N4 +// Location: FF_X31_Y10_N25 +dffeas \ula_|border[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|border[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|always0~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|border [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|border[1] .is_wysiwyg = "true"; +defparam \ula_|border[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y32_N30 +cycloneive_lcell_comb \ula_|video_|LessThan4~0 ( +// Equation(s): +// \ula_|video_|LessThan4~0_combout = (((!\ula_|video_|vga_hc [4] & !\ula_|video_|vga_hc [5])) # (!\ula_|video_|vga_hc [7])) # (!\ula_|video_|vga_hc [6]) + + .dataa(\ula_|video_|vga_hc [4]), + .datab(\ula_|video_|vga_hc [6]), + .datac(\ula_|video_|vga_hc [7]), + .datad(\ula_|video_|vga_hc [5]), + .cin(gnd), + .combout(\ula_|video_|LessThan4~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|LessThan4~0 .lut_mask = 16'h3F7F; +defparam \ula_|video_|LessThan4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y32_N26 +cycloneive_lcell_comb \ula_|video_|screen_en~0 ( +// Equation(s): +// \ula_|video_|screen_en~0_combout = (!\ula_|video_|vga_vc [9] & (\ula_|video_|vga_hc [9] $ (((\ula_|video_|vga_hc [8]) # (!\ula_|video_|LessThan4~0_combout ))))) + + .dataa(\ula_|video_|vga_hc [9]), + .datab(\ula_|video_|vga_vc [9]), + .datac(\ula_|video_|vga_hc [8]), + .datad(\ula_|video_|LessThan4~0_combout ), + .cin(gnd), + .combout(\ula_|video_|screen_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|screen_en~0 .lut_mask = 16'h1211; +defparam \ula_|video_|screen_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y32_N28 cycloneive_lcell_comb \ula_|video_|LessThan6~0 ( // Equation(s): -// \ula_|video_|LessThan6~0_combout = (!\ula_|video_|vga_vc [2] & (!\ula_|video_|vga_vc [3] & ((!\ula_|video_|vga_vc [0]) # (!\ula_|video_|vga_vc [1])))) +// \ula_|video_|LessThan6~0_combout = (!\ula_|video_|vga_vc [3] & (!\ula_|video_|vga_vc [2] & ((!\ula_|video_|vga_vc [1]) # (!\ula_|video_|vga_vc [0])))) - .dataa(\ula_|video_|vga_vc [2]), - .datab(\ula_|video_|vga_vc [3]), - .datac(\ula_|video_|vga_vc [1]), - .datad(\ula_|video_|vga_vc [0]), + .dataa(\ula_|video_|vga_vc [3]), + .datab(\ula_|video_|vga_vc [2]), + .datac(\ula_|video_|vga_vc [0]), + .datad(\ula_|video_|vga_vc [1]), .cin(gnd), .combout(\ula_|video_|LessThan6~0_combout ), .cout()); @@ -57932,76 +57718,128 @@ defparam \ula_|video_|LessThan6~0 .lut_mask = 16'h0111; defparam \ula_|video_|LessThan6~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y33_N30 +// Location: LCCOMB_X35_Y32_N12 +cycloneive_lcell_comb \ula_|video_|LessThan6~1 ( +// Equation(s): +// \ula_|video_|LessThan6~1_combout = ((!\ula_|video_|vga_vc [5] & ((\ula_|video_|LessThan6~0_combout ) # (!\ula_|video_|vga_vc [4])))) # (!\ula_|video_|vga_vc [6]) + + .dataa(\ula_|video_|vga_vc [4]), + .datab(\ula_|video_|vga_vc [6]), + .datac(\ula_|video_|vga_vc [5]), + .datad(\ula_|video_|LessThan6~0_combout ), + .cin(gnd), + .combout(\ula_|video_|LessThan6~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|LessThan6~1 .lut_mask = 16'h3F37; +defparam \ula_|video_|LessThan6~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y32_N22 +cycloneive_lcell_comb \ula_|video_|screen_en~1 ( +// Equation(s): +// \ula_|video_|screen_en~1_combout = (\ula_|video_|screen_en~0_combout & ((\ula_|video_|vga_vc [7] & ((\ula_|video_|LessThan6~1_combout ) # (!\ula_|video_|vga_vc [8]))) # (!\ula_|video_|vga_vc [7] & ((\ula_|video_|vga_vc [8]) # +// (!\ula_|video_|LessThan6~1_combout ))))) + + .dataa(\ula_|video_|vga_vc [7]), + .datab(\ula_|video_|vga_vc [8]), + .datac(\ula_|video_|screen_en~0_combout ), + .datad(\ula_|video_|LessThan6~1_combout ), + .cin(gnd), + .combout(\ula_|video_|screen_en~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|screen_en~1 .lut_mask = 16'hE070; +defparam \ula_|video_|screen_en~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y32_N14 +cycloneive_lcell_comb \ula_|video_|LessThan2~0 ( +// Equation(s): +// \ula_|video_|LessThan2~0_combout = (!\ula_|video_|vga_vc [9] & (!\ula_|video_|vga_vc [8] & (!\ula_|video_|vga_vc [6] & !\ula_|video_|vga_vc [7]))) + + .dataa(\ula_|video_|vga_vc [9]), + .datab(\ula_|video_|vga_vc [8]), + .datac(\ula_|video_|vga_vc [6]), + .datad(\ula_|video_|vga_vc [7]), + .cin(gnd), + .combout(\ula_|video_|LessThan2~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|LessThan2~0 .lut_mask = 16'h0001; +defparam \ula_|video_|LessThan2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y32_N12 cycloneive_lcell_comb \ula_|video_|LessThan2~1 ( // Equation(s): // \ula_|video_|LessThan2~1_combout = (\ula_|video_|LessThan2~0_combout & (((!\ula_|video_|vga_vc [4] & \ula_|video_|LessThan6~0_combout )) # (!\ula_|video_|vga_vc [5]))) - .dataa(\ula_|video_|vga_vc [5]), - .datab(\ula_|video_|vga_vc [4]), + .dataa(\ula_|video_|vga_vc [4]), + .datab(\ula_|video_|vga_vc [5]), .datac(\ula_|video_|LessThan2~0_combout ), .datad(\ula_|video_|LessThan6~0_combout ), .cin(gnd), .combout(\ula_|video_|LessThan2~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|LessThan2~1 .lut_mask = 16'h7050; +defparam \ula_|video_|LessThan2~1 .lut_mask = 16'h7030; defparam \ula_|video_|LessThan2~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y33_N16 +// Location: LCCOMB_X36_Y32_N4 cycloneive_lcell_comb \ula_|video_|LessThan3~0 ( // Equation(s): -// \ula_|video_|LessThan3~0_combout = ((\ula_|video_|LessThan6~0_combout & (!\ula_|video_|vga_vc [5] & \ula_|video_|Equal2~0_combout ))) # (!\ula_|video_|vga_vc [9]) +// \ula_|video_|LessThan3~0_combout = ((!\ula_|video_|vga_vc [5] & (\ula_|video_|LessThan6~0_combout & \ula_|video_|Equal2~0_combout ))) # (!\ula_|video_|vga_vc [9]) - .dataa(\ula_|video_|vga_vc [9]), + .dataa(\ula_|video_|vga_vc [5]), .datab(\ula_|video_|LessThan6~0_combout ), - .datac(\ula_|video_|vga_vc [5]), + .datac(\ula_|video_|vga_vc [9]), .datad(\ula_|video_|Equal2~0_combout ), .cin(gnd), .combout(\ula_|video_|LessThan3~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|LessThan3~0 .lut_mask = 16'h5D55; +defparam \ula_|video_|LessThan3~0 .lut_mask = 16'h4F0F; defparam \ula_|video_|LessThan3~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y33_N22 +// Location: LCCOMB_X34_Y32_N2 cycloneive_lcell_comb \ula_|video_|LessThan0~0 ( // Equation(s): -// \ula_|video_|LessThan0~0_combout = (!\ula_|video_|vga_hc [4] & (!\ula_|video_|vga_hc [6] & !\ula_|video_|vga_hc [5])) +// \ula_|video_|LessThan0~0_combout = (!\ula_|video_|vga_hc [6] & (!\ula_|video_|vga_hc [4] & !\ula_|video_|vga_hc [5])) - .dataa(\ula_|video_|vga_hc [4]), + .dataa(gnd), .datab(\ula_|video_|vga_hc [6]), - .datac(gnd), + .datac(\ula_|video_|vga_hc [4]), .datad(\ula_|video_|vga_hc [5]), .cin(gnd), .combout(\ula_|video_|LessThan0~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|LessThan0~0 .lut_mask = 16'h0011; +defparam \ula_|video_|LessThan0~0 .lut_mask = 16'h0003; defparam \ula_|video_|LessThan0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y33_N24 +// Location: LCCOMB_X34_Y32_N0 cycloneive_lcell_comb \ula_|video_|disp_enable~0 ( // Equation(s): -// \ula_|video_|disp_enable~0_combout = (\ula_|video_|vga_hc [8] & (((\ula_|video_|LessThan0~0_combout & !\ula_|video_|vga_hc [7])) # (!\ula_|video_|vga_hc [9]))) # (!\ula_|video_|vga_hc [8] & ((\ula_|video_|vga_hc [9]) # -// ((!\ula_|video_|LessThan0~0_combout & \ula_|video_|vga_hc [7])))) +// \ula_|video_|disp_enable~0_combout = (\ula_|video_|vga_hc [8] & (((!\ula_|video_|vga_hc [7] & \ula_|video_|LessThan0~0_combout )) # (!\ula_|video_|vga_hc [9]))) # (!\ula_|video_|vga_hc [8] & ((\ula_|video_|vga_hc [9]) # ((\ula_|video_|vga_hc [7] & +// !\ula_|video_|LessThan0~0_combout )))) - .dataa(\ula_|video_|LessThan0~0_combout ), + .dataa(\ula_|video_|vga_hc [7]), .datab(\ula_|video_|vga_hc [8]), - .datac(\ula_|video_|vga_hc [7]), - .datad(\ula_|video_|vga_hc [9]), + .datac(\ula_|video_|vga_hc [9]), + .datad(\ula_|video_|LessThan0~0_combout ), .cin(gnd), .combout(\ula_|video_|disp_enable~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|disp_enable~0 .lut_mask = 16'h3BDC; +defparam \ula_|video_|disp_enable~0 .lut_mask = 16'h7C3E; defparam \ula_|video_|disp_enable~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y33_N2 +// Location: LCCOMB_X36_Y32_N6 cycloneive_lcell_comb \ula_|video_|disp_enable~1 ( // Equation(s): // \ula_|video_|disp_enable~1_combout = (!\ula_|video_|LessThan2~1_combout & (\ula_|video_|LessThan3~0_combout & \ula_|video_|disp_enable~0_combout )) @@ -58018,239 +57856,7 @@ defparam \ula_|video_|disp_enable~1 .lut_mask = 16'h4400; defparam \ula_|video_|disp_enable~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y22_N11 -dffeas \ula_|border[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\D[1]~34_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|always0~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|border [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|border[1] .is_wysiwyg = "true"; -defparam \ula_|border[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y33_N8 -cycloneive_lcell_comb \ula_|video_|LessThan6~1 ( -// Equation(s): -// \ula_|video_|LessThan6~1_combout = ((!\ula_|video_|vga_vc [5] & ((\ula_|video_|LessThan6~0_combout ) # (!\ula_|video_|vga_vc [4])))) # (!\ula_|video_|vga_vc [6]) - - .dataa(\ula_|video_|vga_vc [6]), - .datab(\ula_|video_|vga_vc [5]), - .datac(\ula_|video_|vga_vc [4]), - .datad(\ula_|video_|LessThan6~0_combout ), - .cin(gnd), - .combout(\ula_|video_|LessThan6~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|LessThan6~1 .lut_mask = 16'h7757; -defparam \ula_|video_|LessThan6~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N28 -cycloneive_lcell_comb \ula_|video_|LessThan4~0 ( -// Equation(s): -// \ula_|video_|LessThan4~0_combout = (((!\ula_|video_|vga_hc [4] & !\ula_|video_|vga_hc [5])) # (!\ula_|video_|vga_hc [7])) # (!\ula_|video_|vga_hc [6]) - - .dataa(\ula_|video_|vga_hc [4]), - .datab(\ula_|video_|vga_hc [5]), - .datac(\ula_|video_|vga_hc [6]), - .datad(\ula_|video_|vga_hc [7]), - .cin(gnd), - .combout(\ula_|video_|LessThan4~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|LessThan4~0 .lut_mask = 16'h1FFF; -defparam \ula_|video_|LessThan4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y33_N10 -cycloneive_lcell_comb \ula_|video_|screen_en~0 ( -// Equation(s): -// \ula_|video_|screen_en~0_combout = (!\ula_|video_|vga_vc [9] & (\ula_|video_|vga_hc [9] $ (((\ula_|video_|vga_hc [8]) # (!\ula_|video_|LessThan4~0_combout ))))) - - .dataa(\ula_|video_|vga_hc [9]), - .datab(\ula_|video_|vga_vc [9]), - .datac(\ula_|video_|LessThan4~0_combout ), - .datad(\ula_|video_|vga_hc [8]), - .cin(gnd), - .combout(\ula_|video_|screen_en~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|screen_en~0 .lut_mask = 16'h1121; -defparam \ula_|video_|screen_en~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y33_N22 -cycloneive_lcell_comb \ula_|video_|screen_en~1 ( -// Equation(s): -// \ula_|video_|screen_en~1_combout = (\ula_|video_|screen_en~0_combout & ((\ula_|video_|vga_vc [7] & ((\ula_|video_|LessThan6~1_combout ) # (!\ula_|video_|vga_vc [8]))) # (!\ula_|video_|vga_vc [7] & ((\ula_|video_|vga_vc [8]) # -// (!\ula_|video_|LessThan6~1_combout ))))) - - .dataa(\ula_|video_|vga_vc [7]), - .datab(\ula_|video_|vga_vc [8]), - .datac(\ula_|video_|LessThan6~1_combout ), - .datad(\ula_|video_|screen_en~0_combout ), - .cin(gnd), - .combout(\ula_|video_|screen_en~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|screen_en~1 .lut_mask = 16'hE700; -defparam \ula_|video_|screen_en~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y33_N28 -cycloneive_lcell_comb \ula_|video_|attr_prefetch[1]~feeder ( -// Equation(s): -// \ula_|video_|attr_prefetch[1]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|attr_prefetch[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|attr_prefetch[1]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|attr_prefetch[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N10 -cycloneive_lcell_comb \ula_|video_|Decoder0~1 ( -// Equation(s): -// \ula_|video_|Decoder0~1_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|vga_hc [3] & (\ula_|video_|vga_hc [1] & !\ula_|video_|vga_hc [0]))) - - .dataa(\ula_|video_|vga_hc [2]), - .datab(\ula_|video_|vga_hc [3]), - .datac(\ula_|video_|vga_hc [1]), - .datad(\ula_|video_|vga_hc [0]), - .cin(gnd), - .combout(\ula_|video_|Decoder0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Decoder0~1 .lut_mask = 16'h0080; -defparam \ula_|video_|Decoder0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y33_N29 -dffeas \ula_|video_|attr_prefetch[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|attr_prefetch[1]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|attr_prefetch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|attr_prefetch[1] .is_wysiwyg = "true"; -defparam \ula_|video_|attr_prefetch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N12 -cycloneive_lcell_comb \ula_|video_|Decoder0~0 ( -// Equation(s): -// \ula_|video_|Decoder0~0_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|vga_hc [3] & (\ula_|video_|vga_hc [1] & \ula_|video_|vga_hc [0]))) - - .dataa(\ula_|video_|vga_hc [2]), - .datab(\ula_|video_|vga_hc [3]), - .datac(\ula_|video_|vga_hc [1]), - .datad(\ula_|video_|vga_hc [0]), - .cin(gnd), - .combout(\ula_|video_|Decoder0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Decoder0~0 .lut_mask = 16'h8000; -defparam \ula_|video_|Decoder0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y33_N27 -dffeas \ula_|video_|attr[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|attr_prefetch [1]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|Decoder0~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|attr [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|attr[1] .is_wysiwyg = "true"; -defparam \ula_|video_|attr[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y33_N10 -cycloneive_lcell_comb \ula_|video_|attr_prefetch[4]~feeder ( -// Equation(s): -// \ula_|video_|attr_prefetch[4]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|attr_prefetch[4]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|attr_prefetch[4]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|attr_prefetch[4]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y33_N11 -dffeas \ula_|video_|attr_prefetch[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|attr_prefetch[4]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|attr_prefetch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|attr_prefetch[4] .is_wysiwyg = "true"; -defparam \ula_|video_|attr_prefetch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X37_Y33_N13 -dffeas \ula_|video_|attr[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|attr_prefetch [4]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|Decoder0~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|attr [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|attr[4] .is_wysiwyg = "true"; -defparam \ula_|video_|attr[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y33_N24 +// Location: LCCOMB_X38_Y32_N8 cycloneive_lcell_comb \ula_|video_|attr_prefetch[7]~feeder ( // Equation(s): // \ula_|video_|attr_prefetch[7]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 @@ -58267,7 +57873,24 @@ defparam \ula_|video_|attr_prefetch[7]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|attr_prefetch[7]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N25 +// Location: LCCOMB_X35_Y31_N24 +cycloneive_lcell_comb \ula_|video_|Decoder0~1 ( +// Equation(s): +// \ula_|video_|Decoder0~1_combout = (\ula_|video_|vga_hc [1] & (\ula_|video_|vga_hc [3] & (\ula_|video_|vga_hc [2] & !\ula_|video_|vga_hc [0]))) + + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|vga_hc [3]), + .datac(\ula_|video_|vga_hc [2]), + .datad(\ula_|video_|vga_hc [0]), + .cin(gnd), + .combout(\ula_|video_|Decoder0~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Decoder0~1 .lut_mask = 16'h0080; +defparam \ula_|video_|Decoder0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X38_Y32_N9 dffeas \ula_|video_|attr_prefetch[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr_prefetch[7]~feeder_combout ), @@ -58286,7 +57909,24 @@ defparam \ula_|video_|attr_prefetch[7] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[7] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y33_N5 +// Location: LCCOMB_X35_Y31_N2 +cycloneive_lcell_comb \ula_|video_|Decoder0~0 ( +// Equation(s): +// \ula_|video_|Decoder0~0_combout = (\ula_|video_|vga_hc [1] & (\ula_|video_|vga_hc [3] & (\ula_|video_|vga_hc [2] & \ula_|video_|vga_hc [0]))) + + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|vga_hc [3]), + .datac(\ula_|video_|vga_hc [2]), + .datad(\ula_|video_|vga_hc [0]), + .cin(gnd), + .combout(\ula_|video_|Decoder0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Decoder0~0 .lut_mask = 16'h8000; +defparam \ula_|video_|Decoder0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y32_N23 dffeas \ula_|video_|attr[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -58305,24 +57945,24 @@ defparam \ula_|video_|attr[7] .is_wysiwyg = "true"; defparam \ula_|video_|attr[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y33_N22 +// Location: LCCOMB_X35_Y31_N0 cycloneive_lcell_comb \ula_|video_|frame[0]~12 ( // Equation(s): -// \ula_|video_|frame[0]~12_combout = \ula_|video_|Equal3~1_combout $ (\ula_|video_|frame [0]) +// \ula_|video_|frame[0]~12_combout = \ula_|video_|frame [0] $ (\ula_|video_|Equal3~1_combout ) - .dataa(\ula_|video_|Equal3~1_combout ), + .dataa(gnd), .datab(gnd), .datac(\ula_|video_|frame [0]), - .datad(gnd), + .datad(\ula_|video_|Equal3~1_combout ), .cin(gnd), .combout(\ula_|video_|frame[0]~12_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|frame[0]~12 .lut_mask = 16'h5A5A; +defparam \ula_|video_|frame[0]~12 .lut_mask = 16'h0FF0; defparam \ula_|video_|frame[0]~12 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X34_Y33_N23 +// Location: FF_X35_Y31_N1 dffeas \ula_|video_|frame[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|frame[0]~12_combout ), @@ -58341,7 +57981,7 @@ defparam \ula_|video_|frame[0] .is_wysiwyg = "true"; defparam \ula_|video_|frame[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X35_Y33_N24 +// Location: LCCOMB_X35_Y32_N14 cycloneive_lcell_comb \ula_|video_|frame[1]~4 ( // Equation(s): // \ula_|video_|frame[1]~4_combout = (\ula_|video_|frame [0] & (\ula_|video_|frame [1] $ (VCC))) # (!\ula_|video_|frame [0] & (\ula_|video_|frame [1] & VCC)) @@ -58359,7 +57999,7 @@ defparam \ula_|video_|frame[1]~4 .lut_mask = 16'h6688; defparam \ula_|video_|frame[1]~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X35_Y33_N25 +// Location: FF_X35_Y32_N15 dffeas \ula_|video_|frame[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|frame[1]~4_combout ), @@ -58378,25 +58018,25 @@ defparam \ula_|video_|frame[1] .is_wysiwyg = "true"; defparam \ula_|video_|frame[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X35_Y33_N26 +// Location: LCCOMB_X35_Y32_N16 cycloneive_lcell_comb \ula_|video_|frame[2]~6 ( // Equation(s): // \ula_|video_|frame[2]~6_combout = (\ula_|video_|frame [2] & (!\ula_|video_|frame[1]~5 )) # (!\ula_|video_|frame [2] & ((\ula_|video_|frame[1]~5 ) # (GND))) // \ula_|video_|frame[2]~7 = CARRY((!\ula_|video_|frame[1]~5 ) # (!\ula_|video_|frame [2])) - .dataa(\ula_|video_|frame [2]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|video_|frame [2]), .datac(gnd), .datad(vcc), .cin(\ula_|video_|frame[1]~5 ), .combout(\ula_|video_|frame[2]~6_combout ), .cout(\ula_|video_|frame[2]~7 )); // synopsys translate_off -defparam \ula_|video_|frame[2]~6 .lut_mask = 16'h5A5F; +defparam \ula_|video_|frame[2]~6 .lut_mask = 16'h3C3F; defparam \ula_|video_|frame[2]~6 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X35_Y33_N27 +// Location: FF_X35_Y32_N17 dffeas \ula_|video_|frame[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|frame[2]~6_combout ), @@ -58415,7 +58055,7 @@ defparam \ula_|video_|frame[2] .is_wysiwyg = "true"; defparam \ula_|video_|frame[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X35_Y33_N28 +// Location: LCCOMB_X35_Y32_N18 cycloneive_lcell_comb \ula_|video_|frame[3]~8 ( // Equation(s): // \ula_|video_|frame[3]~8_combout = (\ula_|video_|frame [3] & (\ula_|video_|frame[2]~7 $ (GND))) # (!\ula_|video_|frame [3] & (!\ula_|video_|frame[2]~7 & VCC)) @@ -58433,7 +58073,7 @@ defparam \ula_|video_|frame[3]~8 .lut_mask = 16'hC30C; defparam \ula_|video_|frame[3]~8 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X35_Y33_N29 +// Location: FF_X35_Y32_N19 dffeas \ula_|video_|frame[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|frame[3]~8_combout ), @@ -58452,27 +58092,44 @@ defparam \ula_|video_|frame[3] .is_wysiwyg = "true"; defparam \ula_|video_|frame[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X35_Y33_N30 +// Location: LCCOMB_X35_Y32_N20 cycloneive_lcell_comb \ula_|video_|frame[4]~10 ( // Equation(s): -// \ula_|video_|frame[4]~10_combout = \ula_|video_|frame [4] $ (\ula_|video_|frame[3]~9 ) +// \ula_|video_|frame[4]~10_combout = \ula_|video_|frame[3]~9 $ (\ula_|video_|frame [4]) - .dataa(\ula_|video_|frame [4]), + .dataa(gnd), .datab(gnd), .datac(gnd), - .datad(gnd), + .datad(\ula_|video_|frame [4]), .cin(\ula_|video_|frame[3]~9 ), .combout(\ula_|video_|frame[4]~10_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|frame[4]~10 .lut_mask = 16'h5A5A; +defparam \ula_|video_|frame[4]~10 .lut_mask = 16'h0FF0; defparam \ula_|video_|frame[4]~10 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X35_Y33_N31 +// Location: LCCOMB_X37_Y32_N0 +cycloneive_lcell_comb \ula_|video_|frame[4]~feeder ( +// Equation(s): +// \ula_|video_|frame[4]~feeder_combout = \ula_|video_|frame[4]~10_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|frame[4]~10_combout ), + .cin(gnd), + .combout(\ula_|video_|frame[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|frame[4]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|frame[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y32_N1 dffeas \ula_|video_|frame[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|frame[4]~10_combout ), + .d(\ula_|video_|frame[4]~feeder_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -58488,7 +58145,7 @@ defparam \ula_|video_|frame[4] .is_wysiwyg = "true"; defparam \ula_|video_|frame[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N4 +// Location: LCCOMB_X37_Y32_N22 cycloneive_lcell_comb \ula_|video_|inverted ( // Equation(s): // \ula_|video_|inverted~combout = (\ula_|video_|attr [7] & \ula_|video_|frame [4]) @@ -58505,41 +58162,41 @@ defparam \ula_|video_|inverted .lut_mask = 16'hF000; defparam \ula_|video_|inverted .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N12 +// Location: LCCOMB_X38_Y32_N4 cycloneive_lcell_comb \ula_|video_|bits_prefetch[6]~feeder ( // Equation(s): // \ula_|video_|bits_prefetch[6]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 ), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 ), + .datad(gnd), .cin(gnd), .combout(\ula_|video_|bits_prefetch[6]~feeder_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|bits_prefetch[6]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|bits_prefetch[6]~feeder .lut_mask = 16'hF0F0; defparam \ula_|video_|bits_prefetch[6]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y31_N8 +// Location: LCCOMB_X35_Y31_N10 cycloneive_lcell_comb \ula_|video_|Decoder0~2 ( // Equation(s): -// \ula_|video_|Decoder0~2_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [1] & !\ula_|video_|vga_hc [0]))) +// \ula_|video_|Decoder0~2_combout = (!\ula_|video_|vga_hc [1] & (\ula_|video_|vga_hc [3] & (\ula_|video_|vga_hc [2] & !\ula_|video_|vga_hc [0]))) - .dataa(\ula_|video_|vga_hc [2]), + .dataa(\ula_|video_|vga_hc [1]), .datab(\ula_|video_|vga_hc [3]), - .datac(\ula_|video_|vga_hc [1]), + .datac(\ula_|video_|vga_hc [2]), .datad(\ula_|video_|vga_hc [0]), .cin(gnd), .combout(\ula_|video_|Decoder0~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Decoder0~2 .lut_mask = 16'h0008; +defparam \ula_|video_|Decoder0~2 .lut_mask = 16'h0040; defparam \ula_|video_|Decoder0~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N13 +// Location: FF_X38_Y32_N5 dffeas \ula_|video_|bits_prefetch[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits_prefetch[6]~feeder_combout ), @@ -58558,32 +58215,15 @@ defparam \ula_|video_|bits_prefetch[6] .is_wysiwyg = "true"; defparam \ula_|video_|bits_prefetch[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N6 -cycloneive_lcell_comb \ula_|video_|bits[6]~feeder ( -// Equation(s): -// \ula_|video_|bits[6]~feeder_combout = \ula_|video_|bits_prefetch [6] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|bits_prefetch [6]), - .cin(gnd), - .combout(\ula_|video_|bits[6]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|bits[6]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|bits[6]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y33_N7 +// Location: FF_X37_Y32_N27 dffeas \ula_|video_|bits[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|bits[6]~feeder_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\ula_|video_|bits_prefetch [6]), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), + .sload(vcc), .ena(\ula_|video_|Decoder0~0_combout ), .devclrn(devclrn), .devpor(devpor), @@ -58594,7 +58234,7 @@ defparam \ula_|video_|bits[6] .is_wysiwyg = "true"; defparam \ula_|video_|bits[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N22 +// Location: LCCOMB_X38_Y32_N10 cycloneive_lcell_comb \ula_|video_|bits_prefetch[4]~feeder ( // Equation(s): // \ula_|video_|bits_prefetch[4]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 @@ -58611,7 +58251,7 @@ defparam \ula_|video_|bits_prefetch[4]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits_prefetch[4]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N23 +// Location: FF_X38_Y32_N11 dffeas \ula_|video_|bits_prefetch[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits_prefetch[4]~feeder_combout ), @@ -58630,7 +58270,7 @@ defparam \ula_|video_|bits_prefetch[4] .is_wysiwyg = "true"; defparam \ula_|video_|bits_prefetch[4] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y33_N23 +// Location: FF_X37_Y32_N9 dffeas \ula_|video_|bits[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -58649,7 +58289,7 @@ defparam \ula_|video_|bits[4] .is_wysiwyg = "true"; defparam \ula_|video_|bits[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N18 +// Location: LCCOMB_X38_Y32_N26 cycloneive_lcell_comb \ula_|video_|bits_prefetch[5]~feeder ( // Equation(s): // \ula_|video_|bits_prefetch[5]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 @@ -58666,7 +58306,7 @@ defparam \ula_|video_|bits_prefetch[5]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits_prefetch[5]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N19 +// Location: FF_X38_Y32_N27 dffeas \ula_|video_|bits_prefetch[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits_prefetch[5]~feeder_combout ), @@ -58685,7 +58325,7 @@ defparam \ula_|video_|bits_prefetch[5] .is_wysiwyg = "true"; defparam \ula_|video_|bits_prefetch[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N18 +// Location: LCCOMB_X37_Y32_N12 cycloneive_lcell_comb \ula_|video_|bits[5]~feeder ( // Equation(s): // \ula_|video_|bits[5]~feeder_combout = \ula_|video_|bits_prefetch [5] @@ -58702,7 +58342,7 @@ defparam \ula_|video_|bits[5]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits[5]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X36_Y33_N19 +// Location: FF_X37_Y32_N13 dffeas \ula_|video_|bits[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits[5]~feeder_combout ), @@ -58721,7 +58361,7 @@ defparam \ula_|video_|bits[5] .is_wysiwyg = "true"; defparam \ula_|video_|bits[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N0 +// Location: LCCOMB_X38_Y32_N12 cycloneive_lcell_comb \ula_|video_|bits_prefetch[7]~feeder ( // Equation(s): // \ula_|video_|bits_prefetch[7]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 @@ -58738,7 +58378,7 @@ defparam \ula_|video_|bits_prefetch[7]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits_prefetch[7]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N1 +// Location: FF_X38_Y32_N13 dffeas \ula_|video_|bits_prefetch[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits_prefetch[7]~feeder_combout ), @@ -58757,7 +58397,7 @@ defparam \ula_|video_|bits_prefetch[7] .is_wysiwyg = "true"; defparam \ula_|video_|bits_prefetch[7] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y33_N1 +// Location: FF_X37_Y32_N19 dffeas \ula_|video_|bits[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -58776,41 +58416,41 @@ defparam \ula_|video_|bits[7] .is_wysiwyg = "true"; defparam \ula_|video_|bits[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N0 +// Location: LCCOMB_X37_Y32_N18 cycloneive_lcell_comb \ula_|video_|Mux0~0 ( // Equation(s): -// \ula_|video_|Mux0~0_combout = (\ula_|video_|vga_hc [1] & (((\ula_|video_|vga_hc [2])))) # (!\ula_|video_|vga_hc [1] & ((\ula_|video_|vga_hc [2] & (\ula_|video_|bits [5])) # (!\ula_|video_|vga_hc [2] & ((\ula_|video_|bits [7]))))) +// \ula_|video_|Mux0~0_combout = (\ula_|video_|vga_hc [2] & ((\ula_|video_|bits [5]) # ((\ula_|video_|vga_hc [1])))) # (!\ula_|video_|vga_hc [2] & (((\ula_|video_|bits [7] & !\ula_|video_|vga_hc [1])))) .dataa(\ula_|video_|bits [5]), - .datab(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|vga_hc [2]), .datac(\ula_|video_|bits [7]), - .datad(\ula_|video_|vga_hc [2]), + .datad(\ula_|video_|vga_hc [1]), .cin(gnd), .combout(\ula_|video_|Mux0~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Mux0~0 .lut_mask = 16'hEE30; +defparam \ula_|video_|Mux0~0 .lut_mask = 16'hCCB8; defparam \ula_|video_|Mux0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N22 +// Location: LCCOMB_X37_Y32_N8 cycloneive_lcell_comb \ula_|video_|Mux0~1 ( // Equation(s): // \ula_|video_|Mux0~1_combout = (\ula_|video_|vga_hc [1] & ((\ula_|video_|Mux0~0_combout & ((\ula_|video_|bits [4]))) # (!\ula_|video_|Mux0~0_combout & (\ula_|video_|bits [6])))) # (!\ula_|video_|vga_hc [1] & (((\ula_|video_|Mux0~0_combout )))) - .dataa(\ula_|video_|bits [6]), - .datab(\ula_|video_|vga_hc [1]), + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|bits [6]), .datac(\ula_|video_|bits [4]), .datad(\ula_|video_|Mux0~0_combout ), .cin(gnd), .combout(\ula_|video_|Mux0~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Mux0~1 .lut_mask = 16'hF388; +defparam \ula_|video_|Mux0~1 .lut_mask = 16'hF588; defparam \ula_|video_|Mux0~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N16 +// Location: LCCOMB_X38_Y32_N16 cycloneive_lcell_comb \ula_|video_|bits_prefetch[2]~feeder ( // Equation(s): // \ula_|video_|bits_prefetch[2]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 @@ -58827,7 +58467,7 @@ defparam \ula_|video_|bits_prefetch[2]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits_prefetch[2]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N17 +// Location: FF_X38_Y32_N17 dffeas \ula_|video_|bits_prefetch[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits_prefetch[2]~feeder_combout ), @@ -58846,7 +58486,7 @@ defparam \ula_|video_|bits_prefetch[2] .is_wysiwyg = "true"; defparam \ula_|video_|bits_prefetch[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N12 +// Location: LCCOMB_X37_Y32_N30 cycloneive_lcell_comb \ula_|video_|bits[2]~feeder ( // Equation(s): // \ula_|video_|bits[2]~feeder_combout = \ula_|video_|bits_prefetch [2] @@ -58863,7 +58503,7 @@ defparam \ula_|video_|bits[2]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits[2]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X36_Y33_N13 +// Location: FF_X37_Y32_N31 dffeas \ula_|video_|bits[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits[2]~feeder_combout ), @@ -58882,7 +58522,7 @@ defparam \ula_|video_|bits[2] .is_wysiwyg = "true"; defparam \ula_|video_|bits[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N14 +// Location: LCCOMB_X38_Y32_N6 cycloneive_lcell_comb \ula_|video_|bits_prefetch[0]~feeder ( // Equation(s): // \ula_|video_|bits_prefetch[0]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 @@ -58899,7 +58539,7 @@ defparam \ula_|video_|bits_prefetch[0]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits_prefetch[0]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N15 +// Location: FF_X38_Y32_N7 dffeas \ula_|video_|bits_prefetch[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits_prefetch[0]~feeder_combout ), @@ -58918,7 +58558,7 @@ defparam \ula_|video_|bits_prefetch[0] .is_wysiwyg = "true"; defparam \ula_|video_|bits_prefetch[0] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y33_N3 +// Location: FF_X37_Y32_N25 dffeas \ula_|video_|bits[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -58937,7 +58577,7 @@ defparam \ula_|video_|bits[0] .is_wysiwyg = "true"; defparam \ula_|video_|bits[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N6 +// Location: LCCOMB_X38_Y32_N2 cycloneive_lcell_comb \ula_|video_|bits_prefetch[1]~feeder ( // Equation(s): // \ula_|video_|bits_prefetch[1]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 @@ -58954,7 +58594,7 @@ defparam \ula_|video_|bits_prefetch[1]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits_prefetch[1]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N7 +// Location: FF_X38_Y32_N3 dffeas \ula_|video_|bits_prefetch[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits_prefetch[1]~feeder_combout ), @@ -58973,7 +58613,7 @@ defparam \ula_|video_|bits_prefetch[1] .is_wysiwyg = "true"; defparam \ula_|video_|bits_prefetch[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N26 +// Location: LCCOMB_X37_Y32_N28 cycloneive_lcell_comb \ula_|video_|bits[1]~feeder ( // Equation(s): // \ula_|video_|bits[1]~feeder_combout = \ula_|video_|bits_prefetch [1] @@ -58990,7 +58630,7 @@ defparam \ula_|video_|bits[1]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits[1]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X36_Y33_N27 +// Location: FF_X37_Y32_N29 dffeas \ula_|video_|bits[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits[1]~feeder_combout ), @@ -59009,7 +58649,7 @@ defparam \ula_|video_|bits[1] .is_wysiwyg = "true"; defparam \ula_|video_|bits[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N4 +// Location: LCCOMB_X38_Y32_N20 cycloneive_lcell_comb \ula_|video_|bits_prefetch[3]~feeder ( // Equation(s): // \ula_|video_|bits_prefetch[3]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 @@ -59026,7 +58666,7 @@ defparam \ula_|video_|bits_prefetch[3]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits_prefetch[3]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N5 +// Location: FF_X38_Y32_N21 dffeas \ula_|video_|bits_prefetch[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits_prefetch[3]~feeder_combout ), @@ -59045,7 +58685,7 @@ defparam \ula_|video_|bits_prefetch[3] .is_wysiwyg = "true"; defparam \ula_|video_|bits_prefetch[3] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y33_N25 +// Location: FF_X37_Y32_N7 dffeas \ula_|video_|bits[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -59064,109 +58704,219 @@ defparam \ula_|video_|bits[3] .is_wysiwyg = "true"; defparam \ula_|video_|bits[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N24 +// Location: LCCOMB_X37_Y32_N6 cycloneive_lcell_comb \ula_|video_|Mux0~2 ( // Equation(s): // \ula_|video_|Mux0~2_combout = (\ula_|video_|vga_hc [1] & (((\ula_|video_|vga_hc [2])))) # (!\ula_|video_|vga_hc [1] & ((\ula_|video_|vga_hc [2] & (\ula_|video_|bits [1])) # (!\ula_|video_|vga_hc [2] & ((\ula_|video_|bits [3]))))) - .dataa(\ula_|video_|bits [1]), - .datab(\ula_|video_|vga_hc [1]), + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|bits [1]), .datac(\ula_|video_|bits [3]), .datad(\ula_|video_|vga_hc [2]), .cin(gnd), .combout(\ula_|video_|Mux0~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Mux0~2 .lut_mask = 16'hEE30; +defparam \ula_|video_|Mux0~2 .lut_mask = 16'hEE50; defparam \ula_|video_|Mux0~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N2 +// Location: LCCOMB_X37_Y32_N24 cycloneive_lcell_comb \ula_|video_|Mux0~3 ( // Equation(s): // \ula_|video_|Mux0~3_combout = (\ula_|video_|vga_hc [1] & ((\ula_|video_|Mux0~2_combout & ((\ula_|video_|bits [0]))) # (!\ula_|video_|Mux0~2_combout & (\ula_|video_|bits [2])))) # (!\ula_|video_|vga_hc [1] & (((\ula_|video_|Mux0~2_combout )))) - .dataa(\ula_|video_|bits [2]), - .datab(\ula_|video_|vga_hc [1]), + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|bits [2]), .datac(\ula_|video_|bits [0]), .datad(\ula_|video_|Mux0~2_combout ), .cin(gnd), .combout(\ula_|video_|Mux0~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Mux0~3 .lut_mask = 16'hF388; +defparam \ula_|video_|Mux0~3 .lut_mask = 16'hF588; defparam \ula_|video_|Mux0~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N10 +// Location: LCCOMB_X37_Y32_N20 cycloneive_lcell_comb \ula_|video_|cindex[1]~0 ( // Equation(s): // \ula_|video_|cindex[1]~0_combout = \ula_|video_|inverted~combout $ (((\ula_|video_|vga_hc [3] & ((\ula_|video_|Mux0~3_combout ))) # (!\ula_|video_|vga_hc [3] & (\ula_|video_|Mux0~1_combout )))) - .dataa(\ula_|video_|vga_hc [3]), - .datab(\ula_|video_|inverted~combout ), + .dataa(\ula_|video_|inverted~combout ), + .datab(\ula_|video_|vga_hc [3]), .datac(\ula_|video_|Mux0~1_combout ), .datad(\ula_|video_|Mux0~3_combout ), .cin(gnd), .combout(\ula_|video_|cindex[1]~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|cindex[1]~0 .lut_mask = 16'h369C; +defparam \ula_|video_|cindex[1]~0 .lut_mask = 16'h569A; defparam \ula_|video_|cindex[1]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y33_N12 +// Location: LCCOMB_X38_Y32_N14 +cycloneive_lcell_comb \ula_|video_|attr_prefetch[4]~feeder ( +// Equation(s): +// \ula_|video_|attr_prefetch[4]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ula_|video_|attr_prefetch[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|attr_prefetch[4]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|attr_prefetch[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X38_Y32_N15 +dffeas \ula_|video_|attr_prefetch[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|attr_prefetch[4]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|Decoder0~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|attr_prefetch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|attr_prefetch[4] .is_wysiwyg = "true"; +defparam \ula_|video_|attr_prefetch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X36_Y32_N17 +dffeas \ula_|video_|attr[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|attr_prefetch [4]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|attr [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|attr[4] .is_wysiwyg = "true"; +defparam \ula_|video_|attr[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y32_N28 +cycloneive_lcell_comb \ula_|video_|attr_prefetch[1]~feeder ( +// Equation(s): +// \ula_|video_|attr_prefetch[1]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ula_|video_|attr_prefetch[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|attr_prefetch[1]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|attr_prefetch[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X38_Y32_N29 +dffeas \ula_|video_|attr_prefetch[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|attr_prefetch[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|Decoder0~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|attr_prefetch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|attr_prefetch[1] .is_wysiwyg = "true"; +defparam \ula_|video_|attr_prefetch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X36_Y32_N7 +dffeas \ula_|video_|attr[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|attr_prefetch [1]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|attr [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|attr[1] .is_wysiwyg = "true"; +defparam \ula_|video_|attr[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y32_N16 cycloneive_lcell_comb \ula_|video_|cindex[1]~1 ( // Equation(s): -// \ula_|video_|cindex[1]~1_combout = (\ula_|video_|cindex[1]~0_combout & (\ula_|video_|attr [1])) # (!\ula_|video_|cindex[1]~0_combout & ((\ula_|video_|attr [4]))) +// \ula_|video_|cindex[1]~1_combout = (\ula_|video_|cindex[1]~0_combout & ((\ula_|video_|attr [1]))) # (!\ula_|video_|cindex[1]~0_combout & (\ula_|video_|attr [4])) - .dataa(\ula_|video_|attr [1]), + .dataa(\ula_|video_|cindex[1]~0_combout ), .datab(gnd), .datac(\ula_|video_|attr [4]), - .datad(\ula_|video_|cindex[1]~0_combout ), + .datad(\ula_|video_|attr [1]), .cin(gnd), .combout(\ula_|video_|cindex[1]~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|cindex[1]~1 .lut_mask = 16'hAAF0; +defparam \ula_|video_|cindex[1]~1 .lut_mask = 16'hFA50; defparam \ula_|video_|cindex[1]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y33_N24 +// Location: LCCOMB_X36_Y32_N26 cycloneive_lcell_comb \ula_|video_|VGA_R[0]~0 ( // Equation(s): // \ula_|video_|VGA_R[0]~0_combout = (\ula_|video_|disp_enable~1_combout & ((\ula_|video_|screen_en~1_combout & ((\ula_|video_|cindex[1]~1_combout ))) # (!\ula_|video_|screen_en~1_combout & (\ula_|border [1])))) - .dataa(\ula_|video_|disp_enable~1_combout ), - .datab(\ula_|border [1]), - .datac(\ula_|video_|screen_en~1_combout ), + .dataa(\ula_|border [1]), + .datab(\ula_|video_|screen_en~1_combout ), + .datac(\ula_|video_|disp_enable~1_combout ), .datad(\ula_|video_|cindex[1]~1_combout ), .cin(gnd), .combout(\ula_|video_|VGA_R[0]~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|VGA_R[0]~0 .lut_mask = 16'hA808; +defparam \ula_|video_|VGA_R[0]~0 .lut_mask = 16'hE020; defparam \ula_|video_|VGA_R[0]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N26 +// Location: LCCOMB_X38_Y32_N18 cycloneive_lcell_comb \ula_|video_|attr_prefetch[6]~feeder ( // Equation(s): // \ula_|video_|attr_prefetch[6]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 ), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 ), + .datad(gnd), .cin(gnd), .combout(\ula_|video_|attr_prefetch[6]~feeder_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|attr_prefetch[6]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|attr_prefetch[6]~feeder .lut_mask = 16'hF0F0; defparam \ula_|video_|attr_prefetch[6]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N27 +// Location: FF_X38_Y32_N19 dffeas \ula_|video_|attr_prefetch[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr_prefetch[6]~feeder_combout ), @@ -59185,7 +58935,7 @@ defparam \ula_|video_|attr_prefetch[6] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[6] .power_up = "low"; // synopsys translate_on -// Location: FF_X38_Y33_N1 +// Location: FF_X36_Y32_N9 dffeas \ula_|video_|attr[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -59204,7 +58954,7 @@ defparam \ula_|video_|attr[6] .is_wysiwyg = "true"; defparam \ula_|video_|attr[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X38_Y33_N0 +// Location: LCCOMB_X36_Y32_N8 cycloneive_lcell_comb \ula_|video_|VGA_B[1]~0 ( // Equation(s): // \ula_|video_|VGA_B[1]~0_combout = (!\ula_|video_|LessThan2~1_combout & (\ula_|video_|LessThan3~0_combout & (\ula_|video_|attr [6] & \ula_|video_|disp_enable~0_combout ))) @@ -59221,28 +58971,28 @@ defparam \ula_|video_|VGA_B[1]~0 .lut_mask = 16'h4000; defparam \ula_|video_|VGA_B[1]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y33_N2 +// Location: LCCOMB_X36_Y32_N30 cycloneive_lcell_comb \ula_|video_|VGA_R[1]~1 ( // Equation(s): // \ula_|video_|VGA_R[1]~1_combout = (\ula_|video_|screen_en~1_combout & (\ula_|video_|VGA_B[1]~0_combout & \ula_|video_|cindex[1]~1_combout )) .dataa(\ula_|video_|screen_en~1_combout ), - .datab(gnd), - .datac(\ula_|video_|VGA_B[1]~0_combout ), + .datab(\ula_|video_|VGA_B[1]~0_combout ), + .datac(gnd), .datad(\ula_|video_|cindex[1]~1_combout ), .cin(gnd), .combout(\ula_|video_|VGA_R[1]~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|VGA_R[1]~1 .lut_mask = 16'hA000; +defparam \ula_|video_|VGA_R[1]~1 .lut_mask = 16'h8800; defparam \ula_|video_|VGA_R[1]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y12_N17 +// Location: FF_X31_Y10_N27 dffeas \ula_|border[2] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), - .asdata(\D[2]~46_combout ), + .asdata(\D[2]~39_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), @@ -59257,62 +59007,7 @@ defparam \ula_|border[2] .is_wysiwyg = "true"; defparam \ula_|border[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N8 -cycloneive_lcell_comb \ula_|video_|attr_prefetch[2]~feeder ( -// Equation(s): -// \ula_|video_|attr_prefetch[2]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|attr_prefetch[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|attr_prefetch[2]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|attr_prefetch[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y33_N9 -dffeas \ula_|video_|attr_prefetch[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|attr_prefetch[2]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|attr_prefetch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|attr_prefetch[2] .is_wysiwyg = "true"; -defparam \ula_|video_|attr_prefetch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X36_Y33_N21 -dffeas \ula_|video_|attr[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|attr_prefetch [2]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|Decoder0~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|attr [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|attr[2] .is_wysiwyg = "true"; -defparam \ula_|video_|attr[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y33_N30 +// Location: LCCOMB_X38_Y32_N22 cycloneive_lcell_comb \ula_|video_|attr_prefetch[5]~feeder ( // Equation(s): // \ula_|video_|attr_prefetch[5]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 @@ -59329,7 +59024,7 @@ defparam \ula_|video_|attr_prefetch[5]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|attr_prefetch[5]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N31 +// Location: FF_X38_Y32_N23 dffeas \ula_|video_|attr_prefetch[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr_prefetch[5]~feeder_combout ), @@ -59348,7 +59043,7 @@ defparam \ula_|video_|attr_prefetch[5] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[5] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y33_N15 +// Location: FF_X36_Y32_N21 dffeas \ula_|video_|attr[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -59367,24 +59062,79 @@ defparam \ula_|video_|attr[5] .is_wysiwyg = "true"; defparam \ula_|video_|attr[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N14 -cycloneive_lcell_comb \ula_|video_|cindex[2]~2 ( +// Location: LCCOMB_X38_Y32_N0 +cycloneive_lcell_comb \ula_|video_|attr_prefetch[2]~feeder ( // Equation(s): -// \ula_|video_|cindex[2]~2_combout = (\ula_|video_|cindex[1]~0_combout & (\ula_|video_|attr [2])) # (!\ula_|video_|cindex[1]~0_combout & ((\ula_|video_|attr [5]))) +// \ula_|video_|attr_prefetch[2]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 .dataa(gnd), - .datab(\ula_|video_|attr [2]), + .datab(gnd), + .datac(gnd), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ula_|video_|attr_prefetch[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|attr_prefetch[2]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|attr_prefetch[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X38_Y32_N1 +dffeas \ula_|video_|attr_prefetch[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|attr_prefetch[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|Decoder0~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|attr_prefetch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|attr_prefetch[2] .is_wysiwyg = "true"; +defparam \ula_|video_|attr_prefetch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X36_Y32_N19 +dffeas \ula_|video_|attr[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|attr_prefetch [2]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|attr [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|attr[2] .is_wysiwyg = "true"; +defparam \ula_|video_|attr[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y32_N20 +cycloneive_lcell_comb \ula_|video_|cindex[2]~2 ( +// Equation(s): +// \ula_|video_|cindex[2]~2_combout = (\ula_|video_|cindex[1]~0_combout & ((\ula_|video_|attr [2]))) # (!\ula_|video_|cindex[1]~0_combout & (\ula_|video_|attr [5])) + + .dataa(\ula_|video_|cindex[1]~0_combout ), + .datab(gnd), .datac(\ula_|video_|attr [5]), - .datad(\ula_|video_|cindex[1]~0_combout ), + .datad(\ula_|video_|attr [2]), .cin(gnd), .combout(\ula_|video_|cindex[2]~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|cindex[2]~2 .lut_mask = 16'hCCF0; +defparam \ula_|video_|cindex[2]~2 .lut_mask = 16'hFA50; defparam \ula_|video_|cindex[2]~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y33_N26 +// Location: LCCOMB_X36_Y32_N22 cycloneive_lcell_comb \ula_|video_|VGA_G[0]~0 ( // Equation(s): // \ula_|video_|VGA_G[0]~0_combout = (\ula_|video_|disp_enable~1_combout & ((\ula_|video_|screen_en~1_combout & ((\ula_|video_|cindex[2]~2_combout ))) # (!\ula_|video_|screen_en~1_combout & (\ula_|border [2])))) @@ -59401,15 +59151,15 @@ defparam \ula_|video_|VGA_G[0]~0 .lut_mask = 16'hE020; defparam \ula_|video_|VGA_G[0]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N20 +// Location: LCCOMB_X36_Y32_N18 cycloneive_lcell_comb \ula_|video_|VGA_G[1]~1 ( // Equation(s): -// \ula_|video_|VGA_G[1]~1_combout = (\ula_|video_|VGA_B[1]~0_combout & (\ula_|video_|cindex[2]~2_combout & \ula_|video_|screen_en~1_combout )) +// \ula_|video_|VGA_G[1]~1_combout = (\ula_|video_|VGA_B[1]~0_combout & (\ula_|video_|screen_en~1_combout & \ula_|video_|cindex[2]~2_combout )) .dataa(\ula_|video_|VGA_B[1]~0_combout ), - .datab(\ula_|video_|cindex[2]~2_combout ), + .datab(\ula_|video_|screen_en~1_combout ), .datac(gnd), - .datad(\ula_|video_|screen_en~1_combout ), + .datad(\ula_|video_|cindex[2]~2_combout ), .cin(gnd), .combout(\ula_|video_|VGA_G[1]~1_combout ), .cout()); @@ -59418,11 +59168,11 @@ defparam \ula_|video_|VGA_G[1]~1 .lut_mask = 16'h8800; defparam \ula_|video_|VGA_G[1]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y22_N1 +// Location: FF_X23_Y14_N19 dffeas \ula_|border[0] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), - .asdata(\D[0]~58_combout ), + .asdata(\D[0]~46_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), @@ -59437,7 +59187,7 @@ defparam \ula_|border[0] .is_wysiwyg = "true"; defparam \ula_|border[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N20 +// Location: LCCOMB_X38_Y32_N24 cycloneive_lcell_comb \ula_|video_|attr_prefetch[0]~feeder ( // Equation(s): // \ula_|video_|attr_prefetch[0]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 @@ -59454,7 +59204,7 @@ defparam \ula_|video_|attr_prefetch[0]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|attr_prefetch[0]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N21 +// Location: FF_X38_Y32_N25 dffeas \ula_|video_|attr_prefetch[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr_prefetch[0]~feeder_combout ), @@ -59473,7 +59223,7 @@ defparam \ula_|video_|attr_prefetch[0] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X37_Y33_N28 +// Location: LCCOMB_X37_Y32_N10 cycloneive_lcell_comb \ula_|video_|attr[0]~feeder ( // Equation(s): // \ula_|video_|attr[0]~feeder_combout = \ula_|video_|attr_prefetch [0] @@ -59490,7 +59240,7 @@ defparam \ula_|video_|attr[0]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|attr[0]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X37_Y33_N29 +// Location: FF_X37_Y32_N11 dffeas \ula_|video_|attr[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr[0]~feeder_combout ), @@ -59509,7 +59259,7 @@ defparam \ula_|video_|attr[0] .is_wysiwyg = "true"; defparam \ula_|video_|attr[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N2 +// Location: LCCOMB_X38_Y32_N30 cycloneive_lcell_comb \ula_|video_|attr_prefetch[3]~feeder ( // Equation(s): // \ula_|video_|attr_prefetch[3]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 @@ -59526,7 +59276,7 @@ defparam \ula_|video_|attr_prefetch[3]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|attr_prefetch[3]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N3 +// Location: FF_X38_Y32_N31 dffeas \ula_|video_|attr_prefetch[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr_prefetch[3]~feeder_combout ), @@ -59545,7 +59295,7 @@ defparam \ula_|video_|attr_prefetch[3] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[3] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y33_N29 +// Location: FF_X37_Y32_N17 dffeas \ula_|video_|attr[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -59564,48 +59314,48 @@ defparam \ula_|video_|attr[3] .is_wysiwyg = "true"; defparam \ula_|video_|attr[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N28 +// Location: LCCOMB_X37_Y32_N16 cycloneive_lcell_comb \ula_|video_|cindex[0]~3 ( // Equation(s): // \ula_|video_|cindex[0]~3_combout = (\ula_|video_|cindex[1]~0_combout & (\ula_|video_|attr [0])) # (!\ula_|video_|cindex[1]~0_combout & ((\ula_|video_|attr [3]))) - .dataa(gnd), - .datab(\ula_|video_|attr [0]), + .dataa(\ula_|video_|attr [0]), + .datab(gnd), .datac(\ula_|video_|attr [3]), .datad(\ula_|video_|cindex[1]~0_combout ), .cin(gnd), .combout(\ula_|video_|cindex[0]~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|cindex[0]~3 .lut_mask = 16'hCCF0; +defparam \ula_|video_|cindex[0]~3 .lut_mask = 16'hAAF0; defparam \ula_|video_|cindex[0]~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y33_N30 +// Location: LCCOMB_X37_Y32_N14 cycloneive_lcell_comb \ula_|video_|VGA_B[0]~1 ( // Equation(s): // \ula_|video_|VGA_B[0]~1_combout = (\ula_|video_|disp_enable~1_combout & ((\ula_|video_|screen_en~1_combout & ((\ula_|video_|cindex[0]~3_combout ))) # (!\ula_|video_|screen_en~1_combout & (\ula_|border [0])))) - .dataa(\ula_|video_|disp_enable~1_combout ), + .dataa(\ula_|video_|screen_en~1_combout ), .datab(\ula_|border [0]), - .datac(\ula_|video_|screen_en~1_combout ), + .datac(\ula_|video_|disp_enable~1_combout ), .datad(\ula_|video_|cindex[0]~3_combout ), .cin(gnd), .combout(\ula_|video_|VGA_B[0]~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|VGA_B[0]~1 .lut_mask = 16'hA808; +defparam \ula_|video_|VGA_B[0]~1 .lut_mask = 16'hE040; defparam \ula_|video_|VGA_B[0]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y33_N0 +// Location: LCCOMB_X37_Y32_N4 cycloneive_lcell_comb \ula_|video_|VGA_B[1]~2 ( // Equation(s): -// \ula_|video_|VGA_B[1]~2_combout = (\ula_|video_|screen_en~1_combout & (\ula_|video_|VGA_B[1]~0_combout & \ula_|video_|cindex[0]~3_combout )) +// \ula_|video_|VGA_B[1]~2_combout = (\ula_|video_|VGA_B[1]~0_combout & (\ula_|video_|screen_en~1_combout & \ula_|video_|cindex[0]~3_combout )) - .dataa(\ula_|video_|screen_en~1_combout ), + .dataa(\ula_|video_|VGA_B[1]~0_combout ), .datab(gnd), - .datac(\ula_|video_|VGA_B[1]~0_combout ), + .datac(\ula_|video_|screen_en~1_combout ), .datad(\ula_|video_|cindex[0]~3_combout ), .cin(gnd), .combout(\ula_|video_|VGA_B[1]~2_combout ), @@ -59615,24 +59365,24 @@ defparam \ula_|video_|VGA_B[1]~2 .lut_mask = 16'hA000; defparam \ula_|video_|VGA_B[1]~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y33_N26 +// Location: LCCOMB_X35_Y31_N22 cycloneive_lcell_comb \ula_|video_|Equal0~2 ( // Equation(s): -// \ula_|video_|Equal0~2_combout = (\ula_|video_|vga_hc [6] & (!\ula_|video_|vga_hc [9] & !\ula_|video_|vga_hc [8])) +// \ula_|video_|Equal0~2_combout = (!\ula_|video_|vga_hc [8] & (\ula_|video_|vga_hc [6] & !\ula_|video_|vga_hc [9])) - .dataa(\ula_|video_|vga_hc [6]), - .datab(\ula_|video_|vga_hc [9]), - .datac(gnd), - .datad(\ula_|video_|vga_hc [8]), + .dataa(gnd), + .datab(\ula_|video_|vga_hc [8]), + .datac(\ula_|video_|vga_hc [6]), + .datad(\ula_|video_|vga_hc [9]), .cin(gnd), .combout(\ula_|video_|Equal0~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Equal0~2 .lut_mask = 16'h0022; +defparam \ula_|video_|Equal0~2 .lut_mask = 16'h0030; defparam \ula_|video_|Equal0~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X37_Y33_N7 +// Location: FF_X35_Y31_N21 dffeas \ula_|video_|VGA_HS~_Duplicate_1 ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|Selector0~0_combout ), @@ -59651,21 +59401,21 @@ defparam \ula_|video_|VGA_HS~_Duplicate_1 .is_wysiwyg = "true"; defparam \ula_|video_|VGA_HS~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X37_Y33_N6 +// Location: LCCOMB_X35_Y31_N20 cycloneive_lcell_comb \ula_|video_|Selector0~0 ( // Equation(s): -// \ula_|video_|Selector0~0_combout = (\ula_|video_|Equal0~2_combout & ((\ula_|video_|Equal0~1_combout ) # ((\ula_|video_|Equal1~0_combout & \ula_|video_|VGA_HS~_Duplicate_1_q )))) # (!\ula_|video_|Equal0~2_combout & (\ula_|video_|Equal1~0_combout & -// (\ula_|video_|VGA_HS~_Duplicate_1_q ))) +// \ula_|video_|Selector0~0_combout = (\ula_|video_|Equal0~2_combout & ((\ula_|video_|Equal0~1_combout ) # ((\ula_|video_|VGA_HS~_Duplicate_1_q & \ula_|video_|Equal1~0_combout )))) # (!\ula_|video_|Equal0~2_combout & (((\ula_|video_|VGA_HS~_Duplicate_1_q +// & \ula_|video_|Equal1~0_combout )))) .dataa(\ula_|video_|Equal0~2_combout ), - .datab(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Equal0~1_combout ), .datac(\ula_|video_|VGA_HS~_Duplicate_1_q ), - .datad(\ula_|video_|Equal0~1_combout ), + .datad(\ula_|video_|Equal1~0_combout ), .cin(gnd), .combout(\ula_|video_|Selector0~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Selector0~0 .lut_mask = 16'hEAC0; +defparam \ula_|video_|Selector0~0 .lut_mask = 16'hF888; defparam \ula_|video_|Selector0~0 .sum_lutc_input = "datac"; // synopsys translate_on @@ -59688,7 +59438,7 @@ defparam \ula_|video_|VGA_HS .is_wysiwyg = "true"; defparam \ula_|video_|VGA_HS .power_up = "low"; // synopsys translate_on -// Location: FF_X34_Y33_N25 +// Location: FF_X35_Y32_N5 dffeas \ula_|video_|VGA_VS~_Duplicate_1 ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|Selector1~0_combout ), @@ -59707,21 +59457,21 @@ defparam \ula_|video_|VGA_VS~_Duplicate_1 .is_wysiwyg = "true"; defparam \ula_|video_|VGA_VS~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y33_N24 +// Location: LCCOMB_X35_Y32_N4 cycloneive_lcell_comb \ula_|video_|Selector1~0 ( // Equation(s): -// \ula_|video_|Selector1~0_combout = (\ula_|video_|Equal3~1_combout & (\ula_|video_|Equal2~2_combout & ((\ula_|video_|vga_vc [1])))) # (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|VGA_VS~_Duplicate_1_q ) # ((\ula_|video_|Equal2~2_combout & -// \ula_|video_|vga_vc [1])))) +// \ula_|video_|Selector1~0_combout = (\ula_|video_|Equal2~2_combout & ((\ula_|video_|vga_vc [1]) # ((\ula_|video_|VGA_VS~_Duplicate_1_q & !\ula_|video_|Equal3~1_combout )))) # (!\ula_|video_|Equal2~2_combout & (((\ula_|video_|VGA_VS~_Duplicate_1_q & +// !\ula_|video_|Equal3~1_combout )))) - .dataa(\ula_|video_|Equal3~1_combout ), - .datab(\ula_|video_|Equal2~2_combout ), + .dataa(\ula_|video_|Equal2~2_combout ), + .datab(\ula_|video_|vga_vc [1]), .datac(\ula_|video_|VGA_VS~_Duplicate_1_q ), - .datad(\ula_|video_|vga_vc [1]), + .datad(\ula_|video_|Equal3~1_combout ), .cin(gnd), .combout(\ula_|video_|Selector1~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Selector1~0 .lut_mask = 16'hDC50; +defparam \ula_|video_|Selector1~0 .lut_mask = 16'h88F8; defparam \ula_|video_|Selector1~0 .sum_lutc_input = "datac"; // synopsys translate_on @@ -59744,7 +59494,7 @@ defparam \ula_|video_|VGA_VS .is_wysiwyg = "true"; defparam \ula_|video_|VGA_VS .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X47_Y17_N4 +// Location: LCCOMB_X27_Y13_N26 cycloneive_lcell_comb \z80_|memory_ifc_|q1~feeder ( // Equation(s): // \z80_|memory_ifc_|q1~feeder_combout = \z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q @@ -59761,7 +59511,7 @@ defparam \z80_|memory_ifc_|q1~feeder .lut_mask = 16'hFF00; defparam \z80_|memory_ifc_|q1~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X47_Y17_N5 +// Location: FF_X27_Y13_N27 dffeas \z80_|memory_ifc_|q1 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|memory_ifc_|q1~feeder_combout ), @@ -59780,7 +59530,7 @@ defparam \z80_|memory_ifc_|q1 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|q1 .power_up = "low"; // synopsys translate_on -// Location: FF_X47_Y17_N25 +// Location: FF_X27_Y13_N17 dffeas \z80_|memory_ifc_|q2 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), @@ -59799,7 +59549,7 @@ defparam \z80_|memory_ifc_|q2 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|q2 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X47_Y17_N24 +// Location: LCCOMB_X27_Y13_N16 cycloneive_lcell_comb \z80_|memory_ifc_|nRFSH_out~0 ( // Equation(s): // \z80_|memory_ifc_|nRFSH_out~0_combout = (!\z80_|memory_ifc_|q2~q & \z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q ) @@ -59816,41 +59566,41 @@ defparam \z80_|memory_ifc_|nRFSH_out~0 .lut_mask = 16'h0F00; defparam \z80_|memory_ifc_|nRFSH_out~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X47_Y17_N26 +// Location: LCCOMB_X27_Y13_N20 cycloneive_lcell_comb \z80_|memory_ifc_|nM1_out ( // Equation(s): // \z80_|memory_ifc_|nM1_out~combout = (\z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - .dataa(gnd), + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(gnd), .datad(\z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q ), .cin(gnd), .combout(\z80_|memory_ifc_|nM1_out~combout ), .cout()); // synopsys translate_off -defparam \z80_|memory_ifc_|nM1_out .lut_mask = 16'hFF0F; +defparam \z80_|memory_ifc_|nM1_out .lut_mask = 16'hFF55; defparam \z80_|memory_ifc_|nM1_out .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y26_N0 +// Location: LCCOMB_X24_Y10_N28 cycloneive_lcell_comb \ula_|beep~0 ( // Equation(s): -// \ula_|beep~0_combout = \D[4]~98_combout $ (\raw_loader_in~input_o $ (\D[3]~96_combout )) +// \ula_|beep~0_combout = \raw_loader_in~input_o $ (\D[3]~74_combout $ (\D[4]~76_combout )) - .dataa(gnd), - .datab(\D[4]~98_combout ), - .datac(\raw_loader_in~input_o ), - .datad(\D[3]~96_combout ), + .dataa(\raw_loader_in~input_o ), + .datab(\D[3]~74_combout ), + .datac(gnd), + .datad(\D[4]~76_combout ), .cin(gnd), .combout(\ula_|beep~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|beep~0 .lut_mask = 16'hC33C; +defparam \ula_|beep~0 .lut_mask = 16'h9966; defparam \ula_|beep~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X23_Y26_N1 +// Location: FF_X24_Y10_N29 dffeas \ula_|beep ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\ula_|beep~0_combout ), diff --git a/simulation/modelsim/spectrum_6_1200mv_85c_v_slow.sdo b/simulation/modelsim/spectrum_6_1200mv_85c_v_slow.sdo index 55e5471..299023c 100644 --- a/simulation/modelsim/spectrum_6_1200mv_85c_v_slow.sdo +++ b/simulation/modelsim/spectrum_6_1200mv_85c_v_slow.sdo @@ -29,7 +29,7 @@ (DELAYFILE (SDFVERSION "2.1") (DESIGN "spectrum") - (DATE "04/01/2022 18:55:52") + (DATE "04/02/2022 15:53:45") (VENDOR "Altera") (PROGRAM "Quartus II 32-bit") (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition") @@ -41,8 +41,8 @@ (INSTANCE GPIO_1\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (2109:2109:2109) (2123:2123:2123)) - (PORT oe (1638:1638:1638) (1708:1708:1708)) + (PORT i (1830:1830:1830) (1899:1899:1899)) + (PORT oe (665:665:665) (729:729:729)) (IOPATH i o (2455:2455:2455) (2378:2378:2378)) (IOPATH oe o (2462:2462:2462) (2342:2342:2342)) ) @@ -53,8 +53,8 @@ (INSTANCE GPIO_1\[1\]\~output) (DELAY (ABSOLUTE - (PORT i (2133:2133:2133) (2174:2174:2174)) - (PORT oe (1897:1897:1897) (1931:1931:1931)) + (PORT i (1501:1501:1501) (1544:1544:1544)) + (PORT oe (2628:2628:2628) (2678:2678:2678)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -65,8 +65,8 @@ (INSTANCE GPIO_1\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (1984:1984:1984) (2083:2083:2083)) - (PORT oe (1897:1897:1897) (1931:1931:1931)) + (PORT i (1614:1614:1614) (1670:1670:1670)) + (PORT oe (2628:2628:2628) (2678:2678:2678)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -77,8 +77,8 @@ (INSTANCE GPIO_1\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (2218:2218:2218) (2284:2284:2284)) - (PORT oe (2147:2147:2147) (2236:2236:2236)) + (PORT i (1332:1332:1332) (1382:1382:1382)) + (PORT oe (2433:2433:2433) (2486:2486:2486)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -89,8 +89,8 @@ (INSTANCE GPIO_1\[4\]\~output) (DELAY (ABSOLUTE - (PORT i (2271:2271:2271) (2432:2432:2432)) - (PORT oe (2147:2147:2147) (2236:2236:2236)) + (PORT i (1331:1331:1331) (1379:1379:1379)) + (PORT oe (2433:2433:2433) (2486:2486:2486)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -101,8 +101,8 @@ (INSTANCE GPIO_1\[5\]\~output) (DELAY (ABSOLUTE - (PORT i (1973:1973:1973) (2011:2011:2011)) - (PORT oe (1910:1910:1910) (2005:2005:2005)) + (PORT i (1438:1438:1438) (1484:1484:1484)) + (PORT oe (2229:2229:2229) (2285:2285:2285)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -113,8 +113,8 @@ (INSTANCE GPIO_1\[6\]\~output) (DELAY (ABSOLUTE - (PORT i (1640:1640:1640) (1716:1716:1716)) - (PORT oe (1910:1910:1910) (2005:2005:2005)) + (PORT i (1192:1192:1192) (1274:1274:1274)) + (PORT oe (2229:2229:2229) (2285:2285:2285)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -125,8 +125,8 @@ (INSTANCE GPIO_1\[7\]\~output) (DELAY (ABSOLUTE - (PORT i (1960:1960:1960) (2148:2148:2148)) - (PORT oe (1910:1910:1910) (2005:2005:2005)) + (PORT i (907:907:907) (989:989:989)) + (PORT oe (2229:2229:2229) (2285:2285:2285)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -137,8 +137,8 @@ (INSTANCE GPIO_1\[8\]\~output) (DELAY (ABSOLUTE - (PORT i (976:976:976) (1064:1064:1064)) - (PORT oe (2161:2161:2161) (2266:2266:2266)) + (PORT i (1163:1163:1163) (1233:1233:1233)) + (PORT oe (1969:1969:1969) (2023:2023:2023)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -149,8 +149,8 @@ (INSTANCE GPIO_1\[9\]\~output) (DELAY (ABSOLUTE - (PORT i (1717:1717:1717) (1803:1803:1803)) - (PORT oe (2161:2161:2161) (2266:2266:2266)) + (PORT i (1181:1181:1181) (1259:1259:1259)) + (PORT oe (1969:1969:1969) (2023:2023:2023)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -161,8 +161,8 @@ (INSTANCE GPIO_1\[10\]\~output) (DELAY (ABSOLUTE - (PORT i (1939:1939:1939) (1996:1996:1996)) - (PORT oe (2404:2404:2404) (2537:2537:2537)) + (PORT i (1369:1369:1369) (1442:1442:1442)) + (PORT oe (2324:2324:2324) (2420:2420:2420)) (IOPATH i o (4557:4557:4557) (4190:4190:4190)) (IOPATH oe o (4578:4578:4578) (4159:4159:4159)) ) @@ -173,8 +173,8 @@ (INSTANCE GPIO_1\[11\]\~output) (DELAY (ABSOLUTE - (PORT i (1417:1417:1417) (1462:1462:1462)) - (PORT oe (2161:2161:2161) (2266:2266:2266)) + (PORT i (915:915:915) (998:998:998)) + (PORT oe (1969:1969:1969) (2023:2023:2023)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -185,8 +185,8 @@ (INSTANCE GPIO_1\[12\]\~output) (DELAY (ABSOLUTE - (PORT i (2181:2181:2181) (2209:2209:2209)) - (PORT oe (1700:1700:1700) (1736:1736:1736)) + (PORT i (1937:1937:1937) (2028:2028:2028)) + (PORT oe (2850:2850:2850) (2883:2883:2883)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -197,8 +197,8 @@ (INSTANCE GPIO_1\[13\]\~output) (DELAY (ABSOLUTE - (PORT i (2231:2231:2231) (2361:2361:2361)) - (PORT oe (2404:2404:2404) (2537:2537:2537)) + (PORT i (904:904:904) (971:971:971)) + (PORT oe (2324:2324:2324) (2420:2420:2420)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -209,8 +209,8 @@ (INSTANCE GPIO_1\[14\]\~output) (DELAY (ABSOLUTE - (PORT i (1625:1625:1625) (1715:1715:1715)) - (PORT oe (2140:2140:2140) (2250:2250:2250)) + (PORT i (1461:1461:1461) (1510:1510:1510)) + (PORT oe (2460:2460:2460) (2506:2506:2506)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -221,8 +221,8 @@ (INSTANCE GPIO_1\[15\]\~output) (DELAY (ABSOLUTE - (PORT i (1724:1724:1724) (1854:1854:1854)) - (PORT oe (1916:1916:1916) (1948:1948:1948)) + (PORT i (1184:1184:1184) (1288:1288:1288)) + (PORT oe (2584:2584:2584) (2639:2639:2639)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -233,8 +233,8 @@ (INSTANCE GPIO_1\[16\]\~output) (DELAY (ABSOLUTE - (PORT i (1202:1202:1202) (1265:1265:1265)) - (PORT oe (2441:2441:2441) (2523:2523:2523)) + (PORT i (1221:1221:1221) (1285:1285:1285)) + (PORT oe (2434:2434:2434) (2522:2522:2522)) (IOPATH i o (2582:2582:2582) (2502:2502:2502)) (IOPATH oe o (2585:2585:2585) (2463:2463:2463)) ) @@ -245,8 +245,8 @@ (INSTANCE GPIO_1\[17\]\~output) (DELAY (ABSOLUTE - (PORT i (1216:1216:1216) (1287:1287:1287)) - (PORT oe (2442:2442:2442) (2524:2524:2524)) + (PORT i (1157:1157:1157) (1182:1182:1182)) + (PORT oe (2435:2435:2435) (2523:2523:2523)) (IOPATH i o (2582:2582:2582) (2502:2502:2502)) (IOPATH oe o (2585:2585:2585) (2463:2463:2463)) ) @@ -257,8 +257,8 @@ (INSTANCE GPIO_1\[18\]\~output) (DELAY (ABSOLUTE - (PORT i (1118:1118:1118) (1163:1163:1163)) - (PORT oe (2137:2137:2137) (2196:2196:2196)) + (PORT i (1420:1420:1420) (1450:1450:1450)) + (PORT oe (2131:2131:2131) (2196:2196:2196)) (IOPATH i o (2582:2582:2582) (2502:2502:2502)) (IOPATH oe o (2585:2585:2585) (2463:2463:2463)) ) @@ -269,8 +269,8 @@ (INSTANCE GPIO_1\[19\]\~output) (DELAY (ABSOLUTE - (PORT i (1161:1161:1161) (1237:1237:1237)) - (PORT oe (2441:2441:2441) (2523:2523:2523)) + (PORT i (1387:1387:1387) (1430:1430:1430)) + (PORT oe (2434:2434:2434) (2522:2522:2522)) (IOPATH i o (2582:2582:2582) (2502:2502:2502)) (IOPATH oe o (2585:2585:2585) (2463:2463:2463)) ) @@ -281,8 +281,8 @@ (INSTANCE GPIO_1\[20\]\~output) (DELAY (ABSOLUTE - (PORT i (1455:1455:1455) (1530:1530:1530)) - (PORT oe (2096:2096:2096) (2158:2158:2158)) + (PORT i (1197:1197:1197) (1228:1228:1228)) + (PORT oe (2099:2099:2099) (2154:2154:2154)) (IOPATH i o (2455:2455:2455) (2378:2378:2378)) (IOPATH oe o (2462:2462:2462) (2342:2342:2342)) ) @@ -293,8 +293,8 @@ (INSTANCE GPIO_1\[21\]\~output) (DELAY (ABSOLUTE - (PORT i (1343:1343:1343) (1352:1352:1352)) - (PORT oe (2136:2136:2136) (2195:2195:2195)) + (PORT i (1419:1419:1419) (1480:1480:1480)) + (PORT oe (2130:2130:2130) (2195:2195:2195)) (IOPATH i o (2582:2582:2582) (2502:2502:2502)) (IOPATH oe o (2585:2585:2585) (2463:2463:2463)) ) @@ -305,8 +305,8 @@ (INSTANCE GPIO_1\[22\]\~output) (DELAY (ABSOLUTE - (PORT i (1213:1213:1213) (1275:1275:1275)) - (PORT oe (2035:2035:2035) (2069:2069:2069)) + (PORT i (1428:1428:1428) (1471:1471:1471)) + (PORT oe (2028:2028:2028) (2068:2068:2068)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -317,8 +317,8 @@ (INSTANCE GPIO_1\[23\]\~output) (DELAY (ABSOLUTE - (PORT i (1131:1131:1131) (1146:1146:1146)) - (PORT oe (2405:2405:2405) (2466:2466:2466)) + (PORT i (1285:1285:1285) (1395:1395:1395)) + (PORT oe (2403:2403:2403) (2480:2480:2480)) (IOPATH i o (2582:2582:2582) (2502:2502:2502)) (IOPATH oe o (2585:2585:2585) (2463:2463:2463)) ) @@ -329,8 +329,8 @@ (INSTANCE GPIO_1\[27\]\~output) (DELAY (ABSOLUTE - (PORT i (1412:1412:1412) (1417:1417:1417)) - (PORT oe (1643:1643:1643) (1693:1693:1693)) + (PORT i (2150:2150:2150) (2203:2203:2203)) + (PORT oe (1277:1277:1277) (1408:1408:1408)) (IOPATH i o (2378:2378:2378) (2455:2455:2455)) (IOPATH oe o (2462:2462:2462) (2342:2342:2342)) ) @@ -341,8 +341,8 @@ (INSTANCE GPIO_1\[28\]\~output) (DELAY (ABSOLUTE - (PORT i (1794:1794:1794) (1688:1688:1688)) - (PORT oe (1916:1916:1916) (1948:1948:1948)) + (PORT i (1506:1506:1506) (1516:1516:1516)) + (PORT oe (2584:2584:2584) (2639:2639:2639)) (IOPATH i o (2445:2445:2445) (2535:2535:2535)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -353,8 +353,8 @@ (INSTANCE GPIO_1\[29\]\~output) (DELAY (ABSOLUTE - (PORT i (1533:1533:1533) (1531:1531:1531)) - (PORT oe (1352:1352:1352) (1405:1405:1405)) + (PORT i (1652:1652:1652) (1676:1676:1676)) + (PORT oe (968:968:968) (1077:1077:1077)) (IOPATH i o (2502:2502:2502) (2582:2582:2582)) (IOPATH oe o (2585:2585:2585) (2463:2463:2463)) ) @@ -365,8 +365,8 @@ (INSTANCE GPIO_1\[30\]\~output) (DELAY (ABSOLUTE - (PORT i (1050:1050:1050) (1062:1062:1062)) - (PORT oe (1327:1327:1327) (1369:1369:1369)) + (PORT i (1756:1756:1756) (1738:1738:1738)) + (PORT oe (676:676:676) (749:749:749)) (IOPATH i o (2582:2582:2582) (2502:2502:2502)) (IOPATH oe o (2585:2585:2585) (2463:2463:2463)) ) @@ -377,7 +377,7 @@ (INSTANCE LED\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (1615:1615:1615) (1516:1516:1516)) + (PORT i (1626:1626:1626) (1525:1525:1525)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -397,7 +397,7 @@ (INSTANCE LED\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (1304:1304:1304) (1340:1340:1340)) + (PORT i (1385:1385:1385) (1448:1448:1448)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -452,7 +452,7 @@ (INSTANCE VGA_R\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (1164:1164:1164) (1204:1204:1204)) + (PORT i (1370:1370:1370) (1408:1408:1408)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -462,7 +462,7 @@ (INSTANCE VGA_R\[1\]\~output) (DELAY (ABSOLUTE - (PORT i (1073:1073:1073) (1104:1104:1104)) + (PORT i (1164:1164:1164) (1210:1210:1210)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -472,7 +472,7 @@ (INSTANCE VGA_R\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (774:774:774) (751:751:751)) + (PORT i (512:512:512) (509:509:509)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -482,7 +482,7 @@ (INSTANCE VGA_R\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (986:986:986) (968:968:968)) + (PORT i (1031:1031:1031) (1025:1025:1025)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -492,7 +492,7 @@ (INSTANCE VGA_G\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (972:972:972) (958:958:958)) + (PORT i (789:789:789) (778:778:778)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -502,7 +502,7 @@ (INSTANCE VGA_G\[1\]\~output) (DELAY (ABSOLUTE - (PORT i (721:721:721) (699:699:699)) + (PORT i (777:777:777) (765:765:765)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -512,7 +512,7 @@ (INSTANCE VGA_G\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (843:843:843) (812:812:812)) + (PORT i (1036:1036:1036) (1027:1027:1027)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -522,7 +522,7 @@ (INSTANCE VGA_G\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (843:843:843) (812:812:812)) + (PORT i (1012:1012:1012) (1005:1005:1005)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -532,7 +532,7 @@ (INSTANCE VGA_B\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (717:717:717) (702:702:702)) + (PORT i (779:779:779) (760:760:760)) (IOPATH i o (4557:4557:4557) (4190:4190:4190)) ) ) @@ -542,7 +542,7 @@ (INSTANCE VGA_B\[1\]\~output) (DELAY (ABSOLUTE - (PORT i (692:692:692) (667:667:667)) + (PORT i (725:725:725) (712:712:712)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -552,7 +552,7 @@ (INSTANCE VGA_B\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (952:952:952) (940:940:940)) + (PORT i (984:984:984) (966:966:966)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -562,7 +562,7 @@ (INSTANCE VGA_B\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (1378:1378:1378) (1350:1350:1350)) + (PORT i (1080:1080:1080) (1107:1107:1107)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -590,7 +590,7 @@ (INSTANCE GPIO_1\[25\]\~output) (DELAY (ABSOLUTE - (PORT i (2048:2048:2048) (1957:1957:1957)) + (PORT i (2290:2290:2290) (2263:2263:2263)) (IOPATH i o (2445:2445:2445) (2535:2535:2535)) ) ) @@ -600,7 +600,7 @@ (INSTANCE GPIO_1\[26\]\~output) (DELAY (ABSOLUTE - (PORT i (1307:1307:1307) (1281:1281:1281)) + (PORT i (1745:1745:1745) (1754:1754:1754)) (IOPATH i o (4127:4127:4127) (4477:4477:4477)) ) ) @@ -610,7 +610,7 @@ (INSTANCE GPIO_1\[31\]\~output) (DELAY (ABSOLUTE - (PORT i (927:927:927) (923:923:923)) + (PORT i (1445:1445:1445) (1426:1426:1426)) (IOPATH i o (2582:2582:2582) (2502:2502:2502)) ) ) @@ -620,7 +620,7 @@ (INSTANCE buzzer_out\~output) (DELAY (ABSOLUTE - (PORT i (1348:1348:1348) (1373:1373:1373)) + (PORT i (2280:2280:2280) (2408:2408:2408)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -707,8 +707,8 @@ (INSTANCE ula_\|clocks_\|clk_cpu\~0) (DELAY (ABSOLUTE - (PORT datab (245:245:245) (328:328:328)) - (PORT datad (552:552:552) (573:573:573)) + (PORT datab (243:243:243) (326:326:326)) + (PORT datad (551:551:551) (574:574:574)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -734,35 +734,33 @@ (INSTANCE ula_\|clocks_\|clk_cpu\~clkctrl) (DELAY (ABSOLUTE - (PORT inclk[0] (716:716:716) (747:747:747)) + (PORT inclk[0] (720:720:720) (751:751:751)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|DFFE_M1_ff\~0) + (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_15) (DELAY (ABSOLUTE - (PORT dataa (1122:1122:1122) (1158:1158:1158)) - (PORT datad (1110:1110:1110) (1159:1159:1159)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|ena_M) - (DELAY - (ABSOLUTE - (PORT datac (1094:1094:1094) (1132:1132:1132)) - (PORT datad (1106:1106:1106) (1160:1160:1160)) + (PORT datab (1159:1159:1159) (1227:1227:1227)) + (PORT datac (621:621:621) (692:692:692)) + (PORT datad (895:895:895) (972:972:972)) + (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_12\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (604:604:604) (661:661:661)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_io_ibuf") (INSTANCE KEY\[1\]\~input) @@ -777,9 +775,9 @@ (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_9) (DELAY (ABSOLUTE - (PORT dataa (351:351:351) (490:490:490)) - (PORT datad (1994:1994:1994) (2109:2109:2109)) - (IOPATH dataa combout (304:304:304) (308:308:308)) + (PORT datac (409:409:409) (478:478:478)) + (PORT datad (2505:2505:2505) (2666:2666:2666)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -789,9 +787,9 @@ (INSTANCE z80_\|interrupts_\|nmi_armed) (DELAY (ABSOLUTE - (PORT clk (1476:1476:1476) (1490:1490:1490)) + (PORT clk (1744:1744:1744) (1760:1760:1760)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1325:1325:1325) (1320:1320:1320)) + (PORT clrn (766:766:766) (782:782:782)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -805,47 +803,52 @@ (INSTANCE z80_\|interrupts_\|in_nmi_ALTERA_SYNTHESIZED\~feeder) (DELAY (ABSOLUTE - (PORT datad (790:790:790) (826:826:826)) + (PORT datad (354:354:354) (411:411:411)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_eval_cond\~0) + (INSTANCE z80_\|sequencer_\|DFFE_M2_ff\~0) (DELAY (ABSOLUTE - (PORT datac (243:243:243) (323:323:323)) - (PORT datad (252:252:252) (325:325:325)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (429:429:429) (510:510:510)) + (PORT datab (1159:1159:1159) (1227:1227:1227)) + (PORT datad (893:893:893) (972:972:972)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~4) + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_M2_ff) (DELAY (ABSOLUTE - (PORT dataa (2418:2418:2418) (2567:2567:2567)) - (PORT datab (2411:2411:2411) (2541:2541:2541)) - (PORT datad (1577:1577:1577) (1737:1737:1737)) - (IOPATH dataa combout (301:301:301) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1558:1558:1558) (1539:1539:1539)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|sequencer_\|DFFE_M3_ff\~0) (DELAY (ABSOLUTE - (PORT dataa (1115:1115:1115) (1160:1160:1160)) - (PORT datab (408:408:408) (481:481:481)) - (PORT datad (1111:1111:1111) (1161:1161:1161)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (300:300:300) (311:311:311)) + (PORT dataa (268:268:268) (355:355:355)) + (PORT datab (1162:1162:1162) (1228:1228:1228)) + (PORT datad (896:896:896) (972:972:972)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -856,9 +859,9 @@ (INSTANCE z80_\|sequencer_\|DFFE_M3_ff) (DELAY (ABSOLUTE - (PORT clk (1540:1540:1540) (1556:1556:1556)) + (PORT clk (1514:1514:1514) (1528:1528:1528)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1596:1596:1596) (1571:1571:1571)) + (PORT clrn (1558:1558:1558) (1539:1539:1539)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -867,30 +870,16 @@ (HOLD d (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1355:1355:1355) (1381:1381:1381)) - (PORT datab (1537:1537:1537) (1647:1647:1647)) - (PORT datac (1348:1348:1348) (1441:1441:1441)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|sequencer_\|DFFE_M4_ff\~0) (DELAY (ABSOLUTE - (PORT dataa (1130:1130:1130) (1178:1178:1178)) - (PORT datab (413:413:413) (488:488:488)) - (PORT datad (1104:1104:1104) (1156:1156:1156)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (300:300:300) (311:311:311)) + (PORT dataa (291:291:291) (391:391:391)) + (PORT datab (1158:1158:1158) (1234:1234:1234)) + (PORT datad (894:894:894) (977:977:977)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -901,9 +890,9 @@ (INSTANCE z80_\|sequencer_\|DFFE_M4_ff) (DELAY (ABSOLUTE - (PORT clk (1540:1540:1540) (1556:1556:1556)) + (PORT clk (1514:1514:1514) (1528:1528:1528)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1596:1596:1596) (1571:1571:1571)) + (PORT clrn (1558:1558:1558) (1539:1539:1539)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -914,12 +903,55 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal32\~0) + (INSTANCE z80_\|sequencer_\|M5\~0) (DELAY (ABSOLUTE - (PORT datab (393:393:393) (466:466:466)) - (PORT datad (667:667:667) (742:742:742)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (PORT dataa (267:267:267) (354:354:354)) + (PORT datab (1163:1163:1163) (1235:1235:1235)) + (PORT datad (896:896:896) (975:975:975)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|M5) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1558:1558:1558) (1539:1539:1539)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~5) + (DELAY + (ABSOLUTE + (PORT datab (1182:1182:1182) (1321:1321:1321)) + (PORT datac (960:960:960) (1034:1034:1034)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~22) + (DELAY + (ABSOLUTE + (PORT dataa (1277:1277:1277) (1334:1334:1334)) + (PORT datad (1753:1753:1753) (1821:1821:1821)) + (IOPATH dataa combout (304:304:304) (308:308:308)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -929,48 +961,8 @@ (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_11) (DELAY (ABSOLUTE - (PORT datab (2598:2598:2598) (2742:2742:2742)) - (PORT datad (1607:1607:1607) (1729:1729:1729)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|table_xx\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1365:1365:1365) (1484:1484:1484)) - (PORT datad (1197:1197:1197) (1317:1317:1317)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal1\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1675:1675:1675) (1712:1712:1712)) - (PORT datab (945:945:945) (983:983:983)) - (PORT datac (2134:2134:2134) (2287:2287:2287)) - (PORT datad (1162:1162:1162) (1232:1232:1232)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal2\~0) - (DELAY - (ABSOLUTE - (PORT datac (1459:1459:1459) (1537:1537:1537)) - (PORT datad (2262:2262:2262) (2332:2332:2332)) + (PORT datac (1678:1678:1678) (1762:1762:1762)) + (PORT datad (2068:2068:2068) (2236:2236:2236)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -978,452 +970,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal36\~0) + (INSTANCE z80_\|execute_\|ctl_ir_we\~4) (DELAY (ABSOLUTE - (PORT dataa (1246:1246:1246) (1343:1343:1343)) - (PORT datab (1671:1671:1671) (1786:1786:1786)) - (PORT datac (906:906:906) (959:959:959)) - (PORT datad (943:943:943) (998:998:998)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_tbl_cb_set) - (DELAY - (ABSOLUTE - (PORT dataa (1739:1739:1739) (1786:1786:1786)) - (PORT datab (1426:1426:1426) (1455:1455:1455)) - (PORT datac (846:846:846) (882:882:882)) - (PORT datad (789:789:789) (792:792:792)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_tbl_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1224:1224:1224) (1329:1329:1329)) - (PORT datab (2644:2644:2644) (2764:2764:2764)) - (PORT datac (844:844:844) (879:879:879)) - (PORT datad (972:972:972) (1035:1035:1035)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|DFFE_instCB) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1549:1549:1549)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1588:1588:1588) (1563:1563:1563)) - (PORT ena (790:790:790) (783:783:783)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal52\~0) - (DELAY - (ABSOLUTE - (PORT dataa (711:711:711) (808:808:808)) - (PORT datab (1233:1233:1233) (1347:1347:1347)) - (PORT datac (988:988:988) (1067:1067:1067)) - (PORT datad (1323:1323:1323) (1441:1441:1441)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal2\~1) - (DELAY - (ABSOLUTE - (PORT dataa (2337:2337:2337) (2490:2490:2490)) - (PORT datab (1667:1667:1667) (1786:1786:1786)) - (PORT datac (905:905:905) (957:957:957)) - (PORT datad (672:672:672) (720:720:720)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_tbl_ed_set) - (DELAY - (ABSOLUTE - (PORT dataa (1761:1761:1761) (1838:1838:1838)) - (PORT datab (839:839:839) (854:854:854)) - (PORT datac (1396:1396:1396) (1420:1420:1420)) - (PORT datad (2042:2042:2042) (2106:2106:2106)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|DFFE_instED) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1549:1549:1549)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1588:1588:1588) (1563:1563:1563)) - (PORT ena (790:790:790) (783:783:783)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal13\~0) - (DELAY - (ABSOLUTE - (PORT dataa (714:714:714) (810:810:810)) - (PORT datac (981:981:981) (1058:1058:1058)) - (PORT datad (1323:1323:1323) (1434:1434:1434)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal33\~0) - (DELAY - (ABSOLUTE - (PORT dataa (2169:2169:2169) (2327:2327:2327)) - (PORT datac (1460:1460:1460) (1537:1537:1537)) - (PORT datad (2263:2263:2263) (2329:2329:2329)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_im_we) - (DELAY - (ABSOLUTE - (PORT dataa (610:610:610) (636:636:636)) - (PORT datab (1050:1050:1050) (1169:1169:1169)) - (PORT datac (1337:1337:1337) (1469:1469:1469)) - (PORT datad (915:915:915) (959:959:959)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal49\~0) - (DELAY - (ABSOLUTE - (PORT datab (997:997:997) (1105:1105:1105)) - (PORT datac (656:656:656) (719:719:719)) - (PORT datad (1244:1244:1244) (1328:1328:1328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal33\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1410:1410:1410) (1499:1499:1499)) - (PORT datab (1489:1489:1489) (1614:1614:1614)) - (PORT datac (1433:1433:1433) (1524:1524:1524)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal6\~0) - (DELAY - (ABSOLUTE - (PORT dataa (711:711:711) (809:809:809)) - (PORT datab (1233:1233:1233) (1347:1347:1347)) - (PORT datac (989:989:989) (1067:1067:1067)) - (PORT datad (1323:1323:1323) (1441:1441:1441)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1232:1232:1232) (1301:1301:1301)) - (PORT datab (1273:1273:1273) (1368:1368:1368)) - (PORT datad (711:711:711) (773:773:773)) + (PORT dataa (1200:1200:1200) (1290:1290:1290)) + (PORT datad (1121:1121:1121) (1183:1183:1183)) (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal12\~0) - (DELAY - (ABSOLUTE - (PORT dataa (2639:2639:2639) (2814:2814:2814)) - (PORT datab (899:899:899) (934:934:934)) - (PORT datac (1110:1110:1110) (1167:1167:1167)) - (PORT datad (1150:1150:1150) (1194:1194:1194)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~8) - (DELAY - (ABSOLUTE - (PORT dataa (933:933:933) (1033:1033:1033)) - (PORT datab (1561:1561:1561) (1662:1662:1662)) - (PORT datac (1411:1411:1411) (1476:1476:1476)) - (PORT datad (201:201:201) (238:238:238)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|nM1_int\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1116:1116:1116) (1239:1239:1239)) - (PORT datad (2109:2109:2109) (2254:2254:2254)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1086:1086:1086) (1149:1149:1149)) - (PORT datab (1113:1113:1113) (1123:1123:1123)) - (PORT datac (333:333:333) (359:359:359)) - (PORT datad (689:689:689) (743:743:743)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal3\~0) - (DELAY - (ABSOLUTE - (PORT datac (1439:1439:1439) (1545:1545:1545)) - (PORT datad (1464:1464:1464) (1551:1551:1551)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1247:1247:1247) (1335:1335:1335)) - (PORT datab (1669:1669:1669) (1782:1782:1782)) - (PORT datac (1700:1700:1700) (1785:1785:1785)) - (PORT datad (944:944:944) (1001:1001:1001)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~7) - (DELAY - (ABSOLUTE - (PORT datac (1974:1974:1974) (2154:2154:2154)) - (PORT datad (1235:1235:1235) (1306:1306:1306)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1939:1939:1939) (2060:2060:2060)) - (PORT datac (2560:2560:2560) (2661:2661:2661)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~4) - (DELAY - (ABSOLUTE - (PORT dataa (891:891:891) (937:937:937)) - (PORT datab (1029:1029:1029) (1093:1093:1093)) - (PORT datac (849:849:849) (913:913:913)) - (PORT datad (929:929:929) (973:973:973)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal40\~1) - (DELAY - (ABSOLUTE - (PORT dataa (918:918:918) (941:941:941)) - (PORT datab (898:898:898) (917:917:917)) - (PORT datac (919:919:919) (1011:1011:1011)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal39\~0) - (DELAY - (ABSOLUTE - (PORT dataa (916:916:916) (940:940:940)) - (PORT datab (901:901:901) (913:913:913)) - (PORT datac (920:920:920) (1009:1009:1009)) - (PORT datad (1166:1166:1166) (1216:1216:1216)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~1) - (DELAY - (ABSOLUTE - (PORT dataa (856:856:856) (896:896:896)) - (PORT datac (977:977:977) (1048:1048:1048)) - (PORT datad (1170:1170:1170) (1184:1184:1184)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal13\~1) - (DELAY - (ABSOLUTE - (PORT dataa (2169:2169:2169) (2322:2322:2322)) - (PORT datac (1461:1461:1461) (1534:1534:1534)) - (PORT datad (2261:2261:2261) (2326:2326:2326)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal13\~2) - (DELAY - (ABSOLUTE - (PORT dataa (877:877:877) (972:972:972)) - (PORT datab (1721:1721:1721) (1812:1812:1812)) - (PORT datac (1148:1148:1148) (1153:1153:1153)) - (PORT datad (650:650:650) (690:690:690)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal3\~2) - (DELAY - (ABSOLUTE - (PORT dataa (944:944:944) (975:975:975)) - (PORT datab (2317:2317:2317) (2471:2471:2471)) - (PORT datac (1702:1702:1702) (1788:1788:1788)) - (PORT datad (669:669:669) (716:716:716)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -1433,10 +985,10 @@ (INSTANCE z80_\|execute_\|ctl_state_iy_set\~2) (DELAY (ABSOLUTE - (PORT dataa (1211:1211:1211) (1331:1331:1331)) - (PORT datab (2075:2075:2075) (2256:2256:2256)) - (PORT datac (862:862:862) (881:881:881)) - (PORT datad (1458:1458:1458) (1561:1561:1561)) + (PORT dataa (1727:1727:1727) (1809:1809:1809)) + (PORT datab (2112:2112:2112) (2282:2282:2282)) + (PORT datac (713:713:713) (798:798:798)) + (PORT datad (383:383:383) (415:415:415)) (IOPATH dataa combout (304:304:304) (299:299:299)) (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -1446,220 +998,34 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~8) + (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_16) (DELAY (ABSOLUTE - (PORT datab (1418:1418:1418) (1489:1489:1489)) - (PORT datac (1562:1562:1562) (1631:1631:1631)) + (PORT datab (1159:1159:1159) (1233:1233:1233)) + (PORT datac (237:237:237) (315:315:315)) + (PORT datad (895:895:895) (975:975:975)) (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~6) - (DELAY - (ABSOLUTE - (PORT datac (1595:1595:1595) (1686:1686:1686)) - (PORT datad (1897:1897:1897) (2018:2018:2018)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~9) - (DELAY - (ABSOLUTE - (PORT datac (1033:1033:1033) (1103:1103:1103)) - (PORT datad (985:985:985) (1046:1046:1046)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1003:1003:1003) (1060:1060:1060)) - (PORT datab (989:989:989) (1052:1052:1052)) - (PORT datac (903:903:903) (941:941:941)) - (PORT datad (2055:2055:2055) (2108:2108:2108)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~10) - (DELAY - (ABSOLUTE - (PORT dataa (424:424:424) (461:461:461)) - (PORT datab (1160:1160:1160) (1195:1195:1195)) - (PORT datac (623:623:623) (685:685:685)) - (PORT datad (1108:1108:1108) (1138:1138:1138)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal44\~0) - (DELAY - (ABSOLUTE - (PORT dataa (711:711:711) (810:810:810)) - (PORT datab (1238:1238:1238) (1352:1352:1352)) - (PORT datac (982:982:982) (1059:1059:1059)) - (PORT datad (1323:1323:1323) (1435:1435:1435)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~16) - (DELAY - (ABSOLUTE - (PORT dataa (976:976:976) (1074:1074:1074)) - (PORT datab (1336:1336:1336) (1358:1358:1358)) - (PORT datac (931:931:931) (1016:1016:1016)) - (PORT datad (1108:1108:1108) (1132:1132:1132)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~13) - (DELAY - (ABSOLUTE - (PORT datab (836:836:836) (897:897:897)) - (PORT datac (619:619:619) (671:671:671)) - (PORT datad (213:213:213) (245:245:245)) - (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal50\~0) + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_T5_ff) (DELAY (ABSOLUTE - (PORT datab (998:998:998) (1107:1107:1107)) - (PORT datac (656:656:656) (717:717:717)) - (PORT datad (1193:1193:1193) (1255:1255:1255)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1558:1558:1558) (1539:1539:1539)) + (PORT ena (1441:1441:1441) (1437:1437:1437)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal33\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1233:1233:1233) (1300:1300:1300)) - (PORT datab (1273:1273:1273) (1368:1368:1368)) - (PORT datad (711:711:711) (773:773:773)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~17) - (DELAY - (ABSOLUTE - (PORT dataa (967:967:967) (1063:1063:1063)) - (PORT datab (1112:1112:1112) (1107:1107:1107)) - (PORT datac (928:928:928) (1011:1011:1011)) - (PORT datad (1085:1085:1085) (1082:1082:1082)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~5) - (DELAY - (ABSOLUTE - (PORT datac (1607:1607:1607) (1722:1722:1722)) - (PORT datad (984:984:984) (1047:1047:1047)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~14) - (DELAY - (ABSOLUTE - (PORT dataa (612:612:612) (674:674:674)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (199:199:199) (237:237:237)) - (PORT datad (1103:1103:1103) (1112:1112:1112)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1593:1593:1593) (1671:1671:1671)) - (PORT datab (1420:1420:1420) (1492:1492:1492)) - (PORT datac (372:372:372) (399:399:399)) - (PORT datad (1786:1786:1786) (1904:1904:1904)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1089:1089:1089) (1107:1107:1107)) - (PORT datab (236:236:236) (282:282:282)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) ) ) (CELL @@ -1667,12 +1033,12 @@ (INSTANCE z80_\|execute_\|ctl_state_ixiy_we\~2) (DELAY (ABSOLUTE - (PORT dataa (1302:1302:1302) (1399:1399:1399)) - (PORT datab (1499:1499:1499) (1604:1604:1604)) - (PORT datac (1460:1460:1460) (1551:1551:1551)) - (PORT datad (2054:2054:2054) (2222:2222:2222)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (PORT dataa (856:856:856) (896:896:896)) + (PORT datab (2112:2112:2112) (2285:2285:2285)) + (PORT datac (1687:1687:1687) (1773:1773:1773)) + (PORT datad (896:896:896) (1011:1011:1011)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -1683,9 +1049,9 @@ (INSTANCE z80_\|decode_state_\|DFFE_instIY1) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1547:1547:1547)) + (PORT clk (1525:1525:1525) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1586:1586:1586) (1563:1563:1563)) + (PORT clrn (1559:1559:1559) (1540:1540:1540)) (PORT ena (820:820:820) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) @@ -1698,89 +1064,25 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~5) + (INSTANCE z80_\|decode_state_\|use_ixiy) (DELAY (ABSOLUTE - (PORT dataa (887:887:887) (960:960:960)) - (PORT datac (643:643:643) (708:708:708)) - (PORT datad (1365:1365:1365) (1481:1481:1481)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT datab (504:504:504) (586:586:586)) + (PORT datad (443:443:443) (528:528:528)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~14) + (INSTANCE z80_\|execute_\|ixy_d\~4) (DELAY (ABSOLUTE - (PORT dataa (1259:1259:1259) (1368:1368:1368)) - (PORT datab (463:463:463) (524:524:524)) - (PORT datac (1699:1699:1699) (1754:1754:1754)) - (PORT datad (267:267:267) (321:321:321)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~2) - (DELAY - (ABSOLUTE - (PORT dataa (709:709:709) (805:805:805)) - (PORT datab (1019:1019:1019) (1101:1101:1101)) - (PORT datac (676:676:676) (769:769:769)) - (PORT datad (1322:1322:1322) (1435:1435:1435)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1624:1624:1624) (1717:1717:1717)) - (PORT datab (1533:1533:1533) (1585:1585:1585)) - (PORT datac (1709:1709:1709) (1830:1830:1830)) - (PORT datad (1494:1494:1494) (1626:1626:1626)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1299:1299:1299) (1388:1388:1388)) - (PORT datab (1243:1243:1243) (1323:1323:1323)) - (PORT datac (1034:1034:1034) (1082:1082:1082)) - (PORT datad (1678:1678:1678) (1738:1738:1738)) - (IOPATH dataa combout (356:356:356) (368:368:368)) + (PORT datab (1017:1017:1017) (1082:1082:1082)) + (PORT datac (1488:1488:1488) (1607:1607:1607)) + (PORT datad (946:946:946) (1006:1006:1006)) (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~26) - (DELAY - (ABSOLUTE - (PORT datac (685:685:685) (734:734:734)) - (PORT datad (1734:1734:1734) (1851:1851:1851)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -1788,191 +1090,39 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~27) + (INSTANCE z80_\|execute_\|ixy_d\~11) (DELAY (ABSOLUTE - (PORT dataa (648:648:648) (666:666:666)) - (PORT datac (1102:1102:1102) (1151:1151:1151)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~7) - (DELAY - (ABSOLUTE - (PORT dataa (206:206:206) (252:252:252)) - (PORT datab (244:244:244) (291:291:291)) - (PORT datac (669:669:669) (688:688:688)) - (PORT datad (2054:2054:2054) (2107:2107:2107)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1002:1002:1002) (1065:1065:1065)) - (PORT datab (1219:1219:1219) (1281:1281:1281)) - (PORT datac (688:688:688) (740:740:740)) - (PORT datad (179:179:179) (206:206:206)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~18) - (DELAY - (ABSOLUTE - (PORT dataa (931:931:931) (1031:1031:1031)) - (PORT datab (1557:1557:1557) (1661:1661:1661)) - (PORT datac (1407:1407:1407) (1474:1474:1474)) - (PORT datad (203:203:203) (238:238:238)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal55\~0) - (DELAY - (ABSOLUTE - (PORT dataa (288:288:288) (386:386:386)) - (PORT datac (902:902:902) (964:964:964)) - (PORT datad (928:928:928) (984:984:984)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|comb\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1762:1762:1762) (1872:1872:1872)) - (PORT datac (1146:1146:1146) (1226:1226:1226)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~15) - (DELAY - (ABSOLUTE - (PORT dataa (622:622:622) (664:664:664)) - (PORT datab (1178:1178:1178) (1215:1215:1215)) - (PORT datac (934:934:934) (1030:1030:1030)) - (PORT datad (181:181:181) (212:212:212)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~17) - (DELAY - (ABSOLUTE - (PORT dataa (668:668:668) (723:723:723)) - (PORT datab (653:653:653) (674:674:674)) - (PORT datac (936:936:936) (1036:1036:1036)) - (PORT datad (898:898:898) (943:943:943)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~5) - (DELAY - (ABSOLUTE - (PORT dataa (941:941:941) (958:958:958)) - (PORT datab (1199:1199:1199) (1222:1222:1222)) - (PORT datac (1813:1813:1813) (1890:1890:1890)) - (PORT datad (871:871:871) (910:910:910)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1687:1687:1687) (1746:1746:1746)) - (PORT datac (1659:1659:1659) (1737:1737:1737)) - (PORT datad (1165:1165:1165) (1209:1209:1209)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal9\~0) - (DELAY - (ABSOLUTE - (PORT datac (826:826:826) (880:880:880)) - (PORT datad (900:900:900) (971:971:971)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1685:1685:1685) (1750:1750:1750)) - (PORT datab (1691:1691:1691) (1776:1776:1776)) - (PORT datac (1479:1479:1479) (1575:1575:1575)) - (PORT datad (1244:1244:1244) (1311:1311:1311)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1465:1465:1465) (1537:1537:1537)) - (PORT datab (1233:1233:1233) (1318:1318:1318)) - (PORT datac (1424:1424:1424) (1514:1514:1514)) - (PORT datad (825:825:825) (838:838:838)) + (PORT dataa (1502:1502:1502) (1609:1609:1609)) + (PORT datab (2670:2670:2670) (2813:2813:2813)) + (PORT datac (1298:1298:1298) (1393:1393:1393)) + (PORT datad (858:858:858) (885:885:885)) (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1714:1714:1714) (1799:1799:1799)) + (PORT datac (2408:2408:2408) (2538:2538:2538)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~7) + (DELAY + (ABSOLUTE + (PORT datac (1804:1804:1804) (1893:1893:1893)) + (PORT datad (956:956:956) (1070:1070:1070)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -1980,28 +1130,52 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~20) + (INSTANCE z80_\|execute_\|ixy_d\~6) (DELAY (ABSOLUTE - (PORT dataa (891:891:891) (914:914:914)) - (PORT datab (1241:1241:1241) (1279:1279:1279)) - (PORT datac (1377:1377:1377) (1384:1384:1384)) - (PORT datad (1263:1263:1263) (1301:1301:1301)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (634:634:634) (716:716:716)) + (PORT datac (685:685:685) (777:777:777)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~8) + (DELAY + (ABSOLUTE + (PORT datab (269:269:269) (353:353:353)) + (PORT datad (258:258:258) (340:340:340)) + (IOPATH datab combout (306:306:306) (311:311:311)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal12\~1) + (INSTANCE z80_\|execute_\|ixy_d\~12) (DELAY (ABSOLUTE - (PORT dataa (619:619:619) (657:657:657)) - (PORT datab (963:963:963) (1059:1059:1059)) - (PORT datad (1154:1154:1154) (1176:1176:1176)) + (PORT dataa (2032:2032:2032) (2090:2090:2090)) + (PORT datab (950:950:950) (1005:1005:1005)) + (PORT datac (1675:1675:1675) (1738:1738:1738)) + (PORT datad (1255:1255:1255) (1334:1334:1334)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal33\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1691:1691:1691) (1740:1740:1740)) + (PORT datab (271:271:271) (356:356:356)) + (PORT datad (380:380:380) (449:449:449)) (IOPATH dataa combout (304:304:304) (299:299:299)) (IOPATH datab combout (336:336:336) (332:332:332)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -2010,75 +1184,55 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal9\~1) + (INSTANCE z80_\|pla_decode_\|Equal33\~1) (DELAY (ABSOLUTE - (PORT dataa (1565:1565:1565) (1659:1659:1659)) - (PORT datab (982:982:982) (1039:1039:1039)) - (PORT datac (1634:1634:1634) (1749:1749:1749)) - (PORT datad (1216:1216:1216) (1293:1293:1293)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (1993:1993:1993) (2188:2188:2188)) + (PORT datab (1212:1212:1212) (1313:1313:1313)) + (PORT datad (1274:1274:1274) (1364:1364:1364)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal25\~0) + (INSTANCE z80_\|pla_decode_\|Equal33\~2) (DELAY (ABSOLUTE - (PORT dataa (1460:1460:1460) (1559:1559:1559)) - (PORT datab (1540:1540:1540) (1676:1676:1676)) - (PORT datac (1379:1379:1379) (1439:1439:1439)) - (PORT datad (1566:1566:1566) (1596:1596:1596)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (1216:1216:1216) (1313:1313:1313)) + (PORT datab (987:987:987) (1068:1068:1068)) + (PORT datad (1628:1628:1628) (1639:1639:1639)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~21) + (INSTANCE z80_\|pla_decode_\|Equal21\~0) (DELAY (ABSOLUTE - (PORT dataa (894:894:894) (913:913:913)) - (PORT datab (1819:1819:1819) (1900:1900:1900)) - (PORT datac (867:867:867) (883:883:883)) - (PORT datad (1475:1475:1475) (1552:1552:1552)) - (IOPATH dataa combout (300:300:300) (307:307:307)) + (PORT datab (1417:1417:1417) (1524:1524:1524)) + (PORT datad (1439:1439:1439) (1527:1527:1527)) (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~6) + (INSTANCE z80_\|pla_decode_\|Equal77\~0) (DELAY (ABSOLUTE - (PORT dataa (1220:1220:1220) (1307:1307:1307)) - (PORT datac (948:948:948) (1024:1024:1024)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal19\~0) - (DELAY - (ABSOLUTE - (PORT dataa (940:940:940) (969:969:969)) - (PORT datab (936:936:936) (992:992:992)) - (PORT datac (1633:1633:1633) (1753:1753:1753)) - (PORT datad (1215:1215:1215) (1294:1294:1294)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) + (PORT dataa (1044:1044:1044) (1137:1137:1137)) + (PORT datab (996:996:996) (1103:1103:1103)) + (PORT datac (929:929:929) (1055:1055:1055)) + (PORT datad (975:975:975) (1059:1059:1059)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -2086,58 +1240,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal1\~4) + (INSTANCE z80_\|pla_decode_\|Equal77\~1) (DELAY (ABSOLUTE - (PORT datac (1720:1720:1720) (1792:1792:1792)) - (PORT datad (2039:2039:2039) (2100:2100:2100)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal29\~0) - (DELAY - (ABSOLUTE - (PORT dataa (220:220:220) (263:263:263)) - (PORT datab (1158:1158:1158) (1201:1201:1201)) - (PORT datac (1618:1618:1618) (1607:1607:1607)) - (PORT datad (1454:1454:1454) (1538:1538:1538)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal24\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1564:1564:1564) (1657:1657:1657)) - (PORT datab (978:978:978) (1038:1038:1038)) - (PORT datac (1634:1634:1634) (1759:1759:1759)) - (PORT datad (1220:1220:1220) (1302:1302:1302)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal34\~0) - (DELAY - (ABSOLUTE - (PORT dataa (2169:2169:2169) (2326:2326:2326)) - (PORT datab (948:948:948) (988:988:988)) - (PORT datac (193:193:193) (227:227:227)) - (PORT datad (416:416:416) (461:461:461)) - (IOPATH dataa combout (301:301:301) (299:299:299)) + (PORT dataa (670:670:670) (727:727:727)) + (PORT datab (658:658:658) (743:743:743)) + (PORT datac (1694:1694:1694) (1759:1759:1759)) + (PORT datad (583:583:583) (602:602:602)) + (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -2146,15 +1256,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal37\~0) + (INSTANCE z80_\|pla_decode_\|Equal1\~7) (DELAY (ABSOLUTE - (PORT dataa (445:445:445) (500:500:500)) - (PORT datab (942:942:942) (982:982:982)) - (PORT datac (2138:2138:2138) (2282:2282:2282)) - (PORT datad (1141:1141:1141) (1176:1176:1176)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) + (PORT dataa (1216:1216:1216) (1292:1292:1292)) + (PORT datab (615:615:615) (683:683:683)) + (PORT datac (570:570:570) (579:579:579)) + (PORT datad (592:592:592) (657:657:657)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -2162,15 +1272,99 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal35\~0) + (INSTANCE z80_\|pla_decode_\|Equal79\~0) (DELAY (ABSOLUTE - (PORT dataa (446:446:446) (504:504:504)) - (PORT datab (946:946:946) (982:982:982)) - (PORT datac (2134:2134:2134) (2284:2284:2284)) - (PORT datad (195:195:195) (221:221:221)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) + (PORT dataa (781:781:781) (882:882:882)) + (PORT datab (1924:1924:1924) (2018:2018:2018)) + (PORT datac (1269:1269:1269) (1341:1341:1341)) + (PORT datad (1618:1618:1618) (1697:1697:1697)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|iff1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (218:218:218) (269:269:269)) + (PORT datab (1398:1398:1398) (1441:1441:1441)) + (PORT datac (393:393:393) (457:457:457)) + (PORT datad (1231:1231:1231) (1327:1327:1327)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|DFFE_instIFF2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (216:216:216) (265:265:265)) + (PORT datab (1399:1399:1399) (1440:1440:1440)) + (PORT datad (1233:1233:1233) (1329:1329:1329)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_12) + (DELAY + (ABSOLUTE + (PORT dataa (2786:2786:2786) (2933:2933:2933)) + (PORT datab (693:693:693) (770:770:770)) + (PORT datad (888:888:888) (957:957:957)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_12\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (1082:1082:1082) (1108:1108:1108)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|interrupts_\|DFFE_instIFF2) + (DELAY + (ABSOLUTE + (PORT clk (1541:1541:1541) (1557:1557:1557)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1556:1556:1556) (1548:1548:1548)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal13\~0) + (DELAY + (ABSOLUTE + (PORT dataa (285:285:285) (382:382:382)) + (PORT datac (398:398:398) (476:476:476)) + (PORT datad (390:390:390) (455:455:455)) + (IOPATH dataa combout (303:303:303) (308:308:308)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -2181,433 +1375,10 @@ (INSTANCE z80_\|pla_decode_\|Equal38\~2) (DELAY (ABSOLUTE - (PORT dataa (1627:1627:1627) (1717:1717:1717)) - (PORT datab (1533:1533:1533) (1663:1663:1663)) - (PORT datac (1709:1709:1709) (1827:1827:1827)) - (PORT datad (1445:1445:1445) (1492:1492:1492)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1114:1114:1114) (1137:1137:1137)) - (PORT datab (1107:1107:1107) (1172:1172:1172)) - (PORT datac (580:580:580) (611:611:611)) - (PORT datad (895:895:895) (945:945:945)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~3) - (DELAY - (ABSOLUTE - (PORT dataa (867:867:867) (927:927:927)) - (PORT datab (1362:1362:1362) (1426:1426:1426)) - (PORT datac (584:584:584) (617:617:617)) - (PORT datad (583:583:583) (602:602:602)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|comb\~0) - (DELAY - (ABSOLUTE - (PORT datab (1940:1940:1940) (2011:2011:2011)) - (PORT datac (1163:1163:1163) (1222:1222:1222)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal47\~0) - (DELAY - (ABSOLUTE - (PORT dataa (450:450:450) (507:507:507)) - (PORT datab (949:949:949) (988:988:988)) - (PORT datac (2135:2135:2135) (2282:2282:2282)) - (PORT datad (364:364:364) (385:385:385)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1290:1290:1290) (1360:1360:1360)) - (PORT datab (1193:1193:1193) (1242:1242:1242)) - (PORT datac (172:172:172) (204:204:204)) - (PORT datad (1264:1264:1264) (1365:1365:1365)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~22) - (DELAY - (ABSOLUTE - (PORT dataa (659:659:659) (717:717:717)) - (PORT datab (639:639:639) (661:661:661)) - (PORT datac (180:180:180) (217:217:217)) - (PORT datad (1158:1158:1158) (1203:1203:1203)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~24) - (DELAY - (ABSOLUTE - (PORT dataa (939:939:939) (959:959:959)) - (PORT datab (231:231:231) (282:282:282)) - (PORT datac (629:629:629) (651:651:651)) - (PORT datad (649:649:649) (681:681:681)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla42M3T3_6) - (DELAY - (ABSOLUTE - (PORT dataa (1447:1447:1447) (1493:1493:1493)) - (PORT datab (1229:1229:1229) (1315:1315:1315)) - (PORT datac (680:680:680) (717:717:717)) - (PORT datad (1141:1141:1141) (1161:1161:1161)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~6) - (DELAY - (ABSOLUTE - (PORT dataa (708:708:708) (759:759:759)) - (PORT datab (1141:1141:1141) (1169:1169:1169)) - (PORT datac (1819:1819:1819) (1896:1896:1896)) - (PORT datad (588:588:588) (613:613:613)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal6\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1461:1461:1461) (1560:1560:1560)) - (PORT datab (1137:1137:1137) (1179:1179:1179)) - (PORT datac (1192:1192:1192) (1287:1287:1287)) - (PORT datad (655:655:655) (686:686:686)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1468:1468:1468) (1566:1566:1566)) - (PORT datab (683:683:683) (725:725:725)) - (PORT datac (1193:1193:1193) (1278:1278:1278)) - (PORT datad (1406:1406:1406) (1445:1445:1445)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|M5\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1125:1125:1125) (1173:1173:1173)) - (PORT datab (267:267:267) (350:350:350)) - (PORT datad (1104:1104:1104) (1160:1160:1160)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|M5) - (DELAY - (ABSOLUTE - (PORT clk (1540:1540:1540) (1556:1556:1556)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1596:1596:1596) (1571:1571:1571)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~2) - (DELAY - (ABSOLUTE - (PORT datab (1589:1589:1589) (1719:1719:1719)) - (PORT datac (2606:2606:2606) (2704:2704:2704)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~29) - (DELAY - (ABSOLUTE - (PORT dataa (629:629:629) (665:665:665)) - (PORT datab (931:931:931) (978:978:978)) - (PORT datac (1004:1004:1004) (1061:1061:1061)) - (PORT datad (662:662:662) (691:691:691)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~25) - (DELAY - (ABSOLUTE - (PORT dataa (1946:1946:1946) (2050:2050:2050)) - (PORT datab (687:687:687) (729:729:729)) - (PORT datac (658:658:658) (709:709:709)) - (PORT datad (585:585:585) (615:615:615)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1904:1904:1904) (1999:1999:1999)) - (PORT datab (898:898:898) (961:961:961)) - (PORT datac (193:193:193) (226:226:226)) - (PORT datad (187:187:187) (219:219:219)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1259:1259:1259) (1371:1371:1371)) - (PORT datab (464:464:464) (522:522:522)) - (PORT datac (1696:1696:1696) (1755:1755:1755)) - (PORT datad (268:268:268) (323:323:323)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal52\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1366:1366:1366) (1481:1481:1481)) - (PORT datab (934:934:934) (992:992:992)) - (PORT datac (958:958:958) (990:990:990)) - (PORT datad (1201:1201:1201) (1318:1318:1318)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~14) - (DELAY - (ABSOLUTE - (PORT dataa (972:972:972) (1071:1071:1071)) - (PORT datab (1335:1335:1335) (1360:1360:1360)) - (PORT datac (927:927:927) (1015:1015:1015)) - (PORT datad (1107:1107:1107) (1130:1130:1130)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~8) - (DELAY - (ABSOLUTE - (PORT dataa (636:636:636) (679:679:679)) - (PORT datab (1262:1262:1262) (1301:1301:1301)) - (PORT datac (566:566:566) (573:573:573)) - (PORT datad (1626:1626:1626) (1701:1701:1701)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal24\~0) - (DELAY - (ABSOLUTE - (PORT dataa (708:708:708) (808:808:808)) - (PORT datab (219:219:219) (258:258:258)) - (PORT datac (255:255:255) (343:343:343)) - (PORT datad (881:881:881) (941:941:941)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_pc\~0) - (DELAY - (ABSOLUTE - (PORT dataa (885:885:885) (933:933:933)) - (PORT datab (1109:1109:1109) (1175:1175:1175)) - (PORT datac (1089:1089:1089) (1121:1121:1121)) - (PORT datad (673:673:673) (713:713:713)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_pc\~1) - (DELAY - (ABSOLUTE - (PORT dataa (449:449:449) (492:492:492)) - (PORT datab (1938:1938:1938) (2051:2051:2051)) - (PORT datac (1035:1035:1035) (1084:1084:1084)) - (PORT datad (1561:1561:1561) (1612:1612:1612)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_pc\~2) - (DELAY - (ABSOLUTE - (PORT dataa (920:920:920) (1000:1000:1000)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (895:895:895) (945:945:945)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~17) - (DELAY - (ABSOLUTE - (PORT dataa (637:637:637) (683:683:683)) - (PORT datab (1196:1196:1196) (1213:1213:1213)) - (PORT datac (208:208:208) (248:248:248)) - (PORT datad (624:624:624) (642:642:642)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~6) - (DELAY - (ABSOLUTE - (PORT dataa (421:421:421) (458:458:458)) - (PORT datab (1170:1170:1170) (1201:1201:1201)) - (PORT datac (620:620:620) (684:684:684)) - (PORT datad (1113:1113:1113) (1142:1142:1142)) + (PORT dataa (1561:1561:1561) (1693:1693:1693)) + (PORT datab (1494:1494:1494) (1548:1548:1548)) + (PORT datac (1378:1378:1378) (1556:1556:1556)) + (PORT datad (1509:1509:1509) (1635:1635:1635)) (IOPATH dataa combout (300:300:300) (308:308:308)) (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -2617,6010 +1388,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal11\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1626:1626:1626) (1717:1717:1717)) - (PORT datab (1533:1533:1533) (1584:1584:1584)) - (PORT datac (1703:1703:1703) (1827:1827:1827)) - (PORT datad (1490:1490:1490) (1625:1625:1625)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal10\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1624:1624:1624) (1719:1719:1719)) - (PORT datab (1534:1534:1534) (1581:1581:1581)) - (PORT datac (1711:1711:1711) (1826:1826:1826)) - (PORT datad (1494:1494:1494) (1620:1620:1620)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1688:1688:1688) (1727:1727:1727)) - (PORT datab (1470:1470:1470) (1564:1564:1564)) - (PORT datac (2563:2563:2563) (2660:2660:2660)) - (PORT datad (1901:1901:1901) (2013:2013:2013)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~4) - (DELAY - (ABSOLUTE - (PORT dataa (637:637:637) (682:682:682)) - (PORT datab (1262:1262:1262) (1302:1302:1302)) - (PORT datac (1116:1116:1116) (1135:1135:1135)) - (PORT datad (553:553:553) (571:571:571)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1260:1260:1260) (1370:1370:1370)) - (PORT datab (464:464:464) (521:521:521)) - (PORT datac (1697:1697:1697) (1755:1755:1755)) - (PORT datad (267:267:267) (323:323:323)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1107:1107:1107) (1153:1153:1153)) - (PORT datab (1145:1145:1145) (1184:1184:1184)) - (PORT datac (548:548:548) (563:563:563)) - (PORT datad (609:609:609) (634:634:634)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~9) - (DELAY - (ABSOLUTE - (PORT dataa (291:291:291) (358:358:358)) - (PORT datab (465:465:465) (519:519:519)) - (PORT datac (191:191:191) (223:223:223)) - (PORT datad (1368:1368:1368) (1479:1479:1479)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal46\~0) - (DELAY - (ABSOLUTE - (PORT dataa (286:286:286) (382:382:382)) - (PORT datab (952:952:952) (1018:1018:1018)) - (PORT datac (903:903:903) (963:963:963)) - (PORT datad (1192:1192:1192) (1312:1312:1312)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1252:1252:1252) (1367:1367:1367)) - (PORT datab (866:866:866) (891:891:891)) - (PORT datac (1704:1704:1704) (1755:1755:1755)) - (PORT datad (263:263:263) (316:316:316)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~17) - (DELAY - (ABSOLUTE - (PORT dataa (2111:2111:2111) (2254:2254:2254)) - (PORT datab (2048:2048:2048) (2161:2161:2161)) - (PORT datac (986:986:986) (1043:1043:1043)) - (PORT datad (1210:1210:1210) (1253:1253:1253)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1380:1380:1380) (1424:1424:1424)) - (PORT datab (1059:1059:1059) (1143:1143:1143)) - (PORT datac (754:754:754) (762:762:762)) - (PORT datad (1235:1235:1235) (1269:1269:1269)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (982:982:982) (1061:1061:1061)) - (PORT datac (1148:1148:1148) (1203:1203:1203)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (296:296:296) (369:369:369)) - (PORT datab (465:465:465) (518:518:518)) - (PORT datac (1197:1197:1197) (1289:1289:1289)) - (PORT datad (1363:1363:1363) (1476:1476:1476)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1126:1126:1126) (1248:1248:1248)) - (PORT datab (2197:2197:2197) (2296:2296:2296)) - (PORT datac (1334:1334:1334) (1445:1445:1445)) - (PORT datad (959:959:959) (1022:1022:1022)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1792:1792:1792) (1883:1883:1883)) - (PORT datab (1288:1288:1288) (1337:1337:1337)) - (PORT datac (1377:1377:1377) (1384:1384:1384)) - (PORT datad (883:883:883) (905:905:905)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~8) - (DELAY - (ABSOLUTE - (PORT dataa (614:614:614) (635:635:635)) - (PORT datac (550:550:550) (559:559:559)) - (PORT datad (1232:1232:1232) (1290:1290:1290)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~18) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (242:242:242)) - (PORT datab (219:219:219) (257:257:257)) - (PORT datac (172:172:172) (204:204:204)) - (PORT datad (196:196:196) (221:221:221)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~19) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (207:207:207) (249:249:249)) - (PORT datac (861:861:861) (876:876:876)) - (PORT datad (848:848:848) (889:889:889)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~16) - (DELAY - (ABSOLUTE - (PORT datac (2061:2061:2061) (2184:2184:2184)) - (PORT datad (959:959:959) (1014:1014:1014)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~36) - (DELAY - (ABSOLUTE - (PORT dataa (1615:1615:1615) (1714:1714:1714)) - (PORT datab (1532:1532:1532) (1580:1580:1580)) - (PORT datac (1706:1706:1706) (1825:1825:1825)) - (PORT datad (1489:1489:1489) (1621:1621:1621)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~9) - (DELAY - (ABSOLUTE - (PORT dataa (682:682:682) (717:717:717)) - (PORT datab (1494:1494:1494) (1553:1553:1553)) - (PORT datac (1138:1138:1138) (1205:1205:1205)) - (PORT datad (1383:1383:1383) (1432:1432:1432)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~44) - (DELAY - (ABSOLUTE - (PORT dataa (2148:2148:2148) (2325:2325:2325)) - (PORT datab (675:675:675) (746:746:746)) - (PORT datac (1715:1715:1715) (1794:1794:1794)) - (PORT datad (205:205:205) (235:235:235)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1299:1299:1299) (1399:1399:1399)) - (PORT datad (2046:2046:2046) (2211:2211:2211)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~6) - (DELAY - (ABSOLUTE - (PORT dataa (919:919:919) (999:999:999)) - (PORT datab (454:454:454) (482:482:482)) - (PORT datac (408:408:408) (448:448:448)) - (PORT datad (1564:1564:1564) (1622:1622:1622)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~7) - (DELAY - (ABSOLUTE - (PORT dataa (629:629:629) (651:651:651)) - (PORT datab (1155:1155:1155) (1200:1200:1200)) - (PORT datac (1451:1451:1451) (1502:1502:1502)) - (PORT datad (337:337:337) (358:358:358)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~7) - (DELAY - (ABSOLUTE - (PORT datac (1520:1520:1520) (1613:1613:1613)) - (PORT datad (1159:1159:1159) (1225:1225:1225)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1261:1261:1261) (1371:1371:1371)) - (PORT datab (865:865:865) (889:889:889)) - (PORT datac (1688:1688:1688) (1749:1749:1749)) - (PORT datad (267:267:267) (323:323:323)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1260:1260:1260) (1371:1371:1371)) - (PORT datab (465:465:465) (519:519:519)) - (PORT datac (1689:1689:1689) (1752:1752:1752)) - (PORT datad (268:268:268) (320:320:320)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1420:1420:1420) (1451:1451:1451)) - (PORT datab (1101:1101:1101) (1122:1122:1122)) - (PORT datac (1072:1072:1072) (1084:1084:1084)) - (PORT datad (939:939:939) (973:973:973)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla27npla34M1T1_3) - (DELAY - (ABSOLUTE - (PORT dataa (683:683:683) (719:719:719)) - (PORT datab (1167:1167:1167) (1240:1240:1240)) - (PORT datac (1455:1455:1455) (1509:1509:1509)) - (PORT datad (1468:1468:1468) (1520:1520:1520)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~8) - (DELAY - (ABSOLUTE - (PORT dataa (391:391:391) (420:420:420)) - (PORT datab (200:200:200) (239:239:239)) - (PORT datac (623:623:623) (666:666:666)) - (PORT datad (189:189:189) (220:220:220)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~9) - (DELAY - (ABSOLUTE - (PORT dataa (566:566:566) (593:593:593)) - (PORT datab (860:860:860) (886:886:886)) - (PORT datac (854:854:854) (889:889:889)) - (PORT datad (805:805:805) (822:822:822)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1150:1150:1150) (1163:1163:1163)) - (PORT datab (196:196:196) (235:235:235)) - (PORT datac (186:186:186) (228:228:228)) - (PORT datad (179:179:179) (206:206:206)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~7) - (DELAY - (ABSOLUTE - (PORT dataa (351:351:351) (483:483:483)) - (PORT datab (1218:1218:1218) (1272:1272:1272)) - (PORT datac (679:679:679) (709:709:709)) - (PORT datad (1295:1295:1295) (1387:1387:1387)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~8) - (DELAY - (ABSOLUTE - (PORT datab (2915:2915:2915) (3094:3094:3094)) - (PORT datac (2028:2028:2028) (2098:2098:2098)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla21M2T2_3) - (DELAY - (ABSOLUTE - (PORT dataa (1889:1889:1889) (1934:1934:1934)) - (PORT datab (2084:2084:2084) (2215:2215:2215)) - (PORT datac (1111:1111:1111) (1144:1144:1144)) - (PORT datad (208:208:208) (238:238:238)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_ixy_dT4_2) - (DELAY - (ABSOLUTE - (PORT datac (1234:1234:1234) (1326:1326:1326)) - (PORT datad (625:625:625) (665:665:665)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~39) - (DELAY - (ABSOLUTE - (PORT dataa (1182:1182:1182) (1232:1232:1232)) - (PORT datab (906:906:906) (961:961:961)) - (PORT datac (2032:2032:2032) (2056:2056:2056)) - (PORT datad (1479:1479:1479) (1541:1541:1541)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla26M1T4_3) - (DELAY - (ABSOLUTE - (PORT dataa (1057:1057:1057) (1151:1151:1151)) - (PORT datab (2381:2381:2381) (2493:2493:2493)) - (PORT datad (2113:2113:2113) (2257:2257:2257)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1487:1487:1487) (1536:1536:1536)) - (PORT datab (1011:1011:1011) (1078:1078:1078)) - (PORT datac (900:900:900) (921:921:921)) - (PORT datad (1172:1172:1172) (1187:1187:1187)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1450:1450:1450) (1479:1479:1479)) - (PORT datab (1137:1137:1137) (1178:1178:1178)) - (PORT datac (337:337:337) (365:365:365)) - (PORT datad (1137:1137:1137) (1159:1159:1159)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~38) - (DELAY - (ABSOLUTE - (PORT dataa (373:373:373) (412:412:412)) - (PORT datab (1088:1088:1088) (1114:1114:1114)) - (PORT datac (1575:1575:1575) (1617:1617:1617)) - (PORT datad (811:811:811) (828:828:828)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_zero) - (DELAY - (ABSOLUTE - (PORT dataa (1142:1142:1142) (1206:1206:1206)) - (PORT datab (1169:1169:1169) (1204:1204:1204)) - (PORT datac (835:835:835) (863:863:863)) - (PORT datad (800:800:800) (827:827:827)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1179:1179:1179) (1212:1212:1212)) - (PORT datab (286:286:286) (351:351:351)) - (PORT datac (253:253:253) (312:312:312)) - (PORT datad (252:252:252) (297:297:297)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~14) - (DELAY - (ABSOLUTE - (PORT datac (948:948:948) (1024:1024:1024)) - (PORT datad (2023:2023:2023) (2146:2146:2146)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (856:856:856) (897:897:897)) - (PORT datab (1012:1012:1012) (1081:1081:1081)) - (PORT datac (1223:1223:1223) (1284:1284:1284)) - (PORT datad (1171:1171:1171) (1183:1183:1183)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~1) - (DELAY - (ABSOLUTE - (PORT datab (219:219:219) (257:257:257)) - (PORT datad (194:194:194) (219:219:219)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1179:1179:1179) (1230:1230:1230)) - (PORT datab (1013:1013:1013) (1082:1082:1082)) - (PORT datac (2030:2030:2030) (2056:2056:2056)) - (PORT datad (1479:1479:1479) (1543:1543:1543)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~30) - (DELAY - (ABSOLUTE - (PORT dataa (1303:1303:1303) (1377:1377:1377)) - (PORT datab (1170:1170:1170) (1231:1231:1231)) - (PORT datac (840:840:840) (887:887:887)) - (PORT datad (1322:1322:1322) (1434:1434:1434)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~29) - (DELAY - (ABSOLUTE - (PORT dataa (918:918:918) (984:984:984)) - (PORT datab (941:941:941) (1009:1009:1009)) - (PORT datac (1210:1210:1210) (1289:1289:1289)) - (PORT datad (658:658:658) (688:688:688)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~31) - (DELAY - (ABSOLUTE - (PORT dataa (1353:1353:1353) (1482:1482:1482)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (382:382:382) (410:410:410)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal69\~0) - (DELAY - (ABSOLUTE - (PORT dataa (873:873:873) (968:968:968)) - (PORT datab (1718:1718:1718) (1808:1808:1808)) - (PORT datac (1144:1144:1144) (1148:1148:1148)) - (PORT datad (653:653:653) (693:693:693)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal1\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1201:1201:1201) (1290:1290:1290)) - (PORT datad (1198:1198:1198) (1259:1259:1259)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1009:1009:1009) (1044:1044:1044)) - (PORT datab (2023:2023:2023) (2060:2060:2060)) - (PORT datac (1148:1148:1148) (1153:1153:1153)) - (PORT datad (650:650:650) (690:690:690)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1758:1758:1758) (1876:1876:1876)) - (PORT datab (915:915:915) (977:977:977)) - (PORT datad (216:216:216) (242:242:242)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal56\~0) - (DELAY - (ABSOLUTE - (PORT dataa (670:670:670) (725:725:725)) - (PORT datab (1178:1178:1178) (1215:1215:1215)) - (PORT datac (934:934:934) (1029:1029:1029)) - (PORT datad (903:903:903) (950:950:950)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1467:1467:1467) (1537:1537:1537)) - (PORT datab (1228:1228:1228) (1312:1312:1312)) - (PORT datac (1432:1432:1432) (1520:1520:1520)) - (PORT datad (820:820:820) (833:833:833)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~2) - (DELAY - (ABSOLUTE - (PORT dataa (822:822:822) (845:845:845)) - (PORT datab (854:854:854) (887:887:887)) - (PORT datad (673:673:673) (693:693:693)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~16) - (DELAY - (ABSOLUTE - (PORT dataa (2011:2011:2011) (2114:2114:2114)) - (PORT datab (2111:2111:2111) (2221:2221:2221)) - (PORT datac (547:547:547) (569:569:569)) - (PORT datad (1739:1739:1739) (1782:1782:1782)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~4) - (DELAY - (ABSOLUTE - (PORT dataa (859:859:859) (882:882:882)) - (PORT datab (952:952:952) (1011:1011:1011)) - (PORT datac (178:178:178) (213:213:213)) - (PORT datad (1472:1472:1472) (1533:1533:1533)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~5) - (DELAY - (ABSOLUTE - (PORT datac (1162:1162:1162) (1174:1174:1174)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1237:1237:1237) (1303:1303:1303)) - (PORT datab (992:992:992) (1101:1101:1101)) - (PORT datac (657:657:657) (716:716:716)) - (PORT datad (1239:1239:1239) (1323:1323:1323)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~15) - (DELAY - (ABSOLUTE - (PORT datab (1082:1082:1082) (1193:1193:1193)) - (PORT datac (1465:1465:1465) (1548:1548:1548)) - (PORT datad (2348:2348:2348) (2497:2497:2497)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~8) - (DELAY - (ABSOLUTE - (PORT dataa (669:669:669) (726:726:726)) - (PORT datab (1800:1800:1800) (1830:1830:1830)) - (PORT datac (988:988:988) (1048:1048:1048)) - (PORT datad (1210:1210:1210) (1257:1257:1257)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1026:1026:1026) (1084:1084:1084)) - (PORT datab (1248:1248:1248) (1292:1292:1292)) - (PORT datac (1097:1097:1097) (1128:1128:1128)) - (PORT datad (183:183:183) (212:212:212)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~3) - (DELAY - (ABSOLUTE - (PORT dataa (942:942:942) (983:983:983)) - (PORT datab (1091:1091:1091) (1163:1163:1163)) - (PORT datac (985:985:985) (1050:1050:1050)) - (PORT datad (1157:1157:1157) (1206:1206:1206)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1013:1013:1013) (1086:1086:1086)) - (PORT datab (197:197:197) (234:234:234)) - (PORT datac (1253:1253:1253) (1320:1320:1320)) - (PORT datad (1054:1054:1054) (1123:1123:1123)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4) - (DELAY - (ABSOLUTE - (PORT datab (1514:1514:1514) (1650:1650:1650)) - (PORT datac (1504:1504:1504) (1617:1617:1617)) - (PORT datad (1306:1306:1306) (1325:1325:1325)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~10) - (DELAY - (ABSOLUTE - (PORT dataa (794:794:794) (831:831:831)) - (PORT datab (860:860:860) (870:870:870)) - (PORT datac (1242:1242:1242) (1262:1262:1262)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1415:1415:1415) (1454:1454:1454)) - (PORT datab (2084:2084:2084) (2114:2114:2114)) - (PORT datac (835:835:835) (859:859:859)) - (PORT datad (788:788:788) (798:798:798)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal48\~0) - (DELAY - (ABSOLUTE - (PORT dataa (873:873:873) (968:968:968)) - (PORT datab (1718:1718:1718) (1807:1807:1807)) - (PORT datac (1144:1144:1144) (1148:1148:1148)) - (PORT datad (654:654:654) (693:693:693)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf2_we) - (DELAY - (ABSOLUTE - (PORT dataa (922:922:922) (998:998:998)) - (PORT datab (900:900:900) (985:985:985)) - (PORT datac (966:966:966) (1015:1015:1015)) - (PORT datad (1295:1295:1295) (1365:1365:1365)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~41) - (DELAY - (ABSOLUTE - (PORT dataa (1246:1246:1246) (1336:1336:1336)) - (PORT datab (1005:1005:1005) (1056:1056:1056)) - (PORT datac (209:209:209) (248:248:248)) - (PORT datad (1195:1195:1195) (1244:1244:1244)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1847:1847:1847) (1960:1960:1960)) - (PORT datab (1294:1294:1294) (1397:1397:1397)) - (PORT datac (2030:2030:2030) (2118:2118:2118)) - (PORT datad (836:836:836) (843:843:843)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1215:1215:1215) (1251:1251:1251)) - (PORT datab (1013:1013:1013) (1076:1076:1076)) - (PORT datac (621:621:621) (659:659:659)) - (PORT datad (1176:1176:1176) (1188:1188:1188)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~19) - (DELAY - (ABSOLUTE - (PORT dataa (886:886:886) (945:945:945)) - (PORT datab (1062:1062:1062) (1128:1128:1128)) - (PORT datac (579:579:579) (602:602:602)) - (PORT datad (1089:1089:1089) (1104:1104:1104)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_iorw\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1618:1618:1618) (1711:1711:1711)) - (PORT datab (1527:1527:1527) (1658:1658:1658)) - (PORT datac (1710:1710:1710) (1825:1825:1825)) - (PORT datad (1448:1448:1448) (1496:1496:1496)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1670:1670:1670) (1753:1753:1753)) - (PORT datab (1528:1528:1528) (1617:1617:1617)) - (PORT datac (966:966:966) (1014:1014:1014)) - (PORT datad (1159:1159:1159) (1218:1218:1218)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~20) - (DELAY - (ABSOLUTE - (PORT dataa (587:587:587) (622:622:622)) - (PORT datab (923:923:923) (944:944:944)) - (PORT datac (969:969:969) (1018:1018:1018)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1638:1638:1638) (1764:1764:1764)) - (PORT datab (1075:1075:1075) (1149:1149:1149)) - (PORT datac (1806:1806:1806) (1948:1948:1948)) - (PORT datad (942:942:942) (974:974:974)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1241:1241:1241) (1294:1294:1294)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (972:972:972) (992:992:992)) - (PORT datad (902:902:902) (955:955:955)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1348:1348:1348) (1398:1398:1398)) - (PORT datab (1002:1002:1002) (1057:1057:1057)) - (PORT datac (575:575:575) (596:596:596)) - (PORT datad (637:637:637) (681:681:681)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal20\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1988:1988:1988) (2128:2128:2128)) - (PORT datab (1534:1534:1534) (1632:1632:1632)) - (PORT datac (227:227:227) (272:272:272)) - (PORT datad (1108:1108:1108) (1149:1149:1149)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal68\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1617:1617:1617) (1711:1711:1711)) - (PORT datab (1528:1528:1528) (1657:1657:1657)) - (PORT datac (1709:1709:1709) (1824:1824:1824)) - (PORT datad (1448:1448:1448) (1496:1496:1496)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~14) - (DELAY - (ABSOLUTE - (PORT dataa (922:922:922) (983:983:983)) - (PORT datab (1427:1427:1427) (1510:1510:1510)) - (PORT datac (1333:1333:1333) (1448:1448:1448)) - (PORT datad (1550:1550:1550) (1659:1659:1659)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~13) - (DELAY - (ABSOLUTE - (PORT dataa (699:699:699) (721:721:721)) - (PORT datab (1637:1637:1637) (1642:1642:1642)) - (PORT datac (1298:1298:1298) (1314:1314:1314)) - (PORT datad (1443:1443:1443) (1563:1563:1563)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1580:1580:1580) (1703:1703:1703)) - (PORT datab (1365:1365:1365) (1479:1479:1479)) - (PORT datac (1152:1152:1152) (1186:1186:1186)) - (PORT datad (832:832:832) (834:834:834)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~11) - (DELAY - (ABSOLUTE - (PORT dataa (672:672:672) (729:729:729)) - (PORT datab (995:995:995) (1057:1057:1057)) - (PORT datac (1074:1074:1074) (1196:1196:1196)) - (PORT datad (173:173:173) (197:197:197)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~11) - (DELAY - (ABSOLUTE - (PORT dataa (2265:2265:2265) (2414:2414:2414)) - (PORT datab (848:848:848) (886:886:886)) - (PORT datac (2113:2113:2113) (2221:2221:2221)) - (PORT datad (669:669:669) (694:694:694)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~10) - (DELAY - (ABSOLUTE - (PORT dataa (920:920:920) (996:996:996)) - (PORT datab (1005:1005:1005) (1060:1060:1060)) - (PORT datac (1413:1413:1413) (1487:1487:1487)) - (PORT datad (1522:1522:1522) (1622:1622:1622)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~8) - (DELAY - (ABSOLUTE - (PORT dataa (647:647:647) (684:684:684)) - (PORT datab (440:440:440) (477:477:477)) - (PORT datac (202:202:202) (238:238:238)) - (PORT datad (1428:1428:1428) (1432:1432:1432)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~9) - (DELAY - (ABSOLUTE - (PORT dataa (630:630:630) (662:662:662)) - (PORT datab (1001:1001:1001) (1053:1053:1053)) - (PORT datac (870:870:870) (914:914:914)) - (PORT datad (809:809:809) (854:854:854)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~12) - (DELAY - (ABSOLUTE - (PORT dataa (371:371:371) (392:392:392)) - (PORT datab (331:331:331) (360:360:360)) - (PORT datac (170:170:170) (202:202:202)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~11) - (DELAY - (ABSOLUTE - (PORT dataa (222:222:222) (266:266:266)) - (PORT datab (228:228:228) (271:271:271)) - (PORT datac (201:201:201) (238:238:238)) - (PORT datad (202:202:202) (231:231:231)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~12) - (DELAY - (ABSOLUTE - (PORT dataa (637:637:637) (657:657:657)) - (PORT datab (1415:1415:1415) (1491:1491:1491)) - (PORT datac (638:638:638) (658:658:658)) - (PORT datad (1624:1624:1624) (1706:1706:1706)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~6) - (DELAY - (ABSOLUTE - (PORT dataa (668:668:668) (702:702:702)) - (PORT datab (995:995:995) (1056:1056:1056)) - (PORT datac (1075:1075:1075) (1194:1194:1194)) - (PORT datad (2306:2306:2306) (2342:2342:2342)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~7) - (DELAY - (ABSOLUTE - (PORT dataa (921:921:921) (980:980:980)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (346:346:346) (371:371:371)) - (PORT datad (2307:2307:2307) (2344:2344:2344)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~4) - (DELAY - (ABSOLUTE - (PORT datab (1060:1060:1060) (1178:1178:1178)) - (PORT datac (1452:1452:1452) (1530:1530:1530)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1391:1391:1391) (1453:1453:1453)) - (PORT datab (942:942:942) (993:993:993)) - (PORT datac (1045:1045:1045) (1115:1115:1115)) - (PORT datad (1421:1421:1421) (1470:1470:1470)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (969:969:969) (1009:1009:1009)) - (PORT datab (1445:1445:1445) (1500:1500:1500)) - (PORT datac (972:972:972) (995:995:995)) - (PORT datad (196:196:196) (222:222:222)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1112:1112:1112) (1123:1123:1123)) - (PORT datab (1196:1196:1196) (1246:1246:1246)) - (PORT datac (663:663:663) (712:712:712)) - (PORT datad (879:879:879) (931:931:931)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~13) - (DELAY - (ABSOLUTE - (PORT dataa (604:604:604) (616:616:616)) - (PORT datac (573:573:573) (593:593:593)) - (PORT datad (531:531:531) (543:543:543)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~14) - (DELAY - (ABSOLUTE - (PORT dataa (248:248:248) (303:303:303)) - (PORT datab (1244:1244:1244) (1269:1269:1269)) - (PORT datac (1174:1174:1174) (1214:1214:1214)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~15) - (DELAY - (ABSOLUTE - (PORT dataa (879:879:879) (925:925:925)) - (PORT datab (852:852:852) (865:865:865)) - (PORT datac (342:342:342) (367:367:367)) - (PORT datad (195:195:195) (221:221:221)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_66_oe\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1987:1987:1987) (2132:2132:2132)) - (PORT datab (903:903:903) (955:955:955)) - (PORT datac (224:224:224) (269:269:269)) - (PORT datad (1402:1402:1402) (1466:1466:1466)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel_pla11M1T1_11) - (DELAY - (ABSOLUTE - (PORT dataa (1798:1798:1798) (1933:1933:1933)) - (PORT datab (1613:1613:1613) (1726:1726:1726)) - (PORT datad (1409:1409:1409) (1475:1475:1475)) - (IOPATH dataa combout (301:301:301) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero\~5) - (DELAY - (ABSOLUTE - (PORT dataa (2050:2050:2050) (2089:2089:2089)) - (PORT datab (946:946:946) (1023:1023:1023)) - (PORT datac (1099:1099:1099) (1158:1158:1158)) - (PORT datad (914:914:914) (1002:1002:1002)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1335:1335:1335) (1354:1354:1354)) - (PORT datab (1166:1166:1166) (1239:1239:1239)) - (PORT datac (1485:1485:1485) (1514:1514:1514)) - (PORT datad (1468:1468:1468) (1520:1520:1520)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero) - (DELAY - (ABSOLUTE - (PORT dataa (1144:1144:1144) (1189:1189:1189)) - (PORT datab (222:222:222) (269:269:269)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (836:836:836) (868:868:868)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[2\]) - (DELAY - (ABSOLUTE - (PORT datab (963:963:963) (1010:1010:1010)) - (PORT datac (601:601:601) (607:607:607)) - (PORT datad (676:676:676) (718:718:718)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|ena\~0) - (DELAY - (ABSOLUTE - (PORT datac (928:928:928) (973:973:973)) - (PORT datad (680:680:680) (720:720:720)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_high\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_lq) - (DELAY - (ABSOLUTE - (PORT dataa (1003:1003:1003) (1064:1064:1064)) - (PORT datab (717:717:717) (774:774:774)) - (PORT datac (903:903:903) (944:944:944)) - (PORT datad (1740:1740:1740) (1858:1858:1858)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1494:1494:1494) (1600:1600:1600)) - (PORT datab (1475:1475:1475) (1582:1582:1582)) - (PORT datac (1847:1847:1847) (1916:1916:1916)) - (PORT datad (402:402:402) (439:439:439)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1219:1219:1219) (1306:1306:1306)) - (PORT datac (943:943:943) (1021:1021:1021)) - (PORT datad (1208:1208:1208) (1293:1293:1293)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1221:1221:1221) (1285:1285:1285)) - (PORT datab (1430:1430:1430) (1456:1456:1456)) - (PORT datac (1096:1096:1096) (1116:1116:1116)) - (PORT datad (1325:1325:1325) (1332:1332:1332)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~22) - (DELAY - (ABSOLUTE - (PORT datab (934:934:934) (968:968:968)) - (PORT datac (531:531:531) (544:544:544)) - (PORT datad (171:171:171) (196:196:196)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1001:1001:1001) (1063:1063:1063)) - (PORT datab (717:717:717) (773:773:773)) - (PORT datac (901:901:901) (942:942:942)) - (PORT datad (1738:1738:1738) (1857:1857:1857)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1357:1357:1357) (1397:1397:1397)) - (PORT datab (917:917:917) (962:962:962)) - (PORT datad (619:619:619) (654:654:654)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datad 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(242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~34) - (DELAY - (ABSOLUTE - (PORT dataa (1437:1437:1437) (1451:1451:1451)) - (PORT datab (1439:1439:1439) (1497:1497:1497)) - (PORT datac (974:974:974) (995:995:995)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~35) - (DELAY - (ABSOLUTE - (PORT dataa (1814:1814:1814) (1850:1850:1850)) - (PORT datab (1003:1003:1003) (1029:1029:1029)) - (PORT datac (315:315:315) (336:336:336)) - (PORT datad (172:172:172) (198:198:198)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~36) - (DELAY - (ABSOLUTE - (PORT dataa (673:673:673) (706:706:706)) - (PORT datab (608:608:608) (621:621:621)) - (PORT datac (813:813:813) (840:840:840)) - (PORT datad (337:337:337) (356:356:356)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~43) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (242:242:242)) - (PORT datab (198:198:198) (238:238:238)) - (PORT datac (170:170:170) (204:204:204)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_lo\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1292:1292:1292) (1357:1357:1357)) - (PORT datab (986:986:986) (1070:1070:1070)) - (PORT datac (1073:1073:1073) (1153:1153:1153)) - (PORT datad (966:966:966) (1077:1077:1077)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1463:1463:1463) (1478:1478:1478)) - (PORT datab (1379:1379:1379) (1398:1398:1398)) - (PORT datac (1618:1618:1618) (1662:1662:1662)) - (PORT datad (1263:1263:1263) (1327:1327:1327)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla57M1T4_4) - (DELAY - (ABSOLUTE - (PORT dataa (1202:1202:1202) (1231:1231:1231)) - (PORT datab (1048:1048:1048) (1149:1149:1149)) - (PORT datad (1348:1348:1348) (1490:1490:1490)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_oe\~1) - (DELAY - (ABSOLUTE - (PORT dataa (681:681:681) (736:736:736)) - (PORT datab (1001:1001:1001) (1033:1033:1033)) - (PORT datac (553:553:553) (568:568:568)) - (PORT datad (222:222:222) (249:249:249)) - (IOPATH dataa combout (339:339:339) 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(950:950:950)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal11\~1) - (DELAY - (ABSOLUTE - (PORT datac (1589:1589:1589) (1676:1676:1676)) - (PORT datad (1494:1494:1494) (1621:1621:1621)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla12M3T1_2) - (DELAY - (ABSOLUTE - (PORT dataa (959:959:959) (1016:1016:1016)) - (PORT datab (1194:1194:1194) (1223:1223:1223)) - (PORT datac (1942:1942:1942) (2000:2000:2000)) - (PORT datad (641:641:641) (693:693:693)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~10) - (DELAY - (ABSOLUTE - (PORT dataa (198:198:198) (241:241:241)) - (PORT datab (627:627:627) (662:662:662)) - (PORT datac (1683:1683:1683) (1789:1789:1789)) - (PORT datad (633:633:633) (651:651:651)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1500:1500:1500) (1575:1575:1575)) - (PORT datab (362:362:362) (397:397:397)) - (PORT datac (2091:2091:2091) (2220:2220:2220)) - (PORT datad (590:590:590) (607:607:607)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla77M1T1_3) - (DELAY - (ABSOLUTE - (PORT dataa (736:736:736) (800:800:800)) - (PORT datab (947:947:947) (1025:1025:1025)) - (PORT datac (1098:1098:1098) (1158:1158:1158)) - (PORT datad (911:911:911) (1001:1001:1001)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel_pla82M1T1_16) - (DELAY - (ABSOLUTE - (PORT dataa (1465:1465:1465) (1539:1539:1539)) - (PORT datab (1227:1227:1227) (1318:1318:1318)) - (PORT datac (1459:1459:1459) (1517:1517:1517)) - (PORT datad (1138:1138:1138) (1159:1159:1159)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1840:1840:1840) (1939:1939:1939)) - (PORT datab (2068:2068:2068) (2187:2187:2187)) - (PORT datac (1327:1327:1327) (1336:1336:1336)) - (PORT datad (2013:2013:2013) (2125:2125:2125)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1112:1112:1112) (1215:1215:1215)) - (PORT datab (653:653:653) (674:674:674)) - (PORT datac (1214:1214:1214) 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(130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~25) - (DELAY - (ABSOLUTE - (PORT dataa (1025:1025:1025) (1056:1056:1056)) - (PORT datab (1039:1039:1039) (1096:1096:1096)) - (PORT datac (1052:1052:1052) (1117:1117:1117)) - (PORT datad (625:625:625) (651:651:651)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1581:1581:1581) (1726:1726:1726)) - (PORT datab (205:205:205) (247:247:247)) - (PORT datac (1053:1053:1053) (1117:1117:1117)) - (PORT datad (1795:1795:1795) (1930:1930:1930)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1219:1219:1219) (1272:1272:1272)) - (PORT datab (689:689:689) (706:706:706)) - (PORT datac (1267:1267:1267) (1395:1395:1395)) - (PORT datad (1570:1570:1570) (1720:1720:1720)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~48) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (265:265:265)) - (PORT datab (214:214:214) (259:259:259)) - (PORT datac (1265:1265:1265) (1395:1395:1395)) - (PORT datad (1573:1573:1573) (1723:1723:1723)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1230:1230:1230) (1277:1277:1277)) - (PORT datab (1647:1647:1647) (1673:1673:1673)) - (PORT datac (777:777:777) (786:786:786)) - (PORT datad (581:581:581) (600:600:600)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (635:635:635) (652:652:652)) - (PORT datab (656:656:656) (711:711:711)) - (PORT datac (680:680:680) (730:730:730)) - (PORT datad (800:800:800) (871:871:871)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1001:1001:1001) (1087:1087:1087)) - (PORT datab (1683:1683:1683) (1741:1741:1741)) - (PORT datac (1582:1582:1582) (1690:1690:1690)) - (PORT datad (964:964:964) (1004:1004:1004)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1288:1288:1288) (1342:1342:1342)) - (PORT datab (935:935:935) (949:949:949)) - (PORT datac (978:978:978) (1043:1043:1043)) - (PORT datad (1176:1176:1176) (1188:1188:1188)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~6) - (DELAY - (ABSOLUTE - (PORT dataa (355:355:355) (390:390:390)) - (PORT datab (1476:1476:1476) (1506:1506:1506)) - (PORT datac (1080:1080:1080) (1084:1084:1084)) - (PORT datad (1360:1360:1360) (1375:1375:1375)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~10) - (DELAY - (ABSOLUTE - (PORT dataa (357:357:357) (392:392:392)) - (PORT datab (238:238:238) (276:276:276)) - (PORT datac (1044:1044:1044) (1080:1080:1080)) - (PORT datad (1386:1386:1386) (1428:1428:1428)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla21M2T3_4) - (DELAY - (ABSOLUTE - (PORT dataa (869:869:869) (907:907:907)) - (PORT datab (364:364:364) (400:400:400)) - (PORT datac (656:656:656) (701:701:701)) - (PORT datad (837:837:837) (878:878:878)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~7) - (DELAY - (ABSOLUTE - (PORT dataa (714:714:714) (810:810:810)) - (PORT datab (933:933:933) (988:988:988)) - (PORT datac (981:981:981) (1058:1058:1058)) - (PORT datad (194:194:194) (218:218:218)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1441:1441:1441) (1552:1552:1552)) - (PORT datab (614:614:614) (644:644:644)) - (PORT datac (1197:1197:1197) (1258:1258:1258)) - (PORT datad (844:844:844) (855:855:855)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (229:229:229) (275:275:275)) - (PORT datab (208:208:208) (250:250:250)) - (PORT datac (588:588:588) (608:608:608)) - (PORT datad (876:876:876) (896:896:896)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1212:1212:1212) (1250:1250:1250)) - (PORT datab (965:965:965) (1013:1013:1013)) - (PORT datac (1049:1049:1049) (1111:1111:1111)) - (PORT datad (1444:1444:1444) (1477:1477:1477)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1082:1082:1082) (1153:1153:1153)) - (PORT datab (970:970:970) (1019:1019:1019)) - (PORT datac (308:308:308) (334:334:334)) - (PORT datad (628:628:628) (654:654:654)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1024:1024:1024) (1085:1085:1085)) - (PORT datab (1386:1386:1386) (1414:1414:1414)) - (PORT datac (1180:1180:1180) (1211:1211:1211)) - (PORT datad (1209:1209:1209) (1252:1252:1252)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~5) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (255:255:255)) - (PORT datab (1246:1246:1246) (1296:1296:1296)) - (PORT datac (984:984:984) (1048:1048:1048)) - (PORT datad (625:625:625) (654:654:654)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla20M1T5_5) - (DELAY - (ABSOLUTE - (PORT dataa (873:873:873) (910:910:910)) - (PORT datab (1428:1428:1428) (1466:1466:1466)) - (PORT datac (1688:1688:1688) (1726:1726:1726)) - (PORT datad (2057:2057:2057) (2190:2190:2190)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (613:613:613) (642:642:642)) - (PORT datab (208:208:208) (250:250:250)) - (PORT datac (1398:1398:1398) (1422:1422:1422)) - (PORT datad (1424:1424:1424) (1462:1462:1462)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1803:1803:1803) (1945:1945:1945)) - (PORT datab (847:847:847) (858:858:858)) - (PORT datac (838:838:838) (869:869:869)) - (PORT datad (2056:2056:2056) (2191:2191:2191)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~1) - (DELAY - (ABSOLUTE - (PORT dataa (825:825:825) (847:847:847)) - (PORT datab (783:783:783) (809:809:809)) - (PORT datac (170:170:170) (202:202:202)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~2) - (DELAY - (ABSOLUTE - (PORT dataa (350:350:350) (382:382:382)) - (PORT datab (220:220:220) (258:258:258)) - (PORT datac (193:193:193) (227:227:227)) - (PORT datad (539:539:539) (561:561:561)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (952:952:952) (1004:1004:1004)) - (PORT datab (876:876:876) (893:893:893)) - (PORT datac (1689:1689:1689) (1781:1781:1781)) - (PORT datad (1175:1175:1175) (1232:1232:1232)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1346:1346:1346) (1340:1340:1340)) - (PORT datab (1176:1176:1176) (1219:1219:1219)) - (PORT datac (1123:1123:1123) (1137:1137:1137)) - (PORT datad (665:665:665) (719:719:719)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1197:1197:1197) (1247:1247:1247)) - (PORT datac (582:582:582) (614:614:614)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (1190:1190:1190) (1242:1242:1242)) - (PORT datab (650:650:650) (679:679:679)) - (PORT datac (191:191:191) (237:237:237)) - (PORT datad (607:607:607) (635:635:635)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~7) - (DELAY - (ABSOLUTE - (PORT dataa (228:228:228) (274:274:274)) - (PORT datac (2094:2094:2094) (2219:2219:2219)) - (PORT datad (1462:1462:1462) (1527:1527:1527)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel_pla66npla53M1T1_15) - (DELAY - (ABSOLUTE - (PORT dataa (424:424:424) (461:461:461)) - (PORT datab (1161:1161:1161) (1190:1190:1190)) - (PORT datac (1460:1460:1460) (1518:1518:1518)) - (PORT datad (1106:1106:1106) (1136:1136:1136)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1080:1080:1080) (1147:1147:1147)) - (PORT datab (1037:1037:1037) (1105:1105:1105)) - (PORT datac (1180:1180:1180) (1210:1210:1210)) - (PORT datad (1210:1210:1210) (1252:1252:1252)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~8) - (DELAY - (ABSOLUTE - (PORT dataa (898:898:898) (919:919:919)) - (PORT datab (661:661:661) (705:705:705)) - (PORT datac (1104:1104:1104) (1117:1117:1117)) - (PORT datad (766:766:766) (786:786:786)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1112:1112:1112) (1156:1156:1156)) - (PORT datab (1528:1528:1528) (1657:1657:1657)) - (PORT datac (609:609:609) (665:665:665)) - (PORT datad (181:181:181) (210:210:210)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~4) - (DELAY - (ABSOLUTE - (PORT dataa (734:734:734) (762:762:762)) - (PORT datab (849:849:849) (885:885:885)) - (PORT datac (787:787:787) (804:804:804)) - (PORT datad (670:670:670) (694:694:694)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1025:1025:1025) (1084:1084:1084)) - (PORT datab (969:969:969) (1019:1019:1019)) - (PORT datac (192:192:192) (223:223:223)) - (PORT datad (1444:1444:1444) (1475:1475:1475)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1298:1298:1298) (1390:1390:1390)) - (PORT datab (968:968:968) (1017:1017:1017)) - (PORT datac (1050:1050:1050) (1110:1110:1110)) - (PORT datad (1553:1553:1553) (1682:1682:1682)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~43) - (DELAY - (ABSOLUTE - (PORT dataa (1298:1298:1298) (1391:1391:1391)) - (PORT datab (1247:1247:1247) (1291:1291:1291)) - (PORT datac (985:985:985) (1043:1043:1043)) - (PORT datad (1553:1553:1553) (1682:1682:1682)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~26) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datac (179:179:179) (215:215:215)) - (PORT datad (182:182:182) (211:211:211)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (564:564:564) (579:579:579)) - (PORT datab (244:244:244) (288:288:288)) - (PORT datac (543:543:543) (551:551:551)) - (PORT datad (1454:1454:1454) (1511:1511:1511)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~9) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (1400:1400:1400) (1422:1422:1422)) - (PORT datac (572:572:572) (596:596:596)) - (PORT datad (602:602:602) (630:630:630)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout 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(380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1765:1765:1765) (1808:1808:1808)) - (PORT datab (1620:1620:1620) (1658:1658:1658)) - (PORT datac (1305:1305:1305) (1421:1421:1421)) - (PORT datad (1541:1541:1541) (1677:1677:1677)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1103:1103:1103) (1119:1119:1119)) - (PORT datab (1046:1046:1046) (1094:1094:1094)) - (PORT datac (952:952:952) (984:984:984)) - (PORT datad (819:819:819) (844:844:844)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~7) - (DELAY - (ABSOLUTE - (PORT dataa (982:982:982) (1023:1023:1023)) - (PORT datab (700:700:700) (721:721:721)) - (PORT datac (216:216:216) (260:260:260)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~12) - (DELAY - (ABSOLUTE - (PORT dataa (860:860:860) (874:874:874)) - (PORT datab (648:648:648) (669:669:669)) - (PORT datac (877:877:877) (899:899:899)) - (PORT datad (813:813:813) (834:834:834)) - (IOPATH dataa combout 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(243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (242:242:242) (296:296:296)) - (PORT datab (1200:1200:1200) (1240:1240:1240)) - (PORT datac (1213:1213:1213) (1232:1232:1232)) - (PORT datad (559:559:559) (571:571:571)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (1102:1102:1102) (1121:1121:1121)) - (PORT datab (246:246:246) (294:294:294)) - (PORT datac (901:901:901) (943:943:943)) - (PORT datad (1975:1975:1975) (2012:2012:2012)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout 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(669:669:669)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~5) - (DELAY - (ABSOLUTE - (PORT dataa (865:865:865) (890:890:890)) - (PORT datac (839:839:839) (858:858:858)) - (PORT datad (520:520:520) (531:531:531)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~6) - (DELAY - (ABSOLUTE - (PORT dataa (238:238:238) (288:288:288)) - (PORT datab (250:250:250) (300:300:300)) - (PORT datac (1960:1960:1960) (2089:2089:2089)) - (PORT datad (202:202:202) (238:238:238)) - (IOPATH dataa combout (303:303:303) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~35) - (DELAY - (ABSOLUTE - (PORT dataa (1352:1352:1352) (1478:1478:1478)) - (PORT datab (1346:1346:1346) (1363:1363:1363)) - (PORT datac (870:870:870) (896:896:896)) - (PORT datad (1449:1449:1449) (1511:1511:1511)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (1104:1104:1104) (1189:1189:1189)) - (PORT datab (685:685:685) (754:754:754)) - (PORT datac (958:958:958) (1039:1039:1039)) - (PORT datad (613:613:613) (629:629:629)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~6) - (DELAY - (ABSOLUTE - (PORT dataa (627:627:627) (664:664:664)) - (PORT datab (973:973:973) (1069:1069:1069)) - (PORT datac (1733:1733:1733) (1832:1832:1832)) - (PORT datad (1149:1149:1149) (1173:1173:1173)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1999:1999:1999) (2036:2036:2036)) - (PORT datab (872:872:872) (899:899:899)) - (PORT datac (1356:1356:1356) (1432:1432:1432)) - (PORT datad (1348:1348:1348) (1396:1396:1396)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~0) - (DELAY - (ABSOLUTE - (PORT dataa (618:618:618) (650:650:650)) - (PORT datab (1061:1061:1061) (1123:1123:1123)) - (PORT datac (208:208:208) (247:247:247)) - (PORT datad (864:864:864) (923:923:923)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~3) - (DELAY - (ABSOLUTE - (PORT dataa (612:612:612) (632:632:632)) - (PORT datab (203:203:203) (245:245:245)) - (PORT datac (877:877:877) (914:914:914)) - (PORT datad (853:853:853) (874:874:874)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~52) - (DELAY - (ABSOLUTE - (PORT dataa (1749:1749:1749) (1769:1769:1769)) - (PORT datab (1064:1064:1064) (1181:1181:1181)) - (PORT datac (1204:1204:1204) (1273:1273:1273)) - (PORT datad (860:860:860) (875:875:875)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (686:686:686) (719:719:719)) - (PORT datab (1166:1166:1166) (1236:1236:1236)) - (PORT datac (1485:1485:1485) (1511:1511:1511)) - (PORT datad (1469:1469:1469) (1516:1516:1516)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~2) - (DELAY - (ABSOLUTE - (PORT dataa (858:858:858) (880:880:880)) - (PORT datab (1385:1385:1385) (1395:1395:1395)) - (PORT datac (777:777:777) (796:796:796)) - (PORT datad (1739:1739:1739) (1779:1779:1779)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|rsel3) - (DELAY - (ABSOLUTE - (PORT dataa (1404:1404:1404) (1480:1480:1480)) - (PORT datab (2358:2358:2358) (2492:2492:2492)) - (PORT datac (1133:1133:1133) (1174:1174:1174)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~5) - (DELAY - (ABSOLUTE - (PORT dataa (966:966:966) (1016:1016:1016)) - (PORT datab (1031:1031:1031) (1053:1053:1053)) - (PORT datac (181:181:181) (219:219:219)) - (PORT datad (652:652:652) (692:692:692)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~6) - (DELAY - (ABSOLUTE - (PORT dataa (590:590:590) (616:616:616)) - (PORT datab (672:672:672) (701:701:701)) - (PORT datac (510:510:510) (522:522:522)) - (PORT datad (840:840:840) (853:853:853)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~7) - (DELAY - (ABSOLUTE - (PORT dataa (207:207:207) (256:256:256)) - (PORT datab (884:884:884) (911:911:911)) - (PORT datac (866:866:866) (930:930:930)) - (PORT datad (180:180:180) (209:209:209)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|rsel0) - (DELAY - (ABSOLUTE - (PORT dataa (2169:2169:2169) (2322:2322:2322)) - (PORT datac (1461:1461:1461) (1534:1534:1534)) - (PORT datad (2260:2260:2260) (2326:2326:2326)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_ixy_dT2_2) - (DELAY - (ABSOLUTE - (PORT datab (924:924:924) (1011:1011:1011)) - (PORT datac (1545:1545:1545) (1672:1672:1672)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (705:705:705) (747:747:747)) - (PORT datab (868:868:868) (890:890:890)) - (PORT datac (1285:1285:1285) (1378:1378:1378)) - (PORT datad (896:896:896) (936:936:936)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1484:1484:1484) (1547:1547:1547)) - (PORT datab (205:205:205) (245:245:245)) - (PORT datac (988:988:988) (1034:1034:1034)) - (PORT datad (1031:1031:1031) (1081:1081:1081)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~7) - (DELAY - (ABSOLUTE - (PORT dataa (236:236:236) (286:286:286)) - (PORT datab (373:373:373) (398:398:398)) - (PORT datac (599:599:599) (641:641:641)) - (PORT datad (200:200:200) (235:235:235)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_iorw\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1623:1623:1623) (1713:1713:1713)) - (PORT datab (1529:1529:1529) (1662:1662:1662)) - (PORT datac (1705:1705:1705) (1826:1826:1826)) - (PORT datad (1447:1447:1447) (1495:1495:1495)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1779:1779:1779) (1826:1826:1826)) - (PORT datab (681:681:681) (732:732:732)) - (PORT datac (551:551:551) (571:571:571)) - (PORT datad (1134:1134:1134) (1177:1177:1177)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~14) - (DELAY - (ABSOLUTE - (PORT dataa (688:688:688) (759:759:759)) - (PORT datab (1001:1001:1001) (1109:1109:1109)) - (PORT datac (192:192:192) (226:226:226)) - (PORT datad (1242:1242:1242) (1328:1328:1328)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~11) - (DELAY - (ABSOLUTE - (PORT dataa (598:598:598) (630:630:630)) - (PORT datab (875:875:875) (920:920:920)) - (PORT datac (338:338:338) (364:364:364)) - (PORT datad (685:685:685) (739:739:739)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~12) - (DELAY - (ABSOLUTE - (PORT dataa (655:655:655) (707:707:707)) - (PORT datab (950:950:950) (1008:1008:1008)) - (PORT datac (590:590:590) (605:605:605)) - (PORT datad (654:654:654) (692:692:692)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1138:1138:1138) (1171:1171:1171)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (566:566:566) (595:595:595)) - (PORT datad (180:180:180) (208:208:208)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_66_oe) - (DELAY - (ABSOLUTE - (PORT dataa (362:362:362) (494:494:494)) - (PORT datab (1299:1299:1299) (1396:1396:1396)) - (PORT datac (680:680:680) (764:764:764)) - (PORT datad (1300:1300:1300) (1391:1391:1391)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~34) - (DELAY - (ABSOLUTE - (PORT dataa (1581:1581:1581) (1626:1626:1626)) - (PORT datab (906:906:906) (950:950:950)) - (PORT datac (1263:1263:1263) (1320:1320:1320)) - (PORT datad (1666:1666:1666) (1688:1688:1688)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_apin_mux\~0) - (DELAY - (ABSOLUTE - (PORT dataa (370:370:370) (401:401:401)) - (PORT datab (221:221:221) (260:260:260)) - (PORT datac (653:653:653) (714:714:714)) - (PORT datad (1668:1668:1668) (1689:1689:1689)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1304:1304:1304) (1373:1373:1373)) - (PORT datab (1184:1184:1184) (1235:1235:1235)) - (PORT datac (1139:1139:1139) (1197:1197:1197)) - (PORT datad (1323:1323:1323) (1433:1433:1433)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~75) - (DELAY - (ABSOLUTE - (PORT dataa (908:908:908) (940:940:940)) - (PORT datab (380:380:380) (410:410:410)) - (PORT datac (654:654:654) (698:698:698)) - (PORT datad (1204:1204:1204) (1277:1277:1277)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~76) - (DELAY - (ABSOLUTE - (PORT dataa (1111:1111:1111) (1116:1116:1116)) - (PORT datab (917:917:917) (963:963:963)) - (PORT datac (1010:1010:1010) (1060:1060:1060)) - (PORT datad (924:924:924) (954:954:954)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (206:206:206) (251:251:251)) - (PORT datab (964:964:964) (1061:1061:1061)) - (PORT datac (844:844:844) (886:886:886)) - (PORT datad (905:905:905) (950:950:950)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~48) - (DELAY - (ABSOLUTE - (PORT dataa (998:998:998) (1084:1084:1084)) - (PORT datab (1205:1205:1205) (1272:1272:1272)) - (PORT datac (1579:1579:1579) (1687:1687:1687)) - (PORT datad (1138:1138:1138) (1195:1195:1195)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~46) - (DELAY - (ABSOLUTE - (PORT dataa (613:613:613) (653:653:653)) - (PORT datab (2073:2073:2073) (2252:2252:2252)) - (PORT datac (861:861:861) (894:894:894)) - (PORT datad (1257:1257:1257) (1349:1349:1349)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~53) - (DELAY - (ABSOLUTE - (PORT dataa (892:892:892) (961:961:961)) - (PORT datab (916:916:916) (955:955:955)) - (PORT datac (1131:1131:1131) (1156:1156:1156)) - (PORT datad (926:926:926) (955:955:955)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~92) - (DELAY - (ABSOLUTE - (PORT dataa (1028:1028:1028) (1147:1147:1147)) - (PORT datab (1588:1588:1588) (1723:1723:1723)) - (PORT datac (637:637:637) (656:656:656)) - (PORT datad (1691:1691:1691) (1790:1790:1790)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal19\~1) - (DELAY - (ABSOLUTE - (PORT dataa (2337:2337:2337) (2490:2490:2490)) - (PORT datab (1668:1668:1668) (1785:1785:1785)) - (PORT datac (905:905:905) (956:956:956)) - (PORT datad (672:672:672) (720:720:720)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1009:1009:1009) (1130:1130:1130)) - (PORT datad (1542:1542:1542) (1657:1657:1657)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~38) - (DELAY - (ABSOLUTE - (PORT dataa (1306:1306:1306) (1373:1373:1373)) - (PORT datab (656:656:656) (703:703:703)) - (PORT datac (1351:1351:1351) (1409:1409:1409)) - (PORT datad (881:881:881) (908:908:908)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~93) - (DELAY - (ABSOLUTE - (PORT dataa (1127:1127:1127) (1148:1148:1148)) - (PORT datab (1720:1720:1720) (1825:1825:1825)) - (PORT datac (1557:1557:1557) (1685:1685:1685)) - (PORT datad (1001:1001:1001) (1102:1102:1102)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~39) - (DELAY - (ABSOLUTE - (PORT dataa (1356:1356:1356) (1478:1478:1478)) - (PORT datab (827:827:827) (854:854:854)) - (PORT datac (1113:1113:1113) (1149:1149:1149)) - (PORT datad (635:635:635) (687:687:687)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~24) - (DELAY - (ABSOLUTE - (PORT datab (1169:1169:1169) (1230:1230:1230)) - (PORT datac (194:194:194) (227:227:227)) - (PORT datad (183:183:183) (212:212:212)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~1) - (DELAY - (ABSOLUTE - (PORT dataa (222:222:222) (266:266:266)) - (PORT datab (851:851:851) (919:919:919)) - (PORT datac (194:194:194) (241:241:241)) - (PORT datad (673:673:673) (732:732:732)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla9M1T5_2) - (DELAY - (ABSOLUTE - (PORT dataa (968:968:968) (1052:1052:1052)) - (PORT datab (936:936:936) (1006:1006:1006)) - (PORT datac (1407:1407:1407) (1449:1449:1449)) - (PORT datad (537:537:537) (548:548:548)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~44) - (DELAY - (ABSOLUTE - (PORT dataa (592:592:592) (620:620:620)) - (PORT datab (867:867:867) (902:902:902)) - (PORT datac (1366:1366:1366) (1470:1470:1470)) - (PORT datad (1496:1496:1496) (1606:1606:1606)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (951:951:951) (985:985:985)) - (PORT datab (916:916:916) (957:957:957)) - (PORT datac (915:915:915) (950:950:950)) - (PORT datad (1540:1540:1540) (1625:1625:1625)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1174:1174:1174) (1214:1214:1214)) - (PORT datab (649:649:649) (694:694:694)) - (PORT datac (902:902:902) (950:950:950)) - (PORT datad (338:338:338) (355:355:355)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla10M5T4_2) - (DELAY - (ABSOLUTE - (PORT datab (1511:1511:1511) (1618:1618:1618)) - (PORT datac (1726:1726:1726) (1837:1837:1837)) - (PORT datad (1072:1072:1072) (1082:1082:1082)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (675:675:675) (734:734:734)) - (PORT datab (1163:1163:1163) (1210:1210:1210)) - (PORT datac (852:852:852) (881:881:881)) - (PORT datad (1173:1173:1173) (1254:1254:1254)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~2) - (DELAY - (ABSOLUTE - (PORT dataa (966:966:966) (1001:1001:1001)) - (PORT datab (946:946:946) (986:986:986)) - (PORT datac (632:632:632) (678:678:678)) - (PORT datad (1150:1150:1150) (1195:1195:1195)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~3) - (DELAY - (ABSOLUTE - (PORT datab (865:865:865) (918:918:918)) - (PORT datac (179:179:179) (213:213:213)) - (PORT datad (851:851:851) (896:896:896)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1052:1052:1052) (1077:1077:1077)) - (PORT datab (1450:1450:1450) (1521:1521:1521)) - (PORT datac (1291:1291:1291) (1321:1321:1321)) - (PORT datad (856:856:856) (875:875:875)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1685:1685:1685) (1750:1750:1750)) - (PORT datab (1695:1695:1695) (1779:1779:1779)) - (PORT datac (1479:1479:1479) (1576:1576:1576)) - (PORT datad (855:855:855) (874:874:874)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla38pla13M4T2_4) - (DELAY - (ABSOLUTE - (PORT dataa (1444:1444:1444) (1505:1505:1505)) - (PORT datab (1695:1695:1695) (1774:1774:1774)) - (PORT datac (1653:1653:1653) (1704:1704:1704)) - (PORT datad (1165:1165:1165) (1208:1208:1208)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~15) - (DELAY - (ABSOLUTE - (PORT dataa (829:829:829) (902:902:902)) - (PORT datab (612:612:612) (626:626:626)) - (PORT datac (1486:1486:1486) (1525:1525:1525)) - (PORT datad (572:572:572) (587:587:587)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (932:932:932) (953:953:953)) - (PORT datab (920:920:920) (939:939:939)) - (PORT datac (888:888:888) (933:933:933)) - (PORT datad (195:195:195) (221:221:221)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~94) - (DELAY - (ABSOLUTE - (PORT dataa (1805:1805:1805) (1846:1846:1846)) - (PORT datab (1718:1718:1718) (1824:1824:1824)) - (PORT datac (1560:1560:1560) (1684:1684:1684)) - (PORT datad (1003:1003:1003) (1103:1103:1103)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~87) - (DELAY - (ABSOLUTE - (PORT dataa (1617:1617:1617) (1736:1736:1736)) - (PORT datac (2516:2516:2516) (2621:2621:2621)) - (PORT datad (1496:1496:1496) (1610:1610:1610)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~42) - (DELAY - (ABSOLUTE - (PORT dataa (1179:1179:1179) (1204:1204:1204)) - (PORT datab (1153:1153:1153) (1208:1208:1208)) - (PORT datac (193:193:193) (226:226:226)) - (PORT datad (861:861:861) (880:880:880)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~34) - (DELAY - (ABSOLUTE - (PORT datab (684:684:684) (709:709:709)) - (PORT datac (378:378:378) (413:413:413)) - (PORT datad (203:203:203) (232:232:232)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~16) - (DELAY - (ABSOLUTE - (PORT dataa (454:454:454) (494:494:494)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (807:807:807) (827:827:827)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~6) - (DELAY - (ABSOLUTE - (PORT dataa (372:372:372) (413:413:413)) - (PORT datab (907:907:907) (914:914:914)) - (PORT datac (619:619:619) (656:656:656)) - (PORT datad (1190:1190:1190) (1243:1243:1243)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal2\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1250:1250:1250) (1344:1344:1344)) - (PORT datab (1673:1673:1673) (1790:1790:1790)) - (PORT datac (909:909:909) (958:958:958)) - (PORT datad (940:940:940) (995:995:995)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal1\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1458:1458:1458) (1556:1556:1556)) - (PORT datab (1664:1664:1664) (1735:1735:1735)) - (PORT datac (847:847:847) (861:861:861)) - (PORT datad (654:654:654) (683:683:683)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|bank_exx\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1407:1407:1407) (1552:1552:1552)) - (PORT datab (901:901:901) (929:929:929)) - (PORT datad (2354:2354:2354) (2501:2501:2501)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_control_\|bank_exx) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1532:1532:1532)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1575:1575:1575) (1555:1555:1555)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|bank_hl_de1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1165:1165:1165) (1200:1200:1200)) - (PORT datab (1193:1193:1193) (1243:1243:1243)) - (PORT datad (1206:1206:1206) (1288:1288:1288)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_control_\|bank_hl_de1) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1553:1553:1553)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1593:1593:1593) (1569:1569:1569)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (928:928:928) (961:961:961)) - (PORT datab (2051:2051:2051) (2083:2083:2083)) - (PORT datac (805:805:805) (817:817:817)) - (PORT datad (336:336:336) (360:360:360)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (965:965:965) (998:998:998)) - (PORT datab (1733:1733:1733) (1770:1770:1770)) - (PORT datac (1229:1229:1229) (1327:1327:1327)) - (PORT datad (1151:1151:1151) (1194:1194:1194)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (766:766:766) (785:785:785)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (1230:1230:1230) (1329:1329:1329)) - (PORT datad (1542:1542:1542) (1627:1627:1627)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1235:1235:1235) (1298:1298:1298)) - (PORT datab (1276:1276:1276) (1367:1367:1367)) - (PORT datac (1156:1156:1156) (1195:1195:1195)) - (PORT datad (711:711:711) (777:777:777)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (622:622:622) (656:656:656)) - (PORT datab (603:603:603) (615:615:615)) - (PORT datac (902:902:902) (950:950:950)) - (PORT datad (1750:1750:1750) (1806:1806:1806)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (937:937:937) (985:985:985)) - (PORT datab (359:359:359) (388:388:388)) - (PORT datac (1182:1182:1182) (1242:1242:1242)) - (PORT datad (2028:2028:2028) (2153:2153:2153)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (341:341:341) (372:372:372)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (878:878:878) (913:913:913)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~47) - (DELAY - (ABSOLUTE - (PORT dataa (970:970:970) (1069:1069:1069)) - (PORT datab (913:913:913) (1002:1002:1002)) - (PORT datac (1084:1084:1084) (1074:1074:1074)) - (PORT datad (1060:1060:1060) (1062:1062:1062)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1344:1344:1344) (1441:1441:1441)) - (PORT datab (898:898:898) (946:946:946)) - (PORT datac (669:669:669) (692:692:692)) - (PORT datad (1162:1162:1162) (1228:1228:1228)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~5) - (DELAY - (ABSOLUTE - (PORT dataa (2046:2046:2046) (2143:2143:2143)) - (PORT datac (1652:1652:1652) (1690:1690:1690)) - (PORT datad (1726:1726:1726) (1766:1766:1766)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~2) - (DELAY - (ABSOLUTE - (PORT dataa (985:985:985) (1068:1068:1068)) - (PORT datab (1320:1320:1320) (1358:1358:1358)) - (PORT datac (1320:1320:1320) (1375:1375:1375)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~19) - (DELAY - (ABSOLUTE - (PORT datab (667:667:667) (677:677:677)) - (PORT datac (650:650:650) (674:674:674)) - (PORT datad (899:899:899) (937:937:937)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (666:666:666) (691:691:691)) - (PORT datab (711:711:711) (745:745:745)) - (PORT datac (675:675:675) (730:730:730)) - (PORT datad (832:832:832) (843:843:843)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (844:844:844) (889:889:889)) - (PORT datac (1915:1915:1915) (1982:1982:1982)) - (PORT datad (200:200:200) (239:239:239)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (611:611:611) (677:677:677)) - (PORT datab (864:864:864) (932:932:932)) - (PORT datac (1099:1099:1099) (1123:1123:1123)) - (PORT datad (830:830:830) (852:852:852)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1058:1058:1058) (1166:1166:1166)) - (PORT datab (1000:1000:1000) (1115:1115:1115)) - (PORT datac (1411:1411:1411) (1477:1477:1477)) - (PORT datad (203:203:203) (239:239:239)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1061:1061:1061) (1166:1166:1166)) - (PORT datab (1976:1976:1976) (2065:2065:2065)) - (PORT datac (1151:1151:1151) (1205:1205:1205)) - (PORT datad (941:941:941) (1012:1012:1012)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (199:199:199) (239:239:239)) - (PORT datac (2603:2603:2603) (2772:2772:2772)) - (PORT datad (194:194:194) (219:219:219)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (932:932:932) (1032:1032:1032)) - (PORT datac (1109:1109:1109) (1164:1164:1164)) - (PORT datad (1148:1148:1148) (1191:1191:1191)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~2) - (DELAY - (ABSOLUTE - (PORT dataa (988:988:988) (1040:1040:1040)) - (PORT datab (845:845:845) (850:850:850)) - (PORT datac (2021:2021:2021) (2050:2050:2050)) - (PORT datad (1388:1388:1388) (1426:1426:1426)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~47) - (DELAY - (ABSOLUTE - (PORT dataa (1582:1582:1582) (1703:1703:1703)) - (PORT datab (917:917:917) (971:971:971)) - (PORT datac (929:929:929) (1008:1008:1008)) - (PORT datad (1530:1530:1530) (1630:1630:1630)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~3) - (DELAY - (ABSOLUTE - (PORT dataa (642:642:642) (674:674:674)) - (PORT datab (871:871:871) (890:890:890)) - (PORT datac (598:598:598) (661:661:661)) - (PORT datad (809:809:809) (825:825:825)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1116:1116:1116) (1239:1239:1239)) - (PORT datac (1383:1383:1383) (1458:1458:1458)) - (PORT datad (2108:2108:2108) (2253:2253:2253)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (896:896:896) (968:968:968)) - (PORT datab (1559:1559:1559) (1655:1655:1655)) - (PORT datac (211:211:211) (252:252:252)) - (PORT datad (618:618:618) (634:634:634)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (1375:1375:1375) (1445:1445:1445)) - (PORT datab (619:619:619) (640:640:640)) - (PORT datac (776:776:776) (799:799:799)) - (PORT datad (597:597:597) (614:614:614)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (1683:1683:1683) (1739:1739:1739)) - (PORT datab (1115:1115:1115) (1125:1125:1125)) - (PORT datac (1054:1054:1054) (1110:1110:1110)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~49) - (DELAY - (ABSOLUTE - (PORT dataa (1324:1324:1324) (1411:1411:1411)) - (PORT datab (205:205:205) (247:247:247)) - (PORT datac (592:592:592) (627:627:627)) - (PORT datad (1466:1466:1466) (1538:1538:1538)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (576:576:576) (604:604:604)) - (PORT datab (614:614:614) (675:675:675)) - (PORT datac (611:611:611) (636:636:636)) - (PORT datad (573:573:573) (586:586:586)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (2248:2248:2248) (2386:2386:2386)) - (PORT datab (260:260:260) (341:341:341)) - (PORT datac (1161:1161:1161) (1218:1218:1218)) - (PORT datad (235:235:235) (303:303:303)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~23) + (INSTANCE z80_\|interrupts_\|iff1\~1) (DELAY (ABSOLUTE (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (179:179:179) (216:216:216)) - (PORT datad (874:874:874) (909:909:909)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~28) - (DELAY - (ABSOLUTE - (PORT datab (208:208:208) (250:250:250)) - (PORT datad (663:663:663) (707:707:707)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (215:215:215) (266:266:266)) - (PORT datab (1027:1027:1027) (1068:1068:1068)) - (PORT datac (332:332:332) (358:358:358)) - (PORT datad (688:688:688) (740:740:740)) + (PORT datab (1002:1002:1002) (1061:1061:1061)) + (PORT datac (241:241:241) (318:318:318)) + (PORT datad (1108:1108:1108) (1117:1117:1117)) (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1125:1125:1125) (1247:1247:1247)) - (PORT datac (887:887:887) (944:944:944)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~14) - (DELAY - (ABSOLUTE - (PORT datac (663:663:663) (747:747:747)) - (PORT datad (890:890:890) (915:915:915)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1435:1435:1435) (1516:1516:1516)) - (PORT datab (619:619:619) (646:646:646)) - (PORT datac (172:172:172) (204:204:204)) - (PORT datad (1126:1126:1126) (1172:1172:1172)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~47) - (DELAY - (ABSOLUTE - (PORT dataa (615:615:615) (640:640:640)) - (PORT datab (648:648:648) (672:672:672)) - (PORT datac (891:891:891) (929:929:929)) - (PORT datad (873:873:873) (908:908:908)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~48) - (DELAY - (ABSOLUTE - (PORT dataa (346:346:346) (385:385:385)) - (PORT datab (220:220:220) (259:259:259)) - (PORT datac (616:616:616) (658:658:658)) - (PORT datad (1046:1046:1046) (1069:1069:1069)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~13) - (DELAY - (ABSOLUTE - (PORT dataa (2048:2048:2048) (2143:2143:2143)) - (PORT datac (1652:1652:1652) (1688:1688:1688)) - (PORT datad (1726:1726:1726) (1766:1766:1766)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1331:1331:1331) (1424:1424:1424)) - (PORT datab (1098:1098:1098) (1141:1141:1141)) - (PORT datac (923:923:923) (945:945:945)) - (PORT datad (569:569:569) (578:578:578)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_oe\~1) - (DELAY - (ABSOLUTE - (PORT dataa (231:231:231) (278:278:278)) - (PORT datab (229:229:229) (272:272:272)) - (PORT datac (1186:1186:1186) (1234:1234:1234)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~13) - (DELAY - (ABSOLUTE - (PORT dataa (816:816:816) (855:855:855)) - (PORT datab (1257:1257:1257) (1326:1326:1326)) - (PORT datac (1798:1798:1798) (1932:1932:1932)) - (PORT datad (2112:2112:2112) (2257:2257:2257)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (632:632:632) (652:652:652)) - (PORT datac (595:595:595) (618:618:618)) - (PORT datad (847:847:847) (860:860:860)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~40) - (DELAY - (ABSOLUTE - (PORT dataa (1357:1357:1357) (1484:1484:1484)) - (PORT datab (742:742:742) (806:806:806)) - (PORT datac (873:873:873) (902:902:902)) - (PORT datad (887:887:887) (943:943:943)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~2) - (DELAY - (ABSOLUTE - (PORT dataa (904:904:904) (916:916:916)) - (PORT datab (683:683:683) (749:749:749)) - (PORT datac (971:971:971) (1032:1032:1032)) - (PORT datad (1783:1783:1783) (1858:1858:1858)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1298:1298:1298) (1401:1401:1401)) - (PORT datab (881:881:881) (925:925:925)) - (PORT datac (637:637:637) (657:657:657)) - (PORT datad (1737:1737:1737) (1788:1788:1788)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~43) - (DELAY - (ABSOLUTE - (PORT dataa (1357:1357:1357) (1486:1486:1486)) - (PORT datab (643:643:643) (709:709:709)) - (PORT datac (874:874:874) (901:901:901)) - (PORT datad (380:380:380) (406:406:406)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~5) - (DELAY - (ABSOLUTE - (PORT dataa (892:892:892) (953:953:953)) - (PORT datab (685:685:685) (750:750:750)) - (PORT datac (967:967:967) (1028:1028:1028)) - (PORT datad (629:629:629) (639:639:639)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1456:1456:1456) (1534:1534:1534)) - (PORT datab (926:926:926) (971:971:971)) - (PORT datac (191:191:191) (224:224:224)) - (PORT datad (1396:1396:1396) (1442:1442:1442)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1587:1587:1587) (1654:1654:1654)) - (PORT datab (1578:1578:1578) (1625:1625:1625)) - (PORT datac (1000:1000:1000) (1045:1045:1045)) - (PORT datad (1562:1562:1562) (1620:1620:1620)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1452:1452:1452) (1526:1526:1526)) - (PORT datab (898:898:898) (959:959:959)) - (PORT datac (823:823:823) (876:876:876)) - (PORT datad (584:584:584) (613:613:613)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1449:1449:1449) (1523:1523:1523)) - (PORT datab (899:899:899) (962:962:962)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (914:914:914) (977:977:977)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (596:596:596) (613:613:613)) - (PORT datab (864:864:864) (919:919:919)) - (PORT datac (792:792:792) (849:849:849)) - (PORT datad (781:781:781) (835:835:835)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~13) - (DELAY - (ABSOLUTE - (PORT dataa (652:652:652) (665:665:665)) - (PORT datab (238:238:238) (284:284:284)) - (PORT datac (1314:1314:1314) (1404:1404:1404)) - (PORT datad (2218:2218:2218) (2338:2338:2338)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1788:1788:1788) (1938:1938:1938)) - (PORT datab (1645:1645:1645) (1766:1766:1766)) - (PORT datac (1304:1304:1304) (1398:1398:1398)) - (PORT datad (2565:2565:2565) (2702:2702:2702)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1255:1255:1255) (1317:1317:1317)) - (PORT datab (870:870:870) (893:893:893)) - (PORT datac (173:173:173) (206:206:206)) - (PORT datad (588:588:588) (606:606:606)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1443:1443:1443) (1548:1548:1548)) - (PORT datab (263:263:263) (309:309:309)) - (PORT datac (1197:1197:1197) (1255:1255:1255)) - (PORT datad (842:842:842) (854:854:854)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal62\~2) - (DELAY - (ABSOLUTE - (PORT dataa (856:856:856) (910:910:910)) - (PORT datab (891:891:891) (912:912:912)) - (PORT datac (859:859:859) (877:877:877)) - (PORT datad (902:902:902) (978:978:978)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (859:859:859) (921:921:921)) - (PORT datab (937:937:937) (1012:1012:1012)) - (PORT datac (195:195:195) (239:239:239)) - (PORT datad (1152:1152:1152) (1199:1199:1199)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1470:1470:1470) (1476:1476:1476)) - (PORT datab (1497:1497:1497) (1569:1569:1569)) - (PORT datac (1102:1102:1102) (1120:1120:1120)) - (PORT datad (400:400:400) (436:436:436)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal64\~0) - (DELAY - (ABSOLUTE - (PORT dataa (854:854:854) (906:906:906)) - (PORT datab (893:893:893) (913:913:913)) - (PORT datac (861:861:861) (879:879:879)) - (PORT datad (904:904:904) (979:979:979)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel\[0\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (710:710:710) (805:805:805)) - (PORT datab (775:775:775) (880:880:880)) - (PORT datad (1178:1178:1178) (1197:1197:1197)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (593:593:593) (619:619:619)) - (PORT datab (1166:1166:1166) (1207:1207:1207)) - (PORT datac (854:854:854) (905:905:905)) - (PORT datad (902:902:902) (956:956:956)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1440:1440:1440) (1550:1550:1550)) - (PORT datab (866:866:866) (895:895:895)) - (PORT datac (1284:1284:1284) (1336:1336:1336)) - (PORT datad (1607:1607:1607) (1729:1729:1729)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla89M1T2_3) - (DELAY - (ABSOLUTE - (PORT dataa (1494:1494:1494) (1601:1601:1601)) - (PORT datab (1439:1439:1439) (1451:1451:1451)) - (PORT datac (1444:1444:1444) (1551:1551:1551)) - (PORT datad (402:402:402) (439:439:439)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (1017:1017:1017) (1057:1057:1057)) - (PORT datac (793:793:793) (802:802:802)) - (PORT datad (1022:1022:1022) (1048:1048:1048)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (397:397:397) (440:440:440)) - (PORT datac (980:980:980) (992:992:992)) - (PORT datad (182:182:182) (211:211:211)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (343:343:343) (373:373:373)) - (PORT datab (198:198:198) (235:235:235)) - (PORT datac (586:586:586) (613:613:613)) - (PORT datad (1522:1522:1522) (1622:1622:1622)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (1222:1222:1222) (1272:1272:1272)) - (PORT datab (1222:1222:1222) (1263:1263:1263)) - (PORT datac (892:892:892) (922:922:922)) - (PORT datad (1507:1507:1507) (1624:1624:1624)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (844:844:844) (886:886:886)) - (PORT datab (227:227:227) (274:274:274)) - (PORT datac (1160:1160:1160) (1222:1222:1222)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\~20) - (DELAY - (ABSOLUTE - (PORT dataa (1685:1685:1685) (1744:1744:1744)) - (PORT datab (1695:1695:1695) (1779:1779:1779)) - (PORT datac (1482:1482:1482) (1577:1577:1577)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (934:934:934) (1034:1034:1034)) - (PORT datab (206:206:206) (246:246:246)) - (PORT datac (1192:1192:1192) (1254:1254:1254)) - (PORT datad (882:882:882) (917:917:917)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~35) - (DELAY - (ABSOLUTE - (PORT datab (1193:1193:1193) (1230:1230:1230)) - (PORT datac (1251:1251:1251) (1308:1308:1308)) - (PORT datad (780:780:780) (799:799:799)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_de2\~5) - (DELAY - (ABSOLUTE - (PORT dataa (896:896:896) (976:976:976)) - (PORT datab (940:940:940) (1022:1022:1022)) - (PORT datac (1140:1140:1140) (1178:1178:1178)) - (PORT datad (375:375:375) (417:417:417)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_de2\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1284:1284:1284) (1345:1345:1345)) - (PORT datab (1189:1189:1189) (1228:1228:1228)) - (PORT datac (1135:1135:1135) (1177:1177:1177)) - (PORT datad (780:780:780) (799:799:799)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_hl\~0) - (DELAY - (ABSOLUTE - (PORT dataa (252:252:252) (343:343:343)) - (PORT datab (224:224:224) (272:272:272)) - (PORT datac (342:342:342) (371:371:371)) - (PORT datad (1219:1219:1219) (1301:1301:1301)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|bank_hl_de2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1167:1167:1167) (1203:1203:1203)) - (PORT datab (1191:1191:1191) (1242:1242:1242)) - (PORT datad (1220:1220:1220) (1299:1299:1299)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_control_\|bank_hl_de2) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1553:1553:1553)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1593:1593:1593) (1569:1569:1569)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_hl2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (368:368:368) (405:405:405)) - (PORT datab (224:224:224) (269:269:269)) - (PORT datac (222:222:222) (302:302:302)) - (PORT datad (1202:1202:1202) (1285:1285:1285)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~7) - (DELAY - (ABSOLUTE - (PORT dataa (568:568:568) (586:586:586)) - (PORT datab (1028:1028:1028) (1073:1073:1073)) - (PORT datac (338:338:338) (364:364:364)) - (PORT datad (686:686:686) (739:739:739)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (647:647:647) (687:687:687)) - (PORT datab (1720:1720:1720) (1802:1802:1802)) - (PORT datad (879:879:879) (876:876:876)) - (IOPATH dataa combout (301:301:301) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla30npla13M4T3_5) - (DELAY - (ABSOLUTE - (PORT dataa (2640:2640:2640) (2740:2740:2740)) - (PORT datab (1718:1718:1718) (1823:1823:1823)) - (PORT datac (1017:1017:1017) (1049:1049:1049)) - (PORT datad (1534:1534:1534) (1564:1564:1564)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (229:229:229) (277:277:277)) - (PORT datab (894:894:894) (923:923:923)) - (PORT datac (1486:1486:1486) (1564:1564:1564)) - (PORT datad (1217:1217:1217) (1256:1256:1256)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~13) - (DELAY - (ABSOLUTE - (PORT dataa (985:985:985) (1038:1038:1038)) - (PORT datab (204:204:204) (246:246:246)) - (PORT datac (946:946:946) (1014:1014:1014)) - (PORT datad (209:209:209) (240:240:240)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla30npla13M5T3_5) - (DELAY - (ABSOLUTE - (PORT dataa (941:941:941) (1011:1011:1011)) - (PORT datab (229:229:229) (278:278:278)) - (PORT datac (1408:1408:1408) (1479:1479:1479)) - (PORT datad (1499:1499:1499) (1550:1550:1550)) - (IOPATH dataa combout (304:304:304) (307:307:307)) (IOPATH datab combout (336:336:336) (325:325:325)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -8629,2584 +1404,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~2) + (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_15) (DELAY (ABSOLUTE - (PORT dataa (1150:1150:1150) (1181:1181:1181)) - (PORT datab (1549:1549:1549) (1573:1573:1573)) - (PORT datac (592:592:592) (626:626:626)) - (PORT datad (194:194:194) (219:219:219)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (357:357:357) (391:391:391)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (170:170:170) (202:202:202)) - (PORT datad (178:178:178) (207:207:207)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (910:910:910) (934:934:934)) - (PORT datab (654:654:654) (689:689:689)) - (PORT datac (1104:1104:1104) (1117:1117:1117)) - (PORT datad (766:766:766) (786:786:786)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1624:1624:1624) (1711:1711:1711)) - (PORT datab (1531:1531:1531) (1582:1582:1582)) - (PORT datac (1704:1704:1704) (1824:1824:1824)) - (PORT datad (1073:1073:1073) (1075:1075:1075)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~50) - (DELAY - (ABSOLUTE - (PORT dataa (2002:2002:2002) (2195:2195:2195)) - (PORT datab (1455:1455:1455) (1549:1549:1549)) - (PORT datac (1508:1508:1508) (1592:1592:1592)) - (PORT datad (1918:1918:1918) (1978:1978:1978)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (892:892:892) (965:965:965)) - (PORT datab (871:871:871) (909:909:909)) - (PORT datac (803:803:803) (870:870:870)) - (PORT datad (1526:1526:1526) (1620:1620:1620)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (621:621:621) (664:664:664)) - (PORT datab (678:678:678) (735:735:735)) - (PORT datac (919:919:919) (966:966:966)) - (PORT datad (181:181:181) (210:210:210)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (699:699:699) (728:728:728)) - (PORT datab (1191:1191:1191) (1244:1244:1244)) - (PORT datac (669:669:669) (694:694:694)) - (PORT datad (1304:1304:1304) (1397:1397:1397)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (1369:1369:1369) (1431:1431:1431)) - (PORT datab (643:643:643) (680:680:680)) - (PORT datac (1322:1322:1322) (1362:1362:1362)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla10M5T1_5\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1105:1105:1105) (1190:1190:1190)) - (PORT datab (1820:1820:1820) (1897:1897:1897)) - (PORT datad (966:966:966) (1074:1074:1074)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (904:904:904) (932:932:932)) - (PORT datab (680:680:680) (741:741:741)) - (PORT datac (202:202:202) (239:239:239)) - (PORT datad (2206:2206:2206) (2251:2251:2251)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~51) - (DELAY - (ABSOLUTE - (PORT dataa (1252:1252:1252) (1348:1348:1348)) - (PORT datab (1492:1492:1492) (1598:1598:1598)) - (PORT datac (1226:1226:1226) (1277:1277:1277)) - (PORT datad (1231:1231:1231) (1263:1263:1263)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (1906:1906:1906) (2000:2000:2000)) - (PORT datab (198:198:198) (238:238:238)) - (PORT datac (869:869:869) (926:926:926)) - (PORT datad (188:188:188) (220:220:220)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (621:621:621) (635:635:635)) - (PORT datab (219:219:219) (258:258:258)) - (PORT datac (898:898:898) (931:931:931)) - (PORT datad (816:816:816) (860:860:860)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (810:810:810) (881:881:881)) - (PORT datab (206:206:206) (246:246:246)) - (PORT datac (561:561:561) (575:575:575)) - (PORT datad (613:613:613) (668:668:668)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (844:844:844) (889:889:889)) - (PORT datac (208:208:208) (251:251:251)) - (PORT datad (202:202:202) (238:238:238)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (1311:1311:1311) (1368:1368:1368)) - (PORT datab (614:614:614) (640:640:640)) - (PORT datac (842:842:842) (872:872:872)) - (PORT datad (607:607:607) (635:635:635)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (1417:1417:1417) (1464:1464:1464)) - (PORT datab (910:910:910) (954:954:954)) - (PORT datac (1136:1136:1136) (1177:1177:1177)) - (PORT datad (1173:1173:1173) (1255:1255:1255)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla6M1T4_4) - (DELAY - (ABSOLUTE - (PORT dataa (1757:1757:1757) (1831:1831:1831)) - (PORT datab (836:836:836) (849:849:849)) - (PORT datac (2018:2018:2018) (2050:2050:2050)) - (PORT datad (2040:2040:2040) (2102:2102:2102)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~40) - (DELAY - (ABSOLUTE - (PORT dataa (927:927:927) (961:961:961)) - (PORT datab (1098:1098:1098) (1150:1150:1150)) - (PORT datad (194:194:194) (220:220:220)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (535:535:535) (566:566:566)) - (PORT datab (662:662:662) (694:694:694)) - (PORT datac (2000:2000:2000) (2031:2031:2031)) - (PORT datad (538:538:538) (549:549:549)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (242:242:242)) - (PORT datab (852:852:852) (924:924:924)) - (PORT datac (179:179:179) (214:214:214)) - (PORT datad (195:195:195) (221:221:221)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~38) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (244:244:244)) - (PORT datab (855:855:855) (863:863:863)) - (PORT datac (568:568:568) (591:591:591)) - (PORT datad (181:181:181) (209:209:209)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~93) - (DELAY - (ABSOLUTE - (PORT dataa (1191:1191:1191) (1227:1227:1227)) - (PORT datab (1050:1050:1050) (1057:1057:1057)) - (PORT datac (1185:1185:1185) (1207:1207:1207)) - (PORT datad (1343:1343:1343) (1388:1388:1388)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_de\~0) - (DELAY - (ABSOLUTE - (PORT dataa (249:249:249) (338:338:338)) - (PORT datab (223:223:223) (268:268:268)) - (PORT datac (337:337:337) (367:367:367)) - (PORT datad (1203:1203:1203) (1285:1285:1285)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_50) - (DELAY - (ABSOLUTE - (PORT datab (1384:1384:1384) (1432:1432:1432)) - (PORT datac (1179:1179:1179) (1200:1200:1200)) - (PORT datad (594:594:594) (610:610:610)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_70\~2) - (DELAY - (ABSOLUTE - (PORT datac (900:900:900) (943:943:943)) - (PORT datad (1328:1328:1328) (1383:1383:1383)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_66\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1165:1165:1165) (1261:1261:1261)) - (PORT datab (223:223:223) (270:270:270)) - (PORT datac (1141:1141:1141) (1178:1178:1178)) - (PORT datad (671:671:671) (721:721:721)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_38\~0) - (DELAY - (ABSOLUTE - (PORT dataa (704:704:704) (769:769:769)) - (PORT datab (1469:1469:1469) (1552:1552:1552)) - (PORT datac (1145:1145:1145) (1180:1180:1180)) - (PORT datad (199:199:199) (235:235:235)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_42\~0) - (DELAY - (ABSOLUTE - (PORT dataa (697:697:697) (766:766:766)) - (PORT datab (1471:1471:1471) (1557:1557:1557)) - (PORT datac (1138:1138:1138) (1176:1176:1176)) - (PORT datad (196:196:196) (232:232:232)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1346:1346:1346) (1411:1411:1411)) - (PORT datab (869:869:869) (903:903:903)) - (PORT datac (1807:1807:1807) (1896:1896:1896)) - (PORT datad (1570:1570:1570) (1608:1608:1608)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~10) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (205:205:205) (247:247:247)) - (PORT datad (868:868:868) (885:885:885)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~19) - (DELAY - (ABSOLUTE - (PORT dataa (981:981:981) (1092:1092:1092)) - (PORT datab (657:657:657) (681:681:681)) - (PORT datac (908:908:908) (975:975:975)) - (PORT datad (1438:1438:1438) (1536:1536:1536)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla37pla28M2T3_4) - (DELAY - (ABSOLUTE - (PORT dataa (1101:1101:1101) (1154:1154:1154)) - (PORT datab (701:701:701) (782:782:782)) - (PORT datac (1444:1444:1444) (1551:1551:1551)) - (PORT datad (1465:1465:1465) (1554:1554:1554)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_lo\~8) - (DELAY - (ABSOLUTE - (PORT dataa (601:601:601) (634:634:634)) - (PORT datab (206:206:206) (247:247:247)) - (PORT datac (622:622:622) (651:651:651)) - (PORT datad (1082:1082:1082) (1107:1107:1107)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (390:390:390) (419:419:419)) - (PORT datab (1179:1179:1179) (1229:1229:1229)) - (PORT datac (351:351:351) (380:380:380)) - (PORT datad (1087:1087:1087) (1108:1108:1108)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1246:1246:1246) (1335:1335:1335)) - (PORT datab (1577:1577:1577) (1714:1714:1714)) - (PORT datac (2188:2188:2188) (2312:2312:2312)) - (PORT datad (1069:1069:1069) (1164:1164:1164)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~5) - (DELAY - (ABSOLUTE - (PORT dataa (942:942:942) (1012:1012:1012)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (1253:1253:1253) (1293:1293:1293)) - (PORT datad (195:195:195) (220:220:220)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~6) - (DELAY - (ABSOLUTE - (PORT dataa (630:630:630) (660:660:660)) - (PORT datac (659:659:659) (688:688:688)) - (PORT datad (550:550:550) (559:559:559)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_78\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1144:1144:1144) (1180:1180:1180)) - (PORT datab (218:218:218) (265:265:265)) - (PORT datac (1135:1135:1135) (1168:1168:1168)) - (PORT datad (665:665:665) (712:712:712)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal21\~2) - (DELAY - (ABSOLUTE - (PORT dataa (916:916:916) (938:938:938)) - (PORT datab (900:900:900) (913:913:913)) - (PORT datac (920:920:920) (1008:1008:1008)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|bank_af\~0) - (DELAY - (ABSOLUTE - (PORT dataa (700:700:700) (751:751:751)) - (PORT datab (1166:1166:1166) (1198:1198:1198)) - (PORT datad (948:948:948) (968:968:968)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_control_\|bank_af) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1535:1535:1535)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1558:1558:1558)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_af\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1142:1142:1142) (1184:1184:1184)) - (PORT datab (248:248:248) (332:332:332)) - (PORT datac (1144:1144:1144) (1179:1179:1179)) - (PORT datad (672:672:672) (720:720:720)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_34) - (DELAY - (ABSOLUTE - (PORT dataa (682:682:682) (703:703:703)) - (PORT datab (1351:1351:1351) (1386:1386:1386)) - (PORT datad (908:908:908) (958:958:958)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_af2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1142:1142:1142) (1183:1183:1183)) - (PORT datab (250:250:250) (335:335:335)) - (PORT datac (1137:1137:1137) (1173:1173:1173)) - (PORT datad (664:664:664) (718:718:718)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_30) - (DELAY - (ABSOLUTE - (PORT dataa (1721:1721:1721) (1780:1780:1780)) - (PORT datab (1170:1170:1170) (1223:1223:1223)) - (PORT datad (792:792:792) (797:797:797)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~12) - (DELAY - (ABSOLUTE - (PORT dataa (709:709:709) (761:761:761)) - (PORT datab (914:914:914) (975:975:975)) - (PORT datac (1817:1817:1817) (1896:1896:1896)) - (PORT datad (1153:1153:1153) (1178:1178:1178)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1482:1482:1482) (1581:1581:1581)) - (PORT datac (1016:1016:1016) (1055:1055:1055)) - (PORT datad (321:321:321) (344:344:344)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1428:1428:1428) (1487:1487:1487)) - (PORT datab (1168:1168:1168) (1215:1215:1215)) - (PORT datac (2035:2035:2035) (2124:2124:2124)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1158:1158:1158) (1200:1200:1200)) - (PORT datab (2031:2031:2031) (2127:2127:2127)) - (PORT datac (969:969:969) (1020:1020:1020)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~24) - (DELAY - (ABSOLUTE - (PORT dataa (826:826:826) (902:902:902)) - (PORT datab (1517:1517:1517) (1560:1560:1560)) - (PORT datac (1294:1294:1294) (1324:1324:1324)) - (PORT datad (862:862:862) (880:880:880)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~13) - (DELAY - (ABSOLUTE - (PORT datab (229:229:229) (272:272:272)) - (PORT datac (202:202:202) (239:239:239)) - (PORT datad (202:202:202) (231:231:231)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (1544:1544:1544) (1653:1653:1653)) - (PORT datac (208:208:208) (246:246:246)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~3) - (DELAY - (ABSOLUTE - (PORT dataa (587:587:587) (620:620:620)) - (PORT datab (876:876:876) (893:893:893)) - (PORT datac (1384:1384:1384) (1444:1444:1444)) - (PORT datad (1947:1947:1947) (1977:1977:1977)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (223:223:223) (266:266:266)) - (PORT datab (2017:2017:2017) (2075:2075:2075)) - (PORT datac (804:804:804) (827:827:827)) - (PORT datad (194:194:194) (220:220:220)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~2) - (DELAY - (ABSOLUTE - (PORT dataa (694:694:694) (740:740:740)) - (PORT datab (1445:1445:1445) (1514:1514:1514)) - (PORT datac (360:360:360) (389:389:389)) - (PORT datad (1121:1121:1121) (1177:1177:1177)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~3) - (DELAY - (ABSOLUTE - (PORT dataa (229:229:229) (277:277:277)) - (PORT datab (558:558:558) (578:578:578)) - (PORT datac (804:804:804) (818:818:818)) - (PORT datad (595:595:595) (633:633:633)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1170:1170:1170) (1229:1229:1229)) - (PORT datab (599:599:599) (614:614:614)) - (PORT datac (654:654:654) (698:698:698)) - (PORT datad (866:866:866) (893:893:893)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~5) - (DELAY - (ABSOLUTE - (PORT dataa (692:692:692) (737:737:737)) - (PORT datab (1195:1195:1195) (1210:1210:1210)) - (PORT datac (1157:1157:1157) (1193:1193:1193)) - (PORT datad (590:590:590) (602:602:602)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~4) - (DELAY - (ABSOLUTE - (PORT dataa (901:901:901) (936:936:936)) - (PORT datab (1199:1199:1199) (1253:1253:1253)) - (PORT datac (889:889:889) (931:931:931)) - (PORT datad (630:630:630) (687:687:687)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~7) - (DELAY - (ABSOLUTE - (PORT dataa (591:591:591) (601:601:601)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (172:172:172) (206:206:206)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~8) - (DELAY - (ABSOLUTE - (PORT dataa (921:921:921) (951:951:951)) - (PORT datab (1199:1199:1199) (1252:1252:1252)) - (PORT datac (361:361:361) (394:394:394)) - (PORT datad (1118:1118:1118) (1176:1176:1176)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1169:1169:1169) (1230:1230:1230)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (1158:1158:1158) (1196:1196:1196)) - (PORT datad (863:863:863) (892:892:892)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~10) - (DELAY - (ABSOLUTE - (PORT dataa (206:206:206) (252:252:252)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (652:652:652) (697:697:697)) - (PORT datad (845:845:845) (894:894:894)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (615:615:615) (637:637:637)) - (PORT datab (686:686:686) (707:707:707)) - (PORT datac (378:378:378) (410:410:410)) - (PORT datad (202:202:202) (230:230:230)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (607:607:607) (625:625:625)) - (PORT datac (530:530:530) (542:542:542)) - (PORT datad (838:838:838) (876:876:876)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~29) - (DELAY - (ABSOLUTE - (PORT dataa (929:929:929) (962:962:962)) - (PORT datab (1558:1558:1558) (1661:1661:1661)) - (PORT datac (1407:1407:1407) (1474:1474:1474)) - (PORT datad (200:200:200) (235:235:235)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~13) - (DELAY - (ABSOLUTE - (PORT dataa (619:619:619) (660:660:660)) - (PORT datab (965:965:965) (1060:1060:1060)) - (PORT datac (1732:1732:1732) (1835:1835:1835)) - (PORT datad (1150:1150:1150) (1179:1179:1179)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~49) - (DELAY - (ABSOLUTE - (PORT dataa (1102:1102:1102) (1150:1150:1150)) - (PORT datab (1473:1473:1473) (1583:1583:1583)) - (PORT datac (1614:1614:1614) (1681:1681:1681)) - (PORT datad (1173:1173:1173) (1219:1219:1219)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1405:1405:1405) (1418:1418:1418)) - (PORT datab (1241:1241:1241) (1276:1276:1276)) - (PORT datac (1251:1251:1251) (1275:1275:1275)) - (PORT datad (1260:1260:1260) (1298:1298:1298)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1121:1121:1121) (1151:1151:1151)) - (PORT datac (613:613:613) (636:636:636)) - (PORT datad (172:172:172) (197:197:197)) + (PORT dataa (514:514:514) (593:593:593)) + (PORT datac (268:268:268) (358:358:358)) + (PORT datad (2933:2933:2933) (3111:3111:3111)) (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~28) - (DELAY - (ABSOLUTE - (PORT dataa (236:236:236) (284:284:284)) - (PORT datab (219:219:219) (256:256:256)) - (PORT datac (1148:1148:1148) (1190:1190:1190)) - (PORT datad (194:194:194) (218:218:218)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~35) - (DELAY - (ABSOLUTE - (PORT datab (2004:2004:2004) (2134:2134:2134)) - (PORT datac (1351:1351:1351) (1365:1365:1365)) - (PORT datad (859:859:859) (872:872:872)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~36) - (DELAY - (ABSOLUTE - (PORT dataa (216:216:216) (267:267:267)) - (PORT datab (910:910:910) (941:941:941)) - (PORT datac (621:621:621) (645:645:645)) - (PORT datad (924:924:924) (962:962:962)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1513:1513:1513) (1596:1596:1596)) - (PORT datab (1166:1166:1166) (1202:1202:1202)) - (PORT datac (1104:1104:1104) (1142:1142:1142)) - (PORT datad (548:548:548) (560:560:560)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~31) - (DELAY - (ABSOLUTE - (PORT dataa (614:614:614) (650:650:650)) - (PORT datab (234:234:234) (278:278:278)) - (PORT datac (1132:1132:1132) (1164:1164:1164)) - (PORT datad (196:196:196) (222:222:222)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~29) - (DELAY - (ABSOLUTE - (PORT dataa (1646:1646:1646) (1763:1763:1763)) - (PORT datab (1008:1008:1008) (1101:1101:1101)) - (PORT datac (1033:1033:1033) (1107:1107:1107)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1164:1164:1164) (1208:1208:1208)) - (PORT datab (1537:1537:1537) (1621:1621:1621)) - (PORT datad (201:201:201) (229:229:229)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (888:888:888) (923:923:923)) - (PORT datab (570:570:570) (590:590:590)) - (PORT datac (603:603:603) (628:628:628)) - (PORT datad (595:595:595) (619:619:619)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal33\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1229:1229:1229) (1305:1305:1305)) - (PORT datab (1275:1275:1275) (1372:1372:1372)) - (PORT datac (1155:1155:1155) (1192:1192:1192)) - (PORT datad (709:709:709) (772:772:772)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~0) - (DELAY - (ABSOLUTE - (PORT dataa (690:690:690) (719:719:719)) - (PORT datab (1344:1344:1344) (1367:1367:1367)) - (PORT datac (1222:1222:1222) (1269:1269:1269)) - (PORT datad (1654:1654:1654) (1748:1748:1748)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1005:1005:1005) (1089:1089:1089)) - (PORT datab (887:887:887) (923:923:923)) - (PORT datac (170:170:170) (202:202:202)) - (PORT datad (221:221:221) (249:249:249)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we_lo\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1035:1035:1035) (1133:1133:1133)) - (PORT datac (2185:2185:2185) (2272:2272:2272)) - (PORT datad (654:654:654) (711:711:711)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we_lo\~3) - (DELAY - (ABSOLUTE - (PORT dataa (718:718:718) (782:782:782)) - (PORT datab (1135:1135:1135) (1159:1159:1159)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (1153:1153:1153) (1186:1186:1186)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we_lo\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1016:1016:1016) (1112:1112:1112)) - (PORT datab (668:668:668) (685:685:685)) - (PORT datac (1012:1012:1012) (1113:1113:1113)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (255:255:255)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (180:180:180) (217:217:217)) - (PORT datad (933:933:933) (975:975:975)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_ir\~0) - (DELAY - (ABSOLUTE - (PORT datab (278:278:278) (366:366:366)) - (PORT datac (241:241:241) (319:319:319)) - (PORT datad (246:246:246) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_ir\~1) - (DELAY - (ABSOLUTE - (PORT dataa (941:941:941) (971:971:971)) - (PORT datab (218:218:218) (257:257:257)) - (PORT datac (1095:1095:1095) (1116:1116:1116)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1104:1104:1104) (1192:1192:1192)) - (PORT datab (219:219:219) (258:258:258)) - (PORT datac (650:650:650) (716:716:716)) - (PORT datad (966:966:966) (1077:1077:1077)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (2563:2563:2563) (2705:2705:2705)) - (PORT datab (1595:1595:1595) (1711:1711:1711)) - (PORT datac (194:194:194) (227:227:227)) - (PORT datad (218:218:218) (258:258:258)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1067:1067:1067) (1148:1148:1148)) - (PORT datab (204:204:204) (245:245:245)) - (PORT datac (880:880:880) (911:911:911)) - (PORT datad (824:824:824) (834:834:834)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_ixy_dT5_7) - (DELAY - (ABSOLUTE - (PORT datab (931:931:931) (1002:1002:1002)) - (PORT datad (625:625:625) (662:662:662)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~4) - (DELAY - (ABSOLUTE - (PORT dataa (627:627:627) (663:663:663)) - (PORT datab (924:924:924) (986:986:986)) - (PORT datac (1079:1079:1079) (1113:1113:1113)) - (PORT datad (201:201:201) (229:229:229)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~4) - (DELAY - (ABSOLUTE - (PORT dataa (882:882:882) (951:951:951)) - (PORT datab (902:902:902) (933:933:933)) - (PORT datac (628:628:628) (672:672:672)) - (PORT datad (883:883:883) (909:909:909)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla56M3T3_6) - (DELAY - (ABSOLUTE - (PORT dataa (1992:1992:1992) (2133:2133:2133)) - (PORT datab (907:907:907) (958:958:958)) - (PORT datac (224:224:224) (265:265:265)) - (PORT datad (1139:1139:1139) (1178:1178:1178)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~5) - (DELAY - (ABSOLUTE - (PORT dataa (930:930:930) (951:951:951)) - (PORT datab (917:917:917) (970:970:970)) - (PORT datac (879:879:879) (911:911:911)) - (PORT datad (593:593:593) (627:627:627)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~6) - (DELAY - (ABSOLUTE - (PORT dataa (901:901:901) (926:926:926)) - (PORT datad (181:181:181) (209:209:209)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1074:1074:1074) (1121:1121:1121)) - (PORT datab (894:894:894) (950:950:950)) - (PORT datac (601:601:601) (665:665:665)) - (PORT datad (855:855:855) (908:908:908)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\~16) - (DELAY - (ABSOLUTE - (PORT dataa (2419:2419:2419) (2569:2569:2569)) - (PORT datab (1823:1823:1823) (1925:1925:1925)) - (PORT datac (1074:1074:1074) (1067:1067:1067)) - (PORT datad (1576:1576:1576) (1735:1735:1735)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~11) - (DELAY - (ABSOLUTE - (PORT dataa (827:827:827) (849:849:849)) - (PORT datab (912:912:912) (944:944:944)) - (PORT datac (835:835:835) (868:868:868)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (2421:2421:2421) (2571:2571:2571)) - (PORT datab (2408:2408:2408) (2540:2540:2540)) - (PORT datac (1413:1413:1413) (1473:1473:1473)) - (PORT datad (1573:1573:1573) (1734:1734:1734)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~12) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (229:229:229) (272:272:272)) - (PORT datac (202:202:202) (241:241:241)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1252:1252:1252) (1310:1310:1310)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (832:832:832) (831:831:831)) - (PORT datad (872:872:872) (917:917:917)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (882:882:882) (898:898:898)) - (PORT datab (237:237:237) (281:281:281)) - (PORT datac (619:619:619) (671:671:671)) - (PORT datad (1350:1350:1350) (1391:1391:1391)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~38) - (DELAY - (ABSOLUTE - (PORT dataa (1228:1228:1228) (1318:1318:1318)) - (PORT datab (1384:1384:1384) (1497:1497:1497)) - (PORT datac (857:857:857) (917:917:917)) - (PORT datad (831:831:831) (860:860:860)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~0) - (DELAY - (ABSOLUTE - (PORT dataa (2065:2065:2065) (2136:2136:2136)) - (PORT datab (2504:2504:2504) (2706:2706:2706)) - (PORT datac (2886:2886:2886) (3058:3058:3058)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~24) - (DELAY - (ABSOLUTE - (PORT datab (845:845:845) (894:894:894)) - (PORT datac (990:990:990) (1030:1030:1030)) - (PORT datad (1379:1379:1379) (1425:1425:1425)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (217:217:217) (268:268:268)) - (PORT datac (663:663:663) (700:700:700)) - (PORT datad (1031:1031:1031) (1094:1094:1094)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1328:1328:1328) (1447:1447:1447)) - (PORT datac (1179:1179:1179) (1239:1239:1239)) - (PORT datad (2024:2024:2024) (2146:2146:2146)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1112:1112:1112) (1166:1166:1166)) - (PORT datab (226:226:226) (266:266:266)) - (PORT datac (604:604:604) (622:622:622)) - (PORT datad (1151:1151:1151) (1191:1191:1191)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1111:1111:1111) (1230:1230:1230)) - (PORT datac (1131:1131:1131) (1168:1168:1168)) - (PORT datad (957:957:957) (1017:1017:1017)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3) - (DELAY - (ABSOLUTE - (PORT datab (2109:2109:2109) (2224:2224:2224)) - (PORT datac (925:925:925) (983:983:983)) - (PORT datad (1982:1982:1982) (2072:2072:2072)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (1189:1189:1189) (1250:1250:1250)) - (PORT datab (599:599:599) (617:617:617)) - (PORT datac (871:871:871) (913:913:913)) - (PORT datad (1143:1143:1143) (1193:1193:1193)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (1120:1120:1120) (1154:1154:1154)) - (PORT datab (595:595:595) (609:609:609)) - (PORT datac (1115:1115:1115) (1174:1174:1174)) - (PORT datad (878:878:878) (910:910:910)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1801:1801:1801) (1843:1843:1843)) - (PORT datab (1573:1573:1573) (1608:1608:1608)) - (PORT datad (985:985:985) (1020:1020:1020)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (925:925:925) (957:957:957)) - (PORT datab (1162:1162:1162) (1232:1232:1232)) - (PORT datac (1480:1480:1480) (1554:1554:1554)) - (PORT datad (1102:1102:1102) (1119:1119:1119)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (702:702:702) (740:740:740)) - (PORT datab (913:913:913) (942:942:942)) - (PORT datac (618:618:618) (642:642:642)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (241:241:241)) - (PORT datab (198:198:198) (236:236:236)) - (PORT datac (1512:1512:1512) (1540:1540:1540)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (926:926:926) (959:959:959)) - (PORT datab (887:887:887) (953:953:953)) - (PORT datac (185:185:185) (226:226:226)) - (PORT datad (885:885:885) (902:902:902)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (198:198:198) (241:241:241)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (1725:1725:1725) (1783:1783:1783)) - (PORT datad (330:330:330) (351:351:351)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (1198:1198:1198) (1240:1240:1240)) - (PORT datab (835:835:835) (861:861:861)) - (PORT datac (841:841:841) (865:865:865)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1551:1551:1551) (1610:1610:1610)) - (PORT datab (1763:1763:1763) (1826:1826:1826)) - (PORT datac (2606:2606:2606) (2704:2704:2704)) - (PORT datad (1157:1157:1157) (1177:1177:1177)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (2641:2641:2641) (2744:2744:2744)) - (PORT datab (1587:1587:1587) (1722:1722:1722)) - (PORT datac (639:639:639) (659:659:659)) - (PORT datad (202:202:202) (233:233:233)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (615:615:615) (638:638:638)) - (PORT datab (653:653:653) (683:683:683)) - (PORT datac (637:637:637) (684:684:684)) - (PORT datad (847:847:847) (906:906:906)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_62) - (DELAY - (ABSOLUTE - (PORT datab (707:707:707) (739:739:739)) - (PORT datac (1055:1055:1055) (1068:1068:1068)) - (PORT datad (921:921:921) (956:956:956)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~38) - (DELAY - (ABSOLUTE - (PORT dataa (356:356:356) (401:401:401)) - (PORT datab (1114:1114:1114) (1146:1146:1146)) - (PORT datac (1038:1038:1038) (1080:1080:1080)) - (PORT datad (853:853:853) (854:854:854)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~39) - (DELAY - (ABSOLUTE - (PORT dataa (1748:1748:1748) (1768:1768:1768)) - (PORT datab (881:881:881) (907:907:907)) - (PORT datac (1501:1501:1501) (1630:1630:1630)) - (PORT datad (1129:1129:1129) (1199:1199:1199)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~30) - (DELAY - (ABSOLUTE - (PORT dataa (1137:1137:1137) (1170:1170:1170)) - (PORT datab (1651:1651:1651) (1721:1721:1721)) - (PORT datac (1148:1148:1148) (1186:1186:1186)) - (PORT datad (212:212:212) (247:247:247)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~45) - (DELAY - (ABSOLUTE - (PORT dataa (671:671:671) (702:702:702)) - (PORT datab (1148:1148:1148) (1207:1207:1207)) - (PORT datac (1182:1182:1182) (1237:1237:1237)) - (PORT datad (969:969:969) (1043:1043:1043)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~1) - (DELAY - (ABSOLUTE - (PORT dataa (294:294:294) (365:365:365)) - (PORT datac (1702:1702:1702) (1757:1757:1757)) - (PORT datad (437:437:437) (482:482:482)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~36) - (DELAY - (ABSOLUTE - (PORT dataa (661:661:661) (685:685:685)) - (PORT datab (1154:1154:1154) (1208:1208:1208)) - (PORT datac (1484:1484:1484) (1544:1544:1544)) - (PORT datad (1270:1270:1270) (1331:1331:1331)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~27) - (DELAY - (ABSOLUTE - (PORT dataa (1443:1443:1443) (1501:1501:1501)) - (PORT datab (912:912:912) (961:961:961)) - (PORT datac (896:896:896) (925:925:925)) - (PORT datad (962:962:962) (988:988:988)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~28) - (DELAY - (ABSOLUTE - (PORT dataa (874:874:874) (897:897:897)) - (PORT datac (992:992:992) (1045:1045:1045)) - (PORT datad (172:172:172) (198:198:198)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~37) - (DELAY - (ABSOLUTE - (PORT dataa (1066:1066:1066) (1139:1139:1139)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (1089:1089:1089) (1116:1116:1116)) - (PORT datad (180:180:180) (208:208:208)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~40) - (DELAY - (ABSOLUTE - (PORT dataa (347:347:347) (374:374:374)) - (PORT datab (196:196:196) (234:234:234)) - (PORT datac (345:345:345) (385:385:385)) - (PORT datad (858:858:858) (866:866:866)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~35) - (DELAY - (ABSOLUTE - (PORT dataa (1408:1408:1408) (1444:1444:1444)) - (PORT datab (814:814:814) (844:844:844)) - (PORT datac (1711:1711:1711) (1730:1730:1730)) - (PORT datad (911:911:911) (949:949:949)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~77) - (DELAY - (ABSOLUTE - (PORT dataa (1097:1097:1097) (1124:1124:1124)) - (PORT datab (662:662:662) (693:693:693)) - (PORT datac (868:868:868) (892:892:892)) - (PORT datad (871:871:871) (914:914:914)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~32) - (DELAY - (ABSOLUTE - (PORT dataa (228:228:228) (275:275:275)) - (PORT datab (642:642:642) (663:663:663)) - (PORT datac (1367:1367:1367) (1431:1431:1431)) - (PORT datad (1132:1132:1132) (1158:1158:1158)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla91pla21M4T2_3\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1647:1647:1647) (1764:1764:1764)) - (PORT datab (1009:1009:1009) (1098:1098:1098)) - (PORT datac (1939:1939:1939) (1965:1965:1965)) - (PORT datad (1664:1664:1664) (1726:1726:1726)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~33) - (DELAY - (ABSOLUTE - (PORT dataa (220:220:220) (264:264:264)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (170:170:170) (203:203:203)) - (PORT datad (646:646:646) (703:703:703)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~34) - (DELAY - (ABSOLUTE - (PORT dataa (223:223:223) (275:275:275)) - (PORT datab (645:645:645) (669:669:669)) - (PORT datac (199:199:199) (236:236:236)) - (PORT datad (1191:1191:1191) (1215:1215:1215)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~41) - (DELAY - (ABSOLUTE - (PORT dataa (198:198:198) (241:241:241)) - (PORT datab (1028:1028:1028) (1084:1084:1084)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (593:593:593) (617:617:617)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~10) - (DELAY - (ABSOLUTE - (PORT dataa (896:896:896) (960:960:960)) - (PORT datab (1128:1128:1128) (1156:1156:1156)) - (PORT datac (886:886:886) (918:918:918)) - (PORT datad (1142:1142:1142) (1198:1198:1198)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~11) - (DELAY - (ABSOLUTE - (PORT datab (218:218:218) (256:256:256)) - (PORT datac (593:593:593) (653:653:653)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~3) - (DELAY - (ABSOLUTE - (PORT dataa (214:214:214) (264:264:264)) - (PORT datac (557:557:557) (571:571:571)) - (PORT datad (812:812:812) (882:882:882)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1301:1301:1301) (1363:1363:1363)) - (PORT datab (670:670:670) (695:695:695)) - (PORT datac (195:195:195) (228:228:228)) - (PORT datad (1179:1179:1179) (1216:1216:1216)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~2) - (DELAY - (ABSOLUTE - (PORT dataa (565:565:565) (585:585:585)) - (PORT datac (793:793:793) (849:849:849)) - (PORT datad (781:781:781) (835:835:835)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~5) - (DELAY - (ABSOLUTE - (PORT dataa (914:914:914) (932:932:932)) - (PORT datab (670:670:670) (713:713:713)) - (PORT datac (371:371:371) (406:406:406)) - (PORT datad (595:595:595) (643:643:643)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~45) - (DELAY - (ABSOLUTE - (PORT dataa (627:627:627) (677:677:677)) - (PORT datab (867:867:867) (880:880:880)) - (PORT datac (866:866:866) (892:892:892)) - (PORT datad (646:646:646) (680:680:680)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~46) - (DELAY - (ABSOLUTE - (PORT datab (821:821:821) (842:842:842)) - (PORT datac (201:201:201) (237:237:237)) - (PORT datad (1425:1425:1425) (1509:1509:1509)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~1) - (DELAY - (ABSOLUTE - (PORT dataa (599:599:599) (610:610:610)) - (PORT datab (926:926:926) (956:956:956)) - (PORT datac (586:586:586) (596:596:596)) - (PORT datad (582:582:582) (613:613:613)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~0) - (DELAY - (ABSOLUTE - (PORT dataa (970:970:970) (1011:1011:1011)) - (PORT datab (1561:1561:1561) (1659:1659:1659)) - (PORT datac (842:842:842) (876:876:876)) - (PORT datad (371:371:371) (400:400:400)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~6) - (DELAY - (ABSOLUTE - (PORT dataa (207:207:207) (251:251:251)) - (PORT datab (340:340:340) (371:371:371)) - (PORT datac (211:211:211) (252:252:252)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~4) - (DELAY - (ABSOLUTE - (PORT dataa (926:926:926) (963:963:963)) - (PORT datac (857:857:857) (921:921:921)) - (PORT datad (828:828:828) (859:859:859)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~16) - (DELAY - (ABSOLUTE - (PORT dataa (646:646:646) (681:681:681)) - (PORT datab (1486:1486:1486) (1550:1550:1550)) - (PORT datac (820:820:820) (856:856:856)) - (PORT datad (815:815:815) (871:871:871)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~14) - (DELAY - (ABSOLUTE - (PORT dataa (446:446:446) (504:504:504)) - (PORT datab (946:946:946) (986:986:986)) - (PORT datac (374:374:374) (405:405:405)) - (PORT datad (1915:1915:1915) (2040:2040:2040)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~20) - (DELAY - (ABSOLUTE - (PORT dataa (2472:2472:2472) (2661:2661:2661)) - (PORT datab (554:554:554) (575:575:575)) - (PORT datac (892:892:892) (956:956:956)) - (PORT datad (1125:1125:1125) (1142:1142:1142)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~15) - (DELAY - (ABSOLUTE - (PORT dataa (644:644:644) (677:677:677)) - (PORT datab (581:581:581) (596:596:596)) - (PORT datac (785:785:785) (834:834:834)) - (PORT datad (202:202:202) (230:230:230)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~17) - (DELAY - (ABSOLUTE - (PORT dataa (587:587:587) (619:619:619)) - (PORT datab (876:876:876) (893:893:893)) - (PORT datac (1988:1988:1988) (2046:2046:2046)) - (PORT datad (596:596:596) (620:620:620)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1153:1153:1153) (1167:1167:1167)) - (PORT datab (1567:1567:1567) (1688:1688:1688)) - (PORT datac (635:635:635) (692:692:692)) - (PORT datad (604:604:604) (642:642:642)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~19) - (DELAY - (ABSOLUTE - (PORT dataa (887:887:887) (914:914:914)) - (PORT datab (562:562:562) (571:571:571)) - (PORT datac (611:611:611) (649:649:649)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_pc\~3) - (DELAY - (ABSOLUTE - (PORT dataa (628:628:628) (663:663:663)) - (PORT datab (925:925:925) (986:986:986)) - (PORT datac (532:532:532) (538:538:538)) - (PORT datad (873:873:873) (880:880:880)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_pc) - (DELAY - (ABSOLUTE - (PORT dataa (230:230:230) (276:276:276)) - (PORT datab (643:643:643) (675:675:675)) - (PORT datac (842:842:842) (864:864:864)) - (PORT datad (344:344:344) (366:366:366)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_74) - (DELAY - (ABSOLUTE - (PORT datab (1438:1438:1438) (1508:1508:1508)) - (PORT datac (915:915:915) (945:945:945)) - (PORT datad (819:819:819) (835:835:835)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (229:229:229) (275:275:275)) - (PORT datab (1330:1330:1330) (1334:1334:1334)) - (PORT datac (1375:1375:1375) (1393:1393:1393)) - (PORT datad (312:312:312) (330:330:330)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_75) - (DELAY - (ABSOLUTE - (PORT datab (949:949:949) (999:999:999)) - (PORT datac (1439:1439:1439) (1498:1498:1498)) - (PORT datad (671:671:671) (702:702:702)) - (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -11214,193 +1418,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (974:974:974) (1028:1028:1028)) - (PORT ena (1201:1201:1201) (1184:1184:1184)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (1880:1880:1880) (1905:1905:1905)) - (PORT datab (702:702:702) (730:730:730)) - (PORT datad (1198:1198:1198) (1238:1238:1238)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_63) - (DELAY - (ABSOLUTE - (PORT datab (709:709:709) (737:737:737)) - (PORT datac (1057:1057:1057) (1070:1070:1070)) - (PORT datad (923:923:923) (954:954:954)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[7\]) + (INSTANCE z80_\|interrupts_\|iff1) (DELAY (ABSOLUTE (PORT clk (1541:1541:1541) (1557:1557:1557)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1283:1283:1283) (1286:1286:1286)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~23) - (DELAY - (ABSOLUTE - (PORT datab (738:738:738) (772:772:772)) - (PORT datac (609:609:609) (659:659:659)) - (PORT datad (217:217:217) (286:286:286)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_10\~0) - (DELAY - (ABSOLUTE - (PORT datac (1990:1990:1990) (2095:2095:2095)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_10) - (DELAY - (ABSOLUTE - (PORT clk (1548:1548:1548) (1550:1550:1550)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_9) - (DELAY - (ABSOLUTE - (PORT clk (1548:1548:1548) (1550:1550:1550)) - (PORT asdata (567:567:567) (646:646:646)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|resets_\|DFFE_intr_ff3) - (DELAY - (ABSOLUTE - (PORT clk (1548:1548:1548) (1550:1550:1550)) - (PORT asdata (569:569:569) (648:648:648)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_io_ibuf") - (INSTANCE KEY\[0\]\~input) - (DELAY - (ABSOLUTE - (IOPATH i o (481:481:481) (733:733:733)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE reset) - (DELAY - (ABSOLUTE - (PORT datac (1566:1566:1566) (1527:1527:1527)) - (PORT datad (531:531:531) (524:524:524)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|resets_\|x1\~0) - (DELAY - (ABSOLUTE - (PORT datad (1474:1474:1474) (1549:1549:1549)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|fpga_reset) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1542:1542:1542)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_clkctrl") - (INSTANCE z80_\|fpga_reset\~clkctrl) - (DELAY - (ABSOLUTE - (PORT inclk[0] (727:727:727) (752:752:752)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|resets_\|x1) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1527:1527:1527)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1883:1883:1883) (1869:1869:1869)) + (PORT clrn (1224:1224:1224) (1261:1261:1261)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -11409,1430 +1432,6 @@ (HOLD d (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|resets_\|clrpc_int\~0) - (DELAY - (ABSOLUTE - (PORT dataa (649:649:649) (728:728:728)) - (PORT datab (605:605:605) (665:665:665)) - (PORT datad (1168:1168:1168) (1217:1217:1217)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|resets_\|clrpc_int) - (DELAY - (ABSOLUTE - (PORT clk (1548:1548:1548) (1550:1550:1550)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1597:1597:1597) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|resets_\|clrpc\~0) - (DELAY - (ABSOLUTE - (PORT dataa (251:251:251) (340:340:340)) - (PORT datab (253:253:253) (339:339:339)) - (PORT datad (217:217:217) (285:285:285)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[7\]) - (DELAY - (ABSOLUTE - (PORT datac (657:657:657) (695:695:695)) - (PORT datad (609:609:609) (638:638:638)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_apin_mux\~1) - (DELAY - (ABSOLUTE - (PORT dataa (2470:2470:2470) (2664:2664:2664)) - (PORT datac (891:891:891) (959:959:959)) - (PORT datad (1997:1997:1997) (2087:2087:2087)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (364:364:364) (394:394:394)) - (PORT datab (558:558:558) (580:580:580)) - (PORT datac (844:844:844) (879:879:879)) - (PORT datad (1124:1124:1124) (1141:1141:1141)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1113:1113:1113) (1149:1149:1149)) - (PORT datab (1162:1162:1162) (1184:1184:1184)) - (PORT datac (794:794:794) (810:810:810)) - (PORT datad (642:642:642) (654:654:654)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (985:985:985) (1053:1053:1053)) - (PORT datab (1645:1645:1645) (1657:1657:1657)) - (PORT datac (173:173:173) (207:207:207)) - (PORT datad (1141:1141:1141) (1167:1167:1167)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1232:1232:1232) (1303:1303:1303)) - (PORT datab (1001:1001:1001) (1111:1111:1111)) - (PORT datac (655:655:655) (722:722:722)) - (PORT datad (1242:1242:1242) (1330:1330:1330)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~9) - (DELAY - (ABSOLUTE - (PORT dataa (789:789:789) (798:798:798)) - (PORT datab (653:653:653) (676:676:676)) - (PORT datac (834:834:834) (870:870:870)) - (PORT datad (1032:1032:1032) (1091:1091:1091)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~10) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (714:714:714) (749:749:749)) - (PORT datac (201:201:201) (236:236:236)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~11) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (246:246:246)) - (PORT datac (180:180:180) (218:218:218)) - (PORT datad (538:538:538) (562:562:562)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1254:1254:1254) (1307:1307:1307)) - (PORT datab (845:845:845) (854:854:854)) - (PORT datac (835:835:835) (832:832:832)) - (PORT datad (874:874:874) (917:917:917)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1560:1560:1560)) - (PORT ena (2152:2152:2152) (2220:2220:2220)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~6) - (DELAY - (ABSOLUTE - (PORT dataa (407:407:407) (434:434:434)) - (PORT datab (1814:1814:1814) (1895:1895:1895)) - (PORT datac (201:201:201) (236:236:236)) - (PORT datad (644:644:644) (699:699:699)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1218:1218:1218) (1307:1307:1307)) - (PORT datab (2009:2009:2009) (2129:2129:2129)) - (PORT datac (1296:1296:1296) (1407:1407:1407)) - (PORT datad (2028:2028:2028) (2149:2149:2149)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~8) - (DELAY - (ABSOLUTE - (PORT dataa (384:384:384) (412:412:412)) - (PORT datab (213:213:213) (258:258:258)) - (PORT datac (1100:1100:1100) (1149:1149:1149)) - (PORT datad (1205:1205:1205) (1229:1229:1229)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~9) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (265:265:265)) - (PORT datab (1709:1709:1709) (1797:1797:1797)) - (PORT datac (549:549:549) (562:562:562)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~10) - (DELAY - (ABSOLUTE - (PORT datab (988:988:988) (1021:1021:1021)) - (PORT datac (1126:1126:1126) (1145:1145:1145)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1002:1002:1002) (1072:1072:1072)) - (PORT datad (1126:1126:1126) (1143:1143:1143)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1541:1541:1541) (1557:1557:1557)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1283:1283:1283) (1286:1286:1286)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_54) - (DELAY - (ABSOLUTE - (PORT datab (1546:1546:1546) (1602:1602:1602)) - (PORT datac (1206:1206:1206) (1268:1268:1268)) - (PORT datad (1073:1073:1073) (1099:1099:1099)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_58) - (DELAY - (ABSOLUTE - (PORT datab (1543:1543:1543) (1602:1602:1602)) - (PORT datac (1215:1215:1215) (1279:1279:1279)) - (PORT datad (985:985:985) (1033:1033:1033)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_55) - (DELAY - (ABSOLUTE - (PORT datab (1542:1542:1542) (1602:1602:1602)) - (PORT datac (1217:1217:1217) (1279:1279:1279)) - (PORT datad (1074:1074:1074) (1100:1100:1100)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1531:1531:1531)) - (PORT asdata (1413:1413:1413) (1448:1448:1448)) - (PORT ena (1734:1734:1734) (1719:1719:1719)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_59) - (DELAY - (ABSOLUTE - (PORT datab (1547:1547:1547) (1607:1607:1607)) - (PORT datac (1199:1199:1199) (1261:1261:1261)) - (PORT datad (990:990:990) (1037:1037:1037)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1531:1531:1531)) - (PORT asdata (1413:1413:1413) (1447:1447:1447)) - (PORT ena (1413:1413:1413) (1385:1385:1385)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (870:870:870) (916:916:916)) - (PORT datab (971:971:971) (1024:1024:1024)) - (PORT datad (215:215:215) (283:283:283)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_51) - (DELAY - (ABSOLUTE - (PORT datab (1381:1381:1381) (1428:1428:1428)) - (PORT datac (1185:1185:1185) (1207:1207:1207)) - (PORT datad (589:589:589) (605:605:605)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (726:726:726) (753:753:753)) - (PORT ena (811:811:811) (804:804:804)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_de2\~4) - (DELAY - (ABSOLUTE - (PORT dataa (372:372:372) (407:407:407)) - (PORT datab (224:224:224) (272:272:272)) - (PORT datac (222:222:222) (301:301:301)) - (PORT datad (1218:1218:1218) (1299:1299:1299)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_46) - (DELAY - (ABSOLUTE - (PORT datab (1209:1209:1209) (1234:1234:1234)) - (PORT datac (637:637:637) (665:665:665)) - (PORT datad (1346:1346:1346) (1393:1393:1393)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_47) - (DELAY - (ABSOLUTE - (PORT datab (1212:1212:1212) (1239:1239:1239)) - (PORT datac (637:637:637) (665:665:665)) - (PORT datad (1342:1342:1342) (1391:1391:1391)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (725:725:725) (752:752:752)) - (PORT ena (841:841:841) (846:846:846)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (244:244:244) (331:331:331)) - (PORT datab (261:261:261) (314:314:314)) - (PORT datad (232:232:232) (270:270:270)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_71\~2) - (DELAY - (ABSOLUTE - (PORT datac (898:898:898) (941:941:941)) - (PORT datad (1326:1326:1326) (1381:1381:1381)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_43\~0) - (DELAY - (ABSOLUTE - (PORT dataa (699:699:699) (770:770:770)) - (PORT datab (1175:1175:1175) (1215:1215:1215)) - (PORT datac (195:195:195) (238:238:238)) - (PORT datad (1436:1436:1436) (1519:1519:1519)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1520:1520:1520) (1534:1534:1534)) - (PORT asdata (1192:1192:1192) (1227:1227:1227)) - (PORT ena (1263:1263:1263) (1264:1264:1264)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_39\~0) - (DELAY - (ABSOLUTE - (PORT dataa (695:695:695) (765:765:765)) - (PORT datab (1172:1172:1172) (1214:1214:1214)) - (PORT datac (195:195:195) (237:237:237)) - (PORT datad (1438:1438:1438) (1518:1518:1518)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1520:1520:1520) (1534:1534:1534)) - (PORT asdata (1193:1193:1193) (1225:1225:1225)) - (PORT ena (1207:1207:1207) (1190:1190:1190)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (467:467:467) (505:505:505)) - (PORT datab (241:241:241) (323:323:323)) - (PORT datad (640:640:640) (663:663:663)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_83) - (DELAY - (ABSOLUTE - (PORT dataa (628:628:628) (658:658:658)) - (PORT datab (950:950:950) (994:994:994)) - (PORT datad (672:672:672) (698:698:698)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1544:1544:1544)) - (PORT asdata (1673:1673:1673) (1678:1678:1678)) - (PORT ena (1499:1499:1499) (1507:1507:1507)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (656:656:656) (674:674:674)) - (PORT datab (1409:1409:1409) (1424:1424:1424)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_79\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1144:1144:1144) (1180:1180:1180)) - (PORT datab (1171:1171:1171) (1213:1213:1213)) - (PORT datac (195:195:195) (238:238:238)) - (PORT datad (664:664:664) (715:715:715)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1545:1545:1545)) - (PORT asdata (1225:1225:1225) (1263:1263:1263)) - (PORT ena (1220:1220:1220) (1214:1214:1214)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~39) - (DELAY - (ABSOLUTE - (PORT dataa (911:911:911) (962:962:962)) - (PORT datab (414:414:414) (473:473:473)) - (PORT datac (913:913:913) (963:963:963)) - (PORT datad (609:609:609) (629:629:629)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_iy\~2) - (DELAY - (ABSOLUTE - (PORT dataa (896:896:896) (973:973:973)) - (PORT datab (938:938:938) (1019:1019:1019)) - (PORT datac (1135:1135:1135) (1179:1179:1179)) - (PORT datad (378:378:378) (412:412:412)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_70) - (DELAY - (ABSOLUTE - (PORT datab (929:929:929) (993:993:993)) - (PORT datac (1324:1324:1324) (1357:1357:1357)) - (PORT datad (891:891:891) (947:947:947)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_67\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1168:1168:1168) (1265:1265:1265)) - (PORT datab (1178:1178:1178) (1216:1216:1216)) - (PORT datac (195:195:195) (239:239:239)) - (PORT datad (671:671:671) (719:719:719)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1544:1544:1544)) - (PORT asdata (1674:1674:1674) (1676:1676:1676)) - (PORT ena (1231:1231:1231) (1217:1217:1217)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_71) - (DELAY - (ABSOLUTE - (PORT dataa (1791:1791:1791) (1805:1805:1805)) - (PORT datab (916:916:916) (986:986:986)) - (PORT datad (905:905:905) (958:958:958)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1545:1545:1545)) - (PORT asdata (1226:1226:1226) (1265:1265:1265)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~38) - (DELAY - (ABSOLUTE - (PORT dataa (433:433:433) (465:465:465)) - (PORT datab (634:634:634) (665:665:665)) - (PORT datad (357:357:357) (410:410:410)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_31) - (DELAY - (ABSOLUTE - (PORT dataa (1721:1721:1721) (1780:1780:1780)) - (PORT datab (1171:1171:1171) (1225:1225:1225)) - (PORT datad (792:792:792) (797:797:797)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1545:1545:1545)) - (PORT asdata (1407:1407:1407) (1434:1434:1434)) - (PORT ena (821:821:821) (834:834:834)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (841:841:841) (868:868:868)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_35) - (DELAY - (ABSOLUTE - (PORT datab (1032:1032:1032) (1065:1065:1065)) - (PORT datac (905:905:905) (951:951:951)) - (PORT datad (876:876:876) (937:937:937)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1266:1266:1266) (1269:1269:1269)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (407:407:407) (468:468:468)) - (PORT datab (590:590:590) (630:630:630)) - (PORT datad (216:216:216) (284:284:284)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~40) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (200:200:200) (239:239:239)) - (PORT datac (170:170:170) (203:203:203)) - (PORT datad (530:530:530) (540:540:540)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~41) - (DELAY - (ABSOLUTE - (PORT dataa (658:658:658) (699:699:699)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datad (780:780:780) (810:810:810)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~42) - (DELAY - (ABSOLUTE - (PORT dataa (373:373:373) (397:397:397)) - (PORT datab (625:625:625) (654:654:654)) - (PORT datac (1393:1393:1393) (1416:1416:1416)) - (PORT datad (618:618:618) (673:673:673)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (1402:1402:1402) (1441:1441:1441)) - (PORT ena (1201:1201:1201) (1184:1184:1184)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (220:220:220) (264:264:264)) - (PORT datab (1232:1232:1232) (1270:1270:1270)) - (PORT datad (658:658:658) (688:688:688)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~8) - (DELAY - (ABSOLUTE - (PORT datab (671:671:671) (703:703:703)) - (PORT datac (1147:1147:1147) (1188:1188:1188)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1541:1541:1541) (1557:1557:1557)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1283:1283:1283) (1286:1286:1286)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (1460:1460:1460) (1492:1492:1492)) - (PORT ena (811:811:811) (804:804:804)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (1460:1460:1460) (1491:1491:1491)) - (PORT ena (841:841:841) (846:846:846)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (244:244:244) (331:331:331)) - (PORT datab (262:262:262) (315:315:315)) - (PORT datad (233:233:233) (271:271:271)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1514:1514:1514) (1528:1528:1528)) - (PORT asdata (1185:1185:1185) (1213:1213:1213)) - (PORT ena (816:816:816) (813:813:813)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|db\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1182:1182:1182) (1227:1227:1227)) - (PORT datab (1541:1541:1541) (1602:1602:1602)) - (PORT datad (1074:1074:1074) (1100:1100:1100)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1531:1531:1531)) - (PORT asdata (1483:1483:1483) (1519:1519:1519)) - (PORT ena (1413:1413:1413) (1385:1385:1385)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (639:639:639) (688:688:688)) - (PORT datab (1088:1088:1088) (1097:1097:1097)) - (PORT datad (940:940:940) (980:980:980)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1545:1545:1545)) - (PORT asdata (1236:1236:1236) (1247:1247:1247)) - (PORT ena (1220:1220:1220) (1214:1214:1214)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1545:1545:1545)) - (PORT asdata (1237:1237:1237) (1246:1246:1246)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (641:641:641) (696:696:696)) - (PORT datab (241:241:241) (323:323:323)) - (PORT datad (367:367:367) (395:395:395)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1534:1534:1534)) - (PORT asdata (1461:1461:1461) (1534:1534:1534)) - (PORT ena (1505:1505:1505) (1518:1518:1518)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (347:347:347) (372:372:372)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1520:1520:1520) (1534:1534:1534)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1263:1263:1263) (1264:1264:1264)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1534:1534:1534)) - (PORT asdata (1458:1458:1458) (1530:1530:1530)) - (PORT ena (1407:1407:1407) (1382:1382:1382)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (430:430:430) (499:499:499)) - (PORT datab (652:652:652) (676:676:676)) - (PORT datad (827:827:827) (837:837:837)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1212:1212:1212) (1256:1256:1256)) - (PORT datab (919:919:919) (944:944:944)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1520:1520:1520) (1534:1534:1534)) - (PORT asdata (939:939:939) (964:964:964)) - (PORT ena (1207:1207:1207) (1190:1190:1190)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (455:455:455) (491:491:491)) - (PORT datab (1133:1133:1133) (1178:1178:1178)) - (PORT datad (539:539:539) (559:559:559)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1545:1545:1545)) - (PORT asdata (1719:1719:1719) (1765:1765:1765)) - (PORT ena (821:821:821) (834:834:834)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1545:1545:1545)) - (PORT asdata (1719:1719:1719) (1768:1768:1768)) - (PORT ena (1266:1266:1266) (1269:1269:1269)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (412:412:412) (470:470:470)) - (PORT datab (585:585:585) (623:623:623)) - (PORT datad (216:216:216) (283:283:283)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (607:607:607) (635:635:635)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (344:344:344) (368:368:368)) - (PORT datad (597:597:597) (607:607:607)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (1201:1201:1201) (1235:1235:1235)) - (PORT datab (197:197:197) (237:237:237)) - (PORT datac (1104:1104:1104) (1151:1151:1151)) - (PORT datad (820:820:820) (839:839:839)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (1589:1589:1589) (1608:1608:1608)) - (PORT ena (1201:1201:1201) (1184:1184:1184)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1178:1178:1178) (1198:1198:1198)) - (PORT datab (697:697:697) (724:724:724)) - (PORT datad (1194:1194:1194) (1230:1230:1230)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~1) - (DELAY - (ABSOLUTE - (PORT datab (243:243:243) (325:325:325)) - (PORT datac (706:706:706) (737:737:737)) - (PORT datad (842:842:842) (876:876:876)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~72) - (DELAY - (ABSOLUTE - (PORT dataa (938:938:938) (985:985:985)) - (PORT datab (912:912:912) (985:985:985)) - (PORT datac (1500:1500:1500) (1547:1547:1547)) - (PORT datad (662:662:662) (730:730:730)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_clkctrl") (INSTANCE ula_\|pll_\|altpll_component\|auto_generated\|wire_pll1_clk\[0\]\~clkctrl) @@ -12842,103 +1441,12 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add0\~14) - (DELAY - (ABSOLUTE - (PORT datab (1393:1393:1393) (1462:1462:1462)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datab cout (446:446:446) (318:318:318)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add0\~16) - (DELAY - (ABSOLUTE - (PORT dataa (265:265:265) (352:352:352)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH dataa cout (436:436:436) (315:315:315)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vga_hc\~2) - (DELAY - (ABSOLUTE - (PORT datac (830:830:830) (872:872:872)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_hc\[8\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add0\~18) - (DELAY - (ABSOLUTE - (PORT datad (660:660:660) (722:722:722)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vga_hc\~1) - (DELAY - (ABSOLUTE - (PORT datab (230:230:230) (272:272:272)) - (PORT datad (560:560:560) (588:588:588)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_hc\[9\]) - (DELAY - (ABSOLUTE - (PORT clk (1536:1536:1536) (1548:1548:1548)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|Add0\~0) (DELAY (ABSOLUTE - (PORT datab (1071:1071:1071) (1110:1110:1110)) + (PORT datab (387:387:387) (463:463:463)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -12950,9 +1458,9 @@ (INSTANCE ula_\|video_\|vga_hc\~3) (DELAY (ABSOLUTE - (PORT datac (830:830:830) (865:865:865)) - (PORT datad (903:903:903) (941:941:941)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT datab (348:348:348) (373:373:373)) + (PORT datad (862:862:862) (885:885:885)) + (IOPATH datab combout (306:306:306) (311:311:311)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -12962,13 +1470,13 @@ (INSTANCE ula_\|video_\|vga_hc\[0\]) (DELAY (ABSOLUTE - (PORT clk (1538:1538:1538) (1550:1550:1550)) - (PORT d (74:74:74) (91:91:91)) + (PORT clk (1904:1904:1904) (1926:1926:1926)) + (PORT asdata (1713:1713:1713) (1720:1720:1720)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) ) ) (CELL @@ -12976,7 +1484,7 @@ (INSTANCE ula_\|video_\|Add0\~2) (DELAY (ABSOLUTE - (PORT datab (672:672:672) (727:727:727)) + (PORT datab (1218:1218:1218) (1298:1298:1298)) (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -12985,28 +1493,18 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vga_hc\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (590:590:590) (612:612:612)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|video_\|vga_hc\[1\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1549:1549:1549)) - (PORT d (74:74:74) (91:91:91)) + (PORT clk (1538:1538:1538) (1550:1550:1550)) + (PORT asdata (851:851:851) (856:856:856)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) ) ) (CELL @@ -13014,7 +1512,7 @@ (INSTANCE ula_\|video_\|Add0\~4) (DELAY (ABSOLUTE - (PORT datab (410:410:410) (485:485:485)) + (PORT datab (1426:1426:1426) (1470:1470:1470)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -13028,8 +1526,8 @@ (INSTANCE ula_\|video_\|vga_hc\[2\]) (DELAY (ABSOLUTE - (PORT clk (1533:1533:1533) (1545:1545:1545)) - (PORT asdata (663:663:663) (679:679:679)) + (PORT clk (1538:1538:1538) (1550:1550:1550)) + (PORT asdata (1240:1240:1240) (1252:1252:1252)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -13042,37 +1540,27 @@ (INSTANCE ula_\|video_\|Add0\~6) (DELAY (ABSOLUTE - (PORT datab (693:693:693) (745:745:745)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (654:654:654) (716:716:716)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vga_hc\[3\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (558:558:558) (581:581:581)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|video_\|vga_hc\[3\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1549:1549:1549)) - (PORT d (74:74:74) (91:91:91)) + (PORT clk (1538:1538:1538) (1551:1551:1551)) + (PORT asdata (872:872:872) (875:875:875)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) ) ) (CELL @@ -13080,7 +1568,7 @@ (INSTANCE ula_\|video_\|Add0\~8) (DELAY (ABSOLUTE - (PORT dataa (1094:1094:1094) (1127:1127:1127)) + (PORT dataa (1285:1285:1285) (1353:1353:1353)) (IOPATH dataa combout (354:354:354) (367:367:367)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -13094,8 +1582,8 @@ (INSTANCE ula_\|video_\|vga_hc\[4\]) (DELAY (ABSOLUTE - (PORT clk (1533:1533:1533) (1545:1545:1545)) - (PORT asdata (662:662:662) (678:678:678)) + (PORT clk (1538:1538:1538) (1551:1551:1551)) + (PORT asdata (515:515:515) (545:545:545)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -13103,61 +1591,14 @@ (HOLD asdata (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Equal0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1251:1251:1251) (1340:1340:1340)) - (PORT datab (983:983:983) (1062:1062:1062)) - (PORT datac (978:978:978) (1050:1050:1050)) - (PORT datad (282:282:282) (366:366:366)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Equal0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (687:687:687) (737:737:737)) - (PORT datab (1394:1394:1394) (1464:1464:1464)) - (PORT datad (941:941:941) (937:937:937)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Equal1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (447:447:447) (523:523:523)) - (PORT datab (684:684:684) (758:758:758)) - (PORT datac (646:646:646) (716:716:716)) - (PORT datad (570:570:570) (576:576:576)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|Add0\~10) (DELAY (ABSOLUTE - (PORT dataa (684:684:684) (734:734:734)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (693:693:693) (752:752:752)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -13169,9 +1610,9 @@ (INSTANCE ula_\|video_\|vga_hc\~0) (DELAY (ABSOLUTE - (PORT datac (833:833:833) (875:875:875)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT datab (559:559:559) (576:576:576)) + (PORT datad (862:862:862) (885:885:885)) + (IOPATH datab combout (306:306:306) (311:311:311)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -13181,13 +1622,13 @@ (INSTANCE ula_\|video_\|vga_hc\[5\]) (DELAY (ABSOLUTE - (PORT clk (1533:1533:1533) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) + (PORT clk (1538:1538:1538) (1551:1551:1551)) + (PORT asdata (834:834:834) (842:842:842)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) ) ) (CELL @@ -13195,7 +1636,7 @@ (INSTANCE ula_\|video_\|Add0\~12) (DELAY (ABSOLUTE - (PORT dataa (629:629:629) (686:686:686)) + (PORT dataa (415:415:415) (498:498:498)) (IOPATH dataa combout (354:354:354) (367:367:367)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -13209,8 +1650,8 @@ (INSTANCE ula_\|video_\|vga_hc\[6\]) (DELAY (ABSOLUTE - (PORT clk (1533:1533:1533) (1545:1545:1545)) - (PORT asdata (516:516:516) (547:547:547)) + (PORT clk (1538:1538:1538) (1551:1551:1551)) + (PORT asdata (656:656:656) (679:679:679)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -13218,13 +1659,27 @@ (HOLD asdata (posedge clk) (157:157:157)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add0\~14) + (DELAY + (ABSOLUTE + (PORT datab (412:412:412) (488:488:488)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|video_\|vga_hc\[7\]) (DELAY (ABSOLUTE - (PORT clk (1533:1533:1533) (1545:1545:1545)) - (PORT asdata (869:869:869) (872:872:872)) + (PORT clk (1538:1538:1538) (1551:1551:1551)) + (PORT asdata (658:658:658) (673:673:673)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -13234,36 +1689,220 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add1\~0) + (INSTANCE ula_\|video_\|Add0\~16) (DELAY (ABSOLUTE - (PORT datab (720:720:720) (795:795:795)) + (PORT datab (433:433:433) (508:508:508)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add1\~2) - (DELAY - (ABSOLUTE - (PORT dataa (707:707:707) (782:782:782)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH dataa cout (436:436:436) (315:315:315)) - (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vga_hc\~2) + (DELAY + (ABSOLUTE + (PORT datab (343:343:343) (375:375:375)) + (PORT datad (891:891:891) (915:915:915)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vga_hc\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1538:1538:1538) (1550:1550:1550)) + (PORT asdata (1614:1614:1614) (1607:1607:1607)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add0\~18) + (DELAY + (ABSOLUTE + (PORT datad (240:240:240) (309:309:309)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vga_hc\~1) + (DELAY + (ABSOLUTE + (PORT dataa (808:808:808) (822:822:822)) + (PORT datad (861:861:861) (880:880:880)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vga_hc\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1538:1538:1538) (1551:1551:1551)) + (PORT asdata (655:655:655) (676:676:676)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (768:768:768) (851:851:851)) + (PORT datab (749:749:749) (820:820:820)) + (PORT datac (1156:1156:1156) (1220:1220:1220)) + (PORT datad (681:681:681) (752:752:752)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1276:1276:1276) (1368:1368:1368)) + (PORT datab (1370:1370:1370) (1423:1423:1423)) + (PORT datac (344:344:344) (367:367:367)) + (PORT datad (899:899:899) (950:950:950)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1019:1019:1019) (1112:1112:1112)) + (PORT datab (706:706:706) (782:782:782)) + (PORT datac (644:644:644) (704:704:704)) + (PORT datad (540:540:540) (562:562:562)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (977:977:977) (1037:1037:1037)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vga_vc\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (371:371:371) (416:416:416)) + (PORT datab (913:913:913) (938:938:938)) + (PORT datac (345:345:345) (367:367:367)) + (PORT datad (939:939:939) (996:996:996)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vga_vc\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1536:1536:1536) (1549:1549:1549)) + (PORT asdata (922:922:922) (937:937:937)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add1\~2) + (DELAY + (ABSOLUTE + (PORT datab (908:908:908) (966:966:966)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vga_vc\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (595:595:595) (634:634:634)) + (PORT datab (569:569:569) (587:587:587)) + (PORT datad (1285:1285:1285) (1292:1292:1292)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vga_vc\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1536:1536:1536) (1549:1549:1549)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|Add1\~4) (DELAY (ABSOLUTE - (PORT dataa (679:679:679) (747:747:747)) + (PORT dataa (717:717:717) (778:778:778)) (IOPATH dataa combout (354:354:354) (367:367:367)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -13277,12 +1916,23 @@ (INSTANCE ula_\|video_\|vga_vc\[2\]\~2) (DELAY (ABSOLUTE - (PORT dataa (517:517:517) (564:564:564)) - (PORT datab (595:595:595) (609:609:609)) - (PORT datad (899:899:899) (922:922:922)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (353:353:353) (369:369:369)) + (PORT dataa (370:370:370) (412:412:412)) + (PORT datab (913:913:913) (939:939:939)) + (PORT datac (1176:1176:1176) (1221:1221:1221)) + (PORT datad (175:175:175) (200:200:200)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vga_vc\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (562:562:562) (574:574:574)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -13292,7 +1942,7 @@ (INSTANCE ula_\|video_\|vga_vc\[2\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1536:1536:1536) (1549:1549:1549)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -13306,7 +1956,7 @@ (INSTANCE ula_\|video_\|Add1\~6) (DELAY (ABSOLUTE - (PORT dataa (712:712:712) (782:782:782)) + (PORT dataa (682:682:682) (759:759:759)) (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -13320,13 +1970,13 @@ (INSTANCE ula_\|video_\|vga_vc\[3\]\~3) (DELAY (ABSOLUTE - (PORT dataa (616:616:616) (648:648:648)) - (PORT datab (645:645:645) (692:692:692)) - (PORT datac (679:679:679) (747:747:747)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (685:685:685) (760:760:760)) + (PORT datab (913:913:913) (938:938:938)) + (PORT datac (173:173:173) (206:206:206)) + (PORT datad (342:342:342) (369:369:369)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -13336,8 +1986,8 @@ (INSTANCE ula_\|video_\|vga_vc\[3\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT asdata (1361:1361:1361) (1352:1352:1352)) + (PORT clk (1536:1536:1536) (1549:1549:1549)) + (PORT asdata (1509:1509:1509) (1524:1524:1524)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -13350,9 +2000,9 @@ (INSTANCE ula_\|video_\|Add1\~8) (DELAY (ABSOLUTE - (PORT datab (680:680:680) (762:762:762)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (752:752:752) (814:814:814)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -13364,9 +2014,9 @@ (INSTANCE ula_\|video_\|vga_vc\[4\]\~5) (DELAY (ABSOLUTE - (PORT dataa (516:516:516) (565:565:565)) - (PORT datab (625:625:625) (643:643:643)) - (PORT datad (899:899:899) (921:921:921)) + (PORT dataa (1138:1138:1138) (1176:1176:1176)) + (PORT datab (824:824:824) (840:840:840)) + (PORT datad (890:890:890) (916:916:916)) (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -13379,7 +2029,7 @@ (INSTANCE ula_\|video_\|vga_vc\[4\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1538:1538:1538) (1550:1550:1550)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -13393,51 +2043,21 @@ (INSTANCE ula_\|video_\|Add1\~10) (DELAY (ABSOLUTE - (PORT dataa (690:690:690) (785:785:785)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (711:711:711) (771:771:771)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vga_vc\[5\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (616:616:616) (645:645:645)) - (PORT datab (645:645:645) (689:689:689)) - (PORT datac (698:698:698) (778:778:778)) - (PORT datad (175:175:175) (199:199:199)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_vc\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT asdata (884:884:884) (883:883:883)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|Add1\~12) (DELAY (ABSOLUTE - (PORT datab (720:720:720) (789:789:789)) + (PORT datab (1187:1187:1187) (1234:1234:1234)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -13451,9 +2071,9 @@ (INSTANCE ula_\|video_\|vga_vc\[6\]\~4) (DELAY (ABSOLUTE - (PORT dataa (519:519:519) (562:562:562)) - (PORT datab (588:588:588) (607:607:607)) - (PORT datad (902:902:902) (917:917:917)) + (PORT dataa (1139:1139:1139) (1176:1176:1176)) + (PORT datab (827:827:827) (836:836:836)) + (PORT datad (892:892:892) (916:916:916)) (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -13466,7 +2086,7 @@ (INSTANCE ula_\|video_\|vga_vc\[6\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1538:1538:1538) (1550:1550:1550)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -13480,7 +2100,7 @@ (INSTANCE ula_\|video_\|Add1\~14) (DELAY (ABSOLUTE - (PORT datab (691:691:691) (762:762:762)) + (PORT datab (1131:1131:1131) (1181:1181:1181)) (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -13494,9 +2114,9 @@ (INSTANCE ula_\|video_\|vga_vc\[7\]\~6) (DELAY (ABSOLUTE - (PORT dataa (517:517:517) (566:566:566)) - (PORT datab (1177:1177:1177) (1178:1178:1178)) - (PORT datad (900:900:900) (920:920:920)) + (PORT dataa (1137:1137:1137) (1176:1176:1176)) + (PORT datab (861:861:861) (876:876:876)) + (PORT datad (890:890:890) (917:917:917)) (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -13509,7 +2129,7 @@ (INSTANCE ula_\|video_\|vga_vc\[7\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1538:1538:1538) (1550:1550:1550)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -13523,9 +2143,9 @@ (INSTANCE ula_\|video_\|Add1\~16) (DELAY (ABSOLUTE - (PORT datab (743:743:743) (817:817:817)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (990:990:990) (1090:1090:1090)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -13537,9 +2157,9 @@ (INSTANCE ula_\|video_\|vga_vc\[8\]\~7) (DELAY (ABSOLUTE - (PORT dataa (517:517:517) (558:558:558)) - (PORT datab (998:998:998) (1000:1000:1000)) - (PORT datad (899:899:899) (916:916:916)) + (PORT dataa (597:597:597) (632:632:632)) + (PORT datab (1128:1128:1128) (1140:1140:1140)) + (PORT datad (1288:1288:1288) (1290:1290:1290)) (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -13552,7 +2172,7 @@ (INSTANCE ula_\|video_\|vga_vc\[8\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1536:1536:1536) (1549:1549:1549)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -13566,7 +2186,7 @@ (INSTANCE ula_\|video_\|Add1\~18) (DELAY (ABSOLUTE - (PORT datad (650:650:650) (707:707:707)) + (PORT datad (1249:1249:1249) (1331:1331:1331)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) ) @@ -13577,11 +2197,11 @@ (INSTANCE ula_\|video_\|vga_vc\[9\]\~9) (DELAY (ABSOLUTE - (PORT dataa (518:518:518) (565:565:565)) - (PORT datab (1005:1005:1005) (1007:1007:1007)) - (PORT datad (899:899:899) (922:922:922)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) + (PORT dataa (575:575:575) (606:606:606)) + (PORT datab (623:623:623) (647:647:647)) + (PORT datad (1108:1108:1108) (1134:1134:1134)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -13592,7 +2212,7 @@ (INSTANCE ula_\|video_\|vga_vc\[9\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1538:1538:1538) (1550:1550:1550)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -13603,31 +2223,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Equal2\~0) + (INSTANCE ula_\|video_\|Equal3\~0) (DELAY (ABSOLUTE - (PORT dataa (272:272:272) (361:361:361)) - (PORT datab (270:270:270) (356:356:356)) - (PORT datac (263:263:263) (343:343:343)) - (PORT datad (244:244:244) (317:317:317)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (934:934:934) (998:998:998)) + (PORT datab (1174:1174:1174) (1232:1232:1232)) + (PORT datac (948:948:948) (1009:1009:1009)) + (PORT datad (1182:1182:1182) (1234:1234:1234)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Equal3\~0) + (INSTANCE ula_\|video_\|Equal2\~0) (DELAY (ABSOLUTE - (PORT dataa (1173:1173:1173) (1262:1262:1262)) - (PORT datab (846:846:846) (922:922:922)) - (PORT datac (628:628:628) (679:679:679)) - (PORT datad (673:673:673) (746:746:746)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) + (PORT dataa (459:459:459) (520:520:520)) + (PORT datab (288:288:288) (373:373:373)) + (PORT datac (404:404:404) (466:466:466)) + (PORT datad (384:384:384) (442:442:442)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -13638,10 +2258,10 @@ (INSTANCE ula_\|video_\|Equal3\~1) (DELAY (ABSOLUTE - (PORT dataa (635:635:635) (701:701:701)) - (PORT datab (664:664:664) (725:725:725)) - (PORT datac (564:564:564) (582:582:582)) - (PORT datad (306:306:306) (321:321:321)) + (PORT dataa (1235:1235:1235) (1301:1301:1301)) + (PORT datab (273:273:273) (358:358:358)) + (PORT datac (593:593:593) (612:612:612)) + (PORT datad (347:347:347) (370:370:370)) (IOPATH dataa combout (324:324:324) (328:328:328)) (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -13651,12 +2271,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vga_vc\[0\]\~0) + (INSTANCE ula_\|video_\|vga_vc\[5\]\~8) (DELAY (ABSOLUTE - (PORT dataa (518:518:518) (561:561:561)) - (PORT datab (553:553:553) (567:567:567)) - (PORT datad (900:900:900) (915:915:915)) + (PORT dataa (1137:1137:1137) (1180:1180:1180)) + (PORT datab (624:624:624) (639:639:639)) + (PORT datad (893:893:893) (919:919:919)) (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -13666,10 +2286,10 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_vc\[0\]) + (INSTANCE ula_\|video_\|vga_vc\[5\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1538:1538:1538) (1550:1550:1550)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -13680,32 +2300,33 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vga_vc\[1\]\~1) + (INSTANCE ula_\|video_\|Equal2\~1) (DELAY (ABSOLUTE - (PORT dataa (516:516:516) (560:560:560)) - (PORT datab (566:566:566) (575:575:575)) - (PORT datad (899:899:899) (916:916:916)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (353:353:353) (369:369:369)) + (PORT dataa (721:721:721) (782:782:782)) + (PORT datab (1274:1274:1274) (1364:1364:1364)) + (PORT datac (872:872:872) (944:944:944)) + (PORT datad (938:938:938) (994:994:994)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_vc\[1\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Equal2\~2) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (PORT dataa (1234:1234:1234) (1298:1298:1298)) + (PORT datab (602:602:602) (618:618:618)) + (PORT datad (350:350:350) (372:372:372)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) ) (CELL (CELLTYPE "cycloneive_io_ibuf") @@ -13721,10 +2342,10 @@ (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_13\~0) (DELAY (ABSOLUTE - (PORT dataa (1420:1420:1420) (1497:1497:1497)) - (PORT datab (716:716:716) (801:801:801)) - (PORT datac (1844:1844:1844) (1733:1733:1733)) - (PORT datad (677:677:677) (732:732:732)) + (PORT dataa (849:849:849) (904:904:904)) + (PORT datab (995:995:995) (1083:1083:1083)) + (PORT datac (1205:1205:1205) (1269:1269:1269)) + (PORT datad (1895:1895:1895) (1774:1774:1774)) (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -13732,180 +2353,18 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal79\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1251:1251:1251) (1348:1348:1348)) - (PORT datab (976:976:976) (1034:1034:1034)) - (PORT datac (1637:1637:1637) (1758:1758:1758)) - (PORT datad (1191:1191:1191) (1306:1306:1306)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|DFFE_instIFF2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1500:1500:1500) (1602:1602:1602)) - (PORT datab (361:361:361) (391:391:391)) - (PORT datad (665:665:665) (720:720:720)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_12) - (DELAY - (ABSOLUTE - (PORT dataa (357:357:357) (495:495:495)) - (PORT datab (2014:2014:2014) (2140:2140:2140)) - (PORT datad (275:275:275) (358:358:358)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_clkctrl") - (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_12\~clkctrl) - (DELAY - (ABSOLUTE - (PORT inclk[0] (1586:1586:1586) (1625:1625:1625)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|DFFE_instIFF2) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1553:1553:1553)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1552:1552:1552) (1543:1543:1543)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|iff1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (706:706:706) (765:765:765)) - (PORT datab (266:266:266) (349:349:349)) - (PORT datac (204:204:204) (241:241:241)) - (PORT datad (1456:1456:1456) (1550:1550:1550)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|iff1\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1287:1287:1287) (1330:1330:1330)) - (PORT datab (266:266:266) (349:349:349)) - (PORT datac (888:888:888) (913:913:913)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_15) - (DELAY - (ABSOLUTE - (PORT datab (1431:1431:1431) (1492:1492:1492)) - (PORT datac (1518:1518:1518) (1551:1551:1551)) - (PORT datad (1267:1267:1267) (1335:1335:1335)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|iff1) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1553:1553:1553)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1403:1403:1403) (1412:1412:1412)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Equal2\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1600:1600:1600) (1657:1657:1657)) - (PORT datab (843:843:843) (917:917:917)) - (PORT datac (633:633:633) (688:688:688)) - (PORT datad (427:427:427) (498:498:498)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Equal2\~2) - (DELAY - (ABSOLUTE - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (565:565:565) (583:583:583)) - (PORT datad (436:436:436) (516:516:516)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_13) (DELAY (ABSOLUTE - (PORT dataa (1175:1175:1175) (1240:1240:1240)) - (PORT datab (630:630:630) (645:645:645)) - (PORT datac (1541:1541:1541) (1636:1636:1636)) - (PORT datad (848:848:848) (861:861:861)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (1473:1473:1473) (1566:1566:1566)) + (PORT datab (566:566:566) (587:587:587)) + (PORT datac (622:622:622) (668:668:668)) + (PORT datad (176:176:176) (202:202:202)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -13915,9 +2374,9 @@ (INSTANCE z80_\|interrupts_\|int_armed) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1542:1542:1542)) + (PORT clk (1532:1532:1532) (1543:1543:1543)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1562:1562:1562) (1552:1552:1552)) + (PORT clrn (1563:1563:1563) (1553:1553:1553)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -13926,49 +2385,43 @@ (HOLD d (posedge clk) (157:157:157)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|DFFE_inst44\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1497:1497:1497) (1623:1623:1623)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|interrupts_\|DFFE_inst44) (DELAY (ABSOLUTE - (PORT clk (1533:1533:1533) (1552:1552:1552)) - (PORT asdata (2158:2158:2158) (2284:2284:2284)) - (PORT clrn (1592:1592:1592) (1568:1568:1568)) - (PORT ena (1669:1669:1669) (1678:1678:1678)) + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1566:1566:1566) (1548:1548:1548)) + (PORT ena (959:959:959) (957:957:957)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) + (HOLD d (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~38) + (INSTANCE z80_\|decode_state_\|in_halt\~0) (DELAY (ABSOLUTE - (PORT dataa (355:355:355) (487:487:487)) - (PORT datac (1180:1180:1180) (1261:1261:1261)) - (PORT datad (269:269:269) (350:350:350)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~91) - (DELAY - (ABSOLUTE - (PORT dataa (1671:1671:1671) (1790:1790:1790)) - (PORT datab (1251:1251:1251) (1347:1347:1347)) - (PORT datac (971:971:971) (1065:1065:1065)) - (PORT datad (862:862:862) (887:887:887)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (336:336:336) (325:325:325)) + (PORT dataa (506:506:506) (585:585:585)) + (PORT datac (267:267:267) (357:357:357)) + (PORT datad (703:703:703) (788:788:788)) + (IOPATH dataa combout (325:325:325) (320:320:320)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -13976,15 +2429,44 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~45) + (INSTANCE z80_\|decode_state_\|in_halt\~1) (DELAY (ABSOLUTE - (PORT dataa (1089:1089:1089) (1139:1139:1139)) - (PORT datab (699:699:699) (765:765:765)) - (PORT datac (1191:1191:1191) (1271:1271:1271)) - (PORT datad (626:626:626) (668:668:668)) + (PORT dataa (349:349:349) (379:379:379)) + (PORT datab (1642:1642:1642) (1678:1678:1678)) + (PORT datad (616:616:616) (664:664:664)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|decode_state_\|in_halt) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1567:1567:1567) (1549:1549:1549)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal50\~0) + (DELAY + (ABSOLUTE + (PORT datab (312:312:312) (409:409:409)) + (PORT datac (1832:1832:1832) (1861:1861:1861)) + (PORT datad (578:578:578) (597:597:597)) + (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -13992,15 +2474,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~44) + (INSTANCE z80_\|execute_\|ixy_d\~17) (DELAY (ABSOLUTE - (PORT dataa (1090:1090:1090) (1140:1140:1140)) - (PORT datab (909:909:909) (981:981:981)) - (PORT datac (856:856:856) (898:898:898)) - (PORT datad (1096:1096:1096) (1107:1107:1107)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (PORT dataa (482:482:482) (579:579:579)) + (PORT datab (495:495:495) (577:577:577)) + (PORT datac (828:828:828) (841:841:841)) + (PORT datad (595:595:595) (614:614:614)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -14008,191 +2490,227 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~46) + (INSTANCE z80_\|pla_decode_\|Equal44\~0) (DELAY (ABSOLUTE - (PORT dataa (338:338:338) (372:372:372)) - (PORT datab (702:702:702) (770:770:770)) - (PORT datac (173:173:173) (207:207:207)) - (PORT datad (1101:1101:1101) (1112:1112:1112)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (1042:1042:1042) (1133:1133:1133)) + (PORT datab (997:997:997) (1104:1104:1104)) + (PORT datac (932:932:932) (1055:1055:1055)) + (PORT datad (973:973:973) (1057:1057:1057)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~37) + (INSTANCE z80_\|execute_\|ixy_d\~16) (DELAY (ABSOLUTE - (PORT dataa (1161:1161:1161) (1207:1207:1207)) - (PORT datab (884:884:884) (933:933:933)) - (PORT datac (1058:1058:1058) (1098:1098:1098)) - (PORT datad (202:202:202) (231:231:231)) - (IOPATH dataa combout (304:304:304) (308:308:308)) + (PORT dataa (478:478:478) (576:576:576)) + (PORT datab (499:499:499) (580:580:580)) + (PORT datac (1219:1219:1219) (1275:1275:1275)) + (PORT datad (204:204:204) (233:233:233)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal3\~1) + (DELAY + (ABSOLUTE + (PORT datac (887:887:887) (952:952:952)) + (PORT datad (1303:1303:1303) (1431:1431:1431)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1657:1657:1657) (1683:1683:1683)) + (PORT datab (654:654:654) (688:688:688)) + (PORT datac (918:918:918) (963:963:963)) + (PORT datad (949:949:949) (1026:1026:1026)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1195:1195:1195) (1265:1265:1265)) + (PORT datab (371:371:371) (414:414:414)) + (PORT datac (1556:1556:1556) (1662:1662:1662)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1066:1066:1066) (1147:1147:1147)) + (PORT datab (654:654:654) (705:705:705)) + (PORT datac (646:646:646) (663:663:663)) + (PORT datad (171:171:171) (196:196:196)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal49\~0) + (DELAY + (ABSOLUTE + (PORT datab (312:312:312) (412:412:412)) + (PORT datac (1693:1693:1693) (1762:1762:1762)) + (PORT datad (579:579:579) (601:601:601)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~15) + (DELAY + (ABSOLUTE + (PORT dataa (965:965:965) (1008:1008:1008)) + (PORT datab (925:925:925) (962:962:962)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (1259:1259:1259) (1310:1310:1310)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_ixy_dT5_7) + (DELAY + (ABSOLUTE + (PORT datab (905:905:905) (938:938:938)) + (PORT datac (1425:1425:1425) (1546:1546:1546)) (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~50) + (INSTANCE z80_\|decode_state_\|SYNTHESIZED_WIRE_0\~0) (DELAY (ABSOLUTE - (PORT dataa (830:830:830) (863:863:863)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (1604:1604:1604) (1719:1719:1719)) - (PORT datad (2285:2285:2285) (2389:2389:2389)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (743:743:743) (836:836:836)) + (PORT datab (973:973:973) (1036:1036:1036)) + (PORT datac (192:192:192) (225:225:225)) + (PORT datad (387:387:387) (419:419:419)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~33) + (CELLTYPE "dffeas") + (INSTANCE z80_\|decode_state_\|DFFE_inst4) (DELAY (ABSOLUTE - (PORT dataa (229:229:229) (276:276:276)) - (PORT datab (1151:1151:1151) (1219:1219:1219)) - (PORT datac (1080:1080:1080) (1126:1126:1126)) - (PORT datad (596:596:596) (629:629:629)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT clk (1525:1525:1525) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1559:1559:1559) (1540:1540:1540)) + (PORT ena (820:820:820) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla38pla13M3T2_4) + (INSTANCE z80_\|execute_\|ctl_ir_we\~5) (DELAY (ABSOLUTE - (PORT dataa (1685:1685:1685) (1750:1750:1750)) - (PORT datab (623:623:623) (672:672:672)) - (PORT datac (1663:1663:1663) (1743:1743:1743)) - (PORT datad (1164:1164:1164) (1212:1212:1212)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla40M3T2_4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (729:729:729) (825:825:825)) - (PORT datab (672:672:672) (761:761:761)) - (PORT datac (1148:1148:1148) (1186:1186:1186)) - (PORT datad (212:212:212) (247:247:247)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~31) - (DELAY - (ABSOLUTE - (PORT dataa (1112:1112:1112) (1165:1165:1165)) - (PORT datab (850:850:850) (866:866:866)) - (PORT datac (1208:1208:1208) (1236:1236:1236)) - (PORT datad (822:822:822) (834:834:834)) + (PORT dataa (1042:1042:1042) (1134:1134:1134)) + (PORT datab (504:504:504) (589:589:589)) + (PORT datad (441:441:441) (521:521:521)) (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~32) + (INSTANCE z80_\|execute_\|ctl_ir_we\~13) (DELAY (ABSOLUTE - (PORT dataa (1110:1110:1110) (1168:1168:1168)) - (PORT datab (622:622:622) (673:673:673)) - (PORT datac (209:209:209) (250:250:250)) - (PORT datad (1641:1641:1641) (1711:1711:1711)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~34) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (193:193:193) (238:238:238)) - (PORT datad (180:180:180) (209:209:209)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~51) - (DELAY - (ABSOLUTE - (PORT dataa (1149:1149:1149) (1191:1191:1191)) - (PORT datab (1399:1399:1399) (1505:1505:1505)) - (PORT datac (2514:2514:2514) (2618:2618:2618)) - (PORT datad (1497:1497:1497) (1611:1611:1611)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~30) - (DELAY - (ABSOLUTE - (PORT dataa (691:691:691) (738:738:738)) - (PORT datab (1144:1144:1144) (1210:1210:1210)) - (PORT datac (365:365:365) (393:393:393)) - (PORT datad (865:865:865) (890:890:890)) - (IOPATH dataa combout (337:337:337) (338:338:338)) + (PORT dataa (975:975:975) (1047:1047:1047)) + (PORT datab (611:611:611) (629:629:629)) + (PORT datac (1954:1954:1954) (2059:2059:2059)) + (PORT datad (877:877:877) (926:926:926)) + (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~52) + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[3\]) (DELAY (ABSOLUTE - (PORT dataa (1521:1521:1521) (1648:1648:1648)) - (PORT datab (1395:1395:1395) (1501:1501:1501)) - (PORT datac (2518:2518:2518) (2621:2621:2621)) - (PORT datad (1054:1054:1054) (1086:1086:1086)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) + (PORT clk (1541:1541:1541) (1557:1557:1557)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1567:1567:1567) (1549:1549:1549)) + (PORT ena (1404:1404:1404) (1375:1375:1375)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal8\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1558:1558:1558) (1685:1685:1685)) + (PORT datac (1365:1365:1365) (1540:1540:1540)) + (PORT datad (1513:1513:1513) (1632:1632:1632)) + (IOPATH dataa combout (324:324:324) (328:328:328)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -14200,13 +2718,239 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~35) + (INSTANCE z80_\|execute_\|ctl_mRead\~6) (DELAY (ABSOLUTE - (PORT dataa (370:370:370) (406:406:406)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (619:619:619) (652:652:652)) - (PORT datad (179:179:179) (207:207:207)) + (PORT datab (1318:1318:1318) (1402:1402:1402)) + (PORT datac (638:638:638) (670:670:670)) + (PORT datad (1196:1196:1196) (1265:1265:1265)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal9\~0) + (DELAY + (ABSOLUTE + (PORT datab (1416:1416:1416) (1527:1527:1527)) + (PORT datad (1440:1440:1440) (1528:1528:1528)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal9\~1) + (DELAY + (ABSOLUTE + (PORT dataa (2523:2523:2523) (2690:2690:2690)) + (PORT datab (968:968:968) (1051:1051:1051)) + (PORT datac (1680:1680:1680) (1751:1751:1751)) + (PORT datad (908:908:908) (962:962:962)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla10M5T1_5\~2) + (DELAY + (ABSOLUTE + (PORT datab (1286:1286:1286) (1375:1375:1375)) + (PORT datac (1790:1790:1790) (1858:1858:1858)) + (PORT datad (1011:1011:1011) (1104:1104:1104)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (1360:1360:1360) (1407:1407:1407)) + (PORT datab (1259:1259:1259) (1302:1302:1302)) + (PORT datac (1205:1205:1205) (1234:1234:1234)) + (PORT datad (636:636:636) (687:687:687)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal13\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1565:1565:1565) (1693:1693:1693)) + (PORT datac (1381:1381:1381) (1558:1558:1558)) + (PORT datad (1511:1511:1511) (1631:1631:1631)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal69\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1992:1992:1992) (2184:2184:2184)) + (PORT datab (1223:1223:1223) (1309:1309:1309)) + (PORT datac (1175:1175:1175) (1266:1266:1266)) + (PORT datad (1186:1186:1186) (1205:1205:1205)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (624:624:624) (680:680:680)) + (PORT datab (1525:1525:1525) (1622:1622:1622)) + (PORT datac (851:851:851) (896:896:896)) + (PORT datad (934:934:934) (1019:1019:1019)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~27) + (DELAY + (ABSOLUTE + (PORT dataa (1345:1345:1345) (1475:1475:1475)) + (PORT datab (229:229:229) (272:272:272)) + (PORT datac (1217:1217:1217) (1269:1269:1269)) + (PORT datad (856:856:856) (901:901:901)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1707:1707:1707) (1758:1758:1758)) + (PORT datab (992:992:992) (1035:1035:1035)) + (PORT datac (1141:1141:1141) (1167:1167:1167)) + (PORT datad (1219:1219:1219) (1214:1214:1214)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|rsel3) + (DELAY + (ABSOLUTE + (PORT dataa (790:790:790) (894:894:894)) + (PORT datac (1368:1368:1368) (1448:1448:1448)) + (PORT datad (1229:1229:1229) (1324:1324:1324)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~12) + (DELAY + (ABSOLUTE + (PORT dataa (719:719:719) (795:795:795)) + (PORT datab (1042:1042:1042) (1181:1181:1181)) + (PORT datac (1282:1282:1282) (1348:1348:1348)) + (PORT datad (996:996:996) (1098:1098:1098)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3) + (DELAY + (ABSOLUTE + (PORT dataa (979:979:979) (1067:1067:1067)) + (PORT datac (1110:1110:1110) (1150:1150:1150)) + (PORT datad (1381:1381:1381) (1455:1455:1455)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal56\~0) + (DELAY + (ABSOLUTE + (PORT dataa (987:987:987) (1092:1092:1092)) + (PORT datab (1518:1518:1518) (1582:1582:1582)) + (PORT datac (1014:1014:1014) (1073:1073:1073)) + (PORT datad (1663:1663:1663) (1795:1795:1795)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~24) + (DELAY + (ABSOLUTE + (PORT dataa (2080:2080:2080) (2164:2164:2164)) + (PORT datab (2213:2213:2213) (2326:2326:2326)) + (PORT datac (1928:1928:1928) (1994:1994:1994)) + (PORT datad (915:915:915) (988:988:988)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~25) + (DELAY + (ABSOLUTE + (PORT dataa (2188:2188:2188) (2323:2323:2323)) + (PORT datab (971:971:971) (1055:1055:1055)) + (PORT datac (1166:1166:1166) (1223:1223:1223)) + (PORT datad (896:896:896) (971:971:971)) (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datab combout (342:342:342) (318:318:318)) (IOPATH datac combout (243:243:243) (241:241:241)) @@ -14216,15 +2960,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~36) + (INSTANCE z80_\|execute_\|nextM\~2) (DELAY (ABSOLUTE - (PORT dataa (1104:1104:1104) (1123:1123:1123)) - (PORT datab (643:643:643) (662:662:662)) - (PORT datac (625:625:625) (646:646:646)) - (PORT datad (1379:1379:1379) (1419:1419:1419)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) + (PORT dataa (895:895:895) (980:980:980)) + (PORT datac (569:569:569) (601:601:601)) + (PORT datad (1058:1058:1058) (1065:1065:1065)) + (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -14232,75 +2974,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~44) + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~16) (DELAY (ABSOLUTE - (PORT dataa (2071:2071:2071) (2185:2185:2185)) - (PORT datab (910:910:910) (981:981:981)) - (PORT datac (1397:1397:1397) (1483:1483:1483)) - (PORT datad (646:646:646) (677:677:677)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_use_ixiypla53M2T2_4) - (DELAY - (ABSOLUTE - (PORT dataa (1333:1333:1333) (1437:1437:1437)) - (PORT datab (1764:1764:1764) (1881:1881:1881)) - (PORT datad (630:630:630) (685:685:685)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~45) - (DELAY - (ABSOLUTE - (PORT dataa (216:216:216) (266:266:266)) - (PORT datab (216:216:216) (261:261:261)) - (PORT datac (670:670:670) (716:716:716)) - (PORT datad (570:570:570) (590:590:590)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~43) - (DELAY - (ABSOLUTE - (PORT dataa (1409:1409:1409) (1454:1454:1454)) - (PORT datab (666:666:666) (697:697:697)) - (PORT datac (1989:1989:1989) (2085:2085:2085)) - (PORT datad (1246:1246:1246) (1294:1294:1294)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~71) - (DELAY - (ABSOLUTE - (PORT dataa (207:207:207) (253:253:253)) - (PORT datab (221:221:221) (260:260:260)) - (PORT datac (635:635:635) (682:682:682)) - (PORT datad (190:190:190) (223:223:223)) + (PORT dataa (981:981:981) (1069:1069:1069)) + (PORT datab (975:975:975) (1040:1040:1040)) + (PORT datac (1312:1312:1312) (1366:1366:1366)) + (PORT datad (1233:1233:1233) (1288:1288:1288)) (IOPATH dataa combout (341:341:341) (319:319:319)) (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (241:241:241)) @@ -14310,15 +2990,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~73) + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~3) (DELAY (ABSOLUTE - (PORT dataa (390:390:390) (421:421:421)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (637:637:637) (672:672:672)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (300:300:300) (308:308:308)) + (PORT dataa (628:628:628) (678:678:678)) + (PORT datab (676:676:676) (719:719:719)) + (PORT datac (193:193:193) (226:226:226)) + (PORT datad (194:194:194) (220:220:220)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal40\~0) + (DELAY + (ABSOLUTE + (PORT dataa (976:976:976) (1070:1070:1070)) + (PORT datac (887:887:887) (952:952:952)) + (PORT datad (1303:1303:1303) (1432:1432:1432)) + (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -14326,30 +3020,28 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~46) + (INSTANCE z80_\|pla_decode_\|Equal40\~1) (DELAY (ABSOLUTE - (PORT dataa (673:673:673) (722:722:722)) - (PORT datab (699:699:699) (766:766:766)) - (PORT datac (639:639:639) (671:671:671)) - (PORT datad (1153:1153:1153) (1224:1224:1224)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (232:232:232) (292:292:292)) + (PORT datab (880:880:880) (938:938:938)) + (PORT datad (1360:1360:1360) (1485:1485:1485)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~53) + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla23pla16M3T1_5\~0) (DELAY (ABSOLUTE - (PORT dataa (1647:1647:1647) (1764:1764:1764)) - (PORT datab (1067:1067:1067) (1136:1136:1136)) - (PORT datac (612:612:612) (631:631:631)) - (PORT datad (973:973:973) (1058:1058:1058)) - (IOPATH dataa combout (304:304:304) (299:299:299)) + (PORT dataa (988:988:988) (1091:1091:1091)) + (PORT datab (1082:1082:1082) (1154:1154:1154)) + (PORT datac (940:940:940) (974:974:974)) + (PORT datad (1027:1027:1027) (1094:1094:1094)) + (IOPATH dataa combout (324:324:324) (328:328:328)) (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -14358,13 +3050,1147 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~39) + (INSTANCE z80_\|pla_decode_\|Equal3\~0) (DELAY (ABSOLUTE - (PORT dataa (215:215:215) (264:264:264)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (623:623:623) (647:647:647)) - (PORT datad (565:565:565) (585:585:585)) + (PORT datab (1218:1218:1218) (1320:1320:1320)) + (PORT datad (1266:1266:1266) (1357:1357:1357)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal39\~0) + (DELAY + (ABSOLUTE + (PORT dataa (233:233:233) (292:292:292)) + (PORT datab (879:879:879) (938:938:938)) + (PORT datac (1315:1315:1315) (1437:1437:1437)) + (PORT datad (887:887:887) (944:944:944)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1290:1290:1290) (1340:1340:1340)) + (PORT datab (644:644:644) (674:674:674)) + (PORT datac (1384:1384:1384) (1432:1432:1432)) + (PORT datad (1996:1996:1996) (2055:2055:2055)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~0) + (DELAY + (ABSOLUTE + (PORT datac (1581:1581:1581) (1680:1680:1680)) + (PORT datad (1300:1300:1300) (1409:1409:1409)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|comb\~0) + (DELAY + (ABSOLUTE + (PORT datac (1400:1400:1400) (1460:1460:1460)) + (PORT datad (1209:1209:1209) (1274:1274:1274)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal41\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1026:1026:1026) (1143:1143:1143)) + (PORT datad (1005:1005:1005) (1141:1141:1141)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal47\~0) + (DELAY + (ABSOLUTE + (PORT dataa (980:980:980) (1067:1067:1067)) + (PORT datab (661:661:661) (687:687:687)) + (PORT datac (636:636:636) (654:654:654)) + (PORT datad (681:681:681) (729:729:729)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~32) + (DELAY + (ABSOLUTE + (PORT dataa (1247:1247:1247) (1322:1322:1322)) + (PORT datab (1732:1732:1732) (1828:1828:1828)) + (PORT datac (211:211:211) (251:251:251)) + (PORT datad (1343:1343:1343) (1419:1419:1419)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal19\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1302:1302:1302) (1383:1383:1383)) + (PORT datab (889:889:889) (925:925:925)) + (PORT datac (740:740:740) (846:846:846)) + (PORT datad (1071:1071:1071) (1093:1093:1093)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~9) + (DELAY + (ABSOLUTE + (PORT dataa (214:214:214) (264:264:264)) + (PORT datab (1205:1205:1205) (1281:1281:1281)) + (PORT datac (1579:1579:1579) (1678:1678:1678)) + (PORT datad (1295:1295:1295) (1406:1406:1406)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~5) + (DELAY + (ABSOLUTE + (PORT dataa (616:616:616) (629:629:629)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (575:575:575) (600:600:600)) + (PORT datad (1345:1345:1345) (1384:1384:1384)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~4) + (DELAY + (ABSOLUTE + (PORT dataa (287:287:287) (385:385:385)) + (PORT datab (1160:1160:1160) (1219:1219:1219)) + (PORT datac (396:396:396) (476:476:476)) + (PORT datad (394:394:394) (459:459:459)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla21M2T2_3) + (DELAY + (ABSOLUTE + (PORT dataa (968:968:968) (1036:1036:1036)) + (PORT datab (1665:1665:1665) (1730:1730:1730)) + (PORT datac (938:938:938) (1051:1051:1051)) + (PORT datad (2586:2586:2586) (2762:2762:2762)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~34) + (DELAY + (ABSOLUTE + (PORT dataa (698:698:698) (807:807:807)) + (PORT datab (1716:1716:1716) (1780:1780:1780)) + (PORT datac (1114:1114:1114) (1189:1189:1189)) + (PORT datad (913:913:913) (932:932:932)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_ixy_dT4_2) + (DELAY + (ABSOLUTE + (PORT datac (1594:1594:1594) (1728:1728:1728)) + (PORT datad (1081:1081:1081) (1116:1116:1116)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (206:206:206) (253:253:253)) + (PORT datab (1127:1127:1127) (1206:1206:1206)) + (PORT datac (973:973:973) (1037:1037:1037)) + (PORT datad (1067:1067:1067) (1096:1096:1096)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~5) + (DELAY + (ABSOLUTE + (PORT datab (468:468:468) (546:546:546)) + (PORT datac (417:417:417) (491:491:491)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~11) + (DELAY + (ABSOLUTE + (PORT dataa (847:847:847) (873:873:873)) + (PORT datab (1711:1711:1711) (1758:1758:1758)) + (PORT datac (862:862:862) (891:891:891)) + (PORT datad (901:901:901) (992:992:992)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal20\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1719:1719:1719) (1854:1854:1854)) + (PORT datab (1514:1514:1514) (1573:1573:1573)) + (PORT datac (1305:1305:1305) (1369:1369:1369)) + (PORT datad (659:659:659) (733:733:733)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal13\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1991:1991:1991) (2189:2189:2189)) + (PORT datab (1221:1221:1221) (1309:1309:1309)) + (PORT datac (1178:1178:1178) (1270:1270:1270)) + (PORT datad (1183:1183:1183) (1205:1205:1205)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~24) + (DELAY + (ABSOLUTE + (PORT datac (2181:2181:2181) (2263:2263:2263)) + (PORT datad (1433:1433:1433) (1514:1514:1514)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (1103:1103:1103) (1150:1150:1150)) + (PORT datab (987:987:987) (1033:1033:1033)) + (PORT datac (1354:1354:1354) (1406:1406:1406)) + (PORT datad (1141:1141:1141) (1141:1141:1141)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal48\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2004:2004:2004) (2196:2196:2196)) + (PORT datab (1220:1220:1220) (1307:1307:1307)) + (PORT datac (1184:1184:1184) (1277:1277:1277)) + (PORT datad (1182:1182:1182) (1203:1203:1203)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal10\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1428:1428:1428) (1603:1603:1603)) + (PORT datab (1228:1228:1228) (1299:1299:1299)) + (PORT datac (1530:1530:1530) (1649:1649:1649)) + (PORT datad (1513:1513:1513) (1634:1634:1634)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal11\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1429:1429:1429) (1604:1604:1604)) + (PORT datab (1228:1228:1228) (1299:1299:1299)) + (PORT datac (1531:1531:1531) (1649:1649:1649)) + (PORT datad (1514:1514:1514) (1635:1635:1635)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal63\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1718:1718:1718) (1854:1854:1854)) + (PORT datab (1514:1514:1514) (1575:1575:1575)) + (PORT datac (1305:1305:1305) (1372:1372:1372)) + (PORT datad (659:659:659) (732:732:732)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf2_we) + (DELAY + (ABSOLUTE + (PORT dataa (1148:1148:1148) (1200:1200:1200)) + (PORT datab (1406:1406:1406) (1447:1447:1447)) + (PORT datac (1417:1417:1417) (1511:1511:1511)) + (PORT datad (914:914:914) (985:985:985)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~41) + (DELAY + (ABSOLUTE + (PORT dataa (2364:2364:2364) (2424:2424:2424)) + (PORT datab (1731:1731:1731) (1782:1782:1782)) + (PORT datac (202:202:202) (239:239:239)) + (PORT datad (1368:1368:1368) (1411:1411:1411)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal68\~3) + (DELAY + (ABSOLUTE + (PORT dataa (922:922:922) (994:994:994)) + (PORT datab (1333:1333:1333) (1472:1472:1472)) + (PORT datac (855:855:855) (907:907:907)) + (PORT datad (934:934:934) (1023:1023:1023)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~7) + (DELAY + (ABSOLUTE + (PORT dataa (242:242:242) (286:286:286)) + (PORT datab (207:207:207) (249:249:249)) + (PORT datac (1220:1220:1220) (1271:1271:1271)) + (PORT datad (1076:1076:1076) (1155:1155:1155)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1088:1088:1088) (1110:1110:1110)) + (PORT datab (1585:1585:1585) (1610:1610:1610)) + (PORT datac (1644:1644:1644) (1686:1686:1686)) + (PORT datad (859:859:859) (911:911:911)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~9) + (DELAY + (ABSOLUTE + (PORT dataa (599:599:599) (640:640:640)) + (PORT datab (1733:1733:1733) (1817:1817:1817)) + (PORT datac (1890:1890:1890) (2010:2010:2010)) + (PORT datad (856:856:856) (936:936:936)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1022:1022:1022) (1142:1142:1142)) + (PORT datad (1002:1002:1002) (1146:1146:1146)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (732:732:732) (806:806:806)) + (PORT datab (227:227:227) (268:268:268)) + (PORT datac (1291:1291:1291) (1355:1355:1355)) + (PORT datad (968:968:968) (1051:1051:1051)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~14) + (DELAY + (ABSOLUTE + (PORT dataa (734:734:734) (808:808:808)) + (PORT datab (1047:1047:1047) (1185:1185:1185)) + (PORT datac (1291:1291:1291) (1356:1356:1356)) + (PORT datad (988:988:988) (1089:1089:1089)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~4) + (DELAY + (ABSOLUTE + (PORT dataa (884:884:884) (916:916:916)) + (PORT datab (1918:1918:1918) (2042:2042:2042)) + (PORT datac (1702:1702:1702) (1782:1782:1782)) + (PORT datad (615:615:615) (631:631:631)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1204:1204:1204) (1260:1260:1260)) + (PORT datab (1666:1666:1666) (1743:1743:1743)) + (PORT datac (537:537:537) (553:553:553)) + (PORT datad (1398:1398:1398) (1411:1411:1411)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1655:1655:1655) (1681:1681:1681)) + (PORT datab (649:649:649) (682:682:682)) + (PORT datac (926:926:926) (974:974:974)) + (PORT datad (953:953:953) (1032:1032:1032)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~6) + (DELAY + (ABSOLUTE + (PORT dataa (864:864:864) (938:938:938)) + (PORT datab (1544:1544:1544) (1580:1580:1580)) + (PORT datac (1644:1644:1644) (1686:1686:1686)) + (PORT datad (1435:1435:1435) (1485:1485:1485)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~9) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (244:244:244)) + (PORT datab (207:207:207) (250:250:250)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_iorw\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1561:1561:1561) (1691:1691:1691)) + (PORT datab (1494:1494:1494) (1547:1547:1547)) + (PORT datac (1374:1374:1374) (1549:1549:1549)) + (PORT datad (1513:1513:1513) (1638:1638:1638)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1425:1425:1425) (1601:1601:1601)) + (PORT datab (1225:1225:1225) (1300:1300:1300)) + (PORT datac (1528:1528:1528) (1646:1646:1646)) + (PORT datad (1510:1510:1510) (1633:1633:1633)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~18) + (DELAY + (ABSOLUTE + (PORT dataa (947:947:947) (987:987:987)) + (PORT datab (2520:2520:2520) (2505:2505:2505)) + (PORT datac (863:863:863) (889:889:889)) + (PORT datad (834:834:834) (862:862:862)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal37\~0) + (DELAY + (ABSOLUTE + (PORT dataa (975:975:975) (1066:1066:1066)) + (PORT datab (666:666:666) (692:692:692)) + (PORT datac (593:593:593) (641:641:641)) + (PORT datad (682:682:682) (732:732:732)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1052:1052:1052) (1095:1095:1095)) + (PORT datab (1183:1183:1183) (1218:1218:1218)) + (PORT datac (1171:1171:1171) (1202:1202:1202)) + (PORT datad (1795:1795:1795) (1839:1839:1839)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal35\~0) + (DELAY + (ABSOLUTE + (PORT dataa (979:979:979) (1061:1061:1061)) + (PORT datab (667:667:667) (694:694:694)) + (PORT datac (547:547:547) (568:568:568)) + (PORT datad (684:684:684) (735:735:735)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal21\~1) + (DELAY + (ABSOLUTE + (PORT dataa (234:234:234) (294:294:294)) + (PORT datab (886:886:886) (943:943:943)) + (PORT datac (1217:1217:1217) (1268:1268:1268)) + (PORT datad (1362:1362:1362) (1487:1487:1487)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1419:1419:1419) (1478:1478:1478)) + (PORT datab (1049:1049:1049) (1106:1106:1106)) + (PORT datac (830:830:830) (890:890:890)) + (PORT datad (1676:1676:1676) (1758:1758:1758)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~20) + (DELAY + (ABSOLUTE + (PORT dataa (845:845:845) (888:888:888)) + (PORT datab (858:858:858) (925:925:925)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1327:1327:1327) (1395:1395:1395)) + (PORT datab (220:220:220) (260:260:260)) + (PORT datac (694:694:694) (759:759:759)) + (PORT datad (969:969:969) (1053:1053:1053)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1123:1123:1123) (1170:1170:1170)) + (PORT datab (1532:1532:1532) (1666:1666:1666)) + (PORT datac (957:957:957) (985:985:985)) + (PORT datad (2545:2545:2545) (2613:2613:2613)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~15) + (DELAY + (ABSOLUTE + (PORT dataa (732:732:732) (806:806:806)) + (PORT datab (1045:1045:1045) (1186:1186:1186)) + (PORT datac (1290:1290:1290) (1355:1355:1355)) + (PORT datad (990:990:990) (1092:1092:1092)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1454:1454:1454) (1506:1506:1506)) + (PORT datab (1139:1139:1139) (1168:1168:1168)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (942:942:942) (1007:1007:1007)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~7) + (DELAY + (ABSOLUTE + (PORT dataa (728:728:728) (801:801:801)) + (PORT datab (1042:1042:1042) (1188:1188:1188)) + (PORT datac (1288:1288:1288) (1353:1353:1353)) + (PORT datad (994:994:994) (1099:1099:1099)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal46\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1695:1695:1695) (1742:1742:1742)) + (PORT datab (267:267:267) (352:352:352)) + (PORT datac (240:240:240) (319:319:319)) + (PORT datad (385:385:385) (451:451:451)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1026:1026:1026) (1144:1144:1144)) + (PORT datab (1044:1044:1044) (1182:1182:1182)) + (PORT datac (683:683:683) (746:746:746)) + (PORT datad (1151:1151:1151) (1174:1174:1174)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~3) + (DELAY + (ABSOLUTE + (PORT dataa (696:696:696) (720:720:720)) + (PORT datab (1474:1474:1474) (1515:1515:1515)) + (PORT datac (937:937:937) (976:976:976)) + (PORT datad (906:906:906) (931:931:931)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal52\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1259:1259:1259) (1313:1313:1313)) + (PORT datab (995:995:995) (1101:1101:1101)) + (PORT datac (640:640:640) (656:656:656)) + (PORT datad (1000:1000:1000) (1088:1088:1088)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~21) + (DELAY + (ABSOLUTE + (PORT dataa (2391:2391:2391) (2514:2514:2514)) + (PORT datab (1262:1262:1262) (1375:1375:1375)) + (PORT datac (815:815:815) (835:835:835)) + (PORT datad (379:379:379) (412:412:412)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~13) + (DELAY + (ABSOLUTE + (PORT dataa (611:611:611) (649:649:649)) + (PORT datab (1249:1249:1249) (1289:1289:1289)) + (PORT datac (754:754:754) (766:766:766)) + (PORT datad (1095:1095:1095) (1107:1107:1107)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~6) + (DELAY + (ABSOLUTE + (PORT dataa (479:479:479) (577:577:577)) + (PORT datab (493:493:493) (585:585:585)) + (PORT datac (1217:1217:1217) (1272:1272:1272)) + (PORT datad (204:204:204) (233:233:233)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1527:1527:1527) (1589:1589:1589)) + (PORT datac (1001:1001:1001) (1069:1069:1069)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~14) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (264:264:264)) + (PORT datab (219:219:219) (257:257:257)) + (PORT datac (1134:1134:1134) (1152:1152:1152)) + (PORT datad (1561:1561:1561) (1676:1676:1676)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (1607:1607:1607) (1657:1657:1657)) + (PORT datab (1918:1918:1918) (1952:1952:1952)) + (PORT datac (1659:1659:1659) (1687:1687:1687)) + (PORT datad (544:544:544) (566:566:566)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (793:793:793) (847:847:847)) + (PORT datab (1152:1152:1152) (1192:1192:1192)) + (PORT datac (617:617:617) (641:641:641)) + (PORT datad (195:195:195) (221:221:221)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\~7) + (DELAY + (ABSOLUTE + (PORT dataa (2063:2063:2063) (2160:2160:2160)) + (PORT datab (663:663:663) (691:691:691)) + (PORT datac (866:866:866) (894:894:894)) + (PORT datad (682:682:682) (732:732:732)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|rsel0) + (DELAY + (ABSOLUTE + (PORT datab (1518:1518:1518) (1572:1572:1572)) + (PORT datac (1447:1447:1447) (1523:1523:1523)) + (PORT datad (913:913:913) (997:997:997)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~3) + (DELAY + (ABSOLUTE + (PORT dataa (2132:2132:2132) (2250:2250:2250)) + (PORT datac (1556:1556:1556) (1656:1656:1656)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~0) + (DELAY + (ABSOLUTE + (PORT dataa (902:902:902) (936:936:936)) + (PORT datab (893:893:893) (930:930:930)) + (PORT datac (816:816:816) (838:838:838)) + (PORT datad (899:899:899) (995:995:995)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~2) + (DELAY + (ABSOLUTE + (PORT datab (394:394:394) (472:472:472)) + (PORT datad (435:435:435) (508:508:508)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_ixy_dT2_2) + (DELAY + (ABSOLUTE + (PORT dataa (1103:1103:1103) (1153:1153:1153)) + (PORT datad (1747:1747:1747) (1803:1803:1803)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (972:972:972) (1011:1011:1011)) + (PORT datab (224:224:224) (272:272:272)) + (PORT datac (1378:1378:1378) (1466:1466:1466)) + (PORT datad (1261:1261:1261) (1305:1305:1305)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1417:1417:1417) (1473:1473:1473)) + (PORT datab (1714:1714:1714) (1790:1790:1790)) + (PORT datac (1605:1605:1605) (1674:1674:1674)) + (PORT datad (1247:1247:1247) (1293:1293:1293)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1127:1127:1127) (1134:1134:1134)) + (PORT datab (2242:2242:2242) (2356:2356:2356)) + (PORT datac (777:777:777) (839:839:839)) + (PORT datad (1950:1950:1950) (2093:2093:2093)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~5) + (DELAY + (ABSOLUTE + (PORT dataa (220:220:220) (264:264:264)) + (PORT datab (219:219:219) (258:258:258)) + (PORT datac (396:396:396) (479:479:479)) + (PORT datad (391:391:391) (460:460:460)) (IOPATH dataa combout (337:337:337) (338:338:338)) (IOPATH datab combout (337:337:337) (348:348:348)) (IOPATH datac combout (243:243:243) (241:241:241)) @@ -14374,15 +4200,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~47) + (INSTANCE z80_\|execute_\|ctl_sw_2u\~1) (DELAY (ABSOLUTE - (PORT dataa (399:399:399) (422:422:422)) - (PORT datab (212:212:212) (257:257:257)) - (PORT datac (620:620:620) (677:677:677)) - (PORT datad (196:196:196) (222:222:222)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) + (PORT dataa (430:430:430) (492:492:492)) + (PORT datab (2354:2354:2354) (2430:2430:2430)) + (PORT datac (1369:1369:1369) (1431:1431:1431)) + (PORT datad (598:598:598) (624:624:624)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -14390,13 +4216,463 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~74) + (INSTANCE z80_\|execute_\|ctl_alu_oe\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1729:1729:1729) (1799:1799:1799)) + (PORT datab (311:311:311) (410:410:410)) + (PORT datac (1831:1831:1831) (1860:1860:1860)) + (PORT datad (579:579:579) (596:596:596)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~7) + (DELAY + (ABSOLUTE + (PORT dataa (612:612:612) (647:647:647)) + (PORT datab (1863:1863:1863) (1897:1897:1897)) + (PORT datac (626:626:626) (642:642:642)) + (PORT datad (282:282:282) (366:366:366)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1108:1108:1108) (1170:1170:1170)) + (PORT datab (219:219:219) (256:256:256)) + (PORT datac (1087:1087:1087) (1107:1107:1107)) + (PORT datad (813:813:813) (842:842:842)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~57) + (DELAY + (ABSOLUTE + (PORT dataa (694:694:694) (753:753:753)) + (PORT datab (1124:1124:1124) (1226:1226:1226)) + (PORT datac (1262:1262:1262) (1293:1293:1293)) + (PORT datad (1389:1389:1389) (1445:1445:1445)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~5) + (DELAY + (ABSOLUTE + (PORT datab (866:866:866) (883:883:883)) + (PORT datac (820:820:820) (827:827:827)) + (PORT datad (1115:1115:1115) (1127:1127:1127)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~7) + (DELAY + (ABSOLUTE + (PORT dataa (965:965:965) (990:990:990)) + (PORT datab (883:883:883) (884:884:884)) + (PORT datac (791:791:791) (801:801:801)) + (PORT datad (190:190:190) (223:223:223)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla91pla21M4T2_3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2102:2102:2102) (2259:2259:2259)) + (PORT datab (1188:1188:1188) (1253:1253:1253)) + (PORT datac (1671:1671:1671) (1722:1722:1722)) + (PORT datad (1477:1477:1477) (1575:1575:1575)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~41) + (DELAY + (ABSOLUTE + (PORT dataa (2103:2103:2103) (2258:2258:2258)) + (PORT datab (1738:1738:1738) (1808:1808:1808)) + (PORT datac (2806:2806:2806) (2841:2841:2841)) + (PORT datad (919:919:919) (955:955:955)) + (IOPATH dataa combout (301:301:301) (307:307:307)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~86) + (DELAY + (ABSOLUTE + (PORT dataa (1571:1571:1571) (1698:1698:1698)) + (PORT datab (1204:1204:1204) (1284:1284:1284)) + (PORT datac (1739:1739:1739) (1846:1846:1846)) + (PORT datad (1296:1296:1296) (1412:1412:1412)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~88) + (DELAY + (ABSOLUTE + (PORT dataa (1572:1572:1572) (1693:1693:1693)) + (PORT datab (1731:1731:1731) (1827:1827:1827)) + (PORT datac (1616:1616:1616) (1726:1726:1726)) + (PORT datad (1535:1535:1535) (1631:1631:1631)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~36) + (DELAY + (ABSOLUTE + (PORT dataa (1309:1309:1309) (1363:1363:1363)) + (PORT datab (1381:1381:1381) (1462:1462:1462)) + (PORT datac (1162:1162:1162) (1215:1215:1215)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~87) + (DELAY + (ABSOLUTE + (PORT dataa (1573:1573:1573) (1694:1694:1694)) + (PORT datab (1320:1320:1320) (1444:1444:1444)) + (PORT datac (909:909:909) (943:943:943)) + (PORT datad (1538:1538:1538) (1632:1632:1632)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~26) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (255:255:255)) + (PORT datab (205:205:205) (247:247:247)) + (PORT datad (195:195:195) (220:220:220)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~9) + (DELAY + (ABSOLUTE + (PORT datab (1620:1620:1620) (1755:1755:1755)) + (PORT datac (1436:1436:1436) (1520:1520:1520)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~1) + (DELAY + (ABSOLUTE + (PORT dataa (2838:2838:2838) (2882:2882:2882)) + (PORT datab (957:957:957) (1006:1006:1006)) + (PORT datac (2067:2067:2067) (2222:2222:2222)) + (PORT datad (1102:1102:1102) (1126:1126:1126)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~42) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (583:583:583) (627:627:627)) + (PORT datad (181:181:181) (210:210:210)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal40\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1557:1557:1557) (1685:1685:1685)) + (PORT datab (1555:1555:1555) (1618:1618:1618)) + (PORT datac (1365:1365:1365) (1547:1547:1547)) + (PORT datad (1515:1515:1515) (1636:1636:1636)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~14) + (DELAY + (ABSOLUTE + (PORT dataa (649:649:649) (676:676:676)) + (PORT datab (1264:1264:1264) (1332:1332:1332)) + (PORT datac (2461:2461:2461) (2594:2594:2594)) + (PORT datad (1176:1176:1176) (1221:1221:1221)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal55\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1557:1557:1557) (1685:1685:1685)) + (PORT datac (1365:1365:1365) (1540:1540:1540)) + (PORT datad (1514:1514:1514) (1632:1632:1632)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1865:1865:1865) (1994:1994:1994)) + (PORT datab (1827:1827:1827) (1884:1884:1884)) + (PORT datac (681:681:681) (738:738:738)) + (PORT datad (1773:1773:1773) (1876:1876:1876)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal6\~1) + (DELAY + (ABSOLUTE + (PORT dataa (986:986:986) (1092:1092:1092)) + (PORT datab (1518:1518:1518) (1576:1576:1576)) + (PORT datac (1013:1013:1013) (1071:1071:1071)) + (PORT datad (1664:1664:1664) (1796:1796:1796)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~36) + (DELAY + (ABSOLUTE + (PORT dataa (1996:1996:1996) (2058:2058:2058)) + (PORT datab (2490:2490:2490) (2625:2625:2625)) + (PORT datac (918:918:918) (963:963:963)) + (PORT datad (1180:1180:1180) (1225:1225:1225)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|comb\~1) + (DELAY + (ABSOLUTE + (PORT datab (1098:1098:1098) (1228:1228:1228)) + (PORT datad (1614:1614:1614) (1668:1668:1668)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1119:1119:1119) (1149:1149:1149)) + (PORT datab (1657:1657:1657) (1753:1753:1753)) + (PORT datac (2114:2114:2114) (2210:2210:2210)) + (PORT datad (884:884:884) (939:939:939)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1389:1389:1389) (1413:1413:1413)) + (PORT datab (688:688:688) (747:747:747)) + (PORT datac (955:955:955) (1004:1004:1004)) + (PORT datad (656:656:656) (710:710:710)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal24\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1719:1719:1719) (1855:1855:1855)) + (PORT datab (668:668:668) (696:696:696)) + (PORT datac (2138:2138:2138) (2209:2209:2209)) + (PORT datad (659:659:659) (733:733:733)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~26) + (DELAY + (ABSOLUTE + (PORT dataa (1701:1701:1701) (1788:1788:1788)) + (PORT datab (2094:2094:2094) (2218:2218:2218)) + (PORT datac (1305:1305:1305) (1362:1362:1362)) + (PORT datad (667:667:667) (713:713:713)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~37) + (DELAY + (ABSOLUTE + (PORT dataa (1433:1433:1433) (1498:1498:1498)) + (PORT datab (196:196:196) (235:235:235)) + (PORT datac (614:614:614) (647:647:647)) + (PORT datad (194:194:194) (218:218:218)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~6) (DELAY (ABSOLUTE (PORT dataa (222:222:222) (266:266:266)) - (PORT datab (219:219:219) (258:258:258)) - (PORT datac (881:881:881) (895:895:895)) - (PORT datad (195:195:195) (221:221:221)) + (PORT datab (631:631:631) (652:652:652)) + (PORT datac (828:828:828) (841:841:841)) + (PORT datad (630:630:630) (657:657:657)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\~38) + (DELAY + (ABSOLUTE + (PORT dataa (721:721:721) (782:782:782)) + (PORT datab (1830:1830:1830) (1887:1887:1887)) + (PORT datac (1347:1347:1347) (1345:1345:1345)) + (PORT datad (943:943:943) (965:965:965)) (IOPATH dataa combout (324:324:324) (328:328:328)) (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -14404,16 +4680,310 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1452:1452:1452) (1556:1556:1556)) + (PORT datab (226:226:226) (266:266:266)) + (PORT datac (883:883:883) (918:918:918)) + (PORT datad (182:182:182) (212:212:212)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1216:1216:1216) (1308:1308:1308)) + (PORT datab (987:987:987) (1068:1068:1068)) + (PORT datad (1628:1628:1628) (1638:1638:1638)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~31) + (DELAY + (ABSOLUTE + (PORT dataa (913:913:913) (975:975:975)) + (PORT datab (1308:1308:1308) (1391:1391:1391)) + (PORT datac (680:680:680) (711:711:711)) + (PORT datad (1971:1971:1971) (2146:2146:2146)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla38pla13M4T2_4) + (DELAY + (ABSOLUTE + (PORT dataa (943:943:943) (967:967:967)) + (PORT datab (922:922:922) (975:975:975)) + (PORT datac (568:568:568) (579:579:579)) + (PORT datad (1619:1619:1619) (1707:1707:1707)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|nM1_int\~2) + (DELAY + (ABSOLUTE + (PORT datac (1641:1641:1641) (1746:1746:1746)) + (PORT datad (1900:1900:1900) (2003:2003:2003)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~0) + (DELAY + (ABSOLUTE + (PORT datab (1789:1789:1789) (1892:1892:1892)) + (PORT datad (1246:1246:1246) (1310:1310:1310)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (994:994:994) (1039:1039:1039)) + (PORT datab (867:867:867) (909:909:909)) + (PORT datac (1176:1176:1176) (1197:1197:1197)) + (PORT datad (659:659:659) (707:707:707)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~6) + (DELAY + (ABSOLUTE + (PORT dataa (641:641:641) (664:664:664)) + (PORT datab (934:934:934) (998:998:998)) + (PORT datac (678:678:678) (726:726:726)) + (PORT datad (202:202:202) (232:232:232)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~12) + (DELAY + (ABSOLUTE + (PORT dataa (955:955:955) (1060:1060:1060)) + (PORT datab (1248:1248:1248) (1295:1295:1295)) + (PORT datac (1533:1533:1533) (1659:1659:1659)) + (PORT datad (1298:1298:1298) (1350:1350:1350)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1583:1583:1583) (1713:1713:1713)) + (PORT datab (1362:1362:1362) (1389:1389:1389)) + (PORT datac (188:188:188) (229:229:229)) + (PORT datad (1348:1348:1348) (1437:1437:1437)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal25\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1441:1441:1441) (1529:1529:1529)) + (PORT datab (1660:1660:1660) (1746:1746:1746)) + (PORT datac (1595:1595:1595) (1726:1726:1726)) + (PORT datad (881:881:881) (930:930:930)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal12\~1) + (DELAY + (ABSOLUTE + (PORT dataa (984:984:984) (1094:1094:1094)) + (PORT datab (1515:1515:1515) (1578:1578:1578)) + (PORT datac (2137:2137:2137) (2207:2207:2207)) + (PORT datad (1670:1670:1670) (1805:1805:1805)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~38) + (DELAY + (ABSOLUTE + (PORT dataa (1435:1435:1435) (1450:1450:1450)) + (PORT datab (1976:1976:1976) (2129:2129:2129)) + (PORT datac (608:608:608) (643:643:643)) + (PORT datad (202:202:202) (233:233:233)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~82) + (DELAY + (ABSOLUTE + (PORT dataa (1290:1290:1290) (1410:1410:1410)) + (PORT datab (1526:1526:1526) (1587:1587:1587)) + (PORT datad (1494:1494:1494) (1581:1581:1581)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1199:1199:1199) (1261:1261:1261)) + (PORT datab (611:611:611) (639:639:639)) + (PORT datac (582:582:582) (623:623:623)) + (PORT datad (624:624:624) (638:638:638)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (354:354:354) (389:389:389)) + (PORT datab (1498:1498:1498) (1530:1530:1530)) + (PORT datac (194:194:194) (226:226:226)) + (PORT datad (179:179:179) (209:209:209)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~32) + (DELAY + (ABSOLUTE + (PORT dataa (229:229:229) (276:276:276)) + (PORT datab (228:228:228) (270:270:270)) + (PORT datac (1668:1668:1668) (1696:1696:1696)) + (PORT datad (607:607:607) (625:625:625)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~77) + (DELAY + (ABSOLUTE + (PORT dataa (1296:1296:1296) (1355:1355:1355)) + (PORT datab (1560:1560:1560) (1682:1682:1682)) + (PORT datac (862:862:862) (878:878:878)) + (PORT datad (2069:2069:2069) (2098:2098:2098)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal29\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1307:1307:1307) (1384:1384:1384)) + (PORT datab (896:896:896) (927:927:927)) + (PORT datac (752:752:752) (852:852:852)) + (PORT datad (1765:1765:1765) (1838:1838:1838)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_inc_cy\~78) (DELAY (ABSOLUTE - (PORT datab (206:206:206) (248:248:248)) - (PORT datac (636:636:636) (661:661:661)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (1295:1295:1295) (1357:1357:1357)) + (PORT datab (1558:1558:1558) (1684:1684:1684)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (1091:1091:1091) (1143:1143:1143)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -14423,184 +4993,12 @@ (INSTANCE z80_\|execute_\|ctl_inc_cy\~79) (DELAY (ABSOLUTE - (PORT dataa (209:209:209) (257:257:257)) - (PORT datab (341:341:341) (376:376:376)) - (PORT datac (639:639:639) (674:674:674)) - (PORT datad (182:182:182) (213:213:213)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~80) - (DELAY - (ABSOLUTE - (PORT dataa (676:676:676) (725:725:725)) - (PORT datab (911:911:911) (985:985:985)) - (PORT datac (1190:1190:1190) (1272:1272:1272)) - (PORT datad (188:188:188) (220:220:220)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~81) - (DELAY - (ABSOLUTE - (PORT dataa (868:868:868) (915:915:915)) - (PORT datab (682:682:682) (741:741:741)) - (PORT datac (965:965:965) (1027:1027:1027)) - (PORT datad (621:621:621) (668:668:668)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~82) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (241:241:241)) - (PORT datab (684:684:684) (749:749:749)) - (PORT datac (972:972:972) (1033:1033:1033)) - (PORT datad (1668:1668:1668) (1690:1690:1690)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~83) - (DELAY - (ABSOLUTE - (PORT dataa (207:207:207) (255:255:255)) - (PORT datab (340:340:340) (370:370:370)) - (PORT datac (638:638:638) (672:672:672)) - (PORT datad (357:357:357) (377:377:377)) + (PORT dataa (229:229:229) (275:275:275)) + (PORT datab (2237:2237:2237) (2351:2351:2351)) + (PORT datac (798:798:798) (857:857:857)) + (PORT datad (1951:1951:1951) (2095:2095:2095)) (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~84) - (DELAY - (ABSOLUTE - (PORT datab (205:205:205) (245:245:245)) - (PORT datac (179:179:179) (215:215:215)) - (PORT datad (180:180:180) (207:207:207)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~42) - (DELAY - (ABSOLUTE - (PORT datab (652:652:652) (687:687:687)) - (PORT datac (339:339:339) (370:370:370)) - (PORT datad (180:180:180) (209:209:209)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~90) - (DELAY - (ABSOLUTE - (PORT dataa (1017:1017:1017) (1099:1099:1099)) - (PORT datab (1086:1086:1086) (1123:1123:1123)) - (PORT datac (1171:1171:1171) (1232:1232:1232)) - (PORT datad (1497:1497:1497) (1611:1611:1611)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~41) - (DELAY - (ABSOLUTE - (PORT dataa (227:227:227) (279:279:279)) - (PORT datab (627:627:627) (674:674:674)) - (PORT datac (208:208:208) (246:246:246)) - (PORT datad (180:180:180) (207:207:207)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~66) - (DELAY - (ABSOLUTE - (PORT dataa (355:355:355) (494:494:494)) - (PORT datab (902:902:902) (935:935:935)) - (PORT datac (1178:1178:1178) (1261:1261:1261)) - (PORT datad (273:273:273) (355:355:355)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~67) - (DELAY - (ABSOLUTE - (PORT dataa (1111:1111:1111) (1166:1166:1166)) - (PORT datab (227:227:227) (270:270:270)) - (PORT datac (194:194:194) (242:242:242)) - (PORT datad (872:872:872) (923:923:923)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~68) - (DELAY - (ABSOLUTE - (PORT dataa (1443:1443:1443) (1505:1505:1505)) - (PORT datab (196:196:196) (234:234:234)) - (PORT datac (170:170:170) (202:202:202)) - (PORT datad (1642:1642:1642) (1712:1712:1712)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -14608,64 +5006,16 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~64) + (INSTANCE z80_\|execute_\|ctl_mRead\~14) (DELAY (ABSOLUTE - (PORT dataa (1110:1110:1110) (1166:1166:1166)) - (PORT datab (235:235:235) (278:278:278)) - (PORT datac (195:195:195) (241:241:241)) - (PORT datad (596:596:596) (630:630:630)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~63) - (DELAY - (ABSOLUTE - (PORT dataa (883:883:883) (888:888:888)) - (PORT datab (1133:1133:1133) (1145:1145:1145)) - (PORT datac (343:343:343) (372:372:372)) - (PORT datad (854:854:854) (886:886:886)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~65) - (DELAY - (ABSOLUTE - (PORT dataa (1157:1157:1157) (1221:1221:1221)) - (PORT datab (375:375:375) (398:398:398)) - (PORT datac (308:308:308) (325:325:325)) - (PORT datad (171:171:171) (196:196:196)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~69) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (330:330:330) (348:348:348)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (986:986:986) (1097:1097:1097)) + (PORT datab (665:665:665) (693:693:693)) + (PORT datac (1163:1163:1163) (1260:1260:1260)) + (PORT datad (634:634:634) (689:689:689)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -14675,44 +5025,12 @@ (INSTANCE z80_\|execute_\|ctl_inc_cy\~49) (DELAY (ABSOLUTE - (PORT dataa (663:663:663) (715:715:715)) - (PORT datab (410:410:410) (440:440:440)) - (PORT datac (1131:1131:1131) (1156:1156:1156)) - (PORT datad (854:854:854) (887:887:887)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~50) - (DELAY - (ABSOLUTE - (PORT dataa (663:663:663) (719:719:719)) - (PORT datab (946:946:946) (985:985:985)) - (PORT datac (1123:1123:1123) (1165:1165:1165)) - (PORT datad (1721:1721:1721) (1778:1778:1778)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~51) - (DELAY - (ABSOLUTE - (PORT dataa (372:372:372) (395:395:395)) - (PORT datab (1129:1129:1129) (1184:1184:1184)) - (PORT datac (1040:1040:1040) (1054:1054:1054)) - (PORT datad (1204:1204:1204) (1229:1229:1229)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (306:306:306) (308:308:308)) + (PORT dataa (1591:1591:1591) (1643:1643:1643)) + (PORT datab (1268:1268:1268) (1301:1301:1301)) + (PORT datac (1030:1030:1030) (1104:1104:1104)) + (PORT datad (2454:2454:2454) (2625:2625:2625)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -14720,29 +5038,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~52) + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~5) (DELAY (ABSOLUTE - (PORT dataa (657:657:657) (717:717:717)) - (PORT datab (921:921:921) (959:959:959)) - (PORT datac (913:913:913) (949:949:949)) - (PORT datad (313:313:313) (331:331:331)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~36) - (DELAY - (ABSOLUTE - (PORT dataa (902:902:902) (981:981:981)) - (PORT datab (893:893:893) (932:932:932)) - (PORT datac (1434:1434:1434) (1470:1470:1470)) - (PORT datad (843:843:843) (890:890:890)) + (PORT dataa (948:948:948) (995:995:995)) + (PORT datab (955:955:955) (1002:1002:1002)) + (PORT datac (2810:2810:2810) (2843:2843:2843)) + (PORT datad (2455:2455:2455) (2623:2623:2623)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (310:310:310)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -14752,910 +5054,30 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~37) + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~40) (DELAY (ABSOLUTE - (PORT dataa (1466:1466:1466) (1512:1512:1512)) - (PORT datab (915:915:915) (968:968:968)) - (PORT datac (321:321:321) (356:356:356)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~54) - (DELAY - (ABSOLUTE - (PORT dataa (227:227:227) (280:280:280)) - (PORT datab (200:200:200) (239:239:239)) - (PORT datac (170:170:170) (202:202:202)) - (PORT datad (588:588:588) (601:601:601)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~41) - (DELAY - (ABSOLUTE - (PORT dataa (1188:1188:1188) (1234:1234:1234)) - (PORT datab (1144:1144:1144) (1214:1214:1214)) - (PORT datac (364:364:364) (396:396:396)) - (PORT datad (1141:1141:1141) (1188:1188:1188)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~58) - (DELAY - (ABSOLUTE - (PORT dataa (1122:1122:1122) (1132:1132:1132)) - (PORT datab (1153:1153:1153) (1193:1193:1193)) - (PORT datad (195:195:195) (220:220:220)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~55) - (DELAY - (ABSOLUTE - (PORT dataa (956:956:956) (987:987:987)) - (PORT datab (921:921:921) (959:959:959)) - (PORT datac (635:635:635) (676:676:676)) - (PORT datad (1543:1543:1543) (1626:1626:1626)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~56) - (DELAY - (ABSOLUTE - (PORT dataa (457:457:457) (498:498:498)) - (PORT datab (219:219:219) (258:258:258)) - (PORT datac (805:805:805) (826:826:826)) - (PORT datad (195:195:195) (220:220:220)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~89) - (DELAY - (ABSOLUTE - (PORT dataa (1333:1333:1333) (1437:1437:1437)) - (PORT datab (1163:1163:1163) (1169:1169:1169)) - (PORT datac (1430:1430:1430) (1469:1469:1469)) - (PORT datad (844:844:844) (894:894:894)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~57) - (DELAY - (ABSOLUTE - (PORT dataa (207:207:207) (254:254:254)) - (PORT datab (828:828:828) (830:830:830)) - (PORT datac (314:314:314) (333:333:333)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~59) - (DELAY - (ABSOLUTE - (PORT dataa (907:907:907) (937:937:937)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (590:590:590) (602:602:602)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~60) - (DELAY - (ABSOLUTE - (PORT dataa (1157:1157:1157) (1220:1220:1220)) - (PORT datab (218:218:218) (256:256:256)) - (PORT datac (563:563:563) (566:566:566)) - (PORT datad (559:559:559) (582:582:582)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~47) - (DELAY - (ABSOLUTE - (PORT dataa (1096:1096:1096) (1139:1139:1139)) - (PORT datab (213:213:213) (256:256:256)) - (PORT datac (1061:1061:1061) (1099:1099:1099)) - (PORT datad (189:189:189) (222:222:222)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~88) - (DELAY - (ABSOLUTE - (PORT dataa (1618:1618:1618) (1736:1736:1736)) - (PORT datab (867:867:867) (905:905:905)) - (PORT datac (2517:2517:2517) (2622:2622:2622)) - (PORT datad (1493:1493:1493) (1607:1607:1607)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~48) - (DELAY - (ABSOLUTE - (PORT dataa (592:592:592) (611:611:611)) - (PORT datab (580:580:580) (593:593:593)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (1133:1133:1133) (1184:1184:1184)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~40) - (DELAY - (ABSOLUTE - (PORT datab (652:652:652) (686:686:686)) - (PORT datac (338:338:338) (369:369:369)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~61) - (DELAY - (ABSOLUTE - (PORT dataa (230:230:230) (277:277:277)) - (PORT datab (214:214:214) (259:259:259)) - (PORT datac (1058:1058:1058) (1099:1099:1099)) - (PORT datad (1134:1134:1134) (1161:1161:1161)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~62) - (DELAY - (ABSOLUTE - (PORT dataa (1157:1157:1157) (1225:1225:1225)) - (PORT datab (197:197:197) (237:237:237)) - (PORT datac (551:551:551) (564:564:564)) - (PORT datad (399:399:399) (430:430:430)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~70) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (169:169:169) (201:201:201)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~85) - (DELAY - (ABSOLUTE - (PORT dataa (1122:1122:1122) (1138:1138:1138)) - (PORT datab (1105:1105:1105) (1122:1122:1122)) - (PORT datac (1065:1065:1065) (1088:1088:1088)) - (PORT datad (1172:1172:1172) (1217:1217:1217)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|d0_out) - (DELAY - (ABSOLUTE - (PORT datac (700:700:700) (784:784:784)) - (PORT datad (365:365:365) (386:386:386)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (958:958:958) (1001:1001:1001)) - (PORT datac (681:681:681) (720:720:720)) - (PORT datad (339:339:339) (361:361:361)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[0\]) - (DELAY - (ABSOLUTE - (PORT datac (1006:1006:1006) (1012:1012:1012)) - (PORT datad (924:924:924) (943:943:943)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|Q\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (179:179:179) (207:207:207)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1560:1560:1560)) - (PORT ena (2096:2096:2096) (2133:2133:2133)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_41) - (DELAY - (ABSOLUTE - (PORT dataa (1158:1158:1158) (1184:1184:1184)) - (PORT datab (989:989:989) (1022:1022:1022)) - (PORT datac (696:696:696) (778:778:778)) - (PORT datad (201:201:201) (229:229:229)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1541:1541:1541) (1557:1557:1557)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1283:1283:1283) (1286:1286:1286)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (985:985:985) (1033:1033:1033)) - (PORT ena (1201:1201:1201) (1184:1184:1184)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (356:356:356) (396:396:396)) - (PORT datab (697:697:697) (726:726:726)) - (PORT datad (1194:1194:1194) (1231:1231:1231)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~5) - (DELAY - (ABSOLUTE - (PORT datab (740:740:740) (774:774:774)) - (PORT datac (217:217:217) (294:294:294)) - (PORT datad (608:608:608) (657:657:657)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|d1_out) - (DELAY - (ABSOLUTE - (PORT dataa (845:845:845) (905:905:905)) - (PORT datab (402:402:402) (425:425:425)) - (PORT datac (194:194:194) (227:227:227)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (244:244:244)) - (PORT datab (959:959:959) (1000:1000:1000)) - (PORT datac (683:683:683) (721:721:721)) - (PORT datad (341:341:341) (359:359:359)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[1\]) - (DELAY - (ABSOLUTE - (PORT datab (396:396:396) (421:421:421)) - (PORT datad (345:345:345) (371:371:371)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1541:1541:1541) (1557:1557:1557)) - (PORT asdata (537:537:537) (568:568:568)) - (PORT clrn (1597:1597:1597) (1572:1572:1572)) - (PORT ena (2143:2143:2143) (2210:2210:2210)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_40\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1005:1005:1005) (1069:1069:1069)) - (PORT datab (1154:1154:1154) (1178:1178:1178)) - (PORT datac (812:812:812) (866:866:866)) - (PORT datad (359:359:359) (383:383:383)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|d0_out) - (DELAY - (ABSOLUTE - (PORT dataa (416:416:416) (443:443:443)) - (PORT datab (219:219:219) (258:258:258)) - (PORT datac (236:236:236) (311:311:311)) - (PORT datad (327:327:327) (348:348:348)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (716:716:716) (758:758:758)) - (PORT datab (962:962:962) (1001:1001:1001)) - (PORT datac (617:617:617) (670:670:670)) - (PORT datad (532:532:532) (544:544:544)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[2\]) - (DELAY - (ABSOLUTE - (PORT dataa (553:553:553) (579:579:579)) - (PORT datad (214:214:214) (247:247:247)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|Q\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (195:195:195) (220:220:220)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1541:1541:1541) (1557:1557:1557)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1597:1597:1597) (1572:1572:1572)) - (PORT ena (2146:2146:2146) (2210:2210:2210)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_42) - (DELAY - (ABSOLUTE - (PORT dataa (386:386:386) (424:424:424)) - (PORT datab (1154:1154:1154) (1182:1182:1182)) - (PORT datac (966:966:966) (1033:1033:1033)) - (PORT datad (394:394:394) (449:449:449)) + (PORT dataa (1470:1470:1470) (1524:1524:1524)) + (PORT datab (214:214:214) (258:258:258)) + (PORT datac (187:187:187) (227:227:227)) (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~86) - (DELAY - (ABSOLUTE - (PORT dataa (220:220:220) (263:263:263)) - (PORT datab (205:205:205) (247:247:247)) - (PORT datac (178:178:178) (213:213:213)) - (PORT datad (179:179:179) (208:208:208)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|SYNTHESIZED_WIRE_0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (412:412:412) (441:441:441)) - (PORT datab (1103:1103:1103) (1121:1121:1121)) - (PORT datac (1068:1068:1068) (1079:1079:1079)) - (PORT datad (1177:1177:1177) (1222:1222:1222)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1155:1155:1155) (1182:1182:1182)) - (PORT datab (983:983:983) (1021:1021:1021)) - (PORT datac (960:960:960) (1025:1025:1025)) - (PORT datad (1127:1127:1127) (1138:1138:1138)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|carry_borrow_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (846:846:846) (907:907:907)) - (PORT datab (1376:1376:1376) (1400:1400:1400)) - (PORT datac (695:695:695) (778:778:778)) - (PORT datad (369:369:369) (389:389:389)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|d1_out) - (DELAY - (ABSOLUTE - (PORT datab (205:205:205) (247:247:247)) - (PORT datac (331:331:331) (357:357:357)) - (PORT datad (244:244:244) (316:316:316)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1545:1545:1545)) - (PORT asdata (1394:1394:1394) (1425:1425:1425)) - (PORT ena (821:821:821) (834:834:834)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1545:1545:1545)) - (PORT asdata (1396:1396:1396) (1427:1427:1427)) - (PORT ena (1266:1266:1266) (1269:1269:1269)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~45) - (DELAY - (ABSOLUTE - (PORT dataa (413:413:413) (478:478:478)) - (PORT datab (593:593:593) (633:633:633)) - (PORT datad (219:219:219) (288:288:288)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[3\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (815:815:815) (857:857:857)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1534:1534:1534)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1407:1407:1407) (1382:1382:1382)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1520:1520:1520) (1534:1534:1534)) - (PORT asdata (1165:1165:1165) (1197:1197:1197)) - (PORT ena (1263:1263:1263) (1264:1264:1264)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~48) - (DELAY - (ABSOLUTE - (PORT dataa (617:617:617) (678:678:678)) - (PORT datab (842:842:842) (870:870:870)) - (PORT datad (643:643:643) (672:672:672)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1545:1545:1545)) - (PORT asdata (1201:1201:1201) (1243:1243:1243)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1545:1545:1545)) - (PORT asdata (1200:1200:1200) (1247:1247:1247)) - (PORT ena (1220:1220:1220) (1214:1214:1214)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~49) - (DELAY - (ABSOLUTE - (PORT dataa (645:645:645) (705:705:705)) - (PORT datab (245:245:245) (328:328:328)) - (PORT datad (369:369:369) (400:400:400)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[3\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (812:812:812) (855:855:855)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1534:1534:1534)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1505:1505:1505) (1518:1518:1518)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1520:1520:1520) (1534:1534:1534)) - (PORT asdata (1168:1168:1168) (1200:1200:1200)) - (PORT ena (1207:1207:1207) (1190:1190:1190)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~41) - (DELAY - (ABSOLUTE - (PORT dataa (934:934:934) (963:963:963)) - (PORT datab (606:606:606) (617:617:617)) - (PORT datac (548:548:548) (570:570:570)) - (PORT datad (1519:1519:1519) (1633:1633:1633)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~42) - (DELAY - (ABSOLUTE - (PORT dataa (968:968:968) (1020:1020:1020)) - (PORT datab (580:580:580) (595:595:595)) - (PORT datac (1000:1000:1000) (1021:1021:1021)) - (PORT datad (861:861:861) (896:896:896)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datab combout (331:331:331) (342:342:342)) (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~43) + (INSTANCE z80_\|execute_\|ctl_mRead\~5) (DELAY (ABSOLUTE - (PORT dataa (221:221:221) (264:264:264)) - (PORT datab (681:681:681) (737:737:737)) - (PORT datac (172:172:172) (206:206:206)) - (PORT datad (171:171:171) (196:196:196)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (1216:1216:1216) (1312:1312:1312)) + (PORT datab (1851:1851:1851) (1863:1863:1863)) + (PORT datac (921:921:921) (968:968:968)) + (PORT datad (950:950:950) (1030:1030:1030)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -15665,26 +5087,10 @@ (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~44) (DELAY (ABSOLUTE - (PORT dataa (542:542:542) (562:562:562)) - (PORT datab (612:612:612) (638:638:638)) - (PORT datac (854:854:854) (888:888:888)) - (PORT datad (607:607:607) (635:635:635)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~45) - (DELAY - (ABSOLUTE - (PORT dataa (624:624:624) (687:687:687)) - (PORT datab (643:643:643) (681:681:681)) - (PORT datac (1161:1161:1161) (1210:1210:1210)) - (PORT datad (581:581:581) (616:616:616)) + (PORT dataa (656:656:656) (699:699:699)) + (PORT datab (494:494:494) (576:576:576)) + (PORT datac (567:567:567) (592:592:592)) + (PORT datad (452:452:452) (532:532:532)) (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -15694,29 +5100,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~46) + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~36) (DELAY (ABSOLUTE - (PORT dataa (207:207:207) (255:255:255)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (603:603:603) (634:634:634)) - (PORT datad (181:181:181) (210:210:210)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_48) - (DELAY - (ABSOLUTE - (PORT datab (1437:1437:1437) (1505:1505:1505)) - (PORT datac (1211:1211:1211) (1273:1273:1273)) - (PORT datad (849:849:849) (886:886:886)) - (IOPATH datab combout (304:304:304) (311:311:311)) + (PORT dataa (1199:1199:1199) (1255:1255:1255)) + (PORT datab (861:861:861) (876:876:876)) + (PORT datac (897:897:897) (928:928:928)) + (PORT datad (945:945:945) (998:998:998)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -15724,102 +5116,45 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_44) + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~35) (DELAY (ABSOLUTE - (PORT datab (1435:1435:1435) (1506:1506:1506)) - (PORT datac (1214:1214:1214) (1277:1277:1277)) - (PORT datad (841:841:841) (870:870:870)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (1212:1212:1212) (1298:1298:1298)) + (PORT datab (1168:1168:1168) (1213:1213:1213)) + (PORT datad (618:618:618) (642:642:642)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_45) + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~46) (DELAY (ABSOLUTE - (PORT datab (1431:1431:1431) (1499:1499:1499)) - (PORT datac (1202:1202:1202) (1265:1265:1265)) - (PORT datad (842:842:842) (868:868:868)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1537:1537:1537)) - (PORT asdata (1009:1009:1009) (1065:1065:1065)) - (PORT ena (990:990:990) (994:994:994)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_49) - (DELAY - (ABSOLUTE - (PORT datab (1431:1431:1431) (1500:1500:1500)) - (PORT datac (1204:1204:1204) (1267:1267:1267)) - (PORT datad (851:851:851) (887:887:887)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1537:1537:1537)) - (PORT asdata (1012:1012:1012) (1067:1067:1067)) - (PORT ena (973:973:973) (964:964:964)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~40) - (DELAY - (ABSOLUTE - (PORT dataa (461:461:461) (523:523:523)) - (PORT datab (490:490:490) (541:541:541)) - (PORT datad (217:217:217) (285:285:285)) + (PORT dataa (1793:1793:1793) (1881:1881:1881)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (1680:1680:1680) (1774:1774:1774)) + (PORT datad (173:173:173) (199:199:199)) (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_52) + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~33) (DELAY (ABSOLUTE - (PORT datab (1436:1436:1436) (1501:1501:1501)) - (PORT datac (1209:1209:1209) (1271:1271:1271)) - (PORT datad (1072:1072:1072) (1103:1103:1103)) - (IOPATH datab combout (304:304:304) (311:311:311)) + (PORT dataa (1197:1197:1197) (1236:1236:1236)) + (PORT datab (950:950:950) (991:991:991)) + (PORT datac (1433:1433:1433) (1477:1477:1477)) + (PORT datad (636:636:636) (679:679:679)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -15827,73 +5162,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_57) + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~47) (DELAY (ABSOLUTE - (PORT datab (1436:1436:1436) (1506:1506:1506)) - (PORT datac (1213:1213:1213) (1276:1276:1276)) - (PORT datad (987:987:987) (1036:1036:1036)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (1181:1181:1181) (1200:1200:1200)) - (PORT ena (1400:1400:1400) (1413:1413:1413)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_53) - (DELAY - (ABSOLUTE - (PORT datab (1437:1437:1437) (1502:1502:1502)) - (PORT datac (1212:1212:1212) (1275:1275:1275)) - (PORT datad (1074:1074:1074) (1101:1101:1101)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (1183:1183:1183) (1203:1203:1203)) - (PORT ena (1388:1388:1388) (1427:1427:1427)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_56) - (DELAY - (ABSOLUTE - (PORT datab (1438:1438:1438) (1503:1503:1503)) - (PORT datac (1218:1218:1218) (1279:1279:1279)) - (PORT datad (985:985:985) (1032:1032:1032)) - (IOPATH datab combout (304:304:304) (311:311:311)) + (PORT dataa (1552:1552:1552) (1656:1656:1656)) + (PORT datab (1179:1179:1179) (1236:1236:1236)) + (PORT datac (1130:1130:1130) (1165:1165:1165)) + (PORT datad (2516:2516:2516) (2622:2622:2622)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -15901,135 +5178,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~41) + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla9M1T5_2) (DELAY (ABSOLUTE - (PORT dataa (929:929:929) (988:988:988)) - (PORT datab (242:242:242) (325:325:325)) - (PORT datad (882:882:882) (948:948:948)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_33) - (DELAY - (ABSOLUTE - (PORT datab (1221:1221:1221) (1292:1292:1292)) - (PORT datac (894:894:894) (941:941:941)) - (PORT datad (886:886:886) (945:945:945)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (1204:1204:1204) (1243:1243:1243)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[3\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (936:936:936) (997:997:997)) - (PORT datab (1221:1221:1221) (1285:1285:1285)) - (PORT datad (879:879:879) (935:935:935)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1180:1180:1180) (1217:1217:1217)) - (PORT datab (204:204:204) (246:246:246)) - (PORT datac (1821:1821:1821) (1898:1898:1898)) - (PORT datad (203:203:203) (239:239:239)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~12) - (DELAY - (ABSOLUTE - (PORT dataa (883:883:883) (899:899:899)) - (PORT datab (206:206:206) (247:247:247)) - (PORT datac (601:601:601) (662:662:662)) - (PORT datad (870:870:870) (912:912:912)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_29) - (DELAY - (ABSOLUTE - (PORT dataa (1473:1473:1473) (1527:1527:1527)) - (PORT datac (833:833:833) (838:838:838)) - (PORT datad (1122:1122:1122) (1157:1157:1157)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1534:1534:1534)) - (PORT asdata (981:981:981) (1026:1026:1026)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_28) - (DELAY - (ABSOLUTE - (PORT dataa (1475:1475:1475) (1527:1527:1527)) - (PORT datac (835:835:835) (838:838:838)) - (PORT datad (1125:1125:1125) (1158:1158:1158)) - (IOPATH dataa combout (341:341:341) (347:347:347)) + (PORT dataa (1075:1075:1075) (1128:1128:1128)) + (PORT datab (1701:1701:1701) (1724:1724:1724)) + (PORT datac (838:838:838) (929:929:929)) + (PORT datad (964:964:964) (1036:1036:1036)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -16037,80 +5194,59 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~44) + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~45) (DELAY (ABSOLUTE - (PORT dataa (1083:1083:1083) (1099:1099:1099)) - (PORT datab (1166:1166:1166) (1217:1217:1217)) - (PORT datad (239:239:239) (279:279:279)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) + (PORT dataa (948:948:948) (1000:1000:1000)) + (PORT datab (1783:1783:1783) (1888:1888:1888)) + (PORT datac (1549:1549:1549) (1647:1647:1647)) + (PORT datad (1812:1812:1812) (1928:1928:1928)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[3\]\~feeder) + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~34) (DELAY (ABSOLUTE - (PORT datad (656:656:656) (709:709:709)) + (PORT dataa (952:952:952) (965:965:965)) + (PORT datab (980:980:980) (1032:1032:1032)) + (PORT datac (1654:1654:1654) (1682:1682:1682)) + (PORT datad (616:616:616) (638:638:638)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_69) + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla10M5T4_2) (DELAY (ABSOLUTE - (PORT datab (1122:1122:1122) (1149:1149:1149)) - (PORT datac (1397:1397:1397) (1448:1448:1448)) - (PORT datad (822:822:822) (857:857:857)) - (IOPATH datab combout (306:306:306) (308:308:308)) + (PORT dataa (1213:1213:1213) (1267:1267:1267)) + (PORT datac (1299:1299:1299) (1398:1398:1398)) + (PORT datad (1818:1818:1818) (1895:1895:1895)) + (IOPATH dataa combout (304:304:304) (307:307:307)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_68\~2) + (INSTANCE z80_\|execute_\|ctl_mWrite\~6) (DELAY (ABSOLUTE - (PORT dataa (929:929:929) (987:987:987)) - (PORT datab (1220:1220:1220) (1288:1288:1288)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_64\~0) - (DELAY - (ABSOLUTE - (PORT dataa (403:403:403) (454:454:454)) - (PORT datab (944:944:944) (1025:1025:1025)) - (PORT datac (1146:1146:1146) (1186:1186:1186)) - (PORT datad (666:666:666) (686:686:686)) + (PORT dataa (986:986:986) (1093:1093:1093)) + (PORT datab (1089:1089:1089) (1155:1155:1155)) + (PORT datac (630:630:630) (653:653:653)) + (PORT datad (1665:1665:1665) (1798:1798:1798)) (IOPATH dataa combout (324:324:324) (328:328:328)) (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -16120,11 +5256,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_69\~2) + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~50) (DELAY (ABSOLUTE - (PORT datac (1438:1438:1438) (1484:1484:1484)) - (PORT datad (1123:1123:1123) (1155:1155:1155)) + (PORT dataa (1148:1148:1148) (1201:1201:1201)) + (PORT datab (987:987:987) (1049:1049:1049)) + (PORT datac (990:990:990) (1074:1074:1074)) + (PORT datad (1286:1286:1286) (1359:1359:1359)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (370:370:370) (422:422:422)) + (PORT datab (392:392:392) (422:422:422)) + (PORT datac (1279:1279:1279) (1371:1371:1371)) + (PORT datad (194:194:194) (220:220:220)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -16132,44 +5288,500 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_65\~0) + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~48) (DELAY (ABSOLUTE - (PORT dataa (1170:1170:1170) (1265:1265:1265)) - (PORT datab (813:813:813) (832:832:832)) - (PORT datac (1134:1134:1134) (1171:1171:1171)) - (PORT datad (664:664:664) (713:713:713)) + (PORT dataa (347:347:347) (386:386:386)) + (PORT datab (870:870:870) (966:966:966)) + (PORT datac (814:814:814) (864:864:864)) + (PORT datad (963:963:963) (1033:1033:1033)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~49) + (DELAY + (ABSOLUTE + (PORT dataa (1009:1009:1009) (1108:1108:1108)) + (PORT datab (685:685:685) (743:743:743)) + (PORT datac (1211:1211:1211) (1287:1287:1287)) + (PORT datad (1529:1529:1529) (1619:1619:1619)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~7) + (DELAY + (ABSOLUTE + (PORT dataa (941:941:941) (968:968:968)) + (PORT datab (922:922:922) (974:974:974)) + (PORT datad (1618:1618:1618) (1707:1707:1707)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~29) + (DELAY + (ABSOLUTE + (PORT dataa (998:998:998) (1048:1048:1048)) + (PORT datab (1493:1493:1493) (1551:1551:1551)) + (PORT datac (1064:1064:1064) (1089:1089:1089)) + (PORT datad (1628:1628:1628) (1750:1750:1750)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~11) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (266:266:266)) + (PORT datab (241:241:241) (280:280:280)) + (PORT datac (2369:2369:2369) (2479:2479:2479)) + (PORT datad (992:992:992) (1075:1075:1075)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~27) + (DELAY + (ABSOLUTE + (PORT dataa (1386:1386:1386) (1429:1429:1429)) + (PORT datab (630:630:630) (663:663:663)) + (PORT datac (952:952:952) (1007:1007:1007)) + (PORT datad (400:400:400) (448:448:448)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~44) + (DELAY + (ABSOLUTE + (PORT dataa (933:933:933) (1006:1006:1006)) + (PORT datab (962:962:962) (1010:1010:1010)) + (PORT datac (1861:1861:1861) (1977:1977:1977)) + (PORT datad (1869:1869:1869) (1988:1988:1988)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~28) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (266:266:266)) + (PORT datab (393:393:393) (414:414:414)) + (PORT datad (830:830:830) (852:852:852)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~30) + (DELAY + (ABSOLUTE + (PORT dataa (889:889:889) (944:944:944)) + (PORT datab (832:832:832) (859:859:859)) + (PORT datad (860:860:860) (891:891:891)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1303:1303:1303) (1385:1385:1385)) + (PORT datab (1924:1924:1924) (2018:2018:2018)) + (PORT datac (745:745:745) (851:851:851)) + (PORT datad (823:823:823) (840:840:840)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~3) + (DELAY + (ABSOLUTE + (PORT dataa (719:719:719) (796:796:796)) + (PORT datab (1041:1041:1041) (1183:1183:1183)) + (PORT datac (1281:1281:1281) (1349:1349:1349)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~37) + (DELAY + (ABSOLUTE + (PORT dataa (1069:1069:1069) (1106:1106:1106)) + (PORT datab (982:982:982) (1037:1037:1037)) + (PORT datac (1244:1244:1244) (1292:1292:1292)) + (PORT datad (613:613:613) (631:631:631)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~38) + (DELAY + (ABSOLUTE + (PORT dataa (619:619:619) (663:663:663)) + (PORT datab (1324:1324:1324) (1447:1447:1447)) + (PORT datac (896:896:896) (928:928:928)) + (PORT datad (172:172:172) (197:197:197)) (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~39) + (DELAY + (ABSOLUTE + (PORT dataa (198:198:198) (240:240:240)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (171:171:171) (205:205:205)) + (PORT datad (172:172:172) (196:196:196)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[3\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~43) (DELAY (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (1504:1504:1504) (1545:1545:1545)) - (PORT ena (1131:1131:1131) (1098:1098:1098)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (PORT dataa (1134:1134:1134) (1214:1214:1214)) + (PORT datab (651:651:651) (689:689:689)) + (PORT datac (1164:1164:1164) (1221:1221:1221)) + (PORT datad (1212:1212:1212) (1252:1252:1252)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_68) + (INSTANCE z80_\|execute_\|ctl_alu_oe\~3) (DELAY (ABSOLUTE - (PORT datab (1121:1121:1121) (1148:1148:1148)) - (PORT datac (1398:1398:1398) (1447:1447:1447)) - (PORT datad (821:821:821) (856:856:856)) + (PORT dataa (1726:1726:1726) (1802:1802:1802)) + (PORT datab (310:310:310) (407:407:407)) + (PORT datac (1834:1834:1834) (1865:1865:1865)) + (PORT datad (583:583:583) (603:603:603)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~1) + (DELAY + (ABSOLUTE + (PORT dataa (688:688:688) (743:743:743)) + (PORT datab (1760:1760:1760) (1801:1801:1801)) + (PORT datac (675:675:675) (732:732:732)) + (PORT datad (862:862:862) (917:917:917)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~1) + (DELAY + (ABSOLUTE + (PORT datab (1184:1184:1184) (1221:1221:1221)) + (PORT datac (1397:1397:1397) (1458:1458:1458)) + (PORT datad (1210:1210:1210) (1274:1274:1274)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1521:1521:1521) (1593:1593:1593)) + (PORT datab (1032:1032:1032) (1091:1091:1091)) + (PORT datac (856:856:856) (896:896:896)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~17) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (407:407:407)) + (PORT datab (942:942:942) (977:977:977)) + (PORT datad (615:615:615) (659:659:659)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_iorw\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1562:1562:1562) (1693:1693:1693)) + (PORT datab (1495:1495:1495) (1547:1547:1547)) + (PORT datac (1378:1378:1378) (1554:1554:1554)) + (PORT datad (1508:1508:1508) (1640:1640:1640)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~47) + (DELAY + (ABSOLUTE + (PORT dataa (946:946:946) (987:987:987)) + (PORT datab (937:937:937) (964:964:964)) + (PORT datac (185:185:185) (226:226:226)) + (PORT datad (1578:1578:1578) (1559:1559:1559)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1625:1625:1625) (1763:1763:1763)) + (PORT datab (1659:1659:1659) (1746:1746:1746)) + (PORT datac (2115:2115:2115) (2208:2208:2208)) + (PORT datad (879:879:879) (933:933:933)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~13) + (DELAY + (ABSOLUTE + (PORT datab (1186:1186:1186) (1222:1222:1222)) + (PORT datac (1402:1402:1402) (1461:1461:1461)) + (PORT datad (1209:1209:1209) (1271:1271:1271)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~48) + (DELAY + (ABSOLUTE + (PORT dataa (657:657:657) (679:679:679)) + (PORT datac (1092:1092:1092) (1098:1098:1098)) + (PORT datad (563:563:563) (579:579:579)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~0) + (DELAY + (ABSOLUTE + (PORT dataa (909:909:909) (954:954:954)) + (PORT datab (1482:1482:1482) (1542:1542:1542)) + (PORT datac (823:823:823) (872:872:872)) + (PORT datad (195:195:195) (221:221:221)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla57M1T4_4) + (DELAY + (ABSOLUTE + (PORT datab (1124:1124:1124) (1227:1227:1227)) + (PORT datac (2388:2388:2388) (2467:2467:2467)) + (PORT datad (1389:1389:1389) (1445:1445:1445)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~9) + (DELAY + (ABSOLUTE + (PORT datac (841:841:841) (934:934:934)) + (PORT datad (964:964:964) (1033:1033:1033)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (2570:2570:2570) (2599:2599:2599)) + (PORT datab (1711:1711:1711) (1793:1793:1793)) + (PORT datac (2040:2040:2040) (2106:2106:2106)) + (PORT datad (926:926:926) (970:970:970)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla12M3T1_2) + (DELAY + (ABSOLUTE + (PORT datab (1585:1585:1585) (1644:1644:1644)) + (PORT datac (1798:1798:1798) (1888:1888:1888)) + (PORT datad (955:955:955) (1073:1073:1073)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1138:1138:1138) (1211:1211:1211)) + (PORT datab (2100:2100:2100) (2152:2152:2152)) + (PORT datac (1427:1427:1427) (1516:1516:1516)) + (PORT datad (873:873:873) (902:902:902)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1279:1279:1279) (1378:1378:1378)) + (PORT datab (1710:1710:1710) (1793:1793:1793)) + (PORT datac (1379:1379:1379) (1430:1430:1430)) + (PORT datad (1246:1246:1246) (1297:1297:1297)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~10) + (DELAY + (ABSOLUTE + (PORT dataa (839:839:839) (913:913:913)) + (PORT datab (821:821:821) (872:872:872)) + (PORT datac (356:356:356) (384:384:384)) + (PORT datad (619:619:619) (676:676:676)) + (IOPATH dataa combout (304:304:304) (299:299:299)) (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -16178,28 +5790,519 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~43) + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~10) (DELAY (ABSOLUTE - (PORT dataa (379:379:379) (453:453:453)) - (PORT datab (887:887:887) (923:923:923)) - (PORT datad (364:364:364) (388:388:388)) - (IOPATH dataa combout (304:304:304) (307:307:307)) + (PORT dataa (927:927:927) (998:998:998)) + (PORT datab (1062:1062:1062) (1143:1143:1143)) + (PORT datac (1799:1799:1799) (1899:1899:1899)) + (PORT datad (1114:1114:1114) (1175:1175:1175)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel_pla11M1T1_11) + (DELAY + (ABSOLUTE + (PORT datab (1233:1233:1233) (1310:1310:1310)) + (PORT datac (1159:1159:1159) (1255:1255:1255)) + (PORT datad (1515:1515:1515) (1578:1578:1578)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~11) + (DELAY + (ABSOLUTE + (PORT dataa (598:598:598) (612:612:612)) + (PORT datab (904:904:904) (941:941:941)) + (PORT datac (1425:1425:1425) (1549:1549:1549)) + (PORT datad (854:854:854) (911:911:911)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~11) + (DELAY + (ABSOLUTE + (PORT dataa (662:662:662) (716:716:716)) + (PORT datab (206:206:206) (248:248:248)) + (PORT datac (875:875:875) (908:908:908)) + (PORT datad (1885:1885:1885) (1993:1993:1993)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~1) + (DELAY + (ABSOLUTE + (PORT datac (195:195:195) (235:235:235)) + (PORT datad (209:209:209) (240:240:240)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~4) + (DELAY + (ABSOLUTE + (PORT datac (1272:1272:1272) (1358:1358:1358)) + (PORT datad (2394:2394:2394) (2515:2515:2515)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1498:1498:1498) (1593:1593:1593)) + (PORT datab (1938:1938:1938) (2058:2058:2058)) + (PORT datac (1282:1282:1282) (1342:1342:1342)) + (PORT datad (1494:1494:1494) (1555:1555:1555)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~4) + (DELAY + (ABSOLUTE + (PORT dataa (945:945:945) (1005:1005:1005)) + (PORT datab (1462:1462:1462) (1478:1478:1478)) + (PORT datac (1216:1216:1216) (1256:1256:1256)) + (PORT datad (632:632:632) (677:677:677)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1186:1186:1186) (1211:1211:1211)) + (PORT datab (1426:1426:1426) (1452:1452:1452)) + (PORT datac (1645:1645:1645) (1692:1692:1692)) + (PORT datad (906:906:906) (931:931:931)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (572:572:572) (597:597:597)) + (PORT datab (638:638:638) (678:678:678)) + (PORT datac (635:635:635) (693:693:693)) + (PORT datad (1270:1270:1270) (1340:1340:1340)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~47) + (DELAY + (ABSOLUTE + (PORT dataa (231:231:231) (277:277:277)) + (PORT datab (1228:1228:1228) (1303:1303:1303)) + (PORT datac (1537:1537:1537) (1646:1646:1646)) + (PORT datad (2345:2345:2345) (2485:2485:2485)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1650:1650:1650) (1734:1734:1734)) + (PORT datab (1126:1126:1126) (1204:1204:1204)) + (PORT datac (976:976:976) (1038:1038:1038)) + (PORT datad (180:180:180) (209:209:209)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1131:1131:1131) (1178:1178:1178)) + (PORT datab (1156:1156:1156) (1201:1201:1201)) + (PORT datac (389:389:389) (422:422:422)) + (PORT datad (947:947:947) (1020:1020:1020)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~23) + (DELAY + (ABSOLUTE + (PORT dataa (2319:2319:2319) (2382:2382:2382)) + (PORT datab (1419:1419:1419) (1524:1524:1524)) + (PORT datac (630:630:630) (677:677:677)) + (PORT datad (1440:1440:1440) (1526:1526:1526)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1842:1842:1842) (1975:1975:1975)) + (PORT datab (218:218:218) (256:256:256)) + (PORT datac (1759:1759:1759) (1877:1877:1877)) + (PORT datad (647:647:647) (706:706:706)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~13) + (DELAY + (ABSOLUTE + (PORT dataa (573:573:573) (604:604:604)) + (PORT datab (887:887:887) (918:918:918)) + (PORT datac (600:600:600) (617:617:617)) + (PORT datad (1021:1021:1021) (1018:1018:1018)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1289:1289:1289) (1346:1346:1346)) + (PORT datab (1711:1711:1711) (1793:1793:1793)) + (PORT datac (1378:1378:1378) (1430:1430:1430)) + (PORT datad (1993:1993:1993) (2056:2056:2056)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~1) + (DELAY + (ABSOLUTE + (PORT datac (523:523:523) (541:541:541)) + (PORT datad (598:598:598) (630:630:630)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~29) + (DELAY + (ABSOLUTE + (PORT dataa (1109:1109:1109) (1160:1160:1160)) + (PORT datac (1594:1594:1594) (1729:1729:1729)) + (PORT datad (1744:1744:1744) (1800:1800:1800)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~14) + (DELAY + (ABSOLUTE + (PORT dataa (576:576:576) (616:616:616)) + (PORT datab (198:198:198) (236:236:236)) + (PORT datac (194:194:194) (226:226:226)) + (PORT datad (1196:1196:1196) (1210:1210:1210)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla77M1T1_3) + (DELAY + (ABSOLUTE + (PORT dataa (927:927:927) (996:996:996)) + (PORT datab (1063:1063:1063) (1142:1142:1142)) + (PORT datac (1800:1800:1800) (1897:1897:1897)) + (PORT datad (1115:1115:1115) (1171:1171:1171)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel_pla82M1T1_16) + (DELAY + (ABSOLUTE + (PORT dataa (2188:2188:2188) (2320:2320:2320)) + (PORT datab (1249:1249:1249) (1337:1337:1337)) + (PORT datac (1169:1169:1169) (1222:1222:1222)) + (PORT datad (1585:1585:1585) (1612:1612:1612)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1710:1710:1710) (1802:1802:1802)) + (PORT datab (954:954:954) (997:997:997)) + (PORT datac (1214:1214:1214) (1292:1292:1292)) + (PORT datad (1992:1992:1992) (2067:2067:2067)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1806:1806:1806) (1900:1900:1900)) + (PORT datab (2414:2414:2414) (2552:2552:2552)) + (PORT datac (969:969:969) (1019:1019:1019)) + (PORT datad (1654:1654:1654) (1727:1727:1727)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT datab (1225:1225:1225) (1272:1272:1272)) + (PORT datac (865:865:865) (921:921:921)) + (PORT datad (179:179:179) (208:208:208)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (422:422:422) (483:483:483)) + (PORT datab (2457:2457:2457) (2574:2574:2574)) + (PORT datac (1535:1535:1535) (1632:1632:1632)) + (PORT datad (196:196:196) (222:222:222)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1958:1958:1958) (2047:2047:2047)) + (PORT datab (1490:1490:1490) (1615:1615:1615)) + (PORT datac (1941:1941:1941) (2054:2054:2054)) + (PORT datad (813:813:813) (814:814:814)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal68\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1002:1002:1002) (1101:1101:1101)) + (PORT datab (995:995:995) (1100:1100:1100)) + (PORT datac (930:930:930) (1052:1052:1052)) + (PORT datad (1208:1208:1208) (1317:1317:1317)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1164:1164:1164) (1212:1212:1212)) + (PORT datab (1589:1589:1589) (1690:1690:1690)) + (PORT datac (1934:1934:1934) (2077:2077:2077)) + (PORT datad (636:636:636) (681:681:681)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (355:355:355) (389:389:389)) + (PORT datab (337:337:337) (370:370:370)) + (PORT datac (604:604:604) (621:621:621)) + (PORT datad (586:586:586) (609:609:609)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1421:1421:1421) (1480:1480:1480)) + (PORT datab (1325:1325:1325) (1389:1389:1389)) + (PORT datac (2509:2509:2509) (2600:2600:2600)) + (PORT datad (626:626:626) (665:665:665)) + (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_76\~0) + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~8) (DELAY (ABSOLUTE - (PORT dataa (408:408:408) (464:464:464)) - (PORT datab (1404:1404:1404) (1437:1437:1437)) - (PORT datac (1139:1139:1139) (1179:1179:1179)) - (PORT datad (663:663:663) (683:683:683)) + (PORT dataa (957:957:957) (1012:1012:1012)) + (PORT datac (193:193:193) (227:227:227)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~20) + (DELAY + (ABSOLUTE + (PORT dataa (2048:2048:2048) (2151:2151:2151)) + (PORT datab (1475:1475:1475) (1514:1514:1514)) + (PORT datac (1735:1735:1735) (1813:1813:1813)) + (PORT datad (1685:1685:1685) (1760:1760:1760)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~9) + (DELAY + (ABSOLUTE + (PORT dataa (584:584:584) (611:611:611)) + (PORT datab (1341:1341:1341) (1437:1437:1437)) + (PORT datac (581:581:581) (583:583:583)) + (PORT datad (584:584:584) (598:598:598)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -16209,13 +6312,481 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_77\~0) + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~1) (DELAY (ABSOLUTE - (PORT dataa (1146:1146:1146) (1180:1180:1180)) - (PORT datab (815:815:815) (833:833:833)) - (PORT datac (1143:1143:1143) (1180:1180:1180)) - (PORT datad (671:671:671) (721:721:721)) + (PORT dataa (1788:1788:1788) (1886:1886:1886)) + (PORT datab (1610:1610:1610) (1712:1712:1712)) + (PORT datac (1206:1206:1206) (1258:1258:1258)) + (PORT datad (1676:1676:1676) (1684:1684:1684)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~1) + (DELAY + (ABSOLUTE + (PORT datab (1710:1710:1710) (1787:1787:1787)) + (PORT datac (1374:1374:1374) (1426:1426:1426)) + (PORT datad (1249:1249:1249) (1299:1299:1299)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1312:1312:1312) (1412:1412:1412)) + (PORT datab (841:841:841) (849:849:849)) + (PORT datac (1462:1462:1462) (1589:1589:1589)) + (PORT datad (1074:1074:1074) (1110:1110:1110)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~2) + (DELAY + (ABSOLUTE + (PORT datab (352:352:352) (380:380:380)) + (PORT datac (1868:1868:1868) (1874:1874:1874)) + (PORT datad (656:656:656) (671:671:671)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~17) + (DELAY + (ABSOLUTE + (PORT dataa (2131:2131:2131) (2239:2239:2239)) + (PORT datab (626:626:626) (661:661:661)) + (PORT datac (1313:1313:1313) (1389:1389:1389)) + (PORT datad (391:391:391) (440:440:440)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~18) + (DELAY + (ABSOLUTE + (PORT dataa (2118:2118:2118) (2232:2232:2232)) + (PORT datab (1816:1816:1816) (1930:1930:1930)) + (PORT datac (935:935:935) (973:973:973)) + (PORT datad (908:908:908) (959:959:959)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1429:1429:1429) (1453:1453:1453)) + (PORT datab (216:216:216) (261:261:261)) + (PORT datac (935:935:935) (967:967:967)) + (PORT datad (662:662:662) (727:727:727)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~19) + (DELAY + (ABSOLUTE + (PORT dataa (654:654:654) (677:677:677)) + (PORT datab (1803:1803:1803) (1884:1884:1884)) + (PORT datac (1284:1284:1284) (1375:1375:1375)) + (PORT datad (1323:1323:1323) (1363:1363:1363)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal1\~5) + (DELAY + (ABSOLUTE + (PORT datac (1067:1067:1067) (1146:1146:1146)) + (PORT datad (1372:1372:1372) (1427:1427:1427)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~0) + (DELAY + (ABSOLUTE + (PORT dataa (944:944:944) (1004:1004:1004)) + (PORT datab (1712:1712:1712) (1802:1802:1802)) + (PORT datac (1159:1159:1159) (1189:1189:1189)) + (PORT datad (1813:1813:1813) (1951:1951:1951)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel_pla12M1T1_12\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1787:1787:1787) (1912:1912:1912)) + (PORT datab (2129:2129:2129) (2228:2228:2228)) + (PORT datac (1194:1194:1194) (1252:1252:1252)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~1) + (DELAY + (ABSOLUTE + (PORT dataa (384:384:384) (411:411:411)) + (PORT datab (2129:2129:2129) (2226:2226:2226)) + (PORT datac (178:178:178) (213:213:213)) + (PORT datad (1802:1802:1802) (1929:1929:1929)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~7) + (DELAY + (ABSOLUTE + (PORT dataa (881:881:881) (907:907:907)) + (PORT datab (937:937:937) (1032:1032:1032)) + (PORT datac (704:704:704) (776:776:776)) + (PORT datad (1013:1013:1013) (1073:1073:1073)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1416:1416:1416) (1474:1474:1474)) + (PORT datab (1710:1710:1710) (1796:1796:1796)) + (PORT datac (1673:1673:1673) (1742:1742:1742)) + (PORT datad (1246:1246:1246) (1299:1299:1299)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1258:1258:1258) (1353:1353:1353)) + (PORT datab (1405:1405:1405) (1490:1490:1490)) + (PORT datac (1724:1724:1724) (1804:1804:1804)) + (PORT datad (595:595:595) (607:607:607)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~8) + (DELAY + (ABSOLUTE + (PORT dataa (848:848:848) (858:858:858)) + (PORT datab (801:801:801) (803:803:803)) + (PORT datac (533:533:533) (540:540:540)) + (PORT datad (588:588:588) (604:604:604)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~15) + (DELAY + (ABSOLUTE + (PORT dataa (355:355:355) (387:387:387)) + (PORT datab (355:355:355) (381:381:381)) + (PORT datac (321:321:321) (343:343:343)) + (PORT datad (332:332:332) (348:348:348)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~7) + (DELAY + (ABSOLUTE + (PORT dataa (900:900:900) (956:956:956)) + (PORT datab (390:390:390) (420:420:420)) + (PORT datac (672:672:672) (718:718:718)) + (PORT datad (374:374:374) (405:405:405)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~12) + (DELAY + (ABSOLUTE + (PORT dataa (406:406:406) (451:451:451)) + (PORT datab (221:221:221) (260:260:260)) + (PORT datac (1536:1536:1536) (1624:1624:1624)) + (PORT datad (1236:1236:1236) (1338:1338:1338)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1611:1611:1611) (1705:1705:1705)) + (PORT datab (2059:2059:2059) (2157:2157:2157)) + (PORT datac (2103:2103:2103) (2208:2208:2208)) + (PORT datad (1923:1923:1923) (2008:2008:2008)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~10) + (DELAY + (ABSOLUTE + (PORT dataa (198:198:198) (240:240:240)) + (PORT datab (1408:1408:1408) (1465:1465:1465)) + (PORT datac (1122:1122:1122) (1126:1126:1126)) + (PORT datad (201:201:201) (230:230:230)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~8) + (DELAY + (ABSOLUTE + (PORT dataa (916:916:916) (954:954:954)) + (PORT datab (1496:1496:1496) (1586:1586:1586)) + (PORT datac (891:891:891) (908:908:908)) + (PORT datad (1270:1270:1270) (1340:1340:1340)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal64\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1002:1002:1002) (1138:1138:1138)) + (PORT datab (654:654:654) (715:715:715)) + (PORT datac (322:322:322) (348:348:348)) + (PORT datad (188:188:188) (219:219:219)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (632:632:632) (656:656:656)) + (PORT datab (2132:2132:2132) (2229:2229:2229)) + (PORT datac (1759:1759:1759) (1877:1877:1877)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal62\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1002:1002:1002) (1134:1134:1134)) + (PORT datab (651:651:651) (712:712:712)) + (PORT datac (325:325:325) (349:349:349)) + (PORT datad (187:187:187) (217:217:217)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1524:1524:1524) (1624:1624:1624)) + (PORT datab (1149:1149:1149) (1229:1229:1229)) + (PORT datac (216:216:216) (256:256:256)) + (PORT datad (1269:1269:1269) (1336:1336:1336)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~46) + (DELAY + (ABSOLUTE + (PORT dataa (1675:1675:1675) (1783:1783:1783)) + (PORT datab (1430:1430:1430) (1468:1468:1468)) + (PORT datac (645:645:645) (660:660:660)) + (PORT datad (2755:2755:2755) (2813:2813:2813)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1185:1185:1185) (1222:1222:1222)) + (PORT datab (2780:2780:2780) (2854:2854:2854)) + (PORT datac (1643:1643:1643) (1747:1747:1747)) + (PORT datad (1901:1901:1901) (2004:2004:2004)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~7) + (DELAY + (ABSOLUTE + (PORT dataa (659:659:659) (717:717:717)) + (PORT datab (658:658:658) (685:685:685)) + (PORT datac (1140:1140:1140) (1183:1183:1183)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~11) + (DELAY + (ABSOLUTE + (PORT dataa (680:680:680) (735:735:735)) + (PORT datab (355:355:355) (385:385:385)) + (PORT datac (923:923:923) (989:989:989)) + (PORT datad (187:187:187) (217:217:217)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal62\~3) + (DELAY + (ABSOLUTE + (PORT dataa (2003:2003:2003) (2196:2196:2196)) + (PORT datab (1221:1221:1221) (1319:1319:1319)) + (PORT datac (963:963:963) (986:986:986)) + (PORT datad (1268:1268:1268) (1352:1352:1352)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -16223,14 +6794,1526 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1229:1229:1229) (1254:1254:1254)) + (PORT datab (656:656:656) (680:680:680)) + (PORT datac (2218:2218:2218) (2248:2248:2248)) + (PORT datad (1113:1113:1113) (1134:1134:1134)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (263:263:263)) + (PORT datab (912:912:912) (948:948:948)) + (PORT datac (801:801:801) (807:807:807)) + (PORT datad (1160:1160:1160) (1209:1209:1209)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (255:255:255)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (194:194:194) (220:220:220)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~9) + (DELAY + (ABSOLUTE + (PORT dataa (579:579:579) (616:616:616)) + (PORT datab (219:219:219) (257:257:257)) + (PORT datac (827:827:827) (828:828:828)) + (PORT datad (635:635:635) (645:645:645)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~6) + (DELAY + (ABSOLUTE + (PORT dataa (978:978:978) (1045:1045:1045)) + (PORT datab (1725:1725:1725) (1763:1763:1763)) + (PORT datac (961:961:961) (991:991:991)) + (PORT datad (658:658:658) (694:694:694)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~7) + (DELAY + (ABSOLUTE + (PORT dataa (981:981:981) (1052:1052:1052)) + (PORT datab (926:926:926) (972:972:972)) + (PORT datac (959:959:959) (990:990:990)) + (PORT datad (194:194:194) (220:220:220)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~1) + (DELAY + (ABSOLUTE + (PORT dataa (609:609:609) (642:642:642)) + (PORT datab (1259:1259:1259) (1318:1318:1318)) + (PORT datac (1105:1105:1105) (1155:1155:1155)) + (PORT datad (542:542:542) (549:549:549)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (958:958:958) (992:992:992)) + (PORT datab (1245:1245:1245) (1321:1321:1321)) + (PORT datac (1223:1223:1223) (1310:1310:1310)) + (PORT datad (915:915:915) (952:952:952)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~4) + (DELAY + (ABSOLUTE + (PORT dataa (935:935:935) (980:980:980)) + (PORT datab (692:692:692) (730:730:730)) + (PORT datac (1698:1698:1698) (1738:1738:1738)) + (PORT datad (1113:1113:1113) (1131:1131:1131)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~5) + (DELAY + (ABSOLUTE + (PORT dataa (936:936:936) (984:984:984)) + (PORT datab (1137:1137:1137) (1172:1172:1172)) + (PORT datac (895:895:895) (939:939:939)) + (PORT datad (195:195:195) (220:220:220)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~2) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (877:877:877) (911:911:911)) + (PORT datac (1173:1173:1173) (1210:1210:1210)) + (PORT datad (568:568:568) (585:585:585)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla21M2T3_4) + (DELAY + (ABSOLUTE + (PORT dataa (971:971:971) (1039:1039:1039)) + (PORT datab (1668:1668:1668) (1733:1733:1733)) + (PORT datac (940:940:940) (1053:1053:1053)) + (PORT datad (651:651:651) (709:709:709)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~6) + (DELAY + (ABSOLUTE + (PORT dataa (635:635:635) (652:652:652)) + (PORT datab (1696:1696:1696) (1875:1875:1875)) + (PORT datac (1371:1371:1371) (1456:1456:1456)) + (PORT datad (316:316:316) (337:337:337)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~12) + (DELAY + (ABSOLUTE + (PORT dataa (997:997:997) (1039:1039:1039)) + (PORT datab (681:681:681) (743:743:743)) + (PORT datac (1370:1370:1370) (1453:1453:1453)) + (PORT datad (688:688:688) (735:735:735)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1081:1081:1081) (1099:1099:1099)) + (PORT datab (1323:1323:1323) (1327:1327:1327)) + (PORT datac (1868:1868:1868) (1871:1871:1871)) + (PORT datad (640:640:640) (651:651:651)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~3) + (DELAY + (ABSOLUTE + (PORT dataa (354:354:354) (390:390:390)) + (PORT datab (825:825:825) (851:851:851)) + (PORT datac (178:178:178) (217:217:217)) + (PORT datad (600:600:600) (623:623:623)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_high) + (DELAY + (ABSOLUTE + (PORT dataa (2212:2212:2212) (2301:2301:2301)) + (PORT datab (1863:1863:1863) (1975:1975:1975)) + (PORT datac (536:536:536) (552:552:552)) + (PORT datad (1238:1238:1238) (1329:1329:1329)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1281:1281:1281) (1347:1347:1347)) + (PORT datab (1610:1610:1610) (1648:1648:1648)) + (PORT datac (1169:1169:1169) (1222:1222:1222)) + (PORT datad (1696:1696:1696) (1799:1799:1799)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1632:1632:1632) (1662:1662:1662)) + (PORT datab (1265:1265:1265) (1333:1333:1333)) + (PORT datac (2462:2462:2462) (2596:2596:2596)) + (PORT datad (911:911:911) (938:938:938)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal61\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1561:1561:1561) (1694:1694:1694)) + (PORT datab (1558:1558:1558) (1623:1623:1623)) + (PORT datac (1379:1379:1379) (1557:1557:1557)) + (PORT datad (1509:1509:1509) (1636:1636:1636)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1285:1285:1285) (1353:1353:1353)) + (PORT datab (1252:1252:1252) (1341:1341:1341)) + (PORT datac (1128:1128:1128) (1177:1177:1177)) + (PORT datad (615:615:615) (659:659:659)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1494:1494:1494) (1588:1588:1588)) + (PORT datab (1151:1151:1151) (1164:1164:1164)) + (PORT datac (1070:1070:1070) (1069:1069:1069)) + (PORT datad (716:716:716) (790:790:790)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1149:1149:1149) (1182:1182:1182)) + (PORT datab (860:860:860) (889:889:889)) + (PORT datac (845:845:845) (891:891:891)) + (PORT datad (1613:1613:1613) (1637:1637:1637)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~18) + (DELAY + (ABSOLUTE + (PORT dataa (649:649:649) (671:671:671)) + (PORT datab (1804:1804:1804) (1888:1888:1888)) + (PORT datac (1288:1288:1288) (1380:1380:1380)) + (PORT datad (1322:1322:1322) (1363:1363:1363)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~10) + (DELAY + (ABSOLUTE + (PORT dataa (613:613:613) (649:649:649)) + (PORT datab (1251:1251:1251) (1289:1289:1289)) + (PORT datac (752:752:752) (764:764:764)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~2) + (DELAY + (ABSOLUTE + (PORT datab (610:610:610) (615:615:615)) + (PORT datac (633:633:633) (653:653:653)) + (PORT datad (1864:1864:1864) (1909:1909:1909)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1996:1996:1996) (2194:2194:2194)) + (PORT datab (1221:1221:1221) (1306:1306:1306)) + (PORT datad (1183:1183:1183) (1203:1203:1203)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~3) + (DELAY + (ABSOLUTE + (PORT dataa (944:944:944) (995:995:995)) + (PORT datab (1244:1244:1244) (1296:1296:1296)) + (PORT datac (2743:2743:2743) (2858:2858:2858)) + (PORT datad (1374:1374:1374) (1415:1415:1415)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~26) + (DELAY + (ABSOLUTE + (PORT dataa (1074:1074:1074) (1116:1116:1116)) + (PORT datab (1273:1273:1273) (1302:1302:1302)) + (PORT datac (1138:1138:1138) (1158:1158:1158)) + (PORT datad (1560:1560:1560) (1679:1679:1679)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (244:244:244)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (202:202:202) (239:239:239)) + (PORT datad (195:195:195) (220:220:220)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_lo\~9) + (DELAY + (ABSOLUTE + (PORT dataa (2193:2193:2193) (2363:2363:2363)) + (PORT datab (745:745:745) (820:820:820)) + (PORT datac (1804:1804:1804) (1892:1892:1892)) + (PORT datad (932:932:932) (1032:1032:1032)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (949:949:949) (978:978:978)) + (PORT datab (850:850:850) (909:909:909)) + (PORT datac (2180:2180:2180) (2265:2265:2265)) + (PORT datad (1711:1711:1711) (1846:1846:1846)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_oe\~1) + (DELAY + (ABSOLUTE + (PORT dataa (983:983:983) (1040:1040:1040)) + (PORT datab (873:873:873) (899:899:899)) + (PORT datac (918:918:918) (968:968:968)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~6) + (DELAY + (ABSOLUTE + (PORT dataa (892:892:892) (913:913:913)) + (PORT datab (1670:1670:1670) (1749:1749:1749)) + (PORT datac (934:934:934) (965:965:965)) + (PORT datad (1389:1389:1389) (1404:1404:1404)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1499:1499:1499) (1628:1628:1628)) + (PORT datab (937:937:937) (996:996:996)) + (PORT datac (1435:1435:1435) (1520:1520:1520)) + (PORT datad (1888:1888:1888) (1916:1916:1916)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~8) + (DELAY + (ABSOLUTE + (PORT dataa (218:218:218) (269:269:269)) + (PORT datac (1056:1056:1056) (1073:1073:1073)) + (PORT datad (653:653:653) (670:670:670)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~9) + (DELAY + (ABSOLUTE + (PORT dataa (937:937:937) (1004:1004:1004)) + (PORT datab (1474:1474:1474) (1513:1513:1513)) + (PORT datac (936:936:936) (975:975:975)) + (PORT datad (1646:1646:1646) (1715:1715:1715)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (257:257:257)) + (PORT datab (1671:1671:1671) (1753:1753:1753)) + (PORT datac (1246:1246:1246) (1319:1319:1319)) + (PORT datad (182:182:182) (212:212:212)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (635:635:635) (710:710:710)) + (PORT datab (1462:1462:1462) (1554:1554:1554)) + (PORT datac (2183:2183:2183) (2263:2263:2263)) + (PORT datad (1316:1316:1316) (1373:1373:1373)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (249:249:249) (295:295:295)) + (PORT datab (1590:1590:1590) (1583:1583:1583)) + (PORT datac (539:539:539) (554:554:554)) + (PORT datad (218:218:218) (258:258:258)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla83M1T3_2) + (DELAY + (ABSOLUTE + (PORT dataa (945:945:945) (1002:1002:1002)) + (PORT datab (1919:1919:1919) (1951:1951:1951)) + (PORT datac (1162:1162:1162) (1193:1193:1193)) + (PORT datad (1687:1687:1687) (1760:1760:1760)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1657:1657:1657) (1684:1684:1684)) + (PORT datab (1509:1509:1509) (1566:1566:1566)) + (PORT datac (626:626:626) (656:656:656)) + (PORT datad (948:948:948) (1027:1027:1027)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~38) + (DELAY + (ABSOLUTE + (PORT dataa (988:988:988) (1050:1050:1050)) + (PORT datab (1482:1482:1482) (1510:1510:1510)) + (PORT datac (1379:1379:1379) (1463:1463:1463)) + (PORT datad (907:907:907) (951:951:951)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~28) + (DELAY + (ABSOLUTE + (PORT dataa (945:945:945) (1002:1002:1002)) + (PORT datab (1713:1713:1713) (1799:1799:1799)) + (PORT datac (1162:1162:1162) (1193:1193:1193)) + (PORT datad (2291:2291:2291) (2362:2362:2362)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~6) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (700:700:700) (742:742:742)) + (PORT datac (821:821:821) (867:867:867)) + (PORT datad (211:211:211) (243:243:243)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~37) + (DELAY + (ABSOLUTE + (PORT dataa (2304:2304:2304) (2381:2381:2381)) + (PORT datab (1670:1670:1670) (1716:1716:1716)) + (PORT datac (604:604:604) (650:650:650)) + (PORT datad (898:898:898) (960:960:960)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~39) + (DELAY + (ABSOLUTE + (PORT dataa (1177:1177:1177) (1195:1195:1195)) + (PORT datab (531:531:531) (554:554:554)) + (PORT datac (570:570:570) (577:577:577)) + (PORT datad (1560:1560:1560) (1675:1675:1675)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_daa) + (DELAY + (ABSOLUTE + (PORT dataa (2150:2150:2150) (2247:2247:2247)) + (PORT datab (882:882:882) (944:944:944)) + (PORT datac (1798:1798:1798) (1902:1902:1902)) + (PORT datad (1114:1114:1114) (1173:1173:1173)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~7) + (DELAY + (ABSOLUTE + (PORT dataa (424:424:424) (486:486:486)) + (PORT datab (627:627:627) (663:663:663)) + (PORT datac (1709:1709:1709) (1751:1751:1751)) + (PORT datad (2329:2329:2329) (2397:2397:2397)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~8) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (2354:2354:2354) (2430:2430:2430)) + (PORT datac (882:882:882) (943:943:943)) + (PORT datad (196:196:196) (222:222:222)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~30) + (DELAY + (ABSOLUTE + (PORT dataa (1727:1727:1727) (1814:1814:1814)) + (PORT datab (952:952:952) (1007:1007:1007)) + (PORT datac (1672:1672:1672) (1742:1742:1742)) + (PORT datad (1045:1045:1045) (1128:1128:1128)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~31) + (DELAY + (ABSOLUTE + (PORT datab (629:629:629) (646:646:646)) + (PORT datac (852:852:852) (860:860:860)) + (PORT datad (549:549:549) (555:555:555)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~25) + (DELAY + (ABSOLUTE + (PORT datac (1712:1712:1712) (1753:1753:1753)) + (PORT datad (632:632:632) (691:691:691)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~40) + (DELAY + (ABSOLUTE + (PORT dataa (667:667:667) (712:712:712)) + (PORT datab (1437:1437:1437) (1441:1441:1441)) + (PORT datac (1443:1443:1443) (1489:1489:1489)) + (PORT datad (838:838:838) (875:875:875)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~42) + (DELAY + (ABSOLUTE + (PORT dataa (209:209:209) (257:257:257)) + (PORT datab (633:633:633) (653:653:653)) + (PORT datac (801:801:801) (833:833:833)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla65npla52M1T4_4) + (DELAY + (ABSOLUTE + (PORT dataa (1441:1441:1441) (1487:1487:1487)) + (PORT datab (1568:1568:1568) (1657:1657:1657)) + (PORT datac (813:813:813) (833:833:833)) + (PORT datad (1236:1236:1236) (1341:1341:1341)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~4) + (DELAY + (ABSOLUTE + (PORT dataa (660:660:660) (720:720:720)) + (PORT datab (709:709:709) (763:763:763)) + (PORT datac (918:918:918) (970:970:970)) + (PORT datad (615:615:615) (633:633:633)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~47) + (DELAY + (ABSOLUTE + (PORT dataa (2318:2318:2318) (2418:2418:2418)) + (PORT datab (927:927:927) (955:955:955)) + (PORT datac (1554:1554:1554) (1653:1653:1653)) + (PORT datad (1922:1922:1922) (2011:2011:2011)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~34) + (DELAY + (ABSOLUTE + (PORT dataa (935:935:935) (1007:1007:1007)) + (PORT datab (687:687:687) (763:763:763)) + (PORT datac (559:559:559) (571:571:571)) + (PORT datad (1644:1644:1644) (1710:1710:1710)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~35) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (257:257:257)) + (PORT datab (336:336:336) (369:369:369)) + (PORT datac (1234:1234:1234) (1291:1291:1291)) + (PORT datad (907:907:907) (963:963:963)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~36) + (DELAY + (ABSOLUTE + (PORT dataa (1090:1090:1090) (1119:1119:1119)) + (PORT datab (856:856:856) (861:861:861)) + (PORT datac (579:579:579) (597:597:597)) + (PORT datad (545:545:545) (551:551:551)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~28) + (DELAY + (ABSOLUTE + (PORT dataa (707:707:707) (756:756:756)) + (PORT datab (958:958:958) (1003:1003:1003)) + (PORT datac (1167:1167:1167) (1223:1223:1223)) + (PORT datad (1125:1125:1125) (1182:1182:1182)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~44) + (DELAY + (ABSOLUTE + (PORT dataa (667:667:667) (723:723:723)) + (PORT datab (1687:1687:1687) (1768:1768:1768)) + (PORT datac (1403:1403:1403) (1556:1556:1556)) + (PORT datad (615:615:615) (639:639:639)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~29) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datac (858:858:858) (882:882:882)) + (PORT datad (180:180:180) (209:209:209)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~16) + (DELAY + (ABSOLUTE + (PORT datac (1464:1464:1464) (1592:1592:1592)) + (PORT datad (1080:1080:1080) (1115:1115:1115)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~27) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (265:265:265)) + (PORT datab (1591:1591:1591) (1599:1599:1599)) + (PORT datac (193:193:193) (226:226:226)) + (PORT datad (332:332:332) (350:350:350)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~10) + (DELAY + (ABSOLUTE + (PORT dataa (216:216:216) (267:267:267)) + (PORT datab (207:207:207) (249:249:249)) + (PORT datac (1058:1058:1058) (1075:1075:1075)) + (PORT datad (654:654:654) (671:671:671)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~31) + (DELAY + (ABSOLUTE + (PORT dataa (1966:1966:1966) (2113:2113:2113)) + (PORT datab (2242:2242:2242) (2358:2358:2358)) + (PORT datac (389:389:389) (423:423:423)) + (PORT datad (647:647:647) (684:684:684)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~30) + (DELAY + (ABSOLUTE + (PORT dataa (1262:1262:1262) (1336:1336:1336)) + (PORT datab (1328:1328:1328) (1392:1392:1392)) + (PORT datac (871:871:871) (913:913:913)) + (PORT datad (625:625:625) (662:662:662)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~32) + (DELAY + (ABSOLUTE + (PORT dataa (2546:2546:2546) (2637:2637:2637)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (2208:2208:2208) (2324:2324:2324)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~33) + (DELAY + (ABSOLUTE + (PORT dataa (1028:1028:1028) (1062:1062:1062)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (761:761:761) (761:761:761)) + (PORT datad (798:798:798) (800:800:800)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~21) + (DELAY + (ABSOLUTE + (PORT dataa (984:984:984) (1054:1054:1054)) + (PORT datab (1816:1816:1816) (1894:1894:1894)) + (PORT datac (945:945:945) (997:997:997)) + (PORT datad (1463:1463:1463) (1516:1516:1516)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~45) + (DELAY + (ABSOLUTE + (PORT dataa (2585:2585:2585) (2658:2658:2658)) + (PORT datab (1534:1534:1534) (1667:1667:1667)) + (PORT datac (171:171:171) (205:205:205)) + (PORT datad (937:937:937) (1001:1001:1001)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~22) + (DELAY + (ABSOLUTE + (PORT dataa (341:341:341) (379:379:379)) + (PORT datab (1818:1818:1818) (1898:1898:1898)) + (PORT datac (957:957:957) (990:990:990)) + (PORT datad (951:951:951) (1002:1002:1002)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~23) + (DELAY + (ABSOLUTE + (PORT dataa (993:993:993) (1031:1031:1031)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (1779:1779:1779) (1862:1862:1862)) + (PORT datad (1426:1426:1426) (1463:1463:1463)) + (IOPATH dataa combout (341:341:341) (328:328:328)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~24) + (DELAY + (ABSOLUTE + (PORT dataa (1125:1125:1125) (1172:1172:1172)) + (PORT datab (1820:1820:1820) (1897:1897:1897)) + (PORT datac (1404:1404:1404) (1423:1423:1423)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (341:341:341) (328:328:328)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~25) + (DELAY + (ABSOLUTE + (PORT dataa (1454:1454:1454) (1506:1506:1506)) + (PORT datab (1731:1731:1731) (1771:1771:1771)) + (PORT datac (1092:1092:1092) (1132:1132:1132)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~26) + (DELAY + (ABSOLUTE + (PORT dataa (220:220:220) (262:262:262)) + (PORT datab (939:939:939) (993:993:993)) + (PORT datac (810:810:810) (823:823:823)) + (PORT datad (194:194:194) (218:218:218)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~43) + (DELAY + (ABSOLUTE + (PORT dataa (567:567:567) (584:584:584)) + (PORT datab (586:586:586) (594:594:594)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_low) + (DELAY + (ABSOLUTE + (PORT dataa (997:997:997) (1038:1038:1038)) + (PORT datab (1942:1942:1942) (1998:1998:1998)) + (PORT datac (2183:2183:2183) (2258:2258:2258)) + (PORT datad (1441:1441:1441) (1528:1528:1528)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1288:1288:1288) (1355:1355:1355)) + (PORT datab (923:923:923) (1007:1007:1007)) + (PORT datac (1130:1130:1130) (1176:1176:1176)) + (PORT datad (829:829:829) (892:892:892)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero) + (DELAY + (ABSOLUTE + (PORT dataa (610:610:610) (630:630:630)) + (PORT datab (1839:1839:1839) (1888:1888:1888)) + (PORT datac (1621:1621:1621) (1720:1720:1720)) + (PORT datad (523:523:523) (534:534:534)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~13) + (DELAY + (ABSOLUTE + (PORT dataa (660:660:660) (716:716:716)) + (PORT datab (610:610:610) (628:628:628)) + (PORT datac (1954:1954:1954) (2059:2059:2059)) + (PORT datad (602:602:602) (628:628:628)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1609:1609:1609) (1660:1660:1660)) + (PORT datab (568:568:568) (602:602:602)) + (PORT datac (1888:1888:1888) (1990:1990:1990)) + (PORT datad (1814:1814:1814) (1949:1949:1949)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1335:1335:1335) (1393:1393:1393)) + (PORT datab (198:198:198) (236:236:236)) + (PORT datac (2026:2026:2026) (2181:2181:2181)) + (PORT datad (1017:1017:1017) (1044:1044:1044)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~3) + (DELAY + (ABSOLUTE + (PORT dataa (991:991:991) (1029:1029:1029)) + (PORT datab (1738:1738:1738) (1788:1788:1788)) + (PORT datac (1776:1776:1776) (1858:1858:1858)) + (PORT datad (938:938:938) (1001:1001:1001)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~4) + (DELAY + (ABSOLUTE + (PORT dataa (980:980:980) (1048:1048:1048)) + (PORT datab (990:990:990) (1042:1042:1042)) + (PORT datac (959:959:959) (988:988:988)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4) + (DELAY + (ABSOLUTE + (PORT dataa (1964:1964:1964) (2059:2059:2059)) + (PORT datab (1220:1220:1220) (1270:1270:1270)) + (PORT datad (1572:1572:1572) (1663:1663:1663)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1808:1808:1808) (1896:1896:1896)) + (PORT datab (1137:1137:1137) (1167:1167:1167)) + (PORT datac (906:906:906) (944:944:944)) + (PORT datad (1460:1460:1460) (1513:1513:1513)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~10) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (380:380:380)) + (PORT datab (221:221:221) (260:260:260)) + (PORT datac (186:186:186) (224:224:224)) + (PORT datad (644:644:644) (661:661:661)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~11) + (DELAY + (ABSOLUTE + (PORT dataa (689:689:689) (756:756:756)) + (PORT datab (1818:1818:1818) (1889:1889:1889)) + (PORT datac (623:623:623) (637:637:637)) + (PORT datad (816:816:816) (822:822:822)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1106:1106:1106) (1160:1160:1160)) + (PORT datab (1783:1783:1783) (1844:1844:1844)) + (PORT datac (1595:1595:1595) (1729:1729:1729)) + (PORT datad (579:579:579) (594:594:594)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~15) + (DELAY + (ABSOLUTE + (PORT dataa (561:561:561) (583:583:583)) + (PORT datab (199:199:199) (239:239:239)) + (PORT datac (511:511:511) (521:521:521)) + (PORT datad (798:798:798) (800:800:800)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[3\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (950:950:950) (979:979:979)) + (PORT datab (854:854:854) (879:879:879)) + (PORT datac (876:876:876) (880:880:880)) + (PORT datad (624:624:624) (643:643:643)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[3\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (713:713:713) (757:757:757)) + (PORT datab (888:888:888) (902:902:902)) + (PORT datac (887:887:887) (909:909:909)) + (PORT datad (172:172:172) (196:196:196)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|ena) + (DELAY + (ABSOLUTE + (PORT dataa (948:948:948) (978:978:978)) + (PORT datac (897:897:897) (919:919:919)) + (PORT datad (848:848:848) (860:860:860)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[3\]) + (INSTANCE z80_\|alu_\|op1_low\[3\]) (DELAY (ABSOLUTE - (PORT clk (1535:1535:1535) (1554:1554:1554)) + (PORT clk (1547:1547:1547) (1549:1549:1549)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1461:1461:1461) (1468:1468:1468)) + (PORT ena (794:794:794) (792:792:792)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -16241,32 +8324,2585 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~31) + (INSTANCE z80_\|alu_\|db_low\[3\]\~15) (DELAY (ABSOLUTE - (PORT dataa (1782:1782:1782) (1906:1906:1906)) - (PORT datab (973:973:973) (1022:1022:1022)) - (PORT datac (1471:1471:1471) (1489:1489:1489)) - (PORT datad (1978:1978:1978) (2013:2013:2013)) + (PORT dataa (654:654:654) (683:683:683)) + (PORT datab (706:706:706) (724:724:724)) + (PORT datac (670:670:670) (744:744:744)) + (PORT datad (429:429:429) (500:500:500)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[3\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (275:275:275) (330:330:330)) + (PORT datac (1117:1117:1117) (1123:1123:1123)) + (PORT datad (344:344:344) (366:366:366)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~33) + (DELAY + (ABSOLUTE + (PORT dataa (903:903:903) (937:937:937)) + (PORT datab (1708:1708:1708) (1760:1760:1760)) + (PORT datac (862:862:862) (894:894:894)) + (PORT datad (899:899:899) (996:996:996)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~34) + (DELAY + (ABSOLUTE + (PORT dataa (607:607:607) (641:641:641)) + (PORT datab (1113:1113:1113) (1182:1182:1182)) + (PORT datac (609:609:609) (635:635:635)) + (PORT datad (900:900:900) (929:929:929)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~48) + (DELAY + (ABSOLUTE + (PORT dataa (1612:1612:1612) (1708:1708:1708)) + (PORT datab (1588:1588:1588) (1686:1686:1686)) + (PORT datac (2100:2100:2100) (2212:2212:2212)) + (PORT datad (1125:1125:1125) (1128:1128:1128)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~35) + (DELAY + (ABSOLUTE + (PORT dataa (866:866:866) (923:923:923)) + (PORT datab (1589:1589:1589) (1736:1736:1736)) + (PORT datac (826:826:826) (871:871:871)) + (PORT datad (1185:1185:1185) (1202:1202:1202)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~36) + (DELAY + (ABSOLUTE + (PORT dataa (624:624:624) (656:656:656)) + (PORT datab (841:841:841) (859:859:859)) + (PORT datac (622:622:622) (633:633:633)) + (PORT datad (173:173:173) (197:197:197)) (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~37) + (DELAY + (ABSOLUTE + (PORT dataa (223:223:223) (278:278:278)) + (PORT datab (646:646:646) (670:670:670)) + (PORT datac (586:586:586) (604:604:604)) + (PORT datad (590:590:590) (608:608:608)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla26M1T4_3) + (DELAY + (ABSOLUTE + (PORT dataa (1614:1614:1614) (1710:1710:1710)) + (PORT datab (1669:1669:1669) (1707:1707:1707)) + (PORT datad (1923:1923:1923) (2012:2012:2012)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~38) + (DELAY + (ABSOLUTE + (PORT dataa (1018:1018:1018) (1094:1094:1094)) + (PORT datab (2048:2048:2048) (2131:2131:2131)) + (PORT datac (1072:1072:1072) (1128:1128:1128)) + (PORT datad (1108:1108:1108) (1172:1172:1172)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~39) + (DELAY + (ABSOLUTE + (PORT dataa (1409:1409:1409) (1467:1467:1467)) + (PORT datab (2028:2028:2028) (2091:2091:2091)) + (PORT datac (1605:1605:1605) (1677:1677:1677)) + (PORT datad (1248:1248:1248) (1299:1299:1299)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~40) + (DELAY + (ABSOLUTE + (PORT dataa (417:417:417) (442:442:442)) + (PORT datab (813:813:813) (847:847:847)) + (PORT datac (201:201:201) (237:237:237)) + (PORT datad (839:839:839) (889:889:889)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~41) + (DELAY + (ABSOLUTE + (PORT dataa (1902:1902:1902) (1975:1975:1975)) + (PORT datab (854:854:854) (902:902:902)) + (PORT datac (2419:2419:2419) (2508:2508:2508)) + (PORT datad (891:891:891) (939:939:939)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low) + (DELAY + (ABSOLUTE + (PORT dataa (987:987:987) (1065:1065:1065)) + (PORT datab (236:236:236) (281:281:281)) + (PORT datac (1684:1684:1684) (1767:1767:1767)) + (PORT datad (826:826:826) (855:855:855)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|result_lo\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT asdata (946:946:946) (976:976:976)) + (PORT ena (1975:1975:1975) (1964:1964:1964)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~5) + (DELAY + (ABSOLUTE + (PORT dataa (876:876:876) (951:951:951)) + (PORT datab (244:244:244) (288:288:288)) + (PORT datac (1192:1192:1192) (1241:1241:1241)) + (PORT datad (1027:1027:1027) (1107:1107:1107)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~6) + (DELAY + (ABSOLUTE + (PORT dataa (862:862:862) (914:914:914)) + (PORT datab (654:654:654) (683:683:683)) + (PORT datac (808:808:808) (801:801:801)) + (PORT datad (623:623:623) (663:663:663)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1228:1228:1228) (1256:1256:1256)) + (PORT datab (642:642:642) (714:714:714)) + (PORT datac (1093:1093:1093) (1122:1122:1122)) + (PORT datad (629:629:629) (643:643:643)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1340:1340:1340) (1376:1376:1376)) + (PORT datab (1193:1193:1193) (1245:1245:1245)) + (PORT datac (1641:1641:1641) (1744:1744:1744)) + (PORT datad (1899:1899:1899) (2002:2002:2002)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~10) + (DELAY + (ABSOLUTE + (PORT dataa (205:205:205) (251:251:251)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (1045:1045:1045) (1117:1117:1117)) + (PORT datad (194:194:194) (220:220:220)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~2) + (DELAY + (ABSOLUTE + (PORT dataa (847:847:847) (874:874:874)) + (PORT datab (892:892:892) (926:926:926)) + (PORT datac (707:707:707) (777:777:777)) + (PORT datad (901:901:901) (992:992:992)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel_pla66npla53M1T1_15) + (DELAY + (ABSOLUTE + (PORT dataa (1898:1898:1898) (1930:1930:1930)) + (PORT datab (1085:1085:1085) (1159:1159:1159)) + (PORT datac (1435:1435:1435) (1548:1548:1548)) + (PORT datad (1477:1477:1477) (1541:1541:1541)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (693:693:693) (754:754:754)) + (PORT datab (893:893:893) (934:934:934)) + (PORT datac (1262:1262:1262) (1296:1296:1296)) + (PORT datad (1388:1388:1388) (1477:1477:1477)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~8) + (DELAY + (ABSOLUTE + (PORT dataa (984:984:984) (1012:1012:1012)) + (PORT datab (923:923:923) (944:944:944)) + (PORT datac (888:888:888) (916:916:916)) + (PORT datad (1082:1082:1082) (1090:1090:1090)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1924:1924:1924) (2037:2037:2037)) + (PORT datab (1344:1344:1344) (1350:1350:1350)) + (PORT datac (875:875:875) (906:906:906)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~7) + (DELAY + (ABSOLUTE + (PORT dataa (816:816:816) (850:850:850)) + (PORT datab (590:590:590) (599:599:599)) + (PORT datac (1182:1182:1182) (1215:1215:1215)) + (PORT datad (594:594:594) (645:645:645)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1740:1740:1740) (1786:1786:1786)) + (PORT datab (413:413:413) (437:437:437)) + (PORT datac (591:591:591) (622:622:622)) + (PORT datad (1148:1148:1148) (1183:1183:1183)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (566:566:566) (604:604:604)) + (PORT datab (1165:1165:1165) (1178:1178:1178)) + (PORT datac (1574:1574:1574) (1621:1621:1621)) + (PORT datad (582:582:582) (583:583:583)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~8) + (DELAY + (ABSOLUTE + (PORT dataa (941:941:941) (972:972:972)) + (PORT datab (1052:1052:1052) (1122:1122:1122)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (824:824:824) (862:862:862)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~16) + (DELAY + (ABSOLUTE + (PORT dataa (661:661:661) (718:718:718)) + (PORT datab (219:219:219) (258:258:258)) + (PORT datac (568:568:568) (582:582:582)) + (PORT datad (853:853:853) (910:910:910)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1101:1101:1101) (1146:1146:1146)) + (PORT datab (572:572:572) (587:587:587)) + (PORT datac (1520:1520:1520) (1523:1523:1523)) + (PORT datad (836:836:836) (851:851:851)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~48) + (DELAY + (ABSOLUTE + (PORT dataa (1193:1193:1193) (1258:1258:1258)) + (PORT datab (1853:1853:1853) (1991:1991:1991)) + (PORT datac (565:565:565) (572:572:572)) + (PORT datad (1722:1722:1722) (1801:1801:1801)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1424:1424:1424) (1504:1504:1504)) + (PORT datab (976:976:976) (1040:1040:1040)) + (PORT datac (1110:1110:1110) (1148:1148:1148)) + (PORT datad (954:954:954) (1028:1028:1028)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~5) + (DELAY + (ABSOLUTE + (PORT dataa (630:630:630) (676:676:676)) + (PORT datab (692:692:692) (757:757:757)) + (PORT datac (638:638:638) (671:671:671)) + (PORT datad (649:649:649) (681:681:681)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~2) + (DELAY + (ABSOLUTE + (PORT dataa (2623:2623:2623) (2703:2703:2703)) + (PORT datab (912:912:912) (940:940:940)) + (PORT datac (1619:1619:1619) (1751:1751:1751)) + (PORT datad (1171:1171:1171) (1196:1196:1196)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~0) + (DELAY + (ABSOLUTE + (PORT dataa (951:951:951) (1017:1017:1017)) + (PORT datab (1649:1649:1649) (1785:1785:1785)) + (PORT datac (934:934:934) (1010:1010:1010)) + (PORT datad (1238:1238:1238) (1290:1290:1290)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1056:1056:1056) (1070:1070:1070)) + (PORT datab (665:665:665) (703:703:703)) + (PORT datac (194:194:194) (228:228:228)) + (PORT datad (181:181:181) (208:208:208)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (1322:1322:1322) (1436:1436:1436)) + (PORT datab (359:359:359) (391:391:391)) + (PORT datac (1243:1243:1243) (1275:1275:1275)) + (PORT datad (1324:1324:1324) (1428:1428:1428)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~33) + (DELAY + (ABSOLUTE + (PORT dataa (1134:1134:1134) (1183:1183:1183)) + (PORT datab (1731:1731:1731) (1830:1830:1830)) + (PORT datac (1336:1336:1336) (1440:1440:1440)) + (PORT datad (1344:1344:1344) (1422:1422:1422)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (1571:1571:1571) (1698:1698:1698)) + (PORT datab (1203:1203:1203) (1284:1284:1284)) + (PORT datac (1579:1579:1579) (1681:1681:1681)) + (PORT datad (181:181:181) (210:210:210)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~6) + (DELAY + (ABSOLUTE + (PORT dataa (964:964:964) (989:989:989)) + (PORT datab (909:909:909) (981:981:981)) + (PORT datac (1063:1063:1063) (1077:1077:1077)) + (PORT datad (189:189:189) (222:222:222)) + (IOPATH dataa combout (303:303:303) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~6) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (907:907:907) (935:935:935)) + (PORT datac (1323:1323:1323) (1342:1342:1342)) + (PORT datad (312:312:312) (332:332:332)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~7) + (DELAY + (ABSOLUTE + (PORT dataa (681:681:681) (738:738:738)) + (PORT datab (663:663:663) (725:725:725)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (195:195:195) (221:221:221)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~2) + (DELAY + (ABSOLUTE + (PORT dataa (628:628:628) (670:670:670)) + (PORT datab (1712:1712:1712) (1788:1788:1788)) + (PORT datac (937:937:937) (1023:1023:1023)) + (PORT datad (2493:2493:2493) (2650:2650:2650)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1217:1217:1217) (1262:1262:1262)) + (PORT datab (1353:1353:1353) (1438:1438:1438)) + (PORT datac (1518:1518:1518) (1594:1594:1594)) + (PORT datad (1975:1975:1975) (2069:2069:2069)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1683:1683:1683) (1795:1795:1795)) + (PORT datab (736:736:736) (782:782:782)) + (PORT datac (564:564:564) (587:587:587)) + (PORT datad (874:874:874) (900:900:900)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla27npla34M1T1_3) + (DELAY + (ABSOLUTE + (PORT dataa (751:751:751) (826:826:826)) + (PORT datab (1797:1797:1797) (1874:1874:1874)) + (PORT datac (2203:2203:2203) (2280:2280:2280)) + (PORT datad (694:694:694) (787:787:787)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~8) + (DELAY + (ABSOLUTE + (PORT dataa (876:876:876) (910:910:910)) + (PORT datab (196:196:196) (235:235:235)) + (PORT datac (1090:1090:1090) (1140:1140:1140)) + (PORT datad (179:179:179) (207:207:207)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~7) + (DELAY + (ABSOLUTE + (PORT dataa (665:665:665) (710:710:710)) + (PORT datab (602:602:602) (620:620:620)) + (PORT datac (1445:1445:1445) (1492:1492:1492)) + (PORT datad (836:836:836) (873:873:873)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~5) + (DELAY + (ABSOLUTE + (PORT dataa (988:988:988) (1050:1050:1050)) + (PORT datab (907:907:907) (974:974:974)) + (PORT datac (927:927:927) (971:971:971)) + (PORT datad (1125:1125:1125) (1181:1181:1181)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~19) + (DELAY + (ABSOLUTE + (PORT dataa (877:877:877) (918:918:918)) + (PORT datab (934:934:934) (991:991:991)) + (PORT datac (936:936:936) (999:999:999)) + (PORT datad (898:898:898) (915:915:915)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~18) + (DELAY + (ABSOLUTE + (PORT dataa (994:994:994) (1044:1044:1044)) + (PORT datab (688:688:688) (747:747:747)) + (PORT datac (1103:1103:1103) (1124:1124:1124)) + (PORT datad (656:656:656) (710:710:710)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~2) + (DELAY + (ABSOLUTE + (PORT dataa (396:396:396) (426:426:426)) + (PORT datab (218:218:218) (256:256:256)) + (PORT datac (213:213:213) (246:246:246)) + (PORT datad (1704:1704:1704) (1718:1718:1718)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal24\~1) + (DELAY + (ABSOLUTE + (PORT dataa (2523:2523:2523) (2690:2690:2690)) + (PORT datab (967:967:967) (1050:1050:1050)) + (PORT datac (1680:1680:1680) (1751:1751:1751)) + (PORT datad (908:908:908) (966:966:966)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~3) + (DELAY + (ABSOLUTE + (PORT dataa (901:901:901) (976:976:976)) + (PORT datab (1429:1429:1429) (1485:1485:1485)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (626:626:626) (675:675:675)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1188:1188:1188) (1243:1243:1243)) + (PORT datab (1357:1357:1357) (1444:1444:1444)) + (PORT datac (1250:1250:1250) (1340:1340:1340)) + (PORT datad (979:979:979) (1021:1021:1021)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~20) + (DELAY + (ABSOLUTE + (PORT dataa (618:618:618) (633:633:633)) + (PORT datab (597:597:597) (620:620:620)) + (PORT datac (974:974:974) (1034:1034:1034)) + (PORT datad (940:940:940) (987:987:987)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~5) + (DELAY + (ABSOLUTE + (PORT dataa (726:726:726) (763:763:763)) + (PORT datab (864:864:864) (922:922:922)) + (PORT datac (605:605:605) (625:625:625)) + (PORT datad (1117:1117:1117) (1166:1166:1166)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~22) + (DELAY + (ABSOLUTE + (PORT dataa (945:945:945) (999:999:999)) + (PORT datab (1189:1189:1189) (1233:1233:1233)) + (PORT datac (835:835:835) (854:854:854)) + (PORT datad (584:584:584) (629:629:629)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla42M3T3_6) + (DELAY + (ABSOLUTE + (PORT dataa (1179:1179:1179) (1244:1244:1244)) + (PORT datab (1085:1085:1085) (1155:1155:1155)) + (PORT datac (634:634:634) (659:659:659)) + (PORT datad (1671:1671:1671) (1806:1806:1806)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~6) + (DELAY + (ABSOLUTE + (PORT dataa (869:869:869) (901:901:901)) + (PORT datab (943:943:943) (965:965:965)) + (PORT datac (2100:2100:2100) (2201:2201:2201)) + (PORT datad (875:875:875) (929:929:929)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1922:1922:1922) (2033:2033:2033)) + (PORT datad (1201:1201:1201) (1281:1281:1281)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~30) + (DELAY + (ABSOLUTE + (PORT dataa (636:636:636) (660:660:660)) + (PORT datab (719:719:719) (753:753:753)) + (PORT datac (1032:1032:1032) (1114:1114:1114)) + (PORT datad (840:840:840) (883:883:883)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~23) + (DELAY + (ABSOLUTE + (PORT dataa (636:636:636) (654:654:654)) + (PORT datab (1280:1280:1280) (1351:1351:1351)) + (PORT datac (1031:1031:1031) (1113:1113:1113)) + (PORT datad (840:840:840) (882:882:882)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1381:1381:1381) (1435:1435:1435)) + (PORT datab (219:219:219) (258:258:258)) + (PORT datac (589:589:589) (623:623:623)) + (PORT datad (868:868:868) (903:903:903)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~3) + (DELAY + (ABSOLUTE + (PORT dataa (2277:2277:2277) (2380:2380:2380)) + (PORT datab (1135:1135:1135) (1157:1157:1157)) + (PORT datac (955:955:955) (999:999:999)) + (PORT datad (654:654:654) (706:706:706)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~10) + (DELAY + (ABSOLUTE + (PORT dataa (848:848:848) (859:859:859)) + (PORT datab (800:800:800) (804:804:804)) + (PORT datad (1152:1152:1152) (1151:1151:1151)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~18) + (DELAY + (ABSOLUTE + (PORT dataa (881:881:881) (914:914:914)) + (PORT datab (1241:1241:1241) (1283:1283:1283)) + (PORT datac (1219:1219:1219) (1260:1260:1260)) + (PORT datad (1131:1131:1131) (1133:1133:1133)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_pc\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1171:1171:1171) (1204:1204:1204)) + (PORT datab (883:883:883) (956:956:956)) + (PORT datac (1863:1863:1863) (1953:1953:1953)) + (PORT datad (667:667:667) (715:715:715)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_pc\~1) + (DELAY + (ABSOLUTE + (PORT dataa (900:900:900) (975:975:975)) + (PORT datab (243:243:243) (289:289:289)) + (PORT datac (214:214:214) (247:247:247)) + (PORT datad (931:931:931) (953:953:953)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_pc\~2) + (DELAY + (ABSOLUTE + (PORT dataa (668:668:668) (708:708:708)) + (PORT datab (244:244:244) (292:292:292)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (1703:1703:1703) (1718:1718:1718)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~19) + (DELAY + (ABSOLUTE + (PORT dataa (922:922:922) (965:965:965)) + (PORT datab (686:686:686) (707:707:707)) + (PORT datac (1217:1217:1217) (1260:1260:1260)) + (PORT datad (672:672:672) (725:725:725)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~20) + (DELAY + (ABSOLUTE + (PORT dataa (606:606:606) (633:633:633)) + (PORT datab (220:220:220) (258:258:258)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~21) + (DELAY + (ABSOLUTE + (PORT dataa (914:914:914) (973:973:973)) + (PORT datab (843:843:843) (926:926:926)) + (PORT datac (201:201:201) (237:237:237)) + (PORT datad (630:630:630) (676:676:676)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~9) + (DELAY + (ABSOLUTE + (PORT dataa (644:644:644) (695:695:695)) + (PORT datab (641:641:641) (683:683:683)) + (PORT datac (1183:1183:1183) (1242:1242:1242)) + (PORT datad (610:610:610) (646:646:646)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1726:1726:1726) (1799:1799:1799)) + (PORT datab (309:309:309) (407:407:407)) + (PORT datac (847:847:847) (860:860:860)) + (PORT datad (585:585:585) (601:601:601)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_1d\~8) + (DELAY + (ABSOLUTE + (PORT dataa (2003:2003:2003) (2195:2195:2195)) + (PORT datab (1221:1221:1221) (1318:1318:1318)) + (PORT datac (680:680:680) (711:711:711)) + (PORT datad (1269:1269:1269) (1352:1352:1352)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~10) + (DELAY + (ABSOLUTE + (PORT dataa (654:654:654) (703:703:703)) + (PORT datab (1127:1127:1127) (1205:1205:1205)) + (PORT datac (905:905:905) (942:942:942)) + (PORT datad (1157:1157:1157) (1213:1213:1213)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~11) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (1223:1223:1223) (1239:1239:1239)) + (PORT datac (713:713:713) (793:793:793)) + (PORT datad (171:171:171) (196:196:196)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1188:1188:1188) (1235:1235:1235)) + (PORT datab (962:962:962) (1003:1003:1003)) + (PORT datac (601:601:601) (615:615:615)) + (PORT datad (855:855:855) (895:895:895)) + (IOPATH dataa combout (303:303:303) (299:299:299)) (IOPATH datab combout (304:304:304) (308:308:308)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~13) + (DELAY + (ABSOLUTE + (PORT dataa (894:894:894) (932:932:932)) + (PORT datab (200:200:200) (240:240:240)) + (PORT datac (822:822:822) (843:843:843)) + (PORT datad (834:834:834) (852:852:852)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[7\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (644:644:644) (670:670:670)) + (PORT datac (587:587:587) (602:602:602)) + (PORT datad (699:699:699) (727:727:727)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|SYNTHESIZED_WIRE_2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (631:631:631) (702:702:702)) + (PORT datab (1106:1106:1106) (1116:1116:1116)) + (PORT datac (315:315:315) (342:342:342)) + (PORT datad (1985:1985:1985) (2137:2137:2137)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla89M1T2_3) + (DELAY + (ABSOLUTE + (PORT dataa (1830:1830:1830) (1937:1937:1937)) + (PORT datab (937:937:937) (1014:1014:1014)) + (PORT datac (891:891:891) (955:955:955)) + (PORT datad (1116:1116:1116) (1171:1171:1171)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~32) + (DELAY + (ABSOLUTE + (PORT dataa (674:674:674) (722:722:722)) + (PORT datab (950:950:950) (998:998:998)) + (PORT datac (1223:1223:1223) (1290:1290:1290)) + (PORT datad (2080:2080:2080) (2164:2164:2164)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~2) + (DELAY + (ABSOLUTE + (PORT dataa (921:921:921) (987:987:987)) + (PORT datab (1589:1589:1589) (1689:1689:1689)) + (PORT datac (1933:1933:1933) (2076:2076:2076)) + (PORT datad (637:637:637) (680:680:680)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~22) + (DELAY + (ABSOLUTE + (PORT dataa (1966:1966:1966) (2055:2055:2055)) + (PORT datab (960:960:960) (1020:1020:1020)) + (PORT datac (2103:2103:2103) (2213:2213:2213)) + (PORT datad (1127:1127:1127) (1179:1179:1179)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~3) + (DELAY + (ABSOLUTE + (PORT dataa (659:659:659) (707:707:707)) + (PORT datab (200:200:200) (239:239:239)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~4) + (DELAY + (ABSOLUTE + (PORT dataa (606:606:606) (634:634:634)) + (PORT datab (634:634:634) (651:651:651)) + (PORT datac (852:852:852) (861:861:861)) + (PORT datad (619:619:619) (671:671:671)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~5) + (DELAY + (ABSOLUTE + (PORT dataa (602:602:602) (639:639:639)) + (PORT datab (1150:1150:1150) (1196:1196:1196)) + (PORT datac (217:217:217) (261:261:261)) + (PORT datad (617:617:617) (626:626:626)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1256:1256:1256) (1357:1357:1357)) + (PORT datab (1414:1414:1414) (1475:1475:1475)) + (PORT datac (637:637:637) (694:694:694)) + (PORT datad (1773:1773:1773) (1906:1906:1906)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~13) + (DELAY + (ABSOLUTE + (PORT dataa (654:654:654) (684:684:684)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (218:218:218) (262:262:262)) + (PORT datad (196:196:196) (221:221:221)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1005:1005:1005) (1135:1135:1135)) + (PORT datab (227:227:227) (270:270:270)) + (PORT datac (1120:1120:1120) (1159:1159:1159)) + (PORT datad (611:611:611) (638:638:638)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~6) + (DELAY + (ABSOLUTE + (PORT datab (569:569:569) (591:591:591)) + (PORT datac (322:322:322) (351:351:351)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~7) + (DELAY + (ABSOLUTE + (PORT dataa (375:375:375) (400:400:400)) + (PORT datab (208:208:208) (251:251:251)) + (PORT datac (171:171:171) (205:205:205)) + (PORT datad (574:574:574) (601:601:601)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_nop3pla68M1T3_2) + (DELAY + (ABSOLUTE + (PORT dataa (1692:1692:1692) (1735:1735:1735)) + (PORT datab (1411:1411:1411) (1454:1454:1454)) + (PORT datac (1930:1930:1930) (1994:1994:1994)) + (PORT datad (919:919:919) (992:992:992)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2368:2368:2368) (2429:2429:2429)) + (PORT datab (200:200:200) (239:239:239)) + (PORT datac (894:894:894) (932:932:932)) + (PORT datad (1352:1352:1352) (1390:1390:1390)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~17) + (DELAY + (ABSOLUTE + (PORT dataa (977:977:977) (1073:1073:1073)) + (PORT datab (230:230:230) (271:271:271)) + (PORT datac (1199:1199:1199) (1225:1225:1225)) + (PORT datad (858:858:858) (898:898:898)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1938:1938:1938) (1958:1958:1958)) + (PORT datab (198:198:198) (238:238:238)) + (PORT datac (194:194:194) (227:227:227)) + (PORT datad (1135:1135:1135) (1178:1178:1178)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~2) + (DELAY + (ABSOLUTE + (PORT dataa (840:840:840) (888:888:888)) + (PORT datab (655:655:655) (683:683:683)) + (PORT datac (833:833:833) (838:838:838)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (2369:2369:2369) (2430:2430:2430)) + (PORT datab (1735:1735:1735) (1787:1787:1787)) + (PORT datac (895:895:895) (929:929:929)) + (PORT datad (1351:1351:1351) (1387:1387:1387)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1169:1169:1169) (1230:1230:1230)) + (PORT datab (1101:1101:1101) (1165:1165:1165)) + (PORT datac (2016:2016:2016) (2103:2103:2103)) + (PORT datad (1737:1737:1737) (1808:1808:1808)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal73\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1993:1993:1993) (2185:2185:2185)) + (PORT datab (1209:1209:1209) (1305:1305:1305)) + (PORT datac (967:967:967) (992:992:992)) + (PORT datad (1278:1278:1278) (1365:1365:1365)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal72\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1002:1002:1002) (1133:1133:1133)) + (PORT datab (226:226:226) (266:266:266)) + (PORT datac (1116:1116:1116) (1197:1197:1197)) + (PORT datad (1497:1497:1497) (1581:1581:1581)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~1) + (DELAY + (ABSOLUTE + (PORT dataa (654:654:654) (678:678:678)) + (PORT datab (197:197:197) (237:237:237)) + (PORT datac (1112:1112:1112) (1136:1136:1136)) + (PORT datad (602:602:602) (621:621:621)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (351:351:351) (382:382:382)) + (PORT datab (570:570:570) (590:590:590)) + (PORT datac (321:321:321) (350:350:350)) + (PORT datad (801:801:801) (849:849:849)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (679:679:679) (764:764:764)) + (PORT datab (1518:1518:1518) (1635:1635:1635)) + (PORT datad (982:982:982) (1050:1050:1050)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (928:928:928) (999:999:999)) + (PORT datac (2233:2233:2233) (2307:2307:2307)) + (PORT datad (877:877:877) (925:925:925)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (578:578:578) (612:612:612)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (1452:1452:1452) (1529:1529:1529)) + (PORT datad (577:577:577) (602:602:602)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~8) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (565:565:565) (594:594:594)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~14) + (DELAY + (ABSOLUTE + (PORT datab (1111:1111:1111) (1193:1193:1193)) + (PORT datad (1341:1341:1341) (1439:1439:1439)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~10) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (380:380:380) (414:414:414)) + (PORT datac (1736:1736:1736) (1805:1805:1805)) + (PORT datad (180:180:180) (209:209:209)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal45\~0) + (DELAY + (ABSOLUTE + (PORT dataa (943:943:943) (965:965:965)) + (PORT datab (1161:1161:1161) (1240:1240:1240)) + (PORT datac (1214:1214:1214) (1321:1321:1321)) + (PORT datad (1622:1622:1622) (1713:1713:1713)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1238:1238:1238) (1300:1300:1300)) + (PORT datab (882:882:882) (904:904:904)) + (PORT datac (1153:1153:1153) (1191:1191:1191)) + (PORT datad (1675:1675:1675) (1682:1682:1682)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1253:1253:1253) (1274:1274:1274)) + (PORT datab (960:960:960) (1020:1020:1020)) + (PORT datac (1803:1803:1803) (1899:1899:1899)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1563:1563:1563) (1648:1648:1648)) + (PORT datab (1247:1247:1247) (1330:1330:1330)) + (PORT datac (173:173:173) (206:206:206)) + (PORT datad (990:990:990) (1070:1070:1070)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~8) + (DELAY + (ABSOLUTE + (PORT dataa (886:886:886) (931:931:931)) + (PORT datab (598:598:598) (607:607:607)) + (PORT datac (354:354:354) (377:377:377)) + (PORT datad (1043:1043:1043) (1093:1093:1093)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~9) + (DELAY + (ABSOLUTE + (PORT dataa (654:654:654) (674:674:674)) + (PORT datac (620:620:620) (647:647:647)) + (PORT datad (602:602:602) (621:621:621)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~10) + (DELAY + (ABSOLUTE + (PORT dataa (609:609:609) (630:630:630)) + (PORT datab (652:652:652) (663:663:663)) + (PORT datac (337:337:337) (364:364:364)) + (PORT datad (821:821:821) (826:826:826)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S) + (DELAY + (ABSOLUTE + (PORT dataa (871:871:871) (889:889:889)) + (PORT datab (206:206:206) (248:248:248)) + (PORT datac (381:381:381) (416:416:416)) + (PORT datad (610:610:610) (620:620:620)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[3\]) + (DELAY + (ABSOLUTE + (PORT dataa (714:714:714) (762:762:762)) + (PORT datac (890:890:890) (917:917:917)) + (PORT datad (832:832:832) (845:845:845)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|ena\~0) + (DELAY + (ABSOLUTE + (PORT dataa (949:949:949) (979:979:979)) + (PORT datac (889:889:889) (914:914:914)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_high\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1547:1547:1547) (1549:1549:1549)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op1\[3\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1171:1171:1171) (1243:1243:1243)) + (PORT datab (687:687:687) (716:716:716)) + (PORT datac (407:407:407) (483:483:483)) + (PORT datad (430:430:430) (502:502:502)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|SYNTHESIZED_WIRE_10\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1286:1286:1286) (1369:1369:1369)) + (PORT datac (193:193:193) (226:226:226)) + (PORT datad (203:203:203) (232:232:232)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_we_lo\~2) + (DELAY + (ABSOLUTE + (PORT datab (951:951:951) (991:991:991)) + (PORT datac (1196:1196:1196) (1230:1230:1230)) + (PORT datad (2493:2493:2493) (2650:2650:2650)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_we_lo\~3) + (DELAY + (ABSOLUTE + (PORT dataa (956:956:956) (991:991:991)) + (PORT datab (355:355:355) (385:385:385)) + (PORT datac (1167:1167:1167) (1226:1226:1226)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~14) + (DELAY + (ABSOLUTE + (PORT dataa (869:869:869) (900:900:900)) + (PORT datab (946:946:946) (967:967:967)) + (PORT datac (876:876:876) (883:883:883)) + (PORT datad (925:925:925) (1020:1020:1020)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_hi\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1873:1873:1873) (1898:1898:1898)) + (PORT datab (944:944:944) (963:963:963)) + (PORT datac (2100:2100:2100) (2199:2199:2199)) + (PORT datad (181:181:181) (208:208:208)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal33\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1216:1216:1216) (1312:1312:1312)) + (PORT datab (1851:1851:1851) (1863:1863:1863)) + (PORT datac (921:921:921) (968:968:968)) + (PORT datad (950:950:950) (1030:1030:1030)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~0) + (DELAY + (ABSOLUTE + (PORT dataa (655:655:655) (704:704:704)) + (PORT datab (640:640:640) (661:661:661)) + (PORT datac (1432:1432:1432) (1481:1481:1481)) + (PORT datad (913:913:913) (957:957:957)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (948:948:948) (995:995:995)) + (PORT datab (205:205:205) (245:245:245)) + (PORT datac (2069:2069:2069) (2220:2220:2220)) + (PORT datad (1163:1163:1163) (1227:1227:1227)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (814:814:814) (843:843:843)) + (PORT datab (651:651:651) (693:693:693)) + (PORT datac (1541:1541:1541) (1564:1564:1564)) + (PORT datad (1078:1078:1078) (1112:1112:1112)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~4) + (DELAY + (ABSOLUTE + (PORT dataa (883:883:883) (921:921:921)) + (PORT datab (1052:1052:1052) (1120:1120:1120)) + (PORT datac (652:652:652) (708:708:708)) + (PORT datad (639:639:639) (696:696:696)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_hi) + (DELAY + (ABSOLUTE + (PORT dataa (898:898:898) (916:916:916)) + (PORT datab (885:885:885) (897:897:897)) + (PORT datad (185:185:185) (217:217:217)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (917:917:917) (986:986:986)) + (PORT datab (1287:1287:1287) (1375:1375:1375)) + (PORT datac (1229:1229:1229) (1337:1337:1337)) + (PORT datad (1191:1191:1191) (1247:1247:1247)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1231:1231:1231) (1292:1292:1292)) + (PORT datab (1815:1815:1815) (1890:1890:1890)) + (PORT datac (853:853:853) (898:898:898)) + (PORT datad (1260:1260:1260) (1341:1341:1341)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1364:1364:1364) (1422:1422:1422)) + (PORT datab (1769:1769:1769) (1787:1787:1787)) + (PORT datac (1143:1143:1143) (1192:1192:1192)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~12) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (394:394:394) (428:428:428)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (361:361:361) (392:392:392)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~13) + (DELAY + (ABSOLUTE + (PORT dataa (229:229:229) (278:278:278)) + (PORT datab (1732:1732:1732) (1770:1770:1770)) + (PORT datac (568:568:568) (573:573:573)) + (PORT datad (1511:1511:1511) (1602:1602:1602)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla56M3T3_6) + (DELAY + (ABSOLUTE + (PORT dataa (1180:1180:1180) (1242:1242:1242)) + (PORT datab (669:669:669) (696:696:696)) + (PORT datac (1304:1304:1304) (1370:1370:1370)) + (PORT datad (1674:1674:1674) (1808:1808:1808)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1273:1273:1273) (1322:1322:1322)) + (PORT datab (1235:1235:1235) (1269:1269:1269)) + (PORT datac (591:591:591) (626:626:626)) + (PORT datad (203:203:203) (231:231:231)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~7) + (DELAY + (ABSOLUTE + (PORT dataa (905:905:905) (919:919:919)) + (PORT datab (227:227:227) (267:267:267)) + (PORT datac (2102:2102:2102) (2199:2199:2199)) + (PORT datad (802:802:802) (830:830:830)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1767:1767:1767) (1883:1883:1883)) + (PORT datab (1504:1504:1504) (1590:1590:1590)) + (PORT datac (1111:1111:1111) (1116:1116:1116)) + (PORT datad (187:187:187) (218:218:218)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (1341:1341:1341) (1400:1400:1400)) + (PORT datab (633:633:633) (676:676:676)) + (PORT datac (613:613:613) (649:649:649)) + (PORT datad (1395:1395:1395) (1455:1455:1455)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~8) + (DELAY + (ABSOLUTE + (PORT dataa (899:899:899) (959:959:959)) + (PORT datac (1093:1093:1093) (1116:1116:1116)) + (PORT datad (1195:1195:1195) (1215:1215:1215)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (608:608:608) (670:670:670)) + (PORT datab (665:665:665) (684:684:684)) + (PORT datac (607:607:607) (657:657:657)) + (PORT datad (926:926:926) (953:953:953)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (683:683:683) (741:741:741)) + (PORT datab (371:371:371) (411:411:411)) + (PORT datac (1161:1161:1161) (1224:1224:1224)) + (PORT datad (1144:1144:1144) (1209:1209:1209)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~41) + (DELAY + (ABSOLUTE + (PORT dataa (1153:1153:1153) (1173:1173:1173)) + (PORT datab (1815:1815:1815) (1890:1890:1890)) + (PORT datac (1133:1133:1133) (1169:1169:1169)) + (PORT datad (1259:1259:1259) (1341:1341:1341)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~10) + (DELAY + (ABSOLUTE + (PORT dataa (942:942:942) (998:998:998)) + (PORT datac (881:881:881) (928:928:928)) + (PORT datad (913:913:913) (970:970:970)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\~21) + (DELAY + (ABSOLUTE + (PORT dataa (1624:1624:1624) (1764:1764:1764)) + (PORT datab (917:917:917) (973:973:973)) + (PORT datad (1620:1620:1620) (1708:1708:1708)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~3) + (DELAY + (ABSOLUTE + (PORT dataa (286:286:286) (384:384:384)) + (PORT datab (270:270:270) (355:355:355)) + (PORT datad (245:245:245) (317:317:317)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (832:832:832) (859:859:859)) + (PORT datab (1173:1173:1173) (1194:1194:1194)) + (PORT datac (853:853:853) (852:852:852)) + (PORT datad (195:195:195) (220:220:220)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (251:251:251)) + (PORT datab (654:654:654) (674:674:674)) + (PORT datac (1329:1329:1329) (1368:1368:1368)) + (PORT datad (1055:1055:1055) (1101:1101:1101)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (1471:1471:1471) (1518:1518:1518)) + (PORT datab (951:951:951) (992:992:992)) + (PORT datac (613:613:613) (630:630:630)) + (PORT datad (617:617:617) (654:654:654)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (955:955:955) (1003:1003:1003)) + (PORT datab (1697:1697:1697) (1738:1738:1738)) + (PORT datac (1328:1328:1328) (1367:1367:1367)) + (PORT datad (328:328:328) (353:353:353)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1557:1557:1557) (1655:1655:1655)) + (PORT datac (963:963:963) (1037:1037:1037)) + (PORT datad (906:906:906) (970:970:970)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (1204:1204:1204) (1246:1246:1246)) + (PORT datab (1074:1074:1074) (1106:1106:1106)) + (PORT datac (915:915:915) (939:939:939)) + (PORT datad (216:216:216) (252:252:252)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (406:406:406) (452:452:452)) + (PORT datab (597:597:597) (624:624:624)) + (PORT datad (1125:1125:1125) (1177:1177:1177)) + (IOPATH dataa combout (301:301:301) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (886:886:886) (941:941:941)) + (PORT datab (243:243:243) (290:290:290)) + (PORT datad (847:847:847) (880:880:880)) + (IOPATH dataa combout (301:301:301) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (921:921:921) (958:958:958)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (220:220:220) (263:263:263)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (1539:1539:1539) (1627:1627:1627)) + (PORT datad (570:570:570) (583:583:583)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~30) (DELAY (ABSOLUTE - (PORT dataa (631:631:631) (660:660:660)) - (PORT datab (1249:1249:1249) (1275:1275:1275)) - (PORT datac (1822:1822:1822) (1900:1900:1900)) - (PORT datad (1106:1106:1106) (1134:1134:1134)) - (IOPATH dataa combout (327:327:327) (347:347:347)) + (PORT dataa (895:895:895) (943:943:943)) + (PORT datab (580:580:580) (595:595:595)) + (PORT datac (841:841:841) (867:867:867)) + (PORT datad (497:497:497) (505:505:505)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~13) + (DELAY + (ABSOLUTE + (PORT dataa (2017:2017:2017) (2107:2107:2107)) + (PORT datab (947:947:947) (968:968:968)) + (PORT datac (2102:2102:2102) (2203:2203:2203)) + (PORT datad (202:202:202) (230:230:230)) + (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -16276,11 +10912,11 @@ (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~32) (DELAY (ABSOLUTE - (PORT dataa (640:640:640) (687:687:687)) - (PORT datab (905:905:905) (971:971:971)) - (PORT datac (861:861:861) (888:888:888)) - (PORT datad (171:171:171) (196:196:196)) - (IOPATH dataa combout (371:371:371) (376:376:376)) + (PORT dataa (870:870:870) (898:898:898)) + (PORT datab (815:815:815) (899:899:899)) + (PORT datac (917:917:917) (934:934:934)) + (PORT datad (876:876:876) (927:927:927)) + (IOPATH dataa combout (327:327:327) (347:347:347)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -16292,28 +10928,12 @@ (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~33) (DELAY (ABSOLUTE - (PORT dataa (208:208:208) (256:256:256)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (1153:1153:1153) (1178:1178:1178)) - (PORT datad (204:204:204) (241:241:241)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_hi\~0) - (DELAY - (ABSOLUTE - (PORT dataa (713:713:713) (766:766:766)) - (PORT datab (205:205:205) (245:245:245)) - (PORT datac (346:346:346) (370:370:370)) - (PORT datad (1145:1145:1145) (1176:1176:1176)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (1510:1510:1510) (1595:1595:1595)) + (PORT datab (234:234:234) (278:278:278)) + (PORT datac (1578:1578:1578) (1617:1617:1617)) + (PORT datad (2293:2293:2293) (2360:2360:2360)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -16321,12 +10941,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_hi) + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~34) (DELAY (ABSOLUTE - (PORT datab (922:922:922) (944:944:944)) - (PORT datac (595:595:595) (615:615:615)) - (PORT datad (181:181:181) (212:212:212)) + (PORT dataa (1667:1667:1667) (1727:1727:1727)) + (PORT datab (658:658:658) (688:688:688)) + (PORT datac (1225:1225:1225) (1319:1319:1319)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -16335,12 +10957,28 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_81) + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~35) (DELAY (ABSOLUTE - (PORT dataa (877:877:877) (900:900:900)) - (PORT datac (1144:1144:1144) (1163:1163:1163)) - (PORT datad (832:832:832) (861:861:861)) + (PORT dataa (208:208:208) (255:255:255)) + (PORT datab (651:651:651) (673:673:673)) + (PORT datac (177:177:177) (215:215:215)) + (PORT datad (1154:1154:1154) (1258:1258:1258)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_73) + (DELAY + (ABSOLUTE + (PORT dataa (1040:1040:1040) (1067:1067:1067)) + (PORT datac (1098:1098:1098) (1139:1139:1139)) + (PORT datad (899:899:899) (934:934:934)) (IOPATH dataa combout (304:304:304) (307:307:307)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -16349,12 +10987,86 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[3\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[3\]) (DELAY (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (1506:1506:1506) (1545:1545:1545)) - (PORT ena (1261:1261:1261) (1299:1299:1299)) + (PORT clk (1520:1520:1520) (1533:1533:1533)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1256:1256:1256) (1263:1263:1263)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_ir\~0) + (DELAY + (ABSOLUTE + (PORT datab (1019:1019:1019) (1083:1083:1083)) + (PORT datac (962:962:962) (1040:1040:1040)) + (PORT datad (950:950:950) (1010:1010:1010)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_ir\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1305:1305:1305) (1390:1390:1390)) + (PORT datab (1378:1378:1378) (1422:1422:1422)) + (PORT datac (343:343:343) (366:366:366)) + (PORT datad (812:812:812) (886:886:886)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_60) + (DELAY + (ABSOLUTE + (PORT datab (927:927:927) (977:977:977)) + (PORT datac (1099:1099:1099) (1140:1140:1140)) + (PORT datad (798:798:798) (805:805:805)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_61) + (DELAY + (ABSOLUTE + (PORT datab (926:926:926) (973:973:973)) + (PORT datac (1100:1100:1100) (1142:1142:1142)) + (PORT datad (798:798:798) (804:804:804)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1533:1533:1533)) + (PORT asdata (537:537:537) (567:567:567)) + (PORT ena (1448:1448:1448) (1437:1437:1437)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -16365,28 +11077,60 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_80) + (INSTANCE z80_\|execute_\|ctl_reg_sys_we_lo\~4) (DELAY (ABSOLUTE - (PORT dataa (874:874:874) (899:899:899)) - (PORT datac (1138:1138:1138) (1159:1159:1159)) - (PORT datad (835:835:835) (861:861:861)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT datab (1167:1167:1167) (1178:1178:1178)) + (PORT datac (1620:1620:1620) (1701:1701:1701)) + (PORT datad (922:922:922) (986:986:986)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~45) + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo) (DELAY (ABSOLUTE - (PORT dataa (1100:1100:1100) (1149:1149:1149)) - (PORT datab (1280:1280:1280) (1386:1386:1386)) - (PORT datad (842:842:842) (869:869:869)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT dataa (621:621:621) (685:685:685)) + (PORT datab (199:199:199) (239:239:239)) + (PORT datac (1721:1721:1721) (1776:1776:1776)) + (PORT datad (855:855:855) (858:858:858)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sw_4d_hi\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1106:1106:1106) (1116:1116:1116)) + (PORT datab (930:930:930) (973:973:973)) + (PORT datac (1150:1150:1150) (1188:1188:1188)) + (PORT datad (798:798:798) (803:803:803)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (888:888:888) (915:915:915)) + (PORT datab (675:675:675) (708:708:708)) + (PORT datad (674:674:674) (703:703:703)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -16394,47 +11138,71 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_41\~0) + (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~11) (DELAY (ABSOLUTE - (PORT dataa (638:638:638) (693:693:693)) - (PORT datab (1259:1259:1259) (1346:1346:1346)) - (PORT datac (1146:1146:1146) (1187:1187:1187)) - (PORT datad (374:374:374) (412:412:412)) + (PORT datab (687:687:687) (708:708:708)) + (PORT datac (358:358:358) (423:423:423)) + (PORT datad (317:317:317) (329:329:329)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[11\]) + (DELAY + (ABSOLUTE + (PORT dataa (679:679:679) (697:697:697)) + (PORT datac (582:582:582) (602:602:602)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_apin_mux\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1030:1030:1030) (1119:1119:1119)) + (PORT datab (1518:1518:1518) (1635:1635:1635)) + (PORT datac (1117:1117:1117) (1167:1167:1167)) (IOPATH dataa combout (354:354:354) (349:349:349)) (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~37) + (DELAY + (ABSOLUTE + (PORT dataa (1277:1277:1277) (1377:1377:1377)) + (PORT datab (1354:1354:1354) (1443:1443:1443)) + (PORT datac (1715:1715:1715) (1795:1795:1795)) + (PORT datad (975:975:975) (1020:1020:1020)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (990:990:990) (1035:1035:1035)) - (PORT ena (1193:1193:1193) (1176:1176:1176)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_36\~0) + (INSTANCE z80_\|execute_\|ctl_inc_dec\~2) (DELAY (ABSOLUTE - (PORT dataa (404:404:404) (462:462:462)) - (PORT datab (1258:1258:1258) (1341:1341:1341)) - (PORT datac (1142:1142:1142) (1186:1186:1186)) - (PORT datad (664:664:664) (686:686:686)) + (PORT dataa (1213:1213:1213) (1259:1259:1259)) + (PORT datab (1016:1016:1016) (1060:1060:1060)) + (PORT datac (1158:1158:1158) (1222:1222:1222)) + (PORT datad (194:194:194) (219:219:219)) (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datab combout (336:336:336) (332:332:332)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -16442,13 +11210,77 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_37\~0) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~40) (DELAY (ABSOLUTE - (PORT dataa (639:639:639) (696:696:696)) - (PORT datab (1255:1255:1255) (1339:1339:1339)) - (PORT datac (1141:1141:1141) (1184:1184:1184)) - (PORT datad (375:375:375) (413:413:413)) + (PORT dataa (1746:1746:1746) (1830:1830:1830)) + (PORT datab (1356:1356:1356) (1439:1439:1439)) + (PORT datac (1514:1514:1514) (1589:1589:1589)) + (PORT datad (1458:1458:1458) (1519:1519:1519)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~4) + (DELAY + (ABSOLUTE + (PORT dataa (2047:2047:2047) (2159:2159:2159)) + (PORT datab (219:219:219) (258:258:258)) + (PORT datac (1157:1157:1157) (1221:1221:1221)) + (PORT datad (1817:1817:1817) (1893:1893:1893)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1213:1213:1213) (1263:1263:1263)) + (PORT datab (207:207:207) (250:250:250)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (1456:1456:1456) (1521:1521:1521)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (675:675:675) (747:747:747)) + (PORT datab (1133:1133:1133) (1173:1173:1173)) + (PORT datac (1505:1505:1505) (1624:1624:1624)) + (PORT datad (1434:1434:1434) (1501:1501:1501)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla6M1T4_4) + (DELAY + (ABSOLUTE + (PORT dataa (1306:1306:1306) (1391:1391:1391)) + (PORT datab (966:966:966) (1005:1005:1005)) + (PORT datac (1643:1643:1643) (1693:1693:1693)) + (PORT datad (970:970:970) (1027:1027:1027)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -16457,30 +11289,742 @@ ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[3\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~42) (DELAY (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (989:989:989) (1035:1035:1035)) - (PORT ena (1283:1283:1283) (1283:1283:1283)) + (PORT dataa (1075:1075:1075) (1128:1128:1128)) + (PORT datac (814:814:814) (867:867:867)) + (PORT datad (1664:1664:1664) (1683:1683:1683)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (264:264:264)) + (PORT datab (213:213:213) (257:257:257)) + (PORT datac (783:783:783) (838:838:838)) + (PORT datad (1281:1281:1281) (1350:1350:1350)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_1d\~4) + (DELAY + (ABSOLUTE + (PORT dataa (674:674:674) (713:713:713)) + (PORT datab (689:689:689) (753:753:753)) + (PORT datac (922:922:922) (973:973:973)) + (PORT datad (1125:1125:1125) (1154:1154:1154)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~3) + (DELAY + (ABSOLUTE + (PORT datab (868:868:868) (939:939:939)) + (PORT datac (584:584:584) (610:610:610)) + (PORT datad (603:603:603) (622:622:622)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~9) + (DELAY + (ABSOLUTE + (PORT dataa (834:834:834) (885:885:885)) + (PORT datab (1220:1220:1220) (1298:1298:1298)) + (PORT datac (1748:1748:1748) (1824:1824:1824)) + (PORT datad (1447:1447:1447) (1467:1467:1467)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1781:1781:1781) (1865:1865:1865)) + (PORT datab (196:196:196) (235:235:235)) + (PORT datac (1671:1671:1671) (1712:1712:1712)) + (PORT datad (1446:1446:1446) (1465:1465:1465)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~8) + (DELAY + (ABSOLUTE + (PORT dataa (2024:2024:2024) (2123:2123:2123)) + (PORT datab (1444:1444:1444) (1474:1474:1474)) + (PORT datac (668:668:668) (691:691:691)) + (PORT datad (1093:1093:1093) (1141:1141:1141)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~2) + (DELAY + (ABSOLUTE + (PORT dataa (401:401:401) (449:449:449)) + (PORT datab (221:221:221) (260:260:260)) + (PORT datad (783:783:783) (837:837:837)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~11) + (DELAY + (ABSOLUTE + (PORT dataa (356:356:356) (399:399:399)) + (PORT datab (1697:1697:1697) (1741:1741:1741)) + (PORT datac (1324:1324:1324) (1368:1368:1368)) + (PORT datad (181:181:181) (212:212:212)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~12) + (DELAY + (ABSOLUTE + (PORT datac (841:841:841) (870:870:870)) + (PORT datad (840:840:840) (834:834:834)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1790:1790:1790) (1875:1875:1875)) + (PORT datab (242:242:242) (289:289:289)) + (PORT datac (662:662:662) (700:700:700)) + (PORT datad (929:929:929) (952:952:952)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~5) + (DELAY + (ABSOLUTE + (PORT dataa (881:881:881) (908:908:908)) + (PORT datab (603:603:603) (635:635:635)) + (PORT datac (355:355:355) (384:384:384)) + (PORT datad (614:614:614) (628:628:628)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1430:1430:1430) (1499:1499:1499)) + (PORT datab (1185:1185:1185) (1226:1226:1226)) + (PORT datac (624:624:624) (688:688:688)) + (PORT datad (1209:1209:1209) (1274:1274:1274)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~10) + (DELAY + (ABSOLUTE + (PORT dataa (385:385:385) (415:415:415)) + (PORT datac (1063:1063:1063) (1070:1070:1070)) + (PORT datad (595:595:595) (604:604:604)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1874:1874:1874) (1932:1932:1932)) + (PORT datab (395:395:395) (431:431:431)) + (PORT datac (1474:1474:1474) (1511:1511:1511)) + (PORT datad (362:362:362) (392:392:392)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1179:1179:1179) (1222:1222:1222)) + (PORT datab (601:601:601) (615:615:615)) + (PORT datac (356:356:356) (383:383:383)) + (PORT datad (218:218:218) (254:254:254)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (854:854:854) (911:911:911)) + (PORT datab (640:640:640) (701:701:701)) + (PORT datac (1847:1847:1847) (1863:1863:1863)) + (PORT datad (603:603:603) (644:644:644)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~9) + (DELAY + (ABSOLUTE + (PORT dataa (658:658:658) (675:675:675)) + (PORT datab (1485:1485:1485) (1542:1542:1542)) + (PORT datac (618:618:618) (638:638:638)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~11) + (DELAY + (ABSOLUTE + (PORT dataa (608:608:608) (637:637:637)) + (PORT datab (206:206:206) (246:246:246)) + (PORT datac (171:171:171) (203:203:203)) + (PORT datad (172:172:172) (198:198:198)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~12) + (DELAY + (ABSOLUTE + (PORT dataa (233:233:233) (282:282:282)) + (PORT datab (1735:1735:1735) (1773:1773:1773)) + (PORT datac (343:343:343) (367:367:367)) + (PORT datad (1513:1513:1513) (1604:1604:1604)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1562:1562:1562) (1544:1544:1544)) + (PORT ena (1676:1676:1676) (1678:1678:1678)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) + (HOLD d (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_40\~0) + (INSTANCE z80_\|execute_\|fIOWrite\~0) (DELAY (ABSOLUTE - (PORT dataa (402:402:402) (457:457:457)) - (PORT datab (1258:1258:1258) (1344:1344:1344)) - (PORT datac (1146:1146:1146) (1187:1187:1187)) - (PORT datad (666:666:666) (682:682:682)) + (PORT dataa (2133:2133:2133) (2247:2247:2247)) + (PORT datab (2287:2287:2287) (2396:2396:2396)) + (PORT datac (1558:1558:1558) (1657:1657:1657)) + (PORT datad (2000:2000:2000) (2096:2096:2096)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~8) + (DELAY + (ABSOLUTE + (PORT dataa (2546:2546:2546) (2638:2638:2638)) + (PORT datab (1188:1188:1188) (1214:1214:1214)) + (PORT datac (634:634:634) (665:665:665)) + (PORT datad (833:833:833) (902:902:902)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1588:1588:1588) (1640:1640:1640)) + (PORT datab (213:213:213) (257:257:257)) + (PORT datac (193:193:193) (227:227:227)) + (PORT datad (1163:1163:1163) (1227:1227:1227)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~9) + (DELAY + (ABSOLUTE + (PORT dataa (230:230:230) (277:277:277)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (832:832:832) (840:840:840)) + (PORT datad (632:632:632) (692:692:692)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[1\]) + (DELAY + (ABSOLUTE + (PORT dataa (617:617:617) (651:651:651)) + (PORT datac (927:927:927) (948:948:948)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1526:1526:1526) (1546:1546:1546)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1573:1573:1573) (1552:1552:1552)) + (PORT ena (1991:1991:1991) (1983:1983:1983)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_apin_mux\~0) + (DELAY + (ABSOLUTE + (PORT dataa (214:214:214) (265:265:265)) + (PORT datab (219:219:219) (257:257:257)) + (PORT datac (209:209:209) (248:248:248)) + (PORT datad (1166:1166:1166) (1243:1243:1243)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1875:1875:1875) (1932:1932:1932)) + (PORT datab (1847:1847:1847) (1929:1929:1929)) + (PORT datac (194:194:194) (227:227:227)) + (PORT datad (1220:1220:1220) (1273:1273:1273)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1899:1899:1899) (2034:2034:2034)) + (PORT datac (1755:1755:1755) (1880:1880:1880)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_40\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1836:1836:1836) (1914:1914:1914)) + (PORT datab (393:393:393) (464:464:464)) + (PORT datac (1281:1281:1281) (1295:1295:1295)) + (PORT datad (197:197:197) (232:232:232)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~21) + (DELAY + (ABSOLUTE + (PORT dataa (1141:1141:1141) (1193:1193:1193)) + (PORT datab (1533:1533:1533) (1612:1612:1612)) + (PORT datac (1293:1293:1293) (1315:1315:1315)) + (PORT datad (1125:1125:1125) (1163:1163:1163)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (1921:1921:1921) (2032:2032:2032)) + (PORT datab (1238:1238:1238) (1320:1320:1320)) + (PORT datac (193:193:193) (226:226:226)) + (PORT datad (1989:1989:1989) (2064:2064:2064)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (1752:1752:1752) (1846:1846:1846)) + (PORT datab (234:234:234) (277:277:277)) + (PORT datac (1577:1577:1577) (1617:1617:1617)) + (PORT datad (1811:1811:1811) (1943:1943:1943)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (1627:1627:1627) (1722:1722:1722)) + (PORT datac (815:815:815) (866:866:866)) + (PORT datad (1467:1467:1467) (1547:1547:1547)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (209:209:209) (257:257:257)) + (PORT datab (1453:1453:1453) (1476:1476:1476)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (1294:1294:1294) (1384:1384:1384)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_63) + (DELAY + (ABSOLUTE + (PORT datab (902:902:902) (946:946:946)) + (PORT datac (1148:1148:1148) (1185:1185:1185)) + (PORT datad (799:799:799) (805:805:805)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1231:1231:1231) (1237:1237:1237)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~49) + (DELAY + (ABSOLUTE + (PORT dataa (1939:1939:1939) (1993:1993:1993)) + (PORT datab (1250:1250:1250) (1300:1300:1300)) + (PORT datac (919:919:919) (936:936:936)) + (PORT datad (1080:1080:1080) (1156:1156:1156)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~2) + (DELAY + (ABSOLUTE + (PORT datac (848:848:848) (880:880:880)) + (PORT datad (647:647:647) (704:704:704)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~50) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (266:266:266)) + (PORT datab (1271:1271:1271) (1337:1337:1337)) + (PORT datac (172:172:172) (206:206:206)) + (PORT datad (580:580:580) (596:596:596)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (945:945:945) (986:986:986)) + (PORT datab (1764:1764:1764) (1805:1805:1805)) + (PORT datac (678:678:678) (736:736:736)) + (PORT datad (904:904:904) (937:937:937)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_oe\~1) + (DELAY + (ABSOLUTE + (PORT dataa (229:229:229) (277:277:277)) + (PORT datab (240:240:240) (279:279:279)) + (PORT datac (637:637:637) (654:654:654)) + (PORT datad (1224:1224:1224) (1274:1274:1274)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~13) + (DELAY + (ABSOLUTE + (PORT dataa (891:891:891) (908:908:908)) + (PORT datab (1229:1229:1229) (1316:1316:1316)) + (PORT datac (838:838:838) (873:873:873)) + (PORT datad (1223:1223:1223) (1295:1295:1295)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~12) + (DELAY + (ABSOLUTE + (PORT datab (859:859:859) (880:880:880)) + (PORT datac (576:576:576) (592:592:592)) + (PORT datad (556:556:556) (557:557:557)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1934:1934:1934) (1998:1998:1998)) + (PORT datab (1408:1408:1408) (1411:1411:1411)) + (PORT datac (577:577:577) (613:613:613)) + (PORT datad (1428:1428:1428) (1538:1538:1538)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1367:1367:1367) (1430:1430:1430)) + (PORT datab (1228:1228:1228) (1316:1316:1316)) + (PORT datac (983:983:983) (1020:1020:1020)) + (PORT datad (885:885:885) (896:896:896)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1483:1483:1483) (1502:1502:1502)) + (PORT datab (208:208:208) (250:250:250)) + (PORT datac (344:344:344) (376:376:376)) + (PORT datad (203:203:203) (231:231:231)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (310:310:310)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -16490,12 +12034,1382 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~42) + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~5) (DELAY (ABSOLUTE - (PORT dataa (423:423:423) (485:485:485)) - (PORT datab (1600:1600:1600) (1653:1653:1653)) - (PORT datad (1181:1181:1181) (1221:1221:1221)) + (PORT dataa (1132:1132:1132) (1165:1165:1165)) + (PORT datab (227:227:227) (266:266:266)) + (PORT datac (1096:1096:1096) (1117:1117:1117)) + (PORT datad (1197:1197:1197) (1216:1216:1216)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1169:1169:1169) (1218:1218:1218)) + (PORT datab (220:220:220) (259:259:259)) + (PORT datac (1220:1220:1220) (1304:1304:1304)) + (PORT datad (618:618:618) (661:661:661)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1047:1047:1047) (1090:1090:1090)) + (PORT datab (651:651:651) (671:671:671)) + (PORT datac (831:831:831) (835:835:835)) + (PORT datad (182:182:182) (212:212:212)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~10) + (DELAY + (ABSOLUTE + (PORT dataa (231:231:231) (279:279:279)) + (PORT datab (1126:1126:1126) (1204:1204:1204)) + (PORT datac (1875:1875:1875) (1956:1956:1956)) + (PORT datad (1434:1434:1434) (1505:1505:1505)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_1d\~9) + (DELAY + (ABSOLUTE + (PORT datab (1832:1832:1832) (1926:1926:1926)) + (PORT datac (2081:2081:2081) (2255:2255:2255)) + (PORT datad (866:866:866) (901:901:901)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~9) + (DELAY + (ABSOLUTE + (PORT dataa (2210:2210:2210) (2368:2368:2368)) + (PORT datab (971:971:971) (1073:1073:1073)) + (PORT datac (193:193:193) (226:226:226)) + (PORT datad (1305:1305:1305) (1307:1307:1307)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (974:974:974) (1058:1058:1058)) + (PORT datab (845:845:845) (896:896:896)) + (PORT datad (345:345:345) (371:371:371)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~7) + (DELAY + (ABSOLUTE + (PORT dataa (392:392:392) (436:436:436)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (558:558:558) (564:564:564)) + (PORT datad (180:180:180) (209:209:209)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1101:1101:1101) (1193:1193:1193)) + (PORT datab (1600:1600:1600) (1725:1725:1725)) + (PORT datac (583:583:583) (625:625:625)) + (PORT datad (190:190:190) (222:222:222)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (2313:2313:2313) (2362:2362:2362)) + (PORT datab (873:873:873) (920:920:920)) + (PORT datac (1997:1997:1997) (2080:2080:2080)) + (PORT datad (2019:2019:2019) (2099:2099:2099)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1584:1584:1584) (1660:1660:1660)) + (PORT datab (1349:1349:1349) (1417:1417:1417)) + (PORT datac (1996:1996:1996) (2081:2081:2081)) + (PORT datad (1237:1237:1237) (1277:1277:1277)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~3) + (DELAY + (ABSOLUTE + (PORT dataa (899:899:899) (943:943:943)) + (PORT datab (206:206:206) (248:248:248)) + (PORT datac (171:171:171) (205:205:205)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (988:988:988) (1017:1017:1017)) + (PORT datab (688:688:688) (721:721:721)) + (PORT datac (849:849:849) (866:866:866)) + (PORT datad (891:891:891) (908:908:908)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (627:627:627) (692:692:692)) + (PORT datab (1851:1851:1851) (1861:1861:1861)) + (PORT datac (324:324:324) (346:346:346)) + (PORT datad (616:616:616) (643:643:643)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (570:570:570) (606:606:606)) + (PORT datab (1463:1463:1463) (1579:1579:1579)) + (PORT datac (578:578:578) (615:615:615)) + (PORT datad (1326:1326:1326) (1365:1365:1365)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla30npla13M4T3_5) + (DELAY + (ABSOLUTE + (PORT dataa (1308:1308:1308) (1396:1396:1396)) + (PORT datab (2420:2420:2420) (2553:2553:2553)) + (PORT datac (1094:1094:1094) (1118:1118:1118)) + (PORT datad (1195:1195:1195) (1217:1217:1217)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (948:948:948) (992:992:992)) + (PORT datab (957:957:957) (994:994:994)) + (PORT datac (1610:1610:1610) (1647:1647:1647)) + (PORT datad (1133:1133:1133) (1157:1157:1157)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (1188:1188:1188) (1197:1197:1197)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (1467:1467:1467) (1527:1527:1527)) + (PORT datad (927:927:927) (965:965:965)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (958:958:958) (1050:1050:1050)) + (PORT datab (1498:1498:1498) (1564:1564:1564)) + (PORT datac (1217:1217:1217) (1285:1285:1285)) + (PORT datad (1171:1171:1171) (1216:1216:1216)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (862:862:862) (897:897:897)) + (PORT datab (1733:1733:1733) (1770:1770:1770)) + (PORT datac (173:173:173) (206:206:206)) + (PORT datad (1512:1512:1512) (1602:1602:1602)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (242:242:242)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (194:194:194) (226:226:226)) + (PORT datad (610:610:610) (650:650:650)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (229:229:229) (276:276:276)) + (PORT datab (963:963:963) (1008:1008:1008)) + (PORT datac (624:624:624) (685:685:685)) + (PORT datad (1510:1510:1510) (1601:1601:1601)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (1678:1678:1678) (1717:1717:1717)) + (PORT datab (1179:1179:1179) (1219:1219:1219)) + (PORT datac (838:838:838) (872:872:872)) + (PORT datad (819:819:819) (842:842:842)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (241:241:241)) + (PORT datab (637:637:637) (694:694:694)) + (PORT datac (569:569:569) (590:590:590)) + (PORT datad (352:352:352) (382:382:382)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (2032:2032:2032) (2117:2117:2117)) + (PORT datab (1122:1122:1122) (1190:1190:1190)) + (PORT datac (2283:2283:2283) (2323:2323:2323)) + (PORT datad (1325:1325:1325) (1378:1378:1378)) + (IOPATH dataa combout (301:301:301) (307:307:307)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (897:897:897) (941:941:941)) + (PORT datab (425:425:425) (457:457:457)) + (PORT datac (839:839:839) (906:906:906)) + (PORT datad (194:194:194) (220:220:220)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (246:246:246)) + (PORT datab (207:207:207) (249:249:249)) + (PORT datac (585:585:585) (610:610:610)) + (PORT datad (194:194:194) (219:219:219)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (1483:1483:1483) (1501:1501:1501)) + (PORT datab (227:227:227) (266:266:266)) + (PORT datac (671:671:671) (719:719:719)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (964:964:964) (989:989:989)) + (PORT datab (212:212:212) (257:257:257)) + (PORT datad (888:888:888) (910:910:910)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (632:632:632) (645:645:645)) + (PORT datab (1105:1105:1105) (1105:1105:1105)) + (PORT datac (853:853:853) (869:869:869)) + (PORT datad (1157:1157:1157) (1187:1187:1187)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (412:412:412) (444:444:444)) + (PORT datab (391:391:391) (432:432:432)) + (PORT datac (178:178:178) (216:216:216)) + (PORT datad (171:171:171) (196:196:196)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal2\~2) + (DELAY + (ABSOLUTE + (PORT dataa (789:789:789) (894:894:894)) + (PORT datab (1922:1922:1922) (2016:2016:2016)) + (PORT datac (1273:1273:1273) (1346:1346:1346)) + (PORT datad (865:865:865) (888:888:888)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal1\~6) + (DELAY + (ABSOLUTE + (PORT dataa (370:370:370) (421:421:421)) + (PORT datab (1311:1311:1311) (1402:1402:1402)) + (PORT datac (829:829:829) (882:882:882)) + (PORT datad (357:357:357) (382:382:382)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|bank_exx\~2) + (DELAY + (ABSOLUTE + (PORT dataa (883:883:883) (915:915:915)) + (PORT datab (1481:1481:1481) (1573:1573:1573)) + (PORT datad (1200:1200:1200) (1275:1275:1275)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_control_\|bank_exx) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1567:1567:1567) (1549:1549:1549)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|bank_hl_de1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (948:948:948) (984:984:984)) + (PORT datab (619:619:619) (652:652:652)) + (PORT datad (276:276:276) (359:359:359)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_control_\|bank_hl_de1) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1567:1567:1567) (1549:1549:1549)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (627:627:627) (662:662:662)) + (PORT datab (741:741:741) (823:823:823)) + (PORT datac (1191:1191:1191) (1206:1206:1206)) + (PORT datad (1607:1607:1607) (1626:1626:1626)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (932:932:932) (967:967:967)) + (PORT datac (596:596:596) (622:622:622)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (852:852:852) (872:872:872)) + (PORT datab (588:588:588) (598:598:598)) + (PORT datac (871:871:871) (881:881:881)) + (PORT datad (183:183:183) (213:213:213)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (209:209:209) (256:256:256)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (820:820:820) (826:826:826)) + (PORT datad (931:931:931) (1009:1009:1009)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (951:951:951) (1014:1014:1014)) + (PORT datab (1267:1267:1267) (1328:1328:1328)) + (PORT datac (1708:1708:1708) (1771:1771:1771)) + (PORT datad (623:623:623) (637:637:637)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~45) + (DELAY + (ABSOLUTE + (PORT dataa (569:569:569) (606:606:606)) + (PORT datab (612:612:612) (649:649:649)) + (PORT datac (2087:2087:2087) (2253:2253:2253)) + (PORT datad (1784:1784:1784) (1865:1865:1865)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~2) + (DELAY + (ABSOLUTE + (PORT dataa (229:229:229) (275:275:275)) + (PORT datab (1702:1702:1702) (1722:1722:1722)) + (PORT datac (1037:1037:1037) (1088:1088:1088)) + (PORT datad (1279:1279:1279) (1348:1348:1348)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~3) + (DELAY + (ABSOLUTE + (PORT dataa (238:238:238) (287:287:287)) + (PORT datab (1179:1179:1179) (1189:1189:1189)) + (PORT datac (196:196:196) (239:239:239)) + (PORT datad (1523:1523:1523) (1592:1592:1592)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (633:633:633) (679:679:679)) + (PORT datab (220:220:220) (258:258:258)) + (PORT datac (200:200:200) (235:235:235)) + (PORT datad (804:804:804) (872:872:872)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (641:641:641) (676:676:676)) + (PORT datab (1421:1421:1421) (1501:1501:1501)) + (PORT datac (1162:1162:1162) (1195:1195:1195)) + (PORT datad (927:927:927) (965:965:965)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (1065:1065:1065) (1131:1131:1131)) + (PORT datab (688:688:688) (752:752:752)) + (PORT datac (643:643:643) (676:676:676)) + (PORT datad (1563:1563:1563) (1600:1600:1600)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1160:1160:1160) (1177:1177:1177)) + (PORT datab (923:923:923) (945:945:945)) + (PORT datac (820:820:820) (828:828:828)) + (PORT datad (837:837:837) (844:844:844)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~34) + (DELAY + (ABSOLUTE + (PORT datab (337:337:337) (367:367:367)) + (PORT datac (179:179:179) (216:216:216)) + (PORT datad (919:919:919) (988:988:988)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (579:579:579) (597:597:597)) + (PORT datac (763:763:763) (765:765:765)) + (PORT datad (318:318:318) (336:336:336)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (845:845:845) (901:901:901)) + (PORT datab (666:666:666) (696:696:696)) + (PORT datac (939:939:939) (971:971:971)) + (PORT datad (1281:1281:1281) (1352:1352:1352)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (1065:1065:1065) (1134:1134:1134)) + (PORT datab (1262:1262:1262) (1330:1330:1330)) + (PORT datac (922:922:922) (973:973:973)) + (PORT datad (942:942:942) (1006:1006:1006)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (608:608:608) (652:652:652)) + (PORT datab (1334:1334:1334) (1345:1345:1345)) + (PORT datac (922:922:922) (975:975:975)) + (PORT datad (172:172:172) (198:198:198)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (906:906:906) (934:934:934)) + (PORT datab (1264:1264:1264) (1330:1330:1330)) + (PORT datac (1581:1581:1581) (1628:1628:1628)) + (PORT datad (665:665:665) (713:713:713)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (1852:1852:1852) (1972:1972:1972)) + (PORT datab (1783:1783:1783) (1887:1887:1887)) + (PORT datac (186:186:186) (226:226:226)) + (PORT datad (1166:1166:1166) (1230:1230:1230)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1073:1073:1073) (1074:1074:1074)) + (PORT datab (626:626:626) (653:653:653)) + (PORT datac (1027:1027:1027) (1044:1044:1044)) + (PORT datad (1119:1119:1119) (1146:1146:1146)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (371:371:371) (392:392:392)) + (PORT datab (198:198:198) (236:236:236)) + (PORT datac (178:178:178) (213:213:213)) + (PORT datad (1663:1663:1663) (1726:1726:1726)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (215:215:215) (265:265:265)) + (PORT datab (1080:1080:1080) (1127:1127:1127)) + (PORT datac (867:867:867) (890:890:890)) + (PORT datad (1433:1433:1433) (1461:1461:1461)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (989:989:989) (1067:1067:1067)) + (PORT datab (1063:1063:1063) (1078:1078:1078)) + (PORT datac (1678:1678:1678) (1763:1763:1763)) + (PORT datad (828:828:828) (852:852:852)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (710:710:710) (785:785:785)) + (PORT datab (420:420:420) (490:490:490)) + (PORT datac (628:628:628) (694:694:694)) + (PORT datad (235:235:235) (303:303:303)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (681:681:681) (756:756:756)) + (PORT datab (1699:1699:1699) (1761:1761:1761)) + (PORT datac (347:347:347) (381:381:381)) + (PORT datad (1611:1611:1611) (1667:1667:1667)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (699:699:699) (774:774:774)) + (PORT datab (1189:1189:1189) (1284:1284:1284)) + (PORT datac (712:712:712) (808:808:808)) + (PORT datad (1178:1178:1178) (1275:1275:1275)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (741:741:741) (843:843:843)) + (PORT datab (1182:1182:1182) (1192:1192:1192)) + (PORT datac (1157:1157:1157) (1253:1253:1253)) + (PORT datad (1371:1371:1371) (1436:1436:1436)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (918:918:918) (998:998:998)) + (PORT datab (198:198:198) (238:238:238)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (1145:1145:1145) (1175:1175:1175)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (740:740:740) (806:806:806)) + (PORT datab (638:638:638) (650:650:650)) + (PORT datac (806:806:806) (818:818:818)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (577:577:577) (597:597:597)) + (PORT datab (369:369:369) (392:392:392)) + (PORT datac (859:859:859) (861:861:861)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_de2\~5) + (DELAY + (ABSOLUTE + (PORT dataa (480:480:480) (578:578:578)) + (PORT datab (494:494:494) (583:583:583)) + (PORT datac (840:840:840) (864:864:864)) + (PORT datad (915:915:915) (945:945:945)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_de2\~6) + (DELAY + (ABSOLUTE + (PORT dataa (577:577:577) (593:593:593)) + (PORT datab (341:341:341) (370:370:370)) + (PORT datac (766:766:766) (769:769:769)) + (PORT datad (196:196:196) (221:221:221)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_de\~0) + (DELAY + (ABSOLUTE + (PORT dataa (250:250:250) (340:340:340)) + (PORT datab (299:299:299) (394:394:394)) + (PORT datac (1077:1077:1077) (1071:1071:1071)) + (PORT datad (192:192:192) (226:226:226)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_50) + (DELAY + (ABSOLUTE + (PORT dataa (721:721:721) (783:783:783)) + (PORT datac (808:808:808) (854:854:854)) + (PORT datad (615:615:615) (659:659:659)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|bank_hl_de2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (950:950:950) (985:985:985)) + (PORT datab (614:614:614) (650:650:650)) + (PORT datad (276:276:276) (359:359:359)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_control_\|bank_hl_de2) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1567:1567:1567) (1549:1549:1549)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_de2\~4) + (DELAY + (ABSOLUTE + (PORT dataa (250:250:250) (341:341:341)) + (PORT datab (302:302:302) (397:397:397)) + (PORT datac (1073:1073:1073) (1071:1071:1071)) + (PORT datad (194:194:194) (229:229:229)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_46) + (DELAY + (ABSOLUTE + (PORT dataa (724:724:724) (786:786:786)) + (PORT datac (810:810:810) (853:853:853)) + (PORT datad (645:645:645) (684:684:684)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_47) + (DELAY + (ABSOLUTE + (PORT dataa (724:724:724) (783:783:783)) + (PORT datac (810:810:810) (854:854:854)) + (PORT datad (645:645:645) (685:685:685)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1549:1549:1549)) + (PORT asdata (1547:1547:1547) (1577:1577:1577)) + (PORT ena (974:974:974) (969:969:969)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_51) + (DELAY + (ABSOLUTE + (PORT dataa (724:724:724) (787:787:787)) + (PORT datac (810:810:810) (855:855:855)) + (PORT datad (614:614:614) (660:660:660)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1549:1549:1549)) + (PORT asdata (1547:1547:1547) (1574:1574:1574)) + (PORT ena (975:975:975) (970:970:970)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (408:408:408) (451:451:451)) + (PORT datab (440:440:440) (472:472:472)) + (PORT datad (215:215:215) (284:284:284)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_hl\~0) + (DELAY + (ABSOLUTE + (PORT dataa (249:249:249) (339:339:339)) + (PORT datab (300:300:300) (394:394:394)) + (PORT datac (1073:1073:1073) (1068:1068:1068)) + (PORT datad (194:194:194) (228:228:228)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_59) + (DELAY + (ABSOLUTE + (PORT dataa (928:928:928) (980:980:980)) + (PORT datab (648:648:648) (704:704:704)) + (PORT datad (595:595:595) (638:638:638)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT asdata (882:882:882) (892:892:892)) + (PORT ena (981:981:981) (980:980:980)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_hl2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (250:250:250) (339:339:339)) + (PORT datab (302:302:302) (394:394:394)) + (PORT datac (1077:1077:1077) (1074:1074:1074)) + (PORT datad (193:193:193) (226:226:226)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_54) + (DELAY + (ABSOLUTE + (PORT dataa (927:927:927) (974:974:974)) + (PORT datab (1199:1199:1199) (1242:1242:1242)) + (PORT datad (642:642:642) (684:684:684)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_55) + (DELAY + (ABSOLUTE + (PORT dataa (926:926:926) (980:980:980)) + (PORT datab (1196:1196:1196) (1244:1244:1244)) + (PORT datad (639:639:639) (683:683:683)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT asdata (881:881:881) (892:892:892)) + (PORT ena (811:811:811) (804:804:804)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_58) + (DELAY + (ABSOLUTE + (PORT dataa (925:925:925) (980:980:980)) + (PORT datac (617:617:617) (671:671:671)) + (PORT datad (595:595:595) (637:637:637)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (242:242:242) (329:329:329)) + (PORT datab (253:253:253) (303:303:303)) + (PORT datad (228:228:228) (265:265:265)) (IOPATH dataa combout (304:304:304) (307:307:307)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -16505,75 +13419,957 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~46) + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_70\~2) (DELAY (ABSOLUTE - (PORT dataa (603:603:603) (634:634:634)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (170:170:170) (203:203:203)) - (PORT datad (787:787:787) (785:785:785)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT datab (1169:1169:1169) (1216:1216:1216)) + (PORT datac (968:968:968) (1025:1025:1025)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~47) + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_38\~0) (DELAY (ABSOLUTE - (PORT dataa (623:623:623) (653:653:653)) - (PORT datab (336:336:336) (368:368:368)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (626:626:626) (642:642:642)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (921:921:921) (988:988:988)) - (PORT datab (218:218:218) (257:257:257)) - (PORT datac (618:618:618) (661:661:661)) - (PORT datad (787:787:787) (791:791:791)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT dataa (1015:1015:1015) (1091:1091:1091)) + (PORT datab (772:772:772) (829:829:829)) + (PORT datac (627:627:627) (674:674:674)) + (PORT datad (945:945:945) (977:977:977)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_71\~2) + (DELAY + (ABSOLUTE + (PORT datab (1168:1168:1168) (1211:1211:1211)) + (PORT datac (961:961:961) (1019:1019:1019)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_43\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1022:1022:1022) (1103:1103:1103)) + (PORT datab (763:763:763) (823:823:823)) + (PORT datac (608:608:608) (659:659:659)) + (PORT datad (940:940:940) (975:975:975)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT asdata (1267:1267:1267) (1311:1311:1311)) + (PORT ena (1220:1220:1220) (1212:1212:1212)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_39\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1022:1022:1022) (1102:1102:1102)) + (PORT datab (768:768:768) (831:831:831)) + (PORT datac (608:608:608) (661:661:661)) + (PORT datad (938:938:938) (975:975:975)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT asdata (1266:1266:1266) (1308:1308:1308)) + (PORT ena (1200:1200:1200) (1188:1188:1188)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_42\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1019:1019:1019) (1100:1100:1100)) + (PORT datab (764:764:764) (828:828:828)) + (PORT datac (631:631:631) (679:679:679)) + (PORT datad (939:939:939) (973:973:973)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (865:865:865) (934:934:934)) + (PORT datab (242:242:242) (325:325:325)) + (PORT datad (657:657:657) (720:720:720)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~15) + (DELAY + (ABSOLUTE + (PORT dataa (210:210:210) (256:256:256)) + (PORT datab (655:655:655) (678:678:678)) + (PORT datac (1025:1025:1025) (1067:1067:1067)) + (PORT datad (181:181:181) (210:210:210)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1118:1118:1118) (1130:1130:1130)) + (PORT datab (1452:1452:1452) (1476:1476:1476)) + (PORT datac (350:350:350) (377:377:377)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_83) + (DELAY + (ABSOLUTE + (PORT dataa (981:981:981) (1022:1022:1022)) + (PORT datac (1151:1151:1151) (1189:1189:1189)) + (PORT datad (876:876:876) (909:909:909)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1535:1535:1535)) + (PORT asdata (1552:1552:1552) (1574:1574:1574)) + (PORT ena (1274:1274:1274) (1265:1265:1265)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_82) + (DELAY + (ABSOLUTE + (PORT dataa (980:980:980) (1021:1021:1021)) + (PORT datac (1147:1147:1147) (1188:1188:1188)) + (PORT datad (872:872:872) (910:910:910)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~37) + (DELAY + (ABSOLUTE + (PORT datab (629:629:629) (651:651:651)) + (PORT datad (929:929:929) (952:952:952)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_66\~0) + (DELAY + (ABSOLUTE + (PORT dataa (666:666:666) (715:715:715)) + (PORT datab (961:961:961) (1016:1016:1016)) + (PORT datac (925:925:925) (952:952:952)) + (PORT datad (729:729:729) (785:785:785)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_iy\~2) + (DELAY + (ABSOLUTE + (PORT dataa (476:476:476) (576:576:576)) + (PORT datab (504:504:504) (584:584:584)) + (PORT datac (843:843:843) (866:866:866)) + (PORT datad (916:916:916) (947:947:947)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_71) + (DELAY + (ABSOLUTE + (PORT datab (1080:1080:1080) (1098:1098:1098)) + (PORT datac (821:821:821) (861:861:861)) + (PORT datad (1158:1158:1158) (1197:1197:1197)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT asdata (1278:1278:1278) (1319:1319:1319)) + (PORT ena (790:790:790) (782:782:782)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_67\~0) + (DELAY + (ABSOLUTE + (PORT dataa (640:640:640) (696:696:696)) + (PORT datab (752:752:752) (818:818:818)) + (PORT datac (927:927:927) (953:953:953)) + (PORT datad (933:933:933) (979:979:979)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT asdata (1277:1277:1277) (1319:1319:1319)) + (PORT ena (1288:1288:1288) (1306:1306:1306)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_70) + (DELAY + (ABSOLUTE + (PORT datab (1080:1080:1080) (1097:1097:1097)) + (PORT datac (821:821:821) (860:860:860)) + (PORT datad (1158:1158:1158) (1197:1197:1197)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (663:663:663) (742:742:742)) + (PORT datab (240:240:240) (322:322:322)) + (PORT datad (231:231:231) (269:269:269)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla37pla28M2T3_4) + (DELAY + (ABSOLUTE + (PORT dataa (1235:1235:1235) (1299:1299:1299)) + (PORT datab (2094:2094:2094) (2218:2218:2218)) + (PORT datac (1670:1670:1670) (1752:1752:1752)) + (PORT datad (666:666:666) (714:714:714)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1108:1108:1108) (1132:1132:1132)) + (PORT datab (1982:1982:1982) (2008:2008:2008)) + (PORT datac (1747:1747:1747) (1823:1823:1823)) + (PORT datad (568:568:568) (585:585:585)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1036:1036:1036) (1106:1106:1106)) + (PORT datac (560:560:560) (564:564:564)) + (PORT datad (316:316:316) (335:335:335)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_lo\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1071:1071:1071) (1086:1086:1086)) + (PORT datab (1166:1166:1166) (1189:1189:1189)) + (PORT datac (904:904:904) (933:933:933)) + (PORT datad (180:180:180) (210:210:210)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (194:194:194) (219:219:219)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~4) + (DELAY + (ABSOLUTE + (PORT dataa (2119:2119:2119) (2290:2290:2290)) + (PORT datab (993:993:993) (1113:1113:1113)) + (PORT datac (1800:1800:1800) (1891:1891:1891)) + (PORT datad (868:868:868) (902:902:902)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~5) + (DELAY + (ABSOLUTE + (PORT dataa (934:934:934) (978:978:978)) + (PORT datab (383:383:383) (410:410:410)) + (PORT datac (619:619:619) (675:675:675)) + (PORT datad (632:632:632) (646:646:646)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~6) + (DELAY + (ABSOLUTE + (PORT dataa (366:366:366) (386:386:386)) + (PORT datab (829:829:829) (911:911:911)) + (PORT datac (833:833:833) (856:856:856)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_79\~0) + (DELAY + (ABSOLUTE + (PORT dataa (894:894:894) (914:914:914)) + (PORT datab (768:768:768) (829:829:829)) + (PORT datac (608:608:608) (661:661:661)) + (PORT datad (938:938:938) (974:974:974)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1438:1438:1438) (1476:1476:1476)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_1d\~5) + (DELAY + (ABSOLUTE + (PORT dataa (877:877:877) (897:897:897)) + (PORT datab (741:741:741) (827:827:827)) + (PORT datac (1193:1193:1193) (1210:1210:1210)) + (PORT datad (196:196:196) (221:221:221)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_im_we) + (DELAY + (ABSOLUTE + (PORT dataa (2036:2036:2036) (2132:2132:2132)) + (PORT datab (1850:1850:1850) (1987:1987:1987)) + (PORT datac (1886:1886:1886) (1987:1987:1987)) + (PORT datad (1685:1685:1685) (1763:1763:1763)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_1d\~6) + (DELAY + (ABSOLUTE + (PORT dataa (626:626:626) (665:665:665)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (854:854:854) (889:889:889)) + (PORT datad (631:631:631) (666:666:666)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_1d\~7) + (DELAY + (ABSOLUTE + (PORT dataa (863:863:863) (899:899:899)) + (PORT datab (1394:1394:1394) (1389:1389:1389)) + (PORT datac (633:633:633) (693:693:693)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_ds\[2\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (827:827:827) (862:862:862)) + (PORT datab (1124:1124:1124) (1164:1164:1164)) + (PORT datac (655:655:655) (684:684:684)) + (PORT datad (1218:1218:1218) (1229:1229:1229)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[2\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (865:865:865) (888:888:888)) + (PORT datab (373:373:373) (407:407:407)) + (PORT datac (408:408:408) (450:450:450)) + (PORT datad (176:176:176) (201:201:201)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~11) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (263:263:263)) + (PORT datab (655:655:655) (675:675:675)) + (PORT datac (912:912:912) (927:927:927)) + (PORT datad (1988:1988:1988) (2062:2062:2062)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~12) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (254:254:254)) + (PORT datab (1505:1505:1505) (1589:1589:1589)) + (PORT datac (825:825:825) (846:846:846)) + (PORT datad (188:188:188) (219:219:219)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (1288:1288:1288) (1315:1315:1315)) + (PORT datab (1444:1444:1444) (1478:1478:1478)) + (PORT datac (1648:1648:1648) (1683:1683:1683)) + (PORT datad (364:364:364) (397:397:397)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (671:671:671) (717:717:717)) + (PORT datab (1159:1159:1159) (1190:1190:1190)) + (PORT datac (657:657:657) (723:723:723)) + (PORT datad (1115:1115:1115) (1128:1128:1128)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (1062:1062:1062) (1130:1130:1130)) + (PORT datab (952:952:952) (1010:1010:1010)) + (PORT datac (607:607:607) (626:626:626)) + (PORT datad (940:940:940) (1002:1002:1002)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (242:242:242)) + (PORT datab (679:679:679) (723:723:723)) + (PORT datac (174:174:174) (207:207:207)) + (PORT datad (602:602:602) (611:611:611)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~41) + (DELAY + (ABSOLUTE + (PORT dataa (350:350:350) (391:391:391)) + (PORT datab (1103:1103:1103) (1102:1102:1102)) + (PORT datac (874:874:874) (899:899:899)) + (PORT datad (592:592:592) (600:600:600)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~43) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (656:656:656) (713:713:713)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (180:180:180) (207:207:207)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_68\~2) + (DELAY + (ABSOLUTE + (PORT datac (1873:1873:1873) (1943:1943:1943)) + (PORT datad (1780:1780:1780) (1858:1858:1858)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_64\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1195:1195:1195) (1243:1243:1243)) + (PORT datab (598:598:598) (625:625:625)) + (PORT datac (949:949:949) (998:998:998)) + (PORT datad (643:643:643) (669:669:669)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_76\~0) + (DELAY + (ABSOLUTE + (PORT dataa (961:961:961) (994:994:994)) + (PORT datab (750:750:750) (818:818:818)) + (PORT datac (852:852:852) (869:869:869)) + (PORT datad (650:650:650) (672:672:672)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_68) + (DELAY + (ABSOLUTE + (PORT datab (1052:1052:1052) (1073:1073:1073)) + (PORT datac (1876:1876:1876) (1945:1945:1945)) + (PORT datad (1783:1783:1783) (1860:1860:1860)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_40\~0) + (DELAY + (ABSOLUTE + (PORT dataa (688:688:688) (765:765:765)) + (PORT datab (1487:1487:1487) (1504:1504:1504)) + (PORT datac (880:880:880) (892:892:892)) + (PORT datad (618:618:618) (651:651:651)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_36\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1018:1018:1018) (1095:1095:1095)) + (PORT datab (770:770:770) (831:831:831)) + (PORT datac (925:925:925) (952:952:952)) + (PORT datad (651:651:651) (672:672:672)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~18) (DELAY (ABSOLUTE - (PORT dataa (1064:1064:1064) (1103:1103:1103)) - (PORT datab (836:836:836) (868:868:868)) - (PORT datac (218:218:218) (261:261:261)) + (PORT dataa (692:692:692) (732:732:732)) + (PORT datab (348:348:348) (382:382:382)) + (PORT datac (600:600:600) (629:629:629)) (IOPATH dataa combout (354:354:354) (349:349:349)) (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (243:243:243) (242:242:242)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_80) + (DELAY + (ABSOLUTE + (PORT datab (929:929:929) (971:971:971)) + (PORT datac (1103:1103:1103) (1141:1141:1141)) + (PORT datad (942:942:942) (978:978:978)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal21\~2) + (DELAY + (ABSOLUTE + (PORT dataa (232:232:232) (291:291:291)) + (PORT datab (883:883:883) (939:939:939)) + (PORT datad (1361:1361:1361) (1485:1485:1485)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|bank_af\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1181:1181:1181) (1223:1223:1223)) + (PORT datab (1462:1462:1462) (1481:1481:1481)) + (PORT datad (324:324:324) (335:335:335)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_control_\|bank_af) + (DELAY + (ABSOLUTE + (PORT clk (1513:1513:1513) (1527:1527:1527)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1557:1557:1557) (1538:1538:1538)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_af\~0) + (DELAY + (ABSOLUTE + (PORT dataa (889:889:889) (912:912:912)) + (PORT datab (968:968:968) (1010:1010:1010)) + (PORT datac (1317:1317:1317) (1480:1480:1480)) + (PORT datad (714:714:714) (774:774:774)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_af2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (891:891:891) (917:917:917)) + (PORT datab (967:967:967) (1015:1015:1015)) + (PORT datac (1318:1318:1318) (1484:1484:1484)) + (PORT datad (727:727:727) (784:784:784)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_28) + (DELAY + (ABSOLUTE + (PORT dataa (1908:1908:1908) (1979:1979:1979)) + (PORT datac (617:617:617) (658:658:658)) + (PORT datad (1772:1772:1772) (1850:1850:1850)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (673:673:673) (722:722:722)) + (PORT datab (585:585:585) (616:616:616)) + (PORT datac (604:604:604) (633:633:633)) + (PORT datad (399:399:399) (442:442:442)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~19) (DELAY (ABSOLUTE - (PORT dataa (649:649:649) (671:671:671)) - (PORT datab (834:834:834) (892:892:892)) - (PORT datac (174:174:174) (207:207:207)) - (PORT datad (874:874:874) (899:899:899)) + (PORT dataa (370:370:370) (402:402:402)) + (PORT datab (673:673:673) (707:707:707)) + (PORT datac (312:312:312) (333:333:333)) + (PORT datad (173:173:173) (199:199:199)) (IOPATH dataa combout (354:354:354) (349:349:349)) (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (243:243:243) (241:241:241)) @@ -16581,14 +14377,70 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_52) + (DELAY + (ABSOLUTE + (PORT dataa (1127:1127:1127) (1157:1157:1157)) + (PORT datac (1399:1399:1399) (1453:1453:1453)) + (PORT datad (822:822:822) (847:847:847)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_44) + (DELAY + (ABSOLUTE + (PORT dataa (1835:1835:1835) (1917:1917:1917)) + (PORT datac (1882:1882:1882) (1953:1953:1953)) + (PORT datad (1121:1121:1121) (1148:1148:1148)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_48) + (DELAY + (ABSOLUTE + (PORT dataa (1836:1836:1836) (1917:1917:1917)) + (PORT datac (1883:1883:1883) (1953:1953:1953)) + (PORT datad (1107:1107:1107) (1112:1112:1112)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_56) + (DELAY + (ABSOLUTE + (PORT dataa (1832:1832:1832) (1915:1915:1915)) + (PORT datac (1879:1879:1879) (1950:1950:1950)) + (PORT datad (1091:1091:1091) (1097:1097:1097)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~16) (DELAY (ABSOLUTE - (PORT dataa (221:221:221) (265:265:265)) - (PORT datab (220:220:220) (259:259:259)) - (PORT datac (194:194:194) (228:228:228)) + (PORT dataa (897:897:897) (939:939:939)) + (PORT datab (222:222:222) (261:261:261)) + (PORT datac (195:195:195) (229:229:229)) (PORT datad (196:196:196) (222:222:222)) (IOPATH dataa combout (354:354:354) (349:349:349)) (IOPATH datab combout (355:355:355) (349:349:349)) @@ -16602,10 +14454,10 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~20) (DELAY (ABSOLUTE - (PORT dataa (1547:1547:1547) (1564:1564:1564)) - (PORT datab (851:851:851) (910:910:910)) - (PORT datac (1130:1130:1130) (1151:1151:1151)) - (PORT datad (173:173:173) (198:198:198)) + (PORT dataa (1197:1197:1197) (1216:1216:1216)) + (PORT datab (198:198:198) (236:236:236)) + (PORT datac (565:565:565) (582:582:582)) + (PORT datad (1141:1141:1141) (1165:1165:1165)) (IOPATH dataa combout (354:354:354) (349:349:349)) (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (243:243:243) (241:241:241)) @@ -16615,368 +14467,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_73) + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_69\~2) (DELAY (ABSOLUTE - (PORT dataa (1308:1308:1308) (1399:1399:1399)) - (PORT datac (1141:1141:1141) (1164:1164:1164)) - (PORT datad (832:832:832) (866:866:866)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1308:1308:1308) (1303:1303:1303)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1537:1537:1537)) - (PORT asdata (1187:1187:1187) (1229:1229:1229)) - (PORT ena (990:990:990) (994:994:994)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1537:1537:1537)) - (PORT asdata (1186:1186:1186) (1227:1227:1227)) - (PORT ena (973:973:973) (964:964:964)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (460:460:460) (523:523:523)) - (PORT datab (492:492:492) (541:541:541)) - (PORT datad (216:216:216) (285:285:285)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (1950:1950:1950) (1996:1996:1996)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (937:937:937) (991:991:991)) - (PORT datab (1222:1222:1222) (1291:1291:1291)) - (PORT datad (879:879:879) (935:935:935)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1535:1535:1535) (1554:1554:1554)) - (PORT asdata (545:545:545) (579:579:579)) - (PORT ena (1461:1461:1461) (1468:1468:1468)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (1716:1716:1716) (1767:1767:1767)) - (PORT ena (1261:1261:1261) (1299:1299:1299)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1098:1098:1098) (1151:1151:1151)) - (PORT datab (648:648:648) (728:728:728)) - (PORT datad (845:845:845) (876:876:876)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1534:1534:1534)) - (PORT asdata (2219:2219:2219) (2260:2260:2260)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (851:851:851) (881:881:881)) - (PORT datab (1166:1166:1166) (1218:1218:1218)) - (PORT datad (240:240:240) (280:280:280)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (1976:1976:1976) (2020:2020:2020)) - (PORT ena (1193:1193:1193) (1176:1176:1176)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (1977:1977:1977) (2023:2023:2023)) - (PORT ena (1283:1283:1283) (1283:1283:1283)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (387:387:387) (466:466:466)) - (PORT datab (1593:1593:1593) (1643:1643:1643)) - (PORT datad (1180:1180:1180) (1216:1216:1216)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (1715:1715:1715) (1766:1766:1766)) - (PORT ena (1131:1131:1131) (1098:1098:1098)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1611:1611:1611) (1650:1650:1650)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (391:391:391) (433:433:433)) - (PORT datab (886:886:886) (923:923:923)) - (PORT datad (859:859:859) (925:925:925)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (241:241:241)) - (PORT datab (632:632:632) (649:649:649)) - (PORT datac (338:338:338) (358:358:358)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (2372:2372:2372) (2423:2423:2423)) - (PORT ena (1388:1388:1388) (1427:1427:1427)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (2371:2371:2371) (2423:2423:2423)) - (PORT ena (1400:1400:1400) (1413:1413:1413)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (926:926:926) (986:986:986)) - (PORT datab (911:911:911) (986:986:986)) - (PORT datad (216:216:216) (285:285:285)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (651:651:651) (672:672:672)) - (PORT datab (196:196:196) (235:235:235)) - (PORT datac (596:596:596) (613:613:613)) - (PORT datad (313:313:313) (323:323:323)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) + (PORT datac (1867:1867:1867) (1939:1939:1939)) + (PORT datad (1774:1774:1774) (1853:1853:1853)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -16984,803 +14479,28 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~21) + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_65\~0) (DELAY (ABSOLUTE - (PORT dataa (879:879:879) (944:944:944)) - (PORT datab (543:543:543) (563:563:563)) - (PORT datac (1049:1049:1049) (1102:1102:1102)) - (PORT datad (1297:1297:1297) (1338:1338:1338)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_60) - (DELAY - (ABSOLUTE - (PORT dataa (860:860:860) (911:911:911)) - (PORT datac (1138:1138:1138) (1159:1159:1159)) - (PORT datad (844:844:844) (869:869:869)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_61) - (DELAY - (ABSOLUTE - (PORT dataa (860:860:860) (909:909:909)) - (PORT datac (1140:1140:1140) (1164:1164:1164)) - (PORT datad (844:844:844) (871:871:871)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1535:1535:1535) (1554:1554:1554)) - (PORT asdata (1391:1391:1391) (1443:1443:1443)) - (PORT ena (935:935:935) (924:924:924)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sw_4d_hi\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1171:1171:1171) (1195:1195:1195)) - (PORT datab (835:835:835) (855:855:855)) - (PORT datac (1143:1143:1143) (1163:1163:1163)) - (PORT datad (844:844:844) (868:868:868)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (230:230:230) (276:276:276)) - (PORT datab (409:409:409) (450:450:450)) - (PORT datad (382:382:382) (419:419:419)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_72) - (DELAY - (ABSOLUTE - (PORT dataa (1308:1308:1308) (1398:1398:1398)) - (PORT datac (1141:1141:1141) (1165:1165:1165)) - (PORT datad (832:832:832) (866:866:866)) - (IOPATH dataa combout (341:341:341) (347:347:347)) + (PORT dataa (655:655:655) (687:687:687)) + (PORT datab (964:964:964) (1019:1019:1019)) + (PORT datac (926:926:926) (953:953:953)) + (PORT datad (730:730:730) (786:786:786)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (244:244:244) (331:331:331)) - (PORT datac (762:762:762) (815:815:815)) - (PORT datad (642:642:642) (666:666:666)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (239:239:239) (292:292:292)) - (PORT datab (235:235:235) (277:277:277)) - (PORT datac (1097:1097:1097) (1113:1113:1113)) - (PORT datad (212:212:212) (246:246:246)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|d1_out) - (DELAY - (ABSOLUTE - (PORT dataa (418:418:418) (508:508:508)) - (PORT datab (279:279:279) (364:364:364)) - (PORT datac (1332:1332:1332) (1337:1337:1337)) - (PORT datad (184:184:184) (216:216:216)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1554:1554:1554)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (842:842:842) (856:856:856)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (951:951:951) (975:975:975)) - (PORT ena (1388:1388:1388) (1427:1427:1427)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (951:951:951) (974:974:974)) - (PORT ena (1400:1400:1400) (1413:1413:1413)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (918:918:918) (978:978:978)) - (PORT datab (914:914:914) (989:989:989)) - (PORT datad (214:214:214) (283:283:283)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1537:1537:1537)) - (PORT asdata (1393:1393:1393) (1432:1432:1432)) - (PORT ena (990:990:990) (994:994:994)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1537:1537:1537)) - (PORT asdata (1390:1390:1390) (1429:1429:1429)) - (PORT ena (973:973:973) (964:964:964)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (462:462:462) (517:517:517)) - (PORT datab (496:496:496) (537:537:537)) - (PORT datad (217:217:217) (286:286:286)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (1278:1278:1278) (1308:1308:1308)) - (PORT ena (1283:1283:1283) (1283:1283:1283)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (1278:1278:1278) (1306:1306:1306)) - (PORT ena (1193:1193:1193) (1176:1176:1176)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (388:388:388) (458:458:458)) - (PORT datab (1599:1599:1599) (1646:1646:1646)) - (PORT datad (1181:1181:1181) (1215:1215:1215)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1534:1534:1534)) - (PORT asdata (1228:1228:1228) (1277:1277:1277)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (1058:1058:1058) (1070:1070:1070)) - (PORT datab (1167:1167:1167) (1216:1216:1216)) - (PORT datad (237:237:237) (277:277:277)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (810:810:810) (862:862:862)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1214:1214:1214) (1210:1210:1210)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (1259:1259:1259) (1290:1290:1290)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (244:244:244) (331:331:331)) - (PORT datab (243:243:243) (289:289:289)) - (PORT datad (875:875:875) (901:901:901)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT asdata (689:689:689) (709:709:709)) - (PORT ena (1404:1404:1404) (1382:1382:1382)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1474:1474:1474) (1488:1488:1488)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (1058:1058:1058) (1072:1072:1072)) - (PORT datab (1270:1270:1270) (1360:1360:1360)) - (PORT datad (216:216:216) (285:285:285)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (838:838:838) (872:872:872)) - (PORT datab (1030:1030:1030) (1072:1072:1072)) - (PORT datac (803:803:803) (856:856:856)) - (PORT datad (173:173:173) (197:197:197)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (969:969:969) (986:986:986)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[0\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (931:931:931) (986:986:986)) - (PORT datab (1221:1221:1221) (1292:1292:1292)) - (PORT datad (887:887:887) (945:945:945)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (380:380:380) (429:429:429)) - (PORT datab (829:829:829) (880:880:880)) - (PORT datac (170:170:170) (202:202:202)) - (PORT datad (558:558:558) (582:582:582)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (834:834:834) (864:864:864)) - (PORT datab (867:867:867) (903:903:903)) - (PORT datac (808:808:808) (862:862:862)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1554:1554:1554)) - (PORT asdata (881:881:881) (888:888:888)) - (PORT ena (940:940:940) (926:926:926)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (238:238:238) (288:288:288)) - (PORT datab (905:905:905) (941:941:941)) - (PORT datad (211:211:211) (245:245:245)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (237:237:237) (288:288:288)) - (PORT datac (214:214:214) (290:290:290)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1135:1135:1135) (1153:1153:1153)) - (PORT datab (827:827:827) (837:837:837)) - (PORT datac (199:199:199) (234:234:234)) - (PORT datad (171:171:171) (196:196:196)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[8\]) - (DELAY - (ABSOLUTE - (PORT dataa (688:688:688) (733:733:733)) - (PORT datac (799:799:799) (817:817:817)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[8\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1560:1560:1560)) - (PORT ena (2152:2152:2152) (2220:2220:2220)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|carry_borrow_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (422:422:422) (513:513:513)) - (PORT datab (280:280:280) (369:369:369)) - (PORT datac (1329:1329:1329) (1334:1334:1334)) - (PORT datad (189:189:189) (221:221:221)) - (IOPATH dataa combout (301:301:301) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|d0_out) - (DELAY - (ABSOLUTE - (PORT datac (248:248:248) (337:337:337)) - (PORT datad (324:324:324) (346:346:346)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (712:712:712) (756:756:756)) - (PORT datac (810:810:810) (842:842:842)) - (PORT datad (578:578:578) (586:586:586)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[9\]) - (DELAY - (ABSOLUTE - (PORT datab (355:355:355) (385:385:385)) - (PORT datac (880:880:880) (911:911:911)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|Q\[9\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (554:554:554) (561:561:561)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[9\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1560:1560:1560)) - (PORT ena (2096:2096:2096) (2133:2133:2133)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|d1_out) - (DELAY - (ABSOLUTE - (PORT dataa (268:268:268) (364:364:364)) - (PORT datab (279:279:279) (374:374:374)) - (PORT datac (1335:1335:1335) (1349:1349:1349)) - (PORT datad (325:325:325) (343:343:343)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (1106:1106:1106) (1145:1145:1145)) - (PORT ena (1388:1388:1388) (1427:1427:1427)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (1107:1107:1107) (1146:1146:1146)) - (PORT ena (1400:1400:1400) (1413:1413:1413)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (921:921:921) (980:980:980)) - (PORT datab (914:914:914) (982:982:982)) - (PORT datad (216:216:216) (283:283:283)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1534:1534:1534)) - (PORT asdata (1947:1947:1947) (2004:2004:2004)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (812:812:812) (827:827:827)) - (PORT datab (1168:1168:1168) (1216:1216:1216)) - (PORT datad (240:240:240) (281:281:281)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[2\]) (DELAY (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (1439:1439:1439) (1508:1508:1508)) - (PORT ena (1131:1131:1131) (1098:1098:1098)) + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT asdata (1533:1533:1533) (1561:1561:1561)) + (PORT ena (1229:1229:1229) (1240:1240:1240)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -17791,10 +14511,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[2\]\~feeder) + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_69) (DELAY (ABSOLUTE - (PORT datad (778:778:778) (850:850:850)) + (PORT datab (1052:1052:1052) (1072:1072:1072)) + (PORT datac (1869:1869:1869) (1942:1942:1942)) + (PORT datad (1777:1777:1777) (1856:1856:1856)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -17804,66 +14528,9 @@ (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[2\]) (DELAY (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (391:391:391) (433:433:433)) - (PORT datab (886:886:886) (923:923:923)) - (PORT datad (350:350:350) (406:406:406)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1005:1005:1005) (1055:1055:1055)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1193:1193:1193) (1176:1176:1176)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (1994:1994:1994) (2075:2075:2075)) - (PORT ena (1283:1283:1283) (1283:1283:1283)) + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT asdata (1536:1536:1536) (1566:1566:1566)) + (PORT ena (1168:1168:1168) (1147:1147:1147)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -17874,27 +14541,43 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~33) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~34) (DELAY (ABSOLUTE - (PORT dataa (568:568:568) (641:641:641)) - (PORT datab (1599:1599:1599) (1649:1649:1649)) - (PORT datad (1179:1179:1179) (1219:1219:1219)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (693:693:693) (725:725:725)) + (PORT datab (268:268:268) (323:323:323)) + (PORT datad (217:217:217) (285:285:285)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_77\~0) + (DELAY + (ABSOLUTE + (PORT dataa (655:655:655) (688:688:688)) + (PORT datab (773:773:773) (830:830:830)) + (PORT datac (856:856:856) (878:878:878)) + (PORT datad (945:945:945) (977:977:977)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[2\]) (DELAY (ABSOLUTE - (PORT clk (1535:1535:1535) (1554:1554:1554)) + (PORT clk (1520:1520:1520) (1533:1533:1533)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1461:1461:1461) (1468:1468:1468)) + (PORT ena (1503:1503:1503) (1497:1497:1497)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -17903,14 +14586,28 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_81) + (DELAY + (ABSOLUTE + (PORT datab (930:930:930) (973:973:973)) + (PORT datac (1105:1105:1105) (1142:1142:1142)) + (PORT datad (943:943:943) (979:979:979)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[2\]) (DELAY (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (1439:1439:1439) (1506:1506:1506)) - (PORT ena (1261:1261:1261) (1299:1299:1299)) + (PORT clk (1520:1520:1520) (1533:1533:1533)) + (PORT asdata (1702:1702:1702) (1705:1705:1705)) + (PORT ena (1227:1227:1227) (1249:1249:1249)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -17924,9 +14621,54 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~36) (DELAY (ABSOLUTE - (PORT dataa (1100:1100:1100) (1147:1147:1147)) - (PORT datab (678:678:678) (753:753:753)) - (PORT datad (849:849:849) (878:878:878)) + (PORT dataa (707:707:707) (780:780:780)) + (PORT datab (242:242:242) (322:322:322)) + (PORT datad (694:694:694) (744:744:744)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_29) + (DELAY + (ABSOLUTE + (PORT dataa (1921:1921:1921) (1993:1993:1993)) + (PORT datac (619:619:619) (662:662:662)) + (PORT datad (1786:1786:1786) (1864:1864:1864)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1533:1533:1533)) + (PORT asdata (1200:1200:1200) (1213:1213:1213)) + (PORT ena (1201:1201:1201) (1198:1198:1198)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (1201:1201:1201) (1222:1222:1222)) + (PORT datab (908:908:908) (935:935:935)) + (PORT datad (400:400:400) (437:437:437)) (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -17934,15 +14676,94 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_37\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1024:1024:1024) (1103:1103:1103)) + (PORT datab (758:758:758) (823:823:823)) + (PORT datac (925:925:925) (953:953:953)) + (PORT datad (628:628:628) (646:646:646)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (1353:1353:1353) (1408:1408:1408)) + (PORT ena (1225:1225:1225) (1236:1236:1236)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_41\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1023:1023:1023) (1104:1104:1104)) + (PORT datab (761:761:761) (825:825:825)) + (PORT datac (925:925:925) (955:955:955)) + (PORT datad (626:626:626) (647:647:647)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (1351:1351:1351) (1406:1406:1406)) + (PORT ena (1440:1440:1440) (1419:1419:1419)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (702:702:702) (764:764:764)) + (PORT datab (658:658:658) (677:677:677)) + (PORT datad (217:217:217) (286:286:286)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~37) (DELAY (ABSOLUTE - (PORT dataa (631:631:631) (653:653:653)) - (PORT datab (198:198:198) (236:236:236)) - (PORT datac (599:599:599) (617:617:617)) - (PORT datad (175:175:175) (201:201:201)) + (PORT dataa (602:602:602) (622:622:622)) + (PORT datab (642:642:642) (658:658:658)) + (PORT datac (618:618:618) (634:634:634)) + (PORT datad (998:998:998) (1038:1038:1038)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -17950,35 +14771,73 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_45) + (DELAY + (ABSOLUTE + (PORT dataa (1532:1532:1532) (1588:1588:1588)) + (PORT datab (2174:2174:2174) (2213:2213:2213)) + (PORT datad (1400:1400:1400) (1412:1412:1412)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (968:968:968) (992:992:992)) + (PORT ena (981:981:981) (980:980:980)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (563:563:563) (585:585:585)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_49) + (DELAY + (ABSOLUTE + (PORT dataa (1834:1834:1834) (1916:1916:1916)) + (PORT datac (1881:1881:1881) (1952:1952:1952)) + (PORT datad (1107:1107:1107) (1109:1109:1109)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[2\]) (DELAY (ABSOLUTE - (PORT clk (1523:1523:1523) (1537:1537:1537)) - (PORT asdata (2176:2176:2176) (2269:2269:2269)) - (PORT ena (973:973:973) (964:964:964)) + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1190:1190:1190) (1164:1164:1164)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1537:1537:1537)) - (PORT asdata (2177:2177:2177) (2273:2273:2273)) - (PORT ena (990:990:990) (994:994:994)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) + (HOLD d (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) ) ) @@ -17987,24 +14846,38 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~31) (DELAY (ABSOLUTE - (PORT dataa (461:461:461) (524:524:524)) - (PORT datab (243:243:243) (326:326:326)) - (PORT datad (454:454:454) (497:497:497)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT dataa (700:700:700) (735:735:735)) + (PORT datab (699:699:699) (719:719:719)) + (PORT datad (217:217:217) (286:286:286)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_33) + (DELAY + (ABSOLUTE + (PORT dataa (1526:1526:1526) (1579:1579:1579)) + (PORT datab (2177:2177:2177) (2222:2222:2222)) + (PORT datad (1364:1364:1364) (1385:1385:1385)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[2\]) (DELAY (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (2201:2201:2201) (2285:2285:2285)) - (PORT ena (794:794:794) (792:792:792)) + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (912:912:912) (926:926:926)) + (PORT ena (790:790:790) (782:782:782)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -18015,12 +14888,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[2\]\~17) + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[2\]\~12) (DELAY (ABSOLUTE - (PORT dataa (928:928:928) (990:990:990)) - (PORT datab (1220:1220:1220) (1290:1290:1290)) - (PORT datad (884:884:884) (941:941:941)) + (PORT dataa (1538:1538:1538) (1587:1587:1587)) + (PORT datab (2171:2171:2171) (2210:2210:2210)) + (PORT datad (1367:1367:1367) (1389:1389:1389)) (IOPATH dataa combout (300:300:300) (308:308:308)) (IOPATH datab combout (300:300:300) (310:310:310)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -18028,15 +14901,90 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_57) + (DELAY + (ABSOLUTE + (PORT dataa (1835:1835:1835) (1917:1917:1917)) + (PORT datac (1882:1882:1882) (1952:1952:1952)) + (PORT datad (1091:1091:1091) (1095:1095:1095)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1530:1530:1530)) + (PORT asdata (1220:1220:1220) (1225:1225:1225)) + (PORT ena (1240:1240:1240) (1223:1223:1223)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_53) + (DELAY + (ABSOLUTE + (PORT dataa (1127:1127:1127) (1157:1157:1157)) + (PORT datac (1398:1398:1398) (1452:1452:1452)) + (PORT datad (822:822:822) (846:846:846)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1530:1530:1530)) + (PORT asdata (1220:1220:1220) (1222:1222:1222)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (730:730:730) (755:755:755)) + (PORT datab (242:242:242) (323:323:323)) + (PORT datad (227:227:227) (265:265:265)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~38) (DELAY (ABSOLUTE - (PORT dataa (773:773:773) (837:837:837)) - (PORT datab (560:560:560) (597:597:597)) - (PORT datac (558:558:558) (555:555:555)) - (PORT datad (850:850:850) (877:877:877)) + (PORT dataa (335:335:335) (368:368:368)) + (PORT datab (622:622:622) (648:648:648)) + (PORT datac (339:339:339) (359:359:359)) + (PORT datad (316:316:316) (336:336:336)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -18046,92 +14994,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~39) + (INSTANCE z80_\|execute_\|ctl_inc_dec\~11) (DELAY (ABSOLUTE - (PORT dataa (837:837:837) (909:909:909)) - (PORT datab (396:396:396) (421:421:421)) - (PORT datac (848:848:848) (907:907:907)) - (PORT datad (1297:1297:1297) (1337:1337:1337)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1554:1554:1554)) - (PORT asdata (545:545:545) (579:579:579)) - (PORT ena (940:940:940) (926:926:926)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1897:1897:1897) (1987:1987:1987)) - (PORT datab (235:235:235) (281:281:281)) - (PORT datad (211:211:211) (246:246:246)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1554:1554:1554)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (842:842:842) (856:856:856)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (237:237:237) (287:287:287)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datad (354:354:354) (413:413:413)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1139:1139:1139) (1156:1156:1156)) - (PORT datab (545:545:545) (561:561:561)) - (PORT datac (201:201:201) (238:238:238)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) + (PORT dataa (1309:1309:1309) (1333:1333:1333)) + (PORT datab (1787:1787:1787) (1911:1911:1911)) + (PORT datac (2047:2047:2047) (2168:2168:2168)) + (PORT datad (1796:1796:1796) (1868:1868:1868)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -18139,97 +15010,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[10\]) + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|d0_out) (DELAY (ABSOLUTE - (PORT datac (200:200:200) (235:235:235)) - (PORT datad (869:869:869) (899:899:899)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|Q\[10\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (531:531:531) (546:546:546)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[10\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1560:1560:1560)) - (PORT ena (2096:2096:2096) (2133:2133:2133)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|carry_borrow_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (270:270:270) (368:368:368)) - (PORT datab (276:276:276) (370:370:370)) - (PORT datac (1338:1338:1338) (1352:1352:1352)) - (PORT datad (324:324:324) (345:345:345)) - (IOPATH dataa combout (301:301:301) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[11\]) - (DELAY - (ABSOLUTE - (PORT datab (602:602:602) (632:632:632)) - (PORT datad (924:924:924) (945:945:945)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[11\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1560:1560:1560)) - (PORT ena (2096:2096:2096) (2133:2133:2133)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[11\]) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (265:265:265)) - (PORT datac (568:568:568) (632:632:632)) + (PORT dataa (965:965:965) (1060:1060:1060)) + (PORT datac (186:186:186) (228:228:228)) (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datac combout (243:243:243) (242:242:242)) ) @@ -18237,12 +15022,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[3\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[1\]) (DELAY (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT clk (1520:1520:1520) (1533:1533:1533)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1308:1308:1308) (1303:1303:1303)) + (PORT ena (1256:1256:1256) (1263:1263:1263)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -18252,13 +15037,481 @@ ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[3\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~5) (DELAY (ABSOLUTE - (PORT clk (1535:1535:1535) (1554:1554:1554)) - (PORT asdata (738:738:738) (772:772:772)) - (PORT ena (935:935:935) (924:924:924)) + (PORT dataa (911:911:911) (984:984:984)) + (PORT datab (1562:1562:1562) (1669:1669:1669)) + (PORT datac (1535:1535:1535) (1633:1633:1633)) + (PORT datad (396:396:396) (445:445:445)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1001:1001:1001) (1101:1101:1101)) + (PORT datab (1208:1208:1208) (1269:1269:1269)) + (PORT datac (1708:1708:1708) (1749:1749:1749)) + (PORT datad (674:674:674) (737:737:737)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~4) + (DELAY + (ABSOLUTE + (PORT dataa (339:339:339) (368:368:368)) + (PORT datab (228:228:228) (270:270:270)) + (PORT datac (690:690:690) (753:753:753)) + (PORT datad (334:334:334) (356:356:356)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1572:1572:1572) (1633:1633:1633)) + (PORT datab (1675:1675:1675) (1753:1753:1753)) + (PORT datac (2438:2438:2438) (2563:2563:2563)) + (PORT datad (1464:1464:1464) (1552:1552:1552)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1187:1187:1187) (1256:1256:1256)) + (PORT datab (1497:1497:1497) (1588:1588:1588)) + (PORT datac (825:825:825) (837:837:837)) + (PORT datad (911:911:911) (933:933:933)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~16) + (DELAY + (ABSOLUTE + (PORT dataa (651:651:651) (689:689:689)) + (PORT datab (923:923:923) (984:984:984)) + (PORT datac (2027:2027:2027) (2074:2074:2074)) + (PORT datad (1269:1269:1269) (1341:1341:1341)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~6) + (DELAY + (ABSOLUTE + (PORT dataa (636:636:636) (702:702:702)) + (PORT datab (199:199:199) (239:239:239)) + (PORT datac (171:171:171) (203:203:203)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~7) + (DELAY + (ABSOLUTE + (PORT dataa (652:652:652) (685:685:685)) + (PORT datab (1497:1497:1497) (1586:1586:1586)) + (PORT datac (215:215:215) (258:258:258)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~10) + (DELAY + (ABSOLUTE + (PORT dataa (2089:2089:2089) (2206:2206:2206)) + (PORT datab (1341:1341:1341) (1346:1346:1346)) + (PORT datac (1430:1430:1430) (1538:1538:1538)) + (PORT datad (844:844:844) (882:882:882)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~8) + (DELAY + (ABSOLUTE + (PORT dataa (223:223:223) (278:278:278)) + (PORT datab (881:881:881) (923:923:923)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (1876:1876:1876) (2029:2029:2029)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel_nop3pla68M3T1_20) + (DELAY + (ABSOLUTE + (PORT dataa (936:936:936) (999:999:999)) + (PORT datab (976:976:976) (1037:1037:1037)) + (PORT datac (1800:1800:1800) (1897:1897:1897)) + (PORT datad (1656:1656:1656) (1724:1724:1724)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~42) + (DELAY + (ABSOLUTE + (PORT datac (586:586:586) (602:602:602)) + (PORT datad (196:196:196) (236:236:236)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~9) + (DELAY + (ABSOLUTE + (PORT dataa (592:592:592) (622:622:622)) + (PORT datab (197:197:197) (237:237:237)) + (PORT datac (901:901:901) (936:936:936)) + (PORT datad (211:211:211) (243:243:243)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~5) + (DELAY + (ABSOLUTE + (PORT dataa (647:647:647) (699:699:699)) + (PORT datab (1906:1906:1906) (1991:1991:1991)) + (PORT datac (1135:1135:1135) (1200:1200:1200)) + (PORT datad (1429:1429:1429) (1503:1503:1503)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~6) + (DELAY + (ABSOLUTE + (PORT dataa (2152:2152:2152) (2228:2228:2228)) + (PORT datab (969:969:969) (1086:1086:1086)) + (PORT datac (1061:1061:1061) (1115:1115:1115)) + (PORT datad (1104:1104:1104) (1170:1170:1170)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~7) + (DELAY + (ABSOLUTE + (PORT dataa (413:413:413) (439:439:439)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (201:201:201) (237:237:237)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1496:1496:1496) (1590:1590:1590)) + (PORT datac (1286:1286:1286) (1347:1347:1347)) + (PORT datad (1899:1899:1899) (2019:2019:2019)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1187:1187:1187) (1240:1240:1240)) + (PORT datab (930:930:930) (999:999:999)) + (PORT datac (1936:1936:1936) (2079:2079:2079)) + (PORT datad (607:607:607) (665:665:665)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (623:623:623) (662:662:662)) + (PORT datab (1100:1100:1100) (1165:1165:1165)) + (PORT datac (813:813:813) (826:826:826)) + (PORT datad (846:846:846) (923:923:923)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~3) + (DELAY + (ABSOLUTE + (PORT dataa (572:572:572) (612:612:612)) + (PORT datab (887:887:887) (950:950:950)) + (PORT datac (784:784:784) (791:791:791)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~2) + (DELAY + (ABSOLUTE + (PORT dataa (418:418:418) (444:444:444)) + (PORT datab (1102:1102:1102) (1162:1162:1162)) + (PORT datac (2128:2128:2128) (2195:2195:2195)) + (PORT datad (814:814:814) (882:882:882)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1125:1125:1125) (1164:1164:1164)) + (PORT datab (1363:1363:1363) (1391:1391:1391)) + (PORT datac (555:555:555) (574:574:574)) + (PORT datad (831:831:831) (848:848:848)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~4) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (241:241:241)) + (PORT datab (196:196:196) (235:235:235)) + (PORT datac (836:836:836) (862:862:862)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~8) + (DELAY + (ABSOLUTE + (PORT dataa (633:633:633) (669:669:669)) + (PORT datab (220:220:220) (259:259:259)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (172:172:172) (198:198:198)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1496:1496:1496) (1590:1590:1590)) + (PORT datab (1937:1937:1937) (2057:2057:2057)) + (PORT datac (1288:1288:1288) (1349:1349:1349)) + (PORT datad (1492:1492:1492) (1552:1552:1552)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~2) + (DELAY + (ABSOLUTE + (PORT datab (630:630:630) (651:651:651)) + (PORT datac (853:853:853) (863:863:863)) + (PORT datad (359:359:359) (379:379:379)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (915:915:915) (927:927:927)) + (PORT datab (1335:1335:1335) (1355:1355:1355)) + (PORT datac (1623:1623:1623) (1740:1740:1740)) + (PORT datad (588:588:588) (591:591:591)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (790:790:790) (782:782:782)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_32) + (DELAY + (ABSOLUTE + (PORT dataa (1526:1526:1526) (1579:1579:1579)) + (PORT datab (2177:2177:2177) (2220:2220:2220)) + (PORT datad (1363:1363:1363) (1385:1385:1385)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1533:1533:1533)) + (PORT asdata (713:713:713) (749:749:749)) + (PORT ena (1227:1227:1227) (1249:1249:1249)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1533:1533:1533)) + (PORT asdata (714:714:714) (748:748:748)) + (PORT ena (1503:1503:1503) (1497:1497:1497)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -18269,14 +15522,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~10) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~81) (DELAY (ABSOLUTE - (PORT dataa (221:221:221) (264:264:264)) - (PORT datab (407:407:407) (446:446:446)) - (PORT datad (388:388:388) (422:422:422)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (702:702:702) (773:773:773)) + (PORT datab (240:240:240) (322:322:322)) + (PORT datad (698:698:698) (750:750:750)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -18284,43 +15537,27 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~11) + (INSTANCE z80_\|alu_\|db_high\[2\]\~8) (DELAY (ABSOLUTE - (PORT dataa (247:247:247) (335:335:335)) - (PORT datac (823:823:823) (870:870:870)) - (PORT datad (639:639:639) (664:664:664)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT datab (872:872:872) (903:903:903)) + (PORT datac (789:789:789) (812:812:812)) + (PORT datad (1182:1182:1182) (1266:1266:1266)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~12) + (INSTANCE z80_\|alu_\|db_high\[2\]\~9) (DELAY (ABSOLUTE - (PORT dataa (565:565:565) (577:577:577)) - (PORT datab (846:846:846) (883:883:883)) - (PORT datac (679:679:679) (728:728:728)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~48) - (DELAY - (ABSOLUTE - (PORT dataa (612:612:612) (644:644:644)) - (PORT datab (820:820:820) (880:880:880)) - (PORT datac (393:393:393) (430:430:430)) - (PORT datad (1301:1301:1301) (1333:1333:1333)) + (PORT dataa (1091:1091:1091) (1112:1112:1112)) + (PORT datab (700:700:700) (753:753:753)) + (PORT datac (173:173:173) (207:207:207)) + (PORT datad (1274:1274:1274) (1296:1296:1296)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -18330,15 +15567,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[3\]\~9) + (INSTANCE z80_\|alu_\|db_high\[2\]\~11) (DELAY (ABSOLUTE - (PORT dataa (872:872:872) (916:916:916)) - (PORT datab (223:223:223) (272:272:272)) - (PORT datac (1159:1159:1159) (1203:1203:1203)) - (PORT datad (607:607:607) (634:634:634)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (331:331:331) (342:342:342)) + (PORT datab (274:274:274) (331:331:331)) + (PORT datac (244:244:244) (308:308:308)) + (PORT datad (250:250:250) (298:298:298)) + (IOPATH datab combout (304:304:304) (311:311:311)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -18346,40 +15581,24 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_low) + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[2\]) (DELAY (ABSOLUTE - (PORT dataa (1004:1004:1004) (1068:1068:1068)) - (PORT datab (2092:2092:2092) (2152:2152:2152)) - (PORT datac (686:686:686) (739:739:739)) - (PORT datad (1737:1737:1737) (1857:1857:1857)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[3\]) - (DELAY - (ABSOLUTE - (PORT datab (964:964:964) (1009:1009:1009)) - (PORT datac (1166:1166:1166) (1163:1163:1163)) - (PORT datad (680:680:680) (717:717:717)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (934:934:934) (963:963:963)) + (PORT datac (620:620:620) (650:650:650)) + (PORT datad (831:831:831) (844:844:844)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_high\[3\]) + (INSTANCE z80_\|alu_\|op1_high\[2\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1531:1531:1531)) + (PORT clk (1547:1547:1547) (1549:1549:1549)) (PORT d (74:74:74) (91:91:91)) (PORT ena (819:819:819) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) @@ -18392,61 +15611,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op1\[3\]\~3) + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_lq) (DELAY (ABSOLUTE - (PORT datab (652:652:652) (711:711:711)) - (PORT datac (647:647:647) (707:707:707)) - (PORT datad (634:634:634) (661:661:661)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_10\~0) - (DELAY - (ABSOLUTE - (PORT dataa (638:638:638) (713:713:713)) - (PORT datab (641:641:641) (708:708:708)) - (PORT datac (193:193:193) (226:226:226)) - (PORT datad (575:575:575) (599:599:599)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1127:1127:1127) (1169:1169:1169)) - (PORT datab (1268:1268:1268) (1379:1379:1379)) - (PORT datac (613:613:613) (634:634:634)) - (PORT datad (1131:1131:1131) (1134:1134:1134)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~10) - (DELAY - (ABSOLUTE - (PORT dataa (2003:2003:2003) (2192:2192:2192)) - (PORT datab (1271:1271:1271) (1346:1346:1346)) - (PORT datac (994:994:994) (1035:1035:1035)) - (PORT datad (1461:1461:1461) (1531:1531:1531)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) + (PORT dataa (1728:1728:1728) (1817:1817:1817)) + (PORT datab (954:954:954) (1011:1011:1011)) + (PORT datac (1674:1674:1674) (1744:1744:1744)) + (PORT datad (1047:1047:1047) (1131:1131:1131)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -18454,15 +15627,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~0) + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[2\]\~2) (DELAY (ABSOLUTE - (PORT dataa (1013:1013:1013) (1048:1048:1048)) - (PORT datab (1598:1598:1598) (1713:1713:1713)) - (PORT datac (1145:1145:1145) (1147:1147:1147)) - (PORT datad (654:654:654) (698:698:698)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) + (PORT datac (612:612:612) (626:626:626)) + (PORT datad (650:650:650) (658:658:658)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -18473,10 +15642,10 @@ (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~5) (DELAY (ABSOLUTE - (PORT dataa (2564:2564:2564) (2702:2702:2702)) - (PORT datab (1558:1558:1558) (1680:1680:1680)) - (PORT datac (866:866:866) (908:908:908)) - (PORT datad (191:191:191) (224:224:224)) + (PORT dataa (1847:1847:1847) (1981:1981:1981)) + (PORT datab (1906:1906:1906) (2025:2025:2025)) + (PORT datac (1061:1061:1061) (1069:1069:1069)) + (PORT datad (345:345:345) (369:369:369)) (IOPATH dataa combout (303:303:303) (299:299:299)) (IOPATH datab combout (304:304:304) (308:308:308)) (IOPATH datac combout (243:243:243) (242:242:242)) @@ -18484,18 +15653,32 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~6) + (DELAY + (ABSOLUTE + (PORT dataa (610:610:610) (653:653:653)) + (PORT datab (1978:1978:1978) (2129:2129:2129)) + (PORT datac (1712:1712:1712) (1753:1753:1753)) + (PORT datad (1105:1105:1105) (1133:1133:1133)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~7) (DELAY (ABSOLUTE - (PORT dataa (385:385:385) (411:411:411)) - (PORT datab (804:804:804) (851:851:851)) - (PORT datac (829:829:829) (862:862:862)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (349:349:349) (384:384:384)) + (PORT datac (196:196:196) (241:241:241)) + (PORT datad (211:211:211) (245:245:245)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -18505,12 +15688,12 @@ (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~8) (DELAY (ABSOLUTE - (PORT dataa (647:647:647) (668:668:668)) - (PORT datab (1164:1164:1164) (1226:1226:1226)) - (PORT datac (562:562:562) (562:562:562)) - (PORT datad (595:595:595) (626:626:626)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) + (PORT dataa (866:866:866) (890:890:890)) + (PORT datab (219:219:219) (258:258:258)) + (PORT datac (531:531:531) (544:544:544)) + (PORT datad (1010:1010:1010) (1067:1067:1067)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -18518,29 +15701,33 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[1\]\~5) + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_zero) (DELAY (ABSOLUTE - (PORT dataa (588:588:588) (616:616:616)) - (PORT datab (1125:1125:1125) (1173:1173:1173)) - (PORT datac (561:561:561) (579:579:579)) - (PORT datad (905:905:905) (952:952:952)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (794:794:794) (844:844:844)) + (PORT datab (658:658:658) (689:689:689)) + (PORT datac (823:823:823) (867:867:867)) + (PORT datad (564:564:564) (578:578:578)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[1\]\~6) + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[2\]\~3) (DELAY (ABSOLUTE - (PORT dataa (258:258:258) (332:332:332)) - (PORT datac (170:170:170) (202:202:202)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (899:899:899) (923:923:923)) + (PORT datac (928:928:928) (953:953:953)) + (PORT datad (866:866:866) (900:900:900)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -18549,10 +15736,1862 @@ (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|ena) (DELAY (ABSOLUTE - (PORT dataa (263:263:263) (339:339:339)) - (PORT datac (1090:1090:1090) (1144:1144:1144)) - (PORT datad (902:902:902) (951:951:951)) + (PORT dataa (652:652:652) (673:673:673)) + (PORT datab (912:912:912) (940:940:940)) + (PORT datac (936:936:936) (955:955:955)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_high\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1535:1535:1535) (1540:1540:1540)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[2\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (604:604:604) (673:673:673)) + (PORT datab (703:703:703) (722:722:722)) + (PORT datac (623:623:623) (644:644:644)) + (PORT datad (657:657:657) (722:722:722)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[2\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (619:619:619) (669:669:669)) + (PORT datab (1147:1147:1147) (1159:1159:1159)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (321:321:321) (342:342:342)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~1) + (DELAY + (ABSOLUTE + (PORT datab (696:696:696) (745:745:745)) + (PORT datad (646:646:646) (669:669:669)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[2\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (874:874:874) (936:936:936)) + (PORT datab (602:602:602) (632:632:632)) + (PORT datac (342:342:342) (366:366:366)) + (PORT datad (623:623:623) (654:654:654)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT asdata (936:936:936) (967:967:967)) + (PORT ena (790:790:790) (782:782:782)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT asdata (938:938:938) (970:970:970)) + (PORT ena (1288:1288:1288) (1306:1306:1306)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~78) + (DELAY + (ABSOLUTE + (PORT dataa (663:663:663) (748:748:748)) + (PORT datab (241:241:241) (323:323:323)) + (PORT datad (232:232:232) (273:273:273)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_78\~0) + (DELAY + (ABSOLUTE + (PORT dataa (890:890:890) (908:908:908)) + (PORT datab (753:753:753) (817:817:817)) + (PORT datac (632:632:632) (680:680:680)) + (PORT datad (940:940:940) (969:969:969)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT asdata (537:537:537) (568:568:568)) + (PORT ena (1438:1438:1438) (1476:1476:1476)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~79) + (DELAY + (ABSOLUTE + (PORT dataa (701:701:701) (767:767:767)) + (PORT datab (860:860:860) (879:879:879)) + (PORT datad (1349:1349:1349) (1339:1339:1339)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_34) + (DELAY + (ABSOLUTE + (PORT dataa (1003:1003:1003) (1065:1065:1065)) + (PORT datac (1584:1584:1584) (1603:1603:1603)) + (PORT datad (1140:1140:1140) (1176:1176:1176)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (877:877:877) (903:903:903)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_35) + (DELAY + (ABSOLUTE + (PORT dataa (1009:1009:1009) (1067:1067:1067)) + (PORT datac (1587:1587:1587) (1605:1605:1605)) + (PORT datad (1143:1143:1143) (1178:1178:1178)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (812:812:812) (804:804:804)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_31) + (DELAY + (ABSOLUTE + (PORT dataa (1005:1005:1005) (1065:1065:1065)) + (PORT datab (1168:1168:1168) (1214:1214:1214)) + (PORT datac (794:794:794) (826:826:826)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT asdata (1225:1225:1225) (1251:1251:1251)) + (PORT ena (841:841:841) (846:846:846)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_30) + (DELAY + (ABSOLUTE + (PORT dataa (1000:1000:1000) (1056:1056:1056)) + (PORT datab (1168:1168:1168) (1209:1209:1209)) + (PORT datac (795:795:795) (824:824:824)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~75) + (DELAY + (ABSOLUTE + (PORT dataa (230:230:230) (279:279:279)) + (PORT datab (242:242:242) (324:324:324)) + (PORT datad (202:202:202) (231:231:231)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (632:632:632) (663:663:663)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1220:1220:1220) (1212:1212:1212)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT asdata (1168:1168:1168) (1193:1193:1193)) + (PORT ena (1200:1200:1200) (1188:1188:1188)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~76) + (DELAY + (ABSOLUTE + (PORT dataa (855:855:855) (927:927:927)) + (PORT datab (241:241:241) (323:323:323)) + (PORT datad (662:662:662) (728:728:728)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1535:1535:1535)) + (PORT asdata (964:964:964) (1000:1000:1000)) + (PORT ena (1274:1274:1274) (1265:1265:1265)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~77) + (DELAY + (ABSOLUTE + (PORT dataa (383:383:383) (407:407:407)) + (PORT datad (923:923:923) (952:952:952)) (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~80) + (DELAY + (ABSOLUTE + (PORT dataa (557:557:557) (571:571:571)) + (PORT datab (523:523:523) (537:537:537)) + (PORT datac (774:774:774) (767:767:767)) + (PORT datad (829:829:829) (841:841:841)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1535:1535:1535)) + (PORT asdata (925:925:925) (956:956:956)) + (PORT ena (975:975:975) (963:963:963)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1535:1535:1535)) + (PORT asdata (925:925:925) (955:955:955)) + (PORT ena (1008:1008:1008) (1010:1010:1010)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~74) + (DELAY + (ABSOLUTE + (PORT dataa (376:376:376) (418:418:418)) + (PORT datab (239:239:239) (321:321:321)) + (PORT datad (368:368:368) (391:391:391)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1550:1550:1550)) + (PORT asdata (1170:1170:1170) (1200:1200:1200)) + (PORT ena (811:811:811) (804:804:804)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1550:1550:1550)) + (PORT asdata (1170:1170:1170) (1200:1200:1200)) + (PORT ena (842:842:842) (856:856:856)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~73) + (DELAY + (ABSOLUTE + (PORT dataa (243:243:243) (330:330:330)) + (PORT datab (237:237:237) (282:282:282)) + (PORT datad (211:211:211) (243:243:243)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~81) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (242:242:242)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datad (609:609:609) (620:620:620)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1132:1132:1132) (1169:1169:1169)) + (PORT datab (656:656:656) (710:710:710)) + (PORT datac (625:625:625) (675:675:675)) + (PORT datad (1350:1350:1350) (1340:1340:1340)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (681:681:681) (698:698:698)) + (PORT datab (640:640:640) (663:663:663)) + (PORT datac (665:665:665) (728:728:728)) + (PORT datad (1170:1170:1170) (1177:1177:1177)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (413:413:413) (443:443:443)) + (PORT datab (196:196:196) (235:235:235)) + (PORT datac (606:606:606) (655:655:655)) + (PORT datad (173:173:173) (197:197:197)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~92) + (DELAY + (ABSOLUTE + (PORT dataa (925:925:925) (979:979:979)) + (PORT datab (664:664:664) (723:723:723)) + (PORT datac (614:614:614) (668:668:668)) + (PORT datad (592:592:592) (635:635:635)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (406:406:406) (454:454:454)) + (PORT datab (439:439:439) (469:469:469)) + (PORT datac (601:601:601) (622:622:622)) + (PORT datad (582:582:582) (592:592:592)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_74) + (DELAY + (ABSOLUTE + (PORT dataa (1043:1043:1043) (1067:1067:1067)) + (PORT datac (1149:1149:1149) (1189:1189:1189)) + (PORT datad (874:874:874) (911:911:911)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_62) + (DELAY + (ABSOLUTE + (PORT datab (901:901:901) (951:951:951)) + (PORT datac (1148:1148:1148) (1189:1189:1189)) + (PORT datad (798:798:798) (802:802:802)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (448:448:448) (491:491:491)) + (PORT datab (1064:1064:1064) (1078:1078:1078)) + (PORT datac (1615:1615:1615) (1630:1630:1630)) + (PORT datad (615:615:615) (638:638:638)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1231:1231:1231) (1237:1237:1237)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT asdata (732:732:732) (765:765:765)) + (PORT ena (790:790:790) (782:782:782)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT asdata (536:536:536) (566:566:566)) + (PORT ena (1438:1438:1438) (1476:1476:1476)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~55) + (DELAY + (ABSOLUTE + (PORT dataa (258:258:258) (314:314:314)) + (PORT datab (632:632:632) (696:696:696)) + (PORT datad (362:362:362) (421:421:421)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT asdata (735:735:735) (766:766:766)) + (PORT ena (1288:1288:1288) (1306:1306:1306)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~56) + (DELAY + (ABSOLUTE + (PORT datab (198:198:198) (236:236:236)) + (PORT datad (639:639:639) (700:700:700)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT asdata (912:912:912) (932:932:932)) + (PORT ena (981:981:981) (980:980:980)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT asdata (911:911:911) (930:930:930)) + (PORT ena (811:811:811) (804:804:804)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~57) + (DELAY + (ABSOLUTE + (PORT dataa (244:244:244) (330:330:330)) + (PORT datab (253:253:253) (303:303:303)) + (PORT datad (229:229:229) (266:266:266)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT asdata (1017:1017:1017) (1036:1036:1036)) + (PORT ena (1220:1220:1220) (1212:1212:1212)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT asdata (1017:1017:1017) (1039:1039:1039)) + (PORT ena (1200:1200:1200) (1188:1188:1188)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~59) + (DELAY + (ABSOLUTE + (PORT dataa (863:863:863) (935:935:935)) + (PORT datab (241:241:241) (324:324:324)) + (PORT datad (658:658:658) (724:724:724)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT asdata (1040:1040:1040) (1065:1065:1065)) + (PORT ena (812:812:812) (804:804:804)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT asdata (1041:1041:1041) (1066:1066:1066)) + (PORT ena (841:841:841) (846:846:846)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~58) + (DELAY + (ABSOLUTE + (PORT dataa (231:231:231) (280:280:280)) + (PORT datab (241:241:241) (323:323:323)) + (PORT datad (201:201:201) (228:228:228)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1535:1535:1535)) + (PORT asdata (1414:1414:1414) (1418:1418:1418)) + (PORT ena (1274:1274:1274) (1265:1265:1265)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~60) + (DELAY + (ABSOLUTE + (PORT dataa (636:636:636) (656:656:656)) + (PORT datab (336:336:336) (365:365:365)) + (PORT datad (930:930:930) (955:955:955)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1549:1549:1549)) + (PORT asdata (1181:1181:1181) (1187:1187:1187)) + (PORT ena (974:974:974) (969:969:969)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1549:1549:1549)) + (PORT asdata (1182:1182:1182) (1188:1188:1188)) + (PORT ena (975:975:975) (970:970:970)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~53) + (DELAY + (ABSOLUTE + (PORT dataa (409:409:409) (451:451:451)) + (PORT datab (434:434:434) (466:466:466)) + (PORT datad (216:216:216) (284:284:284)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~54) + (DELAY + (ABSOLUTE + (PORT dataa (865:865:865) (894:894:894)) + (PORT datac (905:905:905) (908:908:908)) + (PORT datad (845:845:845) (879:879:879)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~61) + (DELAY + (ABSOLUTE + (PORT dataa (635:635:635) (651:651:651)) + (PORT datab (615:615:615) (639:639:639)) + (PORT datac (345:345:345) (369:369:369)) + (PORT datad (341:341:341) (361:361:361)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~62) + (DELAY + (ABSOLUTE + (PORT dataa (633:633:633) (650:650:650)) + (PORT datab (664:664:664) (693:693:693)) + (PORT datac (1100:1100:1100) (1130:1130:1130)) + (PORT datad (624:624:624) (647:647:647)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_75) + (DELAY + (ABSOLUTE + (PORT dataa (1041:1041:1041) (1071:1071:1071)) + (PORT datac (1149:1149:1149) (1187:1187:1187)) + (PORT datad (874:874:874) (906:906:906)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (672:672:672) (693:693:693)) + (PORT ena (1200:1200:1200) (1181:1181:1181)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (893:893:893) (938:938:938)) + (PORT datab (677:677:677) (714:714:714)) + (PORT datad (402:402:402) (437:437:437)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (245:245:245) (332:332:332)) + (PORT datab (198:198:198) (238:238:238)) + (PORT datad (613:613:613) (638:638:638)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_4\|d0_out) + (DELAY + (ABSOLUTE + (PORT datac (931:931:931) (1001:1001:1001)) + (PORT datad (599:599:599) (611:611:611)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1647:1647:1647) (1678:1678:1678)) + (PORT datab (198:198:198) (238:238:238)) + (PORT datac (576:576:576) (590:590:590)) + (PORT datad (351:351:351) (383:383:383)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[4\]) + (DELAY + (ABSOLUTE + (PORT datab (942:942:942) (968:968:968)) + (PORT datad (940:940:940) (982:982:982)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1560:1560:1560) (1542:1542:1542)) + (PORT ena (1949:1949:1949) (1917:1917:1917)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_4\|d1_out) + (DELAY + (ABSOLUTE + (PORT dataa (1126:1126:1126) (1148:1148:1148)) + (PORT datab (960:960:960) (1034:1034:1034)) + (PORT datac (913:913:913) (1000:1000:1000)) + (PORT datad (599:599:599) (612:612:612)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (985:985:985) (993:993:993)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT asdata (1770:1770:1770) (1777:1777:1777)) + (PORT ena (981:981:981) (980:980:980)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT asdata (1769:1769:1769) (1776:1776:1776)) + (PORT ena (811:811:811) (804:804:804)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~64) + (DELAY + (ABSOLUTE + (PORT dataa (385:385:385) (457:457:457)) + (PORT datab (253:253:253) (304:304:304)) + (PORT datad (230:230:230) (269:269:269)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1549:1549:1549)) + (PORT asdata (1221:1221:1221) (1232:1232:1232)) + (PORT ena (974:974:974) (969:969:969)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1549:1549:1549)) + (PORT asdata (1221:1221:1221) (1232:1232:1232)) + (PORT ena (975:975:975) (970:970:970)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~63) + (DELAY + (ABSOLUTE + (PORT dataa (406:406:406) (455:455:455)) + (PORT datab (435:435:435) (464:464:464)) + (PORT datad (215:215:215) (283:283:283)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1549:1549:1549)) + (PORT asdata (1759:1759:1759) (1781:1781:1781)) + (PORT ena (1240:1240:1240) (1231:1231:1231)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (849:849:849) (862:862:862)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1549:1549:1549)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1207:1207:1207) (1180:1180:1180)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~65) + (DELAY + (ABSOLUTE + (PORT dataa (698:698:698) (740:740:740)) + (PORT datab (706:706:706) (731:731:731)) + (PORT datad (217:217:217) (285:285:285)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (790:790:790) (782:782:782)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT asdata (1725:1725:1725) (1719:1719:1719)) + (PORT ena (1438:1438:1438) (1476:1476:1476)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~69) + (DELAY + (ABSOLUTE + (PORT dataa (697:697:697) (765:765:765)) + (PORT datab (617:617:617) (679:679:679)) + (PORT datad (374:374:374) (394:394:394)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1535:1535:1535)) + (PORT asdata (1502:1502:1502) (1512:1512:1512)) + (PORT ena (1243:1243:1243) (1246:1246:1246)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT asdata (2035:2035:2035) (2028:2028:2028)) + (PORT ena (1220:1220:1220) (1212:1212:1212)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~68) + (DELAY + (ABSOLUTE + (PORT dataa (636:636:636) (696:696:696)) + (PORT datab (681:681:681) (741:741:741)) + (PORT datad (662:662:662) (728:728:728)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1535:1535:1535)) + (PORT asdata (1504:1504:1504) (1515:1515:1515)) + (PORT ena (1274:1274:1274) (1265:1265:1265)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT asdata (2034:2034:2034) (2029:2029:2029)) + (PORT ena (1200:1200:1200) (1188:1188:1188)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~66) + (DELAY + (ABSOLUTE + (PORT dataa (862:862:862) (933:933:933)) + (PORT datab (587:587:587) (614:614:614)) + (PORT datad (555:555:555) (569:569:569)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~67) + (DELAY + (ABSOLUTE + (PORT datab (958:958:958) (995:995:995)) + (PORT datad (601:601:601) (616:616:616)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~70) + (DELAY + (ABSOLUTE + (PORT dataa (641:641:641) (660:660:660)) + (PORT datab (671:671:671) (687:687:687)) + (PORT datac (602:602:602) (610:610:610)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~71) + (DELAY + (ABSOLUTE + (PORT dataa (337:337:337) (369:369:369)) + (PORT datab (635:635:635) (653:653:653)) + (PORT datad (595:595:595) (608:608:608)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~72) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (826:826:826) (846:846:846)) + (PORT datac (631:631:631) (652:652:652)) + (PORT datad (832:832:832) (865:865:865)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (913:913:913) (926:926:926)) + (PORT ena (971:971:971) (959:959:959)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[5\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1444:1444:1444) (1471:1471:1471)) + (PORT datab (1050:1050:1050) (1065:1065:1065)) + (PORT datad (561:561:561) (573:573:573)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[5\]\~17) + (DELAY + (ABSOLUTE + (PORT datab (243:243:243) (325:325:325)) + (PORT datac (334:334:334) (359:359:359)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[5\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (579:579:579) (605:605:605)) + (PORT datab (219:219:219) (258:258:258)) + (PORT datac (171:171:171) (205:205:205)) + (PORT datad (1832:1832:1832) (1823:1823:1823)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[5\]) + (DELAY + (ABSOLUTE + (PORT datab (896:896:896) (918:918:918)) + (PORT datad (941:941:941) (978:978:978)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1560:1560:1560) (1542:1542:1542)) + (PORT ena (1949:1949:1949) (1917:1917:1917)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~10) + (DELAY + (ABSOLUTE + (PORT datac (1275:1275:1275) (1291:1291:1291)) + (PORT datad (1798:1798:1798) (1868:1868:1868)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_43\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1011:1011:1011) (1080:1080:1080)) + (PORT datab (1788:1788:1788) (1913:1913:1913)) + (PORT datac (211:211:211) (256:256:256)) + (PORT datad (1858:1858:1858) (1988:1988:1988)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_44) + (DELAY + (ABSOLUTE + (PORT dataa (1893:1893:1893) (2029:2029:2029)) + (PORT datab (1787:1787:1787) (1908:1908:1908)) + (PORT datac (208:208:208) (257:257:257)) + (PORT datad (1226:1226:1226) (1279:1279:1279)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[6\]) + (DELAY + (ABSOLUTE + (PORT datac (872:872:872) (895:895:895)) + (PORT datad (939:939:939) (981:981:981)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1560:1560:1560) (1542:1542:1542)) + (PORT ena (1949:1949:1949) (1917:1917:1917)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[6\]) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (255:255:255)) + (PORT datab (208:208:208) (250:250:250)) + (PORT datac (942:942:942) (988:988:988)) + (PORT datad (204:204:204) (234:234:234)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (985:985:985) (993:993:993)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (672:672:672) (694:694:694)) + (PORT ena (971:971:971) (959:959:959)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (643:643:643) (697:697:697)) + (PORT datab (1050:1050:1050) (1068:1068:1068)) + (PORT datad (561:561:561) (576:576:576)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~20) + (DELAY + (ABSOLUTE + (PORT datab (242:242:242) (324:324:324)) + (PORT datac (336:336:336) (359:359:359)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (579:579:579) (604:604:604)) + (PORT datab (860:860:860) (862:862:862)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (1832:1832:1832) (1822:1822:1822)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~82) + (DELAY + (ABSOLUTE + (PORT dataa (1133:1133:1133) (1169:1169:1169)) + (PORT datab (605:605:605) (614:614:614)) + (PORT datac (635:635:635) (662:662:662)) + (PORT datad (634:634:634) (651:651:651)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_ds\[6\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (821:821:821) (854:854:854)) + (PORT datab (1116:1116:1116) (1154:1154:1154)) + (PORT datac (650:650:650) (678:678:678)) + (PORT datad (863:863:863) (906:906:906)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sw1_\|db_down\[6\]\~1) + (DELAY + (ABSOLUTE + (PORT datab (654:654:654) (671:671:671)) + (PORT datac (404:404:404) (449:449:449)) + (PORT datad (833:833:833) (842:842:842)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_66_oe) + (DELAY + (ABSOLUTE + (PORT dataa (2284:2284:2284) (2429:2429:2429)) + (PORT datab (1247:1247:1247) (1332:1332:1332)) + (PORT datac (597:597:597) (660:660:660)) + (PORT datad (1623:1623:1623) (1693:1693:1693)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[1\]) + (DELAY + (ABSOLUTE + (PORT dataa (947:947:947) (979:979:979)) + (PORT datac (895:895:895) (917:917:917)) + (PORT datad (616:616:616) (641:641:641)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_high\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1547:1547:1547) (1549:1549:1549)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[1\]\~4) + (DELAY + (ABSOLUTE + (PORT datab (656:656:656) (697:697:697)) + (PORT datac (612:612:612) (626:626:626)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[1\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (965:965:965) (988:988:988)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (629:629:629) (647:647:647)) + (PORT datad (866:866:866) (896:896:896)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -18563,7 +17602,7 @@ (INSTANCE z80_\|alu_\|op2_high\[1\]) (DELAY (ABSOLUTE - (PORT clk (1529:1529:1529) (1531:1531:1531)) + (PORT clk (1535:1535:1535) (1540:1540:1540)) (PORT d (74:74:74) (91:91:91)) (PORT ena (819:819:819) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) @@ -18576,72 +17615,42 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[1\]) + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[1\]\~2) (DELAY (ABSOLUTE - (PORT datab (968:968:968) (1010:1010:1010)) - (PORT datac (370:370:370) (404:404:404)) - (PORT datad (675:675:675) (715:715:715)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_high\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[1\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (676:676:676) (733:733:733)) - (PORT datab (1128:1128:1128) (1182:1182:1182)) - (PORT datac (588:588:588) (620:620:620)) - (PORT datad (380:380:380) (439:439:439)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[1\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (264:264:264) (340:340:340)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (556:556:556) (578:578:578)) - (PORT datad (900:900:900) (949:949:949)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) + (PORT dataa (650:650:650) (672:672:672)) + (PORT datab (717:717:717) (776:776:776)) + (PORT datac (1098:1098:1098) (1129:1129:1129)) + (PORT datad (1110:1110:1110) (1144:1144:1144)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[1\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (965:965:965) (991:991:991)) + (PORT datab (908:908:908) (935:935:935)) + (PORT datac (629:629:629) (666:666:666)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|alu_\|op2_low\[1\]) (DELAY (ABSOLUTE - (PORT clk (1529:1529:1529) (1531:1531:1531)) + (PORT clk (1535:1535:1535) (1540:1540:1540)) (PORT d (74:74:74) (91:91:91)) (PORT ena (819:819:819) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) @@ -18652,991 +17661,16 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1468:1468:1468) (1479:1479:1479)) - (PORT datab (1497:1497:1497) (1572:1572:1572)) - (PORT datac (1847:1847:1847) (1915:1915:1915)) - (PORT datad (402:402:402) (438:438:438)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~20) - (DELAY - (ABSOLUTE - (PORT dataa (1433:1433:1433) (1518:1518:1518)) - (PORT datab (1643:1643:1643) (1769:1769:1769)) - (PORT datac (1052:1052:1052) (1102:1102:1102)) - (PORT datad (1294:1294:1294) (1385:1385:1385)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~12) - (DELAY - (ABSOLUTE - (PORT dataa (885:885:885) (898:898:898)) - (PORT datab (943:943:943) (983:983:983)) - (PORT datac (858:858:858) (877:877:877)) - (PORT datad (654:654:654) (664:664:664)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~18) - (DELAY - (ABSOLUTE - (PORT dataa (480:480:480) (518:518:518)) - (PORT datab (1187:1187:1187) (1249:1249:1249)) - (PORT datac (925:925:925) (1011:1011:1011)) - (PORT datad (1383:1383:1383) (1482:1482:1482)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal61\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1746:1746:1746) (1869:1869:1869)) - (PORT datab (1375:1375:1375) (1426:1426:1426)) - (PORT datac (1591:1591:1591) (1672:1672:1672)) - (PORT datad (1495:1495:1495) (1627:1627:1627)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~16) - (DELAY - (ABSOLUTE - (PORT datab (1828:1828:1828) (1926:1926:1926)) - (PORT datac (1699:1699:1699) (1792:1792:1792)) - (PORT datad (926:926:926) (994:994:994)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1872:1872:1872) (1889:1889:1889)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (880:880:880) (886:886:886)) - (PORT datad (803:803:803) (814:814:814)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1342:1342:1342) (1440:1440:1440)) - (PORT datab (1765:1765:1765) (1873:1873:1873)) - (PORT datac (1447:1447:1447) (1536:1536:1536)) - (PORT datad (195:195:195) (220:220:220)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1520:1520:1520) (1609:1609:1609)) - (PORT datab (925:925:925) (988:988:988)) - (PORT datac (193:193:193) (226:226:226)) - (PORT datad (203:203:203) (232:232:232)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~12) - (DELAY - (ABSOLUTE - (PORT dataa (219:219:219) (262:262:262)) - (PORT datab (207:207:207) (249:249:249)) - (PORT datac (177:177:177) (214:214:214)) - (PORT datad (182:182:182) (212:212:212)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~22) - (DELAY - (ABSOLUTE - (PORT dataa (1766:1766:1766) (1808:1808:1808)) - (PORT datab (836:836:836) (862:862:862)) - (PORT datac (1306:1306:1306) (1421:1421:1421)) - (PORT datad (2555:2555:2555) (2677:2677:2677)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~20) - (DELAY - (ABSOLUTE - (PORT dataa (582:582:582) (614:614:614)) - (PORT datab (246:246:246) (286:286:286)) - (PORT datac (221:221:221) (257:257:257)) - (PORT datad (904:904:904) (976:976:976)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1051:1051:1051) (1075:1075:1075)) - (PORT datab (1615:1615:1615) (1655:1655:1655)) - (PORT datac (1187:1187:1187) (1227:1227:1227)) - (PORT datad (1742:1742:1742) (1769:1769:1769)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal71\~2) - (DELAY - (ABSOLUTE - (PORT dataa (861:861:861) (921:921:921)) - (PORT datab (941:941:941) (1014:1014:1014)) - (PORT datac (219:219:219) (254:254:254)) - (PORT datad (903:903:903) (974:974:974)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~8) - (DELAY - (ABSOLUTE - (PORT dataa (209:209:209) (258:258:258)) - (PORT datab (220:220:220) (259:259:259)) - (PORT datac (201:201:201) (238:238:238)) - (PORT datad (182:182:182) (211:211:211)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~31) - (DELAY - (ABSOLUTE - (PORT dataa (1219:1219:1219) (1272:1272:1272)) - (PORT datab (227:227:227) (268:268:268)) - (PORT datac (2061:2061:2061) (2171:2171:2171)) - (PORT datad (1409:1409:1409) (1503:1503:1503)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~4) - (DELAY - (ABSOLUTE - (PORT dataa (697:697:697) (718:718:718)) - (PORT datab (1484:1484:1484) (1542:1542:1542)) - (PORT datac (1486:1486:1486) (1511:1511:1511)) - (PORT datad (640:640:640) (654:654:654)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla25M1T1_3) - (DELAY - (ABSOLUTE - (PORT dataa (837:837:837) (857:857:857)) - (PORT datab (1485:1485:1485) (1542:1542:1542)) - (PORT datac (1608:1608:1608) (1613:1613:1613)) - (PORT datad (1444:1444:1444) (1563:1563:1563)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~5) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (213:213:213) (257:257:257)) - (PORT datac (838:838:838) (870:870:870)) - (PORT datad (195:195:195) (220:220:220)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~6) - (DELAY - (ABSOLUTE - (PORT dataa (222:222:222) (266:266:266)) - (PORT datab (221:221:221) (260:260:260)) - (PORT datac (1070:1070:1070) (1092:1092:1092)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal72\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1402:1402:1402) (1477:1477:1477)) - (PORT datab (2359:2359:2359) (2492:2492:2492)) - (PORT datac (1132:1132:1132) (1171:1171:1171)) - (PORT datad (855:855:855) (857:857:857)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal73\~2) - (DELAY - (ABSOLUTE - (PORT dataa (2002:2002:2002) (2149:2149:2149)) - (PORT datab (1120:1120:1120) (1189:1189:1189)) - (PORT datac (1350:1350:1350) (1403:1403:1403)) - (PORT datad (855:855:855) (872:872:872)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~0) - (DELAY - (ABSOLUTE - (PORT dataa (975:975:975) (1049:1049:1049)) - (PORT datab (960:960:960) (1047:1047:1047)) - (PORT datac (1782:1782:1782) (1803:1803:1803)) - (PORT datad (1450:1450:1450) (1533:1533:1533)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1044:1044:1044) (1059:1059:1059)) - (PORT datab (197:197:197) (237:237:237)) - (PORT datac (616:616:616) (640:640:640)) - (PORT datad (601:601:601) (613:613:613)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1518:1518:1518) (1586:1586:1586)) - (PORT datab (1962:1962:1962) (1991:1991:1991)) - (PORT datac (1263:1263:1263) (1313:1313:1313)) - (PORT datad (933:933:933) (1002:1002:1002)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~3) - (DELAY - (ABSOLUTE - (PORT datab (864:864:864) (893:893:893)) - (PORT datac (819:819:819) (853:853:853)) - (PORT datad (811:811:811) (845:845:845)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (2565:2565:2565) (2704:2704:2704)) - (PORT datac (1529:1529:1529) (1648:1648:1648)) - (PORT datad (1533:1533:1533) (1667:1667:1667)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (248:248:248) (304:304:304)) - (PORT datab (199:199:199) (237:237:237)) - (PORT datac (1176:1176:1176) (1212:1212:1212)) - (PORT datad (191:191:191) (224:224:224)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (808:808:808) (859:859:859)) - (PORT datab (618:618:618) (647:647:647)) - (PORT datac (171:171:171) (205:205:205)) - (PORT datad (802:802:802) (881:881:881)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~15) - (DELAY - (ABSOLUTE - (PORT dataa (915:915:915) (957:957:957)) - (PORT datac (824:824:824) (856:856:856)) - (PORT datad (647:647:647) (680:680:680)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~16) - (DELAY - (ABSOLUTE - (PORT dataa (912:912:912) (960:960:960)) - (PORT datab (362:362:362) (394:394:394)) - (PORT datac (591:591:591) (619:619:619)) - (PORT datad (338:338:338) (357:357:357)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~6) - (DELAY - (ABSOLUTE - (PORT datac (891:891:891) (933:933:933)) - (PORT datad (831:831:831) (843:843:843)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~7) - (DELAY - (ABSOLUTE - (PORT dataa (634:634:634) (649:649:649)) - (PORT datab (1105:1105:1105) (1114:1114:1114)) - (PORT datac (753:753:753) (781:781:781)) - (PORT datad (613:613:613) (631:631:631)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (917:917:917) (942:942:942)) - (PORT datab (207:207:207) (249:249:249)) - (PORT datad (195:195:195) (221:221:221)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel_pla12M1T1_12\~0) - (DELAY - (ABSOLUTE - (PORT dataa (2002:2002:2002) (2062:2062:2062)) - (PORT datab (228:228:228) (270:270:270)) - (PORT datac (1707:1707:1707) (1823:1823:1823)) - (PORT datad (1505:1505:1505) (1539:1539:1539)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1137:1137:1137) (1211:1211:1211)) - (PORT datab (1568:1568:1568) (1705:1705:1705)) - (PORT datac (2532:2532:2532) (2663:2663:2663)) - (PORT datad (189:189:189) (222:222:222)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1005:1005:1005) (1063:1063:1063)) - (PORT datab (1299:1299:1299) (1349:1349:1349)) - (PORT datac (890:890:890) (914:914:914)) - (PORT datad (180:180:180) (209:209:209)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~8) - (DELAY - (ABSOLUTE - (PORT dataa (640:640:640) (665:665:665)) - (PORT datab (2303:2303:2303) (2383:2383:2383)) - (PORT datac (2057:2057:2057) (2199:2199:2199)) - (PORT datad (1163:1163:1163) (1186:1186:1186)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~8) - (DELAY - (ABSOLUTE - (PORT dataa (618:618:618) (640:640:640)) - (PORT datab (608:608:608) (638:638:638)) - (PORT datac (549:549:549) (557:557:557)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1025:1025:1025) (1068:1068:1068)) - (PORT datab (2030:2030:2030) (2166:2166:2166)) - (PORT datac (821:821:821) (831:831:831)) - (PORT datad (2503:2503:2503) (2629:2629:2629)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1546:1546:1546) (1624:1624:1624)) - (PORT datab (938:938:938) (1017:1017:1017)) - (PORT datac (601:601:601) (662:662:662)) - (PORT datad (580:580:580) (585:585:585)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~13) - (DELAY - (ABSOLUTE - (PORT dataa (845:845:845) (920:920:920)) - (PORT datab (220:220:220) (258:258:258)) - (PORT datac (666:666:666) (685:685:685)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~14) - (DELAY - (ABSOLUTE - (PORT dataa (658:658:658) (680:680:680)) - (PORT datab (1172:1172:1172) (1198:1198:1198)) - (PORT datac (636:636:636) (693:693:693)) - (PORT datad (307:307:307) (324:324:324)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~15) - (DELAY - (ABSOLUTE - (PORT dataa (651:651:651) (694:694:694)) - (PORT datab (806:806:806) (876:876:876)) - (PORT datac (1101:1101:1101) (1130:1130:1130)) - (PORT datad (589:589:589) (627:627:627)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_nop3pla68M1T3_2) - (DELAY - (ABSOLUTE - (PORT dataa (625:625:625) (667:667:667)) - (PORT datab (654:654:654) (679:679:679)) - (PORT datac (936:936:936) (1033:1033:1033)) - (PORT datad (830:830:830) (861:861:861)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1518:1518:1518) (1588:1588:1588)) - (PORT datab (1051:1051:1051) (1075:1075:1075)) - (PORT datac (1263:1263:1263) (1316:1316:1316)) - (PORT datad (930:930:930) (999:999:999)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1452:1452:1452) (1482:1482:1482)) - (PORT datab (1142:1142:1142) (1181:1181:1181)) - (PORT datac (1196:1196:1196) (1287:1287:1287)) - (PORT datad (1139:1139:1139) (1160:1160:1160)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~1) - (DELAY - (ABSOLUTE - (PORT dataa (631:631:631) (646:646:646)) - (PORT datab (1014:1014:1014) (1076:1076:1076)) - (PORT datac (798:798:798) (807:807:807)) - (PORT datad (619:619:619) (632:632:632)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~2) - (DELAY - (ABSOLUTE - (PORT dataa (230:230:230) (276:276:276)) - (PORT datab (1030:1030:1030) (1067:1067:1067)) - (PORT datac (871:871:871) (866:866:866)) - (PORT datad (599:599:599) (614:614:614)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~7) - (DELAY - (ABSOLUTE - (PORT dataa (583:583:583) (619:619:619)) - (PORT datab (225:225:225) (273:273:273)) - (PORT datac (824:824:824) (846:846:846)) - (PORT datad (1377:1377:1377) (1491:1491:1491)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~9) - (DELAY - (ABSOLUTE - (PORT dataa (780:780:780) (837:837:837)) - (PORT datab (827:827:827) (864:864:864)) - (PORT datac (762:762:762) (835:835:835)) - (PORT datad (767:767:767) (810:810:810)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~10) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf) - (DELAY - (ABSOLUTE - (PORT clk (1511:1511:1511) (1525:1525:1525)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1230:1230:1230) (1277:1277:1277)) - (PORT datab (699:699:699) (755:755:755)) - (PORT datac (917:917:917) (964:964:964)) - (PORT datad (1070:1070:1070) (1101:1101:1101)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel_nop3pla68M3T1_20) - (DELAY - (ABSOLUTE - (PORT dataa (625:625:625) (667:667:667)) - (PORT datab (653:653:653) (673:673:673)) - (PORT datac (935:935:935) (1036:1036:1036)) - (PORT datad (387:387:387) (408:408:408)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~10) - (DELAY - (ABSOLUTE - (PORT dataa (971:971:971) (1042:1042:1042)) - (PORT datab (1807:1807:1807) (1835:1835:1835)) - (PORT datac (1262:1262:1262) (1315:1315:1315)) - (PORT datad (1069:1069:1069) (1081:1081:1081)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~8) - (DELAY - (ABSOLUTE - (PORT dataa (2018:2018:2018) (2105:2105:2105)) - (PORT datab (2408:2408:2408) (2537:2537:2537)) - (PORT datac (1381:1381:1381) (1441:1441:1441)) - (PORT datad (1576:1576:1576) (1733:1733:1733)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1517:1517:1517) (1579:1579:1579)) - (PORT datab (385:385:385) (404:404:404)) - (PORT datac (1263:1263:1263) (1308:1308:1308)) - (PORT datad (871:871:871) (923:923:923)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1215:1215:1215) (1269:1269:1269)) - (PORT datab (340:340:340) (375:375:375)) - (PORT datac (1057:1057:1057) (1084:1084:1084)) - (PORT datad (337:337:337) (358:358:358)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~14) - (DELAY - (ABSOLUTE - (PORT dataa (354:354:354) (385:385:385)) - (PORT datab (643:643:643) (665:665:665)) - (PORT datac (169:169:169) (201:201:201)) - (PORT datad (616:616:616) (624:624:624)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~18) - (DELAY - (ABSOLUTE - (PORT dataa (837:837:837) (887:887:887)) - (PORT datab (1118:1118:1118) (1197:1197:1197)) - (PORT datac (848:848:848) (898:898:898)) - (PORT datad (364:364:364) (426:426:426)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_high) - (DELAY - (ABSOLUTE - (PORT dataa (2563:2563:2563) (2705:2705:2705)) - (PORT datab (221:221:221) (260:260:260)) - (PORT datac (1385:1385:1385) (1391:1391:1391)) - (PORT datad (1888:1888:1888) (1980:1980:1980)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|alu_\|alu_op2\[1\]\~1) (DELAY (ABSOLUTE - (PORT dataa (455:455:455) (529:529:529)) - (PORT datab (452:452:452) (522:522:522)) - (PORT datac (877:877:877) (897:897:897)) - (PORT datad (660:660:660) (680:680:680)) - (IOPATH dataa combout (324:324:324) (328:328:328)) + (PORT dataa (592:592:592) (661:661:661)) + (PORT datab (219:219:219) (258:258:258)) + (PORT datac (193:193:193) (226:226:226)) + (PORT datad (549:549:549) (604:604:604)) + (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -19648,12 +17682,28 @@ (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_10\~1) (DELAY (ABSOLUTE - (PORT dataa (546:546:546) (573:573:573)) - (PORT datab (633:633:633) (685:685:685)) - (PORT datac (619:619:619) (639:639:639)) - (PORT datad (630:630:630) (672:672:672)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (337:337:337) (348:348:348)) + (PORT dataa (928:928:928) (972:972:972)) + (PORT datab (872:872:872) (933:933:933)) + (PORT datac (1114:1114:1114) (1134:1134:1134)) + (PORT datad (181:181:181) (209:209:209)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_8\~0) + (DELAY + (ABSOLUTE + (PORT dataa (929:929:929) (977:977:977)) + (PORT datab (877:877:877) (939:939:939)) + (PORT datac (1116:1116:1116) (1138:1138:1138)) + (PORT datad (180:180:180) (207:207:207)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (304:304:304) (311:311:311)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -19661,15 +17711,75 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~9) + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_10\~0) (DELAY (ABSOLUTE - (PORT dataa (815:815:815) (850:850:850)) - (PORT datab (621:621:621) (640:640:640)) - (PORT datac (194:194:194) (228:228:228)) - (PORT datad (182:182:182) (212:212:212)) + (PORT datac (1062:1062:1062) (1104:1104:1104)) + (PORT datad (323:323:323) (344:344:344)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~5) + (DELAY + (ABSOLUTE + (PORT dataa (650:650:650) (685:685:685)) + (PORT datab (974:974:974) (983:983:983)) + (PORT datac (617:617:617) (635:635:635)) + (PORT datad (602:602:602) (621:621:621)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~2) + (DELAY + (ABSOLUTE + (PORT dataa (896:896:896) (938:938:938)) + (PORT datab (2096:2096:2096) (2147:2147:2147)) + (PORT datac (1426:1426:1426) (1512:1512:1512)) + (PORT datad (1434:1434:1434) (1483:1483:1483)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R) + (DELAY + (ABSOLUTE + (PORT dataa (574:574:574) (613:613:613)) + (PORT datab (204:204:204) (244:244:244)) + (PORT datac (1113:1113:1113) (1136:1136:1136)) + (PORT datad (1277:1277:1277) (1367:1367:1367)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[0\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (281:281:281) (354:354:354)) + (PORT datab (277:277:277) (334:334:334)) + (PORT datac (1112:1112:1112) (1121:1121:1121)) + (PORT datad (248:248:248) (292:292:292)) (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab combout (342:342:342) (318:318:318)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -19677,14 +17787,227 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[0\]\~7) + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[0\]) (DELAY (ABSOLUTE - (PORT dataa (811:811:811) (823:823:823)) - (PORT datab (610:610:610) (633:633:633)) - (PORT datac (1092:1092:1092) (1142:1142:1142)) - (PORT datad (895:895:895) (948:948:948)) - (IOPATH dataa combout (304:304:304) (308:308:308)) + (PORT dataa (947:947:947) (977:977:977)) + (PORT datac (896:896:896) (918:918:918)) + (PORT datad (653:653:653) (691:691:691)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_high\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1547:1547:1547) (1549:1549:1549)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[0\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (430:430:430) (459:459:459)) + (PORT datab (951:951:951) (997:997:997)) + (PORT datac (352:352:352) (377:377:377)) + (PORT datad (383:383:383) (450:450:450)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[0\]\~22) + (DELAY + (ABSOLUTE + (PORT datab (857:857:857) (876:876:876)) + (PORT datac (842:842:842) (868:868:868)) + (PORT datad (1187:1187:1187) (1271:1271:1271)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[0\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (911:911:911) (923:923:923)) + (PORT datab (1301:1301:1301) (1338:1338:1338)) + (PORT datad (177:177:177) (203:203:203)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[0\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (665:665:665) (697:697:697)) + (PORT datab (694:694:694) (745:745:745)) + (PORT datac (648:648:648) (667:667:667)) + (PORT datad (175:175:175) (200:200:200)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (280:280:280) (356:356:356)) + (PORT datab (276:276:276) (335:335:335)) + (PORT datac (1112:1112:1112) (1121:1121:1121)) + (PORT datad (243:243:243) (286:286:286)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|result_lo\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT asdata (538:538:538) (569:569:569)) + (PORT ena (1716:1716:1716) (1724:1724:1724)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (613:613:613) (662:662:662)) + (PORT datab (690:690:690) (734:734:734)) + (PORT datac (914:914:914) (939:939:939)) + (PORT datad (848:848:848) (864:864:864)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT datac (885:885:885) (905:905:905)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_low\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1547:1547:1547) (1549:1549:1549)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (794:794:794) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (430:430:430) (457:457:457)) + (PORT datab (613:613:613) (677:677:677)) + (PORT datac (352:352:352) (375:375:375)) + (PORT datad (400:400:400) (463:463:463)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (550:550:550) (573:573:573)) + (PORT datab (593:593:593) (608:608:608)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~1) + (DELAY + (ABSOLUTE + (PORT dataa (816:816:816) (845:845:845)) + (PORT datab (271:271:271) (354:354:354)) + (PORT datac (667:667:667) (748:748:748)) + (PORT datad (824:824:824) (845:845:845)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1142:1142:1142) (1189:1189:1189)) + (PORT datab (845:845:845) (850:850:850)) + (PORT datac (609:609:609) (641:641:641)) + (PORT datad (1844:1844:1844) (1963:1963:1963)) + (IOPATH dataa combout (324:324:324) (328:328:328)) (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -19693,11 +18016,216 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[0\]\~8) + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~3) (DELAY (ABSOLUTE - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (232:232:232) (287:287:287)) + (PORT dataa (2483:2483:2483) (2607:2607:2607)) + (PORT datab (1066:1066:1066) (1107:1107:1107)) + (PORT datac (372:372:372) (395:395:395)) + (PORT datad (1729:1729:1729) (1766:1766:1766)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (223:223:223) (268:268:268)) + (PORT datab (1935:1935:1935) (1992:1992:1992)) + (PORT datac (889:889:889) (926:926:926)) + (PORT datad (1141:1141:1141) (1182:1182:1182)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (209:209:209) (255:255:255)) + (PORT datab (1226:1226:1226) (1278:1278:1278)) + (PORT datac (218:218:218) (263:263:263)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (254:254:254)) + (PORT datab (206:206:206) (247:247:247)) + (PORT datac (172:172:172) (204:204:204)) + (PORT datad (593:593:593) (595:595:595)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~0) + (DELAY + (ABSOLUTE + (PORT dataa (812:812:812) (841:841:841)) + (PORT datab (872:872:872) (895:895:895)) + (PORT datac (209:209:209) (250:250:250)) + (PORT datad (598:598:598) (653:653:653)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~1) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (244:244:244)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datad (196:196:196) (222:222:222)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1086:1086:1086) (1145:1145:1145)) + (PORT datab (270:270:270) (354:354:354)) + (PORT datac (858:858:858) (939:939:939)) + (PORT datad (1180:1180:1180) (1263:1263:1263)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~2) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (1056:1056:1056) (1107:1107:1107)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (847:847:847) (876:876:876)) + (PORT datab (206:206:206) (248:248:248)) + (PORT datad (1179:1179:1179) (1266:1266:1266)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (725:725:725) (788:788:788)) + (PORT datab (1120:1120:1120) (1167:1167:1167)) + (PORT datac (602:602:602) (610:610:610)) + (PORT datad (808:808:808) (828:828:828)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (336:336:336) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (694:694:694) (718:718:718)) + (PORT datab (205:205:205) (247:247:247)) + (PORT datac (693:693:693) (747:747:747)) + (PORT datad (665:665:665) (701:701:701)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1097:1097:1097) (1131:1131:1131)) + (PORT datab (956:956:956) (1006:1006:1006)) + (PORT datac (541:541:541) (541:541:541)) + (PORT datad (583:583:583) (644:644:644)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (666:666:666) (698:698:698)) + (PORT datab (911:911:911) (937:937:937)) + (PORT datac (934:934:934) (954:954:954)) + (PORT datad (325:325:325) (339:339:339)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -19705,10 +18233,10 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_high\[0\]) + (INSTANCE z80_\|alu_\|op2_low\[0\]) (DELAY (ABSOLUTE - (PORT clk (1529:1529:1529) (1531:1531:1531)) + (PORT clk (1535:1535:1535) (1540:1540:1540)) (PORT d (74:74:74) (91:91:91)) (PORT ena (819:819:819) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) @@ -19724,60 +18252,26 @@ (INSTANCE z80_\|alu_\|alu_op2\[0\]\~3) (DELAY (ABSOLUTE - (PORT dataa (432:432:432) (521:521:521)) - (PORT datab (682:682:682) (739:739:739)) - (PORT datac (877:877:877) (897:897:897)) - (PORT datad (660:660:660) (685:685:685)) + (PORT dataa (405:405:405) (486:486:486)) + (PORT datab (405:405:405) (430:430:430)) + (PORT datac (618:618:618) (634:634:634)) + (PORT datad (395:395:395) (460:460:460)) (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~12) - (DELAY - (ABSOLUTE - (PORT dataa (862:862:862) (922:922:922)) - (PORT datab (224:224:224) (269:269:269)) - (PORT datac (826:826:826) (848:848:848)) - (PORT datad (904:904:904) (974:974:974)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~8) - (DELAY - (ABSOLUTE - (PORT dataa (786:786:786) (842:842:842)) - (PORT datab (197:197:197) (237:237:237)) - (PORT datac (1821:1821:1821) (1815:1815:1815)) - (PORT datad (790:790:790) (826:826:826)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_1) (DELAY (ABSOLUTE - (PORT dataa (684:684:684) (706:706:706)) - (PORT datab (1772:1772:1772) (1798:1798:1798)) - (PORT datac (179:179:179) (214:214:214)) - (PORT datad (823:823:823) (837:837:837)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (332:332:332)) + (PORT dataa (1101:1101:1101) (1146:1146:1146)) + (PORT datac (1094:1094:1094) (1114:1114:1114)) + (PORT datad (181:181:181) (210:210:210)) + (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -19785,31 +18279,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~21) + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla26M3T5_8) (DELAY (ABSOLUTE - (PORT dataa (2390:2390:2390) (2544:2544:2544)) - (PORT datab (1497:1497:1497) (1581:1581:1581)) - (PORT datac (874:874:874) (897:897:897)) - (PORT datad (1014:1014:1014) (1128:1128:1128)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~22) - (DELAY - (ABSOLUTE - (PORT dataa (578:578:578) (605:605:605)) - (PORT datab (974:974:974) (1056:1056:1056)) - (PORT datac (672:672:672) (715:715:715)) - (PORT datad (819:819:819) (820:820:820)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (300:300:300) (308:308:308)) + (PORT datab (930:930:930) (1046:1046:1046)) + (PORT datac (826:826:826) (869:869:869)) + (PORT datad (1304:1304:1304) (1448:1448:1448)) + (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -19817,45 +18293,45 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~19) + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~14) (DELAY (ABSOLUTE - (PORT dataa (987:987:987) (1039:1039:1039)) - (PORT datab (434:434:434) (474:474:474)) - (PORT datac (947:947:947) (1015:1015:1015)) - (PORT datad (1175:1175:1175) (1235:1235:1235)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~27) - (DELAY - (ABSOLUTE - (PORT dataa (238:238:238) (285:285:285)) - (PORT datab (222:222:222) (261:261:261)) - (PORT datac (194:194:194) (228:228:228)) - (PORT datad (208:208:208) (238:238:238)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~29) - (DELAY - (ABSOLUTE - (PORT datab (229:229:229) (278:278:278)) - (PORT datac (193:193:193) (235:235:235)) - (PORT datad (374:374:374) (396:396:396)) + (PORT dataa (3085:3085:3085) (3152:3152:3152)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (1680:1680:1680) (1768:1768:1768)) + (PORT datad (826:826:826) (854:854:854)) + (IOPATH dataa combout (303:303:303) (299:299:299)) (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1331:1331:1331) (1419:1419:1419)) + (PORT datac (588:588:588) (638:638:638)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1646:1646:1646) (1724:1724:1724)) + (PORT datab (1909:1909:1909) (1995:1995:1995)) + (PORT datac (1136:1136:1136) (1198:1198:1198)) + (PORT datad (1428:1428:1428) (1497:1497:1497)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -19863,13 +18339,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~23) + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~17) (DELAY (ABSOLUTE - (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (639:639:639) (661:661:661)) - (PORT datac (172:172:172) (204:204:204)) - (PORT datad (195:195:195) (220:220:220)) + (PORT dataa (198:198:198) (240:240:240)) + (PORT datab (631:631:631) (669:669:669)) + (PORT datac (206:206:206) (246:246:246)) + (PORT datad (892:892:892) (940:940:940)) (IOPATH dataa combout (354:354:354) (349:349:349)) (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -19879,13 +18355,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~37) + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~44) (DELAY (ABSOLUTE - (PORT datab (1269:1269:1269) (1380:1380:1380)) - (PORT datac (901:901:901) (917:917:917)) - (PORT datad (1177:1177:1177) (1191:1191:1191)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT dataa (405:405:405) (433:433:433)) + (PORT datab (237:237:237) (282:282:282)) + (PORT datac (611:611:611) (637:637:637)) + (PORT datad (591:591:591) (612:612:612)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~20) + (DELAY + (ABSOLUTE + (PORT dataa (1646:1646:1646) (1723:1723:1723)) + (PORT datab (1128:1128:1128) (1211:1211:1211)) + (PORT datac (1136:1136:1136) (1198:1198:1198)) + (PORT datad (1429:1429:1429) (1497:1497:1497)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -19893,15 +18387,79 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~38) + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~21) (DELAY (ABSOLUTE - (PORT dataa (1285:1285:1285) (1340:1340:1340)) - (PORT datab (1007:1007:1007) (1075:1075:1075)) - (PORT datac (1456:1456:1456) (1496:1496:1496)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (304:304:304) (308:308:308)) + (PORT dataa (228:228:228) (276:276:276)) + (PORT datab (1127:1127:1127) (1211:1211:1211)) + (PORT datac (973:973:973) (1038:1038:1038)) + (PORT datad (172:172:172) (198:198:198)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~18) + (DELAY + (ABSOLUTE + (PORT dataa (924:924:924) (993:993:993)) + (PORT datab (1226:1226:1226) (1276:1276:1276)) + (PORT datac (2112:2112:2112) (2204:2204:2204)) + (PORT datad (1660:1660:1660) (1676:1676:1676)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~19) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (265:265:265)) + (PORT datab (245:245:245) (293:293:293)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (210:210:210) (243:243:243)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~22) + (DELAY + (ABSOLUTE + (PORT dataa (223:223:223) (267:267:267)) + (PORT datab (238:238:238) (283:283:283)) + (PORT datac (591:591:591) (637:637:637)) + (PORT datad (623:623:623) (638:638:638)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~43) + (DELAY + (ABSOLUTE + (PORT dataa (660:660:660) (718:718:718)) + (PORT datab (963:963:963) (1006:1006:1006)) + (PORT datac (1606:1606:1606) (1643:1643:1643)) + (PORT datad (613:613:613) (630:630:630)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -19912,13 +18470,13 @@ (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~24) (DELAY (ABSOLUTE - (PORT dataa (2050:2050:2050) (2087:2087:2087)) - (PORT datab (943:943:943) (1022:1022:1022)) - (PORT datac (1211:1211:1211) (1239:1239:1239)) - (PORT datad (1083:1083:1083) (1126:1126:1126)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (1252:1252:1252) (1300:1300:1300)) + (PORT datab (1028:1028:1028) (1085:1085:1085)) + (PORT datac (3027:3027:3027) (3057:3057:3057)) + (PORT datad (1455:1455:1455) (1504:1504:1504)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -19928,156 +18486,12 @@ (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~25) (DELAY (ABSOLUTE - (PORT dataa (923:923:923) (949:949:949)) - (PORT datab (1060:1060:1060) (1085:1085:1085)) - (PORT datac (892:892:892) (934:934:934)) - (PORT datad (568:568:568) (571:571:571)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~26) - (DELAY - (ABSOLUTE - (PORT dataa (1490:1490:1490) (1592:1592:1592)) - (PORT datab (438:438:438) (472:472:472)) - (PORT datac (945:945:945) (997:997:997)) - (PORT datad (1178:1178:1178) (1233:1233:1233)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~27) - (DELAY - (ABSOLUTE - (PORT dataa (1493:1493:1493) (1597:1597:1597)) - (PORT datab (234:234:234) (278:278:278)) - (PORT datac (2021:2021:2021) (2050:2050:2050)) + (PORT dataa (941:941:941) (975:975:975)) + (PORT datab (1204:1204:1204) (1270:1270:1270)) + (PORT datac (896:896:896) (940:940:940)) (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~28) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (220:220:220) (259:259:259)) - (PORT datac (609:609:609) (638:638:638)) - (PORT datad (194:194:194) (220:220:220)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~30) - (DELAY - (ABSOLUTE - (PORT dataa (209:209:209) (258:258:258)) - (PORT datab (218:218:218) (256:256:256)) - (PORT datac (817:817:817) (862:862:862)) - (PORT datad (554:554:554) (572:572:572)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~34) - (DELAY - (ABSOLUTE - (PORT dataa (1462:1462:1462) (1525:1525:1525)) - (PORT datab (1404:1404:1404) (1424:1424:1424)) - (PORT datac (1574:1574:1574) (1618:1618:1618)) - (PORT datad (1065:1065:1065) (1079:1079:1079)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~32) - (DELAY - (ABSOLUTE - (PORT dataa (734:734:734) (759:759:759)) - (PORT datab (699:699:699) (730:730:730)) - (PORT datac (1599:1599:1599) (1604:1604:1604)) - (PORT datad (1436:1436:1436) (1479:1479:1479)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~43) - (DELAY - (ABSOLUTE - (PORT dataa (1343:1343:1343) (1425:1425:1425)) - (PORT datab (1086:1086:1086) (1110:1110:1110)) - (PORT datac (1574:1574:1574) (1614:1614:1614)) - (PORT datad (1794:1794:1794) (1911:1911:1911)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~33) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (843:843:843) (880:880:880)) - (PORT datac (1602:1602:1602) (1608:1608:1608)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~42) - (DELAY - (ABSOLUTE - (PORT dataa (837:837:837) (867:867:867)) - (PORT datab (1092:1092:1092) (1116:1116:1116)) - (PORT datac (2113:2113:2113) (2219:2219:2219)) - (PORT datad (1789:1789:1789) (1904:1904:1904)) (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -20088,90 +18502,10 @@ (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~35) (DELAY (ABSOLUTE - (PORT dataa (199:199:199) (242:242:242)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (1016:1016:1016) (1027:1027:1027)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~41) - (DELAY - (ABSOLUTE - (PORT dataa (675:675:675) (702:702:702)) - (PORT datab (2051:2051:2051) (2134:2134:2134)) - (PORT datac (1486:1486:1486) (1540:1540:1540)) - (PORT datad (1327:1327:1327) (1454:1454:1454)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~30) - (DELAY - (ABSOLUTE - (PORT dataa (1519:1519:1519) (1580:1580:1580)) - (PORT datab (1960:1960:1960) (1986:1986:1986)) - (PORT datac (1263:1263:1263) (1313:1313:1313)) - (PORT datad (869:869:869) (922:922:922)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1748:1748:1748) (1872:1872:1872)) - (PORT datab (1028:1028:1028) (1083:1083:1083)) - (PORT datac (199:199:199) (235:235:235)) - (PORT datad (1506:1506:1506) (1541:1541:1541)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~31) - (DELAY - (ABSOLUTE - (PORT dataa (1165:1165:1165) (1194:1194:1194)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (1359:1359:1359) (1382:1382:1382)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~44) - (DELAY - (ABSOLUTE - (PORT dataa (819:819:819) (841:841:841)) - (PORT datab (1818:1818:1818) (1968:1968:1968)) - (PORT datac (1306:1306:1306) (1386:1386:1386)) - (PORT datad (1794:1794:1794) (1911:1911:1911)) + (PORT dataa (2133:2133:2133) (2251:2251:2251)) + (PORT datab (2062:2062:2062) (2161:2161:2161)) + (PORT datac (1557:1557:1557) (1656:1656:1656)) + (PORT datad (1125:1125:1125) (1129:1129:1129)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -20179,18 +18513,130 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~23) + (DELAY + (ABSOLUTE + (PORT dataa (224:224:224) (279:279:279)) + (PORT datab (1030:1030:1030) (1085:1085:1085)) + (PORT datac (575:575:575) (587:587:587)) + (PORT datad (847:847:847) (867:867:867)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~26) + (DELAY + (ABSOLUTE + (PORT dataa (1451:1451:1451) (1458:1458:1458)) + (PORT datab (1101:1101:1101) (1148:1148:1148)) + (PORT datac (1380:1380:1380) (1467:1467:1467)) + (PORT datad (908:908:908) (950:950:950)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~34) + (DELAY + (ABSOLUTE + (PORT dataa (2559:2559:2559) (2697:2697:2697)) + (PORT datab (1483:1483:1483) (1515:1515:1515)) + (PORT datac (1449:1449:1449) (1537:1537:1537)) + (PORT datad (913:913:913) (966:966:966)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~27) + (DELAY + (ABSOLUTE + (PORT dataa (745:745:745) (816:816:816)) + (PORT datab (1711:1711:1711) (1759:1759:1759)) + (PORT datac (862:862:862) (891:891:891)) + (PORT datad (1925:1925:1925) (2095:2095:2095)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~28) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (246:246:246)) + (PORT datab (939:939:939) (1037:1037:1037)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (1925:1925:1925) (2098:2098:2098)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~29) + (DELAY + (ABSOLUTE + (PORT dataa (988:988:988) (1052:1052:1052)) + (PORT datab (893:893:893) (923:923:923)) + (PORT datac (1450:1450:1450) (1477:1477:1477)) + (PORT datad (1671:1671:1671) (1723:1723:1723)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~30) (DELAY (ABSOLUTE (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (699:699:699) (733:733:733)) - (PORT datac (862:862:862) (901:901:901)) - (PORT datad (693:693:693) (717:717:717)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (1120:1120:1120) (1150:1150:1150)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~31) + (DELAY + (ABSOLUTE + (PORT dataa (610:610:610) (634:634:634)) + (PORT datab (196:196:196) (234:234:234)) + (PORT datac (171:171:171) (205:205:205)) + (PORT datad (607:607:607) (619:619:619)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -20200,28 +18646,10 @@ (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~36) (DELAY (ABSOLUTE - (PORT dataa (532:532:532) (551:551:551)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (641:641:641) (659:659:659)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~39) - (DELAY - (ABSOLUTE - (PORT dataa (593:593:593) (620:620:620)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (603:603:603) (622:622:622)) - (PORT datad (345:345:345) (359:359:359)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) + (PORT dataa (1280:1280:1280) (1375:1375:1375)) + (PORT datac (1673:1673:1673) (1738:1738:1738)) + (PORT datad (1996:1996:1996) (2055:2055:2055)) + (IOPATH dataa combout (354:354:354) (367:367:367)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -20229,47 +18657,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~40) + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~37) (DELAY (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (917:917:917) (956:956:956)) - (PORT datac (193:193:193) (226:226:226)) - (PORT datad (317:317:317) (337:337:337)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1666:1666:1666) (1754:1754:1754)) - (PORT datab (1416:1416:1416) (1493:1493:1493)) - (PORT datac (639:639:639) (659:659:659)) - (PORT datad (847:847:847) (875:875:875)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1450:1450:1450) (1506:1506:1506)) - (PORT datab (849:849:849) (859:859:859)) - (PORT datac (836:836:836) (864:864:864)) - (PORT datad (1389:1389:1389) (1423:1423:1423)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) + (PORT dataa (1418:1418:1418) (1478:1478:1478)) + (PORT datab (1638:1638:1638) (1708:1708:1708)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (1247:1247:1247) (1293:1293:1293)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -20277,314 +18673,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R) + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~32) (DELAY (ABSOLUTE - (PORT dataa (831:831:831) (869:869:869)) - (PORT datab (1772:1772:1772) (1798:1798:1798)) - (PORT datac (618:618:618) (638:638:638)) - (PORT datad (822:822:822) (837:837:837)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[3\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1198:1198:1198) (1248:1248:1248)) - (PORT datab (223:223:223) (268:268:268)) - (PORT datac (914:914:914) (947:947:947)) - (PORT datad (607:607:607) (631:631:631)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[3\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (263:263:263) (334:334:334)) - (PORT datab (944:944:944) (991:991:991)) - (PORT datac (535:535:535) (545:545:545)) - (PORT datad (1139:1139:1139) (1125:1125:1125)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_high\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[3\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (596:596:596) (673:673:673)) - (PORT datab (1125:1125:1125) (1173:1173:1173)) - (PORT datac (583:583:583) (615:615:615)) - (PORT datad (389:389:389) (443:443:443)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[3\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (263:263:263) (340:340:340)) - (PORT datab (199:199:199) (239:239:239)) - (PORT datac (559:559:559) (583:583:583)) - (PORT datad (901:901:901) (948:948:948)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_low\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op2\[3\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (423:423:423) (511:511:511)) - (PORT datab (419:419:419) (499:499:499)) - (PORT datac (878:878:878) (901:901:901)) - (PORT datad (657:657:657) (678:678:678)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|SYNTHESIZED_WIRE_10\~1) - (DELAY - (ABSOLUTE - (PORT dataa (207:207:207) (253:253:253)) - (PORT datab (638:638:638) (659:659:659)) - (PORT datac (355:355:355) (378:378:378)) - (PORT datad (830:830:830) (837:837:837)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|SYNTHESIZED_WIRE_10\~0) - (DELAY - (ABSOLUTE - (PORT dataa (390:390:390) (419:419:419)) - (PORT datab (653:653:653) (711:711:711)) - (PORT datac (647:647:647) (707:707:707)) - (PORT datad (635:635:635) (659:659:659)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|cy_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (413:413:413) (443:443:443)) - (PORT datab (239:239:239) (284:284:284)) - (PORT datac (181:181:181) (218:218:218)) - (PORT datad (180:180:180) (208:208:208)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf\~0) - (DELAY - (ABSOLUTE - (PORT dataa (709:709:709) (742:742:742)) - (PORT datab (1178:1178:1178) (1274:1274:1274)) - (PORT datac (855:855:855) (865:865:865)) - (PORT datad (674:674:674) (693:693:693)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1304:1304:1304) (1358:1358:1358)) - (PORT datab (1962:1962:1962) (1990:1990:1990)) - (PORT datac (1486:1486:1486) (1545:1545:1545)) - (PORT datad (1495:1495:1495) (1557:1557:1557)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1144:1144:1144) (1179:1179:1179)) - (PORT datab (609:609:609) (638:638:638)) - (PORT datac (820:820:820) (842:842:842)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf\~1) - (DELAY - (ABSOLUTE - (PORT dataa (209:209:209) (257:257:257)) + (PORT dataa (199:199:199) (242:242:242)) (PORT datab (196:196:196) (235:235:235)) - (PORT datad (798:798:798) (805:805:805)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (815:815:815) (832:832:832)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~33) + (DELAY + (ABSOLUTE + (PORT dataa (349:349:349) (384:384:384)) + (PORT datab (972:972:972) (1035:1035:1035)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (603:603:603) (650:650:650)) (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf) - (DELAY - (ABSOLUTE - (PORT clk (1514:1514:1514) (1528:1528:1528)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1152:1152:1152) (1175:1175:1175)) - (PORT datac (567:567:567) (576:576:576)) - (PORT datad (1627:1627:1627) (1703:1703:1703)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~12) - (DELAY - (ABSOLUTE - (PORT dataa (919:919:919) (927:927:927)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (1829:1829:1829) (1911:1911:1911)) - (PORT datad (562:562:562) (570:570:570)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~13) - (DELAY - (ABSOLUTE - (PORT dataa (378:378:378) (415:415:415)) - (PORT datab (2086:2086:2086) (2229:2229:2229)) - (PORT datac (1314:1314:1314) (1402:1402:1402)) - (PORT datad (902:902:902) (968:968:968)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|flags_hf) - (DELAY - (ABSOLUTE - (PORT dataa (385:385:385) (462:462:462)) - (PORT datab (612:612:612) (633:633:633)) - (PORT datac (1175:1175:1175) (1235:1235:1235)) - (PORT datad (822:822:822) (844:844:844)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (337:337:337) (348:348:348)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -20595,9 +18708,23 @@ (INSTANCE z80_\|alu_control_\|alu_core_cf_in\~0) (DELAY (ABSOLUTE - (PORT dataa (572:572:572) (597:597:597)) - (PORT datab (615:615:615) (638:638:638)) - (PORT datad (567:567:567) (574:574:574)) + (PORT dataa (637:637:637) (672:672:672)) + (PORT datab (848:848:848) (872:872:872)) + (PORT datac (845:845:845) (855:855:855)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op1\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1096:1096:1096) (1133:1133:1133)) + (PORT datab (951:951:951) (1001:1001:1001)) + (PORT datad (578:578:578) (641:641:641)) (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -20609,10 +18736,10 @@ (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|result\~0) (DELAY (ABSOLUTE - (PORT dataa (660:660:660) (685:685:685)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (807:807:807) (808:808:808)) - (PORT datad (203:203:203) (232:232:232)) + (PORT dataa (199:199:199) (241:241:241)) + (PORT datab (196:196:196) (235:235:235)) + (PORT datac (1034:1034:1034) (1067:1067:1067)) + (PORT datad (180:180:180) (207:207:207)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (243:243:243) (242:242:242)) @@ -20620,735 +18747,17 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (1698:1698:1698) (1789:1789:1789)) - (PORT datab (919:919:919) (952:952:952)) - (PORT datac (888:888:888) (909:909:909)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[12\]) - (DELAY - (ABSOLUTE - (PORT datab (403:403:403) (448:448:448)) - (PORT datac (885:885:885) (915:915:915)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|Q\[12\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (314:314:314) (333:333:333)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[12\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1581:1581:1581) (1561:1561:1561)) - (PORT ena (2058:2058:2058) (2109:2109:2109)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|d0_out) - (DELAY - (ABSOLUTE - (PORT dataa (625:625:625) (638:638:638)) - (PORT datab (903:903:903) (926:926:926)) - (PORT datac (240:240:240) (327:327:327)) - (PORT datad (577:577:577) (639:639:639)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1308:1308:1308) (1303:1303:1303)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1535:1535:1535) (1554:1554:1554)) - (PORT asdata (1270:1270:1270) (1318:1318:1318)) - (PORT ena (935:935:935) (924:924:924)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (410:410:410) (460:460:460)) - (PORT datab (412:412:412) (448:448:448)) - (PORT datad (194:194:194) (218:218:218)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (674:674:674) (717:717:717)) - (PORT datac (216:216:216) (293:293:293)) - (PORT datad (775:775:775) (807:807:807)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (391:391:391) (418:418:418)) - (PORT datab (838:838:838) (875:875:875)) - (PORT datac (679:679:679) (721:721:721)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1534:1534:1534)) - (PORT asdata (2041:2041:2041) (2053:2053:2053)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~62) - (DELAY - (ABSOLUTE - (PORT dataa (409:409:409) (437:437:437)) - (PORT datab (1165:1165:1165) (1216:1216:1216)) - (PORT datad (739:739:739) (751:751:751)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1535:1535:1535) (1554:1554:1554)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1461:1461:1461) (1468:1468:1468)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1534:1534:1534)) - (PORT asdata (2041:2041:2041) (2050:2050:2050)) - (PORT ena (1236:1236:1236) (1273:1273:1273)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~63) - (DELAY - (ABSOLUTE - (PORT dataa (692:692:692) (780:780:780)) - (PORT datab (884:884:884) (909:909:909)) - (PORT datad (866:866:866) (902:902:902)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (1376:1376:1376) (1427:1427:1427)) - (PORT ena (1214:1214:1214) (1210:1210:1210)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (1376:1376:1376) (1429:1429:1429)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~61) - (DELAY - (ABSOLUTE - (PORT dataa (905:905:905) (945:945:945)) - (PORT datab (244:244:244) (290:290:290)) - (PORT datad (216:216:216) (284:284:284)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[4\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1394:1394:1394) (1418:1418:1418)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1193:1193:1193) (1176:1176:1176)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (1721:1721:1721) (1742:1742:1742)) - (PORT ena (1283:1283:1283) (1283:1283:1283)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~60) - (DELAY - (ABSOLUTE - (PORT dataa (392:392:392) (467:467:467)) - (PORT datab (1593:1593:1593) (1645:1645:1645)) - (PORT datad (1180:1180:1180) (1215:1215:1215)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~64) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (809:809:809) (810:810:810)) - (PORT datad (610:610:610) (622:622:622)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (1872:1872:1872) (1943:1943:1943)) - (PORT ena (1388:1388:1388) (1427:1427:1427)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (1872:1872:1872) (1942:1942:1942)) - (PORT ena (1400:1400:1400) (1413:1413:1413)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~59) - (DELAY - (ABSOLUTE - (PORT dataa (932:932:932) (991:991:991)) - (PORT datab (912:912:912) (981:981:981)) - (PORT datad (215:215:215) (283:283:283)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1537:1537:1537)) - (PORT asdata (1938:1938:1938) (1952:1952:1952)) - (PORT ena (990:990:990) (994:994:994)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1537:1537:1537)) - (PORT asdata (1936:1936:1936) (1952:1952:1952)) - (PORT ena (973:973:973) (964:964:964)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~58) - (DELAY - (ABSOLUTE - (PORT dataa (466:466:466) (519:519:519)) - (PORT datab (492:492:492) (537:537:537)) - (PORT datad (217:217:217) (284:284:284)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (1867:1867:1867) (1935:1935:1935)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[4\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (930:930:930) (988:988:988)) - (PORT datab (1221:1221:1221) (1295:1295:1295)) - (PORT datad (887:887:887) (943:943:943)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~65) - (DELAY - (ABSOLUTE - (PORT dataa (644:644:644) (697:697:697)) - (PORT datab (331:331:331) (360:360:360)) - (PORT datac (577:577:577) (594:594:594)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~66) - (DELAY - (ABSOLUTE - (PORT dataa (883:883:883) (947:947:947)) - (PORT datab (844:844:844) (916:916:916)) - (PORT datac (840:840:840) (851:851:851)) - (PORT datad (1298:1298:1298) (1335:1335:1335)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[4\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1304:1304:1304) (1356:1356:1356)) - (PORT datab (968:968:968) (1024:1024:1024)) - (PORT datac (891:891:891) (908:908:908)) - (PORT datad (1445:1445:1445) (1454:1454:1454)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[7\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (1289:1289:1289) (1337:1337:1337)) - (PORT datab (1225:1225:1225) (1251:1251:1251)) - (PORT datac (904:904:904) (947:947:947)) - (PORT datad (928:928:928) (986:986:986)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[4\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (206:206:206) (251:251:251)) - (PORT datab (249:249:249) (305:305:305)) - (PORT datac (1067:1067:1067) (1064:1064:1064)) - (PORT datad (949:949:949) (996:996:996)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1286:1286:1286) (1354:1354:1354)) - (PORT datab (933:933:933) (990:990:990)) - (PORT datac (372:372:372) (402:402:402)) - (PORT datad (1200:1200:1200) (1314:1314:1314)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1111:1111:1111) (1230:1230:1230)) - (PORT datab (1831:1831:1831) (1921:1921:1921)) - (PORT datac (881:881:881) (935:935:935)) - (PORT datad (1554:1554:1554) (1661:1661:1661)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~4) - (DELAY - (ABSOLUTE - (PORT dataa (923:923:923) (987:987:987)) - (PORT datab (637:637:637) (672:672:672)) - (PORT datac (1395:1395:1395) (1470:1470:1470)) - (PORT datad (580:580:580) (617:617:617)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (204:204:204) (249:249:249)) - (PORT datac (935:935:935) (965:965:965)) - (PORT datad (241:241:241) (282:282:282)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1179:1179:1179) (1212:1212:1212)) - (PORT datab (290:290:290) (355:355:355)) - (PORT datac (254:254:254) (314:314:314)) - (PORT datad (246:246:246) (292:292:292)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[0\]) - (DELAY - (ABSOLUTE - (PORT datab (359:359:359) (395:395:395)) - (PORT datac (927:927:927) (982:982:982)) - (PORT datad (676:676:676) (714:714:714)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_high\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (636:636:636) (695:695:695)) - (PORT datab (1175:1175:1175) (1218:1218:1218)) - (PORT datac (649:649:649) (707:707:707)) - (PORT datad (660:660:660) (719:719:719)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|alu_\|db_high\[0\]\~25) (DELAY (ABSOLUTE - (PORT dataa (598:598:598) (629:629:629)) - (PORT datab (329:329:329) (356:356:356)) - (PORT datac (1163:1163:1163) (1203:1203:1203)) - (PORT datad (530:530:530) (548:548:548)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (645:645:645) (679:679:679)) - (PORT datab (998:998:998) (1032:1032:1032)) - (PORT datac (172:172:172) (204:204:204)) - (PORT datad (220:220:220) (263:263:263)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[0\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (594:594:594) (621:621:621)) - (PORT datab (963:963:963) (1009:1009:1009)) - (PORT datac (864:864:864) (907:907:907)) - (PORT datad (337:337:337) (357:357:357)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[0\]\~8) - (DELAY - (ABSOLUTE - (PORT datac (173:173:173) (206:206:206)) - (PORT datad (674:674:674) (713:713:713)) + (PORT dataa (370:370:370) (393:393:393)) + (PORT datab (376:376:376) (407:407:407)) + (PORT datac (840:840:840) (893:893:893)) + (PORT datad (1078:1078:1078) (1078:1078:1078)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -21356,59 +18765,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|ena) + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[0\]\~6) (DELAY (ABSOLUTE - (PORT dataa (903:903:903) (963:963:963)) - (PORT datab (719:719:719) (762:762:762)) - (PORT datac (929:929:929) (980:980:980)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_low\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op1\[0\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (647:647:647) (678:678:678)) - (PORT datab (640:640:640) (697:697:697)) - (PORT datac (608:608:608) (646:646:646)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[0\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (620:620:620) (648:648:648)) - (PORT datab (935:935:935) (984:984:984)) - (PORT datac (1093:1093:1093) (1149:1149:1149)) - (PORT datad (575:575:575) (595:595:595)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (306:306:306) (311:311:311)) + (PORT dataa (651:651:651) (667:667:667)) + (PORT datab (655:655:655) (679:679:679)) + (PORT datac (919:919:919) (940:940:940)) + (PORT datad (625:625:625) (655:655:655)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -21416,22 +18781,22 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[0\]\~7) + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[0\]\~7) (DELAY (ABSOLUTE - (PORT dataa (263:263:263) (339:339:339)) - (PORT datac (171:171:171) (204:204:204)) - (IOPATH dataa combout (356:356:356) (368:368:368)) + (PORT datab (911:911:911) (939:939:939)) + (PORT datac (173:173:173) (206:206:206)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (242:242:242)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_low\[0\]) + (INSTANCE z80_\|alu_\|op2_high\[0\]) (DELAY (ABSOLUTE - (PORT clk (1529:1529:1529) (1531:1531:1531)) + (PORT clk (1535:1535:1535) (1540:1540:1540)) (PORT d (74:74:74) (91:91:91)) (PORT ena (819:819:819) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) @@ -21447,11 +18812,11 @@ (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_10\~0) (DELAY (ABSOLUTE - (PORT dataa (431:431:431) (524:524:524)) - (PORT datac (650:650:650) (711:711:711)) - (PORT datad (658:658:658) (684:684:684)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (408:408:408) (491:491:491)) + (PORT datab (402:402:402) (430:430:430)) + (PORT datad (398:398:398) (464:464:464)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -21461,10 +18826,10 @@ (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_10\~1) (DELAY (ABSOLUTE - (PORT dataa (592:592:592) (600:600:600)) - (PORT datab (826:826:826) (830:830:830)) - (PORT datac (805:805:805) (806:806:806)) - (PORT datad (202:202:202) (231:231:231)) + (PORT dataa (653:653:653) (673:673:673)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (1033:1033:1033) (1067:1067:1067)) + (PORT datad (180:180:180) (209:209:209)) (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (242:242:242)) @@ -21477,5139 +18842,27 @@ (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|cy_out\~0) (DELAY (ABSOLUTE - (PORT dataa (688:688:688) (712:712:712)) - (PORT datab (207:207:207) (248:248:248)) - (PORT datac (203:203:203) (240:240:240)) - (PORT datad (818:818:818) (831:831:831)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op1\[1\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (649:649:649) (676:676:676)) - (PORT datab (632:632:632) (684:684:684)) - (PORT datad (630:630:630) (672:672:672)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_10\~0) - (DELAY - (ABSOLUTE - (PORT dataa (683:683:683) (704:704:704)) - (PORT datab (860:860:860) (876:876:876)) - (PORT datac (181:181:181) (218:218:218)) - (PORT datad (515:515:515) (526:526:526)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (206:206:206) (252:252:252)) - (PORT datab (213:213:213) (257:257:257)) - (PORT datac (201:201:201) (238:238:238)) - (PORT datad (182:182:182) (212:212:212)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op1\[2\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (632:632:632) (690:690:690)) - (PORT datab (662:662:662) (696:696:696)) - (PORT datad (604:604:604) (655:655:655)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_10\~1) - (DELAY - (ABSOLUTE - (PORT dataa (369:369:369) (405:405:405)) - (PORT datab (638:638:638) (659:659:659)) - (PORT datac (180:180:180) (216:216:216)) - (PORT datad (830:830:830) (837:837:837)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|cy_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (387:387:387) (410:410:410)) - (PORT datab (394:394:394) (423:423:423)) - (PORT datac (177:177:177) (214:214:214)) - (PORT datad (368:368:368) (390:390:390)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~5) - (DELAY - (ABSOLUTE - (PORT datac (1740:1740:1740) (1766:1766:1766)) - (PORT datad (822:822:822) (836:836:836)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|SYNTHESIZED_WIRE_1) - (DELAY - (ABSOLUTE - (PORT dataa (371:371:371) (410:410:410)) - (PORT datab (234:234:234) (279:279:279)) - (PORT datac (177:177:177) (213:213:213)) - (PORT datad (179:179:179) (207:207:207)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|result\~0) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (255:255:255)) - (PORT datab (236:236:236) (281:281:281)) - (PORT datac (354:354:354) (379:379:379)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[7\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1068:1068:1068) (1102:1102:1102)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1193:1193:1193) (1176:1176:1176)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (1435:1435:1435) (1482:1482:1482)) - (PORT ena (1283:1283:1283) (1283:1283:1283)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~69) - (DELAY - (ABSOLUTE - (PORT dataa (244:244:244) (331:331:331)) - (PORT datab (1596:1596:1596) (1648:1648:1648)) - (PORT datad (1179:1179:1179) (1221:1221:1221)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (1647:1647:1647) (1718:1718:1718)) - (PORT ena (1214:1214:1214) (1210:1210:1210)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (1644:1644:1644) (1714:1714:1714)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~70) - (DELAY - (ABSOLUTE - (PORT dataa (902:902:902) (942:942:942)) - (PORT datab (245:245:245) (290:290:290)) - (PORT datad (218:218:218) (287:287:287)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1535:1535:1535) (1554:1554:1554)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1461:1461:1461) (1468:1468:1468)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1534:1534:1534)) - (PORT asdata (1405:1405:1405) (1471:1471:1471)) - (PORT ena (1236:1236:1236) (1273:1273:1273)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~72) - (DELAY - (ABSOLUTE - (PORT dataa (712:712:712) (798:798:798)) - (PORT datab (884:884:884) (909:909:909)) - (PORT datad (866:866:866) (902:902:902)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1534:1534:1534)) - (PORT asdata (1404:1404:1404) (1472:1472:1472)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~71) - (DELAY - (ABSOLUTE - (PORT dataa (1391:1391:1391) (1418:1418:1418)) - (PORT datab (1167:1167:1167) (1217:1217:1217)) - (PORT datad (238:238:238) (279:279:279)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~73) - (DELAY - (ABSOLUTE - (PORT dataa (820:820:820) (843:843:843)) - (PORT datab (1070:1070:1070) (1130:1130:1130)) - (PORT datac (171:171:171) (205:205:205)) - (PORT datad (172:172:172) (198:198:198)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1537:1537:1537)) - (PORT asdata (1442:1442:1442) (1490:1490:1490)) - (PORT ena (990:990:990) (994:994:994)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1537:1537:1537)) - (PORT asdata (1439:1439:1439) (1490:1490:1490)) - (PORT ena (973:973:973) (964:964:964)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~67) - (DELAY - (ABSOLUTE - (PORT dataa (466:466:466) (523:523:523)) - (PORT datab (492:492:492) (536:536:536)) - (PORT datad (216:216:216) (284:284:284)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (1377:1377:1377) (1423:1423:1423)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[7\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (938:938:938) (994:994:994)) - (PORT datab (1222:1222:1222) (1294:1294:1294)) - (PORT datad (881:881:881) (941:941:941)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (1195:1195:1195) (1249:1249:1249)) - (PORT ena (1388:1388:1388) (1427:1427:1427)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (1195:1195:1195) (1248:1248:1248)) - (PORT ena (1400:1400:1400) (1413:1413:1413)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~68) - (DELAY - (ABSOLUTE - (PORT dataa (924:924:924) (985:985:985)) - (PORT datab (910:910:910) (988:988:988)) - (PORT datad (217:217:217) (286:286:286)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~74) - (DELAY - (ABSOLUTE - (PORT dataa (384:384:384) (410:410:410)) - (PORT datab (634:634:634) (661:661:661)) - (PORT datac (637:637:637) (673:673:673)) - (PORT datad (789:789:789) (853:853:853)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1535:1535:1535) (1554:1554:1554)) - (PORT asdata (1138:1138:1138) (1178:1178:1178)) - (PORT ena (935:935:935) (924:924:924)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (222:222:222) (266:266:266)) - (PORT datab (407:407:407) (446:446:446)) - (PORT datad (387:387:387) (422:422:422)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1308:1308:1308) (1303:1303:1303)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (794:794:794) (860:860:860)) - (PORT datac (214:214:214) (289:289:289)) - (PORT datad (646:646:646) (672:672:672)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|SYNTHESIZED_WIRE_0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (623:623:623) (634:634:634)) - (PORT datab (906:906:906) (933:933:933)) - (PORT datac (239:239:239) (322:322:322)) - (PORT datad (576:576:576) (636:636:636)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|d1_out) - (DELAY - (ABSOLUTE - (PORT datac (258:258:258) (345:345:345)) - (PORT datad (187:187:187) (220:220:220)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (1405:1405:1405) (1477:1477:1477)) - (PORT ena (1261:1261:1261) (1299:1299:1299)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1535:1535:1535) (1554:1554:1554)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1461:1461:1461) (1468:1468:1468)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~54) - (DELAY - (ABSOLUTE - (PORT dataa (1099:1099:1099) (1151:1151:1151)) - (PORT datab (881:881:881) (915:915:915)) - (PORT datad (665:665:665) (744:744:744)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1534:1534:1534)) - (PORT asdata (2052:2052:2052) (2111:2111:2111)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~53) - (DELAY - (ABSOLUTE - (PORT dataa (1647:1647:1647) (1654:1654:1654)) - (PORT datab (1164:1164:1164) (1211:1211:1211)) - (PORT datad (231:231:231) (271:271:271)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[5\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1101:1101:1101) (1166:1166:1166)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1193:1193:1193) (1176:1176:1176)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (1418:1418:1418) (1481:1481:1481)) - (PORT ena (1283:1283:1283) (1283:1283:1283)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~51) - (DELAY - (ABSOLUTE - (PORT dataa (380:380:380) (459:459:459)) - (PORT datab (1594:1594:1594) (1651:1651:1651)) - (PORT datad (1178:1178:1178) (1221:1221:1221)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (1799:1799:1799) (1855:1855:1855)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (1406:1406:1406) (1476:1476:1476)) - (PORT ena (1131:1131:1131) (1098:1098:1098)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~52) - (DELAY - (ABSOLUTE - (PORT dataa (416:416:416) (478:478:478)) - (PORT datab (881:881:881) (916:916:916)) - (PORT datad (364:364:364) (384:384:384)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~55) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (338:338:338) (368:368:368)) - (PORT datac (804:804:804) (808:808:808)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1537:1537:1537)) - (PORT asdata (1448:1448:1448) (1498:1498:1498)) - (PORT ena (973:973:973) (964:964:964)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1537:1537:1537)) - (PORT asdata (1448:1448:1448) (1501:1501:1501)) - (PORT ena (990:990:990) (994:994:994)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~49) - (DELAY - (ABSOLUTE - (PORT dataa (462:462:462) (518:518:518)) - (PORT datab (240:240:240) (322:322:322)) - (PORT datad (458:458:458) (504:504:504)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (1721:1721:1721) (1779:1779:1779)) - (PORT ena (1400:1400:1400) (1413:1413:1413)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (1723:1723:1723) (1782:1782:1782)) - (PORT ena (1388:1388:1388) (1427:1427:1427)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~50) - (DELAY - (ABSOLUTE - (PORT dataa (931:931:931) (989:989:989)) - (PORT datab (243:243:243) (326:326:326)) - (PORT datad (883:883:883) (941:941:941)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (1771:1771:1771) (1829:1829:1829)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[5\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (928:928:928) (989:989:989)) - (PORT datab (1220:1220:1220) (1296:1296:1296)) - (PORT datad (884:884:884) (944:944:944)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~56) - (DELAY - (ABSOLUTE - (PORT dataa (655:655:655) (699:699:699)) - (PORT datab (825:825:825) (869:869:869)) - (PORT datac (606:606:606) (632:632:632)) - (PORT datad (842:842:842) (848:848:848)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~57) - (DELAY - (ABSOLUTE - (PORT dataa (884:884:884) (946:946:946)) - (PORT datab (197:197:197) (234:234:234)) - (PORT datac (817:817:817) (863:863:863)) - (PORT datad (1298:1298:1298) (1332:1332:1332)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1535:1535:1535) (1554:1554:1554)) - (PORT asdata (1159:1159:1159) (1205:1205:1205)) - (PORT ena (935:935:935) (924:924:924)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (410:410:410) (459:459:459)) - (PORT datab (218:218:218) (256:256:256)) - (PORT datad (386:386:386) (413:413:413)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1308:1308:1308) (1303:1303:1303)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (673:673:673) (716:716:716)) - (PORT datab (379:379:379) (421:421:421)) - (PORT datac (215:215:215) (292:292:292)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (567:567:567) (582:582:582)) - (PORT datab (844:844:844) (883:883:883)) - (PORT datac (682:682:682) (722:722:722)) - (PORT datad (173:173:173) (197:197:197)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[13\]) - (DELAY - (ABSOLUTE - (PORT datab (383:383:383) (425:425:425)) - (PORT datac (886:886:886) (918:918:918)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|Q\[13\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (335:335:335) (352:352:352)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[13\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1581:1581:1581) (1561:1561:1561)) - (PORT ena (2058:2058:2058) (2109:2109:2109)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_53\~0) - (DELAY - (ABSOLUTE - (PORT datac (258:258:258) (345:345:345)) - (PORT datad (869:869:869) (891:891:891)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[15\]) - (DELAY - (ABSOLUTE - (PORT datac (356:356:356) (377:377:377)) - (PORT datad (867:867:867) (889:889:889)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[15\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1581:1581:1581) (1561:1561:1561)) - (PORT ena (2058:2058:2058) (2109:2109:2109)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[14\]) - (DELAY - (ABSOLUTE - (PORT dataa (290:290:290) (385:385:385)) - (PORT datab (215:215:215) (260:260:260)) - (PORT datac (245:245:245) (326:326:326)) - (PORT datad (866:866:866) (891:891:891)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1308:1308:1308) (1303:1303:1303)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1537:1537:1537)) - (PORT asdata (2284:2284:2284) (2422:2422:2422)) - (PORT ena (990:990:990) (994:994:994)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1537:1537:1537)) - (PORT asdata (2284:2284:2284) (2422:2422:2422)) - (PORT ena (973:973:973) (964:964:964)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~76) - (DELAY - (ABSOLUTE - (PORT dataa (461:461:461) (524:524:524)) - (PORT datab (491:491:491) (541:541:541)) - (PORT datad (217:217:217) (286:286:286)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1534:1534:1534)) - (PORT asdata (1879:1879:1879) (1975:1975:1975)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~80) - (DELAY - (ABSOLUTE - (PORT dataa (818:818:818) (835:835:835)) - (PORT datab (1168:1168:1168) (1216:1216:1216)) - (PORT datad (239:239:239) (281:281:281)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (1192:1192:1192) (1258:1258:1258)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (2131:2131:2131) (2211:2211:2211)) - (PORT ena (1131:1131:1131) (1098:1098:1098)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~79) - (DELAY - (ABSOLUTE - (PORT dataa (390:390:390) (460:460:460)) - (PORT datab (883:883:883) (917:917:917)) - (PORT datad (364:364:364) (384:384:384)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (1453:1453:1453) (1497:1497:1497)) - (PORT ena (1283:1283:1283) (1283:1283:1283)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (1453:1453:1453) (1497:1497:1497)) - (PORT ena (1193:1193:1193) (1176:1176:1176)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~78) - (DELAY - (ABSOLUTE - (PORT dataa (1297:1297:1297) (1353:1353:1353)) - (PORT datab (1218:1218:1218) (1255:1255:1255)) - (PORT datad (214:214:214) (282:282:282)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1535:1535:1535) (1554:1554:1554)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1461:1461:1461) (1468:1468:1468)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (2133:2133:2133) (2211:2211:2211)) - (PORT ena (1261:1261:1261) (1299:1299:1299)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~81) - (DELAY - (ABSOLUTE - (PORT dataa (1100:1100:1100) (1146:1146:1146)) - (PORT datab (681:681:681) (756:756:756)) - (PORT datad (848:848:848) (874:874:874)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~82) - (DELAY - (ABSOLUTE - (PORT dataa (605:605:605) (624:624:624)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (595:595:595) (612:612:612)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (1205:1205:1205) (1270:1270:1270)) - (PORT ena (1388:1388:1388) (1427:1427:1427)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (1205:1205:1205) (1270:1270:1270)) - (PORT ena (1400:1400:1400) (1413:1413:1413)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~77) - (DELAY - (ABSOLUTE - (PORT dataa (930:930:930) (985:985:985)) - (PORT datab (912:912:912) (982:982:982)) - (PORT datad (216:216:216) (284:284:284)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (2162:2162:2162) (2212:2212:2212)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[6\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (939:939:939) (997:997:997)) - (PORT datab (1220:1220:1220) (1296:1296:1296)) - (PORT datad (879:879:879) (940:940:940)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~83) - (DELAY - (ABSOLUTE - (PORT dataa (634:634:634) (650:650:650)) - (PORT datab (632:632:632) (657:657:657)) - (PORT datac (489:489:489) (507:507:507)) - (PORT datad (173:173:173) (197:197:197)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~84) - (DELAY - (ABSOLUTE - (PORT dataa (879:879:879) (944:944:944)) - (PORT datab (672:672:672) (688:688:688)) - (PORT datac (786:786:786) (839:839:839)) - (PORT datad (1301:1301:1301) (1333:1333:1333)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1535:1535:1535) (1554:1554:1554)) - (PORT asdata (1132:1132:1132) (1183:1183:1183)) - (PORT ena (935:935:935) (924:924:924)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (410:410:410) (466:466:466)) - (PORT datab (218:218:218) (258:258:258)) - (PORT datad (382:382:382) (412:412:412)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (245:245:245) (332:332:332)) - (PORT datab (670:670:670) (688:688:688)) - (PORT datad (645:645:645) (672:672:672)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (366:366:366) (401:401:401)) - (PORT datab (712:712:712) (754:754:754)) - (PORT datac (808:808:808) (840:840:840)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[14\]) - (DELAY - (ABSOLUTE - (PORT dataa (916:916:916) (955:955:955)) - (PORT datac (361:361:361) (395:395:395)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|Q\[14\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (320:320:320) (331:331:331)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[14\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1581:1581:1581) (1561:1561:1561)) - (PORT ena (2058:2058:2058) (2109:2109:2109)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_16) - (DELAY - (ABSOLUTE - (PORT dataa (1141:1141:1141) (1169:1169:1169)) - (PORT datab (404:404:404) (477:477:477)) - (PORT datac (1110:1110:1110) (1117:1117:1117)) - (PORT datad (632:632:632) (663:663:663)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[15\]) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (214:214:214) (258:258:258)) - (PORT datac (232:232:232) (316:316:316)) - (PORT datad (339:339:339) (360:360:360)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (379:379:379) (417:417:417)) - (PORT datab (712:712:712) (760:760:760)) - (PORT datac (814:814:814) (847:847:847)) - (PORT datad (550:550:550) (569:569:569)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~75) - (DELAY - (ABSOLUTE - (PORT dataa (880:880:880) (950:950:950)) - (PORT datab (664:664:664) (704:704:704)) - (PORT datac (792:792:792) (834:834:834)) - (PORT datad (1297:1297:1297) (1337:1337:1337)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[7\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (1297:1297:1297) (1347:1347:1347)) - (PORT datab (973:973:973) (1026:1026:1026)) - (PORT datac (1877:1877:1877) (1946:1946:1946)) - (PORT datad (831:831:831) (844:844:844)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[7\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (204:204:204) (249:249:249)) - (PORT datab (256:256:256) (314:314:314)) - (PORT datac (1193:1193:1193) (1204:1204:1204)) - (PORT datad (945:945:945) (989:989:989)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~1) - (DELAY - (ABSOLUTE - (PORT dataa (933:933:933) (970:970:970)) - (PORT datab (1223:1223:1223) (1296:1296:1296)) - (PORT datac (905:905:905) (924:924:924)) - (PORT datad (1385:1385:1385) (1451:1451:1451)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~0) - (DELAY - (ABSOLUTE - (PORT dataa (893:893:893) (902:902:902)) - (PORT datab (661:661:661) (697:697:697)) - (PORT datac (670:670:670) (697:697:697)) - (PORT datad (675:675:675) (694:694:694)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1512:1512:1512) (1612:1612:1612)) - (PORT datab (1393:1393:1393) (1508:1508:1508)) - (PORT datac (1411:1411:1411) (1459:1459:1459)) - (PORT datad (835:835:835) (870:870:870)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (608:608:608) (635:635:635)) - (PORT datab (198:198:198) (238:238:238)) - (PORT datac (194:194:194) (228:228:228)) - (PORT datad (1083:1083:1083) (1127:1127:1127)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1159:1159:1159) (1199:1199:1199)) - (PORT datab (1007:1007:1007) (1063:1063:1063)) - (PORT datac (212:212:212) (252:252:252)) - (PORT datad (1995:1995:1995) (2085:2085:2085)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (211:211:211) (260:260:260)) - (PORT datab (634:634:634) (650:650:650)) - (PORT datac (599:599:599) (616:616:616)) - (PORT datad (610:610:610) (626:626:626)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~2) - (DELAY - (ABSOLUTE - (PORT datab (701:701:701) (761:761:761)) - (PORT datac (1331:1331:1331) (1352:1352:1352)) - (PORT datad (1148:1148:1148) (1179:1179:1179)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1693:1693:1693) (1732:1732:1732)) - (PORT datab (1474:1474:1474) (1569:1569:1569)) - (PORT datac (2562:2562:2562) (2664:2664:2664)) - (PORT datad (1898:1898:1898) (2017:2017:2017)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1942:1942:1942) (2062:2062:2062)) - (PORT datab (198:198:198) (236:236:236)) - (PORT datac (918:918:918) (965:965:965)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~1) - (DELAY - (ABSOLUTE - (PORT dataa (634:634:634) (664:664:664)) - (PORT datab (640:640:640) (658:658:658)) - (PORT datad (880:880:880) (936:936:936)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf) - (DELAY - (ABSOLUTE - (PORT clk (1511:1511:1511) (1525:1525:1525)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1199:1199:1199) (1286:1286:1286)) - (PORT datab (255:255:255) (340:340:340)) - (PORT datac (1353:1353:1353) (1415:1415:1415)) - (PORT datad (1199:1199:1199) (1262:1262:1262)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~2) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (196:196:196) (235:235:235)) - (PORT datad (1171:1171:1171) (1244:1244:1244)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~5) - (DELAY - (ABSOLUTE - (PORT datab (219:219:219) (259:259:259)) - (PORT datac (882:882:882) (919:919:919)) - (PORT datad (1382:1382:1382) (1453:1453:1453)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (416:416:416) (442:442:442)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (896:896:896) (932:932:932)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (423:423:423) (511:511:511)) - (PORT datab (1166:1166:1166) (1210:1210:1210)) - (PORT datac (593:593:593) (646:646:646)) - (PORT datad (662:662:662) (719:719:719)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (1177:1177:1177) (1208:1208:1208)) - (PORT datab (281:281:281) (344:344:344)) - (PORT datac (245:245:245) (304:304:304)) - (PORT datad (256:256:256) (301:301:301)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (342:342:342) (378:378:378)) - (PORT datab (802:802:802) (831:831:831)) - (PORT datac (498:498:498) (504:504:504)) - (PORT datad (1104:1104:1104) (1147:1147:1147)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (600:600:600) (639:639:639)) - (PORT datab (999:999:999) (1033:1033:1033)) - (PORT datac (589:589:589) (604:604:604)) - (PORT datad (221:221:221) (264:264:264)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[3\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (378:378:378) (404:404:404)) - (PORT datab (893:893:893) (942:942:942)) - (PORT datac (1167:1167:1167) (1166:1166:1166)) - (PORT datad (680:680:680) (715:715:715)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_low\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (695:695:695) (756:756:756)) - (PORT datab (1177:1177:1177) (1222:1222:1222)) - (PORT datac (613:613:613) (678:678:678)) - (PORT datad (666:666:666) (725:725:725)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\~2) - (DELAY - (ABSOLUTE - (PORT datab (288:288:288) (350:350:350)) - (PORT datad (251:251:251) (296:296:296)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (285:285:285) (347:347:347)) - (PORT datab (620:620:620) (638:638:638)) - (PORT datac (1141:1141:1141) (1167:1167:1167)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|result_lo\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1535:1535:1535)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1283:1283:1283) (1287:1287:1287)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (968:968:968) (996:996:996)) - (PORT datac (1660:1660:1660) (1742:1742:1742)) - (PORT datad (1418:1418:1418) (1445:1445:1445)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1138:1138:1138) (1168:1168:1168)) - (PORT datab (1129:1129:1129) (1182:1182:1182)) - (PORT datac (171:171:171) (205:205:205)) - (PORT datad (241:241:241) (282:282:282)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (522:522:522) (538:538:538)) - (PORT datab (879:879:879) (956:956:956)) - (PORT datac (959:959:959) (990:990:990)) - (PORT datad (594:594:594) (608:608:608)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (1196:1196:1196) (1243:1243:1243)) - (PORT datab (609:609:609) (645:645:645)) - (PORT datac (193:193:193) (235:235:235)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[3\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (669:669:669) (695:695:695)) - (PORT datab (912:912:912) (959:959:959)) - (PORT datac (854:854:854) (883:883:883)) - (PORT datad (1144:1144:1144) (1179:1179:1179)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[3\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (638:638:638) (678:678:678)) - (PORT datab (961:961:961) (1023:1023:1023)) - (PORT datac (1152:1152:1152) (1178:1178:1178)) - (PORT datad (225:225:225) (270:270:270)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~7) - (DELAY - (ABSOLUTE - (PORT dataa (230:230:230) (279:279:279)) - (PORT datab (1448:1448:1448) (1517:1517:1517)) - (PORT datac (1115:1115:1115) (1163:1163:1163)) - (PORT datad (178:178:178) (206:206:206)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~49) - (DELAY - (ABSOLUTE - (PORT dataa (1187:1187:1187) (1261:1261:1261)) - (PORT datab (930:930:930) (959:959:959)) - (PORT datac (533:533:533) (553:553:553)) - (PORT datad (844:844:844) (856:856:856)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_oe\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1441:1441:1441) (1548:1548:1548)) - (PORT datab (218:218:218) (257:257:257)) - (PORT datac (235:235:235) (277:277:277)) - (PORT datad (1401:1401:1401) (1453:1453:1453)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_35) - (DELAY - (ABSOLUTE - (PORT dataa (645:645:645) (663:663:663)) - (PORT datab (615:615:615) (664:664:664)) - (PORT datac (664:664:664) (693:693:693)) - (PORT datad (680:680:680) (701:701:701)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~7) - (DELAY - (ABSOLUTE - (PORT datab (614:614:614) (644:644:644)) - (PORT datad (801:801:801) (877:877:877)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla69M2T2_3) - (DELAY - (ABSOLUTE - (PORT dataa (640:640:640) (665:665:665)) - (PORT datab (2306:2306:2306) (2385:2385:2385)) - (PORT datac (2054:2054:2054) (2198:2198:2198)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~13) - (DELAY - (ABSOLUTE - (PORT dataa (377:377:377) (426:426:426)) - (PORT datab (1624:1624:1624) (1701:1701:1701)) - (PORT datac (829:829:829) (848:848:848)) - (PORT datad (180:180:180) (209:209:209)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~14) - (DELAY - (ABSOLUTE - (PORT dataa (816:816:816) (877:877:877)) - (PORT datab (360:360:360) (396:396:396)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (182:182:182) (211:211:211)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~15) - (DELAY - (ABSOLUTE - (PORT dataa (930:930:930) (1002:1002:1002)) - (PORT datab (692:692:692) (710:710:710)) - (PORT datac (563:563:563) (586:586:586)) - (PORT datad (616:616:616) (630:630:630)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|flags_xf) - (DELAY - (ABSOLUTE - (PORT clk (1514:1514:1514) (1528:1528:1528)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[3\]\~33) - (DELAY - (ABSOLUTE - (PORT datab (957:957:957) (981:981:981)) - (PORT datac (645:645:645) (694:694:694)) - (PORT datad (656:656:656) (712:712:712)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~3) - (DELAY - (ABSOLUTE - (PORT dataa (348:348:348) (378:378:378)) - (PORT datab (209:209:209) (251:251:251)) - (PORT datac (177:177:177) (213:213:213)) - (PORT datad (652:652:652) (692:692:692)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla23pla16M3T1_5\~0) - (DELAY - (ABSOLUTE - (PORT dataa (887:887:887) (904:904:904)) - (PORT datab (994:994:994) (1026:1026:1026)) - (PORT datac (1433:1433:1433) (1520:1520:1520)) - (PORT datad (1142:1142:1142) (1160:1160:1160)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~4) - (DELAY - (ABSOLUTE - (PORT dataa (644:644:644) (697:697:697)) - (PORT datab (936:936:936) (950:950:950)) - (PORT datac (1455:1455:1455) (1497:1497:1497)) - (PORT datad (1163:1163:1163) (1183:1183:1183)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~5) - (DELAY - (ABSOLUTE - (PORT dataa (631:631:631) (638:638:638)) - (PORT datab (207:207:207) (248:248:248)) - (PORT datac (881:881:881) (909:909:909)) - (PORT datad (194:194:194) (219:219:219)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~8) - (DELAY - (ABSOLUTE - (PORT datab (1639:1639:1639) (1704:1704:1704)) - (PORT datac (1440:1440:1440) (1481:1481:1481)) - (PORT datad (1160:1160:1160) (1199:1199:1199)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sw1_\|db_down\[3\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (362:362:362) (500:500:500)) - (PORT datab (1223:1223:1223) (1282:1282:1282)) - (PORT datac (1145:1145:1145) (1179:1179:1179)) - (PORT datad (899:899:899) (938:938:938)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[3\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (868:868:868) (917:917:917)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (870:870:870) (900:900:900)) - (PORT datad (616:616:616) (665:665:665)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[3\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (622:622:622) (647:647:647)) - (PORT datab (247:247:247) (295:295:295)) - (PORT datac (1154:1154:1154) (1184:1184:1184)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~46) - (DELAY - (ABSOLUTE - (PORT dataa (474:474:474) (512:512:512)) - (PORT datab (1141:1141:1141) (1188:1188:1188)) - (PORT datad (1463:1463:1463) (1479:1479:1479)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~47) - (DELAY - (ABSOLUTE - (PORT dataa (421:421:421) (486:486:486)) - (PORT datac (173:173:173) (206:206:206)) - (PORT datad (1618:1618:1618) (1617:1617:1617)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~50) - (DELAY - (ABSOLUTE - (PORT datab (353:353:353) (390:390:390)) - (PORT datac (784:784:784) (794:794:794)) - (PORT datad (320:320:320) (341:341:341)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1531:1531:1531)) - (PORT asdata (970:970:970) (1022:1022:1022)) - (PORT ena (1413:1413:1413) (1385:1385:1385)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1531:1531:1531)) - (PORT asdata (970:970:970) (1022:1022:1022)) - (PORT ena (1734:1734:1734) (1719:1719:1719)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~44) - (DELAY - (ABSOLUTE - (PORT dataa (247:247:247) (336:336:336)) - (PORT datab (975:975:975) (1029:1029:1029)) - (PORT datad (845:845:845) (875:875:875)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (868:868:868) (877:877:877)) - (PORT ena (811:811:811) (804:804:804)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (869:869:869) (877:877:877)) - (PORT ena (841:841:841) (846:846:846)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~43) - (DELAY - (ABSOLUTE - (PORT dataa (246:246:246) (333:333:333)) - (PORT datab (260:260:260) (314:314:314)) - (PORT datad (229:229:229) (267:267:267)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~51) - (DELAY - (ABSOLUTE - (PORT dataa (858:858:858) (870:870:870)) - (PORT datab (202:202:202) (242:242:242)) - (PORT datac (607:607:607) (626:626:626)) - (PORT datad (625:625:625) (639:639:639)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~52) - (DELAY - (ABSOLUTE - (PORT dataa (858:858:858) (895:895:895)) - (PORT datab (609:609:609) (627:627:627)) - (PORT datac (332:332:332) (359:359:359)) - (PORT datad (1115:1115:1115) (1138:1138:1138)) - (IOPATH dataa combout (300:300:300) (307:307:307)) + (PORT datab (1375:1375:1375) (1436:1436:1436)) + (PORT datac (1062:1062:1062) (1107:1107:1107)) + (PORT datad (181:181:181) (210:210:210)) (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (957:957:957) (1002:1002:1002)) - (PORT ena (1201:1201:1201) (1184:1184:1184)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1331:1331:1331) (1374:1374:1374)) - (PORT datab (697:697:697) (731:731:731)) - (PORT datad (1194:1194:1194) (1238:1238:1238)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1541:1541:1541) (1557:1557:1557)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1283:1283:1283) (1286:1286:1286)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (609:609:609) (669:669:669)) - (PORT datac (704:704:704) (742:742:742)) - (PORT datad (220:220:220) (290:290:290)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (379:379:379) (401:401:401)) - (PORT datab (960:960:960) (999:999:999)) - (PORT datac (683:683:683) (718:718:718)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[3\]) - (DELAY - (ABSOLUTE - (PORT datab (240:240:240) (286:286:286)) - (PORT datac (548:548:548) (560:560:560)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1541:1541:1541) (1557:1557:1557)) - (PORT asdata (870:870:870) (882:882:882)) - (PORT clrn (1597:1597:1597) (1572:1572:1572)) - (PORT ena (2143:2143:2143) (2210:2210:2210)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_45\~4) - (DELAY - (ABSOLUTE - (PORT dataa (387:387:387) (429:429:429)) - (PORT datab (1153:1153:1153) (1183:1183:1183)) - (PORT datac (963:963:963) (1032:1032:1032)) - (PORT datad (244:244:244) (316:316:316)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|carry_borrow_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (350:350:350) (392:392:392)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (340:340:340) (367:367:367)) - (PORT datad (324:324:324) (346:346:346)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_4\|d0_out) - (DELAY - (ABSOLUTE - (PORT dataa (265:265:265) (352:352:352)) - (PORT datab (206:206:206) (248:248:248)) - (PORT datac (332:332:332) (358:358:358)) - (PORT datad (196:196:196) (221:221:221)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (1239:1239:1239) (1260:1260:1260)) - (PORT ena (811:811:811) (804:804:804)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (1236:1236:1236) (1256:1256:1256)) - (PORT ena (841:841:841) (846:846:846)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~53) - (DELAY - (ABSOLUTE - (PORT dataa (244:244:244) (331:331:331)) - (PORT datab (258:258:258) (310:310:310)) - (PORT datad (228:228:228) (266:266:266)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~54) - (DELAY - (ABSOLUTE - (PORT dataa (635:635:635) (663:663:663)) - (PORT datab (1133:1133:1133) (1182:1182:1182)) - (PORT datad (630:630:630) (644:644:644)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1545:1545:1545)) - (PORT asdata (1202:1202:1202) (1222:1222:1222)) - (PORT ena (821:821:821) (834:834:834)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1545:1545:1545)) - (PORT asdata (1206:1206:1206) (1227:1227:1227)) - (PORT ena (1266:1266:1266) (1269:1269:1269)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~58) - (DELAY - (ABSOLUTE - (PORT dataa (408:408:408) (466:466:466)) - (PORT datab (591:591:591) (631:631:631)) - (PORT datad (218:218:218) (288:288:288)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1534:1534:1534)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1505:1505:1505) (1518:1518:1518)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1520:1520:1520) (1534:1534:1534)) - (PORT asdata (958:958:958) (967:967:967)) - (PORT ena (1207:1207:1207) (1190:1190:1190)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1520:1520:1520) (1534:1534:1534)) - (PORT asdata (960:960:960) (969:969:969)) - (PORT ena (1263:1263:1263) (1264:1264:1264)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~59) - (DELAY - (ABSOLUTE - (PORT dataa (467:467:467) (505:505:505)) - (PORT datab (668:668:668) (703:703:703)) - (PORT datad (216:216:216) (284:284:284)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~60) - (DELAY - (ABSOLUTE - (PORT dataa (646:646:646) (665:665:665)) - (PORT datab (920:920:920) (943:943:943)) - (PORT datac (213:213:213) (288:288:288)) - (PORT datad (335:335:335) (356:356:356)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1531:1531:1531)) - (PORT asdata (993:993:993) (1020:1020:1020)) - (PORT ena (1734:1734:1734) (1719:1719:1719)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1531:1531:1531)) - (PORT asdata (995:995:995) (1022:1022:1022)) - (PORT ena (1413:1413:1413) (1385:1385:1385)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~57) - (DELAY - (ABSOLUTE - (PORT dataa (875:875:875) (922:922:922)) - (PORT datab (965:965:965) (1021:1021:1021)) - (PORT datad (217:217:217) (286:286:286)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1545:1545:1545)) - (PORT asdata (984:984:984) (1006:1006:1006)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1545:1545:1545)) - (PORT asdata (982:982:982) (1003:1003:1003)) - (PORT ena (1220:1220:1220) (1214:1214:1214)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~55) - (DELAY - (ABSOLUTE - (PORT dataa (645:645:645) (700:700:700)) - (PORT datab (396:396:396) (436:436:436)) - (PORT datad (215:215:215) (283:283:283)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1534:1534:1534)) - (PORT asdata (875:875:875) (882:882:882)) - (PORT ena (1407:1407:1407) (1382:1382:1382)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~56) - (DELAY - (ABSOLUTE - (PORT dataa (527:527:527) (547:547:547)) - (PORT datad (825:825:825) (835:835:835)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~61) - (DELAY - (ABSOLUTE - (PORT dataa (340:340:340) (377:377:377)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (1018:1018:1018) (1019:1019:1019)) - (PORT datad (173:173:173) (197:197:197)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~62) - (DELAY - (ABSOLUTE - (PORT dataa (198:198:198) (241:241:241)) - (PORT datab (856:856:856) (875:875:875)) - (PORT datac (1094:1094:1094) (1126:1126:1126)) - (PORT datad (1162:1162:1162) (1190:1190:1190)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (1359:1359:1359) (1370:1370:1370)) - (PORT ena (1201:1201:1201) (1184:1184:1184)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (889:889:889) (911:911:911)) - (PORT datab (1236:1236:1236) (1275:1275:1275)) - (PORT datad (664:664:664) (688:688:688)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1541:1541:1541) (1557:1557:1557)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1283:1283:1283) (1286:1286:1286)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~14) - (DELAY - (ABSOLUTE - (PORT datab (624:624:624) (675:675:675)) - (PORT datac (704:704:704) (739:739:739)) - (PORT datad (216:216:216) (285:285:285)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (379:379:379) (401:401:401)) - (PORT datab (959:959:959) (1001:1001:1001)) - (PORT datac (682:682:682) (721:721:721)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[4\]) - (DELAY - (ABSOLUTE - (PORT datab (238:238:238) (283:283:283)) - (PORT datad (529:529:529) (540:540:540)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1541:1541:1541) (1557:1557:1557)) - (PORT asdata (852:852:852) (858:858:858)) - (PORT clrn (1597:1597:1597) (1572:1572:1572)) - (PORT ena (2143:2143:2143) (2210:2210:2210)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_44) - (DELAY - (ABSOLUTE - (PORT dataa (1155:1155:1155) (1182:1182:1182)) - (PORT datab (985:985:985) (1022:1022:1022)) - (PORT datad (201:201:201) (229:229:229)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_4\|d1_out) - (DELAY - (ABSOLUTE - (PORT dataa (710:710:710) (770:770:770)) - (PORT datab (1162:1162:1162) (1199:1199:1199)) - (PORT datac (626:626:626) (647:647:647)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1531:1531:1531)) - (PORT asdata (879:879:879) (891:891:891)) - (PORT ena (1413:1413:1413) (1385:1385:1385)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1531:1531:1531)) - (PORT asdata (878:878:878) (893:893:893)) - (PORT ena (1734:1734:1734) (1719:1719:1719)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~64) - (DELAY - (ABSOLUTE - (PORT dataa (244:244:244) (331:331:331)) - (PORT datab (966:966:966) (1022:1022:1022)) - (PORT datad (843:843:843) (873:873:873)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1517:1517:1517) (1531:1531:1531)) - (PORT asdata (692:692:692) (715:715:715)) - (PORT ena (1477:1477:1477) (1472:1472:1472)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1517:1517:1517) (1531:1531:1531)) - (PORT asdata (692:692:692) (713:713:713)) - (PORT ena (1247:1247:1247) (1263:1263:1263)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~63) - (DELAY - (ABSOLUTE - (PORT dataa (1095:1095:1095) (1134:1134:1134)) - (PORT datab (241:241:241) (323:323:323)) - (PORT datad (658:658:658) (679:679:679)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1534:1534:1534)) - (PORT asdata (1437:1437:1437) (1460:1460:1460)) - (PORT ena (1505:1505:1505) (1518:1518:1518)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1520:1520:1520) (1534:1534:1534)) - (PORT asdata (1457:1457:1457) (1472:1472:1472)) - (PORT ena (1207:1207:1207) (1190:1190:1190)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~66) - (DELAY - (ABSOLUTE - (PORT dataa (458:458:458) (494:494:494)) - (PORT datab (1132:1132:1132) (1177:1177:1177)) - (PORT datad (626:626:626) (636:636:636)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~67) - (DELAY - (ABSOLUTE - (PORT datab (918:918:918) (940:940:940)) - (PORT datad (338:338:338) (359:359:359)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1545:1545:1545)) - (PORT asdata (1214:1214:1214) (1217:1217:1217)) - (PORT ena (821:821:821) (834:834:834)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1545:1545:1545)) - (PORT asdata (1214:1214:1214) (1215:1215:1215)) - (PORT ena (1266:1266:1266) (1269:1269:1269)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~65) - (DELAY - (ABSOLUTE - (PORT dataa (409:409:409) (467:467:467)) - (PORT datab (592:592:592) (632:632:632)) - (PORT datad (216:216:216) (284:284:284)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1545:1545:1545)) - (PORT asdata (1471:1471:1471) (1477:1477:1477)) - (PORT ena (1220:1220:1220) (1214:1214:1214)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[5\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (607:607:607) (622:622:622)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~69) - (DELAY - (ABSOLUTE - (PORT dataa (641:641:641) (693:693:693)) - (PORT datab (390:390:390) (429:429:429)) - (PORT datad (215:215:215) (283:283:283)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[5\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (853:853:853) (859:859:859)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1534:1534:1534)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1407:1407:1407) (1382:1382:1382)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1520:1520:1520) (1534:1534:1534)) - (PORT asdata (1457:1457:1457) (1474:1474:1474)) - (PORT ena (1263:1263:1263) (1264:1264:1264)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~68) - (DELAY - (ABSOLUTE - (PORT dataa (574:574:574) (638:638:638)) - (PORT datab (836:836:836) (860:860:860)) - (PORT datad (645:645:645) (669:669:669)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~70) - (DELAY - (ABSOLUTE - (PORT dataa (638:638:638) (656:656:656)) - (PORT datab (1118:1118:1118) (1148:1148:1148)) - (PORT datac (339:339:339) (359:359:359)) - (PORT datad (587:587:587) (601:601:601)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~71) - (DELAY - (ABSOLUTE - (PORT dataa (372:372:372) (394:394:394)) - (PORT datac (170:170:170) (203:203:203)) - (PORT datad (175:175:175) (202:202:202)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~72) - (DELAY - (ABSOLUTE - (PORT dataa (639:639:639) (699:699:699)) - (PORT datab (929:929:929) (992:992:992)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (1608:1608:1608) (1611:1611:1611)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (1227:1227:1227) (1243:1243:1243)) - (PORT ena (1201:1201:1201) (1184:1184:1184)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[5\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1190:1190:1190) (1197:1197:1197)) - (PORT datab (1236:1236:1236) (1275:1275:1275)) - (PORT datad (664:664:664) (688:688:688)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1553:1553:1553)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (811:811:811) (804:804:804)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[5\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (229:229:229) (275:275:275)) - (PORT datac (613:613:613) (632:632:632)) - (PORT datad (219:219:219) (288:288:288)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[5\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (655:655:655) (670:670:670)) - (PORT datab (1331:1331:1331) (1335:1335:1335)) - (PORT datac (192:192:192) (224:224:224)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[5\]) - (DELAY - (ABSOLUTE - (PORT datac (653:653:653) (693:693:693)) - (PORT datad (834:834:834) (843:843:843)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1560:1560:1560)) - (PORT ena (2152:2152:2152) (2220:2220:2220)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_43\~4) - (DELAY - (ABSOLUTE - (PORT dataa (920:920:920) (994:994:994)) - (PORT datab (1154:1154:1154) (1178:1178:1178)) - (PORT datac (960:960:960) (1026:1026:1026)) - (PORT datad (362:362:362) (387:387:387)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[6\]) - (DELAY - (ABSOLUTE - (PORT dataa (657:657:657) (687:687:687)) - (PORT datab (1161:1161:1161) (1198:1198:1198)) - (PORT datac (811:811:811) (865:865:865)) - (PORT datad (615:615:615) (643:643:643)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1541:1541:1541) (1557:1557:1557)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1283:1283:1283) (1286:1286:1286)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1531:1531:1531)) - (PORT asdata (1676:1676:1676) (1684:1684:1684)) - (PORT ena (1734:1734:1734) (1719:1719:1719)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[6\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1342:1342:1342) (1345:1345:1345)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1413:1413:1413) (1385:1385:1385)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~74) - (DELAY - (ABSOLUTE - (PORT dataa (870:870:870) (918:918:918)) - (PORT datab (966:966:966) (1020:1020:1020)) - (PORT datad (217:217:217) (285:285:285)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1517:1517:1517) (1531:1531:1531)) - (PORT asdata (1896:1896:1896) (1881:1881:1881)) - (PORT ena (1477:1477:1477) (1472:1472:1472)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1517:1517:1517) (1531:1531:1531)) - (PORT asdata (1893:1893:1893) (1878:1878:1878)) - (PORT ena (1247:1247:1247) (1263:1263:1263)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~73) - (DELAY - (ABSOLUTE - (PORT dataa (1092:1092:1092) (1133:1133:1133)) - (PORT datab (241:241:241) (323:323:323)) - (PORT datad (654:654:654) (676:676:676)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1544:1544:1544)) - (PORT asdata (2168:2168:2168) (2154:2154:2154)) - (PORT ena (1231:1231:1231) (1217:1217:1217)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[6\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1053:1053:1053) (1073:1073:1073)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~78) - (DELAY - (ABSOLUTE - (PORT dataa (435:435:435) (470:470:470)) - (PORT datab (637:637:637) (669:669:669)) - (PORT datad (374:374:374) (432:432:432)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1463:1463:1463) (1454:1454:1454)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~79) - (DELAY - (ABSOLUTE - (PORT dataa (689:689:689) (771:771:771)) - (PORT datab (945:945:945) (995:995:995)) - (PORT datac (878:878:878) (894:894:894)) - (PORT datad (606:606:606) (625:625:625)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1544:1544:1544)) - (PORT asdata (2168:2168:2168) (2153:2153:2153)) - (PORT ena (1499:1499:1499) (1507:1507:1507)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[6\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1302:1302:1302) (1310:1310:1310)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1520:1520:1520) (1534:1534:1534)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1263:1263:1263) (1264:1264:1264)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1520:1520:1520) (1534:1534:1534)) - (PORT asdata (1608:1608:1608) (1628:1628:1628)) - (PORT ena (1207:1207:1207) (1190:1190:1190)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~76) - (DELAY - (ABSOLUTE - (PORT dataa (466:466:466) (503:503:503)) - (PORT datab (242:242:242) (324:324:324)) - (PORT datad (640:640:640) (666:666:666)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~77) - (DELAY - (ABSOLUTE - (PORT datab (1410:1410:1410) (1425:1425:1425)) - (PORT datad (563:563:563) (574:574:574)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~80) - (DELAY - (ABSOLUTE - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1545:1545:1545)) - (PORT asdata (1342:1342:1342) (1366:1366:1366)) - (PORT ena (821:821:821) (834:834:834)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (1430:1430:1430) (1466:1466:1466)) - (PORT ena (841:841:841) (846:846:846)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~75) - (DELAY - (ABSOLUTE - (PORT dataa (412:412:412) (471:471:471)) - (PORT datab (584:584:584) (622:622:622)) - (PORT datad (835:835:835) (900:900:900)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~81) - (DELAY - (ABSOLUTE - (PORT dataa (374:374:374) (399:399:399)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (794:794:794) (791:791:791)) - (PORT datad (776:776:776) (774:774:774)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~82) - (DELAY - (ABSOLUTE - (PORT dataa (592:592:592) (625:625:625)) - (PORT datab (658:658:658) (716:716:716)) - (PORT datac (1393:1393:1393) (1416:1416:1416)) - (PORT datad (599:599:599) (618:618:618)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (967:967:967) (1025:1025:1025)) - (PORT ena (1201:1201:1201) (1184:1184:1184)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1322:1322:1322) (1350:1350:1350)) - (PORT datab (1232:1232:1232) (1270:1270:1270)) - (PORT datad (660:660:660) (687:687:687)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~20) - (DELAY - (ABSOLUTE - (PORT datab (673:673:673) (705:705:705)) - (PORT datac (668:668:668) (749:749:749)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (714:714:714) (760:760:760)) - (PORT datab (648:648:648) (689:689:689)) - (PORT datac (926:926:926) (965:965:965)) - (PORT datad (593:593:593) (644:644:644)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[6\]) - (DELAY - (ABSOLUTE - (PORT datac (652:652:652) (694:694:694)) - (PORT datad (819:819:819) (838:838:838)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1560:1560:1560)) - (PORT ena (2152:2152:2152) (2220:2220:2220)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_47\~0) - (DELAY - (ABSOLUTE - (PORT dataa (628:628:628) (670:670:670)) - (PORT datab (632:632:632) (673:673:673)) - (PORT datac (811:811:811) (863:863:863)) - (PORT datad (1165:1165:1165) (1193:1193:1193)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_47) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (242:242:242)) - (PORT datab (1158:1158:1158) (1194:1194:1194)) - (PORT datac (628:628:628) (651:651:651)) - (PORT datad (616:616:616) (644:644:644)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|d0_out) - (DELAY - (ABSOLUTE - (PORT dataa (423:423:423) (515:515:515)) - (PORT datad (190:190:190) (222:222:222)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (708:708:708) (752:752:752)) - (PORT datab (962:962:962) (1002:1002:1002)) - (PORT datac (171:171:171) (203:203:203)) - (PORT datad (619:619:619) (645:645:645)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1517:1517:1517) (1531:1531:1531)) - (PORT asdata (1212:1212:1212) (1251:1251:1251)) - (PORT ena (1477:1477:1477) (1472:1472:1472)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1517:1517:1517) (1531:1531:1531)) - (PORT asdata (1211:1211:1211) (1254:1254:1254)) - (PORT ena (1247:1247:1247) (1263:1263:1263)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~83) - (DELAY - (ABSOLUTE - (PORT dataa (1092:1092:1092) (1137:1137:1137)) - (PORT datab (243:243:243) (325:325:325)) - (PORT datad (656:656:656) (679:679:679)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1531:1531:1531)) - (PORT asdata (1408:1408:1408) (1437:1437:1437)) - (PORT ena (1734:1734:1734) (1719:1719:1719)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1531:1531:1531)) - (PORT asdata (1410:1410:1410) (1439:1439:1439)) - (PORT ena (1413:1413:1413) (1385:1385:1385)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~84) - (DELAY - (ABSOLUTE - (PORT dataa (876:876:876) (924:924:924)) - (PORT datab (963:963:963) (1013:1013:1013)) - (PORT datad (216:216:216) (284:284:284)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1544:1544:1544)) - (PORT asdata (1934:1934:1934) (1968:1968:1968)) - (PORT ena (1231:1231:1231) (1217:1217:1217)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[7\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1624:1624:1624) (1645:1645:1645)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~88) - (DELAY - (ABSOLUTE - (PORT dataa (435:435:435) (469:469:469)) - (PORT datab (636:636:636) (669:669:669)) - (PORT datad (370:370:370) (429:429:429)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1544:1544:1544)) - (PORT asdata (1932:1932:1932) (1967:1967:1967)) - (PORT ena (1499:1499:1499) (1507:1507:1507)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1520:1520:1520) (1534:1534:1534)) - (PORT asdata (1954:1954:1954) (1989:1989:1989)) - (PORT ena (1263:1263:1263) (1264:1264:1264)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1520:1520:1520) (1534:1534:1534)) - (PORT asdata (1954:1954:1954) (1989:1989:1989)) - (PORT ena (1207:1207:1207) (1190:1190:1190)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~86) - (DELAY - (ABSOLUTE - (PORT dataa (459:459:459) (495:495:495)) - (PORT datab (241:241:241) (322:322:322)) - (PORT datad (640:640:640) (664:664:664)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~87) - (DELAY - (ABSOLUTE - (PORT datab (1411:1411:1411) (1427:1427:1427)) - (PORT datad (587:587:587) (598:598:598)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1545:1545:1545)) - (PORT asdata (1731:1731:1731) (1772:1772:1772)) - (PORT ena (821:821:821) (834:834:834)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1545:1545:1545)) - (PORT asdata (1730:1730:1730) (1774:1774:1774)) - (PORT ena (1266:1266:1266) (1269:1269:1269)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~85) - (DELAY - (ABSOLUTE - (PORT dataa (407:407:407) (467:467:467)) - (PORT datab (591:591:591) (631:631:631)) - (PORT datad (216:216:216) (283:283:283)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1463:1463:1463) (1454:1454:1454)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~89) - (DELAY - (ABSOLUTE - (PORT dataa (646:646:646) (738:738:738)) - (PORT datab (944:944:944) (996:996:996)) - (PORT datac (844:844:844) (845:845:845)) - (PORT datad (606:606:606) (623:623:623)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~90) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (242:242:242)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (496:496:496) (503:503:503)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~91) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (364:364:364) (385:385:385)) - (PORT datad (573:573:573) (586:586:586)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~92) - (DELAY - (ABSOLUTE - (PORT dataa (667:667:667) (723:723:723)) - (PORT datab (660:660:660) (704:704:704)) - (PORT datac (1391:1391:1391) (1414:1414:1414)) - (PORT datad (597:597:597) (618:618:618)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_ds\[7\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1484:1484:1484) (1528:1528:1528)) - (PORT datab (1645:1645:1645) (1711:1711:1711)) - (PORT datac (872:872:872) (914:914:914)) - (PORT datad (1163:1163:1163) (1203:1203:1203)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|im2) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1541:1541:1541)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1571:1571:1571) (1550:1550:1550)) - (PORT ena (1258:1258:1258) (1280:1280:1280)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~12) - (DELAY - (ABSOLUTE - (PORT dataa (354:354:354) (492:492:492)) - (PORT datac (1227:1227:1227) (1295:1295:1295)) - (PORT datad (274:274:274) (356:356:356)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_mask543_en\~0) - (DELAY - (ABSOLUTE - (PORT dataa (356:356:356) (494:494:494)) - (PORT datab (716:716:716) (747:747:747)) - (PORT datac (192:192:192) (224:224:224)) - (PORT datad (1301:1301:1301) (1395:1395:1395)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[7\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (881:881:881) (903:903:903)) - (PORT datab (928:928:928) (957:957:957)) - (PORT datac (631:631:631) (687:687:687)) - (PORT datad (632:632:632) (647:647:647)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[7\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (841:841:841) (861:861:861)) - (PORT datab (852:852:852) (879:879:879)) - (PORT datac (900:900:900) (940:940:940)) - (PORT datad (639:639:639) (700:700:700)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[7\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (204:204:204) (249:249:249)) - (PORT datab (244:244:244) (291:291:291)) - (PORT datac (645:645:645) (698:698:698)) - (PORT datad (617:617:617) (628:628:628)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_34) - (DELAY - (ABSOLUTE - (PORT dataa (693:693:693) (738:738:738)) - (PORT datab (889:889:889) (932:932:932)) - (PORT datac (869:869:869) (862:862:862)) - (PORT datad (202:202:202) (231:231:231)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1252:1252:1252) (1344:1344:1344)) - (PORT datab (857:857:857) (911:911:911)) - (PORT datac (614:614:614) (652:652:652)) - (PORT datad (195:195:195) (220:220:220)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_sf) - (DELAY - (ABSOLUTE - (PORT clk (1511:1511:1511) (1525:1525:1525)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (843:843:843) (856:856:856)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal62\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1466:1466:1466) (1594:1594:1594)) - (PORT datab (1469:1469:1469) (1553:1553:1553)) - (PORT datac (1102:1102:1102) (1148:1148:1148)) - (PORT datad (647:647:647) (684:684:684)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1119:1119:1119) (1156:1156:1156)) - (PORT datab (747:747:747) (772:772:772)) - (PORT datac (1394:1394:1394) (1464:1464:1464)) - (PORT datad (1189:1189:1189) (1225:1225:1225)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (929:929:929) (1006:1006:1006)) - (PORT datab (1150:1150:1150) (1220:1220:1220)) - (PORT datac (733:733:733) (829:829:829)) - (PORT datad (1883:1883:1883) (2044:2044:2044)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~7) - (DELAY - (ABSOLUTE - (PORT dataa (737:737:737) (802:802:802)) - (PORT datab (1392:1392:1392) (1509:1509:1509)) - (PORT datac (1112:1112:1112) (1157:1157:1157)) - (PORT datad (198:198:198) (235:235:235)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (653:653:653) (668:668:668)) - (PORT datab (819:819:819) (840:840:840)) - (PORT datac (1123:1123:1123) (1137:1137:1137)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~9) - (DELAY - (ABSOLUTE - (PORT dataa (674:674:674) (696:696:696)) - (PORT datab (1031:1031:1031) (1083:1083:1083)) - (PORT datac (562:562:562) (584:584:584)) - (PORT datad (901:901:901) (957:957:957)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~0) - (DELAY - (ABSOLUTE - (PORT dataa (704:704:704) (741:741:741)) - (PORT datab (618:618:618) (633:633:633)) - (PORT datac (237:237:237) (315:315:315)) - (PORT datad (181:181:181) (212:212:212)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1120:1120:1120) (1156:1156:1156)) - (PORT datab (746:746:746) (770:770:770)) - (PORT datac (899:899:899) (956:956:956)) - (PORT datad (1169:1169:1169) (1206:1206:1206)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1433:1433:1433) (1488:1488:1488)) - (PORT datab (677:677:677) (711:711:711)) - (PORT datac (171:171:171) (203:203:203)) - (PORT datad (1402:1402:1402) (1440:1440:1440)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1422:1422:1422) (1463:1463:1463)) - (PORT datab (746:746:746) (770:770:770)) - (PORT datac (1125:1125:1125) (1193:1193:1193)) - (PORT datad (171:171:171) (196:196:196)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~0) - (DELAY - (ABSOLUTE - (PORT dataa (415:415:415) (496:496:496)) - (PORT datab (268:268:268) (357:357:357)) - (PORT datac (230:230:230) (313:313:313)) - (PORT datad (609:609:609) (655:655:655)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~3) - (DELAY - (ABSOLUTE - (PORT dataa (845:845:845) (908:908:908)) - (PORT datab (730:730:730) (816:816:816)) - (PORT datad (395:395:395) (453:453:453)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~2) - (DELAY - (ABSOLUTE - (PORT dataa (422:422:422) (513:513:513)) - (PORT datab (390:390:390) (465:465:465)) - (PORT datac (675:675:675) (735:735:735)) - (PORT datad (679:679:679) (752:752:752)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~1) - (DELAY - (ABSOLUTE - (PORT dataa (269:269:269) (367:367:367)) - (PORT datab (598:598:598) (665:665:665)) - (PORT datac (245:245:245) (334:334:334)) - (PORT datad (371:371:371) (425:425:425)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~4) - (DELAY - (ABSOLUTE - (PORT dataa (587:587:587) (599:599:599)) - (PORT datab (914:914:914) (923:923:923)) - (PORT datac (565:565:565) (580:580:580)) - (PORT datad (307:307:307) (323:323:323)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1424:1424:1424) (1466:1466:1466)) - (PORT datab (1535:1535:1535) (1597:1597:1597)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1559:1559:1559)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1118:1118:1118) (1158:1158:1158)) - (PORT datab (675:675:675) (710:710:710)) - (PORT datac (900:900:900) (960:960:960)) - (PORT datad (1167:1167:1167) (1206:1206:1206)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~2) - (DELAY - (ABSOLUTE - (PORT dataa (979:979:979) (1040:1040:1040)) - (PORT datab (271:271:271) (356:356:356)) - (PORT datac (1122:1122:1122) (1190:1190:1190)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~3) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (746:746:746) (769:769:769)) - (PORT datac (1390:1390:1390) (1425:1425:1425)) - (PORT datad (245:245:245) (316:316:316)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_control_\|DFFE_latch_pf_tmp) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1535:1535:1535)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1283:1283:1283) (1287:1287:1287)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_1) (DELAY (ABSOLUTE - (PORT dataa (221:221:221) (264:264:264)) - (PORT datab (214:214:214) (259:259:259)) - (PORT datac (179:179:179) (216:216:216)) - (PORT datad (181:181:181) (210:210:210)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (398:398:398) (425:425:425)) + (PORT datab (206:206:206) (246:246:246)) + (PORT datac (1090:1090:1090) (1110:1110:1110)) + (PORT datad (188:188:188) (218:218:218)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -26619,12 +18872,12 @@ (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|result\~0) (DELAY (ABSOLUTE - (PORT dataa (545:545:545) (570:570:570)) - (PORT datab (213:213:213) (257:257:257)) - (PORT datac (177:177:177) (214:214:214)) - (PORT datad (173:173:173) (197:197:197)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT dataa (399:399:399) (426:426:426)) + (PORT datab (345:345:345) (377:377:377)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (189:189:189) (221:221:221)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -26632,43 +18885,30 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_parity_out\~0) + (INSTANCE z80_\|alu_\|db_high\[1\]\~14) (DELAY (ABSOLUTE - (PORT dataa (813:813:813) (826:826:826)) - (PORT datac (328:328:328) (358:358:358)) - (PORT datad (196:196:196) (221:221:221)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (280:280:280) (355:355:355)) + (PORT datab (281:281:281) (340:340:340)) + (PORT datac (1112:1112:1112) (1120:1120:1120)) + (PORT datad (247:247:247) (291:291:291)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_parity_out) + (INSTANCE z80_\|alu_\|db_high\[1\]\~15) (DELAY (ABSOLUTE - (PORT dataa (350:350:350) (381:381:381)) - (PORT datab (662:662:662) (697:697:697)) - (PORT datad (172:172:172) (198:198:198)) + (PORT dataa (246:246:246) (301:301:301)) + (PORT datab (876:876:876) (938:938:938)) + (PORT datac (603:603:603) (612:612:612)) + (PORT datad (566:566:566) (620:620:620)) (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1118:1118:1118) (1161:1161:1161)) - (PORT datab (1154:1154:1154) (1224:1224:1224)) - (PORT datac (1392:1392:1392) (1427:1427:1427)) - (PORT datad (1169:1169:1169) (1209:1209:1209)) - (IOPATH dataa combout (341:341:341) (319:319:319)) (IOPATH datab combout (342:342:342) (318:318:318)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -26677,1089 +18917,88 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~8) + (INSTANCE z80_\|alu_\|db_high\[1\]\~16) (DELAY (ABSOLUTE - (PORT dataa (933:933:933) (998:998:998)) - (PORT datab (748:748:748) (772:772:772)) - (PORT datac (646:646:646) (675:675:675)) - (PORT datad (174:174:174) (200:200:200)) + (PORT dataa (563:563:563) (593:593:593)) + (PORT datac (954:954:954) (1041:1041:1041)) + (PORT datad (347:347:347) (371:371:371)) (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~9) + (INSTANCE z80_\|alu_\|db_high\[1\]\~17) (DELAY (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (198:198:198) (238:238:238)) - (PORT datac (1374:1374:1374) (1429:1429:1429)) + (PORT dataa (838:838:838) (862:862:862)) + (PORT datab (639:639:639) (654:654:654)) + (PORT datad (1108:1108:1108) (1130:1130:1130)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (640:640:640) (666:666:666)) + (PORT datab (640:640:640) (663:663:663)) + (PORT datac (696:696:696) (745:745:745)) + (PORT datad (595:595:595) (635:635:635)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[1\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (870:870:870) (932:932:932)) + (PORT datab (678:678:678) (709:709:709)) + (PORT datac (342:342:342) (367:367:367)) (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~10) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (254:254:254)) - (PORT datab (341:341:341) (367:367:367)) - (PORT datac (1214:1214:1214) (1255:1255:1255)) - (PORT datad (677:677:677) (698:698:698)) (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf) - (DELAY - (ABSOLUTE - (PORT clk (1514:1514:1514) (1528:1528:1528)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|sel\[1\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (922:922:922) (946:946:946)) - (PORT datab (2012:2012:2012) (2066:2066:2066)) - (PORT datac (919:919:919) (1015:1015:1015)) - (PORT datad (863:863:863) (877:877:877)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11\~2) - (DELAY - (ABSOLUTE - (PORT dataa (409:409:409) (447:447:447)) - (PORT datab (1195:1195:1195) (1198:1198:1198)) - (PORT datac (601:601:601) (607:607:607)) - (PORT datad (334:334:334) (359:359:359)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_12) - (DELAY - (ABSOLUTE - (PORT dataa (825:825:825) (855:855:855)) - (PORT datad (337:337:337) (354:354:354)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11\~0) - (DELAY - (ABSOLUTE - (PORT dataa (224:224:224) (278:278:278)) - (PORT datab (223:223:223) (271:271:271)) - (PORT datac (616:616:616) (645:645:645)) - (PORT datad (216:216:216) (258:258:258)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11\~1) - (DELAY - (ABSOLUTE - (PORT dataa (592:592:592) (621:621:621)) - (PORT datab (686:686:686) (701:701:701)) - (PORT datac (562:562:562) (583:583:583)) - (PORT datad (312:312:312) (322:322:322)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_37\~0) - (DELAY - (ABSOLUTE - (PORT dataa (622:622:622) (661:661:661)) - (PORT datab (654:654:654) (674:674:674)) - (PORT datac (240:240:240) (317:317:317)) - (PORT datad (385:385:385) (407:407:407)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_37\~1) - (DELAY - (ABSOLUTE - (PORT dataa (646:646:646) (692:692:692)) - (PORT datab (199:199:199) (239:239:239)) - (PORT datac (610:610:610) (651:651:651)) - (PORT datad (176:176:176) (202:202:202)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_39) - (DELAY - (ABSOLUTE - (PORT clk (1517:1517:1517) (1530:1530:1530)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1244:1244:1244) (1250:1250:1250)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|b2v_inst_cond_mux\|out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1638:1638:1638) (1703:1703:1703)) - (PORT datab (222:222:222) (261:261:261)) - (PORT datac (181:181:181) (218:218:218)) - (PORT datad (884:884:884) (949:949:949)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|b2v_inst_cond_mux\|out\~1) - (DELAY - (ABSOLUTE - (PORT dataa (669:669:669) (747:747:747)) - (PORT datab (659:659:659) (717:717:717)) - (PORT datac (181:181:181) (218:218:218)) - (PORT datad (172:172:172) (198:198:198)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|flags_cond_true\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1816:1816:1816) (1911:1911:1911)) - (PORT datab (2014:2014:2014) (2068:2068:2068)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_control_\|flags_cond_true) - (DELAY - (ABSOLUTE - (PORT clk (1514:1514:1514) (1527:1527:1527)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~13) - (DELAY - (ABSOLUTE - (PORT dataa (629:629:629) (663:663:663)) - (PORT datab (1772:1772:1772) (1863:1863:1863)) - (PORT datac (1815:1815:1815) (1893:1893:1893)) - (PORT datad (552:552:552) (570:570:570)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~14) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (256:256:256)) - (PORT datab (230:230:230) (280:280:280)) - (PORT datac (563:563:563) (592:592:592)) - (PORT datad (181:181:181) (211:211:211)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~17) - (DELAY - (ABSOLUTE - (PORT dataa (888:888:888) (905:905:905)) - (PORT datab (221:221:221) (261:261:261)) - (PORT datac (623:623:623) (650:650:650)) - (PORT datad (1193:1193:1193) (1247:1247:1247)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_82) - (DELAY - (ABSOLUTE - (PORT dataa (629:629:629) (658:658:658)) - (PORT datab (949:949:949) (994:994:994)) - (PORT datad (671:671:671) (699:699:699)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (640:640:640) (694:694:694)) - (PORT datab (517:517:517) (537:537:537)) - (PORT datac (742:742:742) (744:744:744)) - (PORT datad (1107:1107:1107) (1107:1107:1107)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (545:545:545) (573:573:573)) - (PORT datab (199:199:199) (239:239:239)) - (PORT datac (580:580:580) (606:606:606)) - (PORT datad (621:621:621) (643:643:643)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (198:198:198) (242:242:242)) - (PORT datab (259:259:259) (310:310:310)) - (PORT datac (607:607:607) (617:617:617)) - (PORT datad (236:236:236) (276:276:276)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1545:1545:1545)) - (PORT asdata (1881:1881:1881) (1885:1885:1885)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1544:1544:1544)) - (PORT asdata (1836:1836:1836) (1841:1841:1841)) - (PORT ena (1231:1231:1231) (1217:1217:1217)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (434:434:434) (465:465:465)) - (PORT datab (378:378:378) (448:448:448)) - (PORT datad (608:608:608) (629:629:629)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1544:1544:1544)) - (PORT asdata (1836:1836:1836) (1841:1841:1841)) - (PORT ena (1499:1499:1499) (1507:1507:1507)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1520:1520:1520) (1534:1534:1534)) - (PORT asdata (2122:2122:2122) (2138:2138:2138)) - (PORT ena (1207:1207:1207) (1190:1190:1190)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1535:1535:1535)) - (PORT asdata (2124:2124:2124) (2160:2160:2160)) - (PORT ena (841:841:841) (846:846:846)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (462:462:462) (498:498:498)) - (PORT datab (667:667:667) (706:706:706)) - (PORT datad (632:632:632) (685:685:685)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~27) - (DELAY - (ABSOLUTE - (PORT datab (1411:1411:1411) (1423:1423:1423)) - (PORT datad (585:585:585) (594:594:594)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1545:1545:1545)) - (PORT asdata (1880:1880:1880) (1884:1884:1884)) - (PORT ena (1220:1220:1220) (1214:1214:1214)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (657:657:657) (709:709:709)) - (PORT datab (945:945:945) (994:994:994)) - (PORT datac (888:888:888) (910:910:910)) - (PORT datad (609:609:609) (625:625:625)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1545:1545:1545)) - (PORT asdata (1630:1630:1630) (1644:1644:1644)) - (PORT ena (821:821:821) (834:834:834)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (823:823:823) (864:864:864)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1266:1266:1266) (1269:1269:1269)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (412:412:412) (473:473:473)) - (PORT datab (583:583:583) (621:621:621)) - (PORT datad (584:584:584) (628:628:628)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (246:246:246)) - (PORT datab (200:200:200) (239:239:239)) - (PORT datac (170:170:170) (202:202:202)) - (PORT datad (551:551:551) (556:556:556)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1532:1532:1532) (1549:1549:1549)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1413:1413:1413) (1385:1385:1385)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1531:1531:1531)) - (PORT asdata (1857:1857:1857) (1863:1863:1863)) - (PORT ena (1734:1734:1734) (1719:1719:1719)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (242:242:242) (328:328:328)) - (PORT datab (962:962:962) (1016:1016:1016)) - (PORT datad (847:847:847) (873:873:873)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (712:712:712) (740:740:740)) - (PORT ena (811:811:811) (804:804:804)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (712:712:712) (740:740:740)) - (PORT ena (841:841:841) (846:846:846)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (243:243:243) (329:329:329)) - (PORT datab (263:263:263) (316:316:316)) - (PORT datad (234:234:234) (273:273:273)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (684:684:684) (726:726:726)) - (PORT datab (635:635:635) (674:674:674)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (1349:1349:1349) (1373:1373:1373)) - (PORT datab (623:623:623) (653:653:653)) - (PORT datac (643:643:643) (694:694:694)) - (PORT datad (308:308:308) (323:323:323)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_ds\[1\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1481:1481:1481) (1531:1531:1531)) - (PORT datab (1644:1644:1644) (1715:1715:1715)) - (PORT datac (1522:1522:1522) (1538:1538:1538)) - (PORT datad (1165:1165:1165) (1205:1205:1205)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[1\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (978:978:978) (996:996:996)) - (PORT datab (878:878:878) (913:913:913)) - (PORT datac (923:923:923) (978:978:978)) - (PORT datad (879:879:879) (914:914:914)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[1\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (696:696:696) (721:721:721)) - (PORT datab (1150:1150:1150) (1186:1186:1186)) - (PORT datac (887:887:887) (975:975:975)) - (PORT datad (1184:1184:1184) (1219:1219:1219)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[1\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (203:203:203) (248:248:248)) - (PORT datab (943:943:943) (996:996:996)) - (PORT datac (648:648:648) (674:674:674)) - (PORT datad (172:172:172) (198:198:198)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[1\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1303:1303:1303) (1352:1352:1352)) - (PORT datab (933:933:933) (975:975:975)) - (PORT datac (1446:1446:1446) (1491:1491:1491)) - (PORT datad (926:926:926) (983:983:983)) - (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[1\]\~13) + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[1\]\~4) (DELAY (ABSOLUTE - (PORT dataa (204:204:204) (248:248:248)) - (PORT datab (986:986:986) (1033:1033:1033)) - (PORT datac (900:900:900) (933:933:933)) - (PORT datad (222:222:222) (267:267:267)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1695:1695:1695) (1783:1783:1783)) - (PORT datac (897:897:897) (925:925:925)) - (PORT datad (364:364:364) (385:385:385)) + (PORT dataa (948:948:948) (982:982:982)) + (PORT datab (886:886:886) (904:904:904)) + (PORT datac (647:647:647) (670:670:670)) + (PORT datad (613:613:613) (642:642:642)) (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~22) - (DELAY - (ABSOLUTE - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (926:926:926) (952:952:952)) - (PORT datad (237:237:237) (274:274:274)) (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1179:1179:1179) (1212:1212:1212)) - (PORT datab (286:286:286) (347:347:347)) - (PORT datac (254:254:254) (311:311:311)) - (PORT datad (254:254:254) (300:300:300)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (432:432:432) (525:525:525)) - (PORT datab (1170:1170:1170) (1217:1217:1217)) - (PORT datac (1156:1156:1156) (1212:1212:1212)) - (PORT datad (661:661:661) (724:724:724)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|result_lo\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1535:1535:1535)) - (PORT asdata (672:672:672) (698:698:698)) - (PORT ena (1283:1283:1283) (1287:1287:1287)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (632:632:632) (638:638:638)) - (PORT datab (368:368:368) (389:389:389)) - (PORT datad (1139:1139:1139) (1146:1146:1146)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (587:587:587) (597:597:597)) - (PORT datab (220:220:220) (258:258:258)) - (PORT datac (1124:1124:1124) (1146:1146:1146)) - (PORT datad (335:335:335) (355:355:355)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[0\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1292:1292:1292) (1345:1345:1345)) - (PORT datab (915:915:915) (937:937:937)) - (PORT datac (1123:1123:1123) (1144:1144:1144)) - (PORT datad (945:945:945) (995:995:995)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[0\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (964:964:964) (1020:1020:1020)) - (PORT datac (806:806:806) (813:813:813)) - (PORT datad (227:227:227) (273:273:273)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (970:970:970) (999:999:999)) - (PORT datac (1663:1663:1663) (1739:1739:1739)) - (PORT datad (1415:1415:1415) (1442:1442:1442)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (243:243:243)) - (PORT datac (902:902:902) (931:931:931)) - (PORT datad (239:239:239) (281:281:281)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1179:1179:1179) (1211:1211:1211)) - (PORT datab (286:286:286) (349:349:349)) - (PORT datac (255:255:255) (313:313:313)) - (PORT datad (248:248:248) (293:293:293)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (671:671:671) (728:728:728)) - (PORT datab (1171:1171:1171) (1217:1217:1217)) - (PORT datac (615:615:615) (673:673:673)) - (PORT datad (661:661:661) (723:723:723)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|result_lo\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1535:1535:1535)) - (PORT asdata (1127:1127:1127) (1132:1132:1132)) - (PORT ena (1283:1283:1283) (1287:1287:1287)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (549:549:549) (578:578:578)) - (PORT datab (331:331:331) (362:362:362)) - (PORT datad (1138:1138:1138) (1145:1145:1145)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (683:683:683) (703:703:703)) - (PORT datab (359:359:359) (389:389:389)) - (PORT datac (797:797:797) (800:800:800)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[1\]\~5) (DELAY (ABSOLUTE - (PORT dataa (588:588:588) (619:619:619)) - (PORT datab (968:968:968) (1015:1015:1015)) - (PORT datac (371:371:371) (403:403:403)) - (PORT datad (863:863:863) (917:917:917)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[1\]\~6) - (DELAY - (ABSOLUTE - (PORT datac (173:173:173) (207:207:207)) - (PORT datad (681:681:681) (721:721:721)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT datac (895:895:895) (917:917:917)) + (PORT datad (173:173:173) (197:197:197)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -27769,9 +19008,9 @@ (INSTANCE z80_\|alu_\|op1_low\[1\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1531:1531:1531)) + (PORT clk (1547:1547:1547) (1549:1549:1549)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (790:790:790) (782:782:782)) + (PORT ena (794:794:794) (792:792:792)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -27785,10 +19024,5562 @@ (INSTANCE z80_\|alu_control_\|out\[6\]\~0) (DELAY (ABSOLUTE - (PORT datab (264:264:264) (346:346:346)) + (PORT dataa (264:264:264) (350:350:350)) (PORT datac (235:235:235) (311:311:311)) - (PORT datad (235:235:235) (303:303:303)) + (PORT datad (257:257:257) (326:326:326)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|out\[6\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (903:903:903) (994:994:994)) + (PORT datab (883:883:883) (922:922:922)) + (PORT datac (898:898:898) (995:995:995)) + (PORT datad (849:849:849) (924:924:924)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|out\[6\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (212:212:212) (257:257:257)) + (PORT datac (674:674:674) (774:774:774)) + (PORT datad (860:860:860) (934:934:934)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_12) + (DELAY + (ABSOLUTE + (PORT datac (675:675:675) (703:703:703)) + (PORT datad (855:855:855) (888:888:888)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_37\~0) + (DELAY + (ABSOLUTE + (PORT dataa (274:274:274) (365:365:365)) + (PORT datab (2171:2171:2171) (2260:2260:2260)) + (PORT datac (924:924:924) (952:952:952)) + (PORT datad (2241:2241:2241) (2306:2306:2306)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11\~2) + (DELAY + (ABSOLUTE + (PORT dataa (715:715:715) (761:761:761)) + (PORT datab (690:690:690) (730:730:730)) + (PORT datac (620:620:620) (647:647:647)) + (PORT datad (614:614:614) (644:644:644)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11\~0) + (DELAY + (ABSOLUTE + (PORT dataa (697:697:697) (718:718:718)) + (PORT datab (371:371:371) (402:402:402)) + (PORT datac (193:193:193) (227:227:227)) + (PORT datad (180:180:180) (209:209:209)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11\~1) + (DELAY + (ABSOLUTE + (PORT dataa (367:367:367) (405:405:405)) + (PORT datab (898:898:898) (920:920:920)) + (PORT datac (363:363:363) (385:385:385)) + (PORT datad (341:341:341) (360:360:360)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_37\~1) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (242:242:242)) + (PORT datab (198:198:198) (238:238:238)) + (PORT datac (833:833:833) (847:847:847)) + (PORT datad (337:337:337) (358:358:358)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~7) + (DELAY + (ABSOLUTE + (PORT datac (1455:1455:1455) (1533:1533:1533)) + (PORT datad (575:575:575) (600:600:600)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1186:1186:1186) (1211:1211:1211)) + (PORT datab (887:887:887) (918:918:918)) + (PORT datac (319:319:319) (353:353:353)) + (PORT datad (609:609:609) (640:640:640)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_39) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1218:1218:1218) (1200:1200:1200)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~51) + (DELAY + (ABSOLUTE + (PORT dataa (1441:1441:1441) (1461:1461:1461)) + (PORT datab (868:868:868) (922:922:922)) + (PORT datac (857:857:857) (873:873:873)) + (PORT datad (884:884:884) (896:896:896)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_oe\~2) + (DELAY + (ABSOLUTE + (PORT dataa (584:584:584) (599:599:599)) + (PORT datab (866:866:866) (904:904:904)) + (PORT datac (982:982:982) (1018:1018:1018)) + (PORT datad (1154:1154:1154) (1183:1183:1183)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~7) + (DELAY + (ABSOLUTE + (PORT dataa (878:878:878) (924:924:924)) + (PORT datab (1320:1320:1320) (1374:1374:1374)) + (PORT datac (822:822:822) (818:818:818)) + (PORT datad (553:553:553) (557:557:557)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[6\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (898:898:898) (922:922:922)) + (PORT datab (708:708:708) (776:776:776)) + (PORT datac (834:834:834) (845:845:845)) + (PORT datad (544:544:544) (559:559:559)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[6\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (1136:1136:1136) (1152:1152:1152)) + (PORT datab (214:214:214) (259:259:259)) + (PORT datac (187:187:187) (227:227:227)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~8) + (DELAY + (ABSOLUTE + (PORT dataa (822:822:822) (850:850:850)) + (PORT datab (1119:1119:1119) (1158:1158:1158)) + (PORT datac (650:650:650) (674:674:674)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[6\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (864:864:864) (895:895:895)) + (PORT datab (883:883:883) (901:901:901)) + (PORT datac (635:635:635) (694:694:694)) + (PORT datad (1043:1043:1043) (1071:1071:1071)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[6\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (266:266:266)) + (PORT datab (412:412:412) (439:439:439)) + (PORT datac (364:364:364) (397:397:397)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[6\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (197:197:197) (237:237:237)) + (PORT datac (335:335:335) (357:357:357)) + (PORT datad (364:364:364) (391:391:391)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[6\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (650:650:650) (679:679:679)) + (PORT datab (935:935:935) (951:951:951)) + (PORT datac (592:592:592) (608:608:608)) + (PORT datad (681:681:681) (707:707:707)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[6\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (747:747:747) (776:776:776)) + (PORT datab (257:257:257) (318:318:318)) + (PORT datac (856:856:856) (874:874:874)) + (PORT datad (176:176:176) (201:201:201)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1533:1533:1533)) + (PORT asdata (1436:1436:1436) (1451:1451:1451)) + (PORT ena (1201:1201:1201) (1198:1198:1198)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~80) + (DELAY + (ABSOLUTE + (PORT dataa (1197:1197:1197) (1218:1218:1218)) + (PORT datab (1143:1143:1143) (1170:1170:1170)) + (PORT datad (394:394:394) (433:433:433)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT asdata (1261:1261:1261) (1297:1297:1297)) + (PORT ena (1229:1229:1229) (1240:1240:1240)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT asdata (1266:1266:1266) (1301:1301:1301)) + (PORT ena (1168:1168:1168) (1147:1147:1147)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~79) + (DELAY + (ABSOLUTE + (PORT dataa (694:694:694) (730:730:730)) + (PORT datab (269:269:269) (324:324:324)) + (PORT datad (218:218:218) (287:287:287)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (1436:1436:1436) (1448:1448:1448)) + (PORT ena (1225:1225:1225) (1236:1236:1236)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1089:1089:1089) (1102:1102:1102)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1440:1440:1440) (1419:1419:1419)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~78) + (DELAY + (ABSOLUTE + (PORT dataa (701:701:701) (760:760:760)) + (PORT datab (657:657:657) (680:680:680)) + (PORT datad (216:216:216) (284:284:284)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~82) + (DELAY + (ABSOLUTE + (PORT dataa (846:846:846) (871:871:871)) + (PORT datab (552:552:552) (566:566:566)) + (PORT datac (573:573:573) (568:568:568)) + (PORT datad (340:340:340) (366:366:366)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1530:1530:1530)) + (PORT asdata (1184:1184:1184) (1204:1204:1204)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|db\[6\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1425:1425:1425) (1489:1489:1489)) + (PORT datab (1191:1191:1191) (1211:1211:1211)) + (PORT datad (825:825:825) (851:851:851)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (889:889:889) (925:925:925)) + (PORT ena (1277:1277:1277) (1271:1271:1271)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (936:936:936) (959:959:959)) + (PORT ena (981:981:981) (980:980:980)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (583:583:583) (602:602:602)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1190:1190:1190) (1164:1164:1164)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~76) + (DELAY + (ABSOLUTE + (PORT dataa (697:697:697) (733:733:733)) + (PORT datab (696:696:696) (722:722:722)) + (PORT datad (216:216:216) (285:285:285)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~77) + (DELAY + (ABSOLUTE + (PORT dataa (637:637:637) (673:673:673)) + (PORT datab (612:612:612) (640:640:640)) + (PORT datad (337:337:337) (356:356:356)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~83) + (DELAY + (ABSOLUTE + (PORT dataa (244:244:244) (331:331:331)) + (PORT datab (207:207:207) (249:249:249)) + (PORT datac (564:564:564) (575:575:575)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~84) + (DELAY + (ABSOLUTE + (PORT dataa (864:864:864) (911:911:911)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (1098:1098:1098) (1107:1107:1107)) + (PORT datad (605:605:605) (620:620:620)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1532:1532:1532)) + (PORT asdata (676:676:676) (691:691:691)) + (PORT ena (1224:1224:1224) (1225:1225:1225)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (683:683:683) (713:713:713)) + (PORT datab (894:894:894) (926:926:926)) + (PORT datad (630:630:630) (653:653:653)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1279:1279:1279) (1290:1290:1290)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (384:384:384)) + (PORT datab (243:243:243) (324:324:324)) + (PORT datad (1051:1051:1051) (1065:1065:1065)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[13\]) + (DELAY + (ABSOLUTE + (PORT dataa (628:628:628) (669:669:669)) + (PORT datad (1092:1092:1092) (1096:1096:1096)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1561:1561:1561) (1543:1543:1543)) + (PORT ena (1886:1886:1886) (1891:1891:1891)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|d0_out) + (DELAY + (ABSOLUTE + (PORT dataa (425:425:425) (505:505:505)) + (PORT datab (214:214:214) (259:259:259)) + (PORT datac (655:655:655) (700:700:700)) + (PORT datad (409:409:409) (474:474:474)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT asdata (1215:1215:1215) (1236:1236:1236)) + (PORT ena (1229:1229:1229) (1240:1240:1240)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT asdata (1215:1215:1215) (1239:1239:1239)) + (PORT ena (1168:1168:1168) (1147:1147:1147)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~61) + (DELAY + (ABSOLUTE + (PORT dataa (694:694:694) (729:729:729)) + (PORT datab (271:271:271) (330:330:330)) + (PORT datad (215:215:215) (283:283:283)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1533:1533:1533)) + (PORT asdata (1878:1878:1878) (1923:1923:1923)) + (PORT ena (1201:1201:1201) (1198:1198:1198)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~62) + (DELAY + (ABSOLUTE + (PORT dataa (1203:1203:1203) (1222:1222:1222)) + (PORT datab (894:894:894) (936:936:936)) + (PORT datad (397:397:397) (440:440:440)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (1161:1161:1161) (1187:1187:1187)) + (PORT ena (1225:1225:1225) (1236:1236:1236)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (619:619:619) (636:636:636)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1440:1440:1440) (1419:1419:1419)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~60) + (DELAY + (ABSOLUTE + (PORT dataa (701:701:701) (759:759:759)) + (PORT datab (660:660:660) (686:686:686)) + (PORT datad (214:214:214) (282:282:282)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1533:1533:1533)) + (PORT asdata (1712:1712:1712) (1726:1726:1726)) + (PORT ena (1227:1227:1227) (1249:1249:1249)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1533:1533:1533)) + (PORT asdata (1711:1711:1711) (1726:1726:1726)) + (PORT ena (1503:1503:1503) (1497:1497:1497)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~63) + (DELAY + (ABSOLUTE + (PORT dataa (701:701:701) (776:776:776)) + (PORT datab (241:241:241) (322:322:322)) + (PORT datad (698:698:698) (745:745:745)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~64) + (DELAY + (ABSOLUTE + (PORT dataa (578:578:578) (599:599:599)) + (PORT datab (597:597:597) (621:621:621)) + (PORT datac (611:611:611) (632:632:632)) + (PORT datad (311:311:311) (330:330:330)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (790:790:790) (782:782:782)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1530:1530:1530)) + (PORT asdata (1340:1340:1340) (1368:1368:1368)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|db\[4\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1429:1429:1429) (1490:1490:1490)) + (PORT datab (1191:1191:1191) (1208:1208:1208)) + (PORT datad (822:822:822) (848:848:848)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (926:926:926) (946:946:946)) + (PORT ena (1277:1277:1277) (1271:1271:1271)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (675:675:675) (703:703:703)) + (PORT ena (1190:1190:1190) (1164:1164:1164)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (678:678:678) (706:706:706)) + (PORT ena (981:981:981) (980:980:980)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~58) + (DELAY + (ABSOLUTE + (PORT dataa (698:698:698) (730:730:730)) + (PORT datab (242:242:242) (324:324:324)) + (PORT datad (622:622:622) (632:632:632)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~59) + (DELAY + (ABSOLUTE + (PORT dataa (637:637:637) (673:673:673)) + (PORT datab (638:638:638) (657:657:657)) + (PORT datad (339:339:339) (359:359:359)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~65) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (207:207:207) (248:248:248)) + (PORT datac (216:216:216) (292:292:292)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~66) + (DELAY + (ABSOLUTE + (PORT dataa (864:864:864) (908:908:908)) + (PORT datab (925:925:925) (935:935:935)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (608:608:608) (619:619:619)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1532:1532:1532)) + (PORT asdata (671:671:671) (693:693:693)) + (PORT ena (1224:1224:1224) (1225:1225:1225)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (682:682:682) (711:711:711)) + (PORT datab (1220:1220:1220) (1264:1264:1264)) + (PORT datad (630:630:630) (653:653:653)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1279:1279:1279) (1290:1290:1290)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (198:198:198) (241:241:241)) + (PORT datab (244:244:244) (327:327:327)) + (PORT datad (1054:1054:1054) (1068:1068:1068)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (654:654:654) (675:675:675)) + (PORT datab (199:199:199) (239:239:239)) + (PORT datac (582:582:582) (610:610:610)) + (PORT datad (1332:1332:1332) (1347:1347:1347)) + (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[12\]) + (DELAY + (ABSOLUTE + (PORT dataa (673:673:673) (695:695:695)) + (PORT datac (594:594:594) (625:625:625)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1561:1561:1561) (1543:1543:1543)) + (PORT ena (1886:1886:1886) (1891:1891:1891)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|SYNTHESIZED_WIRE_0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (425:425:425) (505:505:505)) + (PORT datab (214:214:214) (260:260:260)) + (PORT datac (655:655:655) (700:700:700)) + (PORT datad (408:408:408) (474:474:474)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[14\]) + (DELAY + (ABSOLUTE + (PORT dataa (433:433:433) (506:506:506)) + (PORT datab (860:860:860) (882:882:882)) + (PORT datac (236:236:236) (325:325:325)) + (PORT datad (344:344:344) (368:368:368)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (1357:1357:1357) (1390:1390:1390)) + (PORT datab (611:611:611) (644:644:644)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (627:627:627) (643:643:643)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[14\]) + (DELAY + (ABSOLUTE + (PORT datac (596:596:596) (626:626:626)) + (PORT datad (622:622:622) (640:640:640)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1561:1561:1561) (1543:1543:1543)) + (PORT ena (1886:1886:1886) (1891:1891:1891)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[15\]) + (DELAY + (ABSOLUTE + (PORT dataa (630:630:630) (666:666:666)) + (PORT datad (611:611:611) (624:624:624)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1561:1561:1561) (1543:1543:1543)) + (PORT ena (1886:1886:1886) (1891:1891:1891)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[15\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (244:244:244) (302:302:302)) + (PORT datab (224:224:224) (273:273:273)) + (PORT datac (586:586:586) (607:607:607)) + (PORT datad (683:683:683) (737:737:737)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[15\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (272:272:272) (369:369:369)) + (PORT datab (859:859:859) (881:881:881)) + (PORT datac (375:375:375) (442:442:442)) + (PORT datad (597:597:597) (606:606:606)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1279:1279:1279) (1290:1290:1290)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1532:1532:1532)) + (PORT asdata (893:893:893) (906:906:906)) + (PORT ena (1224:1224:1224) (1225:1225:1225)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (684:684:684) (713:713:713)) + (PORT datab (667:667:667) (692:692:692)) + (PORT datad (1402:1402:1402) (1416:1416:1416)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (244:244:244) (332:332:332)) + (PORT datab (1076:1076:1076) (1105:1105:1105)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (1356:1356:1356) (1388:1388:1388)) + (PORT datab (362:362:362) (392:392:392)) + (PORT datac (579:579:579) (609:609:609)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (1446:1446:1446) (1450:1450:1450)) + (PORT ena (790:790:790) (782:782:782)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[7\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1537:1537:1537) (1586:1586:1586)) + (PORT datab (2171:2171:2171) (2210:2210:2210)) + (PORT datad (1367:1367:1367) (1389:1389:1389)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1533:1533:1533)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1503:1503:1503) (1497:1497:1497)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1533:1533:1533)) + (PORT asdata (535:535:535) (566:566:566)) + (PORT ena (1227:1227:1227) (1249:1249:1249)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~72) + (DELAY + (ABSOLUTE + (PORT dataa (701:701:701) (775:775:775)) + (PORT datab (645:645:645) (696:696:696)) + (PORT datad (698:698:698) (745:745:745)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1533:1533:1533)) + (PORT asdata (1651:1651:1651) (1665:1665:1665)) + (PORT ena (1201:1201:1201) (1198:1198:1198)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~71) + (DELAY + (ABSOLUTE + (PORT dataa (1203:1203:1203) (1222:1222:1222)) + (PORT datab (938:938:938) (968:968:968)) + (PORT datad (394:394:394) (437:437:437)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT asdata (1465:1465:1465) (1482:1482:1482)) + (PORT ena (1229:1229:1229) (1240:1240:1240)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT asdata (1465:1465:1465) (1481:1481:1481)) + (PORT ena (1168:1168:1168) (1147:1147:1147)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~70) + (DELAY + (ABSOLUTE + (PORT dataa (691:691:691) (730:730:730)) + (PORT datab (270:270:270) (329:329:329)) + (PORT datad (217:217:217) (285:285:285)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (1240:1240:1240) (1271:1271:1271)) + (PORT ena (1225:1225:1225) (1236:1236:1236)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (1237:1237:1237) (1268:1268:1268)) + (PORT ena (1440:1440:1440) (1419:1419:1419)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~69) + (DELAY + (ABSOLUTE + (PORT dataa (700:700:700) (762:762:762)) + (PORT datab (657:657:657) (681:681:681)) + (PORT datad (217:217:217) (285:285:285)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~73) + (DELAY + (ABSOLUTE + (PORT dataa (839:839:839) (851:851:851)) + (PORT datab (618:618:618) (634:634:634)) + (PORT datac (534:534:534) (537:537:537)) + (PORT datad (343:343:343) (365:365:365)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1530:1530:1530)) + (PORT asdata (917:917:917) (929:929:929)) + (PORT ena (1240:1240:1240) (1223:1223:1223)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1530:1530:1530)) + (PORT asdata (919:919:919) (932:932:932)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~68) + (DELAY + (ABSOLUTE + (PORT dataa (724:724:724) (754:754:754)) + (PORT datab (241:241:241) (323:323:323)) + (PORT datad (234:234:234) (272:272:272)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (1431:1431:1431) (1431:1431:1431)) + (PORT ena (981:981:981) (980:980:980)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (878:878:878) (903:903:903)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1190:1190:1190) (1164:1164:1164)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~67) + (DELAY + (ABSOLUTE + (PORT dataa (691:691:691) (724:724:724)) + (PORT datab (698:698:698) (718:718:718)) + (PORT datad (214:214:214) (283:283:283)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~74) + (DELAY + (ABSOLUTE + (PORT dataa (555:555:555) (577:577:577)) + (PORT datab (793:793:793) (854:854:854)) + (PORT datac (765:765:765) (799:799:799)) + (PORT datad (361:361:361) (384:384:384)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~75) + (DELAY + (ABSOLUTE + (PORT dataa (846:846:846) (873:873:873)) + (PORT datab (921:921:921) (954:954:954)) + (PORT datac (1144:1144:1144) (1167:1167:1167)) + (PORT datad (557:557:557) (573:573:573)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[7\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (653:653:653) (677:677:677)) + (PORT datab (911:911:911) (921:921:921)) + (PORT datac (591:591:591) (605:605:605)) + (PORT datad (636:636:636) (650:650:650)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[7\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (747:747:747) (781:781:781)) + (PORT datab (259:259:259) (317:317:317)) + (PORT datac (896:896:896) (906:906:906)) + (PORT datad (178:178:178) (204:204:204)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (910:910:910) (932:932:932)) + (PORT datac (545:545:545) (573:573:573)) + (PORT datad (702:702:702) (798:798:798)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~1) + (DELAY + (ABSOLUTE + (PORT datab (200:200:200) (239:239:239)) + (PORT datac (186:186:186) (224:224:224)) + (PORT datad (1129:1129:1129) (1137:1137:1137)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~2) + (DELAY + (ABSOLUTE + (PORT dataa (867:867:867) (903:903:903)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (1106:1106:1106) (1114:1114:1114)) + (PORT datad (1128:1128:1128) (1135:1135:1135)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1136:1136:1136) (1150:1150:1150)) + (PORT datab (671:671:671) (726:726:726)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~8) + (DELAY + (ABSOLUTE + (PORT dataa (911:911:911) (984:984:984)) + (PORT datac (596:596:596) (629:629:629)) + (PORT datad (393:393:393) (441:441:441)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1166:1166:1166) (1214:1214:1214)) + (PORT datab (987:987:987) (1055:1055:1055)) + (PORT datac (315:315:315) (342:342:342)) + (PORT datad (907:907:907) (962:962:962)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~10) + (DELAY + (ABSOLUTE + (PORT dataa (2112:2112:2112) (2291:2291:2291)) + (PORT datab (1583:1583:1583) (1640:1640:1640)) + (PORT datac (1803:1803:1803) (1891:1891:1891)) + (PORT datad (956:956:956) (1070:1070:1070)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~11) + (DELAY + (ABSOLUTE + (PORT dataa (983:983:983) (1011:1011:1011)) + (PORT datab (622:622:622) (650:650:650)) + (PORT datac (2485:2485:2485) (2499:2499:2499)) + (PORT datad (580:580:580) (583:583:583)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1408:1408:1408) (1423:1423:1423)) + (PORT datab (379:379:379) (410:410:410)) + (PORT datac (1069:1069:1069) (1083:1083:1083)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~9) + (DELAY + (ABSOLUTE + (PORT dataa (617:617:617) (692:692:692)) + (PORT datab (1200:1200:1200) (1228:1228:1228)) + (PORT datac (610:610:610) (632:632:632)) + (PORT datad (672:672:672) (769:769:769)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~46) + (DELAY + (ABSOLUTE + (PORT dataa (1496:1496:1496) (1591:1591:1591)) + (PORT datab (1529:1529:1529) (1592:1592:1592)) + (PORT datad (1898:1898:1898) (2020:2020:2020)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~9) + (DELAY + (ABSOLUTE + (PORT dataa (631:631:631) (671:671:671)) + (PORT datab (220:220:220) (259:259:259)) + (PORT datac (186:186:186) (227:227:227)) + (PORT datad (642:642:642) (660:660:660)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~10) + (DELAY + (ABSOLUTE + (PORT dataa (924:924:924) (992:992:992)) + (PORT datab (862:862:862) (887:887:887)) + (PORT datac (909:909:909) (984:984:984)) + (PORT datad (211:211:211) (245:245:245)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1509:1509:1509) (1602:1602:1602)) + (PORT datab (207:207:207) (249:249:249)) + (PORT datac (803:803:803) (840:840:840)) + (PORT datad (607:607:607) (653:653:653)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1143:1143:1143) (1189:1189:1189)) + (PORT datab (660:660:660) (710:710:710)) + (PORT datac (579:579:579) (598:598:598)) + (PORT datad (625:625:625) (673:673:673)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~15) + (DELAY + (ABSOLUTE + (PORT dataa (2002:2002:2002) (2194:2194:2194)) + (PORT datab (1218:1218:1218) (1314:1314:1314)) + (PORT datac (965:965:965) (989:989:989)) + (PORT datad (1275:1275:1275) (1361:1361:1361)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1024:1024:1024) (1073:1073:1073)) + (PORT datab (236:236:236) (280:280:280)) + (PORT datac (314:314:314) (333:333:333)) + (PORT datad (1437:1437:1437) (1476:1476:1476)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~3) + (DELAY + (ABSOLUTE + (PORT dataa (627:627:627) (673:673:673)) + (PORT datab (1184:1184:1184) (1240:1240:1240)) + (PORT datac (817:817:817) (851:851:851)) + (PORT datad (1106:1106:1106) (1136:1136:1136)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|flags_cf) + (DELAY + (ABSOLUTE + (PORT dataa (652:652:652) (707:707:707)) + (PORT datab (854:854:854) (925:925:925)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (375:375:375) (406:406:406)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sw2_\|db_up\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT datac (874:874:874) (895:895:895)) + (PORT datad (546:546:546) (563:563:563)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[0\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (865:865:865) (891:891:891)) + (PORT datab (600:600:600) (623:623:623)) + (PORT datac (408:408:408) (452:452:452)) + (PORT datad (604:604:604) (618:618:618)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1231:1231:1231) (1237:1237:1237)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (675:675:675) (697:697:697)) + (PORT ena (1200:1200:1200) (1181:1181:1181)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (893:893:893) (937:937:937)) + (PORT datab (1242:1242:1242) (1275:1275:1275)) + (PORT datad (402:402:402) (438:438:438)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (245:245:245) (332:332:332)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (613:613:613) (631:631:631)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~70) + (DELAY + (ABSOLUTE + (PORT dataa (1002:1002:1002) (1055:1055:1055)) + (PORT datab (1627:1627:1627) (1636:1636:1636)) + (PORT datac (1549:1549:1549) (1655:1655:1655)) + (PORT datad (2773:2773:2773) (2972:2972:2972)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~28) + (DELAY + (ABSOLUTE + (PORT dataa (1714:1714:1714) (1799:1799:1799)) + (PORT datab (1830:1830:1830) (1927:1927:1927)) + (PORT datac (1212:1212:1212) (1288:1288:1288)) + (PORT datad (990:990:990) (1065:1065:1065)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1702:1702:1702) (1727:1727:1727)) + (PORT datab (904:904:904) (954:954:954)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (680:680:680) (736:736:736)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~27) + (DELAY + (ABSOLUTE + (PORT dataa (1711:1711:1711) (1798:1798:1798)) + (PORT datab (690:690:690) (747:747:747)) + (PORT datac (1216:1216:1216) (1291:1291:1291)) + (PORT datad (987:987:987) (1065:1065:1065)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~10) + (DELAY + (ABSOLUTE + (PORT dataa (982:982:982) (1056:1056:1056)) + (PORT datab (227:227:227) (268:268:268)) + (PORT datac (852:852:852) (906:906:906)) + (PORT datad (203:203:203) (233:233:233)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla38pla13M3T2_4) + (DELAY + (ABSOLUTE + (PORT dataa (979:979:979) (1051:1051:1051)) + (PORT datab (1662:1662:1662) (1751:1751:1751)) + (PORT datac (1100:1100:1100) (1120:1120:1120)) + (PORT datad (900:900:900) (918:918:918)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~11) + (DELAY + (ABSOLUTE + (PORT dataa (2808:2808:2808) (3011:3011:3011)) + (PORT datab (2312:2312:2312) (2341:2341:2341)) + (PORT datac (1243:1243:1243) (1275:1275:1275)) + (PORT datad (1270:1270:1270) (1307:1307:1307)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla40M3T2_4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1202:1202:1202) (1238:1238:1238)) + (PORT datab (1183:1183:1183) (1320:1320:1320)) + (PORT datac (960:960:960) (1033:1033:1033)) + (PORT datad (639:639:639) (680:680:680)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~9) + (DELAY + (ABSOLUTE + (PORT dataa (869:869:869) (883:883:883)) + (PORT datab (227:227:227) (269:269:269)) + (PORT datac (1087:1087:1087) (1134:1134:1134)) + (PORT datad (943:943:943) (963:963:963)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~12) + (DELAY + (ABSOLUTE + (PORT dataa (209:209:209) (255:255:255)) + (PORT datab (206:206:206) (248:248:248)) + (PORT datac (654:654:654) (676:676:676)) + (PORT datad (622:622:622) (650:650:650)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1177:1177:1177) (1211:1211:1211)) + (PORT datab (934:934:934) (953:953:953)) + (PORT datac (847:847:847) (878:878:878)) + (PORT datad (1296:1296:1296) (1363:1363:1363)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1301:1301:1301) (1408:1408:1408)) + (PORT datab (1510:1510:1510) (1602:1602:1602)) + (PORT datac (886:886:886) (946:946:946)) + (PORT datad (2838:2838:2838) (2937:2937:2937)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~13) + (DELAY + (ABSOLUTE + (PORT dataa (2022:2022:2022) (2107:2107:2107)) + (PORT datab (2444:2444:2444) (2572:2572:2572)) + (PORT datac (660:660:660) (715:715:715)) + (PORT datad (983:983:983) (1064:1064:1064)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~14) + (DELAY + (ABSOLUTE + (PORT dataa (661:661:661) (683:683:683)) + (PORT datab (652:652:652) (679:679:679)) + (PORT datac (187:187:187) (227:227:227)) + (PORT datad (347:347:347) (370:370:370)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_use_ixiypla53M2T2_4) + (DELAY + (ABSOLUTE + (PORT dataa (2023:2023:2023) (2107:2107:2107)) + (PORT datab (1189:1189:1189) (1228:1228:1228)) + (PORT datac (851:851:851) (873:873:873)) + (PORT datad (984:984:984) (1063:1063:1063)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~16) + (DELAY + (ABSOLUTE + (PORT dataa (568:568:568) (592:592:592)) + (PORT datab (392:392:392) (422:422:422)) + (PORT datac (179:179:179) (215:215:215)) + (PORT datad (337:337:337) (357:357:357)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~22) + (DELAY + (ABSOLUTE + (PORT dataa (655:655:655) (682:682:682)) + (PORT datab (1346:1346:1346) (1448:1448:1448)) + (PORT datac (1534:1534:1534) (1623:1623:1623)) + (PORT datad (1652:1652:1652) (1728:1728:1728)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~23) + (DELAY + (ABSOLUTE + (PORT dataa (401:401:401) (429:429:429)) + (PORT datab (1152:1152:1152) (1216:1216:1216)) + (PORT datac (1367:1367:1367) (1418:1418:1418)) + (PORT datad (2160:2160:2160) (2356:2356:2356)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~24) + (DELAY + (ABSOLUTE + (PORT dataa (1522:1522:1522) (1603:1603:1603)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (169:169:169) (202:202:202)) + (PORT datad (2160:2160:2160) (2356:2356:2356)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~41) + (DELAY + (ABSOLUTE + (PORT dataa (976:976:976) (1029:1029:1029)) + (PORT datab (955:955:955) (1004:1004:1004)) + (PORT datac (1229:1229:1229) (1299:1299:1299)) + (PORT datad (658:658:658) (706:706:706)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~21) + (DELAY + (ABSOLUTE + (PORT dataa (842:842:842) (869:869:869)) + (PORT datab (1383:1383:1383) (1429:1429:1429)) + (PORT datac (1609:1609:1609) (1641:1641:1641)) + (PORT datad (830:830:830) (858:858:858)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~25) + (DELAY + (ABSOLUTE + (PORT dataa (670:670:670) (695:695:695)) + (PORT datab (908:908:908) (921:921:921)) + (PORT datac (876:876:876) (893:893:893)) + (PORT datad (180:180:180) (208:208:208)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~69) + (DELAY + (ABSOLUTE + (PORT dataa (1000:1000:1000) (1053:1053:1053)) + (PORT datab (2808:2808:2808) (3013:3013:3013)) + (PORT datac (179:179:179) (216:216:216)) + (PORT datad (1382:1382:1382) (1437:1437:1437)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~17) + (DELAY + (ABSOLUTE + (PORT dataa (504:504:504) (583:583:583)) + (PORT datac (265:265:265) (354:354:354)) + (PORT datad (700:700:700) (785:785:785)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~71) + (DELAY + (ABSOLUTE + (PORT dataa (1655:1655:1655) (1694:1694:1694)) + (PORT datab (198:198:198) (238:238:238)) + (PORT datac (178:178:178) (213:213:213)) + (PORT datad (1175:1175:1175) (1237:1237:1237)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~44) + (DELAY + (ABSOLUTE + (PORT dataa (220:220:220) (262:262:262)) + (PORT datab (1337:1337:1337) (1422:1422:1422)) + (PORT datac (636:636:636) (654:654:654)) + (PORT datad (1177:1177:1177) (1244:1244:1244)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~42) + (DELAY + (ABSOLUTE + (PORT dataa (670:670:670) (699:699:699)) + (PORT datac (876:876:876) (893:893:893)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~43) + (DELAY + (ABSOLUTE + (PORT dataa (1218:1218:1218) (1286:1286:1286)) + (PORT datab (199:199:199) (239:239:239)) + (PORT datac (1061:1061:1061) (1086:1086:1086)) + (PORT datad (974:974:974) (1012:1012:1012)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~57) + (DELAY + (ABSOLUTE + (PORT dataa (1383:1383:1383) (1420:1420:1420)) + (PORT datab (1160:1160:1160) (1211:1211:1211)) + (PORT datac (620:620:620) (647:647:647)) + (PORT datad (620:620:620) (637:637:637)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~54) + (DELAY + (ABSOLUTE + (PORT dataa (1708:1708:1708) (1796:1796:1796)) + (PORT datab (2444:2444:2444) (2575:2575:2575)) + (PORT datac (1803:1803:1803) (1899:1899:1899)) + (PORT datad (680:680:680) (733:733:733)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~58) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (392:392:392) (420:420:420)) + (PORT datac (179:179:179) (216:216:216)) + (PORT datad (322:322:322) (343:343:343)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~18) + (DELAY + (ABSOLUTE + (PORT dataa (981:981:981) (1054:1054:1054)) + (PORT datab (228:228:228) (269:269:269)) + (PORT datac (179:179:179) (217:217:217)) + (PORT datad (622:622:622) (647:647:647)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~19) + (DELAY + (ABSOLUTE + (PORT dataa (870:870:870) (881:881:881)) + (PORT datab (379:379:379) (406:406:406)) + (PORT datac (623:623:623) (650:650:650)) + (PORT datad (588:588:588) (611:611:611)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~45) + (DELAY + (ABSOLUTE + (PORT dataa (1218:1218:1218) (1267:1267:1267)) + (PORT datab (1012:1012:1012) (1054:1054:1054)) + (PORT datac (572:572:572) (575:575:575)) + (PORT datad (1453:1453:1453) (1517:1517:1517)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~34) + (DELAY + (ABSOLUTE + (PORT dataa (2809:2809:2809) (3013:3013:3013)) + (PORT datab (1267:1267:1267) (1332:1332:1332)) + (PORT datac (977:977:977) (1038:1038:1038)) + (PORT datad (1269:1269:1269) (1304:1304:1304)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~35) + (DELAY + (ABSOLUTE + (PORT dataa (1296:1296:1296) (1347:1347:1347)) + (PORT datab (206:206:206) (247:247:247)) + (PORT datac (682:682:682) (723:723:723)) + (PORT datad (171:171:171) (196:196:196)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~46) + (DELAY + (ABSOLUTE + (PORT dataa (1286:1286:1286) (1347:1347:1347)) + (PORT datab (1241:1241:1241) (1309:1309:1309)) + (PORT datac (1253:1253:1253) (1318:1318:1318)) + (PORT datad (1457:1457:1457) (1522:1522:1522)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~47) + (DELAY + (ABSOLUTE + (PORT dataa (622:622:622) (686:686:686)) + (PORT datab (1241:1241:1241) (1308:1308:1308)) + (PORT datac (1517:1517:1517) (1594:1594:1594)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~48) + (DELAY + (ABSOLUTE + (PORT dataa (947:947:947) (998:998:998)) + (PORT datab (2479:2479:2479) (2662:2662:2662)) + (PORT datac (606:606:606) (642:642:642)) + (PORT datad (919:919:919) (994:994:994)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~50) + (DELAY + (ABSOLUTE + (PORT dataa (659:659:659) (678:678:678)) + (PORT datab (213:213:213) (256:256:256)) + (PORT datac (911:911:911) (964:964:964)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~51) + (DELAY + (ABSOLUTE + (PORT dataa (215:215:215) (267:267:267)) + (PORT datab (1161:1161:1161) (1213:1213:1213)) + (PORT datac (188:188:188) (228:228:228)) + (PORT datad (924:924:924) (975:975:975)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~85) + (DELAY + (ABSOLUTE + (PORT dataa (1302:1302:1302) (1408:1408:1408)) + (PORT datab (1249:1249:1249) (1314:1314:1314)) + (PORT datac (945:945:945) (1046:1046:1046)) + (PORT datad (642:642:642) (700:700:700)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~63) + (DELAY + (ABSOLUTE + (PORT dataa (510:510:510) (589:589:589)) + (PORT datab (937:937:937) (989:989:989)) + (PORT datac (848:848:848) (887:887:887)) + (PORT datad (695:695:695) (784:784:784)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~64) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (265:265:265)) + (PORT datab (875:875:875) (912:912:912)) + (PORT datac (854:854:854) (907:907:907)) + (PORT datad (622:622:622) (646:646:646)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~65) + (DELAY + (ABSOLUTE + (PORT dataa (228:228:228) (273:273:273)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (571:571:571) (580:580:580)) + (PORT datad (195:195:195) (221:221:221)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~59) + (DELAY + (ABSOLUTE + (PORT dataa (943:943:943) (964:964:964)) + (PORT datab (1662:1662:1662) (1751:1751:1751)) + (PORT datac (856:856:856) (906:906:906)) + (PORT datad (886:886:886) (935:935:935)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~60) + (DELAY + (ABSOLUTE + (PORT dataa (198:198:198) (241:241:241)) + (PORT datab (661:661:661) (686:686:686)) + (PORT datac (177:177:177) (213:213:213)) + (PORT datad (835:835:835) (883:883:883)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~61) + (DELAY + (ABSOLUTE + (PORT dataa (1302:1302:1302) (1407:1407:1407)) + (PORT datab (1250:1250:1250) (1315:1315:1315)) + (PORT datac (946:946:946) (1048:1048:1048)) + (PORT datad (1134:1134:1134) (1164:1164:1164)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~62) + (DELAY + (ABSOLUTE + (PORT dataa (661:661:661) (684:684:684)) + (PORT datab (645:645:645) (669:669:669)) + (PORT datac (608:608:608) (628:628:628)) + (PORT datad (172:172:172) (198:198:198)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~66) + (DELAY + (ABSOLUTE + (PORT dataa (198:198:198) (240:240:240)) + (PORT datab (341:341:341) (371:371:371)) + (PORT datac (185:185:185) (229:229:229)) + (PORT datad (172:172:172) (196:196:196)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~53) + (DELAY + (ABSOLUTE + (PORT dataa (1321:1321:1321) (1411:1411:1411)) + (PORT datab (206:206:206) (248:248:248)) + (PORT datac (1179:1179:1179) (1210:1210:1210)) + (PORT datad (1349:1349:1349) (1366:1366:1366)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~52) + (DELAY + (ABSOLUTE + (PORT dataa (1260:1260:1260) (1311:1311:1311)) + (PORT datab (1397:1397:1397) (1421:1421:1421)) + (PORT datac (1108:1108:1108) (1135:1135:1135)) + (PORT datad (872:872:872) (913:913:913)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~84) + (DELAY + (ABSOLUTE + (PORT dataa (1794:1794:1794) (1865:1865:1865)) + (PORT datab (196:196:196) (235:235:235)) + (PORT datac (200:200:200) (238:238:238)) + (PORT datad (1232:1232:1232) (1283:1283:1283)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla91pla20M2T2_3) + (DELAY + (ABSOLUTE + (PORT dataa (1304:1304:1304) (1411:1411:1411)) + (PORT datab (1506:1506:1506) (1599:1599:1599)) + (PORT datac (913:913:913) (932:932:932)) + (PORT datad (1600:1600:1600) (1628:1628:1628)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~55) + (DELAY + (ABSOLUTE + (PORT dataa (910:910:910) (945:945:945)) + (PORT datab (218:218:218) (257:257:257)) + (PORT datac (788:788:788) (808:808:808)) + (PORT datad (322:322:322) (344:344:344)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~56) + (DELAY + (ABSOLUTE + (PORT dataa (611:611:611) (633:633:633)) + (PORT datab (647:647:647) (671:671:671)) + (PORT datac (1133:1133:1133) (1178:1178:1178)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~67) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (241:241:241)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (172:172:172) (204:204:204)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~20) + (DELAY + (ABSOLUTE + (PORT dataa (216:216:216) (267:267:267)) + (PORT datab (392:392:392) (424:424:424)) + (PORT datac (188:188:188) (229:229:229)) + (PORT datad (527:527:527) (547:547:547)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~83) + (DELAY + (ABSOLUTE + (PORT dataa (1271:1271:1271) (1341:1341:1341)) + (PORT datab (1531:1531:1531) (1623:1623:1623)) + (PORT datac (609:609:609) (627:627:627)) + (PORT datad (1261:1261:1261) (1368:1368:1368)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~68) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (197:197:197) (237:237:237)) + (PORT datac (608:608:608) (627:627:627)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|Q\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (197:197:197) (223:223:223)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1526:1526:1526) (1546:1546:1546)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1573:1573:1573) (1552:1552:1552)) + (PORT ena (1991:1991:1991) (1983:1983:1983)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~72) + (DELAY + (ABSOLUTE + (PORT dataa (667:667:667) (698:698:698)) + (PORT datab (640:640:640) (664:664:664)) + (PORT datac (877:877:877) (896:896:896)) + (PORT datad (181:181:181) (210:210:210)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~73) + (DELAY + (ABSOLUTE + (PORT dataa (1572:1572:1572) (1699:1699:1699)) + (PORT datab (957:957:957) (1009:1009:1009)) + (PORT datac (208:208:208) (247:247:247)) + (PORT datad (1802:1802:1802) (1903:1903:1903)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~74) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (253:253:253)) + (PORT datab (1207:1207:1207) (1284:1284:1284)) + (PORT datac (1334:1334:1334) (1437:1437:1437)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~75) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (242:242:242)) + (PORT datab (207:207:207) (247:247:247)) + (PORT datac (615:615:615) (669:669:669)) + (PORT datad (1180:1180:1180) (1239:1239:1239)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~76) + (DELAY + (ABSOLUTE + (PORT dataa (215:215:215) (267:267:267)) + (PORT datab (205:205:205) (245:245:245)) + (PORT datac (526:526:526) (541:541:541)) + (PORT datad (358:358:358) (378:378:378)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~80) + (DELAY + (ABSOLUTE + (PORT datab (198:198:198) (238:238:238)) + (PORT datac (1152:1152:1152) (1187:1187:1187)) + (PORT datad (182:182:182) (212:212:212)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~81) + (DELAY + (ABSOLUTE + (PORT dataa (1218:1218:1218) (1287:1287:1287)) + (PORT datab (206:206:206) (248:248:248)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (609:609:609) (651:651:651)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|d0_out) + (DELAY + (ABSOLUTE + (PORT dataa (1501:1501:1501) (1627:1627:1627)) + (PORT datab (1554:1554:1554) (1576:1576:1576)) + (PORT datac (249:249:249) (334:334:334)) + (PORT datad (1466:1466:1466) (1550:1550:1550)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1647:1647:1647) (1677:1677:1677)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (804:804:804) (814:814:814)) + (PORT datad (351:351:351) (383:383:383)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1549:1549:1549)) + (PORT asdata (990:990:990) (1006:1006:1006)) + (PORT ena (1240:1240:1240) (1231:1231:1231)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1470:1470:1470) (1475:1475:1475)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1549:1549:1549)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1207:1207:1207) (1180:1180:1180)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (702:702:702) (744:744:744)) + (PORT datab (710:710:710) (732:732:732)) + (PORT datad (217:217:217) (285:285:285)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT asdata (1255:1255:1255) (1279:1279:1279)) + (PORT ena (1200:1200:1200) (1188:1188:1188)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (865:865:865) (934:934:934)) + (PORT datab (1146:1146:1146) (1157:1157:1157)) + (PORT datad (557:557:557) (569:569:569)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1169:1169:1169) (1184:1184:1184)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1550:1550:1550)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (811:811:811) (804:804:804)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1550:1550:1550)) + (PORT asdata (1786:1786:1786) (1780:1780:1780)) + (PORT ena (842:842:842) (856:856:856)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (387:387:387) (466:466:466)) + (PORT datab (237:237:237) (282:282:282)) + (PORT datad (208:208:208) (237:237:237)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT asdata (941:941:941) (960:960:960)) + (PORT ena (811:811:811) (804:804:804)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|db\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (927:927:927) (974:974:974)) + (PORT datab (643:643:643) (698:698:698)) + (PORT datad (643:643:643) (686:686:686)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT asdata (941:941:941) (957:957:957)) + (PORT ena (981:981:981) (980:980:980)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (603:603:603) (631:631:631)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datad (229:229:229) (266:266:266)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (645:645:645) (674:674:674)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1220:1220:1220) (1212:1212:1212)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1535:1535:1535)) + (PORT asdata (1552:1552:1552) (1574:1574:1574)) + (PORT ena (1243:1243:1243) (1246:1246:1246)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (622:622:622) (694:694:694)) + (PORT datab (690:690:690) (760:760:760)) + (PORT datad (619:619:619) (672:672:672)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1535:1535:1535)) + (PORT asdata (1552:1552:1552) (1574:1574:1574)) + (PORT ena (1274:1274:1274) (1265:1265:1265)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (195:195:195) (221:221:221)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1438:1438:1438) (1476:1476:1476)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT asdata (898:898:898) (922:922:922)) + (PORT ena (790:790:790) (782:782:782)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (386:386:386) (467:467:467)) + (PORT datab (631:631:631) (697:697:697)) + (PORT datad (231:231:231) (271:271:271)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (954:954:954) (995:995:995)) + (PORT datad (565:565:565) (578:578:578)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (650:650:650) (671:671:671)) + (PORT datab (636:636:636) (653:653:653)) + (PORT datac (869:869:869) (872:872:872)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (1133:1133:1133) (1172:1172:1172)) + (PORT datab (663:663:663) (694:694:694)) + (PORT datac (616:616:616) (644:644:644)) + (PORT datad (624:624:624) (637:637:637)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[0\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (348:348:348) (376:376:376)) + (PORT datab (202:202:202) (241:241:241)) + (PORT datac (899:899:899) (921:921:921)) + (PORT datad (201:201:201) (229:229:229)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[0\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (869:869:869) (904:904:904)) + (PORT datab (898:898:898) (903:903:903)) + (PORT datac (172:172:172) (206:206:206)) + (PORT datad (368:368:368) (394:394:394)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[8\]) + (DELAY + (ABSOLUTE + (PORT datac (856:856:856) (889:889:889)) + (PORT datad (941:941:941) (982:982:982)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1560:1560:1560) (1542:1542:1542)) + (PORT ena (1949:1949:1949) (1917:1917:1917)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|d0_out) + (DELAY + (ABSOLUTE + (PORT datac (638:638:638) (656:656:656)) + (PORT datad (584:584:584) (644:644:644)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1535:1535:1535)) + (PORT asdata (924:924:924) (951:951:951)) + (PORT ena (975:975:975) (963:963:963)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1535:1535:1535)) + (PORT asdata (925:925:925) (952:952:952)) + (PORT ena (1008:1008:1008) (1010:1010:1010)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~84) + (DELAY + (ABSOLUTE + (PORT dataa (374:374:374) (417:417:417)) + (PORT datab (242:242:242) (325:325:325)) + (PORT datad (368:368:368) (394:394:394)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1140:1140:1140) (1149:1149:1149)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1550:1550:1550)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (811:811:811) (804:804:804)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1550:1550:1550)) + (PORT asdata (1217:1217:1217) (1236:1236:1236)) + (PORT ena (842:842:842) (856:856:856)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~83) + (DELAY + (ABSOLUTE + (PORT dataa (388:388:388) (458:458:458)) + (PORT datab (235:235:235) (279:279:279)) + (PORT datad (209:209:209) (240:240:240)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT asdata (537:537:537) (568:568:568)) + (PORT ena (1438:1438:1438) (1476:1476:1476)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~88) + (DELAY + (ABSOLUTE + (PORT dataa (697:697:697) (764:764:764)) + (PORT datab (867:867:867) (894:894:894)) + (PORT datad (1351:1351:1351) (1343:1343:1343)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT asdata (1191:1191:1191) (1218:1218:1218)) + (PORT ena (1220:1220:1220) (1212:1212:1212)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT asdata (1191:1191:1191) (1218:1218:1218)) + (PORT ena (1200:1200:1200) (1188:1188:1188)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~86) + (DELAY + (ABSOLUTE + (PORT dataa (858:858:858) (928:928:928)) + (PORT datab (241:241:241) (322:322:322)) + (PORT datad (662:662:662) (722:722:722)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT asdata (947:947:947) (965:965:965)) + (PORT ena (790:790:790) (782:782:782)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT asdata (947:947:947) (966:966:966)) + (PORT ena (1288:1288:1288) (1306:1306:1306)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~87) + (DELAY + (ABSOLUTE + (PORT dataa (667:667:667) (749:749:749)) + (PORT datab (240:240:240) (322:322:322)) + (PORT datad (231:231:231) (272:272:272)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT asdata (970:970:970) (1006:1006:1006)) + (PORT ena (841:841:841) (847:847:847)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|db\[7\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1175:1175:1175) (1215:1215:1215)) + (PORT datab (888:888:888) (933:933:933)) + (PORT datad (943:943:943) (978:978:978)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~89) + (DELAY + (ABSOLUTE + (PORT dataa (640:640:640) (675:675:675)) + (PORT datab (896:896:896) (922:922:922)) + (PORT datac (575:575:575) (602:602:602)) + (PORT datad (172:172:172) (198:198:198)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1549:1549:1549)) + (PORT asdata (1242:1242:1242) (1258:1258:1258)) + (PORT ena (1240:1240:1240) (1231:1231:1231)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1549:1549:1549)) + (PORT asdata (1239:1239:1239) (1254:1254:1254)) + (PORT ena (1207:1207:1207) (1180:1180:1180)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~85) + (DELAY + (ABSOLUTE + (PORT dataa (695:695:695) (736:736:736)) + (PORT datab (706:706:706) (728:728:728)) + (PORT datad (218:218:218) (287:287:287)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~90) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (661:661:661) (676:676:676)) + (PORT datac (765:765:765) (775:775:775)) + (PORT datad (783:783:783) (784:784:784)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~91) + (DELAY + (ABSOLUTE + (PORT dataa (586:586:586) (603:603:603)) + (PORT datab (663:663:663) (696:696:696)) + (PORT datac (1100:1100:1100) (1134:1134:1134)) + (PORT datad (609:609:609) (628:628:628)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT asdata (692:692:692) (718:718:718)) + (PORT ena (811:811:811) (804:804:804)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (655:655:655) (704:704:704)) + (PORT datab (219:219:219) (259:259:259)) + (PORT datad (1066:1066:1066) (1071:1071:1071)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (985:985:985) (993:993:993)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (338:338:338) (368:368:368)) + (PORT datac (335:335:335) (361:361:361)) + (PORT datad (217:217:217) (286:286:286)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (820:820:820) (838:838:838)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (549:549:549) (570:570:570)) + (PORT datad (1831:1831:1831) (1825:1825:1825)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[7\]) + (DELAY + (ABSOLUTE + (PORT dataa (614:614:614) (638:638:638)) + (PORT datac (858:858:858) (881:881:881)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|Q\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (195:195:195) (220:220:220)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1562:1562:1562) (1544:1544:1544)) + (PORT ena (1676:1676:1676) (1678:1678:1678)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|d1_out) + (DELAY + (ABSOLUTE + (PORT dataa (910:910:910) (931:931:931)) + (PORT datab (965:965:965) (1050:1050:1050)) + (PORT datac (655:655:655) (698:698:698)) + (PORT datad (584:584:584) (648:648:648)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1279:1279:1279) (1290:1290:1290)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1532:1532:1532)) + (PORT asdata (1459:1459:1459) (1478:1478:1478)) + (PORT ena (1224:1224:1224) (1225:1225:1225)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (684:684:684) (708:708:708)) + (PORT datab (665:665:665) (687:687:687)) + (PORT datad (600:600:600) (617:617:617)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT datab (1080:1080:1080) (1107:1107:1107)) + (PORT datac (217:217:217) (294:294:294)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (664:664:664) (679:679:679)) + (PORT datab (199:199:199) (239:239:239)) + (PORT datac (582:582:582) (610:610:610)) + (PORT datad (1332:1332:1332) (1347:1347:1347)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1530:1530:1530)) + (PORT asdata (1174:1174:1174) (1179:1179:1179)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1530:1530:1530)) + (PORT asdata (1174:1174:1174) (1181:1181:1181)) + (PORT ena (1240:1240:1240) (1223:1223:1223)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (726:726:726) (751:751:751)) + (PORT datab (260:260:260) (312:312:312)) + (PORT datad (217:217:217) (286:286:286)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT asdata (1871:1871:1871) (1898:1898:1898)) + (PORT ena (1168:1168:1168) (1147:1147:1147)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1533:1533:1533)) + (PORT asdata (1876:1876:1876) (1902:1902:1902)) + (PORT ena (1230:1230:1230) (1209:1209:1209)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (694:694:694) (728:728:728)) + (PORT datab (270:270:270) (330:330:330)) + (PORT datad (386:386:386) (445:445:445)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1533:1533:1533)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1227:1227:1227) (1249:1249:1249)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1533:1533:1533)) + (PORT asdata (890:890:890) (899:899:899)) + (PORT ena (1503:1503:1503) (1497:1497:1497)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (705:705:705) (782:782:782)) + (PORT datab (588:588:588) (663:663:663)) + (PORT datad (695:695:695) (748:748:748)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (1676:1676:1676) (1719:1719:1719)) + (PORT ena (1440:1440:1440) (1419:1419:1419)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (1676:1676:1676) (1719:1719:1719)) + (PORT ena (1225:1225:1225) (1236:1236:1236)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (702:702:702) (763:763:763)) + (PORT datab (657:657:657) (676:676:676)) + (PORT datad (215:215:215) (283:283:283)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1533:1533:1533)) + (PORT asdata (1878:1878:1878) (1906:1906:1906)) + (PORT ena (1201:1201:1201) (1198:1198:1198)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (1202:1202:1202) (1220:1220:1220)) + (PORT datab (905:905:905) (941:941:941)) + (PORT datad (400:400:400) (443:443:443)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (604:604:604) (631:631:631)) + (PORT datab (380:380:380) (406:406:406)) + (PORT datac (872:872:872) (889:889:889)) + (PORT datad (617:617:617) (626:626:626)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (1841:1841:1841) (1879:1879:1879)) + (PORT ena (790:790:790) (782:782:782)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[0\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1530:1530:1530) (1588:1588:1588)) + (PORT datab (2174:2174:2174) (2219:2219:2219)) + (PORT datad (1365:1365:1365) (1389:1389:1389)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (1822:1822:1822) (1851:1851:1851)) + (PORT ena (981:981:981) (980:980:980)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1248:1248:1248) (1278:1278:1278)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1190:1190:1190) (1164:1164:1164)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (693:693:693) (730:730:730)) + (PORT datab (696:696:696) (723:723:723)) + (PORT datad (217:217:217) (286:286:286)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (898:898:898) (935:935:935)) + (PORT datab (200:200:200) (239:239:239)) + (PORT datac (621:621:621) (634:634:634)) + (PORT datad (596:596:596) (619:619:619)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (636:636:636) (671:671:671)) + (PORT datab (367:367:367) (389:389:389)) + (PORT datac (1143:1143:1143) (1172:1172:1172)) + (PORT datad (882:882:882) (921:921:921)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[0\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (649:649:649) (677:677:677)) + (PORT datab (680:680:680) (699:699:699)) + (PORT datac (843:843:843) (848:848:848)) + (PORT datad (706:706:706) (734:734:734)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[0\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (858:858:858) (890:890:890)) + (PORT datab (258:258:258) (317:317:317)) + (PORT datac (590:590:590) (603:603:603)) + (PORT datad (176:176:176) (201:201:201)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (903:903:903) (932:932:932)) + (PORT datab (849:849:849) (885:885:885)) + (PORT datad (1178:1178:1178) (1265:1265:1265)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (851:851:851) (882:882:882)) + (PORT datab (1295:1295:1295) (1332:1332:1332)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (245:245:245) (299:299:299)) + (PORT datab (575:575:575) (641:641:641)) + (PORT datac (603:603:603) (610:610:610)) + (PORT datad (891:891:891) (928:928:928)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (283:283:283) (354:354:354)) + (PORT datab (279:279:279) (337:337:337)) + (PORT datac (1112:1112:1112) (1118:1118:1118)) + (PORT datad (241:241:241) (285:285:285)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|result_lo\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (195:195:195) (222:222:222)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|result_lo\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1716:1716:1716) (1724:1724:1724)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (794:794:794) (816:816:816)) + (PORT datac (540:540:540) (554:554:554)) + (PORT datad (383:383:383) (442:442:442)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (374:374:374) (398:398:398)) + (PORT datab (700:700:700) (735:735:735)) + (PORT datac (692:692:692) (742:742:742)) + (PORT datad (591:591:591) (606:606:606)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[1\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (652:652:652) (676:676:676)) + (PORT datab (624:624:624) (641:641:641)) + (PORT datac (640:640:640) (667:667:667)) + (PORT datad (1143:1143:1143) (1178:1178:1178)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (745:745:745) (781:781:781)) + (PORT datab (257:257:257) (316:316:316)) + (PORT datac (878:878:878) (881:881:881)) + (PORT datad (177:177:177) (203:203:203)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1533:1533:1533)) + (PORT asdata (1431:1431:1431) (1460:1460:1460)) + (PORT ena (1201:1201:1201) (1198:1198:1198)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1200:1200:1200) (1221:1221:1221)) + (PORT datab (1449:1449:1449) (1507:1507:1507)) + (PORT datad (396:396:396) (441:441:441)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (887:887:887) (910:910:910)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1168:1168:1168) (1147:1147:1147)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1533:1533:1533)) + (PORT asdata (1434:1434:1434) (1461:1461:1461)) + (PORT ena (1230:1230:1230) (1209:1209:1209)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (607:607:607) (637:637:637)) + (PORT datab (374:374:374) (443:443:443)) + (PORT datad (344:344:344) (358:358:358)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (1462:1462:1462) (1488:1488:1488)) + (PORT ena (1225:1225:1225) (1236:1236:1236)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (1463:1463:1463) (1487:1487:1487)) + (PORT ena (1440:1440:1440) (1419:1419:1419)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (699:699:699) (766:766:766)) + (PORT datab (656:656:656) (686:686:686)) + (PORT datad (217:217:217) (286:286:286)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1533:1533:1533)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1503:1503:1503) (1497:1497:1497)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1533:1533:1533)) + (PORT asdata (707:707:707) (735:735:735)) + (PORT ena (1227:1227:1227) (1249:1249:1249)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (709:709:709) (784:784:784)) + (PORT datab (240:240:240) (322:322:322)) + (PORT datad (695:695:695) (743:743:743)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (200:200:200) (240:240:240)) + (PORT datac (627:627:627) (653:653:653)) + (PORT datad (556:556:556) (561:561:561)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (902:902:902) (919:919:919)) + (PORT ena (790:790:790) (782:782:782)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1534:1534:1534) (1587:1587:1587)) + (PORT datab (2170:2170:2170) (2215:2215:2215)) + (PORT datad (1366:1366:1366) (1387:1387:1387)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1530:1530:1530)) + (PORT asdata (1477:1477:1477) (1520:1520:1520)) + (PORT ena (1240:1240:1240) (1223:1223:1223)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1530:1530:1530)) + (PORT asdata (1474:1474:1474) (1517:1517:1517)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (728:728:728) (759:759:759)) + (PORT datab (243:243:243) (325:325:325)) + (PORT datad (229:229:229) (268:268:268)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (1490:1490:1490) (1530:1530:1530)) + (PORT ena (981:981:981) (980:980:980)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (610:610:610) (627:627:627)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1190:1190:1190) (1164:1164:1164)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (692:692:692) (725:725:725)) + (PORT datab (697:697:697) (718:718:718)) + (PORT datad (217:217:217) (285:285:285)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (631:631:631) (650:650:650)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (604:604:604) (625:625:625)) + (PORT datad (318:318:318) (338:338:338)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (1187:1187:1187) (1214:1214:1214)) + (PORT datab (375:375:375) (399:399:399)) + (PORT datac (833:833:833) (850:850:850)) + (PORT datad (885:885:885) (921:921:921)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1533:1533:1533)) + (PORT asdata (849:849:849) (864:864:864)) + (PORT ena (1448:1448:1448) (1437:1437:1437)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (702:702:702) (730:730:730)) + (PORT datab (711:711:711) (739:739:739)) + (PORT datad (647:647:647) (666:666:666)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (244:244:244) (331:331:331)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datad (650:650:650) (672:672:672)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1116:1116:1116) (1170:1170:1170)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (1368:1368:1368) (1378:1378:1378)) + (PORT datad (219:219:219) (258:258:258)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[9\]) + (DELAY + (ABSOLUTE + (PORT datac (894:894:894) (933:933:933)) + (PORT datad (939:939:939) (978:978:978)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|Q\[9\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (179:179:179) (207:207:207)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1560:1560:1560) (1542:1542:1542)) + (PORT ena (1949:1949:1949) (1917:1917:1917)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[10\]) + (DELAY + (ABSOLUTE + (PORT dataa (627:627:627) (667:667:667)) + (PORT datad (595:595:595) (612:612:612)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1561:1561:1561) (1543:1543:1543)) + (PORT ena (1886:1886:1886) (1891:1891:1891)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|d1_out) + (DELAY + (ABSOLUTE + (PORT dataa (217:217:217) (268:268:268)) + (PORT datab (688:688:688) (731:731:731)) + (PORT datac (934:934:934) (1023:1023:1023)) + (PORT datad (416:416:416) (486:486:486)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1533:1533:1533)) + (PORT asdata (666:666:666) (699:699:699)) + (PORT ena (1448:1448:1448) (1437:1437:1437)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (895:895:895) (920:920:920)) + (PORT datab (711:711:711) (744:744:744)) + (PORT datad (649:649:649) (671:671:671)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1533:1533:1533)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1256:1256:1256) (1263:1263:1263)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (241:241:241)) + (PORT datab (688:688:688) (709:709:709)) + (PORT datad (218:218:218) (285:285:285)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (636:636:636) (672:672:672)) + (PORT datab (1397:1397:1397) (1412:1412:1412)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (219:219:219) (258:258:258)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (1181:1181:1181) (1211:1211:1211)) + (PORT datab (569:569:569) (592:592:592)) + (PORT datac (620:620:620) (643:643:643)) + (PORT datad (883:883:883) (918:918:918)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[2\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (621:621:621) (633:633:633)) + (PORT datab (624:624:624) (650:650:650)) + (PORT datac (530:530:530) (543:543:543)) + (PORT datad (608:608:608) (624:624:624)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[2\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (742:742:742) (772:772:772)) + (PORT datab (576:576:576) (599:599:599)) + (PORT datac (219:219:219) (271:271:271)) + (PORT datad (640:640:640) (654:654:654)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[2\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (653:653:653) (681:681:681)) + (PORT datab (867:867:867) (913:913:913)) + (PORT datac (364:364:364) (393:393:393)) + (PORT datad (854:854:854) (860:860:860)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (332:332:332)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -27799,10 +24590,10 @@ (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~2) (DELAY (ABSOLUTE - (PORT datac (852:852:852) (861:861:861)) - (PORT datad (679:679:679) (700:700:700)) + (PORT datab (236:236:236) (279:279:279)) + (PORT datac (785:785:785) (807:807:807)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -27811,11 +24602,11 @@ (INSTANCE z80_\|alu_flags_\|flags_hf2\~0) (DELAY (ABSOLUTE - (PORT dataa (690:690:690) (732:732:732)) - (PORT datab (199:199:199) (237:237:237)) - (PORT datad (621:621:621) (632:632:632)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) + (PORT dataa (411:411:411) (437:437:437)) + (PORT datab (200:200:200) (239:239:239)) + (PORT datad (648:648:648) (705:705:705)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -27826,7 +24617,7 @@ (INSTANCE z80_\|alu_flags_\|flags_hf2) (DELAY (ABSOLUTE - (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -27840,106 +24631,105 @@ (INSTANCE z80_\|alu_control_\|db\[2\]\~23) (DELAY (ABSOLUTE - (PORT dataa (1183:1183:1183) (1231:1231:1231)) - (PORT datab (681:681:681) (697:697:697)) - (PORT datac (1123:1123:1123) (1203:1203:1203)) - (PORT datad (667:667:667) (721:721:721)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_ds\[2\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1196:1196:1196) (1252:1252:1252)) - (PORT datab (1640:1640:1640) (1708:1708:1708)) - (PORT datac (1440:1440:1440) (1482:1482:1482)) - (PORT datad (844:844:844) (890:890:890)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) + (PORT dataa (1137:1137:1137) (1150:1150:1150)) + (PORT datab (714:714:714) (805:805:805)) + (PORT datac (852:852:852) (893:893:893)) + (PORT datad (189:189:189) (220:220:220)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[2\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (666:666:666) (686:686:686)) - (PORT datab (928:928:928) (956:956:956)) - (PORT datac (630:630:630) (688:688:688)) - (PORT datad (848:848:848) (847:847:847)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[2\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (837:837:837) (856:856:856)) - (PORT datab (904:904:904) (946:946:946)) - (PORT datac (412:412:412) (479:479:479)) - (PORT datad (832:832:832) (862:862:862)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|alu_control_\|db\[2\]\~29) (DELAY (ABSOLUTE - (PORT dataa (682:682:682) (712:712:712)) - (PORT datab (943:943:943) (996:996:996)) - (PORT datac (576:576:576) (598:598:598)) - (PORT datad (316:316:316) (337:337:337)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (339:339:339) (373:373:373)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (599:599:599) (609:609:609)) + (PORT datad (215:215:215) (247:247:247)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[2\]\~14) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~39) (DELAY (ABSOLUTE - (PORT dataa (1305:1305:1305) (1357:1357:1357)) - (PORT datab (967:967:967) (1024:1024:1024)) - (PORT datac (922:922:922) (952:952:952)) - (PORT datad (1557:1557:1557) (1610:1610:1610)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) + (PORT dataa (832:832:832) (860:860:860)) + (PORT datab (609:609:609) (659:659:659)) + (PORT datac (352:352:352) (379:379:379)) + (PORT datad (597:597:597) (646:646:646)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[2\]\~15) + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[2\]) (DELAY (ABSOLUTE - (PORT dataa (620:620:620) (642:642:642)) - (PORT datab (987:987:987) (1034:1034:1034)) - (PORT datac (175:175:175) (210:210:210)) - (PORT datad (221:221:221) (266:266:266)) + (PORT clk (1529:1529:1529) (1549:1549:1549)) + (PORT asdata (1245:1245:1245) (1255:1255:1255)) + (PORT ena (1240:1240:1240) (1231:1231:1231)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1549:1549:1549)) + (PORT asdata (1242:1242:1242) (1251:1251:1251)) + (PORT ena (1207:1207:1207) (1180:1180:1180)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (702:702:702) (744:744:744)) + (PORT datab (710:710:710) (732:732:732)) + (PORT datad (217:217:217) (286:286:286)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (385:385:385) (413:413:413)) + (PORT datab (338:338:338) (368:368:368)) + (PORT datac (173:173:173) (206:206:206)) + (PORT datad (637:637:637) (652:652:652)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -27949,60 +24739,181 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~2) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~41) (DELAY (ABSOLUTE - (PORT dataa (1693:1693:1693) (1778:1778:1778)) - (PORT datab (916:916:916) (942:942:942)) - (PORT datac (904:904:904) (929:929:929)) - (IOPATH dataa combout (339:339:339) (367:367:367)) + (PORT dataa (522:522:522) (545:545:545)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datad (622:622:622) (631:631:631)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (1132:1132:1132) (1176:1176:1176)) + (PORT datab (618:618:618) (633:633:633)) + (PORT datac (634:634:634) (662:662:662)) + (PORT datad (650:650:650) (677:677:677)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (537:537:537) (567:567:567)) + (PORT ena (1200:1200:1200) (1181:1181:1181)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (893:893:893) (941:941:941)) + (PORT datab (691:691:691) (715:715:715)) + (PORT datad (404:404:404) (441:441:441)) + (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (381:381:381) (459:459:459)) + (PORT datac (171:171:171) (202:202:202)) + (PORT datad (613:613:613) (632:632:632)) + (IOPATH dataa combout (304:304:304) (307:307:307)) (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~3) + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_41) (DELAY (ABSOLUTE - (PORT dataa (1446:1446:1446) (1487:1487:1487)) - (PORT datab (1129:1129:1129) (1183:1183:1183)) - (PORT datac (170:170:170) (203:203:203)) - (PORT datad (234:234:234) (275:275:275)) + (PORT dataa (1836:1836:1836) (1914:1914:1914)) + (PORT datab (397:397:397) (461:461:461)) + (PORT datac (1281:1281:1281) (1295:1295:1295)) + (PORT datad (197:197:197) (232:232:232)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|SYNTHESIZED_WIRE_0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1502:1502:1502) (1628:1628:1628)) + (PORT datab (1490:1490:1490) (1584:1584:1584)) + (PORT datac (1527:1527:1527) (1545:1545:1545)) + (PORT datad (341:341:341) (362:362:362)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|d0_out) + (DELAY + (ABSOLUTE + (PORT dataa (955:955:955) (1038:1038:1038)) + (PORT datac (373:373:373) (399:399:399)) + (PORT datad (188:188:188) (221:221:221)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (241:241:241)) + (PORT datab (381:381:381) (418:418:418)) + (PORT datac (1615:1615:1615) (1633:1633:1633)) + (PORT datad (597:597:597) (613:613:613)) (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[2\]\~2) + (INSTANCE z80_\|address_latch_\|abusz\[2\]) (DELAY (ABSOLUTE - (PORT dataa (221:221:221) (274:274:274)) - (PORT datab (246:246:246) (301:301:301)) - (PORT datac (617:617:617) (647:647:647)) - (PORT datad (845:845:845) (875:875:875)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT datac (928:928:928) (948:948:948)) + (PORT datad (620:620:620) (633:633:633)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[2\]\~3) + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[2\]) (DELAY (ABSOLUTE - (PORT dataa (549:549:549) (580:580:580)) - (PORT datab (714:714:714) (753:753:753)) - (PORT datac (601:601:601) (608:608:608)) - (PORT datad (865:865:865) (915:915:915)) - (IOPATH dataa combout (354:354:354) (349:349:349)) + (PORT clk (1526:1526:1526) (1546:1546:1546)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1573:1573:1573) (1552:1552:1552)) + (PORT ena (1991:1991:1991) (1983:1983:1983)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_42) + (DELAY + (ABSOLUTE + (PORT dataa (1767:1767:1767) (1880:1880:1880)) + (PORT datab (1425:1425:1425) (1484:1484:1484)) + (PORT datac (211:211:211) (261:261:261)) + (PORT datad (1854:1854:1854) (1987:1987:1987)) + (IOPATH dataa combout (300:300:300) (308:308:308)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -28011,12 +24922,43 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_low\[2\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[3\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1531:1531:1531)) + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (535:535:535) (566:566:566)) + (PORT ena (1200:1200:1200) (1181:1181:1181)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (893:893:893) (937:937:937)) + (PORT datab (1125:1125:1125) (1146:1146:1146)) + (PORT datad (407:407:407) (440:440:440)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (790:790:790) (782:782:782)) + (PORT ena (1231:1231:1231) (1237:1237:1237)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -28027,13 +24969,169 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[2\]\~0) + (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~11) (DELAY (ABSOLUTE - (PORT dataa (654:654:654) (718:718:718)) - (PORT datab (1128:1128:1128) (1175:1175:1175)) - (PORT datac (587:587:587) (617:617:617)) - (PORT datad (401:401:401) (459:459:459)) + (PORT dataa (644:644:644) (683:683:683)) + (PORT datab (196:196:196) (235:235:235)) + (PORT datad (360:360:360) (421:421:421)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|d1_out) + (DELAY + (ABSOLUTE + (PORT dataa (217:217:217) (268:268:268)) + (PORT datab (654:654:654) (726:726:726)) + (PORT datac (368:368:368) (392:392:392)) + (PORT datad (181:181:181) (208:208:208)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1649:1649:1649) (1672:1672:1672)) + (PORT datab (196:196:196) (235:235:235)) + (PORT datac (607:607:607) (628:628:628)) + (PORT datad (350:350:350) (377:377:377)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[3\]) + (DELAY + (ABSOLUTE + (PORT datab (961:961:961) (983:983:983)) + (PORT datac (560:560:560) (566:566:566)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1526:1526:1526) (1546:1546:1546)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1573:1573:1573) (1552:1552:1552)) + (PORT ena (1991:1991:1991) (1983:1983:1983)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_45\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1898:1898:1898) (2033:2033:2033)) + (PORT datab (655:655:655) (722:722:722)) + (PORT datac (208:208:208) (256:256:256)) + (PORT datad (1741:1741:1741) (1836:1836:1836)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|carry_borrow_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (216:216:216) (267:267:267)) + (PORT datab (207:207:207) (248:248:248)) + (PORT datac (370:370:370) (397:397:397)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_47\~0) + (DELAY + (ABSOLUTE + (PORT dataa (972:972:972) (1024:1024:1024)) + (PORT datab (220:220:220) (269:269:269)) + (PORT datac (210:210:210) (259:259:259)) + (PORT datad (1322:1322:1322) (1328:1328:1328)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_47) + (DELAY + (ABSOLUTE + (PORT dataa (229:229:229) (276:276:276)) + (PORT datab (207:207:207) (249:249:249)) + (PORT datac (179:179:179) (217:217:217)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|carry_borrow_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (913:913:913) (932:932:932)) + (PORT datab (967:967:967) (1049:1049:1049)) + (PORT datac (659:659:659) (695:695:695)) + (PORT datad (584:584:584) (643:643:643)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|carry_borrow_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (215:215:215) (264:264:264)) + (PORT datab (689:689:689) (734:734:734)) + (PORT datac (934:934:934) (1018:1018:1018)) + (PORT datad (414:414:414) (480:480:480)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -28043,31 +25141,106 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[2\]\~1) + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[11\]) (DELAY (ABSOLUTE - (PORT dataa (261:261:261) (336:336:336)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (559:559:559) (578:578:578)) - (PORT datad (903:903:903) (954:954:954)) + (PORT datac (244:244:244) (324:324:324)) + (PORT datad (188:188:188) (219:219:219)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (242:242:242) (294:294:294)) + (PORT datab (1394:1394:1394) (1406:1406:1406)) + (PORT datac (171:171:171) (205:205:205)) + (PORT datad (614:614:614) (628:628:628)) (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_low\[2\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[3\]) (DELAY (ABSOLUTE - (PORT clk (1529:1529:1529) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) + (PORT clk (1517:1517:1517) (1530:1530:1530)) + (PORT asdata (1196:1196:1196) (1206:1206:1206)) + (PORT ena (1240:1240:1240) (1223:1223:1223)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1530:1530:1530)) + (PORT asdata (1194:1194:1194) (1204:1204:1204)) (PORT ena (819:819:819) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~41) + (DELAY + (ABSOLUTE + (PORT dataa (725:725:725) (752:752:752)) + (PORT datab (241:241:241) (323:323:323)) + (PORT datad (235:235:235) (274:274:274)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1533:1533:1533)) + (PORT asdata (692:692:692) (716:716:716)) + (PORT ena (1227:1227:1227) (1249:1249:1249)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1533:1533:1533)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1503:1503:1503) (1497:1497:1497)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) (TIMINGCHECK (HOLD d (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) @@ -28075,63 +25248,380 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~5) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~45) (DELAY (ABSOLUTE - (PORT dataa (460:460:460) (538:538:538)) - (PORT datab (638:638:638) (705:705:705)) - (PORT datac (1102:1102:1102) (1133:1133:1133)) - (PORT datad (662:662:662) (719:719:719)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) + (PORT dataa (708:708:708) (782:782:782)) + (PORT datab (630:630:630) (667:667:667)) + (PORT datad (215:215:215) (283:283:283)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1533:1533:1533)) + (PORT asdata (995:995:995) (1025:1025:1025)) + (PORT ena (1201:1201:1201) (1198:1198:1198)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~44) + (DELAY + (ABSOLUTE + (PORT dataa (1201:1201:1201) (1222:1222:1222)) + (PORT datab (926:926:926) (942:942:942)) + (PORT datad (400:400:400) (437:437:437)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT asdata (995:995:995) (1024:1024:1024)) + (PORT ena (1229:1229:1229) (1240:1240:1240)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT asdata (994:994:994) (1022:1022:1022)) + (PORT ena (1168:1168:1168) (1147:1147:1147)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~43) + (DELAY + (ABSOLUTE + (PORT dataa (691:691:691) (729:729:729)) + (PORT datab (270:270:270) (330:330:330)) + (PORT datad (357:357:357) (414:414:414)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (1244:1244:1244) (1251:1251:1251)) + (PORT ena (1440:1440:1440) (1419:1419:1419)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (1243:1243:1243) (1251:1251:1251)) + (PORT ena (1225:1225:1225) (1236:1236:1236)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (701:701:701) (757:757:757)) + (PORT datab (241:241:241) (322:322:322)) + (PORT datad (621:621:621) (642:642:642)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (627:627:627) (657:657:657)) + (PORT datab (332:332:332) (362:362:362)) + (PORT datac (536:536:536) (536:536:536)) + (PORT datad (320:320:320) (342:342:342)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (609:609:609) (622:622:622)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1190:1190:1190) (1164:1164:1164)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (954:954:954) (960:960:960)) + (PORT ena (981:981:981) (980:980:980)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (699:699:699) (734:734:734)) + (PORT datab (243:243:243) (325:325:325)) + (PORT datad (620:620:620) (634:634:634)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (1162:1162:1162) (1178:1178:1178)) + (PORT ena (790:790:790) (782:782:782)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[3\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1823:1823:1823) (1903:1903:1903)) + (PORT datab (657:657:657) (696:696:696)) + (PORT datac (1871:1871:1871) (1941:1941:1941)) + (PORT datad (876:876:876) (916:916:916)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (649:649:649) (682:682:682)) + (PORT datab (198:198:198) (235:235:235)) + (PORT datac (638:638:638) (653:653:653)) + (PORT datad (174:174:174) (198:198:198)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~48) + (DELAY + (ABSOLUTE + (PORT dataa (642:642:642) (673:673:673)) + (PORT datab (922:922:922) (955:955:955)) + (PORT datac (1143:1143:1143) (1168:1168:1168)) + (PORT datad (591:591:591) (602:602:602)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[3\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (645:645:645) (670:670:670)) + (PORT datab (627:627:627) (653:653:653)) + (PORT datac (621:621:621) (641:641:641)) + (PORT datad (699:699:699) (726:726:726)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[3\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (604:604:604) (628:628:628)) + (PORT datab (258:258:258) (316:316:316)) + (PORT datac (591:591:591) (608:608:608)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[2\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (1098:1098:1098) (1120:1120:1120)) + (PORT datab (1155:1155:1155) (1240:1240:1240)) + (PORT datad (621:621:621) (637:637:637)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[2\]\~22) + (DELAY + (ABSOLUTE + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (669:669:669) (702:702:702)) + (PORT datad (1093:1093:1093) (1130:1130:1130)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|alu_\|result_lo\[2\]) (DELAY (ABSOLUTE - (PORT clk (1518:1518:1518) (1535:1535:1535)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1283:1283:1283) (1287:1287:1287)) + (PORT clk (1541:1541:1541) (1557:1557:1557)) + (PORT asdata (678:678:678) (699:699:699)) + (PORT ena (2016:2016:2016) (1997:1997:1997)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~6) + (INSTANCE z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\~3) (DELAY (ABSOLUTE - (PORT dataa (339:339:339) (368:368:368)) - (PORT datab (597:597:597) (636:636:636)) - (PORT datac (965:965:965) (999:999:999)) - (PORT datad (590:590:590) (645:645:645)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT datab (273:273:273) (330:330:330)) + (PORT datac (248:248:248) (311:311:311)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[2\]\~3) + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[2\]\~6) (DELAY (ABSOLUTE - (PORT dataa (222:222:222) (276:276:276)) - (PORT datab (653:653:653) (675:675:675)) - (PORT datac (916:916:916) (949:949:949)) - (PORT datad (220:220:220) (264:264:264)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) + (PORT dataa (707:707:707) (780:780:780)) + (PORT datab (1133:1133:1133) (1158:1158:1158)) + (PORT datac (611:611:611) (627:627:627)) + (PORT datad (673:673:673) (728:728:728)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -28139,26 +25629,26 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[2\]\~4) + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[2\]\~7) (DELAY (ABSOLUTE - (PORT dataa (263:263:263) (337:337:337)) - (PORT datab (596:596:596) (614:614:614)) - (PORT datac (585:585:585) (589:589:589)) - (PORT datad (896:896:896) (944:944:944)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (954:954:954) (983:983:983)) + (PORT datab (899:899:899) (929:929:929)) + (PORT datac (171:171:171) (203:203:203)) + (PORT datad (651:651:651) (660:660:660)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_high\[2\]) + (INSTANCE z80_\|alu_\|op2_low\[2\]) (DELAY (ABSOLUTE - (PORT clk (1529:1529:1529) (1531:1531:1531)) + (PORT clk (1535:1535:1535) (1540:1540:1540)) (PORT d (74:74:74) (91:91:91)) (PORT ena (819:819:819) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) @@ -28169,17 +25659,856 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[2\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (653:653:653) (683:683:683)) + (PORT datab (435:435:435) (506:506:506)) + (PORT datac (575:575:575) (624:624:624)) + (PORT datad (670:670:670) (685:685:685)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[2\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (275:275:275) (331:331:331)) + (PORT datac (1117:1117:1117) (1123:1123:1123)) + (PORT datad (322:322:322) (343:343:343)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[2\]\~20) + (DELAY + (ABSOLUTE + (PORT datab (1083:1083:1083) (1100:1100:1100)) + (PORT datad (309:309:309) (325:325:325)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[2\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (242:242:242)) + (PORT datab (703:703:703) (741:741:741)) + (PORT datac (696:696:696) (750:750:750)) + (PORT datad (593:593:593) (611:611:611)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[2\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (950:950:950) (984:984:984)) + (PORT datab (659:659:659) (688:688:688)) + (PORT datac (622:622:622) (649:649:649)) + (PORT datad (851:851:851) (867:867:867)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[2\]\~8) + (DELAY + (ABSOLUTE + (PORT datac (889:889:889) (916:916:916)) + (PORT datad (172:172:172) (198:198:198)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_low\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1547:1547:1547) (1549:1549:1549)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (794:794:794) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op1\[2\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (651:651:651) (707:707:707)) + (PORT datab (1141:1141:1141) (1208:1208:1208)) + (PORT datac (645:645:645) (676:676:676)) + (PORT datad (608:608:608) (660:660:660)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_10\~1) + (DELAY + (ABSOLUTE + (PORT dataa (382:382:382) (410:410:410)) + (PORT datac (185:185:185) (226:226:226)) + (PORT datad (997:997:997) (1055:1055:1055)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_10\~0) + (DELAY + (ABSOLUTE + (PORT dataa (215:215:215) (265:265:265)) + (PORT datab (434:434:434) (504:504:504)) + (PORT datac (575:575:575) (636:636:636)) + (PORT datad (1404:1404:1404) (1413:1413:1413)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (398:398:398) (425:425:425)) + (PORT datab (1375:1375:1375) (1435:1435:1435)) + (PORT datac (180:180:180) (217:217:217)) + (PORT datad (189:189:189) (221:221:221)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|cy_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (255:255:255)) + (PORT datab (1049:1049:1049) (1119:1119:1119)) + (PORT datac (179:179:179) (216:216:216)) + (PORT datad (633:633:633) (651:651:651)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|SYNTHESIZED_WIRE_10\~0) + (DELAY + (ABSOLUTE + (PORT dataa (473:473:473) (551:551:551)) + (PORT datab (228:228:228) (270:270:270)) + (PORT datac (408:408:408) (484:484:484)) + (PORT datad (1402:1402:1402) (1415:1415:1415)) + (IOPATH dataa combout (301:301:301) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|cy_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (256:256:256)) + (PORT datab (228:228:228) (269:269:269)) + (PORT datac (1310:1310:1310) (1377:1377:1377)) + (PORT datad (182:182:182) (211:211:211)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf\~0) + (DELAY + (ABSOLUTE + (PORT dataa (815:815:815) (841:841:841)) + (PORT datab (873:873:873) (893:893:893)) + (PORT datac (207:207:207) (247:247:247)) + (PORT datad (645:645:645) (702:702:702)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (2369:2369:2369) (2430:2430:2430)) + (PORT datab (1735:1735:1735) (1787:1787:1787)) + (PORT datac (895:895:895) (929:929:929)) + (PORT datad (1370:1370:1370) (1410:1410:1410)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (611:611:611) (622:622:622)) + (PORT datab (954:954:954) (1018:1018:1018)) + (PORT datac (192:192:192) (225:225:225)) + (PORT datad (603:603:603) (625:625:625)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf\~1) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (206:206:206) (247:247:247)) + (PORT datad (327:327:327) (344:344:344)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|flags_hf) + (DELAY + (ABSOLUTE + (PORT dataa (923:923:923) (975:975:975)) + (PORT datab (198:198:198) (238:238:238)) + (PORT datac (1881:1881:1881) (1931:1931:1931)) + (PORT datad (1149:1149:1149) (1161:1161:1161)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[4\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (1196:1196:1196) (1252:1252:1252)) + (PORT datab (698:698:698) (741:741:741)) + (PORT datac (359:359:359) (392:392:392)) + (PORT datad (378:378:378) (403:403:403)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[4\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (604:604:604) (626:626:626)) + (PORT datab (1093:1093:1093) (1119:1119:1119)) + (PORT datac (853:853:853) (862:862:862)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[4\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (694:694:694) (749:749:749)) + (PORT datab (341:341:341) (374:374:374)) + (PORT datac (405:405:405) (444:444:444)) + (PORT datad (368:368:368) (394:394:394)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[4\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (647:647:647) (673:673:673)) + (PORT datab (917:917:917) (929:929:929)) + (PORT datac (595:595:595) (614:614:614)) + (PORT datad (663:663:663) (684:684:684)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[4\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (746:746:746) (777:777:777)) + (PORT datab (256:256:256) (317:317:317)) + (PORT datac (174:174:174) (208:208:208)) + (PORT datad (599:599:599) (615:615:615)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[3\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (911:911:911) (923:923:923)) + (PORT datab (1205:1205:1205) (1303:1303:1303)) + (PORT datad (858:858:858) (880:880:880)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[3\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (377:377:377) (403:403:403)) + (PORT datab (1119:1119:1119) (1166:1166:1166)) + (PORT datac (692:692:692) (749:749:749)) + (PORT datad (1069:1069:1069) (1074:1074:1074)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[3\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (871:871:871) (932:932:932)) + (PORT datab (907:907:907) (925:925:925)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[3\]\~25) + (DELAY + (ABSOLUTE + (PORT datab (702:702:702) (739:739:739)) + (PORT datac (693:693:693) (746:746:746)) + (PORT datad (195:195:195) (220:220:220)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[3\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (678:678:678) (751:751:751)) + (PORT datab (1133:1133:1133) (1158:1158:1158)) + (PORT datac (673:673:673) (734:734:734)) + (PORT datad (774:774:774) (776:776:776)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[3\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1193:1193:1193) (1211:1211:1211)) + (PORT datab (901:901:901) (928:928:928)) + (PORT datac (919:919:919) (941:941:941)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_low\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1535:1535:1535) (1540:1540:1540)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[3\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (964:964:964) (991:991:991)) + (PORT datab (811:811:811) (818:818:818)) + (PORT datac (1164:1164:1164) (1176:1176:1176)) + (PORT datad (627:627:627) (661:661:661)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[3\]\~1) + (DELAY + (ABSOLUTE + (PORT datab (905:905:905) (934:934:934)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_high\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1535:1535:1535) (1540:1540:1540)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op2\[3\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (701:701:701) (723:723:723)) + (PORT datab (701:701:701) (774:774:774)) + (PORT datac (885:885:885) (890:890:890)) + (PORT datad (663:663:663) (720:720:720)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|SYNTHESIZED_WIRE_1) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (254:254:254)) + (PORT datab (205:205:205) (245:245:245)) + (PORT datac (1129:1129:1129) (1129:1129:1129)) + (PORT datad (202:202:202) (230:230:230)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|result\~0) + (DELAY + (ABSOLUTE + (PORT dataa (367:367:367) (405:405:405)) + (PORT datab (394:394:394) (419:419:419)) + (PORT datac (551:551:551) (560:560:560)) + (PORT datad (339:339:339) (361:361:361)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (245:245:245) (300:300:300)) + (PORT datab (618:618:618) (675:675:675)) + (PORT datac (1466:1466:1466) (1547:1547:1547)) + (PORT datad (223:223:223) (253:253:253)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1084:1084:1084) (1105:1105:1105)) + (PORT datab (211:211:211) (255:255:255)) + (PORT datad (1179:1179:1179) (1265:1265:1265)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1087:1087:1087) (1092:1092:1092)) + (PORT datab (1119:1119:1119) (1162:1162:1162)) + (PORT datad (307:307:307) (322:322:322)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (266:266:266) (338:338:338)) + (PORT datab (276:276:276) (332:332:332)) + (PORT datac (1117:1117:1117) (1128:1128:1128)) + (PORT datad (250:250:250) (294:294:294)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (643:643:643) (671:671:671)) + (PORT datab (344:344:344) (376:376:376)) + (PORT datac (640:640:640) (694:694:694)) + (PORT datad (609:609:609) (635:635:635)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (871:871:871) (932:932:932)) + (PORT datab (630:630:630) (668:668:668)) + (PORT datac (346:346:346) (371:371:371)) + (PORT datad (556:556:556) (562:562:562)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_34) + (DELAY + (ABSOLUTE + (PORT dataa (885:885:885) (932:932:932)) + (PORT datab (1083:1083:1083) (1097:1097:1097)) + (PORT datac (521:521:521) (536:536:536)) + (PORT datad (632:632:632) (660:660:660)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_sf) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1218:1218:1218) (1200:1200:1200)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~5) + (DELAY + (ABSOLUTE + (PORT dataa (238:238:238) (287:287:287)) + (PORT datab (247:247:247) (295:295:295)) + (PORT datac (621:621:621) (646:646:646)) + (PORT datad (879:879:879) (944:944:944)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1712:1712:1712) (1781:1781:1781)) + (PORT datab (894:894:894) (917:917:917)) + (PORT datac (1041:1041:1041) (1058:1058:1058)) + (PORT datad (939:939:939) (999:999:999)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_nop3pla68M2T2_3) + (DELAY + (ABSOLUTE + (PORT dataa (2280:2280:2280) (2349:2349:2349)) + (PORT datab (2206:2206:2206) (2381:2381:2381)) + (PORT datac (2140:2140:2140) (2225:2225:2225)) + (PORT datad (725:725:725) (814:814:814)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1277:1277:1277) (1318:1318:1318)) + (PORT datab (953:953:953) (983:983:983)) + (PORT datac (2034:2034:2034) (2052:2052:2052)) + (PORT datad (1669:1669:1669) (1733:1733:1733)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~8) + (DELAY + (ABSOLUTE + (PORT dataa (880:880:880) (926:926:926)) + (PORT datab (198:198:198) (238:238:238)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~11) + (DELAY + (ABSOLUTE + (PORT dataa (825:825:825) (825:825:825)) + (PORT datab (1077:1077:1077) (1071:1071:1071)) + (PORT datac (1238:1238:1238) (1269:1269:1269)) + (PORT datad (580:580:580) (592:592:592)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~12) + (DELAY + (ABSOLUTE + (PORT dataa (668:668:668) (729:729:729)) + (PORT datab (664:664:664) (729:729:729)) + (PORT datac (653:653:653) (709:709:709)) + (PORT datad (1168:1168:1168) (1191:1191:1191)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~15) + (DELAY + (ABSOLUTE + (PORT dataa (838:838:838) (864:864:864)) + (PORT datab (742:742:742) (832:832:832)) + (PORT datac (172:172:172) (206:206:206)) + (PORT datad (1009:1009:1009) (1024:1024:1024)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|alu_\|alu_op2\[2\]\~0) (DELAY (ABSOLUTE - (PORT dataa (461:461:461) (534:534:534)) - (PORT datab (695:695:695) (720:720:720)) - (PORT datac (877:877:877) (900:900:900)) - (PORT datad (417:417:417) (490:490:490)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT dataa (705:705:705) (729:729:729)) + (PORT datab (917:917:917) (927:927:927)) + (PORT datac (577:577:577) (626:626:626)) + (PORT datad (657:657:657) (722:722:722)) + (IOPATH dataa combout (337:337:337) (347:347:347)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -28190,12 +26519,12 @@ (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_1) (DELAY (ABSOLUTE - (PORT dataa (388:388:388) (411:411:411)) - (PORT datab (395:395:395) (424:424:424)) - (PORT datac (177:177:177) (214:214:214)) - (PORT datad (345:345:345) (368:368:368)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) + (PORT dataa (207:207:207) (255:255:255)) + (PORT datab (207:207:207) (250:250:250)) + (PORT datac (1131:1131:1131) (1130:1130:1130)) + (PORT datad (632:632:632) (653:653:653)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -28206,10 +26535,10 @@ (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|result\~0) (DELAY (ABSOLUTE - (PORT dataa (368:368:368) (407:407:407)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (180:180:180) (217:217:217)) - (PORT datad (354:354:354) (383:383:383)) + (PORT dataa (214:214:214) (264:264:264)) + (PORT datab (197:197:197) (234:234:234)) + (PORT datac (346:346:346) (370:370:370)) + (PORT datad (634:634:634) (650:650:650)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (243:243:243) (242:242:242)) @@ -28218,30 +26547,32 @@ ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~9) + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_control_\|DFFE_latch_pf_tmp) (DELAY (ABSOLUTE - (PORT dataa (1176:1176:1176) (1207:1207:1207)) - (PORT datab (281:281:281) (344:344:344)) - (PORT datac (244:244:244) (303:303:303)) - (PORT datad (255:255:255) (301:301:301)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT clk (1542:1542:1542) (1558:1558:1558)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (2192:2192:2192) (2164:2164:2164)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~11) + (INSTANCE z80_\|alu_\|alu_parity_out\~0) (DELAY (ABSOLUTE - (PORT dataa (1695:1695:1695) (1779:1779:1779)) - (PORT datac (887:887:887) (904:904:904)) - (PORT datad (883:883:883) (900:900:900)) - (IOPATH dataa combout (356:356:356) (368:368:368)) + (PORT dataa (938:938:938) (957:957:957)) + (PORT datab (390:390:390) (456:456:456)) + (PORT datac (865:865:865) (875:875:875)) + (PORT datad (1093:1093:1093) (1147:1147:1147)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -28249,76 +26580,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~12) + (INSTANCE z80_\|alu_\|alu_parity_out\~1) (DELAY (ABSOLUTE - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (911:911:911) (960:960:960)) - (PORT datad (237:237:237) (277:277:277)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (638:638:638) (711:711:711)) - (PORT datab (1166:1166:1166) (1213:1213:1213)) - (PORT datac (421:421:421) (493:493:493)) - (PORT datad (662:662:662) (719:719:719)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (1116:1116:1116) (1164:1164:1164)) - (PORT datac (603:603:603) (622:622:622)) - (PORT datad (629:629:629) (654:654:654)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1253:1253:1253) (1347:1347:1347)) - (PORT datab (239:239:239) (295:295:295)) - (PORT datac (959:959:959) (993:993:993)) - (PORT datad (329:329:329) (348:348:348)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[6\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (1295:1295:1295) (1347:1347:1347)) - (PORT datab (963:963:963) (1021:1021:1021)) - (PORT datac (1621:1621:1621) (1653:1653:1653)) - (PORT datad (867:867:867) (886:886:886)) - (IOPATH dataa combout (350:350:350) (366:366:366)) + (PORT dataa (540:540:540) (566:566:566)) + (PORT datab (530:530:530) (556:556:556)) + (PORT datac (171:171:171) (205:205:205)) + (PORT datad (864:864:864) (870:870:870)) + (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -28327,13 +26596,141 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[6\]\~23) + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~4) (DELAY (ABSOLUTE - (PORT dataa (644:644:644) (667:667:667)) - (PORT datab (983:983:983) (1034:1034:1034)) - (PORT datac (313:313:313) (343:343:343)) - (PORT datad (228:228:228) (273:273:273)) + (PORT dataa (937:937:937) (954:954:954)) + (PORT datab (1448:1448:1448) (1493:1493:1493)) + (PORT datac (747:747:747) (825:825:825)) + (PORT datad (1218:1218:1218) (1214:1214:1214)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~5) + (DELAY + (ABSOLUTE + (PORT dataa (998:998:998) (1078:1078:1078)) + (PORT datab (537:537:537) (564:564:564)) + (PORT datac (556:556:556) (566:566:566)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1711:1711:1711) (1763:1763:1763)) + (PORT datab (1530:1530:1530) (1589:1589:1589)) + (PORT datac (746:746:746) (827:827:827)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~1) + (DELAY + (ABSOLUTE + (PORT dataa (996:996:996) (1074:1074:1074)) + (PORT datab (1245:1245:1245) (1252:1252:1252)) + (PORT datac (903:903:903) (917:917:917)) + (PORT datad (1415:1415:1415) (1455:1455:1455)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~2) + (DELAY + (ABSOLUTE + (PORT dataa (969:969:969) (1032:1032:1032)) + (PORT datab (1232:1232:1232) (1293:1293:1293)) + (PORT datac (1228:1228:1228) (1282:1282:1282)) + (PORT datad (586:586:586) (644:644:644)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~1) + (DELAY + (ABSOLUTE + (PORT dataa (970:970:970) (1065:1065:1065)) + (PORT datab (965:965:965) (1048:1048:1048)) + (PORT datac (244:244:244) (323:323:323)) + (PORT datad (420:420:420) (487:487:487)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~3) + (DELAY + (ABSOLUTE + (PORT dataa (281:281:281) (374:374:374)) + (PORT datab (270:270:270) (354:354:354)) + (PORT datac (243:243:243) (321:321:321)) + (PORT datad (805:805:805) (861:861:861)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~0) + (DELAY + (ABSOLUTE + (PORT dataa (269:269:269) (363:363:363)) + (PORT datab (408:408:408) (479:479:479)) + (PORT datac (244:244:244) (322:322:322)) + (PORT datad (403:403:403) (466:466:466)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~4) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (201:201:201) (241:241:241)) + (PORT datac (615:615:615) (627:627:627)) + (PORT datad (315:315:315) (336:336:336)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -28343,155 +26740,46 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|out\[6\]\~1) + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~5) (DELAY (ABSOLUTE - (PORT dataa (390:390:390) (465:465:465)) - (PORT datab (263:263:263) (345:345:345)) - (PORT datac (236:236:236) (312:312:312)) - (PORT datad (196:196:196) (222:222:222)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|out\[6\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1182:1182:1182) (1227:1227:1227)) - (PORT datab (658:658:658) (671:671:671)) - (PORT datac (632:632:632) (691:691:691)) - (PORT datad (234:234:234) (310:310:310)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1155:1155:1155) (1213:1213:1213)) - (PORT datab (894:894:894) (942:942:942)) - (PORT datac (660:660:660) (687:687:687)) - (PORT datad (883:883:883) (901:901:901)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~20) - (DELAY - (ABSOLUTE - (PORT datab (924:924:924) (933:933:933)) - (PORT datac (1121:1121:1121) (1153:1153:1153)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (970:970:970) (1018:1018:1018)) - (PORT datab (950:950:950) (1001:1001:1001)) - (PORT datac (170:170:170) (202:202:202)) - (PORT datad (876:876:876) (911:911:911)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (689:689:689) (714:714:714)) - (PORT datab (198:198:198) (236:236:236)) - (PORT datac (1597:1597:1597) (1627:1627:1627)) - (PORT datad (861:861:861) (875:875:875)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_zero_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (640:640:640) (655:655:655)) - (PORT datab (1245:1245:1245) (1272:1272:1272)) - (PORT datac (1147:1147:1147) (1195:1195:1195)) - (PORT datad (336:336:336) (365:365:365)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\~3) - (DELAY - (ABSOLUTE - (PORT datab (287:287:287) (348:348:348)) - (PORT datad (249:249:249) (295:295:295)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (PORT dataa (884:884:884) (911:911:911)) + (PORT datab (1164:1164:1164) (1198:1198:1198)) + (PORT datad (2161:2161:2161) (2216:2216:2216)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|im1) + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep) (DELAY (ABSOLUTE - (PORT clk (1525:1525:1525) (1541:1541:1541)) + (PORT clk (1523:1523:1523) (1536:1536:1536)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1571:1571:1571) (1550:1550:1550)) - (PORT ena (1258:1258:1258) (1280:1280:1280)) + (PORT clrn (1566:1566:1566) (1548:1548:1548)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) ) (TIMINGCHECK (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_ff_oe\~0) + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~2) (DELAY (ABSOLUTE - (PORT dataa (1215:1215:1215) (1260:1260:1260)) - (PORT datab (1208:1208:1208) (1291:1291:1291)) - (PORT datac (1222:1222:1222) (1290:1290:1290)) - (PORT datad (272:272:272) (349:349:349)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (304:304:304) (311:311:311)) + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (1161:1161:1161) (1229:1229:1229)) + (PORT datac (408:408:408) (474:474:474)) + (PORT datad (1668:1668:1668) (1715:1715:1715)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -28499,31 +26787,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_ff_oe\~1) + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~3) (DELAY (ABSOLUTE - (PORT dataa (353:353:353) (485:485:485)) - (PORT datab (196:196:196) (235:235:235)) - (PORT datac (1143:1143:1143) (1174:1174:1174)) - (PORT datad (1174:1174:1174) (1212:1212:1212)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (775:775:775) (860:860:860)) + (PORT datac (1129:1129:1129) (1197:1197:1197)) + (PORT datad (1504:1504:1504) (1551:1551:1551)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[0\]\~4) + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~7) (DELAY (ABSOLUTE - (PORT dataa (993:993:993) (1051:1051:1051)) - (PORT datab (1152:1152:1152) (1212:1212:1212)) - (PORT datac (671:671:671) (716:716:716)) - (PORT datad (621:621:621) (670:670:670)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT dataa (1708:1708:1708) (1759:1759:1759)) + (PORT datab (1533:1533:1533) (1591:1591:1591)) + (PORT datac (2080:2080:2080) (2120:2120:2120)) + (PORT datad (1220:1220:1220) (1219:1219:1219)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -28531,59 +26819,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[6\]\~8) + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~8) (DELAY (ABSOLUTE - (PORT datab (864:864:864) (885:885:885)) - (PORT datac (946:946:946) (986:986:986)) - (PORT datad (214:214:214) (249:249:249)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~37) - (DELAY - (ABSOLUTE - (PORT dataa (1300:1300:1300) (1399:1399:1399)) - (PORT datab (2075:2075:2075) (2259:2259:2259)) - (PORT datac (822:822:822) (879:879:879)) - (PORT datad (913:913:913) (964:964:964)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~28) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (1269:1269:1269) (1304:1304:1304)) - (PORT datac (1404:1404:1404) (1456:1456:1456)) - (PORT datad (913:913:913) (977:977:977)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~29) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (242:242:242)) - (PORT datab (241:241:241) (281:281:281)) - (PORT datac (1941:1941:1941) (2072:2072:2072)) - (PORT datad (187:187:187) (218:218:218)) + (PORT dataa (941:941:941) (961:961:961)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (746:746:746) (824:824:824)) + (PORT datad (969:969:969) (1032:1032:1032)) (IOPATH dataa combout (304:304:304) (308:308:308)) (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -28593,13 +26835,45 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~30) + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~9) (DELAY (ABSOLUTE - (PORT dataa (875:875:875) (914:914:914)) - (PORT datab (230:230:230) (277:277:277)) - (PORT datac (631:631:631) (653:653:653)) - (PORT datad (955:955:955) (999:999:999)) + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (175:175:175) (202:202:202)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~0) + (DELAY + (ABSOLUTE + (PORT dataa (861:861:861) (924:924:924)) + (PORT datab (266:266:266) (349:349:349)) + (PORT datac (826:826:826) (871:871:871)) + (PORT datad (603:603:603) (618:618:618)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1167:1167:1167) (1185:1185:1185)) + (PORT datab (859:859:859) (905:905:905)) + (PORT datac (1075:1075:1075) (1090:1090:1090)) + (PORT datad (174:174:174) (200:200:200)) (IOPATH dataa combout (327:327:327) (347:347:347)) (IOPATH datab combout (331:331:331) (342:342:342)) (IOPATH datac combout (243:243:243) (241:241:241)) @@ -28608,48 +26882,46 @@ ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~37) + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf) (DELAY (ABSOLUTE - (PORT dataa (1051:1051:1051) (1095:1095:1095)) - (PORT datab (1067:1067:1067) (1105:1105:1105)) - (PORT datac (1033:1033:1033) (1064:1064:1064)) - (PORT datad (634:634:634) (644:644:644)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~55) + (INSTANCE z80_\|alu_control_\|sel\[1\]\~0) (DELAY (ABSOLUTE - (PORT dataa (960:960:960) (1056:1056:1056)) - (PORT datab (1130:1130:1130) (1132:1132:1132)) - (PORT datac (939:939:939) (1031:1031:1031)) - (PORT datad (1060:1060:1060) (1062:1062:1062)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~38) - (DELAY - (ABSOLUTE - (PORT dataa (888:888:888) (940:940:940)) - (PORT datab (200:200:200) (240:240:240)) - (PORT datac (539:539:539) (555:555:555)) - (PORT datad (545:545:545) (556:556:556)) + (PORT dataa (1236:1236:1236) (1265:1265:1265)) + (PORT datab (1389:1389:1389) (1522:1522:1522)) + (PORT datac (201:201:201) (251:251:251)) + (PORT datad (858:858:858) (898:898:898)) (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|b2v_inst_cond_mux\|out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (274:274:274) (366:366:366)) + (PORT datab (610:610:610) (623:623:623)) + (PORT datac (1009:1009:1009) (1040:1040:1040)) + (PORT datad (1045:1045:1045) (1094:1094:1094)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (304:304:304) (311:311:311)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -28657,15 +26929,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~34) + (INSTANCE z80_\|alu_control_\|b2v_inst_cond_mux\|out\~1) (DELAY (ABSOLUTE - (PORT dataa (682:682:682) (715:715:715)) - (PORT datab (898:898:898) (929:929:929)) - (PORT datac (1980:1980:1980) (2019:2019:2019)) - (PORT datad (830:830:830) (842:842:842)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) + (PORT dataa (905:905:905) (961:961:961)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (1008:1008:1008) (1039:1039:1039)) + (PORT datad (239:239:239) (309:309:309)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -28673,137 +26945,88 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~3) + (INSTANCE z80_\|alu_control_\|flags_cond_true\~0) (DELAY (ABSOLUTE - (PORT datab (833:833:833) (894:894:894)) - (PORT datac (622:622:622) (675:675:675)) - (PORT datad (207:207:207) (239:239:239)) + (PORT dataa (983:983:983) (1049:1049:1049)) + (PORT datab (762:762:762) (857:857:857)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~31) + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_control_\|flags_cond_true) (DELAY (ABSOLUTE - (PORT dataa (231:231:231) (279:279:279)) - (PORT datab (238:238:238) (284:284:284)) - (PORT datac (356:356:356) (385:385:385)) - (PORT datad (1060:1060:1060) (1062:1062:1062)) - (IOPATH dataa combout (354:354:354) (367:367:367)) + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~20) + (DELAY + (ABSOLUTE + (PORT dataa (1921:1921:1921) (2028:2028:2028)) + (PORT datab (896:896:896) (1016:1016:1016)) + (PORT datac (838:838:838) (860:860:860)) + (PORT datad (927:927:927) (1020:1020:1020)) + (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~32) + (INSTANCE z80_\|execute_\|ctl_sw_4d\~1) (DELAY (ABSOLUTE - (PORT dataa (719:719:719) (787:787:787)) - (PORT datab (1609:1609:1609) (1627:1627:1627)) - (PORT datac (617:617:617) (649:649:649)) - (PORT datad (544:544:544) (562:562:562)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (914:914:914) (954:954:954)) + (PORT datab (1571:1571:1571) (1598:1598:1598)) + (PORT datac (589:589:589) (609:609:609)) + (PORT datad (345:345:345) (368:368:368)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~33) + (INSTANCE z80_\|execute_\|ctl_sw_4d\~6) (DELAY (ABSOLUTE - (PORT datab (553:553:553) (575:575:575)) - (PORT datac (1318:1318:1318) (1317:1317:1317)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~35) - (DELAY - (ABSOLUTE - (PORT dataa (1048:1048:1048) (1070:1070:1070)) - (PORT datab (577:577:577) (591:591:591)) - (PORT datac (783:783:783) (785:785:785)) - (PORT datad (770:770:770) (770:770:770)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (180:180:180) (208:208:208)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|DFFE_mrd_ff1) + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[1\]) (DELAY (ABSOLUTE - (PORT clk (1535:1535:1535) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1591:1591:1591) (1566:1566:1566)) - (PORT ena (1291:1291:1291) (1310:1310:1310)) + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (893:893:893) (901:901:901)) + (PORT ena (1200:1200:1200) (1181:1181:1181)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|wait_mrd\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (815:815:815) (866:866:866)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|wait_mrd) - (DELAY - (ABSOLUTE - (PORT clk (1540:1540:1540) (1538:1538:1538)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1588:1588:1588) (1565:1565:1565)) - (PORT ena (1172:1172:1172) (1151:1151:1151)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|DFFE_mrd_ff3) - (DELAY - (ABSOLUTE - (PORT clk (1542:1542:1542) (1544:1544:1544)) - (PORT asdata (1226:1226:1226) (1290:1290:1290)) - (PORT clrn (1591:1591:1591) (1566:1566:1566)) - (PORT ena (1321:1321:1321) (1347:1347:1347)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) ) (TIMINGCHECK @@ -28813,12 +27036,492 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|nRD_out\~1) + (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~4) (DELAY (ABSOLUTE - (PORT dataa (909:909:909) (983:983:983)) - (PORT datad (215:215:215) (284:284:284)) + (PORT dataa (892:892:892) (941:941:941)) + (PORT datab (1199:1199:1199) (1216:1216:1216)) + (PORT datad (403:403:403) (442:442:442)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1231:1231:1231) (1237:1237:1237)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~5) + (DELAY + (ABSOLUTE + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (215:215:215) (292:292:292)) + (PORT datad (613:613:613) (638:638:638)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|d1_out) + (DELAY + (ABSOLUTE + (PORT dataa (665:665:665) (729:729:729)) + (PORT datac (192:192:192) (226:226:226)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1648:1648:1648) (1674:1674:1674)) + (PORT datab (198:198:198) (236:236:236)) + (PORT datac (1059:1059:1059) (1066:1066:1066)) + (PORT datad (349:349:349) (378:378:378)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT asdata (1302:1302:1302) (1309:1309:1309)) + (PORT ena (1438:1438:1438) (1476:1476:1476)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (701:701:701) (767:767:767)) + (PORT datab (1396:1396:1396) (1392:1392:1392)) + (PORT datad (849:849:849) (862:862:862)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT asdata (979:979:979) (998:998:998)) + (PORT ena (790:790:790) (782:782:782)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT asdata (980:980:980) (995:995:995)) + (PORT ena (1288:1288:1288) (1306:1306:1306)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (257:257:257) (313:313:313)) + (PORT datab (240:240:240) (321:321:321)) + (PORT datad (634:634:634) (698:698:698)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT asdata (970:970:970) (1000:1000:1000)) + (PORT ena (1220:1220:1220) (1212:1212:1212)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT asdata (972:972:972) (1003:1003:1003)) + (PORT ena (1200:1200:1200) (1188:1188:1188)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (861:861:861) (934:934:934)) + (PORT datab (243:243:243) (325:325:325)) + (PORT datad (661:661:661) (726:726:726)) (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1535:1535:1535)) + (PORT asdata (1831:1831:1831) (1846:1846:1846)) + (PORT ena (1274:1274:1274) (1265:1265:1265)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~27) + (DELAY + (ABSOLUTE + (PORT datab (604:604:604) (620:620:620)) + (PORT datad (923:923:923) (952:952:952)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (590:590:590) (603:603:603)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datad (808:808:808) (811:811:811)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT asdata (1017:1017:1017) (1050:1050:1050)) + (PORT ena (981:981:981) (980:980:980)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT asdata (1017:1017:1017) (1051:1051:1051)) + (PORT ena (811:811:811) (804:804:804)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (243:243:243) (329:329:329)) + (PORT datab (252:252:252) (300:300:300)) + (PORT datad (233:233:233) (270:270:270)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1549:1549:1549)) + (PORT asdata (563:563:563) (596:596:596)) + (PORT ena (974:974:974) (969:969:969)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1549:1549:1549)) + (PORT asdata (566:566:566) (599:599:599)) + (PORT ena (975:975:975) (970:970:970)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (407:407:407) (451:451:451)) + (PORT datab (440:440:440) (467:467:467)) + (PORT datad (216:216:216) (285:285:285)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1549:1549:1549)) + (PORT asdata (969:969:969) (979:979:979)) + (PORT ena (1240:1240:1240) (1231:1231:1231)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1549:1549:1549)) + (PORT asdata (969:969:969) (979:979:979)) + (PORT ena (1207:1207:1207) (1180:1180:1180)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (695:695:695) (738:738:738)) + (PORT datab (706:706:706) (729:729:729)) + (PORT datad (216:216:216) (284:284:284)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (609:609:609) (629:629:629)) + (PORT datab (625:625:625) (639:639:639)) + (PORT datac (173:173:173) (207:207:207)) + (PORT datad (334:334:334) (356:356:356)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (864:864:864) (905:905:905)) + (PORT datab (867:867:867) (896:896:896)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (202:202:202) (229:229:229)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_ds\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (828:828:828) (858:858:858)) + (PORT datab (1125:1125:1125) (1165:1165:1165)) + (PORT datac (655:655:655) (680:680:680)) + (PORT datad (656:656:656) (708:708:708)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[1\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (204:204:204) (249:249:249)) + (PORT datab (706:706:706) (725:725:725)) + (PORT datac (407:407:407) (452:452:452)) + (PORT datad (834:834:834) (844:844:844)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[1\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (885:885:885) (898:898:898)) + (PORT datab (1129:1129:1129) (1147:1147:1147)) + (PORT datac (359:359:359) (390:390:390)) + (PORT datad (1401:1401:1401) (1460:1460:1460)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[1\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (348:348:348) (380:380:380)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (600:600:600) (611:611:611)) + (PORT datad (216:216:216) (251:251:251)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (571:571:571) (599:599:599)) + (PORT datac (1398:1398:1398) (1439:1439:1439)) + (PORT datad (597:597:597) (611:611:611)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -28828,12 +27531,12 @@ (INSTANCE z80_\|execute_\|nextM\~4) (DELAY (ABSOLUTE - (PORT dataa (233:233:233) (281:281:281)) - (PORT datab (702:702:702) (781:781:781)) - (PORT datac (856:856:856) (898:898:898)) - (PORT datad (1074:1074:1074) (1111:1111:1111)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT dataa (1236:1236:1236) (1302:1302:1302)) + (PORT datab (677:677:677) (701:701:701)) + (PORT datac (1229:1229:1229) (1298:1298:1298)) + (PORT datad (664:664:664) (715:715:715)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -28844,12 +27547,12 @@ (INSTANCE z80_\|execute_\|ctl_iorw\~12) (DELAY (ABSOLUTE - (PORT dataa (1890:1890:1890) (1960:1960:1960)) - (PORT datab (1472:1472:1472) (1522:1522:1522)) - (PORT datac (1489:1489:1489) (1536:1536:1536)) - (PORT datad (1919:1919:1919) (1985:1985:1985)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT dataa (894:894:894) (948:948:948)) + (PORT datab (1333:1333:1333) (1473:1473:1473)) + (PORT datac (890:890:890) (957:957:957)) + (PORT datad (1498:1498:1498) (1591:1591:1591)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -28860,10 +27563,10 @@ (INSTANCE z80_\|execute_\|ctl_iorw\~8) (DELAY (ABSOLUTE - (PORT dataa (1104:1104:1104) (1152:1152:1152)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (201:201:201) (236:236:236)) - (PORT datad (679:679:679) (747:747:747)) + (PORT dataa (1241:1241:1241) (1304:1304:1304)) + (PORT datab (645:645:645) (695:695:695)) + (PORT datac (926:926:926) (972:972:972)) + (PORT datad (658:658:658) (708:708:708)) (IOPATH dataa combout (304:304:304) (299:299:299)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -28876,12 +27579,12 @@ (INSTANCE z80_\|execute_\|ctl_iorw\~9) (DELAY (ABSOLUTE - (PORT dataa (876:876:876) (891:891:891)) - (PORT datab (1170:1170:1170) (1227:1227:1227)) - (PORT datac (822:822:822) (840:840:840)) - (PORT datad (805:805:805) (814:814:814)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (331:331:331) (342:342:342)) + (PORT dataa (1705:1705:1705) (1717:1717:1717)) + (PORT datab (1161:1161:1161) (1188:1188:1188)) + (PORT datac (418:418:418) (456:456:456)) + (PORT datad (1002:1002:1002) (1015:1015:1015)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -28892,10 +27595,10 @@ (INSTANCE z80_\|memory_ifc_\|DFFE_iorq_ff1) (DELAY (ABSOLUTE - (PORT clk (1535:1535:1535) (1551:1551:1551)) + (PORT clk (1531:1531:1531) (1550:1550:1550)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1591:1591:1591) (1566:1566:1566)) - (PORT ena (1291:1291:1291) (1310:1310:1310)) + (PORT clrn (1578:1578:1578) (1557:1557:1557)) + (PORT ena (1463:1463:1463) (1456:1456:1456)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -28905,43 +27608,15 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_15\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (220:220:220) (290:290:290)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_15) (DELAY (ABSOLUTE - (PORT clk (1535:1535:1535) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1591:1591:1591) (1566:1566:1566)) - (PORT ena (1291:1291:1291) (1310:1310:1310)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|wait_iorq) - (DELAY - (ABSOLUTE - (PORT clk (1542:1542:1542) (1544:1544:1544)) - (PORT asdata (581:581:581) (655:655:655)) - (PORT clrn (1591:1591:1591) (1566:1566:1566)) - (PORT ena (1321:1321:1321) (1347:1347:1347)) + (PORT clk (1531:1531:1531) (1550:1550:1550)) + (PORT asdata (742:742:742) (811:811:811)) + (PORT clrn (1578:1578:1578) (1557:1557:1557)) + (PORT ena (1463:1463:1463) (1456:1456:1456)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -28951,15 +27626,43 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|wait_iorq\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (226:226:226) (298:298:298)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|wait_iorq) + (DELAY + (ABSOLUTE + (PORT clk (1541:1541:1541) (1540:1540:1540)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1578:1578:1578) (1557:1557:1557)) + (PORT ena (1434:1434:1434) (1415:1415:1415)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|memory_ifc_\|DFFE_iorq_ff4) (DELAY (ABSOLUTE - (PORT clk (1542:1542:1542) (1544:1544:1544)) - (PORT asdata (567:567:567) (645:645:645)) - (PORT clrn (1591:1591:1591) (1566:1566:1566)) - (PORT ena (1321:1321:1321) (1347:1347:1347)) + (PORT clk (1541:1541:1541) (1540:1540:1540)) + (PORT asdata (567:567:567) (643:643:643)) + (PORT clrn (1578:1578:1578) (1557:1557:1557)) + (PORT ena (1434:1434:1434) (1415:1415:1415)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -28974,93 +27677,29 @@ (INSTANCE z80_\|memory_ifc_\|iorq\~0) (DELAY (ABSOLUTE - (PORT datab (250:250:250) (335:335:335)) - (PORT datad (613:613:613) (663:663:663)) + (PORT datab (250:250:250) (333:333:333)) + (PORT datad (224:224:224) (295:295:295)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIORead\~1) - (DELAY - (ABSOLUTE - (PORT dataa (222:222:222) (265:265:265)) - (PORT datab (941:941:941) (1024:1024:1024)) - (PORT datac (374:374:374) (401:401:401)) - (PORT datad (217:217:217) (243:243:243)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIORead\~2) - (DELAY - (ABSOLUTE - (PORT dataa (888:888:888) (913:913:913)) - (PORT datab (215:215:215) (260:260:260)) - (PORT datac (1187:1187:1187) (1208:1208:1208)) - (PORT datad (1091:1091:1091) (1137:1137:1137)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIORead\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1889:1889:1889) (1932:1932:1932)) - (PORT datab (1525:1525:1525) (1597:1597:1597)) - (PORT datac (2202:2202:2202) (2248:2248:2248)) - (PORT datad (210:210:210) (242:242:242)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIORead\~3) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (263:263:263)) - (PORT datab (336:336:336) (366:366:366)) - (PORT datac (586:586:586) (589:589:589)) - (PORT datad (351:351:351) (382:382:382)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|memory_ifc_\|DFFE_m1_ff1) (DELAY (ABSOLUTE - (PORT clk (1540:1540:1540) (1541:1541:1541)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1588:1588:1588) (1563:1563:1563)) - (PORT ena (1810:1810:1810) (1851:1851:1851)) + (PORT clk (1541:1541:1541) (1540:1540:1540)) + (PORT asdata (909:909:909) (908:908:908)) + (PORT clrn (1578:1578:1578) (1557:1557:1557)) + (PORT ena (1434:1434:1434) (1415:1415:1415)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) ) ) @@ -29069,7 +27708,7 @@ (INSTANCE z80_\|memory_ifc_\|wait_m_ALTERA_SYNTHESIZED1\~0) (DELAY (ABSOLUTE - (PORT datad (586:586:586) (642:642:642)) + (PORT datad (220:220:220) (290:290:290)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -29079,10 +27718,10 @@ (INSTANCE z80_\|memory_ifc_\|wait_m_ALTERA_SYNTHESIZED1) (DELAY (ABSOLUTE - (PORT clk (1542:1542:1542) (1544:1544:1544)) + (PORT clk (1541:1541:1541) (1540:1540:1540)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1591:1591:1591) (1566:1566:1566)) - (PORT ena (1321:1321:1321) (1347:1347:1347)) + (PORT clrn (1578:1578:1578) (1557:1557:1557)) + (PORT ena (1434:1434:1434) (1415:1415:1415)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -29097,10 +27736,10 @@ (INSTANCE z80_\|memory_ifc_\|DFFE_m1_ff3) (DELAY (ABSOLUTE - (PORT clk (1535:1535:1535) (1551:1551:1551)) - (PORT asdata (568:568:568) (646:646:646)) - (PORT clrn (1591:1591:1591) (1566:1566:1566)) - (PORT ena (1291:1291:1291) (1310:1310:1310)) + (PORT clk (1531:1531:1531) (1550:1550:1550)) + (PORT asdata (566:566:566) (646:646:646)) + (PORT clrn (1578:1578:1578) (1557:1557:1557)) + (PORT ena (1463:1463:1463) (1456:1456:1456)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -29115,11 +27754,11 @@ (INSTANCE z80_\|memory_ifc_\|nRD_out\~0) (DELAY (ABSOLUTE - (PORT dataa (1456:1456:1456) (1520:1520:1520)) - (PORT datab (251:251:251) (336:336:336)) - (PORT datad (1485:1485:1485) (1574:1574:1574)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) + (PORT dataa (251:251:251) (341:341:341)) + (PORT datab (691:691:691) (771:771:771)) + (PORT datad (888:888:888) (958:958:958)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -29127,99 +27766,151 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|nRD_out\~2) + (INSTANCE z80_\|execute_\|fIORead\~0) (DELAY (ABSOLUTE - (PORT dataa (340:340:340) (376:376:376)) - (PORT datab (352:352:352) (391:391:391)) - (PORT datac (1027:1027:1027) (1030:1030:1030)) - (PORT datad (180:180:180) (209:209:209)) - (IOPATH dataa combout (371:371:371) (376:376:376)) + (PORT dataa (1279:1279:1279) (1321:1321:1321)) + (PORT datab (2174:2174:2174) (2263:2263:2263)) + (PORT datac (1118:1118:1118) (1130:1130:1130)) + (PORT datad (2170:2170:2170) (2342:2342:2342)) + (IOPATH dataa combout (327:327:327) (347:347:347)) (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Equal2\~1) + (INSTANCE z80_\|execute_\|fIORead\~1) (DELAY (ABSOLUTE - (PORT dataa (1747:1747:1747) (1852:1852:1852)) - (PORT datab (1597:1597:1597) (1730:1730:1730)) - (PORT datac (1200:1200:1200) (1265:1265:1265)) - (IOPATH dataa combout (356:356:356) (368:368:368)) + (PORT dataa (666:666:666) (725:725:725)) + (PORT datab (1591:1591:1591) (1692:1692:1692)) + (PORT datac (1661:1661:1661) (1724:1724:1724)) + (PORT datad (195:195:195) (219:219:219)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIORead\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1692:1692:1692) (1763:1763:1763)) + (PORT datab (228:228:228) (268:268:268)) + (PORT datac (171:171:171) (203:203:203)) + (PORT datad (1162:1162:1162) (1199:1199:1199)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIOWrite\~1) + (DELAY + (ABSOLUTE + (PORT dataa (682:682:682) (765:765:765)) + (PORT datac (994:994:994) (1080:1080:1080)) + (PORT datad (194:194:194) (220:220:220)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIORead\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1209:1209:1209) (1261:1261:1261)) + (PORT datab (650:650:650) (700:700:700)) + (PORT datac (1322:1322:1322) (1379:1379:1379)) + (PORT datad (181:181:181) (210:210:210)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~30) + (DELAY + (ABSOLUTE + (PORT dataa (1161:1161:1161) (1178:1178:1178)) + (PORT datab (1372:1372:1372) (1394:1394:1394)) + (PORT datac (1442:1442:1442) (1487:1487:1487)) + (PORT datad (1300:1300:1300) (1339:1339:1339)) + (IOPATH dataa combout (341:341:341) (319:319:319)) (IOPATH datab combout (342:342:342) (318:318:318)) (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~0) + (INSTANCE z80_\|execute_\|ctl_mRead\~31) (DELAY (ABSOLUTE - (PORT dataa (2395:2395:2395) (2551:2551:2551)) - (PORT datad (1014:1014:1014) (1128:1128:1128)) + (PORT dataa (947:947:947) (994:994:994)) + (PORT datac (592:592:592) (623:623:623)) + (PORT datad (858:858:858) (892:892:892)) (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~5) + (INSTANCE z80_\|execute_\|nextM\~3) (DELAY (ABSOLUTE - (PORT datab (1342:1342:1342) (1445:1445:1445)) - (PORT datac (2885:2885:2885) (3060:3060:3060)) - (PORT datad (2470:2470:2470) (2672:2672:2672)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (1192:1192:1192) (1262:1262:1262)) + (PORT datab (366:366:366) (408:408:408)) + (PORT datac (1561:1561:1561) (1669:1669:1669)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~6) + (INSTANCE z80_\|execute_\|ctl_mRead\~29) (DELAY (ABSOLUTE - (PORT dataa (378:378:378) (401:401:401)) - (PORT datab (883:883:883) (892:892:892)) - (PORT datac (957:957:957) (1029:1029:1029)) - (PORT datad (1073:1073:1073) (1058:1058:1058)) + (PORT dataa (231:231:231) (277:277:277)) + (PORT datab (1152:1152:1152) (1217:1217:1217)) + (PORT datac (922:922:922) (972:972:972)) + (PORT datad (1258:1258:1258) (1312:1312:1312)) (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~2) + (INSTANCE z80_\|execute_\|setM1\~58) (DELAY (ABSOLUTE - (PORT dataa (931:931:931) (1027:1027:1027)) - (PORT datac (1189:1189:1189) (1270:1270:1270)) - (PORT datad (2029:2029:2029) (2154:2154:2154)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1470:1470:1470) (1514:1514:1514)) - (PORT datab (897:897:897) (976:976:976)) - (PORT datac (362:362:362) (383:383:383)) - (PORT datad (193:193:193) (218:218:218)) + (PORT dataa (264:264:264) (351:351:351)) + (PORT datab (279:279:279) (360:360:360)) + (PORT datac (590:590:590) (620:620:620)) + (PORT datad (819:819:819) (832:832:832)) (IOPATH dataa combout (341:341:341) (319:319:319)) (IOPATH datab combout (342:342:342) (318:318:318)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -29229,14 +27920,272 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~1) + (INSTANCE z80_\|execute_\|setM1\~38) (DELAY (ABSOLUTE - (PORT dataa (678:678:678) (736:736:736)) - (PORT datab (837:837:837) (873:873:873)) - (PORT datac (876:876:876) (891:891:891)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (354:354:354) (349:349:349)) + (PORT datac (882:882:882) (918:918:918)) + (PORT datad (181:181:181) (209:209:209)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1166:1166:1166) (1211:1211:1211)) + (PORT datab (634:634:634) (687:687:687)) + (PORT datad (632:632:632) (649:649:649)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~39) + (DELAY + (ABSOLUTE + (PORT dataa (1118:1118:1118) (1184:1184:1184)) + (PORT datac (847:847:847) (847:847:847)) + (PORT datad (1982:1982:1982) (2076:2076:2076)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~40) + (DELAY + (ABSOLUTE + (PORT dataa (847:847:847) (900:900:900)) + (PORT datab (912:912:912) (955:955:955)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (799:799:799) (849:849:849)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~32) + (DELAY + (ABSOLUTE + (PORT dataa (217:217:217) (269:269:269)) + (PORT datab (938:938:938) (966:966:966)) + (PORT datac (344:344:344) (377:377:377)) + (PORT datad (361:361:361) (382:382:382)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~33) + (DELAY + (ABSOLUTE + (PORT dataa (382:382:382) (406:406:406)) + (PORT datab (706:706:706) (753:753:753)) + (PORT datac (1380:1380:1380) (1388:1388:1388)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|DFFE_mrd_ff1) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1558:1558:1558) (1539:1539:1539)) + (PORT ena (1458:1458:1458) (1464:1464:1464)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|wait_mrd\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (922:922:922) (980:980:980)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|wait_mrd) + (DELAY + (ABSOLUTE + (PORT clk (1541:1541:1541) (1540:1540:1540)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1578:1578:1578) (1557:1557:1557)) + (PORT ena (1434:1434:1434) (1415:1415:1415)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|DFFE_mrd_ff3) + (DELAY + (ABSOLUTE + (PORT clk (1541:1541:1541) (1540:1540:1540)) + (PORT asdata (575:575:575) (657:657:657)) + (PORT clrn (1578:1578:1578) (1557:1557:1557)) + (PORT ena (1434:1434:1434) (1415:1415:1415)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|nRD_out\~1) + (DELAY + (ABSOLUTE + (PORT datac (232:232:232) (316:316:316)) + (PORT datad (217:217:217) (286:286:286)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|nRD_out\~2) + (DELAY + (ABSOLUTE + (PORT dataa (359:359:359) (396:396:396)) + (PORT datab (352:352:352) (382:382:382)) + (PORT datac (617:617:617) (624:624:624)) + (PORT datad (328:328:328) (345:345:345)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIOWrite\~3) + (DELAY + (ABSOLUTE + (PORT datab (1524:1524:1524) (1641:1641:1641)) + (PORT datac (995:995:995) (1081:1081:1081)) + (PORT datad (655:655:655) (722:722:722)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIOWrite\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1038:1038:1038) (1076:1076:1076)) + (PORT datab (663:663:663) (710:710:710)) + (PORT datac (174:174:174) (208:208:208)) + (PORT datad (1064:1064:1064) (1054:1054:1054)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIOWrite\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1282:1282:1282) (1318:1318:1318)) + (PORT datab (1147:1147:1147) (1226:1226:1226)) + (PORT datac (850:850:850) (883:883:883)) + (PORT datad (1534:1534:1534) (1603:1603:1603)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIOWrite\~5) + (DELAY + (ABSOLUTE + (PORT dataa (998:998:998) (1057:1057:1057)) + (PORT datab (200:200:200) (239:239:239)) + (PORT datac (581:581:581) (624:624:624)) + (PORT datad (180:180:180) (208:208:208)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1510:1510:1510) (1571:1571:1571)) + (PORT datab (900:900:900) (924:924:924)) + (PORT datac (669:669:669) (712:712:712)) + (PORT datad (342:342:342) (372:372:372)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~12) + (DELAY + (ABSOLUTE + (PORT dataa (718:718:718) (781:781:781)) + (PORT datab (628:628:628) (691:691:691)) + (PORT datac (598:598:598) (632:632:632)) + (PORT datad (348:348:348) (371:371:371)) + (IOPATH dataa combout (337:337:337) (338:338:338)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -29245,32 +28194,231 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~2) + (INSTANCE z80_\|execute_\|ctl_mWrite\~13) (DELAY (ABSOLUTE - (PORT dataa (1253:1253:1253) (1311:1311:1311)) - (PORT datab (870:870:870) (881:881:881)) - (PORT datac (1299:1299:1299) (1298:1298:1298)) - (PORT datad (625:625:625) (681:681:681)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) + (PORT dataa (1200:1200:1200) (1223:1223:1223)) + (PORT datab (595:595:595) (608:608:608)) + (PORT datac (613:613:613) (635:635:635)) + (PORT datad (953:953:953) (996:996:996)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~14) + (DELAY + (ABSOLUTE + (PORT dataa (609:609:609) (626:626:626)) + (PORT datab (641:641:641) (671:671:671)) + (PORT datac (171:171:171) (205:205:205)) + (PORT datad (630:630:630) (667:667:667)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~16) + (DELAY + (ABSOLUTE + (PORT dataa (862:862:862) (907:907:907)) + (PORT datab (850:850:850) (904:904:904)) + (PORT datac (1001:1001:1001) (1039:1039:1039)) + (PORT datad (915:915:915) (962:962:962)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (304:304:304) (308:308:308)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|DFFE_mwr_ff1) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1550:1550:1550)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1578:1578:1578) (1557:1557:1557)) + (PORT ena (1463:1463:1463) (1456:1456:1456)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|wait_mwr\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (219:219:219) (288:288:288)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|wait_mwr) + (DELAY + (ABSOLUTE + (PORT clk (1541:1541:1541) (1540:1540:1540)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1578:1578:1578) (1557:1557:1557)) + (PORT ena (1434:1434:1434) (1415:1415:1415)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|mwr_wr) + (DELAY + (ABSOLUTE + (PORT clk (1541:1541:1541) (1540:1540:1540)) + (PORT asdata (567:567:567) (646:646:646)) + (PORT clrn (1578:1578:1578) (1557:1557:1557)) + (PORT ena (1434:1434:1434) (1415:1415:1415)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|nWR_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (656:656:656) (680:680:680)) + (PORT datab (221:221:221) (260:260:260)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal2\~1) + (DELAY + (ABSOLUTE + (PORT datab (2798:2798:2798) (2990:2990:2990)) + (PORT datac (551:551:551) (572:572:572)) + (PORT datad (605:605:605) (624:624:624)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1274:1274:1274) (1333:1333:1333)) + (PORT datab (1518:1518:1518) (1582:1582:1582)) + (PORT datac (1806:1806:1806) (1891:1891:1891)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~4) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (265:265:265)) + (PORT datab (1176:1176:1176) (1239:1239:1239)) + (PORT datac (1171:1171:1171) (1216:1216:1216)) + (PORT datad (885:885:885) (932:932:932)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2087:2087:2087) (2180:2180:2180)) + (PORT datac (1567:1567:1567) (1702:1702:1702)) + (PORT datad (1512:1512:1512) (1607:1607:1607)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1232:1232:1232) (1278:1278:1278)) + (PORT datab (204:204:204) (246:246:246)) + (PORT datac (1687:1687:1687) (1766:1766:1766)) + (PORT datad (1285:1285:1285) (1324:1324:1324)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~3) (DELAY (ABSOLUTE - (PORT dataa (198:198:198) (242:242:242)) - (PORT datab (1100:1100:1100) (1104:1104:1104)) - (PORT datac (369:369:369) (395:395:395)) - (PORT datad (1798:1798:1798) (1887:1887:1887)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (345:345:345) (375:375:375)) + (PORT datab (901:901:901) (982:982:982)) + (PORT datac (606:606:606) (625:625:625)) + (PORT datad (1750:1750:1750) (1772:1772:1772)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~8) + (DELAY + (ABSOLUTE + (PORT dataa (964:964:964) (1050:1050:1050)) + (PORT datab (1272:1272:1272) (1308:1308:1308)) + (PORT datac (1058:1058:1058) (1063:1063:1063)) + (PORT datad (1189:1189:1189) (1207:1207:1207)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -29280,74 +28428,28 @@ (INSTANCE z80_\|execute_\|fMWrite\~7) (DELAY (ABSOLUTE - (PORT datab (916:916:916) (964:964:964)) - (PORT datac (850:850:850) (896:896:896)) - (PORT datad (781:781:781) (791:791:791)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (913:913:913) (975:975:975)) + (PORT datab (1052:1052:1052) (1084:1084:1084)) + (PORT datac (1145:1145:1145) (1210:1210:1210)) + (PORT datad (1125:1125:1125) (1136:1136:1136)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~4) + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~16) (DELAY (ABSOLUTE - (PORT dataa (1515:1515:1515) (1583:1583:1583)) - (PORT datab (200:200:200) (239:239:239)) - (PORT datac (1714:1714:1714) (1760:1760:1760)) - (PORT datad (881:881:881) (920:920:920)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1447:1447:1447) (1506:1506:1506)) - (PORT datab (1169:1169:1169) (1174:1174:1174)) - (PORT datac (894:894:894) (923:923:923)) - (PORT datad (781:781:781) (794:794:794)) + (PORT dataa (615:615:615) (682:682:682)) + (PORT datab (1168:1168:1168) (1211:1211:1211)) + (PORT datac (1681:1681:1681) (1773:1773:1773)) + (PORT datad (2059:2059:2059) (2140:2140:2140)) (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1513:1513:1513) (1581:1581:1581)) - (PORT datab (1150:1150:1150) (1204:1204:1204)) - (PORT datac (1094:1094:1094) (1111:1111:1111)) - (PORT datad (616:616:616) (634:634:634)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1253:1253:1253) (1361:1361:1361)) - (PORT datab (869:869:869) (894:894:894)) - (PORT datac (1706:1706:1706) (1761:1761:1761)) - (PORT datad (263:263:263) (315:315:315)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -29358,13 +28460,29 @@ (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~8) (DELAY (ABSOLUTE - (PORT dataa (1146:1146:1146) (1188:1188:1188)) - (PORT datab (214:214:214) (258:258:258)) - (PORT datac (192:192:192) (225:225:225)) - (PORT datad (621:621:621) (651:651:651)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (1324:1324:1324) (1371:1371:1371)) + (PORT datab (646:646:646) (678:678:678)) + (PORT datac (1703:1703:1703) (1791:1791:1791)) + (PORT datad (1158:1158:1158) (1211:1211:1211)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1015:1015:1015) (1130:1130:1130)) + (PORT datab (1047:1047:1047) (1185:1185:1185)) + (PORT datac (699:699:699) (763:763:763)) + (PORT datad (1149:1149:1149) (1171:1171:1171)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -29374,26 +28492,12 @@ (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~9) (DELAY (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (222:222:222) (261:261:261)) - (PORT datac (1051:1051:1051) (1068:1068:1068)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1101:1101:1101) (1104:1104:1104)) - (PORT datab (879:879:879) (888:888:888)) - (PORT datac (609:609:609) (624:624:624)) - (PORT datad (1198:1198:1198) (1221:1221:1221)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) + (PORT dataa (656:656:656) (682:682:682)) + (PORT datab (926:926:926) (943:943:943)) + (PORT datac (919:919:919) (950:950:950)) + (PORT datad (181:181:181) (210:210:210)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -29401,15 +28505,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~5) + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~7) (DELAY (ABSOLUTE - (PORT dataa (901:901:901) (927:927:927)) - (PORT datab (206:206:206) (246:246:246)) - (PORT datac (583:583:583) (601:601:601)) - (PORT datad (197:197:197) (223:223:223)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) + (PORT dataa (1685:1685:1685) (1721:1721:1721)) + (PORT datab (644:644:644) (666:666:666)) + (PORT datac (1247:1247:1247) (1297:1297:1297)) + (PORT datad (944:944:944) (994:994:994)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -29421,9 +28525,9 @@ (DELAY (ABSOLUTE (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (199:199:199) (239:239:239)) - (PORT datac (332:332:332) (351:351:351)) - (PORT datad (813:813:813) (840:840:840)) + (PORT datab (198:198:198) (238:238:238)) + (PORT datac (171:171:171) (205:205:205)) + (PORT datad (174:174:174) (200:200:200)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -29433,31 +28537,45 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~10) + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~11) (DELAY (ABSOLUTE - (PORT dataa (881:881:881) (906:906:906)) - (PORT datab (1043:1043:1043) (1098:1098:1098)) - (PORT datac (1093:1093:1093) (1111:1111:1111)) - (PORT datad (1130:1130:1130) (1132:1132:1132)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (1135:1135:1135) (1136:1136:1136)) + (PORT datab (613:613:613) (639:639:639)) + (PORT datac (1433:1433:1433) (1447:1447:1447)) + (PORT datad (607:607:607) (657:657:657)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~11) + (INSTANCE z80_\|execute_\|fMWrite\~5) (DELAY (ABSOLUTE - (PORT dataa (202:202:202) (247:247:247)) - (PORT datab (199:199:199) (239:239:239)) - (PORT datac (173:173:173) (206:206:206)) - (PORT datad (181:181:181) (210:210:210)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) + (PORT dataa (1525:1525:1525) (1584:1584:1584)) + (PORT datab (1242:1242:1242) (1306:1306:1306)) + (PORT datac (901:901:901) (949:949:949)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~6) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (209:209:209) (252:252:252)) + (PORT datac (1251:1251:1251) (1315:1315:1315)) + (PORT datad (1976:1976:1976) (2069:2069:2069)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -29468,29 +28586,61 @@ (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~12) (DELAY (ABSOLUTE - (PORT dataa (572:572:572) (605:605:605)) - (PORT datab (1113:1113:1113) (1136:1136:1136)) - (PORT datac (1714:1714:1714) (1760:1760:1760)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (333:333:333) (332:332:332)) + (PORT dataa (676:676:676) (728:728:728)) + (PORT datab (638:638:638) (697:697:697)) + (PORT datac (907:907:907) (942:942:942)) + (PORT datad (171:171:171) (196:196:196)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~4) + (DELAY + (ABSOLUTE + (PORT dataa (403:403:403) (428:428:428)) + (PORT datab (1485:1485:1485) (1511:1511:1511)) + (PORT datac (652:652:652) (695:695:695)) + (PORT datad (1507:1507:1507) (1573:1573:1573)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1795:1795:1795) (1871:1871:1871)) + (PORT datab (1177:1177:1177) (1242:1242:1242)) + (PORT datac (607:607:607) (643:643:643)) + (PORT datad (854:854:854) (884:884:884)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~13) (DELAY (ABSOLUTE - (PORT dataa (675:675:675) (726:726:726)) - (PORT datab (198:198:198) (236:236:236)) - (PORT datac (612:612:612) (639:639:639)) - (PORT datad (196:196:196) (220:220:220)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (198:198:198) (241:241:241)) + (PORT datab (972:972:972) (1020:1020:1020)) + (PORT datac (1248:1248:1248) (1305:1305:1305)) + (PORT datad (1976:1976:1976) (2070:2070:2070)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -29500,23 +28650,51 @@ (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~14) (DELAY (ABSOLUTE - (PORT dataa (198:198:198) (241:241:241)) - (PORT datab (930:930:930) (979:979:979)) - (PORT datac (1054:1054:1054) (1167:1167:1167)) - (PORT datad (1137:1137:1137) (1183:1183:1183)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (598:598:598) (646:646:646)) + (PORT datab (938:938:938) (995:995:995)) + (PORT datac (592:592:592) (636:636:636)) + (PORT datad (594:594:594) (607:607:607)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~2) + (DELAY + (ABSOLUTE + (PORT datab (1021:1021:1021) (1085:1085:1085)) + (PORT datad (951:951:951) (1011:1011:1011)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1357:1357:1357) (1373:1373:1373)) + (PORT datab (344:344:344) (377:377:377)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (652:652:652) (719:719:719)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|clk_delay_\|DFF_inst5\~feeder) (DELAY (ABSOLUTE - (PORT datad (225:225:225) (296:296:296)) + (PORT datad (1320:1320:1320) (1382:1382:1382)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -29526,9 +28704,9 @@ (INSTANCE z80_\|clk_delay_\|DFF_inst5) (DELAY (ABSOLUTE - (PORT clk (1528:1528:1528) (1547:1547:1547)) + (PORT clk (1520:1520:1520) (1539:1539:1539)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1587:1587:1587) (1563:1563:1563)) + (PORT clrn (1566:1566:1566) (1545:1545:1545)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -29537,30 +28715,20 @@ (HOLD d (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|wait_iorqinta\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (228:228:228) (301:301:301)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|memory_ifc_\|wait_iorqinta) (DELAY (ABSOLUTE - (PORT clk (1538:1538:1538) (1537:1537:1537)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1587:1587:1587) (1563:1563:1563)) + (PORT clk (1541:1541:1541) (1539:1539:1539)) + (PORT asdata (1496:1496:1496) (1564:1564:1564)) + (PORT clrn (1577:1577:1577) (1556:1556:1556)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) ) ) (CELL @@ -29568,9 +28736,9 @@ (INSTANCE z80_\|memory_ifc_\|DFFE_intr_ff3) (DELAY (ABSOLUTE - (PORT clk (1528:1528:1528) (1547:1547:1547)) - (PORT asdata (568:568:568) (647:647:647)) - (PORT clrn (1587:1587:1587) (1563:1563:1563)) + (PORT clk (1530:1530:1530) (1550:1550:1550)) + (PORT asdata (567:567:567) (644:644:644)) + (PORT clrn (1577:1577:1577) (1556:1556:1556)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -29584,11 +28752,11 @@ (INSTANCE z80_\|memory_ifc_\|nIORQ_out\~0) (DELAY (ABSOLUTE - (PORT dataa (253:253:253) (342:342:342)) - (PORT datad (605:605:605) (631:631:631)) - (IOPATH dataa combout (354:354:354) (367:367:367)) + (PORT dataa (562:562:562) (579:579:579)) + (PORT datab (250:250:250) (334:334:334)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -29597,28 +28765,12 @@ (INSTANCE Equal2\~0) (DELAY (ABSOLUTE - (PORT dataa (1750:1750:1750) (1853:1853:1853)) - (PORT datab (1593:1593:1593) (1734:1734:1734)) - (PORT datac (1199:1199:1199) (1264:1264:1264)) - (PORT datad (1222:1222:1222) (1307:1307:1307)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ExtRamWE\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1747:1747:1747) (1852:1852:1852)) - (PORT datab (1597:1597:1597) (1730:1730:1730)) - (PORT datac (1200:1200:1200) (1265:1265:1265)) - (PORT datad (1220:1220:1220) (1307:1307:1307)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT dataa (245:245:245) (300:300:300)) + (PORT datab (2799:2799:2799) (2989:2989:2989)) + (PORT datac (549:549:549) (569:569:569)) + (PORT datad (605:605:605) (620:620:620)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -29626,12 +28778,26 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[13\]\~13) + (INSTANCE z80_\|execute_\|ctl_apin_mux\~2) (DELAY (ABSOLUTE - (PORT dataa (1796:1796:1796) (1810:1810:1810)) - (PORT datab (849:849:849) (873:873:873)) - (PORT datad (335:335:335) (353:353:353)) + (PORT dataa (873:873:873) (893:893:893)) + (PORT datac (1481:1481:1481) (1512:1512:1512)) + (PORT datad (852:852:852) (904:904:904)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[10\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1433:1433:1433) (1480:1480:1480)) + (PORT datab (535:535:535) (553:553:553)) + (PORT datad (317:317:317) (337:337:337)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -29643,651 +28809,55 @@ (INSTANCE z80_\|execute_\|ctl_apin_mux2\~0) (DELAY (ABSOLUTE - (PORT dataa (949:949:949) (1028:1028:1028)) - (PORT datab (994:994:994) (1080:1080:1080)) - (PORT datac (1875:1875:1875) (2047:2047:2047)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) + (PORT dataa (1979:1979:1979) (2093:2093:2093)) + (PORT datab (1651:1651:1651) (1771:1771:1771)) + (PORT datac (1461:1461:1461) (1587:1587:1587)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (342:342:342) (318:318:318)) (IOPATH datac combout (241:241:241) (241:241:241)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_ab_pin_we\~2) + (INSTANCE z80_\|pin_control_\|bus_ab_pin_we\~0) (DELAY (ABSOLUTE - (PORT dataa (1686:1686:1686) (1827:1827:1827)) - (PORT datab (974:974:974) (1024:1024:1024)) - (PORT datac (941:941:941) (1003:1003:1003)) - (PORT datad (1201:1201:1201) (1259:1259:1259)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_ab_pin_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (948:948:948) (1027:1027:1027)) - (PORT datab (994:994:994) (1080:1080:1080)) - (PORT datac (1875:1875:1875) (2047:2047:2047)) - (PORT datad (622:622:622) (660:660:660)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[13\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1534:1534:1534)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (603:603:603) (689:689:689)) - (PORT sload (1125:1125:1125) (1169:1169:1169)) - (PORT ena (1155:1155:1155) (1129:1129:1129)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[13\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (1195:1195:1195) (1254:1254:1254)) - (PORT datad (2019:2019:2019) (2140:2140:2140)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[14\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1794:1794:1794) (1807:1807:1807)) - (PORT datab (219:219:219) (257:257:257)) - (PORT datad (320:320:320) (334:334:334)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[14\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1534:1534:1534)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (590:590:590) (668:668:668)) - (PORT sload (1125:1125:1125) (1169:1169:1169)) - (PORT ena (1155:1155:1155) (1129:1129:1129)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[14\]\~23) - (DELAY - (ABSOLUTE - (PORT datab (2045:2045:2045) (2178:2178:2178)) - (PORT datad (1147:1147:1147) (1202:1202:1202)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[15\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1796:1796:1796) (1810:1810:1810)) - (PORT datab (337:337:337) (371:371:371)) - (PORT datad (554:554:554) (561:561:561)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[15\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1534:1534:1534)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (577:577:577) (658:658:658)) - (PORT sload (1125:1125:1125) (1169:1169:1169)) - (PORT ena (1155:1155:1155) (1129:1129:1129)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[15\]\~22) - (DELAY - (ABSOLUTE - (PORT datab (1641:1641:1641) (1729:1729:1729)) - (PORT datac (1584:1584:1584) (1634:1634:1634)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode236w\[2\]) - (DELAY - (ABSOLUTE - (PORT dataa (697:697:697) (725:725:725)) - (PORT datab (261:261:261) (314:314:314)) - (PORT datac (366:366:366) (404:404:404)) - (PORT datad (1304:1304:1304) (1296:1296:1296)) - (IOPATH dataa combout (300:300:300) (308:308:308)) + (PORT dataa (991:991:991) (1078:1078:1078)) + (PORT datab (228:228:228) (269:269:269)) + (PORT datad (1333:1333:1333) (1330:1330:1330)) + (IOPATH dataa combout (301:301:301) (307:307:307)) (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|rden_decode\|w_anode284w\[2\]\~0) + (INSTANCE z80_\|pin_control_\|bus_ab_pin_we\~1) (DELAY (ABSOLUTE - (PORT datab (2037:2037:2037) (2174:2174:2174)) - (PORT datac (1153:1153:1153) (1208:1208:1208)) - (PORT datad (1144:1144:1144) (1203:1203:1203)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[0\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (911:911:911) (971:971:971)) - (PORT datad (1987:1987:1987) (2083:2083:2083)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[1\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (854:854:854) (879:879:879)) - (PORT datab (373:373:373) (396:396:396)) - (PORT datad (334:334:334) (343:343:343)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1548:1548:1548) (1550:1550:1550)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (1128:1128:1128) (1174:1174:1174)) - (PORT sload (1213:1213:1213) (1283:1283:1283)) - (PORT ena (1456:1456:1456) (1440:1440:1440)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[1\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (1793:1793:1793) (1909:1909:1909)) - (PORT datad (678:678:678) (733:733:733)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[2\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (855:855:855) (880:880:880)) - (PORT datab (604:604:604) (620:620:620)) - (PORT datad (532:532:532) (544:544:544)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1548:1548:1548) (1550:1550:1550)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (992:992:992) (1045:1045:1045)) - (PORT sload (1213:1213:1213) (1283:1283:1283)) - (PORT ena (1456:1456:1456) (1440:1440:1440)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[2\]\~26) - (DELAY - (ABSOLUTE - (PORT datac (1749:1749:1749) (1862:1862:1862)) - (PORT datad (642:642:642) (699:699:699)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[3\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (858:858:858) (887:887:887)) - (PORT datab (535:535:535) (551:551:551)) - (PORT datad (339:339:339) (355:355:355)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1548:1548:1548) (1550:1550:1550)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (751:751:751) (807:807:807)) - (PORT sload (1213:1213:1213) (1283:1283:1283)) - (PORT ena (1456:1456:1456) (1440:1440:1440)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[3\]\~27) - (DELAY - (ABSOLUTE - (PORT datac (1754:1754:1754) (1872:1872:1872)) - (PORT datad (367:367:367) (429:429:429)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[4\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (853:853:853) (880:880:880)) - (PORT datab (534:534:534) (559:559:559)) - (PORT datad (339:339:339) (357:357:357)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1548:1548:1548) (1550:1550:1550)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (979:979:979) (1031:1031:1031)) - (PORT sload (1213:1213:1213) (1283:1283:1283)) - (PORT ena (1456:1456:1456) (1440:1440:1440)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[4\]\~28) - (DELAY - (ABSOLUTE - (PORT datac (1758:1758:1758) (1874:1874:1874)) - (PORT datad (652:652:652) (710:710:710)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[5\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1351:1351:1351) (1385:1385:1385)) - (PORT datab (337:337:337) (371:371:371)) - (PORT datad (196:196:196) (222:222:222)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1533:1533:1533)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (1019:1019:1019) (1078:1078:1078)) - (PORT sload (1150:1150:1150) (1218:1218:1218)) - (PORT ena (1176:1176:1176) (1166:1166:1166)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[5\]\~29) - (DELAY - (ABSOLUTE - (PORT datab (2021:2021:2021) (2124:2124:2124)) - (PORT datac (676:676:676) (743:743:743)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[6\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (221:221:221) (260:260:260)) - (PORT datad (1323:1323:1323) (1343:1343:1343)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1533:1533:1533)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (1156:1156:1156) (1209:1209:1209)) - (PORT sload (1150:1150:1150) (1218:1218:1218)) - (PORT ena (1176:1176:1176) (1166:1166:1166)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[6\]\~30) - (DELAY - (ABSOLUTE - (PORT datab (696:696:696) (759:759:759)) - (PORT datac (1750:1750:1750) (1863:1863:1863)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[7\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1354:1354:1354) (1387:1387:1387)) - (PORT datab (199:199:199) (239:239:239)) - (PORT datad (194:194:194) (219:219:219)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1533:1533:1533)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (1639:1639:1639) (1657:1657:1657)) - (PORT sload (1150:1150:1150) (1218:1218:1218)) - (PORT ena (1176:1176:1176) (1166:1166:1166)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[7\]\~31) - (DELAY - (ABSOLUTE - (PORT datac (1748:1748:1748) (1867:1867:1867)) - (PORT datad (927:927:927) (1010:1010:1010)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[8\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (342:342:342) (380:380:380)) - (PORT datab (1361:1361:1361) (1369:1369:1369)) - (PORT datad (196:196:196) (222:222:222)) + (PORT dataa (1078:1078:1078) (1090:1090:1090)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (1490:1490:1490) (1609:1609:1609)) + (PORT datad (873:873:873) (922:922:922)) (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[8\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1533:1533:1533)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (597:597:597) (678:678:678)) - (PORT sload (1150:1150:1150) (1218:1218:1218)) - (PORT ena (1176:1176:1176) (1166:1166:1166)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[8\]\~18) - (DELAY - (ABSOLUTE - (PORT datab (948:948:948) (1009:1009:1009)) - (PORT datad (2008:2008:2008) (2130:2130:2130)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[9\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1391:1391:1391) (1422:1422:1422)) - (PORT datab (220:220:220) (259:259:259)) - (PORT datad (552:552:552) (561:561:561)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[9\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1533:1533:1533)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (591:591:591) (677:677:677)) - (PORT sload (1117:1117:1117) (1168:1168:1168)) - (PORT ena (811:811:811) (804:804:804)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[9\]\~17) - (DELAY - (ABSOLUTE - (PORT datac (1757:1757:1757) (1868:1868:1868)) - (PORT datad (678:678:678) (737:737:737)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[10\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (264:264:264)) - (PORT datab (567:567:567) (585:585:585)) - (PORT datad (1365:1365:1365) (1379:1379:1379)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[10\]) (DELAY (ABSOLUTE - (PORT clk (1528:1528:1528) (1533:1533:1533)) + (PORT clk (1523:1523:1523) (1527:1527:1527)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (580:580:580) (668:668:668)) - (PORT sload (1117:1117:1117) (1168:1168:1168)) - (PORT ena (811:811:811) (804:804:804)) + (PORT asdata (581:581:581) (655:655:655)) + (PORT sload (2032:2032:2032) (2084:2084:2084)) + (PORT ena (2298:2298:2298) (2265:2265:2265)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -30298,5778 +28868,6 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[10\]\~24) - (DELAY - (ABSOLUTE - (PORT datac (910:910:910) (972:972:972)) - (PORT datad (1442:1442:1442) (1565:1565:1565)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[11\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (264:264:264)) - (PORT datab (197:197:197) (234:234:234)) - (PORT datad (1362:1362:1362) (1374:1374:1374)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[11\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1533:1533:1533)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (913:913:913) (972:972:972)) - (PORT sload (1117:1117:1117) (1168:1168:1168)) - (PORT ena (811:811:811) (804:804:804)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[11\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (942:942:942) (1010:1010:1010)) - (PORT datad (1442:1442:1442) (1566:1566:1566)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[12\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (340:340:340) (375:375:375)) - (PORT datab (816:816:816) (834:834:834)) - (PORT datad (1561:1561:1561) (1571:1571:1571)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[12\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1534:1534:1534)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (583:583:583) (667:667:667)) - (PORT sload (1125:1125:1125) (1169:1169:1169)) - (PORT ena (1155:1155:1155) (1129:1129:1129)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[12\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1791:1791:1791) (1903:1903:1903)) - (PORT datad (854:854:854) (913:913:913)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1010:1010:1010) (1062:1062:1062)) - (PORT clk (1856:1856:1856) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1009:1009:1009) (1047:1047:1047)) - (PORT d[1] (2076:2076:2076) (2305:2305:2305)) - (PORT d[2] (1463:1463:1463) (1514:1514:1514)) - (PORT d[3] (2867:2867:2867) (3072:3072:3072)) - (PORT d[4] (2625:2625:2625) (2841:2841:2841)) - (PORT d[5] (3152:3152:3152) (3353:3353:3353)) - (PORT d[6] (1368:1368:1368) (1453:1453:1453)) - (PORT d[7] (2906:2906:2906) (3079:3079:3079)) - (PORT d[8] (997:997:997) (1014:1014:1014)) - (PORT d[9] (1597:1597:1597) (1654:1654:1654)) - (PORT d[10] (1607:1607:1607) (1695:1695:1695)) - (PORT d[11] (2235:2235:2235) (2380:2380:2380)) - (PORT d[12] (1610:1610:1610) (1712:1712:1712)) - (PORT clk (1853:1853:1853) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (958:958:958) (934:934:934)) - (PORT clk (1853:1853:1853) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1883:1883:1883)) - (PORT d[0] (1472:1472:1472) (1458:1458:1458)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1816:1816:1816) (1842:1842:1842)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1001:1001:1001) (1005:1005:1005)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1002:1002:1002) (1006:1006:1006)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1002:1002:1002) (1006:1006:1006)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1002:1002:1002) (1006:1006:1006)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1896:1896:1896) (1918:1918:1918)) - (PORT asdata (2035:2035:2035) (2085:2085:2085)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1543:1543:1543)) - (PORT asdata (1451:1451:1451) (1488:1488:1488)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode223w\[2\]) - (DELAY - (ABSOLUTE - (PORT dataa (697:697:697) (725:725:725)) - (PORT datab (262:262:262) (316:316:316)) - (PORT datac (367:367:367) (405:405:405)) - (PORT datad (1303:1303:1303) (1300:1300:1300)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode223w\[2\]\~0) - (DELAY - (ABSOLUTE - (PORT datab (2042:2042:2042) (2178:2178:2178)) - (PORT datac (1154:1154:1154) (1211:1211:1211)) - (PORT datad (1145:1145:1145) (1206:1206:1206)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (991:991:991) (1045:1045:1045)) - (PORT clk (1854:1854:1854) (1881:1881:1881)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1010:1010:1010) (1048:1048:1048)) - (PORT d[1] (2092:2092:2092) (2316:2316:2316)) - (PORT d[2] (3345:3345:3345) (3458:3458:3458)) - (PORT d[3] (2859:2859:2859) (3062:3062:3062)) - (PORT d[4] (2566:2566:2566) (2775:2775:2775)) - (PORT d[5] (3169:3169:3169) (3393:3393:3393)) - (PORT d[6] (1618:1618:1618) (1695:1695:1695)) - (PORT d[7] (2898:2898:2898) (3057:3057:3057)) - (PORT d[8] (1024:1024:1024) (1046:1046:1046)) - (PORT d[9] (3241:3241:3241) (3372:3372:3372)) - (PORT d[10] (1642:1642:1642) (1735:1735:1735)) - (PORT d[11] (1916:1916:1916) (2070:2070:2070)) - (PORT d[12] (1870:1870:1870) (1971:1971:1971)) - (PORT clk (1851:1851:1851) (1877:1877:1877)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (950:950:950) (925:925:925)) - (PORT clk (1851:1851:1851) (1877:1877:1877)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1854:1854:1854) (1881:1881:1881)) - (PORT d[0] (1713:1713:1713) (1683:1683:1683)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1855:1855:1855) (1882:1882:1882)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1855:1855:1855) (1882:1882:1882)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1855:1855:1855) (1882:1882:1882)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1855:1855:1855) (1882:1882:1882)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1814:1814:1814) (1840:1840:1840)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (999:999:999) (1003:1003:1003)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1000:1000:1000) (1004:1004:1004)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1000:1000:1000) (1004:1004:1004)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1000:1000:1000) (1004:1004:1004)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) - (PORT asdata (1470:1470:1470) (1518:1518:1518)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) - (PORT asdata (706:706:706) (770:770:770)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode244w\[2\]) - (DELAY - (ABSOLUTE - (PORT dataa (700:700:700) (726:726:726)) - (PORT datab (266:266:266) (319:319:319)) - (PORT datac (371:371:371) (404:404:404)) - (PORT datad (1304:1304:1304) (1295:1295:1295)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode244w\[2\]\~0) - (DELAY - (ABSOLUTE - (PORT datab (2038:2038:2038) (2171:2171:2171)) - (PORT datac (1153:1153:1153) (1206:1206:1206)) - (PORT datad (1143:1143:1143) (1202:1202:1202)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1184:1184:1184) (1228:1228:1228)) - (PORT clk (1845:1845:1845) (1873:1873:1873)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3973:3973:3973) (4187:4187:4187)) - (PORT d[1] (1695:1695:1695) (1858:1858:1858)) - (PORT d[2] (3329:3329:3329) (3462:3462:3462)) - (PORT d[3] (2153:2153:2153) (2276:2276:2276)) - (PORT d[4] (2142:2142:2142) (2252:2252:2252)) - (PORT d[5] (1659:1659:1659) (1777:1777:1777)) - (PORT d[6] (1754:1754:1754) (1804:1804:1804)) - (PORT d[7] (3063:3063:3063) (3210:3210:3210)) - (PORT d[8] (3317:3317:3317) (3546:3546:3546)) - (PORT d[9] (1753:1753:1753) (1814:1814:1814)) - (PORT d[10] (3216:3216:3216) (3426:3426:3426)) - (PORT d[11] (2090:2090:2090) (2212:2212:2212)) - (PORT d[12] (1771:1771:1771) (1834:1834:1834)) - (PORT clk (1842:1842:1842) (1869:1869:1869)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2235:2235:2235) (2268:2268:2268)) - (PORT clk (1842:1842:1842) (1869:1869:1869)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1845:1845:1845) (1873:1873:1873)) - (PORT d[0] (2962:2962:2962) (3024:3024:3024)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1846:1846:1846) (1874:1874:1874)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1846:1846:1846) (1874:1874:1874)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1846:1846:1846) (1874:1874:1874)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1846:1846:1846) (1874:1874:1874)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1805:1805:1805) (1832:1832:1832)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (990:990:990) (995:995:995)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (991:991:991) (996:996:996)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (991:991:991) (996:996:996)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (991:991:991) (996:996:996)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~90) - (DELAY - (ABSOLUTE - (PORT dataa (602:602:602) (616:616:616)) - (PORT datab (976:976:976) (1039:1039:1039)) - (PORT datac (828:828:828) (832:832:832)) - (PORT datad (1142:1142:1142) (1222:1222:1222)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode252w\[2\]) - (DELAY - (ABSOLUTE - (PORT dataa (700:700:700) (731:731:731)) - (PORT datab (265:265:265) (319:319:319)) - (PORT datac (371:371:371) (408:408:408)) - (PORT datad (1303:1303:1303) (1299:1299:1299)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode252w\[2\]\~0) - (DELAY - (ABSOLUTE - (PORT datab (2046:2046:2046) (2179:2179:2179)) - (PORT datac (1157:1157:1157) (1209:1209:1209)) - (PORT datad (1148:1148:1148) (1203:1203:1203)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1196:1196:1196) (1209:1209:1209)) - (PORT clk (1854:1854:1854) (1881:1881:1881)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4200:4200:4200) (4456:4456:4456)) - (PORT d[1] (2340:2340:2340) (2537:2537:2537)) - (PORT d[2] (3231:3231:3231) (3326:3326:3326)) - (PORT d[3] (2575:2575:2575) (2761:2761:2761)) - (PORT d[4] (2559:2559:2559) (2766:2766:2766)) - (PORT d[5] (2828:2828:2828) (3008:3008:3008)) - (PORT d[6] (1911:1911:1911) (2053:2053:2053)) - (PORT d[7] (2601:2601:2601) (2739:2739:2739)) - (PORT d[8] (3332:3332:3332) (3618:3618:3618)) - (PORT d[9] (2924:2924:2924) (3075:3075:3075)) - (PORT d[10] (5088:5088:5088) (5359:5359:5359)) - (PORT d[11] (1899:1899:1899) (2034:2034:2034)) - (PORT d[12] (2169:2169:2169) (2292:2292:2292)) - (PORT clk (1851:1851:1851) (1877:1877:1877)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2009:2009:2009) (1965:1965:1965)) - (PORT clk (1851:1851:1851) (1877:1877:1877)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1854:1854:1854) (1881:1881:1881)) - (PORT d[0] (2224:2224:2224) (2198:2198:2198)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1855:1855:1855) (1882:1882:1882)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1855:1855:1855) (1882:1882:1882)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1855:1855:1855) (1882:1882:1882)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1855:1855:1855) (1882:1882:1882)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1814:1814:1814) (1840:1840:1840)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (999:999:999) (1003:1003:1003)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1000:1000:1000) (1004:1004:1004)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1000:1000:1000) (1004:1004:1004)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1000:1000:1000) (1004:1004:1004)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~91) - (DELAY - (ABSOLUTE - (PORT dataa (837:837:837) (859:859:859)) - (PORT datab (1432:1432:1432) (1519:1519:1519)) - (PORT datac (318:318:318) (339:339:339)) - (PORT datad (1100:1100:1100) (1101:1101:1101)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|decode2\|eq_node\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (698:698:698) (723:723:723)) - (PORT datab (257:257:257) (310:310:310)) - (PORT datac (364:364:364) (402:402:402)) - (PORT datad (1304:1304:1304) (1295:1295:1295)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_clkctrl") - (INSTANCE CLOCK_50\~inputclkctrl) - (DELAY - (ABSOLUTE - (PORT inclk[0] (154:154:154) (138:138:138)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vram_address\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1044:1044:1044) (1098:1098:1098)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vram_address\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1253:1253:1253) (1340:1340:1340)) - (PORT datab (987:987:987) (1065:1065:1065)) - (PORT datac (971:971:971) (1042:1042:1042)) - (PORT datad (277:277:277) (361:361:361)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1539:1539:1539) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1216:1216:1216) (1194:1194:1194)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1539:1539:1539) (1551:1551:1551)) - (PORT asdata (1205:1205:1205) (1280:1280:1280)) - (PORT ena (1216:1216:1216) (1194:1194:1194)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vram_address\[2\]\~4) - (DELAY - (ABSOLUTE - (PORT datac (896:896:896) (972:972:972)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1539:1539:1539) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1216:1216:1216) (1194:1194:1194)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add3\~0) - (DELAY - (ABSOLUTE - (PORT datac (891:891:891) (968:968:968)) - (PORT datad (1442:1442:1442) (1493:1493:1493)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1539:1539:1539) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1216:1216:1216) (1194:1194:1194)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add3\~1) - (DELAY - (ABSOLUTE - (PORT dataa (929:929:929) (1008:1008:1008)) - (PORT datac (1383:1383:1383) (1458:1458:1458)) - (PORT datad (1442:1442:1442) (1493:1493:1493)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1539:1539:1539) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1216:1216:1216) (1194:1194:1194)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (697:697:697) (779:779:779)) - (PORT datab (721:721:721) (803:803:803)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH dataa cout (436:436:436) (315:315:315)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datab cout (446:446:446) (318:318:318)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~2) - (DELAY - (ABSOLUTE - (PORT datab (644:644:644) (722:722:722)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datab cout (446:446:446) (318:318:318)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~4) - (DELAY - (ABSOLUTE - (PORT datab (706:706:706) (772:772:772)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datab cout (446:446:446) (318:318:318)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~6) - (DELAY - (ABSOLUTE - (PORT datab (682:682:682) (766:766:766)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datab cout (446:446:446) (318:318:318)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1539:1539:1539) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1216:1216:1216) (1194:1194:1194)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~8) - (DELAY - (ABSOLUTE - (PORT dataa (700:700:700) (788:788:788)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH dataa cout (436:436:436) (315:315:315)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1539:1539:1539) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1216:1216:1216) (1194:1194:1194)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~10) - (DELAY - (ABSOLUTE - (PORT dataa (980:980:980) (1052:1052:1052)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH dataa cout (436:436:436) (315:315:315)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1539:1539:1539) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1216:1216:1216) (1194:1194:1194)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~12) - (DELAY - (ABSOLUTE - (PORT datab (694:694:694) (766:766:766)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datab cout (446:446:446) (318:318:318)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Selector6\~0) - (DELAY - (ABSOLUTE - (PORT datab (610:610:610) (638:638:638)) - (PORT datac (561:561:561) (582:582:582)) - (PORT datad (957:957:957) (1029:1029:1029)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vram_address\[9\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1254:1254:1254) (1344:1344:1344)) - (PORT datab (987:987:987) (1066:1066:1066)) - (PORT datac (976:976:976) (1049:1049:1049)) - (PORT datad (282:282:282) (366:366:366)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[8\]) - (DELAY - (ABSOLUTE - (PORT clk (1538:1538:1538) (1550:1550:1550)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (820:820:820) (826:826:826)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~14) - (DELAY - (ABSOLUTE - (PORT datad (708:708:708) (780:780:780)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Selector5\~0) - (DELAY - (ABSOLUTE - (PORT dataa (655:655:655) (677:677:677)) - (PORT datac (792:792:792) (807:807:807)) - (PORT datad (957:957:957) (1033:1033:1033)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[9\]) - (DELAY - (ABSOLUTE - (PORT clk (1538:1538:1538) (1550:1550:1550)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (820:820:820) (826:826:826)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vram_address\[10\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1251:1251:1251) (1338:1338:1338)) - (PORT datab (981:981:981) (1058:1058:1058)) - (PORT datac (980:980:980) (1051:1051:1051)) - (PORT datad (285:285:285) (369:369:369)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vram_address\[10\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (612:612:612) (644:644:644)) - (PORT datab (1014:1014:1014) (1089:1089:1089)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[10\]) - (DELAY - (ABSOLUTE - (PORT clk (1538:1538:1538) (1550:1550:1550)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Selector3\~0) - (DELAY - (ABSOLUTE - (PORT datab (613:613:613) (639:639:639)) - (PORT datad (958:958:958) (1031:1031:1031)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[11\]) - (DELAY - (ABSOLUTE - (PORT clk (1538:1538:1538) (1550:1550:1550)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (820:820:820) (826:826:826)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Selector2\~0) - (DELAY - (ABSOLUTE - (PORT datac (618:618:618) (638:638:638)) - (PORT datad (957:957:957) (1029:1029:1029)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[12\]) - (DELAY - (ABSOLUTE - (PORT clk (1538:1538:1538) (1550:1550:1550)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (820:820:820) (826:826:826)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1548:1548:1548) (1620:1620:1620)) - (PORT clk (1864:1864:1864) (1891:1891:1891)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2599:2599:2599) (2697:2697:2697)) - (PORT d[1] (2358:2358:2358) (2589:2589:2589)) - (PORT d[2] (2326:2326:2326) (2476:2476:2476)) - (PORT d[3] (1990:1990:1990) (2063:2063:2063)) - (PORT d[4] (2926:2926:2926) (3182:3182:3182)) - (PORT d[5] (2089:2089:2089) (2294:2294:2294)) - (PORT d[6] (1566:1566:1566) (1667:1667:1667)) - (PORT d[7] (1626:1626:1626) (1711:1711:1711)) - (PORT d[8] (2773:2773:2773) (3020:3020:3020)) - (PORT d[9] (2077:2077:2077) (2186:2186:2186)) - (PORT d[10] (2124:2124:2124) (2247:2247:2247)) - (PORT d[11] (3187:3187:3187) (3328:3328:3328)) - (PORT d[12] (2201:2201:2201) (2298:2298:2298)) - (PORT clk (1861:1861:1861) (1887:1887:1887)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2768:2768:2768) (2740:2740:2740)) - (PORT clk (1861:1861:1861) (1887:1887:1887)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1864:1864:1864) (1891:1891:1891)) - (PORT d[0] (2876:2876:2876) (2827:2827:2827)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1865:1865:1865) (1892:1892:1892)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1865:1865:1865) (1892:1892:1892)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1865:1865:1865) (1892:1892:1892)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1865:1865:1865) (1892:1892:1892)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1819:1819:1819) (1816:1816:1816)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2147:2147:2147) (2193:2193:2193)) - (PORT clk (1829:1829:1829) (1822:1822:1822)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4636:4636:4636) (4688:4688:4688)) - (PORT d[1] (4395:4395:4395) (4383:4383:4383)) - (PORT d[2] (4558:4558:4558) (4624:4624:4624)) - (PORT d[3] (4721:4721:4721) (4720:4720:4720)) - (PORT d[4] (4265:4265:4265) (4262:4262:4262)) - (PORT d[5] (4417:4417:4417) (4355:4355:4355)) - (PORT d[6] (4638:4638:4638) (4708:4708:4708)) - (PORT d[7] (4394:4394:4394) (4343:4343:4343)) - (PORT d[8] (4731:4731:4731) (4705:4705:4705)) - (PORT d[9] (4601:4601:4601) (4791:4791:4791)) - (PORT d[10] (4436:4436:4436) (4445:4445:4445)) - (PORT d[11] (4654:4654:4654) (4682:4682:4682)) - (PORT d[12] (4454:4454:4454) (4466:4466:4466)) - (PORT clk (1825:1825:1825) (1818:1818:1818)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1829:1829:1829) (1822:1822:1822)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1830:1830:1830) (1823:1823:1823)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1830:1830:1830) (1823:1823:1823)) - (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1830:1830:1830) (1823:1823:1823)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1830:1830:1830) (1823:1823:1823)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1821:1821:1821) (1818:1818:1818)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|address_reg_a\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1203:1203:1203) (1298:1298:1298)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|address_reg_a\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1923:1923:1923) (1947:1947:1947)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) - (PORT asdata (1724:1724:1724) (1774:1774:1774)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|decode2\|eq_node\[1\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (697:697:697) (726:726:726)) - (PORT datab (262:262:262) (315:315:315)) - (PORT datac (366:366:366) (405:405:405)) - (PORT datad (1303:1303:1303) (1300:1300:1300)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1513:1513:1513) (1593:1593:1593)) - (PORT clk (1857:1857:1857) (1885:1885:1885)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2905:2905:2905) (3002:3002:3002)) - (PORT d[1] (2381:2381:2381) (2621:2621:2621)) - (PORT d[2] (1221:1221:1221) (1275:1275:1275)) - (PORT d[3] (2017:2017:2017) (2080:2080:2080)) - (PORT d[4] (2910:2910:2910) (3179:3179:3179)) - (PORT d[5] (2405:2405:2405) (2631:2631:2631)) - (PORT d[6] (1533:1533:1533) (1608:1608:1608)) - (PORT d[7] (1282:1282:1282) (1365:1365:1365)) - (PORT d[8] (1697:1697:1697) (1794:1794:1794)) - (PORT d[9] (1564:1564:1564) (1639:1639:1639)) - (PORT d[10] (2164:2164:2164) (2311:2311:2311)) - (PORT d[11] (3205:3205:3205) (3345:3345:3345)) - (PORT d[12] (1922:1922:1922) (2027:2027:2027)) - (PORT clk (1854:1854:1854) (1881:1881:1881)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2709:2709:2709) (2650:2650:2650)) - (PORT clk (1854:1854:1854) (1881:1881:1881)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1885:1885:1885)) - (PORT d[0] (3090:3090:3090) (3120:3120:3120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1886:1886:1886)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1886:1886:1886)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1886:1886:1886)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1886:1886:1886)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1812:1812:1812) (1810:1810:1810)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2167:2167:2167) (2208:2208:2208)) - (PORT clk (1822:1822:1822) (1816:1816:1816)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4624:4624:4624) (4660:4660:4660)) - (PORT d[1] (4162:4162:4162) (4152:4152:4152)) - (PORT d[2] (4263:4263:4263) (4325:4325:4325)) - (PORT d[3] (4486:4486:4486) (4524:4524:4524)) - (PORT d[4] (4333:4333:4333) (4346:4346:4346)) - (PORT d[5] (4356:4356:4356) (4399:4399:4399)) - (PORT d[6] (4459:4459:4459) (4542:4542:4542)) - (PORT d[7] (4161:4161:4161) (4129:4129:4129)) - (PORT d[8] (4409:4409:4409) (4389:4389:4389)) - (PORT d[9] (4581:4581:4581) (4772:4772:4772)) - (PORT d[10] (4418:4418:4418) (4409:4409:4409)) - (PORT d[11] (4535:4535:4535) (4594:4594:4594)) - (PORT d[12] (4450:4450:4450) (4459:4459:4459)) - (PORT clk (1818:1818:1818) (1812:1812:1812)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1822:1822:1822) (1816:1816:1816)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1823:1823:1823) (1817:1817:1817)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1823:1823:1823) (1817:1817:1817)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1823:1823:1823) (1817:1817:1817)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1823:1823:1823) (1817:1817:1817)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2533:2533:2533) (2623:2623:2623)) - (PORT d[1] (2220:2220:2220) (2418:2418:2418)) - (PORT d[2] (2325:2325:2325) (2498:2498:2498)) - (PORT d[3] (2178:2178:2178) (2338:2338:2338)) - (PORT d[4] (2896:2896:2896) (3148:3148:3148)) - (PORT d[5] (2277:2277:2277) (2465:2465:2465)) - (PORT d[6] (1866:1866:1866) (1991:1991:1991)) - (PORT d[7] (2226:2226:2226) (2303:2303:2303)) - (PORT d[8] (2742:2742:2742) (2980:2980:2980)) - (PORT d[9] (1744:1744:1744) (1855:1855:1855)) - (PORT d[10] (1754:1754:1754) (1834:1834:1834)) - (PORT d[11] (3116:3116:3116) (3240:3240:3240)) - (PORT d[12] (1285:1285:1285) (1359:1359:1359)) - (PORT clk (1869:1869:1869) (1894:1894:1894)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1869:1869:1869) (1894:1894:1894)) - (PORT d[0] (2187:2187:2187) (2254:2254:2254)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1870:1870:1870) (1895:1895:1895)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1832:1832:1832) (1857:1857:1857)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1017:1017:1017) (1020:1020:1020)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1018:1018:1018) (1021:1021:1021)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1018:1018:1018) (1021:1021:1021)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1018:1018:1018) (1021:1021:1021)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~87) - (DELAY - (ABSOLUTE - (PORT dataa (1348:1348:1348) (1400:1400:1400)) - (PORT datab (276:276:276) (364:364:364)) - (PORT datac (1381:1381:1381) (1421:1421:1421)) - (PORT datad (1657:1657:1657) (1684:1684:1684)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3643:3643:3643) (3885:3885:3885)) - (PORT d[1] (2602:2602:2602) (2837:2837:2837)) - (PORT d[2] (2449:2449:2449) (2542:2542:2542)) - (PORT d[3] (2141:2141:2141) (2296:2296:2296)) - (PORT d[4] (2227:2227:2227) (2405:2405:2405)) - (PORT d[5] (2065:2065:2065) (2249:2249:2249)) - (PORT d[6] (1926:1926:1926) (2066:2066:2066)) - (PORT d[7] (1993:1993:1993) (2107:2107:2107)) - (PORT d[8] (2992:2992:2992) (3233:3233:3233)) - (PORT d[9] (2617:2617:2617) (2763:2763:2763)) - (PORT d[10] (4742:4742:4742) (4968:4968:4968)) - (PORT d[11] (2083:2083:2083) (2222:2222:2222)) - (PORT d[12] (2446:2446:2446) (2592:2592:2592)) - (PORT clk (1857:1857:1857) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1883:1883:1883)) - (PORT d[0] (3176:3176:3176) (3088:3088:3088)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1820:1820:1820) (1846:1846:1846)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~88) - (DELAY - (ABSOLUTE - (PORT dataa (1285:1285:1285) (1292:1292:1292)) - (PORT datab (1157:1157:1157) (1165:1165:1165)) - (PORT datac (1614:1614:1614) (1636:1636:1636)) - (PORT datad (180:180:180) (209:209:209)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~89) - (DELAY - (ABSOLUTE - (PORT dataa (1434:1434:1434) (1498:1498:1498)) - (PORT datab (207:207:207) (249:249:249)) - (PORT datac (624:624:624) (685:685:685)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~111) - (DELAY - (ABSOLUTE - (PORT dataa (642:642:642) (683:683:683)) - (PORT datab (2010:2010:2010) (2117:2117:2117)) - (PORT datac (918:918:918) (1000:1000:1000)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_io_ibuf") - (INSTANCE raw_loader_in\~input) - (DELAY - (ABSOLUTE - (IOPATH i o (479:479:479) (732:732:732)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~86) - (DELAY - (ABSOLUTE - (PORT dataa (909:909:909) (967:967:967)) - (PORT datac (1544:1544:1544) (1682:1682:1682)) - (PORT datad (1984:1984:1984) (2079:2079:2079)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~100) - (DELAY - (ABSOLUTE - (PORT dataa (952:952:952) (1002:1002:1002)) - (PORT datab (1379:1379:1379) (1383:1383:1383)) - (PORT datac (181:181:181) (218:218:218)) - (PORT datad (181:181:181) (208:208:208)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~101) - (DELAY - (ABSOLUTE - (PORT dataa (947:947:947) (995:995:995)) - (PORT datab (894:894:894) (965:965:965)) - (PORT datac (1645:1645:1645) (1669:1669:1669)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[6\]) - (DELAY - (ABSOLUTE - (PORT dataa (275:275:275) (336:336:336)) - (PORT datab (1389:1389:1389) (1429:1429:1429)) - (PORT datac (938:938:938) (1004:1004:1004)) - (PORT datad (830:830:830) (833:833:833)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_re\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1684:1684:1684) (1826:1826:1826)) - (PORT datab (754:754:754) (857:857:857)) - (PORT datac (961:961:961) (1023:1023:1023)) - (PORT datad (1204:1204:1204) (1263:1263:1263)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_2) - (DELAY - (ABSOLUTE - (PORT dataa (971:971:971) (1041:1041:1041)) - (PORT datab (973:973:973) (1033:1033:1033)) - (PORT datac (961:961:961) (1024:1024:1024)) - (PORT datad (181:181:181) (209:209:209)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1526:1526:1526) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (841:841:841) (846:846:846)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[6\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (1178:1178:1178) (1226:1226:1226)) - (PORT datac (224:224:224) (273:273:273)) - (PORT datad (210:210:210) (243:243:243)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|ir_\|opcode\[6\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (195:195:195) (219:219:219)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1107:1107:1107) (1191:1191:1191)) - (PORT datab (909:909:909) (972:972:972)) - (PORT datac (661:661:661) (712:712:712)) - (PORT datad (375:375:375) (392:392:392)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1534:1534:1534)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1557:1557:1557)) - (PORT ena (1231:1231:1231) (1217:1217:1217)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal41\~0) - (DELAY - (ABSOLUTE - (PORT datac (1703:1703:1703) (1754:1754:1754)) - (PORT datad (1223:1223:1223) (1322:1322:1322)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal41\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1499:1499:1499) (1573:1573:1573)) - (PORT datab (2298:2298:2298) (2366:2366:2366)) - (PORT datac (2132:2132:2132) (2282:2282:2282)) - (PORT datad (1454:1454:1454) (1538:1538:1538)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal41\~2) - (DELAY - (ABSOLUTE - (PORT dataa (450:450:450) (502:502:502)) - (PORT datab (1649:1649:1649) (1644:1644:1644)) - (PORT datac (170:170:170) (202:202:202)) - (PORT datad (1095:1095:1095) (1127:1127:1127)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe) - (DELAY - (ABSOLUTE - (PORT dataa (1962:1962:1962) (2070:2070:2070)) - (PORT datab (1125:1125:1125) (1133:1133:1133)) - (PORT datac (2059:2059:2059) (2181:2181:2181)) - (PORT datad (179:179:179) (207:207:207)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1180:1180:1180) (1214:1214:1214)) - (PORT datab (292:292:292) (354:354:354)) - (PORT datac (259:259:259) (316:316:316)) - (PORT datad (245:245:245) (290:290:290)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1130:1130:1130) (1202:1202:1202)) - (PORT datab (1172:1172:1172) (1221:1221:1221)) - (PORT datac (419:419:419) (491:491:491)) - (PORT datad (660:660:660) (723:723:723)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (952:952:952) (1002:1002:1002)) - (PORT datac (1667:1667:1667) (1748:1748:1748)) - (PORT datad (900:900:900) (923:923:923)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~18) - (DELAY - (ABSOLUTE - (PORT datab (201:201:201) (240:240:240)) - (PORT datac (891:891:891) (913:913:913)) - (PORT datad (244:244:244) (286:286:286)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (369:369:369) (390:390:390)) - (PORT datab (631:631:631) (659:659:659)) - (PORT datac (1160:1160:1160) (1204:1204:1204)) - (PORT datad (606:606:606) (623:623:623)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (999:999:999) (1032:1032:1032)) - (PORT datac (582:582:582) (614:614:614)) - (PORT datad (221:221:221) (263:263:263)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[5\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (1300:1300:1300) (1351:1351:1351)) - (PORT datab (940:940:940) (958:958:958)) - (PORT datac (1822:1822:1822) (1884:1884:1884)) - (PORT datad (931:931:931) (981:981:981)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[5\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (647:647:647) (673:673:673)) - (PORT datab (255:255:255) (313:313:313)) - (PORT datac (175:175:175) (209:209:209)) - (PORT datad (945:945:945) (988:988:988)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sw1_\|db_down\[5\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (361:361:361) (501:501:501)) - (PORT datab (1351:1351:1351) (1413:1413:1413)) - (PORT datac (1147:1147:1147) (1181:1181:1181)) - (PORT datad (1196:1196:1196) (1243:1243:1243)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_36) - (DELAY - (ABSOLUTE - (PORT dataa (556:556:556) (578:578:578)) - (PORT datab (623:623:623) (651:651:651)) - (PORT datac (663:663:663) (695:695:695)) - (PORT datad (679:679:679) (697:697:697)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|flags_yf) - (DELAY - (ABSOLUTE - (PORT clk (1514:1514:1514) (1528:1528:1528)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[5\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (644:644:644) (702:702:702)) - (PORT datab (900:900:900) (949:949:949)) - (PORT datac (666:666:666) (693:693:693)) - (PORT datad (888:888:888) (905:905:905)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[5\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (969:969:969) (987:987:987)) - (PORT datab (200:200:200) (240:240:240)) - (PORT datac (948:948:948) (982:982:982)) - (PORT datad (864:864:864) (880:880:880)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[5\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (685:685:685) (717:717:717)) - (PORT datab (1197:1197:1197) (1212:1212:1212)) - (PORT datac (1119:1119:1119) (1150:1150:1150)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~107) - (DELAY - (ABSOLUTE - (PORT dataa (1749:1749:1749) (1858:1858:1858)) - (PORT datab (1231:1231:1231) (1298:1298:1298)) - (PORT datac (1559:1559:1559) (1700:1700:1700)) - (PORT datad (1126:1126:1126) (1171:1171:1171)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1190:1190:1190) (1230:1230:1230)) - (PORT clk (1845:1845:1845) (1873:1873:1873)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3686:3686:3686) (3900:3900:3900)) - (PORT d[1] (1735:1735:1735) (1904:1904:1904)) - (PORT d[2] (3045:3045:3045) (3164:3164:3164)) - (PORT d[3] (1901:1901:1901) (2003:2003:2003)) - (PORT d[4] (2206:2206:2206) (2342:2342:2342)) - (PORT d[5] (2677:2677:2677) (2865:2865:2865)) - (PORT d[6] (2060:2060:2060) (2133:2133:2133)) - (PORT d[7] (2769:2769:2769) (2894:2894:2894)) - (PORT d[8] (3033:3033:3033) (3241:3241:3241)) - (PORT d[9] (2831:2831:2831) (2926:2926:2926)) - (PORT d[10] (3516:3516:3516) (3751:3751:3751)) - (PORT d[11] (1807:1807:1807) (1907:1907:1907)) - (PORT d[12] (2081:2081:2081) (2168:2168:2168)) - (PORT clk (1842:1842:1842) (1869:1869:1869)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1939:1939:1939) (1956:1956:1956)) - (PORT clk (1842:1842:1842) (1869:1869:1869)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1845:1845:1845) (1873:1873:1873)) - (PORT d[0] (2676:2676:2676) (2715:2715:2715)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1846:1846:1846) (1874:1874:1874)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1846:1846:1846) (1874:1874:1874)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1846:1846:1846) (1874:1874:1874)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1846:1846:1846) (1874:1874:1874)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1805:1805:1805) (1832:1832:1832)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (990:990:990) (995:995:995)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (991:991:991) (996:996:996)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (991:991:991) (996:996:996)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (991:991:991) (996:996:996)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1180:1180:1180) (1209:1209:1209)) - (PORT clk (1843:1843:1843) (1871:1871:1871)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3984:3984:3984) (4216:4216:4216)) - (PORT d[1] (1704:1704:1704) (1855:1855:1855)) - (PORT d[2] (3307:3307:3307) (3443:3443:3443)) - (PORT d[3] (1880:1880:1880) (1997:1997:1997)) - (PORT d[4] (1863:1863:1863) (1963:1963:1963)) - (PORT d[5] (1643:1643:1643) (1769:1769:1769)) - (PORT d[6] (1761:1761:1761) (1817:1817:1817)) - (PORT d[7] (3056:3056:3056) (3189:3189:3189)) - (PORT d[8] (3324:3324:3324) (3551:3551:3551)) - (PORT d[9] (2869:2869:2869) (2985:2985:2985)) - (PORT d[10] (3454:3454:3454) (3652:3652:3652)) - (PORT d[11] (1540:1540:1540) (1618:1618:1618)) - (PORT d[12] (1726:1726:1726) (1787:1787:1787)) - (PORT clk (1840:1840:1840) (1867:1867:1867)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1932:1932:1932) (1890:1890:1890)) - (PORT clk (1840:1840:1840) (1867:1867:1867)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1843:1843:1843) (1871:1871:1871)) - (PORT d[0] (2406:2406:2406) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1872:1872:1872)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1872:1872:1872)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1872:1872:1872)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1872:1872:1872)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1803:1803:1803) (1830:1830:1830)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (988:988:988) (993:993:993)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (989:989:989) (994:994:994)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (989:989:989) (994:994:994)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (989:989:989) (994:994:994)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1218:1218:1218) (1268:1268:1268)) - (PORT clk (1843:1843:1843) (1871:1871:1871)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3686:3686:3686) (3901:3901:3901)) - (PORT d[1] (1692:1692:1692) (1858:1858:1858)) - (PORT d[2] (2977:2977:2977) (3118:3118:3118)) - (PORT d[3] (2124:2124:2124) (2230:2230:2230)) - (PORT d[4] (2237:2237:2237) (2352:2352:2352)) - (PORT d[5] (2684:2684:2684) (2875:2875:2875)) - (PORT d[6] (1801:1801:1801) (1880:1880:1880)) - (PORT d[7] (2772:2772:2772) (2901:2901:2901)) - (PORT d[8] (3346:3346:3346) (3575:3575:3575)) - (PORT d[9] (2889:2889:2889) (3004:3004:3004)) - (PORT d[10] (3484:3484:3484) (3709:3709:3709)) - (PORT d[11] (1816:1816:1816) (1924:1924:1924)) - (PORT d[12] (2023:2023:2023) (2090:2090:2090)) - (PORT clk (1840:1840:1840) (1867:1867:1867)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1889:1889:1889) (1883:1883:1883)) - (PORT clk (1840:1840:1840) (1867:1867:1867)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1843:1843:1843) (1871:1871:1871)) - (PORT d[0] (2482:2482:2482) (2488:2488:2488)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1872:1872:1872)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1872:1872:1872)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1872:1872:1872)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1872:1872:1872)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1803:1803:1803) (1830:1830:1830)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (988:988:988) (993:993:993)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (989:989:989) (994:994:994)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (989:989:989) (994:994:994)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (989:989:989) (994:994:994)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1446:1446:1446) (1499:1499:1499)) - (PORT datab (1431:1431:1431) (1517:1517:1517)) - (PORT datac (1141:1141:1141) (1132:1132:1132)) - (PORT datad (1111:1111:1111) (1136:1136:1136)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1272:1272:1272) (1326:1326:1326)) - (PORT clk (1855:1855:1855) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2887:2887:2887) (3004:3004:3004)) - (PORT d[1] (2662:2662:2662) (2916:2916:2916)) - (PORT d[2] (1218:1218:1218) (1257:1257:1257)) - (PORT d[3] (1701:1701:1701) (1750:1750:1750)) - (PORT d[4] (2885:2885:2885) (3119:3119:3119)) - (PORT d[5] (2382:2382:2382) (2607:2607:2607)) - (PORT d[6] (1263:1263:1263) (1339:1339:1339)) - (PORT d[7] (1323:1323:1323) (1404:1404:1404)) - (PORT d[8] (1739:1739:1739) (1814:1814:1814)) - (PORT d[9] (1262:1262:1262) (1335:1335:1335)) - (PORT d[10] (2409:2409:2409) (2560:2560:2560)) - (PORT d[11] (3166:3166:3166) (3381:3381:3381)) - (PORT d[12] (2205:2205:2205) (2307:2307:2307)) - (PORT clk (1852:1852:1852) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1501:1501:1501) (1496:1496:1496)) - (PORT clk (1852:1852:1852) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1855:1855:1855) (1883:1883:1883)) - (PORT d[0] (2128:2128:2128) (2120:2120:2120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1815:1815:1815) (1842:1842:1842)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1000:1000:1000) (1005:1005:1005)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1001:1001:1001) (1006:1006:1006)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1001:1001:1001) (1006:1006:1006)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1001:1001:1001) (1006:1006:1006)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1130:1130:1130) (1175:1175:1175)) - (PORT datab (1704:1704:1704) (1781:1781:1781)) - (PORT datac (171:171:171) (203:203:203)) - (PORT datad (1426:1426:1426) (1482:1482:1482)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1607:1607:1607) (1720:1720:1720)) - (PORT clk (1852:1852:1852) (1880:1880:1880)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3186:3186:3186) (3300:3300:3300)) - (PORT d[1] (2007:2007:2007) (2188:2188:2188)) - (PORT d[2] (2193:2193:2193) (2290:2290:2290)) - (PORT d[3] (1861:1861:1861) (1989:1989:1989)) - (PORT d[4] (2485:2485:2485) (2606:2606:2606)) - (PORT d[5] (2236:2236:2236) (2402:2402:2402)) - (PORT d[6] (1711:1711:1711) (1755:1755:1755)) - (PORT d[7] (1687:1687:1687) (1776:1776:1776)) - (PORT d[8] (2608:2608:2608) (2791:2791:2791)) - (PORT d[9] (1955:1955:1955) (2077:2077:2077)) - (PORT d[10] (2011:2011:2011) (2111:2111:2111)) - (PORT d[11] (2425:2425:2425) (2555:2555:2555)) - (PORT d[12] (2552:2552:2552) (2625:2625:2625)) - (PORT clk (1849:1849:1849) (1876:1876:1876)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2563:2563:2563) (2536:2536:2536)) - (PORT clk (1849:1849:1849) (1876:1876:1876)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1880:1880:1880)) - (PORT d[0] (3968:3968:3968) (4054:4054:4054)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1881:1881:1881)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1881:1881:1881)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1881:1881:1881)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1881:1881:1881)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1807:1807:1807) (1805:1805:1805)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1738:1738:1738) (1727:1727:1727)) - (PORT clk (1817:1817:1817) (1811:1811:1811)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4391:4391:4391) (4458:4458:4458)) - (PORT d[1] (4215:4215:4215) (4261:4261:4261)) - (PORT d[2] (4322:4322:4322) (4388:4388:4388)) - (PORT d[3] (4683:4683:4683) (4718:4718:4718)) - (PORT d[4] (4355:4355:4355) (4366:4366:4366)) - (PORT d[5] (4618:4618:4618) (4672:4672:4672)) - (PORT d[6] (4745:4745:4745) (4781:4781:4781)) - (PORT d[7] (4330:4330:4330) (4399:4399:4399)) - (PORT d[8] (4420:4420:4420) (4455:4455:4455)) - (PORT d[9] (4477:4477:4477) (4721:4721:4721)) - (PORT d[10] (4604:4604:4604) (4600:4600:4600)) - (PORT d[11] (4406:4406:4406) (4437:4437:4437)) - (PORT d[12] (4503:4503:4503) (4638:4638:4638)) - (PORT clk (1813:1813:1813) (1807:1807:1807)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1817:1817:1817) (1811:1811:1811)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1818:1818:1818) (1812:1812:1812)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1818:1818:1818) (1812:1812:1812)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1818:1818:1818) (1812:1812:1812)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1818:1818:1818) (1812:1812:1812)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2857:2857:2857) (2972:2972:2972)) - (PORT d[1] (1730:1730:1730) (1897:1897:1897)) - (PORT d[2] (1950:1950:1950) (2070:2070:2070)) - (PORT d[3] (1897:1897:1897) (2023:2023:2023)) - (PORT d[4] (2739:2739:2739) (2895:2895:2895)) - (PORT d[5] (2232:2232:2232) (2412:2412:2412)) - (PORT d[6] (1964:1964:1964) (2031:2031:2031)) - (PORT d[7] (2136:2136:2136) (2268:2268:2268)) - (PORT d[8] (2383:2383:2383) (2561:2561:2561)) - (PORT d[9] (1973:1973:1973) (2079:2079:2079)) - (PORT d[10] (1681:1681:1681) (1740:1740:1740)) - (PORT d[11] (2036:2036:2036) (2101:2101:2101)) - (PORT d[12] (2509:2509:2509) (2578:2578:2578)) - (PORT clk (1857:1857:1857) (1882:1882:1882)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1882:1882:1882)) - (PORT d[0] (2716:2716:2716) (2794:2794:2794)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1883:1883:1883)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1820:1820:1820) (1845:1845:1845)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1008:1008:1008)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1009:1009:1009)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1009:1009:1009)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1009:1009:1009)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3922:3922:3922) (4160:4160:4160)) - (PORT d[1] (2875:2875:2875) (3108:3108:3108)) - (PORT d[2] (2719:2719:2719) (2815:2815:2815)) - (PORT d[3] (2274:2274:2274) (2436:2436:2436)) - (PORT d[4] (2511:2511:2511) (2691:2691:2691)) - (PORT d[5] (2520:2520:2520) (2696:2696:2696)) - (PORT d[6] (1898:1898:1898) (2018:2018:2018)) - (PORT d[7] (2284:2284:2284) (2398:2398:2398)) - (PORT d[8] (3090:3090:3090) (3363:3363:3363)) - (PORT d[9] (2691:2691:2691) (2835:2835:2835)) - (PORT d[10] (4531:4531:4531) (4774:4774:4774)) - (PORT d[11] (1925:1925:1925) (2083:2083:2083)) - (PORT d[12] (2422:2422:2422) (2553:2553:2553)) - (PORT clk (1857:1857:1857) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1883:1883:1883)) - (PORT d[0] (3644:3644:3644) (3567:3567:3567)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1820:1820:1820) (1846:1846:1846)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1502:1502:1502) (1566:1566:1566)) - (PORT clk (1869:1869:1869) (1895:1895:1895)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2818:2818:2818) (2896:2896:2896)) - (PORT d[1] (2077:2077:2077) (2294:2294:2294)) - (PORT d[2] (2223:2223:2223) (2370:2370:2370)) - (PORT d[3] (2274:2274:2274) (2375:2375:2375)) - (PORT d[4] (2928:2928:2928) (3204:3204:3204)) - (PORT d[5] (2379:2379:2379) (2550:2550:2550)) - (PORT d[6] (1572:1572:1572) (1678:1678:1678)) - (PORT d[7] (1564:1564:1564) (1666:1666:1666)) - (PORT d[8] (2761:2761:2761) (2991:2991:2991)) - (PORT d[9] (2092:2092:2092) (2225:2225:2225)) - (PORT d[10] (1872:1872:1872) (1997:1997:1997)) - (PORT d[11] (2890:2890:2890) (3011:3011:3011)) - (PORT d[12] (1605:1605:1605) (1686:1686:1686)) - (PORT clk (1866:1866:1866) (1891:1891:1891)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2511:2511:2511) (2509:2509:2509)) - (PORT clk (1866:1866:1866) (1891:1891:1891)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1869:1869:1869) (1895:1895:1895)) - (PORT d[0] (2908:2908:2908) (2850:2850:2850)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1870:1870:1870) (1896:1896:1896)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1870:1870:1870) (1896:1896:1896)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1870:1870:1870) (1896:1896:1896)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1870:1870:1870) (1896:1896:1896)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1824:1824:1824) (1820:1820:1820)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2487:2487:2487) (2567:2567:2567)) - (PORT clk (1834:1834:1834) (1826:1826:1826)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4515:4515:4515) (4502:4502:4502)) - (PORT d[1] (4098:4098:4098) (4096:4096:4096)) - (PORT d[2] (4387:4387:4387) (4416:4416:4416)) - (PORT d[3] (4466:4466:4466) (4494:4494:4494)) - (PORT d[4] (4550:4550:4550) (4547:4547:4547)) - (PORT d[5] (4395:4395:4395) (4433:4433:4433)) - (PORT d[6] (4601:4601:4601) (4650:4650:4650)) - (PORT d[7] (4160:4160:4160) (4143:4143:4143)) - (PORT d[8] (4661:4661:4661) (4689:4689:4689)) - (PORT d[9] (4502:4502:4502) (4695:4695:4695)) - (PORT d[10] (4622:4622:4622) (4632:4632:4632)) - (PORT d[11] (4398:4398:4398) (4428:4428:4428)) - (PORT d[12] (4464:4464:4464) (4487:4487:4487)) - (PORT clk (1830:1830:1830) (1822:1822:1822)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1834:1834:1834) (1826:1826:1826)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1835:1835:1835) (1827:1827:1827)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1835:1835:1835) (1827:1827:1827)) - (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1835:1835:1835) (1827:1827:1827)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1835:1835:1835) (1827:1827:1827)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1822:1822:1822)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Mux2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1428:1428:1428) (1500:1500:1500)) - (PORT datab (969:969:969) (1047:1047:1047)) - (PORT datac (1170:1170:1170) (1197:1197:1197)) - (PORT datad (1685:1685:1685) (1714:1714:1714)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Mux2\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1516:1516:1516) (1602:1602:1602)) - (PORT datab (970:970:970) (1048:1048:1048)) - (PORT datac (1706:1706:1706) (1767:1767:1767)) - (PORT datad (171:171:171) (196:196:196)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[5\]\~110) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (246:246:246)) - (PORT datab (1206:1206:1206) (1299:1299:1299)) - (PORT datac (1658:1658:1658) (1693:1693:1693)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[5\]\~85) - (DELAY - (ABSOLUTE - (PORT dataa (1382:1382:1382) (1395:1395:1395)) - (PORT datab (1382:1382:1382) (1409:1409:1409)) - (PORT datac (842:842:842) (919:919:919)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[5\]\~99) - (DELAY - (ABSOLUTE - (PORT dataa (809:809:809) (832:832:832)) - (PORT datad (194:194:194) (219:219:219)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[5\]) - (DELAY - (ABSOLUTE - (PORT dataa (972:972:972) (1043:1043:1043)) - (PORT datab (1039:1039:1039) (1071:1071:1071)) - (PORT datac (240:240:240) (293:293:293)) - (PORT datad (948:948:948) (984:984:984)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1526:1526:1526) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (841:841:841) (846:846:846)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[5\]\~14) - (DELAY - (ABSOLUTE - (PORT datab (707:707:707) (729:729:729)) - (PORT datac (235:235:235) (309:309:309)) - (PORT datad (359:359:359) (384:384:384)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[5\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (980:980:980) (1004:1004:1004)) - (PORT datab (917:917:917) (967:967:967)) - (PORT datac (825:825:825) (825:825:825)) - (PORT datad (891:891:891) (919:919:919)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1541:1541:1541)) - (PORT asdata (598:598:598) (653:653:653)) - (PORT clrn (1571:1571:1571) (1550:1550:1550)) - (PORT ena (1479:1479:1479) (1488:1488:1488)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|SYNTHESIZED_WIRE_0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1209:1209:1209) (1333:1333:1333)) - (PORT datab (857:857:857) (877:877:877)) - (PORT datac (862:862:862) (884:884:884)) - (PORT datad (1897:1897:1897) (1952:1952:1952)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|DFFE_inst4) - (DELAY - (ABSOLUTE - (PORT clk (1527:1527:1527) (1547:1547:1547)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1586:1586:1586) (1563:1563:1563)) - (PORT ena (820:820:820) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|use_ixiy) - (DELAY - (ABSOLUTE - (PORT dataa (974:974:974) (1072:1072:1072)) - (PORT datac (930:930:930) (1012:1012:1012)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~23) - (DELAY - (ABSOLUTE - (PORT dataa (1192:1192:1192) (1230:1230:1230)) - (PORT datab (998:998:998) (1107:1107:1107)) - (PORT datac (657:657:657) (721:721:721)) - (PORT datad (1243:1243:1243) (1329:1329:1329)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~34) - (DELAY - (ABSOLUTE - (PORT dataa (888:888:888) (915:915:915)) - (PORT datab (667:667:667) (679:679:679)) - (PORT datac (904:904:904) (934:934:934)) - (PORT datad (360:360:360) (382:382:382)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~31) - (DELAY - (ABSOLUTE - (PORT dataa (1168:1168:1168) (1211:1211:1211)) - (PORT datab (1607:1607:1607) (1625:1625:1625)) - (PORT datac (614:614:614) (646:646:646)) - (PORT datad (1081:1081:1081) (1126:1126:1126)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~29) - (DELAY - (ABSOLUTE - (PORT dataa (1255:1255:1255) (1363:1363:1363)) - (PORT datab (469:469:469) (523:523:523)) - (PORT datac (1707:1707:1707) (1763:1763:1763)) - (PORT datad (264:264:264) (317:317:317)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~30) - (DELAY - (ABSOLUTE - (PORT dataa (390:390:390) (441:441:441)) - (PORT datab (198:198:198) (238:238:238)) - (PORT datac (1072:1072:1072) (1108:1108:1108)) - (PORT datad (202:202:202) (231:231:231)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~28) - (DELAY - (ABSOLUTE - (PORT dataa (1172:1172:1172) (1212:1212:1212)) - (PORT datab (568:568:568) (599:599:599)) - (PORT datac (1103:1103:1103) (1115:1115:1115)) - (PORT datad (317:317:317) (336:336:336)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~32) - (DELAY - (ABSOLUTE - (PORT dataa (851:851:851) (898:898:898)) - (PORT datab (198:198:198) (236:236:236)) - (PORT datac (590:590:590) (597:597:597)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~42) - (DELAY - (ABSOLUTE - (PORT dataa (230:230:230) (275:275:275)) - (PORT datab (645:645:645) (670:670:670)) - (PORT datac (194:194:194) (238:238:238)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~14) - (DELAY - (ABSOLUTE - (PORT dataa (887:887:887) (914:914:914)) - (PORT datab (1115:1115:1115) (1147:1147:1147)) - (PORT datac (1402:1402:1402) (1464:1464:1464)) - (PORT datad (899:899:899) (942:942:942)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~10) - (DELAY - (ABSOLUTE - (PORT dataa (885:885:885) (895:895:895)) - (PORT datab (939:939:939) (994:994:994)) - (PORT datac (959:959:959) (1031:1031:1031)) - (PORT datad (1113:1113:1113) (1143:1143:1143)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~9) - (DELAY - (ABSOLUTE - (PORT dataa (889:889:889) (916:916:916)) - (PORT datab (876:876:876) (896:896:896)) - (PORT datac (1106:1106:1106) (1134:1134:1134)) - (PORT datad (326:326:326) (350:350:350)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1572:1572:1572) (1664:1664:1664)) - (PORT datab (205:205:205) (245:245:245)) - (PORT datac (1885:1885:1885) (1936:1936:1936)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1126:1126:1126) (1249:1249:1249)) - (PORT datab (997:997:997) (1061:1061:1061)) - (PORT datac (1628:1628:1628) (1678:1678:1678)) - (PORT datad (1161:1161:1161) (1198:1198:1198)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1424:1424:1424) (1425:1425:1425)) - (PORT datab (1116:1116:1116) (1146:1146:1146)) - (PORT datac (1040:1040:1040) (1082:1082:1082)) - (PORT datad (337:337:337) (357:357:357)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~15) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (172:172:172) (206:206:206)) - (PORT datad (594:594:594) (614:614:614)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~20) - (DELAY - (ABSOLUTE - (PORT dataa (631:631:631) (644:644:644)) - (PORT datab (1041:1041:1041) (1082:1082:1082)) - (PORT datac (571:571:571) (588:588:588)) - (PORT datad (598:598:598) (647:647:647)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~48) - (DELAY - (ABSOLUTE - (PORT dataa (886:886:886) (933:933:933)) - (PORT datab (1205:1205:1205) (1227:1227:1227)) - (PORT datac (1512:1512:1512) (1585:1585:1585)) - (PORT datad (674:674:674) (712:712:712)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~22) - (DELAY - (ABSOLUTE - (PORT dataa (1353:1353:1353) (1383:1383:1383)) - (PORT datab (852:852:852) (880:880:880)) - (PORT datac (1075:1075:1075) (1109:1109:1109)) - (PORT datad (195:195:195) (220:220:220)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~21) - (DELAY - (ABSOLUTE - (PORT dataa (870:870:870) (942:942:942)) - (PORT datab (941:941:941) (1018:1018:1018)) - (PORT datac (1551:1551:1551) (1591:1591:1591)) - (PORT datad (1215:1215:1215) (1217:1217:1217)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~23) - (DELAY - (ABSOLUTE - (PORT dataa (867:867:867) (909:909:909)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (806:806:806) (819:819:819)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~26) - (DELAY - (ABSOLUTE - (PORT dataa (2068:2068:2068) (2159:2159:2159)) - (PORT datab (1202:1202:1202) (1215:1215:1215)) - (PORT datac (1137:1137:1137) (1179:1179:1179)) - (PORT datad (1150:1150:1150) (1187:1187:1187)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~25) - (DELAY - (ABSOLUTE - (PORT dataa (2504:2504:2504) (2616:2616:2616)) - (PORT datab (576:576:576) (586:586:586)) - (PORT datac (193:193:193) (227:227:227)) - (PORT datad (981:981:981) (1012:1012:1012)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~27) - (DELAY - (ABSOLUTE - (PORT dataa (1663:1663:1663) (1697:1697:1697)) - (PORT datab (833:833:833) (893:893:893)) - (PORT datac (1036:1036:1036) (1091:1091:1091)) - (PORT datad (770:770:770) (816:816:816)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~33) - (DELAY - (ABSOLUTE - (PORT dataa (1031:1031:1031) (1043:1043:1043)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (819:819:819) (869:869:869)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~35) - (DELAY - (ABSOLUTE - (PORT dataa (865:865:865) (888:888:888)) - (PORT datab (198:198:198) (236:236:236)) - (PORT datac (821:821:821) (872:872:872)) - (PORT datad (195:195:195) (219:219:219)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_re) - (DELAY - (ABSOLUTE - (PORT datab (974:974:974) (1035:1035:1035)) - (PORT datac (964:964:964) (1026:1026:1026)) - (PORT datad (182:182:182) (211:211:211)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1008:1008:1008) (1080:1080:1080)) - (PORT clk (1860:1860:1860) (1887:1887:1887)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1191:1191:1191) (1224:1224:1224)) - (PORT d[1] (2415:2415:2415) (2649:2649:2649)) - (PORT d[2] (1758:1758:1758) (1803:1803:1803)) - (PORT d[3] (1013:1013:1013) (1063:1063:1063)) - (PORT d[4] (2608:2608:2608) (2826:2826:2826)) - (PORT d[5] (3496:3496:3496) (3699:3699:3699)) - (PORT d[6] (1026:1026:1026) (1099:1099:1099)) - (PORT d[7] (3197:3197:3197) (3375:3375:3375)) - (PORT d[8] (1246:1246:1246) (1270:1270:1270)) - (PORT d[9] (1026:1026:1026) (1088:1088:1088)) - (PORT d[10] (1315:1315:1315) (1388:1388:1388)) - (PORT d[11] (2503:2503:2503) (2659:2659:2659)) - (PORT d[12] (1307:1307:1307) (1387:1387:1387)) - (PORT clk (1857:1857:1857) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (944:944:944) (900:900:900)) - (PORT clk (1857:1857:1857) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (PORT d[0] (1721:1721:1721) (1677:1677:1677)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1820:1820:1820) (1846:1846:1846)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (708:708:708) (754:754:754)) - (PORT clk (1860:1860:1860) (1888:1888:1888)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (966:966:966) (1010:1010:1010)) - (PORT d[1] (2966:2966:2966) (3237:3237:3237)) - (PORT d[2] (1238:1238:1238) (1256:1256:1256)) - (PORT d[3] (1302:1302:1302) (1383:1383:1383)) - (PORT d[4] (2581:2581:2581) (2796:2796:2796)) - (PORT d[5] (2980:2980:2980) (3208:3208:3208)) - (PORT d[6] (692:692:692) (727:727:727)) - (PORT d[7] (705:705:705) (744:744:744)) - (PORT d[8] (1011:1011:1011) (1032:1032:1032)) - (PORT d[9] (717:717:717) (757:757:757)) - (PORT d[10] (1036:1036:1036) (1102:1102:1102)) - (PORT d[11] (2544:2544:2544) (2757:2757:2757)) - (PORT d[12] (1267:1267:1267) (1319:1319:1319)) - (PORT clk (1857:1857:1857) (1884:1884:1884)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (967:967:967) (945:945:945)) - (PORT clk (1857:1857:1857) (1884:1884:1884)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1888:1888:1888)) - (PORT d[0] (2089:2089:2089) (2073:2073:2073)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1889:1889:1889)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1889:1889:1889)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1889:1889:1889)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1889:1889:1889)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1820:1820:1820) (1847:1847:1847)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1010:1010:1010)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1011:1011:1011)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1011:1011:1011)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1011:1011:1011)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[1\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (682:682:682) (752:752:752)) - (PORT datab (688:688:688) (754:754:754)) - (PORT datac (786:786:786) (795:795:795)) - (PORT datad (864:864:864) (896:896:896)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (700:700:700) (744:744:744)) - (PORT clk (1860:1860:1860) (1887:1887:1887)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3167:3167:3167) (3303:3303:3303)) - (PORT d[1] (2937:2937:2937) (3208:3208:3208)) - (PORT d[2] (967:967:967) (987:987:987)) - (PORT d[3] (1341:1341:1341) (1401:1401:1401)) - (PORT d[4] (2612:2612:2612) (2843:2843:2843)) - (PORT d[5] (2651:2651:2651) (2894:2894:2894)) - (PORT d[6] (960:960:960) (1001:1001:1001)) - (PORT d[7] (1270:1270:1270) (1343:1343:1343)) - (PORT d[8] (1442:1442:1442) (1513:1513:1513)) - (PORT d[9] (971:971:971) (1019:1019:1019)) - (PORT d[10] (1031:1031:1031) (1057:1057:1057)) - (PORT d[11] (2872:2872:2872) (3095:3095:3095)) - (PORT d[12] (969:969:969) (1020:1020:1020)) - (PORT clk (1857:1857:1857) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1245:1245:1245) (1221:1221:1221)) - (PORT clk (1857:1857:1857) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (PORT d[0] (2049:2049:2049) (2003:2003:2003)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1820:1820:1820) (1846:1846:1846)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (743:743:743) (772:772:772)) - (PORT clk (1859:1859:1859) (1886:1886:1886)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3188:3188:3188) (3327:3327:3327)) - (PORT d[1] (2678:2678:2678) (2951:2951:2951)) - (PORT d[2] (1298:1298:1298) (1309:1309:1309)) - (PORT d[3] (1348:1348:1348) (1402:1402:1402)) - (PORT d[4] (2616:2616:2616) (2850:2850:2850)) - (PORT d[5] (2675:2675:2675) (2903:2903:2903)) - (PORT d[6] (1230:1230:1230) (1289:1289:1289)) - (PORT d[7] (1132:1132:1132) (1148:1148:1148)) - (PORT d[8] (1470:1470:1470) (1552:1552:1552)) - (PORT d[9] (1550:1550:1550) (1617:1617:1617)) - (PORT d[10] (724:724:724) (767:767:767)) - (PORT d[11] (2854:2854:2854) (3086:3086:3086)) - (PORT d[12] (971:971:971) (1034:1034:1034)) - (PORT clk (1856:1856:1856) (1882:1882:1882)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1229:1229:1229) (1208:1208:1208)) - (PORT clk (1856:1856:1856) (1882:1882:1882)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1859:1859:1859) (1886:1886:1886)) - (PORT d[0] (1822:1822:1822) (1811:1811:1811)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1819:1819:1819) (1845:1845:1845)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1004:1004:1004) (1008:1008:1008)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[1\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1242:1242:1242) (1299:1299:1299)) - (PORT datab (198:198:198) (238:238:238)) - (PORT datac (968:968:968) (1003:1003:1003)) - (PORT datad (1089:1089:1089) (1119:1119:1119)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (746:746:746) (776:776:776)) - (PORT clk (1853:1853:1853) (1881:1881:1881)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2906:2906:2906) (3003:3003:3003)) - (PORT d[1] (2374:2374:2374) (2624:2624:2624)) - (PORT d[2] (1590:1590:1590) (1604:1604:1604)) - (PORT d[3] (1983:1983:1983) (2059:2059:2059)) - (PORT d[4] (2920:2920:2920) (3176:3176:3176)) - (PORT d[5] (2692:2692:2692) (2903:2903:2903)) - (PORT d[6] (1267:1267:1267) (1350:1350:1350)) - (PORT d[7] (1307:1307:1307) (1395:1395:1395)) - (PORT d[8] (1742:1742:1742) (1842:1842:1842)) - (PORT d[9] (1557:1557:1557) (1621:1621:1621)) - (PORT d[10] (2161:2161:2161) (2306:2306:2306)) - (PORT d[11] (3233:3233:3233) (3375:3375:3375)) - (PORT d[12] (1281:1281:1281) (1357:1357:1357)) - (PORT clk (1850:1850:1850) (1877:1877:1877)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2941:2941:2941) (2895:2895:2895)) - (PORT clk (1850:1850:1850) (1877:1877:1877)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1881:1881:1881)) - (PORT d[0] (3092:3092:3092) (3136:3136:3136)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1854:1854:1854) (1882:1882:1882)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1854:1854:1854) (1882:1882:1882)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1854:1854:1854) (1882:1882:1882)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1854:1854:1854) (1882:1882:1882)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1808:1808:1808) (1806:1806:1806)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2118:2118:2118) (2165:2165:2165)) - (PORT clk (1818:1818:1818) (1812:1812:1812)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4374:4374:4374) (4418:4418:4418)) - (PORT d[1] (4140:4140:4140) (4128:4128:4128)) - (PORT d[2] (4277:4277:4277) (4327:4327:4327)) - (PORT d[3] (4389:4389:4389) (4374:4374:4374)) - (PORT d[4] (4369:4369:4369) (4385:4385:4385)) - (PORT d[5] (4402:4402:4402) (4357:4357:4357)) - (PORT d[6] (4635:4635:4635) (4717:4717:4717)) - (PORT d[7] (4444:4444:4444) (4393:4393:4393)) - (PORT d[8] (4445:4445:4445) (4433:4433:4433)) - (PORT d[9] (4508:4508:4508) (4699:4699:4699)) - (PORT d[10] (4409:4409:4409) (4440:4440:4440)) - (PORT d[11] (4509:4509:4509) (4563:4563:4563)) - (PORT d[12] (4429:4429:4429) (4547:4547:4547)) - (PORT clk (1814:1814:1814) (1808:1808:1808)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1818:1818:1818) (1812:1812:1812)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1819:1819:1819) (1813:1813:1813)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1819:1819:1819) (1813:1813:1813)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1819:1819:1819) (1813:1813:1813)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1819:1819:1819) (1813:1813:1813)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2570:2570:2570) (2648:2648:2648)) - (PORT d[1] (2033:2033:2033) (2232:2232:2232)) - (PORT d[2] (2324:2324:2324) (2498:2498:2498)) - (PORT d[3] (2521:2521:2521) (2687:2687:2687)) - (PORT d[4] (2940:2940:2940) (3191:3191:3191)) - (PORT d[5] (2266:2266:2266) (2447:2447:2447)) - (PORT d[6] (1866:1866:1866) (1990:1990:1990)) - (PORT d[7] (2543:2543:2543) (2628:2628:2628)) - (PORT d[8] (2767:2767:2767) (2988:2988:2988)) - (PORT d[9] (1759:1759:1759) (1863:1863:1863)) - (PORT d[10] (1515:1515:1515) (1609:1609:1609)) - (PORT d[11] (3453:3453:3453) (3586:3586:3586)) - (PORT d[12] (1542:1542:1542) (1649:1649:1649)) - (PORT clk (1868:1868:1868) (1894:1894:1894)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1868:1868:1868) (1894:1894:1894)) - (PORT d[0] (2191:2191:2191) (2247:2247:2247)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1869:1869:1869) (1895:1895:1895)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1831:1831:1831) (1857:1857:1857)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1016:1016:1016) (1020:1020:1020)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1017:1017:1017) (1021:1021:1021)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1017:1017:1017) (1021:1021:1021)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1017:1017:1017) (1021:1021:1021)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1511:1511:1511) (1554:1554:1554)) - (PORT d[1] (2684:2684:2684) (2948:2948:2948)) - (PORT d[2] (989:989:989) (1036:1036:1036)) - (PORT d[3] (1684:1684:1684) (1752:1752:1752)) - (PORT d[4] (2594:2594:2594) (2826:2826:2826)) - (PORT d[5] (2711:2711:2711) (2920:2920:2920)) - (PORT d[6] (973:973:973) (1031:1031:1031)) - (PORT d[7] (964:964:964) (1018:1018:1018)) - (PORT d[8] (1426:1426:1426) (1505:1505:1505)) - (PORT d[9] (1567:1567:1567) (1660:1660:1660)) - (PORT d[10] (2478:2478:2478) (2623:2623:2623)) - (PORT d[11] (2885:2885:2885) (3126:3126:3126)) - (PORT d[12] (1271:1271:1271) (1324:1324:1324)) - (PORT clk (1855:1855:1855) (1882:1882:1882)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1855:1855:1855) (1882:1882:1882)) - (PORT d[0] (872:872:872) (859:859:859)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1883:1883:1883)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1818:1818:1818) (1845:1845:1845)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1003:1003:1003) (1008:1008:1008)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1004:1004:1004) (1009:1009:1009)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1004:1004:1004) (1009:1009:1009)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1004:1004:1004) (1009:1009:1009)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (926:926:926) (931:931:931)) - (PORT clk (1857:1857:1857) (1884:1884:1884)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3174:3174:3174) (3295:3295:3295)) - (PORT d[1] (2670:2670:2670) (2938:2938:2938)) - (PORT d[2] (1591:1591:1591) (1604:1604:1604)) - (PORT d[3] (1700:1700:1700) (1749:1749:1749)) - (PORT d[4] (2908:2908:2908) (3176:3176:3176)) - (PORT d[5] (2711:2711:2711) (2920:2920:2920)) - (PORT d[6] (974:974:974) (1032:1032:1032)) - (PORT d[7] (1544:1544:1544) (1607:1607:1607)) - (PORT d[8] (3051:3051:3051) (3314:3314:3314)) - (PORT d[9] (996:996:996) (1062:1062:1062)) - (PORT d[10] (2482:2482:2482) (2620:2620:2620)) - (PORT d[11] (2859:2859:2859) (3096:3096:3096)) - (PORT d[12] (2233:2233:2233) (2338:2338:2338)) - (PORT clk (1854:1854:1854) (1880:1880:1880)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3083:3083:3083) (3081:3081:3081)) - (PORT clk (1854:1854:1854) (1880:1880:1880)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1884:1884:1884)) - (PORT d[0] (1803:1803:1803) (1787:1787:1787)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1885:1885:1885)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1885:1885:1885)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1885:1885:1885)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1885:1885:1885)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1812:1812:1812) (1809:1809:1809)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2405:2405:2405) (2433:2433:2433)) - (PORT clk (1822:1822:1822) (1815:1815:1815)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4622:4622:4622) (4649:4649:4649)) - (PORT d[1] (4242:4242:4242) (4320:4320:4320)) - (PORT d[2] (4251:4251:4251) (4295:4295:4295)) - (PORT d[3] (4399:4399:4399) (4422:4422:4422)) - (PORT d[4] (4340:4340:4340) (4354:4354:4354)) - (PORT d[5] (4534:4534:4534) (4546:4546:4546)) - (PORT d[6] (4731:4731:4731) (4801:4801:4801)) - (PORT d[7] (4488:4488:4488) (4531:4531:4531)) - (PORT d[8] (4436:4436:4436) (4436:4436:4436)) - (PORT d[9] (4525:4525:4525) (4711:4711:4711)) - (PORT d[10] (4473:4473:4473) (4495:4495:4495)) - (PORT d[11] (4414:4414:4414) (4386:4386:4386)) - (PORT d[12] (4391:4391:4391) (4381:4381:4381)) - (PORT clk (1818:1818:1818) (1811:1811:1811)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1822:1822:1822) (1815:1815:1815)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1823:1823:1823) (1816:1816:1816)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1823:1823:1823) (1816:1816:1816)) - (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1823:1823:1823) (1816:1816:1816)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1823:1823:1823) (1816:1816:1816)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1814:1814:1814) (1811:1811:1811)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Selector1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (668:668:668) (731:731:731)) - (PORT datab (1192:1192:1192) (1240:1240:1240)) - (PORT datac (825:825:825) (833:833:833)) - (PORT datad (890:890:890) (911:911:911)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Selector1\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1189:1189:1189) (1198:1198:1198)) - (PORT datab (1192:1192:1192) (1240:1240:1240)) - (PORT datac (1509:1509:1509) (1586:1586:1586)) - (PORT datad (171:171:171) (196:196:196)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~103) - (DELAY - (ABSOLUTE - (PORT dataa (1738:1738:1738) (1846:1846:1846)) - (PORT datab (1412:1412:1412) (1506:1506:1506)) - (PORT datac (648:648:648) (701:701:701)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (336:336:336) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_io_ibuf") (INSTANCE PS2_DAT\~input) @@ -36080,24 +28878,45 @@ ) ) (CELL - (CELLTYPE "cycloneive_clkctrl") - (INSTANCE reset\~clkctrl) + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE KEY\[0\]\~input) (DELAY (ABSOLUTE - (PORT inclk[0] (842:842:842) (859:859:859)) + (IOPATH i o (481:481:481) (733:733:733)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\~0) + (INSTANCE reset) (DELAY (ABSOLUTE - (PORT dataa (282:282:282) (386:386:386)) - (PORT datab (291:291:291) (382:382:382)) - (PORT datad (245:245:245) (325:325:325)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT datac (1601:1601:1601) (1525:1525:1525)) + (PORT datad (820:820:820) (846:846:846)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE reset\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (573:573:573) (569:569:569)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\~3) + (DELAY + (ABSOLUTE + (PORT dataa (273:273:273) (374:374:374)) + (PORT datab (282:282:282) (378:378:378)) + (PORT datad (249:249:249) (330:330:330)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -36117,7 +28936,7 @@ (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[7\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (3358:3358:3358) (3700:3700:3700)) + (PORT datad (3184:3184:3184) (3436:3436:3436)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -36127,9 +28946,9 @@ (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[7\]) (DELAY (ABSOLUTE - (PORT clk (1512:1512:1512) (1525:1525:1525)) + (PORT clk (1509:1509:1509) (1522:1522:1522)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1566:1566:1566) (1561:1561:1561)) + (PORT clrn (1550:1550:1550) (1543:1543:1543)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -36143,7 +28962,7 @@ (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[6\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (225:225:225) (297:297:297)) + (PORT datad (226:226:226) (300:300:300)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -36153,9 +28972,9 @@ (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[6\]) (DELAY (ABSOLUTE - (PORT clk (1512:1512:1512) (1525:1525:1525)) + (PORT clk (1509:1509:1509) (1522:1522:1522)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1566:1566:1566) (1561:1561:1561)) + (PORT clrn (1550:1550:1550) (1543:1543:1543)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -36169,7 +28988,7 @@ (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[5\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (227:227:227) (302:302:302)) + (PORT datad (240:240:240) (310:310:310)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -36179,9 +28998,9 @@ (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[5\]) (DELAY (ABSOLUTE - (PORT clk (1512:1512:1512) (1525:1525:1525)) + (PORT clk (1509:1509:1509) (1522:1522:1522)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1566:1566:1566) (1561:1561:1561)) + (PORT clrn (1550:1550:1550) (1543:1543:1543)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -36195,7 +29014,7 @@ (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[4\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (239:239:239) (309:309:309)) + (PORT datad (224:224:224) (296:296:296)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -36205,9 +29024,9 @@ (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[4\]) (DELAY (ABSOLUTE - (PORT clk (1512:1512:1512) (1525:1525:1525)) + (PORT clk (1509:1509:1509) (1522:1522:1522)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1566:1566:1566) (1561:1561:1561)) + (PORT clrn (1550:1550:1550) (1543:1543:1543)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -36216,28 +29035,12 @@ (HOLD d (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|Equal0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (252:252:252) (342:342:342)) - (PORT datab (250:250:250) (335:335:335)) - (PORT datac (380:380:380) (441:441:441)) - (PORT datad (225:225:225) (298:298:298)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[3\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (227:227:227) (299:299:299)) + (PORT datad (226:226:226) (300:300:300)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -36247,9 +29050,9 @@ (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[3\]) (DELAY (ABSOLUTE - (PORT clk (1512:1512:1512) (1525:1525:1525)) + (PORT clk (1509:1509:1509) (1522:1522:1522)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1566:1566:1566) (1561:1561:1561)) + (PORT clrn (1550:1550:1550) (1543:1543:1543)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -36263,7 +29066,7 @@ (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[2\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (228:228:228) (301:301:301)) + (PORT datad (226:226:226) (299:299:299)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -36273,9 +29076,9 @@ (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[2\]) (DELAY (ABSOLUTE - (PORT clk (1512:1512:1512) (1525:1525:1525)) + (PORT clk (1509:1509:1509) (1522:1522:1522)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1566:1566:1566) (1561:1561:1561)) + (PORT clrn (1550:1550:1550) (1543:1543:1543)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -36289,7 +29092,7 @@ (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[1\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (226:226:226) (298:298:298)) + (PORT datad (225:225:225) (297:297:297)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -36299,9 +29102,9 @@ (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[1\]) (DELAY (ABSOLUTE - (PORT clk (1512:1512:1512) (1525:1525:1525)) + (PORT clk (1509:1509:1509) (1522:1522:1522)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1566:1566:1566) (1561:1561:1561)) + (PORT clrn (1550:1550:1550) (1543:1543:1543)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -36310,17 +29113,33 @@ (HOLD d (posedge clk) (157:157:157)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (253:253:253) (343:343:343)) + (PORT datab (251:251:251) (336:336:336)) + (PORT datac (376:376:376) (441:441:441)) + (PORT datad (226:226:226) (298:298:298)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|ps2_keyboard_\|Equal0\~1) (DELAY (ABSOLUTE - (PORT dataa (202:202:202) (246:246:246)) - (PORT datab (252:252:252) (337:337:337)) - (PORT datac (225:225:225) (305:305:305)) - (PORT datad (227:227:227) (299:299:299)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (253:253:253) (343:343:343)) + (PORT datab (253:253:253) (338:338:338)) + (PORT datac (226:226:226) (307:307:307)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -36331,7 +29150,7 @@ (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[0\]\~0) (DELAY (ABSOLUTE - (PORT datac (226:226:226) (307:307:307)) + (PORT datac (227:227:227) (309:309:309)) (IOPATH datac combout (241:241:241) (241:241:241)) ) ) @@ -36341,9 +29160,9 @@ (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[0\]) (DELAY (ABSOLUTE - (PORT clk (1512:1512:1512) (1525:1525:1525)) + (PORT clk (1509:1509:1509) (1522:1522:1522)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1566:1566:1566) (1561:1561:1561)) + (PORT clrn (1550:1550:1550) (1543:1543:1543)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -36357,9 +29176,9 @@ (INSTANCE ula_\|ps2_keyboard_\|ps2_clk_in\~0) (DELAY (ABSOLUTE - (PORT datab (208:208:208) (249:249:249)) + (PORT dataa (211:211:211) (258:258:258)) (PORT datad (227:227:227) (299:299:299)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -36370,9 +29189,9 @@ (INSTANCE ula_\|ps2_keyboard_\|ps2_clk_in) (DELAY (ABSOLUTE - (PORT clk (1512:1512:1512) (1525:1525:1525)) + (PORT clk (1509:1509:1509) (1522:1522:1522)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1566:1566:1566) (1561:1561:1561)) + (PORT clrn (1550:1550:1550) (1543:1543:1543)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -36386,10 +29205,10 @@ (INSTANCE ula_\|ps2_keyboard_\|clk_edge\~0) (DELAY (ABSOLUTE - (PORT datab (208:208:208) (250:250:250)) - (PORT datac (218:218:218) (295:295:295)) - (PORT datad (224:224:224) (296:296:296)) - (IOPATH datab combout (304:304:304) (311:311:311)) + (PORT dataa (212:212:212) (261:261:261)) + (PORT datac (217:217:217) (293:293:293)) + (PORT datad (228:228:228) (301:301:301)) + (IOPATH dataa combout (303:303:303) (308:308:308)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -36400,9 +29219,9 @@ (INSTANCE ula_\|ps2_keyboard_\|clk_edge) (DELAY (ABSOLUTE - (PORT clk (1512:1512:1512) (1525:1525:1525)) + (PORT clk (1509:1509:1509) (1522:1522:1522)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1566:1566:1566) (1561:1561:1561)) + (PORT clrn (1550:1550:1550) (1543:1543:1543)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -36413,13 +29232,13 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\[0\]) + (INSTANCE ula_\|ps2_keyboard_\|bit_count\[3\]) (DELAY (ABSOLUTE - (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT clk (1507:1507:1507) (1521:1521:1521)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1567:1567:1567) (1562:1562:1562)) - (PORT ena (2016:2016:2016) (2055:2055:2055)) + (PORT clrn (1547:1547:1547) (1540:1540:1540)) + (PORT ena (2271:2271:2271) (2360:2360:2360)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -36434,9 +29253,9 @@ (INSTANCE ula_\|ps2_keyboard_\|bit_count\~1) (DELAY (ABSOLUTE - (PORT dataa (282:282:282) (387:387:387)) - (PORT datab (292:292:292) (383:383:383)) - (PORT datad (240:240:240) (317:317:317)) + (PORT dataa (271:271:271) (369:369:369)) + (PORT datab (278:278:278) (372:372:372)) + (PORT datad (250:250:250) (334:334:334)) (IOPATH dataa combout (303:303:303) (299:299:299)) (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -36449,43 +29268,10 @@ (INSTANCE ula_\|ps2_keyboard_\|bit_count\[2\]) (DELAY (ABSOLUTE - (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT clk (1507:1507:1507) (1521:1521:1521)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1567:1567:1567) (1562:1562:1562)) - (PORT ena (2016:2016:2016) (2055:2055:2055)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\~3) - (DELAY - (ABSOLUTE - (PORT dataa (279:279:279) (382:382:382)) - (PORT datab (278:278:278) (373:373:373)) - (PORT datad (242:242:242) (321:321:321)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1535:1535:1535)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1567:1567:1567) (1562:1562:1562)) - (PORT ena (2016:2016:2016) (2055:2055:2055)) + (PORT clrn (1547:1547:1547) (1540:1540:1540)) + (PORT ena (2271:2271:2271) (2360:2360:2360)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -36500,9 +29286,9 @@ (INSTANCE ula_\|ps2_keyboard_\|bit_count\~2) (DELAY (ABSOLUTE - (PORT dataa (410:410:410) (480:480:480)) - (PORT datab (279:279:279) (374:374:374)) - (PORT datad (243:243:243) (322:322:322)) + (PORT dataa (272:272:272) (374:374:374)) + (PORT datab (281:281:281) (377:377:377)) + (PORT datad (247:247:247) (327:327:327)) (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datab combout (336:336:336) (325:325:325)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -36515,10 +29301,43 @@ (INSTANCE ula_\|ps2_keyboard_\|bit_count\[1\]) (DELAY (ABSOLUTE - (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT clk (1507:1507:1507) (1521:1521:1521)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1567:1567:1567) (1562:1562:1562)) - (PORT ena (2016:2016:2016) (2055:2055:2055)) + (PORT clrn (1547:1547:1547) (1540:1540:1540)) + (PORT ena (2271:2271:2271) (2360:2360:2360)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\~0) + (DELAY + (ABSOLUTE + (PORT dataa (277:277:277) (377:377:377)) + (PORT datab (276:276:276) (371:371:371)) + (PORT datad (251:251:251) (330:330:330)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1507:1507:1507) (1521:1521:1521)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1547:1547:1547) (1540:1540:1540)) + (PORT ena (2271:2271:2271) (2360:2360:2360)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -36533,10 +29352,10 @@ (INSTANCE ula_\|ps2_keyboard_\|always1\~0) (DELAY (ABSOLUTE - (PORT dataa (275:275:275) (377:377:377)) - (PORT datab (288:288:288) (377:377:377)) - (PORT datac (3414:3414:3414) (3775:3775:3775)) - (PORT datad (251:251:251) (331:331:331)) + (PORT dataa (276:276:276) (373:373:373)) + (PORT datab (279:279:279) (374:374:374)) + (PORT datac (4093:4093:4093) (4524:4524:4524)) + (PORT datad (243:243:243) (322:322:322)) (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -36549,11 +29368,11 @@ (INSTANCE ula_\|ps2_keyboard_\|LessThan0\~0) (DELAY (ABSOLUTE - (PORT datab (289:289:289) (380:380:380)) - (PORT datac (247:247:247) (341:341:341)) - (PORT datad (248:248:248) (328:328:328)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (276:276:276) (378:378:378)) + (PORT datab (278:278:278) (373:373:373)) + (PORT datad (246:246:246) (325:325:325)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -36563,12 +29382,12 @@ (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[0\]\~0) (DELAY (ABSOLUTE - (PORT dataa (202:202:202) (246:246:246)) - (PORT datab (264:264:264) (354:354:354)) - (PORT datac (1368:1368:1368) (1427:1427:1427)) + (PORT dataa (269:269:269) (366:366:366)) + (PORT datab (201:201:201) (241:241:241)) + (PORT datac (1623:1623:1623) (1741:1741:1741)) (PORT datad (182:182:182) (211:211:211)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -36579,10 +29398,10 @@ (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[8\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1544:1544:1544)) - (PORT asdata (3957:3957:3957) (4311:4311:4311)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (PORT ena (1226:1226:1226) (1215:1215:1215)) + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT asdata (4114:4114:4114) (4514:4514:4514)) + (PORT clrn (1555:1555:1555) (1548:1548:1548)) + (PORT ena (1802:1802:1802) (1801:1801:1801)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -36592,21 +29411,31 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (219:219:219) (288:288:288)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[7\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1544:1544:1544)) - (PORT asdata (560:560:560) (634:634:634)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (PORT ena (1226:1226:1226) (1215:1215:1215)) + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1555:1555:1555) (1548:1548:1548)) + (PORT ena (1802:1802:1802) (1801:1801:1801)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) + (HOLD d (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) ) ) @@ -36615,10 +29444,10 @@ (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[6\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1544:1544:1544)) - (PORT asdata (602:602:602) (685:685:685)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (PORT ena (1226:1226:1226) (1215:1215:1215)) + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT asdata (629:629:629) (715:715:715)) + (PORT clrn (1555:1555:1555) (1548:1548:1548)) + (PORT ena (1802:1802:1802) (1801:1801:1801)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -36633,10 +29462,10 @@ (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[5\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1544:1544:1544)) - (PORT asdata (588:588:588) (665:665:665)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (PORT ena (1226:1226:1226) (1215:1215:1215)) + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT asdata (1040:1040:1040) (1106:1106:1106)) + (PORT clrn (1555:1555:1555) (1548:1548:1548)) + (PORT ena (1802:1802:1802) (1801:1801:1801)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -36651,10 +29480,10 @@ (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[4\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1543:1543:1543)) - (PORT asdata (958:958:958) (1010:1010:1010)) - (PORT clrn (1576:1576:1576) (1571:1571:1571)) - (PORT ena (1200:1200:1200) (1196:1196:1196)) + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT asdata (809:809:809) (898:898:898)) + (PORT clrn (1555:1555:1555) (1548:1548:1548)) + (PORT ena (1802:1802:1802) (1801:1801:1801)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -36669,10 +29498,10 @@ (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[3\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1544:1544:1544)) - (PORT asdata (960:960:960) (1018:1018:1018)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (PORT ena (1226:1226:1226) (1215:1215:1215)) + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (1541:1541:1541) (1621:1621:1621)) + (PORT clrn (1557:1557:1557) (1549:1549:1549)) + (PORT ena (2289:2289:2289) (2267:2267:2267)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -36687,10 +29516,10 @@ (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[2\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1543:1543:1543)) - (PORT asdata (951:951:951) (1014:1014:1014)) - (PORT clrn (1576:1576:1576) (1571:1571:1571)) - (PORT ena (1200:1200:1200) (1196:1196:1196)) + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT asdata (1528:1528:1528) (1600:1600:1600)) + (PORT clrn (1555:1555:1555) (1547:1547:1547)) + (PORT ena (1975:1975:1975) (1972:1972:1972)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -36705,10 +29534,10 @@ (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[1\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1543:1543:1543)) - (PORT asdata (761:761:761) (840:840:840)) - (PORT clrn (1576:1576:1576) (1571:1571:1571)) - (PORT ena (1200:1200:1200) (1196:1196:1196)) + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT asdata (604:604:604) (688:688:688)) + (PORT clrn (1555:1555:1555) (1547:1547:1547)) + (PORT ena (1975:1975:1975) (1972:1972:1972)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -36718,93 +29547,43 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1133:1133:1133) (1224:1224:1224)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[0\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1543:1543:1543)) - (PORT asdata (791:791:791) (867:867:867)) - (PORT clrn (1576:1576:1576) (1571:1571:1571)) - (PORT ena (1200:1200:1200) (1196:1196:1196)) + (PORT clk (1510:1510:1510) (1524:1524:1524)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1550:1550:1550) (1543:1543:1543)) + (PORT ena (1270:1270:1270) (1278:1278:1278)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) + (HOLD d (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Equal0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (990:990:990) (1075:1075:1075)) - (PORT datab (675:675:675) (742:742:742)) - (PORT datac (757:757:757) (876:876:876)) - (PORT datad (781:781:781) (888:888:888)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Equal0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1415:1415:1415) (1549:1549:1549)) - (PORT datab (937:937:937) (1037:1037:1037)) - (PORT datac (171:171:171) (205:205:205)) - (PORT datad (763:763:763) (875:875:875)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|extended\~0) - (DELAY - (ABSOLUTE - (PORT datab (1062:1062:1062) (1155:1155:1155)) - (PORT datad (785:785:785) (795:795:795)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (664:664:664) (722:722:722)) - (PORT datab (288:288:288) (378:378:378)) - (PORT datad (833:833:833) (880:880:880)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~0) (DELAY (ABSOLUTE - (PORT dataa (741:741:741) (827:827:827)) - (PORT datab (669:669:669) (749:749:749)) - (PORT datac (655:655:655) (721:721:721)) - (PORT datad (438:438:438) (511:511:511)) + (PORT dataa (1156:1156:1156) (1261:1261:1261)) + (PORT datab (313:313:313) (413:413:413)) + (PORT datac (960:960:960) (1045:1045:1045)) + (PORT datad (949:949:949) (1017:1017:1017)) (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (243:243:243) (242:242:242)) @@ -36812,15 +29591,30 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (465:465:465) (561:561:561)) + (PORT datab (495:495:495) (591:591:591)) + (PORT datad (442:442:442) (500:500:500)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~2) (DELAY (ABSOLUTE - (PORT datab (668:668:668) (736:736:736)) - (PORT datac (345:345:345) (369:369:369)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT dataa (1049:1049:1049) (1137:1137:1137)) + (PORT datac (173:173:173) (206:206:206)) + (PORT datad (777:777:777) (823:823:823)) + (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -36831,10 +29625,10 @@ (INSTANCE ula_\|ps2_keyboard_\|scan_code_ready\~0) (DELAY (ABSOLUTE - (PORT dataa (210:210:210) (255:255:255)) - (PORT datab (3434:3434:3434) (3812:3812:3812)) - (PORT datac (1368:1368:1368) (1428:1428:1428)) - (PORT datad (358:358:358) (390:390:390)) + (PORT dataa (4129:4129:4129) (4562:4562:4562)) + (PORT datab (1649:1649:1649) (1770:1770:1770)) + (PORT datac (623:623:623) (642:642:642)) + (PORT datad (181:181:181) (209:209:209)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -36847,9 +29641,9 @@ (INSTANCE ula_\|ps2_keyboard_\|scan_code_ready) (DELAY (ABSOLUTE - (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT clk (1507:1507:1507) (1521:1521:1521)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1567:1567:1567) (1562:1562:1562)) + (PORT clrn (1547:1547:1547) (1540:1540:1540)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -36858,15 +29652,91 @@ (HOLD d (posedge clk) (157:157:157)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (434:434:434) (504:504:504)) + (PORT datab (983:983:983) (1066:1066:1066)) + (PORT datac (931:931:931) (996:996:996)) + (PORT datad (678:678:678) (759:759:759)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (694:694:694) (783:783:783)) + (PORT datab (693:693:693) (752:752:752)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (2178:2178:2178) (2280:2280:2280)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|released\~0) + (DELAY + (ABSOLUTE + (PORT dataa (291:291:291) (387:387:387)) + (PORT datab (1232:1232:1232) (1299:1299:1299)) + (PORT datad (333:333:333) (358:358:358)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|released) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1555:1555:1555) (1548:1548:1548)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|extended\~0) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (397:397:397)) + (PORT datad (956:956:956) (1027:1027:1027)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|zx_keyboard_\|extended) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1545:1545:1545)) + (PORT clk (1521:1521:1521) (1534:1534:1534)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (PORT ena (1764:1764:1764) (1796:1796:1796)) + (PORT clrn (1555:1555:1555) (1548:1548:1548)) + (PORT ena (1826:1826:1826) (1852:1852:1852)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -36878,26 +29748,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~15) + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~21) (DELAY (ABSOLUTE - (PORT dataa (678:678:678) (758:758:758)) - (PORT datab (664:664:664) (692:692:692)) - (PORT datac (260:260:260) (346:346:346)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (486:486:486) (553:553:553)) - (PORT datac (1367:1367:1367) (1453:1453:1453)) - (PORT datad (841:841:841) (864:864:864)) + (PORT dataa (515:515:515) (590:590:590)) + (PORT datac (288:288:288) (373:373:373)) + (PORT datad (1195:1195:1195) (1259:1259:1259)) (IOPATH dataa combout (325:325:325) (320:320:320)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -36906,293 +29762,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~37) + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~22) (DELAY (ABSOLUTE - (PORT dataa (1164:1164:1164) (1265:1265:1265)) - (PORT datac (641:641:641) (670:670:670)) - (PORT datad (910:910:910) (977:977:977)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|shifted\~0) - (DELAY - (ABSOLUTE - (PORT dataa (396:396:396) (426:426:426)) - (PORT datac (615:615:615) (667:667:667)) - (PORT datad (726:726:726) (803:803:803)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|released\~0) - (DELAY - (ABSOLUTE - (PORT dataa (669:669:669) (736:736:736)) - (PORT datab (663:663:663) (694:694:694)) - (PORT datad (1337:1337:1337) (1379:1379:1379)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|released) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr17\~0) - (DELAY - (ABSOLUTE - (PORT dataa (488:488:488) (568:568:568)) - (PORT datab (663:663:663) (740:740:740)) - (PORT datac (606:606:606) (673:673:673)) - (PORT datad (259:259:259) (336:336:336)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|shifted\~2) - (DELAY - (ABSOLUTE - (PORT dataa (203:203:203) (247:247:247)) - (PORT datac (416:416:416) (498:498:498)) - (PORT datad (651:651:651) (725:725:725)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|shifted\~3) - (DELAY - (ABSOLUTE - (PORT dataa (601:601:601) (616:616:616)) - (PORT datab (428:428:428) (507:507:507)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|shifted) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1543:1543:1543)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1576:1576:1576) (1571:1571:1571)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (744:744:744) (848:848:848)) - (PORT datab (984:984:984) (1072:1072:1072)) - (PORT datad (962:962:962) (1042:1042:1042)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~38) - (DELAY - (ABSOLUTE - (PORT datab (751:751:751) (858:858:858)) - (PORT datac (739:739:739) (840:840:840)) - (PORT datad (729:729:729) (835:835:835)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~39) - (DELAY - (ABSOLUTE - (PORT dataa (351:351:351) (394:394:394)) - (PORT datab (201:201:201) (241:241:241)) - (PORT datad (175:175:175) (202:202:202)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1573:1573:1573)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]\~31) - (DELAY - (ABSOLUTE - (PORT datab (963:963:963) (1041:1041:1041)) - (PORT datad (729:729:729) (834:834:834)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (740:740:740) (827:827:827)) - (PORT datab (290:290:290) (378:378:378)) - (PORT datac (649:649:649) (725:725:725)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~32) - (DELAY - (ABSOLUTE - (PORT datab (655:655:655) (729:729:729)) - (PORT datac (395:395:395) (471:471:471)) - (PORT datad (657:657:657) (716:716:716)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (376:376:376) (418:418:418)) - (PORT datab (223:223:223) (270:270:270)) - (PORT datac (658:658:658) (723:723:723)) - (PORT datad (433:433:433) (507:507:507)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (225:225:225) (269:269:269)) - (PORT datab (622:622:622) (671:671:671)) - (PORT datad (962:962:962) (1038:1038:1038)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1573:1573:1573)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (1160:1160:1160) (1230:1230:1230)) - (PORT datab (241:241:241) (321:321:321)) - (PORT datac (215:215:215) (291:291:291)) - (PORT datad (548:548:548) (570:570:570)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (969:969:969) (1044:1044:1044)) - (PORT datac (902:902:902) (995:995:995)) + (PORT dataa (667:667:667) (737:737:737)) + (PORT datac (259:259:259) (350:350:350)) (IOPATH dataa combout (341:341:341) (347:347:347)) (IOPATH datac combout (243:243:243) (242:242:242)) ) @@ -37200,29 +29774,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~28) + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]\~23) (DELAY (ABSOLUTE - (PORT dataa (1413:1413:1413) (1549:1549:1549)) - (PORT datab (696:696:696) (729:729:729)) - (PORT datac (959:959:959) (1041:1041:1041)) - (PORT datad (190:190:190) (224:224:224)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~29) - (DELAY - (ABSOLUTE - (PORT datab (981:981:981) (1070:1070:1070)) - (PORT datac (721:721:721) (830:830:830)) - (PORT datad (729:729:729) (838:838:838)) - (IOPATH datab combout (342:342:342) (342:342:342)) + (PORT dataa (847:847:847) (935:935:935)) + (PORT datab (1008:1008:1008) (1092:1092:1092)) + (PORT datac (830:830:830) (887:887:887)) + (PORT datad (1542:1542:1542) (1630:1630:1630)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -37230,12 +29790,26 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~30) + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]\~24) (DELAY (ABSOLUTE - (PORT dataa (792:792:792) (908:908:908)) - (PORT datab (667:667:667) (685:685:685)) - (PORT datad (496:496:496) (512:512:512)) + (PORT dataa (756:756:756) (830:830:830)) + (PORT datab (951:951:951) (1077:1077:1077)) + (PORT datad (198:198:198) (224:224:224)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (936:936:936) (1023:1023:1023)) + (PORT datab (642:642:642) (729:729:729)) + (PORT datad (375:375:375) (402:402:402)) (IOPATH dataa combout (325:325:325) (328:328:328)) (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -37243,75 +29817,14 @@ ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1573:1573:1573)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (1414:1414:1414) (1542:1542:1542)) - (PORT datab (213:213:213) (258:258:258)) - (PORT datac (667:667:667) (692:692:692)) - (PORT datad (766:766:766) (872:872:872)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (716:716:716) (818:818:818)) - (PORT datab (363:363:363) (394:394:394)) - (PORT datac (717:717:717) (819:819:819)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (1555:1555:1555) (1666:1666:1666)) - (PORT datab (982:982:982) (1037:1037:1037)) - (PORT datad (518:518:518) (530:530:530)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT clk (1518:1518:1518) (1532:1532:1532)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) + (PORT clrn (1558:1558:1558) (1550:1550:1550)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -37325,23 +29838,374 @@ (INSTANCE ula_\|zx_keyboard_\|key_row\~0) (DELAY (ABSOLUTE - (PORT datab (1469:1469:1469) (1606:1606:1606)) - (PORT datac (912:912:912) (975:975:975)) - (PORT datad (217:217:217) (285:285:285)) + (PORT datab (2434:2434:2434) (2613:2613:2613)) + (PORT datac (1881:1881:1881) (1943:1943:1943)) + (PORT datad (216:216:216) (284:284:284)) (IOPATH datab combout (336:336:336) (325:325:325)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (846:846:846) (935:935:935)) + (PORT datab (1010:1010:1010) (1096:1096:1096)) + (PORT datac (829:829:829) (887:887:887)) + (PORT datad (908:908:908) (1031:1031:1031)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (1316:1316:1316) (1413:1413:1413)) + (PORT datab (971:971:971) (1049:1049:1049)) + (PORT datad (399:399:399) (475:475:475)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (612:612:612) (635:635:635)) + (PORT datab (949:949:949) (1020:1020:1020)) + (PORT datad (184:184:184) (215:215:215)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1558:1558:1558) (1549:1549:1549)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[11\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1433:1433:1433) (1482:1482:1482)) + (PORT datab (1398:1398:1398) (1451:1451:1451)) + (PORT datad (306:306:306) (323:323:323)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1527:1527:1527)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (980:980:980) (1030:1030:1030)) + (PORT sload (2032:2032:2032) (2084:2084:2084)) + (PORT ena (2298:2298:2298) (2265:2265:2265)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[11\]\~19) + (DELAY + (ABSOLUTE + (PORT datac (2119:2119:2119) (2214:2214:2214)) + (PORT datad (1199:1199:1199) (1296:1296:1296)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (506:506:506) (582:582:582)) + (PORT datab (727:727:727) (802:802:802)) + (PORT datac (290:290:290) (379:379:379)) + (PORT datad (1195:1195:1195) (1258:1258:1258)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1196:1196:1196) (1273:1273:1273)) + (PORT datab (719:719:719) (787:787:787)) + (PORT datac (961:961:961) (1035:1035:1035)) + (PORT datad (2206:2206:2206) (2296:2296:2296)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1482:1482:1482) (1607:1607:1607)) + (PORT datab (965:965:965) (1044:1044:1044)) + (PORT datac (614:614:614) (634:634:634)) + (PORT datad (347:347:347) (370:370:370)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (783:783:783) (866:866:866)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1558:1558:1558) (1550:1550:1550)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[9\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1396:1396:1396) (1442:1442:1442)) + (PORT datab (868:868:868) (901:901:901)) + (PORT datad (180:180:180) (209:209:209)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1527:1527:1527)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (580:580:580) (654:654:654)) + (PORT sload (2041:2041:2041) (2133:2133:2133)) + (PORT ena (2004:2004:2004) (1967:1967:1967)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[9\]\~17) + (DELAY + (ABSOLUTE + (PORT datab (261:261:261) (344:344:344)) + (PORT datac (2391:2391:2391) (2523:2523:2523)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~13) + (DELAY + (ABSOLUTE + (PORT datab (1232:1232:1232) (1296:1296:1296)) + (PORT datac (289:289:289) (378:378:378)) + (PORT datad (332:332:332) (357:357:357)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|shifted\~2) + (DELAY + (ABSOLUTE + (PORT datab (1028:1028:1028) (1107:1107:1107)) + (PORT datac (700:700:700) (766:766:766)) + (PORT datad (597:597:597) (613:613:613)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~14) (DELAY (ABSOLUTE - (PORT datab (425:425:425) (503:503:503)) - (PORT datac (1117:1117:1117) (1170:1170:1170)) - (PORT datad (651:651:651) (723:723:723)) + (PORT dataa (1047:1047:1047) (1139:1139:1139)) + (PORT datab (313:313:313) (414:414:414)) + (PORT datac (957:957:957) (1046:1046:1046)) + (PORT datad (946:946:946) (1019:1019:1019)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1049:1049:1049) (1136:1136:1136)) + (PORT datab (200:200:200) (240:240:240)) + (PORT datac (961:961:961) (1043:1043:1043)) + (PORT datad (1125:1125:1125) (1214:1214:1214)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr17\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1157:1157:1157) (1263:1263:1263)) + (PORT datab (314:314:314) (413:413:413)) + (PORT datac (957:957:957) (1039:1039:1039)) + (PORT datad (913:913:913) (983:983:983)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|shifted\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1050:1050:1050) (1142:1142:1142)) + (PORT datab (975:975:975) (1058:1058:1058)) + (PORT datac (321:321:321) (340:340:340)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|shifted\~4) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (1163:1163:1163) (1216:1216:1216)) + (PORT datad (851:851:851) (879:879:879)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|shifted) + (DELAY + (ABSOLUTE + (PORT clk (1510:1510:1510) (1524:1524:1524)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1550:1550:1550) (1543:1543:1543)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~12) + (DELAY + (ABSOLUTE + (PORT datab (1165:1165:1165) (1220:1220:1220)) + (PORT datac (260:260:260) (338:338:338)) + (PORT datad (1006:1006:1006) (1089:1089:1089)) (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -37353,43 +30217,11 @@ (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~16) (DELAY (ABSOLUTE - (PORT dataa (693:693:693) (776:776:776)) - (PORT datab (412:412:412) (493:493:493)) - (PORT datac (606:606:606) (674:674:674)) - (PORT datad (261:261:261) (340:340:340)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (490:490:490) (569:569:569)) - (PORT datab (664:664:664) (741:741:741)) - (PORT datac (497:497:497) (515:515:515)) - (PORT datad (655:655:655) (724:724:724)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (600:600:600) (615:615:615)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datad (175:175:175) (200:200:200)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (336:336:336) (332:332:332)) + (PORT dataa (877:877:877) (922:922:922)) + (PORT datab (201:201:201) (241:241:241)) + (PORT datad (176:176:176) (202:202:202)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -37400,9 +30232,9 @@ (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1543:1543:1543)) + (PORT clk (1510:1510:1510) (1524:1524:1524)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1576:1576:1576) (1571:1571:1571)) + (PORT clrn (1550:1550:1550) (1543:1543:1543)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -37413,15 +30245,45 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~19) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[8\]\~8) (DELAY (ABSOLUTE - (PORT dataa (707:707:707) (768:768:768)) - (PORT datab (1230:1230:1230) (1291:1291:1291)) - (PORT datac (443:443:443) (506:506:506)) - (PORT datad (1066:1066:1066) (1109:1109:1109)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) + (PORT dataa (1396:1396:1396) (1442:1442:1442)) + (PORT datab (975:975:975) (1010:1010:1010)) + (PORT datad (171:171:171) (196:196:196)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1527:1527:1527)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (748:748:748) (806:806:806)) + (PORT sload (2041:2041:2041) (2133:2133:2133)) + (PORT ena (2004:2004:2004) (1967:1967:1967)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[8\]\~18) + (DELAY + (ABSOLUTE + (PORT datac (2403:2403:2403) (2576:2576:2576)) + (PORT datad (1457:1457:1457) (1514:1514:1514)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -37429,31 +30291,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~20) + (INSTANCE D\[1\]\~26) (DELAY (ABSOLUTE - (PORT dataa (752:752:752) (844:844:844)) - (PORT datab (1400:1400:1400) (1489:1489:1489)) - (PORT datac (917:917:917) (988:988:988)) - (PORT datad (854:854:854) (921:921:921)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (225:225:225) (279:279:279)) - (PORT datab (222:222:222) (261:261:261)) - (PORT datac (739:739:739) (839:839:839)) - (PORT datad (1547:1547:1547) (1637:1637:1637)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) + (PORT dataa (676:676:676) (744:744:744)) + (PORT datab (1126:1126:1126) (1130:1130:1130)) + (PORT datac (801:801:801) (888:888:888)) + (PORT datad (197:197:197) (223:223:223)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -37461,12 +30307,190 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]\~22) + (INSTANCE D\[1\]\~27) (DELAY (ABSOLUTE - (PORT datab (523:523:523) (533:533:533)) - (PORT datad (944:944:944) (998:998:998)) + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (388:388:388) (462:462:462)) + (PORT datac (1053:1053:1053) (1052:1052:1052)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[12\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1430:1430:1430) (1480:1480:1480)) + (PORT datab (338:338:338) (373:373:373)) + (PORT datad (561:561:561) (569:569:569)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1527:1527:1527)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (588:588:588) (665:665:665)) + (PORT sload (2032:2032:2032) (2084:2084:2084)) + (PORT ena (2298:2298:2298) (2265:2265:2265)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[12\]\~21) + (DELAY + (ABSOLUTE + (PORT datac (2385:2385:2385) (2515:2515:2515)) + (PORT datad (991:991:991) (1047:1047:1047)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|d1_out) + (DELAY + (ABSOLUTE + (PORT datab (383:383:383) (410:410:410)) + (PORT datad (403:403:403) (462:462:462)) (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[13\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1434:1434:1434) (1480:1480:1480)) + (PORT datab (197:197:197) (234:234:234)) + (PORT datad (194:194:194) (219:219:219)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1527:1527:1527)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (970:970:970) (1036:1036:1036)) + (PORT sload (2032:2032:2032) (2084:2084:2084)) + (PORT ena (2298:2298:2298) (2265:2265:2265)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[13\]\~20) + (DELAY + (ABSOLUTE + (PORT datab (2598:2598:2598) (2762:2762:2762)) + (PORT datad (2258:2258:2258) (2378:2378:2378)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (956:956:956) (1021:1021:1021)) + (PORT datac (666:666:666) (730:730:730)) + (PORT datad (987:987:987) (1074:1074:1074)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~34) + (DELAY + (ABSOLUTE + (PORT datab (714:714:714) (780:780:780)) + (PORT datac (700:700:700) (763:763:763)) + (PORT datad (598:598:598) (610:610:610)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (641:641:641) (679:679:679)) + (PORT datac (993:993:993) (1069:1069:1069)) + (PORT datad (693:693:693) (763:763:763)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (1487:1487:1487) (1546:1546:1546)) + (PORT datab (723:723:723) (778:778:778)) + (PORT datad (918:918:918) (979:979:979)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (245:245:245)) + (PORT datab (207:207:207) (249:249:249)) + (PORT datad (176:176:176) (202:202:202)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -37474,12 +30498,85 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]) + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT clk (1519:1519:1519) (1533:1533:1533)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) + (PORT clrn (1559:1559:1559) (1552:1552:1552)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]\~29) + (DELAY + (ABSOLUTE + (PORT datac (952:952:952) (1033:1033:1033)) + (PORT datad (659:659:659) (715:715:715)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (1019:1019:1019) (1100:1100:1100)) + (PORT datab (1231:1231:1231) (1315:1315:1315)) + (PORT datac (986:986:986) (1079:1079:1079)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (413:413:413) (493:493:493)) + (PORT datab (652:652:652) (695:695:695)) + (PORT datac (346:346:346) (367:367:367)) + (PORT datad (936:936:936) (976:976:976)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (626:626:626) (654:654:654)) + (PORT datab (942:942:942) (1015:1015:1015)) + (PORT datad (322:322:322) (342:342:342)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1533:1533:1533)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1559:1559:1559) (1552:1552:1552)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -37493,44 +30590,12 @@ (INSTANCE D\[1\]\~28) (DELAY (ABSOLUTE - (PORT dataa (670:670:670) (729:729:729)) - (PORT datab (1120:1120:1120) (1195:1195:1195)) - (PORT datac (633:633:633) (694:694:694)) - (PORT datad (216:216:216) (284:284:284)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (687:687:687) (745:745:745)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (195:195:195) (228:228:228)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~41) - (DELAY - (ABSOLUTE - (PORT dataa (484:484:484) (550:550:550)) - (PORT datab (1228:1228:1228) (1291:1291:1291)) - (PORT datac (741:741:741) (842:842:842)) - (PORT datad (842:842:842) (867:867:867)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) + (PORT dataa (605:605:605) (633:633:633)) + (PORT datab (778:778:778) (783:783:783)) + (PORT datac (214:214:214) (289:289:289)) + (PORT datad (215:215:215) (283:283:283)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -37538,30 +30603,58 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~42) + (INSTANCE z80_\|address_pins_\|abus\[0\]\~16) (DELAY (ABSOLUTE - (PORT dataa (783:783:783) (875:875:875)) - (PORT datab (913:913:913) (986:986:986)) - (PORT datac (1115:1115:1115) (1162:1162:1162)) - (PORT datad (710:710:710) (791:791:791)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (325:325:325)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT datab (956:956:956) (1016:1016:1016)) + (PORT datac (2761:2761:2761) (2948:2948:2948)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~43) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[14\]\~14) (DELAY (ABSOLUTE - (PORT dataa (358:358:358) (395:395:395)) - (PORT datac (700:700:700) (784:784:784)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (1429:1429:1429) (1479:1479:1479)) + (PORT datab (219:219:219) (258:258:258)) + (PORT datad (313:313:313) (329:329:329)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1527:1527:1527)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (582:582:582) (670:670:670)) + (PORT sload (2032:2032:2032) (2084:2084:2084)) + (PORT ena (2298:2298:2298) (2265:2265:2265)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[14\]\~23) + (DELAY + (ABSOLUTE + (PORT datac (2563:2563:2563) (2734:2734:2734)) + (PORT datad (1593:1593:1593) (1728:1728:1728)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -37571,23 +30664,71 @@ (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~40) (DELAY (ABSOLUTE - (PORT dataa (776:776:776) (868:868:868)) - (PORT datab (912:912:912) (984:984:984)) - (PORT datac (659:659:659) (735:735:735)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (997:997:997) (1075:1075:1075)) + (PORT datab (1225:1225:1225) (1305:1305:1305)) + (PORT datad (1291:1291:1291) (1368:1368:1368)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~44) + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~41) (DELAY (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datad (176:176:176) (202:202:202)) - (IOPATH dataa combout (354:354:354) (367:367:367)) + (PORT dataa (997:997:997) (1082:1082:1082)) + (PORT datab (426:426:426) (515:515:515)) + (PORT datac (174:174:174) (207:207:207)) + (PORT datad (944:944:944) (1011:1011:1011)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (784:784:784) (862:862:862)) + (PORT datab (747:747:747) (839:839:839)) + (PORT datac (563:563:563) (583:583:583)) + (PORT datad (427:427:427) (491:491:491)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (1010:1010:1010) (1060:1060:1060)) + (PORT datac (964:964:964) (1035:1035:1035)) + (PORT datad (911:911:911) (979:979:979)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (245:245:245)) + (PORT datab (652:652:652) (675:675:675)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -37598,9 +30739,9 @@ (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT clk (1518:1518:1518) (1532:1532:1532)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1572:1572:1572)) + (PORT clrn (1558:1558:1558) (1549:1549:1549)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -37611,13 +30752,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~45) + (INSTANCE ula_\|zx_keyboard_\|WideOr16\~4) (DELAY (ABSOLUTE - (PORT dataa (632:632:632) (710:710:710)) - (PORT datab (496:496:496) (580:580:580)) - (PORT datac (396:396:396) (470:470:470)) - (PORT datad (601:601:601) (643:643:643)) + (PORT dataa (1160:1160:1160) (1266:1266:1266)) + (PORT datab (314:314:314) (415:415:415)) + (PORT datac (959:959:959) (1046:1046:1046)) + (PORT datad (944:944:944) (1020:1020:1020)) (IOPATH dataa combout (354:354:354) (349:349:349)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -37625,48 +30766,16 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr16\~5) - (DELAY - (ABSOLUTE - (PORT dataa (825:825:825) (937:937:937)) - (PORT datab (941:941:941) (1038:1038:1038)) - (PORT datac (758:758:758) (878:878:878)) - (PORT datad (764:764:764) (871:871:871)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|zx_keyboard_\|WideOr16\~2) (DELAY (ABSOLUTE - (PORT dataa (820:820:820) (932:932:932)) - (PORT datab (788:788:788) (904:904:904)) - (PORT datad (763:763:763) (876:876:876)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr16\~4) - (DELAY - (ABSOLUTE - (PORT dataa (824:824:824) (935:935:935)) - (PORT datab (938:938:938) (1037:1037:1037)) - (PORT datac (757:757:757) (875:875:875)) - (PORT datad (764:764:764) (875:875:875)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT datab (310:310:310) (407:407:407)) + (PORT datac (953:953:953) (1042:1042:1042)) + (PORT datad (1132:1132:1132) (1222:1222:1222)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -37676,13 +30785,29 @@ (INSTANCE ula_\|zx_keyboard_\|WideOr16\~7) (DELAY (ABSOLUTE - (PORT dataa (232:232:232) (279:279:279)) - (PORT datab (941:941:941) (1039:1039:1039)) - (PORT datac (311:311:311) (337:337:337)) - (PORT datad (1387:1387:1387) (1504:1504:1504)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (995:995:995) (1078:1078:1078)) + (PORT datab (200:200:200) (239:239:239)) + (PORT datac (328:328:328) (353:353:353)) + (PORT datad (946:946:946) (1017:1017:1017)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr16\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1158:1158:1158) (1264:1264:1264)) + (PORT datab (315:315:315) (413:413:413)) + (PORT datac (960:960:960) (1044:1044:1044)) + (PORT datad (945:945:945) (1017:1017:1017)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -37692,10 +30817,10 @@ (INSTANCE ula_\|zx_keyboard_\|WideOr16\~6) (DELAY (ABSOLUTE - (PORT dataa (1416:1416:1416) (1544:1544:1544)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (932:932:932) (1003:1003:1003)) - (PORT datad (517:517:517) (528:528:528)) + (PORT dataa (1047:1047:1047) (1139:1139:1139)) + (PORT datab (200:200:200) (240:240:240)) + (PORT datac (957:957:957) (1042:1042:1042)) + (PORT datad (355:355:355) (386:386:386)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -37705,14 +30830,30 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~46) + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~43) (DELAY (ABSOLUTE - (PORT dataa (376:376:376) (398:398:398)) - (PORT datab (274:274:274) (359:359:359)) - (PORT datad (604:604:604) (617:617:617)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (336:336:336) (332:332:332)) + (PORT dataa (512:512:512) (589:589:589)) + (PORT datab (319:319:319) (414:414:414)) + (PORT datac (465:465:465) (559:559:559)) + (PORT datad (1192:1192:1192) (1259:1259:1259)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~44) + (DELAY + (ABSOLUTE + (PORT dataa (411:411:411) (441:441:441)) + (PORT datab (609:609:609) (638:638:638)) + (PORT datad (1081:1081:1081) (1131:1131:1131)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -37723,9 +30864,9 @@ (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1544:1544:1544)) + (PORT clk (1519:1519:1519) (1533:1533:1533)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) + (PORT clrn (1560:1560:1560) (1552:1552:1552)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -37736,602 +30877,45 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~31) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[15\]\~15) (DELAY (ABSOLUTE - (PORT dataa (1387:1387:1387) (1447:1447:1447)) - (PORT datab (411:411:411) (471:471:471)) - (PORT datac (1375:1375:1375) (1408:1408:1408)) - (PORT datad (583:583:583) (631:631:631)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (784:784:784) (804:804:804)) - (PORT datab (3348:3348:3348) (3488:3488:3488)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (1705:1705:1705) (1713:1713:1713)) - (PORT datab (1225:1225:1225) (1301:1301:1301)) - (PORT datac (636:636:636) (675:675:675)) - (PORT datad (1144:1144:1144) (1160:1160:1160)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (1504:1504:1504) (1628:1628:1628)) - (PORT datab (1226:1226:1226) (1302:1302:1302)) - (PORT datac (171:171:171) (203:203:203)) - (PORT datad (1240:1240:1240) (1368:1368:1368)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[1\]) - (DELAY - (ABSOLUTE - (PORT dataa (970:970:970) (1042:1042:1042)) - (PORT datab (636:636:636) (676:676:676)) - (PORT datac (240:240:240) (293:293:293)) - (PORT datad (1667:1667:1667) (1728:1728:1728)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1526:1526:1526) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (841:841:841) (846:846:846)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[1\]\~10) - (DELAY - (ABSOLUTE - (PORT datab (912:912:912) (931:931:931)) - (PORT datac (945:945:945) (986:986:986)) - (PORT datad (219:219:219) (254:254:254)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[1\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (253:253:253) (310:310:310)) - (PORT datab (705:705:705) (769:769:769)) - (PORT datac (170:170:170) (203:203:203)) - (PORT datad (208:208:208) (240:240:240)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|ir_\|opcode\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (195:195:195) (220:220:220)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1534:1534:1534)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1557:1557:1557)) - (PORT ena (1231:1231:1231) (1217:1217:1217)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal40\~0) - (DELAY - (ABSOLUTE - (PORT dataa (284:284:284) (380:380:380)) - (PORT datac (903:903:903) (966:966:966)) - (PORT datad (928:928:928) (982:982:982)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal21\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1410:1410:1410) (1521:1521:1521)) - (PORT datab (897:897:897) (911:911:911)) - (PORT datac (924:924:924) (1011:1011:1011)) - (PORT datad (876:876:876) (894:894:894)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~26) - (DELAY - (ABSOLUTE - (PORT dataa (1572:1572:1572) (1710:1710:1710)) - (PORT datab (2337:2337:2337) (2410:2410:2410)) - (PORT datac (671:671:671) (718:718:718)) - (PORT datad (2748:2748:2748) (2873:2873:2873)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~28) - (DELAY - (ABSOLUTE - (PORT dataa (207:207:207) (253:253:253)) - (PORT datab (232:232:232) (283:283:283)) - (PORT datac (195:195:195) (238:238:238)) - (PORT datad (371:371:371) (399:399:399)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~3) - (DELAY - (ABSOLUTE - (PORT dataa (626:626:626) (658:658:658)) - (PORT datab (427:427:427) (471:471:471)) - (PORT datac (543:543:543) (559:559:559)) - (PORT datad (1164:1164:1164) (1218:1218:1218)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1490:1490:1490) (1592:1592:1592)) - (PORT datab (438:438:438) (474:474:474)) - (PORT datac (943:943:943) (994:994:994)) - (PORT datad (211:211:211) (243:243:243)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~5) - (DELAY - (ABSOLUTE - (PORT dataa (974:974:974) (1047:1047:1047)) - (PORT datab (1110:1110:1110) (1179:1179:1179)) - (PORT datac (1261:1261:1261) (1313:1313:1313)) - (PORT datad (1359:1359:1359) (1384:1384:1384)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1101:1101:1101) (1122:1122:1122)) - (PORT datab (961:961:961) (1050:1050:1050)) - (PORT datac (1264:1264:1264) (1310:1310:1310)) - (PORT datad (1206:1206:1206) (1270:1270:1270)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1505:1505:1505) (1526:1526:1526)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (868:868:868) (865:865:865)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1606:1606:1606) (1627:1627:1627)) - (PORT datab (831:831:831) (859:859:859)) - (PORT datad (1029:1029:1029) (1028:1028:1028)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1568:1568:1568) (1597:1597:1597)) + (PORT dataa (1432:1432:1432) (1481:1481:1481)) (PORT datab (197:197:197) (236:236:236)) - (PORT datac (643:643:643) (684:684:684)) - (PORT datad (555:555:555) (558:558:558)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~9) - (DELAY - (ABSOLUTE - (PORT dataa (622:622:622) (650:650:650)) - (PORT datab (552:552:552) (565:565:565)) - (PORT datac (194:194:194) (227:227:227)) - (PORT datad (372:372:372) (397:397:397)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~21) - (DELAY - (ABSOLUTE - (PORT dataa (2257:2257:2257) (2337:2337:2337)) - (PORT datab (1549:1549:1549) (1673:1673:1673)) - (PORT datac (902:902:902) (922:922:922)) - (PORT datad (1165:1165:1165) (1178:1178:1178)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~12) - (DELAY - (ABSOLUTE - (PORT datab (230:230:230) (277:277:277)) - (PORT datac (343:343:343) (365:365:365)) - (PORT datad (369:369:369) (394:394:394)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1298:1298:1298) (1395:1395:1395)) - (PORT datab (927:927:927) (974:974:974)) - (PORT datac (1940:1940:1940) (2070:2070:2070)) - (PORT datad (2052:2052:2052) (2214:2214:2214)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~11) - (DELAY - (ABSOLUTE - (PORT dataa (855:855:855) (906:906:906)) - (PORT datab (230:230:230) (277:277:277)) - (PORT datac (196:196:196) (240:240:240)) - (PORT datad (370:370:370) (394:394:394)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1155:1155:1155) (1167:1167:1167)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (173:173:173) (206:206:206)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~17) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (255:255:255)) - (PORT datab (222:222:222) (268:268:268)) - (PORT datac (200:200:200) (236:236:236)) - (PORT datad (223:223:223) (250:250:250)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~32) - (DELAY - (ABSOLUTE - (PORT dataa (1938:1938:1938) (2062:2062:2062)) - (PORT datab (2594:2594:2594) (2695:2695:2695)) - (PORT datad (1436:1436:1436) (1528:1528:1528)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~15) - (DELAY - (ABSOLUTE - (PORT dataa (666:666:666) (720:720:720)) - (PORT datab (699:699:699) (758:758:758)) - (PORT datac (1095:1095:1095) (1090:1090:1090)) - (PORT datad (644:644:644) (692:692:692)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~16) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (254:254:254)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (611:611:611) (632:632:632)) - (PORT datad (777:777:777) (789:789:789)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~18) - (DELAY - (ABSOLUTE - (PORT dataa (845:845:845) (890:890:890)) - (PORT datab (332:332:332) (362:362:362)) - (PORT datac (372:372:372) (397:397:397)) - (PORT datad (604:604:604) (626:626:626)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1811:1811:1811) (1903:1903:1903)) - (PORT datab (921:921:921) (989:989:989)) - (PORT datac (923:923:923) (1008:1008:1008)) - (PORT datad (436:436:436) (468:468:468)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (929:929:929) (966:966:966)) - (PORT datac (902:902:902) (921:921:921)) - (PORT datad (1383:1383:1383) (1455:1455:1455)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~1) - (DELAY - (ABSOLUTE - (PORT dataa (418:418:418) (444:444:444)) - (PORT datac (192:192:192) (225:225:225)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1154:1154:1154) (1242:1242:1242)) - (PORT datab (196:196:196) (236:236:236)) - (PORT datac (593:593:593) (604:604:604)) - (PORT datad (376:376:376) (396:396:396)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1155:1155:1155) (1240:1240:1240)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datad (877:877:877) (932:932:932)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) + (PORT datad (194:194:194) (220:220:220)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[15\]) (DELAY (ABSOLUTE - (PORT clk (1511:1511:1511) (1525:1525:1525)) + (PORT clk (1523:1523:1523) (1527:1527:1527)) (PORT d (74:74:74) (91:91:91)) + (PORT asdata (720:720:720) (784:784:784)) + (PORT sload (2032:2032:2032) (2084:2084:2084)) + (PORT ena (2298:2298:2298) (2265:2265:2265)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~10) + (INSTANCE z80_\|address_pins_\|abus\[15\]\~22) (DELAY (ABSOLUTE - (PORT dataa (2446:2446:2446) (2535:2535:2535)) - (PORT datab (1615:1615:1615) (1728:1728:1728)) - (PORT datac (1769:1769:1769) (1897:1897:1897)) - (PORT datad (1666:1666:1666) (1684:1684:1684)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) + (PORT datac (2760:2760:2760) (2950:2950:2950)) + (PORT datad (1406:1406:1406) (1489:1489:1489)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -38339,77 +30923,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~11) + (INSTANCE D\[1\]\~29) (DELAY (ABSOLUTE - (PORT dataa (1432:1432:1432) (1515:1515:1515)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (1052:1052:1052) (1100:1100:1100)) - (PORT datad (1335:1335:1335) (1356:1356:1356)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1121:1121:1121) (1241:1241:1241)) - (PORT datac (884:884:884) (939:939:939)) - (PORT datad (957:957:957) (1022:1022:1022)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~9) - (DELAY - (ABSOLUTE - (PORT dataa (903:903:903) (935:935:935)) - (PORT datab (944:944:944) (1021:1021:1021)) - (PORT datac (588:588:588) (603:603:603)) - (PORT datad (537:537:537) (536:536:536)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~12) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (838:838:838) (860:860:860)) - (PORT datac (169:169:169) (202:202:202)) - (PORT datad (195:195:195) (228:228:228)) + (PORT dataa (1387:1387:1387) (1514:1514:1514)) + (PORT datab (887:887:887) (932:932:932)) + (PORT datac (647:647:647) (708:708:708)) + (PORT datad (602:602:602) (621:621:621)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~14) + (INSTANCE D\[1\]\~30) (DELAY (ABSOLUTE - (PORT dataa (1156:1156:1156) (1255:1255:1255)) - (PORT datab (257:257:257) (345:345:345)) - (PORT datac (214:214:214) (290:290:290)) - (PORT datad (580:580:580) (615:615:615)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) + (PORT dataa (1020:1020:1020) (1076:1076:1076)) + (PORT datab (365:365:365) (385:385:385)) + (PORT datac (2860:2860:2860) (3133:3133:3133)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -38417,63 +30955,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~20) + (INSTANCE ExtRamWE\~0) (DELAY (ABSOLUTE - (PORT dataa (572:572:572) (607:607:607)) - (PORT datab (199:199:199) (239:239:239)) - (PORT datac (590:590:590) (613:613:613)) - (PORT datad (600:600:600) (615:615:615)) - (IOPATH dataa combout (354:354:354) (367:367:367)) + (PORT dataa (247:247:247) (305:305:305)) + (PORT datab (2796:2796:2796) (2991:2991:2991)) + (PORT datac (551:551:551) (572:572:572)) + (PORT datad (604:604:604) (624:624:624)) + (IOPATH dataa combout (325:325:325) (320:320:320)) (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1561:1561:1561) (1706:1706:1706)) - (PORT datab (2568:2568:2568) (2670:2670:2670)) - (PORT datac (1057:1057:1057) (1083:1083:1083)) - (PORT datad (862:862:862) (898:898:898)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1089:1089:1089) (1120:1120:1120)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (1186:1186:1186) (1228:1228:1228)) - (PORT datad (564:564:564) (579:579:579)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~5) - (DELAY - (ABSOLUTE - (PORT dataa (911:911:911) (920:920:920)) - (PORT datab (219:219:219) (258:258:258)) - (PORT datac (237:237:237) (278:278:278)) - (PORT datad (594:594:594) (611:611:611)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -38481,4348 +30971,121 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~6) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode236w\[2\]) (DELAY (ABSOLUTE - (PORT dataa (948:948:948) (1036:1036:1036)) - (PORT datab (263:263:263) (310:310:310)) - (PORT datac (1393:1393:1393) (1475:1475:1475)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~7) - (DELAY - (ABSOLUTE - (PORT dataa (923:923:923) (950:950:950)) - (PORT datab (1129:1129:1129) (1199:1199:1199)) - (PORT datac (889:889:889) (932:932:932)) - (PORT datad (1015:1015:1015) (1011:1011:1011)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_set\~0) - (DELAY - (ABSOLUTE - (PORT dataa (477:477:477) (514:514:514)) - (PORT datab (896:896:896) (914:914:914)) - (PORT datac (922:922:922) (1007:1007:1007)) - (PORT datad (405:405:405) (434:434:434)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~4) - (DELAY - (ABSOLUTE - (PORT datab (1062:1062:1062) (1088:1088:1088)) - (PORT datac (208:208:208) (250:250:250)) - (PORT datad (209:209:209) (241:241:241)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~9) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (524:524:524) (539:539:539)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|flags_cf) - (DELAY - (ABSOLUTE - (PORT dataa (198:198:198) (240:240:240)) - (PORT datab (594:594:594) (613:613:613)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (567:567:567) (592:592:592)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[0\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (694:694:694) (746:746:746)) - (PORT datab (661:661:661) (721:721:721)) - (PORT datac (883:883:883) (903:903:903)) - (PORT datad (893:893:893) (916:916:916)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sw2_\|db_up\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT datac (1154:1154:1154) (1188:1188:1188)) - (PORT datad (629:629:629) (643:643:643)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[0\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (384:384:384) (408:408:408)) - (PORT datab (644:644:644) (678:678:678)) - (PORT datac (871:871:871) (896:896:896)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[0\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (701:701:701) (721:721:721)) - (PORT datab (956:956:956) (981:981:981)) - (PORT datac (172:172:172) (206:206:206)) - (PORT datad (217:217:217) (250:250:250)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~67) - (DELAY - (ABSOLUTE - (PORT dataa (688:688:688) (772:772:772)) - (PORT datac (1115:1115:1115) (1160:1160:1160)) - (PORT datad (739:739:739) (827:827:827)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~81) - (DELAY - (ABSOLUTE - (PORT dataa (785:785:785) (871:871:871)) - (PORT datab (725:725:725) (810:810:810)) - (PORT datac (1118:1118:1118) (1161:1161:1161)) - (PORT datad (711:711:711) (788:788:788)) - (IOPATH dataa combout (341:341:341) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~82) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (246:246:246)) - (PORT datab (915:915:915) (989:989:989)) - (PORT datac (1116:1116:1116) (1162:1162:1162)) - (PORT datad (329:329:329) (349:349:349)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~83) - (DELAY - (ABSOLUTE - (PORT dataa (212:212:212) (261:261:261)) - (PORT datab (199:199:199) (239:239:239)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~84) - (DELAY - (ABSOLUTE - (PORT dataa (727:727:727) (814:814:814)) - (PORT datab (981:981:981) (1068:1068:1068)) - (PORT datac (722:722:722) (831:831:831)) - (PORT datad (729:729:729) (835:835:835)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~85) - (DELAY - (ABSOLUTE - (PORT dataa (792:792:792) (903:903:903)) - (PORT datab (736:736:736) (834:834:834)) - (PORT datac (710:710:710) (811:811:811)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~86) - (DELAY - (ABSOLUTE - (PORT dataa (351:351:351) (390:390:390)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datad (338:338:338) (357:357:357)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1573:1573:1573)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~49) - (DELAY - (ABSOLUTE - (PORT dataa (1159:1159:1159) (1230:1230:1230)) - (PORT datab (724:724:724) (793:793:793)) - (PORT datac (214:214:214) (291:291:291)) - (PORT datad (550:550:550) (572:572:572)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (949:949:949) (1028:1028:1028)) - (PORT datab (779:779:779) (879:879:879)) - (PORT datac (1365:1365:1365) (1458:1458:1458)) - (PORT datad (1189:1189:1189) (1251:1251:1251)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\~76) - (DELAY - (ABSOLUTE - (PORT dataa (345:345:345) (382:382:382)) - (PORT datab (281:281:281) (364:364:364)) - (PORT datac (928:928:928) (975:975:975)) - (PORT datad (1494:1494:1494) (1585:1585:1585)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~73) - (DELAY - (ABSOLUTE - (PORT datac (740:740:740) (842:842:842)) - (PORT datad (1190:1190:1190) (1255:1255:1255)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~47) - (DELAY - (ABSOLUTE - (PORT dataa (782:782:782) (872:872:872)) - (PORT datab (728:728:728) (815:815:815)) - (PORT datac (884:884:884) (953:953:953)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (751:751:751) (844:844:844)) - (PORT datab (1502:1502:1502) (1605:1605:1605)) - (PORT datac (916:916:916) (991:991:991)) - (PORT datad (852:852:852) (919:919:919)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\~74) - (DELAY - (ABSOLUTE - (PORT dataa (588:588:588) (610:610:610)) - (PORT datab (344:344:344) (369:369:369)) - (PORT datac (1366:1366:1366) (1452:1452:1452)) - (PORT datad (1547:1547:1547) (1637:1637:1637)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~75) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (245:245:245)) - (PORT datab (201:201:201) (241:241:241)) - (PORT datac (448:448:448) (513:513:513)) - (PORT datad (841:841:841) (864:864:864)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~77) - (DELAY - (ABSOLUTE - (PORT dataa (556:556:556) (571:571:571)) - (PORT datab (335:335:335) (364:364:364)) - (PORT datad (736:736:736) (824:824:824)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]\~71) - (DELAY - (ABSOLUTE - (PORT dataa (758:758:758) (862:862:862)) - (PORT datab (729:729:729) (828:828:828)) - (PORT datac (335:335:335) (363:363:363)) - (PORT datad (1132:1132:1132) (1201:1201:1201)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]\~72) - (DELAY - (ABSOLUTE - (PORT datab (199:199:199) (239:239:239)) - (PORT datad (718:718:718) (814:814:814)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~47) - (DELAY - (ABSOLUTE - (PORT dataa (384:384:384) (455:455:455)) - (PORT datab (1124:1124:1124) (1199:1199:1199)) - (PORT datac (636:636:636) (698:698:698)) - (PORT datad (629:629:629) (680:680:680)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[0\]\~80) - (DELAY - (ABSOLUTE - (PORT dataa (1557:1557:1557) (1665:1665:1665)) - (PORT datab (981:981:981) (1035:1035:1035)) - (PORT datad (515:515:515) (529:529:529)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]\~78) - (DELAY - (ABSOLUTE - (PORT dataa (489:489:489) (569:569:569)) - (PORT datac (607:607:607) (672:672:672)) - (PORT datad (260:260:260) (335:335:335)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]\~79) - (DELAY - (ABSOLUTE - (PORT dataa (404:404:404) (428:428:428)) - (PORT datab (848:848:848) (850:850:850)) - (PORT datad (734:734:734) (821:821:821)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|key_row\~1) - (DELAY - (ABSOLUTE - (PORT datab (1472:1472:1472) (1607:1607:1607)) - (PORT datac (347:347:347) (411:411:411)) - (PORT datad (901:901:901) (962:962:962)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~48) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (220:220:220) (260:260:260)) - (PORT datac (215:215:215) (291:291:291)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|shifted\~1) - (DELAY - (ABSOLUTE - (PORT datac (1076:1076:1076) (1171:1171:1171)) - (PORT datad (1031:1031:1031) (1115:1115:1115)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~90) - (DELAY - (ABSOLUTE - (PORT dataa (1413:1413:1413) (1543:1543:1543)) - (PORT datab (788:788:788) (903:903:903)) - (PORT datac (960:960:960) (1037:1037:1037)) - (PORT datad (777:777:777) (882:882:882)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~91) - (DELAY - (ABSOLUTE - (PORT dataa (209:209:209) (256:256:256)) - (PORT datab (675:675:675) (704:704:704)) - (PORT datac (604:604:604) (622:622:622)) - (PORT datad (901:901:901) (976:976:976)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~92) - (DELAY - (ABSOLUTE - (PORT datab (968:968:968) (1057:1057:1057)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~63) - (DELAY - (ABSOLUTE - (PORT datac (654:654:654) (724:724:724)) - (PORT datad (637:637:637) (707:707:707)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr16\~3) - (DELAY - (ABSOLUTE - (PORT datab (654:654:654) (726:726:726)) - (PORT datac (693:693:693) (782:782:782)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~87) - (DELAY - (ABSOLUTE - (PORT dataa (210:210:210) (258:258:258)) - (PORT datab (473:473:473) (549:549:549)) - (PORT datac (637:637:637) (704:704:704)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~132) - (DELAY - (ABSOLUTE - (PORT dataa (230:230:230) (277:277:277)) - (PORT datab (665:665:665) (741:741:741)) - (PORT datad (650:650:650) (727:727:727)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~88) - (DELAY - (ABSOLUTE - (PORT dataa (861:861:861) (926:926:926)) - (PORT datab (223:223:223) (262:262:262)) - (PORT datac (337:337:337) (360:360:360)) - (PORT datad (543:543:543) (562:562:562)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~89) - (DELAY - (ABSOLUTE - (PORT dataa (815:815:815) (820:820:820)) - (PORT datad (946:946:946) (995:995:995)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~50) - (DELAY - (ABSOLUTE - (PORT dataa (1387:1387:1387) (1444:1444:1444)) - (PORT datab (598:598:598) (652:652:652)) - (PORT datac (1375:1375:1375) (1406:1406:1406)) - (PORT datad (218:218:218) (287:287:287)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~51) - (DELAY - (ABSOLUTE - (PORT dataa (784:784:784) (804:804:804)) - (PORT datab (3349:3349:3349) (3490:3490:3490)) - (PORT datac (171:171:171) (205:205:205)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (891:891:891) (902:902:902)) - (PORT clk (1860:1860:1860) (1887:1887:1887)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1236:1236:1236) (1280:1280:1280)) - (PORT d[1] (983:983:983) (1045:1045:1045)) - (PORT d[2] (962:962:962) (977:977:977)) - (PORT d[3] (1021:1021:1021) (1074:1074:1074)) - (PORT d[4] (2601:2601:2601) (2818:2818:2818)) - (PORT d[5] (1028:1028:1028) (1063:1063:1063)) - (PORT d[6] (994:994:994) (1056:1056:1056)) - (PORT d[7] (954:954:954) (1016:1016:1016)) - (PORT d[8] (1046:1046:1046) (1093:1093:1093)) - (PORT d[9] (998:998:998) (1055:1055:1055)) - (PORT d[10] (1047:1047:1047) (1121:1121:1121)) - (PORT d[11] (2576:2576:2576) (2762:2762:2762)) - (PORT d[12] (1307:1307:1307) (1386:1386:1386)) - (PORT clk (1857:1857:1857) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (951:951:951) (911:911:911)) - (PORT clk (1857:1857:1857) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (PORT d[0] (1484:1484:1484) (1455:1455:1455)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1820:1820:1820) (1846:1846:1846)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (980:980:980) (991:991:991)) - (PORT clk (1860:1860:1860) (1887:1887:1887)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (706:706:706) (727:727:727)) - (PORT d[1] (2392:2392:2392) (2624:2624:2624)) - (PORT d[2] (1503:1503:1503) (1540:1540:1540)) - (PORT d[3] (981:981:981) (1040:1040:1040)) - (PORT d[4] (2591:2591:2591) (2807:2807:2807)) - (PORT d[5] (3468:3468:3468) (3668:3668:3668)) - (PORT d[6] (1271:1271:1271) (1334:1334:1334)) - (PORT d[7] (3191:3191:3191) (3366:3366:3366)) - (PORT d[8] (691:691:691) (713:713:713)) - (PORT d[9] (1603:1603:1603) (1661:1661:1661)) - (PORT d[10] (1346:1346:1346) (1434:1434:1434)) - (PORT d[11] (2230:2230:2230) (2413:2413:2413)) - (PORT d[12] (1570:1570:1570) (1649:1649:1649)) - (PORT clk (1857:1857:1857) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (671:671:671) (627:627:627)) - (PORT clk (1857:1857:1857) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (PORT d[0] (1485:1485:1485) (1441:1441:1441)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1820:1820:1820) (1846:1846:1846)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1101:1101:1101) (1111:1111:1111)) - (PORT clk (1859:1859:1859) (1886:1886:1886)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (986:986:986) (1014:1014:1014)) - (PORT d[1] (3450:3450:3450) (3742:3742:3742)) - (PORT d[2] (1249:1249:1249) (1290:1290:1290)) - (PORT d[3] (1284:1284:1284) (1331:1331:1331)) - (PORT d[4] (2575:2575:2575) (2806:2806:2806)) - (PORT d[5] (3485:3485:3485) (3709:3709:3709)) - (PORT d[6] (1317:1317:1317) (1415:1415:1415)) - (PORT d[7] (1218:1218:1218) (1279:1279:1279)) - (PORT d[8] (1003:1003:1003) (1027:1027:1027)) - (PORT d[9] (1567:1567:1567) (1623:1623:1623)) - (PORT d[10] (1356:1356:1356) (1454:1454:1454)) - (PORT d[11] (2251:2251:2251) (2436:2436:2436)) - (PORT d[12] (1606:1606:1606) (1702:1702:1702)) - (PORT clk (1856:1856:1856) (1882:1882:1882)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (963:963:963) (919:919:919)) - (PORT clk (1856:1856:1856) (1882:1882:1882)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1859:1859:1859) (1886:1886:1886)) - (PORT d[0] (1702:1702:1702) (1655:1655:1655)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1819:1819:1819) (1845:1845:1845)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1004:1004:1004) (1008:1008:1008)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~55) - (DELAY - (ABSOLUTE - (PORT dataa (374:374:374) (409:409:409)) - (PORT datab (686:686:686) (752:752:752)) - (PORT datac (651:651:651) (716:716:716)) - (PORT datad (645:645:645) (655:655:655)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (325:325:325)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1183:1183:1183) (1208:1208:1208)) - (PORT clk (1850:1850:1850) (1878:1878:1878)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3642:3642:3642) (3824:3824:3824)) - (PORT d[1] (1366:1366:1366) (1493:1493:1493)) - (PORT d[2] (2003:2003:2003) (2099:2099:2099)) - (PORT d[3] (2459:2459:2459) (2585:2585:2585)) - (PORT d[4] (2200:2200:2200) (2332:2332:2332)) - (PORT d[5] (1345:1345:1345) (1450:1450:1450)) - (PORT d[6] (1456:1456:1456) (1487:1487:1487)) - (PORT d[7] (3346:3346:3346) (3494:3494:3494)) - (PORT d[8] (3607:3607:3607) (3856:3856:3856)) - (PORT d[9] (3167:3167:3167) (3306:3306:3306)) - (PORT d[10] (3154:3154:3154) (3327:3327:3327)) - (PORT d[11] (1793:1793:1793) (1891:1891:1891)) - (PORT d[12] (1416:1416:1416) (1454:1454:1454)) - (PORT clk (1847:1847:1847) (1874:1874:1874)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1620:1620:1620) (1580:1580:1580)) - (PORT clk (1847:1847:1847) (1874:1874:1874)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1878:1878:1878)) - (PORT d[0] (2766:2766:2766) (2809:2809:2809)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1879:1879:1879)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1879:1879:1879)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1879:1879:1879)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1879:1879:1879)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1810:1810:1810) (1837:1837:1837)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (995:995:995) (1000:1000:1000)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~56) - (DELAY - (ABSOLUTE - (PORT dataa (1047:1047:1047) (1075:1075:1075)) - (PORT datab (1410:1410:1410) (1504:1504:1504)) - (PORT datac (532:532:532) (545:545:545)) - (PORT datad (1173:1173:1173) (1173:1173:1173)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1641:1641:1641) (1729:1729:1729)) - (PORT clk (1857:1857:1857) (1885:1885:1885)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2872:2872:2872) (2966:2966:2966)) - (PORT d[1] (2017:2017:2017) (2182:2182:2182)) - (PORT d[2] (1954:1954:1954) (2061:2061:2061)) - (PORT d[3] (1897:1897:1897) (2022:2022:2022)) - (PORT d[4] (3021:3021:3021) (3172:3172:3172)) - (PORT d[5] (2229:2229:2229) (2391:2391:2391)) - (PORT d[6] (1711:1711:1711) (1774:1774:1774)) - (PORT d[7] (2133:2133:2133) (2250:2250:2250)) - (PORT d[8] (2427:2427:2427) (2610:2610:2610)) - (PORT d[9] (1679:1679:1679) (1785:1785:1785)) - (PORT d[10] (1442:1442:1442) (1508:1508:1508)) - (PORT d[11] (1723:1723:1723) (1780:1780:1780)) - (PORT d[12] (2286:2286:2286) (2347:2347:2347)) - (PORT clk (1854:1854:1854) (1881:1881:1881)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2567:2567:2567) (2620:2620:2620)) - (PORT clk (1854:1854:1854) (1881:1881:1881)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1885:1885:1885)) - (PORT d[0] (3733:3733:3733) (3648:3648:3648)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1886:1886:1886)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1886:1886:1886)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1886:1886:1886)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1886:1886:1886)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1812:1812:1812) (1810:1810:1810)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2034:2034:2034) (2028:2028:2028)) - (PORT clk (1822:1822:1822) (1816:1816:1816)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4393:4393:4393) (4461:4461:4461)) - (PORT d[1] (4131:4131:4131) (4181:4181:4181)) - (PORT d[2] (4247:4247:4247) (4323:4323:4323)) - (PORT d[3] (4546:4546:4546) (4614:4614:4614)) - (PORT d[4] (4322:4322:4322) (4309:4309:4309)) - (PORT d[5] (4617:4617:4617) (4651:4651:4651)) - (PORT d[6] (4408:4408:4408) (4485:4485:4485)) - (PORT d[7] (4302:4302:4302) (4274:4274:4274)) - (PORT d[8] (4572:4572:4572) (4637:4637:4637)) - (PORT d[9] (4446:4446:4446) (4691:4691:4691)) - (PORT d[10] (4705:4705:4705) (4743:4743:4743)) - (PORT d[11] (4358:4358:4358) (4390:4390:4390)) - (PORT d[12] (4507:4507:4507) (4645:4645:4645)) - (PORT clk (1818:1818:1818) (1812:1812:1812)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1822:1822:1822) (1816:1816:1816)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1823:1823:1823) (1817:1817:1817)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1823:1823:1823) (1817:1817:1817)) - (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1823:1823:1823) (1817:1817:1817)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1823:1823:1823) (1817:1817:1817)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1814:1814:1814) (1812:1812:1812)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2840:2840:2840) (2949:2949:2949)) - (PORT d[1] (1732:1732:1732) (1897:1897:1897)) - (PORT d[2] (1932:1932:1932) (2053:2053:2053)) - (PORT d[3] (1899:1899:1899) (2019:2019:2019)) - (PORT d[4] (2772:2772:2772) (2916:2916:2916)) - (PORT d[5] (2232:2232:2232) (2415:2415:2415)) - (PORT d[6] (2007:2007:2007) (2069:2069:2069)) - (PORT d[7] (2130:2130:2130) (2260:2260:2260)) - (PORT d[8] (2390:2390:2390) (2571:2571:2571)) - (PORT d[9] (1959:1959:1959) (2082:2082:2082)) - (PORT d[10] (1985:1985:1985) (2067:2067:2067)) - (PORT d[11] (2017:2017:2017) (2091:2091:2091)) - (PORT d[12] (2566:2566:2566) (2656:2656:2656)) - (PORT clk (1859:1859:1859) (1884:1884:1884)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1859:1859:1859) (1884:1884:1884)) - (PORT d[0] (2730:2730:2730) (2796:2796:2796)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1885:1885:1885)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1822:1822:1822) (1847:1847:1847)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1007:1007:1007) (1010:1010:1010)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1008:1008:1008) (1011:1011:1011)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1008:1008:1008) (1011:1011:1011)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1008:1008:1008) (1011:1011:1011)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1622:1622:1622) (1706:1706:1706)) - (PORT clk (1855:1855:1855) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2870:2870:2870) (2964:2964:2964)) - (PORT d[1] (2048:2048:2048) (2231:2231:2231)) - (PORT d[2] (1893:1893:1893) (1990:1990:1990)) - (PORT d[3] (1883:1883:1883) (2014:2014:2014)) - (PORT d[4] (3037:3037:3037) (3174:3174:3174)) - (PORT d[5] (1957:1957:1957) (2122:2122:2122)) - (PORT d[6] (1728:1728:1728) (1783:1783:1783)) - (PORT d[7] (1821:1821:1821) (1856:1856:1856)) - (PORT d[8] (2421:2421:2421) (2612:2612:2612)) - (PORT d[9] (1968:1968:1968) (2080:2080:2080)) - (PORT d[10] (2002:2002:2002) (2089:2089:2089)) - (PORT d[11] (2528:2528:2528) (2597:2597:2597)) - (PORT d[12] (2240:2240:2240) (2309:2309:2309)) - (PORT clk (1852:1852:1852) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2519:2519:2519) (2503:2503:2503)) - (PORT clk (1852:1852:1852) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1855:1855:1855) (1883:1883:1883)) - (PORT d[0] (3674:3674:3674) (3756:3756:3756)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1810:1810:1810) (1808:1808:1808)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2034:2034:2034) (2023:2023:2023)) - (PORT clk (1820:1820:1820) (1814:1814:1814)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4437:4437:4437) (4508:4508:4508)) - (PORT d[1] (4211:4211:4211) (4251:4251:4251)) - (PORT d[2] (4278:4278:4278) (4341:4341:4341)) - (PORT d[3] (4543:4543:4543) (4609:4609:4609)) - (PORT d[4] (4346:4346:4346) (4342:4342:4342)) - (PORT d[5] (4610:4610:4610) (4641:4641:4641)) - (PORT d[6] (4708:4708:4708) (4757:4757:4757)) - (PORT d[7] (4312:4312:4312) (4268:4268:4268)) - (PORT d[8] (4489:4489:4489) (4504:4504:4504)) - (PORT d[9] (4453:4453:4453) (4722:4722:4722)) - (PORT d[10] (4622:4622:4622) (4654:4654:4654)) - (PORT d[11] (4366:4366:4366) (4392:4392:4392)) - (PORT d[12] (4506:4506:4506) (4645:4645:4645)) - (PORT clk (1816:1816:1816) (1810:1810:1810)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1820:1820:1820) (1814:1814:1814)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1821:1821:1821) (1815:1815:1815)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1821:1821:1821) (1815:1815:1815)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1821:1821:1821) (1815:1815:1815)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1821:1821:1821) (1815:1815:1815)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~52) - (DELAY - (ABSOLUTE - (PORT dataa (1206:1206:1206) (1287:1287:1287)) - (PORT datab (1437:1437:1437) (1489:1489:1489)) - (PORT datac (1126:1126:1126) (1177:1177:1177)) - (PORT datad (1429:1429:1429) (1485:1485:1485)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3633:3633:3633) (3814:3814:3814)) - (PORT d[1] (2642:2642:2642) (2867:2867:2867)) - (PORT d[2] (1648:1648:1648) (1726:1726:1726)) - (PORT d[3] (2160:2160:2160) (2263:2263:2263)) - (PORT d[4] (2162:2162:2162) (2254:2254:2254)) - (PORT d[5] (1662:1662:1662) (1786:1786:1786)) - (PORT d[6] (1132:1132:1132) (1171:1171:1171)) - (PORT d[7] (1160:1160:1160) (1190:1190:1190)) - (PORT d[8] (2171:2171:2171) (2353:2353:2353)) - (PORT d[9] (2266:2266:2266) (2413:2413:2413)) - (PORT d[10] (2562:2562:2562) (2693:2693:2693)) - (PORT d[11] (915:915:915) (961:961:961)) - (PORT d[12] (1750:1750:1750) (1775:1775:1775)) - (PORT clk (1847:1847:1847) (1874:1874:1874)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1847:1847:1847) (1874:1874:1874)) - (PORT d[0] (3453:3453:3453) (3330:3330:3330)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1875:1875:1875)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1810:1810:1810) (1837:1837:1837)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (995:995:995) (1000:1000:1000)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~53) - (DELAY - (ABSOLUTE - (PORT dataa (1208:1208:1208) (1217:1217:1217)) - (PORT datab (1079:1079:1079) (1088:1088:1088)) - (PORT datac (181:181:181) (219:219:219)) - (PORT datad (1384:1384:1384) (1408:1408:1408)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~54) - (DELAY - (ABSOLUTE - (PORT dataa (1502:1502:1502) (1614:1614:1614)) - (PORT datab (951:951:951) (1007:1007:1007)) - (PORT datac (180:180:180) (216:216:216)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (325:325:325)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~106) - (DELAY - (ABSOLUTE - (PORT dataa (678:678:678) (778:778:778)) - (PORT datab (1164:1164:1164) (1255:1255:1255)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (174:174:174) (198:198:198)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~57) - (DELAY - (ABSOLUTE - (PORT dataa (1972:1972:1972) (2064:2064:2064)) - (PORT datab (1148:1148:1148) (1200:1200:1200)) - (PORT datac (180:180:180) (216:216:216)) - (PORT datad (843:843:843) (868:868:868)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~58) - (DELAY - (ABSOLUTE - (PORT dataa (1975:1975:1975) (2066:2066:2066)) - (PORT datab (647:647:647) (708:708:708)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (1634:1634:1634) (1673:1673:1673)) - (IOPATH dataa combout (371:371:371) (376:376:376)) + (PORT dataa (1195:1195:1195) (1214:1214:1214)) + (PORT datab (243:243:243) (298:298:298)) + (PORT datac (570:570:570) (596:596:596)) + (PORT datad (1615:1615:1615) (1654:1654:1654)) + (IOPATH dataa combout (324:324:324) (328:328:328)) (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[0\]) - (DELAY - (ABSOLUTE - (PORT dataa (977:977:977) (1044:1044:1044)) - (PORT datab (918:918:918) (964:964:964)) - (PORT datac (244:244:244) (297:297:297)) - (PORT datad (1588:1588:1588) (1606:1606:1606)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[0\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|rden_decode\|w_anode284w\[2\]\~0) (DELAY (ABSOLUTE - (PORT clk (1526:1526:1526) (1531:1531:1531)) + (PORT datab (1632:1632:1632) (1772:1772:1772)) + (PORT datac (2564:2564:2564) (2736:2736:2736)) + (PORT datad (2259:2259:2259) (2383:2383:2383)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1257:1257:1257) (1294:1294:1294)) + (PORT datab (341:341:341) (369:369:369)) + (PORT datad (195:195:195) (220:220:220)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1537:1537:1537) (1535:1535:1535)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (841:841:841) (846:846:846)) + (PORT asdata (982:982:982) (1034:1034:1034)) + (PORT sload (1782:1782:1782) (1900:1900:1900)) + (PORT ena (1716:1716:1716) (1679:1679:1679)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[0\]\~16) - (DELAY - (ABSOLUTE - (PORT datab (393:393:393) (423:423:423)) - (PORT datac (407:407:407) (468:468:468)) - (PORT datad (674:674:674) (692:692:692)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[0\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (981:981:981) (1004:1004:1004)) - (PORT datab (1377:1377:1377) (1376:1376:1376)) - (PORT datac (889:889:889) (939:939:939)) - (PORT datad (892:892:892) (894:894:894)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1519:1519:1519) (1532:1532:1532)) - (PORT asdata (1523:1523:1523) (1555:1555:1555)) - (PORT clrn (1576:1576:1576) (1555:1555:1555)) - (PORT ena (1506:1506:1506) (1484:1484:1484)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK + (HOLD sload (posedge clk) (157:157:157)) (HOLD asdata (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal63\~0) + (INSTANCE z80_\|address_pins_\|abus\[1\]\~25) (DELAY (ABSOLUTE - (PORT dataa (1988:1988:1988) (2128:2128:2128)) - (PORT datab (1534:1534:1534) (1633:1633:1633)) - (PORT datac (227:227:227) (272:272:272)) - (PORT datad (1108:1108:1108) (1149:1149:1149)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_daa) - (DELAY - (ABSOLUTE - (PORT dataa (1494:1494:1494) (1599:1599:1599)) - (PORT datab (1480:1480:1480) (1588:1588:1588)) - (PORT datac (1844:1844:1844) (1910:1910:1910)) - (PORT datad (400:400:400) (434:434:434)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|SYNTHESIZED_WIRE_2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (357:357:357) (496:496:496)) - (PORT datab (712:712:712) (746:746:746)) - (PORT datac (1434:1434:1434) (1535:1535:1535)) - (PORT datad (1300:1300:1300) (1393:1393:1393)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (684:684:684) (734:734:734)) - (PORT datac (1154:1154:1154) (1186:1186:1186)) - (PORT datad (918:918:918) (942:942:942)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (198:198:198) (241:241:241)) - (PORT datab (661:661:661) (720:720:720)) - (PORT datac (871:871:871) (900:900:900)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[4\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (530:530:530) (558:558:558)) - (PORT datab (903:903:903) (932:932:932)) - (PORT datac (591:591:591) (604:604:604)) - (PORT datad (1156:1156:1156) (1185:1185:1185)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[4\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (655:655:655) (673:673:673)) - (PORT datab (955:955:955) (981:981:981)) - (PORT datac (646:646:646) (694:694:694)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[4\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (897:897:897) (931:931:931)) - (PORT datab (243:243:243) (291:291:291)) - (PORT datac (626:626:626) (680:680:680)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~119) - (DELAY - (ABSOLUTE - (PORT dataa (757:757:757) (859:859:859)) - (PORT datab (722:722:722) (821:821:821)) - (PORT datac (1142:1142:1142) (1227:1227:1227)) - (PORT datad (912:912:912) (978:978:978)) - (IOPATH dataa combout (341:341:341) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~120) - (DELAY - (ABSOLUTE - (PORT dataa (678:678:678) (707:707:707)) - (PORT datab (345:345:345) (371:371:371)) - (PORT datac (711:711:711) (812:812:812)) - (PORT datad (733:733:733) (834:834:834)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~95) - (DELAY - (ABSOLUTE - (PORT dataa (792:792:792) (904:904:904)) - (PORT datac (708:708:708) (801:801:801)) - (PORT datad (1136:1136:1136) (1221:1221:1221)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~121) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (243:243:243)) - (PORT datad (180:180:180) (209:209:209)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1573:1573:1573)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~117) - (DELAY - (ABSOLUTE - (PORT dataa (444:444:444) (535:535:535)) - (PORT datab (659:659:659) (735:735:735)) - (PORT datad (723:723:723) (804:804:804)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~136) - (DELAY - (ABSOLUTE - (PORT dataa (563:563:563) (585:585:585)) - (PORT datab (451:451:451) (519:519:519)) - (PORT datad (651:651:651) (723:723:723)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~130) - (DELAY - (ABSOLUTE - (PORT dataa (680:680:680) (763:763:763)) - (PORT datab (663:663:663) (692:692:692)) - (PORT datad (833:833:833) (881:881:881)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~118) - (DELAY - (ABSOLUTE - (PORT dataa (794:794:794) (905:905:905)) - (PORT datab (628:628:628) (650:650:650)) - (PORT datad (616:616:616) (634:634:634)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1573:1573:1573)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~78) - (DELAY - (ABSOLUTE - (PORT dataa (894:894:894) (906:906:906)) - (PORT datab (874:874:874) (902:902:902)) - (PORT datac (610:610:610) (671:671:671)) - (PORT datad (657:657:657) (708:708:708)) - (IOPATH dataa combout (303:303:303) (308:308:308)) + (PORT datab (598:598:598) (658:658:658)) + (PORT datac (2048:2048:2048) (2144:2144:2144)) (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~126) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[2\]\~2) (DELAY (ABSOLUTE - (PORT dataa (822:822:822) (934:934:934)) - (PORT datab (697:697:697) (727:727:727)) - (PORT datac (960:960:960) (1039:1039:1039)) - (PORT datad (1384:1384:1384) (1501:1501:1501)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~128) - (DELAY - (ABSOLUTE - (PORT dataa (970:970:970) (1046:1046:1046)) - (PORT datab (788:788:788) (902:902:902)) - (PORT datac (903:903:903) (997:997:997)) - (PORT datad (767:767:767) (878:878:878)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~129) - (DELAY - (ABSOLUTE - (PORT dataa (352:352:352) (385:385:385)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datad (904:904:904) (977:977:977)) + (PORT dataa (1257:1257:1257) (1298:1298:1298)) + (PORT datab (384:384:384) (413:413:413)) + (PORT datad (311:311:311) (330:330:330)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[2\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1537:1537:1537) (1535:1535:1535)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1573:1573:1573)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~127) - (DELAY - (ABSOLUTE - (PORT dataa (601:601:601) (636:636:636)) - (PORT datab (964:964:964) (1050:1050:1050)) - (PORT datad (568:568:568) (584:584:584)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Equal0\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1590:1590:1590) (1687:1687:1687)) - (PORT datac (744:744:744) (848:848:848)) - (PORT datad (713:713:713) (799:799:799)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~51) - (DELAY - (ABSOLUTE - (PORT dataa (707:707:707) (730:730:730)) - (PORT datab (1231:1231:1231) (1291:1291:1291)) - (PORT datac (920:920:920) (989:989:989)) - (PORT datad (331:331:331) (350:350:350)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~125) - (DELAY - (ABSOLUTE - (PORT dataa (210:210:210) (260:260:260)) - (PORT datab (965:965:965) (1053:1053:1053)) - (PORT datad (361:361:361) (388:388:388)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~79) - (DELAY - (ABSOLUTE - (PORT dataa (1349:1349:1349) (1392:1392:1392)) - (PORT datab (1223:1223:1223) (1278:1278:1278)) - (PORT datac (216:216:216) (293:293:293)) - (PORT datad (217:217:217) (286:286:286)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~122) - (DELAY - (ABSOLUTE - (PORT dataa (447:447:447) (536:536:536)) - (PORT datab (659:659:659) (734:734:734)) - (PORT datad (725:725:725) (804:804:804)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~123) - (DELAY - (ABSOLUTE - (PORT dataa (585:585:585) (608:608:608)) - (PORT datab (728:728:728) (826:826:826)) - (PORT datac (1546:1546:1546) (1656:1656:1656)) - (PORT datad (580:580:580) (596:596:596)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~124) - (DELAY - (ABSOLUTE - (PORT dataa (656:656:656) (689:689:689)) - (PORT datab (745:745:745) (852:852:852)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|key_row\~3) - (DELAY - (ABSOLUTE - (PORT datab (1510:1510:1510) (1603:1603:1603)) - (PORT datac (869:869:869) (961:961:961)) - (PORT datad (218:218:218) (287:287:287)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~80) - (DELAY - (ABSOLUTE - (PORT dataa (377:377:377) (453:453:453)) - (PORT datab (632:632:632) (659:659:659)) - (PORT datac (1349:1349:1349) (1408:1408:1408)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~111) - (DELAY - (ABSOLUTE - (PORT dataa (793:793:793) (903:903:903)) - (PORT datac (702:702:702) (794:794:794)) - (PORT datad (1130:1130:1130) (1214:1214:1214)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~97) - (DELAY - (ABSOLUTE - (PORT dataa (1164:1164:1164) (1266:1266:1266)) - (PORT datab (724:724:724) (824:824:824)) - (PORT datac (642:642:642) (670:670:670)) - (PORT datad (909:909:909) (977:977:977)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~116) - (DELAY - (ABSOLUTE - (PORT dataa (383:383:383) (411:411:411)) - (PORT datab (222:222:222) (261:261:261)) - (PORT datad (183:183:183) (213:213:213)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1573:1573:1573)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]\~115) - (DELAY - (ABSOLUTE - (PORT dataa (585:585:585) (605:605:605)) - (PORT datab (363:363:363) (394:394:394)) - (PORT datad (717:717:717) (811:811:811)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~77) - (DELAY - (ABSOLUTE - (PORT dataa (1136:1136:1136) (1168:1168:1168)) - (PORT datab (1142:1142:1142) (1214:1214:1214)) - (PORT datac (639:639:639) (698:698:698)) - (PORT datad (218:218:218) (287:287:287)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~81) - (DELAY - (ABSOLUTE - (PORT dataa (1616:1616:1616) (1662:1662:1662)) - (PORT datab (198:198:198) (236:236:236)) - (PORT datac (173:173:173) (206:206:206)) - (PORT datad (171:171:171) (196:196:196)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3349:3349:3349) (3565:3565:3565)) - (PORT d[1] (1605:1605:1605) (1743:1743:1743)) - (PORT d[2] (2398:2398:2398) (2522:2522:2522)) - (PORT d[3] (1878:1878:1878) (1993:1993:1993)) - (PORT d[4] (1904:1904:1904) (2011:2011:2011)) - (PORT d[5] (2072:2072:2072) (2262:2262:2262)) - (PORT d[6] (2267:2267:2267) (2352:2352:2352)) - (PORT d[7] (2156:2156:2156) (2268:2268:2268)) - (PORT d[8] (2927:2927:2927) (3117:3117:3117)) - (PORT d[9] (2257:2257:2257) (2323:2323:2323)) - (PORT d[10] (4015:4015:4015) (4256:4256:4256)) - (PORT d[11] (1788:1788:1788) (1883:1883:1883)) - (PORT d[12] (2324:2324:2324) (2423:2423:2423)) - (PORT clk (1848:1848:1848) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1875:1875:1875)) - (PORT d[0] (2435:2435:2435) (2530:2530:2530)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1849:1849:1849) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1811:1811:1811) (1838:1838:1838)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1496:1496:1496) (1570:1570:1570)) - (PORT clk (1848:1848:1848) (1876:1876:1876)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3471:3471:3471) (3598:3598:3598)) - (PORT d[1] (1681:1681:1681) (1841:1841:1841)) - (PORT d[2] (1803:1803:1803) (1868:1868:1868)) - (PORT d[3] (2137:2137:2137) (2245:2245:2245)) - (PORT d[4] (2206:2206:2206) (2306:2306:2306)) - (PORT d[5] (1648:1648:1648) (1787:1787:1787)) - (PORT d[6] (1447:1447:1447) (1468:1468:1468)) - (PORT d[7] (1455:1455:1455) (1504:1504:1504)) - (PORT d[8] (2907:2907:2907) (3106:3106:3106)) - (PORT d[9] (2261:2261:2261) (2404:2404:2404)) - (PORT d[10] (2303:2303:2303) (2432:2432:2432)) - (PORT d[11] (2139:2139:2139) (2251:2251:2251)) - (PORT d[12] (2022:2022:2022) (2077:2077:2077)) - (PORT clk (1845:1845:1845) (1872:1872:1872)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2862:2862:2862) (2854:2854:2854)) - (PORT clk (1845:1845:1845) (1872:1872:1872)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1876:1876:1876)) - (PORT d[0] (4272:4272:4272) (4376:4376:4376)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1849:1849:1849) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1849:1849:1849) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1849:1849:1849) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1849:1849:1849) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1803:1803:1803) (1801:1801:1801)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1739:1739:1739) (1715:1715:1715)) - (PORT clk (1813:1813:1813) (1807:1807:1807)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4403:4403:4403) (4442:4442:4442)) - (PORT d[1] (4232:4232:4232) (4305:4305:4305)) - (PORT d[2] (4291:4291:4291) (4336:4336:4336)) - (PORT d[3] (4528:4528:4528) (4564:4564:4564)) - (PORT d[4] (4637:4637:4637) (4664:4664:4664)) - (PORT d[5] (4315:4315:4315) (4358:4358:4358)) - (PORT d[6] (4706:4706:4706) (4798:4798:4798)) - (PORT d[7] (4277:4277:4277) (4349:4349:4349)) - (PORT d[8] (4511:4511:4511) (4526:4526:4526)) - (PORT d[9] (4469:4469:4469) (4738:4738:4738)) - (PORT d[10] (4368:4368:4368) (4407:4407:4407)) - (PORT d[11] (4392:4392:4392) (4374:4374:4374)) - (PORT d[12] (4337:4337:4337) (4342:4342:4342)) - (PORT clk (1809:1809:1809) (1803:1803:1803)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1813:1813:1813) (1807:1807:1807)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1814:1814:1814) (1808:1808:1808)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1814:1814:1814) (1808:1808:1808)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1814:1814:1814) (1808:1808:1808)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1814:1814:1814) (1808:1808:1808)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4186:4186:4186) (4425:4425:4425)) - (PORT d[1] (2884:2884:2884) (3131:3131:3131)) - (PORT d[2] (2708:2708:2708) (2819:2819:2819)) - (PORT d[3] (2283:2283:2283) (2458:2458:2458)) - (PORT d[4] (2517:2517:2517) (2710:2710:2710)) - (PORT d[5] (2529:2529:2529) (2722:2722:2722)) - (PORT d[6] (1890:1890:1890) (2008:2008:2008)) - (PORT d[7] (2314:2314:2314) (2443:2443:2443)) - (PORT d[8] (3115:3115:3115) (3376:3376:3376)) - (PORT d[9] (2627:2627:2627) (2762:2762:2762)) - (PORT d[10] (4822:4822:4822) (5078:5078:5078)) - (PORT d[11] (1897:1897:1897) (2050:2050:2050)) - (PORT d[12] (2209:2209:2209) (2354:2354:2354)) - (PORT clk (1856:1856:1856) (1882:1882:1882)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1882:1882:1882)) - (PORT d[0] (3638:3638:3638) (3555:3555:3555)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1883:1883:1883)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1819:1819:1819) (1845:1845:1845)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1004:1004:1004) (1008:1008:1008)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1555:1555:1555) (1647:1647:1647)) - (PORT clk (1849:1849:1849) (1877:1877:1877)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3013:3013:3013) (3193:3193:3193)) - (PORT d[1] (2314:2314:2314) (2501:2501:2501)) - (PORT d[2] (2182:2182:2182) (2293:2293:2293)) - (PORT d[3] (1900:1900:1900) (2029:2029:2029)) - (PORT d[4] (2430:2430:2430) (2538:2538:2538)) - (PORT d[5] (1950:1950:1950) (2108:2108:2108)) - (PORT d[6] (1747:1747:1747) (1762:1762:1762)) - (PORT d[7] (2376:2376:2376) (2506:2506:2506)) - (PORT d[8] (2895:2895:2895) (3077:3077:3077)) - (PORT d[9] (1983:1983:1983) (2113:2113:2113)) - (PORT d[10] (2017:2017:2017) (2125:2125:2125)) - (PORT d[11] (2437:2437:2437) (2546:2546:2546)) - (PORT d[12] (2561:2561:2561) (2626:2626:2626)) - (PORT clk (1846:1846:1846) (1873:1873:1873)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2577:2577:2577) (2632:2632:2632)) - (PORT clk (1846:1846:1846) (1873:1873:1873)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1849:1849:1849) (1877:1877:1877)) - (PORT d[0] (4055:4055:4055) (3952:3952:3952)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1878:1878:1878)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1878:1878:1878)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1878:1878:1878)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1878:1878:1878)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1804:1804:1804) (1802:1802:1802)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2048:2048:2048) (2021:2021:2021)) - (PORT clk (1814:1814:1814) (1808:1808:1808)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4402:4402:4402) (4453:4453:4453)) - (PORT d[1] (4222:4222:4222) (4285:4285:4285)) - (PORT d[2] (4296:4296:4296) (4356:4356:4356)) - (PORT d[3] (4467:4467:4467) (4510:4510:4510)) - (PORT d[4] (4361:4361:4361) (4378:4378:4378)) - (PORT d[5] (4645:4645:4645) (4676:4676:4676)) - (PORT d[6] (4445:4445:4445) (4533:4533:4533)) - (PORT d[7] (4329:4329:4329) (4398:4398:4398)) - (PORT d[8] (4517:4517:4517) (4536:4536:4536)) - (PORT d[9] (4456:4456:4456) (4702:4702:4702)) - (PORT d[10] (4317:4317:4317) (4323:4323:4323)) - (PORT d[11] (4684:4684:4684) (4714:4714:4714)) - (PORT d[12] (4438:4438:4438) (4553:4553:4553)) - (PORT clk (1810:1810:1810) (1804:1804:1804)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1814:1814:1814) (1808:1808:1808)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1815:1815:1815) (1809:1809:1809)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1815:1815:1815) (1809:1809:1809)) - (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1815:1815:1815) (1809:1809:1809)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1815:1815:1815) (1809:1809:1809)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1806:1806:1806) (1804:1804:1804)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Selector4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1163:1163:1163) (1219:1219:1219)) - (PORT datab (947:947:947) (1002:1002:1002)) - (PORT datac (1385:1385:1385) (1418:1418:1418)) - (PORT datad (1436:1436:1436) (1475:1475:1475)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Selector4\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1314:1314:1314) (1369:1369:1369)) - (PORT datab (951:951:951) (1008:1008:1008)) - (PORT datac (1440:1440:1440) (1502:1502:1502)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (901:901:901) (939:939:939)) - (PORT clk (1851:1851:1851) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3349:3349:3349) (3527:3527:3527)) - (PORT d[1] (1734:1734:1734) (1904:1904:1904)) - (PORT d[2] (1993:1993:1993) (2068:2068:2068)) - (PORT d[3] (2163:2163:2163) (2257:2257:2257)) - (PORT d[4] (1834:1834:1834) (1918:1918:1918)) - (PORT d[5] (1363:1363:1363) (1460:1460:1460)) - (PORT d[6] (1449:1449:1449) (1474:1474:1474)) - (PORT d[7] (3354:3354:3354) (3503:3503:3503)) - (PORT d[8] (2447:2447:2447) (2653:2653:2653)) - (PORT d[9] (3517:3517:3517) (3682:3682:3682)) - (PORT d[10] (2917:2917:2917) (3102:3102:3102)) - (PORT d[11] (1485:1485:1485) (1553:1553:1553)) - (PORT d[12] (1460:1460:1460) (1502:1502:1502)) - (PORT clk (1848:1848:1848) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3345:3345:3345) (3355:3355:3355)) - (PORT clk (1848:1848:1848) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1879:1879:1879)) - (PORT d[0] (1944:1944:1944) (1906:1906:1906)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1811:1811:1811) (1838:1838:1838)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1470:1470:1470) (1515:1515:1515)) - (PORT clk (1841:1841:1841) (1869:1869:1869)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3671:3671:3671) (3886:3886:3886)) - (PORT d[1] (1690:1690:1690) (1854:1854:1854)) - (PORT d[2] (3275:3275:3275) (3430:3430:3430)) - (PORT d[3] (2158:2158:2158) (2262:2262:2262)) - (PORT d[4] (2542:2542:2542) (2676:2676:2676)) - (PORT d[5] (1672:1672:1672) (1804:1804:1804)) - (PORT d[6] (1797:1797:1797) (1871:1871:1871)) - (PORT d[7] (1692:1692:1692) (1762:1762:1762)) - (PORT d[8] (3323:3323:3323) (3550:3550:3550)) - (PORT d[9] (2846:2846:2846) (2959:2959:2959)) - (PORT d[10] (3476:3476:3476) (3688:3688:3688)) - (PORT d[11] (1790:1790:1790) (1894:1894:1894)) - (PORT d[12] (1727:1727:1727) (1788:1788:1788)) - (PORT clk (1838:1838:1838) (1865:1865:1865)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1941:1941:1941) (1913:1913:1913)) - (PORT clk (1838:1838:1838) (1865:1865:1865)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1841:1841:1841) (1869:1869:1869)) - (PORT d[0] (2779:2779:2779) (2775:2775:2775)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1842:1842:1842) (1870:1870:1870)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1842:1842:1842) (1870:1870:1870)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1842:1842:1842) (1870:1870:1870)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1842:1842:1842) (1870:1870:1870)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1801:1801:1801) (1828:1828:1828)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (986:986:986) (991:991:991)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (987:987:987) (992:992:992)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (987:987:987) (992:992:992)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (987:987:987) (992:992:992)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1247:1247:1247) (1305:1305:1305)) - (PORT clk (1851:1851:1851) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3351:3351:3351) (3542:3542:3542)) - (PORT d[1] (1331:1331:1331) (1442:1442:1442)) - (PORT d[2] (1949:1949:1949) (2052:2052:2052)) - (PORT d[3] (1549:1549:1549) (1617:1617:1617)) - (PORT d[4] (1868:1868:1868) (1957:1957:1957)) - (PORT d[5] (1641:1641:1641) (1721:1721:1721)) - (PORT d[6] (1178:1178:1178) (1228:1228:1228)) - (PORT d[7] (1451:1451:1451) (1507:1507:1507)) - (PORT d[8] (2507:2507:2507) (2697:2697:2697)) - (PORT d[9] (3505:3505:3505) (3649:3649:3649)) - (PORT d[10] (2878:2878:2878) (3044:3044:3044)) - (PORT d[11] (1237:1237:1237) (1307:1307:1307)) - (PORT d[12] (1108:1108:1108) (1125:1125:1125)) - (PORT clk (1848:1848:1848) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2872:2872:2872) (2909:2909:2909)) - (PORT clk (1848:1848:1848) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1879:1879:1879)) - (PORT d[0] (3248:3248:3248) (3325:3325:3325)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1811:1811:1811) (1838:1838:1838)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1750:1750:1750) (1835:1835:1835)) - (PORT clk (1850:1850:1850) (1878:1878:1878)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3365:3365:3365) (3581:3581:3581)) - (PORT d[1] (1702:1702:1702) (1864:1864:1864)) - (PORT d[2] (2694:2694:2694) (2816:2816:2816)) - (PORT d[3] (2143:2143:2143) (2257:2257:2257)) - (PORT d[4] (2191:2191:2191) (2314:2314:2314)) - (PORT d[5] (2392:2392:2392) (2607:2607:2607)) - (PORT d[6] (2106:2106:2106) (2209:2209:2209)) - (PORT d[7] (2467:2467:2467) (2597:2597:2597)) - (PORT d[8] (3036:3036:3036) (3248:3248:3248)) - (PORT d[9] (2577:2577:2577) (2669:2669:2669)) - (PORT d[10] (3785:3785:3785) (4034:4034:4034)) - (PORT d[11] (1778:1778:1778) (1856:1856:1856)) - (PORT d[12] (2315:2315:2315) (2396:2396:2396)) - (PORT clk (1847:1847:1847) (1874:1874:1874)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2267:2267:2267) (2265:2265:2265)) - (PORT clk (1847:1847:1847) (1874:1874:1874)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1878:1878:1878)) - (PORT d[0] (2685:2685:2685) (2695:2695:2695)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1879:1879:1879)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1879:1879:1879)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1879:1879:1879)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1879:1879:1879)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1810:1810:1810) (1837:1837:1837)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (995:995:995) (1000:1000:1000)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1829:1829:1829) (1854:1854:1854)) - (PORT datab (1177:1177:1177) (1181:1181:1181)) - (PORT datad (1696:1696:1696) (1748:1748:1748)) - (IOPATH dataa combout (341:341:341) (320:320:320)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1465:1465:1465) (1535:1535:1535)) - (PORT datab (1484:1484:1484) (1501:1501:1501)) - (PORT datac (2124:2124:2124) (2189:2189:2189)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~109) - (DELAY - (ABSOLUTE - (PORT dataa (680:680:680) (777:777:777)) - (PORT datab (1164:1164:1164) (1255:1255:1255)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (173:173:173) (197:197:197)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~97) - (DELAY - (ABSOLUTE - (PORT dataa (887:887:887) (916:916:916)) - (PORT datab (1551:1551:1551) (1605:1605:1605)) - (PORT datac (1462:1462:1462) (1538:1538:1538)) - (PORT datad (182:182:182) (211:211:211)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~98) - (DELAY - (ABSOLUTE - (PORT dataa (1168:1168:1168) (1244:1244:1244)) - (PORT datab (1665:1665:1665) (1708:1708:1708)) - (PORT datac (1463:1463:1463) (1538:1538:1538)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[4\]) - (DELAY - (ABSOLUTE - (PORT dataa (970:970:970) (1037:1037:1037)) - (PORT datab (1506:1506:1506) (1524:1524:1524)) - (PORT datac (236:236:236) (289:289:289)) - (PORT datad (1153:1153:1153) (1165:1165:1165)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1526:1526:1526) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (841:841:841) (846:846:846)) + (PORT asdata (588:588:588) (666:666:666)) + (PORT sload (1782:1782:1782) (1900:1900:1900)) + (PORT ena (1716:1716:1716) (1679:1679:1679)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[4\]\~18) + (INSTANCE z80_\|address_pins_\|abus\[2\]\~26) (DELAY (ABSOLUTE - (PORT dataa (395:395:395) (471:471:471)) - (PORT datab (388:388:388) (422:422:422)) - (PORT datad (671:671:671) (693:693:693)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[4\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (981:981:981) (1007:1007:1007)) - (PORT datab (922:922:922) (965:965:965)) - (PORT datac (888:888:888) (938:938:938)) - (PORT datad (898:898:898) (913:913:913)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1541:1541:1541)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1571:1571:1571) (1550:1550:1550)) - (PORT ena (1479:1479:1479) (1488:1488:1488)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal21\~0) - (DELAY - (ABSOLUTE - (PORT datac (1440:1440:1440) (1546:1546:1546)) - (PORT datad (1464:1464:1464) (1552:1552:1552)) + (PORT datac (2048:2048:2048) (2143:2143:2143)) + (PORT datad (238:238:238) (306:306:306)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -42830,109 +31093,91 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~5) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[3\]\~3) (DELAY (ABSOLUTE - (PORT dataa (1381:1381:1381) (1434:1434:1434)) - (PORT datab (981:981:981) (1038:1038:1038)) - (PORT datac (1636:1636:1636) (1757:1757:1757)) - (PORT datad (1217:1217:1217) (1298:1298:1298)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1286:1286:1286) (1367:1367:1367)) - (PORT datab (1528:1528:1528) (1599:1599:1599)) - (PORT datac (821:821:821) (830:830:830)) - (PORT datad (201:201:201) (229:229:229)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~3) - (DELAY - (ABSOLUTE - (PORT datab (1536:1536:1536) (1647:1647:1647)) - (PORT datac (1349:1349:1349) (1441:1441:1441)) - (PORT datad (2442:2442:2442) (2633:2633:2633)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~4) - (DELAY - (ABSOLUTE - (PORT dataa (863:863:863) (915:915:915)) - (PORT datab (925:925:925) (953:953:953)) - (PORT datac (1717:1717:1717) (1764:1764:1764)) - (PORT datad (174:174:174) (199:199:199)) + (PORT dataa (753:753:753) (767:767:767)) + (PORT datab (379:379:379) (407:407:407)) + (PORT datad (1216:1216:1216) (1251:1251:1251)) (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~5) - (DELAY - (ABSOLUTE - (PORT dataa (426:426:426) (455:455:455)) - (PORT datab (1184:1184:1184) (1238:1238:1238)) - (PORT datac (171:171:171) (205:205:205)) - (PORT datad (360:360:360) (383:383:383)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~11) - (DELAY - (ABSOLUTE - (PORT dataa (931:931:931) (953:953:953)) - (PORT datab (618:618:618) (660:660:660)) - (PORT datac (888:888:888) (936:936:936)) - (PORT datad (892:892:892) (905:905:905)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~12) - (DELAY - (ABSOLUTE - (PORT dataa (2004:2004:2004) (2054:2054:2054)) - (PORT datab (1141:1141:1141) (1140:1140:1140)) - (PORT datac (850:850:850) (856:856:856)) - (PORT datad (641:641:641) (681:681:681)) - (IOPATH dataa combout (324:324:324) (328:328:328)) (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1537:1537:1537) (1535:1535:1535)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (588:588:588) (666:666:666)) + (PORT sload (1782:1782:1782) (1900:1900:1900)) + (PORT ena (1716:1716:1716) (1679:1679:1679)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[3\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (401:401:401) (476:476:476)) + (PORT datac (2051:2051:2051) (2145:2145:2145)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[4\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1400:1400:1400) (1446:1446:1446)) + (PORT datab (928:928:928) (953:953:953)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1527:1527:1527)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (712:712:712) (784:784:784)) + (PORT sload (2041:2041:2041) (2133:2133:2133)) + (PORT ena (2004:2004:2004) (1967:1967:1967)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[4\]\~28) + (DELAY + (ABSOLUTE + (PORT datac (2392:2392:2392) (2522:2522:2522)) + (PORT datad (237:237:237) (305:305:305)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -42940,304 +31185,160 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~13) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[5\]\~5) (DELAY (ABSOLUTE - (PORT dataa (201:201:201) (243:243:243)) - (PORT datab (596:596:596) (607:607:607)) - (PORT datac (532:532:532) (546:546:546)) - (PORT datad (180:180:180) (208:208:208)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1573:1573:1573) (1667:1667:1667)) - (PORT datab (881:881:881) (895:895:895)) - (PORT datac (1465:1465:1465) (1505:1505:1505)) - (PORT datad (1073:1073:1073) (1063:1063:1063)) + (PORT dataa (1400:1400:1400) (1447:1447:1447)) + (PORT datab (944:944:944) (959:959:959)) + (PORT datad (319:319:319) (341:341:341)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~15) - (DELAY - (ABSOLUTE - (PORT dataa (637:637:637) (652:652:652)) - (PORT datab (877:877:877) (906:906:906)) - (PORT datac (864:864:864) (874:874:874)) - (PORT datad (1193:1193:1193) (1249:1249:1249)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|DFFE_mwr_ff1) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[5\]) (DELAY (ABSOLUTE - (PORT clk (1535:1535:1535) (1551:1551:1551)) + (PORT clk (1523:1523:1523) (1527:1527:1527)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1591:1591:1591) (1566:1566:1566)) - (PORT ena (1291:1291:1291) (1310:1310:1310)) + (PORT asdata (581:581:581) (655:655:655)) + (PORT sload (2041:2041:2041) (2133:2133:2133)) + (PORT ena (2004:2004:2004) (1967:1967:1967)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) ) (TIMINGCHECK (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|wait_mwr\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (219:219:219) (289:289:289)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|wait_mwr) - (DELAY - (ABSOLUTE - (PORT clk (1542:1542:1542) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1591:1591:1591) (1566:1566:1566)) - (PORT ena (1321:1321:1321) (1347:1347:1347)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|mwr_wr) - (DELAY - (ABSOLUTE - (PORT clk (1542:1542:1542) (1544:1544:1544)) - (PORT asdata (567:567:567) (645:645:645)) - (PORT clrn (1591:1591:1591) (1566:1566:1566)) - (PORT ena (1321:1321:1321) (1347:1347:1347)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK + (HOLD sload (posedge clk) (157:157:157)) (HOLD asdata (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|nWR_out\~0) + (INSTANCE z80_\|address_pins_\|abus\[5\]\~29) (DELAY (ABSOLUTE - (PORT dataa (870:870:870) (890:890:890)) - (PORT datab (351:351:351) (390:390:390)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) + (PORT datac (2387:2387:2387) (2516:2516:2516)) + (PORT datad (237:237:237) (305:305:305)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[5\]\~84) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[6\]\~6) (DELAY (ABSOLUTE - (PORT dataa (1754:1754:1754) (1854:1854:1854)) - (PORT datab (1594:1594:1594) (1729:1729:1729)) - (PORT datac (1191:1191:1191) (1256:1256:1256)) - (PORT datad (1224:1224:1224) (1308:1308:1308)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (1398:1398:1398) (1445:1445:1445)) + (PORT datab (897:897:897) (908:908:908)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1527:1527:1527)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (724:724:724) (783:783:783)) + (PORT sload (2041:2041:2041) (2133:2133:2133)) + (PORT ena (2004:2004:2004) (1967:1967:1967)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[6\]\~30) + (DELAY + (ABSOLUTE + (PORT datab (263:263:263) (345:345:345)) + (PORT datac (2385:2385:2385) (2515:2515:2515)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[7\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1428:1428:1428) (1479:1479:1479)) + (PORT datab (574:574:574) (589:589:589)) + (PORT datad (1317:1317:1317) (1317:1317:1317)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1527:1527:1527)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (727:727:727) (784:784:784)) + (PORT sload (2032:2032:2032) (2084:2084:2084)) + (PORT ena (2298:2298:2298) (2265:2265:2265)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[7\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (2753:2753:2753) (2927:2927:2927)) + (PORT datad (919:919:919) (994:994:994)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[10\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (2700:2700:2700) (2865:2865:2865)) + (PORT datad (1399:1399:1399) (1477:1477:1477)) + (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.datain_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1170:1170:1170) (1220:1220:1220)) - (PORT clk (1856:1856:1856) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4199:4199:4199) (4456:4456:4456)) - (PORT d[1] (2869:2869:2869) (3121:3121:3121)) - (PORT d[2] (3253:3253:3253) (3349:3349:3349)) - (PORT d[3] (2536:2536:2536) (2717:2717:2717)) - (PORT d[4] (2232:2232:2232) (2420:2420:2420)) - (PORT d[5] (2568:2568:2568) (2749:2749:2749)) - (PORT d[6] (1862:1862:1862) (1979:1979:1979)) - (PORT d[7] (2324:2324:2324) (2461:2461:2461)) - (PORT d[8] (3106:3106:3106) (3383:3383:3383)) - (PORT d[9] (2915:2915:2915) (3048:3048:3048)) - (PORT d[10] (4807:4807:4807) (5077:5077:5077)) - (PORT d[11] (2186:2186:2186) (2342:2342:2342)) - (PORT d[12] (2200:2200:2200) (2338:2338:2338)) - (PORT clk (1853:1853:1853) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1968:1968:1968) (1944:1944:1944)) - (PORT clk (1853:1853:1853) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1883:1883:1883)) - (PORT d[0] (2326:2326:2326) (2304:2304:2304)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1816:1816:1816) (1842:1842:1842)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1001:1001:1001) (1005:1005:1005)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1002:1002:1002) (1006:1006:1006)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1002:1002:1002) (1006:1006:1006)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1002:1002:1002) (1006:1006:1006)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1193:1193:1193) (1222:1222:1222)) + (PORT d[0] (949:949:949) (947:947:947)) (PORT clk (1858:1858:1858) (1884:1884:1884)) ) ) @@ -43247,22 +31348,22 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (4194:4194:4194) (4449:4449:4449)) - (PORT d[1] (2891:2891:2891) (3144:3144:3144)) - (PORT d[2] (2764:2764:2764) (2858:2858:2858)) - (PORT d[3] (2536:2536:2536) (2713:2713:2713)) - (PORT d[4] (2253:2253:2253) (2443:2443:2443)) - (PORT d[5] (2541:2541:2541) (2717:2717:2717)) - (PORT d[6] (1898:1898:1898) (2008:2008:2008)) - (PORT d[7] (2297:2297:2297) (2428:2428:2428)) - (PORT d[8] (3124:3124:3124) (3401:3401:3401)) - (PORT d[9] (2609:2609:2609) (2741:2741:2741)) - (PORT d[10] (4803:4803:4803) (5068:5068:5068)) - (PORT d[11] (1891:1891:1891) (2036:2036:2036)) - (PORT d[12] (2208:2208:2208) (2353:2353:2353)) + (PORT d[0] (3244:3244:3244) (3484:3484:3484)) + (PORT d[1] (1230:1230:1230) (1303:1303:1303)) + (PORT d[2] (2930:2930:2930) (3162:3162:3162)) + (PORT d[3] (711:711:711) (746:746:746)) + (PORT d[4] (1129:1129:1129) (1133:1133:1133)) + (PORT d[5] (1229:1229:1229) (1266:1266:1266)) + (PORT d[6] (986:986:986) (1025:1025:1025)) + (PORT d[7] (2881:2881:2881) (3130:3130:3130)) + (PORT d[8] (1254:1254:1254) (1284:1284:1284)) + (PORT d[9] (965:965:965) (989:989:989)) + (PORT d[10] (1597:1597:1597) (1663:1663:1663)) + (PORT d[11] (1508:1508:1508) (1552:1552:1552)) + (PORT d[12] (2584:2584:2584) (2670:2670:2670)) (PORT clk (1855:1855:1855) (1880:1880:1880)) ) ) @@ -43272,10 +31373,10 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.we_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2383:2383:2383) (2365:2365:2365)) + (PORT d[0] (1973:1973:1973) (1902:1902:1902)) (PORT clk (1855:1855:1855) (1880:1880:1880)) ) ) @@ -43285,17 +31386,17 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) (DELAY (ABSOLUTE (PORT clk (1858:1858:1858) (1884:1884:1884)) - (PORT d[0] (2857:2857:2857) (2839:2839:2839)) + (PORT d[0] (2244:2244:2244) (2181:2181:2181)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_a) (DELAY (ABSOLUTE (PORT clk (1859:1859:1859) (1885:1885:1885)) @@ -43305,7 +31406,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) (DELAY (ABSOLUTE (PORT clk (1859:1859:1859) (1885:1885:1885)) @@ -43315,7 +31416,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_a) (DELAY (ABSOLUTE (PORT clk (1859:1859:1859) (1885:1885:1885)) @@ -43325,7 +31426,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_a) (DELAY (ABSOLUTE (PORT clk (1859:1859:1859) (1885:1885:1885)) @@ -43335,7 +31436,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) (DELAY (ABSOLUTE (PORT clk (1818:1818:1818) (1843:1843:1843)) @@ -43349,7 +31450,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) (DELAY (ABSOLUTE (PORT clk (1003:1003:1003) (1006:1006:1006)) @@ -43358,7 +31459,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) (DELAY (ABSOLUTE (PORT clk (1004:1004:1004) (1007:1007:1007)) @@ -43367,7 +31468,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) (DELAY (ABSOLUTE (PORT clk (1004:1004:1004) (1007:1007:1007)) @@ -43377,7 +31478,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) (DELAY (ABSOLUTE (PORT clk (1004:1004:1004) (1007:1007:1007)) @@ -43385,982 +31486,17 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (880:880:880) (918:918:918)) - (PORT clk (1852:1852:1852) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1334:1334:1334) (1380:1380:1380)) - (PORT d[1] (2044:2044:2044) (2248:2248:2248)) - (PORT d[2] (3016:3016:3016) (3126:3126:3126)) - (PORT d[3] (2584:2584:2584) (2783:2783:2783)) - (PORT d[4] (2569:2569:2569) (2761:2761:2761)) - (PORT d[5] (2836:2836:2836) (3029:3029:3029)) - (PORT d[6] (1949:1949:1949) (2075:2075:2075)) - (PORT d[7] (2609:2609:2609) (2760:2760:2760)) - (PORT d[8] (3388:3388:3388) (3680:3680:3680)) - (PORT d[9] (2935:2935:2935) (3067:3067:3067)) - (PORT d[10] (5109:5109:5109) (5374:5374:5374)) - (PORT d[11] (1927:1927:1927) (2066:2066:2066)) - (PORT d[12] (1910:1910:1910) (2033:2033:2033)) - (PORT clk (1849:1849:1849) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1228:1228:1228) (1223:1223:1223)) - (PORT clk (1849:1849:1849) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1879:1879:1879)) - (PORT d[0] (2528:2528:2528) (2496:2496:2496)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1812:1812:1812) (1838:1838:1838)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1001:1001:1001)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~6) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode223w\[2\]) (DELAY (ABSOLUTE - (PORT dataa (1430:1430:1430) (1510:1510:1510)) - (PORT datab (977:977:977) (1037:1037:1037)) - (PORT datac (1084:1084:1084) (1106:1106:1106)) - (PORT datad (833:833:833) (863:863:863)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1183:1183:1183) (1216:1216:1216)) - (PORT clk (1849:1849:1849) (1876:1876:1876)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3355:3355:3355) (3572:3572:3572)) - (PORT d[1] (1697:1697:1697) (1865:1865:1865)) - (PORT d[2] (2991:2991:2991) (3133:3133:3133)) - (PORT d[3] (2197:2197:2197) (2290:2290:2290)) - (PORT d[4] (2502:2502:2502) (2653:2653:2653)) - (PORT d[5] (2405:2405:2405) (2601:2601:2601)) - (PORT d[6] (2102:2102:2102) (2200:2200:2200)) - (PORT d[7] (2478:2478:2478) (2588:2588:2588)) - (PORT d[8] (3018:3018:3018) (3244:3244:3244)) - (PORT d[9] (2534:2534:2534) (2624:2624:2624)) - (PORT d[10] (3776:3776:3776) (4011:4011:4011)) - (PORT d[11] (1726:1726:1726) (1804:1804:1804)) - (PORT d[12] (2323:2323:2323) (2409:2409:2409)) - (PORT clk (1846:1846:1846) (1872:1872:1872)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2206:2206:2206) (2199:2199:2199)) - (PORT clk (1846:1846:1846) (1872:1872:1872)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1849:1849:1849) (1876:1876:1876)) - (PORT d[0] (2749:2749:2749) (2715:2715:2715)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1809:1809:1809) (1835:1835:1835)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (994:994:994) (998:998:998)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (995:995:995) (999:999:999)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (995:995:995) (999:999:999)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (995:995:995) (999:999:999)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1449:1449:1449) (1499:1499:1499)) - (PORT datab (1154:1154:1154) (1180:1180:1180)) - (PORT datac (171:171:171) (203:203:203)) - (PORT datad (1425:1425:1425) (1425:1425:1425)) + (PORT dataa (1196:1196:1196) (1217:1217:1217)) + (PORT datab (239:239:239) (292:292:292)) + (PORT datac (568:568:568) (595:595:595)) + (PORT datad (1614:1614:1614) (1653:1653:1653)) (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1785:1785:1785) (1834:1834:1834)) - (PORT clk (1844:1844:1844) (1873:1873:1873)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3330:3330:3330) (3510:3510:3510)) - (PORT d[1] (2345:2345:2345) (2548:2548:2548)) - (PORT d[2] (2224:2224:2224) (2307:2307:2307)) - (PORT d[3] (1895:1895:1895) (2026:2026:2026)) - (PORT d[4] (2445:2445:2445) (2553:2553:2553)) - (PORT d[5] (1968:1968:1968) (2118:2118:2118)) - (PORT d[6] (1422:1422:1422) (1463:1463:1463)) - (PORT d[7] (1469:1469:1469) (1501:1501:1501)) - (PORT d[8] (2903:2903:2903) (3100:3100:3100)) - (PORT d[9] (1984:1984:1984) (2114:2114:2114)) - (PORT d[10] (1991:1991:1991) (2095:2095:2095)) - (PORT d[11] (1441:1441:1441) (1479:1479:1479)) - (PORT d[12] (2020:2020:2020) (2065:2065:2065)) - (PORT clk (1841:1841:1841) (1869:1869:1869)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2835:2835:2835) (2823:2823:2823)) - (PORT clk (1841:1841:1841) (1869:1869:1869)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1873:1873:1873)) - (PORT d[0] (3960:3960:3960) (4062:4062:4062)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1845:1845:1845) (1874:1874:1874)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1845:1845:1845) (1874:1874:1874)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1845:1845:1845) (1874:1874:1874)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1845:1845:1845) (1874:1874:1874)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1799:1799:1799) (1798:1798:1798)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1198:1198:1198) (1181:1181:1181)) - (PORT clk (1809:1809:1809) (1804:1804:1804)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4418:4418:4418) (4468:4468:4468)) - (PORT d[1] (4222:4222:4222) (4280:4280:4280)) - (PORT d[2] (4287:4287:4287) (4334:4334:4334)) - (PORT d[3] (4530:4530:4530) (4580:4580:4580)) - (PORT d[4] (4340:4340:4340) (4354:4354:4354)) - (PORT d[5] (4359:4359:4359) (4381:4381:4381)) - (PORT d[6] (4659:4659:4659) (4748:4748:4748)) - (PORT d[7] (4373:4373:4373) (4445:4445:4445)) - (PORT d[8] (4529:4529:4529) (4546:4546:4546)) - (PORT d[9] (4710:4710:4710) (4968:4968:4968)) - (PORT d[10] (4380:4380:4380) (4418:4418:4418)) - (PORT d[11] (4364:4364:4364) (4385:4385:4385)) - (PORT d[12] (4681:4681:4681) (4658:4658:4658)) - (PORT clk (1805:1805:1805) (1800:1800:1800)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1809:1809:1809) (1804:1804:1804)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1810:1810:1810) (1805:1805:1805)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1810:1810:1810) (1805:1805:1805)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1810:1810:1810) (1805:1805:1805)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1810:1810:1810) (1805:1805:1805)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2604:2604:2604) (2682:2682:2682)) - (PORT d[1] (2063:2063:2063) (2283:2283:2283)) - (PORT d[2] (2289:2289:2289) (2441:2441:2441)) - (PORT d[3] (2285:2285:2285) (2377:2377:2377)) - (PORT d[4] (2950:2950:2950) (3220:3220:3220)) - (PORT d[5] (2075:2075:2075) (2260:2260:2260)) - (PORT d[6] (1854:1854:1854) (1963:1963:1963)) - (PORT d[7] (2555:2555:2555) (2658:2658:2658)) - (PORT d[8] (2752:2752:2752) (3006:3006:3006)) - (PORT d[9] (1553:1553:1553) (1673:1673:1673)) - (PORT d[10] (1845:1845:1845) (1962:1962:1962)) - (PORT d[11] (2882:2882:2882) (3002:3002:3002)) - (PORT d[12] (1537:1537:1537) (1640:1640:1640)) - (PORT clk (1867:1867:1867) (1892:1892:1892)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1867:1867:1867) (1892:1892:1892)) - (PORT d[0] (2184:2184:2184) (2245:2245:2245)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1868:1868:1868) (1893:1893:1893)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1830:1830:1830) (1855:1855:1855)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1015:1015:1015) (1018:1018:1018)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1016:1016:1016) (1019:1019:1019)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1016:1016:1016) (1019:1019:1019)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1016:1016:1016) (1019:1019:1019)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3543:3543:3543) (3733:3733:3733)) - (PORT d[1] (1715:1715:1715) (1880:1880:1880)) - (PORT d[2] (2685:2685:2685) (2807:2807:2807)) - (PORT d[3] (2133:2133:2133) (2228:2228:2228)) - (PORT d[4] (1902:1902:1902) (2026:2026:2026)) - (PORT d[5] (2379:2379:2379) (2573:2573:2573)) - (PORT d[6] (2329:2329:2329) (2418:2418:2418)) - (PORT d[7] (2458:2458:2458) (2570:2570:2570)) - (PORT d[8] (2691:2691:2691) (2888:2888:2888)) - (PORT d[9] (2519:2519:2519) (2590:2590:2590)) - (PORT d[10] (3815:3815:3815) (4071:4071:4071)) - (PORT d[11] (1813:1813:1813) (1894:1894:1894)) - (PORT d[12] (2372:2372:2372) (2459:2459:2459)) - (PORT clk (1848:1848:1848) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1875:1875:1875)) - (PORT d[0] (2529:2529:2529) (2434:2434:2434)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1849:1849:1849) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1811:1811:1811) (1838:1838:1838)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1649:1649:1649) (1736:1736:1736)) - (PORT clk (1860:1860:1860) (1888:1888:1888)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2915:2915:2915) (3030:3030:3030)) - (PORT d[1] (2366:2366:2366) (2611:2611:2611)) - (PORT d[2] (2597:2597:2597) (2777:2777:2777)) - (PORT d[3] (2017:2017:2017) (2075:2075:2075)) - (PORT d[4] (2919:2919:2919) (3173:3173:3173)) - (PORT d[5] (2370:2370:2370) (2578:2578:2578)) - (PORT d[6] (1866:1866:1866) (1962:1962:1962)) - (PORT d[7] (1642:1642:1642) (1751:1751:1751)) - (PORT d[8] (3027:3027:3027) (3282:3282:3282)) - (PORT d[9] (1219:1219:1219) (1304:1304:1304)) - (PORT d[10] (2155:2155:2155) (2296:2296:2296)) - (PORT d[11] (3694:3694:3694) (3833:3833:3833)) - (PORT d[12] (1894:1894:1894) (1995:1995:1995)) - (PORT clk (1857:1857:1857) (1884:1884:1884)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2802:2802:2802) (2787:2787:2787)) - (PORT clk (1857:1857:1857) (1884:1884:1884)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1888:1888:1888)) - (PORT d[0] (3138:3138:3138) (3102:3102:3102)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1889:1889:1889)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1889:1889:1889)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1889:1889:1889)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1889:1889:1889)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1815:1815:1815) (1813:1813:1813)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2176:2176:2176) (2231:2231:2231)) - (PORT clk (1825:1825:1825) (1819:1819:1819)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4610:4610:4610) (4658:4658:4658)) - (PORT d[1] (4157:4157:4157) (4160:4160:4160)) - (PORT d[2] (4196:4196:4196) (4284:4284:4284)) - (PORT d[3] (4718:4718:4718) (4716:4716:4716)) - (PORT d[4] (4356:4356:4356) (4386:4386:4386)) - (PORT d[5] (4428:4428:4428) (4381:4381:4381)) - (PORT d[6] (4640:4640:4640) (4703:4703:4703)) - (PORT d[7] (4181:4181:4181) (4140:4140:4140)) - (PORT d[8] (4708:4708:4708) (4720:4720:4720)) - (PORT d[9] (4594:4594:4594) (4806:4806:4806)) - (PORT d[10] (4407:4407:4407) (4422:4422:4422)) - (PORT d[11] (4504:4504:4504) (4555:4555:4555)) - (PORT d[12] (4480:4480:4480) (4497:4497:4497)) - (PORT clk (1821:1821:1821) (1815:1815:1815)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1825:1825:1825) (1819:1819:1819)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1820:1820:1820)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1820:1820:1820)) - (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1820:1820:1820)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1820:1820:1820)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1817:1817:1817) (1815:1815:1815)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Mux0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1424:1424:1424) (1496:1496:1496)) - (PORT datab (973:973:973) (1052:1052:1052)) - (PORT datac (1431:1431:1431) (1467:1467:1467)) - (PORT datad (1389:1389:1389) (1443:1443:1443)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Mux0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1500:1500:1500) (1615:1615:1615)) - (PORT datab (972:972:972) (1051:1051:1051)) - (PORT datac (1456:1456:1456) (1510:1510:1510)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datab combout (342:342:342) (318:318:318)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -44368,169 +31504,218 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[7\]\~112) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode223w\[2\]\~0) (DELAY (ABSOLUTE - (PORT dataa (1480:1480:1480) (1579:1579:1579)) - (PORT datab (1206:1206:1206) (1296:1296:1296)) - (PORT datac (173:173:173) (206:206:206)) - (PORT datad (174:174:174) (198:198:198)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT datab (1635:1635:1635) (1774:1774:1774)) + (PORT datac (2565:2565:2565) (2731:2731:2731)) + (PORT datad (2259:2259:2259) (2379:2379:2379)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[7\]\~94) + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register) (DELAY (ABSOLUTE - (PORT dataa (1382:1382:1382) (1396:1396:1396)) - (PORT datab (885:885:885) (963:963:963)) - (PORT datac (171:171:171) (203:203:203)) - (PORT datad (1346:1346:1346) (1371:1371:1371)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT d[0] (745:745:745) (777:777:777)) + (PORT clk (1854:1854:1854) (1881:1881:1881)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2601:2601:2601) (2724:2724:2724)) + (PORT d[1] (957:957:957) (991:991:991)) + (PORT d[2] (2647:2647:2647) (2880:2880:2880)) + (PORT d[3] (990:990:990) (1038:1038:1038)) + (PORT d[4] (704:704:704) (741:741:741)) + (PORT d[5] (668:668:668) (685:685:685)) + (PORT d[6] (666:666:666) (687:687:687)) + (PORT d[7] (2154:2154:2154) (2329:2329:2329)) + (PORT d[8] (1515:1515:1515) (1558:1558:1558)) + (PORT d[9] (665:665:665) (685:685:685)) + (PORT d[10] (2168:2168:2168) (2235:2235:2235)) + (PORT d[11] (1753:1753:1753) (1779:1779:1779)) + (PORT d[12] (2577:2577:2577) (2648:2648:2648)) + (PORT clk (1851:1851:1851) (1877:1877:1877)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1431:1431:1431) (1378:1378:1378)) + (PORT clk (1851:1851:1851) (1877:1877:1877)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1881:1881:1881)) + (PORT d[0] (1918:1918:1918) (1876:1876:1876)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1855:1855:1855) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1855:1855:1855) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1855:1855:1855) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1855:1855:1855) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1814:1814:1814) (1840:1840:1840)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (999:999:999) (1003:1003:1003)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1000:1000:1000) (1004:1004:1004)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1000:1000:1000) (1004:1004:1004)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1000:1000:1000) (1004:1004:1004)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[7\]\~102) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[0\]\~feeder) (DELAY (ABSOLUTE - (PORT datac (191:191:191) (224:224:224)) - (PORT datad (781:781:781) (792:792:792)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[7\]) - (DELAY - (ABSOLUTE - (PORT dataa (968:968:968) (1025:1025:1025)) - (PORT datab (229:229:229) (272:272:272)) - (PORT datac (239:239:239) (287:287:287)) - (PORT datad (858:858:858) (899:899:899)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT datad (1551:1551:1551) (1591:1591:1591)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[7\]) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[0\]) (DELAY (ABSOLUTE - (PORT clk (1526:1526:1526) (1531:1531:1531)) + (PORT clk (1516:1516:1516) (1529:1529:1529)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (841:841:841) (846:846:846)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[7\]\~5) - (DELAY - (ABSOLUTE - (PORT datab (1164:1164:1164) (1192:1192:1192)) - (PORT datac (942:942:942) (1003:1003:1003)) - (PORT datad (367:367:367) (390:390:390)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[7\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (267:267:267) (355:355:355)) - (PORT datab (711:711:711) (731:731:731)) - (PORT datac (879:879:879) (883:883:883)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[7\]) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]) (DELAY (ABSOLUTE - (PORT clk (1522:1522:1522) (1535:1535:1535)) - (PORT asdata (546:546:546) (581:581:581)) - (PORT clrn (1579:1579:1579) (1558:1558:1558)) - (PORT ena (1501:1501:1501) (1488:1488:1488)) + (PORT clk (1516:1516:1516) (1529:1529:1529)) + (PORT asdata (1468:1468:1468) (1527:1527:1527)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) ) (TIMINGCHECK (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal77\~0) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode244w\[2\]) (DELAY (ABSOLUTE - (PORT dataa (711:711:711) (814:814:814)) - (PORT datab (1235:1235:1235) (1355:1355:1355)) - (PORT datac (985:985:985) (1064:1064:1064)) - (PORT datad (1322:1322:1322) (1437:1437:1437)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~5) - (DELAY - (ABSOLUTE - (PORT dataa (690:690:690) (756:756:756)) - (PORT datab (994:994:994) (1104:1104:1104)) - (PORT datac (1148:1148:1148) (1191:1191:1191)) - (PORT datad (1194:1194:1194) (1254:1254:1254)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla31pla33M4T1_3) - (DELAY - (ABSOLUTE - (PORT dataa (717:717:717) (780:780:780)) - (PORT datab (376:376:376) (417:417:417)) - (PORT datac (1100:1100:1100) (1123:1123:1123)) - (PORT datad (1740:1740:1740) (1811:1811:1811)) + (PORT dataa (1201:1201:1201) (1224:1224:1224)) + (PORT datab (238:238:238) (291:291:291)) + (PORT datac (574:574:574) (597:597:597)) + (PORT datad (1616:1616:1616) (1655:1655:1655)) (IOPATH dataa combout (327:327:327) (347:347:347)) (IOPATH datab combout (331:331:331) (342:342:342)) (IOPATH datac combout (243:243:243) (241:241:241)) @@ -44540,645 +31725,24 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~3) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode244w\[2\]\~0) (DELAY (ABSOLUTE - (PORT dataa (999:999:999) (1037:1037:1037)) - (PORT datab (1148:1148:1148) (1181:1181:1181)) - (PORT datac (1118:1118:1118) (1156:1156:1156)) - (PORT datad (172:172:172) (198:198:198)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1747:1747:1747) (1768:1768:1768)) - (PORT datab (1063:1063:1063) (1181:1181:1181)) - (PORT datac (1205:1205:1205) (1277:1277:1277)) - (PORT datad (1152:1152:1152) (1188:1188:1188)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1745:1745:1745) (1764:1764:1764)) - (PORT datab (372:372:372) (420:420:420)) - (PORT datac (1499:1499:1499) (1632:1632:1632)) - (PORT datad (1111:1111:1111) (1140:1140:1140)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (232:232:232) (279:279:279)) - (PORT datab (1037:1037:1037) (1088:1088:1088)) - (PORT datac (1095:1095:1095) (1134:1134:1134)) - (PORT datad (1073:1073:1073) (1110:1110:1110)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (880:880:880) (904:904:904)) - (PORT datab (1509:1509:1509) (1569:1569:1569)) - (PORT datac (829:829:829) (848:848:848)) - (PORT datad (860:860:860) (875:875:875)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~7) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (171:171:171) (205:205:205)) - (PORT datad (172:172:172) (198:198:198)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]\~50) - (DELAY - (ABSOLUTE - (PORT datac (1078:1078:1078) (1174:1174:1174)) - (PORT datad (1031:1031:1031) (1116:1116:1116)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]\~52) - (DELAY - (ABSOLUTE - (PORT dataa (403:403:403) (436:436:436)) - (PORT datab (968:968:968) (1056:1056:1056)) - (PORT datad (175:175:175) (200:200:200)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]\~48) - (DELAY - (ABSOLUTE - (PORT dataa (224:224:224) (280:280:280)) - (PORT datab (775:775:775) (874:874:874)) - (PORT datac (1366:1366:1366) (1453:1453:1453)) - (PORT datad (1546:1546:1546) (1637:1637:1637)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[2\]\~49) - (DELAY - (ABSOLUTE - (PORT dataa (345:345:345) (379:379:379)) - (PORT datab (222:222:222) (260:260:260)) - (PORT datad (739:739:739) (824:824:824)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (2308:2308:2308) (2488:2488:2488)) - (PORT datab (241:241:241) (322:322:322)) - (PORT datac (574:574:574) (621:621:621)) - (PORT datad (1325:1325:1325) (1345:1345:1345)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~57) - (DELAY - (ABSOLUTE - (PORT datab (965:965:965) (1048:1048:1048)) - (PORT datad (728:728:728) (839:839:839)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~58) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (246:246:246)) - (PORT datab (622:622:622) (672:672:672)) - (PORT datad (961:961:961) (1040:1040:1040)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1573:1573:1573)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~59) - (DELAY - (ABSOLUTE - (PORT dataa (489:489:489) (568:568:568)) - (PORT datab (664:664:664) (740:740:740)) - (PORT datac (606:606:606) (671:671:671)) - (PORT datad (721:721:721) (799:799:799)) - (IOPATH dataa combout (341:341:341) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~131) - (DELAY - (ABSOLUTE - (PORT dataa (447:447:447) (538:538:538)) - (PORT datab (342:342:342) (377:377:377)) - (PORT datad (260:260:260) (338:338:338)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~60) - (DELAY - (ABSOLUTE - (PORT dataa (792:792:792) (908:908:908)) - (PORT datab (1091:1091:1091) (1095:1095:1095)) - (PORT datad (617:617:617) (636:636:636)) - (IOPATH dataa combout (325:325:325) (328:328:328)) + (PORT datab (2065:2065:2065) (2202:2202:2202)) + (PORT datac (1304:1304:1304) (1449:1449:1449)) + (PORT datad (3045:3045:3045) (3237:3237:3237)) (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1573:1573:1573)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (1155:1155:1155) (1224:1224:1224)) - (PORT datab (240:240:240) (321:321:321)) - (PORT datac (568:568:568) (626:626:626)) - (PORT datad (553:553:553) (572:572:572)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]\~53) - (DELAY - (ABSOLUTE - (PORT datac (1077:1077:1077) (1170:1170:1170)) - (PORT datad (1031:1031:1031) (1112:1112:1112)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]\~55) - (DELAY - (ABSOLUTE - (PORT dataa (227:227:227) (285:285:285)) - (PORT datab (390:390:390) (410:410:410)) - (PORT datac (918:918:918) (988:988:988)) - (PORT datad (328:328:328) (348:348:348)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]\~56) - (DELAY - (ABSOLUTE - (PORT datab (969:969:969) (1059:1059:1059)) - (PORT datad (338:338:338) (357:357:357)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]\~54) - (DELAY - (ABSOLUTE - (PORT dataa (406:406:406) (439:439:439)) - (PORT datab (969:969:969) (1059:1059:1059)) - (PORT datad (195:195:195) (220:220:220)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (244:244:244) (330:330:330)) - (PORT datab (242:242:242) (324:324:324)) - (PORT datac (559:559:559) (587:587:587)) - (PORT datad (556:556:556) (572:572:572)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~68) - (DELAY - (ABSOLUTE - (PORT dataa (963:963:963) (1040:1040:1040)) - (PORT datab (793:793:793) (911:911:911)) - (PORT datac (907:907:907) (1000:1000:1000)) - (PORT datad (764:764:764) (871:871:871)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~69) - (DELAY - (ABSOLUTE - (PORT dataa (358:358:358) (395:395:395)) - (PORT datab (737:737:737) (825:825:825)) - (PORT datad (589:589:589) (600:600:600)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~70) - (DELAY - (ABSOLUTE - (PORT dataa (213:213:213) (262:262:262)) - (PORT datab (201:201:201) (241:241:241)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~61) - (DELAY - (ABSOLUTE - (PORT datac (244:244:244) (324:324:324)) - (PORT datad (831:831:831) (879:879:879)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~62) - (DELAY - (ABSOLUTE - (PORT dataa (699:699:699) (764:764:764)) - (PORT datab (349:349:349) (382:382:382)) - (PORT datac (658:658:658) (727:727:727)) - (PORT datad (638:638:638) (705:705:705)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~64) - (DELAY - (ABSOLUTE - (PORT dataa (210:210:210) (257:257:257)) - (PORT datab (471:471:471) (546:546:546)) - (PORT datac (352:352:352) (381:381:381)) - (PORT datad (197:197:197) (232:232:232)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~65) - (DELAY - (ABSOLUTE - (PORT dataa (734:734:734) (824:824:824)) - (PORT datab (493:493:493) (577:577:577)) - (PORT datac (572:572:572) (608:608:608)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Selector13\~0) - (DELAY - (ABSOLUTE - (PORT dataa (747:747:747) (849:849:849)) - (PORT datab (773:773:773) (872:872:872)) - (PORT datad (959:959:959) (1036:1036:1036)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~66) - (DELAY - (ABSOLUTE - (PORT dataa (340:340:340) (370:370:370)) - (PORT datad (635:635:635) (675:675:675)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~38) - (DELAY - (ABSOLUTE - (PORT dataa (1664:1664:1664) (1689:1689:1689)) - (PORT datab (618:618:618) (678:678:678)) - (PORT datac (1058:1058:1058) (1128:1128:1128)) - (PORT datad (216:216:216) (284:284:284)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~39) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (634:634:634) (655:655:655)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (589:589:589) (603:603:603)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~104) - (DELAY - (ABSOLUTE - (PORT datab (1233:1233:1233) (1299:1299:1299)) - (PORT datac (655:655:655) (738:738:738)) - (PORT datad (1395:1395:1395) (1412:1412:1412)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.datain_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (947:947:947) (974:974:974)) + (PORT d[0] (985:985:985) (999:999:999)) (PORT clk (1850:1850:1850) (1877:1877:1877)) ) ) @@ -45188,22 +31752,22 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.addr_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1333:1333:1333) (1379:1379:1379)) - (PORT d[1] (1965:1965:1965) (2168:2168:2168)) - (PORT d[2] (3064:3064:3064) (3182:3182:3182)) - (PORT d[3] (2837:2837:2837) (3038:3038:3038)) - (PORT d[4] (2548:2548:2548) (2738:2738:2738)) - (PORT d[5] (2841:2841:2841) (3039:3039:3039)) - (PORT d[6] (1923:1923:1923) (2045:2045:2045)) - (PORT d[7] (2590:2590:2590) (2742:2742:2742)) - (PORT d[8] (3415:3415:3415) (3712:3712:3712)) - (PORT d[9] (1607:1607:1607) (1686:1686:1686)) - (PORT d[10] (5088:5088:5088) (5355:5355:5355)) - (PORT d[11] (1909:1909:1909) (2057:2057:2057)) - (PORT d[12] (1909:1909:1909) (2032:2032:2032)) + (PORT d[0] (2598:2598:2598) (2701:2701:2701)) + (PORT d[1] (974:974:974) (1037:1037:1037)) + (PORT d[2] (2642:2642:2642) (2868:2868:2868)) + (PORT d[3] (973:973:973) (1022:1022:1022)) + (PORT d[4] (745:745:745) (794:794:794)) + (PORT d[5] (1202:1202:1202) (1239:1239:1239)) + (PORT d[6] (1002:1002:1002) (1045:1045:1045)) + (PORT d[7] (2142:2142:2142) (2302:2302:2302)) + (PORT d[8] (1221:1221:1221) (1255:1255:1255)) + (PORT d[9] (1256:1256:1256) (1275:1275:1275)) + (PORT d[10] (1133:1133:1133) (1153:1153:1153)) + (PORT d[11] (1494:1494:1494) (1524:1524:1524)) + (PORT d[12] (2288:2288:2288) (2355:2355:2355)) (PORT clk (1847:1847:1847) (1873:1873:1873)) ) ) @@ -45213,10 +31777,10 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.we_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1221:1221:1221) (1217:1217:1217)) + (PORT d[0] (2238:2238:2238) (2178:2178:2178)) (PORT clk (1847:1847:1847) (1873:1873:1873)) ) ) @@ -45226,17 +31790,17 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.active_core_port_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.active_core_port_a) (DELAY (ABSOLUTE (PORT clk (1850:1850:1850) (1877:1877:1877)) - (PORT d[0] (2517:2517:2517) (2474:2474:2474)) + (PORT d[0] (1924:1924:1924) (1902:1902:1902)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.wpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.wpgen_a) (DELAY (ABSOLUTE (PORT clk (1851:1851:1851) (1878:1878:1878)) @@ -45246,7 +31810,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rpgen_a) (DELAY (ABSOLUTE (PORT clk (1851:1851:1851) (1878:1878:1878)) @@ -45256,7 +31820,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.ftpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.ftpgen_a) (DELAY (ABSOLUTE (PORT clk (1851:1851:1851) (1878:1878:1878)) @@ -45266,7 +31830,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rwpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rwpgen_a) (DELAY (ABSOLUTE (PORT clk (1851:1851:1851) (1878:1878:1878)) @@ -45276,7 +31840,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.dataout_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.dataout_a_register) (DELAY (ABSOLUTE (PORT clk (1810:1810:1810) (1836:1836:1836)) @@ -45290,7 +31854,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.active_core_port_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.active_core_port_b) (DELAY (ABSOLUTE (PORT clk (995:995:995) (999:999:999)) @@ -45299,7 +31863,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rpgen_b) (DELAY (ABSOLUTE (PORT clk (996:996:996) (1000:1000:1000)) @@ -45308,7 +31872,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.ftpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.ftpgen_b) (DELAY (ABSOLUTE (PORT clk (996:996:996) (1000:1000:1000)) @@ -45318,7 +31882,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rwpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rwpgen_b) (DELAY (ABSOLUTE (PORT clk (996:996:996) (1000:1000:1000)) @@ -45327,164 +31891,85 @@ ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.datain_a_register) + (CELLTYPE "dffeas") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[1\]) (DELAY (ABSOLUTE - (PORT d[0] (704:704:704) (727:727:727)) - (PORT clk (1858:1858:1858) (1884:1884:1884)) + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT asdata (2072:2072:2072) (2099:2099:2099)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) + (HOLD asdata (posedge clk) (157:157:157)) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) + (CELLTYPE "dffeas") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[1\]) (DELAY (ABSOLUTE - (PORT d[0] (1274:1274:1274) (1301:1301:1301)) - (PORT d[1] (2099:2099:2099) (2330:2330:2330)) - (PORT d[2] (1248:1248:1248) (1286:1286:1286)) - (PORT d[3] (1307:1307:1307) (1357:1357:1357)) - (PORT d[4] (2610:2610:2610) (2833:2833:2833)) - (PORT d[5] (3471:3471:3471) (3676:3676:3676)) - (PORT d[6] (1323:1323:1323) (1420:1420:1420)) - (PORT d[7] (2887:2887:2887) (3061:3061:3061)) - (PORT d[8] (985:985:985) (1023:1023:1023)) - (PORT d[9] (1296:1296:1296) (1359:1359:1359)) - (PORT d[10] (1357:1357:1357) (1455:1455:1455)) - (PORT d[11] (2476:2476:2476) (2609:2609:2609)) - (PORT d[12] (1610:1610:1610) (1711:1711:1711)) - (PORT clk (1855:1855:1855) (1880:1880:1880)) + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT asdata (2010:2010:2010) (2103:2103:2103)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) + (HOLD asdata (posedge clk) (157:157:157)) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.we_a_register) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[1\]\~0) (DELAY (ABSOLUTE - (PORT d[0] (979:979:979) (953:953:953)) - (PORT clk (1855:1855:1855) (1880:1880:1880)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1884:1884:1884)) - (PORT d[0] (1492:1492:1492) (1460:1460:1460)) + (PORT dataa (600:600:600) (611:611:611)) + (PORT datab (1169:1169:1169) (1231:1231:1231)) + (PORT datac (851:851:851) (858:858:858)) + (PORT datad (1375:1375:1375) (1438:1438:1438)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_a) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode252w\[2\]) (DELAY (ABSOLUTE - (PORT clk (1859:1859:1859) (1885:1885:1885)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + (PORT dataa (1201:1201:1201) (1224:1224:1224)) + (PORT datab (242:242:242) (296:296:296)) + (PORT datac (574:574:574) (599:599:599)) + (PORT datad (1614:1614:1614) (1659:1659:1659)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode252w\[2\]\~0) (DELAY (ABSOLUTE - (PORT clk (1859:1859:1859) (1885:1885:1885)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1859:1859:1859) (1885:1885:1885)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1859:1859:1859) (1885:1885:1885)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + (PORT datab (2067:2067:2067) (2204:2204:2204)) + (PORT datac (1304:1304:1304) (1447:1447:1447)) + (PORT datad (3040:3040:3040) (3233:3233:3233)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.datain_a_register) (DELAY (ABSOLUTE - (PORT clk (1818:1818:1818) (1843:1843:1843)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1003:1003:1003) (1006:1006:1006)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1004:1004:1004) (1007:1007:1007)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1004:1004:1004) (1007:1007:1007)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1004:1004:1004) (1007:1007:1007)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (947:947:947) (973:973:973)) + (PORT d[0] (1016:1016:1016) (1054:1054:1054)) (PORT clk (1852:1852:1852) (1879:1879:1879)) ) ) @@ -45494,22 +31979,22 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.addr_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1343:1343:1343) (1413:1413:1413)) - (PORT d[1] (3163:3163:3163) (3436:3436:3436)) - (PORT d[2] (3532:3532:3532) (3625:3625:3625)) - (PORT d[3] (2837:2837:2837) (3043:3043:3043)) - (PORT d[4] (2558:2558:2558) (2781:2781:2781)) - (PORT d[5] (2869:2869:2869) (3072:3072:3072)) - (PORT d[6] (1676:1676:1676) (1759:1759:1759)) - (PORT d[7] (1505:1505:1505) (1586:1586:1586)) - (PORT d[8] (3442:3442:3442) (3720:3720:3720)) - (PORT d[9] (3231:3231:3231) (3382:3382:3382)) - (PORT d[10] (5089:5089:5089) (5374:5374:5374)) - (PORT d[11] (1942:1942:1942) (2100:2100:2100)) - (PORT d[12] (1901:1901:1901) (2017:2017:2017)) + (PORT d[0] (2322:2322:2322) (2426:2426:2426)) + (PORT d[1] (984:984:984) (1039:1039:1039)) + (PORT d[2] (2633:2633:2633) (2847:2847:2847)) + (PORT d[3] (2802:2802:2802) (2969:2969:2969)) + (PORT d[4] (733:733:733) (772:772:772)) + (PORT d[5] (1238:1238:1238) (1298:1298:1298)) + (PORT d[6] (985:985:985) (1001:1001:1001)) + (PORT d[7] (1894:1894:1894) (2056:2056:2056)) + (PORT d[8] (1208:1208:1208) (1253:1253:1253)) + (PORT d[9] (971:971:971) (1010:1010:1010)) + (PORT d[10] (666:666:666) (702:702:702)) + (PORT d[11] (1500:1500:1500) (1540:1540:1540)) + (PORT d[12] (2302:2302:2302) (2344:2344:2344)) (PORT clk (1849:1849:1849) (1875:1875:1875)) ) ) @@ -45519,10 +32004,10 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.we_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1717:1717:1717) (1648:1648:1648)) + (PORT d[0] (1755:1755:1755) (1733:1733:1733)) (PORT clk (1849:1849:1849) (1875:1875:1875)) ) ) @@ -45532,17 +32017,17 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.active_core_port_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.active_core_port_a) (DELAY (ABSOLUTE (PORT clk (1852:1852:1852) (1879:1879:1879)) - (PORT d[0] (2052:2052:2052) (2017:2017:2017)) + (PORT d[0] (1916:1916:1916) (1893:1893:1893)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.wpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.wpgen_a) (DELAY (ABSOLUTE (PORT clk (1853:1853:1853) (1880:1880:1880)) @@ -45552,7 +32037,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rpgen_a) (DELAY (ABSOLUTE (PORT clk (1853:1853:1853) (1880:1880:1880)) @@ -45562,7 +32047,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.ftpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.ftpgen_a) (DELAY (ABSOLUTE (PORT clk (1853:1853:1853) (1880:1880:1880)) @@ -45572,7 +32057,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rwpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rwpgen_a) (DELAY (ABSOLUTE (PORT clk (1853:1853:1853) (1880:1880:1880)) @@ -45582,7 +32067,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.dataout_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.dataout_a_register) (DELAY (ABSOLUTE (PORT clk (1812:1812:1812) (1838:1838:1838)) @@ -45596,7 +32081,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.active_core_port_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.active_core_port_b) (DELAY (ABSOLUTE (PORT clk (997:997:997) (1001:1001:1001)) @@ -45605,7 +32090,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rpgen_b) (DELAY (ABSOLUTE (PORT clk (998:998:998) (1002:1002:1002)) @@ -45614,7 +32099,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.ftpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.ftpgen_b) (DELAY (ABSOLUTE (PORT clk (998:998:998) (1002:1002:1002)) @@ -45624,7 +32109,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rwpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rwpgen_b) (DELAY (ABSOLUTE (PORT clk (998:998:998) (1002:1002:1002)) @@ -45633,12 +32118,40 @@ ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[1\]\~1) (DELAY (ABSOLUTE - (PORT d[0] (1152:1152:1152) (1168:1168:1168)) - (PORT clk (1849:1849:1849) (1876:1876:1876)) + (PORT dataa (1142:1142:1142) (1139:1139:1139)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (1584:1584:1584) (1649:1649:1649)) + (PORT datad (1176:1176:1176) (1205:1205:1205)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2019:2019:2019) (2126:2126:2126)) + (PORT d[1] (1666:1666:1666) (1726:1726:1726)) + (PORT d[2] (2398:2398:2398) (2532:2532:2532)) + (PORT d[3] (2708:2708:2708) (2856:2856:2856)) + (PORT d[4] (1028:1028:1028) (1106:1106:1106)) + (PORT d[5] (1544:1544:1544) (1604:1604:1604)) + (PORT d[6] (3201:3201:3201) (3239:3239:3239)) + (PORT d[7] (1837:1837:1837) (1963:1963:1963)) + (PORT d[8] (1554:1554:1554) (1611:1611:1611)) + (PORT d[9] (3400:3400:3400) (3677:3677:3677)) + (PORT d[10] (1240:1240:1240) (1281:1281:1281)) + (PORT d[11] (1473:1473:1473) (1515:1515:1515)) + (PORT d[12] (1982:1982:1982) (2007:2007:2007)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) ) ) (TIMINGCHECK @@ -45647,98 +32160,30 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) (DELAY (ABSOLUTE - (PORT d[0] (3672:3672:3672) (3852:3852:3852)) - (PORT d[1] (1686:1686:1686) (1851:1851:1851)) - (PORT d[2] (1971:1971:1971) (2046:2046:2046)) - (PORT d[3] (2163:2163:2163) (2263:2263:2263)) - (PORT d[4] (2177:2177:2177) (2306:2306:2306)) - (PORT d[5] (1373:1373:1373) (1485:1485:1485)) - (PORT d[6] (1492:1492:1492) (1541:1541:1541)) - (PORT d[7] (1731:1731:1731) (1802:1802:1802)) - (PORT d[8] (3606:3606:3606) (3855:3855:3855)) - (PORT d[9] (3144:3144:3144) (3281:3281:3281)) - (PORT d[10] (3176:3176:3176) (3363:3363:3363)) - (PORT d[11] (2072:2072:2072) (2195:2195:2195)) - (PORT d[12] (1417:1417:1417) (1455:1455:1455)) - (PORT clk (1846:1846:1846) (1872:1872:1872)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1662:1662:1662) (1645:1645:1645)) - (PORT clk (1846:1846:1846) (1872:1872:1872)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1849:1849:1849) (1876:1876:1876)) - (PORT d[0] (2686:2686:2686) (2681:2681:2681)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) + (PORT d[0] (2414:2414:2414) (2383:2383:2383)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1850:1850:1850) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1877:1877:1877)) + (PORT clk (1858:1858:1858) (1884:1884:1884)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1809:1809:1809) (1835:1835:1835)) + (PORT clk (1820:1820:1820) (1846:1846:1846)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -45749,395 +32194,711 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (994:994:994) (998:998:998)) + (PORT clk (1005:1005:1005) (1009:1009:1009)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (995:995:995) (999:999:999)) + (PORT clk (1006:1006:1006) (1010:1010:1010)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (995:995:995) (999:999:999)) + (PORT clk (1006:1006:1006) (1010:1010:1010)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (995:995:995) (999:999:999)) + (PORT clk (1006:1006:1006) (1010:1010:1010)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1803:1803:1803) (1910:1910:1910)) + (PORT d[1] (2308:2308:2308) (2393:2393:2393)) + (PORT d[2] (2037:2037:2037) (2203:2203:2203)) + (PORT d[3] (1874:1874:1874) (1990:1990:1990)) + (PORT d[4] (2328:2328:2328) (2369:2369:2369)) + (PORT d[5] (1694:1694:1694) (1782:1782:1782)) + (PORT d[6] (1733:1733:1733) (1817:1817:1817)) + (PORT d[7] (1535:1535:1535) (1647:1647:1647)) + (PORT d[8] (2183:2183:2183) (2307:2307:2307)) + (PORT d[9] (3031:3031:3031) (3242:3242:3242)) + (PORT d[10] (1585:1585:1585) (1671:1671:1671)) + (PORT d[11] (1956:1956:1956) (2023:2023:2023)) + (PORT d[12] (2060:2060:2060) (2089:2089:2089)) + (PORT clk (1848:1848:1848) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1875:1875:1875)) + (PORT d[0] (2543:2543:2543) (2570:2570:2570)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1811:1811:1811) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE CLOCK_50\~inputclkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (154:154:154) (138:138:138)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~43) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|address_reg_a\[0\]\~feeder) (DELAY (ABSOLUTE - (PORT dataa (980:980:980) (1035:1035:1035)) - (PORT datab (1190:1190:1190) (1238:1238:1238)) - (PORT datac (820:820:820) (836:836:836)) - (PORT datad (1047:1047:1047) (1047:1047:1047)) - (IOPATH dataa combout (341:341:341) (367:367:367)) + (PORT datad (1548:1548:1548) (1588:1588:1588)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|address_reg_a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1529:1529:1529)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1529:1529:1529)) + (PORT asdata (560:560:560) (634:634:634)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (264:264:264) (350:350:350)) + (PORT datab (2598:2598:2598) (2766:2766:2766)) + (PORT datad (1596:1596:1596) (1730:1730:1730)) + (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~44) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|decode2\|eq_node\[1\]\~0) (DELAY (ABSOLUTE - (PORT dataa (1175:1175:1175) (1168:1168:1168)) - (PORT datab (1602:1602:1602) (1692:1692:1692)) - (PORT datac (1163:1163:1163) (1158:1158:1158)) - (PORT datad (312:312:312) (328:328:328)) + (PORT dataa (1201:1201:1201) (1220:1220:1220)) + (PORT datab (238:238:238) (292:292:292)) + (PORT datac (574:574:574) (597:597:597)) + (PORT datad (1616:1616:1616) (1655:1655:1655)) (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vram_address\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (927:927:927) (1008:1008:1008)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vram_address\~0) + (DELAY + (ABSOLUTE + (PORT dataa (774:774:774) (855:855:855)) + (PORT datab (754:754:754) (825:825:825)) + (PORT datac (1156:1156:1156) (1215:1215:1215)) + (PORT datad (683:683:683) (750:750:750)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[0\]) (DELAY (ABSOLUTE - (PORT d[0] (3036:3036:3036) (3209:3209:3209)) - (PORT d[1] (2901:2901:2901) (3127:3127:3127)) - (PORT d[2] (1663:1663:1663) (1761:1761:1761)) - (PORT d[3] (1512:1512:1512) (1583:1583:1583)) - (PORT d[4] (1858:1858:1858) (1967:1967:1967)) - (PORT d[5] (1341:1341:1341) (1451:1451:1451)) - (PORT d[6] (1141:1141:1141) (1162:1162:1162)) - (PORT d[7] (1474:1474:1474) (1532:1532:1532)) - (PORT d[8] (2472:2472:2472) (2678:2678:2678)) - (PORT d[9] (3827:3827:3827) (3998:3998:3998)) - (PORT d[10] (2576:2576:2576) (2725:2725:2725)) - (PORT d[11] (1801:1801:1801) (1882:1882:1882)) - (PORT d[12] (2041:2041:2041) (2064:2064:2064)) - (PORT clk (1849:1849:1849) (1875:1875:1875)) + (PORT clk (1538:1538:1538) (1549:1549:1549)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1195:1195:1195) (1177:1177:1177)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vram_address\[1\]\~feeder) (DELAY (ABSOLUTE - (PORT clk (1849:1849:1849) (1875:1875:1875)) - (PORT d[0] (1267:1267:1267) (1274:1274:1274)) + (PORT datad (908:908:908) (960:960:960)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[1\]) (DELAY (ABSOLUTE - (PORT clk (1850:1850:1850) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1812:1812:1812) (1838:1838:1838)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + (PORT clk (1538:1538:1538) (1549:1549:1549)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1195:1195:1195) (1177:1177:1177)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vram_address\[2\]\~4) (DELAY (ABSOLUTE - (PORT clk (997:997:997) (1001:1001:1001)) + (PORT datac (742:742:742) (821:821:821)) + (IOPATH datac combout (241:241:241) (241:241:241)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[2\]) (DELAY (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1634:1634:1634) (1680:1680:1680)) - (PORT clk (1866:1866:1866) (1893:1893:1893)) + (PORT clk (1538:1538:1538) (1549:1549:1549)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1195:1195:1195) (1177:1177:1177)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add3\~0) (DELAY (ABSOLUTE - (PORT d[0] (2598:2598:2598) (2696:2696:2696)) - (PORT d[1] (2070:2070:2070) (2298:2298:2298)) - (PORT d[2] (2574:2574:2574) (2730:2730:2730)) - (PORT d[3] (2266:2266:2266) (2351:2351:2351)) - (PORT d[4] (2949:2949:2949) (3214:3214:3214)) - (PORT d[5] (2088:2088:2088) (2293:2293:2293)) - (PORT d[6] (1571:1571:1571) (1677:1677:1677)) - (PORT d[7] (2825:2825:2825) (2918:2918:2918)) - (PORT d[8] (2797:2797:2797) (3045:3045:3045)) - (PORT d[9] (2076:2076:2076) (2185:2185:2185)) - (PORT d[10] (1851:1851:1851) (1973:1973:1973)) - (PORT d[11] (3686:3686:3686) (3803:3803:3803)) - (PORT d[12] (1884:1884:1884) (1967:1967:1967)) - (PORT clk (1863:1863:1863) (1889:1889:1889)) + (PORT datac (743:743:743) (822:822:822)) + (PORT datad (1123:1123:1123) (1176:1176:1176)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1538:1538:1538) (1549:1549:1549)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1195:1195:1195) (1177:1177:1177)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.we_a_register) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add3\~1) (DELAY (ABSOLUTE - (PORT d[0] (3175:3175:3175) (3145:3145:3145)) - (PORT clk (1863:1863:1863) (1889:1889:1889)) + (PORT dataa (959:959:959) (1026:1026:1026)) + (PORT datac (742:742:742) (820:820:820)) + (PORT datad (1122:1122:1122) (1177:1177:1177)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1538:1538:1538) (1549:1549:1549)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1195:1195:1195) (1177:1177:1177)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~0) (DELAY (ABSOLUTE - (PORT clk (1866:1866:1866) (1893:1893:1893)) - (PORT d[0] (2870:2870:2870) (2913:2913:2913)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1867:1867:1867) (1894:1894:1894)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1867:1867:1867) (1894:1894:1894)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1867:1867:1867) (1894:1894:1894)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1867:1867:1867) (1894:1894:1894)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1821:1821:1821) (1818:1818:1818)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2160:2160:2160) (2219:2219:2219)) - (PORT clk (1831:1831:1831) (1824:1824:1824)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4537:4537:4537) (4504:4504:4504)) - (PORT d[1] (4325:4325:4325) (4356:4356:4356)) - (PORT d[2] (4543:4543:4543) (4609:4609:4609)) - (PORT d[3] (4478:4478:4478) (4499:4499:4499)) - (PORT d[4] (4324:4324:4324) (4305:4305:4305)) - (PORT d[5] (4367:4367:4367) (4410:4410:4410)) - (PORT d[6] (4631:4631:4631) (4697:4697:4697)) - (PORT d[7] (4151:4151:4151) (4116:4116:4116)) - (PORT d[8] (4445:4445:4445) (4476:4476:4476)) - (PORT d[9] (4629:4629:4629) (4823:4823:4823)) - (PORT d[10] (4475:4475:4475) (4482:4482:4482)) - (PORT d[11] (4668:4668:4668) (4671:4671:4671)) - (PORT d[12] (4491:4491:4491) (4515:4515:4515)) - (PORT clk (1827:1827:1827) (1820:1820:1820)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1831:1831:1831) (1824:1824:1824)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1832:1832:1832) (1825:1825:1825)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1832:1832:1832) (1825:1825:1825)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1832:1832:1832) (1825:1825:1825)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1832:1832:1832) (1825:1825:1825)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + (PORT dataa (932:932:932) (998:998:998)) + (PORT datab (1249:1249:1249) (1307:1307:1307)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~40) + (INSTANCE ula_\|video_\|Add4\~2) (DELAY (ABSOLUTE - (PORT dataa (1345:1345:1345) (1398:1398:1398)) - (PORT datab (279:279:279) (367:367:367)) - (PORT datac (1350:1350:1350) (1376:1376:1376)) - (PORT datad (1465:1465:1465) (1526:1526:1526)) - (IOPATH dataa combout (356:356:356) (368:368:368)) + (PORT datab (982:982:982) (1044:1044:1044)) (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~4) + (DELAY + (ABSOLUTE + (PORT datab (1173:1173:1173) (1231:1231:1231)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~6) + (DELAY + (ABSOLUTE + (PORT datab (762:762:762) (823:823:823)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1537:1537:1537) (1549:1549:1549)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1273:1273:1273) (1275:1275:1275)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~8) + (DELAY + (ABSOLUTE + (PORT datab (949:949:949) (1027:1027:1027)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1537:1537:1537) (1549:1549:1549)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1273:1273:1273) (1275:1275:1275)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~10) + (DELAY + (ABSOLUTE + (PORT dataa (960:960:960) (1019:1019:1019)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1537:1537:1537) (1549:1549:1549)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1273:1273:1273) (1275:1275:1275)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1136:1136:1136) (1207:1207:1207)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Selector6\~0) + (DELAY + (ABSOLUTE + (PORT datab (947:947:947) (1025:1025:1025)) + (PORT datac (317:317:317) (346:346:346)) + (PORT datad (346:346:346) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vram_address\[9\]\~1) (DELAY (ABSOLUTE - (PORT d[0] (1584:1584:1584) (1645:1645:1645)) - (PORT clk (1870:1870:1870) (1897:1897:1897)) + (PORT dataa (772:772:772) (854:854:854)) + (PORT datab (753:753:753) (824:824:824)) + (PORT datac (1159:1159:1159) (1218:1218:1218)) + (PORT datad (684:684:684) (753:753:753)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1538:1538:1538) (1549:1549:1549)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1273:1273:1273) (1272:1272:1272)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~14) + (DELAY + (ABSOLUTE + (PORT datad (902:902:902) (975:975:975)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Selector5\~0) + (DELAY + (ABSOLUTE + (PORT datab (944:944:944) (1027:1027:1027)) + (PORT datac (344:344:344) (370:370:370)) + (PORT datad (346:346:346) (370:370:370)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1538:1538:1538) (1549:1549:1549)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1273:1273:1273) (1272:1272:1272)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vram_address\[10\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (765:765:765) (847:847:847)) + (PORT datab (750:750:750) (819:819:819)) + (PORT datac (1163:1163:1163) (1219:1219:1219)) + (PORT datad (688:688:688) (752:752:752)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vram_address\[10\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (776:776:776) (857:857:857)) + (PORT datab (615:615:615) (632:632:632)) + (PORT datad (176:176:176) (202:202:202)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1537:1537:1537) (1549:1549:1549)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Selector3\~0) + (DELAY + (ABSOLUTE + (PORT datac (911:911:911) (989:989:989)) + (PORT datad (350:350:350) (370:370:370)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1538:1538:1538) (1549:1549:1549)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1273:1273:1273) (1272:1272:1272)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Selector2\~0) + (DELAY + (ABSOLUTE + (PORT datac (911:911:911) (990:990:990)) + (PORT datad (347:347:347) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1538:1538:1538) (1549:1549:1549)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1273:1273:1273) (1272:1272:1272)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1380:1380:1380) (1460:1460:1460)) + (PORT clk (1860:1860:1860) (1888:1888:1888)) ) ) (TIMINGCHECK @@ -46146,23 +32907,23 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2320:2320:2320) (2387:2387:2387)) - (PORT d[1] (2054:2054:2054) (2261:2261:2261)) - (PORT d[2] (2320:2320:2320) (2490:2490:2490)) - (PORT d[3] (2275:2275:2275) (2437:2437:2437)) - (PORT d[4] (2932:2932:2932) (3188:3188:3188)) - (PORT d[5] (2382:2382:2382) (2576:2576:2576)) - (PORT d[6] (1862:1862:1862) (1984:1984:1984)) - (PORT d[7] (2524:2524:2524) (2619:2619:2619)) - (PORT d[8] (3132:3132:3132) (3396:3396:3396)) - (PORT d[9] (1782:1782:1782) (1897:1897:1897)) - (PORT d[10] (1810:1810:1810) (1908:1908:1908)) - (PORT d[11] (2927:2927:2927) (3048:3048:3048)) - (PORT d[12] (1876:1876:1876) (1989:1989:1989)) - (PORT clk (1867:1867:1867) (1893:1893:1893)) + (PORT d[0] (2750:2750:2750) (2962:2962:2962)) + (PORT d[1] (3054:3054:3054) (3174:3174:3174)) + (PORT d[2] (1898:1898:1898) (2003:2003:2003)) + (PORT d[3] (2672:2672:2672) (2885:2885:2885)) + (PORT d[4] (2971:2971:2971) (3095:3095:3095)) + (PORT d[5] (3481:3481:3481) (3602:3602:3602)) + (PORT d[6] (2165:2165:2165) (2264:2264:2264)) + (PORT d[7] (1936:1936:1936) (2113:2113:2113)) + (PORT d[8] (2731:2731:2731) (2831:2831:2831)) + (PORT d[9] (3077:3077:3077) (3162:3162:3162)) + (PORT d[10] (3386:3386:3386) (3609:3609:3609)) + (PORT d[11] (2969:2969:2969) (3152:3152:3152)) + (PORT d[12] (2048:2048:2048) (2158:2158:2158)) + (PORT clk (1857:1857:1857) (1884:1884:1884)) ) ) (TIMINGCHECK @@ -46171,11 +32932,11 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.we_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2203:2203:2203) (2195:2195:2195)) - (PORT clk (1867:1867:1867) (1893:1893:1893)) + (PORT d[0] (3102:3102:3102) (3112:3112:3112)) + (PORT clk (1857:1857:1857) (1884:1884:1884)) ) ) (TIMINGCHECK @@ -46184,60 +32945,60 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1870:1870:1870) (1897:1897:1897)) - (PORT d[0] (3171:3171:3171) (3110:3110:3110)) + (PORT clk (1860:1860:1860) (1888:1888:1888)) + (PORT d[0] (3359:3359:3359) (3390:3390:3390)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1871:1871:1871) (1898:1898:1898)) + (PORT clk (1861:1861:1861) (1889:1889:1889)) (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1871:1871:1871) (1898:1898:1898)) + (PORT clk (1861:1861:1861) (1889:1889:1889)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1871:1871:1871) (1898:1898:1898)) + (PORT clk (1861:1861:1861) (1889:1889:1889)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1871:1871:1871) (1898:1898:1898)) + (PORT clk (1861:1861:1861) (1889:1889:1889)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1825:1825:1825) (1822:1822:1822)) + (PORT clk (1815:1815:1815) (1813:1813:1813)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -46248,11 +33009,11 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_b_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.datain_b_register) (DELAY (ABSOLUTE - (PORT d[0] (2476:2476:2476) (2528:2528:2528)) - (PORT clk (1835:1835:1835) (1828:1828:1828)) + (PORT d[0] (2696:2696:2696) (2893:2893:2893)) + (PORT clk (1825:1825:1825) (1819:1819:1819)) ) ) (TIMINGCHECK @@ -46261,23 +33022,23 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_b_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.addr_b_register) (DELAY (ABSOLUTE - (PORT d[0] (4504:4504:4504) (4508:4508:4508)) - (PORT d[1] (4109:4109:4109) (4118:4118:4118)) - (PORT d[2] (4505:4505:4505) (4547:4547:4547)) - (PORT d[3] (4566:4566:4566) (4624:4624:4624)) - (PORT d[4] (4563:4563:4563) (4541:4541:4541)) - (PORT d[5] (4668:4668:4668) (4705:4705:4705)) - (PORT d[6] (4650:4650:4650) (4703:4703:4703)) - (PORT d[7] (4197:4197:4197) (4161:4161:4161)) - (PORT d[8] (4693:4693:4693) (4743:4743:4743)) - (PORT d[9] (4535:4535:4535) (4748:4748:4748)) - (PORT d[10] (4537:4537:4537) (4522:4522:4522)) - (PORT d[11] (4499:4499:4499) (4551:4551:4551)) - (PORT d[12] (4595:4595:4595) (4623:4623:4623)) - (PORT clk (1831:1831:1831) (1824:1824:1824)) + (PORT d[0] (4089:4089:4089) (4122:4122:4122)) + (PORT d[1] (4121:4121:4121) (4097:4097:4097)) + (PORT d[2] (4114:4114:4114) (4135:4135:4135)) + (PORT d[3] (4139:4139:4139) (4213:4213:4213)) + (PORT d[4] (4181:4181:4181) (4258:4258:4258)) + (PORT d[5] (4447:4447:4447) (4531:4531:4531)) + (PORT d[6] (4238:4238:4238) (4316:4316:4316)) + (PORT d[7] (4193:4193:4193) (4288:4288:4288)) + (PORT d[8] (4190:4190:4190) (4234:4234:4234)) + (PORT d[9] (4277:4277:4277) (4323:4323:4323)) + (PORT d[10] (4109:4109:4109) (4115:4115:4115)) + (PORT d[11] (4356:4356:4356) (4399:4399:4399)) + (PORT d[12] (4034:4034:4034) (4089:4089:4089)) + (PORT clk (1821:1821:1821) (1815:1815:1815)) ) ) (TIMINGCHECK @@ -46286,59 +33047,276 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (1835:1835:1835) (1828:1828:1828)) + (PORT clk (1825:1825:1825) (1819:1819:1819)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_b) (DELAY (ABSOLUTE - (PORT clk (1836:1836:1836) (1829:1829:1829)) + (PORT clk (1826:1826:1826) (1820:1820:1820)) (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1836:1836:1836) (1829:1829:1829)) + (PORT clk (1826:1826:1826) (1820:1820:1820)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1826:1826:1826) (1820:1820:1820)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1826:1826:1826) (1820:1820:1820)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|decode2\|eq_node\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1197:1197:1197) (1221:1221:1221)) + (PORT datab (242:242:242) (297:297:297)) + (PORT datac (571:571:571) (599:599:599)) + (PORT datad (1614:1614:1614) (1658:1658:1658)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1598:1598:1598) (1668:1668:1668)) + (PORT clk (1870:1870:1870) (1896:1896:1896)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2743:2743:2743) (2934:2934:2934)) + (PORT d[1] (2708:2708:2708) (2829:2829:2829)) + (PORT d[2] (2186:2186:2186) (2311:2311:2311)) + (PORT d[3] (2324:2324:2324) (2514:2514:2514)) + (PORT d[4] (2669:2669:2669) (2771:2771:2771)) + (PORT d[5] (3184:3184:3184) (3303:3303:3303)) + (PORT d[6] (2450:2450:2450) (2566:2566:2566)) + (PORT d[7] (1984:1984:1984) (2179:2179:2179)) + (PORT d[8] (2430:2430:2430) (2505:2505:2505)) + (PORT d[9] (2673:2673:2673) (2782:2782:2782)) + (PORT d[10] (4100:4100:4100) (4359:4359:4359)) + (PORT d[11] (2717:2717:2717) (2910:2910:2910)) + (PORT d[12] (2586:2586:2586) (2706:2706:2706)) + (PORT clk (1867:1867:1867) (1892:1892:1892)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2496:2496:2496) (2533:2533:2533)) + (PORT clk (1867:1867:1867) (1892:1892:1892)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1870:1870:1870) (1896:1896:1896)) + (PORT d[0] (3724:3724:3724) (3665:3665:3665)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1871:1871:1871) (1897:1897:1897)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1871:1871:1871) (1897:1897:1897)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1871:1871:1871) (1897:1897:1897)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1871:1871:1871) (1897:1897:1897)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1825:1825:1825) (1821:1821:1821)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2962:2962:2962) (3172:3172:3172)) + (PORT clk (1835:1835:1835) (1827:1827:1827)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4063:4063:4063) (4054:4054:4054)) + (PORT d[1] (4098:4098:4098) (4072:4072:4072)) + (PORT d[2] (4134:4134:4134) (4164:4164:4164)) + (PORT d[3] (4116:4116:4116) (4184:4184:4184)) + (PORT d[4] (4210:4210:4210) (4304:4304:4304)) + (PORT d[5] (4215:4215:4215) (4252:4252:4252)) + (PORT d[6] (4326:4326:4326) (4369:4369:4369)) + (PORT d[7] (4037:4037:4037) (4096:4096:4096)) + (PORT d[8] (4327:4327:4327) (4350:4350:4350)) + (PORT d[9] (4214:4214:4214) (4279:4279:4279)) + (PORT d[10] (4097:4097:4097) (4102:4102:4102)) + (PORT d[11] (4290:4290:4290) (4257:4257:4257)) + (PORT d[12] (4221:4221:4221) (4283:4283:4283)) + (PORT clk (1831:1831:1831) (1823:1823:1823)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1835:1835:1835) (1827:1827:1827)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1836:1836:1836) (1828:1828:1828)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1836:1836:1836) (1828:1828:1828)) (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (1836:1836:1836) (1829:1829:1829)) + (PORT clk (1836:1836:1836) (1828:1828:1828)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (1836:1836:1836) (1829:1829:1829)) + (PORT clk (1836:1836:1836) (1828:1828:1828)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_b_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_b_register) (DELAY (ABSOLUTE - (PORT clk (1827:1827:1827) (1824:1824:1824)) + (PORT clk (1827:1827:1827) (1823:1823:1823)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -46347,144 +33325,47 @@ (HOLD d (posedge clk) (159:159:159)) ) ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (987:987:987) (1035:1035:1035)) - (PORT d[1] (989:989:989) (1045:1045:1045)) - (PORT d[2] (1232:1232:1232) (1248:1248:1248)) - (PORT d[3] (1325:1325:1325) (1386:1386:1386)) - (PORT d[4] (2598:2598:2598) (2808:2808:2808)) - (PORT d[5] (2981:2981:2981) (3208:3208:3208)) - (PORT d[6] (983:983:983) (1027:1027:1027)) - (PORT d[7] (1279:1279:1279) (1356:1356:1356)) - (PORT d[8] (1032:1032:1032) (1055:1055:1055)) - (PORT d[9] (975:975:975) (1020:1020:1020)) - (PORT d[10] (1319:1319:1319) (1384:1384:1384)) - (PORT d[11] (2558:2558:2558) (2742:2742:2742)) - (PORT d[12] (1296:1296:1296) (1368:1368:1368)) - (PORT clk (1857:1857:1857) (1884:1884:1884)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1884:1884:1884)) - (PORT d[0] (574:574:574) (581:581:581)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1885:1885:1885)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1820:1820:1820) (1847:1847:1847)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1010:1010:1010)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1011:1011:1011)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1011:1011:1011)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1011:1011:1011)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~41) + (INSTANCE Selector1\~0) (DELAY (ABSOLUTE - (PORT dataa (1284:1284:1284) (1294:1294:1294)) - (PORT datab (865:865:865) (914:914:914)) - (PORT datac (861:861:861) (866:866:866)) - (PORT datad (181:181:181) (211:211:211)) + (PORT dataa (1388:1388:1388) (1516:1516:1516)) + (PORT datab (866:866:866) (882:882:882)) + (PORT datac (1443:1443:1443) (1490:1490:1490)) + (PORT datad (1435:1435:1435) (1479:1479:1479)) (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~42) + (INSTANCE Selector1\~1) (DELAY (ABSOLUTE - (PORT dataa (209:209:209) (255:255:255)) - (PORT datab (282:282:282) (370:370:370)) - (PORT datac (1627:1627:1627) (1645:1645:1645)) + (PORT dataa (1389:1389:1389) (1516:1516:1516)) + (PORT datab (1129:1129:1129) (1178:1178:1178)) + (PORT datac (1393:1393:1393) (1412:1412:1412)) (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~105) + (INSTANCE D\[1\]\~81) (DELAY (ABSOLUTE - (PORT dataa (199:199:199) (242:242:242)) - (PORT datab (928:928:928) (981:981:981)) - (PORT datac (1193:1193:1193) (1255:1255:1255)) - (PORT datad (572:572:572) (583:583:583)) + (PORT dataa (202:202:202) (246:246:246)) + (PORT datab (1199:1199:1199) (1296:1296:1296)) + (PORT datac (2728:2728:2728) (2883:2883:2883)) + (PORT datad (305:305:305) (322:322:322)) (IOPATH dataa combout (354:354:354) (367:367:367)) (IOPATH datab combout (331:331:331) (342:342:342)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -46494,15 +33375,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~45) + (INSTANCE D\[1\]\~31) (DELAY (ABSOLUTE - (PORT dataa (365:365:365) (410:410:410)) - (PORT datab (234:234:234) (278:278:278)) - (PORT datac (180:180:180) (217:217:217)) - (PORT datad (183:183:183) (212:212:212)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (916:916:916) (932:932:932)) + (PORT datab (917:917:917) (934:934:934)) + (PORT datac (345:345:345) (368:368:368)) + (PORT datad (180:180:180) (209:209:209)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (336:336:336) (342:342:342)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -46510,15 +33391,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~46) + (INSTANCE D\[1\]\~32) (DELAY (ABSOLUTE - (PORT dataa (415:415:415) (501:501:501)) - (PORT datab (234:234:234) (278:278:278)) - (PORT datac (1139:1139:1139) (1183:1183:1183)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (914:914:914) (925:925:925)) + (PORT datab (957:957:957) (1021:1021:1021)) + (PORT datac (1532:1532:1532) (1586:1586:1586)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -46526,28 +33407,60 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[2\]) + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[1\]) (DELAY (ABSOLUTE - (PORT dataa (978:978:978) (1031:1031:1031)) - (PORT datab (648:648:648) (673:673:673)) - (PORT datac (597:597:597) (612:612:612)) - (PORT datad (194:194:194) (219:219:219)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (1428:1428:1428) (1481:1481:1481)) + (PORT datab (219:219:219) (258:258:258)) + (PORT datac (1147:1147:1147) (1143:1143:1143)) + (PORT datad (375:375:375) (401:401:401)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_re\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1218:1218:1218) (1274:1274:1274)) + (PORT datab (229:229:229) (271:271:271)) + (PORT datac (962:962:962) (1042:1042:1042)) + (PORT datad (982:982:982) (1049:1049:1049)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_2) + (DELAY + (ABSOLUTE + (PORT dataa (1430:1430:1430) (1481:1481:1481)) + (PORT datab (1084:1084:1084) (1098:1098:1098)) + (PORT datac (1130:1130:1130) (1197:1197:1197)) + (PORT datad (763:763:763) (761:761:761)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[2\]) + (INSTANCE z80_\|data_pins_\|dout\[1\]) (DELAY (ABSOLUTE - (PORT clk (1525:1525:1525) (1530:1530:1530)) + (PORT clk (1527:1527:1527) (1531:1531:1531)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1245:1245:1245) (1226:1226:1226)) + (PORT ena (819:819:819) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -46558,13 +33471,77 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[2\]\~12) + (INSTANCE z80_\|bus_control_\|db\[1\]\~11) (DELAY (ABSOLUTE - (PORT datab (920:920:920) (962:962:962)) - (PORT datac (944:944:944) (990:990:990)) - (PORT datad (218:218:218) (253:253:253)) - (IOPATH datab combout (306:306:306) (308:308:308)) + (PORT dataa (397:397:397) (444:444:444)) + (PORT datab (200:200:200) (239:239:239)) + (PORT datac (238:238:238) (315:315:315)) + (PORT datad (579:579:579) (606:606:606)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1566:1566:1566) (1548:1548:1548)) + (PORT ena (1684:1684:1684) (1669:1669:1669)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal2\~0) + (DELAY + (ABSOLUTE + (PORT datab (1698:1698:1698) (1757:1757:1757)) + (PORT datac (654:654:654) (719:719:719)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~15) + (DELAY + (ABSOLUTE + (PORT dataa (2188:2188:2188) (2324:2324:2324)) + (PORT datab (969:969:969) (1053:1053:1053)) + (PORT datac (1168:1168:1168) (1226:1226:1226)) + (PORT datad (896:896:896) (972:972:972)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~39) + (DELAY + (ABSOLUTE + (PORT dataa (1007:1007:1007) (1110:1110:1110)) + (PORT datab (1244:1244:1244) (1325:1325:1325)) + (PORT datac (883:883:883) (943:943:943)) + (PORT datad (986:986:986) (1067:1067:1067)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -46572,15 +33549,93 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[2\]\~13) + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~36) (DELAY (ABSOLUTE - (PORT dataa (439:439:439) (507:507:507)) - (PORT datab (236:236:236) (280:280:280)) - (PORT datac (225:225:225) (274:274:274)) - (PORT datad (173:173:173) (199:199:199)) + (PORT datab (610:610:610) (642:642:642)) + (PORT datac (1168:1168:1168) (1225:1225:1225)) + (PORT datad (623:623:623) (639:639:639)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~4) + (DELAY + (ABSOLUTE + (PORT dataa (883:883:883) (944:944:944)) + (PORT datab (920:920:920) (970:970:970)) + (PORT datac (1596:1596:1596) (1726:1726:1726)) + (PORT datad (1620:1620:1620) (1707:1707:1707)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~16) + (DELAY + (ABSOLUTE + (PORT dataa (354:354:354) (391:391:391)) + (PORT datab (2085:2085:2085) (2190:2190:2190)) + (PORT datac (1444:1444:1444) (1488:1488:1488)) + (PORT datad (303:303:303) (318:318:318)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~17) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (242:242:242)) + (PORT datab (214:214:214) (256:256:256)) + (PORT datac (1325:1325:1325) (1351:1351:1351)) + (PORT datad (175:175:175) (201:201:201)) (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1966:1966:1966) (2113:2113:2113)) + (PORT datab (2242:2242:2242) (2358:2358:2358)) + (PORT datac (848:848:848) (890:890:890)) + (PORT datad (647:647:647) (684:684:684)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1133:1133:1133) (1155:1155:1155)) + (PORT datab (2068:2068:2068) (2184:2184:2184)) + (PORT datac (847:847:847) (869:869:869)) + (PORT datad (1033:1033:1033) (1085:1085:1085)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -46588,259 +33643,210 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[2\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT asdata (1864:1864:1864) (1894:1894:1894)) + (PORT ena (981:981:981) (980:980:980)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT asdata (1862:1862:1862) (1894:1894:1894)) + (PORT ena (811:811:811) (804:804:804)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~44) + (DELAY + (ABSOLUTE + (PORT dataa (242:242:242) (328:328:328)) + (PORT datab (256:256:256) (308:308:308)) + (PORT datad (231:231:231) (265:265:265)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1549:1549:1549)) + (PORT asdata (545:545:545) (579:579:579)) + (PORT ena (974:974:974) (969:969:969)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1549:1549:1549)) + (PORT asdata (545:545:545) (579:579:579)) + (PORT ena (975:975:975) (970:970:970)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~43) + (DELAY + (ABSOLUTE + (PORT dataa (405:405:405) (456:456:456)) + (PORT datab (436:436:436) (470:470:470)) + (PORT datad (217:217:217) (286:286:286)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1535:1535:1535)) + (PORT asdata (1249:1249:1249) (1268:1268:1268)) + (PORT ena (1274:1274:1274) (1265:1265:1265)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT asdata (1613:1613:1613) (1650:1650:1650)) + (PORT ena (1200:1200:1200) (1188:1188:1188)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (864:864:864) (935:935:935)) + (PORT datab (580:580:580) (607:607:607)) + (PORT datad (1013:1013:1013) (1025:1025:1025)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~47) + (DELAY + (ABSOLUTE + (PORT datab (955:955:955) (991:991:991)) + (PORT datad (637:637:637) (649:649:649)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1489:1489:1489) (1505:1505:1505)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (790:790:790) (782:782:782)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[3\]) (DELAY (ABSOLUTE (PORT clk (1521:1521:1521) (1534:1534:1534)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1557:1557:1557)) - (PORT ena (1231:1231:1231) (1217:1217:1217)) + (PORT asdata (1241:1241:1241) (1250:1250:1250)) + (PORT ena (1438:1438:1438) (1476:1476:1476)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal3\~1) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~49) (DELAY (ABSOLUTE - (PORT datac (1460:1460:1460) (1533:1533:1533)) - (PORT datad (2264:2264:2264) (2327:2327:2327)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal43\~0) - (DELAY - (ABSOLUTE - (PORT dataa (944:944:944) (975:975:975)) - (PORT datab (940:940:940) (997:997:997)) - (PORT datac (1637:1637:1637) (1758:1758:1758)) - (PORT datad (1220:1220:1220) (1303:1303:1303)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|test1\~2) - (DELAY - (ABSOLUTE - (PORT dataa (198:198:198) (241:241:241)) - (PORT datab (218:218:218) (256:256:256)) - (PORT datac (198:198:198) (235:235:235)) - (PORT datad (195:195:195) (220:220:220)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|test1\~3) - (DELAY - (ABSOLUTE - (PORT dataa (845:845:845) (859:859:859)) - (PORT datab (2054:2054:2054) (2187:2187:2187)) - (PORT datac (1260:1260:1260) (1358:1358:1358)) - (PORT datad (1087:1087:1087) (1084:1084:1084)) + (PORT dataa (697:697:697) (771:771:771)) + (PORT datab (376:376:376) (443:443:443)) + (PORT datad (370:370:370) (395:395:395)) (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|in_nmi_ALTERA_SYNTHESIZED) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1552:1552:1552)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1592:1592:1592) (1568:1568:1568)) - (PORT ena (1669:1669:1669) (1678:1678:1678)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|clk_delay_\|SYNTHESIZED_WIRE_4) - (DELAY - (ABSOLUTE - (PORT dataa (1217:1217:1217) (1308:1308:1308)) - (PORT datab (2052:2052:2052) (2184:2184:2184)) - (PORT datac (1270:1270:1270) (1384:1384:1384)) - (PORT datad (1880:1880:1880) (1934:1934:1934)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|clk_delay_\|SYNTHESIZED_WIRE_7) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1547:1547:1547)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1587:1587:1587) (1563:1563:1563)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|clk_delay_\|hold_clk_iorq) - (DELAY - (ABSOLUTE - (PORT datab (252:252:252) (337:337:337)) - (PORT datad (226:226:226) (299:299:299)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_T1_ff) - (DELAY - (ABSOLUTE - (PORT clk (1540:1540:1540) (1556:1556:1556)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1596:1596:1596) (1571:1571:1571)) - (PORT ena (1939:1939:1939) (2030:2030:2030)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_13) - (DELAY - (ABSOLUTE - (PORT dataa (267:267:267) (353:353:353)) - (PORT datac (1094:1094:1094) (1135:1135:1135)) - (PORT datad (1105:1105:1105) (1151:1151:1151)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_T2_ff) - (DELAY - (ABSOLUTE - (PORT clk (1540:1540:1540) (1556:1556:1556)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1596:1596:1596) (1571:1571:1571)) - (PORT ena (1939:1939:1939) (2030:2030:2030)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|resets_\|x3) - (DELAY - (ABSOLUTE - (PORT dataa (2393:2393:2393) (2551:2551:2551)) - (PORT datac (239:239:239) (317:317:317)) - (PORT datad (1364:1364:1364) (1506:1506:1506)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_12) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1532:1532:1532)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1883:1883:1883) (1869:1869:1869)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_clkctrl") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_12\~clkctrl) - (DELAY - (ABSOLUTE - (PORT inclk[0] (1583:1583:1583) (1637:1637:1637)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_M1_ff) - (DELAY - (ABSOLUTE - (PORT clk (1540:1540:1540) (1556:1556:1556)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1596:1596:1596) (1571:1571:1571)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|DFFE_M2_ff\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1130:1130:1130) (1176:1176:1176)) - (PORT datab (283:283:283) (372:372:372)) - (PORT datad (1106:1106:1106) (1160:1160:1160)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -46848,1071 +33854,56 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_M2_ff) + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[3\]) (DELAY (ABSOLUTE - (PORT clk (1540:1540:1540) (1556:1556:1556)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1596:1596:1596) (1571:1571:1571)) + (PORT clk (1529:1529:1529) (1549:1549:1549)) + (PORT asdata (955:955:955) (966:966:966)) + (PORT ena (1240:1240:1240) (1231:1231:1231)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~3) - (DELAY - (ABSOLUTE - (PORT datac (1051:1051:1051) (1164:1164:1164)) - (PORT datad (2030:2030:2030) (2123:2123:2123)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1463:1463:1463) (1520:1520:1520)) - (PORT datab (853:853:853) (881:881:881)) - (PORT datac (791:791:791) (801:801:801)) - (PORT datad (672:672:672) (691:691:691)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~8) - (DELAY - (ABSOLUTE - (PORT dataa (996:996:996) (1076:1076:1076)) - (PORT datab (661:661:661) (685:685:685)) - (PORT datac (956:956:956) (1008:1008:1008)) - (PORT datad (2243:2243:2243) (2327:2327:2327)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~9) - (DELAY - (ABSOLUTE - (PORT dataa (873:873:873) (910:910:910)) - (PORT datab (847:847:847) (857:857:857)) - (PORT datac (945:945:945) (997:997:997)) - (PORT datad (402:402:402) (435:435:435)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~10) - (DELAY - (ABSOLUTE - (PORT dataa (675:675:675) (725:725:725)) - (PORT datab (334:334:334) (363:363:363)) - (PORT datac (1475:1475:1475) (1542:1542:1542)) - (PORT datad (2078:2078:2078) (2128:2128:2128)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~12) - (DELAY - (ABSOLUTE - (PORT dataa (402:402:402) (429:429:429)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (171:171:171) (203:203:203)) - (PORT datad (180:180:180) (209:209:209)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~15) - (DELAY - (ABSOLUTE - (PORT dataa (2002:2002:2002) (2100:2100:2100)) - (PORT datab (880:880:880) (891:891:891)) - (PORT datac (1448:1448:1448) (1504:1504:1504)) - (PORT datad (181:181:181) (209:209:209)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~6) - (DELAY - (ABSOLUTE - (PORT dataa (231:231:231) (277:277:277)) - (PORT datab (236:236:236) (281:281:281)) - (PORT datac (354:354:354) (382:382:382)) - (PORT datad (1061:1061:1061) (1062:1062:1062)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~7) - (DELAY - (ABSOLUTE - (PORT dataa (231:231:231) (279:279:279)) - (PORT datab (198:198:198) (236:236:236)) - (PORT datac (989:989:989) (1043:1043:1043)) - (PORT datad (780:780:780) (803:803:803)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~13) - (DELAY - (ABSOLUTE - (PORT datab (1104:1104:1104) (1138:1138:1138)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (316:316:316) (336:336:336)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~39) - (DELAY - (ABSOLUTE - (PORT datac (766:766:766) (771:771:771)) - (PORT datad (608:608:608) (623:623:623)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~5) - (DELAY - (ABSOLUTE - (PORT dataa (207:207:207) (252:252:252)) - (PORT datab (2053:2053:2053) (2084:2084:2084)) - (PORT datac (618:618:618) (675:675:675)) - (PORT datad (334:334:334) (341:341:341)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~14) - (DELAY - (ABSOLUTE - (PORT dataa (834:834:834) (843:843:843)) - (PORT datab (877:877:877) (909:909:909)) - (PORT datac (1022:1022:1022) (1035:1035:1035)) - (PORT datad (538:538:538) (551:551:551)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_15) - (DELAY - (ABSOLUTE - (PORT datab (273:273:273) (358:358:358)) - (PORT datac (1093:1093:1093) (1130:1130:1130)) - (PORT datad (1107:1107:1107) (1155:1155:1155)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_T4_ff) - (DELAY - (ABSOLUTE - (PORT clk (1540:1540:1540) (1556:1556:1556)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1596:1596:1596) (1571:1571:1571)) - (PORT ena (1939:1939:1939) (2030:2030:2030)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_16) + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[3\]\~feeder) (DELAY (ABSOLUTE - (PORT dataa (1123:1123:1123) (1157:1157:1157)) - (PORT datac (246:246:246) (327:327:327)) - (PORT datad (1110:1110:1110) (1159:1159:1159)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_T5_ff) - (DELAY - (ABSOLUTE - (PORT clk (1540:1540:1540) (1556:1556:1556)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1596:1596:1596) (1571:1571:1571)) - (PORT ena (1939:1939:1939) (2030:2030:2030)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_17) - (DELAY - (ABSOLUTE - (PORT datab (265:265:265) (348:348:348)) - (PORT datac (1077:1077:1077) (1114:1114:1114)) - (PORT datad (1111:1111:1111) (1161:1161:1161)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|T6) - (DELAY - (ABSOLUTE - (PORT clk (1540:1540:1540) (1556:1556:1556)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1596:1596:1596) (1571:1571:1571)) - (PORT ena (1939:1939:1939) (2030:2030:2030)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~13) - (DELAY - (ABSOLUTE - (PORT dataa (611:611:611) (637:637:637)) - (PORT datab (872:872:872) (895:895:895)) - (PORT datac (589:589:589) (612:612:612)) - (PORT datad (914:914:914) (960:960:960)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal77\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1005:1005:1005) (1115:1115:1115)) - (PORT datab (1187:1187:1187) (1258:1258:1258)) - (PORT datac (655:655:655) (715:715:715)) - (PORT datad (1245:1245:1245) (1328:1328:1328)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~12) - (DELAY - (ABSOLUTE - (PORT dataa (673:673:673) (719:719:719)) - (PORT datab (1671:1671:1671) (1704:1704:1704)) - (PORT datac (864:864:864) (890:890:890)) - (PORT datad (857:857:857) (896:896:896)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~14) - (DELAY - (ABSOLUTE - (PORT datab (197:197:197) (237:237:237)) - (PORT datac (631:631:631) (681:681:681)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~41) - (DELAY - (ABSOLUTE - (PORT dataa (390:390:390) (442:442:442)) - (PORT datac (1069:1069:1069) (1104:1104:1104)) - (PORT datad (202:202:202) (230:230:230)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~42) - (DELAY - (ABSOLUTE - (PORT dataa (937:937:937) (992:992:992)) - (PORT datab (1106:1106:1106) (1172:1172:1172)) - (PORT datac (411:411:411) (452:452:452)) - (PORT datad (2503:2503:2503) (2629:2629:2629)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~43) - (DELAY - (ABSOLUTE - (PORT dataa (2006:2006:2006) (2147:2147:2147)) - (PORT datab (771:771:771) (831:831:831)) - (PORT datac (960:960:960) (989:989:989)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~44) - (DELAY - (ABSOLUTE - (PORT dataa (898:898:898) (941:941:941)) - (PORT datab (355:355:355) (391:391:391)) - (PORT datac (202:202:202) (239:239:239)) - (PORT datad (759:759:759) (760:760:760)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~50) - (DELAY - (ABSOLUTE - (PORT dataa (377:377:377) (403:403:403)) - (PORT datab (1048:1048:1048) (1080:1080:1080)) - (PORT datac (170:170:170) (204:204:204)) - (PORT datad (1303:1303:1303) (1325:1325:1325)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~51) - (DELAY - (ABSOLUTE - (PORT dataa (1126:1126:1126) (1188:1188:1188)) - (PORT datab (198:198:198) (238:238:238)) - (PORT datac (200:200:200) (237:237:237)) - (PORT datad (181:181:181) (212:212:212)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~6) - (DELAY - (ABSOLUTE - (PORT dataa (851:851:851) (871:871:871)) - (PORT datab (1589:1589:1589) (1720:1720:1720)) - (PORT datac (636:636:636) (653:653:653)) - (PORT datad (1694:1694:1694) (1790:1790:1790)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~7) - (DELAY - (ABSOLUTE - (PORT datab (867:867:867) (913:913:913)) - (PORT datac (893:893:893) (946:946:946)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1439:1439:1439) (1482:1482:1482)) - (PORT datab (885:885:885) (895:895:895)) - (PORT datac (878:878:878) (926:926:926)) - (PORT datad (632:632:632) (642:642:642)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1493:1493:1493) (1600:1600:1600)) - (PORT datab (1951:1951:1951) (2023:2023:2023)) - (PORT datac (1350:1350:1350) (1424:1424:1424)) - (PORT datad (1111:1111:1111) (1134:1134:1134)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~10) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (265:265:265)) - (PORT datab (1125:1125:1125) (1164:1164:1164)) - (PORT datac (514:514:514) (525:525:525)) - (PORT datad (639:639:639) (676:676:676)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~11) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (1215:1215:1215) (1255:1255:1255)) - (PORT datac (1013:1013:1013) (1058:1058:1058)) - (PORT datad (342:342:342) (364:364:364)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~17) - (DELAY - (ABSOLUTE - (PORT dataa (621:621:621) (655:655:655)) - (PORT datab (1046:1046:1046) (1078:1078:1078)) - (PORT datac (2017:2017:2017) (2052:2052:2052)) - (PORT datad (621:621:621) (635:635:635)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~31) - (DELAY - (ABSOLUTE - (PORT dataa (629:629:629) (662:662:662)) - (PORT datab (914:914:914) (975:975:975)) - (PORT datac (1817:1817:1817) (1894:1894:1894)) - (PORT datad (898:898:898) (912:912:912)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~28) - (DELAY - (ABSOLUTE - (PORT dataa (358:358:358) (403:403:403)) - (PORT datab (1223:1223:1223) (1259:1259:1259)) - (PORT datac (1402:1402:1402) (1465:1465:1465)) - (PORT datad (856:856:856) (854:854:854)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~30) - (DELAY - (ABSOLUTE - (PORT dataa (863:863:863) (886:886:886)) - (PORT datab (916:916:916) (944:944:944)) - (PORT datac (906:906:906) (930:930:930)) - (PORT datad (843:843:843) (882:882:882)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~32) - (DELAY - (ABSOLUTE - (PORT dataa (921:921:921) (960:960:960)) - (PORT datab (360:360:360) (395:395:395)) - (PORT datac (859:859:859) (902:902:902)) - (PORT datad (1107:1107:1107) (1120:1120:1120)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~33) - (DELAY - (ABSOLUTE - (PORT dataa (593:593:593) (602:602:602)) - (PORT datab (196:196:196) (235:235:235)) - (PORT datac (896:896:896) (935:935:935)) - (PORT datad (173:173:173) (197:197:197)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~25) - (DELAY - (ABSOLUTE - (PORT dataa (1130:1130:1130) (1215:1215:1215)) - (PORT datac (627:627:627) (650:650:650)) - (PORT datad (1592:1592:1592) (1700:1700:1700)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~26) - (DELAY - (ABSOLUTE - (PORT dataa (862:862:862) (906:906:906)) - (PORT datab (1566:1566:1566) (1611:1611:1611)) - (PORT datac (868:868:868) (891:891:891)) - (PORT datad (1122:1122:1122) (1151:1151:1151)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~24) - (DELAY - (ABSOLUTE - (PORT dataa (673:673:673) (723:723:723)) - (PORT datab (660:660:660) (684:684:684)) - (PORT datac (2018:2018:2018) (1985:1985:1985)) - (PORT datad (954:954:954) (1028:1028:1028)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~27) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (643:643:643) (693:693:693)) - (PORT datad (661:661:661) (727:727:727)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~22) - (DELAY - (ABSOLUTE - (PORT dataa (932:932:932) (949:949:949)) - (PORT datab (904:904:904) (924:924:924)) - (PORT datac (888:888:888) (932:932:932)) - (PORT datad (623:623:623) (628:628:628)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1744:1744:1744) (1869:1869:1869)) - (PORT datab (1550:1550:1550) (1688:1688:1688)) - (PORT datac (1209:1209:1209) (1285:1285:1285)) - (PORT datad (1505:1505:1505) (1539:1539:1539)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~53) - (DELAY - (ABSOLUTE - (PORT dataa (965:965:965) (1045:1045:1045)) - (PORT datab (936:936:936) (1009:1009:1009)) - (PORT datac (649:649:649) (669:669:669)) - (PORT datad (1286:1286:1286) (1339:1339:1339)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~23) - (DELAY - (ABSOLUTE - (PORT dataa (198:198:198) (240:240:240)) - (PORT datab (363:363:363) (396:396:396)) - (PORT datac (1524:1524:1524) (1571:1571:1571)) - (PORT datad (171:171:171) (196:196:196)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~18) - (DELAY - (ABSOLUTE - (PORT dataa (372:372:372) (412:412:412)) - (PORT datab (990:990:990) (1020:1020:1020)) - (PORT datac (1523:1523:1523) (1602:1602:1602)) - (PORT datad (193:193:193) (219:219:219)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~19) - (DELAY - (ABSOLUTE - (PORT dataa (627:627:627) (644:644:644)) - (PORT datab (693:693:693) (758:758:758)) - (PORT datac (646:646:646) (704:704:704)) - (PORT datad (1320:1320:1320) (1419:1419:1419)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~20) - (DELAY - (ABSOLUTE - (PORT dataa (625:625:625) (675:675:675)) - (PORT datab (1180:1180:1180) (1218:1218:1218)) - (PORT datac (868:868:868) (922:922:922)) - (PORT datad (604:604:604) (625:625:625)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~34) - (DELAY - (ABSOLUTE - (PORT dataa (612:612:612) (649:649:649)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (309:309:309) (334:334:334)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~52) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (242:242:242)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (312:312:312) (330:330:330)) - (PORT datad (970:970:970) (1032:1032:1032)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_14) - (DELAY - (ABSOLUTE - (PORT dataa (1112:1112:1112) (1167:1167:1167)) - (PORT datac (245:245:245) (326:326:326)) - (PORT datad (1111:1111:1111) (1159:1159:1159)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_T3_ff) - (DELAY - (ABSOLUTE - (PORT clk (1540:1540:1540) (1556:1556:1556)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1596:1596:1596) (1571:1571:1571)) - (PORT ena (1939:1939:1939) (2030:2030:2030)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_1M1T3_3) - (DELAY - (ABSOLUTE - (PORT datac (984:984:984) (1073:1073:1073)) - (PORT datad (1348:1348:1348) (1490:1490:1490)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|in_halt\~0) - (DELAY - (ABSOLUTE - (PORT dataa (361:361:361) (497:497:497)) - (PORT datac (1177:1177:1177) (1261:1261:1261)) - (PORT datad (272:272:272) (353:353:353)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|in_halt\~1) - (DELAY - (ABSOLUTE - (PORT dataa (641:641:641) (697:697:697)) - (PORT datab (1593:1593:1593) (1628:1628:1628)) - (PORT datad (638:638:638) (679:679:679)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|in_halt) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1532:1532:1532)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1575:1575:1575) (1555:1555:1555)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~2) - (DELAY - (ABSOLUTE - (PORT dataa (991:991:991) (1049:1049:1049)) - (PORT datab (1153:1153:1153) (1214:1214:1214)) - (PORT datac (671:671:671) (718:718:718)) - (PORT datad (624:624:624) (674:674:674)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1120:1120:1120) (1227:1227:1227)) - (PORT datab (994:994:994) (1058:1058:1058)) - (PORT datac (1165:1165:1165) (1211:1211:1211)) - (PORT datad (879:879:879) (933:933:933)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~6) - (DELAY - (ABSOLUTE - (PORT dataa (401:401:401) (432:432:432)) - (PORT datab (689:689:689) (742:742:742)) - (PORT datac (882:882:882) (943:943:943)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~4) - (DELAY - (ABSOLUTE - (PORT datac (1080:1080:1080) (1100:1100:1100)) - (PORT datad (647:647:647) (663:663:663)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe) - (DELAY - (ABSOLUTE - (PORT dataa (220:220:220) (263:263:263)) - (PORT datab (954:954:954) (979:979:979)) - (PORT datac (638:638:638) (653:653:653)) - (PORT datad (173:173:173) (197:197:197)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[0\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (254:254:254) (309:309:309)) - (PORT datac (944:944:944) (985:985:985)) (PORT datad (335:335:335) (356:356:356)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]\~93) + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[3\]) (DELAY (ABSOLUTE - (PORT dataa (227:227:227) (285:285:285)) - (PORT datab (780:780:780) (881:881:881)) - (PORT datac (1368:1368:1368) (1458:1458:1458)) - (PORT datad (562:562:562) (568:568:568)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT clk (1529:1529:1529) (1549:1549:1549)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1207:1207:1207) (1180:1180:1180)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]\~94) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~45) (DELAY (ABSOLUTE - (PORT dataa (628:628:628) (659:659:659)) - (PORT datab (733:733:733) (831:831:831)) - (PORT datad (718:718:718) (812:812:812)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT dataa (695:695:695) (736:736:736)) + (PORT datab (706:706:706) (728:728:728)) + (PORT datad (217:217:217) (286:286:286)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -47920,273 +33911,60 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[3\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) + (PORT clk (1522:1522:1522) (1535:1535:1535)) + (PORT asdata (1249:1249:1249) (1271:1271:1271)) + (PORT ena (1243:1243:1243) (1246:1246:1246)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]\~96) - (DELAY - (ABSOLUTE - (PORT dataa (741:741:741) (849:849:849)) - (PORT datab (1176:1176:1176) (1266:1266:1266)) - (PORT datac (727:727:727) (821:821:821)) - (PORT datad (735:735:735) (837:837:837)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]\~98) - (DELAY - (ABSOLUTE - (PORT dataa (204:204:204) (249:249:249)) - (PORT datab (208:208:208) (251:251:251)) - (PORT datad (184:184:184) (213:213:213)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[3\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1573:1573:1573)) + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT asdata (1613:1613:1613) (1651:1651:1651)) + (PORT ena (1220:1220:1220) (1212:1212:1212)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~65) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~48) (DELAY (ABSOLUTE - (PORT dataa (1136:1136:1136) (1168:1168:1168)) - (PORT datab (1145:1145:1145) (1215:1215:1215)) - (PORT datac (215:215:215) (292:292:292)) - (PORT datad (361:361:361) (417:417:417)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]\~99) - (DELAY - (ABSOLUTE - (PORT dataa (783:783:783) (873:873:873)) - (PORT datab (729:729:729) (817:817:817)) - (PORT datac (885:885:885) (954:954:954)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]\~100) - (DELAY - (ABSOLUTE - (PORT dataa (342:342:342) (378:378:378)) - (PORT datab (200:200:200) (239:239:239)) - (PORT datad (735:735:735) (822:822:822)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~101) - (DELAY - (ABSOLUTE - (PORT dataa (745:745:745) (850:850:850)) - (PORT datab (987:987:987) (1082:1082:1082)) - (PORT datad (938:938:938) (1011:1011:1011)) + (PORT dataa (635:635:635) (695:695:695)) + (PORT datab (727:727:727) (792:792:792)) + (PORT datad (659:659:659) (725:725:725)) (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~102) - (DELAY - (ABSOLUTE - (PORT dataa (743:743:743) (852:852:852)) - (PORT datab (723:723:723) (826:826:826)) - (PORT datac (1146:1146:1146) (1231:1231:1231)) - (PORT datad (910:910:910) (977:977:977)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~133) - (DELAY - (ABSOLUTE - (PORT dataa (676:676:676) (704:704:704)) - (PORT datab (200:200:200) (240:240:240)) - (PORT datac (728:728:728) (824:824:824)) - (PORT datad (731:731:731) (831:831:831)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~103) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datad (322:322:322) (345:345:345)) - (IOPATH dataa combout (325:325:325) (328:328:328)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1573:1573:1573)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~66) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~50) (DELAY (ABSOLUTE - (PORT dataa (601:601:601) (622:622:622)) - (PORT datab (422:422:422) (485:485:485)) - (PORT datac (556:556:556) (585:585:585)) - (PORT datad (616:616:616) (671:671:671)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]\~104) - (DELAY - (ABSOLUTE - (PORT dataa (714:714:714) (816:816:816)) - (PORT datab (729:729:729) (827:827:827)) - (PORT datac (720:720:720) (822:822:822)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]\~105) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (245:245:245)) - (PORT datab (367:367:367) (395:395:395)) - (PORT datad (718:718:718) (814:814:814)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~106) - (DELAY - (ABSOLUTE - (PORT dataa (1414:1414:1414) (1548:1548:1548)) - (PORT datab (216:216:216) (261:261:261)) - (PORT datac (959:959:959) (1039:1039:1039)) - (PORT datad (204:204:204) (234:234:234)) + (PORT dataa (608:608:608) (647:647:647)) + (PORT datab (638:638:638) (656:656:656)) + (PORT datac (171:171:171) (205:205:205)) + (PORT datad (610:610:610) (628:628:628)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -48196,15 +33974,199 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Selector5\~1) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~51) (DELAY (ABSOLUTE - (PORT dataa (732:732:732) (817:817:817)) - (PORT datab (665:665:665) (745:745:745)) - (PORT datac (658:658:658) (727:727:727)) - (PORT datad (433:433:433) (505:505:505)) + (PORT dataa (595:595:595) (627:627:627)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datad (343:343:343) (367:367:367)) (IOPATH dataa combout (300:300:300) (308:308:308)) (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~52) + (DELAY + (ABSOLUTE + (PORT dataa (863:863:863) (906:906:906)) + (PORT datab (343:343:343) (371:371:371)) + (PORT datac (599:599:599) (609:609:609)) + (PORT datad (202:202:202) (231:231:231)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_35) + (DELAY + (ABSOLUTE + (PORT dataa (864:864:864) (928:928:928)) + (PORT datab (351:351:351) (388:388:388)) + (PORT datac (1136:1136:1136) (1149:1149:1149)) + (PORT datad (627:627:627) (645:645:645)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1193:1193:1193) (1268:1268:1268)) + (PORT datab (1695:1695:1695) (1875:1875:1875)) + (PORT datac (1375:1375:1375) (1453:1453:1453)) + (PORT datad (819:819:819) (821:821:821)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~16) + (DELAY + (ABSOLUTE + (PORT datab (198:198:198) (236:236:236)) + (PORT datac (180:180:180) (217:217:217)) + (PORT datad (196:196:196) (222:222:222)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~17) + (DELAY + (ABSOLUTE + (PORT dataa (381:381:381) (405:405:405)) + (PORT datab (207:207:207) (249:249:249)) + (PORT datac (192:192:192) (226:226:226)) + (PORT datad (1021:1021:1021) (1018:1018:1018)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1190:1190:1190) (1212:1212:1212)) + (PORT datab (199:199:199) (239:239:239)) + (PORT datac (637:637:637) (676:676:676)) + (PORT datad (591:591:591) (596:596:596)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|flags_xf) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1440:1440:1440) (1432:1432:1432)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[3\]\~33) + (DELAY + (ABSOLUTE + (PORT datab (633:633:633) (647:647:647)) + (PORT datac (1099:1099:1099) (1100:1100:1100)) + (PORT datad (218:218:218) (287:287:287)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sw1_\|db_down\[3\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (868:868:868) (907:907:907)) + (PORT datab (1400:1400:1400) (1399:1399:1399)) + (PORT datac (637:637:637) (697:697:697)) + (PORT datad (635:635:635) (684:684:684)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[3\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (1273:1273:1273) (1305:1305:1305)) + (PORT datab (422:422:422) (447:447:447)) + (PORT datac (343:343:343) (364:364:364)) + (PORT datad (176:176:176) (201:201:201)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[3\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (203:203:203) (247:247:247)) + (PORT datab (390:390:390) (425:425:425)) + (PORT datac (843:843:843) (851:851:851)) + (PORT datad (219:219:219) (253:253:253)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]\~75) + (DELAY + (ABSOLUTE + (PORT dataa (1058:1058:1058) (1138:1138:1138)) + (PORT datac (1183:1183:1183) (1257:1257:1257)) + (PORT datad (647:647:647) (705:705:705)) + (IOPATH dataa combout (325:325:325) (320:320:320)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -48215,56 +34177,88 @@ (INSTANCE ula_\|zx_keyboard_\|Selector5\~0) (DELAY (ABSOLUTE - (PORT dataa (230:230:230) (279:279:279)) - (PORT datab (412:412:412) (492:492:492)) - (PORT datac (628:628:628) (701:701:701)) - (PORT datad (406:406:406) (471:471:471)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (669:669:669) (737:737:737)) + (PORT datab (828:828:828) (850:850:850)) + (PORT datac (461:461:461) (552:552:552)) + (PORT datad (437:437:437) (520:520:520)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~134) + (INSTANCE ula_\|zx_keyboard_\|Selector5\~1) (DELAY (ABSOLUTE - (PORT dataa (377:377:377) (399:399:399)) - (PORT datab (380:380:380) (403:403:403)) - (PORT datad (833:833:833) (879:879:879)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (PORT dataa (1160:1160:1160) (1266:1266:1266)) + (PORT datab (314:314:314) (415:415:415)) + (PORT datac (956:956:956) (1048:1048:1048)) + (PORT datad (944:944:944) (1022:1022:1022)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~132) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (492:492:492) (589:589:589)) + (PORT datad (796:796:796) (841:841:841)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (304:304:304) (308:308:308)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~106) + (DELAY + (ABSOLUTE + (PORT dataa (466:466:466) (564:564:564)) + (PORT datab (1156:1156:1156) (1181:1181:1181)) + (PORT datac (461:461:461) (553:553:553)) + (PORT datad (197:197:197) (223:223:223)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~107) (DELAY (ABSOLUTE - (PORT dataa (740:740:740) (824:824:824)) - (PORT datab (602:602:602) (630:630:630)) - (PORT datac (616:616:616) (675:675:675)) - (PORT datad (531:531:531) (537:537:537)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (508:508:508) (583:583:583)) + (PORT datab (200:200:200) (240:240:240)) + (PORT datac (260:260:260) (347:347:347)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~135) + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~133) (DELAY (ABSOLUTE - (PORT dataa (737:737:737) (827:827:827)) - (PORT datab (274:274:274) (360:360:360)) - (PORT datad (1094:1094:1094) (1148:1148:1148)) + (PORT dataa (516:516:516) (591:591:591)) + (PORT datab (273:273:273) (359:359:359)) + (PORT datad (910:910:910) (996:996:996)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -48277,11 +34271,11 @@ (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~108) (DELAY (ABSOLUTE - (PORT dataa (202:202:202) (245:245:245)) - (PORT datab (365:365:365) (407:407:407)) - (PORT datad (175:175:175) (200:200:200)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datad (197:197:197) (222:222:222)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -48292,9 +34286,9 @@ (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1544:1544:1544)) + (PORT clk (1521:1521:1521) (1535:1535:1535)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) + (PORT clrn (1555:1555:1555) (1548:1548:1548)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -48305,13 +34299,285 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~67) + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]\~104) (DELAY (ABSOLUTE - (PORT dataa (243:243:243) (330:330:330)) - (PORT datab (1198:1198:1198) (1264:1264:1264)) - (PORT datac (618:618:618) (676:676:676)) - (PORT datad (777:777:777) (790:790:790)) + (PORT dataa (987:987:987) (1069:1069:1069)) + (PORT datac (965:965:965) (1038:1038:1038)) + (PORT datad (993:993:993) (1070:1070:1070)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]\~105) + (DELAY + (ABSOLUTE + (PORT dataa (923:923:923) (940:940:940)) + (PORT datab (727:727:727) (802:802:802)) + (PORT datad (176:176:176) (201:201:201)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1558:1558:1558) (1549:1549:1549)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~55) + (DELAY + (ABSOLUTE + (PORT dataa (1111:1111:1111) (1125:1125:1125)) + (PORT datab (660:660:660) (727:727:727)) + (PORT datac (215:215:215) (292:292:292)) + (PORT datad (1016:1016:1016) (1042:1042:1042)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (842:842:842) (929:929:929)) + (PORT datab (1013:1013:1013) (1093:1093:1093)) + (PORT datac (636:636:636) (713:713:713)) + (PORT datad (911:911:911) (1029:1029:1029)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~62) + (DELAY + (ABSOLUTE + (PORT datac (709:709:709) (781:781:781)) + (PORT datad (1541:1541:1541) (1630:1630:1630)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]\~102) + (DELAY + (ABSOLUTE + (PORT dataa (937:937:937) (1030:1030:1030)) + (PORT datab (221:221:221) (260:260:260)) + (PORT datac (952:952:952) (1027:1027:1027)) + (PORT datad (214:214:214) (247:247:247)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]\~103) + (DELAY + (ABSOLUTE + (PORT datab (725:725:725) (803:803:803)) + (PORT datad (841:841:841) (842:842:842)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1558:1558:1558) (1549:1549:1549)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~96) + (DELAY + (ABSOLUTE + (PORT dataa (651:651:651) (684:684:684)) + (PORT datab (1519:1519:1519) (1598:1598:1598)) + (PORT datac (966:966:966) (1036:1036:1036)) + (PORT datad (1155:1155:1155) (1230:1230:1230)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~94) + (DELAY + (ABSOLUTE + (PORT dataa (1009:1009:1009) (1062:1062:1062)) + (PORT datab (950:950:950) (1023:1023:1023)) + (PORT datad (1154:1154:1154) (1231:1231:1231)) + (IOPATH dataa combout (301:301:301) (307:307:307)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]\~95) + (DELAY + (ABSOLUTE + (PORT dataa (1580:1580:1580) (1672:1672:1672)) + (PORT datab (683:683:683) (775:775:775)) + (PORT datac (716:716:716) (784:784:784)) + (PORT datad (974:974:974) (1053:1053:1053)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]\~97) + (DELAY + (ABSOLUTE + (PORT dataa (406:406:406) (433:433:433)) + (PORT datab (397:397:397) (421:421:421)) + (PORT datad (345:345:345) (370:370:370)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1558:1558:1558) (1550:1550:1550)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~45) + (DELAY + (ABSOLUTE + (PORT dataa (1196:1196:1196) (1271:1271:1271)) + (PORT datac (964:964:964) (1033:1033:1033)) + (PORT datad (2207:2207:2207) (2293:2293:2293)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]\~92) + (DELAY + (ABSOLUTE + (PORT dataa (232:232:232) (280:280:280)) + (PORT datab (634:634:634) (648:648:648)) + (PORT datac (690:690:690) (755:755:755)) + (PORT datad (991:991:991) (1066:1066:1066)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]\~93) + (DELAY + (ABSOLUTE + (PORT dataa (990:990:990) (1073:1073:1073)) + (PORT datab (726:726:726) (803:803:803)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1558:1558:1558) (1549:1549:1549)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~53) + (DELAY + (ABSOLUTE + (PORT dataa (682:682:682) (741:741:741)) + (PORT datab (631:631:631) (650:650:650)) + (PORT datac (215:215:215) (290:290:290)) + (PORT datad (1076:1076:1076) (1076:1076:1076)) (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -48321,13 +34587,27 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]\~112) + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~99) (DELAY (ABSOLUTE - (PORT dataa (853:853:853) (877:877:877)) - (PORT datab (222:222:222) (269:269:269)) - (PORT datac (638:638:638) (702:702:702)) - (PORT datad (324:324:324) (344:344:344)) + (PORT datab (944:944:944) (1067:1067:1067)) + (PORT datac (952:952:952) (1022:1022:1022)) + (PORT datad (969:969:969) (1052:1052:1052)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~100) + (DELAY + (ABSOLUTE + (PORT dataa (203:203:203) (248:248:248)) + (PORT datab (240:240:240) (285:285:285)) + (PORT datac (956:956:956) (1028:1028:1028)) + (PORT datad (659:659:659) (739:739:739)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -48337,15 +34617,88 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]\~113) + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~98) (DELAY (ABSOLUTE - (PORT dataa (734:734:734) (817:817:817)) - (PORT datab (201:201:201) (241:241:241)) - (PORT datac (569:569:569) (605:605:605)) - (PORT datad (464:464:464) (535:535:535)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) + (PORT dataa (1005:1005:1005) (1057:1057:1057)) + (PORT datac (967:967:967) (1042:1042:1042)) + (PORT datad (915:915:915) (983:983:983)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~101) + (DELAY + (ABSOLUTE + (PORT dataa (652:652:652) (685:685:685)) + (PORT datab (635:635:635) (652:652:652)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1558:1558:1558) (1549:1549:1549)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\~3) + (DELAY + (ABSOLUTE + (PORT dataa (2700:2700:2700) (2865:2865:2865)) + (PORT datab (1435:1435:1435) (1516:1516:1516)) + (PORT datad (641:641:641) (695:695:695)) + (IOPATH dataa combout (301:301:301) (307:307:307)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~54) + (DELAY + (ABSOLUTE + (PORT dataa (244:244:244) (331:331:331)) + (PORT datab (200:200:200) (239:239:239)) + (PORT datac (1051:1051:1051) (1057:1057:1057)) + (PORT datad (320:320:320) (341:341:341)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~109) + (DELAY + (ABSOLUTE + (PORT datab (952:952:952) (1012:1012:1012)) + (PORT datac (986:986:986) (1057:1057:1057)) + (PORT datad (1124:1124:1124) (1177:1177:1177)) + (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -48353,12 +34706,56 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]\~114) + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~60) (DELAY (ABSOLUTE - (PORT datab (562:562:562) (582:582:582)) - (PORT datad (867:867:867) (872:872:872)) + (PORT datab (1016:1016:1016) (1109:1109:1109)) + (PORT datac (985:985:985) (1055:1055:1055)) (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]\~110) + (DELAY + (ABSOLUTE + (PORT dataa (210:210:210) (259:259:259)) + (PORT datab (1231:1231:1231) (1316:1316:1316)) + (PORT datac (838:838:838) (853:853:853)) + (PORT datad (204:204:204) (233:233:233)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]\~111) + (DELAY + (ABSOLUTE + (PORT dataa (874:874:874) (905:905:905)) + (PORT datab (1046:1046:1046) (1134:1134:1134)) + (PORT datac (317:317:317) (335:335:335)) + (PORT datad (738:738:738) (802:802:802)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]\~112) + (DELAY + (ABSOLUTE + (PORT dataa (224:224:224) (268:268:268)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (325:325:325) (328:328:328)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -48369,9 +34766,9 @@ (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]) (DELAY (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT clk (1518:1518:1518) (1531:1531:1531)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1568:1568:1568) (1563:1563:1563)) + (PORT clrn (1557:1557:1557) (1549:1549:1549)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -48382,46 +34779,60 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~109) + (INSTANCE ula_\|zx_keyboard_\|Selector13\~0) (DELAY (ABSOLUTE - (PORT dataa (740:740:740) (820:820:820)) - (PORT datab (654:654:654) (726:726:726)) - (PORT datac (638:638:638) (703:703:703)) - (PORT datad (802:802:802) (842:842:842)) + (PORT dataa (1514:1514:1514) (1594:1594:1594)) + (PORT datab (919:919:919) (975:975:975)) + (PORT datad (914:914:914) (982:982:982)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~113) + (DELAY + (ABSOLUTE + (PORT dataa (1018:1018:1018) (1098:1098:1098)) + (PORT datab (1231:1231:1231) (1315:1315:1315)) + (PORT datac (986:986:986) (1079:1079:1079)) + (PORT datad (735:735:735) (800:800:800)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~114) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (246:246:246)) + (PORT datab (773:773:773) (840:840:840)) + (PORT datac (346:346:346) (369:369:369)) + (PORT datad (954:954:954) (1014:1014:1014)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~135) + (DELAY + (ABSOLUTE + (PORT dataa (871:871:871) (904:904:904)) + (PORT datab (1043:1043:1043) (1133:1133:1133)) + (PORT datad (174:174:174) (200:200:200)) (IOPATH dataa combout (301:301:301) (299:299:299)) (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~110) - (DELAY - (ABSOLUTE - (PORT dataa (736:736:736) (822:822:822)) - (PORT datab (225:225:225) (273:273:273)) - (PORT datac (173:173:173) (207:207:207)) - (PORT datad (638:638:638) (709:709:709)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~137) - (DELAY - (ABSOLUTE - (PORT dataa (734:734:734) (821:821:821)) - (PORT datab (334:334:334) (362:362:362)) - (PORT datad (340:340:340) (370:370:370)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -48429,14 +34840,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~138) + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~136) (DELAY (ABSOLUTE - (PORT dataa (1042:1042:1042) (1147:1147:1147)) - (PORT datab (671:671:671) (712:712:712)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (351:351:351) (382:382:382)) + (PORT datab (199:199:199) (237:237:237)) + (PORT datad (936:936:936) (977:977:977)) + (IOPATH dataa combout (301:301:301) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -48447,9 +34858,9 @@ (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1544:1544:1544)) + (PORT clk (1518:1518:1518) (1531:1531:1531)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) + (PORT clrn (1557:1557:1557) (1549:1549:1549)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -48460,13 +34871,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|key_row\~2) + (INSTANCE D\[3\]\~56) (DELAY (ABSOLUTE - (PORT datab (1402:1402:1402) (1455:1455:1455)) - (PORT datac (1615:1615:1615) (1701:1701:1701)) - (PORT datad (1189:1189:1189) (1294:1294:1294)) - (IOPATH datab combout (306:306:306) (308:308:308)) + (PORT dataa (1612:1612:1612) (1712:1712:1712)) + (PORT datab (242:242:242) (324:324:324)) + (PORT datac (216:216:216) (293:293:293)) + (PORT datad (622:622:622) (639:639:639)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -48474,43 +34887,27 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~68) + (INSTANCE D\[3\]\~57) (DELAY (ABSOLUTE - (PORT dataa (230:230:230) (277:277:277)) - (PORT datab (1199:1199:1199) (1232:1232:1232)) - (PORT datac (1173:1173:1173) (1255:1255:1255)) - (PORT datad (174:174:174) (198:198:198)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~69) - (DELAY - (ABSOLUTE - (PORT dataa (1123:1123:1123) (1183:1183:1183)) - (PORT datab (3290:3290:3290) (3477:3477:3477)) - (PORT datac (1148:1148:1148) (1200:1200:1200)) - (PORT datad (561:561:561) (572:572:572)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (198:198:198) (236:236:236)) + (PORT datac (839:839:839) (887:887:887)) + (PORT datad (581:581:581) (597:597:597)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.datain_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1048:1048:1048) (1087:1087:1087)) - (PORT clk (1847:1847:1847) (1875:1875:1875)) + (PORT d[0] (1024:1024:1024) (1024:1024:1024)) + (PORT clk (1860:1860:1860) (1887:1887:1887)) ) ) (TIMINGCHECK @@ -48519,23 +34916,23 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.addr_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (3996:3996:3996) (4212:4212:4212)) - (PORT d[1] (1700:1700:1700) (1852:1852:1852)) - (PORT d[2] (1685:1685:1685) (1760:1760:1760)) - (PORT d[3] (1880:1880:1880) (1986:1986:1986)) - (PORT d[4] (2151:2151:2151) (2275:2275:2275)) - (PORT d[5] (1351:1351:1351) (1462:1462:1462)) - (PORT d[6] (1496:1496:1496) (1550:1550:1550)) - (PORT d[7] (3357:3357:3357) (3515:3515:3515)) - (PORT d[8] (3629:3629:3629) (3880:3880:3880)) - (PORT d[9] (1469:1469:1469) (1530:1530:1530)) - (PORT d[10] (3184:3184:3184) (3384:3384:3384)) - (PORT d[11] (2096:2096:2096) (2225:2225:2225)) - (PORT d[12] (1735:1735:1735) (1780:1780:1780)) - (PORT clk (1844:1844:1844) (1871:1871:1871)) + (PORT d[0] (3190:3190:3190) (3440:3440:3440)) + (PORT d[1] (1579:1579:1579) (1682:1682:1682)) + (PORT d[2] (985:985:985) (1036:1036:1036)) + (PORT d[3] (3294:3294:3294) (3529:3529:3529)) + (PORT d[4] (1012:1012:1012) (1054:1054:1054)) + (PORT d[5] (1476:1476:1476) (1548:1548:1548)) + (PORT d[6] (999:999:999) (1021:1021:1021)) + (PORT d[7] (2842:2842:2842) (3107:3107:3107)) + (PORT d[8] (3605:3605:3605) (3755:3755:3755)) + (PORT d[9] (1157:1157:1157) (1203:1203:1203)) + (PORT d[10] (4314:4314:4314) (4615:4615:4615)) + (PORT d[11] (3873:3873:3873) (4130:4130:4130)) + (PORT d[12] (1171:1171:1171) (1229:1229:1229)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) ) ) (TIMINGCHECK @@ -48544,11 +34941,11 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.we_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2569:2569:2569) (2625:2625:2625)) - (PORT clk (1844:1844:1844) (1871:1871:1871)) + (PORT d[0] (1490:1490:1490) (1463:1463:1463)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) ) ) (TIMINGCHECK @@ -48557,60 +34954,60 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.active_core_port_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1847:1847:1847) (1875:1875:1875)) - (PORT d[0] (2985:2985:2985) (3047:3047:3047)) + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (PORT d[0] (2399:2399:2399) (2365:2365:2365)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.wpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1848:1848:1848) (1876:1876:1876)) + (PORT clk (1861:1861:1861) (1888:1888:1888)) (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1848:1848:1848) (1876:1876:1876)) + (PORT clk (1861:1861:1861) (1888:1888:1888)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.ftpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1848:1848:1848) (1876:1876:1876)) + (PORT clk (1861:1861:1861) (1888:1888:1888)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rwpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1848:1848:1848) (1876:1876:1876)) + (PORT clk (1861:1861:1861) (1888:1888:1888)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.dataout_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1807:1807:1807) (1834:1834:1834)) + (PORT clk (1820:1820:1820) (1846:1846:1846)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -48621,38 +35018,38 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.active_core_port_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (992:992:992) (997:997:997)) + (PORT clk (1005:1005:1005) (1009:1009:1009)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (993:993:993) (998:998:998)) + (PORT clk (1006:1006:1006) (1010:1010:1010)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.ftpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (993:993:993) (998:998:998)) + (PORT clk (1006:1006:1006) (1010:1010:1010)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rwpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (993:993:993) (998:998:998)) + (PORT clk (1006:1006:1006) (1010:1010:1010)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) @@ -48662,7 +35059,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (672:672:672) (698:698:698)) + (PORT d[0] (673:673:673) (710:710:710)) (PORT clk (1851:1851:1851) (1879:1879:1879)) ) ) @@ -48675,19 +35072,19 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (3032:3032:3032) (3215:3215:3215)) - (PORT d[1] (1378:1378:1378) (1491:1491:1491)) - (PORT d[2] (2016:2016:2016) (2093:2093:2093)) - (PORT d[3] (2186:2186:2186) (2283:2283:2283)) - (PORT d[4] (1556:1556:1556) (1641:1641:1641)) - (PORT d[5] (1392:1392:1392) (1479:1479:1479)) - (PORT d[6] (1191:1191:1191) (1221:1221:1221)) - (PORT d[7] (3356:3356:3356) (3523:3523:3523)) - (PORT d[8] (2486:2486:2486) (2673:2673:2673)) - (PORT d[9] (3482:3482:3482) (3624:3624:3624)) - (PORT d[10] (2885:2885:2885) (3060:3060:3060)) - (PORT d[11] (1777:1777:1777) (1854:1854:1854)) - (PORT d[12] (1425:1425:1425) (1448:1448:1448)) + (PORT d[0] (1483:1483:1483) (1549:1549:1549)) + (PORT d[1] (4915:4915:4915) (5068:5068:5068)) + (PORT d[2] (2938:2938:2938) (3151:3151:3151)) + (PORT d[3] (1865:1865:1865) (1973:1973:1973)) + (PORT d[4] (1455:1455:1455) (1521:1521:1521)) + (PORT d[5] (1706:1706:1706) (1782:1782:1782)) + (PORT d[6] (1587:1587:1587) (1637:1637:1637)) + (PORT d[7] (2163:2163:2163) (2307:2307:2307)) + (PORT d[8] (2866:2866:2866) (3048:3048:3048)) + (PORT d[9] (2802:2802:2802) (3009:3009:3009)) + (PORT d[10] (2515:2515:2515) (2695:2695:2695)) + (PORT d[11] (2310:2310:2310) (2437:2437:2437)) + (PORT d[12] (3002:3002:3002) (3102:3102:3102)) (PORT clk (1848:1848:1848) (1875:1875:1875)) ) ) @@ -48700,7 +35097,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1966:1966:1966) (1924:1924:1924)) + (PORT d[0] (2297:2297:2297) (2314:2314:2314)) (PORT clk (1848:1848:1848) (1875:1875:1875)) ) ) @@ -48714,7 +35111,7 @@ (DELAY (ABSOLUTE (PORT clk (1851:1851:1851) (1879:1879:1879)) - (PORT d[0] (2989:2989:2989) (2983:2983:2983)) + (PORT d[0] (1975:1975:1975) (1961:1961:1961)) ) ) ) @@ -48810,13 +35207,181 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (937:937:937) (967:967:967)) + (PORT clk (1850:1850:1850) (1878:1878:1878)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1499:1499:1499) (1536:1536:1536)) + (PORT d[1] (1885:1885:1885) (1998:1998:1998)) + (PORT d[2] (1901:1901:1901) (2033:2033:2033)) + (PORT d[3] (1833:1833:1833) (1903:1903:1903)) + (PORT d[4] (1733:1733:1733) (1793:1793:1793)) + (PORT d[5] (1393:1393:1393) (1463:1463:1463)) + (PORT d[6] (1726:1726:1726) (1772:1772:1772)) + (PORT d[7] (1830:1830:1830) (1968:1968:1968)) + (PORT d[8] (2835:2835:2835) (3009:3009:3009)) + (PORT d[9] (3113:3113:3113) (3322:3322:3322)) + (PORT d[10] (1759:1759:1759) (1852:1852:1852)) + (PORT d[11] (2264:2264:2264) (2387:2387:2387)) + (PORT d[12] (2709:2709:2709) (2808:2808:2808)) + (PORT clk (1847:1847:1847) (1874:1874:1874)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1756:1756:1756) (1705:1705:1705)) + (PORT clk (1847:1847:1847) (1874:1874:1874)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1878:1878:1878)) + (PORT d[0] (1769:1769:1769) (1741:1741:1741)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1810:1810:1810) (1837:1837:1837)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (1000:1000:1000)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[3\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (742:742:742) (848:848:848)) + (PORT datab (639:639:639) (650:650:650)) + (PORT datad (894:894:894) (895:895:895)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_ram_register") (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (988:988:988) (1034:1034:1034)) - (PORT clk (1852:1852:1852) (1879:1879:1879)) + (PORT d[0] (963:963:963) (997:997:997)) + (PORT clk (1851:1851:1851) (1879:1879:1879)) ) ) (TIMINGCHECK @@ -48828,20 +35393,20 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (3012:3012:3012) (3174:3174:3174)) - (PORT d[1] (1364:1364:1364) (1477:1477:1477)) - (PORT d[2] (1640:1640:1640) (1735:1735:1735)) - (PORT d[3] (1512:1512:1512) (1577:1577:1577)) - (PORT d[4] (1911:1911:1911) (1988:1988:1988)) - (PORT d[5] (1627:1627:1627) (1743:1743:1743)) - (PORT d[6] (1358:1358:1358) (1370:1370:1370)) - (PORT d[7] (1444:1444:1444) (1493:1493:1493)) - (PORT d[8] (2152:2152:2152) (2337:2337:2337)) - (PORT d[9] (3818:3818:3818) (3964:3964:3964)) - (PORT d[10] (2602:2602:2602) (2756:2756:2756)) - (PORT d[11] (1824:1824:1824) (1907:1907:1907)) - (PORT d[12] (2034:2034:2034) (2077:2077:2077)) - (PORT clk (1849:1849:1849) (1875:1875:1875)) + (PORT d[0] (1776:1776:1776) (1835:1835:1835)) + (PORT d[1] (4575:4575:4575) (4749:4749:4749)) + (PORT d[2] (1693:1693:1693) (1828:1828:1828)) + (PORT d[3] (2896:2896:2896) (3023:3023:3023)) + (PORT d[4] (4166:4166:4166) (4317:4317:4317)) + (PORT d[5] (1736:1736:1736) (1799:1799:1799)) + (PORT d[6] (3621:3621:3621) (3744:3744:3744)) + (PORT d[7] (2168:2168:2168) (2330:2330:2330)) + (PORT d[8] (2799:2799:2799) (2963:2963:2963)) + (PORT d[9] (2778:2778:2778) (2982:2982:2982)) + (PORT d[10] (2510:2510:2510) (2687:2687:2687)) + (PORT d[11] (1966:1966:1966) (2071:2071:2071)) + (PORT d[12] (3629:3629:3629) (3803:3803:3803)) + (PORT clk (1848:1848:1848) (1875:1875:1875)) ) ) (TIMINGCHECK @@ -48853,8 +35418,8 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1660:1660:1660) (1642:1642:1642)) - (PORT clk (1849:1849:1849) (1875:1875:1875)) + (PORT d[0] (1496:1496:1496) (1451:1451:1451)) + (PORT clk (1848:1848:1848) (1875:1875:1875)) ) ) (TIMINGCHECK @@ -48866,8 +35431,8 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1852:1852:1852) (1879:1879:1879)) - (PORT d[0] (2201:2201:2201) (2225:2225:2225)) + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (PORT d[0] (2606:2606:2606) (2654:2654:2654)) ) ) ) @@ -48876,7 +35441,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1853:1853:1853) (1880:1880:1880)) + (PORT clk (1852:1852:1852) (1880:1880:1880)) (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) ) ) @@ -48886,7 +35451,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1853:1853:1853) (1880:1880:1880)) + (PORT clk (1852:1852:1852) (1880:1880:1880)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) @@ -48896,7 +35461,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1853:1853:1853) (1880:1880:1880)) + (PORT clk (1852:1852:1852) (1880:1880:1880)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) @@ -48906,7 +35471,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1853:1853:1853) (1880:1880:1880)) + (PORT clk (1852:1852:1852) (1880:1880:1880)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) @@ -48914,288 +35479,6 @@ (CELL (CELLTYPE "cycloneive_ram_register") (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1812:1812:1812) (1838:1838:1838)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1001:1001:1001)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~73) - (DELAY - (ABSOLUTE - (PORT dataa (627:627:627) (653:653:653)) - (PORT datab (1345:1345:1345) (1422:1422:1422)) - (PORT datac (885:885:885) (921:921:921)) - (PORT datad (1162:1162:1162) (1219:1219:1219)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1287:1287:1287) (1355:1355:1355)) - (PORT clk (1847:1847:1847) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3658:3658:3658) (3886:3886:3886)) - (PORT d[1] (1696:1696:1696) (1864:1864:1864)) - (PORT d[2] (3022:3022:3022) (3145:3145:3145)) - (PORT d[3] (2178:2178:2178) (2273:2273:2273)) - (PORT d[4] (2261:2261:2261) (2381:2381:2381)) - (PORT d[5] (2406:2406:2406) (2602:2602:2602)) - (PORT d[6] (2067:2067:2067) (2147:2147:2147)) - (PORT d[7] (2761:2761:2761) (2873:2873:2873)) - (PORT d[8] (3032:3032:3032) (3240:3240:3240)) - (PORT d[9] (2561:2561:2561) (2657:2657:2657)) - (PORT d[10] (3754:3754:3754) (3977:3977:3977)) - (PORT d[11] (1812:1812:1812) (1889:1889:1889)) - (PORT d[12] (2036:2036:2036) (2121:2121:2121)) - (PORT clk (1844:1844:1844) (1871:1871:1871)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2791:2791:2791) (2784:2784:2784)) - (PORT clk (1844:1844:1844) (1871:1871:1871)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1847:1847:1847) (1875:1875:1875)) - (PORT d[0] (2736:2736:2736) (2702:2702:2702)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1807:1807:1807) (1834:1834:1834)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (992:992:992) (997:997:997)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (993:993:993) (998:998:998)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (993:993:993) (998:998:998)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (993:993:993) (998:998:998)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~74) - (DELAY - (ABSOLUTE - (PORT dataa (1203:1203:1203) (1271:1271:1271)) - (PORT datab (935:935:935) (963:963:963)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (1431:1431:1431) (1479:1479:1479)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3642:3642:3642) (3806:3806:3806)) - (PORT d[1] (2601:2601:2601) (2824:2824:2824)) - (PORT d[2] (1657:1657:1657) (1747:1747:1747)) - (PORT d[3] (2161:2161:2161) (2264:2264:2264)) - (PORT d[4] (1866:1866:1866) (1940:1940:1940)) - (PORT d[5] (1348:1348:1348) (1465:1465:1465)) - (PORT d[6] (1148:1148:1148) (1176:1176:1176)) - (PORT d[7] (1458:1458:1458) (1492:1492:1492)) - (PORT d[8] (2173:2173:2173) (2360:2360:2360)) - (PORT d[9] (3841:3841:3841) (3989:3989:3989)) - (PORT d[10] (2571:2571:2571) (2714:2714:2714)) - (PORT d[11] (2100:2100:2100) (2188:2188:2188)) - (PORT d[12] (2024:2024:2024) (2056:2056:2056)) - (PORT clk (1848:1848:1848) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1875:1875:1875)) - (PORT d[0] (3353:3353:3353) (3478:3478:3478)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1849:1849:1849) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) (DELAY (ABSOLUTE (PORT clk (1811:1811:1811) (1838:1838:1838)) @@ -49209,7 +35492,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) (DELAY (ABSOLUTE (PORT clk (996:996:996) (1001:1001:1001)) @@ -49218,7 +35501,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) (DELAY (ABSOLUTE (PORT clk (997:997:997) (1002:1002:1002)) @@ -49227,7 +35510,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) (DELAY (ABSOLUTE (PORT clk (997:997:997) (1002:1002:1002)) @@ -49237,7 +35520,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) (DELAY (ABSOLUTE (PORT clk (997:997:997) (1002:1002:1002)) @@ -49245,218 +35528,17 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1472:1472:1472) (1543:1543:1543)) - (PORT clk (1846:1846:1846) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3349:3349:3349) (3537:3537:3537)) - (PORT d[1] (2304:2304:2304) (2505:2505:2505)) - (PORT d[2] (2195:2195:2195) (2287:2287:2287)) - (PORT d[3] (1835:1835:1835) (1941:1941:1941)) - (PORT d[4] (2157:2157:2157) (2255:2255:2255)) - (PORT d[5] (1649:1649:1649) (1788:1788:1788)) - (PORT d[6] (1483:1483:1483) (1506:1506:1506)) - (PORT d[7] (1491:1491:1491) (1524:1524:1524)) - (PORT d[8] (2907:2907:2907) (3105:3105:3105)) - (PORT d[9] (2279:2279:2279) (2414:2414:2414)) - (PORT d[10] (2285:2285:2285) (2382:2382:2382)) - (PORT d[11] (2475:2475:2475) (2611:2611:2611)) - (PORT d[12] (1976:1976:1976) (2027:2027:2027)) - (PORT clk (1843:1843:1843) (1871:1871:1871)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2840:2840:2840) (2830:2830:2830)) - (PORT clk (1843:1843:1843) (1871:1871:1871)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1846:1846:1846) (1875:1875:1875)) - (PORT d[0] (3982:3982:3982) (4087:4087:4087)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1847:1847:1847) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1847:1847:1847) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1847:1847:1847) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1847:1847:1847) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1801:1801:1801) (1800:1800:1800)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2301:2301:2301) (2290:2290:2290)) - (PORT clk (1811:1811:1811) (1806:1806:1806)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4340:4340:4340) (4420:4420:4420)) - (PORT d[1] (4239:4239:4239) (4282:4282:4282)) - (PORT d[2] (4257:4257:4257) (4315:4315:4315)) - (PORT d[3] (4538:4538:4538) (4588:4588:4588)) - (PORT d[4] (4287:4287:4287) (4306:4306:4306)) - (PORT d[5] (4351:4351:4351) (4371:4371:4371)) - (PORT d[6] (4481:4481:4481) (4572:4572:4572)) - (PORT d[7] (4342:4342:4342) (4398:4398:4398)) - (PORT d[8] (4597:4597:4597) (4592:4592:4592)) - (PORT d[9] (4469:4469:4469) (4739:4739:4739)) - (PORT d[10] (4352:4352:4352) (4394:4394:4394)) - (PORT d[11] (4350:4350:4350) (4370:4370:4370)) - (PORT d[12] (4626:4626:4626) (4608:4608:4608)) - (PORT clk (1807:1807:1807) (1802:1802:1802)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1811:1811:1811) (1806:1806:1806)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1812:1812:1812) (1807:1807:1807)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1812:1812:1812) (1807:1807:1807)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1812:1812:1812) (1807:1807:1807)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1812:1812:1812) (1807:1807:1807)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~70) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[3\]\~7) (DELAY (ABSOLUTE - (PORT dataa (886:886:886) (944:944:944)) - (PORT datab (1682:1682:1682) (1751:1751:1751)) - (PORT datac (910:910:910) (950:950:950)) - (PORT datad (1193:1193:1193) (1243:1243:1243)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT dataa (1555:1555:1555) (1629:1629:1629)) + (PORT datab (1068:1068:1068) (1073:1073:1073)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (920:920:920) (938:938:938)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -49467,20 +35549,20 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (3603:3603:3603) (3780:3780:3780)) - (PORT d[1] (2612:2612:2612) (2820:2820:2820)) - (PORT d[2] (1542:1542:1542) (1613:1613:1613)) - (PORT d[3] (2126:2126:2126) (2248:2248:2248)) - (PORT d[4] (2158:2158:2158) (2252:2252:2252)) - (PORT d[5] (1643:1643:1643) (1776:1776:1776)) - (PORT d[6] (1395:1395:1395) (1417:1417:1417)) - (PORT d[7] (1473:1473:1473) (1509:1509:1509)) - (PORT d[8] (2157:2157:2157) (2322:2322:2322)) - (PORT d[9] (2292:2292:2292) (2444:2444:2444)) - (PORT d[10] (2276:2276:2276) (2402:2402:2402)) - (PORT d[11] (2115:2115:2115) (2225:2225:2225)) - (PORT d[12] (2288:2288:2288) (2338:2338:2338)) - (PORT clk (1846:1846:1846) (1873:1873:1873)) + (PORT d[0] (3390:3390:3390) (3666:3666:3666)) + (PORT d[1] (4281:4281:4281) (4436:4436:4436)) + (PORT d[2] (2345:2345:2345) (2515:2515:2515)) + (PORT d[3] (2564:2564:2564) (2692:2692:2692)) + (PORT d[4] (4103:4103:4103) (4254:4254:4254)) + (PORT d[5] (2082:2082:2082) (2178:2178:2178)) + (PORT d[6] (3273:3273:3273) (3383:3383:3383)) + (PORT d[7] (3289:3289:3289) (3476:3476:3476)) + (PORT d[8] (2493:2493:2493) (2604:2604:2604)) + (PORT d[9] (2780:2780:2780) (2975:2975:2975)) + (PORT d[10] (2224:2224:2224) (2398:2398:2398)) + (PORT d[11] (2350:2350:2350) (2448:2448:2448)) + (PORT d[12] (3337:3337:3337) (3492:3492:3492)) + (PORT clk (1847:1847:1847) (1874:1874:1874)) ) ) (TIMINGCHECK @@ -49492,8 +35574,8 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1846:1846:1846) (1873:1873:1873)) - (PORT d[0] (3448:3448:3448) (3327:3327:3327)) + (PORT clk (1847:1847:1847) (1874:1874:1874)) + (PORT d[0] (4670:4670:4670) (4544:4544:4544)) ) ) ) @@ -49502,7 +35584,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1847:1847:1847) (1874:1874:1874)) + (PORT clk (1848:1848:1848) (1875:1875:1875)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) @@ -49512,7 +35594,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1809:1809:1809) (1836:1836:1836)) + (PORT clk (1810:1810:1810) (1837:1837:1837)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -49526,7 +35608,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (994:994:994) (999:999:999)) + (PORT clk (995:995:995) (1000:1000:1000)) ) ) ) @@ -49535,7 +35617,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (995:995:995) (1000:1000:1000)) + (PORT clk (996:996:996) (1001:1001:1001)) ) ) ) @@ -49544,7 +35626,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (995:995:995) (1000:1000:1000)) + (PORT clk (996:996:996) (1001:1001:1001)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) @@ -49554,24 +35636,306 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (995:995:995) (1000:1000:1000)) + (PORT clk (996:996:996) (1001:1001:1001)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~71) + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) (DELAY (ABSOLUTE - (PORT dataa (230:230:230) (276:276:276)) - (PORT datab (906:906:906) (941:941:941)) - (PORT datac (1129:1129:1129) (1177:1177:1177)) - (PORT datad (181:181:181) (209:209:209)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT d[0] (2571:2571:2571) (2717:2717:2717)) + (PORT d[1] (2866:2866:2866) (2983:2983:2983)) + (PORT d[2] (2017:2017:2017) (2175:2175:2175)) + (PORT d[3] (2450:2450:2450) (2565:2565:2565)) + (PORT d[4] (2353:2353:2353) (2464:2464:2464)) + (PORT d[5] (2400:2400:2400) (2521:2521:2521)) + (PORT d[6] (3248:3248:3248) (3366:3366:3366)) + (PORT d[7] (2069:2069:2069) (2197:2197:2197)) + (PORT d[8] (2413:2413:2413) (2506:2506:2506)) + (PORT d[9] (3015:3015:3015) (3237:3237:3237)) + (PORT d[10] (3895:3895:3895) (4155:4155:4155)) + (PORT d[11] (2298:2298:2298) (2420:2420:2420)) + (PORT d[12] (2690:2690:2690) (2811:2811:2811)) + (PORT clk (1859:1859:1859) (1885:1885:1885)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1885:1885:1885)) + (PORT d[0] (3635:3635:3635) (3699:3699:3699)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1886:1886:1886)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1822:1822:1822) (1848:1848:1848)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1007:1007:1007) (1011:1011:1011)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1008:1008:1008) (1012:1012:1012)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1008:1008:1008) (1012:1012:1012)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1008:1008:1008) (1012:1012:1012)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1618:1618:1618) (1721:1721:1721)) + (PORT clk (1848:1848:1848) (1876:1876:1876)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3132:3132:3132) (3373:3373:3373)) + (PORT d[1] (3979:3979:3979) (4148:4148:4148)) + (PORT d[2] (2052:2052:2052) (2220:2220:2220)) + (PORT d[3] (2223:2223:2223) (2345:2345:2345)) + (PORT d[4] (3835:3835:3835) (3970:3970:3970)) + (PORT d[5] (2376:2376:2376) (2490:2490:2490)) + (PORT d[6] (3017:3017:3017) (3129:3129:3129)) + (PORT d[7] (3020:3020:3020) (3170:3170:3170)) + (PORT d[8] (2470:2470:2470) (2585:2585:2585)) + (PORT d[9] (2475:2475:2475) (2647:2647:2647)) + (PORT d[10] (2936:2936:2936) (3120:3120:3120)) + (PORT d[11] (2315:2315:2315) (2426:2426:2426)) + (PORT d[12] (3050:3050:3050) (3185:3185:3185)) + (PORT clk (1845:1845:1845) (1872:1872:1872)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2050:2050:2050) (2036:2036:2036)) + (PORT clk (1845:1845:1845) (1872:1872:1872)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1876:1876:1876)) + (PORT d[0] (5470:5470:5470) (5591:5591:5591)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1803:1803:1803) (1801:1801:1801)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2106:2106:2106) (2320:2320:2320)) + (PORT clk (1813:1813:1813) (1807:1807:1807)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4170:4170:4170) (4263:4263:4263)) + (PORT d[1] (4283:4283:4283) (4356:4356:4356)) + (PORT d[2] (4122:4122:4122) (4213:4213:4213)) + (PORT d[3] (4257:4257:4257) (4365:4365:4365)) + (PORT d[4] (4105:4105:4105) (4265:4265:4265)) + (PORT d[5] (4360:4360:4360) (4467:4467:4467)) + (PORT d[6] (4086:4086:4086) (4153:4153:4153)) + (PORT d[7] (4082:4082:4082) (4201:4201:4201)) + (PORT d[8] (4244:4244:4244) (4296:4296:4296)) + (PORT d[9] (4129:4129:4129) (4241:4241:4241)) + (PORT d[10] (4179:4179:4179) (4236:4236:4236)) + (PORT d[11] (4332:4332:4332) (4408:4408:4408)) + (PORT d[12] (4199:4199:4199) (4244:4244:4244)) + (PORT clk (1809:1809:1809) (1803:1803:1803)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1813:1813:1813) (1807:1807:1807)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1814:1814:1814) (1808:1808:1808)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1814:1814:1814) (1808:1808:1808)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1814:1814:1814) (1808:1808:1808)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1814:1814:1814) (1808:1808:1808)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) @@ -49580,7 +35944,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1549:1549:1549) (1631:1631:1631)) + (PORT d[0] (1626:1626:1626) (1746:1746:1746)) (PORT clk (1862:1862:1862) (1888:1888:1888)) ) ) @@ -49593,19 +35957,19 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2520:2520:2520) (2617:2617:2617)) - (PORT d[1] (1962:1962:1962) (2122:2122:2122)) - (PORT d[2] (1955:1955:1955) (2077:2077:2077)) - (PORT d[3] (1876:1876:1876) (2000:2000:2000)) - (PORT d[4] (2723:2723:2723) (2864:2864:2864)) - (PORT d[5] (2232:2232:2232) (2416:2416:2416)) - (PORT d[6] (2043:2043:2043) (2115:2115:2115)) - (PORT d[7] (2404:2404:2404) (2531:2531:2531)) - (PORT d[8] (2398:2398:2398) (2577:2577:2577)) - (PORT d[9] (1996:1996:1996) (2101:2101:2101)) - (PORT d[10] (1691:1691:1691) (1769:1769:1769)) - (PORT d[11] (2047:2047:2047) (2128:2128:2128)) - (PORT d[12] (2520:2520:2520) (2605:2605:2605)) + (PORT d[0] (3032:3032:3032) (3145:3145:3145)) + (PORT d[1] (3400:3400:3400) (3508:3508:3508)) + (PORT d[2] (2324:2324:2324) (2504:2504:2504)) + (PORT d[3] (2415:2415:2415) (2549:2549:2549)) + (PORT d[4] (2681:2681:2681) (2805:2805:2805)) + (PORT d[5] (2687:2687:2687) (2824:2824:2824)) + (PORT d[6] (3773:3773:3773) (3895:3895:3895)) + (PORT d[7] (2122:2122:2122) (2230:2230:2230)) + (PORT d[8] (2623:2623:2623) (2737:2737:2737)) + (PORT d[9] (3006:3006:3006) (3209:3209:3209)) + (PORT d[10] (3661:3661:3661) (3927:3927:3927)) + (PORT d[11] (2644:2644:2644) (2790:2790:2790)) + (PORT d[12] (2960:2960:2960) (3114:3114:3114)) (PORT clk (1859:1859:1859) (1884:1884:1884)) ) ) @@ -49618,7 +35982,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2655:2655:2655) (2640:2640:2640)) + (PORT d[0] (2559:2559:2559) (2640:2640:2640)) (PORT clk (1859:1859:1859) (1884:1884:1884)) ) ) @@ -49632,7 +35996,7 @@ (DELAY (ABSOLUTE (PORT clk (1862:1862:1862) (1888:1888:1888)) - (PORT d[0] (3407:3407:3407) (3339:3339:3339)) + (PORT d[0] (4980:4980:4980) (4896:4896:4896)) ) ) ) @@ -49695,7 +36059,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_b_register) (DELAY (ABSOLUTE - (PORT d[0] (2066:2066:2066) (2077:2077:2077)) + (PORT d[0] (1009:1009:1009) (1040:1040:1040)) (PORT clk (1827:1827:1827) (1819:1819:1819)) ) ) @@ -49708,19 +36072,19 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_b_register) (DELAY (ABSOLUTE - (PORT d[0] (4618:4618:4618) (4692:4692:4692)) - (PORT d[1] (4233:4233:4233) (4271:4271:4271)) - (PORT d[2] (4532:4532:4532) (4592:4592:4592)) - (PORT d[3] (4449:4449:4449) (4489:4489:4489)) - (PORT d[4] (4330:4330:4330) (4336:4336:4336)) - (PORT d[5] (4590:4590:4590) (4607:4607:4607)) - (PORT d[6] (4724:4724:4724) (4801:4801:4801)) - (PORT d[7] (4565:4565:4565) (4613:4613:4613)) - (PORT d[8] (4569:4569:4569) (4629:4629:4629)) - (PORT d[9] (4484:4484:4484) (4751:4751:4751)) - (PORT d[10] (4377:4377:4377) (4395:4395:4395)) - (PORT d[11] (4636:4636:4636) (4682:4682:4682)) - (PORT d[12] (4604:4604:4604) (4754:4754:4754)) + (PORT d[0] (4206:4206:4206) (4219:4219:4219)) + (PORT d[1] (4225:4225:4225) (4248:4248:4248)) + (PORT d[2] (4205:4205:4205) (4256:4256:4256)) + (PORT d[3] (4155:4155:4155) (4223:4223:4223)) + (PORT d[4] (4145:4145:4145) (4273:4273:4273)) + (PORT d[5] (4334:4334:4334) (4436:4436:4436)) + (PORT d[6] (4172:4172:4172) (4239:4239:4239)) + (PORT d[7] (4081:4081:4081) (4200:4200:4200)) + (PORT d[8] (4275:4275:4275) (4413:4413:4413)) + (PORT d[9] (4093:4093:4093) (4197:4197:4197)) + (PORT d[10] (4212:4212:4212) (4265:4265:4265)) + (PORT d[11] (4197:4197:4197) (4204:4204:4204)) + (PORT d[12] (4233:4233:4233) (4300:4300:4300)) (PORT clk (1823:1823:1823) (1815:1815:1815)) ) ) @@ -49793,15 +36157,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~72) + (INSTANCE Selector3\~1) (DELAY (ABSOLUTE - (PORT dataa (887:887:887) (946:946:946)) - (PORT datab (206:206:206) (248:248:248)) - (PORT datac (171:171:171) (205:205:205)) - (PORT datad (1482:1482:1482) (1521:1521:1521)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT dataa (626:626:626) (676:676:676)) + (PORT datab (1763:1763:1763) (1794:1794:1794)) + (PORT datac (1241:1241:1241) (1286:1286:1286)) + (PORT datad (1522:1522:1522) (1589:1589:1589)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -49809,15 +36173,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~108) + (INSTANCE Selector3\~2) (DELAY (ABSOLUTE - (PORT dataa (1613:1613:1613) (1669:1669:1669)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (1616:1616:1616) (1701:1701:1701)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (PORT dataa (1323:1323:1323) (1337:1337:1337)) + (PORT datab (1761:1761:1761) (1795:1795:1795)) + (PORT datac (1720:1720:1720) (1775:1775:1775)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -49825,13 +36189,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~95) + (INSTANCE D\[3\]\~85) (DELAY (ABSOLUTE - (PORT dataa (209:209:209) (257:257:257)) - (PORT datab (1399:1399:1399) (1458:1458:1458)) - (PORT datac (1325:1325:1325) (1390:1390:1390)) - (PORT datad (341:341:341) (359:359:359)) + (PORT dataa (1884:1884:1884) (2060:2060:2060)) + (PORT datab (3102:3102:3102) (3317:3317:3317)) + (PORT datac (173:173:173) (206:206:206)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~73) + (DELAY + (ABSOLUTE + (PORT dataa (2216:2216:2216) (2293:2293:2293)) + (PORT datab (1657:1657:1657) (1691:1691:1691)) + (PORT datac (1127:1127:1127) (1190:1190:1190)) + (PORT datad (180:180:180) (207:207:207)) (IOPATH dataa combout (327:327:327) (347:347:347)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (243:243:243) (241:241:241)) @@ -49841,16 +36221,16 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~96) + (INSTANCE D\[3\]\~74) (DELAY (ABSOLUTE - (PORT dataa (1628:1628:1628) (1657:1657:1657)) - (PORT datab (1397:1397:1397) (1455:1455:1455)) - (PORT datac (1102:1102:1102) (1179:1179:1179)) - (PORT datad (313:313:313) (331:331:331)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (1969:1969:1969) (2019:2019:2019)) + (PORT datab (1656:1656:1656) (1689:1689:1689)) + (PORT datac (1631:1631:1631) (1668:1668:1668)) + (PORT datad (172:172:172) (198:198:198)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -49860,12 +36240,12 @@ (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[3\]) (DELAY (ABSOLUTE - (PORT dataa (975:975:975) (1040:1040:1040)) - (PORT datab (1658:1658:1658) (1724:1724:1724)) - (PORT datac (239:239:239) (291:291:291)) - (PORT datad (875:875:875) (896:896:896)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) + (PORT dataa (1427:1427:1427) (1480:1480:1480)) + (PORT datab (401:401:401) (439:439:439)) + (PORT datac (825:825:825) (872:872:872)) + (PORT datad (1491:1491:1491) (1510:1510:1510)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (306:306:306) (311:311:311)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -49876,9 +36256,9 @@ (INSTANCE z80_\|data_pins_\|dout\[3\]) (DELAY (ABSOLUTE - (PORT clk (1526:1526:1526) (1531:1531:1531)) + (PORT clk (1527:1527:1527) (1531:1531:1531)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (841:841:841) (846:846:846)) + (PORT ena (819:819:819) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -49892,11 +36272,11 @@ (INSTANCE z80_\|bus_control_\|db\[3\]\~20) (DELAY (ABSOLUTE - (PORT dataa (252:252:252) (310:310:310)) - (PORT datab (660:660:660) (727:727:727)) - (PORT datad (213:213:213) (248:248:248)) - (IOPATH dataa combout (301:301:301) (307:307:307)) - (IOPATH datab combout (300:300:300) (311:311:311)) + (PORT datab (360:360:360) (398:398:398)) + (PORT datac (336:336:336) (367:367:367)) + (PORT datad (376:376:376) (438:438:438)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -49906,26 +36286,38 @@ (INSTANCE z80_\|bus_control_\|db\[3\]\~21) (DELAY (ABSOLUTE - (PORT dataa (984:984:984) (1009:1009:1009)) - (PORT datab (906:906:906) (952:952:952)) - (PORT datac (884:884:884) (932:932:932)) - (PORT datad (924:924:924) (947:947:947)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (723:723:723) (780:780:780)) + (PORT datab (692:692:692) (741:741:741)) + (PORT datac (595:595:595) (638:638:638)) + (PORT datad (1670:1670:1670) (1692:1692:1692)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[3\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\~2) (DELAY (ABSOLUTE - (PORT clk (1525:1525:1525) (1541:1541:1541)) + (PORT datab (274:274:274) (330:330:330)) + (PORT datac (247:247:247) (310:310:310)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|interrupts_\|im2) + (DELAY + (ABSOLUTE + (PORT clk (1541:1541:1541) (1557:1557:1557)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1571:1571:1571) (1550:1550:1550)) - (PORT ena (1479:1479:1479) (1488:1488:1488)) + (PORT clrn (1567:1567:1567) (1549:1549:1549)) + (PORT ena (1482:1482:1482) (1498:1498:1498)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -49937,13 +36329,2008 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~4) + (INSTANCE z80_\|execute_\|ctl_mRead\~10) (DELAY (ABSOLUTE - (PORT dataa (1465:1465:1465) (1561:1561:1561)) - (PORT datab (1173:1173:1173) (1201:1201:1201)) - (PORT datac (1193:1193:1193) (1280:1280:1280)) - (PORT datad (1406:1406:1406) (1444:1444:1444)) + (PORT dataa (501:501:501) (579:579:579)) + (PORT datab (879:879:879) (976:976:976)) + (PORT datac (269:269:269) (359:359:359)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_mask543_en\~0) + (DELAY + (ABSOLUTE + (PORT dataa (508:508:508) (587:587:587)) + (PORT datab (220:220:220) (259:259:259)) + (PORT datac (616:616:616) (616:616:616)) + (PORT datad (893:893:893) (913:913:913)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[7\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1352:1352:1352) (1488:1488:1488)) + (PORT datab (576:576:576) (605:605:605)) + (PORT datac (832:832:832) (842:842:842)) + (PORT datad (545:545:545) (557:557:557)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[7\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (922:922:922) (952:952:952)) + (PORT datab (368:368:368) (387:387:387)) + (PORT datac (565:565:565) (583:583:583)) + (PORT datad (202:202:202) (230:230:230)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[7\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (861:861:861) (886:886:886)) + (PORT datab (673:673:673) (695:695:695)) + (PORT datac (404:404:404) (447:447:447)) + (PORT datad (172:172:172) (198:198:198)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[7\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datad (362:362:362) (387:387:387)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[7\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1415:1415:1415) (1446:1446:1446)) + (PORT datab (362:362:362) (395:395:395)) + (PORT datad (1352:1352:1352) (1361:1361:1361)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[5\]\~67) + (DELAY + (ABSOLUTE + (PORT dataa (249:249:249) (305:305:305)) + (PORT datab (2795:2795:2795) (2985:2985:2985)) + (PORT datac (554:554:554) (576:576:576)) + (PORT datad (606:606:606) (625:625:625)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (433:433:433) (451:451:451)) + (PORT clk (1858:1858:1858) (1886:1886:1886)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3321:3321:3321) (3530:3530:3530)) + (PORT d[1] (1554:1554:1554) (1635:1635:1635)) + (PORT d[2] (1866:1866:1866) (1937:1937:1937)) + (PORT d[3] (2650:2650:2650) (2849:2849:2849)) + (PORT d[4] (3248:3248:3248) (3394:3394:3394)) + (PORT d[5] (3980:3980:3980) (4138:4138:4138)) + (PORT d[6] (1598:1598:1598) (1673:1673:1673)) + (PORT d[7] (2269:2269:2269) (2463:2463:2463)) + (PORT d[8] (3003:3003:3003) (3126:3126:3126)) + (PORT d[9] (1757:1757:1757) (1842:1842:1842)) + (PORT d[10] (3962:3962:3962) (4221:4221:4221)) + (PORT d[11] (3574:3574:3574) (3779:3779:3779)) + (PORT d[12] (1770:1770:1770) (1850:1850:1850)) + (PORT clk (1855:1855:1855) (1882:1882:1882)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1797:1797:1797) (1804:1804:1804)) + (PORT clk (1855:1855:1855) (1882:1882:1882)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1886:1886:1886)) + (PORT d[0] (2686:2686:2686) (2697:2697:2697)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1818:1818:1818) (1845:1845:1845)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1003:1003:1003) (1008:1008:1008)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1009:1009:1009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1009:1009:1009)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1009:1009:1009)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (713:713:713) (729:729:729)) + (PORT clk (1859:1859:1859) (1886:1886:1886)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3609:3609:3609) (3820:3820:3820)) + (PORT d[1] (1588:1588:1588) (1675:1675:1675)) + (PORT d[2] (1578:1578:1578) (1673:1673:1673)) + (PORT d[3] (2934:2934:2934) (3140:3140:3140)) + (PORT d[4] (3540:3540:3540) (3690:3690:3690)) + (PORT d[5] (4008:4008:4008) (4175:4175:4175)) + (PORT d[6] (1596:1596:1596) (1649:1649:1649)) + (PORT d[7] (2297:2297:2297) (2486:2486:2486)) + (PORT d[8] (3303:3303:3303) (3429:3429:3429)) + (PORT d[9] (1788:1788:1788) (1877:1877:1877)) + (PORT d[10] (3965:3965:3965) (4227:4227:4227)) + (PORT d[11] (3579:3579:3579) (3787:3787:3787)) + (PORT d[12] (1737:1737:1737) (1834:1834:1834)) + (PORT clk (1856:1856:1856) (1882:1882:1882)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1852:1852:1852) (1826:1826:1826)) + (PORT clk (1856:1856:1856) (1882:1882:1882)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1886:1886:1886)) + (PORT d[0] (2578:2578:2578) (2564:2564:2564)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1819:1819:1819) (1845:1845:1845)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1008:1008:1008)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (825:825:825) (840:840:840)) + (PORT datab (1443:1443:1443) (1548:1548:1548)) + (PORT datac (883:883:883) (887:887:887)) + (PORT datad (1488:1488:1488) (1577:1577:1577)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (705:705:705) (752:752:752)) + (PORT clk (1860:1860:1860) (1888:1888:1888)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3622:3622:3622) (3851:3851:3851)) + (PORT d[1] (1282:1282:1282) (1357:1357:1357)) + (PORT d[2] (1268:1268:1268) (1348:1348:1348)) + (PORT d[3] (2986:2986:2986) (3181:3181:3181)) + (PORT d[4] (3528:3528:3528) (3691:3691:3691)) + (PORT d[5] (4274:4274:4274) (4437:4437:4437)) + (PORT d[6] (1319:1319:1319) (1375:1375:1375)) + (PORT d[7] (2558:2558:2558) (2800:2800:2800)) + (PORT d[8] (3323:3323:3323) (3446:3446:3446)) + (PORT d[9] (2053:2053:2053) (2112:2112:2112)) + (PORT d[10] (3999:3999:3999) (4273:4273:4273)) + (PORT d[11] (3568:3568:3568) (3801:3801:3801)) + (PORT d[12] (1499:1499:1499) (1556:1556:1556)) + (PORT clk (1857:1857:1857) (1884:1884:1884)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1490:1490:1490) (1482:1482:1482)) + (PORT clk (1857:1857:1857) (1884:1884:1884)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1888:1888:1888)) + (PORT d[0] (2685:2685:2685) (2637:2637:2637)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1847:1847:1847)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1010:1010:1010)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1011:1011:1011)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1011:1011:1011)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1011:1011:1011)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1015:1015:1015) (1051:1051:1051)) + (PORT clk (1860:1860:1860) (1887:1887:1887)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2938:2938:2938) (3189:3189:3189)) + (PORT d[1] (1276:1276:1276) (1338:1338:1338)) + (PORT d[2] (1269:1269:1269) (1331:1331:1331)) + (PORT d[3] (3309:3309:3309) (3542:3542:3542)) + (PORT d[4] (3813:3813:3813) (4002:4002:4002)) + (PORT d[5] (1464:1464:1464) (1519:1519:1519)) + (PORT d[6] (1310:1310:1310) (1355:1355:1355)) + (PORT d[7] (2597:2597:2597) (2822:2822:2822)) + (PORT d[8] (3293:3293:3293) (3442:3442:3442)) + (PORT d[9] (1490:1490:1490) (1549:1549:1549)) + (PORT d[10] (4282:4282:4282) (4575:4575:4575)) + (PORT d[11] (3879:3879:3879) (4130:4130:4130)) + (PORT d[12] (1483:1483:1483) (1560:1560:1560)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1641:1641:1641) (1578:1578:1578)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (PORT d[0] (2502:2502:2502) (2457:2457:2457)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1846:1846:1846)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (1178:1178:1178) (1188:1188:1188)) + (PORT datac (1803:1803:1803) (1899:1899:1899)) + (PORT datad (1338:1338:1338) (1353:1353:1353)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2467:2467:2467) (2663:2663:2663)) + (PORT d[1] (2723:2723:2723) (2844:2844:2844)) + (PORT d[2] (2220:2220:2220) (2326:2326:2326)) + (PORT d[3] (2315:2315:2315) (2492:2492:2492)) + (PORT d[4] (2651:2651:2651) (2757:2757:2757)) + (PORT d[5] (2910:2910:2910) (3032:3032:3032)) + (PORT d[6] (2689:2689:2689) (2779:2779:2779)) + (PORT d[7] (1980:1980:1980) (2172:2172:2172)) + (PORT d[8] (2407:2407:2407) (2482:2482:2482)) + (PORT d[9] (2926:2926:2926) (3008:3008:3008)) + (PORT d[10] (4086:4086:4086) (4372:4372:4372)) + (PORT d[11] (2934:2934:2934) (3119:3119:3119)) + (PORT d[12] (2364:2364:2364) (2475:2475:2475)) + (PORT clk (1866:1866:1866) (1891:1891:1891)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1866:1866:1866) (1891:1891:1891)) + (PORT d[0] (2730:2730:2730) (2773:2773:2773)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1867:1867:1867) (1892:1892:1892)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1829:1829:1829) (1854:1854:1854)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1014:1014:1014) (1017:1017:1017)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1015:1015:1015) (1018:1018:1018)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1015:1015:1015) (1018:1018:1018)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1015:1015:1015) (1018:1018:1018)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1078:1078:1078) (1075:1075:1075)) + (PORT clk (1855:1855:1855) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3337:3337:3337) (3543:3543:3543)) + (PORT d[1] (1935:1935:1935) (2020:2020:2020)) + (PORT d[2] (1898:1898:1898) (1995:1995:1995)) + (PORT d[3] (2945:2945:2945) (3137:3137:3137)) + (PORT d[4] (3259:3259:3259) (3390:3390:3390)) + (PORT d[5] (3698:3698:3698) (3841:3841:3841)) + (PORT d[6] (3247:3247:3247) (3354:3354:3354)) + (PORT d[7] (2249:2249:2249) (2446:2446:2446)) + (PORT d[8] (2991:2991:2991) (3096:3096:3096)) + (PORT d[9] (3392:3392:3392) (3490:3490:3490)) + (PORT d[10] (3958:3958:3958) (4200:4200:4200)) + (PORT d[11] (3288:3288:3288) (3477:3477:3477)) + (PORT d[12] (2051:2051:2051) (2165:2165:2165)) + (PORT clk (1852:1852:1852) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3101:3101:3101) (3111:3111:3111)) + (PORT clk (1852:1852:1852) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1855:1855:1855) (1883:1883:1883)) + (PORT d[0] (3055:3055:3055) (3068:3068:3068)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1810:1810:1810) (1808:1808:1808)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2419:2419:2419) (2599:2599:2599)) + (PORT clk (1820:1820:1820) (1814:1814:1814)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4231:4231:4231) (4215:4215:4215)) + (PORT d[1] (4359:4359:4359) (4372:4372:4372)) + (PORT d[2] (4164:4164:4164) (4188:4188:4188)) + (PORT d[3] (4164:4164:4164) (4242:4242:4242)) + (PORT d[4] (4113:4113:4113) (4265:4265:4265)) + (PORT d[5] (4316:4316:4316) (4445:4445:4445)) + (PORT d[6] (4184:4184:4184) (4238:4238:4238)) + (PORT d[7] (4036:4036:4036) (4137:4137:4137)) + (PORT d[8] (4295:4295:4295) (4299:4299:4299)) + (PORT d[9] (4296:4296:4296) (4400:4400:4400)) + (PORT d[10] (4241:4241:4241) (4307:4307:4307)) + (PORT d[11] (4319:4319:4319) (4408:4408:4408)) + (PORT d[12] (4212:4212:4212) (4259:4259:4259)) + (PORT clk (1816:1816:1816) (1810:1810:1810)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1814:1814:1814)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1821:1821:1821) (1815:1815:1815)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1821:1821:1821) (1815:1815:1815)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1821:1821:1821) (1815:1815:1815)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1821:1821:1821) (1815:1815:1815)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1207:1207:1207) (1211:1211:1211)) + (PORT clk (1853:1853:1853) (1881:1881:1881)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3306:3306:3306) (3496:3496:3496)) + (PORT d[1] (2990:2990:2990) (3143:3143:3143)) + (PORT d[2] (1892:1892:1892) (1990:1990:1990)) + (PORT d[3] (2334:2334:2334) (2532:2532:2532)) + (PORT d[4] (3249:3249:3249) (3381:3381:3381)) + (PORT d[5] (3697:3697:3697) (3840:3840:3840)) + (PORT d[6] (2351:2351:2351) (2442:2442:2442)) + (PORT d[7] (2185:2185:2185) (2360:2360:2360)) + (PORT d[8] (2691:2691:2691) (2784:2784:2784)) + (PORT d[9] (2245:2245:2245) (2325:2325:2325)) + (PORT d[10] (3672:3672:3672) (3909:3909:3909)) + (PORT d[11] (3268:3268:3268) (3478:3478:3478)) + (PORT d[12] (2033:2033:2033) (2161:2161:2161)) + (PORT clk (1850:1850:1850) (1877:1877:1877)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2199:2199:2199) (2195:2195:2195)) + (PORT clk (1850:1850:1850) (1877:1877:1877)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1881:1881:1881)) + (PORT d[0] (3072:3072:3072) (3054:3054:3054)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1808:1808:1808) (1806:1806:1806)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2682:2682:2682) (2860:2860:2860)) + (PORT clk (1818:1818:1818) (1812:1812:1812)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4199:4199:4199) (4194:4194:4194)) + (PORT d[1] (4123:4123:4123) (4119:4119:4119)) + (PORT d[2] (4282:4282:4282) (4380:4380:4380)) + (PORT d[3] (4157:4157:4157) (4224:4224:4224)) + (PORT d[4] (4097:4097:4097) (4250:4250:4250)) + (PORT d[5] (4374:4374:4374) (4426:4426:4426)) + (PORT d[6] (4243:4243:4243) (4281:4281:4281)) + (PORT d[7] (4157:4157:4157) (4210:4210:4210)) + (PORT d[8] (4307:4307:4307) (4339:4339:4339)) + (PORT d[9] (4320:4320:4320) (4416:4416:4416)) + (PORT d[10] (4225:4225:4225) (4267:4267:4267)) + (PORT d[11] (4323:4323:4323) (4416:4416:4416)) + (PORT d[12] (4104:4104:4104) (4195:4195:4195)) + (PORT clk (1814:1814:1814) (1808:1808:1808)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1818:1818:1818) (1812:1812:1812)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1819:1819:1819) (1813:1813:1813)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1819:1819:1819) (1813:1813:1813)) + (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1819:1819:1819) (1813:1813:1813)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1819:1819:1819) (1813:1813:1813)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1810:1810:1810) (1808:1808:1808)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Mux0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1699:1699:1699) (1838:1838:1838)) + (PORT datab (676:676:676) (697:697:697)) + (PORT datac (861:861:861) (889:889:889)) + (PORT datad (1226:1226:1226) (1281:1281:1281)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2758:2758:2758) (2973:2973:2973)) + (PORT d[1] (2459:2459:2459) (2561:2561:2561)) + (PORT d[2] (2454:2454:2454) (2579:2579:2579)) + (PORT d[3] (2605:2605:2605) (2806:2806:2806)) + (PORT d[4] (2391:2391:2391) (2486:2486:2486)) + (PORT d[5] (2623:2623:2623) (2726:2726:2726)) + (PORT d[6] (2453:2453:2453) (2587:2587:2587)) + (PORT d[7] (2233:2233:2233) (2438:2438:2438)) + (PORT d[8] (2128:2128:2128) (2186:2186:2186)) + (PORT d[9] (2932:2932:2932) (3041:3041:3041)) + (PORT d[10] (3805:3805:3805) (4084:4084:4084)) + (PORT d[11] (2563:2563:2563) (2666:2666:2666)) + (PORT d[12] (2766:2766:2766) (2874:2874:2874)) + (PORT clk (1868:1868:1868) (1894:1894:1894)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1868:1868:1868) (1894:1894:1894)) + (PORT d[0] (2808:2808:2808) (2746:2746:2746)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1869:1869:1869) (1895:1895:1895)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1831:1831:1831) (1857:1857:1857)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1016:1016:1016) (1020:1020:1020)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1017:1017:1017) (1021:1021:1021)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1017:1017:1017) (1021:1021:1021)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1017:1017:1017) (1021:1021:1021)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Mux0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1699:1699:1699) (1838:1838:1838)) + (PORT datab (1460:1460:1460) (1484:1484:1484)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (1468:1468:1468) (1528:1528:1528)) + (IOPATH dataa combout (341:341:341) (320:320:320)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[7\]\~89) + (DELAY + (ABSOLUTE + (PORT dataa (2046:2046:2046) (2109:2109:2109)) + (PORT datab (198:198:198) (236:236:236)) + (PORT datac (1678:1678:1678) (1752:1752:1752)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[7\]\~72) + (DELAY + (ABSOLUTE + (PORT dataa (1415:1415:1415) (1492:1492:1492)) + (PORT datab (1626:1626:1626) (1692:1692:1692)) + (PORT datac (171:171:171) (203:203:203)) + (PORT datad (1421:1421:1421) (1438:1438:1438)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~84) + (DELAY + (ABSOLUTE + (PORT dataa (586:586:586) (613:613:613)) + (PORT datab (2797:2797:2797) (2988:2988:2988)) + (PORT datac (586:586:586) (600:600:600)) + (PORT datad (604:604:604) (625:625:625)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[7\]\~80) + (DELAY + (ABSOLUTE + (PORT datac (194:194:194) (227:227:227)) + (PORT datad (1411:1411:1411) (1455:1455:1455)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[7\]) + (DELAY + (ABSOLUTE + (PORT dataa (1429:1429:1429) (1486:1486:1486)) + (PORT datab (220:220:220) (259:259:259)) + (PORT datac (1143:1143:1143) (1216:1216:1216)) + (PORT datad (375:375:375) (401:401:401)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1527:1527:1527) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[7\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (397:397:397) (444:444:444)) + (PORT datab (367:367:367) (389:389:389)) + (PORT datac (604:604:604) (641:641:641)) + (PORT datad (579:579:579) (609:609:609)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1566:1566:1566) (1548:1548:1548)) + (PORT ena (1684:1684:1684) (1669:1669:1669)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (289:289:289) (386:386:386)) + (PORT datab (271:271:271) (355:355:355)) + (PORT datac (397:397:397) (476:476:476)) + (PORT datad (395:395:395) (461:461:461)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal12\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1565:1565:1565) (1693:1693:1693)) + (PORT datab (1560:1560:1560) (1620:1620:1620)) + (PORT datac (1382:1382:1382) (1558:1558:1558)) + (PORT datad (1512:1512:1512) (1630:1630:1630)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~16) + (DELAY + (ABSOLUTE + (PORT dataa (2000:2000:2000) (2198:2198:2198)) + (PORT datab (1217:1217:1217) (1319:1319:1319)) + (PORT datac (679:679:679) (710:710:710)) + (PORT datad (1265:1265:1265) (1358:1358:1358)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~24) + (DELAY + (ABSOLUTE + (PORT dataa (1357:1357:1357) (1405:1405:1405)) + (PORT datab (911:911:911) (960:960:960)) + (PORT datac (859:859:859) (917:917:917)) + (PORT datad (1673:1673:1673) (1702:1702:1702)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~25) + (DELAY + (ABSOLUTE + (PORT dataa (950:950:950) (1026:1026:1026)) + (PORT datab (639:639:639) (660:660:660)) + (PORT datac (603:603:603) (629:629:629)) + (PORT datad (913:913:913) (956:956:956)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~21) + (DELAY + (ABSOLUTE + (PORT dataa (1727:1727:1727) (1799:1799:1799)) + (PORT datab (308:308:308) (404:404:404)) + (PORT datac (627:627:627) (644:644:644)) + (PORT datad (586:586:586) (603:603:603)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~16) + (DELAY + (ABSOLUTE + (PORT dataa (2061:2061:2061) (2163:2163:2163)) + (PORT datab (945:945:945) (981:981:981)) + (PORT datac (1147:1147:1147) (1157:1157:1157)) + (PORT datad (1082:1082:1082) (1111:1111:1111)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1175:1175:1175) (1200:1200:1200)) + (PORT datab (904:904:904) (947:947:947)) + (PORT datac (600:600:600) (633:633:633)) + (PORT datad (402:402:402) (447:447:447)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~15) + (DELAY + (ABSOLUTE + (PORT dataa (2062:2062:2062) (2162:2162:2162)) + (PORT datab (1760:1760:1760) (1802:1802:1802)) + (PORT datac (2157:2157:2157) (2242:2242:2242)) + (PORT datad (937:937:937) (972:972:972)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~12) + (DELAY + (ABSOLUTE + (PORT dataa (990:990:990) (1048:1048:1048)) + (PORT datab (736:736:736) (781:781:781)) + (PORT datac (566:566:566) (589:589:589)) + (PORT datad (1128:1128:1128) (1178:1178:1178)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~11) + (DELAY + (ABSOLUTE + (PORT dataa (649:649:649) (662:662:662)) + (PORT datab (655:655:655) (707:707:707)) + (PORT datac (909:909:909) (932:932:932)) + (PORT datad (1081:1081:1081) (1110:1110:1110)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~13) + (DELAY + (ABSOLUTE + (PORT dataa (610:610:610) (638:638:638)) + (PORT datab (707:707:707) (763:763:763)) + (PORT datac (660:660:660) (697:697:697)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~17) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (242:242:242)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (1234:1234:1234) (1277:1277:1277)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~22) + (DELAY + (ABSOLUTE + (PORT dataa (631:631:631) (660:660:660)) + (PORT datab (608:608:608) (638:638:638)) + (PORT datac (1163:1163:1163) (1218:1218:1218)) + (PORT datad (608:608:608) (647:647:647)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~27) + (DELAY + (ABSOLUTE + (PORT dataa (2262:2262:2262) (2324:2324:2324)) + (PORT datab (1432:1432:1432) (1501:1501:1501)) + (PORT datac (1161:1161:1161) (1183:1183:1183)) + (PORT datad (905:905:905) (948:948:948)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~37) + (DELAY + (ABSOLUTE + (PORT dataa (1527:1527:1527) (1594:1594:1594)) + (PORT datab (608:608:608) (643:643:643)) + (PORT datac (985:985:985) (1077:1077:1077)) + (PORT datad (897:897:897) (960:960:960)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~31) + (DELAY + (ABSOLUTE + (PORT dataa (1161:1161:1161) (1178:1178:1178)) + (PORT datab (922:922:922) (943:943:943)) + (PORT datac (887:887:887) (906:906:906)) + (PORT datad (1299:1299:1299) (1340:1340:1340)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~29) + (DELAY + (ABSOLUTE + (PORT dataa (730:730:730) (805:805:805)) + (PORT datab (1044:1044:1044) (1191:1191:1191)) + (PORT datac (1289:1289:1289) (1355:1355:1355)) + (PORT datad (994:994:994) (1098:1098:1098)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~30) + (DELAY + (ABSOLUTE + (PORT dataa (1098:1098:1098) (1168:1168:1168)) + (PORT datab (227:227:227) (267:267:267)) + (PORT datac (890:890:890) (940:940:940)) + (PORT datad (933:933:933) (975:975:975)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~28) + (DELAY + (ABSOLUTE + (PORT dataa (921:921:921) (946:946:946)) + (PORT datab (1148:1148:1148) (1174:1174:1174)) + (PORT datac (1343:1343:1343) (1359:1359:1359)) + (PORT datad (944:944:944) (997:997:997)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~32) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (255:255:255)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~33) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (244:244:244)) + (PORT datab (215:215:215) (260:260:260)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~23) + (DELAY + (ABSOLUTE + (PORT dataa (1463:1463:1463) (1508:1508:1508)) + (PORT datab (876:876:876) (881:881:881)) + (PORT datac (864:864:864) (889:889:889)) + (PORT datad (616:616:616) (659:659:659)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~34) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (628:628:628) (646:646:646)) + (PORT datac (868:868:868) (883:883:883)) + (PORT datad (636:636:636) (669:669:669)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~35) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (409:409:409)) + (PORT datab (945:945:945) (981:981:981)) + (PORT datac (1115:1115:1115) (1121:1121:1121)) + (PORT datad (1081:1081:1081) (1111:1111:1111)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1553:1553:1553) (1651:1651:1651)) + (PORT datab (1183:1183:1183) (1320:1320:1320)) + (PORT datac (627:627:627) (668:668:668)) + (PORT datad (588:588:588) (600:600:600)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~36) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (245:245:245) (293:293:293)) + (PORT datac (604:604:604) (646:646:646)) + (PORT datad (181:181:181) (210:210:210)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_re) + (DELAY + (ABSOLUTE + (PORT dataa (1162:1162:1162) (1235:1235:1235)) + (PORT datac (1054:1054:1054) (1067:1067:1067)) + (PORT datad (764:764:764) (762:762:762)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~118) + (DELAY + (ABSOLUTE + (PORT dataa (996:996:996) (1079:1079:1079)) + (PORT datab (1516:1516:1516) (1598:1598:1598)) + (PORT datac (1146:1146:1146) (1191:1191:1191)) + (PORT datad (1154:1154:1154) (1231:1231:1231)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~119) + (DELAY + (ABSOLUTE + (PORT dataa (1315:1315:1315) (1409:1409:1409)) + (PORT datab (426:426:426) (511:511:511)) + (PORT datac (314:314:314) (332:332:332)) + (PORT datad (624:624:624) (642:642:642)) (IOPATH dataa combout (324:324:324) (328:328:328)) (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -49953,15 +38340,11438 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_apin_mux\~2) + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~120) (DELAY (ABSOLUTE - (PORT dataa (894:894:894) (970:970:970)) - (PORT datab (221:221:221) (261:261:261)) - (PORT datac (896:896:896) (900:900:900)) + (PORT dataa (199:199:199) (243:243:243)) + (PORT datad (197:197:197) (223:223:223)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1558:1558:1558) (1549:1549:1549)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~129) + (DELAY + (ABSOLUTE + (PORT dataa (434:434:434) (508:508:508)) + (PORT datab (1214:1214:1214) (1261:1261:1261)) + (PORT datac (334:334:334) (361:361:361)) + (PORT datad (677:677:677) (764:764:764)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~116) + (DELAY + (ABSOLUTE + (PORT dataa (788:788:788) (864:864:864)) + (PORT datab (449:449:449) (527:527:527)) + (PORT datad (1018:1018:1018) (1089:1089:1089)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~134) + (DELAY + (ABSOLUTE + (PORT dataa (990:990:990) (1075:1075:1075)) + (PORT datab (1219:1219:1219) (1293:1293:1293)) + (PORT datad (316:316:316) (335:335:335)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~117) + (DELAY + (ABSOLUTE + (PORT dataa (635:635:635) (712:712:712)) + (PORT datab (344:344:344) (377:377:377)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1555:1555:1555) (1547:1547:1547)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~60) + (DELAY + (ABSOLUTE + (PORT dataa (1083:1083:1083) (1090:1090:1090)) + (PORT datab (1039:1039:1039) (1115:1115:1115)) + (PORT datac (389:389:389) (452:452:452)) + (PORT datad (848:848:848) (908:908:908)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|Equal0\~2) + (DELAY + (ABSOLUTE + (PORT datab (943:943:943) (1067:1067:1067)) + (PORT datac (709:709:709) (781:781:781)) + (PORT datad (655:655:655) (736:736:736)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]\~121) + (DELAY + (ABSOLUTE + (PORT dataa (935:935:935) (1021:1021:1021)) + (PORT datab (1537:1537:1537) (1611:1611:1611)) + (PORT datad (367:367:367) (393:393:393)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1558:1558:1558) (1550:1550:1550)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~115) + (DELAY + (ABSOLUTE + (PORT dataa (211:211:211) (258:258:258)) + (PORT datab (222:222:222) (262:262:262)) + (PORT datad (361:361:361) (382:382:382)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1558:1558:1558) (1549:1549:1549)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\~4) + (DELAY + (ABSOLUTE + (PORT dataa (430:430:430) (499:499:499)) + (PORT datac (2398:2398:2398) (2573:2573:2573)) + (PORT datad (1459:1459:1459) (1518:1518:1518)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~61) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (244:244:244)) + (PORT datab (1122:1122:1122) (1127:1127:1127)) + (PORT datac (215:215:215) (291:291:291)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~124) + (DELAY + (ABSOLUTE + (PORT datab (704:704:704) (778:778:778)) + (PORT datac (275:275:275) (362:362:362)) + (PORT datad (660:660:660) (718:718:718)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~125) + (DELAY + (ABSOLUTE + (PORT dataa (996:996:996) (1073:1073:1073)) + (PORT datab (200:200:200) (239:239:239)) + (PORT datac (602:602:602) (612:612:612)) + (PORT datad (2182:2182:2182) (2284:2284:2284)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~126) + (DELAY + (ABSOLUTE + (PORT dataa (606:606:606) (634:634:634)) + (PORT datab (474:474:474) (548:548:548)) + (PORT datad (174:174:174) (198:198:198)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1555:1555:1555) (1548:1548:1548)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~122) + (DELAY + (ABSOLUTE + (PORT dataa (996:996:996) (1072:1072:1072)) + (PORT datab (2218:2218:2218) (2323:2323:2323)) + (PORT datac (952:952:952) (1036:1036:1036)) + (PORT datad (657:657:657) (717:717:717)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~123) + (DELAY + (ABSOLUTE + (PORT dataa (923:923:923) (933:933:933)) + (PORT datab (200:200:200) (239:239:239)) + (PORT datad (437:437:437) (511:511:511)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1555:1555:1555) (1548:1548:1548)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~62) + (DELAY + (ABSOLUTE + (PORT dataa (243:243:243) (328:328:328)) + (PORT datab (2091:2091:2091) (2125:2125:2125)) + (PORT datac (864:864:864) (897:897:897)) + (PORT datad (216:216:216) (284:284:284)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~49) + (DELAY + (ABSOLUTE + (PORT dataa (944:944:944) (972:972:972)) + (PORT datab (2243:2243:2243) (2333:2333:2333)) + (PORT datac (835:835:835) (848:848:848)) + (PORT datad (972:972:972) (1027:1027:1027)) (IOPATH dataa combout (327:327:327) (347:347:347)) (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|shifted\~3) + (DELAY + (ABSOLUTE + (PORT datac (1088:1088:1088) (1177:1177:1177)) + (PORT datad (1209:1209:1209) (1270:1270:1270)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~127) + (DELAY + (ABSOLUTE + (PORT dataa (784:784:784) (865:865:865)) + (PORT datab (363:363:363) (401:401:401)) + (PORT datad (198:198:198) (224:224:224)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1558:1558:1558) (1550:1550:1550)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~128) + (DELAY + (ABSOLUTE + (PORT dataa (777:777:777) (865:865:865)) + (PORT datab (884:884:884) (903:903:903)) + (PORT datad (345:345:345) (368:368:368)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1558:1558:1558) (1550:1550:1550)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~63) + (DELAY + (ABSOLUTE + (PORT dataa (841:841:841) (925:925:925)) + (PORT datab (628:628:628) (655:655:655)) + (PORT datac (1228:1228:1228) (1317:1317:1317)) + (PORT datad (1348:1348:1348) (1469:1469:1469)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~64) + (DELAY + (ABSOLUTE + (PORT dataa (855:855:855) (857:857:857)) + (PORT datab (980:980:980) (994:994:994)) + (PORT datac (2856:2856:2856) (3130:3130:3130)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1003:1003:1003) (1023:1023:1023)) + (PORT clk (1856:1856:1856) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2316:2316:2316) (2413:2413:2413)) + (PORT d[1] (1270:1270:1270) (1336:1336:1336)) + (PORT d[2] (2153:2153:2153) (2308:2308:2308)) + (PORT d[3] (2467:2467:2467) (2629:2629:2629)) + (PORT d[4] (998:998:998) (1054:1054:1054)) + (PORT d[5] (1250:1250:1250) (1291:1291:1291)) + (PORT d[6] (3512:3512:3512) (3548:3548:3548)) + (PORT d[7] (1888:1888:1888) (2045:2045:2045)) + (PORT d[8] (1240:1240:1240) (1295:1295:1295)) + (PORT d[9] (3442:3442:3442) (3722:3722:3722)) + (PORT d[10] (992:992:992) (1040:1040:1040)) + (PORT d[11] (1520:1520:1520) (1555:1555:1555)) + (PORT d[12] (2020:2020:2020) (2068:2068:2068)) + (PORT clk (1853:1853:1853) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1476:1476:1476) (1465:1465:1465)) + (PORT clk (1853:1853:1853) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1883:1883:1883)) + (PORT d[0] (2158:2158:2158) (2124:2124:2124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1816:1816:1816) (1842:1842:1842)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1001:1001:1001) (1005:1005:1005)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1002:1002:1002) (1006:1006:1006)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1002:1002:1002) (1006:1006:1006)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1002:1002:1002) (1006:1006:1006)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (991:991:991) (1004:1004:1004)) + (PORT clk (1854:1854:1854) (1881:1881:1881)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2556:2556:2556) (2659:2659:2659)) + (PORT d[1] (1257:1257:1257) (1329:1329:1329)) + (PORT d[2] (2368:2368:2368) (2579:2579:2579)) + (PORT d[3] (2792:2792:2792) (2975:2975:2975)) + (PORT d[4] (742:742:742) (799:799:799)) + (PORT d[5] (1249:1249:1249) (1290:1290:1290)) + (PORT d[6] (3491:3491:3491) (3525:3525:3525)) + (PORT d[7] (1866:1866:1866) (2023:2023:2023)) + (PORT d[8] (1212:1212:1212) (1262:1262:1262)) + (PORT d[9] (3469:3469:3469) (3754:3754:3754)) + (PORT d[10] (990:990:990) (1024:1024:1024)) + (PORT d[11] (1507:1507:1507) (1551:1551:1551)) + (PORT d[12] (2277:2277:2277) (2330:2330:2330)) + (PORT clk (1851:1851:1851) (1877:1877:1877)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1984:1984:1984) (1937:1937:1937)) + (PORT clk (1851:1851:1851) (1877:1877:1877)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1881:1881:1881)) + (PORT d[0] (1916:1916:1916) (1885:1885:1885)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1855:1855:1855) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1855:1855:1855) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1855:1855:1855) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1855:1855:1855) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1814:1814:1814) (1840:1840:1840)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (999:999:999) (1003:1003:1003)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1000:1000:1000) (1004:1004:1004)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1000:1000:1000) (1004:1004:1004)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1000:1000:1000) (1004:1004:1004)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (979:979:979) (1006:1006:1006)) + (PORT clk (1856:1856:1856) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2603:2603:2603) (2726:2726:2726)) + (PORT d[1] (1252:1252:1252) (1326:1326:1326)) + (PORT d[2] (2923:2923:2923) (3153:3153:3153)) + (PORT d[3] (982:982:982) (1016:1016:1016)) + (PORT d[4] (740:740:740) (778:778:778)) + (PORT d[5] (1191:1191:1191) (1244:1244:1244)) + (PORT d[6] (977:977:977) (999:999:999)) + (PORT d[7] (2181:2181:2181) (2361:2361:2361)) + (PORT d[8] (1248:1248:1248) (1302:1302:1302)) + (PORT d[9] (964:964:964) (979:979:979)) + (PORT d[10] (4573:4573:4573) (4886:4886:4886)) + (PORT d[11] (1531:1531:1531) (1576:1576:1576)) + (PORT d[12] (2585:2585:2585) (2670:2670:2670)) + (PORT clk (1853:1853:1853) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (925:925:925) (881:881:881)) + (PORT clk (1853:1853:1853) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1883:1883:1883)) + (PORT d[0] (2184:2184:2184) (2115:2115:2115)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1816:1816:1816) (1842:1842:1842)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1001:1001:1001) (1005:1005:1005)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1002:1002:1002) (1006:1006:1006)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1002:1002:1002) (1006:1006:1006)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1002:1002:1002) (1006:1006:1006)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (747:747:747) (776:776:776)) + (PORT clk (1852:1852:1852) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2600:2600:2600) (2704:2704:2704)) + (PORT d[1] (949:949:949) (995:995:995)) + (PORT d[2] (2647:2647:2647) (2879:2879:2879)) + (PORT d[3] (995:995:995) (1046:1046:1046)) + (PORT d[4] (714:714:714) (746:746:746)) + (PORT d[5] (889:889:889) (921:921:921)) + (PORT d[6] (1226:1226:1226) (1240:1240:1240)) + (PORT d[7] (2177:2177:2177) (2355:2355:2355)) + (PORT d[8] (927:927:927) (954:954:954)) + (PORT d[9] (962:962:962) (980:980:980)) + (PORT d[10] (2172:2172:2172) (2231:2231:2231)) + (PORT d[11] (1185:1185:1185) (1207:1207:1207)) + (PORT d[12] (2316:2316:2316) (2387:2387:2387)) + (PORT clk (1849:1849:1849) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1209:1209:1209) (1166:1166:1166)) + (PORT clk (1849:1849:1849) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1879:1879:1879)) + (PORT d[0] (2107:2107:2107) (2058:2058:2058)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (886:886:886) (945:945:945)) + (PORT datab (874:874:874) (868:868:868)) + (PORT datac (827:827:827) (831:831:831)) + (PORT datad (1376:1376:1376) (1438:1438:1438)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1116:1116:1116) (1150:1150:1150)) + (PORT datab (1109:1109:1109) (1114:1114:1114)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (1746:1746:1746) (1849:1849:1849)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2042:2042:2042) (2133:2133:2133)) + (PORT d[1] (1633:1633:1633) (1690:1690:1690)) + (PORT d[2] (2214:2214:2214) (2383:2383:2383)) + (PORT d[3] (2758:2758:2758) (2918:2918:2918)) + (PORT d[4] (1023:1023:1023) (1094:1094:1094)) + (PORT d[5] (1542:1542:1542) (1600:1600:1600)) + (PORT d[6] (3496:3496:3496) (3536:3536:3536)) + (PORT d[7] (1846:1846:1846) (2009:2009:2009)) + (PORT d[8] (1536:1536:1536) (1608:1608:1608)) + (PORT d[9] (3451:3451:3451) (3717:3717:3717)) + (PORT d[10] (976:976:976) (1035:1035:1035)) + (PORT d[11] (947:947:947) (1004:1004:1004)) + (PORT d[12] (1991:1991:1991) (2028:2028:2028)) + (PORT clk (1856:1856:1856) (1882:1882:1882)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1882:1882:1882)) + (PORT d[0] (2339:2339:2339) (2361:2361:2361)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1883:1883:1883)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1819:1819:1819) (1845:1845:1845)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1008:1008:1008)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1591:1591:1591) (1680:1680:1680)) + (PORT clk (1864:1864:1864) (1891:1891:1891)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2597:2597:2597) (2802:2802:2802)) + (PORT d[1] (2423:2423:2423) (2558:2558:2558)) + (PORT d[2] (2208:2208:2208) (2331:2331:2331)) + (PORT d[3] (2640:2640:2640) (2832:2832:2832)) + (PORT d[4] (2962:2962:2962) (3072:3072:3072)) + (PORT d[5] (3679:3679:3679) (3784:3784:3784)) + (PORT d[6] (2961:2961:2961) (3093:3093:3093)) + (PORT d[7] (1977:1977:1977) (2149:2149:2149)) + (PORT d[8] (2696:2696:2696) (2777:2777:2777)) + (PORT d[9] (2624:2624:2624) (2711:2711:2711)) + (PORT d[10] (3643:3643:3643) (3873:3873:3873)) + (PORT d[11] (3247:3247:3247) (3429:3429:3429)) + (PORT d[12] (2402:2402:2402) (2538:2538:2538)) + (PORT clk (1861:1861:1861) (1887:1887:1887)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2803:2803:2803) (2827:2827:2827)) + (PORT clk (1861:1861:1861) (1887:1887:1887)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1864:1864:1864) (1891:1891:1891)) + (PORT d[0] (3387:3387:3387) (3427:3427:3427)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1865:1865:1865) (1892:1892:1892)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1865:1865:1865) (1892:1892:1892)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1865:1865:1865) (1892:1892:1892)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1865:1865:1865) (1892:1892:1892)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1819:1819:1819) (1816:1816:1816)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2697:2697:2697) (2894:2894:2894)) + (PORT clk (1829:1829:1829) (1822:1822:1822)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4069:4069:4069) (4099:4099:4099)) + (PORT d[1] (4103:4103:4103) (4067:4067:4067)) + (PORT d[2] (4123:4123:4123) (4136:4136:4136)) + (PORT d[3] (4170:4170:4170) (4223:4223:4223)) + (PORT d[4] (4256:4256:4256) (4384:4384:4384)) + (PORT d[5] (4464:4464:4464) (4551:4551:4551)) + (PORT d[6] (4216:4216:4216) (4293:4293:4293)) + (PORT d[7] (4073:4073:4073) (4122:4122:4122)) + (PORT d[8] (4185:4185:4185) (4250:4250:4250)) + (PORT d[9] (4229:4229:4229) (4289:4289:4289)) + (PORT d[10] (4100:4100:4100) (4099:4099:4099)) + (PORT d[11] (4276:4276:4276) (4280:4280:4280)) + (PORT d[12] (4103:4103:4103) (4196:4196:4196)) + (PORT clk (1825:1825:1825) (1818:1818:1818)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1829:1829:1829) (1822:1822:1822)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1830:1830:1830) (1823:1823:1823)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1830:1830:1830) (1823:1823:1823)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1830:1830:1830) (1823:1823:1823)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1830:1830:1830) (1823:1823:1823)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1702:1702:1702) (1829:1829:1829)) + (PORT clk (1844:1844:1844) (1873:1873:1873)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3120:3120:3120) (3377:3377:3377)) + (PORT d[1] (3988:3988:3988) (4117:4117:4117)) + (PORT d[2] (2054:2054:2054) (2224:2224:2224)) + (PORT d[3] (2171:2171:2171) (2286:2286:2286)) + (PORT d[4] (3529:3529:3529) (3657:3657:3657)) + (PORT d[5] (2341:2341:2341) (2458:2458:2458)) + (PORT d[6] (3271:3271:3271) (3376:3376:3376)) + (PORT d[7] (1637:1637:1637) (1757:1757:1757)) + (PORT d[8] (2198:2198:2198) (2315:2315:2315)) + (PORT d[9] (2510:2510:2510) (2590:2590:2590)) + (PORT d[10] (2660:2660:2660) (2871:2871:2871)) + (PORT d[11] (2001:2001:2001) (2095:2095:2095)) + (PORT d[12] (3015:3015:3015) (3165:3165:3165)) + (PORT clk (1841:1841:1841) (1869:1869:1869)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3168:3168:3168) (3259:3259:3259)) + (PORT clk (1841:1841:1841) (1869:1869:1869)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1873:1873:1873)) + (PORT d[0] (5281:5281:5281) (5171:5171:5171)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1874:1874:1874)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1874:1874:1874)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1874:1874:1874)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1874:1874:1874)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1799:1799:1799) (1798:1798:1798)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2386:2386:2386) (2603:2603:2603)) + (PORT clk (1809:1809:1809) (1804:1804:1804)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4219:4219:4219) (4281:4281:4281)) + (PORT d[1] (4270:4270:4270) (4325:4325:4325)) + (PORT d[2] (4095:4095:4095) (4204:4204:4204)) + (PORT d[3] (4293:4293:4293) (4421:4421:4421)) + (PORT d[4] (4107:4107:4107) (4220:4220:4220)) + (PORT d[5] (4318:4318:4318) (4418:4418:4418)) + (PORT d[6] (4128:4128:4128) (4196:4196:4196)) + (PORT d[7] (4078:4078:4078) (4195:4195:4195)) + (PORT d[8] (4287:4287:4287) (4309:4309:4309)) + (PORT d[9] (4099:4099:4099) (4204:4204:4204)) + (PORT d[10] (4255:4255:4255) (4320:4320:4320)) + (PORT d[11] (4343:4343:4343) (4435:4435:4435)) + (PORT d[12] (4182:4182:4182) (4226:4226:4226)) + (PORT clk (1805:1805:1805) (1800:1800:1800)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1809:1809:1809) (1804:1804:1804)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1810:1810:1810) (1805:1805:1805)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1810:1810:1810) (1805:1805:1805)) + (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1810:1810:1810) (1805:1805:1805)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1810:1810:1810) (1805:1805:1805)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1801:1801:1801) (1800:1800:1800)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1639:1639:1639) (1708:1708:1708)) + (PORT d[1] (1271:1271:1271) (1337:1337:1337)) + (PORT d[2] (2348:2348:2348) (2577:2577:2577)) + (PORT d[3] (2790:2790:2790) (2929:2929:2929)) + (PORT d[4] (1002:1002:1002) (1075:1075:1075)) + (PORT d[5] (1507:1507:1507) (1546:1546:1546)) + (PORT d[6] (3478:3478:3478) (3531:3531:3531)) + (PORT d[7] (1876:1876:1876) (2017:2017:2017)) + (PORT d[8] (1552:1552:1552) (1629:1629:1629)) + (PORT d[9] (3460:3460:3460) (3738:3738:3738)) + (PORT d[10] (951:951:951) (1011:1011:1011)) + (PORT d[11] (1492:1492:1492) (1533:1533:1533)) + (PORT d[12] (1997:1997:1997) (2043:2043:2043)) + (PORT clk (1855:1855:1855) (1880:1880:1880)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1855:1855:1855) (1880:1880:1880)) + (PORT d[0] (2338:2338:2338) (2320:2320:2320)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1881:1881:1881)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1818:1818:1818) (1843:1843:1843)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1003:1003:1003) (1006:1006:1006)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1007:1007:1007)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1007:1007:1007)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1007:1007:1007)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1389:1389:1389) (1516:1516:1516)) + (PORT datab (868:868:868) (879:879:879)) + (PORT datac (1474:1474:1474) (1580:1580:1580)) + (PORT datad (1108:1108:1108) (1131:1131:1131)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector4\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1166:1166:1166) (1179:1179:1179)) + (PORT datab (1070:1070:1070) (1089:1089:1089)) + (PORT datac (1676:1676:1676) (1711:1711:1711)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~86) + (DELAY + (ABSOLUTE + (PORT dataa (2693:2693:2693) (2866:2866:2866)) + (PORT datab (1198:1198:1198) (1298:1298:1298)) + (PORT datac (172:172:172) (206:206:206)) + (PORT datad (312:312:312) (324:324:324)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (336:336:336) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~75) + (DELAY + (ABSOLUTE + (PORT dataa (915:915:915) (931:931:931)) + (PORT datab (346:346:346) (372:372:372)) + (PORT datac (886:886:886) (900:900:900)) + (PORT datad (180:180:180) (210:210:210)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~76) + (DELAY + (ABSOLUTE + (PORT dataa (918:918:918) (930:930:930)) + (PORT datab (964:964:964) (1032:1032:1032)) + (PORT datac (1537:1537:1537) (1594:1594:1594)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[4\]) + (DELAY + (ABSOLUTE + (PORT dataa (699:699:699) (756:756:756)) + (PORT datab (398:398:398) (436:436:436)) + (PORT datac (1392:1392:1392) (1434:1434:1434)) + (PORT datad (840:840:840) (886:886:886)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1527:1527:1527) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[4\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (564:564:564) (592:592:592)) + (PORT datab (385:385:385) (461:461:461)) + (PORT datad (579:579:579) (605:605:605)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[4\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (722:722:722) (776:776:776)) + (PORT datab (650:650:650) (703:703:703)) + (PORT datac (619:619:619) (666:666:666)) + (PORT datad (1672:1672:1672) (1695:1695:1695)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1541:1541:1541) (1557:1557:1557)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1567:1567:1567) (1549:1549:1549)) + (PORT ena (1404:1404:1404) (1375:1375:1375)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal32\~0) + (DELAY + (ABSOLUTE + (PORT datab (1215:1215:1215) (1315:1315:1315)) + (PORT datad (1274:1274:1274) (1353:1353:1353)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal41\~1) + (DELAY + (ABSOLUTE + (PORT dataa (481:481:481) (578:578:578)) + (PORT datab (500:500:500) (579:579:579)) + (PORT datac (926:926:926) (1051:1051:1051)) + (PORT datad (976:976:976) (1060:1060:1060)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal41\~2) + (DELAY + (ABSOLUTE + (PORT dataa (2522:2522:2522) (2693:2693:2693)) + (PORT datab (641:641:641) (697:697:697)) + (PORT datac (832:832:832) (846:846:846)) + (PORT datad (915:915:915) (945:945:945)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal36\~0) + (DELAY + (ABSOLUTE + (PORT dataa (792:792:792) (893:893:893)) + (PORT datab (1920:1920:1920) (2012:2012:2012)) + (PORT datac (1274:1274:1274) (1343:1343:1343)) + (PORT datad (869:869:869) (888:888:888)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_tbl_cb_set) + (DELAY + (ABSOLUTE + (PORT dataa (993:993:993) (1045:1045:1045)) + (PORT datab (918:918:918) (947:947:947)) + (PORT datac (1266:1266:1266) (1289:1289:1289)) + (PORT datad (640:640:640) (690:690:690)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_tbl_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1661:1661:1661) (1739:1739:1739)) + (PORT datab (699:699:699) (752:752:752)) + (PORT datac (1265:1265:1265) (1288:1288:1288)) + (PORT datad (631:631:631) (685:685:685)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|decode_state_\|DFFE_instCB) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1566:1566:1566) (1548:1548:1548)) + (PORT ena (790:790:790) (783:783:783)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal52\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1042:1042:1042) (1134:1134:1134)) + (PORT datab (997:997:997) (1103:1103:1103)) + (PORT datac (932:932:932) (1054:1054:1054)) + (PORT datad (973:973:973) (1056:1056:1056)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (739:739:739) (833:833:833)) + (PORT datab (562:562:562) (576:576:576)) + (PORT datac (1143:1143:1143) (1241:1241:1241)) + (PORT datad (1800:1800:1800) (1868:1868:1868)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_tbl_ed_set) + (DELAY + (ABSOLUTE + (PORT dataa (1695:1695:1695) (1747:1747:1747)) + (PORT datab (927:927:927) (961:961:961)) + (PORT datac (953:953:953) (1006:1006:1006)) + (PORT datad (386:386:386) (457:457:457)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|decode_state_\|DFFE_instED) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1566:1566:1566) (1548:1548:1548)) + (PORT ena (790:790:790) (783:783:783)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|table_xx\~0) + (DELAY + (ABSOLUTE + (PORT dataa (289:289:289) (385:385:385)) + (PORT datad (383:383:383) (443:443:443)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal34\~0) + (DELAY + (ABSOLUTE + (PORT dataa (979:979:979) (1062:1062:1062)) + (PORT datab (661:661:661) (688:688:688)) + (PORT datac (566:566:566) (598:598:598)) + (PORT datad (681:681:681) (729:729:729)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1175:1175:1175) (1210:1210:1210)) + (PORT datab (1702:1702:1702) (1772:1772:1772)) + (PORT datac (799:799:799) (820:820:820)) + (PORT datad (1291:1291:1291) (1362:1362:1362)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1325:1325:1325) (1414:1414:1414)) + (PORT datab (691:691:691) (743:743:743)) + (PORT datac (1107:1107:1107) (1128:1128:1128)) + (PORT datad (908:908:908) (955:955:955)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~4) + (DELAY + (ABSOLUTE + (PORT dataa (876:876:876) (916:916:916)) + (PORT datab (1259:1259:1259) (1324:1324:1324)) + (PORT datac (950:950:950) (994:994:994)) + (PORT datad (668:668:668) (713:713:713)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1319:1319:1319) (1408:1408:1408)) + (PORT datab (688:688:688) (747:747:747)) + (PORT datac (846:846:846) (880:880:880)) + (PORT datad (900:900:900) (917:917:917)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1630:1630:1630) (1685:1685:1685)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (955:955:955) (1002:1002:1002)) + (PORT datad (1291:1291:1291) (1368:1368:1368)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~7) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (242:242:242)) + (PORT datab (200:200:200) (240:240:240)) + (PORT datac (600:600:600) (608:608:608)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~8) + (DELAY + (ABSOLUTE + (PORT dataa (817:817:817) (853:853:853)) + (PORT datab (1522:1522:1522) (1531:1531:1531)) + (PORT datac (920:920:920) (963:963:963)) + (PORT datad (669:669:669) (714:714:714)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1178:1178:1178) (1214:1214:1214)) + (PORT datab (933:933:933) (990:990:990)) + (PORT datac (624:624:624) (641:641:641)) + (PORT datad (1672:1672:1672) (1732:1732:1732)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1320:1320:1320) (1407:1407:1407)) + (PORT datab (204:204:204) (246:246:246)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (1348:1348:1348) (1364:1364:1364)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~16) + (DELAY + (ABSOLUTE + (PORT dataa (862:862:862) (922:922:922)) + (PORT datab (1255:1255:1255) (1310:1310:1310)) + (PORT datac (1428:1428:1428) (1489:1489:1489)) + (PORT datad (195:195:195) (220:220:220)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~17) + (DELAY + (ABSOLUTE + (PORT dataa (973:973:973) (1059:1059:1059)) + (PORT datab (1386:1386:1386) (1448:1448:1448)) + (PORT datac (203:203:203) (242:242:242)) + (PORT datad (652:652:652) (687:687:687)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1158:1158:1158) (1234:1234:1234)) + (PORT datab (247:247:247) (295:295:295)) + (PORT datac (874:874:874) (913:913:913)) + (PORT datad (179:179:179) (206:206:206)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~18) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (371:371:371)) + (PORT datab (1142:1142:1142) (1187:1187:1187)) + (PORT datac (194:194:194) (226:226:226)) + (PORT datad (599:599:599) (612:612:612)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1844:1844:1844) (1951:1951:1951)) + (PORT datab (1206:1206:1206) (1281:1281:1281)) + (PORT datac (1620:1620:1620) (1731:1731:1731)) + (PORT datad (1706:1706:1706) (1792:1792:1792)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_pc\~3) + (DELAY + (ABSOLUTE + (PORT dataa (664:664:664) (682:682:682)) + (PORT datab (1450:1450:1450) (1461:1461:1461)) + (PORT datac (849:849:849) (882:882:882)) + (PORT datad (637:637:637) (694:694:694)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_pc) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (241:241:241)) + (PORT datab (890:890:890) (940:940:940)) + (PORT datac (572:572:572) (593:593:593)) + (PORT datad (841:841:841) (863:863:863)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_72) + (DELAY + (ABSOLUTE + (PORT dataa (1040:1040:1040) (1066:1066:1066)) + (PORT datac (1102:1102:1102) (1139:1139:1139)) + (PORT datad (899:899:899) (932:932:932)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1078:1078:1078) (1103:1103:1103)) + (PORT datab (711:711:711) (744:744:744)) + (PORT datac (1364:1364:1364) (1375:1375:1375)) + (PORT datad (648:648:648) (671:671:671)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1533:1533:1533)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1256:1256:1256) (1263:1263:1263)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1533:1533:1533)) + (PORT asdata (537:537:537) (567:567:567)) + (PORT ena (1448:1448:1448) (1437:1437:1437)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (651:651:651) (685:685:685)) + (PORT datab (711:711:711) (743:743:743)) + (PORT datad (649:649:649) (669:669:669)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1079:1079:1079) (1101:1101:1101)) + (PORT datab (379:379:379) (452:452:452)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (301:301:301) (307:307:307)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (244:244:244) (296:296:296)) + (PORT datab (658:658:658) (679:679:679)) + (PORT datac (1367:1367:1367) (1374:1374:1374)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1530:1530:1530)) + (PORT asdata (1388:1388:1388) (1436:1436:1436)) + (PORT ena (1240:1240:1240) (1223:1223:1223)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1530:1530:1530)) + (PORT asdata (1390:1390:1390) (1437:1437:1437)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~50) + (DELAY + (ABSOLUTE + (PORT dataa (723:723:723) (755:755:755)) + (PORT datab (242:242:242) (323:323:323)) + (PORT datad (233:233:233) (272:272:272)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1533:1533:1533)) + (PORT asdata (1188:1188:1188) (1204:1204:1204)) + (PORT ena (1201:1201:1201) (1198:1198:1198)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~53) + (DELAY + (ABSOLUTE + (PORT dataa (1201:1201:1201) (1220:1220:1220)) + (PORT datab (1150:1150:1150) (1180:1180:1180)) + (PORT datad (396:396:396) (440:440:440)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1533:1533:1533)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1503:1503:1503) (1497:1497:1497)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1533:1533:1533)) + (PORT asdata (935:935:935) (960:960:960)) + (PORT ena (1227:1227:1227) (1249:1249:1249)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~54) + (DELAY + (ABSOLUTE + (PORT dataa (705:705:705) (779:779:779)) + (PORT datab (242:242:242) (324:324:324)) + (PORT datad (696:696:696) (747:747:747)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT asdata (1458:1458:1458) (1482:1482:1482)) + (PORT ena (1229:1229:1229) (1240:1240:1240)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT asdata (1461:1461:1461) (1487:1487:1487)) + (PORT ena (1168:1168:1168) (1147:1147:1147)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~52) + (DELAY + (ABSOLUTE + (PORT dataa (693:693:693) (728:728:728)) + (PORT datab (269:269:269) (323:323:323)) + (PORT datad (217:217:217) (286:286:286)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (1214:1214:1214) (1221:1221:1221)) + (PORT ena (1440:1440:1440) (1419:1419:1419)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (1216:1216:1216) (1225:1225:1225)) + (PORT ena (1225:1225:1225) (1236:1236:1236)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (699:699:699) (763:763:763)) + (PORT datab (243:243:243) (325:325:325)) + (PORT datad (618:618:618) (641:641:641)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~55) + (DELAY + (ABSOLUTE + (PORT dataa (377:377:377) (399:399:399)) + (PORT datab (605:605:605) (629:629:629)) + (PORT datac (540:540:540) (552:552:552)) + (PORT datad (339:339:339) (358:358:358)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (932:932:932) (939:939:939)) + (PORT ena (790:790:790) (782:782:782)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[5\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1536:1536:1536) (1586:1586:1586)) + (PORT datab (2170:2170:2170) (2209:2209:2209)) + (PORT datad (1366:1366:1366) (1388:1388:1388)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (985:985:985) (1002:1002:1002)) + (PORT ena (981:981:981) (980:980:980)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (589:589:589) (597:597:597)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1190:1190:1190) (1164:1164:1164)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~49) + (DELAY + (ABSOLUTE + (PORT dataa (695:695:695) (731:731:731)) + (PORT datab (697:697:697) (721:721:721)) + (PORT datad (217:217:217) (285:285:285)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~56) + (DELAY + (ABSOLUTE + (PORT dataa (814:814:814) (868:868:868)) + (PORT datab (975:975:975) (1017:1017:1017)) + (PORT datac (528:528:528) (538:538:538)) + (PORT datad (342:342:342) (365:365:365)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~57) + (DELAY + (ABSOLUTE + (PORT dataa (657:657:657) (678:678:678)) + (PORT datab (920:920:920) (958:958:958)) + (PORT datac (1143:1143:1143) (1171:1171:1171)) + (PORT datad (553:553:553) (570:570:570)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[5\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (628:628:628) (667:667:667)) + (PORT datab (689:689:689) (718:718:718)) + (PORT datac (529:529:529) (546:546:546)) + (PORT datad (577:577:577) (584:584:584)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[5\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (347:347:347) (379:379:379)) + (PORT datab (634:634:634) (653:653:653)) + (PORT datac (224:224:224) (279:279:279)) + (PORT datad (703:703:703) (733:733:733)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sw1_\|db_down\[5\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (669:669:669) (734:734:734)) + (PORT datab (1402:1402:1402) (1399:1399:1399)) + (PORT datac (954:954:954) (970:970:970)) + (PORT datad (840:840:840) (860:860:860)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_36) + (DELAY + (ABSOLUTE + (PORT dataa (864:864:864) (926:926:926)) + (PORT datab (665:665:665) (685:685:685)) + (PORT datac (1135:1135:1135) (1146:1146:1146)) + (PORT datad (599:599:599) (617:617:617)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|flags_yf) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1440:1440:1440) (1432:1432:1432)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[5\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (867:867:867) (885:885:885)) + (PORT datab (221:221:221) (267:267:267)) + (PORT datac (847:847:847) (882:882:882)) + (PORT datad (200:200:200) (226:226:226)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[5\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (205:205:205) (249:249:249)) + (PORT datab (601:601:601) (610:610:610)) + (PORT datac (1879:1879:1879) (1868:1868:1868)) + (PORT datad (383:383:383) (406:406:406)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[5\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (829:829:829) (849:849:849)) + (PORT datab (393:393:393) (429:429:429)) + (PORT datac (174:174:174) (208:208:208)) + (PORT datad (216:216:216) (251:251:251)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (749:749:749) (798:798:798)) + (PORT clk (1860:1860:1860) (1888:1888:1888)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3623:3623:3623) (3852:3852:3852)) + (PORT d[1] (1238:1238:1238) (1321:1321:1321)) + (PORT d[2] (1219:1219:1219) (1249:1249:1249)) + (PORT d[3] (3278:3278:3278) (3487:3487:3487)) + (PORT d[4] (3539:3539:3539) (3704:3704:3704)) + (PORT d[5] (4281:4281:4281) (4445:4445:4445)) + (PORT d[6] (1319:1319:1319) (1374:1374:1374)) + (PORT d[7] (2567:2567:2567) (2787:2787:2787)) + (PORT d[8] (3323:3323:3323) (3447:3447:3447)) + (PORT d[9] (1517:1517:1517) (1578:1578:1578)) + (PORT d[10] (4299:4299:4299) (4577:4577:4577)) + (PORT d[11] (3876:3876:3876) (4125:4125:4125)) + (PORT d[12] (1520:1520:1520) (1580:1580:1580)) + (PORT clk (1857:1857:1857) (1884:1884:1884)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1512:1512:1512) (1505:1505:1505)) + (PORT clk (1857:1857:1857) (1884:1884:1884)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1888:1888:1888)) + (PORT d[0] (2707:2707:2707) (2660:2660:2660)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1847:1847:1847)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1010:1010:1010)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1011:1011:1011)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1011:1011:1011)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1011:1011:1011)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1106:1106:1106) (1158:1158:1158)) + (PORT clk (1860:1860:1860) (1887:1887:1887)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2907:2907:2907) (3158:3158:3158)) + (PORT d[1] (980:980:980) (1020:1020:1020)) + (PORT d[2] (1229:1229:1229) (1296:1296:1296)) + (PORT d[3] (3293:3293:3293) (3527:3527:3527)) + (PORT d[4] (1036:1036:1036) (1093:1093:1093)) + (PORT d[5] (1454:1454:1454) (1511:1511:1511)) + (PORT d[6] (1303:1303:1303) (1332:1332:1332)) + (PORT d[7] (2564:2564:2564) (2814:2814:2814)) + (PORT d[8] (3570:3570:3570) (3717:3717:3717)) + (PORT d[9] (1493:1493:1493) (1571:1571:1571)) + (PORT d[10] (4286:4286:4286) (4579:4579:4579)) + (PORT d[11] (3883:3883:3883) (4119:4119:4119)) + (PORT d[12] (1501:1501:1501) (1562:1562:1562)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1837:1837:1837) (1761:1761:1761)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (PORT d[0] (2502:2502:2502) (2456:2456:2456)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1846:1846:1846)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (743:743:743) (785:785:785)) + (PORT clk (1860:1860:1860) (1887:1887:1887)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3640:3640:3640) (3867:3867:3867)) + (PORT d[1] (1263:1263:1263) (1344:1344:1344)) + (PORT d[2] (1555:1555:1555) (1618:1618:1618)) + (PORT d[3] (2985:2985:2985) (3180:3180:3180)) + (PORT d[4] (3522:3522:3522) (3690:3690:3690)) + (PORT d[5] (4009:4009:4009) (4176:4176:4176)) + (PORT d[6] (1585:1585:1585) (1639:1639:1639)) + (PORT d[7] (2268:2268:2268) (2493:2493:2493)) + (PORT d[8] (3312:3312:3312) (3456:3456:3456)) + (PORT d[9] (1780:1780:1780) (1860:1860:1860)) + (PORT d[10] (3993:3993:3993) (4259:4259:4259)) + (PORT d[11] (3579:3579:3579) (3788:3788:3788)) + (PORT d[12] (1755:1755:1755) (1839:1839:1839)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1528:1528:1528) (1500:1500:1500)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (PORT d[0] (3101:3101:3101) (3070:3070:3070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1846:1846:1846)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (708:708:708) (730:730:730)) + (PORT clk (1857:1857:1857) (1884:1884:1884)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3320:3320:3320) (3529:3529:3529)) + (PORT d[1] (1925:1925:1925) (2035:2035:2035)) + (PORT d[2] (1583:1583:1583) (1671:1671:1671)) + (PORT d[3] (2976:2976:2976) (3185:3185:3185)) + (PORT d[4] (3240:3240:3240) (3388:3388:3388)) + (PORT d[5] (3971:3971:3971) (4117:4117:4117)) + (PORT d[6] (1878:1878:1878) (1973:1973:1973)) + (PORT d[7] (2258:2258:2258) (2473:2473:2473)) + (PORT d[8] (3006:3006:3006) (3103:3103:3103)) + (PORT d[9] (2107:2107:2107) (2217:2217:2217)) + (PORT d[10] (3706:3706:3706) (3953:3953:3953)) + (PORT d[11] (3262:3262:3262) (3467:3467:3467)) + (PORT d[12] (1721:1721:1721) (1829:1829:1829)) + (PORT clk (1854:1854:1854) (1880:1880:1880)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1774:1774:1774) (1779:1779:1779)) + (PORT clk (1854:1854:1854) (1880:1880:1880)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1884:1884:1884)) + (PORT d[0] (2663:2663:2663) (2678:2678:2678)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1817:1817:1817) (1843:1843:1843)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1002:1002:1002) (1006:1006:1006)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1003:1003:1003) (1007:1007:1007)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1003:1003:1003) (1007:1007:1007)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1003:1003:1003) (1007:1007:1007)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (873:873:873) (896:896:896)) + (PORT datab (1443:1443:1443) (1545:1545:1545)) + (PORT datac (837:837:837) (843:843:843)) + (PORT datad (1491:1491:1491) (1579:1579:1579)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1224:1224:1224) (1254:1254:1254)) + (PORT datab (1250:1250:1250) (1252:1252:1252)) + (PORT datac (1806:1806:1806) (1901:1901:1901)) + (PORT datad (312:312:312) (328:328:328)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2736:2736:2736) (2927:2927:2927)) + (PORT d[1] (2212:2212:2212) (2337:2337:2337)) + (PORT d[2] (2433:2433:2433) (2537:2537:2537)) + (PORT d[3] (2574:2574:2574) (2745:2745:2745)) + (PORT d[4] (2659:2659:2659) (2748:2748:2748)) + (PORT d[5] (2923:2923:2923) (3031:3031:3031)) + (PORT d[6] (2947:2947:2947) (3063:3063:3063)) + (PORT d[7] (1963:1963:1963) (2155:2155:2155)) + (PORT d[8] (2395:2395:2395) (2452:2452:2452)) + (PORT d[9] (3128:3128:3128) (3211:3211:3211)) + (PORT d[10] (4046:4046:4046) (4316:4316:4316)) + (PORT d[11] (3089:3089:3089) (3284:3284:3284)) + (PORT d[12] (2737:2737:2737) (2894:2894:2894)) + (PORT clk (1867:1867:1867) (1893:1893:1893)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1867:1867:1867) (1893:1893:1893)) + (PORT d[0] (2745:2745:2745) (2807:2807:2807)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1868:1868:1868) (1894:1894:1894)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1830:1830:1830) (1856:1856:1856)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1015:1015:1015) (1019:1019:1019)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1016:1016:1016) (1020:1020:1020)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1016:1016:1016) (1020:1020:1020)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1016:1016:1016) (1020:1020:1020)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1979:1979:1979) (2050:2050:2050)) + (PORT d[1] (1590:1590:1590) (1643:1643:1643)) + (PORT d[2] (2393:2393:2393) (2525:2525:2525)) + (PORT d[3] (2491:2491:2491) (2649:2649:2649)) + (PORT d[4] (1238:1238:1238) (1305:1305:1305)) + (PORT d[5] (1545:1545:1545) (1605:1605:1605)) + (PORT d[6] (2631:2631:2631) (2688:2688:2688)) + (PORT d[7] (1839:1839:1839) (1978:1978:1978)) + (PORT d[8] (1582:1582:1582) (1642:1642:1642)) + (PORT d[9] (3336:3336:3336) (3585:3585:3585)) + (PORT d[10] (1236:1236:1236) (1276:1276:1276)) + (PORT d[11] (1201:1201:1201) (1245:1245:1245)) + (PORT d[12] (1657:1657:1657) (1673:1673:1673)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1883:1883:1883)) + (PORT d[0] (2372:2372:2372) (2336:2336:2336)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1846:1846:1846)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1159:1159:1159) (1159:1159:1159)) + (PORT clk (1857:1857:1857) (1885:1885:1885)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3013:3013:3013) (3204:3204:3204)) + (PORT d[1] (3047:3047:3047) (3183:3183:3183)) + (PORT d[2] (1908:1908:1908) (1988:1988:1988)) + (PORT d[3] (2333:2333:2333) (2531:2531:2531)) + (PORT d[4] (2951:2951:2951) (3077:3077:3077)) + (PORT d[5] (3204:3204:3204) (3342:3342:3342)) + (PORT d[6] (2360:2360:2360) (2459:2459:2459)) + (PORT d[7] (2245:2245:2245) (2426:2426:2426)) + (PORT d[8] (2709:2709:2709) (2808:2808:2808)) + (PORT d[9] (2628:2628:2628) (2722:2722:2722)) + (PORT d[10] (3690:3690:3690) (3918:3918:3918)) + (PORT d[11] (3268:3268:3268) (3477:3477:3477)) + (PORT d[12] (2070:2070:2070) (2181:2181:2181)) + (PORT clk (1854:1854:1854) (1881:1881:1881)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3372:3372:3372) (3395:3395:3395)) + (PORT clk (1854:1854:1854) (1881:1881:1881)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1885:1885:1885)) + (PORT d[0] (3350:3350:3350) (3368:3368:3368)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1886:1886:1886)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1886:1886:1886)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1886:1886:1886)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1886:1886:1886)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1810:1810:1810)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2713:2713:2713) (2908:2908:2908)) + (PORT clk (1822:1822:1822) (1816:1816:1816)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4225:4225:4225) (4211:4211:4211)) + (PORT d[1] (4225:4225:4225) (4280:4280:4280)) + (PORT d[2] (4120:4120:4120) (4160:4160:4160)) + (PORT d[3] (4205:4205:4205) (4285:4285:4285)) + (PORT d[4] (4152:4152:4152) (4284:4284:4284)) + (PORT d[5] (4348:4348:4348) (4392:4392:4392)) + (PORT d[6] (4200:4200:4200) (4260:4260:4260)) + (PORT d[7] (4039:4039:4039) (4157:4157:4157)) + (PORT d[8] (4218:4218:4218) (4264:4264:4264)) + (PORT d[9] (4253:4253:4253) (4354:4354:4354)) + (PORT d[10] (4253:4253:4253) (4298:4298:4298)) + (PORT d[11] (4351:4351:4351) (4448:4448:4448)) + (PORT d[12] (4022:4022:4022) (4075:4075:4075)) + (PORT clk (1818:1818:1818) (1812:1812:1812)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1822:1822:1822) (1816:1816:1816)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1823:1823:1823) (1817:1817:1817)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1823:1823:1823) (1817:1817:1817)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1823:1823:1823) (1817:1817:1817)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1823:1823:1823) (1817:1817:1817)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1246:1246:1246) (1307:1307:1307)) + (PORT clk (1866:1866:1866) (1893:1893:1893)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2843:2843:2843) (3053:3053:3053)) + (PORT d[1] (2717:2717:2717) (2847:2847:2847)) + (PORT d[2] (2495:2495:2495) (2606:2606:2606)) + (PORT d[3] (2312:2312:2312) (2504:2504:2504)) + (PORT d[4] (2948:2948:2948) (3057:3057:3057)) + (PORT d[5] (2937:2937:2937) (3064:3064:3064)) + (PORT d[6] (2974:2974:2974) (3090:3090:3090)) + (PORT d[7] (1949:1949:1949) (2124:2124:2124)) + (PORT d[8] (2408:2408:2408) (2483:2483:2483)) + (PORT d[9] (2376:2376:2376) (2489:2489:2489)) + (PORT d[10] (3631:3631:3631) (3871:3871:3871)) + (PORT d[11] (3258:3258:3258) (3445:3445:3445)) + (PORT d[12] (2606:2606:2606) (2706:2706:2706)) + (PORT clk (1863:1863:1863) (1889:1889:1889)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2477:2477:2477) (2512:2512:2512)) + (PORT clk (1863:1863:1863) (1889:1889:1889)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1866:1866:1866) (1893:1893:1893)) + (PORT d[0] (3408:3408:3408) (3363:3363:3363)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1867:1867:1867) (1894:1894:1894)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1867:1867:1867) (1894:1894:1894)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1867:1867:1867) (1894:1894:1894)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1867:1867:1867) (1894:1894:1894)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1821:1821:1821) (1818:1818:1818)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2996:2996:2996) (3194:3194:3194)) + (PORT clk (1831:1831:1831) (1824:1824:1824)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4076:4076:4076) (4059:4059:4059)) + (PORT d[1] (4345:4345:4345) (4349:4349:4349)) + (PORT d[2] (4182:4182:4182) (4239:4239:4239)) + (PORT d[3] (4358:4358:4358) (4385:4385:4385)) + (PORT d[4] (4208:4208:4208) (4286:4286:4286)) + (PORT d[5] (4678:4678:4678) (4720:4720:4720)) + (PORT d[6] (4167:4167:4167) (4246:4246:4246)) + (PORT d[7] (4191:4191:4191) (4279:4279:4279)) + (PORT d[8] (4219:4219:4219) (4290:4290:4290)) + (PORT d[9] (4270:4270:4270) (4340:4340:4340)) + (PORT d[10] (4050:4050:4050) (4047:4047:4047)) + (PORT d[11] (4323:4323:4323) (4360:4360:4360)) + (PORT d[12] (4220:4220:4220) (4284:4284:4284)) + (PORT clk (1827:1827:1827) (1820:1820:1820)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1831:1831:1831) (1824:1824:1824)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1832:1832:1832) (1825:1825:1825)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1832:1832:1832) (1825:1825:1825)) + (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1832:1832:1832) (1825:1825:1825)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1832:1832:1832) (1825:1825:1825)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1823:1823:1823) (1820:1820:1820)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Mux2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1266:1266:1266) (1329:1329:1329)) + (PORT datab (2194:2194:2194) (2333:2333:2333)) + (PORT datac (906:906:906) (919:919:919)) + (PORT datad (1091:1091:1091) (1135:1135:1135)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Mux2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1698:1698:1698) (1835:1835:1835)) + (PORT datab (1402:1402:1402) (1435:1435:1435)) + (PORT datac (1386:1386:1386) (1465:1465:1465)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[5\]\~87) + (DELAY + (ABSOLUTE + (PORT dataa (2046:2046:2046) (2109:2109:2109)) + (PORT datab (199:199:199) (237:237:237)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (1259:1259:1259) (1359:1359:1359)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[5\]\~68) + (DELAY + (ABSOLUTE + (PORT dataa (1411:1411:1411) (1486:1486:1486)) + (PORT datab (1257:1257:1257) (1350:1350:1350)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (1420:1420:1420) (1435:1435:1435)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[5\]\~77) + (DELAY + (ABSOLUTE + (PORT datac (192:192:192) (226:226:226)) + (PORT datad (1410:1410:1410) (1459:1459:1459)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[5\]) + (DELAY + (ABSOLUTE + (PORT dataa (1673:1673:1673) (1675:1675:1675)) + (PORT datab (380:380:380) (406:406:406)) + (PORT datac (1376:1376:1376) (1410:1410:1410)) + (PORT datad (675:675:675) (717:717:717)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1527:1527:1527) (1531:1531:1531)) + (PORT asdata (659:659:659) (676:676:676)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[5\]\~14) + (DELAY + (ABSOLUTE + (PORT datab (615:615:615) (648:648:648)) + (PORT datac (537:537:537) (559:559:559)) + (PORT datad (238:238:238) (306:306:306)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[5\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (722:722:722) (779:779:779)) + (PORT datab (654:654:654) (712:712:712)) + (PORT datac (612:612:612) (664:664:664)) + (PORT datad (1669:1669:1669) (1694:1694:1694)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT asdata (948:948:948) (981:981:981)) + (PORT clrn (1567:1567:1567) (1549:1549:1549)) + (PORT ena (1667:1667:1667) (1658:1658:1658)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~8) + (DELAY + (ABSOLUTE + (PORT dataa (2526:2526:2526) (2690:2690:2690)) + (PORT datab (952:952:952) (990:990:990)) + (PORT datac (1195:1195:1195) (1230:1230:1230)) + (PORT datad (907:907:907) (962:962:962)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1319:1319:1319) (1432:1432:1432)) + (PORT datab (1270:1270:1270) (1304:1304:1304)) + (PORT datac (936:936:936) (1009:1009:1009)) + (PORT datad (1321:1321:1321) (1424:1424:1424)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1782:1782:1782) (1824:1824:1824)) + (PORT datab (1204:1204:1204) (1229:1229:1229)) + (PORT datac (1706:1706:1706) (1772:1772:1772)) + (PORT datad (1238:1238:1238) (1293:1293:1293)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (1155:1155:1155) (1222:1222:1222)) + (PORT datac (191:191:191) (224:224:224)) + (PORT datad (1232:1232:1232) (1289:1289:1289)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla31pla33M4T1_3) + (DELAY + (ABSOLUTE + (PORT dataa (1181:1181:1181) (1249:1249:1249)) + (PORT datab (2049:2049:2049) (2175:2175:2175)) + (PORT datac (199:199:199) (236:236:236)) + (PORT datad (1656:1656:1656) (1764:1764:1764)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1516:1516:1516) (1555:1555:1555)) + (PORT datab (196:196:196) (235:235:235)) + (PORT datac (193:193:193) (227:227:227)) + (PORT datad (861:861:861) (876:876:876)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1765:1765:1765) (1812:1812:1812)) + (PORT datab (1649:1649:1649) (1786:1786:1786)) + (PORT datac (1241:1241:1241) (1272:1272:1272)) + (PORT datad (1117:1117:1117) (1148:1148:1148)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~7) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (196:196:196) (234:234:234)) + (PORT datac (349:349:349) (373:373:373)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~66) + (DELAY + (ABSOLUTE + (PORT dataa (292:292:292) (389:389:389)) + (PORT datab (275:275:275) (361:361:361)) + (PORT datac (1338:1338:1338) (1403:1403:1403)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~80) + (DELAY + (ABSOLUTE + (PORT dataa (991:991:991) (1073:1073:1073)) + (PORT datab (686:686:686) (745:745:745)) + (PORT datac (1185:1185:1185) (1260:1260:1260)) + (PORT datad (1018:1018:1018) (1093:1093:1093)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~81) + (DELAY + (ABSOLUTE + (PORT dataa (204:204:204) (249:249:249)) + (PORT datac (264:264:264) (352:352:352)) + (PORT datad (962:962:962) (1026:1026:1026)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~82) + (DELAY + (ABSOLUTE + (PORT dataa (669:669:669) (704:704:704)) + (PORT datab (228:228:228) (269:269:269)) + (PORT datad (172:172:172) (198:198:198)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1555:1555:1555) (1547:1547:1547)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~84) + (DELAY + (ABSOLUTE + (PORT dataa (1483:1483:1483) (1544:1544:1544)) + (PORT datab (720:720:720) (777:777:777)) + (PORT datad (915:915:915) (979:979:979)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~83) + (DELAY + (ABSOLUTE + (PORT dataa (1014:1014:1014) (1115:1115:1115)) + (PORT datab (1848:1848:1848) (1906:1906:1906)) + (PORT datac (1448:1448:1448) (1501:1501:1501)) + (PORT datad (672:672:672) (725:725:725)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~85) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (247:247:247)) + (PORT datab (200:200:200) (240:240:240)) + (PORT datad (183:183:183) (213:213:213)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1533:1533:1533)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1559:1559:1559) (1552:1552:1552)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (606:606:606) (635:635:635)) + (PORT datab (671:671:671) (733:733:733)) + (PORT datac (748:748:748) (748:748:748)) + (PORT datad (217:217:217) (285:285:285)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]\~78) + (DELAY + (ABSOLUTE + (PORT dataa (755:755:755) (828:828:828)) + (PORT datab (950:950:950) (1074:1074:1074)) + (PORT datac (346:346:346) (368:368:368)) + (PORT datad (655:655:655) (738:738:738)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]\~79) + (DELAY + (ABSOLUTE + (PORT dataa (935:935:935) (1020:1020:1020)) + (PORT datad (348:348:348) (372:372:372)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1558:1558:1558) (1550:1550:1550)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]\~76) + (DELAY + (ABSOLUTE + (PORT dataa (935:935:935) (1023:1023:1023)) + (PORT datab (641:641:641) (657:657:657)) + (PORT datad (809:809:809) (821:821:821)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1558:1558:1558) (1550:1550:1550)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[0\]\~77) + (DELAY + (ABSOLUTE + (PORT dataa (935:935:935) (1025:1025:1025)) + (PORT datab (643:643:643) (729:729:729)) + (PORT datad (373:373:373) (399:399:399)) + (IOPATH dataa combout (301:301:301) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1558:1558:1558) (1550:1550:1550)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (244:244:244) (331:331:331)) + (PORT datab (1037:1037:1037) (1114:1114:1114)) + (PORT datac (1050:1050:1050) (1049:1049:1049)) + (PORT datad (217:217:217) (286:286:286)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1318:1318:1318) (1412:1412:1412)) + (PORT datab (424:424:424) (511:511:511)) + (PORT datac (962:962:962) (1039:1039:1039)) + (PORT datad (943:943:943) (1007:1007:1007)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\~71) + (DELAY + (ABSOLUTE + (PORT dataa (233:233:233) (282:282:282)) + (PORT datab (719:719:719) (787:787:787)) + (PORT datac (952:952:952) (1033:1033:1033)) + (PORT datad (609:609:609) (621:621:621)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (336:336:336) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~70) + (DELAY + (ABSOLUTE + (PORT dataa (1210:1210:1210) (1301:1301:1301)) + (PORT datad (990:990:990) (1066:1066:1066)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~72) + (DELAY + (ABSOLUTE + (PORT dataa (301:301:301) (394:394:394)) + (PORT datab (668:668:668) (685:685:685)) + (PORT datac (563:563:563) (590:590:590)) + (PORT datad (608:608:608) (620:620:620)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (705:705:705) (807:807:807)) + (PORT datab (415:415:415) (494:494:494)) + (PORT datac (678:678:678) (748:748:748)) + (PORT datad (2180:2180:2180) (2284:2284:2284)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\~73) + (DELAY + (ABSOLUTE + (PORT dataa (303:303:303) (398:398:398)) + (PORT datab (222:222:222) (261:261:261)) + (PORT datac (931:931:931) (998:998:998)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~74) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (246:246:246)) + (PORT datab (199:199:199) (239:239:239)) + (PORT datad (433:433:433) (509:509:509)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1555:1555:1555) (1548:1548:1548)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\~2) + (DELAY + (ABSOLUTE + (PORT datab (707:707:707) (761:761:761)) + (PORT datac (2400:2400:2400) (2577:2577:2577)) + (PORT datad (1458:1458:1458) (1517:1517:1517)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~41) + (DELAY + (ABSOLUTE + (PORT dataa (243:243:243) (330:330:330)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (1087:1087:1087) (1090:1090:1090)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~89) + (DELAY + (ABSOLUTE + (PORT dataa (663:663:663) (751:751:751)) + (PORT datab (1009:1009:1009) (1098:1098:1098)) + (PORT datac (711:711:711) (784:784:784)) + (PORT datad (906:906:906) (1032:1032:1032)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~90) + (DELAY + (ABSOLUTE + (PORT dataa (1583:1583:1583) (1677:1677:1677)) + (PORT datab (199:199:199) (239:239:239)) + (PORT datac (850:850:850) (868:868:868)) + (PORT datad (818:818:818) (889:889:889)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~91) + (DELAY + (ABSOLUTE + (PORT datab (1037:1037:1037) (1058:1058:1058)) + (PORT datad (924:924:924) (982:982:982)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1533:1533:1533)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1559:1559:1559) (1551:1551:1551)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~131) + (DELAY + (ABSOLUTE + (PORT dataa (666:666:666) (735:735:735)) + (PORT datab (827:827:827) (847:847:847)) + (PORT datad (439:439:439) (517:517:517)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr16\~3) + (DELAY + (ABSOLUTE + (PORT datac (952:952:952) (1022:1022:1022)) + (PORT datad (969:969:969) (1052:1052:1052)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~86) + (DELAY + (ABSOLUTE + (PORT dataa (936:936:936) (1029:1029:1029)) + (PORT datab (239:239:239) (284:284:284)) + (PORT datac (173:173:173) (207:207:207)) + (PORT datad (654:654:654) (737:737:737)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~87) + (DELAY + (ABSOLUTE + (PORT dataa (843:843:843) (929:929:929)) + (PORT datab (825:825:825) (879:879:879)) + (PORT datac (347:347:347) (381:381:381)) + (PORT datad (911:911:911) (1030:1030:1030)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~88) + (DELAY + (ABSOLUTE + (PORT dataa (893:893:893) (911:911:911)) + (PORT datad (925:925:925) (982:982:982)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1533:1533:1533)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1559:1559:1559) (1551:1551:1551)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~43) + (DELAY + (ABSOLUTE + (PORT dataa (1384:1384:1384) (1510:1510:1510)) + (PORT datab (242:242:242) (324:324:324)) + (PORT datac (214:214:214) (290:290:290)) + (PORT datad (601:601:601) (621:621:621)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~44) + (DELAY + (ABSOLUTE + (PORT dataa (333:333:333) (369:369:369)) + (PORT datab (826:826:826) (844:844:844)) + (PORT datac (2857:2857:2857) (3133:3133:3133)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (964:964:964) (1010:1010:1010)) + (PORT clk (1852:1852:1852) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1763:1763:1763) (1827:1827:1827)) + (PORT d[1] (4509:4509:4509) (4694:4694:4694)) + (PORT d[2] (2644:2644:2644) (2832:2832:2832)) + (PORT d[3] (2892:2892:2892) (3019:3019:3019)) + (PORT d[4] (4184:4184:4184) (4338:4338:4338)) + (PORT d[5] (2041:2041:2041) (2118:2118:2118)) + (PORT d[6] (1910:1910:1910) (1958:1958:1958)) + (PORT d[7] (2150:2150:2150) (2311:2311:2311)) + (PORT d[8] (2790:2790:2790) (2934:2934:2934)) + (PORT d[9] (2801:2801:2801) (3009:3009:3009)) + (PORT d[10] (2500:2500:2500) (2657:2657:2657)) + (PORT d[11] (2674:2674:2674) (2772:2772:2772)) + (PORT d[12] (3653:3653:3653) (3814:3814:3814)) + (PORT clk (1849:1849:1849) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1741:1741:1741) (1730:1730:1730)) + (PORT clk (1849:1849:1849) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1879:1879:1879)) + (PORT d[0] (2286:2286:2286) (2237:2237:2237)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (988:988:988) (1037:1037:1037)) + (PORT clk (1852:1852:1852) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3402:3402:3402) (3662:3662:3662)) + (PORT d[1] (4509:4509:4509) (4693:4693:4693)) + (PORT d[2] (2666:2666:2666) (2856:2856:2856)) + (PORT d[3] (2504:2504:2504) (2645:2645:2645)) + (PORT d[4] (4145:4145:4145) (4301:4301:4301)) + (PORT d[5] (2075:2075:2075) (2166:2166:2166)) + (PORT d[6] (3311:3311:3311) (3443:3443:3443)) + (PORT d[7] (3625:3625:3625) (3776:3776:3776)) + (PORT d[8] (3159:3159:3159) (3368:3368:3368)) + (PORT d[9] (2487:2487:2487) (2679:2679:2679)) + (PORT d[10] (2231:2231:2231) (2388:2388:2388)) + (PORT d[11] (2673:2673:2673) (2771:2771:2771)) + (PORT d[12] (3369:3369:3369) (3533:3533:3533)) + (PORT clk (1849:1849:1849) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1803:1803:1803) (1749:1749:1749)) + (PORT clk (1849:1849:1849) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1879:1879:1879)) + (PORT d[0] (2590:2590:2590) (2602:2602:2602)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (709:709:709) (734:734:734)) + (PORT clk (1851:1851:1851) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1467:1467:1467) (1536:1536:1536)) + (PORT d[1] (2275:2275:2275) (2353:2353:2353)) + (PORT d[2] (1890:1890:1890) (2010:2010:2010)) + (PORT d[3] (1588:1588:1588) (1687:1687:1687)) + (PORT d[4] (4135:4135:4135) (4312:4312:4312)) + (PORT d[5] (1695:1695:1695) (1762:1762:1762)) + (PORT d[6] (1890:1890:1890) (1938:1938:1938)) + (PORT d[7] (2144:2144:2144) (2301:2301:2301)) + (PORT d[8] (2776:2776:2776) (2940:2940:2940)) + (PORT d[9] (2811:2811:2811) (3005:3005:3005)) + (PORT d[10] (2514:2514:2514) (2694:2694:2694)) + (PORT d[11] (2275:2275:2275) (2383:2383:2383)) + (PORT d[12] (3669:3669:3669) (3854:3854:3854)) + (PORT clk (1848:1848:1848) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1458:1458:1458) (1401:1401:1401)) + (PORT clk (1848:1848:1848) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (PORT d[0] (2246:2246:2246) (2210:2210:2210)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1811:1811:1811) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1029:1029:1029) (1058:1058:1058)) + (PORT clk (1851:1851:1851) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3424:3424:3424) (3686:3686:3686)) + (PORT d[1] (4505:4505:4505) (4687:4687:4687)) + (PORT d[2] (2639:2639:2639) (2822:2822:2822)) + (PORT d[3] (2565:2565:2565) (2693:2693:2693)) + (PORT d[4] (3831:3831:3831) (3986:3986:3986)) + (PORT d[5] (2081:2081:2081) (2177:2177:2177)) + (PORT d[6] (3281:3281:3281) (3405:3405:3405)) + (PORT d[7] (3357:3357:3357) (3510:3510:3510)) + (PORT d[8] (3424:3424:3424) (3624:3624:3624)) + (PORT d[9] (2513:2513:2513) (2710:2710:2710)) + (PORT d[10] (2210:2210:2210) (2369:2369:2369)) + (PORT d[11] (2667:2667:2667) (2785:2785:2785)) + (PORT d[12] (3368:3368:3368) (3532:3532:3532)) + (PORT clk (1848:1848:1848) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2007:2007:2007) (2007:2007:2007)) + (PORT clk (1848:1848:1848) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (PORT d[0] (2533:2533:2533) (2546:2546:2546)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1811:1811:1811) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (952:952:952) (987:987:987)) + (PORT datab (1269:1269:1269) (1337:1337:1337)) + (PORT datac (1528:1528:1528) (1593:1593:1593)) + (PORT datad (1358:1358:1358) (1381:1381:1381)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (325:325:325)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1159:1159:1159) (1196:1196:1196)) + (PORT datab (1184:1184:1184) (1203:1203:1203)) + (PORT datac (1816:1816:1816) (1835:1835:1835)) + (PORT datad (173:173:173) (197:197:197)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2932:2932:2932) (3182:3182:3182)) + (PORT d[1] (978:978:978) (1027:1027:1027)) + (PORT d[2] (2932:2932:2932) (3179:3179:3179)) + (PORT d[3] (989:989:989) (1021:1021:1021)) + (PORT d[4] (979:979:979) (1010:1010:1010)) + (PORT d[5] (1202:1202:1202) (1237:1237:1237)) + (PORT d[6] (998:998:998) (1020:1020:1020)) + (PORT d[7] (2853:2853:2853) (3100:3100:3100)) + (PORT d[8] (3580:3580:3580) (3745:3745:3745)) + (PORT d[9] (1168:1168:1168) (1216:1216:1216)) + (PORT d[10] (4587:4587:4587) (4885:4885:4885)) + (PORT d[11] (1487:1487:1487) (1529:1529:1529)) + (PORT d[12] (2563:2563:2563) (2646:2646:2646)) + (PORT clk (1856:1856:1856) (1882:1882:1882)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1882:1882:1882)) + (PORT d[0] (1247:1247:1247) (1229:1229:1229)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1883:1883:1883)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1819:1819:1819) (1845:1845:1845)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1008:1008:1008)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1566:1566:1566) (1637:1637:1637)) + (PORT clk (1857:1857:1857) (1885:1885:1885)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2776:2776:2776) (2894:2894:2894)) + (PORT d[1] (3418:3418:3418) (3548:3548:3548)) + (PORT d[2] (2596:2596:2596) (2777:2777:2777)) + (PORT d[3] (2111:2111:2111) (2240:2240:2240)) + (PORT d[4] (2684:2684:2684) (2812:2812:2812)) + (PORT d[5] (2721:2721:2721) (2841:2841:2841)) + (PORT d[6] (2973:2973:2973) (3076:3076:3076)) + (PORT d[7] (2385:2385:2385) (2526:2526:2526)) + (PORT d[8] (2615:2615:2615) (2708:2708:2708)) + (PORT d[9] (2730:2730:2730) (2932:2932:2932)) + (PORT d[10] (3110:3110:3110) (3367:3367:3367)) + (PORT d[11] (2295:2295:2295) (2406:2406:2406)) + (PORT d[12] (2998:2998:2998) (3173:3173:3173)) + (PORT clk (1854:1854:1854) (1881:1881:1881)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2828:2828:2828) (2920:2920:2920)) + (PORT clk (1854:1854:1854) (1881:1881:1881)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1885:1885:1885)) + (PORT d[0] (4970:4970:4970) (4881:4881:4881)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1886:1886:1886)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1886:1886:1886)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1886:1886:1886)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1886:1886:1886)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1810:1810:1810)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1001:1001:1001) (1042:1042:1042)) + (PORT clk (1822:1822:1822) (1816:1816:1816)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4142:4142:4142) (4153:4153:4153)) + (PORT d[1] (4301:4301:4301) (4373:4373:4373)) + (PORT d[2] (4153:4153:4153) (4257:4257:4257)) + (PORT d[3] (4216:4216:4216) (4298:4298:4298)) + (PORT d[4] (4121:4121:4121) (4247:4247:4247)) + (PORT d[5] (4316:4316:4316) (4337:4337:4337)) + (PORT d[6] (4117:4117:4117) (4156:4156:4156)) + (PORT d[7] (4126:4126:4126) (4250:4250:4250)) + (PORT d[8] (4272:4272:4272) (4391:4391:4391)) + (PORT d[9] (4091:4091:4091) (4177:4177:4177)) + (PORT d[10] (4258:4258:4258) (4258:4258:4258)) + (PORT d[11] (4239:4239:4239) (4250:4250:4250)) + (PORT d[12] (4162:4162:4162) (4229:4229:4229)) + (PORT clk (1818:1818:1818) (1812:1812:1812)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1822:1822:1822) (1816:1816:1816)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1823:1823:1823) (1817:1817:1817)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1823:1823:1823) (1817:1817:1817)) + (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1823:1823:1823) (1817:1817:1817)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1823:1823:1823) (1817:1817:1817)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1814:1814:1814) (1812:1812:1812)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1323:1323:1323) (1362:1362:1362)) + (PORT clk (1849:1849:1849) (1877:1877:1877)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3073:3073:3073) (3330:3330:3330)) + (PORT d[1] (4002:4002:4002) (4175:4175:4175)) + (PORT d[2] (2366:2366:2366) (2533:2533:2533)) + (PORT d[3] (2529:2529:2529) (2671:2671:2671)) + (PORT d[4] (4109:4109:4109) (4267:4267:4267)) + (PORT d[5] (2341:2341:2341) (2437:2437:2437)) + (PORT d[6] (3267:3267:3267) (3370:3370:3370)) + (PORT d[7] (3313:3313:3313) (3506:3506:3506)) + (PORT d[8] (2482:2482:2482) (2602:2602:2602)) + (PORT d[9] (2471:2471:2471) (2641:2641:2641)) + (PORT d[10] (2662:2662:2662) (2853:2853:2853)) + (PORT d[11] (2354:2354:2354) (2453:2453:2453)) + (PORT d[12] (3328:3328:3328) (3468:3468:3468)) + (PORT clk (1846:1846:1846) (1873:1873:1873)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2014:2014:2014) (1999:1999:1999)) + (PORT clk (1846:1846:1846) (1873:1873:1873)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1877:1877:1877)) + (PORT d[0] (5474:5474:5474) (5597:5597:5597)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1878:1878:1878)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1878:1878:1878)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1878:1878:1878)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1878:1878:1878)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1804:1804:1804) (1802:1802:1802)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2078:2078:2078) (2283:2283:2283)) + (PORT clk (1814:1814:1814) (1808:1808:1808)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4231:4231:4231) (4308:4308:4308)) + (PORT d[1] (4283:4283:4283) (4355:4355:4355)) + (PORT d[2] (4152:4152:4152) (4236:4236:4236)) + (PORT d[3] (4261:4261:4261) (4359:4359:4359)) + (PORT d[4] (4181:4181:4181) (4391:4391:4391)) + (PORT d[5] (4386:4386:4386) (4502:4502:4502)) + (PORT d[6] (4109:4109:4109) (4199:4199:4199)) + (PORT d[7] (4092:4092:4092) (4207:4207:4207)) + (PORT d[8] (4340:4340:4340) (4366:4366:4366)) + (PORT d[9] (4147:4147:4147) (4246:4246:4246)) + (PORT d[10] (4225:4225:4225) (4278:4278:4278)) + (PORT d[11] (4357:4357:4357) (4437:4437:4437)) + (PORT d[12] (4225:4225:4225) (4293:4293:4293)) + (PORT clk (1810:1810:1810) (1804:1804:1804)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1814:1814:1814) (1808:1808:1808)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1815:1815:1815) (1809:1809:1809)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1815:1815:1815) (1809:1809:1809)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1815:1815:1815) (1809:1809:1809)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1815:1815:1815) (1809:1809:1809)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1194:1194:1194) (1267:1267:1267)) + (PORT datab (678:678:678) (723:723:723)) + (PORT datac (1729:1729:1729) (1757:1757:1757)) + (PORT datad (1180:1180:1180) (1211:1211:1211)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2556:2556:2556) (2680:2680:2680)) + (PORT d[1] (3408:3408:3408) (3502:3502:3502)) + (PORT d[2] (2280:2280:2280) (2429:2429:2429)) + (PORT d[3] (2427:2427:2427) (2540:2540:2540)) + (PORT d[4] (2671:2671:2671) (2782:2782:2782)) + (PORT d[5] (2678:2678:2678) (2797:2797:2797)) + (PORT d[6] (3247:3247:3247) (3365:3365:3365)) + (PORT d[7] (2124:2124:2124) (2236:2236:2236)) + (PORT d[8] (2618:2618:2618) (2716:2716:2716)) + (PORT d[9] (3014:3014:3014) (3218:3218:3218)) + (PORT d[10] (3514:3514:3514) (3791:3791:3791)) + (PORT d[11] (2608:2608:2608) (2736:2736:2736)) + (PORT d[12] (2711:2711:2711) (2865:2865:2865)) + (PORT clk (1859:1859:1859) (1884:1884:1884)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1884:1884:1884)) + (PORT d[0] (4003:4003:4003) (3938:3938:3938)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1822:1822:1822) (1847:1847:1847)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1007:1007:1007) (1010:1010:1010)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1008:1008:1008) (1011:1011:1011)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1008:1008:1008) (1011:1011:1011)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1008:1008:1008) (1011:1011:1011)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1411:1411:1411) (1433:1433:1433)) + (PORT datab (1763:1763:1763) (1798:1798:1798)) + (PORT datac (173:173:173) (207:207:207)) + (PORT datad (1747:1747:1747) (1800:1800:1800)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (325:325:325)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~83) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (246:246:246)) + (PORT datab (3099:3099:3099) (3313:3313:3313)) + (PORT datac (1845:1845:1845) (2016:2016:2016)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~45) + (DELAY + (ABSOLUTE + (PORT dataa (1165:1165:1165) (1228:1228:1228)) + (PORT datab (1042:1042:1042) (1085:1085:1085)) + (PORT datac (179:179:179) (216:216:216)) + (PORT datad (1618:1618:1618) (1648:1648:1648)) + (IOPATH dataa combout (301:301:301) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (1666:1666:1666) (1706:1706:1706)) + (PORT datab (1658:1658:1658) (1692:1692:1692)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (1753:1753:1753) (1834:1834:1834)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[0\]) + (DELAY + (ABSOLUTE + (PORT dataa (1426:1426:1426) (1476:1476:1476)) + (PORT datab (2669:2669:2669) (2808:2808:2808)) + (PORT datac (339:339:339) (362:362:362)) + (PORT datad (371:371:371) (396:396:396)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1527:1527:1527) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[0\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (601:601:601) (664:664:664)) + (PORT datab (361:361:361) (398:398:398)) + (PORT datac (337:337:337) (369:369:369)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[0\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1418:1418:1418) (1451:1451:1451)) + (PORT datab (650:650:650) (674:674:674)) + (PORT datac (193:193:193) (226:226:226)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1566:1566:1566) (1548:1548:1548)) + (PORT ena (1698:1698:1698) (1714:1714:1714)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal3\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1711:1711:1711) (1845:1845:1845)) + (PORT datab (1089:1089:1089) (1155:1155:1155)) + (PORT datac (630:630:630) (652:652:652)) + (PORT datad (1105:1105:1105) (1133:1133:1133)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal43\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1304:1304:1304) (1384:1384:1384)) + (PORT datab (893:893:893) (927:927:927)) + (PORT datac (748:748:748) (850:850:850)) + (PORT datad (1074:1074:1074) (1094:1094:1094)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|test1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (826:826:826) (849:849:849)) + (PORT datab (197:197:197) (234:234:234)) + (PORT datac (184:184:184) (226:226:226)) + (PORT datad (195:195:195) (220:220:220)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|test1\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1107:1107:1107) (1206:1206:1206)) + (PORT datab (1070:1070:1070) (1116:1116:1116)) + (PORT datac (631:631:631) (696:696:696)) + (PORT datad (904:904:904) (922:922:922)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|interrupts_\|in_nmi_ALTERA_SYNTHESIZED) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1566:1566:1566) (1548:1548:1548)) + (PORT ena (959:959:959) (957:957:957)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|clk_delay_\|SYNTHESIZED_WIRE_4) + (DELAY + (ABSOLUTE + (PORT dataa (634:634:634) (704:704:704)) + (PORT datab (1457:1457:1457) (1571:1571:1571)) + (PORT datac (1217:1217:1217) (1298:1298:1298)) + (PORT datad (856:856:856) (904:904:904)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|clk_delay_\|SYNTHESIZED_WIRE_7) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1567:1567:1567) (1548:1548:1548)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|clk_delay_\|hold_clk_iorq) + (DELAY + (ABSOLUTE + (PORT dataa (1127:1127:1127) (1169:1169:1169)) + (PORT datab (1278:1278:1278) (1345:1345:1345)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_T4_ff) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1558:1558:1558) (1539:1539:1539)) + (PORT ena (1441:1441:1441) (1437:1437:1437)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_eval_cond\~0) + (DELAY + (ABSOLUTE + (PORT datac (1091:1091:1091) (1195:1195:1195)) + (PORT datad (1389:1389:1389) (1444:1444:1444)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~27) + (DELAY + (ABSOLUTE + (PORT dataa (1012:1012:1012) (1076:1076:1076)) + (PORT datab (1181:1181:1181) (1206:1206:1206)) + (PORT datac (627:627:627) (672:672:672)) + (PORT datad (623:623:623) (643:643:643)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~26) + (DELAY + (ABSOLUTE + (PORT datab (1127:1127:1127) (1212:1212:1212)) + (PORT datac (1880:1880:1880) (1963:1963:1963)) + (PORT datad (1816:1816:1816) (1920:1920:1920)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~28) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (244:244:244)) + (PORT datab (199:199:199) (237:237:237)) + (PORT datac (193:193:193) (225:225:225)) + (PORT datad (1435:1435:1435) (1502:1502:1502)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~6) + (DELAY + (ABSOLUTE + (PORT dataa (961:961:961) (1014:1014:1014)) + (PORT datab (678:678:678) (699:699:699)) + (PORT datac (202:202:202) (241:241:241)) + (PORT datad (1258:1258:1258) (1313:1313:1313)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~7) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (245:245:245)) + (PORT datab (924:924:924) (983:983:983)) + (PORT datac (1118:1118:1118) (1186:1186:1186)) + (PORT datad (1371:1371:1371) (1416:1416:1416)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~8) + (DELAY + (ABSOLUTE + (PORT dataa (871:871:871) (908:908:908)) + (PORT datab (1079:1079:1079) (1141:1141:1141)) + (PORT datac (914:914:914) (982:982:982)) + (PORT datad (671:671:671) (720:720:720)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~9) + (DELAY + (ABSOLUTE + (PORT dataa (918:918:918) (984:984:984)) + (PORT datab (1455:1455:1455) (1518:1518:1518)) + (PORT datac (1102:1102:1102) (1173:1173:1173)) + (PORT datad (874:874:874) (902:902:902)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~10) + (DELAY + (ABSOLUTE + (PORT dataa (646:646:646) (665:665:665)) + (PORT datab (1335:1335:1335) (1344:1344:1344)) + (PORT datac (589:589:589) (607:607:607)) + (PORT datad (2396:2396:2396) (2468:2468:2468)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~12) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (246:246:246)) + (PORT datab (207:207:207) (250:250:250)) + (PORT datac (542:542:542) (559:559:559)) + (PORT datad (648:648:648) (691:691:691)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~15) + (DELAY + (ABSOLUTE + (PORT dataa (661:661:661) (680:680:680)) + (PORT datab (1937:1937:1937) (2057:2057:2057)) + (PORT datac (1464:1464:1464) (1549:1549:1549)) + (PORT datad (341:341:341) (369:369:369)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~13) + (DELAY + (ABSOLUTE + (PORT dataa (375:375:375) (399:399:399)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~41) + (DELAY + (ABSOLUTE + (PORT datab (218:218:218) (256:256:256)) + (PORT datac (1086:1086:1086) (1106:1106:1106)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1308:1308:1308) (1393:1393:1393)) + (PORT datab (1212:1212:1212) (1329:1329:1329)) + (PORT datac (808:808:808) (824:824:824)) + (PORT datad (765:765:765) (807:807:807)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1233:1233:1233) (1321:1321:1321)) + (PORT datab (953:953:953) (1004:1004:1004)) + (PORT datac (834:834:834) (857:857:857)) + (PORT datad (588:588:588) (600:600:600)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|ena_M) + (DELAY + (ABSOLUTE + (PORT datab (1159:1159:1159) (1227:1227:1227)) + (PORT datad (894:894:894) (970:970:970)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_T1_ff) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1558:1558:1558) (1539:1539:1539)) + (PORT ena (1441:1441:1441) (1437:1437:1437)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_13) + (DELAY + (ABSOLUTE + (PORT datab (273:273:273) (358:358:358)) + (PORT datac (1558:1558:1558) (1647:1647:1647)) + (PORT datad (895:895:895) (976:976:976)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_T2_ff) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1558:1558:1558) (1539:1539:1539)) + (PORT ena (1441:1441:1441) (1437:1437:1437)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_14) + (DELAY + (ABSOLUTE + (PORT datab (274:274:274) (360:360:360)) + (PORT datac (1559:1559:1559) (1647:1647:1647)) + (PORT datad (896:896:896) (976:976:976)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_T3_ff) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1558:1558:1558) (1539:1539:1539)) + (PORT ena (1441:1441:1441) (1437:1437:1437)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_1M1T3_3) + (DELAY + (ABSOLUTE + (PORT datac (1216:1216:1216) (1297:1297:1297)) + (PORT datad (1623:1623:1623) (1694:1694:1694)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_66_oe\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1427:1427:1427) (1437:1437:1437)) + (PORT datab (664:664:664) (695:695:695)) + (PORT datac (1306:1306:1306) (1375:1375:1375)) + (PORT datad (1666:1666:1666) (1801:1801:1801)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|interrupts_\|im1) + (DELAY + (ABSOLUTE + (PORT clk (1541:1541:1541) (1557:1557:1557)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1567:1567:1567) (1549:1549:1549)) + (PORT ena (1482:1482:1482) (1498:1498:1498)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_ff_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (295:295:295) (389:389:389)) + (PORT datab (882:882:882) (979:979:979)) + (PORT datac (826:826:826) (910:910:910)) + (PORT datad (1121:1121:1121) (1163:1163:1163)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_ff_oe\~1) + (DELAY + (ABSOLUTE + (PORT dataa (648:648:648) (695:695:695)) + (PORT datab (1160:1160:1160) (1205:1205:1205)) + (PORT datac (463:463:463) (541:541:541)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_zero_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1557:1557:1557) (1574:1574:1574)) + (PORT datab (1249:1249:1249) (1315:1315:1315)) + (PORT datac (1415:1415:1415) (1497:1497:1497)) + (PORT datad (905:905:905) (896:896:896)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (256:256:256)) + (PORT datab (205:205:205) (248:248:248)) + (PORT datac (1372:1372:1372) (1416:1416:1416)) + (PORT datad (698:698:698) (786:786:786)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[6\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (558:558:558) (586:586:586)) + (PORT datac (1329:1329:1329) (1349:1349:1349)) + (PORT datad (593:593:593) (603:603:603)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (945:945:945) (970:970:970)) + (PORT clk (1843:1843:1843) (1871:1871:1871)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1480:1480:1480) (1540:1540:1540)) + (PORT d[1] (1855:1855:1855) (1932:1932:1932)) + (PORT d[2] (2198:2198:2198) (2365:2365:2365)) + (PORT d[3] (1860:1860:1860) (1959:1959:1959)) + (PORT d[4] (2303:2303:2303) (2359:2359:2359)) + (PORT d[5] (1442:1442:1442) (1514:1514:1514)) + (PORT d[6] (1422:1422:1422) (1484:1484:1484)) + (PORT d[7] (1524:1524:1524) (1633:1633:1633)) + (PORT d[8] (2464:2464:2464) (2618:2618:2618)) + (PORT d[9] (3448:3448:3448) (3679:3679:3679)) + (PORT d[10] (1283:1283:1283) (1336:1336:1336)) + (PORT d[11] (1663:1663:1663) (1697:1697:1697)) + (PORT d[12] (2373:2373:2373) (2438:2438:2438)) + (PORT clk (1840:1840:1840) (1867:1867:1867)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1496:1496:1496) (1448:1448:1448)) + (PORT clk (1840:1840:1840) (1867:1867:1867)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1871:1871:1871)) + (PORT d[0] (1761:1761:1761) (1748:1748:1748)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1872:1872:1872)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1872:1872:1872)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1872:1872:1872)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1872:1872:1872)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1803:1803:1803) (1830:1830:1830)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (988:988:988) (993:993:993)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (989:989:989) (994:994:994)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (989:989:989) (994:994:994)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (989:989:989) (994:994:994)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1028:1028:1028) (1050:1050:1050)) + (PORT clk (1841:1841:1841) (1869:1869:1869)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1207:1207:1207) (1267:1267:1267)) + (PORT d[1] (1839:1839:1839) (1930:1930:1930)) + (PORT d[2] (1987:1987:1987) (2149:2149:2149)) + (PORT d[3] (1847:1847:1847) (1958:1958:1958)) + (PORT d[4] (2349:2349:2349) (2423:2423:2423)) + (PORT d[5] (1411:1411:1411) (1468:1468:1468)) + (PORT d[6] (1418:1418:1418) (1478:1478:1478)) + (PORT d[7] (1552:1552:1552) (1669:1669:1669)) + (PORT d[8] (2535:2535:2535) (2674:2674:2674)) + (PORT d[9] (3468:3468:3468) (3682:3682:3682)) + (PORT d[10] (1582:1582:1582) (1673:1673:1673)) + (PORT d[11] (1374:1374:1374) (1405:1405:1405)) + (PORT d[12] (2405:2405:2405) (2480:2480:2480)) + (PORT clk (1838:1838:1838) (1865:1865:1865)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1442:1442:1442) (1439:1439:1439)) + (PORT clk (1838:1838:1838) (1865:1865:1865)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1869:1869:1869)) + (PORT d[0] (1771:1771:1771) (1732:1732:1732)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1870:1870:1870)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1870:1870:1870)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1870:1870:1870)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1870:1870:1870)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1801:1801:1801) (1828:1828:1828)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (986:986:986) (991:991:991)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (987:987:987) (992:992:992)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (987:987:987) (992:992:992)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (987:987:987) (992:992:992)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (936:936:936) (957:957:957)) + (PORT clk (1847:1847:1847) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1190:1190:1190) (1232:1232:1232)) + (PORT d[1] (1836:1836:1836) (1942:1942:1942)) + (PORT d[2] (3210:3210:3210) (3443:3443:3443)) + (PORT d[3] (1559:1559:1559) (1636:1636:1636)) + (PORT d[4] (1981:1981:1981) (2055:2055:2055)) + (PORT d[5] (1388:1388:1388) (1453:1453:1453)) + (PORT d[6] (1715:1715:1715) (1779:1779:1779)) + (PORT d[7] (1251:1251:1251) (1325:1325:1325)) + (PORT d[8] (2576:2576:2576) (2738:2738:2738)) + (PORT d[9] (3161:3161:3161) (3375:3375:3375)) + (PORT d[10] (1305:1305:1305) (1378:1378:1378)) + (PORT d[11] (1689:1689:1689) (1717:1717:1717)) + (PORT d[12] (2675:2675:2675) (2763:2763:2763)) + (PORT clk (1844:1844:1844) (1871:1871:1871)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2082:2082:2082) (2053:2053:2053)) + (PORT clk (1844:1844:1844) (1871:1871:1871)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1847:1847:1847) (1875:1875:1875)) + (PORT d[0] (1957:1957:1957) (1912:1912:1912)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1807:1807:1807) (1834:1834:1834)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (992:992:992) (997:997:997)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (993:993:993) (998:998:998)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (993:993:993) (998:998:998)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (993:993:993) (998:998:998)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (702:702:702) (726:726:726)) + (PORT clk (1845:1845:1845) (1873:1873:1873)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1179:1179:1179) (1220:1220:1220)) + (PORT d[1] (2152:2152:2152) (2255:2255:2255)) + (PORT d[2] (2004:2004:2004) (2150:2150:2150)) + (PORT d[3] (1895:1895:1895) (2014:2014:2014)) + (PORT d[4] (1748:1748:1748) (1828:1828:1828)) + (PORT d[5] (1380:1380:1380) (1431:1431:1431)) + (PORT d[6] (1141:1141:1141) (1173:1173:1173)) + (PORT d[7] (1238:1238:1238) (1309:1309:1309)) + (PORT d[8] (2575:2575:2575) (2737:2737:2737)) + (PORT d[9] (3135:3135:3135) (3345:3345:3345)) + (PORT d[10] (1292:1292:1292) (1363:1363:1363)) + (PORT d[11] (1657:1657:1657) (1703:1703:1703)) + (PORT d[12] (1147:1147:1147) (1187:1187:1187)) + (PORT clk (1842:1842:1842) (1869:1869:1869)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2557:2557:2557) (2590:2590:2590)) + (PORT clk (1842:1842:1842) (1869:1869:1869)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1873:1873:1873)) + (PORT d[0] (1461:1461:1461) (1431:1431:1431)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1874:1874:1874)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1874:1874:1874)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1874:1874:1874)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1874:1874:1874)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1805:1805:1805) (1832:1832:1832)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (990:990:990) (995:995:995)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (991:991:991) (996:996:996)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (991:991:991) (996:996:996)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (991:991:991) (996:996:996)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[6\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (909:909:909) (934:934:934)) + (PORT datab (674:674:674) (688:688:688)) + (PORT datac (1144:1144:1144) (1212:1212:1212)) + (PORT datad (1290:1290:1290) (1419:1419:1419)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[6\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1218:1218:1218) (1246:1246:1246)) + (PORT datab (1255:1255:1255) (1282:1282:1282)) + (PORT datac (313:313:313) (332:332:332)) + (PORT datad (1956:1956:1956) (2083:2083:2083)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1807:1807:1807) (1893:1893:1893)) + (PORT d[1] (2094:2094:2094) (2205:2205:2205)) + (PORT d[2] (2125:2125:2125) (2264:2264:2264)) + (PORT d[3] (1876:1876:1876) (1969:1969:1969)) + (PORT d[4] (2315:2315:2315) (2392:2392:2392)) + (PORT d[5] (1694:1694:1694) (1783:1783:1783)) + (PORT d[6] (1925:1925:1925) (1996:1996:1996)) + (PORT d[7] (1486:1486:1486) (1574:1574:1574)) + (PORT d[8] (2216:2216:2216) (2334:2334:2334)) + (PORT d[9] (3286:3286:3286) (3488:3488:3488)) + (PORT d[10] (1591:1591:1591) (1690:1690:1690)) + (PORT d[11] (1981:1981:1981) (2051:2051:2051)) + (PORT d[12] (1772:1772:1772) (1798:1798:1798)) + (PORT clk (1848:1848:1848) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1875:1875:1875)) + (PORT d[0] (2644:2644:2644) (2591:2591:2591)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1811:1811:1811) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1489:1489:1489) (1574:1574:1574)) + (PORT d[1] (2573:2573:2573) (2667:2667:2667)) + (PORT d[2] (2212:2212:2212) (2353:2353:2353)) + (PORT d[3] (1869:1869:1869) (1982:1982:1982)) + (PORT d[4] (2315:2315:2315) (2365:2365:2365)) + (PORT d[5] (1709:1709:1709) (1786:1786:1786)) + (PORT d[6] (1728:1728:1728) (1808:1808:1808)) + (PORT d[7] (1522:1522:1522) (1615:1615:1615)) + (PORT d[8] (2225:2225:2225) (2361:2361:2361)) + (PORT d[9] (3531:3531:3531) (3742:3742:3742)) + (PORT d[10] (1351:1351:1351) (1439:1439:1439)) + (PORT d[11] (1655:1655:1655) (1706:1706:1706)) + (PORT d[12] (2100:2100:2100) (2152:2152:2152)) + (PORT clk (1846:1846:1846) (1872:1872:1872)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1872:1872:1872)) + (PORT d[0] (1291:1291:1291) (1265:1265:1265)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1847:1847:1847) (1873:1873:1873)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1809:1809:1809) (1835:1835:1835)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (994:994:994) (998:998:998)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (999:999:999)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (999:999:999)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (999:999:999)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1321:1321:1321) (1383:1383:1383)) + (PORT clk (1846:1846:1846) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3132:3132:3132) (3372:3372:3372)) + (PORT d[1] (4267:4267:4267) (4444:4444:4444)) + (PORT d[2] (2301:2301:2301) (2470:2470:2470)) + (PORT d[3] (2187:2187:2187) (2289:2289:2289)) + (PORT d[4] (3508:3508:3508) (3634:3634:3634)) + (PORT d[5] (2380:2380:2380) (2498:2498:2498)) + (PORT d[6] (4072:4072:4072) (4206:4206:4206)) + (PORT d[7] (3046:3046:3046) (3200:3200:3200)) + (PORT d[8] (2176:2176:2176) (2293:2293:2293)) + (PORT d[9] (2772:2772:2772) (2847:2847:2847)) + (PORT d[10] (2937:2937:2937) (3127:3127:3127)) + (PORT d[11] (3179:3179:3179) (3339:3339:3339)) + (PORT d[12] (3050:3050:3050) (3184:3184:3184)) + (PORT clk (1843:1843:1843) (1871:1871:1871)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2312:2312:2312) (2312:2312:2312)) + (PORT clk (1843:1843:1843) (1871:1871:1871)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1875:1875:1875)) + (PORT d[0] (5462:5462:5462) (5569:5569:5569)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1847:1847:1847) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1847:1847:1847) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1847:1847:1847) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1847:1847:1847) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1801:1801:1801) (1800:1800:1800)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2093:2093:2093) (2293:2293:2293)) + (PORT clk (1811:1811:1811) (1806:1806:1806)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4214:4214:4214) (4279:4279:4279)) + (PORT d[1] (4301:4301:4301) (4372:4372:4372)) + (PORT d[2] (4125:4125:4125) (4227:4227:4227)) + (PORT d[3] (4288:4288:4288) (4412:4412:4412)) + (PORT d[4] (4100:4100:4100) (4252:4252:4252)) + (PORT d[5] (4335:4335:4335) (4468:4468:4468)) + (PORT d[6] (4130:4130:4130) (4197:4197:4197)) + (PORT d[7] (4081:4081:4081) (4200:4200:4200)) + (PORT d[8] (4230:4230:4230) (4286:4286:4286)) + (PORT d[9] (4102:4102:4102) (4208:4208:4208)) + (PORT d[10] (4243:4243:4243) (4291:4291:4291)) + (PORT d[11] (4340:4340:4340) (4429:4429:4429)) + (PORT d[12] (4159:4159:4159) (4233:4233:4233)) + (PORT clk (1807:1807:1807) (1802:1802:1802)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1811:1811:1811) (1806:1806:1806)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1807:1807:1807)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1807:1807:1807)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1807:1807:1807)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1807:1807:1807)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1313:1313:1313) (1378:1378:1378)) + (PORT clk (1852:1852:1852) (1880:1880:1880)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2797:2797:2797) (2917:2917:2917)) + (PORT d[1] (3674:3674:3674) (3821:3821:3821)) + (PORT d[2] (2586:2586:2586) (2781:2781:2781)) + (PORT d[3] (1912:1912:1912) (2028:2028:2028)) + (PORT d[4] (3515:3515:3515) (3623:3623:3623)) + (PORT d[5] (2661:2661:2661) (2772:2772:2772)) + (PORT d[6] (4062:4062:4062) (4173:4173:4173)) + (PORT d[7] (2712:2712:2712) (2860:2860:2860)) + (PORT d[8] (2947:2947:2947) (3041:3041:3041)) + (PORT d[9] (2758:2758:2758) (2945:2945:2945)) + (PORT d[10] (3655:3655:3655) (3891:3891:3891)) + (PORT d[11] (2910:2910:2910) (3054:3054:3054)) + (PORT d[12] (2719:2719:2719) (2843:2843:2843)) + (PORT clk (1849:1849:1849) (1876:1876:1876)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2834:2834:2834) (2931:2931:2931)) + (PORT clk (1849:1849:1849) (1876:1876:1876)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (PORT d[0] (5279:5279:5279) (5172:5172:5172)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1881:1881:1881)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1881:1881:1881)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1881:1881:1881)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1881:1881:1881)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1807:1807:1807) (1805:1805:1805)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1326:1326:1326) (1367:1367:1367)) + (PORT clk (1817:1817:1817) (1811:1811:1811)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4380:4380:4380) (4430:4430:4430)) + (PORT d[1] (4245:4245:4245) (4297:4297:4297)) + (PORT d[2] (4163:4163:4163) (4287:4287:4287)) + (PORT d[3] (4271:4271:4271) (4359:4359:4359)) + (PORT d[4] (4118:4118:4118) (4243:4243:4243)) + (PORT d[5] (4331:4331:4331) (4458:4458:4458)) + (PORT d[6] (4092:4092:4092) (4140:4140:4140)) + (PORT d[7] (4012:4012:4012) (4135:4135:4135)) + (PORT d[8] (4274:4274:4274) (4402:4402:4402)) + (PORT d[9] (4040:4040:4040) (4147:4147:4147)) + (PORT d[10] (4259:4259:4259) (4327:4327:4327)) + (PORT d[11] (4179:4179:4179) (4202:4202:4202)) + (PORT d[12] (4212:4212:4212) (4286:4286:4286)) + (PORT clk (1813:1813:1813) (1807:1807:1807)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1817:1817:1817) (1811:1811:1811)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1818:1818:1818) (1812:1812:1812)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1818:1818:1818) (1812:1812:1812)) + (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1818:1818:1818) (1812:1812:1812)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1818:1818:1818) (1812:1812:1812)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1809:1809:1809) (1807:1807:1807)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1626:1626:1626) (1682:1682:1682)) + (PORT datab (1084:1084:1084) (1109:1109:1109)) + (PORT datac (1464:1464:1464) (1492:1492:1492)) + (PORT datad (1498:1498:1498) (1563:1563:1563)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector6\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1293:1293:1293) (1371:1371:1371)) + (PORT datab (393:393:393) (418:418:418)) + (PORT datac (1538:1538:1538) (1525:1525:1525)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~88) + (DELAY + (ABSOLUTE + (PORT dataa (1598:1598:1598) (1753:1753:1753)) + (PORT datab (3082:3082:3082) (3273:3273:3273)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE raw_loader_in\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (479:479:479) (732:732:732)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~69) + (DELAY + (ABSOLUTE + (PORT datab (3078:3078:3078) (3271:3271:3271)) + (PORT datac (1351:1351:1351) (1416:1416:1416)) + (PORT datad (1578:1578:1578) (1622:1622:1622)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~78) + (DELAY + (ABSOLUTE + (PORT dataa (1148:1148:1148) (1172:1172:1172)) + (PORT datab (1123:1123:1123) (1163:1163:1163)) + (PORT datac (178:178:178) (214:214:214)) + (PORT datad (182:182:182) (211:211:211)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~79) + (DELAY + (ABSOLUTE + (PORT dataa (1330:1330:1330) (1422:1422:1422)) + (PORT datab (1122:1122:1122) (1164:1164:1164)) + (PORT datac (1105:1105:1105) (1155:1155:1155)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[6\]) + (DELAY + (ABSOLUTE + (PORT dataa (1426:1426:1426) (1479:1479:1479)) + (PORT datab (400:400:400) (440:440:440)) + (PORT datac (1276:1276:1276) (1302:1302:1302)) + (PORT datad (195:195:195) (221:221:221)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1527:1527:1527) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[6\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (398:398:398) (440:440:440)) + (PORT datab (377:377:377) (400:400:400)) + (PORT datac (363:363:363) (430:430:430)) + (PORT datad (579:579:579) (606:606:606)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1566:1566:1566) (1548:1548:1548)) + (PORT ena (1684:1684:1684) (1669:1669:1669)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1019:1019:1019) (1143:1143:1143)) + (PORT datab (1044:1044:1044) (1189:1189:1189)) + (PORT datac (694:694:694) (760:760:760)) + (PORT datad (1149:1149:1149) (1174:1174:1174)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (935:935:935) (1005:1005:1005)) + (PORT datab (964:964:964) (1009:1009:1009)) + (PORT datac (186:186:186) (228:228:228)) + (PORT datad (1645:1645:1645) (1710:1710:1710)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~4) + (DELAY + (ABSOLUTE + (PORT datac (1432:1432:1432) (1541:1541:1541)) + (PORT datad (1343:1343:1343) (1341:1341:1341)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~2) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (255:255:255)) + (PORT datab (207:207:207) (249:249:249)) + (PORT datac (1372:1372:1372) (1418:1418:1418)) + (PORT datad (700:700:700) (789:789:789)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~5) + (DELAY + (ABSOLUTE + (PORT dataa (421:421:421) (482:482:482)) + (PORT datab (609:609:609) (624:624:624)) + (PORT datac (594:594:594) (626:626:626)) + (PORT datad (603:603:603) (630:630:630)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~6) + (DELAY + (ABSOLUTE + (PORT dataa (976:976:976) (1045:1045:1045)) + (PORT datab (196:196:196) (234:234:234)) + (PORT datac (1955:1955:1955) (2058:2058:2058)) + (PORT datad (1784:1784:1784) (1837:1837:1837)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (342:342:342) (377:377:377)) + (PORT datac (1519:1519:1519) (1510:1510:1510)) + (PORT datad (850:850:850) (879:879:879)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (367:367:367) (406:406:406)) + (PORT datac (1375:1375:1375) (1409:1409:1409)) + (PORT datad (334:334:334) (355:355:355)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~61) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (256:256:256)) + (PORT datab (988:988:988) (1051:1051:1051)) + (PORT datac (1200:1200:1200) (1278:1278:1278)) + (PORT datad (937:937:937) (977:977:977)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~63) + (DELAY + (ABSOLUTE + (PORT dataa (410:410:410) (489:489:489)) + (PORT datab (199:199:199) (239:239:239)) + (PORT datac (859:859:859) (882:882:882)) + (PORT datad (202:202:202) (230:230:230)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~64) + (DELAY + (ABSOLUTE + (PORT dataa (871:871:871) (901:901:901)) + (PORT datab (773:773:773) (837:837:837)) + (PORT datac (320:320:320) (339:339:339)) + (PORT datad (1004:1004:1004) (1090:1090:1090)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~65) + (DELAY + (ABSOLUTE + (PORT dataa (351:351:351) (381:381:381)) + (PORT datad (174:174:174) (201:201:201)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1557:1557:1557) (1549:1549:1549)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~67) + (DELAY + (ABSOLUTE + (PORT dataa (1059:1059:1059) (1136:1136:1136)) + (PORT datab (687:687:687) (747:747:747)) + (PORT datad (962:962:962) (1025:1025:1025)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~68) + (DELAY + (ABSOLUTE + (PORT dataa (990:990:990) (1072:1072:1072)) + (PORT datab (1214:1214:1214) (1285:1285:1285)) + (PORT datac (261:261:261) (347:347:347)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~69) + (DELAY + (ABSOLUTE + (PORT dataa (670:670:670) (705:705:705)) + (PORT datab (230:230:230) (273:273:273)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1555:1555:1555) (1547:1547:1547)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (653:653:653) (715:715:715)) + (PORT datab (385:385:385) (451:451:451)) + (PORT datac (1078:1078:1078) (1083:1083:1083)) + (PORT datad (624:624:624) (661:661:661)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~58) + (DELAY + (ABSOLUTE + (PORT dataa (787:787:787) (866:866:866)) + (PORT datab (448:448:448) (525:525:525)) + (PORT datac (1184:1184:1184) (1259:1259:1259)) + (PORT datad (648:648:648) (704:704:704)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~130) + (DELAY + (ABSOLUTE + (PORT dataa (991:991:991) (1074:1074:1074)) + (PORT datab (559:559:559) (576:576:576)) + (PORT datac (261:261:261) (348:348:348)) + (PORT datad (1017:1017:1017) (1092:1092:1092)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~59) + (DELAY + (ABSOLUTE + (PORT dataa (634:634:634) (710:710:710)) + (PORT datab (344:344:344) (373:373:373)) + (PORT datad (499:499:499) (510:510:510)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1555:1555:1555) (1547:1547:1547)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~56) + (DELAY + (ABSOLUTE + (PORT datac (666:666:666) (727:727:727)) + (PORT datad (689:689:689) (759:759:759)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~57) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (246:246:246)) + (PORT datab (943:943:943) (1018:1018:1018)) + (PORT datad (325:325:325) (344:344:344)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1533:1533:1533)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1559:1559:1559) (1552:1552:1552)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (2099:2099:2099) (2130:2130:2130)) + (PORT datab (419:419:419) (486:486:486)) + (PORT datac (867:867:867) (901:901:901)) + (PORT datad (675:675:675) (729:729:729)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]\~54) + (DELAY + (ABSOLUTE + (PORT datac (1091:1091:1091) (1182:1182:1182)) + (PORT datad (1208:1208:1208) (1271:1271:1271)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]\~55) + (DELAY + (ABSOLUTE + (PORT dataa (783:783:783) (871:871:871)) + (PORT datab (366:366:366) (403:403:403)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1558:1558:1558) (1550:1550:1550)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]\~50) + (DELAY + (ABSOLUTE + (PORT datac (1093:1093:1093) (1185:1185:1185)) + (PORT datad (1208:1208:1208) (1267:1267:1267)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (210:210:210) (257:257:257)) + (PORT datab (366:366:366) (403:403:403)) + (PORT datad (737:737:737) (821:821:821)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1558:1558:1558) (1550:1550:1550)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]\~52) + (DELAY + (ABSOLUTE + (PORT dataa (902:902:902) (935:935:935)) + (PORT datab (645:645:645) (669:669:669)) + (PORT datac (182:182:182) (220:220:220)) + (PORT datad (1923:1923:1923) (2012:2012:2012)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]\~53) + (DELAY + (ABSOLUTE + (PORT dataa (785:785:785) (866:866:866)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1558:1558:1558) (1550:1550:1550)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (383:383:383) (453:453:453)) + (PORT datab (415:415:415) (474:474:474)) + (PORT datac (1051:1051:1051) (1055:1055:1055)) + (PORT datad (843:843:843) (857:857:857)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[2\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (367:367:367) (405:405:405)) + (PORT datab (886:886:886) (906:906:906)) + (PORT datac (1093:1093:1093) (1184:1184:1184)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[2\]\~48) + (DELAY + (ABSOLUTE + (PORT datab (199:199:199) (238:238:238)) + (PORT datad (732:732:732) (816:816:816)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1558:1558:1558) (1550:1550:1550)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\~1) + (DELAY + (ABSOLUTE + (PORT datab (1126:1126:1126) (1194:1194:1194)) + (PORT datac (2686:2686:2686) (2847:2847:2847)) + (PORT datad (218:218:218) (287:287:287)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (2330:2330:2330) (2493:2493:2493)) + (PORT datab (241:241:241) (323:323:323)) + (PORT datac (343:343:343) (366:366:366)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (365:365:365) (387:387:387)) + (PORT datac (759:759:759) (766:766:766)) + (PORT datad (859:859:859) (894:894:894)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (978:978:978) (1013:1013:1013)) + (PORT clk (1845:1845:1845) (1873:1873:1873)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1539:1539:1539) (1622:1622:1622)) + (PORT d[1] (2607:2607:2607) (2688:2688:2688)) + (PORT d[2] (2171:2171:2171) (2319:2319:2319)) + (PORT d[3] (1846:1846:1846) (1952:1952:1952)) + (PORT d[4] (2317:2317:2317) (2374:2374:2374)) + (PORT d[5] (1398:1398:1398) (1468:1468:1468)) + (PORT d[6] (1423:1423:1423) (1485:1485:1485)) + (PORT d[7] (1543:1543:1543) (1643:1643:1643)) + (PORT d[8] (2272:2272:2272) (2402:2402:2402)) + (PORT d[9] (3351:3351:3351) (3559:3559:3559)) + (PORT d[10] (1322:1322:1322) (1383:1383:1383)) + (PORT d[11] (1649:1649:1649) (1694:1694:1694)) + (PORT d[12] (2365:2365:2365) (2417:2417:2417)) + (PORT clk (1842:1842:1842) (1869:1869:1869)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1809:1809:1809) (1763:1763:1763)) + (PORT clk (1842:1842:1842) (1869:1869:1869)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1873:1873:1873)) + (PORT d[0] (1979:1979:1979) (1957:1957:1957)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1874:1874:1874)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1874:1874:1874)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1874:1874:1874)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1874:1874:1874)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1805:1805:1805) (1832:1832:1832)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (990:990:990) (995:995:995)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (991:991:991) (996:996:996)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (991:991:991) (996:996:996)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (991:991:991) (996:996:996)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (695:695:695) (718:718:718)) + (PORT clk (1843:1843:1843) (1871:1871:1871)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1232:1232:1232) (1287:1287:1287)) + (PORT d[1] (1839:1839:1839) (1928:1928:1928)) + (PORT d[2] (2152:2152:2152) (2302:2302:2302)) + (PORT d[3] (1872:1872:1872) (1989:1989:1989)) + (PORT d[4] (2048:2048:2048) (2133:2133:2133)) + (PORT d[5] (1091:1091:1091) (1114:1114:1114)) + (PORT d[6] (1409:1409:1409) (1454:1454:1454)) + (PORT d[7] (1530:1530:1530) (1645:1645:1645)) + (PORT d[8] (2543:2543:2543) (2695:2695:2695)) + (PORT d[9] (3411:3411:3411) (3618:3618:3618)) + (PORT d[10] (1316:1316:1316) (1396:1396:1396)) + (PORT d[11] (1672:1672:1672) (1707:1707:1707)) + (PORT d[12] (2406:2406:2406) (2481:2481:2481)) + (PORT clk (1840:1840:1840) (1867:1867:1867)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2592:2592:2592) (2628:2628:2628)) + (PORT clk (1840:1840:1840) (1867:1867:1867)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1871:1871:1871)) + (PORT d[0] (1732:1732:1732) (1708:1708:1708)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1872:1872:1872)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1872:1872:1872)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1872:1872:1872)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1872:1872:1872)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1803:1803:1803) (1830:1830:1830)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (988:988:988) (993:993:993)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (989:989:989) (994:994:994)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (989:989:989) (994:994:994)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (989:989:989) (994:994:994)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (962:962:962) (972:972:972)) + (PORT clk (1849:1849:1849) (1876:1876:1876)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1430:1430:1430) (1475:1475:1475)) + (PORT d[1] (1863:1863:1863) (1974:1974:1974)) + (PORT d[2] (1874:1874:1874) (2006:2006:2006)) + (PORT d[3] (1548:1548:1548) (1613:1613:1613)) + (PORT d[4] (1720:1720:1720) (1791:1791:1791)) + (PORT d[5] (1419:1419:1419) (1494:1494:1494)) + (PORT d[6] (1725:1725:1725) (1771:1771:1771)) + (PORT d[7] (1852:1852:1852) (1991:1991:1991)) + (PORT d[8] (3082:3082:3082) (3241:3241:3241)) + (PORT d[9] (3171:3171:3171) (3406:3406:3406)) + (PORT d[10] (1563:1563:1563) (1656:1656:1656)) + (PORT d[11] (2265:2265:2265) (2388:2388:2388)) + (PORT d[12] (2708:2708:2708) (2807:2807:2807)) + (PORT clk (1846:1846:1846) (1872:1872:1872)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1810:1810:1810) (1782:1782:1782)) + (PORT clk (1846:1846:1846) (1872:1872:1872)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1876:1876:1876)) + (PORT d[0] (2235:2235:2235) (2184:2184:2184)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1809:1809:1809) (1835:1835:1835)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (994:994:994) (998:998:998)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (999:999:999)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (999:999:999)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (999:999:999)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[2\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (980:980:980) (1052:1052:1052)) + (PORT datab (910:910:910) (970:970:970)) + (PORT datac (864:864:864) (861:861:861)) + (PORT datad (915:915:915) (931:931:931)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (979:979:979) (1014:1014:1014)) + (PORT clk (1847:1847:1847) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1495:1495:1495) (1550:1550:1550)) + (PORT d[1] (2584:2584:2584) (2663:2663:2663)) + (PORT d[2] (2005:2005:2005) (2167:2167:2167)) + (PORT d[3] (1860:1860:1860) (1959:1959:1959)) + (PORT d[4] (2033:2033:2033) (2096:2096:2096)) + (PORT d[5] (1398:1398:1398) (1469:1469:1469)) + (PORT d[6] (1719:1719:1719) (1785:1785:1785)) + (PORT d[7] (1509:1509:1509) (1601:1601:1601)) + (PORT d[8] (2234:2234:2234) (2387:2387:2387)) + (PORT d[9] (3351:3351:3351) (3558:3558:3558)) + (PORT d[10] (1332:1332:1332) (1407:1407:1407)) + (PORT d[11] (1681:1681:1681) (1737:1737:1737)) + (PORT d[12] (2101:2101:2101) (2153:2153:2153)) + (PORT clk (1844:1844:1844) (1871:1871:1871)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1701:1701:1701) (1711:1711:1711)) + (PORT clk (1844:1844:1844) (1871:1871:1871)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1847:1847:1847) (1875:1875:1875)) + (PORT d[0] (1789:1789:1789) (1743:1743:1743)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1807:1807:1807) (1834:1834:1834)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (992:992:992) (997:997:997)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (993:993:993) (998:998:998)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (993:993:993) (998:998:998)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (993:993:993) (998:998:998)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[2\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (991:991:991) (1002:1002:1002)) + (PORT datab (1317:1317:1317) (1455:1455:1455)) + (PORT datac (173:173:173) (206:206:206)) + (PORT datad (1201:1201:1201) (1246:1246:1246)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1788:1788:1788) (1877:1877:1877)) + (PORT d[1] (2361:2361:2361) (2459:2459:2459)) + (PORT d[2] (1956:1956:1956) (2114:2114:2114)) + (PORT d[3] (1873:1873:1873) (1989:1989:1989)) + (PORT d[4] (2307:2307:2307) (2357:2357:2357)) + (PORT d[5] (1690:1690:1690) (1776:1776:1776)) + (PORT d[6] (1732:1732:1732) (1816:1816:1816)) + (PORT d[7] (1555:1555:1555) (1649:1649:1649)) + (PORT d[8] (2191:2191:2191) (2347:2347:2347)) + (PORT d[9] (3356:3356:3356) (3572:3572:3572)) + (PORT d[10] (1583:1583:1583) (1661:1661:1661)) + (PORT d[11] (1970:1970:1970) (2025:2025:2025)) + (PORT d[12] (2068:2068:2068) (2110:2110:2110)) + (PORT clk (1847:1847:1847) (1874:1874:1874)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1847:1847:1847) (1874:1874:1874)) + (PORT d[0] (1275:1275:1275) (1274:1274:1274)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1875:1875:1875)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1810:1810:1810) (1837:1837:1837)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (1000:1000:1000)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2278:2278:2278) (2409:2409:2409)) + (PORT d[1] (3439:3439:3439) (3559:3559:3559)) + (PORT d[2] (2283:2283:2283) (2459:2459:2459)) + (PORT d[3] (2427:2427:2427) (2545:2545:2545)) + (PORT d[4] (2662:2662:2662) (2786:2786:2786)) + (PORT d[5] (2725:2725:2725) (2847:2847:2847)) + (PORT d[6] (3253:3253:3253) (3377:3377:3377)) + (PORT d[7] (2389:2389:2389) (2532:2532:2532)) + (PORT d[8] (2637:2637:2637) (2732:2732:2732)) + (PORT d[9] (2733:2733:2733) (2939:2939:2939)) + (PORT d[10] (3679:3679:3679) (3942:3942:3942)) + (PORT d[11] (2598:2598:2598) (2740:2740:2740)) + (PORT d[12] (2405:2405:2405) (2534:2534:2534)) + (PORT clk (1857:1857:1857) (1882:1882:1882)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1882:1882:1882)) + (PORT d[0] (4039:4039:4039) (3953:3953:3953)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1883:1883:1883)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1845:1845:1845)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1008:1008:1008)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1009:1009:1009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1009:1009:1009)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1009:1009:1009)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1546:1546:1546) (1629:1629:1629)) + (PORT clk (1849:1849:1849) (1877:1877:1877)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2782:2782:2782) (3017:3017:3017)) + (PORT d[1] (3696:3696:3696) (3846:3846:3846)) + (PORT d[2] (2300:2300:2300) (2462:2462:2462)) + (PORT d[3] (1908:1908:1908) (2025:2025:2025)) + (PORT d[4] (3502:3502:3502) (3621:3621:3621)) + (PORT d[5] (2770:2770:2770) (2893:2893:2893)) + (PORT d[6] (2979:2979:2979) (3093:3093:3093)) + (PORT d[7] (2708:2708:2708) (2854:2854:2854)) + (PORT d[8] (2190:2190:2190) (2293:2293:2293)) + (PORT d[9] (2908:2908:2908) (3077:3077:3077)) + (PORT d[10] (3379:3379:3379) (3620:3620:3620)) + (PORT d[11] (2309:2309:2309) (2408:2408:2408)) + (PORT d[12] (3006:3006:3006) (3139:3139:3139)) + (PORT clk (1846:1846:1846) (1873:1873:1873)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2327:2327:2327) (2335:2335:2335)) + (PORT clk (1846:1846:1846) (1873:1873:1873)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1877:1877:1877)) + (PORT d[0] (5176:5176:5176) (5277:5277:5277)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1878:1878:1878)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1878:1878:1878)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1878:1878:1878)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1878:1878:1878)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1804:1804:1804) (1802:1802:1802)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1357:1357:1357) (1402:1402:1402)) + (PORT clk (1814:1814:1814) (1808:1808:1808)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4184:4184:4184) (4244:4244:4244)) + (PORT d[1] (4245:4245:4245) (4296:4296:4296)) + (PORT d[2] (4109:4109:4109) (4210:4210:4210)) + (PORT d[3] (4316:4316:4316) (4447:4447:4447)) + (PORT d[4] (4132:4132:4132) (4244:4244:4244)) + (PORT d[5] (4358:4358:4358) (4486:4486:4486)) + (PORT d[6] (4149:4149:4149) (4218:4218:4218)) + (PORT d[7] (4070:4070:4070) (4173:4173:4173)) + (PORT d[8] (4401:4401:4401) (4450:4450:4450)) + (PORT d[9] (4118:4118:4118) (4213:4213:4213)) + (PORT d[10] (4259:4259:4259) (4326:4326:4326)) + (PORT d[11] (4343:4343:4343) (4436:4436:4436)) + (PORT d[12] (4162:4162:4162) (4268:4268:4268)) + (PORT clk (1810:1810:1810) (1804:1804:1804)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1814:1814:1814) (1808:1808:1808)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1815:1815:1815) (1809:1809:1809)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1815:1815:1815) (1809:1809:1809)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1815:1815:1815) (1809:1809:1809)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1815:1815:1815) (1809:1809:1809)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1635:1635:1635) (1736:1736:1736)) + (PORT clk (1855:1855:1855) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2769:2769:2769) (2892:2892:2892)) + (PORT d[1] (3675:3675:3675) (3804:3804:3804)) + (PORT d[2] (2626:2626:2626) (2825:2825:2825)) + (PORT d[3] (2214:2214:2214) (2326:2326:2326)) + (PORT d[4] (3219:3219:3219) (3326:3326:3326)) + (PORT d[5] (2898:2898:2898) (3031:3031:3031)) + (PORT d[6] (3790:3790:3790) (3911:3911:3911)) + (PORT d[7] (2700:2700:2700) (2864:2864:2864)) + (PORT d[8] (2395:2395:2395) (2480:2480:2480)) + (PORT d[9] (2642:2642:2642) (2770:2770:2770)) + (PORT d[10] (3427:3427:3427) (3672:3672:3672)) + (PORT d[11] (2316:2316:2316) (2429:2429:2429)) + (PORT d[12] (2971:2971:2971) (3142:3142:3142)) + (PORT clk (1852:1852:1852) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2833:2833:2833) (2930:2930:2930)) + (PORT clk (1852:1852:1852) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1855:1855:1855) (1883:1883:1883)) + (PORT d[0] (5273:5273:5273) (5168:5168:5168)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1810:1810:1810) (1808:1808:1808)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1035:1035:1035) (1083:1083:1083)) + (PORT clk (1820:1820:1820) (1814:1814:1814)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4177:4177:4177) (4235:4235:4235)) + (PORT d[1] (4298:4298:4298) (4370:4370:4370)) + (PORT d[2] (4174:4174:4174) (4275:4275:4275)) + (PORT d[3] (4395:4395:4395) (4446:4446:4446)) + (PORT d[4] (4147:4147:4147) (4276:4276:4276)) + (PORT d[5] (4270:4270:4270) (4393:4393:4393)) + (PORT d[6] (4089:4089:4089) (4191:4191:4191)) + (PORT d[7] (4096:4096:4096) (4203:4203:4203)) + (PORT d[8] (4302:4302:4302) (4418:4418:4418)) + (PORT d[9] (4083:4083:4083) (4168:4168:4168)) + (PORT d[10] (4255:4255:4255) (4227:4227:4227)) + (PORT d[11] (4248:4248:4248) (4254:4254:4254)) + (PORT d[12] (4214:4214:4214) (4278:4278:4278)) + (PORT clk (1816:1816:1816) (1810:1810:1810)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1814:1814:1814)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1821:1821:1821) (1815:1815:1815)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1821:1821:1821) (1815:1815:1815)) + (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1821:1821:1821) (1815:1815:1815)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1821:1821:1821) (1815:1815:1815)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1810:1810:1810)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (639:639:639) (659:659:659)) + (PORT datab (636:636:636) (654:654:654)) + (PORT datac (1229:1229:1229) (1282:1282:1282)) + (PORT datad (1527:1527:1527) (1587:1587:1587)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1393:1393:1393) (1396:1396:1396)) + (PORT datab (1198:1198:1198) (1234:1234:1234)) + (PORT datac (1242:1242:1242) (1318:1318:1318)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~82) + (DELAY + (ABSOLUTE + (PORT dataa (1631:1631:1631) (1779:1779:1779)) + (PORT datab (2600:2600:2600) (2767:2767:2767)) + (PORT datac (173:173:173) (207:207:207)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (1636:1636:1636) (1703:1703:1703)) + (PORT datab (1121:1121:1121) (1146:1146:1146)) + (PORT datac (1231:1231:1231) (1274:1274:1274)) + (PORT datad (182:182:182) (211:211:211)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (336:336:336) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (1637:1637:1637) (1700:1700:1700)) + (PORT datab (1583:1583:1583) (1625:1625:1625)) + (PORT datac (1954:1954:1954) (1991:1991:1991)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[2\]) + (DELAY + (ABSOLUTE + (PORT dataa (1431:1431:1431) (1482:1482:1482)) + (PORT datab (217:217:217) (256:256:256)) + (PORT datac (1755:1755:1755) (1789:1789:1789)) + (PORT datad (376:376:376) (397:397:397)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1527:1527:1527) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[2\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (563:563:563) (589:589:589)) + (PORT datac (352:352:352) (379:379:379)) + (PORT datad (1350:1350:1350) (1374:1374:1374)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[2\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (398:398:398) (441:441:441)) + (PORT datab (621:621:621) (651:651:651)) + (PORT datac (236:236:236) (312:312:312)) + (PORT datad (316:316:316) (336:336:336)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT asdata (717:717:717) (742:742:742)) + (PORT clrn (1566:1566:1566) (1548:1548:1548)) + (PORT ena (1698:1698:1698) (1714:1714:1714)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal1\~4) + (DELAY + (ABSOLUTE + (PORT datab (1700:1700:1700) (1759:1759:1759)) + (PORT datac (651:651:651) (715:715:715)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~26) + (DELAY + (ABSOLUTE + (PORT dataa (626:626:626) (679:679:679)) + (PORT datab (581:581:581) (612:612:612)) + (PORT datac (853:853:853) (895:895:895)) + (PORT datad (936:936:936) (1013:1013:1013)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~45) + (DELAY + (ABSOLUTE + (PORT dataa (667:667:667) (723:723:723)) + (PORT datab (1346:1346:1346) (1450:1450:1450)) + (PORT datac (950:950:950) (1009:1009:1009)) + (PORT datad (2364:2364:2364) (2472:2472:2472)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1189:1189:1189) (1236:1236:1236)) + (PORT datac (609:609:609) (620:620:620)) + (PORT datad (672:672:672) (721:721:721)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~18) + (DELAY + (ABSOLUTE + (PORT dataa (660:660:660) (720:720:720)) + (PORT datab (196:196:196) (234:234:234)) + (PORT datac (602:602:602) (615:615:615)) + (PORT datad (795:795:795) (812:812:812)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~11) + (DELAY + (ABSOLUTE + (PORT dataa (944:944:944) (1031:1031:1031)) + (PORT datab (1698:1698:1698) (1757:1757:1757)) + (PORT datac (612:612:612) (633:633:633)) + (PORT datad (1614:1614:1614) (1665:1665:1665)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~10) + (DELAY + (ABSOLUTE + (PORT dataa (654:654:654) (726:726:726)) + (PORT datab (655:655:655) (690:690:690)) + (PORT datac (935:935:935) (977:977:977)) + (PORT datad (1702:1702:1702) (1730:1730:1730)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1253:1253:1253) (1327:1327:1327)) + (PORT datab (863:863:863) (881:881:881)) + (PORT datac (2210:2210:2210) (2204:2204:2204)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~8) + (DELAY + (ABSOLUTE + (PORT dataa (391:391:391) (436:436:436)) + (PORT datab (1048:1048:1048) (1142:1142:1142)) + (PORT datac (1229:1229:1229) (1337:1337:1337)) + (PORT datad (1809:1809:1809) (1886:1886:1886)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1642:1642:1642) (1711:1711:1711)) + (PORT datab (1060:1060:1060) (1165:1165:1165)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~13) + (DELAY + (ABSOLUTE + (PORT dataa (881:881:881) (911:911:911)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (1094:1094:1094) (1103:1103:1103)) + (PORT datad (527:527:527) (539:539:539)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~15) + (DELAY + (ABSOLUTE + (PORT dataa (900:900:900) (931:931:931)) + (PORT datab (1455:1455:1455) (1475:1475:1475)) + (PORT datac (852:852:852) (892:892:892)) + (PORT datad (323:323:323) (336:336:336)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1112:1112:1112) (1123:1123:1123)) + (PORT datab (642:642:642) (684:684:684)) + (PORT datac (193:193:193) (225:225:225)) + (PORT datad (851:851:851) (887:887:887)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~16) + (DELAY + (ABSOLUTE + (PORT datab (939:939:939) (960:960:960)) + (PORT datac (544:544:544) (543:543:543)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1124:1124:1124) (1167:1167:1167)) + (PORT datab (639:639:639) (659:659:659)) + (PORT datac (393:393:393) (428:428:428)) + (PORT datad (1282:1282:1282) (1352:1352:1352)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~23) + (DELAY + (ABSOLUTE + (PORT dataa (1232:1232:1232) (1279:1279:1279)) + (PORT datab (645:645:645) (677:677:677)) + (PORT datac (323:323:323) (355:355:355)) + (PORT datad (615:615:615) (636:636:636)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~22) + (DELAY + (ABSOLUTE + (PORT dataa (1502:1502:1502) (1573:1573:1573)) + (PORT datab (659:659:659) (686:686:686)) + (PORT datac (1295:1295:1295) (1359:1359:1359)) + (PORT datad (1603:1603:1603) (1668:1668:1668)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~56) + (DELAY + (ABSOLUTE + (PORT dataa (288:288:288) (386:386:386)) + (PORT datab (269:269:269) (352:352:352)) + (PORT datac (394:394:394) (461:461:461)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~24) + (DELAY + (ABSOLUTE + (PORT dataa (986:986:986) (1028:1028:1028)) + (PORT datab (716:716:716) (749:749:749)) + (PORT datac (686:686:686) (718:718:718)) + (PORT datad (339:339:339) (357:357:357)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~25) + (DELAY + (ABSOLUTE + (PORT dataa (870:870:870) (906:906:906)) + (PORT datab (945:945:945) (1011:1011:1011)) + (PORT datac (586:586:586) (615:615:615)) + (PORT datad (861:861:861) (893:893:893)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~26) + (DELAY + (ABSOLUTE + (PORT dataa (1699:1699:1699) (1734:1734:1734)) + (PORT datab (1175:1175:1175) (1288:1288:1288)) + (PORT datac (850:850:850) (860:860:860)) + (PORT datad (203:203:203) (232:232:232)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~27) + (DELAY + (ABSOLUTE + (PORT dataa (918:918:918) (952:952:952)) + (PORT datab (965:965:965) (1064:1064:1064)) + (PORT datac (882:882:882) (917:917:917)) + (PORT datad (1924:1924:1924) (1970:1970:1970)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~28) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (219:219:219) (259:259:259)) + (PORT datac (574:574:574) (597:597:597)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~55) + (DELAY + (ABSOLUTE + (PORT dataa (1153:1153:1153) (1187:1187:1187)) + (PORT datab (469:469:469) (549:549:549)) + (PORT datac (420:420:420) (492:492:492)) + (PORT datad (1653:1653:1653) (1722:1722:1722)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~29) + (DELAY + (ABSOLUTE + (PORT dataa (726:726:726) (762:762:762)) + (PORT datab (626:626:626) (660:660:660)) + (PORT datac (884:884:884) (917:917:917)) + (PORT datad (622:622:622) (653:653:653)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~31) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (266:266:266)) + (PORT datab (1282:1282:1282) (1355:1355:1355)) + (PORT datac (170:170:170) (204:204:204)) + (PORT datad (578:578:578) (591:591:591)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~33) + (DELAY + (ABSOLUTE + (PORT dataa (1171:1171:1171) (1229:1229:1229)) + (PORT datab (1916:1916:1916) (1950:1950:1950)) + (PORT datac (608:608:608) (630:630:630)) + (PORT datad (1176:1176:1176) (1214:1214:1214)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~32) + (DELAY + (ABSOLUTE + (PORT dataa (837:837:837) (859:859:859)) + (PORT datab (719:719:719) (751:751:751)) + (PORT datac (608:608:608) (626:626:626)) + (PORT datad (1118:1118:1118) (1168:1168:1168)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~34) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (2938:2938:2938) (3016:3016:3016)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~20) + (DELAY + (ABSOLUTE + (PORT dataa (882:882:882) (902:902:902)) + (PORT datab (953:953:953) (1032:1032:1032)) + (PORT datac (203:203:203) (242:242:242)) + (PORT datad (1353:1353:1353) (1385:1385:1385)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~21) + (DELAY + (ABSOLUTE + (PORT dataa (607:607:607) (657:657:657)) + (PORT datab (966:966:966) (1062:1062:1062)) + (PORT datac (1191:1191:1191) (1245:1245:1245)) + (PORT datad (558:558:558) (574:574:574)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~35) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (169:169:169) (202:202:202)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~43) + (DELAY + (ABSOLUTE + (PORT datab (889:889:889) (942:942:942)) + (PORT datac (1266:1266:1266) (1297:1297:1297)) + (PORT datad (653:653:653) (705:705:705)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~44) + (DELAY + (ABSOLUTE + (PORT dataa (1105:1105:1105) (1131:1131:1131)) + (PORT datab (1221:1221:1221) (1298:1298:1298)) + (PORT datac (1671:1671:1671) (1710:1710:1710)) + (PORT datad (1088:1088:1088) (1188:1188:1188)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~45) + (DELAY + (ABSOLUTE + (PORT dataa (1917:1917:1917) (2023:2023:2023)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (2387:2387:2387) (2467:2467:2467)) + (PORT datad (357:357:357) (390:390:390)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~46) + (DELAY + (ABSOLUTE + (PORT dataa (828:828:828) (878:878:878)) + (PORT datab (967:967:967) (1007:1007:1007)) + (PORT datac (634:634:634) (663:663:663)) + (PORT datad (189:189:189) (222:222:222)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~52) + (DELAY + (ABSOLUTE + (PORT dataa (1292:1292:1292) (1331:1331:1331)) + (PORT datab (198:198:198) (236:236:236)) + (PORT datac (389:389:389) (424:424:424)) + (PORT datad (616:616:616) (656:656:656)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_17) + (DELAY + (ABSOLUTE + (PORT dataa (1049:1049:1049) (1100:1100:1100)) + (PORT datac (840:840:840) (932:932:932)) + (PORT datad (361:361:361) (394:394:394)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|T6) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1565:1565:1565) (1547:1547:1547)) + (PORT ena (1195:1195:1195) (1189:1189:1189)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~53) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (799:799:799) (844:844:844)) + (PORT datac (215:215:215) (290:290:290)) + (PORT datad (188:188:188) (218:218:218)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~54) + (DELAY + (ABSOLUTE + (PORT dataa (570:570:570) (598:598:598)) + (PORT datab (867:867:867) (889:889:889)) + (PORT datac (907:907:907) (970:970:970)) + (PORT datad (551:551:551) (571:571:571)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|DFFE_M1_ff\~0) + (DELAY + (ABSOLUTE + (PORT datab (1159:1159:1159) (1227:1227:1227)) + (PORT datad (895:895:895) (972:972:972)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_M1_ff) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1558:1558:1558) (1539:1539:1539)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|resets_\|x1\~0) + (DELAY + (ABSOLUTE + (PORT datad (196:196:196) (221:221:221)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|fpga_reset) + (DELAY + (ABSOLUTE + (PORT clk (1541:1541:1541) (1560:1560:1560)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE z80_\|fpga_reset\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (596:596:596) (645:645:645)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|resets_\|x1) + (DELAY + (ABSOLUTE + (PORT clk (1546:1546:1546) (1547:1547:1547)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1584:1584:1584) (1563:1563:1563)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|resets_\|x3) + (DELAY + (ABSOLUTE + (PORT datab (2088:2088:2088) (2192:2192:2192)) + (PORT datac (238:238:238) (315:315:315)) + (PORT datad (2475:2475:2475) (2528:2528:2528)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_12) + (DELAY + (ABSOLUTE + (PORT clk (1538:1538:1538) (1555:1555:1555)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1584:1584:1584) (1563:1563:1563)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_10\~0) + (DELAY + (ABSOLUTE + (PORT datad (1770:1770:1770) (1814:1814:1814)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_10) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1526:1526:1526)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_9\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (225:225:225) (298:298:298)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_9) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1526:1526:1526)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|resets_\|DFFE_intr_ff3) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1526:1526:1526)) + (PORT asdata (567:567:567) (646:646:646)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|resets_\|clrpc_int\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1154:1154:1154) (1241:1241:1241)) + (PORT datab (1446:1446:1446) (1529:1529:1529)) + (PORT datad (1248:1248:1248) (1375:1375:1375)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|resets_\|clrpc_int) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1526:1526:1526)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1560:1560:1560) (1542:1542:1542)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|resets_\|clrpc\~0) + (DELAY + (ABSOLUTE + (PORT dataa (253:253:253) (343:343:343)) + (PORT datab (249:249:249) (335:335:335)) + (PORT datad (218:218:218) (287:287:287)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[0\]) + (DELAY + (ABSOLUTE + (PORT datab (961:961:961) (981:981:981)) + (PORT datad (595:595:595) (611:611:611)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -49970,11 +49780,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[0\]\~0) (DELAY (ABSOLUTE - (PORT dataa (1391:1391:1391) (1424:1424:1424)) - (PORT datab (630:630:630) (671:671:671)) - (PORT datad (180:180:180) (209:209:209)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT dataa (622:622:622) (639:639:639)) + (PORT datab (1234:1234:1234) (1264:1264:1264)) + (PORT datad (524:524:524) (538:538:538)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -49984,11 +49794,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[0\]) (DELAY (ABSOLUTE - (PORT clk (1528:1528:1528) (1533:1533:1533)) + (PORT clk (1537:1537:1537) (1535:1535:1535)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (580:580:580) (654:654:654)) - (PORT sload (1117:1117:1117) (1168:1168:1168)) - (PORT ena (811:811:811) (804:804:804)) + (PORT asdata (593:593:593) (675:675:675)) + (PORT sload (1782:1782:1782) (1900:1900:1900)) + (PORT ena (1716:1716:1716) (1679:1679:1679)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -50001,11 +49811,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~59) + (INSTANCE D\[0\]\~47) (DELAY (ABSOLUTE - (PORT dataa (884:884:884) (914:914:914)) - (PORT datab (1147:1147:1147) (1200:1200:1200)) + (PORT dataa (1162:1162:1162) (1228:1228:1228)) + (PORT datab (1041:1041:1041) (1085:1085:1085)) (PORT datac (179:179:179) (216:216:216)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) @@ -50015,15 +49825,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~60) + (INSTANCE D\[0\]\~48) (DELAY (ABSOLUTE - (PORT dataa (948:948:948) (996:996:996)) - (PORT datab (642:642:642) (701:701:701)) - (PORT datac (1642:1642:1642) (1669:1669:1669)) - (PORT datad (329:329:329) (345:345:345)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (342:342:342) (318:318:318)) + (PORT dataa (1311:1311:1311) (1393:1393:1393)) + (PORT datab (1298:1298:1298) (1344:1344:1344)) + (PORT datac (1371:1371:1371) (1393:1393:1393)) + (PORT datad (331:331:331) (348:348:348)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -50031,72 +49841,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~61) + (INSTANCE D\[1\]\~49) (DELAY (ABSOLUTE - (PORT dataa (1445:1445:1445) (1468:1468:1468)) - (PORT datac (831:831:831) (845:845:845)) - (PORT datad (196:196:196) (222:222:222)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~62) - (DELAY - (ABSOLUTE - (PORT dataa (1402:1402:1402) (1476:1476:1476)) - (PORT datab (940:940:940) (1026:1026:1026)) - (PORT datac (962:962:962) (1081:1081:1081)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~63) - (DELAY - (ABSOLUTE - (PORT dataa (365:365:365) (413:413:413)) - (PORT datac (179:179:179) (216:216:216)) - (PORT datad (180:180:180) (209:209:209)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~64) - (DELAY - (ABSOLUTE - (PORT dataa (414:414:414) (500:500:500)) - (PORT datab (233:233:233) (277:277:277)) - (PORT datac (1139:1139:1139) (1183:1183:1183)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~75) - (DELAY - (ABSOLUTE - (PORT dataa (211:211:211) (260:260:260)) - (PORT datac (1325:1325:1325) (1392:1392:1392)) - (PORT datad (197:197:197) (223:223:223)) + (PORT dataa (382:382:382) (409:409:409)) + (PORT datac (885:885:885) (898:898:898)) + (PORT datad (182:182:182) (211:211:211)) (IOPATH dataa combout (341:341:341) (347:347:347)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -50105,13 +49855,43 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~76) + (INSTANCE D\[1\]\~50) (DELAY (ABSOLUTE - (PORT dataa (1121:1121:1121) (1209:1209:1209)) - (PORT datab (1140:1140:1140) (1196:1196:1196)) - (PORT datac (1527:1527:1527) (1561:1561:1561)) - (PORT datad (328:328:328) (343:343:343)) + (PORT dataa (915:915:915) (931:931:931)) + (PORT datab (956:956:956) (1023:1023:1023)) + (PORT datac (1536:1536:1536) (1592:1592:1592)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (1313:1313:1313) (1364:1364:1364)) + (PORT datac (1087:1087:1087) (1112:1112:1112)) + (PORT datad (183:183:183) (212:212:212)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~52) + (DELAY + (ABSOLUTE + (PORT dataa (1130:1130:1130) (1185:1185:1185)) + (PORT datab (1122:1122:1122) (1162:1162:1162)) + (PORT datac (1107:1107:1107) (1159:1159:1159)) + (PORT datad (324:324:324) (339:339:339)) (IOPATH dataa combout (341:341:341) (319:319:319)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -50121,12 +49901,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~82) + (INSTANCE D\[3\]\~58) (DELAY (ABSOLUTE - (PORT dataa (887:887:887) (917:917:917)) - (PORT datab (1549:1549:1549) (1602:1602:1602)) - (PORT datad (181:181:181) (209:209:209)) + (PORT dataa (1162:1162:1162) (1228:1228:1228)) + (PORT datab (1714:1714:1714) (1779:1779:1779)) + (PORT datad (181:181:181) (210:210:210)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -50135,13 +49915,43 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~83) + (INSTANCE D\[3\]\~59) (DELAY (ABSOLUTE - (PORT dataa (952:952:952) (1002:1002:1002)) - (PORT datab (1444:1444:1444) (1508:1508:1508)) - (PORT datac (1641:1641:1641) (1667:1667:1667)) - (PORT datad (330:330:330) (348:348:348)) + (PORT dataa (1149:1149:1149) (1221:1221:1221)) + (PORT datab (1298:1298:1298) (1344:1344:1344)) + (PORT datac (1372:1372:1372) (1395:1395:1395)) + (PORT datad (308:308:308) (327:327:327)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~65) + (DELAY + (ABSOLUTE + (PORT datab (345:345:345) (370:370:370)) + (PORT datac (885:885:885) (896:896:896)) + (PORT datad (180:180:180) (207:207:207)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~66) + (DELAY + (ABSOLUTE + (PORT dataa (918:918:918) (929:929:929)) + (PORT datab (963:963:963) (1031:1031:1031)) + (PORT datac (1536:1536:1536) (1593:1593:1593)) + (PORT datad (175:175:175) (201:201:201)) (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (342:342:342) (318:318:318)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -50151,13 +49961,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~92) + (INSTANCE D\[6\]\~70) (DELAY (ABSOLUTE - (PORT datab (1379:1379:1379) (1383:1383:1383)) - (PORT datac (179:179:179) (215:215:215)) - (PORT datad (180:180:180) (207:207:207)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT dataa (1152:1152:1152) (1177:1177:1177)) + (PORT datac (181:181:181) (217:217:217)) + (PORT datad (180:180:180) (209:209:209)) + (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -50165,15 +49975,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~93) + (INSTANCE D\[6\]\~71) (DELAY (ABSOLUTE - (PORT dataa (948:948:948) (1000:1000:1000)) - (PORT datab (894:894:894) (967:967:967)) - (PORT datac (1642:1642:1642) (1672:1672:1672)) + (PORT dataa (1326:1326:1326) (1423:1423:1423)) + (PORT datab (1123:1123:1123) (1164:1164:1164)) + (PORT datac (1104:1104:1104) (1158:1158:1158)) (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -50184,11 +49994,11 @@ (INSTANCE z80_\|nM1_int\~3) (DELAY (ABSOLUTE - (PORT datab (1365:1365:1365) (1505:1505:1505)) - (PORT datac (2335:2335:2335) (2467:2467:2467)) - (PORT datad (554:554:554) (564:564:564)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (1731:1731:1731) (1846:1846:1846)) + (PORT datab (1069:1069:1069) (1116:1116:1116)) + (PORT datad (438:438:438) (506:506:506)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -50198,10 +50008,10 @@ (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_16) (DELAY (ABSOLUTE - (PORT clk (1535:1535:1535) (1551:1551:1551)) + (PORT clk (1523:1523:1523) (1537:1537:1537)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1591:1591:1591) (1566:1566:1566)) - (PORT ena (1291:1291:1291) (1310:1310:1310)) + (PORT clrn (1567:1567:1567) (1548:1548:1548)) + (PORT ena (1722:1722:1722) (1695:1695:1695)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50216,7 +50026,7 @@ (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_17\~feeder) (DELAY (ABSOLUTE - (PORT datad (242:242:242) (312:312:312)) + (PORT datad (678:678:678) (728:728:728)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -50226,10 +50036,10 @@ (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_17) (DELAY (ABSOLUTE - (PORT clk (1542:1542:1542) (1544:1544:1544)) + (PORT clk (1541:1541:1541) (1540:1540:1540)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1591:1591:1591) (1566:1566:1566)) - (PORT ena (1321:1321:1321) (1347:1347:1347)) + (PORT clrn (1578:1578:1578) (1557:1557:1557)) + (PORT ena (1434:1434:1434) (1415:1415:1415)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50244,10 +50054,10 @@ (INSTANCE z80_\|memory_ifc_\|DFFE_mreq_ff2) (DELAY (ABSOLUTE - (PORT clk (1542:1542:1542) (1544:1544:1544)) - (PORT asdata (565:565:565) (644:644:644)) - (PORT clrn (1591:1591:1591) (1566:1566:1566)) - (PORT ena (1321:1321:1321) (1347:1347:1347)) + (PORT clk (1541:1541:1541) (1540:1540:1540)) + (PORT asdata (567:567:567) (645:645:645)) + (PORT clrn (1578:1578:1578) (1557:1557:1557)) + (PORT ena (1434:1434:1434) (1415:1415:1415)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50262,9 +50072,9 @@ (INSTANCE z80_\|memory_ifc_\|nMREQ_out\~0) (DELAY (ABSOLUTE - (PORT dataa (251:251:251) (340:340:340)) - (PORT datab (251:251:251) (335:335:335)) - (PORT datad (216:216:216) (283:283:283)) + (PORT dataa (253:253:253) (343:343:343)) + (PORT datab (250:250:250) (336:336:336)) + (PORT datad (217:217:217) (286:286:286)) (IOPATH dataa combout (354:354:354) (349:349:349)) (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -50277,9 +50087,9 @@ (INSTANCE z80_\|memory_ifc_\|nMREQ_out\~1) (DELAY (ABSOLUTE - (PORT dataa (912:912:912) (985:985:985)) - (PORT datab (200:200:200) (240:240:240)) - (PORT datad (182:182:182) (211:211:211)) + (PORT dataa (261:261:261) (353:353:353)) + (PORT datab (220:220:220) (260:260:260)) + (PORT datad (174:174:174) (199:199:199)) (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -50310,9 +50120,9 @@ (INSTANCE ula_\|i2c_loader_\|divider\[0\]) (DELAY (ABSOLUTE - (PORT clk (1910:1910:1910) (1908:1908:1908)) + (PORT clk (1911:1911:1911) (1909:1909:1909)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) + (PORT clrn (1565:1565:1565) (1557:1557:1557)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50326,8 +50136,8 @@ (INSTANCE ula_\|i2c_loader_\|divider\[1\]\~5) (DELAY (ABSOLUTE - (PORT dataa (253:253:253) (345:345:345)) - (PORT datab (251:251:251) (337:337:337)) + (PORT dataa (255:255:255) (347:347:347)) + (PORT datab (249:249:249) (334:334:334)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datab combout (344:344:344) (369:369:369)) @@ -50341,9 +50151,9 @@ (INSTANCE ula_\|i2c_loader_\|divider\[1\]) (DELAY (ABSOLUTE - (PORT clk (1910:1910:1910) (1908:1908:1908)) + (PORT clk (1911:1911:1911) (1909:1909:1909)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) + (PORT clrn (1565:1565:1565) (1557:1557:1557)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50357,9 +50167,9 @@ (INSTANCE ula_\|i2c_loader_\|divider\[2\]\~7) (DELAY (ABSOLUTE - (PORT dataa (253:253:253) (343:343:343)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (249:249:249) (333:333:333)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -50371,9 +50181,9 @@ (INSTANCE ula_\|i2c_loader_\|divider\[2\]) (DELAY (ABSOLUTE - (PORT clk (1910:1910:1910) (1908:1908:1908)) + (PORT clk (1911:1911:1911) (1909:1909:1909)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) + (PORT clrn (1565:1565:1565) (1557:1557:1557)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50387,7 +50197,7 @@ (INSTANCE ula_\|i2c_loader_\|divider\[3\]\~9) (DELAY (ABSOLUTE - (PORT datab (252:252:252) (338:338:338)) + (PORT datab (250:250:250) (335:335:335)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -50401,66 +50211,9 @@ (INSTANCE ula_\|i2c_loader_\|divider\[3\]) (DELAY (ABSOLUTE - (PORT clk (1910:1910:1910) (1908:1908:1908)) + (PORT clk (1911:1911:1911) (1909:1909:1909)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|divider\[4\]\~11) - (DELAY - (ABSOLUTE - (PORT datab (251:251:251) (337:337:337)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datab cout (446:446:446) (318:318:318)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|divider\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1910:1910:1910) (1908:1908:1908)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|divider\[5\]\~13) - (DELAY - (ABSOLUTE - (PORT datad (226:226:226) (299:299:299)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|divider\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1910:1910:1910) (1908:1908:1908)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) + (PORT clrn (1565:1565:1565) (1557:1557:1557)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50474,9 +50227,9 @@ (INSTANCE ula_\|i2c_loader_\|WideAnd0\~0) (DELAY (ABSOLUTE - (PORT dataa (253:253:253) (343:343:343)) - (PORT datab (253:253:253) (339:339:339)) - (PORT datac (223:223:223) (302:302:302)) + (PORT dataa (254:254:254) (346:346:346)) + (PORT datab (251:251:251) (336:336:336)) + (PORT datac (223:223:223) (304:304:304)) (PORT datad (225:225:225) (297:297:297)) (IOPATH dataa combout (324:324:324) (328:328:328)) (IOPATH datab combout (333:333:333) (332:332:332)) @@ -50485,16 +50238,73 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|divider\[4\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (251:251:251) (341:341:341)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|divider\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1911:1911:1911) (1909:1909:1909)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1565:1565:1565) (1557:1557:1557)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|divider\[5\]\~13) + (DELAY + (ABSOLUTE + (PORT datab (252:252:252) (338:338:338)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH cin combout (455:455:455) (437:437:437)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|divider\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1911:1911:1911) (1909:1909:1909)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1565:1565:1565) (1557:1557:1557)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2c_loader_\|WideAnd0) (DELAY (ABSOLUTE - (PORT datab (250:250:250) (334:334:334)) - (PORT datac (173:173:173) (206:206:206)) - (PORT datad (225:225:225) (296:296:296)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (202:202:202) (247:247:247)) + (PORT datac (225:225:225) (306:306:306)) + (PORT datad (227:227:227) (301:301:301)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -50504,10 +50314,10 @@ (INSTANCE ula_\|i2c_loader_\|state\.Idle) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1547:1547:1547)) + (PORT clk (1532:1532:1532) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1575:1575:1575)) - (PORT ena (1428:1428:1428) (1403:1403:1403)) + (PORT clrn (1566:1566:1566) (1559:1559:1559)) + (PORT ena (1477:1477:1477) (1441:1441:1441)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50522,7 +50332,7 @@ (INSTANCE ula_\|i2c_loader_\|phase\~0) (DELAY (ABSOLUTE - (PORT datad (245:245:245) (317:317:317)) + (PORT datad (271:271:271) (351:351:351)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -50533,10 +50343,10 @@ (INSTANCE ula_\|i2c_loader_\|phase\[0\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1547:1547:1547)) + (PORT clk (1532:1532:1532) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1575:1575:1575)) - (PORT ena (1428:1428:1428) (1403:1403:1403)) + (PORT clrn (1566:1566:1566) (1559:1559:1559)) + (PORT ena (1477:1477:1477) (1441:1441:1441)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50551,8 +50361,8 @@ (INSTANCE ula_\|i2c_loader_\|phase\~1) (DELAY (ABSOLUTE - (PORT datab (333:333:333) (440:440:440)) - (PORT datad (247:247:247) (319:319:319)) + (PORT datab (280:280:280) (369:369:369)) + (PORT datad (271:271:271) (351:351:351)) (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -50564,10 +50374,10 @@ (INSTANCE ula_\|i2c_loader_\|phase\[1\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1547:1547:1547)) + (PORT clk (1532:1532:1532) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1575:1575:1575)) - (PORT ena (1428:1428:1428) (1403:1403:1403)) + (PORT clrn (1566:1566:1566) (1559:1559:1559)) + (PORT ena (1477:1477:1477) (1441:1441:1441)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50582,20 +50392,24 @@ (INSTANCE ula_\|i2c_loader_\|nbit\~5) (DELAY (ABSOLUTE - (PORT dataa (636:636:636) (709:709:709)) - (IOPATH dataa combout (356:356:356) (368:368:368)) + (PORT datad (666:666:666) (722:722:722)) (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|thisbyte\[0\]\~8) + (INSTANCE ula_\|i2c_loader_\|state\.Idle\~0) (DELAY (ABSOLUTE - (PORT datab (307:307:307) (404:404:404)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (274:274:274) (365:365:365)) + (PORT datab (279:279:279) (367:367:367)) + (PORT datac (587:587:587) (646:646:646)) + (PORT datad (403:403:403) (461:461:461)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -50605,21 +50419,131 @@ (INSTANCE ula_\|i2c_loader_\|Mux42\~0) (DELAY (ABSOLUTE - (PORT datac (700:700:700) (774:774:774)) - (PORT datad (677:677:677) (746:746:746)) + (PORT datab (632:632:632) (708:708:708)) + (PORT datac (647:647:647) (712:712:712)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbit\~6) + (DELAY + (ABSOLUTE + (PORT datab (703:703:703) (762:762:762)) + (PORT datad (241:241:241) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|nbit\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1544:1544:1544)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1564:1564:1564) (1557:1557:1557)) + (PORT ena (972:972:972) (970:970:970)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Done\~0) + (DELAY + (ABSOLUTE + (PORT dataa (254:254:254) (345:345:345)) + (PORT datab (271:271:271) (362:362:362)) + (PORT datac (838:838:838) (903:903:903)) + (PORT datad (235:235:235) (311:311:311)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Ack\~0) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (373:373:373)) + (PORT datab (400:400:400) (435:435:435)) + (PORT datac (352:352:352) (376:376:376)) + (PORT datad (407:407:407) (476:476:476)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Ack\~1) + (DELAY + (ABSOLUTE + (PORT dataa (642:642:642) (658:658:658)) + (PORT datab (624:624:624) (689:689:689)) + (PORT datad (174:174:174) (198:198:198)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|state\.Ack) + (DELAY + (ABSOLUTE + (PORT clk (1902:1902:1902) (1931:1931:1931)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1566:1566:1566) (1559:1559:1559)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (659:659:659) (724:724:724)) + (PORT datab (596:596:596) (661:661:661)) + (PORT datac (639:639:639) (701:701:701)) + (PORT datad (257:257:257) (336:336:336)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2c_loader_\|nbyte\~4) (DELAY (ABSOLUTE - (PORT dataa (286:286:286) (381:381:381)) - (PORT datab (336:336:336) (443:443:443)) - (PORT datad (634:634:634) (704:704:704)) + (PORT dataa (783:783:783) (830:830:830)) + (PORT datab (489:489:489) (568:568:568)) + (PORT datad (445:445:445) (512:512:512)) (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -50632,8 +50556,8 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[0\]\~7) (DELAY (ABSOLUTE - (PORT datab (290:290:290) (381:381:381)) - (PORT datac (578:578:578) (623:623:623)) + (PORT datab (597:597:597) (658:658:658)) + (PORT datac (596:596:596) (666:666:666)) (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (243:243:243) (242:242:242)) ) @@ -50653,10 +50577,10 @@ (INSTANCE ula_\|i2c_loader_\|nbyte\[0\]\~1) (DELAY (ABSOLUTE - (PORT dataa (284:284:284) (379:379:379)) - (PORT datab (272:272:272) (359:359:359)) - (PORT datac (301:301:301) (403:403:403)) - (PORT datad (516:516:516) (513:513:513)) + (PORT dataa (291:291:291) (389:389:389)) + (PORT datab (291:291:291) (384:384:384)) + (PORT datac (453:453:453) (533:533:533)) + (PORT datad (690:690:690) (674:674:674)) (IOPATH dataa combout (341:341:341) (319:319:319)) (IOPATH datab combout (342:342:342) (318:318:318)) (IOPATH datac combout (243:243:243) (241:241:241)) @@ -50669,10 +50593,10 @@ (INSTANCE ula_\|i2c_loader_\|nbyte\[0\]\~2) (DELAY (ABSOLUTE - (PORT dataa (662:662:662) (747:747:747)) - (PORT datab (653:653:653) (670:670:670)) - (PORT datac (172:172:172) (206:206:206)) - (PORT datad (174:174:174) (200:200:200)) + (PORT dataa (618:618:618) (686:686:686)) + (PORT datab (399:399:399) (439:439:439)) + (PORT datac (305:305:305) (329:329:329)) + (PORT datad (175:175:175) (202:202:202)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -50685,11 +50609,11 @@ (INSTANCE ula_\|i2c_loader_\|nbyte\[0\]\~3) (DELAY (ABSOLUTE - (PORT datab (835:835:835) (857:857:857)) - (PORT datac (423:423:423) (492:492:492)) - (PORT datad (174:174:174) (198:198:198)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT datab (437:437:437) (516:516:516)) + (PORT datac (619:619:619) (636:636:636)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -50699,9 +50623,9 @@ (INSTANCE ula_\|i2c_loader_\|nbyte\[1\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1547:1547:1547)) + (PORT clk (1532:1532:1532) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1575:1575:1575)) + (PORT clrn (1566:1566:1566) (1559:1559:1559)) (PORT ena (820:820:820) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) @@ -50714,63 +50638,66 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Stop\~0) + (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~1) (DELAY (ABSOLUTE - (PORT dataa (677:677:677) (755:755:755)) - (PORT datab (713:713:713) (770:770:770)) - (PORT datac (253:253:253) (337:337:337)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (289:289:289) (384:384:384)) + (PORT datab (291:291:291) (384:384:384)) + (PORT datac (593:593:593) (653:653:653)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Stop\~1) + (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~3) (DELAY (ABSOLUTE - (PORT dataa (596:596:596) (620:620:620)) - (PORT datab (263:263:263) (314:314:314)) - (PORT datad (341:341:341) (360:360:360)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (353:353:353) (369:369:369)) + (PORT dataa (378:378:378) (400:400:400)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (352:352:352) (377:377:377)) + (PORT datad (443:443:443) (511:511:511)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (204:204:204) (249:249:249)) + (PORT datab (404:404:404) (441:441:441)) + (PORT datac (622:622:622) (637:637:637)) + (PORT datad (411:411:411) (481:481:481)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|state\.Stop) + (INSTANCE ula_\|i2c_loader_\|nbit\[0\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT clk (1902:1902:1902) (1930:1930:1930)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) + (PORT clrn (1564:1564:1564) (1557:1557:1557)) + (PORT ena (943:943:943) (928:928:928)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) ) (TIMINGCHECK (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Idle\~0) - (DELAY - (ABSOLUTE - (PORT dataa (291:291:291) (389:389:389)) - (PORT datab (261:261:261) (350:350:350)) - (PORT datac (232:232:232) (318:318:318)) - (PORT datad (567:567:567) (616:616:616)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) + (HOLD ena (posedge clk) (157:157:157)) ) ) (CELL @@ -50778,9 +50705,9 @@ (INSTANCE ula_\|i2c_loader_\|nbit\~0) (DELAY (ABSOLUTE - (PORT dataa (637:637:637) (710:710:710)) - (PORT datab (267:267:267) (356:356:356)) - (PORT datad (234:234:234) (311:311:311)) + (PORT dataa (870:870:870) (945:945:945)) + (PORT datab (269:269:269) (361:361:361)) + (PORT datad (232:232:232) (308:308:308)) (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -50795,8 +50722,8 @@ (ABSOLUTE (PORT clk (1530:1530:1530) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1572:1572:1572)) - (PORT ena (1191:1191:1191) (1184:1184:1184)) + (PORT clrn (1564:1564:1564) (1557:1557:1557)) + (PORT ena (972:972:972) (970:970:970)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50808,46 +50735,68 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Done\~0) + (INSTANCE ula_\|i2c_loader_\|state\.Done\~1) (DELAY (ABSOLUTE - (PORT dataa (259:259:259) (351:351:351)) - (PORT datab (249:249:249) (335:335:335)) - (PORT datac (602:602:602) (665:665:665)) - (PORT datad (238:238:238) (316:316:316)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (254:254:254) (343:343:343)) + (PORT datab (270:270:270) (362:362:362)) + (PORT datad (235:235:235) (311:311:311)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Ack\~0) + (INSTANCE ula_\|i2c_loader_\|state\~27) (DELAY (ABSOLUTE - (PORT dataa (361:361:361) (399:399:399)) - (PORT datab (370:370:370) (392:392:392)) - (PORT datac (920:920:920) (977:977:977)) - (PORT datad (327:327:327) (351:351:351)) - (IOPATH dataa combout (341:341:341) (319:319:319)) + (PORT dataa (663:663:663) (729:729:729)) + (PORT datab (677:677:677) (747:747:747)) + (PORT datac (599:599:599) (616:616:616)) + (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\~24) + (DELAY + (ABSOLUTE + (PORT datab (289:289:289) (381:381:381)) + (PORT datac (259:259:259) (350:350:350)) + (PORT datad (253:253:253) (329:329:329)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Ack\~1) + (INSTANCE ula_\|i2c_loader_\|state\~26) (DELAY (ABSOLUTE - (PORT dataa (203:203:203) (247:247:247)) - (PORT datab (562:562:562) (591:591:591)) - (PORT datad (443:443:443) (515:515:515)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (336:336:336) (342:342:342)) + (PORT datab (483:483:483) (561:561:561)) + (PORT datac (195:195:195) (228:228:228)) + (PORT datad (395:395:395) (460:460:460)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Data\~0) + (DELAY + (ABSOLUTE + (PORT datab (201:201:201) (241:241:241)) + (PORT datad (319:319:319) (339:339:339)) + (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -50855,18 +50804,68 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|state\.Ack) + (INSTANCE ula_\|i2c_loader_\|state\.Data) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1544:1544:1544)) + (PORT clk (1532:1532:1532) (1547:1547:1547)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1572:1572:1572)) + (PORT asdata (549:549:549) (584:584:584)) + (PORT clrn (1566:1566:1566) (1560:1560:1560)) + (PORT sload (1221:1221:1221) (1323:1323:1323)) + (PORT ena (1246:1246:1246) (1213:1213:1213)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) ) (TIMINGCHECK (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Done\~2) + (DELAY + (ABSOLUTE + (PORT dataa (218:218:218) (271:271:271)) + (PORT datab (289:289:289) (380:380:380)) + (PORT datac (599:599:599) (615:615:615)) + (PORT datad (238:238:238) (307:307:307)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Pause\~1) + (DELAY + (ABSOLUTE + (PORT dataa (637:637:637) (713:713:713)) + (PORT datab (200:200:200) (240:240:240)) + (PORT datac (204:204:204) (242:242:242)) + (PORT datad (568:568:568) (620:620:620)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|thisbyte\[0\]\~8) + (DELAY + (ABSOLUTE + (PORT datab (287:287:287) (377:377:377)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) ) ) (CELL @@ -50874,13 +50873,13 @@ (INSTANCE ula_\|i2c_loader_\|nbyte\[1\]\~5) (DELAY (ABSOLUTE - (PORT dataa (285:285:285) (380:380:380)) - (PORT datab (272:272:272) (356:356:356)) - (PORT datac (302:302:302) (404:404:404)) - (PORT datad (517:517:517) (510:510:510)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (687:687:687) (747:747:747)) + (PORT datab (612:612:612) (670:670:670)) + (PORT datac (567:567:567) (618:618:618)) + (PORT datad (713:713:713) (698:698:698)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -50890,10 +50889,10 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[0\]\~18) (DELAY (ABSOLUTE - (PORT dataa (416:416:416) (489:489:489)) - (PORT datab (587:587:587) (640:640:640)) - (PORT datac (850:850:850) (859:859:859)) - (PORT datad (309:309:309) (325:325:325)) + (PORT dataa (601:601:601) (660:660:660)) + (PORT datab (610:610:610) (670:670:670)) + (PORT datac (831:831:831) (829:829:829)) + (PORT datad (175:175:175) (201:201:201)) (IOPATH dataa combout (300:300:300) (308:308:308)) (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -50906,12 +50905,12 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[0\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1546:1546:1546)) + (PORT clk (1898:1898:1898) (1914:1914:1914)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (1124:1124:1124) (1148:1148:1148)) - (PORT clrn (1579:1579:1579) (1574:1574:1574)) - (PORT sload (1067:1067:1067) (1036:1036:1036)) - (PORT ena (794:794:794) (792:792:792)) + (PORT asdata (1879:1879:1879) (2003:2003:2003)) + (PORT clrn (1565:1565:1565) (1559:1559:1559)) + (PORT sload (1322:1322:1322) (1292:1292:1292)) + (PORT ena (820:820:820) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50928,7 +50927,7 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[1\]\~10) (DELAY (ABSOLUTE - (PORT datab (297:297:297) (392:392:392)) + (PORT datab (281:281:281) (370:370:370)) (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -50942,12 +50941,12 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[1\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1546:1546:1546)) + (PORT clk (1898:1898:1898) (1914:1914:1914)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (1125:1125:1125) (1149:1149:1149)) - (PORT clrn (1579:1579:1579) (1574:1574:1574)) - (PORT sload (1067:1067:1067) (1036:1036:1036)) - (PORT ena (794:794:794) (792:792:792)) + (PORT asdata (1879:1879:1879) (2004:2004:2004)) + (PORT clrn (1565:1565:1565) (1559:1559:1559)) + (PORT sload (1322:1322:1322) (1292:1292:1292)) + (PORT ena (820:820:820) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50964,9 +50963,9 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[2\]\~12) (DELAY (ABSOLUTE - (PORT datab (288:288:288) (380:380:380)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (289:289:289) (389:389:389)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -50978,11 +50977,11 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[2\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1546:1546:1546)) + (PORT clk (1898:1898:1898) (1914:1914:1914)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1574:1574:1574)) - (PORT sload (1067:1067:1067) (1036:1036:1036)) - (PORT ena (794:794:794) (792:792:792)) + (PORT clrn (1565:1565:1565) (1559:1559:1559)) + (PORT sload (1322:1322:1322) (1292:1292:1292)) + (PORT ena (820:820:820) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50999,7 +50998,7 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[3\]\~14) (DELAY (ABSOLUTE - (PORT datab (306:306:306) (403:403:403)) + (PORT datab (286:286:286) (378:378:378)) (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -51013,12 +51012,12 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[3\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1546:1546:1546)) + (PORT clk (1898:1898:1898) (1914:1914:1914)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (1125:1125:1125) (1150:1150:1150)) - (PORT clrn (1579:1579:1579) (1574:1574:1574)) - (PORT sload (1067:1067:1067) (1036:1036:1036)) - (PORT ena (794:794:794) (792:792:792)) + (PORT asdata (1880:1880:1880) (2004:2004:2004)) + (PORT clrn (1565:1565:1565) (1559:1559:1559)) + (PORT sload (1322:1322:1322) (1292:1292:1292)) + (PORT ena (820:820:820) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -51035,10 +51034,10 @@ (INSTANCE ula_\|i2c_loader_\|Equal2\~0) (DELAY (ABSOLUTE - (PORT dataa (426:426:426) (508:508:508)) - (PORT datab (298:298:298) (392:392:392)) - (PORT datac (277:277:277) (365:365:365)) - (PORT datad (279:279:279) (363:363:363)) + (PORT dataa (647:647:647) (713:713:713)) + (PORT datab (659:659:659) (718:718:718)) + (PORT datac (408:408:408) (480:480:480)) + (PORT datad (449:449:449) (524:524:524)) (IOPATH dataa combout (354:354:354) (349:349:349)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -51046,28 +51045,12 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Pause\~0) - (DELAY - (ABSOLUTE - (PORT dataa (710:710:710) (798:798:798)) - (PORT datab (261:261:261) (350:350:350)) - (PORT datac (704:704:704) (778:778:778)) - (PORT datad (260:260:260) (337:337:337)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2c_loader_\|thisbyte\[4\]\~16) (DELAY (ABSOLUTE - (PORT dataa (308:308:308) (413:413:413)) + (PORT dataa (292:292:292) (385:385:385)) (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH cin combout (455:455:455) (437:437:437)) ) @@ -51078,11 +51061,11 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[4\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1546:1546:1546)) + (PORT clk (1898:1898:1898) (1914:1914:1914)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1574:1574:1574)) - (PORT sload (1067:1067:1067) (1036:1036:1036)) - (PORT ena (794:794:794) (792:792:792)) + (PORT clrn (1565:1565:1565) (1559:1559:1559)) + (PORT sload (1322:1322:1322) (1292:1292:1292)) + (PORT ena (820:820:820) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -51096,30 +51079,28 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Pause\~1) + (INSTANCE ula_\|i2c_loader_\|Equal2\~1) (DELAY (ABSOLUTE - (PORT datab (622:622:622) (640:640:640)) - (PORT datac (335:335:335) (357:357:357)) - (PORT datad (658:658:658) (710:710:710)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT datac (174:174:174) (208:208:208)) + (PORT datad (415:415:415) (482:482:482)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Done\~2) + (INSTANCE ula_\|i2c_loader_\|state\.Pause\~0) (DELAY (ABSOLUTE - (PORT dataa (223:223:223) (267:267:267)) - (PORT datab (286:286:286) (376:376:376)) - (PORT datac (231:231:231) (314:314:314)) - (PORT datad (487:487:487) (489:489:489)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (275:275:275) (366:366:366)) + (PORT datab (396:396:396) (434:434:434)) + (PORT datac (594:594:594) (654:654:654)) + (PORT datad (536:536:536) (550:550:550)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -51129,27 +51110,11 @@ (INSTANCE ula_\|i2c_loader_\|state\.Pause\~2) (DELAY (ABSOLUTE - (PORT dataa (345:345:345) (374:374:374)) - (PORT datab (266:266:266) (320:320:320)) - (PORT datac (261:261:261) (352:352:352)) - (PORT datad (421:421:421) (491:491:491)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Pause\~3) - (DELAY - (ABSOLUTE - (PORT dataa (343:343:343) (380:380:380)) - (PORT datab (590:590:590) (613:613:613)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) + (PORT dataa (202:202:202) (245:245:245)) + (PORT datab (644:644:644) (668:668:668)) + (PORT datad (337:337:337) (357:357:357)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (336:336:336) (342:342:342)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -51160,9 +51125,9 @@ (INSTANCE ula_\|i2c_loader_\|state\.Pause) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT clk (1532:1532:1532) (1547:1547:1547)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) + (PORT clrn (1566:1566:1566) (1560:1560:1560)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -51176,9 +51141,9 @@ (INSTANCE ula_\|i2c_loader_\|state\~25) (DELAY (ABSOLUTE - (PORT dataa (264:264:264) (356:356:356)) - (PORT datab (267:267:267) (321:321:321)) - (PORT datad (419:419:419) (488:488:488)) + (PORT dataa (593:593:593) (651:651:651)) + (PORT datab (580:580:580) (597:597:597)) + (PORT datad (262:262:262) (341:341:341)) (IOPATH dataa combout (300:300:300) (308:308:308)) (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -51191,10 +51156,10 @@ (INSTANCE ula_\|i2c_loader_\|state\.Start) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT clk (1532:1532:1532) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (PORT ena (1192:1192:1192) (1154:1154:1154)) + (PORT clrn (1566:1566:1566) (1559:1559:1559)) + (PORT ena (1477:1477:1477) (1441:1441:1441)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -51209,8 +51174,8 @@ (INSTANCE ula_\|i2c_loader_\|nbyte\~0) (DELAY (ABSOLUTE - (PORT datab (330:330:330) (437:437:437)) - (PORT datad (630:630:630) (700:700:700)) + (PORT datab (485:485:485) (562:562:562)) + (PORT datad (449:449:449) (514:514:514)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -51222,9 +51187,9 @@ (INSTANCE ula_\|i2c_loader_\|nbyte\[0\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1547:1547:1547)) + (PORT clk (1532:1532:1532) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1575:1575:1575)) + (PORT clrn (1566:1566:1566) (1559:1559:1559)) (PORT ena (820:820:820) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) @@ -51237,13 +51202,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~1) + (INSTANCE ula_\|i2c_loader_\|state\.Stop\~0) (DELAY (ABSOLUTE - (PORT dataa (678:678:678) (749:749:749)) - (PORT datac (684:684:684) (733:733:733)) - (PORT datad (441:441:441) (514:514:514)) - (IOPATH dataa combout (371:371:371) (376:376:376)) + (PORT datab (290:290:290) (382:382:382)) + (PORT datac (262:262:262) (352:352:352)) + (PORT datad (255:255:255) (331:331:331)) + (IOPATH datab combout (336:336:336) (325:325:325)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -51251,78 +51216,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~2) + (INSTANCE ula_\|i2c_loader_\|state\.Stop\~1) (DELAY (ABSOLUTE - (PORT dataa (1033:1033:1033) (1086:1086:1086)) - (PORT datab (486:486:486) (561:561:561)) - (PORT datac (255:255:255) (338:338:338)) - (PORT datad (669:669:669) (726:726:726)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (590:590:590) (648:648:648)) - (PORT datad (326:326:326) (348:348:348)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (348:348:348) (387:387:387)) - (PORT datab (262:262:262) (314:314:314)) - (PORT datac (556:556:556) (578:578:578)) - (PORT datad (424:424:424) (491:491:491)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|nbit\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1900:1900:1900) (1919:1919:1919)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1572:1572:1572)) - (PORT ena (1160:1160:1160) (1135:1135:1135)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\~6) - (DELAY - (ABSOLUTE - (PORT dataa (634:634:634) (707:707:707)) - (PORT datad (241:241:241) (319:319:319)) - (IOPATH dataa combout (356:356:356) (368:368:368)) + (PORT dataa (202:202:202) (245:245:245)) + (PORT datab (649:649:649) (669:669:669)) + (PORT datad (376:376:376) (396:396:396)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -51330,111 +51231,18 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|nbit\[1\]) + (INSTANCE ula_\|i2c_loader_\|state\.Stop) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1544:1544:1544)) + (PORT clk (1902:1902:1902) (1931:1931:1931)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1572:1572:1572)) - (PORT ena (1191:1191:1191) (1184:1184:1184)) + (PORT clrn (1566:1566:1566) (1559:1559:1559)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) ) (TIMINGCHECK (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Done\~1) - (DELAY - (ABSOLUTE - (PORT dataa (260:260:260) (355:355:355)) - (PORT datab (252:252:252) (338:338:338)) - (PORT datad (241:241:241) (319:319:319)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\~27) - (DELAY - (ABSOLUTE - (PORT dataa (707:707:707) (793:793:793)) - (PORT datac (701:701:701) (775:775:775)) - (PORT datad (486:486:486) (488:488:488)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\~24) - (DELAY - (ABSOLUTE - (PORT dataa (677:677:677) (753:753:753)) - (PORT datab (714:714:714) (770:770:770)) - (PORT datac (251:251:251) (332:332:332)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\~26) - (DELAY - (ABSOLUTE - (PORT dataa (710:710:710) (798:798:798)) - (PORT datac (702:702:702) (777:777:777)) - (PORT datad (347:347:347) (368:368:368)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Data\~0) - (DELAY - (ABSOLUTE - (PORT dataa (203:203:203) (248:248:248)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|state\.Data) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (578:578:578) (625:625:625)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (PORT sload (875:875:875) (1003:1003:1003)) - (PORT ena (1192:1192:1192) (1154:1154:1154)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) ) ) (CELL @@ -51442,11 +51250,11 @@ (INSTANCE ula_\|i2c_loader_\|scl_out\~0) (DELAY (ABSOLUTE - (PORT datab (288:288:288) (379:379:379)) - (PORT datac (607:607:607) (657:657:657)) - (PORT datad (233:233:233) (310:310:310)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (413:413:413) (490:490:490)) + (PORT datab (290:290:290) (381:381:381)) + (PORT datad (565:565:565) (619:619:619)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -51458,8 +51266,8 @@ (ABSOLUTE (PORT clk (1532:1532:1532) (1547:1547:1547)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1575:1575:1575)) - (PORT ena (1428:1428:1428) (1403:1403:1403)) + (PORT clrn (1566:1566:1566) (1560:1560:1560)) + (PORT ena (1246:1246:1246) (1213:1213:1213)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -51474,10 +51282,10 @@ (INSTANCE ula_\|i2c_loader_\|scl_out\~1) (DELAY (ABSOLUTE - (PORT dataa (661:661:661) (746:746:746)) - (PORT datab (330:330:330) (435:435:435)) - (PORT datac (260:260:260) (348:348:348)) - (PORT datad (218:218:218) (287:287:287)) + (PORT dataa (640:640:640) (713:713:713)) + (PORT datab (673:673:673) (740:740:740)) + (PORT datac (597:597:597) (666:666:666)) + (PORT datad (217:217:217) (285:285:285)) (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (242:242:242)) @@ -51490,12 +51298,12 @@ (INSTANCE ula_\|i2c_loader_\|scl_out\~2) (DELAY (ABSOLUTE - (PORT dataa (650:650:650) (670:670:670)) - (PORT datab (200:200:200) (240:240:240)) - (PORT datad (630:630:630) (699:699:699)) + (PORT dataa (218:218:218) (270:270:270)) + (PORT datab (199:199:199) (237:237:237)) + (PORT datac (609:609:609) (674:674:674)) (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH datac combout (243:243:243) (242:242:242)) ) ) ) @@ -51505,9 +51313,9 @@ (DELAY (ABSOLUTE (PORT clk (1473:1473:1473) (1495:1495:1495)) - (PORT d (958:958:958) (1002:1002:1002)) - (PORT aload (1710:1710:1710) (1775:1775:1775)) - (PORT ena (885:885:885) (884:884:884)) + (PORT d (960:960:960) (1004:1004:1004)) + (PORT aload (1697:1697:1697) (1760:1760:1760)) + (PORT ena (697:697:697) (696:696:696)) (IOPATH (posedge clk) q (617:617:617) (612:612:612)) (IOPATH (posedge aload) q (513:513:513) (508:508:508)) ) @@ -51526,8 +51334,8 @@ (ABSOLUTE (PORT clk (1532:1532:1532) (1547:1547:1547)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1575:1575:1575)) - (PORT ena (1428:1428:1428) (1403:1403:1403)) + (PORT clrn (1566:1566:1566) (1560:1560:1560)) + (PORT ena (1246:1246:1246) (1213:1213:1213)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -51542,10 +51350,10 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\~4) (DELAY (ABSOLUTE - (PORT datac (887:887:887) (940:940:940)) - (PORT datad (610:610:610) (673:673:673)) + (PORT dataa (496:496:496) (561:561:561)) + (PORT datac (640:640:640) (708:708:708)) + (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -51554,10 +51362,10 @@ (INSTANCE ula_\|i2c_loader_\|Mux35\~0) (DELAY (ABSOLUTE - (PORT dataa (442:442:442) (520:520:520)) - (PORT datab (457:457:457) (520:520:520)) - (PORT datac (391:391:391) (449:449:449)) - (PORT datad (395:395:395) (456:456:456)) + (PORT dataa (646:646:646) (716:716:716)) + (PORT datab (654:654:654) (720:720:720)) + (PORT datac (405:405:405) (482:482:482)) + (PORT datad (446:446:446) (528:528:528)) (IOPATH dataa combout (304:304:304) (308:308:308)) (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -51570,26 +51378,10 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\~13) (DELAY (ABSOLUTE - (PORT dataa (306:306:306) (409:409:409)) - (PORT datab (298:298:298) (389:389:389)) - (PORT datac (278:278:278) (370:370:370)) - (PORT datad (262:262:262) (338:338:338)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~14) - (DELAY - (ABSOLUTE - (PORT datac (274:274:274) (369:369:369)) - (PORT datad (260:260:260) (337:337:337)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT dataa (291:291:291) (392:392:392)) + (PORT datac (262:262:262) (350:350:350)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) ) ) ) @@ -51598,12 +51390,92 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\~15) (DELAY (ABSOLUTE - (PORT dataa (203:203:203) (248:248:248)) - (PORT datab (307:307:307) (404:404:404)) - (PORT datac (278:278:278) (370:370:370)) - (PORT datad (198:198:198) (224:224:224)) + (PORT dataa (289:289:289) (389:389:389)) + (PORT datab (280:280:280) (368:368:368)) + (PORT datac (259:259:259) (348:348:348)) + (PORT datad (262:262:262) (342:342:342)) (IOPATH dataa combout (354:354:354) (367:367:367)) (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~16) + (DELAY + (ABSOLUTE + (PORT dataa (210:210:210) (260:260:260)) + (PORT datab (291:291:291) (383:383:383)) + (PORT datac (173:173:173) (207:207:207)) + (PORT datad (262:262:262) (342:342:342)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~17) + (DELAY + (ABSOLUTE + (PORT dataa (601:601:601) (671:671:671)) + (PORT datab (483:483:483) (567:567:567)) + (PORT datac (405:405:405) (482:482:482)) + (PORT datad (617:617:617) (682:682:682)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~18) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (245:245:245)) + (PORT datab (447:447:447) (517:517:517)) + (PORT datac (520:520:520) (535:535:535)) + (PORT datad (446:446:446) (524:524:524)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~20) + (DELAY + (ABSOLUTE + (PORT dataa (631:631:631) (694:694:694)) + (PORT datab (654:654:654) (720:720:720)) + (PORT datac (616:616:616) (676:676:676)) + (PORT datad (418:418:418) (485:485:485)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~21) + (DELAY + (ABSOLUTE + (PORT dataa (550:550:550) (573:573:573)) + (PORT datab (200:200:200) (238:238:238)) + (PORT datac (405:405:405) (480:480:480)) + (PORT datad (446:446:446) (524:524:524)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -51611,12 +51483,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~24) + (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~23) (DELAY (ABSOLUTE - (PORT datab (456:456:456) (520:520:520)) - (PORT datac (890:890:890) (943:943:943)) - (PORT datad (414:414:414) (478:478:478)) + (PORT datab (661:661:661) (726:726:726)) + (PORT datac (638:638:638) (705:705:705)) + (PORT datad (451:451:451) (531:531:531)) (IOPATH datab combout (336:336:336) (325:325:325)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -51628,10 +51500,12 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~6) (DELAY (ABSOLUTE - (PORT dataa (707:707:707) (795:795:795)) - (PORT datac (702:702:702) (777:777:777)) - (PORT datad (261:261:261) (341:341:341)) - (IOPATH dataa combout (324:324:324) (328:328:328)) + (PORT dataa (372:372:372) (404:404:404)) + (PORT datab (629:629:629) (692:692:692)) + (PORT datac (272:272:272) (355:355:355)) + (PORT datad (248:248:248) (320:320:320)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -51642,26 +51516,12 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~7) (DELAY (ABSOLUTE - (PORT dataa (294:294:294) (393:393:393)) - (PORT datab (263:263:263) (313:313:313)) - (PORT datac (173:173:173) (205:205:205)) - (PORT datad (350:350:350) (370:370:370)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~8) - (DELAY - (ABSOLUTE - (PORT datab (447:447:447) (530:530:530)) - (PORT datac (557:557:557) (581:581:581)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH datab combout (304:304:304) (311:311:311)) + (PORT dataa (203:203:203) (247:247:247)) + (PORT datab (281:281:281) (370:370:370)) + (PORT datac (817:817:817) (831:831:831)) + (PORT datad (269:269:269) (349:349:349)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -51674,9 +51534,9 @@ (ABSOLUTE (PORT clk (1532:1532:1532) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1574:1574:1574)) - (PORT sclr (1104:1104:1104) (1198:1198:1198)) - (PORT ena (1397:1397:1397) (1366:1366:1366)) + (PORT clrn (1566:1566:1566) (1559:1559:1559)) + (PORT sclr (948:948:948) (1050:1050:1050)) + (PORT ena (922:922:922) (904:904:904)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -51687,48 +51547,32 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~21) - (DELAY - (ABSOLUTE - (PORT dataa (305:305:305) (408:408:408)) - (PORT datab (305:305:305) (398:398:398)) - (PORT datac (278:278:278) (369:369:369)) - (PORT datad (262:262:262) (338:338:338)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2c_loader_\|shiftreg\~22) (DELAY (ABSOLUTE - (PORT dataa (374:374:374) (397:397:397)) - (PORT datab (373:373:373) (401:401:401)) - (PORT datac (390:390:390) (448:448:448)) - (PORT datad (413:413:413) (480:480:480)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (646:646:646) (716:716:716)) + (PORT datad (221:221:221) (291:291:291)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~23) + (INSTANCE ula_\|i2c_loader_\|shiftreg\[6\]\~9) (DELAY (ABSOLUTE - (PORT dataa (247:247:247) (334:334:334)) - (PORT datac (893:893:893) (946:946:946)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (371:371:371) (403:403:403)) + (PORT datab (625:625:625) (687:687:687)) + (PORT datac (274:274:274) (360:360:360)) + (PORT datad (245:245:245) (317:317:317)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -51738,29 +51582,13 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[6\]\~10) (DELAY (ABSOLUTE - (PORT dataa (712:712:712) (775:775:775)) - (PORT datab (482:482:482) (560:560:560)) - (PORT datac (588:588:588) (650:650:650)) - (PORT datad (197:197:197) (223:223:223)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[6\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1032:1032:1032) (1083:1083:1083)) - (PORT datab (561:561:561) (587:587:587)) - (PORT datac (921:921:921) (976:976:976)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (201:201:201) (246:246:246)) + (PORT datab (282:282:282) (370:370:370)) + (PORT datac (817:817:817) (834:834:834)) + (PORT datad (269:269:269) (349:349:349)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -51772,8 +51600,8 @@ (ABSOLUTE (PORT clk (1532:1532:1532) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1574:1574:1574)) - (PORT ena (1207:1207:1207) (1188:1188:1188)) + (PORT clrn (1566:1566:1566) (1559:1559:1559)) + (PORT ena (1000:1000:1000) (1005:1005:1005)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -51783,49 +51611,17 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~18) - (DELAY - (ABSOLUTE - (PORT dataa (305:305:305) (410:410:410)) - (PORT datab (303:303:303) (399:399:399)) - (PORT datac (274:274:274) (364:364:364)) - (PORT datad (268:268:268) (349:349:349)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2c_loader_\|shiftreg\~19) (DELAY (ABSOLUTE - (PORT dataa (445:445:445) (522:522:522)) - (PORT datab (419:419:419) (491:491:491)) - (PORT datac (308:308:308) (330:330:330)) - (PORT datad (197:197:197) (222:222:222)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~20) - (DELAY - (ABSOLUTE - (PORT dataa (248:248:248) (337:337:337)) - (PORT datac (886:886:886) (938:938:938)) - (PORT datad (176:176:176) (202:202:202)) - (IOPATH dataa combout (304:304:304) (307:307:307)) + (PORT dataa (203:203:203) (247:247:247)) + (PORT datab (247:247:247) (331:331:331)) + (PORT datac (639:639:639) (707:707:707)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (331:331:331) (342:342:342)) (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -51836,74 +51632,8 @@ (ABSOLUTE (PORT clk (1532:1532:1532) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1574:1574:1574)) - (PORT ena (1207:1207:1207) (1188:1188:1188)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~16) - (DELAY - (ABSOLUTE - (PORT dataa (424:424:424) (505:505:505)) - (PORT datab (298:298:298) (389:389:389)) - (PORT datac (273:273:273) (368:368:368)) - (PORT datad (278:278:278) (358:358:358)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~17) - (DELAY - (ABSOLUTE - (PORT dataa (441:441:441) (526:526:526)) - (PORT datab (454:454:454) (519:519:519)) - (PORT datac (501:501:501) (509:509:509)) - (PORT datad (352:352:352) (369:369:369)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~26) - (DELAY - (ABSOLUTE - (PORT dataa (639:639:639) (715:715:715)) - (PORT datab (244:244:244) (327:327:327)) - (PORT datac (888:888:888) (940:940:940)) - (PORT datad (175:175:175) (200:200:200)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1546:1546:1546)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1574:1574:1574)) - (PORT ena (1207:1207:1207) (1188:1188:1188)) + (PORT clrn (1566:1566:1566) (1559:1559:1559)) + (PORT ena (1000:1000:1000) (1005:1005:1005)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -51918,12 +51648,12 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\~25) (DELAY (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (679:679:679) (734:734:734)) - (PORT datac (620:620:620) (667:667:667)) - (PORT datad (364:364:364) (423:423:423)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (499:499:499) (565:565:565)) + (PORT datab (674:674:674) (746:746:746)) + (PORT datac (319:319:319) (348:348:348)) + (PORT datad (218:218:218) (287:287:287)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -51931,13 +51661,13 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[4\]) + (INSTANCE ula_\|i2c_loader_\|shiftreg\[3\]) (DELAY (ABSOLUTE (PORT clk (1532:1532:1532) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1574:1574:1574)) - (PORT ena (1410:1410:1410) (1399:1399:1399)) + (PORT clrn (1566:1566:1566) (1559:1559:1559)) + (PORT ena (1000:1000:1000) (1005:1005:1005)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -51952,9 +51682,75 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\~12) (DELAY (ABSOLUTE - (PORT dataa (544:544:544) (558:558:558)) - (PORT datab (488:488:488) (559:559:559)) - (PORT datad (364:364:364) (420:420:420)) + (PORT dataa (290:290:290) (391:391:391)) + (PORT datab (281:281:281) (370:370:370)) + (PORT datac (260:260:260) (349:349:349)) + (PORT datad (261:261:261) (340:340:340)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~14) + (DELAY + (ABSOLUTE + (PORT dataa (210:210:210) (257:257:257)) + (PORT datab (289:289:289) (380:380:380)) + (PORT datac (173:173:173) (205:205:205)) + (PORT datad (260:260:260) (338:338:338)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~24) + (DELAY + (ABSOLUTE + (PORT dataa (499:499:499) (565:565:565)) + (PORT datab (244:244:244) (327:327:327)) + (PORT datac (640:640:640) (708:708:708)) + (PORT datad (318:318:318) (338:338:338)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|shiftreg\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1546:1546:1546)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1566:1566:1566) (1559:1559:1559)) + (PORT ena (1000:1000:1000) (1005:1005:1005)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~11) + (DELAY + (ABSOLUTE + (PORT dataa (364:364:364) (400:400:400)) + (PORT datab (630:630:630) (693:693:693)) + (PORT datad (366:366:366) (424:424:424)) (IOPATH dataa combout (354:354:354) (349:349:349)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -51966,10 +51762,10 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[5\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1544:1544:1544)) + (PORT clk (1532:1532:1532) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1572:1572:1572)) - (PORT sload (1203:1203:1203) (1299:1299:1299)) + (PORT clrn (1566:1566:1566) (1559:1559:1559)) + (PORT sload (887:887:887) (1009:1009:1009)) (PORT ena (812:812:812) (805:805:805)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) @@ -51984,12 +51780,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~9) + (INSTANCE ula_\|i2c_loader_\|shiftreg\~8) (DELAY (ABSOLUTE - (PORT datab (642:642:642) (706:706:706)) - (PORT datac (893:893:893) (946:946:946)) - (PORT datad (198:198:198) (224:224:224)) + (PORT datab (416:416:416) (476:476:476)) + (PORT datac (646:646:646) (715:715:715)) + (PORT datad (196:196:196) (222:222:222)) (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -52003,9 +51799,9 @@ (ABSOLUTE (PORT clk (1532:1532:1532) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1574:1574:1574)) - (PORT sclr (1104:1104:1104) (1198:1198:1198)) - (PORT ena (1207:1207:1207) (1188:1188:1188)) + (PORT clrn (1566:1566:1566) (1559:1559:1559)) + (PORT sclr (948:948:948) (1050:1050:1050)) + (PORT ena (1000:1000:1000) (1005:1005:1005)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52021,8 +51817,8 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[7\]\~5) (DELAY (ABSOLUTE - (PORT datac (887:887:887) (939:939:939)) - (PORT datad (218:218:218) (287:287:287)) + (PORT datac (646:646:646) (714:714:714)) + (PORT datad (219:219:219) (288:288:288)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -52035,9 +51831,9 @@ (ABSOLUTE (PORT clk (1532:1532:1532) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1574:1574:1574)) - (PORT sclr (1104:1104:1104) (1198:1198:1198)) - (PORT ena (1397:1397:1397) (1366:1366:1366)) + (PORT clrn (1566:1566:1566) (1559:1559:1559)) + (PORT sclr (948:948:948) (1050:1050:1050)) + (PORT ena (922:922:922) (904:904:904)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52053,13 +51849,13 @@ (INSTANCE ula_\|i2c_loader_\|sda_out\~0) (DELAY (ABSOLUTE - (PORT dataa (683:683:683) (742:742:742)) - (PORT datab (416:416:416) (490:490:490)) - (PORT datac (558:558:558) (607:607:607)) - (PORT datad (384:384:384) (444:444:444)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (580:580:580) (642:642:642)) + (PORT datab (591:591:591) (655:655:655)) + (PORT datac (645:645:645) (710:710:710)) + (PORT datad (264:264:264) (344:344:344)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -52069,10 +51865,10 @@ (INSTANCE ula_\|i2c_loader_\|sda_out\~1) (DELAY (ABSOLUTE - (PORT dataa (537:537:537) (561:561:561)) - (PORT datab (327:327:327) (433:433:433)) - (PORT datac (345:345:345) (368:368:368)) - (PORT datad (517:517:517) (510:510:510)) + (PORT dataa (553:553:553) (579:579:579)) + (PORT datab (677:677:677) (747:747:747)) + (PORT datac (172:172:172) (206:206:206)) + (PORT datad (498:498:498) (491:491:491)) (IOPATH dataa combout (341:341:341) (319:319:319)) (IOPATH datab combout (342:342:342) (318:318:318)) (IOPATH datac combout (243:243:243) (242:242:242)) @@ -52085,13 +51881,13 @@ (INSTANCE ula_\|i2c_loader_\|sda_out\~2) (DELAY (ABSOLUTE - (PORT dataa (254:254:254) (345:345:345)) - (PORT datab (329:329:329) (434:434:434)) - (PORT datac (260:260:260) (345:345:345)) - (PORT datad (181:181:181) (208:208:208)) + (PORT dataa (253:253:253) (346:346:346)) + (PORT datab (628:628:628) (705:705:705)) + (PORT datac (643:643:643) (707:707:707)) + (PORT datad (181:181:181) (210:210:210)) (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -52101,13 +51897,13 @@ (INSTANCE ula_\|i2c_loader_\|sda_out\~3) (DELAY (ABSOLUTE - (PORT dataa (255:255:255) (348:348:348)) - (PORT datab (324:324:324) (431:431:431)) - (PORT datac (261:261:261) (346:346:346)) - (PORT datad (180:180:180) (208:208:208)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (255:255:255) (347:347:347)) + (PORT datab (632:632:632) (709:709:709)) + (PORT datac (647:647:647) (712:712:712)) + (PORT datad (181:181:181) (208:208:208)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -52117,12 +51913,12 @@ (INSTANCE ula_\|i2c_loader_\|sda_out\~4) (DELAY (ABSOLUTE - (PORT dataa (663:663:663) (743:743:743)) - (PORT datab (802:802:802) (828:828:828)) - (PORT datac (173:173:173) (206:206:206)) + (PORT dataa (220:220:220) (273:273:273)) + (PORT datab (640:640:640) (701:701:701)) + (PORT datac (172:172:172) (206:206:206)) (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH dataa combout (301:301:301) (307:307:307)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -52134,9 +51930,9 @@ (DELAY (ABSOLUTE (PORT clk (1475:1475:1475) (1497:1497:1497)) - (PORT d (691:691:691) (730:730:730)) - (PORT aload (1726:1726:1726) (1792:1792:1792)) - (PORT ena (1272:1272:1272) (1294:1294:1294)) + (PORT d (694:694:694) (732:732:732)) + (PORT aload (1713:1713:1713) (1777:1777:1777)) + (PORT ena (857:857:857) (866:866:866)) (IOPATH (posedge clk) q (617:617:617) (612:612:612)) (IOPATH (posedge aload) q (513:513:513) (508:508:508)) ) @@ -52162,9 +51958,9 @@ (INSTANCE ula_\|i2s_intf_\|mclk_r\~_Duplicate_1) (DELAY (ABSOLUTE - (PORT clk (1892:1892:1892) (1916:1916:1916)) + (PORT clk (1925:1925:1925) (1950:1950:1950)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1573:1573:1573) (1569:1569:1569)) + (PORT clrn (1567:1567:1567) (1559:1559:1559)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52179,8 +51975,8 @@ (DELAY (ABSOLUTE (PORT clk (1506:1506:1506) (1528:1528:1528)) - (PORT d (2379:2379:2379) (2282:2282:2282)) - (PORT clrn (1763:1763:1763) (1815:1815:1815)) + (PORT d (1249:1249:1249) (1276:1276:1276)) + (PORT clrn (1750:1750:1750) (1800:1800:1800)) (IOPATH (posedge clk) q (586:586:586) (589:589:589)) (IOPATH (negedge clrn) q (712:712:712) (715:715:715)) ) @@ -52195,7 +51991,7 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~1) (DELAY (ABSOLUTE - (PORT dataa (697:697:697) (777:777:777)) + (PORT dataa (403:403:403) (487:487:487)) (IOPATH dataa cout (436:436:436) (315:315:315)) ) ) @@ -52205,9 +52001,9 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~2) (DELAY (ABSOLUTE - (PORT datab (251:251:251) (336:336:336)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (427:427:427) (494:494:494)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -52219,8 +52015,8 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\~2) (DELAY (ABSOLUTE - (PORT dataa (230:230:230) (277:277:277)) - (PORT datac (174:174:174) (208:208:208)) + (PORT dataa (451:451:451) (498:498:498)) + (PORT datac (316:316:316) (346:346:346)) (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datac combout (243:243:243) (242:242:242)) ) @@ -52231,9 +52027,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[1\]) (DELAY (ABSOLUTE - (PORT clk (1892:1892:1892) (1916:1916:1916)) + (PORT clk (1935:1935:1935) (1961:1961:1961)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1573:1573:1573) (1569:1569:1569)) + (PORT clrn (1567:1567:1567) (1559:1559:1559)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52247,9 +52043,9 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~4) (DELAY (ABSOLUTE - (PORT dataa (398:398:398) (479:479:479)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (390:390:390) (459:459:459)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -52261,8 +52057,8 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[2\]\~8) (DELAY (ABSOLUTE - (PORT datad (328:328:328) (343:343:343)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT datac (347:347:347) (370:370:370)) + (IOPATH datac combout (241:241:241) (241:241:241)) ) ) ) @@ -52271,9 +52067,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[2\]) (DELAY (ABSOLUTE - (PORT clk (1892:1892:1892) (1915:1915:1915)) + (PORT clk (1935:1935:1935) (1961:1961:1961)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1573:1573:1573) (1568:1568:1568)) + (PORT clrn (1567:1567:1567) (1559:1559:1559)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52287,7 +52083,7 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~6) (DELAY (ABSOLUTE - (PORT datab (391:391:391) (458:458:458)) + (PORT datab (388:388:388) (459:459:459)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -52301,8 +52097,8 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[3\]\~7) (DELAY (ABSOLUTE - (PORT datac (345:345:345) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT datad (561:561:561) (568:568:568)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -52311,9 +52107,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[3\]) (DELAY (ABSOLUTE - (PORT clk (1892:1892:1892) (1916:1916:1916)) + (PORT clk (1935:1935:1935) (1961:1961:1961)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1573:1573:1573) (1569:1569:1569)) + (PORT clrn (1567:1567:1567) (1559:1559:1559)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52327,9 +52123,9 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~8) (DELAY (ABSOLUTE - (PORT datab (251:251:251) (337:337:337)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (395:395:395) (469:469:469)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -52341,10 +52137,10 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\~1) (DELAY (ABSOLUTE - (PORT dataa (231:231:231) (281:281:281)) - (PORT datac (172:172:172) (204:204:204)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT datac (413:413:413) (454:454:454)) + (PORT datad (314:314:314) (335:335:335)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -52353,9 +52149,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[4\]) (DELAY (ABSOLUTE - (PORT clk (1892:1892:1892) (1916:1916:1916)) + (PORT clk (1935:1935:1935) (1961:1961:1961)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1573:1573:1573) (1569:1569:1569)) + (PORT clrn (1567:1567:1567) (1559:1559:1559)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52369,9 +52165,9 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~10) (DELAY (ABSOLUTE - (PORT datab (251:251:251) (337:337:337)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (393:393:393) (467:467:467)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -52383,7 +52179,7 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[5\]\~6) (DELAY (ABSOLUTE - (PORT datad (175:175:175) (201:201:201)) + (PORT datad (339:339:339) (359:359:359)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -52393,9 +52189,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[5\]) (DELAY (ABSOLUTE - (PORT clk (1892:1892:1892) (1916:1916:1916)) + (PORT clk (1935:1935:1935) (1961:1961:1961)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1573:1573:1573) (1569:1569:1569)) + (PORT clrn (1567:1567:1567) (1559:1559:1559)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52409,12 +52205,12 @@ (INSTANCE ula_\|i2s_intf_\|Equal0\~1) (DELAY (ABSOLUTE - (PORT dataa (400:400:400) (481:481:481)) - (PORT datab (252:252:252) (338:338:338)) - (PORT datac (365:365:365) (427:427:427)) - (PORT datad (227:227:227) (300:300:300)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) + (PORT dataa (398:398:398) (469:469:469)) + (PORT datab (391:391:391) (460:460:460)) + (PORT datac (358:358:358) (423:423:423)) + (PORT datad (367:367:367) (422:422:422)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -52425,7 +52221,7 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~12) (DELAY (ABSOLUTE - (PORT dataa (427:427:427) (491:491:491)) + (PORT dataa (429:429:429) (493:493:493)) (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -52439,8 +52235,8 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[6\]\~5) (DELAY (ABSOLUTE - (PORT datad (338:338:338) (357:357:357)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT datac (317:317:317) (343:343:343)) + (IOPATH datac combout (241:241:241) (241:241:241)) ) ) ) @@ -52449,9 +52245,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[6\]) (DELAY (ABSOLUTE - (PORT clk (1892:1892:1892) (1916:1916:1916)) + (PORT clk (1935:1935:1935) (1961:1961:1961)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1573:1573:1573) (1569:1569:1569)) + (PORT clrn (1567:1567:1567) (1559:1559:1559)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52465,9 +52261,9 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~14) (DELAY (ABSOLUTE - (PORT dataa (438:438:438) (507:507:507)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (251:251:251) (336:336:336)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -52479,8 +52275,8 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[7\]\~4) (DELAY (ABSOLUTE - (PORT datad (333:333:333) (348:348:348)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT datac (174:174:174) (208:208:208)) + (IOPATH datac combout (241:241:241) (241:241:241)) ) ) ) @@ -52489,9 +52285,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[7\]) (DELAY (ABSOLUTE - (PORT clk (1892:1892:1892) (1915:1915:1915)) + (PORT clk (1925:1925:1925) (1950:1950:1950)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1573:1573:1573) (1568:1568:1568)) + (PORT clrn (1567:1567:1567) (1559:1559:1559)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52505,9 +52301,9 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~16) (DELAY (ABSOLUTE - (PORT dataa (396:396:396) (467:467:467)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (250:250:250) (335:335:335)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -52519,8 +52315,8 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\~0) (DELAY (ABSOLUTE - (PORT datab (376:376:376) (401:401:401)) - (PORT datac (380:380:380) (411:411:411)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (193:193:193) (226:226:226)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (241:241:241) (241:241:241)) ) @@ -52531,9 +52327,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[8\]) (DELAY (ABSOLUTE - (PORT clk (1892:1892:1892) (1916:1916:1916)) + (PORT clk (1925:1925:1925) (1950:1950:1950)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1573:1573:1573) (1569:1569:1569)) + (PORT clrn (1567:1567:1567) (1559:1559:1559)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52547,8 +52343,8 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~18) (DELAY (ABSOLUTE - (PORT datad (383:383:383) (442:442:442)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT datab (254:254:254) (340:340:340)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH cin combout (455:455:455) (437:437:437)) ) ) @@ -52558,8 +52354,8 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[9\]\~3) (DELAY (ABSOLUTE - (PORT datad (337:337:337) (357:357:357)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT datac (173:173:173) (207:207:207)) + (IOPATH datac combout (241:241:241) (241:241:241)) ) ) ) @@ -52568,9 +52364,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[9\]) (DELAY (ABSOLUTE - (PORT clk (1892:1892:1892) (1916:1916:1916)) + (PORT clk (1925:1925:1925) (1950:1950:1950)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1573:1573:1573) (1569:1569:1569)) + (PORT clrn (1567:1567:1567) (1559:1559:1559)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52584,12 +52380,12 @@ (INSTANCE ula_\|i2s_intf_\|Equal0\~0) (DELAY (ABSOLUTE - (PORT dataa (397:397:397) (468:468:468)) - (PORT datab (423:423:423) (484:484:484)) - (PORT datac (392:392:392) (453:453:453)) - (PORT datad (393:393:393) (454:454:454)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) + (PORT dataa (426:426:426) (489:489:489)) + (PORT datab (251:251:251) (336:336:336)) + (PORT datac (221:221:221) (301:301:301)) + (PORT datad (223:223:223) (295:295:295)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -52600,35 +52396,25 @@ (INSTANCE ula_\|i2s_intf_\|Equal0\~2) (DELAY (ABSOLUTE - (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (249:249:249) (333:333:333)) - (PORT datac (664:664:664) (736:736:736)) + (PORT dataa (429:429:429) (495:495:495)) + (PORT datab (202:202:202) (242:242:242)) + (PORT datac (373:373:373) (448:448:448)) (PORT datad (176:176:176) (202:202:202)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|lrclk_r\~_Duplicate_2feeder) - (DELAY - (ABSOLUTE - (PORT datad (198:198:198) (224:224:224)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|i2s_intf_\|lrclk_r\~_Duplicate_2) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1540:1540:1540)) + (PORT clk (1924:1924:1924) (1949:1949:1949)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1574:1574:1574) (1568:1568:1568)) + (PORT clrn (1566:1566:1566) (1558:1558:1558)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52642,10 +52428,9 @@ (INSTANCE ula_\|i2s_intf_\|lrclk_r\~0) (DELAY (ABSOLUTE - (PORT datab (905:905:905) (938:938:938)) - (PORT datad (233:233:233) (308:308:308)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT datab (795:795:795) (857:857:857)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) ) ) ) @@ -52655,8 +52440,8 @@ (DELAY (ABSOLUTE (PORT clk (1505:1505:1505) (1526:1526:1526)) - (PORT d (2289:2289:2289) (2450:2450:2450)) - (PORT clrn (1761:1761:1761) (1813:1813:1813)) + (PORT d (1358:1358:1358) (1407:1407:1407)) + (PORT clrn (1748:1748:1748) (1798:1798:1798)) (IOPATH (posedge clk) q (586:586:586) (589:589:589)) (IOPATH (negedge clrn) q (712:712:712) (715:715:715)) ) @@ -52672,8 +52457,8 @@ (DELAY (ABSOLUTE (PORT clk (1505:1505:1505) (1527:1527:1527)) - (PORT d (2528:2528:2528) (2663:2663:2663)) - (PORT clrn (1762:1762:1762) (1814:1814:1814)) + (PORT d (1356:1356:1356) (1407:1407:1407)) + (PORT clrn (1749:1749:1749) (1799:1799:1799)) (IOPATH (posedge clk) q (586:586:586) (589:589:589)) (IOPATH (negedge clrn) q (712:712:712) (715:715:715)) ) @@ -52688,20 +52473,30 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[0\]\~5) (DELAY (ABSOLUTE - (PORT datab (248:248:248) (334:334:334)) + (PORT datab (249:249:249) (334:334:334)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datab cout (446:446:446) (318:318:318)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|bclk_r\~_Duplicate_1feeder) + (DELAY + (ABSOLUTE + (PORT datad (195:195:195) (220:220:220)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|i2s_intf_\|bclk_r\~_Duplicate_1) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1541:1541:1541)) + (PORT clk (1533:1533:1533) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1574:1574:1574) (1569:1569:1569)) + (PORT clrn (1567:1567:1567) (1558:1558:1558)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52715,10 +52510,10 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[4\]\~15) (DELAY (ABSOLUTE - (PORT datab (235:235:235) (283:283:283)) - (PORT datac (873:873:873) (896:896:896)) - (PORT datad (241:241:241) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (PORT dataa (279:279:279) (379:379:379)) + (PORT datac (601:601:601) (623:623:623)) + (PORT datad (204:204:204) (232:232:232)) + (IOPATH dataa combout (325:325:325) (320:320:320)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -52729,12 +52524,12 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[0\]) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1541:1541:1541)) + (PORT clk (1533:1533:1533) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (2714:2714:2714) (2746:2746:2746)) - (PORT clrn (1574:1574:1574) (1569:1569:1569)) - (PORT sload (1479:1479:1479) (1529:1529:1529)) - (PORT ena (790:790:790) (783:783:783)) + (PORT asdata (571:571:571) (613:613:613)) + (PORT clrn (1567:1567:1567) (1558:1558:1558)) + (PORT sload (1210:1210:1210) (1266:1266:1266)) + (PORT ena (794:794:794) (792:792:792)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52751,9 +52546,9 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[1\]\~7) (DELAY (ABSOLUTE - (PORT datab (248:248:248) (333:333:333)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (436:436:436) (500:500:500)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -52765,12 +52560,12 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[1\]) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1541:1541:1541)) + (PORT clk (1533:1533:1533) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (2713:2713:2713) (2746:2746:2746)) - (PORT clrn (1574:1574:1574) (1569:1569:1569)) - (PORT sload (1479:1479:1479) (1529:1529:1529)) - (PORT ena (790:790:790) (783:783:783)) + (PORT asdata (570:570:570) (613:613:613)) + (PORT clrn (1567:1567:1567) (1558:1558:1558)) + (PORT sload (1210:1210:1210) (1266:1266:1266)) + (PORT ena (794:794:794) (792:792:792)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52801,12 +52596,12 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[2\]) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1541:1541:1541)) + (PORT clk (1533:1533:1533) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (2711:2711:2711) (2744:2744:2744)) - (PORT clrn (1574:1574:1574) (1569:1569:1569)) - (PORT sload (1479:1479:1479) (1529:1529:1529)) - (PORT ena (790:790:790) (783:783:783)) + (PORT asdata (569:569:569) (609:609:609)) + (PORT clrn (1567:1567:1567) (1558:1558:1558)) + (PORT sload (1210:1210:1210) (1266:1266:1266)) + (PORT ena (794:794:794) (792:792:792)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52823,7 +52618,7 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[3\]\~11) (DELAY (ABSOLUTE - (PORT dataa (252:252:252) (343:343:343)) + (PORT dataa (252:252:252) (341:341:341)) (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -52837,12 +52632,12 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[3\]) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1541:1541:1541)) + (PORT clk (1533:1533:1533) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (2711:2711:2711) (2744:2744:2744)) - (PORT clrn (1574:1574:1574) (1569:1569:1569)) - (PORT sload (1479:1479:1479) (1529:1529:1529)) - (PORT ena (790:790:790) (783:783:783)) + (PORT asdata (570:570:570) (610:610:610)) + (PORT clrn (1567:1567:1567) (1558:1558:1558)) + (PORT sload (1210:1210:1210) (1266:1266:1266)) + (PORT ena (794:794:794) (792:792:792)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52854,22 +52649,6 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|LessThan0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (252:252:252) (343:343:343)) - (PORT datab (252:252:252) (338:338:338)) - (PORT datac (223:223:223) (303:303:303)) - (PORT datad (227:227:227) (299:299:299)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2s_intf_\|bitcount\[4\]\~13) @@ -52886,12 +52665,12 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[4\]) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1541:1541:1541)) + (PORT clk (1533:1533:1533) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (2710:2710:2710) (2743:2743:2743)) - (PORT clrn (1574:1574:1574) (1569:1569:1569)) - (PORT sload (1479:1479:1479) (1529:1529:1529)) - (PORT ena (790:790:790) (783:783:783)) + (PORT asdata (570:570:570) (610:610:610)) + (PORT clrn (1567:1567:1567) (1558:1558:1558)) + (PORT sload (1210:1210:1210) (1266:1266:1266)) + (PORT ena (794:794:794) (792:792:792)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52903,12 +52682,75 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|LessThan0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (439:439:439) (503:503:503)) + (PORT datab (252:252:252) (338:338:338)) + (PORT datac (225:225:225) (305:305:305)) + (PORT datad (226:226:226) (300:300:300)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|shiftreg\[4\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (437:437:437) (501:501:501)) + (PORT datab (390:390:390) (411:411:411)) + (PORT datac (240:240:240) (328:328:328)) + (PORT datad (190:190:190) (223:223:223)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add2\~18) + (DELAY + (ABSOLUTE + (PORT dataa (492:492:492) (538:538:538)) + (PORT datab (382:382:382) (421:421:421)) + (PORT datad (220:220:220) (257:257:257)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|bdivider\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1566:1566:1566) (1558:1558:1558)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2s_intf_\|Add2\~7) (DELAY (ABSOLUTE - (PORT dataa (467:467:467) (538:538:538)) + (PORT dataa (287:287:287) (384:384:384)) (IOPATH dataa cout (436:436:436) (315:315:315)) ) ) @@ -52918,7 +52760,7 @@ (INSTANCE ula_\|i2s_intf_\|Add2\~8) (DELAY (ABSOLUTE - (PORT dataa (253:253:253) (344:344:344)) + (PORT dataa (252:252:252) (343:343:343)) (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -52932,12 +52774,12 @@ (INSTANCE ula_\|i2s_intf_\|Add2\~20) (DELAY (ABSOLUTE - (PORT dataa (470:470:470) (540:540:540)) - (PORT datab (903:903:903) (940:940:940)) - (PORT datac (205:205:205) (243:243:243)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) + (PORT dataa (291:291:291) (387:387:387)) + (PORT datab (201:201:201) (240:240:240)) + (PORT datac (456:456:456) (504:504:504)) + (PORT datad (217:217:217) (253:253:253)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -52948,9 +52790,9 @@ (INSTANCE ula_\|i2s_intf_\|bdivider\[1\]) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1540:1540:1540)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1574:1574:1574) (1568:1568:1568)) + (PORT clrn (1566:1566:1566) (1558:1558:1558)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52964,7 +52806,7 @@ (INSTANCE ula_\|i2s_intf_\|Add2\~10) (DELAY (ABSOLUTE - (PORT dataa (399:399:399) (472:472:472)) + (PORT dataa (253:253:253) (343:343:343)) (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -52978,12 +52820,12 @@ (INSTANCE ula_\|i2s_intf_\|Add2\~17) (DELAY (ABSOLUTE - (PORT dataa (227:227:227) (284:284:284)) - (PORT datab (234:234:234) (285:285:285)) - (PORT datac (875:875:875) (898:898:898)) - (PORT datad (338:338:338) (359:359:359)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (499:499:499) (546:546:546)) + (PORT datab (232:232:232) (275:275:275)) + (PORT datac (355:355:355) (391:391:391)) + (PORT datad (176:176:176) (202:202:202)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (304:304:304) (308:308:308)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -52994,9 +52836,9 @@ (INSTANCE ula_\|i2s_intf_\|bdivider\[2\]) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1541:1541:1541)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1574:1574:1574) (1569:1569:1569)) + (PORT clrn (1566:1566:1566) (1558:1558:1558)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53010,7 +52852,7 @@ (INSTANCE ula_\|i2s_intf_\|Add2\~12) (DELAY (ABSOLUTE - (PORT datab (253:253:253) (339:339:339)) + (PORT datab (249:249:249) (334:334:334)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -53024,12 +52866,12 @@ (INSTANCE ula_\|i2s_intf_\|Add2\~19) (DELAY (ABSOLUTE - (PORT dataa (471:471:471) (539:539:539)) - (PORT datab (906:906:906) (939:939:939)) - (PORT datac (206:206:206) (243:243:243)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) + (PORT dataa (290:290:290) (387:387:387)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (441:441:441) (486:486:486)) + (PORT datad (221:221:221) (257:257:257)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -53040,9 +52882,9 @@ (INSTANCE ula_\|i2s_intf_\|bdivider\[3\]) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1540:1540:1540)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1574:1574:1574) (1568:1568:1568)) + (PORT clrn (1566:1566:1566) (1558:1558:1558)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53056,7 +52898,7 @@ (INSTANCE ula_\|i2s_intf_\|Add2\~14) (DELAY (ABSOLUTE - (PORT datad (362:362:362) (417:417:417)) + (PORT datad (228:228:228) (301:301:301)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) ) @@ -53067,12 +52909,12 @@ (INSTANCE ula_\|i2s_intf_\|Add2\~16) (DELAY (ABSOLUTE - (PORT dataa (227:227:227) (285:285:285)) - (PORT datab (235:235:235) (288:288:288)) - (PORT datac (875:875:875) (900:900:900)) - (PORT datad (339:339:339) (359:359:359)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (500:500:500) (547:547:547)) + (PORT datab (232:232:232) (275:275:275)) + (PORT datac (355:355:355) (391:391:391)) + (PORT datad (175:175:175) (202:202:202)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (304:304:304) (308:308:308)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -53083,9 +52925,9 @@ (INSTANCE ula_\|i2s_intf_\|bdivider\[4\]) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1541:1541:1541)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1574:1574:1574) (1569:1569:1569)) + (PORT clrn (1566:1566:1566) (1558:1558:1558)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53099,72 +52941,25 @@ (INSTANCE ula_\|i2s_intf_\|Equal1\~0) (DELAY (ABSOLUTE - (PORT dataa (253:253:253) (345:345:345)) - (PORT datab (253:253:253) (339:339:339)) - (PORT datac (368:368:368) (430:430:430)) - (PORT datad (361:361:361) (415:415:415)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (252:252:252) (343:343:343)) + (PORT datab (249:249:249) (335:335:335)) + (PORT datac (223:223:223) (304:304:304)) + (PORT datad (226:226:226) (299:299:299)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[4\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (266:266:266) (353:353:353)) - (PORT datab (217:217:217) (263:263:263)) - (PORT datac (241:241:241) (328:328:328)) - (PORT datad (373:373:373) (399:399:399)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~18) - (DELAY - (ABSOLUTE - (PORT dataa (908:908:908) (938:938:938)) - (PORT datab (235:235:235) (286:286:286)) - (PORT datad (375:375:375) (401:401:401)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|bdivider\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1527:1527:1527) (1541:1541:1541)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1574:1574:1574) (1569:1569:1569)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2s_intf_\|Equal1\~1) (DELAY (ABSOLUTE - (PORT datac (382:382:382) (450:450:450)) - (PORT datad (371:371:371) (396:396:396)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT datab (244:244:244) (291:291:291)) + (PORT datad (261:261:261) (342:342:342)) + (IOPATH datab combout (306:306:306) (311:311:311)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53174,12 +52969,12 @@ (INSTANCE ula_\|i2s_intf_\|bclk_r\~0) (DELAY (ABSOLUTE - (PORT datab (216:216:216) (262:262:262)) - (PORT datac (239:239:239) (326:326:326)) - (PORT datad (238:238:238) (316:316:316)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT dataa (275:275:275) (376:376:376)) + (PORT datab (215:215:215) (259:259:259)) + (PORT datac (240:240:240) (328:328:328)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) ) ) ) @@ -53188,12 +52983,13 @@ (INSTANCE ula_\|i2s_intf_\|bclk_r\~1) (DELAY (ABSOLUTE - (PORT dataa (226:226:226) (283:283:283)) - (PORT datab (199:199:199) (239:239:239)) - (PORT datad (869:869:869) (882:882:882)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) + (PORT dataa (373:373:373) (401:401:401)) + (PORT datab (631:631:631) (655:655:655)) + (PORT datac (245:245:245) (335:335:335)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53204,8 +53000,8 @@ (DELAY (ABSOLUTE (PORT clk (1504:1504:1504) (1526:1526:1526)) - (PORT d (2278:2278:2278) (2430:2430:2430)) - (PORT clrn (1761:1761:1761) (1813:1813:1813)) + (PORT d (1540:1540:1540) (1616:1616:1616)) + (PORT clrn (1748:1748:1748) (1798:1798:1798)) (IOPATH (posedge clk) q (586:586:586) (589:589:589)) (IOPATH (negedge clrn) q (712:712:712) (715:715:715)) ) @@ -53215,27 +53011,17 @@ (HOLD d (posedge clk) (97:97:97)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|pcm_outl\[13\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (861:861:861) (917:917:917)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|always0\~2) (DELAY (ABSOLUTE - (PORT dataa (1754:1754:1754) (1860:1860:1860)) - (PORT datab (1594:1594:1594) (1730:1730:1730)) - (PORT datac (1193:1193:1193) (1255:1255:1255)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (586:586:586) (615:615:615)) + (PORT datab (2799:2799:2799) (2989:2989:2989)) + (PORT datad (605:605:605) (624:624:624)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -53244,12 +53030,12 @@ (INSTANCE ula_\|always0\~3) (DELAY (ABSOLUTE - (PORT dataa (686:686:686) (777:777:777)) - (PORT datab (1248:1248:1248) (1347:1347:1347)) - (PORT datac (1200:1200:1200) (1266:1266:1266)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) + (PORT dataa (246:246:246) (300:300:300)) + (PORT datab (958:958:958) (1019:1019:1019)) + (PORT datac (2765:2765:2765) (2956:2956:2956)) + (PORT datad (520:520:520) (530:530:530)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -53257,12 +53043,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|pcm_outl\[13\]) + (INSTANCE ula_\|pcm_outl\[14\]) (DELAY (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT clk (1518:1518:1518) (1532:1532:1532)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (2002:2002:2002) (1998:1998:1998)) + (PORT ena (1943:1943:1943) (1924:1924:1924)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -53276,12 +53062,12 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[0\]\~19) (DELAY (ABSOLUTE - (PORT dataa (225:225:225) (279:279:279)) - (PORT datab (216:216:216) (259:259:259)) - (PORT datac (241:241:241) (328:328:328)) - (PORT datad (239:239:239) (317:317:317)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (331:331:331) (342:342:342)) + (PORT dataa (371:371:371) (403:403:403)) + (PORT datab (269:269:269) (361:361:361)) + (PORT datac (247:247:247) (339:339:339)) + (PORT datad (190:190:190) (222:222:222)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -53301,11 +53087,11 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[0\]\~20) (DELAY (ABSOLUTE - (PORT dataa (1354:1354:1354) (1417:1417:1417)) - (PORT datab (1297:1297:1297) (1385:1385:1385)) - (PORT datad (764:764:764) (757:757:757)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (336:336:336) (342:342:342)) + (PORT dataa (496:496:496) (543:543:543)) + (PORT datab (340:340:340) (373:373:373)) + (PORT datad (795:795:795) (785:785:785)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -53316,9 +53102,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[0\]) (DELAY (ABSOLUTE - (PORT clk (1877:1877:1877) (1887:1887:1887)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1572:1572:1572)) + (PORT clrn (1566:1566:1566) (1558:1558:1558)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53332,10 +53118,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~18) (DELAY (ABSOLUTE - (PORT datab (244:244:244) (327:327:327)) - (PORT datad (1250:1250:1250) (1334:1334:1334)) + (PORT datab (423:423:423) (489:489:489)) + (PORT datac (764:764:764) (828:828:828)) (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH datac combout (241:241:241) (241:241:241)) ) ) ) @@ -53344,10 +53130,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[4\]\~2) (DELAY (ABSOLUTE - (PORT datab (234:234:234) (283:283:283)) - (PORT datac (872:872:872) (895:895:895)) - (PORT datad (240:240:240) (318:318:318)) - (IOPATH datab combout (304:304:304) (311:311:311)) + (PORT dataa (274:274:274) (375:375:375)) + (PORT datac (601:601:601) (625:625:625)) + (PORT datad (204:204:204) (234:234:234)) + (IOPATH dataa combout (303:303:303) (308:308:308)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -53358,10 +53144,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[1\]) (DELAY (ABSOLUTE - (PORT clk (1907:1907:1907) (1929:1929:1929)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1572:1572:1572)) - (PORT ena (2122:2122:2122) (2190:2190:2190)) + (PORT clrn (1566:1566:1566) (1558:1558:1558)) + (PORT ena (1212:1212:1212) (1209:1209:1209)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53376,10 +53162,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~17) (DELAY (ABSOLUTE - (PORT datac (216:216:216) (293:293:293)) - (PORT datad (1250:1250:1250) (1341:1341:1341)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT datab (792:792:792) (867:867:867)) + (PORT datac (219:219:219) (296:296:296)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) ) ) ) @@ -53388,10 +53174,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[2\]) (DELAY (ABSOLUTE - (PORT clk (1907:1907:1907) (1929:1929:1929)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1572:1572:1572)) - (PORT ena (2122:2122:2122) (2190:2190:2190)) + (PORT clrn (1566:1566:1566) (1558:1558:1558)) + (PORT ena (1212:1212:1212) (1209:1209:1209)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53406,9 +53192,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~16) (DELAY (ABSOLUTE - (PORT datab (245:245:245) (328:328:328)) - (PORT datad (1259:1259:1259) (1340:1340:1340)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (PORT datac (758:758:758) (830:830:830)) + (PORT datad (219:219:219) (287:287:287)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53418,10 +53204,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[3\]) (DELAY (ABSOLUTE - (PORT clk (1907:1907:1907) (1929:1929:1929)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1572:1572:1572)) - (PORT ena (2122:2122:2122) (2190:2190:2190)) + (PORT clrn (1566:1566:1566) (1558:1558:1558)) + (PORT ena (1212:1212:1212) (1209:1209:1209)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53436,10 +53222,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~15) (DELAY (ABSOLUTE - (PORT datab (246:246:246) (330:330:330)) - (PORT datad (1269:1269:1269) (1352:1352:1352)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT datab (797:797:797) (863:863:863)) + (PORT datac (219:219:219) (296:296:296)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) ) ) ) @@ -53448,10 +53234,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[4\]) (DELAY (ABSOLUTE - (PORT clk (1907:1907:1907) (1929:1929:1929)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1572:1572:1572)) - (PORT ena (2122:2122:2122) (2190:2190:2190)) + (PORT clrn (1566:1566:1566) (1558:1558:1558)) + (PORT ena (1212:1212:1212) (1209:1209:1209)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53466,9 +53252,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~14) (DELAY (ABSOLUTE - (PORT datab (245:245:245) (328:328:328)) - (PORT datad (1270:1270:1270) (1351:1351:1351)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (PORT datac (751:751:751) (831:831:831)) + (PORT datad (219:219:219) (288:288:288)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53478,10 +53264,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[5\]) (DELAY (ABSOLUTE - (PORT clk (1907:1907:1907) (1929:1929:1929)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1572:1572:1572)) - (PORT ena (2122:2122:2122) (2190:2190:2190)) + (PORT clrn (1566:1566:1566) (1558:1558:1558)) + (PORT ena (1212:1212:1212) (1209:1209:1209)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53496,10 +53282,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~13) (DELAY (ABSOLUTE - (PORT dataa (247:247:247) (335:335:335)) - (PORT datad (1261:1261:1261) (1348:1348:1348)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT datab (799:799:799) (870:870:870)) + (PORT datac (217:217:217) (294:294:294)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) ) ) ) @@ -53508,10 +53294,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[6\]) (DELAY (ABSOLUTE - (PORT clk (1907:1907:1907) (1929:1929:1929)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1572:1572:1572)) - (PORT ena (2122:2122:2122) (2190:2190:2190)) + (PORT clrn (1566:1566:1566) (1558:1558:1558)) + (PORT ena (1212:1212:1212) (1209:1209:1209)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53526,9 +53312,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~12) (DELAY (ABSOLUTE - (PORT datab (245:245:245) (328:328:328)) - (PORT datad (1246:1246:1246) (1335:1335:1335)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (PORT datac (766:766:766) (829:829:829)) + (PORT datad (218:218:218) (286:286:286)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53538,10 +53324,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[7\]) (DELAY (ABSOLUTE - (PORT clk (1907:1907:1907) (1929:1929:1929)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1572:1572:1572)) - (PORT ena (2122:2122:2122) (2190:2190:2190)) + (PORT clrn (1566:1566:1566) (1558:1558:1558)) + (PORT ena (1212:1212:1212) (1209:1209:1209)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53556,10 +53342,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~11) (DELAY (ABSOLUTE - (PORT datac (216:216:216) (292:292:292)) - (PORT datad (1248:1248:1248) (1334:1334:1334)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT datab (802:802:802) (872:872:872)) + (PORT datac (217:217:217) (294:294:294)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) ) ) ) @@ -53568,10 +53354,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[8\]) (DELAY (ABSOLUTE - (PORT clk (1907:1907:1907) (1929:1929:1929)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1572:1572:1572)) - (PORT ena (2122:2122:2122) (2190:2190:2190)) + (PORT clrn (1566:1566:1566) (1558:1558:1558)) + (PORT ena (1212:1212:1212) (1209:1209:1209)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53586,9 +53372,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~10) (DELAY (ABSOLUTE - (PORT datab (244:244:244) (327:327:327)) - (PORT datad (1249:1249:1249) (1344:1344:1344)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (PORT datac (754:754:754) (823:823:823)) + (PORT datad (219:219:219) (288:288:288)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53598,10 +53384,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[9\]) (DELAY (ABSOLUTE - (PORT clk (1907:1907:1907) (1929:1929:1929)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1572:1572:1572)) - (PORT ena (2122:2122:2122) (2190:2190:2190)) + (PORT clrn (1566:1566:1566) (1558:1558:1558)) + (PORT ena (1212:1212:1212) (1209:1209:1209)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53616,10 +53402,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~9) (DELAY (ABSOLUTE - (PORT datac (218:218:218) (296:296:296)) - (PORT datad (1269:1269:1269) (1350:1350:1350)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT dataa (247:247:247) (335:335:335)) + (PORT datac (759:759:759) (831:831:831)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (241:241:241)) ) ) ) @@ -53628,10 +53414,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[10\]) (DELAY (ABSOLUTE - (PORT clk (1907:1907:1907) (1929:1929:1929)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1572:1572:1572)) - (PORT ena (2122:2122:2122) (2190:2190:2190)) + (PORT clrn (1566:1566:1566) (1558:1558:1558)) + (PORT ena (1212:1212:1212) (1209:1209:1209)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53646,9 +53432,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~8) (DELAY (ABSOLUTE - (PORT dataa (246:246:246) (334:334:334)) - (PORT datad (1268:1268:1268) (1351:1351:1351)) - (IOPATH dataa combout (354:354:354) (367:367:367)) + (PORT datac (760:760:760) (831:831:831)) + (PORT datad (219:219:219) (288:288:288)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53658,10 +53444,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[11\]) (DELAY (ABSOLUTE - (PORT clk (1907:1907:1907) (1929:1929:1929)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1572:1572:1572)) - (PORT ena (2122:2122:2122) (2190:2190:2190)) + (PORT clrn (1566:1566:1566) (1558:1558:1558)) + (PORT ena (1212:1212:1212) (1209:1209:1209)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53676,10 +53462,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~7) (DELAY (ABSOLUTE - (PORT datab (244:244:244) (327:327:327)) - (PORT datad (1265:1265:1265) (1355:1355:1355)) + (PORT datab (245:245:245) (327:327:327)) + (PORT datac (765:765:765) (828:828:828)) (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH datac combout (241:241:241) (241:241:241)) ) ) ) @@ -53688,10 +53474,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[12\]) (DELAY (ABSOLUTE - (PORT clk (1907:1907:1907) (1929:1929:1929)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1572:1572:1572)) - (PORT ena (2122:2122:2122) (2190:2190:2190)) + (PORT clrn (1566:1566:1566) (1558:1558:1558)) + (PORT ena (1212:1212:1212) (1209:1209:1209)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53701,47 +53487,16 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|PCM_INR\[14\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1406:1406:1406) (1457:1457:1457)) - (PORT datab (896:896:896) (935:935:935)) - (PORT datad (232:232:232) (306:306:306)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|PCM_INR\[14\]) - (DELAY - (ABSOLUTE - (PORT clk (1527:1527:1527) (1540:1540:1540)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1574:1574:1574) (1568:1568:1568)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2s_intf_\|PCM_INL\[14\]\~0) (DELAY (ABSOLUTE - (PORT dataa (1405:1405:1405) (1456:1456:1456)) - (PORT datab (896:896:896) (934:934:934)) - (PORT datad (232:232:232) (306:306:306)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT dataa (501:501:501) (547:547:547)) + (PORT datab (587:587:587) (643:643:643)) + (PORT datad (384:384:384) (441:441:441)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (336:336:336) (342:342:342)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -53752,9 +53507,40 @@ (INSTANCE ula_\|i2s_intf_\|PCM_INL\[14\]) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1540:1540:1540)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1574:1574:1574) (1568:1568:1568)) + (PORT clrn (1566:1566:1566) (1558:1558:1558)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|PCM_INR\[14\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (495:495:495) (542:542:542)) + (PORT datab (585:585:585) (641:641:641)) + (PORT datad (382:382:382) (439:439:439)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|PCM_INR\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1566:1566:1566) (1558:1558:1558)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53768,8 +53554,8 @@ (INSTANCE ula_\|pcm_outr\~0) (DELAY (ABSOLUTE - (PORT datac (218:218:218) (296:296:296)) - (PORT datad (219:219:219) (289:289:289)) + (PORT datac (216:216:216) (293:293:293)) + (PORT datad (218:218:218) (286:286:286)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -53780,9 +53566,9 @@ (INSTANCE ula_\|pcm_outl\[12\]) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1540:1540:1540)) + (PORT clk (1526:1526:1526) (1538:1538:1538)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (2116:2116:2116) (2146:2146:2146)) + (PORT ena (3548:3548:3548) (3625:3625:3625)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -53796,11 +53582,11 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~6) (DELAY (ABSOLUTE - (PORT datab (1303:1303:1303) (1391:1391:1391)) - (PORT datac (218:218:218) (295:295:295)) - (PORT datad (1337:1337:1337) (1421:1421:1421)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT datab (246:246:246) (330:330:330)) + (PORT datac (749:749:749) (828:828:828)) + (PORT datad (385:385:385) (449:449:449)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53810,10 +53596,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[13\]) (DELAY (ABSOLUTE - (PORT clk (1907:1907:1907) (1929:1929:1929)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1572:1572:1572)) - (PORT ena (2122:2122:2122) (2190:2190:2190)) + (PORT clrn (1566:1566:1566) (1558:1558:1558)) + (PORT ena (1212:1212:1212) (1209:1209:1209)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53823,16 +53609,32 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|pcm_outl\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (2394:2394:2394) (2437:2437:2437)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2s_intf_\|shiftreg\~5) (DELAY (ABSOLUTE - (PORT datab (1222:1222:1222) (1334:1334:1334)) - (PORT datac (217:217:217) (292:292:292)) - (PORT datad (1267:1267:1267) (1356:1356:1356)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (247:247:247) (333:333:333)) + (PORT datab (794:794:794) (864:864:864)) + (PORT datad (1954:1954:1954) (2063:2063:2063)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53842,10 +53644,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[14\]) (DELAY (ABSOLUTE - (PORT clk (1907:1907:1907) (1929:1929:1929)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1572:1572:1572)) - (PORT ena (2122:2122:2122) (2190:2190:2190)) + (PORT clrn (1566:1566:1566) (1558:1558:1558)) + (PORT ena (1212:1212:1212) (1209:1209:1209)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53855,33 +53657,17 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|pcm_outl\[14\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (2262:2262:2262) (2235:2235:2235)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2s_intf_\|shiftreg\~4) (DELAY (ABSOLUTE - (PORT dataa (1212:1212:1212) (1296:1296:1296)) - (PORT datac (981:981:981) (1087:1087:1087)) - (PORT datad (656:656:656) (680:680:680)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT dataa (2341:2341:2341) (2498:2498:2498)) + (PORT datab (265:265:265) (347:347:347)) + (PORT datac (756:756:756) (824:824:824)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) ) ) ) @@ -53890,10 +53676,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[15\]) (DELAY (ABSOLUTE - (PORT clk (1895:1895:1895) (1927:1927:1927)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1575:1575:1575) (1569:1569:1569)) - (PORT ena (1154:1154:1154) (1136:1136:1136)) + (PORT clrn (1566:1566:1566) (1558:1558:1558)) + (PORT ena (1212:1212:1212) (1209:1209:1209)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53908,10 +53694,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~3) (DELAY (ABSOLUTE - (PORT datac (216:216:216) (293:293:293)) - (PORT datad (656:656:656) (683:683:683)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT dataa (451:451:451) (498:498:498)) + (PORT datac (603:603:603) (664:664:664)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) ) ) ) @@ -53920,10 +53706,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[16\]) (DELAY (ABSOLUTE - (PORT clk (1528:1528:1528) (1541:1541:1541)) + (PORT clk (1905:1905:1905) (1924:1924:1924)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1575:1575:1575) (1569:1569:1569)) - (PORT ena (1190:1190:1190) (1184:1184:1184)) + (PORT clrn (1567:1567:1567) (1559:1559:1559)) + (PORT ena (1441:1441:1441) (1438:1438:1438)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53938,10 +53724,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~0) (DELAY (ABSOLUTE - (PORT datab (243:243:243) (325:325:325)) - (PORT datad (652:652:652) (681:681:681)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT dataa (245:245:245) (332:332:332)) + (PORT datac (416:416:416) (458:458:458)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (241:241:241)) ) ) ) @@ -53951,9 +53737,9 @@ (DELAY (ABSOLUTE (PORT clk (1508:1508:1508) (1530:1530:1530)) - (PORT d (1487:1487:1487) (1588:1588:1588)) - (PORT clrn (1765:1765:1765) (1817:1817:1817)) - (PORT ena (1717:1717:1717) (1806:1806:1806)) + (PORT d (899:899:899) (948:948:948)) + (PORT clrn (1752:1752:1752) (1802:1802:1802)) + (PORT ena (887:887:887) (888:888:888)) (IOPATH (posedge clk) q (586:586:586) (589:589:589)) (IOPATH (negedge clrn) q (712:712:712) (715:715:715)) ) @@ -53967,16 +53753,57 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|LessThan2\~0) + (INSTANCE ula_\|border\[1\]\~feeder) (DELAY (ABSOLUTE - (PORT dataa (291:291:291) (381:381:381)) - (PORT datab (270:270:270) (353:353:353)) - (PORT datac (262:262:262) (341:341:341)) - (PORT datad (244:244:244) (316:316:316)) + (PORT datad (217:217:217) (243:243:243)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|border\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1943:1943:1943) (1924:1924:1924)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|LessThan4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (449:449:449) (514:514:514)) + (PORT datab (272:272:272) (357:357:357)) + (PORT datac (242:242:242) (321:321:321)) + (PORT datad (243:243:243) (313:313:313)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|screen_en\~0) + (DELAY + (ABSOLUTE + (PORT dataa (444:444:444) (511:511:511)) + (PORT datab (269:269:269) (352:352:352)) + (PORT datad (309:309:309) (327:327:327)) (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53986,10 +53813,57 @@ (INSTANCE ula_\|video_\|LessThan6\~0) (DELAY (ABSOLUTE - (PORT dataa (263:263:263) (348:348:348)) - (PORT datab (260:260:260) (342:342:342)) - (PORT datac (255:255:255) (332:332:332)) - (PORT datad (237:237:237) (307:307:307)) + (PORT dataa (262:262:262) (348:348:348)) + (PORT datab (261:261:261) (342:342:342)) + (PORT datad (238:238:238) (307:307:307)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|LessThan6\~1) + (DELAY + (ABSOLUTE + (PORT dataa (283:283:283) (370:370:370)) + (PORT datab (281:281:281) (364:364:364)) + (PORT datac (236:236:236) (313:313:313)) + (PORT datad (338:338:338) (357:357:357)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|screen_en\~1) + (DELAY + (ABSOLUTE + (PORT dataa (413:413:413) (492:492:492)) + (PORT datab (463:463:463) (525:525:525)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (174:174:174) (198:198:198)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|LessThan2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (655:655:655) (724:724:724)) + (PORT datab (290:290:290) (376:376:376)) + (PORT datac (424:424:424) (483:483:483)) + (PORT datad (385:385:385) (444:444:444)) (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -54002,12 +53876,12 @@ (INSTANCE ula_\|video_\|LessThan2\~1) (DELAY (ABSOLUTE - (PORT dataa (457:457:457) (540:540:540)) - (PORT datab (270:270:270) (354:354:354)) - (PORT datac (173:173:173) (207:207:207)) - (PORT datad (356:356:356) (374:374:374)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (333:333:333) (332:332:332)) + (PORT dataa (641:641:641) (708:708:708)) + (PORT datab (415:415:415) (493:493:493)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (205:205:205) (235:235:235)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -54018,12 +53892,13 @@ (INSTANCE ula_\|video_\|LessThan3\~0) (DELAY (ABSOLUTE - (PORT dataa (291:291:291) (383:383:383)) - (PORT datab (241:241:241) (280:280:280)) - (PORT datad (195:195:195) (221:221:221)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (353:353:353) (369:369:369)) + (PORT dataa (624:624:624) (700:700:700)) + (PORT datab (228:228:228) (271:271:271)) + (PORT datac (620:620:620) (685:685:685)) + (PORT datad (194:194:194) (219:219:219)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54033,11 +53908,10 @@ (INSTANCE ula_\|video_\|LessThan0\~0) (DELAY (ABSOLUTE - (PORT dataa (271:271:271) (361:361:361)) - (PORT datab (261:261:261) (343:343:343)) - (PORT datad (247:247:247) (320:320:320)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) + (PORT datab (269:269:269) (352:352:352)) + (PORT datad (246:246:246) (318:318:318)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54047,11 +53921,11 @@ (INSTANCE ula_\|video_\|disp_enable\~0) (DELAY (ABSOLUTE - (PORT dataa (199:199:199) (242:242:242)) - (PORT datab (410:410:410) (484:484:484)) - (PORT datad (659:659:659) (717:717:717)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (PORT dataa (274:274:274) (364:364:364)) + (PORT datab (437:437:437) (511:511:511)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -54062,100 +53936,21 @@ (INSTANCE ula_\|video_\|disp_enable\~1) (DELAY (ABSOLUTE - (PORT dataa (211:211:211) (260:260:260)) - (PORT datab (207:207:207) (248:248:248)) - (PORT datad (348:348:348) (371:371:371)) + (PORT dataa (208:208:208) (254:254:254)) + (PORT datab (206:206:206) (247:247:247)) + (PORT datad (516:516:516) (530:530:530)) (IOPATH dataa combout (325:325:325) (328:328:328)) (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|border\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1527:1527:1527) (1540:1540:1540)) - (PORT asdata (537:537:537) (568:568:568)) - (PORT ena (2116:2116:2116) (2146:2146:2146)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|LessThan6\~1) + (INSTANCE ula_\|video_\|attr_prefetch\[7\]\~feeder) (DELAY (ABSOLUTE - (PORT dataa (453:453:453) (541:541:541)) - (PORT datab (461:461:461) (551:551:551)) - (PORT datac (424:424:424) (504:504:504)) - (PORT datad (416:416:416) (444:444:444)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|LessThan4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (271:271:271) (361:361:361)) - (PORT datab (273:273:273) (358:358:358)) - (PORT datad (236:236:236) (304:304:304)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|screen_en\~0) - (DELAY - (ABSOLUTE - (PORT dataa (446:446:446) (522:522:522)) - (PORT datab (461:461:461) (542:542:542)) - (PORT datac (543:543:543) (561:561:561)) - (PORT datad (646:646:646) (718:718:718)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|screen_en\~1) - (DELAY - (ABSOLUTE - (PORT dataa (683:683:683) (744:744:744)) - (PORT datab (483:483:483) (561:561:561)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|attr_prefetch\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1472:1472:1472) (1505:1505:1505)) + (PORT datad (1377:1377:1377) (1378:1378:1378)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54165,10 +53960,10 @@ (INSTANCE ula_\|video_\|Decoder0\~1) (DELAY (ABSOLUTE - (PORT dataa (1252:1252:1252) (1343:1343:1343)) - (PORT datab (984:984:984) (1066:1066:1066)) - (PORT datac (973:973:973) (1043:1043:1043)) - (PORT datad (280:280:280) (364:364:364)) + (PORT dataa (773:773:773) (856:856:856)) + (PORT datab (754:754:754) (825:825:825)) + (PORT datac (1155:1155:1155) (1215:1215:1215)) + (PORT datad (683:683:683) (750:750:750)) (IOPATH dataa combout (327:327:327) (347:347:347)) (IOPATH datab combout (331:331:331) (342:342:342)) (IOPATH datac combout (243:243:243) (241:241:241)) @@ -54178,12 +53973,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr_prefetch\[1\]) + (INSTANCE ula_\|video_\|attr_prefetch\[7\]) (DELAY (ABSOLUTE - (PORT clk (1944:1944:1944) (1969:1969:1969)) + (PORT clk (1933:1933:1933) (1959:1959:1959)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1465:1465:1465) (1443:1443:1443)) + (PORT ena (1402:1402:1402) (1376:1376:1376)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54197,10 +53992,10 @@ (INSTANCE ula_\|video_\|Decoder0\~0) (DELAY (ABSOLUTE - (PORT dataa (1252:1252:1252) (1342:1342:1342)) - (PORT datab (985:985:985) (1065:1065:1065)) - (PORT datac (974:974:974) (1042:1042:1042)) - (PORT datad (280:280:280) (364:364:364)) + (PORT dataa (764:764:764) (844:844:844)) + (PORT datab (749:749:749) (818:818:818)) + (PORT datac (1162:1162:1162) (1223:1223:1223)) + (PORT datad (687:687:687) (756:756:756)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -54208,98 +54003,14 @@ ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1536:1536:1536) (1548:1548:1548)) - (PORT asdata (1788:1788:1788) (1847:1847:1847)) - (PORT ena (1421:1421:1421) (1414:1414:1414)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|attr_prefetch\[4\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1546:1546:1546) (1544:1544:1544)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr_prefetch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1944:1944:1944) (1969:1969:1969)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1465:1465:1465) (1443:1443:1443)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1536:1536:1536) (1548:1548:1548)) - (PORT asdata (1012:1012:1012) (1085:1085:1085)) - (PORT ena (1421:1421:1421) (1414:1414:1414)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|attr_prefetch\[7\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1196:1196:1196) (1239:1239:1239)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr_prefetch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1944:1944:1944) (1969:1969:1969)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1465:1465:1465) (1443:1443:1443)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|video_\|attr\[7\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1549:1549:1549)) - (PORT asdata (1010:1010:1010) (1078:1078:1078)) - (PORT ena (1428:1428:1428) (1418:1418:1418)) + (PORT clk (1536:1536:1536) (1548:1548:1548)) + (PORT asdata (769:769:769) (839:839:839)) + (PORT ena (1446:1446:1446) (1427:1427:1427)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54313,9 +54024,9 @@ (INSTANCE ula_\|video_\|frame\[0\]\~12) (DELAY (ABSOLUTE - (PORT dataa (620:620:620) (643:643:643)) - (IOPATH dataa combout (356:356:356) (368:368:368)) + (PORT datad (587:587:587) (602:602:602)) (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -54324,7 +54035,7 @@ (INSTANCE ula_\|video_\|frame\[0\]) (DELAY (ABSOLUTE - (PORT clk (1539:1539:1539) (1551:1551:1551)) + (PORT clk (1537:1537:1537) (1549:1549:1549)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -54338,7 +54049,7 @@ (INSTANCE ula_\|video_\|frame\[1\]\~4) (DELAY (ABSOLUTE - (PORT dataa (613:613:613) (667:667:667)) + (PORT dataa (841:841:841) (891:891:891)) (PORT datab (243:243:243) (325:325:325)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH dataa cout (436:436:436) (315:315:315)) @@ -54353,9 +54064,9 @@ (INSTANCE ula_\|video_\|frame\[1\]) (DELAY (ABSOLUTE - (PORT clk (1538:1538:1538) (1551:1551:1551)) + (PORT clk (1538:1538:1538) (1550:1550:1550)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1236:1236:1236) (1237:1237:1237)) + (PORT ena (1722:1722:1722) (1716:1716:1716)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54369,9 +54080,9 @@ (INSTANCE ula_\|video_\|frame\[2\]\~6) (DELAY (ABSOLUTE - (PORT dataa (244:244:244) (331:331:331)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (243:243:243) (325:325:325)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -54383,9 +54094,9 @@ (INSTANCE ula_\|video_\|frame\[2\]) (DELAY (ABSOLUTE - (PORT clk (1538:1538:1538) (1551:1551:1551)) + (PORT clk (1538:1538:1538) (1550:1550:1550)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1236:1236:1236) (1237:1237:1237)) + (PORT ena (1722:1722:1722) (1716:1716:1716)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54399,7 +54110,7 @@ (INSTANCE ula_\|video_\|frame\[3\]\~8) (DELAY (ABSOLUTE - (PORT datab (242:242:242) (324:324:324)) + (PORT datab (243:243:243) (325:325:325)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -54413,9 +54124,9 @@ (INSTANCE ula_\|video_\|frame\[3\]) (DELAY (ABSOLUTE - (PORT clk (1538:1538:1538) (1551:1551:1551)) + (PORT clk (1538:1538:1538) (1550:1550:1550)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1236:1236:1236) (1237:1237:1237)) + (PORT ena (1722:1722:1722) (1716:1716:1716)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54429,20 +54140,30 @@ (INSTANCE ula_\|video_\|frame\[4\]\~10) (DELAY (ABSOLUTE - (PORT dataa (266:266:266) (353:353:353)) - (IOPATH dataa combout (356:356:356) (368:368:368)) + (PORT datad (688:688:688) (754:754:754)) + (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|frame\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (533:533:533) (544:544:544)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|video_\|frame\[4\]) (DELAY (ABSOLUTE - (PORT clk (1538:1538:1538) (1551:1551:1551)) + (PORT clk (1536:1536:1536) (1548:1548:1548)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1236:1236:1236) (1237:1237:1237)) + (PORT ena (1155:1155:1155) (1132:1132:1132)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54456,7 +54177,7 @@ (INSTANCE ula_\|video_\|inverted) (DELAY (ABSOLUTE - (PORT datad (372:372:372) (423:423:423)) + (PORT datad (239:239:239) (308:308:308)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -54467,8 +54188,8 @@ (INSTANCE ula_\|video_\|bits_prefetch\[6\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (1154:1154:1154) (1160:1160:1160)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT datac (1456:1456:1456) (1512:1512:1512)) + (IOPATH datac combout (243:243:243) (242:242:242)) ) ) ) @@ -54477,13 +54198,13 @@ (INSTANCE ula_\|video_\|Decoder0\~2) (DELAY (ABSOLUTE - (PORT dataa (1252:1252:1252) (1340:1340:1340)) - (PORT datab (986:986:986) (1064:1064:1064)) - (PORT datac (973:973:973) (1044:1044:1044)) - (PORT datad (279:279:279) (363:363:363)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (766:766:766) (847:847:847)) + (PORT datab (750:750:750) (821:821:821)) + (PORT datac (1157:1157:1157) (1222:1222:1222)) + (PORT datad (683:683:683) (754:754:754)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54493,9 +54214,9 @@ (INSTANCE ula_\|video_\|bits_prefetch\[6\]) (DELAY (ABSOLUTE - (PORT clk (1915:1915:1915) (1933:1933:1933)) + (PORT clk (1904:1904:1904) (1922:1922:1922)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1455:1455:1455) (1444:1444:1444)) + (PORT ena (1467:1467:1467) (1441:1441:1441)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54504,29 +54225,19 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|bits\[6\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (609:609:609) (678:678:678)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|video_\|bits\[6\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1549:1549:1549)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1428:1428:1428) (1418:1418:1418)) + (PORT clk (1536:1536:1536) (1548:1548:1548)) + (PORT asdata (929:929:929) (984:984:984)) + (PORT ena (1446:1446:1446) (1427:1427:1427)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) ) ) @@ -54535,7 +54246,7 @@ (INSTANCE ula_\|video_\|bits_prefetch\[4\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (1545:1545:1545) (1541:1541:1541)) + (PORT datad (1765:1765:1765) (1863:1863:1863)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54545,9 +54256,9 @@ (INSTANCE ula_\|video_\|bits_prefetch\[4\]) (DELAY (ABSOLUTE - (PORT clk (1915:1915:1915) (1933:1933:1933)) + (PORT clk (1904:1904:1904) (1922:1922:1922)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1455:1455:1455) (1444:1444:1444)) + (PORT ena (1467:1467:1467) (1441:1441:1441)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54561,9 +54272,9 @@ (INSTANCE ula_\|video_\|bits\[4\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1549:1549:1549)) - (PORT asdata (997:997:997) (1070:1070:1070)) - (PORT ena (1428:1428:1428) (1418:1418:1418)) + (PORT clk (1536:1536:1536) (1548:1548:1548)) + (PORT asdata (738:738:738) (812:812:812)) + (PORT ena (1446:1446:1446) (1427:1427:1427)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54577,7 +54288,7 @@ (INSTANCE ula_\|video_\|bits_prefetch\[5\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (937:937:937) (955:955:955)) + (PORT datad (826:826:826) (849:849:849)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54587,9 +54298,9 @@ (INSTANCE ula_\|video_\|bits_prefetch\[5\]) (DELAY (ABSOLUTE - (PORT clk (1915:1915:1915) (1933:1933:1933)) + (PORT clk (1904:1904:1904) (1922:1922:1922)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1455:1455:1455) (1444:1444:1444)) + (PORT ena (1467:1467:1467) (1441:1441:1441)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54603,7 +54314,7 @@ (INSTANCE ula_\|video_\|bits\[5\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (651:651:651) (725:725:725)) + (PORT datad (420:420:420) (492:492:492)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54613,9 +54324,9 @@ (INSTANCE ula_\|video_\|bits\[5\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1549:1549:1549)) + (PORT clk (1536:1536:1536) (1548:1548:1548)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1428:1428:1428) (1418:1418:1418)) + (PORT ena (1446:1446:1446) (1427:1427:1427)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54629,7 +54340,7 @@ (INSTANCE ula_\|video_\|bits_prefetch\[7\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (1201:1201:1201) (1243:1243:1243)) + (PORT datad (1377:1377:1377) (1381:1381:1381)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54639,9 +54350,9 @@ (INSTANCE ula_\|video_\|bits_prefetch\[7\]) (DELAY (ABSOLUTE - (PORT clk (1915:1915:1915) (1933:1933:1933)) + (PORT clk (1904:1904:1904) (1922:1922:1922)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1455:1455:1455) (1444:1444:1444)) + (PORT ena (1467:1467:1467) (1441:1441:1441)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54655,9 +54366,9 @@ (INSTANCE ula_\|video_\|bits\[7\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1549:1549:1549)) - (PORT asdata (1216:1216:1216) (1295:1295:1295)) - (PORT ena (1428:1428:1428) (1418:1418:1418)) + (PORT clk (1536:1536:1536) (1548:1548:1548)) + (PORT asdata (768:768:768) (840:840:840)) + (PORT ena (1446:1446:1446) (1427:1427:1427)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54671,11 +54382,11 @@ (INSTANCE ula_\|video_\|Mux0\~0) (DELAY (ABSOLUTE - (PORT dataa (385:385:385) (460:460:460)) - (PORT datab (288:288:288) (377:377:377)) - (PORT datad (636:636:636) (698:698:698)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT dataa (244:244:244) (330:330:330)) + (PORT datab (620:620:620) (682:682:682)) + (PORT datad (607:607:607) (663:663:663)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -54686,9 +54397,9 @@ (INSTANCE ula_\|video_\|Mux0\~1) (DELAY (ABSOLUTE - (PORT dataa (244:244:244) (330:330:330)) - (PORT datab (287:287:287) (374:374:374)) - (PORT datad (175:175:175) (201:201:201)) + (PORT dataa (629:629:629) (697:697:697)) + (PORT datab (418:418:418) (498:498:498)) + (PORT datad (174:174:174) (198:198:198)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -54701,7 +54412,7 @@ (INSTANCE ula_\|video_\|bits_prefetch\[2\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (883:883:883) (890:890:890)) + (PORT datad (1741:1741:1741) (1810:1810:1810)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54711,9 +54422,9 @@ (INSTANCE ula_\|video_\|bits_prefetch\[2\]) (DELAY (ABSOLUTE - (PORT clk (1915:1915:1915) (1933:1933:1933)) + (PORT clk (1904:1904:1904) (1922:1922:1922)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1455:1455:1455) (1444:1444:1444)) + (PORT ena (1467:1467:1467) (1441:1441:1441)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54727,7 +54438,7 @@ (INSTANCE ula_\|video_\|bits\[2\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (640:640:640) (711:711:711)) + (PORT datad (581:581:581) (639:639:639)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54737,9 +54448,9 @@ (INSTANCE ula_\|video_\|bits\[2\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1549:1549:1549)) + (PORT clk (1536:1536:1536) (1548:1548:1548)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1428:1428:1428) (1418:1418:1418)) + (PORT ena (1446:1446:1446) (1427:1427:1427)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54753,7 +54464,7 @@ (INSTANCE ula_\|video_\|bits_prefetch\[0\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (1463:1463:1463) (1429:1429:1429)) + (PORT datad (1510:1510:1510) (1493:1493:1493)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54763,9 +54474,9 @@ (INSTANCE ula_\|video_\|bits_prefetch\[0\]) (DELAY (ABSOLUTE - (PORT clk (1915:1915:1915) (1933:1933:1933)) + (PORT clk (1904:1904:1904) (1922:1922:1922)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1455:1455:1455) (1444:1444:1444)) + (PORT ena (1467:1467:1467) (1441:1441:1441)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54779,9 +54490,9 @@ (INSTANCE ula_\|video_\|bits\[0\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1549:1549:1549)) - (PORT asdata (978:978:978) (1047:1047:1047)) - (PORT ena (1428:1428:1428) (1418:1418:1418)) + (PORT clk (1536:1536:1536) (1548:1548:1548)) + (PORT asdata (1454:1454:1454) (1504:1504:1504)) + (PORT ena (1446:1446:1446) (1427:1427:1427)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54795,7 +54506,7 @@ (INSTANCE ula_\|video_\|bits_prefetch\[1\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (1470:1470:1470) (1502:1502:1502)) + (PORT datad (870:870:870) (874:874:874)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54805,9 +54516,9 @@ (INSTANCE ula_\|video_\|bits_prefetch\[1\]) (DELAY (ABSOLUTE - (PORT clk (1915:1915:1915) (1933:1933:1933)) + (PORT clk (1904:1904:1904) (1922:1922:1922)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1455:1455:1455) (1444:1444:1444)) + (PORT ena (1467:1467:1467) (1441:1441:1441)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54821,7 +54532,7 @@ (INSTANCE ula_\|video_\|bits\[1\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (642:642:642) (704:704:704)) + (PORT datad (402:402:402) (473:473:473)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54831,9 +54542,9 @@ (INSTANCE ula_\|video_\|bits\[1\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1549:1549:1549)) + (PORT clk (1536:1536:1536) (1548:1548:1548)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1428:1428:1428) (1418:1418:1418)) + (PORT ena (1446:1446:1446) (1427:1427:1427)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54847,7 +54558,7 @@ (INSTANCE ula_\|video_\|bits_prefetch\[3\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (1276:1276:1276) (1241:1241:1241)) + (PORT datad (1411:1411:1411) (1456:1456:1456)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54857,9 +54568,9 @@ (INSTANCE ula_\|video_\|bits_prefetch\[3\]) (DELAY (ABSOLUTE - (PORT clk (1915:1915:1915) (1933:1933:1933)) + (PORT clk (1904:1904:1904) (1922:1922:1922)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1455:1455:1455) (1444:1444:1444)) + (PORT ena (1467:1467:1467) (1441:1441:1441)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54873,9 +54584,9 @@ (INSTANCE ula_\|video_\|bits\[3\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1549:1549:1549)) - (PORT asdata (1448:1448:1448) (1474:1474:1474)) - (PORT ena (1428:1428:1428) (1418:1418:1418)) + (PORT clk (1536:1536:1536) (1548:1548:1548)) + (PORT asdata (738:738:738) (813:813:813)) + (PORT ena (1446:1446:1446) (1427:1427:1427)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54889,11 +54600,11 @@ (INSTANCE ula_\|video_\|Mux0\~2) (DELAY (ABSOLUTE - (PORT dataa (242:242:242) (328:328:328)) - (PORT datab (286:286:286) (373:373:373)) - (PORT datad (633:633:633) (694:694:694)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT dataa (629:629:629) (697:697:697)) + (PORT datab (242:242:242) (325:325:325)) + (PORT datad (594:594:594) (647:647:647)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -54904,9 +54615,9 @@ (INSTANCE ula_\|video_\|Mux0\~3) (DELAY (ABSOLUTE - (PORT dataa (243:243:243) (329:329:329)) - (PORT datab (287:287:287) (377:377:377)) - (PORT datad (175:175:175) (201:201:201)) + (PORT dataa (625:625:625) (695:695:695)) + (PORT datab (382:382:382) (456:456:456)) + (PORT datad (174:174:174) (199:199:199)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -54919,25 +54630,109 @@ (INSTANCE ula_\|video_\|cindex\[1\]\~0) (DELAY (ABSOLUTE - (PORT dataa (401:401:401) (477:477:477)) - (PORT datab (198:198:198) (237:237:237)) + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (641:641:641) (704:704:704)) (PORT datac (173:173:173) (206:206:206)) (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (337:337:337) (347:347:347)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (337:337:337) (348:348:348)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|attr_prefetch\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1766:1766:1766) (1863:1863:1863)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr_prefetch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1933:1933:1933) (1959:1959:1959)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1402:1402:1402) (1376:1376:1376)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1536:1536:1536) (1549:1549:1549)) + (PORT asdata (979:979:979) (1037:1037:1037)) + (PORT ena (1455:1455:1455) (1436:1436:1436)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|attr_prefetch\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (871:871:871) (877:877:877)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr_prefetch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1933:1933:1933) (1959:1959:1959)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1402:1402:1402) (1376:1376:1376)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1536:1536:1536) (1549:1549:1549)) + (PORT asdata (1530:1530:1530) (1600:1600:1600)) + (PORT ena (1455:1455:1455) (1436:1436:1436)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|cindex\[1\]\~1) (DELAY (ABSOLUTE - (PORT dataa (245:245:245) (332:332:332)) - (PORT datad (347:347:347) (363:363:363)) - (IOPATH dataa combout (304:304:304) (308:308:308)) + (PORT dataa (372:372:372) (412:412:412)) + (PORT datad (217:217:217) (285:285:285)) + (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -54948,13 +54743,13 @@ (INSTANCE ula_\|video_\|VGA_R\[0\]\~0) (DELAY (ABSOLUTE - (PORT dataa (398:398:398) (453:453:453)) - (PORT datab (1490:1490:1490) (1585:1585:1585)) - (PORT datac (235:235:235) (278:278:278)) - (PORT datad (180:180:180) (208:208:208)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (2638:2638:2638) (2746:2746:2746)) + (PORT datab (365:365:365) (401:401:401)) + (PORT datac (591:591:591) (601:601:601)) + (PORT datad (181:181:181) (209:209:209)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54964,8 +54759,8 @@ (INSTANCE ula_\|video_\|attr_prefetch\[6\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (1157:1157:1157) (1161:1161:1161)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT datac (1456:1456:1456) (1515:1515:1515)) + (IOPATH datac combout (243:243:243) (242:242:242)) ) ) ) @@ -54974,9 +54769,9 @@ (INSTANCE ula_\|video_\|attr_prefetch\[6\]) (DELAY (ABSOLUTE - (PORT clk (1944:1944:1944) (1969:1969:1969)) + (PORT clk (1933:1933:1933) (1959:1959:1959)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1465:1465:1465) (1443:1443:1443)) + (PORT ena (1402:1402:1402) (1376:1376:1376)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54990,9 +54785,9 @@ (INSTANCE ula_\|video_\|attr\[6\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT asdata (1216:1216:1216) (1269:1269:1269)) - (PORT ena (1638:1638:1638) (1616:1616:1616)) + (PORT clk (1536:1536:1536) (1549:1549:1549)) + (PORT asdata (967:967:967) (1031:1031:1031)) + (PORT ena (1455:1455:1455) (1436:1436:1436)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -55006,9 +54801,9 @@ (INSTANCE ula_\|video_\|VGA_B\[1\]\~0) (DELAY (ABSOLUTE - (PORT dataa (212:212:212) (261:261:261)) - (PORT datab (208:208:208) (249:249:249)) - (PORT datad (348:348:348) (371:371:371)) + (PORT dataa (208:208:208) (255:255:255)) + (PORT datab (207:207:207) (248:248:248)) + (PORT datad (516:516:516) (531:531:531)) (IOPATH dataa combout (324:324:324) (328:328:328)) (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -55021,11 +54816,11 @@ (INSTANCE ula_\|video_\|VGA_R\[1\]\~1) (DELAY (ABSOLUTE - (PORT dataa (269:269:269) (322:322:322)) - (PORT datac (391:391:391) (430:430:430)) - (PORT datad (180:180:180) (208:208:208)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (1284:1284:1284) (1303:1303:1303)) + (PORT datab (222:222:222) (262:262:262)) + (PORT datad (181:181:181) (209:209:209)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -55035,51 +54830,9 @@ (INSTANCE ula_\|border\[2\]) (DELAY (ABSOLUTE - (PORT clk (1521:1521:1521) (1535:1535:1535)) - (PORT asdata (956:956:956) (977:977:977)) - (PORT ena (812:812:812) (804:804:804)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|attr_prefetch\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (884:884:884) (889:889:889)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr_prefetch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1944:1944:1944) (1969:1969:1969)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1465:1465:1465) (1443:1443:1443)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1549:1549:1549)) - (PORT asdata (1208:1208:1208) (1265:1265:1265)) - (PORT ena (1428:1428:1428) (1418:1418:1418)) + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT asdata (1885:1885:1885) (1886:1886:1886)) + (PORT ena (1943:1943:1943) (1924:1924:1924)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -55093,7 +54846,7 @@ (INSTANCE ula_\|video_\|attr_prefetch\[5\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (935:935:935) (952:952:952)) + (PORT datad (826:826:826) (849:849:849)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -55103,9 +54856,9 @@ (INSTANCE ula_\|video_\|attr_prefetch\[5\]) (DELAY (ABSOLUTE - (PORT clk (1944:1944:1944) (1969:1969:1969)) + (PORT clk (1933:1933:1933) (1959:1959:1959)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1465:1465:1465) (1443:1443:1443)) + (PORT ena (1402:1402:1402) (1376:1376:1376)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -55119,9 +54872,51 @@ (INSTANCE ula_\|video_\|attr\[5\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1549:1549:1549)) - (PORT asdata (993:993:993) (1051:1051:1051)) - (PORT ena (1428:1428:1428) (1418:1418:1418)) + (PORT clk (1536:1536:1536) (1549:1549:1549)) + (PORT asdata (1027:1027:1027) (1097:1097:1097)) + (PORT ena (1455:1455:1455) (1436:1436:1436)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|attr_prefetch\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1744:1744:1744) (1810:1810:1810)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr_prefetch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1933:1933:1933) (1959:1959:1959)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1402:1402:1402) (1376:1376:1376)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1536:1536:1536) (1549:1549:1549)) + (PORT asdata (1392:1392:1392) (1436:1436:1436)) + (PORT ena (1455:1455:1455) (1436:1436:1436)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -55135,9 +54930,9 @@ (INSTANCE ula_\|video_\|cindex\[2\]\~2) (DELAY (ABSOLUTE - (PORT datab (242:242:242) (324:324:324)) - (PORT datad (203:203:203) (232:232:232)) - (IOPATH datab combout (306:306:306) (311:311:311)) + (PORT dataa (371:371:371) (413:413:413)) + (PORT datad (217:217:217) (286:286:286)) + (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -55148,10 +54943,10 @@ (INSTANCE ula_\|video_\|VGA_G\[0\]\~0) (DELAY (ABSOLUTE - (PORT dataa (2313:2313:2313) (2480:2480:2480)) - (PORT datab (411:411:411) (449:449:449)) - (PORT datac (384:384:384) (420:420:420)) - (PORT datad (547:547:547) (557:557:557)) + (PORT dataa (2643:2643:2643) (2790:2790:2790)) + (PORT datab (366:366:366) (401:401:401)) + (PORT datac (591:591:591) (600:600:600)) + (PORT datad (180:180:180) (208:208:208)) (IOPATH dataa combout (341:341:341) (319:319:319)) (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (242:242:242)) @@ -55164,9 +54959,9 @@ (INSTANCE ula_\|video_\|VGA_G\[1\]\~1) (DELAY (ABSOLUTE - (PORT dataa (636:636:636) (662:662:662)) - (PORT datab (221:221:221) (261:261:261)) - (PORT datad (378:378:378) (398:398:398)) + (PORT dataa (841:841:841) (856:856:856)) + (PORT datab (367:367:367) (405:405:405)) + (PORT datad (181:181:181) (210:210:210)) (IOPATH dataa combout (300:300:300) (308:308:308)) (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -55178,9 +54973,9 @@ (INSTANCE ula_\|border\[0\]) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1540:1540:1540)) - (PORT asdata (1466:1466:1466) (1519:1519:1519)) - (PORT ena (2116:2116:2116) (2146:2146:2146)) + (PORT clk (1515:1515:1515) (1528:1528:1528)) + (PORT asdata (3345:3345:3345) (3552:3552:3552)) + (PORT ena (2394:2394:2394) (2437:2437:2437)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -55194,7 +54989,7 @@ (INSTANCE ula_\|video_\|attr_prefetch\[0\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (1462:1462:1462) (1430:1430:1430)) + (PORT datad (1513:1513:1513) (1495:1495:1495)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -55204,9 +54999,9 @@ (INSTANCE ula_\|video_\|attr_prefetch\[0\]) (DELAY (ABSOLUTE - (PORT clk (1944:1944:1944) (1969:1969:1969)) + (PORT clk (1933:1933:1933) (1959:1959:1959)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1465:1465:1465) (1443:1443:1443)) + (PORT ena (1402:1402:1402) (1376:1376:1376)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -55220,7 +55015,7 @@ (INSTANCE ula_\|video_\|attr\[0\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (839:839:839) (888:888:888)) + (PORT datad (624:624:624) (687:687:687)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -55232,7 +55027,7 @@ (ABSOLUTE (PORT clk (1536:1536:1536) (1548:1548:1548)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1421:1421:1421) (1414:1414:1414)) + (PORT ena (1446:1446:1446) (1427:1427:1427)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -55246,7 +55041,7 @@ (INSTANCE ula_\|video_\|attr_prefetch\[3\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (1276:1276:1276) (1242:1242:1242)) + (PORT datad (1412:1412:1412) (1456:1456:1456)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -55256,9 +55051,9 @@ (INSTANCE ula_\|video_\|attr_prefetch\[3\]) (DELAY (ABSOLUTE - (PORT clk (1944:1944:1944) (1969:1969:1969)) + (PORT clk (1933:1933:1933) (1959:1959:1959)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1465:1465:1465) (1443:1443:1443)) + (PORT ena (1402:1402:1402) (1376:1376:1376)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -55272,9 +55067,9 @@ (INSTANCE ula_\|video_\|attr\[3\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1549:1549:1549)) - (PORT asdata (965:965:965) (1040:1040:1040)) - (PORT ena (1428:1428:1428) (1418:1418:1418)) + (PORT clk (1536:1536:1536) (1548:1548:1548)) + (PORT asdata (772:772:772) (846:846:846)) + (PORT ena (1446:1446:1446) (1427:1427:1427)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -55288,9 +55083,9 @@ (INSTANCE ula_\|video_\|cindex\[0\]\~3) (DELAY (ABSOLUTE - (PORT datab (384:384:384) (459:459:459)) - (PORT datad (204:204:204) (232:232:232)) - (IOPATH datab combout (306:306:306) (311:311:311)) + (PORT dataa (244:244:244) (330:330:330)) + (PORT datad (195:195:195) (221:221:221)) + (IOPATH dataa combout (304:304:304) (308:308:308)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -55301,13 +55096,13 @@ (INSTANCE ula_\|video_\|VGA_B\[0\]\~1) (DELAY (ABSOLUTE - (PORT dataa (399:399:399) (453:453:453)) - (PORT datab (1662:1662:1662) (1745:1745:1745)) - (PORT datac (233:233:233) (279:279:279)) - (PORT datad (334:334:334) (354:354:354)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (588:588:588) (614:614:614)) + (PORT datab (2087:2087:2087) (2265:2265:2265)) + (PORT datac (317:317:317) (337:337:337)) + (PORT datad (181:181:181) (209:209:209)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -55317,9 +55112,9 @@ (INSTANCE ula_\|video_\|VGA_B\[1\]\~2) (DELAY (ABSOLUTE - (PORT dataa (269:269:269) (323:323:323)) - (PORT datac (391:391:391) (429:429:429)) - (PORT datad (340:340:340) (359:359:359)) + (PORT dataa (586:586:586) (617:617:617)) + (PORT datac (561:561:561) (576:576:576)) + (PORT datad (180:180:180) (208:208:208)) (IOPATH dataa combout (304:304:304) (307:307:307)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -55331,11 +55126,11 @@ (INSTANCE ula_\|video_\|Equal0\~2) (DELAY (ABSOLUTE - (PORT dataa (681:681:681) (753:753:753)) - (PORT datab (282:282:282) (364:364:364)) - (PORT datad (645:645:645) (715:715:715)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT datab (674:674:674) (739:739:739)) + (PORT datac (1157:1157:1157) (1216:1216:1216)) + (PORT datad (980:980:980) (1067:1067:1067)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -55345,7 +55140,7 @@ (INSTANCE ula_\|video_\|VGA_HS\~_Duplicate_1) (DELAY (ABSOLUTE - (PORT clk (1536:1536:1536) (1548:1548:1548)) + (PORT clk (1537:1537:1537) (1549:1549:1549)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -55359,11 +55154,11 @@ (INSTANCE ula_\|video_\|Selector0\~0) (DELAY (ABSOLUTE - (PORT dataa (1030:1030:1030) (1035:1035:1035)) - (PORT datab (228:228:228) (270:270:270)) - (PORT datad (571:571:571) (575:575:575)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (575:575:575) (602:602:602)) + (PORT datad (326:326:326) (352:352:352)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -55375,7 +55170,7 @@ (DELAY (ABSOLUTE (PORT clk (1509:1509:1509) (1531:1531:1531)) - (PORT d (1715:1715:1715) (1721:1721:1721)) + (PORT d (1732:1732:1732) (1749:1749:1749)) (IOPATH (posedge clk) q (586:586:586) (589:589:589)) ) ) @@ -55389,7 +55184,7 @@ (INSTANCE ula_\|video_\|VGA_VS\~_Duplicate_1) (DELAY (ABSOLUTE - (PORT clk (1539:1539:1539) (1551:1551:1551)) + (PORT clk (1538:1538:1538) (1550:1550:1550)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -55403,11 +55198,11 @@ (INSTANCE ula_\|video_\|Selector1\~0) (DELAY (ABSOLUTE - (PORT dataa (620:620:620) (642:642:642)) - (PORT datab (1174:1174:1174) (1179:1179:1179)) - (PORT datad (691:691:691) (762:762:762)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (304:304:304) (311:311:311)) + (PORT dataa (1099:1099:1099) (1106:1106:1106)) + (PORT datab (1453:1453:1453) (1488:1488:1488)) + (PORT datad (1108:1108:1108) (1129:1129:1129)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -55419,7 +55214,7 @@ (DELAY (ABSOLUTE (PORT clk (1507:1507:1507) (1529:1529:1529)) - (PORT d (1805:1805:1805) (1839:1839:1839)) + (PORT d (1320:1320:1320) (1349:1349:1349)) (IOPATH (posedge clk) q (586:586:586) (589:589:589)) ) ) @@ -55433,7 +55228,7 @@ (INSTANCE z80_\|memory_ifc_\|q1\~feeder) (DELAY (ABSOLUTE - (PORT datad (620:620:620) (667:667:667)) + (PORT datad (252:252:252) (325:325:325)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -55443,10 +55238,10 @@ (INSTANCE z80_\|memory_ifc_\|q1) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1553:1553:1553)) + (PORT clk (1523:1523:1523) (1537:1537:1537)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1592:1592:1592) (1568:1568:1568)) - (PORT ena (1483:1483:1483) (1473:1473:1473)) + (PORT clrn (1567:1567:1567) (1548:1548:1548)) + (PORT ena (1722:1722:1722) (1695:1695:1695)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -55461,10 +55256,10 @@ (INSTANCE z80_\|memory_ifc_\|q2) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1553:1553:1553)) + (PORT clk (1523:1523:1523) (1537:1537:1537)) (PORT asdata (560:560:560) (634:634:634)) - (PORT clrn (1592:1592:1592) (1568:1568:1568)) - (PORT ena (1483:1483:1483) (1473:1473:1473)) + (PORT clrn (1567:1567:1567) (1548:1548:1548)) + (PORT ena (1722:1722:1722) (1695:1695:1695)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -55479,7 +55274,7 @@ (INSTANCE z80_\|memory_ifc_\|nRFSH_out\~0) (DELAY (ABSOLUTE - (PORT datad (621:621:621) (666:666:666)) + (PORT datad (252:252:252) (326:326:326)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -55490,9 +55285,9 @@ (INSTANCE z80_\|memory_ifc_\|nM1_out) (DELAY (ABSOLUTE - (PORT datac (1282:1282:1282) (1346:1346:1346)) - (PORT datad (621:621:621) (669:669:669)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (2533:2533:2533) (2712:2712:2712)) + (PORT datad (251:251:251) (327:327:327)) + (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -55502,11 +55297,11 @@ (INSTANCE ula_\|beep\~0) (DELAY (ABSOLUTE - (PORT datab (1714:1714:1714) (1839:1839:1839)) - (PORT datac (3217:3217:3217) (3502:3502:3502)) - (PORT datad (1247:1247:1247) (1342:1342:1342)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (3786:3786:3786) (4218:4218:4218)) + (PORT datab (1147:1147:1147) (1179:1179:1179)) + (PORT datad (1264:1264:1264) (1278:1278:1278)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -55516,9 +55311,9 @@ (INSTANCE ula_\|beep) (DELAY (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT clk (1510:1510:1510) (1524:1524:1524)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (2564:2564:2564) (2572:2572:2572)) + (PORT ena (2464:2464:2464) (2441:2441:2441)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) diff --git a/simulation/modelsim/spectrum_min_1200mv_0c_fast.vo b/simulation/modelsim/spectrum_min_1200mv_0c_fast.vo index 1f3d9fd..1d942e6 100644 --- a/simulation/modelsim/spectrum_min_1200mv_0c_fast.vo +++ b/simulation/modelsim/spectrum_min_1200mv_0c_fast.vo @@ -16,7 +16,7 @@ // PROGRAM "Quartus II 32-bit" // VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" -// DATE "04/01/2022 18:55:51" +// DATE "04/02/2022 15:53:44" // // Device: Altera EP4CE22F17C6 Package FBGA256 @@ -56,8 +56,8 @@ input CLOCK_50; input [1:0] KEY; input PS2_CLK; input PS2_DAT; -output I2C_SCLK; -output I2C_SDAT; +inout I2C_SCLK; +inout I2C_SDAT; output AUD_XCK; output AUD_ADCLRCK; output AUD_DACLRCK; @@ -178,786 +178,67 @@ wire \SW[2]~input_o ; wire \ula_|clocks_|clk_cpu~0_combout ; wire \ula_|clocks_|clk_cpu~q ; wire \ula_|clocks_|clk_cpu~clkctrl_outclk ; -wire \z80_|sequencer_|DFFE_M1_ff~0_combout ; -wire \z80_|sequencer_|ena_M~combout ; +wire \z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ; +wire \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ; wire \KEY[1]~input_o ; wire \z80_|interrupts_|nmi_armed~feeder_combout ; wire \z80_|interrupts_|SYNTHESIZED_WIRE_9~combout ; wire \z80_|interrupts_|nmi_armed~q ; wire \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder_combout ; -wire \z80_|execute_|ctl_eval_cond~0_combout ; -wire \z80_|execute_|ixy_d~4_combout ; +wire \z80_|sequencer_|DFFE_M2_ff~0_combout ; +wire \z80_|sequencer_|DFFE_M2_ff~q ; wire \z80_|sequencer_|DFFE_M3_ff~0_combout ; wire \z80_|sequencer_|DFFE_M3_ff~q ; -wire \z80_|execute_|fIOWrite~1_combout ; wire \z80_|sequencer_|DFFE_M4_ff~0_combout ; wire \z80_|sequencer_|DFFE_M4_ff~q ; -wire \z80_|pla_decode_|Equal32~0_combout ; -wire \z80_|resets_|SYNTHESIZED_WIRE_11~combout ; -wire \z80_|decode_state_|table_xx~0_combout ; -wire \z80_|pla_decode_|Equal1~7_combout ; -wire \z80_|pla_decode_|Equal2~0_combout ; -wire \z80_|pla_decode_|Equal36~0_combout ; -wire \z80_|execute_|ctl_state_tbl_cb_set~combout ; -wire \z80_|execute_|ctl_state_tbl_we~8_combout ; -wire \z80_|decode_state_|DFFE_instCB~q ; -wire \z80_|pla_decode_|Equal52~0_combout ; -wire \z80_|pla_decode_|Equal2~1_combout ; -wire \z80_|execute_|ctl_state_tbl_ed_set~combout ; -wire \z80_|decode_state_|DFFE_instED~q ; -wire \z80_|pla_decode_|Equal13~0_combout ; -wire \z80_|pla_decode_|Equal33~0_combout ; -wire \z80_|execute_|ctl_im_we~combout ; -wire \z80_|pla_decode_|Equal49~0_combout ; -wire \z80_|pla_decode_|Equal33~1_combout ; -wire \z80_|pla_decode_|Equal6~0_combout ; -wire \z80_|execute_|ctl_mRead~14_combout ; -wire \z80_|pla_decode_|Equal12~0_combout ; -wire \z80_|execute_|ctl_sw_1d~8_combout ; -wire \z80_|nM1_int~2_combout ; -wire \z80_|execute_|ctl_sw_1d~5_combout ; -wire \z80_|pla_decode_|Equal3~0_combout ; -wire \z80_|execute_|ctl_mRead~4_combout ; -wire \z80_|execute_|ixy_d~7_combout ; -wire \z80_|execute_|ctl_state_alu~4_combout ; -wire \z80_|execute_|ctl_sw_1d~4_combout ; -wire \z80_|pla_decode_|Equal40~1_combout ; -wire \z80_|pla_decode_|Equal39~0_combout ; -wire \z80_|execute_|ctl_bus_db_oe~1_combout ; -wire \z80_|pla_decode_|Equal13~1_combout ; -wire \z80_|pla_decode_|Equal13~2_combout ; -wire \z80_|pla_decode_|Equal3~2_combout ; -wire \z80_|execute_|ctl_state_iy_set~2_combout ; -wire \z80_|execute_|ixy_d~8_combout ; -wire \z80_|execute_|ixy_d~6_combout ; -wire \z80_|execute_|ixy_d~9_combout ; -wire \z80_|execute_|ixy_d~12_combout ; -wire \z80_|execute_|ixy_d~10_combout ; -wire \z80_|pla_decode_|Equal44~0_combout ; -wire \z80_|execute_|ixy_d~16_combout ; -wire \z80_|execute_|ixy_d~13_combout ; -wire \z80_|pla_decode_|Equal50~0_combout ; -wire \z80_|pla_decode_|Equal33~2_combout ; -wire \z80_|execute_|ixy_d~17_combout ; -wire \z80_|execute_|ixy_d~5_combout ; -wire \z80_|execute_|ixy_d~14_combout ; -wire \z80_|execute_|ixy_d~11_combout ; -wire \z80_|execute_|ixy_d~15_combout ; -wire \z80_|execute_|ctl_state_ixiy_we~2_combout ; -wire \z80_|decode_state_|DFFE_instIY1~q ; -wire \z80_|execute_|ctl_ir_we~5_combout ; -wire \z80_|execute_|ctl_ir_we~14_combout ; -wire \z80_|execute_|ctl_mWrite~2_combout ; -wire \z80_|execute_|ctl_mWrite~16_combout ; -wire \z80_|execute_|ctl_flags_alu~18_combout ; -wire \z80_|execute_|ctl_mRead~26_combout ; -wire \z80_|execute_|ctl_mRead~27_combout ; -wire \z80_|execute_|ctl_bus_db_oe~7_combout ; -wire \z80_|execute_|ctl_sw_2d~5_combout ; -wire \z80_|execute_|ctl_mRead~18_combout ; -wire \z80_|pla_decode_|Equal55~0_combout ; -wire \z80_|execute_|comb~1_combout ; -wire \z80_|execute_|ctl_mRead~15_combout ; -wire \z80_|execute_|ctl_mRead~17_combout ; -wire \z80_|execute_|ctl_reg_in_hi~5_combout ; -wire \z80_|execute_|ctl_mRead~9_combout ; -wire \z80_|pla_decode_|Equal9~0_combout ; -wire \z80_|execute_|ctl_mRead~10_combout ; -wire \z80_|execute_|ctl_mRead~8_combout ; -wire \z80_|execute_|ctl_mRead~20_combout ; -wire \z80_|pla_decode_|Equal12~1_combout ; -wire \z80_|pla_decode_|Equal9~1_combout ; -wire \z80_|pla_decode_|Equal25~0_combout ; -wire \z80_|execute_|ctl_mRead~21_combout ; -wire \z80_|execute_|ctl_state_alu~6_combout ; -wire \z80_|pla_decode_|Equal19~0_combout ; -wire \z80_|pla_decode_|Equal1~4_combout ; -wire \z80_|pla_decode_|Equal29~0_combout ; -wire \z80_|pla_decode_|Equal24~1_combout ; -wire \z80_|pla_decode_|Equal34~0_combout ; -wire \z80_|pla_decode_|Equal37~0_combout ; -wire \z80_|pla_decode_|Equal35~0_combout ; -wire \z80_|pla_decode_|Equal38~2_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~2_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~3_combout ; -wire \z80_|execute_|comb~0_combout ; -wire \z80_|pla_decode_|Equal47~0_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~4_combout ; -wire \z80_|execute_|ctl_mRead~22_combout ; -wire \z80_|execute_|ctl_mRead~24_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ; -wire \z80_|execute_|ctl_reg_in_hi~6_combout ; -wire \z80_|pla_decode_|Equal6~1_combout ; -wire \z80_|execute_|ctl_mRead~16_combout ; wire \z80_|sequencer_|M5~0_combout ; wire \z80_|sequencer_|M5~q ; -wire \z80_|execute_|ctl_reg_in_hi~2_combout ; -wire \z80_|execute_|setM1~29_combout ; -wire \z80_|execute_|ctl_mRead~25_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~6_combout ; -wire \z80_|execute_|ctl_ir_we~7_combout ; -wire \z80_|pla_decode_|Equal52~1_combout ; -wire \z80_|execute_|ctl_state_alu~14_combout ; -wire \z80_|execute_|ctl_state_alu~8_combout ; -wire \z80_|pla_decode_|Equal24~0_combout ; -wire \z80_|reg_control_|reg_sel_pc~0_combout ; -wire \z80_|reg_control_|reg_sel_pc~1_combout ; -wire \z80_|reg_control_|reg_sel_pc~2_combout ; -wire \z80_|execute_|fMRead~17_combout ; -wire \z80_|execute_|ctl_mRead~6_combout ; -wire \z80_|pla_decode_|Equal11~0_combout ; -wire \z80_|pla_decode_|Equal10~0_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~9_combout ; -wire \z80_|execute_|ctl_sw_2d~4_combout ; -wire \z80_|execute_|ctl_ir_we~15_combout ; -wire \z80_|execute_|fMRead~16_combout ; -wire \z80_|execute_|ctl_ir_we~9_combout ; -wire \z80_|pla_decode_|Equal46~0_combout ; -wire \z80_|execute_|ctl_ir_we~10_combout ; -wire \z80_|execute_|ctl_flags_alu~17_combout ; -wire \z80_|execute_|ctl_flags_alu~6_combout ; -wire \z80_|execute_|ctl_ir_we~6_combout ; -wire \z80_|execute_|ctl_ir_we~8_combout ; -wire \z80_|execute_|ctl_flags_alu~16_combout ; -wire \z80_|execute_|ctl_reg_in_hi~3_combout ; -wire \z80_|execute_|ctl_mWrite~8_combout ; -wire \z80_|execute_|fMRead~18_combout ; -wire \z80_|execute_|fMRead~19_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~16_combout ; -wire \z80_|execute_|ctl_mRead~36_combout ; -wire \z80_|execute_|ctl_alu_op_low~9_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~44_combout ; -wire \z80_|execute_|ctl_mRead~11_combout ; -wire \z80_|execute_|ctl_sw_2d~6_combout ; -wire \z80_|execute_|ctl_sw_2d~7_combout ; -wire \z80_|execute_|ctl_mWrite~7_combout ; -wire \z80_|execute_|ctl_ir_we~11_combout ; -wire \z80_|execute_|ctl_ir_we~12_combout ; -wire \z80_|execute_|ctl_flags_sz_we~0_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ; -wire \z80_|execute_|ctl_sw_2d~8_combout ; -wire \z80_|execute_|ctl_sw_2d~9_combout ; -wire \z80_|execute_|ctl_sw_1d~6_combout ; -wire \z80_|execute_|ctl_sw_1d~7_combout ; -wire \z80_|execute_|ctl_alu_op_low~8_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ; -wire \z80_|execute_|ctl_reg_out_hi~4_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~15_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~38_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_zero~combout ; -wire \z80_|alu_|db_low[2]~4_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~14_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ; -wire \z80_|execute_|ctl_sw_4u~1_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~5_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~30_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~29_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~31_combout ; -wire \z80_|pla_decode_|Equal69~0_combout ; -wire \z80_|pla_decode_|Equal1~5_combout ; -wire \z80_|execute_|ctl_alu_op_low~14_combout ; -wire \z80_|execute_|ctl_alu_op_low~12_combout ; -wire \z80_|pla_decode_|Equal56~0_combout ; -wire \z80_|execute_|ctl_alu_op_low~11_combout ; -wire \z80_|execute_|nextM~2_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~16_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~4_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~5_combout ; -wire \z80_|execute_|ctl_alu_oe~3_combout ; -wire \z80_|execute_|ctl_alu_op_low~15_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~8_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~9_combout ; -wire \z80_|execute_|ctl_alu_core_R~3_combout ; -wire \z80_|execute_|ctl_alu_core_R~4_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~10_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~11_combout ; -wire \z80_|pla_decode_|Equal48~0_combout ; -wire \z80_|execute_|ctl_flags_hf2_we~combout ; -wire \z80_|execute_|ctl_alu_shift_oe~41_combout ; -wire \z80_|execute_|ctl_flags_xy_we~18_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~17_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~19_combout ; -wire \z80_|execute_|ctl_iorw~10_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~18_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~20_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~13_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~9_combout ; -wire \z80_|execute_|ctl_bus_db_oe~3_combout ; -wire \z80_|pla_decode_|Equal20~0_combout ; -wire \z80_|pla_decode_|Equal68~2_combout ; -wire \z80_|execute_|ctl_flags_bus~14_combout ; -wire \z80_|execute_|ctl_alu_op_low~13_combout ; -wire \z80_|execute_|ctl_flags_bus~15_combout ; -wire \z80_|execute_|ctl_flags_bus~11_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~11_combout ; -wire \z80_|execute_|ctl_flags_bus~10_combout ; -wire \z80_|execute_|ctl_flags_bus~8_combout ; -wire \z80_|execute_|ctl_flags_bus~9_combout ; -wire \z80_|execute_|ctl_flags_bus~12_combout ; -wire \z80_|execute_|ctl_flags_xy_we~11_combout ; -wire \z80_|execute_|ctl_flags_xy_we~12_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~6_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~7_combout ; -wire \z80_|execute_|ctl_ir_we~4_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~8_combout ; -wire \z80_|execute_|ctl_bus_db_oe~0_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~12_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~13_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~14_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_bus~15_combout ; -wire \z80_|execute_|ctl_66_oe~2_combout ; -wire \z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ; -wire \z80_|execute_|ctl_alu_op1_sel_zero~5_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_zero~4_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_zero~combout ; -wire \z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_lq~combout ; -wire \z80_|execute_|ctl_alu_op_low~10_combout ; -wire \z80_|execute_|fMWrite~11_combout ; -wire \z80_|execute_|ctl_alu_op_low~21_combout ; +wire \z80_|execute_|ixy_d~5_combout ; wire \z80_|execute_|ctl_alu_op_low~22_combout ; -wire \z80_|execute_|ctl_alu_op_low~16_combout ; -wire \z80_|execute_|ctl_alu_op_low~17_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ; -wire \z80_|execute_|ctl_reg_gp_sel~36_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~4_combout ; -wire \z80_|execute_|ctl_state_alu~5_combout ; -wire \z80_|execute_|ctl_alu_op_low~18_combout ; -wire \z80_|execute_|ctl_alu_op_low~19_combout ; -wire \z80_|execute_|ctl_alu_op_low~33_combout ; -wire \z80_|execute_|ctl_alu_op_low~20_combout ; -wire \z80_|execute_|ctl_alu_op_low~23_combout ; -wire \z80_|execute_|ctl_alu_op_low~24_combout ; -wire \z80_|execute_|ctl_alu_op_low~25_combout ; -wire \z80_|execute_|ctl_alu_op_low~34_combout ; -wire \z80_|execute_|ctl_alu_op_low~combout ; -wire \z80_|execute_|ctl_alu_shift_oe~40_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~37_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~39_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~46_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~42_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~21_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~45_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~22_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~23_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~24_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~25_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~14_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~26_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~27_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~28_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~10_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~11_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~32_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~33_combout ; -wire \z80_|execute_|ctl_reg_use_sp~0_combout ; -wire \z80_|execute_|ctl_reg_use_sp~1_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~12_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~47_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~34_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~35_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~36_combout ; -wire \z80_|execute_|ctl_alu_shift_oe~43_combout ; -wire \z80_|execute_|ctl_reg_in_lo~9_combout ; -wire \z80_|execute_|ctl_alu_op1_oe~0_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ; -wire \z80_|execute_|ctl_alu_op1_oe~1_combout ; -wire \z80_|execute_|ctl_flags_xy_we~8_combout ; -wire \z80_|execute_|ctl_flags_xy_we~9_combout ; -wire \z80_|pla_decode_|Equal8~0_combout ; -wire \z80_|execute_|ctl_flags_alu~9_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~4_combout ; -wire \z80_|execute_|ctl_flags_sz_we~3_combout ; -wire \z80_|pla_decode_|Equal11~1_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ; -wire \z80_|execute_|ctl_flags_alu~10_combout ; -wire \z80_|execute_|ctl_flags_alu~11_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ; -wire \z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ; -wire \z80_|execute_|ctl_flags_use_cf2~13_combout ; -wire \z80_|execute_|ctl_flags_cf_we~7_combout ; -wire \z80_|execute_|ctl_pf_sel[0]~2_combout ; -wire \z80_|execute_|ctl_alu_oe~2_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~25_combout ; -wire \z80_|execute_|ctl_flags_hf_we~5_combout ; -wire \z80_|execute_|ctl_flags_pf_we~10_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ; -wire \z80_|execute_|ctl_flags_pf_we~2_combout ; -wire \z80_|execute_|ctl_flags_pf_we~3_combout ; -wire \z80_|execute_|ctl_flags_xy_we~17_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~5_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~6_combout ; -wire \z80_|execute_|ctl_flags_xy_we~10_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ; -wire \z80_|execute_|ctl_state_alu~7_combout ; -wire \z80_|execute_|ctl_flags_sz_we~1_combout ; -wire \z80_|execute_|ctl_flags_cf_we~2_combout ; -wire \z80_|execute_|ctl_alu_core_S~6_combout ; -wire \z80_|execute_|ctl_alu_core_S~7_combout ; -wire \z80_|execute_|ctl_alu_core_S~4_combout ; -wire \z80_|execute_|ctl_alu_core_S~5_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ; -wire \z80_|execute_|ctl_alu_res_oe~0_combout ; -wire \z80_|execute_|ctl_alu_oe~15_combout ; -wire \z80_|execute_|ctl_alu_res_oe~1_combout ; -wire \z80_|execute_|ctl_alu_res_oe~2_combout ; -wire \z80_|execute_|ctl_alu_op2_oe~0_combout ; -wire \z80_|alu_|db_high[3]~2_combout ; -wire \z80_|alu_|db_high[3]~3_combout ; -wire \z80_|alu_|db_low[2]~24_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~7_combout ; -wire \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ; -wire \z80_|execute_|ctl_reg_in_hi~8_combout ; -wire \z80_|execute_|ctl_alu_oe~8_combout ; -wire \z80_|execute_|ctl_alu_oe~4_combout ; -wire \z80_|execute_|ctl_mWrite~9_combout ; -wire \z80_|execute_|ctl_alu_core_S~10_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~43_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~26_combout ; -wire \z80_|execute_|ctl_bus_db_we~5_combout ; -wire \z80_|execute_|ctl_alu_oe~9_combout ; -wire \z80_|execute_|ctl_alu_oe~11_combout ; -wire \z80_|execute_|ctl_alu_oe~5_combout ; -wire \z80_|execute_|ctl_alu_core_S~11_combout ; -wire \z80_|execute_|ctl_alu_oe~6_combout ; -wire \z80_|execute_|ctl_alu_oe~7_combout ; -wire \z80_|execute_|ctl_alu_oe~12_combout ; -wire \z80_|execute_|ctl_alu_oe~13_combout ; -wire \z80_|execute_|ctl_alu_oe~14_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~24_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~27_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ; -wire \z80_|execute_|ctl_reg_out_hi~8_combout ; -wire \z80_|execute_|setM1~54_combout ; -wire \z80_|execute_|ctl_sw_2u~1_combout ; -wire \z80_|execute_|ctl_sw_2u~4_combout ; -wire \z80_|execute_|ctl_sw_2u~5_combout ; -wire \z80_|execute_|ctl_sw_2u~6_combout ; -wire \z80_|execute_|ctl_inc_cy~35_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ; -wire \z80_|execute_|ctl_mWrite~6_combout ; -wire \z80_|execute_|ctl_sw_2u~2_combout ; -wire \z80_|execute_|ctl_sw_2u~0_combout ; -wire \z80_|execute_|ctl_sw_2u~3_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ; -wire \z80_|execute_|ctl_reg_out_lo~2_combout ; -wire \z80_|execute_|rsel3~combout ; -wire \z80_|execute_|ctl_reg_out_hi~5_combout ; -wire \z80_|execute_|ctl_reg_out_hi~6_combout ; -wire \z80_|execute_|ctl_reg_out_hi~7_combout ; -wire \z80_|execute_|rsel0~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ; -wire \z80_|execute_|ctl_reg_out_lo~6_combout ; -wire \z80_|execute_|ctl_reg_out_lo~7_combout ; -wire \z80_|execute_|ctl_iorw~11_combout ; -wire \z80_|execute_|ctl_sw_2d~10_combout ; -wire \z80_|execute_|ctl_sw_2d~14_combout ; -wire \z80_|execute_|ctl_sw_2d~11_combout ; -wire \z80_|execute_|ctl_sw_2d~12_combout ; -wire \z80_|execute_|ctl_sw_2d~13_combout ; -wire \z80_|execute_|ctl_66_oe~combout ; -wire \z80_|execute_|ctl_inc_cy~34_combout ; -wire \z80_|execute_|ctl_apin_mux~0_combout ; -wire \z80_|execute_|ctl_sw_4u~5_combout ; -wire \z80_|execute_|ctl_inc_cy~75_combout ; -wire \z80_|execute_|ctl_inc_cy~76_combout ; -wire \z80_|pla_decode_|Equal4~0_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~48_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~46_combout ; -wire \z80_|execute_|ctl_inc_cy~53_combout ; -wire \z80_|execute_|ctl_inc_cy~92_combout ; -wire \z80_|pla_decode_|Equal19~1_combout ; -wire \z80_|execute_|ctl_sw_4u~0_combout ; -wire \z80_|execute_|ctl_inc_cy~38_combout ; -wire \z80_|execute_|ctl_inc_cy~93_combout ; -wire \z80_|execute_|ctl_inc_cy~39_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~24_combout ; -wire \z80_|execute_|ctl_reg_gp_we~1_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ; -wire \z80_|execute_|ctl_bus_inc_oe~44_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~5_combout ; -wire \z80_|execute_|ctl_reg_gp_we~0_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ; -wire \z80_|execute_|ctl_sw_4u~2_combout ; -wire \z80_|execute_|ctl_sw_4u~3_combout ; -wire \z80_|execute_|fMRead~3_combout ; -wire \z80_|execute_|ctl_sw_4u~4_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ; -wire \z80_|execute_|ctl_reg_sel_wz~15_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ; -wire \z80_|execute_|ctl_inc_cy~94_combout ; -wire \z80_|execute_|ctl_inc_cy~87_combout ; -wire \z80_|execute_|ctl_inc_cy~42_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~16_combout ; -wire \z80_|execute_|ctl_sw_4u~6_combout ; -wire \z80_|pla_decode_|Equal2~2_combout ; -wire \z80_|pla_decode_|Equal1~6_combout ; -wire \z80_|reg_control_|bank_exx~2_combout ; -wire \z80_|reg_control_|bank_exx~q ; -wire \z80_|reg_control_|bank_hl_de1~0_combout ; -wire \z80_|reg_control_|bank_hl_de1~q ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~10_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~11_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~12_combout ; -wire \z80_|execute_|ctl_mRead~7_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~9_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~37_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~13_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ; -wire \z80_|execute_|fMWrite~3_combout ; -wire \z80_|execute_|ctl_flags_bus~5_combout ; -wire \z80_|execute_|fMRead~2_combout ; -wire \z80_|execute_|ctl_mRead~19_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~7_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~8_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~14_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~16_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~15_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~17_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~19_combout ; -wire \z80_|execute_|ctl_reg_use_sp~2_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~47_combout ; -wire \z80_|execute_|ctl_reg_use_sp~3_combout ; -wire \z80_|execute_|ctl_sw_1d~9_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~21_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~20_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~22_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~18_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~23_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~28_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ; -wire \z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ; -wire \z80_|execute_|ctl_flags_hf_cpl~14_combout ; -wire \z80_|execute_|ctl_flags_hf_cpl~10_combout ; -wire \z80_|execute_|setM1~47_combout ; -wire \z80_|execute_|setM1~48_combout ; -wire \z80_|execute_|ctl_al_we~13_combout ; -wire \z80_|execute_|ctl_flags_oe~0_combout ; -wire \z80_|execute_|ctl_flags_oe~1_combout ; -wire \z80_|execute_|ctl_reg_in_hi~13_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~29_combout ; -wire \z80_|execute_|ctl_inc_cy~40_combout ; -wire \z80_|execute_|ctl_inc_dec~2_combout ; -wire \z80_|execute_|ctl_inc_dec~12_combout ; -wire \z80_|execute_|ctl_inc_cy~43_combout ; -wire \z80_|execute_|ctl_inc_dec~5_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~4_combout ; -wire \z80_|execute_|fMRead~6_combout ; -wire \z80_|execute_|fMRead~7_combout ; -wire \z80_|execute_|fMRead~8_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~26_combout ; -wire \z80_|execute_|ctl_state_alu~13_combout ; -wire \z80_|execute_|ctl_state_alu~10_combout ; -wire \z80_|execute_|ctl_state_alu~11_combout ; -wire \z80_|execute_|ctl_state_alu~9_combout ; -wire \z80_|pla_decode_|Equal62~2_combout ; -wire \z80_|execute_|ctl_flags_pf_we~4_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ; -wire \z80_|pla_decode_|Equal64~0_combout ; -wire \z80_|execute_|ctl_pf_sel[0]~3_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ; -wire \z80_|execute_|ctl_state_alu~15_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~25_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~30_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[1]~31_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~33_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~34_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo~20_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~32_combout ; -wire \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ; -wire \z80_|reg_control_|reg_sel_de2~5_combout ; -wire \z80_|reg_control_|reg_sel_de2~6_combout ; -wire \z80_|reg_control_|reg_sel_hl~0_combout ; -wire \z80_|reg_control_|bank_hl_de2~0_combout ; -wire \z80_|reg_control_|bank_hl_de2~q ; -wire \z80_|reg_control_|reg_sel_hl2~0_combout ; -wire \z80_|execute_|ctl_reg_in_hi~7_combout ; -wire \z80_|execute_|ctl_reg_gp_we~4_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ; -wire \z80_|execute_|ctl_reg_gp_we~3_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~13_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5~combout ; -wire \z80_|execute_|ctl_reg_gp_we~2_combout ; -wire \z80_|execute_|ctl_reg_gp_we~5_combout ; -wire \z80_|execute_|ctl_reg_gp_we~6_combout ; -wire \z80_|execute_|ctl_al_we~14_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~32_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ; -wire \z80_|execute_|setM1~40_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~93_combout ; -wire \z80_|reg_control_|reg_sel_de~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ; -wire \z80_|execute_|ctl_reg_in_hi~9_combout ; -wire \z80_|execute_|ctl_reg_in_hi~10_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~19_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ; -wire \z80_|execute_|ctl_reg_in_lo~8_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~19_combout ; -wire \z80_|execute_|ctl_reg_use_sp~4_combout ; -wire \z80_|execute_|ctl_reg_use_sp~5_combout ; -wire \z80_|execute_|ctl_reg_use_sp~6_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ; -wire \z80_|pla_decode_|Equal21~2_combout ; -wire \z80_|reg_control_|bank_af~0_combout ; -wire \z80_|reg_control_|bank_af~q ; -wire \z80_|reg_control_|reg_sel_af~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ; -wire \z80_|reg_control_|reg_sel_af2~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ; -wire \z80_|execute_|ctl_reg_sel_wz~12_combout ; -wire \z80_|execute_|ctl_flags_bus~4_combout ; -wire \z80_|execute_|ctl_flags_bus~6_combout ; -wire \z80_|execute_|ctl_flags_bus~7_combout ; -wire \z80_|execute_|fMRead~24_combout ; -wire \z80_|execute_|ctl_flags_bus~13_combout ; -wire \z80_|execute_|ctl_flags_bus~combout ; -wire \z80_|execute_|ctl_inc_dec~3_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~2_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~3_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~6_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~5_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~4_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~7_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~8_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~9_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~10_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~29_combout ; -wire \z80_|execute_|ctl_mRead~13_combout ; -wire \z80_|execute_|pc_inc_hold~49_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~9_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ; -wire \z80_|execute_|pc_inc_hold~28_combout ; -wire \z80_|execute_|setM1~35_combout ; -wire \z80_|execute_|setM1~36_combout ; -wire \z80_|execute_|fMRead~5_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~31_combout ; -wire \z80_|execute_|pc_inc_hold~29_combout ; -wire \z80_|execute_|ctl_reg_sys_we~1_combout ; -wire \z80_|execute_|ctl_reg_sys_we~2_combout ; -wire \z80_|pla_decode_|Equal33~3_combout ; -wire \z80_|execute_|ctl_reg_sys_we~0_combout ; -wire \z80_|execute_|ctl_reg_sys_we~3_combout ; -wire \z80_|execute_|ctl_reg_sys_we_lo~2_combout ; -wire \z80_|execute_|ctl_reg_sys_we_lo~3_combout ; -wire \z80_|execute_|ctl_reg_sys_we_lo~4_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~combout ; -wire \z80_|execute_|ctl_reg_sel_ir~0_combout ; -wire \z80_|execute_|ctl_reg_sel_ir~1_combout ; -wire \z80_|execute_|ctl_reg_out_lo~9_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~36_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ; -wire \z80_|execute_|ctl_reg_in_hi~4_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~4_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ; -wire \z80_|execute_|ctl_reg_sel_wz~5_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~6_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~7_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo~16_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~11_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~12_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~13_combout ; -wire \z80_|execute_|ctl_al_we~4_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~38_combout ; -wire \z80_|execute_|fMRead~0_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ; -wire \z80_|execute_|ctl_inc_dec~4_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~9_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~8_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ; -wire \z80_|execute_|ctl_al_we~5_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~18_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[0]~37_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ; -wire \z80_|execute_|ctl_bus_inc_oe~38_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~39_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~30_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~45_combout ; -wire \z80_|execute_|fMRead~1_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~36_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~27_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~28_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~37_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~40_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~35_combout ; -wire \z80_|execute_|ctl_inc_cy~77_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~32_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~33_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~34_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~41_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~10_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~11_combout ; -wire \z80_|execute_|ctl_sw_4d~3_combout ; -wire \z80_|execute_|ctl_sw_4d~4_combout ; -wire \z80_|execute_|ctl_sw_4d~2_combout ; -wire \z80_|execute_|ctl_sw_4d~5_combout ; -wire \z80_|execute_|setM1~45_combout ; -wire \z80_|execute_|setM1~46_combout ; -wire \z80_|execute_|ctl_sw_4d~1_combout ; -wire \z80_|execute_|ctl_sw_4d~0_combout ; -wire \z80_|execute_|ctl_sw_4d~6_combout ; -wire \z80_|execute_|fMRead~4_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~16_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~14_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~20_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~15_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~17_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~18_combout ; -wire \z80_|execute_|ctl_reg_sel_pc~19_combout ; -wire \z80_|reg_control_|reg_sel_pc~3_combout ; -wire \z80_|reg_control_|reg_sel_pc~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ; -wire \z80_|reg_file_|db_lo_as[0]~2_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ; -wire \z80_|reg_file_|db_lo_as[7]~22_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ; -wire \z80_|reg_file_|db_lo_as[7]~23_combout ; -wire \z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ; -wire \z80_|resets_|SYNTHESIZED_WIRE_10~q ; -wire \z80_|resets_|SYNTHESIZED_WIRE_9~q ; -wire \z80_|resets_|DFFE_intr_ff3~q ; -wire \ula_|pll_|altpll_component|auto_generated|wire_pll1_locked ; -wire \KEY[0]~input_o ; -wire \reset~combout ; -wire \z80_|resets_|x1~0_combout ; -wire \z80_|fpga_reset~feeder_combout ; -wire \z80_|fpga_reset~q ; -wire \z80_|fpga_reset~clkctrl_outclk ; -wire \z80_|resets_|x1~q ; -wire \z80_|resets_|clrpc_int~0_combout ; -wire \z80_|resets_|clrpc_int~q ; -wire \z80_|resets_|clrpc~0_combout ; -wire \z80_|execute_|ctl_apin_mux~1_combout ; -wire \z80_|execute_|ctl_al_we~6_combout ; -wire \z80_|execute_|ctl_al_we~7_combout ; -wire \z80_|execute_|ctl_al_we~8_combout ; -wire \z80_|execute_|ctl_alu_oe~10_combout ; -wire \z80_|execute_|ctl_al_we~9_combout ; -wire \z80_|execute_|ctl_al_we~10_combout ; -wire \z80_|execute_|ctl_al_we~11_combout ; -wire \z80_|execute_|ctl_al_we~12_combout ; -wire \z80_|execute_|ctl_inc_dec~6_combout ; -wire \z80_|execute_|fIOWrite~0_combout ; -wire \z80_|execute_|ctl_inc_dec~8_combout ; -wire \z80_|execute_|ctl_inc_dec~9_combout ; -wire \z80_|execute_|ctl_inc_dec~10_combout ; -wire \z80_|execute_|ctl_inc_dec~7_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~34_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ; -wire \z80_|reg_control_|reg_sel_de2~4_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~33_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~36_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~37_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~39_combout ; -wire \z80_|reg_control_|reg_sel_iy~2_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~38_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ; -wire \z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~35_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~40_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~41_combout ; -wire \z80_|reg_file_|gdfx_temp0[2]~42_combout ; -wire \z80_|reg_file_|db_lo_as[2]~7_combout ; -wire \z80_|reg_file_|db_lo_as[2]~8_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~10_combout ; -wire \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~11_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~15_combout ; -wire \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~14_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~16_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~12_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~13_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~17_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~22_combout ; -wire \z80_|reg_file_|db_lo_as[0]~0_combout ; -wire \z80_|reg_file_|db_lo_as[0]~1_combout ; -wire \z80_|execute_|ctl_inc_cy~72_combout ; +wire \z80_|resets_|SYNTHESIZED_WIRE_11~combout ; +wire \z80_|execute_|ctl_ir_we~4_combout ; +wire \z80_|execute_|ctl_state_iy_set~2_combout ; +wire \z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ; +wire \z80_|sequencer_|DFFE_T5_ff~q ; +wire \z80_|execute_|ctl_state_ixiy_we~2_combout ; +wire \z80_|decode_state_|DFFE_instIY1~q ; +wire \z80_|decode_state_|use_ixiy~combout ; +wire \z80_|execute_|ixy_d~4_combout ; +wire \z80_|execute_|ixy_d~11_combout ; +wire \z80_|execute_|ixy_d~9_combout ; +wire \z80_|execute_|ixy_d~7_combout ; +wire \z80_|execute_|ixy_d~6_combout ; +wire \z80_|execute_|ixy_d~8_combout ; +wire \z80_|execute_|ixy_d~12_combout ; +wire \z80_|pla_decode_|Equal33~0_combout ; +wire \z80_|pla_decode_|Equal33~1_combout ; +wire \z80_|pla_decode_|Equal33~2_combout ; +wire \z80_|pla_decode_|Equal21~0_combout ; +wire \z80_|pla_decode_|Equal77~0_combout ; +wire \z80_|pla_decode_|Equal77~1_combout ; +wire \z80_|pla_decode_|Equal1~7_combout ; +wire \z80_|pla_decode_|Equal79~0_combout ; +wire \z80_|interrupts_|iff1~0_combout ; +wire \z80_|interrupts_|DFFE_instIFF2~0_combout ; +wire \z80_|interrupts_|SYNTHESIZED_WIRE_12~combout ; +wire \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl_outclk ; +wire \z80_|interrupts_|DFFE_instIFF2~q ; +wire \z80_|pla_decode_|Equal13~0_combout ; +wire \z80_|pla_decode_|Equal38~2_combout ; +wire \z80_|interrupts_|iff1~1_combout ; +wire \z80_|interrupts_|SYNTHESIZED_WIRE_15~combout ; +wire \z80_|interrupts_|iff1~q ; wire \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ; -wire \ula_|video_|Add0~15 ; -wire \ula_|video_|Add0~16_combout ; -wire \ula_|video_|vga_hc~2_combout ; -wire \ula_|video_|Add0~17 ; -wire \ula_|video_|Add0~18_combout ; -wire \ula_|video_|vga_hc~1_combout ; wire \ula_|video_|Add0~0_combout ; wire \ula_|video_|vga_hc~3_combout ; wire \ula_|video_|Add0~1 ; wire \ula_|video_|Add0~2_combout ; -wire \ula_|video_|vga_hc[1]~feeder_combout ; wire \ula_|video_|Add0~3 ; wire \ula_|video_|Add0~4_combout ; wire \ula_|video_|Add0~5 ; wire \ula_|video_|Add0~6_combout ; -wire \ula_|video_|vga_hc[3]~feeder_combout ; wire \ula_|video_|Add0~7 ; wire \ula_|video_|Add0~8_combout ; -wire \ula_|video_|Equal0~0_combout ; -wire \ula_|video_|Equal0~1_combout ; -wire \ula_|video_|Equal1~0_combout ; wire \ula_|video_|Add0~9 ; wire \ula_|video_|Add0~10_combout ; wire \ula_|video_|vga_hc~0_combout ; @@ -965,10 +246,24 @@ wire \ula_|video_|Add0~11 ; wire \ula_|video_|Add0~12_combout ; wire \ula_|video_|Add0~13 ; wire \ula_|video_|Add0~14_combout ; +wire \ula_|video_|Add0~15 ; +wire \ula_|video_|Add0~16_combout ; +wire \ula_|video_|vga_hc~2_combout ; +wire \ula_|video_|Add0~17 ; +wire \ula_|video_|Add0~18_combout ; +wire \ula_|video_|vga_hc~1_combout ; +wire \ula_|video_|Equal0~0_combout ; +wire \ula_|video_|Equal0~1_combout ; +wire \ula_|video_|Equal1~0_combout ; wire \ula_|video_|Add1~0_combout ; +wire \ula_|video_|vga_vc[0]~0_combout ; +wire \ula_|video_|Add1~1 ; +wire \ula_|video_|Add1~2_combout ; +wire \ula_|video_|vga_vc[1]~1_combout ; wire \ula_|video_|Add1~3 ; wire \ula_|video_|Add1~4_combout ; wire \ula_|video_|vga_vc[2]~2_combout ; +wire \ula_|video_|vga_vc[2]~feeder_combout ; wire \ula_|video_|Add1~5 ; wire \ula_|video_|Add1~6_combout ; wire \ula_|video_|vga_vc[3]~3_combout ; @@ -976,8 +271,6 @@ wire \ula_|video_|Add1~7 ; wire \ula_|video_|Add1~8_combout ; wire \ula_|video_|vga_vc[4]~5_combout ; wire \ula_|video_|Add1~9 ; -wire \ula_|video_|Add1~10_combout ; -wire \ula_|video_|vga_vc[5]~8_combout ; wire \ula_|video_|Add1~11 ; wire \ula_|video_|Add1~12_combout ; wire \ula_|video_|vga_vc[6]~4_combout ; @@ -990,359 +283,1298 @@ wire \ula_|video_|vga_vc[8]~7_combout ; wire \ula_|video_|Add1~17 ; wire \ula_|video_|Add1~18_combout ; wire \ula_|video_|vga_vc[9]~9_combout ; -wire \ula_|video_|Equal2~0_combout ; wire \ula_|video_|Equal3~0_combout ; +wire \ula_|video_|Equal2~0_combout ; wire \ula_|video_|Equal3~1_combout ; -wire \ula_|video_|vga_vc[0]~0_combout ; -wire \ula_|video_|Add1~1 ; -wire \ula_|video_|Add1~2_combout ; -wire \ula_|video_|vga_vc[1]~1_combout ; -wire \SW[1]~input_o ; -wire \z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout ; -wire \z80_|pla_decode_|Equal79~0_combout ; -wire \z80_|interrupts_|DFFE_instIFF2~0_combout ; -wire \z80_|interrupts_|SYNTHESIZED_WIRE_12~combout ; -wire \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl_outclk ; -wire \z80_|interrupts_|DFFE_instIFF2~q ; -wire \z80_|interrupts_|iff1~0_combout ; -wire \z80_|interrupts_|iff1~1_combout ; -wire \z80_|interrupts_|SYNTHESIZED_WIRE_15~combout ; -wire \z80_|interrupts_|iff1~q ; +wire \ula_|video_|Add1~10_combout ; +wire \ula_|video_|vga_vc[5]~8_combout ; wire \ula_|video_|Equal2~1_combout ; wire \ula_|video_|Equal2~2_combout ; +wire \SW[1]~input_o ; +wire \z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout ; wire \z80_|interrupts_|SYNTHESIZED_WIRE_13~combout ; wire \z80_|interrupts_|int_armed~q ; +wire \z80_|interrupts_|DFFE_inst44~feeder_combout ; wire \z80_|interrupts_|DFFE_inst44~q ; -wire \z80_|execute_|pc_inc_hold~38_combout ; -wire \z80_|execute_|ctl_inc_cy~91_combout ; -wire \z80_|execute_|pc_inc_hold~45_combout ; -wire \z80_|execute_|pc_inc_hold~44_combout ; -wire \z80_|execute_|pc_inc_hold~46_combout ; -wire \z80_|execute_|pc_inc_hold~37_combout ; -wire \z80_|execute_|pc_inc_hold~50_combout ; -wire \z80_|execute_|pc_inc_hold~33_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ; -wire \z80_|execute_|pc_inc_hold~31_combout ; -wire \z80_|execute_|pc_inc_hold~32_combout ; -wire \z80_|execute_|pc_inc_hold~34_combout ; -wire \z80_|execute_|pc_inc_hold~51_combout ; -wire \z80_|execute_|pc_inc_hold~30_combout ; -wire \z80_|execute_|pc_inc_hold~52_combout ; -wire \z80_|execute_|pc_inc_hold~35_combout ; -wire \z80_|execute_|pc_inc_hold~36_combout ; -wire \z80_|execute_|ctl_inc_cy~44_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ; -wire \z80_|execute_|ctl_inc_cy~45_combout ; -wire \z80_|execute_|pc_inc_hold~43_combout ; -wire \z80_|execute_|ctl_inc_cy~71_combout ; -wire \z80_|execute_|ctl_inc_cy~73_combout ; -wire \z80_|execute_|ctl_inc_cy~46_combout ; -wire \z80_|execute_|pc_inc_hold~53_combout ; -wire \z80_|execute_|pc_inc_hold~39_combout ; -wire \z80_|execute_|pc_inc_hold~47_combout ; -wire \z80_|execute_|ctl_inc_cy~74_combout ; +wire \z80_|decode_state_|in_halt~0_combout ; +wire \z80_|decode_state_|in_halt~1_combout ; +wire \z80_|decode_state_|in_halt~q ; +wire \z80_|pla_decode_|Equal50~0_combout ; +wire \z80_|execute_|ixy_d~17_combout ; +wire \z80_|pla_decode_|Equal44~0_combout ; +wire \z80_|execute_|ixy_d~16_combout ; +wire \z80_|pla_decode_|Equal3~1_combout ; +wire \z80_|execute_|ixy_d~10_combout ; +wire \z80_|execute_|ixy_d~13_combout ; +wire \z80_|execute_|ixy_d~14_combout ; +wire \z80_|pla_decode_|Equal49~0_combout ; +wire \z80_|execute_|ixy_d~15_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ; +wire \z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout ; +wire \z80_|decode_state_|DFFE_inst4~q ; +wire \z80_|execute_|ctl_ir_we~5_combout ; +wire \z80_|execute_|ctl_ir_we~13_combout ; +wire \z80_|pla_decode_|Equal8~0_combout ; +wire \z80_|execute_|ctl_mRead~6_combout ; +wire \z80_|pla_decode_|Equal9~0_combout ; +wire \z80_|pla_decode_|Equal9~1_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ; +wire \z80_|pla_decode_|Equal13~1_combout ; +wire \z80_|pla_decode_|Equal69~0_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ; +wire \z80_|execute_|ctl_alu_op_low~27_combout ; +wire \z80_|execute_|ctl_reg_out_lo~2_combout ; +wire \z80_|execute_|rsel3~combout ; +wire \z80_|execute_|ctl_ir_we~12_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ; +wire \z80_|pla_decode_|Equal56~0_combout ; +wire \z80_|execute_|ctl_alu_op_low~24_combout ; +wire \z80_|execute_|ctl_alu_op_low~25_combout ; +wire \z80_|execute_|nextM~2_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~16_combout ; +wire \z80_|execute_|ctl_reg_out_lo~3_combout ; +wire \z80_|pla_decode_|Equal40~0_combout ; +wire \z80_|pla_decode_|Equal40~1_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ; +wire \z80_|pla_decode_|Equal3~0_combout ; +wire \z80_|pla_decode_|Equal39~0_combout ; +wire \z80_|execute_|ctl_reg_out_lo~4_combout ; +wire \z80_|execute_|ctl_alu_oe~0_combout ; +wire \z80_|execute_|comb~0_combout ; +wire \z80_|pla_decode_|Equal41~0_combout ; +wire \z80_|pla_decode_|Equal47~0_combout ; +wire \z80_|execute_|ctl_inc_cy~32_combout ; +wire \z80_|pla_decode_|Equal19~0_combout ; +wire \z80_|execute_|ctl_reg_out_lo~9_combout ; +wire \z80_|execute_|ctl_reg_out_lo~5_combout ; +wire \z80_|execute_|ctl_mWrite~4_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ; +wire \z80_|execute_|ctl_mRead~34_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ; +wire \z80_|execute_|ctl_mWrite~5_combout ; +wire \z80_|execute_|nextM~11_combout ; +wire \z80_|pla_decode_|Equal20~0_combout ; +wire \z80_|pla_decode_|Equal13~2_combout ; +wire \z80_|execute_|ctl_mRead~24_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~27_combout ; +wire \z80_|pla_decode_|Equal48~0_combout ; +wire \z80_|pla_decode_|Equal10~0_combout ; +wire \z80_|pla_decode_|Equal11~0_combout ; +wire \z80_|pla_decode_|Equal63~0_combout ; +wire \z80_|execute_|ctl_flags_hf2_we~combout ; +wire \z80_|execute_|ctl_alu_shift_oe~41_combout ; +wire \z80_|pla_decode_|Equal68~3_combout ; +wire \z80_|execute_|ctl_flags_bus~7_combout ; +wire \z80_|execute_|ctl_flags_bus~8_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~9_combout ; +wire \z80_|execute_|ctl_ir_we~6_combout ; +wire \z80_|execute_|ctl_ir_we~8_combout ; +wire \z80_|execute_|ctl_ir_we~14_combout ; +wire \z80_|execute_|ctl_flags_bus~4_combout ; +wire \z80_|execute_|ctl_flags_bus~5_combout ; +wire \z80_|execute_|ctl_mRead~4_combout ; +wire \z80_|execute_|ctl_flags_bus~6_combout ; +wire \z80_|execute_|ctl_flags_bus~9_combout ; +wire \z80_|execute_|ctl_iorw~11_combout ; +wire \z80_|execute_|ctl_mWrite~17_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~18_combout ; +wire \z80_|pla_decode_|Equal37~0_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~19_combout ; +wire \z80_|pla_decode_|Equal35~0_combout ; +wire \z80_|pla_decode_|Equal21~1_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~17_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~20_combout ; +wire \z80_|execute_|ctl_ir_we~9_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~11_combout ; +wire \z80_|execute_|ctl_ir_we~15_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~7_combout ; +wire \z80_|execute_|ctl_ir_we~7_combout ; +wire \z80_|pla_decode_|Equal46~0_combout ; +wire \z80_|execute_|ctl_ir_we~11_combout ; +wire \z80_|execute_|ctl_bus_db_oe~3_combout ; +wire \z80_|pla_decode_|Equal52~1_combout ; +wire \z80_|execute_|ctl_flags_xy_we~21_combout ; +wire \z80_|execute_|ctl_flags_xy_we~13_combout ; +wire \z80_|execute_|ctl_state_alu~6_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~14_combout ; +wire \z80_|execute_|ctl_flags_xy_we~14_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~24_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ; +wire \z80_|execute_|ctl_reg_gp_sel~7_combout ; +wire \z80_|execute_|rsel0~combout ; +wire \z80_|execute_|ctl_state_alu~3_combout ; +wire \z80_|execute_|ctl_reg_use_sp~0_combout ; +wire \z80_|execute_|ctl_state_alu~2_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ; +wire \z80_|execute_|ctl_reg_out_lo~6_combout ; +wire \z80_|execute_|ctl_state_alu~5_combout ; +wire \z80_|execute_|ctl_sw_2u~1_combout ; +wire \z80_|execute_|ctl_alu_oe~1_combout ; +wire \z80_|execute_|ctl_mWrite~7_combout ; +wire \z80_|execute_|ctl_sw_2u~4_combout ; +wire \z80_|execute_|setM1~57_combout ; +wire \z80_|execute_|ctl_sw_2u~5_combout ; +wire \z80_|execute_|ctl_reg_out_lo~7_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~0_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~41_combout ; +wire \z80_|execute_|ctl_inc_cy~86_combout ; +wire \z80_|execute_|ctl_inc_cy~88_combout ; +wire \z80_|execute_|ctl_inc_cy~36_combout ; +wire \z80_|execute_|ctl_inc_cy~87_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~26_combout ; +wire \z80_|execute_|ctl_mWrite~9_combout ; +wire \z80_|execute_|ctl_reg_sys_we~1_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~42_combout ; +wire \z80_|pla_decode_|Equal40~2_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~14_combout ; +wire \z80_|pla_decode_|Equal55~0_combout ; +wire \z80_|execute_|ctl_mRead~11_combout ; +wire \z80_|pla_decode_|Equal6~1_combout ; +wire \z80_|execute_|setM1~36_combout ; +wire \z80_|execute_|comb~1_combout ; +wire \z80_|execute_|ctl_mRead~13_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~11_combout ; +wire \z80_|pla_decode_|Equal24~0_combout ; +wire \z80_|execute_|pc_inc_hold~26_combout ; +wire \z80_|execute_|setM1~37_combout ; +wire \z80_|execute_|pc_inc_hold~6_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo~38_combout ; +wire \z80_|execute_|fMRead~7_combout ; +wire \z80_|execute_|ctl_mRead~12_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~31_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ; +wire \z80_|nM1_int~2_combout ; +wire \z80_|execute_|ctl_sw_4u~0_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ; +wire \z80_|execute_|fMRead~6_combout ; +wire \z80_|execute_|ctl_inc_dec~12_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ; +wire \z80_|pla_decode_|Equal25~0_combout ; +wire \z80_|pla_decode_|Equal12~1_combout ; +wire \z80_|execute_|ctl_inc_cy~38_combout ; +wire \z80_|execute_|ctl_inc_cy~82_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~16_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~32_combout ; +wire \z80_|execute_|ctl_inc_cy~77_combout ; +wire \z80_|pla_decode_|Equal29~0_combout ; wire \z80_|execute_|ctl_inc_cy~78_combout ; wire \z80_|execute_|ctl_inc_cy~79_combout ; -wire \z80_|execute_|ctl_inc_cy~80_combout ; -wire \z80_|execute_|ctl_inc_cy~81_combout ; -wire \z80_|execute_|ctl_inc_cy~82_combout ; -wire \z80_|execute_|ctl_inc_cy~83_combout ; -wire \z80_|execute_|ctl_inc_cy~84_combout ; -wire \z80_|execute_|pc_inc_hold~42_combout ; -wire \z80_|execute_|ctl_inc_cy~90_combout ; -wire \z80_|execute_|pc_inc_hold~41_combout ; -wire \z80_|execute_|ctl_inc_cy~66_combout ; -wire \z80_|execute_|ctl_inc_cy~67_combout ; -wire \z80_|execute_|ctl_inc_cy~68_combout ; -wire \z80_|execute_|ctl_inc_cy~64_combout ; -wire \z80_|execute_|ctl_inc_cy~63_combout ; -wire \z80_|execute_|ctl_inc_cy~65_combout ; -wire \z80_|execute_|ctl_inc_cy~69_combout ; +wire \z80_|execute_|ctl_mRead~14_combout ; wire \z80_|execute_|ctl_inc_cy~49_combout ; -wire \z80_|execute_|ctl_inc_cy~50_combout ; -wire \z80_|execute_|ctl_inc_cy~51_combout ; -wire \z80_|execute_|ctl_inc_cy~52_combout ; -wire \z80_|execute_|ctl_inc_cy~36_combout ; -wire \z80_|execute_|ctl_inc_cy~37_combout ; -wire \z80_|execute_|ctl_inc_cy~54_combout ; -wire \z80_|execute_|ctl_inc_cy~41_combout ; -wire \z80_|execute_|ctl_inc_cy~58_combout ; -wire \z80_|execute_|ctl_inc_cy~55_combout ; -wire \z80_|execute_|ctl_inc_cy~56_combout ; -wire \z80_|execute_|ctl_inc_cy~89_combout ; -wire \z80_|execute_|ctl_inc_cy~57_combout ; -wire \z80_|execute_|ctl_inc_cy~59_combout ; -wire \z80_|execute_|ctl_inc_cy~60_combout ; -wire \z80_|execute_|ctl_inc_cy~47_combout ; -wire \z80_|execute_|ctl_inc_cy~88_combout ; -wire \z80_|execute_|ctl_inc_cy~48_combout ; -wire \z80_|execute_|pc_inc_hold~40_combout ; -wire \z80_|execute_|ctl_inc_cy~61_combout ; -wire \z80_|execute_|ctl_inc_cy~62_combout ; -wire \z80_|execute_|ctl_inc_cy~70_combout ; -wire \z80_|execute_|ctl_inc_cy~85_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ; -wire \z80_|reg_file_|db_lo_as[0]~3_combout ; -wire \z80_|address_latch_|Q[0]~feeder_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ; -wire \z80_|reg_file_|db_lo_as[1]~4_combout ; -wire \z80_|reg_file_|db_lo_as[1]~5_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ; -wire \z80_|reg_file_|db_lo_as[1]~6_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ; -wire \z80_|reg_file_|db_lo_as[2]~9_combout ; -wire \z80_|address_latch_|Q[2]~feeder_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ; -wire \z80_|execute_|ctl_inc_cy~86_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ; -wire \z80_|execute_|ctl_inc_dec~11_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~45_combout ; -wire \z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~48_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~49_combout ; -wire \z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~5_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~40_combout ; +wire \z80_|execute_|ctl_mRead~5_combout ; wire \z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~40_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~41_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[3]~18_combout ; -wire \z80_|execute_|ctl_reg_in_hi~11_combout ; -wire \z80_|execute_|ctl_reg_in_hi~12_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~44_combout ; -wire \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~43_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ; -wire \z80_|reg_control_|reg_sys_we_hi~0_combout ; -wire \z80_|reg_control_|reg_sys_we_hi~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~45_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~42_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~46_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~47_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~17_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~18_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~19_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~16_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~20_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~8_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[1]~15_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~13_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~12_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~10_combout ; -wire \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~11_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~14_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~9_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~15_combout ; -wire \z80_|reg_file_|gdfx_temp1[1]~21_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ; -wire \z80_|reg_control_|reg_sw_4d_hi~0_combout ; -wire \z80_|reg_file_|db_hi_as[1]~0_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ; -wire \z80_|reg_file_|db_hi_as[1]~1_combout ; -wire \z80_|reg_file_|db_hi_as[0]~2_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~23_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~22_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~24_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~26_combout ; -wire \z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~25_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~27_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~28_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[0]~16_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~29_combout ; -wire \z80_|reg_file_|gdfx_temp1[0]~30_combout ; -wire \z80_|reg_file_|db_hi_as[0]~4_combout ; -wire \z80_|reg_file_|db_hi_as[0]~5_combout ; -wire \z80_|reg_file_|db_hi_as[0]~6_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ; -wire \z80_|reg_file_|db_hi_as[1]~3_combout ; -wire \z80_|address_latch_|Q[9]~feeder_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~32_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~35_combout ; -wire \z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~34_combout ; -wire \z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~33_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~36_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~37_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~31_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[2]~17_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~38_combout ; -wire \z80_|reg_file_|gdfx_temp1[2]~39_combout ; -wire \z80_|reg_file_|db_hi_as[2]~7_combout ; -wire \z80_|reg_file_|db_hi_as[2]~8_combout ; -wire \z80_|reg_file_|db_hi_as[2]~9_combout ; -wire \z80_|address_latch_|Q[10]~feeder_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ; -wire \z80_|reg_file_|db_hi_as[3]~10_combout ; -wire \z80_|reg_file_|db_hi_as[3]~11_combout ; -wire \z80_|reg_file_|db_hi_as[3]~12_combout ; -wire \z80_|reg_file_|gdfx_temp1[3]~48_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ; -wire \z80_|execute_|ctl_alu_op1_sel_low~combout ; -wire \z80_|alu_|alu_op1[3]~3_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~6_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~10_combout ; -wire \z80_|execute_|ctl_alu_core_R~0_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~5_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~7_combout ; -wire \z80_|execute_|ctl_alu_op2_sel_bus~8_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|ena~combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~6_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~20_combout ; -wire \z80_|execute_|ctl_state_alu~12_combout ; -wire \z80_|execute_|ctl_alu_core_hf~18_combout ; -wire \z80_|pla_decode_|Equal61~2_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~16_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~17_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~21_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~15_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~12_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~22_combout ; -wire \z80_|execute_|ctl_alu_core_hf~20_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~36_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~35_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~46_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~33_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~47_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ; +wire \z80_|execute_|ctl_bus_inc_oe~45_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~34_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ; +wire \z80_|execute_|ctl_mWrite~6_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~50_combout ; +wire \z80_|pla_decode_|Equal4~0_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~48_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~49_combout ; +wire \z80_|execute_|ctl_mRead~7_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~29_combout ; +wire \z80_|execute_|ctl_alu_core_S~11_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~27_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~44_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~28_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~30_combout ; +wire \z80_|execute_|ctl_mRead~3_combout ; +wire \z80_|execute_|fMRead~3_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~37_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~38_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~39_combout ; +wire \z80_|execute_|ctl_bus_inc_oe~43_combout ; +wire \z80_|execute_|ctl_alu_oe~3_combout ; +wire \z80_|execute_|fMWrite~1_combout ; +wire \z80_|execute_|ctl_flags_bus~1_combout ; +wire \z80_|execute_|fMRead~5_combout ; +wire \z80_|execute_|ctl_mRead~17_combout ; +wire \z80_|execute_|ctl_iorw~10_combout ; +wire \z80_|execute_|setM1~47_combout ; +wire \z80_|execute_|ctl_mWrite~8_combout ; +wire \z80_|execute_|ctl_al_we~13_combout ; +wire \z80_|execute_|setM1~48_combout ; +wire \z80_|execute_|ctl_sw_4d~0_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ; +wire \z80_|execute_|ctl_mRead~9_combout ; +wire \z80_|execute_|ctl_flags_sz_we~3_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ; +wire \z80_|execute_|ctl_flags_alu~9_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~2_combout ; +wire \z80_|execute_|ctl_flags_alu~10_combout ; +wire \z80_|execute_|ctl_flags_xy_we~10_combout ; +wire \z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ; +wire \z80_|execute_|ctl_flags_xy_we~11_combout ; +wire \z80_|execute_|ctl_flags_alu~11_combout ; +wire \z80_|execute_|ctl_reg_use_sp~1_combout ; +wire \z80_|execute_|ctl_state_alu~4_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~9_combout ; +wire \z80_|execute_|ctl_sw_2d~4_combout ; +wire \z80_|execute_|ctl_flags_sz_we~0_combout ; wire \z80_|execute_|ctl_flags_sz_we~4_combout ; -wire \z80_|pla_decode_|Equal71~2_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ; +wire \z80_|execute_|ctl_alu_op_low~47_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~3_combout ; +wire \z80_|execute_|ctl_flags_alu~12_combout ; +wire \z80_|execute_|ctl_alu_op_low~23_combout ; +wire \z80_|execute_|ctl_flags_xy_we~19_combout ; +wire \z80_|execute_|ctl_flags_alu~13_combout ; +wire \z80_|execute_|ctl_reg_out_hi~4_combout ; +wire \z80_|execute_|ctl_sw_4u~1_combout ; +wire \z80_|execute_|ctl_alu_op_low~29_combout ; +wire \z80_|execute_|ctl_flags_alu~14_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ; +wire \z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ; +wire \z80_|execute_|ctl_flags_use_cf2~13_combout ; +wire \z80_|execute_|ctl_flags_cf_we~7_combout ; +wire \z80_|execute_|ctl_pf_sel[0]~2_combout ; +wire \z80_|execute_|ctl_flags_hf_we~5_combout ; +wire \z80_|execute_|ctl_flags_pf_we~10_combout ; +wire \z80_|pla_decode_|Equal68~2_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~13_combout ; +wire \z80_|execute_|ctl_flags_pf_we~2_combout ; +wire \z80_|execute_|ctl_alu_oe~4_combout ; +wire \z80_|execute_|ctl_flags_xy_we~8_combout ; +wire \z80_|execute_|ctl_flags_xy_we~20_combout ; +wire \z80_|execute_|ctl_flags_xy_we~9_combout ; +wire \z80_|execute_|ctl_flags_sz_we~1_combout ; +wire \z80_|execute_|ctl_bus_db_oe~1_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~10_combout ; +wire \z80_|execute_|ctl_flags_sz_we~2_combout ; +wire \z80_|execute_|ctl_flags_alu~17_combout ; +wire \z80_|execute_|ctl_flags_alu~18_combout ; +wire \z80_|execute_|ctl_flags_alu~6_combout ; +wire \z80_|execute_|ctl_flags_alu~19_combout ; +wire \z80_|pla_decode_|Equal1~5_combout ; +wire \z80_|execute_|ctl_alu_core_R~0_combout ; +wire \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ; +wire \z80_|execute_|ctl_alu_core_R~1_combout ; +wire \z80_|execute_|ctl_flags_alu~7_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~5_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~8_combout ; +wire \z80_|execute_|ctl_flags_alu~8_combout ; +wire \z80_|execute_|ctl_flags_alu~15_combout ; +wire \z80_|execute_|ctl_state_alu~7_combout ; +wire \z80_|execute_|ctl_state_alu~12_combout ; +wire \z80_|execute_|ctl_state_alu~9_combout ; +wire \z80_|execute_|ctl_state_alu~10_combout ; +wire \z80_|execute_|ctl_state_alu~8_combout ; +wire \z80_|pla_decode_|Equal64~0_combout ; +wire \z80_|execute_|ctl_pf_sel[0]~3_combout ; +wire \z80_|pla_decode_|Equal62~2_combout ; +wire \z80_|execute_|ctl_flags_pf_we~4_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~46_combout ; +wire \z80_|execute_|ctl_flags_pf_we~6_combout ; +wire \z80_|execute_|ctl_flags_pf_we~7_combout ; +wire \z80_|execute_|ctl_state_alu~11_combout ; +wire \z80_|pla_decode_|Equal62~3_combout ; +wire \z80_|execute_|ctl_flags_pf_we~5_combout ; +wire \z80_|execute_|ctl_flags_pf_we~3_combout ; +wire \z80_|execute_|ctl_flags_pf_we~8_combout ; +wire \z80_|execute_|ctl_flags_pf_we~9_combout ; +wire \z80_|execute_|ctl_alu_core_S~6_combout ; +wire \z80_|execute_|ctl_alu_core_S~7_combout ; +wire \z80_|execute_|ctl_alu_res_oe~1_combout ; +wire \z80_|execute_|ctl_alu_res_oe~0_combout ; +wire \z80_|execute_|ctl_alu_core_S~4_combout ; +wire \z80_|execute_|ctl_alu_core_S~5_combout ; +wire \z80_|execute_|ctl_alu_res_oe~2_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ; +wire \z80_|reg_control_|reg_sys_we_lo~6_combout ; +wire \z80_|execute_|ctl_flags_xy_we~12_combout ; +wire \z80_|execute_|ctl_flags_cf_we~2_combout ; +wire \z80_|execute_|ctl_alu_res_oe~3_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_high~combout ; +wire \z80_|execute_|ctl_alu_op1_sel_zero~4_combout ; +wire \z80_|execute_|ctl_alu_core_hf~12_combout ; +wire \z80_|pla_decode_|Equal61~2_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~4_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~13_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~14_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~18_combout ; +wire \z80_|execute_|ctl_flags_bus~10_combout ; +wire \z80_|execute_|ctl_flags_bus~2_combout ; +wire \z80_|execute_|ctl_flags_bus~0_combout ; +wire \z80_|execute_|ctl_flags_bus~3_combout ; +wire \z80_|execute_|fMRead~26_combout ; +wire \z80_|execute_|ctl_flags_bus~combout ; +wire \z80_|execute_|ctl_reg_in_lo~9_combout ; +wire \z80_|execute_|ctl_alu_op1_oe~0_combout ; +wire \z80_|execute_|ctl_alu_op1_oe~1_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~6_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~12_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~8_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~9_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~combout ; +wire \z80_|execute_|ctl_alu_op2_oe~0_combout ; +wire \z80_|alu_|db_high[3]~0_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla83M1T3_2~combout ; +wire \z80_|execute_|ctl_alu_shift_oe~15_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~38_combout ; +wire \z80_|execute_|ctl_alu_op_low~28_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~6_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~37_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~39_combout ; +wire \z80_|execute_|ctl_flags_cf2_sel_daa~combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~7_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~8_combout ; +wire \z80_|execute_|ctl_alu_op_low~30_combout ; wire \z80_|execute_|ctl_alu_op_low~31_combout ; +wire \z80_|execute_|ctl_mRead~25_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~40_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~42_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~4_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~47_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~34_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~35_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~36_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~28_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~44_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~29_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~16_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~27_combout ; +wire \z80_|execute_|ctl_alu_bs_oe~10_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~31_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~30_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~32_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~33_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~21_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~45_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~22_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~23_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~24_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~25_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~26_combout ; +wire \z80_|execute_|ctl_alu_shift_oe~43_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_low~combout ; +wire \z80_|execute_|ctl_alu_op1_sel_zero~5_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_zero~combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~13_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~17_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~14_combout ; +wire \z80_|execute_|ctl_alu_core_R~3_combout ; +wire \z80_|execute_|ctl_alu_core_R~4_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~9_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~10_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~11_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~12_combout ; +wire \z80_|execute_|ctl_alu_op1_sel_bus~15_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~6_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|ena~combout ; +wire \z80_|alu_|db_low[3]~15_combout ; +wire \z80_|alu_|db_low[3]~16_combout ; +wire \z80_|execute_|ctl_alu_op_low~33_combout ; +wire \z80_|execute_|ctl_alu_op_low~34_combout ; +wire \z80_|execute_|ctl_alu_op_low~48_combout ; +wire \z80_|execute_|ctl_alu_op_low~35_combout ; +wire \z80_|execute_|ctl_alu_op_low~36_combout ; +wire \z80_|execute_|ctl_alu_op_low~37_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ; +wire \z80_|execute_|ctl_alu_op_low~38_combout ; +wire \z80_|execute_|ctl_alu_op_low~39_combout ; +wire \z80_|execute_|ctl_alu_op_low~40_combout ; +wire \z80_|execute_|ctl_alu_op_low~41_combout ; +wire \z80_|execute_|ctl_alu_op_low~combout ; +wire \z80_|execute_|ctl_alu_oe~5_combout ; +wire \z80_|execute_|ctl_alu_oe~6_combout ; +wire \z80_|execute_|ctl_alu_oe~9_combout ; +wire \z80_|execute_|ctl_alu_core_S~12_combout ; +wire \z80_|execute_|ctl_alu_oe~10_combout ; +wire \z80_|execute_|ctl_alu_oe~2_combout ; +wire \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~15_combout ; +wire \z80_|execute_|ctl_reg_in_hi~8_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~7_combout ; +wire \z80_|execute_|ctl_alu_oe~7_combout ; +wire \z80_|execute_|ctl_mWrite~11_combout ; +wire \z80_|execute_|ctl_bus_db_we~5_combout ; +wire \z80_|execute_|ctl_alu_oe~8_combout ; +wire \z80_|execute_|ctl_flags_alu~16_combout ; +wire \z80_|execute_|ctl_alu_oe~11_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ; +wire \z80_|execute_|ctl_reg_out_hi~8_combout ; +wire \z80_|execute_|ctl_reg_out_hi~5_combout ; +wire \z80_|execute_|ctl_sw_2u~2_combout ; +wire \z80_|execute_|ctl_sw_2u~0_combout ; +wire \z80_|execute_|ctl_sw_2u~3_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ; +wire \z80_|execute_|ctl_inc_cy~33_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~37_combout ; +wire \z80_|execute_|ctl_sw_2u~6_combout ; +wire \z80_|execute_|ctl_reg_out_hi~6_combout ; +wire \z80_|execute_|ctl_reg_out_hi~7_combout ; +wire \z80_|execute_|ctl_mRead~2_combout ; +wire \z80_|execute_|ctl_sw_2d~6_combout ; +wire \z80_|execute_|ctl_sw_2d~7_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ; +wire \z80_|execute_|ctl_sw_2d~8_combout ; +wire \z80_|execute_|ctl_bus_db_oe~7_combout ; +wire \z80_|execute_|ctl_sw_2d~5_combout ; +wire \z80_|execute_|ctl_mRead~19_combout ; +wire \z80_|execute_|ctl_mRead~18_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~2_combout ; +wire \z80_|pla_decode_|Equal24~1_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~3_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~4_combout ; +wire \z80_|execute_|ctl_mRead~20_combout ; +wire \z80_|execute_|ctl_reg_in_hi~5_combout ; +wire \z80_|execute_|ctl_mRead~22_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ; +wire \z80_|execute_|ctl_reg_in_hi~6_combout ; +wire \z80_|execute_|ctl_reg_in_hi~2_combout ; +wire \z80_|execute_|setM1~30_combout ; +wire \z80_|execute_|ctl_mRead~23_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~6_combout ; +wire \z80_|execute_|ctl_reg_in_hi~3_combout ; +wire \z80_|execute_|ctl_mWrite~10_combout ; +wire \z80_|execute_|fMRead~18_combout ; +wire \z80_|reg_control_|reg_sel_pc~0_combout ; +wire \z80_|reg_control_|reg_sel_pc~1_combout ; +wire \z80_|reg_control_|reg_sel_pc~2_combout ; +wire \z80_|execute_|fMRead~19_combout ; +wire \z80_|execute_|fMRead~20_combout ; +wire \z80_|execute_|fMRead~21_combout ; +wire \z80_|execute_|ctl_sw_2d~9_combout ; +wire \z80_|execute_|ctl_sw_2d~14_combout ; +wire \z80_|execute_|ctl_sw_1d~8_combout ; +wire \z80_|execute_|ctl_sw_2d~10_combout ; +wire \z80_|execute_|ctl_sw_2d~11_combout ; +wire \z80_|execute_|ctl_sw_2d~12_combout ; +wire \z80_|execute_|ctl_sw_2d~13_combout ; +wire \z80_|alu_|db[7]~9_combout ; +wire \z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ; +wire \z80_|execute_|ctl_alu_op_low~32_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~2_combout ; +wire \z80_|execute_|ctl_flags_xy_we~22_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~3_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ; wire \z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ; +wire \z80_|execute_|ctl_alu_core_hf~15_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ; -wire \z80_|pla_decode_|Equal72~2_combout ; -wire \z80_|pla_decode_|Equal73~2_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~7_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~17_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ; +wire \z80_|execute_|ctl_flags_nf_we~3_combout ; wire \z80_|execute_|ctl_flags_nf_we~0_combout ; +wire \z80_|pla_decode_|Equal73~2_combout ; +wire \z80_|pla_decode_|Equal72~2_combout ; wire \z80_|execute_|ctl_flags_nf_we~1_combout ; wire \z80_|execute_|ctl_flags_nf_we~2_combout ; -wire \z80_|execute_|ctl_flags_nf_we~3_combout ; wire \z80_|execute_|ctl_flags_sz_we~5_combout ; wire \z80_|execute_|ctl_flags_sz_we~6_combout ; wire \z80_|execute_|ctl_flags_nf_we~4_combout ; -wire \z80_|execute_|setM1~15_combout ; -wire \z80_|execute_|setM1~16_combout ; -wire \z80_|execute_|ctl_flags_xy_we~6_combout ; -wire \z80_|execute_|ctl_flags_xy_we~7_combout ; -wire \z80_|execute_|ctl_flags_sz_we~2_combout ; -wire \z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ; -wire \z80_|execute_|ctl_alu_core_R~1_combout ; -wire \z80_|execute_|ctl_flags_alu~7_combout ; -wire \z80_|reg_control_|reg_sys_we_lo~8_combout ; -wire \z80_|execute_|ctl_flags_alu~8_combout ; -wire \z80_|execute_|ctl_flags_xy_we~16_combout ; -wire \z80_|execute_|ctl_flags_alu~12_combout ; -wire \z80_|execute_|ctl_flags_alu~13_combout ; -wire \z80_|execute_|ctl_flags_alu~14_combout ; -wire \z80_|execute_|ctl_flags_alu~15_combout ; -wire \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~19_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~7_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~9_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~10_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_nf~q ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~7_combout ; -wire \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ; +wire \z80_|execute_|ctl_flags_hf_cpl~14_combout ; +wire \z80_|execute_|ctl_flags_hf_cpl~10_combout ; +wire \z80_|pla_decode_|Equal45~0_combout ; +wire \z80_|execute_|ctl_flags_hf_cpl~11_combout ; +wire \z80_|execute_|ctl_flags_hf_cpl~12_combout ; +wire \z80_|execute_|ctl_flags_hf_cpl~13_combout ; +wire \z80_|execute_|ctl_alu_core_S~8_combout ; +wire \z80_|execute_|ctl_alu_core_S~9_combout ; +wire \z80_|execute_|ctl_alu_core_S~10_combout ; +wire \z80_|execute_|ctl_alu_core_S~combout ; +wire \z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ; +wire \z80_|alu_|alu_op1[3]~2_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ; +wire \z80_|execute_|ctl_reg_sys_we_lo~2_combout ; +wire \z80_|execute_|ctl_reg_sys_we_lo~3_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~14_combout ; +wire \z80_|reg_control_|reg_sys_we_hi~0_combout ; +wire \z80_|pla_decode_|Equal33~3_combout ; +wire \z80_|execute_|ctl_reg_sys_we~0_combout ; +wire \z80_|execute_|ctl_reg_sys_we~2_combout ; +wire \z80_|execute_|ctl_reg_sys_we~3_combout ; +wire \z80_|execute_|ctl_reg_in_hi~4_combout ; +wire \z80_|reg_control_|reg_sys_we_hi~combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo~17_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~11_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~12_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~13_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ; +wire \z80_|execute_|ctl_reg_sel_wz~6_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~7_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~9_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~8_combout ; +wire \z80_|execute_|ctl_al_we~5_combout ; +wire \z80_|execute_|ctl_al_we~4_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~41_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~10_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo~21_combout ; +wire \z80_|execute_|ctl_inc_dec~3_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ; +wire \z80_|execute_|fMRead~2_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~20_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~29_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~13_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ; +wire \z80_|execute_|ctl_reg_sel_ir~0_combout ; +wire \z80_|execute_|ctl_reg_sel_ir~1_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ; +wire \z80_|execute_|ctl_reg_sys_we_lo~4_combout ; +wire \z80_|reg_control_|reg_sys_we_lo~combout ; +wire \z80_|reg_control_|reg_sw_4d_hi~0_combout ; +wire \z80_|reg_file_|db_hi_as[3]~10_combout ; +wire \z80_|reg_file_|db_hi_as[3]~11_combout ; +wire \z80_|execute_|ctl_apin_mux~1_combout ; +wire \z80_|execute_|ctl_inc_cy~37_combout ; +wire \z80_|execute_|ctl_inc_dec~2_combout ; +wire \z80_|execute_|ctl_inc_cy~40_combout ; +wire \z80_|execute_|ctl_inc_dec~4_combout ; +wire \z80_|execute_|ctl_inc_dec~5_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~4_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ; +wire \z80_|execute_|setM1~42_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~12_combout ; +wire \z80_|execute_|ctl_sw_1d~4_combout ; +wire \z80_|execute_|ctl_sw_4d~3_combout ; +wire \z80_|execute_|fMRead~9_combout ; +wire \z80_|execute_|fMRead~10_combout ; +wire \z80_|execute_|fMRead~8_combout ; +wire \z80_|execute_|ctl_sw_4d~2_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~11_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~12_combout ; +wire \z80_|execute_|ctl_sw_4d~4_combout ; +wire \z80_|execute_|ctl_sw_4d~5_combout ; +wire \z80_|execute_|ctl_al_we~14_combout ; +wire \z80_|execute_|ctl_al_we~10_combout ; +wire \z80_|execute_|ctl_al_we~6_combout ; +wire \z80_|execute_|ctl_al_we~7_combout ; +wire \z80_|execute_|ctl_al_we~8_combout ; +wire \z80_|execute_|ctl_al_we~9_combout ; +wire \z80_|execute_|ctl_al_we~11_combout ; +wire \z80_|execute_|ctl_al_we~12_combout ; +wire \z80_|execute_|fIOWrite~0_combout ; +wire \z80_|execute_|ctl_inc_dec~8_combout ; +wire \z80_|execute_|ctl_reg_gp_we~2_combout ; +wire \z80_|execute_|ctl_inc_dec~9_combout ; +wire \z80_|execute_|ctl_apin_mux~0_combout ; +wire \z80_|execute_|ctl_inc_dec~6_combout ; +wire \z80_|execute_|ctl_inc_dec~7_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~21_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[0]~40_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~39_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[0]~13_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[0]~31_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ; +wire \z80_|execute_|setM1~49_combout ; +wire \z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ; +wire \z80_|execute_|setM1~50_combout ; +wire \z80_|execute_|ctl_flags_oe~0_combout ; +wire \z80_|execute_|ctl_flags_oe~1_combout ; +wire \z80_|execute_|ctl_reg_in_hi~13_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~12_combout ; +wire \z80_|execute_|ctl_reg_in_hi~7_combout ; +wire \z80_|execute_|ctl_state_alu~13_combout ; +wire \z80_|execute_|ctl_reg_gp_we~6_combout ; +wire \z80_|execute_|ctl_reg_gp_we~5_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~17_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ; wire \z80_|execute_|ctl_alu_sel_op2_neg~10_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~8_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~9_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~11_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~14_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_neg~18_combout ; -wire \z80_|execute_|ctl_alu_sel_op2_high~combout ; +wire \z80_|execute_|ctl_sw_1d~9_combout ; +wire \z80_|execute_|ctl_reg_gp_we~9_combout ; +wire \z80_|execute_|ctl_reg_gp_we~4_combout ; +wire \z80_|execute_|ctl_reg_gp_we~7_combout ; +wire \z80_|execute_|ctl_reg_gp_we~3_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~32_combout ; +wire \z80_|execute_|ctl_sw_4u~2_combout ; +wire \z80_|execute_|ctl_sw_4u~3_combout ; +wire \z80_|execute_|ctl_reg_gp_we~8_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~14_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~24_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~46_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~22_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~23_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~26_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~34_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~25_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~21_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ; +wire \z80_|pla_decode_|Equal2~2_combout ; +wire \z80_|pla_decode_|Equal1~6_combout ; +wire \z80_|reg_control_|bank_exx~2_combout ; +wire \z80_|reg_control_|bank_exx~q ; +wire \z80_|reg_control_|bank_hl_de1~0_combout ; +wire \z80_|reg_control_|bank_hl_de1~q ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~28_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~29_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~30_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~13_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ; +wire \z80_|execute_|ctl_reg_use_sp~2_combout ; +wire \z80_|execute_|ctl_reg_use_sp~3_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~14_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~32_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~33_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~16_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~34_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~20_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~21_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~22_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~18_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~37_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~19_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~23_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~16_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~17_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~11_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~36_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~8_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~9_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~10_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~15_combout ; +wire \z80_|execute_|ctl_reg_gp_sel[1]~31_combout ; +wire \z80_|reg_control_|reg_sel_de2~5_combout ; +wire \z80_|reg_control_|reg_sel_de2~6_combout ; +wire \z80_|reg_control_|reg_sel_de~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ; +wire \z80_|reg_control_|bank_hl_de2~0_combout ; +wire \z80_|reg_control_|bank_hl_de2~q ; +wire \z80_|reg_control_|reg_sel_de2~4_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~33_combout ; +wire \z80_|reg_control_|reg_sel_hl~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ; +wire \z80_|reg_control_|reg_sel_hl2~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~34_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~36_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~15_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~18_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~37_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ; +wire \z80_|reg_control_|reg_sel_iy~2_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~38_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ; +wire \z80_|execute_|ctl_reg_in_hi~9_combout ; +wire \z80_|execute_|ctl_reg_in_hi~10_combout ; +wire \z80_|execute_|ctl_reg_in_lo~8_combout ; +wire \z80_|reg_file_|b2v_latch_sp_lo|latch[2]~feeder_combout ; +wire \z80_|execute_|ctl_reg_use_sp~4_combout ; +wire \z80_|execute_|ctl_reg_use_sp~5_combout ; +wire \z80_|execute_|ctl_reg_use_sp~6_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ; +wire \z80_|execute_|ctl_sw_1d~5_combout ; +wire \z80_|execute_|ctl_im_we~combout ; +wire \z80_|execute_|ctl_sw_1d~6_combout ; +wire \z80_|execute_|ctl_sw_1d~7_combout ; +wire \z80_|reg_file_|db_lo_ds[2]~2_combout ; +wire \z80_|alu_control_|db[2]~28_combout ; +wire \z80_|execute_|ctl_reg_in_hi~11_combout ; +wire \z80_|execute_|ctl_reg_in_hi~12_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ; +wire \z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~18_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ; +wire \z80_|pla_decode_|Equal21~2_combout ; +wire \z80_|reg_control_|bank_af~0_combout ; +wire \z80_|reg_control_|bank_af~q ; +wire \z80_|reg_control_|reg_sel_af~0_combout ; +wire \z80_|reg_control_|reg_sel_af2~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~17_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~19_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~16_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~20_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~34_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~36_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~35_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~33_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~37_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ; +wire \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~31_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[2]~12_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~32_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~38_combout ; +wire \z80_|execute_|ctl_inc_dec~11_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ; +wire \z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ; +wire \z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ; +wire \z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~4_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~5_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~16_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~6_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~7_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~10_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~8_combout ; +wire \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ; +wire \z80_|execute_|ctl_alu_op_low~42_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~9_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ; +wire \z80_|execute_|ctl_mWrite~18_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~2_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ; +wire \z80_|execute_|ctl_flags_cf2_we~4_combout ; +wire \z80_|execute_|ctl_flags_cf2_we~2_combout ; +wire \z80_|execute_|ctl_flags_cf2_we~3_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_32~combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~81_combout ; +wire \z80_|alu_|db_high[2]~8_combout ; +wire \z80_|alu_|db_high[2]~9_combout ; +wire \z80_|alu_|db_high[2]~11_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_lq~combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~5_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~6_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~7_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_bus~8_combout ; +wire \z80_|execute_|ctl_alu_op2_sel_zero~combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|ena~combout ; +wire \z80_|alu_|db_high[2]~10_combout ; +wire \z80_|alu_|db_high[2]~12_combout ; +wire \z80_|alu_|db_high[3]~1_combout ; +wire \z80_|alu_|db_high[2]~13_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~78_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~79_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ; +wire \z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~75_combout ; +wire \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~76_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~77_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~80_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~74_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~73_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~81_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~19_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~18_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~20_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~92_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~21_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ; +wire \z80_|reg_file_|db_lo_as[0]~2_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~55_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~56_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~57_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~59_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~58_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~60_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~53_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~54_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~61_combout ; +wire \z80_|reg_file_|gdfx_temp0[4]~62_combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ; +wire \z80_|reg_file_|db_lo_as[4]~13_combout ; +wire \z80_|reg_file_|db_lo_as[4]~14_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ; +wire \z80_|reg_file_|db_lo_as[4]~15_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~64_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~63_combout ; +wire \z80_|reg_file_|b2v_latch_af_lo|latch[5]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~65_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~69_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~68_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~66_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~67_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~70_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~71_combout ; +wire \z80_|reg_file_|gdfx_temp0[5]~72_combout ; +wire \z80_|reg_file_|db_lo_as[5]~16_combout ; +wire \z80_|reg_file_|db_lo_as[5]~17_combout ; +wire \z80_|reg_file_|db_lo_as[5]~18_combout ; +wire \z80_|execute_|ctl_inc_dec~10_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ; +wire \z80_|reg_file_|db_lo_as[6]~19_combout ; +wire \z80_|reg_file_|db_lo_as[6]~20_combout ; +wire \z80_|reg_file_|db_lo_as[6]~21_combout ; +wire \z80_|reg_file_|gdfx_temp0[6]~82_combout ; +wire \z80_|reg_file_|db_lo_ds[6]~0_combout ; +wire \z80_|sw1_|db_down[6]~1_combout ; +wire \z80_|execute_|ctl_66_oe~combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~4_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~2_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~3_combout ; wire \z80_|alu_|alu_op2[1]~1_combout ; wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ; -wire \z80_|execute_|ctl_alu_core_S~9_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8_combout ; -wire \z80_|alu_|alu_op2[0]~3_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_nf~12_combout ; -wire \z80_|execute_|ctl_alu_core_S~8_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ; -wire \z80_|execute_|ctl_alu_core_hf~21_combout ; -wire \z80_|execute_|ctl_alu_core_hf~22_combout ; -wire \z80_|execute_|ctl_alu_core_hf~19_combout ; -wire \z80_|execute_|ctl_alu_op_low~27_combout ; -wire \z80_|execute_|ctl_alu_op_low~29_combout ; -wire \z80_|execute_|ctl_alu_core_hf~23_combout ; -wire \z80_|execute_|ctl_alu_core_hf~37_combout ; -wire \z80_|execute_|ctl_alu_core_hf~38_combout ; -wire \z80_|execute_|ctl_alu_core_hf~24_combout ; -wire \z80_|execute_|ctl_alu_core_hf~25_combout ; -wire \z80_|execute_|ctl_alu_core_hf~26_combout ; -wire \z80_|execute_|ctl_alu_core_hf~27_combout ; -wire \z80_|execute_|ctl_alu_core_hf~28_combout ; -wire \z80_|execute_|ctl_alu_op_low~30_combout ; -wire \z80_|execute_|ctl_alu_core_hf~34_combout ; -wire \z80_|execute_|ctl_alu_core_hf~32_combout ; -wire \z80_|execute_|ctl_alu_core_hf~43_combout ; -wire \z80_|execute_|ctl_alu_core_hf~33_combout ; -wire \z80_|execute_|ctl_alu_core_hf~42_combout ; -wire \z80_|execute_|ctl_alu_core_hf~35_combout ; -wire \z80_|execute_|ctl_alu_core_hf~41_combout ; -wire \z80_|execute_|ctl_alu_core_hf~30_combout ; -wire \z80_|execute_|ctl_mWrite~10_combout ; -wire \z80_|execute_|ctl_alu_core_hf~31_combout ; -wire \z80_|execute_|ctl_alu_core_hf~44_combout ; -wire \z80_|execute_|ctl_alu_core_hf~29_combout ; -wire \z80_|execute_|ctl_alu_core_hf~36_combout ; -wire \z80_|execute_|ctl_alu_core_hf~39_combout ; -wire \z80_|execute_|ctl_alu_core_hf~40_combout ; -wire \z80_|execute_|ctl_flags_hf_we~2_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ; +wire \z80_|execute_|ctl_alu_core_R~5_combout ; wire \z80_|execute_|ctl_alu_core_R~2_combout ; wire \z80_|execute_|ctl_alu_core_R~combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3_combout ; -wire \z80_|alu_|alu_op2[3]~2_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ; +wire \z80_|alu_|db_high[0]~20_combout ; +wire \z80_|alu_|db_high[0]~21_combout ; +wire \z80_|alu_|db_high[0]~22_combout ; +wire \z80_|alu_|db_high[0]~23_combout ; +wire \z80_|alu_|db_high[0]~24_combout ; +wire \z80_|alu_|db_low[0]~4_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~2_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~3_combout ; +wire \z80_|alu_|db_low[0]~5_combout ; +wire \z80_|alu_|db_low[0]~6_combout ; +wire \z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ; +wire \z80_|execute_|ctl_flags_hf_we~2_combout ; +wire \z80_|execute_|ctl_flags_cf_we~3_combout ; +wire \z80_|execute_|ctl_flags_cf_we~4_combout ; +wire \z80_|execute_|ctl_flags_cf_we~5_combout ; +wire \z80_|execute_|ctl_flags_cf_we~6_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf~q ; +wire \z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ; +wire \z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ; +wire \z80_|alu_|db_low[0]~2_combout ; +wire \z80_|alu_|db_low[0]~3_combout ; +wire \z80_|alu_|db_low[0]~24_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~0_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~1_combout ; +wire \z80_|alu_|alu_op2[0]~3_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla26M3T5_8~combout ; +wire \z80_|execute_|ctl_alu_core_hf~14_combout ; +wire \z80_|execute_|ctl_alu_core_hf~16_combout ; +wire \z80_|execute_|ctl_alu_core_hf~13_combout ; +wire \z80_|execute_|ctl_alu_core_hf~17_combout ; +wire \z80_|execute_|ctl_alu_op_low~44_combout ; +wire \z80_|execute_|ctl_alu_core_hf~20_combout ; +wire \z80_|execute_|ctl_alu_core_hf~21_combout ; +wire \z80_|execute_|ctl_alu_core_hf~18_combout ; +wire \z80_|execute_|ctl_alu_core_hf~19_combout ; +wire \z80_|execute_|ctl_alu_core_hf~22_combout ; +wire \z80_|execute_|ctl_alu_op_low~43_combout ; +wire \z80_|execute_|ctl_alu_core_hf~24_combout ; +wire \z80_|execute_|ctl_alu_core_hf~25_combout ; +wire \z80_|execute_|ctl_alu_core_hf~35_combout ; +wire \z80_|execute_|ctl_alu_core_hf~23_combout ; +wire \z80_|execute_|ctl_alu_core_hf~26_combout ; +wire \z80_|execute_|ctl_alu_core_hf~34_combout ; +wire \z80_|execute_|ctl_alu_core_hf~27_combout ; +wire \z80_|execute_|ctl_alu_core_hf~28_combout ; +wire \z80_|execute_|ctl_alu_core_hf~29_combout ; +wire \z80_|execute_|ctl_alu_core_hf~30_combout ; +wire \z80_|execute_|ctl_alu_core_hf~31_combout ; +wire \z80_|execute_|ctl_alu_core_hf~36_combout ; +wire \z80_|execute_|ctl_alu_core_hf~37_combout ; +wire \z80_|execute_|ctl_alu_core_hf~32_combout ; +wire \z80_|execute_|ctl_alu_core_hf~33_combout ; +wire \z80_|alu_control_|alu_core_cf_in~0_combout ; +wire \z80_|alu_|alu_op1[0]~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ; +wire \z80_|alu_|db_high[0]~25_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~6_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ; +wire \z80_|alu_|db_high[1]~14_combout ; +wire \z80_|alu_|db_high[1]~15_combout ; +wire \z80_|alu_|db_high[1]~16_combout ; +wire \z80_|alu_|db_high[1]~17_combout ; +wire \z80_|alu_|db_high[1]~18_combout ; +wire \z80_|alu_|db_high[1]~19_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ; +wire \z80_|alu_control_|out[6]~0_combout ; +wire \z80_|alu_control_|out[6]~1_combout ; +wire \z80_|alu_control_|out[6]~2_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ; +wire \z80_|execute_|ctl_flags_sz_we~7_combout ; +wire \z80_|execute_|ctl_flags_sz_we~8_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ; +wire \z80_|execute_|setM1~51_combout ; +wire \z80_|execute_|ctl_flags_oe~2_combout ; +wire \z80_|execute_|ctl_sw_2u~7_combout ; +wire \z80_|alu_control_|db[6]~20_combout ; +wire \z80_|alu_control_|db[6]~21_combout ; +wire \z80_|execute_|ctl_reg_out_lo~8_combout ; +wire \z80_|alu_control_|db[6]~10_combout ; +wire \z80_|alu_control_|db[6]~11_combout ; +wire \z80_|alu_control_|db[6]~22_combout ; +wire \z80_|alu_|db[6]~21_combout ; +wire \z80_|alu_|db[6]~22_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~80_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~79_combout ; +wire \z80_|reg_file_|b2v_latch_bc_hi|latch[6]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~78_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~82_combout ; +wire \z80_|reg_file_|b2v_latch_hl2_hi|db[6]~5_combout ; +wire \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~76_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~77_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~83_combout ; +wire \z80_|reg_file_|gdfx_temp1[6]~84_combout ; +wire \z80_|reg_file_|db_hi_as[6]~22_combout ; +wire \z80_|reg_file_|db_hi_as[6]~23_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~61_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~62_combout ; +wire \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~60_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~63_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~64_combout ; +wire \z80_|reg_file_|b2v_latch_hl2_hi|db[4]~4_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~58_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~59_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~65_combout ; +wire \z80_|reg_file_|gdfx_temp1[4]~66_combout ; +wire \z80_|reg_file_|db_hi_as[4]~16_combout ; +wire \z80_|reg_file_|db_hi_as[4]~17_combout ; +wire \z80_|reg_file_|db_hi_as[4]~18_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ; +wire \z80_|reg_file_|db_hi_as[6]~24_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|address[15]~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|address[15]~1_combout ; +wire \z80_|reg_file_|db_hi_as[7]~19_combout ; +wire \z80_|reg_file_|db_hi_as[7]~20_combout ; +wire \z80_|reg_file_|db_hi_as[7]~21_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[7]~15_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~72_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~71_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~70_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~69_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~73_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~68_combout ; +wire \z80_|reg_file_|b2v_latch_de_hi|latch[7]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~67_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~74_combout ; +wire \z80_|reg_file_|gdfx_temp1[7]~75_combout ; +wire \z80_|alu_|db[7]~11_combout ; +wire \z80_|alu_|db[7]~12_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf2~q ; +wire \z80_|execute_|ctl_flags_use_cf2~8_combout ; +wire \z80_|execute_|ctl_flags_use_cf2~9_combout ; +wire \z80_|execute_|ctl_flags_use_cf2~10_combout ; +wire \z80_|execute_|ctl_flags_use_cf2~11_combout ; +wire \z80_|execute_|ctl_flags_use_cf2~12_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ; +wire \z80_|execute_|ctl_alu_op_low~46_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~9_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ; +wire \z80_|execute_|ctl_flags_cf_cpl~3_combout ; +wire \z80_|alu_flags_|flags_cf~combout ; +wire \z80_|sw2_|db_up[0]~0_combout ; +wire \z80_|alu_control_|db[0]~8_combout ; +wire \z80_|reg_file_|db_lo_as[0]~0_combout ; +wire \z80_|reg_file_|db_lo_as[0]~1_combout ; +wire \z80_|execute_|ctl_inc_cy~70_combout ; +wire \z80_|execute_|pc_inc_hold~28_combout ; +wire \z80_|execute_|pc_inc_hold~15_combout ; +wire \z80_|execute_|pc_inc_hold~27_combout ; +wire \z80_|execute_|pc_inc_hold~10_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ; +wire \z80_|execute_|pc_inc_hold~11_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ; +wire \z80_|execute_|pc_inc_hold~9_combout ; +wire \z80_|execute_|pc_inc_hold~12_combout ; +wire \z80_|execute_|pc_inc_hold~7_combout ; +wire \z80_|execute_|pc_inc_hold~8_combout ; +wire \z80_|execute_|pc_inc_hold~13_combout ; +wire \z80_|execute_|pc_inc_hold~14_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ; +wire \z80_|execute_|pc_inc_hold~16_combout ; +wire \z80_|execute_|pc_inc_hold~22_combout ; +wire \z80_|execute_|pc_inc_hold~23_combout ; +wire \z80_|execute_|pc_inc_hold~24_combout ; +wire \z80_|execute_|ctl_inc_cy~41_combout ; +wire \z80_|execute_|pc_inc_hold~21_combout ; +wire \z80_|execute_|pc_inc_hold~25_combout ; +wire \z80_|execute_|ctl_inc_cy~69_combout ; +wire \z80_|execute_|pc_inc_hold~17_combout ; +wire \z80_|execute_|ctl_inc_cy~71_combout ; +wire \z80_|execute_|ctl_inc_cy~44_combout ; +wire \z80_|execute_|ctl_inc_cy~42_combout ; +wire \z80_|execute_|ctl_inc_cy~43_combout ; +wire \z80_|execute_|ctl_inc_cy~57_combout ; +wire \z80_|execute_|ctl_inc_cy~54_combout ; +wire \z80_|execute_|ctl_inc_cy~58_combout ; +wire \z80_|execute_|pc_inc_hold~18_combout ; +wire \z80_|execute_|pc_inc_hold~19_combout ; +wire \z80_|execute_|ctl_inc_cy~45_combout ; +wire \z80_|execute_|ctl_inc_cy~34_combout ; +wire \z80_|execute_|ctl_inc_cy~35_combout ; +wire \z80_|execute_|ctl_inc_cy~46_combout ; +wire \z80_|execute_|ctl_inc_cy~47_combout ; +wire \z80_|execute_|ctl_inc_cy~48_combout ; +wire \z80_|execute_|ctl_inc_cy~50_combout ; +wire \z80_|execute_|ctl_inc_cy~51_combout ; +wire \z80_|execute_|ctl_inc_cy~85_combout ; +wire \z80_|execute_|ctl_inc_cy~63_combout ; +wire \z80_|execute_|ctl_inc_cy~64_combout ; +wire \z80_|execute_|ctl_inc_cy~65_combout ; +wire \z80_|execute_|ctl_inc_cy~59_combout ; +wire \z80_|execute_|ctl_inc_cy~60_combout ; +wire \z80_|execute_|ctl_inc_cy~61_combout ; +wire \z80_|execute_|ctl_inc_cy~62_combout ; +wire \z80_|execute_|ctl_inc_cy~66_combout ; +wire \z80_|execute_|ctl_inc_cy~53_combout ; +wire \z80_|execute_|ctl_inc_cy~52_combout ; +wire \z80_|execute_|ctl_inc_cy~84_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ; +wire \z80_|execute_|ctl_inc_cy~55_combout ; +wire \z80_|execute_|ctl_inc_cy~56_combout ; +wire \z80_|execute_|ctl_inc_cy~67_combout ; +wire \z80_|execute_|pc_inc_hold~20_combout ; +wire \z80_|execute_|ctl_inc_cy~83_combout ; +wire \z80_|execute_|ctl_inc_cy~68_combout ; +wire \z80_|address_latch_|Q[0]~feeder_combout ; +wire \z80_|execute_|ctl_inc_cy~72_combout ; +wire \z80_|execute_|ctl_inc_cy~73_combout ; +wire \z80_|execute_|ctl_inc_cy~74_combout ; +wire \z80_|execute_|ctl_inc_cy~75_combout ; +wire \z80_|execute_|ctl_inc_cy~76_combout ; +wire \z80_|execute_|ctl_inc_cy~80_combout ; +wire \z80_|execute_|ctl_inc_cy~81_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ; +wire \z80_|reg_file_|db_lo_as[0]~3_combout ; +wire \z80_|reg_file_|b2v_latch_af_lo|latch[0]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~13_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~12_combout ; +wire \z80_|reg_file_|b2v_latch_de_lo|latch[0]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~10_combout ; +wire \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~11_combout ; +wire \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~14_combout ; +wire \z80_|reg_file_|b2v_latch_sp_lo|latch[0]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~15_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~16_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~17_combout ; +wire \z80_|reg_file_|gdfx_temp0[0]~22_combout ; +wire \z80_|alu_control_|db[0]~9_combout ; +wire \z80_|alu_control_|db[0]~12_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~84_combout ; +wire \z80_|reg_file_|b2v_latch_de_lo|latch[7]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~83_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~88_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~86_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~87_combout ; +wire \z80_|reg_file_|b2v_latch_wz_lo|db[7]~0_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~89_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~85_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~90_combout ; +wire \z80_|reg_file_|gdfx_temp0[7]~91_combout ; +wire \z80_|reg_file_|db_lo_as[7]~22_combout ; +wire \z80_|reg_file_|db_lo_as[7]~23_combout ; +wire \z80_|reg_file_|db_lo_as[7]~24_combout ; +wire \z80_|address_latch_|Q[7]~feeder_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ; +wire \z80_|reg_file_|db_hi_as[0]~4_combout ; +wire \z80_|reg_file_|db_hi_as[0]~5_combout ; +wire \z80_|reg_file_|db_hi_as[0]~6_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~23_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~25_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~27_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~24_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~26_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~28_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[0]~11_combout ; +wire \z80_|reg_file_|b2v_latch_de_hi|latch[0]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~22_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~29_combout ; +wire \z80_|reg_file_|gdfx_temp1[0]~30_combout ; +wire \z80_|alu_|db[0]~13_combout ; +wire \z80_|alu_|db[0]~14_combout ; +wire \z80_|alu_|db_low[1]~10_combout ; +wire \z80_|alu_|db_low[1]~11_combout ; +wire \z80_|alu_|db_low[1]~8_combout ; +wire \z80_|alu_|db_low[1]~7_combout ; +wire \z80_|alu_|result_lo[1]~feeder_combout ; +wire \z80_|alu_|db_low[1]~9_combout ; +wire \z80_|alu_|db_low[1]~12_combout ; +wire \z80_|alu_|db[1]~8_combout ; +wire \z80_|alu_|db[1]~10_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~12_combout ; +wire \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~11_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~10_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~13_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~14_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[1]~10_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~9_combout ; +wire \z80_|reg_file_|b2v_latch_de_hi|latch[1]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~8_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~15_combout ; +wire \z80_|reg_file_|gdfx_temp1[1]~21_combout ; +wire \z80_|reg_file_|db_hi_as[1]~0_combout ; +wire \z80_|reg_file_|db_hi_as[1]~1_combout ; +wire \z80_|reg_file_|db_hi_as[1]~3_combout ; +wire \z80_|address_latch_|Q[9]~feeder_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ; +wire \z80_|reg_file_|db_hi_as[2]~7_combout ; +wire \z80_|reg_file_|db_hi_as[2]~8_combout ; +wire \z80_|reg_file_|db_hi_as[2]~9_combout ; +wire \z80_|reg_file_|gdfx_temp1[2]~39_combout ; +wire \z80_|alu_|db[2]~15_combout ; +wire \z80_|alu_|db[2]~16_combout ; +wire \z80_|alu_control_|db[2]~27_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ; +wire \z80_|alu_flags_|flags_hf2~0_combout ; +wire \z80_|alu_flags_|flags_hf2~q ; +wire \z80_|alu_control_|db[2]~23_combout ; +wire \z80_|alu_control_|db[2]~29_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~39_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~35_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~40_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~41_combout ; +wire \z80_|reg_file_|gdfx_temp0[2]~42_combout ; +wire \z80_|reg_file_|db_lo_as[2]~7_combout ; +wire \z80_|reg_file_|db_lo_as[2]~8_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ; +wire \z80_|reg_file_|db_lo_as[2]~9_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ; +wire \z80_|reg_file_|db_lo_as[3]~10_combout ; +wire \z80_|reg_file_|db_lo_as[3]~11_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ; +wire \z80_|reg_file_|db_lo_as[3]~12_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ; +wire \z80_|reg_file_|db_hi_as[3]~12_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~41_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~45_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~44_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~43_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~42_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~46_combout ; +wire \z80_|reg_file_|b2v_latch_de_hi|latch[3]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~40_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[3]~13_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~47_combout ; +wire \z80_|reg_file_|gdfx_temp1[3]~48_combout ; +wire \z80_|alu_|db[3]~19_combout ; +wire \z80_|alu_|db[3]~20_combout ; +wire \z80_|alu_|db_low[2]~21_combout ; +wire \z80_|alu_|db_low[2]~22_combout ; +wire \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~6_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~7_combout ; +wire \z80_|alu_|db_low[2]~18_combout ; +wire \z80_|alu_|db_low[2]~19_combout ; +wire \z80_|alu_|db_low[2]~20_combout ; +wire \z80_|alu_|db_low[2]~23_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~7_combout ; +wire \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~8_combout ; +wire \z80_|alu_|alu_op1[2]~1_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ; wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ; wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ; @@ -1350,449 +1582,292 @@ wire \z80_|execute_|ctl_flags_hf_we~3_combout ; wire \z80_|execute_|ctl_flags_hf_we~4_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_hf~q ; -wire \z80_|execute_|ctl_flags_hf_cpl~11_combout ; -wire \z80_|execute_|ctl_flags_hf_cpl~12_combout ; -wire \z80_|execute_|ctl_flags_hf_cpl~13_combout ; wire \z80_|alu_flags_|flags_hf~combout ; -wire \z80_|alu_control_|alu_core_cf_in~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ; -wire \z80_|alu_|db_high[0]~23_combout ; -wire \z80_|address_latch_|Q[12]~feeder_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ; -wire \z80_|reg_file_|db_hi_as[4]~16_combout ; -wire \z80_|reg_file_|db_hi_as[4]~17_combout ; -wire \z80_|reg_file_|db_hi_as[4]~18_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~62_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~63_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~61_combout ; -wire \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~60_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~64_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~59_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~58_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[4]~19_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~65_combout ; -wire \z80_|reg_file_|gdfx_temp1[4]~66_combout ; -wire \z80_|alu_|db[4]~16_combout ; -wire \z80_|alu_|db[7]~26_combout ; +wire \z80_|alu_control_|db[4]~30_combout ; +wire \z80_|alu_control_|db[4]~31_combout ; +wire \z80_|alu_control_|db[4]~32_combout ; wire \z80_|alu_|db[4]~17_combout ; -wire \z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ; -wire \z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ; -wire \z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ; -wire \z80_|alu_|db_high[0]~24_combout ; -wire \z80_|alu_|db_high[0]~21_combout ; -wire \z80_|alu_|db_high[0]~22_combout ; -wire \z80_|alu_|db_high[0]~25_combout ; -wire \z80_|alu_|db_high[0]~26_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|ena~combout ; -wire \z80_|alu_|alu_op1[0]~1_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ; -wire \z80_|alu_|alu_op1[1]~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ; -wire \z80_|alu_|alu_op1[2]~2_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ; -wire \z80_|execute_|ctl_alu_core_R~5_combout ; +wire \z80_|alu_|db[4]~18_combout ; +wire \z80_|alu_|db_low[3]~13_combout ; +wire \z80_|alu_|db_low[3]~14_combout ; +wire \z80_|alu_|db_low[3]~17_combout ; +wire \z80_|alu_|db_low[3]~25_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~4_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~5_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0_combout ; +wire \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1_combout ; +wire \z80_|alu_|alu_op2[3]~2_combout ; wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout ; wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ; -wire \z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~69_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~70_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~72_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~71_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~73_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~67_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[7]~20_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~68_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~74_combout ; -wire \z80_|reg_file_|db_hi_as[7]~19_combout ; -wire \z80_|reg_file_|db_hi_as[7]~20_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~54_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~53_combout ; -wire \z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~51_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~52_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~55_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~49_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~50_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[5]~14_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~56_combout ; -wire \z80_|reg_file_|gdfx_temp1[5]~57_combout ; -wire \z80_|reg_file_|db_hi_as[5]~13_combout ; -wire \z80_|reg_file_|db_hi_as[5]~14_combout ; -wire \z80_|reg_file_|db_hi_as[5]~15_combout ; -wire \z80_|address_latch_|Q[13]~feeder_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~76_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~80_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~79_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~78_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~81_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~82_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~77_combout ; -wire \z80_|reg_file_|b2v_latch_af_hi|db[6]~21_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~83_combout ; -wire \z80_|reg_file_|gdfx_temp1[6]~84_combout ; -wire \z80_|reg_file_|db_hi_as[6]~22_combout ; -wire \z80_|reg_file_|db_hi_as[6]~23_combout ; -wire \z80_|reg_file_|db_hi_as[6]~24_combout ; -wire \z80_|address_latch_|Q[14]~feeder_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout ; -wire \z80_|reg_file_|db_hi_as[7]~21_combout ; -wire \z80_|reg_file_|gdfx_temp1[7]~75_combout ; -wire \z80_|alu_|db[7]~20_combout ; -wire \z80_|alu_|db[7]~21_combout ; -wire \z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ; -wire \z80_|execute_|ctl_flags_cf_we~4_combout ; -wire \z80_|execute_|ctl_flags_cf_we~5_combout ; -wire \z80_|execute_|ctl_flags_cf_we~3_combout ; -wire \z80_|execute_|ctl_flags_cf_we~6_combout ; -wire \z80_|execute_|ctl_flags_cf2_we~2_combout ; -wire \z80_|execute_|ctl_flags_cf2_we~4_combout ; -wire \z80_|execute_|ctl_flags_cf2_we~3_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf~q ; -wire \z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ; -wire \z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ; -wire \z80_|alu_|db_high[3]~5_combout ; -wire \z80_|alu_|db_high[3]~6_combout ; +wire \z80_|alu_|db_high[3]~3_combout ; wire \z80_|alu_|db_high[3]~4_combout ; -wire \z80_|alu_|db_high[3]~27_combout ; +wire \z80_|alu_|db_high[3]~5_combout ; +wire \z80_|alu_|db_high[3]~2_combout ; +wire \z80_|alu_|db_high[3]~6_combout ; wire \z80_|alu_|db_high[3]~7_combout ; -wire \z80_|alu_|db_high[3]~8_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4_combout ; -wire \z80_|alu_|db_low[3]~9_combout ; -wire \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ; -wire \z80_|alu_|db_low[3]~10_combout ; -wire \z80_|alu_|db_low[3]~7_combout ; -wire \z80_|alu_|db_low[3]~8_combout ; -wire \z80_|alu_|db_low[3]~11_combout ; -wire \z80_|alu_|db_low[3]~25_combout ; -wire \z80_|alu_|db[3]~10_combout ; -wire \z80_|alu_|db[3]~11_combout ; -wire \z80_|execute_|ctl_sw_2u~7_combout ; -wire \z80_|execute_|setM1~49_combout ; -wire \z80_|execute_|ctl_flags_oe~2_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ; -wire \z80_|execute_|ctl_flags_sz_we~7_combout ; -wire \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ; -wire \z80_|execute_|ctl_flags_xy_we~13_combout ; -wire \z80_|execute_|ctl_flags_xy_we~14_combout ; -wire \z80_|execute_|ctl_flags_xy_we~15_combout ; -wire \z80_|alu_flags_|flags_xf~q ; -wire \z80_|alu_control_|db[3]~33_combout ; -wire \z80_|execute_|ctl_reg_out_lo~3_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ; -wire \z80_|execute_|ctl_reg_out_lo~4_combout ; -wire \z80_|execute_|ctl_reg_out_lo~5_combout ; -wire \z80_|execute_|ctl_reg_out_lo~8_combout ; -wire \z80_|sw1_|db_down[3]~1_combout ; -wire \z80_|alu_control_|db[3]~34_combout ; -wire \z80_|alu_control_|db[3]~35_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~46_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~47_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~50_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~44_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~43_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~51_combout ; -wire \z80_|reg_file_|gdfx_temp0[3]~52_combout ; -wire \z80_|reg_file_|db_lo_as[3]~10_combout ; -wire \z80_|reg_file_|db_lo_as[3]~11_combout ; -wire \z80_|reg_file_|db_lo_as[3]~12_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~53_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~54_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~58_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~59_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~60_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~57_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~55_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~56_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~61_combout ; -wire \z80_|reg_file_|gdfx_temp0[4]~62_combout ; -wire \z80_|reg_file_|db_lo_as[4]~13_combout ; -wire \z80_|reg_file_|db_lo_as[4]~14_combout ; -wire \z80_|reg_file_|db_lo_as[4]~15_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~64_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~63_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~66_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~67_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~65_combout ; -wire \z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~69_combout ; -wire \z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~68_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~70_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~71_combout ; -wire \z80_|reg_file_|gdfx_temp0[5]~72_combout ; -wire \z80_|reg_file_|db_lo_as[5]~16_combout ; -wire \z80_|reg_file_|db_lo_as[5]~17_combout ; -wire \z80_|reg_file_|db_lo_as[5]~18_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout ; -wire \z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~74_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~73_combout ; -wire \z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~78_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~79_combout ; -wire \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~76_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~77_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~80_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~75_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~81_combout ; -wire \z80_|reg_file_|gdfx_temp0[6]~82_combout ; -wire \z80_|reg_file_|db_lo_as[6]~19_combout ; -wire \z80_|reg_file_|db_lo_as[6]~20_combout ; -wire \z80_|reg_file_|db_lo_as[6]~21_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ; -wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ; -wire \z80_|reg_file_|db_lo_as[7]~24_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~83_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~84_combout ; -wire \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~88_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~86_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~87_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~85_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~89_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~90_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~91_combout ; -wire \z80_|reg_file_|gdfx_temp0[7]~92_combout ; -wire \z80_|reg_file_|db_lo_ds[7]~0_combout ; -wire \z80_|interrupts_|im2~q ; -wire \z80_|execute_|ctl_mRead~12_combout ; -wire \z80_|execute_|ctl_sw_mask543_en~0_combout ; -wire \z80_|alu_control_|db[7]~17_combout ; -wire \z80_|alu_control_|db[7]~16_combout ; -wire \z80_|alu_control_|db[7]~18_combout ; wire \z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ; -wire \z80_|execute_|ctl_flags_sz_we~8_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_sf~q ; -wire \z80_|pla_decode_|Equal62~3_combout ; -wire \z80_|execute_|ctl_flags_pf_we~5_combout ; -wire \z80_|execute_|ctl_flags_pf_we~6_combout ; -wire \z80_|execute_|ctl_flags_pf_we~7_combout ; -wire \z80_|execute_|ctl_flags_pf_we~8_combout ; -wire \z80_|execute_|ctl_flags_pf_we~9_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~5_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~7_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~6_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~8_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~11_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~12_combout ; +wire \z80_|execute_|ctl_alu_sel_op2_neg~15_combout ; +wire \z80_|alu_|alu_op2[2]~0_combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ; +wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ; +wire \z80_|alu_control_|DFFE_latch_pf_tmp~q ; +wire \z80_|alu_|alu_parity_out~0_combout ; +wire \z80_|alu_|alu_parity_out~1_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ; -wire \z80_|decode_state_|DFFE_instNonRep~0_combout ; -wire \z80_|decode_state_|DFFE_instNonRep~3_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~1_combout ; wire \z80_|decode_state_|DFFE_instNonRep~2_combout ; wire \z80_|decode_state_|DFFE_instNonRep~1_combout ; +wire \z80_|decode_state_|DFFE_instNonRep~3_combout ; +wire \z80_|decode_state_|DFFE_instNonRep~0_combout ; wire \z80_|decode_state_|DFFE_instNonRep~4_combout ; wire \z80_|decode_state_|DFFE_instNonRep~5_combout ; wire \z80_|decode_state_|DFFE_instNonRep~q ; -wire \z80_|alu_flags_|DFFE_inst_latch_pf~1_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ; -wire \z80_|alu_control_|DFFE_latch_pf_tmp~q ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ; -wire \z80_|alu_|alu_parity_out~0_combout ; -wire \z80_|alu_|alu_parity_out~combout ; wire \z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ; +wire \z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_pf~10_combout ; wire \z80_|alu_flags_|DFFE_inst_latch_pf~q ; wire \z80_|alu_control_|sel[1]~0_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ; wire \z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ; wire \z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ; wire \z80_|alu_control_|flags_cond_true~0_combout ; wire \z80_|alu_control_|flags_cond_true~q ; -wire \z80_|execute_|ctl_reg_sel_wz~13_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~14_combout ; -wire \z80_|execute_|ctl_reg_sel_wz~17_combout ; -wire \z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~18_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~20_combout ; -wire \z80_|reg_file_|gdfx_temp0[0]~21_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~20_combout ; +wire \z80_|execute_|ctl_sw_4d~1_combout ; +wire \z80_|execute_|ctl_sw_4d~6_combout ; +wire \z80_|reg_file_|db_lo_as[1]~4_combout ; +wire \z80_|reg_file_|db_lo_as[1]~5_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ; +wire \z80_|reg_file_|db_lo_as[1]~6_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~29_combout ; wire \z80_|reg_file_|gdfx_temp0[1]~28_combout ; wire \z80_|reg_file_|gdfx_temp0[1]~26_combout ; wire \z80_|reg_file_|gdfx_temp0[1]~27_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~29_combout ; -wire \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout ; -wire \z80_|reg_file_|gdfx_temp0[1]~25_combout ; wire \z80_|reg_file_|gdfx_temp0[1]~30_combout ; -wire \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder_combout ; wire \z80_|reg_file_|gdfx_temp0[1]~24_combout ; wire \z80_|reg_file_|gdfx_temp0[1]~23_combout ; +wire \z80_|reg_file_|gdfx_temp0[1]~25_combout ; wire \z80_|reg_file_|gdfx_temp0[1]~31_combout ; wire \z80_|reg_file_|gdfx_temp0[1]~32_combout ; wire \z80_|reg_file_|db_lo_ds[1]~1_combout ; wire \z80_|alu_control_|db[1]~25_combout ; wire \z80_|alu_control_|db[1]~24_combout ; wire \z80_|alu_control_|db[1]~26_combout ; -wire \z80_|alu_|db[1]~12_combout ; -wire \z80_|alu_|db[1]~13_combout ; -wire \z80_|alu_|db_low[0]~21_combout ; -wire \z80_|alu_|db_low[0]~22_combout ; -wire \z80_|alu_|db_low[0]~18_combout ; -wire \z80_|alu_|db_low[0]~19_combout ; -wire \z80_|alu_|db_low[0]~20_combout ; -wire \z80_|alu_|db_low[0]~23_combout ; -wire \z80_|alu_|db[0]~18_combout ; -wire \z80_|alu_|db[0]~19_combout ; -wire \z80_|alu_|db_low[1]~15_combout ; -wire \z80_|alu_|db_low[1]~16_combout ; -wire \z80_|alu_|db_low[1]~12_combout ; -wire \z80_|alu_|db_low[1]~13_combout ; -wire \z80_|alu_|db_low[1]~14_combout ; -wire \z80_|alu_|db_low[1]~17_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6_combout ; -wire \z80_|alu_control_|out[6]~0_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ; -wire \z80_|alu_flags_|flags_hf2~0_combout ; -wire \z80_|alu_flags_|flags_hf2~q ; -wire \z80_|alu_control_|db[2]~23_combout ; -wire \z80_|reg_file_|db_lo_ds[2]~2_combout ; -wire \z80_|alu_control_|db[2]~28_combout ; -wire \z80_|alu_control_|db[2]~27_combout ; -wire \z80_|alu_control_|db[2]~29_combout ; -wire \z80_|alu_|db[2]~14_combout ; -wire \z80_|alu_|db[2]~15_combout ; -wire \z80_|alu_|db_low[2]~2_combout ; -wire \z80_|alu_|db_low[2]~3_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout ; -wire \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1_combout ; -wire \z80_|alu_|db_low[2]~5_combout ; -wire \z80_|alu_|db_low[2]~6_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ; -wire \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4_combout ; -wire \z80_|alu_|alu_op2[2]~0_combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ; -wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ; -wire \z80_|alu_|db_high[2]~9_combout ; -wire \z80_|alu_|db_high[2]~11_combout ; -wire \z80_|alu_|db_high[2]~12_combout ; -wire \z80_|alu_|db_high[2]~10_combout ; -wire \z80_|alu_|db_high[2]~13_combout ; -wire \z80_|alu_|db_high[2]~14_combout ; -wire \z80_|alu_|db[6]~22_combout ; -wire \z80_|alu_|db[6]~23_combout ; -wire \z80_|alu_control_|out[6]~1_combout ; -wire \z80_|alu_control_|out[6]~2_combout ; -wire \z80_|alu_control_|db[6]~19_combout ; -wire \z80_|alu_control_|db[6]~20_combout ; -wire \z80_|alu_control_|db[6]~21_combout ; -wire \z80_|alu_control_|db[6]~22_combout ; -wire \z80_|execute_|ctl_bus_zero_oe~0_combout ; -wire \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ; -wire \z80_|interrupts_|im1~q ; -wire \z80_|execute_|ctl_bus_ff_oe~0_combout ; -wire \z80_|execute_|ctl_bus_ff_oe~1_combout ; -wire \z80_|bus_control_|db[0]~4_combout ; -wire \z80_|bus_control_|db[6]~8_combout ; -wire \z80_|execute_|ctl_mRead~37_combout ; -wire \z80_|execute_|ctl_mRead~28_combout ; -wire \z80_|execute_|ctl_mRead~29_combout ; -wire \z80_|execute_|ctl_mRead~30_combout ; -wire \z80_|execute_|setM1~37_combout ; -wire \z80_|execute_|setM1~55_combout ; -wire \z80_|execute_|setM1~38_combout ; -wire \z80_|execute_|ctl_mRead~34_combout ; -wire \z80_|execute_|nextM~3_combout ; -wire \z80_|execute_|ctl_mRead~31_combout ; -wire \z80_|execute_|ctl_mRead~32_combout ; -wire \z80_|execute_|ctl_mRead~33_combout ; -wire \z80_|execute_|ctl_mRead~35_combout ; -wire \z80_|memory_ifc_|DFFE_mrd_ff1~q ; -wire \z80_|memory_ifc_|wait_mrd~feeder_combout ; -wire \z80_|memory_ifc_|wait_mrd~q ; -wire \z80_|memory_ifc_|DFFE_mrd_ff3~q ; -wire \z80_|memory_ifc_|nRD_out~1_combout ; +wire \z80_|bus_control_|db[1]~10_combout ; wire \z80_|execute_|nextM~4_combout ; wire \z80_|execute_|ctl_iorw~12_combout ; wire \z80_|execute_|ctl_iorw~8_combout ; wire \z80_|execute_|ctl_iorw~9_combout ; wire \z80_|memory_ifc_|DFFE_iorq_ff1~q ; -wire \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder_combout ; wire \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ; +wire \z80_|memory_ifc_|wait_iorq~feeder_combout ; wire \z80_|memory_ifc_|wait_iorq~q ; wire \z80_|memory_ifc_|DFFE_iorq_ff4~q ; wire \z80_|memory_ifc_|iorq~0_combout ; -wire \z80_|execute_|fIORead~1_combout ; -wire \z80_|execute_|fIORead~2_combout ; -wire \z80_|execute_|fIORead~0_combout ; -wire \z80_|execute_|fIORead~3_combout ; wire \z80_|memory_ifc_|DFFE_m1_ff1~q ; wire \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout ; wire \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ; wire \z80_|memory_ifc_|DFFE_m1_ff3~q ; wire \z80_|memory_ifc_|nRD_out~0_combout ; +wire \z80_|execute_|fIORead~0_combout ; +wire \z80_|execute_|fIORead~1_combout ; +wire \z80_|execute_|fIORead~2_combout ; +wire \z80_|execute_|fIOWrite~1_combout ; +wire \z80_|execute_|fIORead~3_combout ; +wire \z80_|execute_|ctl_mRead~30_combout ; +wire \z80_|execute_|ctl_mRead~31_combout ; +wire \z80_|execute_|nextM~3_combout ; +wire \z80_|execute_|ctl_mRead~29_combout ; +wire \z80_|execute_|setM1~58_combout ; +wire \z80_|execute_|setM1~38_combout ; +wire \z80_|execute_|fMRead~4_combout ; +wire \z80_|execute_|setM1~39_combout ; +wire \z80_|execute_|setM1~40_combout ; +wire \z80_|execute_|ctl_mRead~32_combout ; +wire \z80_|execute_|ctl_mRead~33_combout ; +wire \z80_|memory_ifc_|DFFE_mrd_ff1~q ; +wire \z80_|memory_ifc_|wait_mrd~feeder_combout ; +wire \z80_|memory_ifc_|wait_mrd~q ; +wire \z80_|memory_ifc_|DFFE_mrd_ff3~q ; +wire \z80_|memory_ifc_|nRD_out~1_combout ; wire \z80_|memory_ifc_|nRD_out~2_combout ; +wire \z80_|execute_|fIOWrite~3_combout ; +wire \z80_|execute_|fIOWrite~4_combout ; +wire \z80_|execute_|fIOWrite~2_combout ; +wire \z80_|execute_|fIOWrite~5_combout ; +wire \z80_|execute_|ctl_mWrite~15_combout ; +wire \z80_|execute_|ctl_mWrite~12_combout ; +wire \z80_|execute_|ctl_mWrite~13_combout ; +wire \z80_|execute_|ctl_mWrite~14_combout ; +wire \z80_|execute_|ctl_mWrite~16_combout ; +wire \z80_|memory_ifc_|DFFE_mwr_ff1~q ; +wire \z80_|memory_ifc_|wait_mwr~feeder_combout ; +wire \z80_|memory_ifc_|wait_mwr~q ; +wire \z80_|memory_ifc_|mwr_wr~q ; +wire \z80_|memory_ifc_|nWR_out~0_combout ; wire \Equal2~1_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~0_combout ; -wire \z80_|execute_|fMWrite~5_combout ; -wire \z80_|execute_|fMWrite~6_combout ; -wire \z80_|execute_|fMWrite~2_combout ; +wire \z80_|execute_|fMWrite~3_combout ; wire \z80_|execute_|fMWrite~4_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~1_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~2_combout ; +wire \z80_|execute_|fMWrite~0_combout ; +wire \z80_|execute_|fMWrite~2_combout ; wire \z80_|pin_control_|bus_db_pin_oe~3_combout ; -wire \z80_|execute_|fMWrite~7_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~4_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~7_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~6_combout ; -wire \z80_|execute_|fMWrite~9_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~8_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~9_combout ; wire \z80_|execute_|fMWrite~8_combout ; -wire \z80_|pin_control_|bus_db_pin_oe~5_combout ; +wire \z80_|execute_|fMWrite~7_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~16_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~8_combout ; +wire \z80_|execute_|fMWrite~6_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~9_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~7_combout ; wire \z80_|pin_control_|bus_db_pin_oe~10_combout ; -wire \z80_|execute_|fMWrite~10_combout ; wire \z80_|pin_control_|bus_db_pin_oe~11_combout ; +wire \z80_|execute_|fMWrite~5_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~6_combout ; wire \z80_|pin_control_|bus_db_pin_oe~12_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~4_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~5_combout ; wire \z80_|pin_control_|bus_db_pin_oe~13_combout ; wire \z80_|pin_control_|bus_db_pin_oe~14_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~2_combout ; +wire \z80_|pin_control_|bus_db_pin_oe~15_combout ; wire \z80_|clk_delay_|DFF_inst5~feeder_combout ; wire \z80_|clk_delay_|DFF_inst5~q ; -wire \z80_|memory_ifc_|wait_iorqinta~feeder_combout ; wire \z80_|memory_ifc_|wait_iorqinta~q ; wire \z80_|memory_ifc_|DFFE_intr_ff3~q ; wire \z80_|memory_ifc_|nIORQ_out~0_combout ; wire \Equal2~0_combout ; -wire \ExtRamWE~0_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[13]~13_combout ; +wire \z80_|execute_|ctl_apin_mux~2_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[10]~10_combout ; wire \z80_|execute_|ctl_apin_mux2~0_combout ; -wire \z80_|pin_control_|bus_ab_pin_we~2_combout ; -wire \z80_|pin_control_|bus_ab_pin_we~3_combout ; +wire \z80_|pin_control_|bus_ab_pin_we~0_combout ; +wire \z80_|pin_control_|bus_ab_pin_we~1_combout ; +wire \PS2_DAT~input_o ; +wire \ula_|pll_|altpll_component|auto_generated|wire_pll1_locked ; +wire \KEY[0]~input_o ; +wire \reset~combout ; +wire \reset~clkctrl_outclk ; +wire \ula_|ps2_keyboard_|bit_count~3_combout ; +wire \PS2_CLK~input_o ; +wire \ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ; +wire \ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ; +wire \ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ; +wire \ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ; +wire \ula_|ps2_keyboard_|clk_filter[3]~feeder_combout ; +wire \ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ; +wire \ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ; +wire \ula_|ps2_keyboard_|Equal0~0_combout ; +wire \ula_|ps2_keyboard_|Equal0~1_combout ; +wire \ula_|ps2_keyboard_|clk_filter[0]~0_combout ; +wire \ula_|ps2_keyboard_|ps2_clk_in~0_combout ; +wire \ula_|ps2_keyboard_|ps2_clk_in~q ; +wire \ula_|ps2_keyboard_|clk_edge~0_combout ; +wire \ula_|ps2_keyboard_|clk_edge~q ; +wire \ula_|ps2_keyboard_|bit_count~1_combout ; +wire \ula_|ps2_keyboard_|bit_count~2_combout ; +wire \ula_|ps2_keyboard_|bit_count~0_combout ; +wire \ula_|ps2_keyboard_|always1~0_combout ; +wire \ula_|ps2_keyboard_|LessThan0~0_combout ; +wire \ula_|ps2_keyboard_|shiftreg[0]~0_combout ; +wire \ula_|ps2_keyboard_|shiftreg[7]~feeder_combout ; +wire \ula_|ps2_keyboard_|shiftreg[0]~feeder_combout ; +wire \ula_|ps2_keyboard_|WideXor0~0_combout ; +wire \ula_|ps2_keyboard_|WideXor0~1_combout ; +wire \ula_|ps2_keyboard_|WideXor0~2_combout ; +wire \ula_|ps2_keyboard_|scan_code_ready~0_combout ; +wire \ula_|ps2_keyboard_|scan_code_ready~q ; +wire \ula_|zx_keyboard_|Equal0~0_combout ; +wire \ula_|zx_keyboard_|Equal0~1_combout ; +wire \ula_|zx_keyboard_|released~0_combout ; +wire \ula_|zx_keyboard_|released~q ; +wire \ula_|zx_keyboard_|extended~0_combout ; +wire \ula_|zx_keyboard_|extended~q ; +wire \ula_|zx_keyboard_|keys[7][1]~21_combout ; +wire \ula_|zx_keyboard_|keys[5][4]~22_combout ; +wire \ula_|zx_keyboard_|keys[1][4]~23_combout ; +wire \ula_|zx_keyboard_|keys[2][1]~24_combout ; +wire \ula_|zx_keyboard_|keys[2][1]~25_combout ; +wire \ula_|zx_keyboard_|keys[2][1]~q ; +wire \ula_|zx_keyboard_|key_row~0_combout ; +wire \ula_|zx_keyboard_|keys[3][1]~26_combout ; +wire \ula_|zx_keyboard_|keys[3][1]~27_combout ; +wire \ula_|zx_keyboard_|keys[3][1]~28_combout ; +wire \ula_|zx_keyboard_|keys[3][1]~q ; +wire \z80_|address_pins_|DFFE_apin_latch[11]~11_combout ; +wire \z80_|address_pins_|abus[11]~19_combout ; +wire \ula_|zx_keyboard_|keys[7][4]~17_combout ; +wire \ula_|zx_keyboard_|keys[6][4]~18_combout ; +wire \ula_|zx_keyboard_|keys[1][1]~19_combout ; +wire \ula_|zx_keyboard_|keys[1][1]~20_combout ; +wire \ula_|zx_keyboard_|keys[1][1]~q ; +wire \z80_|address_pins_|DFFE_apin_latch[9]~9_combout ; +wire \z80_|address_pins_|abus[9]~17_combout ; +wire \ula_|zx_keyboard_|keys[0][0]~13_combout ; +wire \ula_|zx_keyboard_|shifted~2_combout ; +wire \ula_|zx_keyboard_|keys[0][1]~14_combout ; +wire \ula_|zx_keyboard_|keys[0][1]~15_combout ; +wire \ula_|zx_keyboard_|WideOr17~0_combout ; +wire \ula_|zx_keyboard_|shifted~5_combout ; +wire \ula_|zx_keyboard_|shifted~4_combout ; +wire \ula_|zx_keyboard_|shifted~q ; +wire \ula_|zx_keyboard_|keys[0][1]~12_combout ; +wire \ula_|zx_keyboard_|keys[0][1]~16_combout ; +wire \ula_|zx_keyboard_|keys[0][1]~q ; +wire \z80_|address_pins_|DFFE_apin_latch[8]~8_combout ; +wire \z80_|address_pins_|abus[8]~18_combout ; +wire \D[1]~26_combout ; +wire \D[1]~27_combout ; +wire \z80_|address_pins_|DFFE_apin_latch[12]~12_combout ; +wire \z80_|address_pins_|abus[12]~21_combout ; +wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ; +wire \z80_|address_pins_|DFFE_apin_latch[13]~13_combout ; wire \z80_|address_pins_|abus[13]~20_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~36_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~34_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~35_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~33_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~37_combout ; +wire \ula_|zx_keyboard_|keys[5][1]~q ; +wire \ula_|zx_keyboard_|keys[4][1]~29_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~30_combout ; +wire \ula_|zx_keyboard_|keys[5][2]~31_combout ; +wire \ula_|zx_keyboard_|keys[4][1]~32_combout ; +wire \ula_|zx_keyboard_|keys[4][1]~q ; +wire \D[1]~28_combout ; +wire \z80_|address_pins_|abus[0]~16_combout ; wire \z80_|address_pins_|DFFE_apin_latch[14]~14_combout ; wire \z80_|address_pins_|abus[14]~23_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~40_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~41_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~39_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~38_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~42_combout ; +wire \ula_|zx_keyboard_|keys[6][1]~q ; +wire \ula_|zx_keyboard_|WideOr16~4_combout ; +wire \ula_|zx_keyboard_|WideOr16~2_combout ; +wire \ula_|zx_keyboard_|WideOr16~7_combout ; +wire \ula_|zx_keyboard_|WideOr16~5_combout ; +wire \ula_|zx_keyboard_|WideOr16~6_combout ; +wire \ula_|zx_keyboard_|keys[7][1]~43_combout ; +wire \ula_|zx_keyboard_|keys[7][1]~44_combout ; +wire \ula_|zx_keyboard_|keys[7][1]~q ; wire \z80_|address_pins_|DFFE_apin_latch[15]~15_combout ; wire \z80_|address_pins_|abus[15]~22_combout ; +wire \D[1]~29_combout ; +wire \D[1]~30_combout ; +wire \ExtRamWE~0_combout ; wire \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ; -wire \z80_|address_pins_|abus[0]~16_combout ; wire \z80_|address_pins_|DFFE_apin_latch[1]~1_combout ; wire \z80_|address_pins_|abus[1]~25_combout ; wire \z80_|address_pins_|DFFE_apin_latch[2]~2_combout ; @@ -1807,30 +1882,27 @@ wire \z80_|address_pins_|DFFE_apin_latch[6]~6_combout ; wire \z80_|address_pins_|abus[6]~30_combout ; wire \z80_|address_pins_|DFFE_apin_latch[7]~7_combout ; wire \z80_|address_pins_|abus[7]~31_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[8]~8_combout ; -wire \z80_|address_pins_|abus[8]~18_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[9]~9_combout ; -wire \z80_|address_pins_|abus[9]~17_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[10]~10_combout ; wire \z80_|address_pins_|abus[10]~24_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[11]~11_combout ; -wire \z80_|address_pins_|abus[11]~19_combout ; -wire \z80_|address_pins_|DFFE_apin_latch[12]~12_combout ; -wire \z80_|address_pins_|abus[12]~21_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ; wire \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ; +wire \ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ; wire \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ; -wire \D[6]~90_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout ; wire \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ; -wire \D[6]~91_combout ; -wire \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ; wire \CLOCK_50~inputclkctrl_outclk ; +wire \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ; +wire \Selector3~0_combout ; +wire \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ; wire \~GND~combout ; wire \ula_|video_|vram_address[0]~feeder_combout ; wire \ula_|video_|vram_address~0_combout ; +wire \ula_|video_|vram_address[1]~feeder_combout ; wire \ula_|video_|vram_address[2]~4_combout ; wire \ula_|video_|Add3~0_combout ; wire \ula_|video_|Add3~1_combout ; @@ -1842,483 +1914,369 @@ wire \ula_|video_|Add4~7 ; wire \ula_|video_|Add4~8_combout ; wire \ula_|video_|Add4~9 ; wire \ula_|video_|Add4~10_combout ; +wire \ula_|video_|Add4~0_combout ; wire \ula_|video_|Add4~11 ; wire \ula_|video_|Add4~12_combout ; -wire \ula_|video_|Add4~0_combout ; wire \ula_|video_|Selector6~0_combout ; wire \ula_|video_|vram_address[9]~1_combout ; +wire \ula_|video_|Add4~2_combout ; wire \ula_|video_|Add4~13 ; wire \ula_|video_|Add4~14_combout ; -wire \ula_|video_|Add4~2_combout ; wire \ula_|video_|Selector5~0_combout ; wire \ula_|video_|Add4~4_combout ; wire \ula_|video_|vram_address[10]~2_combout ; wire \ula_|video_|vram_address[10]~3_combout ; wire \ula_|video_|Selector3~0_combout ; wire \ula_|video_|Selector2~0_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ; -wire \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ; -wire \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ; -wire \D[6]~87_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ; -wire \D[6]~88_combout ; -wire \D[6]~89_combout ; -wire \D[6]~111_combout ; -wire \raw_loader_in~input_o ; -wire \D[6]~86_combout ; -wire \D[6]~100_combout ; -wire \D[6]~101_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout ; +wire \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ; +wire \Selector1~0_combout ; +wire \Selector1~1_combout ; +wire \D[1]~81_combout ; +wire \D[1]~31_combout ; +wire \D[1]~32_combout ; wire \z80_|pin_control_|bus_db_pin_re~2_combout ; wire \z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ; -wire \z80_|bus_control_|db[6]~9_combout ; -wire \z80_|ir_|opcode[6]~feeder_combout ; -wire \z80_|execute_|ctl_ir_we~13_combout ; -wire \z80_|pla_decode_|Equal41~0_combout ; +wire \z80_|bus_control_|db[1]~11_combout ; +wire \z80_|pla_decode_|Equal2~0_combout ; +wire \z80_|execute_|ctl_mRead~15_combout ; +wire \z80_|execute_|ctl_inc_cy~39_combout ; +wire \z80_|execute_|ctl_reg_sys_hilo[1]~36_combout ; +wire \z80_|execute_|ctl_sw_4u~4_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~16_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~17_combout ; +wire \z80_|execute_|ctl_sw_4u~5_combout ; +wire \z80_|execute_|ctl_sw_4u~6_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~44_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~43_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~46_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~47_combout ; +wire \z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~49_combout ; +wire \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~45_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~48_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~50_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~51_combout ; +wire \z80_|reg_file_|gdfx_temp0[3]~52_combout ; +wire \z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ; +wire \z80_|execute_|ctl_flags_xy_we~15_combout ; +wire \z80_|execute_|ctl_flags_xy_we~16_combout ; +wire \z80_|execute_|ctl_flags_xy_we~17_combout ; +wire \z80_|execute_|ctl_flags_xy_we~18_combout ; +wire \z80_|alu_flags_|flags_xf~q ; +wire \z80_|alu_control_|db[3]~33_combout ; +wire \z80_|sw1_|db_down[3]~2_combout ; +wire \z80_|alu_control_|db[3]~34_combout ; +wire \z80_|alu_control_|db[3]~35_combout ; +wire \ula_|zx_keyboard_|keys[3][0]~75_combout ; +wire \ula_|zx_keyboard_|Selector5~0_combout ; +wire \ula_|zx_keyboard_|Selector5~1_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~132_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~106_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~107_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~133_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~108_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~q ; +wire \ula_|zx_keyboard_|keys[5][3]~104_combout ; +wire \ula_|zx_keyboard_|keys[5][3]~105_combout ; +wire \ula_|zx_keyboard_|keys[5][3]~q ; +wire \D[3]~55_combout ; +wire \ula_|zx_keyboard_|keys[6][4]~46_combout ; +wire \ula_|zx_keyboard_|keys[5][4]~62_combout ; +wire \ula_|zx_keyboard_|keys[3][3]~102_combout ; +wire \ula_|zx_keyboard_|keys[3][3]~103_combout ; +wire \ula_|zx_keyboard_|keys[3][3]~q ; +wire \ula_|zx_keyboard_|keys[0][4]~96_combout ; +wire \ula_|zx_keyboard_|keys[2][4]~94_combout ; +wire \ula_|zx_keyboard_|keys[0][3]~95_combout ; +wire \ula_|zx_keyboard_|keys[0][3]~97_combout ; +wire \ula_|zx_keyboard_|keys[0][3]~q ; +wire \ula_|zx_keyboard_|keys[6][4]~45_combout ; +wire \ula_|zx_keyboard_|keys[1][3]~92_combout ; +wire \ula_|zx_keyboard_|keys[1][3]~93_combout ; +wire \ula_|zx_keyboard_|keys[1][3]~q ; +wire \D[3]~53_combout ; +wire \ula_|zx_keyboard_|keys[2][3]~99_combout ; +wire \ula_|zx_keyboard_|keys[2][3]~100_combout ; +wire \ula_|zx_keyboard_|keys[2][3]~98_combout ; +wire \ula_|zx_keyboard_|keys[2][3]~101_combout ; +wire \ula_|zx_keyboard_|keys[2][3]~q ; +wire \ula_|zx_keyboard_|key_row~3_combout ; +wire \D[3]~54_combout ; +wire \ula_|zx_keyboard_|keys[0][4]~109_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~60_combout ; +wire \ula_|zx_keyboard_|keys[7][3]~110_combout ; +wire \ula_|zx_keyboard_|keys[7][3]~111_combout ; +wire \ula_|zx_keyboard_|keys[7][3]~112_combout ; +wire \ula_|zx_keyboard_|keys[7][3]~q ; +wire \ula_|zx_keyboard_|Selector13~0_combout ; +wire \ula_|zx_keyboard_|keys[6][3]~113_combout ; +wire \ula_|zx_keyboard_|keys[6][3]~114_combout ; +wire \ula_|zx_keyboard_|keys[6][3]~135_combout ; +wire \ula_|zx_keyboard_|keys[6][3]~136_combout ; +wire \ula_|zx_keyboard_|keys[6][3]~q ; +wire \D[3]~56_combout ; +wire \D[3]~57_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ; +wire \Selector3~1_combout ; +wire \Selector3~2_combout ; +wire \D[3]~85_combout ; +wire \D[3]~73_combout ; +wire \D[3]~74_combout ; +wire \z80_|bus_control_|db[3]~20_combout ; +wire \z80_|bus_control_|db[3]~21_combout ; +wire \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ; +wire \z80_|interrupts_|im2~q ; +wire \z80_|execute_|ctl_mRead~10_combout ; +wire \z80_|execute_|ctl_sw_mask543_en~0_combout ; +wire \z80_|alu_control_|db[7]~16_combout ; +wire \z80_|alu_control_|db[7]~17_combout ; +wire \z80_|alu_control_|db[7]~18_combout ; +wire \z80_|alu_control_|db[7]~19_combout ; +wire \z80_|bus_control_|db[7]~5_combout ; +wire \D[5]~67_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout ; +wire \Mux0~0_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ; +wire \Mux0~1_combout ; +wire \D[7]~89_combout ; +wire \D[7]~72_combout ; +wire \D[0]~84_combout ; +wire \D[7]~80_combout ; +wire \z80_|bus_control_|db[7]~7_combout ; +wire \z80_|pla_decode_|Equal6~0_combout ; +wire \z80_|pla_decode_|Equal12~0_combout ; +wire \z80_|execute_|ctl_mRead~16_combout ; +wire \z80_|execute_|fMRead~24_combout ; +wire \z80_|execute_|fMRead~25_combout ; +wire \z80_|execute_|ctl_mRead~21_combout ; +wire \z80_|execute_|fMRead~16_combout ; +wire \z80_|execute_|fMRead~14_combout ; +wire \z80_|execute_|fMRead~15_combout ; +wire \z80_|execute_|fMRead~12_combout ; +wire \z80_|execute_|fMRead~11_combout ; +wire \z80_|execute_|fMRead~13_combout ; +wire \z80_|execute_|fMRead~17_combout ; +wire \z80_|execute_|fMRead~22_combout ; +wire \z80_|execute_|fMRead~27_combout ; +wire \z80_|execute_|fMRead~37_combout ; +wire \z80_|execute_|fMRead~31_combout ; +wire \z80_|execute_|fMRead~29_combout ; +wire \z80_|execute_|fMRead~30_combout ; +wire \z80_|execute_|fMRead~28_combout ; +wire \z80_|execute_|fMRead~32_combout ; +wire \z80_|execute_|fMRead~33_combout ; +wire \z80_|execute_|fMRead~23_combout ; +wire \z80_|execute_|fMRead~34_combout ; +wire \z80_|execute_|fMRead~35_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~19_combout ; +wire \z80_|execute_|fMRead~36_combout ; +wire \z80_|pin_control_|bus_db_pin_re~combout ; +wire \ula_|zx_keyboard_|keys[2][4]~118_combout ; +wire \ula_|zx_keyboard_|keys[2][4]~119_combout ; +wire \ula_|zx_keyboard_|keys[2][4]~120_combout ; +wire \ula_|zx_keyboard_|keys[2][4]~q ; +wire \ula_|zx_keyboard_|keys[3][4]~129_combout ; +wire \ula_|zx_keyboard_|keys[3][4]~116_combout ; +wire \ula_|zx_keyboard_|keys[3][4]~134_combout ; +wire \ula_|zx_keyboard_|keys[3][4]~117_combout ; +wire \ula_|zx_keyboard_|keys[3][4]~q ; +wire \D[4]~60_combout ; +wire \ula_|zx_keyboard_|Equal0~2_combout ; +wire \ula_|zx_keyboard_|keys[1][4]~121_combout ; +wire \ula_|zx_keyboard_|keys[1][4]~q ; +wire \ula_|zx_keyboard_|keys[0][4]~115_combout ; +wire \ula_|zx_keyboard_|keys[0][4]~q ; +wire \ula_|zx_keyboard_|key_row~4_combout ; +wire \D[4]~61_combout ; +wire \ula_|zx_keyboard_|keys[4][4]~124_combout ; +wire \ula_|zx_keyboard_|keys[4][4]~125_combout ; +wire \ula_|zx_keyboard_|keys[4][4]~126_combout ; +wire \ula_|zx_keyboard_|keys[4][4]~q ; +wire \ula_|zx_keyboard_|keys[5][4]~122_combout ; +wire \ula_|zx_keyboard_|keys[5][4]~123_combout ; +wire \ula_|zx_keyboard_|keys[5][4]~q ; +wire \D[4]~62_combout ; +wire \ula_|zx_keyboard_|keys[7][4]~49_combout ; +wire \ula_|zx_keyboard_|shifted~3_combout ; +wire \ula_|zx_keyboard_|keys[7][4]~127_combout ; +wire \ula_|zx_keyboard_|keys[7][4]~q ; +wire \ula_|zx_keyboard_|keys[6][4]~128_combout ; +wire \ula_|zx_keyboard_|keys[6][4]~q ; +wire \D[4]~63_combout ; +wire \D[4]~64_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ; +wire \Selector4~0_combout ; +wire \Selector4~1_combout ; +wire \D[4]~86_combout ; +wire \D[4]~75_combout ; +wire \D[4]~76_combout ; +wire \z80_|bus_control_|db[4]~18_combout ; +wire \z80_|bus_control_|db[4]~19_combout ; +wire \z80_|pla_decode_|Equal32~0_combout ; wire \z80_|pla_decode_|Equal41~1_combout ; wire \z80_|pla_decode_|Equal41~2_combout ; -wire \z80_|execute_|ctl_alu_bs_oe~combout ; -wire \z80_|alu_|db_high[1]~15_combout ; -wire \z80_|alu_|db_high[1]~16_combout ; -wire \z80_|alu_|db_high[1]~17_combout ; -wire \z80_|alu_|db_high[1]~18_combout ; -wire \z80_|alu_|db_high[1]~19_combout ; -wire \z80_|alu_|db_high[1]~20_combout ; +wire \z80_|pla_decode_|Equal36~0_combout ; +wire \z80_|execute_|ctl_state_tbl_cb_set~combout ; +wire \z80_|execute_|ctl_state_tbl_we~8_combout ; +wire \z80_|decode_state_|DFFE_instCB~q ; +wire \z80_|pla_decode_|Equal52~0_combout ; +wire \z80_|pla_decode_|Equal2~1_combout ; +wire \z80_|execute_|ctl_state_tbl_ed_set~combout ; +wire \z80_|decode_state_|DFFE_instED~q ; +wire \z80_|decode_state_|table_xx~0_combout ; +wire \z80_|pla_decode_|Equal34~0_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~6_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~5_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~4_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~2_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~3_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~7_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~8_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~9_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~10_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~16_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~17_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~15_combout ; +wire \z80_|execute_|ctl_reg_sel_pc~18_combout ; +wire \z80_|execute_|ctl_reg_sel_wz~19_combout ; +wire \z80_|reg_control_|reg_sel_pc~3_combout ; +wire \z80_|reg_control_|reg_sel_pc~combout ; +wire \z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ; +wire \z80_|reg_file_|db_hi_as[0]~2_combout ; +wire \z80_|reg_file_|db_hi_as[5]~13_combout ; +wire \z80_|reg_file_|db_hi_as[5]~14_combout ; +wire \z80_|reg_file_|db_hi_as[5]~15_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~50_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~53_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~54_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~52_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~51_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~55_combout ; +wire \z80_|reg_file_|b2v_latch_af_hi|db[5]~14_combout ; +wire \z80_|reg_file_|b2v_latch_de_hi|latch[5]~feeder_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~49_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~56_combout ; +wire \z80_|reg_file_|gdfx_temp1[5]~57_combout ; +wire \z80_|alu_|db[5]~23_combout ; wire \z80_|alu_|db[5]~24_combout ; -wire \z80_|alu_|db[5]~25_combout ; wire \z80_|sw1_|db_down[5]~0_combout ; wire \z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout ; wire \z80_|alu_flags_|flags_yf~q ; wire \z80_|alu_control_|db[5]~13_combout ; wire \z80_|alu_control_|db[5]~14_combout ; wire \z80_|alu_control_|db[5]~15_combout ; -wire \D[0]~107_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ; wire \ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ; wire \ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout ; wire \rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ; wire \rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout ; wire \Mux2~0_combout ; wire \Mux2~1_combout ; -wire \D[5]~110_combout ; -wire \D[5]~85_combout ; -wire \D[5]~99_combout ; +wire \D[5]~87_combout ; +wire \D[5]~68_combout ; +wire \D[5]~77_combout ; wire \z80_|bus_control_|db[5]~14_combout ; wire \z80_|bus_control_|db[5]~15_combout ; -wire \z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout ; -wire \z80_|decode_state_|DFFE_inst4~q ; -wire \z80_|decode_state_|use_ixiy~combout ; -wire \z80_|execute_|ctl_mRead~23_combout ; -wire \z80_|execute_|fMRead~34_combout ; -wire \z80_|execute_|fMRead~31_combout ; -wire \z80_|execute_|fMRead~29_combout ; -wire \z80_|execute_|fMRead~30_combout ; -wire \z80_|execute_|fMRead~28_combout ; -wire \z80_|execute_|fMRead~32_combout ; -wire \z80_|execute_|ctl_bus_inc_oe~42_combout ; -wire \z80_|execute_|fMRead~14_combout ; -wire \z80_|execute_|fMRead~10_combout ; -wire \z80_|execute_|fMRead~9_combout ; -wire \z80_|execute_|fMRead~11_combout ; -wire \z80_|execute_|fMRead~12_combout ; -wire \z80_|execute_|fMRead~13_combout ; -wire \z80_|execute_|fMRead~15_combout ; -wire \z80_|execute_|fMRead~20_combout ; -wire \z80_|execute_|pc_inc_hold~48_combout ; -wire \z80_|execute_|fMRead~22_combout ; -wire \z80_|execute_|fMRead~21_combout ; -wire \z80_|execute_|fMRead~23_combout ; -wire \z80_|execute_|fMRead~26_combout ; -wire \z80_|execute_|fMRead~25_combout ; -wire \z80_|execute_|fMRead~27_combout ; -wire \z80_|execute_|fMRead~33_combout ; -wire \z80_|execute_|fMRead~35_combout ; -wire \z80_|pin_control_|bus_db_pin_re~combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ; -wire \Selector1~0_combout ; -wire \Selector1~1_combout ; -wire \D[1]~103_combout ; -wire \PS2_DAT~input_o ; -wire \reset~clkctrl_outclk ; -wire \ula_|ps2_keyboard_|bit_count~0_combout ; -wire \PS2_CLK~input_o ; -wire \ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ; -wire \ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ; -wire \ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ; -wire \ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ; -wire \ula_|ps2_keyboard_|Equal0~0_combout ; -wire \ula_|ps2_keyboard_|clk_filter[3]~feeder_combout ; -wire \ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ; -wire \ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ; -wire \ula_|ps2_keyboard_|Equal0~1_combout ; -wire \ula_|ps2_keyboard_|clk_filter[0]~0_combout ; -wire \ula_|ps2_keyboard_|ps2_clk_in~0_combout ; -wire \ula_|ps2_keyboard_|ps2_clk_in~q ; -wire \ula_|ps2_keyboard_|clk_edge~0_combout ; -wire \ula_|ps2_keyboard_|clk_edge~q ; -wire \ula_|ps2_keyboard_|bit_count~1_combout ; -wire \ula_|ps2_keyboard_|bit_count~3_combout ; -wire \ula_|ps2_keyboard_|bit_count~2_combout ; -wire \ula_|ps2_keyboard_|always1~0_combout ; -wire \ula_|ps2_keyboard_|LessThan0~0_combout ; -wire \ula_|ps2_keyboard_|shiftreg[0]~0_combout ; -wire \ula_|zx_keyboard_|Equal0~0_combout ; -wire \ula_|zx_keyboard_|Equal0~1_combout ; -wire \ula_|zx_keyboard_|extended~0_combout ; -wire \ula_|ps2_keyboard_|WideXor0~1_combout ; -wire \ula_|ps2_keyboard_|WideXor0~0_combout ; -wire \ula_|ps2_keyboard_|WideXor0~2_combout ; -wire \ula_|ps2_keyboard_|scan_code_ready~0_combout ; -wire \ula_|ps2_keyboard_|scan_code_ready~q ; -wire \ula_|zx_keyboard_|extended~q ; -wire \ula_|zx_keyboard_|keys[0][0]~15_combout ; -wire \ula_|zx_keyboard_|keys[5][1]~36_combout ; -wire \ula_|zx_keyboard_|keys[5][1]~37_combout ; -wire \ula_|zx_keyboard_|shifted~0_combout ; -wire \ula_|zx_keyboard_|released~0_combout ; -wire \ula_|zx_keyboard_|released~q ; -wire \ula_|zx_keyboard_|WideOr17~0_combout ; -wire \ula_|zx_keyboard_|shifted~2_combout ; -wire \ula_|zx_keyboard_|shifted~3_combout ; -wire \ula_|zx_keyboard_|shifted~q ; -wire \ula_|zx_keyboard_|keys[5][1]~35_combout ; -wire \ula_|zx_keyboard_|keys[5][1]~38_combout ; -wire \ula_|zx_keyboard_|keys[5][1]~39_combout ; -wire \ula_|zx_keyboard_|keys[5][1]~q ; -wire \ula_|zx_keyboard_|keys[4][1]~31_combout ; -wire \ula_|zx_keyboard_|keys[7][1]~23_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~32_combout ; -wire \ula_|zx_keyboard_|keys[5][2]~33_combout ; -wire \ula_|zx_keyboard_|keys[4][1]~34_combout ; -wire \ula_|zx_keyboard_|keys[4][1]~q ; -wire \D[1]~30_combout ; -wire \ula_|zx_keyboard_|keys[5][4]~24_combout ; -wire \ula_|zx_keyboard_|keys[3][1]~28_combout ; -wire \ula_|zx_keyboard_|keys[3][1]~29_combout ; -wire \ula_|zx_keyboard_|keys[3][1]~30_combout ; -wire \ula_|zx_keyboard_|keys[3][1]~q ; -wire \ula_|zx_keyboard_|keys[1][4]~25_combout ; -wire \ula_|zx_keyboard_|keys[2][1]~26_combout ; -wire \ula_|zx_keyboard_|keys[2][1]~27_combout ; -wire \ula_|zx_keyboard_|keys[2][1]~q ; -wire \ula_|zx_keyboard_|key_row~0_combout ; -wire \ula_|zx_keyboard_|keys[0][1]~14_combout ; -wire \ula_|zx_keyboard_|keys[0][1]~16_combout ; -wire \ula_|zx_keyboard_|keys[0][1]~17_combout ; -wire \ula_|zx_keyboard_|keys[0][1]~18_combout ; -wire \ula_|zx_keyboard_|keys[0][1]~q ; -wire \ula_|zx_keyboard_|keys[7][4]~19_combout ; -wire \ula_|zx_keyboard_|keys[6][4]~20_combout ; -wire \ula_|zx_keyboard_|keys[1][1]~21_combout ; -wire \ula_|zx_keyboard_|keys[1][1]~22_combout ; -wire \ula_|zx_keyboard_|keys[1][1]~q ; -wire \D[1]~28_combout ; -wire \D[1]~29_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~41_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~42_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~43_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~40_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~44_combout ; -wire \ula_|zx_keyboard_|keys[6][1]~q ; -wire \ula_|zx_keyboard_|keys[7][1]~45_combout ; -wire \ula_|zx_keyboard_|WideOr16~5_combout ; -wire \ula_|zx_keyboard_|WideOr16~2_combout ; -wire \ula_|zx_keyboard_|WideOr16~4_combout ; -wire \ula_|zx_keyboard_|WideOr16~7_combout ; -wire \ula_|zx_keyboard_|WideOr16~6_combout ; -wire \ula_|zx_keyboard_|keys[7][1]~46_combout ; -wire \ula_|zx_keyboard_|keys[7][1]~q ; -wire \D[1]~31_combout ; -wire \D[1]~32_combout ; -wire \D[1]~33_combout ; -wire \D[1]~34_combout ; -wire \z80_|bus_control_|db[1]~10_combout ; -wire \z80_|bus_control_|db[1]~11_combout ; -wire \z80_|ir_|opcode[1]~feeder_combout ; -wire \z80_|pla_decode_|Equal40~0_combout ; -wire \z80_|pla_decode_|Equal21~1_combout ; -wire \z80_|execute_|ctl_alu_op_low~26_combout ; -wire \z80_|execute_|ctl_alu_op_low~28_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~3_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~2_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~21_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ; -wire \z80_|execute_|ctl_alu_op_low~32_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~19_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ; -wire \z80_|alu_flags_|DFFE_inst_latch_cf2~q ; -wire \z80_|execute_|ctl_flags_use_cf2~10_combout ; -wire \z80_|execute_|ctl_flags_use_cf2~11_combout ; -wire \z80_|execute_|ctl_flags_use_cf2~8_combout ; -wire \z80_|execute_|ctl_flags_use_cf2~9_combout ; -wire \z80_|execute_|ctl_flags_use_cf2~12_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ; -wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~20_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~10_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~8_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~5_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~6_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~7_combout ; -wire \z80_|execute_|ctl_flags_cf_set~0_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~4_combout ; -wire \z80_|execute_|ctl_flags_cf_cpl~9_combout ; -wire \z80_|alu_flags_|flags_cf~combout ; -wire \z80_|alu_control_|db[0]~8_combout ; -wire \z80_|sw2_|db_up[0]~0_combout ; -wire \z80_|alu_control_|db[0]~9_combout ; -wire \z80_|alu_control_|db[0]~12_combout ; -wire \ula_|zx_keyboard_|keys[5][0]~67_combout ; -wire \ula_|zx_keyboard_|keys[5][0]~81_combout ; -wire \ula_|zx_keyboard_|keys[5][0]~82_combout ; -wire \ula_|zx_keyboard_|keys[5][0]~83_combout ; -wire \ula_|zx_keyboard_|keys[5][0]~q ; -wire \ula_|zx_keyboard_|keys[4][0]~84_combout ; -wire \ula_|zx_keyboard_|keys[4][0]~85_combout ; -wire \ula_|zx_keyboard_|keys[4][0]~86_combout ; -wire \ula_|zx_keyboard_|keys[4][0]~q ; -wire \D[0]~49_combout ; -wire \ula_|zx_keyboard_|WideOr4~0_combout ; -wire \ula_|zx_keyboard_|keys~76_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~73_combout ; -wire \ula_|zx_keyboard_|keys[6][4]~47_combout ; -wire \ula_|zx_keyboard_|WideOr0~0_combout ; -wire \ula_|zx_keyboard_|keys~74_combout ; -wire \ula_|zx_keyboard_|keys[0][0]~75_combout ; -wire \ula_|zx_keyboard_|keys[0][0]~77_combout ; -wire \ula_|zx_keyboard_|keys[0][0]~q ; -wire \ula_|zx_keyboard_|keys[1][0]~71_combout ; -wire \ula_|zx_keyboard_|keys[1][0]~72_combout ; -wire \ula_|zx_keyboard_|keys[1][0]~q ; -wire \D[0]~47_combout ; -wire \ula_|zx_keyboard_|keys[2][0]~80_combout ; -wire \ula_|zx_keyboard_|keys[2][0]~q ; -wire \ula_|zx_keyboard_|keys[3][0]~78_combout ; -wire \ula_|zx_keyboard_|keys[3][0]~79_combout ; -wire \ula_|zx_keyboard_|keys[3][0]~q ; -wire \ula_|zx_keyboard_|key_row~1_combout ; -wire \D[0]~48_combout ; -wire \ula_|zx_keyboard_|shifted~1_combout ; -wire \ula_|zx_keyboard_|keys[6][0]~90_combout ; -wire \ula_|zx_keyboard_|keys[6][0]~91_combout ; -wire \ula_|zx_keyboard_|keys[6][0]~92_combout ; -wire \ula_|zx_keyboard_|keys[6][0]~q ; -wire \ula_|zx_keyboard_|keys[5][4]~63_combout ; -wire \ula_|zx_keyboard_|WideOr16~3_combout ; -wire \ula_|zx_keyboard_|keys[7][0]~87_combout ; -wire \ula_|zx_keyboard_|keys[7][0]~132_combout ; -wire \ula_|zx_keyboard_|keys[7][0]~88_combout ; -wire \ula_|zx_keyboard_|keys[7][0]~89_combout ; -wire \ula_|zx_keyboard_|keys[7][0]~q ; -wire \D[0]~50_combout ; -wire \D[0]~51_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ; -wire \D[0]~55_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ; -wire \D[0]~56_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ; -wire \D[0]~52_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ; -wire \D[0]~53_combout ; -wire \D[0]~54_combout ; -wire \D[0]~106_combout ; -wire \D[0]~57_combout ; -wire \D[0]~58_combout ; -wire \z80_|bus_control_|db[0]~16_combout ; -wire \z80_|bus_control_|db[0]~17_combout ; -wire \z80_|pla_decode_|Equal63~0_combout ; -wire \z80_|execute_|ctl_flags_cf2_sel_daa~combout ; -wire \z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ; -wire \z80_|alu_control_|db[6]~10_combout ; -wire \z80_|alu_control_|db[6]~11_combout ; -wire \z80_|alu_control_|db[4]~30_combout ; -wire \z80_|alu_control_|db[4]~31_combout ; -wire \z80_|alu_control_|db[4]~32_combout ; -wire \ula_|zx_keyboard_|keys[2][4]~119_combout ; -wire \ula_|zx_keyboard_|keys[2][4]~120_combout ; -wire \ula_|zx_keyboard_|keys[2][4]~95_combout ; -wire \ula_|zx_keyboard_|keys[2][4]~121_combout ; -wire \ula_|zx_keyboard_|keys[2][4]~q ; -wire \ula_|zx_keyboard_|keys[3][4]~117_combout ; -wire \ula_|zx_keyboard_|keys[3][4]~136_combout ; -wire \ula_|zx_keyboard_|keys[3][4]~130_combout ; -wire \ula_|zx_keyboard_|keys[3][4]~118_combout ; -wire \ula_|zx_keyboard_|keys[3][4]~q ; -wire \D[4]~78_combout ; -wire \ula_|zx_keyboard_|keys[6][4]~126_combout ; -wire \ula_|zx_keyboard_|keys[5][4]~128_combout ; -wire \ula_|zx_keyboard_|keys[5][4]~129_combout ; -wire \ula_|zx_keyboard_|keys[5][4]~q ; -wire \ula_|zx_keyboard_|keys[6][4]~127_combout ; -wire \ula_|zx_keyboard_|keys[6][4]~q ; -wire \ula_|zx_keyboard_|Equal0~2_combout ; -wire \ula_|zx_keyboard_|keys[7][4]~51_combout ; -wire \ula_|zx_keyboard_|keys[7][4]~125_combout ; -wire \ula_|zx_keyboard_|keys[7][4]~q ; -wire \D[4]~79_combout ; -wire \ula_|zx_keyboard_|keys[4][4]~122_combout ; -wire \ula_|zx_keyboard_|keys[4][4]~123_combout ; -wire \ula_|zx_keyboard_|keys[4][4]~124_combout ; -wire \ula_|zx_keyboard_|keys[4][4]~q ; -wire \ula_|zx_keyboard_|key_row~3_combout ; -wire \D[4]~80_combout ; -wire \ula_|zx_keyboard_|keys[0][4]~111_combout ; -wire \ula_|zx_keyboard_|keys[0][4]~97_combout ; -wire \ula_|zx_keyboard_|keys[0][4]~116_combout ; -wire \ula_|zx_keyboard_|keys[0][4]~q ; -wire \ula_|zx_keyboard_|keys[1][4]~115_combout ; -wire \ula_|zx_keyboard_|keys[1][4]~q ; -wire \D[4]~77_combout ; -wire \D[4]~81_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout ; -wire \Selector4~0_combout ; -wire \Selector4~1_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2_combout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3_combout ; -wire \D[4]~109_combout ; -wire \D[4]~97_combout ; -wire \D[4]~98_combout ; -wire \z80_|bus_control_|db[4]~18_combout ; -wire \z80_|bus_control_|db[4]~19_combout ; -wire \z80_|pla_decode_|Equal21~0_combout ; -wire \z80_|execute_|ctl_mRead~5_combout ; -wire \z80_|execute_|fIOWrite~2_combout ; -wire \z80_|execute_|fIOWrite~3_combout ; -wire \z80_|execute_|fIOWrite~4_combout ; -wire \z80_|execute_|fIOWrite~5_combout ; -wire \z80_|execute_|ctl_mWrite~11_combout ; -wire \z80_|execute_|ctl_mWrite~12_combout ; -wire \z80_|execute_|ctl_mWrite~13_combout ; -wire \z80_|execute_|ctl_mWrite~14_combout ; -wire \z80_|execute_|ctl_mWrite~15_combout ; -wire \z80_|memory_ifc_|DFFE_mwr_ff1~q ; -wire \z80_|memory_ifc_|wait_mwr~feeder_combout ; -wire \z80_|memory_ifc_|wait_mwr~q ; -wire \z80_|memory_ifc_|mwr_wr~q ; -wire \z80_|memory_ifc_|nWR_out~0_combout ; -wire \D[5]~84_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ; -wire \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout ; -wire \Mux0~0_combout ; -wire \Mux0~1_combout ; -wire \D[7]~112_combout ; -wire \D[7]~94_combout ; -wire \D[7]~102_combout ; -wire \z80_|bus_control_|db[7]~5_combout ; -wire \z80_|bus_control_|db[7]~7_combout ; -wire \z80_|pla_decode_|Equal77~0_combout ; -wire \z80_|execute_|ctl_mWrite~5_combout ; -wire \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ; -wire \z80_|execute_|ctl_bus_db_we~3_combout ; +wire \z80_|execute_|ctl_mRead~8_combout ; wire \z80_|execute_|ctl_bus_db_we~8_combout ; -wire \z80_|execute_|ctl_bus_db_we~2_combout ; wire \z80_|execute_|ctl_bus_db_we~4_combout ; wire \z80_|execute_|ctl_bus_db_we~6_combout ; +wire \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ; +wire \z80_|execute_|ctl_bus_db_we~3_combout ; +wire \z80_|execute_|ctl_bus_db_we~2_combout ; wire \z80_|execute_|ctl_bus_db_we~7_combout ; -wire \ula_|zx_keyboard_|keys[0][2]~50_combout ; -wire \ula_|zx_keyboard_|keys[0][2]~52_combout ; -wire \ula_|zx_keyboard_|keys[0][2]~q ; -wire \ula_|zx_keyboard_|keys[3][3]~48_combout ; -wire \ula_|zx_keyboard_|keys[1][2]~49_combout ; -wire \ula_|zx_keyboard_|keys[1][2]~q ; -wire \D[2]~35_combout ; -wire \ula_|zx_keyboard_|keys[5][2]~57_combout ; -wire \ula_|zx_keyboard_|keys[5][2]~58_combout ; -wire \ula_|zx_keyboard_|keys[5][2]~q ; -wire \ula_|zx_keyboard_|keys[4][2]~59_combout ; -wire \ula_|zx_keyboard_|keys[4][2]~131_combout ; -wire \ula_|zx_keyboard_|keys[4][2]~60_combout ; -wire \ula_|zx_keyboard_|keys[4][2]~q ; -wire \D[2]~37_combout ; -wire \ula_|zx_keyboard_|keys[3][2]~53_combout ; -wire \ula_|zx_keyboard_|keys[2][2]~55_combout ; -wire \ula_|zx_keyboard_|keys[2][2]~56_combout ; -wire \ula_|zx_keyboard_|keys[2][2]~q ; -wire \ula_|zx_keyboard_|keys[3][2]~54_combout ; -wire \ula_|zx_keyboard_|keys[3][2]~q ; -wire \D[2]~36_combout ; -wire \ula_|zx_keyboard_|keys[6][2]~68_combout ; -wire \ula_|zx_keyboard_|keys[6][2]~69_combout ; -wire \ula_|zx_keyboard_|keys[6][2]~70_combout ; -wire \ula_|zx_keyboard_|keys[6][2]~q ; -wire \ula_|zx_keyboard_|keys[7][2]~61_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~62_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~64_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~65_combout ; -wire \ula_|zx_keyboard_|Selector13~0_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~66_combout ; -wire \ula_|zx_keyboard_|keys[7][2]~q ; -wire \D[2]~38_combout ; -wire \D[2]~39_combout ; -wire \D[2]~104_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ; -wire \D[2]~43_combout ; -wire \D[2]~44_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout ; -wire \D[2]~40_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ; -wire \D[2]~41_combout ; -wire \D[2]~42_combout ; -wire \D[2]~105_combout ; -wire \D[2]~45_combout ; -wire \D[2]~46_combout ; -wire \z80_|bus_control_|db[2]~12_combout ; -wire \z80_|bus_control_|db[2]~13_combout ; -wire \z80_|pla_decode_|Equal3~1_combout ; +wire \ula_|zx_keyboard_|keys[5][0]~66_combout ; +wire \ula_|zx_keyboard_|keys[5][0]~80_combout ; +wire \ula_|zx_keyboard_|keys[5][0]~81_combout ; +wire \ula_|zx_keyboard_|keys[5][0]~82_combout ; +wire \ula_|zx_keyboard_|keys[5][0]~q ; +wire \ula_|zx_keyboard_|keys[4][0]~84_combout ; +wire \ula_|zx_keyboard_|keys[4][0]~83_combout ; +wire \ula_|zx_keyboard_|keys[4][0]~85_combout ; +wire \ula_|zx_keyboard_|keys[4][0]~q ; +wire \D[0]~42_combout ; +wire \ula_|zx_keyboard_|keys[1][0]~78_combout ; +wire \ula_|zx_keyboard_|keys[1][0]~79_combout ; +wire \ula_|zx_keyboard_|keys[1][0]~q ; +wire \ula_|zx_keyboard_|keys[3][0]~76_combout ; +wire \ula_|zx_keyboard_|keys[3][0]~q ; +wire \ula_|zx_keyboard_|keys[2][0]~77_combout ; +wire \ula_|zx_keyboard_|keys[2][0]~q ; +wire \D[0]~40_combout ; +wire \ula_|zx_keyboard_|WideOr0~0_combout ; +wire \ula_|zx_keyboard_|keys~71_combout ; +wire \ula_|zx_keyboard_|keys[4][3]~70_combout ; +wire \ula_|zx_keyboard_|keys[0][0]~72_combout ; +wire \ula_|zx_keyboard_|WideOr4~0_combout ; +wire \ula_|zx_keyboard_|keys~73_combout ; +wire \ula_|zx_keyboard_|keys[0][0]~74_combout ; +wire \ula_|zx_keyboard_|keys[0][0]~q ; +wire \ula_|zx_keyboard_|key_row~2_combout ; +wire \D[0]~41_combout ; +wire \ula_|zx_keyboard_|keys[6][0]~89_combout ; +wire \ula_|zx_keyboard_|keys[6][0]~90_combout ; +wire \ula_|zx_keyboard_|keys[6][0]~91_combout ; +wire \ula_|zx_keyboard_|keys[6][0]~q ; +wire \ula_|zx_keyboard_|keys[7][0]~131_combout ; +wire \ula_|zx_keyboard_|WideOr16~3_combout ; +wire \ula_|zx_keyboard_|keys[7][0]~86_combout ; +wire \ula_|zx_keyboard_|keys[7][0]~87_combout ; +wire \ula_|zx_keyboard_|keys[7][0]~88_combout ; +wire \ula_|zx_keyboard_|keys[7][0]~q ; +wire \D[0]~43_combout ; +wire \D[0]~44_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4_combout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~5_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ; +wire \Selector2~0_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ; +wire \Selector2~1_combout ; +wire \D[0]~83_combout ; +wire \D[0]~45_combout ; +wire \D[0]~46_combout ; +wire \z80_|bus_control_|db[0]~16_combout ; +wire \z80_|bus_control_|db[0]~17_combout ; +wire \z80_|pla_decode_|Equal3~2_combout ; wire \z80_|pla_decode_|Equal43~0_combout ; wire \z80_|interrupts_|test1~2_combout ; wire \z80_|interrupts_|test1~3_combout ; @@ -2326,154 +2284,184 @@ wire \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ; wire \z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout ; wire \z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ; wire \z80_|clk_delay_|hold_clk_iorq~combout ; -wire \z80_|sequencer_|DFFE_T1_ff~q ; -wire \z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ; -wire \z80_|sequencer_|DFFE_T2_ff~q ; -wire \z80_|resets_|x3~combout ; -wire \z80_|resets_|SYNTHESIZED_WIRE_12~q ; -wire \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ; -wire \z80_|sequencer_|DFFE_M1_ff~q ; -wire \z80_|sequencer_|DFFE_M2_ff~0_combout ; -wire \z80_|sequencer_|DFFE_M2_ff~q ; -wire \z80_|execute_|ctl_mWrite~3_combout ; -wire \z80_|execute_|nextM~11_combout ; +wire \z80_|sequencer_|DFFE_T4_ff~q ; +wire \z80_|execute_|ctl_eval_cond~0_combout ; +wire \z80_|execute_|ctl_mRead~27_combout ; +wire \z80_|execute_|ctl_mRead~26_combout ; +wire \z80_|execute_|ctl_mRead~28_combout ; +wire \z80_|execute_|nextM~6_combout ; +wire \z80_|execute_|nextM~7_combout ; wire \z80_|execute_|nextM~8_combout ; wire \z80_|execute_|nextM~9_combout ; wire \z80_|execute_|nextM~10_combout ; wire \z80_|execute_|nextM~12_combout ; wire \z80_|execute_|nextM~15_combout ; -wire \z80_|execute_|nextM~6_combout ; -wire \z80_|execute_|nextM~7_combout ; wire \z80_|execute_|nextM~13_combout ; -wire \z80_|execute_|setM1~39_combout ; +wire \z80_|execute_|setM1~41_combout ; wire \z80_|execute_|nextM~5_combout ; wire \z80_|execute_|nextM~14_combout ; -wire \z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ; -wire \z80_|sequencer_|DFFE_T4_ff~q ; -wire \z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ; -wire \z80_|sequencer_|DFFE_T5_ff~q ; -wire \z80_|sequencer_|SYNTHESIZED_WIRE_17~combout ; -wire \z80_|sequencer_|T6~q ; -wire \z80_|execute_|setM1~13_combout ; -wire \z80_|pla_decode_|Equal77~1_combout ; -wire \z80_|execute_|setM1~12_combout ; -wire \z80_|execute_|setM1~14_combout ; -wire \z80_|execute_|setM1~41_combout ; -wire \z80_|execute_|setM1~42_combout ; -wire \z80_|execute_|setM1~43_combout ; -wire \z80_|execute_|setM1~44_combout ; -wire \z80_|execute_|setM1~50_combout ; -wire \z80_|execute_|setM1~51_combout ; -wire \z80_|execute_|setM1~6_combout ; -wire \z80_|execute_|setM1~7_combout ; -wire \z80_|execute_|setM1~8_combout ; -wire \z80_|execute_|setM1~9_combout ; -wire \z80_|execute_|setM1~10_combout ; -wire \z80_|execute_|setM1~11_combout ; -wire \z80_|execute_|setM1~17_combout ; -wire \z80_|execute_|setM1~31_combout ; -wire \z80_|execute_|setM1~28_combout ; -wire \z80_|execute_|setM1~30_combout ; -wire \z80_|execute_|setM1~32_combout ; -wire \z80_|execute_|setM1~33_combout ; -wire \z80_|execute_|setM1~25_combout ; -wire \z80_|execute_|setM1~26_combout ; -wire \z80_|execute_|setM1~24_combout ; -wire \z80_|execute_|setM1~27_combout ; -wire \z80_|execute_|setM1~22_combout ; -wire \z80_|execute_|setM1~21_combout ; -wire \z80_|execute_|setM1~53_combout ; -wire \z80_|execute_|setM1~23_combout ; -wire \z80_|execute_|setM1~18_combout ; -wire \z80_|execute_|setM1~19_combout ; -wire \z80_|execute_|setM1~20_combout ; -wire \z80_|execute_|setM1~34_combout ; -wire \z80_|execute_|setM1~52_combout ; +wire \z80_|sequencer_|ena_M~combout ; +wire \z80_|sequencer_|DFFE_T1_ff~q ; +wire \z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ; +wire \z80_|sequencer_|DFFE_T2_ff~q ; wire \z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ; wire \z80_|sequencer_|DFFE_T3_ff~q ; wire \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ; -wire \z80_|decode_state_|in_halt~0_combout ; -wire \z80_|decode_state_|in_halt~1_combout ; -wire \z80_|decode_state_|in_halt~q ; +wire \z80_|execute_|ctl_66_oe~2_combout ; +wire \z80_|interrupts_|im1~q ; +wire \z80_|execute_|ctl_bus_ff_oe~0_combout ; +wire \z80_|execute_|ctl_bus_ff_oe~1_combout ; +wire \z80_|execute_|ctl_bus_zero_oe~0_combout ; +wire \z80_|bus_control_|db[0]~4_combout ; +wire \z80_|bus_control_|db[6]~8_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ; +wire \Selector6~0_combout ; +wire \Selector6~1_combout ; +wire \D[6]~88_combout ; +wire \raw_loader_in~input_o ; +wire \D[6]~69_combout ; +wire \D[6]~78_combout ; +wire \D[6]~79_combout ; +wire \z80_|bus_control_|db[6]~9_combout ; +wire \z80_|execute_|ctl_ir_we~10_combout ; +wire \z80_|execute_|ctl_bus_db_oe~0_combout ; +wire \z80_|execute_|ctl_bus_db_oe~4_combout ; wire \z80_|execute_|ctl_bus_db_oe~2_combout ; wire \z80_|execute_|ctl_bus_db_oe~5_combout ; wire \z80_|execute_|ctl_bus_db_oe~6_combout ; -wire \z80_|execute_|ctl_bus_db_oe~4_combout ; wire \z80_|execute_|ctl_bus_db_oe~combout ; wire \z80_|bus_control_|db[0]~6_combout ; -wire \ula_|zx_keyboard_|keys[1][3]~93_combout ; -wire \ula_|zx_keyboard_|keys[1][3]~94_combout ; -wire \ula_|zx_keyboard_|keys[1][3]~q ; -wire \ula_|zx_keyboard_|keys[0][3]~96_combout ; -wire \ula_|zx_keyboard_|keys[0][3]~98_combout ; -wire \ula_|zx_keyboard_|keys[0][3]~q ; -wire \D[3]~65_combout ; -wire \ula_|zx_keyboard_|keys[3][3]~99_combout ; -wire \ula_|zx_keyboard_|keys[3][3]~100_combout ; -wire \ula_|zx_keyboard_|keys[3][3]~q ; -wire \ula_|zx_keyboard_|keys[2][3]~101_combout ; -wire \ula_|zx_keyboard_|keys[2][3]~102_combout ; -wire \ula_|zx_keyboard_|keys[2][3]~133_combout ; -wire \ula_|zx_keyboard_|keys[2][3]~103_combout ; -wire \ula_|zx_keyboard_|keys[2][3]~q ; -wire \D[3]~66_combout ; -wire \ula_|zx_keyboard_|keys[5][3]~104_combout ; -wire \ula_|zx_keyboard_|keys[5][3]~105_combout ; -wire \ula_|zx_keyboard_|keys[5][3]~q ; -wire \ula_|zx_keyboard_|keys[4][3]~106_combout ; -wire \ula_|zx_keyboard_|Selector5~1_combout ; -wire \ula_|zx_keyboard_|Selector5~0_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~134_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~107_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~135_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~108_combout ; -wire \ula_|zx_keyboard_|keys[4][3]~q ; -wire \D[3]~67_combout ; -wire \ula_|zx_keyboard_|keys[7][3]~112_combout ; -wire \ula_|zx_keyboard_|keys[7][3]~113_combout ; -wire \ula_|zx_keyboard_|keys[7][3]~114_combout ; -wire \ula_|zx_keyboard_|keys[7][3]~q ; -wire \ula_|zx_keyboard_|keys[6][3]~109_combout ; -wire \ula_|zx_keyboard_|keys[6][3]~110_combout ; -wire \ula_|zx_keyboard_|keys[6][3]~137_combout ; -wire \ula_|zx_keyboard_|keys[6][3]~138_combout ; -wire \ula_|zx_keyboard_|keys[6][3]~q ; -wire \ula_|zx_keyboard_|key_row~2_combout ; -wire \D[3]~68_combout ; -wire \D[3]~69_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ; -wire \D[3]~73_combout ; -wire \ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ; -wire \D[3]~74_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ; -wire \D[3]~70_combout ; -wire \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ; -wire \D[3]~71_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ; -wire \D[3]~72_combout ; -wire \D[3]~108_combout ; -wire \D[3]~95_combout ; -wire \D[3]~96_combout ; -wire \z80_|bus_control_|db[3]~20_combout ; -wire \z80_|bus_control_|db[3]~21_combout ; -wire \z80_|execute_|ctl_mWrite~4_combout ; -wire \z80_|execute_|ctl_apin_mux~2_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~61_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~63_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~64_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~65_combout ; +wire \ula_|zx_keyboard_|keys[7][2]~q ; +wire \ula_|zx_keyboard_|keys[6][2]~67_combout ; +wire \ula_|zx_keyboard_|keys[6][2]~68_combout ; +wire \ula_|zx_keyboard_|keys[6][2]~69_combout ; +wire \ula_|zx_keyboard_|keys[6][2]~q ; +wire \D[2]~36_combout ; +wire \ula_|zx_keyboard_|keys[4][2]~58_combout ; +wire \ula_|zx_keyboard_|keys[4][2]~130_combout ; +wire \ula_|zx_keyboard_|keys[4][2]~59_combout ; +wire \ula_|zx_keyboard_|keys[4][2]~q ; +wire \ula_|zx_keyboard_|keys[5][2]~56_combout ; +wire \ula_|zx_keyboard_|keys[5][2]~57_combout ; +wire \ula_|zx_keyboard_|keys[5][2]~q ; +wire \D[2]~35_combout ; +wire \ula_|zx_keyboard_|keys[0][2]~54_combout ; +wire \ula_|zx_keyboard_|keys[0][2]~55_combout ; +wire \ula_|zx_keyboard_|keys[0][2]~q ; +wire \ula_|zx_keyboard_|keys[3][2]~50_combout ; +wire \ula_|zx_keyboard_|keys[3][2]~51_combout ; +wire \ula_|zx_keyboard_|keys[3][2]~q ; +wire \ula_|zx_keyboard_|keys[2][2]~52_combout ; +wire \ula_|zx_keyboard_|keys[2][2]~53_combout ; +wire \ula_|zx_keyboard_|keys[2][2]~q ; +wire \D[2]~33_combout ; +wire \ula_|zx_keyboard_|keys[1][2]~47_combout ; +wire \ula_|zx_keyboard_|keys[1][2]~48_combout ; +wire \ula_|zx_keyboard_|keys[1][2]~q ; +wire \ula_|zx_keyboard_|key_row~1_combout ; +wire \D[2]~34_combout ; +wire \D[2]~37_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout ; +wire \ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ; +wire \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~3_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ; +wire \Selector0~0_combout ; +wire \Selector0~1_combout ; +wire \D[2]~82_combout ; +wire \D[2]~38_combout ; +wire \D[2]~39_combout ; +wire \z80_|bus_control_|db[2]~12_combout ; +wire \z80_|bus_control_|db[2]~13_combout ; +wire \z80_|pla_decode_|Equal1~4_combout ; +wire \z80_|execute_|ctl_alu_op_low~26_combout ; +wire \z80_|execute_|ctl_alu_op_low~45_combout ; +wire \z80_|execute_|setM1~17_combout ; +wire \z80_|execute_|setM1~18_combout ; +wire \z80_|execute_|setM1~11_combout ; +wire \z80_|execute_|setM1~10_combout ; +wire \z80_|execute_|setM1~12_combout ; +wire \z80_|execute_|setM1~8_combout ; +wire \z80_|execute_|setM1~9_combout ; +wire \z80_|execute_|setM1~13_combout ; +wire \z80_|execute_|setM1~15_combout ; +wire \z80_|execute_|setM1~14_combout ; +wire \z80_|execute_|setM1~16_combout ; +wire \z80_|execute_|setM1~19_combout ; +wire \z80_|execute_|setM1~23_combout ; +wire \z80_|execute_|setM1~22_combout ; +wire \z80_|execute_|setM1~56_combout ; +wire \z80_|execute_|setM1~24_combout ; +wire \z80_|execute_|setM1~25_combout ; +wire \z80_|execute_|setM1~26_combout ; +wire \z80_|execute_|setM1~27_combout ; +wire \z80_|execute_|setM1~28_combout ; +wire \z80_|execute_|setM1~55_combout ; +wire \z80_|execute_|setM1~29_combout ; +wire \z80_|execute_|setM1~31_combout ; +wire \z80_|execute_|setM1~33_combout ; +wire \z80_|execute_|setM1~32_combout ; +wire \z80_|execute_|setM1~34_combout ; +wire \z80_|execute_|setM1~20_combout ; +wire \z80_|execute_|setM1~21_combout ; +wire \z80_|execute_|setM1~35_combout ; +wire \z80_|execute_|setM1~43_combout ; +wire \z80_|execute_|setM1~44_combout ; +wire \z80_|execute_|setM1~45_combout ; +wire \z80_|execute_|setM1~46_combout ; +wire \z80_|execute_|setM1~52_combout ; +wire \z80_|sequencer_|SYNTHESIZED_WIRE_17~combout ; +wire \z80_|sequencer_|T6~q ; +wire \z80_|execute_|setM1~53_combout ; +wire \z80_|execute_|setM1~54_combout ; +wire \z80_|sequencer_|DFFE_M1_ff~0_combout ; +wire \z80_|sequencer_|DFFE_M1_ff~q ; +wire \z80_|resets_|x1~0_combout ; +wire \z80_|fpga_reset~feeder_combout ; +wire \z80_|fpga_reset~q ; +wire \z80_|fpga_reset~clkctrl_outclk ; +wire \z80_|resets_|x1~q ; +wire \z80_|resets_|x3~combout ; +wire \z80_|resets_|SYNTHESIZED_WIRE_12~q ; +wire \z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ; +wire \z80_|resets_|SYNTHESIZED_WIRE_10~q ; +wire \z80_|resets_|SYNTHESIZED_WIRE_9~feeder_combout ; +wire \z80_|resets_|SYNTHESIZED_WIRE_9~q ; +wire \z80_|resets_|DFFE_intr_ff3~q ; +wire \z80_|resets_|clrpc_int~0_combout ; +wire \z80_|resets_|clrpc_int~q ; +wire \z80_|resets_|clrpc~0_combout ; wire \z80_|address_pins_|DFFE_apin_latch[0]~0_combout ; -wire \D[0]~59_combout ; -wire \D[0]~60_combout ; -wire \D[1]~61_combout ; -wire \D[1]~62_combout ; -wire \D[2]~63_combout ; -wire \D[2]~64_combout ; -wire \D[3]~75_combout ; -wire \D[3]~76_combout ; -wire \D[4]~82_combout ; -wire \D[4]~83_combout ; -wire \D[6]~92_combout ; -wire \D[6]~93_combout ; +wire \D[0]~47_combout ; +wire \D[0]~48_combout ; +wire \D[1]~49_combout ; +wire \D[1]~50_combout ; +wire \D[2]~51_combout ; +wire \D[2]~52_combout ; +wire \D[3]~58_combout ; +wire \D[3]~59_combout ; +wire \D[4]~65_combout ; +wire \D[4]~66_combout ; +wire \D[6]~70_combout ; +wire \D[6]~71_combout ; wire \z80_|nM1_int~3_combout ; wire \z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q ; wire \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder_combout ; @@ -2489,33 +2477,43 @@ wire \ula_|i2c_loader_|divider[1]~6 ; wire \ula_|i2c_loader_|divider[2]~7_combout ; wire \ula_|i2c_loader_|divider[2]~8 ; wire \ula_|i2c_loader_|divider[3]~9_combout ; +wire \ula_|i2c_loader_|WideAnd0~0_combout ; wire \ula_|i2c_loader_|divider[3]~10 ; wire \ula_|i2c_loader_|divider[4]~11_combout ; wire \ula_|i2c_loader_|divider[4]~12 ; wire \ula_|i2c_loader_|divider[5]~13_combout ; -wire \ula_|i2c_loader_|WideAnd0~0_combout ; wire \ula_|i2c_loader_|WideAnd0~combout ; wire \ula_|i2c_loader_|state.Idle~q ; wire \ula_|i2c_loader_|phase~0_combout ; wire \ula_|i2c_loader_|phase~1_combout ; wire \ula_|i2c_loader_|nbit~5_combout ; -wire \ula_|i2c_loader_|thisbyte[0]~8_combout ; +wire \ula_|i2c_loader_|state.Idle~0_combout ; wire \ula_|i2c_loader_|Mux42~0_combout ; +wire \ula_|i2c_loader_|nbit~6_combout ; +wire \ula_|i2c_loader_|state.Done~0_combout ; +wire \ula_|i2c_loader_|state.Ack~0_combout ; +wire \ula_|i2c_loader_|state.Ack~1_combout ; +wire \ula_|i2c_loader_|state.Ack~q ; +wire \ula_|i2c_loader_|nbit[0]~2_combout ; wire \ula_|i2c_loader_|nbyte~4_combout ; wire \ula_|i2c_loader_|thisbyte[0]~7_combout ; wire \I2C_SDAT~input_o ; wire \ula_|i2c_loader_|nbyte[0]~1_combout ; wire \ula_|i2c_loader_|nbyte[0]~2_combout ; wire \ula_|i2c_loader_|nbyte[0]~3_combout ; -wire \ula_|i2c_loader_|state.Stop~0_combout ; -wire \ula_|i2c_loader_|state.Stop~1_combout ; -wire \ula_|i2c_loader_|state.Stop~q ; -wire \ula_|i2c_loader_|state.Idle~0_combout ; +wire \ula_|i2c_loader_|nbit[0]~1_combout ; +wire \ula_|i2c_loader_|nbit[0]~3_combout ; +wire \ula_|i2c_loader_|nbit[0]~4_combout ; wire \ula_|i2c_loader_|nbit~0_combout ; -wire \ula_|i2c_loader_|state.Done~0_combout ; -wire \ula_|i2c_loader_|state.Ack~0_combout ; -wire \ula_|i2c_loader_|state.Ack~1_combout ; -wire \ula_|i2c_loader_|state.Ack~q ; +wire \ula_|i2c_loader_|state.Done~1_combout ; +wire \ula_|i2c_loader_|state~27_combout ; +wire \ula_|i2c_loader_|state~24_combout ; +wire \ula_|i2c_loader_|state~26_combout ; +wire \ula_|i2c_loader_|state.Data~0_combout ; +wire \ula_|i2c_loader_|state.Data~q ; +wire \ula_|i2c_loader_|state.Done~2_combout ; +wire \ula_|i2c_loader_|state.Pause~1_combout ; +wire \ula_|i2c_loader_|thisbyte[0]~8_combout ; wire \ula_|i2c_loader_|nbyte[1]~5_combout ; wire \ula_|i2c_loader_|thisbyte[0]~18_combout ; wire \ula_|i2c_loader_|thisbyte[0]~9 ; @@ -2525,28 +2523,18 @@ wire \ula_|i2c_loader_|thisbyte[2]~12_combout ; wire \ula_|i2c_loader_|thisbyte[2]~13 ; wire \ula_|i2c_loader_|thisbyte[3]~14_combout ; wire \ula_|i2c_loader_|Equal2~0_combout ; -wire \ula_|i2c_loader_|state.Pause~0_combout ; wire \ula_|i2c_loader_|thisbyte[3]~15 ; wire \ula_|i2c_loader_|thisbyte[4]~16_combout ; -wire \ula_|i2c_loader_|state.Pause~1_combout ; -wire \ula_|i2c_loader_|state.Done~2_combout ; +wire \ula_|i2c_loader_|Equal2~1_combout ; +wire \ula_|i2c_loader_|state.Pause~0_combout ; wire \ula_|i2c_loader_|state.Pause~2_combout ; -wire \ula_|i2c_loader_|state.Pause~3_combout ; wire \ula_|i2c_loader_|state.Pause~q ; wire \ula_|i2c_loader_|state~25_combout ; wire \ula_|i2c_loader_|state.Start~q ; wire \ula_|i2c_loader_|nbyte~0_combout ; -wire \ula_|i2c_loader_|nbit[0]~1_combout ; -wire \ula_|i2c_loader_|nbit[0]~2_combout ; -wire \ula_|i2c_loader_|nbit[0]~3_combout ; -wire \ula_|i2c_loader_|nbit[0]~4_combout ; -wire \ula_|i2c_loader_|nbit~6_combout ; -wire \ula_|i2c_loader_|state.Done~1_combout ; -wire \ula_|i2c_loader_|state~27_combout ; -wire \ula_|i2c_loader_|state~24_combout ; -wire \ula_|i2c_loader_|state~26_combout ; -wire \ula_|i2c_loader_|state.Data~0_combout ; -wire \ula_|i2c_loader_|state.Data~q ; +wire \ula_|i2c_loader_|state.Stop~0_combout ; +wire \ula_|i2c_loader_|state.Stop~1_combout ; +wire \ula_|i2c_loader_|state.Stop~q ; wire \ula_|i2c_loader_|scl_out~0_combout ; wire \ula_|i2c_loader_|scl_out~_Duplicate_1_q ; wire \ula_|i2c_loader_|scl_out~1_combout ; @@ -2556,26 +2544,25 @@ wire \ula_|i2c_loader_|sda_out~_Duplicate_1_q ; wire \ula_|i2c_loader_|shiftreg~4_combout ; wire \ula_|i2c_loader_|Mux35~0_combout ; wire \ula_|i2c_loader_|shiftreg~13_combout ; -wire \ula_|i2c_loader_|shiftreg~14_combout ; wire \ula_|i2c_loader_|shiftreg~15_combout ; -wire \ula_|i2c_loader_|shiftreg[0]~24_combout ; -wire \ula_|i2c_loader_|shiftreg[0]~6_combout ; -wire \ula_|i2c_loader_|shiftreg[0]~7_combout ; -wire \ula_|i2c_loader_|shiftreg[0]~8_combout ; -wire \ula_|i2c_loader_|shiftreg~21_combout ; -wire \ula_|i2c_loader_|shiftreg~22_combout ; -wire \ula_|i2c_loader_|shiftreg~23_combout ; -wire \ula_|i2c_loader_|shiftreg[6]~10_combout ; -wire \ula_|i2c_loader_|shiftreg[6]~11_combout ; -wire \ula_|i2c_loader_|shiftreg~18_combout ; -wire \ula_|i2c_loader_|shiftreg~19_combout ; -wire \ula_|i2c_loader_|shiftreg~20_combout ; wire \ula_|i2c_loader_|shiftreg~16_combout ; wire \ula_|i2c_loader_|shiftreg~17_combout ; -wire \ula_|i2c_loader_|shiftreg~26_combout ; +wire \ula_|i2c_loader_|shiftreg~18_combout ; +wire \ula_|i2c_loader_|shiftreg~20_combout ; +wire \ula_|i2c_loader_|shiftreg~21_combout ; +wire \ula_|i2c_loader_|shiftreg[0]~23_combout ; +wire \ula_|i2c_loader_|shiftreg[0]~6_combout ; +wire \ula_|i2c_loader_|shiftreg[0]~7_combout ; +wire \ula_|i2c_loader_|shiftreg~22_combout ; +wire \ula_|i2c_loader_|shiftreg[6]~9_combout ; +wire \ula_|i2c_loader_|shiftreg[6]~10_combout ; +wire \ula_|i2c_loader_|shiftreg~19_combout ; wire \ula_|i2c_loader_|shiftreg~25_combout ; wire \ula_|i2c_loader_|shiftreg~12_combout ; -wire \ula_|i2c_loader_|shiftreg~9_combout ; +wire \ula_|i2c_loader_|shiftreg~14_combout ; +wire \ula_|i2c_loader_|shiftreg~24_combout ; +wire \ula_|i2c_loader_|shiftreg~11_combout ; +wire \ula_|i2c_loader_|shiftreg~8_combout ; wire \ula_|i2c_loader_|shiftreg[7]~5_combout ; wire \ula_|i2c_loader_|sda_out~0_combout ; wire \ula_|i2c_loader_|sda_out~1_combout ; @@ -2616,12 +2603,12 @@ wire \ula_|i2s_intf_|Add0~18_combout ; wire \ula_|i2s_intf_|lrdivider[9]~3_combout ; wire \ula_|i2s_intf_|Equal0~0_combout ; wire \ula_|i2s_intf_|Equal0~2_combout ; -wire \ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder_combout ; wire \ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ; wire \ula_|i2s_intf_|lrclk_r~0_combout ; wire \ula_|i2s_intf_|lrclk_r~q ; wire \ula_|i2s_intf_|lrclk_r~_Duplicate_1_q ; wire \ula_|i2s_intf_|bitcount[0]~5_combout ; +wire \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder_combout ; wire \ula_|i2s_intf_|bclk_r~_Duplicate_1_q ; wire \ula_|i2s_intf_|bitcount[4]~15_combout ; wire \ula_|i2s_intf_|bitcount[0]~6 ; @@ -2630,9 +2617,11 @@ wire \ula_|i2s_intf_|bitcount[1]~8 ; wire \ula_|i2s_intf_|bitcount[2]~9_combout ; wire \ula_|i2s_intf_|bitcount[2]~10 ; wire \ula_|i2s_intf_|bitcount[3]~11_combout ; -wire \ula_|i2s_intf_|LessThan0~0_combout ; wire \ula_|i2s_intf_|bitcount[3]~12 ; wire \ula_|i2s_intf_|bitcount[4]~13_combout ; +wire \ula_|i2s_intf_|LessThan0~0_combout ; +wire \ula_|i2s_intf_|shiftreg[4]~1_combout ; +wire \ula_|i2s_intf_|Add2~18_combout ; wire \ula_|i2s_intf_|Add2~7_cout ; wire \ula_|i2s_intf_|Add2~8_combout ; wire \ula_|i2s_intf_|Add2~20_combout ; @@ -2646,13 +2635,10 @@ wire \ula_|i2s_intf_|Add2~13 ; wire \ula_|i2s_intf_|Add2~14_combout ; wire \ula_|i2s_intf_|Add2~16_combout ; wire \ula_|i2s_intf_|Equal1~0_combout ; -wire \ula_|i2s_intf_|shiftreg[4]~1_combout ; -wire \ula_|i2s_intf_|Add2~18_combout ; wire \ula_|i2s_intf_|Equal1~1_combout ; wire \ula_|i2s_intf_|bclk_r~0_combout ; wire \ula_|i2s_intf_|bclk_r~1_combout ; wire \ula_|i2s_intf_|bclk_r~q ; -wire \ula_|pcm_outl[13]~feeder_combout ; wire \ula_|always0~2_combout ; wire \ula_|always0~3_combout ; wire \ula_|i2s_intf_|shiftreg[0]~19_combout ; @@ -2671,33 +2657,30 @@ wire \ula_|i2s_intf_|shiftreg~10_combout ; wire \ula_|i2s_intf_|shiftreg~9_combout ; wire \ula_|i2s_intf_|shiftreg~8_combout ; wire \ula_|i2s_intf_|shiftreg~7_combout ; -wire \ula_|i2s_intf_|PCM_INR[14]~0_combout ; wire \ula_|i2s_intf_|PCM_INL[14]~0_combout ; +wire \ula_|i2s_intf_|PCM_INR[14]~0_combout ; wire \ula_|pcm_outr~0_combout ; wire \ula_|i2s_intf_|shiftreg~6_combout ; wire \ula_|i2s_intf_|shiftreg~5_combout ; wire \ula_|i2s_intf_|shiftreg~4_combout ; wire \ula_|i2s_intf_|shiftreg~3_combout ; wire \ula_|i2s_intf_|shiftreg~0_combout ; -wire \ula_|video_|LessThan2~0_combout ; +wire \ula_|border[1]~feeder_combout ; +wire \ula_|video_|LessThan4~0_combout ; +wire \ula_|video_|screen_en~0_combout ; wire \ula_|video_|LessThan6~0_combout ; +wire \ula_|video_|LessThan6~1_combout ; +wire \ula_|video_|screen_en~1_combout ; +wire \ula_|video_|LessThan2~0_combout ; wire \ula_|video_|LessThan2~1_combout ; wire \ula_|video_|LessThan3~0_combout ; wire \ula_|video_|LessThan0~0_combout ; wire \ula_|video_|disp_enable~0_combout ; wire \ula_|video_|disp_enable~1_combout ; -wire \ula_|video_|LessThan6~1_combout ; -wire \ula_|video_|LessThan4~0_combout ; -wire \ula_|video_|screen_en~0_combout ; -wire \ula_|video_|screen_en~1_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 ; -wire \ula_|video_|attr_prefetch[1]~feeder_combout ; -wire \ula_|video_|Decoder0~1_combout ; -wire \ula_|video_|Decoder0~0_combout ; -wire \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 ; -wire \ula_|video_|attr_prefetch[4]~feeder_combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 ; wire \ula_|video_|attr_prefetch[7]~feeder_combout ; +wire \ula_|video_|Decoder0~1_combout ; +wire \ula_|video_|Decoder0~0_combout ; wire \ula_|video_|frame[0]~12_combout ; wire \ula_|video_|frame[1]~4_combout ; wire \ula_|video_|frame[1]~5 ; @@ -2706,11 +2689,12 @@ wire \ula_|video_|frame[2]~7 ; wire \ula_|video_|frame[3]~8_combout ; wire \ula_|video_|frame[3]~9 ; wire \ula_|video_|frame[4]~10_combout ; +wire \ula_|video_|frame[4]~feeder_combout ; wire \ula_|video_|inverted~combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 ; wire \ula_|video_|bits_prefetch[6]~feeder_combout ; wire \ula_|video_|Decoder0~2_combout ; -wire \ula_|video_|bits[6]~feeder_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 ; wire \ula_|video_|bits_prefetch[4]~feeder_combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 ; wire \ula_|video_|bits_prefetch[5]~feeder_combout ; @@ -2723,6 +2707,7 @@ wire \ula_|video_|bits_prefetch[2]~feeder_combout ; wire \ula_|video_|bits[2]~feeder_combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 ; wire \ula_|video_|bits_prefetch[0]~feeder_combout ; +wire \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 ; wire \ula_|video_|bits_prefetch[1]~feeder_combout ; wire \ula_|video_|bits[1]~feeder_combout ; wire \ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 ; @@ -2730,13 +2715,15 @@ wire \ula_|video_|bits_prefetch[3]~feeder_combout ; wire \ula_|video_|Mux0~2_combout ; wire \ula_|video_|Mux0~3_combout ; wire \ula_|video_|cindex[1]~0_combout ; +wire \ula_|video_|attr_prefetch[4]~feeder_combout ; +wire \ula_|video_|attr_prefetch[1]~feeder_combout ; wire \ula_|video_|cindex[1]~1_combout ; wire \ula_|video_|VGA_R[0]~0_combout ; wire \ula_|video_|attr_prefetch[6]~feeder_combout ; wire \ula_|video_|VGA_B[1]~0_combout ; wire \ula_|video_|VGA_R[1]~1_combout ; -wire \ula_|video_|attr_prefetch[2]~feeder_combout ; wire \ula_|video_|attr_prefetch[5]~feeder_combout ; +wire \ula_|video_|attr_prefetch[2]~feeder_combout ; wire \ula_|video_|cindex[2]~2_combout ; wire \ula_|video_|VGA_G[0]~0_combout ; wire \ula_|video_|VGA_G[1]~1_combout ; @@ -2761,42 +2748,24 @@ wire \z80_|memory_ifc_|nM1_out~combout ; wire \ula_|beep~0_combout ; wire \ula_|beep~q ; wire [0:0] \ram0|altsyncram_component|auto_generated|address_reg_a ; -wire [1:0] \ram1|altsyncram_component|auto_generated|address_reg_a ; wire [2:0] \ram1|altsyncram_component|auto_generated|decode3|w_anode244w ; -wire [2:0] \ram1|altsyncram_component|auto_generated|decode3|w_anode223w ; wire [2:0] \ula_|border ; wire [0:0] \ula_|clocks_|counter ; -wire [7:0] \ula_|i2c_loader_|shiftreg ; wire [1:0] \ula_|i2c_loader_|nbyte ; -wire [5:0] \ula_|i2c_loader_|divider ; -wire [17:0] \ula_|i2s_intf_|shiftreg ; wire [4:0] \ula_|i2s_intf_|bitcount ; -wire [15:0] \ula_|i2s_intf_|PCM_INR ; -wire [9:0] \ula_|video_|vga_vc ; wire [4:0] \ula_|video_|frame ; -wire [7:0] \ula_|video_|bits_prefetch ; wire [7:0] \ula_|video_|attr_prefetch ; -wire [7:0] \ula_|ps2_keyboard_|clk_filter ; -wire [7:0] \z80_|reg_file_|b2v_latch_af_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_bc2_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_bc_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_de2_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_de_lo|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_af_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_bc2_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_de2_hi|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_hl2_lo|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_hl_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_ir_lo|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_ix_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_iy_lo|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_pc_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_sp_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_wz_lo|latch ; -wire [3:0] \z80_|alu_|op2_low ; wire [3:0] \z80_|alu_|op1_low ; -wire [15:0] \z80_|address_latch_|Q ; -wire [15:0] \z80_|address_latch_|b2v_inst_inc_dec|address ; -wire [15:0] \z80_|address_pins_|DFFE_apin_latch ; -wire [7:0] \z80_|data_pins_|dout ; -wire [7:0] \z80_|ir_|opcode ; +wire [7:0] \z80_|reg_file_|b2v_latch_af2_hi|latch ; +wire [15:0] \z80_|address_latch_|abusz ; +wire [7:0] \z80_|data_pins_|SYNTHESIZED_WIRE_0 ; wire [0:0] \ram0|altsyncram_component|auto_generated|out_address_reg_a ; wire [1:0] \ram1|altsyncram_component|auto_generated|out_address_reg_a ; wire [2:0] \ram1|altsyncram_component|auto_generated|decode3|w_anode252w ; @@ -2815,13 +2784,11 @@ wire [7:0] \ula_|video_|bits ; wire [7:0] \ula_|video_|attr ; wire [8:0] \ula_|ps2_keyboard_|shiftreg ; wire [3:0] \ula_|ps2_keyboard_|bit_count ; -wire [7:0] \z80_|reg_file_|b2v_latch_af2_lo|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_af_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_bc2_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_bc_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_de2_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_de_hi|latch ; -wire [7:0] \z80_|reg_file_|b2v_latch_hl2_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_af_lo|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_bc2_lo|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_bc_lo|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_de2_lo|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_de_lo|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_hl_hi|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_ir_hi|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_ix_hi|latch ; @@ -2829,53 +2796,73 @@ wire [7:0] \z80_|reg_file_|b2v_latch_iy_hi|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_pc_hi|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_sp_hi|latch ; wire [7:0] \z80_|reg_file_|b2v_latch_wz_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_wz_lo|latch ; wire [3:0] \z80_|alu_|result_lo ; wire [3:0] \z80_|alu_|op2_high ; wire [3:0] \z80_|alu_|op1_high ; wire [3:0] \z80_|alu_|b2v_op1_latch_mux_high|Q ; -wire [7:0] \z80_|reg_file_|b2v_latch_af2_hi|latch ; -wire [15:0] \z80_|address_latch_|abusz ; -wire [7:0] \z80_|data_pins_|SYNTHESIZED_WIRE_0 ; +wire [15:0] \z80_|address_latch_|Q ; +wire [15:0] \z80_|address_latch_|b2v_inst_inc_dec|address ; +wire [15:0] \z80_|address_pins_|DFFE_apin_latch ; +wire [7:0] \z80_|data_pins_|dout ; +wire [7:0] \z80_|ir_|opcode ; +wire [1:0] \ram1|altsyncram_component|auto_generated|address_reg_a ; +wire [2:0] \ram1|altsyncram_component|auto_generated|decode3|w_anode223w ; +wire [7:0] \ula_|i2c_loader_|shiftreg ; +wire [5:0] \ula_|i2c_loader_|divider ; +wire [17:0] \ula_|i2s_intf_|shiftreg ; +wire [15:0] \ula_|i2s_intf_|PCM_INR ; +wire [9:0] \ula_|video_|vga_vc ; +wire [7:0] \ula_|video_|bits_prefetch ; +wire [7:0] \ula_|ps2_keyboard_|clk_filter ; +wire [7:0] \z80_|reg_file_|b2v_latch_af2_lo|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_bc_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_de_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_hl2_hi|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_ir_lo|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_iy_lo|latch ; +wire [7:0] \z80_|reg_file_|b2v_latch_sp_lo|latch ; +wire [3:0] \z80_|alu_|op2_low ; wire [4:0] \ula_|pll_|altpll_component|auto_generated|pll1_CLK_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a25_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ; -wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ; -wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; -wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; -wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; -wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a28_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ; @@ -2883,33 +2870,33 @@ wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_b wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a4_PORTBDATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ; -wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ; -wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a5_PORTBDATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a5_PORTBDATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ; -wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ; -wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus ; -wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ; +wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ; wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a31_PORTADATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ; -wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ; -wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus ; wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ; wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ; +wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus ; assign \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk [0] = \ula_|pll_|altpll_component|auto_generated|pll1_CLK_bus [0]; assign \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk [1] = \ula_|pll_|altpll_component|auto_generated|pll1_CLK_bus [1]; @@ -2917,82 +2904,82 @@ assign \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk [2] = \ula_|pll_ assign \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk [3] = \ula_|pll_|altpll_component|auto_generated|pll1_CLK_bus [3]; assign \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk [4] = \ula_|pll_|altpll_component|auto_generated|pll1_CLK_bus [4]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus [0]; - assign \ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus [0]; + assign \ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0]; assign \ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a25_PORTADATAOUT_bus [0]; assign \rom|altsyncram_component|auto_generated|ram_block1a9~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a1~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [0]; + assign \ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a1~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus [0]; -assign \ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a10~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a10~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus [0]; -assign \ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a8~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus [0]; +assign \ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a8~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; -assign \ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus [0]; +assign \ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; - -assign \ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus [0]; - -assign \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus [0]; assign \ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus [0]; - assign \ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus [0]; assign \ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a28_PORTADATAOUT_bus [0]; @@ -3007,60 +2994,60 @@ assign \rom|altsyncram_component|auto_generated|ram_block1a4~portadataout = \ro assign \ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus [0]; - assign \ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus [0]; + assign \ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus [0]; assign \ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus [0]; assign \rom|altsyncram_component|auto_generated|ram_block1a13~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|ram_block1a5~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus [0]; + assign \ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a5_PORTBDATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a5~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus [0]; -assign \ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus [0]; + +assign \ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a14~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a6~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|ram_block1a14~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus [0]; - -assign \ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus [0]; - -assign \rom|altsyncram_component|auto_generated|ram_block1a6~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus [0]; - -assign \ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus [0]; +assign \ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus [0]; assign \ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus [0]; -assign \ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus [0]; - assign \ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus [0]; assign \ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a31_PORTADATAOUT_bus [0]; assign \rom|altsyncram_component|auto_generated|ram_block1a15~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus [0]; -assign \ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus [0]; - -assign \ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus [0]; - assign \rom|altsyncram_component|auto_generated|ram_block1a7~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus [0]; assign \ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus [0]; +assign \ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus [0]; + +assign \ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus [0]; + // Location: IOOBUF_X53_Y21_N23 cycloneive_io_obuf \GPIO_1[0]~output ( .i(\z80_|address_pins_|DFFE_apin_latch [0]), @@ -3271,8 +3258,8 @@ defparam \GPIO_1[15]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y11_N9 cycloneive_io_obuf \GPIO_1[16]~output ( - .i(\D[0]~60_combout ), - .oe(\D[0]~107_combout ), + .i(\D[0]~48_combout ), + .oe(\D[0]~84_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[16]), @@ -3284,8 +3271,8 @@ defparam \GPIO_1[16]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y12_N2 cycloneive_io_obuf \GPIO_1[17]~output ( - .i(\D[1]~62_combout ), - .oe(\D[0]~107_combout ), + .i(\D[1]~50_combout ), + .oe(\D[0]~84_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[17]), @@ -3297,8 +3284,8 @@ defparam \GPIO_1[17]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y8_N23 cycloneive_io_obuf \GPIO_1[18]~output ( - .i(\D[2]~64_combout ), - .oe(\D[0]~107_combout ), + .i(\D[2]~52_combout ), + .oe(\D[0]~84_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[18]), @@ -3310,8 +3297,8 @@ defparam \GPIO_1[18]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y11_N2 cycloneive_io_obuf \GPIO_1[19]~output ( - .i(\D[3]~76_combout ), - .oe(\D[0]~107_combout ), + .i(\D[3]~59_combout ), + .oe(\D[0]~84_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[19]), @@ -3323,8 +3310,8 @@ defparam \GPIO_1[19]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y6_N16 cycloneive_io_obuf \GPIO_1[20]~output ( - .i(\D[4]~83_combout ), - .oe(\D[0]~107_combout ), + .i(\D[4]~66_combout ), + .oe(\D[0]~84_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[20]), @@ -3336,8 +3323,8 @@ defparam \GPIO_1[20]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y7_N9 cycloneive_io_obuf \GPIO_1[21]~output ( - .i(\D[5]~85_combout ), - .oe(\D[0]~107_combout ), + .i(\D[5]~68_combout ), + .oe(\D[0]~84_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[21]), @@ -3349,8 +3336,8 @@ defparam \GPIO_1[21]~output .open_drain_output = "false"; // Location: IOOBUF_X49_Y0_N2 cycloneive_io_obuf \GPIO_1[22]~output ( - .i(\D[6]~93_combout ), - .oe(\D[0]~107_combout ), + .i(\D[6]~71_combout ), + .oe(\D[0]~84_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[22]), @@ -3362,8 +3349,8 @@ defparam \GPIO_1[22]~output .open_drain_output = "false"; // Location: IOOBUF_X53_Y9_N23 cycloneive_io_obuf \GPIO_1[23]~output ( - .i(\D[7]~94_combout ), - .oe(\D[0]~107_combout ), + .i(\D[7]~72_combout ), + .oe(\D[0]~84_combout ), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), .o(GPIO_1[23]), @@ -4024,7 +4011,7 @@ defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl .cl defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: LCCOMB_X25_Y33_N4 +// Location: LCCOMB_X25_Y33_N0 cycloneive_lcell_comb \ula_|clocks_|counter[0]~0 ( // Equation(s): // \ula_|clocks_|counter[0]~0_combout = !\ula_|clocks_|counter [0] @@ -4041,7 +4028,7 @@ defparam \ula_|clocks_|counter[0]~0 .lut_mask = 16'h0F0F; defparam \ula_|clocks_|counter[0]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X25_Y33_N5 +// Location: FF_X25_Y33_N1 dffeas \ula_|clocks_|counter[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), .d(\ula_|clocks_|counter[0]~0_combout ), @@ -4070,7 +4057,7 @@ defparam \SW[2]~input .bus_hold = "false"; defparam \SW[2]~input .simulate_z_as = "z"; // synopsys translate_on -// Location: LCCOMB_X25_Y33_N10 +// Location: LCCOMB_X25_Y33_N4 cycloneive_lcell_comb \ula_|clocks_|clk_cpu~0 ( // Equation(s): // \ula_|clocks_|clk_cpu~0_combout = \ula_|clocks_|clk_cpu~q $ (((\SW[2]~input_o ) # (!\ula_|clocks_|counter [0]))) @@ -4087,7 +4074,7 @@ defparam \ula_|clocks_|clk_cpu~0 .lut_mask = 16'h0FC3; defparam \ula_|clocks_|clk_cpu~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X25_Y33_N11 +// Location: FF_X25_Y33_N5 dffeas \ula_|clocks_|clk_cpu ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), .d(\ula_|clocks_|clk_cpu~0_combout ), @@ -4106,7 +4093,7 @@ defparam \ula_|clocks_|clk_cpu .is_wysiwyg = "true"; defparam \ula_|clocks_|clk_cpu .power_up = "low"; // synopsys translate_on -// Location: CLKCTRL_G14 +// Location: CLKCTRL_G12 cycloneive_clkctrl \ula_|clocks_|clk_cpu~clkctrl ( .ena(vcc), .inclk({vcc,vcc,vcc,\ula_|clocks_|clk_cpu~q }), @@ -4119,38 +4106,34 @@ defparam \ula_|clocks_|clk_cpu~clkctrl .clock_type = "global clock"; defparam \ula_|clocks_|clk_cpu~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: LCCOMB_X32_Y17_N20 -cycloneive_lcell_comb \z80_|sequencer_|DFFE_M1_ff~0 ( +// Location: LCCOMB_X26_Y13_N30 +cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_15 ( // Equation(s): -// \z80_|sequencer_|DFFE_M1_ff~0_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # (\z80_|execute_|nextM~14_combout ))) - - .dataa(\z80_|execute_|setM1~52_combout ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|DFFE_M1_ff~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_M1_ff~0 .lut_mask = 16'hAAA0; -defparam \z80_|sequencer_|DFFE_M1_ff~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N12 -cycloneive_lcell_comb \z80_|sequencer_|ena_M ( -// Equation(s): -// \z80_|sequencer_|ena_M~combout = (\z80_|execute_|setM1~52_combout & !\z80_|execute_|nextM~14_combout ) +// \z80_|sequencer_|SYNTHESIZED_WIRE_15~combout = (\z80_|execute_|setM1~54_combout & (\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|execute_|nextM~14_combout )) .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|setM1~52_combout ), + .datab(\z80_|execute_|setM1~54_combout ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), .datad(\z80_|execute_|nextM~14_combout ), .cin(gnd), - .combout(\z80_|sequencer_|ena_M~combout ), + .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ), .cout()); // synopsys translate_off -defparam \z80_|sequencer_|ena_M .lut_mask = 16'h00F0; -defparam \z80_|sequencer_|ena_M .sum_lutc_input = "datac"; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_15 .lut_mask = 16'h00C0; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: CLKCTRL_G9 +cycloneive_clkctrl \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\z80_|resets_|SYNTHESIZED_WIRE_12~q }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk )); +// synopsys translate_off +defparam \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl .clock_type = "global clock"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl .ena_register_mode = "none"; // synopsys translate_on // Location: IOIBUF_X0_Y16_N8 @@ -4163,7 +4146,7 @@ defparam \KEY[1]~input .bus_hold = "false"; defparam \KEY[1]~input .simulate_z_as = "z"; // synopsys translate_on -// Location: LCCOMB_X24_Y15_N6 +// Location: LCCOMB_X27_Y13_N8 cycloneive_lcell_comb \z80_|interrupts_|nmi_armed~feeder ( // Equation(s): // \z80_|interrupts_|nmi_armed~feeder_combout = VCC @@ -4180,24 +4163,24 @@ defparam \z80_|interrupts_|nmi_armed~feeder .lut_mask = 16'hFFFF; defparam \z80_|interrupts_|nmi_armed~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y15_N2 +// Location: LCCOMB_X27_Y13_N4 cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_9 ( // Equation(s): // \z80_|interrupts_|SYNTHESIZED_WIRE_9~combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .dataa(gnd), .datab(gnd), - .datac(gnd), + .datac(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .cin(gnd), .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_9~combout ), .cout()); // synopsys translate_off -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_9 .lut_mask = 16'hAAFF; +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_9 .lut_mask = 16'hF0FF; defparam \z80_|interrupts_|SYNTHESIZED_WIRE_9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y15_N7 +// Location: FF_X27_Y13_N9 dffeas \z80_|interrupts_|nmi_armed ( .clk(!\KEY[1]~input_o ), .d(\z80_|interrupts_|nmi_armed~feeder_combout ), @@ -4216,7 +4199,7 @@ defparam \z80_|interrupts_|nmi_armed .is_wysiwyg = "true"; defparam \z80_|interrupts_|nmi_armed .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y15_N12 +// Location: LCCOMB_X28_Y13_N0 cycloneive_lcell_comb \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder ( // Equation(s): // \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder_combout = \z80_|interrupts_|nmi_armed~q @@ -4233,58 +4216,60 @@ defparam \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder .lut_mask = 16'hFF00 defparam \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_eval_cond~0 ( +// Location: LCCOMB_X26_Y13_N22 +cycloneive_lcell_comb \z80_|sequencer_|DFFE_M2_ff~0 ( // Equation(s): -// \z80_|execute_|ctl_eval_cond~0_combout = (\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) +// \z80_|sequencer_|DFFE_M2_ff~0_combout = (\z80_|execute_|setM1~54_combout & ((\z80_|execute_|nextM~14_combout & (!\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|DFFE_M2_ff~q ))))) - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|execute_|setM1~54_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|execute_|nextM~14_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_eval_cond~0_combout ), + .combout(\z80_|sequencer_|DFFE_M2_ff~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_eval_cond~0 .lut_mask = 16'h00F0; -defparam \z80_|execute_|ctl_eval_cond~0 .sum_lutc_input = "datac"; +defparam \z80_|sequencer_|DFFE_M2_ff~0 .lut_mask = 16'h44C0; +defparam \z80_|sequencer_|DFFE_M2_ff~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X41_Y18_N0 -cycloneive_lcell_comb \z80_|execute_|ixy_d~4 ( -// Equation(s): -// \z80_|execute_|ixy_d~4_combout = (!\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~4_combout ), - .cout()); +// Location: FF_X26_Y13_N23 +dffeas \z80_|sequencer_|DFFE_M2_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|DFFE_M2_ff~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_M2_ff~q ), + .prn(vcc)); // synopsys translate_off -defparam \z80_|execute_|ixy_d~4 .lut_mask = 16'h1100; -defparam \z80_|execute_|ixy_d~4 .sum_lutc_input = "datac"; +defparam \z80_|sequencer_|DFFE_M2_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_M2_ff .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y17_N30 +// Location: LCCOMB_X26_Y13_N6 cycloneive_lcell_comb \z80_|sequencer_|DFFE_M3_ff~0 ( // Equation(s): -// \z80_|sequencer_|DFFE_M3_ff~0_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|DFFE_M3_ff~q ))))) +// \z80_|sequencer_|DFFE_M3_ff~0_combout = (\z80_|execute_|setM1~54_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|DFFE_M3_ff~q ))))) - .dataa(\z80_|execute_|setM1~52_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|execute_|setM1~54_combout ), .datac(\z80_|sequencer_|DFFE_M3_ff~q ), .datad(\z80_|execute_|nextM~14_combout ), .cin(gnd), .combout(\z80_|sequencer_|DFFE_M3_ff~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|sequencer_|DFFE_M3_ff~0 .lut_mask = 16'h88A0; +defparam \z80_|sequencer_|DFFE_M3_ff~0 .lut_mask = 16'h88C0; defparam \z80_|sequencer_|DFFE_M3_ff~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y17_N31 +// Location: FF_X26_Y13_N7 dffeas \z80_|sequencer_|DFFE_M3_ff ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|sequencer_|DFFE_M3_ff~0_combout ), @@ -4303,41 +4288,24 @@ defparam \z80_|sequencer_|DFFE_M3_ff .is_wysiwyg = "true"; defparam \z80_|sequencer_|DFFE_M3_ff .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X37_Y18_N12 -cycloneive_lcell_comb \z80_|execute_|fIOWrite~1 ( -// Equation(s): -// \z80_|execute_|fIOWrite~1_combout = (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|execute_|ixy_d~4_combout ))) - - .dataa(\z80_|execute_|ixy_d~4_combout ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|fIOWrite~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIOWrite~1 .lut_mask = 16'hD0D0; -defparam \z80_|execute_|fIOWrite~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N2 +// Location: LCCOMB_X26_Y13_N10 cycloneive_lcell_comb \z80_|sequencer_|DFFE_M4_ff~0 ( // Equation(s): -// \z80_|sequencer_|DFFE_M4_ff~0_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|DFFE_M4_ff~q ))))) +// \z80_|sequencer_|DFFE_M4_ff~0_combout = (\z80_|execute_|setM1~54_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|DFFE_M4_ff~q ))))) - .dataa(\z80_|execute_|setM1~52_combout ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|execute_|setM1~54_combout ), .datac(\z80_|sequencer_|DFFE_M4_ff~q ), .datad(\z80_|execute_|nextM~14_combout ), .cin(gnd), .combout(\z80_|sequencer_|DFFE_M4_ff~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|sequencer_|DFFE_M4_ff~0 .lut_mask = 16'h88A0; +defparam \z80_|sequencer_|DFFE_M4_ff~0 .lut_mask = 16'h88C0; defparam \z80_|sequencer_|DFFE_M4_ff~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y17_N3 +// Location: FF_X26_Y13_N11 dffeas \z80_|sequencer_|DFFE_M4_ff ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|sequencer_|DFFE_M4_ff~0_combout ), @@ -4356,1685 +4324,24 @@ defparam \z80_|sequencer_|DFFE_M4_ff .is_wysiwyg = "true"; defparam \z80_|sequencer_|DFFE_M4_ff .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y11_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal32~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal32~0_combout = (\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4]) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [3]), - .datac(gnd), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal32~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal32~0 .lut_mask = 16'h00CC; -defparam \z80_|pla_decode_|Equal32~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N14 -cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_11 ( -// Equation(s): -// \z80_|resets_|SYNTHESIZED_WIRE_11~combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_11 .lut_mask = 16'hFF33; -defparam \z80_|resets_|SYNTHESIZED_WIRE_11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N10 -cycloneive_lcell_comb \z80_|decode_state_|table_xx~0 ( -// Equation(s): -// \z80_|decode_state_|table_xx~0_combout = (\z80_|decode_state_|DFFE_instED~q ) # (\z80_|decode_state_|DFFE_instCB~q ) - - .dataa(\z80_|decode_state_|DFFE_instED~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|decode_state_|DFFE_instCB~q ), - .cin(gnd), - .combout(\z80_|decode_state_|table_xx~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|table_xx~0 .lut_mask = 16'hFFAA; -defparam \z80_|decode_state_|table_xx~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N10 -cycloneive_lcell_comb \z80_|pla_decode_|Equal1~7 ( -// Equation(s): -// \z80_|pla_decode_|Equal1~7_combout = (\z80_|ir_|opcode [7] & (!\z80_|decode_state_|table_xx~0_combout & (\z80_|ir_|opcode [0] & \z80_|ir_|opcode [6]))) - - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|decode_state_|table_xx~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|ir_|opcode [6]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal1~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal1~7 .lut_mask = 16'h2000; -defparam \z80_|pla_decode_|Equal1~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N20 -cycloneive_lcell_comb \z80_|pla_decode_|Equal2~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal2~0_combout = (!\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal2~0 .lut_mask = 16'h0F00; -defparam \z80_|pla_decode_|Equal2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N12 -cycloneive_lcell_comb \z80_|pla_decode_|Equal36~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal36~0_combout = (\z80_|pla_decode_|Equal1~7_combout & (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal32~0_combout & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~7_combout ), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|pla_decode_|Equal32~0_combout ), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal36~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal36~0 .lut_mask = 16'h2000; -defparam \z80_|pla_decode_|Equal36~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_cb_set ( -// Equation(s): -// \z80_|execute_|ctl_state_tbl_cb_set~combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|pla_decode_|Equal41~2_combout ) # ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal36~0_combout )))) # -// (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|pla_decode_|Equal36~0_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|pla_decode_|Equal41~2_combout ), - .datad(\z80_|pla_decode_|Equal36~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_tbl_cb_set~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_tbl_cb_set .lut_mask = 16'hB3A0; -defparam \z80_|execute_|ctl_state_tbl_cb_set .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_state_tbl_we~8_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # ((\z80_|sequencer_|DFFE_T3_ff~q & \z80_|pla_decode_|Equal41~2_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|pla_decode_|Equal41~2_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_tbl_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_tbl_we~8 .lut_mask = 16'h00EA; -defparam \z80_|execute_|ctl_state_tbl_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X41_Y17_N29 -dffeas \z80_|decode_state_|DFFE_instCB ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_state_tbl_cb_set~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_state_tbl_we~8_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|decode_state_|DFFE_instCB~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instCB .is_wysiwyg = "true"; -defparam \z80_|decode_state_|DFFE_instCB .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal52~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal52~0_combout = (\z80_|ir_|opcode [7] & (!\z80_|decode_state_|DFFE_instCB~q & (\z80_|ir_|opcode [6] & !\z80_|decode_state_|DFFE_instED~q ))) - - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|decode_state_|DFFE_instCB~q ), - .datac(\z80_|ir_|opcode [6]), - .datad(\z80_|decode_state_|DFFE_instED~q ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal52~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal52~0 .lut_mask = 16'h0020; -defparam \z80_|pla_decode_|Equal52~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal2~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal2~1_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal32~0_combout & \z80_|pla_decode_|Equal52~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|pla_decode_|Equal32~0_combout ), - .datad(\z80_|pla_decode_|Equal52~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal2~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal2~1 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal2~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_ed_set ( -// Equation(s): -// \z80_|execute_|ctl_state_tbl_ed_set~combout = (\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal2~1_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & !\z80_|ir_|opcode [1]))) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|pla_decode_|Equal2~1_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_tbl_ed_set~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_tbl_ed_set .lut_mask = 16'h0008; -defparam \z80_|execute_|ctl_state_tbl_ed_set .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X41_Y17_N17 -dffeas \z80_|decode_state_|DFFE_instED ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_state_tbl_ed_set~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_state_tbl_we~8_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|decode_state_|DFFE_instED~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instED .is_wysiwyg = "true"; -defparam \z80_|decode_state_|DFFE_instED .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal13~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal13~0_combout = (!\z80_|ir_|opcode [7] & (\z80_|ir_|opcode [6] & \z80_|decode_state_|DFFE_instED~q )) - - .dataa(\z80_|ir_|opcode [7]), - .datab(gnd), - .datac(\z80_|ir_|opcode [6]), - .datad(\z80_|decode_state_|DFFE_instED~q ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal13~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal13~0 .lut_mask = 16'h5000; -defparam \z80_|pla_decode_|Equal13~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal33~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal33~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1])) - - .dataa(\z80_|ir_|opcode [0]), - .datab(gnd), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal33~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal33~0 .lut_mask = 16'h5000; -defparam \z80_|pla_decode_|Equal33~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_im_we ( -// Equation(s): -// \z80_|execute_|ctl_im_we~combout = (\z80_|pla_decode_|Equal13~0_combout & (\z80_|sequencer_|DFFE_T3_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|pla_decode_|Equal33~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_im_we~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_im_we .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_im_we .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N18 -cycloneive_lcell_comb \z80_|pla_decode_|Equal49~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal49~0_combout = (!\z80_|decode_state_|in_halt~q & (\z80_|pla_decode_|Equal77~0_combout & \z80_|pla_decode_|Equal33~0_combout )) - - .dataa(gnd), - .datab(\z80_|decode_state_|in_halt~q ), - .datac(\z80_|pla_decode_|Equal77~0_combout ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal49~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal49~0 .lut_mask = 16'h3000; -defparam \z80_|pla_decode_|Equal49~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N2 -cycloneive_lcell_comb \z80_|pla_decode_|Equal33~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal33~1_combout = (\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [5] & !\z80_|ir_|opcode [3])) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|ir_|opcode [3]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal33~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal33~1 .lut_mask = 16'h0808; -defparam \z80_|pla_decode_|Equal33~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N30 -cycloneive_lcell_comb \z80_|pla_decode_|Equal6~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal6~0_combout = (!\z80_|ir_|opcode [7] & (!\z80_|decode_state_|DFFE_instCB~q & (!\z80_|ir_|opcode [6] & !\z80_|decode_state_|DFFE_instED~q ))) - - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|decode_state_|DFFE_instCB~q ), - .datac(\z80_|ir_|opcode [6]), - .datad(\z80_|decode_state_|DFFE_instED~q ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal6~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal6~0 .lut_mask = 16'h0001; -defparam \z80_|pla_decode_|Equal6~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~14 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~14_combout = (!\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal6~0_combout )) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~14 .lut_mask = 16'h4400; -defparam \z80_|execute_|ctl_mRead~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N18 -cycloneive_lcell_comb \z80_|pla_decode_|Equal12~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal12~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2]))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal12~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal12~0 .lut_mask = 16'h0040; -defparam \z80_|pla_decode_|Equal12~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~8 ( -// Equation(s): -// \z80_|execute_|ctl_sw_1d~8_combout = (((!\z80_|ir_|opcode [4] & \z80_|ir_|opcode [5])) # (!\z80_|pla_decode_|Equal12~0_combout )) # (!\z80_|ir_|opcode [3]) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal12~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~8 .lut_mask = 16'h4FFF; -defparam \z80_|execute_|ctl_sw_1d~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N12 -cycloneive_lcell_comb \z80_|nM1_int~2 ( -// Equation(s): -// \z80_|nM1_int~2_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|nM1_int~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|nM1_int~2 .lut_mask = 16'h0055; -defparam \z80_|nM1_int~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~5 ( -// Equation(s): -// \z80_|execute_|ctl_sw_1d~5_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal49~0_combout ) # ((\z80_|execute_|ctl_mRead~14_combout ) # (!\z80_|execute_|ctl_sw_1d~8_combout )))) - - .dataa(\z80_|pla_decode_|Equal49~0_combout ), - .datab(\z80_|execute_|ctl_mRead~14_combout ), - .datac(\z80_|execute_|ctl_sw_1d~8_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~5 .lut_mask = 16'hEF00; -defparam \z80_|execute_|ctl_sw_1d~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal3~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal3~0_combout = (\z80_|ir_|opcode [3] & \z80_|ir_|opcode [4]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal3~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal3~0 .lut_mask = 16'hF000; -defparam \z80_|pla_decode_|Equal3~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~4 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~4_combout = (\z80_|pla_decode_|Equal1~7_combout & (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal3~0_combout & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~7_combout ), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|pla_decode_|Equal3~0_combout ), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~4 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_mRead~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|ixy_d~7 ( -// Equation(s): -// \z80_|execute_|ixy_d~7_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M3_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~7 .lut_mask = 16'h0F00; -defparam \z80_|execute_|ixy_d~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~4 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~4_combout = (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~4 .lut_mask = 16'hA0A0; -defparam \z80_|execute_|ctl_state_alu~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~4 ( -// Equation(s): -// \z80_|execute_|ctl_sw_1d~4_combout = (\z80_|execute_|ctl_mRead~5_combout & (!\z80_|execute_|ctl_state_alu~4_combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|execute_|ctl_mRead~4_combout )))) # (!\z80_|execute_|ctl_mRead~5_combout & -// (((!\z80_|execute_|ixy_d~7_combout )) # (!\z80_|execute_|ctl_mRead~4_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~5_combout ), - .datab(\z80_|execute_|ctl_mRead~4_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~4 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_sw_1d~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N10 -cycloneive_lcell_comb \z80_|pla_decode_|Equal40~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal40~1_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal40~0_combout & \z80_|ir_|opcode [5])) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal40~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal40~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal40~1 .lut_mask = 16'h8080; -defparam \z80_|pla_decode_|Equal40~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal39~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal39~0_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal40~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal3~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal40~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal3~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal39~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal39~0 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal39~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~1 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~1_combout = (!\z80_|pla_decode_|Equal40~1_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal39~0_combout )) - - .dataa(\z80_|pla_decode_|Equal40~1_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~1 .lut_mask = 16'h0005; -defparam \z80_|execute_|ctl_bus_db_oe~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N26 -cycloneive_lcell_comb \z80_|pla_decode_|Equal13~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal13~1_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1])) - - .dataa(\z80_|ir_|opcode [0]), - .datab(gnd), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal13~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal13~1 .lut_mask = 16'hA000; -defparam \z80_|pla_decode_|Equal13~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal13~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal13~2_combout = (\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|pla_decode_|Equal13~1_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal13~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal13~2 .lut_mask = 16'h2000; -defparam \z80_|pla_decode_|Equal13~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal3~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal3~2_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal3~0_combout & \z80_|pla_decode_|Equal52~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|pla_decode_|Equal3~0_combout ), - .datad(\z80_|pla_decode_|Equal52~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal3~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal3~2 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal3~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_state_iy_set~2 ( -// Equation(s): -// \z80_|execute_|ctl_state_iy_set~2_combout = (\z80_|ir_|opcode [5] & (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal3~2_combout & \z80_|sequencer_|DFFE_T2_ff~q ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|pla_decode_|Equal3~2_combout ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_iy_set~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_iy_set~2 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_state_iy_set~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N26 -cycloneive_lcell_comb \z80_|execute_|ixy_d~8 ( -// Equation(s): -// \z80_|execute_|ixy_d~8_combout = (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T5_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|sequencer_|DFFE_T5_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~8 .lut_mask = 16'hC0C0; -defparam \z80_|execute_|ixy_d~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ixy_d~6 ( -// Equation(s): -// \z80_|execute_|ixy_d~6_combout = (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~6 .lut_mask = 16'hF000; -defparam \z80_|execute_|ixy_d~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N6 -cycloneive_lcell_comb \z80_|execute_|ixy_d~9 ( -// Equation(s): -// \z80_|execute_|ixy_d~9_combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_M3_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~9 .lut_mask = 16'hF000; -defparam \z80_|execute_|ixy_d~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N8 -cycloneive_lcell_comb \z80_|execute_|ixy_d~12 ( -// Equation(s): -// \z80_|execute_|ixy_d~12_combout = (!\z80_|execute_|ixy_d~7_combout & (!\z80_|execute_|ixy_d~8_combout & (!\z80_|execute_|ixy_d~6_combout & !\z80_|execute_|ixy_d~9_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ixy_d~8_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|execute_|ixy_d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~12 .lut_mask = 16'h0001; -defparam \z80_|execute_|ixy_d~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N22 -cycloneive_lcell_comb \z80_|execute_|ixy_d~10 ( -// Equation(s): -// \z80_|execute_|ixy_d~10_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|pla_decode_|Equal3~1_combout ), - .datac(\z80_|decode_state_|use_ixiy~combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~10 .lut_mask = 16'h8000; -defparam \z80_|execute_|ixy_d~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal44~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal44~0_combout = (\z80_|ir_|opcode [7] & (!\z80_|decode_state_|DFFE_instCB~q & (!\z80_|ir_|opcode [6] & !\z80_|decode_state_|DFFE_instED~q ))) - - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|decode_state_|DFFE_instCB~q ), - .datac(\z80_|ir_|opcode [6]), - .datad(\z80_|decode_state_|DFFE_instED~q ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal44~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal44~0 .lut_mask = 16'h0002; -defparam \z80_|pla_decode_|Equal44~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N0 -cycloneive_lcell_comb \z80_|execute_|ixy_d~16 ( -// Equation(s): -// \z80_|execute_|ixy_d~16_combout = (\z80_|pla_decode_|Equal44~0_combout & (\z80_|pla_decode_|Equal33~0_combout & ((\z80_|decode_state_|DFFE_inst4~q ) # (\z80_|decode_state_|DFFE_instIY1~q )))) - - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(\z80_|pla_decode_|Equal44~0_combout ), - .datac(\z80_|decode_state_|DFFE_instIY1~q ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~16 .lut_mask = 16'hC800; -defparam \z80_|execute_|ixy_d~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N28 -cycloneive_lcell_comb \z80_|execute_|ixy_d~13 ( -// Equation(s): -// \z80_|execute_|ixy_d~13_combout = (\z80_|pla_decode_|Equal41~2_combout ) # ((\z80_|execute_|ixy_d~10_combout ) # (\z80_|execute_|ixy_d~16_combout )) - - .dataa(gnd), - .datab(\z80_|pla_decode_|Equal41~2_combout ), - .datac(\z80_|execute_|ixy_d~10_combout ), - .datad(\z80_|execute_|ixy_d~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~13 .lut_mask = 16'hFFFC; -defparam \z80_|execute_|ixy_d~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal50~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal50~0_combout = (!\z80_|decode_state_|in_halt~q & (\z80_|pla_decode_|Equal77~0_combout & \z80_|pla_decode_|Equal33~1_combout )) - - .dataa(gnd), - .datab(\z80_|decode_state_|in_halt~q ), - .datac(\z80_|pla_decode_|Equal77~0_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal50~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal50~0 .lut_mask = 16'h3000; -defparam \z80_|pla_decode_|Equal50~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal33~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal33~2_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal6~0_combout )) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal33~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal33~2 .lut_mask = 16'h8800; -defparam \z80_|pla_decode_|Equal33~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N30 -cycloneive_lcell_comb \z80_|execute_|ixy_d~17 ( -// Equation(s): -// \z80_|execute_|ixy_d~17_combout = (\z80_|decode_state_|DFFE_inst4~q & (!\z80_|pla_decode_|Equal50~0_combout & ((!\z80_|pla_decode_|Equal33~2_combout )))) # (!\z80_|decode_state_|DFFE_inst4~q & (((!\z80_|pla_decode_|Equal50~0_combout & -// !\z80_|pla_decode_|Equal33~2_combout )) # (!\z80_|decode_state_|DFFE_instIY1~q ))) - - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(\z80_|pla_decode_|Equal50~0_combout ), - .datac(\z80_|decode_state_|DFFE_instIY1~q ), - .datad(\z80_|pla_decode_|Equal33~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~17 .lut_mask = 16'h0537; -defparam \z80_|execute_|ixy_d~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N16 -cycloneive_lcell_comb \z80_|execute_|ixy_d~5 ( -// Equation(s): -// \z80_|execute_|ixy_d~5_combout = (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_M3_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~5 .lut_mask = 16'hF000; -defparam \z80_|execute_|ixy_d~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N22 -cycloneive_lcell_comb \z80_|execute_|ixy_d~14 ( -// Equation(s): -// \z80_|execute_|ixy_d~14_combout = (\z80_|execute_|ixy_d~12_combout & (((!\z80_|execute_|ixy_d~13_combout & \z80_|execute_|ixy_d~17_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) # (!\z80_|execute_|ixy_d~12_combout & -// (!\z80_|execute_|ixy_d~13_combout & (\z80_|execute_|ixy_d~17_combout ))) - - .dataa(\z80_|execute_|ixy_d~12_combout ), - .datab(\z80_|execute_|ixy_d~13_combout ), - .datac(\z80_|execute_|ixy_d~17_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~14 .lut_mask = 16'h30BA; -defparam \z80_|execute_|ixy_d~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N18 -cycloneive_lcell_comb \z80_|execute_|ixy_d~11 ( -// Equation(s): -// \z80_|execute_|ixy_d~11_combout = (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T5_ff~q ) # ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|execute_|ixy_d~4_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|execute_|ixy_d~4_combout ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~11 .lut_mask = 16'hCC8C; -defparam \z80_|execute_|ixy_d~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N12 -cycloneive_lcell_comb \z80_|execute_|ixy_d~15 ( -// Equation(s): -// \z80_|execute_|ixy_d~15_combout = ((\z80_|pla_decode_|Equal49~0_combout & (\z80_|decode_state_|use_ixiy~combout & \z80_|execute_|ixy_d~11_combout ))) # (!\z80_|execute_|ixy_d~14_combout ) - - .dataa(\z80_|pla_decode_|Equal49~0_combout ), - .datab(\z80_|decode_state_|use_ixiy~combout ), - .datac(\z80_|execute_|ixy_d~14_combout ), - .datad(\z80_|execute_|ixy_d~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ixy_d~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ixy_d~15 .lut_mask = 16'h8F0F; -defparam \z80_|execute_|ixy_d~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_state_ixiy_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_state_ixiy_we~2_combout = (\z80_|sequencer_|DFFE_T5_ff~q & ((\z80_|execute_|ixy_d~15_combout ) # ((\z80_|sequencer_|DFFE_T2_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )))) # (!\z80_|sequencer_|DFFE_T5_ff~q & -// (\z80_|sequencer_|DFFE_T2_ff~q & ((!\z80_|sequencer_|DFFE_M1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|execute_|ixy_d~15_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_ixiy_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_ixiy_we~2 .lut_mask = 16'hA0EC; -defparam \z80_|execute_|ctl_state_ixiy_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y15_N23 -dffeas \z80_|decode_state_|DFFE_instIY1 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_state_iy_set~2_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_state_ixiy_we~2_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|decode_state_|DFFE_instIY1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instIY1 .is_wysiwyg = "true"; -defparam \z80_|decode_state_|DFFE_instIY1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~5_combout = (!\z80_|decode_state_|DFFE_inst4~q & (!\z80_|decode_state_|DFFE_instIY1~q & \z80_|decode_state_|DFFE_instCB~q )) - - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(gnd), - .datac(\z80_|decode_state_|DFFE_instIY1~q ), - .datad(\z80_|decode_state_|DFFE_instCB~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~5 .lut_mask = 16'h0500; -defparam \z80_|execute_|ctl_ir_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~14 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~14_combout = (!\z80_|ir_|opcode [6] & (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) - - .dataa(\z80_|ir_|opcode [6]), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|execute_|ctl_ir_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~14 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_ir_we~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~2 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~2_combout = (\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [6] & (\z80_|ir_|opcode [7] & \z80_|decode_state_|DFFE_instED~q ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|ir_|opcode [6]), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|decode_state_|DFFE_instED~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~2 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_mWrite~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~16 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~16_combout = (\z80_|ir_|opcode [1] & (\z80_|execute_|ctl_mWrite~2_combout & (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [0]))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~16 .lut_mask = 16'h0008; -defparam \z80_|execute_|ctl_mWrite~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~18 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~18_combout = (((!\z80_|execute_|ctl_ir_we~14_combout & !\z80_|execute_|ctl_mWrite~16_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|sequencer_|DFFE_T4_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|execute_|ctl_ir_we~14_combout ), - .datad(\z80_|execute_|ctl_mWrite~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~18 .lut_mask = 16'h777F; -defparam \z80_|execute_|ctl_flags_alu~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~26 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~26_combout = (\z80_|pla_decode_|Equal13~2_combout & !\z80_|ir_|opcode [3]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~26 .lut_mask = 16'h00F0; -defparam \z80_|execute_|ctl_mRead~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~27 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~27_combout = (\z80_|pla_decode_|Equal13~2_combout & \z80_|ir_|opcode [3]) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(gnd), - .datac(\z80_|ir_|opcode [3]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~27 .lut_mask = 16'hA0A0; -defparam \z80_|execute_|ctl_mRead~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~7 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~7_combout = (\z80_|execute_|ctl_flags_alu~18_combout & (((!\z80_|execute_|ctl_mRead~26_combout & !\z80_|execute_|ctl_mRead~27_combout )) # (!\z80_|execute_|ixy_d~9_combout ))) - - .dataa(\z80_|execute_|ctl_flags_alu~18_combout ), - .datab(\z80_|execute_|ctl_mRead~26_combout ), - .datac(\z80_|execute_|ctl_mRead~27_combout ), - .datad(\z80_|execute_|ixy_d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~7 .lut_mask = 16'h02AA; -defparam \z80_|execute_|ctl_bus_db_oe~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~5 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~5_combout = (\z80_|execute_|ctl_bus_db_oe~7_combout & (((\z80_|execute_|ctl_bus_db_oe~1_combout & !\z80_|pla_decode_|Equal13~2_combout )) # (!\z80_|execute_|ixy_d~7_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~5 .lut_mask = 16'h5D00; -defparam \z80_|execute_|ctl_sw_2d~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~18 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~18_combout = (!\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal12~0_combout ))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal12~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~18 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_mRead~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N12 -cycloneive_lcell_comb \z80_|pla_decode_|Equal55~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal55~0_combout = (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1])) - - .dataa(\z80_|ir_|opcode [0]), - .datab(gnd), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal55~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal55~0 .lut_mask = 16'h0500; -defparam \z80_|pla_decode_|Equal55~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|comb~1 ( -// Equation(s): -// \z80_|execute_|comb~1_combout = (\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4]) - - .dataa(\z80_|ir_|opcode [5]), - .datab(gnd), - .datac(\z80_|ir_|opcode [4]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|comb~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|comb~1 .lut_mask = 16'hA0A0; -defparam \z80_|execute_|comb~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~15 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~15_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [3] & \z80_|execute_|comb~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|execute_|comb~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~15 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_mRead~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~17 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~17_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~17 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_mRead~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~5_combout = ((!\z80_|execute_|ctl_mRead~18_combout & (!\z80_|execute_|ctl_mRead~15_combout & !\z80_|execute_|ctl_mRead~17_combout ))) # (!\z80_|execute_|ixy_d~6_combout ) - - .dataa(\z80_|execute_|ctl_mRead~18_combout ), - .datab(\z80_|execute_|ctl_mRead~15_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|execute_|ctl_mRead~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~5 .lut_mask = 16'h0F1F; -defparam \z80_|execute_|ctl_reg_in_hi~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~9 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~9_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal55~0_combout & \z80_|pla_decode_|Equal33~1_combout )) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~9 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_mRead~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal9~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal9~0_combout = (!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal9~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal9~0 .lut_mask = 16'h000F; -defparam \z80_|pla_decode_|Equal9~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~10 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~10_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal55~0_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal9~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal9~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~10 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_mRead~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~8 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~8_combout = (\z80_|pla_decode_|Equal13~0_combout & (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~8 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_mRead~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~20 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~20_combout = (\z80_|execute_|ctl_mRead~9_combout ) # ((\z80_|execute_|ctl_mRead~15_combout ) # ((\z80_|execute_|ctl_mRead~10_combout ) # (\z80_|execute_|ctl_mRead~8_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~9_combout ), - .datab(\z80_|execute_|ctl_mRead~15_combout ), - .datac(\z80_|execute_|ctl_mRead~10_combout ), - .datad(\z80_|execute_|ctl_mRead~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~20 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_mRead~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal12~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal12~1_combout = (\z80_|pla_decode_|Equal55~0_combout & (!\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal6~0_combout )) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal12~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal12~1 .lut_mask = 16'h2200; -defparam \z80_|pla_decode_|Equal12~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N10 -cycloneive_lcell_comb \z80_|pla_decode_|Equal9~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal9~1_combout = (\z80_|pla_decode_|Equal9~0_combout & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal1~7_combout ))) - - .dataa(\z80_|pla_decode_|Equal9~0_combout ), - .datab(\z80_|pla_decode_|Equal2~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal1~7_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal9~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal9~1 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal9~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal25~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal25~0_combout = (\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal55~0_combout & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal25~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal25~0 .lut_mask = 16'h2000; -defparam \z80_|pla_decode_|Equal25~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~21 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~21_combout = (\z80_|pla_decode_|Equal9~1_combout ) # ((\z80_|execute_|ctl_mRead~17_combout ) # ((!\z80_|pla_decode_|Equal12~1_combout & \z80_|pla_decode_|Equal25~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal12~1_combout ), - .datab(\z80_|pla_decode_|Equal9~1_combout ), - .datac(\z80_|execute_|ctl_mRead~17_combout ), - .datad(\z80_|pla_decode_|Equal25~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~21 .lut_mask = 16'hFDFC; -defparam \z80_|execute_|ctl_mRead~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~6 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~6_combout = (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_M4_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~6 .lut_mask = 16'hA0A0; -defparam \z80_|execute_|ctl_state_alu~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal19~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal19~0_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal32~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal1~7_combout ))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|pla_decode_|Equal32~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal1~7_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal19~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal19~0 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal19~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N30 -cycloneive_lcell_comb \z80_|pla_decode_|Equal1~4 ( -// Equation(s): -// \z80_|pla_decode_|Equal1~4_combout = (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [1]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal1~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal1~4 .lut_mask = 16'h000F; -defparam \z80_|pla_decode_|Equal1~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N2 -cycloneive_lcell_comb \z80_|pla_decode_|Equal29~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal29~0_combout = (\z80_|pla_decode_|Equal1~7_combout & (\z80_|pla_decode_|Equal1~4_combout & (\z80_|pla_decode_|Equal32~0_combout & !\z80_|ir_|opcode [5]))) - - .dataa(\z80_|pla_decode_|Equal1~7_combout ), - .datab(\z80_|pla_decode_|Equal1~4_combout ), - .datac(\z80_|pla_decode_|Equal32~0_combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal29~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal29~0 .lut_mask = 16'h0080; -defparam \z80_|pla_decode_|Equal29~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N20 -cycloneive_lcell_comb \z80_|pla_decode_|Equal24~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal24~1_combout = (\z80_|pla_decode_|Equal9~0_combout & (\z80_|pla_decode_|Equal2~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal1~7_combout ))) - - .dataa(\z80_|pla_decode_|Equal9~0_combout ), - .datab(\z80_|pla_decode_|Equal2~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal1~7_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal24~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal24~1 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal24~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N18 -cycloneive_lcell_comb \z80_|pla_decode_|Equal34~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal34~0_combout = (!\z80_|ir_|opcode [0] & (!\z80_|decode_state_|table_xx~0_combout & (\z80_|pla_decode_|Equal3~1_combout & \z80_|pla_decode_|Equal41~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|decode_state_|table_xx~0_combout ), - .datac(\z80_|pla_decode_|Equal3~1_combout ), - .datad(\z80_|pla_decode_|Equal41~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal34~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal34~0 .lut_mask = 16'h1000; -defparam \z80_|pla_decode_|Equal34~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal37~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal37~0_combout = (\z80_|pla_decode_|Equal41~0_combout & (!\z80_|decode_state_|table_xx~0_combout & (!\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal1~4_combout ))) - - .dataa(\z80_|pla_decode_|Equal41~0_combout ), - .datab(\z80_|decode_state_|table_xx~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal1~4_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal37~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal37~0 .lut_mask = 16'h0200; -defparam \z80_|pla_decode_|Equal37~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N12 -cycloneive_lcell_comb \z80_|pla_decode_|Equal35~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal35~0_combout = (\z80_|pla_decode_|Equal41~0_combout & (!\z80_|decode_state_|table_xx~0_combout & (!\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal41~0_combout ), - .datab(\z80_|decode_state_|table_xx~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal35~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal35~0 .lut_mask = 16'h0200; -defparam \z80_|pla_decode_|Equal35~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N14 -cycloneive_lcell_comb \z80_|pla_decode_|Equal38~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal38~2_combout = (!\z80_|ir_|opcode [1] & (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [2] & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal38~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal38~2 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal38~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N14 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~2 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~2_combout = (\z80_|pla_decode_|Equal34~0_combout ) # ((\z80_|pla_decode_|Equal37~0_combout ) # ((\z80_|pla_decode_|Equal35~0_combout ) # (\z80_|pla_decode_|Equal38~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal34~0_combout ), - .datab(\z80_|pla_decode_|Equal37~0_combout ), - .datac(\z80_|pla_decode_|Equal35~0_combout ), - .datad(\z80_|pla_decode_|Equal38~2_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~2 .lut_mask = 16'hFFFE; -defparam \z80_|reg_control_|reg_sys_we_lo~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N22 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~3 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~3_combout = (\z80_|pla_decode_|Equal19~0_combout ) # ((\z80_|pla_decode_|Equal29~0_combout ) # ((\z80_|pla_decode_|Equal24~1_combout ) # (\z80_|reg_control_|reg_sys_we_lo~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal19~0_combout ), - .datab(\z80_|pla_decode_|Equal29~0_combout ), - .datac(\z80_|pla_decode_|Equal24~1_combout ), - .datad(\z80_|reg_control_|reg_sys_we_lo~2_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~3 .lut_mask = 16'hFFFE; -defparam \z80_|reg_control_|reg_sys_we_lo~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N4 -cycloneive_lcell_comb \z80_|execute_|comb~0 ( -// Equation(s): -// \z80_|execute_|comb~0_combout = (\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1]) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [2]), - .datac(\z80_|ir_|opcode [1]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|comb~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|comb~0 .lut_mask = 16'hC0C0; -defparam \z80_|execute_|comb~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N30 -cycloneive_lcell_comb \z80_|pla_decode_|Equal47~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal47~0_combout = (\z80_|pla_decode_|Equal41~0_combout & (!\z80_|decode_state_|table_xx~0_combout & (\z80_|ir_|opcode [0] & \z80_|execute_|comb~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal41~0_combout ), - .datab(\z80_|decode_state_|table_xx~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|execute_|comb~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal47~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal47~0 .lut_mask = 16'h2000; -defparam \z80_|pla_decode_|Equal47~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N8 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~4 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~4_combout = (\z80_|execute_|ctl_state_alu~6_combout & (!\z80_|pla_decode_|Equal47~0_combout & ((!\z80_|reg_control_|reg_sys_we_lo~3_combout ) # (!\z80_|execute_|ctl_state_alu~4_combout )))) # -// (!\z80_|execute_|ctl_state_alu~6_combout & (((!\z80_|reg_control_|reg_sys_we_lo~3_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~6_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|reg_control_|reg_sys_we_lo~3_combout ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~4 .lut_mask = 16'h153F; -defparam \z80_|reg_control_|reg_sys_we_lo~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~22 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~22_combout = (\z80_|reg_control_|reg_sys_we_lo~4_combout & (((!\z80_|execute_|ctl_mRead~20_combout & !\z80_|execute_|ctl_mRead~21_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~20_combout ), - .datab(\z80_|execute_|ctl_mRead~21_combout ), - .datac(\z80_|reg_control_|reg_sys_we_lo~4_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~22 .lut_mask = 16'h10F0; -defparam \z80_|execute_|ctl_mRead~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~24 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~24_combout = (\z80_|execute_|ctl_reg_in_hi~5_combout & (\z80_|execute_|ctl_mRead~22_combout & ((!\z80_|execute_|ctl_state_alu~6_combout ) # (!\z80_|execute_|ctl_mRead~18_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~18_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~5_combout ), - .datac(\z80_|execute_|ctl_mRead~22_combout ), - .datad(\z80_|execute_|ctl_state_alu~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~24 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_mRead~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout = (\z80_|pla_decode_|Equal52~0_combout & (!\z80_|ir_|opcode [0] & (\z80_|execute_|ixy_d~6_combout & \z80_|pla_decode_|Equal3~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal52~0_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|pla_decode_|Equal3~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~6_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & (((!\z80_|pla_decode_|Equal19~0_combout & !\z80_|pla_decode_|Equal35~0_combout )) # (!\z80_|execute_|ixy_d~6_combout ))) - - .dataa(\z80_|pla_decode_|Equal19~0_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|pla_decode_|Equal35~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~6 .lut_mask = 16'h0313; -defparam \z80_|execute_|ctl_reg_in_hi~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N20 -cycloneive_lcell_comb \z80_|pla_decode_|Equal6~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal6~1_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal1~4_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal1~4_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal6~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal6~1 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal6~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~16 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~16_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal1~4_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal52~0_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal1~4_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal52~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~16 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_mRead~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N16 +// Location: LCCOMB_X26_Y13_N0 cycloneive_lcell_comb \z80_|sequencer_|M5~0 ( // Equation(s): -// \z80_|sequencer_|M5~0_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|M5~q ))))) +// \z80_|sequencer_|M5~0_combout = (\z80_|execute_|setM1~54_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|M5~q ))))) - .dataa(\z80_|execute_|setM1~52_combout ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|execute_|setM1~54_combout ), .datac(\z80_|sequencer_|M5~q ), .datad(\z80_|execute_|nextM~14_combout ), .cin(gnd), .combout(\z80_|sequencer_|M5~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|sequencer_|M5~0 .lut_mask = 16'h88A0; +defparam \z80_|sequencer_|M5~0 .lut_mask = 16'h88C0; defparam \z80_|sequencer_|M5~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y17_N17 +// Location: FF_X26_Y13_N1 dffeas \z80_|sequencer_|M5 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|sequencer_|M5~0_combout ), @@ -6053,12847 +4360,427 @@ defparam \z80_|sequencer_|M5 .is_wysiwyg = "true"; defparam \z80_|sequencer_|M5 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X38_Y17_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~2 ( +// Location: LCCOMB_X24_Y11_N10 +cycloneive_lcell_comb \z80_|execute_|ixy_d~5 ( // Equation(s): -// \z80_|execute_|ctl_reg_in_hi~2_combout = (\z80_|sequencer_|M5~q & \z80_|sequencer_|DFFE_T3_ff~q ) +// \z80_|execute_|ixy_d~5_combout = (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ) .dataa(gnd), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), .datad(gnd), .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .combout(\z80_|execute_|ixy_d~5_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~2 .lut_mask = 16'hC0C0; -defparam \z80_|execute_|ctl_reg_in_hi~2 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ixy_d~5 .lut_mask = 16'hC0C0; +defparam \z80_|execute_|ixy_d~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|setM1~29 ( -// Equation(s): -// \z80_|execute_|setM1~29_combout = (\z80_|execute_|ctl_mRead~16_combout & (!\z80_|execute_|ixy_d~6_combout & ((!\z80_|execute_|ctl_mRead~17_combout ) # (!\z80_|execute_|ctl_reg_in_hi~2_combout )))) # (!\z80_|execute_|ctl_mRead~16_combout & -// (((!\z80_|execute_|ctl_mRead~17_combout ) # (!\z80_|execute_|ctl_reg_in_hi~2_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~16_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datad(\z80_|execute_|ctl_mRead~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~29 .lut_mask = 16'h0777; -defparam \z80_|execute_|setM1~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~25 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~25_combout = (\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|execute_|ctl_mRead~16_combout & ((!\z80_|execute_|ctl_state_alu~6_combout ) # (!\z80_|execute_|ctl_mRead~17_combout )))) # (!\z80_|execute_|ctl_state_alu~4_combout -// & (((!\z80_|execute_|ctl_state_alu~6_combout )) # (!\z80_|execute_|ctl_mRead~17_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_mRead~17_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_mRead~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~25 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_mRead~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~6_combout = (\z80_|execute_|setM1~29_combout & (\z80_|execute_|ctl_mRead~25_combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|pla_decode_|Equal6~1_combout )))) - - .dataa(\z80_|pla_decode_|Equal6~1_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|execute_|setM1~29_combout ), - .datad(\z80_|execute_|ctl_mRead~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~6 .lut_mask = 16'h7000; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~7_combout = (!\z80_|ir_|opcode [6] & (\z80_|pla_decode_|Equal33~0_combout & (\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) - - .dataa(\z80_|ir_|opcode [6]), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|execute_|ctl_ir_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~7 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_ir_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N2 -cycloneive_lcell_comb \z80_|pla_decode_|Equal52~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal52~1_combout = (!\z80_|decode_state_|DFFE_instED~q & (\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal41~0_combout & !\z80_|decode_state_|DFFE_instCB~q ))) - - .dataa(\z80_|decode_state_|DFFE_instED~q ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|pla_decode_|Equal41~0_combout ), - .datad(\z80_|decode_state_|DFFE_instCB~q ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal52~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal52~1 .lut_mask = 16'h0040; -defparam \z80_|pla_decode_|Equal52~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~14 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~14_combout = (!\z80_|decode_state_|DFFE_inst4~q & (\z80_|pla_decode_|Equal44~0_combout & (!\z80_|decode_state_|DFFE_instIY1~q & \z80_|pla_decode_|Equal33~0_combout ))) - - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(\z80_|pla_decode_|Equal44~0_combout ), - .datac(\z80_|decode_state_|DFFE_instIY1~q ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~14 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_state_alu~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~8 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~8_combout = (\z80_|execute_|ctl_state_alu~4_combout & (((!\z80_|pla_decode_|Equal52~1_combout & !\z80_|execute_|ctl_state_alu~14_combout )))) # (!\z80_|execute_|ctl_state_alu~4_combout & -// (((!\z80_|execute_|ctl_state_alu~14_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_state_alu~6_combout ), - .datac(\z80_|pla_decode_|Equal52~1_combout ), - .datad(\z80_|execute_|ctl_state_alu~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~8 .lut_mask = 16'h115F; -defparam \z80_|execute_|ctl_state_alu~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N20 -cycloneive_lcell_comb \z80_|pla_decode_|Equal24~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal24~0_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|pla_decode_|Equal52~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal24~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal24~0 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal24~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N0 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_pc~0_combout = ((!\z80_|pla_decode_|Equal37~0_combout & ((!\z80_|pla_decode_|Equal9~0_combout ) # (!\z80_|pla_decode_|Equal24~0_combout )))) # (!\z80_|execute_|ixy_d~6_combout ) - - .dataa(\z80_|pla_decode_|Equal24~0_combout ), - .datab(\z80_|pla_decode_|Equal37~0_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|pla_decode_|Equal9~0_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_pc~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_pc~0 .lut_mask = 16'h1F3F; -defparam \z80_|reg_control_|reg_sel_pc~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N26 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~1 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_pc~1_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ctl_reg_in_hi~2_combout & ((!\z80_|pla_decode_|Equal29~0_combout ) # (!\z80_|execute_|ixy_d~6_combout )))) # (!\z80_|pla_decode_|Equal47~0_combout & -// (((!\z80_|pla_decode_|Equal29~0_combout )) # (!\z80_|execute_|ixy_d~6_combout ))) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datad(\z80_|pla_decode_|Equal29~0_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_pc~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_pc~1 .lut_mask = 16'h135F; -defparam \z80_|reg_control_|reg_sel_pc~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N12 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~2 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_pc~2_combout = (\z80_|reg_control_|reg_sel_pc~0_combout & (\z80_|reg_control_|reg_sel_pc~1_combout & ((!\z80_|pla_decode_|Equal38~2_combout ) # (!\z80_|execute_|ixy_d~6_combout )))) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|reg_control_|reg_sel_pc~0_combout ), - .datac(\z80_|reg_control_|reg_sel_pc~1_combout ), - .datad(\z80_|pla_decode_|Equal38~2_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_pc~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_pc~2 .lut_mask = 16'h40C0; -defparam \z80_|reg_control_|reg_sel_pc~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|fMRead~17 ( -// Equation(s): -// \z80_|execute_|fMRead~17_combout = (\z80_|execute_|ctl_state_alu~8_combout & (\z80_|reg_control_|reg_sel_pc~2_combout & ((!\z80_|execute_|ctl_ir_we~7_combout ) # (!\z80_|execute_|ctl_state_alu~4_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_ir_we~7_combout ), - .datac(\z80_|execute_|ctl_state_alu~8_combout ), - .datad(\z80_|reg_control_|reg_sel_pc~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~17 .lut_mask = 16'h7000; -defparam \z80_|execute_|fMRead~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~6 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~6_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal3~1_combout & (!\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|pla_decode_|Equal3~1_combout ), - .datac(\z80_|decode_state_|use_ixiy~combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~6 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_mRead~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal11~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal11~0_combout = (!\z80_|ir_|opcode [1] & (\z80_|execute_|ctl_mWrite~2_combout & (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [0]))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal11~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal11~0 .lut_mask = 16'h0004; -defparam \z80_|pla_decode_|Equal11~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal10~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal10~0_combout = (!\z80_|ir_|opcode [1] & (\z80_|execute_|ctl_mWrite~2_combout & (!\z80_|ir_|opcode [2] & \z80_|ir_|opcode [0]))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal10~0 .lut_mask = 16'h0400; -defparam \z80_|pla_decode_|Equal10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~9_combout = (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|pla_decode_|Equal10~0_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(\z80_|pla_decode_|Equal11~0_combout ), - .datab(\z80_|pla_decode_|Equal10~0_combout ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~9 .lut_mask = 16'h1FFF; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~4 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~4_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & (((!\z80_|execute_|ctl_state_alu~4_combout & !\z80_|execute_|ctl_state_alu~6_combout )) # (!\z80_|execute_|ctl_mRead~6_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_state_alu~6_combout ), - .datac(\z80_|execute_|ctl_mRead~6_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~4 .lut_mask = 16'h1F00; -defparam \z80_|execute_|ctl_sw_2d~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~15 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~15_combout = (\z80_|ir_|opcode [6] & (\z80_|pla_decode_|Equal33~0_combout & (\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) - - .dataa(\z80_|ir_|opcode [6]), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|execute_|ctl_ir_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~15 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_ir_we~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|fMRead~16 ( -// Equation(s): -// \z80_|execute_|fMRead~16_combout = (\z80_|execute_|ctl_reg_in_hi~2_combout & (!\z80_|execute_|ctl_mRead~18_combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_ir_we~15_combout )))) # (!\z80_|execute_|ctl_reg_in_hi~2_combout & -// (((!\z80_|execute_|ctl_state_alu~4_combout )) # (!\z80_|execute_|ctl_ir_we~15_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_mRead~18_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~16 .lut_mask = 16'h135F; -defparam \z80_|execute_|fMRead~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~9 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~9_combout = (\z80_|execute_|ctl_ir_we~5_combout & (\z80_|pla_decode_|Equal41~0_combout & ((!\z80_|decode_state_|DFFE_instCB~q ) # (!\z80_|pla_decode_|Equal33~0_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~5_combout ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|pla_decode_|Equal41~0_combout ), - .datad(\z80_|decode_state_|DFFE_instCB~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~9 .lut_mask = 16'h20A0; -defparam \z80_|execute_|ctl_ir_we~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N22 -cycloneive_lcell_comb \z80_|pla_decode_|Equal46~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal46~0_combout = (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [1] & (\z80_|ir_|opcode [2] & \z80_|decode_state_|DFFE_instCB~q ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [1]), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|decode_state_|DFFE_instCB~q ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal46~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal46~0 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal46~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~10 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~10_combout = (!\z80_|ir_|opcode [6] & (!\z80_|pla_decode_|Equal46~0_combout & (\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) - - .dataa(\z80_|ir_|opcode [6]), - .datab(\z80_|pla_decode_|Equal46~0_combout ), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|execute_|ctl_ir_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~10 .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_ir_we~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~17 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~17_combout = (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|execute_|ctl_ir_we~7_combout ), - .datad(\z80_|execute_|ctl_ir_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~17 .lut_mask = 16'h777F; -defparam \z80_|execute_|ctl_flags_alu~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~6_combout = (\z80_|execute_|ctl_flags_alu~17_combout & (((!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~9_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~15_combout ), - .datab(\z80_|execute_|ctl_ir_we~9_combout ), - .datac(\z80_|execute_|ctl_flags_alu~17_combout ), - .datad(\z80_|execute_|ctl_state_alu~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~6 .lut_mask = 16'h10F0; -defparam \z80_|execute_|ctl_flags_alu~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~6_combout = (!\z80_|ir_|opcode [6] & !\z80_|ir_|opcode [7]) - - .dataa(\z80_|ir_|opcode [6]), - .datab(gnd), - .datac(\z80_|ir_|opcode [7]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~6 .lut_mask = 16'h0505; -defparam \z80_|execute_|ctl_ir_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~8_combout = (\z80_|execute_|ctl_ir_we~5_combout & (\z80_|execute_|ctl_ir_we~6_combout & ((!\z80_|decode_state_|DFFE_instCB~q ) # (!\z80_|pla_decode_|Equal33~0_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~5_combout ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|execute_|ctl_ir_we~6_combout ), - .datad(\z80_|decode_state_|DFFE_instCB~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~8 .lut_mask = 16'h20A0; -defparam \z80_|execute_|ctl_ir_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~16 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~16_combout = (((!\z80_|execute_|ctl_ir_we~8_combout & !\z80_|execute_|ctl_ir_we~14_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M4_ff~q ) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|execute_|ctl_ir_we~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~16 .lut_mask = 16'h3F7F; -defparam \z80_|execute_|ctl_flags_alu~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~3_combout = ((!\z80_|execute_|ctl_mRead~8_combout & (!\z80_|execute_|ctl_mRead~10_combout & !\z80_|execute_|ctl_mRead~9_combout ))) # (!\z80_|execute_|ixy_d~6_combout ) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|execute_|ctl_mRead~8_combout ), - .datac(\z80_|execute_|ctl_mRead~10_combout ), - .datad(\z80_|execute_|ctl_mRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~3 .lut_mask = 16'h5557; -defparam \z80_|execute_|ctl_reg_in_hi~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~8 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~8_combout = (\z80_|execute_|ctl_flags_alu~6_combout & (\z80_|execute_|ctl_flags_alu~16_combout & \z80_|execute_|ctl_reg_in_hi~3_combout )) - - .dataa(\z80_|execute_|ctl_flags_alu~6_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_flags_alu~16_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~8 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_mWrite~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|fMRead~18 ( -// Equation(s): -// \z80_|execute_|fMRead~18_combout = (\z80_|execute_|fMRead~17_combout & (\z80_|execute_|ctl_sw_2d~4_combout & (\z80_|execute_|fMRead~16_combout & \z80_|execute_|ctl_mWrite~8_combout ))) - - .dataa(\z80_|execute_|fMRead~17_combout ), - .datab(\z80_|execute_|ctl_sw_2d~4_combout ), - .datac(\z80_|execute_|fMRead~16_combout ), - .datad(\z80_|execute_|ctl_mWrite~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~18 .lut_mask = 16'h8000; -defparam \z80_|execute_|fMRead~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N26 -cycloneive_lcell_comb \z80_|execute_|fMRead~19 ( -// Equation(s): -// \z80_|execute_|fMRead~19_combout = (\z80_|execute_|ctl_mRead~24_combout & (\z80_|execute_|ctl_reg_in_hi~6_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~6_combout & \z80_|execute_|fMRead~18_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~24_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~6_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), - .datad(\z80_|execute_|fMRead~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~19 .lut_mask = 16'h8000; -defparam \z80_|execute_|fMRead~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~16 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~16_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|execute_|ixy_d~15_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~16 .lut_mask = 16'h0F00; -defparam \z80_|execute_|ctl_alu_shift_oe~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~36 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~36_combout = (\z80_|ir_|opcode [1] & (\z80_|execute_|ctl_mWrite~2_combout & (!\z80_|ir_|opcode [2] & \z80_|ir_|opcode [0]))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~36 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_mRead~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~9_combout = (\z80_|pla_decode_|Equal1~4_combout & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [0] & \z80_|execute_|ctl_mWrite~3_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~4_combout ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|execute_|ctl_mWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~9 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_alu_op_low~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~44 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~44_combout = (!\z80_|execute_|ctl_alu_op_low~9_combout & (((!\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|execute_|ctl_mRead~36_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|execute_|ctl_mRead~36_combout ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|execute_|ctl_alu_op_low~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~44 .lut_mask = 16'h007F; -defparam \z80_|execute_|ctl_alu_shift_oe~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~11 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~11_combout = (\z80_|sequencer_|DFFE_T5_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~11 .lut_mask = 16'h00AA; -defparam \z80_|execute_|ctl_mRead~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~6 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~6_combout = (\z80_|execute_|ixy_d~6_combout & (!\z80_|pla_decode_|Equal9~1_combout & ((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_mRead~11_combout )))) # (!\z80_|execute_|ixy_d~6_combout & -// (((!\z80_|pla_decode_|Equal47~0_combout )) # (!\z80_|execute_|ctl_mRead~11_combout ))) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|execute_|ctl_mRead~11_combout ), - .datac(\z80_|pla_decode_|Equal47~0_combout ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~6 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_sw_2d~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~7 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~7_combout = (\z80_|execute_|ctl_sw_2d~6_combout & (((!\z80_|execute_|ctl_mRead~4_combout & !\z80_|pla_decode_|Equal6~1_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_sw_2d~6_combout ), - .datab(\z80_|execute_|ctl_mRead~4_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal6~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~7 .lut_mask = 16'h0A2A; -defparam \z80_|execute_|ctl_sw_2d~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~7 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~7_combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_M4_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|sequencer_|DFFE_M4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~7 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_mWrite~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~11 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~11_combout = (\z80_|ir_|opcode [6] & (!\z80_|pla_decode_|Equal46~0_combout & (!\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) - - .dataa(\z80_|ir_|opcode [6]), - .datab(\z80_|pla_decode_|Equal46~0_combout ), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|execute_|ctl_ir_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~11 .lut_mask = 16'h0200; -defparam \z80_|execute_|ctl_ir_we~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~12 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~12_combout = (\z80_|ir_|opcode [6] & (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|ir_|opcode [7] & \z80_|execute_|ctl_ir_we~5_combout ))) - - .dataa(\z80_|ir_|opcode [6]), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|execute_|ctl_ir_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~12 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_ir_we~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~0 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~0_combout = (\z80_|execute_|ctl_mWrite~7_combout & (!\z80_|execute_|ctl_ir_we~11_combout & ((!\z80_|execute_|ctl_ir_we~12_combout )))) # (!\z80_|execute_|ctl_mWrite~7_combout & (((!\z80_|execute_|ctl_ir_we~12_combout ) # -// (!\z80_|execute_|ctl_mWrite~3_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~7_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_mWrite~3_combout ), - .datad(\z80_|execute_|ctl_ir_we~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~0 .lut_mask = 16'h0577; -defparam \z80_|execute_|ctl_flags_sz_we~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout = (\z80_|pla_decode_|Equal1~4_combout & (!\z80_|ir_|opcode [0] & (\z80_|nM1_int~2_combout & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~4_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~8 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~8_combout = (\z80_|execute_|ctl_alu_shift_oe~44_combout & (\z80_|execute_|ctl_sw_2d~7_combout & (\z80_|execute_|ctl_flags_sz_we~0_combout & !\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~44_combout ), - .datab(\z80_|execute_|ctl_sw_2d~7_combout ), - .datac(\z80_|execute_|ctl_flags_sz_we~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~8 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_sw_2d~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~9 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~9_combout = (\z80_|execute_|ctl_sw_2d~5_combout & (\z80_|execute_|fMRead~19_combout & (!\z80_|execute_|ctl_alu_shift_oe~16_combout & \z80_|execute_|ctl_sw_2d~8_combout ))) - - .dataa(\z80_|execute_|ctl_sw_2d~5_combout ), - .datab(\z80_|execute_|fMRead~19_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~16_combout ), - .datad(\z80_|execute_|ctl_sw_2d~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~9 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_sw_2d~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~6 ( -// Equation(s): -// \z80_|execute_|ctl_sw_1d~6_combout = (!\z80_|execute_|ctl_im_we~combout & (!\z80_|execute_|ctl_sw_1d~5_combout & (\z80_|execute_|ctl_sw_1d~4_combout & \z80_|execute_|ctl_sw_2d~9_combout ))) - - .dataa(\z80_|execute_|ctl_im_we~combout ), - .datab(\z80_|execute_|ctl_sw_1d~5_combout ), - .datac(\z80_|execute_|ctl_sw_1d~4_combout ), - .datad(\z80_|execute_|ctl_sw_2d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~6 .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_sw_1d~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~7 ( -// Equation(s): -// \z80_|execute_|ctl_sw_1d~7_combout = ((!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & \z80_|pla_decode_|Equal47~0_combout ))) # (!\z80_|execute_|ctl_sw_1d~6_combout ) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|execute_|ctl_sw_1d~6_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~7 .lut_mask = 16'h7333; -defparam \z80_|execute_|ctl_sw_1d~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y18_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~8_combout = (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~8 .lut_mask = 16'hC0C0; -defparam \z80_|execute_|ctl_alu_op_low~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y18_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout = (\z80_|execute_|ctl_mWrite~2_combout & (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal2~0_combout & \z80_|execute_|ctl_alu_op_low~8_combout ))) - - .dataa(\z80_|execute_|ctl_mWrite~2_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|pla_decode_|Equal2~0_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|execute_|ixy_d~15_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~39 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~39_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout & (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & ((!\z80_|execute_|ctl_mRead~36_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_mRead~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~39 .lut_mask = 16'h0111; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|pla_decode_|Equal21~1_combout & !\z80_|sequencer_|DFFE_M1_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|pla_decode_|Equal21~1_combout ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 .lut_mask = 16'h0088; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_hi~4_combout = ((!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal40~1_combout & !\z80_|pla_decode_|Equal39~0_combout ))) # (!\z80_|execute_|ixy_d~9_combout ) - - .dataa(\z80_|execute_|ixy_d~9_combout ), - .datab(\z80_|pla_decode_|Equal21~1_combout ), - .datac(\z80_|pla_decode_|Equal40~1_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_hi~4 .lut_mask = 16'h5557; -defparam \z80_|execute_|ctl_reg_out_hi~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~15 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~15_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal6~0_combout & (!\z80_|pla_decode_|Equal33~1_combout & \z80_|pla_decode_|Equal3~1_combout ))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|pla_decode_|Equal33~1_combout ), - .datad(\z80_|pla_decode_|Equal3~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~15 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_alu_shift_oe~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~38 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~38_combout = (!\z80_|execute_|ctl_alu_shift_oe~15_combout & (((!\z80_|execute_|ctl_state_alu~4_combout & !\z80_|execute_|ctl_state_alu~6_combout )) # (!\z80_|execute_|ctl_mRead~6_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~38 .lut_mask = 16'h0037; -defparam \z80_|execute_|ctl_alu_shift_oe~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_zero ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_zero~combout = ((\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~38_combout ) # (!\z80_|execute_|ctl_reg_out_hi~4_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), - .datac(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_zero .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_alu_op2_sel_zero .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N14 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~4 ( -// Equation(s): -// \z80_|alu_|db_low[2]~4_combout = ((\z80_|bus_control_|db[4]~19_combout & (!\z80_|bus_control_|db[5]~15_combout & !\z80_|bus_control_|db[3]~21_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datab(\z80_|bus_control_|db[4]~19_combout ), - .datac(\z80_|bus_control_|db[5]~15_combout ), - .datad(\z80_|bus_control_|db[3]~21_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~4 .lut_mask = 16'h555D; -defparam \z80_|alu_|db_low[2]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~14_combout = (\z80_|sequencer_|DFFE_M4_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~14 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_alu_shift_oe~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~11 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[0]~11_combout = ((!\z80_|pla_decode_|Equal40~1_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal39~0_combout ))) # (!\z80_|execute_|ixy_d~5_combout ) - - .dataa(\z80_|pla_decode_|Equal40~1_combout ), - .datab(\z80_|pla_decode_|Equal21~1_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~11 .lut_mask = 16'h0F1F; -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~1 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~1_combout = (\z80_|execute_|ctl_reg_out_hi~4_combout & \z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~1 .lut_mask = 16'hCC00; -defparam \z80_|execute_|ctl_sw_4u~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~5_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout & (((!\z80_|pla_decode_|Equal21~1_combout & !\z80_|execute_|ctl_mRead~36_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), - .datab(\z80_|pla_decode_|Equal21~1_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_mRead~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~5 .lut_mask = 16'h0515; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~30 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~30_combout = (\z80_|execute_|ctl_sw_4u~1_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~5_combout & ((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|execute_|ctl_sw_4u~1_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~30 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_alu_shift_oe~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~29 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~29_combout = (\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|execute_|ctl_mRead~36_combout & ((!\z80_|execute_|ctl_mWrite~3_combout ) # (!\z80_|execute_|ctl_mWrite~16_combout )))) # -// (!\z80_|execute_|ctl_state_alu~4_combout & (((!\z80_|execute_|ctl_mWrite~3_combout )) # (!\z80_|execute_|ctl_mWrite~16_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_mWrite~16_combout ), - .datac(\z80_|execute_|ctl_mRead~36_combout ), - .datad(\z80_|execute_|ctl_mWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~29 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_alu_shift_oe~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~31 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~31_combout = (\z80_|execute_|ctl_alu_shift_oe~30_combout & (\z80_|execute_|ctl_alu_shift_oe~29_combout & ((!\z80_|execute_|ctl_mRead~11_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~30_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~29_combout ), - .datad(\z80_|execute_|ctl_mRead~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~31 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_alu_shift_oe~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal69~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal69~0_combout = (!\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|pla_decode_|Equal13~1_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal69~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal69~0 .lut_mask = 16'h4000; -defparam \z80_|pla_decode_|Equal69~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N24 -cycloneive_lcell_comb \z80_|pla_decode_|Equal1~5 ( -// Equation(s): -// \z80_|pla_decode_|Equal1~5_combout = (\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [5]) - - .dataa(\z80_|ir_|opcode [4]), - .datab(gnd), - .datac(gnd), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal1~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal1~5 .lut_mask = 16'h00AA; -defparam \z80_|pla_decode_|Equal1~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~14_combout = (\z80_|pla_decode_|Equal1~5_combout & (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~5_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|pla_decode_|Equal13~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~14 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_op_low~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~12 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~12_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal2~0_combout & (!\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal2~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~12 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_alu_op_low~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal56~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal56~0_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal1~4_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal1~4_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal56~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal56~0 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal56~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~11_combout = (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~11 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_alu_op_low~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|nextM~2 ( -// Equation(s): -// \z80_|execute_|nextM~2_combout = (!\z80_|execute_|ctl_alu_op_low~12_combout & (!\z80_|pla_decode_|Equal56~0_combout & !\z80_|execute_|ctl_alu_op_low~11_combout )) - - .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_alu_op_low~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~2 .lut_mask = 16'h0011; -defparam \z80_|execute_|nextM~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~16 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~16_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # ((\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T3_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|execute_|nextM~2_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~16 .lut_mask = 16'h0F08; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~4_combout = (!\z80_|execute_|ctl_alu_op_low~14_combout & (!\z80_|execute_|ctl_alu_op1_sel_bus~16_combout & ((!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # (!\z80_|pla_decode_|Equal69~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal69~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~4 .lut_mask = 16'h0103; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~5_combout = (\z80_|execute_|ctl_alu_shift_oe~38_combout & \z80_|execute_|ctl_alu_op1_sel_bus~4_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~5 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~3 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~3_combout = (\z80_|pla_decode_|Equal77~0_combout & ((\z80_|decode_state_|in_halt~q ) # ((!\z80_|pla_decode_|Equal33~1_combout & !\z80_|pla_decode_|Equal33~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|decode_state_|in_halt~q ), - .datac(\z80_|pla_decode_|Equal77~0_combout ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~3 .lut_mask = 16'hC0D0; -defparam \z80_|execute_|ctl_alu_oe~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~15 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~15_combout = ((!\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|execute_|ixy_d~15_combout ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|execute_|ixy_d~15_combout ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~15 .lut_mask = 16'h0F3F; -defparam \z80_|execute_|ctl_alu_op_low~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~8_combout = (\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|execute_|ctl_ir_we~7_combout & ((!\z80_|execute_|ctl_ir_we~10_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) # -// (!\z80_|execute_|ctl_state_alu~4_combout & (((!\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_ir_we~7_combout ), - .datad(\z80_|execute_|ctl_ir_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~8 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~9_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~8_combout & (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_ir_we~10_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~9 .lut_mask = 16'h1F00; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~3 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~3_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|execute_|ctl_ir_we~9_combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_ir_we~15_combout )))) # -// (!\z80_|execute_|ctl_eval_cond~0_combout & (((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_ir_we~15_combout )))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|ctl_ir_we~9_combout ), - .datac(\z80_|execute_|ctl_ir_we~15_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~3 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_alu_core_R~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~4_combout = (\z80_|execute_|ctl_alu_core_R~3_combout & (((!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~9_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~15_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~3_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_ir_we~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~4 .lut_mask = 16'h0C4C; -defparam \z80_|execute_|ctl_alu_core_R~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|execute_|ctl_ir_we~11_combout )) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|execute_|ctl_ir_we~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 .lut_mask = 16'h3000; -defparam \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~10_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~9_combout & (\z80_|execute_|ctl_flags_sz_we~0_combout & (\z80_|execute_|ctl_alu_core_R~4_combout & !\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout -// ))) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~0_combout ), - .datac(\z80_|execute_|ctl_alu_core_R~4_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~10 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~11_combout = (((\z80_|execute_|ctl_alu_oe~3_combout & \z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~10_combout )) # (!\z80_|execute_|ctl_alu_op_low~15_combout ) - - .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~15_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~11 .lut_mask = 16'h8FFF; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal48~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal48~0_combout = (!\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|pla_decode_|Equal13~1_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal48~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal48~0 .lut_mask = 16'h1000; -defparam \z80_|pla_decode_|Equal48~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf2_we ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf2_we~combout = (\z80_|pla_decode_|Equal63~0_combout & (!\z80_|ir_|opcode [4] & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & !\z80_|ir_|opcode [3]))) - - .dataa(\z80_|pla_decode_|Equal63~0_combout ), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf2_we~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf2_we .lut_mask = 16'h0020; -defparam \z80_|execute_|ctl_flags_hf2_we .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~41 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~41_combout = (!\z80_|execute_|ctl_flags_hf2_we~combout & (((!\z80_|pla_decode_|Equal10~0_combout & !\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|execute_|ctl_flags_hf2_we~combout ), - .datad(\z80_|pla_decode_|Equal11~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~41 .lut_mask = 16'h0307; -defparam \z80_|execute_|ctl_alu_shift_oe~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~18 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~18_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|pla_decode_|Equal44~0_combout & !\z80_|pla_decode_|Equal52~1_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|pla_decode_|Equal44~0_combout ), - .datad(\z80_|pla_decode_|Equal52~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~18 .lut_mask = 16'hBBBF; -defparam \z80_|execute_|ctl_flags_xy_we~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~17 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~17_combout = ((!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal35~0_combout & !\z80_|pla_decode_|Equal39~0_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|pla_decode_|Equal21~1_combout ), - .datac(\z80_|pla_decode_|Equal35~0_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~17 .lut_mask = 16'h5557; -defparam \z80_|execute_|ctl_alu_shift_oe~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~19 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~19_combout = (\z80_|pla_decode_|Equal40~1_combout ) # ((\z80_|pla_decode_|Equal37~0_combout ) # ((\z80_|pla_decode_|Equal41~2_combout ) # (\z80_|pla_decode_|Equal34~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal40~1_combout ), - .datab(\z80_|pla_decode_|Equal37~0_combout ), - .datac(\z80_|pla_decode_|Equal41~2_combout ), - .datad(\z80_|pla_decode_|Equal34~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~19 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_alu_shift_oe~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_iorw~10 ( -// Equation(s): -// \z80_|execute_|ctl_iorw~10_combout = (!\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [2] & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_iorw~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_iorw~10 .lut_mask = 16'h0100; -defparam \z80_|execute_|ctl_iorw~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~18 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~18_combout = ((!\z80_|execute_|ctl_mWrite~16_combout & (!\z80_|execute_|ctl_mRead~36_combout & !\z80_|execute_|ctl_iorw~10_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) - - .dataa(\z80_|execute_|ctl_mWrite~16_combout ), - .datab(\z80_|execute_|ctl_mRead~36_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_iorw~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~18 .lut_mask = 16'h0F1F; -defparam \z80_|execute_|ctl_alu_shift_oe~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~20 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~20_combout = (\z80_|execute_|ctl_alu_shift_oe~17_combout & (\z80_|execute_|ctl_alu_shift_oe~18_combout & ((!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # (!\z80_|execute_|ctl_alu_shift_oe~19_combout )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~17_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~19_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~20 .lut_mask = 16'h2A00; -defparam \z80_|execute_|ctl_alu_shift_oe~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~13 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~13_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~12_combout ))) # (!\z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|execute_|ctl_ir_we~9_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|ctl_ir_we~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~13 .lut_mask = 16'hF5F7; -defparam \z80_|execute_|ctl_alu_bs_oe~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~9_combout = (\z80_|execute_|ctl_alu_bs_oe~13_combout & (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|execute_|ctl_alu_bs_oe~13_combout ), - .datac(\z80_|execute_|ctl_ir_we~10_combout ), - .datad(\z80_|execute_|ctl_ir_we~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~9 .lut_mask = 16'h444C; -defparam \z80_|execute_|ctl_alu_bs_oe~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~3 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~3_combout = (\z80_|execute_|ctl_alu_bs_oe~9_combout & (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~11_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~9_combout ), - .datad(\z80_|execute_|ctl_ir_we~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~3 .lut_mask = 16'h3070; -defparam \z80_|execute_|ctl_bus_db_oe~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N26 -cycloneive_lcell_comb \z80_|pla_decode_|Equal20~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal20~0_combout = (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [5] & (\z80_|execute_|comb~0_combout & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|execute_|comb~0_combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal20~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal20~0 .lut_mask = 16'h2000; -defparam \z80_|pla_decode_|Equal20~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal68~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal68~2_combout = (!\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [2] & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal68~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal68~2 .lut_mask = 16'h1000; -defparam \z80_|pla_decode_|Equal68~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~14 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~14_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal20~0_combout & !\z80_|pla_decode_|Equal68~2_combout ))) # (!\z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|pla_decode_|Equal20~0_combout ), - .datab(\z80_|pla_decode_|Equal68~2_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~14 .lut_mask = 16'hFF1F; -defparam \z80_|execute_|ctl_flags_bus~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~13 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~13_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal3~1_combout & ((!\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal21~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal21~0_combout ), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|pla_decode_|Equal3~1_combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~13 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_alu_op_low~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~15 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~15_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|execute_|ctl_alu_op_low~13_combout & !\z80_|execute_|ctl_alu_op_low~12_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|execute_|ctl_alu_op_low~13_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~15 .lut_mask = 16'hBBBF; -defparam \z80_|execute_|ctl_flags_bus~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~11_combout = (\z80_|execute_|ctl_flags_bus~15_combout & (((!\z80_|execute_|ctl_ir_we~14_combout & !\z80_|execute_|ctl_ir_we~8_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|execute_|ctl_ir_we~14_combout ), - .datac(\z80_|execute_|ctl_ir_we~8_combout ), - .datad(\z80_|execute_|ctl_flags_bus~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~11 .lut_mask = 16'h5700; -defparam \z80_|execute_|ctl_flags_bus~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N20 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~11 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~11_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|pla_decode_|Equal56~0_combout & !\z80_|execute_|ctl_alu_op_low~11_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|execute_|ctl_alu_op_low~11_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~11 .lut_mask = 16'hAFBF; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~10_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~11_combout & (((!\z80_|pla_decode_|Equal21~0_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )) # (!\z80_|pla_decode_|Equal63~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal63~0_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~11_combout ), - .datad(\z80_|pla_decode_|Equal21~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~10 .lut_mask = 16'h70F0; -defparam \z80_|execute_|ctl_flags_bus~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~8_combout = (\z80_|execute_|ixy_d~10_combout ) # ((\z80_|pla_decode_|Equal63~0_combout & ((\z80_|pla_decode_|Equal3~0_combout ) # (\z80_|pla_decode_|Equal32~0_combout )))) - - .dataa(\z80_|execute_|ixy_d~10_combout ), - .datab(\z80_|pla_decode_|Equal63~0_combout ), - .datac(\z80_|pla_decode_|Equal3~0_combout ), - .datad(\z80_|pla_decode_|Equal32~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~8 .lut_mask = 16'hEEEA; -defparam \z80_|execute_|ctl_flags_bus~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~9_combout = ((!\z80_|pla_decode_|Equal13~2_combout & (!\z80_|execute_|ctl_mRead~6_combout & !\z80_|execute_|ctl_flags_bus~8_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|execute_|ctl_mRead~6_combout ), - .datad(\z80_|execute_|ctl_flags_bus~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~9 .lut_mask = 16'h3337; -defparam \z80_|execute_|ctl_flags_bus~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~12 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~12_combout = (\z80_|execute_|ctl_flags_bus~14_combout & (\z80_|execute_|ctl_flags_bus~11_combout & (\z80_|execute_|ctl_flags_bus~10_combout & \z80_|execute_|ctl_flags_bus~9_combout ))) - - .dataa(\z80_|execute_|ctl_flags_bus~14_combout ), - .datab(\z80_|execute_|ctl_flags_bus~11_combout ), - .datac(\z80_|execute_|ctl_flags_bus~10_combout ), - .datad(\z80_|execute_|ctl_flags_bus~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~12 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_bus~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~11_combout = (\z80_|execute_|ctl_flags_xy_we~18_combout & (\z80_|execute_|ctl_alu_shift_oe~20_combout & (\z80_|execute_|ctl_bus_db_oe~3_combout & \z80_|execute_|ctl_flags_bus~12_combout ))) - - .dataa(\z80_|execute_|ctl_flags_xy_we~18_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~20_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~3_combout ), - .datad(\z80_|execute_|ctl_flags_bus~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~11 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_xy_we~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~12 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~12_combout = (\z80_|execute_|ctl_alu_shift_oe~41_combout & (\z80_|execute_|ctl_flags_xy_we~11_combout & ((!\z80_|execute_|ctl_state_alu~14_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~41_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~11_combout ), - .datad(\z80_|execute_|ctl_state_alu~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~12 .lut_mask = 16'h20A0; -defparam \z80_|execute_|ctl_flags_xy_we~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~6_combout = (\z80_|execute_|ctl_mWrite~3_combout & (!\z80_|execute_|ctl_ir_we~14_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|execute_|ctl_ir_we~8_combout )))) # -// (!\z80_|execute_|ctl_mWrite~3_combout & (((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|execute_|ctl_ir_we~8_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~3_combout ), - .datab(\z80_|execute_|ctl_ir_we~14_combout ), - .datac(\z80_|execute_|ctl_ir_we~8_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~6 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~7 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~7_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~6_combout & (\z80_|execute_|ctl_flags_alu~16_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal20~0_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ), - .datac(\z80_|execute_|ctl_flags_alu~16_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~7 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~4_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M4_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~4 .lut_mask = 16'h3030; -defparam \z80_|execute_|ctl_ir_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~8_combout = ((!\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~9_combout ))) # (!\z80_|execute_|ctl_ir_we~4_combout ) - - .dataa(\z80_|execute_|ctl_ir_we~12_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_ir_we~9_combout ), - .datad(\z80_|execute_|ctl_ir_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~8 .lut_mask = 16'h01FF; -defparam \z80_|execute_|ctl_alu_bs_oe~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~0_combout = (\z80_|execute_|ctl_alu_bs_oe~8_combout & (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_ir_we~10_combout ), - .datad(\z80_|execute_|ctl_alu_bs_oe~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~0 .lut_mask = 16'h3700; -defparam \z80_|execute_|ctl_bus_db_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~12 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~12_combout = (!\z80_|execute_|ctl_alu_op_low~9_combout & (((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|pla_decode_|Equal41~2_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~9_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|pla_decode_|Equal41~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~12 .lut_mask = 16'h0515; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~13 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~13_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~7_combout & (\z80_|execute_|ctl_bus_db_oe~0_combout & \z80_|execute_|ctl_alu_op1_sel_bus~12_combout )) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_bus_db_oe~0_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~13 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~14_combout = (\z80_|execute_|ctl_flags_xy_we~12_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~13_combout & ((!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # (!\z80_|pla_decode_|Equal48~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal48~0_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~12_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~14 .lut_mask = 16'h4C00; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~15 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_bus~15_combout = (((\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ) # (!\z80_|execute_|ctl_alu_op1_sel_bus~14_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~5_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~31_combout ) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~31_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~5_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_bus~15 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|ctl_alu_op1_sel_bus~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_66_oe~2 ( -// Equation(s): -// \z80_|execute_|ctl_66_oe~2_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|execute_|comb~0_combout & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal52~0_combout ), - .datac(\z80_|execute_|comb~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_66_oe~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_66_oe~2 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_66_oe~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla11M1T1_11 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|pla_decode_|Equal10~0_combout )) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal10~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel_pla11M1T1_11 .lut_mask = 16'h1100; -defparam \z80_|execute_|ctl_pf_sel_pla11M1T1_11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_zero~5_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal63~0_combout & (\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4]))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|pla_decode_|Equal63~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_zero~5 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_alu_op1_sel_zero~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_zero~4_combout = (\z80_|pla_decode_|Equal3~1_combout & (!\z80_|ir_|opcode [0] & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_zero~4 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_alu_op1_sel_zero~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_zero~combout = (\z80_|execute_|ctl_66_oe~2_combout ) # ((\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ) # (\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ))) - - .dataa(\z80_|execute_|ctl_66_oe~2_combout ), - .datab(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_zero .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_alu_op1_sel_zero .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N16 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[2] ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_high|Q [2] = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & (\z80_|alu_|db_high[2]~14_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .datac(\z80_|alu_|db_high[2]~14_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [2]), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[2] .lut_mask = 16'h00C0; -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N2 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|ena~0 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ) # (\z80_|execute_|ctl_alu_op1_sel_zero~combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_high|ena~0 .lut_mask = 16'hFFF0; -defparam \z80_|alu_|b2v_op1_latch_mux_high|ena~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y10_N17 -dffeas \z80_|alu_|op1_high[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [2]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_high [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_high[2] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_high[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_lq ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_lq~combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ixy_d~7_combout ) # ((\z80_|execute_|ixy_d~6_combout & !\z80_|ir_|opcode [3])))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|pla_decode_|Equal13~2_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_lq .lut_mask = 16'h88C8; -defparam \z80_|execute_|ctl_alu_op2_sel_lq .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~10_combout = (((!\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [3])) # (!\z80_|pla_decode_|Equal63~0_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal63~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~10 .lut_mask = 16'h1FFF; -defparam \z80_|execute_|ctl_alu_op_low~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N28 -cycloneive_lcell_comb \z80_|execute_|fMWrite~11 ( -// Equation(s): -// \z80_|execute_|fMWrite~11_combout = ((!\z80_|pla_decode_|Equal13~2_combout ) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|pla_decode_|Equal13~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~11 .lut_mask = 16'h5FFF; -defparam \z80_|execute_|fMWrite~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~21 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~21_combout = ((\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # (\z80_|execute_|ctl_alu_op_low~9_combout ))) # (!\z80_|execute_|fMWrite~11_combout ) - - .dataa(\z80_|execute_|fMWrite~11_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~21 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_alu_op_low~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N4 +// Location: LCCOMB_X21_Y12_N24 cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~22 ( // Equation(s): -// \z80_|execute_|ctl_alu_op_low~22_combout = ((\z80_|execute_|ctl_alu_op_low~21_combout ) # (!\z80_|execute_|ctl_alu_op1_sel_bus~10_combout )) # (!\z80_|execute_|ctl_alu_op_low~10_combout ) +// \z80_|execute_|ctl_alu_op_low~22_combout = (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ) - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op_low~10_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~21_combout ), + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), .cin(gnd), .combout(\z80_|execute_|ctl_alu_op_low~22_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~22 .lut_mask = 16'hFF3F; +defparam \z80_|execute_|ctl_alu_op_low~22 .lut_mask = 16'hAA00; defparam \z80_|execute_|ctl_alu_op_low~22 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y14_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~16 ( +// Location: LCCOMB_X26_Y16_N30 +cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_11 ( // Equation(s): -// \z80_|execute_|ctl_alu_op_low~16_combout = ((!\z80_|execute_|ixy_d~7_combout & ((\z80_|ir_|opcode [3]) # (!\z80_|execute_|ixy_d~6_combout )))) # (!\z80_|pla_decode_|Equal13~2_combout ) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|pla_decode_|Equal13~2_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~16 .lut_mask = 16'h7737; -defparam \z80_|execute_|ctl_alu_op_low~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~17 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~17_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~7_combout & (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & \z80_|execute_|ctl_alu_op_low~16_combout )) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), - .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_alu_op_low~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~17 .lut_mask = 16'h2200; -defparam \z80_|execute_|ctl_alu_op_low~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout = (!\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal44~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T4_ff~q ))) - - .dataa(\z80_|pla_decode_|Equal33~0_combout ), - .datab(\z80_|pla_decode_|Equal44~0_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel~36 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel~36_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|sequencer_|DFFE_T4_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|pla_decode_|Equal52~0_combout ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel~36 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_gp_sel~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~4_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout & (\z80_|execute_|ctl_state_alu~8_combout & (!\z80_|execute_|ctl_reg_gp_sel~36_combout & \z80_|execute_|ctl_alu_op2_sel_bus~9_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), - .datab(\z80_|execute_|ctl_state_alu~8_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel~36_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~4 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~5 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~5_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ) +// \z80_|resets_|SYNTHESIZED_WIRE_11~combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T2_ff~q ) .dataa(gnd), .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~5 .lut_mask = 16'h0F00; -defparam \z80_|execute_|ctl_state_alu~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~18 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~18_combout = (\z80_|execute_|ctl_mWrite~3_combout & ((\z80_|pla_decode_|Equal56~0_combout ) # ((\z80_|execute_|ctl_alu_op_low~11_combout )))) # (!\z80_|execute_|ctl_mWrite~3_combout & -// (\z80_|execute_|ctl_state_alu~5_combout & ((\z80_|pla_decode_|Equal56~0_combout ) # (\z80_|execute_|ctl_alu_op_low~11_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~3_combout ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|execute_|ctl_state_alu~5_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~18 .lut_mask = 16'hFAC8; -defparam \z80_|execute_|ctl_alu_op_low~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~19 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~19_combout = ((\z80_|execute_|ctl_alu_op_low~14_combout ) # ((\z80_|execute_|ctl_alu_op_low~18_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~38_combout ))) # (!\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~19 .lut_mask = 16'hFFDF; -defparam \z80_|execute_|ctl_alu_op_low~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~33 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~33_combout = (((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|execute_|ctl_alu_op_low~12_combout ) - - .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~33 .lut_mask = 16'h77F7; -defparam \z80_|execute_|ctl_alu_op_low~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~20 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~20_combout = (\z80_|execute_|ctl_alu_op_low~19_combout ) # (!\z80_|execute_|ctl_alu_op_low~33_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_op_low~19_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~33_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~20 .lut_mask = 16'hF0FF; -defparam \z80_|execute_|ctl_alu_op_low~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~23 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~23_combout = (\z80_|execute_|ctl_mRead~36_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout )))) # (!\z80_|execute_|ctl_mRead~36_combout & (\z80_|execute_|ixy_d~5_combout & -// ((\z80_|pla_decode_|Equal39~0_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~36_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~23 .lut_mask = 16'hECA8; -defparam \z80_|execute_|ctl_alu_op_low~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~24 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~24_combout = (\z80_|execute_|ctl_alu_op_low~22_combout ) # (((\z80_|execute_|ctl_alu_op_low~20_combout ) # (\z80_|execute_|ctl_alu_op_low~23_combout )) # (!\z80_|execute_|ctl_alu_op_low~17_combout )) - - .dataa(\z80_|execute_|ctl_alu_op_low~22_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~20_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~23_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~24 .lut_mask = 16'hFFFB; -defparam \z80_|execute_|ctl_alu_op_low~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~25 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~25_combout = (\z80_|execute_|ixy_d~9_combout & (((\z80_|pla_decode_|Equal40~1_combout ) # (\z80_|pla_decode_|Equal39~0_combout )))) # (!\z80_|execute_|ixy_d~9_combout & (\z80_|execute_|ixy_d~5_combout & -// (\z80_|pla_decode_|Equal40~1_combout ))) - - .dataa(\z80_|execute_|ixy_d~9_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|pla_decode_|Equal40~1_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~25 .lut_mask = 16'hEAE0; -defparam \z80_|execute_|ctl_alu_op_low~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~34 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~34_combout = (\z80_|execute_|ctl_alu_op_low~25_combout ) # ((\z80_|pla_decode_|Equal21~1_combout & (\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ))) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|ctl_alu_op_low~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~34 .lut_mask = 16'hFF08; -defparam \z80_|execute_|ctl_alu_op_low~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~combout = ((\z80_|execute_|ctl_alu_op_low~24_combout ) # ((\z80_|execute_|ctl_alu_op_low~34_combout ) # (\z80_|execute_|ctl_alu_op_low~26_combout ))) # (!\z80_|execute_|ctl_alu_op_low~15_combout ) - - .dataa(\z80_|execute_|ctl_alu_op_low~15_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~24_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~34_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~26_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_alu_op_low .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~40 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~40_combout = ((\z80_|execute_|ixy_d~9_combout & ((\z80_|execute_|ctl_mRead~26_combout ) # (\z80_|execute_|ctl_mRead~27_combout )))) # (!\z80_|execute_|ctl_flags_xy_we~18_combout ) - - .dataa(\z80_|execute_|ctl_mRead~26_combout ), - .datab(\z80_|execute_|ctl_mRead~27_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~18_combout ), - .datad(\z80_|execute_|ixy_d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~40 .lut_mask = 16'hEF0F; -defparam \z80_|execute_|ctl_alu_shift_oe~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~37 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~37_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_alu_oe~3_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) - - .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~37 .lut_mask = 16'hAE00; -defparam \z80_|execute_|ctl_alu_shift_oe~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~39 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~39_combout = (\z80_|execute_|ctl_alu_shift_oe~37_combout ) # (((\z80_|execute_|ctl_state_alu~14_combout & \z80_|execute_|ctl_alu_shift_oe~14_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~5_combout )) - - .dataa(\z80_|execute_|ctl_state_alu~14_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~37_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~39 .lut_mask = 16'hECFF; -defparam \z80_|execute_|ctl_alu_shift_oe~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~46 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~46_combout = (\z80_|execute_|ctl_alu_shift_oe~41_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|pla_decode_|Equal48~0_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~41_combout ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|pla_decode_|Equal48~0_combout ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), .datad(\z80_|sequencer_|DFFE_M1_ff~q ), .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~46_combout ), + .combout(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~46 .lut_mask = 16'hAA2A; -defparam \z80_|execute_|ctl_alu_shift_oe~46 .sum_lutc_input = "datac"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_11 .lut_mask = 16'hFF0F; +defparam \z80_|resets_|SYNTHESIZED_WIRE_11 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X40_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~42 ( +// Location: LCCOMB_X31_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~4 ( // Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~42_combout = (\z80_|execute_|ctl_alu_shift_oe~40_combout ) # (((\z80_|execute_|ctl_alu_shift_oe~39_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~46_combout )) # (!\z80_|execute_|ctl_alu_op_low~17_combout )) +// \z80_|execute_|ctl_ir_we~4_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M4_ff~q ) - .dataa(\z80_|execute_|ctl_alu_shift_oe~40_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~39_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~46_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~42 .lut_mask = 16'hFBFF; -defparam \z80_|execute_|ctl_alu_shift_oe~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~21 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~21_combout = (\z80_|execute_|ctl_ir_we~15_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # ((\z80_|execute_|ctl_state_alu~6_combout & !\z80_|execute_|ctl_ir_we~4_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~6_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_ir_we~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~21 .lut_mask = 16'hF200; -defparam \z80_|execute_|ctl_alu_shift_oe~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~45 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~45_combout = (\z80_|execute_|ctl_alu_shift_oe~21_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|execute_|ctl_alu_shift_oe~21_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|ctl_ir_we~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~45 .lut_mask = 16'hC4CC; -defparam \z80_|execute_|ctl_alu_shift_oe~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~22 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~22_combout = (\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_state_alu~6_combout ) # (\z80_|execute_|ctl_alu_shift_oe~45_combout )))) # -// (!\z80_|execute_|ctl_ir_we~9_combout & (((\z80_|execute_|ctl_alu_shift_oe~45_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~6_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_ir_we~9_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~45_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~22 .lut_mask = 16'h3F20; -defparam \z80_|execute_|ctl_alu_shift_oe~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~23 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~23_combout = (\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # (\z80_|execute_|ctl_alu_shift_oe~22_combout )))) # -// (!\z80_|execute_|ctl_ir_we~9_combout & (((\z80_|execute_|ctl_alu_shift_oe~22_combout )))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~22_combout ), - .datac(\z80_|execute_|ctl_ir_we~9_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~23 .lut_mask = 16'h0CEC; -defparam \z80_|execute_|ctl_alu_shift_oe~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~24 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~24_combout = (\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_mWrite~7_combout ) # (\z80_|execute_|ctl_alu_shift_oe~23_combout )))) # -// (!\z80_|execute_|ctl_ir_we~12_combout & (((\z80_|execute_|ctl_alu_shift_oe~23_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~7_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~23_combout ), - .datad(\z80_|execute_|ctl_ir_we~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~24 .lut_mask = 16'h32F0; -defparam \z80_|execute_|ctl_alu_shift_oe~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~25 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~25_combout = (\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|execute_|ctl_alu_shift_oe~24_combout ) # (\z80_|execute_|ctl_mWrite~3_combout )))) # -// (!\z80_|execute_|ctl_ir_we~12_combout & (\z80_|execute_|ctl_alu_shift_oe~24_combout )) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~24_combout ), - .datab(\z80_|execute_|ctl_ir_we~12_combout ), - .datac(\z80_|execute_|ctl_mWrite~3_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~25 .lut_mask = 16'h22EA; -defparam \z80_|execute_|ctl_alu_shift_oe~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~14_combout = (\z80_|execute_|ctl_ir_we~11_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # ((\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~14 .lut_mask = 16'hC0C8; -defparam \z80_|execute_|ctl_alu_bs_oe~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~26 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~26_combout = (!\z80_|execute_|ctl_alu_bs_oe~14_combout & ((\z80_|execute_|ctl_alu_shift_oe~25_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout & \z80_|execute_|ctl_mWrite~7_combout )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~25_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_mWrite~7_combout ), - .datad(\z80_|execute_|ctl_alu_bs_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~26 .lut_mask = 16'h00EA; -defparam \z80_|execute_|ctl_alu_shift_oe~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~27 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~27_combout = (\z80_|execute_|ctl_ir_we~7_combout & ((\z80_|execute_|ctl_state_alu~6_combout ) # ((\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ctl_bus_db_oe~1_combout )))) # (!\z80_|execute_|ctl_ir_we~7_combout & -// (\z80_|execute_|ixy_d~7_combout & ((!\z80_|execute_|ctl_bus_db_oe~1_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~27 .lut_mask = 16'hA0EC; -defparam \z80_|execute_|ctl_alu_shift_oe~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~28 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~28_combout = ((\z80_|execute_|ctl_alu_shift_oe~27_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~20_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~44_combout ) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~44_combout ), + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), .datab(gnd), - .datac(\z80_|execute_|ctl_alu_shift_oe~20_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~27_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~28 .lut_mask = 16'hFF5F; -defparam \z80_|execute_|ctl_alu_shift_oe~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~10_combout = (\z80_|execute_|ctl_ir_we~7_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) # (!\z80_|execute_|ctl_ir_we~7_combout & (\z80_|execute_|ctl_ir_we~4_combout -// & (\z80_|execute_|ctl_ir_we~10_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_ir_we~10_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~10 .lut_mask = 16'hEAC8; -defparam \z80_|execute_|ctl_alu_bs_oe~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~11_combout = (\z80_|execute_|ctl_alu_bs_oe~10_combout ) # ((\z80_|execute_|ctl_alu_bs_oe~14_combout ) # ((!\z80_|execute_|ctl_alu_bs_oe~8_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~9_combout ))) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~10_combout ), - .datab(\z80_|execute_|ctl_alu_bs_oe~14_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~9_combout ), - .datad(\z80_|execute_|ctl_alu_bs_oe~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~11 .lut_mask = 16'hEFFF; -defparam \z80_|execute_|ctl_alu_bs_oe~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~32 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~32_combout = (!\z80_|execute_|ctl_alu_bs_oe~11_combout & ((\z80_|execute_|ctl_alu_shift_oe~28_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~31_combout ))) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_shift_oe~28_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~31_combout ), - .datad(\z80_|execute_|ctl_alu_bs_oe~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~32 .lut_mask = 16'h00CF; -defparam \z80_|execute_|ctl_alu_shift_oe~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~33 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~33_combout = (\z80_|execute_|ctl_alu_shift_oe~32_combout ) # ((!\z80_|execute_|ctl_alu_bs_oe~combout & ((\z80_|execute_|ctl_alu_shift_oe~16_combout ) # (!\z80_|execute_|ctl_alu_op_low~15_combout )))) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datab(\z80_|execute_|ctl_alu_op_low~15_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~16_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~33 .lut_mask = 16'hFF51; -defparam \z80_|execute_|ctl_alu_shift_oe~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~0_combout = ((!\z80_|execute_|ctl_alu_op_low~12_combout & (!\z80_|execute_|ctl_alu_op_low~11_combout & !\z80_|pla_decode_|Equal56~0_combout ))) # (!\z80_|execute_|ctl_state_alu~5_combout ) - - .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~11_combout ), - .datac(\z80_|execute_|ctl_state_alu~5_combout ), - .datad(\z80_|pla_decode_|Equal56~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~0 .lut_mask = 16'h0F1F; -defparam \z80_|execute_|ctl_reg_use_sp~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~1 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~1_combout = (\z80_|execute_|ctl_reg_use_sp~0_combout & \z80_|execute_|nextM~11_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_use_sp~0_combout ), .datac(gnd), - .datad(\z80_|execute_|nextM~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~1 .lut_mask = 16'hCC00; -defparam \z80_|execute_|ctl_reg_use_sp~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~12 ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~12_combout = (\z80_|execute_|ctl_alu_bs_oe~14_combout ) # ((!\z80_|execute_|ctl_alu_bs_oe~8_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~9_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_bs_oe~14_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~9_combout ), - .datad(\z80_|execute_|ctl_alu_bs_oe~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe~12 .lut_mask = 16'hCFFF; -defparam \z80_|execute_|ctl_alu_bs_oe~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~47 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~47_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|sequencer_|DFFE_M1_ff~q & \z80_|execute_|ctl_ir_we~7_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|ctl_ir_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~47 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_shift_oe~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~34 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~34_combout = (\z80_|execute_|ctl_ir_we~10_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_state_alu~6_combout ) # (\z80_|execute_|ctl_alu_shift_oe~47_combout )))) # -// (!\z80_|execute_|ctl_ir_we~10_combout & (((\z80_|execute_|ctl_alu_shift_oe~47_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~6_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_ir_we~10_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~47_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~34 .lut_mask = 16'h3F20; -defparam \z80_|execute_|ctl_alu_shift_oe~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~35 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~35_combout = (!\z80_|execute_|ctl_alu_bs_oe~12_combout & ((\z80_|execute_|ctl_alu_shift_oe~34_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & \z80_|execute_|ctl_ir_we~10_combout )))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|ctl_ir_we~10_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~12_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~34_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~35 .lut_mask = 16'h0F08; -defparam \z80_|execute_|ctl_alu_shift_oe~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~36 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~36_combout = (((\z80_|execute_|ctl_alu_shift_oe~35_combout ) # (!\z80_|execute_|ctl_reg_use_sp~1_combout )) # (!\z80_|execute_|ctl_flags_bus~12_combout )) # (!\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ), - .datab(\z80_|execute_|ctl_flags_bus~12_combout ), - .datac(\z80_|execute_|ctl_reg_use_sp~1_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~35_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~36 .lut_mask = 16'hFF7F; -defparam \z80_|execute_|ctl_alu_shift_oe~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~43 ( -// Equation(s): -// \z80_|execute_|ctl_alu_shift_oe~43_combout = (\z80_|execute_|ctl_alu_shift_oe~42_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~26_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~33_combout ) # (\z80_|execute_|ctl_alu_shift_oe~36_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~42_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~26_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~33_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_shift_oe~43 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_alu_shift_oe~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_lo~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_lo~9_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q ))) # (!\z80_|pla_decode_|Equal47~0_combout ) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|M5~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_lo~9 .lut_mask = 16'hF5F7; -defparam \z80_|execute_|ctl_reg_in_lo~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_oe~0_combout = ((\z80_|execute_|ctl_66_oe~2_combout ) # ((\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_alu_shift_oe~14_combout ))) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ) - - .dataa(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datab(\z80_|execute_|ctl_66_oe~2_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_oe~0 .lut_mask = 16'hFDDD; -defparam \z80_|execute_|ctl_alu_op1_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout = (\z80_|pla_decode_|Equal48~0_combout & (\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )) - - .dataa(\z80_|pla_decode_|Equal48~0_combout ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 .lut_mask = 16'h0088; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_oe~1 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_oe~1_combout = (\z80_|execute_|ctl_alu_op1_oe~0_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ) # ((\z80_|execute_|ctl_alu_oe~3_combout & \z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_alu_op1_oe~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_oe~1 .lut_mask = 16'hFFF8; -defparam \z80_|execute_|ctl_alu_op1_oe~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~8_combout = (((!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4])) # (!\z80_|pla_decode_|Equal63~0_combout )) # (!\z80_|nM1_int~2_combout ) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal63~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~8 .lut_mask = 16'h777F; -defparam \z80_|execute_|ctl_flags_xy_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~9_combout = (!\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout & (\z80_|execute_|ctl_flags_xy_we~8_combout & ((!\z80_|sequencer_|DFFE_T5_ff~q ) # (!\z80_|execute_|ixy_d~15_combout )))) - - .dataa(\z80_|execute_|ixy_d~15_combout ), - .datab(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .datac(\z80_|sequencer_|DFFE_T5_ff~q ), - .datad(\z80_|execute_|ctl_flags_xy_we~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~9 .lut_mask = 16'h1300; -defparam \z80_|execute_|ctl_flags_xy_we~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N18 -cycloneive_lcell_comb \z80_|pla_decode_|Equal8~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal8~0_combout = (\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [2] & \z80_|ir_|opcode [0])) - - .dataa(gnd), - .datab(\z80_|ir_|opcode [1]), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal8~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal8~0 .lut_mask = 16'h0C00; -defparam \z80_|pla_decode_|Equal8~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~9_combout = (((!\z80_|nM1_int~2_combout & !\z80_|execute_|ixy_d~6_combout )) # (!\z80_|execute_|ctl_mWrite~2_combout )) # (!\z80_|pla_decode_|Equal8~0_combout ) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal8~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~2_combout ), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~9 .lut_mask = 16'h3F7F; -defparam \z80_|execute_|ctl_flags_alu~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~4_combout = ((!\z80_|pla_decode_|Equal40~1_combout & (!\z80_|pla_decode_|Equal39~0_combout & !\z80_|pla_decode_|Equal21~1_combout ))) # (!\z80_|execute_|ixy_d~8_combout ) - - .dataa(\z80_|pla_decode_|Equal40~1_combout ), - .datab(\z80_|pla_decode_|Equal39~0_combout ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|execute_|ixy_d~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~4 .lut_mask = 16'h01FF; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~3_combout = (\z80_|pla_decode_|Equal21~1_combout & (!\z80_|execute_|ctl_mRead~11_combout & ((!\z80_|pla_decode_|Equal10~0_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) # (!\z80_|pla_decode_|Equal21~1_combout & -// (((!\z80_|pla_decode_|Equal10~0_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|execute_|ctl_mRead~11_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|pla_decode_|Equal10~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~3 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_flags_sz_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal11~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal11~1_combout = (!\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [0]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal11~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal11~1 .lut_mask = 16'h000F; -defparam \z80_|pla_decode_|Equal11~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout = (\z80_|execute_|ixy_d~7_combout & (\z80_|execute_|ctl_mWrite~2_combout & (!\z80_|ir_|opcode [2] & \z80_|pla_decode_|Equal11~1_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|pla_decode_|Equal11~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~10_combout = (\z80_|execute_|ctl_flags_alu~9_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~4_combout & (\z80_|execute_|ctl_flags_sz_we~3_combout & !\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ))) - - .dataa(\z80_|execute_|ctl_flags_alu~9_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), - .datac(\z80_|execute_|ctl_flags_sz_we~3_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~10 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_flags_alu~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~11_combout = (\z80_|execute_|ctl_flags_xy_we~9_combout & (\z80_|execute_|ctl_flags_alu~10_combout & ((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|execute_|ixy_d~15_combout )))) - - .dataa(\z80_|execute_|ixy_d~15_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~9_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|execute_|ctl_flags_alu~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~11 .lut_mask = 16'h4C00; -defparam \z80_|execute_|ctl_flags_alu~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout = (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal63~0_combout & (!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4]))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal63~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 .lut_mask = 16'h0008; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla82M1T1_16 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout = (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [0] & (\z80_|nM1_int~2_combout & \z80_|pla_decode_|Equal3~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal3~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel_pla82M1T1_16 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_pf_sel_pla82M1T1_16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~13 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~13_combout = (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|execute_|ctl_mRead~6_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|execute_|ctl_mRead~6_combout ), .datad(\z80_|sequencer_|DFFE_M4_ff~q ), .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~13_combout ), + .combout(\z80_|execute_|ctl_ir_we~4_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~13 .lut_mask = 16'h3F7F; -defparam \z80_|execute_|ctl_flags_use_cf2~13 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_ir_we~4 .lut_mask = 16'h5500; +defparam \z80_|execute_|ctl_ir_we~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~7 ( +// Location: LCCOMB_X26_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_state_iy_set~2 ( // Equation(s): -// \z80_|execute_|ctl_flags_cf_we~7_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # (((!\z80_|pla_decode_|Equal55~0_combout ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|pla_decode_|Equal13~0_combout )) +// \z80_|execute_|ctl_state_iy_set~2_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal3~2_combout ))) - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|pla_decode_|Equal55~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~7 .lut_mask = 16'hBFFF; -defparam \z80_|execute_|ctl_flags_cf_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel[0]~2 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel[0]~2_combout = (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (\z80_|execute_|ctl_flags_use_cf2~13_combout & \z80_|execute_|ctl_flags_cf_we~7_combout )) - - .dataa(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .datab(\z80_|execute_|ctl_flags_use_cf2~13_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_flags_cf_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel[0]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel[0]~2 .lut_mask = 16'h4400; -defparam \z80_|execute_|ctl_pf_sel[0]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~2 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~2_combout = (\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_T1_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~2 .lut_mask = 16'h00F0; -defparam \z80_|execute_|ctl_alu_oe~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~25 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~25_combout = (\z80_|execute_|ctl_ir_we~14_combout & (!\z80_|execute_|ixy_d~7_combout & ((!\z80_|execute_|ctl_alu_oe~2_combout )))) # (!\z80_|execute_|ctl_ir_we~14_combout & (((!\z80_|execute_|ctl_alu_oe~2_combout ) # -// (!\z80_|execute_|ctl_ir_we~8_combout )))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_ir_we~14_combout ), - .datac(\z80_|execute_|ctl_ir_we~8_combout ), - .datad(\z80_|execute_|ctl_alu_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~25 .lut_mask = 16'h0377; -defparam \z80_|execute_|ctl_bus_inc_oe~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_we~5_combout = (\z80_|execute_|ctl_bus_inc_oe~25_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|execute_|ctl_ir_we~8_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|execute_|ctl_bus_inc_oe~25_combout ), - .datac(\z80_|execute_|ctl_ir_we~8_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_we~5 .lut_mask = 16'hCC8C; -defparam \z80_|execute_|ctl_flags_hf_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~10_combout = (\z80_|execute_|ctl_flags_hf_we~5_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|pla_decode_|Equal13~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(\z80_|execute_|ctl_flags_hf_we~5_combout ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~10 .lut_mask = 16'hCCC4; -defparam \z80_|execute_|ctl_flags_pf_we~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~48 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~48_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|execute_|ctl_alu_op_low~13_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~13_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~48 .lut_mask = 16'h3331; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~2_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout & (\z80_|execute_|ctl_pf_sel[0]~2_combout & (\z80_|execute_|ctl_flags_pf_we~10_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .datab(\z80_|execute_|ctl_pf_sel[0]~2_combout ), - .datac(\z80_|execute_|ctl_flags_pf_we~10_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~2 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_flags_pf_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~3_combout = (\z80_|execute_|ctl_flags_pf_we~2_combout & (((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_ir_we~12_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_flags_pf_we~2_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_ir_we~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~3 .lut_mask = 16'h0A2A; -defparam \z80_|execute_|ctl_flags_pf_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y19_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~17 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~17_combout = (((!\z80_|pla_decode_|Equal13~0_combout ) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|pla_decode_|Equal55~0_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~17 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_flags_xy_we~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N6 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~5 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~5_combout = ((!\z80_|pla_decode_|Equal40~1_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal39~0_combout ))) # (!\z80_|execute_|ixy_d~6_combout ) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|pla_decode_|Equal40~1_combout ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~5 .lut_mask = 16'h5557; -defparam \z80_|reg_control_|reg_sys_we_lo~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N26 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~6 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~6_combout = (\z80_|execute_|ctl_flags_xy_we~17_combout & (\z80_|reg_control_|reg_sys_we_lo~5_combout & ((!\z80_|execute_|ctl_alu_op_low~8_combout ) # (!\z80_|pla_decode_|Equal56~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal56~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~17_combout ), - .datad(\z80_|reg_control_|reg_sys_we_lo~5_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~6 .lut_mask = 16'h7000; -defparam \z80_|reg_control_|reg_sys_we_lo~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~10_combout = (\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ixy_d~7_combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) # (!\z80_|pla_decode_|Equal56~0_combout & -// (((!\z80_|nM1_int~2_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal56~0_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|pla_decode_|Equal20~0_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~10 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_flags_xy_we~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout = (\z80_|execute_|ctl_mWrite~2_combout & (\z80_|execute_|ctl_state_alu~4_combout & (\z80_|pla_decode_|Equal2~0_combout & !\z80_|ir_|opcode [0]))) - - .dataa(\z80_|execute_|ctl_mWrite~2_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|pla_decode_|Equal2~0_combout ), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~7 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~7_combout = (\z80_|ir_|opcode [7] & (!\z80_|pla_decode_|Equal33~0_combout & (!\z80_|ir_|opcode [6] & !\z80_|decode_state_|table_xx~0_combout ))) - - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|ir_|opcode [6]), - .datad(\z80_|decode_state_|table_xx~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~7 .lut_mask = 16'h0002; -defparam \z80_|execute_|ctl_state_alu~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~1 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~1_combout = ((!\z80_|execute_|ctl_state_alu~14_combout & (!\z80_|execute_|ctl_state_alu~7_combout & !\z80_|pla_decode_|Equal52~1_combout ))) # (!\z80_|nM1_int~2_combout ) - - .dataa(\z80_|execute_|ctl_state_alu~14_combout ), - .datab(\z80_|execute_|ctl_state_alu~7_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal52~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~1 .lut_mask = 16'h0F1F; -defparam \z80_|execute_|ctl_flags_sz_we~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~2_combout = (\z80_|reg_control_|reg_sys_we_lo~6_combout & (\z80_|execute_|ctl_flags_xy_we~10_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout & \z80_|execute_|ctl_flags_sz_we~1_combout ))) - - .dataa(\z80_|reg_control_|reg_sys_we_lo~6_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~10_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), - .datad(\z80_|execute_|ctl_flags_sz_we~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~2 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_flags_cf_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~6_combout = (\z80_|nM1_int~2_combout & (!\z80_|execute_|ctl_ir_we~9_combout & ((!\z80_|execute_|ctl_mWrite~3_combout ) # (!\z80_|execute_|ctl_ir_we~15_combout )))) # (!\z80_|nM1_int~2_combout & -// (((!\z80_|execute_|ctl_mWrite~3_combout )) # (!\z80_|execute_|ctl_ir_we~15_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_ir_we~9_combout ), - .datad(\z80_|execute_|ctl_mWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~6 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_alu_core_S~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~7 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~7_combout = (\z80_|execute_|ctl_alu_core_S~6_combout & (((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_alu_oe~2_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~9_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_alu_core_S~6_combout ), - .datad(\z80_|execute_|ctl_alu_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~7 .lut_mask = 16'h10F0; -defparam \z80_|execute_|ctl_alu_core_S~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~4_combout = (\z80_|execute_|ctl_ir_we~7_combout & (!\z80_|execute_|ctl_mWrite~3_combout & ((!\z80_|execute_|ctl_ir_we~10_combout ) # (!\z80_|nM1_int~2_combout )))) # (!\z80_|execute_|ctl_ir_we~7_combout & -// (((!\z80_|execute_|ctl_ir_we~10_combout ) # (!\z80_|nM1_int~2_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_mWrite~3_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_ir_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~4 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_alu_core_S~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~5_combout = (\z80_|execute_|ctl_alu_core_S~4_combout & (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~7_combout )) # (!\z80_|execute_|ctl_alu_oe~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_S~4_combout ), - .datab(\z80_|execute_|ctl_ir_we~10_combout ), - .datac(\z80_|execute_|ctl_ir_we~7_combout ), - .datad(\z80_|execute_|ctl_alu_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~5 .lut_mask = 16'h02AA; -defparam \z80_|execute_|ctl_alu_core_S~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout = (\z80_|execute_|ctl_mWrite~2_combout & (\z80_|pla_decode_|Equal8~0_combout & (\z80_|sequencer_|DFFE_T5_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ))) - - .dataa(\z80_|execute_|ctl_mWrite~2_combout ), - .datab(\z80_|pla_decode_|Equal8~0_combout ), - .datac(\z80_|sequencer_|DFFE_T5_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_alu_res_oe~0_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout & (((!\z80_|pla_decode_|Equal69~0_combout & !\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal69~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_res_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_res_oe~0 .lut_mask = 16'h0133; -defparam \z80_|execute_|ctl_alu_res_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~15 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~15_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_mWrite~2_combout & !\z80_|sequencer_|DFFE_M1_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~2_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~15 .lut_mask = 16'h0040; -defparam \z80_|execute_|ctl_alu_oe~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~1 ( -// Equation(s): -// \z80_|execute_|ctl_alu_res_oe~1_combout = (\z80_|execute_|ctl_alu_core_S~7_combout & (\z80_|execute_|ctl_alu_core_S~5_combout & (\z80_|execute_|ctl_alu_res_oe~0_combout & !\z80_|execute_|ctl_alu_oe~15_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_S~7_combout ), - .datab(\z80_|execute_|ctl_alu_core_S~5_combout ), - .datac(\z80_|execute_|ctl_alu_res_oe~0_combout ), - .datad(\z80_|execute_|ctl_alu_oe~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_res_oe~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_res_oe~1 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_alu_res_oe~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~2 ( -// Equation(s): -// \z80_|execute_|ctl_alu_res_oe~2_combout = (\z80_|execute_|ctl_flags_alu~11_combout & (\z80_|execute_|ctl_flags_pf_we~3_combout & (\z80_|execute_|ctl_flags_cf_we~2_combout & \z80_|execute_|ctl_alu_res_oe~1_combout ))) - - .dataa(\z80_|execute_|ctl_flags_alu~11_combout ), - .datab(\z80_|execute_|ctl_flags_pf_we~3_combout ), - .datac(\z80_|execute_|ctl_flags_cf_we~2_combout ), - .datad(\z80_|execute_|ctl_alu_res_oe~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_res_oe~2 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_res_oe~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_oe~0_combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # ((!\z80_|ir_|opcode [3] & \z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|pla_decode_|Equal13~2_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_oe~0 .lut_mask = 16'h8C88; -defparam \z80_|execute_|ctl_alu_op2_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N4 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~2 ( -// Equation(s): -// \z80_|alu_|db_high[3]~2_combout = (\z80_|execute_|ctl_alu_bs_oe~combout ) # ((\z80_|execute_|ctl_alu_op1_oe~1_combout ) # ((\z80_|execute_|ctl_alu_op2_oe~0_combout ) # (!\z80_|execute_|ctl_alu_res_oe~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~2 .lut_mask = 16'hFFEF; -defparam \z80_|alu_|db_high[3]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N0 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~3 ( -// Equation(s): -// \z80_|alu_|db_high[3]~3_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout ) # (\z80_|alu_|db_high[3]~2_combout ) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datab(gnd), - .datac(\z80_|alu_|db_high[3]~2_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~3 .lut_mask = 16'hFAFA; -defparam \z80_|alu_|db_high[3]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N20 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~24 ( -// Equation(s): -// \z80_|alu_|db_low[2]~24_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout & (\z80_|alu_|db_low[2]~3_combout & (\z80_|alu_|db_low[2]~6_combout ))) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout & (((\z80_|alu_|db_low[2]~3_combout & -// \z80_|alu_|db_low[2]~6_combout )) # (!\z80_|alu_|db_high[3]~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datab(\z80_|alu_|db_low[2]~3_combout ), - .datac(\z80_|alu_|db_low[2]~6_combout ), - .datad(\z80_|alu_|db_high[3]~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~24 .lut_mask = 16'hC0D5; -defparam \z80_|alu_|db_low[2]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N24 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~7 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~7_combout = (\z80_|reg_control_|reg_sys_we_lo~6_combout & ((!\z80_|execute_|ixy_d~15_combout ) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(\z80_|reg_control_|reg_sys_we_lo~6_combout ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~7 .lut_mask = 16'h0AAA; -defparam \z80_|reg_control_|reg_sys_we_lo~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout = (!\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|nM1_int~2_combout & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|pla_decode_|Equal3~1_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~19 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout = ((!\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_ir_we~8_combout & !\z80_|execute_|ctl_ir_we~10_combout ))) # (!\z80_|nM1_int~2_combout ) - - .dataa(\z80_|execute_|ctl_ir_we~9_combout ), - .datab(\z80_|execute_|ctl_ir_we~8_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_ir_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~19 .lut_mask = 16'h0F1F; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~8_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout & (\z80_|execute_|ctl_flags_sz_we~1_combout & (!\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout & \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~1_combout ), - .datac(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~8 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_reg_in_hi~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~8_combout = (\z80_|reg_control_|reg_sys_we_lo~7_combout & (\z80_|execute_|ctl_reg_in_hi~8_combout & ((!\z80_|execute_|ctl_ir_we~4_combout ) # (!\z80_|pla_decode_|Equal13~2_combout )))) - - .dataa(\z80_|reg_control_|reg_sys_we_lo~7_combout ), - .datab(\z80_|pla_decode_|Equal13~2_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~8 .lut_mask = 16'h2A00; -defparam \z80_|execute_|ctl_alu_oe~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~4 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~4_combout = ((!\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_alu_op_low~12_combout & !\z80_|execute_|ctl_alu_op_low~11_combout ))) # (!\z80_|execute_|ixy_d~7_combout ) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~12_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~4 .lut_mask = 16'h5557; -defparam \z80_|execute_|ctl_alu_oe~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~9 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~9_combout = (\z80_|execute_|ctl_flags_use_cf2~13_combout & (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_mWrite~3_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~7_combout ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_flags_use_cf2~13_combout ), - .datad(\z80_|execute_|ctl_mWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~9 .lut_mask = 16'h10F0; -defparam \z80_|execute_|ctl_mWrite~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~10_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~9_combout ))) # (!\z80_|sequencer_|M5~q ) - - .dataa(\z80_|sequencer_|M5~q ), - .datab(\z80_|execute_|ctl_ir_we~15_combout ), - .datac(\z80_|execute_|ctl_ir_we~9_combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~10 .lut_mask = 16'hFF57; -defparam \z80_|execute_|ctl_alu_core_S~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~43 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~43_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~7_combout ))) # (!\z80_|sequencer_|M5~q ) - - .dataa(\z80_|sequencer_|M5~q ), - .datab(\z80_|execute_|ctl_ir_we~10_combout ), - .datac(\z80_|execute_|ctl_ir_we~7_combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~43 .lut_mask = 16'hFF57; -defparam \z80_|execute_|ctl_bus_inc_oe~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~26 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~26_combout = (\z80_|execute_|ctl_alu_core_S~10_combout & (\z80_|execute_|ctl_bus_inc_oe~43_combout & \z80_|execute_|ctl_bus_inc_oe~25_combout )) - - .dataa(\z80_|execute_|ctl_alu_core_S~10_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~26 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_bus_inc_oe~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_we~5_combout = (\z80_|execute_|ctl_mWrite~9_combout & (\z80_|execute_|ctl_bus_inc_oe~26_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|execute_|ctl_mRead~26_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~9_combout ), - .datab(\z80_|execute_|ctl_mRead~26_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~26_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~5 .lut_mask = 16'h20A0; -defparam \z80_|execute_|ctl_bus_db_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~9_combout = (\z80_|execute_|ctl_alu_oe~8_combout & (\z80_|execute_|ctl_alu_oe~4_combout & (\z80_|execute_|ctl_reg_in_lo~9_combout & \z80_|execute_|ctl_bus_db_we~5_combout ))) - - .dataa(\z80_|execute_|ctl_alu_oe~8_combout ), - .datab(\z80_|execute_|ctl_alu_oe~4_combout ), - .datac(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datad(\z80_|execute_|ctl_bus_db_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~9 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_oe~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~11_combout = (\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_alu_oe~3_combout ) # ((\z80_|pla_decode_|Equal69~0_combout ) # (\z80_|execute_|ctl_mWrite~16_combout )))) - - .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), - .datab(\z80_|pla_decode_|Equal69~0_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_mWrite~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~11 .lut_mask = 16'hF0E0; -defparam \z80_|execute_|ctl_alu_oe~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~5_combout = (\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|execute_|ctl_mWrite~16_combout & ((!\z80_|execute_|ctl_mRead~11_combout ) # (!\z80_|execute_|ctl_mRead~36_combout )))) # (!\z80_|execute_|ctl_state_alu~4_combout & -// (((!\z80_|execute_|ctl_mRead~11_combout ) # (!\z80_|execute_|ctl_mRead~36_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_mWrite~16_combout ), - .datac(\z80_|execute_|ctl_mRead~36_combout ), - .datad(\z80_|execute_|ctl_mRead~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~5 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_alu_oe~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~11_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_ir_we~12_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~11_combout ), - .datab(\z80_|execute_|ctl_ir_we~12_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~11 .lut_mask = 16'hFFF1; -defparam \z80_|execute_|ctl_alu_core_S~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~6_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout & (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal20~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~6 .lut_mask = 16'h0013; -defparam \z80_|execute_|ctl_alu_oe~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~7 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~7_combout = (\z80_|execute_|ctl_alu_oe~6_combout & (((!\z80_|execute_|ctl_mRead~27_combout & !\z80_|execute_|ctl_mRead~26_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_mRead~27_combout ), - .datac(\z80_|execute_|ctl_mRead~26_combout ), - .datad(\z80_|execute_|ctl_alu_oe~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~7 .lut_mask = 16'h5700; -defparam \z80_|execute_|ctl_alu_oe~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~12 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~12_combout = (\z80_|execute_|ctl_alu_oe~11_combout ) # (((!\z80_|execute_|ctl_alu_oe~7_combout ) # (!\z80_|execute_|ctl_alu_core_S~11_combout )) # (!\z80_|execute_|ctl_alu_oe~5_combout )) - - .dataa(\z80_|execute_|ctl_alu_oe~11_combout ), - .datab(\z80_|execute_|ctl_alu_oe~5_combout ), - .datac(\z80_|execute_|ctl_alu_core_S~11_combout ), - .datad(\z80_|execute_|ctl_alu_oe~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~12 .lut_mask = 16'hBFFF; -defparam \z80_|execute_|ctl_alu_oe~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~13 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~13_combout = (\z80_|execute_|ctl_alu_oe~12_combout ) # (((\z80_|execute_|ctl_66_oe~2_combout ) # (!\z80_|execute_|ctl_flags_alu~10_combout )) # (!\z80_|execute_|ctl_flags_xy_we~9_combout )) - - .dataa(\z80_|execute_|ctl_alu_oe~12_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~9_combout ), - .datac(\z80_|execute_|ctl_66_oe~2_combout ), - .datad(\z80_|execute_|ctl_flags_alu~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~13 .lut_mask = 16'hFBFF; -defparam \z80_|execute_|ctl_alu_oe~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~14_combout = (\z80_|execute_|ctl_alu_oe~13_combout ) # (!\z80_|execute_|ctl_alu_oe~9_combout ) - - .dataa(\z80_|execute_|ctl_alu_oe~9_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_oe~13_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~14 .lut_mask = 16'hF5F5; -defparam \z80_|execute_|ctl_alu_oe~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~24 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~24_combout = (\z80_|execute_|ctl_flags_xy_we~12_combout & (((!\z80_|pla_decode_|Equal48~0_combout & !\z80_|pla_decode_|Equal69~0_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|pla_decode_|Equal48~0_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~12_combout ), - .datad(\z80_|pla_decode_|Equal69~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~24 .lut_mask = 16'h3070; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~27 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~27_combout = (\z80_|pla_decode_|Equal20~0_combout & (!\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ixy_d~6_combout ) # (!\z80_|execute_|ctl_mRead~26_combout )))) # (!\z80_|pla_decode_|Equal20~0_combout & -// (((!\z80_|execute_|ixy_d~6_combout )) # (!\z80_|execute_|ctl_mRead~26_combout ))) - - .dataa(\z80_|pla_decode_|Equal20~0_combout ), - .datab(\z80_|execute_|ctl_mRead~26_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~27 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~40 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~40_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~24_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~27_combout & \z80_|execute_|nextM~11_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~27_combout ), - .datad(\z80_|execute_|nextM~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~40 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~53 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~53_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal21~1_combout ) # (!\z80_|sequencer_|DFFE_T4_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), - .datad(\z80_|pla_decode_|Equal21~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~53 .lut_mask = 16'hB0F0; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_hi~8_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & ((\z80_|execute_|ctl_ir_we~12_combout ) # (!\z80_|execute_|nextM~2_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~12_combout ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|execute_|nextM~2_combout ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_hi~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_hi~8 .lut_mask = 16'h8C00; -defparam \z80_|execute_|ctl_reg_out_hi~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|setM1~54 ( -// Equation(s): -// \z80_|execute_|setM1~54_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|execute_|ctl_ir_we~9_combout ), - .datac(\z80_|execute_|ctl_ir_we~10_combout ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~54_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~54 .lut_mask = 16'hABFF; -defparam \z80_|execute_|setM1~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~1 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~1_combout = ((!\z80_|execute_|ctl_ir_we~8_combout & (!\z80_|execute_|ctl_ir_we~11_combout & !\z80_|execute_|ctl_state_alu~7_combout ))) # (!\z80_|execute_|ctl_eval_cond~0_combout ) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_state_alu~7_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~1 .lut_mask = 16'h01FF; -defparam \z80_|execute_|ctl_sw_2u~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~4 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~4_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|execute_|ctl_mWrite~5_combout & ((!\z80_|execute_|ctl_alu_oe~3_combout )))) # (!\z80_|execute_|ctl_eval_cond~0_combout & (((!\z80_|execute_|ctl_ir_we~4_combout )) # -// (!\z80_|execute_|ctl_mWrite~5_combout ))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|ctl_mWrite~5_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|execute_|ctl_alu_oe~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~4 .lut_mask = 16'h1537; -defparam \z80_|execute_|ctl_sw_2u~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~5 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~5_combout = (\z80_|execute_|setM1~54_combout & (\z80_|execute_|ctl_sw_2u~1_combout & \z80_|execute_|ctl_sw_2u~4_combout )) - - .dataa(\z80_|execute_|setM1~54_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_sw_2u~1_combout ), - .datad(\z80_|execute_|ctl_sw_2u~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~5 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_sw_2u~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~6 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~6_combout = (\z80_|execute_|ctl_reg_gp_sel~36_combout & (\z80_|execute_|comb~0_combout $ ((!\z80_|ir_|opcode [0])))) # (!\z80_|execute_|ctl_reg_gp_sel~36_combout & (!\z80_|execute_|ctl_sw_2u~5_combout & -// (\z80_|execute_|comb~0_combout $ (!\z80_|ir_|opcode [0])))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel~36_combout ), - .datab(\z80_|execute_|comb~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|execute_|ctl_sw_2u~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~6 .lut_mask = 16'h82C3; -defparam \z80_|execute_|ctl_sw_2u~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~35 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~35_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ctl_state_alu~5_combout & ((!\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|pla_decode_|Equal47~0_combout & -// (((!\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|pla_decode_|Equal34~0_combout ), - .datad(\z80_|execute_|ctl_state_alu~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~35 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_inc_cy~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~35 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~35_combout = (\z80_|execute_|ctl_inc_cy~35_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|sequencer_|DFFE_M4_ff~q ) # (!\z80_|pla_decode_|Equal19~0_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|pla_decode_|Equal19~0_combout ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|execute_|ctl_inc_cy~35_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~35 .lut_mask = 16'hBF00; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~6 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~6_combout = (\z80_|pla_decode_|Equal55~0_combout & (!\z80_|ir_|opcode [3] & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~6 .lut_mask = 16'h0200; -defparam \z80_|execute_|ctl_mWrite~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~2 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~2_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|execute_|ctl_mWrite~6_combout & ((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|execute_|ctl_eval_cond~0_combout & -// (((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|ctl_mWrite~6_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|execute_|ctl_mRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~2 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_sw_2u~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~0 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~0_combout = (\z80_|pla_decode_|Equal9~1_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((!\z80_|execute_|ctl_mWrite~4_combout ) # (!\z80_|execute_|ctl_state_alu~5_combout )))) # (!\z80_|pla_decode_|Equal9~1_combout & -// (((!\z80_|execute_|ctl_mWrite~4_combout ) # (!\z80_|execute_|ctl_state_alu~5_combout )))) - - .dataa(\z80_|pla_decode_|Equal9~1_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_state_alu~5_combout ), - .datad(\z80_|execute_|ctl_mWrite~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~0 .lut_mask = 16'h0777; -defparam \z80_|execute_|ctl_sw_2u~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~3 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~3_combout = (\z80_|execute_|ctl_sw_2u~2_combout & (\z80_|execute_|ctl_sw_2u~0_combout & ((!\z80_|execute_|ctl_alu_oe~2_combout ) # (!\z80_|execute_|ctl_mRead~8_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~8_combout ), - .datab(\z80_|execute_|ctl_sw_2u~2_combout ), - .datac(\z80_|execute_|ctl_sw_2u~0_combout ), - .datad(\z80_|execute_|ctl_alu_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~3 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_sw_2u~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~52 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~52_combout = (\z80_|execute_|ctl_sw_2u~3_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|sequencer_|M5~q )) # (!\z80_|execute_|ctl_mRead~10_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|execute_|ctl_sw_2u~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~52 .lut_mask = 16'hDF00; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout = (\z80_|pla_decode_|Equal1~4_combout & (\z80_|ir_|opcode [0] & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~4_combout ), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~2_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|pla_decode_|Equal69~0_combout ) # (\z80_|execute_|ctl_alu_op_low~13_combout )))) - - .dataa(\z80_|pla_decode_|Equal69~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~13_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~2 .lut_mask = 16'hFEF0; -defparam \z80_|execute_|ctl_reg_out_lo~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N18 -cycloneive_lcell_comb \z80_|execute_|rsel3 ( -// Equation(s): -// \z80_|execute_|rsel3~combout = \z80_|ir_|opcode [3] $ (((\z80_|ir_|opcode [4] & \z80_|ir_|opcode [5]))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|ir_|opcode [3]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|rsel3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|rsel3 .lut_mask = 16'h7878; -defparam \z80_|execute_|rsel3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_hi~5_combout = (\z80_|execute_|ctl_mRead~5_combout & (!\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|rsel3~combout ) # (!\z80_|execute_|ctl_reg_out_lo~2_combout )))) # (!\z80_|execute_|ctl_mRead~5_combout & -// (((\z80_|execute_|rsel3~combout ) # (!\z80_|execute_|ctl_reg_out_lo~2_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~5_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|execute_|ctl_reg_out_lo~2_combout ), - .datad(\z80_|execute_|rsel3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_hi~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_hi~5 .lut_mask = 16'h7707; -defparam \z80_|execute_|ctl_reg_out_hi~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_hi~6_combout = (!\z80_|execute_|ctl_sw_2u~6_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout & \z80_|execute_|ctl_reg_out_hi~5_combout ))) - - .dataa(\z80_|execute_|ctl_sw_2u~6_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ), - .datad(\z80_|execute_|ctl_reg_out_hi~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_hi~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_hi~6 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_out_hi~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_hi~7_combout = ((\z80_|execute_|ctl_reg_out_hi~8_combout ) # ((!\z80_|execute_|ctl_reg_out_hi~6_combout ) # (!\z80_|execute_|ctl_reg_out_hi~4_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ), - .datab(\z80_|execute_|ctl_reg_out_hi~8_combout ), - .datac(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .datad(\z80_|execute_|ctl_reg_out_hi~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_hi~7 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_reg_out_hi~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N28 -cycloneive_lcell_comb \z80_|execute_|rsel0 ( -// Equation(s): -// \z80_|execute_|rsel0~combout = \z80_|ir_|opcode [0] $ (((\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1]))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(gnd), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|execute_|rsel0~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|rsel0 .lut_mask = 16'h5AAA; -defparam \z80_|execute_|rsel0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout = (\z80_|execute_|ixy_d~15_combout & \z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(gnd), - .datab(\z80_|execute_|ixy_d~15_combout ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 .lut_mask = 16'hC0C0; -defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~33 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~33_combout = (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout & (\z80_|execute_|ctl_reg_use_sp~0_combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_mRead~36_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), - .datab(\z80_|execute_|ctl_reg_use_sp~0_combout ), - .datac(\z80_|execute_|ctl_mRead~36_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~33 .lut_mask = 16'h0444; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~6_combout = (\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout & ((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~6 .lut_mask = 16'h0888; -defparam \z80_|execute_|ctl_reg_out_lo~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~7_combout = (\z80_|execute_|ctl_reg_out_lo~6_combout & (((!\z80_|execute_|ctl_reg_gp_sel~36_combout & \z80_|execute_|ctl_sw_2u~5_combout )) # (!\z80_|execute_|rsel0~combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel~36_combout ), - .datab(\z80_|execute_|rsel0~combout ), - .datac(\z80_|execute_|ctl_reg_out_lo~6_combout ), - .datad(\z80_|execute_|ctl_sw_2u~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~7 .lut_mask = 16'h7030; -defparam \z80_|execute_|ctl_reg_out_lo~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_iorw~11 ( -// Equation(s): -// \z80_|execute_|ctl_iorw~11_combout = (!\z80_|ir_|opcode [1] & (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [2] & \z80_|pla_decode_|Equal13~0_combout ))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|ir_|opcode [0]), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|pla_decode_|Equal13~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_iorw~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_iorw~11 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_iorw~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~10 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~10_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (((\z80_|execute_|rsel3~combout & \z80_|execute_|ctl_iorw~11_combout )) # (!\z80_|execute_|nextM~2_combout ))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|rsel3~combout ), - .datac(\z80_|execute_|nextM~2_combout ), - .datad(\z80_|execute_|ctl_iorw~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~10 .lut_mask = 16'h8A0A; -defparam \z80_|execute_|ctl_sw_2d~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~14 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~14_combout = (!\z80_|execute_|ctl_mRead~14_combout & (((\z80_|decode_state_|in_halt~q ) # (!\z80_|pla_decode_|Equal33~0_combout )) # (!\z80_|pla_decode_|Equal77~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal77~0_combout ), - .datab(\z80_|decode_state_|in_halt~q ), - .datac(\z80_|execute_|ctl_mRead~14_combout ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~14 .lut_mask = 16'h0D0F; -defparam \z80_|execute_|ctl_sw_2d~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~11 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~11_combout = (\z80_|execute_|ctl_sw_2d~10_combout ) # ((\z80_|nM1_int~2_combout & ((!\z80_|execute_|ctl_sw_1d~8_combout ) # (!\z80_|execute_|ctl_sw_2d~14_combout )))) - - .dataa(\z80_|execute_|ctl_sw_2d~10_combout ), - .datab(\z80_|execute_|ctl_sw_2d~14_combout ), - .datac(\z80_|execute_|ctl_sw_1d~8_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~11 .lut_mask = 16'hBFAA; -defparam \z80_|execute_|ctl_sw_2d~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~12 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~12_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|execute_|rsel3~combout & ((\z80_|execute_|ctl_alu_op_low~14_combout ) # (\z80_|execute_|ctl_alu_shift_oe~15_combout )))) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .datad(\z80_|execute_|rsel3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~12 .lut_mask = 16'hFEAA; -defparam \z80_|execute_|ctl_sw_2d~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~13 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2d~13_combout = ((\z80_|execute_|ctl_sw_2d~11_combout ) # ((\z80_|execute_|ctl_sw_2d~12_combout ) # (!\z80_|execute_|ctl_sw_2d~9_combout ))) # (!\z80_|execute_|ctl_reg_out_lo~7_combout ) - - .dataa(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .datab(\z80_|execute_|ctl_sw_2d~11_combout ), - .datac(\z80_|execute_|ctl_sw_2d~12_combout ), - .datad(\z80_|execute_|ctl_sw_2d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2d~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2d~13 .lut_mask = 16'hFDFF; -defparam \z80_|execute_|ctl_sw_2d~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_66_oe ( -// Equation(s): -// \z80_|execute_|ctl_66_oe~combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|sequencer_|DFFE_T3_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|pla_decode_|Equal47~0_combout ))) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_66_oe~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_66_oe .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_66_oe .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~34 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~34_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|pla_decode_|Equal47~0_combout & ((!\z80_|execute_|ctl_alu_oe~2_combout ) # (!\z80_|pla_decode_|Equal34~0_combout )))) # (!\z80_|execute_|ixy_d~7_combout & -// (((!\z80_|execute_|ctl_alu_oe~2_combout )) # (!\z80_|pla_decode_|Equal34~0_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|pla_decode_|Equal34~0_combout ), - .datac(\z80_|pla_decode_|Equal47~0_combout ), - .datad(\z80_|execute_|ctl_alu_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~34 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_inc_cy~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~0 ( -// Equation(s): -// \z80_|execute_|ctl_apin_mux~0_combout = (\z80_|execute_|ctl_inc_cy~34_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout & ((!\z80_|execute_|ctl_alu_oe~2_combout ) # (!\z80_|pla_decode_|Equal19~0_combout )))) - - .dataa(\z80_|execute_|ctl_inc_cy~34_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), - .datac(\z80_|pla_decode_|Equal19~0_combout ), - .datad(\z80_|execute_|ctl_alu_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_apin_mux~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_apin_mux~0 .lut_mask = 16'h0888; -defparam \z80_|execute_|ctl_apin_mux~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~5 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~5_combout = (\z80_|execute_|ctl_alu_op_low~14_combout ) # (((\z80_|execute_|ctl_alu_shift_oe~14_combout & \z80_|pla_decode_|Equal47~0_combout )) # (!\z80_|execute_|ctl_sw_4u~1_combout )) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datac(\z80_|execute_|ctl_sw_4u~1_combout ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~5 .lut_mask = 16'hEFCF; -defparam \z80_|execute_|ctl_sw_4u~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~75 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~75_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & (!\z80_|pla_decode_|Equal38~2_combout & ((!\z80_|pla_decode_|Equal37~0_combout )))) # (!\z80_|execute_|ctl_alu_op_low~8_combout & (((!\z80_|pla_decode_|Equal38~2_combout -// & !\z80_|pla_decode_|Equal37~0_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datab(\z80_|pla_decode_|Equal38~2_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|pla_decode_|Equal37~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~75_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~75 .lut_mask = 16'h0537; -defparam \z80_|execute_|ctl_inc_cy~75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~76 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~76_combout = (\z80_|execute_|ctl_inc_cy~75_combout & (((!\z80_|execute_|ctl_alu_op_low~8_combout & !\z80_|execute_|ixy_d~5_combout )) # (!\z80_|pla_decode_|Equal29~0_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~75_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|pla_decode_|Equal29~0_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~76_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~76 .lut_mask = 16'h0A2A; -defparam \z80_|execute_|ctl_inc_cy~76 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal4~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal4~0_combout = (\z80_|execute_|comb~1_combout & (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal1~7_combout & \z80_|pla_decode_|Equal1~4_combout ))) - - .dataa(\z80_|execute_|comb~1_combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|pla_decode_|Equal1~7_combout ), - .datad(\z80_|pla_decode_|Equal1~4_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal4~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal4~0 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y19_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~48 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~48_combout = (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|execute_|ctl_mWrite~4_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|execute_|ctl_mWrite~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~48 .lut_mask = 16'h1FFF; -defparam \z80_|execute_|ctl_bus_inc_oe~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~46 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~46_combout = (\z80_|execute_|ctl_bus_inc_oe~48_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T5_ff~q )) # (!\z80_|pla_decode_|Equal4~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal4~0_combout ), + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|execute_|ctl_bus_inc_oe~48_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal3~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_iy_set~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_iy_set~2 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_state_iy_set~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N18 +cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_16 ( +// Equation(s): +// \z80_|sequencer_|SYNTHESIZED_WIRE_16~combout = (\z80_|execute_|setM1~54_combout & (\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|execute_|nextM~14_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|setM1~54_combout ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_16 .lut_mask = 16'h00C0; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y13_N19 +dffeas \z80_|sequencer_|DFFE_T5_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_T5_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_T5_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_T5_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_state_ixiy_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_state_ixiy_we~2_combout = (\z80_|execute_|ixy_d~15_combout & ((\z80_|sequencer_|DFFE_T5_ff~q ) # ((!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T2_ff~q )))) # (!\z80_|execute_|ixy_d~15_combout & +// (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|execute_|ixy_d~15_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), .datad(\z80_|sequencer_|DFFE_T5_ff~q ), .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~46_combout ), + .combout(\z80_|execute_|ctl_state_ixiy_we~2_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~46 .lut_mask = 16'hD0F0; -defparam \z80_|execute_|ctl_bus_inc_oe~46 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_state_ixiy_we~2 .lut_mask = 16'hBA30; +defparam \z80_|execute_|ctl_state_ixiy_we~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y18_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~53 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~53_combout = (\z80_|execute_|ctl_mRead~16_combout & (!\z80_|execute_|ctl_alu_op_low~8_combout & ((!\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|execute_|ctl_mRead~16_combout & (((!\z80_|execute_|ctl_alu_op_low~8_combout & -// !\z80_|execute_|ixy_d~5_combout )) # (!\z80_|pla_decode_|Equal9~1_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~16_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~53_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~53 .lut_mask = 16'h0537; -defparam \z80_|execute_|ctl_inc_cy~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~92 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~92_combout = (((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|pla_decode_|Equal9~1_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|sequencer_|DFFE_M4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~92_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~92 .lut_mask = 16'h5F7F; -defparam \z80_|execute_|ctl_inc_cy~92 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal19~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal19~1_combout = (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal32~0_combout & \z80_|pla_decode_|Equal52~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|pla_decode_|Equal32~0_combout ), - .datad(\z80_|pla_decode_|Equal52~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal19~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal19~1 .lut_mask = 16'h2000; -defparam \z80_|pla_decode_|Equal19~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~0 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~0_combout = (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|M5~q ) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|sequencer_|M5~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~0 .lut_mask = 16'hAA00; -defparam \z80_|execute_|ctl_sw_4u~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~38 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~38_combout = (((!\z80_|execute_|ctl_alu_shift_oe~14_combout & !\z80_|execute_|ctl_sw_4u~0_combout )) # (!\z80_|pla_decode_|Equal3~1_combout )) # (!\z80_|pla_decode_|Equal19~1_combout ) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|pla_decode_|Equal19~1_combout ), - .datac(\z80_|execute_|ctl_sw_4u~0_combout ), - .datad(\z80_|pla_decode_|Equal3~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~38 .lut_mask = 16'h37FF; -defparam \z80_|execute_|ctl_inc_cy~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~93 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~93_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|pla_decode_|Equal34~0_combout ) - - .dataa(\z80_|pla_decode_|Equal34~0_combout ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~93_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~93 .lut_mask = 16'h57FF; -defparam \z80_|execute_|ctl_inc_cy~93 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~39 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~39_combout = (\z80_|execute_|ctl_inc_cy~93_combout & (((!\z80_|execute_|ctl_alu_op_low~8_combout & !\z80_|execute_|ixy_d~5_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|execute_|ctl_inc_cy~93_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~39 .lut_mask = 16'h444C; -defparam \z80_|execute_|ctl_inc_cy~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~24 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~24_combout = (\z80_|execute_|ctl_inc_cy~92_combout & (\z80_|execute_|ctl_inc_cy~38_combout & \z80_|execute_|ctl_inc_cy~39_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_inc_cy~92_combout ), - .datac(\z80_|execute_|ctl_inc_cy~38_combout ), - .datad(\z80_|execute_|ctl_inc_cy~39_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~24 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_bus_inc_oe~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~1 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~1_combout = (\z80_|execute_|ctl_inc_cy~76_combout & (\z80_|execute_|ctl_bus_inc_oe~46_combout & (\z80_|execute_|ctl_inc_cy~53_combout & \z80_|execute_|ctl_bus_inc_oe~24_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~76_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~46_combout ), - .datac(\z80_|execute_|ctl_inc_cy~53_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~1 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_we~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T5_ff~q & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal8~0_combout ))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T5_ff~q ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|pla_decode_|Equal8~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~44 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~44_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout & (((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|pla_decode_|Equal11~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal11~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~44 .lut_mask = 16'h1333; -defparam \z80_|execute_|ctl_bus_inc_oe~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~5_combout = ((!\z80_|pla_decode_|Equal10~0_combout & (!\z80_|pla_decode_|Equal11~0_combout & !\z80_|execute_|ctl_mRead~36_combout ))) # (!\z80_|execute_|ctl_alu_op_low~8_combout ) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|execute_|ctl_mRead~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~5 .lut_mask = 16'h3337; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~0_combout = (\z80_|execute_|ctl_bus_inc_oe~44_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~5_combout & ((!\z80_|execute_|ctl_mWrite~16_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_mWrite~16_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~0 .lut_mask = 16'h2A00; -defparam \z80_|execute_|ctl_reg_gp_we~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|sequencer_|M5~q & \z80_|pla_decode_|Equal9~1_combout )) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~35 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~35_combout = (\z80_|execute_|ctl_reg_gp_we~0_combout & (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout & ((!\z80_|pla_decode_|Equal10~0_combout ) # (!\z80_|execute_|ixy_d~9_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_we~0_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), - .datad(\z80_|pla_decode_|Equal10~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~35 .lut_mask = 16'h020A; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~2 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~2_combout = (\z80_|execute_|ixy_d~5_combout & (\z80_|execute_|nextM~2_combout & ((!\z80_|execute_|ixy_d~9_combout ) # (!\z80_|pla_decode_|Equal11~0_combout )))) # (!\z80_|execute_|ixy_d~5_combout & -// (((!\z80_|execute_|ixy_d~9_combout )) # (!\z80_|pla_decode_|Equal11~0_combout ))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|execute_|nextM~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~2 .lut_mask = 16'h3F15; -defparam \z80_|execute_|ctl_sw_4u~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~3 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~3_combout = (\z80_|execute_|ctl_reg_gp_we~1_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout & \z80_|execute_|ctl_sw_4u~2_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~1_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ), - .datad(\z80_|execute_|ctl_sw_4u~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~3 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_sw_4u~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N0 -cycloneive_lcell_comb \z80_|execute_|fMRead~3 ( -// Equation(s): -// \z80_|execute_|fMRead~3_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & (!\z80_|execute_|ctl_state_alu~14_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_mRead~15_combout )))) # -// (!\z80_|execute_|ctl_alu_op_low~8_combout & (((!\z80_|execute_|ctl_alu_shift_oe~14_combout )) # (!\z80_|execute_|ctl_mRead~15_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datab(\z80_|execute_|ctl_mRead~15_combout ), - .datac(\z80_|execute_|ctl_state_alu~14_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~3 .lut_mask = 16'h135F; -defparam \z80_|execute_|fMRead~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~4 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~4_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal55~0_combout & (!\z80_|ir_|opcode [5] & \z80_|execute_|ctl_alu_op_low~8_combout ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~4 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_sw_4u~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout = (\z80_|execute_|ctl_alu_shift_oe~14_combout & (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~15 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~15_combout = (!\z80_|execute_|ctl_sw_4u~4_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|ctl_ir_we~12_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~12_combout ), - .datab(\z80_|execute_|ctl_sw_4u~4_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~15 .lut_mask = 16'h0013; -defparam \z80_|execute_|ctl_reg_sel_wz~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~8_combout = (\z80_|execute_|ctl_mRead~10_combout & (!\z80_|execute_|ctl_alu_shift_oe~14_combout & ((!\z80_|execute_|ctl_sw_4u~0_combout )))) # (!\z80_|execute_|ctl_mRead~10_combout & -// (((!\z80_|execute_|ctl_alu_shift_oe~14_combout & !\z80_|execute_|ctl_sw_4u~0_combout )) # (!\z80_|execute_|ctl_mRead~8_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datac(\z80_|execute_|ctl_mRead~8_combout ), - .datad(\z80_|execute_|ctl_sw_4u~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~8 .lut_mask = 16'h0537; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~94 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~94_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|execute_|ctl_mRead~17_combout ) - - .dataa(\z80_|execute_|ctl_mRead~17_combout ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~94_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~94 .lut_mask = 16'h57FF; -defparam \z80_|execute_|ctl_inc_cy~94 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~87 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~87_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|pla_decode_|Equal13~2_combout ) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~87_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~87 .lut_mask = 16'h5FFF; -defparam \z80_|execute_|ctl_inc_cy~87 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~42 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~42_combout = (\z80_|pla_decode_|Equal12~1_combout ) # (((!\z80_|execute_|ctl_sw_4u~0_combout & !\z80_|execute_|ctl_alu_shift_oe~14_combout )) # (!\z80_|pla_decode_|Equal25~0_combout )) - - .dataa(\z80_|execute_|ctl_sw_4u~0_combout ), - .datab(\z80_|pla_decode_|Equal12~1_combout ), - .datac(\z80_|pla_decode_|Equal25~0_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~42 .lut_mask = 16'hCFDF; -defparam \z80_|execute_|ctl_inc_cy~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~34 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~34_combout = (\z80_|execute_|ctl_inc_cy~94_combout & (\z80_|execute_|ctl_inc_cy~87_combout & \z80_|execute_|ctl_inc_cy~42_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_inc_cy~94_combout ), - .datac(\z80_|execute_|ctl_inc_cy~87_combout ), - .datad(\z80_|execute_|ctl_inc_cy~42_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~34 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~16 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~16_combout = (\z80_|execute_|fMRead~3_combout & (\z80_|execute_|ctl_reg_sel_wz~15_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ))) - - .dataa(\z80_|execute_|fMRead~3_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~15_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~16 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sel_wz~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~6 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4u~6_combout = ((\z80_|execute_|ctl_sw_4u~5_combout ) # ((!\z80_|execute_|ctl_reg_sel_wz~16_combout ) # (!\z80_|execute_|ctl_sw_4u~3_combout ))) # (!\z80_|execute_|ctl_apin_mux~0_combout ) - - .dataa(\z80_|execute_|ctl_apin_mux~0_combout ), - .datab(\z80_|execute_|ctl_sw_4u~5_combout ), - .datac(\z80_|execute_|ctl_sw_4u~3_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4u~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4u~6 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_sw_4u~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N22 -cycloneive_lcell_comb \z80_|pla_decode_|Equal2~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal2~2_combout = (\z80_|pla_decode_|Equal1~7_combout & (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal32~0_combout & \z80_|pla_decode_|Equal2~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~7_combout ), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|pla_decode_|Equal32~0_combout ), - .datad(\z80_|pla_decode_|Equal2~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal2~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal2~2 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal2~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal1~6 ( -// Equation(s): -// \z80_|pla_decode_|Equal1~6_combout = (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal1~5_combout & (\z80_|pla_decode_|Equal1~7_combout & \z80_|pla_decode_|Equal1~4_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal1~5_combout ), - .datac(\z80_|pla_decode_|Equal1~7_combout ), - .datad(\z80_|pla_decode_|Equal1~4_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal1~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal1~6 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal1~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N22 -cycloneive_lcell_comb \z80_|reg_control_|bank_exx~2 ( -// Equation(s): -// \z80_|reg_control_|bank_exx~2_combout = \z80_|reg_control_|bank_exx~q $ (((!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal1~6_combout & \z80_|sequencer_|DFFE_T2_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|pla_decode_|Equal1~6_combout ), - .datac(\z80_|reg_control_|bank_exx~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|reg_control_|bank_exx~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|bank_exx~2 .lut_mask = 16'hB4F0; -defparam \z80_|reg_control_|bank_exx~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y13_N23 -dffeas \z80_|reg_control_|bank_exx ( +// Location: FF_X26_Y16_N7 +dffeas \z80_|decode_state_|DFFE_instIY1 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_control_|bank_exx~2_combout ), + .d(\z80_|execute_|ctl_state_iy_set~2_combout ), .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(vcc), + .ena(\z80_|execute_|ctl_state_ixiy_we~2_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|reg_control_|bank_exx~q ), + .q(\z80_|decode_state_|DFFE_instIY1~q ), .prn(vcc)); // synopsys translate_off -defparam \z80_|reg_control_|bank_exx .is_wysiwyg = "true"; -defparam \z80_|reg_control_|bank_exx .power_up = "low"; +defparam \z80_|decode_state_|DFFE_instIY1 .is_wysiwyg = "true"; +defparam \z80_|decode_state_|DFFE_instIY1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y15_N26 -cycloneive_lcell_comb \z80_|reg_control_|bank_hl_de1~0 ( +// Location: LCCOMB_X25_Y16_N10 +cycloneive_lcell_comb \z80_|decode_state_|use_ixiy ( // Equation(s): -// \z80_|reg_control_|bank_hl_de1~0_combout = \z80_|reg_control_|bank_hl_de1~q $ (((\z80_|pla_decode_|Equal2~2_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & !\z80_|reg_control_|bank_exx~q )))) - - .dataa(\z80_|pla_decode_|Equal2~2_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|reg_control_|bank_hl_de1~q ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_control_|bank_hl_de1~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|bank_hl_de1~0 .lut_mask = 16'hF0D2; -defparam \z80_|reg_control_|bank_hl_de1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y15_N27 -dffeas \z80_|reg_control_|bank_hl_de1 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_control_|bank_hl_de1~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_control_|bank_hl_de1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_control_|bank_hl_de1 .is_wysiwyg = "true"; -defparam \z80_|reg_control_|bank_hl_de1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~10 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~10_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|pla_decode_|Equal4~0_combout ) # ((\z80_|pla_decode_|Equal2~1_combout & \z80_|pla_decode_|Equal1~4_combout )))) - - .dataa(\z80_|pla_decode_|Equal4~0_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|pla_decode_|Equal2~1_combout ), - .datad(\z80_|pla_decode_|Equal1~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~10 .lut_mask = 16'hC888; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~11 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~11_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout ) # (\z80_|execute_|ctl_state_alu~4_combout )))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|nextM~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~11 .lut_mask = 16'h00FE; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~12 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~12_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ) # ((\z80_|execute_|ctl_state_alu~4_combout & \z80_|execute_|ctl_mRead~36_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|ctl_mRead~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~12 .lut_mask = 16'hFEEE; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~7 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~7_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|decode_state_|use_ixiy~combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~7 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_mRead~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~9_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mRead~5_combout ) # ((\z80_|execute_|ctl_mRead~7_combout ) # (\z80_|execute_|ctl_mWrite~16_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~5_combout ), - .datab(\z80_|execute_|ctl_mRead~7_combout ), - .datac(\z80_|execute_|ctl_mWrite~16_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~9 .lut_mask = 16'hFE00; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~37 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~37_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~5_combout & (((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|execute_|ctl_mWrite~16_combout ))) - - .dataa(\z80_|execute_|ctl_mWrite~16_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~37 .lut_mask = 16'h4CCC; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~13 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~13_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~12_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~9_combout ) # ((\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ) # (!\z80_|execute_|ctl_reg_gp_sel[1]~37_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~12_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~9_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~37_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~13 .lut_mask = 16'hFFEF; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~47 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~47_combout = (\z80_|decode_state_|DFFE_inst4~q ) # ((\z80_|decode_state_|DFFE_instIY1~q ) # ((!\z80_|pla_decode_|Equal50~0_combout & !\z80_|pla_decode_|Equal49~0_combout ))) - - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(\z80_|decode_state_|DFFE_instIY1~q ), - .datac(\z80_|pla_decode_|Equal50~0_combout ), - .datad(\z80_|pla_decode_|Equal49~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~47 .lut_mask = 16'hEEEF; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|fMWrite~3 ( -// Equation(s): -// \z80_|execute_|fMWrite~3_combout = (!\z80_|execute_|ctl_ir_we~15_combout & (!\z80_|execute_|ctl_ir_we~14_combout & (!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_mRead~6_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~15_combout ), - .datab(\z80_|execute_|ctl_ir_we~14_combout ), - .datac(\z80_|execute_|ctl_ir_we~7_combout ), - .datad(\z80_|execute_|ctl_mRead~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~3 .lut_mask = 16'h0001; -defparam \z80_|execute_|fMWrite~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~5_combout = (\z80_|ir_|opcode [2]) # ((\z80_|ir_|opcode [1]) # (!\z80_|execute_|ctl_mWrite~2_combout )) - - .dataa(\z80_|ir_|opcode [2]), - .datab(gnd), - .datac(\z80_|execute_|ctl_mWrite~2_combout ), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~5 .lut_mask = 16'hFFAF; -defparam \z80_|execute_|ctl_flags_bus~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N26 -cycloneive_lcell_comb \z80_|execute_|fMRead~2 ( -// Equation(s): -// \z80_|execute_|fMRead~2_combout = (!\z80_|pla_decode_|Equal13~2_combout & (!\z80_|execute_|ctl_state_alu~14_combout & \z80_|execute_|ctl_flags_bus~5_combout )) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(\z80_|execute_|ctl_state_alu~14_combout ), - .datac(\z80_|execute_|ctl_flags_bus~5_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|fMRead~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~2 .lut_mask = 16'h1010; -defparam \z80_|execute_|fMRead~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~19 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~19_combout = (\z80_|execute_|fMWrite~3_combout & (\z80_|execute_|fMRead~2_combout & !\z80_|execute_|ctl_ir_we~12_combout )) +// \z80_|decode_state_|use_ixiy~combout = (\z80_|decode_state_|DFFE_inst4~q ) # (\z80_|decode_state_|DFFE_instIY1~q ) .dataa(gnd), - .datab(\z80_|execute_|fMWrite~3_combout ), - .datac(\z80_|execute_|fMRead~2_combout ), - .datad(\z80_|execute_|ctl_ir_we~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~19 .lut_mask = 16'h00C0; -defparam \z80_|execute_|ctl_mRead~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~7_combout = (\z80_|execute_|ctl_state_alu~5_combout & (((\z80_|execute_|ctl_mRead~36_combout ) # (!\z80_|execute_|ctl_mRead~19_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), - .datab(\z80_|execute_|ctl_state_alu~5_combout ), - .datac(\z80_|execute_|ctl_mRead~36_combout ), - .datad(\z80_|execute_|ctl_mRead~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~7 .lut_mask = 16'hC4CC; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~8_combout = (\z80_|ir_|opcode [2] & ((!\z80_|execute_|ctl_sw_2u~5_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), - .datab(gnd), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|execute_|ctl_sw_2u~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~8 .lut_mask = 16'h50F0; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~14 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~14_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~13_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~7_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~8_combout ) # (!\z80_|execute_|ctl_alu_op_low~15_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~13_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~7_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~15_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~14 .lut_mask = 16'hFFEF; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~16 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~16_combout = (\z80_|ir_|opcode [3] & (((\z80_|sequencer_|DFFE_T3_ff~q )))) # (!\z80_|ir_|opcode [3] & (((\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|pla_decode_|Equal12~0_combout )) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal12~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~16 .lut_mask = 16'hC5CD; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~15 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~15_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|ir_|opcode [3] & (\z80_|ir_|opcode [7] & \z80_|ir_|opcode [6]))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|ir_|opcode [6]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~15 .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~17 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~17_combout = (\z80_|ir_|opcode [0] & (((\z80_|execute_|ctl_reg_gp_sel[1]~15_combout )))) # (!\z80_|ir_|opcode [0] & (\z80_|execute_|ctl_reg_gp_sel[1]~16_combout & ((\z80_|execute_|ctl_ir_we~6_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~16_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|execute_|ctl_ir_we~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~17 .lut_mask = 16'hCAC0; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~19 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~19_combout = (!\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2])) - - .dataa(\z80_|ir_|opcode [4]), - .datab(gnd), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~19 .lut_mask = 16'h0050; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~2_combout = (((!\z80_|execute_|ctl_mRead~11_combout & !\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal8~0_combout )) # (!\z80_|pla_decode_|Equal6~0_combout ) - - .dataa(\z80_|execute_|ctl_mRead~11_combout ), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal8~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~2 .lut_mask = 16'h37FF; -defparam \z80_|execute_|ctl_reg_use_sp~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~47 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~47_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q ))) # (!\z80_|execute_|ctl_mRead~8_combout ) - - .dataa(\z80_|sequencer_|M5~q ), - .datab(\z80_|execute_|ctl_mRead~8_combout ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~47 .lut_mask = 16'hFF37; -defparam \z80_|execute_|ctl_bus_inc_oe~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~3_combout = (\z80_|execute_|ctl_reg_use_sp~2_combout & (\z80_|execute_|ctl_reg_use_sp~0_combout & (\z80_|execute_|ctl_bus_inc_oe~47_combout & \z80_|execute_|nextM~11_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~2_combout ), - .datab(\z80_|execute_|ctl_reg_use_sp~0_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~47_combout ), - .datad(\z80_|execute_|nextM~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~3 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_use_sp~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~9 ( -// Equation(s): -// \z80_|execute_|ctl_sw_1d~9_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal6~1_combout & !\z80_|sequencer_|DFFE_M1_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal6~1_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_1d~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_1d~9 .lut_mask = 16'h0050; -defparam \z80_|execute_|ctl_sw_1d~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~21 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~21_combout = (!\z80_|execute_|ctl_sw_1d~9_combout & (((!\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ctl_state_alu~5_combout )) # (!\z80_|execute_|ctl_mWrite~4_combout ))) - - .dataa(\z80_|execute_|ctl_mWrite~4_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|execute_|ctl_state_alu~5_combout ), - .datad(\z80_|execute_|ctl_sw_1d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~21 .lut_mask = 16'h0057; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~20 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~20_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout & ((\z80_|pla_decode_|Equal33~1_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~15_combout & -// !\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~20 .lut_mask = 16'hAB00; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~20 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~20_combout = (!\z80_|execute_|ctl_alu_oe~3_combout & (!\z80_|execute_|ctl_mRead~14_combout & !\z80_|pla_decode_|Equal49~0_combout )) - - .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), - .datab(\z80_|execute_|ctl_mRead~14_combout ), - .datac(\z80_|pla_decode_|Equal49~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~20 .lut_mask = 16'h0101; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~49 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~49_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((\z80_|execute_|ctl_reg_gp_sel[0]~20_combout ) # (\z80_|sequencer_|DFFE_M1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~20_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~49 .lut_mask = 16'hCCC8; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~22 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~22_combout = (\z80_|execute_|ctl_reg_use_sp~3_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~21_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~6_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~3_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[0]~21_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~22 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~18 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~18_combout = (!\z80_|decode_state_|DFFE_instED~q & (!\z80_|decode_state_|DFFE_instCB~q & ((\z80_|sequencer_|M5~q ) # (\z80_|sequencer_|DFFE_M4_ff~q )))) - - .dataa(\z80_|sequencer_|M5~q ), - .datab(\z80_|decode_state_|DFFE_instED~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|decode_state_|DFFE_instCB~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~18 .lut_mask = 16'h0032; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~23 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~23_combout = ((\z80_|execute_|ctl_reg_gp_sel[1]~17_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~19_combout & \z80_|execute_|ctl_reg_gp_sel[1]~18_combout ))) # (!\z80_|execute_|ctl_reg_gp_sel[0]~22_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~17_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~22_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~23 .lut_mask = 16'h8F0F; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~28 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~28_combout = (\z80_|execute_|ctl_sw_2u~2_combout & !\z80_|execute_|ctl_reg_gp_sel~36_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_sw_2u~2_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_gp_sel~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~28 .lut_mask = 16'h00CC; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~23 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~23_combout = (\z80_|execute_|ctl_sw_1d~4_combout & (((!\z80_|pla_decode_|Equal69~0_combout & \z80_|execute_|ctl_sw_1d~8_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_sw_1d~4_combout ), - .datab(\z80_|pla_decode_|Equal69~0_combout ), - .datac(\z80_|execute_|ctl_sw_1d~8_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~23 .lut_mask = 16'h20AA; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_sel_shift~2_combout = (!\z80_|execute_|ctl_ir_we~8_combout & !\z80_|pla_decode_|Equal20~0_combout ) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal20~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~2 .lut_mask = 16'h0505; -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~14 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_cpl~14_combout = (\z80_|ir_|opcode [4]) # (!\z80_|pla_decode_|Equal63~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|pla_decode_|Equal63~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_cpl~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_cpl~14 .lut_mask = 16'hF0FF; -defparam \z80_|execute_|ctl_flags_hf_cpl~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_cpl~10_combout = (!\z80_|pla_decode_|Equal68~2_combout & (!\z80_|execute_|ctl_state_alu~7_combout & (\z80_|execute_|ctl_flags_hf_cpl~14_combout & !\z80_|execute_|ctl_alu_op_low~13_combout ))) - - .dataa(\z80_|pla_decode_|Equal68~2_combout ), - .datab(\z80_|execute_|ctl_state_alu~7_combout ), - .datac(\z80_|execute_|ctl_flags_hf_cpl~14_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_cpl~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_cpl~10 .lut_mask = 16'h0010; -defparam \z80_|execute_|ctl_flags_hf_cpl~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N22 -cycloneive_lcell_comb \z80_|execute_|setM1~47 ( -// Equation(s): -// \z80_|execute_|setM1~47_combout = (!\z80_|execute_|ctl_ir_we~11_combout & (!\z80_|pla_decode_|Equal69~0_combout & ((!\z80_|pla_decode_|Equal21~0_combout ) # (!\z80_|pla_decode_|Equal63~0_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~11_combout ), - .datab(\z80_|pla_decode_|Equal63~0_combout ), - .datac(\z80_|pla_decode_|Equal21~0_combout ), - .datad(\z80_|pla_decode_|Equal69~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~47 .lut_mask = 16'h0015; -defparam \z80_|execute_|setM1~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|setM1~48 ( -// Equation(s): -// \z80_|execute_|setM1~48_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout & (\z80_|execute_|ctl_flags_hf_cpl~10_combout & (\z80_|execute_|setM1~47_combout & \z80_|execute_|nextM~2_combout ))) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), - .datab(\z80_|execute_|ctl_flags_hf_cpl~10_combout ), - .datac(\z80_|execute_|setM1~47_combout ), - .datad(\z80_|execute_|nextM~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~48 .lut_mask = 16'h8000; -defparam \z80_|execute_|setM1~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~13 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~13_combout = (\z80_|ir_|opcode [2]) # ((!\z80_|ir_|opcode [1]) # (!\z80_|execute_|ctl_mWrite~2_combout )) - - .dataa(\z80_|ir_|opcode [2]), - .datab(gnd), - .datac(\z80_|execute_|ctl_mWrite~2_combout ), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~13 .lut_mask = 16'hAFFF; -defparam \z80_|execute_|ctl_al_we~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_flags_oe~0_combout = (!\z80_|execute_|ctl_ir_we~14_combout & (!\z80_|execute_|ctl_mRead~6_combout & (!\z80_|execute_|ctl_ir_we~12_combout & !\z80_|execute_|ctl_iorw~10_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~14_combout ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|execute_|ctl_iorw~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_oe~0 .lut_mask = 16'h0001; -defparam \z80_|execute_|ctl_flags_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~1 ( -// Equation(s): -// \z80_|execute_|ctl_flags_oe~1_combout = (\z80_|execute_|ctl_al_we~13_combout & (\z80_|execute_|ctl_flags_bus~5_combout & (!\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_flags_oe~0_combout ))) - - .dataa(\z80_|execute_|ctl_al_we~13_combout ), - .datab(\z80_|execute_|ctl_flags_bus~5_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|ctl_flags_oe~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_oe~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_oe~1 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_flags_oe~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~13 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~13_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & ((!\z80_|execute_|ctl_flags_oe~1_combout ) # (!\z80_|execute_|setM1~48_combout )))) - - .dataa(\z80_|execute_|setM1~48_combout ), - .datab(\z80_|execute_|ctl_flags_oe~1_combout ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~13 .lut_mask = 16'h0070; -defparam \z80_|execute_|ctl_reg_in_hi~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~29 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~29_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~28_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~27_combout & !\z80_|execute_|ctl_reg_in_hi~13_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~28_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~27_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~29 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~40 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~40_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ctl_state_alu~4_combout & ((!\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ctl_state_alu~6_combout )))) # (!\z80_|pla_decode_|Equal47~0_combout & -// (((!\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|execute_|ctl_state_alu~6_combout ), - .datac(\z80_|pla_decode_|Equal34~0_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~40 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_inc_cy~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~2 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~2_combout = (\z80_|execute_|ctl_inc_cy~40_combout & (((!\z80_|pla_decode_|Equal19~0_combout & !\z80_|pla_decode_|Equal9~1_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~40_combout ), - .datab(\z80_|pla_decode_|Equal19~0_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~2 .lut_mask = 16'h0A2A; -defparam \z80_|execute_|ctl_inc_dec~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~12 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~12_combout = (\z80_|execute_|ctl_inc_dec~2_combout & (((!\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|pla_decode_|Equal9~1_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|execute_|ctl_inc_dec~2_combout ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~12 .lut_mask = 16'h4CCC; -defparam \z80_|execute_|ctl_inc_dec~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~43 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~43_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ctl_mRead~11_combout & ((!\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ixy_d~9_combout )))) # (!\z80_|pla_decode_|Equal47~0_combout & -// (((!\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|execute_|ixy_d~9_combout ))) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|pla_decode_|Equal34~0_combout ), - .datad(\z80_|execute_|ctl_mRead~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~43 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_inc_cy~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~5 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~5_combout = (\z80_|execute_|ctl_inc_dec~12_combout & (\z80_|execute_|ctl_inc_cy~43_combout & ((!\z80_|execute_|ixy_d~9_combout ) # (!\z80_|pla_decode_|Equal19~0_combout )))) - - .dataa(\z80_|execute_|ctl_inc_dec~12_combout ), - .datab(\z80_|pla_decode_|Equal19~0_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|execute_|ctl_inc_cy~43_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~5 .lut_mask = 16'h2A00; -defparam \z80_|execute_|ctl_inc_dec~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~4_combout = (\z80_|execute_|ctl_inc_dec~5_combout & (((!\z80_|execute_|ctl_mRead~11_combout & !\z80_|execute_|ctl_state_alu~4_combout )) # (!\z80_|execute_|ctl_mWrite~4_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~11_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_inc_dec~5_combout ), - .datad(\z80_|execute_|ctl_mWrite~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~4 .lut_mask = 16'h10F0; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|fMRead~6 ( -// Equation(s): -// \z80_|execute_|fMRead~6_combout = (\z80_|pla_decode_|Equal29~0_combout & (!\z80_|execute_|ctl_state_alu~5_combout & (!\z80_|execute_|ixy_d~7_combout ))) # (!\z80_|pla_decode_|Equal29~0_combout & (((!\z80_|execute_|ctl_state_alu~5_combout & -// !\z80_|execute_|ixy_d~7_combout )) # (!\z80_|pla_decode_|Equal9~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal29~0_combout ), - .datab(\z80_|execute_|ctl_state_alu~5_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~6 .lut_mask = 16'h0357; -defparam \z80_|execute_|fMRead~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|fMRead~7 ( -// Equation(s): -// \z80_|execute_|fMRead~7_combout = (\z80_|execute_|ctl_state_alu~5_combout & (((!\z80_|pla_decode_|Equal37~0_combout & !\z80_|execute_|ctl_mRead~16_combout )))) # (!\z80_|execute_|ctl_state_alu~5_combout & (((!\z80_|pla_decode_|Equal37~0_combout & -// !\z80_|execute_|ctl_mRead~16_combout )) # (!\z80_|execute_|ixy_d~7_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~5_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|pla_decode_|Equal37~0_combout ), - .datad(\z80_|execute_|ctl_mRead~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~7 .lut_mask = 16'h111F; -defparam \z80_|execute_|fMRead~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N26 -cycloneive_lcell_comb \z80_|execute_|fMRead~8 ( -// Equation(s): -// \z80_|execute_|fMRead~8_combout = (\z80_|execute_|fMRead~7_combout & (((!\z80_|execute_|ctl_state_alu~5_combout & !\z80_|execute_|ixy_d~7_combout )) # (!\z80_|pla_decode_|Equal38~2_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~5_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|execute_|fMRead~7_combout ), - .datad(\z80_|pla_decode_|Equal38~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~8 .lut_mask = 16'h10F0; -defparam \z80_|execute_|fMRead~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~26 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~26_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~4_combout & (\z80_|execute_|ctl_reg_gp_we~1_combout & (\z80_|execute_|fMRead~6_combout & \z80_|execute_|fMRead~8_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~1_combout ), - .datac(\z80_|execute_|fMRead~6_combout ), - .datad(\z80_|execute_|fMRead~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~26 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~13 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~13_combout = (\z80_|execute_|ctl_state_alu~8_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|pla_decode_|Equal52~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal52~1_combout ), - .datab(\z80_|execute_|ctl_state_alu~8_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~13 .lut_mask = 16'hC4CC; -defparam \z80_|execute_|ctl_state_alu~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~10 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~10_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~10 .lut_mask = 16'h3331; -defparam \z80_|execute_|ctl_state_alu~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~11 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~11_combout = (\z80_|execute_|ctl_state_alu~5_combout & ((\z80_|pla_decode_|Equal52~1_combout ) # ((\z80_|execute_|ctl_state_alu~10_combout & \z80_|execute_|ctl_state_alu~7_combout )))) # -// (!\z80_|execute_|ctl_state_alu~5_combout & (((\z80_|execute_|ctl_state_alu~10_combout & \z80_|execute_|ctl_state_alu~7_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~5_combout ), - .datab(\z80_|pla_decode_|Equal52~1_combout ), - .datac(\z80_|execute_|ctl_state_alu~10_combout ), - .datad(\z80_|execute_|ctl_state_alu~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~11 .lut_mask = 16'hF888; -defparam \z80_|execute_|ctl_state_alu~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~9 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~9_combout = (\z80_|execute_|ctl_state_alu~14_combout & (((\z80_|nM1_int~2_combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) # (!\z80_|execute_|ctl_state_alu~14_combout & (\z80_|pla_decode_|Equal52~1_combout & -// ((\z80_|nM1_int~2_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~14_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal52~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~9 .lut_mask = 16'hF3A2; -defparam \z80_|execute_|ctl_state_alu~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N14 -cycloneive_lcell_comb \z80_|pla_decode_|Equal62~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal62~2_combout = (\z80_|ir_|opcode [5] & (((\z80_|execute_|ctl_state_alu~11_combout ) # (\z80_|execute_|ctl_state_alu~9_combout )) # (!\z80_|execute_|ctl_state_alu~13_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~13_combout ), - .datab(\z80_|execute_|ctl_state_alu~11_combout ), - .datac(\z80_|execute_|ctl_state_alu~9_combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal62~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal62~2 .lut_mask = 16'hFD00; -defparam \z80_|pla_decode_|Equal62~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~4_combout = (((\z80_|ir_|opcode [3] & \z80_|ir_|opcode [4])) # (!\z80_|nM1_int~2_combout )) # (!\z80_|pla_decode_|Equal62~2_combout ) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|pla_decode_|Equal62~2_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~4 .lut_mask = 16'h8FFF; -defparam \z80_|execute_|ctl_flags_pf_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~21 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~21_combout = ((!\z80_|execute_|ctl_mRead~4_combout & ((!\z80_|pla_decode_|Equal63~0_combout ) # (!\z80_|pla_decode_|Equal32~0_combout )))) # (!\z80_|nM1_int~2_combout ) - - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_mRead~4_combout ), - .datad(\z80_|pla_decode_|Equal63~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~21 .lut_mask = 16'h373F; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal64~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal64~0_combout = (!\z80_|ir_|opcode [5] & (((\z80_|execute_|ctl_state_alu~11_combout ) # (\z80_|execute_|ctl_state_alu~9_combout )) # (!\z80_|execute_|ctl_state_alu~13_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~13_combout ), - .datab(\z80_|execute_|ctl_state_alu~11_combout ), - .datac(\z80_|execute_|ctl_state_alu~9_combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal64~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal64~0 .lut_mask = 16'h00FD; -defparam \z80_|pla_decode_|Equal64~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel[0]~3 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel[0]~3_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # ((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|pla_decode_|Equal64~0_combout )) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal64~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel[0]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel[0]~3 .lut_mask = 16'hEEFF; -defparam \z80_|execute_|ctl_pf_sel[0]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~22 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~22_combout = (\z80_|execute_|ctl_flags_pf_we~4_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout & (\z80_|execute_|ctl_alu_oe~7_combout & \z80_|execute_|ctl_pf_sel[0]~3_combout ))) - - .dataa(\z80_|execute_|ctl_flags_pf_we~4_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~21_combout ), - .datac(\z80_|execute_|ctl_alu_oe~7_combout ), - .datad(\z80_|execute_|ctl_pf_sel[0]~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~22 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~15 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~15_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|execute_|ctl_state_alu~14_combout & !\z80_|pla_decode_|Equal52~1_combout ))) # (!\z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(\z80_|execute_|ctl_state_alu~14_combout ), - .datab(\z80_|pla_decode_|Equal52~1_combout ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~15 .lut_mask = 16'hFF1F; -defparam \z80_|execute_|ctl_state_alu~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout = (\z80_|ir_|opcode [4] & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal63~0_combout ))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal63~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~25 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~25_combout = (\z80_|execute_|ctl_state_alu~15_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~24_combout & !\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout )) - - .dataa(\z80_|execute_|ctl_state_alu~15_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~25 .lut_mask = 16'h00A0; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~30 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~30_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~29_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~26_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout & \z80_|execute_|ctl_reg_gp_sel[0]~25_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~29_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~30 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~31 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[1]~31_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~14_combout ) # (((\z80_|execute_|ctl_reg_gp_sel[1]~23_combout & \z80_|ir_|opcode [5])) # (!\z80_|execute_|ctl_reg_gp_sel[0]~30_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~14_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[1]~31 .lut_mask = 16'hEFAF; -defparam \z80_|execute_|ctl_reg_gp_sel[1]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~33 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~33_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|pla_decode_|Equal11~0_combout ) # ((\z80_|execute_|ctl_mRead~5_combout )))) # (!\z80_|execute_|ixy_d~7_combout & (\z80_|pla_decode_|Equal11~0_combout & -// ((\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ctl_mRead~5_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~33 .lut_mask = 16'hECA8; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~34 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~34_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ) # ((\z80_|ir_|opcode [1] & ((!\z80_|execute_|ctl_sw_2u~5_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), - .datab(\z80_|execute_|ctl_sw_2u~5_combout ), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~34 .lut_mask = 16'hFF70; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo~20 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo~20_combout = ((\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal55~0_combout )) # (!\z80_|pla_decode_|Equal6~0_combout ) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo~20 .lut_mask = 16'hF7F7; -defparam \z80_|execute_|ctl_reg_sys_hilo~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~32 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~32_combout = (\z80_|ir_|opcode [4] & (((\z80_|execute_|ctl_state_alu~5_combout & !\z80_|execute_|ctl_reg_sys_hilo~20_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~22_combout ))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|execute_|ctl_reg_gp_sel[0]~22_combout ), - .datac(\z80_|execute_|ctl_state_alu~5_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~32 .lut_mask = 16'h22A2; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~35 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel[0]~35_combout = ((\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ) # (\z80_|execute_|ctl_reg_gp_sel[0]~32_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel[0]~35 .lut_mask = 16'hFFF3; -defparam \z80_|execute_|ctl_reg_gp_sel[0]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N18 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~5 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_de2~5_combout = (!\z80_|decode_state_|DFFE_instIY1~q & (!\z80_|decode_state_|DFFE_inst4~q & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|decode_state_|DFFE_instIY1~q ), .datab(\z80_|decode_state_|DFFE_inst4~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_de2~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_de2~5 .lut_mask = 16'h0010; -defparam \z80_|reg_control_|reg_sel_de2~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N24 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~6 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_de2~6_combout = (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & ((\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[0]~30_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_de2~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_de2~6 .lut_mask = 16'h0F0B; -defparam \z80_|reg_control_|reg_sel_de2~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N0 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_hl~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_hl~0_combout = (!\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de1~q & ((\z80_|reg_control_|reg_sel_de2~6_combout ))) # (!\z80_|reg_control_|bank_hl_de1~q & (\z80_|reg_control_|reg_sel_de2~5_combout )))) - - .dataa(\z80_|reg_control_|bank_hl_de1~q ), - .datab(\z80_|reg_control_|reg_sel_de2~5_combout ), - .datac(\z80_|reg_control_|reg_sel_de2~6_combout ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_hl~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_hl~0 .lut_mask = 16'h00E4; -defparam \z80_|reg_control_|reg_sel_hl~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N14 -cycloneive_lcell_comb \z80_|reg_control_|bank_hl_de2~0 ( -// Equation(s): -// \z80_|reg_control_|bank_hl_de2~0_combout = \z80_|reg_control_|bank_hl_de2~q $ (((\z80_|pla_decode_|Equal2~2_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|reg_control_|bank_exx~q )))) - - .dataa(\z80_|pla_decode_|Equal2~2_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|reg_control_|bank_hl_de2~q ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_control_|bank_hl_de2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|bank_hl_de2~0 .lut_mask = 16'hD2F0; -defparam \z80_|reg_control_|bank_hl_de2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y15_N15 -dffeas \z80_|reg_control_|bank_hl_de2 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_control_|bank_hl_de2~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_control_|bank_hl_de2~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_control_|bank_hl_de2 .is_wysiwyg = "true"; -defparam \z80_|reg_control_|bank_hl_de2 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N30 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_hl2~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_hl2~0_combout = (\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de2~q & (\z80_|reg_control_|reg_sel_de2~6_combout )) # (!\z80_|reg_control_|bank_hl_de2~q & ((\z80_|reg_control_|reg_sel_de2~5_combout ))))) - - .dataa(\z80_|reg_control_|reg_sel_de2~6_combout ), - .datab(\z80_|reg_control_|reg_sel_de2~5_combout ), - .datac(\z80_|reg_control_|bank_hl_de2~q ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_hl2~0 .lut_mask = 16'hAC00; -defparam \z80_|reg_control_|reg_sel_hl2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~7_combout = (\z80_|nM1_int~2_combout & (((\z80_|pla_decode_|Equal69~0_combout ) # (!\z80_|execute_|ctl_sw_1d~8_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~20_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~20_combout ), - .datab(\z80_|pla_decode_|Equal69~0_combout ), - .datac(\z80_|execute_|ctl_sw_1d~8_combout ), - .datad(\z80_|nM1_int~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~7 .lut_mask = 16'hDF00; -defparam \z80_|execute_|ctl_reg_in_hi~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~4_combout = (!\z80_|execute_|ctl_reg_in_hi~7_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout & \z80_|execute_|ctl_state_alu~15_combout )) - - .dataa(\z80_|execute_|ctl_reg_in_hi~7_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), .datac(gnd), - .datad(\z80_|execute_|ctl_state_alu~15_combout ), + .datad(\z80_|decode_state_|DFFE_instIY1~q ), .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~4_combout ), + .combout(\z80_|decode_state_|use_ixiy~combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~4 .lut_mask = 16'h1100; -defparam \z80_|execute_|ctl_reg_gp_we~4 .sum_lutc_input = "datac"; +defparam \z80_|decode_state_|use_ixiy .lut_mask = 16'hFFCC; +defparam \z80_|decode_state_|use_ixiy .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 ( +// Location: LCCOMB_X28_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ixy_d~4 ( // Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M4_ff~q & (\z80_|pla_decode_|Equal25~0_combout & !\z80_|pla_decode_|Equal12~1_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|pla_decode_|Equal25~0_combout ), - .datad(\z80_|pla_decode_|Equal12~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~3_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~6_combout & (!\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout & ((!\z80_|execute_|ctl_iorw~10_combout ) # (!\z80_|nM1_int~2_combout )))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), - .datac(\z80_|execute_|ctl_iorw~10_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~3 .lut_mask = 16'h004C; -defparam \z80_|execute_|ctl_reg_gp_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~13 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~13_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout & ((!\z80_|pla_decode_|Equal21~1_combout ) # (!\z80_|execute_|ctl_mRead~11_combout -// )))) - - .dataa(\z80_|execute_|ctl_mRead~11_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5~combout ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~13 .lut_mask = 16'h0013; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5~combout = (\z80_|execute_|ctl_reg_in_hi~2_combout & (\z80_|pla_decode_|Equal25~0_combout & ((\z80_|ir_|opcode [3]) # (!\z80_|pla_decode_|Equal12~0_combout )))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datab(\z80_|pla_decode_|Equal12~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal25~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5 .lut_mask = 16'hA200; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~2_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~13_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5~combout & !\z80_|execute_|ctl_sw_1d~9_combout ))) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~22_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5~combout ), - .datad(\z80_|execute_|ctl_sw_1d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~2 .lut_mask = 16'h0008; -defparam \z80_|execute_|ctl_reg_gp_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~5_combout = (!\z80_|execute_|ctl_reg_in_hi~13_combout & (\z80_|execute_|ctl_reg_gp_we~4_combout & (\z80_|execute_|ctl_reg_gp_we~3_combout & \z80_|execute_|ctl_reg_gp_we~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~13_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~4_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~3_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~5 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_gp_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_we~6_combout = (((\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout )) # (!\z80_|execute_|ctl_sw_4u~3_combout )) # (!\z80_|execute_|ctl_reg_gp_we~5_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_we~5_combout ), - .datab(\z80_|execute_|ctl_sw_4u~3_combout ), - .datac(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_we~6 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|ctl_reg_gp_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~14 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~14_combout = (!\z80_|execute_|ctl_mRead~7_combout & (((\z80_|ir_|opcode [2]) # (!\z80_|execute_|ctl_mWrite~2_combout )) # (!\z80_|ir_|opcode [1]))) - - .dataa(\z80_|ir_|opcode [1]), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|execute_|ctl_mRead~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~14 .lut_mask = 16'h00F7; -defparam \z80_|execute_|ctl_al_we~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~50 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~50_combout = (!\z80_|execute_|ctl_flags_oe~1_combout & (((!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|execute_|ctl_flags_oe~1_combout ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~50 .lut_mask = 16'h1033; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~26 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~26_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ) # ((\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mWrite~4_combout ) # (!\z80_|execute_|ctl_al_we~14_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~4_combout ), - .datab(\z80_|execute_|ctl_al_we~14_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~50_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~26 .lut_mask = 16'hFBF0; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~27 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~27_combout = (\z80_|execute_|rsel3~combout & (((!\z80_|execute_|ctl_reg_gp_sel[0]~20_combout & \z80_|nM1_int~2_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~20_combout ), - .datab(\z80_|execute_|rsel3~combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~27 .lut_mask = 16'h40CC; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~28 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~28_combout = (((\z80_|execute_|ctl_ir_we~7_combout ) # (\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo~20_combout ) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), - .datac(\z80_|execute_|ctl_ir_we~7_combout ), - .datad(\z80_|execute_|ctl_ir_we~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~28 .lut_mask = 16'hFFF7; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~29 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~29_combout = (\z80_|execute_|ctl_state_alu~5_combout & ((\z80_|execute_|ctl_iorw~11_combout ) # ((\z80_|execute_|ctl_state_alu~14_combout ) # (\z80_|execute_|ctl_reg_gp_hilo[0]~28_combout )))) - - .dataa(\z80_|execute_|ctl_iorw~11_combout ), - .datab(\z80_|execute_|ctl_state_alu~5_combout ), - .datac(\z80_|execute_|ctl_state_alu~14_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~29 .lut_mask = 16'hCCC8; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal9~1_combout & \z80_|sequencer_|M5~q )) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|pla_decode_|Equal9~1_combout ), - .datac(gnd), - .datad(\z80_|sequencer_|M5~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 .lut_mask = 16'h4400; -defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~31 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~31_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout & (((!\z80_|execute_|ctl_mRead~8_combout & !\z80_|execute_|ctl_mRead~10_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~8_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), - .datad(\z80_|execute_|ctl_mRead~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~31 .lut_mask = 16'h0307; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~51 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~51_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # ((\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T2_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|execute_|nextM~2_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~51 .lut_mask = 16'h0F08; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~30 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~30_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ) # (((\z80_|pla_decode_|Equal6~1_combout & \z80_|execute_|ixy_d~7_combout )) # (!\z80_|execute_|ctl_mRead~25_combout )) - - .dataa(\z80_|pla_decode_|Equal6~1_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~51_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_mRead~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~30 .lut_mask = 16'hECFF; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~32 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~32_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ) # ((\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ) # -// (!\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~32 .lut_mask = 16'hFFEF; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~34 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~34_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ) # (((\z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ) # (\z80_|execute_|ctl_reg_gp_hilo[0]~32_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~33_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~34 .lut_mask = 16'hFFFB; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~24 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout = ((\z80_|execute_|ctl_reg_gp_sel~36_combout ) # (!\z80_|execute_|ctl_sw_2u~5_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_sel~36_combout ), - .datad(\z80_|execute_|ctl_sw_2u~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~24 .lut_mask = 16'hF5FF; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~25 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~25_combout = (\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|execute_|rsel0~combout & ((\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout )))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & -// (((\z80_|execute_|rsel0~combout & \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout )) # (!\z80_|execute_|setM1~48_combout ))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|execute_|rsel0~combout ), - .datac(\z80_|execute_|setM1~48_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~25 .lut_mask = 16'hCD05; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~36 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~36_combout = (\z80_|pla_decode_|Equal11~0_combout & (!\z80_|execute_|ixy_d~6_combout & (!\z80_|execute_|ixy_d~9_combout ))) # (!\z80_|pla_decode_|Equal11~0_combout & (((!\z80_|pla_decode_|Equal10~0_combout )) # -// (!\z80_|execute_|ixy_d~6_combout ))) - - .dataa(\z80_|pla_decode_|Equal11~0_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|pla_decode_|Equal10~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~36 .lut_mask = 16'h1357; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout = (!\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal2~1_combout & (\z80_|execute_|ctl_eval_cond~0_combout & !\z80_|ir_|opcode [1]))) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|pla_decode_|Equal2~1_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 .lut_mask = 16'h0040; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N4 -cycloneive_lcell_comb \z80_|execute_|setM1~40 ( -// Equation(s): -// \z80_|execute_|setM1~40_combout = (!\z80_|pla_decode_|Equal4~0_combout & ((!\z80_|pla_decode_|Equal8~0_combout ) # (!\z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal4~0_combout ), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal8~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~40 .lut_mask = 16'h1155; -defparam \z80_|execute_|setM1~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~18 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout & (!\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout & ((\z80_|execute_|setM1~40_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|setM1~40_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~18 .lut_mask = 16'h1101; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~37 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~37_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout & \z80_|execute_|ctl_reg_gp_sel[1]~26_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~35_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~37 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y14_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~38 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ) # ((!\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~34_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~38 .lut_mask = 16'hEFFF; -defparam \z80_|execute_|ctl_reg_gp_hilo[0]~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~93 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~93_combout = (!\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & ((\z80_|reg_control_|reg_sel_hl~0_combout ) # (\z80_|reg_control_|reg_sel_hl2~0_combout )))) - - .dataa(\z80_|reg_control_|reg_sel_hl~0_combout ), - .datab(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~93_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~93 .lut_mask = 16'h0E00; -defparam \z80_|reg_file_|gdfx_temp0[0]~93 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N28 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_de~0_combout = (!\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de1~q & (\z80_|reg_control_|reg_sel_de2~5_combout )) # (!\z80_|reg_control_|bank_hl_de1~q & ((\z80_|reg_control_|reg_sel_de2~6_combout ))))) - - .dataa(\z80_|reg_control_|bank_hl_de1~q ), - .datab(\z80_|reg_control_|reg_sel_de2~5_combout ), - .datac(\z80_|reg_control_|reg_sel_de2~6_combout ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_de~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_de~0 .lut_mask = 16'h00D8; -defparam \z80_|reg_control_|reg_sel_de~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N0 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_50 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_50~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_de~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_de~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_50 .lut_mask = 16'h0C00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N0 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout = (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 .lut_mask = 16'h0F00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N18 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout = (\z80_|decode_state_|DFFE_inst4~q & (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 .lut_mask = 16'h0080; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N30 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|reg_control_|bank_exx~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 .lut_mask = 16'h0400; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N12 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|reg_control_|bank_exx~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 .lut_mask = 16'h0100; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~9_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|execute_|ctl_mRead~4_combout )))) # (!\z80_|pla_decode_|Equal47~0_combout -// & (((!\z80_|execute_|ixy_d~7_combout )) # (!\z80_|execute_|ctl_mRead~4_combout ))) - - .dataa(\z80_|pla_decode_|Equal47~0_combout ), - .datab(\z80_|execute_|ctl_mRead~4_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~9 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_reg_in_hi~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~10 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~10_combout = (\z80_|execute_|ctl_reg_in_hi~9_combout & (\z80_|execute_|ctl_reg_in_hi~8_combout & \z80_|execute_|ctl_reg_gp_we~5_combout )) - - .dataa(\z80_|execute_|ctl_reg_in_hi~9_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~8_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_gp_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~10 .lut_mask = 16'h8800; -defparam \z80_|execute_|ctl_reg_in_hi~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~19 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~19_combout = (\z80_|execute_|ctl_mRead~22_combout & (\z80_|reg_control_|reg_sys_we_lo~6_combout & ((!\z80_|execute_|ixy_d~15_combout ) # (!\z80_|sequencer_|DFFE_T3_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|execute_|ctl_mRead~22_combout ), - .datac(\z80_|reg_control_|reg_sys_we_lo~6_combout ), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~19 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_reg_sel_wz~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout = (\z80_|pla_decode_|Equal24~0_combout & (\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|ir_|opcode [3] & \z80_|ir_|opcode [4]))) - - .dataa(\z80_|pla_decode_|Equal24~0_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_lo~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_lo~8_combout = (((\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ) # (!\z80_|execute_|ctl_reg_sel_wz~19_combout )) # (!\z80_|execute_|ctl_reg_in_hi~10_combout )) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ) - - .dataa(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~10_combout ), - .datac(\z80_|execute_|ctl_reg_sel_wz~19_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_lo~8 .lut_mask = 16'hFF7F; -defparam \z80_|execute_|ctl_reg_in_lo~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y12_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~19 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~19_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ) # ((\z80_|execute_|ctl_sw_4u~6_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ) # (\z80_|execute_|ctl_reg_in_lo~8_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|execute_|ctl_sw_4u~6_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .datad(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~19 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp0[0]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~4_combout = (\z80_|pla_decode_|Equal6~1_combout & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_M1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|pla_decode_|Equal6~1_combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~4 .lut_mask = 16'h00B0; -defparam \z80_|execute_|ctl_reg_use_sp~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~5_combout = (\z80_|execute_|ctl_reg_use_sp~4_combout ) # ((\z80_|execute_|ctl_mRead~17_combout & ((\z80_|execute_|ctl_reg_in_hi~2_combout ) # (\z80_|execute_|ctl_state_alu~6_combout )))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datab(\z80_|execute_|ctl_reg_use_sp~4_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_mRead~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~5 .lut_mask = 16'hFECC; -defparam \z80_|execute_|ctl_reg_use_sp~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_use_sp~6_combout = (\z80_|execute_|ctl_reg_use_sp~5_combout ) # ((!\z80_|execute_|ctl_reg_use_sp~3_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[1]~26_combout )) - - .dataa(\z80_|execute_|ctl_reg_use_sp~5_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), - .datad(\z80_|execute_|ctl_reg_use_sp~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_use_sp~6 .lut_mask = 16'hAFFF; -defparam \z80_|execute_|ctl_reg_use_sp~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N2 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout = (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal21~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal21~2_combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal40~0_combout & !\z80_|ir_|opcode [5])) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|pla_decode_|Equal40~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal21~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal21~2 .lut_mask = 16'h0808; -defparam \z80_|pla_decode_|Equal21~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N20 -cycloneive_lcell_comb \z80_|reg_control_|bank_af~0 ( -// Equation(s): -// \z80_|reg_control_|bank_af~0_combout = \z80_|reg_control_|bank_af~q $ (((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|pla_decode_|Equal21~2_combout & \z80_|pla_decode_|Equal32~0_combout )))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|pla_decode_|Equal21~2_combout ), - .datac(\z80_|reg_control_|bank_af~q ), - .datad(\z80_|pla_decode_|Equal32~0_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|bank_af~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|bank_af~0 .lut_mask = 16'hB4F0; -defparam \z80_|reg_control_|bank_af~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y12_N21 -dffeas \z80_|reg_control_|bank_af ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_control_|bank_af~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_control_|bank_af~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_control_|bank_af .is_wysiwyg = "true"; -defparam \z80_|reg_control_|bank_af .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N28 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_af~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_af~0_combout = (!\z80_|execute_|ctl_reg_use_sp~6_combout & (!\z80_|reg_control_|bank_af~q & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datab(\z80_|reg_control_|bank_af~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_af~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_af~0 .lut_mask = 16'h1000; -defparam \z80_|reg_control_|reg_sel_af~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N4 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_34 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_34~combout = (\z80_|reg_control_|reg_sel_af~0_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & !\z80_|execute_|ctl_reg_gp_we~6_combout )) - - .dataa(\z80_|reg_control_|reg_sel_af~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_34 .lut_mask = 16'h0088; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N10 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_af2~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_af2~0_combout = (!\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|reg_control_|bank_af~q & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datab(\z80_|reg_control_|bank_af~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_af2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_af2~0 .lut_mask = 16'h4000; -defparam \z80_|reg_control_|reg_sel_af2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N18 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_30 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_30~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_af2~0_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datac(gnd), - .datad(\z80_|reg_control_|reg_sel_af2~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_30 .lut_mask = 16'h2200; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~12 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~12_combout = (\z80_|execute_|ixy_d~6_combout & (!\z80_|pla_decode_|Equal19~0_combout & ((!\z80_|pla_decode_|Equal9~1_combout )))) # (!\z80_|execute_|ixy_d~6_combout & (((!\z80_|pla_decode_|Equal9~1_combout ) # -// (!\z80_|execute_|ctl_reg_in_hi~2_combout )))) - - .dataa(\z80_|pla_decode_|Equal19~0_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~12 .lut_mask = 16'h035F; -defparam \z80_|execute_|ctl_reg_sel_wz~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~4_combout = (\z80_|ir_|opcode [5]) # ((!\z80_|pla_decode_|Equal13~1_combout ) # (!\z80_|pla_decode_|Equal13~0_combout )) - - .dataa(\z80_|ir_|opcode [5]), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|pla_decode_|Equal13~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~4 .lut_mask = 16'hAFFF; -defparam \z80_|execute_|ctl_flags_bus~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~6_combout = (\z80_|pla_decode_|Equal44~0_combout ) # ((\z80_|pla_decode_|Equal52~0_combout & \z80_|pla_decode_|Equal33~0_combout )) - - .dataa(\z80_|pla_decode_|Equal52~0_combout ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|pla_decode_|Equal44~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~6 .lut_mask = 16'hF8F8; -defparam \z80_|execute_|ctl_flags_bus~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~7_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (((\z80_|execute_|ctl_flags_bus~6_combout ) # (!\z80_|execute_|ctl_flags_bus~5_combout )) # (!\z80_|execute_|ctl_flags_bus~4_combout ))) - - .dataa(\z80_|execute_|ctl_flags_bus~4_combout ), - .datab(\z80_|execute_|ctl_flags_bus~5_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_flags_bus~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~7 .lut_mask = 16'hF070; -defparam \z80_|execute_|ctl_flags_bus~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N22 -cycloneive_lcell_comb \z80_|execute_|fMRead~24 ( -// Equation(s): -// \z80_|execute_|fMRead~24_combout = (\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_state_alu~4_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_state_alu~14_combout )))) # -// (!\z80_|execute_|ctl_ir_we~12_combout & (((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_state_alu~14_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~12_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_state_alu~14_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~24 .lut_mask = 16'h0777; -defparam \z80_|execute_|fMRead~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~13 ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~13_combout = (\z80_|execute_|ctl_alu_shift_oe~20_combout & (\z80_|execute_|ctl_bus_db_oe~3_combout & \z80_|execute_|ctl_flags_bus~12_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_shift_oe~20_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~3_combout ), - .datad(\z80_|execute_|ctl_flags_bus~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus~13 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_flags_bus~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus ( -// Equation(s): -// \z80_|execute_|ctl_flags_bus~combout = (\z80_|execute_|ctl_flags_bus~7_combout ) # (((\z80_|execute_|ctl_flags_hf2_we~combout ) # (!\z80_|execute_|ctl_flags_bus~13_combout )) # (!\z80_|execute_|fMRead~24_combout )) - - .dataa(\z80_|execute_|ctl_flags_bus~7_combout ), - .datab(\z80_|execute_|fMRead~24_combout ), - .datac(\z80_|execute_|ctl_flags_hf2_we~combout ), - .datad(\z80_|execute_|ctl_flags_bus~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_bus~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_bus .lut_mask = 16'hFBFF; -defparam \z80_|execute_|ctl_flags_bus .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~3 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~3_combout = ((!\z80_|pla_decode_|Equal11~0_combout & ((!\z80_|execute_|ctl_mWrite~2_combout ) # (!\z80_|pla_decode_|Equal55~0_combout )))) # (!\z80_|execute_|ctl_mWrite~7_combout ) - - .dataa(\z80_|pla_decode_|Equal11~0_combout ), - .datab(\z80_|execute_|ctl_mWrite~7_combout ), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|execute_|ctl_mWrite~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~3 .lut_mask = 16'h3777; -defparam \z80_|execute_|ctl_inc_dec~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~14 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~14_combout = (\z80_|execute_|ctl_inc_dec~3_combout & (!\z80_|nM1_int~2_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout & \z80_|execute_|fMRead~3_combout ))) - - .dataa(\z80_|execute_|ctl_inc_dec~3_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), - .datad(\z80_|execute_|fMRead~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~14 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~2_combout = ((!\z80_|execute_|ctl_mRead~15_combout & ((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout )))) # (!\z80_|execute_|ixy_d~5_combout ) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|ctl_mRead~15_combout ), - .datac(\z80_|pla_decode_|Equal25~0_combout ), - .datad(\z80_|pla_decode_|Equal12~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~2 .lut_mask = 16'h7757; -defparam \z80_|execute_|ctl_reg_sel_pc~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~3_combout = (\z80_|execute_|ctl_reg_sel_pc~2_combout & (((!\z80_|execute_|ctl_mRead~10_combout & !\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~2_combout ), - .datac(\z80_|pla_decode_|Equal19~0_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~3 .lut_mask = 16'h04CC; -defparam \z80_|execute_|ctl_reg_sel_pc~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~6_combout = (\z80_|pla_decode_|Equal34~0_combout & (!\z80_|execute_|ixy_d~5_combout & ((!\z80_|execute_|ctl_alu_op_low~8_combout ) # (!\z80_|execute_|ixy_d~16_combout )))) # (!\z80_|pla_decode_|Equal34~0_combout & -// (((!\z80_|execute_|ctl_alu_op_low~8_combout )) # (!\z80_|execute_|ixy_d~16_combout ))) - - .dataa(\z80_|pla_decode_|Equal34~0_combout ), - .datab(\z80_|execute_|ixy_d~16_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~6 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_reg_sel_pc~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~5_combout = ((!\z80_|execute_|ctl_mRead~8_combout & (!\z80_|execute_|ctl_mRead~17_combout & !\z80_|execute_|ctl_mRead~9_combout ))) # (!\z80_|execute_|ixy_d~5_combout ) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|ctl_mRead~8_combout ), - .datac(\z80_|execute_|ctl_mRead~17_combout ), - .datad(\z80_|execute_|ctl_mRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~5 .lut_mask = 16'h5557; -defparam \z80_|execute_|ctl_reg_sel_pc~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~4_combout = ((!\z80_|execute_|ixy_d~10_combout & ((!\z80_|pla_decode_|Equal21~0_combout ) # (!\z80_|pla_decode_|Equal24~0_combout )))) # (!\z80_|execute_|ctl_alu_op_low~8_combout ) - - .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datab(\z80_|pla_decode_|Equal24~0_combout ), - .datac(\z80_|pla_decode_|Equal21~0_combout ), - .datad(\z80_|execute_|ixy_d~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~4 .lut_mask = 16'h557F; -defparam \z80_|execute_|ctl_reg_sel_pc~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~7_combout = (\z80_|execute_|ctl_reg_sel_pc~3_combout & (\z80_|execute_|ctl_reg_sel_pc~6_combout & (\z80_|execute_|ctl_reg_sel_pc~5_combout & \z80_|execute_|ctl_reg_sel_pc~4_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~3_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~6_combout ), - .datac(\z80_|execute_|ctl_reg_sel_pc~5_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~7 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sel_pc~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~8_combout = (\z80_|pla_decode_|Equal3~0_combout & ((\z80_|pla_decode_|Equal24~0_combout ) # ((\z80_|pla_decode_|Equal25~0_combout & !\z80_|pla_decode_|Equal12~1_combout )))) # (!\z80_|pla_decode_|Equal3~0_combout & -// (((\z80_|pla_decode_|Equal25~0_combout & !\z80_|pla_decode_|Equal12~1_combout )))) - - .dataa(\z80_|pla_decode_|Equal3~0_combout ), - .datab(\z80_|pla_decode_|Equal24~0_combout ), - .datac(\z80_|pla_decode_|Equal25~0_combout ), - .datad(\z80_|pla_decode_|Equal12~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~8 .lut_mask = 16'h88F8; -defparam \z80_|execute_|ctl_reg_sel_pc~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~9_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & ((\z80_|pla_decode_|Equal34~0_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~8_combout ) # (\z80_|execute_|ctl_mRead~17_combout )))) - - .dataa(\z80_|pla_decode_|Equal34~0_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~8_combout ), - .datac(\z80_|execute_|ctl_mRead~17_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~9 .lut_mask = 16'hFE00; -defparam \z80_|execute_|ctl_reg_sel_pc~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~10 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~10_combout = (\z80_|execute_|ctl_reg_sel_pc~7_combout & (!\z80_|execute_|ctl_reg_sel_pc~9_combout & ((!\z80_|pla_decode_|Equal41~2_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~7_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~9_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|pla_decode_|Equal41~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~10 .lut_mask = 16'h0222; -defparam \z80_|execute_|ctl_reg_sel_pc~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~13 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~13_combout = (\z80_|execute_|ctl_reg_sel_pc~10_combout & (\z80_|execute_|ctl_inc_cy~94_combout & (\z80_|execute_|ctl_inc_cy~87_combout & \z80_|execute_|ctl_inc_cy~42_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~10_combout ), - .datab(\z80_|execute_|ctl_inc_cy~94_combout ), - .datac(\z80_|execute_|ctl_inc_cy~87_combout ), - .datad(\z80_|execute_|ctl_inc_cy~42_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~13 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~15 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~15_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout & -// !\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~15 .lut_mask = 16'h0020; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~29 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~29_combout = (!\z80_|execute_|ctl_mRead~14_combout & ((\z80_|ir_|opcode [5]) # ((\z80_|ir_|opcode [3]) # (!\z80_|pla_decode_|Equal12~0_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~14_combout ), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal12~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~29 .lut_mask = 16'h5455; -defparam \z80_|execute_|ctl_bus_inc_oe~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~13 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~13_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|ir_|opcode [3] & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~13 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_mRead~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N8 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~49 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~49_combout = (!\z80_|pla_decode_|Equal35~0_combout & (((\z80_|ir_|opcode [3]) # (\z80_|ir_|opcode [4])) # (!\z80_|pla_decode_|Equal24~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal24~0_combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|pla_decode_|Equal35~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~49 .lut_mask = 16'h00FD; -defparam \z80_|execute_|pc_inc_hold~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~9_combout = (!\z80_|execute_|ctl_mRead~10_combout & (!\z80_|execute_|ctl_mRead~15_combout & (!\z80_|pla_decode_|Equal41~2_combout & !\z80_|execute_|ctl_mRead~8_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|execute_|ctl_mRead~15_combout ), - .datac(\z80_|pla_decode_|Equal41~2_combout ), - .datad(\z80_|execute_|ctl_mRead~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~9 .lut_mask = 16'h0001; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~10 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~10_combout = (\z80_|execute_|pc_inc_hold~49_combout & (!\z80_|pla_decode_|Equal19~0_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~9_combout )) - - .dataa(\z80_|execute_|pc_inc_hold~49_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal19~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~10 .lut_mask = 16'h0A00; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~28 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~28_combout = (!\z80_|pla_decode_|Equal33~2_combout & (((!\z80_|pla_decode_|Equal49~0_combout & !\z80_|pla_decode_|Equal50~0_combout )) # (!\z80_|decode_state_|use_ixiy~combout ))) - - .dataa(\z80_|pla_decode_|Equal33~2_combout ), - .datab(\z80_|pla_decode_|Equal49~0_combout ), - .datac(\z80_|decode_state_|use_ixiy~combout ), - .datad(\z80_|pla_decode_|Equal50~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~28 .lut_mask = 16'h0515; -defparam \z80_|execute_|pc_inc_hold~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|setM1~35 ( -// Equation(s): -// \z80_|execute_|setM1~35_combout = (!\z80_|pla_decode_|Equal6~1_combout & (!\z80_|pla_decode_|Equal39~0_combout & !\z80_|pla_decode_|Equal40~1_combout )) - - .dataa(gnd), - .datab(\z80_|pla_decode_|Equal6~1_combout ), - .datac(\z80_|pla_decode_|Equal39~0_combout ), - .datad(\z80_|pla_decode_|Equal40~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~35 .lut_mask = 16'h0003; -defparam \z80_|execute_|setM1~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N16 -cycloneive_lcell_comb \z80_|execute_|setM1~36 ( -// Equation(s): -// \z80_|execute_|setM1~36_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout & (!\z80_|execute_|ctl_mRead~9_combout & (\z80_|execute_|pc_inc_hold~28_combout & \z80_|execute_|setM1~35_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), - .datab(\z80_|execute_|ctl_mRead~9_combout ), - .datac(\z80_|execute_|pc_inc_hold~28_combout ), - .datad(\z80_|execute_|setM1~35_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~36 .lut_mask = 16'h2000; -defparam \z80_|execute_|setM1~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y18_N2 -cycloneive_lcell_comb \z80_|execute_|fMRead~5 ( -// Equation(s): -// \z80_|execute_|fMRead~5_combout = (!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|execute_|ctl_mRead~13_combout & (!\z80_|pla_decode_|Equal52~1_combout & \z80_|execute_|setM1~36_combout ))) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|execute_|ctl_mRead~13_combout ), - .datac(\z80_|pla_decode_|Equal52~1_combout ), - .datad(\z80_|execute_|setM1~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~5 .lut_mask = 16'h0100; -defparam \z80_|execute_|fMRead~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y18_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~31 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~31_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout & (((\z80_|execute_|ctl_bus_inc_oe~29_combout & \z80_|execute_|fMRead~5_combout )) # (!\z80_|execute_|ctl_alu_op_low~8_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~29_combout ), - .datad(\z80_|execute_|fMRead~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~31 .lut_mask = 16'hA222; -defparam \z80_|execute_|ctl_bus_inc_oe~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N20 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~29 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~29_combout = (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T4_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~29 .lut_mask = 16'hC8C8; -defparam \z80_|execute_|pc_inc_hold~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~1 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we~1_combout = (\z80_|execute_|pc_inc_hold~29_combout & ((\z80_|pla_decode_|Equal10~0_combout ) # (\z80_|execute_|ctl_mRead~36_combout ))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|execute_|ctl_mRead~36_combout ), - .datac(gnd), - .datad(\z80_|execute_|pc_inc_hold~29_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we~1 .lut_mask = 16'hEE00; -defparam \z80_|execute_|ctl_reg_sys_we~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we~2_combout = (!\z80_|execute_|ctl_reg_sys_we~1_combout & (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|execute_|ctl_mWrite~16_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|execute_|ctl_reg_sys_we~1_combout ), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|execute_|ctl_mWrite~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we~2 .lut_mask = 16'h1113; -defparam \z80_|execute_|ctl_reg_sys_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N14 -cycloneive_lcell_comb \z80_|pla_decode_|Equal33~3 ( -// Equation(s): -// \z80_|pla_decode_|Equal33~3_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal33~0_combout & (\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|decode_state_|use_ixiy~combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal33~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal33~3 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal33~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we~0_combout = (\z80_|execute_|ixy_d~5_combout & ((\z80_|pla_decode_|Equal33~3_combout ) # ((\z80_|pla_decode_|Equal6~1_combout ) # (!\z80_|execute_|pc_inc_hold~49_combout )))) - - .dataa(\z80_|pla_decode_|Equal33~3_combout ), - .datab(\z80_|execute_|pc_inc_hold~49_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|pla_decode_|Equal6~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we~0 .lut_mask = 16'hF0B0; -defparam \z80_|execute_|ctl_reg_sys_we~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we~3_combout = (((\z80_|execute_|ctl_reg_sys_we~0_combout ) # (\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout )) # (!\z80_|execute_|ctl_reg_sys_we~2_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~31_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~31_combout ), - .datab(\z80_|execute_|ctl_reg_sys_we~2_combout ), - .datac(\z80_|execute_|ctl_reg_sys_we~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we~3 .lut_mask = 16'hFFF7; -defparam \z80_|execute_|ctl_reg_sys_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we_lo~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we_lo~2_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal55~0_combout & \z80_|pla_decode_|Equal6~0_combout )) - - .dataa(\z80_|ir_|opcode [5]), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we_lo~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we_lo~2 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_reg_sys_we_lo~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we_lo~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we_lo~3_combout = (\z80_|execute_|ctl_reg_sys_we_lo~2_combout ) # ((\z80_|pla_decode_|Equal9~1_combout ) # ((\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal8~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|pla_decode_|Equal8~0_combout ), - .datac(\z80_|execute_|ctl_reg_sys_we_lo~2_combout ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we_lo~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we_lo~3 .lut_mask = 16'hFFF8; -defparam \z80_|execute_|ctl_reg_sys_we_lo~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we_lo~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_we_lo~4_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|execute_|ctl_reg_sys_we_lo~3_combout & \z80_|sequencer_|DFFE_M2_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|execute_|ctl_reg_sys_we_lo~3_combout ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_we_lo~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_we_lo~4 .lut_mask = 16'h8080; -defparam \z80_|execute_|ctl_reg_sys_we_lo~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N20 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~combout = (\z80_|execute_|ctl_reg_sys_we~3_combout ) # ((\z80_|execute_|ctl_reg_sys_we_lo~4_combout ) # ((!\z80_|reg_control_|reg_sys_we_lo~7_combout ) # (!\z80_|reg_control_|reg_sys_we_lo~4_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_we~3_combout ), - .datab(\z80_|execute_|ctl_reg_sys_we_lo~4_combout ), - .datac(\z80_|reg_control_|reg_sys_we_lo~4_combout ), - .datad(\z80_|reg_control_|reg_sys_we_lo~7_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo .lut_mask = 16'hEFFF; -defparam \z80_|reg_control_|reg_sys_we_lo .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_ir~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_ir~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T3_ff~q ))) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_ir~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_ir~0 .lut_mask = 16'h3330; -defparam \z80_|execute_|ctl_reg_sel_ir~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_ir~1 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_ir~1_combout = ((\z80_|execute_|ctl_reg_sel_ir~0_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & !\z80_|execute_|ctl_flags_bus~4_combout ))) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ) - - .dataa(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_flags_bus~4_combout ), - .datad(\z80_|execute_|ctl_reg_sel_ir~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_ir~1 .lut_mask = 16'hFF5D; -defparam \z80_|execute_|ctl_reg_sel_ir~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~9_combout = (\z80_|execute_|ctl_inc_cy~34_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|sequencer_|M5~q ) # (!\z80_|pla_decode_|Equal19~0_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|execute_|ctl_inc_cy~34_combout ), - .datac(\z80_|pla_decode_|Equal19~0_combout ), - .datad(\z80_|sequencer_|M5~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~9 .lut_mask = 16'h8CCC; -defparam \z80_|execute_|ctl_reg_out_lo~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~36 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~36_combout = (\z80_|execute_|ctl_alu_op_low~14_combout ) # ((\z80_|sequencer_|DFFE_T4_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|pla_decode_|Equal48~0_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|pla_decode_|Equal48~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~36 .lut_mask = 16'hF2F0; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~12 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[0]~12_combout = (((\z80_|ir_|opcode [3] & \z80_|execute_|ctl_reg_sys_hilo[1]~36_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout )) # (!\z80_|execute_|ctl_reg_out_lo~9_combout ) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|execute_|ctl_reg_out_lo~9_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~12 .lut_mask = 16'hBF3F; -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout = (\z80_|sequencer_|DFFE_T5_ff~q & \z80_|execute_|ixy_d~15_combout ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T5_ff~q ), - .datac(gnd), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 .lut_mask = 16'hCC00; -defparam \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~4_combout = (\z80_|reg_control_|reg_sel_pc~2_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~4_combout & (\z80_|execute_|ctl_alu_oe~4_combout & !\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ))) - - .dataa(\z80_|reg_control_|reg_sel_pc~2_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), - .datac(\z80_|execute_|ctl_alu_oe~4_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~4 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_in_hi~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~4_combout = ((!\z80_|pla_decode_|Equal34~0_combout & ((!\z80_|pla_decode_|Equal3~1_combout ) # (!\z80_|pla_decode_|Equal19~1_combout )))) # (!\z80_|execute_|ctl_reg_in_hi~2_combout ) - - .dataa(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datab(\z80_|pla_decode_|Equal34~0_combout ), - .datac(\z80_|pla_decode_|Equal19~1_combout ), - .datad(\z80_|pla_decode_|Equal3~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~4 .lut_mask = 16'h5777; -defparam \z80_|execute_|ctl_reg_sel_wz~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|execute_|comb~0_combout & \z80_|execute_|ixy_d~6_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|pla_decode_|Equal52~0_combout ), - .datac(\z80_|execute_|comb~0_combout ), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~5_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & (((!\z80_|execute_|ctl_mRead~10_combout & !\z80_|execute_|ctl_mRead~8_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|execute_|ctl_mRead~8_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~5 .lut_mask = 16'h001F; -defparam \z80_|execute_|ctl_reg_sel_wz~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~6 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~6_combout = (\z80_|execute_|ctl_reg_sel_wz~4_combout & \z80_|execute_|ctl_reg_sel_wz~5_combout ) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~4_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|execute_|ctl_reg_sel_wz~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~6 .lut_mask = 16'hAA00; -defparam \z80_|execute_|ctl_reg_sel_wz~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~7 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~7_combout = (\z80_|execute_|ctl_bus_db_oe~0_combout & (\z80_|execute_|ctl_reg_in_hi~4_combout & (\z80_|execute_|ctl_reg_in_hi~3_combout & \z80_|execute_|ctl_reg_sel_wz~6_combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_oe~0_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~4_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~3_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~7 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sel_wz~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo~16 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo~16_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|execute_|ctl_mRead~14_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|execute_|ctl_mRead~14_combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo~16 .lut_mask = 16'h80C0; -defparam \z80_|execute_|ctl_reg_sys_hilo~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~11 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~11_combout = (!\z80_|execute_|ctl_reg_sys_hilo~16_combout & (((!\z80_|execute_|ctl_mRead~36_combout & !\z80_|pla_decode_|Equal10~0_combout )) # (!\z80_|execute_|ctl_mWrite~7_combout ))) - - .dataa(\z80_|execute_|ctl_mWrite~7_combout ), - .datab(\z80_|execute_|ctl_mRead~36_combout ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~11 .lut_mask = 16'h0057; -defparam \z80_|execute_|ctl_reg_sel_pc~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~17 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~17_combout = (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~17 .lut_mask = 16'hE0F0; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~12 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~12_combout = (\z80_|execute_|ctl_reg_sel_pc~11_combout & (((\z80_|execute_|ctl_flags_bus~5_combout & \z80_|execute_|ctl_al_we~13_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~11_combout ), - .datab(\z80_|execute_|ctl_flags_bus~5_combout ), - .datac(\z80_|execute_|ctl_al_we~13_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~12 .lut_mask = 16'h80AA; -defparam \z80_|execute_|ctl_reg_sel_pc~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~13 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~13_combout = (\z80_|execute_|ctl_reg_sel_pc~12_combout & (\z80_|execute_|setM1~52_combout & ((!\z80_|pla_decode_|Equal6~1_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~12_combout ), - .datac(\z80_|execute_|setM1~52_combout ), - .datad(\z80_|pla_decode_|Equal6~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~13 .lut_mask = 16'h40C0; -defparam \z80_|execute_|ctl_reg_sel_pc~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~4_combout = (!\z80_|execute_|ctl_mRead~4_combout & (!\z80_|execute_|ixy_d~16_combout & (!\z80_|execute_|ixy_d~10_combout & !\z80_|execute_|ctl_mRead~5_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~4_combout ), - .datab(\z80_|execute_|ixy_d~16_combout ), - .datac(\z80_|execute_|ixy_d~10_combout ), - .datad(\z80_|execute_|ctl_mRead~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~4 .lut_mask = 16'h0001; -defparam \z80_|execute_|ctl_al_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~38 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~38_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ctl_al_we~4_combout )))) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|pla_decode_|Equal34~0_combout ), - .datad(\z80_|execute_|ctl_al_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~38 .lut_mask = 16'h2022; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y18_N24 -cycloneive_lcell_comb \z80_|execute_|fMRead~0 ( -// Equation(s): -// \z80_|execute_|fMRead~0_combout = ((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|fMRead~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~0 .lut_mask = 16'h5D5D; -defparam \z80_|execute_|fMRead~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~24 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~24_combout = (!\z80_|pla_decode_|Equal6~1_combout & (\z80_|execute_|ctl_bus_db_oe~1_combout & !\z80_|pla_decode_|Equal52~1_combout )) - - .dataa(gnd), - .datab(\z80_|pla_decode_|Equal6~1_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .datad(\z80_|pla_decode_|Equal52~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~24 .lut_mask = 16'h0030; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~25 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~25_combout = (!\z80_|execute_|fMRead~0_combout & ((!\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), - .datab(gnd), - .datac(\z80_|execute_|fMRead~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~25 .lut_mask = 16'h050F; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~4 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~4_combout = ((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~4 .lut_mask = 16'h0FAF; -defparam \z80_|execute_|ctl_inc_dec~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~21 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~21_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & (\z80_|execute_|ctl_reg_sys_hilo~20_combout & ((\z80_|execute_|ctl_inc_dec~4_combout ) # (!\z80_|pla_decode_|Equal33~3_combout )))) # -// (!\z80_|execute_|ctl_alu_op_low~8_combout & (((\z80_|execute_|ctl_inc_dec~4_combout ) # (!\z80_|pla_decode_|Equal33~3_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), - .datac(\z80_|execute_|ctl_inc_dec~4_combout ), - .datad(\z80_|pla_decode_|Equal33~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~21 .lut_mask = 16'hD0DD; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~9 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~9_combout = (!\z80_|execute_|ctl_ir_we~8_combout & (!\z80_|execute_|ctl_mRead~15_combout & !\z80_|execute_|ctl_ir_we~14_combout )) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_mRead~15_combout ), - .datad(\z80_|execute_|ctl_ir_we~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~9 .lut_mask = 16'h0005; -defparam \z80_|execute_|ctl_reg_sel_wz~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|execute_|ctl_ir_we~12_combout & \z80_|sequencer_|DFFE_M2_ff~q )) +// \z80_|execute_|ixy_d~4_combout = (!\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) .dataa(gnd), .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 .lut_mask = 16'hC000; -defparam \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~22 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~22_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~21_combout & (!\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout & ((\z80_|execute_|ctl_reg_sel_wz~9_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout -// )))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~21_combout ), - .datac(\z80_|execute_|ctl_reg_sel_wz~9_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~22 .lut_mask = 16'h00C4; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~23 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~23_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout & (((\z80_|execute_|pc_inc_hold~49_combout & !\z80_|pla_decode_|Equal6~1_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~49_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ), - .datac(\z80_|pla_decode_|Equal6~1_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~23 .lut_mask = 16'h08CC; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~8_combout = (!\z80_|execute_|ctl_mRead~17_combout & ((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~17_combout ), - .datab(\z80_|pla_decode_|Equal12~1_combout ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal25~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~8 .lut_mask = 16'h4455; -defparam \z80_|execute_|ctl_reg_sel_wz~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~18 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~18_combout = (!\z80_|execute_|ctl_reg_sel_wz~8_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # ((\z80_|execute_|ctl_state_alu~5_combout ) # (\z80_|execute_|ctl_alu_oe~2_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~8_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_state_alu~5_combout ), - .datad(\z80_|execute_|ctl_alu_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~18 .lut_mask = 16'h5554; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~19 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~19_combout = (!\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout & ((\z80_|execute_|fMRead~0_combout ) # ((!\z80_|execute_|ctl_mRead~9_combout & \z80_|execute_|pc_inc_hold~28_combout )))) - - .dataa(\z80_|execute_|fMRead~0_combout ), - .datab(\z80_|execute_|ctl_mRead~9_combout ), - .datac(\z80_|execute_|pc_inc_hold~28_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~19 .lut_mask = 16'h00BA; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~26 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~26_combout = (!\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout & (\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~26 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~5_combout = (\z80_|execute_|ctl_reg_sel_wz~8_combout & (!\z80_|pla_decode_|Equal34~0_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout & !\z80_|execute_|ctl_mRead~9_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~8_combout ), - .datab(\z80_|pla_decode_|Equal34~0_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), - .datad(\z80_|execute_|ctl_mRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~5 .lut_mask = 16'h0020; -defparam \z80_|execute_|ctl_al_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~27 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~27_combout = (!\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout & ((\z80_|execute_|ctl_al_we~5_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~38_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_al_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~27 .lut_mask = 16'h4404; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~28 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~28_combout = (\z80_|execute_|ctl_reg_sel_wz~7_combout & (\z80_|execute_|ctl_reg_sel_pc~13_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~7_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~13_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~28 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~18 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~18_combout = (\z80_|alu_control_|flags_cond_true~q & (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|pla_decode_|Equal35~0_combout ))) - - .dataa(\z80_|alu_control_|flags_cond_true~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|pla_decode_|Equal35~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~18 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sel_wz~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~37 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[0]~37_combout = (\z80_|execute_|ctl_reg_sel_wz~18_combout ) # ((\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|M5~q & \z80_|pla_decode_|Equal9~1_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~37 .lut_mask = 16'hFF80; -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~29 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[0]~29_combout = (\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ) # (((\z80_|execute_|ctl_reg_sys_hilo[0]~37_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~19_combout )) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~19_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~37_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~29 .lut_mask = 16'hFFBF; -defparam \z80_|execute_|ctl_reg_sys_hilo[0]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N12 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_62 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_62~combout = (!\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|execute_|ctl_reg_sel_ir~1_combout & \z80_|execute_|ctl_reg_sys_hilo[0]~29_combout )) - - .dataa(gnd), - .datab(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datac(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_62 .lut_mask = 16'h3000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_62 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~38 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~38_combout = ((\z80_|execute_|ctl_ir_we~11_combout ) # ((\z80_|execute_|ctl_mRead~6_combout ) # (\z80_|execute_|ctl_mRead~7_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_mRead~6_combout ), - .datad(\z80_|execute_|ctl_mRead~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~38 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_bus_inc_oe~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~39 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~39_combout = (\z80_|execute_|ctl_mRead~10_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~38_combout ) # ((\z80_|pla_decode_|Equal13~2_combout ) # (\z80_|execute_|ctl_state_alu~14_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~38_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|ctl_state_alu~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~39 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_bus_inc_oe~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~30 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~30_combout = (\z80_|execute_|pc_inc_hold~49_combout & (!\z80_|pla_decode_|Equal6~1_combout & ((!\z80_|pla_decode_|Equal33~2_combout ) # (!\z80_|decode_state_|use_ixiy~combout )))) - - .dataa(\z80_|execute_|pc_inc_hold~49_combout ), - .datab(\z80_|pla_decode_|Equal6~1_combout ), - .datac(\z80_|decode_state_|use_ixiy~combout ), - .datad(\z80_|pla_decode_|Equal33~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~30 .lut_mask = 16'h0222; -defparam \z80_|execute_|ctl_bus_inc_oe~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~45 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~45_combout = (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & ((!\z80_|execute_|nextM~2_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~30_combout )))) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~30_combout ), - .datab(\z80_|execute_|nextM~2_combout ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~45 .lut_mask = 16'h7000; -defparam \z80_|execute_|ctl_bus_inc_oe~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N12 -cycloneive_lcell_comb \z80_|execute_|fMRead~1 ( -// Equation(s): -// \z80_|execute_|fMRead~1_combout = ((!\z80_|pla_decode_|Equal33~0_combout ) # (!\z80_|ir_|opcode [7])) # (!\z80_|execute_|ctl_ir_we~5_combout ) - - .dataa(\z80_|execute_|ctl_ir_we~5_combout ), - .datab(gnd), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~1 .lut_mask = 16'h5FFF; -defparam \z80_|execute_|fMRead~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~36 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~36_combout = (\z80_|execute_|ixy_d~7_combout & (((\z80_|execute_|ctl_mRead~6_combout ) # (\z80_|execute_|ctl_mRead~5_combout )) # (!\z80_|execute_|fMRead~1_combout ))) - - .dataa(\z80_|execute_|fMRead~1_combout ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_mRead~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~36 .lut_mask = 16'hF0D0; -defparam \z80_|execute_|ctl_bus_inc_oe~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~27 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~27_combout = (\z80_|execute_|ctl_ir_we~4_combout & (!\z80_|execute_|ctl_mRead~9_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|execute_|ctl_mWrite~16_combout )))) # (!\z80_|execute_|ctl_ir_we~4_combout & -// (((!\z80_|execute_|ixy_d~5_combout )) # (!\z80_|execute_|ctl_mWrite~16_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ctl_mWrite~16_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|execute_|ctl_mRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~27 .lut_mask = 16'h153F; -defparam \z80_|execute_|ctl_bus_inc_oe~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~28 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~28_combout = (\z80_|execute_|ctl_bus_inc_oe~47_combout & (\z80_|execute_|ctl_bus_inc_oe~26_combout & \z80_|execute_|ctl_bus_inc_oe~27_combout )) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~47_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_bus_inc_oe~26_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~27_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~28 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_bus_inc_oe~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~37 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~37_combout = (\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ) # ((\z80_|execute_|ctl_bus_inc_oe~36_combout ) # ((!\z80_|execute_|ctl_bus_inc_oe~28_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~46_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~36_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~46_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~28_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~37 .lut_mask = 16'hEFFF; -defparam \z80_|execute_|ctl_bus_inc_oe~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~40 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~40_combout = (\z80_|execute_|ctl_bus_inc_oe~45_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~37_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~39_combout & \z80_|execute_|ctl_ir_we~4_combout ))) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~39_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~45_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~37_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~40 .lut_mask = 16'hFFEC; -defparam \z80_|execute_|ctl_bus_inc_oe~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~35 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~35_combout = ((\z80_|execute_|ctl_alu_oe~2_combout & ((\z80_|execute_|ctl_mRead~6_combout ) # (\z80_|execute_|ctl_mRead~10_combout )))) # (!\z80_|execute_|ctl_bus_inc_oe~44_combout ) - - .dataa(\z80_|execute_|ctl_mRead~6_combout ), - .datab(\z80_|execute_|ctl_alu_oe~2_combout ), - .datac(\z80_|execute_|ctl_mRead~10_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~44_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~35 .lut_mask = 16'hC8FF; -defparam \z80_|execute_|ctl_bus_inc_oe~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~77 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~77_combout = (\z80_|execute_|ctl_inc_cy~76_combout & (((!\z80_|execute_|ctl_alu_shift_oe~14_combout & !\z80_|execute_|ctl_sw_4u~0_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|execute_|ctl_sw_4u~0_combout ), - .datac(\z80_|execute_|ctl_inc_cy~76_combout ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~77_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~77 .lut_mask = 16'h10F0; -defparam \z80_|execute_|ctl_inc_cy~77 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~32 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~32_combout = (\z80_|execute_|ixy_d~9_combout & (!\z80_|pla_decode_|Equal11~0_combout & ((!\z80_|pla_decode_|Equal10~0_combout )))) # (!\z80_|execute_|ixy_d~9_combout & (((!\z80_|execute_|ctl_alu_shift_oe~14_combout )) # -// (!\z80_|pla_decode_|Equal11~0_combout ))) - - .dataa(\z80_|execute_|ixy_d~9_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datad(\z80_|pla_decode_|Equal10~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~32 .lut_mask = 16'h1537; -defparam \z80_|execute_|ctl_bus_inc_oe~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M4_ff~q & (\z80_|execute_|ctl_mWrite~2_combout & \z80_|pla_decode_|Equal55~0_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|execute_|ctl_mWrite~2_combout ), - .datad(\z80_|pla_decode_|Equal55~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~33 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~33_combout = (!\z80_|execute_|ctl_reg_sys_we~1_combout & (\z80_|execute_|ctl_bus_inc_oe~32_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout & \z80_|execute_|ctl_bus_inc_oe~24_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_we~1_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~32_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~33 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_bus_inc_oe~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~34 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~34_combout = (((!\z80_|execute_|ctl_bus_inc_oe~33_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[1]~5_combout )) # (!\z80_|execute_|ctl_inc_cy~77_combout )) # (!\z80_|execute_|ctl_inc_cy~53_combout ) - - .dataa(\z80_|execute_|ctl_inc_cy~53_combout ), - .datab(\z80_|execute_|ctl_inc_cy~77_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~34 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_bus_inc_oe~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~41 ( -// Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~41_combout = (\z80_|execute_|ctl_bus_inc_oe~40_combout ) # (((\z80_|execute_|ctl_bus_inc_oe~35_combout ) # (\z80_|execute_|ctl_bus_inc_oe~34_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~31_combout )) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~40_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~31_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~35_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~34_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~41 .lut_mask = 16'hFFFB; -defparam \z80_|execute_|ctl_bus_inc_oe~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~10 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~10_combout = (\z80_|execute_|ctl_reg_sel_wz~8_combout & ((\z80_|execute_|ctl_reg_sel_wz~9_combout ) # ((!\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|execute_|ctl_reg_sel_wz~8_combout & -// (((!\z80_|execute_|ctl_alu_oe~2_combout & !\z80_|execute_|ctl_ir_we~4_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~9_combout ), - .datab(\z80_|execute_|ctl_alu_oe~2_combout ), - .datac(\z80_|execute_|ctl_reg_sel_wz~8_combout ), - .datad(\z80_|execute_|ctl_ir_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~10 .lut_mask = 16'hA0F3; -defparam \z80_|execute_|ctl_reg_sel_wz~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~11 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~11_combout = (\z80_|execute_|ctl_reg_sel_wz~7_combout & \z80_|execute_|ctl_reg_sel_wz~10_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_sel_wz~7_combout ), - .datac(\z80_|execute_|ctl_reg_sel_wz~10_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~11 .lut_mask = 16'hC0C0; -defparam \z80_|execute_|ctl_reg_sel_wz~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~3 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~3_combout = (\z80_|execute_|ctl_sw_1d~4_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~4_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout )) - - .dataa(\z80_|execute_|ctl_sw_1d~4_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~3 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_sw_4d~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~4 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~4_combout = (\z80_|execute_|ctl_flags_bus~5_combout & (((!\z80_|execute_|ctl_reg_in_hi~2_combout )) # (!\z80_|pla_decode_|Equal9~1_combout ))) # (!\z80_|execute_|ctl_flags_bus~5_combout & (!\z80_|execute_|ixy_d~6_combout & -// ((!\z80_|execute_|ctl_reg_in_hi~2_combout ) # (!\z80_|pla_decode_|Equal9~1_combout )))) - - .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), - .datab(\z80_|pla_decode_|Equal9~1_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~4 .lut_mask = 16'h2A3F; -defparam \z80_|execute_|ctl_sw_4d~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y14_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~2 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~2_combout = (\z80_|execute_|ctl_reg_in_lo~9_combout & (\z80_|execute_|fMRead~6_combout & \z80_|execute_|fMRead~8_combout )) - - .dataa(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datab(gnd), - .datac(\z80_|execute_|fMRead~6_combout ), - .datad(\z80_|execute_|fMRead~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~2 .lut_mask = 16'hA000; -defparam \z80_|execute_|ctl_sw_4d~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~5 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~5_combout = (\z80_|execute_|ctl_reg_sel_wz~11_combout & (\z80_|execute_|ctl_sw_4d~3_combout & (\z80_|execute_|ctl_sw_4d~4_combout & \z80_|execute_|ctl_sw_4d~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~11_combout ), - .datab(\z80_|execute_|ctl_sw_4d~3_combout ), - .datac(\z80_|execute_|ctl_sw_4d~4_combout ), - .datad(\z80_|execute_|ctl_sw_4d~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~5 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_sw_4d~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|setM1~45 ( -// Equation(s): -// \z80_|execute_|setM1~45_combout = (!\z80_|execute_|ctl_iorw~11_combout & (\z80_|execute_|ctl_mRead~19_combout & (!\z80_|execute_|ctl_mRead~13_combout & !\z80_|execute_|ctl_iorw~10_combout ))) - - .dataa(\z80_|execute_|ctl_iorw~11_combout ), - .datab(\z80_|execute_|ctl_mRead~19_combout ), - .datac(\z80_|execute_|ctl_mRead~13_combout ), - .datad(\z80_|execute_|ctl_iorw~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~45 .lut_mask = 16'h0004; -defparam \z80_|execute_|setM1~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N12 -cycloneive_lcell_comb \z80_|execute_|setM1~46 ( -// Equation(s): -// \z80_|execute_|setM1~46_combout = (\z80_|execute_|ctl_al_we~13_combout & (\z80_|execute_|setM1~45_combout & !\z80_|execute_|ctl_mWrite~6_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_al_we~13_combout ), - .datac(\z80_|execute_|setM1~45_combout ), - .datad(\z80_|execute_|ctl_mWrite~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~46 .lut_mask = 16'h00C0; -defparam \z80_|execute_|setM1~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~1 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~1_combout = ((!\z80_|decode_state_|use_ixiy~combout & ((\z80_|pla_decode_|Equal50~0_combout ) # (\z80_|pla_decode_|Equal49~0_combout )))) # (!\z80_|execute_|setM1~46_combout ) - - .dataa(\z80_|pla_decode_|Equal50~0_combout ), - .datab(\z80_|decode_state_|use_ixiy~combout ), - .datac(\z80_|pla_decode_|Equal49~0_combout ), - .datad(\z80_|execute_|setM1~46_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~1 .lut_mask = 16'h32FF; -defparam \z80_|execute_|ctl_sw_4d~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~0 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~0_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ) # ((\z80_|execute_|ctl_reg_sel_wz~18_combout ) # ((\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ctl_al_we~14_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|execute_|ctl_al_we~14_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~0 .lut_mask = 16'hFFAE; -defparam \z80_|execute_|ctl_sw_4d~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~6 ( -// Equation(s): -// \z80_|execute_|ctl_sw_4d~6_combout = ((\z80_|execute_|ctl_sw_4d~0_combout ) # ((\z80_|execute_|ctl_sw_4d~1_combout & \z80_|execute_|ctl_state_alu~5_combout ))) # (!\z80_|execute_|ctl_sw_4d~5_combout ) - - .dataa(\z80_|execute_|ctl_sw_4d~5_combout ), - .datab(\z80_|execute_|ctl_sw_4d~1_combout ), - .datac(\z80_|execute_|ctl_state_alu~5_combout ), - .datad(\z80_|execute_|ctl_sw_4d~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_4d~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_4d~6 .lut_mask = 16'hFFD5; -defparam \z80_|execute_|ctl_sw_4d~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y18_N18 -cycloneive_lcell_comb \z80_|execute_|fMRead~4 ( -// Equation(s): -// \z80_|execute_|fMRead~4_combout = (\z80_|execute_|ctl_reg_sel_wz~8_combout & (!\z80_|pla_decode_|Equal34~0_combout & \z80_|execute_|ctl_al_we~4_combout )) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~8_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal34~0_combout ), - .datad(\z80_|execute_|ctl_al_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~4 .lut_mask = 16'h0A00; -defparam \z80_|execute_|fMRead~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~16 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~16_combout = (((\z80_|execute_|ctl_state_alu~5_combout & !\z80_|execute_|fMRead~4_combout )) # (!\z80_|execute_|ctl_reg_sel_pc~10_combout )) # (!\z80_|execute_|ctl_apin_mux~0_combout ) - - .dataa(\z80_|execute_|ctl_apin_mux~0_combout ), - .datab(\z80_|execute_|ctl_state_alu~5_combout ), - .datac(\z80_|execute_|fMRead~4_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~16 .lut_mask = 16'h5DFF; -defparam \z80_|execute_|ctl_reg_sel_pc~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~14 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~14_combout = (!\z80_|pla_decode_|Equal21~1_combout & (((\z80_|decode_state_|table_xx~0_combout ) # (!\z80_|pla_decode_|Equal33~0_combout )) # (!\z80_|pla_decode_|Equal41~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal41~0_combout ), - .datab(\z80_|decode_state_|table_xx~0_combout ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|pla_decode_|Equal21~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~14 .lut_mask = 16'h00DF; -defparam \z80_|execute_|ctl_reg_sel_pc~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~20 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~20_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|pla_decode_|Equal33~3_combout ) # (!\z80_|execute_|ctl_al_we~5_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|execute_|ctl_al_we~5_combout ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|pla_decode_|Equal33~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~20 .lut_mask = 16'h5010; -defparam \z80_|execute_|ctl_reg_sel_pc~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y18_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~15 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~15_combout = (\z80_|execute_|ctl_reg_sel_pc~20_combout ) # ((!\z80_|execute_|fMRead~0_combout & ((!\z80_|execute_|setM1~36_combout ) # (!\z80_|execute_|ctl_reg_sel_pc~14_combout )))) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~14_combout ), - .datab(\z80_|execute_|setM1~36_combout ), - .datac(\z80_|execute_|ctl_reg_sel_pc~20_combout ), - .datad(\z80_|execute_|fMRead~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~15 .lut_mask = 16'hF0F7; -defparam \z80_|execute_|ctl_reg_sel_pc~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~17 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~17_combout = (!\z80_|nM1_int~2_combout & (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|execute_|ctl_mWrite~16_combout )) # (!\z80_|execute_|ctl_mWrite~7_combout ))) - - .dataa(\z80_|pla_decode_|Equal11~0_combout ), - .datab(\z80_|execute_|ctl_mWrite~7_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_mWrite~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~17 .lut_mask = 16'h0307; -defparam \z80_|execute_|ctl_reg_sel_pc~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~18 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~18_combout = (((!\z80_|execute_|ctl_bus_inc_oe~30_combout & \z80_|execute_|ixy_d~5_combout )) # (!\z80_|execute_|ctl_reg_sel_pc~17_combout )) # (!\z80_|execute_|ctl_sw_4u~1_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~30_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_sw_4u~1_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~18 .lut_mask = 16'h4FFF; -defparam \z80_|execute_|ctl_reg_sel_pc~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~19 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_pc~19_combout = ((\z80_|execute_|ctl_reg_sel_pc~16_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~15_combout ) # (\z80_|execute_|ctl_reg_sel_pc~18_combout ))) # (!\z80_|execute_|ctl_reg_sel_pc~13_combout ) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~13_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~16_combout ), - .datac(\z80_|execute_|ctl_reg_sel_pc~15_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_pc~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_pc~19 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_reg_sel_pc~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N24 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~3 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_pc~3_combout = (\z80_|reg_control_|reg_sel_pc~2_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~4_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout & \z80_|execute_|ctl_reg_sel_wz~4_combout ))) - - .dataa(\z80_|reg_control_|reg_sel_pc~2_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~4_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_pc~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_pc~3 .lut_mask = 16'h0800; -defparam \z80_|reg_control_|reg_sel_pc~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N18 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc ( -// Equation(s): -// \z80_|reg_control_|reg_sel_pc~combout = (!\z80_|execute_|ctl_reg_sel_wz~18_combout & (\z80_|execute_|ctl_reg_sel_pc~19_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & \z80_|reg_control_|reg_sel_pc~3_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~18_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~19_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .datad(\z80_|reg_control_|reg_sel_pc~3_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_pc~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_pc .lut_mask = 16'h0400; -defparam \z80_|reg_control_|reg_sel_pc .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y15_N8 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_74 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_74~combout = (\z80_|reg_control_|reg_sel_pc~combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout & !\z80_|reg_control_|reg_sys_we_lo~combout )) - - .dataa(gnd), - .datab(\z80_|reg_control_|reg_sel_pc~combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .datad(\z80_|reg_control_|reg_sys_we_lo~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_74 .lut_mask = 16'h00C0; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N22 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~2 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[0]~2_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ) # ((\z80_|execute_|ctl_bus_inc_oe~41_combout ) # ((\z80_|execute_|ctl_sw_4d~6_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|execute_|ctl_sw_4d~6_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[0]~2 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|db_lo_as[0]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N18 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_75 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_75~combout = (\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout & (\z80_|reg_control_|reg_sel_pc~combout & \z80_|reg_control_|reg_sys_we_lo~combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .datac(\z80_|reg_control_|reg_sel_pc~combout ), - .datad(\z80_|reg_control_|reg_sys_we_lo~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_75 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N3 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[7]~24_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N2 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~22 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[7]~22_combout = (\z80_|reg_file_|gdfx_temp0[7]~92_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) # (!\z80_|reg_file_|gdfx_temp0[7]~92_combout & -// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [7]), - .datad(\z80_|execute_|ctl_sw_4d~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[7]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[7]~22 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_lo_as[7]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N28 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_63 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_63~combout = (\z80_|reg_control_|reg_sys_we_lo~combout & (\z80_|execute_|ctl_reg_sel_ir~1_combout & \z80_|execute_|ctl_reg_sys_hilo[0]~29_combout )) - - .dataa(gnd), - .datab(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datac(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_63 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y17_N25 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[7]~24_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N14 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~23 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[7]~23_combout = (\z80_|reg_file_|db_lo_as[7]~22_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datac(\z80_|reg_file_|db_lo_as[7]~22_combout ), - .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[7]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[7]~23 .lut_mask = 16'hF030; -defparam \z80_|reg_file_|db_lo_as[7]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N26 -cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_10~0 ( -// Equation(s): -// \z80_|resets_|SYNTHESIZED_WIRE_10~0_combout = !\z80_|resets_|SYNTHESIZED_WIRE_12~q - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h0F0F; -defparam \z80_|resets_|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y17_N27 -dffeas \z80_|resets_|SYNTHESIZED_WIRE_10 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_10 .is_wysiwyg = "true"; -defparam \z80_|resets_|SYNTHESIZED_WIRE_10 .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y17_N9 -dffeas \z80_|resets_|SYNTHESIZED_WIRE_9 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_9 .is_wysiwyg = "true"; -defparam \z80_|resets_|SYNTHESIZED_WIRE_9 .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y17_N29 -dffeas \z80_|resets_|DFFE_intr_ff3 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|resets_|DFFE_intr_ff3~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|resets_|DFFE_intr_ff3 .is_wysiwyg = "true"; -defparam \z80_|resets_|DFFE_intr_ff3 .power_up = "low"; -// synopsys translate_on - -// Location: IOIBUF_X53_Y14_N1 -cycloneive_io_ibuf \KEY[0]~input ( - .i(KEY[0]), - .ibar(gnd), - .o(\KEY[0]~input_o )); -// synopsys translate_off -defparam \KEY[0]~input .bus_hold = "false"; -defparam \KEY[0]~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: LCCOMB_X52_Y14_N4 -cycloneive_lcell_comb reset( -// Equation(s): -// \reset~combout = (!\KEY[0]~input_o ) # (!\ula_|pll_|altpll_component|auto_generated|wire_pll1_locked ) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|pll_|altpll_component|auto_generated|wire_pll1_locked ), - .datad(\KEY[0]~input_o ), - .cin(gnd), - .combout(\reset~combout ), - .cout()); -// synopsys translate_off -defparam reset.lut_mask = 16'h0FFF; -defparam reset.sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N26 -cycloneive_lcell_comb \z80_|resets_|x1~0 ( -// Equation(s): -// \z80_|resets_|x1~0_combout = !\reset~combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\reset~combout ), - .cin(gnd), - .combout(\z80_|resets_|x1~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|resets_|x1~0 .lut_mask = 16'h00FF; -defparam \z80_|resets_|x1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y33_N0 -cycloneive_lcell_comb \z80_|fpga_reset~feeder ( -// Equation(s): -// \z80_|fpga_reset~feeder_combout = VCC - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(gnd), - .cin(gnd), - .combout(\z80_|fpga_reset~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|fpga_reset~feeder .lut_mask = 16'hFFFF; -defparam \z80_|fpga_reset~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y33_N1 -dffeas \z80_|fpga_reset ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|fpga_reset~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|fpga_reset~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|fpga_reset .is_wysiwyg = "true"; -defparam \z80_|fpga_reset .power_up = "low"; -// synopsys translate_on - -// Location: CLKCTRL_G12 -cycloneive_clkctrl \z80_|fpga_reset~clkctrl ( - .ena(vcc), - .inclk({vcc,vcc,vcc,\z80_|fpga_reset~q }), - .clkselect(2'b00), - .devclrn(devclrn), - .devpor(devpor), - .outclk(\z80_|fpga_reset~clkctrl_outclk )); -// synopsys translate_off -defparam \z80_|fpga_reset~clkctrl .clock_type = "global clock"; -defparam \z80_|fpga_reset~clkctrl .ena_register_mode = "none"; -// synopsys translate_on - -// Location: FF_X35_Y13_N27 -dffeas \z80_|resets_|x1 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|resets_|x1~0_combout ), - .asdata(vcc), - .clrn(\z80_|fpga_reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|resets_|x1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|resets_|x1 .is_wysiwyg = "true"; -defparam \z80_|resets_|x1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N18 -cycloneive_lcell_comb \z80_|resets_|clrpc_int~0 ( -// Equation(s): -// \z80_|resets_|clrpc_int~0_combout = (\z80_|sequencer_|DFFE_M1_ff~q & (((\z80_|resets_|clrpc_int~q )))) # (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|resets_|clrpc_int~q & !\z80_|resets_|x1~q )) # -// (!\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|resets_|clrpc_int~q )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|resets_|clrpc_int~q ), - .datad(\z80_|resets_|x1~q ), - .cin(gnd), - .combout(\z80_|resets_|clrpc_int~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|resets_|clrpc_int~0 .lut_mask = 16'hB0B4; -defparam \z80_|resets_|clrpc_int~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y17_N19 -dffeas \z80_|resets_|clrpc_int ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|resets_|clrpc_int~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|resets_|clrpc_int~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|resets_|clrpc_int .is_wysiwyg = "true"; -defparam \z80_|resets_|clrpc_int .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N28 -cycloneive_lcell_comb \z80_|resets_|clrpc~0 ( -// Equation(s): -// \z80_|resets_|clrpc~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_10~q ) # ((\z80_|resets_|SYNTHESIZED_WIRE_9~q ) # ((\z80_|resets_|DFFE_intr_ff3~q ) # (\z80_|resets_|clrpc_int~q ))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), - .datac(\z80_|resets_|DFFE_intr_ff3~q ), - .datad(\z80_|resets_|clrpc_int~q ), - .cin(gnd), - .combout(\z80_|resets_|clrpc~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|resets_|clrpc~0 .lut_mask = 16'hFFFE; -defparam \z80_|resets_|clrpc~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N4 -cycloneive_lcell_comb \z80_|address_latch_|abusz[7] ( -// Equation(s): -// \z80_|address_latch_|abusz [7] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[7]~24_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(\z80_|reg_file_|db_lo_as[7]~24_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [7]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[7] .lut_mask = 16'h0F00; -defparam \z80_|address_latch_|abusz[7] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~1 ( -// Equation(s): -// \z80_|execute_|ctl_apin_mux~1_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (\z80_|sequencer_|DFFE_M2_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_apin_mux~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_apin_mux~1 .lut_mask = 16'h5550; -defparam \z80_|execute_|ctl_apin_mux~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~6_combout = (\z80_|execute_|ctl_apin_mux~1_combout & (((\z80_|pla_decode_|Equal33~3_combout ) # (!\z80_|execute_|ctl_al_we~14_combout )) # (!\z80_|execute_|ctl_al_we~5_combout ))) - - .dataa(\z80_|execute_|ctl_apin_mux~1_combout ), - .datab(\z80_|execute_|ctl_al_we~5_combout ), - .datac(\z80_|execute_|ctl_al_we~14_combout ), - .datad(\z80_|pla_decode_|Equal33~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~6 .lut_mask = 16'hAA2A; -defparam \z80_|execute_|ctl_al_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~7_combout = (\z80_|execute_|ctl_state_alu~6_combout & (((!\z80_|execute_|ctl_flags_bus~5_combout ) # (!\z80_|execute_|ctl_al_we~13_combout )))) # (!\z80_|execute_|ctl_state_alu~6_combout & (\z80_|execute_|ctl_ir_we~4_combout & -// ((!\z80_|execute_|ctl_flags_bus~5_combout ) # (!\z80_|execute_|ctl_al_we~13_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~6_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_al_we~13_combout ), - .datad(\z80_|execute_|ctl_flags_bus~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~7 .lut_mask = 16'h0EEE; -defparam \z80_|execute_|ctl_al_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~8_combout = ((\z80_|execute_|ctl_al_we~7_combout ) # ((\z80_|execute_|ixy_d~6_combout & \z80_|pla_decode_|Equal35~0_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|execute_|ctl_al_we~7_combout ), - .datad(\z80_|pla_decode_|Equal35~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~8 .lut_mask = 16'hFBF3; -defparam \z80_|execute_|ctl_al_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_oe~10_combout = (\z80_|decode_state_|in_halt~q ) # (((!\z80_|pla_decode_|Equal33~1_combout & !\z80_|pla_decode_|Equal33~0_combout )) # (!\z80_|pla_decode_|Equal77~0_combout )) - - .dataa(\z80_|pla_decode_|Equal33~1_combout ), - .datab(\z80_|decode_state_|in_halt~q ), - .datac(\z80_|pla_decode_|Equal77~0_combout ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_oe~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_oe~10 .lut_mask = 16'hCFDF; -defparam \z80_|execute_|ctl_alu_oe~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~9 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~9_combout = (((!\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~29_combout )) # (!\z80_|execute_|ctl_al_we~4_combout )) # (!\z80_|execute_|ctl_alu_oe~10_combout ) - - .dataa(\z80_|execute_|ctl_alu_oe~10_combout ), - .datab(\z80_|execute_|ctl_al_we~4_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~29_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~9 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_al_we~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~10 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~10_combout = (\z80_|execute_|ctl_al_we~8_combout ) # ((\z80_|execute_|ctl_state_alu~5_combout & ((\z80_|execute_|ctl_al_we~9_combout ) # (!\z80_|execute_|setM1~45_combout )))) - - .dataa(\z80_|execute_|ctl_al_we~8_combout ), - .datab(\z80_|execute_|ctl_state_alu~5_combout ), - .datac(\z80_|execute_|setM1~45_combout ), - .datad(\z80_|execute_|ctl_al_we~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~10 .lut_mask = 16'hEEAE; -defparam \z80_|execute_|ctl_al_we~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~11 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~11_combout = (\z80_|execute_|ctl_al_we~6_combout ) # ((\z80_|execute_|ctl_al_we~10_combout ) # (!\z80_|execute_|ctl_sw_4d~5_combout )) - - .dataa(\z80_|execute_|ctl_al_we~6_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_sw_4d~5_combout ), - .datad(\z80_|execute_|ctl_al_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~11 .lut_mask = 16'hFFAF; -defparam \z80_|execute_|ctl_al_we~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_al_we~12 ( -// Equation(s): -// \z80_|execute_|ctl_al_we~12_combout = (\z80_|execute_|ctl_al_we~11_combout ) # (((\z80_|execute_|ixy_d~7_combout & \z80_|pla_decode_|Equal6~1_combout )) # (!\z80_|execute_|setM1~52_combout )) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_al_we~11_combout ), - .datac(\z80_|execute_|setM1~52_combout ), - .datad(\z80_|pla_decode_|Equal6~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_al_we~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_al_we~12 .lut_mask = 16'hEFCF; -defparam \z80_|execute_|ctl_al_we~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y16_N5 -dffeas \z80_|address_latch_|Q[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [7]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[7] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~6 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~6_combout = (\z80_|execute_|ctl_apin_mux~0_combout & (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout & ((!\z80_|execute_|ctl_ir_we~4_combout ) # (!\z80_|pla_decode_|Equal9~1_combout )))) - - .dataa(\z80_|execute_|ctl_apin_mux~0_combout ), - .datab(\z80_|pla_decode_|Equal9~1_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), - .datad(\z80_|execute_|ctl_ir_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~6 .lut_mask = 16'h020A; -defparam \z80_|execute_|ctl_inc_dec~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N24 -cycloneive_lcell_comb \z80_|execute_|fIOWrite~0 ( -// Equation(s): -// \z80_|execute_|fIOWrite~0_combout = ((!\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q ))) # (!\z80_|sequencer_|DFFE_M2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), .datac(\z80_|sequencer_|DFFE_T1_ff~q ), .datad(\z80_|sequencer_|DFFE_T2_ff~q ), .cin(gnd), - .combout(\z80_|execute_|fIOWrite~0_combout ), + .combout(\z80_|execute_|ixy_d~4_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fIOWrite~0 .lut_mask = 16'h3373; -defparam \z80_|execute_|fIOWrite~0 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ixy_d~4 .lut_mask = 16'h0030; +defparam \z80_|execute_|ixy_d~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y18_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~8 ( +// Location: LCCOMB_X21_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|ixy_d~11 ( // Equation(s): -// \z80_|execute_|ctl_inc_dec~8_combout = (\z80_|execute_|ctl_mWrite~4_combout & (((\z80_|execute_|ctl_mRead~11_combout ) # (!\z80_|execute_|fIOWrite~0_combout )) # (!\z80_|execute_|ctl_inc_dec~4_combout ))) +// \z80_|execute_|ixy_d~11_combout = (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # ((\z80_|sequencer_|DFFE_T5_ff~q ) # (!\z80_|execute_|ixy_d~4_combout )))) - .dataa(\z80_|execute_|ctl_inc_dec~4_combout ), - .datab(\z80_|execute_|fIOWrite~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|execute_|ctl_mRead~11_combout ), + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T5_ff~q ), + .datad(\z80_|execute_|ixy_d~4_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~8_combout ), + .combout(\z80_|execute_|ixy_d~11_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~8 .lut_mask = 16'hF070; -defparam \z80_|execute_|ctl_inc_dec~8 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ixy_d~11 .lut_mask = 16'hC8CC; +defparam \z80_|execute_|ixy_d~11 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y18_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~9 ( +// Location: LCCOMB_X21_Y14_N6 +cycloneive_lcell_comb \z80_|execute_|ixy_d~9 ( // Equation(s): -// \z80_|execute_|ctl_inc_dec~9_combout = ((\z80_|execute_|ctl_inc_dec~8_combout ) # ((!\z80_|execute_|ctl_reg_gp_we~0_combout & \z80_|ir_|opcode [3]))) # (!\z80_|execute_|ctl_inc_dec~3_combout ) +// \z80_|execute_|ixy_d~9_combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_M3_ff~q ) - .dataa(\z80_|execute_|ctl_reg_gp_we~0_combout ), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|execute_|ctl_inc_dec~3_combout ), - .datad(\z80_|execute_|ctl_inc_dec~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~9 .lut_mask = 16'hFF4F; -defparam \z80_|execute_|ctl_inc_dec~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~10 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~10_combout = (\z80_|execute_|ctl_inc_dec~9_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_inc_dec~6_combout ), - .datac(\z80_|execute_|ctl_inc_dec~9_combout ), + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), .datad(gnd), .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~10_combout ), + .combout(\z80_|execute_|ixy_d~9_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~10 .lut_mask = 16'hF3F3; -defparam \z80_|execute_|ctl_inc_dec~10 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ixy_d~9 .lut_mask = 16'hA0A0; +defparam \z80_|execute_|ixy_d~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y17_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~7 ( +// Location: LCCOMB_X26_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|ixy_d~7 ( // Equation(s): -// \z80_|execute_|ctl_inc_dec~7_combout = (!\z80_|execute_|ctl_bus_inc_oe~33_combout ) # (!\z80_|execute_|ctl_inc_dec~5_combout ) +// \z80_|execute_|ixy_d~7_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M3_ff~q ) - .dataa(\z80_|execute_|ctl_inc_dec~5_combout ), + .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~7_combout ), + .combout(\z80_|execute_|ixy_d~7_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~7 .lut_mask = 16'h55FF; -defparam \z80_|execute_|ctl_inc_dec~7 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ixy_d~7 .lut_mask = 16'h0F00; +defparam \z80_|execute_|ixy_d~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y17_N17 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[2]~9_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [2]), - .prn(vcc)); +// Location: LCCOMB_X24_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|ixy_d~6 ( +// Equation(s): +// \z80_|execute_|ixy_d~6_combout = (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_M3_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~6_combout ), + .cout()); // synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[2] .power_up = "low"; +defparam \z80_|execute_|ixy_d~6 .lut_mask = 16'hA0A0; +defparam \z80_|execute_|ixy_d~6 .sum_lutc_input = "datac"; // synopsys translate_on // Location: LCCOMB_X26_Y13_N8 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_54 ( +cycloneive_lcell_comb \z80_|execute_|ixy_d~8 ( // Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_54~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl2~0_combout )) +// \z80_|execute_|ixy_d~8_combout = (\z80_|sequencer_|DFFE_T5_ff~q & \z80_|sequencer_|DFFE_M3_ff~q ) .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_54 .lut_mask = 16'h0C00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N22 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_58 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_58~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_58 .lut_mask = 16'h0C00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N26 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_55 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_55~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl2~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_55 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y9_N1 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N0 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_59 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_59~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_59 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_59 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y9_N3 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~34 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~34_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (\z80_|reg_file_|b2v_latch_hl2_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (((\z80_|reg_file_|b2v_latch_hl_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]), - .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [2]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~34 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[2]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N28 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_51 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_51~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_de~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_de~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_51 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y13_N11 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N12 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~4 ( -// Equation(s): -// \z80_|reg_control_|reg_sel_de2~4_combout = (\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de2~q & ((\z80_|reg_control_|reg_sel_de2~5_combout ))) # (!\z80_|reg_control_|bank_hl_de2~q & (\z80_|reg_control_|reg_sel_de2~6_combout )))) - - .dataa(\z80_|reg_control_|reg_sel_de2~6_combout ), - .datab(\z80_|reg_control_|reg_sel_de2~5_combout ), - .datac(\z80_|reg_control_|bank_hl_de2~q ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_de2~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sel_de2~4 .lut_mask = 16'hCA00; -defparam \z80_|reg_control_|reg_sel_de2~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N2 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_46 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_46~combout = (!\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|reg_control_|reg_sel_de2~4_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datac(\z80_|reg_control_|reg_sel_de2~4_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_46 .lut_mask = 16'h3000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N14 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_47 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_47~combout = (\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|reg_control_|reg_sel_de2~4_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datac(\z80_|reg_control_|reg_sel_de2~4_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_47 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y13_N17 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~33 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~33_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [2] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [2] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [2]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~33 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[2]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N26 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 .lut_mask = 16'hF000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N14 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & !\z80_|reg_control_|bank_exx~q ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 .lut_mask = 16'h0010; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y11_N15 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N8 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & \z80_|reg_control_|bank_exx~q ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), - .datad(\z80_|reg_control_|bank_exx~q ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 .lut_mask = 16'h1000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y11_N25 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~36 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~36_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [2]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [2]), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~36 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[2]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N30 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_83 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_83~combout = (\z80_|execute_|ctl_reg_sel_wz~17_combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout & \z80_|reg_control_|reg_sys_we_lo~combout )) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~17_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), + .datab(\z80_|sequencer_|DFFE_T5_ff~q ), .datac(gnd), - .datad(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .combout(\z80_|execute_|ixy_d~8_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_83 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_83 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ixy_d~8 .lut_mask = 16'hCC00; +defparam \z80_|execute_|ixy_d~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y10_N13 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~37 ( +// Location: LCCOMB_X27_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|ixy_d~12 ( // Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~37_combout = (\z80_|reg_file_|gdfx_temp0[2]~36_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) +// \z80_|execute_|ixy_d~12_combout = (!\z80_|execute_|ixy_d~9_combout & (!\z80_|execute_|ixy_d~7_combout & (!\z80_|execute_|ixy_d~6_combout & !\z80_|execute_|ixy_d~8_combout ))) - .dataa(\z80_|reg_file_|gdfx_temp0[2]~36_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [2]), - .datad(gnd), + .dataa(\z80_|execute_|ixy_d~9_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ixy_d~8_combout ), .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~37_combout ), + .combout(\z80_|execute_|ixy_d~12_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~37 .lut_mask = 16'hA2A2; -defparam \z80_|reg_file_|gdfx_temp0[2]~37 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ixy_d~12 .lut_mask = 16'h0001; +defparam \z80_|execute_|ixy_d~12 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y12_N6 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 ( +// Location: LCCOMB_X29_Y13_N24 +cycloneive_lcell_comb \z80_|pla_decode_|Equal33~0 ( // Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout = (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) +// \z80_|pla_decode_|Equal33~0_combout = (\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [0] & \z80_|ir_|opcode [1])) - .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|ir_|opcode [0]), + .datac(gnd), + .datad(\z80_|ir_|opcode [1]), .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .combout(\z80_|pla_decode_|Equal33~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal33~0 .lut_mask = 16'h2200; +defparam \z80_|pla_decode_|Equal33~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y10_N25 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~39 ( +// Location: LCCOMB_X20_Y17_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal33~1 ( // Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~39_combout = (\z80_|alu_control_|db[2]~29_combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [2]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) # (!\z80_|alu_control_|db[2]~29_combout & -// (!\z80_|execute_|ctl_reg_in_lo~8_combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) +// \z80_|pla_decode_|Equal33~1_combout = (\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [3])) - .dataa(\z80_|alu_control_|db[2]~29_combout ), - .datab(\z80_|reg_file_|b2v_latch_sp_lo|latch [2]), - .datac(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|ir_|opcode [4]), + .datac(gnd), + .datad(\z80_|ir_|opcode [3]), .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~39_combout ), + .combout(\z80_|pla_decode_|Equal33~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~39 .lut_mask = 16'h8CAF; -defparam \z80_|reg_file_|gdfx_temp0[2]~39 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal33~1 .lut_mask = 16'h0088; +defparam \z80_|pla_decode_|Equal33~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y15_N22 -cycloneive_lcell_comb \z80_|reg_control_|reg_sel_iy~2 ( +// Location: LCCOMB_X24_Y15_N24 +cycloneive_lcell_comb \z80_|pla_decode_|Equal33~2 ( // Equation(s): -// \z80_|reg_control_|reg_sel_iy~2_combout = (\z80_|decode_state_|DFFE_instIY1~q & (!\z80_|decode_state_|DFFE_inst4~q & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) +// \z80_|pla_decode_|Equal33~2_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal33~1_combout )) - .dataa(\z80_|decode_state_|DFFE_instIY1~q ), - .datab(\z80_|decode_state_|DFFE_inst4~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal33~1_combout ), .cin(gnd), - .combout(\z80_|reg_control_|reg_sel_iy~2_combout ), + .combout(\z80_|pla_decode_|Equal33~2_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_control_|reg_sel_iy~2 .lut_mask = 16'h0020; -defparam \z80_|reg_control_|reg_sel_iy~2 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal33~2 .lut_mask = 16'h8800; +defparam \z80_|pla_decode_|Equal33~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y10_N26 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_70 ( +// Location: LCCOMB_X28_Y19_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal21~0 ( // Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_70~combout = (!\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & \z80_|reg_control_|reg_sel_iy~2_combout )) +// \z80_|pla_decode_|Equal21~0_combout = (\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [3]) .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datad(\z80_|reg_control_|reg_sel_iy~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70 .lut_mask = 16'h3000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N16 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout = (\z80_|decode_state_|DFFE_inst4~q & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 .lut_mask = 16'h0080; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y10_N31 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N24 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_71 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_71~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (\z80_|reg_control_|reg_sel_iy~2_combout & \z80_|execute_|ctl_reg_gp_we~6_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datab(\z80_|reg_control_|reg_sel_iy~2_combout ), + .datab(\z80_|ir_|opcode [4]), .datac(gnd), - .datad(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datad(\z80_|ir_|opcode [3]), .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .combout(\z80_|pla_decode_|Equal21~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal21~0 .lut_mask = 16'h00CC; +defparam \z80_|pla_decode_|Equal21~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y10_N15 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~38 ( +// Location: LCCOMB_X25_Y16_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal77~0 ( // Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~38_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) +// \z80_|pla_decode_|Equal77~0_combout = (!\z80_|decode_state_|DFFE_instCB~q & (!\z80_|decode_state_|DFFE_instED~q & (!\z80_|ir_|opcode [7] & \z80_|ir_|opcode [6]))) - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [2]), - .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [2]), + .dataa(\z80_|decode_state_|DFFE_instCB~q ), + .datab(\z80_|decode_state_|DFFE_instED~q ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|ir_|opcode [6]), .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~38_combout ), + .combout(\z80_|pla_decode_|Equal77~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~38 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[2]~38 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal77~0 .lut_mask = 16'h0100; +defparam \z80_|pla_decode_|Equal77~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y10_N10 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_31 ( +// Location: LCCOMB_X28_Y16_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal77~1 ( // Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_31~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_af2~0_combout )) +// \z80_|pla_decode_|Equal77~1_combout = (\z80_|pla_decode_|Equal21~0_combout & (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal77~0_combout ))) - .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datac(gnd), - .datad(\z80_|reg_control_|reg_sel_af2~0_combout ), + .dataa(\z80_|pla_decode_|Equal21~0_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|pla_decode_|Equal77~0_combout ), .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .combout(\z80_|pla_decode_|Equal77~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_31 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_31 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal77~1 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal77~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y10_N23 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N28 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder ( +// Location: LCCOMB_X28_Y13_N26 +cycloneive_lcell_comb \z80_|pla_decode_|Equal1~7 ( // Equation(s): -// \z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp0[2]~42_combout +// \z80_|pla_decode_|Equal1~7_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [6] & (!\z80_|decode_state_|table_xx~0_combout & \z80_|ir_|opcode [7]))) - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [6]), + .datac(\z80_|decode_state_|table_xx~0_combout ), + .datad(\z80_|ir_|opcode [7]), .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder_combout ), + .combout(\z80_|pla_decode_|Equal1~7_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal1~7 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal1~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y14_N8 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_35 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_35~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_af~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_af~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_35 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N29 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~35 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~35_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [2]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [2]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~35 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[2]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~40 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~40_combout = (\z80_|reg_file_|gdfx_temp0[2]~37_combout & (\z80_|reg_file_|gdfx_temp0[2]~39_combout & (\z80_|reg_file_|gdfx_temp0[2]~38_combout & \z80_|reg_file_|gdfx_temp0[2]~35_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[2]~37_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[2]~39_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[2]~38_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[2]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~40 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[2]~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~41 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~41_combout = (\z80_|reg_file_|gdfx_temp0[2]~34_combout & (\z80_|reg_file_|gdfx_temp0[2]~33_combout & \z80_|reg_file_|gdfx_temp0[2]~40_combout )) - - .dataa(\z80_|reg_file_|gdfx_temp0[2]~34_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[2]~33_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[2]~40_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~41 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|gdfx_temp0[2]~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~42 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[2]~42_combout = ((\z80_|reg_file_|gdfx_temp0[2]~41_combout & ((\z80_|reg_file_|db_lo_as[2]~9_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .datac(\z80_|execute_|ctl_sw_4u~6_combout ), - .datad(\z80_|reg_file_|db_lo_as[2]~9_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[2]~42 .lut_mask = 16'hBB3B; -defparam \z80_|reg_file_|gdfx_temp0[2]~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N21 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[2]~9_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N20 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~7 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[2]~7_combout = (\z80_|reg_file_|gdfx_temp0[2]~42_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # (!\z80_|reg_file_|gdfx_temp0[2]~42_combout & -// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .datab(\z80_|execute_|ctl_sw_4d~6_combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[2]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[2]~7 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|db_lo_as[2]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N26 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~8 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[2]~8_combout = (\z80_|reg_file_|db_lo_as[2]~7_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_lo|latch [2]), - .datad(\z80_|reg_file_|db_lo_as[2]~7_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[2]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[2]~8 .lut_mask = 16'hF300; -defparam \z80_|reg_file_|db_lo_as[2]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y17_N9 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[0]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y13_N13 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y13_N19 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~10 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~10_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [0] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [0] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [0]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~10 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[0]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y13_N29 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N28 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]) # (!\z80_|reg_control_|reg_sel_hl2~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~38_combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]), - .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y9_N9 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~11 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~11_combout = (\z80_|reg_file_|gdfx_temp0[0]~10_combout & (\z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0_combout & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[0]~10_combout ), - .datab(\z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_hl_lo|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~11 .lut_mask = 16'h8088; -defparam \z80_|reg_file_|gdfx_temp0[0]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y10_N21 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y10_N19 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~15 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~15_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_sp_lo|latch [0]), - .datac(\z80_|reg_file_|b2v_latch_iy_lo|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~15 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp0[0]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y11_N19 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N30 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder_combout = \z80_|reg_file_|gdfx_temp0[0]~22_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y11_N31 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y11_N1 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~14 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~14_combout = (\z80_|reg_file_|b2v_latch_bc_lo|latch [0] & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # (!\z80_|reg_file_|b2v_latch_bc_lo|latch [0] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc_lo|latch [0]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~14 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[0]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~16 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~16_combout = (\z80_|reg_file_|gdfx_temp0[0]~15_combout & (\z80_|reg_file_|gdfx_temp0[0]~14_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[0]~15_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [0]), - .datad(\z80_|reg_file_|gdfx_temp0[0]~14_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~16 .lut_mask = 16'hA200; -defparam \z80_|reg_file_|gdfx_temp0[0]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y11_N1 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~12 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~12_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [0] & ((\z80_|alu_control_|db[0]~12_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (((\z80_|alu_control_|db[0]~12_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [0]), - .datad(\z80_|alu_control_|db[0]~12_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~12 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[0]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N7 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y10_N13 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~13 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~13_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [0]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [0]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~13 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[0]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~17 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~17_combout = (\z80_|reg_file_|gdfx_temp0[0]~11_combout & (\z80_|reg_file_|gdfx_temp0[0]~16_combout & (\z80_|reg_file_|gdfx_temp0[0]~12_combout & \z80_|reg_file_|gdfx_temp0[0]~13_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[0]~11_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~16_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[0]~12_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[0]~13_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~17 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[0]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~22 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~22_combout = ((\z80_|reg_file_|gdfx_temp0[0]~17_combout & ((\z80_|reg_file_|db_lo_as[0]~3_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~17_combout ), - .datac(\z80_|reg_file_|db_lo_as[0]~3_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~22 .lut_mask = 16'hC4FF; -defparam \z80_|reg_file_|gdfx_temp0[0]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N25 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[0]~3_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N24 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~0 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[0]~0_combout = (\z80_|reg_file_|gdfx_temp0[0]~22_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) # (!\z80_|reg_file_|gdfx_temp0[0]~22_combout & -// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [0]), - .datad(\z80_|execute_|ctl_sw_4d~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[0]~0 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_lo_as[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N22 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~1 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[0]~1_combout = (\z80_|reg_file_|db_lo_as[0]~0_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|b2v_latch_ir_lo|latch [0]), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datad(\z80_|reg_file_|db_lo_as[0]~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[0]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[0]~1 .lut_mask = 16'hCF00; -defparam \z80_|reg_file_|db_lo_as[0]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~72 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~72_combout = (!\z80_|nM1_int~2_combout & (((!\z80_|execute_|ctl_alu_op_low~8_combout & !\z80_|execute_|ixy_d~5_combout )) # (!\z80_|pla_decode_|Equal41~2_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|pla_decode_|Equal41~2_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~72_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~72 .lut_mask = 16'h0515; -defparam \z80_|execute_|ctl_inc_cy~72 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: CLKCTRL_G18 -cycloneive_clkctrl \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl ( - .ena(vcc), - .inclk({vcc,vcc,vcc,\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk [0]}), - .clkselect(2'b00), - .devclrn(devclrn), - .devpor(devpor), - .outclk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk )); -// synopsys translate_off -defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .clock_type = "global clock"; -defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .ena_register_mode = "none"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N16 -cycloneive_lcell_comb \ula_|video_|Add0~14 ( -// Equation(s): -// \ula_|video_|Add0~14_combout = (\ula_|video_|vga_hc [7] & (!\ula_|video_|Add0~13 )) # (!\ula_|video_|vga_hc [7] & ((\ula_|video_|Add0~13 ) # (GND))) -// \ula_|video_|Add0~15 = CARRY((!\ula_|video_|Add0~13 ) # (!\ula_|video_|vga_hc [7])) - - .dataa(gnd), - .datab(\ula_|video_|vga_hc [7]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add0~13 ), - .combout(\ula_|video_|Add0~14_combout ), - .cout(\ula_|video_|Add0~15 )); -// synopsys translate_off -defparam \ula_|video_|Add0~14 .lut_mask = 16'h3C3F; -defparam \ula_|video_|Add0~14 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N18 -cycloneive_lcell_comb \ula_|video_|Add0~16 ( -// Equation(s): -// \ula_|video_|Add0~16_combout = (\ula_|video_|vga_hc [8] & (\ula_|video_|Add0~15 $ (GND))) # (!\ula_|video_|vga_hc [8] & (!\ula_|video_|Add0~15 & VCC)) -// \ula_|video_|Add0~17 = CARRY((\ula_|video_|vga_hc [8] & !\ula_|video_|Add0~15 )) - - .dataa(\ula_|video_|vga_hc [8]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add0~15 ), - .combout(\ula_|video_|Add0~16_combout ), - .cout(\ula_|video_|Add0~17 )); -// synopsys translate_off -defparam \ula_|video_|Add0~16 .lut_mask = 16'hA50A; -defparam \ula_|video_|Add0~16 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N26 -cycloneive_lcell_comb \ula_|video_|vga_hc~2 ( -// Equation(s): -// \ula_|video_|vga_hc~2_combout = (\ula_|video_|Equal1~0_combout & \ula_|video_|Add0~16_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|video_|Equal1~0_combout ), - .datad(\ula_|video_|Add0~16_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_hc~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_hc~2 .lut_mask = 16'hF000; -defparam \ula_|video_|vga_hc~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y33_N27 -dffeas \ula_|video_|vga_hc[8] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_hc~2_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_hc [8]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_hc[8] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_hc[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N20 -cycloneive_lcell_comb \ula_|video_|Add0~18 ( -// Equation(s): -// \ula_|video_|Add0~18_combout = \ula_|video_|Add0~17 $ (\ula_|video_|vga_hc [9]) - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|vga_hc [9]), - .cin(\ula_|video_|Add0~17 ), - .combout(\ula_|video_|Add0~18_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Add0~18 .lut_mask = 16'h0FF0; -defparam \ula_|video_|Add0~18 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y33_N20 -cycloneive_lcell_comb \ula_|video_|vga_hc~1 ( -// Equation(s): -// \ula_|video_|vga_hc~1_combout = (\ula_|video_|Equal1~0_combout & \ula_|video_|Add0~18_combout ) - - .dataa(gnd), - .datab(\ula_|video_|Equal1~0_combout ), - .datac(gnd), - .datad(\ula_|video_|Add0~18_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_hc~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_hc~1 .lut_mask = 16'hCC00; -defparam \ula_|video_|vga_hc~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y33_N21 -dffeas \ula_|video_|vga_hc[9] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_hc~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_hc [9]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_hc[9] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_hc[9] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N2 -cycloneive_lcell_comb \ula_|video_|Add0~0 ( -// Equation(s): -// \ula_|video_|Add0~0_combout = \ula_|video_|vga_hc [0] $ (VCC) -// \ula_|video_|Add0~1 = CARRY(\ula_|video_|vga_hc [0]) - - .dataa(gnd), - .datab(\ula_|video_|vga_hc [0]), - .datac(gnd), - .datad(vcc), - .cin(gnd), - .combout(\ula_|video_|Add0~0_combout ), - .cout(\ula_|video_|Add0~1 )); -// synopsys translate_off -defparam \ula_|video_|Add0~0 .lut_mask = 16'h33CC; -defparam \ula_|video_|Add0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N0 -cycloneive_lcell_comb \ula_|video_|vga_hc~3 ( -// Equation(s): -// \ula_|video_|vga_hc~3_combout = (\ula_|video_|Add0~0_combout & \ula_|video_|Equal1~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|video_|Add0~0_combout ), - .datad(\ula_|video_|Equal1~0_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_hc~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_hc~3 .lut_mask = 16'hF000; -defparam \ula_|video_|vga_hc~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y31_N1 -dffeas \ula_|video_|vga_hc[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_hc~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_hc [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_hc[0] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_hc[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N4 -cycloneive_lcell_comb \ula_|video_|Add0~2 ( -// Equation(s): -// \ula_|video_|Add0~2_combout = (\ula_|video_|vga_hc [1] & (!\ula_|video_|Add0~1 )) # (!\ula_|video_|vga_hc [1] & ((\ula_|video_|Add0~1 ) # (GND))) -// \ula_|video_|Add0~3 = CARRY((!\ula_|video_|Add0~1 ) # (!\ula_|video_|vga_hc [1])) - - .dataa(gnd), - .datab(\ula_|video_|vga_hc [1]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add0~1 ), - .combout(\ula_|video_|Add0~2_combout ), - .cout(\ula_|video_|Add0~3 )); -// synopsys translate_off -defparam \ula_|video_|Add0~2 .lut_mask = 16'h3C3F; -defparam \ula_|video_|Add0~2 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y33_N16 -cycloneive_lcell_comb \ula_|video_|vga_hc[1]~feeder ( -// Equation(s): -// \ula_|video_|vga_hc[1]~feeder_combout = \ula_|video_|Add0~2_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|Add0~2_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_hc[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_hc[1]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|vga_hc[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y33_N17 -dffeas \ula_|video_|vga_hc[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_hc[1]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_hc [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_hc[1] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_hc[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N6 -cycloneive_lcell_comb \ula_|video_|Add0~4 ( -// Equation(s): -// \ula_|video_|Add0~4_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|Add0~3 $ (GND))) # (!\ula_|video_|vga_hc [2] & (!\ula_|video_|Add0~3 & VCC)) -// \ula_|video_|Add0~5 = CARRY((\ula_|video_|vga_hc [2] & !\ula_|video_|Add0~3 )) - - .dataa(gnd), - .datab(\ula_|video_|vga_hc [2]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add0~3 ), - .combout(\ula_|video_|Add0~4_combout ), - .cout(\ula_|video_|Add0~5 )); -// synopsys translate_off -defparam \ula_|video_|Add0~4 .lut_mask = 16'hC30C; -defparam \ula_|video_|Add0~4 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y33_N23 -dffeas \ula_|video_|vga_hc[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|Add0~4_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_hc [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_hc[2] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_hc[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N8 -cycloneive_lcell_comb \ula_|video_|Add0~6 ( -// Equation(s): -// \ula_|video_|Add0~6_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|Add0~5 )) # (!\ula_|video_|vga_hc [3] & ((\ula_|video_|Add0~5 ) # (GND))) -// \ula_|video_|Add0~7 = CARRY((!\ula_|video_|Add0~5 ) # (!\ula_|video_|vga_hc [3])) - - .dataa(gnd), - .datab(\ula_|video_|vga_hc [3]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add0~5 ), - .combout(\ula_|video_|Add0~6_combout ), - .cout(\ula_|video_|Add0~7 )); -// synopsys translate_off -defparam \ula_|video_|Add0~6 .lut_mask = 16'h3C3F; -defparam \ula_|video_|Add0~6 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y33_N8 -cycloneive_lcell_comb \ula_|video_|vga_hc[3]~feeder ( -// Equation(s): -// \ula_|video_|vga_hc[3]~feeder_combout = \ula_|video_|Add0~6_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|Add0~6_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_hc[3]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_hc[3]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|vga_hc[3]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y33_N9 -dffeas \ula_|video_|vga_hc[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_hc[3]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_hc [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_hc[3] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_hc[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N10 -cycloneive_lcell_comb \ula_|video_|Add0~8 ( -// Equation(s): -// \ula_|video_|Add0~8_combout = (\ula_|video_|vga_hc [4] & (\ula_|video_|Add0~7 $ (GND))) # (!\ula_|video_|vga_hc [4] & (!\ula_|video_|Add0~7 & VCC)) -// \ula_|video_|Add0~9 = CARRY((\ula_|video_|vga_hc [4] & !\ula_|video_|Add0~7 )) - - .dataa(\ula_|video_|vga_hc [4]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add0~7 ), - .combout(\ula_|video_|Add0~8_combout ), - .cout(\ula_|video_|Add0~9 )); -// synopsys translate_off -defparam \ula_|video_|Add0~8 .lut_mask = 16'hA50A; -defparam \ula_|video_|Add0~8 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y33_N31 -dffeas \ula_|video_|vga_hc[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|Add0~8_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_hc [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_hc[4] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_hc[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N18 -cycloneive_lcell_comb \ula_|video_|Equal0~0 ( -// Equation(s): -// \ula_|video_|Equal0~0_combout = (!\ula_|video_|vga_hc [2] & (!\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [1] & !\ula_|video_|vga_hc [0]))) - - .dataa(\ula_|video_|vga_hc [2]), - .datab(\ula_|video_|vga_hc [3]), - .datac(\ula_|video_|vga_hc [1]), - .datad(\ula_|video_|vga_hc [0]), - .cin(gnd), - .combout(\ula_|video_|Equal0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Equal0~0 .lut_mask = 16'h0001; -defparam \ula_|video_|Equal0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N30 -cycloneive_lcell_comb \ula_|video_|Equal0~1 ( -// Equation(s): -// \ula_|video_|Equal0~1_combout = (\ula_|video_|vga_hc [5] & (!\ula_|video_|vga_hc [7] & (!\ula_|video_|vga_hc [4] & \ula_|video_|Equal0~0_combout ))) - - .dataa(\ula_|video_|vga_hc [5]), - .datab(\ula_|video_|vga_hc [7]), - .datac(\ula_|video_|vga_hc [4]), - .datad(\ula_|video_|Equal0~0_combout ), - .cin(gnd), - .combout(\ula_|video_|Equal0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Equal0~1 .lut_mask = 16'h0200; -defparam \ula_|video_|Equal0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y33_N16 -cycloneive_lcell_comb \ula_|video_|Equal1~0 ( -// Equation(s): -// \ula_|video_|Equal1~0_combout = (((\ula_|video_|vga_hc [6]) # (!\ula_|video_|Equal0~1_combout )) # (!\ula_|video_|vga_hc [8])) # (!\ula_|video_|vga_hc [9]) - - .dataa(\ula_|video_|vga_hc [9]), - .datab(\ula_|video_|vga_hc [8]), - .datac(\ula_|video_|vga_hc [6]), - .datad(\ula_|video_|Equal0~1_combout ), - .cin(gnd), - .combout(\ula_|video_|Equal1~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Equal1~0 .lut_mask = 16'hF7FF; -defparam \ula_|video_|Equal1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N12 -cycloneive_lcell_comb \ula_|video_|Add0~10 ( -// Equation(s): -// \ula_|video_|Add0~10_combout = (\ula_|video_|vga_hc [5] & (!\ula_|video_|Add0~9 )) # (!\ula_|video_|vga_hc [5] & ((\ula_|video_|Add0~9 ) # (GND))) -// \ula_|video_|Add0~11 = CARRY((!\ula_|video_|Add0~9 ) # (!\ula_|video_|vga_hc [5])) - - .dataa(\ula_|video_|vga_hc [5]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add0~9 ), - .combout(\ula_|video_|Add0~10_combout ), - .cout(\ula_|video_|Add0~11 )); -// synopsys translate_off -defparam \ula_|video_|Add0~10 .lut_mask = 16'h5A5F; -defparam \ula_|video_|Add0~10 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N0 -cycloneive_lcell_comb \ula_|video_|vga_hc~0 ( -// Equation(s): -// \ula_|video_|vga_hc~0_combout = (\ula_|video_|Equal1~0_combout & \ula_|video_|Add0~10_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|video_|Equal1~0_combout ), - .datad(\ula_|video_|Add0~10_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_hc~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_hc~0 .lut_mask = 16'hF000; -defparam \ula_|video_|vga_hc~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y33_N1 -dffeas \ula_|video_|vga_hc[5] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_hc~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_hc [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_hc[5] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_hc[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N14 -cycloneive_lcell_comb \ula_|video_|Add0~12 ( -// Equation(s): -// \ula_|video_|Add0~12_combout = (\ula_|video_|vga_hc [6] & (\ula_|video_|Add0~11 $ (GND))) # (!\ula_|video_|vga_hc [6] & (!\ula_|video_|Add0~11 & VCC)) -// \ula_|video_|Add0~13 = CARRY((\ula_|video_|vga_hc [6] & !\ula_|video_|Add0~11 )) - - .dataa(\ula_|video_|vga_hc [6]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add0~11 ), - .combout(\ula_|video_|Add0~12_combout ), - .cout(\ula_|video_|Add0~13 )); -// synopsys translate_off -defparam \ula_|video_|Add0~12 .lut_mask = 16'hA50A; -defparam \ula_|video_|Add0~12 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y33_N29 -dffeas \ula_|video_|vga_hc[6] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|Add0~12_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_hc [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_hc[6] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_hc[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X39_Y33_N25 -dffeas \ula_|video_|vga_hc[7] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|Add0~14_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_hc [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_hc[7] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_hc[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y33_N0 -cycloneive_lcell_comb \ula_|video_|Add1~0 ( -// Equation(s): -// \ula_|video_|Add1~0_combout = \ula_|video_|vga_vc [0] $ (VCC) -// \ula_|video_|Add1~1 = CARRY(\ula_|video_|vga_vc [0]) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [0]), - .datac(gnd), - .datad(vcc), - .cin(gnd), - .combout(\ula_|video_|Add1~0_combout ), - .cout(\ula_|video_|Add1~1 )); -// synopsys translate_off -defparam \ula_|video_|Add1~0 .lut_mask = 16'h33CC; -defparam \ula_|video_|Add1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y33_N2 -cycloneive_lcell_comb \ula_|video_|Add1~2 ( -// Equation(s): -// \ula_|video_|Add1~2_combout = (\ula_|video_|vga_vc [1] & (!\ula_|video_|Add1~1 )) # (!\ula_|video_|vga_vc [1] & ((\ula_|video_|Add1~1 ) # (GND))) -// \ula_|video_|Add1~3 = CARRY((!\ula_|video_|Add1~1 ) # (!\ula_|video_|vga_vc [1])) - - .dataa(\ula_|video_|vga_vc [1]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add1~1 ), - .combout(\ula_|video_|Add1~2_combout ), - .cout(\ula_|video_|Add1~3 )); -// synopsys translate_off -defparam \ula_|video_|Add1~2 .lut_mask = 16'h5A5F; -defparam \ula_|video_|Add1~2 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y33_N4 -cycloneive_lcell_comb \ula_|video_|Add1~4 ( -// Equation(s): -// \ula_|video_|Add1~4_combout = (\ula_|video_|vga_vc [2] & (\ula_|video_|Add1~3 $ (GND))) # (!\ula_|video_|vga_vc [2] & (!\ula_|video_|Add1~3 & VCC)) -// \ula_|video_|Add1~5 = CARRY((\ula_|video_|vga_vc [2] & !\ula_|video_|Add1~3 )) - - .dataa(\ula_|video_|vga_vc [2]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add1~3 ), - .combout(\ula_|video_|Add1~4_combout ), - .cout(\ula_|video_|Add1~5 )); -// synopsys translate_off -defparam \ula_|video_|Add1~4 .lut_mask = 16'hA50A; -defparam \ula_|video_|Add1~4 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N12 -cycloneive_lcell_comb \ula_|video_|vga_vc[2]~2 ( -// Equation(s): -// \ula_|video_|vga_vc[2]~2_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [2]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~4_combout )))) - - .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Add1~4_combout ), - .datac(\ula_|video_|vga_vc [2]), - .datad(\ula_|video_|Equal3~1_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[2]~2 .lut_mask = 16'h00E4; -defparam \ula_|video_|vga_vc[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y33_N13 -dffeas \ula_|video_|vga_vc[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[2]~2_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[2] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y33_N6 -cycloneive_lcell_comb \ula_|video_|Add1~6 ( -// Equation(s): -// \ula_|video_|Add1~6_combout = (\ula_|video_|vga_vc [3] & (!\ula_|video_|Add1~5 )) # (!\ula_|video_|vga_vc [3] & ((\ula_|video_|Add1~5 ) # (GND))) -// \ula_|video_|Add1~7 = CARRY((!\ula_|video_|Add1~5 ) # (!\ula_|video_|vga_vc [3])) - - .dataa(\ula_|video_|vga_vc [3]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add1~5 ), - .combout(\ula_|video_|Add1~6_combout ), - .cout(\ula_|video_|Add1~7 )); -// synopsys translate_off -defparam \ula_|video_|Add1~6 .lut_mask = 16'h5A5F; -defparam \ula_|video_|Add1~6 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y33_N20 -cycloneive_lcell_comb \ula_|video_|vga_vc[3]~3 ( -// Equation(s): -// \ula_|video_|vga_vc[3]~3_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [3])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~6_combout ))))) - - .dataa(\ula_|video_|Equal3~1_combout ), - .datab(\ula_|video_|Equal1~0_combout ), - .datac(\ula_|video_|vga_vc [3]), - .datad(\ula_|video_|Add1~6_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[3]~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[3]~3 .lut_mask = 16'h5140; -defparam \ula_|video_|vga_vc[3]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y33_N3 -dffeas \ula_|video_|vga_vc[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|vga_vc[3]~3_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[3] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y33_N8 -cycloneive_lcell_comb \ula_|video_|Add1~8 ( -// Equation(s): -// \ula_|video_|Add1~8_combout = (\ula_|video_|vga_vc [4] & (\ula_|video_|Add1~7 $ (GND))) # (!\ula_|video_|vga_vc [4] & (!\ula_|video_|Add1~7 & VCC)) -// \ula_|video_|Add1~9 = CARRY((\ula_|video_|vga_vc [4] & !\ula_|video_|Add1~7 )) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [4]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add1~7 ), - .combout(\ula_|video_|Add1~8_combout ), - .cout(\ula_|video_|Add1~9 )); -// synopsys translate_off -defparam \ula_|video_|Add1~8 .lut_mask = 16'hC30C; -defparam \ula_|video_|Add1~8 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N20 -cycloneive_lcell_comb \ula_|video_|vga_vc[4]~5 ( -// Equation(s): -// \ula_|video_|vga_vc[4]~5_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [4]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~8_combout )))) - - .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Add1~8_combout ), - .datac(\ula_|video_|vga_vc [4]), - .datad(\ula_|video_|Equal3~1_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[4]~5_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[4]~5 .lut_mask = 16'h00E4; -defparam \ula_|video_|vga_vc[4]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y33_N21 -dffeas \ula_|video_|vga_vc[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[4]~5_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[4] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y33_N10 -cycloneive_lcell_comb \ula_|video_|Add1~10 ( -// Equation(s): -// \ula_|video_|Add1~10_combout = (\ula_|video_|vga_vc [5] & (!\ula_|video_|Add1~9 )) # (!\ula_|video_|vga_vc [5] & ((\ula_|video_|Add1~9 ) # (GND))) -// \ula_|video_|Add1~11 = CARRY((!\ula_|video_|Add1~9 ) # (!\ula_|video_|vga_vc [5])) - - .dataa(\ula_|video_|vga_vc [5]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add1~9 ), - .combout(\ula_|video_|Add1~10_combout ), - .cout(\ula_|video_|Add1~11 )); -// synopsys translate_off -defparam \ula_|video_|Add1~10 .lut_mask = 16'h5A5F; -defparam \ula_|video_|Add1~10 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y33_N22 -cycloneive_lcell_comb \ula_|video_|vga_vc[5]~8 ( -// Equation(s): -// \ula_|video_|vga_vc[5]~8_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [5])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~10_combout ))))) - - .dataa(\ula_|video_|Equal3~1_combout ), - .datab(\ula_|video_|Equal1~0_combout ), - .datac(\ula_|video_|vga_vc [5]), - .datad(\ula_|video_|Add1~10_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[5]~8_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[5]~8 .lut_mask = 16'h5140; -defparam \ula_|video_|vga_vc[5]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y33_N17 -dffeas \ula_|video_|vga_vc[5] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|vga_vc[5]~8_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[5] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y33_N12 -cycloneive_lcell_comb \ula_|video_|Add1~12 ( -// Equation(s): -// \ula_|video_|Add1~12_combout = (\ula_|video_|vga_vc [6] & (\ula_|video_|Add1~11 $ (GND))) # (!\ula_|video_|vga_vc [6] & (!\ula_|video_|Add1~11 & VCC)) -// \ula_|video_|Add1~13 = CARRY((\ula_|video_|vga_vc [6] & !\ula_|video_|Add1~11 )) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [6]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add1~11 ), - .combout(\ula_|video_|Add1~12_combout ), - .cout(\ula_|video_|Add1~13 )); -// synopsys translate_off -defparam \ula_|video_|Add1~12 .lut_mask = 16'hC30C; -defparam \ula_|video_|Add1~12 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N6 -cycloneive_lcell_comb \ula_|video_|vga_vc[6]~4 ( -// Equation(s): -// \ula_|video_|vga_vc[6]~4_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [6]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~12_combout )))) - - .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Add1~12_combout ), - .datac(\ula_|video_|vga_vc [6]), - .datad(\ula_|video_|Equal3~1_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[6]~4_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[6]~4 .lut_mask = 16'h00E4; -defparam \ula_|video_|vga_vc[6]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y33_N7 -dffeas \ula_|video_|vga_vc[6] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[6]~4_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[6] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y33_N14 -cycloneive_lcell_comb \ula_|video_|Add1~14 ( -// Equation(s): -// \ula_|video_|Add1~14_combout = (\ula_|video_|vga_vc [7] & (!\ula_|video_|Add1~13 )) # (!\ula_|video_|vga_vc [7] & ((\ula_|video_|Add1~13 ) # (GND))) -// \ula_|video_|Add1~15 = CARRY((!\ula_|video_|Add1~13 ) # (!\ula_|video_|vga_vc [7])) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [7]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add1~13 ), - .combout(\ula_|video_|Add1~14_combout ), - .cout(\ula_|video_|Add1~15 )); -// synopsys translate_off -defparam \ula_|video_|Add1~14 .lut_mask = 16'h3C3F; -defparam \ula_|video_|Add1~14 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N14 -cycloneive_lcell_comb \ula_|video_|vga_vc[7]~6 ( -// Equation(s): -// \ula_|video_|vga_vc[7]~6_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [7]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~14_combout )))) - - .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Add1~14_combout ), - .datac(\ula_|video_|vga_vc [7]), - .datad(\ula_|video_|Equal3~1_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[7]~6_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[7]~6 .lut_mask = 16'h00E4; -defparam \ula_|video_|vga_vc[7]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y33_N15 -dffeas \ula_|video_|vga_vc[7] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[7]~6_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[7] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y33_N16 -cycloneive_lcell_comb \ula_|video_|Add1~16 ( -// Equation(s): -// \ula_|video_|Add1~16_combout = (\ula_|video_|vga_vc [8] & (\ula_|video_|Add1~15 $ (GND))) # (!\ula_|video_|vga_vc [8] & (!\ula_|video_|Add1~15 & VCC)) -// \ula_|video_|Add1~17 = CARRY((\ula_|video_|vga_vc [8] & !\ula_|video_|Add1~15 )) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [8]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add1~15 ), - .combout(\ula_|video_|Add1~16_combout ), - .cout(\ula_|video_|Add1~17 )); -// synopsys translate_off -defparam \ula_|video_|Add1~16 .lut_mask = 16'hC30C; -defparam \ula_|video_|Add1~16 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N24 -cycloneive_lcell_comb \ula_|video_|vga_vc[8]~7 ( -// Equation(s): -// \ula_|video_|vga_vc[8]~7_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [8]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~16_combout )))) - - .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Add1~16_combout ), - .datac(\ula_|video_|vga_vc [8]), - .datad(\ula_|video_|Equal3~1_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[8]~7_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[8]~7 .lut_mask = 16'h00E4; -defparam \ula_|video_|vga_vc[8]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y33_N25 -dffeas \ula_|video_|vga_vc[8] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[8]~7_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [8]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[8] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y33_N18 -cycloneive_lcell_comb \ula_|video_|Add1~18 ( -// Equation(s): -// \ula_|video_|Add1~18_combout = \ula_|video_|Add1~17 $ (\ula_|video_|vga_vc [9]) - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|vga_vc [9]), - .cin(\ula_|video_|Add1~17 ), - .combout(\ula_|video_|Add1~18_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Add1~18 .lut_mask = 16'h0FF0; -defparam \ula_|video_|Add1~18 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N10 -cycloneive_lcell_comb \ula_|video_|vga_vc[9]~9 ( -// Equation(s): -// \ula_|video_|vga_vc[9]~9_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [9]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~18_combout )))) - - .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Add1~18_combout ), - .datac(\ula_|video_|vga_vc [9]), - .datad(\ula_|video_|Equal3~1_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[9]~9_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[9]~9 .lut_mask = 16'h00E4; -defparam \ula_|video_|vga_vc[9]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y33_N11 -dffeas \ula_|video_|vga_vc[9] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[9]~9_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [9]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[9] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[9] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N18 -cycloneive_lcell_comb \ula_|video_|Equal2~0 ( -// Equation(s): -// \ula_|video_|Equal2~0_combout = (!\ula_|video_|vga_vc [6] & (!\ula_|video_|vga_vc [4] & (!\ula_|video_|vga_vc [7] & !\ula_|video_|vga_vc [8]))) - - .dataa(\ula_|video_|vga_vc [6]), - .datab(\ula_|video_|vga_vc [4]), - .datac(\ula_|video_|vga_vc [7]), - .datad(\ula_|video_|vga_vc [8]), - .cin(gnd), - .combout(\ula_|video_|Equal2~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Equal2~0 .lut_mask = 16'h0001; -defparam \ula_|video_|Equal2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y33_N30 -cycloneive_lcell_comb \ula_|video_|Equal3~0 ( -// Equation(s): -// \ula_|video_|Equal3~0_combout = (\ula_|video_|vga_vc [3] & (\ula_|video_|vga_vc [2] & (!\ula_|video_|vga_vc [1] & \ula_|video_|vga_vc [0]))) - - .dataa(\ula_|video_|vga_vc [3]), - .datab(\ula_|video_|vga_vc [2]), - .datac(\ula_|video_|vga_vc [1]), - .datad(\ula_|video_|vga_vc [0]), - .cin(gnd), - .combout(\ula_|video_|Equal3~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Equal3~0 .lut_mask = 16'h0800; -defparam \ula_|video_|Equal3~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y33_N18 -cycloneive_lcell_comb \ula_|video_|Equal3~1 ( -// Equation(s): -// \ula_|video_|Equal3~1_combout = (!\ula_|video_|vga_vc [5] & (\ula_|video_|vga_vc [9] & (\ula_|video_|Equal2~0_combout & \ula_|video_|Equal3~0_combout ))) - - .dataa(\ula_|video_|vga_vc [5]), - .datab(\ula_|video_|vga_vc [9]), - .datac(\ula_|video_|Equal2~0_combout ), - .datad(\ula_|video_|Equal3~0_combout ), - .cin(gnd), - .combout(\ula_|video_|Equal3~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Equal3~1 .lut_mask = 16'h4000; -defparam \ula_|video_|Equal3~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N28 -cycloneive_lcell_comb \ula_|video_|vga_vc[0]~0 ( -// Equation(s): -// \ula_|video_|vga_vc[0]~0_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [0]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~0_combout )))) - - .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Add1~0_combout ), - .datac(\ula_|video_|vga_vc [0]), - .datad(\ula_|video_|Equal3~1_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[0]~0 .lut_mask = 16'h00E4; -defparam \ula_|video_|vga_vc[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y33_N29 -dffeas \ula_|video_|vga_vc[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[0]~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[0] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y33_N22 -cycloneive_lcell_comb \ula_|video_|vga_vc[1]~1 ( -// Equation(s): -// \ula_|video_|vga_vc[1]~1_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [1]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~2_combout )))) - - .dataa(\ula_|video_|Equal1~0_combout ), - .datab(\ula_|video_|Add1~2_combout ), - .datac(\ula_|video_|vga_vc [1]), - .datad(\ula_|video_|Equal3~1_combout ), - .cin(gnd), - .combout(\ula_|video_|vga_vc[1]~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vga_vc[1]~1 .lut_mask = 16'h00E4; -defparam \ula_|video_|vga_vc[1]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y33_N23 -dffeas \ula_|video_|vga_vc[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vga_vc[1]~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vga_vc [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vga_vc[1] .is_wysiwyg = "true"; -defparam \ula_|video_|vga_vc[1] .power_up = "low"; -// synopsys translate_on - -// Location: IOIBUF_X27_Y0_N15 -cycloneive_io_ibuf \SW[1]~input ( - .i(SW[1]), - .ibar(gnd), - .o(\SW[1]~input_o )); -// synopsys translate_off -defparam \SW[1]~input .bus_hold = "false"; -defparam \SW[1]~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N30 -cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_13~0 ( -// Equation(s): -// \z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout = (!\ula_|video_|vga_hc [8] & (!\ula_|video_|vga_vc [1] & (!\SW[1]~input_o & !\ula_|video_|vga_hc [9]))) - - .dataa(\ula_|video_|vga_hc [8]), - .datab(\ula_|video_|vga_vc [1]), - .datac(\SW[1]~input_o ), - .datad(\ula_|video_|vga_hc [9]), - .cin(gnd), - .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13~0 .lut_mask = 16'h0001; -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N30 +// Location: LCCOMB_X29_Y17_N26 cycloneive_lcell_comb \z80_|pla_decode_|Equal79~0 ( // Equation(s): -// \z80_|pla_decode_|Equal79~0_combout = (\z80_|pla_decode_|Equal1~7_combout & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4]))) +// \z80_|pla_decode_|Equal79~0_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal1~7_combout & \z80_|ir_|opcode [4]))) - .dataa(\z80_|pla_decode_|Equal1~7_combout ), + .dataa(\z80_|ir_|opcode [5]), .datab(\z80_|pla_decode_|Equal2~0_combout ), - .datac(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal1~7_combout ), .datad(\z80_|ir_|opcode [4]), .cin(gnd), .combout(\z80_|pla_decode_|Equal79~0_combout ), @@ -18903,38 +4790,56 @@ defparam \z80_|pla_decode_|Equal79~0 .lut_mask = 16'h8000; defparam \z80_|pla_decode_|Equal79~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y17_N16 +// Location: LCCOMB_X29_Y17_N12 +cycloneive_lcell_comb \z80_|interrupts_|iff1~0 ( +// Equation(s): +// \z80_|interrupts_|iff1~0_combout = (\z80_|pla_decode_|Equal79~0_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|ir_|opcode [3]))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|interrupts_|iff1~q )))) # +// (!\z80_|pla_decode_|Equal79~0_combout & (((\z80_|interrupts_|iff1~q )))) + + .dataa(\z80_|pla_decode_|Equal79~0_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|interrupts_|iff1~q ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|interrupts_|iff1~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|iff1~0 .lut_mask = 16'hF870; +defparam \z80_|interrupts_|iff1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N30 cycloneive_lcell_comb \z80_|interrupts_|DFFE_instIFF2~0 ( // Equation(s): -// \z80_|interrupts_|DFFE_instIFF2~0_combout = (\z80_|pla_decode_|Equal79~0_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|ir_|opcode [3])) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|interrupts_|DFFE_instIFF2~q -// ))))) # (!\z80_|pla_decode_|Equal79~0_combout & (((\z80_|interrupts_|DFFE_instIFF2~q )))) +// \z80_|interrupts_|DFFE_instIFF2~0_combout = (\z80_|pla_decode_|Equal79~0_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|ir_|opcode [3]))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|interrupts_|DFFE_instIFF2~q +// )))) # (!\z80_|pla_decode_|Equal79~0_combout & (((\z80_|interrupts_|DFFE_instIFF2~q )))) - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal79~0_combout ), + .dataa(\z80_|pla_decode_|Equal79~0_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), .datac(\z80_|interrupts_|DFFE_instIFF2~q ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|ir_|opcode [3]), .cin(gnd), .combout(\z80_|interrupts_|DFFE_instIFF2~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|interrupts_|DFFE_instIFF2~0 .lut_mask = 16'hB8F0; +defparam \z80_|interrupts_|DFFE_instIFF2~0 .lut_mask = 16'hF870; defparam \z80_|interrupts_|DFFE_instIFF2~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y15_N28 +// Location: LCCOMB_X27_Y11_N24 cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_12 ( // Equation(s): -// \z80_|interrupts_|SYNTHESIZED_WIRE_12~combout = ((!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & \z80_|interrupts_|DFFE_inst44~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) +// \z80_|interrupts_|SYNTHESIZED_WIRE_12~combout = ((\z80_|interrupts_|DFFE_inst44~q & !\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|interrupts_|DFFE_inst44~q ), .datac(gnd), - .datad(\z80_|interrupts_|DFFE_inst44~q ), + .datad(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), .cin(gnd), .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_12~combout ), .cout()); // synopsys translate_off -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12 .lut_mask = 16'h7733; +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12 .lut_mask = 16'h55DD; defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12 .sum_lutc_input = "datac"; // synopsys translate_on @@ -18951,7 +4856,7 @@ defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl .clock_type = "global clo defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: FF_X35_Y17_N17 +// Location: FF_X29_Y17_N31 dffeas \z80_|interrupts_|DFFE_instIFF2 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|interrupts_|DFFE_instIFF2~0_combout ), @@ -18970,60 +4875,76 @@ defparam \z80_|interrupts_|DFFE_instIFF2 .is_wysiwyg = "true"; defparam \z80_|interrupts_|DFFE_instIFF2 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X35_Y17_N2 -cycloneive_lcell_comb \z80_|interrupts_|iff1~0 ( +// Location: LCCOMB_X29_Y13_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal13~0 ( // Equation(s): -// \z80_|interrupts_|iff1~0_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|pla_decode_|Equal79~0_combout & ((\z80_|ir_|opcode [3]))) # (!\z80_|pla_decode_|Equal79~0_combout & (\z80_|interrupts_|iff1~q )))) # -// (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|interrupts_|iff1~q )) +// \z80_|pla_decode_|Equal13~0_combout = (\z80_|decode_state_|DFFE_instED~q & (!\z80_|ir_|opcode [7] & \z80_|ir_|opcode [6])) - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|interrupts_|iff1~q ), - .datac(\z80_|pla_decode_|Equal79~0_combout ), - .datad(\z80_|ir_|opcode [3]), + .dataa(\z80_|decode_state_|DFFE_instED~q ), + .datab(gnd), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|ir_|opcode [6]), .cin(gnd), - .combout(\z80_|interrupts_|iff1~0_combout ), + .combout(\z80_|pla_decode_|Equal13~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|interrupts_|iff1~0 .lut_mask = 16'hEC4C; -defparam \z80_|interrupts_|iff1~0 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal13~0 .lut_mask = 16'h0A00; +defparam \z80_|pla_decode_|Equal13~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y17_N18 +// Location: LCCOMB_X21_Y16_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal38~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal38~2_combout = (\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [1] & \z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal38~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal38~2 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal38~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N0 cycloneive_lcell_comb \z80_|interrupts_|iff1~1 ( // Equation(s): -// \z80_|interrupts_|iff1~1_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|pla_decode_|Equal38~2_combout & (\z80_|interrupts_|DFFE_instIFF2~q )) # (!\z80_|pla_decode_|Equal38~2_combout & ((\z80_|interrupts_|iff1~0_combout ))))) # -// (!\z80_|execute_|ctl_eval_cond~0_combout & (((\z80_|interrupts_|iff1~0_combout )))) +// \z80_|interrupts_|iff1~1_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|pla_decode_|Equal38~2_combout & ((\z80_|interrupts_|DFFE_instIFF2~q ))) # (!\z80_|pla_decode_|Equal38~2_combout & (\z80_|interrupts_|iff1~0_combout )))) # +// (!\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|interrupts_|iff1~0_combout )) - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|interrupts_|DFFE_instIFF2~q ), - .datac(\z80_|pla_decode_|Equal38~2_combout ), - .datad(\z80_|interrupts_|iff1~0_combout ), + .dataa(\z80_|interrupts_|iff1~0_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|interrupts_|DFFE_instIFF2~q ), + .datad(\z80_|pla_decode_|Equal38~2_combout ), .cin(gnd), .combout(\z80_|interrupts_|iff1~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|interrupts_|iff1~1 .lut_mask = 16'hDF80; +defparam \z80_|interrupts_|iff1~1 .lut_mask = 16'hE2AA; defparam \z80_|interrupts_|iff1~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y18_N12 +// Location: LCCOMB_X28_Y13_N20 cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_15 ( // Equation(s): -// \z80_|interrupts_|SYNTHESIZED_WIRE_15~combout = ((\z80_|interrupts_|DFFE_inst44~q ) # (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) +// \z80_|interrupts_|SYNTHESIZED_WIRE_15~combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # ((\z80_|interrupts_|DFFE_inst44~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(gnd), .datac(\z80_|interrupts_|DFFE_inst44~q ), - .datad(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .cin(gnd), .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_15~combout ), .cout()); // synopsys translate_off -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_15 .lut_mask = 16'hFFF3; +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_15 .lut_mask = 16'hFAFF; defparam \z80_|interrupts_|SYNTHESIZED_WIRE_15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X35_Y17_N19 +// Location: FF_X29_Y17_N1 dffeas \z80_|interrupts_|iff1 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|interrupts_|iff1~1_combout ), @@ -19042,14 +4963,1122 @@ defparam \z80_|interrupts_|iff1 .is_wysiwyg = "true"; defparam \z80_|interrupts_|iff1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X37_Y33_N4 -cycloneive_lcell_comb \ula_|video_|Equal2~1 ( +// Location: CLKCTRL_G18 +cycloneive_clkctrl \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk [0]}), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk )); +// synopsys translate_off +defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .clock_type = "global clock"; +defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y32_N6 +cycloneive_lcell_comb \ula_|video_|Add0~0 ( // Equation(s): -// \ula_|video_|Equal2~1_combout = (!\ula_|video_|vga_vc [3] & (!\ula_|video_|vga_vc [2] & (!\ula_|video_|vga_vc [9] & !\ula_|video_|vga_vc [0]))) +// \ula_|video_|Add0~0_combout = \ula_|video_|vga_hc [0] $ (VCC) +// \ula_|video_|Add0~1 = CARRY(\ula_|video_|vga_hc [0]) + + .dataa(gnd), + .datab(\ula_|video_|vga_hc [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\ula_|video_|Add0~0_combout ), + .cout(\ula_|video_|Add0~1 )); +// synopsys translate_off +defparam \ula_|video_|Add0~0 .lut_mask = 16'h33CC; +defparam \ula_|video_|Add0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y32_N28 +cycloneive_lcell_comb \ula_|video_|vga_hc~3 ( +// Equation(s): +// \ula_|video_|vga_hc~3_combout = (\ula_|video_|Add0~0_combout & \ula_|video_|Equal1~0_combout ) + + .dataa(gnd), + .datab(\ula_|video_|Add0~0_combout ), + .datac(gnd), + .datad(\ula_|video_|Equal1~0_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_hc~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_hc~3 .lut_mask = 16'hCC00; +defparam \ula_|video_|vga_hc~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y32_N13 +dffeas \ula_|video_|vga_hc[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|vga_hc~3_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_hc [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_hc[0] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_hc[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y32_N8 +cycloneive_lcell_comb \ula_|video_|Add0~2 ( +// Equation(s): +// \ula_|video_|Add0~2_combout = (\ula_|video_|vga_hc [1] & (!\ula_|video_|Add0~1 )) # (!\ula_|video_|vga_hc [1] & ((\ula_|video_|Add0~1 ) # (GND))) +// \ula_|video_|Add0~3 = CARRY((!\ula_|video_|Add0~1 ) # (!\ula_|video_|vga_hc [1])) + + .dataa(gnd), + .datab(\ula_|video_|vga_hc [1]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add0~1 ), + .combout(\ula_|video_|Add0~2_combout ), + .cout(\ula_|video_|Add0~3 )); +// synopsys translate_off +defparam \ula_|video_|Add0~2 .lut_mask = 16'h3C3F; +defparam \ula_|video_|Add0~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X35_Y32_N25 +dffeas \ula_|video_|vga_hc[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|Add0~2_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_hc [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_hc[1] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_hc[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y32_N10 +cycloneive_lcell_comb \ula_|video_|Add0~4 ( +// Equation(s): +// \ula_|video_|Add0~4_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|Add0~3 $ (GND))) # (!\ula_|video_|vga_hc [2] & (!\ula_|video_|Add0~3 & VCC)) +// \ula_|video_|Add0~5 = CARRY((\ula_|video_|vga_hc [2] & !\ula_|video_|Add0~3 )) + + .dataa(gnd), + .datab(\ula_|video_|vga_hc [2]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add0~3 ), + .combout(\ula_|video_|Add0~4_combout ), + .cout(\ula_|video_|Add0~5 )); +// synopsys translate_off +defparam \ula_|video_|Add0~4 .lut_mask = 16'hC30C; +defparam \ula_|video_|Add0~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X35_Y32_N3 +dffeas \ula_|video_|vga_hc[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|Add0~4_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_hc [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_hc[2] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_hc[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y32_N12 +cycloneive_lcell_comb \ula_|video_|Add0~6 ( +// Equation(s): +// \ula_|video_|Add0~6_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|Add0~5 )) # (!\ula_|video_|vga_hc [3] & ((\ula_|video_|Add0~5 ) # (GND))) +// \ula_|video_|Add0~7 = CARRY((!\ula_|video_|Add0~5 ) # (!\ula_|video_|vga_hc [3])) + + .dataa(\ula_|video_|vga_hc [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add0~5 ), + .combout(\ula_|video_|Add0~6_combout ), + .cout(\ula_|video_|Add0~7 )); +// synopsys translate_off +defparam \ula_|video_|Add0~6 .lut_mask = 16'h5A5F; +defparam \ula_|video_|Add0~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X34_Y32_N21 +dffeas \ula_|video_|vga_hc[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|Add0~6_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_hc [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_hc[3] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_hc[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y32_N14 +cycloneive_lcell_comb \ula_|video_|Add0~8 ( +// Equation(s): +// \ula_|video_|Add0~8_combout = (\ula_|video_|vga_hc [4] & (\ula_|video_|Add0~7 $ (GND))) # (!\ula_|video_|vga_hc [4] & (!\ula_|video_|Add0~7 & VCC)) +// \ula_|video_|Add0~9 = CARRY((\ula_|video_|vga_hc [4] & !\ula_|video_|Add0~7 )) + + .dataa(\ula_|video_|vga_hc [4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add0~7 ), + .combout(\ula_|video_|Add0~8_combout ), + .cout(\ula_|video_|Add0~9 )); +// synopsys translate_off +defparam \ula_|video_|Add0~8 .lut_mask = 16'hA50A; +defparam \ula_|video_|Add0~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X34_Y32_N3 +dffeas \ula_|video_|vga_hc[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|Add0~8_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_hc [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_hc[4] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_hc[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y32_N16 +cycloneive_lcell_comb \ula_|video_|Add0~10 ( +// Equation(s): +// \ula_|video_|Add0~10_combout = (\ula_|video_|vga_hc [5] & (!\ula_|video_|Add0~9 )) # (!\ula_|video_|vga_hc [5] & ((\ula_|video_|Add0~9 ) # (GND))) +// \ula_|video_|Add0~11 = CARRY((!\ula_|video_|Add0~9 ) # (!\ula_|video_|vga_hc [5])) + + .dataa(gnd), + .datab(\ula_|video_|vga_hc [5]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add0~9 ), + .combout(\ula_|video_|Add0~10_combout ), + .cout(\ula_|video_|Add0~11 )); +// synopsys translate_off +defparam \ula_|video_|Add0~10 .lut_mask = 16'h3C3F; +defparam \ula_|video_|Add0~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y32_N26 +cycloneive_lcell_comb \ula_|video_|vga_hc~0 ( +// Equation(s): +// \ula_|video_|vga_hc~0_combout = (\ula_|video_|Add0~10_combout & \ula_|video_|Equal1~0_combout ) + + .dataa(gnd), + .datab(\ula_|video_|Add0~10_combout ), + .datac(gnd), + .datad(\ula_|video_|Equal1~0_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_hc~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_hc~0 .lut_mask = 16'hCC00; +defparam \ula_|video_|vga_hc~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y32_N29 +dffeas \ula_|video_|vga_hc[5] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|vga_hc~0_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_hc [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_hc[5] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_hc[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y32_N18 +cycloneive_lcell_comb \ula_|video_|Add0~12 ( +// Equation(s): +// \ula_|video_|Add0~12_combout = (\ula_|video_|vga_hc [6] & (\ula_|video_|Add0~11 $ (GND))) # (!\ula_|video_|vga_hc [6] & (!\ula_|video_|Add0~11 & VCC)) +// \ula_|video_|Add0~13 = CARRY((\ula_|video_|vga_hc [6] & !\ula_|video_|Add0~11 )) + + .dataa(\ula_|video_|vga_hc [6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add0~11 ), + .combout(\ula_|video_|Add0~12_combout ), + .cout(\ula_|video_|Add0~13 )); +// synopsys translate_off +defparam \ula_|video_|Add0~12 .lut_mask = 16'hA50A; +defparam \ula_|video_|Add0~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X34_Y32_N5 +dffeas \ula_|video_|vga_hc[6] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|Add0~12_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_hc [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_hc[6] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_hc[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y32_N20 +cycloneive_lcell_comb \ula_|video_|Add0~14 ( +// Equation(s): +// \ula_|video_|Add0~14_combout = (\ula_|video_|vga_hc [7] & (!\ula_|video_|Add0~13 )) # (!\ula_|video_|vga_hc [7] & ((\ula_|video_|Add0~13 ) # (GND))) +// \ula_|video_|Add0~15 = CARRY((!\ula_|video_|Add0~13 ) # (!\ula_|video_|vga_hc [7])) + + .dataa(gnd), + .datab(\ula_|video_|vga_hc [7]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add0~13 ), + .combout(\ula_|video_|Add0~14_combout ), + .cout(\ula_|video_|Add0~15 )); +// synopsys translate_off +defparam \ula_|video_|Add0~14 .lut_mask = 16'h3C3F; +defparam \ula_|video_|Add0~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X34_Y32_N27 +dffeas \ula_|video_|vga_hc[7] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|Add0~14_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_hc [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_hc[7] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_hc[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y32_N22 +cycloneive_lcell_comb \ula_|video_|Add0~16 ( +// Equation(s): +// \ula_|video_|Add0~16_combout = (\ula_|video_|vga_hc [8] & (\ula_|video_|Add0~15 $ (GND))) # (!\ula_|video_|vga_hc [8] & (!\ula_|video_|Add0~15 & VCC)) +// \ula_|video_|Add0~17 = CARRY((\ula_|video_|vga_hc [8] & !\ula_|video_|Add0~15 )) + + .dataa(gnd), + .datab(\ula_|video_|vga_hc [8]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add0~15 ), + .combout(\ula_|video_|Add0~16_combout ), + .cout(\ula_|video_|Add0~17 )); +// synopsys translate_off +defparam \ula_|video_|Add0~16 .lut_mask = 16'hC30C; +defparam \ula_|video_|Add0~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y32_N2 +cycloneive_lcell_comb \ula_|video_|vga_hc~2 ( +// Equation(s): +// \ula_|video_|vga_hc~2_combout = (\ula_|video_|Add0~16_combout & \ula_|video_|Equal1~0_combout ) + + .dataa(gnd), + .datab(\ula_|video_|Add0~16_combout ), + .datac(gnd), + .datad(\ula_|video_|Equal1~0_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_hc~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_hc~2 .lut_mask = 16'hCC00; +defparam \ula_|video_|vga_hc~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y32_N27 +dffeas \ula_|video_|vga_hc[8] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|vga_hc~2_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_hc [8]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_hc[8] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_hc[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y32_N24 +cycloneive_lcell_comb \ula_|video_|Add0~18 ( +// Equation(s): +// \ula_|video_|Add0~18_combout = \ula_|video_|Add0~17 $ (\ula_|video_|vga_hc [9]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|vga_hc [9]), + .cin(\ula_|video_|Add0~17 ), + .combout(\ula_|video_|Add0~18_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Add0~18 .lut_mask = 16'h0FF0; +defparam \ula_|video_|Add0~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y32_N4 +cycloneive_lcell_comb \ula_|video_|vga_hc~1 ( +// Equation(s): +// \ula_|video_|vga_hc~1_combout = (\ula_|video_|Add0~18_combout & \ula_|video_|Equal1~0_combout ) + + .dataa(\ula_|video_|Add0~18_combout ), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|Equal1~0_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_hc~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_hc~1 .lut_mask = 16'hAA00; +defparam \ula_|video_|vga_hc~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y32_N1 +dffeas \ula_|video_|vga_hc[9] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|vga_hc~1_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_hc [9]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_hc[9] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_hc[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y31_N14 +cycloneive_lcell_comb \ula_|video_|Equal0~0 ( +// Equation(s): +// \ula_|video_|Equal0~0_combout = (!\ula_|video_|vga_hc [1] & (!\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [2] & !\ula_|video_|vga_hc [0]))) + + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|vga_hc [3]), + .datac(\ula_|video_|vga_hc [2]), + .datad(\ula_|video_|vga_hc [0]), + .cin(gnd), + .combout(\ula_|video_|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Equal0~0 .lut_mask = 16'h0001; +defparam \ula_|video_|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y31_N24 +cycloneive_lcell_comb \ula_|video_|Equal0~1 ( +// Equation(s): +// \ula_|video_|Equal0~1_combout = (!\ula_|video_|vga_hc [4] & (!\ula_|video_|vga_hc [7] & (\ula_|video_|Equal0~0_combout & \ula_|video_|vga_hc [5]))) + + .dataa(\ula_|video_|vga_hc [4]), + .datab(\ula_|video_|vga_hc [7]), + .datac(\ula_|video_|Equal0~0_combout ), + .datad(\ula_|video_|vga_hc [5]), + .cin(gnd), + .combout(\ula_|video_|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Equal0~1 .lut_mask = 16'h1000; +defparam \ula_|video_|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y31_N8 +cycloneive_lcell_comb \ula_|video_|Equal1~0 ( +// Equation(s): +// \ula_|video_|Equal1~0_combout = ((\ula_|video_|vga_hc [6]) # ((!\ula_|video_|Equal0~1_combout ) # (!\ula_|video_|vga_hc [8]))) # (!\ula_|video_|vga_hc [9]) + + .dataa(\ula_|video_|vga_hc [9]), + .datab(\ula_|video_|vga_hc [6]), + .datac(\ula_|video_|vga_hc [8]), + .datad(\ula_|video_|Equal0~1_combout ), + .cin(gnd), + .combout(\ula_|video_|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Equal1~0 .lut_mask = 16'hDFFF; +defparam \ula_|video_|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y31_N2 +cycloneive_lcell_comb \ula_|video_|Add1~0 ( +// Equation(s): +// \ula_|video_|Add1~0_combout = \ula_|video_|vga_vc [0] $ (VCC) +// \ula_|video_|Add1~1 = CARRY(\ula_|video_|vga_vc [0]) + + .dataa(\ula_|video_|vga_vc [0]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\ula_|video_|Add1~0_combout ), + .cout(\ula_|video_|Add1~1 )); +// synopsys translate_off +defparam \ula_|video_|Add1~0 .lut_mask = 16'h55AA; +defparam \ula_|video_|Add1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y31_N28 +cycloneive_lcell_comb \ula_|video_|vga_vc[0]~0 ( +// Equation(s): +// \ula_|video_|vga_vc[0]~0_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [0]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~0_combout )))) + + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Equal3~1_combout ), + .datac(\ula_|video_|Add1~0_combout ), + .datad(\ula_|video_|vga_vc [0]), + .cin(gnd), + .combout(\ula_|video_|vga_vc[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[0]~0 .lut_mask = 16'h3210; +defparam \ula_|video_|vga_vc[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y32_N29 +dffeas \ula_|video_|vga_vc[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|vga_vc[0]~0_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[0] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y31_N4 +cycloneive_lcell_comb \ula_|video_|Add1~2 ( +// Equation(s): +// \ula_|video_|Add1~2_combout = (\ula_|video_|vga_vc [1] & (!\ula_|video_|Add1~1 )) # (!\ula_|video_|vga_vc [1] & ((\ula_|video_|Add1~1 ) # (GND))) +// \ula_|video_|Add1~3 = CARRY((!\ula_|video_|Add1~1 ) # (!\ula_|video_|vga_vc [1])) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [1]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add1~1 ), + .combout(\ula_|video_|Add1~2_combout ), + .cout(\ula_|video_|Add1~3 )); +// synopsys translate_off +defparam \ula_|video_|Add1~2 .lut_mask = 16'h3C3F; +defparam \ula_|video_|Add1~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y32_N10 +cycloneive_lcell_comb \ula_|video_|vga_vc[1]~1 ( +// Equation(s): +// \ula_|video_|vga_vc[1]~1_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [1]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~2_combout )))) + + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Add1~2_combout ), + .datac(\ula_|video_|vga_vc [1]), + .datad(\ula_|video_|Equal3~1_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[1]~1 .lut_mask = 16'h00E4; +defparam \ula_|video_|vga_vc[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y32_N11 +dffeas \ula_|video_|vga_vc[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[1]~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[1] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y31_N6 +cycloneive_lcell_comb \ula_|video_|Add1~4 ( +// Equation(s): +// \ula_|video_|Add1~4_combout = (\ula_|video_|vga_vc [2] & (\ula_|video_|Add1~3 $ (GND))) # (!\ula_|video_|vga_vc [2] & (!\ula_|video_|Add1~3 & VCC)) +// \ula_|video_|Add1~5 = CARRY((\ula_|video_|vga_vc [2] & !\ula_|video_|Add1~3 )) + + .dataa(\ula_|video_|vga_vc [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add1~3 ), + .combout(\ula_|video_|Add1~4_combout ), + .cout(\ula_|video_|Add1~5 )); +// synopsys translate_off +defparam \ula_|video_|Add1~4 .lut_mask = 16'hA50A; +defparam \ula_|video_|Add1~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y31_N22 +cycloneive_lcell_comb \ula_|video_|vga_vc[2]~2 ( +// Equation(s): +// \ula_|video_|vga_vc[2]~2_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [2])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~4_combout ))))) + + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Equal3~1_combout ), + .datac(\ula_|video_|vga_vc [2]), + .datad(\ula_|video_|Add1~4_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[2]~2 .lut_mask = 16'h3120; +defparam \ula_|video_|vga_vc[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y32_N24 +cycloneive_lcell_comb \ula_|video_|vga_vc[2]~feeder ( +// Equation(s): +// \ula_|video_|vga_vc[2]~feeder_combout = \ula_|video_|vga_vc[2]~2_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|vga_vc[2]~2_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[2]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|vga_vc[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y32_N25 +dffeas \ula_|video_|vga_vc[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[2] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y31_N8 +cycloneive_lcell_comb \ula_|video_|Add1~6 ( +// Equation(s): +// \ula_|video_|Add1~6_combout = (\ula_|video_|vga_vc [3] & (!\ula_|video_|Add1~5 )) # (!\ula_|video_|vga_vc [3] & ((\ula_|video_|Add1~5 ) # (GND))) +// \ula_|video_|Add1~7 = CARRY((!\ula_|video_|Add1~5 ) # (!\ula_|video_|vga_vc [3])) .dataa(\ula_|video_|vga_vc [3]), - .datab(\ula_|video_|vga_vc [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add1~5 ), + .combout(\ula_|video_|Add1~6_combout ), + .cout(\ula_|video_|Add1~7 )); +// synopsys translate_off +defparam \ula_|video_|Add1~6 .lut_mask = 16'h5A5F; +defparam \ula_|video_|Add1~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y31_N24 +cycloneive_lcell_comb \ula_|video_|vga_vc[3]~3 ( +// Equation(s): +// \ula_|video_|vga_vc[3]~3_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [3])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~6_combout ))))) + + .dataa(\ula_|video_|vga_vc [3]), + .datab(\ula_|video_|Equal3~1_combout ), + .datac(\ula_|video_|Add1~6_combout ), + .datad(\ula_|video_|Equal1~0_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[3]~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[3]~3 .lut_mask = 16'h2230; +defparam \ula_|video_|vga_vc[3]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y32_N31 +dffeas \ula_|video_|vga_vc[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|vga_vc[3]~3_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[3] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y31_N10 +cycloneive_lcell_comb \ula_|video_|Add1~8 ( +// Equation(s): +// \ula_|video_|Add1~8_combout = (\ula_|video_|vga_vc [4] & (\ula_|video_|Add1~7 $ (GND))) # (!\ula_|video_|vga_vc [4] & (!\ula_|video_|Add1~7 & VCC)) +// \ula_|video_|Add1~9 = CARRY((\ula_|video_|vga_vc [4] & !\ula_|video_|Add1~7 )) + + .dataa(\ula_|video_|vga_vc [4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add1~7 ), + .combout(\ula_|video_|Add1~8_combout ), + .cout(\ula_|video_|Add1~9 )); +// synopsys translate_off +defparam \ula_|video_|Add1~8 .lut_mask = 16'hA50A; +defparam \ula_|video_|Add1~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y32_N6 +cycloneive_lcell_comb \ula_|video_|vga_vc[4]~5 ( +// Equation(s): +// \ula_|video_|vga_vc[4]~5_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [4]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~8_combout )))) + + .dataa(\ula_|video_|Equal3~1_combout ), + .datab(\ula_|video_|Add1~8_combout ), + .datac(\ula_|video_|vga_vc [4]), + .datad(\ula_|video_|Equal1~0_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[4]~5_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[4]~5 .lut_mask = 16'h5044; +defparam \ula_|video_|vga_vc[4]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y32_N7 +dffeas \ula_|video_|vga_vc[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[4]~5_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[4] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y31_N12 +cycloneive_lcell_comb \ula_|video_|Add1~10 ( +// Equation(s): +// \ula_|video_|Add1~10_combout = (\ula_|video_|vga_vc [5] & (!\ula_|video_|Add1~9 )) # (!\ula_|video_|vga_vc [5] & ((\ula_|video_|Add1~9 ) # (GND))) +// \ula_|video_|Add1~11 = CARRY((!\ula_|video_|Add1~9 ) # (!\ula_|video_|vga_vc [5])) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [5]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add1~9 ), + .combout(\ula_|video_|Add1~10_combout ), + .cout(\ula_|video_|Add1~11 )); +// synopsys translate_off +defparam \ula_|video_|Add1~10 .lut_mask = 16'h3C3F; +defparam \ula_|video_|Add1~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y31_N14 +cycloneive_lcell_comb \ula_|video_|Add1~12 ( +// Equation(s): +// \ula_|video_|Add1~12_combout = (\ula_|video_|vga_vc [6] & (\ula_|video_|Add1~11 $ (GND))) # (!\ula_|video_|vga_vc [6] & (!\ula_|video_|Add1~11 & VCC)) +// \ula_|video_|Add1~13 = CARRY((\ula_|video_|vga_vc [6] & !\ula_|video_|Add1~11 )) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [6]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add1~11 ), + .combout(\ula_|video_|Add1~12_combout ), + .cout(\ula_|video_|Add1~13 )); +// synopsys translate_off +defparam \ula_|video_|Add1~12 .lut_mask = 16'hC30C; +defparam \ula_|video_|Add1~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y32_N0 +cycloneive_lcell_comb \ula_|video_|vga_vc[6]~4 ( +// Equation(s): +// \ula_|video_|vga_vc[6]~4_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [6]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~12_combout )))) + + .dataa(\ula_|video_|Equal3~1_combout ), + .datab(\ula_|video_|Add1~12_combout ), + .datac(\ula_|video_|vga_vc [6]), + .datad(\ula_|video_|Equal1~0_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[6]~4_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[6]~4 .lut_mask = 16'h5044; +defparam \ula_|video_|vga_vc[6]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y32_N1 +dffeas \ula_|video_|vga_vc[6] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[6]~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[6] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y31_N16 +cycloneive_lcell_comb \ula_|video_|Add1~14 ( +// Equation(s): +// \ula_|video_|Add1~14_combout = (\ula_|video_|vga_vc [7] & (!\ula_|video_|Add1~13 )) # (!\ula_|video_|vga_vc [7] & ((\ula_|video_|Add1~13 ) # (GND))) +// \ula_|video_|Add1~15 = CARRY((!\ula_|video_|Add1~13 ) # (!\ula_|video_|vga_vc [7])) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [7]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add1~13 ), + .combout(\ula_|video_|Add1~14_combout ), + .cout(\ula_|video_|Add1~15 )); +// synopsys translate_off +defparam \ula_|video_|Add1~14 .lut_mask = 16'h3C3F; +defparam \ula_|video_|Add1~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y32_N8 +cycloneive_lcell_comb \ula_|video_|vga_vc[7]~6 ( +// Equation(s): +// \ula_|video_|vga_vc[7]~6_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [7]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~14_combout )))) + + .dataa(\ula_|video_|Equal3~1_combout ), + .datab(\ula_|video_|Add1~14_combout ), + .datac(\ula_|video_|vga_vc [7]), + .datad(\ula_|video_|Equal1~0_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[7]~6_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[7]~6 .lut_mask = 16'h5044; +defparam \ula_|video_|vga_vc[7]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y32_N9 +dffeas \ula_|video_|vga_vc[7] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[7]~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[7] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y31_N18 +cycloneive_lcell_comb \ula_|video_|Add1~16 ( +// Equation(s): +// \ula_|video_|Add1~16_combout = (\ula_|video_|vga_vc [8] & (\ula_|video_|Add1~15 $ (GND))) # (!\ula_|video_|vga_vc [8] & (!\ula_|video_|Add1~15 & VCC)) +// \ula_|video_|Add1~17 = CARRY((\ula_|video_|vga_vc [8] & !\ula_|video_|Add1~15 )) + + .dataa(\ula_|video_|vga_vc [8]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add1~15 ), + .combout(\ula_|video_|Add1~16_combout ), + .cout(\ula_|video_|Add1~17 )); +// synopsys translate_off +defparam \ula_|video_|Add1~16 .lut_mask = 16'hA50A; +defparam \ula_|video_|Add1~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y32_N0 +cycloneive_lcell_comb \ula_|video_|vga_vc[8]~7 ( +// Equation(s): +// \ula_|video_|vga_vc[8]~7_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [8]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~16_combout )))) + + .dataa(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Add1~16_combout ), + .datac(\ula_|video_|vga_vc [8]), + .datad(\ula_|video_|Equal3~1_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[8]~7_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[8]~7 .lut_mask = 16'h00E4; +defparam \ula_|video_|vga_vc[8]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y32_N1 +dffeas \ula_|video_|vga_vc[8] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[8]~7_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [8]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[8] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y31_N20 +cycloneive_lcell_comb \ula_|video_|Add1~18 ( +// Equation(s): +// \ula_|video_|Add1~18_combout = \ula_|video_|Add1~17 $ (\ula_|video_|vga_vc [9]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|vga_vc [9]), + .cin(\ula_|video_|Add1~17 ), + .combout(\ula_|video_|Add1~18_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Add1~18 .lut_mask = 16'h0FF0; +defparam \ula_|video_|Add1~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y32_N28 +cycloneive_lcell_comb \ula_|video_|vga_vc[9]~9 ( +// Equation(s): +// \ula_|video_|vga_vc[9]~9_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [9]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~18_combout )))) + + .dataa(\ula_|video_|Add1~18_combout ), + .datab(\ula_|video_|Equal1~0_combout ), .datac(\ula_|video_|vga_vc [9]), + .datad(\ula_|video_|Equal3~1_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[9]~9_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[9]~9 .lut_mask = 16'h00E2; +defparam \ula_|video_|vga_vc[9]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y32_N29 +dffeas \ula_|video_|vga_vc[9] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[9]~9_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [9]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[9] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y30_N0 +cycloneive_lcell_comb \ula_|video_|Equal3~0 ( +// Equation(s): +// \ula_|video_|Equal3~0_combout = (\ula_|video_|vga_vc [0] & (\ula_|video_|vga_vc [3] & (\ula_|video_|vga_vc [2] & !\ula_|video_|vga_vc [1]))) + + .dataa(\ula_|video_|vga_vc [0]), + .datab(\ula_|video_|vga_vc [3]), + .datac(\ula_|video_|vga_vc [2]), + .datad(\ula_|video_|vga_vc [1]), + .cin(gnd), + .combout(\ula_|video_|Equal3~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Equal3~0 .lut_mask = 16'h0080; +defparam \ula_|video_|Equal3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y32_N2 +cycloneive_lcell_comb \ula_|video_|Equal2~0 ( +// Equation(s): +// \ula_|video_|Equal2~0_combout = (!\ula_|video_|vga_vc [6] & (!\ula_|video_|vga_vc [8] & (!\ula_|video_|vga_vc [4] & !\ula_|video_|vga_vc [7]))) + + .dataa(\ula_|video_|vga_vc [6]), + .datab(\ula_|video_|vga_vc [8]), + .datac(\ula_|video_|vga_vc [4]), + .datad(\ula_|video_|vga_vc [7]), + .cin(gnd), + .combout(\ula_|video_|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Equal2~0 .lut_mask = 16'h0001; +defparam \ula_|video_|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y32_N10 +cycloneive_lcell_comb \ula_|video_|Equal3~1 ( +// Equation(s): +// \ula_|video_|Equal3~1_combout = (!\ula_|video_|vga_vc [5] & (\ula_|video_|vga_vc [9] & (\ula_|video_|Equal3~0_combout & \ula_|video_|Equal2~0_combout ))) + + .dataa(\ula_|video_|vga_vc [5]), + .datab(\ula_|video_|vga_vc [9]), + .datac(\ula_|video_|Equal3~0_combout ), + .datad(\ula_|video_|Equal2~0_combout ), + .cin(gnd), + .combout(\ula_|video_|Equal3~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Equal3~1 .lut_mask = 16'h4000; +defparam \ula_|video_|Equal3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y32_N30 +cycloneive_lcell_comb \ula_|video_|vga_vc[5]~8 ( +// Equation(s): +// \ula_|video_|vga_vc[5]~8_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [5]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~10_combout )))) + + .dataa(\ula_|video_|Equal3~1_combout ), + .datab(\ula_|video_|Add1~10_combout ), + .datac(\ula_|video_|vga_vc [5]), + .datad(\ula_|video_|Equal1~0_combout ), + .cin(gnd), + .combout(\ula_|video_|vga_vc[5]~8_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vga_vc[5]~8 .lut_mask = 16'h5044; +defparam \ula_|video_|vga_vc[5]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y32_N31 +dffeas \ula_|video_|vga_vc[5] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vga_vc[5]~8_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vga_vc [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vga_vc[5] .is_wysiwyg = "true"; +defparam \ula_|video_|vga_vc[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y31_N26 +cycloneive_lcell_comb \ula_|video_|Equal2~1 ( +// Equation(s): +// \ula_|video_|Equal2~1_combout = (!\ula_|video_|vga_vc [2] & (!\ula_|video_|vga_vc [9] & (!\ula_|video_|vga_vc [3] & !\ula_|video_|vga_vc [0]))) + + .dataa(\ula_|video_|vga_vc [2]), + .datab(\ula_|video_|vga_vc [9]), + .datac(\ula_|video_|vga_vc [3]), .datad(\ula_|video_|vga_vc [0]), .cin(gnd), .combout(\ula_|video_|Equal2~1_combout ), @@ -19059,41 +6088,68 @@ defparam \ula_|video_|Equal2~1 .lut_mask = 16'h0001; defparam \ula_|video_|Equal2~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y33_N14 +// Location: LCCOMB_X35_Y32_N24 cycloneive_lcell_comb \ula_|video_|Equal2~2 ( // Equation(s): -// \ula_|video_|Equal2~2_combout = (\ula_|video_|Equal2~1_combout & (\ula_|video_|Equal2~0_combout & !\ula_|video_|vga_vc [5])) +// \ula_|video_|Equal2~2_combout = (!\ula_|video_|vga_vc [5] & (\ula_|video_|Equal2~1_combout & \ula_|video_|Equal2~0_combout )) - .dataa(gnd), + .dataa(\ula_|video_|vga_vc [5]), .datab(\ula_|video_|Equal2~1_combout ), - .datac(\ula_|video_|Equal2~0_combout ), - .datad(\ula_|video_|vga_vc [5]), + .datac(gnd), + .datad(\ula_|video_|Equal2~0_combout ), .cin(gnd), .combout(\ula_|video_|Equal2~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Equal2~2 .lut_mask = 16'h00C0; +defparam \ula_|video_|Equal2~2 .lut_mask = 16'h4400; defparam \ula_|video_|Equal2~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y31_N28 +// Location: IOIBUF_X27_Y0_N15 +cycloneive_io_ibuf \SW[1]~input ( + .i(SW[1]), + .ibar(gnd), + .o(\SW[1]~input_o )); +// synopsys translate_off +defparam \SW[1]~input .bus_hold = "false"; +defparam \SW[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y33_N2 +cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_13~0 ( +// Equation(s): +// \z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout = (!\ula_|video_|vga_vc [1] & (!\ula_|video_|vga_hc [8] & (!\ula_|video_|vga_hc [9] & !\SW[1]~input_o ))) + + .dataa(\ula_|video_|vga_vc [1]), + .datab(\ula_|video_|vga_hc [8]), + .datac(\ula_|video_|vga_hc [9]), + .datad(\SW[1]~input_o ), + .cin(gnd), + .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13~0 .lut_mask = 16'h0001; +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y33_N20 cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_13 ( // Equation(s): -// \z80_|interrupts_|SYNTHESIZED_WIRE_13~combout = (!\ula_|video_|vga_hc [7] & (\z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout & (\z80_|interrupts_|iff1~q & \ula_|video_|Equal2~2_combout ))) +// \z80_|interrupts_|SYNTHESIZED_WIRE_13~combout = (\z80_|interrupts_|iff1~q & (\ula_|video_|Equal2~2_combout & (!\ula_|video_|vga_hc [7] & \z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout ))) - .dataa(\ula_|video_|vga_hc [7]), - .datab(\z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout ), - .datac(\z80_|interrupts_|iff1~q ), - .datad(\ula_|video_|Equal2~2_combout ), + .dataa(\z80_|interrupts_|iff1~q ), + .datab(\ula_|video_|Equal2~2_combout ), + .datac(\ula_|video_|vga_hc [7]), + .datad(\z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout ), .cin(gnd), .combout(\z80_|interrupts_|SYNTHESIZED_WIRE_13~combout ), .cout()); // synopsys translate_off -defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13 .lut_mask = 16'h4000; +defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13 .lut_mask = 16'h0800; defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X35_Y31_N29 +// Location: FF_X35_Y33_N21 dffeas \z80_|interrupts_|int_armed ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|interrupts_|SYNTHESIZED_WIRE_13~combout ), @@ -19112,15 +6168,32 @@ defparam \z80_|interrupts_|int_armed .is_wysiwyg = "true"; defparam \z80_|interrupts_|int_armed .power_up = "low"; // synopsys translate_on -// Location: FF_X32_Y15_N11 +// Location: LCCOMB_X28_Y13_N30 +cycloneive_lcell_comb \z80_|interrupts_|DFFE_inst44~feeder ( +// Equation(s): +// \z80_|interrupts_|DFFE_inst44~feeder_combout = \z80_|interrupts_|int_armed~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|interrupts_|int_armed~q ), + .cin(gnd), + .combout(\z80_|interrupts_|DFFE_inst44~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|DFFE_inst44~feeder .lut_mask = 16'hFF00; +defparam \z80_|interrupts_|DFFE_inst44~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y13_N31 dffeas \z80_|interrupts_|DFFE_inst44 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|interrupts_|int_armed~q ), + .d(\z80_|interrupts_|DFFE_inst44~feeder_combout ), + .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), .sclr(gnd), - .sload(vcc), + .sload(gnd), .ena(\z80_|interrupts_|test1~3_combout ), .devclrn(devclrn), .devpor(devpor), @@ -19131,14509 +6204,44 @@ defparam \z80_|interrupts_|DFFE_inst44 .is_wysiwyg = "true"; defparam \z80_|interrupts_|DFFE_inst44 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~38 ( +// Location: LCCOMB_X28_Y13_N4 +cycloneive_lcell_comb \z80_|decode_state_|in_halt~0 ( // Equation(s): -// \z80_|execute_|pc_inc_hold~38_combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # ((\z80_|decode_state_|in_halt~q ) # (\z80_|interrupts_|DFFE_inst44~q )) +// \z80_|decode_state_|in_halt~0_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (!\z80_|interrupts_|DFFE_inst44~q & \z80_|decode_state_|in_halt~q )) .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), .datab(gnd), - .datac(\z80_|decode_state_|in_halt~q ), - .datad(\z80_|interrupts_|DFFE_inst44~q ), + .datac(\z80_|interrupts_|DFFE_inst44~q ), + .datad(\z80_|decode_state_|in_halt~q ), .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~38_combout ), + .combout(\z80_|decode_state_|in_halt~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~38 .lut_mask = 16'hFFFA; -defparam \z80_|execute_|pc_inc_hold~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~91 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~91_combout = (((!\z80_|sequencer_|DFFE_M3_ff~q & !\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|pla_decode_|Equal34~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~91_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~91 .lut_mask = 16'h57FF; -defparam \z80_|execute_|ctl_inc_cy~91 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~45 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~45_combout = (\z80_|pla_decode_|Equal19~0_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ctl_mRead~36_combout & \z80_|execute_|pc_inc_hold~29_combout )))) # (!\z80_|pla_decode_|Equal19~0_combout & -// (((\z80_|execute_|ctl_mRead~36_combout & \z80_|execute_|pc_inc_hold~29_combout )))) - - .dataa(\z80_|pla_decode_|Equal19~0_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_mRead~36_combout ), - .datad(\z80_|execute_|pc_inc_hold~29_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~45 .lut_mask = 16'hF888; -defparam \z80_|execute_|pc_inc_hold~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~44 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~44_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & ((\z80_|pla_decode_|Equal19~0_combout ) # ((!\z80_|execute_|pc_inc_hold~49_combout ) # (!\z80_|execute_|ctl_bus_db_oe~1_combout )))) - - .dataa(\z80_|pla_decode_|Equal19~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .datad(\z80_|execute_|pc_inc_hold~49_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~44 .lut_mask = 16'h8CCC; -defparam \z80_|execute_|pc_inc_hold~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N2 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~46 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~46_combout = (\z80_|execute_|pc_inc_hold~45_combout ) # ((\z80_|execute_|pc_inc_hold~44_combout ) # ((\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|pc_inc_hold~49_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~45_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|pc_inc_hold~44_combout ), - .datad(\z80_|execute_|pc_inc_hold~49_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~46 .lut_mask = 16'hFAFE; -defparam \z80_|execute_|pc_inc_hold~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N18 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~37 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~37_combout = (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|execute_|pc_inc_hold~29_combout ) # ((\z80_|pla_decode_|Equal52~1_combout & \z80_|execute_|ctl_alu_op_low~8_combout )))) # (!\z80_|pla_decode_|Equal10~0_combout & -// (\z80_|pla_decode_|Equal52~1_combout & (\z80_|execute_|ctl_alu_op_low~8_combout ))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|pla_decode_|Equal52~1_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datad(\z80_|execute_|pc_inc_hold~29_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~37 .lut_mask = 16'hEAC0; -defparam \z80_|execute_|pc_inc_hold~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N12 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~50 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~50_combout = (\z80_|execute_|pc_inc_hold~37_combout ) # ((\z80_|execute_|ixy_d~16_combout & (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ))) - - .dataa(\z80_|execute_|ixy_d~16_combout ), - .datab(\z80_|execute_|pc_inc_hold~37_combout ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~50 .lut_mask = 16'hECCC; -defparam \z80_|execute_|pc_inc_hold~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N22 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~33 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~33_combout = (\z80_|execute_|ctl_mRead~10_combout & (((\z80_|execute_|ctl_alu_op_low~8_combout ) # (\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|execute_|ctl_mRead~10_combout & (\z80_|pla_decode_|Equal6~1_combout & -// ((\z80_|execute_|ctl_alu_op_low~8_combout ) # (\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|pla_decode_|Equal6~1_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~33 .lut_mask = 16'hEEE0; -defparam \z80_|execute_|pc_inc_hold~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|execute_|ixy_d~5_combout & (\z80_|pla_decode_|Equal55~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal33~2_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|decode_state_|use_ixiy~combout ), - .datad(\z80_|pla_decode_|Equal33~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N26 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~31 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~31_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ) # ((\z80_|execute_|ctl_alu_op_low~8_combout & ((\z80_|execute_|ctl_mRead~14_combout ) # (!\z80_|execute_|pc_inc_hold~28_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ), - .datac(\z80_|execute_|ctl_mRead~14_combout ), - .datad(\z80_|execute_|pc_inc_hold~28_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~31 .lut_mask = 16'hECEE; -defparam \z80_|execute_|pc_inc_hold~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N12 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~32 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~32_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & (((\z80_|execute_|ctl_mRead~9_combout ) # (\z80_|execute_|ctl_mRead~15_combout )))) # (!\z80_|execute_|ctl_alu_op_low~8_combout & (\z80_|execute_|ixy_d~5_combout & -// ((\z80_|execute_|ctl_mRead~15_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_mRead~9_combout ), - .datad(\z80_|execute_|ctl_mRead~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~32 .lut_mask = 16'hEEA0; -defparam \z80_|execute_|pc_inc_hold~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N16 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~34 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~34_combout = (\z80_|execute_|pc_inc_hold~33_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ) # ((\z80_|execute_|pc_inc_hold~31_combout ) # (\z80_|execute_|pc_inc_hold~32_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~33_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ), - .datac(\z80_|execute_|pc_inc_hold~31_combout ), - .datad(\z80_|execute_|pc_inc_hold~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~34 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|pc_inc_hold~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N28 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~51 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~51_combout = (((!\z80_|sequencer_|DFFE_M3_ff~q & !\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|execute_|ctl_mRead~17_combout ) - - .dataa(\z80_|execute_|ctl_mRead~17_combout ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~51_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~51 .lut_mask = 16'h57FF; -defparam \z80_|execute_|pc_inc_hold~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N22 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~30 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~30_combout = (\z80_|pla_decode_|Equal12~1_combout ) # (((!\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ctl_alu_op_low~8_combout )) # (!\z80_|pla_decode_|Equal25~0_combout )) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|pla_decode_|Equal12~1_combout ), - .datac(\z80_|pla_decode_|Equal25~0_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~30 .lut_mask = 16'hCFDF; -defparam \z80_|execute_|pc_inc_hold~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N6 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~52 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~52_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|execute_|ctl_mRead~8_combout & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (\z80_|sequencer_|DFFE_M2_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|execute_|ctl_mRead~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~52_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~52 .lut_mask = 16'hA800; -defparam \z80_|execute_|pc_inc_hold~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N8 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~35 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~35_combout = (!\z80_|execute_|pc_inc_hold~34_combout & (\z80_|execute_|pc_inc_hold~51_combout & (\z80_|execute_|pc_inc_hold~30_combout & !\z80_|execute_|pc_inc_hold~52_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~34_combout ), - .datab(\z80_|execute_|pc_inc_hold~51_combout ), - .datac(\z80_|execute_|pc_inc_hold~30_combout ), - .datad(\z80_|execute_|pc_inc_hold~52_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~35 .lut_mask = 16'h0040; -defparam \z80_|execute_|pc_inc_hold~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N4 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~36 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~36_combout = ((\z80_|pla_decode_|Equal11~0_combout & ((\z80_|execute_|ctl_mWrite~7_combout ) # (\z80_|execute_|ctl_alu_shift_oe~14_combout )))) # (!\z80_|execute_|pc_inc_hold~35_combout ) - - .dataa(\z80_|execute_|ctl_mWrite~7_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|pc_inc_hold~35_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~36 .lut_mask = 16'hCF8F; -defparam \z80_|execute_|pc_inc_hold~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~44 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~44_combout = (((!\z80_|pla_decode_|Equal21~0_combout & !\z80_|pla_decode_|Equal3~0_combout )) # (!\z80_|pla_decode_|Equal24~0_combout )) # (!\z80_|execute_|ctl_alu_op_low~8_combout ) - - .dataa(\z80_|pla_decode_|Equal21~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|pla_decode_|Equal3~0_combout ), - .datad(\z80_|pla_decode_|Equal24~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~44 .lut_mask = 16'h37FF; -defparam \z80_|execute_|ctl_inc_cy~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|execute_|ixy_d~10_combout )) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(gnd), - .datad(\z80_|execute_|ixy_d~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 .lut_mask = 16'h8800; -defparam \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~45 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~45_combout = (!\z80_|execute_|pc_inc_hold~50_combout & (!\z80_|execute_|pc_inc_hold~36_combout & (\z80_|execute_|ctl_inc_cy~44_combout & !\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~50_combout ), - .datab(\z80_|execute_|pc_inc_hold~36_combout ), - .datac(\z80_|execute_|ctl_inc_cy~44_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~45 .lut_mask = 16'h0010; -defparam \z80_|execute_|ctl_inc_cy~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~43 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~43_combout = (\z80_|execute_|ctl_mWrite~2_combout & (\z80_|pla_decode_|Equal55~0_combout & ((\z80_|execute_|ctl_mWrite~7_combout ) # (\z80_|execute_|ctl_alu_shift_oe~14_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~7_combout ), - .datab(\z80_|execute_|ctl_mWrite~2_combout ), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~43 .lut_mask = 16'hC080; -defparam \z80_|execute_|pc_inc_hold~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~71 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~71_combout = (\z80_|execute_|ctl_inc_cy~91_combout & (!\z80_|execute_|pc_inc_hold~46_combout & (\z80_|execute_|ctl_inc_cy~45_combout & !\z80_|execute_|pc_inc_hold~43_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~91_combout ), - .datab(\z80_|execute_|pc_inc_hold~46_combout ), - .datac(\z80_|execute_|ctl_inc_cy~45_combout ), - .datad(\z80_|execute_|pc_inc_hold~43_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~71_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~71 .lut_mask = 16'h0020; -defparam \z80_|execute_|ctl_inc_cy~71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~73 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~73_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (((\z80_|execute_|ctl_inc_cy~72_combout & \z80_|execute_|ctl_inc_cy~71_combout )) # (!\z80_|execute_|pc_inc_hold~38_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|execute_|ctl_inc_cy~72_combout ), - .datac(\z80_|execute_|pc_inc_hold~38_combout ), - .datad(\z80_|execute_|ctl_inc_cy~71_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~73_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~73 .lut_mask = 16'h8A0A; -defparam \z80_|execute_|ctl_inc_cy~73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~46 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~46_combout = (\z80_|execute_|ixy_d~5_combout & (\z80_|execute_|ctl_mWrite~16_combout & ((\z80_|execute_|ctl_inc_cy~45_combout ) # (!\z80_|execute_|pc_inc_hold~38_combout )))) - - .dataa(\z80_|execute_|ctl_inc_cy~45_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|pc_inc_hold~38_combout ), - .datad(\z80_|execute_|ctl_mWrite~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~46 .lut_mask = 16'h8C00; -defparam \z80_|execute_|ctl_inc_cy~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N24 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~53 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~53_combout = (\z80_|pla_decode_|Equal11~0_combout & (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T4_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|sequencer_|DFFE_M4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~53_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~53 .lut_mask = 16'hE000; -defparam \z80_|execute_|pc_inc_hold~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N0 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~39 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~39_combout = (!\z80_|execute_|pc_inc_hold~50_combout & (!\z80_|execute_|pc_inc_hold~53_combout & (\z80_|execute_|pc_inc_hold~35_combout & !\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~50_combout ), - .datab(\z80_|execute_|pc_inc_hold~53_combout ), - .datac(\z80_|execute_|pc_inc_hold~35_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~39 .lut_mask = 16'h0010; -defparam \z80_|execute_|pc_inc_hold~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N10 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~47 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~47_combout = (\z80_|execute_|pc_inc_hold~46_combout ) # ((\z80_|execute_|pc_inc_hold~43_combout ) # ((!\z80_|execute_|ctl_inc_cy~44_combout ) # (!\z80_|execute_|pc_inc_hold~39_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~46_combout ), - .datab(\z80_|execute_|pc_inc_hold~43_combout ), - .datac(\z80_|execute_|pc_inc_hold~39_combout ), - .datad(\z80_|execute_|ctl_inc_cy~44_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~47 .lut_mask = 16'hEFFF; -defparam \z80_|execute_|pc_inc_hold~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~74 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~74_combout = (((!\z80_|execute_|ctl_inc_cy~40_combout ) # (!\z80_|execute_|ctl_inc_cy~34_combout )) # (!\z80_|execute_|ctl_inc_cy~35_combout )) # (!\z80_|execute_|ctl_inc_cy~43_combout ) - - .dataa(\z80_|execute_|ctl_inc_cy~43_combout ), - .datab(\z80_|execute_|ctl_inc_cy~35_combout ), - .datac(\z80_|execute_|ctl_inc_cy~34_combout ), - .datad(\z80_|execute_|ctl_inc_cy~40_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~74_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~74 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_inc_cy~74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y15_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~78 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~78_combout = ((\z80_|execute_|ctl_inc_cy~74_combout ) # (!\z80_|execute_|ctl_inc_cy~77_combout )) # (!\z80_|execute_|ctl_inc_cy~39_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_inc_cy~39_combout ), - .datac(\z80_|execute_|ctl_inc_cy~77_combout ), - .datad(\z80_|execute_|ctl_inc_cy~74_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~78_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~78 .lut_mask = 16'hFF3F; -defparam \z80_|execute_|ctl_inc_cy~78 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~79 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~79_combout = (\z80_|execute_|ctl_inc_cy~78_combout & (((!\z80_|execute_|pc_inc_hold~47_combout & \z80_|execute_|ctl_inc_cy~91_combout )) # (!\z80_|execute_|pc_inc_hold~38_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~47_combout ), - .datab(\z80_|execute_|ctl_inc_cy~78_combout ), - .datac(\z80_|execute_|pc_inc_hold~38_combout ), - .datad(\z80_|execute_|ctl_inc_cy~91_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~79_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~79 .lut_mask = 16'h4C0C; -defparam \z80_|execute_|ctl_inc_cy~79 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~80 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~80_combout = (\z80_|execute_|ctl_inc_cy~45_combout & (\z80_|execute_|ctl_alu_op_low~8_combout & (\z80_|execute_|ctl_mRead~36_combout & !\z80_|execute_|pc_inc_hold~43_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~45_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|execute_|ctl_mRead~36_combout ), - .datad(\z80_|execute_|pc_inc_hold~43_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~80_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~80 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_inc_cy~80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~81 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~81_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal19~1_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # (\z80_|execute_|ixy_d~9_combout )))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|pla_decode_|Equal19~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~81_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~81 .lut_mask = 16'hA800; -defparam \z80_|execute_|ctl_inc_cy~81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~82 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~82_combout = (\z80_|execute_|ctl_inc_cy~81_combout ) # ((\z80_|pla_decode_|Equal19~0_combout & ((\z80_|execute_|ctl_state_alu~6_combout ) # (\z80_|execute_|ctl_alu_oe~2_combout )))) - - .dataa(\z80_|execute_|ctl_inc_cy~81_combout ), - .datab(\z80_|pla_decode_|Equal19~0_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_alu_oe~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~82_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~82 .lut_mask = 16'hEEEA; -defparam \z80_|execute_|ctl_inc_cy~82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~83 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~83_combout = (\z80_|execute_|pc_inc_hold~47_combout & (!\z80_|execute_|pc_inc_hold~38_combout & ((\z80_|execute_|ctl_inc_cy~82_combout ) # (!\z80_|execute_|ctl_inc_cy~38_combout )))) # (!\z80_|execute_|pc_inc_hold~47_combout -// & ((\z80_|execute_|ctl_inc_cy~82_combout ) # ((!\z80_|execute_|ctl_inc_cy~38_combout )))) - - .dataa(\z80_|execute_|pc_inc_hold~47_combout ), - .datab(\z80_|execute_|ctl_inc_cy~82_combout ), - .datac(\z80_|execute_|pc_inc_hold~38_combout ), - .datad(\z80_|execute_|ctl_inc_cy~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~83_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~83 .lut_mask = 16'h4C5F; -defparam \z80_|execute_|ctl_inc_cy~83 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~84 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~84_combout = (\z80_|execute_|ctl_inc_cy~79_combout ) # ((\z80_|execute_|ctl_inc_cy~80_combout ) # (\z80_|execute_|ctl_inc_cy~83_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_inc_cy~79_combout ), - .datac(\z80_|execute_|ctl_inc_cy~80_combout ), - .datad(\z80_|execute_|ctl_inc_cy~83_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~84_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~84 .lut_mask = 16'hFFFC; -defparam \z80_|execute_|ctl_inc_cy~84 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N10 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~42 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~42_combout = ((\z80_|execute_|pc_inc_hold~34_combout ) # (\z80_|execute_|pc_inc_hold~52_combout )) # (!\z80_|execute_|pc_inc_hold~30_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|pc_inc_hold~30_combout ), - .datac(\z80_|execute_|pc_inc_hold~34_combout ), - .datad(\z80_|execute_|pc_inc_hold~52_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~42 .lut_mask = 16'hFFF3; -defparam \z80_|execute_|pc_inc_hold~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~90 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~90_combout = (((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|execute_|ctl_mRead~8_combout ) - - .dataa(\z80_|sequencer_|M5~q ), - .datab(\z80_|execute_|ctl_mRead~8_combout ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~90_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~90 .lut_mask = 16'h37FF; -defparam \z80_|execute_|ctl_inc_cy~90 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N2 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~41 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~41_combout = (\z80_|execute_|pc_inc_hold~31_combout ) # ((\z80_|execute_|pc_inc_hold~32_combout ) # ((\z80_|execute_|ixy_d~5_combout & \z80_|execute_|ctl_mRead~9_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~31_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_mRead~9_combout ), - .datad(\z80_|execute_|pc_inc_hold~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~41 .lut_mask = 16'hFFEA; -defparam \z80_|execute_|pc_inc_hold~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~66 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~66_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|execute_|ctl_mRead~14_combout & (!\z80_|decode_state_|in_halt~q & !\z80_|interrupts_|DFFE_inst44~q ))) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|execute_|ctl_mRead~14_combout ), - .datac(\z80_|decode_state_|in_halt~q ), - .datad(\z80_|interrupts_|DFFE_inst44~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~66_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~66 .lut_mask = 16'h0004; -defparam \z80_|execute_|ctl_inc_cy~66 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~67 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~67_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & ((\z80_|execute_|ctl_inc_cy~66_combout ) # ((!\z80_|execute_|ctl_reg_sys_hilo~20_combout & !\z80_|execute_|pc_inc_hold~31_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo~20_combout ), - .datac(\z80_|execute_|pc_inc_hold~31_combout ), - .datad(\z80_|execute_|ctl_inc_cy~66_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~67_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~67 .lut_mask = 16'hAA02; -defparam \z80_|execute_|ctl_inc_cy~67 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~68 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~68_combout = (\z80_|execute_|ctl_inc_cy~67_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~14_combout & (!\z80_|execute_|pc_inc_hold~41_combout & \z80_|execute_|ctl_mRead~15_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|execute_|pc_inc_hold~41_combout ), - .datac(\z80_|execute_|ctl_inc_cy~67_combout ), - .datad(\z80_|execute_|ctl_mRead~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~68_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~68 .lut_mask = 16'hF2F0; -defparam \z80_|execute_|ctl_inc_cy~68 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y19_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~64 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~64_combout = (!\z80_|execute_|pc_inc_hold~31_combout & (((!\z80_|execute_|ctl_alu_op_low~8_combout & !\z80_|execute_|ixy_d~5_combout )) # (!\z80_|execute_|ctl_mRead~9_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datab(\z80_|execute_|ctl_mRead~9_combout ), - .datac(\z80_|execute_|pc_inc_hold~31_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~64_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~64 .lut_mask = 16'h0307; -defparam \z80_|execute_|ctl_inc_cy~64 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~63 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~63_combout = (\z80_|execute_|ctl_mRead~10_combout & (!\z80_|execute_|pc_inc_hold~34_combout & ((\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (\z80_|execute_|ctl_sw_4u~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datab(\z80_|execute_|ctl_mRead~10_combout ), - .datac(\z80_|execute_|pc_inc_hold~34_combout ), - .datad(\z80_|execute_|ctl_sw_4u~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~63_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~63 .lut_mask = 16'h0C08; -defparam \z80_|execute_|ctl_inc_cy~63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~65 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~65_combout = (\z80_|execute_|ctl_inc_cy~63_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & ((\z80_|execute_|ctl_inc_cy~64_combout ) # (!\z80_|execute_|pc_inc_hold~38_combout )))) - - .dataa(\z80_|execute_|pc_inc_hold~38_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), - .datac(\z80_|execute_|ctl_inc_cy~64_combout ), - .datad(\z80_|execute_|ctl_inc_cy~63_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~65_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~65 .lut_mask = 16'hFFC4; -defparam \z80_|execute_|ctl_inc_cy~65 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~69 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~69_combout = (\z80_|execute_|ctl_inc_cy~68_combout ) # ((\z80_|execute_|ctl_inc_cy~65_combout ) # ((!\z80_|execute_|pc_inc_hold~42_combout & !\z80_|execute_|ctl_inc_cy~90_combout ))) - - .dataa(\z80_|execute_|pc_inc_hold~42_combout ), - .datab(\z80_|execute_|ctl_inc_cy~90_combout ), - .datac(\z80_|execute_|ctl_inc_cy~68_combout ), - .datad(\z80_|execute_|ctl_inc_cy~65_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~69_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~69 .lut_mask = 16'hFFF1; -defparam \z80_|execute_|ctl_inc_cy~69 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~49 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~49_combout = ((\z80_|pla_decode_|Equal9~1_combout & ((\z80_|execute_|ixy_d~9_combout ) # (\z80_|execute_|ctl_state_alu~6_combout )))) # (!\z80_|execute_|ctl_inc_cy~92_combout ) - - .dataa(\z80_|execute_|ixy_d~9_combout ), - .datab(\z80_|execute_|ctl_state_alu~6_combout ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|execute_|ctl_inc_cy~92_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~49 .lut_mask = 16'hE0FF; -defparam \z80_|execute_|ctl_inc_cy~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~50 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~50_combout = (\z80_|execute_|ixy_d~9_combout & ((\z80_|pla_decode_|Equal11~0_combout ) # ((\z80_|execute_|ctl_mWrite~4_combout & \z80_|execute_|ixy_d~7_combout )))) # (!\z80_|execute_|ixy_d~9_combout & -// (((\z80_|execute_|ctl_mWrite~4_combout & \z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|execute_|ixy_d~9_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~50 .lut_mask = 16'hF888; -defparam \z80_|execute_|ctl_inc_cy~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~51 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~51_combout = (\z80_|execute_|ctl_inc_cy~50_combout ) # (((\z80_|execute_|ctl_mWrite~4_combout & \z80_|execute_|ctl_mRead~11_combout )) # (!\z80_|execute_|ctl_inc_cy~94_combout )) - - .dataa(\z80_|execute_|ctl_inc_cy~50_combout ), - .datab(\z80_|execute_|ctl_mWrite~4_combout ), - .datac(\z80_|execute_|ctl_inc_cy~94_combout ), - .datad(\z80_|execute_|ctl_mRead~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~51_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~51 .lut_mask = 16'hEFAF; -defparam \z80_|execute_|ctl_inc_cy~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~52 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~52_combout = (\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ) # ((\z80_|execute_|ctl_inc_cy~51_combout ) # ((\z80_|execute_|ctl_alu_op_low~8_combout & \z80_|pla_decode_|Equal11~0_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|execute_|ctl_inc_cy~51_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~52_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~52 .lut_mask = 16'hFFEA; -defparam \z80_|execute_|ctl_inc_cy~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~36 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~36_combout = ((!\z80_|execute_|ctl_state_alu~4_combout & (!\z80_|execute_|ctl_alu_op_low~8_combout & !\z80_|execute_|ixy_d~5_combout ))) # (!\z80_|execute_|ctl_mWrite~4_combout ) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|execute_|ctl_mWrite~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~36 .lut_mask = 16'h01FF; -defparam \z80_|execute_|ctl_inc_cy~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~37 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~37_combout = (\z80_|execute_|ctl_sw_2u~0_combout & (\z80_|execute_|ctl_inc_cy~36_combout & ((!\z80_|pla_decode_|Equal11~0_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ctl_sw_2u~0_combout ), - .datad(\z80_|execute_|ctl_inc_cy~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~37 .lut_mask = 16'h7000; -defparam \z80_|execute_|ctl_inc_cy~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~54 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~54_combout = ((\z80_|execute_|ctl_inc_cy~49_combout ) # ((\z80_|execute_|ctl_inc_cy~52_combout ) # (!\z80_|execute_|ctl_inc_cy~37_combout ))) # (!\z80_|execute_|ctl_inc_cy~53_combout ) - - .dataa(\z80_|execute_|ctl_inc_cy~53_combout ), - .datab(\z80_|execute_|ctl_inc_cy~49_combout ), - .datac(\z80_|execute_|ctl_inc_cy~52_combout ), - .datad(\z80_|execute_|ctl_inc_cy~37_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~54_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~54 .lut_mask = 16'hFDFF; -defparam \z80_|execute_|ctl_inc_cy~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~41 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~41_combout = (!\z80_|execute_|ctl_mRead~17_combout & (!\z80_|pla_decode_|Equal34~0_combout & ((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~17_combout ), - .datab(\z80_|pla_decode_|Equal12~1_combout ), - .datac(\z80_|pla_decode_|Equal25~0_combout ), - .datad(\z80_|pla_decode_|Equal34~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~41 .lut_mask = 16'h0045; -defparam \z80_|execute_|ctl_inc_cy~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~58 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~58_combout = (\z80_|execute_|ctl_mRead~4_combout ) # ((\z80_|execute_|ctl_mWrite~6_combout ) # (!\z80_|execute_|ctl_inc_cy~41_combout )) - - .dataa(\z80_|execute_|ctl_mRead~4_combout ), - .datab(\z80_|execute_|ctl_mWrite~6_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_inc_cy~41_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~58_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~58 .lut_mask = 16'hEEFF; -defparam \z80_|execute_|ctl_inc_cy~58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y18_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~55 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~55_combout = (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|execute_|ctl_alu_op_low~8_combout ) # ((\z80_|execute_|ixy_d~9_combout )))) # (!\z80_|pla_decode_|Equal10~0_combout & (\z80_|execute_|ctl_alu_op_low~8_combout & -// ((\z80_|execute_|ctl_mRead~36_combout )))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|execute_|ctl_mRead~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~55_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~55 .lut_mask = 16'hECA8; -defparam \z80_|execute_|ctl_inc_cy~55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y19_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~56 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~56_combout = (((!\z80_|execute_|ctl_reg_sys_we~2_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout )) # (!\z80_|execute_|ctl_reg_sel_pc~17_combout )) # (!\z80_|execute_|fMRead~3_combout ) - - .dataa(\z80_|execute_|fMRead~3_combout ), - .datab(\z80_|execute_|ctl_reg_sel_pc~17_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), - .datad(\z80_|execute_|ctl_reg_sys_we~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~56_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~56 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_inc_cy~56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~89 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~89_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|pla_decode_|Equal41~2_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~30_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|execute_|ctl_bus_inc_oe~30_combout ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|pla_decode_|Equal41~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~89_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~89 .lut_mask = 16'hA020; -defparam \z80_|execute_|ctl_inc_cy~89 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~57 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~57_combout = ((\z80_|execute_|ctl_inc_cy~55_combout ) # ((\z80_|execute_|ctl_inc_cy~56_combout ) # (\z80_|execute_|ctl_inc_cy~89_combout ))) # (!\z80_|execute_|ctl_reg_sel_pc~7_combout ) - - .dataa(\z80_|execute_|ctl_reg_sel_pc~7_combout ), - .datab(\z80_|execute_|ctl_inc_cy~55_combout ), - .datac(\z80_|execute_|ctl_inc_cy~56_combout ), - .datad(\z80_|execute_|ctl_inc_cy~89_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~57_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~57 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_inc_cy~57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y19_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~59 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~59_combout = (\z80_|execute_|ctl_inc_cy~57_combout ) # ((\z80_|execute_|ctl_alu_op_low~8_combout & ((\z80_|execute_|ctl_inc_cy~58_combout ) # (!\z80_|execute_|fMRead~5_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datab(\z80_|execute_|ctl_inc_cy~58_combout ), - .datac(\z80_|execute_|fMRead~5_combout ), - .datad(\z80_|execute_|ctl_inc_cy~57_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~59_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~59 .lut_mask = 16'hFF8A; -defparam \z80_|execute_|ctl_inc_cy~59 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~60 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~60_combout = (\z80_|execute_|pc_inc_hold~38_combout & (\z80_|execute_|pc_inc_hold~35_combout & (\z80_|execute_|ctl_inc_cy~54_combout ))) # (!\z80_|execute_|pc_inc_hold~38_combout & (((\z80_|execute_|ctl_inc_cy~54_combout ) # -// (\z80_|execute_|ctl_inc_cy~59_combout )))) - - .dataa(\z80_|execute_|pc_inc_hold~38_combout ), - .datab(\z80_|execute_|pc_inc_hold~35_combout ), - .datac(\z80_|execute_|ctl_inc_cy~54_combout ), - .datad(\z80_|execute_|ctl_inc_cy~59_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~60_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~60 .lut_mask = 16'hD5D0; -defparam \z80_|execute_|ctl_inc_cy~60 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~47 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~47_combout = (\z80_|execute_|ctl_state_alu~14_combout & (!\z80_|execute_|pc_inc_hold~36_combout & (\z80_|execute_|ctl_alu_op_low~8_combout & !\z80_|execute_|pc_inc_hold~50_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~14_combout ), - .datab(\z80_|execute_|pc_inc_hold~36_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datad(\z80_|execute_|pc_inc_hold~50_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~47 .lut_mask = 16'h0020; -defparam \z80_|execute_|ctl_inc_cy~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~88 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~88_combout = (\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ) # ((\z80_|pla_decode_|Equal13~2_combout & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ))) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~88_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~88 .lut_mask = 16'hECCC; -defparam \z80_|execute_|ctl_inc_cy~88 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~48 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~48_combout = (\z80_|execute_|ctl_inc_cy~47_combout ) # ((\z80_|execute_|ctl_inc_cy~88_combout & ((\z80_|execute_|pc_inc_hold~39_combout ) # (!\z80_|execute_|pc_inc_hold~38_combout )))) - - .dataa(\z80_|execute_|pc_inc_hold~39_combout ), - .datab(\z80_|execute_|ctl_inc_cy~47_combout ), - .datac(\z80_|execute_|ctl_inc_cy~88_combout ), - .datad(\z80_|execute_|pc_inc_hold~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~48 .lut_mask = 16'hECFC; -defparam \z80_|execute_|ctl_inc_cy~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N18 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~40 ( -// Equation(s): -// \z80_|execute_|pc_inc_hold~40_combout = (\z80_|execute_|pc_inc_hold~30_combout & !\z80_|execute_|pc_inc_hold~34_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|pc_inc_hold~30_combout ), - .datac(\z80_|execute_|pc_inc_hold~34_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~40 .lut_mask = 16'h0C0C; -defparam \z80_|execute_|pc_inc_hold~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y19_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~61 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~61_combout = (!\z80_|execute_|pc_inc_hold~36_combout & (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|execute_|ixy_d~9_combout ) # (\z80_|execute_|ctl_alu_op_low~8_combout )))) - - .dataa(\z80_|execute_|ixy_d~9_combout ), - .datab(\z80_|execute_|pc_inc_hold~36_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datad(\z80_|pla_decode_|Equal10~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~61_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~61 .lut_mask = 16'h3200; -defparam \z80_|execute_|ctl_inc_cy~61 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~62 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~62_combout = (\z80_|execute_|ctl_inc_cy~61_combout ) # ((!\z80_|execute_|ctl_inc_cy~42_combout & ((\z80_|execute_|pc_inc_hold~40_combout ) # (!\z80_|execute_|pc_inc_hold~38_combout )))) - - .dataa(\z80_|execute_|pc_inc_hold~38_combout ), - .datab(\z80_|execute_|pc_inc_hold~40_combout ), - .datac(\z80_|execute_|ctl_inc_cy~61_combout ), - .datad(\z80_|execute_|ctl_inc_cy~42_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~62_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~62 .lut_mask = 16'hF0FD; -defparam \z80_|execute_|ctl_inc_cy~62 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y19_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~70 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~70_combout = (\z80_|execute_|ctl_inc_cy~69_combout ) # ((\z80_|execute_|ctl_inc_cy~60_combout ) # ((\z80_|execute_|ctl_inc_cy~48_combout ) # (\z80_|execute_|ctl_inc_cy~62_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~69_combout ), - .datab(\z80_|execute_|ctl_inc_cy~60_combout ), - .datac(\z80_|execute_|ctl_inc_cy~48_combout ), - .datad(\z80_|execute_|ctl_inc_cy~62_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~70_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~70 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_inc_cy~70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~85 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~85_combout = (\z80_|execute_|ctl_inc_cy~73_combout ) # ((\z80_|execute_|ctl_inc_cy~46_combout ) # ((\z80_|execute_|ctl_inc_cy~84_combout ) # (\z80_|execute_|ctl_inc_cy~70_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~73_combout ), - .datab(\z80_|execute_|ctl_inc_cy~46_combout ), - .datac(\z80_|execute_|ctl_inc_cy~84_combout ), - .datad(\z80_|execute_|ctl_inc_cy~70_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~85_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~85 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_inc_cy~85 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N28 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout = \z80_|address_latch_|Q [0] $ (\z80_|execute_|ctl_inc_cy~85_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|address_latch_|Q [0]), - .datad(\z80_|execute_|ctl_inc_cy~85_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out .lut_mask = 16'h0FF0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N8 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~3 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[0]~3_combout = ((\z80_|reg_file_|db_lo_as[0]~1_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[0]~1_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[0]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[0]~3 .lut_mask = 16'hAF2F; -defparam \z80_|reg_file_|db_lo_as[0]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N28 -cycloneive_lcell_comb \z80_|address_latch_|abusz[0] ( -// Equation(s): -// \z80_|address_latch_|abusz [0] = (\z80_|reg_file_|db_lo_as[0]~3_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|reg_file_|db_lo_as[0]~3_combout ), - .datad(\z80_|resets_|clrpc~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [0]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[0] .lut_mask = 16'h00F0; -defparam \z80_|address_latch_|abusz[0] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N22 -cycloneive_lcell_comb \z80_|address_latch_|Q[0]~feeder ( -// Equation(s): -// \z80_|address_latch_|Q[0]~feeder_combout = \z80_|address_latch_|abusz [0] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [0]), - .cin(gnd), - .combout(\z80_|address_latch_|Q[0]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|Q[0]~feeder .lut_mask = 16'hFF00; -defparam \z80_|address_latch_|Q[0]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N23 -dffeas \z80_|address_latch_|Q[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|Q[0]~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[0] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N4 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout = \z80_|address_latch_|Q [0] $ (((\z80_|execute_|ctl_inc_dec~9_combout ) # ((\z80_|execute_|ctl_inc_dec~7_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout )))) - - .dataa(\z80_|execute_|ctl_inc_dec~9_combout ), - .datab(\z80_|execute_|ctl_inc_dec~6_combout ), - .datac(\z80_|address_latch_|Q [0]), - .datad(\z80_|execute_|ctl_inc_dec~7_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 .lut_mask = 16'h0F4B; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y17_N5 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[1]~6_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X31_Y13_N23 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[1]~6_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N22 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~4 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[1]~4_combout = (\z80_|reg_file_|gdfx_temp0[1]~32_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) # (!\z80_|reg_file_|gdfx_temp0[1]~32_combout & -// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [1]), - .datad(\z80_|execute_|ctl_sw_4d~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[1]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[1]~4 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_lo_as[1]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N26 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~5 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[1]~5_combout = (\z80_|reg_file_|db_lo_as[1]~4_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_lo|latch [1]), - .datad(\z80_|reg_file_|db_lo_as[1]~4_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[1]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[1]~5 .lut_mask = 16'hF300; -defparam \z80_|reg_file_|db_lo_as[1]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N24 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout = \z80_|address_latch_|Q [1] $ (((\z80_|execute_|ctl_inc_cy~85_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ))) - - .dataa(\z80_|address_latch_|Q [1]), - .datab(\z80_|execute_|ctl_inc_cy~85_combout ), - .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out .lut_mask = 16'h6A6A; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N4 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~6 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[1]~6_combout = ((\z80_|reg_file_|db_lo_as[1]~5_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[1]~5_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[1]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[1]~6 .lut_mask = 16'hAF2F; -defparam \z80_|reg_file_|db_lo_as[1]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N14 -cycloneive_lcell_comb \z80_|address_latch_|abusz[1] ( -// Equation(s): -// \z80_|address_latch_|abusz [1] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[1]~6_combout ) - - .dataa(gnd), - .datab(\z80_|resets_|clrpc~0_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|db_lo_as[1]~6_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [1]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[1] .lut_mask = 16'h3300; -defparam \z80_|address_latch_|abusz[1] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y17_N19 -dffeas \z80_|address_latch_|Q[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|address_latch_|abusz [1]), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[1] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N6 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout = \z80_|address_latch_|Q [1] $ ((((\z80_|execute_|ctl_inc_dec~10_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )) # (!\z80_|execute_|ctl_inc_dec~5_combout ))) - - .dataa(\z80_|execute_|ctl_inc_dec~5_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .datac(\z80_|address_latch_|Q [1]), - .datad(\z80_|execute_|ctl_inc_dec~10_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4 .lut_mask = 16'h0F87; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N22 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout = \z80_|address_latch_|Q [2] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout & (\z80_|execute_|ctl_inc_cy~85_combout & -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout )))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), - .datab(\z80_|execute_|ctl_inc_cy~85_combout ), - .datac(\z80_|address_latch_|Q [2]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out .lut_mask = 16'h78F0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N16 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~9 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[2]~9_combout = ((\z80_|reg_file_|db_lo_as[2]~8_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|reg_file_|db_lo_as[2]~8_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[2]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[2]~9 .lut_mask = 16'hF575; -defparam \z80_|reg_file_|db_lo_as[2]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N12 -cycloneive_lcell_comb \z80_|address_latch_|abusz[2] ( -// Equation(s): -// \z80_|address_latch_|abusz [2] = (\z80_|reg_file_|db_lo_as[2]~9_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[2]~9_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|resets_|clrpc~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [2]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[2] .lut_mask = 16'h00AA; -defparam \z80_|address_latch_|abusz[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N14 -cycloneive_lcell_comb \z80_|address_latch_|Q[2]~feeder ( -// Equation(s): -// \z80_|address_latch_|Q[2]~feeder_combout = \z80_|address_latch_|abusz [2] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [2]), - .cin(gnd), - .combout(\z80_|address_latch_|Q[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|Q[2]~feeder .lut_mask = 16'hFF00; -defparam \z80_|address_latch_|Q[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y17_N15 -dffeas \z80_|address_latch_|Q[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|Q[2]~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[2] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N2 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout = \z80_|address_latch_|Q [2] $ (((\z80_|execute_|ctl_inc_dec~10_combout ) # ((!\z80_|execute_|ctl_inc_dec~5_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) - - .dataa(\z80_|execute_|ctl_inc_dec~10_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .datac(\z80_|execute_|ctl_inc_dec~5_combout ), - .datad(\z80_|address_latch_|Q [2]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42 .lut_mask = 16'h40BF; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~86 ( -// Equation(s): -// \z80_|execute_|ctl_inc_cy~86_combout = (\z80_|execute_|ctl_inc_cy~73_combout ) # ((\z80_|execute_|ctl_inc_cy~79_combout ) # ((\z80_|execute_|ctl_inc_cy~80_combout ) # (\z80_|execute_|ctl_inc_cy~83_combout ))) - - .dataa(\z80_|execute_|ctl_inc_cy~73_combout ), - .datab(\z80_|execute_|ctl_inc_cy~79_combout ), - .datac(\z80_|execute_|ctl_inc_cy~80_combout ), - .datad(\z80_|execute_|ctl_inc_cy~83_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_cy~86_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_cy~86 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_inc_cy~86 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N0 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout & ((\z80_|execute_|ctl_inc_cy~46_combout ) # ((\z80_|execute_|ctl_inc_cy~86_combout ) # -// (\z80_|execute_|ctl_inc_cy~70_combout )))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), - .datab(\z80_|execute_|ctl_inc_cy~46_combout ), - .datac(\z80_|execute_|ctl_inc_cy~86_combout ), - .datad(\z80_|execute_|ctl_inc_cy~70_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'hAAA8; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~11 ( -// Equation(s): -// \z80_|execute_|ctl_inc_dec~11_combout = (\z80_|execute_|ctl_inc_dec~9_combout ) # (((!\z80_|execute_|ctl_bus_inc_oe~33_combout ) # (!\z80_|execute_|ctl_inc_dec~5_combout )) # (!\z80_|execute_|ctl_inc_dec~6_combout )) - - .dataa(\z80_|execute_|ctl_inc_dec~9_combout ), - .datab(\z80_|execute_|ctl_inc_dec~6_combout ), - .datac(\z80_|execute_|ctl_inc_dec~5_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_inc_dec~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_inc_dec~11 .lut_mask = 16'hBFFF; -defparam \z80_|execute_|ctl_inc_dec~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N0 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout = (\z80_|execute_|ctl_inc_cy~85_combout & ((\z80_|address_latch_|Q [1] & (!\z80_|execute_|ctl_inc_dec~11_combout & \z80_|address_latch_|Q [0])) # (!\z80_|address_latch_|Q -// [1] & (\z80_|execute_|ctl_inc_dec~11_combout & !\z80_|address_latch_|Q [0])))) - - .dataa(\z80_|address_latch_|Q [1]), - .datab(\z80_|execute_|ctl_inc_dec~11_combout ), - .datac(\z80_|address_latch_|Q [0]), - .datad(\z80_|execute_|ctl_inc_cy~85_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0 .lut_mask = 16'h2400; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N10 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout = \z80_|address_latch_|Q [3] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout -// ))) - - .dataa(gnd), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ), - .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ), - .datad(\z80_|address_latch_|Q [3]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out .lut_mask = 16'h3FC0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N15 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y10_N21 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~45 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~45_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [3]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [3]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~45 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[3]~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N26 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp0[3]~52_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y11_N27 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y11_N11 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~48 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~48_combout = (\z80_|reg_file_|b2v_latch_ix_lo|latch [3] & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # (!\z80_|reg_file_|b2v_latch_ix_lo|latch [3] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_ix_lo|latch [3]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc_lo|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~48 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[3]~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y10_N5 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y10_N11 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~49 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~49_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [3]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_iy_lo|latch [3]), - .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~49 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[3]~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N12 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp0[3]~52_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y11_N13 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y11_N27 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~41 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~41_combout = ((!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~23_combout ), - .datac(\z80_|execute_|nextM~2_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~41 .lut_mask = 16'h3F3B; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~42 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~42_combout = ((\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mRead~5_combout ) # (!\z80_|execute_|ctl_al_we~14_combout )))) # (!\z80_|execute_|setM1~29_combout ) - - .dataa(\z80_|execute_|ctl_mRead~5_combout ), - .datab(\z80_|execute_|setM1~29_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_al_we~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~42 .lut_mask = 16'hB3F3; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~43 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~43_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ) # ((!\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout & !\z80_|execute_|rsel3~combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~49_combout ), - .datab(\z80_|execute_|rsel3~combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~43 .lut_mask = 16'hFFF1; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~44 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~44_combout = ((\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ) # ((!\z80_|execute_|rsel0~combout & \z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~52_combout ), - .datab(\z80_|execute_|rsel0~combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~44 .lut_mask = 16'hF7F5; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~45 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~45_combout = ((\z80_|execute_|ctl_state_alu~5_combout & ((!\z80_|execute_|setM1~46_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout )))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), - .datab(\z80_|execute_|ctl_state_alu~5_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), - .datad(\z80_|execute_|setM1~46_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~45 .lut_mask = 16'h5DDD; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~46 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout = ((\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ) # (!\z80_|execute_|ctl_reg_gp_we~2_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~53_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~46 .lut_mask = 16'hFDFF; -defparam \z80_|execute_|ctl_reg_gp_hilo[1]~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N14 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_48 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_48~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_de~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_de~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_48 .lut_mask = 16'h0C00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N20 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_44 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_44~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_de2~4_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_de2~4_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_44 .lut_mask = 16'h0C00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N4 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_45 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_45~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_de2~4_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_de2~4_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_45 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y13_N15 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N6 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_49 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_49~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_de~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_de~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_49 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y13_N1 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~40 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~40_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [3]), - .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [3]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~40 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[3]~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N12 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_52 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_52~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl2~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_52 .lut_mask = 16'h0C00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N18 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_57 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_57~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_57 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N9 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N16 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_53 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_53~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl2~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_53 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N19 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N30 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_56 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_56~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_hl~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_56 .lut_mask = 16'h0C00; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~41 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~41_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [3]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [3]), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~41 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp1[3]~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N26 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_33 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_33~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|reg_control_|reg_sel_af~0_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datad(\z80_|reg_control_|reg_sel_af~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_33 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y14_N5 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N4 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[3]~18 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[3]~18_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [3]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [3]), - .datad(\z80_|reg_control_|reg_sel_af~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[3]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[3]~18 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[3]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~11 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~11_combout = (((\z80_|pla_decode_|Equal9~1_combout & \z80_|execute_|ixy_d~6_combout )) # (!\z80_|execute_|ctl_reg_in_hi~5_combout )) # (!\z80_|execute_|ctl_reg_in_hi~6_combout ) - - .dataa(\z80_|pla_decode_|Equal9~1_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~6_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~11 .lut_mask = 16'hB3FF; -defparam \z80_|execute_|ctl_reg_in_hi~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~12 ( -// Equation(s): -// \z80_|execute_|ctl_reg_in_hi~12_combout = (\z80_|execute_|ctl_reg_in_hi~11_combout ) # (((!\z80_|execute_|ctl_reg_in_hi~4_combout ) # (!\z80_|execute_|ctl_reg_in_hi~3_combout )) # (!\z80_|execute_|ctl_reg_in_hi~10_combout )) - - .dataa(\z80_|execute_|ctl_reg_in_hi~11_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~10_combout ), - .datac(\z80_|execute_|ctl_reg_in_hi~3_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_in_hi~12 .lut_mask = 16'hBFFF; -defparam \z80_|execute_|ctl_reg_in_hi~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N12 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_29 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_29~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_af2~0_combout & \z80_|execute_|ctl_reg_gp_we~6_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datab(gnd), - .datac(\z80_|reg_control_|reg_sel_af2~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_29 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y11_N19 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N2 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_28 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_28~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & (\z80_|reg_control_|reg_sel_af2~0_combout & !\z80_|execute_|ctl_reg_gp_we~6_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datab(gnd), - .datac(\z80_|reg_control_|reg_sel_af2~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_28 .lut_mask = 16'h00A0; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~44 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~44_combout = (\z80_|alu_|db[3]~11_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[3]~11_combout & (!\z80_|execute_|ctl_reg_in_hi~12_combout & -// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|alu_|db[3]~11_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~44 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[3]~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N8 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp1[3]~48_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N12 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_69 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_69~combout = (\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & \z80_|reg_control_|reg_sel_iy~2_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datad(\z80_|reg_control_|reg_sel_iy~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y12_N9 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N24 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout = (!\z80_|execute_|ctl_reg_gp_we~6_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(gnd), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 .lut_mask = 16'h4444; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N2 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|decode_state_|DFFE_inst4~q & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|decode_state_|DFFE_inst4~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 .lut_mask = 16'h4000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N8 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & \z80_|execute_|ctl_reg_gp_we~6_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datad(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 .lut_mask = 16'hF000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N4 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout = (\z80_|decode_state_|DFFE_inst4~q & (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 .lut_mask = 16'h0080; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y12_N29 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N14 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_68 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_68~combout = (!\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout & \z80_|reg_control_|reg_sel_iy~2_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datad(\z80_|reg_control_|reg_sel_iy~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68 .lut_mask = 16'h3000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~43 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~43_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [3] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [3] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [3]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~43 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[3]~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N20 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y12_N22 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout = (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y15_N23 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~31 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~31_combout = (!\z80_|ir_|opcode [3] & ((\z80_|execute_|ctl_alu_op_low~14_combout ) # ((\z80_|pla_decode_|Equal48~0_combout & \z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal48~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|execute_|ctl_eval_cond~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~31 .lut_mask = 16'h5450; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~30 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~30_combout = ((\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ) # ((\z80_|pla_decode_|Equal35~0_combout & \z80_|execute_|ixy_d~6_combout ))) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ) - - .dataa(\z80_|pla_decode_|Equal35~0_combout ), - .datab(\z80_|execute_|ctl_reg_in_lo~9_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~30 .lut_mask = 16'hFFB3; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~32 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~32_combout = (((\z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ) # (\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout )) # (!\z80_|execute_|ctl_reg_out_hi~4_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), - .datab(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~32 .lut_mask = 16'hFFF7; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~33 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo[1]~33_combout = ((\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ) # ((!\z80_|execute_|ctl_reg_in_hi~5_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ))) # (!\z80_|execute_|ctl_reg_sel_wz~12_combout ) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~12_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), - .datad(\z80_|execute_|ctl_reg_in_hi~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~33 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_reg_sys_hilo[1]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N30 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_hi~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_hi~0_combout = ((\z80_|execute_|ixy_d~6_combout & ((\z80_|pla_decode_|Equal19~0_combout ) # (\z80_|execute_|ctl_reg_sys_we_lo~3_combout )))) # (!\z80_|execute_|ctl_reg_sel_wz~13_combout ) - - .dataa(\z80_|pla_decode_|Equal19~0_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~13_combout ), - .datac(\z80_|execute_|ctl_reg_sys_we_lo~3_combout ), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_hi~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_hi~0 .lut_mask = 16'hFB33; -defparam \z80_|reg_control_|reg_sys_we_hi~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N14 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_hi ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_hi~combout = ((\z80_|reg_control_|reg_sys_we_hi~0_combout ) # (\z80_|execute_|ctl_reg_sys_we~3_combout )) # (!\z80_|execute_|ctl_reg_in_hi~4_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_in_hi~4_combout ), - .datac(\z80_|reg_control_|reg_sys_we_hi~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_we~3_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_hi~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_hi .lut_mask = 16'hFFF3; -defparam \z80_|reg_control_|reg_sys_we_hi .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N4 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_81 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_81~combout = (\z80_|execute_|ctl_reg_sel_wz~17_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & \z80_|reg_control_|reg_sys_we_hi~combout )) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~17_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_81 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y12_N27 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N22 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_80 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_80~combout = (\z80_|execute_|ctl_reg_sel_wz~17_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & !\z80_|reg_control_|reg_sys_we_hi~combout )) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~17_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_80 .lut_mask = 16'h00A0; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~45 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~45_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [3]), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~45_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~45 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[3]~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N6 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & (!\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), - .datab(\z80_|reg_control_|bank_exx~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 .lut_mask = 16'h0002; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y13_N1 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N10 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|reg_control_|bank_exx~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 .lut_mask = 16'h0400; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N16 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & (\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), - .datab(\z80_|reg_control_|bank_exx~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 .lut_mask = 16'h0008; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y13_N3 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y15_N4 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout = (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), - .datab(\z80_|reg_control_|bank_exx~q ), - .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 .lut_mask = 16'h0100; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~42 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~42_combout = (\z80_|reg_file_|b2v_latch_bc_hi|latch [3] & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_hi|latch [3] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc_hi|latch [3]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~42 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[3]~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~46 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~46_combout = (\z80_|reg_file_|gdfx_temp1[3]~44_combout & (\z80_|reg_file_|gdfx_temp1[3]~43_combout & (\z80_|reg_file_|gdfx_temp1[3]~45_combout & \z80_|reg_file_|gdfx_temp1[3]~42_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[3]~44_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[3]~43_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[3]~45_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[3]~42_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~46 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[3]~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~47 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~47_combout = (\z80_|reg_file_|gdfx_temp1[3]~40_combout & (\z80_|reg_file_|gdfx_temp1[3]~41_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[3]~18_combout & \z80_|reg_file_|gdfx_temp1[3]~46_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[3]~40_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[3]~41_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|db[3]~18_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[3]~46_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~47 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[3]~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~17 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~17_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ) # ((\z80_|reg_control_|reg_sel_af~0_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) - - .dataa(\z80_|reg_control_|reg_sel_af~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~17 .lut_mask = 16'hFFF8; -defparam \z80_|reg_file_|gdfx_temp1[0]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~18 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~18_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~18 .lut_mask = 16'hFEFE; -defparam \z80_|reg_file_|gdfx_temp1[0]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~19 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~19_combout = (\z80_|reg_file_|gdfx_temp1[0]~17_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ) # ((\z80_|reg_file_|gdfx_temp1[0]~18_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~17_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[0]~18_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~19 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp1[0]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~16 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~16_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~16 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp1[0]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y13_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~20 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~20_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout ) # ((\z80_|reg_file_|gdfx_temp1[0]~19_combout ) # ((\z80_|execute_|ctl_sw_4u~6_combout ) # (\z80_|reg_file_|gdfx_temp1[0]~16_combout ))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~19_combout ), - .datac(\z80_|execute_|ctl_sw_4u~6_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[0]~16_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~20 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp1[0]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N10 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_73 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_73~combout = (\z80_|reg_control_|reg_sel_pc~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & \z80_|reg_control_|reg_sys_we_hi~combout )) - - .dataa(\z80_|reg_control_|reg_sel_pc~combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_73 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N13 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[1]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y13_N19 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y13_N25 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~8 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~8_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [1]), - .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [1]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~8 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[1]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y14_N3 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N2 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[1]~15 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[1]~15_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [1]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [1]), - .datad(\z80_|reg_control_|reg_sel_af~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[1]~15 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y15_N9 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y12_N11 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~13 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~13_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [1]), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~13 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[1]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y11_N21 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~12 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~12_combout = (\z80_|alu_|db[1]~13_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[1]~13_combout & (!\z80_|execute_|ctl_reg_in_hi~12_combout & -// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|alu_|db[1]~13_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~12 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[1]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y13_N5 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y13_N31 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~10 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~10_combout = (\z80_|reg_file_|b2v_latch_bc_hi|latch [1] & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_hi|latch [1] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc_hi|latch [1]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~10 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[1]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y12_N21 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N28 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder_combout = \z80_|reg_file_|gdfx_temp1[1]~21_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y12_N29 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~11 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~11_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [1]), - .datad(\z80_|reg_file_|b2v_latch_iy_hi|latch [1]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~11 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[1]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~14 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~14_combout = (\z80_|reg_file_|gdfx_temp1[1]~13_combout & (\z80_|reg_file_|gdfx_temp1[1]~12_combout & (\z80_|reg_file_|gdfx_temp1[1]~10_combout & \z80_|reg_file_|gdfx_temp1[1]~11_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[1]~13_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[1]~12_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[1]~10_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[1]~11_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~14 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[1]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N15 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y14_N17 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~9 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~9_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [1]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [1]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~9 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[1]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~15 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~15_combout = (\z80_|reg_file_|gdfx_temp1[1]~8_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[1]~15_combout & (\z80_|reg_file_|gdfx_temp1[1]~14_combout & \z80_|reg_file_|gdfx_temp1[1]~9_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[1]~8_combout ), - .datab(\z80_|reg_file_|b2v_latch_af_hi|db[1]~15_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[1]~14_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[1]~9_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~15 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~21 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[1]~21_combout = ((\z80_|reg_file_|gdfx_temp1[1]~15_combout & ((\z80_|reg_file_|db_hi_as[1]~3_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[1]~15_combout ), - .datac(\z80_|reg_file_|db_hi_as[1]~3_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[1]~21 .lut_mask = 16'hD5DD; -defparam \z80_|reg_file_|gdfx_temp1[1]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N28 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_60 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_60~combout = (!\z80_|reg_control_|reg_sys_we_hi~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & \z80_|execute_|ctl_reg_sel_ir~1_combout )) - - .dataa(\z80_|reg_control_|reg_sys_we_hi~combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datad(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_60 .lut_mask = 16'h5000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_60 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N16 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_61 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_61~combout = (\z80_|reg_control_|reg_sys_we_hi~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & \z80_|execute_|ctl_reg_sel_ir~1_combout )) - - .dataa(\z80_|reg_control_|reg_sys_we_hi~combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datad(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_61 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_61 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y15_N17 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[1]~3_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N6 -cycloneive_lcell_comb \z80_|reg_control_|reg_sw_4d_hi~0 ( -// Equation(s): -// \z80_|reg_control_|reg_sw_4d_hi~0_combout = (\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_control_|reg_sys_we_lo~combout ) # ((!\z80_|execute_|ctl_reg_sel_ir~1_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout )))) - - .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), - .datab(\z80_|reg_control_|reg_sys_we_lo~combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datad(\z80_|execute_|ctl_reg_sel_ir~1_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sw_4d_hi~0 .lut_mask = 16'h8AAA; -defparam \z80_|reg_control_|reg_sw_4d_hi~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N16 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~0 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[1]~0_combout = (\z80_|reg_file_|gdfx_temp1[1]~21_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) # (!\z80_|reg_file_|gdfx_temp1[1]~21_combout & -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [1]), - .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[1]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[1]~0 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_hi_as[1]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N12 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_72 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_72~combout = (\z80_|reg_control_|reg_sel_pc~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout & !\z80_|reg_control_|reg_sys_we_hi~combout )) - - .dataa(\z80_|reg_control_|reg_sel_pc~combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), - .datad(\z80_|reg_control_|reg_sys_we_hi~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_72 .lut_mask = 16'h00A0; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_72 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N10 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~1 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[1]~1_combout = (\z80_|reg_file_|db_hi_as[1]~0_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|b2v_latch_pc_hi|latch [1]), - .datab(gnd), - .datac(\z80_|reg_file_|db_hi_as[1]~0_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[1]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[1]~1 .lut_mask = 16'hA0F0; -defparam \z80_|reg_file_|db_hi_as[1]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N30 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~2 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[0]~2_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ) # ((\z80_|execute_|ctl_bus_inc_oe~41_combout ) # (\z80_|reg_control_|reg_sw_4d_hi~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[0]~2 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|db_hi_as[0]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N2 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout = \z80_|address_latch_|Q [8] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout & (\z80_|address_latch_|Q [7] $ (\z80_|execute_|ctl_inc_dec~11_combout ))))) - - .dataa(\z80_|address_latch_|Q [7]), - .datab(\z80_|address_latch_|Q [8]), - .datac(\z80_|execute_|ctl_inc_dec~11_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out .lut_mask = 16'h96CC; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y15_N27 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[0]~6_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y14_N3 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y14_N1 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~23 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~23_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [0]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [0]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~23 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[0]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y13_N7 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y13_N29 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~22 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~22_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [0]), - .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [0]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~22 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[0]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y13_N21 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y13_N7 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~24 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~24_combout = (\z80_|reg_file_|b2v_latch_bc2_hi|latch [0] & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # (!\z80_|reg_file_|b2v_latch_bc2_hi|latch [0] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc_hi|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~24 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[0]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y11_N15 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~26 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~26_combout = (\z80_|alu_|db[0]~19_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[0]~19_combout & (!\z80_|execute_|ctl_reg_in_hi~12_combout & -// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|alu_|db[0]~19_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~26 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[0]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N26 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder_combout = \z80_|reg_file_|gdfx_temp1[0]~30_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y12_N27 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y12_N5 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~25 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~25_combout = (\z80_|reg_file_|b2v_latch_ix_hi|latch [0] & (((\z80_|reg_file_|b2v_latch_iy_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ))) # (!\z80_|reg_file_|b2v_latch_ix_hi|latch [0] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & ((\z80_|reg_file_|b2v_latch_iy_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_ix_hi|latch [0]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datac(\z80_|reg_file_|b2v_latch_iy_hi|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~25 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[0]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y14_N13 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X26_Y14_N7 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~27 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~27_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (\z80_|reg_file_|b2v_latch_wz_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (((\z80_|reg_file_|b2v_latch_sp_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_sp_hi|latch [0]), - .datad(\z80_|reg_file_|b2v_latch_wz_hi|latch [0]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~27 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[0]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~28 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~28_combout = (\z80_|reg_file_|gdfx_temp1[0]~24_combout & (\z80_|reg_file_|gdfx_temp1[0]~26_combout & (\z80_|reg_file_|gdfx_temp1[0]~25_combout & \z80_|reg_file_|gdfx_temp1[0]~27_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~24_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~26_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[0]~25_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[0]~27_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~28 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[0]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y14_N29 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N28 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[0]~16 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[0]~16_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [0]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [0]), - .datad(\z80_|reg_control_|reg_sel_af~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[0]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[0]~16 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[0]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~29 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~29_combout = (\z80_|reg_file_|gdfx_temp1[0]~23_combout & (\z80_|reg_file_|gdfx_temp1[0]~22_combout & (\z80_|reg_file_|gdfx_temp1[0]~28_combout & \z80_|reg_file_|b2v_latch_af_hi|db[0]~16_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~23_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~22_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[0]~28_combout ), - .datad(\z80_|reg_file_|b2v_latch_af_hi|db[0]~16_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~29 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[0]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y14_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~30 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[0]~30_combout = ((\z80_|reg_file_|gdfx_temp1[0]~29_combout & ((\z80_|reg_file_|db_hi_as[0]~6_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|db_hi_as[0]~6_combout ), - .datab(\z80_|execute_|ctl_sw_4u~6_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[0]~29_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[0]~30 .lut_mask = 16'hBF0F; -defparam \z80_|reg_file_|gdfx_temp1[0]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y15_N21 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[0]~6_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[0] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N20 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~4 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[0]~4_combout = (\z80_|reg_control_|reg_sw_4d_hi~0_combout & (\z80_|reg_file_|gdfx_temp1[0]~30_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) - - .dataa(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [0]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[0]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[0]~4 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|db_hi_as[0]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N24 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~5 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[0]~5_combout = (\z80_|reg_file_|db_hi_as[0]~4_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datab(gnd), - .datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [0]), - .datad(\z80_|reg_file_|db_hi_as[0]~4_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[0]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[0]~5 .lut_mask = 16'hF500; -defparam \z80_|reg_file_|db_hi_as[0]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N26 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~6 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[0]~6_combout = ((\z80_|reg_file_|db_hi_as[0]~5_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), - .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datad(\z80_|reg_file_|db_hi_as[0]~5_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[0]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[0]~6 .lut_mask = 16'hDF0F; -defparam \z80_|reg_file_|db_hi_as[0]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N8 -cycloneive_lcell_comb \z80_|address_latch_|abusz[8] ( -// Equation(s): -// \z80_|address_latch_|abusz [8] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[0]~6_combout ) - - .dataa(\z80_|resets_|clrpc~0_combout ), - .datab(gnd), - .datac(\z80_|reg_file_|db_hi_as[0]~6_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [8]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[8] .lut_mask = 16'h5050; -defparam \z80_|address_latch_|abusz[8] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y16_N9 -dffeas \z80_|address_latch_|Q[8] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [8]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [8]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[8] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N18 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout & ((\z80_|address_latch_|Q [7] & (\z80_|address_latch_|Q [8] & !\z80_|execute_|ctl_inc_dec~11_combout -// )) # (!\z80_|address_latch_|Q [7] & (!\z80_|address_latch_|Q [8] & \z80_|execute_|ctl_inc_dec~11_combout )))) - - .dataa(\z80_|address_latch_|Q [7]), - .datab(\z80_|address_latch_|Q [8]), - .datac(\z80_|execute_|ctl_inc_dec~11_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 .lut_mask = 16'h1800; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N20 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout = \z80_|address_latch_|Q [9] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|address_latch_|Q [9]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out .lut_mask = 16'h0FF0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N12 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~3 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[1]~3_combout = ((\z80_|reg_file_|db_hi_as[1]~1_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_hi_as[1]~1_combout ), - .datab(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[1]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[1]~3 .lut_mask = 16'hBB3B; -defparam \z80_|reg_file_|db_hi_as[1]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N24 -cycloneive_lcell_comb \z80_|address_latch_|abusz[9] ( -// Equation(s): -// \z80_|address_latch_|abusz [9] = (\z80_|reg_file_|db_hi_as[1]~3_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(gnd), - .datab(\z80_|reg_file_|db_hi_as[1]~3_combout ), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [9]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[9] .lut_mask = 16'h0C0C; -defparam \z80_|address_latch_|abusz[9] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N4 -cycloneive_lcell_comb \z80_|address_latch_|Q[9]~feeder ( -// Equation(s): -// \z80_|address_latch_|Q[9]~feeder_combout = \z80_|address_latch_|abusz [9] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [9]), - .cin(gnd), - .combout(\z80_|address_latch_|Q[9]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|Q[9]~feeder .lut_mask = 16'hFF00; -defparam \z80_|address_latch_|Q[9]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N5 -dffeas \z80_|address_latch_|Q[9] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|Q[9]~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [9]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[9] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[9] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N30 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout = \z80_|address_latch_|Q [10] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout & (\z80_|address_latch_|Q [9] $ -// (\z80_|execute_|ctl_inc_dec~11_combout ))))) - - .dataa(\z80_|address_latch_|Q [10]), - .datab(\z80_|address_latch_|Q [9]), - .datac(\z80_|execute_|ctl_inc_dec~11_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out .lut_mask = 16'h96AA; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N7 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y14_N13 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~32 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~32_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [2]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [2]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~32 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[2]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y11_N25 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~35 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~35_combout = (\z80_|alu_|db[2]~15_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[2]~15_combout & (!\z80_|execute_|ctl_reg_in_hi~12_combout & -// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|alu_|db[2]~15_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~35 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[2]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y12_N19 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N18 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp1[2]~39_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y12_N19 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~34 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~34_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [2]), - .datad(\z80_|reg_file_|b2v_latch_iy_hi|latch [2]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~34 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[2]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N16 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp1[2]~39_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y13_N17 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y13_N15 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~33 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~33_combout = (\z80_|reg_file_|b2v_latch_bc_hi|latch [2] & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_hi|latch [2] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc_hi|latch [2]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~33 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[2]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y15_N21 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y12_N1 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~36 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~36_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [2]), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~36 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[2]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~37 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~37_combout = (\z80_|reg_file_|gdfx_temp1[2]~35_combout & (\z80_|reg_file_|gdfx_temp1[2]~34_combout & (\z80_|reg_file_|gdfx_temp1[2]~33_combout & \z80_|reg_file_|gdfx_temp1[2]~36_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[2]~35_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[2]~34_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[2]~33_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[2]~36_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~37 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[2]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y13_N5 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y13_N31 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~31 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~31_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datab(\z80_|reg_file_|b2v_latch_de_hi|latch [2]), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [2]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~31 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[2]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y14_N23 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N22 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[2]~17 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[2]~17_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [2]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [2]), - .datad(\z80_|reg_control_|reg_sel_af~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[2]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[2]~17 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[2]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y12_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~38 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~38_combout = (\z80_|reg_file_|gdfx_temp1[2]~32_combout & (\z80_|reg_file_|gdfx_temp1[2]~37_combout & (\z80_|reg_file_|gdfx_temp1[2]~31_combout & \z80_|reg_file_|b2v_latch_af_hi|db[2]~17_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[2]~32_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[2]~37_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[2]~31_combout ), - .datad(\z80_|reg_file_|b2v_latch_af_hi|db[2]~17_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~38 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[2]~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~39 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[2]~39_combout = ((\z80_|reg_file_|gdfx_temp1[2]~38_combout & ((\z80_|reg_file_|db_hi_as[2]~9_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[2]~38_combout ), - .datab(\z80_|reg_file_|db_hi_as[2]~9_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[2]~39 .lut_mask = 16'h8FAF; -defparam \z80_|reg_file_|gdfx_temp1[2]~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y15_N19 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[2]~9_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N18 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~7 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[2]~7_combout = (\z80_|reg_file_|gdfx_temp1[2]~39_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) # (!\z80_|reg_file_|gdfx_temp1[2]~39_combout & -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [2]), - .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[2]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[2]~7 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_hi_as[2]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y15_N9 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[2]~9_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[2] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N2 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~8 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[2]~8_combout = (\z80_|reg_file_|db_hi_as[2]~7_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datab(\z80_|reg_file_|db_hi_as[2]~7_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|b2v_latch_pc_hi|latch [2]), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[2]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[2]~8 .lut_mask = 16'hCC44; -defparam \z80_|reg_file_|db_hi_as[2]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N8 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~9 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[2]~9_combout = ((\z80_|reg_file_|db_hi_as[2]~8_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), - .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datad(\z80_|reg_file_|db_hi_as[2]~8_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[2]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[2]~9 .lut_mask = 16'hDF0F; -defparam \z80_|reg_file_|db_hi_as[2]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y15_N0 -cycloneive_lcell_comb \z80_|address_latch_|abusz[10] ( -// Equation(s): -// \z80_|address_latch_|abusz [10] = (\z80_|reg_file_|db_hi_as[2]~9_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|reg_file_|db_hi_as[2]~9_combout ), - .datad(\z80_|resets_|clrpc~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [10]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[10] .lut_mask = 16'h00F0; -defparam \z80_|address_latch_|abusz[10] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N26 -cycloneive_lcell_comb \z80_|address_latch_|Q[10]~feeder ( -// Equation(s): -// \z80_|address_latch_|Q[10]~feeder_combout = \z80_|address_latch_|abusz [10] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [10]), - .cin(gnd), - .combout(\z80_|address_latch_|Q[10]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|Q[10]~feeder .lut_mask = 16'hFF00; -defparam \z80_|address_latch_|Q[10]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N27 -dffeas \z80_|address_latch_|Q[10] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|Q[10]~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [10]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[10] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[10] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N10 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout & ((\z80_|address_latch_|Q [10] & (\z80_|address_latch_|Q [9] & -// !\z80_|execute_|ctl_inc_dec~11_combout )) # (!\z80_|address_latch_|Q [10] & (!\z80_|address_latch_|Q [9] & \z80_|execute_|ctl_inc_dec~11_combout )))) - - .dataa(\z80_|address_latch_|Q [10]), - .datab(\z80_|address_latch_|Q [9]), - .datac(\z80_|execute_|ctl_inc_dec~11_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 .lut_mask = 16'h1800; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N14 -cycloneive_lcell_comb \z80_|address_latch_|abusz[11] ( -// Equation(s): -// \z80_|address_latch_|abusz [11] = (\z80_|reg_file_|db_hi_as[3]~12_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(gnd), - .datab(\z80_|reg_file_|db_hi_as[3]~12_combout ), - .datac(gnd), - .datad(\z80_|resets_|clrpc~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [11]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[11] .lut_mask = 16'h00CC; -defparam \z80_|address_latch_|abusz[11] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N15 -dffeas \z80_|address_latch_|Q[11] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [11]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [11]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[11] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[11] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N12 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[11] ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|address [11] = \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout $ (\z80_|address_latch_|Q [11]) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), - .datab(gnd), - .datac(\z80_|address_latch_|Q [11]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[11] .lut_mask = 16'h5A5A; -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[11] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N31 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[3]~12_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y15_N31 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[3]~12_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N30 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~10 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[3]~10_combout = (\z80_|reg_file_|gdfx_temp1[3]~48_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) # (!\z80_|reg_file_|gdfx_temp1[3]~48_combout & -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [3]), - .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[3]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[3]~10 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_hi_as[3]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N0 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~11 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[3]~11_combout = (\z80_|reg_file_|db_hi_as[3]~10_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|b2v_latch_pc_hi|latch [3]), - .datab(gnd), - .datac(\z80_|reg_file_|db_hi_as[3]~10_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[3]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[3]~11 .lut_mask = 16'hA0F0; -defparam \z80_|reg_file_|db_hi_as[3]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N30 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~12 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[3]~12_combout = ((\z80_|reg_file_|db_hi_as[3]~11_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [11]) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datad(\z80_|reg_file_|db_hi_as[3]~11_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[3]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[3]~12 .lut_mask = 16'hBF0F; -defparam \z80_|reg_file_|db_hi_as[3]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~48 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[3]~48_combout = ((\z80_|reg_file_|gdfx_temp1[3]~47_combout & ((\z80_|reg_file_|db_hi_as[3]~12_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[3]~47_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datac(\z80_|reg_file_|db_hi_as[3]~12_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[3]~48 .lut_mask = 16'hB3BB; -defparam \z80_|reg_file_|gdfx_temp1[3]~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N16 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & ((\z80_|alu_|db_low[3]~11_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~43_combout & !\z80_|alu_|db_high[3]~2_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .datab(\z80_|alu_|db_low[3]~11_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datad(\z80_|alu_|db_high[3]~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9 .lut_mask = 16'h888A; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_low ( -// Equation(s): -// \z80_|execute_|ctl_alu_op1_sel_low~combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ixy_d~9_combout ) # ((\z80_|execute_|ixy_d~7_combout & !\z80_|ir_|opcode [3])))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op1_sel_low .lut_mask = 16'hC0E0; -defparam \z80_|execute_|ctl_alu_op1_sel_low .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N6 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[3] ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_high|Q [3] = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & (\z80_|alu_|db_high[3]~8_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .datac(\z80_|alu_|db_high[3]~8_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [3]), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[3] .lut_mask = 16'h00C0; -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[3] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y10_N7 -dffeas \z80_|alu_|op1_high[3] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [3]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_high [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_high[3] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_high[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N10 -cycloneive_lcell_comb \z80_|alu_|alu_op1[3]~3 ( -// Equation(s): -// \z80_|alu_|alu_op1[3]~3_combout = (\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [3]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [3])) - - .dataa(gnd), - .datab(\z80_|alu_|op1_high [3]), - .datac(\z80_|alu_|op1_low [3]), - .datad(\z80_|execute_|ctl_alu_op_low~combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_op1[3]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op1[3]~3 .lut_mask = 16'hF0CC; -defparam \z80_|alu_|alu_op1[3]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N16 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout = (!\z80_|alu_|alu_op2[2]~0_combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_low [2]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_high -// [2])))) - - .dataa(\z80_|alu_|op1_high [2]), - .datab(\z80_|alu_|op1_low [2]), - .datac(\z80_|alu_|alu_op2[2]~0_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h0305; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~6_combout = ((\z80_|pla_decode_|Equal8~0_combout & (\z80_|execute_|ixy_d~5_combout & \z80_|execute_|ctl_mWrite~2_combout ))) # (!\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ) - - .dataa(\z80_|pla_decode_|Equal8~0_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ), - .datad(\z80_|execute_|ctl_mWrite~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~6 .lut_mask = 16'h8F0F; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~10_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ixy_d~15_combout & ((\z80_|execute_|ctl_bus_db_oe~1_combout ) # (!\z80_|sequencer_|DFFE_M3_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|execute_|ctl_bus_db_oe~1_combout ), - .datad(\z80_|execute_|ixy_d~15_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~10 .lut_mask = 16'hAAFB; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~0 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~0_combout = (\z80_|pla_decode_|Equal1~5_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal13~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~5_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|pla_decode_|Equal13~0_combout ), - .datad(\z80_|pla_decode_|Equal13~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~0 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_alu_core_R~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~5_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|execute_|ctl_alu_core_R~0_combout & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T3_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datad(\z80_|execute_|ctl_alu_core_R~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~5 .lut_mask = 16'hFEF0; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~7 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~7_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ) # (((\z80_|execute_|ctl_alu_op2_sel_bus~5_combout ) # (!\z80_|execute_|ctl_reg_use_sp~1_combout )) # (!\z80_|execute_|ctl_alu_op2_sel_bus~10_combout )) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), - .datab(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), - .datac(\z80_|execute_|ctl_reg_use_sp~1_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~7 .lut_mask = 16'hFFBF; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op2_sel_bus~8_combout = ((\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ) # ((\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_alu_shift_oe~14_combout ))) # (!\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op2_sel_bus~8 .lut_mask = 16'hFF8F; -defparam \z80_|execute_|ctl_alu_op2_sel_bus~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N4 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout = (\z80_|alu_|db_low[1]~17_combout & ((\z80_|execute_|ctl_alu_op2_sel_lq~combout ) # ((\z80_|alu_|db_high[1]~20_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) # -// (!\z80_|alu_|db_low[1]~17_combout & (((\z80_|alu_|db_high[1]~20_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) - - .dataa(\z80_|alu_|db_low[1]~17_combout ), - .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datac(\z80_|alu_|db_high[1]~20_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5 .lut_mask = 16'hF888; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N0 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout ) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datab(gnd), - .datac(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6 .lut_mask = 16'h5050; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N16 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|ena ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|ena~combout = (\z80_|execute_|ctl_alu_op2_sel_zero~combout ) # ((\z80_|execute_|ctl_alu_op2_sel_lq~combout ) # (\z80_|execute_|ctl_alu_op2_sel_bus~8_combout )) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|ena .lut_mask = 16'hFFFA; -defparam \z80_|alu_|b2v_op2_latch_mux_high|ena .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y10_N1 -dffeas \z80_|alu_|op2_high[1] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_high [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_high[1] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_high[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N22 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[1] ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_high|Q [1] = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & (\z80_|alu_|db_high[1]~20_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .datac(\z80_|alu_|db_high[1]~20_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [1]), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[1] .lut_mask = 16'h00C0; -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[1] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y10_N23 -dffeas \z80_|alu_|op1_high[1] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [1]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_high [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_high[1] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_high[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N28 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [1])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [1]))))) - - .dataa(\z80_|alu_|op1_low [1]), - .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datac(\z80_|execute_|ctl_alu_op_low~combout ), - .datad(\z80_|alu_|op1_high [1]), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 .lut_mask = 16'h8C80; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N20 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ) # ((\z80_|alu_|db_low[1]~17_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datab(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4_combout ), - .datac(\z80_|alu_|db_low[1]~17_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 .lut_mask = 16'h5444; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y10_N21 -dffeas \z80_|alu_|op2_low[1] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_low [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_low[1] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_low[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~6 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~6_combout = (((!\z80_|nM1_int~2_combout & !\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal63~0_combout )) # (!\z80_|pla_decode_|Equal32~0_combout ) - - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal63~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~6 .lut_mask = 16'h57FF; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~20 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~20_combout = (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|pla_decode_|Equal68~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal68~2_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~20 .lut_mask = 16'h0D0F; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~12 ( -// Equation(s): -// \z80_|execute_|ctl_state_alu~12_combout = (\z80_|execute_|ctl_state_alu~9_combout ) # ((\z80_|execute_|ctl_reg_gp_sel~36_combout ) # ((\z80_|execute_|ctl_state_alu~11_combout ) # (!\z80_|execute_|ctl_state_alu~8_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~9_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel~36_combout ), - .datac(\z80_|execute_|ctl_state_alu~11_combout ), - .datad(\z80_|execute_|ctl_state_alu~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_state_alu~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_state_alu~12 .lut_mask = 16'hFEFF; -defparam \z80_|execute_|ctl_state_alu~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~18 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~18_combout = ((!\z80_|pla_decode_|Equal3~0_combout & ((\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal21~0_combout )))) # (!\z80_|execute_|ctl_state_alu~12_combout ) - - .dataa(\z80_|execute_|ctl_state_alu~12_combout ), - .datab(\z80_|pla_decode_|Equal3~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal21~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~18 .lut_mask = 16'h7577; -defparam \z80_|execute_|ctl_alu_core_hf~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N0 -cycloneive_lcell_comb \z80_|pla_decode_|Equal61~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal61~2_combout = (\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal6~0_combout & (!\z80_|ir_|opcode [1] & \z80_|ir_|opcode [0]))) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [0]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal61~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal61~2 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal61~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~16 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~16_combout = (\z80_|pla_decode_|Equal61~2_combout & ((\z80_|sequencer_|DFFE_M2_ff~q ) # (\z80_|sequencer_|DFFE_M4_ff~q ))) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M4_ff~q ), - .datad(\z80_|pla_decode_|Equal61~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~16 .lut_mask = 16'hFC00; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~17 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~17_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~6_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~20_combout & (\z80_|execute_|ctl_alu_core_hf~18_combout & !\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ))) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~20_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~18_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~17 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~21 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~21_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~17_combout & (((!\z80_|execute_|ctl_mWrite~16_combout ) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|execute_|ctl_mWrite~16_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~21 .lut_mask = 16'h7F00; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~15 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~15_combout = (((\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ) # (\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout )) # (!\z80_|execute_|ctl_alu_sel_op2_neg~4_combout )) # (!\z80_|execute_|ctl_reg_out_hi~4_combout -// ) - - .dataa(\z80_|execute_|ctl_reg_out_hi~4_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~15 .lut_mask = 16'hFFF7; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~12 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~12_combout = (\z80_|execute_|ctl_flags_alu~17_combout & (\z80_|execute_|ctl_bus_inc_oe~43_combout & (\z80_|execute_|ctl_alu_core_S~4_combout & \z80_|execute_|ctl_alu_op1_sel_bus~8_combout ))) - - .dataa(\z80_|execute_|ctl_flags_alu~17_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~43_combout ), - .datac(\z80_|execute_|ctl_alu_core_S~4_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~12 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N6 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~22 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~22_combout = (\z80_|execute_|ctl_alu_shift_oe~38_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|execute_|ctl_ir_we~11_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~11_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~22 .lut_mask = 16'hC4CC; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~20 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~20_combout = ((\z80_|ir_|opcode [5]) # ((!\z80_|pla_decode_|Equal32~0_combout & !\z80_|pla_decode_|Equal9~0_combout ))) # (!\z80_|execute_|ctl_state_alu~12_combout ) - - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|pla_decode_|Equal9~0_combout ), - .datac(\z80_|execute_|ctl_state_alu~12_combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~20 .lut_mask = 16'hFF1F; -defparam \z80_|execute_|ctl_alu_core_hf~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~4_combout = (\z80_|execute_|ctl_flags_sz_we~0_combout & (((!\z80_|execute_|ctl_ir_we~12_combout & !\z80_|execute_|ctl_ir_we~11_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_flags_sz_we~0_combout ), - .datab(\z80_|execute_|ctl_ir_we~12_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_ir_we~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~4 .lut_mask = 16'h0A2A; -defparam \z80_|execute_|ctl_flags_sz_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N2 -cycloneive_lcell_comb \z80_|pla_decode_|Equal71~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal71~2_combout = (!\z80_|ir_|opcode [3] & (!\z80_|ir_|opcode [4] & (\z80_|execute_|ctl_state_alu~12_combout & \z80_|ir_|opcode [5]))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|execute_|ctl_state_alu~12_combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal71~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal71~2 .lut_mask = 16'h1000; -defparam \z80_|pla_decode_|Equal71~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N18 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~8 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~8_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~22_combout & (\z80_|execute_|ctl_alu_core_hf~20_combout & (\z80_|execute_|ctl_flags_sz_we~4_combout & !\z80_|pla_decode_|Equal71~2_combout ))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~22_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~20_combout ), - .datac(\z80_|execute_|ctl_flags_sz_we~4_combout ), - .datad(\z80_|pla_decode_|Equal71~2_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~8 .lut_mask = 16'h0080; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~31 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~31_combout = (!\z80_|execute_|ctl_alu_op_low~9_combout & (((!\z80_|sequencer_|DFFE_M4_ff~q ) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|pla_decode_|Equal13~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal13~2_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~9_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_M4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~31 .lut_mask = 16'h1333; -defparam \z80_|execute_|ctl_alu_op_low~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N22 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~4 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~4_combout = (\z80_|pla_decode_|Equal21~0_combout & ((\z80_|nM1_int~2_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout )))) # (!\z80_|pla_decode_|Equal21~0_combout & (\z80_|pla_decode_|Equal3~0_combout & -// ((\z80_|nM1_int~2_combout ) # (\z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal21~0_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal3~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~4 .lut_mask = 16'hFCA8; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout = (\z80_|pla_decode_|Equal13~1_combout & (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal6~0_combout & !\z80_|ir_|opcode [5]))) - - .dataa(\z80_|pla_decode_|Equal13~1_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|pla_decode_|Equal6~0_combout ), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N16 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~5 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~5_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout & \z80_|pla_decode_|Equal63~0_combout -// ))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), - .datac(\z80_|pla_decode_|Equal63~0_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~5 .lut_mask = 16'hFFEC; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y15_N26 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~6 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~6_combout = (\z80_|execute_|ctl_alu_op_low~31_combout & (\z80_|execute_|ctl_flags_pf_we~10_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~7_combout & !\z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~31_combout ), - .datab(\z80_|execute_|ctl_flags_pf_we~10_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~6 .lut_mask = 16'h0080; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal72~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal72~2_combout = (\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [3] & \z80_|execute_|ctl_state_alu~12_combout ))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|execute_|ctl_state_alu~12_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal72~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal72~2 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal72~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y9_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal73~2 ( -// Equation(s): -// \z80_|pla_decode_|Equal73~2_combout = (\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [3] & (!\z80_|ir_|opcode [4] & \z80_|execute_|ctl_state_alu~12_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|ir_|opcode [4]), - .datad(\z80_|execute_|ctl_state_alu~12_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal73~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal73~2 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal73~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~0 ( -// Equation(s): -// \z80_|execute_|ctl_flags_nf_we~0_combout = (\z80_|pla_decode_|Equal61~2_combout & (!\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|execute_|ctl_mRead~36_combout )))) # (!\z80_|pla_decode_|Equal61~2_combout & -// (((!\z80_|execute_|ixy_d~5_combout )) # (!\z80_|execute_|ctl_mRead~36_combout ))) - - .dataa(\z80_|pla_decode_|Equal61~2_combout ), - .datab(\z80_|execute_|ctl_mRead~36_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_nf_we~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_nf_we~0 .lut_mask = 16'h135F; -defparam \z80_|execute_|ctl_flags_nf_we~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~1 ( -// Equation(s): -// \z80_|execute_|ctl_flags_nf_we~1_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout & (!\z80_|pla_decode_|Equal72~2_combout & (!\z80_|pla_decode_|Equal73~2_combout & \z80_|execute_|ctl_flags_nf_we~0_combout ))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ), - .datab(\z80_|pla_decode_|Equal72~2_combout ), - .datac(\z80_|pla_decode_|Equal73~2_combout ), - .datad(\z80_|execute_|ctl_flags_nf_we~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_nf_we~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_nf_we~1 .lut_mask = 16'h0200; -defparam \z80_|execute_|ctl_flags_nf_we~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_nf_we~2_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal10~0_combout ) # ((\z80_|pla_decode_|Equal11~0_combout ) # (\z80_|pla_decode_|Equal61~2_combout )))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal61~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_nf_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_nf_we~2 .lut_mask = 16'hF0E0; -defparam \z80_|execute_|ctl_flags_nf_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_nf_we~3_combout = ((\z80_|execute_|ctl_flags_nf_we~2_combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~21_combout )) # (!\z80_|execute_|ctl_flags_nf_we~1_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_flags_nf_we~1_combout ), - .datac(\z80_|execute_|ctl_flags_nf_we~2_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~21_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_nf_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_nf_we~3 .lut_mask = 16'hF3FF; -defparam \z80_|execute_|ctl_flags_nf_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~5_combout = (\z80_|sequencer_|DFFE_T4_ff~q ) # ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~5 .lut_mask = 16'hFAFF; -defparam \z80_|execute_|ctl_flags_sz_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~6_combout = (\z80_|pla_decode_|Equal48~0_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # ((\z80_|execute_|ctl_flags_sz_we~5_combout & \z80_|execute_|ctl_alu_core_R~0_combout )))) # -// (!\z80_|pla_decode_|Equal48~0_combout & (\z80_|execute_|ctl_flags_sz_we~5_combout & ((\z80_|execute_|ctl_alu_core_R~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal48~0_combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~5_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datad(\z80_|execute_|ctl_alu_core_R~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~6 .lut_mask = 16'hECA0; -defparam \z80_|execute_|ctl_flags_sz_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_nf_we~4_combout = (((\z80_|execute_|ctl_flags_nf_we~3_combout ) # (\z80_|execute_|ctl_flags_sz_we~6_combout )) # (!\z80_|execute_|ctl_flags_xy_we~12_combout )) # (!\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~12_combout ), - .datac(\z80_|execute_|ctl_flags_nf_we~3_combout ), - .datad(\z80_|execute_|ctl_flags_sz_we~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_nf_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_nf_we~4 .lut_mask = 16'hFFF7; -defparam \z80_|execute_|ctl_flags_nf_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y9_N12 -cycloneive_lcell_comb \z80_|execute_|setM1~15 ( -// Equation(s): -// \z80_|execute_|setM1~15_combout = (!\z80_|execute_|ctl_alu_shift_oe~15_combout & (\z80_|execute_|ctl_sw_2u~1_combout & \z80_|execute_|ctl_state_alu~8_combout )) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_sw_2u~1_combout ), - .datad(\z80_|execute_|ctl_state_alu~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~15 .lut_mask = 16'h5000; -defparam \z80_|execute_|setM1~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|setM1~16 ( -// Equation(s): -// \z80_|execute_|setM1~16_combout = (\z80_|execute_|setM1~15_combout & (!\z80_|execute_|ctl_alu_op1_sel_zero~4_combout & (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & \z80_|execute_|ctl_alu_op_low~31_combout ))) - - .dataa(\z80_|execute_|setM1~15_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datad(\z80_|execute_|ctl_alu_op_low~31_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~16 .lut_mask = 16'h0200; -defparam \z80_|execute_|setM1~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~6_combout = (!\z80_|execute_|ctl_reg_gp_sel~36_combout & \z80_|execute_|setM1~16_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_sel~36_combout ), - .datad(\z80_|execute_|setM1~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~6 .lut_mask = 16'h0F00; -defparam \z80_|execute_|ctl_flags_xy_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~7_combout = (\z80_|execute_|ctl_flags_pf_we~2_combout & (\z80_|execute_|ctl_flags_xy_we~17_combout & (\z80_|execute_|ctl_flags_xy_we~6_combout & \z80_|execute_|ctl_alu_oe~5_combout ))) - - .dataa(\z80_|execute_|ctl_flags_pf_we~2_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~17_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~6_combout ), - .datad(\z80_|execute_|ctl_alu_oe~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~7 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_xy_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~2_combout = (\z80_|execute_|ctl_flags_sz_we~1_combout & (\z80_|execute_|ctl_flags_xy_we~7_combout & \z80_|execute_|ctl_alu_op2_sel_bus~10_combout )) - - .dataa(\z80_|execute_|ctl_flags_sz_we~1_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~7_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~2 .lut_mask = 16'h8800; -defparam \z80_|execute_|ctl_flags_sz_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla12M1T1_12~0 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout = (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal11~1_combout & (!\z80_|ir_|opcode [2] & \z80_|execute_|ctl_mWrite~2_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal11~1_combout ), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|execute_|ctl_mWrite~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel_pla12M1T1_12~0 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_pf_sel_pla12M1T1_12~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~1 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~1_combout = (\z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ) # ((\z80_|execute_|ctl_alu_core_R~0_combout & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|execute_|ctl_alu_core_R~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~1 .lut_mask = 16'hFBAA; -defparam \z80_|execute_|ctl_alu_core_R~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~7_combout = (\z80_|execute_|ctl_alu_core_R~1_combout ) # (((\z80_|execute_|ixy_d~7_combout & \z80_|pla_decode_|Equal56~0_combout )) # (!\z80_|execute_|ctl_flags_alu~18_combout )) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~1_combout ), - .datac(\z80_|pla_decode_|Equal56~0_combout ), - .datad(\z80_|execute_|ctl_flags_alu~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~7 .lut_mask = 16'hECFF; -defparam \z80_|execute_|ctl_flags_alu~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N24 -cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~8 ( -// Equation(s): -// \z80_|reg_control_|reg_sys_we_lo~8_combout = (\z80_|reg_control_|reg_sys_we_lo~5_combout & (((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|pla_decode_|Equal56~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal56~0_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|reg_control_|reg_sys_we_lo~5_combout ), - .cin(gnd), - .combout(\z80_|reg_control_|reg_sys_we_lo~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_control_|reg_sys_we_lo~8 .lut_mask = 16'h7F00; -defparam \z80_|reg_control_|reg_sys_we_lo~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~8_combout = ((\z80_|execute_|ctl_flags_alu~7_combout ) # ((!\z80_|reg_control_|reg_sys_we_lo~8_combout ) # (!\z80_|execute_|ctl_flags_alu~16_combout ))) # (!\z80_|execute_|ctl_flags_alu~6_combout ) - - .dataa(\z80_|execute_|ctl_flags_alu~6_combout ), - .datab(\z80_|execute_|ctl_flags_alu~7_combout ), - .datac(\z80_|execute_|ctl_flags_alu~16_combout ), - .datad(\z80_|reg_control_|reg_sys_we_lo~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~8 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_flags_alu~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~16 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~16_combout = (\z80_|execute_|ctl_alu_op_low~10_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|pla_decode_|Equal20~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal20~0_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|execute_|ctl_alu_op_low~10_combout ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~16 .lut_mask = 16'hD0F0; -defparam \z80_|execute_|ctl_flags_xy_we~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~12 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~12_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~5_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout & ((!\z80_|execute_|ctl_mRead~36_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|ctl_mRead~36_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~12 .lut_mask = 16'h0070; -defparam \z80_|execute_|ctl_flags_alu~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~13 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~13_combout = (\z80_|execute_|ctl_flags_sz_we~4_combout & (\z80_|execute_|ctl_flags_xy_we~16_combout & (\z80_|execute_|ctl_sw_2d~4_combout & \z80_|execute_|ctl_flags_alu~12_combout ))) - - .dataa(\z80_|execute_|ctl_flags_sz_we~4_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~16_combout ), - .datac(\z80_|execute_|ctl_sw_2d~4_combout ), - .datad(\z80_|execute_|ctl_flags_alu~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~13 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_alu~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~14 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~14_combout = (\z80_|execute_|ctl_reg_use_sp~1_combout & (\z80_|execute_|ctl_alu_op_low~15_combout & (\z80_|execute_|ctl_sw_4u~1_combout & \z80_|execute_|ctl_flags_alu~13_combout ))) - - .dataa(\z80_|execute_|ctl_reg_use_sp~1_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~15_combout ), - .datac(\z80_|execute_|ctl_sw_4u~1_combout ), - .datad(\z80_|execute_|ctl_flags_alu~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~14 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_flags_alu~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~15 ( -// Equation(s): -// \z80_|execute_|ctl_flags_alu~15_combout = ((\z80_|execute_|ctl_flags_alu~8_combout ) # ((!\z80_|execute_|ctl_flags_alu~11_combout ) # (!\z80_|execute_|ctl_flags_alu~14_combout ))) # (!\z80_|execute_|ctl_flags_sz_we~2_combout ) - - .dataa(\z80_|execute_|ctl_flags_sz_we~2_combout ), - .datab(\z80_|execute_|ctl_flags_alu~8_combout ), - .datac(\z80_|execute_|ctl_flags_alu~14_combout ), - .datad(\z80_|execute_|ctl_flags_alu~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_alu~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_alu~15 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_flags_alu~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [3] & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N12 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout = (\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ) # ((\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal10~0_combout ) # (\z80_|pla_decode_|Equal61~2_combout )))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|pla_decode_|Equal61~2_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 .lut_mask = 16'hFCEC; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~19 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~19_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal3~1_combout ))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|pla_decode_|Equal6~0_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal3~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~19 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N30 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ) # ((\z80_|execute_|ctl_alu_sel_op2_neg~19_combout ) # ((\z80_|alu_control_|db[1]~26_combout & \z80_|execute_|ctl_flags_bus~combout ))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~19_combout ), - .datac(\z80_|alu_control_|db[1]~26_combout ), - .datad(\z80_|execute_|ctl_flags_bus~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 .lut_mask = 16'hFEEE; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N20 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout = ((\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ) # ((\z80_|execute_|ctl_flags_alu~15_combout & \z80_|alu_|db_high[3]~8_combout ))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ) - - .dataa(\z80_|execute_|ctl_flags_alu~15_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), - .datac(\z80_|alu_|db_high[3]~8_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 .lut_mask = 16'hFFB3; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N20 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~7 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~7_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout & (((!\z80_|pla_decode_|Equal32~0_combout & !\z80_|pla_decode_|Equal21~0_combout )) # (!\z80_|pla_decode_|Equal62~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal32~0_combout ), - .datab(\z80_|pla_decode_|Equal62~2_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ), - .datad(\z80_|pla_decode_|Equal21~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~7 .lut_mask = 16'h3070; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N6 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~9 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~9_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~7_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~11_combout & (!\z80_|execute_|ctl_alu_core_R~1_combout & \z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~7_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~11_combout ), - .datac(\z80_|execute_|ctl_alu_core_R~1_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~9 .lut_mask = 16'h0800; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N26 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~10 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~10_combout = (\z80_|execute_|ctl_flags_nf_we~4_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout & ((\z80_|alu_flags_|DFFE_inst_latch_nf~9_combout )))) # (!\z80_|execute_|ctl_flags_nf_we~4_combout & -// (((\z80_|alu_flags_|DFFE_inst_latch_nf~q )))) - - .dataa(\z80_|execute_|ctl_flags_nf_we~4_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~9_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~10 .lut_mask = 16'hD850; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y9_N27 -dffeas \z80_|alu_flags_|DFFE_inst_latch_nf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|DFFE_inst_latch_nf~10_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~7 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~7_combout = ((\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # (\z80_|execute_|ctl_flags_cf2_sel_daa~combout )))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~7 .lut_mask = 16'hE0FF; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 ( -// Equation(s): -// \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [3] & \z80_|execute_|ixy_d~7_combout ))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~10 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~10_combout = (\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ) # ((\z80_|pla_decode_|Equal61~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # (\z80_|nM1_int~2_combout )))) - - .dataa(\z80_|pla_decode_|Equal61~2_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~10 .lut_mask = 16'hFFA8; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~8_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (!\z80_|sequencer_|DFFE_T3_ff~q & ((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|sequencer_|DFFE_M3_ff~q )))) # (!\z80_|sequencer_|DFFE_M2_ff~q & -// (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|sequencer_|DFFE_M3_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~8 .lut_mask = 16'h7707; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~9_combout = ((\z80_|pla_decode_|Equal10~0_combout & ((\z80_|nM1_int~2_combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~8_combout )))) # (!\z80_|execute_|ctl_alu_op_low~33_combout ) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~33_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~9 .lut_mask = 16'hB3BB; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~11 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~11_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ) # ((\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ) # ((\z80_|execute_|ctl_alu_op_low~8_combout & \z80_|execute_|ctl_alu_op_low~12_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~12_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~11 .lut_mask = 16'hFFEC; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~14 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~14_combout = (((\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ) # (\z80_|execute_|ctl_alu_sel_op2_neg~11_combout )) # (!\z80_|execute_|ctl_alu_sel_op2_neg~12_combout )) # (!\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~14 .lut_mask = 16'hFFF7; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~18 ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_neg~18_combout = ((\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ) # ((\z80_|execute_|ctl_alu_sel_op2_neg~15_combout & \z80_|alu_flags_|DFFE_inst_latch_sf~q ))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~21_combout ) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~21_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_neg~18 .lut_mask = 16'hFDF5; -defparam \z80_|execute_|ctl_alu_sel_op2_neg~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_high ( -// Equation(s): -// \z80_|execute_|ctl_alu_sel_op2_high~combout = ((\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|pla_decode_|Equal13~2_combout & \z80_|sequencer_|DFFE_M3_ff~q ))) # (!\z80_|execute_|ctl_alu_res_oe~2_combout ) - - .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), - .datab(\z80_|pla_decode_|Equal13~2_combout ), - .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_sel_op2_high .lut_mask = 16'h8F0F; -defparam \z80_|execute_|ctl_alu_sel_op2_high .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N6 -cycloneive_lcell_comb \z80_|alu_|alu_op2[1]~1 ( -// Equation(s): -// \z80_|alu_|alu_op2[1]~1_combout = \z80_|execute_|ctl_alu_sel_op2_neg~18_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_high [1])) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_low [1]))))) - - .dataa(\z80_|alu_|op2_high [1]), - .datab(\z80_|alu_|op2_low [1]), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_op2[1]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op2[1]~1 .lut_mask = 16'h5A3C; -defparam \z80_|alu_|alu_op2[1]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N30 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout = (!\z80_|alu_|alu_op2[1]~1_combout & ((\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_low [1])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_high -// [1]))))) - - .dataa(\z80_|alu_|alu_op2[1]~1_combout ), - .datab(\z80_|alu_|op1_low [1]), - .datac(\z80_|execute_|ctl_alu_op_low~combout ), - .datad(\z80_|alu_|op1_high [1]), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'h1015; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~9 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~9_combout = (((\z80_|pla_decode_|Equal71~2_combout ) # (!\z80_|execute_|ctl_alu_core_S~11_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~10_combout )) # (!\z80_|execute_|ctl_alu_core_S~5_combout ) - - .dataa(\z80_|execute_|ctl_alu_core_S~5_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), - .datac(\z80_|execute_|ctl_alu_core_S~11_combout ), - .datad(\z80_|pla_decode_|Equal71~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~9 .lut_mask = 16'hFF7F; -defparam \z80_|execute_|ctl_alu_core_S~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N22 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout = (\z80_|alu_|db_high[0]~26_combout & ((\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ) # ((\z80_|alu_|db_low[0]~23_combout & \z80_|execute_|ctl_alu_op2_sel_lq~combout )))) # -// (!\z80_|alu_|db_high[0]~26_combout & (\z80_|alu_|db_low[0]~23_combout & (\z80_|execute_|ctl_alu_op2_sel_lq~combout ))) - - .dataa(\z80_|alu_|db_high[0]~26_combout ), - .datab(\z80_|alu_|db_low[0]~23_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7 .lut_mask = 16'hEAC0; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N6 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8_combout = (\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout & !\z80_|execute_|ctl_alu_op2_sel_zero~combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8 .lut_mask = 16'h00F0; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y10_N7 -dffeas \z80_|alu_|op2_high[0] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_high [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_high[0] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_high[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N2 -cycloneive_lcell_comb \z80_|alu_|alu_op2[0]~3 ( -// Equation(s): -// \z80_|alu_|alu_op2[0]~3_combout = \z80_|execute_|ctl_alu_sel_op2_neg~18_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [0]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [0])))) - - .dataa(\z80_|alu_|op2_low [0]), - .datab(\z80_|alu_|op2_high [0]), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_op2[0]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op2[0]~3 .lut_mask = 16'h3C5A; -defparam \z80_|alu_|alu_op2[0]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N0 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~12 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_nf~12_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout & ((\z80_|ir_|opcode [3]) # ((!\z80_|ir_|opcode [4]) # (!\z80_|pla_decode_|Equal62~2_combout )))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal62~2_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~12 .lut_mask = 16'hB0F0; -defparam \z80_|alu_flags_|DFFE_inst_latch_nf~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~8 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_S~8_combout = (!\z80_|execute_|ctl_alu_core_R~1_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~6_combout & \z80_|execute_|ctl_alu_core_S~7_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_R~1_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~12_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_S~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_S~8 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_alu_core_S~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N2 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout = (((!\z80_|execute_|ctl_alu_core_S~9_combout & !\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout )) # (!\z80_|execute_|ctl_alu_core_S~8_combout )) # -// (!\z80_|execute_|ctl_alu_core_R~4_combout ) - - .dataa(\z80_|execute_|ctl_alu_core_S~9_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~4_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 .lut_mask = 16'h37FF; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~21 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~21_combout = (\z80_|execute_|ctl_alu_core_hf~20_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # ((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|execute_|ixy_d~15_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|execute_|ixy_d~15_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~20_combout ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~21 .lut_mask = 16'hB0F0; -defparam \z80_|execute_|ctl_alu_core_hf~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~22 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~22_combout = (((\z80_|execute_|ixy_d~8_combout & \z80_|pla_decode_|Equal21~1_combout )) # (!\z80_|execute_|ctl_alu_core_hf~21_combout )) # (!\z80_|execute_|ctl_alu_core_hf~18_combout ) - - .dataa(\z80_|execute_|ctl_alu_core_hf~18_combout ), - .datab(\z80_|execute_|ixy_d~8_combout ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~21_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~22 .lut_mask = 16'hD5FF; -defparam \z80_|execute_|ctl_alu_core_hf~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~19 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~19_combout = (\z80_|pla_decode_|Equal21~1_combout & ((\z80_|execute_|ctl_mRead~11_combout ) # ((\z80_|execute_|ixy_d~6_combout & !\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~11_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~19 .lut_mask = 16'hA0E0; -defparam \z80_|execute_|ctl_alu_core_hf~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~27 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~27_combout = (\z80_|execute_|ctl_alu_op_low~19_combout ) # (((\z80_|execute_|ctl_alu_op_low~22_combout ) # (!\z80_|execute_|ctl_alu_op_low~33_combout )) # (!\z80_|execute_|ctl_alu_op_low~17_combout )) - - .dataa(\z80_|execute_|ctl_alu_op_low~19_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~17_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~22_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~33_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~27 .lut_mask = 16'hFBFF; -defparam \z80_|execute_|ctl_alu_op_low~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~29 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~29_combout = (\z80_|execute_|ctl_alu_op_low~23_combout ) # ((\z80_|execute_|ctl_alu_op_low~34_combout ) # (\z80_|execute_|ctl_alu_op_low~27_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op_low~23_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~34_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~29 .lut_mask = 16'hFFFC; -defparam \z80_|execute_|ctl_alu_op_low~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~23 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~23_combout = (\z80_|execute_|ctl_alu_core_hf~22_combout & (((\z80_|execute_|ctl_alu_core_hf~19_combout & !\z80_|execute_|ctl_alu_op_low~29_combout )) # (!\z80_|execute_|ctl_alu_op_low~28_combout ))) # -// (!\z80_|execute_|ctl_alu_core_hf~22_combout & (\z80_|execute_|ctl_alu_core_hf~19_combout & (!\z80_|execute_|ctl_alu_op_low~29_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~22_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~19_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~29_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~28_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~23 .lut_mask = 16'h0CAE; -defparam \z80_|execute_|ctl_alu_core_hf~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~37 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~37_combout = (\z80_|pla_decode_|Equal39~0_combout ) # ((!\z80_|execute_|ixy_d~5_combout & \z80_|pla_decode_|Equal40~1_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|pla_decode_|Equal40~1_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~37 .lut_mask = 16'hFF30; -defparam \z80_|execute_|ctl_alu_core_hf~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~38 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~38_combout = (\z80_|execute_|ctl_alu_core_hf~37_combout & ((\z80_|execute_|ixy_d~6_combout ) # ((\z80_|execute_|ixy_d~8_combout & !\z80_|execute_|ixy_d~9_combout )))) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|execute_|ixy_d~8_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~37_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~38 .lut_mask = 16'hAE00; -defparam \z80_|execute_|ctl_alu_core_hf~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~24 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~24_combout = (\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (((!\z80_|pla_decode_|Equal32~0_combout ) # (!\z80_|pla_decode_|Equal63~0_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|pla_decode_|Equal63~0_combout ), - .datac(\z80_|pla_decode_|Equal32~0_combout ), - .datad(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~24 .lut_mask = 16'h7F00; -defparam \z80_|execute_|ctl_alu_core_hf~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~25 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~25_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # ((\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ) # ((!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & \z80_|execute_|ctl_alu_core_hf~24_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .datab(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~25 .lut_mask = 16'hEFEE; -defparam \z80_|execute_|ctl_alu_core_hf~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~26 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~26_combout = (\z80_|execute_|ctl_mRead~36_combout & ((\z80_|execute_|ctl_mRead~11_combout ) # ((\z80_|execute_|ixy_d~6_combout & !\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~36_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|execute_|ctl_mRead~11_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~26 .lut_mask = 16'hA0A8; -defparam \z80_|execute_|ctl_alu_core_hf~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~27 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~27_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ) # ((\z80_|execute_|ctl_alu_core_hf~26_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|execute_|ctl_mRead~36_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~36_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~26_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~27 .lut_mask = 16'hDFCC; -defparam \z80_|execute_|ctl_alu_core_hf~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~28 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~28_combout = (\z80_|execute_|ctl_alu_core_hf~25_combout & (((\z80_|execute_|ctl_alu_core_hf~27_combout & !\z80_|execute_|ctl_alu_op_low~27_combout )) # (!\z80_|execute_|ctl_alu_op_low~20_combout ))) # -// (!\z80_|execute_|ctl_alu_core_hf~25_combout & (((\z80_|execute_|ctl_alu_core_hf~27_combout & !\z80_|execute_|ctl_alu_op_low~27_combout )))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~25_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~20_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~27_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~28 .lut_mask = 16'h22F2; -defparam \z80_|execute_|ctl_alu_core_hf~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~30 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~30_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ) # (((\z80_|execute_|ctl_alu_op_low~14_combout ) # (!\z80_|execute_|ctl_alu_op2_sel_bus~9_combout )) # (!\z80_|execute_|ctl_state_alu~13_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), - .datab(\z80_|execute_|ctl_state_alu~13_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~30 .lut_mask = 16'hFBFF; -defparam \z80_|execute_|ctl_alu_op_low~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~34 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~34_combout = (\z80_|execute_|ctl_mRead~6_combout & ((\z80_|execute_|ctl_mWrite~3_combout ) # ((\z80_|execute_|ctl_mWrite~7_combout & !\z80_|execute_|ctl_state_alu~6_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~3_combout ), - .datab(\z80_|execute_|ctl_mWrite~7_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_mRead~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~34 .lut_mask = 16'hAE00; -defparam \z80_|execute_|ctl_alu_core_hf~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~32 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~32_combout = (\z80_|execute_|ctl_alu_op_low~8_combout & (((\z80_|execute_|ctl_alu_op_low~11_combout )))) # (!\z80_|execute_|ctl_alu_op_low~8_combout & (\z80_|execute_|ixy_d~7_combout & -// ((!\z80_|execute_|ctl_mWrite~3_combout )))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~11_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datad(\z80_|execute_|ctl_mWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~32 .lut_mask = 16'hC0CA; -defparam \z80_|execute_|ctl_alu_core_hf~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~43 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~43_combout = (\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|execute_|ctl_mRead~6_combout & (\z80_|execute_|ctl_state_alu~6_combout ))) # (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M2_ff~q ) # -// ((\z80_|execute_|ctl_mRead~6_combout & \z80_|execute_|ctl_state_alu~6_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~43 .lut_mask = 16'hD5C0; -defparam \z80_|execute_|ctl_alu_core_hf~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~33 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~33_combout = (!\z80_|execute_|ctl_alu_core_hf~43_combout & ((\z80_|execute_|ctl_alu_core_hf~32_combout & ((\z80_|pla_decode_|Equal56~0_combout ) # (\z80_|execute_|ctl_alu_op_low~8_combout ))) # -// (!\z80_|execute_|ctl_alu_core_hf~32_combout & (\z80_|pla_decode_|Equal56~0_combout & \z80_|execute_|ctl_alu_op_low~8_combout )))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~32_combout ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~43_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~33 .lut_mask = 16'h00E8; -defparam \z80_|execute_|ctl_alu_core_hf~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~42 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~42_combout = (!\z80_|execute_|ctl_alu_shift_oe~15_combout & (((!\z80_|sequencer_|DFFE_M2_ff~q ) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|execute_|ctl_mRead~6_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~15_combout ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~42 .lut_mask = 16'h1555; -defparam \z80_|execute_|ctl_alu_core_hf~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~35 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~35_combout = (\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # ((\z80_|execute_|ctl_alu_core_hf~42_combout & ((\z80_|execute_|ctl_alu_core_hf~34_combout ) # (\z80_|execute_|ctl_alu_core_hf~33_combout )))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~34_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~33_combout ), - .datac(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~42_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~35 .lut_mask = 16'hFEF0; -defparam \z80_|execute_|ctl_alu_core_hf~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~41 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~41_combout = (!\z80_|execute_|ctl_state_alu~4_combout & (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|pla_decode_|Equal10~0_combout & !\z80_|sequencer_|DFFE_T1_ff~q ))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~41 .lut_mask = 16'h0040; -defparam \z80_|execute_|ctl_alu_core_hf~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~30 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~30_combout = (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|nM1_int~2_combout ) # ((\z80_|pla_decode_|Equal11~0_combout & !\z80_|execute_|ctl_alu_sel_op2_neg~8_combout )))) # (!\z80_|pla_decode_|Equal10~0_combout & -// (\z80_|pla_decode_|Equal11~0_combout & ((!\z80_|execute_|ctl_alu_sel_op2_neg~8_combout )))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~30 .lut_mask = 16'hA0EC; -defparam \z80_|execute_|ctl_alu_core_hf~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~10 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~10_combout = (!\z80_|ir_|opcode [2] & (\z80_|execute_|ctl_state_alu~4_combout & (\z80_|pla_decode_|Equal11~1_combout & \z80_|execute_|ctl_mWrite~2_combout ))) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|pla_decode_|Equal11~1_combout ), - .datad(\z80_|execute_|ctl_mWrite~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~10 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_mWrite~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~31 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~31_combout = (!\z80_|execute_|ctl_alu_op_low~14_combout & (!\z80_|execute_|ctl_mWrite~10_combout & ((\z80_|execute_|ctl_alu_core_hf~41_combout ) # (\z80_|execute_|ctl_alu_core_hf~30_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~14_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~41_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~30_combout ), - .datad(\z80_|execute_|ctl_mWrite~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~31 .lut_mask = 16'h0054; -defparam \z80_|execute_|ctl_alu_core_hf~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~44 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~44_combout = (\z80_|execute_|ctl_alu_op_low~12_combout & (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~44 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_alu_core_hf~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~29 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~29_combout = (!\z80_|execute_|ctl_alu_op_low~19_combout & ((\z80_|execute_|ctl_alu_core_hf~44_combout ) # ((\z80_|execute_|ctl_alu_op_low~11_combout & \z80_|execute_|ixy_d~7_combout )))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~44_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~11_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~19_combout ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~29 .lut_mask = 16'h0E0A; -defparam \z80_|execute_|ctl_alu_core_hf~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~36 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~36_combout = (\z80_|execute_|ctl_alu_core_hf~31_combout ) # ((\z80_|execute_|ctl_alu_core_hf~29_combout ) # ((!\z80_|execute_|ctl_alu_op_low~30_combout & \z80_|execute_|ctl_alu_core_hf~35_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~30_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~35_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~31_combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~29_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~36_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~36 .lut_mask = 16'hFFF4; -defparam \z80_|execute_|ctl_alu_core_hf~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~39 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~39_combout = (\z80_|execute_|ctl_alu_core_hf~28_combout ) # ((\z80_|execute_|ctl_alu_core_hf~36_combout ) # ((\z80_|execute_|ctl_alu_core_hf~38_combout & !\z80_|execute_|ctl_alu_op_low~24_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~38_combout ), - .datab(\z80_|execute_|ctl_alu_core_hf~28_combout ), - .datac(\z80_|execute_|ctl_alu_core_hf~36_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~24_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~39 .lut_mask = 16'hFCFE; -defparam \z80_|execute_|ctl_alu_core_hf~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~40 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_hf~40_combout = (\z80_|execute_|ctl_alu_core_hf~23_combout ) # ((\z80_|execute_|ctl_alu_core_hf~39_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout & !\z80_|execute_|ctl_alu_op_low~combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_hf~23_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), - .datac(\z80_|execute_|ctl_alu_op_low~combout ), - .datad(\z80_|execute_|ctl_alu_core_hf~39_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_hf~40_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_hf~40 .lut_mask = 16'hFFAE; -defparam \z80_|execute_|ctl_alu_core_hf~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_we~2_combout = (\z80_|execute_|ctl_flags_xy_we~11_combout & (\z80_|execute_|ctl_flags_hf_we~5_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_state_alu~14_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~14_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~11_combout ), - .datad(\z80_|execute_|ctl_flags_hf_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_we~2 .lut_mask = 16'h7000; -defparam \z80_|execute_|ctl_flags_hf_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~2 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~2_combout = (\z80_|nM1_int~2_combout & (\z80_|execute_|ctl_mWrite~2_combout & ((\z80_|pla_decode_|Equal55~0_combout ) # (\z80_|pla_decode_|Equal8~0_combout )))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~2_combout ), - .datad(\z80_|pla_decode_|Equal8~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~2 .lut_mask = 16'hA080; -defparam \z80_|execute_|ctl_alu_core_R~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~combout = (\z80_|execute_|ctl_alu_core_R~2_combout ) # (((\z80_|pla_decode_|Equal73~2_combout ) # (!\z80_|execute_|ctl_alu_core_S~8_combout )) # (!\z80_|execute_|ctl_alu_core_R~4_combout )) - - .dataa(\z80_|execute_|ctl_alu_core_R~2_combout ), - .datab(\z80_|execute_|ctl_alu_core_R~4_combout ), - .datac(\z80_|pla_decode_|Equal73~2_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R .lut_mask = 16'hFBFF; -defparam \z80_|execute_|ctl_alu_core_R .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N2 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|alu_|db_low[3]~11_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~43_combout & !\z80_|alu_|db_high[3]~2_combout )))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datab(\z80_|alu_|db_low[3]~11_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datad(\z80_|alu_|db_high[3]~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9 .lut_mask = 16'hC0D0; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N8 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~8_combout & \z80_|alu_|db_high[3]~8_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datab(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .datac(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9_combout ), - .datad(\z80_|alu_|db_high[3]~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2 .lut_mask = 16'h5450; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y10_N9 -dffeas \z80_|alu_|op2_high[3] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_high [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_high[3] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_high[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N2 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [3]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [3])))) - - .dataa(\z80_|alu_|op1_high [3]), - .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datac(\z80_|execute_|ctl_alu_op_low~combout ), - .datad(\z80_|alu_|op1_low [3]), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2 .lut_mask = 16'hC808; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N18 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2_combout ) # ((\z80_|alu_|db_low[3]~25_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datab(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2_combout ), - .datac(\z80_|alu_|db_low[3]~25_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3 .lut_mask = 16'h5444; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y10_N19 -dffeas \z80_|alu_|op2_low[3] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_low [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_low[3] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_low[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N26 -cycloneive_lcell_comb \z80_|alu_|alu_op2[3]~2 ( -// Equation(s): -// \z80_|alu_|alu_op2[3]~2_combout = \z80_|execute_|ctl_alu_sel_op2_neg~18_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_high [3])) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_low [3]))))) - - .dataa(\z80_|alu_|op2_high [3]), - .datab(\z80_|alu_|op2_low [3]), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), - .datad(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_op2[3]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op2[3]~2 .lut_mask = 16'h5A3C; -defparam \z80_|alu_|alu_op2[3]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N4 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout = (\z80_|execute_|ctl_alu_core_S~9_combout ) # (((\z80_|alu_|alu_op1[3]~3_combout & \z80_|alu_|alu_op2[3]~2_combout )) # (!\z80_|execute_|ctl_alu_core_S~8_combout )) - - .dataa(\z80_|alu_|alu_op1[3]~3_combout ), - .datab(\z80_|execute_|ctl_alu_core_S~9_combout ), - .datac(\z80_|alu_|alu_op2[3]~2_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hECFF; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N16 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout = (!\z80_|alu_|alu_op2[3]~2_combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_low [3]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_high -// [3])))) - - .dataa(\z80_|alu_|alu_op2[3]~2_combout ), - .datab(\z80_|alu_|op1_high [3]), - .datac(\z80_|alu_|op1_low [3]), - .datad(\z80_|execute_|ctl_alu_op_low~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h0511; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N30 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ) # -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_core_R~combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0 .lut_mask = 16'hAFAE; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N2 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_hf~0 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_hf~0_combout = (\z80_|execute_|ctl_flags_bus~combout & ((\z80_|alu_control_|db[4]~32_combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & \z80_|execute_|ctl_flags_alu~15_combout )))) # -// (!\z80_|execute_|ctl_flags_bus~combout & (((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & \z80_|execute_|ctl_flags_alu~15_combout )))) - - .dataa(\z80_|execute_|ctl_flags_bus~combout ), - .datab(\z80_|alu_control_|db[4]~32_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), - .datad(\z80_|execute_|ctl_flags_alu~15_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_hf~0 .lut_mask = 16'h8F88; -defparam \z80_|alu_flags_|DFFE_inst_latch_hf~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_we~3_combout = (\z80_|pla_decode_|Equal11~0_combout & ((\z80_|nM1_int~2_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) # (!\z80_|pla_decode_|Equal11~0_combout & (((\z80_|pla_decode_|Equal10~0_combout & -// \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_we~3 .lut_mask = 16'hFC88; -defparam \z80_|execute_|ctl_flags_hf_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_we~4_combout = ((\z80_|execute_|ctl_flags_sz_we~6_combout ) # ((\z80_|execute_|ctl_flags_hf_we~3_combout ) # (!\z80_|execute_|ctl_flags_xy_we~6_combout ))) # (!\z80_|execute_|ctl_flags_alu~14_combout ) - - .dataa(\z80_|execute_|ctl_flags_alu~14_combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~6_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~6_combout ), - .datad(\z80_|execute_|ctl_flags_hf_we~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_we~4 .lut_mask = 16'hFFDF; -defparam \z80_|execute_|ctl_flags_hf_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N6 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_hf~1 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_hf~1_combout = (\z80_|execute_|ctl_flags_hf_we~2_combout & ((\z80_|execute_|ctl_flags_hf_we~4_combout & (\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout )) # (!\z80_|execute_|ctl_flags_hf_we~4_combout & -// ((\z80_|alu_flags_|DFFE_inst_latch_hf~q ))))) # (!\z80_|execute_|ctl_flags_hf_we~2_combout & (\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout )) - - .dataa(\z80_|execute_|ctl_flags_hf_we~2_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), - .datad(\z80_|execute_|ctl_flags_hf_we~4_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_hf~1 .lut_mask = 16'hCCE4; -defparam \z80_|alu_flags_|DFFE_inst_latch_hf~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y11_N7 -dffeas \z80_|alu_flags_|DFFE_inst_latch_hf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_hf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_hf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_cpl~11_combout = (\z80_|execute_|ctl_mRead~6_combout ) # ((\z80_|pla_decode_|Equal52~1_combout ) # (\z80_|execute_|ctl_state_alu~14_combout )) - - .dataa(\z80_|execute_|ctl_mRead~6_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal52~1_combout ), - .datad(\z80_|execute_|ctl_state_alu~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_cpl~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_cpl~11 .lut_mask = 16'hFFFA; -defparam \z80_|execute_|ctl_flags_hf_cpl~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~12 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_cpl~12_combout = ((\z80_|execute_|ctl_flags_hf_cpl~11_combout ) # ((\z80_|pla_decode_|Equal10~0_combout ) # (\z80_|execute_|ctl_alu_op_low~12_combout ))) # (!\z80_|execute_|ctl_flags_hf_cpl~10_combout ) - - .dataa(\z80_|execute_|ctl_flags_hf_cpl~10_combout ), - .datab(\z80_|execute_|ctl_flags_hf_cpl~11_combout ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_cpl~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_cpl~12 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_flags_hf_cpl~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~13 ( -// Equation(s): -// \z80_|execute_|ctl_flags_hf_cpl~13_combout = (\z80_|execute_|ctl_flags_hf_cpl~12_combout & (\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|alu_flags_|DFFE_inst_latch_nf~q ))) - - .dataa(\z80_|execute_|ctl_flags_hf_cpl~12_combout ), - .datab(\z80_|sequencer_|DFFE_T2_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_hf_cpl~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_hf_cpl~13 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_flags_hf_cpl~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N8 -cycloneive_lcell_comb \z80_|alu_flags_|flags_hf ( -// Equation(s): -// \z80_|alu_flags_|flags_hf~combout = \z80_|alu_flags_|DFFE_inst_latch_hf~q $ (((\z80_|execute_|ctl_flags_hf_cpl~13_combout ) # ((!\z80_|alu_flags_|flags_cf~combout & \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout )))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), - .datab(\z80_|alu_flags_|flags_cf~combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .datad(\z80_|execute_|ctl_flags_hf_cpl~13_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|flags_hf~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_hf .lut_mask = 16'h559A; -defparam \z80_|alu_flags_|flags_hf .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N30 -cycloneive_lcell_comb \z80_|alu_control_|alu_core_cf_in~0 ( -// Equation(s): -// \z80_|alu_control_|alu_core_cf_in~0_combout = (\z80_|execute_|ctl_alu_core_hf~40_combout & ((\z80_|alu_flags_|flags_hf~combout ))) # (!\z80_|execute_|ctl_alu_core_hf~40_combout & (\z80_|alu_flags_|flags_cf~combout )) - - .dataa(\z80_|execute_|ctl_alu_core_hf~40_combout ), - .datab(\z80_|alu_flags_|flags_cf~combout ), - .datac(gnd), - .datad(\z80_|alu_flags_|flags_hf~combout ), - .cin(gnd), - .combout(\z80_|alu_control_|alu_core_cf_in~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|alu_core_cf_in~0 .lut_mask = 16'hEE44; -defparam \z80_|alu_control_|alu_core_cf_in~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N20 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout = (\z80_|alu_|alu_op2[0]~3_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ) # ((\z80_|alu_control_|alu_core_cf_in~0_combout & \z80_|alu_|alu_op1[0]~1_combout )))) -// # (!\z80_|alu_|alu_op2[0]~3_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_control_|alu_core_cf_in~0_combout ) # (\z80_|alu_|alu_op1[0]~1_combout )))) - - .dataa(\z80_|alu_|alu_op2[0]~3_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ), - .datac(\z80_|alu_control_|alu_core_cf_in~0_combout ), - .datad(\z80_|alu_|alu_op1[0]~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 .lut_mask = 16'hECC8; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N12 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~23 ( -// Equation(s): -// \z80_|alu_|db_high[0]~23_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[5]~25_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[3]~11_combout )) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|alu_|db[3]~11_combout ), - .datac(\z80_|alu_|db[5]~25_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~23 .lut_mask = 16'hE4E4; -defparam \z80_|alu_|db_high[0]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N8 -cycloneive_lcell_comb \z80_|address_latch_|abusz[12] ( -// Equation(s): -// \z80_|address_latch_|abusz [12] = (\z80_|reg_file_|db_hi_as[4]~18_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(gnd), - .datab(\z80_|reg_file_|db_hi_as[4]~18_combout ), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [12]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[12] .lut_mask = 16'h0C0C; -defparam \z80_|address_latch_|abusz[12] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N14 -cycloneive_lcell_comb \z80_|address_latch_|Q[12]~feeder ( -// Equation(s): -// \z80_|address_latch_|Q[12]~feeder_combout = \z80_|address_latch_|abusz [12] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [12]), - .cin(gnd), - .combout(\z80_|address_latch_|Q[12]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|Q[12]~feeder .lut_mask = 16'hFF00; -defparam \z80_|address_latch_|Q[12]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N15 -dffeas \z80_|address_latch_|Q[12] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|Q[12]~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [12]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[12] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[12] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N30 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout = \z80_|address_latch_|Q [12] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout & (\z80_|execute_|ctl_inc_dec~11_combout $ -// (\z80_|address_latch_|Q [11]))))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), - .datab(\z80_|execute_|ctl_inc_dec~11_combout ), - .datac(\z80_|address_latch_|Q [12]), - .datad(\z80_|address_latch_|Q [11]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out .lut_mask = 16'hD278; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N5 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[4]~18_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y15_N7 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[4]~18_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N6 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~16 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[4]~16_combout = (\z80_|reg_control_|reg_sw_4d_hi~0_combout & (\z80_|reg_file_|gdfx_temp1[4]~66_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) - - .dataa(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [4]), - .datad(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[4]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[4]~16 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|db_hi_as[4]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N18 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~17 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[4]~17_combout = (\z80_|reg_file_|db_hi_as[4]~16_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datab(gnd), - .datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [4]), - .datad(\z80_|reg_file_|db_hi_as[4]~16_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[4]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[4]~17 .lut_mask = 16'hF500; -defparam \z80_|reg_file_|db_hi_as[4]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N4 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~18 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[4]~18_combout = ((\z80_|reg_file_|db_hi_as[4]~17_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datad(\z80_|reg_file_|db_hi_as[4]~17_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[4]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[4]~18 .lut_mask = 16'hBF0F; -defparam \z80_|reg_file_|db_hi_as[4]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y11_N11 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~62 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~62_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (\z80_|reg_file_|b2v_latch_af2_hi|latch [4] & ((\z80_|alu_|db[4]~17_combout ) # (!\z80_|execute_|ctl_reg_in_hi~12_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout & (((\z80_|alu_|db[4]~17_combout )) # (!\z80_|execute_|ctl_reg_in_hi~12_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [4]), - .datad(\z80_|alu_|db[4]~17_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~62_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~62 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[4]~62 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y15_N13 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y11_N29 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~63 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~63_combout = (\z80_|reg_file_|b2v_latch_sp_hi|latch [4] & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ))) # (!\z80_|reg_file_|b2v_latch_sp_hi|latch [4] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_sp_hi|latch [4]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~63_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~63 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[4]~63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y12_N23 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y12_N21 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~61 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~61_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (\z80_|reg_file_|b2v_latch_ix_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_iy_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (((\z80_|reg_file_|b2v_latch_iy_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_iy_hi|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~61_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~61 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[4]~61 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N24 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder_combout = \z80_|reg_file_|gdfx_temp1[4]~66_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y13_N25 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y13_N23 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~60 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~60_combout = (\z80_|reg_file_|b2v_latch_bc_hi|latch [4] & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_hi|latch [4] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc_hi|latch [4]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~60_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~60 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[4]~60 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~64 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~64_combout = (\z80_|reg_file_|gdfx_temp1[4]~62_combout & (\z80_|reg_file_|gdfx_temp1[4]~63_combout & (\z80_|reg_file_|gdfx_temp1[4]~61_combout & \z80_|reg_file_|gdfx_temp1[4]~60_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[4]~62_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[4]~63_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[4]~61_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[4]~60_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~64_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~64 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[4]~64 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N31 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y14_N29 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~59 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~59_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~59_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~59 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[4]~59 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y13_N23 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y13_N13 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~58 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~58_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~58_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~58 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[4]~58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y14_N19 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N18 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[4]~19 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[4]~19_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [4]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [4]), - .datad(\z80_|reg_control_|reg_sel_af~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[4]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[4]~19 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[4]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~65 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~65_combout = (\z80_|reg_file_|gdfx_temp1[4]~64_combout & (\z80_|reg_file_|gdfx_temp1[4]~59_combout & (\z80_|reg_file_|gdfx_temp1[4]~58_combout & \z80_|reg_file_|b2v_latch_af_hi|db[4]~19_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[4]~64_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[4]~59_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[4]~58_combout ), - .datad(\z80_|reg_file_|b2v_latch_af_hi|db[4]~19_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~65_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~65 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[4]~65 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~66 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[4]~66_combout = ((\z80_|reg_file_|gdfx_temp1[4]~65_combout & ((\z80_|reg_file_|db_hi_as[4]~18_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datab(\z80_|reg_file_|db_hi_as[4]~18_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[4]~65_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[4]~66 .lut_mask = 16'hD5F5; -defparam \z80_|reg_file_|gdfx_temp1[4]~66 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N26 -cycloneive_lcell_comb \z80_|alu_|db[4]~16 ( -// Equation(s): -// \z80_|alu_|db[4]~16_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[4]~66_combout & ((\z80_|alu_control_|db[4]~32_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & -// (((\z80_|alu_control_|db[4]~32_combout )) # (!\z80_|execute_|ctl_sw_2d~13_combout ))) - - .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datab(\z80_|execute_|ctl_sw_2d~13_combout ), - .datac(\z80_|alu_control_|db[4]~32_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[4]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[4]~16 .lut_mask = 16'hF351; -defparam \z80_|alu_|db[4]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N2 -cycloneive_lcell_comb \z80_|alu_|db[7]~26 ( -// Equation(s): -// \z80_|alu_|db[7]~26_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout ) # ((\z80_|execute_|ctl_alu_oe~13_combout ) # ((\z80_|execute_|ctl_sw_2d~13_combout ) # (!\z80_|execute_|ctl_alu_oe~9_combout ))) - - .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datab(\z80_|execute_|ctl_alu_oe~13_combout ), - .datac(\z80_|execute_|ctl_alu_oe~9_combout ), - .datad(\z80_|execute_|ctl_sw_2d~13_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[7]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[7]~26 .lut_mask = 16'hFFEF; -defparam \z80_|alu_|db[7]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N0 -cycloneive_lcell_comb \z80_|alu_|db[4]~17 ( -// Equation(s): -// \z80_|alu_|db[4]~17_combout = ((\z80_|alu_|db[4]~16_combout & ((\z80_|alu_|db_high[0]~26_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~26_combout ) - - .dataa(\z80_|alu_|db[4]~16_combout ), - .datab(\z80_|alu_|db[7]~26_combout ), - .datac(\z80_|alu_|db_high[0]~26_combout ), - .datad(\z80_|execute_|ctl_alu_oe~14_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[4]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[4]~17 .lut_mask = 16'hB3BB; -defparam \z80_|alu_|db[4]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_sel_shift~3_combout = (\z80_|execute_|ctl_state_alu~6_combout ) # ((\z80_|pla_decode_|Equal33~0_combout & (\z80_|execute_|ctl_mWrite~3_combout & \z80_|decode_state_|DFFE_instCB~q ))) - - .dataa(\z80_|execute_|ctl_state_alu~6_combout ), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|execute_|ctl_mWrite~3_combout ), - .datad(\z80_|decode_state_|DFFE_instCB~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~3 .lut_mask = 16'hEAAA; -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_sel_shift~5_combout = (\z80_|sequencer_|DFFE_T4_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|execute_|ctl_ir_we~8_combout ) # (\z80_|pla_decode_|Equal20~0_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|pla_decode_|Equal20~0_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~5 .lut_mask = 16'h00C8; -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_sel_shift~4_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ) # ((\z80_|execute_|ctl_ir_we~6_combout & (\z80_|execute_|ctl_flags_cf2_sel_shift~3_combout & \z80_|execute_|ctl_ir_we~5_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~6_combout ), - .datab(\z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ), - .datac(\z80_|execute_|ctl_ir_we~5_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~4 .lut_mask = 16'hFF80; -defparam \z80_|execute_|ctl_flags_cf2_sel_shift~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N10 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~24 ( -// Equation(s): -// \z80_|alu_|db_high[0]~24_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_high[0]~23_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[4]~17_combout ))) - - .dataa(\z80_|alu_|db_high[0]~23_combout ), - .datab(gnd), - .datac(\z80_|alu_|db[4]~17_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~24 .lut_mask = 16'hAAF0; -defparam \z80_|alu_|db_high[0]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N4 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~21 ( -// Equation(s): -// \z80_|alu_|db_high[0]~21_combout = ((!\z80_|bus_control_|db[4]~19_combout & (\z80_|bus_control_|db[5]~15_combout & !\z80_|bus_control_|db[3]~21_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datab(\z80_|bus_control_|db[4]~19_combout ), - .datac(\z80_|bus_control_|db[5]~15_combout ), - .datad(\z80_|bus_control_|db[3]~21_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~21 .lut_mask = 16'h5575; -defparam \z80_|alu_|db_high[0]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N20 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[0] ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_high|Q [0] = (\z80_|alu_|db_high[0]~26_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout )) - - .dataa(gnd), - .datab(\z80_|alu_|db_high[0]~26_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [0]), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[0] .lut_mask = 16'h00C0; -defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[0] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y10_N21 -dffeas \z80_|alu_|op1_high[0] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [0]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_high [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_high[0] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_high[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N8 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~22 ( -// Equation(s): -// \z80_|alu_|db_high[0]~22_combout = (\z80_|alu_|op1_high [0] & (((\z80_|alu_|op2_high [0]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|alu_|op1_high [0] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_high [0]) # -// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) - - .dataa(\z80_|alu_|op1_high [0]), - .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datac(\z80_|alu_|op2_high [0]), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~22 .lut_mask = 16'hB0BB; -defparam \z80_|alu_|db_high[0]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N4 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~25 ( -// Equation(s): -// \z80_|alu_|db_high[0]~25_combout = (\z80_|alu_|db_high[0]~21_combout & (\z80_|alu_|db_high[0]~22_combout & ((\z80_|alu_|db_high[0]~24_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) - - .dataa(\z80_|alu_|db_high[0]~24_combout ), - .datab(\z80_|alu_|db_high[0]~21_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datad(\z80_|alu_|db_high[0]~22_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~25 .lut_mask = 16'h8C00; -defparam \z80_|alu_|db_high[0]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N22 -cycloneive_lcell_comb \z80_|alu_|db_high[0]~26 ( -// Equation(s): -// \z80_|alu_|db_high[0]~26_combout = ((\z80_|alu_|db_high[0]~25_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) # (!\z80_|alu_|db_high[3]~3_combout ) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), - .datab(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datac(\z80_|alu_|db_high[0]~25_combout ), - .datad(\z80_|alu_|db_high[3]~3_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[0]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[0]~26 .lut_mask = 16'hE0FF; -defparam \z80_|alu_|db_high[0]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N4 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout = (\z80_|alu_|db_low[0]~23_combout & ((\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_low~combout & \z80_|alu_|db_high[0]~26_combout )))) # -// (!\z80_|alu_|db_low[0]~23_combout & (((\z80_|execute_|ctl_alu_op1_sel_low~combout & \z80_|alu_|db_high[0]~26_combout )))) - - .dataa(\z80_|alu_|db_low[0]~23_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .datad(\z80_|alu_|db_high[0]~26_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 .lut_mask = 16'hF888; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N30 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8_combout = (\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8 .lut_mask = 16'h00F0; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N12 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|ena ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|ena~combout = (\z80_|execute_|ctl_alu_op1_sel_low~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~combout ) # (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout )) - - .dataa(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|ena .lut_mask = 16'hFEFE; -defparam \z80_|alu_|b2v_op1_latch_mux_low|ena .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y10_N31 -dffeas \z80_|alu_|op1_low[0] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_low [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_low[0] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_low[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N12 -cycloneive_lcell_comb \z80_|alu_|alu_op1[0]~1 ( -// Equation(s): -// \z80_|alu_|alu_op1[0]~1_combout = (\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [0])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [0]))) - - .dataa(\z80_|execute_|ctl_alu_op_low~combout ), - .datab(\z80_|alu_|op1_low [0]), - .datac(\z80_|alu_|op1_high [0]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|alu_op1[0]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op1[0]~1 .lut_mask = 16'hD8D8; -defparam \z80_|alu_|alu_op1[0]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N30 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout = (\z80_|alu_|alu_op1[0]~1_combout & ((\z80_|execute_|ctl_alu_op2_sel_lq~combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~8_combout & \z80_|alu_|db_low[0]~23_combout )))) # -// (!\z80_|alu_|alu_op1[0]~1_combout & (\z80_|execute_|ctl_alu_op2_sel_bus~8_combout & ((\z80_|alu_|db_low[0]~23_combout )))) - - .dataa(\z80_|alu_|alu_op1[0]~1_combout ), - .datab(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datad(\z80_|alu_|db_low[0]~23_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 .lut_mask = 16'hECA0; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N14 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datab(gnd), - .datac(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 .lut_mask = 16'h5050; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y10_N15 -dffeas \z80_|alu_|op2_low[0] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_low [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_low[0] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_low[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N12 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout = (\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [0]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [0])) - - .dataa(\z80_|alu_|op2_low [0]), - .datab(gnd), - .datac(\z80_|alu_|op2_high [0]), - .datad(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'hF0AA; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N14 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout = (\z80_|alu_control_|alu_core_cf_in~0_combout & ((\z80_|alu_|alu_op1[0]~1_combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout $ -// (\z80_|execute_|ctl_alu_sel_op2_neg~18_combout )))) # (!\z80_|alu_control_|alu_core_cf_in~0_combout & (\z80_|alu_|alu_op1[0]~1_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout $ -// (\z80_|execute_|ctl_alu_sel_op2_neg~18_combout )))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), - .datac(\z80_|alu_control_|alu_core_cf_in~0_combout ), - .datad(\z80_|alu_|alu_op1[0]~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hF660; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N28 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|execute_|ctl_alu_core_S~9_combout & (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout & -// \z80_|execute_|ctl_alu_core_S~8_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_S~9_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), - .datac(\z80_|execute_|ctl_alu_core_R~combout ), - .datad(\z80_|execute_|ctl_alu_core_S~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 .lut_mask = 16'hF1F0; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N26 -cycloneive_lcell_comb \z80_|alu_|alu_op1[1]~0 ( -// Equation(s): -// \z80_|alu_|alu_op1[1]~0_combout = (\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [1])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [1]))) - - .dataa(\z80_|execute_|ctl_alu_op_low~combout ), - .datab(\z80_|alu_|op1_low [1]), - .datac(gnd), - .datad(\z80_|alu_|op1_high [1]), - .cin(gnd), - .combout(\z80_|alu_|alu_op1[1]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op1[1]~0 .lut_mask = 16'hDD88; -defparam \z80_|alu_|alu_op1[1]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N0 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout = (\z80_|execute_|ctl_alu_core_S~9_combout ) # (((\z80_|alu_|alu_op1[1]~0_combout & \z80_|alu_|alu_op2[1]~1_combout )) # (!\z80_|execute_|ctl_alu_core_S~8_combout )) - - .dataa(\z80_|execute_|ctl_alu_core_S~9_combout ), - .datab(\z80_|execute_|ctl_alu_core_S~8_combout ), - .datac(\z80_|alu_|alu_op1[1]~0_combout ), - .datad(\z80_|alu_|alu_op2[1]~1_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'hFBBB; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N24 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout = (!\z80_|execute_|ctl_alu_core_R~combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ) # -// ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout & !\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout )))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), - .datac(\z80_|execute_|ctl_alu_core_R~combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 .lut_mask = 16'h0F01; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N26 -cycloneive_lcell_comb \z80_|alu_|alu_op1[2]~2 ( -// Equation(s): -// \z80_|alu_|alu_op1[2]~2_combout = (\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [2]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [2])) - - .dataa(\z80_|alu_|op1_high [2]), - .datab(\z80_|execute_|ctl_alu_op_low~combout ), - .datac(gnd), - .datad(\z80_|alu_|op1_low [2]), - .cin(gnd), - .combout(\z80_|alu_|alu_op1[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op1[2]~2 .lut_mask = 16'hEE22; -defparam \z80_|alu_|alu_op1[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N8 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout = (\z80_|execute_|ctl_alu_core_S~9_combout ) # (((\z80_|alu_|alu_op2[2]~0_combout & \z80_|alu_|alu_op1[2]~2_combout )) # (!\z80_|execute_|ctl_alu_core_S~8_combout )) - - .dataa(\z80_|alu_|alu_op2[2]~0_combout ), - .datab(\z80_|execute_|ctl_alu_core_S~9_combout ), - .datac(\z80_|alu_|alu_op1[2]~2_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hECFF; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N2 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ) # -// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), - .datad(\z80_|execute_|ctl_alu_core_R~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 .lut_mask = 16'hFF0B; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~5 ( -// Equation(s): -// \z80_|execute_|ctl_alu_core_R~5_combout = (\z80_|execute_|ctl_alu_core_R~4_combout & \z80_|execute_|ctl_alu_core_S~8_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_alu_core_R~4_combout ), - .datad(\z80_|execute_|ctl_alu_core_S~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_core_R~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_core_R~5 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_alu_core_R~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N6 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ) # -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout )))) # (!\z80_|execute_|ctl_alu_core_R~5_combout ) - - .dataa(\z80_|execute_|ctl_alu_core_R~5_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1 .lut_mask = 16'h5F5D; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N14 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout = (\z80_|alu_|alu_op1[3]~3_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout & -// \z80_|alu_|alu_op2[3]~2_combout )))) # (!\z80_|alu_|alu_op1[3]~3_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_|alu_op2[3]~2_combout ) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout )))) - - .dataa(\z80_|alu_|alu_op1[3]~3_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), - .datac(\z80_|alu_|alu_op2[3]~2_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 .lut_mask = 16'hFB20; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N12 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder_combout = \z80_|reg_file_|gdfx_temp1[7]~75_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y13_N13 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y13_N19 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~69 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~69_combout = (\z80_|reg_file_|b2v_latch_bc_hi|latch [7] & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_hi|latch [7] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc_hi|latch [7]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~69_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~69 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[7]~69 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y12_N3 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y12_N25 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y12_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~70 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~70_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (\z80_|reg_file_|b2v_latch_ix_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_iy_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout & (((\z80_|reg_file_|b2v_latch_iy_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_iy_hi|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~70_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~70 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[7]~70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y15_N11 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y11_N27 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~72 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~72_combout = (\z80_|reg_file_|b2v_latch_sp_hi|latch [7] & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ))) # (!\z80_|reg_file_|b2v_latch_sp_hi|latch [7] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_sp_hi|latch [7]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~72_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~72 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[7]~72 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y11_N17 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~71 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~71_combout = (\z80_|alu_|db[7]~21_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[7]~21_combout & (!\z80_|execute_|ctl_reg_in_hi~12_combout & -// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|alu_|db[7]~21_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~71_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~71 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[7]~71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~73 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~73_combout = (\z80_|reg_file_|gdfx_temp1[7]~69_combout & (\z80_|reg_file_|gdfx_temp1[7]~70_combout & (\z80_|reg_file_|gdfx_temp1[7]~72_combout & \z80_|reg_file_|gdfx_temp1[7]~71_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[7]~69_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[7]~70_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[7]~72_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[7]~71_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~73_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~73 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[7]~73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y13_N27 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y13_N17 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~67 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~67_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~67_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~67 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[7]~67 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y14_N15 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N14 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[7]~20 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[7]~20_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [7]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [7]), - .datad(\z80_|reg_control_|reg_sel_af~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[7]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[7]~20 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[7]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N11 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y14_N21 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~68 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~68_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~68_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~68 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[7]~68 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y11_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~74 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~74_combout = (\z80_|reg_file_|gdfx_temp1[7]~73_combout & (\z80_|reg_file_|gdfx_temp1[7]~67_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[7]~20_combout & \z80_|reg_file_|gdfx_temp1[7]~68_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[7]~73_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[7]~67_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|db[7]~20_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[7]~68_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~74_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~74 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[7]~74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y15_N29 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[7]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N28 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~19 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[7]~19_combout = (\z80_|reg_file_|gdfx_temp1[7]~75_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) # (!\z80_|reg_file_|gdfx_temp1[7]~75_combout & -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [7]), - .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[7]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[7]~19 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_hi_as[7]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N27 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[7]~21_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N28 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~20 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[7]~20_combout = (\z80_|reg_file_|db_hi_as[7]~19_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|db_hi_as[7]~19_combout ), - .datab(gnd), - .datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[7]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[7]~20 .lut_mask = 16'hA0AA; -defparam \z80_|reg_file_|db_hi_as[7]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N2 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout & ((\z80_|execute_|ctl_inc_dec~11_combout & (!\z80_|address_latch_|Q [12] & -// !\z80_|address_latch_|Q [11])) # (!\z80_|execute_|ctl_inc_dec~11_combout & (\z80_|address_latch_|Q [12] & \z80_|address_latch_|Q [11])))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), - .datab(\z80_|execute_|ctl_inc_dec~11_combout ), - .datac(\z80_|address_latch_|Q [12]), - .datad(\z80_|address_latch_|Q [11]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'h2008; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N8 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout = \z80_|address_latch_|Q [13] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|address_latch_|Q [13]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out .lut_mask = 16'h0FF0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y12_N13 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y15_N5 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~54 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~54_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [5]), - .datad(\z80_|reg_file_|b2v_latch_sp_hi|latch [5]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~54_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~54 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[5]~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y11_N1 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~53 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~53_combout = (\z80_|alu_|db[5]~25_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[5]~25_combout & (!\z80_|execute_|ctl_reg_in_hi~12_combout & -// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|alu_|db[5]~25_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~53_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~53 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[5]~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N8 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder_combout = \z80_|reg_file_|gdfx_temp1[5]~57_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y13_N9 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y13_N11 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~51 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~51_combout = (\z80_|reg_file_|b2v_latch_bc_hi|latch [5] & (((\z80_|reg_file_|b2v_latch_bc2_hi|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))) # (!\z80_|reg_file_|b2v_latch_bc_hi|latch [5] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout & ((\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_bc_hi|latch [5]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~51_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~51 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[5]~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y12_N11 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y12_N3 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~52 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~52_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [5] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [5] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [5]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~52_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~52 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[5]~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~55 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~55_combout = (\z80_|reg_file_|gdfx_temp1[5]~54_combout & (\z80_|reg_file_|gdfx_temp1[5]~53_combout & (\z80_|reg_file_|gdfx_temp1[5]~51_combout & \z80_|reg_file_|gdfx_temp1[5]~52_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[5]~54_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[5]~53_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[5]~51_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[5]~52_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~55_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~55 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[5]~55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y13_N9 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y13_N3 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~49 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~49_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datab(\z80_|reg_file_|b2v_latch_de_hi|latch [5]), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~49 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[5]~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N5 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y14_N27 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~50 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~50_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [5]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [5]), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~50 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp1[5]~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y14_N21 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N20 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[5]~14 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[5]~14_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [5]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [5]), - .datad(\z80_|reg_control_|reg_sel_af~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[5]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[5]~14 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[5]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~56 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~56_combout = (\z80_|reg_file_|gdfx_temp1[5]~55_combout & (\z80_|reg_file_|gdfx_temp1[5]~49_combout & (\z80_|reg_file_|gdfx_temp1[5]~50_combout & \z80_|reg_file_|b2v_latch_af_hi|db[5]~14_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[5]~55_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[5]~49_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[5]~50_combout ), - .datad(\z80_|reg_file_|b2v_latch_af_hi|db[5]~14_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~56_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~56 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[5]~56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~57 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[5]~57_combout = ((\z80_|reg_file_|gdfx_temp1[5]~56_combout & ((\z80_|reg_file_|db_hi_as[5]~15_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[5]~56_combout ), - .datac(\z80_|reg_file_|db_hi_as[5]~15_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[5]~57 .lut_mask = 16'hD5DD; -defparam \z80_|reg_file_|gdfx_temp1[5]~57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y15_N1 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[5]~15_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N0 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~13 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[5]~13_combout = (\z80_|reg_control_|reg_sw_4d_hi~0_combout & (\z80_|reg_file_|gdfx_temp1[5]~57_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) - - .dataa(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[5]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[5]~13 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|db_hi_as[5]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N23 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[5]~15_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N16 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~14 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[5]~14_combout = (\z80_|reg_file_|db_hi_as[5]~13_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .datab(\z80_|reg_file_|db_hi_as[5]~13_combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [5]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[5]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[5]~14 .lut_mask = 16'hC4C4; -defparam \z80_|reg_file_|db_hi_as[5]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N22 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~15 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[5]~15_combout = ((\z80_|reg_file_|db_hi_as[5]~14_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datad(\z80_|reg_file_|db_hi_as[5]~14_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[5]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[5]~15 .lut_mask = 16'hBF0F; -defparam \z80_|reg_file_|db_hi_as[5]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N2 -cycloneive_lcell_comb \z80_|address_latch_|abusz[13] ( -// Equation(s): -// \z80_|address_latch_|abusz [13] = (\z80_|reg_file_|db_hi_as[5]~15_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(gnd), - .datab(\z80_|reg_file_|db_hi_as[5]~15_combout ), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [13]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[13] .lut_mask = 16'h0C0C; -defparam \z80_|address_latch_|abusz[13] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N22 -cycloneive_lcell_comb \z80_|address_latch_|Q[13]~feeder ( -// Equation(s): -// \z80_|address_latch_|Q[13]~feeder_combout = \z80_|address_latch_|abusz [13] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [13]), - .cin(gnd), - .combout(\z80_|address_latch_|Q[13]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|Q[13]~feeder .lut_mask = 16'hFF00; -defparam \z80_|address_latch_|Q[13]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N23 -dffeas \z80_|address_latch_|Q[13] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|Q[13]~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [13]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[13] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[13] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N6 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout = \z80_|address_latch_|Q [13] $ (\z80_|execute_|ctl_inc_dec~11_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|address_latch_|Q [13]), - .datad(\z80_|execute_|ctl_inc_dec~11_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 .lut_mask = 16'h0FF0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N26 -cycloneive_lcell_comb \z80_|address_latch_|abusz[15] ( -// Equation(s): -// \z80_|address_latch_|abusz [15] = (\z80_|reg_file_|db_hi_as[7]~21_combout & !\z80_|resets_|clrpc~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|reg_file_|db_hi_as[7]~21_combout ), - .datad(\z80_|resets_|clrpc~0_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [15]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[15] .lut_mask = 16'h00F0; -defparam \z80_|address_latch_|abusz[15] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N27 -dffeas \z80_|address_latch_|Q[15] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [15]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [15]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[15] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[15] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N20 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[14] ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|address [14] = \z80_|address_latch_|Q [14] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout & (\z80_|address_latch_|Q [13] $ (\z80_|execute_|ctl_inc_dec~11_combout ))))) - - .dataa(\z80_|address_latch_|Q [13]), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), - .datac(\z80_|address_latch_|Q [14]), - .datad(\z80_|execute_|ctl_inc_dec~11_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[14] .lut_mask = 16'hB478; -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[14] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y16_N7 -dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_hi_as[6]~24_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y13_N11 -dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y13_N21 -dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y13_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~76 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~76_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~76_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~76 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp1[6]~76 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y11_N23 -dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y11_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~80 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~80_combout = (\z80_|alu_|db[6]~23_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # (!\z80_|alu_|db[6]~23_combout & (!\z80_|execute_|ctl_reg_in_hi~12_combout & -// ((\z80_|reg_file_|b2v_latch_af2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) - - .dataa(\z80_|alu_|db[6]~23_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~12_combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~80_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~80 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp1[6]~80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y12_N17 -dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y12_N9 -dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~79 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~79_combout = (\z80_|reg_file_|b2v_latch_iy_hi|latch [6] & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) # (!\z80_|reg_file_|b2v_latch_iy_hi|latch [6] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_iy_hi|latch [6]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~79_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~79 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp1[6]~79 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y13_N27 -dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y13_N29 -dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y13_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~78 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~78_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (\z80_|reg_file_|b2v_latch_bc2_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_bc_hi|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~78_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~78 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[6]~78 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y15_N25 -dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y12_N7 -dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~81 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~81_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (\z80_|reg_file_|b2v_latch_sp_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_wz_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout & (((\z80_|reg_file_|b2v_latch_wz_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [6]), - .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~81_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~81 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp1[6]~81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y12_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~82 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~82_combout = (\z80_|reg_file_|gdfx_temp1[6]~80_combout & (\z80_|reg_file_|gdfx_temp1[6]~79_combout & (\z80_|reg_file_|gdfx_temp1[6]~78_combout & \z80_|reg_file_|gdfx_temp1[6]~81_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[6]~80_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[6]~79_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[6]~78_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[6]~81_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~82_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~82 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[6]~82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y14_N23 -dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y14_N25 -dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y14_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~77 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~77_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (\z80_|reg_file_|b2v_latch_hl2_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout & (((\z80_|reg_file_|b2v_latch_hl_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~77_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~77 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp1[6]~77 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y14_N13 -dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N12 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[6]~21 ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_hi|db[6]~21_combout = (\z80_|execute_|ctl_reg_gp_we~6_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [6]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout )) - - .dataa(\z80_|execute_|ctl_reg_gp_we~6_combout ), - .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~46_combout ), - .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [6]), - .datad(\z80_|reg_control_|reg_sel_af~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_hi|db[6]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_hi|db[6]~21 .lut_mask = 16'hFBFF; -defparam \z80_|reg_file_|b2v_latch_af_hi|db[6]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y14_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~83 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~83_combout = (\z80_|reg_file_|gdfx_temp1[6]~76_combout & (\z80_|reg_file_|gdfx_temp1[6]~82_combout & (\z80_|reg_file_|gdfx_temp1[6]~77_combout & \z80_|reg_file_|b2v_latch_af_hi|db[6]~21_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp1[6]~76_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[6]~82_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[6]~77_combout ), - .datad(\z80_|reg_file_|b2v_latch_af_hi|db[6]~21_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~83_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~83 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp1[6]~83 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~84 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[6]~84_combout = ((\z80_|reg_file_|gdfx_temp1[6]~83_combout & ((\z80_|reg_file_|db_hi_as[6]~24_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[6]~83_combout ), - .datac(\z80_|reg_file_|db_hi_as[6]~24_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[6]~84 .lut_mask = 16'hD5DD; -defparam \z80_|reg_file_|gdfx_temp1[6]~84 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y15_N19 -dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_hi_as[6]~24_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N18 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~22 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[6]~22_combout = (\z80_|reg_control_|reg_sw_4d_hi~0_combout & (\z80_|reg_file_|gdfx_temp1[6]~84_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # -// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) - - .dataa(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[6]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[6]~22 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|db_hi_as[6]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N20 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~23 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[6]~23_combout = (\z80_|reg_file_|db_hi_as[6]~22_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) - - .dataa(\z80_|reg_file_|b2v_latch_pc_hi|latch [6]), - .datab(\z80_|reg_file_|db_hi_as[6]~22_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[6]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[6]~23 .lut_mask = 16'h88CC; -defparam \z80_|reg_file_|db_hi_as[6]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N6 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~24 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[6]~24_combout = ((\z80_|reg_file_|db_hi_as[6]~23_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [14]) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), - .datab(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datad(\z80_|reg_file_|db_hi_as[6]~23_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[6]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[6]~24 .lut_mask = 16'hBF33; -defparam \z80_|reg_file_|db_hi_as[6]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N14 -cycloneive_lcell_comb \z80_|address_latch_|abusz[14] ( -// Equation(s): -// \z80_|address_latch_|abusz [14] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[6]~24_combout ) - - .dataa(\z80_|resets_|clrpc~0_combout ), - .datab(gnd), - .datac(\z80_|reg_file_|db_hi_as[6]~24_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [14]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[14] .lut_mask = 16'h5050; -defparam \z80_|address_latch_|abusz[14] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N4 -cycloneive_lcell_comb \z80_|address_latch_|Q[14]~feeder ( -// Equation(s): -// \z80_|address_latch_|Q[14]~feeder_combout = \z80_|address_latch_|abusz [14] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [14]), - .cin(gnd), - .combout(\z80_|address_latch_|Q[14]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|Q[14]~feeder .lut_mask = 16'hFF00; -defparam \z80_|address_latch_|Q[14]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N5 -dffeas \z80_|address_latch_|Q[14] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|Q[14]~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [14]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[14] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[14] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y16_N4 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout = \z80_|address_latch_|Q [14] $ (((\z80_|execute_|ctl_inc_dec~9_combout ) # ((\z80_|execute_|ctl_inc_dec~7_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout )))) - - .dataa(\z80_|execute_|ctl_inc_dec~9_combout ), - .datab(\z80_|address_latch_|Q [14]), - .datac(\z80_|execute_|ctl_inc_dec~6_combout ), - .datad(\z80_|execute_|ctl_inc_dec~7_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16 .lut_mask = 16'h3363; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N12 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[15] ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|address [15] = \z80_|address_latch_|Q [15] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout & -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout )))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), - .datac(\z80_|address_latch_|Q [15]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16~combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [15]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[15] .lut_mask = 16'h78F0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[15] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y16_N26 -cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~21 ( -// Equation(s): -// \z80_|reg_file_|db_hi_as[7]~21_combout = ((\z80_|reg_file_|db_hi_as[7]~20_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [15]) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_hi_as[7]~20_combout ), - .datab(\z80_|reg_file_|db_hi_as[0]~2_combout ), - .datac(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|address [15]), - .cin(gnd), - .combout(\z80_|reg_file_|db_hi_as[7]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_hi_as[7]~21 .lut_mask = 16'hBB3B; -defparam \z80_|reg_file_|db_hi_as[7]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y15_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~75 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp1[7]~75_combout = ((\z80_|reg_file_|gdfx_temp1[7]~74_combout & ((\z80_|reg_file_|db_hi_as[7]~21_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), - .datab(\z80_|reg_file_|gdfx_temp1[7]~74_combout ), - .datac(\z80_|reg_file_|db_hi_as[7]~21_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp1[7]~75 .lut_mask = 16'hD5DD; -defparam \z80_|reg_file_|gdfx_temp1[7]~75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N6 -cycloneive_lcell_comb \z80_|alu_|db[7]~20 ( -// Equation(s): -// \z80_|alu_|db[7]~20_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[7]~75_combout & ((\z80_|alu_control_|db[7]~18_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & -// (((\z80_|alu_control_|db[7]~18_combout )) # (!\z80_|execute_|ctl_sw_2d~13_combout ))) - - .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datab(\z80_|execute_|ctl_sw_2d~13_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), - .datad(\z80_|alu_control_|db[7]~18_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[7]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[7]~20 .lut_mask = 16'hF531; -defparam \z80_|alu_|db[7]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N24 -cycloneive_lcell_comb \z80_|alu_|db[7]~21 ( -// Equation(s): -// \z80_|alu_|db[7]~21_combout = ((\z80_|alu_|db[7]~20_combout & ((\z80_|alu_|db_high[3]~8_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~26_combout ) - - .dataa(\z80_|alu_|db[7]~20_combout ), - .datab(\z80_|alu_|db[7]~26_combout ), - .datac(\z80_|alu_|db_high[3]~8_combout ), - .datad(\z80_|execute_|ctl_alu_oe~14_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[7]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[7]~21 .lut_mask = 16'hB3BB; -defparam \z80_|alu_|db[7]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N22 -cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~1 ( -// Equation(s): -// \z80_|alu_control_|b2v_inst_shift_mux|out~1_combout = (\z80_|ir_|opcode [5] & (\z80_|alu_|db[7]~21_combout & ((\z80_|ir_|opcode [3])))) # (!\z80_|ir_|opcode [5] & ((\z80_|ir_|opcode [3] & ((\z80_|alu_|db[0]~19_combout ))) # (!\z80_|ir_|opcode [3] & -// (\z80_|alu_|db[7]~21_combout )))) - - .dataa(\z80_|alu_|db[7]~21_combout ), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|alu_|db[0]~19_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~1 .lut_mask = 16'hB822; -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N4 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~0 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf~0_combout = (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & (\z80_|alu_control_|db[0]~12_combout & (\z80_|execute_|ctl_flags_bus~combout ))) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & -// ((\z80_|execute_|ctl_flags_alu~15_combout ) # ((\z80_|alu_control_|db[0]~12_combout & \z80_|execute_|ctl_flags_bus~combout )))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), - .datab(\z80_|alu_control_|db[0]~12_combout ), - .datac(\z80_|execute_|ctl_flags_bus~combout ), - .datad(\z80_|execute_|ctl_flags_alu~15_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~0 .lut_mask = 16'hD5C0; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~4_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # ((\z80_|execute_|ixy_d~6_combout & \z80_|execute_|ctl_mRead~36_combout ))) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|execute_|ctl_mRead~36_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~4 .lut_mask = 16'hFFF8; -defparam \z80_|execute_|ctl_flags_cf_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~5_combout = ((\z80_|execute_|ctl_flags_cf_we~4_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # (\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ))) # (!\z80_|execute_|ctl_flags_cf_we~7_combout ) - - .dataa(\z80_|execute_|ctl_flags_cf_we~7_combout ), - .datab(\z80_|execute_|ctl_flags_cf_we~4_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .datad(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~5 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_flags_cf_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y12_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~3_combout = (\z80_|execute_|ctl_flags_hf2_we~combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((!\z80_|execute_|ctl_flags_bus~5_combout ) # (!\z80_|execute_|ctl_flags_bus~4_combout )))) - - .dataa(\z80_|execute_|ctl_flags_bus~4_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|execute_|ctl_flags_hf2_we~combout ), - .datad(\z80_|execute_|ctl_flags_bus~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~3 .lut_mask = 16'hF4FC; -defparam \z80_|execute_|ctl_flags_cf_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_we~6_combout = ((\z80_|execute_|ctl_flags_cf_we~5_combout ) # ((\z80_|execute_|ctl_flags_cf_we~3_combout ) # (!\z80_|execute_|ctl_flags_cf_we~2_combout ))) # (!\z80_|execute_|ctl_flags_hf_we~2_combout ) - - .dataa(\z80_|execute_|ctl_flags_hf_we~2_combout ), - .datab(\z80_|execute_|ctl_flags_cf_we~5_combout ), - .datac(\z80_|execute_|ctl_flags_cf_we~3_combout ), - .datad(\z80_|execute_|ctl_flags_cf_we~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_we~6 .lut_mask = 16'hFDFF; -defparam \z80_|execute_|ctl_flags_cf_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_we~2_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~38_combout ) # (!\z80_|execute_|ctl_alu_op1_sel_bus~7_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_we~2 .lut_mask = 16'hCFFF; -defparam \z80_|execute_|ctl_flags_cf2_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_we~4_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & ((\z80_|pla_decode_|Equal11~0_combout ) # (\z80_|pla_decode_|Equal10~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal11~0_combout ), - .datab(\z80_|pla_decode_|Equal10~0_combout ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_we~4 .lut_mask = 16'hE000; -defparam \z80_|execute_|ctl_flags_cf2_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_we~3_combout = (\z80_|execute_|ctl_flags_cf2_we~2_combout ) # ((\z80_|execute_|ctl_flags_cf2_we~4_combout ) # ((\z80_|sequencer_|DFFE_T3_ff~q & \z80_|execute_|ixy_d~15_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|execute_|ctl_flags_cf2_we~2_combout ), - .datac(\z80_|execute_|ixy_d~15_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_we~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_we~3 .lut_mask = 16'hFFEC; -defparam \z80_|execute_|ctl_flags_cf2_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N2 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~1 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf~1_combout = (\z80_|execute_|ctl_flags_cf_we~6_combout & ((\z80_|execute_|ctl_flags_cf2_we~3_combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf~q ))) # (!\z80_|execute_|ctl_flags_cf2_we~3_combout & -// (\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout )))) # (!\z80_|execute_|ctl_flags_cf_we~6_combout & (((\z80_|alu_flags_|DFFE_inst_latch_cf~q )))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ), - .datab(\z80_|execute_|ctl_flags_cf_we~6_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), - .datad(\z80_|execute_|ctl_flags_cf2_we~3_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~1 .lut_mask = 16'hF0B8; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y9_N3 -dffeas \z80_|alu_flags_|DFFE_inst_latch_cf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N0 -cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~0 ( -// Equation(s): -// \z80_|alu_control_|b2v_inst_shift_mux|out~0_combout = (\z80_|ir_|opcode [4] & ((\z80_|ir_|opcode [5] & ((!\z80_|ir_|opcode [3]))) # (!\z80_|ir_|opcode [5] & (\z80_|alu_flags_|DFFE_inst_latch_cf~q )))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [5]), - .cin(gnd), - .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~0 .lut_mask = 16'h0A88; -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N4 -cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~2 ( -// Equation(s): -// \z80_|alu_control_|b2v_inst_shift_mux|out~2_combout = (\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ) # ((\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout & !\z80_|ir_|opcode [4])) - - .dataa(\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ), - .datab(\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ), - .datac(gnd), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~2 .lut_mask = 16'hCCEE; -defparam \z80_|alu_control_|b2v_inst_shift_mux|out~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N14 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~5 ( -// Equation(s): -// \z80_|alu_|db_high[3]~5_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[6]~23_combout ))) - - .dataa(gnd), - .datab(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), - .datac(\z80_|alu_|db[6]~23_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~5 .lut_mask = 16'hCCF0; -defparam \z80_|alu_|db_high[3]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N20 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~6 ( -// Equation(s): -// \z80_|alu_|db_high[3]~6_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_high[3]~5_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[7]~21_combout ))) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .datab(\z80_|alu_|db_high[3]~5_combout ), - .datac(\z80_|alu_|db[7]~21_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~6 .lut_mask = 16'hD8D8; -defparam \z80_|alu_|db_high[3]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N28 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~4 ( -// Equation(s): -// \z80_|alu_|db_high[3]~4_combout = (\z80_|alu_|op2_high [3] & (((\z80_|alu_|op1_high [3])) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout ))) # (!\z80_|alu_|op2_high [3] & (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_high [3]) # -// (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) - - .dataa(\z80_|alu_|op2_high [3]), - .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datac(\z80_|alu_|op1_high [3]), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~4 .lut_mask = 16'hA2F3; -defparam \z80_|alu_|db_high[3]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N30 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~27 ( -// Equation(s): -// \z80_|alu_|db_high[3]~27_combout = ((\z80_|bus_control_|db[4]~19_combout & (\z80_|bus_control_|db[5]~15_combout & \z80_|bus_control_|db[3]~21_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datab(\z80_|bus_control_|db[4]~19_combout ), - .datac(\z80_|bus_control_|db[5]~15_combout ), - .datad(\z80_|bus_control_|db[3]~21_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~27 .lut_mask = 16'hD555; -defparam \z80_|alu_|db_high[3]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N6 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~7 ( -// Equation(s): -// \z80_|alu_|db_high[3]~7_combout = (\z80_|alu_|db_high[3]~4_combout & (\z80_|alu_|db_high[3]~27_combout & ((\z80_|alu_|db_high[3]~6_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) - - .dataa(\z80_|alu_|db_high[3]~6_combout ), - .datab(\z80_|alu_|db_high[3]~4_combout ), - .datac(\z80_|alu_|db_high[3]~27_combout ), - .datad(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~7 .lut_mask = 16'h80C0; -defparam \z80_|alu_|db_high[3]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N28 -cycloneive_lcell_comb \z80_|alu_|db_high[3]~8 ( -// Equation(s): -// \z80_|alu_|db_high[3]~8_combout = ((\z80_|alu_|db_high[3]~7_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) # (!\z80_|alu_|db_high[3]~3_combout ) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), - .datab(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datac(\z80_|alu_|db_high[3]~7_combout ), - .datad(\z80_|alu_|db_high[3]~3_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[3]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[3]~8 .lut_mask = 16'hE0FF; -defparam \z80_|alu_|db_high[3]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N14 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & ((\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_low~combout & \z80_|alu_|db_high[3]~8_combout )))) - - .dataa(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .datac(\z80_|alu_|db_high[3]~8_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4 .lut_mask = 16'h00EA; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y10_N15 -dffeas \z80_|alu_|op1_low[3] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_low [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_low[3] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_low[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N0 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~9 ( -// Equation(s): -// \z80_|alu_|db_low[3]~9_combout = (\z80_|alu_|op1_low [3] & (((\z80_|alu_|op2_low [3]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|alu_|op1_low [3] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_low [3]) # -// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) - - .dataa(\z80_|alu_|op1_low [3]), - .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datac(\z80_|alu_|op2_low [3]), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~9 .lut_mask = 16'hB0BB; -defparam \z80_|alu_|db_low[3]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N10 -cycloneive_lcell_comb \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 ( -// Equation(s): -// \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout = (\z80_|bus_control_|db[4]~19_combout & \z80_|bus_control_|db[3]~21_combout ) - - .dataa(gnd), - .datab(\z80_|bus_control_|db[4]~19_combout ), - .datac(gnd), - .datad(\z80_|bus_control_|db[3]~21_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 .lut_mask = 16'hCC00; -defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N24 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~10 ( -// Equation(s): -// \z80_|alu_|db_low[3]~10_combout = (\z80_|alu_|db_low[3]~9_combout & (((!\z80_|bus_control_|db[5]~15_combout & \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout )) # (!\z80_|execute_|ctl_alu_bs_oe~combout ))) - - .dataa(\z80_|bus_control_|db[5]~15_combout ), - .datab(\z80_|alu_|db_low[3]~9_combout ), - .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datad(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~10 .lut_mask = 16'h4C0C; -defparam \z80_|alu_|db_low[3]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y10_N15 -dffeas \z80_|alu_|result_lo[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_alu_op_low~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|result_lo [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|result_lo[3] .is_wysiwyg = "true"; -defparam \z80_|alu_|result_lo[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N14 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~7 ( -// Equation(s): -// \z80_|alu_|db_low[3]~7_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[4]~17_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[2]~15_combout ))) - - .dataa(\z80_|alu_|db[4]~17_combout ), - .datab(gnd), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|alu_|db[2]~15_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~7 .lut_mask = 16'hAFA0; -defparam \z80_|alu_|db_low[3]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N28 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~8 ( -// Equation(s): -// \z80_|alu_|db_low[3]~8_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_low[3]~7_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[3]~11_combout ))) # -// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) - - .dataa(\z80_|alu_|db[3]~11_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datac(\z80_|alu_|db_low[3]~7_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~8 .lut_mask = 16'hF3BB; -defparam \z80_|alu_|db_low[3]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N8 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~11 ( -// Equation(s): -// \z80_|alu_|db_low[3]~11_combout = (\z80_|alu_|db_low[3]~10_combout & (\z80_|alu_|db_low[3]~8_combout & ((\z80_|alu_|result_lo [3]) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) - - .dataa(\z80_|alu_|db_low[3]~10_combout ), - .datab(\z80_|alu_|result_lo [3]), - .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datad(\z80_|alu_|db_low[3]~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~11 .lut_mask = 16'hA800; -defparam \z80_|alu_|db_low[3]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N6 -cycloneive_lcell_comb \z80_|alu_|db_low[3]~25 ( -// Equation(s): -// \z80_|alu_|db_low[3]~25_combout = (\z80_|alu_|db_low[3]~11_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~43_combout & !\z80_|alu_|db_high[3]~2_combout )) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datab(\z80_|alu_|db_high[3]~2_combout ), - .datac(\z80_|alu_|db_low[3]~11_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|db_low[3]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[3]~25 .lut_mask = 16'hF1F1; -defparam \z80_|alu_|db_low[3]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y14_N12 -cycloneive_lcell_comb \z80_|alu_|db[3]~10 ( -// Equation(s): -// \z80_|alu_|db[3]~10_combout = (\z80_|execute_|ctl_alu_oe~14_combout & (\z80_|alu_|db_low[3]~25_combout & ((\z80_|reg_file_|gdfx_temp1[3]~48_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) # (!\z80_|execute_|ctl_alu_oe~14_combout & -// (((\z80_|reg_file_|gdfx_temp1[3]~48_combout )) # (!\z80_|execute_|ctl_reg_out_hi~7_combout ))) - - .dataa(\z80_|execute_|ctl_alu_oe~14_combout ), - .datab(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), - .datad(\z80_|alu_|db_low[3]~25_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[3]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[3]~10 .lut_mask = 16'hF351; -defparam \z80_|alu_|db[3]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N12 -cycloneive_lcell_comb \z80_|alu_|db[3]~11 ( -// Equation(s): -// \z80_|alu_|db[3]~11_combout = ((\z80_|alu_|db[3]~10_combout & ((\z80_|alu_control_|db[3]~35_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|alu_|db[7]~26_combout ) - - .dataa(\z80_|alu_|db[3]~10_combout ), - .datab(\z80_|execute_|ctl_sw_2d~13_combout ), - .datac(\z80_|alu_control_|db[3]~35_combout ), - .datad(\z80_|alu_|db[7]~26_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[3]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[3]~11 .lut_mask = 16'hA2FF; -defparam \z80_|alu_|db[3]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y16_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~7 ( -// Equation(s): -// \z80_|execute_|ctl_sw_2u~7_combout = (((\z80_|nM1_int~2_combout & \z80_|execute_|ctl_alu_oe~3_combout )) # (!\z80_|execute_|ctl_reg_out_hi~6_combout )) # (!\z80_|execute_|ctl_alu_oe~9_combout ) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_alu_oe~3_combout ), - .datac(\z80_|execute_|ctl_alu_oe~9_combout ), - .datad(\z80_|execute_|ctl_reg_out_hi~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_2u~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_2u~7 .lut_mask = 16'h8FFF; -defparam \z80_|execute_|ctl_sw_2u~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N0 -cycloneive_lcell_comb \z80_|execute_|setM1~49 ( -// Equation(s): -// \z80_|execute_|setM1~49_combout = (\z80_|execute_|setM1~48_combout & (!\z80_|pla_decode_|Equal52~1_combout & ((!\z80_|pla_decode_|Equal63~0_combout ) # (!\z80_|pla_decode_|Equal3~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal3~0_combout ), - .datab(\z80_|pla_decode_|Equal63~0_combout ), - .datac(\z80_|execute_|setM1~48_combout ), - .datad(\z80_|pla_decode_|Equal52~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~49_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~49 .lut_mask = 16'h0070; -defparam \z80_|execute_|setM1~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_oe~2_combout = (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_state_alu~14_combout ) # ((!\z80_|execute_|ctl_flags_oe~1_combout ) # (!\z80_|execute_|setM1~49_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~14_combout ), - .datab(\z80_|execute_|setM1~49_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|execute_|ctl_flags_oe~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_oe~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_oe~2 .lut_mask = 16'h0B0F; -defparam \z80_|execute_|ctl_flags_oe~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N30 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_35 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout = (\z80_|alu_|db_low[3]~25_combout & ((\z80_|execute_|ctl_flags_alu~15_combout ) # ((\z80_|alu_control_|db[3]~35_combout & \z80_|execute_|ctl_flags_bus~combout )))) # (!\z80_|alu_|db_low[3]~25_combout & -// (\z80_|alu_control_|db[3]~35_combout & (\z80_|execute_|ctl_flags_bus~combout ))) - - .dataa(\z80_|alu_|db_low[3]~25_combout ), - .datab(\z80_|alu_control_|db[3]~35_combout ), - .datac(\z80_|execute_|ctl_flags_bus~combout ), - .datad(\z80_|execute_|ctl_flags_alu~15_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_35 .lut_mask = 16'hEAC0; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~7_combout = (\z80_|execute_|ctl_flags_xy_we~12_combout & !\z80_|execute_|ctl_flags_sz_we~6_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_flags_xy_we~12_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_flags_sz_we~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~7 .lut_mask = 16'h00CC; -defparam \z80_|execute_|ctl_flags_sz_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout = (\z80_|pla_decode_|Equal56~0_combout & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T2_ff~q )) - - .dataa(\z80_|pla_decode_|Equal56~0_combout ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3 .lut_mask = 16'h8080; -defparam \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~13 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~13_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ) # ((\z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ) # -// (!\z80_|execute_|ctl_flags_xy_we~10_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3~combout ), - .datab(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~0_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), - .datad(\z80_|execute_|ctl_flags_xy_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~13 .lut_mask = 16'hFEFF; -defparam \z80_|execute_|ctl_flags_xy_we~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y13_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~14 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~14_combout = (((\z80_|execute_|ctl_flags_xy_we~13_combout ) # (!\z80_|execute_|ctl_flags_xy_we~7_combout )) # (!\z80_|execute_|ctl_flags_xy_we~9_combout )) # (!\z80_|execute_|ctl_flags_xy_we~16_combout ) - - .dataa(\z80_|execute_|ctl_flags_xy_we~16_combout ), - .datab(\z80_|execute_|ctl_flags_xy_we~9_combout ), - .datac(\z80_|execute_|ctl_flags_xy_we~13_combout ), - .datad(\z80_|execute_|ctl_flags_xy_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~14 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|ctl_flags_xy_we~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~15 ( -// Equation(s): -// \z80_|execute_|ctl_flags_xy_we~15_combout = (((\z80_|execute_|ctl_flags_xy_we~14_combout ) # (!\z80_|execute_|ctl_flags_pf_we~4_combout )) # (!\z80_|execute_|ctl_flags_sz_we~7_combout )) # (!\z80_|execute_|ctl_pf_sel[0]~3_combout ) - - .dataa(\z80_|execute_|ctl_pf_sel[0]~3_combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~7_combout ), - .datac(\z80_|execute_|ctl_flags_pf_we~4_combout ), - .datad(\z80_|execute_|ctl_flags_xy_we~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_xy_we~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_xy_we~15 .lut_mask = 16'hFF7F; -defparam \z80_|execute_|ctl_flags_xy_we~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y11_N31 -dffeas \z80_|alu_flags_|flags_xf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_flags_xy_we~15_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|flags_xf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_xf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|flags_xf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N8 -cycloneive_lcell_comb \z80_|alu_control_|db[3]~33 ( -// Equation(s): -// \z80_|alu_control_|db[3]~33_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & ((\z80_|alu_flags_|flags_xf~q ) # (!\z80_|execute_|ctl_flags_oe~2_combout ))) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_flags_oe~2_combout ), - .datac(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .datad(\z80_|alu_flags_|flags_xf~q ), - .cin(gnd), - .combout(\z80_|alu_control_|db[3]~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[3]~33 .lut_mask = 16'hF030; -defparam \z80_|alu_control_|db[3]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y14_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~3_combout = (\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ) # ((\z80_|execute_|ctl_reg_out_lo~2_combout & \z80_|execute_|rsel3~combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), - .datab(\z80_|execute_|ctl_reg_out_lo~2_combout ), - .datac(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), - .datad(\z80_|execute_|rsel3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~3 .lut_mask = 16'hFEFA; -defparam \z80_|execute_|ctl_reg_out_lo~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout = (\z80_|pla_decode_|Equal1~7_combout & (\z80_|execute_|ixy_d~7_combout & (!\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal3~1_combout ))) - - .dataa(\z80_|pla_decode_|Equal1~7_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|pla_decode_|Equal3~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~4 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~4_combout = (\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ) # ((\z80_|execute_|ixy_d~9_combout & ((\z80_|pla_decode_|Equal40~1_combout ) # (\z80_|pla_decode_|Equal39~0_combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ), - .datab(\z80_|pla_decode_|Equal40~1_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~4 .lut_mask = 16'hFAEA; -defparam \z80_|execute_|ctl_reg_out_lo~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y14_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~5 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~5_combout = (\z80_|execute_|ctl_reg_out_lo~3_combout ) # (((\z80_|execute_|ctl_reg_out_lo~4_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout )) # (!\z80_|execute_|ctl_reg_out_lo~9_combout )) - - .dataa(\z80_|execute_|ctl_reg_out_lo~3_combout ), - .datab(\z80_|execute_|ctl_reg_out_lo~9_combout ), - .datac(\z80_|execute_|ctl_reg_out_lo~4_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~5 .lut_mask = 16'hFBFF; -defparam \z80_|execute_|ctl_reg_out_lo~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~8 ( -// Equation(s): -// \z80_|execute_|ctl_reg_out_lo~8_combout = ((\z80_|execute_|ctl_reg_out_lo~5_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout )) # (!\z80_|execute_|ctl_reg_out_lo~7_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), - .datad(\z80_|execute_|ctl_reg_out_lo~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_out_lo~8 .lut_mask = 16'hFF3F; -defparam \z80_|execute_|ctl_reg_out_lo~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N16 -cycloneive_lcell_comb \z80_|sw1_|db_down[3]~1 ( -// Equation(s): -// \z80_|sw1_|db_down[3]~1_combout = (\z80_|bus_control_|db[3]~21_combout ) # ((\z80_|execute_|ctl_sw_1d~6_combout & ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|execute_|ctl_66_oe~2_combout )))) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|execute_|ctl_sw_1d~6_combout ), - .datac(\z80_|execute_|ctl_66_oe~2_combout ), - .datad(\z80_|bus_control_|db[3]~21_combout ), - .cin(gnd), - .combout(\z80_|sw1_|db_down[3]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sw1_|db_down[3]~1 .lut_mask = 16'hFF8C; -defparam \z80_|sw1_|db_down[3]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N10 -cycloneive_lcell_comb \z80_|alu_control_|db[3]~34 ( -// Equation(s): -// \z80_|alu_control_|db[3]~34_combout = (\z80_|alu_control_|db[3]~33_combout & (\z80_|sw1_|db_down[3]~1_combout & ((\z80_|reg_file_|gdfx_temp0[3]~52_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .datab(\z80_|alu_control_|db[3]~33_combout ), - .datac(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datad(\z80_|sw1_|db_down[3]~1_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[3]~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[3]~34 .lut_mask = 16'h8C00; -defparam \z80_|alu_control_|db[3]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N0 -cycloneive_lcell_comb \z80_|alu_control_|db[3]~35 ( -// Equation(s): -// \z80_|alu_control_|db[3]~35_combout = ((\z80_|alu_control_|db[3]~34_combout & ((\z80_|alu_|db[3]~11_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|alu_|db[3]~11_combout ), - .datab(\z80_|alu_control_|db[6]~11_combout ), - .datac(\z80_|execute_|ctl_sw_2u~7_combout ), - .datad(\z80_|alu_control_|db[3]~34_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[3]~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[3]~35 .lut_mask = 16'hBF33; -defparam \z80_|alu_control_|db[3]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~46 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~46_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [3] & ((\z80_|alu_control_|db[3]~35_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (((\z80_|alu_control_|db[3]~35_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [3]), - .datad(\z80_|alu_control_|db[3]~35_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~46_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~46 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[3]~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~47 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~47_combout = (\z80_|reg_file_|gdfx_temp0[3]~46_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(\z80_|reg_file_|b2v_latch_wz_lo|latch [3]), - .datab(gnd), - .datac(\z80_|reg_file_|gdfx_temp0[3]~46_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~47_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~47 .lut_mask = 16'hA0F0; -defparam \z80_|reg_file_|gdfx_temp0[3]~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~50 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~50_combout = (\z80_|reg_file_|gdfx_temp0[3]~48_combout & (\z80_|reg_file_|gdfx_temp0[3]~49_combout & \z80_|reg_file_|gdfx_temp0[3]~47_combout )) - - .dataa(gnd), - .datab(\z80_|reg_file_|gdfx_temp0[3]~48_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[3]~49_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[3]~47_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~50 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|gdfx_temp0[3]~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y9_N31 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y9_N5 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~44 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~44_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [3] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [3] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [3]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~44 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[3]~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y13_N7 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y13_N5 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~43 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~43_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [3] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [3] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [3]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [3]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~43 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[3]~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~51 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~51_combout = (\z80_|reg_file_|gdfx_temp0[3]~45_combout & (\z80_|reg_file_|gdfx_temp0[3]~50_combout & (\z80_|reg_file_|gdfx_temp0[3]~44_combout & \z80_|reg_file_|gdfx_temp0[3]~43_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[3]~45_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[3]~50_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[3]~44_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[3]~43_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~51 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[3]~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y13_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~52 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[3]~52_combout = ((\z80_|reg_file_|gdfx_temp0[3]~51_combout & ((\z80_|reg_file_|db_lo_as[3]~12_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[3]~12_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[3]~52 .lut_mask = 16'h8FCF; -defparam \z80_|reg_file_|gdfx_temp0[3]~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N13 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[3]~12_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N12 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~10 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[3]~10_combout = (\z80_|reg_file_|gdfx_temp0[3]~52_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) # (!\z80_|reg_file_|gdfx_temp0[3]~52_combout & -// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [3]), - .datad(\z80_|execute_|ctl_sw_4d~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[3]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[3]~10 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|db_lo_as[3]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y17_N3 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[3]~12_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[3] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N20 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~11 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[3]~11_combout = (\z80_|reg_file_|db_lo_as[3]~10_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(\z80_|reg_file_|db_lo_as[3]~10_combout ), - .datab(gnd), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [3]), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[3]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[3]~11 .lut_mask = 16'hAA0A; -defparam \z80_|reg_file_|db_lo_as[3]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N2 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~12 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[3]~12_combout = ((\z80_|reg_file_|db_lo_as[3]~11_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datad(\z80_|reg_file_|db_lo_as[3]~11_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[3]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[3]~12 .lut_mask = 16'hBF0F; -defparam \z80_|reg_file_|db_lo_as[3]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N2 -cycloneive_lcell_comb \z80_|address_latch_|abusz[3] ( -// Equation(s): -// \z80_|address_latch_|abusz [3] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[3]~12_combout ) - - .dataa(gnd), - .datab(\z80_|resets_|clrpc~0_combout ), - .datac(\z80_|reg_file_|db_lo_as[3]~12_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [3]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[3] .lut_mask = 16'h3030; -defparam \z80_|address_latch_|abusz[3] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y17_N17 -dffeas \z80_|address_latch_|Q[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|address_latch_|abusz [3]), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[3] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N20 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout = \z80_|address_latch_|Q [3] $ (((\z80_|execute_|ctl_inc_dec~10_combout ) # ((!\z80_|execute_|ctl_inc_dec~5_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) - - .dataa(\z80_|execute_|ctl_inc_dec~10_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .datac(\z80_|execute_|ctl_inc_dec~5_combout ), - .datad(\z80_|address_latch_|Q [3]), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4 .lut_mask = 16'h40BF; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N6 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout & -// (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout ))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ), - .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 .lut_mask = 16'h8000; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N12 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout = \z80_|address_latch_|Q [4] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout & -// (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout )))) - - .dataa(\z80_|address_latch_|Q [4]), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0_combout ), - .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out .lut_mask = 16'h6AAA; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y13_N27 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y13_N9 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~53 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~53_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [4] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [4] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [4]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~53_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~53 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[4]~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~54 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~54_combout = (\z80_|reg_file_|gdfx_temp0[4]~53_combout & ((\z80_|alu_control_|db[4]~32_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) - - .dataa(\z80_|alu_control_|db[4]~32_combout ), - .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[4]~53_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~54_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~54 .lut_mask = 16'hBB00; -defparam \z80_|reg_file_|gdfx_temp0[4]~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N27 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y10_N1 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~58 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~58_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~58_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~58 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[4]~58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y11_N31 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y11_N23 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y11_N21 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~59 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~59_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_bc_lo|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~59_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~59 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[4]~59 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~60 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~60_combout = (\z80_|reg_file_|gdfx_temp0[4]~58_combout & (\z80_|reg_file_|gdfx_temp0[4]~59_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[4]~58_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [4]), - .datad(\z80_|reg_file_|gdfx_temp0[4]~59_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~60_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~60 .lut_mask = 16'hA200; -defparam \z80_|reg_file_|gdfx_temp0[4]~60 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y9_N21 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y9_N11 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~57 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~57_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (\z80_|reg_file_|b2v_latch_hl2_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (((\z80_|reg_file_|b2v_latch_hl_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~57_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~57 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[4]~57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y10_N1 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y10_N7 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~55 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~55_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datac(\z80_|reg_file_|b2v_latch_iy_lo|latch [4]), - .datad(\z80_|reg_file_|b2v_latch_sp_lo|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~55_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~55 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[4]~55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y11_N21 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~56 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~56_combout = (\z80_|reg_file_|gdfx_temp0[4]~55_combout & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[4]~55_combout ), - .datab(gnd), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~56_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~56 .lut_mask = 16'hA0AA; -defparam \z80_|reg_file_|gdfx_temp0[4]~56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~61 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~61_combout = (\z80_|reg_file_|gdfx_temp0[4]~54_combout & (\z80_|reg_file_|gdfx_temp0[4]~60_combout & (\z80_|reg_file_|gdfx_temp0[4]~57_combout & \z80_|reg_file_|gdfx_temp0[4]~56_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[4]~54_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[4]~60_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[4]~57_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[4]~56_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~61 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[4]~61 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~62 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[4]~62_combout = ((\z80_|reg_file_|gdfx_temp0[4]~61_combout & ((\z80_|reg_file_|db_lo_as[4]~15_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .datac(\z80_|reg_file_|db_lo_as[4]~15_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[4]~62 .lut_mask = 16'hB3BB; -defparam \z80_|reg_file_|gdfx_temp0[4]~62 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N7 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[4]~15_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N6 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~13 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[4]~13_combout = (\z80_|reg_file_|gdfx_temp0[4]~62_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # (!\z80_|reg_file_|gdfx_temp0[4]~62_combout & -// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .datab(\z80_|execute_|ctl_sw_4d~6_combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [4]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[4]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[4]~13 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|db_lo_as[4]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y17_N7 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[4]~15_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[4] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N12 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~14 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[4]~14_combout = (\z80_|reg_file_|db_lo_as[4]~13_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|db_lo_as[4]~13_combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [4]), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[4]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[4]~14 .lut_mask = 16'hCC0C; -defparam \z80_|reg_file_|db_lo_as[4]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N6 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~15 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[4]~15_combout = ((\z80_|reg_file_|db_lo_as[4]~14_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datad(\z80_|reg_file_|db_lo_as[4]~14_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[4]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[4]~15 .lut_mask = 16'hBF0F; -defparam \z80_|reg_file_|db_lo_as[4]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N16 -cycloneive_lcell_comb \z80_|address_latch_|abusz[4] ( -// Equation(s): -// \z80_|address_latch_|abusz [4] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[4]~15_combout ) - - .dataa(gnd), - .datab(\z80_|resets_|clrpc~0_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|db_lo_as[4]~15_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [4]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[4] .lut_mask = 16'h3300; -defparam \z80_|address_latch_|abusz[4] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y17_N23 -dffeas \z80_|address_latch_|Q[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|address_latch_|abusz [4]), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[4] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N22 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout = \z80_|address_latch_|Q [4] $ (((\z80_|execute_|ctl_inc_dec~9_combout ) # ((\z80_|execute_|ctl_inc_dec~7_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout )))) - - .dataa(\z80_|execute_|ctl_inc_dec~9_combout ), - .datab(\z80_|execute_|ctl_inc_dec~6_combout ), - .datac(\z80_|address_latch_|Q [4]), - .datad(\z80_|execute_|ctl_inc_dec~7_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 .lut_mask = 16'h0F4B; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N28 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout = \z80_|address_latch_|Q [5] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout & \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout -// ))) - - .dataa(\z80_|address_latch_|Q [5]), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out .lut_mask = 16'h6A6A; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y9_N23 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y9_N13 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~64 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~64_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [5] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [5] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [5]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~64_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~64 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[5]~64 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y9_N21 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y9_N23 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~63 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~63_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (\z80_|reg_file_|b2v_latch_de2_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_de_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & ((\z80_|reg_file_|b2v_latch_de_lo|latch [5]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datab(\z80_|reg_file_|b2v_latch_de_lo|latch [5]), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~63_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~63 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[5]~63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y11_N9 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y11_N5 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~66 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~66_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [5] & ((\z80_|alu_control_|db[5]~15_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (((\z80_|alu_control_|db[5]~15_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [5]), - .datad(\z80_|alu_control_|db[5]~15_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~66_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~66 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[5]~66 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~67 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~67_combout = (\z80_|reg_file_|gdfx_temp0[5]~66_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [5]), - .datad(\z80_|reg_file_|gdfx_temp0[5]~66_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~67_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~67 .lut_mask = 16'hF300; -defparam \z80_|reg_file_|gdfx_temp0[5]~67 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N31 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y10_N17 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~65 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~65_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [5]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [5]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~65_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~65 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[5]~65 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y10_N31 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N28 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder_combout = \z80_|reg_file_|gdfx_temp0[5]~72_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y10_N29 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~69 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~69_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [5]), - .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [5]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~69_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~69 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[5]~69 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y11_N6 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder_combout = \z80_|reg_file_|gdfx_temp0[5]~72_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y11_N7 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y11_N3 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~68 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~68_combout = (\z80_|reg_file_|b2v_latch_ix_lo|latch [5] & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # (!\z80_|reg_file_|b2v_latch_ix_lo|latch [5] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_ix_lo|latch [5]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc_lo|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~68_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~68 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[5]~68 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N0 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~70 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~70_combout = (\z80_|reg_file_|gdfx_temp0[5]~67_combout & (\z80_|reg_file_|gdfx_temp0[5]~65_combout & (\z80_|reg_file_|gdfx_temp0[5]~69_combout & \z80_|reg_file_|gdfx_temp0[5]~68_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[5]~67_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[5]~65_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[5]~69_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[5]~68_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~70_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~70 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[5]~70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N30 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~71 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~71_combout = (\z80_|reg_file_|gdfx_temp0[5]~64_combout & (\z80_|reg_file_|gdfx_temp0[5]~63_combout & \z80_|reg_file_|gdfx_temp0[5]~70_combout )) - - .dataa(\z80_|reg_file_|gdfx_temp0[5]~64_combout ), - .datab(gnd), - .datac(\z80_|reg_file_|gdfx_temp0[5]~63_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[5]~70_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~71 .lut_mask = 16'hA000; -defparam \z80_|reg_file_|gdfx_temp0[5]~71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~72 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[5]~72_combout = ((\z80_|reg_file_|gdfx_temp0[5]~71_combout & ((\z80_|reg_file_|db_lo_as[5]~18_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .datab(\z80_|reg_file_|db_lo_as[5]~18_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), - .datad(\z80_|execute_|ctl_sw_4u~6_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[5]~72 .lut_mask = 16'hD5F5; -defparam \z80_|reg_file_|gdfx_temp0[5]~72 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N5 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[5]~18_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N4 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~16 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[5]~16_combout = (\z80_|reg_file_|gdfx_temp0[5]~72_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # (!\z80_|reg_file_|gdfx_temp0[5]~72_combout & -// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .datab(\z80_|execute_|ctl_sw_4d~6_combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [5]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[5]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[5]~16 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|db_lo_as[5]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y15_N25 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[5]~18_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[5] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N2 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~17 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[5]~17_combout = (\z80_|reg_file_|db_lo_as[5]~16_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datab(gnd), - .datac(\z80_|reg_file_|db_lo_as[5]~16_combout ), - .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [5]), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[5]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[5]~17 .lut_mask = 16'hF050; -defparam \z80_|reg_file_|db_lo_as[5]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N24 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~18 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[5]~18_combout = ((\z80_|reg_file_|db_lo_as[5]~17_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datad(\z80_|reg_file_|db_lo_as[5]~17_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[5]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[5]~18 .lut_mask = 16'hBF0F; -defparam \z80_|reg_file_|db_lo_as[5]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N26 -cycloneive_lcell_comb \z80_|address_latch_|abusz[5] ( -// Equation(s): -// \z80_|address_latch_|abusz [5] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[5]~18_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(\z80_|reg_file_|db_lo_as[5]~18_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [5]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[5] .lut_mask = 16'h0F00; -defparam \z80_|address_latch_|abusz[5] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y16_N27 -dffeas \z80_|address_latch_|Q[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [5]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[5] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y17_N26 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout = \z80_|address_latch_|Q [5] $ ((((\z80_|execute_|ctl_inc_dec~10_combout ) # (!\z80_|execute_|ctl_inc_dec~5_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout ))) - - .dataa(\z80_|address_latch_|Q [5]), - .datab(\z80_|execute_|ctl_bus_inc_oe~33_combout ), - .datac(\z80_|execute_|ctl_inc_dec~5_combout ), - .datad(\z80_|execute_|ctl_inc_dec~10_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4 .lut_mask = 16'h5595; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N16 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[6] ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|address [6] = \z80_|address_latch_|Q [6] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout & -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout )))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|address_latch_|Q [6]), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[6] .lut_mask = 16'h78F0; -defparam \z80_|address_latch_|b2v_inst_inc_dec|address[6] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y17_N11 -dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|db_lo_as[6]~21_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y9_N17 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N6 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder_combout = \z80_|reg_file_|gdfx_temp0[6]~82_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y9_N7 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~74 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~74_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (\z80_|reg_file_|b2v_latch_hl2_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (((\z80_|reg_file_|b2v_latch_hl_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~74_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~74 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[6]~74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y9_N19 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y9_N5 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~73 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~73_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (\z80_|reg_file_|b2v_latch_de2_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_de_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & ((\z80_|reg_file_|b2v_latch_de_lo|latch [6]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datab(\z80_|reg_file_|b2v_latch_de_lo|latch [6]), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~73_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~73 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[6]~73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y10_N19 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N2 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder_combout = \z80_|reg_file_|gdfx_temp0[6]~82_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y10_N3 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~78 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~78_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~78_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~78 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[6]~78 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N29 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~79 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~79_combout = (\z80_|reg_file_|b2v_latch_sp_lo|latch [6] & (((\z80_|alu_control_|db[6]~22_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) # (!\z80_|reg_file_|b2v_latch_sp_lo|latch [6] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|alu_control_|db[6]~22_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_sp_lo|latch [6]), - .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datac(\z80_|alu_control_|db[6]~22_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~79_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~79 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[6]~79 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y10_N17 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N16 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder_combout = \z80_|reg_file_|gdfx_temp0[6]~82_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y11_N17 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y11_N19 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N18 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~76 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~76_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [6]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [6]), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~76_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~76 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[6]~76 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N16 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~77 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~77_combout = (\z80_|reg_file_|gdfx_temp0[6]~76_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [6]), - .datad(\z80_|reg_file_|gdfx_temp0[6]~76_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~77_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~77 .lut_mask = 16'hF300; -defparam \z80_|reg_file_|gdfx_temp0[6]~77 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~80 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~80_combout = (\z80_|reg_file_|gdfx_temp0[6]~78_combout & (\z80_|reg_file_|gdfx_temp0[6]~79_combout & \z80_|reg_file_|gdfx_temp0[6]~77_combout )) - - .dataa(gnd), - .datab(\z80_|reg_file_|gdfx_temp0[6]~78_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[6]~79_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[6]~77_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~80 .lut_mask = 16'hC000; -defparam \z80_|reg_file_|gdfx_temp0[6]~80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N5 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y14_N25 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~75 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~75_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [6]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [6]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~75_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~75 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[6]~75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~81 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~81_combout = (\z80_|reg_file_|gdfx_temp0[6]~74_combout & (\z80_|reg_file_|gdfx_temp0[6]~73_combout & (\z80_|reg_file_|gdfx_temp0[6]~80_combout & \z80_|reg_file_|gdfx_temp0[6]~75_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[6]~74_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[6]~73_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[6]~75_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~81_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~81 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[6]~81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~82 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[6]~82_combout = ((\z80_|reg_file_|gdfx_temp0[6]~81_combout & ((\z80_|reg_file_|db_lo_as[6]~21_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|gdfx_temp0[6]~81_combout ), - .datab(\z80_|reg_file_|db_lo_as[6]~21_combout ), - .datac(\z80_|execute_|ctl_sw_4u~6_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[6]~82 .lut_mask = 16'h8AFF; -defparam \z80_|reg_file_|gdfx_temp0[6]~82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N19 -dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|db_lo_as[6]~21_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[6] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N18 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~19 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[6]~19_combout = (\z80_|reg_file_|gdfx_temp0[6]~82_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # (!\z80_|reg_file_|gdfx_temp0[6]~82_combout & -// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) - - .dataa(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .datab(\z80_|execute_|ctl_sw_4d~6_combout ), - .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [6]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[6]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[6]~19 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|db_lo_as[6]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N16 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~20 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[6]~20_combout = (\z80_|reg_file_|db_lo_as[6]~19_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), - .datac(\z80_|reg_file_|b2v_latch_ir_lo|latch [6]), - .datad(\z80_|reg_file_|db_lo_as[6]~19_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[6]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[6]~20 .lut_mask = 16'hF300; -defparam \z80_|reg_file_|db_lo_as[6]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N10 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~21 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[6]~21_combout = ((\z80_|reg_file_|db_lo_as[6]~20_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [6]) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), - .datac(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datad(\z80_|reg_file_|db_lo_as[6]~20_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[6]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[6]~21 .lut_mask = 16'hDF55; -defparam \z80_|reg_file_|db_lo_as[6]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N22 -cycloneive_lcell_comb \z80_|address_latch_|abusz[6] ( -// Equation(s): -// \z80_|address_latch_|abusz [6] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[6]~21_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|clrpc~0_combout ), - .datad(\z80_|reg_file_|db_lo_as[6]~21_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|abusz [6]), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|abusz[6] .lut_mask = 16'h0F00; -defparam \z80_|address_latch_|abusz[6] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y16_N23 -dffeas \z80_|address_latch_|Q[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_latch_|abusz [6]), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_al_we~12_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_latch_|Q [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_latch_|Q[6] .is_wysiwyg = "true"; -defparam \z80_|address_latch_|Q[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N6 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout = (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|address_latch_|Q [6] $ (((\z80_|execute_|ctl_inc_dec~10_combout ) # (\z80_|execute_|ctl_inc_dec~7_combout ))))) - - .dataa(\z80_|execute_|ctl_inc_dec~10_combout ), - .datab(\z80_|execute_|ctl_inc_dec~7_combout ), - .datac(\z80_|address_latch_|Q [6]), - .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 .lut_mask = 16'h001E; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N0 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout & -// (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout ))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), - .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 .lut_mask = 16'h8000; -defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N24 -cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out ( -// Equation(s): -// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout = \z80_|address_latch_|Q [7] $ (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ) - - .dataa(\z80_|address_latch_|Q [7]), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), - .cin(gnd), - .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out .lut_mask = 16'h55AA; -defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N24 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~24 ( -// Equation(s): -// \z80_|reg_file_|db_lo_as[7]~24_combout = ((\z80_|reg_file_|db_lo_as[7]~23_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~41_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[0]~2_combout ), - .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), - .datac(\z80_|reg_file_|db_lo_as[7]~23_combout ), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_as[7]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_as[7]~24 .lut_mask = 16'hF575; -defparam \z80_|reg_file_|db_lo_as[7]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y9_N25 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y9_N11 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~83 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~83_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & (\z80_|reg_file_|b2v_latch_de2_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_de_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout & ((\z80_|reg_file_|b2v_latch_de_lo|latch [7]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datab(\z80_|reg_file_|b2v_latch_de_lo|latch [7]), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~83_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~83 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[7]~83 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y9_N29 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y9_N19 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~84 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~84_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (\z80_|reg_file_|b2v_latch_hl2_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout & (((\z80_|reg_file_|b2v_latch_hl_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_hl_lo|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~84_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~84 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[7]~84 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y10_N11 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N12 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder_combout = \z80_|reg_file_|gdfx_temp0[7]~92_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y10_N13 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N10 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~88 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~88_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_iy_lo|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~88_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~88 .lut_mask = 16'hF351; -defparam \z80_|reg_file_|gdfx_temp0[7]~88 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y10_N21 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y11_N9 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y11_N7 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~86 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~86_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [7]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [7]), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [7]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~86_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~86 .lut_mask = 16'hC4F5; -defparam \z80_|reg_file_|gdfx_temp0[7]~86 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~87 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~87_combout = (\z80_|reg_file_|gdfx_temp0[7]~86_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [7]), - .datad(\z80_|reg_file_|gdfx_temp0[7]~86_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~87_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~87 .lut_mask = 16'hF300; -defparam \z80_|reg_file_|gdfx_temp0[7]~87 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N25 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y10_N19 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~85 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~85_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [7]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [7]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~85_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~85 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[7]~85 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y13_N15 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[7] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~89 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~89_combout = (\z80_|reg_file_|b2v_latch_sp_lo|latch [7] & (((\z80_|alu_control_|db[7]~18_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) # (!\z80_|reg_file_|b2v_latch_sp_lo|latch [7] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|alu_control_|db[7]~18_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_sp_lo|latch [7]), - .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datac(\z80_|alu_control_|db[7]~18_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~89_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~89 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[7]~89 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N6 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~90 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~90_combout = (\z80_|reg_file_|gdfx_temp0[7]~88_combout & (\z80_|reg_file_|gdfx_temp0[7]~87_combout & (\z80_|reg_file_|gdfx_temp0[7]~85_combout & \z80_|reg_file_|gdfx_temp0[7]~89_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[7]~88_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[7]~87_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[7]~85_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[7]~89_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~90 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[7]~90 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N28 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~91 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~91_combout = (\z80_|reg_file_|gdfx_temp0[7]~83_combout & (\z80_|reg_file_|gdfx_temp0[7]~84_combout & \z80_|reg_file_|gdfx_temp0[7]~90_combout )) - - .dataa(\z80_|reg_file_|gdfx_temp0[7]~83_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[7]~84_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~91 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|gdfx_temp0[7]~91 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N14 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~92 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[7]~92_combout = ((\z80_|reg_file_|gdfx_temp0[7]~91_combout & ((\z80_|reg_file_|db_lo_as[7]~24_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|reg_file_|db_lo_as[7]~24_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), - .datac(\z80_|execute_|ctl_sw_4u~6_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[7]~92 .lut_mask = 16'h8CFF; -defparam \z80_|reg_file_|gdfx_temp0[7]~92 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N6 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[7]~0 ( -// Equation(s): -// \z80_|reg_file_|db_lo_ds[7]~0_combout = (\z80_|reg_file_|gdfx_temp0[7]~92_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout & (\z80_|execute_|ctl_reg_out_lo~7_combout & !\z80_|execute_|ctl_reg_out_lo~5_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), - .datab(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[7]~92_combout ), - .datad(\z80_|execute_|ctl_reg_out_lo~5_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_ds[7]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_ds[7]~0 .lut_mask = 16'hF0F8; -defparam \z80_|reg_file_|db_lo_ds[7]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y10_N11 -dffeas \z80_|interrupts_|im2 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_im_we~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|interrupts_|im2~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|interrupts_|im2 .is_wysiwyg = "true"; -defparam \z80_|interrupts_|im2 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~12 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~12_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|interrupts_|im2~q & \z80_|interrupts_|DFFE_inst44~q )) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(gnd), - .datac(\z80_|interrupts_|im2~q ), - .datad(\z80_|interrupts_|DFFE_inst44~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~12 .lut_mask = 16'h5000; -defparam \z80_|execute_|ctl_mRead~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_sw_mask543_en~0 ( -// Equation(s): -// \z80_|execute_|ctl_sw_mask543_en~0_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (!\z80_|execute_|ctl_mRead~12_combout & \z80_|pla_decode_|Equal47~0_combout ))) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|execute_|ctl_mRead~12_combout ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_sw_mask543_en~0 .lut_mask = 16'h0400; -defparam \z80_|execute_|ctl_sw_mask543_en~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N12 -cycloneive_lcell_comb \z80_|alu_control_|db[7]~17 ( -// Equation(s): -// \z80_|alu_control_|db[7]~17_combout = (\z80_|reg_file_|db_lo_ds[7]~0_combout & (((!\z80_|execute_|ctl_sw_mask543_en~0_combout & \z80_|bus_control_|db[7]~7_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) - - .dataa(\z80_|reg_file_|db_lo_ds[7]~0_combout ), - .datab(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .datac(\z80_|execute_|ctl_sw_1d~7_combout ), - .datad(\z80_|bus_control_|db[7]~7_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[7]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[7]~17 .lut_mask = 16'h2A0A; -defparam \z80_|alu_control_|db[7]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N16 -cycloneive_lcell_comb \z80_|alu_control_|db[7]~16 ( -// Equation(s): -// \z80_|alu_control_|db[7]~16_combout = (\z80_|execute_|ctl_flags_oe~2_combout & (((\z80_|execute_|ctl_sw_2u~7_combout & !\z80_|alu_|db[7]~21_combout )) # (!\z80_|alu_flags_|DFFE_inst_latch_sf~q ))) # (!\z80_|execute_|ctl_flags_oe~2_combout & -// (\z80_|execute_|ctl_sw_2u~7_combout & (!\z80_|alu_|db[7]~21_combout ))) - - .dataa(\z80_|execute_|ctl_flags_oe~2_combout ), - .datab(\z80_|execute_|ctl_sw_2u~7_combout ), - .datac(\z80_|alu_|db[7]~21_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), - .cin(gnd), - .combout(\z80_|alu_control_|db[7]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[7]~16 .lut_mask = 16'h0CAE; -defparam \z80_|alu_control_|db[7]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N14 -cycloneive_lcell_comb \z80_|alu_control_|db[7]~18 ( -// Equation(s): -// \z80_|alu_control_|db[7]~18_combout = ((\z80_|alu_control_|db[7]~17_combout & (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & !\z80_|alu_control_|db[7]~16_combout ))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|alu_control_|db[7]~17_combout ), - .datab(\z80_|alu_control_|db[6]~11_combout ), - .datac(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .datad(\z80_|alu_control_|db[7]~16_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[7]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[7]~18 .lut_mask = 16'h33B3; -defparam \z80_|alu_control_|db[7]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N8 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_34 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout = (\z80_|execute_|ctl_flags_bus~combout & ((\z80_|alu_control_|db[7]~18_combout ) # ((\z80_|alu_|db_high[3]~8_combout & \z80_|execute_|ctl_flags_alu~15_combout )))) # (!\z80_|execute_|ctl_flags_bus~combout -// & (((\z80_|alu_|db_high[3]~8_combout & \z80_|execute_|ctl_flags_alu~15_combout )))) - - .dataa(\z80_|execute_|ctl_flags_bus~combout ), - .datab(\z80_|alu_control_|db[7]~18_combout ), - .datac(\z80_|alu_|db_high[3]~8_combout ), - .datad(\z80_|execute_|ctl_flags_alu~15_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_34 .lut_mask = 16'hF888; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y9_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_sz_we~8_combout = (((!\z80_|execute_|ctl_flags_sz_we~7_combout ) # (!\z80_|execute_|ctl_flags_sz_we~2_combout )) # (!\z80_|execute_|ctl_flags_sz_we~4_combout )) # (!\z80_|execute_|ctl_flags_sz_we~3_combout ) - - .dataa(\z80_|execute_|ctl_flags_sz_we~3_combout ), - .datab(\z80_|execute_|ctl_flags_sz_we~4_combout ), - .datac(\z80_|execute_|ctl_flags_sz_we~2_combout ), - .datad(\z80_|execute_|ctl_flags_sz_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_sz_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_sz_we~8 .lut_mask = 16'h7FFF; -defparam \z80_|execute_|ctl_flags_sz_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y9_N9 -dffeas \z80_|alu_flags_|DFFE_inst_latch_sf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_flags_sz_we~8_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_sf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_sf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N26 -cycloneive_lcell_comb \z80_|pla_decode_|Equal62~3 ( -// Equation(s): -// \z80_|pla_decode_|Equal62~3_combout = (\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [4] & (\z80_|ir_|opcode [3] & \z80_|execute_|ctl_state_alu~12_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|execute_|ctl_state_alu~12_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal62~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal62~3 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal62~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~5_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal62~3_combout ) # ((\z80_|execute_|ctl_mWrite~16_combout ) # (\z80_|pla_decode_|Equal11~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal62~3_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_mWrite~16_combout ), - .datad(\z80_|pla_decode_|Equal11~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~5 .lut_mask = 16'hCCC8; -defparam \z80_|execute_|ctl_flags_pf_we~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~6_combout = (\z80_|pla_decode_|Equal69~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|pla_decode_|Equal69~0_combout ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~6 .lut_mask = 16'h008C; -defparam \z80_|execute_|ctl_flags_pf_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~7_combout = (\z80_|execute_|ctl_flags_pf_we~6_combout ) # ((\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # ((\z80_|nM1_int~2_combout & \z80_|execute_|ctl_mRead~36_combout ))) - - .dataa(\z80_|nM1_int~2_combout ), - .datab(\z80_|execute_|ctl_mRead~36_combout ), - .datac(\z80_|execute_|ctl_flags_pf_we~6_combout ), - .datad(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~7 .lut_mask = 16'hFFF8; -defparam \z80_|execute_|ctl_flags_pf_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~8_combout = (((\z80_|execute_|ctl_flags_pf_we~5_combout ) # (\z80_|execute_|ctl_flags_pf_we~7_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~46_combout )) # (!\z80_|execute_|ctl_flags_pf_we~3_combout ) - - .dataa(\z80_|execute_|ctl_flags_pf_we~3_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~46_combout ), - .datac(\z80_|execute_|ctl_flags_pf_we~5_combout ), - .datad(\z80_|execute_|ctl_flags_pf_we~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~8 .lut_mask = 16'hFFF7; -defparam \z80_|execute_|ctl_flags_pf_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_pf_we~9_combout = ((\z80_|execute_|ctl_flags_pf_we~8_combout ) # ((!\z80_|execute_|ctl_pf_sel[0]~3_combout ) # (!\z80_|execute_|ctl_flags_pf_we~4_combout ))) # (!\z80_|execute_|ctl_flags_xy_we~11_combout ) - - .dataa(\z80_|execute_|ctl_flags_xy_we~11_combout ), - .datab(\z80_|execute_|ctl_flags_pf_we~8_combout ), - .datac(\z80_|execute_|ctl_flags_pf_we~4_combout ), - .datad(\z80_|execute_|ctl_pf_sel[0]~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_pf_we~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_pf_we~9 .lut_mask = 16'hDFFF; -defparam \z80_|execute_|ctl_flags_pf_we~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N10 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~0 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~0_combout = (\z80_|execute_|ctl_flags_pf_we~9_combout & (\z80_|execute_|ctl_flags_bus~combout & (\z80_|alu_control_|db[2]~29_combout ))) # (!\z80_|execute_|ctl_flags_pf_we~9_combout & -// (((\z80_|alu_flags_|DFFE_inst_latch_pf~q )))) - - .dataa(\z80_|execute_|ctl_flags_bus~combout ), - .datab(\z80_|alu_control_|db[2]~29_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), - .datad(\z80_|execute_|ctl_flags_pf_we~9_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~0 .lut_mask = 16'h88F0; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N22 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~4 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~4_combout = (\z80_|execute_|ctl_pf_sel[0]~2_combout & (((!\z80_|pla_decode_|Equal62~3_combout & !\z80_|execute_|ctl_alu_op_low~13_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal62~3_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_pf_sel[0]~2_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~13_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~4 .lut_mask = 16'h3070; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N28 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~5 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~5_combout = (\z80_|execute_|ctl_pf_sel[0]~3_combout & (!\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout $ -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout )))) # (!\z80_|execute_|ctl_pf_sel[0]~3_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout $ (((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ))))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), - .datab(\z80_|execute_|ctl_pf_sel[0]~3_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~5 .lut_mask = 16'h152A; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N26 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~6 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~6_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout & (((\z80_|execute_|ctl_flags_bus~5_combout & !\z80_|pla_decode_|Equal69~0_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|pla_decode_|Equal69~0_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~6 .lut_mask = 16'h3B00; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~6 .sum_lutc_input = "datac"; +defparam \z80_|decode_state_|in_halt~0 .lut_mask = 16'h0500; +defparam \z80_|decode_state_|in_halt~0 .sum_lutc_input = "datac"; // synopsys translate_on // Location: LCCOMB_X28_Y16_N24 -cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~0 ( +cycloneive_lcell_comb \z80_|decode_state_|in_halt~1 ( // Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~0_combout = (!\z80_|address_latch_|Q [14] & (!\z80_|address_latch_|Q [12] & (!\z80_|address_latch_|Q [15] & !\z80_|address_latch_|Q [13]))) +// \z80_|decode_state_|in_halt~1_combout = (\z80_|decode_state_|in_halt~0_combout ) # ((\z80_|pla_decode_|Equal77~1_combout & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & !\z80_|decode_state_|in_halt~q ))) - .dataa(\z80_|address_latch_|Q [14]), - .datab(\z80_|address_latch_|Q [12]), - .datac(\z80_|address_latch_|Q [15]), - .datad(\z80_|address_latch_|Q [13]), + .dataa(\z80_|pla_decode_|Equal77~1_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|decode_state_|in_halt~q ), + .datad(\z80_|decode_state_|in_halt~0_combout ), .cin(gnd), - .combout(\z80_|decode_state_|DFFE_instNonRep~0_combout ), + .combout(\z80_|decode_state_|in_halt~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep~0 .lut_mask = 16'h0001; -defparam \z80_|decode_state_|DFFE_instNonRep~0 .sum_lutc_input = "datac"; +defparam \z80_|decode_state_|in_halt~1 .lut_mask = 16'hFF08; +defparam \z80_|decode_state_|in_halt~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y17_N16 -cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~3 ( -// Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~3_combout = (!\z80_|address_latch_|Q [1] & (\z80_|address_latch_|Q [0] & (!\z80_|address_latch_|Q [3] & !\z80_|address_latch_|Q [2]))) - - .dataa(\z80_|address_latch_|Q [1]), - .datab(\z80_|address_latch_|Q [0]), - .datac(\z80_|address_latch_|Q [3]), - .datad(\z80_|address_latch_|Q [2]), - .cin(gnd), - .combout(\z80_|decode_state_|DFFE_instNonRep~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep~3 .lut_mask = 16'h0004; -defparam \z80_|decode_state_|DFFE_instNonRep~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N14 -cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~2 ( -// Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~2_combout = (!\z80_|address_latch_|Q [7] & (!\z80_|address_latch_|Q [6] & (!\z80_|address_latch_|Q [5] & !\z80_|address_latch_|Q [4]))) - - .dataa(\z80_|address_latch_|Q [7]), - .datab(\z80_|address_latch_|Q [6]), - .datac(\z80_|address_latch_|Q [5]), - .datad(\z80_|address_latch_|Q [4]), - .cin(gnd), - .combout(\z80_|decode_state_|DFFE_instNonRep~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep~2 .lut_mask = 16'h0001; -defparam \z80_|decode_state_|DFFE_instNonRep~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N8 -cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~1 ( -// Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~1_combout = (!\z80_|address_latch_|Q [10] & (!\z80_|address_latch_|Q [11] & (!\z80_|address_latch_|Q [9] & !\z80_|address_latch_|Q [8]))) - - .dataa(\z80_|address_latch_|Q [10]), - .datab(\z80_|address_latch_|Q [11]), - .datac(\z80_|address_latch_|Q [9]), - .datad(\z80_|address_latch_|Q [8]), - .cin(gnd), - .combout(\z80_|decode_state_|DFFE_instNonRep~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep~1 .lut_mask = 16'h0001; -defparam \z80_|decode_state_|DFFE_instNonRep~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N18 -cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~4 ( -// Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~4_combout = (\z80_|decode_state_|DFFE_instNonRep~0_combout & (\z80_|decode_state_|DFFE_instNonRep~3_combout & (\z80_|decode_state_|DFFE_instNonRep~2_combout & \z80_|decode_state_|DFFE_instNonRep~1_combout ))) - - .dataa(\z80_|decode_state_|DFFE_instNonRep~0_combout ), - .datab(\z80_|decode_state_|DFFE_instNonRep~3_combout ), - .datac(\z80_|decode_state_|DFFE_instNonRep~2_combout ), - .datad(\z80_|decode_state_|DFFE_instNonRep~1_combout ), - .cin(gnd), - .combout(\z80_|decode_state_|DFFE_instNonRep~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep~4 .lut_mask = 16'h8000; -defparam \z80_|decode_state_|DFFE_instNonRep~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N16 -cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~5 ( -// Equation(s): -// \z80_|decode_state_|DFFE_instNonRep~5_combout = (\z80_|execute_|ctl_flags_bus~5_combout & (((\z80_|decode_state_|DFFE_instNonRep~q )))) # (!\z80_|execute_|ctl_flags_bus~5_combout & ((\z80_|execute_|ixy_d~9_combout & -// ((\z80_|decode_state_|DFFE_instNonRep~4_combout ))) # (!\z80_|execute_|ixy_d~9_combout & (\z80_|decode_state_|DFFE_instNonRep~q )))) - - .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), - .datab(\z80_|execute_|ixy_d~9_combout ), - .datac(\z80_|decode_state_|DFFE_instNonRep~q ), - .datad(\z80_|decode_state_|DFFE_instNonRep~4_combout ), - .cin(gnd), - .combout(\z80_|decode_state_|DFFE_instNonRep~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep~5 .lut_mask = 16'hF4B0; -defparam \z80_|decode_state_|DFFE_instNonRep~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y16_N17 -dffeas \z80_|decode_state_|DFFE_instNonRep ( +// Location: FF_X28_Y16_N25 +dffeas \z80_|decode_state_|in_halt ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|decode_state_|DFFE_instNonRep~5_combout ), + .d(\z80_|decode_state_|in_halt~1_combout ), .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), @@ -33642,7153 +6250,203 @@ dffeas \z80_|decode_state_|DFFE_instNonRep ( .ena(vcc), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|decode_state_|DFFE_instNonRep~q ), + .q(\z80_|decode_state_|in_halt~q ), .prn(vcc)); // synopsys translate_off -defparam \z80_|decode_state_|DFFE_instNonRep .is_wysiwyg = "true"; -defparam \z80_|decode_state_|DFFE_instNonRep .power_up = "low"; +defparam \z80_|decode_state_|in_halt .is_wysiwyg = "true"; +defparam \z80_|decode_state_|in_halt .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y16_N12 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~1 ( +// Location: LCCOMB_X28_Y16_N8 +cycloneive_lcell_comb \z80_|pla_decode_|Equal50~0 ( // Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~1_combout = (!\z80_|pla_decode_|Equal62~3_combout & (\z80_|execute_|ctl_pf_sel[0]~3_combout & (\z80_|execute_|ctl_pf_sel[0]~2_combout & !\z80_|execute_|ctl_alu_op_low~13_combout ))) - - .dataa(\z80_|pla_decode_|Equal62~3_combout ), - .datab(\z80_|execute_|ctl_pf_sel[0]~3_combout ), - .datac(\z80_|execute_|ctl_pf_sel[0]~2_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~13_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~1 .lut_mask = 16'h0040; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N10 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~2 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~2_combout = (\z80_|pla_decode_|Equal69~0_combout & ((\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout & (\z80_|interrupts_|DFFE_instIFF2~q )) # (!\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout & -// ((!\z80_|decode_state_|DFFE_instNonRep~q ))))) - - .dataa(\z80_|interrupts_|DFFE_instIFF2~q ), - .datab(\z80_|decode_state_|DFFE_instNonRep~q ), - .datac(\z80_|pla_decode_|Equal69~0_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~2 .lut_mask = 16'hA030; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N24 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~3 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~3_combout = (\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_flags_bus~5_combout & (\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout )) # (!\z80_|execute_|ctl_flags_bus~5_combout & -// ((!\z80_|decode_state_|DFFE_instNonRep~q ))))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_flags_bus~5_combout ), - .datad(\z80_|decode_state_|DFFE_instNonRep~q ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~3 .lut_mask = 16'h808C; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y10_N23 -dffeas \z80_|alu_control_|DFFE_latch_pf_tmp ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|alu_parity_out~combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_alu_op_low~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_control_|DFFE_latch_pf_tmp~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_control_|DFFE_latch_pf_tmp .is_wysiwyg = "true"; -defparam \z80_|alu_control_|DFFE_latch_pf_tmp .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N16 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ) # -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout )))) # (!\z80_|execute_|ctl_alu_core_R~5_combout ) - - .dataa(\z80_|execute_|ctl_alu_core_R~5_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 .lut_mask = 16'h55FD; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y10_N22 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout = (\z80_|alu_|alu_op2[1]~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout & -// \z80_|alu_|alu_op1[1]~0_combout )))) # (!\z80_|alu_|alu_op2[1]~1_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_|alu_op1[1]~0_combout ) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout )))) - - .dataa(\z80_|alu_|alu_op2[1]~1_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), - .datac(\z80_|alu_|alu_op1[1]~0_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 .lut_mask = 16'hFB20; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N28 -cycloneive_lcell_comb \z80_|alu_|alu_parity_out~0 ( -// Equation(s): -// \z80_|alu_|alu_parity_out~0_combout = \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout $ (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout $ (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout )) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), - .datab(gnd), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_parity_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_parity_out~0 .lut_mask = 16'hA55A; -defparam \z80_|alu_|alu_parity_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N22 -cycloneive_lcell_comb \z80_|alu_|alu_parity_out ( -// Equation(s): -// \z80_|alu_|alu_parity_out~combout = \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout $ (\z80_|alu_|alu_parity_out~0_combout $ (((\z80_|execute_|ctl_alu_op_low~combout ) # (\z80_|alu_control_|DFFE_latch_pf_tmp~q )))) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~combout ), - .datac(\z80_|alu_control_|DFFE_latch_pf_tmp~q ), - .datad(\z80_|alu_|alu_parity_out~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|alu_parity_out~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_parity_out .lut_mask = 16'hA956; -defparam \z80_|alu_|alu_parity_out .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N20 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~7 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~7_combout = (\z80_|pla_decode_|Equal62~3_combout ) # ((\z80_|pla_decode_|Equal69~0_combout ) # ((\z80_|execute_|ctl_alu_op_low~13_combout ) # (!\z80_|execute_|ctl_flags_bus~5_combout ))) - - .dataa(\z80_|pla_decode_|Equal62~3_combout ), - .datab(\z80_|pla_decode_|Equal69~0_combout ), - .datac(\z80_|execute_|ctl_flags_bus~5_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~13_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~7 .lut_mask = 16'hFFEF; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N2 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~8 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~8_combout = (\z80_|execute_|ctl_pf_sel[0]~2_combout & (\z80_|execute_|ctl_pf_sel[0]~3_combout & ((!\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ) # (!\z80_|nM1_int~2_combout )))) - - .dataa(\z80_|execute_|ctl_pf_sel[0]~2_combout ), - .datab(\z80_|nM1_int~2_combout ), - .datac(\z80_|execute_|ctl_pf_sel[0]~3_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~8 .lut_mask = 16'h20A0; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y16_N4 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~9 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~9_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ) # ((\z80_|alu_|alu_parity_out~combout & \z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ), - .datac(\z80_|alu_|alu_parity_out~combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~9 .lut_mask = 16'hFEEE; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N14 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~10 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_pf~10_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ) # ((\z80_|execute_|ctl_flags_pf_we~9_combout & (\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout & \z80_|execute_|ctl_flags_alu~15_combout ))) - - .dataa(\z80_|execute_|ctl_flags_pf_we~9_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ), - .datad(\z80_|execute_|ctl_flags_alu~15_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~10 .lut_mask = 16'hECCC; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y11_N15 -dffeas \z80_|alu_flags_|DFFE_inst_latch_pf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|DFFE_inst_latch_pf~10_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_pf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_pf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N14 -cycloneive_lcell_comb \z80_|alu_control_|sel[1]~0 ( -// Equation(s): -// \z80_|alu_control_|sel[1]~0_combout = (\z80_|ir_|opcode [5] & (((!\z80_|pla_decode_|Equal40~0_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal6~0_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal40~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|sel[1]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|sel[1]~0 .lut_mask = 16'h70F0; -defparam \z80_|alu_control_|sel[1]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N18 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout = (!\z80_|alu_|db_high[1]~20_combout & (!\z80_|alu_|db_high[3]~8_combout & (!\z80_|alu_|db_high[2]~14_combout & !\z80_|alu_|db_high[0]~26_combout ))) - - .dataa(\z80_|alu_|db_high[1]~20_combout ), - .datab(\z80_|alu_|db_high[3]~8_combout ), - .datac(\z80_|alu_|db_high[2]~14_combout ), - .datad(\z80_|alu_|db_high[0]~26_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2 .lut_mask = 16'h0001; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N4 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_12 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout = (\z80_|alu_control_|db[6]~22_combout & \z80_|execute_|ctl_flags_bus~combout ) - - .dataa(\z80_|alu_control_|db[6]~22_combout ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|execute_|ctl_flags_bus~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_12 .lut_mask = 16'hAA00; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N14 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout = (!\z80_|alu_|db_low[3]~11_combout & (\z80_|alu_|db_high[3]~3_combout & ((!\z80_|alu_|db_low[2]~3_combout ) # (!\z80_|alu_|db_low[2]~6_combout )))) - - .dataa(\z80_|alu_|db_low[2]~6_combout ), - .datab(\z80_|alu_|db_low[3]~11_combout ), - .datac(\z80_|alu_|db_low[2]~3_combout ), - .datad(\z80_|alu_|db_high[3]~3_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 .lut_mask = 16'h1300; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N8 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout = (!\z80_|alu_|db_low[1]~17_combout & (\z80_|execute_|ctl_flags_alu~15_combout & (!\z80_|alu_|db_low[0]~23_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ))) - - .dataa(\z80_|alu_|db_low[1]~17_combout ), - .datab(\z80_|execute_|ctl_flags_alu~15_combout ), - .datac(\z80_|alu_|db_low[0]~23_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 .lut_mask = 16'h0400; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N2 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout = (((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ) # (!\z80_|execute_|ixy_d~7_combout )) # (!\z80_|pla_decode_|Equal13~0_combout )) # (!\z80_|pla_decode_|Equal55~0_combout ) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .datad(\z80_|execute_|ixy_d~7_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 .lut_mask = 16'hF7FF; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y13_N26 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout & ((\z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout )))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 .lut_mask = 16'hEC00; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y13_N27 -dffeas \z80_|alu_flags_|SYNTHESIZED_WIRE_39 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_flags_sz_we~8_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_39 .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_39 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N28 -cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_cond_mux|out~0 ( -// Equation(s): -// \z80_|alu_control_|b2v_inst_cond_mux|out~0_combout = (\z80_|alu_control_|sel[1]~0_combout & (((\z80_|ir_|opcode [4])))) # (!\z80_|alu_control_|sel[1]~0_combout & ((\z80_|ir_|opcode [4] & ((\z80_|alu_flags_|flags_cf~combout ))) # (!\z80_|ir_|opcode [4] -// & (\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q )))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .datab(\z80_|alu_flags_|flags_cf~combout ), - .datac(\z80_|alu_control_|sel[1]~0_combout ), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|b2v_inst_cond_mux|out~0 .lut_mask = 16'hFC0A; -defparam \z80_|alu_control_|b2v_inst_cond_mux|out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N18 -cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_cond_mux|out~1 ( -// Equation(s): -// \z80_|alu_control_|b2v_inst_cond_mux|out~1_combout = (\z80_|alu_control_|sel[1]~0_combout & ((\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout & (\z80_|alu_flags_|DFFE_inst_latch_sf~q )) # (!\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout & -// ((\z80_|alu_flags_|DFFE_inst_latch_pf~q ))))) # (!\z80_|alu_control_|sel[1]~0_combout & (((\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout )))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), - .datac(\z80_|alu_control_|sel[1]~0_combout ), - .datad(\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|b2v_inst_cond_mux|out~1 .lut_mask = 16'hAFC0; -defparam \z80_|alu_control_|b2v_inst_cond_mux|out~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N20 -cycloneive_lcell_comb \z80_|alu_control_|flags_cond_true~0 ( -// Equation(s): -// \z80_|alu_control_|flags_cond_true~0_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|ir_|opcode [3] $ (((!\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ))))) # (!\z80_|execute_|ctl_eval_cond~0_combout & -// (((\z80_|alu_control_|flags_cond_true~q )))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|alu_control_|flags_cond_true~q ), - .datad(\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|flags_cond_true~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|flags_cond_true~0 .lut_mask = 16'hB874; -defparam \z80_|alu_control_|flags_cond_true~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y11_N21 -dffeas \z80_|alu_control_|flags_cond_true ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_control_|flags_cond_true~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_control_|flags_cond_true~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_control_|flags_cond_true .is_wysiwyg = "true"; -defparam \z80_|alu_control_|flags_cond_true .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~13 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~13_combout = (((!\z80_|pla_decode_|Equal35~0_combout & !\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|execute_|ixy_d~6_combout )) # (!\z80_|alu_control_|flags_cond_true~q ) - - .dataa(\z80_|pla_decode_|Equal35~0_combout ), - .datab(\z80_|alu_control_|flags_cond_true~q ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|pla_decode_|Equal34~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~13 .lut_mask = 16'h3F7F; -defparam \z80_|execute_|ctl_reg_sel_wz~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~14 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~14_combout = (((\z80_|execute_|ctl_66_oe~2_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~13_combout )) # (!\z80_|execute_|ctl_reg_in_hi~5_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~12_combout ) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~12_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~5_combout ), - .datac(\z80_|execute_|ctl_66_oe~2_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~13_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~14 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|ctl_reg_sel_wz~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y14_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~17 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sel_wz~17_combout = (\z80_|execute_|ctl_reg_sel_wz~14_combout ) # (((!\z80_|execute_|ctl_reg_sel_wz~16_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~19_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~11_combout )) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~14_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~11_combout ), - .datac(\z80_|execute_|ctl_reg_sel_wz~19_combout ), - .datad(\z80_|execute_|ctl_reg_sel_wz~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sel_wz~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sel_wz~17 .lut_mask = 16'hBFFF; -defparam \z80_|execute_|ctl_reg_sel_wz~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y15_N16 -cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_82 ( -// Equation(s): -// \z80_|reg_file_|SYNTHESIZED_WIRE_82~combout = (\z80_|execute_|ctl_reg_sel_wz~17_combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout & !\z80_|reg_control_|reg_sys_we_lo~combout )) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~17_combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~29_combout ), - .datac(gnd), - .datad(\z80_|reg_control_|reg_sys_we_lo~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_82 .lut_mask = 16'h0088; -defparam \z80_|reg_file_|SYNTHESIZED_WIRE_82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y10_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~18 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~18_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~18 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp0[0]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y12_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~20 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~20_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ) # ((\z80_|reg_file_|gdfx_temp0[0]~19_combout ) # ((\z80_|reg_file_|gdfx_temp0[0]~18_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~19_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[0]~18_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~20 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp0[0]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N20 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~21 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[0]~21_combout = (\z80_|reg_file_|gdfx_temp0[0]~93_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ) # ((\z80_|reg_file_|gdfx_temp0[0]~20_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[0]~93_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .datac(\z80_|reg_file_|gdfx_temp0[0]~20_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[0]~21 .lut_mask = 16'hFFFE; -defparam \z80_|reg_file_|gdfx_temp0[0]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y10_N23 -dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X31_Y10_N27 -dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N26 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~28 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~28_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), - .datab(\z80_|reg_file_|b2v_latch_iy_lo|latch [1]), - .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~28 .lut_mask = 16'hD0DD; -defparam \z80_|reg_file_|gdfx_temp0[1]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y10_N25 -dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y11_N13 -dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y12_N25 -dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y11_N12 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~26 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~26_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), - .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [1]), - .datad(\z80_|reg_file_|b2v_latch_bc_lo|latch [1]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~26 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[1]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~27 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~27_combout = (\z80_|reg_file_|gdfx_temp0[1]~26_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) +// \z80_|pla_decode_|Equal50~0_combout = (!\z80_|decode_state_|in_halt~q & (\z80_|pla_decode_|Equal33~1_combout & \z80_|pla_decode_|Equal77~0_combout )) .dataa(gnd), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), - .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [1]), - .datad(\z80_|reg_file_|gdfx_temp0[1]~26_combout ), + .datab(\z80_|decode_state_|in_halt~q ), + .datac(\z80_|pla_decode_|Equal33~1_combout ), + .datad(\z80_|pla_decode_|Equal77~0_combout ), .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~27_combout ), + .combout(\z80_|pla_decode_|Equal50~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~27 .lut_mask = 16'hF300; -defparam \z80_|reg_file_|gdfx_temp0[1]~27 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal50~0 .lut_mask = 16'h3000; +defparam \z80_|pla_decode_|Equal50~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y10_N17 -dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N4 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~29 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~29_combout = (\z80_|reg_file_|b2v_latch_sp_lo|latch [1] & (((\z80_|alu_control_|db[1]~26_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) # (!\z80_|reg_file_|b2v_latch_sp_lo|latch [1] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|alu_control_|db[1]~26_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_sp_lo|latch [1]), - .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), - .datac(\z80_|alu_control_|db[1]~26_combout ), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~29 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[1]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N3 -dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N8 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout = \z80_|reg_file_|gdfx_temp0[1]~32_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y10_N9 -dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_af_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y10_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~25 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~25_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - - .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), - .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [1]), - .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [1]), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~25 .lut_mask = 16'hF531; -defparam \z80_|reg_file_|gdfx_temp0[1]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y10_N2 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~30 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~30_combout = (\z80_|reg_file_|gdfx_temp0[1]~28_combout & (\z80_|reg_file_|gdfx_temp0[1]~27_combout & (\z80_|reg_file_|gdfx_temp0[1]~29_combout & \z80_|reg_file_|gdfx_temp0[1]~25_combout ))) - - .dataa(\z80_|reg_file_|gdfx_temp0[1]~28_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[1]~27_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[1]~29_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[1]~25_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~30 .lut_mask = 16'h8000; -defparam \z80_|reg_file_|gdfx_temp0[1]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N26 -cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder ( -// Equation(s): -// \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder_combout = \z80_|reg_file_|gdfx_temp0[1]~32_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder .lut_mask = 16'hFF00; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y9_N27 -dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y9_N25 -dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y9_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~24 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~24_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [1] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [1] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [1]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), - .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~24 .lut_mask = 16'hB0BB; -defparam \z80_|reg_file_|gdfx_temp0[1]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y13_N23 -dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y13_N25 -dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[1] .is_wysiwyg = "true"; -defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N24 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~23 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~23_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [1] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [1] & -// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) - - .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [1]), - .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), - .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [1]), - .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~23 .lut_mask = 16'hA2F3; -defparam \z80_|reg_file_|gdfx_temp0[1]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y13_N22 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~31 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~31_combout = (\z80_|reg_file_|gdfx_temp0[1]~30_combout & (\z80_|reg_file_|gdfx_temp0[1]~24_combout & \z80_|reg_file_|gdfx_temp0[1]~23_combout )) - - .dataa(\z80_|reg_file_|gdfx_temp0[1]~30_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[1]~24_combout ), - .datac(gnd), - .datad(\z80_|reg_file_|gdfx_temp0[1]~23_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~31 .lut_mask = 16'h8800; -defparam \z80_|reg_file_|gdfx_temp0[1]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y13_N8 -cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~32 ( -// Equation(s): -// \z80_|reg_file_|gdfx_temp0[1]~32_combout = ((\z80_|reg_file_|gdfx_temp0[1]~31_combout & ((\z80_|reg_file_|db_lo_as[1]~6_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) - - .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), - .datac(\z80_|reg_file_|db_lo_as[1]~6_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[1]~31_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|gdfx_temp0[1]~32 .lut_mask = 16'hF733; -defparam \z80_|reg_file_|gdfx_temp0[1]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N12 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[1]~1 ( -// Equation(s): -// \z80_|reg_file_|db_lo_ds[1]~1_combout = (\z80_|reg_file_|gdfx_temp0[1]~32_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout & (\z80_|execute_|ctl_reg_out_lo~7_combout & !\z80_|execute_|ctl_reg_out_lo~5_combout ))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), - .datab(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), - .datad(\z80_|execute_|ctl_reg_out_lo~5_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_ds[1]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_ds[1]~1 .lut_mask = 16'hF0F8; -defparam \z80_|reg_file_|db_lo_ds[1]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N30 -cycloneive_lcell_comb \z80_|alu_control_|db[1]~25 ( -// Equation(s): -// \z80_|alu_control_|db[1]~25_combout = (\z80_|reg_file_|db_lo_ds[1]~1_combout & (((\z80_|bus_control_|db[1]~11_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) - - .dataa(\z80_|bus_control_|db[1]~11_combout ), - .datab(\z80_|reg_file_|db_lo_ds[1]~1_combout ), - .datac(\z80_|execute_|ctl_sw_1d~7_combout ), - .datad(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[1]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[1]~25 .lut_mask = 16'h0C8C; -defparam \z80_|alu_control_|db[1]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N28 -cycloneive_lcell_comb \z80_|alu_control_|db[1]~24 ( -// Equation(s): -// \z80_|alu_control_|db[1]~24_combout = (\z80_|execute_|ctl_flags_oe~2_combout & (((\z80_|execute_|ctl_sw_2u~7_combout & !\z80_|alu_|db[1]~13_combout )) # (!\z80_|alu_flags_|DFFE_inst_latch_nf~q ))) # (!\z80_|execute_|ctl_flags_oe~2_combout & -// (\z80_|execute_|ctl_sw_2u~7_combout & ((!\z80_|alu_|db[1]~13_combout )))) - - .dataa(\z80_|execute_|ctl_flags_oe~2_combout ), - .datab(\z80_|execute_|ctl_sw_2u~7_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .datad(\z80_|alu_|db[1]~13_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[1]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[1]~24 .lut_mask = 16'h0ACE; -defparam \z80_|alu_control_|db[1]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N20 -cycloneive_lcell_comb \z80_|alu_control_|db[1]~26 ( -// Equation(s): -// \z80_|alu_control_|db[1]~26_combout = ((\z80_|alu_control_|db[1]~25_combout & (\z80_|alu_control_|db[2]~23_combout & !\z80_|alu_control_|db[1]~24_combout ))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|alu_control_|db[1]~25_combout ), - .datab(\z80_|alu_control_|db[2]~23_combout ), - .datac(\z80_|alu_control_|db[6]~11_combout ), - .datad(\z80_|alu_control_|db[1]~24_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[1]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[1]~26 .lut_mask = 16'h0F8F; -defparam \z80_|alu_control_|db[1]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N22 -cycloneive_lcell_comb \z80_|alu_|db[1]~12 ( -// Equation(s): -// \z80_|alu_|db[1]~12_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[1]~21_combout & ((\z80_|alu_control_|db[1]~26_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & -// ((\z80_|alu_control_|db[1]~26_combout ) # ((!\z80_|execute_|ctl_sw_2d~13_combout )))) - - .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datab(\z80_|alu_control_|db[1]~26_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), - .datad(\z80_|execute_|ctl_sw_2d~13_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[1]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[1]~12 .lut_mask = 16'hC4F5; -defparam \z80_|alu_|db[1]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N8 -cycloneive_lcell_comb \z80_|alu_|db[1]~13 ( -// Equation(s): -// \z80_|alu_|db[1]~13_combout = ((\z80_|alu_|db[1]~12_combout & ((\z80_|alu_|db_low[1]~17_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~26_combout ) - - .dataa(\z80_|alu_|db[1]~12_combout ), - .datab(\z80_|execute_|ctl_alu_oe~14_combout ), - .datac(\z80_|alu_|db_low[1]~17_combout ), - .datad(\z80_|alu_|db[7]~26_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[1]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[1]~13 .lut_mask = 16'hA2FF; -defparam \z80_|alu_|db[1]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N18 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~21 ( -// Equation(s): -// \z80_|alu_|db_low[0]~21_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[1]~13_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(gnd), - .datac(\z80_|alu_|db[1]~13_combout ), - .datad(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~21 .lut_mask = 16'hF5A0; -defparam \z80_|alu_|db_low[0]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N0 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~22 ( -// Equation(s): -// \z80_|alu_|db_low[0]~22_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_low[0]~21_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[0]~19_combout ))) - - .dataa(gnd), - .datab(\z80_|alu_|db_low[0]~21_combout ), - .datac(\z80_|alu_|db[0]~19_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~22 .lut_mask = 16'hCCF0; -defparam \z80_|alu_|db_low[0]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N16 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~18 ( -// Equation(s): -// \z80_|alu_|db_low[0]~18_combout = ((!\z80_|bus_control_|db[4]~19_combout & (!\z80_|bus_control_|db[5]~15_combout & !\z80_|bus_control_|db[3]~21_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datab(\z80_|bus_control_|db[4]~19_combout ), - .datac(\z80_|bus_control_|db[5]~15_combout ), - .datad(\z80_|bus_control_|db[3]~21_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~18 .lut_mask = 16'h5557; -defparam \z80_|alu_|db_low[0]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N20 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~19 ( -// Equation(s): -// \z80_|alu_|db_low[0]~19_combout = (\z80_|alu_|op2_low [0] & (((\z80_|alu_|op1_low [0])) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout ))) # (!\z80_|alu_|op2_low [0] & (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_low [0]) # -// (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) - - .dataa(\z80_|alu_|op2_low [0]), - .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datac(\z80_|alu_|op1_low [0]), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~19 .lut_mask = 16'hA2F3; -defparam \z80_|alu_|db_low[0]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y10_N25 -dffeas \z80_|alu_|result_lo[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_alu_op_low~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|result_lo [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|result_lo[0] .is_wysiwyg = "true"; -defparam \z80_|alu_|result_lo[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N24 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~20 ( -// Equation(s): -// \z80_|alu_|db_low[0]~20_combout = (\z80_|alu_|db_low[0]~18_combout & (\z80_|alu_|db_low[0]~19_combout & ((\z80_|alu_|result_lo [0]) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) - - .dataa(\z80_|alu_|db_low[0]~18_combout ), - .datab(\z80_|alu_|db_low[0]~19_combout ), - .datac(\z80_|alu_|result_lo [0]), - .datad(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~20 .lut_mask = 16'h8880; -defparam \z80_|alu_|db_low[0]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N22 -cycloneive_lcell_comb \z80_|alu_|db_low[0]~23 ( -// Equation(s): -// \z80_|alu_|db_low[0]~23_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout & (\z80_|alu_|db_low[0]~22_combout & ((\z80_|alu_|db_low[0]~20_combout )))) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout & (((\z80_|alu_|db_low[0]~20_combout ) # -// (!\z80_|alu_|db_high[3]~2_combout )))) - - .dataa(\z80_|alu_|db_low[0]~22_combout ), - .datab(\z80_|alu_|db_high[3]~2_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datad(\z80_|alu_|db_low[0]~20_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[0]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[0]~23 .lut_mask = 16'hAF03; -defparam \z80_|alu_|db_low[0]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N10 -cycloneive_lcell_comb \z80_|alu_|db[0]~18 ( -// Equation(s): -// \z80_|alu_|db[0]~18_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[0]~30_combout & ((\z80_|alu_|db_low[0]~23_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & -// ((\z80_|alu_|db_low[0]~23_combout ) # ((!\z80_|execute_|ctl_alu_oe~14_combout )))) - - .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datab(\z80_|alu_|db_low[0]~23_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), - .datad(\z80_|execute_|ctl_alu_oe~14_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[0]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[0]~18 .lut_mask = 16'hC4F5; -defparam \z80_|alu_|db[0]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N16 -cycloneive_lcell_comb \z80_|alu_|db[0]~19 ( -// Equation(s): -// \z80_|alu_|db[0]~19_combout = ((\z80_|alu_|db[0]~18_combout & ((\z80_|alu_control_|db[0]~12_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|alu_|db[7]~26_combout ) - - .dataa(\z80_|alu_|db[0]~18_combout ), - .datab(\z80_|execute_|ctl_sw_2d~13_combout ), - .datac(\z80_|alu_control_|db[0]~12_combout ), - .datad(\z80_|alu_|db[7]~26_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[0]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[0]~19 .lut_mask = 16'hA2FF; -defparam \z80_|alu_|db[0]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N30 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~15 ( -// Equation(s): -// \z80_|alu_|db_low[1]~15_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[2]~15_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[0]~19_combout )) - - .dataa(\z80_|alu_|db[0]~19_combout ), - .datab(gnd), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|alu_|db[2]~15_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~15 .lut_mask = 16'hFA0A; -defparam \z80_|alu_|db_low[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N16 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~16 ( -// Equation(s): -// \z80_|alu_|db_low[1]~16_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_low[1]~15_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[1]~13_combout ))) - - .dataa(\z80_|alu_|db_low[1]~15_combout ), - .datab(gnd), - .datac(\z80_|alu_|db[1]~13_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~16 .lut_mask = 16'hAAF0; -defparam \z80_|alu_|db_low[1]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N6 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~12 ( -// Equation(s): -// \z80_|alu_|db_low[1]~12_combout = ((!\z80_|bus_control_|db[4]~19_combout & (!\z80_|bus_control_|db[5]~15_combout & \z80_|bus_control_|db[3]~21_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datab(\z80_|bus_control_|db[4]~19_combout ), - .datac(\z80_|bus_control_|db[5]~15_combout ), - .datad(\z80_|bus_control_|db[3]~21_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~12 .lut_mask = 16'h5755; -defparam \z80_|alu_|db_low[1]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N18 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~13 ( -// Equation(s): -// \z80_|alu_|db_low[1]~13_combout = (\z80_|alu_|op2_low [1] & (((\z80_|alu_|op1_low [1])) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout ))) # (!\z80_|alu_|op2_low [1] & (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_low [1]) # -// (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) - - .dataa(\z80_|alu_|op2_low [1]), - .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datac(\z80_|alu_|op1_low [1]), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~13 .lut_mask = 16'hA2F3; -defparam \z80_|alu_|db_low[1]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y10_N21 -dffeas \z80_|alu_|result_lo[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_alu_op_low~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|result_lo [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|result_lo[1] .is_wysiwyg = "true"; -defparam \z80_|alu_|result_lo[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N20 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~14 ( -// Equation(s): -// \z80_|alu_|db_low[1]~14_combout = (\z80_|alu_|db_low[1]~12_combout & (\z80_|alu_|db_low[1]~13_combout & ((\z80_|alu_|result_lo [1]) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) - - .dataa(\z80_|alu_|db_low[1]~12_combout ), - .datab(\z80_|alu_|db_low[1]~13_combout ), - .datac(\z80_|alu_|result_lo [1]), - .datad(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~14 .lut_mask = 16'h8880; -defparam \z80_|alu_|db_low[1]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N18 -cycloneive_lcell_comb \z80_|alu_|db_low[1]~17 ( -// Equation(s): -// \z80_|alu_|db_low[1]~17_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout & (((\z80_|alu_|db_low[1]~16_combout & \z80_|alu_|db_low[1]~14_combout )))) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout & (((\z80_|alu_|db_low[1]~14_combout )) # -// (!\z80_|alu_|db_high[3]~2_combout ))) - - .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datab(\z80_|alu_|db_high[3]~2_combout ), - .datac(\z80_|alu_|db_low[1]~16_combout ), - .datad(\z80_|alu_|db_low[1]~14_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[1]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[1]~17 .lut_mask = 16'hF511; -defparam \z80_|alu_|db_low[1]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N26 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout = (\z80_|alu_|db_low[1]~17_combout & ((\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ) # ((\z80_|alu_|db_high[1]~20_combout & \z80_|execute_|ctl_alu_op1_sel_low~combout )))) # -// (!\z80_|alu_|db_low[1]~17_combout & (((\z80_|alu_|db_high[1]~20_combout & \z80_|execute_|ctl_alu_op1_sel_low~combout )))) - - .dataa(\z80_|alu_|db_low[1]~17_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .datac(\z80_|alu_|db_high[1]~20_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 .lut_mask = 16'hF888; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N0 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6_combout = (\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout & !\z80_|execute_|ctl_alu_op1_sel_zero~combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6 .lut_mask = 16'h00F0; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y10_N1 -dffeas \z80_|alu_|op1_low[1] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_low [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_low[1] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_low[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N28 -cycloneive_lcell_comb \z80_|alu_control_|out[6]~0 ( -// Equation(s): -// \z80_|alu_control_|out[6]~0_combout = (\z80_|alu_|op1_low [3] & ((\z80_|alu_|op1_low [1]) # (\z80_|alu_|op1_low [2]))) - - .dataa(gnd), - .datab(\z80_|alu_|op1_low [1]), - .datac(\z80_|alu_|op1_low [3]), - .datad(\z80_|alu_|op1_low [2]), - .cin(gnd), - .combout(\z80_|alu_control_|out[6]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|out[6]~0 .lut_mask = 16'hF0C0; -defparam \z80_|alu_control_|out[6]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N18 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~2 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf~2_combout = (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & \z80_|execute_|ctl_flags_alu~15_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), - .datad(\z80_|execute_|ctl_flags_alu~15_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~2 .lut_mask = 16'h0F00; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N8 -cycloneive_lcell_comb \z80_|alu_flags_|flags_hf2~0 ( -// Equation(s): -// \z80_|alu_flags_|flags_hf2~0_combout = (\z80_|execute_|ctl_flags_hf2_we~combout & ((\z80_|alu_control_|db[4]~32_combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout )))) # (!\z80_|execute_|ctl_flags_hf2_we~combout & -// (((\z80_|alu_flags_|flags_hf2~q )))) - - .dataa(\z80_|alu_control_|db[4]~32_combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ), - .datac(\z80_|alu_flags_|flags_hf2~q ), - .datad(\z80_|execute_|ctl_flags_hf2_we~combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|flags_hf2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_hf2~0 .lut_mask = 16'hEEF0; -defparam \z80_|alu_flags_|flags_hf2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y11_N9 -dffeas \z80_|alu_flags_|flags_hf2 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|flags_hf2~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|flags_hf2~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_hf2 .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|flags_hf2 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N12 -cycloneive_lcell_comb \z80_|alu_control_|db[2]~23 ( -// Equation(s): -// \z80_|alu_control_|db[2]~23_combout = (\z80_|execute_|ctl_66_oe~combout ) # ((\z80_|alu_control_|out[6]~0_combout ) # ((\z80_|alu_flags_|flags_hf2~q ) # (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout ))) - - .dataa(\z80_|execute_|ctl_66_oe~combout ), - .datab(\z80_|alu_control_|out[6]~0_combout ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datad(\z80_|alu_flags_|flags_hf2~q ), - .cin(gnd), - .combout(\z80_|alu_control_|db[2]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[2]~23 .lut_mask = 16'hFFEF; -defparam \z80_|alu_control_|db[2]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y9_N26 -cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[2]~2 ( -// Equation(s): -// \z80_|reg_file_|db_lo_ds[2]~2_combout = (\z80_|reg_file_|gdfx_temp0[2]~42_combout ) # ((!\z80_|execute_|ctl_reg_out_lo~5_combout & (\z80_|execute_|ctl_reg_out_lo~7_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ))) - - .dataa(\z80_|execute_|ctl_reg_out_lo~5_combout ), - .datab(\z80_|execute_|ctl_reg_out_lo~7_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), - .datad(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), - .cin(gnd), - .combout(\z80_|reg_file_|db_lo_ds[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|reg_file_|db_lo_ds[2]~2 .lut_mask = 16'hFF40; -defparam \z80_|reg_file_|db_lo_ds[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N16 -cycloneive_lcell_comb \z80_|alu_control_|db[2]~28 ( -// Equation(s): -// \z80_|alu_control_|db[2]~28_combout = (\z80_|reg_file_|db_lo_ds[2]~2_combout & (((\z80_|bus_control_|db[2]~13_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) - - .dataa(\z80_|bus_control_|db[2]~13_combout ), - .datab(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .datac(\z80_|execute_|ctl_sw_1d~7_combout ), - .datad(\z80_|reg_file_|db_lo_ds[2]~2_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[2]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[2]~28 .lut_mask = 16'h2F00; -defparam \z80_|alu_control_|db[2]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y11_N28 -cycloneive_lcell_comb \z80_|alu_control_|db[2]~27 ( -// Equation(s): -// \z80_|alu_control_|db[2]~27_combout = (\z80_|execute_|ctl_flags_oe~2_combout & (((!\z80_|alu_|db[2]~15_combout & \z80_|execute_|ctl_sw_2u~7_combout )) # (!\z80_|alu_flags_|DFFE_inst_latch_pf~q ))) # (!\z80_|execute_|ctl_flags_oe~2_combout & -// (!\z80_|alu_|db[2]~15_combout & ((\z80_|execute_|ctl_sw_2u~7_combout )))) - - .dataa(\z80_|execute_|ctl_flags_oe~2_combout ), - .datab(\z80_|alu_|db[2]~15_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), - .datad(\z80_|execute_|ctl_sw_2u~7_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[2]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[2]~27 .lut_mask = 16'h3B0A; -defparam \z80_|alu_control_|db[2]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N22 -cycloneive_lcell_comb \z80_|alu_control_|db[2]~29 ( -// Equation(s): -// \z80_|alu_control_|db[2]~29_combout = ((\z80_|alu_control_|db[2]~23_combout & (\z80_|alu_control_|db[2]~28_combout & !\z80_|alu_control_|db[2]~27_combout ))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|alu_control_|db[6]~11_combout ), - .datab(\z80_|alu_control_|db[2]~23_combout ), - .datac(\z80_|alu_control_|db[2]~28_combout ), - .datad(\z80_|alu_control_|db[2]~27_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[2]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[2]~29 .lut_mask = 16'h55D5; -defparam \z80_|alu_control_|db[2]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N30 -cycloneive_lcell_comb \z80_|alu_|db[2]~14 ( -// Equation(s): -// \z80_|alu_|db[2]~14_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[2]~39_combout & ((\z80_|alu_control_|db[2]~29_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & -// (((\z80_|alu_control_|db[2]~29_combout )) # (!\z80_|execute_|ctl_sw_2d~13_combout ))) - - .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datab(\z80_|execute_|ctl_sw_2d~13_combout ), - .datac(\z80_|alu_control_|db[2]~29_combout ), - .datad(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[2]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[2]~14 .lut_mask = 16'hF351; -defparam \z80_|alu_|db[2]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N4 -cycloneive_lcell_comb \z80_|alu_|db[2]~15 ( -// Equation(s): -// \z80_|alu_|db[2]~15_combout = ((\z80_|alu_|db[2]~14_combout & ((\z80_|alu_|db_low[2]~24_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~26_combout ) - - .dataa(\z80_|alu_|db_low[2]~24_combout ), - .datab(\z80_|execute_|ctl_alu_oe~14_combout ), - .datac(\z80_|alu_|db[2]~14_combout ), - .datad(\z80_|alu_|db[7]~26_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[2]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[2]~15 .lut_mask = 16'hB0FF; -defparam \z80_|alu_|db[2]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N4 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~2 ( -// Equation(s): -// \z80_|alu_|db_low[2]~2_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[3]~11_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[1]~13_combout ))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|alu_|db[3]~11_combout ), - .datac(\z80_|alu_|db[1]~13_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~2 .lut_mask = 16'hD8D8; -defparam \z80_|alu_|db_low[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N8 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~3 ( -// Equation(s): -// \z80_|alu_|db_low[2]~3_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_low[2]~2_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[2]~15_combout ))) # -// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) - - .dataa(\z80_|alu_|db[2]~15_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datac(\z80_|alu_|db_low[2]~2_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~3 .lut_mask = 16'hF3BB; -defparam \z80_|alu_|db_low[2]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N18 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & (((\z80_|alu_|db_low[2]~6_combout & \z80_|alu_|db_low[2]~3_combout )) # (!\z80_|alu_|db_high[3]~3_combout ))) - - .dataa(\z80_|alu_|db_low[2]~6_combout ), - .datab(\z80_|alu_|db_high[3]~3_combout ), - .datac(\z80_|alu_|db_low[2]~3_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2 .lut_mask = 16'hB300; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N24 -cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 ( -// Equation(s): -// \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & ((\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout ) # ((\z80_|alu_|db_high[2]~14_combout & \z80_|execute_|ctl_alu_op1_sel_low~combout )))) - - .dataa(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2_combout ), - .datab(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), - .datac(\z80_|alu_|db_high[2]~14_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_low~combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 .lut_mask = 16'h3222; -defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y10_N25 -dffeas \z80_|alu_|op1_low[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op1_low [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op1_low[2] .is_wysiwyg = "true"; -defparam \z80_|alu_|op1_low[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N24 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [2]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [2])))) - - .dataa(\z80_|alu_|op1_high [2]), - .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datac(\z80_|execute_|ctl_alu_op_low~combout ), - .datad(\z80_|alu_|op1_low [2]), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0 .lut_mask = 16'hC808; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N12 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0_combout ) # ((\z80_|alu_|db_low[2]~24_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datab(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0_combout ), - .datac(\z80_|alu_|db_low[2]~24_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1 .lut_mask = 16'h5444; -defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y10_N13 -dffeas \z80_|alu_|op2_low[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_low [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_low[2] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_low[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N30 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~5 ( -// Equation(s): -// \z80_|alu_|db_low[2]~5_combout = (\z80_|alu_|op2_low [2] & ((\z80_|alu_|op1_low [2]) # ((!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) # (!\z80_|alu_|op2_low [2] & (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_low [2]) # -// (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) - - .dataa(\z80_|alu_|op2_low [2]), - .datab(\z80_|alu_|op1_low [2]), - .datac(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~5 .lut_mask = 16'h8ACF; -defparam \z80_|alu_|db_low[2]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y10_N13 -dffeas \z80_|alu_|result_lo[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_alu_op_low~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|result_lo [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|result_lo[2] .is_wysiwyg = "true"; -defparam \z80_|alu_|result_lo[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N30 -cycloneive_lcell_comb \z80_|alu_|db_low[2]~6 ( -// Equation(s): -// \z80_|alu_|db_low[2]~6_combout = (\z80_|alu_|db_low[2]~4_combout & (\z80_|alu_|db_low[2]~5_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|result_lo [2])))) - - .dataa(\z80_|alu_|db_low[2]~4_combout ), - .datab(\z80_|alu_|db_low[2]~5_combout ), - .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datad(\z80_|alu_|result_lo [2]), - .cin(gnd), - .combout(\z80_|alu_|db_low[2]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_low[2]~6 .lut_mask = 16'h8880; -defparam \z80_|alu_|db_low[2]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N24 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & (((\z80_|alu_|db_low[2]~6_combout & \z80_|alu_|db_low[2]~3_combout )) # (!\z80_|alu_|db_high[3]~3_combout ))) - - .dataa(\z80_|alu_|db_low[2]~6_combout ), - .datab(\z80_|alu_|db_low[2]~3_combout ), - .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), - .datad(\z80_|alu_|db_high[3]~3_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 .lut_mask = 16'h80F0; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y10_N26 -cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4 ( -// Equation(s): -// \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ) # ((\z80_|alu_|db_high[2]~14_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), - .datab(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ), - .datac(\z80_|alu_|db_high[2]~14_combout ), - .datad(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4 .lut_mask = 16'h5444; -defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y10_N27 -dffeas \z80_|alu_|op2_high[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_|op2_high [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_|op2_high[2] .is_wysiwyg = "true"; -defparam \z80_|alu_|op2_high[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N14 -cycloneive_lcell_comb \z80_|alu_|alu_op2[2]~0 ( -// Equation(s): -// \z80_|alu_|alu_op2[2]~0_combout = \z80_|execute_|ctl_alu_sel_op2_neg~18_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_high [2])) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_low [2]))))) - - .dataa(\z80_|alu_|op2_high [2]), - .datab(\z80_|execute_|ctl_alu_sel_op2_high~combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), - .datad(\z80_|alu_|op2_low [2]), - .cin(gnd), - .combout(\z80_|alu_|alu_op2[2]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|alu_op2[2]~0 .lut_mask = 16'h4B78; -defparam \z80_|alu_|alu_op2[2]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N0 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ) # -// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) # (!\z80_|execute_|ctl_alu_core_R~5_combout ) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), - .datad(\z80_|execute_|ctl_alu_core_R~5_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 .lut_mask = 16'h0BFF; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y10_N12 -cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 ( -// Equation(s): -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout = (\z80_|alu_|alu_op2[2]~0_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ) # ((\z80_|alu_|alu_op1[2]~2_combout & -// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) # (!\z80_|alu_|alu_op2[2]~0_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_|alu_op1[2]~2_combout ) # -// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) - - .dataa(\z80_|alu_|alu_op2[2]~0_combout ), - .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ), - .datac(\z80_|alu_|alu_op1[2]~2_combout ), - .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 .lut_mask = 16'hECC8; -defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N26 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~9 ( -// Equation(s): -// \z80_|alu_|db_high[2]~9_combout = ((\z80_|bus_control_|db[4]~19_combout & (\z80_|bus_control_|db[5]~15_combout & !\z80_|bus_control_|db[3]~21_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datab(\z80_|bus_control_|db[4]~19_combout ), - .datac(\z80_|bus_control_|db[5]~15_combout ), - .datad(\z80_|bus_control_|db[3]~21_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~9 .lut_mask = 16'h55D5; -defparam \z80_|alu_|db_high[2]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N24 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~11 ( -// Equation(s): -// \z80_|alu_|db_high[2]~11_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[7]~21_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[5]~25_combout )) - - .dataa(\z80_|ir_|opcode [3]), - .datab(gnd), - .datac(\z80_|alu_|db[5]~25_combout ), - .datad(\z80_|alu_|db[7]~21_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~11 .lut_mask = 16'hFA50; -defparam \z80_|alu_|db_high[2]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N22 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~12 ( -// Equation(s): -// \z80_|alu_|db_high[2]~12_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_high[2]~11_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[6]~23_combout ))) - - .dataa(gnd), - .datab(\z80_|alu_|db_high[2]~11_combout ), - .datac(\z80_|alu_|db[6]~23_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~12 .lut_mask = 16'hCCF0; -defparam \z80_|alu_|db_high[2]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N24 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~10 ( -// Equation(s): -// \z80_|alu_|db_high[2]~10_combout = (\z80_|alu_|op1_high [2] & (((\z80_|alu_|op2_high [2]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|alu_|op1_high [2] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_high [2]) # -// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) - - .dataa(\z80_|alu_|op1_high [2]), - .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datac(\z80_|alu_|op2_high [2]), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~10 .lut_mask = 16'hB0BB; -defparam \z80_|alu_|db_high[2]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N20 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~13 ( -// Equation(s): -// \z80_|alu_|db_high[2]~13_combout = (\z80_|alu_|db_high[2]~9_combout & (\z80_|alu_|db_high[2]~10_combout & ((\z80_|alu_|db_high[2]~12_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) - - .dataa(\z80_|alu_|db_high[2]~9_combout ), - .datab(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datac(\z80_|alu_|db_high[2]~12_combout ), - .datad(\z80_|alu_|db_high[2]~10_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~13 .lut_mask = 16'hA200; -defparam \z80_|alu_|db_high[2]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N10 -cycloneive_lcell_comb \z80_|alu_|db_high[2]~14 ( -// Equation(s): -// \z80_|alu_|db_high[2]~14_combout = ((\z80_|alu_|db_high[2]~13_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ) # (\z80_|execute_|ctl_alu_res_oe~2_combout )))) # (!\z80_|alu_|db_high[3]~3_combout ) - - .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), - .datab(\z80_|alu_|db_high[3]~3_combout ), - .datac(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datad(\z80_|alu_|db_high[2]~13_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[2]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[2]~14 .lut_mask = 16'hFB33; -defparam \z80_|alu_|db_high[2]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N18 -cycloneive_lcell_comb \z80_|alu_|db[6]~22 ( -// Equation(s): -// \z80_|alu_|db[6]~22_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[6]~84_combout & ((\z80_|alu_control_|db[6]~22_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & -// (((\z80_|alu_control_|db[6]~22_combout )) # (!\z80_|execute_|ctl_sw_2d~13_combout ))) - - .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datab(\z80_|execute_|ctl_sw_2d~13_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), - .datad(\z80_|alu_control_|db[6]~22_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[6]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[6]~22 .lut_mask = 16'hF531; -defparam \z80_|alu_|db[6]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N20 -cycloneive_lcell_comb \z80_|alu_|db[6]~23 ( -// Equation(s): -// \z80_|alu_|db[6]~23_combout = ((\z80_|alu_|db[6]~22_combout & ((\z80_|alu_|db_high[2]~14_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~26_combout ) - - .dataa(\z80_|alu_|db_high[2]~14_combout ), - .datab(\z80_|execute_|ctl_alu_oe~14_combout ), - .datac(\z80_|alu_|db[6]~22_combout ), - .datad(\z80_|alu_|db[7]~26_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[6]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[6]~23 .lut_mask = 16'hB0FF; -defparam \z80_|alu_|db[6]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y10_N10 -cycloneive_lcell_comb \z80_|alu_control_|out[6]~1 ( -// Equation(s): -// \z80_|alu_control_|out[6]~1_combout = (\z80_|alu_|op1_high [2]) # ((\z80_|alu_|op1_high [1]) # ((\z80_|alu_|op1_high [0] & \z80_|alu_control_|out[6]~0_combout ))) - - .dataa(\z80_|alu_|op1_high [2]), - .datab(\z80_|alu_|op1_high [0]), - .datac(\z80_|alu_|op1_high [1]), - .datad(\z80_|alu_control_|out[6]~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|out[6]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|out[6]~1 .lut_mask = 16'hFEFA; -defparam \z80_|alu_control_|out[6]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N26 -cycloneive_lcell_comb \z80_|alu_control_|out[6]~2 ( -// Equation(s): -// \z80_|alu_control_|out[6]~2_combout = (\z80_|execute_|ctl_66_oe~combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_cf~q ) # ((\z80_|alu_control_|out[6]~1_combout & \z80_|alu_|op1_high [3]))) - - .dataa(\z80_|execute_|ctl_66_oe~combout ), - .datab(\z80_|alu_control_|out[6]~1_combout ), - .datac(\z80_|alu_|op1_high [3]), - .datad(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), - .cin(gnd), - .combout(\z80_|alu_control_|out[6]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|out[6]~2 .lut_mask = 16'hFFEA; -defparam \z80_|alu_control_|out[6]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N12 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~19 ( -// Equation(s): -// \z80_|alu_control_|db[6]~19_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & ((\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ) # ((\z80_|alu_control_|out[6]~2_combout )))) # (!\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & -// (!\z80_|execute_|ctl_flags_oe~2_combout & ((\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ) # (\z80_|alu_control_|out[6]~2_combout )))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .datab(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .datac(\z80_|execute_|ctl_flags_oe~2_combout ), - .datad(\z80_|alu_control_|out[6]~2_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~19 .lut_mask = 16'hAF8C; -defparam \z80_|alu_control_|db[6]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N26 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~20 ( -// Equation(s): -// \z80_|alu_control_|db[6]~20_combout = (\z80_|alu_control_|db[6]~19_combout & ((\z80_|alu_|db[6]~23_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout ))) - - .dataa(gnd), - .datab(\z80_|alu_|db[6]~23_combout ), - .datac(\z80_|execute_|ctl_sw_2u~7_combout ), - .datad(\z80_|alu_control_|db[6]~19_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~20 .lut_mask = 16'hCF00; -defparam \z80_|alu_control_|db[6]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N24 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~21 ( -// Equation(s): -// \z80_|alu_control_|db[6]~21_combout = (\z80_|alu_control_|db[6]~20_combout & (((\z80_|bus_control_|db[6]~9_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) - - .dataa(\z80_|bus_control_|db[6]~9_combout ), - .datab(\z80_|execute_|ctl_sw_1d~7_combout ), - .datac(\z80_|alu_control_|db[6]~20_combout ), - .datad(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~21 .lut_mask = 16'h30B0; -defparam \z80_|alu_control_|db[6]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N6 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~22 ( -// Equation(s): -// \z80_|alu_control_|db[6]~22_combout = ((\z80_|alu_control_|db[6]~21_combout & ((\z80_|reg_file_|gdfx_temp0[6]~82_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|alu_control_|db[6]~11_combout ), - .datab(\z80_|alu_control_|db[6]~21_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), - .datad(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~22 .lut_mask = 16'hD5DD; -defparam \z80_|alu_control_|db[6]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_zero_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_bus_zero_oe~0_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal33~1_combout & ((\z80_|execute_|ctl_alu_op_low~13_combout ) # (\z80_|execute_|ctl_iorw~11_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~13_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_iorw~11_combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_zero_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_zero_oe~0 .lut_mask = 16'hC800; -defparam \z80_|execute_|ctl_bus_zero_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N8 -cycloneive_lcell_comb \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 ( -// Equation(s): -// \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout = (\z80_|bus_control_|db[4]~19_combout & !\z80_|bus_control_|db[3]~21_combout ) - - .dataa(gnd), - .datab(\z80_|bus_control_|db[4]~19_combout ), - .datac(gnd), - .datad(\z80_|bus_control_|db[3]~21_combout ), - .cin(gnd), - .combout(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 .lut_mask = 16'h00CC; -defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y10_N9 -dffeas \z80_|interrupts_|im1 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_im_we~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|interrupts_|im1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|interrupts_|im1 .is_wysiwyg = "true"; -defparam \z80_|interrupts_|im1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_ff_oe~0 ( -// Equation(s): -// \z80_|execute_|ctl_bus_ff_oe~0_combout = (\z80_|interrupts_|DFFE_inst44~q & ((\z80_|interrupts_|im1~q ) # ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|interrupts_|im2~q )))) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|interrupts_|im1~q ), - .datac(\z80_|interrupts_|im2~q ), - .datad(\z80_|interrupts_|DFFE_inst44~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_ff_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_ff_oe~0 .lut_mask = 16'hDC00; -defparam \z80_|execute_|ctl_bus_ff_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_ff_oe~1 ( -// Equation(s): -// \z80_|execute_|ctl_bus_ff_oe~1_combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) # (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|execute_|ctl_bus_ff_oe~0_combout & -// ((\z80_|execute_|ctl_66_oe~2_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|execute_|ctl_bus_ff_oe~0_combout ), - .datac(\z80_|execute_|ctl_66_oe~2_combout ), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_ff_oe~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_ff_oe~1 .lut_mask = 16'h40EE; -defparam \z80_|execute_|ctl_bus_ff_oe~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N0 -cycloneive_lcell_comb \z80_|bus_control_|db[0]~4 ( -// Equation(s): -// \z80_|bus_control_|db[0]~4_combout = (\z80_|execute_|ctl_bus_ff_oe~1_combout ) # ((!\z80_|execute_|ctl_bus_zero_oe~0_combout & ((\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) # (!\z80_|decode_state_|in_halt~q )))) - - .dataa(\z80_|decode_state_|in_halt~q ), - .datab(\z80_|execute_|ctl_bus_zero_oe~0_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|execute_|ctl_bus_ff_oe~1_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[0]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[0]~4 .lut_mask = 16'hFF31; -defparam \z80_|bus_control_|db[0]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N6 -cycloneive_lcell_comb \z80_|bus_control_|db[6]~8 ( -// Equation(s): -// \z80_|bus_control_|db[6]~8_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[6]~22_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) - - .dataa(gnd), - .datab(\z80_|alu_control_|db[6]~22_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|bus_control_|db[0]~4_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[6]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[6]~8 .lut_mask = 16'hCF00; -defparam \z80_|bus_control_|db[6]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~37 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~37_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal37~0_combout & !\z80_|execute_|ctl_mRead~36_combout ))) # (!\z80_|sequencer_|DFFE_T5_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|pla_decode_|Equal37~0_combout ), - .datad(\z80_|execute_|ctl_mRead~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~37 .lut_mask = 16'hDDDF; -defparam \z80_|execute_|ctl_mRead~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~28 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~28_combout = (\z80_|execute_|ctl_mRead~37_combout & (!\z80_|execute_|ctl_reg_gp_sel~36_combout & ((!\z80_|pla_decode_|Equal38~2_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~37_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|ctl_reg_gp_sel~36_combout ), - .datad(\z80_|pla_decode_|Equal38~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~28 .lut_mask = 16'h020A; -defparam \z80_|execute_|ctl_mRead~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~29 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~29_combout = (\z80_|execute_|ctl_mRead~28_combout & (\z80_|execute_|ctl_mRead~25_combout & ((!\z80_|pla_decode_|Equal21~1_combout ) # (!\z80_|execute_|ctl_mRead~11_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~28_combout ), - .datab(\z80_|execute_|ctl_mRead~11_combout ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|execute_|ctl_mRead~25_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~29 .lut_mask = 16'h2A00; -defparam \z80_|execute_|ctl_mRead~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~30 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~30_combout = (\z80_|execute_|ctl_mRead~29_combout & (\z80_|execute_|ctl_reg_in_hi~5_combout & (\z80_|execute_|ctl_mRead~22_combout & !\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ))) - - .dataa(\z80_|execute_|ctl_mRead~29_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~5_combout ), - .datac(\z80_|execute_|ctl_mRead~22_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~30 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_mRead~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y18_N0 -cycloneive_lcell_comb \z80_|execute_|setM1~37 ( -// Equation(s): -// \z80_|execute_|setM1~37_combout = (!\z80_|pla_decode_|Equal9~1_combout & (!\z80_|pla_decode_|Equal29~0_combout & (\z80_|execute_|ctl_al_we~4_combout & \z80_|execute_|ctl_inc_cy~41_combout ))) - - .dataa(\z80_|pla_decode_|Equal9~1_combout ), - .datab(\z80_|pla_decode_|Equal29~0_combout ), - .datac(\z80_|execute_|ctl_al_we~4_combout ), - .datad(\z80_|execute_|ctl_inc_cy~41_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~37_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~37 .lut_mask = 16'h1000; -defparam \z80_|execute_|setM1~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N10 -cycloneive_lcell_comb \z80_|execute_|setM1~55 ( +// Location: LCCOMB_X25_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|ixy_d~17 ( // Equation(s): -// \z80_|execute_|setM1~55_combout = (!\z80_|execute_|ctl_mRead~14_combout & ((\z80_|decode_state_|DFFE_instIY1~q ) # ((\z80_|decode_state_|DFFE_inst4~q ) # (!\z80_|pla_decode_|Equal49~0_combout )))) +// \z80_|execute_|ixy_d~17_combout = (\z80_|decode_state_|DFFE_instIY1~q & (((!\z80_|pla_decode_|Equal33~2_combout & !\z80_|pla_decode_|Equal50~0_combout )))) # (!\z80_|decode_state_|DFFE_instIY1~q & (((!\z80_|pla_decode_|Equal33~2_combout & +// !\z80_|pla_decode_|Equal50~0_combout )) # (!\z80_|decode_state_|DFFE_inst4~q ))) .dataa(\z80_|decode_state_|DFFE_instIY1~q ), - .datab(\z80_|execute_|ctl_mRead~14_combout ), - .datac(\z80_|decode_state_|DFFE_inst4~q ), - .datad(\z80_|pla_decode_|Equal49~0_combout ), + .datab(\z80_|decode_state_|DFFE_inst4~q ), + .datac(\z80_|pla_decode_|Equal33~2_combout ), + .datad(\z80_|pla_decode_|Equal50~0_combout ), .cin(gnd), - .combout(\z80_|execute_|setM1~55_combout ), + .combout(\z80_|execute_|ixy_d~17_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|setM1~55 .lut_mask = 16'h3233; -defparam \z80_|execute_|setM1~55 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ixy_d~17 .lut_mask = 16'h111F; +defparam \z80_|execute_|ixy_d~17 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y18_N30 -cycloneive_lcell_comb \z80_|execute_|setM1~38 ( +// Location: LCCOMB_X25_Y16_N0 +cycloneive_lcell_comb \z80_|pla_decode_|Equal44~0 ( // Equation(s): -// \z80_|execute_|setM1~38_combout = (!\z80_|execute_|ctl_mRead~16_combout & (\z80_|execute_|setM1~37_combout & (\z80_|execute_|setM1~55_combout & \z80_|execute_|setM1~36_combout ))) +// \z80_|pla_decode_|Equal44~0_combout = (!\z80_|decode_state_|DFFE_instCB~q & (!\z80_|decode_state_|DFFE_instED~q & (\z80_|ir_|opcode [7] & !\z80_|ir_|opcode [6]))) - .dataa(\z80_|execute_|ctl_mRead~16_combout ), - .datab(\z80_|execute_|setM1~37_combout ), - .datac(\z80_|execute_|setM1~55_combout ), - .datad(\z80_|execute_|setM1~36_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~38_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~38 .lut_mask = 16'h4000; -defparam \z80_|execute_|setM1~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~34 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~34_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (((\z80_|execute_|ctl_mRead~13_combout ) # (!\z80_|execute_|ctl_mRead~19_combout )) # (!\z80_|execute_|setM1~38_combout ))) - - .dataa(\z80_|execute_|setM1~38_combout ), - .datab(\z80_|execute_|ctl_mRead~13_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_mRead~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~34 .lut_mask = 16'hD0F0; -defparam \z80_|execute_|ctl_mRead~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N2 -cycloneive_lcell_comb \z80_|execute_|nextM~3 ( -// Equation(s): -// \z80_|execute_|nextM~3_combout = (!\z80_|pla_decode_|Equal41~2_combout & (!\z80_|execute_|ixy_d~10_combout & !\z80_|execute_|ixy_d~16_combout )) - - .dataa(gnd), - .datab(\z80_|pla_decode_|Equal41~2_combout ), - .datac(\z80_|execute_|ixy_d~10_combout ), - .datad(\z80_|execute_|ixy_d~16_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~3 .lut_mask = 16'h0003; -defparam \z80_|execute_|nextM~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~31 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~31_combout = (\z80_|execute_|ixy_d~8_combout & (((\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal49~0_combout )) # (!\z80_|execute_|nextM~3_combout ))) - - .dataa(\z80_|execute_|ixy_d~8_combout ), - .datab(\z80_|decode_state_|use_ixiy~combout ), - .datac(\z80_|execute_|nextM~3_combout ), - .datad(\z80_|pla_decode_|Equal49~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~31 .lut_mask = 16'h8A0A; -defparam \z80_|execute_|ctl_mRead~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~32 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~32_combout = (\z80_|execute_|ctl_state_alu~4_combout & ((\z80_|pla_decode_|Equal33~3_combout ) # ((\z80_|pla_decode_|Equal6~1_combout ) # (\z80_|pla_decode_|Equal41~2_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|pla_decode_|Equal33~3_combout ), - .datac(\z80_|pla_decode_|Equal6~1_combout ), - .datad(\z80_|pla_decode_|Equal41~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~32 .lut_mask = 16'hAAA8; -defparam \z80_|execute_|ctl_mRead~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~33 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~33_combout = (\z80_|execute_|ctl_mRead~32_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & \z80_|execute_|ctl_mRead~12_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .datac(\z80_|execute_|ctl_mRead~12_combout ), - .datad(\z80_|execute_|ctl_mRead~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~33 .lut_mask = 16'hFFC0; -defparam \z80_|execute_|ctl_mRead~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~35 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~35_combout = ((\z80_|execute_|ctl_mRead~34_combout ) # ((\z80_|execute_|ctl_mRead~31_combout ) # (\z80_|execute_|ctl_mRead~33_combout ))) # (!\z80_|execute_|ctl_mRead~30_combout ) - - .dataa(\z80_|execute_|ctl_mRead~30_combout ), - .datab(\z80_|execute_|ctl_mRead~34_combout ), - .datac(\z80_|execute_|ctl_mRead~31_combout ), - .datad(\z80_|execute_|ctl_mRead~33_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~35_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~35 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|ctl_mRead~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X43_Y17_N23 -dffeas \z80_|memory_ifc_|DFFE_mrd_ff1 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_mRead~35_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_mrd_ff1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_mrd_ff1 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_mrd_ff1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y15_N24 -cycloneive_lcell_comb \z80_|memory_ifc_|wait_mrd~feeder ( -// Equation(s): -// \z80_|memory_ifc_|wait_mrd~feeder_combout = \z80_|memory_ifc_|DFFE_mrd_ff1~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|memory_ifc_|DFFE_mrd_ff1~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|wait_mrd~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_mrd~feeder .lut_mask = 16'hFF00; -defparam \z80_|memory_ifc_|wait_mrd~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X46_Y15_N25 -dffeas \z80_|memory_ifc_|wait_mrd ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|memory_ifc_|wait_mrd~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|wait_mrd~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_mrd .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|wait_mrd .power_up = "low"; -// synopsys translate_on - -// Location: FF_X43_Y17_N3 -dffeas \z80_|memory_ifc_|DFFE_mrd_ff3 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|memory_ifc_|wait_mrd~q ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_mrd_ff3~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_mrd_ff3 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_mrd_ff3 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N8 -cycloneive_lcell_comb \z80_|memory_ifc_|nRD_out~1 ( -// Equation(s): -// \z80_|memory_ifc_|nRD_out~1_combout = (!\z80_|memory_ifc_|wait_mrd~q & !\z80_|memory_ifc_|DFFE_mrd_ff3~q ) - - .dataa(\z80_|memory_ifc_|wait_mrd~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|memory_ifc_|DFFE_mrd_ff3~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|nRD_out~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|nRD_out~1 .lut_mask = 16'h0055; -defparam \z80_|memory_ifc_|nRD_out~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N30 -cycloneive_lcell_comb \z80_|execute_|nextM~4 ( -// Equation(s): -// \z80_|execute_|nextM~4_combout = ((!\z80_|execute_|ctl_mRead~36_combout & ((!\z80_|pla_decode_|Equal24~0_combout ) # (!\z80_|pla_decode_|Equal21~0_combout )))) # (!\z80_|execute_|ctl_state_alu~4_combout ) - - .dataa(\z80_|pla_decode_|Equal21~0_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_mRead~36_combout ), - .datad(\z80_|pla_decode_|Equal24~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~4 .lut_mask = 16'h373F; -defparam \z80_|execute_|nextM~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_iorw~12 ( -// Equation(s): -// \z80_|execute_|ctl_iorw~12_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [2]))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|pla_decode_|Equal13~0_combout ), - .datac(\z80_|ir_|opcode [1]), - .datad(\z80_|ir_|opcode [2]), - .cin(gnd), - .combout(\z80_|execute_|ctl_iorw~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_iorw~12 .lut_mask = 16'h0008; -defparam \z80_|execute_|ctl_iorw~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_iorw~8 ( -// Equation(s): -// \z80_|execute_|ctl_iorw~8_combout = (\z80_|execute_|ctl_iorw~12_combout ) # ((\z80_|pla_decode_|Equal24~0_combout & (\z80_|pla_decode_|Equal3~0_combout & \z80_|execute_|ctl_state_alu~4_combout ))) - - .dataa(\z80_|pla_decode_|Equal24~0_combout ), - .datab(\z80_|execute_|ctl_iorw~12_combout ), - .datac(\z80_|pla_decode_|Equal3~0_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_iorw~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_iorw~8 .lut_mask = 16'hECCC; -defparam \z80_|execute_|ctl_iorw~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_iorw~9 ( -// Equation(s): -// \z80_|execute_|ctl_iorw~9_combout = ((\z80_|execute_|ctl_iorw~8_combout ) # ((\z80_|execute_|ctl_mRead~11_combout & \z80_|execute_|ctl_mWrite~16_combout ))) # (!\z80_|execute_|nextM~4_combout ) - - .dataa(\z80_|execute_|nextM~4_combout ), - .datab(\z80_|execute_|ctl_mRead~11_combout ), - .datac(\z80_|execute_|ctl_mWrite~16_combout ), - .datad(\z80_|execute_|ctl_iorw~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_iorw~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_iorw~9 .lut_mask = 16'hFFD5; -defparam \z80_|execute_|ctl_iorw~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X43_Y17_N7 -dffeas \z80_|memory_ifc_|DFFE_iorq_ff1 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_iorw~9_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_iorq_ff1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_iorq_ff1 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_iorq_ff1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N26 -cycloneive_lcell_comb \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder ( -// Equation(s): -// \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder_combout = \z80_|memory_ifc_|DFFE_iorq_ff1~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|memory_ifc_|DFFE_iorq_ff1~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder .lut_mask = 16'hFF00; -defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X43_Y17_N27 -dffeas \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 .power_up = "low"; -// synopsys translate_on - -// Location: FF_X43_Y17_N9 -dffeas \z80_|memory_ifc_|wait_iorq ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|wait_iorq~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_iorq .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|wait_iorq .power_up = "low"; -// synopsys translate_on - -// Location: FF_X43_Y17_N13 -dffeas \z80_|memory_ifc_|DFFE_iorq_ff4 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|memory_ifc_|wait_iorq~q ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_iorq_ff4~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_iorq_ff4 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_iorq_ff4 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N12 -cycloneive_lcell_comb \z80_|memory_ifc_|iorq~0 ( -// Equation(s): -// \z80_|memory_ifc_|iorq~0_combout = (\z80_|memory_ifc_|wait_iorq~q ) # ((\z80_|memory_ifc_|DFFE_iorq_ff4~q ) # (\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q )) - - .dataa(gnd), - .datab(\z80_|memory_ifc_|wait_iorq~q ), - .datac(\z80_|memory_ifc_|DFFE_iorq_ff4~q ), - .datad(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|iorq~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|iorq~0 .lut_mask = 16'hFFFC; -defparam \z80_|memory_ifc_|iorq~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|fIORead~1 ( -// Equation(s): -// \z80_|execute_|fIORead~1_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_mWrite~2_combout & ((\z80_|execute_|ctl_state_alu~5_combout ) # (\z80_|execute_|ctl_mWrite~3_combout )))) - - .dataa(\z80_|pla_decode_|Equal55~0_combout ), - .datab(\z80_|execute_|ctl_state_alu~5_combout ), - .datac(\z80_|execute_|ctl_mWrite~3_combout ), - .datad(\z80_|execute_|ctl_mWrite~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIORead~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIORead~1 .lut_mask = 16'hA800; -defparam \z80_|execute_|fIORead~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N18 -cycloneive_lcell_comb \z80_|execute_|fIORead~2 ( -// Equation(s): -// \z80_|execute_|fIORead~2_combout = (\z80_|execute_|fIORead~1_combout ) # ((\z80_|execute_|ctl_alu_op_low~9_combout ) # ((\z80_|execute_|ctl_iorw~10_combout & !\z80_|execute_|fIOWrite~0_combout ))) - - .dataa(\z80_|execute_|ctl_iorw~10_combout ), - .datab(\z80_|execute_|fIOWrite~0_combout ), - .datac(\z80_|execute_|fIORead~1_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIORead~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIORead~2 .lut_mask = 16'hFFF2; -defparam \z80_|execute_|fIORead~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y18_N6 -cycloneive_lcell_comb \z80_|execute_|fIORead~0 ( -// Equation(s): -// \z80_|execute_|fIORead~0_combout = (\z80_|execute_|ctl_mWrite~2_combout & (\z80_|pla_decode_|Equal55~0_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ctl_alu_op_low~8_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~2_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|pla_decode_|Equal55~0_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIORead~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIORead~0 .lut_mask = 16'hA080; -defparam \z80_|execute_|fIORead~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N6 -cycloneive_lcell_comb \z80_|execute_|fIORead~3 ( -// Equation(s): -// \z80_|execute_|fIORead~3_combout = (\z80_|execute_|fIORead~2_combout ) # ((\z80_|execute_|fIORead~0_combout ) # ((\z80_|execute_|fIOWrite~1_combout & \z80_|execute_|ctl_mRead~4_combout ))) - - .dataa(\z80_|execute_|fIOWrite~1_combout ), - .datab(\z80_|execute_|fIORead~2_combout ), - .datac(\z80_|execute_|ctl_mRead~4_combout ), - .datad(\z80_|execute_|fIORead~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|fIORead~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fIORead~3 .lut_mask = 16'hFFEC; -defparam \z80_|execute_|fIORead~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X41_Y17_N25 -dffeas \z80_|memory_ifc_|DFFE_m1_ff1 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|setM1~52_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_m1_ff1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_m1_ff1 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_m1_ff1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N14 -cycloneive_lcell_comb \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0 ( -// Equation(s): -// \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout = !\z80_|memory_ifc_|DFFE_m1_ff1~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|memory_ifc_|DFFE_m1_ff1~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0 .lut_mask = 16'h00FF; -defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X43_Y17_N15 -dffeas \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 .power_up = "low"; -// synopsys translate_on - -// Location: FF_X43_Y17_N21 -dffeas \z80_|memory_ifc_|DFFE_m1_ff3 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_m1_ff3~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_m1_ff3 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_m1_ff3 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N20 -cycloneive_lcell_comb \z80_|memory_ifc_|nRD_out~0 ( -// Equation(s): -// \z80_|memory_ifc_|nRD_out~0_combout = (\z80_|interrupts_|DFFE_inst44~q & (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & ((\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ) # (\z80_|memory_ifc_|DFFE_m1_ff3~q )))) # (!\z80_|interrupts_|DFFE_inst44~q & -// ((\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ) # ((\z80_|memory_ifc_|DFFE_m1_ff3~q )))) - - .dataa(\z80_|interrupts_|DFFE_inst44~q ), - .datab(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ), - .datac(\z80_|memory_ifc_|DFFE_m1_ff3~q ), - .datad(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|nRD_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|nRD_out~0 .lut_mask = 16'hFC54; -defparam \z80_|memory_ifc_|nRD_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N18 -cycloneive_lcell_comb \z80_|memory_ifc_|nRD_out~2 ( -// Equation(s): -// \z80_|memory_ifc_|nRD_out~2_combout = ((\z80_|memory_ifc_|nRD_out~0_combout ) # ((\z80_|memory_ifc_|iorq~0_combout & \z80_|execute_|fIORead~3_combout ))) # (!\z80_|memory_ifc_|nRD_out~1_combout ) - - .dataa(\z80_|memory_ifc_|nRD_out~1_combout ), - .datab(\z80_|memory_ifc_|iorq~0_combout ), - .datac(\z80_|execute_|fIORead~3_combout ), - .datad(\z80_|memory_ifc_|nRD_out~0_combout ), - .cin(gnd), - .combout(\z80_|memory_ifc_|nRD_out~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|nRD_out~2 .lut_mask = 16'hFFD5; -defparam \z80_|memory_ifc_|nRD_out~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N24 -cycloneive_lcell_comb \Equal2~1 ( -// Equation(s): -// \Equal2~1_combout = (!\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|memory_ifc_|nRD_out~2_combout & \z80_|resets_|SYNTHESIZED_WIRE_12~q )) - - .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), - .datab(\z80_|memory_ifc_|nRD_out~2_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(gnd), - .cin(gnd), - .combout(\Equal2~1_combout ), - .cout()); -// synopsys translate_off -defparam \Equal2~1 .lut_mask = 16'h4040; -defparam \Equal2~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N30 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~0 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~0_combout = (\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|sequencer_|DFFE_T3_ff~q ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~0 .lut_mask = 16'hFFAA; -defparam \z80_|pin_control_|bus_db_pin_oe~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y18_N10 -cycloneive_lcell_comb \z80_|execute_|fMWrite~5 ( -// Equation(s): -// \z80_|execute_|fMWrite~5_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|sequencer_|DFFE_M4_ff~q ) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_M4_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~5 .lut_mask = 16'h3F33; -defparam \z80_|execute_|fMWrite~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N8 -cycloneive_lcell_comb \z80_|execute_|fMWrite~6 ( -// Equation(s): -// \z80_|execute_|fMWrite~6_combout = (!\z80_|execute_|fMWrite~5_combout & ((\z80_|execute_|ctl_mRead~7_combout ) # ((\z80_|pla_decode_|Equal13~2_combout ) # (\z80_|execute_|ctl_mWrite~5_combout )))) - - .dataa(\z80_|execute_|fMWrite~5_combout ), - .datab(\z80_|execute_|ctl_mRead~7_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|ctl_mWrite~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~6 .lut_mask = 16'h5554; -defparam \z80_|execute_|fMWrite~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N30 -cycloneive_lcell_comb \z80_|execute_|fMWrite~2 ( -// Equation(s): -// \z80_|execute_|fMWrite~2_combout = ((!\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|M5~q ) - - .dataa(\z80_|sequencer_|M5~q ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T2_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~2 .lut_mask = 16'h555F; -defparam \z80_|execute_|fMWrite~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N2 -cycloneive_lcell_comb \z80_|execute_|fMWrite~4 ( -// Equation(s): -// \z80_|execute_|fMWrite~4_combout = (!\z80_|execute_|fMWrite~3_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ixy_d~6_combout ) # (!\z80_|execute_|fMWrite~2_combout )))) - - .dataa(\z80_|execute_|ixy_d~5_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|execute_|fMWrite~2_combout ), - .datad(\z80_|execute_|fMWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~4 .lut_mask = 16'h00EF; -defparam \z80_|execute_|fMWrite~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N20 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~1 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~1_combout = (\z80_|execute_|ctl_bus_inc_oe~24_combout & (!\z80_|execute_|fIOWrite~5_combout & (!\z80_|execute_|fMWrite~6_combout & !\z80_|execute_|fMWrite~4_combout ))) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~24_combout ), - .datab(\z80_|execute_|fIOWrite~5_combout ), - .datac(\z80_|execute_|fMWrite~6_combout ), - .datad(\z80_|execute_|fMWrite~4_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~1 .lut_mask = 16'h0002; -defparam \z80_|pin_control_|bus_db_pin_oe~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N30 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~2 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~2_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|pla_decode_|Equal11~0_combout & ((!\z80_|execute_|ctl_mRead~8_combout ) # (!\z80_|execute_|ctl_reg_in_hi~2_combout )))) # (!\z80_|execute_|ixy_d~7_combout & -// (((!\z80_|execute_|ctl_mRead~8_combout )) # (!\z80_|execute_|ctl_reg_in_hi~2_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datac(\z80_|pla_decode_|Equal11~0_combout ), - .datad(\z80_|execute_|ctl_mRead~8_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~2 .lut_mask = 16'h135F; -defparam \z80_|pin_control_|bus_db_pin_oe~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y18_N24 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~3 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~3_combout = (\z80_|pin_control_|bus_db_pin_oe~2_combout & (((\z80_|execute_|ixy_d~4_combout ) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|execute_|ctl_mWrite~5_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~2_combout ), - .datab(\z80_|execute_|ctl_mWrite~5_combout ), - .datac(\z80_|execute_|ixy_d~4_combout ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~3 .lut_mask = 16'hA2AA; -defparam \z80_|pin_control_|bus_db_pin_oe~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N8 -cycloneive_lcell_comb \z80_|execute_|fMWrite~7 ( -// Equation(s): -// \z80_|execute_|fMWrite~7_combout = (!\z80_|execute_|ctl_mWrite~16_combout & (!\z80_|execute_|ctl_mWrite~4_combout & !\z80_|execute_|ctl_mRead~7_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_mWrite~16_combout ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|execute_|ctl_mRead~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~7 .lut_mask = 16'h0003; -defparam \z80_|execute_|fMWrite~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N30 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~4 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~4_combout = (\z80_|execute_|ctl_inc_dec~2_combout & ((\z80_|execute_|fMWrite~7_combout ) # ((!\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ixy_d~6_combout )))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|fMWrite~7_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|execute_|ctl_inc_dec~2_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~4 .lut_mask = 16'hCD00; -defparam \z80_|pin_control_|bus_db_pin_oe~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N10 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~7 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~7_combout = (\z80_|execute_|ctl_ir_we~4_combout & (!\z80_|execute_|ctl_mRead~10_combout & ((!\z80_|execute_|ctl_mRead~7_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) # (!\z80_|execute_|ctl_ir_we~4_combout & -// (((!\z80_|execute_|ctl_mRead~7_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) - - .dataa(\z80_|execute_|ctl_ir_we~4_combout ), - .datab(\z80_|execute_|ctl_mRead~10_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|execute_|ctl_mRead~7_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~7 .lut_mask = 16'h0777; -defparam \z80_|pin_control_|bus_db_pin_oe~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N4 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~6 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~6_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|execute_|ctl_mRead~6_combout & ((\z80_|execute_|fMRead~1_combout )))) # (!\z80_|execute_|ixy_d~7_combout & (((!\z80_|execute_|ctl_alu_oe~2_combout )) # -// (!\z80_|execute_|ctl_mRead~6_combout ))) - - .dataa(\z80_|execute_|ixy_d~7_combout ), - .datab(\z80_|execute_|ctl_mRead~6_combout ), - .datac(\z80_|execute_|ctl_alu_oe~2_combout ), - .datad(\z80_|execute_|fMRead~1_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~6 .lut_mask = 16'h3715; -defparam \z80_|pin_control_|bus_db_pin_oe~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N2 -cycloneive_lcell_comb \z80_|execute_|fMWrite~9 ( -// Equation(s): -// \z80_|execute_|fMWrite~9_combout = (\z80_|pla_decode_|Equal46~0_combout ) # (((\z80_|ir_|opcode [6] & !\z80_|ir_|opcode [7])) # (!\z80_|execute_|ctl_ir_we~5_combout )) - - .dataa(\z80_|ir_|opcode [6]), - .datab(\z80_|pla_decode_|Equal46~0_combout ), - .datac(\z80_|ir_|opcode [7]), - .datad(\z80_|execute_|ctl_ir_we~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~9 .lut_mask = 16'hCEFF; -defparam \z80_|execute_|fMWrite~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N22 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~8 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~8_combout = (\z80_|execute_|ctl_mWrite~6_combout & (\z80_|execute_|fIOWrite~0_combout & ((\z80_|execute_|fMWrite~2_combout ) # (\z80_|execute_|fMWrite~9_combout )))) # (!\z80_|execute_|ctl_mWrite~6_combout & -// (((\z80_|execute_|fMWrite~2_combout ) # (\z80_|execute_|fMWrite~9_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~6_combout ), - .datab(\z80_|execute_|fIOWrite~0_combout ), - .datac(\z80_|execute_|fMWrite~2_combout ), - .datad(\z80_|execute_|fMWrite~9_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~8 .lut_mask = 16'hDDD0; -defparam \z80_|pin_control_|bus_db_pin_oe~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y18_N0 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~9 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~9_combout = (\z80_|pin_control_|bus_db_pin_oe~8_combout & (\z80_|execute_|fMWrite~11_combout & !\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout )) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~8_combout ), - .datab(\z80_|execute_|fMWrite~11_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~9 .lut_mask = 16'h0808; -defparam \z80_|pin_control_|bus_db_pin_oe~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N26 -cycloneive_lcell_comb \z80_|execute_|fMWrite~8 ( -// Equation(s): -// \z80_|execute_|fMWrite~8_combout = (\z80_|execute_|ctl_state_alu~6_combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # ((\z80_|execute_|ctl_mRead~7_combout ) # (\z80_|execute_|ctl_mRead~9_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~5_combout ), - .datab(\z80_|execute_|ctl_mRead~7_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|ctl_mRead~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~8 .lut_mask = 16'hF0E0; -defparam \z80_|execute_|fMWrite~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N26 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~5 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~5_combout = (\z80_|execute_|ctl_reg_sel_wz~4_combout & (\z80_|execute_|ctl_reg_sel_wz~5_combout & (!\z80_|execute_|fMWrite~8_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sel_wz~4_combout ), - .datab(\z80_|execute_|ctl_reg_sel_wz~5_combout ), - .datac(\z80_|execute_|fMWrite~8_combout ), - .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~8_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~5 .lut_mask = 16'h0800; -defparam \z80_|pin_control_|bus_db_pin_oe~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N20 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~10 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~10_combout = (\z80_|pin_control_|bus_db_pin_oe~7_combout & (\z80_|pin_control_|bus_db_pin_oe~6_combout & (\z80_|pin_control_|bus_db_pin_oe~9_combout & \z80_|pin_control_|bus_db_pin_oe~5_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~7_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~6_combout ), - .datac(\z80_|pin_control_|bus_db_pin_oe~9_combout ), - .datad(\z80_|pin_control_|bus_db_pin_oe~5_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~10 .lut_mask = 16'h8000; -defparam \z80_|pin_control_|bus_db_pin_oe~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N22 -cycloneive_lcell_comb \z80_|execute_|fMWrite~10 ( -// Equation(s): -// \z80_|execute_|fMWrite~10_combout = (\z80_|execute_|ctl_reg_in_hi~2_combout & ((\z80_|pla_decode_|Equal9~1_combout ) # ((\z80_|execute_|ctl_mRead~10_combout )))) # (!\z80_|execute_|ctl_reg_in_hi~2_combout & (\z80_|execute_|ctl_alu_oe~2_combout & -// ((\z80_|pla_decode_|Equal9~1_combout ) # (\z80_|execute_|ctl_mRead~10_combout )))) - - .dataa(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datab(\z80_|pla_decode_|Equal9~1_combout ), - .datac(\z80_|execute_|ctl_alu_oe~2_combout ), - .datad(\z80_|execute_|ctl_mRead~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMWrite~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMWrite~10 .lut_mask = 16'hFAC8; -defparam \z80_|execute_|fMWrite~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N0 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~11 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~11_combout = (\z80_|pin_control_|bus_db_pin_oe~4_combout & (\z80_|pin_control_|bus_db_pin_oe~10_combout & (!\z80_|execute_|fMWrite~10_combout & \z80_|execute_|ctl_bus_inc_oe~28_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~4_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~10_combout ), - .datac(\z80_|execute_|fMWrite~10_combout ), - .datad(\z80_|execute_|ctl_bus_inc_oe~28_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~11 .lut_mask = 16'h0800; -defparam \z80_|pin_control_|bus_db_pin_oe~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y18_N26 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~12 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~12_combout = (\z80_|pin_control_|bus_db_pin_oe~3_combout & (\z80_|pin_control_|bus_db_pin_oe~11_combout & ((!\z80_|execute_|ixy_d~6_combout ) # (!\z80_|pla_decode_|Equal11~0_combout )))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~3_combout ), - .datab(\z80_|pla_decode_|Equal11~0_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|pin_control_|bus_db_pin_oe~11_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~12 .lut_mask = 16'h2A00; -defparam \z80_|pin_control_|bus_db_pin_oe~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y17_N22 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~13 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~13_combout = (\z80_|execute_|ctl_apin_mux~0_combout & (\z80_|pin_control_|bus_db_pin_oe~1_combout & (\z80_|pin_control_|bus_db_pin_oe~12_combout & \z80_|execute_|ctl_inc_cy~37_combout ))) - - .dataa(\z80_|execute_|ctl_apin_mux~0_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~1_combout ), - .datac(\z80_|pin_control_|bus_db_pin_oe~12_combout ), - .datad(\z80_|execute_|ctl_inc_cy~37_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~13 .lut_mask = 16'h8000; -defparam \z80_|pin_control_|bus_db_pin_oe~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N28 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~14 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_oe~14_combout = (\z80_|pin_control_|bus_db_pin_oe~0_combout & (((\z80_|sequencer_|DFFE_T4_ff~q & \z80_|execute_|fIOWrite~5_combout )) # (!\z80_|pin_control_|bus_db_pin_oe~13_combout ))) # -// (!\z80_|pin_control_|bus_db_pin_oe~0_combout & (((\z80_|sequencer_|DFFE_T4_ff~q & \z80_|execute_|fIOWrite~5_combout )))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~0_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~13_combout ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|execute_|fIOWrite~5_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_oe~14 .lut_mask = 16'hF222; -defparam \z80_|pin_control_|bus_db_pin_oe~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N0 -cycloneive_lcell_comb \z80_|clk_delay_|DFF_inst5~feeder ( -// Equation(s): -// \z80_|clk_delay_|DFF_inst5~feeder_combout = \z80_|clk_delay_|SYNTHESIZED_WIRE_7~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ), - .cin(gnd), - .combout(\z80_|clk_delay_|DFF_inst5~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|clk_delay_|DFF_inst5~feeder .lut_mask = 16'hFF00; -defparam \z80_|clk_delay_|DFF_inst5~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X43_Y15_N1 -dffeas \z80_|clk_delay_|DFF_inst5 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|clk_delay_|DFF_inst5~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|clk_delay_|DFF_inst5~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|clk_delay_|DFF_inst5 .is_wysiwyg = "true"; -defparam \z80_|clk_delay_|DFF_inst5 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N22 -cycloneive_lcell_comb \z80_|memory_ifc_|wait_iorqinta~feeder ( -// Equation(s): -// \z80_|memory_ifc_|wait_iorqinta~feeder_combout = \z80_|clk_delay_|DFF_inst5~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|clk_delay_|DFF_inst5~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|wait_iorqinta~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_iorqinta~feeder .lut_mask = 16'hFF00; -defparam \z80_|memory_ifc_|wait_iorqinta~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X43_Y15_N23 -dffeas \z80_|memory_ifc_|wait_iorqinta ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|memory_ifc_|wait_iorqinta~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|wait_iorqinta~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_iorqinta .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|wait_iorqinta .power_up = "low"; -// synopsys translate_on - -// Location: FF_X43_Y15_N13 -dffeas \z80_|memory_ifc_|DFFE_intr_ff3 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|memory_ifc_|wait_iorqinta~q ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_intr_ff3~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_intr_ff3 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_intr_ff3 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N12 -cycloneive_lcell_comb \z80_|memory_ifc_|nIORQ_out~0 ( -// Equation(s): -// \z80_|memory_ifc_|nIORQ_out~0_combout = (\z80_|memory_ifc_|wait_iorqinta~q ) # ((\z80_|memory_ifc_|DFFE_intr_ff3~q ) # (\z80_|memory_ifc_|iorq~0_combout )) - - .dataa(\z80_|memory_ifc_|wait_iorqinta~q ), - .datab(gnd), - .datac(\z80_|memory_ifc_|DFFE_intr_ff3~q ), - .datad(\z80_|memory_ifc_|iorq~0_combout ), - .cin(gnd), - .combout(\z80_|memory_ifc_|nIORQ_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|nIORQ_out~0 .lut_mask = 16'hFFFA; -defparam \z80_|memory_ifc_|nIORQ_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N18 -cycloneive_lcell_comb \Equal2~0 ( -// Equation(s): -// \Equal2~0_combout = (!\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|memory_ifc_|nRD_out~2_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \z80_|memory_ifc_|nIORQ_out~0_combout ))) - - .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), - .datab(\z80_|memory_ifc_|nRD_out~2_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|memory_ifc_|nIORQ_out~0_combout ), - .cin(gnd), - .combout(\Equal2~0_combout ), - .cout()); -// synopsys translate_off -defparam \Equal2~0 .lut_mask = 16'h4000; -defparam \Equal2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N22 -cycloneive_lcell_comb \ExtRamWE~0 ( -// Equation(s): -// \ExtRamWE~0_combout = (\z80_|memory_ifc_|nWR_out~0_combout & (!\z80_|memory_ifc_|nRD_out~2_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|memory_ifc_|nIORQ_out~0_combout ))) - - .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), - .datab(\z80_|memory_ifc_|nRD_out~2_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|memory_ifc_|nIORQ_out~0_combout ), - .cin(gnd), - .combout(\ExtRamWE~0_combout ), - .cout()); -// synopsys translate_off -defparam \ExtRamWE~0 .lut_mask = 16'h0020; -defparam \ExtRamWE~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N18 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[13]~13 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[13]~13_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [13]))) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [13]), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[13]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[13]~13 .lut_mask = 16'hDD88; -defparam \z80_|address_pins_|DFFE_apin_latch[13]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux2~0 ( -// Equation(s): -// \z80_|execute_|ctl_apin_mux2~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|execute_|ctl_apin_mux2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_apin_mux2~0 .lut_mask = 16'h0B0B; -defparam \z80_|execute_|ctl_apin_mux2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N28 -cycloneive_lcell_comb \z80_|pin_control_|bus_ab_pin_we~2 ( -// Equation(s): -// \z80_|pin_control_|bus_ab_pin_we~2_combout = (((\z80_|execute_|fMRead~35_combout ) # (\z80_|execute_|fIORead~3_combout )) # (!\z80_|pin_control_|bus_db_pin_oe~13_combout )) # (!\z80_|sequencer_|DFFE_M1_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|pin_control_|bus_db_pin_oe~13_combout ), - .datac(\z80_|execute_|fMRead~35_combout ), - .datad(\z80_|execute_|fIORead~3_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_ab_pin_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_ab_pin_we~2 .lut_mask = 16'hFFF7; -defparam \z80_|pin_control_|bus_ab_pin_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N2 -cycloneive_lcell_comb \z80_|pin_control_|bus_ab_pin_we~3 ( -// Equation(s): -// \z80_|pin_control_|bus_ab_pin_we~3_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (((!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|pin_control_|bus_ab_pin_we~2_combout )) # (!\z80_|sequencer_|DFFE_M1_ff~q ))) # (!\z80_|sequencer_|DFFE_T3_ff~q & -// (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|pin_control_|bus_ab_pin_we~2_combout )))) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|pin_control_|bus_ab_pin_we~2_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_ab_pin_we~3 .lut_mask = 16'h3B0A; -defparam \z80_|pin_control_|bus_ab_pin_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N19 -dffeas \z80_|address_pins_|DFFE_apin_latch[13] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[13]~13_combout ), - .asdata(\z80_|address_latch_|Q [13]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [13]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[13] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[13] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N0 -cycloneive_lcell_comb \z80_|address_pins_|abus[13]~20 ( -// Equation(s): -// \z80_|address_pins_|abus[13]~20_combout = (\z80_|address_pins_|DFFE_apin_latch [13]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [13]), - .datab(gnd), - .datac(gnd), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\z80_|address_pins_|abus[13]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[13]~20 .lut_mask = 16'hAAFF; -defparam \z80_|address_pins_|abus[13]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N28 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[14]~14 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[14]~14_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|address [14])) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [14]))) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [14]), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[14]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[14]~14 .lut_mask = 16'hDD88; -defparam \z80_|address_pins_|DFFE_apin_latch[14]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N29 -dffeas \z80_|address_pins_|DFFE_apin_latch[14] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[14]~14_combout ), - .asdata(\z80_|address_latch_|Q [14]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [14]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[14] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[14] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N4 -cycloneive_lcell_comb \z80_|address_pins_|abus[14]~23 ( -// Equation(s): -// \z80_|address_pins_|abus[14]~23_combout = (\z80_|address_pins_|DFFE_apin_latch [14]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(gnd), - .datad(\z80_|address_pins_|DFFE_apin_latch [14]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[14]~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[14]~23 .lut_mask = 16'hFF33; -defparam \z80_|address_pins_|abus[14]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N10 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[15]~15 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[15]~15_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [15]))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [15])) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|abusz [15]), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|address [15]), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[15]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[15]~15 .lut_mask = 16'hEE44; -defparam \z80_|address_pins_|DFFE_apin_latch[15]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N11 -dffeas \z80_|address_pins_|DFFE_apin_latch[15] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[15]~15_combout ), - .asdata(\z80_|address_latch_|Q [15]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [15]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[15] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[15] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X23_Y15_N12 -cycloneive_lcell_comb \z80_|address_pins_|abus[15]~22 ( -// Equation(s): -// \z80_|address_pins_|abus[15]~22_combout = (\z80_|address_pins_|DFFE_apin_latch [15]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [15]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_pins_|abus[15]~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[15]~22 .lut_mask = 16'hF3F3; -defparam \z80_|address_pins_|abus[15]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N8 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2] = (\ExtRamWE~0_combout & (\z80_|address_pins_|abus[13]~20_combout & (!\z80_|address_pins_|abus[14]~23_combout & \z80_|address_pins_|abus[15]~22_combout ))) - - .dataa(\ExtRamWE~0_combout ), - .datab(\z80_|address_pins_|abus[13]~20_combout ), - .datac(\z80_|address_pins_|abus[14]~23_combout ), - .datad(\z80_|address_pins_|abus[15]~22_combout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] .lut_mask = 16'h0800; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N22 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\z80_|address_pins_|DFFE_apin_latch [13] & !\z80_|address_pins_|DFFE_apin_latch [14])) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [13]), - .datad(\z80_|address_pins_|DFFE_apin_latch [14]), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 .lut_mask = 16'h00C0; -defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N0 -cycloneive_lcell_comb \z80_|address_pins_|abus[0]~16 ( -// Equation(s): -// \z80_|address_pins_|abus[0]~16_combout = (\z80_|address_pins_|DFFE_apin_latch [0]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [0]), - .datab(gnd), - .datac(gnd), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\z80_|address_pins_|abus[0]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[0]~16 .lut_mask = 16'hAAFF; -defparam \z80_|address_pins_|abus[0]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N28 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[1]~1 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[1]~1_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [1]))) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [1]), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[1]~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[1]~1 .lut_mask = 16'hDD88; -defparam \z80_|address_pins_|DFFE_apin_latch[1]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y17_N29 -dffeas \z80_|address_pins_|DFFE_apin_latch[1] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[1]~1_combout ), - .asdata(\z80_|address_latch_|Q [1]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[1] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y18_N20 -cycloneive_lcell_comb \z80_|address_pins_|abus[1]~25 ( -// Equation(s): -// \z80_|address_pins_|abus[1]~25_combout = (\z80_|address_pins_|DFFE_apin_latch [1]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_pins_|DFFE_apin_latch [1]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[1]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[1]~25 .lut_mask = 16'hFF55; -defparam \z80_|address_pins_|abus[1]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N18 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[2]~2 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[2]~2_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [2])) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|abusz [2]), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[2]~2 .lut_mask = 16'hEE44; -defparam \z80_|address_pins_|DFFE_apin_latch[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y17_N19 -dffeas \z80_|address_pins_|DFFE_apin_latch[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[2]~2_combout ), - .asdata(\z80_|address_latch_|Q [2]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[2] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y18_N26 -cycloneive_lcell_comb \z80_|address_pins_|abus[2]~26 ( -// Equation(s): -// \z80_|address_pins_|abus[2]~26_combout = (\z80_|address_pins_|DFFE_apin_latch [2]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|address_pins_|DFFE_apin_latch [2]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[2]~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[2]~26 .lut_mask = 16'hFF0F; -defparam \z80_|address_pins_|abus[2]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N0 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[3]~3 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[3]~3_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [3])) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|abusz [3]), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[3]~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[3]~3 .lut_mask = 16'hEE44; -defparam \z80_|address_pins_|DFFE_apin_latch[3]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y17_N1 -dffeas \z80_|address_pins_|DFFE_apin_latch[3] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[3]~3_combout ), - .asdata(\z80_|address_latch_|Q [3]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [3]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[3] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y18_N12 -cycloneive_lcell_comb \z80_|address_pins_|abus[3]~27 ( -// Equation(s): -// \z80_|address_pins_|abus[3]~27_combout = (\z80_|address_pins_|DFFE_apin_latch [3]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|address_pins_|DFFE_apin_latch [3]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[3]~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[3]~27 .lut_mask = 16'hFF0F; -defparam \z80_|address_pins_|abus[3]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N30 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[4]~4 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[4]~4_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [4])) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|abusz [4]), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[4]~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[4]~4 .lut_mask = 16'hEE44; -defparam \z80_|address_pins_|DFFE_apin_latch[4]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y17_N31 -dffeas \z80_|address_pins_|DFFE_apin_latch[4] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[4]~4_combout ), - .asdata(\z80_|address_latch_|Q [4]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[4] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y18_N2 -cycloneive_lcell_comb \z80_|address_pins_|abus[4]~28 ( -// Equation(s): -// \z80_|address_pins_|abus[4]~28_combout = (\z80_|address_pins_|DFFE_apin_latch [4]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|address_pins_|DFFE_apin_latch [4]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[4]~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[4]~28 .lut_mask = 16'hFF0F; -defparam \z80_|address_pins_|abus[4]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N12 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[5]~5 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[5]~5_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [5])) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|abusz [5]), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[5]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[5]~5 .lut_mask = 16'hEE44; -defparam \z80_|address_pins_|DFFE_apin_latch[5]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y16_N13 -dffeas \z80_|address_pins_|DFFE_apin_latch[5] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[5]~5_combout ), - .asdata(\z80_|address_latch_|Q [5]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[5] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y17_N20 -cycloneive_lcell_comb \z80_|address_pins_|abus[5]~29 ( -// Equation(s): -// \z80_|address_pins_|abus[5]~29_combout = (\z80_|address_pins_|DFFE_apin_latch [5]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [5]), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_pins_|abus[5]~29_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[5]~29 .lut_mask = 16'hF3F3; -defparam \z80_|address_pins_|abus[5]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N10 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[6]~6 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[6]~6_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [6]))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [6])) - - .dataa(\z80_|address_latch_|abusz [6]), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), - .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[6]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[6]~6 .lut_mask = 16'hCCAA; -defparam \z80_|address_pins_|DFFE_apin_latch[6]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y16_N11 -dffeas \z80_|address_pins_|DFFE_apin_latch[6] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[6]~6_combout ), - .asdata(\z80_|address_latch_|Q [6]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[6] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y18_N28 -cycloneive_lcell_comb \z80_|address_pins_|abus[6]~30 ( -// Equation(s): -// \z80_|address_pins_|abus[6]~30_combout = (\z80_|address_pins_|DFFE_apin_latch [6]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|address_pins_|DFFE_apin_latch [6]), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|address_pins_|abus[6]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[6]~30 .lut_mask = 16'hCFCF; -defparam \z80_|address_pins_|abus[6]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N30 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[7]~7 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[7]~7_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [7])) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|abusz [7]), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[7]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[7]~7 .lut_mask = 16'hEE44; -defparam \z80_|address_pins_|DFFE_apin_latch[7]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y16_N31 -dffeas \z80_|address_pins_|DFFE_apin_latch[7] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[7]~7_combout ), - .asdata(\z80_|address_latch_|Q [7]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [7]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[7] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y18_N22 -cycloneive_lcell_comb \z80_|address_pins_|abus[7]~31 ( -// Equation(s): -// \z80_|address_pins_|abus[7]~31_combout = (\z80_|address_pins_|DFFE_apin_latch [7]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|address_pins_|DFFE_apin_latch [7]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[7]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[7]~31 .lut_mask = 16'hFF0F; -defparam \z80_|address_pins_|abus[7]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y16_N20 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[8]~8 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[8]~8_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [8])) - - .dataa(\z80_|address_latch_|abusz [8]), - .datab(\z80_|execute_|ctl_apin_mux~2_combout ), - .datac(gnd), - .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[8]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[8]~8 .lut_mask = 16'hEE22; -defparam \z80_|address_pins_|DFFE_apin_latch[8]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y16_N21 -dffeas \z80_|address_pins_|DFFE_apin_latch[8] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[8]~8_combout ), - .asdata(\z80_|address_latch_|Q [8]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [8]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[8] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N30 -cycloneive_lcell_comb \z80_|address_pins_|abus[8]~18 ( -// Equation(s): -// \z80_|address_pins_|abus[8]~18_combout = (\z80_|address_pins_|DFFE_apin_latch [8]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|address_pins_|DFFE_apin_latch [8]), - .datac(gnd), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\z80_|address_pins_|abus[8]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[8]~18 .lut_mask = 16'hCCFF; -defparam \z80_|address_pins_|abus[8]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N16 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[9]~9 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[9]~9_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [9]))) - - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), - .datac(gnd), - .datad(\z80_|address_latch_|abusz [9]), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[9]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[9]~9 .lut_mask = 16'hDD88; -defparam \z80_|address_pins_|DFFE_apin_latch[9]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N17 -dffeas \z80_|address_pins_|DFFE_apin_latch[9] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[9]~9_combout ), - .asdata(\z80_|address_latch_|Q [9]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [9]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[9] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[9] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y18_N4 -cycloneive_lcell_comb \z80_|address_pins_|abus[9]~17 ( -// Equation(s): -// \z80_|address_pins_|abus[9]~17_combout = (\z80_|address_pins_|DFFE_apin_latch [9]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|address_pins_|DFFE_apin_latch [9]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[9]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[9]~17 .lut_mask = 16'hFF0F; -defparam \z80_|address_pins_|abus[9]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N24 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[10]~10 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[10]~10_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [10]))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), - .datab(\z80_|address_latch_|abusz [10]), - .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[10]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[10]~10 .lut_mask = 16'hAACC; -defparam \z80_|address_pins_|DFFE_apin_latch[10]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N25 -dffeas \z80_|address_pins_|DFFE_apin_latch[10] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[10]~10_combout ), - .asdata(\z80_|address_latch_|Q [10]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [10]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[10] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[10] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N24 -cycloneive_lcell_comb \z80_|address_pins_|abus[10]~24 ( -// Equation(s): -// \z80_|address_pins_|abus[10]~24_combout = (\z80_|address_pins_|DFFE_apin_latch [10]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|address_pins_|DFFE_apin_latch [10]), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\z80_|address_pins_|abus[10]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[10]~24 .lut_mask = 16'hF0FF; -defparam \z80_|address_pins_|abus[10]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y16_N6 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[11]~11 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[11]~11_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|address [11])) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [11]))) - - .dataa(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), - .datab(\z80_|address_latch_|abusz [11]), - .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[11]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[11]~11 .lut_mask = 16'hAACC; -defparam \z80_|address_pins_|DFFE_apin_latch[11]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y16_N7 -dffeas \z80_|address_pins_|DFFE_apin_latch[11] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[11]~11_combout ), - .asdata(\z80_|address_latch_|Q [11]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [11]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[11] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[11] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N8 -cycloneive_lcell_comb \z80_|address_pins_|abus[11]~19 ( -// Equation(s): -// \z80_|address_pins_|abus[11]~19_combout = (\z80_|address_pins_|DFFE_apin_latch [11]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [11]), - .datab(gnd), - .datac(gnd), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\z80_|address_pins_|abus[11]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[11]~19 .lut_mask = 16'hAAFF; -defparam \z80_|address_pins_|abus[11]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y16_N16 -cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[12]~12 ( -// Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[12]~12_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [12])) - - .dataa(\z80_|address_latch_|abusz [12]), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_apin_mux~2_combout ), - .cin(gnd), - .combout(\z80_|address_pins_|DFFE_apin_latch[12]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[12]~12 .lut_mask = 16'hCCAA; -defparam \z80_|address_pins_|DFFE_apin_latch[12]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y16_N17 -dffeas \z80_|address_pins_|DFFE_apin_latch[12] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|address_pins_|DFFE_apin_latch[12]~12_combout ), - .asdata(\z80_|address_latch_|Q [12]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|address_pins_|DFFE_apin_latch [12]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[12] .is_wysiwyg = "true"; -defparam \z80_|address_pins_|DFFE_apin_latch[12] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y18_N30 -cycloneive_lcell_comb \z80_|address_pins_|abus[12]~21 ( -// Equation(s): -// \z80_|address_pins_|abus[12]~21_combout = (\z80_|address_pins_|DFFE_apin_latch [12]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_pins_|DFFE_apin_latch [12]), - .cin(gnd), - .combout(\z80_|address_pins_|abus[12]~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|address_pins_|abus[12]~21 .lut_mask = 16'hFF55; -defparam \z80_|address_pins_|abus[12]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y11_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a14 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~101_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: FF_X32_Y14_N31 -dffeas \ram1|altsyncram_component|auto_generated|address_reg_a[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|address_pins_|abus[13]~20_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram1|altsyncram_component|auto_generated|address_reg_a [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true"; -defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X32_Y14_N1 -dffeas \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ram1|altsyncram_component|auto_generated|address_reg_a [0]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true"; -defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N12 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2] = (\ExtRamWE~0_combout & (!\z80_|address_pins_|abus[13]~20_combout & (!\z80_|address_pins_|abus[14]~23_combout & \z80_|address_pins_|abus[15]~22_combout ))) - - .dataa(\ExtRamWE~0_combout ), - .datab(\z80_|address_pins_|abus[13]~20_combout ), - .datac(\z80_|address_pins_|abus[14]~23_combout ), - .datad(\z80_|address_pins_|abus[15]~22_combout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] .lut_mask = 16'h0200; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N18 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (!\z80_|address_pins_|DFFE_apin_latch [13] & !\z80_|address_pins_|DFFE_apin_latch [14])) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [13]), - .datad(\z80_|address_pins_|DFFE_apin_latch [14]), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 .lut_mask = 16'h000C; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y10_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a6 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~101_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; -// synopsys translate_on - -// Location: FF_X29_Y14_N5 -dffeas \ram1|altsyncram_component|auto_generated|address_reg_a[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|address_pins_|abus[14]~23_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram1|altsyncram_component|auto_generated|address_reg_a [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1] .is_wysiwyg = "true"; -defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y14_N21 -dffeas \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ram1|altsyncram_component|auto_generated|address_reg_a [1]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] .is_wysiwyg = "true"; -defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N24 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2] = (\ExtRamWE~0_combout & (!\z80_|address_pins_|abus[13]~20_combout & (\z80_|address_pins_|abus[14]~23_combout & \z80_|address_pins_|abus[15]~22_combout ))) - - .dataa(\ExtRamWE~0_combout ), - .datab(\z80_|address_pins_|abus[13]~20_combout ), - .datac(\z80_|address_pins_|abus[14]~23_combout ), - .datad(\z80_|address_pins_|abus[15]~22_combout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] .lut_mask = 16'h2000; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N26 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (!\z80_|address_pins_|DFFE_apin_latch [13] & \z80_|address_pins_|DFFE_apin_latch [14])) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [13]), - .datad(\z80_|address_pins_|DFFE_apin_latch [14]), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 .lut_mask = 16'h0C00; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y10_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a22 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~101_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_first_bit_number = 6; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N10 -cycloneive_lcell_comb \D[6]~90 ( -// Equation(s): -// \D[6]~90_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ) # (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout & ((!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ), - .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .cin(gnd), - .combout(\D[6]~90_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~90 .lut_mask = 16'hCCE2; -defparam \D[6]~90 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N20 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2] = (\ExtRamWE~0_combout & (\z80_|address_pins_|abus[13]~20_combout & (\z80_|address_pins_|abus[14]~23_combout & \z80_|address_pins_|abus[15]~22_combout ))) - - .dataa(\ExtRamWE~0_combout ), - .datab(\z80_|address_pins_|abus[13]~20_combout ), - .datac(\z80_|address_pins_|abus[14]~23_combout ), - .datad(\z80_|address_pins_|abus[15]~22_combout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] .lut_mask = 16'h8000; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N6 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout = ((\z80_|address_pins_|DFFE_apin_latch [13] & \z80_|address_pins_|DFFE_apin_latch [14])) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [13]), - .datad(\z80_|address_pins_|DFFE_apin_latch [14]), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 .lut_mask = 16'hF333; -defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y6_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a30 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~101_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_first_bit_number = 6; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N16 -cycloneive_lcell_comb \D[6]~91 ( -// Equation(s): -// \D[6]~91_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[6]~90_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ))) # (!\D[6]~90_combout & -// (\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[6]~90_combout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\D[6]~90_combout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ), - .cin(gnd), - .combout(\D[6]~91_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~91 .lut_mask = 16'hF838; -defparam \D[6]~91 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N2 -cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0 ( -// Equation(s): -// \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout = (\ExtRamWE~0_combout & (!\z80_|address_pins_|abus[13]~20_combout & (\z80_|address_pins_|abus[14]~23_combout & !\z80_|address_pins_|abus[15]~22_combout ))) - - .dataa(\ExtRamWE~0_combout ), - .datab(\z80_|address_pins_|abus[13]~20_combout ), - .datac(\z80_|address_pins_|abus[14]~23_combout ), - .datad(\z80_|address_pins_|abus[15]~22_combout ), - .cin(gnd), - .combout(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0 .lut_mask = 16'h0020; -defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: CLKCTRL_G15 -cycloneive_clkctrl \CLOCK_50~inputclkctrl ( - .ena(vcc), - .inclk({vcc,vcc,vcc,\CLOCK_50~input_o }), - .clkselect(2'b00), - .devclrn(devclrn), - .devpor(devpor), - .outclk(\CLOCK_50~inputclkctrl_outclk )); -// synopsys translate_off -defparam \CLOCK_50~inputclkctrl .clock_type = "global clock"; -defparam \CLOCK_50~inputclkctrl .ena_register_mode = "none"; -// synopsys translate_on - -// Location: LCCOMB_X5_Y24_N16 -cycloneive_lcell_comb \~GND ( -// Equation(s): -// \~GND~combout = GND - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(gnd), - .cin(gnd), - .combout(\~GND~combout ), - .cout()); -// synopsys translate_off -defparam \~GND .lut_mask = 16'h0000; -defparam \~GND .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N20 -cycloneive_lcell_comb \ula_|video_|vram_address[0]~feeder ( -// Equation(s): -// \ula_|video_|vram_address[0]~feeder_combout = \ula_|video_|vga_hc [4] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|vga_hc [4]), - .cin(gnd), - .combout(\ula_|video_|vram_address[0]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address[0]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|vram_address[0]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N4 -cycloneive_lcell_comb \ula_|video_|vram_address~0 ( -// Equation(s): -// \ula_|video_|vram_address~0_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [2] $ (\ula_|video_|vga_hc [1])))) - - .dataa(\ula_|video_|vga_hc [2]), - .datab(\ula_|video_|vga_hc [3]), - .datac(\ula_|video_|vga_hc [1]), - .datad(\ula_|video_|vga_hc [0]), - .cin(gnd), - .combout(\ula_|video_|vram_address~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address~0 .lut_mask = 16'h0048; -defparam \ula_|video_|vram_address~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y33_N21 -dffeas \ula_|video_|vram_address[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vram_address[0]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[0] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X34_Y33_N19 -dffeas \ula_|video_|vram_address[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|vga_hc [5]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[1] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N0 -cycloneive_lcell_comb \ula_|video_|vram_address[2]~4 ( -// Equation(s): -// \ula_|video_|vram_address[2]~4_combout = !\ula_|video_|vga_hc [6] - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|video_|vga_hc [6]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|video_|vram_address[2]~4_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address[2]~4 .lut_mask = 16'h0F0F; -defparam \ula_|video_|vram_address[2]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y33_N1 -dffeas \ula_|video_|vram_address[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vram_address[2]~4_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[2] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N26 -cycloneive_lcell_comb \ula_|video_|Add3~0 ( -// Equation(s): -// \ula_|video_|Add3~0_combout = \ula_|video_|vga_hc [6] $ (\ula_|video_|vga_hc [7]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|video_|vga_hc [6]), - .datad(\ula_|video_|vga_hc [7]), - .cin(gnd), - .combout(\ula_|video_|Add3~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Add3~0 .lut_mask = 16'h0FF0; -defparam \ula_|video_|Add3~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y33_N27 -dffeas \ula_|video_|vram_address[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Add3~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[3] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N28 -cycloneive_lcell_comb \ula_|video_|Add3~1 ( -// Equation(s): -// \ula_|video_|Add3~1_combout = \ula_|video_|vga_hc [8] $ (((!\ula_|video_|vga_hc [7]) # (!\ula_|video_|vga_hc [6]))) - - .dataa(\ula_|video_|vga_hc [6]), - .datab(gnd), - .datac(\ula_|video_|vga_hc [8]), - .datad(\ula_|video_|vga_hc [7]), - .cin(gnd), - .combout(\ula_|video_|Add3~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Add3~1 .lut_mask = 16'hA50F; -defparam \ula_|video_|Add3~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y33_N29 -dffeas \ula_|video_|vram_address[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Add3~1_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[4] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N2 -cycloneive_lcell_comb \ula_|video_|Add4~0 ( -// Equation(s): -// \ula_|video_|Add4~0_combout = (\ula_|video_|vga_vc [0] & (\ula_|video_|vga_vc [1] $ (VCC))) # (!\ula_|video_|vga_vc [0] & (\ula_|video_|vga_vc [1] & VCC)) -// \ula_|video_|Add4~1 = CARRY((\ula_|video_|vga_vc [0] & \ula_|video_|vga_vc [1])) - - .dataa(\ula_|video_|vga_vc [0]), - .datab(\ula_|video_|vga_vc [1]), - .datac(gnd), - .datad(vcc), - .cin(gnd), - .combout(\ula_|video_|Add4~0_combout ), - .cout(\ula_|video_|Add4~1 )); -// synopsys translate_off -defparam \ula_|video_|Add4~0 .lut_mask = 16'h6688; -defparam \ula_|video_|Add4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N4 -cycloneive_lcell_comb \ula_|video_|Add4~2 ( -// Equation(s): -// \ula_|video_|Add4~2_combout = (\ula_|video_|vga_vc [2] & (\ula_|video_|Add4~1 & VCC)) # (!\ula_|video_|vga_vc [2] & (!\ula_|video_|Add4~1 )) -// \ula_|video_|Add4~3 = CARRY((!\ula_|video_|vga_vc [2] & !\ula_|video_|Add4~1 )) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [2]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~1 ), - .combout(\ula_|video_|Add4~2_combout ), - .cout(\ula_|video_|Add4~3 )); -// synopsys translate_off -defparam \ula_|video_|Add4~2 .lut_mask = 16'hC303; -defparam \ula_|video_|Add4~2 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N6 -cycloneive_lcell_comb \ula_|video_|Add4~4 ( -// Equation(s): -// \ula_|video_|Add4~4_combout = (\ula_|video_|vga_vc [3] & ((GND) # (!\ula_|video_|Add4~3 ))) # (!\ula_|video_|vga_vc [3] & (\ula_|video_|Add4~3 $ (GND))) -// \ula_|video_|Add4~5 = CARRY((\ula_|video_|vga_vc [3]) # (!\ula_|video_|Add4~3 )) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [3]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~3 ), - .combout(\ula_|video_|Add4~4_combout ), - .cout(\ula_|video_|Add4~5 )); -// synopsys translate_off -defparam \ula_|video_|Add4~4 .lut_mask = 16'h3CCF; -defparam \ula_|video_|Add4~4 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N8 -cycloneive_lcell_comb \ula_|video_|Add4~6 ( -// Equation(s): -// \ula_|video_|Add4~6_combout = (\ula_|video_|vga_vc [4] & (!\ula_|video_|Add4~5 )) # (!\ula_|video_|vga_vc [4] & ((\ula_|video_|Add4~5 ) # (GND))) -// \ula_|video_|Add4~7 = CARRY((!\ula_|video_|Add4~5 ) # (!\ula_|video_|vga_vc [4])) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [4]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~5 ), - .combout(\ula_|video_|Add4~6_combout ), - .cout(\ula_|video_|Add4~7 )); -// synopsys translate_off -defparam \ula_|video_|Add4~6 .lut_mask = 16'h3C3F; -defparam \ula_|video_|Add4~6 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X34_Y33_N9 -dffeas \ula_|video_|vram_address[5] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Add4~6_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[5] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N10 -cycloneive_lcell_comb \ula_|video_|Add4~8 ( -// Equation(s): -// \ula_|video_|Add4~8_combout = (\ula_|video_|vga_vc [5] & ((GND) # (!\ula_|video_|Add4~7 ))) # (!\ula_|video_|vga_vc [5] & (\ula_|video_|Add4~7 $ (GND))) -// \ula_|video_|Add4~9 = CARRY((\ula_|video_|vga_vc [5]) # (!\ula_|video_|Add4~7 )) - - .dataa(\ula_|video_|vga_vc [5]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~7 ), - .combout(\ula_|video_|Add4~8_combout ), - .cout(\ula_|video_|Add4~9 )); -// synopsys translate_off -defparam \ula_|video_|Add4~8 .lut_mask = 16'h5AAF; -defparam \ula_|video_|Add4~8 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X34_Y33_N11 -dffeas \ula_|video_|vram_address[6] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Add4~8_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[6] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N12 -cycloneive_lcell_comb \ula_|video_|Add4~10 ( -// Equation(s): -// \ula_|video_|Add4~10_combout = (\ula_|video_|vga_vc [6] & (!\ula_|video_|Add4~9 )) # (!\ula_|video_|vga_vc [6] & ((\ula_|video_|Add4~9 ) # (GND))) -// \ula_|video_|Add4~11 = CARRY((!\ula_|video_|Add4~9 ) # (!\ula_|video_|vga_vc [6])) - - .dataa(\ula_|video_|vga_vc [6]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~9 ), - .combout(\ula_|video_|Add4~10_combout ), - .cout(\ula_|video_|Add4~11 )); -// synopsys translate_off -defparam \ula_|video_|Add4~10 .lut_mask = 16'h5A5F; -defparam \ula_|video_|Add4~10 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X34_Y33_N13 -dffeas \ula_|video_|vram_address[7] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Add4~10_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[7] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N14 -cycloneive_lcell_comb \ula_|video_|Add4~12 ( -// Equation(s): -// \ula_|video_|Add4~12_combout = (\ula_|video_|vga_vc [7] & ((GND) # (!\ula_|video_|Add4~11 ))) # (!\ula_|video_|vga_vc [7] & (\ula_|video_|Add4~11 $ (GND))) -// \ula_|video_|Add4~13 = CARRY((\ula_|video_|vga_vc [7]) # (!\ula_|video_|Add4~11 )) - - .dataa(gnd), - .datab(\ula_|video_|vga_vc [7]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|video_|Add4~11 ), - .combout(\ula_|video_|Add4~12_combout ), - .cout(\ula_|video_|Add4~13 )); -// synopsys translate_off -defparam \ula_|video_|Add4~12 .lut_mask = 16'h3CCF; -defparam \ula_|video_|Add4~12 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N22 -cycloneive_lcell_comb \ula_|video_|Selector6~0 ( -// Equation(s): -// \ula_|video_|Selector6~0_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|Add4~12_combout )) # (!\ula_|video_|vga_hc [2] & ((\ula_|video_|Add4~0_combout ))) - - .dataa(gnd), - .datab(\ula_|video_|Add4~12_combout ), - .datac(\ula_|video_|Add4~0_combout ), - .datad(\ula_|video_|vga_hc [2]), - .cin(gnd), - .combout(\ula_|video_|Selector6~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Selector6~0 .lut_mask = 16'hCCF0; -defparam \ula_|video_|Selector6~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N14 -cycloneive_lcell_comb \ula_|video_|vram_address[9]~1 ( -// Equation(s): -// \ula_|video_|vram_address[9]~1_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [2] $ (\ula_|video_|vga_hc [1])))) - - .dataa(\ula_|video_|vga_hc [2]), - .datab(\ula_|video_|vga_hc [3]), - .datac(\ula_|video_|vga_hc [1]), - .datad(\ula_|video_|vga_hc [0]), - .cin(gnd), - .combout(\ula_|video_|vram_address[9]~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address[9]~1 .lut_mask = 16'h0048; -defparam \ula_|video_|vram_address[9]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y31_N23 -dffeas \ula_|video_|vram_address[8] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Selector6~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address[9]~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [8]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[8] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y33_N16 -cycloneive_lcell_comb \ula_|video_|Add4~14 ( -// Equation(s): -// \ula_|video_|Add4~14_combout = \ula_|video_|Add4~13 $ (!\ula_|video_|vga_vc [8]) - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|vga_vc [8]), - .cin(\ula_|video_|Add4~13 ), - .combout(\ula_|video_|Add4~14_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Add4~14 .lut_mask = 16'hF00F; -defparam \ula_|video_|Add4~14 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N20 -cycloneive_lcell_comb \ula_|video_|Selector5~0 ( -// Equation(s): -// \ula_|video_|Selector5~0_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|Add4~14_combout )) # (!\ula_|video_|vga_hc [2] & ((\ula_|video_|Add4~2_combout ))) - - .dataa(\ula_|video_|Add4~14_combout ), - .datab(gnd), - .datac(\ula_|video_|Add4~2_combout ), - .datad(\ula_|video_|vga_hc [2]), - .cin(gnd), - .combout(\ula_|video_|Selector5~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Selector5~0 .lut_mask = 16'hAAF0; -defparam \ula_|video_|Selector5~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y31_N21 -dffeas \ula_|video_|vram_address[9] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Selector5~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address[9]~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [9]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[9] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[9] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N28 -cycloneive_lcell_comb \ula_|video_|vram_address[10]~2 ( -// Equation(s): -// \ula_|video_|vram_address[10]~2_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [2] $ (\ula_|video_|vga_hc [1])))) - - .dataa(\ula_|video_|vga_hc [2]), - .datab(\ula_|video_|vga_hc [3]), - .datac(\ula_|video_|vga_hc [1]), - .datad(\ula_|video_|vga_hc [0]), - .cin(gnd), - .combout(\ula_|video_|vram_address[10]~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address[10]~2 .lut_mask = 16'h0048; -defparam \ula_|video_|vram_address[10]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N30 -cycloneive_lcell_comb \ula_|video_|vram_address[10]~3 ( -// Equation(s): -// \ula_|video_|vram_address[10]~3_combout = (\ula_|video_|vram_address[10]~2_combout & (\ula_|video_|Add4~4_combout & (\ula_|video_|vga_hc [1]))) # (!\ula_|video_|vram_address[10]~2_combout & (((\ula_|video_|vram_address [10])))) - - .dataa(\ula_|video_|Add4~4_combout ), - .datab(\ula_|video_|vga_hc [1]), - .datac(\ula_|video_|vram_address [10]), - .datad(\ula_|video_|vram_address[10]~2_combout ), - .cin(gnd), - .combout(\ula_|video_|vram_address[10]~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|vram_address[10]~3 .lut_mask = 16'h88F0; -defparam \ula_|video_|vram_address[10]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y31_N31 -dffeas \ula_|video_|vram_address[10] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|vram_address[10]~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [10]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[10] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[10] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N16 -cycloneive_lcell_comb \ula_|video_|Selector3~0 ( -// Equation(s): -// \ula_|video_|Selector3~0_combout = (\ula_|video_|Add4~12_combout ) # (\ula_|video_|vga_hc [2]) - - .dataa(gnd), - .datab(\ula_|video_|Add4~12_combout ), - .datac(gnd), - .datad(\ula_|video_|vga_hc [2]), - .cin(gnd), - .combout(\ula_|video_|Selector3~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Selector3~0 .lut_mask = 16'hFFCC; -defparam \ula_|video_|Selector3~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y31_N17 -dffeas \ula_|video_|vram_address[11] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Selector3~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address[9]~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [11]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[11] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[11] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N26 -cycloneive_lcell_comb \ula_|video_|Selector2~0 ( -// Equation(s): -// \ula_|video_|Selector2~0_combout = (\ula_|video_|Add4~14_combout ) # (\ula_|video_|vga_hc [2]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|video_|Add4~14_combout ), - .datad(\ula_|video_|vga_hc [2]), - .cin(gnd), - .combout(\ula_|video_|Selector2~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Selector2~0 .lut_mask = 16'hFFF0; -defparam \ula_|video_|Selector2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y31_N27 -dffeas \ula_|video_|vram_address[12] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|Selector2~0_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|vram_address[9]~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|vram_address [12]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|vram_address[12] .is_wysiwyg = "true"; -defparam \ula_|video_|vram_address[12] .power_up = "low"; -// synopsys translate_on - -// Location: M9K_X33_Y27_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a6 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~101_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_first_bit_number = 6; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFFFFFEBFFFFFFFFFFFFFFFFFFFFFFFBFFFFFFFFFFFFFFFFFDFFFFFFFFFFFFFBFFFFFFFFFEFFFFFFFDFFFFFFFFFFFFFEFFFFFFFDF8FFFFFFF9FFFFFFFFFFFFFFFF3FFFFFFE7FFFFFFFFFFFFFFFF; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000380001887600094C977486989000000000000000000000000FFFFFFFFC0810205C00018C36DC09CF97749EDCD00000000000000000000000000000001FFFFFFFDC004000B6D028BF17749ED8100000000000000000000000000000001BF7EFDF9400404A96D8289B57549FFC10000000000000000000000003F7EFDF90000000140041EB16D8298357DC9F7410000000000000000000000007FFFFFFD8000000340043AB160021E757DC9134100000000000000000000000040810207BFFFFFFF5FE430497702760D60099349000000000000000000000000408102073FFFFFFD5FE40E49774240C96009735D; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h5FE8334948F827C15FF88F8169A80ECB609EAD417A698FC178F33E8171F72A915FE836E948F807C95FF88F81E9A80FC7639E1FC17B2BBEC170730F8D70F7B0C1400826E548B807C95FF88F95E8280FCB63C6BCC17B3B3FC171AB3E81708734C1400826ED58F8258159F88B8168280FC161629DC17A3B3F41738B3F8150AF16E9400826ED581805C151D88A8160682FC1422297C17A2A39C162FB378550CF10A1400826ED58182581D1580B8761EC2FC14232B7C179AA39C5627B7781D0CF10D3400826E158182D81F0488A4B61EC0DC143789FC17BBB39C1610B7F81D45F11D34008A7E958080D01F0088A4160B42DD143689FC17B9B398561837F81D41702B1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h50DF086350368F0151C688016801460157EDE81148F310013FFFFFFF40810103D2D70D4B50168F0141D6C8116C01462153EDA90148F31D01BFFFFFFF40810107D2D7296354D68501403EC0016C01482173FDA08148F11F01800000037FFFFFFD4297893154DE81054022D2116C014D6153FCA00148D10F01000000013F7EFEF9429F810150CEC10143E042016C014C09537DA00148D11F01BF7EFEF900000001469F833150168D0543E04A116F014DA15379B181C8511F03FFFFFFFD00000001449AAB2155368D01482046016F416CA15079B001C8513E03C0810105FFFFFFFF403A8B0155C685014800461167476CA15039B08180413E0500000007FFFFFFFF; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N22 -cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder ( -// Equation(s): -// \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout = \z80_|address_pins_|abus[13]~20_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|address_pins_|abus[13]~20_combout ), - .cin(gnd), - .combout(\ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder .lut_mask = 16'hFF00; -defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y14_N23 -dffeas \ram0|altsyncram_component|auto_generated|address_reg_a[0] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram0|altsyncram_component|auto_generated|address_reg_a [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true"; -defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X30_Y14_N1 -dffeas \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(gnd), - .asdata(\ram0|altsyncram_component|auto_generated|address_reg_a [0]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true"; -defparam \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N10 -cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1 ( -// Equation(s): -// \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout = (\ExtRamWE~0_combout & (\z80_|address_pins_|abus[13]~20_combout & (\z80_|address_pins_|abus[14]~23_combout & !\z80_|address_pins_|abus[15]~22_combout ))) - - .dataa(\ExtRamWE~0_combout ), - .datab(\z80_|address_pins_|abus[13]~20_combout ), - .datac(\z80_|address_pins_|abus[14]~23_combout ), - .datad(\z80_|address_pins_|abus[15]~22_combout ), - .cin(gnd), - .combout(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .cout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1 .lut_mask = 16'h0080; -defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y25_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a14 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(gnd), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[6]~101_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_first_bit_number = 6; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y33_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a14 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h4200420000441C443C0C3C00480018FC387C7C000000007E180038300000204880084204004204423E1E3E02247E3C7E3C7E7E7E7E30007E3C7E7E7E3C7E7C3C0400000000000C34023C2E302464003C00000000000000000020460024000000FF991E65536D2D8D9C9B4DB081C83A5A881B0DFDE2D72DF0FA08FCD6F664173D989098D02025E0F6043B4B9080F4923880C3A3B02D269E730C3DCC423386DCB98B4AD0C5C8D6119602E5121008325B7457090E914F4876EC8A18C664210A4C2392C7658400073421047C75FBE7BE73FDFFF05FEE07BF8AEF7F1378B359E8C61F8F692C2218C98A4A8748531986E7C770D984E0000C02060C000C0DF50F68A580; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h0100046606572583002086010800054C0F2DE8371AC0000A9003E024840C7C0806F6612D770080980A40D293FEC069F16CB2164CA033C539F69B37741AEF1CE3662FF5DF9CB107BB23A39EF7B95E7372200448DBDC18F9C0DE0EF379BF49480657781E91788044213E091339886F337D0612CA646CD48FC58EE77EDD7ECEC466C744FD00E1A7F9E9FBFE4777FD50ABD11F0E57FF4808802282200888A20AA88000000008800AC11D556264251ECFA68C056FBCCB040C614A6850222300D2F6FF59F878FCF5689FCFEF34BFD52FA2422A56A3C113409F7813007F8D6B5F80FE9D7FB1E62675F7C2CBE01032DCA16BADC570C1CBF7ECBC4E7E6C54A5D4550BE1A8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'hE33CB578DEBFAFAEDFD530DE8FA1992072F31B116644B18C72F9F44116C79ADF2F3982C7BE09AD4A32196807648A2495ADF98FD2B16CC096A5E25F5BC811C953CEC3000F432029B3FE3F211712944CA54D1940F193204C199C9F49666CC11B38C23B9D130CA49818913D3A2C1FBF71C5B0C774336F903C677D976189D98CA127AAAD6B6AF36195DA637C6EFA3E36E8FE97FA02EC26EB46198AD8DAD8C11260AF499D7BD86619EE5574CD27C80D39F71E653FDCF1B366737233CBB98D1E7B330F7DCCFC5939C4EC79CF0E1CD43BA7AFC716900A21BDB9DD0FCC7ECE1063238407C7E1B221EA10E38F64EF31CEBF3368E1C712BB1B33781134CFE54C2123349A6E; -defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h5F9CB25A3631964C20007FF5754FC631A97D4F93986C30CF24394625658DE9A7C228A2050470925E29A35D8D06242712CD25C9241898204D85A710947C802013E1265727652C8F0C422BA8C28A0FBB893B0881E00403DDD8843B2D8EB929D0D8CB76E03779E019E2C4E4028219C38C202C9384E0D24E569C2E4D4D60B670CE37414D536A41D144B6C4624A2B00366D8CF6734A4A2DC465B308462CCBD1BF9CB863FC93EDB2CA5DC61B01639318985C88F01680E307C42311C0124700B28BF9B4FF7CCCEFE1996DE3ED6D8CFBF1871BD98EE7646242664EB2E338BD009838637124C921BB3332DC66D9C1706B6C48C3129639A3BA4088EDB496EDBBBFC2CC40B6; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N2 -cycloneive_lcell_comb \D[6]~87 ( -// Equation(s): -// \D[6]~87_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))) # (!\z80_|address_pins_|abus[14]~23_combout -// & (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout )))) - - .dataa(\z80_|address_pins_|abus[14]~23_combout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout ), - .datad(\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ), - .cin(gnd), - .combout(\D[6]~87_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~87 .lut_mask = 16'hE6A2; -defparam \D[6]~87 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y1_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a6 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h3C766E63DB6481CB39BC8C68831C724633186CC1BAE9D608A5DEF0FF219C28C1EFF4FDE394D0E19B6FD89186C23CF071E6F1CC8F7FC4F1E48756B0DCD8ED6D0C3DA139003D7A86B2F878DD99DAFB70DE1A19F3FB7DB3B8EF2633007664CB19992E43664448EFF06072648DBA32EDB76E26439BCCEF2DFBF664594B04FBAE72A84A3E508B49DC6BEAAB4F3F0CCCF6D8F568F2DA00EB384A7F53249323198000100408002024010408824080002008011482ED5615E40012EE630C3B2CDB2C13A736DB5B7BD2850018CF936621C6863095A73F7BE7442CB13110B9C0BBB96EEF16CE618EEDCFB393738178C476C367909F71307F6803F677575763DB2D8C3118E4; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h881331ED7AC4EFD38DFACDBB236790005719AEA2FAECCF0D126A30A27222D61BBA428334561F4EDB60C6BF8DB6E267BC56CB69BBCE636CCCB3B2B4B103CC46D5CEEC06DAECB0001569589D5F267AFE086C8FED5DE41DFEFF027DFDFF7FFBFBFDFFDFFF6FFFBDFFDFFF57FF7F7FB7FBBDFBDFFDBFF78FFDBFFEDDFFFDFFFEFF6FF7F7FDDFFEDFF6FF7FFEEFFEFEFC4E51EC0888848E1F2044B47B66608D8A3B3919B9466E6D60D27565964244B218B48AD83430D996068EC908D9E112096996041D77401A0C0CCF5DEEE561F7F7E68CBE72E48E570B047C772CBACC33753080E32EB0B348C0B62337739B1BC73192392592C84E37B7AC141CFE65EE76D83C9083; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h1C5CF062CA6F13854A59BDEEEA07E3C6559EBB3618111895CBBACCBCD512B5F07D361CCE72B925658DBE1F7C4707E195C5C665B8118C3C31B196C261DA85A5E11889D25CB816ACC6627802052C61A4099B7B0EC923971DB3B9F9204BDBCCFA457EE296E8986E64C6DC99E59436641567648CB84DEB7D7937F974F038D838274F3D3CF1BE8C84DDB000565880A776E5C0E13166E49F47119A4CA1311CF97B965E7CBBCB2CB384BD0D92ED105D0617856E80441124B31DE58B8C001607FEE668899693E3EFF8FBF1FCEEFBCF7CF9BA6C37640DDF7FFE6187B19ACF089D4C038F6607B78D38001FE67E56CCE399DE36D7DDBD699D5CFC5B6D7A1421CE06FE40DB6E; -defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h0776C62C316FF94B0BC3A0288DE6A62B14D6C1A2DADF9BDF85B2CCB02CE1DB2D96632C3232C3974CDC1172E1779D8C6738251819975DB8146067301E0C0277B6B657485DCD62AC0662C8C005DDE7494C9CA13AAE3234BB0EE1B708A23A2F48AC4C3838641E940620F9CDDCCA14BCC07104C112BCC9032C48E925594CB886A604C9F7627EB100872A52FB5141D65111E6C8DA0ADB6CEC6004461D0E366B20DCCDB607E624499300E4DF6D95CB62F62FB75403E400EFBC3BD34080FC9CDCFCFCFFFFFFFFFFFFFFFFFFFFF7BFFFFFFFFFFFFFFFFFFFFFFFFFFFCF9FFFFFEFFFF81FFDDFFFFFFFFFFFFFF7FFBFFFBFDC0A6DBE6F8BE5BB7FE7A39B3DA3F3BE13B679; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N6 -cycloneive_lcell_comb \D[6]~88 ( -// Equation(s): -// \D[6]~88_combout = (\z80_|address_pins_|abus[15]~22_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout $ (((\D[6]~87_combout ))))) # (!\z80_|address_pins_|abus[15]~22_combout & -// (((\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout & !\D[6]~87_combout )))) - - .dataa(\z80_|address_pins_|abus[15]~22_combout ), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ), - .datad(\D[6]~87_combout ), - .cin(gnd), - .combout(\D[6]~88_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~88 .lut_mask = 16'h22D8; -defparam \D[6]~88 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N20 -cycloneive_lcell_comb \D[6]~89 ( -// Equation(s): -// \D[6]~89_combout = (\D[6]~87_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout & !\D[6]~88_combout )))) # (!\D[6]~87_combout & -// (((!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & \D[6]~88_combout )))) - - .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ), - .datab(\D[6]~87_combout ), - .datac(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datad(\D[6]~88_combout ), - .cin(gnd), - .combout(\D[6]~89_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~89 .lut_mask = 16'hC3C8; -defparam \D[6]~89 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N14 -cycloneive_lcell_comb \D[6]~111 ( -// Equation(s): -// \D[6]~111_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [15] & (\D[6]~91_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\D[6]~89_combout ))))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & -// (\D[6]~91_combout )) - - .dataa(\D[6]~91_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [15]), - .datad(\D[6]~89_combout ), - .cin(gnd), - .combout(\D[6]~111_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~111 .lut_mask = 16'hAEA2; -defparam \D[6]~111 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: IOIBUF_X16_Y34_N8 -cycloneive_io_ibuf \raw_loader_in~input ( - .i(raw_loader_in), - .ibar(gnd), - .o(\raw_loader_in~input_o )); -// synopsys translate_off -defparam \raw_loader_in~input .bus_hold = "false"; -defparam \raw_loader_in~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N18 -cycloneive_lcell_comb \D[6]~86 ( -// Equation(s): -// \D[6]~86_combout = (\z80_|address_pins_|DFFE_apin_latch [0]) # ((\raw_loader_in~input_o ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [0]), - .datab(gnd), - .datac(\raw_loader_in~input_o ), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .cin(gnd), - .combout(\D[6]~86_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~86 .lut_mask = 16'hFAFF; -defparam \D[6]~86 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N28 -cycloneive_lcell_comb \D[6]~100 ( -// Equation(s): -// \D[6]~100_combout = ((\Equal2~0_combout & ((\D[6]~86_combout ))) # (!\Equal2~0_combout & (\D[6]~111_combout ))) # (!\Equal2~1_combout ) - - .dataa(\Equal2~1_combout ), - .datab(\Equal2~0_combout ), - .datac(\D[6]~111_combout ), - .datad(\D[6]~86_combout ), - .cin(gnd), - .combout(\D[6]~100_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~100 .lut_mask = 16'hFD75; -defparam \D[6]~100 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N4 -cycloneive_lcell_comb \D[6]~101 ( -// Equation(s): -// \D[6]~101_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\z80_|data_pins_|dout [6] & \D[6]~100_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\D[6]~100_combout )) # (!\Equal2~1_combout ))) - - .dataa(\Equal2~1_combout ), - .datab(\z80_|data_pins_|dout [6]), - .datac(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datad(\D[6]~100_combout ), - .cin(gnd), - .combout(\D[6]~101_combout ), - .cout()); -// synopsys translate_off -defparam \D[6]~101 .lut_mask = 16'hCF05; -defparam \D[6]~101 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N12 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [6] = (\z80_|pin_control_|bus_db_pin_re~combout & ((\D[6]~101_combout ) # ((\z80_|execute_|ctl_bus_db_we~7_combout & \z80_|bus_control_|db[6]~9_combout )))) # (!\z80_|pin_control_|bus_db_pin_re~combout & -// (((\z80_|execute_|ctl_bus_db_we~7_combout & \z80_|bus_control_|db[6]~9_combout )))) - - .dataa(\z80_|pin_control_|bus_db_pin_re~combout ), - .datab(\D[6]~101_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|bus_control_|db[6]~9_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [6]), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] .lut_mask = 16'hF888; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N10 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_re~2 ( -// Equation(s): -// \z80_|pin_control_|bus_db_pin_re~2_combout = (\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & ((\z80_|execute_|fIORead~3_combout )))) # (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # -// ((\z80_|sequencer_|DFFE_T3_ff~q & \z80_|execute_|fIORead~3_combout )))) - - .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|execute_|fIORead~3_combout ), - .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_re~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_re~2 .lut_mask = 16'hDC50; -defparam \z80_|pin_control_|bus_db_pin_re~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N16 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_2 ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_2~combout = (\z80_|execute_|ctl_bus_db_we~7_combout ) # ((\z80_|pin_control_|bus_db_pin_re~2_combout ) # ((\z80_|execute_|fMRead~35_combout & \z80_|sequencer_|DFFE_T2_ff~q ))) - - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(\z80_|execute_|fMRead~35_combout ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|pin_control_|bus_db_pin_re~2_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_2 .lut_mask = 16'hFFEA; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y13_N13 -dffeas \z80_|data_pins_|dout[6] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [6]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|data_pins_|dout [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|data_pins_|dout[6] .is_wysiwyg = "true"; -defparam \z80_|data_pins_|dout[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N16 -cycloneive_lcell_comb \z80_|bus_control_|db[6]~9 ( -// Equation(s): -// \z80_|bus_control_|db[6]~9_combout = ((\z80_|bus_control_|db[6]~8_combout & ((\z80_|data_pins_|dout [6]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - - .dataa(\z80_|bus_control_|db[6]~8_combout ), - .datab(\z80_|data_pins_|dout [6]), - .datac(\z80_|execute_|ctl_bus_db_oe~combout ), - .datad(\z80_|bus_control_|db[0]~6_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[6]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[6]~9 .lut_mask = 16'h8AFF; -defparam \z80_|bus_control_|db[6]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N8 -cycloneive_lcell_comb \z80_|ir_|opcode[6]~feeder ( -// Equation(s): -// \z80_|ir_|opcode[6]~feeder_combout = \z80_|bus_control_|db[6]~9_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|bus_control_|db[6]~9_combout ), - .cin(gnd), - .combout(\z80_|ir_|opcode[6]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|ir_|opcode[6]~feeder .lut_mask = 16'hFF00; -defparam \z80_|ir_|opcode[6]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~13 ( -// Equation(s): -// \z80_|execute_|ctl_ir_we~13_combout = ((\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_ir_we~5_combout ) # (\z80_|pla_decode_|Equal41~2_combout )))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) - - .dataa(\z80_|execute_|ctl_ir_we~5_combout ), - .datab(\z80_|pla_decode_|Equal41~2_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_ir_we~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_ir_we~13 .lut_mask = 16'hE0FF; -defparam \z80_|execute_|ctl_ir_we~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y12_N9 -dffeas \z80_|ir_|opcode[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|ir_|opcode[6]~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|ir_|opcode [6]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|ir_|opcode[6] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal41~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal41~0_combout = (\z80_|ir_|opcode [7] & \z80_|ir_|opcode [6]) - - .dataa(gnd), - .datab(gnd), + .dataa(\z80_|decode_state_|DFFE_instCB~q ), + .datab(\z80_|decode_state_|DFFE_instED~q ), .datac(\z80_|ir_|opcode [7]), .datad(\z80_|ir_|opcode [6]), .cin(gnd), - .combout(\z80_|pla_decode_|Equal41~0_combout ), + .combout(\z80_|pla_decode_|Equal44~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal41~0 .lut_mask = 16'hF000; -defparam \z80_|pla_decode_|Equal41~0 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal44~0 .lut_mask = 16'h0010; +defparam \z80_|pla_decode_|Equal44~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y16_N22 -cycloneive_lcell_comb \z80_|pla_decode_|Equal41~1 ( +// Location: LCCOMB_X25_Y16_N20 +cycloneive_lcell_comb \z80_|execute_|ixy_d~16 ( // Equation(s): -// \z80_|pla_decode_|Equal41~1_combout = (!\z80_|ir_|opcode [2] & (\z80_|ir_|opcode [1] & (\z80_|ir_|opcode [0] & !\z80_|ir_|opcode [5]))) +// \z80_|execute_|ixy_d~16_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal44~0_combout & ((\z80_|decode_state_|DFFE_instIY1~q ) # (\z80_|decode_state_|DFFE_inst4~q )))) - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|ir_|opcode [1]), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|ir_|opcode [5]), + .dataa(\z80_|decode_state_|DFFE_instIY1~q ), + .datab(\z80_|decode_state_|DFFE_inst4~q ), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|pla_decode_|Equal44~0_combout ), .cin(gnd), - .combout(\z80_|pla_decode_|Equal41~1_combout ), + .combout(\z80_|execute_|ixy_d~16_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal41~1 .lut_mask = 16'h0040; -defparam \z80_|pla_decode_|Equal41~1 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ixy_d~16 .lut_mask = 16'hE000; +defparam \z80_|execute_|ixy_d~16 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y16_N24 -cycloneive_lcell_comb \z80_|pla_decode_|Equal41~2 ( +// Location: LCCOMB_X23_Y13_N24 +cycloneive_lcell_comb \z80_|pla_decode_|Equal3~1 ( // Equation(s): -// \z80_|pla_decode_|Equal41~2_combout = (\z80_|pla_decode_|Equal41~0_combout & (\z80_|pla_decode_|Equal32~0_combout & (\z80_|pla_decode_|Equal41~1_combout & \z80_|decode_state_|use_ixiy~combout ))) - - .dataa(\z80_|pla_decode_|Equal41~0_combout ), - .datab(\z80_|pla_decode_|Equal32~0_combout ), - .datac(\z80_|pla_decode_|Equal41~1_combout ), - .datad(\z80_|decode_state_|use_ixiy~combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal41~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal41~2 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal41~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe ( -// Equation(s): -// \z80_|execute_|ctl_alu_bs_oe~combout = (\z80_|execute_|ctl_alu_bs_oe~11_combout ) # ((\z80_|sequencer_|DFFE_M4_ff~q & (\z80_|pla_decode_|Equal41~2_combout & !\z80_|sequencer_|DFFE_T1_ff~q ))) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|pla_decode_|Equal41~2_combout ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|execute_|ctl_alu_bs_oe~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_bs_oe~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_bs_oe .lut_mask = 16'hFF08; -defparam \z80_|execute_|ctl_alu_bs_oe .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N2 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~15 ( -// Equation(s): -// \z80_|alu_|db_high[1]~15_combout = ((!\z80_|bus_control_|db[4]~19_combout & (\z80_|bus_control_|db[5]~15_combout & \z80_|bus_control_|db[3]~21_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) - - .dataa(\z80_|execute_|ctl_alu_bs_oe~combout ), - .datab(\z80_|bus_control_|db[4]~19_combout ), - .datac(\z80_|bus_control_|db[5]~15_combout ), - .datad(\z80_|bus_control_|db[3]~21_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~15 .lut_mask = 16'h7555; -defparam \z80_|alu_|db_high[1]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y10_N10 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~16 ( -// Equation(s): -// \z80_|alu_|db_high[1]~16_combout = (\z80_|alu_|op1_high [1] & (((\z80_|alu_|op2_high [1]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|alu_|op1_high [1] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_high [1]) # -// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) - - .dataa(\z80_|alu_|op1_high [1]), - .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), - .datac(\z80_|alu_|op2_high [1]), - .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~16 .lut_mask = 16'hB0BB; -defparam \z80_|alu_|db_high[1]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N20 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~17 ( -// Equation(s): -// \z80_|alu_|db_high[1]~17_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[6]~23_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[4]~17_combout ))) - - .dataa(\z80_|alu_|db[6]~23_combout ), - .datab(gnd), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|alu_|db[4]~17_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~17 .lut_mask = 16'hAFA0; -defparam \z80_|alu_|db_high[1]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y9_N26 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~18 ( -// Equation(s): -// \z80_|alu_|db_high[1]~18_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_high[1]~17_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[5]~25_combout ))) +// \z80_|pla_decode_|Equal3~1_combout = (\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [1]) .dataa(gnd), - .datab(\z80_|alu_|db_high[1]~17_combout ), - .datac(\z80_|alu_|db[5]~25_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~18 .lut_mask = 16'hCCF0; -defparam \z80_|alu_|db_high[1]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N12 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~19 ( -// Equation(s): -// \z80_|alu_|db_high[1]~19_combout = (\z80_|alu_|db_high[1]~15_combout & (\z80_|alu_|db_high[1]~16_combout & ((\z80_|alu_|db_high[1]~18_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) - - .dataa(\z80_|alu_|db_high[1]~15_combout ), - .datab(\z80_|alu_|db_high[1]~16_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), - .datad(\z80_|alu_|db_high[1]~18_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~19 .lut_mask = 16'h8808; -defparam \z80_|alu_|db_high[1]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y10_N26 -cycloneive_lcell_comb \z80_|alu_|db_high[1]~20 ( -// Equation(s): -// \z80_|alu_|db_high[1]~20_combout = ((\z80_|alu_|db_high[1]~19_combout & ((\z80_|execute_|ctl_alu_res_oe~2_combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout )))) # (!\z80_|alu_|db_high[3]~3_combout ) - - .dataa(\z80_|alu_|db_high[1]~19_combout ), - .datab(\z80_|execute_|ctl_alu_res_oe~2_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), - .datad(\z80_|alu_|db_high[3]~3_combout ), - .cin(gnd), - .combout(\z80_|alu_|db_high[1]~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db_high[1]~20 .lut_mask = 16'hA8FF; -defparam \z80_|alu_|db_high[1]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N14 -cycloneive_lcell_comb \z80_|alu_|db[5]~24 ( -// Equation(s): -// \z80_|alu_|db[5]~24_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[5]~57_combout & ((\z80_|alu_control_|db[5]~15_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & -// ((\z80_|alu_control_|db[5]~15_combout ) # ((!\z80_|execute_|ctl_sw_2d~13_combout )))) - - .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), - .datab(\z80_|alu_control_|db[5]~15_combout ), - .datac(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), - .datad(\z80_|execute_|ctl_sw_2d~13_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[5]~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[5]~24 .lut_mask = 16'hC4F5; -defparam \z80_|alu_|db[5]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y10_N28 -cycloneive_lcell_comb \z80_|alu_|db[5]~25 ( -// Equation(s): -// \z80_|alu_|db[5]~25_combout = ((\z80_|alu_|db[5]~24_combout & ((\z80_|alu_|db_high[1]~20_combout ) # (!\z80_|execute_|ctl_alu_oe~14_combout )))) # (!\z80_|alu_|db[7]~26_combout ) - - .dataa(\z80_|alu_|db_high[1]~20_combout ), - .datab(\z80_|alu_|db[7]~26_combout ), - .datac(\z80_|alu_|db[5]~24_combout ), - .datad(\z80_|execute_|ctl_alu_oe~14_combout ), - .cin(gnd), - .combout(\z80_|alu_|db[5]~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_|db[5]~25 .lut_mask = 16'hB3F3; -defparam \z80_|alu_|db[5]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N14 -cycloneive_lcell_comb \z80_|sw1_|db_down[5]~0 ( -// Equation(s): -// \z80_|sw1_|db_down[5]~0_combout = (\z80_|bus_control_|db[5]~15_combout ) # ((\z80_|execute_|ctl_sw_1d~6_combout & ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|execute_|ctl_66_oe~2_combout )))) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|bus_control_|db[5]~15_combout ), - .datac(\z80_|execute_|ctl_66_oe~2_combout ), - .datad(\z80_|execute_|ctl_sw_1d~6_combout ), - .cin(gnd), - .combout(\z80_|sw1_|db_down[5]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sw1_|db_down[5]~0 .lut_mask = 16'hEFCC; -defparam \z80_|sw1_|db_down[5]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N22 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_36 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout = (\z80_|alu_control_|db[5]~15_combout & ((\z80_|execute_|ctl_flags_bus~combout ) # ((\z80_|alu_|db_high[1]~20_combout & \z80_|execute_|ctl_flags_alu~15_combout )))) # (!\z80_|alu_control_|db[5]~15_combout -// & (\z80_|alu_|db_high[1]~20_combout & ((\z80_|execute_|ctl_flags_alu~15_combout )))) - - .dataa(\z80_|alu_control_|db[5]~15_combout ), - .datab(\z80_|alu_|db_high[1]~20_combout ), - .datac(\z80_|execute_|ctl_flags_bus~combout ), - .datad(\z80_|execute_|ctl_flags_alu~15_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_36 .lut_mask = 16'hECA0; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y11_N23 -dffeas \z80_|alu_flags_|flags_yf ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_flags_xy_we~15_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|flags_yf~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_yf .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|flags_yf .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N2 -cycloneive_lcell_comb \z80_|alu_control_|db[5]~13 ( -// Equation(s): -// \z80_|alu_control_|db[5]~13_combout = (\z80_|alu_flags_|flags_yf~q & ((\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ) # ((\z80_|alu_control_|out[6]~2_combout )))) # (!\z80_|alu_flags_|flags_yf~q & (!\z80_|execute_|ctl_flags_oe~2_combout & -// ((\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ) # (\z80_|alu_control_|out[6]~2_combout )))) - - .dataa(\z80_|alu_flags_|flags_yf~q ), - .datab(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .datac(\z80_|execute_|ctl_flags_oe~2_combout ), - .datad(\z80_|alu_control_|out[6]~2_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[5]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[5]~13 .lut_mask = 16'hAF8C; -defparam \z80_|alu_control_|db[5]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N0 -cycloneive_lcell_comb \z80_|alu_control_|db[5]~14 ( -// Equation(s): -// \z80_|alu_control_|db[5]~14_combout = (\z80_|sw1_|db_down[5]~0_combout & (\z80_|alu_control_|db[5]~13_combout & ((\z80_|reg_file_|gdfx_temp0[5]~72_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) - - .dataa(\z80_|sw1_|db_down[5]~0_combout ), - .datab(\z80_|alu_control_|db[5]~13_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), - .datad(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[5]~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[5]~14 .lut_mask = 16'h8088; -defparam \z80_|alu_control_|db[5]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y11_N10 -cycloneive_lcell_comb \z80_|alu_control_|db[5]~15 ( -// Equation(s): -// \z80_|alu_control_|db[5]~15_combout = ((\z80_|alu_control_|db[5]~14_combout & ((\z80_|alu_|db[5]~25_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|alu_control_|db[6]~11_combout ), - .datab(\z80_|alu_|db[5]~25_combout ), - .datac(\z80_|execute_|ctl_sw_2u~7_combout ), - .datad(\z80_|alu_control_|db[5]~14_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[5]~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[5]~15 .lut_mask = 16'hDF55; -defparam \z80_|alu_control_|db[5]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N10 -cycloneive_lcell_comb \D[0]~107 ( -// Equation(s): -// \D[0]~107_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout ) # ((!\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \z80_|memory_ifc_|nRD_out~2_combout ))) - - .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|memory_ifc_|nRD_out~2_combout ), - .datad(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .cin(gnd), - .combout(\D[0]~107_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~107 .lut_mask = 16'hFF40; -defparam \D[0]~107 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y6_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a21 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[5]~99_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_first_bit_number = 5; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y9_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a5 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[5]~99_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_bit_number = 5; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024; -// synopsys translate_on - -// Location: M9K_X22_Y7_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a13 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[5]~99_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_bit_number = 5; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N8 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4 .lut_mask = 16'hDC98; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y23_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a29 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[5]~99_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_first_bit_number = 5; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N6 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4_combout & -// ((\ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout )))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4_combout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4_combout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5 .lut_mask = 16'hF838; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y26_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a13 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(gnd), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[5]~99_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_bit_number = 5; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_first_bit_number = 5; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y29_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a13 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_bit_number = 5; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init3 = 2048'h990442000864A0284030400454782424440404007E404808A4005448387E547C8004420800620824402040024A1242124204044008404208420A4A42424A1242020028008000524A024A4A284252446240001000101042000054265C7E0600007FAF5CA001C181BE0C02418447B1D88BAA85409896BC7C0E5FAC2529CB69A4038E2564731F88FE730045956C357C5ECF7EF8591DF2A8ACFFBFEEF268CD9B51238594AF691A9B8640983B7F76AAB97209EA6257389992FFE684926E0B19FA338B8489D73811171D5C9FF3DCFFFFFF8002000780101F3F4035A0CDED99F79A4775854F179F7D7DBBCF81B2F6421FF684CA6AF85894D29B9D3ACCBA3F27D9DC9911; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init2 = 2048'h5B438D714D4E3DD115E8BD1286EAB5FA1D71BD8F4508BD4BDC8838F9D27B552259BCEFFBB68A6FF529B3B0D92970010BBB6C7D872421210E190E1CCC47A485EAD2F8735647315839EF6F683C64773FC73464D5FE354936D50823A5DAEBEBDBCC6CAFF2622B8D518F63C6030424188FD357718970D25A30CD0731E532DB23002D02C12B12378356DE2C52041CA7A320C51E0D7CA9F5D575775D57FD75DDFDF75FFFDFFFD75F145247F03A0AE7F1E1EB2D5A99D2444108C6A5979B7CC26ABCC241EA4C912568003BB493CE04FF086C188980052BF6ABAAA2FD5D658000011277EB924C10EFAF3CB9B62486512344C61ADE6F15AB67F335A52513FF05AFAEEE8400; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 2048'h0C840083AD485153ACD3C035591630199B8C096CE4DC557D6D55FCCD738573D6E0948817C496E9DE8EA1F88F627B7460106691CC452DB9799E59A5D003733C4EA1BCE33AD2D8BE40A4E5BB7D7BBEC2CEADBBC8B6F87A4A56FBE0B891DE57E4C64EF9AD87727C49CFE7C5DE942B72AC7F6D97DE18920777FDDEE9EB11122A4E18F5569FDE08906765428FB9E6F89FBF0DEAA6064637BCA63FD02E273E5557F0548662C97BC2E8D3FFDB26D23E87BFD97E635A6560CFD93F8EED26E30C70DE8633D6B97C86DF7D9BEDFB99E36B6658F16C6DEFBDD5DF728D6209C852C37FE67CFF32EE4CCCECC64F7E6225FC99EC64C3B6DD7DED0FD7CCEA3BF09A006ECDD1009E; -defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'hA9C9CE3AECF7BE27C000000A8ABA95251B309A60B9DDC19EC3E391458CBB53CA00A85E3C5AAE2C49DDC2F6C7B013DACB319A769818A1081A7389F711D76A09BCBED23D9A99FF9B77183697955D76BF0E0008822742DA45B883C9193DAF09424501859565800698515E10A8189EE9B323E35CE7388D73C6E7A50D0DE6739C73AC538D134115D860ADA57B5B868E54393B1E31E762062577697D57E8464340420E9434CCA34CC9A1CB1FAACC56168071EAC113F5265D5F6A45A098D604A820508C4EA47F9A7E46083716911B0D585CE937B530218E8D2AD3777EE7D3B4BC56C29ADB46809D15D185F8809229B150C29C8081174CA6173B99703DA466629005C604; -// synopsys translate_on - -// Location: M9K_X33_Y2_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a5 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_bit_number = 5; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init3 = 2048'hE10F8B8C100323720BEBBDEBB81DF13FF97B252E2CB4F27BA091FBD0002D1A611E1EDBBC716D44D2912B80041C44558060CFCF15955C0D780DD5E71393920844F25E16C87C5D0308EEC52C011514BBC13AFA1028924D0C7CE738105BD47A10AA5B5C1D9D4193E4339F492B0E1A64E13AE35BE6B67AC8057BDACC155F14E906A017A1841358335450D4B26CD2A21B3D8F2211080B81EC040D7FA0B51CD48008112508062020A02490900092D2040259108806A328F4006D2AA514B42FB006ECCCCB9A360865678449975A8AE72B5C0F7BA800C1B5DC55D7D6FE2EF4EED85D00AB111821321BA426A4FE4956B43595832C271E83E060341AE5F2023FC808177383; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init2 = 2048'h1A2955372D510AC266A5445146E27000020C320FAE1557E37154040A13202DC6F40B840FB9A59B6DBB296562CB6220EFBE99D2776A202044D9101006FD221D305519198C859000004012AFF4FB060307C92BB732203BFDFEFFFFFFDFFF87FCFFFBFFEFF03FFE0FFFBFAFE0FF80787FFF7FFF83F7F87003FFBFFFFBFFFBFF0FFC0FF81FFF7FFBFFDFFFBFFFE1FF0086F3141AAB6005810A0621595A893F9D85983B9254954341968BAC8C141C90938C05B2C9CD267E11650407375FEDD6A2FEB346AAF6CFDC0791AA97B741995A3B3981E06D1A44D3711955197BB9910FCA20744915C84D6C24BAF53929814CA8A4697E8F4201145AE7415DC122A5F010436107; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048'h02E84F969E3C800AC610D276182020227809001A50DDDBA3487BB6AE802BA06509312DA0E620656EAF24D57C08FFB14D289613DC32083803B84DC6415FD5EDC000300A8D128FA20030ACCBAFA237B7024504D36A4BA26081137F059E78991154FE2AC2A884A8CC7FBBB21C851CC92B12E15593C0C020FFEE066558590E882D5B67459F1A8C3240FE4E6A8D028C0C088FCF471D400A19B38211004DD122212288B111114514CB11840E04828849C621392041163C00808C67223422F00110201DD18FCFFFF3FFE7F9FFFFFFF82C0B422D214711E08904524A069491774E663F48F665955B4E2C63DAC0078652D10120900298F7EE380092442AFD400BEC43C003; -defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'hB5D49EA9D7036A45AA9E870B8E8016720C7C3102AE925262492C84584942D209042216E0216C85B8912250B7157D5955AD406CB685BBF071B47D5193363C1CECAFE59E91BF11498940A0944996D47EE8D7E3A4EAE611AE19A965D01BA86B55E9C52A6A379A382C6C265FB0DA01396D0800C0046405C06F466DD18C4DD7655CD4E7622EC485808C841D64B737041FF68813B149A41531A0A692FB14AE2E5B49D49CDCADCF90E7BD88125BCE706BF6D04AABFC1C001163DC6EFF7FD3230303030000000000000000000008400000000000000000000000000030600000100007E00220000000000000080040004023AD496997B8C0077B886EEF161CF2298A091B; -// synopsys translate_on - -// Location: M9K_X33_Y29_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a5 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[5]~99_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a5_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_bit_number = 5; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_first_bit_number = 5; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init3 = 2048'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF80000001C000000160F000FF70C0007F78C00000F05001007870010010000000000800000038000000F000000070000000300000006000000000000040000000F00000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000000001D108000BEDA9FA9698A000000000000000000000000FFFFFFFF408102048004188297E014DA9FA9E9CA00000000000000000000000000000000FFFFFFFC800400CA972208DA9FA9CD8E00000000000000000000000000000000FFFFFFFC8004046A97A289FA9FA9CDC20000000000000000000000007FFFFFFC8000000280040E2A97A2997A9DA9CFC20000000000000000000000007FFFFFFE8000000280042EB28002BE369DA9274200000000000000000000000040810206BFFFFFFE9FE430A29D82AC3E8009E34A000000000000000000000000000000023FFFFFFC9FE4B1829FA2800E8009436A; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048'h9FE8334E88F827C697F88D1600A80A44809E8FC2B86999C2B85B3A82B1D32A869FE8336A88F807CA97F88F96A0A80EC2838E8D42B9E98FC2B86B3B82B0D7B2D2800832E288F827CA97F88B82A0080EC683869542B939B8C2B1AB0F8290B730C2800826EA8878078297F88AD2A0280EC283E694C2B83A3BC2A3AB3E8291A316AA800826EE881807C69DE8ABD6A0280BC282209CD2BA2A3D42A2737F82918314E2800806E6981805C69D48AED6A1E80BCA82709FC2BB223DC2A07B7F8295DF11C2800886E6980805869848AAC6A1E42DC281789DC2BBAA3DC6A02B7582955F00928008A6EE98082D9618088AC8A0F40FC289E89DC2BBCA3DC2A18B7782154F02F0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'h174F0870801C870281E2C982A801460297E5AC0288F318023FFFFFFC0000000297DF094A8094870281D6C082AC01460293FDA89288D31902BFFFFFFE40810106879F8D228C8685028016C082AC014642B3FCA80288D10F02800000027FFFFFFE879F893284DEC9028000408AAC014C02937DA00288D10F02800000027FFFFFFC841FA902804E81068BC04292AC0145E29379B00288D11F02FFFFFFFC0000000084FE89328166C1028BE05282AE4144829179B20288511F02FFFFFFFC0000000084F283328516850A88204602874364829179B08280513E0240810104FFFFFFFF843A8302853685828800560287476C928039B00200413E0000000000FFFFFFFF; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N0 -cycloneive_lcell_comb \Mux2~0 ( -// Equation(s): -// \Mux2~0_combout = (\z80_|address_pins_|abus[14]~23_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout )))) # (!\z80_|address_pins_|abus[14]~23_combout & -// (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ))) - - .dataa(\z80_|address_pins_|abus[14]~23_combout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout ), - .cin(gnd), - .combout(\Mux2~0_combout ), - .cout()); -// synopsys translate_off -defparam \Mux2~0 .lut_mask = 16'hBA98; -defparam \Mux2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N2 -cycloneive_lcell_comb \Mux2~1 ( -// Equation(s): -// \Mux2~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Mux2~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout )) # (!\Mux2~0_combout & -// ((\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Mux2~0_combout )))) - - .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ), - .datad(\Mux2~0_combout ), - .cin(gnd), - .combout(\Mux2~1_combout ), - .cout()); -// synopsys translate_off -defparam \Mux2~1 .lut_mask = 16'hBBC0; -defparam \Mux2~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N20 -cycloneive_lcell_comb \D[5]~110 ( -// Equation(s): -// \D[5]~110_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [15] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\Mux2~1_combout ))))) # -// (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout )) - - .dataa(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [15]), - .datad(\Mux2~1_combout ), - .cin(gnd), - .combout(\D[5]~110_combout ), - .cout()); -// synopsys translate_off -defparam \D[5]~110 .lut_mask = 16'hAEA2; -defparam \D[5]~110 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N28 -cycloneive_lcell_comb \D[5]~85 ( -// Equation(s): -// \D[5]~85_combout = (\D[5]~84_combout & (\D[5]~110_combout & ((\z80_|data_pins_|dout [5]) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) # (!\D[5]~84_combout & (((\z80_|data_pins_|dout [5])) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout ))) - - .dataa(\D[5]~84_combout ), - .datab(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datac(\z80_|data_pins_|dout [5]), - .datad(\D[5]~110_combout ), - .cin(gnd), - .combout(\D[5]~85_combout ), - .cout()); -// synopsys translate_off -defparam \D[5]~85 .lut_mask = 16'hF351; -defparam \D[5]~85 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N24 -cycloneive_lcell_comb \D[5]~99 ( -// Equation(s): -// \D[5]~99_combout = (\D[5]~85_combout ) # (!\D[0]~107_combout ) - - .dataa(\D[0]~107_combout ), .datab(gnd), - .datac(gnd), - .datad(\D[5]~85_combout ), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [1]), .cin(gnd), - .combout(\D[5]~99_combout ), + .combout(\z80_|pla_decode_|Equal3~1_combout ), .cout()); // synopsys translate_off -defparam \D[5]~99 .lut_mask = 16'hFF55; -defparam \D[5]~99 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal3~1 .lut_mask = 16'h00F0; +defparam \z80_|pla_decode_|Equal3~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y13_N14 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[5] ( +// Location: LCCOMB_X24_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|ixy_d~10 ( // Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [5] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[5]~15_combout ) # ((\D[5]~99_combout & \z80_|pin_control_|bus_db_pin_re~combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & -// (\D[5]~99_combout & (\z80_|pin_control_|bus_db_pin_re~combout ))) +// \z80_|execute_|ixy_d~10_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal6~0_combout ))) - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(\D[5]~99_combout ), - .datac(\z80_|pin_control_|bus_db_pin_re~combout ), - .datad(\z80_|bus_control_|db[5]~15_combout ), + .dataa(\z80_|pla_decode_|Equal33~1_combout ), + .datab(\z80_|pla_decode_|Equal3~1_combout ), + .datac(\z80_|decode_state_|use_ixiy~combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [5]), + .combout(\z80_|execute_|ixy_d~10_combout ), .cout()); // synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[5] .lut_mask = 16'hEAC0; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[5] .sum_lutc_input = "datac"; +defparam \z80_|execute_|ixy_d~10 .lut_mask = 16'h8000; +defparam \z80_|execute_|ixy_d~10 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y13_N15 -dffeas \z80_|data_pins_|dout[5] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [5]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|data_pins_|dout [5]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|data_pins_|dout[5] .is_wysiwyg = "true"; -defparam \z80_|data_pins_|dout[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N22 -cycloneive_lcell_comb \z80_|bus_control_|db[5]~14 ( +// Location: LCCOMB_X24_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|ixy_d~13 ( // Equation(s): -// \z80_|bus_control_|db[5]~14_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [5]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) +// \z80_|execute_|ixy_d~13_combout = (\z80_|execute_|ixy_d~16_combout ) # ((\z80_|execute_|ixy_d~10_combout ) # (\z80_|pla_decode_|Equal41~2_combout )) + + .dataa(\z80_|execute_|ixy_d~16_combout ), + .datab(\z80_|execute_|ixy_d~10_combout ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~13 .lut_mask = 16'hFEFE; +defparam \z80_|execute_|ixy_d~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|ixy_d~14 ( +// Equation(s): +// \z80_|execute_|ixy_d~14_combout = (\z80_|execute_|ixy_d~12_combout & (((\z80_|execute_|ixy_d~17_combout & !\z80_|execute_|ixy_d~13_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) # (!\z80_|execute_|ixy_d~12_combout & +// (((\z80_|execute_|ixy_d~17_combout & !\z80_|execute_|ixy_d~13_combout )))) + + .dataa(\z80_|execute_|ixy_d~12_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ixy_d~17_combout ), + .datad(\z80_|execute_|ixy_d~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ixy_d~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ixy_d~14 .lut_mask = 16'h22F2; +defparam \z80_|execute_|ixy_d~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N10 +cycloneive_lcell_comb \z80_|pla_decode_|Equal49~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal49~0_combout = (!\z80_|decode_state_|in_halt~q & (\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal77~0_combout )) .dataa(gnd), - .datab(\z80_|execute_|ctl_bus_db_oe~combout ), - .datac(\z80_|data_pins_|dout [5]), - .datad(\z80_|bus_control_|db[0]~4_combout ), + .datab(\z80_|decode_state_|in_halt~q ), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|pla_decode_|Equal77~0_combout ), .cin(gnd), - .combout(\z80_|bus_control_|db[5]~14_combout ), + .combout(\z80_|pla_decode_|Equal49~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[5]~14 .lut_mask = 16'hF300; -defparam \z80_|bus_control_|db[5]~14 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal49~0 .lut_mask = 16'h3000; +defparam \z80_|pla_decode_|Equal49~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y10_N22 -cycloneive_lcell_comb \z80_|bus_control_|db[5]~15 ( +// Location: LCCOMB_X24_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ixy_d~15 ( // Equation(s): -// \z80_|bus_control_|db[5]~15_combout = ((\z80_|bus_control_|db[5]~14_combout & ((\z80_|alu_control_|db[5]~15_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) +// \z80_|execute_|ixy_d~15_combout = ((\z80_|decode_state_|use_ixiy~combout & (\z80_|execute_|ixy_d~11_combout & \z80_|pla_decode_|Equal49~0_combout ))) # (!\z80_|execute_|ixy_d~14_combout ) - .dataa(\z80_|bus_control_|db[0]~6_combout ), - .datab(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datac(\z80_|alu_control_|db[5]~15_combout ), - .datad(\z80_|bus_control_|db[5]~14_combout ), + .dataa(\z80_|decode_state_|use_ixiy~combout ), + .datab(\z80_|execute_|ixy_d~11_combout ), + .datac(\z80_|execute_|ixy_d~14_combout ), + .datad(\z80_|pla_decode_|Equal49~0_combout ), .cin(gnd), - .combout(\z80_|bus_control_|db[5]~15_combout ), + .combout(\z80_|execute_|ixy_d~15_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[5]~15 .lut_mask = 16'hF755; -defparam \z80_|bus_control_|db[5]~15 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ixy_d~15 .lut_mask = 16'h8F0F; +defparam \z80_|execute_|ixy_d~15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X34_Y10_N13 -dffeas \z80_|ir_|opcode[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|bus_control_|db[5]~15_combout ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|ir_|opcode [5]), - .prn(vcc)); +// Location: LCCOMB_X28_Y18_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout = (\z80_|execute_|ixy_d~15_combout & \z80_|sequencer_|DFFE_T5_ff~q ) + + .dataa(gnd), + .datab(\z80_|execute_|ixy_d~15_combout ), + .datac(\z80_|sequencer_|DFFE_T5_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), + .cout()); // synopsys translate_off -defparam \z80_|ir_|opcode[5] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[5] .power_up = "low"; +defparam \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 .lut_mask = 16'hC0C0; +defparam \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y15_N20 +// Location: LCCOMB_X26_Y16_N28 cycloneive_lcell_comb \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 ( // Equation(s): // \z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (((!\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout )))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (!\z80_|ir_|opcode [5] & @@ -40796,17 +6454,17 @@ cycloneive_lcell_comb \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 ( .dataa(\z80_|ir_|opcode [5]), .datab(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), - .datac(\z80_|pla_decode_|Equal3~2_combout ), - .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|pla_decode_|Equal3~2_combout ), .cin(gnd), .combout(\z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'h3350; +defparam \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'h3530; defparam \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X37_Y15_N21 +// Location: FF_X26_Y16_N29 dffeas \z80_|decode_state_|DFFE_inst4 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout ), @@ -40825,525 +6483,32592 @@ defparam \z80_|decode_state_|DFFE_inst4 .is_wysiwyg = "true"; defparam \z80_|decode_state_|DFFE_inst4 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X40_Y18_N4 -cycloneive_lcell_comb \z80_|decode_state_|use_ixiy ( +// Location: LCCOMB_X25_Y16_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~5 ( // Equation(s): -// \z80_|decode_state_|use_ixiy~combout = (\z80_|decode_state_|DFFE_inst4~q ) # (\z80_|decode_state_|DFFE_instIY1~q ) +// \z80_|execute_|ctl_ir_we~5_combout = (\z80_|decode_state_|DFFE_instCB~q & (!\z80_|decode_state_|DFFE_inst4~q & !\z80_|decode_state_|DFFE_instIY1~q )) - .dataa(\z80_|decode_state_|DFFE_inst4~q ), - .datab(gnd), - .datac(\z80_|decode_state_|DFFE_instIY1~q ), - .datad(gnd), + .dataa(\z80_|decode_state_|DFFE_instCB~q ), + .datab(\z80_|decode_state_|DFFE_inst4~q ), + .datac(gnd), + .datad(\z80_|decode_state_|DFFE_instIY1~q ), .cin(gnd), - .combout(\z80_|decode_state_|use_ixiy~combout ), + .combout(\z80_|execute_|ctl_ir_we~5_combout ), .cout()); // synopsys translate_off -defparam \z80_|decode_state_|use_ixiy .lut_mask = 16'hFAFA; -defparam \z80_|decode_state_|use_ixiy .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_ir_we~5 .lut_mask = 16'h0022; +defparam \z80_|execute_|ctl_ir_we~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y17_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~23 ( +// Location: LCCOMB_X24_Y17_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~13 ( // Equation(s): -// \z80_|execute_|ctl_mRead~23_combout = (!\z80_|decode_state_|use_ixiy~combout & (!\z80_|decode_state_|in_halt~q & (\z80_|pla_decode_|Equal77~0_combout & \z80_|pla_decode_|Equal33~0_combout ))) +// \z80_|execute_|ctl_ir_we~13_combout = ((\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|pla_decode_|Equal41~2_combout ) # (\z80_|execute_|ctl_ir_we~5_combout )))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) - .dataa(\z80_|decode_state_|use_ixiy~combout ), - .datab(\z80_|decode_state_|in_halt~q ), - .datac(\z80_|pla_decode_|Equal77~0_combout ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mRead~23 .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_mRead~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N16 -cycloneive_lcell_comb \z80_|execute_|fMRead~34 ( -// Equation(s): -// \z80_|execute_|fMRead~34_combout = (\z80_|execute_|ctl_mRead~23_combout ) # (((\z80_|execute_|ctl_ir_we~12_combout ) # (!\z80_|execute_|fMRead~5_combout )) # (!\z80_|execute_|fMWrite~3_combout )) - - .dataa(\z80_|execute_|ctl_mRead~23_combout ), - .datab(\z80_|execute_|fMWrite~3_combout ), - .datac(\z80_|execute_|ctl_ir_we~12_combout ), - .datad(\z80_|execute_|fMRead~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~34 .lut_mask = 16'hFBFF; -defparam \z80_|execute_|fMRead~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y16_N14 -cycloneive_lcell_comb \z80_|execute_|fMRead~31 ( -// Equation(s): -// \z80_|execute_|fMRead~31_combout = (\z80_|execute_|ixy_d~6_combout & ((\z80_|pla_decode_|Equal33~3_combout ) # ((\z80_|pla_decode_|Equal6~1_combout )))) # (!\z80_|execute_|ixy_d~6_combout & (\z80_|execute_|ixy_d~5_combout & -// ((\z80_|pla_decode_|Equal33~3_combout ) # (\z80_|pla_decode_|Equal6~1_combout )))) - - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|pla_decode_|Equal33~3_combout ), - .datac(\z80_|pla_decode_|Equal6~1_combout ), - .datad(\z80_|execute_|ixy_d~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|fMRead~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|fMRead~31 .lut_mask = 16'hFCA8; -defparam \z80_|execute_|fMRead~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|fMRead~29 ( -// Equation(s): -// \z80_|execute_|fMRead~29_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|execute_|ctl_ir_we~5_combout & ((\z80_|ir_|opcode [6]) # (\z80_|ir_|opcode [7])))) - - .dataa(\z80_|ir_|opcode [6]), - .datab(\z80_|pla_decode_|Equal33~0_combout ), - .datac(\z80_|ir_|opcode [7]), + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|pla_decode_|Equal41~2_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), .datad(\z80_|execute_|ctl_ir_we~5_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~29_combout ), + .combout(\z80_|execute_|ctl_ir_we~13_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~29 .lut_mask = 16'hC800; -defparam \z80_|execute_|fMRead~29 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_ir_we~13 .lut_mask = 16'hF5D5; +defparam \z80_|execute_|ctl_ir_we~13 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y16_N14 -cycloneive_lcell_comb \z80_|execute_|fMRead~30 ( +// Location: FF_X30_Y17_N31 +dffeas \z80_|ir_|opcode[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|bus_control_|db[3]~21_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|ir_|opcode [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|ir_|opcode[3] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y16_N26 +cycloneive_lcell_comb \z80_|pla_decode_|Equal8~0 ( // Equation(s): -// \z80_|execute_|fMRead~30_combout = (\z80_|execute_|ctl_alu_shift_oe~14_combout & ((\z80_|execute_|ctl_ir_we~9_combout ) # ((\z80_|execute_|fMRead~29_combout ) # (\z80_|execute_|ctl_ir_we~10_combout )))) +// \z80_|pla_decode_|Equal8~0_combout = (!\z80_|ir_|opcode [2] & (\z80_|ir_|opcode [1] & \z80_|ir_|opcode [0])) + + .dataa(\z80_|ir_|opcode [2]), + .datab(gnd), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal8~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal8~0 .lut_mask = 16'h5000; +defparam \z80_|pla_decode_|Equal8~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~6 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~6_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal8~0_combout & \z80_|pla_decode_|Equal13~0_combout )) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|pla_decode_|Equal8~0_combout ), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~6 .lut_mask = 16'h3000; +defparam \z80_|execute_|ctl_mRead~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N10 +cycloneive_lcell_comb \z80_|pla_decode_|Equal9~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal9~0_combout = (!\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [3]) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [4]), + .datac(gnd), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal9~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal9~0 .lut_mask = 16'h0033; +defparam \z80_|pla_decode_|Equal9~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal9~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal9~1_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal1~7_combout & \z80_|pla_decode_|Equal9~0_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal2~0_combout ), + .datac(\z80_|pla_decode_|Equal1~7_combout ), + .datad(\z80_|pla_decode_|Equal9~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal9~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal9~1 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal9~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal9~1_combout & \z80_|sequencer_|M5~q )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|pla_decode_|Equal9~1_combout ), + .datad(\z80_|sequencer_|M5~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 .lut_mask = 16'h3000; +defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~28 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~28_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout & (((!\z80_|execute_|ctl_mRead~8_combout & !\z80_|execute_|ctl_mRead~6_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|execute_|ctl_mRead~8_combout ), + .datac(\z80_|execute_|ctl_mRead~6_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~28 .lut_mask = 16'h0057; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y16_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal13~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal13~1_combout = (\z80_|ir_|opcode [2] & (\z80_|ir_|opcode [1] & \z80_|ir_|opcode [0])) + + .dataa(\z80_|ir_|opcode [2]), + .datab(gnd), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal13~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal13~1 .lut_mask = 16'hA000; +defparam \z80_|pla_decode_|Equal13~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y17_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal69~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal69~0_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|ir_|opcode [4] & \z80_|pla_decode_|Equal13~1_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|pla_decode_|Equal13~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal69~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal69~0 .lut_mask = 16'h4000; +defparam \z80_|pla_decode_|Equal69~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout = (\z80_|pla_decode_|Equal1~4_combout & (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal13~0_combout & \z80_|ir_|opcode [0]))) + + .dataa(\z80_|pla_decode_|Equal1~4_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~27 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~27_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal6~0_combout & ((!\z80_|pla_decode_|Equal21~0_combout ) # (!\z80_|ir_|opcode [5])))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal3~1_combout ), + .datac(\z80_|pla_decode_|Equal21~0_combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~27 .lut_mask = 16'h4C00; +defparam \z80_|execute_|ctl_alu_op_low~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~2_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|pla_decode_|Equal69~0_combout ) # (\z80_|execute_|ctl_alu_op_low~27_combout )))) + + .dataa(\z80_|pla_decode_|Equal69~0_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~2 .lut_mask = 16'hFCF8; +defparam \z80_|execute_|ctl_reg_out_lo~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|rsel3 ( +// Equation(s): +// \z80_|execute_|rsel3~combout = \z80_|ir_|opcode [3] $ (((\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4]))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(gnd), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|rsel3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|rsel3 .lut_mask = 16'h5FA0; +defparam \z80_|execute_|rsel3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~12 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~12_combout = (\z80_|execute_|ctl_ir_we~5_combout & (!\z80_|ir_|opcode [7] & (\z80_|pla_decode_|Equal33~0_combout & \z80_|ir_|opcode [6]))) + + .dataa(\z80_|execute_|ctl_ir_we~5_combout ), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~12 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_ir_we~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|execute_|ctl_ir_we~12_combout & \z80_|sequencer_|DFFE_T3_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(gnd), + .datac(\z80_|execute_|ctl_ir_we~12_combout ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal56~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal56~0_combout = (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal1~4_combout & \z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|pla_decode_|Equal1~4_combout ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal56~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal56~0 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal56~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~24 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~24_combout = (\z80_|pla_decode_|Equal2~0_combout & (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|ir_|opcode [3]))) + + .dataa(\z80_|pla_decode_|Equal2~0_combout ), + .datab(\z80_|ir_|opcode [0]), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~24 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_alu_op_low~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~25 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~25_combout = (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|ir_|opcode [3]))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal2~0_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~25 .lut_mask = 16'h0040; +defparam \z80_|execute_|ctl_alu_op_low~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N16 +cycloneive_lcell_comb \z80_|execute_|nextM~2 ( +// Equation(s): +// \z80_|execute_|nextM~2_combout = (!\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_alu_op_low~24_combout & !\z80_|execute_|ctl_alu_op_low~25_combout )) + + .dataa(\z80_|pla_decode_|Equal56~0_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op_low~24_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~2 .lut_mask = 16'h0005; +defparam \z80_|execute_|nextM~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~16 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~16_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # ((\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T3_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|execute_|nextM~2_combout ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~16 .lut_mask = 16'h3320; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~3_combout = (\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ) # ((\z80_|execute_|ctl_reg_out_lo~2_combout & \z80_|execute_|rsel3~combout ))) + + .dataa(\z80_|execute_|ctl_reg_out_lo~2_combout ), + .datab(\z80_|execute_|rsel3~combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~3 .lut_mask = 16'hFFF8; +defparam \z80_|execute_|ctl_reg_out_lo~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y13_N22 +cycloneive_lcell_comb \z80_|pla_decode_|Equal40~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal40~0_combout = (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [1])) + + .dataa(\z80_|ir_|opcode [0]), + .datab(gnd), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal40~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal40~0 .lut_mask = 16'h0005; +defparam \z80_|pla_decode_|Equal40~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y13_N18 +cycloneive_lcell_comb \z80_|pla_decode_|Equal40~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal40~1_combout = (\z80_|pla_decode_|Equal40~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|ir_|opcode [5])) + + .dataa(\z80_|pla_decode_|Equal40~0_combout ), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(gnd), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal40~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal40~1 .lut_mask = 16'h8800; +defparam \z80_|pla_decode_|Equal40~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|execute_|ixy_d~7_combout & \z80_|pla_decode_|Equal1~7_combout ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal3~1_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|pla_decode_|Equal1~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y17_N24 +cycloneive_lcell_comb \z80_|pla_decode_|Equal3~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal3~0_combout = (\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3]) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [4]), + .datac(gnd), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal3~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal3~0 .lut_mask = 16'hCC00; +defparam \z80_|pla_decode_|Equal3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y13_N20 +cycloneive_lcell_comb \z80_|pla_decode_|Equal39~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal39~0_combout = (\z80_|pla_decode_|Equal40~0_combout & (\z80_|pla_decode_|Equal6~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal3~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal40~0_combout ), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal3~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal39~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal39~0 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal39~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~4_combout = (\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ) # ((\z80_|execute_|ixy_d~9_combout & ((\z80_|pla_decode_|Equal40~1_combout ) # (\z80_|pla_decode_|Equal39~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal40~1_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ), + .datac(\z80_|pla_decode_|Equal39~0_combout ), + .datad(\z80_|execute_|ixy_d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~4 .lut_mask = 16'hFECC; +defparam \z80_|execute_|ctl_reg_out_lo~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y18_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~0_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|M5~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|M5~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~0 .lut_mask = 16'h0F00; +defparam \z80_|execute_|ctl_alu_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|comb~0 ( +// Equation(s): +// \z80_|execute_|comb~0_combout = (\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|execute_|comb~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|comb~0 .lut_mask = 16'hF000; +defparam \z80_|execute_|comb~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N28 +cycloneive_lcell_comb \z80_|pla_decode_|Equal41~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal41~0_combout = (\z80_|ir_|opcode [6] & \z80_|ir_|opcode [7]) + + .dataa(\z80_|ir_|opcode [6]), + .datab(gnd), + .datac(gnd), + .datad(\z80_|ir_|opcode [7]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal41~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal41~0 .lut_mask = 16'hAA00; +defparam \z80_|pla_decode_|Equal41~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N30 +cycloneive_lcell_comb \z80_|pla_decode_|Equal47~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal47~0_combout = (\z80_|ir_|opcode [0] & (!\z80_|decode_state_|table_xx~0_combout & (\z80_|execute_|comb~0_combout & \z80_|pla_decode_|Equal41~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|decode_state_|table_xx~0_combout ), + .datac(\z80_|execute_|comb~0_combout ), + .datad(\z80_|pla_decode_|Equal41~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal47~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal47~0 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal47~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y18_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~32 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~32_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|pla_decode_|Equal47~0_combout & ((!\z80_|execute_|ctl_alu_oe~0_combout ) # (!\z80_|pla_decode_|Equal34~0_combout )))) # (!\z80_|execute_|ixy_d~7_combout & +// (((!\z80_|execute_|ctl_alu_oe~0_combout )) # (!\z80_|pla_decode_|Equal34~0_combout ))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|pla_decode_|Equal34~0_combout ), + .datac(\z80_|execute_|ctl_alu_oe~0_combout ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~32 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_inc_cy~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N22 +cycloneive_lcell_comb \z80_|pla_decode_|Equal19~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal19~0_combout = (\z80_|pla_decode_|Equal1~7_combout & (\z80_|pla_decode_|Equal32~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal3~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal1~7_combout ), + .datab(\z80_|pla_decode_|Equal32~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal3~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal19~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal19~0 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal19~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~9_combout = (\z80_|execute_|ctl_inc_cy~32_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|sequencer_|M5~q )) # (!\z80_|pla_decode_|Equal19~0_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~32_combout ), + .datab(\z80_|pla_decode_|Equal19~0_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|M5~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~9 .lut_mask = 16'hA2AA; +defparam \z80_|execute_|ctl_reg_out_lo~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~5_combout = ((\z80_|execute_|ctl_reg_out_lo~3_combout ) # ((\z80_|execute_|ctl_reg_out_lo~4_combout ) # (!\z80_|execute_|ctl_reg_out_lo~9_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~3_combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~4_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~5 .lut_mask = 16'hFDFF; +defparam \z80_|execute_|ctl_reg_out_lo~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~4 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~4_combout = (\z80_|decode_state_|DFFE_instED~q & (\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [7] & !\z80_|ir_|opcode [6]))) + + .dataa(\z80_|decode_state_|DFFE_instED~q ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~4 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_mWrite~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout = (\z80_|pla_decode_|Equal2~0_combout & (\z80_|execute_|ctl_mWrite~4_combout & (!\z80_|ir_|opcode [0] & \z80_|execute_|ctl_alu_op_low~22_combout ))) + + .dataa(\z80_|pla_decode_|Equal2~0_combout ), + .datab(\z80_|execute_|ctl_mWrite~4_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|execute_|ctl_alu_op_low~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~34 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~34_combout = (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [2] & (\z80_|ir_|opcode [1] & \z80_|execute_|ctl_mWrite~4_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|execute_|ctl_mWrite~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~34 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_mRead~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|execute_|ixy_d~15_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|execute_|ixy_d~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y17_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~36 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~36_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout & (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|execute_|ctl_mRead~34_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~36 .lut_mask = 16'h0015; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~5 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~5_combout = (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T4_ff~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~5 .lut_mask = 16'hC0C0; +defparam \z80_|execute_|ctl_mWrite~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N6 +cycloneive_lcell_comb \z80_|execute_|nextM~11 ( +// Equation(s): +// \z80_|execute_|nextM~11_combout = ((!\z80_|execute_|ctl_alu_op_low~25_combout & (!\z80_|execute_|ctl_alu_op_low~24_combout & !\z80_|pla_decode_|Equal56~0_combout ))) # (!\z80_|execute_|ctl_mWrite~5_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~25_combout ), + .datab(\z80_|execute_|ctl_mWrite~5_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~24_combout ), + .datad(\z80_|pla_decode_|Equal56~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~11 .lut_mask = 16'h3337; +defparam \z80_|execute_|nextM~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N26 +cycloneive_lcell_comb \z80_|pla_decode_|Equal20~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal20~0_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|execute_|comb~0_combout & !\z80_|ir_|opcode [5]))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|execute_|comb~0_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal20~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal20~0 .lut_mask = 16'h0080; +defparam \z80_|pla_decode_|Equal20~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y17_N10 +cycloneive_lcell_comb \z80_|pla_decode_|Equal13~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal13~2_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [4] & \z80_|pla_decode_|Equal13~1_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|pla_decode_|Equal13~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal13~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal13~2 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal13~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~24 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~24_combout = (\z80_|pla_decode_|Equal13~2_combout & !\z80_|ir_|opcode [3]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~24 .lut_mask = 16'h00F0; +defparam \z80_|execute_|ctl_mRead~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~27 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~27_combout = (\z80_|pla_decode_|Equal20~0_combout & (!\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ctl_mRead~24_combout ) # (!\z80_|execute_|ixy_d~6_combout )))) # (!\z80_|pla_decode_|Equal20~0_combout & +// (((!\z80_|execute_|ctl_mRead~24_combout ) # (!\z80_|execute_|ixy_d~6_combout )))) + + .dataa(\z80_|pla_decode_|Equal20~0_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ctl_mRead~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~27 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y17_N20 +cycloneive_lcell_comb \z80_|pla_decode_|Equal48~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal48~0_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [4] & \z80_|pla_decode_|Equal13~1_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|pla_decode_|Equal13~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal48~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal48~0 .lut_mask = 16'h0400; +defparam \z80_|pla_decode_|Equal48~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y16_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal10~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal10~0_combout = (!\z80_|ir_|opcode [1] & (\z80_|execute_|ctl_mWrite~4_combout & (!\z80_|ir_|opcode [2] & \z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [1]), + .datab(\z80_|execute_|ctl_mWrite~4_combout ), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal10~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal10~0 .lut_mask = 16'h0400; +defparam \z80_|pla_decode_|Equal10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y16_N0 +cycloneive_lcell_comb \z80_|pla_decode_|Equal11~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal11~0_combout = (!\z80_|ir_|opcode [1] & (\z80_|execute_|ctl_mWrite~4_combout & (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [1]), + .datab(\z80_|execute_|ctl_mWrite~4_combout ), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal11~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal11~0 .lut_mask = 16'h0004; +defparam \z80_|pla_decode_|Equal11~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N24 +cycloneive_lcell_comb \z80_|pla_decode_|Equal63~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal63~0_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|execute_|comb~0_combout & \z80_|ir_|opcode [5]))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|execute_|comb~0_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal63~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal63~0 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal63~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf2_we ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf2_we~combout = (\z80_|pla_decode_|Equal63~0_combout & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (!\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [3]))) + + .dataa(\z80_|pla_decode_|Equal63~0_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf2_we~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf2_we .lut_mask = 16'h0008; +defparam \z80_|execute_|ctl_flags_hf2_we .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~41 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~41_combout = (!\z80_|execute_|ctl_flags_hf2_we~combout & (((!\z80_|pla_decode_|Equal10~0_combout & !\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|execute_|ctl_flags_hf2_we~combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~41 .lut_mask = 16'h010F; +defparam \z80_|execute_|ctl_alu_shift_oe~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y13_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal68~3 ( +// Equation(s): +// \z80_|pla_decode_|Equal68~3_combout = (\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [1] & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal68~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal68~3 .lut_mask = 16'h0020; +defparam \z80_|pla_decode_|Equal68~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~7_combout = (\z80_|execute_|ctl_alu_op_low~27_combout ) # ((\z80_|pla_decode_|Equal68~3_combout ) # ((\z80_|pla_decode_|Equal21~0_combout & \z80_|pla_decode_|Equal63~0_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~27_combout ), + .datab(\z80_|pla_decode_|Equal68~3_combout ), + .datac(\z80_|pla_decode_|Equal21~0_combout ), + .datad(\z80_|pla_decode_|Equal63~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~7 .lut_mask = 16'hFEEE; +defparam \z80_|execute_|ctl_flags_bus~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~8_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|execute_|ctl_alu_op_low~25_combout ) # ((\z80_|execute_|ctl_flags_bus~7_combout ) # (\z80_|pla_decode_|Equal20~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~25_combout ), + .datab(\z80_|execute_|ctl_flags_bus~7_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|pla_decode_|Equal20~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~8 .lut_mask = 16'hF0E0; +defparam \z80_|execute_|ctl_flags_bus~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N18 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~9 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~9_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|execute_|ctl_alu_op_low~24_combout & !\z80_|pla_decode_|Equal56~0_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) + + .dataa(\z80_|execute_|ctl_alu_op_low~24_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|pla_decode_|Equal56~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~9 .lut_mask = 16'hCFDF; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~6_combout = (!\z80_|ir_|opcode [6] & !\z80_|ir_|opcode [7]) + + .dataa(\z80_|ir_|opcode [6]), + .datab(gnd), + .datac(gnd), + .datad(\z80_|ir_|opcode [7]), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~6 .lut_mask = 16'h0055; +defparam \z80_|execute_|ctl_ir_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~8_combout = (\z80_|execute_|ctl_ir_we~5_combout & (\z80_|execute_|ctl_ir_we~6_combout & ((!\z80_|decode_state_|DFFE_instCB~q ) # (!\z80_|pla_decode_|Equal33~0_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~5_combout ), + .datab(\z80_|execute_|ctl_ir_we~6_combout ), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|decode_state_|DFFE_instCB~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~8 .lut_mask = 16'h0888; +defparam \z80_|execute_|ctl_ir_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~14 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~14_combout = (\z80_|execute_|ctl_ir_we~5_combout & (!\z80_|ir_|opcode [7] & (\z80_|pla_decode_|Equal33~0_combout & !\z80_|ir_|opcode [6]))) + + .dataa(\z80_|execute_|ctl_ir_we~5_combout ), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~14 .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_ir_we~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~4_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~8_combout & !\z80_|execute_|ctl_ir_we~14_combout ))) # (!\z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|execute_|ctl_ir_we~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~4 .lut_mask = 16'hF3F7; +defparam \z80_|execute_|ctl_flags_bus~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~5_combout = (\z80_|execute_|ixy_d~10_combout ) # ((\z80_|pla_decode_|Equal63~0_combout & ((\z80_|pla_decode_|Equal32~0_combout ) # (\z80_|pla_decode_|Equal3~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal32~0_combout ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|execute_|ixy_d~10_combout ), + .datad(\z80_|pla_decode_|Equal3~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~5 .lut_mask = 16'hFCF8; +defparam \z80_|execute_|ctl_flags_bus~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~4 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~4_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal3~1_combout & (!\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~1_combout ), + .datab(\z80_|pla_decode_|Equal3~1_combout ), + .datac(\z80_|decode_state_|use_ixiy~combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~4 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_mRead~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~6_combout = ((!\z80_|execute_|ctl_flags_bus~5_combout & (!\z80_|pla_decode_|Equal13~2_combout & !\z80_|execute_|ctl_mRead~4_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) + + .dataa(\z80_|execute_|ctl_flags_bus~5_combout ), + .datab(\z80_|pla_decode_|Equal13~2_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|execute_|ctl_mRead~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~6 .lut_mask = 16'h0F1F; +defparam \z80_|execute_|ctl_flags_bus~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~9 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~9_combout = (!\z80_|execute_|ctl_flags_bus~8_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~9_combout & (\z80_|execute_|ctl_flags_bus~4_combout & \z80_|execute_|ctl_flags_bus~6_combout ))) + + .dataa(\z80_|execute_|ctl_flags_bus~8_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~9_combout ), + .datac(\z80_|execute_|ctl_flags_bus~4_combout ), + .datad(\z80_|execute_|ctl_flags_bus~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~9 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_flags_bus~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_iorw~11 ( +// Equation(s): +// \z80_|execute_|ctl_iorw~11_combout = (!\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_iorw~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_iorw~11 .lut_mask = 16'h0004; +defparam \z80_|execute_|ctl_iorw~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y16_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~17 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~17_combout = (\z80_|ir_|opcode [1] & (\z80_|execute_|ctl_mWrite~4_combout & (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [1]), + .datab(\z80_|execute_|ctl_mWrite~4_combout ), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~17 .lut_mask = 16'h0008; +defparam \z80_|execute_|ctl_mWrite~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y14_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~18 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~18_combout = ((!\z80_|execute_|ctl_iorw~11_combout & (!\z80_|execute_|ctl_mWrite~17_combout & !\z80_|execute_|ctl_mRead~34_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) + + .dataa(\z80_|execute_|ctl_iorw~11_combout ), + .datab(\z80_|execute_|ctl_mWrite~17_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~18 .lut_mask = 16'h01FF; +defparam \z80_|execute_|ctl_alu_shift_oe~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N14 +cycloneive_lcell_comb \z80_|pla_decode_|Equal37~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal37~0_combout = (!\z80_|ir_|opcode [0] & (!\z80_|decode_state_|table_xx~0_combout & (\z80_|pla_decode_|Equal1~4_combout & \z80_|pla_decode_|Equal41~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|decode_state_|table_xx~0_combout ), + .datac(\z80_|pla_decode_|Equal1~4_combout ), + .datad(\z80_|pla_decode_|Equal41~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal37~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal37~0 .lut_mask = 16'h1000; +defparam \z80_|pla_decode_|Equal37~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~19 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~19_combout = (\z80_|pla_decode_|Equal41~2_combout ) # ((\z80_|pla_decode_|Equal37~0_combout ) # ((\z80_|pla_decode_|Equal40~1_combout ) # (\z80_|pla_decode_|Equal34~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal41~2_combout ), + .datab(\z80_|pla_decode_|Equal37~0_combout ), + .datac(\z80_|pla_decode_|Equal40~1_combout ), + .datad(\z80_|pla_decode_|Equal34~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~19 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_alu_shift_oe~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N0 +cycloneive_lcell_comb \z80_|pla_decode_|Equal35~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal35~0_combout = (!\z80_|ir_|opcode [0] & (!\z80_|decode_state_|table_xx~0_combout & (\z80_|pla_decode_|Equal2~0_combout & \z80_|pla_decode_|Equal41~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|decode_state_|table_xx~0_combout ), + .datac(\z80_|pla_decode_|Equal2~0_combout ), + .datad(\z80_|pla_decode_|Equal41~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal35~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal35~0 .lut_mask = 16'h1000; +defparam \z80_|pla_decode_|Equal35~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y13_N0 +cycloneive_lcell_comb \z80_|pla_decode_|Equal21~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal21~1_combout = (\z80_|pla_decode_|Equal40~0_combout & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal21~0_combout & !\z80_|ir_|opcode [5]))) + + .dataa(\z80_|pla_decode_|Equal40~0_combout ), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|pla_decode_|Equal21~0_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal21~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal21~1 .lut_mask = 16'h0080; +defparam \z80_|pla_decode_|Equal21~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~17 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~17_combout = ((!\z80_|pla_decode_|Equal39~0_combout & (!\z80_|pla_decode_|Equal35~0_combout & !\z80_|pla_decode_|Equal21~1_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) + + .dataa(\z80_|pla_decode_|Equal39~0_combout ), + .datab(\z80_|pla_decode_|Equal35~0_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|pla_decode_|Equal21~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~17 .lut_mask = 16'h0F1F; +defparam \z80_|execute_|ctl_alu_shift_oe~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~20 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~20_combout = (\z80_|execute_|ctl_alu_shift_oe~18_combout & (\z80_|execute_|ctl_alu_shift_oe~17_combout & ((!\z80_|execute_|ctl_alu_shift_oe~19_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~18_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~19_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~20 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_alu_shift_oe~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~9 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~9_combout = (\z80_|pla_decode_|Equal41~0_combout & (\z80_|execute_|ctl_ir_we~5_combout & ((!\z80_|decode_state_|DFFE_instCB~q ) # (!\z80_|pla_decode_|Equal33~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|pla_decode_|Equal41~0_combout ), + .datac(\z80_|execute_|ctl_ir_we~5_combout ), + .datad(\z80_|decode_state_|DFFE_instCB~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~9 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_ir_we~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y20_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~11_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|execute_|ctl_ir_we~12_combout & !\z80_|execute_|ctl_ir_we~9_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) + + .dataa(\z80_|execute_|ctl_ir_we~12_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|execute_|ctl_ir_we~9_combout ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~11 .lut_mask = 16'hCDFF; +defparam \z80_|execute_|ctl_alu_bs_oe~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~15 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~15_combout = (\z80_|execute_|ctl_ir_we~5_combout & (\z80_|ir_|opcode [7] & (\z80_|pla_decode_|Equal33~0_combout & \z80_|ir_|opcode [6]))) + + .dataa(\z80_|execute_|ctl_ir_we~5_combout ), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~15 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_ir_we~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y20_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~7_combout = (\z80_|execute_|ctl_alu_bs_oe~11_combout & (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|execute_|ctl_ir_we~10_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~11_combout ), + .datad(\z80_|execute_|ctl_ir_we~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~7 .lut_mask = 16'h5070; +defparam \z80_|execute_|ctl_alu_bs_oe~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~7_combout = (\z80_|execute_|ctl_ir_we~5_combout & (\z80_|ir_|opcode [7] & (\z80_|pla_decode_|Equal33~0_combout & !\z80_|ir_|opcode [6]))) + + .dataa(\z80_|execute_|ctl_ir_we~5_combout ), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~7 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_ir_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N4 +cycloneive_lcell_comb \z80_|pla_decode_|Equal46~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal46~0_combout = (\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [0] & (\z80_|decode_state_|DFFE_instCB~q & \z80_|ir_|opcode [1]))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|ir_|opcode [0]), + .datac(\z80_|decode_state_|DFFE_instCB~q ), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal46~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal46~0 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal46~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~11 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~11_combout = (\z80_|ir_|opcode [6] & (!\z80_|ir_|opcode [7] & (\z80_|execute_|ctl_ir_we~5_combout & !\z80_|pla_decode_|Equal46~0_combout ))) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|execute_|ctl_ir_we~5_combout ), + .datad(\z80_|pla_decode_|Equal46~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~11 .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_ir_we~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~3 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~3_combout = (\z80_|execute_|ctl_alu_bs_oe~7_combout & (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~11_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~7_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_ir_we~7_combout ), + .datad(\z80_|execute_|ctl_ir_we~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~3 .lut_mask = 16'h222A; +defparam \z80_|execute_|ctl_bus_db_oe~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal52~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal52~1_combout = (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|decode_state_|DFFE_instED~q & (\z80_|pla_decode_|Equal41~0_combout & !\z80_|decode_state_|DFFE_instCB~q ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|decode_state_|DFFE_instED~q ), + .datac(\z80_|pla_decode_|Equal41~0_combout ), + .datad(\z80_|decode_state_|DFFE_instCB~q ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal52~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal52~1 .lut_mask = 16'h0020; +defparam \z80_|pla_decode_|Equal52~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~21 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~21_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal44~0_combout & !\z80_|pla_decode_|Equal52~1_combout ))) # (!\z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|pla_decode_|Equal44~0_combout ), + .datad(\z80_|pla_decode_|Equal52~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~21 .lut_mask = 16'hDDDF; +defparam \z80_|execute_|ctl_flags_xy_we~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~13 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~13_combout = (\z80_|execute_|ctl_flags_bus~9_combout & (\z80_|execute_|ctl_alu_shift_oe~20_combout & (\z80_|execute_|ctl_bus_db_oe~3_combout & \z80_|execute_|ctl_flags_xy_we~21_combout ))) + + .dataa(\z80_|execute_|ctl_flags_bus~9_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~20_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~3_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~13 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_flags_xy_we~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~6 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~6_combout = (!\z80_|decode_state_|DFFE_instIY1~q & (!\z80_|decode_state_|DFFE_inst4~q & (\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal44~0_combout ))) + + .dataa(\z80_|decode_state_|DFFE_instIY1~q ), + .datab(\z80_|decode_state_|DFFE_inst4~q ), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|pla_decode_|Equal44~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~6 .lut_mask = 16'h1000; +defparam \z80_|execute_|ctl_state_alu~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~14 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~14_combout = (\z80_|sequencer_|DFFE_M4_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~14 .lut_mask = 16'hA0A0; +defparam \z80_|execute_|ctl_alu_shift_oe~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~14 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~14_combout = (\z80_|execute_|ctl_alu_shift_oe~41_combout & (\z80_|execute_|ctl_flags_xy_we~13_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_state_alu~6_combout )))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~41_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~13_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~14 .lut_mask = 16'h0888; +defparam \z80_|execute_|ctl_flags_xy_we~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y19_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~24 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~24_combout = (\z80_|execute_|ctl_flags_xy_we~14_combout & (((!\z80_|pla_decode_|Equal48~0_combout & !\z80_|pla_decode_|Equal69~0_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|pla_decode_|Equal48~0_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|pla_decode_|Equal69~0_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~24 .lut_mask = 16'h3700; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y19_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~37 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~37_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout & (\z80_|execute_|nextM~11_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~27_combout & \z80_|execute_|ctl_reg_gp_sel[0]~24_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ), + .datab(\z80_|execute_|nextM~11_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~27_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~37 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel~7_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|decode_state_|table_xx~0_combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal41~0_combout ))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|decode_state_|table_xx~0_combout ), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|pla_decode_|Equal41~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel~7 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_reg_gp_sel~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|rsel0 ( +// Equation(s): +// \z80_|execute_|rsel0~combout = \z80_|ir_|opcode [0] $ (((\z80_|ir_|opcode [1] & \z80_|ir_|opcode [2]))) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|rsel0~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|rsel0 .lut_mask = 16'h3FC0; +defparam \z80_|execute_|rsel0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~3 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~3_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~3 .lut_mask = 16'h5050; +defparam \z80_|execute_|ctl_state_alu~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~0_combout = ((!\z80_|execute_|ctl_alu_op_low~24_combout & (!\z80_|execute_|ctl_alu_op_low~25_combout & !\z80_|pla_decode_|Equal56~0_combout ))) # (!\z80_|execute_|ctl_state_alu~3_combout ) + + .dataa(\z80_|execute_|ctl_state_alu~3_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~24_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~25_combout ), + .datad(\z80_|pla_decode_|Equal56~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~0 .lut_mask = 16'h5557; +defparam \z80_|execute_|ctl_reg_use_sp~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~2 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~2_combout = (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~2 .lut_mask = 16'hCC00; +defparam \z80_|execute_|ctl_state_alu~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout = (\z80_|execute_|ixy_d~15_combout & \z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|execute_|ixy_d~15_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 .lut_mask = 16'hAA00; +defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~30 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~30_combout = (\z80_|execute_|ctl_reg_use_sp~0_combout & (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout & ((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|ctl_mRead~34_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~34_combout ), + .datab(\z80_|execute_|ctl_reg_use_sp~0_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~30 .lut_mask = 16'h004C; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~12 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[0]~12_combout = ((!\z80_|pla_decode_|Equal39~0_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal40~1_combout ))) # (!\z80_|execute_|ixy_d~5_combout ) + + .dataa(\z80_|pla_decode_|Equal39~0_combout ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|pla_decode_|Equal40~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~12 .lut_mask = 16'h0F1F; +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~6_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~30_combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ), + .datab(\z80_|pla_decode_|Equal47~0_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~6 .lut_mask = 16'h20A0; +defparam \z80_|execute_|ctl_reg_out_lo~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~5 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~5_combout = (!\z80_|decode_state_|table_xx~0_combout & (!\z80_|pla_decode_|Equal33~0_combout & (\z80_|ir_|opcode [7] & !\z80_|ir_|opcode [6]))) + + .dataa(\z80_|decode_state_|table_xx~0_combout ), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~5 .lut_mask = 16'h0010; +defparam \z80_|execute_|ctl_state_alu~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~1 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~1_combout = ((!\z80_|execute_|ctl_ir_we~8_combout & (!\z80_|execute_|ctl_state_alu~5_combout & !\z80_|execute_|ctl_ir_we~11_combout ))) # (!\z80_|execute_|ctl_eval_cond~0_combout ) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_state_alu~5_combout ), + .datad(\z80_|execute_|ctl_ir_we~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~1 .lut_mask = 16'h3337; +defparam \z80_|execute_|ctl_sw_2u~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~1 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~1_combout = (\z80_|pla_decode_|Equal77~0_combout & ((\z80_|decode_state_|in_halt~q ) # ((!\z80_|pla_decode_|Equal33~0_combout & !\z80_|pla_decode_|Equal33~1_combout )))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|decode_state_|in_halt~q ), + .datac(\z80_|pla_decode_|Equal33~1_combout ), + .datad(\z80_|pla_decode_|Equal77~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~1 .lut_mask = 16'hCD00; +defparam \z80_|execute_|ctl_alu_oe~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~7 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~7_combout = (\z80_|pla_decode_|Equal77~0_combout & (\z80_|pla_decode_|Equal33~1_combout & (!\z80_|decode_state_|use_ixiy~combout & !\z80_|decode_state_|in_halt~q ))) + + .dataa(\z80_|pla_decode_|Equal77~0_combout ), + .datab(\z80_|pla_decode_|Equal33~1_combout ), + .datac(\z80_|decode_state_|use_ixiy~combout ), + .datad(\z80_|decode_state_|in_halt~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~7 .lut_mask = 16'h0008; +defparam \z80_|execute_|ctl_mWrite~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~4 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~4_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|execute_|ctl_alu_oe~1_combout & (!\z80_|execute_|ctl_mWrite~7_combout ))) # (!\z80_|execute_|ctl_eval_cond~0_combout & (((!\z80_|execute_|ctl_ir_we~4_combout ) # +// (!\z80_|execute_|ctl_mWrite~7_combout )))) + + .dataa(\z80_|execute_|ctl_alu_oe~1_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~7_combout ), + .datad(\z80_|execute_|ctl_ir_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~4 .lut_mask = 16'h0737; +defparam \z80_|execute_|ctl_sw_2u~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|setM1~57 ( +// Equation(s): +// \z80_|execute_|setM1~57_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~10_combout ))) # (!\z80_|sequencer_|DFFE_T4_ff~q ) .dataa(\z80_|execute_|ctl_ir_we~9_combout ), - .datab(\z80_|execute_|fMRead~29_combout ), - .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), - .datad(\z80_|execute_|ctl_ir_we~10_combout ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|execute_|ctl_ir_we~10_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), .cin(gnd), - .combout(\z80_|execute_|fMRead~30_combout ), + .combout(\z80_|execute_|setM1~57_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~30 .lut_mask = 16'hF0E0; -defparam \z80_|execute_|fMRead~30 .sum_lutc_input = "datac"; +defparam \z80_|execute_|setM1~57 .lut_mask = 16'hFF37; +defparam \z80_|execute_|setM1~57 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X41_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|fMRead~28 ( +// Location: LCCOMB_X29_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~5 ( // Equation(s): -// \z80_|execute_|fMRead~28_combout = ((\z80_|execute_|ixy_d~6_combout & ((\z80_|pla_decode_|Equal41~2_combout ) # (\z80_|pla_decode_|Equal9~1_combout )))) # (!\z80_|execute_|nextM~4_combout ) +// \z80_|execute_|ctl_sw_2u~5_combout = (\z80_|execute_|ctl_sw_2u~1_combout & (\z80_|execute_|ctl_sw_2u~4_combout & \z80_|execute_|setM1~57_combout )) - .dataa(\z80_|execute_|ixy_d~6_combout ), - .datab(\z80_|pla_decode_|Equal41~2_combout ), + .dataa(gnd), + .datab(\z80_|execute_|ctl_sw_2u~1_combout ), + .datac(\z80_|execute_|ctl_sw_2u~4_combout ), + .datad(\z80_|execute_|setM1~57_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~5 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_sw_2u~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~7_combout = (\z80_|execute_|ctl_reg_out_lo~6_combout & (((!\z80_|execute_|ctl_reg_gp_sel~7_combout & \z80_|execute_|ctl_sw_2u~5_combout )) # (!\z80_|execute_|rsel0~combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel~7_combout ), + .datab(\z80_|execute_|rsel0~combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~6_combout ), + .datad(\z80_|execute_|ctl_sw_2u~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~7 .lut_mask = 16'h7030; +defparam \z80_|execute_|ctl_reg_out_lo~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~0_combout = (\z80_|execute_|ctl_alu_shift_oe~14_combout & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|execute_|ctl_mWrite~4_combout & !\z80_|ir_|opcode [0]))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datab(\z80_|pla_decode_|Equal2~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~0 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~41 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~41_combout = (\z80_|execute_|ixy_d~9_combout & (((!\z80_|pla_decode_|Equal10~0_combout & !\z80_|pla_decode_|Equal11~0_combout )))) # (!\z80_|execute_|ixy_d~9_combout & (((!\z80_|pla_decode_|Equal11~0_combout )) # +// (!\z80_|execute_|ctl_alu_shift_oe~14_combout ))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datab(\z80_|execute_|ixy_d~9_combout ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|pla_decode_|Equal11~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~41 .lut_mask = 16'h113F; +defparam \z80_|execute_|ctl_bus_inc_oe~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~86 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~86_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|pla_decode_|Equal19~0_combout ) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|pla_decode_|Equal19~0_combout ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|sequencer_|M5~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~86_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~86 .lut_mask = 16'h3F7F; +defparam \z80_|execute_|ctl_inc_cy~86 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y18_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~88 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~88_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|pla_decode_|Equal34~0_combout ) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|pla_decode_|Equal34~0_combout ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~88_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~88 .lut_mask = 16'h37FF; +defparam \z80_|execute_|ctl_inc_cy~88 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~36 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~36_combout = (\z80_|execute_|ctl_inc_cy~88_combout & (((!\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ctl_alu_op_low~22_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|pla_decode_|Equal47~0_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datad(\z80_|execute_|ctl_inc_cy~88_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~36 .lut_mask = 16'h3700; +defparam \z80_|execute_|ctl_inc_cy~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~87 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~87_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|pla_decode_|Equal9~1_combout ) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|sequencer_|M5~q ), .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|execute_|nextM~4_combout ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), .cin(gnd), - .combout(\z80_|execute_|fMRead~28_combout ), + .combout(\z80_|execute_|ctl_inc_cy~87_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~28 .lut_mask = 16'hA8FF; -defparam \z80_|execute_|fMRead~28 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_inc_cy~87 .lut_mask = 16'h1FFF; +defparam \z80_|execute_|ctl_inc_cy~87 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X41_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|fMRead~32 ( +// Location: LCCOMB_X20_Y18_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~26 ( // Equation(s): -// \z80_|execute_|fMRead~32_combout = ((\z80_|execute_|fMRead~31_combout ) # ((\z80_|execute_|fMRead~30_combout ) # (\z80_|execute_|fMRead~28_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ) +// \z80_|execute_|ctl_bus_inc_oe~26_combout = (\z80_|execute_|ctl_inc_cy~86_combout & (\z80_|execute_|ctl_inc_cy~36_combout & \z80_|execute_|ctl_inc_cy~87_combout )) - .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~13_combout ), - .datab(\z80_|execute_|fMRead~31_combout ), - .datac(\z80_|execute_|fMRead~30_combout ), - .datad(\z80_|execute_|fMRead~28_combout ), + .dataa(\z80_|execute_|ctl_inc_cy~86_combout ), + .datab(\z80_|execute_|ctl_inc_cy~36_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_inc_cy~87_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~32_combout ), + .combout(\z80_|execute_|ctl_bus_inc_oe~26_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~32 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|fMRead~32 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_inc_oe~26 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_bus_inc_oe~26 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y18_N30 +// Location: LCCOMB_X30_Y19_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~9 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~9_combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_M4_ff~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~9 .lut_mask = 16'hC0C0; +defparam \z80_|execute_|ctl_mWrite~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y18_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~1 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we~1_combout = (\z80_|pla_decode_|Equal10~0_combout & (((\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (\z80_|execute_|ctl_mWrite~9_combout )))) # (!\z80_|pla_decode_|Equal10~0_combout & (\z80_|execute_|ctl_mRead~34_combout +// & ((\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (\z80_|execute_|ctl_mWrite~9_combout )))) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datad(\z80_|execute_|ctl_mWrite~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we~1 .lut_mask = 16'hEEE0; +defparam \z80_|execute_|ctl_reg_sys_we~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y18_N20 cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~42 ( // Equation(s): -// \z80_|execute_|ctl_bus_inc_oe~42_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~5_combout & (\z80_|execute_|ctl_inc_cy~77_combout & \z80_|execute_|ctl_inc_cy~53_combout )) +// \z80_|execute_|ctl_bus_inc_oe~42_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~0_combout & (\z80_|execute_|ctl_bus_inc_oe~41_combout & (\z80_|execute_|ctl_bus_inc_oe~26_combout & !\z80_|execute_|ctl_reg_sys_we~1_combout ))) - .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), - .datab(\z80_|execute_|ctl_inc_cy~77_combout ), - .datac(\z80_|execute_|ctl_inc_cy~53_combout ), - .datad(gnd), + .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~0_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~26_combout ), + .datad(\z80_|execute_|ctl_reg_sys_we~1_combout ), .cin(gnd), .combout(\z80_|execute_|ctl_bus_inc_oe~42_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_inc_oe~42 .lut_mask = 16'h8080; +defparam \z80_|execute_|ctl_bus_inc_oe~42 .lut_mask = 16'h0040; defparam \z80_|execute_|ctl_bus_inc_oe~42 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y18_N12 -cycloneive_lcell_comb \z80_|execute_|fMRead~14 ( +// Location: LCCOMB_X21_Y16_N22 +cycloneive_lcell_comb \z80_|pla_decode_|Equal40~2 ( // Equation(s): -// \z80_|execute_|fMRead~14_combout = (\z80_|execute_|ctl_mRead~23_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout ) # ((\z80_|execute_|ctl_mRead~15_combout ) # (\z80_|execute_|ctl_ir_we~12_combout ))) +// \z80_|pla_decode_|Equal40~2_combout = (!\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal6~0_combout & (!\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [0]))) - .dataa(\z80_|execute_|ctl_mRead~23_combout ), + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal40~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal40~2 .lut_mask = 16'h0004; +defparam \z80_|pla_decode_|Equal40~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~14 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~14_combout = (!\z80_|pla_decode_|Equal52~1_combout & (((\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal40~2_combout )) # (!\z80_|pla_decode_|Equal21~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal52~1_combout ), + .datab(\z80_|pla_decode_|Equal21~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal40~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~14 .lut_mask = 16'h5155; +defparam \z80_|execute_|ctl_reg_sel_pc~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y16_N28 +cycloneive_lcell_comb \z80_|pla_decode_|Equal55~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal55~0_combout = (!\z80_|ir_|opcode [2] & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [0])) + + .dataa(\z80_|ir_|opcode [2]), + .datab(gnd), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal55~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal55~0 .lut_mask = 16'h0050; +defparam \z80_|pla_decode_|Equal55~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~11 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~11_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal55~0_combout & \z80_|ir_|opcode [3]))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~11 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_mRead~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N4 +cycloneive_lcell_comb \z80_|pla_decode_|Equal6~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal6~1_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal1~4_combout & \z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|pla_decode_|Equal1~4_combout ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal6~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal6~1 .lut_mask = 16'h4000; +defparam \z80_|pla_decode_|Equal6~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|setM1~36 ( +// Equation(s): +// \z80_|execute_|setM1~36_combout = (!\z80_|pla_decode_|Equal6~1_combout & (((!\z80_|ir_|opcode [5] & !\z80_|pla_decode_|Equal3~0_combout )) # (!\z80_|pla_decode_|Equal40~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal6~1_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal3~0_combout ), + .datad(\z80_|pla_decode_|Equal40~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~36 .lut_mask = 16'h0155; +defparam \z80_|execute_|setM1~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|comb~1 ( +// Equation(s): +// \z80_|execute_|comb~1_combout = (\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4]) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [5]), + .datac(gnd), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|comb~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|comb~1 .lut_mask = 16'hCC00; +defparam \z80_|execute_|comb~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~13 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~13_combout = (\z80_|execute_|comb~1_combout & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal55~0_combout ))) + + .dataa(\z80_|execute_|comb~1_combout ), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~13 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_mRead~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~11 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~11_combout = (!\z80_|pla_decode_|Equal41~2_combout & (!\z80_|execute_|ctl_mRead~13_combout & (!\z80_|execute_|ctl_mRead~8_combout & !\z80_|execute_|ctl_mRead~6_combout ))) + + .dataa(\z80_|pla_decode_|Equal41~2_combout ), + .datab(\z80_|execute_|ctl_mRead~13_combout ), + .datac(\z80_|execute_|ctl_mRead~8_combout ), + .datad(\z80_|execute_|ctl_mRead~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~11 .lut_mask = 16'h0001; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N28 +cycloneive_lcell_comb \z80_|pla_decode_|Equal24~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal24~0_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|pla_decode_|Equal2~0_combout & !\z80_|ir_|opcode [5]))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal52~0_combout ), + .datac(\z80_|pla_decode_|Equal2~0_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal24~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal24~0 .lut_mask = 16'h0080; +defparam \z80_|pla_decode_|Equal24~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N12 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~26 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~26_combout = (!\z80_|pla_decode_|Equal35~0_combout & ((\z80_|ir_|opcode [4]) # ((\z80_|ir_|opcode [3]) # (!\z80_|pla_decode_|Equal24~0_combout )))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|pla_decode_|Equal35~0_combout ), + .datad(\z80_|pla_decode_|Equal24~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~26 .lut_mask = 16'h0E0F; +defparam \z80_|execute_|pc_inc_hold~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|setM1~37 ( +// Equation(s): +// \z80_|execute_|setM1~37_combout = (!\z80_|pla_decode_|Equal19~0_combout & (\z80_|execute_|setM1~36_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~11_combout & \z80_|execute_|pc_inc_hold~26_combout ))) + + .dataa(\z80_|pla_decode_|Equal19~0_combout ), + .datab(\z80_|execute_|setM1~36_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~11_combout ), + .datad(\z80_|execute_|pc_inc_hold~26_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~37 .lut_mask = 16'h4000; +defparam \z80_|execute_|setM1~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~6 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~6_combout = (!\z80_|pla_decode_|Equal33~2_combout & (((!\z80_|pla_decode_|Equal50~0_combout & !\z80_|pla_decode_|Equal49~0_combout )) # (!\z80_|decode_state_|use_ixiy~combout ))) + + .dataa(\z80_|decode_state_|use_ixiy~combout ), + .datab(\z80_|pla_decode_|Equal50~0_combout ), + .datac(\z80_|pla_decode_|Equal33~2_combout ), + .datad(\z80_|pla_decode_|Equal49~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~6 .lut_mask = 16'h0507; +defparam \z80_|execute_|pc_inc_hold~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo~38 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo~38_combout = (\z80_|execute_|pc_inc_hold~6_combout & (((!\z80_|pla_decode_|Equal33~1_combout ) # (!\z80_|pla_decode_|Equal6~0_combout )) # (!\z80_|pla_decode_|Equal55~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|pla_decode_|Equal33~1_combout ), + .datad(\z80_|execute_|pc_inc_hold~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo~38 .lut_mask = 16'h7F00; +defparam \z80_|execute_|ctl_reg_sys_hilo~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|fMRead~7 ( +// Equation(s): +// \z80_|execute_|fMRead~7_combout = (\z80_|execute_|ctl_reg_sel_pc~14_combout & (!\z80_|execute_|ctl_mRead~11_combout & (\z80_|execute_|setM1~37_combout & \z80_|execute_|ctl_reg_sys_hilo~38_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~14_combout ), + .datab(\z80_|execute_|ctl_mRead~11_combout ), + .datac(\z80_|execute_|setM1~37_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo~38_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~7 .lut_mask = 16'h2000; +defparam \z80_|execute_|fMRead~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~12 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~12_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal6~0_combout & !\z80_|pla_decode_|Equal33~1_combout )) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~12 .lut_mask = 16'h0088; +defparam \z80_|execute_|ctl_mRead~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~31 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~31_combout = (!\z80_|execute_|ctl_mRead~12_combout & ((\z80_|ir_|opcode [3]) # ((\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal12~0_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~12_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|pla_decode_|Equal12~0_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~31 .lut_mask = 16'h5545; +defparam \z80_|execute_|ctl_bus_inc_oe~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_alu_shift_oe~14_combout & \z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~1_combout ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N12 +cycloneive_lcell_comb \z80_|nM1_int~2 ( +// Equation(s): +// \z80_|nM1_int~2_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|nM1_int~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|nM1_int~2 .lut_mask = 16'h000F; +defparam \z80_|nM1_int~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~0 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~0_combout = (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|M5~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(gnd), + .datad(\z80_|sequencer_|M5~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~0 .lut_mask = 16'hCC00; +defparam \z80_|execute_|ctl_sw_4u~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~10 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~10_combout = (\z80_|execute_|ctl_mRead~8_combout & (!\z80_|execute_|ctl_alu_shift_oe~14_combout & (!\z80_|execute_|ctl_sw_4u~0_combout ))) # (!\z80_|execute_|ctl_mRead~8_combout & +// (((!\z80_|execute_|ctl_alu_shift_oe~14_combout & !\z80_|execute_|ctl_sw_4u~0_combout )) # (!\z80_|execute_|ctl_mRead~6_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~8_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datac(\z80_|execute_|ctl_sw_4u~0_combout ), + .datad(\z80_|execute_|ctl_mRead~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~10 .lut_mask = 16'h0357; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|fMRead~6 ( +// Equation(s): +// \z80_|execute_|fMRead~6_combout = (\z80_|execute_|ctl_mRead~13_combout & (!\z80_|execute_|ctl_alu_shift_oe~14_combout & ((!\z80_|execute_|ctl_alu_op_low~22_combout ) # (!\z80_|execute_|ctl_state_alu~6_combout )))) # +// (!\z80_|execute_|ctl_mRead~13_combout & (((!\z80_|execute_|ctl_alu_op_low~22_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~13_combout ), + .datab(\z80_|execute_|ctl_state_alu~6_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~6 .lut_mask = 16'h153F; +defparam \z80_|execute_|fMRead~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~12 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~12_combout = (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|execute_|ctl_mWrite~17_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|sequencer_|DFFE_M4_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|execute_|ctl_mWrite~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~12 .lut_mask = 16'h5F7F; +defparam \z80_|execute_|ctl_inc_dec~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~15 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~15_combout = (!\z80_|nM1_int~2_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout & (\z80_|execute_|fMRead~6_combout & \z80_|execute_|ctl_inc_dec~12_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), + .datac(\z80_|execute_|fMRead~6_combout ), + .datad(\z80_|execute_|ctl_inc_dec~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~15 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N28 +cycloneive_lcell_comb \z80_|pla_decode_|Equal25~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal25~0_combout = (!\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal55~0_combout ))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal25~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal25~0 .lut_mask = 16'h4000; +defparam \z80_|pla_decode_|Equal25~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal12~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal12~1_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal2~0_combout & !\z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|pla_decode_|Equal2~0_combout ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal12~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal12~1 .lut_mask = 16'h0040; +defparam \z80_|pla_decode_|Equal12~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~38 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~38_combout = ((\z80_|pla_decode_|Equal12~1_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~14_combout & !\z80_|execute_|ctl_sw_4u~0_combout ))) # (!\z80_|pla_decode_|Equal25~0_combout ) + + .dataa(\z80_|pla_decode_|Equal25~0_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datac(\z80_|pla_decode_|Equal12~1_combout ), + .datad(\z80_|execute_|ctl_sw_4u~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~38 .lut_mask = 16'hF5F7; +defparam \z80_|execute_|ctl_inc_cy~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~82 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~82_combout = ((!\z80_|sequencer_|DFFE_M2_ff~q ) # (!\z80_|pla_decode_|Equal13~2_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|pla_decode_|Equal13~2_combout ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~82_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~82 .lut_mask = 16'h77FF; +defparam \z80_|execute_|ctl_inc_cy~82 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~14 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~14_combout = (\z80_|execute_|ctl_inc_cy~38_combout & (\z80_|execute_|ctl_inc_cy~39_combout & (\z80_|execute_|ctl_reg_sel_pc~10_combout & \z80_|execute_|ctl_inc_cy~82_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~38_combout ), + .datab(\z80_|execute_|ctl_inc_cy~39_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~10_combout ), + .datad(\z80_|execute_|ctl_inc_cy~82_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~14 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~16 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~16_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout & +// \z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~16 .lut_mask = 16'h1000; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~32 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~32_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~16_combout & (((\z80_|execute_|fMRead~7_combout & \z80_|execute_|ctl_bus_inc_oe~31_combout )) # (!\z80_|execute_|ctl_alu_op_low~22_combout ))) + + .dataa(\z80_|execute_|fMRead~7_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~31_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~32 .lut_mask = 16'hB300; +defparam \z80_|execute_|ctl_bus_inc_oe~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~77 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~77_combout = (\z80_|execute_|ixy_d~5_combout & (((!\z80_|pla_decode_|Equal37~0_combout & !\z80_|pla_decode_|Equal38~2_combout )))) # (!\z80_|execute_|ixy_d~5_combout & (((!\z80_|pla_decode_|Equal37~0_combout & +// !\z80_|pla_decode_|Equal38~2_combout )) # (!\z80_|execute_|ctl_alu_op_low~22_combout ))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datac(\z80_|pla_decode_|Equal37~0_combout ), + .datad(\z80_|pla_decode_|Equal38~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~77_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~77 .lut_mask = 16'h111F; +defparam \z80_|execute_|ctl_inc_cy~77 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N4 +cycloneive_lcell_comb \z80_|pla_decode_|Equal29~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal29~0_combout = (\z80_|pla_decode_|Equal1~7_combout & (\z80_|pla_decode_|Equal32~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal1~4_combout ))) + + .dataa(\z80_|pla_decode_|Equal1~7_combout ), + .datab(\z80_|pla_decode_|Equal32~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal1~4_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal29~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal29~0 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal29~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~78 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~78_combout = (\z80_|execute_|ctl_inc_cy~77_combout & (((!\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ctl_alu_op_low~22_combout )) # (!\z80_|pla_decode_|Equal29~0_combout ))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datac(\z80_|execute_|ctl_inc_cy~77_combout ), + .datad(\z80_|pla_decode_|Equal29~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~78_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~78 .lut_mask = 16'h10F0; +defparam \z80_|execute_|ctl_inc_cy~78 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~79 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~79_combout = (\z80_|execute_|ctl_inc_cy~78_combout & (((!\z80_|execute_|ctl_sw_4u~0_combout & !\z80_|execute_|ctl_alu_shift_oe~14_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) + + .dataa(\z80_|execute_|ctl_sw_4u~0_combout ), + .datab(\z80_|pla_decode_|Equal47~0_combout ), + .datac(\z80_|execute_|ctl_inc_cy~78_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~79_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~79 .lut_mask = 16'h3070; +defparam \z80_|execute_|ctl_inc_cy~79 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~14 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~14_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal1~4_combout ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal52~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal1~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~14 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_mRead~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y18_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~49 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~49_combout = (\z80_|execute_|ixy_d~5_combout & (!\z80_|pla_decode_|Equal9~1_combout & (!\z80_|execute_|ctl_mRead~14_combout ))) # (!\z80_|execute_|ixy_d~5_combout & (((!\z80_|pla_decode_|Equal9~1_combout & +// !\z80_|execute_|ctl_mRead~14_combout )) # (!\z80_|execute_|ctl_alu_op_low~22_combout ))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|pla_decode_|Equal9~1_combout ), + .datac(\z80_|execute_|ctl_mRead~14_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~49_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~49 .lut_mask = 16'h0357; +defparam \z80_|execute_|ctl_inc_cy~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y18_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~5_combout = ((!\z80_|pla_decode_|Equal11~0_combout & (!\z80_|execute_|ctl_mRead~34_combout & !\z80_|pla_decode_|Equal10~0_combout ))) # (!\z80_|execute_|ctl_alu_op_low~22_combout ) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~5 .lut_mask = 16'h01FF; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y18_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~40 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~40_combout = (\z80_|execute_|ctl_inc_cy~79_combout & (\z80_|execute_|ctl_inc_cy~49_combout & \z80_|execute_|ctl_reg_gp_sel[1]~5_combout )) + + .dataa(\z80_|execute_|ctl_inc_cy~79_combout ), + .datab(\z80_|execute_|ctl_inc_cy~49_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~40 .lut_mask = 16'h8080; +defparam \z80_|execute_|ctl_bus_inc_oe~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~5 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~5_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal33~1_combout & (!\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|pla_decode_|Equal33~1_combout ), + .datac(\z80_|decode_state_|use_ixiy~combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~5 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_mRead~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~44 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~44_combout = (\z80_|decode_state_|DFFE_inst4~q ) # ((\z80_|decode_state_|DFFE_instIY1~q ) # ((!\z80_|pla_decode_|Equal49~0_combout & !\z80_|pla_decode_|Equal50~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal49~0_combout ), + .datab(\z80_|decode_state_|DFFE_inst4~q ), + .datac(\z80_|pla_decode_|Equal50~0_combout ), + .datad(\z80_|decode_state_|DFFE_instIY1~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~44 .lut_mask = 16'hFFCD; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~36 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~36_combout = (\z80_|execute_|ctl_mRead~5_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout ) # ((\z80_|execute_|ctl_mRead~4_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~5_combout ), .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_mRead~15_combout ), - .datad(\z80_|execute_|ctl_ir_we~12_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ), + .datad(\z80_|execute_|ctl_mRead~4_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~14_combout ), + .combout(\z80_|execute_|ctl_bus_inc_oe~36_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~14 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|fMRead~14 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_inc_oe~36 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|ctl_bus_inc_oe~36 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y18_N18 -cycloneive_lcell_comb \z80_|execute_|fMRead~10 ( +// Location: LCCOMB_X21_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~35 ( // Equation(s): -// \z80_|execute_|fMRead~10_combout = (!\z80_|execute_|ctl_mRead~4_combout & (!\z80_|pla_decode_|Equal6~1_combout & (!\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_bus_db_oe~1_combout ))) +// \z80_|execute_|ctl_bus_inc_oe~35_combout = (\z80_|execute_|ctl_state_alu~6_combout ) # ((\z80_|pla_decode_|Equal13~2_combout ) # (\z80_|execute_|ctl_mRead~8_combout )) - .dataa(\z80_|execute_|ctl_mRead~4_combout ), - .datab(\z80_|pla_decode_|Equal6~1_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .dataa(\z80_|execute_|ctl_state_alu~6_combout ), + .datab(\z80_|pla_decode_|Equal13~2_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_mRead~8_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~10_combout ), + .combout(\z80_|execute_|ctl_bus_inc_oe~35_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~10 .lut_mask = 16'h0100; -defparam \z80_|execute_|fMRead~10 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_inc_oe~35 .lut_mask = 16'hFFEE; +defparam \z80_|execute_|ctl_bus_inc_oe~35 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y18_N28 -cycloneive_lcell_comb \z80_|execute_|fMRead~9 ( +// Location: LCCOMB_X21_Y17_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~46 ( // Equation(s): -// \z80_|execute_|fMRead~9_combout = (\z80_|execute_|ctl_mRead~23_combout ) # (((\z80_|execute_|ctl_mRead~13_combout ) # (!\z80_|execute_|nextM~3_combout )) # (!\z80_|execute_|pc_inc_hold~28_combout )) +// \z80_|execute_|ctl_bus_inc_oe~46_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|execute_|ctl_bus_inc_oe~36_combout ) # (\z80_|execute_|ctl_bus_inc_oe~35_combout )))) - .dataa(\z80_|execute_|ctl_mRead~23_combout ), - .datab(\z80_|execute_|pc_inc_hold~28_combout ), - .datac(\z80_|execute_|ctl_mRead~13_combout ), - .datad(\z80_|execute_|nextM~3_combout ), + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|execute_|ctl_bus_inc_oe~36_combout ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|execute_|ctl_bus_inc_oe~35_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~9_combout ), + .combout(\z80_|execute_|ctl_bus_inc_oe~46_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~9 .lut_mask = 16'hFBFF; -defparam \z80_|execute_|fMRead~9 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_inc_oe~46 .lut_mask = 16'h5040; +defparam \z80_|execute_|ctl_bus_inc_oe~46 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y18_N24 -cycloneive_lcell_comb \z80_|execute_|fMRead~11 ( +// Location: LCCOMB_X24_Y11_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~33 ( // Equation(s): -// \z80_|execute_|fMRead~11_combout = (\z80_|execute_|ctl_state_alu~4_combout & (((\z80_|execute_|ctl_ir_we~14_combout ) # (\z80_|execute_|fMRead~9_combout )) # (!\z80_|execute_|fMRead~10_combout ))) +// \z80_|execute_|ctl_bus_inc_oe~33_combout = (\z80_|execute_|pc_inc_hold~26_combout & (!\z80_|pla_decode_|Equal6~1_combout & ((!\z80_|pla_decode_|Equal33~2_combout ) # (!\z80_|decode_state_|use_ixiy~combout )))) - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|fMRead~10_combout ), - .datac(\z80_|execute_|ctl_ir_we~14_combout ), - .datad(\z80_|execute_|fMRead~9_combout ), + .dataa(\z80_|decode_state_|use_ixiy~combout ), + .datab(\z80_|execute_|pc_inc_hold~26_combout ), + .datac(\z80_|pla_decode_|Equal6~1_combout ), + .datad(\z80_|pla_decode_|Equal33~2_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~11_combout ), + .combout(\z80_|execute_|ctl_bus_inc_oe~33_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~11 .lut_mask = 16'hAAA2; -defparam \z80_|execute_|fMRead~11 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_inc_oe~33 .lut_mask = 16'h040C; +defparam \z80_|execute_|ctl_bus_inc_oe~33 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X35_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|fMRead~12 ( +// Location: LCCOMB_X21_Y17_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~47 ( // Equation(s): -// \z80_|execute_|fMRead~12_combout = (\z80_|execute_|ctl_ir_we~8_combout ) # ((\z80_|execute_|ctl_ir_we~14_combout ) # ((\z80_|pla_decode_|Equal49~0_combout & !\z80_|decode_state_|use_ixiy~combout ))) +// \z80_|execute_|ctl_bus_inc_oe~47_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & ((!\z80_|execute_|ctl_bus_inc_oe~33_combout ) # (!\z80_|execute_|nextM~2_combout )))) - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|execute_|nextM~2_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~47 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_bus_inc_oe~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal8~0_combout & (\z80_|sequencer_|DFFE_T5_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ))) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(\z80_|pla_decode_|Equal8~0_combout ), + .datac(\z80_|sequencer_|DFFE_T5_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~45 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~45_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout & (((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|pla_decode_|Equal11~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~45 .lut_mask = 16'h070F; +defparam \z80_|execute_|ctl_bus_inc_oe~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~34 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~34_combout = ((\z80_|execute_|ctl_alu_oe~0_combout & ((\z80_|execute_|ctl_mRead~4_combout ) # (\z80_|execute_|ctl_mRead~8_combout )))) # (!\z80_|execute_|ctl_bus_inc_oe~45_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~45_combout ), + .datab(\z80_|execute_|ctl_mRead~4_combout ), + .datac(\z80_|execute_|ctl_alu_oe~0_combout ), + .datad(\z80_|execute_|ctl_mRead~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~34 .lut_mask = 16'hF5D5; +defparam \z80_|execute_|ctl_bus_inc_oe~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout = (\z80_|pla_decode_|Equal9~1_combout & (\z80_|sequencer_|M5~q & \z80_|sequencer_|DFFE_T4_ff~q )) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(gnd), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~6 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~6_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal52~0_combout & \z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal3~1_combout ), + .datac(\z80_|pla_decode_|Equal52~0_combout ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~6 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_mWrite~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~50 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~50_combout = (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|execute_|ctl_mWrite~6_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|execute_|ctl_mWrite~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~50_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~50 .lut_mask = 16'h37FF; +defparam \z80_|execute_|ctl_bus_inc_oe~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal4~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal4~0_combout = (\z80_|pla_decode_|Equal1~4_combout & (\z80_|pla_decode_|Equal1~7_combout & (\z80_|ir_|opcode [3] & \z80_|execute_|comb~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal1~4_combout ), + .datab(\z80_|pla_decode_|Equal1~7_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|execute_|comb~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal4~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal4~0 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~48 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~48_combout = (\z80_|execute_|ctl_bus_inc_oe~50_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|pla_decode_|Equal4~0_combout )) # (!\z80_|sequencer_|DFFE_T5_ff~q ))) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~50_combout ), + .datab(\z80_|sequencer_|DFFE_T5_ff~q ), + .datac(\z80_|pla_decode_|Equal4~0_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~48 .lut_mask = 16'hAA2A; +defparam \z80_|execute_|ctl_bus_inc_oe~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~49 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~49_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q ))) # (!\z80_|execute_|ctl_mRead~6_combout ) + + .dataa(\z80_|sequencer_|M5~q ), + .datab(\z80_|execute_|ctl_mRead~6_combout ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~49_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~49 .lut_mask = 16'hFF37; +defparam \z80_|execute_|ctl_bus_inc_oe~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~7 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~7_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal55~0_combout & \z80_|pla_decode_|Equal6~0_combout )) + + .dataa(\z80_|pla_decode_|Equal33~1_combout ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~7 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_mRead~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~29 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~29_combout = (\z80_|execute_|ixy_d~5_combout & (!\z80_|execute_|ctl_mWrite~17_combout & ((!\z80_|execute_|ctl_ir_we~4_combout ) # (!\z80_|execute_|ctl_mRead~7_combout )))) # (!\z80_|execute_|ixy_d~5_combout & +// (((!\z80_|execute_|ctl_ir_we~4_combout )) # (!\z80_|execute_|ctl_mRead~7_combout ))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_mRead~7_combout ), + .datac(\z80_|execute_|ctl_mWrite~17_combout ), + .datad(\z80_|execute_|ctl_ir_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~29 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_bus_inc_oe~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~11_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # (((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|sequencer_|M5~q )) + + .dataa(\z80_|execute_|ctl_ir_we~9_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|M5~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~11 .lut_mask = 16'hF1FF; +defparam \z80_|execute_|ctl_alu_core_S~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y17_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~27 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~27_combout = (\z80_|execute_|ctl_alu_oe~0_combout & (!\z80_|execute_|ctl_ir_we~14_combout & ((!\z80_|execute_|ctl_ir_we~8_combout )))) # (!\z80_|execute_|ctl_alu_oe~0_combout & (((!\z80_|execute_|ixy_d~7_combout )) # +// (!\z80_|execute_|ctl_ir_we~14_combout ))) + + .dataa(\z80_|execute_|ctl_alu_oe~0_combout ), .datab(\z80_|execute_|ctl_ir_we~14_combout ), - .datac(\z80_|pla_decode_|Equal49~0_combout ), - .datad(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ctl_ir_we~8_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~12_combout ), + .combout(\z80_|execute_|ctl_bus_inc_oe~27_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~12 .lut_mask = 16'hEEFE; -defparam \z80_|execute_|fMRead~12 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_inc_oe~27 .lut_mask = 16'h1537; +defparam \z80_|execute_|ctl_bus_inc_oe~27 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y18_N14 -cycloneive_lcell_comb \z80_|execute_|fMRead~13 ( +// Location: LCCOMB_X23_Y19_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~44 ( // Equation(s): -// \z80_|execute_|fMRead~13_combout = (!\z80_|execute_|fMWrite~5_combout & ((\z80_|execute_|fMRead~12_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout ) # (\z80_|execute_|ctl_mRead~6_combout )))) +// \z80_|execute_|ctl_bus_inc_oe~44_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~7_combout )) # (!\z80_|sequencer_|M5~q )) - .dataa(\z80_|execute_|fMRead~12_combout ), - .datab(\z80_|execute_|ctl_ir_we~11_combout ), - .datac(\z80_|execute_|ctl_mRead~6_combout ), - .datad(\z80_|execute_|fMWrite~5_combout ), + .dataa(\z80_|execute_|ctl_ir_we~10_combout ), + .datab(\z80_|execute_|ctl_ir_we~7_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|M5~q ), .cin(gnd), - .combout(\z80_|execute_|fMRead~13_combout ), + .combout(\z80_|execute_|ctl_bus_inc_oe~44_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~13 .lut_mask = 16'h00FE; -defparam \z80_|execute_|fMRead~13 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_inc_oe~44 .lut_mask = 16'hF1FF; +defparam \z80_|execute_|ctl_bus_inc_oe~44 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y18_N30 -cycloneive_lcell_comb \z80_|execute_|fMRead~15 ( +// Location: LCCOMB_X25_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~28 ( // Equation(s): -// \z80_|execute_|fMRead~15_combout = (\z80_|execute_|fMRead~11_combout ) # ((\z80_|execute_|fMRead~13_combout ) # ((\z80_|execute_|fMRead~14_combout & \z80_|execute_|ctl_state_alu~6_combout ))) +// \z80_|execute_|ctl_bus_inc_oe~28_combout = (\z80_|execute_|ctl_alu_core_S~11_combout & (\z80_|execute_|ctl_bus_inc_oe~27_combout & \z80_|execute_|ctl_bus_inc_oe~44_combout )) - .dataa(\z80_|execute_|fMRead~14_combout ), - .datab(\z80_|execute_|fMRead~11_combout ), - .datac(\z80_|execute_|fMRead~13_combout ), - .datad(\z80_|execute_|ctl_state_alu~6_combout ), + .dataa(\z80_|execute_|ctl_alu_core_S~11_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~27_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_bus_inc_oe~44_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~15_combout ), + .combout(\z80_|execute_|ctl_bus_inc_oe~28_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~15 .lut_mask = 16'hFEFC; -defparam \z80_|execute_|fMRead~15 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_inc_oe~28 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_bus_inc_oe~28 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y17_N2 -cycloneive_lcell_comb \z80_|execute_|fMRead~20 ( +// Location: LCCOMB_X23_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~30 ( // Equation(s): -// \z80_|execute_|fMRead~20_combout = (((\z80_|execute_|fMRead~15_combout ) # (!\z80_|execute_|ctl_sw_4d~2_combout )) # (!\z80_|execute_|fMRead~19_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~42_combout ) +// \z80_|execute_|ctl_bus_inc_oe~30_combout = (\z80_|execute_|ctl_bus_inc_oe~49_combout & (\z80_|execute_|ctl_bus_inc_oe~29_combout & \z80_|execute_|ctl_bus_inc_oe~28_combout )) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~49_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~29_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_bus_inc_oe~28_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~30 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_bus_inc_oe~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~3 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~3_combout = (\z80_|pla_decode_|Equal1~7_combout & (\z80_|pla_decode_|Equal2~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal21~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal1~7_combout ), + .datab(\z80_|pla_decode_|Equal2~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal21~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~3 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_mRead~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|fMRead~3 ( +// Equation(s): +// \z80_|execute_|fMRead~3_combout = ((!\z80_|pla_decode_|Equal33~0_combout ) # (!\z80_|ir_|opcode [7])) # (!\z80_|execute_|ctl_ir_we~5_combout ) + + .dataa(\z80_|execute_|ctl_ir_we~5_combout ), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|fMRead~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~3 .lut_mask = 16'h7F7F; +defparam \z80_|execute_|fMRead~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~37 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~37_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mRead~3_combout ) # ((\z80_|execute_|ctl_mRead~4_combout ) # (!\z80_|execute_|fMRead~3_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~3_combout ), + .datab(\z80_|execute_|ctl_mRead~4_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|fMRead~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~37 .lut_mask = 16'hE0F0; +defparam \z80_|execute_|ctl_bus_inc_oe~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~38 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~38_combout = (\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ) # (((\z80_|execute_|ctl_bus_inc_oe~37_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~30_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~48_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~48_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~30_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~37_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~38 .lut_mask = 16'hFFBF; +defparam \z80_|execute_|ctl_bus_inc_oe~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~39 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~39_combout = (\z80_|execute_|ctl_bus_inc_oe~46_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~47_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~34_combout ) # (\z80_|execute_|ctl_bus_inc_oe~38_combout ))) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~46_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~47_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~34_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~38_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_inc_oe~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_inc_oe~39 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_bus_inc_oe~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~43 ( +// Equation(s): +// \z80_|execute_|ctl_bus_inc_oe~43_combout = (((\z80_|execute_|ctl_bus_inc_oe~39_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~40_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~32_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~42_combout ) .dataa(\z80_|execute_|ctl_bus_inc_oe~42_combout ), - .datab(\z80_|execute_|fMRead~19_combout ), - .datac(\z80_|execute_|fMRead~15_combout ), - .datad(\z80_|execute_|ctl_sw_4d~2_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~32_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~40_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~39_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~20_combout ), + .combout(\z80_|execute_|ctl_bus_inc_oe~43_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~20 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|fMRead~20 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_bus_inc_oe~43 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_bus_inc_oe~43 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y15_N4 -cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~48 ( +// Location: LCCOMB_X28_Y16_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~3 ( // Equation(s): -// \z80_|execute_|pc_inc_hold~48_combout = (\z80_|execute_|ixy_d~5_combout & ((\z80_|pla_decode_|Equal35~0_combout ) # ((\z80_|pla_decode_|Equal24~0_combout & \z80_|pla_decode_|Equal9~0_combout )))) +// \z80_|execute_|ctl_alu_oe~3_combout = (\z80_|decode_state_|in_halt~q ) # (((!\z80_|pla_decode_|Equal33~0_combout & !\z80_|pla_decode_|Equal33~1_combout )) # (!\z80_|pla_decode_|Equal77~0_combout )) - .dataa(\z80_|pla_decode_|Equal24~0_combout ), - .datab(\z80_|pla_decode_|Equal35~0_combout ), - .datac(\z80_|execute_|ixy_d~5_combout ), - .datad(\z80_|pla_decode_|Equal9~0_combout ), + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|decode_state_|in_halt~q ), + .datac(\z80_|pla_decode_|Equal33~1_combout ), + .datad(\z80_|pla_decode_|Equal77~0_combout ), .cin(gnd), - .combout(\z80_|execute_|pc_inc_hold~48_combout ), + .combout(\z80_|execute_|ctl_alu_oe~3_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|pc_inc_hold~48 .lut_mask = 16'hE0C0; -defparam \z80_|execute_|pc_inc_hold~48 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_alu_oe~3 .lut_mask = 16'hCDFF; +defparam \z80_|execute_|ctl_alu_oe~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X41_Y16_N30 -cycloneive_lcell_comb \z80_|execute_|fMRead~22 ( +// Location: LCCOMB_X25_Y14_N8 +cycloneive_lcell_comb \z80_|execute_|fMWrite~1 ( // Equation(s): -// \z80_|execute_|fMRead~22_combout = (\z80_|execute_|ctl_mRead~17_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # ((\z80_|execute_|ctl_alu_oe~2_combout )))) # (!\z80_|execute_|ctl_mRead~17_combout & (\z80_|execute_|ctl_mRead~18_combout & -// ((\z80_|execute_|ctl_ir_we~4_combout ) # (\z80_|execute_|ctl_alu_oe~2_combout )))) +// \z80_|execute_|fMWrite~1_combout = (!\z80_|execute_|ctl_ir_we~15_combout & (!\z80_|execute_|ctl_mRead~4_combout & (!\z80_|execute_|ctl_ir_we~14_combout & !\z80_|execute_|ctl_ir_we~7_combout ))) - .dataa(\z80_|execute_|ctl_mRead~17_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_mRead~18_combout ), - .datad(\z80_|execute_|ctl_alu_oe~2_combout ), + .dataa(\z80_|execute_|ctl_ir_we~15_combout ), + .datab(\z80_|execute_|ctl_mRead~4_combout ), + .datac(\z80_|execute_|ctl_ir_we~14_combout ), + .datad(\z80_|execute_|ctl_ir_we~7_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~22_combout ), + .combout(\z80_|execute_|fMWrite~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~22 .lut_mask = 16'hFAC8; -defparam \z80_|execute_|fMRead~22 .sum_lutc_input = "datac"; +defparam \z80_|execute_|fMWrite~1 .lut_mask = 16'h0001; +defparam \z80_|execute_|fMWrite~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y15_N2 -cycloneive_lcell_comb \z80_|execute_|fMRead~21 ( +// Location: LCCOMB_X24_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~1 ( // Equation(s): -// \z80_|execute_|fMRead~21_combout = (\z80_|execute_|ctl_state_alu~5_combout & (((\z80_|execute_|ctl_mRead~36_combout ) # (!\z80_|execute_|fMRead~4_combout )) # (!\z80_|execute_|fMRead~2_combout ))) +// \z80_|execute_|ctl_flags_bus~1_combout = ((\z80_|ir_|opcode [2]) # (\z80_|ir_|opcode [1])) # (!\z80_|execute_|ctl_mWrite~4_combout ) - .dataa(\z80_|execute_|fMRead~2_combout ), - .datab(\z80_|execute_|ctl_mRead~36_combout ), - .datac(\z80_|execute_|ctl_state_alu~5_combout ), - .datad(\z80_|execute_|fMRead~4_combout ), + .dataa(gnd), + .datab(\z80_|execute_|ctl_mWrite~4_combout ), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [1]), .cin(gnd), - .combout(\z80_|execute_|fMRead~21_combout ), + .combout(\z80_|execute_|ctl_flags_bus~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~21 .lut_mask = 16'hD0F0; -defparam \z80_|execute_|fMRead~21 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_flags_bus~1 .lut_mask = 16'hFFF3; +defparam \z80_|execute_|ctl_flags_bus~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y15_N10 -cycloneive_lcell_comb \z80_|execute_|fMRead~23 ( +// Location: LCCOMB_X25_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|fMRead~5 ( // Equation(s): -// \z80_|execute_|fMRead~23_combout = ((\z80_|execute_|pc_inc_hold~48_combout ) # ((\z80_|execute_|fMRead~22_combout ) # (\z80_|execute_|fMRead~21_combout ))) # (!\z80_|execute_|ctl_bus_db_oe~0_combout ) +// \z80_|execute_|fMRead~5_combout = (!\z80_|pla_decode_|Equal13~2_combout & (\z80_|execute_|ctl_flags_bus~1_combout & !\z80_|execute_|ctl_state_alu~6_combout )) - .dataa(\z80_|execute_|ctl_bus_db_oe~0_combout ), - .datab(\z80_|execute_|pc_inc_hold~48_combout ), - .datac(\z80_|execute_|fMRead~22_combout ), - .datad(\z80_|execute_|fMRead~21_combout ), + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(\z80_|execute_|ctl_flags_bus~1_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(gnd), .cin(gnd), - .combout(\z80_|execute_|fMRead~23_combout ), + .combout(\z80_|execute_|fMRead~5_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~23 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|fMRead~23 .sum_lutc_input = "datac"; +defparam \z80_|execute_|fMRead~5 .lut_mask = 16'h0404; +defparam \z80_|execute_|fMRead~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y12_N8 +// Location: LCCOMB_X25_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~17 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~17_combout = (\z80_|execute_|fMWrite~1_combout & (!\z80_|execute_|ctl_ir_we~12_combout & \z80_|execute_|fMRead~5_combout )) + + .dataa(\z80_|execute_|fMWrite~1_combout ), + .datab(\z80_|execute_|ctl_ir_we~12_combout ), + .datac(gnd), + .datad(\z80_|execute_|fMRead~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~17 .lut_mask = 16'h2200; +defparam \z80_|execute_|ctl_mRead~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_iorw~10 ( +// Equation(s): +// \z80_|execute_|ctl_iorw~10_combout = (!\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [1] & \z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_iorw~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_iorw~10 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_iorw~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|setM1~47 ( +// Equation(s): +// \z80_|execute_|setM1~47_combout = (!\z80_|execute_|ctl_iorw~11_combout & (!\z80_|execute_|ctl_mRead~11_combout & (\z80_|execute_|ctl_mRead~17_combout & !\z80_|execute_|ctl_iorw~10_combout ))) + + .dataa(\z80_|execute_|ctl_iorw~11_combout ), + .datab(\z80_|execute_|ctl_mRead~11_combout ), + .datac(\z80_|execute_|ctl_mRead~17_combout ), + .datad(\z80_|execute_|ctl_iorw~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~47 .lut_mask = 16'h0010; +defparam \z80_|execute_|setM1~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~8 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~8_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal6~0_combout & (!\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal55~0_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~8 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_mWrite~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~13 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~13_combout = ((\z80_|ir_|opcode [2]) # (!\z80_|ir_|opcode [1])) # (!\z80_|execute_|ctl_mWrite~4_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_mWrite~4_combout ), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~13 .lut_mask = 16'hF3FF; +defparam \z80_|execute_|ctl_al_we~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|setM1~48 ( +// Equation(s): +// \z80_|execute_|setM1~48_combout = (\z80_|execute_|setM1~47_combout & (!\z80_|execute_|ctl_mWrite~8_combout & \z80_|execute_|ctl_al_we~13_combout )) + + .dataa(\z80_|execute_|setM1~47_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_mWrite~8_combout ), + .datad(\z80_|execute_|ctl_al_we~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~48 .lut_mask = 16'h0A00; +defparam \z80_|execute_|setM1~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~0 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~0_combout = (\z80_|execute_|ctl_state_alu~3_combout & (((!\z80_|decode_state_|use_ixiy~combout & !\z80_|execute_|ctl_alu_oe~3_combout )) # (!\z80_|execute_|setM1~48_combout ))) + + .dataa(\z80_|decode_state_|use_ixiy~combout ), + .datab(\z80_|execute_|ctl_state_alu~3_combout ), + .datac(\z80_|execute_|ctl_alu_oe~3_combout ), + .datad(\z80_|execute_|setM1~48_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~0 .lut_mask = 16'h04CC; +defparam \z80_|execute_|ctl_sw_4d~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|pla_decode_|Equal48~0_combout & !\z80_|sequencer_|DFFE_M1_ff~q )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|pla_decode_|Equal48~0_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 .lut_mask = 16'h00C0; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~9 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~9_combout = (\z80_|sequencer_|DFFE_T5_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T5_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~9 .lut_mask = 16'h00F0; +defparam \z80_|execute_|ctl_mRead~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~3_combout = (\z80_|pla_decode_|Equal10~0_combout & (!\z80_|execute_|ixy_d~7_combout & ((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|pla_decode_|Equal21~1_combout )))) # (!\z80_|pla_decode_|Equal10~0_combout & +// (((!\z80_|execute_|ctl_mRead~9_combout )) # (!\z80_|pla_decode_|Equal21~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|execute_|ctl_mRead~9_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~3 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_flags_sz_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout = (\z80_|pla_decode_|Equal11~0_combout & (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M3_ff~q )) + + .dataa(gnd), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 .lut_mask = 16'h0C00; +defparam \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~9 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~9_combout = (((!\z80_|execute_|ixy_d~6_combout & !\z80_|nM1_int~2_combout )) # (!\z80_|execute_|ctl_mWrite~4_combout )) # (!\z80_|pla_decode_|Equal8~0_combout ) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|pla_decode_|Equal8~0_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_mWrite~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~9 .lut_mask = 16'h37FF; +defparam \z80_|execute_|ctl_flags_alu~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~2 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~2_combout = ((!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal39~0_combout & !\z80_|pla_decode_|Equal40~1_combout ))) # (!\z80_|execute_|ixy_d~8_combout ) + + .dataa(\z80_|execute_|ixy_d~8_combout ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|pla_decode_|Equal39~0_combout ), + .datad(\z80_|pla_decode_|Equal40~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~2 .lut_mask = 16'h5557; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~10_combout = (\z80_|execute_|ctl_flags_sz_we~3_combout & (!\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout & (\z80_|execute_|ctl_flags_alu~9_combout & \z80_|execute_|ctl_alu_sel_op2_neg~2_combout ))) + + .dataa(\z80_|execute_|ctl_flags_sz_we~3_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), + .datac(\z80_|execute_|ctl_flags_alu~9_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~10 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_flags_alu~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~10_combout = (((!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4])) # (!\z80_|nM1_int~2_combout )) # (!\z80_|pla_decode_|Equal63~0_combout ) + + .dataa(\z80_|pla_decode_|Equal63~0_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~10 .lut_mask = 16'h777F; +defparam \z80_|execute_|ctl_flags_xy_we~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla11M1T1_11 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|pla_decode_|Equal10~0_combout )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|pla_decode_|Equal10~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel_pla11M1T1_11 .lut_mask = 16'h0300; +defparam \z80_|execute_|ctl_pf_sel_pla11M1T1_11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~11 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~11_combout = (\z80_|execute_|ctl_flags_xy_we~10_combout & (!\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout & ((!\z80_|sequencer_|DFFE_T5_ff~q ) # (!\z80_|execute_|ixy_d~15_combout )))) + + .dataa(\z80_|execute_|ctl_flags_xy_we~10_combout ), + .datab(\z80_|execute_|ixy_d~15_combout ), + .datac(\z80_|sequencer_|DFFE_T5_ff~q ), + .datad(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~11 .lut_mask = 16'h002A; +defparam \z80_|execute_|ctl_flags_xy_we~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~11 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~11_combout = (\z80_|execute_|ctl_flags_alu~10_combout & (\z80_|execute_|ctl_flags_xy_we~11_combout & ((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|execute_|ixy_d~15_combout )))) + + .dataa(\z80_|execute_|ctl_flags_alu~10_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~11_combout ), + .datac(\z80_|execute_|ixy_d~15_combout ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~11 .lut_mask = 16'h0888; +defparam \z80_|execute_|ctl_flags_alu~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~1 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~1_combout = (\z80_|execute_|ctl_reg_use_sp~0_combout & \z80_|execute_|nextM~11_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_use_sp~0_combout ), + .datad(\z80_|execute_|nextM~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~1 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_reg_use_sp~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~4 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~4_combout = (\z80_|sequencer_|DFFE_M4_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~4 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_state_alu~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~9_combout = (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|pla_decode_|Equal10~0_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|pla_decode_|Equal10~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~9 .lut_mask = 16'h777F; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~4 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~4_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & (((!\z80_|execute_|ctl_state_alu~4_combout & !\z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|execute_|ctl_mRead~4_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|ctl_mRead~4_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~4 .lut_mask = 16'h3700; +defparam \z80_|execute_|ctl_sw_2d~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~0 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~0_combout = (\z80_|execute_|ctl_mWrite~9_combout & (((!\z80_|execute_|ctl_ir_we~12_combout & !\z80_|execute_|ctl_ir_we~11_combout )))) # (!\z80_|execute_|ctl_mWrite~9_combout & (((!\z80_|execute_|ctl_ir_we~12_combout )) +// # (!\z80_|execute_|ctl_mWrite~5_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~5_combout ), + .datab(\z80_|execute_|ctl_mWrite~9_combout ), + .datac(\z80_|execute_|ctl_ir_we~12_combout ), + .datad(\z80_|execute_|ctl_ir_we~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~0 .lut_mask = 16'h131F; +defparam \z80_|execute_|ctl_flags_sz_we~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~4_combout = (\z80_|execute_|ctl_flags_sz_we~0_combout & (((!\z80_|execute_|ctl_ir_we~12_combout & !\z80_|execute_|ctl_ir_we~11_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .datab(\z80_|execute_|ctl_ir_we~12_combout ), + .datac(\z80_|execute_|ctl_ir_we~11_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~4 .lut_mask = 16'h02AA; +defparam \z80_|execute_|ctl_flags_sz_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y16_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~47 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~47_combout = (\z80_|pla_decode_|Equal8~0_combout & (\z80_|execute_|ctl_mWrite~4_combout & (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_M3_ff~q ))) + + .dataa(\z80_|pla_decode_|Equal8~0_combout ), + .datab(\z80_|execute_|ctl_mWrite~4_combout ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~47 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_op_low~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~3 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~3_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout & (((!\z80_|pla_decode_|Equal21~1_combout & !\z80_|execute_|ctl_mRead~34_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal21~1_combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~3 .lut_mask = 16'h001F; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~12 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~12_combout = (!\z80_|execute_|ctl_alu_op_low~47_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~3_combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~47_combout ), + .datab(\z80_|pla_decode_|Equal20~0_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~12 .lut_mask = 16'h1050; +defparam \z80_|execute_|ctl_flags_alu~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~23 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~23_combout = (((!\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [3])) # (!\z80_|pla_decode_|Equal63~0_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|pla_decode_|Equal63~0_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~23 .lut_mask = 16'h5F7F; +defparam \z80_|execute_|ctl_alu_op_low~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~19 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~19_combout = (\z80_|execute_|ctl_alu_op_low~23_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|pla_decode_|Equal20~0_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|execute_|ctl_alu_op_low~23_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|pla_decode_|Equal20~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~19 .lut_mask = 16'hC4CC; +defparam \z80_|execute_|ctl_flags_xy_we~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~13 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~13_combout = (\z80_|execute_|ctl_sw_2d~4_combout & (\z80_|execute_|ctl_flags_sz_we~4_combout & (\z80_|execute_|ctl_flags_alu~12_combout & \z80_|execute_|ctl_flags_xy_we~19_combout ))) + + .dataa(\z80_|execute_|ctl_sw_2d~4_combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~4_combout ), + .datac(\z80_|execute_|ctl_flags_alu~12_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~13 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_flags_alu~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_hi~4_combout = ((!\z80_|pla_decode_|Equal40~1_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal39~0_combout ))) # (!\z80_|execute_|ixy_d~9_combout ) + + .dataa(\z80_|pla_decode_|Equal40~1_combout ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|pla_decode_|Equal39~0_combout ), + .datad(\z80_|execute_|ixy_d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_hi~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_hi~4 .lut_mask = 16'h01FF; +defparam \z80_|execute_|ctl_reg_out_hi~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~1 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~1_combout = (\z80_|execute_|ctl_reg_out_hi~4_combout & \z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_out_hi~4_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~1 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_sw_4u~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~29 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~29_combout = ((!\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|execute_|ixy_d~15_combout ) + + .dataa(\z80_|execute_|ixy_d~15_combout ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~29 .lut_mask = 16'h555F; +defparam \z80_|execute_|ctl_alu_op_low~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~14 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~14_combout = (\z80_|execute_|ctl_reg_use_sp~1_combout & (\z80_|execute_|ctl_flags_alu~13_combout & (\z80_|execute_|ctl_sw_4u~1_combout & \z80_|execute_|ctl_alu_op_low~29_combout ))) + + .dataa(\z80_|execute_|ctl_reg_use_sp~1_combout ), + .datab(\z80_|execute_|ctl_flags_alu~13_combout ), + .datac(\z80_|execute_|ctl_sw_4u~1_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~29_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~14 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_flags_alu~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout = (\z80_|pla_decode_|Equal63~0_combout & (\z80_|nM1_int~2_combout & (!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4]))) + + .dataa(\z80_|pla_decode_|Equal63~0_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 .lut_mask = 16'h0008; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla82M1T1_16 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout = (!\z80_|ir_|opcode [0] & (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal3~1_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|pla_decode_|Equal3~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel_pla82M1T1_16 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_pf_sel_pla82M1T1_16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~13 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~13_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|execute_|ctl_mRead~4_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|execute_|ctl_mRead~4_combout ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~13 .lut_mask = 16'h777F; +defparam \z80_|execute_|ctl_flags_use_cf2~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~7_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|pla_decode_|Equal13~0_combout ) # (!\z80_|pla_decode_|Equal55~0_combout ))) # (!\z80_|sequencer_|DFFE_M3_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~7 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_flags_cf_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel[0]~2 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel[0]~2_combout = (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (\z80_|execute_|ctl_flags_use_cf2~13_combout & \z80_|execute_|ctl_flags_cf_we~7_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .datac(\z80_|execute_|ctl_flags_use_cf2~13_combout ), + .datad(\z80_|execute_|ctl_flags_cf_we~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel[0]~2 .lut_mask = 16'h3000; +defparam \z80_|execute_|ctl_pf_sel[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_we~5_combout = (\z80_|execute_|ctl_bus_inc_oe~27_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|execute_|ctl_ir_we~8_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|execute_|ctl_bus_inc_oe~27_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_we~5 .lut_mask = 16'hFD00; +defparam \z80_|execute_|ctl_flags_hf_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~10_combout = (\z80_|execute_|ctl_flags_hf_we~5_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|pla_decode_|Equal13~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|execute_|ctl_flags_hf_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~10 .lut_mask = 16'hFD00; +defparam \z80_|execute_|ctl_flags_pf_we~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N8 +cycloneive_lcell_comb \z80_|pla_decode_|Equal68~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal68~2_combout = (\z80_|ir_|opcode [6] & (\z80_|decode_state_|DFFE_instED~q & (!\z80_|ir_|opcode [7] & !\z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|decode_state_|DFFE_instED~q ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal68~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal68~2 .lut_mask = 16'h0008; +defparam \z80_|pla_decode_|Equal68~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~13 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~13_combout = ((!\z80_|execute_|ctl_alu_op_low~27_combout & ((!\z80_|pla_decode_|Equal68~2_combout ) # (!\z80_|pla_decode_|Equal1~4_combout )))) # (!\z80_|nM1_int~2_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~27_combout ), + .datab(\z80_|pla_decode_|Equal1~4_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal68~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~13 .lut_mask = 16'h1F5F; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~2_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout & (\z80_|execute_|ctl_pf_sel[0]~2_combout & (\z80_|execute_|ctl_flags_pf_we~10_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~13_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .datab(\z80_|execute_|ctl_pf_sel[0]~2_combout ), + .datac(\z80_|execute_|ctl_flags_pf_we~10_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~2 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_flags_pf_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~4_combout = (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|execute_|ctl_mWrite~17_combout & ((!\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|ctl_mRead~9_combout )))) # (!\z80_|execute_|ctl_state_alu~2_combout & +// (((!\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|ctl_mRead~9_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ctl_mWrite~17_combout ), + .datac(\z80_|execute_|ctl_mRead~9_combout ), + .datad(\z80_|execute_|ctl_mRead~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~4 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_alu_oe~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y18_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~8_combout = (!\z80_|execute_|ctl_reg_gp_sel~7_combout & \z80_|execute_|setM1~18_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_sel~7_combout ), + .datab(gnd), + .datac(\z80_|execute_|setM1~18_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~8 .lut_mask = 16'h5050; +defparam \z80_|execute_|ctl_flags_xy_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y19_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~20 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~20_combout = (((!\z80_|pla_decode_|Equal13~0_combout ) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|pla_decode_|Equal55~0_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~20 .lut_mask = 16'h7FFF; +defparam \z80_|execute_|ctl_flags_xy_we~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~9 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~9_combout = (\z80_|execute_|ctl_flags_pf_we~2_combout & (\z80_|execute_|ctl_alu_oe~4_combout & (\z80_|execute_|ctl_flags_xy_we~8_combout & \z80_|execute_|ctl_flags_xy_we~20_combout ))) + + .dataa(\z80_|execute_|ctl_flags_pf_we~2_combout ), + .datab(\z80_|execute_|ctl_alu_oe~4_combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~8_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~9 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_flags_xy_we~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~1 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~1_combout = ((!\z80_|execute_|ctl_state_alu~5_combout & (!\z80_|execute_|ctl_state_alu~6_combout & !\z80_|pla_decode_|Equal52~1_combout ))) # (!\z80_|nM1_int~2_combout ) + + .dataa(\z80_|execute_|ctl_state_alu~5_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|pla_decode_|Equal52~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~1 .lut_mask = 16'h3337; +defparam \z80_|execute_|ctl_flags_sz_we~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~1 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~1_combout = (!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal39~0_combout & !\z80_|pla_decode_|Equal40~1_combout )) + + .dataa(gnd), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|pla_decode_|Equal39~0_combout ), + .datad(\z80_|pla_decode_|Equal40~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~1 .lut_mask = 16'h0003; +defparam \z80_|execute_|ctl_bus_db_oe~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~10_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ixy_d~15_combout & ((\z80_|execute_|ctl_bus_db_oe~1_combout ) # (!\z80_|sequencer_|DFFE_M3_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|execute_|ixy_d~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~10 .lut_mask = 16'hF0FD; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~2_combout = (\z80_|execute_|ctl_flags_xy_we~9_combout & (\z80_|execute_|ctl_flags_sz_we~1_combout & \z80_|execute_|ctl_alu_op2_sel_bus~10_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_flags_xy_we~9_combout ), + .datac(\z80_|execute_|ctl_flags_sz_we~1_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~2 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_flags_sz_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y17_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~17 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~17_combout = (((!\z80_|execute_|ctl_ir_we~14_combout & !\z80_|execute_|ctl_ir_we~8_combout )) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|execute_|ctl_ir_we~14_combout ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|execute_|ctl_ir_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~17 .lut_mask = 16'h5F7F; +defparam \z80_|execute_|ctl_flags_alu~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~18 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~18_combout = (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|execute_|ctl_ir_we~7_combout ), + .datad(\z80_|execute_|ctl_ir_we~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~18 .lut_mask = 16'h777F; +defparam \z80_|execute_|ctl_flags_alu~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~6_combout = (\z80_|execute_|ctl_flags_alu~18_combout & (((!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~9_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~15_combout ), + .datab(\z80_|execute_|ctl_flags_alu~18_combout ), + .datac(\z80_|execute_|ctl_ir_we~9_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~6 .lut_mask = 16'h04CC; +defparam \z80_|execute_|ctl_flags_alu~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~19 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~19_combout = (((!\z80_|execute_|ctl_ir_we~14_combout & !\z80_|execute_|ctl_mWrite~17_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|sequencer_|DFFE_T4_ff~q ) + + .dataa(\z80_|execute_|ctl_ir_we~14_combout ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|execute_|ctl_mWrite~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~19 .lut_mask = 16'h3F7F; +defparam \z80_|execute_|ctl_flags_alu~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N24 +cycloneive_lcell_comb \z80_|pla_decode_|Equal1~5 ( +// Equation(s): +// \z80_|pla_decode_|Equal1~5_combout = (!\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal1~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal1~5 .lut_mask = 16'h0F00; +defparam \z80_|pla_decode_|Equal1~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y19_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~0 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~0_combout = (\z80_|pla_decode_|Equal1~5_combout & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|pla_decode_|Equal13~1_combout & !\z80_|sequencer_|DFFE_M1_ff~q ))) + + .dataa(\z80_|pla_decode_|Equal1~5_combout ), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|pla_decode_|Equal13~1_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~0 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_alu_core_R~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|pla_decode_|Equal11~0_combout )) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2 .lut_mask = 16'h1010; +defparam \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~1 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~1_combout = (\z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ) # ((\z80_|execute_|ctl_alu_core_R~0_combout & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|execute_|ctl_alu_core_R~0_combout ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~1 .lut_mask = 16'hFAF2; +defparam \z80_|execute_|ctl_alu_core_R~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~7_combout = ((\z80_|execute_|ctl_alu_core_R~1_combout ) # ((\z80_|pla_decode_|Equal56~0_combout & \z80_|execute_|ixy_d~7_combout ))) # (!\z80_|execute_|ctl_flags_alu~19_combout ) + + .dataa(\z80_|execute_|ctl_flags_alu~19_combout ), + .datab(\z80_|pla_decode_|Equal56~0_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ctl_alu_core_R~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~7 .lut_mask = 16'hFFD5; +defparam \z80_|execute_|ctl_flags_alu~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N12 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~5 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~5_combout = ((!\z80_|pla_decode_|Equal39~0_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal40~1_combout ))) # (!\z80_|execute_|ixy_d~6_combout ) + + .dataa(\z80_|pla_decode_|Equal39~0_combout ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|pla_decode_|Equal40~1_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~5 .lut_mask = 16'h0F1F; +defparam \z80_|reg_control_|reg_sys_we_lo~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N28 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~8 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~8_combout = (\z80_|reg_control_|reg_sys_we_lo~5_combout & (((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|pla_decode_|Equal56~0_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|pla_decode_|Equal56~0_combout ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|reg_control_|reg_sys_we_lo~5_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~8 .lut_mask = 16'h7F00; +defparam \z80_|reg_control_|reg_sys_we_lo~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~8_combout = (((\z80_|execute_|ctl_flags_alu~7_combout ) # (!\z80_|reg_control_|reg_sys_we_lo~8_combout )) # (!\z80_|execute_|ctl_flags_alu~6_combout )) # (!\z80_|execute_|ctl_flags_alu~17_combout ) + + .dataa(\z80_|execute_|ctl_flags_alu~17_combout ), + .datab(\z80_|execute_|ctl_flags_alu~6_combout ), + .datac(\z80_|execute_|ctl_flags_alu~7_combout ), + .datad(\z80_|reg_control_|reg_sys_we_lo~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~8 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|ctl_flags_alu~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~15 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~15_combout = (((\z80_|execute_|ctl_flags_alu~8_combout ) # (!\z80_|execute_|ctl_flags_sz_we~2_combout )) # (!\z80_|execute_|ctl_flags_alu~14_combout )) # (!\z80_|execute_|ctl_flags_alu~11_combout ) + + .dataa(\z80_|execute_|ctl_flags_alu~11_combout ), + .datab(\z80_|execute_|ctl_flags_alu~14_combout ), + .datac(\z80_|execute_|ctl_flags_sz_we~2_combout ), + .datad(\z80_|execute_|ctl_flags_alu~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~15 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_flags_alu~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~7 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~7_combout = (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|execute_|ctl_state_alu~6_combout & ((!\z80_|pla_decode_|Equal52~1_combout )))) # (!\z80_|execute_|ctl_state_alu~2_combout & +// (((!\z80_|execute_|ctl_state_alu~4_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ctl_state_alu~6_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|pla_decode_|Equal52~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~7 .lut_mask = 16'h1537; +defparam \z80_|execute_|ctl_state_alu~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~12 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~12_combout = (\z80_|execute_|ctl_state_alu~7_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|pla_decode_|Equal52~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal52~1_combout ), + .datab(\z80_|execute_|ctl_state_alu~7_combout ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~12 .lut_mask = 16'hCC4C; +defparam \z80_|execute_|ctl_state_alu~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~9 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~9_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # ((\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~9 .lut_mask = 16'h00EF; +defparam \z80_|execute_|ctl_state_alu~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~10 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~10_combout = (\z80_|execute_|ctl_state_alu~9_combout & ((\z80_|execute_|ctl_state_alu~5_combout ) # ((\z80_|pla_decode_|Equal52~1_combout & \z80_|execute_|ctl_state_alu~3_combout )))) # +// (!\z80_|execute_|ctl_state_alu~9_combout & (((\z80_|pla_decode_|Equal52~1_combout & \z80_|execute_|ctl_state_alu~3_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~9_combout ), + .datab(\z80_|execute_|ctl_state_alu~5_combout ), + .datac(\z80_|pla_decode_|Equal52~1_combout ), + .datad(\z80_|execute_|ctl_state_alu~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~10 .lut_mask = 16'hF888; +defparam \z80_|execute_|ctl_state_alu~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~8 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~8_combout = (\z80_|pla_decode_|Equal52~1_combout & (((\z80_|nM1_int~2_combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) # (!\z80_|pla_decode_|Equal52~1_combout & (\z80_|execute_|ctl_state_alu~6_combout & +// ((\z80_|nM1_int~2_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) + + .dataa(\z80_|pla_decode_|Equal52~1_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~8 .lut_mask = 16'hFA32; +defparam \z80_|execute_|ctl_state_alu~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal64~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal64~0_combout = (!\z80_|ir_|opcode [5] & (((\z80_|execute_|ctl_state_alu~10_combout ) # (\z80_|execute_|ctl_state_alu~8_combout )) # (!\z80_|execute_|ctl_state_alu~12_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|execute_|ctl_state_alu~12_combout ), + .datac(\z80_|execute_|ctl_state_alu~10_combout ), + .datad(\z80_|execute_|ctl_state_alu~8_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal64~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal64~0 .lut_mask = 16'h5551; +defparam \z80_|pla_decode_|Equal64~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel[0]~3 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel[0]~3_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # (\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|pla_decode_|Equal64~0_combout ) + + .dataa(\z80_|pla_decode_|Equal64~0_combout ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel[0]~3 .lut_mask = 16'hFDFD; +defparam \z80_|execute_|ctl_pf_sel[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N22 +cycloneive_lcell_comb \z80_|pla_decode_|Equal62~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal62~2_combout = (\z80_|ir_|opcode [5] & (((\z80_|execute_|ctl_state_alu~10_combout ) # (\z80_|execute_|ctl_state_alu~8_combout )) # (!\z80_|execute_|ctl_state_alu~12_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|execute_|ctl_state_alu~12_combout ), + .datac(\z80_|execute_|ctl_state_alu~10_combout ), + .datad(\z80_|execute_|ctl_state_alu~8_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal62~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal62~2 .lut_mask = 16'hAAA2; +defparam \z80_|pla_decode_|Equal62~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~4_combout = (((\z80_|ir_|opcode [3] & \z80_|ir_|opcode [4])) # (!\z80_|nM1_int~2_combout )) # (!\z80_|pla_decode_|Equal62~2_combout ) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|pla_decode_|Equal62~2_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~4 .lut_mask = 16'h8FFF; +defparam \z80_|execute_|ctl_flags_pf_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~46 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~46_combout = (\z80_|execute_|ctl_alu_shift_oe~41_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|pla_decode_|Equal48~0_combout )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|pla_decode_|Equal48~0_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~41_combout ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~46 .lut_mask = 16'hB0F0; +defparam \z80_|execute_|ctl_alu_shift_oe~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~6_combout = (\z80_|pla_decode_|Equal69~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|pla_decode_|Equal69~0_combout ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~6 .lut_mask = 16'h080A; +defparam \z80_|execute_|ctl_flags_pf_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~7_combout = (\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # ((\z80_|execute_|ctl_flags_pf_we~6_combout ) # ((\z80_|execute_|ctl_mRead~34_combout & \z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~34_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .datad(\z80_|execute_|ctl_flags_pf_we~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~7 .lut_mask = 16'hFFF8; +defparam \z80_|execute_|ctl_flags_pf_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~11 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~11_combout = ((\z80_|execute_|ctl_state_alu~10_combout ) # ((\z80_|execute_|ctl_reg_gp_sel~7_combout ) # (\z80_|execute_|ctl_state_alu~8_combout ))) # (!\z80_|execute_|ctl_state_alu~7_combout ) + + .dataa(\z80_|execute_|ctl_state_alu~7_combout ), + .datab(\z80_|execute_|ctl_state_alu~10_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel~7_combout ), + .datad(\z80_|execute_|ctl_state_alu~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~11 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_state_alu~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y17_N26 +cycloneive_lcell_comb \z80_|pla_decode_|Equal62~3 ( +// Equation(s): +// \z80_|pla_decode_|Equal62~3_combout = (\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [4] & (\z80_|execute_|ctl_state_alu~11_combout & \z80_|ir_|opcode [3]))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|execute_|ctl_state_alu~11_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal62~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal62~3 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal62~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~5_combout = (\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_mWrite~17_combout ) # ((\z80_|pla_decode_|Equal11~0_combout ) # (\z80_|pla_decode_|Equal62~3_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~17_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|pla_decode_|Equal62~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~5 .lut_mask = 16'hCCC8; +defparam \z80_|execute_|ctl_flags_pf_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~3_combout = (\z80_|execute_|ctl_flags_pf_we~2_combout & (((!\z80_|execute_|ctl_ir_we~12_combout & !\z80_|execute_|ctl_ir_we~11_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_ir_we~12_combout ), + .datac(\z80_|execute_|ctl_flags_pf_we~2_combout ), + .datad(\z80_|execute_|ctl_ir_we~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~3 .lut_mask = 16'h5070; +defparam \z80_|execute_|ctl_flags_pf_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~8_combout = ((\z80_|execute_|ctl_flags_pf_we~7_combout ) # ((\z80_|execute_|ctl_flags_pf_we~5_combout ) # (!\z80_|execute_|ctl_flags_pf_we~3_combout ))) # (!\z80_|execute_|ctl_alu_shift_oe~46_combout ) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~46_combout ), + .datab(\z80_|execute_|ctl_flags_pf_we~7_combout ), + .datac(\z80_|execute_|ctl_flags_pf_we~5_combout ), + .datad(\z80_|execute_|ctl_flags_pf_we~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~8 .lut_mask = 16'hFDFF; +defparam \z80_|execute_|ctl_flags_pf_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~9 ( +// Equation(s): +// \z80_|execute_|ctl_flags_pf_we~9_combout = (((\z80_|execute_|ctl_flags_pf_we~8_combout ) # (!\z80_|execute_|ctl_flags_pf_we~4_combout )) # (!\z80_|execute_|ctl_pf_sel[0]~3_combout )) # (!\z80_|execute_|ctl_flags_xy_we~13_combout ) + + .dataa(\z80_|execute_|ctl_flags_xy_we~13_combout ), + .datab(\z80_|execute_|ctl_pf_sel[0]~3_combout ), + .datac(\z80_|execute_|ctl_flags_pf_we~4_combout ), + .datad(\z80_|execute_|ctl_flags_pf_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_pf_we~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_pf_we~9 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_flags_pf_we~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y20_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~6_combout = (\z80_|execute_|ctl_ir_we~15_combout & (!\z80_|execute_|ctl_mWrite~5_combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|execute_|ctl_ir_we~9_combout )))) # (!\z80_|execute_|ctl_ir_we~15_combout & +// (((!\z80_|nM1_int~2_combout ) # (!\z80_|execute_|ctl_ir_we~9_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~15_combout ), + .datab(\z80_|execute_|ctl_mWrite~5_combout ), + .datac(\z80_|execute_|ctl_ir_we~9_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~6 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_alu_core_S~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y20_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~7_combout = (\z80_|execute_|ctl_alu_core_S~6_combout & (((!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~9_combout )) # (!\z80_|execute_|ctl_alu_oe~0_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~15_combout ), + .datab(\z80_|execute_|ctl_alu_oe~0_combout ), + .datac(\z80_|execute_|ctl_ir_we~9_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~7 .lut_mask = 16'h3700; +defparam \z80_|execute_|ctl_alu_core_S~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~1 ( +// Equation(s): +// \z80_|execute_|ctl_alu_res_oe~1_combout = (\z80_|execute_|ctl_alu_core_S~7_combout & (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|pla_decode_|Equal69~0_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|pla_decode_|Equal69~0_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_res_oe~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_res_oe~1 .lut_mask = 16'h5700; +defparam \z80_|execute_|ctl_alu_res_oe~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_alu_res_oe~0_combout = (\z80_|pla_decode_|Equal8~0_combout & ((\z80_|execute_|ctl_mRead~9_combout ) # ((\z80_|nM1_int~2_combout & \z80_|pla_decode_|Equal55~0_combout )))) # (!\z80_|pla_decode_|Equal8~0_combout & +// (((\z80_|nM1_int~2_combout & \z80_|pla_decode_|Equal55~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal8~0_combout ), + .datab(\z80_|execute_|ctl_mRead~9_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_res_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_res_oe~0 .lut_mask = 16'hF888; +defparam \z80_|execute_|ctl_alu_res_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y20_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~4_combout = (\z80_|execute_|ctl_ir_we~7_combout & (!\z80_|execute_|ctl_mWrite~5_combout & ((!\z80_|execute_|ctl_ir_we~10_combout ) # (!\z80_|nM1_int~2_combout )))) # (!\z80_|execute_|ctl_ir_we~7_combout & +// (((!\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~7_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|execute_|ctl_mWrite~5_combout ), + .datad(\z80_|execute_|ctl_ir_we~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~4 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_alu_core_S~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y20_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~5_combout = (\z80_|execute_|ctl_alu_core_S~4_combout & (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|execute_|ctl_alu_oe~0_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~7_combout ), + .datab(\z80_|execute_|ctl_ir_we~10_combout ), + .datac(\z80_|execute_|ctl_alu_oe~0_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~5 .lut_mask = 16'h1F00; +defparam \z80_|execute_|ctl_alu_core_S~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~2 ( +// Equation(s): +// \z80_|execute_|ctl_alu_res_oe~2_combout = (\z80_|execute_|ctl_alu_res_oe~1_combout & (\z80_|execute_|ctl_alu_core_S~5_combout & ((!\z80_|execute_|ctl_mWrite~4_combout ) # (!\z80_|execute_|ctl_alu_res_oe~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_res_oe~1_combout ), + .datab(\z80_|execute_|ctl_alu_res_oe~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_res_oe~2 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_alu_res_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y17_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout = (\z80_|pla_decode_|Equal2~0_combout & (\z80_|execute_|ctl_mWrite~4_combout & (!\z80_|ir_|opcode [0] & \z80_|execute_|ctl_state_alu~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal2~0_combout ), + .datab(\z80_|execute_|ctl_mWrite~4_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|execute_|ctl_state_alu~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N18 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~6 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~6_combout = (\z80_|reg_control_|reg_sys_we_lo~5_combout & (\z80_|execute_|ctl_flags_xy_we~20_combout & ((!\z80_|pla_decode_|Equal56~0_combout ) # (!\z80_|execute_|ctl_alu_op_low~22_combout )))) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~5_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datac(\z80_|pla_decode_|Equal56~0_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~20_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~6 .lut_mask = 16'h2A00; +defparam \z80_|reg_control_|reg_sys_we_lo~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~12 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~12_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|pla_decode_|Equal56~0_combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) # (!\z80_|execute_|ixy_d~7_combout & +// (((!\z80_|nM1_int~2_combout )) # (!\z80_|pla_decode_|Equal20~0_combout ))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|pla_decode_|Equal20~0_combout ), + .datac(\z80_|pla_decode_|Equal56~0_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~12 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_flags_xy_we~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~2_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout & (\z80_|reg_control_|reg_sys_we_lo~6_combout & (\z80_|execute_|ctl_flags_sz_we~1_combout & \z80_|execute_|ctl_flags_xy_we~12_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), + .datab(\z80_|reg_control_|reg_sys_we_lo~6_combout ), + .datac(\z80_|execute_|ctl_flags_sz_we~1_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~2 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_flags_cf_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~3 ( +// Equation(s): +// \z80_|execute_|ctl_alu_res_oe~3_combout = (\z80_|execute_|ctl_flags_alu~11_combout & (\z80_|execute_|ctl_alu_res_oe~2_combout & (\z80_|execute_|ctl_flags_cf_we~2_combout & \z80_|execute_|ctl_flags_pf_we~3_combout ))) + + .dataa(\z80_|execute_|ctl_flags_alu~11_combout ), + .datab(\z80_|execute_|ctl_alu_res_oe~2_combout ), + .datac(\z80_|execute_|ctl_flags_cf_we~2_combout ), + .datad(\z80_|execute_|ctl_flags_pf_we~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_res_oe~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_res_oe~3 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_res_oe~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_high ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_high~combout = ((\z80_|pla_decode_|Equal13~2_combout & (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_M3_ff~q ))) # (!\z80_|execute_|ctl_alu_res_oe~3_combout ) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|execute_|ctl_alu_res_oe~3_combout ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_high .lut_mask = 16'h8F0F; +defparam \z80_|execute_|ctl_alu_sel_op2_high .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_zero~4_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|ir_|opcode [0]))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|pla_decode_|Equal3~1_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_zero~4 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_alu_op1_sel_zero~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~12_combout = ((!\z80_|pla_decode_|Equal3~0_combout & ((\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal21~0_combout )))) # (!\z80_|execute_|ctl_state_alu~11_combout ) + + .dataa(\z80_|pla_decode_|Equal3~0_combout ), + .datab(\z80_|pla_decode_|Equal21~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|execute_|ctl_state_alu~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~12 .lut_mask = 16'h51FF; +defparam \z80_|execute_|ctl_alu_core_hf~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y16_N10 +cycloneive_lcell_comb \z80_|pla_decode_|Equal61~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal61~2_combout = (\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal6~0_combout & (!\z80_|ir_|opcode [1] & \z80_|ir_|opcode [0]))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal61~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal61~2 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal61~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~4_combout = (((!\z80_|execute_|ctl_eval_cond~0_combout & !\z80_|nM1_int~2_combout )) # (!\z80_|pla_decode_|Equal32~0_combout )) # (!\z80_|pla_decode_|Equal63~0_combout ) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|pla_decode_|Equal63~0_combout ), + .datad(\z80_|pla_decode_|Equal32~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~4 .lut_mask = 16'h1FFF; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~13 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~13_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~4_combout & (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|pla_decode_|Equal61~2_combout ))) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|pla_decode_|Equal61~2_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), + .datad(\z80_|sequencer_|DFFE_M4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~13 .lut_mask = 16'h3070; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y20_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~14 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~14_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~4_combout & (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (\z80_|execute_|ctl_alu_core_hf~12_combout & \z80_|execute_|ctl_alu_sel_op2_neg~13_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .datab(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~12_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~14 .lut_mask = 16'h1000; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~18 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~18_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~14_combout & (((!\z80_|execute_|ctl_mWrite~17_combout ) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|execute_|ctl_mWrite~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~18 .lut_mask = 16'h2AAA; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~10_combout = (\z80_|execute_|ctl_flags_bus~9_combout & (\z80_|execute_|ctl_alu_shift_oe~20_combout & \z80_|execute_|ctl_bus_db_oe~3_combout )) + + .dataa(\z80_|execute_|ctl_flags_bus~9_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~20_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~3_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~10 .lut_mask = 16'h8080; +defparam \z80_|execute_|ctl_flags_bus~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~2_combout = (\z80_|pla_decode_|Equal44~0_combout ) # ((\z80_|pla_decode_|Equal52~0_combout & \z80_|pla_decode_|Equal33~0_combout )) + + .dataa(gnd), + .datab(\z80_|pla_decode_|Equal44~0_combout ), + .datac(\z80_|pla_decode_|Equal52~0_combout ), + .datad(\z80_|pla_decode_|Equal33~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~2 .lut_mask = 16'hFCCC; +defparam \z80_|execute_|ctl_flags_bus~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y17_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~0 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~0_combout = (\z80_|ir_|opcode [5]) # ((!\z80_|pla_decode_|Equal13~1_combout ) # (!\z80_|pla_decode_|Equal13~0_combout )) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal13~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~0 .lut_mask = 16'hBBFF; +defparam \z80_|execute_|ctl_flags_bus~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_bus~3_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|execute_|ctl_flags_bus~2_combout ) # ((!\z80_|execute_|ctl_flags_bus~0_combout ) # (!\z80_|execute_|ctl_flags_bus~1_combout )))) + + .dataa(\z80_|execute_|ctl_flags_bus~2_combout ), + .datab(\z80_|execute_|ctl_flags_bus~1_combout ), + .datac(\z80_|execute_|ctl_flags_bus~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_bus~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_bus~3 .lut_mask = 16'hBF00; +defparam \z80_|execute_|ctl_flags_bus~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N10 cycloneive_lcell_comb \z80_|execute_|fMRead~26 ( // Equation(s): -// \z80_|execute_|fMRead~26_combout = (\z80_|execute_|ctl_mRead~15_combout ) # ((\z80_|pla_decode_|Equal44~0_combout & (\z80_|pla_decode_|Equal33~0_combout & !\z80_|decode_state_|use_ixiy~combout ))) +// \z80_|execute_|fMRead~26_combout = (\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_state_alu~2_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_state_alu~6_combout )))) # (!\z80_|execute_|ctl_ir_we~12_combout +// & (((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_state_alu~6_combout )))) - .dataa(\z80_|pla_decode_|Equal44~0_combout ), - .datab(\z80_|execute_|ctl_mRead~15_combout ), - .datac(\z80_|pla_decode_|Equal33~0_combout ), - .datad(\z80_|decode_state_|use_ixiy~combout ), + .dataa(\z80_|execute_|ctl_ir_we~12_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), .cin(gnd), .combout(\z80_|execute_|fMRead~26_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~26 .lut_mask = 16'hCCEC; +defparam \z80_|execute_|fMRead~26 .lut_mask = 16'h0777; defparam \z80_|execute_|fMRead~26 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y19_N20 -cycloneive_lcell_comb \z80_|execute_|fMRead~25 ( +// Location: LCCOMB_X29_Y19_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus ( // Equation(s): -// \z80_|execute_|fMRead~25_combout = ((\z80_|sequencer_|DFFE_M2_ff~q & (!\z80_|execute_|ixy_d~4_combout & \z80_|execute_|ctl_mRead~14_combout ))) # (!\z80_|execute_|fMRead~24_combout ) +// \z80_|execute_|ctl_flags_bus~combout = ((\z80_|execute_|ctl_flags_bus~3_combout ) # ((\z80_|execute_|ctl_flags_hf2_we~combout ) # (!\z80_|execute_|fMRead~26_combout ))) # (!\z80_|execute_|ctl_flags_bus~10_combout ) - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|execute_|ixy_d~4_combout ), - .datac(\z80_|execute_|fMRead~24_combout ), - .datad(\z80_|execute_|ctl_mRead~14_combout ), + .dataa(\z80_|execute_|ctl_flags_bus~10_combout ), + .datab(\z80_|execute_|ctl_flags_bus~3_combout ), + .datac(\z80_|execute_|ctl_flags_hf2_we~combout ), + .datad(\z80_|execute_|fMRead~26_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~25_combout ), + .combout(\z80_|execute_|ctl_flags_bus~combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~25 .lut_mask = 16'h2F0F; -defparam \z80_|execute_|fMRead~25 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_flags_bus .lut_mask = 16'hFDFF; +defparam \z80_|execute_|ctl_flags_bus .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|fMRead~27 ( +// Location: LCCOMB_X26_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_lo~9 ( // Equation(s): -// \z80_|execute_|fMRead~27_combout = ((\z80_|execute_|fMRead~25_combout ) # ((\z80_|execute_|fMRead~26_combout & \z80_|execute_|ctl_ir_we~4_combout ))) # (!\z80_|execute_|fMRead~3_combout ) +// \z80_|execute_|ctl_reg_in_lo~9_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q ))) # (!\z80_|pla_decode_|Equal47~0_combout ) - .dataa(\z80_|execute_|fMRead~26_combout ), - .datab(\z80_|execute_|fMRead~3_combout ), - .datac(\z80_|execute_|ctl_ir_we~4_combout ), - .datad(\z80_|execute_|fMRead~25_combout ), + .dataa(\z80_|pla_decode_|Equal47~0_combout ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|M5~q ), .cin(gnd), - .combout(\z80_|execute_|fMRead~27_combout ), + .combout(\z80_|execute_|ctl_reg_in_lo~9_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~27 .lut_mask = 16'hFFB3; -defparam \z80_|execute_|fMRead~27 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_reg_in_lo~9 .lut_mask = 16'hF5F7; +defparam \z80_|execute_|ctl_reg_in_lo~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y17_N18 -cycloneive_lcell_comb \z80_|execute_|fMRead~33 ( +// Location: LCCOMB_X30_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_oe~0 ( // Equation(s): -// \z80_|execute_|fMRead~33_combout = (\z80_|execute_|fMRead~32_combout ) # ((\z80_|execute_|fMRead~20_combout ) # ((\z80_|execute_|fMRead~23_combout ) # (\z80_|execute_|fMRead~27_combout ))) +// \z80_|execute_|ctl_alu_op1_oe~0_combout = ((\z80_|execute_|ctl_66_oe~2_combout ) # ((\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_alu_shift_oe~14_combout ))) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ) - .dataa(\z80_|execute_|fMRead~32_combout ), - .datab(\z80_|execute_|fMRead~20_combout ), - .datac(\z80_|execute_|fMRead~23_combout ), - .datad(\z80_|execute_|fMRead~27_combout ), + .dataa(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .datab(\z80_|execute_|ctl_66_oe~2_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~33_combout ), + .combout(\z80_|execute_|ctl_alu_op1_oe~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~33 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|fMRead~33 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_alu_op1_oe~0 .lut_mask = 16'hFDDD; +defparam \z80_|execute_|ctl_alu_op1_oe~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y17_N8 -cycloneive_lcell_comb \z80_|execute_|fMRead~35 ( +// Location: LCCOMB_X30_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_oe~1 ( // Equation(s): -// \z80_|execute_|fMRead~35_combout = (\z80_|execute_|fMRead~33_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~20_combout ) # ((\z80_|execute_|fMRead~34_combout & !\z80_|execute_|fMRead~0_combout ))) +// \z80_|execute_|ctl_alu_op1_oe~1_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ) # ((\z80_|execute_|ctl_alu_op1_oe~0_combout ) # ((\z80_|nM1_int~2_combout & \z80_|execute_|ctl_alu_oe~1_combout ))) - .dataa(\z80_|execute_|fMRead~34_combout ), - .datab(\z80_|execute_|fMRead~33_combout ), - .datac(\z80_|execute_|fMRead~0_combout ), - .datad(\z80_|execute_|ctl_reg_sel_pc~20_combout ), + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_alu_oe~1_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), + .datad(\z80_|execute_|ctl_alu_op1_oe~0_combout ), .cin(gnd), - .combout(\z80_|execute_|fMRead~35_combout ), + .combout(\z80_|execute_|ctl_alu_op1_oe~1_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fMRead~35 .lut_mask = 16'hFFCE; -defparam \z80_|execute_|fMRead~35 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_alu_op1_oe~1 .lut_mask = 16'hFFF8; +defparam \z80_|execute_|ctl_alu_op1_oe~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y13_N30 -cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_re ( +// Location: LCCOMB_X23_Y19_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~6 ( // Equation(s): -// \z80_|pin_control_|bus_db_pin_re~combout = (\z80_|pin_control_|bus_db_pin_re~2_combout ) # ((\z80_|execute_|fMRead~35_combout & \z80_|sequencer_|DFFE_T2_ff~q )) +// \z80_|execute_|ctl_alu_bs_oe~6_combout = ((!\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~15_combout ))) # (!\z80_|execute_|ctl_ir_we~4_combout ) + + .dataa(\z80_|execute_|ctl_ir_we~12_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ctl_ir_we~9_combout ), + .datad(\z80_|execute_|ctl_ir_we~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~6 .lut_mask = 16'h3337; +defparam \z80_|execute_|ctl_alu_bs_oe~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~12_combout = (\z80_|execute_|ctl_ir_we~11_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # ((!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M4_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|execute_|ctl_ir_we~11_combout ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~12 .lut_mask = 16'hCC40; +defparam \z80_|execute_|ctl_alu_bs_oe~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~8_combout = ((\z80_|execute_|ctl_alu_bs_oe~12_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~7_combout )) # (!\z80_|execute_|ctl_alu_bs_oe~6_combout ) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~6_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_bs_oe~12_combout ), + .datad(\z80_|execute_|ctl_alu_bs_oe~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~8 .lut_mask = 16'hF5FF; +defparam \z80_|execute_|ctl_alu_bs_oe~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~9_combout = (\z80_|execute_|ctl_ir_we~7_combout & (((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # (\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|execute_|ctl_ir_we~7_combout & (\z80_|execute_|ctl_ir_we~10_combout +// & ((\z80_|execute_|ctl_ir_we~4_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~10_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_ir_we~7_combout ), + .datad(\z80_|execute_|ctl_ir_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~9 .lut_mask = 16'hFAC0; +defparam \z80_|execute_|ctl_alu_bs_oe~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~combout = (\z80_|execute_|ctl_alu_bs_oe~8_combout ) # ((\z80_|execute_|ctl_alu_bs_oe~9_combout ) # ((\z80_|execute_|ctl_ir_we~4_combout & \z80_|pla_decode_|Equal41~2_combout ))) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~8_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(\z80_|execute_|ctl_alu_bs_oe~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe .lut_mask = 16'hFFEA; +defparam \z80_|execute_|ctl_alu_bs_oe .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_oe~0_combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # ((!\z80_|ir_|opcode [3] & \z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_oe~0 .lut_mask = 16'hB0A0; +defparam \z80_|execute_|ctl_alu_op2_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N12 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~0 ( +// Equation(s): +// \z80_|alu_|db_high[3]~0_combout = (\z80_|execute_|ctl_alu_op1_oe~1_combout ) # ((\z80_|execute_|ctl_alu_bs_oe~combout ) # ((\z80_|execute_|ctl_alu_op2_oe~0_combout ) # (!\z80_|execute_|ctl_alu_res_oe~3_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datab(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datac(\z80_|execute_|ctl_alu_res_oe~3_combout ), + .datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~0 .lut_mask = 16'hFFEF; +defparam \z80_|alu_|db_high[3]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y19_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla83M1T3_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla83M1T3_2~combout = (\z80_|pla_decode_|Equal1~5_combout & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|pla_decode_|Equal13~1_combout & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal1~5_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|pla_decode_|Equal13~1_combout ), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla83M1T3_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla83M1T3_2 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla83M1T3_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~15 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~15_combout = (!\z80_|pla_decode_|Equal33~1_combout & (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal3~1_combout & \z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~1_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|pla_decode_|Equal3~1_combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~15 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_alu_shift_oe~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~38 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~38_combout = (!\z80_|execute_|ctl_alu_shift_oe~15_combout & (((!\z80_|execute_|ctl_state_alu~4_combout & !\z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|execute_|ctl_mRead~4_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|ctl_mRead~4_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~38 .lut_mask = 16'h0037; +defparam \z80_|execute_|ctl_alu_shift_oe~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y19_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~28 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~28_combout = (\z80_|pla_decode_|Equal1~5_combout & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|pla_decode_|Equal13~1_combout & \z80_|execute_|ctl_eval_cond~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal1~5_combout ), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|pla_decode_|Equal13~1_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~28 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_op_low~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y19_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~6_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla83M1T3_2~combout & (!\z80_|execute_|ctl_alu_op1_sel_bus~16_combout & (\z80_|execute_|ctl_alu_shift_oe~38_combout & !\z80_|execute_|ctl_alu_op_low~28_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla83M1T3_2~combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~38_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~28_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~6 .lut_mask = 16'h0010; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~37 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~37_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_alu_oe~1_combout ) # ((!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & \z80_|execute_|ctl_ir_we~11_combout )))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_ir_we~11_combout ), + .datad(\z80_|execute_|ctl_alu_oe~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~37 .lut_mask = 16'hAA20; +defparam \z80_|execute_|ctl_alu_shift_oe~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~39 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~39_combout = ((\z80_|execute_|ctl_alu_shift_oe~37_combout ) # ((\z80_|execute_|ctl_state_alu~6_combout & \z80_|execute_|ctl_alu_shift_oe~14_combout ))) # (!\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ) + + .dataa(\z80_|execute_|ctl_state_alu~6_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~37_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~39 .lut_mask = 16'hFBF3; +defparam \z80_|execute_|ctl_alu_shift_oe~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_daa ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_sel_daa~combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal63~0_combout & (!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4]))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_sel_daa .lut_mask = 16'h0008; +defparam \z80_|execute_|ctl_flags_cf2_sel_daa .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y17_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~7_combout = (\z80_|execute_|ctl_ir_we~8_combout & (!\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ctl_mWrite~5_combout ) # (!\z80_|execute_|ctl_ir_we~14_combout )))) # (!\z80_|execute_|ctl_ir_we~8_combout +// & (((!\z80_|execute_|ctl_mWrite~5_combout )) # (!\z80_|execute_|ctl_ir_we~14_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|execute_|ctl_ir_we~14_combout ), + .datac(\z80_|execute_|ctl_mWrite~5_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~7 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y17_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~8_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~7_combout & (\z80_|execute_|ctl_flags_alu~17_combout & ((!\z80_|pla_decode_|Equal20~0_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|pla_decode_|Equal20~0_combout ), + .datad(\z80_|execute_|ctl_flags_alu~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~8 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~30 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~30_combout = ((!\z80_|execute_|ixy_d~7_combout & ((\z80_|ir_|opcode [3]) # (!\z80_|execute_|ixy_d~6_combout )))) # (!\z80_|pla_decode_|Equal13~2_combout ) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~30 .lut_mask = 16'h7757; +defparam \z80_|execute_|ctl_alu_op_low~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y18_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~31 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~31_combout = (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (\z80_|execute_|ctl_alu_op1_sel_bus~8_combout & \z80_|execute_|ctl_alu_op_low~30_combout )) .dataa(gnd), - .datab(\z80_|execute_|fMRead~35_combout ), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|pin_control_|bus_db_pin_re~2_combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~30_combout ), .cin(gnd), - .combout(\z80_|pin_control_|bus_db_pin_re~combout ), + .combout(\z80_|execute_|ctl_alu_op_low~31_combout ), .cout()); // synopsys translate_off -defparam \z80_|pin_control_|bus_db_pin_re .lut_mask = 16'hFFC0; -defparam \z80_|pin_control_|bus_db_pin_re .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_alu_op_low~31 .lut_mask = 16'h3000; +defparam \z80_|execute_|ctl_alu_op_low~31 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X33_Y15_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a1 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[1]~34_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), +// Location: LCCOMB_X27_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~25 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~25_combout = (\z80_|pla_decode_|Equal13~2_combout & \z80_|ir_|opcode [3]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~25 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_mRead~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~40 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~40_combout = ((\z80_|execute_|ixy_d~9_combout & ((\z80_|execute_|ctl_mRead~25_combout ) # (\z80_|execute_|ctl_mRead~24_combout )))) # (!\z80_|execute_|ctl_flags_xy_we~21_combout ) + + .dataa(\z80_|execute_|ctl_mRead~25_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~21_combout ), + .datac(\z80_|execute_|ixy_d~9_combout ), + .datad(\z80_|execute_|ctl_mRead~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~40 .lut_mask = 16'hF3B3; +defparam \z80_|execute_|ctl_alu_shift_oe~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~42 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~42_combout = ((\z80_|execute_|ctl_alu_shift_oe~39_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~40_combout ) # (!\z80_|execute_|ctl_alu_op_low~31_combout ))) # (!\z80_|execute_|ctl_alu_shift_oe~46_combout ) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~46_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~39_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~31_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~40_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~42 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|ctl_alu_shift_oe~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout = (!\z80_|pla_decode_|Equal33~0_combout & (\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|pla_decode_|Equal44~0_combout & !\z80_|sequencer_|DFFE_M1_ff~q ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|pla_decode_|Equal44~0_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 .lut_mask = 16'h0040; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y18_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~4_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & (\z80_|execute_|ctl_state_alu~7_combout & (!\z80_|execute_|ctl_reg_gp_sel~7_combout & !\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ))) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), + .datab(\z80_|execute_|ctl_state_alu~7_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel~7_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~4 .lut_mask = 16'h0008; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~47 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~47_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|execute_|ctl_ir_we~7_combout & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_M1_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|execute_|ctl_ir_we~7_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~47 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_shift_oe~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~34 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~34_combout = (\z80_|execute_|ctl_ir_we~10_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ctl_alu_shift_oe~47_combout )))) # +// (!\z80_|execute_|ctl_ir_we~10_combout & (((\z80_|execute_|ctl_alu_shift_oe~47_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~10_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~47_combout ), + .datad(\z80_|execute_|ctl_ir_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~34 .lut_mask = 16'h50F8; +defparam \z80_|execute_|ctl_alu_shift_oe~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~35 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~35_combout = (!\z80_|execute_|ctl_alu_bs_oe~8_combout & ((\z80_|execute_|ctl_alu_shift_oe~34_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & \z80_|execute_|ctl_ir_we~10_combout )))) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~8_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~34_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_ir_we~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~35 .lut_mask = 16'h5444; +defparam \z80_|execute_|ctl_alu_shift_oe~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~36 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~36_combout = (((\z80_|execute_|ctl_alu_shift_oe~35_combout ) # (!\z80_|execute_|ctl_flags_bus~9_combout )) # (!\z80_|execute_|ctl_reg_use_sp~1_combout )) # (!\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ), + .datab(\z80_|execute_|ctl_reg_use_sp~1_combout ), + .datac(\z80_|execute_|ctl_flags_bus~9_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~35_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~36 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_alu_shift_oe~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~28 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~28_combout = (\z80_|execute_|ctl_state_alu~4_combout & ((\z80_|execute_|ctl_ir_we~7_combout ) # ((\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ctl_bus_db_oe~1_combout )))) # (!\z80_|execute_|ctl_state_alu~4_combout +// & (\z80_|execute_|ixy_d~7_combout & ((!\z80_|execute_|ctl_bus_db_oe~1_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|execute_|ctl_ir_we~7_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~28 .lut_mask = 16'hA0EC; +defparam \z80_|execute_|ctl_alu_shift_oe~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~44 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~44_combout = (!\z80_|execute_|ctl_alu_op_low~26_combout & (((!\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~26_combout ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|execute_|ctl_mRead~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~44 .lut_mask = 16'h1555; +defparam \z80_|execute_|ctl_alu_shift_oe~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~29 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~29_combout = (\z80_|execute_|ctl_alu_shift_oe~28_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~44_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~20_combout )) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~28_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_shift_oe~20_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~44_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~29 .lut_mask = 16'hAFFF; +defparam \z80_|execute_|ctl_alu_shift_oe~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~16 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~16_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|execute_|ixy_d~15_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|execute_|ixy_d~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~16 .lut_mask = 16'h0F00; +defparam \z80_|execute_|ctl_alu_shift_oe~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~27 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~27_combout = (!\z80_|execute_|ctl_alu_bs_oe~combout & ((\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ) # (\z80_|execute_|ctl_alu_shift_oe~16_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), + .datab(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~27 .lut_mask = 16'h3332; +defparam \z80_|execute_|ctl_alu_shift_oe~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_bs_oe~10_combout = ((\z80_|execute_|ctl_alu_bs_oe~9_combout ) # ((\z80_|execute_|ctl_alu_bs_oe~12_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~7_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~6_combout ) + + .dataa(\z80_|execute_|ctl_alu_bs_oe~6_combout ), + .datab(\z80_|execute_|ctl_alu_bs_oe~9_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~12_combout ), + .datad(\z80_|execute_|ctl_alu_bs_oe~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_bs_oe~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_bs_oe~10 .lut_mask = 16'hFDFF; +defparam \z80_|execute_|ctl_alu_bs_oe~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~31 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~31_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~3_combout & (\z80_|execute_|ctl_sw_4u~1_combout & ((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout )))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datab(\z80_|pla_decode_|Equal47~0_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), + .datad(\z80_|execute_|ctl_sw_4u~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~31 .lut_mask = 16'h7000; +defparam \z80_|execute_|ctl_alu_shift_oe~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~30 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~30_combout = (\z80_|execute_|ctl_mWrite~5_combout & (!\z80_|execute_|ctl_mWrite~17_combout & ((!\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|ctl_state_alu~2_combout )))) # +// (!\z80_|execute_|ctl_mWrite~5_combout & (((!\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|ctl_state_alu~2_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~5_combout ), + .datab(\z80_|execute_|ctl_mWrite~17_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_mRead~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~30 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_alu_shift_oe~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~32 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~32_combout = (\z80_|execute_|ctl_alu_shift_oe~31_combout & (\z80_|execute_|ctl_alu_shift_oe~30_combout & ((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_mRead~9_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~9_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~31_combout ), + .datac(\z80_|pla_decode_|Equal47~0_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~30_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~32 .lut_mask = 16'h4C00; +defparam \z80_|execute_|ctl_alu_shift_oe~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~33 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~33_combout = (\z80_|execute_|ctl_alu_shift_oe~27_combout ) # ((!\z80_|execute_|ctl_alu_bs_oe~10_combout & ((\z80_|execute_|ctl_alu_shift_oe~29_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~32_combout )))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~29_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~27_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~10_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~32_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~33 .lut_mask = 16'hCECF; +defparam \z80_|execute_|ctl_alu_shift_oe~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y20_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~21 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~21_combout = (\z80_|execute_|ctl_ir_we~15_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # ((!\z80_|execute_|ctl_ir_we~4_combout & \z80_|execute_|ctl_state_alu~4_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~15_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|ctl_state_alu~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~21 .lut_mask = 16'hAA20; +defparam \z80_|execute_|ctl_alu_shift_oe~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y20_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~45 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~45_combout = (\z80_|execute_|ctl_alu_shift_oe~21_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|execute_|ctl_alu_shift_oe~21_combout ), + .datad(\z80_|execute_|ctl_ir_we~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~45 .lut_mask = 16'hD0F0; +defparam \z80_|execute_|ctl_alu_shift_oe~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y20_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~22 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~22_combout = (\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_alu_shift_oe~45_combout ) # (\z80_|execute_|ctl_state_alu~4_combout )))) # +// (!\z80_|execute_|ctl_ir_we~9_combout & (\z80_|execute_|ctl_alu_shift_oe~45_combout )) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~45_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ctl_ir_we~9_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~22 .lut_mask = 16'h3A2A; +defparam \z80_|execute_|ctl_alu_shift_oe~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y20_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~23 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~23_combout = (\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|execute_|ctl_alu_shift_oe~22_combout ) # (\z80_|execute_|ctl_eval_cond~0_combout )))) # +// (!\z80_|execute_|ctl_ir_we~9_combout & (\z80_|execute_|ctl_alu_shift_oe~22_combout )) + + .dataa(\z80_|execute_|ctl_ir_we~9_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~22_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~23 .lut_mask = 16'h44EC; +defparam \z80_|execute_|ctl_alu_shift_oe~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y20_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~24 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~24_combout = (\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_mWrite~9_combout ) # (\z80_|execute_|ctl_alu_shift_oe~23_combout )))) # +// (!\z80_|execute_|ctl_ir_we~12_combout & (((\z80_|execute_|ctl_alu_shift_oe~23_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~12_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ctl_mWrite~9_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~23_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~24 .lut_mask = 16'h7720; +defparam \z80_|execute_|ctl_alu_shift_oe~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y20_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~25 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~25_combout = (\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # (\z80_|execute_|ctl_alu_shift_oe~24_combout )))) # +// (!\z80_|execute_|ctl_ir_we~12_combout & (((\z80_|execute_|ctl_alu_shift_oe~24_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|execute_|ctl_mWrite~5_combout ), + .datac(\z80_|execute_|ctl_ir_we~12_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~25 .lut_mask = 16'h5F40; +defparam \z80_|execute_|ctl_alu_shift_oe~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~26 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~26_combout = (!\z80_|execute_|ctl_alu_bs_oe~12_combout & ((\z80_|execute_|ctl_alu_shift_oe~25_combout ) # ((\z80_|execute_|ctl_mWrite~9_combout & \z80_|execute_|ctl_ir_we~11_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~9_combout ), + .datab(\z80_|execute_|ctl_ir_we~11_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~25_combout ), + .datad(\z80_|execute_|ctl_alu_bs_oe~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~26 .lut_mask = 16'h00F8; +defparam \z80_|execute_|ctl_alu_shift_oe~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~43 ( +// Equation(s): +// \z80_|execute_|ctl_alu_shift_oe~43_combout = (\z80_|execute_|ctl_alu_shift_oe~42_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~36_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~33_combout ) # (\z80_|execute_|ctl_alu_shift_oe~26_combout ))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~42_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~36_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~33_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~26_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_shift_oe~43 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_alu_shift_oe~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_low ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_low~combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ixy_d~9_combout ) # ((\z80_|execute_|ixy_d~7_combout & !\z80_|ir_|opcode [3])))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ixy_d~9_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_low .lut_mask = 16'hC0E0; +defparam \z80_|execute_|ctl_alu_op1_sel_low .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_zero~5_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal63~0_combout & !\z80_|ir_|opcode [4]))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|pla_decode_|Equal63~0_combout ), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_zero~5 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_alu_op1_sel_zero~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y17_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_zero~combout = (\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # ((\z80_|execute_|ctl_66_oe~2_combout ) # ((\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # (\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .datab(\z80_|execute_|ctl_66_oe~2_combout ), + .datac(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_zero .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_alu_op1_sel_zero .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y17_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~13 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~13_combout = (!\z80_|execute_|ctl_alu_op_low~26_combout & (((!\z80_|pla_decode_|Equal41~2_combout & !\z80_|execute_|ctl_ir_we~11_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~26_combout ), + .datab(\z80_|pla_decode_|Equal41~2_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|execute_|ctl_ir_we~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~13 .lut_mask = 16'h0515; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y19_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~17 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~17_combout = (\z80_|execute_|ctl_flags_xy_we~14_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|pla_decode_|Equal48~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal48~0_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~14_combout ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~17 .lut_mask = 16'hCC4C; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y19_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~14 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~14_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~13_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~17_combout & (\z80_|execute_|ctl_bus_db_oe~0_combout & \z80_|execute_|ctl_alu_op1_sel_bus~8_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~13_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~17_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~0_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~14 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y20_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~3 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~3_combout = (\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ctl_ir_we~15_combout ) # (!\z80_|execute_|ctl_state_alu~2_combout )))) # (!\z80_|execute_|ctl_ir_we~9_combout +// & (((!\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_state_alu~2_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~9_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_ir_we~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~3 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_alu_core_R~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y20_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~4 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~4_combout = (\z80_|execute_|ctl_alu_core_R~3_combout & (((!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~9_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~15_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_ir_we~9_combout ), + .datad(\z80_|execute_|ctl_alu_core_R~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~4 .lut_mask = 16'h3700; +defparam \z80_|execute_|ctl_alu_core_R~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|execute_|ctl_ir_we~11_combout & \z80_|sequencer_|DFFE_T4_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|execute_|ctl_ir_we~11_combout ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 .lut_mask = 16'h4400; +defparam \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y20_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~9_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|execute_|ctl_ir_we~10_combout & ((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|ctl_ir_we~7_combout )))) # +// (!\z80_|execute_|ctl_eval_cond~0_combout & (((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|ctl_ir_we~7_combout )))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|ctl_ir_we~10_combout ), + .datac(\z80_|execute_|ctl_ir_we~7_combout ), + .datad(\z80_|execute_|ctl_state_alu~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~9 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~10_combout = (!\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout & (\z80_|execute_|ctl_flags_sz_we~0_combout & (\z80_|execute_|ctl_flags_alu~18_combout & \z80_|execute_|ctl_alu_op1_sel_bus~9_combout +// ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .datac(\z80_|execute_|ctl_flags_alu~18_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~10 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~11_combout = (((\z80_|execute_|ctl_alu_oe~1_combout & \z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~10_combout )) # (!\z80_|execute_|ctl_alu_core_R~4_combout ) + + .dataa(\z80_|execute_|ctl_alu_oe~1_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_alu_core_R~4_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~11 .lut_mask = 16'h8FFF; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~12_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ) # ((\z80_|execute_|ixy_d~15_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T4_ff~q )))) + + .dataa(\z80_|execute_|ixy_d~15_combout ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~12 .lut_mask = 16'hFFA8; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~15 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op1_sel_bus~15_combout = ((\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~32_combout ) # (!\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ))) # (!\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~32_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op1_sel_bus~15 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_alu_op1_sel_bus~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N6 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & ((\z80_|alu_|db_low[3]~17_combout ) # ((!\z80_|alu_|db_high[3]~0_combout & !\z80_|execute_|ctl_alu_shift_oe~43_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datab(\z80_|alu_|db_high[3]~0_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datad(\z80_|alu_|db_low[3]~17_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9 .lut_mask = 16'hAA02; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N4 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~6 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~6_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & ((\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ) # ((\z80_|alu_|db_high[3]~7_combout & \z80_|execute_|ctl_alu_op1_sel_low~combout )))) + + .dataa(\z80_|alu_|db_high[3]~7_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .datad(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~6 .lut_mask = 16'h0F08; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N30 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|ena ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|ena~combout = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~combout ) # (\z80_|execute_|ctl_alu_op1_sel_low~combout )) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|ena .lut_mask = 16'hFFFA; +defparam \z80_|alu_|b2v_op1_latch_mux_low|ena .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y17_N5 +dffeas \z80_|alu_|op1_low[3] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), .devclrn(devclrn), .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), - .portbdataout()); + .q(\z80_|alu_|op1_low [3]), + .prn(vcc)); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; +defparam \z80_|alu_|op1_low[3] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_low[3] .power_up = "low"; // synopsys translate_on -// Location: M9K_X33_Y18_N0 +// Location: LCCOMB_X31_Y17_N4 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~15 ( +// Equation(s): +// \z80_|alu_|db_low[3]~15_combout = (\z80_|execute_|ctl_alu_op2_oe~0_combout & (\z80_|alu_|op2_low [3] & ((\z80_|alu_|op1_low [3]) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout & (((\z80_|alu_|op1_low [3])) +// # (!\z80_|execute_|ctl_alu_op1_oe~1_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datac(\z80_|alu_|op2_low [3]), + .datad(\z80_|alu_|op1_low [3]), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~15 .lut_mask = 16'hF531; +defparam \z80_|alu_|db_low[3]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N24 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~16 ( +// Equation(s): +// \z80_|alu_|db_low[3]~16_combout = (\z80_|alu_|db_low[3]~15_combout & (((\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout & !\z80_|bus_control_|db[5]~15_combout )) # (!\z80_|execute_|ctl_alu_bs_oe~combout ))) + + .dataa(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), + .datab(\z80_|bus_control_|db[5]~15_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datad(\z80_|alu_|db_low[3]~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~16 .lut_mask = 16'h2F00; +defparam \z80_|alu_|db_low[3]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~33 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~33_combout = (\z80_|execute_|ctl_state_alu~3_combout & (((\z80_|execute_|ctl_alu_op_low~24_combout ) # (\z80_|pla_decode_|Equal56~0_combout )))) # (!\z80_|execute_|ctl_state_alu~3_combout & +// (\z80_|execute_|ctl_mWrite~5_combout & ((\z80_|execute_|ctl_alu_op_low~24_combout ) # (\z80_|pla_decode_|Equal56~0_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~3_combout ), + .datab(\z80_|execute_|ctl_mWrite~5_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~24_combout ), + .datad(\z80_|pla_decode_|Equal56~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~33 .lut_mask = 16'hEEE0; +defparam \z80_|execute_|ctl_alu_op_low~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y20_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~34 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~34_combout = (\z80_|execute_|ctl_alu_op_low~33_combout ) # (((\z80_|execute_|ctl_alu_op_low~28_combout ) # (!\z80_|execute_|ctl_alu_op2_sel_bus~4_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~38_combout )) + + .dataa(\z80_|execute_|ctl_alu_op_low~33_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~38_combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~28_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~34 .lut_mask = 16'hFFBF; +defparam \z80_|execute_|ctl_alu_op_low~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~48 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~48_combout = (((!\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|execute_|ctl_alu_op_low~25_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|execute_|ctl_alu_op_low~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~48 .lut_mask = 16'h73FF; +defparam \z80_|execute_|ctl_alu_op_low~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~35 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~35_combout = (\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # (((\z80_|execute_|ctl_alu_op_low~22_combout & \z80_|execute_|ctl_mWrite~17_combout )) # (!\z80_|execute_|ctl_alu_op_low~45_combout )) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~45_combout ), + .datad(\z80_|execute_|ctl_mWrite~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~35 .lut_mask = 16'hEFAF; +defparam \z80_|execute_|ctl_alu_op_low~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~36 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~36_combout = (((\z80_|execute_|ctl_alu_op_low~35_combout ) # (!\z80_|execute_|ctl_alu_core_R~4_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~10_combout )) # (!\z80_|execute_|ctl_alu_op_low~23_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~23_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), + .datac(\z80_|execute_|ctl_alu_core_R~4_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~35_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~36 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_alu_op_low~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y20_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~37 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~37_combout = (\z80_|execute_|ctl_alu_op_low~34_combout ) # (((\z80_|execute_|ctl_alu_op_low~36_combout ) # (!\z80_|execute_|ctl_alu_op_low~48_combout )) # (!\z80_|execute_|ctl_alu_op_low~31_combout )) + + .dataa(\z80_|execute_|ctl_alu_op_low~34_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~31_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~48_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~36_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~37 .lut_mask = 16'hFFBF; +defparam \z80_|execute_|ctl_alu_op_low~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|pla_decode_|Equal21~1_combout & !\z80_|sequencer_|DFFE_M1_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 .lut_mask = 16'h0088; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y20_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~38 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~38_combout = (\z80_|execute_|ixy_d~5_combout & (((\z80_|execute_|ctl_mRead~34_combout ) # (\z80_|pla_decode_|Equal39~0_combout )))) # (!\z80_|execute_|ixy_d~5_combout & (\z80_|execute_|ctl_eval_cond~0_combout & +// (\z80_|execute_|ctl_mRead~34_combout ))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|pla_decode_|Equal39~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~38 .lut_mask = 16'hECE0; +defparam \z80_|execute_|ctl_alu_op_low~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~39 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~39_combout = (\z80_|execute_|ixy_d~9_combout & ((\z80_|pla_decode_|Equal39~0_combout ) # ((\z80_|pla_decode_|Equal40~1_combout )))) # (!\z80_|execute_|ixy_d~9_combout & (((\z80_|execute_|ixy_d~5_combout & +// \z80_|pla_decode_|Equal40~1_combout )))) + + .dataa(\z80_|pla_decode_|Equal39~0_combout ), + .datab(\z80_|execute_|ixy_d~9_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|pla_decode_|Equal40~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~39 .lut_mask = 16'hFC88; +defparam \z80_|execute_|ctl_alu_op_low~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y20_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~40 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~40_combout = (\z80_|execute_|ctl_alu_op_low~37_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ) # ((\z80_|execute_|ctl_alu_op_low~38_combout ) # (\z80_|execute_|ctl_alu_op_low~39_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~37_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), + .datac(\z80_|execute_|ctl_alu_op_low~38_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~39_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~40 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_alu_op_low~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~41 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~41_combout = (\z80_|execute_|ctl_alu_op_low~40_combout ) # ((\z80_|pla_decode_|Equal21~1_combout & ((\z80_|execute_|ixy_d~5_combout ) # (\z80_|execute_|ixy_d~9_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|execute_|ixy_d~9_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~40_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~41 .lut_mask = 16'hFFC8; +defparam \z80_|execute_|ctl_alu_op_low~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~combout = (\z80_|execute_|ctl_alu_op_low~41_combout ) # ((\z80_|execute_|ixy_d~15_combout & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|execute_|ctl_alu_op_low~41_combout ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|execute_|ixy_d~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low .lut_mask = 16'hFECC; +defparam \z80_|execute_|ctl_alu_op_low .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y16_N25 +dffeas \z80_|alu_|result_lo[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_alu_op_low~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|result_lo [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|result_lo[3] .is_wysiwyg = "true"; +defparam \z80_|alu_|result_lo[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~5_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout & (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal20~0_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .datac(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~5 .lut_mask = 16'h0103; +defparam \z80_|execute_|ctl_alu_oe~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~6_combout = (\z80_|execute_|ctl_alu_oe~5_combout & (((!\z80_|execute_|ctl_mRead~24_combout & !\z80_|execute_|ctl_mRead~25_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~24_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|execute_|ctl_alu_oe~5_combout ), + .datad(\z80_|execute_|ctl_mRead~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~6 .lut_mask = 16'h3070; +defparam \z80_|execute_|ctl_alu_oe~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~9_combout = (\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_mWrite~17_combout ) # ((\z80_|execute_|ctl_alu_oe~1_combout ) # (\z80_|pla_decode_|Equal69~0_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~17_combout ), + .datab(\z80_|execute_|ctl_alu_oe~1_combout ), + .datac(\z80_|pla_decode_|Equal69~0_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~9 .lut_mask = 16'hFE00; +defparam \z80_|execute_|ctl_alu_oe~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~12_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~12_combout & !\z80_|execute_|ctl_ir_we~11_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~12_combout ), + .datab(\z80_|execute_|ctl_ir_we~11_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~12 .lut_mask = 16'hFFF1; +defparam \z80_|execute_|ctl_alu_core_S~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~10_combout = ((\z80_|execute_|ctl_alu_oe~9_combout ) # ((!\z80_|execute_|ctl_alu_core_S~12_combout ) # (!\z80_|execute_|ctl_alu_oe~4_combout ))) # (!\z80_|execute_|ctl_alu_oe~6_combout ) + + .dataa(\z80_|execute_|ctl_alu_oe~6_combout ), + .datab(\z80_|execute_|ctl_alu_oe~9_combout ), + .datac(\z80_|execute_|ctl_alu_oe~4_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~10 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_alu_oe~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~2 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~2_combout = ((!\z80_|execute_|ctl_alu_op_low~25_combout & (!\z80_|execute_|ctl_alu_op_low~24_combout & !\z80_|pla_decode_|Equal56~0_combout ))) # (!\z80_|execute_|ixy_d~7_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~25_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~24_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|pla_decode_|Equal56~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~2 .lut_mask = 16'h0F1F; +defparam \z80_|execute_|ctl_alu_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout = (!\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|nM1_int~2_combout & \z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~1_combout ), + .datab(\z80_|pla_decode_|Equal3~1_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 .lut_mask = 16'h4000; +defparam \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~15 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~15_combout = ((!\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_ir_we~8_combout & !\z80_|execute_|ctl_ir_we~10_combout ))) # (!\z80_|nM1_int~2_combout ) + + .dataa(\z80_|execute_|ctl_ir_we~9_combout ), + .datab(\z80_|execute_|ctl_ir_we~8_combout ), + .datac(\z80_|execute_|ctl_ir_we~10_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~15 .lut_mask = 16'h01FF; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~8_combout = (!\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~15_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout & \z80_|execute_|ctl_flags_sz_we~1_combout ))) + + .dataa(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~15_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), + .datad(\z80_|execute_|ctl_flags_sz_we~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~8 .lut_mask = 16'h0400; +defparam \z80_|execute_|ctl_reg_in_hi~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N6 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~7 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~7_combout = (\z80_|reg_control_|reg_sys_we_lo~6_combout & ((!\z80_|execute_|ixy_d~15_combout ) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|reg_control_|reg_sys_we_lo~6_combout ), + .datac(\z80_|execute_|ixy_d~15_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~7 .lut_mask = 16'h4C4C; +defparam \z80_|reg_control_|reg_sys_we_lo~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~7_combout = (\z80_|execute_|ctl_reg_in_hi~8_combout & (\z80_|reg_control_|reg_sys_we_lo~7_combout & ((!\z80_|pla_decode_|Equal13~2_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~8_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|reg_control_|reg_sys_we_lo~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~7 .lut_mask = 16'h4C00; +defparam \z80_|execute_|ctl_alu_oe~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y17_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~11 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~11_combout = (\z80_|execute_|ctl_flags_use_cf2~13_combout & (((!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~7_combout )) # (!\z80_|execute_|ctl_mWrite~5_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~5_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|execute_|ctl_ir_we~7_combout ), + .datad(\z80_|execute_|ctl_flags_use_cf2~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~11 .lut_mask = 16'h5700; +defparam \z80_|execute_|ctl_mWrite~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_we~5_combout = (\z80_|execute_|ctl_bus_inc_oe~28_combout & (\z80_|execute_|ctl_mWrite~11_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|execute_|ctl_mRead~24_combout )))) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~28_combout ), + .datab(\z80_|execute_|ctl_mRead~24_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|execute_|ctl_mWrite~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_we~5 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_bus_db_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~8_combout = (\z80_|execute_|ctl_reg_in_lo~9_combout & (\z80_|execute_|ctl_alu_oe~2_combout & (\z80_|execute_|ctl_alu_oe~7_combout & \z80_|execute_|ctl_bus_db_we~5_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .datab(\z80_|execute_|ctl_alu_oe~2_combout ), + .datac(\z80_|execute_|ctl_alu_oe~7_combout ), + .datad(\z80_|execute_|ctl_bus_db_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~8 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_oe~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~16 ( +// Equation(s): +// \z80_|execute_|ctl_flags_alu~16_combout = (\z80_|execute_|ctl_flags_alu~10_combout & (!\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout & (\z80_|execute_|ctl_flags_xy_we~10_combout & !\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ))) + + .dataa(\z80_|execute_|ctl_flags_alu~10_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~10_combout ), + .datad(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_alu~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_alu~16 .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_flags_alu~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_oe~11_combout = (\z80_|execute_|ctl_alu_oe~10_combout ) # (((\z80_|execute_|ctl_66_oe~2_combout ) # (!\z80_|execute_|ctl_flags_alu~16_combout )) # (!\z80_|execute_|ctl_alu_oe~8_combout )) + + .dataa(\z80_|execute_|ctl_alu_oe~10_combout ), + .datab(\z80_|execute_|ctl_alu_oe~8_combout ), + .datac(\z80_|execute_|ctl_flags_alu~16_combout ), + .datad(\z80_|execute_|ctl_66_oe~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_oe~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_oe~11 .lut_mask = 16'hFFBF; +defparam \z80_|execute_|ctl_alu_oe~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y19_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~48 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~48_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|pla_decode_|Equal21~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal21~1_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~48 .lut_mask = 16'hD0F0; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_hi~8_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & ((\z80_|execute_|ctl_ir_we~12_combout ) # (!\z80_|execute_|nextM~2_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|execute_|nextM~2_combout ), + .datac(\z80_|execute_|ctl_ir_we~12_combout ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_hi~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_hi~8 .lut_mask = 16'hA200; +defparam \z80_|execute_|ctl_reg_out_hi~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_hi~5_combout = (\z80_|execute_|ctl_reg_out_lo~2_combout & (\z80_|execute_|rsel3~combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|execute_|ctl_mRead~3_combout )))) # (!\z80_|execute_|ctl_reg_out_lo~2_combout & +// (((!\z80_|execute_|ixy_d~7_combout )) # (!\z80_|execute_|ctl_mRead~3_combout ))) + + .dataa(\z80_|execute_|ctl_reg_out_lo~2_combout ), + .datab(\z80_|execute_|ctl_mRead~3_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|rsel3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_hi~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_hi~5 .lut_mask = 16'h3F15; +defparam \z80_|execute_|ctl_reg_out_hi~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~2 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~2_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|execute_|ctl_mWrite~8_combout & ((!\z80_|execute_|ctl_mRead~7_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|execute_|ctl_eval_cond~0_combout & +// (((!\z80_|execute_|ctl_mRead~7_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|ctl_mWrite~8_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|execute_|ctl_mRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~2 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_sw_2u~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~0 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~0_combout = (\z80_|execute_|ctl_state_alu~3_combout & (!\z80_|execute_|ctl_mWrite~6_combout & ((!\z80_|pla_decode_|Equal9~1_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|execute_|ctl_state_alu~3_combout & +// (((!\z80_|pla_decode_|Equal9~1_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~3_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|pla_decode_|Equal9~1_combout ), + .datad(\z80_|execute_|ctl_mWrite~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~0 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_sw_2u~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~3 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~3_combout = (\z80_|execute_|ctl_sw_2u~2_combout & (\z80_|execute_|ctl_sw_2u~0_combout & ((!\z80_|execute_|ctl_mRead~6_combout ) # (!\z80_|execute_|ctl_alu_oe~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_oe~0_combout ), + .datab(\z80_|execute_|ctl_mRead~6_combout ), + .datac(\z80_|execute_|ctl_sw_2u~2_combout ), + .datad(\z80_|execute_|ctl_sw_2u~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~3 .lut_mask = 16'h7000; +defparam \z80_|execute_|ctl_sw_2u~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y15_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~47 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~47_combout = (\z80_|execute_|ctl_sw_2u~3_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|execute_|ctl_mRead~8_combout )) # (!\z80_|sequencer_|M5~q ))) + + .dataa(\z80_|sequencer_|M5~q ), + .datab(\z80_|execute_|ctl_sw_2u~3_combout ), + .datac(\z80_|execute_|ctl_mRead~8_combout ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~47 .lut_mask = 16'hCC4C; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y18_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~33 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~33_combout = (\z80_|execute_|ctl_state_alu~3_combout & (!\z80_|pla_decode_|Equal47~0_combout & ((!\z80_|execute_|ctl_ir_we~4_combout ) # (!\z80_|pla_decode_|Equal34~0_combout )))) # (!\z80_|execute_|ctl_state_alu~3_combout & +// (((!\z80_|execute_|ctl_ir_we~4_combout )) # (!\z80_|pla_decode_|Equal34~0_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~3_combout ), + .datab(\z80_|pla_decode_|Equal34~0_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~33 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_inc_cy~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~37 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~37_combout = (\z80_|execute_|ctl_inc_cy~33_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|sequencer_|DFFE_M4_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|pla_decode_|Equal19~0_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|execute_|ctl_inc_cy~33_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~37 .lut_mask = 16'hF700; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~6 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~6_combout = (\z80_|execute_|ctl_reg_gp_sel~7_combout & (\z80_|ir_|opcode [0] $ ((!\z80_|execute_|comb~0_combout )))) # (!\z80_|execute_|ctl_reg_gp_sel~7_combout & (!\z80_|execute_|ctl_sw_2u~5_combout & (\z80_|ir_|opcode [0] $ +// (!\z80_|execute_|comb~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel~7_combout ), + .datab(\z80_|ir_|opcode [0]), + .datac(\z80_|execute_|comb~0_combout ), + .datad(\z80_|execute_|ctl_sw_2u~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~6 .lut_mask = 16'h82C3; +defparam \z80_|execute_|ctl_sw_2u~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_hi~6_combout = (\z80_|execute_|ctl_reg_out_hi~5_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~37_combout & !\z80_|execute_|ctl_sw_2u~6_combout ))) + + .dataa(\z80_|execute_|ctl_reg_out_hi~5_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~37_combout ), + .datad(\z80_|execute_|ctl_sw_2u~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_hi~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_hi~6 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_out_hi~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_hi~7_combout = (((\z80_|execute_|ctl_reg_out_hi~8_combout ) # (!\z80_|execute_|ctl_reg_out_hi~6_combout )) # (!\z80_|execute_|ctl_reg_out_hi~4_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), + .datab(\z80_|execute_|ctl_reg_out_hi~4_combout ), + .datac(\z80_|execute_|ctl_reg_out_hi~8_combout ), + .datad(\z80_|execute_|ctl_reg_out_hi~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_hi~7 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|ctl_reg_out_hi~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~2 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~2_combout = (\z80_|pla_decode_|Equal3~0_combout & (\z80_|pla_decode_|Equal1~7_combout & (\z80_|pla_decode_|Equal2~0_combout & !\z80_|ir_|opcode [5]))) + + .dataa(\z80_|pla_decode_|Equal3~0_combout ), + .datab(\z80_|pla_decode_|Equal1~7_combout ), + .datac(\z80_|pla_decode_|Equal2~0_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~2 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_mRead~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~6 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~6_combout = (\z80_|pla_decode_|Equal9~1_combout & (!\z80_|execute_|ixy_d~6_combout & ((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) # (!\z80_|pla_decode_|Equal9~1_combout & +// (((!\z80_|execute_|ctl_mRead~9_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|pla_decode_|Equal47~0_combout ), + .datac(\z80_|execute_|ctl_mRead~9_combout ), + .datad(\z80_|execute_|ixy_d~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~6 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_sw_2d~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~7 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~7_combout = (\z80_|execute_|ctl_sw_2d~6_combout & (((!\z80_|execute_|ctl_mRead~2_combout & !\z80_|pla_decode_|Equal6~1_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_mRead~2_combout ), + .datac(\z80_|pla_decode_|Equal6~1_combout ), + .datad(\z80_|execute_|ctl_sw_2d~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~7 .lut_mask = 16'h5700; +defparam \z80_|execute_|ctl_sw_2d~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout = (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal1~4_combout & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|ir_|opcode [0]))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|pla_decode_|Equal1~4_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~8 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~8_combout = (\z80_|execute_|ctl_flags_sz_we~0_combout & (\z80_|execute_|ctl_sw_2d~7_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout & \z80_|execute_|ctl_alu_shift_oe~44_combout ))) + + .dataa(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .datab(\z80_|execute_|ctl_sw_2d~7_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~44_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~8 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_sw_2d~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~7 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~7_combout = (\z80_|execute_|ctl_flags_alu~19_combout & (((!\z80_|execute_|ctl_mRead~25_combout & !\z80_|execute_|ctl_mRead~24_combout )) # (!\z80_|execute_|ixy_d~9_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~25_combout ), + .datab(\z80_|execute_|ctl_flags_alu~19_combout ), + .datac(\z80_|execute_|ixy_d~9_combout ), + .datad(\z80_|execute_|ctl_mRead~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~7 .lut_mask = 16'h0C4C; +defparam \z80_|execute_|ctl_bus_db_oe~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~5 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~5_combout = (\z80_|execute_|ctl_bus_db_oe~7_combout & (((!\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_bus_db_oe~1_combout )) # (!\z80_|execute_|ixy_d~7_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(\z80_|execute_|ctl_bus_db_oe~7_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~5 .lut_mask = 16'h4C0C; +defparam \z80_|execute_|ctl_sw_2d~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~19 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~19_combout = (\z80_|execute_|ctl_mRead~15_combout ) # ((\z80_|pla_decode_|Equal9~1_combout ) # ((!\z80_|pla_decode_|Equal12~1_combout & \z80_|pla_decode_|Equal25~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal12~1_combout ), + .datab(\z80_|execute_|ctl_mRead~15_combout ), + .datac(\z80_|pla_decode_|Equal9~1_combout ), + .datad(\z80_|pla_decode_|Equal25~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~19 .lut_mask = 16'hFDFC; +defparam \z80_|execute_|ctl_mRead~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~18 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~18_combout = (\z80_|execute_|ctl_mRead~8_combout ) # ((\z80_|execute_|ctl_mRead~13_combout ) # ((\z80_|execute_|ctl_mRead~7_combout ) # (\z80_|execute_|ctl_mRead~6_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~8_combout ), + .datab(\z80_|execute_|ctl_mRead~13_combout ), + .datac(\z80_|execute_|ctl_mRead~7_combout ), + .datad(\z80_|execute_|ctl_mRead~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~18 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_mRead~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N26 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~2 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~2_combout = (\z80_|pla_decode_|Equal35~0_combout ) # ((\z80_|pla_decode_|Equal34~0_combout ) # ((\z80_|pla_decode_|Equal37~0_combout ) # (\z80_|pla_decode_|Equal38~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal35~0_combout ), + .datab(\z80_|pla_decode_|Equal34~0_combout ), + .datac(\z80_|pla_decode_|Equal37~0_combout ), + .datad(\z80_|pla_decode_|Equal38~2_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~2 .lut_mask = 16'hFFFE; +defparam \z80_|reg_control_|reg_sys_we_lo~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal24~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal24~1_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal1~7_combout & \z80_|pla_decode_|Equal9~0_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal2~0_combout ), + .datac(\z80_|pla_decode_|Equal1~7_combout ), + .datad(\z80_|pla_decode_|Equal9~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal24~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal24~1 .lut_mask = 16'h4000; +defparam \z80_|pla_decode_|Equal24~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N12 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~3 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~3_combout = (\z80_|pla_decode_|Equal29~0_combout ) # ((\z80_|pla_decode_|Equal19~0_combout ) # ((\z80_|reg_control_|reg_sys_we_lo~2_combout ) # (\z80_|pla_decode_|Equal24~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal29~0_combout ), + .datab(\z80_|pla_decode_|Equal19~0_combout ), + .datac(\z80_|reg_control_|reg_sys_we_lo~2_combout ), + .datad(\z80_|pla_decode_|Equal24~1_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~3 .lut_mask = 16'hFFFE; +defparam \z80_|reg_control_|reg_sys_we_lo~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N2 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~4 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~4_combout = (\z80_|reg_control_|reg_sys_we_lo~3_combout & (!\z80_|execute_|ctl_state_alu~2_combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) # +// (!\z80_|reg_control_|reg_sys_we_lo~3_combout & (((!\z80_|execute_|ctl_state_alu~4_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~3_combout ), + .datab(\z80_|pla_decode_|Equal47~0_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo~4 .lut_mask = 16'h135F; +defparam \z80_|reg_control_|reg_sys_we_lo~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~20 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~20_combout = (\z80_|reg_control_|reg_sys_we_lo~4_combout & (((!\z80_|execute_|ctl_mRead~19_combout & !\z80_|execute_|ctl_mRead~18_combout )) # (!\z80_|execute_|ctl_state_alu~2_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~19_combout ), + .datab(\z80_|execute_|ctl_mRead~18_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|reg_control_|reg_sys_we_lo~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~20 .lut_mask = 16'h1F00; +defparam \z80_|execute_|ctl_mRead~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~5_combout = ((!\z80_|execute_|ctl_mRead~13_combout & (!\z80_|execute_|ctl_mRead~15_combout & !\z80_|execute_|ctl_mRead~16_combout ))) # (!\z80_|execute_|ixy_d~6_combout ) + + .dataa(\z80_|execute_|ctl_mRead~13_combout ), + .datab(\z80_|execute_|ctl_mRead~15_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ctl_mRead~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~5 .lut_mask = 16'h0F1F; +defparam \z80_|execute_|ctl_reg_in_hi~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y17_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~22 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~22_combout = (\z80_|execute_|ctl_mRead~20_combout & (\z80_|execute_|ctl_reg_in_hi~5_combout & ((!\z80_|execute_|ctl_mRead~16_combout ) # (!\z80_|execute_|ctl_state_alu~4_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|ctl_mRead~20_combout ), + .datac(\z80_|execute_|ctl_mRead~16_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~22 .lut_mask = 16'h4C00; +defparam \z80_|execute_|ctl_mRead~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout = (\z80_|execute_|ixy_d~6_combout & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal52~0_combout & !\z80_|ir_|opcode [0]))) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|pla_decode_|Equal3~1_combout ), + .datac(\z80_|pla_decode_|Equal52~0_combout ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~6_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & (((!\z80_|pla_decode_|Equal35~0_combout & !\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|execute_|ixy_d~6_combout ))) + + .dataa(\z80_|pla_decode_|Equal35~0_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~6 .lut_mask = 16'h0037; +defparam \z80_|execute_|ctl_reg_in_hi~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~2_combout = (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|M5~q ) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|sequencer_|M5~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~2 .lut_mask = 16'hAA00; +defparam \z80_|execute_|ctl_reg_in_hi~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|setM1~30 ( +// Equation(s): +// \z80_|execute_|setM1~30_combout = (\z80_|execute_|ixy_d~6_combout & (!\z80_|execute_|ctl_mRead~14_combout & ((!\z80_|execute_|ctl_mRead~15_combout ) # (!\z80_|execute_|ctl_reg_in_hi~2_combout )))) # (!\z80_|execute_|ixy_d~6_combout & +// (((!\z80_|execute_|ctl_mRead~15_combout )) # (!\z80_|execute_|ctl_reg_in_hi~2_combout ))) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datac(\z80_|execute_|ctl_mRead~14_combout ), + .datad(\z80_|execute_|ctl_mRead~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~30 .lut_mask = 16'h135F; +defparam \z80_|execute_|setM1~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~23 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~23_combout = (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|execute_|ctl_mRead~14_combout & ((!\z80_|execute_|ctl_mRead~15_combout ) # (!\z80_|execute_|ctl_state_alu~4_combout )))) # (!\z80_|execute_|ctl_state_alu~2_combout +// & (((!\z80_|execute_|ctl_mRead~15_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_mRead~14_combout ), + .datad(\z80_|execute_|ctl_mRead~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~23 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_mRead~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~6_combout = (\z80_|execute_|setM1~30_combout & (\z80_|execute_|ctl_mRead~23_combout & ((!\z80_|pla_decode_|Equal6~1_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) + + .dataa(\z80_|execute_|setM1~30_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|execute_|ctl_mRead~23_combout ), + .datad(\z80_|pla_decode_|Equal6~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~6 .lut_mask = 16'h20A0; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~3_combout = ((!\z80_|execute_|ctl_mRead~7_combout & (!\z80_|execute_|ctl_mRead~8_combout & !\z80_|execute_|ctl_mRead~6_combout ))) # (!\z80_|execute_|ixy_d~6_combout ) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|execute_|ctl_mRead~7_combout ), + .datac(\z80_|execute_|ctl_mRead~8_combout ), + .datad(\z80_|execute_|ctl_mRead~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~3 .lut_mask = 16'h5557; +defparam \z80_|execute_|ctl_reg_in_hi~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~10 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~10_combout = (\z80_|execute_|ctl_flags_alu~17_combout & (\z80_|execute_|ctl_flags_alu~6_combout & \z80_|execute_|ctl_reg_in_hi~3_combout )) + + .dataa(\z80_|execute_|ctl_flags_alu~17_combout ), + .datab(\z80_|execute_|ctl_flags_alu~6_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_in_hi~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~10 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_mWrite~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y18_N26 +cycloneive_lcell_comb \z80_|execute_|fMRead~18 ( +// Equation(s): +// \z80_|execute_|fMRead~18_combout = (\z80_|execute_|ctl_ir_we~15_combout & (!\z80_|execute_|ctl_state_alu~2_combout & ((!\z80_|execute_|ctl_mRead~16_combout ) # (!\z80_|execute_|ctl_reg_in_hi~2_combout )))) # (!\z80_|execute_|ctl_ir_we~15_combout & +// (((!\z80_|execute_|ctl_mRead~16_combout )) # (!\z80_|execute_|ctl_reg_in_hi~2_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~15_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_mRead~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~18 .lut_mask = 16'h135F; +defparam \z80_|execute_|fMRead~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N14 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_pc~0_combout = ((!\z80_|pla_decode_|Equal37~0_combout & ((!\z80_|pla_decode_|Equal24~0_combout ) # (!\z80_|pla_decode_|Equal9~0_combout )))) # (!\z80_|execute_|ixy_d~6_combout ) + + .dataa(\z80_|pla_decode_|Equal37~0_combout ), + .datab(\z80_|pla_decode_|Equal9~0_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|pla_decode_|Equal24~0_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_pc~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_pc~0 .lut_mask = 16'h1F5F; +defparam \z80_|reg_control_|reg_sel_pc~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N8 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~1 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_pc~1_combout = (\z80_|pla_decode_|Equal29~0_combout & (!\z80_|execute_|ixy_d~6_combout & ((!\z80_|execute_|ctl_reg_in_hi~2_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) # (!\z80_|pla_decode_|Equal29~0_combout & +// (((!\z80_|execute_|ctl_reg_in_hi~2_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal29~0_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|pla_decode_|Equal47~0_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_pc~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_pc~1 .lut_mask = 16'h0777; +defparam \z80_|reg_control_|reg_sel_pc~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N18 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~2 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_pc~2_combout = (\z80_|reg_control_|reg_sel_pc~0_combout & (\z80_|reg_control_|reg_sel_pc~1_combout & ((!\z80_|pla_decode_|Equal38~2_combout ) # (!\z80_|execute_|ixy_d~6_combout )))) + + .dataa(\z80_|reg_control_|reg_sel_pc~0_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|reg_control_|reg_sel_pc~1_combout ), + .datad(\z80_|pla_decode_|Equal38~2_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_pc~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_pc~2 .lut_mask = 16'h20A0; +defparam \z80_|reg_control_|reg_sel_pc~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y18_N18 +cycloneive_lcell_comb \z80_|execute_|fMRead~19 ( +// Equation(s): +// \z80_|execute_|fMRead~19_combout = (\z80_|reg_control_|reg_sel_pc~2_combout & (\z80_|execute_|ctl_state_alu~7_combout & ((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|ctl_ir_we~7_combout )))) + + .dataa(\z80_|reg_control_|reg_sel_pc~2_combout ), + .datab(\z80_|execute_|ctl_ir_we~7_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_state_alu~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~19 .lut_mask = 16'h2A00; +defparam \z80_|execute_|fMRead~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|fMRead~20 ( +// Equation(s): +// \z80_|execute_|fMRead~20_combout = (\z80_|execute_|ctl_mWrite~10_combout & (\z80_|execute_|ctl_sw_2d~4_combout & (\z80_|execute_|fMRead~18_combout & \z80_|execute_|fMRead~19_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~10_combout ), + .datab(\z80_|execute_|ctl_sw_2d~4_combout ), + .datac(\z80_|execute_|fMRead~18_combout ), + .datad(\z80_|execute_|fMRead~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~20 .lut_mask = 16'h8000; +defparam \z80_|execute_|fMRead~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|fMRead~21 ( +// Equation(s): +// \z80_|execute_|fMRead~21_combout = (\z80_|execute_|ctl_mRead~22_combout & (\z80_|execute_|ctl_reg_in_hi~6_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~6_combout & \z80_|execute_|fMRead~20_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~22_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~6_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), + .datad(\z80_|execute_|fMRead~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~21 .lut_mask = 16'h8000; +defparam \z80_|execute_|fMRead~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~9 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~9_combout = (\z80_|execute_|ctl_sw_2d~8_combout & (\z80_|execute_|ctl_sw_2d~5_combout & (!\z80_|execute_|ctl_alu_shift_oe~16_combout & \z80_|execute_|fMRead~21_combout ))) + + .dataa(\z80_|execute_|ctl_sw_2d~8_combout ), + .datab(\z80_|execute_|ctl_sw_2d~5_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~16_combout ), + .datad(\z80_|execute_|fMRead~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~9 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_sw_2d~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~14 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~14_combout = (!\z80_|execute_|ctl_mRead~12_combout & (((\z80_|decode_state_|in_halt~q ) # (!\z80_|pla_decode_|Equal77~0_combout )) # (!\z80_|pla_decode_|Equal33~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|decode_state_|in_halt~q ), + .datac(\z80_|execute_|ctl_mRead~12_combout ), + .datad(\z80_|pla_decode_|Equal77~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~14 .lut_mask = 16'h0D0F; +defparam \z80_|execute_|ctl_sw_2d~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~8 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~8_combout = (((\z80_|ir_|opcode [5] & !\z80_|ir_|opcode [4])) # (!\z80_|ir_|opcode [3])) # (!\z80_|pla_decode_|Equal12~0_combout ) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|pla_decode_|Equal12~0_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~8 .lut_mask = 16'h2FFF; +defparam \z80_|execute_|ctl_sw_1d~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~10 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~10_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (((\z80_|execute_|rsel3~combout & \z80_|execute_|ctl_iorw~10_combout )) # (!\z80_|execute_|nextM~2_combout ))) + + .dataa(\z80_|execute_|rsel3~combout ), + .datab(\z80_|execute_|ctl_iorw~10_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|nextM~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~10 .lut_mask = 16'h80F0; +defparam \z80_|execute_|ctl_sw_2d~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~11 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~11_combout = (\z80_|execute_|ctl_sw_2d~10_combout ) # ((\z80_|nM1_int~2_combout & ((!\z80_|execute_|ctl_sw_1d~8_combout ) # (!\z80_|execute_|ctl_sw_2d~14_combout )))) + + .dataa(\z80_|execute_|ctl_sw_2d~14_combout ), + .datab(\z80_|execute_|ctl_sw_1d~8_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_sw_2d~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~11 .lut_mask = 16'hFF70; +defparam \z80_|execute_|ctl_sw_2d~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~12 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~12_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|execute_|rsel3~combout & ((\z80_|execute_|ctl_alu_shift_oe~15_combout ) # (\z80_|execute_|ctl_alu_op_low~28_combout )))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~15_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~28_combout ), + .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datad(\z80_|execute_|rsel3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~12 .lut_mask = 16'hFEF0; +defparam \z80_|execute_|ctl_sw_2d~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~13 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2d~13_combout = ((\z80_|execute_|ctl_sw_2d~11_combout ) # ((\z80_|execute_|ctl_sw_2d~12_combout ) # (!\z80_|execute_|ctl_reg_out_lo~7_combout ))) # (!\z80_|execute_|ctl_sw_2d~9_combout ) + + .dataa(\z80_|execute_|ctl_sw_2d~9_combout ), + .datab(\z80_|execute_|ctl_sw_2d~11_combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .datad(\z80_|execute_|ctl_sw_2d~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2d~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2d~13 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|ctl_sw_2d~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N8 +cycloneive_lcell_comb \z80_|alu_|db[7]~9 ( +// Equation(s): +// \z80_|alu_|db[7]~9_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout ) # ((\z80_|execute_|ctl_sw_2d~13_combout ) # (\z80_|execute_|ctl_alu_oe~11_combout )) + + .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_sw_2d~13_combout ), + .datad(\z80_|execute_|ctl_alu_oe~11_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[7]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[7]~9 .lut_mask = 16'hFFFA; +defparam \z80_|alu_|db[7]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N0 +cycloneive_lcell_comb \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 ( +// Equation(s): +// \z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout = (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )) # (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ))) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datad(\z80_|pla_decode_|Equal47~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 .lut_mask = 16'h1333; +defparam \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout = (\z80_|ir_|opcode [3] & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|pla_decode_|Equal63~0_combout & \z80_|ir_|opcode [4]))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|pla_decode_|Equal63~0_combout ), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~32 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~32_combout = (((!\z80_|pla_decode_|Equal3~0_combout & !\z80_|pla_decode_|Equal21~0_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal63~0_combout ) + + .dataa(\z80_|pla_decode_|Equal63~0_combout ), + .datab(\z80_|pla_decode_|Equal3~0_combout ), + .datac(\z80_|pla_decode_|Equal21~0_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~32 .lut_mask = 16'h57FF; +defparam \z80_|execute_|ctl_alu_op_low~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N2 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~2 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~2_combout = ((!\z80_|pla_decode_|Equal20~0_combout & ((!\z80_|pla_decode_|Equal68~2_combout ) # (!\z80_|pla_decode_|Equal1~4_combout )))) # (!\z80_|nM1_int~2_combout ) + + .dataa(\z80_|pla_decode_|Equal20~0_combout ), + .datab(\z80_|pla_decode_|Equal1~4_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal68~2_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~2 .lut_mask = 16'h1F5F; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~22 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~22_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|ir_|opcode [4])) # (!\z80_|pla_decode_|Equal63~0_combout )) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~22 .lut_mask = 16'hFBFF; +defparam \z80_|execute_|ctl_flags_xy_we~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N28 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~3 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~3_combout = (\z80_|execute_|ctl_alu_op_low~32_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~2_combout & \z80_|execute_|ctl_flags_xy_we~22_combout )) + + .dataa(\z80_|execute_|ctl_alu_op_low~32_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~2_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_flags_xy_we~22_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~3 .lut_mask = 16'h8800; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y18_N2 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~4 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~4_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~3_combout & (\z80_|execute_|ctl_flags_pf_we~10_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~8_combout & \z80_|execute_|ctl_alu_op_low~45_combout ))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~3_combout ), + .datab(\z80_|execute_|ctl_flags_pf_we~10_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~45_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~4 .lut_mask = 16'h8000; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N16 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~5 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~5_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout & (((!\z80_|pla_decode_|Equal21~0_combout & !\z80_|pla_decode_|Equal32~0_combout )) # (!\z80_|pla_decode_|Equal62~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal21~0_combout ), + .datab(\z80_|pla_decode_|Equal32~0_combout ), + .datac(\z80_|pla_decode_|Equal62~2_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~5 .lut_mask = 16'h1F00; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N8 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout = (\z80_|execute_|ctl_alu_shift_oe~38_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|execute_|ctl_ir_we~11_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|execute_|ctl_alu_shift_oe~38_combout ), + .datac(\z80_|execute_|ctl_ir_we~11_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 .lut_mask = 16'hCC4C; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N2 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout & (\z80_|execute_|ctl_flags_sz_we~4_combout & ((!\z80_|pla_decode_|Equal62~2_combout ) # (!\z80_|pla_decode_|Equal9~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal9~0_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ), + .datac(\z80_|pla_decode_|Equal62~2_combout ), + .datad(\z80_|execute_|ctl_flags_sz_we~4_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 .lut_mask = 16'h4C00; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~15 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~15_combout = (\z80_|ir_|opcode [5]) # (((!\z80_|pla_decode_|Equal32~0_combout & !\z80_|pla_decode_|Equal9~0_combout )) # (!\z80_|execute_|ctl_state_alu~11_combout )) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|execute_|ctl_state_alu~11_combout ), + .datac(\z80_|pla_decode_|Equal32~0_combout ), + .datad(\z80_|pla_decode_|Equal9~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~15 .lut_mask = 16'hBBBF; +defparam \z80_|execute_|ctl_alu_core_hf~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N8 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~6 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~6_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout & \z80_|execute_|ctl_alu_core_hf~15_combout ) + + .dataa(gnd), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~15_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~6 .lut_mask = 16'hC0C0; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N10 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~7 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~7_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~5_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~9_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout & !\z80_|execute_|ctl_alu_core_R~1_combout ))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~9_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ), + .datad(\z80_|execute_|ctl_alu_core_R~1_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~7 .lut_mask = 16'h0080; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|ir_|opcode [3]))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N20 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout = (\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ) # ((\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal10~0_combout ) # (\z80_|pla_decode_|Equal61~2_combout )))) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal61~2_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 .lut_mask = 16'hFCEC; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~17 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~17_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal3~1_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~17 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N18 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ) # ((\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ) # ((\z80_|alu_control_|db[1]~26_combout & \z80_|execute_|ctl_flags_bus~combout ))) + + .dataa(\z80_|alu_control_|db[1]~26_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ), + .datac(\z80_|execute_|ctl_flags_bus~combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 .lut_mask = 16'hFFEC; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N4 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout = ((\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ) # ((\z80_|alu_|db_high[3]~7_combout & \z80_|execute_|ctl_flags_alu~15_combout ))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ) + + .dataa(\z80_|alu_|db_high[3]~7_combout ), + .datab(\z80_|execute_|ctl_flags_alu~15_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 .lut_mask = 16'hFF8F; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_nf_we~3_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal10~0_combout ) # ((\z80_|pla_decode_|Equal11~0_combout ) # (\z80_|pla_decode_|Equal61~2_combout )))) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal61~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_nf_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_nf_we~3 .lut_mask = 16'hF0E0; +defparam \z80_|execute_|ctl_flags_nf_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y20_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~0 ( +// Equation(s): +// \z80_|execute_|ctl_flags_nf_we~0_combout = (\z80_|pla_decode_|Equal61~2_combout & (!\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|execute_|ctl_mRead~34_combout )))) # (!\z80_|pla_decode_|Equal61~2_combout & +// (((!\z80_|execute_|ixy_d~5_combout )) # (!\z80_|execute_|ctl_mRead~34_combout ))) + + .dataa(\z80_|pla_decode_|Equal61~2_combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_nf_we~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_nf_we~0 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_flags_nf_we~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y17_N0 +cycloneive_lcell_comb \z80_|pla_decode_|Equal73~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal73~2_combout = (\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [4] & (\z80_|execute_|ctl_state_alu~11_combout & \z80_|ir_|opcode [3]))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|execute_|ctl_state_alu~11_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal73~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal73~2 .lut_mask = 16'h2000; +defparam \z80_|pla_decode_|Equal73~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N26 +cycloneive_lcell_comb \z80_|pla_decode_|Equal72~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal72~2_combout = (\z80_|ir_|opcode [5] & (\z80_|execute_|ctl_state_alu~11_combout & (\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [3]))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|execute_|ctl_state_alu~11_combout ), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal72~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal72~2 .lut_mask = 16'h0080; +defparam \z80_|pla_decode_|Equal72~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y20_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~1 ( +// Equation(s): +// \z80_|execute_|ctl_flags_nf_we~1_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout & (\z80_|execute_|ctl_flags_nf_we~0_combout & (!\z80_|pla_decode_|Equal73~2_combout & !\z80_|pla_decode_|Equal72~2_combout ))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ), + .datab(\z80_|execute_|ctl_flags_nf_we~0_combout ), + .datac(\z80_|pla_decode_|Equal73~2_combout ), + .datad(\z80_|pla_decode_|Equal72~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_nf_we~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_nf_we~1 .lut_mask = 16'h0008; +defparam \z80_|execute_|ctl_flags_nf_we~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_nf_we~2_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~18_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout & (\z80_|execute_|ctl_alu_core_hf~15_combout & \z80_|execute_|ctl_flags_nf_we~1_combout ))) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~15_combout ), + .datad(\z80_|execute_|ctl_flags_nf_we~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_nf_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_nf_we~2 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_flags_nf_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~5_combout = (\z80_|sequencer_|DFFE_T4_ff~q ) # ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~5 .lut_mask = 16'hFFBB; +defparam \z80_|execute_|ctl_flags_sz_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~6_combout = (\z80_|execute_|ctl_flags_sz_we~5_combout & ((\z80_|execute_|ctl_alu_core_R~0_combout ) # ((\z80_|pla_decode_|Equal48~0_combout & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) # +// (!\z80_|execute_|ctl_flags_sz_we~5_combout & (((\z80_|pla_decode_|Equal48~0_combout & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) + + .dataa(\z80_|execute_|ctl_flags_sz_we~5_combout ), + .datab(\z80_|execute_|ctl_alu_core_R~0_combout ), + .datac(\z80_|pla_decode_|Equal48~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~6 .lut_mask = 16'hF888; +defparam \z80_|execute_|ctl_flags_sz_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_nf_we~4_combout = (\z80_|execute_|ctl_flags_nf_we~3_combout ) # (((\z80_|execute_|ctl_flags_sz_we~6_combout ) # (!\z80_|execute_|ctl_flags_xy_we~14_combout )) # (!\z80_|execute_|ctl_flags_nf_we~2_combout )) + + .dataa(\z80_|execute_|ctl_flags_nf_we~3_combout ), + .datab(\z80_|execute_|ctl_flags_nf_we~2_combout ), + .datac(\z80_|execute_|ctl_flags_sz_we~6_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_nf_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_nf_we~4 .lut_mask = 16'hFBFF; +defparam \z80_|execute_|ctl_flags_nf_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N24 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~8 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_nf~8_combout = (\z80_|execute_|ctl_flags_nf_we~4_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~7_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ))) # (!\z80_|execute_|ctl_flags_nf_we~4_combout & +// (((\z80_|alu_flags_|DFFE_inst_latch_nf~q )))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~7_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .datad(\z80_|execute_|ctl_flags_nf_we~4_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~8 .lut_mask = 16'h88F0; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y19_N25 +dffeas \z80_|alu_flags_|DFFE_inst_latch_nf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_nf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_nf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~14 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_cpl~14_combout = (\z80_|ir_|opcode [4]) # (!\z80_|pla_decode_|Equal63~0_combout ) + + .dataa(gnd), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(gnd), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_cpl~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_cpl~14 .lut_mask = 16'hFF33; +defparam \z80_|execute_|ctl_flags_hf_cpl~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_cpl~10_combout = (\z80_|execute_|ctl_flags_hf_cpl~14_combout & (!\z80_|execute_|ctl_alu_op_low~27_combout & (!\z80_|execute_|ctl_state_alu~5_combout & !\z80_|pla_decode_|Equal68~3_combout ))) + + .dataa(\z80_|execute_|ctl_flags_hf_cpl~14_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~27_combout ), + .datac(\z80_|execute_|ctl_state_alu~5_combout ), + .datad(\z80_|pla_decode_|Equal68~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_cpl~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_cpl~10 .lut_mask = 16'h0002; +defparam \z80_|execute_|ctl_flags_hf_cpl~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal45~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal45~0_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [1] & \z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~1_combout ), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal45~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal45~0 .lut_mask = 16'h0800; +defparam \z80_|pla_decode_|Equal45~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~11 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_cpl~11_combout = (\z80_|execute_|ctl_state_alu~6_combout ) # ((\z80_|pla_decode_|Equal52~1_combout ) # ((\z80_|pla_decode_|Equal45~0_combout & !\z80_|decode_state_|use_ixiy~combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~6_combout ), + .datab(\z80_|pla_decode_|Equal45~0_combout ), + .datac(\z80_|decode_state_|use_ixiy~combout ), + .datad(\z80_|pla_decode_|Equal52~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_cpl~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_cpl~11 .lut_mask = 16'hFFAE; +defparam \z80_|execute_|ctl_flags_hf_cpl~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~12 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_cpl~12_combout = ((\z80_|execute_|ctl_alu_op_low~25_combout ) # ((\z80_|pla_decode_|Equal10~0_combout ) # (\z80_|execute_|ctl_flags_hf_cpl~11_combout ))) # (!\z80_|execute_|ctl_flags_hf_cpl~10_combout ) + + .dataa(\z80_|execute_|ctl_flags_hf_cpl~10_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~25_combout ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|execute_|ctl_flags_hf_cpl~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_cpl~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_cpl~12 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_flags_hf_cpl~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~13 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_cpl~13_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~q & (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|execute_|ctl_flags_hf_cpl~12_combout & \z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|execute_|ctl_flags_hf_cpl~12_combout ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_cpl~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_cpl~13 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_flags_hf_cpl~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y17_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~8_combout = (\z80_|execute_|ctl_alu_core_S~6_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~4_combout & (\z80_|execute_|ctl_alu_core_S~11_combout & !\z80_|execute_|ctl_alu_core_R~1_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_S~6_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ), + .datac(\z80_|execute_|ctl_alu_core_S~11_combout ), + .datad(\z80_|execute_|ctl_alu_core_R~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~8 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_alu_core_S~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y20_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~9_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout & (\z80_|execute_|ctl_alu_core_S~8_combout & !\z80_|pla_decode_|Equal72~2_combout )) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_core_S~8_combout ), + .datad(\z80_|pla_decode_|Equal72~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~9 .lut_mask = 16'h00A0; +defparam \z80_|execute_|ctl_alu_core_S~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y20_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~10_combout = (((!\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ) # (!\z80_|execute_|ctl_alu_core_S~12_combout )) # (!\z80_|execute_|ctl_alu_core_R~4_combout )) # (!\z80_|execute_|ctl_alu_core_S~5_combout ) + + .dataa(\z80_|execute_|ctl_alu_core_S~5_combout ), + .datab(\z80_|execute_|ctl_alu_core_R~4_combout ), + .datac(\z80_|execute_|ctl_alu_core_S~12_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S~10 .lut_mask = 16'h7FFF; +defparam \z80_|execute_|ctl_alu_core_S~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y20_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_S~combout = ((\z80_|execute_|ctl_alu_core_S~10_combout ) # ((\z80_|pla_decode_|Equal9~0_combout & \z80_|pla_decode_|Equal62~2_combout ))) # (!\z80_|execute_|ctl_alu_core_S~9_combout ) + + .dataa(\z80_|pla_decode_|Equal9~0_combout ), + .datab(\z80_|execute_|ctl_alu_core_S~9_combout ), + .datac(\z80_|execute_|ctl_alu_core_S~10_combout ), + .datad(\z80_|pla_decode_|Equal62~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_S~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_S .lut_mask = 16'hFBF3; +defparam \z80_|execute_|ctl_alu_core_S .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N12 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[3] ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_high|Q [3] = (\z80_|alu_|db_high[3]~7_combout & (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & \z80_|execute_|ctl_alu_op1_sel_bus~15_combout )) + + .dataa(\z80_|alu_|db_high[3]~7_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [3]), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[3] .lut_mask = 16'h0A00; +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[3] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N8 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|ena~0 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ) # (\z80_|execute_|ctl_alu_op1_sel_zero~combout ) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_high|ena~0 .lut_mask = 16'hFAFA; +defparam \z80_|alu_|b2v_op1_latch_mux_high|ena~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y17_N13 +dffeas \z80_|alu_|op1_high[3] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [3]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_high [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_high[3] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_high[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N14 +cycloneive_lcell_comb \z80_|alu_|alu_op1[3]~2 ( +// Equation(s): +// \z80_|alu_|alu_op1[3]~2_combout = (\z80_|execute_|ctl_alu_op_low~41_combout & (((\z80_|alu_|op1_low [3])))) # (!\z80_|execute_|ctl_alu_op_low~41_combout & ((\z80_|execute_|ctl_alu_op_low~29_combout & (\z80_|alu_|op1_high [3])) # +// (!\z80_|execute_|ctl_alu_op_low~29_combout & ((\z80_|alu_|op1_low [3]))))) + + .dataa(\z80_|execute_|ctl_alu_op_low~41_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~29_combout ), + .datac(\z80_|alu_|op1_high [3]), + .datad(\z80_|alu_|op1_low [3]), + .cin(gnd), + .combout(\z80_|alu_|alu_op1[3]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op1[3]~2 .lut_mask = 16'hFB40; +defparam \z80_|alu_|alu_op1[3]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N12 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout = (\z80_|execute_|ctl_alu_core_S~combout ) # ((\z80_|alu_|alu_op1[3]~2_combout & \z80_|alu_|alu_op2[3]~2_combout )) + + .dataa(\z80_|execute_|ctl_alu_core_S~combout ), + .datab(gnd), + .datac(\z80_|alu_|alu_op1[3]~2_combout ), + .datad(\z80_|alu_|alu_op2[3]~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hFAAA; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we_lo~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we_lo~2_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|ir_|opcode [5])) + + .dataa(gnd), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we_lo~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we_lo~2 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_reg_sys_we_lo~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we_lo~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we_lo~3_combout = (\z80_|pla_decode_|Equal9~1_combout ) # ((\z80_|execute_|ctl_reg_sys_we_lo~2_combout ) # ((\z80_|pla_decode_|Equal8~0_combout & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal8~0_combout ), + .datab(\z80_|pla_decode_|Equal9~1_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_we_lo~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we_lo~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we_lo~3 .lut_mask = 16'hFFEC; +defparam \z80_|execute_|ctl_reg_sys_we_lo~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~14 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~14_combout = (((!\z80_|pla_decode_|Equal35~0_combout & !\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|alu_control_|flags_cond_true~q )) # (!\z80_|execute_|ixy_d~6_combout ) + + .dataa(\z80_|pla_decode_|Equal35~0_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|pla_decode_|Equal34~0_combout ), + .datad(\z80_|alu_control_|flags_cond_true~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~14 .lut_mask = 16'h37FF; +defparam \z80_|execute_|ctl_reg_sel_wz~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N8 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_hi~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_hi~0_combout = ((\z80_|execute_|ixy_d~6_combout & ((\z80_|execute_|ctl_reg_sys_we_lo~3_combout ) # (\z80_|pla_decode_|Equal19~0_combout )))) # (!\z80_|execute_|ctl_reg_sel_wz~14_combout ) + + .dataa(\z80_|execute_|ctl_reg_sys_we_lo~3_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~14_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_hi~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_hi~0 .lut_mask = 16'hC8FF; +defparam \z80_|reg_control_|reg_sys_we_hi~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N20 +cycloneive_lcell_comb \z80_|pla_decode_|Equal33~3 ( +// Equation(s): +// \z80_|pla_decode_|Equal33~3_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal33~1_combout & (\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|pla_decode_|Equal33~1_combout ), + .datac(\z80_|decode_state_|use_ixiy~combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal33~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal33~3 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal33~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we~0_combout = (\z80_|execute_|ixy_d~5_combout & ((\z80_|pla_decode_|Equal33~3_combout ) # ((\z80_|pla_decode_|Equal6~1_combout ) # (!\z80_|execute_|pc_inc_hold~26_combout )))) + + .dataa(\z80_|pla_decode_|Equal33~3_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|pla_decode_|Equal6~1_combout ), + .datad(\z80_|execute_|pc_inc_hold~26_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we~0 .lut_mask = 16'hC8CC; +defparam \z80_|execute_|ctl_reg_sys_we~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we~2_combout = (!\z80_|execute_|ctl_reg_sys_we~1_combout & (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|execute_|ctl_mWrite~17_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout ))) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|execute_|ctl_reg_sys_we~1_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datad(\z80_|execute_|ctl_mWrite~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we~2 .lut_mask = 16'h0313; +defparam \z80_|execute_|ctl_reg_sys_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we~3_combout = (\z80_|execute_|ctl_reg_sys_we~0_combout ) # (((\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ) # (!\z80_|execute_|ctl_reg_sys_we~2_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~32_combout )) + + .dataa(\z80_|execute_|ctl_reg_sys_we~0_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~32_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), + .datad(\z80_|execute_|ctl_reg_sys_we~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we~3 .lut_mask = 16'hFBFF; +defparam \z80_|execute_|ctl_reg_sys_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~4_combout = (\z80_|reg_control_|reg_sel_pc~2_combout & (\z80_|execute_|ctl_alu_oe~2_combout & (!\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout & \z80_|execute_|ctl_alu_sel_op2_neg~2_combout ))) + + .dataa(\z80_|reg_control_|reg_sel_pc~2_combout ), + .datab(\z80_|execute_|ctl_alu_oe~2_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~4 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_in_hi~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N4 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_hi ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_hi~combout = (\z80_|reg_control_|reg_sys_we_hi~0_combout ) # ((\z80_|execute_|ctl_reg_sys_we~3_combout ) # (!\z80_|execute_|ctl_reg_in_hi~4_combout )) + + .dataa(\z80_|reg_control_|reg_sys_we_hi~0_combout ), + .datab(\z80_|execute_|ctl_reg_sys_we~3_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_in_hi~4_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_hi~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_hi .lut_mask = 16'hEEFF; +defparam \z80_|reg_control_|reg_sys_we_hi .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~18 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~18_combout = (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # ((\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~18 .lut_mask = 16'hF0B0; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo~17 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo~17_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|execute_|ctl_mRead~12_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|execute_|ctl_mRead~12_combout ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo~17 .lut_mask = 16'h80C0; +defparam \z80_|execute_|ctl_reg_sys_hilo~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~11 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~11_combout = (!\z80_|execute_|ctl_reg_sys_hilo~17_combout & (((!\z80_|execute_|ctl_mRead~34_combout & !\z80_|pla_decode_|Equal10~0_combout )) # (!\z80_|execute_|ctl_mWrite~9_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~9_combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~11 .lut_mask = 16'h0057; +defparam \z80_|execute_|ctl_reg_sel_pc~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~12 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~12_combout = (\z80_|execute_|ctl_reg_sel_pc~11_combout & (((\z80_|execute_|ctl_flags_bus~1_combout & \z80_|execute_|ctl_al_we~13_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ), + .datab(\z80_|execute_|ctl_flags_bus~1_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~11_combout ), + .datad(\z80_|execute_|ctl_al_we~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~12 .lut_mask = 16'hD050; +defparam \z80_|execute_|ctl_reg_sel_pc~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~13 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~13_combout = (\z80_|execute_|setM1~54_combout & (\z80_|execute_|ctl_reg_sel_pc~12_combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|pla_decode_|Equal6~1_combout )))) + + .dataa(\z80_|execute_|setM1~54_combout ), + .datab(\z80_|pla_decode_|Equal6~1_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~12_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~13 .lut_mask = 16'h20A0; +defparam \z80_|execute_|ctl_reg_sel_pc~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout = (\z80_|execute_|ixy_d~6_combout & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|execute_|comb~0_combout & \z80_|ir_|opcode [0]))) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|pla_decode_|Equal52~0_combout ), + .datac(\z80_|execute_|comb~0_combout ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~6_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & (((!\z80_|execute_|ctl_mRead~8_combout & !\z80_|execute_|ctl_mRead~6_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~8_combout ), + .datab(\z80_|execute_|ctl_mRead~6_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~6 .lut_mask = 16'h010F; +defparam \z80_|execute_|ctl_reg_sel_wz~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~7_combout = (\z80_|execute_|ctl_reg_sel_wz~6_combout & (((!\z80_|pla_decode_|Equal34~0_combout & !\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|execute_|ctl_reg_in_hi~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal34~0_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~7 .lut_mask = 16'h3700; +defparam \z80_|execute_|ctl_reg_sel_wz~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~9_combout = (\z80_|execute_|ctl_bus_db_oe~0_combout & (\z80_|execute_|ctl_reg_in_hi~3_combout & (\z80_|execute_|ctl_reg_sel_wz~7_combout & \z80_|execute_|ctl_reg_in_hi~4_combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_oe~0_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~3_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~7_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~9 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sel_wz~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~25 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~25_combout = (!\z80_|pla_decode_|Equal35~0_combout & (!\z80_|pla_decode_|Equal24~1_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~11_combout & !\z80_|pla_decode_|Equal19~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal35~0_combout ), + .datab(\z80_|pla_decode_|Equal24~1_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~11_combout ), + .datad(\z80_|pla_decode_|Equal19~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~25 .lut_mask = 16'h0010; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~8_combout = (!\z80_|execute_|ctl_mRead~15_combout & ((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~15_combout ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal12~1_combout ), + .datad(\z80_|pla_decode_|Equal25~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~8 .lut_mask = 16'h5055; +defparam \z80_|execute_|ctl_reg_sel_wz~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~5_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout & (!\z80_|pla_decode_|Equal34~0_combout & (\z80_|execute_|ctl_reg_sel_wz~8_combout & !\z80_|execute_|ctl_mRead~7_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ), + .datab(\z80_|pla_decode_|Equal34~0_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~8_combout ), + .datad(\z80_|execute_|ctl_mRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~5 .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_al_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~4_combout = (!\z80_|execute_|ctl_mRead~2_combout & (!\z80_|execute_|ixy_d~10_combout & (!\z80_|execute_|ixy_d~16_combout & !\z80_|execute_|ctl_mRead~3_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~2_combout ), + .datab(\z80_|execute_|ixy_d~10_combout ), + .datac(\z80_|execute_|ixy_d~16_combout ), + .datad(\z80_|execute_|ctl_mRead~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~4 .lut_mask = 16'h0001; +defparam \z80_|execute_|ctl_al_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~41 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~41_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ctl_al_we~4_combout )))) + + .dataa(\z80_|pla_decode_|Equal34~0_combout ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|execute_|ctl_al_we~4_combout ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~41 .lut_mask = 16'h008C; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~10 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~10_combout = (!\z80_|execute_|ctl_ir_we~8_combout & (!\z80_|execute_|ctl_mRead~13_combout & !\z80_|execute_|ctl_ir_we~14_combout )) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_mRead~13_combout ), + .datad(\z80_|execute_|ctl_ir_we~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~10 .lut_mask = 16'h0005; +defparam \z80_|execute_|ctl_reg_sel_wz~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo~21 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo~21_combout = (\z80_|ir_|opcode [5]) # ((!\z80_|pla_decode_|Equal6~0_combout ) # (!\z80_|pla_decode_|Equal55~0_combout )) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo~21 .lut_mask = 16'hBBFF; +defparam \z80_|execute_|ctl_reg_sys_hilo~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~3 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~3_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~3 .lut_mask = 16'h7755; +defparam \z80_|execute_|ctl_inc_dec~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~22 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~22_combout = (\z80_|execute_|ctl_reg_sys_hilo~21_combout & (((\z80_|execute_|ctl_inc_dec~3_combout ) # (!\z80_|pla_decode_|Equal33~3_combout )))) # (!\z80_|execute_|ctl_reg_sys_hilo~21_combout & +// (!\z80_|execute_|ctl_alu_op_low~22_combout & ((\z80_|execute_|ctl_inc_dec~3_combout ) # (!\z80_|pla_decode_|Equal33~3_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo~21_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datac(\z80_|pla_decode_|Equal33~3_combout ), + .datad(\z80_|execute_|ctl_inc_dec~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~22 .lut_mask = 16'hBB0B; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~23 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~23_combout = (!\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout & ((\z80_|execute_|ctl_reg_sel_wz~10_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout +// )))) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~10_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~23 .lut_mask = 16'h2300; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~24 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~24_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout & (((!\z80_|pla_decode_|Equal6~1_combout & \z80_|execute_|pc_inc_hold~26_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) + + .dataa(\z80_|pla_decode_|Equal6~1_combout ), + .datab(\z80_|execute_|pc_inc_hold~26_combout ), + .datac(\z80_|execute_|ixy_d~5_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~24 .lut_mask = 16'h4F00; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~19 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~19_combout = (!\z80_|execute_|ctl_reg_sel_wz~8_combout & ((\z80_|execute_|ctl_state_alu~3_combout ) # ((\z80_|execute_|ctl_alu_oe~0_combout ) # (\z80_|execute_|ctl_ir_we~4_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~3_combout ), + .datab(\z80_|execute_|ctl_alu_oe~0_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~19 .lut_mask = 16'h00FE; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N28 +cycloneive_lcell_comb \z80_|execute_|fMRead~2 ( +// Equation(s): +// \z80_|execute_|fMRead~2_combout = ((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~2 .lut_mask = 16'h0AFF; +defparam \z80_|execute_|fMRead~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~20 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~20_combout = (!\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout & ((\z80_|execute_|fMRead~2_combout ) # ((\z80_|execute_|pc_inc_hold~6_combout & !\z80_|execute_|ctl_mRead~7_combout )))) + + .dataa(\z80_|execute_|pc_inc_hold~6_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ), + .datac(\z80_|execute_|ctl_mRead~7_combout ), + .datad(\z80_|execute_|fMRead~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~20 .lut_mask = 16'h3302; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~26 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~26_combout = (!\z80_|pla_decode_|Equal52~1_combout & (!\z80_|pla_decode_|Equal6~1_combout & \z80_|execute_|ctl_bus_db_oe~1_combout )) + + .dataa(\z80_|pla_decode_|Equal52~1_combout ), + .datab(\z80_|pla_decode_|Equal6~1_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~26 .lut_mask = 16'h1100; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~27 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~27_combout = (!\z80_|execute_|fMRead~2_combout & ((!\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ), + .datab(\z80_|execute_|fMRead~2_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~27 .lut_mask = 16'h1133; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~28 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~28_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~20_combout & (!\z80_|execute_|ctl_reg_sys_hilo[1]~27_combout & \z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~20_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~28 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~29 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~29_combout = (!\z80_|execute_|ctl_reg_sys_hilo[1]~41_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout & ((\z80_|execute_|ctl_al_we~5_combout ) # (!\z80_|execute_|ixy_d~7_combout )))) + + .dataa(\z80_|execute_|ctl_al_we~5_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~41_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~29 .lut_mask = 16'h2300; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~30 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~30_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~16_combout & (\z80_|execute_|ctl_reg_sel_pc~13_combout & (\z80_|execute_|ctl_reg_sel_wz~9_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~29_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~16_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~13_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~9_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~29_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~30 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~13 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~13_combout = (\z80_|pla_decode_|Equal9~1_combout & (!\z80_|execute_|ixy_d~6_combout & ((!\z80_|execute_|ctl_reg_in_hi~2_combout )))) # (!\z80_|pla_decode_|Equal9~1_combout & (((!\z80_|pla_decode_|Equal19~0_combout )) # +// (!\z80_|execute_|ixy_d~6_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~13 .lut_mask = 16'h1537; +defparam \z80_|execute_|ctl_reg_sel_wz~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~32 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~32_combout = ((\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ) # ((\z80_|pla_decode_|Equal35~0_combout & \z80_|execute_|ixy_d~6_combout ))) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ) + + .dataa(\z80_|pla_decode_|Equal35~0_combout ), + .datab(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~32 .lut_mask = 16'hFFB3; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y19_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~33 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~33_combout = (!\z80_|ir_|opcode [3] & ((\z80_|execute_|ctl_alu_op_low~28_combout ) # ((\z80_|pla_decode_|Equal48~0_combout & \z80_|execute_|ctl_eval_cond~0_combout )))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|execute_|ctl_alu_op_low~28_combout ), + .datac(\z80_|pla_decode_|Equal48~0_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~33 .lut_mask = 16'h5444; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y19_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~34 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~34_combout = (((\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ) # (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout )) # (!\z80_|execute_|ctl_reg_out_hi~4_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~37_combout ) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~37_combout ), + .datab(\z80_|execute_|ctl_reg_out_hi~4_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~34 .lut_mask = 16'hFFF7; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~35 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~35_combout = (((\z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~13_combout )) # (!\z80_|execute_|ctl_reg_in_hi~5_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~5_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~13_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~35 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N22 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_73 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_73~combout = (\z80_|reg_control_|reg_sel_pc~combout & (\z80_|reg_control_|reg_sys_we_hi~combout & \z80_|execute_|ctl_reg_sys_hilo[1]~35_combout )) + + .dataa(\z80_|reg_control_|reg_sel_pc~combout ), + .datab(gnd), + .datac(\z80_|reg_control_|reg_sys_we_hi~combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_73 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_73 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y14_N5 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[3]~12_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_ir~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_ir~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_ir~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_ir~0 .lut_mask = 16'h0F0C; +defparam \z80_|execute_|ctl_reg_sel_ir~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_ir~1 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_ir~1_combout = (\z80_|execute_|ctl_reg_sel_ir~0_combout ) # (((\z80_|execute_|ctl_eval_cond~0_combout & !\z80_|execute_|ctl_flags_bus~0_combout )) # (!\z80_|execute_|ctl_reg_in_lo~9_combout )) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|ctl_flags_bus~0_combout ), + .datac(\z80_|execute_|ctl_reg_sel_ir~0_combout ), + .datad(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_ir~1 .lut_mask = 16'hF2FF; +defparam \z80_|execute_|ctl_reg_sel_ir~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N16 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_60 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_60~combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout & (!\z80_|reg_control_|reg_sys_we_hi~combout & \z80_|execute_|ctl_reg_sel_ir~1_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), + .datac(\z80_|reg_control_|reg_sys_we_hi~combout ), + .datad(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_60 .lut_mask = 16'h0C00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_60 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N20 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_61 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_61~combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout & (\z80_|reg_control_|reg_sys_we_hi~combout & \z80_|execute_|ctl_reg_sel_ir~1_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), + .datac(\z80_|reg_control_|reg_sys_we_hi~combout ), + .datad(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_61 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_61 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y14_N15 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[3]~12_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we_lo~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_we_lo~4_combout = (\z80_|execute_|ctl_reg_sys_we_lo~3_combout & (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_M2_ff~q )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_sys_we_lo~3_combout ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_we_lo~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_we_lo~4 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_reg_sys_we_lo~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N22 +cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo ( +// Equation(s): +// \z80_|reg_control_|reg_sys_we_lo~combout = ((\z80_|execute_|ctl_reg_sys_we_lo~4_combout ) # ((\z80_|execute_|ctl_reg_sys_we~3_combout ) # (!\z80_|reg_control_|reg_sys_we_lo~4_combout ))) # (!\z80_|reg_control_|reg_sys_we_lo~7_combout ) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~7_combout ), + .datab(\z80_|execute_|ctl_reg_sys_we_lo~4_combout ), + .datac(\z80_|reg_control_|reg_sys_we_lo~4_combout ), + .datad(\z80_|execute_|ctl_reg_sys_we~3_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sys_we_lo~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sys_we_lo .lut_mask = 16'hFFDF; +defparam \z80_|reg_control_|reg_sys_we_lo .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N2 +cycloneive_lcell_comb \z80_|reg_control_|reg_sw_4d_hi~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sw_4d_hi~0_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_control_|reg_sys_we_lo~combout ) # (!\z80_|execute_|ctl_reg_sel_ir~1_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ))) + + .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), + .datac(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datad(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sw_4d_hi~0 .lut_mask = 16'hA2AA; +defparam \z80_|reg_control_|reg_sw_4d_hi~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N14 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~10 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[3]~10_combout = (\z80_|reg_file_|gdfx_temp1[3]~48_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) # (!\z80_|reg_file_|gdfx_temp1[3]~48_combout & +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [3]), + .datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[3]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[3]~10 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|db_hi_as[3]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N26 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~11 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[3]~11_combout = (\z80_|reg_file_|db_hi_as[3]~10_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [3]), + .datad(\z80_|reg_file_|db_hi_as[3]~10_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[3]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[3]~11 .lut_mask = 16'hF300; +defparam \z80_|reg_file_|db_hi_as[3]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N14 +cycloneive_lcell_comb \z80_|address_latch_|abusz[11] ( +// Equation(s): +// \z80_|address_latch_|abusz [11] = (\z80_|reg_file_|db_hi_as[3]~12_combout & !\z80_|resets_|clrpc~0_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[3]~12_combout ), + .datab(gnd), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [11]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[11] .lut_mask = 16'h0A0A; +defparam \z80_|address_latch_|abusz[11] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~1 ( +// Equation(s): +// \z80_|execute_|ctl_apin_mux~1_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (\z80_|sequencer_|DFFE_M2_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_apin_mux~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_apin_mux~1 .lut_mask = 16'h3232; +defparam \z80_|execute_|ctl_apin_mux~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~37 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~37_combout = (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|pla_decode_|Equal47~0_combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|pla_decode_|Equal34~0_combout )))) # (!\z80_|execute_|ctl_state_alu~2_combout +// & (((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|pla_decode_|Equal34~0_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|pla_decode_|Equal47~0_combout ), + .datac(\z80_|pla_decode_|Equal34~0_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~37 .lut_mask = 16'h0777; +defparam \z80_|execute_|ctl_inc_cy~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~2 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~2_combout = (\z80_|execute_|ctl_inc_cy~37_combout & (((!\z80_|pla_decode_|Equal9~1_combout & !\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|execute_|ctl_inc_cy~37_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~2 .lut_mask = 16'h3700; +defparam \z80_|execute_|ctl_inc_dec~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~40 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~40_combout = (\z80_|pla_decode_|Equal34~0_combout & (!\z80_|execute_|ixy_d~9_combout & ((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) # (!\z80_|pla_decode_|Equal34~0_combout & +// (((!\z80_|execute_|ctl_mRead~9_combout )) # (!\z80_|pla_decode_|Equal47~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal34~0_combout ), + .datab(\z80_|pla_decode_|Equal47~0_combout ), + .datac(\z80_|execute_|ctl_mRead~9_combout ), + .datad(\z80_|execute_|ixy_d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~40 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_inc_cy~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~4 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~4_combout = (\z80_|execute_|ctl_inc_cy~40_combout & (((!\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|sequencer_|DFFE_M3_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|execute_|ctl_inc_cy~40_combout ), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~4 .lut_mask = 16'h4CCC; +defparam \z80_|execute_|ctl_inc_dec~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~5 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~5_combout = (\z80_|execute_|ctl_inc_dec~2_combout & (\z80_|execute_|ctl_inc_dec~4_combout & ((!\z80_|execute_|ixy_d~9_combout ) # (!\z80_|pla_decode_|Equal9~1_combout )))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ctl_inc_dec~2_combout ), + .datac(\z80_|execute_|ctl_inc_dec~4_combout ), + .datad(\z80_|execute_|ixy_d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~5 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_inc_dec~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~4_combout = (\z80_|execute_|ctl_inc_dec~5_combout & (((!\z80_|execute_|ctl_state_alu~2_combout & !\z80_|execute_|ctl_mRead~9_combout )) # (!\z80_|execute_|ctl_mWrite~6_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datac(\z80_|execute_|ctl_inc_dec~5_combout ), + .datad(\z80_|execute_|ctl_mRead~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~4 .lut_mask = 16'h3070; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal2~1_combout & (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [1]))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|pla_decode_|Equal2~1_combout ), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 .lut_mask = 16'h0008; +defparam \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|setM1~42 ( +// Equation(s): +// \z80_|execute_|setM1~42_combout = (!\z80_|pla_decode_|Equal4~0_combout & ((!\z80_|pla_decode_|Equal8~0_combout ) # (!\z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal6~0_combout ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal4~0_combout ), + .datad(\z80_|pla_decode_|Equal8~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~42 .lut_mask = 16'h050F; +defparam \z80_|execute_|setM1~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~12 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~12_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout & (!\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout & ((\z80_|execute_|setM1~42_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ), + .datab(\z80_|execute_|setM1~42_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~12 .lut_mask = 16'h0405; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~4 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~4_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|execute_|ctl_mRead~2_combout & ((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|ctl_mRead~3_combout )))) # (!\z80_|execute_|ixy_d~7_combout & +// (((!\z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|execute_|ctl_mRead~3_combout ))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ctl_mRead~3_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_mRead~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~4 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_sw_1d~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~3 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~3_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~4_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~12_combout & \z80_|execute_|ctl_sw_1d~4_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~12_combout ), + .datad(\z80_|execute_|ctl_sw_1d~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~3 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_sw_4d~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N8 +cycloneive_lcell_comb \z80_|execute_|fMRead~9 ( +// Equation(s): +// \z80_|execute_|fMRead~9_combout = (\z80_|execute_|ctl_mRead~14_combout & (((!\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ctl_state_alu~3_combout )))) # (!\z80_|execute_|ctl_mRead~14_combout & (((!\z80_|execute_|ixy_d~7_combout & +// !\z80_|execute_|ctl_state_alu~3_combout )) # (!\z80_|pla_decode_|Equal37~0_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~14_combout ), + .datab(\z80_|pla_decode_|Equal37~0_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ctl_state_alu~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~9 .lut_mask = 16'h111F; +defparam \z80_|execute_|fMRead~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N2 +cycloneive_lcell_comb \z80_|execute_|fMRead~10 ( +// Equation(s): +// \z80_|execute_|fMRead~10_combout = (\z80_|execute_|fMRead~9_combout & (((!\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ctl_state_alu~3_combout )) # (!\z80_|pla_decode_|Equal38~2_combout ))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|fMRead~9_combout ), + .datac(\z80_|pla_decode_|Equal38~2_combout ), + .datad(\z80_|execute_|ctl_state_alu~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~10 .lut_mask = 16'h0C4C; +defparam \z80_|execute_|fMRead~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|fMRead~8 ( +// Equation(s): +// \z80_|execute_|fMRead~8_combout = (\z80_|pla_decode_|Equal9~1_combout & (!\z80_|execute_|ctl_state_alu~3_combout & (!\z80_|execute_|ixy_d~7_combout ))) # (!\z80_|pla_decode_|Equal9~1_combout & (((!\z80_|execute_|ctl_state_alu~3_combout & +// !\z80_|execute_|ixy_d~7_combout )) # (!\z80_|pla_decode_|Equal29~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ctl_state_alu~3_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|pla_decode_|Equal29~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~8 .lut_mask = 16'h0357; +defparam \z80_|execute_|fMRead~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~2 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~2_combout = (\z80_|execute_|fMRead~10_combout & (\z80_|execute_|fMRead~8_combout & \z80_|execute_|ctl_reg_in_lo~9_combout )) + + .dataa(\z80_|execute_|fMRead~10_combout ), + .datab(\z80_|execute_|fMRead~8_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~2 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_sw_4d~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~11 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~11_combout = (\z80_|execute_|ctl_reg_sel_wz~8_combout & (((\z80_|execute_|ctl_reg_sel_wz~10_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|execute_|ctl_reg_sel_wz~8_combout & +// (!\z80_|execute_|ctl_alu_oe~0_combout & (!\z80_|execute_|ctl_ir_we~4_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~8_combout ), + .datab(\z80_|execute_|ctl_alu_oe~0_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~11 .lut_mask = 16'hAB0B; +defparam \z80_|execute_|ctl_reg_sel_wz~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~12 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~12_combout = (\z80_|execute_|ctl_reg_sel_wz~9_combout & \z80_|execute_|ctl_reg_sel_wz~11_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_sel_wz~9_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~12 .lut_mask = 16'hF000; +defparam \z80_|execute_|ctl_reg_sel_wz~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~4 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~4_combout = (\z80_|pla_decode_|Equal9~1_combout & (!\z80_|execute_|ctl_reg_in_hi~2_combout & ((\z80_|execute_|ctl_flags_bus~1_combout ) # (!\z80_|execute_|ixy_d~6_combout )))) # (!\z80_|pla_decode_|Equal9~1_combout & +// (((\z80_|execute_|ctl_flags_bus~1_combout )) # (!\z80_|execute_|ixy_d~6_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|execute_|ctl_flags_bus~1_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~4 .lut_mask = 16'h51F3; +defparam \z80_|execute_|ctl_sw_4d~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~5 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~5_combout = (\z80_|execute_|ctl_sw_4d~3_combout & (\z80_|execute_|ctl_sw_4d~2_combout & (\z80_|execute_|ctl_reg_sel_wz~12_combout & \z80_|execute_|ctl_sw_4d~4_combout ))) + + .dataa(\z80_|execute_|ctl_sw_4d~3_combout ), + .datab(\z80_|execute_|ctl_sw_4d~2_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~12_combout ), + .datad(\z80_|execute_|ctl_sw_4d~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~5 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_sw_4d~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~14 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~14_combout = (!\z80_|execute_|ctl_mRead~5_combout & ((\z80_|ir_|opcode [2]) # ((!\z80_|ir_|opcode [1]) # (!\z80_|execute_|ctl_mWrite~4_combout )))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|execute_|ctl_mWrite~4_combout ), + .datac(\z80_|execute_|ctl_mRead~5_combout ), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~14 .lut_mask = 16'h0B0F; +defparam \z80_|execute_|ctl_al_we~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~10 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~10_combout = ((\z80_|pla_decode_|Equal33~3_combout ) # (!\z80_|execute_|ctl_al_we~5_combout )) # (!\z80_|execute_|ctl_al_we~14_combout ) + + .dataa(\z80_|execute_|ctl_al_we~14_combout ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal33~3_combout ), + .datad(\z80_|execute_|ctl_al_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~10 .lut_mask = 16'hF5FF; +defparam \z80_|execute_|ctl_al_we~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~6_combout = (\z80_|execute_|ctl_ir_we~4_combout & (((!\z80_|execute_|ctl_al_we~13_combout )) # (!\z80_|execute_|ctl_flags_bus~1_combout ))) # (!\z80_|execute_|ctl_ir_we~4_combout & (\z80_|execute_|ctl_state_alu~4_combout & +// ((!\z80_|execute_|ctl_al_we~13_combout ) # (!\z80_|execute_|ctl_flags_bus~1_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|execute_|ctl_flags_bus~1_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|ctl_al_we~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~6 .lut_mask = 16'h32FA; +defparam \z80_|execute_|ctl_al_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~7_combout = ((\z80_|execute_|ctl_al_we~6_combout ) # ((\z80_|pla_decode_|Equal35~0_combout & \z80_|execute_|ixy_d~6_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|execute_|ctl_al_we~6_combout ), + .datac(\z80_|pla_decode_|Equal35~0_combout ), + .datad(\z80_|execute_|ixy_d~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~7 .lut_mask = 16'hFDDD; +defparam \z80_|execute_|ctl_al_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~8_combout = (((!\z80_|execute_|ctl_al_we~4_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~31_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout )) # (!\z80_|execute_|ctl_alu_oe~3_combout ) + + .dataa(\z80_|execute_|ctl_alu_oe~3_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~31_combout ), + .datad(\z80_|execute_|ctl_al_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~8 .lut_mask = 16'h7FFF; +defparam \z80_|execute_|ctl_al_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~9 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~9_combout = (\z80_|execute_|ctl_al_we~7_combout ) # ((\z80_|execute_|ctl_state_alu~3_combout & ((\z80_|execute_|ctl_al_we~8_combout ) # (!\z80_|execute_|setM1~47_combout )))) + + .dataa(\z80_|execute_|ctl_al_we~7_combout ), + .datab(\z80_|execute_|ctl_state_alu~3_combout ), + .datac(\z80_|execute_|setM1~47_combout ), + .datad(\z80_|execute_|ctl_al_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~9 .lut_mask = 16'hEEAE; +defparam \z80_|execute_|ctl_al_we~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~11 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~11_combout = ((\z80_|execute_|ctl_al_we~9_combout ) # ((\z80_|execute_|ctl_apin_mux~1_combout & \z80_|execute_|ctl_al_we~10_combout ))) # (!\z80_|execute_|ctl_sw_4d~5_combout ) + + .dataa(\z80_|execute_|ctl_apin_mux~1_combout ), + .datab(\z80_|execute_|ctl_sw_4d~5_combout ), + .datac(\z80_|execute_|ctl_al_we~10_combout ), + .datad(\z80_|execute_|ctl_al_we~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~11 .lut_mask = 16'hFFB3; +defparam \z80_|execute_|ctl_al_we~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_al_we~12 ( +// Equation(s): +// \z80_|execute_|ctl_al_we~12_combout = ((\z80_|execute_|ctl_al_we~11_combout ) # ((\z80_|pla_decode_|Equal6~1_combout & \z80_|execute_|ixy_d~7_combout ))) # (!\z80_|execute_|setM1~54_combout ) + + .dataa(\z80_|execute_|setM1~54_combout ), + .datab(\z80_|pla_decode_|Equal6~1_combout ), + .datac(\z80_|execute_|ctl_al_we~11_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_al_we~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_al_we~12 .lut_mask = 16'hFDF5; +defparam \z80_|execute_|ctl_al_we~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y13_N15 +dffeas \z80_|address_latch_|Q[11] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [11]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [11]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[11] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N24 +cycloneive_lcell_comb \z80_|execute_|fIOWrite~0 ( +// Equation(s): +// \z80_|execute_|fIOWrite~0_combout = ((\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q ))) # (!\z80_|sequencer_|DFFE_M2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|fIOWrite~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIOWrite~0 .lut_mask = 16'h0F2F; +defparam \z80_|execute_|fIOWrite~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~8 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~8_combout = (\z80_|execute_|ctl_mWrite~6_combout & ((\z80_|execute_|ctl_mRead~9_combout ) # ((!\z80_|execute_|ctl_inc_dec~3_combout ) # (!\z80_|execute_|fIOWrite~0_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~9_combout ), + .datab(\z80_|execute_|fIOWrite~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~6_combout ), + .datad(\z80_|execute_|ctl_inc_dec~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~8 .lut_mask = 16'hB0F0; +defparam \z80_|execute_|ctl_inc_dec~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y18_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~2_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~5_combout & (\z80_|execute_|ctl_bus_inc_oe~45_combout & ((!\z80_|execute_|ctl_mWrite~17_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~45_combout ), + .datad(\z80_|execute_|ctl_mWrite~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~2 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_reg_gp_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~9 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~9_combout = ((\z80_|execute_|ctl_inc_dec~8_combout ) # ((!\z80_|execute_|ctl_reg_gp_we~2_combout & \z80_|ir_|opcode [3]))) # (!\z80_|execute_|ctl_inc_dec~12_combout ) + + .dataa(\z80_|execute_|ctl_inc_dec~12_combout ), + .datab(\z80_|execute_|ctl_inc_dec~8_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~2_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~9 .lut_mask = 16'hDFDD; +defparam \z80_|execute_|ctl_inc_dec~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N22 +cycloneive_lcell_comb \z80_|address_latch_|abusz[1] ( +// Equation(s): +// \z80_|address_latch_|abusz [1] = (\z80_|reg_file_|db_lo_as[1]~6_combout & !\z80_|resets_|clrpc~0_combout ) + + .dataa(\z80_|reg_file_|db_lo_as[1]~6_combout ), + .datab(gnd), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [1]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[1] .lut_mask = 16'h0A0A; +defparam \z80_|address_latch_|abusz[1] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y11_N23 +dffeas \z80_|address_latch_|Q[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [1]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[1] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~0 ( +// Equation(s): +// \z80_|execute_|ctl_apin_mux~0_combout = (\z80_|execute_|ctl_inc_cy~32_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~37_combout & ((!\z80_|pla_decode_|Equal19~0_combout ) # (!\z80_|execute_|ctl_alu_oe~0_combout )))) + + .dataa(\z80_|execute_|ctl_inc_cy~32_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~37_combout ), + .datac(\z80_|execute_|ctl_alu_oe~0_combout ), + .datad(\z80_|pla_decode_|Equal19~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_apin_mux~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_apin_mux~0 .lut_mask = 16'h0888; +defparam \z80_|execute_|ctl_apin_mux~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~6 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~6_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout & (\z80_|execute_|ctl_apin_mux~0_combout & ((!\z80_|pla_decode_|Equal9~1_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|pla_decode_|Equal9~1_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), + .datad(\z80_|execute_|ctl_apin_mux~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~6 .lut_mask = 16'h0700; +defparam \z80_|execute_|ctl_inc_dec~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~7 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~7_combout = (!\z80_|execute_|ctl_bus_inc_oe~42_combout ) # (!\z80_|execute_|ctl_inc_dec~5_combout ) + + .dataa(\z80_|execute_|ctl_inc_dec~5_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_bus_inc_oe~42_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~7 .lut_mask = 16'h5F5F; +defparam \z80_|execute_|ctl_inc_dec~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N6 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout = \z80_|address_latch_|Q [1] $ (((\z80_|execute_|ctl_inc_dec~9_combout ) # ((\z80_|execute_|ctl_inc_dec~7_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout )))) + + .dataa(\z80_|execute_|ctl_inc_dec~9_combout ), + .datab(\z80_|address_latch_|Q [1]), + .datac(\z80_|execute_|ctl_inc_dec~6_combout ), + .datad(\z80_|execute_|ctl_inc_dec~7_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0 .lut_mask = 16'h3363; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~21 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~21_combout = (\z80_|reg_control_|reg_sys_we_lo~6_combout & (\z80_|execute_|ctl_mRead~20_combout & ((!\z80_|execute_|ixy_d~15_combout ) # (!\z80_|sequencer_|DFFE_T3_ff~q )))) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~6_combout ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|execute_|ixy_d~15_combout ), + .datad(\z80_|execute_|ctl_mRead~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~21 .lut_mask = 16'h2A00; +defparam \z80_|execute_|ctl_reg_sel_wz~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~40 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[0]~40_combout = (\z80_|execute_|ctl_reg_sel_wz~20_combout ) # ((\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|M5~q & \z80_|pla_decode_|Equal9~1_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|M5~q ), + .datac(\z80_|execute_|ctl_reg_sel_wz~20_combout ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~40 .lut_mask = 16'hF8F0; +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y19_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~39 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~39_combout = (\z80_|execute_|ctl_alu_op_low~28_combout ) # ((\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|pla_decode_|Equal48~0_combout & !\z80_|sequencer_|DFFE_M1_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|execute_|ctl_alu_op_low~28_combout ), + .datac(\z80_|pla_decode_|Equal48~0_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~39 .lut_mask = 16'hCCEC; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y19_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~13 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[0]~13_combout = (((\z80_|execute_|ctl_reg_sys_hilo[1]~39_combout & \z80_|ir_|opcode [3])) # (!\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout )) # (!\z80_|execute_|ctl_reg_out_lo~9_combout ) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~39_combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~9_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~13 .lut_mask = 16'hBF3F; +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~31 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[0]~31_combout = (((\z80_|execute_|ctl_reg_sys_hilo[0]~40_combout ) # (\z80_|execute_|ctl_reg_sys_hilo[0]~13_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~21_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~21_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[0]~40_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[0]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~31 .lut_mask = 16'hFFF7; +defparam \z80_|execute_|ctl_reg_sys_hilo[0]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N12 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_63 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_63~combout = (\z80_|execute_|ctl_reg_sys_hilo[0]~31_combout & (\z80_|reg_control_|reg_sys_we_lo~combout & \z80_|execute_|ctl_reg_sel_ir~1_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~31_combout ), + .datac(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datad(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_63 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y12_N9 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[2]~9_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|setM1~49 ( +// Equation(s): +// \z80_|execute_|setM1~49_combout = (!\z80_|execute_|ctl_ir_we~11_combout & (!\z80_|pla_decode_|Equal69~0_combout & ((!\z80_|pla_decode_|Equal63~0_combout ) # (!\z80_|pla_decode_|Equal21~0_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~11_combout ), + .datab(\z80_|pla_decode_|Equal21~0_combout ), + .datac(\z80_|pla_decode_|Equal69~0_combout ), + .datad(\z80_|pla_decode_|Equal63~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~49_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~49 .lut_mask = 16'h0105; +defparam \z80_|execute_|setM1~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_sel_shift~2_combout = (!\z80_|pla_decode_|Equal20~0_combout & !\z80_|execute_|ctl_ir_we~8_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal20~0_combout ), + .datad(\z80_|execute_|ctl_ir_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~2 .lut_mask = 16'h000F; +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|setM1~50 ( +// Equation(s): +// \z80_|execute_|setM1~50_combout = (\z80_|execute_|ctl_flags_hf_cpl~10_combout & (\z80_|execute_|nextM~2_combout & (\z80_|execute_|setM1~49_combout & \z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ))) + + .dataa(\z80_|execute_|ctl_flags_hf_cpl~10_combout ), + .datab(\z80_|execute_|nextM~2_combout ), + .datac(\z80_|execute_|setM1~49_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~50_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~50 .lut_mask = 16'h8000; +defparam \z80_|execute_|setM1~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_flags_oe~0_combout = (!\z80_|execute_|ctl_iorw~11_combout & (!\z80_|execute_|ctl_mRead~4_combout & (!\z80_|execute_|ctl_ir_we~14_combout & !\z80_|execute_|ctl_ir_we~12_combout ))) + + .dataa(\z80_|execute_|ctl_iorw~11_combout ), + .datab(\z80_|execute_|ctl_mRead~4_combout ), + .datac(\z80_|execute_|ctl_ir_we~14_combout ), + .datad(\z80_|execute_|ctl_ir_we~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_oe~0 .lut_mask = 16'h0001; +defparam \z80_|execute_|ctl_flags_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~1 ( +// Equation(s): +// \z80_|execute_|ctl_flags_oe~1_combout = (\z80_|execute_|ctl_al_we~13_combout & (\z80_|execute_|ctl_flags_bus~1_combout & (\z80_|execute_|ctl_flags_oe~0_combout & !\z80_|pla_decode_|Equal13~2_combout ))) + + .dataa(\z80_|execute_|ctl_al_we~13_combout ), + .datab(\z80_|execute_|ctl_flags_bus~1_combout ), + .datac(\z80_|execute_|ctl_flags_oe~0_combout ), + .datad(\z80_|pla_decode_|Equal13~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_oe~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_oe~1 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_flags_oe~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~13 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~13_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & ((!\z80_|execute_|ctl_flags_oe~1_combout ) # (!\z80_|execute_|setM1~50_combout )))) + + .dataa(\z80_|execute_|setM1~50_combout ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|execute_|ctl_flags_oe~1_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~13 .lut_mask = 16'h004C; +defparam \z80_|execute_|ctl_reg_in_hi~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~12 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~12_combout = (!\z80_|execute_|ctl_mRead~12_combout & (!\z80_|execute_|ctl_alu_oe~1_combout & !\z80_|pla_decode_|Equal49~0_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_mRead~12_combout ), + .datac(\z80_|execute_|ctl_alu_oe~1_combout ), + .datad(\z80_|pla_decode_|Equal49~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~12 .lut_mask = 16'h0003; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~7_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal69~0_combout ) # ((!\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ) # (!\z80_|execute_|ctl_sw_1d~8_combout )))) + + .dataa(\z80_|pla_decode_|Equal69~0_combout ), + .datab(\z80_|execute_|ctl_sw_1d~8_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~7 .lut_mask = 16'hBF00; +defparam \z80_|execute_|ctl_reg_in_hi~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~13 ( +// Equation(s): +// \z80_|execute_|ctl_state_alu~13_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|execute_|ctl_state_alu~6_combout & !\z80_|pla_decode_|Equal52~1_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|pla_decode_|Equal52~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_alu~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_alu~13 .lut_mask = 16'hBBBF; +defparam \z80_|execute_|ctl_state_alu~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~6_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout & (!\z80_|execute_|ctl_reg_in_hi~13_combout & (!\z80_|execute_|ctl_reg_in_hi~7_combout & \z80_|execute_|ctl_state_alu~13_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~13_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~7_combout ), + .datad(\z80_|execute_|ctl_state_alu~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~6 .lut_mask = 16'h0100; +defparam \z80_|execute_|ctl_reg_gp_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~5_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout & (((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|pla_decode_|Equal12~1_combout ), + .datad(\z80_|pla_decode_|Equal25~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~5 .lut_mask = 16'h5155; +defparam \z80_|execute_|ctl_reg_gp_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~17 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~17_combout = ((!\z80_|execute_|ctl_mRead~2_combout & ((!\z80_|pla_decode_|Equal32~0_combout ) # (!\z80_|pla_decode_|Equal63~0_combout )))) # (!\z80_|nM1_int~2_combout ) + + .dataa(\z80_|pla_decode_|Equal63~0_combout ), + .datab(\z80_|execute_|ctl_mRead~2_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal32~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~17 .lut_mask = 16'h1F3F; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y20_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~18 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~17_combout & (\z80_|execute_|ctl_pf_sel[0]~3_combout & (\z80_|execute_|ctl_flags_pf_we~4_combout & \z80_|execute_|ctl_alu_oe~6_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~17_combout ), + .datab(\z80_|execute_|ctl_pf_sel[0]~3_combout ), + .datac(\z80_|execute_|ctl_flags_pf_we~4_combout ), + .datad(\z80_|execute_|ctl_alu_oe~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~18 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y17_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~10 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~10_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout & (((!\z80_|execute_|ctl_mRead~34_combout & !\z80_|pla_decode_|Equal21~1_combout )) # (!\z80_|execute_|ctl_mRead~9_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|execute_|ctl_mRead~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~10 .lut_mask = 16'h0155; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~9 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~9_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|pla_decode_|Equal6~1_combout )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|pla_decode_|Equal6~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~9 .lut_mask = 16'h0300; +defparam \z80_|execute_|ctl_sw_1d~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~9_combout = (!\z80_|execute_|ctl_sw_1d~9_combout & (((!\z80_|execute_|ctl_mRead~16_combout ) # (!\z80_|sequencer_|M5~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|M5~q ), + .datac(\z80_|execute_|ctl_sw_1d~9_combout ), + .datad(\z80_|execute_|ctl_mRead~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~9 .lut_mask = 16'h070F; +defparam \z80_|execute_|ctl_reg_gp_we~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~4_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~10_combout & \z80_|execute_|ctl_reg_gp_we~9_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_gp_we~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~4 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_reg_gp_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~7_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~6_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|execute_|ctl_reg_gp_we~5_combout & \z80_|execute_|ctl_reg_gp_we~4_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~6_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~5_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~7 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~3_combout = (\z80_|execute_|ctl_inc_cy~78_combout & (\z80_|execute_|ctl_bus_inc_oe~48_combout & (\z80_|execute_|ctl_bus_inc_oe~26_combout & \z80_|execute_|ctl_inc_cy~49_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~78_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~48_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~26_combout ), + .datad(\z80_|execute_|ctl_inc_cy~49_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~3 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~32 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~32_combout = (\z80_|execute_|ctl_reg_gp_we~2_combout & (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout & ((!\z80_|execute_|ixy_d~9_combout ) # (!\z80_|pla_decode_|Equal10~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~2_combout ), + .datac(\z80_|execute_|ixy_d~9_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~32 .lut_mask = 16'h004C; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~2 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~2_combout = (\z80_|execute_|nextM~2_combout & (((!\z80_|execute_|ixy_d~9_combout )) # (!\z80_|pla_decode_|Equal11~0_combout ))) # (!\z80_|execute_|nextM~2_combout & (!\z80_|execute_|ixy_d~5_combout & +// ((!\z80_|execute_|ixy_d~9_combout ) # (!\z80_|pla_decode_|Equal11~0_combout )))) + + .dataa(\z80_|execute_|nextM~2_combout ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|execute_|ixy_d~9_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~2 .lut_mask = 16'h2A3F; +defparam \z80_|execute_|ctl_sw_4u~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~3 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~3_combout = (\z80_|execute_|ctl_reg_gp_we~3_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout & \z80_|execute_|ctl_sw_4u~2_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~3_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout ), + .datac(\z80_|execute_|ctl_sw_4u~2_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4u~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4u~3 .lut_mask = 16'h8080; +defparam \z80_|execute_|ctl_sw_4u~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_we~8_combout = (\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # (((!\z80_|execute_|ctl_reg_gp_hilo[1]~15_combout ) # (!\z80_|execute_|ctl_sw_4u~3_combout )) # (!\z80_|execute_|ctl_reg_gp_we~7_combout )) + + .dataa(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datac(\z80_|execute_|ctl_sw_4u~3_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_we~8 .lut_mask = 16'hBFFF; +defparam \z80_|execute_|ctl_reg_gp_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~14 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~14_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~13_combout & ((\z80_|pla_decode_|Equal33~1_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~15_combout & +// !\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~13_combout ), + .datab(\z80_|pla_decode_|Equal33~1_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~15_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~14 .lut_mask = 16'h888A; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~24 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~24_combout = (\z80_|execute_|rsel3~combout & (((\z80_|nM1_int~2_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~12_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~14_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~14_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ), + .datad(\z80_|execute_|rsel3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~24 .lut_mask = 16'h5D00; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout = (\z80_|sequencer_|DFFE_M4_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & (!\z80_|pla_decode_|Equal12~1_combout & \z80_|pla_decode_|Equal25~0_combout ))) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|pla_decode_|Equal12~1_combout ), + .datad(\z80_|pla_decode_|Equal25~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~25 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~25_combout = (\z80_|execute_|ctl_ir_we~7_combout ) # ((\z80_|execute_|ctl_ir_we~15_combout ) # ((!\z80_|execute_|ctl_reg_sys_hilo~21_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~7_combout ), + .datab(\z80_|execute_|ctl_ir_we~15_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~25 .lut_mask = 16'hEFFF; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~26 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~26_combout = (\z80_|execute_|ctl_state_alu~3_combout & ((\z80_|execute_|ctl_iorw~10_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ) # (\z80_|execute_|ctl_state_alu~6_combout )))) + + .dataa(\z80_|execute_|ctl_iorw~10_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|execute_|ctl_state_alu~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~26 .lut_mask = 16'hFE00; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~46 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~46_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # ((\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T2_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|nextM~2_combout ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~46 .lut_mask = 16'h0E0C; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~27 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~27_combout = ((\z80_|execute_|ctl_reg_gp_hilo[0]~46_combout ) # ((\z80_|pla_decode_|Equal6~1_combout & \z80_|execute_|ixy_d~7_combout ))) # (!\z80_|execute_|ctl_mRead~23_combout ) + + .dataa(\z80_|execute_|ctl_mRead~23_combout ), + .datab(\z80_|pla_decode_|Equal6~1_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~46_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~27 .lut_mask = 16'hFDF5; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~29 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~29_combout = (\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ) # +// (!\z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~29 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~22 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~22_combout = (\z80_|execute_|ixy_d~7_combout & (((\z80_|execute_|ctl_mWrite~6_combout ) # (\z80_|execute_|ctl_mRead~5_combout )) # (!\z80_|execute_|ctl_al_we~13_combout ))) + + .dataa(\z80_|execute_|ctl_al_we~13_combout ), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datac(\z80_|execute_|ctl_mRead~5_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~22 .lut_mask = 16'hFD00; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~23 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~23_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~22_combout ) # ((!\z80_|execute_|ctl_flags_oe~1_combout & ((\z80_|execute_|ctl_state_alu~3_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~3_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|execute_|ctl_flags_oe~1_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~23 .lut_mask = 16'hFF0B; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~31 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~31_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~24_combout ) # (((\z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ) # (\z80_|execute_|ctl_reg_gp_hilo[0]~23_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~30_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~24_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~23_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~31 .lut_mask = 16'hFFFB; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~33 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~33_combout = (\z80_|execute_|ixy_d~6_combout & (((!\z80_|pla_decode_|Equal10~0_combout & !\z80_|pla_decode_|Equal11~0_combout )))) # (!\z80_|execute_|ixy_d~6_combout & (((!\z80_|pla_decode_|Equal11~0_combout )) # +// (!\z80_|execute_|ixy_d~9_combout ))) + + .dataa(\z80_|execute_|ixy_d~9_combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|pla_decode_|Equal11~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~33 .lut_mask = 16'h113F; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~26 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~26_combout = (\z80_|execute_|ctl_reg_gp_we~3_combout & (\z80_|execute_|fMRead~8_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~4_combout & \z80_|execute_|fMRead~10_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_we~3_combout ), + .datab(\z80_|execute_|fMRead~8_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), + .datad(\z80_|execute_|fMRead~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~26 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~34 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~34_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~12_combout & \z80_|execute_|ctl_reg_gp_sel[1]~26_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~12_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~34 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~25 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~25_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout & (\z80_|execute_|ctl_state_alu~13_combout & \z80_|execute_|ctl_reg_gp_sel[0]~24_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .datab(\z80_|execute_|ctl_state_alu~13_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~25 .lut_mask = 16'h4040; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~20 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~20_combout = (\z80_|execute_|ctl_reg_gp_sel~7_combout ) # ((!\z80_|execute_|ctl_reg_gp_hilo[1]~15_combout ) # (!\z80_|execute_|ctl_sw_2u~5_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_sel~7_combout ), + .datab(\z80_|execute_|ctl_sw_2u~5_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~20 .lut_mask = 16'hBBFF; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~21 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~21_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout & ((\z80_|execute_|rsel0~combout ) # ((!\z80_|execute_|setM1~50_combout & !\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) # +// (!\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout & (((!\z80_|execute_|setM1~50_combout & !\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), + .datab(\z80_|execute_|rsel0~combout ), + .datac(\z80_|execute_|setM1~50_combout ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~21 .lut_mask = 16'h888F; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~35 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[0]~35_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ) # (((\z80_|execute_|ctl_reg_gp_hilo[0]~21_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[0]~25_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~34_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~34_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~35 .lut_mask = 16'hFFBF; +defparam \z80_|execute_|ctl_reg_gp_hilo[0]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N14 +cycloneive_lcell_comb \z80_|pla_decode_|Equal2~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal2~2_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal1~7_combout & \z80_|pla_decode_|Equal32~0_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal2~0_combout ), + .datac(\z80_|pla_decode_|Equal1~7_combout ), + .datad(\z80_|pla_decode_|Equal32~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal2~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal2~2 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N14 +cycloneive_lcell_comb \z80_|pla_decode_|Equal1~6 ( +// Equation(s): +// \z80_|pla_decode_|Equal1~6_combout = (\z80_|pla_decode_|Equal1~4_combout & (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal1~5_combout & \z80_|pla_decode_|Equal1~7_combout ))) + + .dataa(\z80_|pla_decode_|Equal1~4_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|pla_decode_|Equal1~5_combout ), + .datad(\z80_|pla_decode_|Equal1~7_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal1~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal1~6 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal1~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N20 +cycloneive_lcell_comb \z80_|reg_control_|bank_exx~2 ( +// Equation(s): +// \z80_|reg_control_|bank_exx~2_combout = \z80_|reg_control_|bank_exx~q $ (((\z80_|pla_decode_|Equal1~6_combout & (\z80_|sequencer_|DFFE_T2_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )))) + + .dataa(\z80_|pla_decode_|Equal1~6_combout ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|reg_control_|bank_exx~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|reg_control_|bank_exx~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|bank_exx~2 .lut_mask = 16'hF078; +defparam \z80_|reg_control_|bank_exx~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y15_N21 +dffeas \z80_|reg_control_|bank_exx ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_control_|bank_exx~2_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_control_|bank_exx~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_control_|bank_exx .is_wysiwyg = "true"; +defparam \z80_|reg_control_|bank_exx .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N6 +cycloneive_lcell_comb \z80_|reg_control_|bank_hl_de1~0 ( +// Equation(s): +// \z80_|reg_control_|bank_hl_de1~0_combout = \z80_|reg_control_|bank_hl_de1~q $ (((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|pla_decode_|Equal2~2_combout & !\z80_|reg_control_|bank_exx~q )))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|pla_decode_|Equal2~2_combout ), + .datac(\z80_|reg_control_|bank_hl_de1~q ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_control_|bank_hl_de1~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|bank_hl_de1~0 .lut_mask = 16'hF0B4; +defparam \z80_|reg_control_|bank_hl_de1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y15_N7 +dffeas \z80_|reg_control_|bank_hl_de1 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_control_|bank_hl_de1~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_control_|bank_hl_de1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_control_|bank_hl_de1 .is_wysiwyg = "true"; +defparam \z80_|reg_control_|bank_hl_de1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~19 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout = (\z80_|execute_|ctl_sw_1d~4_combout & (((\z80_|execute_|ctl_sw_1d~8_combout & !\z80_|pla_decode_|Equal69~0_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_sw_1d~4_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|execute_|ctl_sw_1d~8_combout ), + .datad(\z80_|pla_decode_|Equal69~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~19 .lut_mask = 16'h22A2; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~28 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~28_combout = (!\z80_|execute_|ctl_reg_gp_sel~7_combout & \z80_|execute_|ctl_sw_2u~2_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_sel~7_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_sw_2u~2_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~28 .lut_mask = 16'h5050; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~29 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~29_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~28_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~27_combout & !\z80_|execute_|ctl_reg_in_hi~13_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~28_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~27_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~29 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~30 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~30_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~25_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~29_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~26_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~29_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~30 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y15_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~13 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~13_combout = (!\z80_|execute_|ctl_sw_1d~9_combout & (((!\z80_|execute_|ctl_state_alu~3_combout & !\z80_|execute_|ixy_d~7_combout )) # (!\z80_|execute_|ctl_mWrite~6_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~3_combout ), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ctl_sw_1d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~13 .lut_mask = 16'h0037; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~45 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~45_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~14_combout & ((\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ) # ((\z80_|sequencer_|DFFE_M1_ff~q ) # (\z80_|sequencer_|DFFE_T1_ff~q )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~14_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~45 .lut_mask = 16'hAAA8; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~2_combout = (((!\z80_|execute_|ctl_mRead~9_combout & !\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal6~0_combout )) # (!\z80_|pla_decode_|Equal8~0_combout ) + + .dataa(\z80_|execute_|ctl_mRead~9_combout ), + .datab(\z80_|pla_decode_|Equal8~0_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~2 .lut_mask = 16'h3F7F; +defparam \z80_|execute_|ctl_reg_use_sp~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~3_combout = (\z80_|execute_|nextM~11_combout & (\z80_|execute_|ctl_bus_inc_oe~49_combout & (\z80_|execute_|ctl_reg_use_sp~0_combout & \z80_|execute_|ctl_reg_use_sp~2_combout ))) + + .dataa(\z80_|execute_|nextM~11_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~49_combout ), + .datac(\z80_|execute_|ctl_reg_use_sp~0_combout ), + .datad(\z80_|execute_|ctl_reg_use_sp~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~3 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_use_sp~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~14 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~14_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~13_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~45_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~6_combout & \z80_|execute_|ctl_reg_use_sp~3_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~13_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ), + .datad(\z80_|execute_|ctl_reg_use_sp~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~14 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~32 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~32_combout = (\z80_|ir_|opcode [4] & (((!\z80_|execute_|ctl_reg_sys_hilo~21_combout & \z80_|execute_|ctl_state_alu~3_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|execute_|ctl_reg_sys_hilo~21_combout ), + .datad(\z80_|execute_|ctl_state_alu~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~32 .lut_mask = 16'h4C44; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~33 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~33_combout = (\z80_|execute_|ixy_d~7_combout & (((\z80_|execute_|ctl_mRead~3_combout ) # (\z80_|pla_decode_|Equal11~0_combout )))) # (!\z80_|execute_|ixy_d~7_combout & (\z80_|execute_|ixy_d~5_combout & +// ((\z80_|pla_decode_|Equal11~0_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_mRead~3_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|pla_decode_|Equal11~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~33 .lut_mask = 16'hFAC0; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~16 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~16_combout = (\z80_|execute_|setM1~57_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~15_combout & (\z80_|execute_|ctl_sw_2u~4_combout & \z80_|execute_|ctl_sw_2u~1_combout ))) + + .dataa(\z80_|execute_|setM1~57_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~15_combout ), + .datac(\z80_|execute_|ctl_sw_2u~4_combout ), + .datad(\z80_|execute_|ctl_sw_2u~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~16 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~34 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~34_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ) # ((!\z80_|execute_|ctl_reg_gp_hilo[1]~16_combout & \z80_|ir_|opcode [1])) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~16_combout ), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~34 .lut_mask = 16'hCFCC; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~35 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[0]~35_combout = ((\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ) # (\z80_|execute_|ctl_reg_gp_sel[0]~34_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[0]~35 .lut_mask = 16'hFFF5; +defparam \z80_|execute_|ctl_reg_gp_sel[0]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~20 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~20_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|pla_decode_|Equal4~0_combout ) # ((\z80_|pla_decode_|Equal1~4_combout & \z80_|pla_decode_|Equal2~1_combout )))) + + .dataa(\z80_|pla_decode_|Equal4~0_combout ), + .datab(\z80_|pla_decode_|Equal1~4_combout ), + .datac(\z80_|pla_decode_|Equal2~1_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~20 .lut_mask = 16'hEA00; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~21 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~21_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout ) # (\z80_|execute_|ctl_state_alu~2_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|nextM~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~21 .lut_mask = 16'h00FE; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~22 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~22_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~20_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~21_combout ) # ((\z80_|execute_|ctl_mRead~34_combout & \z80_|execute_|ctl_state_alu~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~20_combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~22 .lut_mask = 16'hFFEA; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~18 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~18_combout = (\z80_|execute_|ctl_mWrite~17_combout ) # ((\z80_|execute_|ctl_mRead~5_combout ) # ((\z80_|pla_decode_|Equal21~0_combout & \z80_|pla_decode_|Equal24~0_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~17_combout ), + .datab(\z80_|pla_decode_|Equal21~0_combout ), + .datac(\z80_|execute_|ctl_mRead~5_combout ), + .datad(\z80_|pla_decode_|Equal24~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~18 .lut_mask = 16'hFEFA; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~37 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~37_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~5_combout & (((!\z80_|execute_|ctl_mWrite~17_combout ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ), + .datad(\z80_|execute_|ctl_mWrite~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~37 .lut_mask = 16'h70F0; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~19 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~19_combout = ((\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~18_combout & \z80_|execute_|ixy_d~7_combout ))) # (!\z80_|execute_|ctl_reg_gp_sel[1]~37_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~18_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~37_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~19 .lut_mask = 16'hFF8F; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~23 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~23_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~22_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ) # ((!\z80_|execute_|ctl_reg_gp_hilo[1]~16_combout & \z80_|ir_|opcode [2]))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~22_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~16_combout ), + .datad(\z80_|ir_|opcode [2]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~23 .lut_mask = 16'hEFEE; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y14_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~16 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~16_combout = (\z80_|execute_|ctl_state_alu~3_combout & (((\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout )) # (!\z80_|execute_|ctl_mRead~17_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~17_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|ctl_state_alu~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~16 .lut_mask = 16'hF700; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~17 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~17_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~16_combout ) # ((\z80_|execute_|ixy_d~15_combout & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~16_combout ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|execute_|ixy_d~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~17 .lut_mask = 16'hFECC; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~11 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~11_combout = (!\z80_|decode_state_|DFFE_instCB~q & (!\z80_|decode_state_|DFFE_instED~q & ((\z80_|sequencer_|DFFE_M4_ff~q ) # (\z80_|sequencer_|M5~q )))) + + .dataa(\z80_|decode_state_|DFFE_instCB~q ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|decode_state_|DFFE_instED~q ), + .datad(\z80_|sequencer_|M5~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~11 .lut_mask = 16'h0504; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~36 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~36_combout = (\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [2] & (\z80_|execute_|ctl_reg_gp_sel[1]~11_combout & !\z80_|ir_|opcode [4]))) + + .dataa(\z80_|ir_|opcode [1]), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~36 .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~8_combout = (\z80_|ir_|opcode [7] & (!\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|ir_|opcode [3] & \z80_|ir_|opcode [6]))) + + .dataa(\z80_|ir_|opcode [7]), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~8 .lut_mask = 16'h0200; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~9_combout = (\z80_|ir_|opcode [3] & (((\z80_|sequencer_|DFFE_T3_ff~q )))) # (!\z80_|ir_|opcode [3] & (((!\z80_|pla_decode_|Equal12~0_combout & \z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) + + .dataa(\z80_|ir_|opcode [3]), + .datab(\z80_|pla_decode_|Equal12~0_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~9 .lut_mask = 16'hBF05; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~10 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~10_combout = (\z80_|ir_|opcode [0] & (\z80_|execute_|ctl_reg_gp_sel[1]~8_combout )) # (!\z80_|ir_|opcode [0] & (((\z80_|execute_|ctl_reg_gp_sel[1]~9_combout & \z80_|execute_|ctl_ir_we~6_combout )))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~8_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~9_combout ), + .datad(\z80_|execute_|ctl_ir_we~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~10 .lut_mask = 16'hD888; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~15 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~15_combout = (\z80_|ir_|opcode [5] & (((\z80_|execute_|ctl_reg_gp_sel[1]~36_combout & \z80_|execute_|ctl_reg_gp_sel[1]~10_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~15 .lut_mask = 16'hA222; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~31 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel[1]~31_combout = ((\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~17_combout ) # (\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ))) # (!\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~17_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel[1]~31 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_reg_gp_sel[1]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N24 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~5 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_de2~5_combout = (!\z80_|decode_state_|DFFE_instIY1~q & (!\z80_|decode_state_|DFFE_inst4~q & (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & \z80_|execute_|ctl_reg_gp_sel[1]~31_combout ))) + + .dataa(\z80_|decode_state_|DFFE_instIY1~q ), + .datab(\z80_|decode_state_|DFFE_inst4~q ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_de2~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_de2~5 .lut_mask = 16'h0100; +defparam \z80_|reg_control_|reg_sel_de2~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N28 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~6 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_de2~6_combout = (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (((\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ) # (\z80_|execute_|ctl_reg_gp_sel[0]~32_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_de2~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_de2~6 .lut_mask = 16'h00FD; +defparam \z80_|reg_control_|reg_sel_de2~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N24 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_de~0_combout = (!\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de1~q & (\z80_|reg_control_|reg_sel_de2~5_combout )) # (!\z80_|reg_control_|bank_hl_de1~q & ((\z80_|reg_control_|reg_sel_de2~6_combout ))))) + + .dataa(\z80_|reg_control_|bank_hl_de1~q ), + .datab(\z80_|reg_control_|bank_exx~q ), + .datac(\z80_|reg_control_|reg_sel_de2~5_combout ), + .datad(\z80_|reg_control_|reg_sel_de2~6_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_de~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_de~0 .lut_mask = 16'h3120; +defparam \z80_|reg_control_|reg_sel_de~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N14 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_50 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_50~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout & \z80_|reg_control_|reg_sel_de~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .datad(\z80_|reg_control_|reg_sel_de~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_50 .lut_mask = 16'h5000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N22 +cycloneive_lcell_comb \z80_|reg_control_|bank_hl_de2~0 ( +// Equation(s): +// \z80_|reg_control_|bank_hl_de2~0_combout = \z80_|reg_control_|bank_hl_de2~q $ (((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|pla_decode_|Equal2~2_combout & \z80_|reg_control_|bank_exx~q )))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|pla_decode_|Equal2~2_combout ), + .datac(\z80_|reg_control_|bank_hl_de2~q ), + .datad(\z80_|reg_control_|bank_exx~q ), + .cin(gnd), + .combout(\z80_|reg_control_|bank_hl_de2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|bank_hl_de2~0 .lut_mask = 16'hB4F0; +defparam \z80_|reg_control_|bank_hl_de2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y15_N23 +dffeas \z80_|reg_control_|bank_hl_de2 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_control_|bank_hl_de2~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_control_|bank_hl_de2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_control_|bank_hl_de2 .is_wysiwyg = "true"; +defparam \z80_|reg_control_|bank_hl_de2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N16 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~4 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_de2~4_combout = (\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de2~q & (\z80_|reg_control_|reg_sel_de2~5_combout )) # (!\z80_|reg_control_|bank_hl_de2~q & ((\z80_|reg_control_|reg_sel_de2~6_combout ))))) + + .dataa(\z80_|reg_control_|bank_hl_de2~q ), + .datab(\z80_|reg_control_|bank_exx~q ), + .datac(\z80_|reg_control_|reg_sel_de2~5_combout ), + .datad(\z80_|reg_control_|reg_sel_de2~6_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_de2~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_de2~4 .lut_mask = 16'hC480; +defparam \z80_|reg_control_|reg_sel_de2~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N24 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_46 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_46~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout & \z80_|reg_control_|reg_sel_de2~4_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .datad(\z80_|reg_control_|reg_sel_de2~4_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_46 .lut_mask = 16'h5000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N22 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_47 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_47~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout & \z80_|reg_control_|reg_sel_de2~4_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .datad(\z80_|reg_control_|reg_sel_de2~4_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_47 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y11_N1 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N16 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_51 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_51~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout & \z80_|reg_control_|reg_sel_de~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .datad(\z80_|reg_control_|reg_sel_de~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_51 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y11_N7 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~33 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~33_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [2]), + .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~33 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[2]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N8 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_hl~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_hl~0_combout = (!\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de1~q & ((\z80_|reg_control_|reg_sel_de2~6_combout ))) # (!\z80_|reg_control_|bank_hl_de1~q & (\z80_|reg_control_|reg_sel_de2~5_combout )))) + + .dataa(\z80_|reg_control_|bank_hl_de1~q ), + .datab(\z80_|reg_control_|bank_exx~q ), + .datac(\z80_|reg_control_|reg_sel_de2~5_combout ), + .datad(\z80_|reg_control_|reg_sel_de2~6_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_hl~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_hl~0 .lut_mask = 16'h3210; +defparam \z80_|reg_control_|reg_sel_hl~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N26 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_59 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_59~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout & (\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|reg_control_|reg_sel_hl~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_59 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y12_N31 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y15_N30 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_hl2~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_hl2~0_combout = (\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de2~q & ((\z80_|reg_control_|reg_sel_de2~6_combout ))) # (!\z80_|reg_control_|bank_hl_de2~q & (\z80_|reg_control_|reg_sel_de2~5_combout )))) + + .dataa(\z80_|reg_control_|bank_hl_de2~q ), + .datab(\z80_|reg_control_|bank_exx~q ), + .datac(\z80_|reg_control_|reg_sel_de2~5_combout ), + .datad(\z80_|reg_control_|reg_sel_de2~6_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_hl2~0 .lut_mask = 16'hC840; +defparam \z80_|reg_control_|reg_sel_hl2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N4 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_54 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_54~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout & (!\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|reg_control_|reg_sel_hl2~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_54 .lut_mask = 16'h2200; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N18 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_55 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_55~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout & (\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|reg_control_|reg_sel_hl2~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_55 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y12_N25 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N20 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_58 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_58~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout & (!\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|reg_control_|reg_sel_hl~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_58 .lut_mask = 16'h0A00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~34 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~34_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [2] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [2] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [2]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~34 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp0[2]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N2 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout & !\z80_|execute_|ctl_reg_gp_we~8_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 .lut_mask = 16'h0C0C; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N0 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout = (\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & !\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ))) + + .dataa(\z80_|reg_control_|bank_exx~q ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 .lut_mask = 16'h0020; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N22 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout & \z80_|execute_|ctl_reg_gp_we~8_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 .lut_mask = 16'hC0C0; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N18 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout = (!\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & !\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ))) + + .dataa(\z80_|reg_control_|bank_exx~q ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 .lut_mask = 16'h0010; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y14_N29 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N12 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout = (\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & !\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ))) + + .dataa(\z80_|reg_control_|bank_exx~q ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 .lut_mask = 16'h0020; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y14_N7 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N16 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout = (!\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & !\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ))) + + .dataa(\z80_|reg_control_|bank_exx~q ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 .lut_mask = 16'h0010; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~36 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~36_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [2]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [2]), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~36 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[2]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~15 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~15_combout = (((\z80_|execute_|ctl_66_oe~2_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~14_combout )) # (!\z80_|execute_|ctl_reg_in_hi~5_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~13_combout ) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~13_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~5_combout ), + .datac(\z80_|execute_|ctl_66_oe~2_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~15 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|ctl_reg_sel_wz~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~18 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~18_combout = (((\z80_|execute_|ctl_reg_sel_wz~15_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~12_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~21_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~17_combout ) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~17_combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~21_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~12_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~18 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_reg_sel_wz~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N0 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_83 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_83~combout = (\z80_|execute_|ctl_reg_sel_wz~18_combout & (\z80_|reg_control_|reg_sys_we_lo~combout & \z80_|execute_|ctl_reg_sys_hilo[0]~31_combout )) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~18_combout ), + .datab(gnd), + .datac(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_83 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_83 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y13_N5 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N8 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_82 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_82~combout = (\z80_|execute_|ctl_reg_sel_wz~18_combout & (!\z80_|reg_control_|reg_sys_we_lo~combout & \z80_|execute_|ctl_reg_sys_hilo[0]~31_combout )) + + .dataa(\z80_|execute_|ctl_reg_sel_wz~18_combout ), + .datab(gnd), + .datac(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_82 .lut_mask = 16'h0A00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_82 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~37 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~37_combout = (\z80_|reg_file_|gdfx_temp0[2]~36_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|gdfx_temp0[2]~36_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~37 .lut_mask = 16'hC0CC; +defparam \z80_|reg_file_|gdfx_temp0[2]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N6 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & (\z80_|decode_state_|DFFE_inst4~q & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), + .datab(\z80_|decode_state_|DFFE_inst4~q ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 .lut_mask = 16'h0080; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N14 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_iy~2 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_iy~2_combout = (\z80_|decode_state_|DFFE_instIY1~q & (!\z80_|decode_state_|DFFE_inst4~q & (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & \z80_|execute_|ctl_reg_gp_sel[1]~31_combout ))) + + .dataa(\z80_|decode_state_|DFFE_instIY1~q ), + .datab(\z80_|decode_state_|DFFE_inst4~q ), + .datac(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_iy~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_iy~2 .lut_mask = 16'h0200; +defparam \z80_|reg_control_|reg_sel_iy~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N10 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_71 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_71~combout = (\z80_|reg_control_|reg_sel_iy~2_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout & \z80_|execute_|ctl_reg_gp_we~8_combout )) + + .dataa(gnd), + .datab(\z80_|reg_control_|reg_sel_iy~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y12_N3 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N28 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|decode_state_|DFFE_inst4~q ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|decode_state_|DFFE_inst4~q ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 .lut_mask = 16'h2000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y12_N1 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N12 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_70 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_70~combout = (\z80_|reg_control_|reg_sel_iy~2_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout & !\z80_|execute_|ctl_reg_gp_we~8_combout )) + + .dataa(gnd), + .datab(\z80_|reg_control_|reg_sel_iy~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70 .lut_mask = 16'h00C0; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~38 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~38_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (\z80_|reg_file_|b2v_latch_ix_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [2]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_iy_lo|latch [2]), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~38 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[2]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout = (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|ir_|opcode [3] & (\z80_|ir_|opcode [4] & \z80_|pla_decode_|Equal24~0_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|ir_|opcode [4]), + .datad(\z80_|pla_decode_|Equal24~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~9_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|execute_|ctl_mRead~2_combout )))) # (!\z80_|pla_decode_|Equal47~0_combout +// & (((!\z80_|execute_|ixy_d~7_combout )) # (!\z80_|execute_|ctl_mRead~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal47~0_combout ), + .datab(\z80_|execute_|ctl_mRead~2_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~9 .lut_mask = 16'h153F; +defparam \z80_|execute_|ctl_reg_in_hi~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~10 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~10_combout = (\z80_|execute_|ctl_reg_gp_we~7_combout & (\z80_|execute_|ctl_reg_in_hi~8_combout & \z80_|execute_|ctl_reg_in_hi~9_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~7_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_in_hi~8_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~10 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_reg_in_hi~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_lo~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_lo~8_combout = (\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ) # (((!\z80_|execute_|ctl_reg_in_hi~10_combout ) # (!\z80_|execute_|ctl_reg_in_lo~9_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~21_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~21_combout ), + .datac(\z80_|execute_|ctl_reg_in_lo~9_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_lo~8 .lut_mask = 16'hBFFF; +defparam \z80_|execute_|ctl_reg_in_lo~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N0 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_sp_lo|latch[2]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_sp_lo|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp0[2]~42_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_sp_lo|latch[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[2]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~4_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal6~1_combout & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_M1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|pla_decode_|Equal6~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~4 .lut_mask = 16'h0D00; +defparam \z80_|execute_|ctl_reg_use_sp~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~5_combout = (\z80_|execute_|ctl_reg_use_sp~4_combout ) # ((\z80_|execute_|ctl_mRead~15_combout & ((\z80_|execute_|ctl_reg_in_hi~2_combout ) # (\z80_|execute_|ctl_state_alu~4_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~15_combout ), + .datab(\z80_|execute_|ctl_reg_use_sp~4_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~5 .lut_mask = 16'hEEEC; +defparam \z80_|execute_|ctl_reg_use_sp~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_use_sp~6_combout = (\z80_|execute_|ctl_reg_use_sp~5_combout ) # ((!\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ) # (!\z80_|execute_|ctl_reg_use_sp~3_combout )) + + .dataa(\z80_|execute_|ctl_reg_use_sp~5_combout ), + .datab(\z80_|execute_|ctl_reg_use_sp~3_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_use_sp~6 .lut_mask = 16'hBFBF; +defparam \z80_|execute_|ctl_reg_use_sp~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N14 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout = (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & \z80_|execute_|ctl_reg_gp_sel[1]~31_combout ))) + + .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y12_N1 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_sp_lo|latch[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~5 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~5_combout = (\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_mRead~12_combout ) # ((\z80_|pla_decode_|Equal49~0_combout ) # (!\z80_|execute_|ctl_sw_1d~8_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~12_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|execute_|ctl_sw_1d~8_combout ), + .datad(\z80_|pla_decode_|Equal49~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~5 .lut_mask = 16'hCC8C; +defparam \z80_|execute_|ctl_sw_1d~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y19_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_im_we ( +// Equation(s): +// \z80_|execute_|ctl_im_we~combout = (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_im_we~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_im_we .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_im_we .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~6 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~6_combout = (\z80_|execute_|ctl_sw_1d~4_combout & (!\z80_|execute_|ctl_sw_1d~5_combout & (\z80_|execute_|ctl_sw_2d~9_combout & !\z80_|execute_|ctl_im_we~combout ))) + + .dataa(\z80_|execute_|ctl_sw_1d~4_combout ), + .datab(\z80_|execute_|ctl_sw_1d~5_combout ), + .datac(\z80_|execute_|ctl_sw_2d~9_combout ), + .datad(\z80_|execute_|ctl_im_we~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~6 .lut_mask = 16'h0020; +defparam \z80_|execute_|ctl_sw_1d~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~7 ( +// Equation(s): +// \z80_|execute_|ctl_sw_1d~7_combout = ((\z80_|execute_|ctl_66_oe~2_combout & !\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q )) # (!\z80_|execute_|ctl_sw_1d~6_combout ) + + .dataa(\z80_|execute_|ctl_66_oe~2_combout ), + .datab(\z80_|execute_|ctl_sw_1d~6_combout ), + .datac(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_1d~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_1d~7 .lut_mask = 16'h3B3B; +defparam \z80_|execute_|ctl_sw_1d~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N18 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[2]~2 ( +// Equation(s): +// \z80_|reg_file_|db_lo_ds[2]~2_combout = (\z80_|reg_file_|gdfx_temp0[2]~42_combout ) # ((!\z80_|execute_|ctl_reg_out_lo~5_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout & \z80_|execute_|ctl_reg_out_lo~7_combout ))) + + .dataa(\z80_|execute_|ctl_reg_out_lo~5_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_ds[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_ds[2]~2 .lut_mask = 16'hFF40; +defparam \z80_|reg_file_|db_lo_ds[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N8 +cycloneive_lcell_comb \z80_|alu_control_|db[2]~28 ( +// Equation(s): +// \z80_|alu_control_|db[2]~28_combout = (\z80_|reg_file_|db_lo_ds[2]~2_combout & (((!\z80_|execute_|ctl_sw_mask543_en~0_combout & \z80_|bus_control_|db[2]~13_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) + + .dataa(\z80_|execute_|ctl_sw_mask543_en~0_combout ), + .datab(\z80_|bus_control_|db[2]~13_combout ), + .datac(\z80_|execute_|ctl_sw_1d~7_combout ), + .datad(\z80_|reg_file_|db_lo_ds[2]~2_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[2]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[2]~28 .lut_mask = 16'h4F00; +defparam \z80_|alu_control_|db[2]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~11 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~11_combout = (((\z80_|execute_|ixy_d~6_combout & \z80_|pla_decode_|Equal9~1_combout )) # (!\z80_|execute_|ctl_reg_in_hi~5_combout )) # (!\z80_|execute_|ctl_reg_in_hi~6_combout ) + + .dataa(\z80_|execute_|ctl_reg_in_hi~6_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~5_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~11 .lut_mask = 16'hF777; +defparam \z80_|execute_|ctl_reg_in_hi~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~12 ( +// Equation(s): +// \z80_|execute_|ctl_reg_in_hi~12_combout = (((\z80_|execute_|ctl_reg_in_hi~11_combout ) # (!\z80_|execute_|ctl_reg_in_hi~4_combout )) # (!\z80_|execute_|ctl_reg_in_hi~3_combout )) # (!\z80_|execute_|ctl_reg_in_hi~10_combout ) + + .dataa(\z80_|execute_|ctl_reg_in_hi~10_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~3_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~11_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_in_hi~12 .lut_mask = 16'hF7FF; +defparam \z80_|execute_|ctl_reg_in_hi~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~42 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~42_combout = ((\z80_|execute_|ctl_state_alu~3_combout & ((!\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ) # (!\z80_|execute_|setM1~48_combout )))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~34_combout ) + + .dataa(\z80_|execute_|setM1~48_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ), + .datac(\z80_|execute_|ctl_state_alu~3_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~42 .lut_mask = 16'h70FF; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~39 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~39_combout = ((\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mRead~3_combout ) # (!\z80_|execute_|ctl_al_we~14_combout )))) # (!\z80_|execute_|setM1~30_combout ) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|setM1~30_combout ), + .datac(\z80_|execute_|ctl_mRead~3_combout ), + .datad(\z80_|execute_|ctl_al_we~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~39 .lut_mask = 16'hB3BB; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~38 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~38_combout = ((!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ixy_d~5_combout ) # (\z80_|execute_|ctl_state_alu~2_combout )))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ), + .datad(\z80_|execute_|nextM~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~38 .lut_mask = 16'h0FEF; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~40 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~40_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ) # ((!\z80_|execute_|rsel3~combout & !\z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ), + .datab(\z80_|execute_|rsel3~combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~40 .lut_mask = 16'hFAFB; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~41 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~41_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ) # (((!\z80_|execute_|rsel0~combout & \z80_|execute_|ctl_reg_gp_hilo[1]~20_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ), + .datab(\z80_|execute_|rsel0~combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~41 .lut_mask = 16'hBFAF; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~43 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_hilo[1]~43_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ) # (((\z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ) # (!\z80_|execute_|ctl_reg_gp_we~4_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~43 .lut_mask = 16'hFBFF; +defparam \z80_|execute_|ctl_reg_gp_hilo[1]~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N12 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout & !\z80_|execute_|ctl_reg_gp_we~8_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 .lut_mask = 16'h00F0; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N14 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout & (\z80_|decode_state_|DFFE_inst4~q & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .datac(\z80_|decode_state_|DFFE_inst4~q ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 .lut_mask = 16'h0080; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N30 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|execute_|ctl_reg_use_sp~6_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datac(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N14 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_68 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_68~combout = (\z80_|reg_control_|reg_sel_iy~2_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout & !\z80_|execute_|ctl_reg_gp_we~8_combout )) + + .dataa(gnd), + .datab(\z80_|reg_control_|reg_sel_iy~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68 .lut_mask = 16'h00C0; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N0 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout = (!\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) + + .dataa(\z80_|reg_control_|bank_exx~q ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 .lut_mask = 16'h0010; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N8 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout = (\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ))) + + .dataa(\z80_|reg_control_|bank_exx~q ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 .lut_mask = 16'h0200; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~18 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~18_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout )) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~18 .lut_mask = 16'hFEFE; +defparam \z80_|reg_file_|gdfx_temp1[0]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N26 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_80 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_80~combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout & (!\z80_|reg_control_|reg_sys_we_hi~combout & \z80_|execute_|ctl_reg_sel_wz~18_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), + .datac(\z80_|reg_control_|reg_sys_we_hi~combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~18_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_80 .lut_mask = 16'h0C00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y13_N14 +cycloneive_lcell_comb \z80_|pla_decode_|Equal21~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal21~2_combout = (\z80_|pla_decode_|Equal40~0_combout & (\z80_|pla_decode_|Equal6~0_combout & !\z80_|ir_|opcode [5])) + + .dataa(\z80_|pla_decode_|Equal40~0_combout ), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(gnd), + .datad(\z80_|ir_|opcode [5]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal21~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal21~2 .lut_mask = 16'h0088; +defparam \z80_|pla_decode_|Equal21~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N4 +cycloneive_lcell_comb \z80_|reg_control_|bank_af~0 ( +// Equation(s): +// \z80_|reg_control_|bank_af~0_combout = \z80_|reg_control_|bank_af~q $ (((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|pla_decode_|Equal32~0_combout & \z80_|pla_decode_|Equal21~2_combout )))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|pla_decode_|Equal32~0_combout ), + .datac(\z80_|reg_control_|bank_af~q ), + .datad(\z80_|pla_decode_|Equal21~2_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|bank_af~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|bank_af~0 .lut_mask = 16'hB4F0; +defparam \z80_|reg_control_|bank_af~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y13_N5 +dffeas \z80_|reg_control_|bank_af ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_control_|bank_af~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_control_|bank_af~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_control_|bank_af .is_wysiwyg = "true"; +defparam \z80_|reg_control_|bank_af .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N24 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_af~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_af~0_combout = (!\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (!\z80_|reg_control_|bank_af~q & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) + + .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datac(\z80_|reg_control_|bank_af~q ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_af~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_af~0 .lut_mask = 16'h0400; +defparam \z80_|reg_control_|reg_sel_af~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N10 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_af2~0 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_af2~0_combout = (!\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_control_|bank_af~q & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) + + .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datac(\z80_|reg_control_|bank_af~q ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_af2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_af2~0 .lut_mask = 16'h4000; +defparam \z80_|reg_control_|reg_sel_af2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N4 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_28 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_28~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout & (\z80_|reg_control_|reg_sel_af2~0_combout & !\z80_|execute_|ctl_reg_gp_we~8_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datab(gnd), + .datac(\z80_|reg_control_|reg_sel_af2~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_28 .lut_mask = 16'h00A0; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~17 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~17_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout & \z80_|reg_control_|reg_sel_af~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ), + .datac(\z80_|reg_control_|reg_sel_af~0_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~17 .lut_mask = 16'hFFEA; +defparam \z80_|reg_file_|gdfx_temp1[0]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~19 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~19_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ) # ((\z80_|reg_file_|gdfx_temp1[0]~18_combout ) # (\z80_|reg_file_|gdfx_temp1[0]~17_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~18_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[0]~17_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~19 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp1[0]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N0 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_52 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_52~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout & (!\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|reg_control_|reg_sel_hl2~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_52 .lut_mask = 16'h0A00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N28 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_44 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_44~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout & \z80_|reg_control_|reg_sel_de2~4_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datad(\z80_|reg_control_|reg_sel_de2~4_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_44 .lut_mask = 16'h5000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N30 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_48 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_48~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout & \z80_|reg_control_|reg_sel_de~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datad(\z80_|reg_control_|reg_sel_de~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_48 .lut_mask = 16'h5000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N20 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_56 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_56~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout & \z80_|reg_control_|reg_sel_hl~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_56 .lut_mask = 16'h5000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~16 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~16_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~16 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp1[0]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~20 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~20_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout ) # ((\z80_|reg_file_|gdfx_temp1[0]~19_combout ) # ((\z80_|reg_file_|gdfx_temp1[0]~16_combout ) # (\z80_|execute_|ctl_sw_4u~6_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[0]~19_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~16_combout ), + .datad(\z80_|execute_|ctl_sw_4u~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~20 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp1[0]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N6 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout & \z80_|execute_|ctl_reg_gp_we~8_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 .lut_mask = 16'hF000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N4 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & (\z80_|decode_state_|DFFE_inst4~q & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), + .datab(\z80_|decode_state_|DFFE_inst4~q ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 .lut_mask = 16'h0080; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y16_N7 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N8 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_69 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_69~combout = (\z80_|reg_control_|reg_sel_iy~2_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout & \z80_|execute_|ctl_reg_gp_we~8_combout )) + + .dataa(gnd), + .datab(\z80_|reg_control_|reg_sel_iy~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y16_N25 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~34 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~34_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [2]), + .datad(\z80_|reg_file_|b2v_latch_iy_hi|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~34 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[2]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N2 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|execute_|ctl_reg_use_sp~6_combout & \z80_|execute_|ctl_reg_gp_sel[1]~31_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datac(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y15_N15 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N30 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_81 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_81~combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout & (\z80_|reg_control_|reg_sys_we_hi~combout & \z80_|execute_|ctl_reg_sel_wz~18_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), + .datac(\z80_|reg_control_|reg_sys_we_hi~combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~18_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_81 .lut_mask = 16'hC000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_81 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y15_N9 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~36 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~36_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (\z80_|reg_file_|b2v_latch_wz_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [2]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [2]), + .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~36 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp1[2]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N18 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_29 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_29~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout & (\z80_|reg_control_|reg_sel_af2~0_combout & \z80_|execute_|ctl_reg_gp_we~8_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datab(gnd), + .datac(\z80_|reg_control_|reg_sel_af2~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_29 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y16_N25 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~35 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~35_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout & (\z80_|alu_|db[2]~16_combout & ((\z80_|reg_file_|b2v_latch_af2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # +// (!\z80_|execute_|ctl_reg_in_hi~12_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .datab(\z80_|alu_|db[2]~16_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~35 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[2]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N22 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout = (\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ))) + + .dataa(\z80_|reg_control_|bank_exx~q ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 .lut_mask = 16'h0200; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y16_N31 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N20 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout = (!\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ))) + + .dataa(\z80_|reg_control_|bank_exx~q ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 .lut_mask = 16'h0100; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y16_N13 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~33 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~33_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (\z80_|reg_file_|b2v_latch_bc2_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]), + .datad(\z80_|reg_file_|b2v_latch_bc_hi|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~33 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[2]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~37 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~37_combout = (\z80_|reg_file_|gdfx_temp1[2]~34_combout & (\z80_|reg_file_|gdfx_temp1[2]~36_combout & (\z80_|reg_file_|gdfx_temp1[2]~35_combout & \z80_|reg_file_|gdfx_temp1[2]~33_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[2]~34_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[2]~36_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[2]~35_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[2]~33_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~37 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[2]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N20 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_45 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_45~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout & \z80_|reg_control_|reg_sel_de2~4_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sel_de2~4_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_45 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y15_N31 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N12 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp1[2]~39_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N24 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_49 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_49~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout & \z80_|reg_control_|reg_sel_de~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datad(\z80_|reg_control_|reg_sel_de~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_49 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y15_N13 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~31 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~31_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [2]), + .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~31 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[2]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N2 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_33 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_33~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout & \z80_|reg_control_|reg_sel_af~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_33 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y15_N31 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N30 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[2]~12 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[2]~12_combout = (\z80_|execute_|ctl_reg_gp_we~8_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [2]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [2]), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[2]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[2]~12 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[2]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N26 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_57 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_57~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout & \z80_|reg_control_|reg_sel_hl~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_57 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y14_N21 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N2 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_53 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_53~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout & (\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|reg_control_|reg_sel_hl2~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_53 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y14_N7 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~32 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~32_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (\z80_|reg_file_|b2v_latch_hl_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_hl2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (((\z80_|reg_file_|b2v_latch_hl2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [2]), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~32 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[2]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y14_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~38 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~38_combout = (\z80_|reg_file_|gdfx_temp1[2]~37_combout & (\z80_|reg_file_|gdfx_temp1[2]~31_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[2]~12_combout & \z80_|reg_file_|gdfx_temp1[2]~32_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[2]~37_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[2]~31_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|db[2]~12_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[2]~32_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~38 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[2]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~11 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~11_combout = (((\z80_|execute_|ctl_inc_dec~9_combout ) # (!\z80_|execute_|ctl_inc_dec~5_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~42_combout )) # (!\z80_|execute_|ctl_inc_dec~6_combout ) + + .dataa(\z80_|execute_|ctl_inc_dec~6_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~42_combout ), + .datac(\z80_|execute_|ctl_inc_dec~5_combout ), + .datad(\z80_|execute_|ctl_inc_dec~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~11 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_inc_dec~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N8 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout = \z80_|address_latch_|Q [9] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ) + + .dataa(\z80_|address_latch_|Q [9]), + .datab(gnd), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out .lut_mask = 16'h5A5A; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y14_N31 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[1]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y17_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_sel_shift~5_combout = (\z80_|sequencer_|DFFE_T4_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|pla_decode_|Equal20~0_combout ) # (\z80_|execute_|ctl_ir_we~8_combout )))) + + .dataa(\z80_|pla_decode_|Equal20~0_combout ), + .datab(\z80_|sequencer_|DFFE_T4_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|execute_|ctl_ir_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~5 .lut_mask = 16'h0C08; +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_sel_shift~3_combout = (\z80_|execute_|ctl_state_alu~4_combout ) # ((\z80_|decode_state_|DFFE_instCB~q & (\z80_|pla_decode_|Equal33~0_combout & \z80_|execute_|ctl_mWrite~5_combout ))) + + .dataa(\z80_|decode_state_|DFFE_instCB~q ), + .datab(\z80_|pla_decode_|Equal33~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~5_combout ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~3 .lut_mask = 16'hFF80; +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_sel_shift~4_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ) # ((\z80_|execute_|ctl_ir_we~6_combout & (\z80_|execute_|ctl_ir_we~5_combout & \z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ))) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ), + .datab(\z80_|execute_|ctl_ir_we~6_combout ), + .datac(\z80_|execute_|ctl_ir_we~5_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~4 .lut_mask = 16'hEAAA; +defparam \z80_|execute_|ctl_flags_cf2_sel_shift~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~4_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [0] & !\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) + + .dataa(\z80_|pla_decode_|Equal3~1_combout ), + .datab(\z80_|pla_decode_|Equal13~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~4 .lut_mask = 16'h0008; +defparam \z80_|execute_|ctl_flags_cf_cpl~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~5_combout = ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_state_alu~5_combout ) # (\z80_|execute_|ctl_alu_op_low~25_combout )))) # (!\z80_|execute_|ctl_state_alu~13_combout ) + + .dataa(\z80_|execute_|ctl_state_alu~5_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|execute_|ctl_alu_op_low~25_combout ), + .datad(\z80_|execute_|ctl_state_alu~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~5 .lut_mask = 16'h32FF; +defparam \z80_|execute_|ctl_flags_cf_cpl~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~16 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~16_combout = (\z80_|pla_decode_|Equal9~0_combout & (\z80_|pla_decode_|Equal63~0_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # (\z80_|nM1_int~2_combout )))) + + .dataa(\z80_|pla_decode_|Equal9~0_combout ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~16 .lut_mask = 16'h8880; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~6_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_flags_cf_cpl~4_combout ) # ((\z80_|execute_|ctl_flags_cf_cpl~5_combout )))) # (!\z80_|alu_flags_|DFFE_inst_latch_nf~q & +// (((\z80_|execute_|ctl_alu_sel_op2_neg~16_combout )))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .datab(\z80_|execute_|ctl_flags_cf_cpl~4_combout ), + .datac(\z80_|execute_|ctl_flags_cf_cpl~5_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~6 .lut_mask = 16'hFDA8; +defparam \z80_|execute_|ctl_flags_cf_cpl~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y19_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~7_combout = (\z80_|execute_|ctl_flags_cf_cpl~6_combout ) # ((\z80_|pla_decode_|Equal9~0_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal62~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal9~0_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|pla_decode_|Equal62~2_combout ), + .datad(\z80_|execute_|ctl_flags_cf_cpl~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~7 .lut_mask = 16'hFF20; +defparam \z80_|execute_|ctl_flags_cf_cpl~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y20_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~10_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ) # ((!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|execute_|ctl_alu_op_low~25_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|execute_|ctl_alu_op_low~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~10 .lut_mask = 16'hDCCC; +defparam \z80_|execute_|ctl_flags_cf_cpl~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y20_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~8_combout = (\z80_|execute_|ctl_flags_cf_cpl~10_combout ) # ((\z80_|execute_|ctl_alu_op_low~34_combout & (\z80_|execute_|ctl_alu_op_low~25_combout & \z80_|execute_|ctl_alu_op_low~22_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~34_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~25_combout ), + .datac(\z80_|execute_|ctl_flags_cf_cpl~10_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~8 .lut_mask = 16'hF8F0; +defparam \z80_|execute_|ctl_flags_cf_cpl~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 ( +// Equation(s): +// \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ixy_d~7_combout & (!\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal13~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal55~0_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y20_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~42 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~42_combout = (\z80_|execute_|ctl_alu_op_low~34_combout ) # (!\z80_|execute_|ctl_alu_op_low~48_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op_low~48_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~42 .lut_mask = 16'hFF0F; +defparam \z80_|execute_|ctl_alu_op_low~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y20_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~9 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~9_combout = (\z80_|execute_|ctl_flags_cf_cpl~7_combout ) # ((\z80_|execute_|ctl_flags_cf_cpl~8_combout ) # ((\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout & \z80_|execute_|ctl_alu_op_low~42_combout ))) + + .dataa(\z80_|execute_|ctl_flags_cf_cpl~7_combout ), + .datab(\z80_|execute_|ctl_flags_cf_cpl~8_combout ), + .datac(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), + .datad(\z80_|execute_|ctl_alu_op_low~42_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~9 .lut_mask = 16'hFEEE; +defparam \z80_|execute_|ctl_flags_cf_cpl~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y17_N12 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout = (\z80_|execute_|ctl_alu_op_low~40_combout & (\z80_|pla_decode_|Equal21~1_combout & ((\z80_|execute_|ixy_d~6_combout ) # (\z80_|execute_|ctl_mRead~9_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~40_combout ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ctl_mRead~9_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 .lut_mask = 16'h8880; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y20_N24 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout = ((!\z80_|pla_decode_|Equal39~0_combout & ((!\z80_|pla_decode_|Equal40~2_combout ) # (!\z80_|ir_|opcode [5])))) # (!\z80_|execute_|ixy_d~6_combout ) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal40~2_combout ), + .datad(\z80_|pla_decode_|Equal39~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 .lut_mask = 16'h557F; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y20_N22 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout = (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout & ((\z80_|execute_|ctl_alu_op_low~37_combout ) # (\z80_|execute_|ctl_alu_op_low~38_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~37_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~38_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 .lut_mask = 16'h3232; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~18 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~18_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|pla_decode_|Equal11~0_combout & \z80_|sequencer_|DFFE_T3_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(gnd), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~18 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_mWrite~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N14 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1_combout = (!\z80_|execute_|ctl_mWrite~18_combout & (((!\z80_|execute_|ctl_mWrite~17_combout & !\z80_|pla_decode_|Equal61~2_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~17_combout ), + .datab(\z80_|pla_decode_|Equal61~2_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_mWrite~18_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1 .lut_mask = 16'h001F; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y20_N16 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2_combout = (\z80_|nM1_int~2_combout & (!\z80_|execute_|ctl_mRead~34_combout & ((!\z80_|pla_decode_|Equal56~0_combout ) # (!\z80_|execute_|ctl_state_alu~3_combout )))) # (!\z80_|nM1_int~2_combout & +// (((!\z80_|pla_decode_|Equal56~0_combout ) # (!\z80_|execute_|ctl_state_alu~3_combout )))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|execute_|ctl_state_alu~3_combout ), + .datad(\z80_|pla_decode_|Equal56~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2 .lut_mask = 16'h0777; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y20_N10 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3_combout = (\z80_|execute_|ctl_alu_core_R~4_combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~1_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_R~4_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~1_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~2_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3 .lut_mask = 16'h8000; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y20_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~2_combout = (\z80_|execute_|ctl_alu_op_low~37_combout & (((\z80_|execute_|ctl_mRead~34_combout & \z80_|execute_|ixy_d~6_combout )) # (!\z80_|execute_|ctl_alu_oe~4_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~37_combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ctl_alu_oe~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~2 .lut_mask = 16'h80AA; +defparam \z80_|execute_|ctl_flags_cf_cpl~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y20_N2 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~3_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~13_combout & (\z80_|execute_|ctl_alu_core_S~7_combout & !\z80_|execute_|ctl_alu_core_R~1_combout ))) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ), + .datac(\z80_|execute_|ctl_alu_core_S~7_combout ), + .datad(\z80_|execute_|ctl_alu_core_R~1_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'h0080; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y20_N6 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~3_combout & (!\z80_|execute_|ctl_flags_cf_cpl~2_combout & (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0_combout ))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~3_combout ), + .datab(\z80_|execute_|ctl_flags_cf_cpl~2_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 .lut_mask = 16'h0200; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y20_N12 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout = (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout & (\z80_|execute_|ctl_flags_nf_we~1_combout & (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ), + .datab(\z80_|execute_|ctl_flags_nf_we~1_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 .lut_mask = 16'h0400; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_we~4_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & ((\z80_|pla_decode_|Equal11~0_combout ) # (\z80_|pla_decode_|Equal10~0_combout )))) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|pla_decode_|Equal10~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_we~4 .lut_mask = 16'h8880; +defparam \z80_|execute_|ctl_flags_cf2_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y18_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_we~2_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~38_combout ) # (!\z80_|execute_|ctl_alu_op1_sel_bus~8_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~38_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_we~2 .lut_mask = 16'hCFFF; +defparam \z80_|execute_|ctl_flags_cf2_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf2_we~3_combout = (\z80_|execute_|ctl_flags_cf2_we~4_combout ) # ((\z80_|execute_|ctl_flags_cf2_we~2_combout ) # ((\z80_|execute_|ixy_d~15_combout & \z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(\z80_|execute_|ctl_flags_cf2_we~4_combout ), + .datab(\z80_|execute_|ixy_d~15_combout ), + .datac(\z80_|sequencer_|DFFE_T3_ff~q ), + .datad(\z80_|execute_|ctl_flags_cf2_we~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf2_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf2_we~3 .lut_mask = 16'hFFEA; +defparam \z80_|execute_|ctl_flags_cf2_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y15_N13 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N8 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_32 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_32~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout & \z80_|reg_control_|reg_sel_af~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datac(gnd), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_32~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_32 .lut_mask = 16'h4400; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y15_N21 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X35_Y15_N27 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~81 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~81_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (\z80_|reg_file_|b2v_latch_wz_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (((\z80_|reg_file_|b2v_latch_sp_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .datab(\z80_|reg_file_|b2v_latch_wz_hi|latch [6]), + .datac(\z80_|reg_file_|b2v_latch_sp_hi|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~81_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~81 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[6]~81 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N22 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~8 ( +// Equation(s): +// \z80_|alu_|db_high[2]~8_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[7]~12_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[5]~24_combout )) + + .dataa(gnd), + .datab(\z80_|alu_|db[5]~24_combout ), + .datac(\z80_|alu_|db[7]~12_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|alu_|db_high[2]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[2]~8 .lut_mask = 16'hF0CC; +defparam \z80_|alu_|db_high[2]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N28 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~9 ( +// Equation(s): +// \z80_|alu_|db_high[2]~9_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_high[2]~8_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[6]~22_combout ))) # +// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) + + .dataa(\z80_|alu_|db[6]~22_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datac(\z80_|alu_|db_high[2]~8_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[2]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[2]~9 .lut_mask = 16'hF3BB; +defparam \z80_|alu_|db_high[2]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N14 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~11 ( +// Equation(s): +// \z80_|alu_|db_high[2]~11_combout = (\z80_|bus_control_|db[4]~19_combout & (!\z80_|bus_control_|db[3]~21_combout & \z80_|bus_control_|db[5]~15_combout )) + + .dataa(gnd), + .datab(\z80_|bus_control_|db[4]~19_combout ), + .datac(\z80_|bus_control_|db[3]~21_combout ), + .datad(\z80_|bus_control_|db[5]~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[2]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[2]~11 .lut_mask = 16'h0C00; +defparam \z80_|alu_|db_high[2]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N18 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[2] ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_high|Q [2] = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & (\z80_|alu_|db_high[2]~13_combout & \z80_|execute_|ctl_alu_op1_sel_bus~15_combout )) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .datab(gnd), + .datac(\z80_|alu_|db_high[2]~13_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [2]), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[2] .lut_mask = 16'h5000; +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y17_N19 +dffeas \z80_|alu_|op1_high[2] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [2]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_high [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_high[2] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_high[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_lq ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_lq~combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ixy_d~7_combout ) # ((\z80_|execute_|ixy_d~6_combout & !\z80_|ir_|opcode [3])))) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_lq .lut_mask = 16'h88A8; +defparam \z80_|execute_|ctl_alu_op2_sel_lq .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N6 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & \z80_|alu_|db_low[2]~23_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datad(\z80_|alu_|db_low[2]~23_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2 .lut_mask = 16'hF000; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~5_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|execute_|ctl_alu_core_R~0_combout & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T3_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datad(\z80_|execute_|ctl_alu_core_R~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~5 .lut_mask = 16'hFEF0; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~6_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~5_combout ) # ((\z80_|execute_|ctl_alu_op_low~47_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~14_combout & \z80_|pla_decode_|Equal13~2_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~5_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~47_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~6 .lut_mask = 16'hFFEA; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~7_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~4_combout & (\z80_|execute_|ctl_reg_use_sp~0_combout & \z80_|execute_|nextM~11_combout )) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_use_sp~0_combout ), + .datad(\z80_|execute_|nextM~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~7 .lut_mask = 16'hA000; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y19_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_bus~8_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ) # (((!\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ) # (!\z80_|execute_|ctl_alu_op1_sel_bus~14_combout )) # (!\z80_|execute_|ctl_alu_op2_sel_bus~10_combout )) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_bus~8 .lut_mask = 16'hBFFF; +defparam \z80_|execute_|ctl_alu_op2_sel_bus~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y19_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_zero ( +// Equation(s): +// \z80_|execute_|ctl_alu_op2_sel_zero~combout = (((\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ) # (!\z80_|execute_|ctl_alu_shift_oe~38_combout )) # (!\z80_|execute_|ctl_reg_out_hi~4_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ), + .datab(\z80_|execute_|ctl_reg_out_hi~4_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~38_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op2_sel_zero .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_alu_op2_sel_zero .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N10 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2_combout ) # ((\z80_|alu_|db_high[2]~13_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) + + .dataa(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2_combout ), + .datab(\z80_|alu_|db_high[2]~13_combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 .lut_mask = 16'h00EA; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N0 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|ena ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|ena~combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout ) # ((\z80_|execute_|ctl_alu_op2_sel_zero~combout ) # (\z80_|execute_|ctl_alu_op2_sel_bus~8_combout )) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|ena .lut_mask = 16'hFEFE; +defparam \z80_|alu_|b2v_op2_latch_mux_high|ena .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y18_N11 +dffeas \z80_|alu_|op2_high[2] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_high [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_high[2] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_high[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N28 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~10 ( +// Equation(s): +// \z80_|alu_|db_high[2]~10_combout = (\z80_|alu_|op1_high [2] & (((\z80_|alu_|op2_high [2]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|alu_|op1_high [2] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_high [2]) # +// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) + + .dataa(\z80_|alu_|op1_high [2]), + .datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datac(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datad(\z80_|alu_|op2_high [2]), + .cin(gnd), + .combout(\z80_|alu_|db_high[2]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[2]~10 .lut_mask = 16'hBB0B; +defparam \z80_|alu_|db_high[2]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N16 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~12 ( +// Equation(s): +// \z80_|alu_|db_high[2]~12_combout = (\z80_|alu_|db_high[2]~9_combout & (\z80_|alu_|db_high[2]~10_combout & ((\z80_|alu_|db_high[2]~11_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~combout )))) + + .dataa(\z80_|alu_|db_high[2]~9_combout ), + .datab(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datac(\z80_|alu_|db_high[2]~11_combout ), + .datad(\z80_|alu_|db_high[2]~10_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[2]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[2]~12 .lut_mask = 16'hA200; +defparam \z80_|alu_|db_high[2]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N6 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~1 ( +// Equation(s): +// \z80_|alu_|db_high[3]~1_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout ) # (\z80_|alu_|db_high[3]~0_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datac(gnd), + .datad(\z80_|alu_|db_high[3]~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~1 .lut_mask = 16'hFFCC; +defparam \z80_|alu_|db_high[3]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N0 +cycloneive_lcell_comb \z80_|alu_|db_high[2]~13 ( +// Equation(s): +// \z80_|alu_|db_high[2]~13_combout = ((\z80_|alu_|db_high[2]~12_combout & ((\z80_|execute_|ctl_alu_res_oe~3_combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout )))) # (!\z80_|alu_|db_high[3]~1_combout ) + + .dataa(\z80_|execute_|ctl_alu_res_oe~3_combout ), + .datab(\z80_|alu_|db_high[2]~12_combout ), + .datac(\z80_|alu_|db_high[3]~1_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[2]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[2]~13 .lut_mask = 16'hCF8F; +defparam \z80_|alu_|db_high[2]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y12_N29 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X31_Y12_N19 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~78 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~78_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (\z80_|reg_file_|b2v_latch_ix_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [6]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_iy_lo|latch [6]), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~78_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~78 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[6]~78 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y16_N26 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout = (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & \z80_|execute_|ctl_reg_gp_sel[1]~31_combout ))) + + .dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y12_N5 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~79 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~79_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [6] & ((\z80_|alu_control_|db[6]~22_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|alu_control_|db[6]~22_combout ) # ((!\z80_|execute_|ctl_reg_in_lo~8_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datab(\z80_|alu_control_|db[6]~22_combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [6]), + .datad(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~79_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~79 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[6]~79 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N10 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_34 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_34~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_af~0_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~35_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(gnd), + .datac(\z80_|reg_control_|reg_sel_af~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_34 .lut_mask = 16'h5000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N18 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder_combout = \z80_|reg_file_|gdfx_temp0[6]~82_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N0 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_35 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_35~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_af~0_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~35_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(gnd), + .datac(\z80_|reg_control_|reg_sel_af~0_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_35 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y13_N19 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N14 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_31 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_31~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout & \z80_|reg_control_|reg_sel_af2~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .datac(\z80_|reg_control_|reg_sel_af2~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_31 .lut_mask = 16'h8080; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y13_N21 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N28 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_30 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_30~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout & \z80_|reg_control_|reg_sel_af2~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .datac(\z80_|reg_control_|reg_sel_af2~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_30 .lut_mask = 16'h4040; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~75 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~75_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (\z80_|reg_file_|b2v_latch_af_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_af2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (((\z80_|reg_file_|b2v_latch_af2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datab(\z80_|reg_file_|b2v_latch_af_lo|latch [6]), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~75_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~75 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp0[6]~75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N20 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder_combout = \z80_|reg_file_|gdfx_temp0[6]~82_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y14_N21 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X32_Y14_N31 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~76 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~76_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [6]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [6]), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~76_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~76 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[6]~76 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y13_N21 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~77 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~77_combout = (\z80_|reg_file_|gdfx_temp0[6]~76_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[6]~76_combout ), + .datab(gnd), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~77_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~77 .lut_mask = 16'hA0AA; +defparam \z80_|reg_file_|gdfx_temp0[6]~77 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~80 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~80_combout = (\z80_|reg_file_|gdfx_temp0[6]~78_combout & (\z80_|reg_file_|gdfx_temp0[6]~79_combout & (\z80_|reg_file_|gdfx_temp0[6]~75_combout & \z80_|reg_file_|gdfx_temp0[6]~77_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[6]~78_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[6]~79_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[6]~75_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[6]~77_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~80 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[6]~80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y12_N1 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y12_N3 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~74 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~74_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (\z80_|reg_file_|b2v_latch_hl_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl_lo|latch [6]), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~74_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~74 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp0[6]~74 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y11_N13 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y11_N11 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~73 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~73_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [6] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [6] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [6]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~73_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~73 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp0[6]~73 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~81 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~81_combout = (\z80_|reg_file_|gdfx_temp0[6]~80_combout & (\z80_|reg_file_|gdfx_temp0[6]~74_combout & \z80_|reg_file_|gdfx_temp0[6]~73_combout )) + + .dataa(\z80_|reg_file_|gdfx_temp0[6]~80_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[6]~74_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[6]~73_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~81_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~81 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|gdfx_temp0[6]~81 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~19 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~19_combout = (\z80_|execute_|ctl_sw_4u~6_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ) # (\z80_|execute_|ctl_reg_in_lo~8_combout ))) + + .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datad(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~19 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp0[0]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~18 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~18_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~18 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp0[0]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~20 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~20_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ) # ((\z80_|reg_file_|gdfx_temp0[0]~19_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ) # (\z80_|reg_file_|gdfx_temp0[0]~18_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~19_combout ), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~18_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~20 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp0[0]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~92 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~92_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout & (!\z80_|execute_|ctl_reg_gp_we~8_combout & ((\z80_|reg_control_|reg_sel_hl2~0_combout ) # (\z80_|reg_control_|reg_sel_hl~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .datab(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .datac(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datad(\z80_|reg_control_|reg_sel_hl~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~92_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~92 .lut_mask = 16'h0A08; +defparam \z80_|reg_file_|gdfx_temp0[0]~92 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~21 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~21_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ) # ((\z80_|reg_file_|gdfx_temp0[0]~20_combout ) # (\z80_|reg_file_|gdfx_temp0[0]~92_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datac(\z80_|reg_file_|gdfx_temp0[0]~20_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~92_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~21 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|gdfx_temp0[0]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N4 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_74 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_74~combout = (\z80_|reg_control_|reg_sel_pc~combout & (!\z80_|reg_control_|reg_sys_we_lo~combout & \z80_|execute_|ctl_reg_sys_hilo[0]~31_combout )) + + .dataa(\z80_|reg_control_|reg_sel_pc~combout ), + .datab(gnd), + .datac(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_74 .lut_mask = 16'h0A00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_74 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N6 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_62 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_62~combout = (\z80_|execute_|ctl_reg_sys_hilo[0]~31_combout & (!\z80_|reg_control_|reg_sys_we_lo~combout & \z80_|execute_|ctl_reg_sel_ir~1_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~31_combout ), + .datac(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datad(\z80_|execute_|ctl_reg_sel_ir~1_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_62 .lut_mask = 16'h0C00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N26 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~2 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[0]~2_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ) # ((\z80_|execute_|ctl_sw_4d~6_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~43_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .datab(\z80_|execute_|ctl_sw_4d~6_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[0]~2 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|db_lo_as[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y12_N13 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[4]~15_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X31_Y12_N9 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X32_Y12_N3 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~55 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~55_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_sp_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_iy_lo|latch [4]), + .datad(\z80_|reg_file_|b2v_latch_sp_lo|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~55_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~55 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[4]~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y12_N23 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~56 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~56_combout = (\z80_|reg_file_|gdfx_temp0[4]~55_combout & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|gdfx_temp0[4]~55_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~56_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~56 .lut_mask = 16'hC0CC; +defparam \z80_|reg_file_|gdfx_temp0[4]~56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y12_N13 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y12_N23 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~57 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~57_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [4] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [4] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [4]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~57_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~57 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp0[4]~57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y14_N5 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X32_Y14_N11 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~59 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~59_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [4]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [4]), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~59_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~59 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[4]~59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y13_N17 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X31_Y13_N31 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~58 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~58_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (\z80_|reg_file_|b2v_latch_af_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_af2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (((\z80_|reg_file_|b2v_latch_af2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datab(\z80_|reg_file_|b2v_latch_af_lo|latch [4]), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~58_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~58 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp0[4]~58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y13_N1 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~60 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~60_combout = (\z80_|reg_file_|gdfx_temp0[4]~59_combout & (\z80_|reg_file_|gdfx_temp0[4]~58_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp0[4]~59_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[4]~58_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~60_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~60 .lut_mask = 16'h8088; +defparam \z80_|reg_file_|gdfx_temp0[4]~60 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y11_N23 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X31_Y11_N17 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~53 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~53_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [4]), + .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~53_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~53 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[4]~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~54 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~54_combout = (\z80_|reg_file_|gdfx_temp0[4]~53_combout & ((\z80_|alu_control_|db[4]~32_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) + + .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datab(gnd), + .datac(\z80_|alu_control_|db[4]~32_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[4]~53_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~54_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~54 .lut_mask = 16'hF500; +defparam \z80_|reg_file_|gdfx_temp0[4]~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~61 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~61_combout = (\z80_|reg_file_|gdfx_temp0[4]~56_combout & (\z80_|reg_file_|gdfx_temp0[4]~57_combout & (\z80_|reg_file_|gdfx_temp0[4]~60_combout & \z80_|reg_file_|gdfx_temp0[4]~54_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[4]~56_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[4]~57_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[4]~60_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[4]~54_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~61 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[4]~61 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~62 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[4]~62_combout = ((\z80_|reg_file_|gdfx_temp0[4]~61_combout & ((\z80_|reg_file_|db_lo_as[4]~15_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp0[4]~61_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .datac(\z80_|execute_|ctl_sw_4u~6_combout ), + .datad(\z80_|reg_file_|db_lo_as[4]~15_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[4]~62 .lut_mask = 16'hBB3B; +defparam \z80_|reg_file_|gdfx_temp0[4]~62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N10 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_75 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_75~combout = (\z80_|reg_control_|reg_sel_pc~combout & (\z80_|reg_control_|reg_sys_we_lo~combout & \z80_|execute_|ctl_reg_sys_hilo[0]~31_combout )) + + .dataa(\z80_|reg_control_|reg_sel_pc~combout ), + .datab(gnd), + .datac(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[0]~31_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_75 .lut_mask = 16'hA000; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y12_N3 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[4]~15_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N2 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~13 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[4]~13_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[4]~62_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # +// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[4]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[4]~13 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_lo_as[4]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N18 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~14 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[4]~14_combout = (\z80_|reg_file_|db_lo_as[4]~13_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_ir_lo|latch [4]), + .datab(\z80_|reg_file_|db_lo_as[4]~13_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[4]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[4]~14 .lut_mask = 16'h88CC; +defparam \z80_|reg_file_|db_lo_as[4]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N16 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout = \z80_|address_latch_|Q [4] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|address_latch_|Q [4]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out .lut_mask = 16'h0FF0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N12 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~15 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[4]~15_combout = ((\z80_|reg_file_|db_lo_as[4]~14_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .datab(\z80_|reg_file_|db_lo_as[4]~14_combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), + .datad(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[4]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[4]~15 .lut_mask = 16'hC4FF; +defparam \z80_|reg_file_|db_lo_as[4]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N12 +cycloneive_lcell_comb \z80_|address_latch_|abusz[4] ( +// Equation(s): +// \z80_|address_latch_|abusz [4] = (\z80_|reg_file_|db_lo_as[4]~15_combout & !\z80_|resets_|clrpc~0_combout ) + + .dataa(gnd), + .datab(\z80_|reg_file_|db_lo_as[4]~15_combout ), + .datac(gnd), + .datad(\z80_|resets_|clrpc~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [4]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[4] .lut_mask = 16'h00CC; +defparam \z80_|address_latch_|abusz[4] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y10_N13 +dffeas \z80_|address_latch_|Q[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [4]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[4] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N20 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout = \z80_|address_latch_|Q [5] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout & (\z80_|execute_|ctl_inc_dec~11_combout $ (\z80_|address_latch_|Q +// [4]))))) + + .dataa(\z80_|execute_|ctl_inc_dec~11_combout ), + .datab(\z80_|address_latch_|Q [4]), + .datac(\z80_|address_latch_|Q [5]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out .lut_mask = 16'h96F0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y12_N29 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[5]~18_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y12_N17 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y12_N15 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~64 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~64_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [5] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [5] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [5]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~64_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~64 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp0[5]~64 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y11_N27 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X31_Y11_N25 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~63 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~63_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [5]), + .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [5]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~63_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~63 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[5]~63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y11_N17 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N18 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[5]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_lo|latch[5]~feeder_combout = \z80_|reg_file_|gdfx_temp0[5]~72_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[5]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y11_N19 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_af_lo|latch[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~65 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~65_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [5]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [5]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~65_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~65 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[5]~65 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y12_N21 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X32_Y12_N23 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~69 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~69_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [5]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_iy_lo|latch [5]), + .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~69_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~69 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[5]~69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y13_N29 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X32_Y14_N27 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~68 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~68_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (\z80_|reg_file_|b2v_latch_ix_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_ix_lo|latch [5]), + .datac(\z80_|reg_file_|b2v_latch_bc_lo|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~68_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~68 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp0[5]~68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y13_N3 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X32_Y14_N17 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~66 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~66_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [5] & ((\z80_|alu_control_|db[5]~15_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|alu_control_|db[5]~15_combout ) # ((!\z80_|execute_|ctl_reg_in_lo~8_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datab(\z80_|alu_control_|db[5]~15_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [5]), + .datad(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~66_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~66 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[5]~66 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~67 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~67_combout = (\z80_|reg_file_|gdfx_temp0[5]~66_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [5]), + .datad(\z80_|reg_file_|gdfx_temp0[5]~66_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~67_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~67 .lut_mask = 16'hF300; +defparam \z80_|reg_file_|gdfx_temp0[5]~67 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~70 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~70_combout = (\z80_|reg_file_|gdfx_temp0[5]~65_combout & (\z80_|reg_file_|gdfx_temp0[5]~69_combout & (\z80_|reg_file_|gdfx_temp0[5]~68_combout & \z80_|reg_file_|gdfx_temp0[5]~67_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[5]~65_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[5]~69_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[5]~68_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[5]~67_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~70_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~70 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[5]~70 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~71 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~71_combout = (\z80_|reg_file_|gdfx_temp0[5]~64_combout & (\z80_|reg_file_|gdfx_temp0[5]~63_combout & \z80_|reg_file_|gdfx_temp0[5]~70_combout )) + + .dataa(\z80_|reg_file_|gdfx_temp0[5]~64_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[5]~63_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[5]~70_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~71 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|gdfx_temp0[5]~71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~72 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[5]~72_combout = ((\z80_|reg_file_|gdfx_temp0[5]~71_combout & ((\z80_|reg_file_|db_lo_as[5]~18_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp0[5]~71_combout ), + .datab(\z80_|reg_file_|db_lo_as[5]~18_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .datad(\z80_|execute_|ctl_sw_4u~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[5]~72 .lut_mask = 16'h8FAF; +defparam \z80_|reg_file_|gdfx_temp0[5]~72 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y12_N7 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[5]~18_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N6 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~16 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[5]~16_combout = (\z80_|reg_file_|gdfx_temp0[5]~72_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # (!\z80_|reg_file_|gdfx_temp0[5]~72_combout & +// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .datab(\z80_|execute_|ctl_sw_4d~6_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[5]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[5]~16 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|db_lo_as[5]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N14 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~17 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[5]~17_combout = (\z80_|reg_file_|db_lo_as[5]~16_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|b2v_latch_ir_lo|latch [5]), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .datad(\z80_|reg_file_|db_lo_as[5]~16_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[5]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[5]~17 .lut_mask = 16'hCF00; +defparam \z80_|reg_file_|db_lo_as[5]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N28 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~18 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[5]~18_combout = ((\z80_|reg_file_|db_lo_as[5]~17_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), + .datac(\z80_|reg_file_|db_lo_as[5]~17_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[5]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[5]~18 .lut_mask = 16'hD5F5; +defparam \z80_|reg_file_|db_lo_as[5]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N8 +cycloneive_lcell_comb \z80_|address_latch_|abusz[5] ( +// Equation(s): +// \z80_|address_latch_|abusz [5] = (\z80_|reg_file_|db_lo_as[5]~18_combout & !\z80_|resets_|clrpc~0_combout ) + + .dataa(gnd), + .datab(\z80_|reg_file_|db_lo_as[5]~18_combout ), + .datac(gnd), + .datad(\z80_|resets_|clrpc~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [5]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[5] .lut_mask = 16'h00CC; +defparam \z80_|address_latch_|abusz[5] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y10_N9 +dffeas \z80_|address_latch_|Q[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [5]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[5] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~10 ( +// Equation(s): +// \z80_|execute_|ctl_inc_dec~10_combout = (\z80_|execute_|ctl_inc_dec~9_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_inc_dec~6_combout ), + .datad(\z80_|execute_|ctl_inc_dec~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_dec~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_dec~10 .lut_mask = 16'hFF0F; +defparam \z80_|execute_|ctl_inc_dec~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N30 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout = \z80_|address_latch_|Q [5] $ ((((\z80_|execute_|ctl_inc_dec~10_combout ) # (!\z80_|execute_|ctl_inc_dec~5_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~42_combout ))) + + .dataa(\z80_|address_latch_|Q [5]), + .datab(\z80_|execute_|ctl_bus_inc_oe~42_combout ), + .datac(\z80_|execute_|ctl_inc_dec~10_combout ), + .datad(\z80_|execute_|ctl_inc_dec~5_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4 .lut_mask = 16'h5955; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N8 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout = \z80_|address_latch_|Q [4] $ ((((\z80_|execute_|ctl_inc_dec~10_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~42_combout )) # (!\z80_|execute_|ctl_inc_dec~5_combout ))) + + .dataa(\z80_|execute_|ctl_inc_dec~5_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~42_combout ), + .datac(\z80_|execute_|ctl_inc_dec~10_combout ), + .datad(\z80_|address_latch_|Q [4]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 .lut_mask = 16'h08F7; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N20 +cycloneive_lcell_comb \z80_|address_latch_|abusz[6] ( +// Equation(s): +// \z80_|address_latch_|abusz [6] = (\z80_|reg_file_|db_lo_as[6]~21_combout & !\z80_|resets_|clrpc~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|reg_file_|db_lo_as[6]~21_combout ), + .datad(\z80_|resets_|clrpc~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [6]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[6] .lut_mask = 16'h00F0; +defparam \z80_|address_latch_|abusz[6] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y10_N21 +dffeas \z80_|address_latch_|Q[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [6]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[6] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N20 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[6] ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|address [6] = \z80_|address_latch_|Q [6] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout & +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout )))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), + .datac(\z80_|address_latch_|Q [6]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[6] .lut_mask = 16'h78F0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[6] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y12_N25 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[6]~21_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X36_Y12_N11 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[6]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N10 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~19 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[6]~19_combout = (\z80_|reg_file_|gdfx_temp0[6]~82_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # (!\z80_|reg_file_|gdfx_temp0[6]~82_combout & +// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .datab(\z80_|execute_|ctl_sw_4d~6_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[6]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[6]~19 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|db_lo_as[6]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N22 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~20 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[6]~20_combout = (\z80_|reg_file_|db_lo_as[6]~19_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|b2v_latch_ir_lo|latch [6]), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .datad(\z80_|reg_file_|db_lo_as[6]~19_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[6]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[6]~20 .lut_mask = 16'hCF00; +defparam \z80_|reg_file_|db_lo_as[6]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N24 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~21 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[6]~21_combout = ((\z80_|reg_file_|db_lo_as[6]~20_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [6]) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), + .datac(\z80_|reg_file_|db_lo_as[6]~20_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[6]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[6]~21 .lut_mask = 16'hD5F5; +defparam \z80_|reg_file_|db_lo_as[6]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~82 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[6]~82_combout = ((\z80_|reg_file_|gdfx_temp0[6]~81_combout & ((\z80_|reg_file_|db_lo_as[6]~21_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[6]~81_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .datad(\z80_|reg_file_|db_lo_as[6]~21_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[6]~82 .lut_mask = 16'hCF4F; +defparam \z80_|reg_file_|gdfx_temp0[6]~82 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N10 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[6]~0 ( +// Equation(s): +// \z80_|reg_file_|db_lo_ds[6]~0_combout = (\z80_|reg_file_|gdfx_temp0[6]~82_combout ) # ((!\z80_|execute_|ctl_reg_out_lo~5_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout & \z80_|execute_|ctl_reg_out_lo~7_combout ))) + + .dataa(\z80_|execute_|ctl_reg_out_lo~5_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[6]~82_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_ds[6]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_ds[6]~0 .lut_mask = 16'hFF40; +defparam \z80_|reg_file_|db_lo_ds[6]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N28 +cycloneive_lcell_comb \z80_|sw1_|db_down[6]~1 ( +// Equation(s): +// \z80_|sw1_|db_down[6]~1_combout = ((\z80_|bus_control_|db[6]~9_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ) + + .dataa(gnd), + .datab(\z80_|bus_control_|db[6]~9_combout ), + .datac(\z80_|execute_|ctl_sw_1d~7_combout ), + .datad(\z80_|execute_|ctl_sw_mask543_en~0_combout ), + .cin(gnd), + .combout(\z80_|sw1_|db_down[6]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sw1_|db_down[6]~1 .lut_mask = 16'h0FCF; +defparam \z80_|sw1_|db_down[6]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_66_oe ( +// Equation(s): +// \z80_|execute_|ctl_66_oe~combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & \z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(\z80_|pla_decode_|Equal47~0_combout ), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_66_oe~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_66_oe .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_66_oe .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N24 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[1] ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_high|Q [1] = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & \z80_|alu_|db_high[1]~19_combout )) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .datad(\z80_|alu_|db_high[1]~19_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [1]), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[1] .lut_mask = 16'h0A00; +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[1] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y17_N25 +dffeas \z80_|alu_|op1_high[1] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [1]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_high [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_high[1] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_high[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N8 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~4 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~4_combout = (\z80_|alu_|db_low[1]~12_combout & \z80_|execute_|ctl_alu_op2_sel_lq~combout ) + + .dataa(gnd), + .datab(\z80_|alu_|db_low[1]~12_combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~4 .lut_mask = 16'hC0C0; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N16 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~4_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~8_combout & \z80_|alu_|db_high[1]~19_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .datab(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~4_combout ), + .datac(\z80_|alu_|db_high[1]~19_combout ), + .datad(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5 .lut_mask = 16'h00EC; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y18_N17 +dffeas \z80_|alu_|op2_high[1] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_high [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_high[1] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_high[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N18 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~2 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~2_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [1]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [1])))) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datab(\z80_|alu_|op1_high [1]), + .datac(\z80_|execute_|ctl_alu_op_low~combout ), + .datad(\z80_|alu_|op1_low [1]), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~2 .lut_mask = 16'hA808; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N14 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~3 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~3_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~2_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~8_combout & \z80_|alu_|db_low[1]~12_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datac(\z80_|alu_|db_low[1]~12_combout ), + .datad(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~3 .lut_mask = 16'h3320; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y18_N15 +dffeas \z80_|alu_|op2_low[1] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_low [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_low[1] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_low[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N16 +cycloneive_lcell_comb \z80_|alu_|alu_op2[1]~1 ( +// Equation(s): +// \z80_|alu_|alu_op2[1]~1_combout = \z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_high [1])) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_low [1]))))) + + .dataa(\z80_|alu_|op2_high [1]), + .datab(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), + .datad(\z80_|alu_|op2_low [1]), + .cin(gnd), + .combout(\z80_|alu_|alu_op2[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op2[1]~1 .lut_mask = 16'h4B78; +defparam \z80_|alu_|alu_op2[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N0 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout = (!\z80_|alu_|alu_op2[1]~1_combout & ((\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_low [1])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_high +// [1]))))) + + .dataa(\z80_|alu_|op1_low [1]), + .datab(\z80_|alu_|op1_high [1]), + .datac(\z80_|execute_|ctl_alu_op_low~combout ), + .datad(\z80_|alu_|alu_op2[1]~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'h0053; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N30 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout = (\z80_|alu_|alu_op2[1]~1_combout & ((\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [1])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [1]))))) + + .dataa(\z80_|alu_|op1_low [1]), + .datab(\z80_|alu_|op1_high [1]), + .datac(\z80_|execute_|ctl_alu_op_low~combout ), + .datad(\z80_|alu_|alu_op2[1]~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0 .lut_mask = 16'hAC00; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N14 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout = (\z80_|execute_|ctl_alu_core_S~combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_core_S~combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'hFFF0; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y20_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~5_combout = (\z80_|execute_|ctl_alu_core_S~8_combout & (\z80_|execute_|ctl_alu_core_R~4_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout & !\z80_|pla_decode_|Equal72~2_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_S~8_combout ), + .datab(\z80_|execute_|ctl_alu_core_R~4_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ), + .datad(\z80_|pla_decode_|Equal72~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~5 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_alu_core_R~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~2 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~2_combout = (\z80_|execute_|ctl_mWrite~4_combout & (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal8~0_combout ) # (\z80_|pla_decode_|Equal55~0_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~4_combout ), + .datab(\z80_|pla_decode_|Equal8~0_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R~2 .lut_mask = 16'hA080; +defparam \z80_|execute_|ctl_alu_core_R~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y20_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_R~combout = (((\z80_|pla_decode_|Equal73~2_combout ) # (\z80_|execute_|ctl_alu_core_R~2_combout )) # (!\z80_|execute_|ctl_alu_core_S~9_combout )) # (!\z80_|execute_|ctl_alu_core_R~4_combout ) + + .dataa(\z80_|execute_|ctl_alu_core_R~4_combout ), + .datab(\z80_|execute_|ctl_alu_core_S~9_combout ), + .datac(\z80_|pla_decode_|Equal73~2_combout ), + .datad(\z80_|execute_|ctl_alu_core_R~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_R~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_R .lut_mask = 16'hFFF7; +defparam \z80_|execute_|ctl_alu_core_R .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N8 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~20 ( +// Equation(s): +// \z80_|alu_|db_high[0]~20_combout = ((!\z80_|bus_control_|db[3]~21_combout & (\z80_|bus_control_|db[5]~15_combout & !\z80_|bus_control_|db[4]~19_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) + + .dataa(\z80_|bus_control_|db[3]~21_combout ), + .datab(\z80_|bus_control_|db[5]~15_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datad(\z80_|bus_control_|db[4]~19_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~20 .lut_mask = 16'h0F4F; +defparam \z80_|alu_|db_high[0]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N26 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[0] ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_high|Q [0] = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & \z80_|alu_|db_high[0]~25_combout )) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .datad(\z80_|alu_|db_high[0]~25_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [0]), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[0] .lut_mask = 16'h0A00; +defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[0] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y17_N27 +dffeas \z80_|alu_|op1_high[0] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_high|Q [0]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_high [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_high[0] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_high[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N30 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~21 ( +// Equation(s): +// \z80_|alu_|db_high[0]~21_combout = (\z80_|execute_|ctl_alu_op1_oe~1_combout & (\z80_|alu_|op1_high [0] & ((\z80_|alu_|op2_high [0]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout & (((\z80_|alu_|op2_high +// [0]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datab(\z80_|alu_|op1_high [0]), + .datac(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datad(\z80_|alu_|op2_high [0]), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~21 .lut_mask = 16'hDD0D; +defparam \z80_|alu_|db_high[0]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N2 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~22 ( +// Equation(s): +// \z80_|alu_|db_high[0]~22_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[5]~24_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[3]~20_combout )) + + .dataa(gnd), + .datab(\z80_|alu_|db[3]~20_combout ), + .datac(\z80_|alu_|db[5]~24_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~22 .lut_mask = 16'hF0CC; +defparam \z80_|alu_|db_high[0]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N20 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~23 ( +// Equation(s): +// \z80_|alu_|db_high[0]~23_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_high[0]~22_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[4]~18_combout )) + + .dataa(\z80_|alu_|db[4]~18_combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .datac(gnd), + .datad(\z80_|alu_|db_high[0]~22_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~23 .lut_mask = 16'hEE22; +defparam \z80_|alu_|db_high[0]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N26 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~24 ( +// Equation(s): +// \z80_|alu_|db_high[0]~24_combout = (\z80_|alu_|db_high[0]~20_combout & (\z80_|alu_|db_high[0]~21_combout & ((\z80_|alu_|db_high[0]~23_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) + + .dataa(\z80_|alu_|db_high[0]~20_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datac(\z80_|alu_|db_high[0]~21_combout ), + .datad(\z80_|alu_|db_high[0]~23_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~24 .lut_mask = 16'hA020; +defparam \z80_|alu_|db_high[0]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N4 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~4 ( +// Equation(s): +// \z80_|alu_|db_low[0]~4_combout = ((!\z80_|bus_control_|db[3]~21_combout & (!\z80_|bus_control_|db[5]~15_combout & !\z80_|bus_control_|db[4]~19_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) + + .dataa(\z80_|bus_control_|db[3]~21_combout ), + .datab(\z80_|bus_control_|db[5]~15_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datad(\z80_|bus_control_|db[4]~19_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~4 .lut_mask = 16'h0F1F; +defparam \z80_|alu_|db_low[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y18_N27 +dffeas \z80_|alu_|result_lo[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_alu_op_low~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|result_lo [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|result_lo[0] .is_wysiwyg = "true"; +defparam \z80_|alu_|result_lo[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N20 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~2 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~2_combout = (\z80_|alu_|db_low[0]~24_combout & ((\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ) # ((\z80_|alu_|db_high[0]~25_combout & \z80_|execute_|ctl_alu_op1_sel_low~combout )))) # +// (!\z80_|alu_|db_low[0]~24_combout & (\z80_|alu_|db_high[0]~25_combout & ((\z80_|execute_|ctl_alu_op1_sel_low~combout )))) + + .dataa(\z80_|alu_|db_low[0]~24_combout ), + .datab(\z80_|alu_|db_high[0]~25_combout ), + .datac(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~2 .lut_mask = 16'hECA0; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N0 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~3 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~3_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .datad(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~3 .lut_mask = 16'h0F00; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y17_N1 +dffeas \z80_|alu_|op1_low[0] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_low [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_low[0] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_low[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N24 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~5 ( +// Equation(s): +// \z80_|alu_|db_low[0]~5_combout = (\z80_|execute_|ctl_alu_op1_oe~1_combout & (\z80_|alu_|op1_low [0] & ((\z80_|alu_|op2_low [0]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout & (((\z80_|alu_|op2_low [0]) # +// (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datab(\z80_|alu_|op1_low [0]), + .datac(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datad(\z80_|alu_|op2_low [0]), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~5 .lut_mask = 16'hDD0D; +defparam \z80_|alu_|db_low[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N26 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~6 ( +// Equation(s): +// \z80_|alu_|db_low[0]~6_combout = (\z80_|alu_|db_low[0]~4_combout & (\z80_|alu_|db_low[0]~5_combout & ((\z80_|execute_|ctl_alu_res_oe~3_combout ) # (\z80_|alu_|result_lo [0])))) + + .dataa(\z80_|execute_|ctl_alu_res_oe~3_combout ), + .datab(\z80_|alu_|db_low[0]~4_combout ), + .datac(\z80_|alu_|result_lo [0]), + .datad(\z80_|alu_|db_low[0]~5_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~6 .lut_mask = 16'hC800; +defparam \z80_|alu_|db_low[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N30 +cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~1 ( +// Equation(s): +// \z80_|alu_control_|b2v_inst_shift_mux|out~1_combout = (\z80_|ir_|opcode [5] & (\z80_|alu_|db[7]~12_combout & (\z80_|ir_|opcode [3]))) # (!\z80_|ir_|opcode [5] & ((\z80_|ir_|opcode [3] & ((\z80_|alu_|db[0]~14_combout ))) # (!\z80_|ir_|opcode [3] & +// (\z80_|alu_|db[7]~12_combout )))) + + .dataa(\z80_|alu_|db[7]~12_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|alu_|db[0]~14_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~1 .lut_mask = 16'hB282; +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_we~2_combout = (\z80_|execute_|ctl_flags_hf_we~5_combout & (\z80_|execute_|ctl_flags_xy_we~13_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_state_alu~6_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~6_combout ), + .datab(\z80_|execute_|ctl_flags_hf_we~5_combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~13_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_we~2 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_flags_hf_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~3_combout = (\z80_|execute_|ctl_flags_hf2_we~combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((!\z80_|execute_|ctl_flags_bus~1_combout ) # (!\z80_|execute_|ctl_flags_bus~0_combout )))) + + .dataa(\z80_|execute_|ctl_flags_bus~0_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|execute_|ctl_flags_hf2_we~combout ), + .datad(\z80_|execute_|ctl_flags_bus~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~3 .lut_mask = 16'hF4FC; +defparam \z80_|execute_|ctl_flags_cf_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~4_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # ((\z80_|execute_|ixy_d~6_combout & \z80_|execute_|ctl_mRead~34_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .datab(\z80_|execute_|ixy_d~6_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~4 .lut_mask = 16'hFFEA; +defparam \z80_|execute_|ctl_flags_cf_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~5 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~5_combout = ((\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # (\z80_|execute_|ctl_flags_cf_we~4_combout ))) # (!\z80_|execute_|ctl_flags_cf_we~7_combout ) + + .dataa(\z80_|execute_|ctl_flags_cf_we~7_combout ), + .datab(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .datad(\z80_|execute_|ctl_flags_cf_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~5 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_flags_cf_we~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_we~6_combout = (((\z80_|execute_|ctl_flags_cf_we~3_combout ) # (\z80_|execute_|ctl_flags_cf_we~5_combout )) # (!\z80_|execute_|ctl_flags_hf_we~2_combout )) # (!\z80_|execute_|ctl_flags_cf_we~2_combout ) + + .dataa(\z80_|execute_|ctl_flags_cf_we~2_combout ), + .datab(\z80_|execute_|ctl_flags_hf_we~2_combout ), + .datac(\z80_|execute_|ctl_flags_cf_we~3_combout ), + .datad(\z80_|execute_|ctl_flags_cf_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_we~6 .lut_mask = 16'hFFF7; +defparam \z80_|execute_|ctl_flags_cf_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N16 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~0 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf~0_combout = (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & (\z80_|execute_|ctl_flags_bus~combout & ((\z80_|alu_control_|db[0]~12_combout )))) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout +// & ((\z80_|execute_|ctl_flags_alu~15_combout ) # ((\z80_|execute_|ctl_flags_bus~combout & \z80_|alu_control_|db[0]~12_combout )))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), + .datab(\z80_|execute_|ctl_flags_bus~combout ), + .datac(\z80_|execute_|ctl_flags_alu~15_combout ), + .datad(\z80_|alu_control_|db[0]~12_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~0 .lut_mask = 16'hDC50; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N18 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~1 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf~1_combout = (\z80_|execute_|ctl_flags_cf_we~6_combout & ((\z80_|execute_|ctl_flags_cf2_we~3_combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf~q ))) # (!\z80_|execute_|ctl_flags_cf2_we~3_combout & +// (\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout )))) # (!\z80_|execute_|ctl_flags_cf_we~6_combout & (((\z80_|alu_flags_|DFFE_inst_latch_cf~q )))) + + .dataa(\z80_|execute_|ctl_flags_cf_we~6_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), + .datad(\z80_|execute_|ctl_flags_cf2_we~3_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~1 .lut_mask = 16'hF0D8; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y18_N19 +dffeas \z80_|alu_flags_|DFFE_inst_latch_cf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N4 +cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~0 ( +// Equation(s): +// \z80_|alu_control_|b2v_inst_shift_mux|out~0_combout = (\z80_|ir_|opcode [4] & ((\z80_|ir_|opcode [5] & ((!\z80_|ir_|opcode [3]))) # (!\z80_|ir_|opcode [5] & (\z80_|alu_flags_|DFFE_inst_latch_cf~q )))) + + .dataa(\z80_|ir_|opcode [4]), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~0 .lut_mask = 16'h20A8; +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N8 +cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~2 ( +// Equation(s): +// \z80_|alu_control_|b2v_inst_shift_mux|out~2_combout = (\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ) # ((\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout & !\z80_|ir_|opcode [4])) + + .dataa(\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ), + .datab(\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ), + .datac(\z80_|ir_|opcode [4]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~2 .lut_mask = 16'hCECE; +defparam \z80_|alu_control_|b2v_inst_shift_mux|out~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N14 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~2 ( +// Equation(s): +// \z80_|alu_|db_low[0]~2_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[1]~10_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ))) + + .dataa(\z80_|alu_|db[1]~10_combout ), + .datab(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), + .datac(gnd), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~2 .lut_mask = 16'hAACC; +defparam \z80_|alu_|db_low[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N20 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~3 ( +// Equation(s): +// \z80_|alu_|db_low[0]~3_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_low[0]~2_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[0]~14_combout )))) # +// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .datac(\z80_|alu_|db_low[0]~2_combout ), + .datad(\z80_|alu_|db[0]~14_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~3 .lut_mask = 16'hF7D5; +defparam \z80_|alu_|db_low[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N16 +cycloneive_lcell_comb \z80_|alu_|db_low[0]~24 ( +// Equation(s): +// \z80_|alu_|db_low[0]~24_combout = (\z80_|alu_|db_low[0]~6_combout & ((\z80_|alu_|db_low[0]~3_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~43_combout & !\z80_|alu_|db_high[3]~0_combout )))) # (!\z80_|alu_|db_low[0]~6_combout & +// (((!\z80_|execute_|ctl_alu_shift_oe~43_combout & !\z80_|alu_|db_high[3]~0_combout )))) + + .dataa(\z80_|alu_|db_low[0]~6_combout ), + .datab(\z80_|alu_|db_low[0]~3_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datad(\z80_|alu_|db_high[3]~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[0]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[0]~24 .lut_mask = 16'h888F; +defparam \z80_|alu_|db_low[0]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N2 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~0 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~0_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [0]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [0])))) + + .dataa(\z80_|execute_|ctl_alu_op_low~combout ), + .datab(\z80_|alu_|op1_high [0]), + .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datad(\z80_|alu_|op1_low [0]), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~0 .lut_mask = 16'hE040; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N4 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~1 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~1_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~0_combout ) # ((\z80_|alu_|db_low[0]~24_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) + + .dataa(\z80_|alu_|db_low[0]~24_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .datad(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~1 .lut_mask = 16'h3320; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y18_N5 +dffeas \z80_|alu_|op2_low[0] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_low [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_low[0] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_low[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N6 +cycloneive_lcell_comb \z80_|alu_|alu_op2[0]~3 ( +// Equation(s): +// \z80_|alu_|alu_op2[0]~3_combout = \z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_high [0])) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_low [0]))))) + + .dataa(\z80_|alu_|op2_high [0]), + .datab(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), + .datad(\z80_|alu_|op2_low [0]), + .cin(gnd), + .combout(\z80_|alu_|alu_op2[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op2[0]~3 .lut_mask = 16'h4B78; +defparam \z80_|alu_|alu_op2[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N0 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout = ((!\z80_|execute_|ctl_alu_core_S~combout & !\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout )) # (!\z80_|execute_|ctl_alu_core_R~5_combout ) + + .dataa(\z80_|execute_|ctl_alu_core_S~combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_core_R~5_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 .lut_mask = 16'h0F5F; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla26M3T5_8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla26M3T5_8~combout = (\z80_|sequencer_|DFFE_T5_ff~q & (\z80_|pla_decode_|Equal21~1_combout & \z80_|sequencer_|DFFE_M3_ff~q )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T5_ff~q ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla26M3T5_8~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla26M3T5_8 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla26M3T5_8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~14 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~14_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla26M3T5_8~combout ) # ((\z80_|sequencer_|DFFE_T3_ff~q & (!\z80_|sequencer_|DFFE_T2_ff~q & \z80_|execute_|ixy_d~15_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla26M3T5_8~combout ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|execute_|ixy_d~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~14 .lut_mask = 16'hCECC; +defparam \z80_|execute_|ctl_alu_core_hf~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~16 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~16_combout = ((\z80_|execute_|ctl_alu_core_hf~14_combout ) # (!\z80_|execute_|ctl_alu_core_hf~15_combout )) # (!\z80_|execute_|ctl_alu_core_hf~12_combout ) + + .dataa(\z80_|execute_|ctl_alu_core_hf~12_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_core_hf~15_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~16 .lut_mask = 16'hFF5F; +defparam \z80_|execute_|ctl_alu_core_hf~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~13 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~13_combout = (\z80_|pla_decode_|Equal21~1_combout & ((\z80_|execute_|ctl_mRead~9_combout ) # ((!\z80_|execute_|ixy_d~5_combout & \z80_|execute_|ixy_d~6_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|pla_decode_|Equal21~1_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ctl_mRead~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~13 .lut_mask = 16'hCC40; +defparam \z80_|execute_|ctl_alu_core_hf~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~17 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~17_combout = (\z80_|execute_|ctl_alu_core_hf~16_combout & (((\z80_|execute_|ctl_alu_core_hf~13_combout & !\z80_|execute_|ctl_alu_op_low~40_combout )) # (!\z80_|execute_|ctl_alu_op_low~41_combout ))) # +// (!\z80_|execute_|ctl_alu_core_hf~16_combout & (\z80_|execute_|ctl_alu_core_hf~13_combout & ((!\z80_|execute_|ctl_alu_op_low~40_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~16_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~13_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~41_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~40_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~17 .lut_mask = 16'h0ACE; +defparam \z80_|execute_|ctl_alu_core_hf~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y20_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~44 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~44_combout = (\z80_|execute_|ctl_alu_op_low~38_combout ) # ((\z80_|execute_|ctl_alu_op_low~42_combout ) # ((\z80_|execute_|ctl_alu_op_low~36_combout ) # (!\z80_|execute_|ctl_alu_op_low~31_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~38_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~42_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~31_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~36_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~44 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|ctl_alu_op_low~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~20 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~20_combout = (\z80_|execute_|ctl_mRead~34_combout & ((\z80_|execute_|ctl_mRead~9_combout ) # ((!\z80_|execute_|ixy_d~5_combout & \z80_|execute_|ixy_d~6_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ctl_mRead~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~20 .lut_mask = 16'hCC40; +defparam \z80_|execute_|ctl_alu_core_hf~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y17_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~21 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~21_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ) # ((\z80_|execute_|ctl_alu_core_hf~20_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|execute_|ctl_mRead~34_combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~21 .lut_mask = 16'hBFAA; +defparam \z80_|execute_|ctl_alu_core_hf~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~18 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~18_combout = (\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (((!\z80_|pla_decode_|Equal32~0_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal63~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal63~0_combout ), + .datab(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|pla_decode_|Equal32~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~18 .lut_mask = 16'h4CCC; +defparam \z80_|execute_|ctl_alu_core_hf~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~19 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~19_combout = (\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # ((\z80_|execute_|ctl_alu_core_hf~18_combout & !\z80_|execute_|ctl_flags_cf2_sel_daa~combout ))) + + .dataa(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~18_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~19 .lut_mask = 16'hEEFE; +defparam \z80_|execute_|ctl_alu_core_hf~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y20_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~22 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~22_combout = (\z80_|execute_|ctl_alu_op_low~37_combout & (!\z80_|execute_|ctl_alu_op_low~42_combout & ((\z80_|execute_|ctl_alu_core_hf~19_combout )))) # (!\z80_|execute_|ctl_alu_op_low~37_combout & +// ((\z80_|execute_|ctl_alu_core_hf~21_combout ) # ((!\z80_|execute_|ctl_alu_op_low~42_combout & \z80_|execute_|ctl_alu_core_hf~19_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~37_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~42_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~21_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~22 .lut_mask = 16'h7350; +defparam \z80_|execute_|ctl_alu_core_hf~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~43 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~43_combout = ((\z80_|execute_|ctl_alu_op_low~28_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ) # (!\z80_|execute_|ctl_state_alu~12_combout ))) # (!\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~28_combout ), + .datac(\z80_|execute_|ctl_state_alu~12_combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~43 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|ctl_alu_op_low~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y20_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~24 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~24_combout = (\z80_|execute_|ctl_state_alu~2_combout & (\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|execute_|ctl_state_alu~2_combout & (\z80_|execute_|ixy_d~7_combout & ((\z80_|pla_decode_|Equal11~0_combout ) # +// (\z80_|pla_decode_|Equal10~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|execute_|ctl_state_alu~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~24 .lut_mask = 16'hAAC8; +defparam \z80_|execute_|ctl_alu_core_hf~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y20_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~25 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~25_combout = (!\z80_|execute_|ctl_alu_op_low~28_combout & (!\z80_|execute_|ctl_mWrite~18_combout & ((\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # (\z80_|execute_|ctl_alu_core_hf~24_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~28_combout ), + .datab(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .datac(\z80_|execute_|ctl_mWrite~18_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~25 .lut_mask = 16'h0504; +defparam \z80_|execute_|ctl_alu_core_hf~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~35 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~35_combout = (\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|execute_|ctl_alu_op_low~25_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|execute_|ctl_alu_op_low~25_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~35 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_core_hf~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y20_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~23 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~23_combout = (!\z80_|execute_|ctl_alu_op_low~34_combout & ((\z80_|execute_|ctl_alu_core_hf~35_combout ) # ((\z80_|execute_|ixy_d~7_combout & \z80_|execute_|ctl_alu_op_low~24_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~34_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~35_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~24_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~23 .lut_mask = 16'h5450; +defparam \z80_|execute_|ctl_alu_core_hf~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~26 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~26_combout = (!\z80_|execute_|ctl_alu_shift_oe~15_combout & (((\z80_|decode_state_|use_ixiy~combout ) # (!\z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|pla_decode_|Equal45~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal45~0_combout ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_alu_shift_oe~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~26 .lut_mask = 16'h00DF; +defparam \z80_|execute_|ctl_alu_core_hf~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~34 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~34_combout = (\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|execute_|ctl_mRead~4_combout & ((\z80_|execute_|ctl_state_alu~4_combout )))) # (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M2_ff~q ) # +// ((\z80_|execute_|ctl_mRead~4_combout & \z80_|execute_|ctl_state_alu~4_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|execute_|ctl_mRead~4_combout ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|execute_|ctl_state_alu~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~34 .lut_mask = 16'hDC50; +defparam \z80_|execute_|ctl_alu_core_hf~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~27 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~27_combout = (\z80_|execute_|ctl_alu_op_low~22_combout & (((\z80_|execute_|ctl_alu_op_low~24_combout )))) # (!\z80_|execute_|ctl_alu_op_low~22_combout & (\z80_|execute_|ixy_d~7_combout & +// (!\z80_|execute_|ctl_mWrite~5_combout ))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ctl_mWrite~5_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~24_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~27 .lut_mask = 16'hF022; +defparam \z80_|execute_|ctl_alu_core_hf~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~28 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~28_combout = (!\z80_|execute_|ctl_alu_core_hf~34_combout & ((\z80_|pla_decode_|Equal56~0_combout & ((\z80_|execute_|ctl_alu_core_hf~27_combout ) # (\z80_|execute_|ctl_alu_op_low~22_combout ))) # +// (!\z80_|pla_decode_|Equal56~0_combout & (\z80_|execute_|ctl_alu_core_hf~27_combout & \z80_|execute_|ctl_alu_op_low~22_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~34_combout ), + .datab(\z80_|pla_decode_|Equal56~0_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~27_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~28 .lut_mask = 16'h5440; +defparam \z80_|execute_|ctl_alu_core_hf~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~29 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~29_combout = (\z80_|execute_|ctl_mRead~4_combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # ((!\z80_|execute_|ctl_state_alu~4_combout & \z80_|execute_|ctl_mWrite~9_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|ctl_mWrite~9_combout ), + .datac(\z80_|execute_|ctl_mRead~4_combout ), + .datad(\z80_|execute_|ctl_mWrite~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~29 .lut_mask = 16'hF040; +defparam \z80_|execute_|ctl_alu_core_hf~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~30 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~30_combout = (\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # ((\z80_|execute_|ctl_alu_core_hf~26_combout & ((\z80_|execute_|ctl_alu_core_hf~28_combout ) # (\z80_|execute_|ctl_alu_core_hf~29_combout )))) + + .dataa(\z80_|execute_|ctl_alu_core_hf~26_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~28_combout ), + .datac(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~29_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~30 .lut_mask = 16'hFAF8; +defparam \z80_|execute_|ctl_alu_core_hf~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y20_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~31 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~31_combout = (\z80_|execute_|ctl_alu_core_hf~25_combout ) # ((\z80_|execute_|ctl_alu_core_hf~23_combout ) # ((!\z80_|execute_|ctl_alu_op_low~43_combout & \z80_|execute_|ctl_alu_core_hf~30_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~43_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~25_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~23_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~30_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~31 .lut_mask = 16'hFDFC; +defparam \z80_|execute_|ctl_alu_core_hf~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~36 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~36_combout = (\z80_|execute_|ixy_d~6_combout ) # ((\z80_|execute_|ixy_d~8_combout & !\z80_|execute_|ixy_d~9_combout )) + + .dataa(\z80_|execute_|ixy_d~8_combout ), + .datab(gnd), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ixy_d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~36 .lut_mask = 16'hF0FA; +defparam \z80_|execute_|ctl_alu_core_hf~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~37 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~37_combout = (\z80_|execute_|ctl_alu_core_hf~36_combout & ((\z80_|pla_decode_|Equal39~0_combout ) # ((!\z80_|execute_|ixy_d~5_combout & \z80_|pla_decode_|Equal40~1_combout )))) + + .dataa(\z80_|pla_decode_|Equal39~0_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~36_combout ), + .datad(\z80_|pla_decode_|Equal40~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~37 .lut_mask = 16'hB0A0; +defparam \z80_|execute_|ctl_alu_core_hf~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y20_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~32 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~32_combout = (\z80_|execute_|ctl_alu_core_hf~22_combout ) # ((\z80_|execute_|ctl_alu_core_hf~31_combout ) # ((!\z80_|execute_|ctl_alu_op_low~44_combout & \z80_|execute_|ctl_alu_core_hf~37_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~44_combout ), + .datab(\z80_|execute_|ctl_alu_core_hf~22_combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~31_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~37_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~32 .lut_mask = 16'hFDFC; +defparam \z80_|execute_|ctl_alu_core_hf~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~33 ( +// Equation(s): +// \z80_|execute_|ctl_alu_core_hf~33_combout = (\z80_|execute_|ctl_alu_core_hf~17_combout ) # ((\z80_|execute_|ctl_alu_core_hf~32_combout ) # ((!\z80_|execute_|ctl_alu_op_low~combout & \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~17_combout ), + .datad(\z80_|execute_|ctl_alu_core_hf~32_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_core_hf~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_core_hf~33 .lut_mask = 16'hFFF4; +defparam \z80_|execute_|ctl_alu_core_hf~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y14_N22 +cycloneive_lcell_comb \z80_|alu_control_|alu_core_cf_in~0 ( +// Equation(s): +// \z80_|alu_control_|alu_core_cf_in~0_combout = (\z80_|execute_|ctl_alu_core_hf~33_combout & (\z80_|alu_flags_|flags_hf~combout )) # (!\z80_|execute_|ctl_alu_core_hf~33_combout & ((\z80_|alu_flags_|flags_cf~combout ))) + + .dataa(\z80_|alu_flags_|flags_hf~combout ), + .datab(\z80_|alu_flags_|flags_cf~combout ), + .datac(\z80_|execute_|ctl_alu_core_hf~33_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_control_|alu_core_cf_in~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|alu_core_cf_in~0 .lut_mask = 16'hACAC; +defparam \z80_|alu_control_|alu_core_cf_in~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N12 +cycloneive_lcell_comb \z80_|alu_|alu_op1[0]~0 ( +// Equation(s): +// \z80_|alu_|alu_op1[0]~0_combout = (\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [0]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [0])) + + .dataa(\z80_|execute_|ctl_alu_op_low~combout ), + .datab(\z80_|alu_|op1_high [0]), + .datac(gnd), + .datad(\z80_|alu_|op1_low [0]), + .cin(gnd), + .combout(\z80_|alu_|alu_op1[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op1[0]~0 .lut_mask = 16'hEE44; +defparam \z80_|alu_|alu_op1[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N8 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout = (\z80_|alu_|alu_op2[0]~3_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ) # ((\z80_|alu_control_|alu_core_cf_in~0_combout & \z80_|alu_|alu_op1[0]~0_combout )))) +// # (!\z80_|alu_|alu_op2[0]~3_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_control_|alu_core_cf_in~0_combout ) # (\z80_|alu_|alu_op1[0]~0_combout )))) + + .dataa(\z80_|alu_|alu_op2[0]~3_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ), + .datac(\z80_|alu_control_|alu_core_cf_in~0_combout ), + .datad(\z80_|alu_|alu_op1[0]~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 .lut_mask = 16'hECC8; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N30 +cycloneive_lcell_comb \z80_|alu_|db_high[0]~25 ( +// Equation(s): +// \z80_|alu_|db_high[0]~25_combout = ((\z80_|alu_|db_high[0]~24_combout & ((\z80_|execute_|ctl_alu_res_oe~3_combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout )))) # (!\z80_|alu_|db_high[3]~1_combout ) + + .dataa(\z80_|alu_|db_high[0]~24_combout ), + .datab(\z80_|alu_|db_high[3]~1_combout ), + .datac(\z80_|execute_|ctl_alu_res_oe~3_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[0]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[0]~25 .lut_mask = 16'hBBB3; +defparam \z80_|alu_|db_high[0]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N26 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~6 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~6_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|alu_|db_low[0]~24_combout ) # ((\z80_|alu_|db_high[0]~25_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) # +// (!\z80_|execute_|ctl_alu_op2_sel_lq~combout & (\z80_|alu_|db_high[0]~25_combout & (\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datab(\z80_|alu_|db_high[0]~25_combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .datad(\z80_|alu_|db_low[0]~24_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~6 .lut_mask = 16'hEAC0; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N2 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~6_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datac(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~6_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7 .lut_mask = 16'h3030; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y18_N3 +dffeas \z80_|alu_|op2_high[0] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_high [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_high[0] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_high[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N18 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout = (\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_high [0])) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_low [0]))) + + .dataa(\z80_|alu_|op2_high [0]), + .datab(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .datac(gnd), + .datad(\z80_|alu_|op2_low [0]), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'hBB88; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N16 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout = (\z80_|alu_control_|alu_core_cf_in~0_combout & ((\z80_|alu_|alu_op1[0]~0_combout ) # (\z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout )))) # (!\z80_|alu_control_|alu_core_cf_in~0_combout & (\z80_|alu_|alu_op1[0]~0_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ), + .datac(\z80_|alu_control_|alu_core_cf_in~0_combout ), + .datad(\z80_|alu_|alu_op1[0]~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hF660; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N10 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|execute_|ctl_alu_core_S~combout & !\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_core_R~combout ), + .datac(\z80_|execute_|ctl_alu_core_S~combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 .lut_mask = 16'hCCCF; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N22 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ) # +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout )))) # (!\z80_|execute_|ctl_alu_core_R~5_combout ) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), + .datac(\z80_|execute_|ctl_alu_core_R~5_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 .lut_mask = 16'h3F2F; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N28 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout = (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout & (((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout )) # +// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ))) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout & (((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout & +// !\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout )))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 .lut_mask = 16'h50FC; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N6 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~14 ( +// Equation(s): +// \z80_|alu_|db_high[1]~14_combout = ((\z80_|bus_control_|db[3]~21_combout & (\z80_|bus_control_|db[5]~15_combout & !\z80_|bus_control_|db[4]~19_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) + + .dataa(\z80_|bus_control_|db[3]~21_combout ), + .datab(\z80_|bus_control_|db[5]~15_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datad(\z80_|bus_control_|db[4]~19_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~14 .lut_mask = 16'h0F8F; +defparam \z80_|alu_|db_high[1]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N18 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~15 ( +// Equation(s): +// \z80_|alu_|db_high[1]~15_combout = (\z80_|execute_|ctl_alu_op2_oe~0_combout & (\z80_|alu_|op2_high [1] & ((\z80_|alu_|op1_high [1]) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_high +// [1]) # ((!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datab(\z80_|alu_|op1_high [1]), + .datac(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datad(\z80_|alu_|op2_high [1]), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~15 .lut_mask = 16'hCF45; +defparam \z80_|alu_|db_high[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N18 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~16 ( +// Equation(s): +// \z80_|alu_|db_high[1]~16_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[6]~22_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[4]~18_combout ))) + + .dataa(\z80_|alu_|db[6]~22_combout ), + .datab(gnd), + .datac(\z80_|ir_|opcode [3]), + .datad(\z80_|alu_|db[4]~18_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~16 .lut_mask = 16'hAFA0; +defparam \z80_|alu_|db_high[1]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N12 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~17 ( +// Equation(s): +// \z80_|alu_|db_high[1]~17_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_high[1]~16_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[5]~24_combout )) + + .dataa(\z80_|alu_|db[5]~24_combout ), + .datab(\z80_|alu_|db_high[1]~16_combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~17 .lut_mask = 16'hCCAA; +defparam \z80_|alu_|db_high[1]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N6 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~18 ( +// Equation(s): +// \z80_|alu_|db_high[1]~18_combout = (\z80_|alu_|db_high[1]~14_combout & (\z80_|alu_|db_high[1]~15_combout & ((\z80_|alu_|db_high[1]~17_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) + + .dataa(\z80_|alu_|db_high[1]~14_combout ), + .datab(\z80_|alu_|db_high[1]~15_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datad(\z80_|alu_|db_high[1]~17_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~18 .lut_mask = 16'h8808; +defparam \z80_|alu_|db_high[1]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N8 +cycloneive_lcell_comb \z80_|alu_|db_high[1]~19 ( +// Equation(s): +// \z80_|alu_|db_high[1]~19_combout = ((\z80_|alu_|db_high[1]~18_combout & ((\z80_|execute_|ctl_alu_res_oe~3_combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout )))) # (!\z80_|alu_|db_high[3]~1_combout ) + + .dataa(\z80_|execute_|ctl_alu_res_oe~3_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), + .datac(\z80_|alu_|db_high[3]~1_combout ), + .datad(\z80_|alu_|db_high[1]~18_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[1]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[1]~19 .lut_mask = 16'hEF0F; +defparam \z80_|alu_|db_high[1]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N16 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & ((\z80_|alu_|db_low[1]~12_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_low~combout & \z80_|alu_|db_high[1]~19_combout )))) # +// (!\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & (\z80_|execute_|ctl_alu_op1_sel_low~combout & ((\z80_|alu_|db_high[1]~19_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datab(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .datac(\z80_|alu_|db_low[1]~12_combout ), + .datad(\z80_|alu_|db_high[1]~19_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4 .lut_mask = 16'hECA0; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N22 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .datad(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 .lut_mask = 16'h0F00; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y17_N23 +dffeas \z80_|alu_|op1_low[1] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_low [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_low[1] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_low[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N14 +cycloneive_lcell_comb \z80_|alu_control_|out[6]~0 ( +// Equation(s): +// \z80_|alu_control_|out[6]~0_combout = (\z80_|alu_|op1_low [3] & ((\z80_|alu_|op1_low [1]) # (\z80_|alu_|op1_low [2]))) + + .dataa(\z80_|alu_|op1_low [1]), + .datab(gnd), + .datac(\z80_|alu_|op1_low [3]), + .datad(\z80_|alu_|op1_low [2]), + .cin(gnd), + .combout(\z80_|alu_control_|out[6]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|out[6]~0 .lut_mask = 16'hF0A0; +defparam \z80_|alu_control_|out[6]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N22 +cycloneive_lcell_comb \z80_|alu_control_|out[6]~1 ( +// Equation(s): +// \z80_|alu_control_|out[6]~1_combout = (\z80_|alu_|op1_high [2]) # ((\z80_|alu_|op1_high [1]) # ((\z80_|alu_control_|out[6]~0_combout & \z80_|alu_|op1_high [0]))) + + .dataa(\z80_|alu_|op1_high [2]), + .datab(\z80_|alu_control_|out[6]~0_combout ), + .datac(\z80_|alu_|op1_high [0]), + .datad(\z80_|alu_|op1_high [1]), + .cin(gnd), + .combout(\z80_|alu_control_|out[6]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|out[6]~1 .lut_mask = 16'hFFEA; +defparam \z80_|alu_control_|out[6]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N4 +cycloneive_lcell_comb \z80_|alu_control_|out[6]~2 ( +// Equation(s): +// \z80_|alu_control_|out[6]~2_combout = (\z80_|execute_|ctl_66_oe~combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_cf~q ) # ((\z80_|alu_control_|out[6]~1_combout & \z80_|alu_|op1_high [3]))) + + .dataa(\z80_|alu_control_|out[6]~1_combout ), + .datab(\z80_|execute_|ctl_66_oe~combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), + .datad(\z80_|alu_|op1_high [3]), + .cin(gnd), + .combout(\z80_|alu_control_|out[6]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|out[6]~2 .lut_mask = 16'hFEFC; +defparam \z80_|alu_control_|out[6]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N6 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_12 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout = (\z80_|alu_control_|db[6]~22_combout & \z80_|execute_|ctl_flags_bus~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|alu_control_|db[6]~22_combout ), + .datad(\z80_|execute_|ctl_flags_bus~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_12 .lut_mask = 16'hF000; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N0 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ) # (((!\z80_|pla_decode_|Equal13~0_combout ) # (!\z80_|execute_|ixy_d~7_combout )) # (!\z80_|pla_decode_|Equal55~0_combout )) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|pla_decode_|Equal13~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 .lut_mask = 16'hBFFF; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N28 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout = (!\z80_|alu_|db_high[3]~7_combout & (!\z80_|alu_|db_high[0]~25_combout & (!\z80_|alu_|db_high[2]~13_combout & !\z80_|alu_|db_high[1]~19_combout ))) + + .dataa(\z80_|alu_|db_high[3]~7_combout ), + .datab(\z80_|alu_|db_high[0]~25_combout ), + .datac(\z80_|alu_|db_high[2]~13_combout ), + .datad(\z80_|alu_|db_high[1]~19_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2 .lut_mask = 16'h0001; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N4 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout = (\z80_|alu_|db_high[3]~1_combout & (!\z80_|alu_|db_low[1]~12_combout & ((!\z80_|alu_|db_low[0]~3_combout ) # (!\z80_|alu_|db_low[0]~6_combout )))) + + .dataa(\z80_|alu_|db_low[0]~6_combout ), + .datab(\z80_|alu_|db_high[3]~1_combout ), + .datac(\z80_|alu_|db_low[1]~12_combout ), + .datad(\z80_|alu_|db_low[0]~3_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 .lut_mask = 16'h040C; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N24 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout = (!\z80_|alu_|db_low[2]~23_combout & (\z80_|execute_|ctl_flags_alu~15_combout & (!\z80_|alu_|db_low[3]~25_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ))) + + .dataa(\z80_|alu_|db_low[2]~23_combout ), + .datab(\z80_|execute_|ctl_flags_alu~15_combout ), + .datac(\z80_|alu_|db_low[3]~25_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 .lut_mask = 16'h0400; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N12 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout & ((\z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout )))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 .lut_mask = 16'hC888; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~7_combout = (!\z80_|execute_|ctl_flags_sz_we~6_combout & \z80_|execute_|ctl_flags_xy_we~14_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_flags_sz_we~6_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~7 .lut_mask = 16'h0F00; +defparam \z80_|execute_|ctl_flags_sz_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_sz_we~8_combout = (((!\z80_|execute_|ctl_flags_sz_we~3_combout ) # (!\z80_|execute_|ctl_flags_sz_we~2_combout )) # (!\z80_|execute_|ctl_flags_sz_we~4_combout )) # (!\z80_|execute_|ctl_flags_sz_we~7_combout ) + + .dataa(\z80_|execute_|ctl_flags_sz_we~7_combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~4_combout ), + .datac(\z80_|execute_|ctl_flags_sz_we~2_combout ), + .datad(\z80_|execute_|ctl_flags_sz_we~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_sz_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_sz_we~8 .lut_mask = 16'h7FFF; +defparam \z80_|execute_|ctl_flags_sz_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y16_N13 +dffeas \z80_|alu_flags_|SYNTHESIZED_WIRE_39 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_flags_sz_we~8_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_39 .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_39 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N20 +cycloneive_lcell_comb \z80_|execute_|setM1~51 ( +// Equation(s): +// \z80_|execute_|setM1~51_combout = (\z80_|execute_|setM1~50_combout & (!\z80_|pla_decode_|Equal52~1_combout & ((!\z80_|pla_decode_|Equal63~0_combout ) # (!\z80_|pla_decode_|Equal3~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal3~0_combout ), + .datab(\z80_|pla_decode_|Equal63~0_combout ), + .datac(\z80_|execute_|setM1~50_combout ), + .datad(\z80_|pla_decode_|Equal52~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~51_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~51 .lut_mask = 16'h0070; +defparam \z80_|execute_|setM1~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y15_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~2 ( +// Equation(s): +// \z80_|execute_|ctl_flags_oe~2_combout = (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (((\z80_|execute_|ctl_state_alu~6_combout ) # (!\z80_|execute_|ctl_flags_oe~1_combout )) # (!\z80_|execute_|setM1~51_combout ))) + + .dataa(\z80_|execute_|setM1~51_combout ), + .datab(\z80_|execute_|ctl_flags_oe~1_combout ), + .datac(\z80_|execute_|ctl_state_alu~6_combout ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_oe~2 .lut_mask = 16'h00F7; +defparam \z80_|execute_|ctl_flags_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~7 ( +// Equation(s): +// \z80_|execute_|ctl_sw_2u~7_combout = (((\z80_|execute_|ctl_alu_oe~1_combout & \z80_|nM1_int~2_combout )) # (!\z80_|execute_|ctl_alu_oe~8_combout )) # (!\z80_|execute_|ctl_reg_out_hi~6_combout ) + + .dataa(\z80_|execute_|ctl_alu_oe~1_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|execute_|ctl_reg_out_hi~6_combout ), + .datad(\z80_|execute_|ctl_alu_oe~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_2u~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_2u~7 .lut_mask = 16'h8FFF; +defparam \z80_|execute_|ctl_sw_2u~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N10 +cycloneive_lcell_comb \z80_|alu_control_|db[6]~20 ( +// Equation(s): +// \z80_|alu_control_|db[6]~20_combout = (\z80_|alu_|db[6]~22_combout & (!\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & (\z80_|execute_|ctl_flags_oe~2_combout ))) # (!\z80_|alu_|db[6]~22_combout & ((\z80_|execute_|ctl_sw_2u~7_combout ) # +// ((!\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & \z80_|execute_|ctl_flags_oe~2_combout )))) + + .dataa(\z80_|alu_|db[6]~22_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datac(\z80_|execute_|ctl_flags_oe~2_combout ), + .datad(\z80_|execute_|ctl_sw_2u~7_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[6]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[6]~20 .lut_mask = 16'h7530; +defparam \z80_|alu_control_|db[6]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N16 +cycloneive_lcell_comb \z80_|alu_control_|db[6]~21 ( +// Equation(s): +// \z80_|alu_control_|db[6]~21_combout = (!\z80_|alu_control_|db[6]~20_combout & ((\z80_|alu_control_|out[6]~2_combout ) # ((!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & !\z80_|execute_|ctl_66_oe~combout )))) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datab(\z80_|execute_|ctl_66_oe~combout ), + .datac(\z80_|alu_control_|out[6]~2_combout ), + .datad(\z80_|alu_control_|db[6]~20_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[6]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[6]~21 .lut_mask = 16'h00F1; +defparam \z80_|alu_control_|db[6]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_out_lo~8_combout = (\z80_|execute_|ctl_reg_out_lo~5_combout ) # ((!\z80_|execute_|ctl_reg_out_lo~7_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout )) + + .dataa(\z80_|execute_|ctl_reg_out_lo~5_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_out_lo~8 .lut_mask = 16'hBFBF; +defparam \z80_|execute_|ctl_reg_out_lo~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N2 +cycloneive_lcell_comb \z80_|alu_control_|db[6]~10 ( +// Equation(s): +// \z80_|alu_control_|db[6]~10_combout = (\z80_|execute_|ctl_flags_oe~2_combout ) # ((\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|execute_|ctl_66_oe~2_combout & \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ))) + + .dataa(\z80_|execute_|ctl_66_oe~2_combout ), + .datab(\z80_|execute_|ctl_flags_oe~2_combout ), + .datac(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[6]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[6]~10 .lut_mask = 16'hFFEC; +defparam \z80_|alu_control_|db[6]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N28 +cycloneive_lcell_comb \z80_|alu_control_|db[6]~11 ( +// Equation(s): +// \z80_|alu_control_|db[6]~11_combout = (\z80_|execute_|ctl_sw_1d~7_combout ) # ((\z80_|execute_|ctl_reg_out_lo~8_combout ) # ((\z80_|execute_|ctl_sw_2u~7_combout ) # (\z80_|alu_control_|db[6]~10_combout ))) + + .dataa(\z80_|execute_|ctl_sw_1d~7_combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .datac(\z80_|execute_|ctl_sw_2u~7_combout ), + .datad(\z80_|alu_control_|db[6]~10_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[6]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[6]~11 .lut_mask = 16'hFFFE; +defparam \z80_|alu_control_|db[6]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N20 +cycloneive_lcell_comb \z80_|alu_control_|db[6]~22 ( +// Equation(s): +// \z80_|alu_control_|db[6]~22_combout = ((\z80_|reg_file_|db_lo_ds[6]~0_combout & (\z80_|sw1_|db_down[6]~1_combout & \z80_|alu_control_|db[6]~21_combout ))) # (!\z80_|alu_control_|db[6]~11_combout ) + + .dataa(\z80_|reg_file_|db_lo_ds[6]~0_combout ), + .datab(\z80_|sw1_|db_down[6]~1_combout ), + .datac(\z80_|alu_control_|db[6]~21_combout ), + .datad(\z80_|alu_control_|db[6]~11_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[6]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[6]~22 .lut_mask = 16'h80FF; +defparam \z80_|alu_control_|db[6]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N10 +cycloneive_lcell_comb \z80_|alu_|db[6]~21 ( +// Equation(s): +// \z80_|alu_|db[6]~21_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[6]~84_combout & ((\z80_|alu_control_|db[6]~22_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & +// ((\z80_|alu_control_|db[6]~22_combout ) # ((!\z80_|execute_|ctl_sw_2d~13_combout )))) + + .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .datab(\z80_|alu_control_|db[6]~22_combout ), + .datac(\z80_|execute_|ctl_sw_2d~13_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[6]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[6]~21 .lut_mask = 16'hCF45; +defparam \z80_|alu_|db[6]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N24 +cycloneive_lcell_comb \z80_|alu_|db[6]~22 ( +// Equation(s): +// \z80_|alu_|db[6]~22_combout = ((\z80_|alu_|db[6]~21_combout & ((\z80_|alu_|db_high[2]~13_combout ) # (!\z80_|execute_|ctl_alu_oe~11_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|execute_|ctl_alu_oe~11_combout ), + .datab(\z80_|alu_|db[7]~9_combout ), + .datac(\z80_|alu_|db_high[2]~13_combout ), + .datad(\z80_|alu_|db[6]~21_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[6]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[6]~22 .lut_mask = 16'hF733; +defparam \z80_|alu_|db[6]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y16_N3 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~80 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~80_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout & (\z80_|alu_|db[6]~22_combout & ((\z80_|reg_file_|b2v_latch_af2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # +// (!\z80_|execute_|ctl_reg_in_hi~12_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .datab(\z80_|alu_|db[6]~22_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~80_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~80 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[6]~80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y16_N23 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y16_N1 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~79 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~79_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [6]), + .datad(\z80_|reg_file_|b2v_latch_iy_hi|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~79_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~79 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[6]~79 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y16_N23 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N20 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_hi|latch[6]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_bc_hi|latch[6]~feeder_combout = \z80_|reg_file_|gdfx_temp1[6]~84_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_bc_hi|latch[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[6]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y16_N21 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_bc_hi|latch[6]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~78 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~78_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (\z80_|reg_file_|b2v_latch_bc2_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]), + .datad(\z80_|reg_file_|b2v_latch_bc_hi|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~78_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~78 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[6]~78 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y16_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~82 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~82_combout = (\z80_|reg_file_|gdfx_temp1[6]~81_combout & (\z80_|reg_file_|gdfx_temp1[6]~80_combout & (\z80_|reg_file_|gdfx_temp1[6]~79_combout & \z80_|reg_file_|gdfx_temp1[6]~78_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[6]~81_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[6]~80_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[6]~79_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[6]~78_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~82_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~82 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[6]~82 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y14_N19 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N18 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl2_hi|db[6]~5 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_hl2_hi|db[6]~5_combout = (\z80_|execute_|ctl_reg_gp_we~8_combout ) # (((\z80_|reg_file_|b2v_latch_hl2_hi|latch [6]) # (!\z80_|reg_control_|reg_sel_hl2~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [6]), + .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_hl2_hi|db[6]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|db[6]~5 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|db[6]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y15_N7 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X37_Y15_N19 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N24 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder_combout = \z80_|reg_file_|gdfx_temp1[6]~84_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y15_N25 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~76 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~76_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [6]), + .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [6]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~76_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~76 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[6]~76 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~77 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~77_combout = (\z80_|reg_file_|b2v_latch_hl2_hi|db[6]~5_combout & (\z80_|reg_file_|gdfx_temp1[6]~76_combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl2_hi|db[6]~5_combout ), + .datac(\z80_|reg_file_|b2v_latch_hl_hi|latch [6]), + .datad(\z80_|reg_file_|gdfx_temp1[6]~76_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~77_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~77 .lut_mask = 16'hC400; +defparam \z80_|reg_file_|gdfx_temp1[6]~77 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~83 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~83_combout = (\z80_|reg_file_|gdfx_temp1[6]~82_combout & (\z80_|reg_file_|gdfx_temp1[6]~77_combout & ((\z80_|reg_file_|b2v_latch_af_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_32~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_af_hi|latch [6]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_32~combout ), + .datac(\z80_|reg_file_|gdfx_temp1[6]~82_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[6]~77_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~83_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~83 .lut_mask = 16'hB000; +defparam \z80_|reg_file_|gdfx_temp1[6]~83 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~84 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[6]~84_combout = ((\z80_|reg_file_|gdfx_temp1[6]~83_combout & ((\z80_|reg_file_|db_hi_as[6]~24_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[6]~83_combout ), + .datac(\z80_|reg_file_|db_hi_as[6]~24_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[6]~84 .lut_mask = 16'hC4FF; +defparam \z80_|reg_file_|gdfx_temp1[6]~84 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y14_N19 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[6]~24_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N18 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~22 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[6]~22_combout = (\z80_|reg_control_|reg_sw_4d_hi~0_combout & (\z80_|reg_file_|gdfx_temp1[6]~84_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[6]~84_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [6]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[6]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[6]~22 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_hi_as[6]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y14_N17 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[6]~24_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[6] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N26 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~23 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[6]~23_combout = (\z80_|reg_file_|db_hi_as[6]~22_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|db_hi_as[6]~22_combout ), + .datab(\z80_|reg_file_|b2v_latch_pc_hi|latch [6]), + .datac(gnd), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[6]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[6]~23 .lut_mask = 16'h88AA; +defparam \z80_|reg_file_|db_hi_as[6]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N14 +cycloneive_lcell_comb \z80_|address_latch_|abusz[13] ( +// Equation(s): +// \z80_|address_latch_|abusz [13] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[5]~15_combout ) + + .dataa(\z80_|resets_|clrpc~0_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|db_hi_as[5]~15_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [13]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[13] .lut_mask = 16'h5500; +defparam \z80_|address_latch_|abusz[13] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y13_N15 +dffeas \z80_|address_latch_|Q[13] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [13]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [13]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[13] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N18 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout = \z80_|address_latch_|Q [12] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout & (\z80_|address_latch_|Q [11] $ +// (\z80_|execute_|ctl_inc_dec~11_combout ))))) + + .dataa(\z80_|address_latch_|Q [11]), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), + .datac(\z80_|execute_|ctl_inc_dec~11_combout ), + .datad(\z80_|address_latch_|Q [12]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out .lut_mask = 16'hB748; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y16_N31 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y16_N29 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~61 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~61_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [4]), + .datad(\z80_|reg_file_|b2v_latch_iy_hi|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~61_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~61 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[4]~61 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y16_N15 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~62 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~62_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout & (\z80_|alu_|db[4]~18_combout & ((\z80_|reg_file_|b2v_latch_af2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # +// (!\z80_|execute_|ctl_reg_in_hi~12_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .datab(\z80_|alu_|db[4]~18_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~62_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~62 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[4]~62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y16_N3 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N0 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder_combout = \z80_|reg_file_|gdfx_temp1[4]~66_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y16_N1 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~60 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~60_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (\z80_|reg_file_|b2v_latch_bc2_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]), + .datad(\z80_|reg_file_|b2v_latch_bc_hi|latch [4]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~60_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~60 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[4]~60 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y15_N29 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X35_Y15_N23 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~63 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~63_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (\z80_|reg_file_|b2v_latch_wz_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (((\z80_|reg_file_|b2v_latch_sp_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .datab(\z80_|reg_file_|b2v_latch_wz_hi|latch [4]), + .datac(\z80_|reg_file_|b2v_latch_sp_hi|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~63_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~63 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[4]~63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~64 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~64_combout = (\z80_|reg_file_|gdfx_temp1[4]~61_combout & (\z80_|reg_file_|gdfx_temp1[4]~62_combout & (\z80_|reg_file_|gdfx_temp1[4]~60_combout & \z80_|reg_file_|gdfx_temp1[4]~63_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[4]~61_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[4]~62_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[4]~60_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[4]~63_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~64_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~64 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[4]~64 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y15_N5 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X37_Y14_N5 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N4 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl2_hi|db[4]~4 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_hl2_hi|db[4]~4_combout = (\z80_|execute_|ctl_reg_gp_we~8_combout ) # (((\z80_|reg_file_|b2v_latch_hl2_hi|latch [4]) # (!\z80_|reg_control_|reg_sel_hl2~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [4]), + .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_hl2_hi|db[4]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|db[4]~4 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|db[4]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y15_N1 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X37_Y15_N5 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X37_Y15_N23 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~58 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~58_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datab(\z80_|reg_file_|b2v_latch_de_hi|latch [4]), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~58_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~58 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[4]~58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~59 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~59_combout = (\z80_|reg_file_|b2v_latch_hl2_hi|db[4]~4_combout & (\z80_|reg_file_|gdfx_temp1[4]~58_combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl2_hi|db[4]~4_combout ), + .datac(\z80_|reg_file_|b2v_latch_hl_hi|latch [4]), + .datad(\z80_|reg_file_|gdfx_temp1[4]~58_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~59_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~59 .lut_mask = 16'hC400; +defparam \z80_|reg_file_|gdfx_temp1[4]~59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~65 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~65_combout = (\z80_|reg_file_|gdfx_temp1[4]~64_combout & (\z80_|reg_file_|gdfx_temp1[4]~59_combout & ((\z80_|reg_file_|b2v_latch_af_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_32~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[4]~64_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_32~combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [4]), + .datad(\z80_|reg_file_|gdfx_temp1[4]~59_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~65_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~65 .lut_mask = 16'hA200; +defparam \z80_|reg_file_|gdfx_temp1[4]~65 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~66 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[4]~66_combout = ((\z80_|reg_file_|gdfx_temp1[4]~65_combout & ((\z80_|reg_file_|db_hi_as[4]~18_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), + .datab(\z80_|reg_file_|db_hi_as[4]~18_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[4]~65_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[4]~66 .lut_mask = 16'hD0FF; +defparam \z80_|reg_file_|gdfx_temp1[4]~66 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y14_N11 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[4]~18_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N10 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~16 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[4]~16_combout = (\z80_|reg_control_|reg_sw_4d_hi~0_combout & (\z80_|reg_file_|gdfx_temp1[4]~66_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [4]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[4]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[4]~16 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_hi_as[4]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y14_N25 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[4]~18_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[4] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N2 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~17 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[4]~17_combout = (\z80_|reg_file_|db_hi_as[4]~16_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|db_hi_as[4]~16_combout ), + .datab(\z80_|reg_file_|b2v_latch_pc_hi|latch [4]), + .datac(gnd), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[4]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[4]~17 .lut_mask = 16'h88AA; +defparam \z80_|reg_file_|db_hi_as[4]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N24 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~18 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[4]~18_combout = ((\z80_|reg_file_|db_hi_as[4]~17_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), + .datab(\z80_|reg_file_|db_hi_as[4]~17_combout ), + .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[4]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[4]~18 .lut_mask = 16'h8FCF; +defparam \z80_|reg_file_|db_hi_as[4]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N22 +cycloneive_lcell_comb \z80_|address_latch_|abusz[12] ( +// Equation(s): +// \z80_|address_latch_|abusz [12] = (\z80_|reg_file_|db_hi_as[4]~18_combout & !\z80_|resets_|clrpc~0_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[4]~18_combout ), + .datab(gnd), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [12]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[12] .lut_mask = 16'h0A0A; +defparam \z80_|address_latch_|abusz[12] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y13_N23 +dffeas \z80_|address_latch_|Q[12] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [12]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [12]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[12] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N20 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout & ((\z80_|address_latch_|Q [11] & (!\z80_|execute_|ctl_inc_dec~11_combout & +// \z80_|address_latch_|Q [12])) # (!\z80_|address_latch_|Q [11] & (\z80_|execute_|ctl_inc_dec~11_combout & !\z80_|address_latch_|Q [12])))) + + .dataa(\z80_|address_latch_|Q [11]), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), + .datac(\z80_|execute_|ctl_inc_dec~11_combout ), + .datad(\z80_|address_latch_|Q [12]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'h0840; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N24 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[14] ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|address [14] = \z80_|address_latch_|Q [14] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout & (\z80_|address_latch_|Q [13] $ (\z80_|execute_|ctl_inc_dec~11_combout ))))) + + .dataa(\z80_|address_latch_|Q [13]), + .datab(\z80_|execute_|ctl_inc_dec~11_combout ), + .datac(\z80_|address_latch_|Q [14]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[14] .lut_mask = 16'h96F0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[14] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N16 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~24 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[6]~24_combout = ((\z80_|reg_file_|db_hi_as[6]~23_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [14]) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .datab(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datac(\z80_|reg_file_|db_hi_as[6]~23_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[6]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[6]~24 .lut_mask = 16'hF373; +defparam \z80_|reg_file_|db_hi_as[6]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N30 +cycloneive_lcell_comb \z80_|address_latch_|abusz[14] ( +// Equation(s): +// \z80_|address_latch_|abusz [14] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[6]~24_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(\z80_|reg_file_|db_hi_as[6]~24_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [14]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[14] .lut_mask = 16'h0F00; +defparam \z80_|address_latch_|abusz[14] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y13_N31 +dffeas \z80_|address_latch_|Q[14] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [14]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [14]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[14] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N4 +cycloneive_lcell_comb \z80_|address_latch_|abusz[15] ( +// Equation(s): +// \z80_|address_latch_|abusz [15] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[7]~21_combout ) + + .dataa(\z80_|resets_|clrpc~0_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|db_hi_as[7]~21_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [15]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[15] .lut_mask = 16'h5500; +defparam \z80_|address_latch_|abusz[15] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y13_N5 +dffeas \z80_|address_latch_|Q[15] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [15]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [15]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[15] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N2 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[15]~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|address[15]~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout & (\z80_|address_latch_|Q [13] $ (((\z80_|execute_|ctl_inc_dec~10_combout ) # +// (\z80_|execute_|ctl_inc_dec~7_combout ))))) + + .dataa(\z80_|execute_|ctl_inc_dec~10_combout ), + .datab(\z80_|execute_|ctl_inc_dec~7_combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), + .datad(\z80_|address_latch_|Q [13]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|address[15]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[15]~0 .lut_mask = 16'h10E0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[15]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N0 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[15]~1 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|address[15]~1_combout = \z80_|address_latch_|Q [15] $ (((\z80_|address_latch_|b2v_inst_inc_dec|address[15]~0_combout & (\z80_|address_latch_|Q [14] $ (\z80_|execute_|ctl_inc_dec~11_combout ))))) + + .dataa(\z80_|address_latch_|Q [14]), + .datab(\z80_|execute_|ctl_inc_dec~11_combout ), + .datac(\z80_|address_latch_|Q [15]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|address[15]~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|address[15]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[15]~1 .lut_mask = 16'h96F0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[15]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y14_N7 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[7]~21_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X35_Y14_N21 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[7]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N20 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~19 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[7]~19_combout = (\z80_|reg_control_|reg_sw_4d_hi~0_combout & (\z80_|reg_file_|gdfx_temp1[7]~75_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) + + .dataa(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [7]), + .datad(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[7]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[7]~19 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|db_hi_as[7]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N12 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~20 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[7]~20_combout = (\z80_|reg_file_|db_hi_as[7]~19_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_pc_hi|latch [7]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datac(gnd), + .datad(\z80_|reg_file_|db_hi_as[7]~19_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[7]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[7]~20 .lut_mask = 16'hBB00; +defparam \z80_|reg_file_|db_hi_as[7]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N6 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~21 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[7]~21_combout = ((\z80_|reg_file_|db_hi_as[7]~20_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address[15]~1_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|address[15]~1_combout ), + .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datad(\z80_|reg_file_|db_hi_as[7]~20_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[7]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[7]~21 .lut_mask = 16'hDF0F; +defparam \z80_|reg_file_|db_hi_as[7]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y15_N29 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N28 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[7]~15 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[7]~15_combout = (\z80_|execute_|ctl_reg_gp_we~8_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [7]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [7]), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[7]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[7]~15 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[7]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y15_N31 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X35_Y15_N25 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~72 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~72_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (\z80_|reg_file_|b2v_latch_wz_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [7]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [7]), + .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~72_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~72 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp1[7]~72 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y16_N17 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~71 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~71_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout & (\z80_|alu_|db[7]~12_combout & ((\z80_|reg_file_|b2v_latch_af2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # +// (!\z80_|execute_|ctl_reg_in_hi~12_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .datab(\z80_|alu_|db[7]~12_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~71_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~71 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[7]~71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y16_N11 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y16_N13 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~70 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~70_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [7]), + .datad(\z80_|reg_file_|b2v_latch_iy_hi|latch [7]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~70_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~70 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[7]~70 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y16_N15 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X37_Y16_N29 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~69 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~69_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (\z80_|reg_file_|b2v_latch_bc2_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]), + .datad(\z80_|reg_file_|b2v_latch_bc_hi|latch [7]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~69_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~69 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[7]~69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y16_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~73 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~73_combout = (\z80_|reg_file_|gdfx_temp1[7]~72_combout & (\z80_|reg_file_|gdfx_temp1[7]~71_combout & (\z80_|reg_file_|gdfx_temp1[7]~70_combout & \z80_|reg_file_|gdfx_temp1[7]~69_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[7]~72_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[7]~71_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[7]~70_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[7]~69_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~73_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~73 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[7]~73 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y14_N15 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X37_Y14_N25 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~68 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~68_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (\z80_|reg_file_|b2v_latch_hl_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_hl2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (((\z80_|reg_file_|b2v_latch_hl2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [7]), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~68_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~68 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[7]~68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y15_N3 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N0 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_hi|latch[7]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_de_hi|latch[7]~feeder_combout = \z80_|reg_file_|gdfx_temp1[7]~75_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_de_hi|latch[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[7]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y15_N1 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_de_hi|latch[7]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~67 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~67_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [7]), + .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [7]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~67_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~67 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[7]~67 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y15_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~74 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~74_combout = (\z80_|reg_file_|b2v_latch_af_hi|db[7]~15_combout & (\z80_|reg_file_|gdfx_temp1[7]~73_combout & (\z80_|reg_file_|gdfx_temp1[7]~68_combout & \z80_|reg_file_|gdfx_temp1[7]~67_combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_af_hi|db[7]~15_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[7]~73_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[7]~68_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[7]~67_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~74_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~74 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[7]~74 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~75 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[7]~75_combout = ((\z80_|reg_file_|gdfx_temp1[7]~74_combout & ((\z80_|reg_file_|db_hi_as[7]~21_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[7]~21_combout ), + .datab(\z80_|execute_|ctl_sw_4u~6_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[7]~74_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[7]~75 .lut_mask = 16'hBF0F; +defparam \z80_|reg_file_|gdfx_temp1[7]~75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N0 +cycloneive_lcell_comb \z80_|alu_|db[7]~11 ( +// Equation(s): +// \z80_|alu_|db[7]~11_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[7]~75_combout & ((\z80_|alu_control_|db[7]~19_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & +// ((\z80_|alu_control_|db[7]~19_combout ) # ((!\z80_|execute_|ctl_sw_2d~13_combout )))) + + .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .datab(\z80_|alu_control_|db[7]~19_combout ), + .datac(\z80_|execute_|ctl_sw_2d~13_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[7]~75_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[7]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[7]~11 .lut_mask = 16'hCF45; +defparam \z80_|alu_|db[7]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N30 +cycloneive_lcell_comb \z80_|alu_|db[7]~12 ( +// Equation(s): +// \z80_|alu_|db[7]~12_combout = ((\z80_|alu_|db[7]~11_combout & ((\z80_|alu_|db_high[3]~7_combout ) # (!\z80_|execute_|ctl_alu_oe~11_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|execute_|ctl_alu_oe~11_combout ), + .datab(\z80_|alu_|db[7]~9_combout ), + .datac(\z80_|alu_|db_high[3]~7_combout ), + .datad(\z80_|alu_|db[7]~11_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[7]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[7]~12 .lut_mask = 16'hF733; +defparam \z80_|alu_|db[7]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N28 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~0 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[0]~14_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[7]~12_combout ))) + + .dataa(\z80_|alu_|db[0]~14_combout ), + .datab(gnd), + .datac(\z80_|alu_|db[7]~12_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~0 .lut_mask = 16'hAAF0; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N2 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~1 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_control_|out[6]~2_combout ))) + + .dataa(gnd), + .datab(\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ), + .datac(\z80_|alu_control_|out[6]~2_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~1 .lut_mask = 16'hCCF0; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N20 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~2 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (((\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout & !\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout )))) # (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout +// & ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((!\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout )))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ), + .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~2 .lut_mask = 16'h03CA; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N8 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~3 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout = (\z80_|execute_|ctl_flags_cf2_we~3_combout & (\z80_|execute_|ctl_flags_cf2_sel_daa~combout $ (((!\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ))))) # (!\z80_|execute_|ctl_flags_cf2_we~3_combout & +// ((\z80_|alu_flags_|DFFE_inst_latch_cf2~q ) # ((\z80_|execute_|ctl_flags_cf2_sel_daa~combout & \z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout )))) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datab(\z80_|execute_|ctl_flags_cf2_we~3_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~3 .lut_mask = 16'hBA74; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y14_N9 +dffeas \z80_|alu_flags_|DFFE_inst_latch_cf2 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2 .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~8 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~8_combout = (\z80_|pla_decode_|Equal20~0_combout ) # ((\z80_|execute_|ctl_ir_we~14_combout ) # (\z80_|execute_|ctl_ir_we~8_combout )) + + .dataa(\z80_|pla_decode_|Equal20~0_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_ir_we~14_combout ), + .datad(\z80_|execute_|ctl_ir_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~8 .lut_mask = 16'hFFFA; +defparam \z80_|execute_|ctl_flags_use_cf2~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~9 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~9_combout = (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_flags_use_cf2~8_combout ) # ((\z80_|pla_decode_|Equal63~0_combout & \z80_|pla_decode_|Equal9~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal63~0_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|execute_|ctl_flags_use_cf2~8_combout ), + .datad(\z80_|pla_decode_|Equal9~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~9 .lut_mask = 16'h3230; +defparam \z80_|execute_|ctl_flags_use_cf2~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~10 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~10_combout = (\z80_|pla_decode_|Equal11~0_combout & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_M1_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~10 .lut_mask = 16'h0C04; +defparam \z80_|execute_|ctl_flags_use_cf2~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~11 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~11_combout = (\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # ((\z80_|execute_|ctl_flags_use_cf2~10_combout ) # ((\z80_|execute_|ixy_d~7_combout & \z80_|pla_decode_|Equal10~0_combout ))) + + .dataa(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|execute_|ctl_flags_use_cf2~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~11 .lut_mask = 16'hFFEA; +defparam \z80_|execute_|ctl_flags_use_cf2~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~12 ( +// Equation(s): +// \z80_|execute_|ctl_flags_use_cf2~12_combout = ((\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # ((\z80_|execute_|ctl_flags_use_cf2~9_combout ) # (\z80_|execute_|ctl_flags_use_cf2~11_combout ))) # (!\z80_|execute_|ctl_flags_use_cf2~13_combout ) + + .dataa(\z80_|execute_|ctl_flags_use_cf2~13_combout ), + .datab(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), + .datac(\z80_|execute_|ctl_flags_use_cf2~9_combout ), + .datad(\z80_|execute_|ctl_flags_use_cf2~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_use_cf2~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_use_cf2~12 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_flags_use_cf2~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N28 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout = (\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & (\z80_|alu_flags_|DFFE_inst_latch_cf2~q )) # (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & ((\z80_|execute_|ctl_flags_use_cf2~12_combout & +// (\z80_|alu_flags_|DFFE_inst_latch_cf2~q )) # (!\z80_|execute_|ctl_flags_use_cf2~12_combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf~q ))))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), + .datac(\z80_|execute_|ctl_flags_use_cf2~12_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 .lut_mask = 16'hABA8; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~46 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~46_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|pla_decode_|Equal10~0_combout & \z80_|sequencer_|DFFE_T3_ff~q )) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|pla_decode_|Equal10~0_combout ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~46 .lut_mask = 16'h8800; +defparam \z80_|execute_|ctl_alu_op_low~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~9 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~9_combout = (\z80_|execute_|ctl_alu_core_S~4_combout & (\z80_|execute_|ctl_bus_inc_oe~44_combout & (\z80_|execute_|ctl_flags_alu~18_combout & \z80_|execute_|ctl_alu_op1_sel_bus~9_combout ))) + + .dataa(\z80_|execute_|ctl_alu_core_S~4_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~44_combout ), + .datac(\z80_|execute_|ctl_flags_alu~18_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~9 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N28 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|pla_decode_|Equal63~0_combout & (\z80_|pla_decode_|Equal21~0_combout & !\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) + + .dataa(\z80_|pla_decode_|Equal63~0_combout ), + .datab(\z80_|pla_decode_|Equal21~0_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 .lut_mask = 16'hFF08; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N10 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout = (\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # ((\z80_|execute_|ctl_alu_op_low~46_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~46_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 .lut_mask = 16'hFFEF; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N16 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout = ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ) # ((\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & \z80_|execute_|ctl_alu_op_low~42_combout ))) # (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ) + + .dataa(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~42_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 .lut_mask = 16'hFBF3; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y17_N16 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout = (\z80_|execute_|ctl_state_alu~11_combout & ((\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3])) # (!\z80_|ir_|opcode [5] & ((!\z80_|ir_|opcode [3]))))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|execute_|ctl_state_alu~11_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 .lut_mask = 16'h8050; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N22 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ) # ((\z80_|execute_|ctl_alu_op_low~41_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~41_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ), + .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 .lut_mask = 16'hFEFA; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_cf_cpl~3_combout = (\z80_|execute_|ctl_alu_op_low~41_combout & (\z80_|pla_decode_|Equal64~0_combout & ((\z80_|pla_decode_|Equal9~0_combout ) # (\z80_|pla_decode_|Equal3~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~41_combout ), + .datab(\z80_|pla_decode_|Equal9~0_combout ), + .datac(\z80_|pla_decode_|Equal64~0_combout ), + .datad(\z80_|pla_decode_|Equal3~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_cf_cpl~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_cf_cpl~3 .lut_mask = 16'hA080; +defparam \z80_|execute_|ctl_flags_cf_cpl~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N20 +cycloneive_lcell_comb \z80_|alu_flags_|flags_cf ( +// Equation(s): +// \z80_|alu_flags_|flags_cf~combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout $ (((\z80_|execute_|ctl_flags_cf_cpl~9_combout ) # (\z80_|execute_|ctl_flags_cf_cpl~3_combout ))))) + + .dataa(\z80_|execute_|ctl_flags_cf_cpl~9_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ), + .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ), + .datad(\z80_|execute_|ctl_flags_cf_cpl~3_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|flags_cf~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|flags_cf .lut_mask = 16'h0C48; +defparam \z80_|alu_flags_|flags_cf .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N14 +cycloneive_lcell_comb \z80_|sw2_|db_up[0]~0 ( +// Equation(s): +// \z80_|sw2_|db_up[0]~0_combout = (\z80_|alu_|db[0]~14_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|alu_|db[0]~14_combout ), + .datad(\z80_|execute_|ctl_sw_2u~7_combout ), + .cin(gnd), + .combout(\z80_|sw2_|db_up[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sw2_|db_up[0]~0 .lut_mask = 16'hF0FF; +defparam \z80_|sw2_|db_up[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N14 +cycloneive_lcell_comb \z80_|alu_control_|db[0]~8 ( +// Equation(s): +// \z80_|alu_control_|db[0]~8_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & (((!\z80_|execute_|ctl_sw_mask543_en~0_combout & \z80_|bus_control_|db[0]~17_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) + + .dataa(\z80_|execute_|ctl_sw_mask543_en~0_combout ), + .datab(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .datac(\z80_|execute_|ctl_sw_1d~7_combout ), + .datad(\z80_|bus_control_|db[0]~17_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[0]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[0]~8 .lut_mask = 16'h4C0C; +defparam \z80_|alu_control_|db[0]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y12_N11 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[0]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y12_N5 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[0]~3_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N4 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~0 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[0]~0_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[0]~22_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # +// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[0]~0 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_lo_as[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N0 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~1 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[0]~1_combout = (\z80_|reg_file_|db_lo_as[0]~0_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_ir_lo|latch [0]), + .datab(gnd), + .datac(\z80_|reg_file_|db_lo_as[0]~0_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[0]~1 .lut_mask = 16'hA0F0; +defparam \z80_|reg_file_|db_lo_as[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~70 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~70_combout = (!\z80_|nM1_int~2_combout & (((!\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ctl_alu_op_low~22_combout )) # (!\z80_|pla_decode_|Equal41~2_combout ))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|pla_decode_|Equal41~2_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~70_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~70 .lut_mask = 16'h0307; +defparam \z80_|execute_|ctl_inc_cy~70 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N8 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~28 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~28_combout = (\z80_|pla_decode_|Equal10~0_combout & (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|pla_decode_|Equal10~0_combout ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~28 .lut_mask = 16'hC080; +defparam \z80_|execute_|pc_inc_hold~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N10 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~15 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~15_combout = (\z80_|execute_|pc_inc_hold~28_combout ) # ((\z80_|execute_|ctl_alu_op_low~22_combout & ((\z80_|pla_decode_|Equal52~1_combout ) # (\z80_|execute_|ixy_d~16_combout )))) + + .dataa(\z80_|pla_decode_|Equal52~1_combout ), + .datab(\z80_|execute_|ixy_d~16_combout ), + .datac(\z80_|execute_|pc_inc_hold~28_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~15 .lut_mask = 16'hFEF0; +defparam \z80_|execute_|pc_inc_hold~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N18 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~27 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~27_combout = (\z80_|pla_decode_|Equal11~0_combout & (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~27 .lut_mask = 16'hC080; +defparam \z80_|execute_|pc_inc_hold~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~10 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~10_combout = (\z80_|execute_|ctl_alu_op_low~22_combout & (((\z80_|execute_|ctl_mRead~7_combout ) # (\z80_|execute_|ctl_mRead~13_combout )))) # (!\z80_|execute_|ctl_alu_op_low~22_combout & (\z80_|execute_|ixy_d~5_combout & +// ((\z80_|execute_|ctl_mRead~13_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_mRead~7_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datad(\z80_|execute_|ctl_mRead~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~10 .lut_mask = 16'hFAC0; +defparam \z80_|execute_|pc_inc_hold~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout = (\z80_|execute_|ixy_d~5_combout & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal55~0_combout & \z80_|pla_decode_|Equal33~1_combout ))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(\z80_|pla_decode_|Equal33~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~11 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~11_combout = (\z80_|execute_|ctl_alu_op_low~22_combout & ((\z80_|pla_decode_|Equal6~1_combout ) # ((\z80_|execute_|ctl_mRead~8_combout )))) # (!\z80_|execute_|ctl_alu_op_low~22_combout & (\z80_|execute_|ixy_d~5_combout & +// ((\z80_|pla_decode_|Equal6~1_combout ) # (\z80_|execute_|ctl_mRead~8_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datab(\z80_|pla_decode_|Equal6~1_combout ), + .datac(\z80_|execute_|ctl_mRead~8_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~11 .lut_mask = 16'hFCA8; +defparam \z80_|execute_|pc_inc_hold~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout = (\z80_|decode_state_|use_ixiy~combout & (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|pla_decode_|Equal33~2_combout ))) + + .dataa(\z80_|decode_state_|use_ixiy~combout ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|pla_decode_|Equal33~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~9 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~9_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ) # ((\z80_|execute_|ctl_alu_op_low~22_combout & ((\z80_|execute_|ctl_mRead~12_combout ) # (!\z80_|execute_|pc_inc_hold~6_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datac(\z80_|execute_|ctl_mRead~12_combout ), + .datad(\z80_|execute_|pc_inc_hold~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~9 .lut_mask = 16'hEAEE; +defparam \z80_|execute_|pc_inc_hold~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~12 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~12_combout = (\z80_|execute_|pc_inc_hold~10_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ) # ((\z80_|execute_|pc_inc_hold~11_combout ) # (\z80_|execute_|pc_inc_hold~9_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~10_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ), + .datac(\z80_|execute_|pc_inc_hold~11_combout ), + .datad(\z80_|execute_|pc_inc_hold~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~12 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|pc_inc_hold~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~7 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~7_combout = ((\z80_|pla_decode_|Equal12~1_combout ) # ((!\z80_|execute_|ctl_alu_op_low~22_combout & !\z80_|execute_|ixy_d~5_combout ))) # (!\z80_|pla_decode_|Equal25~0_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datab(\z80_|pla_decode_|Equal25~0_combout ), + .datac(\z80_|pla_decode_|Equal12~1_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~7 .lut_mask = 16'hF3F7; +defparam \z80_|execute_|pc_inc_hold~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y14_N8 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~8 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~8_combout = (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|execute_|ctl_mRead~15_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|execute_|ctl_mRead~15_combout ), + .datad(\z80_|sequencer_|DFFE_M3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~8 .lut_mask = 16'h5F7F; +defparam \z80_|execute_|pc_inc_hold~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~13 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~13_combout = (\z80_|execute_|ctl_mRead~6_combout & (\z80_|sequencer_|DFFE_T2_ff~q & ((\z80_|sequencer_|DFFE_M2_ff~q ) # (\z80_|sequencer_|DFFE_M3_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|execute_|ctl_mRead~6_combout ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~13 .lut_mask = 16'hE000; +defparam \z80_|execute_|pc_inc_hold~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y14_N14 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~14 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~14_combout = (!\z80_|execute_|pc_inc_hold~12_combout & (\z80_|execute_|pc_inc_hold~7_combout & (\z80_|execute_|pc_inc_hold~8_combout & !\z80_|execute_|pc_inc_hold~13_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~12_combout ), + .datab(\z80_|execute_|pc_inc_hold~7_combout ), + .datac(\z80_|execute_|pc_inc_hold~8_combout ), + .datad(\z80_|execute_|pc_inc_hold~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~14 .lut_mask = 16'h0040; +defparam \z80_|execute_|pc_inc_hold~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal45~0_combout & \z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|decode_state_|use_ixiy~combout ), + .datac(\z80_|pla_decode_|Equal45~0_combout ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y14_N16 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~16 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~16_combout = (!\z80_|execute_|pc_inc_hold~15_combout & (!\z80_|execute_|pc_inc_hold~27_combout & (\z80_|execute_|pc_inc_hold~14_combout & !\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~15_combout ), + .datab(\z80_|execute_|pc_inc_hold~27_combout ), + .datac(\z80_|execute_|pc_inc_hold~14_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~16 .lut_mask = 16'h0010; +defparam \z80_|execute_|pc_inc_hold~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N8 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~22 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~22_combout = (\z80_|execute_|ctl_mRead~34_combout & (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q )))) + + .dataa(\z80_|execute_|ctl_mRead~34_combout ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~22 .lut_mask = 16'h8880; +defparam \z80_|execute_|pc_inc_hold~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~23 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~23_combout = (\z80_|execute_|pc_inc_hold~26_combout & (!\z80_|pla_decode_|Equal19~0_combout & ((\z80_|execute_|ctl_bus_db_oe~1_combout ) # (!\z80_|execute_|ctl_alu_op_low~22_combout )))) + + .dataa(\z80_|execute_|pc_inc_hold~26_combout ), + .datab(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .datac(\z80_|pla_decode_|Equal19~0_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~23 .lut_mask = 16'h080A; +defparam \z80_|execute_|pc_inc_hold~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~24 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~24_combout = (\z80_|execute_|pc_inc_hold~22_combout ) # ((!\z80_|execute_|pc_inc_hold~23_combout & ((\z80_|execute_|ixy_d~5_combout ) # (\z80_|execute_|ctl_alu_op_low~22_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|pc_inc_hold~22_combout ), + .datac(\z80_|execute_|pc_inc_hold~23_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~24 .lut_mask = 16'hCFCE; +defparam \z80_|execute_|pc_inc_hold~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~41 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~41_combout = (((!\z80_|pla_decode_|Equal3~0_combout & !\z80_|pla_decode_|Equal21~0_combout )) # (!\z80_|pla_decode_|Equal24~0_combout )) # (!\z80_|execute_|ctl_alu_op_low~22_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datab(\z80_|pla_decode_|Equal3~0_combout ), + .datac(\z80_|pla_decode_|Equal21~0_combout ), + .datad(\z80_|pla_decode_|Equal24~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~41 .lut_mask = 16'h57FF; +defparam \z80_|execute_|ctl_inc_cy~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y15_N18 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~21 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~21_combout = (\z80_|execute_|ctl_mWrite~4_combout & (\z80_|pla_decode_|Equal55~0_combout & ((\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (\z80_|execute_|ctl_mWrite~9_combout )))) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datab(\z80_|execute_|ctl_mWrite~4_combout ), + .datac(\z80_|execute_|ctl_mWrite~9_combout ), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~21 .lut_mask = 16'hC800; +defparam \z80_|execute_|pc_inc_hold~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y15_N8 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~25 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~25_combout = ((\z80_|execute_|pc_inc_hold~24_combout ) # ((\z80_|execute_|pc_inc_hold~21_combout ) # (!\z80_|execute_|ctl_inc_cy~41_combout ))) # (!\z80_|execute_|pc_inc_hold~16_combout ) + + .dataa(\z80_|execute_|pc_inc_hold~16_combout ), + .datab(\z80_|execute_|pc_inc_hold~24_combout ), + .datac(\z80_|execute_|ctl_inc_cy~41_combout ), + .datad(\z80_|execute_|pc_inc_hold~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~25 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|pc_inc_hold~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~69 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~69_combout = (!\z80_|execute_|pc_inc_hold~25_combout & (((!\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ctl_alu_op_low~22_combout )) # (!\z80_|pla_decode_|Equal34~0_combout ))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datac(\z80_|execute_|pc_inc_hold~25_combout ), + .datad(\z80_|pla_decode_|Equal34~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~69_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~69 .lut_mask = 16'h010F; +defparam \z80_|execute_|ctl_inc_cy~69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~17 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~17_combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # ((\z80_|interrupts_|DFFE_inst44~q ) # (\z80_|decode_state_|in_halt~q )) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(gnd), + .datac(\z80_|interrupts_|DFFE_inst44~q ), + .datad(\z80_|decode_state_|in_halt~q ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~17 .lut_mask = 16'hFFFA; +defparam \z80_|execute_|pc_inc_hold~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~71 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~71_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (((\z80_|execute_|ctl_inc_cy~70_combout & \z80_|execute_|ctl_inc_cy~69_combout )) # (!\z80_|execute_|pc_inc_hold~17_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|execute_|ctl_inc_cy~70_combout ), + .datac(\z80_|execute_|ctl_inc_cy~69_combout ), + .datad(\z80_|execute_|pc_inc_hold~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~71_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~71 .lut_mask = 16'h80AA; +defparam \z80_|execute_|ctl_inc_cy~71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~44 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~44_combout = (\z80_|execute_|ctl_inc_cy~82_combout & (\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout & ((\z80_|execute_|pc_inc_hold~16_combout ) # (!\z80_|execute_|pc_inc_hold~17_combout )))) # +// (!\z80_|execute_|ctl_inc_cy~82_combout & (((\z80_|execute_|pc_inc_hold~16_combout ) # (!\z80_|execute_|pc_inc_hold~17_combout )))) + + .dataa(\z80_|execute_|ctl_inc_cy~82_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ), + .datac(\z80_|execute_|pc_inc_hold~16_combout ), + .datad(\z80_|execute_|pc_inc_hold~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~44 .lut_mask = 16'hD0DD; +defparam \z80_|execute_|ctl_inc_cy~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~42 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~42_combout = (\z80_|execute_|pc_inc_hold~16_combout & \z80_|execute_|ctl_inc_cy~41_combout ) + + .dataa(\z80_|execute_|pc_inc_hold~16_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_inc_cy~41_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~42 .lut_mask = 16'hA0A0; +defparam \z80_|execute_|ctl_inc_cy~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~43 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~43_combout = (\z80_|execute_|ctl_mWrite~17_combout & (\z80_|execute_|ixy_d~5_combout & ((\z80_|execute_|ctl_inc_cy~42_combout ) # (!\z80_|execute_|pc_inc_hold~17_combout )))) + + .dataa(\z80_|execute_|pc_inc_hold~17_combout ), + .datab(\z80_|execute_|ctl_inc_cy~42_combout ), + .datac(\z80_|execute_|ctl_mWrite~17_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~43 .lut_mask = 16'hD000; +defparam \z80_|execute_|ctl_inc_cy~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~57 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~57_combout = (\z80_|execute_|ctl_inc_cy~38_combout ) # ((\z80_|execute_|pc_inc_hold~17_combout & ((\z80_|execute_|pc_inc_hold~12_combout ) # (!\z80_|execute_|pc_inc_hold~7_combout )))) + + .dataa(\z80_|execute_|ctl_inc_cy~38_combout ), + .datab(\z80_|execute_|pc_inc_hold~17_combout ), + .datac(\z80_|execute_|pc_inc_hold~7_combout ), + .datad(\z80_|execute_|pc_inc_hold~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~57_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~57 .lut_mask = 16'hEEAE; +defparam \z80_|execute_|ctl_inc_cy~57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~54 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~54_combout = ((!\z80_|execute_|ctl_alu_op_low~22_combout & ((!\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_T4_ff~q )))) # (!\z80_|pla_decode_|Equal10~0_combout ) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~54_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~54 .lut_mask = 16'h0F7F; +defparam \z80_|execute_|ctl_inc_cy~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~58 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~58_combout = ((!\z80_|execute_|pc_inc_hold~27_combout & (\z80_|execute_|pc_inc_hold~14_combout & !\z80_|execute_|ctl_inc_cy~54_combout ))) # (!\z80_|execute_|ctl_inc_cy~57_combout ) + + .dataa(\z80_|execute_|ctl_inc_cy~57_combout ), + .datab(\z80_|execute_|pc_inc_hold~27_combout ), + .datac(\z80_|execute_|pc_inc_hold~14_combout ), + .datad(\z80_|execute_|ctl_inc_cy~54_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~58_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~58 .lut_mask = 16'h5575; +defparam \z80_|execute_|ctl_inc_cy~58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~18 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~18_combout = (\z80_|execute_|pc_inc_hold~10_combout ) # ((\z80_|execute_|pc_inc_hold~9_combout ) # ((\z80_|execute_|ixy_d~5_combout & \z80_|execute_|ctl_mRead~7_combout ))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_mRead~7_combout ), + .datac(\z80_|execute_|pc_inc_hold~10_combout ), + .datad(\z80_|execute_|pc_inc_hold~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~18 .lut_mask = 16'hFFF8; +defparam \z80_|execute_|pc_inc_hold~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y14_N30 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~19 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~19_combout = (\z80_|execute_|pc_inc_hold~18_combout ) # ((\z80_|execute_|pc_inc_hold~13_combout ) # ((\z80_|execute_|pc_inc_hold~11_combout ) # (!\z80_|execute_|pc_inc_hold~7_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~18_combout ), + .datab(\z80_|execute_|pc_inc_hold~13_combout ), + .datac(\z80_|execute_|pc_inc_hold~7_combout ), + .datad(\z80_|execute_|pc_inc_hold~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~19 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|pc_inc_hold~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~45 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~45_combout = ((\z80_|pla_decode_|Equal9~1_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ixy_d~9_combout )))) # (!\z80_|execute_|ctl_inc_cy~87_combout ) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_inc_cy~87_combout ), + .datad(\z80_|execute_|ixy_d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~45 .lut_mask = 16'hAF8F; +defparam \z80_|execute_|ctl_inc_cy~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y15_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~34 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~34_combout = ((!\z80_|execute_|ctl_alu_op_low~22_combout & (!\z80_|execute_|ctl_state_alu~2_combout & !\z80_|execute_|ixy_d~5_combout ))) # (!\z80_|execute_|ctl_mWrite~6_combout ) + + .dataa(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~34 .lut_mask = 16'h3337; +defparam \z80_|execute_|ctl_inc_cy~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y15_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~35 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~35_combout = (\z80_|execute_|ctl_sw_2u~0_combout & (\z80_|execute_|ctl_inc_cy~34_combout & ((!\z80_|pla_decode_|Equal11~0_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_sw_2u~0_combout ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|execute_|ctl_inc_cy~34_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~35 .lut_mask = 16'h4C00; +defparam \z80_|execute_|ctl_inc_cy~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~46 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~46_combout = (\z80_|pla_decode_|Equal11~0_combout & ((\z80_|execute_|ixy_d~9_combout ) # ((\z80_|execute_|ctl_mWrite~6_combout & \z80_|execute_|ixy_d~7_combout )))) # (!\z80_|pla_decode_|Equal11~0_combout & +// (\z80_|execute_|ctl_mWrite~6_combout & (\z80_|execute_|ixy_d~7_combout ))) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ixy_d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~46 .lut_mask = 16'hEAC0; +defparam \z80_|execute_|ctl_inc_cy~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~47 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~47_combout = ((\z80_|execute_|ctl_inc_cy~46_combout ) # ((\z80_|execute_|ctl_mWrite~6_combout & \z80_|execute_|ctl_mRead~9_combout ))) # (!\z80_|execute_|ctl_inc_cy~39_combout ) + + .dataa(\z80_|execute_|ctl_inc_cy~39_combout ), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datac(\z80_|execute_|ctl_mRead~9_combout ), + .datad(\z80_|execute_|ctl_inc_cy~46_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~47 .lut_mask = 16'hFFD5; +defparam \z80_|execute_|ctl_inc_cy~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y18_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~48 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~48_combout = (\z80_|execute_|ctl_inc_cy~47_combout ) # ((\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ) # ((\z80_|pla_decode_|Equal11~0_combout & \z80_|execute_|ctl_alu_op_low~22_combout ))) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datac(\z80_|execute_|ctl_inc_cy~47_combout ), + .datad(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~48 .lut_mask = 16'hFFF8; +defparam \z80_|execute_|ctl_inc_cy~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y18_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~50 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~50_combout = (\z80_|execute_|ctl_inc_cy~45_combout ) # (((\z80_|execute_|ctl_inc_cy~48_combout ) # (!\z80_|execute_|ctl_inc_cy~35_combout )) # (!\z80_|execute_|ctl_inc_cy~49_combout )) + + .dataa(\z80_|execute_|ctl_inc_cy~45_combout ), + .datab(\z80_|execute_|ctl_inc_cy~49_combout ), + .datac(\z80_|execute_|ctl_inc_cy~35_combout ), + .datad(\z80_|execute_|ctl_inc_cy~48_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~50_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~50 .lut_mask = 16'hFFBF; +defparam \z80_|execute_|ctl_inc_cy~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y14_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~51 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~51_combout = (\z80_|execute_|ctl_inc_cy~50_combout & (((!\z80_|execute_|pc_inc_hold~19_combout & \z80_|execute_|pc_inc_hold~8_combout )) # (!\z80_|execute_|pc_inc_hold~17_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~19_combout ), + .datab(\z80_|execute_|pc_inc_hold~17_combout ), + .datac(\z80_|execute_|pc_inc_hold~8_combout ), + .datad(\z80_|execute_|ctl_inc_cy~50_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~51_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~51 .lut_mask = 16'h7300; +defparam \z80_|execute_|ctl_inc_cy~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y14_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~85 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~85_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|execute_|ctl_mRead~6_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|execute_|ctl_mRead~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~85_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~85 .lut_mask = 16'h57FF; +defparam \z80_|execute_|ctl_inc_cy~85 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~63 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~63_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (!\z80_|interrupts_|DFFE_inst44~q & (\z80_|execute_|ctl_mRead~12_combout & !\z80_|decode_state_|in_halt~q ))) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|interrupts_|DFFE_inst44~q ), + .datac(\z80_|execute_|ctl_mRead~12_combout ), + .datad(\z80_|decode_state_|in_halt~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~63_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~63 .lut_mask = 16'h0010; +defparam \z80_|execute_|ctl_inc_cy~63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~64 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~64_combout = (\z80_|execute_|ctl_alu_op_low~22_combout & ((\z80_|execute_|ctl_inc_cy~63_combout ) # ((!\z80_|execute_|ctl_reg_sys_hilo~21_combout & !\z80_|execute_|pc_inc_hold~9_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo~21_combout ), + .datab(\z80_|execute_|ctl_inc_cy~63_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datad(\z80_|execute_|pc_inc_hold~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~64_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~64 .lut_mask = 16'hC0D0; +defparam \z80_|execute_|ctl_inc_cy~64 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~65 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~65_combout = (\z80_|execute_|ctl_inc_cy~64_combout ) # ((\z80_|execute_|ctl_mRead~13_combout & (\z80_|execute_|ctl_alu_shift_oe~14_combout & !\z80_|execute_|pc_inc_hold~18_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~13_combout ), + .datab(\z80_|execute_|ctl_inc_cy~64_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datad(\z80_|execute_|pc_inc_hold~18_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~65_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~65 .lut_mask = 16'hCCEC; +defparam \z80_|execute_|ctl_inc_cy~65 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~59 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~59_combout = (((!\z80_|pla_decode_|Equal55~0_combout ) # (!\z80_|execute_|ctl_alu_op_low~22_combout )) # (!\z80_|pla_decode_|Equal6~0_combout )) # (!\z80_|pla_decode_|Equal33~1_combout ) + + .dataa(\z80_|pla_decode_|Equal33~1_combout ), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datad(\z80_|pla_decode_|Equal55~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~59_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~59 .lut_mask = 16'h7FFF; +defparam \z80_|execute_|ctl_inc_cy~59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~60 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~60_combout = ((\z80_|execute_|ctl_inc_cy~59_combout & (!\z80_|execute_|pc_inc_hold~9_combout & !\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ))) # (!\z80_|execute_|pc_inc_hold~17_combout ) + + .dataa(\z80_|execute_|ctl_inc_cy~59_combout ), + .datab(\z80_|execute_|pc_inc_hold~9_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ), + .datad(\z80_|execute_|pc_inc_hold~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~60_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~60 .lut_mask = 16'h02FF; +defparam \z80_|execute_|ctl_inc_cy~60 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~61 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~61_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|execute_|ctl_mRead~8_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|execute_|ctl_mRead~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~61_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~61 .lut_mask = 16'h57FF; +defparam \z80_|execute_|ctl_inc_cy~61 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y14_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~62 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~62_combout = (\z80_|execute_|pc_inc_hold~12_combout & (\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & (\z80_|execute_|ctl_inc_cy~60_combout ))) # (!\z80_|execute_|pc_inc_hold~12_combout & +// (((\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & \z80_|execute_|ctl_inc_cy~60_combout )) # (!\z80_|execute_|ctl_inc_cy~61_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~12_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), + .datac(\z80_|execute_|ctl_inc_cy~60_combout ), + .datad(\z80_|execute_|ctl_inc_cy~61_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~62_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~62 .lut_mask = 16'hC0D5; +defparam \z80_|execute_|ctl_inc_cy~62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y14_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~66 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~66_combout = (\z80_|execute_|ctl_inc_cy~65_combout ) # ((\z80_|execute_|ctl_inc_cy~62_combout ) # ((!\z80_|execute_|ctl_inc_cy~85_combout & !\z80_|execute_|pc_inc_hold~19_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~85_combout ), + .datab(\z80_|execute_|ctl_inc_cy~65_combout ), + .datac(\z80_|execute_|pc_inc_hold~19_combout ), + .datad(\z80_|execute_|ctl_inc_cy~62_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~66_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~66 .lut_mask = 16'hFFCD; +defparam \z80_|execute_|ctl_inc_cy~66 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~53 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~53_combout = ((\z80_|execute_|ixy_d~5_combout & ((\z80_|pla_decode_|Equal41~2_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) # (!\z80_|execute_|ctl_reg_sel_pc~7_combout ) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~7_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~33_combout ), + .datad(\z80_|pla_decode_|Equal41~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~53_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~53 .lut_mask = 16'hBB3B; +defparam \z80_|execute_|ctl_inc_cy~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~52 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~52_combout = (\z80_|execute_|ctl_mRead~2_combout ) # ((\z80_|execute_|ctl_mWrite~8_combout ) # ((\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~8_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~2_combout ), + .datab(\z80_|execute_|ctl_mWrite~8_combout ), + .datac(\z80_|pla_decode_|Equal34~0_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~52_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~52 .lut_mask = 16'hFEFF; +defparam \z80_|execute_|ctl_inc_cy~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~84 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~84_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & ((\z80_|execute_|ctl_inc_cy~52_combout ) # (!\z80_|execute_|fMRead~7_combout )))) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|execute_|ctl_inc_cy~52_combout ), + .datac(\z80_|execute_|fMRead~7_combout ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~84_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~84 .lut_mask = 16'h8A00; +defparam \z80_|execute_|ctl_inc_cy~84 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y14_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|pla_decode_|Equal8~0_combout & \z80_|execute_|ctl_mWrite~4_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|pla_decode_|Equal8~0_combout ), + .datad(\z80_|execute_|ctl_mWrite~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~55 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~55_combout = ((\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ) # ((!\z80_|execute_|ctl_inc_cy~54_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ))) # (!\z80_|execute_|ctl_reg_sys_we~2_combout ) + + .dataa(\z80_|execute_|ctl_reg_sys_we~2_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ), + .datad(\z80_|execute_|ctl_inc_cy~54_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~55_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~55 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_inc_cy~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y14_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~56 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~56_combout = (!\z80_|execute_|pc_inc_hold~17_combout & ((\z80_|execute_|ctl_inc_cy~53_combout ) # ((\z80_|execute_|ctl_inc_cy~84_combout ) # (\z80_|execute_|ctl_inc_cy~55_combout )))) + + .dataa(\z80_|execute_|ctl_inc_cy~53_combout ), + .datab(\z80_|execute_|ctl_inc_cy~84_combout ), + .datac(\z80_|execute_|pc_inc_hold~17_combout ), + .datad(\z80_|execute_|ctl_inc_cy~55_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~56_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~56 .lut_mask = 16'h0F0E; +defparam \z80_|execute_|ctl_inc_cy~56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y14_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~67 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~67_combout = (\z80_|execute_|ctl_inc_cy~58_combout ) # ((\z80_|execute_|ctl_inc_cy~51_combout ) # ((\z80_|execute_|ctl_inc_cy~66_combout ) # (\z80_|execute_|ctl_inc_cy~56_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~58_combout ), + .datab(\z80_|execute_|ctl_inc_cy~51_combout ), + .datac(\z80_|execute_|ctl_inc_cy~66_combout ), + .datad(\z80_|execute_|ctl_inc_cy~56_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~67_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~67 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_inc_cy~67 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y14_N20 +cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~20 ( +// Equation(s): +// \z80_|execute_|pc_inc_hold~20_combout = (\z80_|execute_|pc_inc_hold~19_combout ) # ((\z80_|execute_|pc_inc_hold~27_combout ) # ((\z80_|execute_|pc_inc_hold~15_combout ) # (!\z80_|execute_|pc_inc_hold~8_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~19_combout ), + .datab(\z80_|execute_|pc_inc_hold~27_combout ), + .datac(\z80_|execute_|pc_inc_hold~8_combout ), + .datad(\z80_|execute_|pc_inc_hold~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|pc_inc_hold~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|pc_inc_hold~20 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|pc_inc_hold~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y15_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~83 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~83_combout = (\z80_|execute_|ctl_state_alu~6_combout & (\z80_|sequencer_|DFFE_M2_ff~q & (!\z80_|execute_|pc_inc_hold~20_combout & \z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|execute_|ctl_state_alu~6_combout ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|execute_|pc_inc_hold~20_combout ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~83_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~83 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_inc_cy~83 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~68 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~68_combout = (\z80_|execute_|ctl_inc_cy~44_combout ) # ((\z80_|execute_|ctl_inc_cy~43_combout ) # ((\z80_|execute_|ctl_inc_cy~67_combout ) # (\z80_|execute_|ctl_inc_cy~83_combout ))) + + .dataa(\z80_|execute_|ctl_inc_cy~44_combout ), + .datab(\z80_|execute_|ctl_inc_cy~43_combout ), + .datac(\z80_|execute_|ctl_inc_cy~67_combout ), + .datad(\z80_|execute_|ctl_inc_cy~83_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~68_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~68 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_inc_cy~68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N30 +cycloneive_lcell_comb \z80_|address_latch_|Q[0]~feeder ( +// Equation(s): +// \z80_|address_latch_|Q[0]~feeder_combout = \z80_|address_latch_|abusz [0] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [0]), + .cin(gnd), + .combout(\z80_|address_latch_|Q[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|Q[0]~feeder .lut_mask = 16'hFF00; +defparam \z80_|address_latch_|Q[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y11_N31 +dffeas \z80_|address_latch_|Q[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|Q[0]~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[0] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~72 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~72_combout = (\z80_|execute_|pc_inc_hold~16_combout & (\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout & (\z80_|execute_|ctl_inc_cy~41_combout & !\z80_|execute_|pc_inc_hold~21_combout ))) + + .dataa(\z80_|execute_|pc_inc_hold~16_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ), + .datac(\z80_|execute_|ctl_inc_cy~41_combout ), + .datad(\z80_|execute_|pc_inc_hold~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~72_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~72 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_inc_cy~72 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y18_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~73 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~73_combout = (\z80_|execute_|ixy_d~9_combout ) # ((\z80_|execute_|ctl_alu_oe~0_combout ) # ((\z80_|sequencer_|DFFE_M4_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|execute_|ixy_d~9_combout ), + .datac(\z80_|execute_|ctl_alu_oe~0_combout ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~73_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~73 .lut_mask = 16'hFEFC; +defparam \z80_|execute_|ctl_inc_cy~73 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y18_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~74 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~74_combout = ((\z80_|pla_decode_|Equal19~0_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # (\z80_|execute_|ctl_inc_cy~73_combout )))) # (!\z80_|execute_|ctl_inc_cy~86_combout ) + + .dataa(\z80_|execute_|ctl_inc_cy~86_combout ), + .datab(\z80_|pla_decode_|Equal19~0_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|execute_|ctl_inc_cy~73_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~74_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~74 .lut_mask = 16'hDDD5; +defparam \z80_|execute_|ctl_inc_cy~74 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y15_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~75 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~75_combout = (\z80_|execute_|ctl_inc_cy~72_combout ) # ((\z80_|execute_|ctl_inc_cy~74_combout & ((!\z80_|execute_|pc_inc_hold~17_combout ) # (!\z80_|execute_|pc_inc_hold~25_combout )))) + + .dataa(\z80_|execute_|ctl_inc_cy~72_combout ), + .datab(\z80_|execute_|pc_inc_hold~25_combout ), + .datac(\z80_|execute_|ctl_inc_cy~74_combout ), + .datad(\z80_|execute_|pc_inc_hold~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~75_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~75 .lut_mask = 16'hBAFA; +defparam \z80_|execute_|ctl_inc_cy~75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~76 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~76_combout = (((!\z80_|execute_|ctl_inc_cy~40_combout ) # (!\z80_|execute_|ctl_inc_cy~37_combout )) # (!\z80_|execute_|ctl_inc_cy~33_combout )) # (!\z80_|execute_|ctl_inc_cy~32_combout ) + + .dataa(\z80_|execute_|ctl_inc_cy~32_combout ), + .datab(\z80_|execute_|ctl_inc_cy~33_combout ), + .datac(\z80_|execute_|ctl_inc_cy~37_combout ), + .datad(\z80_|execute_|ctl_inc_cy~40_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~76_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~76 .lut_mask = 16'h7FFF; +defparam \z80_|execute_|ctl_inc_cy~76 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y18_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~80 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~80_combout = (\z80_|execute_|ctl_inc_cy~76_combout ) # ((!\z80_|execute_|ctl_inc_cy~36_combout ) # (!\z80_|execute_|ctl_inc_cy~79_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_inc_cy~76_combout ), + .datac(\z80_|execute_|ctl_inc_cy~79_combout ), + .datad(\z80_|execute_|ctl_inc_cy~36_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~80_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~80 .lut_mask = 16'hCFFF; +defparam \z80_|execute_|ctl_inc_cy~80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y15_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~81 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~81_combout = (\z80_|execute_|ctl_inc_cy~75_combout ) # ((\z80_|execute_|ctl_inc_cy~80_combout & ((\z80_|execute_|ctl_inc_cy~69_combout ) # (!\z80_|execute_|pc_inc_hold~17_combout )))) + + .dataa(\z80_|execute_|pc_inc_hold~17_combout ), + .datab(\z80_|execute_|ctl_inc_cy~69_combout ), + .datac(\z80_|execute_|ctl_inc_cy~75_combout ), + .datad(\z80_|execute_|ctl_inc_cy~80_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~81_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~81 .lut_mask = 16'hFDF0; +defparam \z80_|execute_|ctl_inc_cy~81 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N20 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout = \z80_|address_latch_|Q [0] $ (((\z80_|execute_|ctl_inc_cy~71_combout ) # ((\z80_|execute_|ctl_inc_cy~68_combout ) # (\z80_|execute_|ctl_inc_cy~81_combout )))) + + .dataa(\z80_|execute_|ctl_inc_cy~71_combout ), + .datab(\z80_|execute_|ctl_inc_cy~68_combout ), + .datac(\z80_|address_latch_|Q [0]), + .datad(\z80_|execute_|ctl_inc_cy~81_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out .lut_mask = 16'h0F1E; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N10 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~3 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[0]~3_combout = ((\z80_|reg_file_|db_lo_as[0]~1_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .datab(\z80_|reg_file_|db_lo_as[0]~1_combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), + .datad(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[0]~3 .lut_mask = 16'hC4FF; +defparam \z80_|reg_file_|db_lo_as[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y11_N1 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N10 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[0]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_lo|latch[0]~feeder_combout = \z80_|reg_file_|gdfx_temp0[0]~22_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[0]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y11_N11 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_af_lo|latch[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~13 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~13_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [0]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~13 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[0]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y14_N9 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~12 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~12_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [0] & ((\z80_|alu_control_|db[0]~12_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|alu_control_|db[0]~12_combout ) # ((!\z80_|execute_|ctl_reg_in_lo~8_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datab(\z80_|alu_control_|db[0]~12_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [0]), + .datad(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~12 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[0]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N8 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_lo|latch[0]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_de_lo|latch[0]~feeder_combout = \z80_|reg_file_|gdfx_temp0[0]~22_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_de_lo|latch[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[0]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y11_N9 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_de_lo|latch[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y11_N27 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~10 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~10_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [0] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [0] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [0]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~10 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp0[0]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y12_N3 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N2 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0_combout = ((\z80_|execute_|ctl_reg_gp_we~8_combout ) # ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]) # (!\z80_|reg_control_|reg_sel_hl2~0_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ), + .datab(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]), + .datad(\z80_|reg_control_|reg_sel_hl2~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0 .lut_mask = 16'hFDFF; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y12_N9 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~11 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~11_combout = (\z80_|reg_file_|gdfx_temp0[0]~10_combout & (\z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0_combout & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp0[0]~10_combout ), + .datab(\z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_hl_lo|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~11 .lut_mask = 16'h8088; +defparam \z80_|reg_file_|gdfx_temp0[0]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N2 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder_combout = \z80_|reg_file_|gdfx_temp0[0]~22_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y14_N3 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X32_Y13_N13 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~14 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~14_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (\z80_|reg_file_|b2v_latch_ix_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [0]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [0]), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~14 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[0]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y13_N11 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N20 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_sp_lo|latch[0]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_sp_lo|latch[0]~feeder_combout = \z80_|reg_file_|gdfx_temp0[0]~22_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_sp_lo|latch[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[0]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y12_N21 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_sp_lo|latch[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X31_Y12_N17 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~15 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~15_combout = (\z80_|reg_file_|b2v_latch_sp_lo|latch [0] & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # (!\z80_|reg_file_|b2v_latch_sp_lo|latch [0] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_sp_lo|latch [0]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_iy_lo|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~15 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp0[0]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~16 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~16_combout = (\z80_|reg_file_|gdfx_temp0[0]~14_combout & (\z80_|reg_file_|gdfx_temp0[0]~15_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp0[0]~14_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [0]), + .datad(\z80_|reg_file_|gdfx_temp0[0]~15_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~16 .lut_mask = 16'hA200; +defparam \z80_|reg_file_|gdfx_temp0[0]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~17 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~17_combout = (\z80_|reg_file_|gdfx_temp0[0]~13_combout & (\z80_|reg_file_|gdfx_temp0[0]~12_combout & (\z80_|reg_file_|gdfx_temp0[0]~11_combout & \z80_|reg_file_|gdfx_temp0[0]~16_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[0]~13_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~12_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[0]~11_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~16_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~17 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[0]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~22 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[0]~22_combout = ((\z80_|reg_file_|gdfx_temp0[0]~17_combout & ((\z80_|reg_file_|db_lo_as[0]~3_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .datac(\z80_|reg_file_|db_lo_as[0]~3_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~17_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[0]~22 .lut_mask = 16'hF733; +defparam \z80_|reg_file_|gdfx_temp0[0]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N22 +cycloneive_lcell_comb \z80_|alu_control_|db[0]~9 ( +// Equation(s): +// \z80_|alu_control_|db[0]~9_combout = (\z80_|sw2_|db_up[0]~0_combout & (\z80_|alu_control_|db[0]~8_combout & ((\z80_|reg_file_|gdfx_temp0[0]~22_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) + + .dataa(\z80_|sw2_|db_up[0]~0_combout ), + .datab(\z80_|alu_control_|db[0]~8_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[0]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[0]~9 .lut_mask = 16'h8088; +defparam \z80_|alu_control_|db[0]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N0 +cycloneive_lcell_comb \z80_|alu_control_|db[0]~12 ( +// Equation(s): +// \z80_|alu_control_|db[0]~12_combout = ((\z80_|alu_control_|db[0]~9_combout & ((\z80_|alu_flags_|flags_cf~combout ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) + + .dataa(\z80_|alu_flags_|flags_cf~combout ), + .datab(\z80_|execute_|ctl_flags_oe~2_combout ), + .datac(\z80_|alu_control_|db[0]~9_combout ), + .datad(\z80_|alu_control_|db[6]~11_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[0]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[0]~12 .lut_mask = 16'hB0FF; +defparam \z80_|alu_control_|db[0]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N2 +cycloneive_lcell_comb \z80_|address_latch_|abusz[8] ( +// Equation(s): +// \z80_|address_latch_|abusz [8] = (\z80_|reg_file_|db_hi_as[0]~6_combout & !\z80_|resets_|clrpc~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|reg_file_|db_hi_as[0]~6_combout ), + .datad(\z80_|resets_|clrpc~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [8]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[8] .lut_mask = 16'h00F0; +defparam \z80_|address_latch_|abusz[8] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y10_N3 +dffeas \z80_|address_latch_|Q[8] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [8]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [8]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[8] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N4 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout = \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout $ (\z80_|address_latch_|Q [7]) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), + .datad(\z80_|address_latch_|Q [7]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out .lut_mask = 16'h0FF0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y12_N21 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y12_N11 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~84 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~84_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (\z80_|reg_file_|b2v_latch_hl_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl_lo|latch [7]), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~84_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~84 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp0[7]~84 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N20 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_lo|latch[7]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_de_lo|latch[7]~feeder_combout = \z80_|reg_file_|gdfx_temp0[7]~91_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_de_lo|latch[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[7]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y11_N21 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_de_lo|latch[7]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y11_N7 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y11_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~83 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~83_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [7] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [7] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [7]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~83_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~83 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|gdfx_temp0[7]~83 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y12_N29 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~88 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~88_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [7] & ((\z80_|alu_control_|db[7]~19_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|alu_control_|db[7]~19_combout ) # ((!\z80_|execute_|ctl_reg_in_lo~8_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datab(\z80_|alu_control_|db[7]~19_combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [7]), + .datad(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~88_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~88 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[7]~88 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y14_N25 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X32_Y14_N23 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~86 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~86_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [7]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [7]), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~86_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~86 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[7]~86 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y12_N25 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X31_Y12_N27 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~87 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~87_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (\z80_|reg_file_|b2v_latch_ix_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [7]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_iy_lo|latch [7]), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [7]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~87_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~87 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[7]~87 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y12_N29 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N28 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_wz_lo|db[7]~0 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_wz_lo|db[7]~0_combout = (\z80_|reg_control_|reg_sys_we_lo~combout ) # (((\z80_|reg_file_|b2v_latch_wz_lo|latch [7]) # (!\z80_|execute_|ctl_reg_sel_wz~18_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[0]~31_combout )) + + .dataa(\z80_|reg_control_|reg_sys_we_lo~combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo[0]~31_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [7]), + .datad(\z80_|execute_|ctl_reg_sel_wz~18_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_wz_lo|db[7]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|db[7]~0 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_wz_lo|db[7]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~89 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~89_combout = (\z80_|reg_file_|gdfx_temp0[7]~88_combout & (\z80_|reg_file_|gdfx_temp0[7]~86_combout & (\z80_|reg_file_|gdfx_temp0[7]~87_combout & \z80_|reg_file_|b2v_latch_wz_lo|db[7]~0_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[7]~88_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[7]~86_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[7]~87_combout ), + .datad(\z80_|reg_file_|b2v_latch_wz_lo|db[7]~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~89_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~89 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[7]~89 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y11_N29 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X32_Y11_N7 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~85 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~85_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [7]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [7]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~85_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~85 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[7]~85 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y12_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~90 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~90_combout = (\z80_|reg_file_|gdfx_temp0[7]~84_combout & (\z80_|reg_file_|gdfx_temp0[7]~83_combout & (\z80_|reg_file_|gdfx_temp0[7]~89_combout & \z80_|reg_file_|gdfx_temp0[7]~85_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[7]~84_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[7]~83_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[7]~89_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[7]~85_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~90 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[7]~90 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~91 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[7]~91_combout = ((\z80_|reg_file_|gdfx_temp0[7]~90_combout & ((\z80_|reg_file_|db_lo_as[7]~24_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp0[7]~90_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .datac(\z80_|execute_|ctl_sw_4u~6_combout ), + .datad(\z80_|reg_file_|db_lo_as[7]~24_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[7]~91 .lut_mask = 16'hBB3B; +defparam \z80_|reg_file_|gdfx_temp0[7]~91 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y12_N15 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[7]~24_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N14 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~22 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[7]~22_combout = (\z80_|reg_file_|gdfx_temp0[7]~91_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) # (!\z80_|reg_file_|gdfx_temp0[7]~91_combout & +// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [7]), + .datad(\z80_|execute_|ctl_sw_4d~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[7]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[7]~22 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|db_lo_as[7]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y12_N13 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[7]~24_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[7] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N18 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~23 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[7]~23_combout = (\z80_|reg_file_|db_lo_as[7]~22_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(\z80_|reg_file_|db_lo_as[7]~22_combout ), + .datab(gnd), + .datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [7]), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[7]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[7]~23 .lut_mask = 16'hAA0A; +defparam \z80_|reg_file_|db_lo_as[7]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y12_N12 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~24 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[7]~24_combout = ((\z80_|reg_file_|db_lo_as[7]~23_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), + .datab(\z80_|reg_file_|db_lo_as[7]~23_combout ), + .datac(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[7]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[7]~24 .lut_mask = 16'h8FCF; +defparam \z80_|reg_file_|db_lo_as[7]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N6 +cycloneive_lcell_comb \z80_|address_latch_|abusz[7] ( +// Equation(s): +// \z80_|address_latch_|abusz [7] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[7]~24_combout ) + + .dataa(\z80_|resets_|clrpc~0_combout ), + .datab(gnd), + .datac(\z80_|reg_file_|db_lo_as[7]~24_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [7]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[7] .lut_mask = 16'h5050; +defparam \z80_|address_latch_|abusz[7] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N16 +cycloneive_lcell_comb \z80_|address_latch_|Q[7]~feeder ( +// Equation(s): +// \z80_|address_latch_|Q[7]~feeder_combout = \z80_|address_latch_|abusz [7] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [7]), + .cin(gnd), + .combout(\z80_|address_latch_|Q[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|Q[7]~feeder .lut_mask = 16'hFF00; +defparam \z80_|address_latch_|Q[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y13_N17 +dffeas \z80_|address_latch_|Q[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|Q[7]~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[7] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N10 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout = \z80_|address_latch_|Q [8] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout & (\z80_|execute_|ctl_inc_dec~11_combout $ (\z80_|address_latch_|Q [7]))))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), + .datab(\z80_|address_latch_|Q [8]), + .datac(\z80_|execute_|ctl_inc_dec~11_combout ), + .datad(\z80_|address_latch_|Q [7]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out .lut_mask = 16'hC66C; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y14_N23 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[0]~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X35_Y14_N29 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[0]~6_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N28 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~4 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[0]~4_combout = (\z80_|reg_control_|reg_sw_4d_hi~0_combout & (\z80_|reg_file_|gdfx_temp1[0]~30_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) + + .dataa(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [0]), + .datad(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[0]~4 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|db_hi_as[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N0 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~5 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[0]~5_combout = (\z80_|reg_file_|db_hi_as[0]~4_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [0]), + .datad(\z80_|reg_file_|db_hi_as[0]~4_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[0]~5 .lut_mask = 16'hF300; +defparam \z80_|reg_file_|db_hi_as[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y14_N22 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~6 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[0]~6_combout = ((\z80_|reg_file_|db_hi_as[0]~5_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), + .datab(\z80_|reg_file_|db_hi_as[0]~5_combout ), + .datac(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[0]~6 .lut_mask = 16'h8FCF; +defparam \z80_|reg_file_|db_hi_as[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y14_N27 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X37_Y14_N13 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~23 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~23_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (\z80_|reg_file_|b2v_latch_hl_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_hl2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (((\z80_|reg_file_|b2v_latch_hl2_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [0]), + .datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~23 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[0]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y16_N27 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X35_Y16_N5 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~25 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~25_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_iy_hi|latch [0]), + .datad(\z80_|reg_file_|b2v_latch_ix_hi|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~25 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[0]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y15_N11 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X35_Y15_N13 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~27 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~27_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (\z80_|reg_file_|b2v_latch_wz_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (((\z80_|reg_file_|b2v_latch_sp_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .datab(\z80_|reg_file_|b2v_latch_wz_hi|latch [0]), + .datac(\z80_|reg_file_|b2v_latch_sp_hi|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~27 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[0]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y16_N27 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X37_Y16_N25 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~24 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~24_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (\z80_|reg_file_|b2v_latch_bc2_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc_hi|latch [0]), + .datad(\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~24 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[0]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y16_N27 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~26 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~26_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout & (\z80_|alu_|db[0]~14_combout & ((\z80_|reg_file_|b2v_latch_af2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # +// (!\z80_|execute_|ctl_reg_in_hi~12_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .datab(\z80_|alu_|db[0]~14_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [0]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~26 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[0]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~28 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~28_combout = (\z80_|reg_file_|gdfx_temp1[0]~25_combout & (\z80_|reg_file_|gdfx_temp1[0]~27_combout & (\z80_|reg_file_|gdfx_temp1[0]~24_combout & \z80_|reg_file_|gdfx_temp1[0]~26_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~25_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[0]~27_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~24_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[0]~26_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~28 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[0]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y15_N17 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N16 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[0]~11 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[0]~11_combout = (\z80_|execute_|ctl_reg_gp_we~8_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [0]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [0]), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[0]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[0]~11 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[0]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y15_N11 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N16 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_hi|latch[0]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_de_hi|latch[0]~feeder_combout = \z80_|reg_file_|gdfx_temp1[0]~30_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_de_hi|latch[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[0]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y15_N17 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_de_hi|latch[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[0] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~22 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~22_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [0]), + .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [0]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~22 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[0]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N24 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~29 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~29_combout = (\z80_|reg_file_|gdfx_temp1[0]~23_combout & (\z80_|reg_file_|gdfx_temp1[0]~28_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[0]~11_combout & \z80_|reg_file_|gdfx_temp1[0]~22_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~23_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[0]~28_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|db[0]~11_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[0]~22_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~29 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[0]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~30 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[0]~30_combout = ((\z80_|reg_file_|gdfx_temp1[0]~29_combout & ((\z80_|reg_file_|db_hi_as[0]~6_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[0]~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[0]~29_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datad(\z80_|execute_|ctl_sw_4u~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[0]~30 .lut_mask = 16'h8FCF; +defparam \z80_|reg_file_|gdfx_temp1[0]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N12 +cycloneive_lcell_comb \z80_|alu_|db[0]~13 ( +// Equation(s): +// \z80_|alu_|db[0]~13_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[0]~30_combout & ((\z80_|alu_|db_low[0]~24_combout ) # (!\z80_|execute_|ctl_alu_oe~11_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & +// (((\z80_|alu_|db_low[0]~24_combout ) # (!\z80_|execute_|ctl_alu_oe~11_combout )))) + + .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[0]~30_combout ), + .datac(\z80_|alu_|db_low[0]~24_combout ), + .datad(\z80_|execute_|ctl_alu_oe~11_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[0]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[0]~13 .lut_mask = 16'hD0DD; +defparam \z80_|alu_|db[0]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N22 +cycloneive_lcell_comb \z80_|alu_|db[0]~14 ( +// Equation(s): +// \z80_|alu_|db[0]~14_combout = ((\z80_|alu_|db[0]~13_combout & ((\z80_|alu_control_|db[0]~12_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|alu_control_|db[0]~12_combout ), + .datab(\z80_|alu_|db[7]~9_combout ), + .datac(\z80_|execute_|ctl_sw_2d~13_combout ), + .datad(\z80_|alu_|db[0]~13_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[0]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[0]~14 .lut_mask = 16'hBF33; +defparam \z80_|alu_|db[0]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N12 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~10 ( +// Equation(s): +// \z80_|alu_|db_low[1]~10_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[2]~16_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[0]~14_combout ))) + + .dataa(\z80_|alu_|db[2]~16_combout ), + .datab(\z80_|alu_|db[0]~14_combout ), + .datac(gnd), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~10 .lut_mask = 16'hAACC; +defparam \z80_|alu_|db_low[1]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N10 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~11 ( +// Equation(s): +// \z80_|alu_|db_low[1]~11_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_low[1]~10_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[1]~10_combout )) + + .dataa(\z80_|alu_|db[1]~10_combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .datac(gnd), + .datad(\z80_|alu_|db_low[1]~10_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~11 .lut_mask = 16'hEE22; +defparam \z80_|alu_|db_low[1]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N22 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~8 ( +// Equation(s): +// \z80_|alu_|db_low[1]~8_combout = (\z80_|execute_|ctl_alu_op2_oe~0_combout & (\z80_|alu_|op2_low [1] & ((\z80_|alu_|op1_low [1]) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout & (((\z80_|alu_|op1_low [1]) # +// (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datab(\z80_|alu_|op2_low [1]), + .datac(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .datad(\z80_|alu_|op1_low [1]), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~8 .lut_mask = 16'hDD0D; +defparam \z80_|alu_|db_low[1]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N2 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~7 ( +// Equation(s): +// \z80_|alu_|db_low[1]~7_combout = ((\z80_|bus_control_|db[3]~21_combout & (!\z80_|bus_control_|db[5]~15_combout & !\z80_|bus_control_|db[4]~19_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) + + .dataa(\z80_|bus_control_|db[3]~21_combout ), + .datab(\z80_|bus_control_|db[5]~15_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datad(\z80_|bus_control_|db[4]~19_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~7 .lut_mask = 16'h0F2F; +defparam \z80_|alu_|db_low[1]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N4 +cycloneive_lcell_comb \z80_|alu_|result_lo[1]~feeder ( +// Equation(s): +// \z80_|alu_|result_lo[1]~feeder_combout = \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|result_lo[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|result_lo[1]~feeder .lut_mask = 16'hFF00; +defparam \z80_|alu_|result_lo[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y18_N5 +dffeas \z80_|alu_|result_lo[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|result_lo[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_alu_op_low~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|result_lo [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|result_lo[1] .is_wysiwyg = "true"; +defparam \z80_|alu_|result_lo[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N4 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~9 ( +// Equation(s): +// \z80_|alu_|db_low[1]~9_combout = (\z80_|alu_|db_low[1]~8_combout & (\z80_|alu_|db_low[1]~7_combout & ((\z80_|execute_|ctl_alu_res_oe~3_combout ) # (\z80_|alu_|result_lo [1])))) + + .dataa(\z80_|alu_|db_low[1]~8_combout ), + .datab(\z80_|alu_|db_low[1]~7_combout ), + .datac(\z80_|execute_|ctl_alu_res_oe~3_combout ), + .datad(\z80_|alu_|result_lo [1]), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~9 .lut_mask = 16'h8880; +defparam \z80_|alu_|db_low[1]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N26 +cycloneive_lcell_comb \z80_|alu_|db_low[1]~12 ( +// Equation(s): +// \z80_|alu_|db_low[1]~12_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout & (\z80_|alu_|db_low[1]~11_combout & ((\z80_|alu_|db_low[1]~9_combout )))) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout & (((\z80_|alu_|db_low[1]~9_combout ) # +// (!\z80_|alu_|db_high[3]~0_combout )))) + + .dataa(\z80_|alu_|db_low[1]~11_combout ), + .datab(\z80_|alu_|db_high[3]~0_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datad(\z80_|alu_|db_low[1]~9_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[1]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[1]~12 .lut_mask = 16'hAF03; +defparam \z80_|alu_|db_low[1]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N2 +cycloneive_lcell_comb \z80_|alu_|db[1]~8 ( +// Equation(s): +// \z80_|alu_|db[1]~8_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[1]~21_combout & ((\z80_|alu_control_|db[1]~26_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & +// (((\z80_|alu_control_|db[1]~26_combout )) # (!\z80_|execute_|ctl_sw_2d~13_combout ))) + + .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .datab(\z80_|execute_|ctl_sw_2d~13_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .datad(\z80_|alu_control_|db[1]~26_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[1]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[1]~8 .lut_mask = 16'hF531; +defparam \z80_|alu_|db[1]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N18 +cycloneive_lcell_comb \z80_|alu_|db[1]~10 ( +// Equation(s): +// \z80_|alu_|db[1]~10_combout = ((\z80_|alu_|db[1]~8_combout & ((\z80_|alu_|db_low[1]~12_combout ) # (!\z80_|execute_|ctl_alu_oe~11_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|execute_|ctl_alu_oe~11_combout ), + .datab(\z80_|alu_|db[7]~9_combout ), + .datac(\z80_|alu_|db_low[1]~12_combout ), + .datad(\z80_|alu_|db[1]~8_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[1]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[1]~10 .lut_mask = 16'hF733; +defparam \z80_|alu_|db[1]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y16_N11 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~12 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~12_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout & (\z80_|alu_|db[1]~10_combout & ((\z80_|reg_file_|b2v_latch_af2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # +// (!\z80_|execute_|ctl_reg_in_hi~12_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .datab(\z80_|alu_|db[1]~10_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~12 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[1]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N4 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder_combout = \z80_|reg_file_|gdfx_temp1[1]~21_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y16_N5 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X35_Y16_N1 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~11 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~11_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datab(\z80_|reg_file_|b2v_latch_iy_hi|latch [1]), + .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~11 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[1]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y16_N11 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X37_Y16_N17 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~10 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~10_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (\z80_|reg_file_|b2v_latch_bc2_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]), + .datad(\z80_|reg_file_|b2v_latch_bc_hi|latch [1]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~10 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[1]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y15_N3 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X35_Y15_N1 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~13 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~13_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (\z80_|reg_file_|b2v_latch_wz_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [1]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [1]), + .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~13 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp1[1]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~14 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~14_combout = (\z80_|reg_file_|gdfx_temp1[1]~12_combout & (\z80_|reg_file_|gdfx_temp1[1]~11_combout & (\z80_|reg_file_|gdfx_temp1[1]~10_combout & \z80_|reg_file_|gdfx_temp1[1]~13_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[1]~12_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[1]~11_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[1]~10_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[1]~13_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~14 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[1]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y15_N25 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N24 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[1]~10 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[1]~10_combout = (\z80_|execute_|ctl_reg_gp_we~8_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [1]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [1]), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[1]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[1]~10 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[1]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y14_N29 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X37_Y14_N11 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~9 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~9_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (\z80_|reg_file_|b2v_latch_hl_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_hl2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (((\z80_|reg_file_|b2v_latch_hl2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [1]), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~9 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[1]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y15_N7 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N20 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_hi|latch[1]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_de_hi|latch[1]~feeder_combout = \z80_|reg_file_|gdfx_temp1[1]~21_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_de_hi|latch[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[1]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y15_N21 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_de_hi|latch[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~8 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~8_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [1]), + .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [1]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~8 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[1]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~15 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~15_combout = (\z80_|reg_file_|gdfx_temp1[1]~14_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[1]~10_combout & (\z80_|reg_file_|gdfx_temp1[1]~9_combout & \z80_|reg_file_|gdfx_temp1[1]~8_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[1]~14_combout ), + .datab(\z80_|reg_file_|b2v_latch_af_hi|db[1]~10_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[1]~9_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[1]~8_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~15 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~21 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[1]~21_combout = ((\z80_|reg_file_|gdfx_temp1[1]~15_combout & ((\z80_|reg_file_|db_hi_as[1]~3_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[1]~15_combout ), + .datac(\z80_|reg_file_|db_hi_as[1]~3_combout ), + .datad(\z80_|execute_|ctl_sw_4u~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[1]~21 .lut_mask = 16'hD5DD; +defparam \z80_|reg_file_|gdfx_temp1[1]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y14_N25 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[1]~3_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N24 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~0 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[1]~0_combout = (\z80_|reg_file_|gdfx_temp1[1]~21_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # (!\z80_|reg_file_|gdfx_temp1[1]~21_combout & +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[1]~21_combout ), + .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[1]~0 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|db_hi_as[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N20 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~1 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[1]~1_combout = (\z80_|reg_file_|db_hi_as[1]~0_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_pc_hi|latch [1]), + .datab(\z80_|reg_file_|db_hi_as[1]~0_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[1]~1 .lut_mask = 16'h88CC; +defparam \z80_|reg_file_|db_hi_as[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N30 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~3 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[1]~3_combout = ((\z80_|reg_file_|db_hi_as[1]~1_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), + .datab(\z80_|reg_file_|db_hi_as[1]~1_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .datad(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[1]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[1]~3 .lut_mask = 16'h8CFF; +defparam \z80_|reg_file_|db_hi_as[1]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N24 +cycloneive_lcell_comb \z80_|address_latch_|abusz[9] ( +// Equation(s): +// \z80_|address_latch_|abusz [9] = (\z80_|reg_file_|db_hi_as[1]~3_combout & !\z80_|resets_|clrpc~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|reg_file_|db_hi_as[1]~3_combout ), + .datad(\z80_|resets_|clrpc~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [9]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[9] .lut_mask = 16'h00F0; +defparam \z80_|address_latch_|abusz[9] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N22 +cycloneive_lcell_comb \z80_|address_latch_|Q[9]~feeder ( +// Equation(s): +// \z80_|address_latch_|Q[9]~feeder_combout = \z80_|address_latch_|abusz [9] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [9]), + .cin(gnd), + .combout(\z80_|address_latch_|Q[9]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|Q[9]~feeder .lut_mask = 16'hFF00; +defparam \z80_|address_latch_|Q[9]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y10_N23 +dffeas \z80_|address_latch_|Q[9] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|Q[9]~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [9]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[9] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N26 +cycloneive_lcell_comb \z80_|address_latch_|abusz[10] ( +// Equation(s): +// \z80_|address_latch_|abusz [10] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[2]~9_combout ) + + .dataa(\z80_|resets_|clrpc~0_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|db_hi_as[2]~9_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [10]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[10] .lut_mask = 16'h5500; +defparam \z80_|address_latch_|abusz[10] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y13_N27 +dffeas \z80_|address_latch_|Q[10] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [10]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [10]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[10] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N12 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout = \z80_|address_latch_|Q [10] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout & (\z80_|execute_|ctl_inc_dec~11_combout $ +// (\z80_|address_latch_|Q [9]))))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), + .datab(\z80_|execute_|ctl_inc_dec~11_combout ), + .datac(\z80_|address_latch_|Q [9]), + .datad(\z80_|address_latch_|Q [10]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out .lut_mask = 16'hD728; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y14_N13 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[2]~9_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N12 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~7 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[2]~7_combout = (\z80_|reg_file_|gdfx_temp1[2]~39_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # (!\z80_|reg_file_|gdfx_temp1[2]~39_combout & +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[2]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[2]~7 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|db_hi_as[2]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y14_N19 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[2]~9_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N8 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~8 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[2]~8_combout = (\z80_|reg_file_|db_hi_as[2]~7_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|db_hi_as[2]~7_combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datac(gnd), + .datad(\z80_|reg_file_|b2v_latch_pc_hi|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[2]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[2]~8 .lut_mask = 16'hAA22; +defparam \z80_|reg_file_|db_hi_as[2]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N18 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~9 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[2]~9_combout = ((\z80_|reg_file_|db_hi_as[2]~8_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .datac(\z80_|reg_file_|db_hi_as[2]~8_combout ), + .datad(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[2]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[2]~9 .lut_mask = 16'hB0FF; +defparam \z80_|reg_file_|db_hi_as[2]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~39 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[2]~39_combout = ((\z80_|reg_file_|gdfx_temp1[2]~38_combout & ((\z80_|reg_file_|db_hi_as[2]~9_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[2]~38_combout ), + .datac(\z80_|reg_file_|db_hi_as[2]~9_combout ), + .datad(\z80_|execute_|ctl_sw_4u~6_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[2]~39 .lut_mask = 16'hD5DD; +defparam \z80_|reg_file_|gdfx_temp1[2]~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N24 +cycloneive_lcell_comb \z80_|alu_|db[2]~15 ( +// Equation(s): +// \z80_|alu_|db[2]~15_combout = (\z80_|execute_|ctl_sw_2d~13_combout & (\z80_|alu_control_|db[2]~29_combout & ((\z80_|reg_file_|gdfx_temp1[2]~39_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) # (!\z80_|execute_|ctl_sw_2d~13_combout & +// ((\z80_|reg_file_|gdfx_temp1[2]~39_combout ) # ((!\z80_|execute_|ctl_reg_out_hi~7_combout )))) + + .dataa(\z80_|execute_|ctl_sw_2d~13_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[2]~39_combout ), + .datac(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .datad(\z80_|alu_control_|db[2]~29_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[2]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[2]~15 .lut_mask = 16'hCF45; +defparam \z80_|alu_|db[2]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N4 +cycloneive_lcell_comb \z80_|alu_|db[2]~16 ( +// Equation(s): +// \z80_|alu_|db[2]~16_combout = ((\z80_|alu_|db[2]~15_combout & ((\z80_|alu_|db_low[2]~23_combout ) # (!\z80_|execute_|ctl_alu_oe~11_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|execute_|ctl_alu_oe~11_combout ), + .datab(\z80_|alu_|db[2]~15_combout ), + .datac(\z80_|alu_|db[7]~9_combout ), + .datad(\z80_|alu_|db_low[2]~23_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[2]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[2]~16 .lut_mask = 16'hCF4F; +defparam \z80_|alu_|db[2]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N24 +cycloneive_lcell_comb \z80_|alu_control_|db[2]~27 ( +// Equation(s): +// \z80_|alu_control_|db[2]~27_combout = (\z80_|alu_|db[2]~16_combout & (!\z80_|alu_flags_|DFFE_inst_latch_pf~q & ((\z80_|execute_|ctl_flags_oe~2_combout )))) # (!\z80_|alu_|db[2]~16_combout & ((\z80_|execute_|ctl_sw_2u~7_combout ) # +// ((!\z80_|alu_flags_|DFFE_inst_latch_pf~q & \z80_|execute_|ctl_flags_oe~2_combout )))) + + .dataa(\z80_|alu_|db[2]~16_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), + .datac(\z80_|execute_|ctl_sw_2u~7_combout ), + .datad(\z80_|execute_|ctl_flags_oe~2_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[2]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[2]~27 .lut_mask = 16'h7350; +defparam \z80_|alu_control_|db[2]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N0 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~2 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_cf~2_combout = (\z80_|execute_|ctl_flags_alu~15_combout & !\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_flags_alu~15_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~2 .lut_mask = 16'h0C0C; +defparam \z80_|alu_flags_|DFFE_inst_latch_cf~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N26 +cycloneive_lcell_comb \z80_|alu_flags_|flags_hf2~0 ( +// Equation(s): +// \z80_|alu_flags_|flags_hf2~0_combout = (\z80_|execute_|ctl_flags_hf2_we~combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ) # ((\z80_|alu_control_|db[4]~32_combout )))) # (!\z80_|execute_|ctl_flags_hf2_we~combout & +// (((\z80_|alu_flags_|flags_hf2~q )))) + + .dataa(\z80_|execute_|ctl_flags_hf2_we~combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ), + .datac(\z80_|alu_flags_|flags_hf2~q ), + .datad(\z80_|alu_control_|db[4]~32_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|flags_hf2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|flags_hf2~0 .lut_mask = 16'hFAD8; +defparam \z80_|alu_flags_|flags_hf2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y18_N27 +dffeas \z80_|alu_flags_|flags_hf2 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|flags_hf2~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|flags_hf2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|flags_hf2 .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|flags_hf2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N30 +cycloneive_lcell_comb \z80_|alu_control_|db[2]~23 ( +// Equation(s): +// \z80_|alu_control_|db[2]~23_combout = ((\z80_|alu_flags_|flags_hf2~q ) # ((\z80_|alu_control_|out[6]~0_combout ) # (\z80_|execute_|ctl_66_oe~combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datab(\z80_|alu_flags_|flags_hf2~q ), + .datac(\z80_|alu_control_|out[6]~0_combout ), + .datad(\z80_|execute_|ctl_66_oe~combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[2]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[2]~23 .lut_mask = 16'hFFFD; +defparam \z80_|alu_control_|db[2]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N30 +cycloneive_lcell_comb \z80_|alu_control_|db[2]~29 ( +// Equation(s): +// \z80_|alu_control_|db[2]~29_combout = ((\z80_|alu_control_|db[2]~28_combout & (!\z80_|alu_control_|db[2]~27_combout & \z80_|alu_control_|db[2]~23_combout ))) # (!\z80_|alu_control_|db[6]~11_combout ) + + .dataa(\z80_|alu_control_|db[2]~28_combout ), + .datab(\z80_|alu_control_|db[2]~27_combout ), + .datac(\z80_|alu_control_|db[2]~23_combout ), + .datad(\z80_|alu_control_|db[6]~11_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[2]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[2]~29 .lut_mask = 16'h20FF; +defparam \z80_|alu_control_|db[2]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~39 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~39_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout & (\z80_|alu_control_|db[2]~29_combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) # +// (!\z80_|execute_|ctl_reg_in_lo~8_combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [2]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) + + .dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datab(\z80_|reg_file_|b2v_latch_sp_lo|latch [2]), + .datac(\z80_|alu_control_|db[2]~29_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~39 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[2]~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y11_N3 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X32_Y11_N21 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~35 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~35_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [2]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [2]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~35 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[2]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~40 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~40_combout = (\z80_|reg_file_|gdfx_temp0[2]~37_combout & (\z80_|reg_file_|gdfx_temp0[2]~38_combout & (\z80_|reg_file_|gdfx_temp0[2]~39_combout & \z80_|reg_file_|gdfx_temp0[2]~35_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[2]~37_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[2]~38_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[2]~39_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[2]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~40 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[2]~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~41 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~41_combout = (\z80_|reg_file_|gdfx_temp0[2]~33_combout & (\z80_|reg_file_|gdfx_temp0[2]~34_combout & \z80_|reg_file_|gdfx_temp0[2]~40_combout )) + + .dataa(\z80_|reg_file_|gdfx_temp0[2]~33_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[2]~34_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[2]~40_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~41 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|gdfx_temp0[2]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~42 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[2]~42_combout = ((\z80_|reg_file_|gdfx_temp0[2]~41_combout & ((\z80_|reg_file_|db_lo_as[2]~9_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[2]~41_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .datad(\z80_|reg_file_|db_lo_as[2]~9_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[2]~42 .lut_mask = 16'hCF4F; +defparam \z80_|reg_file_|gdfx_temp0[2]~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y12_N15 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[2]~9_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[2] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N14 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~7 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[2]~7_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[2]~42_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # +// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[2]~42_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [2]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[2]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[2]~7 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_lo_as[2]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N6 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~8 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[2]~8_combout = (\z80_|reg_file_|db_lo_as[2]~7_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(\z80_|reg_file_|b2v_latch_ir_lo|latch [2]), + .datab(gnd), + .datac(\z80_|reg_file_|db_lo_as[2]~7_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[2]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[2]~8 .lut_mask = 16'hA0F0; +defparam \z80_|reg_file_|db_lo_as[2]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N4 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout = \z80_|address_latch_|Q [0] $ (((\z80_|execute_|ctl_inc_dec~9_combout ) # ((\z80_|execute_|ctl_inc_dec~7_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout )))) + + .dataa(\z80_|execute_|ctl_inc_dec~9_combout ), + .datab(\z80_|address_latch_|Q [0]), + .datac(\z80_|execute_|ctl_inc_dec~6_combout ), + .datad(\z80_|execute_|ctl_inc_dec~7_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 .lut_mask = 16'h3363; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N26 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout & ((\z80_|execute_|ctl_inc_cy~71_combout ) # ((\z80_|execute_|ctl_inc_cy~81_combout ) # +// (\z80_|execute_|ctl_inc_cy~68_combout )))) + + .dataa(\z80_|execute_|ctl_inc_cy~71_combout ), + .datab(\z80_|execute_|ctl_inc_cy~81_combout ), + .datac(\z80_|execute_|ctl_inc_cy~68_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'hFE00; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N0 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout = \z80_|address_latch_|Q [2] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout & +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout ))) + + .dataa(\z80_|address_latch_|Q [2]), + .datab(gnd), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out .lut_mask = 16'h5AAA; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N8 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~9 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[2]~9_combout = ((\z80_|reg_file_|db_lo_as[2]~8_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|reg_file_|db_lo_as[2]~8_combout ), + .datab(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[2]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[2]~9 .lut_mask = 16'hBB3B; +defparam \z80_|reg_file_|db_lo_as[2]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N8 +cycloneive_lcell_comb \z80_|address_latch_|abusz[2] ( +// Equation(s): +// \z80_|address_latch_|abusz [2] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[2]~9_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|clrpc~0_combout ), + .datad(\z80_|reg_file_|db_lo_as[2]~9_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [2]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[2] .lut_mask = 16'h0F00; +defparam \z80_|address_latch_|abusz[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y11_N9 +dffeas \z80_|address_latch_|Q[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [2]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[2] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N18 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout = \z80_|address_latch_|Q [2] $ ((((\z80_|execute_|ctl_inc_dec~10_combout ) # (!\z80_|execute_|ctl_inc_dec~5_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~42_combout ))) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~42_combout ), + .datab(\z80_|address_latch_|Q [2]), + .datac(\z80_|execute_|ctl_inc_dec~10_combout ), + .datad(\z80_|execute_|ctl_inc_dec~5_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42 .lut_mask = 16'h3933; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y12_N25 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[3]~12_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N24 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~10 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[3]~10_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[3]~52_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # +// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[3]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[3]~10 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_lo_as[3]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y12_N31 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[3]~12_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N28 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~11 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[3]~11_combout = (\z80_|reg_file_|db_lo_as[3]~10_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .datab(\z80_|reg_file_|db_lo_as[3]~10_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [3]), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[3]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[3]~11 .lut_mask = 16'hCC44; +defparam \z80_|reg_file_|db_lo_as[3]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N26 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout = \z80_|address_latch_|Q [3] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout & +// (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout )))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout ), + .datab(\z80_|address_latch_|Q [3]), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out .lut_mask = 16'h6CCC; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N30 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~12 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[3]~12_combout = ((\z80_|reg_file_|db_lo_as[3]~11_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .datab(\z80_|reg_file_|db_lo_as[3]~11_combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), + .datad(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[3]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[3]~12 .lut_mask = 16'hC4FF; +defparam \z80_|reg_file_|db_lo_as[3]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N14 +cycloneive_lcell_comb \z80_|address_latch_|abusz[3] ( +// Equation(s): +// \z80_|address_latch_|abusz [3] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[3]~12_combout ) + + .dataa(gnd), + .datab(\z80_|resets_|clrpc~0_combout ), + .datac(\z80_|reg_file_|db_lo_as[3]~12_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [3]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[3] .lut_mask = 16'h3030; +defparam \z80_|address_latch_|abusz[3] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y11_N15 +dffeas \z80_|address_latch_|Q[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_latch_|abusz [3]), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_al_we~12_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_latch_|Q [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_latch_|Q[3] .is_wysiwyg = "true"; +defparam \z80_|address_latch_|Q[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N24 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout = \z80_|address_latch_|Q [3] $ ((((\z80_|execute_|ctl_inc_dec~10_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~42_combout )) # (!\z80_|execute_|ctl_inc_dec~5_combout ))) + + .dataa(\z80_|execute_|ctl_inc_dec~5_combout ), + .datab(\z80_|address_latch_|Q [3]), + .datac(\z80_|execute_|ctl_inc_dec~10_combout ), + .datad(\z80_|execute_|ctl_bus_inc_oe~42_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4 .lut_mask = 16'h3933; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N10 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout & +// (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout ))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 .lut_mask = 16'h8000; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N16 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout = (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|address_latch_|Q [6] $ (((\z80_|execute_|ctl_inc_dec~7_combout ) # (\z80_|execute_|ctl_inc_dec~10_combout ))))) + + .dataa(\z80_|address_latch_|Q [6]), + .datab(\z80_|execute_|ctl_inc_dec~7_combout ), + .datac(\z80_|execute_|ctl_inc_dec~10_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 .lut_mask = 16'h0056; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y11_N14 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout & +// (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 .lut_mask = 16'h8000; +defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N22 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout & ((\z80_|address_latch_|Q [8] & (!\z80_|execute_|ctl_inc_dec~11_combout & \z80_|address_latch_|Q +// [7])) # (!\z80_|address_latch_|Q [8] & (\z80_|execute_|ctl_inc_dec~11_combout & !\z80_|address_latch_|Q [7])))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ), + .datab(\z80_|address_latch_|Q [8]), + .datac(\z80_|execute_|ctl_inc_dec~11_combout ), + .datad(\z80_|address_latch_|Q [7]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 .lut_mask = 16'h0820; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N28 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout & ((\z80_|execute_|ctl_inc_dec~11_combout & (!\z80_|address_latch_|Q [9] & +// !\z80_|address_latch_|Q [10])) # (!\z80_|execute_|ctl_inc_dec~11_combout & (\z80_|address_latch_|Q [9] & \z80_|address_latch_|Q [10])))) + + .dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ), + .datab(\z80_|execute_|ctl_inc_dec~11_combout ), + .datac(\z80_|address_latch_|Q [9]), + .datad(\z80_|address_latch_|Q [10]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 .lut_mask = 16'h2008; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N26 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[11] ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|address [11] = \z80_|address_latch_|Q [11] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|address_latch_|Q [11]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[11] .lut_mask = 16'h0FF0; +defparam \z80_|address_latch_|b2v_inst_inc_dec|address[11] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N4 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~12 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[3]~12_combout = ((\z80_|reg_file_|db_hi_as[3]~11_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [11]) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datab(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .datac(\z80_|reg_file_|db_hi_as[3]~11_combout ), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[3]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[3]~12 .lut_mask = 16'hF575; +defparam \z80_|reg_file_|db_hi_as[3]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y14_N17 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X37_Y14_N31 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~41 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~41_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (\z80_|reg_file_|b2v_latch_hl_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_hl2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (((\z80_|reg_file_|b2v_latch_hl2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [3]), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~41 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[3]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y15_N5 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X35_Y15_N7 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~45 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~45_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (\z80_|reg_file_|b2v_latch_wz_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (((\z80_|reg_file_|b2v_latch_sp_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [3]), + .datad(\z80_|reg_file_|b2v_latch_sp_hi|latch [3]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~45 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp1[3]~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y16_N23 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~44 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~44_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout & (\z80_|alu_|db[3]~20_combout & ((\z80_|reg_file_|b2v_latch_af2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # +// (!\z80_|execute_|ctl_reg_in_hi~12_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .datab(\z80_|alu_|db[3]~20_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~44 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[3]~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y16_N19 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y16_N9 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~43 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~43_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [3]), + .datad(\z80_|reg_file_|b2v_latch_iy_hi|latch [3]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~43 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[3]~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y16_N9 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X37_Y16_N7 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~42 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~42_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (\z80_|reg_file_|b2v_latch_bc2_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [3]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_bc_hi|latch [3]), + .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~42_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~42 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp1[3]~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~46 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~46_combout = (\z80_|reg_file_|gdfx_temp1[3]~45_combout & (\z80_|reg_file_|gdfx_temp1[3]~44_combout & (\z80_|reg_file_|gdfx_temp1[3]~43_combout & \z80_|reg_file_|gdfx_temp1[3]~42_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[3]~45_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[3]~44_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[3]~43_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[3]~42_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~46 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[3]~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N8 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_hi|latch[3]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_de_hi|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp1[3]~48_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_de_hi|latch[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[3]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y15_N9 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_de_hi|latch[3]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X37_Y15_N27 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~40 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~40_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datab(\z80_|reg_file_|b2v_latch_de_hi|latch [3]), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~40 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[3]~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y15_N21 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N10 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[3]~13 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[3]~13_combout = (\z80_|execute_|ctl_reg_gp_we~8_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [3]) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout )) # (!\z80_|reg_control_|reg_sel_af~0_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(\z80_|reg_control_|reg_sel_af~0_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datad(\z80_|reg_file_|b2v_latch_af_hi|latch [3]), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[3]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[3]~13 .lut_mask = 16'hFFBF; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[3]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~47 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~47_combout = (\z80_|reg_file_|gdfx_temp1[3]~41_combout & (\z80_|reg_file_|gdfx_temp1[3]~46_combout & (\z80_|reg_file_|gdfx_temp1[3]~40_combout & \z80_|reg_file_|b2v_latch_af_hi|db[3]~13_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[3]~41_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[3]~46_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[3]~40_combout ), + .datad(\z80_|reg_file_|b2v_latch_af_hi|db[3]~13_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~47_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~47 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[3]~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~48 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[3]~48_combout = ((\z80_|reg_file_|gdfx_temp1[3]~47_combout & ((\z80_|reg_file_|db_hi_as[3]~12_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[3]~12_combout ), + .datab(\z80_|execute_|ctl_sw_4u~6_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[3]~47_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[3]~48 .lut_mask = 16'hBF0F; +defparam \z80_|reg_file_|gdfx_temp1[3]~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N6 +cycloneive_lcell_comb \z80_|alu_|db[3]~19 ( +// Equation(s): +// \z80_|alu_|db[3]~19_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[3]~48_combout & ((\z80_|alu_|db_low[3]~25_combout ) # (!\z80_|execute_|ctl_alu_oe~11_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & +// ((\z80_|alu_|db_low[3]~25_combout ) # ((!\z80_|execute_|ctl_alu_oe~11_combout )))) + + .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .datab(\z80_|alu_|db_low[3]~25_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[3]~48_combout ), + .datad(\z80_|execute_|ctl_alu_oe~11_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[3]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[3]~19 .lut_mask = 16'hC4F5; +defparam \z80_|alu_|db[3]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N28 +cycloneive_lcell_comb \z80_|alu_|db[3]~20 ( +// Equation(s): +// \z80_|alu_|db[3]~20_combout = ((\z80_|alu_|db[3]~19_combout & ((\z80_|alu_control_|db[3]~35_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|alu_control_|db[3]~35_combout ), + .datab(\z80_|alu_|db[7]~9_combout ), + .datac(\z80_|execute_|ctl_sw_2d~13_combout ), + .datad(\z80_|alu_|db[3]~19_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[3]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[3]~20 .lut_mask = 16'hBF33; +defparam \z80_|alu_|db[3]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N18 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~21 ( +// Equation(s): +// \z80_|alu_|db_low[2]~21_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[3]~20_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[1]~10_combout ))) + + .dataa(\z80_|alu_|db[3]~20_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(gnd), + .datad(\z80_|alu_|db[1]~10_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[2]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[2]~21 .lut_mask = 16'hBB88; +defparam \z80_|alu_|db_low[2]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N12 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~22 ( +// Equation(s): +// \z80_|alu_|db_low[2]~22_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_low[2]~21_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[2]~16_combout ))) + + .dataa(gnd), + .datab(\z80_|alu_|db_low[2]~21_combout ), + .datac(\z80_|alu_|db[2]~16_combout ), + .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[2]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[2]~22 .lut_mask = 16'hCCF0; +defparam \z80_|alu_|db_low[2]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y17_N1 +dffeas \z80_|alu_|result_lo[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_alu_op_low~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|result_lo [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|result_lo[2] .is_wysiwyg = "true"; +defparam \z80_|alu_|result_lo[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N10 +cycloneive_lcell_comb \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 ( +// Equation(s): +// \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout = (\z80_|bus_control_|db[4]~19_combout & !\z80_|bus_control_|db[3]~21_combout ) + + .dataa(gnd), + .datab(\z80_|bus_control_|db[4]~19_combout ), + .datac(\z80_|bus_control_|db[3]~21_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 .lut_mask = 16'h0C0C; +defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N22 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~6 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~6_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [2])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [2]))))) + + .dataa(\z80_|alu_|op1_low [2]), + .datab(\z80_|execute_|ctl_alu_op_low~combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datad(\z80_|alu_|op1_high [2]), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~6 .lut_mask = 16'hB080; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N30 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~7 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~7_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~6_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~8_combout & \z80_|alu_|db_low[2]~23_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datac(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~6_combout ), + .datad(\z80_|alu_|db_low[2]~23_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~7 .lut_mask = 16'h3230; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y18_N31 +dffeas \z80_|alu_|op2_low[2] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~7_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_low [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_low[2] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_low[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N6 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~18 ( +// Equation(s): +// \z80_|alu_|db_low[2]~18_combout = (\z80_|execute_|ctl_alu_op2_oe~0_combout & (\z80_|alu_|op2_low [2] & ((\z80_|alu_|op1_low [2]) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_low [2]) # +// ((!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datab(\z80_|alu_|op1_low [2]), + .datac(\z80_|alu_|op2_low [2]), + .datad(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[2]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[2]~18 .lut_mask = 16'hC4F5; +defparam \z80_|alu_|db_low[2]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N22 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~19 ( +// Equation(s): +// \z80_|alu_|db_low[2]~19_combout = (\z80_|alu_|db_low[2]~18_combout & (((\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout & !\z80_|bus_control_|db[5]~15_combout )) # (!\z80_|execute_|ctl_alu_bs_oe~combout ))) + + .dataa(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), + .datab(\z80_|bus_control_|db[5]~15_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datad(\z80_|alu_|db_low[2]~18_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[2]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[2]~19 .lut_mask = 16'h2F00; +defparam \z80_|alu_|db_low[2]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N0 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~20 ( +// Equation(s): +// \z80_|alu_|db_low[2]~20_combout = (\z80_|alu_|db_low[2]~19_combout & ((\z80_|execute_|ctl_alu_res_oe~3_combout ) # (\z80_|alu_|result_lo [2]))) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_res_oe~3_combout ), + .datac(\z80_|alu_|result_lo [2]), + .datad(\z80_|alu_|db_low[2]~19_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[2]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[2]~20 .lut_mask = 16'hFC00; +defparam \z80_|alu_|db_low[2]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N2 +cycloneive_lcell_comb \z80_|alu_|db_low[2]~23 ( +// Equation(s): +// \z80_|alu_|db_low[2]~23_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout & (\z80_|alu_|db_low[2]~22_combout & ((\z80_|alu_|db_low[2]~20_combout )))) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout & (((\z80_|alu_|db_low[2]~20_combout ) # +// (!\z80_|alu_|db_high[3]~0_combout )))) + + .dataa(\z80_|alu_|db_low[2]~22_combout ), + .datab(\z80_|alu_|db_high[3]~0_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datad(\z80_|alu_|db_low[2]~20_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[2]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[2]~23 .lut_mask = 16'hAF03; +defparam \z80_|alu_|db_low[2]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N2 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~7 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~7_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & ((\z80_|alu_|db_low[2]~23_combout ) # ((\z80_|alu_|db_high[2]~13_combout & \z80_|execute_|ctl_alu_op1_sel_low~combout )))) # +// (!\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & (((\z80_|alu_|db_high[2]~13_combout & \z80_|execute_|ctl_alu_op1_sel_low~combout )))) + + .dataa(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ), + .datab(\z80_|alu_|db_low[2]~23_combout ), + .datac(\z80_|alu_|db_high[2]~13_combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_low~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~7 .lut_mask = 16'hF888; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N10 +cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~8 ( +// Equation(s): +// \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~8_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~7_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_alu_op1_sel_zero~combout ), + .datad(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~7_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~8 .lut_mask = 16'h0F00; +defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y17_N11 +dffeas \z80_|alu_|op1_low[2] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~8_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op1_low [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op1_low[2] .is_wysiwyg = "true"; +defparam \z80_|alu_|op1_low[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N26 +cycloneive_lcell_comb \z80_|alu_|alu_op1[2]~1 ( +// Equation(s): +// \z80_|alu_|alu_op1[2]~1_combout = (\z80_|execute_|ctl_alu_op_low~41_combout & (\z80_|alu_|op1_low [2])) # (!\z80_|execute_|ctl_alu_op_low~41_combout & ((\z80_|execute_|ctl_alu_op_low~29_combout & ((\z80_|alu_|op1_high [2]))) # +// (!\z80_|execute_|ctl_alu_op_low~29_combout & (\z80_|alu_|op1_low [2])))) + + .dataa(\z80_|alu_|op1_low [2]), + .datab(\z80_|execute_|ctl_alu_op_low~41_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~29_combout ), + .datad(\z80_|alu_|op1_high [2]), + .cin(gnd), + .combout(\z80_|alu_|alu_op1[2]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op1[2]~1 .lut_mask = 16'hBA8A; +defparam \z80_|alu_|alu_op1[2]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N30 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout = (\z80_|execute_|ctl_alu_core_S~combout ) # ((\z80_|alu_|alu_op1[2]~1_combout & \z80_|alu_|alu_op2[2]~0_combout )) + + .dataa(\z80_|alu_|alu_op1[2]~1_combout ), + .datab(gnd), + .datac(\z80_|alu_|alu_op2[2]~0_combout ), + .datad(\z80_|execute_|ctl_alu_core_S~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hFFA0; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N8 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout = (!\z80_|alu_|alu_op2[2]~0_combout & ((\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_low [2])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_high +// [2]))))) + + .dataa(\z80_|alu_|alu_op2[2]~0_combout ), + .datab(\z80_|alu_|op1_low [2]), + .datac(\z80_|alu_|op1_high [2]), + .datad(\z80_|execute_|ctl_alu_op_low~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h1105; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N20 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout = (!\z80_|execute_|ctl_alu_core_R~combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ) # +// ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout & !\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout )))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ), + .datab(\z80_|execute_|ctl_alu_core_R~combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 .lut_mask = 16'h3031; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N16 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ) # +// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), + .datab(\z80_|execute_|ctl_alu_core_R~combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 .lut_mask = 16'hDCDD; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N20 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout = (!\z80_|alu_|alu_op2[3]~2_combout & ((\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_low [3])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_high +// [3]))))) + + .dataa(\z80_|alu_|op1_low [3]), + .datab(\z80_|alu_|alu_op2[3]~2_combout ), + .datac(\z80_|alu_|op1_high [3]), + .datad(\z80_|execute_|ctl_alu_op_low~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h1103; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N10 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ) # +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout )))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .datac(\z80_|execute_|ctl_alu_core_R~combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0 .lut_mask = 16'hF5F4; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N6 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_hf~0 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_hf~0_combout = (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & (\z80_|execute_|ctl_flags_bus~combout & ((\z80_|alu_control_|db[4]~32_combout )))) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout +// & ((\z80_|execute_|ctl_flags_alu~15_combout ) # ((\z80_|execute_|ctl_flags_bus~combout & \z80_|alu_control_|db[4]~32_combout )))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), + .datab(\z80_|execute_|ctl_flags_bus~combout ), + .datac(\z80_|execute_|ctl_flags_alu~15_combout ), + .datad(\z80_|alu_control_|db[4]~32_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_hf~0 .lut_mask = 16'hDC50; +defparam \z80_|alu_flags_|DFFE_inst_latch_hf~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y19_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_we~3_combout = (\z80_|pla_decode_|Equal11~0_combout & (((\z80_|nM1_int~2_combout ) # (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) # (!\z80_|pla_decode_|Equal11~0_combout & (\z80_|pla_decode_|Equal10~0_combout & +// ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) + + .dataa(\z80_|pla_decode_|Equal10~0_combout ), + .datab(\z80_|pla_decode_|Equal11~0_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_we~3 .lut_mask = 16'hEEC0; +defparam \z80_|execute_|ctl_flags_hf_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_flags_hf_we~4_combout = ((\z80_|execute_|ctl_flags_sz_we~6_combout ) # ((\z80_|execute_|ctl_flags_hf_we~3_combout ) # (!\z80_|execute_|ctl_flags_alu~14_combout ))) # (!\z80_|execute_|ctl_flags_xy_we~8_combout ) + + .dataa(\z80_|execute_|ctl_flags_xy_we~8_combout ), + .datab(\z80_|execute_|ctl_flags_sz_we~6_combout ), + .datac(\z80_|execute_|ctl_flags_alu~14_combout ), + .datad(\z80_|execute_|ctl_flags_hf_we~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_hf_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_hf_we~4 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|ctl_flags_hf_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N28 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_hf~1 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_hf~1_combout = (\z80_|execute_|ctl_flags_hf_we~2_combout & ((\z80_|execute_|ctl_flags_hf_we~4_combout & (\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout )) # (!\z80_|execute_|ctl_flags_hf_we~4_combout & +// ((\z80_|alu_flags_|DFFE_inst_latch_hf~q ))))) # (!\z80_|execute_|ctl_flags_hf_we~2_combout & (\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout )) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ), + .datab(\z80_|execute_|ctl_flags_hf_we~2_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), + .datad(\z80_|execute_|ctl_flags_hf_we~4_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_hf~1 .lut_mask = 16'hAAE2; +defparam \z80_|alu_flags_|DFFE_inst_latch_hf~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y18_N29 +dffeas \z80_|alu_flags_|DFFE_inst_latch_hf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_hf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_hf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N16 +cycloneive_lcell_comb \z80_|alu_flags_|flags_hf ( +// Equation(s): +// \z80_|alu_flags_|flags_hf~combout = \z80_|alu_flags_|DFFE_inst_latch_hf~q $ (((\z80_|execute_|ctl_flags_hf_cpl~13_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout & !\z80_|alu_flags_|flags_cf~combout )))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), + .datab(\z80_|execute_|ctl_flags_hf_cpl~13_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_hf~q ), + .datad(\z80_|alu_flags_|flags_cf~combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|flags_hf~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|flags_hf .lut_mask = 16'h3C1E; +defparam \z80_|alu_flags_|flags_hf .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N16 +cycloneive_lcell_comb \z80_|alu_control_|db[4]~30 ( +// Equation(s): +// \z80_|alu_control_|db[4]~30_combout = (\z80_|alu_|db[4]~18_combout & (!\z80_|reg_file_|gdfx_temp0[4]~62_combout & ((\z80_|execute_|ctl_reg_out_lo~8_combout )))) # (!\z80_|alu_|db[4]~18_combout & ((\z80_|execute_|ctl_sw_2u~7_combout ) # +// ((!\z80_|reg_file_|gdfx_temp0[4]~62_combout & \z80_|execute_|ctl_reg_out_lo~8_combout )))) + + .dataa(\z80_|alu_|db[4]~18_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), + .datac(\z80_|execute_|ctl_sw_2u~7_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[4]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[4]~30 .lut_mask = 16'h7350; +defparam \z80_|alu_control_|db[4]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N10 +cycloneive_lcell_comb \z80_|alu_control_|db[4]~31 ( +// Equation(s): +// \z80_|alu_control_|db[4]~31_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & (!\z80_|alu_control_|db[4]~30_combout & ((\z80_|alu_flags_|flags_hf~combout ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) + + .dataa(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .datab(\z80_|alu_flags_|flags_hf~combout ), + .datac(\z80_|execute_|ctl_flags_oe~2_combout ), + .datad(\z80_|alu_control_|db[4]~30_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[4]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[4]~31 .lut_mask = 16'h008A; +defparam \z80_|alu_control_|db[4]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N2 +cycloneive_lcell_comb \z80_|alu_control_|db[4]~32 ( +// Equation(s): +// \z80_|alu_control_|db[4]~32_combout = ((\z80_|alu_control_|db[4]~31_combout & ((\z80_|bus_control_|db[4]~19_combout ) # (!\z80_|execute_|ctl_sw_1d~7_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) + + .dataa(\z80_|bus_control_|db[4]~19_combout ), + .datab(\z80_|alu_control_|db[4]~31_combout ), + .datac(\z80_|execute_|ctl_sw_1d~7_combout ), + .datad(\z80_|alu_control_|db[6]~11_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[4]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[4]~32 .lut_mask = 16'h8CFF; +defparam \z80_|alu_control_|db[4]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N26 +cycloneive_lcell_comb \z80_|alu_|db[4]~17 ( +// Equation(s): +// \z80_|alu_|db[4]~17_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[4]~66_combout & ((\z80_|alu_control_|db[4]~32_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout & +// ((\z80_|alu_control_|db[4]~32_combout ) # ((!\z80_|execute_|ctl_sw_2d~13_combout )))) + + .dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .datab(\z80_|alu_control_|db[4]~32_combout ), + .datac(\z80_|execute_|ctl_sw_2d~13_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[4]~66_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[4]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[4]~17 .lut_mask = 16'hCF45; +defparam \z80_|alu_|db[4]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N16 +cycloneive_lcell_comb \z80_|alu_|db[4]~18 ( +// Equation(s): +// \z80_|alu_|db[4]~18_combout = ((\z80_|alu_|db[4]~17_combout & ((\z80_|alu_|db_high[0]~25_combout ) # (!\z80_|execute_|ctl_alu_oe~11_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|execute_|ctl_alu_oe~11_combout ), + .datab(\z80_|alu_|db[7]~9_combout ), + .datac(\z80_|alu_|db[4]~17_combout ), + .datad(\z80_|alu_|db_high[0]~25_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[4]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[4]~18 .lut_mask = 16'hF373; +defparam \z80_|alu_|db[4]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N16 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~13 ( +// Equation(s): +// \z80_|alu_|db_low[3]~13_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[4]~18_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[2]~16_combout ))) + + .dataa(\z80_|alu_|db[4]~18_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(gnd), + .datad(\z80_|alu_|db[2]~16_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~13 .lut_mask = 16'hBB88; +defparam \z80_|alu_|db_low[3]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N10 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~14 ( +// Equation(s): +// \z80_|alu_|db_low[3]~14_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_low[3]~13_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[3]~20_combout )))) # +// (!\z80_|execute_|ctl_alu_shift_oe~43_combout ) + + .dataa(\z80_|alu_|db_low[3]~13_combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datad(\z80_|alu_|db[3]~20_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~14 .lut_mask = 16'hBF8F; +defparam \z80_|alu_|db_low[3]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N24 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~17 ( +// Equation(s): +// \z80_|alu_|db_low[3]~17_combout = (\z80_|alu_|db_low[3]~16_combout & (\z80_|alu_|db_low[3]~14_combout & ((\z80_|execute_|ctl_alu_res_oe~3_combout ) # (\z80_|alu_|result_lo [3])))) + + .dataa(\z80_|execute_|ctl_alu_res_oe~3_combout ), + .datab(\z80_|alu_|db_low[3]~16_combout ), + .datac(\z80_|alu_|result_lo [3]), + .datad(\z80_|alu_|db_low[3]~14_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~17 .lut_mask = 16'hC800; +defparam \z80_|alu_|db_low[3]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N14 +cycloneive_lcell_comb \z80_|alu_|db_low[3]~25 ( +// Equation(s): +// \z80_|alu_|db_low[3]~25_combout = (\z80_|alu_|db_low[3]~17_combout ) # ((!\z80_|alu_|db_high[3]~0_combout & !\z80_|execute_|ctl_alu_shift_oe~43_combout )) + + .dataa(gnd), + .datab(\z80_|alu_|db_high[3]~0_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datad(\z80_|alu_|db_low[3]~17_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_low[3]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_low[3]~25 .lut_mask = 16'hFF03; +defparam \z80_|alu_|db_low[3]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N24 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~4 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~4_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [3]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [3])))) + + .dataa(\z80_|alu_|op1_high [3]), + .datab(\z80_|execute_|ctl_alu_op_low~combout ), + .datac(\z80_|alu_|op1_low [3]), + .datad(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~4 .lut_mask = 16'hE200; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N28 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~5 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~5_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~4_combout ) # ((\z80_|alu_|db_low[3]~25_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) + + .dataa(\z80_|alu_|db_low[3]~25_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datac(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .datad(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~4_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~5 .lut_mask = 16'h3320; +defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y18_N29 +dffeas \z80_|alu_|op2_low[3] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~5_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_low [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_low[3] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_low[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N12 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~8_combout & ((\z80_|alu_|db_high[3]~7_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_lq~combout & \z80_|alu_|db_low[3]~25_combout )))) # +// (!\z80_|execute_|ctl_alu_op2_sel_bus~8_combout & (\z80_|execute_|ctl_alu_op2_sel_lq~combout & (\z80_|alu_|db_low[3]~25_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ), + .datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ), + .datac(\z80_|alu_|db_low[3]~25_combout ), + .datad(\z80_|alu_|db_high[3]~7_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0 .lut_mask = 16'hEAC0; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y18_N20 +cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1 ( +// Equation(s): +// \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_alu_op2_sel_zero~combout ), + .datac(gnd), + .datad(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1 .lut_mask = 16'h3300; +defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y18_N21 +dffeas \z80_|alu_|op2_high[3] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_|op2_high [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_|op2_high[3] .is_wysiwyg = "true"; +defparam \z80_|alu_|op2_high[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N2 +cycloneive_lcell_comb \z80_|alu_|alu_op2[3]~2 ( +// Equation(s): +// \z80_|alu_|alu_op2[3]~2_combout = \z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [3]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [3])))) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .datab(\z80_|alu_|op2_low [3]), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), + .datad(\z80_|alu_|op2_high [3]), + .cin(gnd), + .combout(\z80_|alu_|alu_op2[3]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op2[3]~2 .lut_mask = 16'h1EB4; +defparam \z80_|alu_|alu_op2[3]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N22 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ) # +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout )))) # (!\z80_|execute_|ctl_alu_core_R~5_combout ) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ), + .datac(\z80_|execute_|ctl_alu_core_R~5_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1 .lut_mask = 16'h5F4F; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N20 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout = (\z80_|alu_|alu_op2[3]~2_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout ) # ((\z80_|alu_|alu_op1[3]~2_combout & +// !\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout )))) # (!\z80_|alu_|alu_op2[3]~2_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_|alu_op1[3]~2_combout ) # +// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout )))) + + .dataa(\z80_|alu_|alu_op2[3]~2_combout ), + .datab(\z80_|alu_|alu_op1[3]~2_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 .lut_mask = 16'hEF08; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N14 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~3 ( +// Equation(s): +// \z80_|alu_|db_high[3]~3_combout = (\z80_|execute_|ctl_alu_op2_oe~0_combout & (\z80_|alu_|op2_high [3] & ((\z80_|alu_|op1_high [3]) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout & (((\z80_|alu_|op1_high +// [3]) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op2_oe~0_combout ), + .datab(\z80_|alu_|op2_high [3]), + .datac(\z80_|alu_|op1_high [3]), + .datad(\z80_|execute_|ctl_alu_op1_oe~1_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~3 .lut_mask = 16'hD0DD; +defparam \z80_|alu_|db_high[3]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N18 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~4 ( +// Equation(s): +// \z80_|alu_|db_high[3]~4_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[6]~22_combout )) + + .dataa(\z80_|alu_|db[6]~22_combout ), + .datab(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ), + .datac(gnd), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~4 .lut_mask = 16'hCCAA; +defparam \z80_|alu_|db_high[3]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N28 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~5 ( +// Equation(s): +// \z80_|alu_|db_high[3]~5_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_high[3]~4_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[7]~12_combout )) + + .dataa(\z80_|alu_|db[7]~12_combout ), + .datab(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), + .datac(gnd), + .datad(\z80_|alu_|db_high[3]~4_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~5 .lut_mask = 16'hEE22; +defparam \z80_|alu_|db_high[3]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N28 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~2 ( +// Equation(s): +// \z80_|alu_|db_high[3]~2_combout = ((\z80_|bus_control_|db[3]~21_combout & (\z80_|bus_control_|db[5]~15_combout & \z80_|bus_control_|db[4]~19_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout ) + + .dataa(\z80_|bus_control_|db[3]~21_combout ), + .datab(\z80_|bus_control_|db[5]~15_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~combout ), + .datad(\z80_|bus_control_|db[4]~19_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~2 .lut_mask = 16'h8F0F; +defparam \z80_|alu_|db_high[3]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y16_N0 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~6 ( +// Equation(s): +// \z80_|alu_|db_high[3]~6_combout = (\z80_|alu_|db_high[3]~3_combout & (\z80_|alu_|db_high[3]~2_combout & ((\z80_|alu_|db_high[3]~5_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout )))) + + .dataa(\z80_|alu_|db_high[3]~3_combout ), + .datab(\z80_|alu_|db_high[3]~5_combout ), + .datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ), + .datad(\z80_|alu_|db_high[3]~2_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~6 .lut_mask = 16'h8A00; +defparam \z80_|alu_|db_high[3]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y16_N22 +cycloneive_lcell_comb \z80_|alu_|db_high[3]~7 ( +// Equation(s): +// \z80_|alu_|db_high[3]~7_combout = ((\z80_|alu_|db_high[3]~6_combout & ((\z80_|execute_|ctl_alu_res_oe~3_combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout )))) # (!\z80_|alu_|db_high[3]~1_combout ) + + .dataa(\z80_|execute_|ctl_alu_res_oe~3_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), + .datac(\z80_|alu_|db_high[3]~1_combout ), + .datad(\z80_|alu_|db_high[3]~6_combout ), + .cin(gnd), + .combout(\z80_|alu_|db_high[3]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db_high[3]~7 .lut_mask = 16'hEF0F; +defparam \z80_|alu_|db_high[3]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N24 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_34 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout = (\z80_|execute_|ctl_flags_bus~combout & ((\z80_|alu_control_|db[7]~19_combout ) # ((\z80_|alu_|db_high[3]~7_combout & \z80_|execute_|ctl_flags_alu~15_combout )))) # (!\z80_|execute_|ctl_flags_bus~combout +// & (((\z80_|alu_|db_high[3]~7_combout & \z80_|execute_|ctl_flags_alu~15_combout )))) + + .dataa(\z80_|execute_|ctl_flags_bus~combout ), + .datab(\z80_|alu_control_|db[7]~19_combout ), + .datac(\z80_|alu_|db_high[3]~7_combout ), + .datad(\z80_|execute_|ctl_flags_alu~15_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_34 .lut_mask = 16'hF888; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y16_N25 +dffeas \z80_|alu_flags_|DFFE_inst_latch_sf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_flags_sz_we~8_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_sf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_sf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~5 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~5_combout = ((\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # (\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout )))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ) + + .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~5 .lut_mask = 16'hEF0F; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~7 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~7_combout = (\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ) # ((\z80_|pla_decode_|Equal61~2_combout & ((\z80_|nM1_int~2_combout ) # (\z80_|execute_|ctl_eval_cond~0_combout )))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), + .datac(\z80_|pla_decode_|Equal61~2_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~7 .lut_mask = 16'hFCEC; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout = (\z80_|pla_decode_|Equal13~0_combout & (\z80_|execute_|ctl_alu_op_low~22_combout & (\z80_|pla_decode_|Equal55~0_combout & !\z80_|ir_|opcode [3]))) + + .dataa(\z80_|pla_decode_|Equal13~0_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datac(\z80_|pla_decode_|Equal55~0_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~6 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~6_combout = (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # ((\z80_|execute_|ixy_d~7_combout ) # (\z80_|nM1_int~2_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ixy_d~7_combout ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|nM1_int~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~6 .lut_mask = 16'hF0E0; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~8 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~8_combout = ((\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ) # (\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ))) # (!\z80_|execute_|ctl_alu_op_low~48_combout +// ) + + .dataa(\z80_|execute_|ctl_alu_op_low~48_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~8 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~11 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~11_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ) # (((\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~10_combout )) # (!\z80_|execute_|ctl_alu_sel_op2_neg~9_combout )) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~11 .lut_mask = 16'hFFBF; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~12 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~12_combout = (((\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ) # (\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout )) # (!\z80_|execute_|ctl_alu_sel_op2_neg~2_combout )) # (!\z80_|execute_|ctl_reg_out_hi~4_combout +// ) + + .dataa(\z80_|execute_|ctl_reg_out_hi~4_combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ), + .datad(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~12 .lut_mask = 16'hFFF7; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~15 ( +// Equation(s): +// \z80_|execute_|ctl_alu_sel_op2_neg~15_combout = ((\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_sf~q & \z80_|execute_|ctl_alu_sel_op2_neg~12_combout ))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), + .datac(\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_sel_op2_neg~15 .lut_mask = 16'hFDF5; +defparam \z80_|execute_|ctl_alu_sel_op2_neg~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N26 +cycloneive_lcell_comb \z80_|alu_|alu_op2[2]~0 ( +// Equation(s): +// \z80_|alu_|alu_op2[2]~0_combout = \z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [2]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [2])))) + + .dataa(\z80_|execute_|ctl_alu_sel_op2_high~combout ), + .datab(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ), + .datac(\z80_|alu_|op2_low [2]), + .datad(\z80_|alu_|op2_high [2]), + .cin(gnd), + .combout(\z80_|alu_|alu_op2[2]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_op2[2]~0 .lut_mask = 16'h369C; +defparam \z80_|alu_|alu_op2[2]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N18 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ) # +// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) # (!\z80_|execute_|ctl_alu_core_R~5_combout ) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ), + .datac(\z80_|execute_|ctl_alu_core_R~5_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 .lut_mask = 16'h4F5F; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N24 +cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 ( +// Equation(s): +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout = (\z80_|alu_|alu_op2[2]~0_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ) # ((\z80_|alu_|alu_op1[2]~1_combout & +// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) # (!\z80_|alu_|alu_op2[2]~0_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_|alu_op1[2]~1_combout ) # +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) + + .dataa(\z80_|alu_|alu_op2[2]~0_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ), + .datac(\z80_|alu_|alu_op1[2]~1_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 .lut_mask = 16'hECC8; +defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y17_N11 +dffeas \z80_|alu_control_|DFFE_latch_pf_tmp ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|alu_parity_out~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_alu_op_low~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_control_|DFFE_latch_pf_tmp~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_control_|DFFE_latch_pf_tmp .is_wysiwyg = "true"; +defparam \z80_|alu_control_|DFFE_latch_pf_tmp .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N8 +cycloneive_lcell_comb \z80_|alu_|alu_parity_out~0 ( +// Equation(s): +// \z80_|alu_|alu_parity_out~0_combout = \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout $ (((\z80_|execute_|ctl_alu_op_low~29_combout & (!\z80_|alu_control_|DFFE_latch_pf_tmp~q & !\z80_|execute_|ctl_alu_op_low~41_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~29_combout ), + .datab(\z80_|alu_control_|DFFE_latch_pf_tmp~q ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~41_combout ), + .cin(gnd), + .combout(\z80_|alu_|alu_parity_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_parity_out~0 .lut_mask = 16'hF0D2; +defparam \z80_|alu_|alu_parity_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N10 +cycloneive_lcell_comb \z80_|alu_|alu_parity_out~1 ( +// Equation(s): +// \z80_|alu_|alu_parity_out~1_combout = \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout $ (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout $ (\z80_|alu_|alu_parity_out~0_combout $ +// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ))) + + .dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ), + .datac(\z80_|alu_|alu_parity_out~0_combout ), + .datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ), + .cin(gnd), + .combout(\z80_|alu_|alu_parity_out~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|alu_parity_out~1 .lut_mask = 16'h9669; +defparam \z80_|alu_|alu_parity_out~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N24 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~4 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~4_combout = (\z80_|execute_|ctl_pf_sel[0]~2_combout & (((!\z80_|pla_decode_|Equal62~3_combout & !\z80_|execute_|ctl_alu_op_low~27_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|execute_|ctl_pf_sel[0]~2_combout ), + .datab(\z80_|pla_decode_|Equal62~3_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~4 .lut_mask = 16'h0A2A; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N18 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~5 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~5_combout = (\z80_|execute_|ctl_pf_sel[0]~3_combout & (!\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout $ +// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout )))) # (!\z80_|execute_|ctl_pf_sel[0]~3_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout $ ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout )))) + + .dataa(\z80_|execute_|ctl_pf_sel[0]~3_combout ), + .datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), + .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~5 .lut_mask = 16'h143C; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N16 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~6 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~6_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout & (((!\z80_|pla_decode_|Equal69~0_combout & \z80_|execute_|ctl_flags_bus~1_combout )) # (!\z80_|nM1_int~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal69~0_combout ), + .datab(\z80_|execute_|ctl_flags_bus~1_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~6 .lut_mask = 16'h4F00; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N6 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~1 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~1_combout = (\z80_|execute_|ctl_pf_sel[0]~3_combout & (!\z80_|execute_|ctl_alu_op_low~27_combout & (\z80_|execute_|ctl_pf_sel[0]~2_combout & !\z80_|pla_decode_|Equal62~3_combout ))) + + .dataa(\z80_|execute_|ctl_pf_sel[0]~3_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~27_combout ), + .datac(\z80_|execute_|ctl_pf_sel[0]~2_combout ), + .datad(\z80_|pla_decode_|Equal62~3_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~1 .lut_mask = 16'h0020; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N30 +cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~2 ( +// Equation(s): +// \z80_|decode_state_|DFFE_instNonRep~2_combout = (!\z80_|address_latch_|Q [6] & (!\z80_|address_latch_|Q [5] & (!\z80_|address_latch_|Q [4] & !\z80_|address_latch_|Q [7]))) + + .dataa(\z80_|address_latch_|Q [6]), + .datab(\z80_|address_latch_|Q [5]), + .datac(\z80_|address_latch_|Q [4]), + .datad(\z80_|address_latch_|Q [7]), + .cin(gnd), + .combout(\z80_|decode_state_|DFFE_instNonRep~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep~2 .lut_mask = 16'h0001; +defparam \z80_|decode_state_|DFFE_instNonRep~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N0 +cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~1 ( +// Equation(s): +// \z80_|decode_state_|DFFE_instNonRep~1_combout = (!\z80_|address_latch_|Q [9] & (!\z80_|address_latch_|Q [8] & (!\z80_|address_latch_|Q [11] & !\z80_|address_latch_|Q [10]))) + + .dataa(\z80_|address_latch_|Q [9]), + .datab(\z80_|address_latch_|Q [8]), + .datac(\z80_|address_latch_|Q [11]), + .datad(\z80_|address_latch_|Q [10]), + .cin(gnd), + .combout(\z80_|decode_state_|DFFE_instNonRep~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep~1 .lut_mask = 16'h0001; +defparam \z80_|decode_state_|DFFE_instNonRep~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N4 +cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~3 ( +// Equation(s): +// \z80_|decode_state_|DFFE_instNonRep~3_combout = (\z80_|address_latch_|Q [0] & (!\z80_|address_latch_|Q [2] & (!\z80_|address_latch_|Q [3] & !\z80_|address_latch_|Q [1]))) + + .dataa(\z80_|address_latch_|Q [0]), + .datab(\z80_|address_latch_|Q [2]), + .datac(\z80_|address_latch_|Q [3]), + .datad(\z80_|address_latch_|Q [1]), + .cin(gnd), + .combout(\z80_|decode_state_|DFFE_instNonRep~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep~3 .lut_mask = 16'h0002; +defparam \z80_|decode_state_|DFFE_instNonRep~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N28 +cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~0 ( +// Equation(s): +// \z80_|decode_state_|DFFE_instNonRep~0_combout = (!\z80_|address_latch_|Q [14] & (!\z80_|address_latch_|Q [15] & (!\z80_|address_latch_|Q [12] & !\z80_|address_latch_|Q [13]))) + + .dataa(\z80_|address_latch_|Q [14]), + .datab(\z80_|address_latch_|Q [15]), + .datac(\z80_|address_latch_|Q [12]), + .datad(\z80_|address_latch_|Q [13]), + .cin(gnd), + .combout(\z80_|decode_state_|DFFE_instNonRep~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep~0 .lut_mask = 16'h0001; +defparam \z80_|decode_state_|DFFE_instNonRep~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y13_N24 +cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~4 ( +// Equation(s): +// \z80_|decode_state_|DFFE_instNonRep~4_combout = (\z80_|decode_state_|DFFE_instNonRep~2_combout & (\z80_|decode_state_|DFFE_instNonRep~1_combout & (\z80_|decode_state_|DFFE_instNonRep~3_combout & \z80_|decode_state_|DFFE_instNonRep~0_combout ))) + + .dataa(\z80_|decode_state_|DFFE_instNonRep~2_combout ), + .datab(\z80_|decode_state_|DFFE_instNonRep~1_combout ), + .datac(\z80_|decode_state_|DFFE_instNonRep~3_combout ), + .datad(\z80_|decode_state_|DFFE_instNonRep~0_combout ), + .cin(gnd), + .combout(\z80_|decode_state_|DFFE_instNonRep~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep~4 .lut_mask = 16'h8000; +defparam \z80_|decode_state_|DFFE_instNonRep~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N20 +cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~5 ( +// Equation(s): +// \z80_|decode_state_|DFFE_instNonRep~5_combout = (\z80_|execute_|ctl_flags_bus~1_combout & (((\z80_|decode_state_|DFFE_instNonRep~q )))) # (!\z80_|execute_|ctl_flags_bus~1_combout & ((\z80_|execute_|ixy_d~9_combout & +// (\z80_|decode_state_|DFFE_instNonRep~4_combout )) # (!\z80_|execute_|ixy_d~9_combout & ((\z80_|decode_state_|DFFE_instNonRep~q ))))) + + .dataa(\z80_|decode_state_|DFFE_instNonRep~4_combout ), + .datab(\z80_|execute_|ctl_flags_bus~1_combout ), + .datac(\z80_|decode_state_|DFFE_instNonRep~q ), + .datad(\z80_|execute_|ixy_d~9_combout ), + .cin(gnd), + .combout(\z80_|decode_state_|DFFE_instNonRep~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep~5 .lut_mask = 16'hE2F0; +defparam \z80_|decode_state_|DFFE_instNonRep~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y15_N21 +dffeas \z80_|decode_state_|DFFE_instNonRep ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|decode_state_|DFFE_instNonRep~5_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|decode_state_|DFFE_instNonRep~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instNonRep .is_wysiwyg = "true"; +defparam \z80_|decode_state_|DFFE_instNonRep .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N12 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~2 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~2_combout = (\z80_|pla_decode_|Equal69~0_combout & ((\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout & ((\z80_|interrupts_|DFFE_instIFF2~q ))) # (!\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout & +// (!\z80_|decode_state_|DFFE_instNonRep~q )))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout ), + .datab(\z80_|decode_state_|DFFE_instNonRep~q ), + .datac(\z80_|interrupts_|DFFE_instIFF2~q ), + .datad(\z80_|pla_decode_|Equal69~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~2 .lut_mask = 16'hB100; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N14 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~3 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~3_combout = (\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_flags_bus~1_combout & (\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout )) # (!\z80_|execute_|ctl_flags_bus~1_combout & +// ((!\z80_|decode_state_|DFFE_instNonRep~q ))))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ), + .datab(\z80_|nM1_int~2_combout ), + .datac(\z80_|decode_state_|DFFE_instNonRep~q ), + .datad(\z80_|execute_|ctl_flags_bus~1_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~3 .lut_mask = 16'h880C; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N2 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~7 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~7_combout = (\z80_|pla_decode_|Equal69~0_combout ) # (((\z80_|pla_decode_|Equal62~3_combout ) # (\z80_|execute_|ctl_alu_op_low~27_combout )) # (!\z80_|execute_|ctl_flags_bus~1_combout )) + + .dataa(\z80_|pla_decode_|Equal69~0_combout ), + .datab(\z80_|execute_|ctl_flags_bus~1_combout ), + .datac(\z80_|pla_decode_|Equal62~3_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~7 .lut_mask = 16'hFFFB; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N0 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~8 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~8_combout = (\z80_|execute_|ctl_pf_sel[0]~2_combout & (\z80_|execute_|ctl_pf_sel[0]~3_combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout )))) + + .dataa(\z80_|execute_|ctl_pf_sel[0]~2_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ), + .datac(\z80_|nM1_int~2_combout ), + .datad(\z80_|execute_|ctl_pf_sel[0]~3_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~8 .lut_mask = 16'h2A00; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N26 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~9 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~9_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ) # ((\z80_|alu_|alu_parity_out~1_combout & \z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ))) + + .dataa(\z80_|alu_|alu_parity_out~1_combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~9 .lut_mask = 16'hFEFC; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N0 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~0 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~0_combout = (\z80_|execute_|ctl_flags_pf_we~9_combout & (\z80_|execute_|ctl_flags_bus~combout & ((\z80_|alu_control_|db[2]~29_combout )))) # (!\z80_|execute_|ctl_flags_pf_we~9_combout & +// (((\z80_|alu_flags_|DFFE_inst_latch_pf~q )))) + + .dataa(\z80_|execute_|ctl_flags_bus~combout ), + .datab(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), + .datac(\z80_|execute_|ctl_flags_pf_we~9_combout ), + .datad(\z80_|alu_control_|db[2]~29_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~0 .lut_mask = 16'hAC0C; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N16 +cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~10 ( +// Equation(s): +// \z80_|alu_flags_|DFFE_inst_latch_pf~10_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ) # ((\z80_|execute_|ctl_flags_alu~15_combout & (\z80_|execute_|ctl_flags_pf_we~9_combout & \z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ))) + + .dataa(\z80_|execute_|ctl_flags_alu~15_combout ), + .datab(\z80_|execute_|ctl_flags_pf_we~9_combout ), + .datac(\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|DFFE_inst_latch_pf~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~10 .lut_mask = 16'hFF80; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y15_N17 +dffeas \z80_|alu_flags_|DFFE_inst_latch_pf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|DFFE_inst_latch_pf~10_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|DFFE_inst_latch_pf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|DFFE_inst_latch_pf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y13_N6 +cycloneive_lcell_comb \z80_|alu_control_|sel[1]~0 ( +// Equation(s): +// \z80_|alu_control_|sel[1]~0_combout = (\z80_|ir_|opcode [5] & (((!\z80_|pla_decode_|Equal6~0_combout ) # (!\z80_|pla_decode_|Equal40~0_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|ir_|opcode [5]), + .datac(\z80_|pla_decode_|Equal40~0_combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|sel[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|sel[1]~0 .lut_mask = 16'h4CCC; +defparam \z80_|alu_control_|sel[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N18 +cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_cond_mux|out~0 ( +// Equation(s): +// \z80_|alu_control_|b2v_inst_cond_mux|out~0_combout = (\z80_|alu_control_|sel[1]~0_combout & (((\z80_|ir_|opcode [4])))) # (!\z80_|alu_control_|sel[1]~0_combout & ((\z80_|ir_|opcode [4] & ((\z80_|alu_flags_|flags_cf~combout ))) # (!\z80_|ir_|opcode [4] +// & (\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q )))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datab(\z80_|alu_flags_|flags_cf~combout ), + .datac(\z80_|alu_control_|sel[1]~0_combout ), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|b2v_inst_cond_mux|out~0 .lut_mask = 16'hFC0A; +defparam \z80_|alu_control_|b2v_inst_cond_mux|out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N16 +cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_cond_mux|out~1 ( +// Equation(s): +// \z80_|alu_control_|b2v_inst_cond_mux|out~1_combout = (\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout & (((\z80_|alu_flags_|DFFE_inst_latch_sf~q ) # (!\z80_|alu_control_|sel[1]~0_combout )))) # (!\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout & +// (\z80_|alu_flags_|DFFE_inst_latch_pf~q & (\z80_|alu_control_|sel[1]~0_combout ))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_pf~q ), + .datab(\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ), + .datac(\z80_|alu_control_|sel[1]~0_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), + .cin(gnd), + .combout(\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|b2v_inst_cond_mux|out~1 .lut_mask = 16'hEC2C; +defparam \z80_|alu_control_|b2v_inst_cond_mux|out~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N26 +cycloneive_lcell_comb \z80_|alu_control_|flags_cond_true~0 ( +// Equation(s): +// \z80_|alu_control_|flags_cond_true~0_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|ir_|opcode [3] $ (((!\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ))))) # (!\z80_|execute_|ctl_eval_cond~0_combout & +// (((\z80_|alu_control_|flags_cond_true~q )))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|alu_control_|flags_cond_true~q ), + .datad(\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|flags_cond_true~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|flags_cond_true~0 .lut_mask = 16'hD872; +defparam \z80_|alu_control_|flags_cond_true~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y16_N27 +dffeas \z80_|alu_control_|flags_cond_true ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_control_|flags_cond_true~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_control_|flags_cond_true~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_control_|flags_cond_true .is_wysiwyg = "true"; +defparam \z80_|alu_control_|flags_cond_true .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y12_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~20 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~20_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|pla_decode_|Equal35~0_combout & \z80_|alu_control_|flags_cond_true~q ))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|pla_decode_|Equal35~0_combout ), + .datad(\z80_|alu_control_|flags_cond_true~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~20 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sel_wz~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~1 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~1_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ) # ((\z80_|execute_|ctl_reg_sel_wz~20_combout ) # ((\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ctl_al_we~14_combout ))) + + .dataa(\z80_|execute_|ixy_d~7_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~20_combout ), + .datad(\z80_|execute_|ctl_al_we~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~1 .lut_mask = 16'hFCFE; +defparam \z80_|execute_|ctl_sw_4d~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~6 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4d~6_combout = (\z80_|execute_|ctl_sw_4d~0_combout ) # ((\z80_|execute_|ctl_sw_4d~1_combout ) # (!\z80_|execute_|ctl_sw_4d~5_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_sw_4d~0_combout ), + .datac(\z80_|execute_|ctl_sw_4d~1_combout ), + .datad(\z80_|execute_|ctl_sw_4d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_4d~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_4d~6 .lut_mask = 16'hFCFF; +defparam \z80_|execute_|ctl_sw_4d~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y12_N17 +dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_lo_as[1]~6_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N16 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~4 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[1]~4_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[1]~32_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # +// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) + + .dataa(\z80_|execute_|ctl_sw_4d~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[1]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[1]~4 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|db_lo_as[1]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y12_N23 +dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_lo_as[1]~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N20 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~5 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[1]~5_combout = (\z80_|reg_file_|db_lo_as[1]~4_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|db_lo_as[1]~4_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_lo|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[1]~5 .lut_mask = 16'hC0CC; +defparam \z80_|reg_file_|db_lo_as[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N18 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout = \z80_|address_latch_|Q [1] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ) + + .dataa(\z80_|address_latch_|Q [1]), + .datab(gnd), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out .lut_mask = 16'h5A5A; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y12_N22 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~6 ( +// Equation(s): +// \z80_|reg_file_|db_lo_as[1]~6_combout = ((\z80_|reg_file_|db_lo_as[1]~5_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .datab(\z80_|reg_file_|db_lo_as[1]~5_combout ), + .datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), + .datad(\z80_|reg_file_|db_lo_as[0]~2_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_as[1]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_as[1]~6 .lut_mask = 16'hC4FF; +defparam \z80_|reg_file_|db_lo_as[1]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y12_N7 +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~29 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~29_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [1] & ((\z80_|alu_control_|db[1]~26_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (((\z80_|alu_control_|db[1]~26_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [1]), + .datad(\z80_|alu_control_|db[1]~26_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~29 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[1]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y12_N15 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X31_Y12_N5 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~28 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~28_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .datab(\z80_|reg_file_|b2v_latch_iy_lo|latch [1]), + .datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~28 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp0[1]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y14_N1 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X32_Y14_N19 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~26 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~26_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [1]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [1]), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~26 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[1]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y13_N19 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y13_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~27 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~27_combout = (\z80_|reg_file_|gdfx_temp0[1]~26_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) + + .dataa(gnd), + .datab(\z80_|reg_file_|gdfx_temp0[1]~26_combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~27 .lut_mask = 16'hC0CC; +defparam \z80_|reg_file_|gdfx_temp0[1]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y12_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~30 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~30_combout = (\z80_|reg_file_|gdfx_temp0[1]~29_combout & (\z80_|reg_file_|gdfx_temp0[1]~28_combout & \z80_|reg_file_|gdfx_temp0[1]~27_combout )) + + .dataa(\z80_|reg_file_|gdfx_temp0[1]~29_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[1]~28_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[1]~27_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~30 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|gdfx_temp0[1]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y12_N7 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y12_N1 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~24 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~24_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [1] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [1] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) + + .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [1]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~24 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp0[1]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y11_N5 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X31_Y11_N19 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~23 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~23_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [1]), + .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [1]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~23 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[1]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y11_N23 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X32_Y11_N25 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~25 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~25_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [1]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [1]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~25 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[1]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N30 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~31 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~31_combout = (\z80_|reg_file_|gdfx_temp0[1]~30_combout & (\z80_|reg_file_|gdfx_temp0[1]~24_combout & (\z80_|reg_file_|gdfx_temp0[1]~23_combout & \z80_|reg_file_|gdfx_temp0[1]~25_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp0[1]~30_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[1]~24_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[1]~23_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[1]~25_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~31 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[1]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~32 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[1]~32_combout = ((\z80_|reg_file_|gdfx_temp0[1]~31_combout & ((\z80_|reg_file_|db_lo_as[1]~6_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), + .datab(\z80_|reg_file_|db_lo_as[1]~6_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[1]~31_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[1]~32 .lut_mask = 16'hD0FF; +defparam \z80_|reg_file_|gdfx_temp0[1]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N30 +cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[1]~1 ( +// Equation(s): +// \z80_|reg_file_|db_lo_ds[1]~1_combout = (\z80_|reg_file_|gdfx_temp0[1]~32_combout ) # ((!\z80_|execute_|ctl_reg_out_lo~5_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout & \z80_|execute_|ctl_reg_out_lo~7_combout ))) + + .dataa(\z80_|execute_|ctl_reg_out_lo~5_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ), + .datac(\z80_|execute_|ctl_reg_out_lo~7_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[1]~32_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_lo_ds[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_lo_ds[1]~1 .lut_mask = 16'hFF40; +defparam \z80_|reg_file_|db_lo_ds[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N16 +cycloneive_lcell_comb \z80_|alu_control_|db[1]~25 ( +// Equation(s): +// \z80_|alu_control_|db[1]~25_combout = (\z80_|reg_file_|db_lo_ds[1]~1_combout & (((\z80_|bus_control_|db[1]~11_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) + + .dataa(\z80_|reg_file_|db_lo_ds[1]~1_combout ), + .datab(\z80_|bus_control_|db[1]~11_combout ), + .datac(\z80_|execute_|ctl_sw_1d~7_combout ), + .datad(\z80_|execute_|ctl_sw_mask543_en~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[1]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[1]~25 .lut_mask = 16'h0A8A; +defparam \z80_|alu_control_|db[1]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N4 +cycloneive_lcell_comb \z80_|alu_control_|db[1]~24 ( +// Equation(s): +// \z80_|alu_control_|db[1]~24_combout = (\z80_|execute_|ctl_flags_oe~2_combout & (((!\z80_|alu_|db[1]~10_combout & \z80_|execute_|ctl_sw_2u~7_combout )) # (!\z80_|alu_flags_|DFFE_inst_latch_nf~q ))) # (!\z80_|execute_|ctl_flags_oe~2_combout & +// (!\z80_|alu_|db[1]~10_combout & (\z80_|execute_|ctl_sw_2u~7_combout ))) + + .dataa(\z80_|execute_|ctl_flags_oe~2_combout ), + .datab(\z80_|alu_|db[1]~10_combout ), + .datac(\z80_|execute_|ctl_sw_2u~7_combout ), + .datad(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), + .cin(gnd), + .combout(\z80_|alu_control_|db[1]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[1]~24 .lut_mask = 16'h30BA; +defparam \z80_|alu_control_|db[1]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N18 +cycloneive_lcell_comb \z80_|alu_control_|db[1]~26 ( +// Equation(s): +// \z80_|alu_control_|db[1]~26_combout = ((\z80_|alu_control_|db[1]~25_combout & (!\z80_|alu_control_|db[1]~24_combout & \z80_|alu_control_|db[2]~23_combout ))) # (!\z80_|alu_control_|db[6]~11_combout ) + + .dataa(\z80_|alu_control_|db[1]~25_combout ), + .datab(\z80_|alu_control_|db[1]~24_combout ), + .datac(\z80_|alu_control_|db[2]~23_combout ), + .datad(\z80_|alu_control_|db[6]~11_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[1]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[1]~26 .lut_mask = 16'h20FF; +defparam \z80_|alu_control_|db[1]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N2 +cycloneive_lcell_comb \z80_|bus_control_|db[1]~10 ( +// Equation(s): +// \z80_|bus_control_|db[1]~10_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[1]~26_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) + + .dataa(\z80_|bus_control_|db[0]~4_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datad(\z80_|alu_control_|db[1]~26_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[1]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[1]~10 .lut_mask = 16'hAA0A; +defparam \z80_|bus_control_|db[1]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|nextM~4 ( +// Equation(s): +// \z80_|execute_|nextM~4_combout = ((!\z80_|execute_|ctl_mRead~34_combout & ((!\z80_|pla_decode_|Equal24~0_combout ) # (!\z80_|pla_decode_|Equal21~0_combout )))) # (!\z80_|execute_|ctl_state_alu~2_combout ) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|pla_decode_|Equal21~0_combout ), + .datad(\z80_|pla_decode_|Equal24~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~4 .lut_mask = 16'h5777; +defparam \z80_|execute_|nextM~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_iorw~12 ( +// Equation(s): +// \z80_|execute_|ctl_iorw~12_combout = (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [2] & \z80_|execute_|ctl_eval_cond~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~0_combout ), + .datab(\z80_|ir_|opcode [1]), + .datac(\z80_|ir_|opcode [2]), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_iorw~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_iorw~12 .lut_mask = 16'h0200; +defparam \z80_|execute_|ctl_iorw~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_iorw~8 ( +// Equation(s): +// \z80_|execute_|ctl_iorw~8_combout = (\z80_|execute_|ctl_iorw~12_combout ) # ((\z80_|execute_|ctl_state_alu~2_combout & (\z80_|pla_decode_|Equal3~0_combout & \z80_|pla_decode_|Equal24~0_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ctl_iorw~12_combout ), + .datac(\z80_|pla_decode_|Equal3~0_combout ), + .datad(\z80_|pla_decode_|Equal24~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_iorw~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_iorw~8 .lut_mask = 16'hECCC; +defparam \z80_|execute_|ctl_iorw~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_iorw~9 ( +// Equation(s): +// \z80_|execute_|ctl_iorw~9_combout = ((\z80_|execute_|ctl_iorw~8_combout ) # ((\z80_|execute_|ctl_mWrite~17_combout & \z80_|execute_|ctl_mRead~9_combout ))) # (!\z80_|execute_|nextM~4_combout ) + + .dataa(\z80_|execute_|ctl_mWrite~17_combout ), + .datab(\z80_|execute_|nextM~4_combout ), + .datac(\z80_|execute_|ctl_mRead~9_combout ), + .datad(\z80_|execute_|ctl_iorw~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_iorw~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_iorw~9 .lut_mask = 16'hFFB3; +defparam \z80_|execute_|ctl_iorw~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y11_N29 +dffeas \z80_|memory_ifc_|DFFE_iorq_ff1 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|execute_|ctl_iorw~9_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_iorq_ff1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_iorq_ff1 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_iorq_ff1 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y11_N25 +dffeas \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|memory_ifc_|DFFE_iorq_ff1~q ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N14 +cycloneive_lcell_comb \z80_|memory_ifc_|wait_iorq~feeder ( +// Equation(s): +// \z80_|memory_ifc_|wait_iorq~feeder_combout = \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|wait_iorq~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_iorq~feeder .lut_mask = 16'hFF00; +defparam \z80_|memory_ifc_|wait_iorq~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y11_N15 +dffeas \z80_|memory_ifc_|wait_iorq ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|memory_ifc_|wait_iorq~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|wait_iorq~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_iorq .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|wait_iorq .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y11_N9 +dffeas \z80_|memory_ifc_|DFFE_iorq_ff4 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|memory_ifc_|wait_iorq~q ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_iorq_ff4~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_iorq_ff4 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_iorq_ff4 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N8 +cycloneive_lcell_comb \z80_|memory_ifc_|iorq~0 ( +// Equation(s): +// \z80_|memory_ifc_|iorq~0_combout = (\z80_|memory_ifc_|wait_iorq~q ) # ((\z80_|memory_ifc_|DFFE_iorq_ff4~q ) # (\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q )) + + .dataa(gnd), + .datab(\z80_|memory_ifc_|wait_iorq~q ), + .datac(\z80_|memory_ifc_|DFFE_iorq_ff4~q ), + .datad(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|iorq~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|iorq~0 .lut_mask = 16'hFFFC; +defparam \z80_|memory_ifc_|iorq~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y11_N3 +dffeas \z80_|memory_ifc_|DFFE_m1_ff1 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|execute_|setM1~54_combout ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_m1_ff1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_m1_ff1 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_m1_ff1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N26 +cycloneive_lcell_comb \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0 ( +// Equation(s): +// \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout = !\z80_|memory_ifc_|DFFE_m1_ff1~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|memory_ifc_|DFFE_m1_ff1~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0 .lut_mask = 16'h00FF; +defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y11_N27 +dffeas \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y11_N19 +dffeas \z80_|memory_ifc_|DFFE_m1_ff3 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_m1_ff3~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_m1_ff3 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_m1_ff3 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N18 +cycloneive_lcell_comb \z80_|memory_ifc_|nRD_out~0 ( +// Equation(s): +// \z80_|memory_ifc_|nRD_out~0_combout = (\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q & (((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q )) # (!\z80_|interrupts_|DFFE_inst44~q ))) # (!\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q & +// (\z80_|memory_ifc_|DFFE_m1_ff3~q & ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|interrupts_|DFFE_inst44~q )))) + + .dataa(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ), + .datab(\z80_|interrupts_|DFFE_inst44~q ), + .datac(\z80_|memory_ifc_|DFFE_m1_ff3~q ), + .datad(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|nRD_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|nRD_out~0 .lut_mask = 16'hFA32; +defparam \z80_|memory_ifc_|nRD_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|fIORead~0 ( +// Equation(s): +// \z80_|execute_|fIORead~0_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_mWrite~4_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # (\z80_|execute_|ctl_alu_op_low~22_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIORead~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIORead~0 .lut_mask = 16'hC080; +defparam \z80_|execute_|fIORead~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N22 +cycloneive_lcell_comb \z80_|execute_|fIORead~1 ( +// Equation(s): +// \z80_|execute_|fIORead~1_combout = (\z80_|pla_decode_|Equal68~2_combout & (\z80_|pla_decode_|Equal1~4_combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # (!\z80_|execute_|fIOWrite~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal68~2_combout ), + .datab(\z80_|pla_decode_|Equal1~4_combout ), + .datac(\z80_|execute_|ctl_mWrite~5_combout ), + .datad(\z80_|execute_|fIOWrite~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIORead~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIORead~1 .lut_mask = 16'h8088; +defparam \z80_|execute_|fIORead~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N30 +cycloneive_lcell_comb \z80_|execute_|fIORead~2 ( +// Equation(s): +// \z80_|execute_|fIORead~2_combout = (\z80_|execute_|fIORead~1_combout ) # ((\z80_|execute_|ctl_mWrite~17_combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # (\z80_|execute_|ctl_state_alu~3_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~5_combout ), + .datab(\z80_|execute_|ctl_state_alu~3_combout ), + .datac(\z80_|execute_|fIORead~1_combout ), + .datad(\z80_|execute_|ctl_mWrite~17_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIORead~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIORead~2 .lut_mask = 16'hFEF0; +defparam \z80_|execute_|fIORead~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|fIOWrite~1 ( +// Equation(s): +// \z80_|execute_|fIOWrite~1_combout = (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|execute_|ixy_d~4_combout ))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|execute_|ixy_d~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIOWrite~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIOWrite~1 .lut_mask = 16'hA0F0; +defparam \z80_|execute_|fIOWrite~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|fIORead~3 ( +// Equation(s): +// \z80_|execute_|fIORead~3_combout = (\z80_|execute_|fIORead~0_combout ) # ((\z80_|execute_|fIORead~2_combout ) # ((\z80_|execute_|ctl_mRead~2_combout & \z80_|execute_|fIOWrite~1_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~2_combout ), + .datab(\z80_|execute_|fIORead~0_combout ), + .datac(\z80_|execute_|fIORead~2_combout ), + .datad(\z80_|execute_|fIOWrite~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIORead~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIORead~3 .lut_mask = 16'hFEFC; +defparam \z80_|execute_|fIORead~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~30 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~30_combout = (\z80_|execute_|ctl_state_alu~2_combout & ((\z80_|pla_decode_|Equal33~3_combout ) # ((\z80_|pla_decode_|Equal41~2_combout ) # (\z80_|pla_decode_|Equal6~1_combout )))) + + .dataa(\z80_|pla_decode_|Equal33~3_combout ), + .datab(\z80_|pla_decode_|Equal41~2_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|pla_decode_|Equal6~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~30 .lut_mask = 16'hF0E0; +defparam \z80_|execute_|ctl_mRead~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~31 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~31_combout = (\z80_|execute_|ctl_mRead~30_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & \z80_|execute_|ctl_mRead~10_combout )) + + .dataa(\z80_|execute_|ctl_mRead~30_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .datad(\z80_|execute_|ctl_mRead~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~31 .lut_mask = 16'hFAAA; +defparam \z80_|execute_|ctl_mRead~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|nextM~3 ( +// Equation(s): +// \z80_|execute_|nextM~3_combout = (!\z80_|execute_|ixy_d~16_combout & (!\z80_|execute_|ixy_d~10_combout & !\z80_|pla_decode_|Equal41~2_combout )) + + .dataa(\z80_|execute_|ixy_d~16_combout ), + .datab(\z80_|execute_|ixy_d~10_combout ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|nextM~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~3 .lut_mask = 16'h0101; +defparam \z80_|execute_|nextM~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~29 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~29_combout = (\z80_|execute_|ixy_d~8_combout & (((\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal49~0_combout )) # (!\z80_|execute_|nextM~3_combout ))) + + .dataa(\z80_|execute_|nextM~3_combout ), + .datab(\z80_|execute_|ixy_d~8_combout ), + .datac(\z80_|decode_state_|use_ixiy~combout ), + .datad(\z80_|pla_decode_|Equal49~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~29 .lut_mask = 16'hC444; +defparam \z80_|execute_|ctl_mRead~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N26 +cycloneive_lcell_comb \z80_|execute_|setM1~58 ( +// Equation(s): +// \z80_|execute_|setM1~58_combout = (!\z80_|execute_|ctl_mRead~12_combout & ((\z80_|decode_state_|DFFE_instIY1~q ) # ((\z80_|decode_state_|DFFE_inst4~q ) # (!\z80_|pla_decode_|Equal49~0_combout )))) + + .dataa(\z80_|decode_state_|DFFE_instIY1~q ), + .datab(\z80_|decode_state_|DFFE_inst4~q ), + .datac(\z80_|pla_decode_|Equal49~0_combout ), + .datad(\z80_|execute_|ctl_mRead~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~58_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~58 .lut_mask = 16'h00EF; +defparam \z80_|execute_|setM1~58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|setM1~38 ( +// Equation(s): +// \z80_|execute_|setM1~38_combout = (\z80_|execute_|setM1~37_combout & \z80_|execute_|ctl_reg_sys_hilo~38_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|setM1~37_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo~38_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~38_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~38 .lut_mask = 16'hF000; +defparam \z80_|execute_|setM1~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|fMRead~4 ( +// Equation(s): +// \z80_|execute_|fMRead~4_combout = (\z80_|execute_|ctl_al_we~4_combout & (\z80_|execute_|ctl_reg_sel_wz~8_combout & !\z80_|pla_decode_|Equal34~0_combout )) + + .dataa(\z80_|execute_|ctl_al_we~4_combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~8_combout ), + .datac(gnd), + .datad(\z80_|pla_decode_|Equal34~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~4 .lut_mask = 16'h0088; +defparam \z80_|execute_|fMRead~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N14 +cycloneive_lcell_comb \z80_|execute_|setM1~39 ( +// Equation(s): +// \z80_|execute_|setM1~39_combout = (!\z80_|pla_decode_|Equal29~0_combout & (\z80_|execute_|fMRead~4_combout & !\z80_|pla_decode_|Equal9~1_combout )) + + .dataa(\z80_|pla_decode_|Equal29~0_combout ), + .datab(gnd), + .datac(\z80_|execute_|fMRead~4_combout ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~39 .lut_mask = 16'h0050; +defparam \z80_|execute_|setM1~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N4 +cycloneive_lcell_comb \z80_|execute_|setM1~40 ( +// Equation(s): +// \z80_|execute_|setM1~40_combout = (\z80_|execute_|setM1~58_combout & (\z80_|execute_|setM1~38_combout & (\z80_|execute_|setM1~39_combout & !\z80_|execute_|ctl_mRead~14_combout ))) + + .dataa(\z80_|execute_|setM1~58_combout ), + .datab(\z80_|execute_|setM1~38_combout ), + .datac(\z80_|execute_|setM1~39_combout ), + .datad(\z80_|execute_|ctl_mRead~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~40_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~40 .lut_mask = 16'h0080; +defparam \z80_|execute_|setM1~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y14_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~32 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~32_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (((\z80_|execute_|ctl_mRead~11_combout ) # (!\z80_|execute_|setM1~40_combout )) # (!\z80_|execute_|ctl_mRead~17_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~17_combout ), + .datab(\z80_|execute_|ctl_mRead~11_combout ), + .datac(\z80_|execute_|ctl_eval_cond~0_combout ), + .datad(\z80_|execute_|setM1~40_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~32 .lut_mask = 16'hD0F0; +defparam \z80_|execute_|ctl_mRead~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y14_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~33 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~33_combout = (\z80_|execute_|ctl_mRead~31_combout ) # (((\z80_|execute_|ctl_mRead~29_combout ) # (\z80_|execute_|ctl_mRead~32_combout )) # (!\z80_|execute_|ctl_mRead~28_combout )) + + .dataa(\z80_|execute_|ctl_mRead~31_combout ), + .datab(\z80_|execute_|ctl_mRead~28_combout ), + .datac(\z80_|execute_|ctl_mRead~29_combout ), + .datad(\z80_|execute_|ctl_mRead~32_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~33 .lut_mask = 16'hFFFB; +defparam \z80_|execute_|ctl_mRead~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y14_N17 +dffeas \z80_|memory_ifc_|DFFE_mrd_ff1 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|execute_|ctl_mRead~33_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_mrd_ff1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_mrd_ff1 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_mrd_ff1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N30 +cycloneive_lcell_comb \z80_|memory_ifc_|wait_mrd~feeder ( +// Equation(s): +// \z80_|memory_ifc_|wait_mrd~feeder_combout = \z80_|memory_ifc_|DFFE_mrd_ff1~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|memory_ifc_|DFFE_mrd_ff1~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|wait_mrd~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_mrd~feeder .lut_mask = 16'hFF00; +defparam \z80_|memory_ifc_|wait_mrd~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y11_N31 +dffeas \z80_|memory_ifc_|wait_mrd ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|memory_ifc_|wait_mrd~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|wait_mrd~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_mrd .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|wait_mrd .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y11_N17 +dffeas \z80_|memory_ifc_|DFFE_mrd_ff3 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|memory_ifc_|wait_mrd~q ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_mrd_ff3~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_mrd_ff3 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_mrd_ff3 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N12 +cycloneive_lcell_comb \z80_|memory_ifc_|nRD_out~1 ( +// Equation(s): +// \z80_|memory_ifc_|nRD_out~1_combout = (!\z80_|memory_ifc_|wait_mrd~q & !\z80_|memory_ifc_|DFFE_mrd_ff3~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|memory_ifc_|wait_mrd~q ), + .datad(\z80_|memory_ifc_|DFFE_mrd_ff3~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|nRD_out~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|nRD_out~1 .lut_mask = 16'h000F; +defparam \z80_|memory_ifc_|nRD_out~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y11_N20 +cycloneive_lcell_comb \z80_|memory_ifc_|nRD_out~2 ( +// Equation(s): +// \z80_|memory_ifc_|nRD_out~2_combout = (\z80_|memory_ifc_|nRD_out~0_combout ) # (((\z80_|memory_ifc_|iorq~0_combout & \z80_|execute_|fIORead~3_combout )) # (!\z80_|memory_ifc_|nRD_out~1_combout )) + + .dataa(\z80_|memory_ifc_|iorq~0_combout ), + .datab(\z80_|memory_ifc_|nRD_out~0_combout ), + .datac(\z80_|execute_|fIORead~3_combout ), + .datad(\z80_|memory_ifc_|nRD_out~1_combout ), + .cin(gnd), + .combout(\z80_|memory_ifc_|nRD_out~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|nRD_out~2 .lut_mask = 16'hECFF; +defparam \z80_|memory_ifc_|nRD_out~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|fIOWrite~3 ( +// Equation(s): +// \z80_|execute_|fIOWrite~3_combout = ((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_M3_ff~q ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|fIOWrite~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIOWrite~3 .lut_mask = 16'h0FCF; +defparam \z80_|execute_|fIOWrite~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|fIOWrite~4 ( +// Equation(s): +// \z80_|execute_|fIOWrite~4_combout = (\z80_|execute_|ctl_mRead~34_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ixy_d~6_combout ) # (!\z80_|execute_|fIOWrite~3_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|execute_|fIOWrite~3_combout ), + .datad(\z80_|execute_|ixy_d~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIOWrite~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIOWrite~4 .lut_mask = 16'hCC8C; +defparam \z80_|execute_|fIOWrite~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y16_N22 +cycloneive_lcell_comb \z80_|execute_|fIOWrite~2 ( +// Equation(s): +// \z80_|execute_|fIOWrite~2_combout = (\z80_|execute_|ctl_iorw~10_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # ((\z80_|execute_|ctl_mWrite~5_combout ) # (!\z80_|execute_|fMRead~2_combout )))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ctl_iorw~10_combout ), + .datac(\z80_|execute_|ctl_mWrite~5_combout ), + .datad(\z80_|execute_|fMRead~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIOWrite~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIOWrite~2 .lut_mask = 16'hC8CC; +defparam \z80_|execute_|fIOWrite~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|fIOWrite~5 ( +// Equation(s): +// \z80_|execute_|fIOWrite~5_combout = (\z80_|execute_|fIOWrite~4_combout ) # ((\z80_|execute_|fIOWrite~2_combout ) # ((\z80_|execute_|ctl_mRead~3_combout & \z80_|execute_|fIOWrite~1_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~3_combout ), + .datab(\z80_|execute_|fIOWrite~4_combout ), + .datac(\z80_|execute_|fIOWrite~2_combout ), + .datad(\z80_|execute_|fIOWrite~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|fIOWrite~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fIOWrite~5 .lut_mask = 16'hFEFC; +defparam \z80_|execute_|fIOWrite~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~15 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~15_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_mWrite~7_combout ) # ((\z80_|execute_|ctl_state_alu~2_combout & \z80_|execute_|ctl_mRead~5_combout )))) # (!\z80_|execute_|ctl_eval_cond~0_combout & +// (((\z80_|execute_|ctl_state_alu~2_combout & \z80_|execute_|ctl_mRead~5_combout )))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|ctl_mWrite~7_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_mRead~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~15 .lut_mask = 16'hF888; +defparam \z80_|execute_|ctl_mWrite~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~12 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~12_combout = (!\z80_|execute_|ctl_mWrite~18_combout & (((!\z80_|execute_|ctl_mRead~6_combout & !\z80_|execute_|ctl_mRead~8_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~4_combout ), + .datab(\z80_|execute_|ctl_mWrite~18_combout ), + .datac(\z80_|execute_|ctl_mRead~6_combout ), + .datad(\z80_|execute_|ctl_mRead~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~12 .lut_mask = 16'h1113; +defparam \z80_|execute_|ctl_mWrite~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~13 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~13_combout = (\z80_|execute_|ctl_mWrite~12_combout & (\z80_|execute_|ctl_mWrite~10_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|execute_|ctl_mWrite~8_combout )))) + + .dataa(\z80_|execute_|ctl_mWrite~8_combout ), + .datab(\z80_|execute_|ctl_mWrite~12_combout ), + .datac(\z80_|execute_|ctl_mWrite~10_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~13 .lut_mask = 16'h40C0; +defparam \z80_|execute_|ctl_mWrite~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~14 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~14_combout = (\z80_|execute_|ctl_mWrite~11_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~4_combout & (\z80_|execute_|ctl_mWrite~13_combout & \z80_|execute_|ctl_bus_db_oe~7_combout ))) + + .dataa(\z80_|execute_|ctl_mWrite~11_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), + .datac(\z80_|execute_|ctl_mWrite~13_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~14 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_mWrite~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~16 ( +// Equation(s): +// \z80_|execute_|ctl_mWrite~16_combout = (\z80_|execute_|ctl_mWrite~15_combout ) # (((\z80_|execute_|ixy_d~8_combout & !\z80_|execute_|ixy_d~17_combout )) # (!\z80_|execute_|ctl_mWrite~14_combout )) + + .dataa(\z80_|execute_|ctl_mWrite~15_combout ), + .datab(\z80_|execute_|ixy_d~8_combout ), + .datac(\z80_|execute_|ixy_d~17_combout ), + .datad(\z80_|execute_|ctl_mWrite~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mWrite~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mWrite~16 .lut_mask = 16'hAEFF; +defparam \z80_|execute_|ctl_mWrite~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y11_N7 +dffeas \z80_|memory_ifc_|DFFE_mwr_ff1 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|execute_|ctl_mWrite~16_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_mwr_ff1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_mwr_ff1 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_mwr_ff1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N22 +cycloneive_lcell_comb \z80_|memory_ifc_|wait_mwr~feeder ( +// Equation(s): +// \z80_|memory_ifc_|wait_mwr~feeder_combout = \z80_|memory_ifc_|DFFE_mwr_ff1~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|memory_ifc_|DFFE_mwr_ff1~q ), + .cin(gnd), + .combout(\z80_|memory_ifc_|wait_mwr~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_mwr~feeder .lut_mask = 16'hFF00; +defparam \z80_|memory_ifc_|wait_mwr~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y11_N23 +dffeas \z80_|memory_ifc_|wait_mwr ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|memory_ifc_|wait_mwr~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|wait_mwr~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_mwr .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|wait_mwr .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y11_N21 +dffeas \z80_|memory_ifc_|mwr_wr ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|memory_ifc_|wait_mwr~q ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|mwr_wr~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|mwr_wr .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|mwr_wr .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N20 +cycloneive_lcell_comb \z80_|memory_ifc_|nWR_out~0 ( +// Equation(s): +// \z80_|memory_ifc_|nWR_out~0_combout = (\z80_|memory_ifc_|mwr_wr~q ) # ((\z80_|execute_|fIOWrite~5_combout & \z80_|memory_ifc_|iorq~0_combout )) + + .dataa(\z80_|execute_|fIOWrite~5_combout ), + .datab(\z80_|memory_ifc_|iorq~0_combout ), + .datac(\z80_|memory_ifc_|mwr_wr~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|memory_ifc_|nWR_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|nWR_out~0 .lut_mask = 16'hF8F8; +defparam \z80_|memory_ifc_|nWR_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N16 +cycloneive_lcell_comb \Equal2~1 ( +// Equation(s): +// \Equal2~1_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\z80_|memory_ifc_|nRD_out~2_combout & !\z80_|memory_ifc_|nWR_out~0_combout )) + + .dataa(gnd), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|memory_ifc_|nRD_out~2_combout ), + .datad(\z80_|memory_ifc_|nWR_out~0_combout ), + .cin(gnd), + .combout(\Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \Equal2~1 .lut_mask = 16'h00C0; +defparam \Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|fMWrite~3 ( +// Equation(s): +// \z80_|execute_|fMWrite~3_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|sequencer_|DFFE_M4_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~3 .lut_mask = 16'h7373; +defparam \z80_|execute_|fMWrite~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N16 +cycloneive_lcell_comb \z80_|execute_|fMWrite~4 ( +// Equation(s): +// \z80_|execute_|fMWrite~4_combout = (!\z80_|execute_|fMWrite~3_combout & ((\z80_|execute_|ctl_mWrite~7_combout ) # ((\z80_|pla_decode_|Equal13~2_combout ) # (\z80_|execute_|ctl_mRead~5_combout )))) + + .dataa(\z80_|execute_|fMWrite~3_combout ), + .datab(\z80_|execute_|ctl_mWrite~7_combout ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|execute_|ctl_mRead~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~4 .lut_mask = 16'h5554; +defparam \z80_|execute_|fMWrite~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N24 +cycloneive_lcell_comb \z80_|execute_|fMWrite~0 ( +// Equation(s): +// \z80_|execute_|fMWrite~0_combout = ((!\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|M5~q ) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(gnd), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~0 .lut_mask = 16'h0F5F; +defparam \z80_|execute_|fMWrite~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|fMWrite~2 ( +// Equation(s): +// \z80_|execute_|fMWrite~2_combout = (!\z80_|execute_|fMWrite~1_combout & (((\z80_|execute_|ixy_d~6_combout ) # (\z80_|execute_|ixy_d~5_combout )) # (!\z80_|execute_|fMWrite~0_combout ))) + + .dataa(\z80_|execute_|fMWrite~1_combout ), + .datab(\z80_|execute_|fMWrite~0_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~2 .lut_mask = 16'h5551; +defparam \z80_|execute_|fMWrite~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N8 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~3 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~3_combout = (\z80_|execute_|ctl_bus_inc_oe~26_combout & (!\z80_|execute_|fMWrite~4_combout & (!\z80_|execute_|fMWrite~2_combout & !\z80_|execute_|fIOWrite~5_combout ))) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~26_combout ), + .datab(\z80_|execute_|fMWrite~4_combout ), + .datac(\z80_|execute_|fMWrite~2_combout ), + .datad(\z80_|execute_|fIOWrite~5_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~3 .lut_mask = 16'h0002; +defparam \z80_|pin_control_|bus_db_pin_oe~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y15_N14 +cycloneive_lcell_comb \z80_|execute_|fMWrite~8 ( +// Equation(s): +// \z80_|execute_|fMWrite~8_combout = (\z80_|pla_decode_|Equal9~1_combout & (((\z80_|execute_|ctl_alu_oe~0_combout ) # (\z80_|execute_|ctl_reg_in_hi~2_combout )))) # (!\z80_|pla_decode_|Equal9~1_combout & (\z80_|execute_|ctl_mRead~8_combout & +// ((\z80_|execute_|ctl_alu_oe~0_combout ) # (\z80_|execute_|ctl_reg_in_hi~2_combout )))) + + .dataa(\z80_|pla_decode_|Equal9~1_combout ), + .datab(\z80_|execute_|ctl_mRead~8_combout ), + .datac(\z80_|execute_|ctl_alu_oe~0_combout ), + .datad(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~8 .lut_mask = 16'hEEE0; +defparam \z80_|execute_|fMWrite~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|fMWrite~7 ( +// Equation(s): +// \z80_|execute_|fMWrite~7_combout = (\z80_|execute_|ctl_state_alu~4_combout & ((\z80_|execute_|ctl_mRead~5_combout ) # ((\z80_|execute_|ctl_mWrite~7_combout ) # (\z80_|execute_|ctl_mRead~7_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~5_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|ctl_mWrite~7_combout ), + .datad(\z80_|execute_|ctl_mRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~7 .lut_mask = 16'hCCC8; +defparam \z80_|execute_|fMWrite~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N26 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~16 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~16_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & (((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|pla_decode_|Equal13~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), + .datab(\z80_|pla_decode_|Equal13~2_combout ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~16 .lut_mask = 16'h1555; +defparam \z80_|pin_control_|bus_db_pin_oe~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N14 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~8 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~8_combout = (\z80_|execute_|ixy_d~5_combout & (!\z80_|execute_|ctl_mRead~5_combout & ((!\z80_|execute_|ctl_ir_we~4_combout ) # (!\z80_|execute_|ctl_mRead~8_combout )))) # (!\z80_|execute_|ixy_d~5_combout & +// (((!\z80_|execute_|ctl_ir_we~4_combout )) # (!\z80_|execute_|ctl_mRead~8_combout ))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_mRead~8_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|execute_|ctl_mRead~5_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~8 .lut_mask = 16'h153F; +defparam \z80_|pin_control_|bus_db_pin_oe~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|fMWrite~6 ( +// Equation(s): +// \z80_|execute_|fMWrite~6_combout = ((\z80_|pla_decode_|Equal46~0_combout ) # ((\z80_|ir_|opcode [6] & !\z80_|ir_|opcode [7]))) # (!\z80_|execute_|ctl_ir_we~5_combout ) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|execute_|ctl_ir_we~5_combout ), + .datad(\z80_|pla_decode_|Equal46~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~6 .lut_mask = 16'hFF2F; +defparam \z80_|execute_|fMWrite~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N8 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~9 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~9_combout = (\z80_|execute_|fMWrite~6_combout & (((\z80_|execute_|fIOWrite~0_combout )) # (!\z80_|execute_|ctl_mWrite~8_combout ))) # (!\z80_|execute_|fMWrite~6_combout & (\z80_|execute_|fMWrite~0_combout & +// ((\z80_|execute_|fIOWrite~0_combout ) # (!\z80_|execute_|ctl_mWrite~8_combout )))) + + .dataa(\z80_|execute_|fMWrite~6_combout ), + .datab(\z80_|execute_|ctl_mWrite~8_combout ), + .datac(\z80_|execute_|fIOWrite~0_combout ), + .datad(\z80_|execute_|fMWrite~0_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~9 .lut_mask = 16'hF3A2; +defparam \z80_|pin_control_|bus_db_pin_oe~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N28 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~7 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~7_combout = (\z80_|execute_|ixy_d~7_combout & (((\z80_|execute_|fMRead~3_combout & !\z80_|execute_|ctl_mRead~4_combout )))) # (!\z80_|execute_|ixy_d~7_combout & (((!\z80_|execute_|ctl_mRead~4_combout )) # +// (!\z80_|execute_|ctl_alu_oe~0_combout ))) + + .dataa(\z80_|execute_|ctl_alu_oe~0_combout ), + .datab(\z80_|execute_|fMRead~3_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ctl_mRead~4_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~7 .lut_mask = 16'h05CF; +defparam \z80_|pin_control_|bus_db_pin_oe~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N10 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~10 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~10_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (\z80_|pin_control_|bus_db_pin_oe~8_combout & (\z80_|pin_control_|bus_db_pin_oe~9_combout & \z80_|pin_control_|bus_db_pin_oe~7_combout ))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~16_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~8_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~9_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~7_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~10 .lut_mask = 16'h8000; +defparam \z80_|pin_control_|bus_db_pin_oe~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N20 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~11 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~11_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout & (!\z80_|execute_|fMWrite~7_combout & (\z80_|execute_|ctl_reg_sel_wz~7_combout & \z80_|pin_control_|bus_db_pin_oe~10_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), + .datab(\z80_|execute_|fMWrite~7_combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~7_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~10_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~11 .lut_mask = 16'h2000; +defparam \z80_|pin_control_|bus_db_pin_oe~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N6 +cycloneive_lcell_comb \z80_|execute_|fMWrite~5 ( +// Equation(s): +// \z80_|execute_|fMWrite~5_combout = (!\z80_|execute_|ctl_mWrite~17_combout & (!\z80_|execute_|ctl_mWrite~6_combout & !\z80_|execute_|ctl_mRead~5_combout )) + + .dataa(\z80_|execute_|ctl_mWrite~17_combout ), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datac(\z80_|execute_|ctl_mRead~5_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|fMWrite~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMWrite~5 .lut_mask = 16'h0101; +defparam \z80_|execute_|fMWrite~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N28 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~6 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~6_combout = (\z80_|execute_|ctl_inc_dec~2_combout & ((\z80_|execute_|fMWrite~5_combout ) # ((!\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ixy_d~6_combout )))) + + .dataa(\z80_|execute_|fMWrite~5_combout ), + .datab(\z80_|execute_|ctl_inc_dec~2_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ixy_d~6_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~6 .lut_mask = 16'h888C; +defparam \z80_|pin_control_|bus_db_pin_oe~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N26 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~12 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~12_combout = (!\z80_|execute_|fMWrite~8_combout & (\z80_|pin_control_|bus_db_pin_oe~11_combout & (\z80_|execute_|ctl_bus_inc_oe~30_combout & \z80_|pin_control_|bus_db_pin_oe~6_combout ))) + + .dataa(\z80_|execute_|fMWrite~8_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~11_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~30_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~6_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~12 .lut_mask = 16'h4000; +defparam \z80_|pin_control_|bus_db_pin_oe~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y16_N20 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~4 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~4_combout = (\z80_|pla_decode_|Equal11~0_combout & (!\z80_|execute_|ixy_d~7_combout & ((!\z80_|execute_|ctl_mRead~6_combout ) # (!\z80_|execute_|ctl_reg_in_hi~2_combout )))) # (!\z80_|pla_decode_|Equal11~0_combout & +// (((!\z80_|execute_|ctl_mRead~6_combout )) # (!\z80_|execute_|ctl_reg_in_hi~2_combout ))) + + .dataa(\z80_|pla_decode_|Equal11~0_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datac(\z80_|execute_|ctl_mRead~6_combout ), + .datad(\z80_|execute_|ixy_d~7_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~4 .lut_mask = 16'h153F; +defparam \z80_|pin_control_|bus_db_pin_oe~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N30 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~5 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~5_combout = (\z80_|pin_control_|bus_db_pin_oe~4_combout & (((\z80_|execute_|ixy_d~4_combout ) # (!\z80_|execute_|ctl_mWrite~7_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|execute_|ctl_mWrite~7_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~4_combout ), + .datad(\z80_|execute_|ixy_d~4_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~5 .lut_mask = 16'hF070; +defparam \z80_|pin_control_|bus_db_pin_oe~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N24 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~13 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~13_combout = (\z80_|pin_control_|bus_db_pin_oe~12_combout & (\z80_|pin_control_|bus_db_pin_oe~5_combout & ((!\z80_|execute_|ixy_d~6_combout ) # (!\z80_|pla_decode_|Equal11~0_combout )))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~12_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~5_combout ), + .datac(\z80_|pla_decode_|Equal11~0_combout ), + .datad(\z80_|execute_|ixy_d~6_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~13 .lut_mask = 16'h0888; +defparam \z80_|pin_control_|bus_db_pin_oe~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y18_N12 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~14 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~14_combout = (\z80_|pin_control_|bus_db_pin_oe~3_combout & (\z80_|execute_|ctl_inc_cy~35_combout & (\z80_|execute_|ctl_apin_mux~0_combout & \z80_|pin_control_|bus_db_pin_oe~13_combout ))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~3_combout ), + .datab(\z80_|execute_|ctl_inc_cy~35_combout ), + .datac(\z80_|execute_|ctl_apin_mux~0_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~13_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~14 .lut_mask = 16'h8000; +defparam \z80_|pin_control_|bus_db_pin_oe~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N4 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~2 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~2_combout = (\z80_|sequencer_|DFFE_T3_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q ) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~2 .lut_mask = 16'hFFCC; +defparam \z80_|pin_control_|bus_db_pin_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N14 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~15 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_oe~15_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout & (\z80_|execute_|fIOWrite~5_combout & ((\z80_|sequencer_|DFFE_T4_ff~q )))) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout & +// ((\z80_|pin_control_|bus_db_pin_oe~2_combout ) # ((\z80_|execute_|fIOWrite~5_combout & \z80_|sequencer_|DFFE_T4_ff~q )))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .datab(\z80_|execute_|fIOWrite~5_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~2_combout ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_oe~15 .lut_mask = 16'hDC50; +defparam \z80_|pin_control_|bus_db_pin_oe~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y11_N12 +cycloneive_lcell_comb \z80_|clk_delay_|DFF_inst5~feeder ( +// Equation(s): +// \z80_|clk_delay_|DFF_inst5~feeder_combout = \z80_|clk_delay_|SYNTHESIZED_WIRE_7~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ), + .cin(gnd), + .combout(\z80_|clk_delay_|DFF_inst5~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|clk_delay_|DFF_inst5~feeder .lut_mask = 16'hFF00; +defparam \z80_|clk_delay_|DFF_inst5~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X38_Y11_N13 +dffeas \z80_|clk_delay_|DFF_inst5 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|clk_delay_|DFF_inst5~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|clk_delay_|DFF_inst5~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|clk_delay_|DFF_inst5 .is_wysiwyg = "true"; +defparam \z80_|clk_delay_|DFF_inst5 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y11_N15 +dffeas \z80_|memory_ifc_|wait_iorqinta ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|clk_delay_|DFF_inst5~q ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|wait_iorqinta~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|wait_iorqinta .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|wait_iorqinta .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y11_N31 +dffeas \z80_|memory_ifc_|DFFE_intr_ff3 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|memory_ifc_|wait_iorqinta~q ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|memory_ifc_|DFFE_intr_ff3~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|memory_ifc_|DFFE_intr_ff3 .is_wysiwyg = "true"; +defparam \z80_|memory_ifc_|DFFE_intr_ff3 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N30 +cycloneive_lcell_comb \z80_|memory_ifc_|nIORQ_out~0 ( +// Equation(s): +// \z80_|memory_ifc_|nIORQ_out~0_combout = (\z80_|memory_ifc_|iorq~0_combout ) # ((\z80_|memory_ifc_|wait_iorqinta~q ) # (\z80_|memory_ifc_|DFFE_intr_ff3~q )) + + .dataa(\z80_|memory_ifc_|iorq~0_combout ), + .datab(\z80_|memory_ifc_|wait_iorqinta~q ), + .datac(\z80_|memory_ifc_|DFFE_intr_ff3~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|memory_ifc_|nIORQ_out~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|memory_ifc_|nIORQ_out~0 .lut_mask = 16'hFEFE; +defparam \z80_|memory_ifc_|nIORQ_out~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N28 +cycloneive_lcell_comb \Equal2~0 ( +// Equation(s): +// \Equal2~0_combout = (\z80_|memory_ifc_|nIORQ_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\z80_|memory_ifc_|nRD_out~2_combout & !\z80_|memory_ifc_|nWR_out~0_combout ))) + + .dataa(\z80_|memory_ifc_|nIORQ_out~0_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|memory_ifc_|nRD_out~2_combout ), + .datad(\z80_|memory_ifc_|nWR_out~0_combout ), + .cin(gnd), + .combout(\Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \Equal2~0 .lut_mask = 16'h0080; +defparam \Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~2 ( +// Equation(s): +// \z80_|execute_|ctl_apin_mux~2_combout = ((\z80_|execute_|ctl_apin_mux~1_combout & \z80_|execute_|ctl_mWrite~6_combout )) # (!\z80_|execute_|ctl_inc_dec~6_combout ) + + .dataa(\z80_|execute_|ctl_apin_mux~1_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_inc_dec~6_combout ), + .datad(\z80_|execute_|ctl_mWrite~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_apin_mux~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_apin_mux~2 .lut_mask = 16'hAF0F; +defparam \z80_|execute_|ctl_apin_mux~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N8 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[10]~10 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[10]~10_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [10]))) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [10]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[10]~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[10]~10 .lut_mask = 16'hDD88; +defparam \z80_|address_pins_|DFFE_apin_latch[10]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux2~0 ( +// Equation(s): +// \z80_|execute_|ctl_apin_mux2~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_apin_mux2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_apin_mux2~0 .lut_mask = 16'h4545; +defparam \z80_|execute_|ctl_apin_mux2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N24 +cycloneive_lcell_comb \z80_|pin_control_|bus_ab_pin_we~0 ( +// Equation(s): +// \z80_|pin_control_|bus_ab_pin_we~0_combout = ((\z80_|execute_|fIORead~3_combout ) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout )) # (!\z80_|sequencer_|DFFE_M1_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|execute_|fIORead~3_combout ), + .datac(gnd), + .datad(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_ab_pin_we~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_ab_pin_we~0 .lut_mask = 16'hDDFF; +defparam \z80_|pin_control_|bus_ab_pin_we~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y12_N26 +cycloneive_lcell_comb \z80_|pin_control_|bus_ab_pin_we~1 ( +// Equation(s): +// \z80_|pin_control_|bus_ab_pin_we~1_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # ((!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|execute_|fMRead~36_combout ) # (\z80_|pin_control_|bus_ab_pin_we~0_combout )))) + + .dataa(\z80_|execute_|fMRead~36_combout ), + .datab(\z80_|pin_control_|bus_ab_pin_we~0_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_ab_pin_we~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_ab_pin_we~1 .lut_mask = 16'hFF0E; +defparam \z80_|pin_control_|bus_ab_pin_we~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y13_N9 +dffeas \z80_|address_pins_|DFFE_apin_latch[10] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[10]~10_combout ), + .asdata(\z80_|address_latch_|Q [10]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [10]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[10] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[10] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X18_Y34_N1 +cycloneive_io_ibuf \PS2_DAT~input ( + .i(PS2_DAT), + .ibar(gnd), + .o(\PS2_DAT~input_o )); +// synopsys translate_off +defparam \PS2_DAT~input .bus_hold = "false"; +defparam \PS2_DAT~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X53_Y14_N1 +cycloneive_io_ibuf \KEY[0]~input ( + .i(KEY[0]), + .ibar(gnd), + .o(\KEY[0]~input_o )); +// synopsys translate_off +defparam \KEY[0]~input .bus_hold = "false"; +defparam \KEY[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X52_Y17_N6 +cycloneive_lcell_comb reset( +// Equation(s): +// \reset~combout = (!\KEY[0]~input_o ) # (!\ula_|pll_|altpll_component|auto_generated|wire_pll1_locked ) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|pll_|altpll_component|auto_generated|wire_pll1_locked ), + .datad(\KEY[0]~input_o ), + .cin(gnd), + .combout(\reset~combout ), + .cout()); +// synopsys translate_off +defparam reset.lut_mask = 16'h0FFF; +defparam reset.sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: CLKCTRL_G8 +cycloneive_clkctrl \reset~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\reset~combout }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\reset~clkctrl_outclk )); +// synopsys translate_off +defparam \reset~clkctrl .clock_type = "global clock"; +defparam \reset~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y10_N0 +cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~3 ( +// Equation(s): +// \ula_|ps2_keyboard_|bit_count~3_combout = (\ula_|ps2_keyboard_|bit_count [2] & (\ula_|ps2_keyboard_|bit_count [0] & (!\ula_|ps2_keyboard_|bit_count [3] & \ula_|ps2_keyboard_|bit_count [1]))) # (!\ula_|ps2_keyboard_|bit_count [2] & +// (((\ula_|ps2_keyboard_|bit_count [3] & !\ula_|ps2_keyboard_|bit_count [1])))) + + .dataa(\ula_|ps2_keyboard_|bit_count [0]), + .datab(\ula_|ps2_keyboard_|bit_count [2]), + .datac(\ula_|ps2_keyboard_|bit_count [3]), + .datad(\ula_|ps2_keyboard_|bit_count [1]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|bit_count~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count~3 .lut_mask = 16'h0830; +defparam \ula_|ps2_keyboard_|bit_count~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X9_Y34_N8 +cycloneive_io_ibuf \PS2_CLK~input ( + .i(PS2_CLK), + .ibar(gnd), + .o(\PS2_CLK~input_o )); +// synopsys translate_off +defparam \PS2_CLK~input .bus_hold = "false"; +defparam \PS2_CLK~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y26_N20 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[7]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[7]~feeder_combout = \PS2_CLK~input_o + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\PS2_CLK~input_o ), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[7]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y26_N21 +dffeas \ula_|ps2_keyboard_|clk_filter[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[7] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y26_N18 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[6]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[6]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [7] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [7]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[6]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y26_N19 +dffeas \ula_|ps2_keyboard_|clk_filter[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[6] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y26_N0 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[5]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[5]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [6] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [6]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[5]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y26_N1 +dffeas \ula_|ps2_keyboard_|clk_filter[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[5] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y26_N6 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[4]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[4]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [5]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[4]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y26_N7 +dffeas \ula_|ps2_keyboard_|clk_filter[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[4] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y26_N10 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[3]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[3]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [4] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [4]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[3]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y26_N11 +dffeas \ula_|ps2_keyboard_|clk_filter[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[3]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[3] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y26_N24 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[2]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[2]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [3] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [3]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[2]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y26_N25 +dffeas \ula_|ps2_keyboard_|clk_filter[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[2] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y26_N26 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[1]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[1]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|clk_filter [2]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[1]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|clk_filter[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y26_N27 +dffeas \ula_|ps2_keyboard_|clk_filter[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[1] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y26_N16 +cycloneive_lcell_comb \ula_|ps2_keyboard_|Equal0~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|Equal0~0_combout = (!\ula_|ps2_keyboard_|clk_filter [4] & (!\ula_|ps2_keyboard_|clk_filter [7] & (!\ula_|ps2_keyboard_|clk_filter [6] & !\ula_|ps2_keyboard_|clk_filter [5]))) + + .dataa(\ula_|ps2_keyboard_|clk_filter [4]), + .datab(\ula_|ps2_keyboard_|clk_filter [7]), + .datac(\ula_|ps2_keyboard_|clk_filter [6]), + .datad(\ula_|ps2_keyboard_|clk_filter [5]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|Equal0~0 .lut_mask = 16'h0001; +defparam \ula_|ps2_keyboard_|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y26_N12 +cycloneive_lcell_comb \ula_|ps2_keyboard_|Equal0~1 ( +// Equation(s): +// \ula_|ps2_keyboard_|Equal0~1_combout = (!\ula_|ps2_keyboard_|clk_filter [3] & (!\ula_|ps2_keyboard_|clk_filter [2] & (!\ula_|ps2_keyboard_|clk_filter [1] & \ula_|ps2_keyboard_|Equal0~0_combout ))) + + .dataa(\ula_|ps2_keyboard_|clk_filter [3]), + .datab(\ula_|ps2_keyboard_|clk_filter [2]), + .datac(\ula_|ps2_keyboard_|clk_filter [1]), + .datad(\ula_|ps2_keyboard_|Equal0~0_combout ), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|Equal0~1 .lut_mask = 16'h0100; +defparam \ula_|ps2_keyboard_|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y26_N2 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[0]~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_filter[0]~0_combout = !\ula_|ps2_keyboard_|clk_filter [1] + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|clk_filter [1]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_filter[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[0]~0 .lut_mask = 16'h0F0F; +defparam \ula_|ps2_keyboard_|clk_filter[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y26_N3 +dffeas \ula_|ps2_keyboard_|clk_filter[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_filter[0]~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_filter [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_filter[0] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_filter[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y26_N22 +cycloneive_lcell_comb \ula_|ps2_keyboard_|ps2_clk_in~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|ps2_clk_in~0_combout = (\ula_|ps2_keyboard_|Equal0~1_combout & ((\ula_|ps2_keyboard_|clk_filter [0]))) # (!\ula_|ps2_keyboard_|Equal0~1_combout & (\ula_|ps2_keyboard_|ps2_clk_in~q )) + + .dataa(\ula_|ps2_keyboard_|Equal0~1_combout ), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|ps2_clk_in~q ), + .datad(\ula_|ps2_keyboard_|clk_filter [0]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|ps2_clk_in~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|ps2_clk_in~0 .lut_mask = 16'hFA50; +defparam \ula_|ps2_keyboard_|ps2_clk_in~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y26_N23 +dffeas \ula_|ps2_keyboard_|ps2_clk_in ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|ps2_clk_in~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|ps2_clk_in~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|ps2_clk_in .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|ps2_clk_in .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y26_N28 +cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_edge~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|clk_edge~0_combout = (\ula_|ps2_keyboard_|Equal0~1_combout & (!\ula_|ps2_keyboard_|ps2_clk_in~q & \ula_|ps2_keyboard_|clk_filter [0])) + + .dataa(\ula_|ps2_keyboard_|Equal0~1_combout ), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|ps2_clk_in~q ), + .datad(\ula_|ps2_keyboard_|clk_filter [0]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|clk_edge~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_edge~0 .lut_mask = 16'h0A00; +defparam \ula_|ps2_keyboard_|clk_edge~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y26_N29 +dffeas \ula_|ps2_keyboard_|clk_edge ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|clk_edge~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|clk_edge~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|clk_edge .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|clk_edge .power_up = "low"; +// synopsys translate_on + +// Location: FF_X21_Y10_N1 +dffeas \ula_|ps2_keyboard_|bit_count[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|bit_count~3_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|clk_edge~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|bit_count [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count[3] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|bit_count[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y10_N28 +cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~1 ( +// Equation(s): +// \ula_|ps2_keyboard_|bit_count~1_combout = (!\ula_|ps2_keyboard_|bit_count [3] & (\ula_|ps2_keyboard_|bit_count [2] $ (((\ula_|ps2_keyboard_|bit_count [0] & \ula_|ps2_keyboard_|bit_count [1]))))) + + .dataa(\ula_|ps2_keyboard_|bit_count [0]), + .datab(\ula_|ps2_keyboard_|bit_count [3]), + .datac(\ula_|ps2_keyboard_|bit_count [2]), + .datad(\ula_|ps2_keyboard_|bit_count [1]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|bit_count~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count~1 .lut_mask = 16'h1230; +defparam \ula_|ps2_keyboard_|bit_count~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y10_N29 +dffeas \ula_|ps2_keyboard_|bit_count[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|bit_count~1_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|clk_edge~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|bit_count [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count[2] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|bit_count[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y10_N10 +cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~2 ( +// Equation(s): +// \ula_|ps2_keyboard_|bit_count~2_combout = (\ula_|ps2_keyboard_|bit_count [0] & (!\ula_|ps2_keyboard_|bit_count [1] & ((!\ula_|ps2_keyboard_|bit_count [3]) # (!\ula_|ps2_keyboard_|bit_count [2])))) # (!\ula_|ps2_keyboard_|bit_count [0] & +// (((\ula_|ps2_keyboard_|bit_count [1] & !\ula_|ps2_keyboard_|bit_count [3])))) + + .dataa(\ula_|ps2_keyboard_|bit_count [0]), + .datab(\ula_|ps2_keyboard_|bit_count [2]), + .datac(\ula_|ps2_keyboard_|bit_count [1]), + .datad(\ula_|ps2_keyboard_|bit_count [3]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|bit_count~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count~2 .lut_mask = 16'h025A; +defparam \ula_|ps2_keyboard_|bit_count~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y10_N11 +dffeas \ula_|ps2_keyboard_|bit_count[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|bit_count~2_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|clk_edge~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|bit_count [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count[1] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|bit_count[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y10_N22 +cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|bit_count~0_combout = (!\ula_|ps2_keyboard_|bit_count [0] & (((!\ula_|ps2_keyboard_|bit_count [1] & !\ula_|ps2_keyboard_|bit_count [2])) # (!\ula_|ps2_keyboard_|bit_count [3]))) + + .dataa(\ula_|ps2_keyboard_|bit_count [1]), + .datab(\ula_|ps2_keyboard_|bit_count [2]), + .datac(\ula_|ps2_keyboard_|bit_count [0]), + .datad(\ula_|ps2_keyboard_|bit_count [3]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|bit_count~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count~0 .lut_mask = 16'h010F; +defparam \ula_|ps2_keyboard_|bit_count~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y10_N23 +dffeas \ula_|ps2_keyboard_|bit_count[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|bit_count~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|clk_edge~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|bit_count [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|bit_count[0] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|bit_count[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y10_N2 +cycloneive_lcell_comb \ula_|ps2_keyboard_|always1~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|always1~0_combout = (!\ula_|ps2_keyboard_|bit_count [1] & (!\ula_|ps2_keyboard_|bit_count [2] & (!\PS2_DAT~input_o & !\ula_|ps2_keyboard_|bit_count [3]))) + + .dataa(\ula_|ps2_keyboard_|bit_count [1]), + .datab(\ula_|ps2_keyboard_|bit_count [2]), + .datac(\PS2_DAT~input_o ), + .datad(\ula_|ps2_keyboard_|bit_count [3]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|always1~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|always1~0 .lut_mask = 16'h0001; +defparam \ula_|ps2_keyboard_|always1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y10_N12 +cycloneive_lcell_comb \ula_|ps2_keyboard_|LessThan0~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|LessThan0~0_combout = (\ula_|ps2_keyboard_|bit_count [3] & ((\ula_|ps2_keyboard_|bit_count [1]) # (\ula_|ps2_keyboard_|bit_count [2]))) + + .dataa(\ula_|ps2_keyboard_|bit_count [1]), + .datab(\ula_|ps2_keyboard_|bit_count [2]), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|bit_count [3]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|LessThan0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|LessThan0~0 .lut_mask = 16'hEE00; +defparam \ula_|ps2_keyboard_|LessThan0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y10_N26 +cycloneive_lcell_comb \ula_|ps2_keyboard_|shiftreg[0]~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|shiftreg[0]~0_combout = (\ula_|ps2_keyboard_|clk_edge~q & (!\ula_|ps2_keyboard_|LessThan0~0_combout & ((\ula_|ps2_keyboard_|bit_count [0]) # (!\ula_|ps2_keyboard_|always1~0_combout )))) + + .dataa(\ula_|ps2_keyboard_|bit_count [0]), + .datab(\ula_|ps2_keyboard_|always1~0_combout ), + .datac(\ula_|ps2_keyboard_|clk_edge~q ), + .datad(\ula_|ps2_keyboard_|LessThan0~0_combout ), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[0]~0 .lut_mask = 16'h00B0; +defparam \ula_|ps2_keyboard_|shiftreg[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y8_N17 +dffeas \ula_|ps2_keyboard_|shiftreg[8] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\PS2_DAT~input_o ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [8]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[8] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N14 +cycloneive_lcell_comb \ula_|ps2_keyboard_|shiftreg[7]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|shiftreg[7]~feeder_combout = \ula_|ps2_keyboard_|shiftreg [8] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [8]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|shiftreg[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[7]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|shiftreg[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y8_N15 +dffeas \ula_|ps2_keyboard_|shiftreg[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|shiftreg[7]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[7] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y8_N9 +dffeas \ula_|ps2_keyboard_|shiftreg[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [7]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[6] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y8_N5 +dffeas \ula_|ps2_keyboard_|shiftreg[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [6]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[5] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y8_N23 +dffeas \ula_|ps2_keyboard_|shiftreg[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [5]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[4] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y9_N17 +dffeas \ula_|ps2_keyboard_|shiftreg[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [4]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[3] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y8_N23 +dffeas \ula_|ps2_keyboard_|shiftreg[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [3]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[2] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y8_N21 +dffeas \ula_|ps2_keyboard_|shiftreg[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|ps2_keyboard_|shiftreg [2]), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[1] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N18 +cycloneive_lcell_comb \ula_|ps2_keyboard_|shiftreg[0]~feeder ( +// Equation(s): +// \ula_|ps2_keyboard_|shiftreg[0]~feeder_combout = \ula_|ps2_keyboard_|shiftreg [1] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|shiftreg[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[0]~feeder .lut_mask = 16'hFF00; +defparam \ula_|ps2_keyboard_|shiftreg[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y10_N19 +dffeas \ula_|ps2_keyboard_|shiftreg[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|shiftreg[0]~feeder_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|shiftreg [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|shiftreg[0] .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|shiftreg[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N4 +cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|WideXor0~0_combout = \ula_|ps2_keyboard_|shiftreg [1] $ (\ula_|ps2_keyboard_|shiftreg [0] $ (\ula_|ps2_keyboard_|shiftreg [3] $ (\ula_|ps2_keyboard_|shiftreg [2]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|WideXor0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|WideXor0~0 .lut_mask = 16'h6996; +defparam \ula_|ps2_keyboard_|WideXor0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N16 +cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~1 ( +// Equation(s): +// \ula_|ps2_keyboard_|WideXor0~1_combout = \ula_|ps2_keyboard_|shiftreg [6] $ (\ula_|ps2_keyboard_|shiftreg [5] $ (\ula_|ps2_keyboard_|shiftreg [8] $ (\ula_|ps2_keyboard_|shiftreg [7]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|ps2_keyboard_|shiftreg [8]), + .datad(\ula_|ps2_keyboard_|shiftreg [7]), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|WideXor0~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|WideXor0~1 .lut_mask = 16'h6996; +defparam \ula_|ps2_keyboard_|WideXor0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N22 +cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~2 ( +// Equation(s): +// \ula_|ps2_keyboard_|WideXor0~2_combout = \ula_|ps2_keyboard_|shiftreg [4] $ (\ula_|ps2_keyboard_|WideXor0~0_combout $ (\ula_|ps2_keyboard_|WideXor0~1_combout )) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|WideXor0~0_combout ), + .datad(\ula_|ps2_keyboard_|WideXor0~1_combout ), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|WideXor0~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|WideXor0~2 .lut_mask = 16'hA55A; +defparam \ula_|ps2_keyboard_|WideXor0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y10_N4 +cycloneive_lcell_comb \ula_|ps2_keyboard_|scan_code_ready~0 ( +// Equation(s): +// \ula_|ps2_keyboard_|scan_code_ready~0_combout = (\PS2_DAT~input_o & (\ula_|ps2_keyboard_|clk_edge~q & (\ula_|ps2_keyboard_|WideXor0~2_combout & \ula_|ps2_keyboard_|LessThan0~0_combout ))) + + .dataa(\PS2_DAT~input_o ), + .datab(\ula_|ps2_keyboard_|clk_edge~q ), + .datac(\ula_|ps2_keyboard_|WideXor0~2_combout ), + .datad(\ula_|ps2_keyboard_|LessThan0~0_combout ), + .cin(gnd), + .combout(\ula_|ps2_keyboard_|scan_code_ready~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|scan_code_ready~0 .lut_mask = 16'h8000; +defparam \ula_|ps2_keyboard_|scan_code_ready~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y10_N5 +dffeas \ula_|ps2_keyboard_|scan_code_ready ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|ps2_keyboard_|scan_code_ready~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|ps2_keyboard_|scan_code_ready~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|ps2_keyboard_|scan_code_ready .is_wysiwyg = "true"; +defparam \ula_|ps2_keyboard_|scan_code_ready .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~0 ( +// Equation(s): +// \ula_|zx_keyboard_|Equal0~0_combout = (\ula_|ps2_keyboard_|shiftreg [7] & (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [7]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|Equal0~0 .lut_mask = 16'h0200; +defparam \ula_|zx_keyboard_|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~1 ( +// Equation(s): +// \ula_|zx_keyboard_|Equal0~1_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|Equal0~0_combout & !\ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|zx_keyboard_|Equal0~0_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|Equal0~1 .lut_mask = 16'h0020; +defparam \ula_|zx_keyboard_|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|released~0 ( +// Equation(s): +// \ula_|zx_keyboard_|released~0_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (\ula_|zx_keyboard_|Equal0~1_combout & ((\ula_|ps2_keyboard_|shiftreg [4]) # (\ula_|zx_keyboard_|released~q )))) # (!\ula_|ps2_keyboard_|scan_code_ready~q & +// (((\ula_|zx_keyboard_|released~q )))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|scan_code_ready~q ), + .datac(\ula_|zx_keyboard_|released~q ), + .datad(\ula_|zx_keyboard_|Equal0~1_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|released~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|released~0 .lut_mask = 16'hF830; +defparam \ula_|zx_keyboard_|released~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y8_N25 +dffeas \ula_|zx_keyboard_|released ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|released~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|released~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|released .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|released .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|extended~0 ( +// Equation(s): +// \ula_|zx_keyboard_|extended~0_combout = (\ula_|zx_keyboard_|Equal0~1_combout & ((\ula_|zx_keyboard_|extended~q ) # (!\ula_|ps2_keyboard_|shiftreg [4]))) + + .dataa(\ula_|zx_keyboard_|Equal0~1_combout ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|extended~q ), + .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|extended~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|extended~0 .lut_mask = 16'hA0AA; +defparam \ula_|zx_keyboard_|extended~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y8_N31 +dffeas \ula_|zx_keyboard_|extended ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|extended~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|ps2_keyboard_|scan_code_ready~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|extended~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|extended .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|extended .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~21 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][1]~21_combout = (!\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [7] & \ula_|ps2_keyboard_|scan_code_ready~q )) + + .dataa(\ula_|zx_keyboard_|extended~q ), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [7]), + .datad(\ula_|ps2_keyboard_|scan_code_ready~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][1]~21_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][1]~21 .lut_mask = 16'h0500; +defparam \ula_|zx_keyboard_|keys[7][1]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~22 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][4]~22_combout = (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [4]) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][4]~22_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][4]~22 .lut_mask = 16'hA0A0; +defparam \ula_|zx_keyboard_|keys[5][4]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][4]~23 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][4]~23_combout = (\ula_|zx_keyboard_|keys[7][1]~21_combout & (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[5][4]~22_combout & !\ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|zx_keyboard_|keys[7][1]~21_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|zx_keyboard_|keys[5][4]~22_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][4]~23_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][4]~23 .lut_mask = 16'h0020; +defparam \ula_|zx_keyboard_|keys[1][4]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][1]~24 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][1]~24_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[1][4]~23_combout )) + + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(gnd), + .datad(\ula_|zx_keyboard_|keys[1][4]~23_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][1]~24_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][1]~24 .lut_mask = 16'h2200; +defparam \ula_|zx_keyboard_|keys[2][1]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][1]~25 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][1]~25_combout = (\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[2][1]~24_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[2][1]~24_combout & ((\ula_|zx_keyboard_|keys[2][1]~q ))))) # +// (!\ula_|ps2_keyboard_|shiftreg [3] & (((\ula_|zx_keyboard_|keys[2][1]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|zx_keyboard_|keys[2][1]~q ), + .datad(\ula_|zx_keyboard_|keys[2][1]~24_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][1]~25_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][1]~25 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[2][1]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y9_N21 +dffeas \ula_|zx_keyboard_|keys[2][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[2][1]~25_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[2][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[2][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~0 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row~0_combout = ((\z80_|address_pins_|DFFE_apin_latch [10]) # (!\ula_|zx_keyboard_|keys[2][1]~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [10]), + .datad(\ula_|zx_keyboard_|keys[2][1]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row~0 .lut_mask = 16'hF3FF; +defparam \ula_|zx_keyboard_|key_row~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~26 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][1]~26_combout = (\ula_|zx_keyboard_|keys[7][1]~21_combout & (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[5][4]~22_combout & !\ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|zx_keyboard_|keys[7][1]~21_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|zx_keyboard_|keys[5][4]~22_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][1]~26_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][1]~26 .lut_mask = 16'h0020; +defparam \ula_|zx_keyboard_|keys[3][1]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~27 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][1]~27_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [3])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][1]~27_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][1]~27 .lut_mask = 16'h2200; +defparam \ula_|zx_keyboard_|keys[3][1]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~28 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][1]~28_combout = (\ula_|zx_keyboard_|keys[3][1]~26_combout & ((\ula_|zx_keyboard_|keys[3][1]~27_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][1]~27_combout & ((\ula_|zx_keyboard_|keys[3][1]~q +// ))))) # (!\ula_|zx_keyboard_|keys[3][1]~26_combout & (((\ula_|zx_keyboard_|keys[3][1]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[3][1]~26_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[3][1]~q ), + .datad(\ula_|zx_keyboard_|keys[3][1]~27_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][1]~28_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][1]~28 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[3][1]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y9_N29 +dffeas \ula_|zx_keyboard_|keys[3][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[3][1]~28_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[3][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[3][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N12 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[11]~11 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[11]~11_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|address [11])) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [11]))) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [11]), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [11]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[11]~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[11]~11 .lut_mask = 16'hDD88; +defparam \z80_|address_pins_|DFFE_apin_latch[11]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y13_N13 +dffeas \z80_|address_pins_|DFFE_apin_latch[11] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[11]~11_combout ), + .asdata(\z80_|address_latch_|Q [11]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [11]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[11] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y6_N16 +cycloneive_lcell_comb \z80_|address_pins_|abus[11]~19 ( +// Equation(s): +// \z80_|address_pins_|abus[11]~19_combout = (\z80_|address_pins_|DFFE_apin_latch [11]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [11]), + .cin(gnd), + .combout(\z80_|address_pins_|abus[11]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[11]~19 .lut_mask = 16'hFF0F; +defparam \z80_|address_pins_|abus[11]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~17 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][4]~17_combout = (!\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [7] & \ula_|ps2_keyboard_|scan_code_ready~q ))) + + .dataa(\ula_|zx_keyboard_|extended~q ), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [7]), + .datad(\ula_|ps2_keyboard_|scan_code_ready~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][4]~17_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][4]~17 .lut_mask = 16'h0100; +defparam \ula_|zx_keyboard_|keys[7][4]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~18 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][4]~18_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][4]~18_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][4]~18 .lut_mask = 16'h4000; +defparam \ula_|zx_keyboard_|keys[6][4]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][1]~19 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][1]~19_combout = (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[7][4]~17_combout & \ula_|zx_keyboard_|keys[6][4]~18_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|zx_keyboard_|keys[7][4]~17_combout ), + .datad(\ula_|zx_keyboard_|keys[6][4]~18_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][1]~19_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][1]~19 .lut_mask = 16'h4000; +defparam \ula_|zx_keyboard_|keys[1][1]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][1]~20 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][1]~20_combout = (\ula_|zx_keyboard_|keys[1][1]~19_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[1][1]~19_combout & ((\ula_|zx_keyboard_|keys[1][1]~q ))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[1][1]~q ), + .datad(\ula_|zx_keyboard_|keys[1][1]~19_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][1]~20_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][1]~20 .lut_mask = 16'h55F0; +defparam \ula_|zx_keyboard_|keys[1][1]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y7_N17 +dffeas \ula_|zx_keyboard_|keys[1][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[1][1]~20_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[1][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[1][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N4 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[9]~9 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[9]~9_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [9]))) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [9]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[9]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[9]~9 .lut_mask = 16'hDD88; +defparam \z80_|address_pins_|DFFE_apin_latch[9]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y10_N5 +dffeas \z80_|address_pins_|DFFE_apin_latch[9] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[9]~9_combout ), + .asdata(\z80_|address_latch_|Q [9]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [9]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[9] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N10 +cycloneive_lcell_comb \z80_|address_pins_|abus[9]~17 ( +// Equation(s): +// \z80_|address_pins_|abus[9]~17_combout = (\z80_|address_pins_|DFFE_apin_latch [9]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [9]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_pins_|abus[9]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[9]~17 .lut_mask = 16'hCFCF; +defparam \z80_|address_pins_|abus[9]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~13 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][0]~13_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (!\ula_|ps2_keyboard_|shiftreg [7] & !\ula_|zx_keyboard_|Equal0~1_combout )) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|scan_code_ready~q ), + .datac(\ula_|ps2_keyboard_|shiftreg [7]), + .datad(\ula_|zx_keyboard_|Equal0~1_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][0]~13_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][0]~13 .lut_mask = 16'h000C; +defparam \ula_|zx_keyboard_|keys[0][0]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~2 ( +// Equation(s): +// \ula_|zx_keyboard_|shifted~2_combout = (!\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|zx_keyboard_|extended~q & \ula_|zx_keyboard_|keys[0][0]~13_combout )) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|zx_keyboard_|extended~q ), + .datad(\ula_|zx_keyboard_|keys[0][0]~13_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|shifted~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|shifted~2 .lut_mask = 16'h0300; +defparam \ula_|zx_keyboard_|shifted~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~14 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][1]~14_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [4] $ (\ula_|ps2_keyboard_|shiftreg [2])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][1]~14_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][1]~14 .lut_mask = 16'h1020; +defparam \ula_|zx_keyboard_|keys[0][1]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~15 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][1]~15_combout = (\ula_|zx_keyboard_|keys[0][1]~14_combout & ((\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [1])) # (!\ula_|ps2_keyboard_|shiftreg [4] & +// (\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [1])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|zx_keyboard_|keys[0][1]~14_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][1]~15_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][1]~15 .lut_mask = 16'h0840; +defparam \ula_|zx_keyboard_|keys[0][1]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr17~0 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr17~0_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [3]))) # (!\ula_|ps2_keyboard_|shiftreg [1] & +// (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [3]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr17~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr17~0 .lut_mask = 16'h4002; +defparam \ula_|zx_keyboard_|WideOr17~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~5 ( +// Equation(s): +// \ula_|zx_keyboard_|shifted~5_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|zx_keyboard_|WideOr17~0_combout )) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|zx_keyboard_|WideOr17~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|shifted~5_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|shifted~5 .lut_mask = 16'h2020; +defparam \ula_|zx_keyboard_|shifted~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~4 ( +// Equation(s): +// \ula_|zx_keyboard_|shifted~4_combout = (\ula_|zx_keyboard_|shifted~5_combout & ((\ula_|zx_keyboard_|shifted~2_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|shifted~2_combout & ((\ula_|zx_keyboard_|shifted~q ))))) # +// (!\ula_|zx_keyboard_|shifted~5_combout & (((\ula_|zx_keyboard_|shifted~q )))) + + .dataa(\ula_|zx_keyboard_|shifted~5_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|shifted~q ), + .datad(\ula_|zx_keyboard_|shifted~2_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|shifted~4_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|shifted~4 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|shifted~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y10_N27 +dffeas \ula_|zx_keyboard_|shifted ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|shifted~4_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|shifted~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|shifted .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|shifted .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~12 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][1]~12_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & !\ula_|ps2_keyboard_|shiftreg [4])) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|shifted~q ), + .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][1]~12_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][1]~12 .lut_mask = 16'hCCCF; +defparam \ula_|zx_keyboard_|keys[0][1]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~16 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][1]~16_combout = (\ula_|zx_keyboard_|shifted~2_combout & ((\ula_|zx_keyboard_|keys[0][1]~15_combout & ((!\ula_|zx_keyboard_|keys[0][1]~12_combout ))) # (!\ula_|zx_keyboard_|keys[0][1]~15_combout & +// (\ula_|zx_keyboard_|keys[0][1]~q )))) # (!\ula_|zx_keyboard_|shifted~2_combout & (((\ula_|zx_keyboard_|keys[0][1]~q )))) + + .dataa(\ula_|zx_keyboard_|shifted~2_combout ), + .datab(\ula_|zx_keyboard_|keys[0][1]~15_combout ), + .datac(\ula_|zx_keyboard_|keys[0][1]~q ), + .datad(\ula_|zx_keyboard_|keys[0][1]~12_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][1]~16_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][1]~16 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[0][1]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y10_N21 +dffeas \ula_|zx_keyboard_|keys[0][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[0][1]~16_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[0][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[0][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N0 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[8]~8 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[8]~8_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [8]))) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [8]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[8]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[8]~8 .lut_mask = 16'hDD88; +defparam \z80_|address_pins_|DFFE_apin_latch[8]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y10_N1 +dffeas \z80_|address_pins_|DFFE_apin_latch[8] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[8]~8_combout ), + .asdata(\z80_|address_latch_|Q [8]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [8]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[8] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N24 +cycloneive_lcell_comb \z80_|address_pins_|abus[8]~18 ( +// Equation(s): +// \z80_|address_pins_|abus[8]~18_combout = (\z80_|address_pins_|DFFE_apin_latch [8]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [8]), + .cin(gnd), + .combout(\z80_|address_pins_|abus[8]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[8]~18 .lut_mask = 16'hFF0F; +defparam \z80_|address_pins_|abus[8]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N2 +cycloneive_lcell_comb \D[1]~26 ( +// Equation(s): +// \D[1]~26_combout = (\ula_|zx_keyboard_|keys[1][1]~q & (\z80_|address_pins_|abus[9]~17_combout & ((\z80_|address_pins_|abus[8]~18_combout ) # (!\ula_|zx_keyboard_|keys[0][1]~q )))) # (!\ula_|zx_keyboard_|keys[1][1]~q & +// (((\z80_|address_pins_|abus[8]~18_combout ) # (!\ula_|zx_keyboard_|keys[0][1]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[1][1]~q ), + .datab(\z80_|address_pins_|abus[9]~17_combout ), + .datac(\ula_|zx_keyboard_|keys[0][1]~q ), + .datad(\z80_|address_pins_|abus[8]~18_combout ), + .cin(gnd), + .combout(\D[1]~26_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~26 .lut_mask = 16'hDD0D; +defparam \D[1]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N4 +cycloneive_lcell_comb \D[1]~27 ( +// Equation(s): +// \D[1]~27_combout = (\ula_|zx_keyboard_|key_row~0_combout & (\D[1]~26_combout & ((\z80_|address_pins_|abus[11]~19_combout ) # (!\ula_|zx_keyboard_|keys[3][1]~q )))) + + .dataa(\ula_|zx_keyboard_|key_row~0_combout ), + .datab(\ula_|zx_keyboard_|keys[3][1]~q ), + .datac(\z80_|address_pins_|abus[11]~19_combout ), + .datad(\D[1]~26_combout ), + .cin(gnd), + .combout(\D[1]~27_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~27 .lut_mask = 16'hA200; +defparam \D[1]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N16 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[12]~12 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[12]~12_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [12]))) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [12]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[12]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[12]~12 .lut_mask = 16'hDD88; +defparam \z80_|address_pins_|DFFE_apin_latch[12]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y13_N17 +dffeas \z80_|address_pins_|DFFE_apin_latch[12] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[12]~12_combout ), + .asdata(\z80_|address_latch_|Q [12]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [12]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[12] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N28 +cycloneive_lcell_comb \z80_|address_pins_|abus[12]~21 ( +// Equation(s): +// \z80_|address_pins_|abus[12]~21_combout = (\z80_|address_pins_|DFFE_apin_latch [12]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [12]), + .cin(gnd), + .combout(\z80_|address_pins_|abus[12]~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[12]~21 .lut_mask = 16'hFF0F; +defparam \z80_|address_pins_|abus[12]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N2 +cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out ( +// Equation(s): +// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout = \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout $ (\z80_|address_latch_|Q [13]) + + .dataa(gnd), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ), + .datac(gnd), + .datad(\z80_|address_latch_|Q [13]), + .cin(gnd), + .combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out .lut_mask = 16'h33CC; +defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N6 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[13]~13 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[13]~13_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [13])) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|abusz [13]), + .datac(gnd), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[13]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[13]~13 .lut_mask = 16'hEE44; +defparam \z80_|address_pins_|DFFE_apin_latch[13]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y13_N7 +dffeas \z80_|address_pins_|DFFE_apin_latch[13] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[13]~13_combout ), + .asdata(\z80_|address_latch_|Q [13]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [13]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[13] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N6 +cycloneive_lcell_comb \z80_|address_pins_|abus[13]~20 ( +// Equation(s): +// \z80_|address_pins_|abus[13]~20_combout = (\z80_|address_pins_|DFFE_apin_latch [13]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(gnd), + .datad(\z80_|address_pins_|DFFE_apin_latch [13]), + .cin(gnd), + .combout(\z80_|address_pins_|abus[13]~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[13]~20 .lut_mask = 16'hFF33; +defparam \z80_|address_pins_|abus[13]~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~36 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][1]~36_combout = (!\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [5])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][1]~36_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1]~36 .lut_mask = 16'h0005; +defparam \ula_|zx_keyboard_|keys[5][1]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~34 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][1]~34_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|zx_keyboard_|extended~q & \ula_|zx_keyboard_|keys[0][0]~13_combout )) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|zx_keyboard_|extended~q ), + .datad(\ula_|zx_keyboard_|keys[0][0]~13_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][1]~34_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1]~34 .lut_mask = 16'h0300; +defparam \ula_|zx_keyboard_|keys[5][1]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~35 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][1]~35_combout = (\ula_|zx_keyboard_|keys[5][1]~34_combout & (\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [2])) + + .dataa(\ula_|zx_keyboard_|keys[5][1]~34_combout ), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][1]~35_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1]~35 .lut_mask = 16'hA000; +defparam \ula_|zx_keyboard_|keys[5][1]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~33 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][1]~33_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [3] & \ula_|zx_keyboard_|shifted~q )) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|zx_keyboard_|shifted~q ), + .datac(gnd), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][1]~33_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1]~33 .lut_mask = 16'hFF88; +defparam \ula_|zx_keyboard_|keys[5][1]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~37 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][1]~37_combout = (\ula_|zx_keyboard_|keys[5][1]~36_combout & ((\ula_|zx_keyboard_|keys[5][1]~35_combout & ((!\ula_|zx_keyboard_|keys[5][1]~33_combout ))) # (!\ula_|zx_keyboard_|keys[5][1]~35_combout & +// (\ula_|zx_keyboard_|keys[5][1]~q )))) # (!\ula_|zx_keyboard_|keys[5][1]~36_combout & (((\ula_|zx_keyboard_|keys[5][1]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][1]~36_combout ), + .datab(\ula_|zx_keyboard_|keys[5][1]~35_combout ), + .datac(\ula_|zx_keyboard_|keys[5][1]~q ), + .datad(\ula_|zx_keyboard_|keys[5][1]~33_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][1]~37_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1]~37 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[5][1]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y10_N23 +dffeas \ula_|zx_keyboard_|keys[5][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[5][1]~37_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[5][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[5][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][1]~29 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][1]~29_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [2]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][1]~29_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][1]~29 .lut_mask = 16'h0F00; +defparam \ula_|zx_keyboard_|keys[4][1]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~30 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][2]~30_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [5])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][2]~30_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2]~30 .lut_mask = 16'h0202; +defparam \ula_|zx_keyboard_|keys[7][2]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~31 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][2]~31_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[7][1]~21_combout & (\ula_|zx_keyboard_|keys[7][2]~30_combout & \ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|zx_keyboard_|keys[7][1]~21_combout ), + .datac(\ula_|zx_keyboard_|keys[7][2]~30_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][2]~31_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][2]~31 .lut_mask = 16'h4000; +defparam \ula_|zx_keyboard_|keys[5][2]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][1]~32 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][1]~32_combout = (\ula_|zx_keyboard_|keys[4][1]~29_combout & ((\ula_|zx_keyboard_|keys[5][2]~31_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[5][2]~31_combout & ((\ula_|zx_keyboard_|keys[4][1]~q +// ))))) # (!\ula_|zx_keyboard_|keys[4][1]~29_combout & (((\ula_|zx_keyboard_|keys[4][1]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[4][1]~29_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[4][1]~q ), + .datad(\ula_|zx_keyboard_|keys[5][2]~31_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][1]~32_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][1]~32 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[4][1]~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y10_N25 +dffeas \ula_|zx_keyboard_|keys[4][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[4][1]~32_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[4][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[4][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N28 +cycloneive_lcell_comb \D[1]~28 ( +// Equation(s): +// \D[1]~28_combout = (\z80_|address_pins_|abus[12]~21_combout & ((\z80_|address_pins_|abus[13]~20_combout ) # ((!\ula_|zx_keyboard_|keys[5][1]~q )))) # (!\z80_|address_pins_|abus[12]~21_combout & (!\ula_|zx_keyboard_|keys[4][1]~q & +// ((\z80_|address_pins_|abus[13]~20_combout ) # (!\ula_|zx_keyboard_|keys[5][1]~q )))) + + .dataa(\z80_|address_pins_|abus[12]~21_combout ), + .datab(\z80_|address_pins_|abus[13]~20_combout ), + .datac(\ula_|zx_keyboard_|keys[5][1]~q ), + .datad(\ula_|zx_keyboard_|keys[4][1]~q ), + .cin(gnd), + .combout(\D[1]~28_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~28 .lut_mask = 16'h8ACF; +defparam \D[1]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N6 +cycloneive_lcell_comb \z80_|address_pins_|abus[0]~16 ( +// Equation(s): +// \z80_|address_pins_|abus[0]~16_combout = (\z80_|address_pins_|DFFE_apin_latch [0]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [0]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_pins_|abus[0]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[0]~16 .lut_mask = 16'hCFCF; +defparam \z80_|address_pins_|abus[0]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N18 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[14]~14 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[14]~14_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|address [14])) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [14]))) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [14]), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [14]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[14]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[14]~14 .lut_mask = 16'hDD88; +defparam \z80_|address_pins_|DFFE_apin_latch[14]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y13_N19 +dffeas \z80_|address_pins_|DFFE_apin_latch[14] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[14]~14_combout ), + .asdata(\z80_|address_latch_|Q [14]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [14]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[14] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N20 +cycloneive_lcell_comb \z80_|address_pins_|abus[14]~23 ( +// Equation(s): +// \z80_|address_pins_|abus[14]~23_combout = (\z80_|address_pins_|DFFE_apin_latch [14]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [14]), + .cin(gnd), + .combout(\z80_|address_pins_|abus[14]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[14]~23 .lut_mask = 16'hFF0F; +defparam \z80_|address_pins_|abus[14]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~40 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][1]~40_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [1])) # (!\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [4] & +// \ula_|ps2_keyboard_|shiftreg [1])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][1]~40_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1]~40 .lut_mask = 16'h1188; +defparam \ula_|zx_keyboard_|keys[6][1]~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~41 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][1]~41_combout = (\ula_|zx_keyboard_|keys[6][1]~40_combout & (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [2] $ (\ula_|ps2_keyboard_|shiftreg [3])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|zx_keyboard_|keys[6][1]~40_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][1]~41_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1]~41 .lut_mask = 16'h6000; +defparam \ula_|zx_keyboard_|keys[6][1]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~39 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][1]~39_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|zx_keyboard_|keys[0][0]~13_combout & !\ula_|zx_keyboard_|extended~q ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|zx_keyboard_|keys[0][0]~13_combout ), + .datad(\ula_|zx_keyboard_|extended~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][1]~39_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1]~39 .lut_mask = 16'h0020; +defparam \ula_|zx_keyboard_|keys[6][1]~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~38 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][1]~38_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [2])) + + .dataa(\ula_|zx_keyboard_|shifted~q ), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][1]~38_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1]~38 .lut_mask = 16'hFFA0; +defparam \ula_|zx_keyboard_|keys[6][1]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~42 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][1]~42_combout = (\ula_|zx_keyboard_|keys[6][1]~41_combout & ((\ula_|zx_keyboard_|keys[6][1]~39_combout & ((!\ula_|zx_keyboard_|keys[6][1]~38_combout ))) # (!\ula_|zx_keyboard_|keys[6][1]~39_combout & +// (\ula_|zx_keyboard_|keys[6][1]~q )))) # (!\ula_|zx_keyboard_|keys[6][1]~41_combout & (((\ula_|zx_keyboard_|keys[6][1]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[6][1]~41_combout ), + .datab(\ula_|zx_keyboard_|keys[6][1]~39_combout ), + .datac(\ula_|zx_keyboard_|keys[6][1]~q ), + .datad(\ula_|zx_keyboard_|keys[6][1]~38_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][1]~42_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1]~42 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[6][1]~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y9_N23 +dffeas \ula_|zx_keyboard_|keys[6][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[6][1]~42_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[6][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[6][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~4 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~4_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [2])) # (!\ula_|ps2_keyboard_|shiftreg [1] & +// (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [2])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~4_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~4 .lut_mask = 16'h0402; +defparam \ula_|zx_keyboard_|WideOr16~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~2 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~2_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [1])) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~2 .lut_mask = 16'h000C; +defparam \ula_|zx_keyboard_|WideOr16~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~7 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~7_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|WideOr16~4_combout )) # (!\ula_|ps2_keyboard_|shiftreg [6] & (((\ula_|zx_keyboard_|WideOr16~2_combout & !\ula_|ps2_keyboard_|shiftreg [2])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|zx_keyboard_|WideOr16~4_combout ), + .datac(\ula_|zx_keyboard_|WideOr16~2_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~7_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~7 .lut_mask = 16'h88D8; +defparam \ula_|zx_keyboard_|WideOr16~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~5 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~5_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [1] & ((!\ula_|ps2_keyboard_|shiftreg [2])))) # (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & +// ((\ula_|ps2_keyboard_|shiftreg [1]) # (\ula_|ps2_keyboard_|shiftreg [2])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~5_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~5 .lut_mask = 16'h3064; +defparam \ula_|zx_keyboard_|WideOr16~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y10_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~6 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~6_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|zx_keyboard_|WideOr16~7_combout )) # (!\ula_|ps2_keyboard_|shiftreg [4] & (((\ula_|ps2_keyboard_|shiftreg [6] & \ula_|zx_keyboard_|WideOr16~5_combout )))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|zx_keyboard_|WideOr16~7_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(\ula_|zx_keyboard_|WideOr16~5_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~6_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~6 .lut_mask = 16'hD888; +defparam \ula_|zx_keyboard_|WideOr16~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~43 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][1]~43_combout = (!\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [7] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|scan_code_ready~q ))) + + .dataa(\ula_|zx_keyboard_|extended~q ), + .datab(\ula_|ps2_keyboard_|shiftreg [7]), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|ps2_keyboard_|scan_code_ready~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][1]~43_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][1]~43 .lut_mask = 16'h0100; +defparam \ula_|zx_keyboard_|keys[7][1]~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y10_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~44 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][1]~44_combout = (\ula_|zx_keyboard_|WideOr16~6_combout & ((\ula_|zx_keyboard_|keys[7][1]~43_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[7][1]~43_combout & (\ula_|zx_keyboard_|keys[7][1]~q )))) +// # (!\ula_|zx_keyboard_|WideOr16~6_combout & (((\ula_|zx_keyboard_|keys[7][1]~q )))) + + .dataa(\ula_|zx_keyboard_|WideOr16~6_combout ), + .datab(\ula_|zx_keyboard_|keys[7][1]~43_combout ), + .datac(\ula_|zx_keyboard_|keys[7][1]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][1]~44_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][1]~44 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[7][1]~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y10_N25 +dffeas \ula_|zx_keyboard_|keys[7][1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[7][1]~44_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[7][1]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][1] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[7][1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N10 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[15]~15 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[15]~15_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address[15]~1_combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [15])) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|abusz [15]), + .datac(gnd), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|address[15]~1_combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[15]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[15]~15 .lut_mask = 16'hEE44; +defparam \z80_|address_pins_|DFFE_apin_latch[15]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y13_N11 +dffeas \z80_|address_pins_|DFFE_apin_latch[15] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[15]~15_combout ), + .asdata(\z80_|address_latch_|Q [15]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [15]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[15] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N8 +cycloneive_lcell_comb \z80_|address_pins_|abus[15]~22 ( +// Equation(s): +// \z80_|address_pins_|abus[15]~22_combout = (\z80_|address_pins_|DFFE_apin_latch [15]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [15]), + .cin(gnd), + .combout(\z80_|address_pins_|abus[15]~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[15]~22 .lut_mask = 16'hFF0F; +defparam \z80_|address_pins_|abus[15]~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N16 +cycloneive_lcell_comb \D[1]~29 ( +// Equation(s): +// \D[1]~29_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\z80_|address_pins_|abus[15]~22_combout ) # (!\ula_|zx_keyboard_|keys[7][1]~q )))) # (!\z80_|address_pins_|abus[14]~23_combout & (!\ula_|zx_keyboard_|keys[6][1]~q & +// ((\z80_|address_pins_|abus[15]~22_combout ) # (!\ula_|zx_keyboard_|keys[7][1]~q )))) + + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\ula_|zx_keyboard_|keys[6][1]~q ), + .datac(\ula_|zx_keyboard_|keys[7][1]~q ), + .datad(\z80_|address_pins_|abus[15]~22_combout ), + .cin(gnd), + .combout(\D[1]~29_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~29 .lut_mask = 16'hBB0B; +defparam \D[1]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N26 +cycloneive_lcell_comb \D[1]~30 ( +// Equation(s): +// \D[1]~30_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[1]~27_combout & (\D[1]~28_combout & \D[1]~29_combout ))) + + .dataa(\D[1]~27_combout ), + .datab(\D[1]~28_combout ), + .datac(\z80_|address_pins_|abus[0]~16_combout ), + .datad(\D[1]~29_combout ), + .cin(gnd), + .combout(\D[1]~30_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~30 .lut_mask = 16'hF8F0; +defparam \D[1]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N20 +cycloneive_lcell_comb \ExtRamWE~0 ( +// Equation(s): +// \ExtRamWE~0_combout = (!\z80_|memory_ifc_|nIORQ_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (!\z80_|memory_ifc_|nRD_out~2_combout & \z80_|memory_ifc_|nWR_out~0_combout ))) + + .dataa(\z80_|memory_ifc_|nIORQ_out~0_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|memory_ifc_|nRD_out~2_combout ), + .datad(\z80_|memory_ifc_|nWR_out~0_combout ), + .cin(gnd), + .combout(\ExtRamWE~0_combout ), + .cout()); +// synopsys translate_off +defparam \ExtRamWE~0 .lut_mask = 16'h0400; +defparam \ExtRamWE~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N0 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2] = (!\z80_|address_pins_|abus[14]~23_combout & (\ExtRamWE~0_combout & (\z80_|address_pins_|abus[15]~22_combout & \z80_|address_pins_|abus[13]~20_combout ))) + + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\ExtRamWE~0_combout ), + .datac(\z80_|address_pins_|abus[15]~22_combout ), + .datad(\z80_|address_pins_|abus[13]~20_combout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] .lut_mask = 16'h4000; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N10 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout = (!\z80_|address_pins_|DFFE_apin_latch [14] & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \z80_|address_pins_|DFFE_apin_latch [13])) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [14]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [13]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 .lut_mask = 16'h3000; +defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N6 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[1]~1 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[1]~1_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [1])) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|abusz [1]), + .datac(gnd), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[1]~1 .lut_mask = 16'hEE44; +defparam \z80_|address_pins_|DFFE_apin_latch[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y11_N7 +dffeas \z80_|address_pins_|DFFE_apin_latch[1] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[1]~1_combout ), + .asdata(\z80_|address_latch_|Q [1]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[1] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N10 +cycloneive_lcell_comb \z80_|address_pins_|abus[1]~25 ( +// Equation(s): +// \z80_|address_pins_|abus[1]~25_combout = (\z80_|address_pins_|DFFE_apin_latch [1]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [1]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_pins_|abus[1]~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[1]~25 .lut_mask = 16'hCFCF; +defparam \z80_|address_pins_|abus[1]~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N12 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[2]~2 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[2]~2_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [2]))) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [2]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[2]~2 .lut_mask = 16'hDD88; +defparam \z80_|address_pins_|DFFE_apin_latch[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y11_N13 +dffeas \z80_|address_pins_|DFFE_apin_latch[2] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[2]~2_combout ), + .asdata(\z80_|address_latch_|Q [2]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[2] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N16 +cycloneive_lcell_comb \z80_|address_pins_|abus[2]~26 ( +// Equation(s): +// \z80_|address_pins_|abus[2]~26_combout = (\z80_|address_pins_|DFFE_apin_latch [2]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [2]), + .cin(gnd), + .combout(\z80_|address_pins_|abus[2]~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[2]~26 .lut_mask = 16'hFF0F; +defparam \z80_|address_pins_|abus[2]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N28 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[3]~3 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[3]~3_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [3])) + + .dataa(\z80_|address_latch_|abusz [3]), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ), + .datac(gnd), + .datad(\z80_|execute_|ctl_apin_mux~2_combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[3]~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[3]~3 .lut_mask = 16'hCCAA; +defparam \z80_|address_pins_|DFFE_apin_latch[3]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y11_N29 +dffeas \z80_|address_pins_|DFFE_apin_latch[3] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[3]~3_combout ), + .asdata(\z80_|address_latch_|Q [3]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[3] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N0 +cycloneive_lcell_comb \z80_|address_pins_|abus[3]~27 ( +// Equation(s): +// \z80_|address_pins_|abus[3]~27_combout = (\z80_|address_pins_|DFFE_apin_latch [3]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [3]), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_pins_|abus[3]~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[3]~27 .lut_mask = 16'hAFAF; +defparam \z80_|address_pins_|abus[3]~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N16 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[4]~4 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[4]~4_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [4]))) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [4]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[4]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[4]~4 .lut_mask = 16'hDD88; +defparam \z80_|address_pins_|DFFE_apin_latch[4]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y10_N17 +dffeas \z80_|address_pins_|DFFE_apin_latch[4] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[4]~4_combout ), + .asdata(\z80_|address_latch_|Q [4]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[4] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N6 +cycloneive_lcell_comb \z80_|address_pins_|abus[4]~28 ( +// Equation(s): +// \z80_|address_pins_|abus[4]~28_combout = (\z80_|address_pins_|DFFE_apin_latch [4]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [4]), + .cin(gnd), + .combout(\z80_|address_pins_|abus[4]~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[4]~28 .lut_mask = 16'hFF0F; +defparam \z80_|address_pins_|abus[4]~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N18 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[5]~5 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[5]~5_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [5]))) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [5]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[5]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[5]~5 .lut_mask = 16'hDD88; +defparam \z80_|address_pins_|DFFE_apin_latch[5]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y10_N19 +dffeas \z80_|address_pins_|DFFE_apin_latch[5] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[5]~5_combout ), + .asdata(\z80_|address_latch_|Q [5]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[5] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N30 +cycloneive_lcell_comb \z80_|address_pins_|abus[5]~29 ( +// Equation(s): +// \z80_|address_pins_|abus[5]~29_combout = (\z80_|address_pins_|DFFE_apin_latch [5]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [5]), + .cin(gnd), + .combout(\z80_|address_pins_|abus[5]~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[5]~29 .lut_mask = 16'hFF0F; +defparam \z80_|address_pins_|abus[5]~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N14 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[6]~6 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[6]~6_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|address [6])) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [6]))) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|address [6]), + .datac(gnd), + .datad(\z80_|address_latch_|abusz [6]), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[6]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[6]~6 .lut_mask = 16'hDD88; +defparam \z80_|address_pins_|DFFE_apin_latch[6]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y10_N15 +dffeas \z80_|address_pins_|DFFE_apin_latch[6] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[6]~6_combout ), + .asdata(\z80_|address_latch_|Q [6]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[6] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y10_N26 +cycloneive_lcell_comb \z80_|address_pins_|abus[6]~30 ( +// Equation(s): +// \z80_|address_pins_|abus[6]~30_combout = (\z80_|address_pins_|DFFE_apin_latch [6]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [6]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|address_pins_|abus[6]~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[6]~30 .lut_mask = 16'hCFCF; +defparam \z80_|address_pins_|abus[6]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y13_N20 +cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[7]~7 ( +// Equation(s): +// \z80_|address_pins_|DFFE_apin_latch[7]~7_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [7])) + + .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), + .datab(\z80_|address_latch_|abusz [7]), + .datac(gnd), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ), + .cin(gnd), + .combout(\z80_|address_pins_|DFFE_apin_latch[7]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[7]~7 .lut_mask = 16'hEE44; +defparam \z80_|address_pins_|DFFE_apin_latch[7]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y13_N21 +dffeas \z80_|address_pins_|DFFE_apin_latch[7] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|address_pins_|DFFE_apin_latch[7]~7_combout ), + .asdata(\z80_|address_latch_|Q [7]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|address_pins_|DFFE_apin_latch [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|address_pins_|DFFE_apin_latch[7] .is_wysiwyg = "true"; +defparam \z80_|address_pins_|DFFE_apin_latch[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N24 +cycloneive_lcell_comb \z80_|address_pins_|abus[7]~31 ( +// Equation(s): +// \z80_|address_pins_|abus[7]~31_combout = (\z80_|address_pins_|DFFE_apin_latch [7]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_pins_|DFFE_apin_latch [7]), + .cin(gnd), + .combout(\z80_|address_pins_|abus[7]~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[7]~31 .lut_mask = 16'hFF55; +defparam \z80_|address_pins_|abus[7]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N0 +cycloneive_lcell_comb \z80_|address_pins_|abus[10]~24 ( +// Equation(s): +// \z80_|address_pins_|abus[10]~24_combout = (\z80_|address_pins_|DFFE_apin_latch [10]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_pins_|DFFE_apin_latch [10]), + .cin(gnd), + .combout(\z80_|address_pins_|abus[10]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|address_pins_|abus[10]~24 .lut_mask = 16'hFF55; +defparam \z80_|address_pins_|abus[10]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y12_N0 cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a9 ( .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), .portare(vcc), @@ -41359,7 +39084,7 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a9 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[1]~34_combout }), + .portadatain({\D[1]~32_combout }), .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , \z80_|address_pins_|abus[0]~16_combout }), @@ -41400,26 +39125,187 @@ defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 204 defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: LCCOMB_X32_Y14_N28 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0 ( +// Location: LCCOMB_X29_Y11_N4 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] ( // Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout )))) +// \ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2] = (!\z80_|address_pins_|abus[14]~23_combout & (\ExtRamWE~0_combout & (\z80_|address_pins_|abus[15]~22_combout & !\z80_|address_pins_|abus[13]~20_combout ))) - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ), + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\ExtRamWE~0_combout ), + .datac(\z80_|address_pins_|abus[15]~22_combout ), + .datad(\z80_|address_pins_|abus[13]~20_combout ), .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout ), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), .cout()); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0 .lut_mask = 16'hDC98; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0 .sum_lutc_input = "datac"; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] .lut_mask = 16'h0040; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X33_Y19_N0 +// Location: LCCOMB_X23_Y10_N0 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout = (!\z80_|address_pins_|DFFE_apin_latch [14] & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|address_pins_|DFFE_apin_latch [13])) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [14]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [13]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 .lut_mask = 16'h0030; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y10_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a1 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[1]~32_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N22 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout = \z80_|address_pins_|abus[13]~20_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_pins_|abus[13]~20_combout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder .lut_mask = 16'hFF00; +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y10_N23 +dffeas \ram1|altsyncram_component|auto_generated|address_reg_a[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram1|altsyncram_component|auto_generated|address_reg_a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true"; +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X23_Y10_N7 +dffeas \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ram1|altsyncram_component|auto_generated|address_reg_a [0]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true"; +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N24 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2] = (\z80_|address_pins_|abus[14]~23_combout & (\ExtRamWE~0_combout & (\z80_|address_pins_|abus[15]~22_combout & !\z80_|address_pins_|abus[13]~20_combout ))) + + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\ExtRamWE~0_combout ), + .datac(\z80_|address_pins_|abus[15]~22_combout ), + .datad(\z80_|address_pins_|abus[13]~20_combout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] .lut_mask = 16'h0080; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y10_N12 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout = (!\z80_|address_pins_|DFFE_apin_latch [13] & (\z80_|address_pins_|DFFE_apin_latch [14] & \z80_|resets_|SYNTHESIZED_WIRE_12~q )) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [13]), + .datac(\z80_|address_pins_|DFFE_apin_latch [14]), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 .lut_mask = 16'h3000; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y8_N0 cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a17 ( .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), .portare(vcc), @@ -41435,7 +39321,7 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a17 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[1]~34_combout }), + .portadatain({\D[1]~32_combout }), .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , \z80_|address_pins_|abus[0]~16_combout }), @@ -41476,7 +39362,98 @@ defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init1 = 20 defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: M9K_X33_Y20_N0 +// Location: FF_X23_Y14_N5 +dffeas \ram1|altsyncram_component|auto_generated|address_reg_a[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|address_pins_|abus[14]~23_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram1|altsyncram_component|auto_generated|address_reg_a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1] .is_wysiwyg = "true"; +defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X23_Y14_N27 +dffeas \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ram1|altsyncram_component|auto_generated|address_reg_a [1]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] .is_wysiwyg = "true"; +defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N8 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0 .lut_mask = 16'hFC22; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N18 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2] = (\z80_|address_pins_|abus[14]~23_combout & (\ExtRamWE~0_combout & (\z80_|address_pins_|abus[15]~22_combout & \z80_|address_pins_|abus[13]~20_combout ))) + + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\ExtRamWE~0_combout ), + .datac(\z80_|address_pins_|abus[15]~22_combout ), + .datad(\z80_|address_pins_|abus[13]~20_combout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] .lut_mask = 16'h8000; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y10_N30 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout = ((\z80_|address_pins_|DFFE_apin_latch [13] & \z80_|address_pins_|DFFE_apin_latch [14])) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [13]), + .datac(\z80_|address_pins_|DFFE_apin_latch [14]), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 .lut_mask = 16'hC0FF; +defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y7_N0 cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a25 ( .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), .portare(vcc), @@ -41492,7 +39469,7 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a25 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[1]~34_combout }), + .portadatain({\D[1]~32_combout }), .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , \z80_|address_pins_|abus[0]~16_combout }), @@ -41533,28 +39510,875 @@ defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init1 = 20 defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: LCCOMB_X32_Y14_N16 +// Location: LCCOMB_X31_Y10_N6 cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1 ( // Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout & -// ((\ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout )))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout )) +// \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout = (\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout & (((\ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout & +// (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]))) - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ), .datab(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout ), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), .datad(\ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ), .cin(gnd), .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ), .cout()); // synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1 .lut_mask = 16'hEC64; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1 .lut_mask = 16'hEC2C; defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X33_Y24_N0 +// Location: M9K_X33_Y2_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a1 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h35C65240B61076066A23CE4CFC5E76063A1C2AE07DF555007338BDC080EA0C23082C891C76A4845096304A0D8502080C1198911998821D09C29CA830C337499236E0548D65FF9125A765F0220F6EB9D1B318244CC6CA2CBC9CEC6979C14EB28DE2E0440C6CBD61341FC178649A852D4A2A0627C688D905B882524E191E7951EAEF30312A73337CBAD4838F42A3293859CD169240D8E652F6D72D8D19D56DD7675939FC47C933E1B0AEF12A484454C247B00A6BEC5402AA08B5106E3065602454C80CEC08A7F5F85CE65326632B4C4F3920019A35AE2AEB321131046EE45B81D4EFD5995634050D4CFEC166B032B6415553AF0358304080D9DD0A2E5948593830; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h376E511217E00B624A46BA2E4CC10B729C326F710F24CFE78C5E63F3024B17CC5E1380C938A0A16C9B696272DE7A2948BE8AFE81310146B8AAE5E549FA27EFBE27929938B8E10530250877A4998D0DF0004852125C20CA8D4279881E41208B14198817644F293AC1946061117122A39D8841818C1389D51BDAC549181902516571163594CEC5863F0F56625E221D6B8180848C6B2BE24AA0AEEE5D187201CAAE6AA394A8644314895565192AE415630A42894D6EF21343903B348EED8642F2310644C9567C0BF9911B870B989C59330089AA4C8065AB1B11132213EE0FD830817DE6C2ED45D76325CA2A8E198859334553AB02945CAB1F17C142288008073004; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h20721F982534A8179F13E2C6328CDE7D2A73087D3A9314419022103DFF7677769FE2D1F27443253D58403577C801AE23371F00290A17E1C4A40258BFD204230EE9969472A81B83113144528F831AA6C3221E137C1E9C670E26809A894013828D9E2DBCBF62498A769893D7218899245CD18AE49F0146517422EE475D520029ED39BCEF6BF4D23532957455F1C80115524179D59C4C4534DF7296991146CE24508366123AA809AB30B47977571C5D70397A93C723106D0A2C254714359DC7C9E13AE624C94932927924D20024CD638A05C8620023319662D80E05805625BC4A4006C78011F78D8B82E59F0CD4B32D6801669BE3EB0B96960DFF152005EC7C16CB; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h9C8CA06AA05B63C89A59A3E4E80807B27A70B0006624C4AC4A0595CCD8CA20824CA272352720BCD900A6D79BFD9D0595EC0D044ABC8CC28E9AE946E3D2000A4EFA4F91915C6AC9D8570C292F10848189906127BCBE06FFE92DAFB4AAFB240D88DDBB7B207EFA1709B05E1C4801BD45625A36BB62220506E171891964A31BED2215408676F600F490FAA59B488C7998CC8CCC28922AC62644EEBB432EEECB51B16CDEE7468681D6C31E4991CA3736E9ACB7531EC6D8BBCD453718101EA25D79278C6AC955A8A6140421573E413CF5A80AA1436D8B4C31A2AB26D2A61CE834248BAD5751BD429B4F61318427560CE39D49299002165212181064E24FF0093B997B; +// synopsys translate_on + +// Location: M9K_X22_Y2_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a9 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h420000004200000000000000000080000000000000000000000000000030004480000000424202423E1E3E02304C3C0C3C7E7E40403E427E3402421824347C1C0400280000003C3406303220344C403C0400100010100000005062742400000091991809FB3BD9084A1241F5015988B3C506031934089E0E1FA8043DDAF2CC07D94A6F2B1D133C211222B22C787D430E45D4C53282288077DFC0F704AAD55127A2BEAEA114958D2817AB1213183A4E1A15E3690A08A33B429284A202011A1243D49CACA1C0A441405A720D21A0921294045F746229E287B95E956AA3DE0CA3B7A019C8039C4DDA6BC99371248CC6008A54CB84503442C4F91309238ECB252072; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h81F3167814687CBD683E54D44555E6C95B5F2A72C0C193C6110C0221A448D0C9A0D8E36A84D5C61285128845215F8F8821C308E368283D8E2B42989C04A8B51354E09A38775020189010680840800297C31282442326D008D1F2351A89FFD7C16087F8B130F04418C0A1C082FC005843F5B42CADD9455ADBD328C13219110DE100D988737BBB44C414210118C673B0C1BDF76C499226F78FF41A0AF7AFD3308AAA0AAA22B1C70003F542A66FD1F1CF9D4578315F8C1C6FEC3EDB9B322CB204821A94A248414CE030020F207BF040A06A3DF993DEA3823423F405294A52014565100E0A7211342DF02958046899EEBE6E491299A09312778193FEBD7FFABA8000; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h2C05EF54A3C0F7F5F017E03F5800377CCF6E493C84E8F56441831087370A084801DEC1A54696B9912E8B0705C8587D4F7D36C8638947A620554CC77819B55B7A12D552A8A0496EFE3AAC6F34739A94E798101823148D811212E9A349CC219049527CCD419525AD29AB7D372C0B56AA0A065F8BDC905346478059EC82801920687FF29C990C9E66273CC78041192D03081CC62A8A0D8CB4D9CF2F2558131A78B8A807C3A1110211AFCA2A142F0BA928156D142250438143D339E4E2079F298493C08C4847914664518E27EF7EB9C870A226AFC35BEDB651840466400D4B3C0F877740114D6B08228BCC693FB12CECCCD2461586069445ACFC910B1241434622B6; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h5FFE6AD3343986C4103935236B6E6E11B940EF46A8FC06E6872A6929D50DCDB75621E625522D34519BF2C353F8AA030B9109C2F9686AD3AF57AF3016D9160354C0BED5FBD379F904A41BAFB6BE4EE9F208058229DD0C354F034A6C4D8B6C16A29F0120108829220B230F44550832C1022530CC13C4C30D8254ECA5200A1941266EE48A1CA6430860DE613153615CAF4C8D191004CE9C6105D8C6795B6484467D21D9DC46029B8376E97F2C7BF8C3A218EE79DDBCF886B2BBDE702F71B38AEC6914E5DCCAFE50CC13922A5B149C598A621F80C24D215291228844E7F33F9763C6639303AE5376F664C7125632C1A280CECD5740C77849D937472B202579964F60; +// synopsys translate_on + +// Location: CLKCTRL_G15 +cycloneive_clkctrl \CLOCK_50~inputclkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\CLOCK_50~input_o }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\CLOCK_50~inputclkctrl_outclk )); +// synopsys translate_off +defparam \CLOCK_50~inputclkctrl .clock_type = "global clock"; +defparam \CLOCK_50~inputclkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N4 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout = \z80_|address_pins_|abus[13]~20_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|address_pins_|abus[13]~20_combout ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder .lut_mask = 16'hFF00; +defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y10_N5 +dffeas \ram0|altsyncram_component|auto_generated|address_reg_a[0] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram0|altsyncram_component|auto_generated|address_reg_a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true"; +defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X23_Y10_N15 +dffeas \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(gnd), + .asdata(\ram0|altsyncram_component|auto_generated|address_reg_a [0]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true"; +defparam \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N14 +cycloneive_lcell_comb \Selector3~0 ( +// Equation(s): +// \Selector3~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [14] & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))) # (!\z80_|address_pins_|DFFE_apin_latch [14] & +// (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0])))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\z80_|address_pins_|DFFE_apin_latch [14]), + .cin(gnd), + .combout(\Selector3~0_combout ), + .cout()); +// synopsys translate_off +defparam \Selector3~0 .lut_mask = 16'hF0B8; +defparam \Selector3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N22 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout = (\z80_|address_pins_|abus[14]~23_combout & (\ExtRamWE~0_combout & (!\z80_|address_pins_|abus[15]~22_combout & \z80_|address_pins_|abus[13]~20_combout ))) + + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\ExtRamWE~0_combout ), + .datac(\z80_|address_pins_|abus[15]~22_combout ), + .datad(\z80_|address_pins_|abus[13]~20_combout ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0 .lut_mask = 16'h0800; +defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y31_N14 +cycloneive_lcell_comb \~GND ( +// Equation(s): +// \~GND~combout = GND + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\~GND~combout ), + .cout()); +// synopsys translate_off +defparam \~GND .lut_mask = 16'h0000; +defparam \~GND .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y30_N24 +cycloneive_lcell_comb \ula_|video_|vram_address[0]~feeder ( +// Equation(s): +// \ula_|video_|vram_address[0]~feeder_combout = \ula_|video_|vga_hc [4] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|vga_hc [4]), + .cin(gnd), + .combout(\ula_|video_|vram_address[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address[0]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|vram_address[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y31_N26 +cycloneive_lcell_comb \ula_|video_|vram_address~0 ( +// Equation(s): +// \ula_|video_|vram_address~0_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [1] $ (\ula_|video_|vga_hc [2])))) + + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|vga_hc [3]), + .datac(\ula_|video_|vga_hc [2]), + .datad(\ula_|video_|vga_hc [0]), + .cin(gnd), + .combout(\ula_|video_|vram_address~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address~0 .lut_mask = 16'h0048; +defparam \ula_|video_|vram_address~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y30_N25 +dffeas \ula_|video_|vram_address[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vram_address[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[0] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y30_N22 +cycloneive_lcell_comb \ula_|video_|vram_address[1]~feeder ( +// Equation(s): +// \ula_|video_|vram_address[1]~feeder_combout = \ula_|video_|vga_hc [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|vga_hc [5]), + .cin(gnd), + .combout(\ula_|video_|vram_address[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address[1]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|vram_address[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y30_N23 +dffeas \ula_|video_|vram_address[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vram_address[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[1] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y30_N20 +cycloneive_lcell_comb \ula_|video_|vram_address[2]~4 ( +// Equation(s): +// \ula_|video_|vram_address[2]~4_combout = !\ula_|video_|vga_hc [6] + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|video_|vga_hc [6]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|video_|vram_address[2]~4_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address[2]~4 .lut_mask = 16'h0F0F; +defparam \ula_|video_|vram_address[2]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y30_N21 +dffeas \ula_|video_|vram_address[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vram_address[2]~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[2] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y30_N30 +cycloneive_lcell_comb \ula_|video_|Add3~0 ( +// Equation(s): +// \ula_|video_|Add3~0_combout = \ula_|video_|vga_hc [6] $ (\ula_|video_|vga_hc [7]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|video_|vga_hc [6]), + .datad(\ula_|video_|vga_hc [7]), + .cin(gnd), + .combout(\ula_|video_|Add3~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Add3~0 .lut_mask = 16'h0FF0; +defparam \ula_|video_|Add3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y30_N31 +dffeas \ula_|video_|vram_address[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Add3~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[3] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y30_N16 +cycloneive_lcell_comb \ula_|video_|Add3~1 ( +// Equation(s): +// \ula_|video_|Add3~1_combout = \ula_|video_|vga_hc [8] $ (((!\ula_|video_|vga_hc [7]) # (!\ula_|video_|vga_hc [6]))) + + .dataa(\ula_|video_|vga_hc [8]), + .datab(gnd), + .datac(\ula_|video_|vga_hc [6]), + .datad(\ula_|video_|vga_hc [7]), + .cin(gnd), + .combout(\ula_|video_|Add3~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Add3~1 .lut_mask = 16'hA555; +defparam \ula_|video_|Add3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y30_N17 +dffeas \ula_|video_|vram_address[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Add3~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[4] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y30_N10 +cycloneive_lcell_comb \ula_|video_|Add4~0 ( +// Equation(s): +// \ula_|video_|Add4~0_combout = (\ula_|video_|vga_vc [0] & (\ula_|video_|vga_vc [1] $ (VCC))) # (!\ula_|video_|vga_vc [0] & (\ula_|video_|vga_vc [1] & VCC)) +// \ula_|video_|Add4~1 = CARRY((\ula_|video_|vga_vc [0] & \ula_|video_|vga_vc [1])) + + .dataa(\ula_|video_|vga_vc [0]), + .datab(\ula_|video_|vga_vc [1]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\ula_|video_|Add4~0_combout ), + .cout(\ula_|video_|Add4~1 )); +// synopsys translate_off +defparam \ula_|video_|Add4~0 .lut_mask = 16'h6688; +defparam \ula_|video_|Add4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y30_N12 +cycloneive_lcell_comb \ula_|video_|Add4~2 ( +// Equation(s): +// \ula_|video_|Add4~2_combout = (\ula_|video_|vga_vc [2] & (\ula_|video_|Add4~1 & VCC)) # (!\ula_|video_|vga_vc [2] & (!\ula_|video_|Add4~1 )) +// \ula_|video_|Add4~3 = CARRY((!\ula_|video_|vga_vc [2] & !\ula_|video_|Add4~1 )) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [2]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~1 ), + .combout(\ula_|video_|Add4~2_combout ), + .cout(\ula_|video_|Add4~3 )); +// synopsys translate_off +defparam \ula_|video_|Add4~2 .lut_mask = 16'hC303; +defparam \ula_|video_|Add4~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y30_N14 +cycloneive_lcell_comb \ula_|video_|Add4~4 ( +// Equation(s): +// \ula_|video_|Add4~4_combout = (\ula_|video_|vga_vc [3] & ((GND) # (!\ula_|video_|Add4~3 ))) # (!\ula_|video_|vga_vc [3] & (\ula_|video_|Add4~3 $ (GND))) +// \ula_|video_|Add4~5 = CARRY((\ula_|video_|vga_vc [3]) # (!\ula_|video_|Add4~3 )) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [3]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~3 ), + .combout(\ula_|video_|Add4~4_combout ), + .cout(\ula_|video_|Add4~5 )); +// synopsys translate_off +defparam \ula_|video_|Add4~4 .lut_mask = 16'h3CCF; +defparam \ula_|video_|Add4~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y30_N16 +cycloneive_lcell_comb \ula_|video_|Add4~6 ( +// Equation(s): +// \ula_|video_|Add4~6_combout = (\ula_|video_|vga_vc [4] & (!\ula_|video_|Add4~5 )) # (!\ula_|video_|vga_vc [4] & ((\ula_|video_|Add4~5 ) # (GND))) +// \ula_|video_|Add4~7 = CARRY((!\ula_|video_|Add4~5 ) # (!\ula_|video_|vga_vc [4])) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [4]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~5 ), + .combout(\ula_|video_|Add4~6_combout ), + .cout(\ula_|video_|Add4~7 )); +// synopsys translate_off +defparam \ula_|video_|Add4~6 .lut_mask = 16'h3C3F; +defparam \ula_|video_|Add4~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X35_Y30_N17 +dffeas \ula_|video_|vram_address[5] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Add4~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [5]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[5] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y30_N18 +cycloneive_lcell_comb \ula_|video_|Add4~8 ( +// Equation(s): +// \ula_|video_|Add4~8_combout = (\ula_|video_|vga_vc [5] & ((GND) # (!\ula_|video_|Add4~7 ))) # (!\ula_|video_|vga_vc [5] & (\ula_|video_|Add4~7 $ (GND))) +// \ula_|video_|Add4~9 = CARRY((\ula_|video_|vga_vc [5]) # (!\ula_|video_|Add4~7 )) + + .dataa(gnd), + .datab(\ula_|video_|vga_vc [5]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~7 ), + .combout(\ula_|video_|Add4~8_combout ), + .cout(\ula_|video_|Add4~9 )); +// synopsys translate_off +defparam \ula_|video_|Add4~8 .lut_mask = 16'h3CCF; +defparam \ula_|video_|Add4~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X35_Y30_N19 +dffeas \ula_|video_|vram_address[6] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Add4~8_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [6]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[6] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y30_N20 +cycloneive_lcell_comb \ula_|video_|Add4~10 ( +// Equation(s): +// \ula_|video_|Add4~10_combout = (\ula_|video_|vga_vc [6] & (!\ula_|video_|Add4~9 )) # (!\ula_|video_|vga_vc [6] & ((\ula_|video_|Add4~9 ) # (GND))) +// \ula_|video_|Add4~11 = CARRY((!\ula_|video_|Add4~9 ) # (!\ula_|video_|vga_vc [6])) + + .dataa(\ula_|video_|vga_vc [6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~9 ), + .combout(\ula_|video_|Add4~10_combout ), + .cout(\ula_|video_|Add4~11 )); +// synopsys translate_off +defparam \ula_|video_|Add4~10 .lut_mask = 16'h5A5F; +defparam \ula_|video_|Add4~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X35_Y30_N21 +dffeas \ula_|video_|vram_address[7] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Add4~10_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [7]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[7] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y30_N22 +cycloneive_lcell_comb \ula_|video_|Add4~12 ( +// Equation(s): +// \ula_|video_|Add4~12_combout = (\ula_|video_|vga_vc [7] & ((GND) # (!\ula_|video_|Add4~11 ))) # (!\ula_|video_|vga_vc [7] & (\ula_|video_|Add4~11 $ (GND))) +// \ula_|video_|Add4~13 = CARRY((\ula_|video_|vga_vc [7]) # (!\ula_|video_|Add4~11 )) + + .dataa(\ula_|video_|vga_vc [7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|video_|Add4~11 ), + .combout(\ula_|video_|Add4~12_combout ), + .cout(\ula_|video_|Add4~13 )); +// synopsys translate_off +defparam \ula_|video_|Add4~12 .lut_mask = 16'h5AAF; +defparam \ula_|video_|Add4~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y30_N26 +cycloneive_lcell_comb \ula_|video_|Selector6~0 ( +// Equation(s): +// \ula_|video_|Selector6~0_combout = (\ula_|video_|vga_hc [2] & ((\ula_|video_|Add4~12_combout ))) # (!\ula_|video_|vga_hc [2] & (\ula_|video_|Add4~0_combout )) + + .dataa(gnd), + .datab(\ula_|video_|vga_hc [2]), + .datac(\ula_|video_|Add4~0_combout ), + .datad(\ula_|video_|Add4~12_combout ), + .cin(gnd), + .combout(\ula_|video_|Selector6~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Selector6~0 .lut_mask = 16'hFC30; +defparam \ula_|video_|Selector6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y31_N16 +cycloneive_lcell_comb \ula_|video_|vram_address[9]~1 ( +// Equation(s): +// \ula_|video_|vram_address[9]~1_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [1] $ (\ula_|video_|vga_hc [2])))) + + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|vga_hc [3]), + .datac(\ula_|video_|vga_hc [2]), + .datad(\ula_|video_|vga_hc [0]), + .cin(gnd), + .combout(\ula_|video_|vram_address[9]~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address[9]~1 .lut_mask = 16'h0048; +defparam \ula_|video_|vram_address[9]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y30_N27 +dffeas \ula_|video_|vram_address[8] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Selector6~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address[9]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [8]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[8] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y30_N24 +cycloneive_lcell_comb \ula_|video_|Add4~14 ( +// Equation(s): +// \ula_|video_|Add4~14_combout = \ula_|video_|Add4~13 $ (!\ula_|video_|vga_vc [8]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|vga_vc [8]), + .cin(\ula_|video_|Add4~13 ), + .combout(\ula_|video_|Add4~14_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Add4~14 .lut_mask = 16'hF00F; +defparam \ula_|video_|Add4~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y30_N12 +cycloneive_lcell_comb \ula_|video_|Selector5~0 ( +// Equation(s): +// \ula_|video_|Selector5~0_combout = (\ula_|video_|vga_hc [2] & ((\ula_|video_|Add4~14_combout ))) # (!\ula_|video_|vga_hc [2] & (\ula_|video_|Add4~2_combout )) + + .dataa(gnd), + .datab(\ula_|video_|vga_hc [2]), + .datac(\ula_|video_|Add4~2_combout ), + .datad(\ula_|video_|Add4~14_combout ), + .cin(gnd), + .combout(\ula_|video_|Selector5~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Selector5~0 .lut_mask = 16'hFC30; +defparam \ula_|video_|Selector5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y30_N13 +dffeas \ula_|video_|vram_address[9] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Selector5~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address[9]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [9]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[9] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y31_N6 +cycloneive_lcell_comb \ula_|video_|vram_address[10]~2 ( +// Equation(s): +// \ula_|video_|vram_address[10]~2_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [1] $ (\ula_|video_|vga_hc [2])))) + + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|vga_hc [3]), + .datac(\ula_|video_|vga_hc [2]), + .datad(\ula_|video_|vga_hc [0]), + .cin(gnd), + .combout(\ula_|video_|vram_address[10]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address[10]~2 .lut_mask = 16'h0048; +defparam \ula_|video_|vram_address[10]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y31_N28 +cycloneive_lcell_comb \ula_|video_|vram_address[10]~3 ( +// Equation(s): +// \ula_|video_|vram_address[10]~3_combout = (\ula_|video_|vram_address[10]~2_combout & (\ula_|video_|vga_hc [1] & (\ula_|video_|Add4~4_combout ))) # (!\ula_|video_|vram_address[10]~2_combout & (((\ula_|video_|vram_address [10])))) + + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|Add4~4_combout ), + .datac(\ula_|video_|vram_address [10]), + .datad(\ula_|video_|vram_address[10]~2_combout ), + .cin(gnd), + .combout(\ula_|video_|vram_address[10]~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|vram_address[10]~3 .lut_mask = 16'h88F0; +defparam \ula_|video_|vram_address[10]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y31_N29 +dffeas \ula_|video_|vram_address[10] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|vram_address[10]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [10]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[10] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y30_N6 +cycloneive_lcell_comb \ula_|video_|Selector3~0 ( +// Equation(s): +// \ula_|video_|Selector3~0_combout = (\ula_|video_|vga_hc [2]) # (\ula_|video_|Add4~12_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|video_|vga_hc [2]), + .datad(\ula_|video_|Add4~12_combout ), + .cin(gnd), + .combout(\ula_|video_|Selector3~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Selector3~0 .lut_mask = 16'hFFF0; +defparam \ula_|video_|Selector3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y30_N7 +dffeas \ula_|video_|vram_address[11] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Selector3~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address[9]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [11]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[11] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y30_N8 +cycloneive_lcell_comb \ula_|video_|Selector2~0 ( +// Equation(s): +// \ula_|video_|Selector2~0_combout = (\ula_|video_|vga_hc [2]) # (\ula_|video_|Add4~14_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|video_|vga_hc [2]), + .datad(\ula_|video_|Add4~14_combout ), + .cin(gnd), + .combout(\ula_|video_|Selector2~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Selector2~0 .lut_mask = 16'hFFF0; +defparam \ula_|video_|Selector2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y30_N9 +dffeas \ula_|video_|vram_address[12] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|Selector2~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|vram_address[9]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|vram_address [12]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|vram_address[12] .is_wysiwyg = "true"; +defparam \ula_|video_|vram_address[12] .power_up = "low"; +// synopsys translate_on + +// Location: M9K_X33_Y26_N0 cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a9 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), @@ -41568,7 +40392,7 @@ cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a9 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[1]~34_combout }), + .portadatain({\D[1]~32_combout }), .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , \z80_|address_pins_|abus[0]~16_combout }), @@ -41625,125 +40449,26 @@ defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 204 defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: M9K_X33_Y32_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a9 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), - .portbdataout()); +// Location: LCCOMB_X29_Y11_N10 +cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1 ( +// Equation(s): +// \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout = (\z80_|address_pins_|abus[14]~23_combout & (\ExtRamWE~0_combout & (!\z80_|address_pins_|abus[15]~22_combout & !\z80_|address_pins_|abus[13]~20_combout ))) + + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\ExtRamWE~0_combout ), + .datac(\z80_|address_pins_|abus[15]~22_combout ), + .datad(\z80_|address_pins_|abus[13]~20_combout ), + .cin(gnd), + .combout(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ), + .cout()); // synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h420000004200000000000000000080000000000000000000000000000030004480000000424202423E1E3E02304C3C0C3C7E7E40403E427E3402421824347C1C0400280000003C3406303220344C403C0400100010100000005062742400000091991809FB3BD9084A1241F5015988B3C506031934089E0E1FA8043DDAF2CC07D94A6F2B1D133C211222B22C787D430E45D4C53282288077DFC0F704AAD55127A2BEAEA114958D2817AB1213183A4E1A15E3690A08A33B429284A202011A1243D49CACA1C0A441405A720D21A0921294045F746229E287B95E956AA3DE0CA3B7A019C8039C4DDA6BC99371248CC6008A54CB84503442C4F91309238ECB252072; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h81F3167814687CBD683E54D44555E6C95B5F2A72C0C193C6110C0221A448D0C9A0D8E36A84D5C61285128845215F8F8821C308E368283D8E2B42989C04A8B51354E09A38775020189010680840800297C31282442326D008D1F2351A89FFD7C16087F8B130F04418C0A1C082FC005843F5B42CADD9455ADBD328C13219110DE100D988737BBB44C414210118C673B0C1BDF76C499226F78FF41A0AF7AFD3308AAA0AAA22B1C70003F542A66FD1F1CF9D4578315F8C1C6FEC3EDB9B322CB204821A94A248414CE030020F207BF040A06A3DF993DEA3823423F405294A52014565100E0A7211342DF02958046899EEBE6E491299A09312778193FEBD7FFABA8000; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h2C05EF54A3C0F7F5F017E03F5800377CCF6E493C84E8F56441831087370A084801DEC1A54696B9912E8B0705C8587D4F7D36C8638947A620554CC77819B55B7A12D552A8A0496EFE3AAC6F34739A94E798101823148D811212E9A349CC219049527CCD419525AD29AB7D372C0B56AA0A065F8BDC905346478059EC82801920687FF29C990C9E66273CC78041192D03081CC62A8A0D8CB4D9CF2F2558131A78B8A807C3A1110211AFCA2A142F0BA928156D142250438143D339E4E2079F298493C08C4847914664518E27EF7EB9C870A226AFC35BEDB651840466400D4B3C0F877740114D6B08228BCC693FB12CECCCD2461586069445ACFC910B1241434622B6; -defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h5FFE6AD3343986C4103935236B6E6E11B940EF46A8FC06E6872A6929D50DCDB75621E625522D34519BF2C353F8AA030B9109C2F9686AD3AF57AF3016D9160354C0BED5FBD379F904A41BAFB6BE4EE9F208058229DD0C354F034A6C4D8B6C16A29F0120108829220B230F44550832C1022530CC13C4C30D8254ECA5200A1941266EE48A1CA6430860DE613153615CAF4C8D191004CE9C6105D8C6795B6484467D21D9DC46029B8376E97F2C7BF8C3A218EE79DDBCF886B2BBDE702F71B38AEC6914E5DCCAFE50CC13922A5B149C598A621F80C24D215291228844E7F33F9763C6639303AE5376F664C7125632C1A280CECD5740C77849D937472B202579964F60; +defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1 .lut_mask = 16'h0008; +defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: M9K_X33_Y21_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a1 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h35C65240B61076066A23CE4CFC5E76063A1C2AE07DF555007338BDC080EA0C23082C891C76A4845096304A0D8502080C1198911998821D09C29CA830C337499236E0548D65FF9125A765F0220F6EB9D1B318244CC6CA2CBC9CEC6979C14EB28DE2E0440C6CBD61341FC178649A852D4A2A0627C688D905B882524E191E7951EAEF30312A73337CBAD4838F42A3293859CD169240D8E652F6D72D8D19D56DD7675939FC47C933E1B0AEF12A484454C247B00A6BEC5402AA08B5106E3065602454C80CEC08A7F5F85CE65326632B4C4F3920019A35AE2AEB321131046EE45B81D4EFD5995634050D4CFEC166B032B6415553AF0358304080D9DD0A2E5948593830; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h376E511217E00B624A46BA2E4CC10B729C326F710F24CFE78C5E63F3024B17CC5E1380C938A0A16C9B696272DE7A2948BE8AFE81310146B8AAE5E549FA27EFBE27929938B8E10530250877A4998D0DF0004852125C20CA8D4279881E41208B14198817644F293AC1946061117122A39D8841818C1389D51BDAC549181902516571163594CEC5863F0F56625E221D6B8180848C6B2BE24AA0AEEE5D187201CAAE6AA394A8644314895565192AE415630A42894D6EF21343903B348EED8642F2310644C9567C0BF9911B870B989C59330089AA4C8065AB1B11132213EE0FD830817DE6C2ED45D76325CA2A8E198859334553AB02945CAB1F17C142288008073004; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h20721F982534A8179F13E2C6328CDE7D2A73087D3A9314419022103DFF7677769FE2D1F27443253D58403577C801AE23371F00290A17E1C4A40258BFD204230EE9969472A81B83113144528F831AA6C3221E137C1E9C670E26809A894013828D9E2DBCBF62498A769893D7218899245CD18AE49F0146517422EE475D520029ED39BCEF6BF4D23532957455F1C80115524179D59C4C4534DF7296991146CE24508366123AA809AB30B47977571C5D70397A93C723106D0A2C254714359DC7C9E13AE624C94932927924D20024CD638A05C8620023319662D80E05805625BC4A4006C78011F78D8B82E59F0CD4B32D6801669BE3EB0B96960DFF152005EC7C16CB; -defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h9C8CA06AA05B63C89A59A3E4E80807B27A70B0006624C4AC4A0595CCD8CA20824CA272352720BCD900A6D79BFD9D0595EC0D044ABC8CC28E9AE946E3D2000A4EFA4F91915C6AC9D8570C292F10848189906127BCBE06FFE92DAFB4AAFB240D88DDBB7B207EFA1709B05E1C4801BD45625A36BB62220506E171891964A31BED2215408676F600F490FAA59B488C7998CC8CCC28922AC62644EEBB432EEECB51B16CDEE7468681D6C31E4991CA3736E9ACB7531EC6D8BBCD453718101EA25D79278C6AC955A8A6140421573E413CF5A80AA1436D8B4C31A2AB26D2A61CE834248BAD5751BD429B4F61318427560CE39D49299002165212181064E24FF0093B997B; -// synopsys translate_on - -// Location: M9K_X33_Y22_N0 +// Location: M9K_X33_Y30_N0 cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a1 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), @@ -41757,7 +40482,7 @@ cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a1 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[1]~34_combout }), + .portadatain({\D[1]~32_combout }), .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , \z80_|address_pins_|abus[0]~16_combout }), @@ -41813,2095 +40538,104 @@ defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 204 defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'hCB9C84F288C855028DE04086AC0122869175A48288D30882FFFFFFFCC0000002CB9C80B78DD447828DE440828C0126829175840280D10B82FFFFFFFDE0408082C8D480838FD45582881C4482840160028179800280510B82C0000001BFFFFFFE8AD480BA8F844182880860828601660A8179900280510B02800000009FBF7F7C8B90A1328C8401828BE0608A86836E1281791012805107029FBF7F7D800000008B9883228C9405828BE0728286832E0281799042C0500F43BFFFFFFF80000000889081128FD400828A0066828782288281199002C0401F03A0408083FFFFFFFF888881128FE440828800268287D22CE280199022A0003F00E0408080FFFFFFFF; // synopsys translate_on -// Location: LCCOMB_X32_Y18_N0 +// Location: LCCOMB_X30_Y10_N20 cycloneive_lcell_comb \Selector1~0 ( // Equation(s): -// \Selector1~0_combout = (\z80_|address_pins_|abus[14]~23_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout )))) # (!\z80_|address_pins_|abus[14]~23_combout -// & (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ))) +// \Selector1~0_combout = (\z80_|address_pins_|abus[14]~23_combout & ((\Selector3~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout )) # (!\Selector3~0_combout & +// ((\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ))))) # (!\z80_|address_pins_|abus[14]~23_combout & (\Selector3~0_combout )) .dataa(\z80_|address_pins_|abus[14]~23_combout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ), + .datab(\Selector3~0_combout ), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout ), .datad(\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ), .cin(gnd), .combout(\Selector1~0_combout ), .cout()); // synopsys translate_off -defparam \Selector1~0 .lut_mask = 16'hBA98; +defparam \Selector1~0 .lut_mask = 16'hE6C4; defparam \Selector1~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y18_N2 +// Location: LCCOMB_X30_Y10_N22 cycloneive_lcell_comb \Selector1~1 ( // Equation(s): -// \Selector1~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Selector1~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout )) # (!\Selector1~0_combout & -// ((\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Selector1~0_combout )))) +// \Selector1~1_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\Selector1~0_combout )))) # (!\z80_|address_pins_|abus[14]~23_combout & ((\Selector1~0_combout & ((\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ))) # +// (!\Selector1~0_combout & (\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout )))) - .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ), .datac(\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ), .datad(\Selector1~0_combout ), .cin(gnd), .combout(\Selector1~1_combout ), .cout()); // synopsys translate_off -defparam \Selector1~1 .lut_mask = 16'hBBC0; +defparam \Selector1~1 .lut_mask = 16'hFA44; defparam \Selector1~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y18_N12 -cycloneive_lcell_comb \D[1]~103 ( +// Location: LCCOMB_X31_Y10_N28 +cycloneive_lcell_comb \D[1]~81 ( // Equation(s): -// \D[1]~103_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [15] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\Selector1~1_combout -// ))))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout )))) +// \D[1]~81_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\Selector1~1_combout ))) +// # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout )))) - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .dataa(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ), .datab(\z80_|address_pins_|DFFE_apin_latch [15]), - .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .datad(\Selector1~1_combout ), .cin(gnd), - .combout(\D[1]~103_combout ), + .combout(\D[1]~81_combout ), .cout()); // synopsys translate_off -defparam \D[1]~103 .lut_mask = 16'hF2D0; -defparam \D[1]~103 .sum_lutc_input = "datac"; +defparam \D[1]~81 .lut_mask = 16'hBA8A; +defparam \D[1]~81 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: IOIBUF_X18_Y34_N1 -cycloneive_io_ibuf \PS2_DAT~input ( - .i(PS2_DAT), - .ibar(gnd), - .o(\PS2_DAT~input_o )); -// synopsys translate_off -defparam \PS2_DAT~input .bus_hold = "false"; -defparam \PS2_DAT~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: CLKCTRL_G5 -cycloneive_clkctrl \reset~clkctrl ( - .ena(vcc), - .inclk({vcc,vcc,vcc,\reset~combout }), - .clkselect(2'b00), - .devclrn(devclrn), - .devpor(devpor), - .outclk(\reset~clkctrl_outclk )); -// synopsys translate_off -defparam \reset~clkctrl .clock_type = "global clock"; -defparam \reset~clkctrl .ena_register_mode = "none"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y21_N2 -cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|bit_count~0_combout = (!\ula_|ps2_keyboard_|bit_count [0] & (((!\ula_|ps2_keyboard_|bit_count [1] & !\ula_|ps2_keyboard_|bit_count [2])) # (!\ula_|ps2_keyboard_|bit_count [3]))) - - .dataa(\ula_|ps2_keyboard_|bit_count [1]), - .datab(\ula_|ps2_keyboard_|bit_count [3]), - .datac(\ula_|ps2_keyboard_|bit_count [0]), - .datad(\ula_|ps2_keyboard_|bit_count [2]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|bit_count~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count~0 .lut_mask = 16'h0307; -defparam \ula_|ps2_keyboard_|bit_count~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: IOIBUF_X9_Y34_N8 -cycloneive_io_ibuf \PS2_CLK~input ( - .i(PS2_CLK), - .ibar(gnd), - .o(\PS2_CLK~input_o )); -// synopsys translate_off -defparam \PS2_CLK~input .bus_hold = "false"; -defparam \PS2_CLK~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N0 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[7]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[7]~feeder_combout = \PS2_CLK~input_o - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\PS2_CLK~input_o ), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[7]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[7]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y26_N1 -dffeas \ula_|ps2_keyboard_|clk_filter[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[7] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N6 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[6]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[6]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [7] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [7]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[6]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[6]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y26_N7 -dffeas \ula_|ps2_keyboard_|clk_filter[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[6] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N20 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[5]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[5]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [6] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [6]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[5]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[5]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y26_N21 -dffeas \ula_|ps2_keyboard_|clk_filter[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[5] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N18 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[4]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[4]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [5] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [5]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[4]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[4]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y26_N19 -dffeas \ula_|ps2_keyboard_|clk_filter[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[4] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N12 -cycloneive_lcell_comb \ula_|ps2_keyboard_|Equal0~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|Equal0~0_combout = (!\ula_|ps2_keyboard_|clk_filter [6] & (!\ula_|ps2_keyboard_|clk_filter [7] & (!\ula_|ps2_keyboard_|clk_filter [5] & !\ula_|ps2_keyboard_|clk_filter [4]))) - - .dataa(\ula_|ps2_keyboard_|clk_filter [6]), - .datab(\ula_|ps2_keyboard_|clk_filter [7]), - .datac(\ula_|ps2_keyboard_|clk_filter [5]), - .datad(\ula_|ps2_keyboard_|clk_filter [4]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|Equal0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|Equal0~0 .lut_mask = 16'h0001; -defparam \ula_|ps2_keyboard_|Equal0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N2 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[3]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[3]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [4] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [4]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[3]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[3]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[3]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y26_N3 -dffeas \ula_|ps2_keyboard_|clk_filter[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[3]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[3] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N28 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[2]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[2]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [3] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [3]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[2]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y26_N29 -dffeas \ula_|ps2_keyboard_|clk_filter[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[2] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N22 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[1]~feeder ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[1]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [2] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|clk_filter [2]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[1]~feeder .lut_mask = 16'hFF00; -defparam \ula_|ps2_keyboard_|clk_filter[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y26_N23 -dffeas \ula_|ps2_keyboard_|clk_filter[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[1] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N16 -cycloneive_lcell_comb \ula_|ps2_keyboard_|Equal0~1 ( -// Equation(s): -// \ula_|ps2_keyboard_|Equal0~1_combout = (\ula_|ps2_keyboard_|Equal0~0_combout & (!\ula_|ps2_keyboard_|clk_filter [2] & (!\ula_|ps2_keyboard_|clk_filter [1] & !\ula_|ps2_keyboard_|clk_filter [3]))) - - .dataa(\ula_|ps2_keyboard_|Equal0~0_combout ), - .datab(\ula_|ps2_keyboard_|clk_filter [2]), - .datac(\ula_|ps2_keyboard_|clk_filter [1]), - .datad(\ula_|ps2_keyboard_|clk_filter [3]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|Equal0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|Equal0~1 .lut_mask = 16'h0002; -defparam \ula_|ps2_keyboard_|Equal0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N10 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[0]~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_filter[0]~0_combout = !\ula_|ps2_keyboard_|clk_filter [1] - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|clk_filter [1]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_filter[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[0]~0 .lut_mask = 16'h0F0F; -defparam \ula_|ps2_keyboard_|clk_filter[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y26_N11 -dffeas \ula_|ps2_keyboard_|clk_filter[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_filter[0]~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_filter [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_filter[0] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_filter[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N26 -cycloneive_lcell_comb \ula_|ps2_keyboard_|ps2_clk_in~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|ps2_clk_in~0_combout = (\ula_|ps2_keyboard_|Equal0~1_combout & ((\ula_|ps2_keyboard_|clk_filter [0]))) # (!\ula_|ps2_keyboard_|Equal0~1_combout & (\ula_|ps2_keyboard_|ps2_clk_in~q )) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|Equal0~1_combout ), - .datac(\ula_|ps2_keyboard_|ps2_clk_in~q ), - .datad(\ula_|ps2_keyboard_|clk_filter [0]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|ps2_clk_in~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|ps2_clk_in~0 .lut_mask = 16'hFC30; -defparam \ula_|ps2_keyboard_|ps2_clk_in~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y26_N27 -dffeas \ula_|ps2_keyboard_|ps2_clk_in ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|ps2_clk_in~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|ps2_clk_in~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|ps2_clk_in .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|ps2_clk_in .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X20_Y26_N4 -cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_edge~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|clk_edge~0_combout = (\ula_|ps2_keyboard_|Equal0~1_combout & (!\ula_|ps2_keyboard_|ps2_clk_in~q & \ula_|ps2_keyboard_|clk_filter [0])) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|Equal0~1_combout ), - .datac(\ula_|ps2_keyboard_|ps2_clk_in~q ), - .datad(\ula_|ps2_keyboard_|clk_filter [0]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|clk_edge~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_edge~0 .lut_mask = 16'h0C00; -defparam \ula_|ps2_keyboard_|clk_edge~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X20_Y26_N5 -dffeas \ula_|ps2_keyboard_|clk_edge ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|clk_edge~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|clk_edge~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|clk_edge .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|clk_edge .power_up = "low"; -// synopsys translate_on - -// Location: FF_X26_Y21_N3 -dffeas \ula_|ps2_keyboard_|bit_count[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|bit_count~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|ps2_keyboard_|clk_edge~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|bit_count [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count[0] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|bit_count[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y21_N0 -cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~1 ( -// Equation(s): -// \ula_|ps2_keyboard_|bit_count~1_combout = (!\ula_|ps2_keyboard_|bit_count [3] & (\ula_|ps2_keyboard_|bit_count [2] $ (((\ula_|ps2_keyboard_|bit_count [1] & \ula_|ps2_keyboard_|bit_count [0]))))) - - .dataa(\ula_|ps2_keyboard_|bit_count [1]), - .datab(\ula_|ps2_keyboard_|bit_count [3]), - .datac(\ula_|ps2_keyboard_|bit_count [2]), - .datad(\ula_|ps2_keyboard_|bit_count [0]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|bit_count~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count~1 .lut_mask = 16'h1230; -defparam \ula_|ps2_keyboard_|bit_count~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y21_N1 -dffeas \ula_|ps2_keyboard_|bit_count[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|bit_count~1_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|ps2_keyboard_|clk_edge~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|bit_count [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count[2] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|bit_count[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y21_N16 -cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~3 ( -// Equation(s): -// \ula_|ps2_keyboard_|bit_count~3_combout = (\ula_|ps2_keyboard_|bit_count [1] & (\ula_|ps2_keyboard_|bit_count [2] & (!\ula_|ps2_keyboard_|bit_count [3] & \ula_|ps2_keyboard_|bit_count [0]))) # (!\ula_|ps2_keyboard_|bit_count [1] & -// (!\ula_|ps2_keyboard_|bit_count [2] & (\ula_|ps2_keyboard_|bit_count [3]))) - - .dataa(\ula_|ps2_keyboard_|bit_count [1]), - .datab(\ula_|ps2_keyboard_|bit_count [2]), - .datac(\ula_|ps2_keyboard_|bit_count [3]), - .datad(\ula_|ps2_keyboard_|bit_count [0]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|bit_count~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count~3 .lut_mask = 16'h1810; -defparam \ula_|ps2_keyboard_|bit_count~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y21_N17 -dffeas \ula_|ps2_keyboard_|bit_count[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|bit_count~3_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|ps2_keyboard_|clk_edge~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|bit_count [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count[3] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|bit_count[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y21_N26 -cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~2 ( -// Equation(s): -// \ula_|ps2_keyboard_|bit_count~2_combout = (\ula_|ps2_keyboard_|bit_count [3] & (!\ula_|ps2_keyboard_|bit_count [2] & (!\ula_|ps2_keyboard_|bit_count [1] & \ula_|ps2_keyboard_|bit_count [0]))) # (!\ula_|ps2_keyboard_|bit_count [3] & -// ((\ula_|ps2_keyboard_|bit_count [1] $ (\ula_|ps2_keyboard_|bit_count [0])))) - - .dataa(\ula_|ps2_keyboard_|bit_count [3]), - .datab(\ula_|ps2_keyboard_|bit_count [2]), - .datac(\ula_|ps2_keyboard_|bit_count [1]), - .datad(\ula_|ps2_keyboard_|bit_count [0]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|bit_count~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count~2 .lut_mask = 16'h0750; -defparam \ula_|ps2_keyboard_|bit_count~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y21_N27 -dffeas \ula_|ps2_keyboard_|bit_count[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|bit_count~2_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|ps2_keyboard_|clk_edge~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|bit_count [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|bit_count[1] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|bit_count[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y21_N22 -cycloneive_lcell_comb \ula_|ps2_keyboard_|always1~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|always1~0_combout = (!\ula_|ps2_keyboard_|bit_count [1] & (!\ula_|ps2_keyboard_|bit_count [3] & (!\PS2_DAT~input_o & !\ula_|ps2_keyboard_|bit_count [2]))) - - .dataa(\ula_|ps2_keyboard_|bit_count [1]), - .datab(\ula_|ps2_keyboard_|bit_count [3]), - .datac(\PS2_DAT~input_o ), - .datad(\ula_|ps2_keyboard_|bit_count [2]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|always1~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|always1~0 .lut_mask = 16'h0001; -defparam \ula_|ps2_keyboard_|always1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y21_N12 -cycloneive_lcell_comb \ula_|ps2_keyboard_|LessThan0~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|LessThan0~0_combout = (\ula_|ps2_keyboard_|bit_count [3] & ((\ula_|ps2_keyboard_|bit_count [1]) # (\ula_|ps2_keyboard_|bit_count [2]))) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|bit_count [3]), - .datac(\ula_|ps2_keyboard_|bit_count [1]), - .datad(\ula_|ps2_keyboard_|bit_count [2]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|LessThan0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|LessThan0~0 .lut_mask = 16'hCCC0; -defparam \ula_|ps2_keyboard_|LessThan0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y21_N6 -cycloneive_lcell_comb \ula_|ps2_keyboard_|shiftreg[0]~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|shiftreg[0]~0_combout = (\ula_|ps2_keyboard_|clk_edge~q & (!\ula_|ps2_keyboard_|LessThan0~0_combout & ((\ula_|ps2_keyboard_|bit_count [0]) # (!\ula_|ps2_keyboard_|always1~0_combout )))) - - .dataa(\ula_|ps2_keyboard_|always1~0_combout ), - .datab(\ula_|ps2_keyboard_|bit_count [0]), - .datac(\ula_|ps2_keyboard_|clk_edge~q ), - .datad(\ula_|ps2_keyboard_|LessThan0~0_combout ), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[0]~0 .lut_mask = 16'h00D0; -defparam \ula_|ps2_keyboard_|shiftreg[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y21_N9 -dffeas \ula_|ps2_keyboard_|shiftreg[8] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\PS2_DAT~input_o ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [8]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[8] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[8] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y21_N15 -dffeas \ula_|ps2_keyboard_|shiftreg[7] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [8]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [7]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[7] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y21_N5 -dffeas \ula_|ps2_keyboard_|shiftreg[6] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [7]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [6]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[6] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y21_N11 -dffeas \ula_|ps2_keyboard_|shiftreg[5] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [6]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [5]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[5] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y21_N11 -dffeas \ula_|ps2_keyboard_|shiftreg[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [5]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[4] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X28_Y21_N25 -dffeas \ula_|ps2_keyboard_|shiftreg[3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [4]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[3] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y21_N29 -dffeas \ula_|ps2_keyboard_|shiftreg[2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [3]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[2] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y21_N1 -dffeas \ula_|ps2_keyboard_|shiftreg[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [2]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[1] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X29_Y21_N17 -dffeas \ula_|ps2_keyboard_|shiftreg[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|ps2_keyboard_|shiftreg [1]), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|shiftreg [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|shiftreg[0] .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|shiftreg[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~0 ( -// Equation(s): -// \ula_|zx_keyboard_|Equal0~0_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [7] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [5]), - .datab(\ula_|ps2_keyboard_|shiftreg [7]), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|Equal0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|Equal0~0 .lut_mask = 16'h0008; -defparam \ula_|zx_keyboard_|Equal0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~1 ( -// Equation(s): -// \ula_|zx_keyboard_|Equal0~1_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|Equal0~0_combout & !\ula_|ps2_keyboard_|shiftreg [1]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|zx_keyboard_|Equal0~0_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|Equal0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|Equal0~1 .lut_mask = 16'h0020; -defparam \ula_|zx_keyboard_|Equal0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|extended~0 ( -// Equation(s): -// \ula_|zx_keyboard_|extended~0_combout = (\ula_|zx_keyboard_|Equal0~1_combout & ((\ula_|zx_keyboard_|extended~q ) # (!\ula_|ps2_keyboard_|shiftreg [4]))) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [4]), - .datac(\ula_|zx_keyboard_|extended~q ), - .datad(\ula_|zx_keyboard_|Equal0~1_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|extended~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|extended~0 .lut_mask = 16'hF300; -defparam \ula_|zx_keyboard_|extended~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y21_N8 -cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~1 ( -// Equation(s): -// \ula_|ps2_keyboard_|WideXor0~1_combout = \ula_|ps2_keyboard_|shiftreg [6] $ (\ula_|ps2_keyboard_|shiftreg [7] $ (\ula_|ps2_keyboard_|shiftreg [8] $ (\ula_|ps2_keyboard_|shiftreg [5]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|ps2_keyboard_|shiftreg [7]), - .datac(\ula_|ps2_keyboard_|shiftreg [8]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|WideXor0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|WideXor0~1 .lut_mask = 16'h6996; -defparam \ula_|ps2_keyboard_|WideXor0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y21_N0 -cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|WideXor0~0_combout = \ula_|ps2_keyboard_|shiftreg [2] $ (\ula_|ps2_keyboard_|shiftreg [0] $ (\ula_|ps2_keyboard_|shiftreg [1] $ (\ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|WideXor0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|WideXor0~0 .lut_mask = 16'h6996; -defparam \ula_|ps2_keyboard_|WideXor0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y21_N6 -cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~2 ( -// Equation(s): -// \ula_|ps2_keyboard_|WideXor0~2_combout = \ula_|ps2_keyboard_|shiftreg [4] $ (\ula_|ps2_keyboard_|WideXor0~1_combout $ (\ula_|ps2_keyboard_|WideXor0~0_combout )) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [4]), - .datac(\ula_|ps2_keyboard_|WideXor0~1_combout ), - .datad(\ula_|ps2_keyboard_|WideXor0~0_combout ), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|WideXor0~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|WideXor0~2 .lut_mask = 16'hC33C; -defparam \ula_|ps2_keyboard_|WideXor0~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X26_Y21_N8 -cycloneive_lcell_comb \ula_|ps2_keyboard_|scan_code_ready~0 ( -// Equation(s): -// \ula_|ps2_keyboard_|scan_code_ready~0_combout = (\ula_|ps2_keyboard_|LessThan0~0_combout & (\PS2_DAT~input_o & (\ula_|ps2_keyboard_|clk_edge~q & \ula_|ps2_keyboard_|WideXor0~2_combout ))) - - .dataa(\ula_|ps2_keyboard_|LessThan0~0_combout ), - .datab(\PS2_DAT~input_o ), - .datac(\ula_|ps2_keyboard_|clk_edge~q ), - .datad(\ula_|ps2_keyboard_|WideXor0~2_combout ), - .cin(gnd), - .combout(\ula_|ps2_keyboard_|scan_code_ready~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|scan_code_ready~0 .lut_mask = 16'h8000; -defparam \ula_|ps2_keyboard_|scan_code_ready~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X26_Y21_N9 -dffeas \ula_|ps2_keyboard_|scan_code_ready ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|ps2_keyboard_|scan_code_ready~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|ps2_keyboard_|scan_code_ready~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|ps2_keyboard_|scan_code_ready .is_wysiwyg = "true"; -defparam \ula_|ps2_keyboard_|scan_code_ready .power_up = "low"; -// synopsys translate_on - -// Location: FF_X27_Y20_N1 -dffeas \ula_|zx_keyboard_|extended ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|extended~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|ps2_keyboard_|scan_code_ready~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|extended~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|extended .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|extended .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y21_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~15 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][0]~15_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (!\ula_|zx_keyboard_|Equal0~1_combout & !\ula_|ps2_keyboard_|shiftreg [7])) - - .dataa(\ula_|ps2_keyboard_|scan_code_ready~q ), - .datab(\ula_|zx_keyboard_|Equal0~1_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [7]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][0]~15 .lut_mask = 16'h0202; -defparam \ula_|zx_keyboard_|keys[0][0]~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~36 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][1]~36_combout = (!\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[0][0]~15_combout )) - - .dataa(\ula_|zx_keyboard_|extended~q ), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][1]~36_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1]~36 .lut_mask = 16'h0500; -defparam \ula_|zx_keyboard_|keys[5][1]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~37 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][1]~37_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[5][1]~36_combout & \ula_|ps2_keyboard_|shiftreg [2])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[5][1]~36_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][1]~37_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1]~37 .lut_mask = 16'hA000; -defparam \ula_|zx_keyboard_|keys[5][1]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~0 ( -// Equation(s): -// \ula_|zx_keyboard_|shifted~0_combout = (\ula_|zx_keyboard_|keys[0][0]~15_combout & (!\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|zx_keyboard_|extended~q )) - - .dataa(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|zx_keyboard_|extended~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|shifted~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|shifted~0 .lut_mask = 16'h000A; -defparam \ula_|zx_keyboard_|shifted~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y21_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|released~0 ( -// Equation(s): -// \ula_|zx_keyboard_|released~0_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (\ula_|zx_keyboard_|Equal0~1_combout & ((\ula_|ps2_keyboard_|shiftreg [4]) # (\ula_|zx_keyboard_|released~q )))) # (!\ula_|ps2_keyboard_|scan_code_ready~q & -// (((\ula_|zx_keyboard_|released~q )))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|zx_keyboard_|Equal0~1_combout ), - .datac(\ula_|zx_keyboard_|released~q ), - .datad(\ula_|ps2_keyboard_|scan_code_ready~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|released~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|released~0 .lut_mask = 16'hC8F0; -defparam \ula_|zx_keyboard_|released~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y21_N19 -dffeas \ula_|zx_keyboard_|released ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|released~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|released~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|released .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|released .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr17~0 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr17~0_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [0]))) # (!\ula_|ps2_keyboard_|shiftreg [1] & -// (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [0]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr17~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr17~0 .lut_mask = 16'h4002; -defparam \ula_|zx_keyboard_|WideOr17~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~2 ( -// Equation(s): -// \ula_|zx_keyboard_|shifted~2_combout = (\ula_|zx_keyboard_|WideOr17~0_combout & (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [4])) - - .dataa(\ula_|zx_keyboard_|WideOr17~0_combout ), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|shifted~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|shifted~2 .lut_mask = 16'h0A00; -defparam \ula_|zx_keyboard_|shifted~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~3 ( -// Equation(s): -// \ula_|zx_keyboard_|shifted~3_combout = (\ula_|zx_keyboard_|shifted~0_combout & ((\ula_|zx_keyboard_|shifted~2_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|shifted~2_combout & ((\ula_|zx_keyboard_|shifted~q ))))) # -// (!\ula_|zx_keyboard_|shifted~0_combout & (((\ula_|zx_keyboard_|shifted~q )))) - - .dataa(\ula_|zx_keyboard_|shifted~0_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|shifted~q ), - .datad(\ula_|zx_keyboard_|shifted~2_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|shifted~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|shifted~3 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|shifted~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y21_N3 -dffeas \ula_|zx_keyboard_|shifted ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|shifted~3_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|shifted~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|shifted .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|shifted .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~35 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][1]~35_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [3])) - - .dataa(\ula_|zx_keyboard_|shifted~q ), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(gnd), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][1]~35_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1]~35 .lut_mask = 16'hFF88; -defparam \ula_|zx_keyboard_|keys[5][1]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~38 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][1]~38_combout = (!\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [0])) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][1]~38_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1]~38 .lut_mask = 16'h0003; -defparam \ula_|zx_keyboard_|keys[5][1]~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~39 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][1]~39_combout = (\ula_|zx_keyboard_|keys[5][1]~37_combout & ((\ula_|zx_keyboard_|keys[5][1]~38_combout & (!\ula_|zx_keyboard_|keys[5][1]~35_combout )) # (!\ula_|zx_keyboard_|keys[5][1]~38_combout & -// ((\ula_|zx_keyboard_|keys[5][1]~q ))))) # (!\ula_|zx_keyboard_|keys[5][1]~37_combout & (((\ula_|zx_keyboard_|keys[5][1]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[5][1]~37_combout ), - .datab(\ula_|zx_keyboard_|keys[5][1]~35_combout ), - .datac(\ula_|zx_keyboard_|keys[5][1]~q ), - .datad(\ula_|zx_keyboard_|keys[5][1]~38_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][1]~39_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1]~39 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[5][1]~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y18_N19 -dffeas \ula_|zx_keyboard_|keys[5][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[5][1]~39_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[5][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[5][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][1]~31 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][1]~31_combout = (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [0]) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][1]~31_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][1]~31 .lut_mask = 16'h00CC; -defparam \ula_|zx_keyboard_|keys[4][1]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y21_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~23 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][1]~23_combout = (!\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [7] & \ula_|ps2_keyboard_|scan_code_ready~q )) - - .dataa(\ula_|zx_keyboard_|extended~q ), - .datab(\ula_|ps2_keyboard_|shiftreg [7]), - .datac(\ula_|ps2_keyboard_|scan_code_ready~q ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][1]~23_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][1]~23 .lut_mask = 16'h1010; -defparam \ula_|zx_keyboard_|keys[7][1]~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y21_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~32 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~32_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [4])) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~32_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~32 .lut_mask = 16'h000C; -defparam \ula_|zx_keyboard_|keys[7][2]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y21_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~33 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][2]~33_combout = (\ula_|zx_keyboard_|keys[7][1]~23_combout & (\ula_|zx_keyboard_|keys[7][2]~32_combout & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|zx_keyboard_|keys[7][1]~23_combout ), - .datab(\ula_|zx_keyboard_|keys[7][2]~32_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][2]~33_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][2]~33 .lut_mask = 16'h0080; -defparam \ula_|zx_keyboard_|keys[5][2]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][1]~34 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][1]~34_combout = (\ula_|zx_keyboard_|keys[4][1]~31_combout & ((\ula_|zx_keyboard_|keys[5][2]~33_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[5][2]~33_combout & (\ula_|zx_keyboard_|keys[4][1]~q -// )))) # (!\ula_|zx_keyboard_|keys[4][1]~31_combout & (((\ula_|zx_keyboard_|keys[4][1]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[4][1]~31_combout ), - .datab(\ula_|zx_keyboard_|keys[5][2]~33_combout ), - .datac(\ula_|zx_keyboard_|keys[4][1]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][1]~34_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][1]~34 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[4][1]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y18_N9 -dffeas \ula_|zx_keyboard_|keys[4][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[4][1]~34_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[4][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[4][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N24 -cycloneive_lcell_comb \D[1]~30 ( -// Equation(s): -// \D[1]~30_combout = (\z80_|address_pins_|abus[13]~20_combout & (((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][1]~q )))) # (!\z80_|address_pins_|abus[13]~20_combout & (!\ula_|zx_keyboard_|keys[5][1]~q & -// ((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][1]~q )))) - - .dataa(\z80_|address_pins_|abus[13]~20_combout ), - .datab(\ula_|zx_keyboard_|keys[5][1]~q ), - .datac(\ula_|zx_keyboard_|keys[4][1]~q ), - .datad(\z80_|address_pins_|abus[12]~21_combout ), - .cin(gnd), - .combout(\D[1]~30_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~30 .lut_mask = 16'hBB0B; -defparam \D[1]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~24 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][4]~24_combout = (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [2]) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][4]~24_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][4]~24 .lut_mask = 16'hA0A0; -defparam \ula_|zx_keyboard_|keys[5][4]~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~28 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][1]~28_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[7][1]~23_combout & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[5][4]~24_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|zx_keyboard_|keys[7][1]~23_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|zx_keyboard_|keys[5][4]~24_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][1]~28_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][1]~28 .lut_mask = 16'h0400; -defparam \ula_|zx_keyboard_|keys[3][1]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~29 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][1]~29_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [0])) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][1]~29_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][1]~29 .lut_mask = 16'h00C0; -defparam \ula_|zx_keyboard_|keys[3][1]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~30 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][1]~30_combout = (\ula_|zx_keyboard_|keys[3][1]~28_combout & ((\ula_|zx_keyboard_|keys[3][1]~29_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][1]~29_combout & ((\ula_|zx_keyboard_|keys[3][1]~q -// ))))) # (!\ula_|zx_keyboard_|keys[3][1]~28_combout & (((\ula_|zx_keyboard_|keys[3][1]~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[3][1]~28_combout ), - .datac(\ula_|zx_keyboard_|keys[3][1]~q ), - .datad(\ula_|zx_keyboard_|keys[3][1]~29_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][1]~30_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][1]~30 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[3][1]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y18_N17 -dffeas \ula_|zx_keyboard_|keys[3][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[3][1]~30_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[3][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[3][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][4]~25 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][4]~25_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[5][4]~24_combout & (\ula_|zx_keyboard_|keys[7][1]~23_combout & !\ula_|ps2_keyboard_|shiftreg [1]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|zx_keyboard_|keys[5][4]~24_combout ), - .datac(\ula_|zx_keyboard_|keys[7][1]~23_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][4]~25_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][4]~25 .lut_mask = 16'h0040; -defparam \ula_|zx_keyboard_|keys[1][4]~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][1]~26 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][1]~26_combout = (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|zx_keyboard_|keys[1][4]~25_combout & \ula_|ps2_keyboard_|shiftreg [0])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [5]), - .datab(\ula_|zx_keyboard_|keys[1][4]~25_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][1]~26_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][1]~26 .lut_mask = 16'h4040; -defparam \ula_|zx_keyboard_|keys[2][1]~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][1]~27 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][1]~27_combout = (\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[2][1]~26_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[2][1]~26_combout & ((\ula_|zx_keyboard_|keys[2][1]~q ))))) # -// (!\ula_|ps2_keyboard_|shiftreg [3] & (((\ula_|zx_keyboard_|keys[2][1]~q )))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[2][1]~q ), - .datad(\ula_|zx_keyboard_|keys[2][1]~26_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][1]~27_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][1]~27 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[2][1]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y20_N17 -dffeas \ula_|zx_keyboard_|keys[2][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[2][1]~27_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[2][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[2][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~0 ( -// Equation(s): -// \ula_|zx_keyboard_|key_row~0_combout = ((\z80_|address_pins_|DFFE_apin_latch [10]) # (!\ula_|zx_keyboard_|keys[2][1]~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [10]), - .datad(\ula_|zx_keyboard_|keys[2][1]~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|key_row~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|key_row~0 .lut_mask = 16'hF3FF; -defparam \ula_|zx_keyboard_|key_row~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~14 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][1]~14_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & !\ula_|ps2_keyboard_|shiftreg [4])) - - .dataa(gnd), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|shifted~q ), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][1]~14_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][1]~14 .lut_mask = 16'hCCCF; -defparam \ula_|zx_keyboard_|keys[0][1]~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~16 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][1]~16_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [4] $ (\ula_|ps2_keyboard_|shiftreg [2])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][1]~16_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][1]~16 .lut_mask = 16'h0060; -defparam \ula_|zx_keyboard_|keys[0][1]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~17 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][1]~17_combout = (\ula_|zx_keyboard_|keys[0][1]~16_combout & ((\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [4])) # (!\ula_|ps2_keyboard_|shiftreg [1] & -// (\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [4])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|zx_keyboard_|keys[0][1]~16_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][1]~17_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][1]~17 .lut_mask = 16'h2040; -defparam \ula_|zx_keyboard_|keys[0][1]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~18 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][1]~18_combout = (\ula_|zx_keyboard_|shifted~0_combout & ((\ula_|zx_keyboard_|keys[0][1]~17_combout & (!\ula_|zx_keyboard_|keys[0][1]~14_combout )) # (!\ula_|zx_keyboard_|keys[0][1]~17_combout & -// ((\ula_|zx_keyboard_|keys[0][1]~q ))))) # (!\ula_|zx_keyboard_|shifted~0_combout & (((\ula_|zx_keyboard_|keys[0][1]~q )))) - - .dataa(\ula_|zx_keyboard_|shifted~0_combout ), - .datab(\ula_|zx_keyboard_|keys[0][1]~14_combout ), - .datac(\ula_|zx_keyboard_|keys[0][1]~q ), - .datad(\ula_|zx_keyboard_|keys[0][1]~17_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][1]~18_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][1]~18 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[0][1]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y21_N7 -dffeas \ula_|zx_keyboard_|keys[0][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[0][1]~18_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[0][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[0][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~19 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][4]~19_combout = (!\ula_|ps2_keyboard_|shiftreg [7] & (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|zx_keyboard_|extended~q & \ula_|ps2_keyboard_|scan_code_ready~q ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [7]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|zx_keyboard_|extended~q ), - .datad(\ula_|ps2_keyboard_|scan_code_ready~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][4]~19_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][4]~19 .lut_mask = 16'h0100; -defparam \ula_|zx_keyboard_|keys[7][4]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~20 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][4]~20_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [2]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [0]), - .datab(\ula_|ps2_keyboard_|shiftreg [4]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][4]~20_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][4]~20 .lut_mask = 16'h0080; -defparam \ula_|zx_keyboard_|keys[6][4]~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][1]~21 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][1]~21_combout = (\ula_|zx_keyboard_|keys[7][4]~19_combout & (\ula_|zx_keyboard_|keys[6][4]~20_combout & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|zx_keyboard_|keys[7][4]~19_combout ), - .datab(\ula_|zx_keyboard_|keys[6][4]~20_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][1]~21_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][1]~21 .lut_mask = 16'h0800; -defparam \ula_|zx_keyboard_|keys[1][1]~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][1]~22 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][1]~22_combout = (\ula_|zx_keyboard_|keys[1][1]~21_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[1][1]~21_combout & (\ula_|zx_keyboard_|keys[1][1]~q )) - - .dataa(gnd), - .datab(\ula_|zx_keyboard_|keys[1][1]~21_combout ), - .datac(\ula_|zx_keyboard_|keys[1][1]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][1]~22_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][1]~22 .lut_mask = 16'h30FC; -defparam \ula_|zx_keyboard_|keys[1][1]~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y20_N13 -dffeas \ula_|zx_keyboard_|keys[1][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[1][1]~22_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[1][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[1][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N2 -cycloneive_lcell_comb \D[1]~28 ( -// Equation(s): -// \D[1]~28_combout = (\ula_|zx_keyboard_|keys[0][1]~q & (\z80_|address_pins_|abus[8]~18_combout & ((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][1]~q )))) # (!\ula_|zx_keyboard_|keys[0][1]~q & -// (((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][1]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[0][1]~q ), - .datab(\z80_|address_pins_|abus[8]~18_combout ), - .datac(\z80_|address_pins_|abus[9]~17_combout ), - .datad(\ula_|zx_keyboard_|keys[1][1]~q ), - .cin(gnd), - .combout(\D[1]~28_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~28 .lut_mask = 16'hD0DD; -defparam \D[1]~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N26 -cycloneive_lcell_comb \D[1]~29 ( -// Equation(s): -// \D[1]~29_combout = (\ula_|zx_keyboard_|key_row~0_combout & (\D[1]~28_combout & ((\z80_|address_pins_|abus[11]~19_combout ) # (!\ula_|zx_keyboard_|keys[3][1]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[3][1]~q ), - .datab(\ula_|zx_keyboard_|key_row~0_combout ), - .datac(\z80_|address_pins_|abus[11]~19_combout ), - .datad(\D[1]~28_combout ), - .cin(gnd), - .combout(\D[1]~29_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~29 .lut_mask = 16'hC400; -defparam \D[1]~29 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~41 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][1]~41_combout = (!\ula_|zx_keyboard_|extended~q & (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[0][0]~15_combout ))) - - .dataa(\ula_|zx_keyboard_|extended~q ), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][1]~41_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1]~41 .lut_mask = 16'h0400; -defparam \ula_|zx_keyboard_|keys[6][1]~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~42 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][1]~42_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [3]))) # (!\ula_|ps2_keyboard_|shiftreg [1] & -// (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][1]~42_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1]~42 .lut_mask = 16'h0240; -defparam \ula_|zx_keyboard_|keys[6][1]~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~43 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][1]~43_combout = (\ula_|zx_keyboard_|keys[6][1]~41_combout & (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|zx_keyboard_|keys[6][1]~42_combout )) - - .dataa(\ula_|zx_keyboard_|keys[6][1]~41_combout ), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|zx_keyboard_|keys[6][1]~42_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][1]~43_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1]~43 .lut_mask = 16'hA000; -defparam \ula_|zx_keyboard_|keys[6][1]~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~40 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][1]~40_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [2] & \ula_|zx_keyboard_|shifted~q )) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|zx_keyboard_|shifted~q ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][1]~40_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1]~40 .lut_mask = 16'hEAEA; -defparam \ula_|zx_keyboard_|keys[6][1]~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~44 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][1]~44_combout = (\ula_|zx_keyboard_|keys[6][1]~43_combout & ((!\ula_|zx_keyboard_|keys[6][1]~40_combout ))) # (!\ula_|zx_keyboard_|keys[6][1]~43_combout & (\ula_|zx_keyboard_|keys[6][1]~q )) - - .dataa(\ula_|zx_keyboard_|keys[6][1]~43_combout ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[6][1]~q ), - .datad(\ula_|zx_keyboard_|keys[6][1]~40_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][1]~44_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1]~44 .lut_mask = 16'h50FA; -defparam \ula_|zx_keyboard_|keys[6][1]~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y20_N25 -dffeas \ula_|zx_keyboard_|keys[6][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[6][1]~44_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[6][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[6][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y21_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~45 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][1]~45_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (!\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [7]))) - - .dataa(\ula_|ps2_keyboard_|scan_code_ready~q ), - .datab(\ula_|zx_keyboard_|extended~q ), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|ps2_keyboard_|shiftreg [7]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][1]~45_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][1]~45 .lut_mask = 16'h0002; -defparam \ula_|zx_keyboard_|keys[7][1]~45 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~5 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~5_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (((!\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [1])))) # (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & -// ((\ula_|ps2_keyboard_|shiftreg [2]) # (\ula_|ps2_keyboard_|shiftreg [1])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~5_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~5 .lut_mask = 16'h0A38; -defparam \ula_|zx_keyboard_|WideOr16~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~2 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~2_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~2 .lut_mask = 16'h0044; -defparam \ula_|zx_keyboard_|WideOr16~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~4 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~4_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1])) # (!\ula_|ps2_keyboard_|shiftreg [2] & -// (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [1])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~4_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~4 .lut_mask = 16'h0140; -defparam \ula_|zx_keyboard_|WideOr16~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~7 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~7_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (((\ula_|zx_keyboard_|WideOr16~4_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|WideOr16~2_combout & (!\ula_|ps2_keyboard_|shiftreg [2]))) - - .dataa(\ula_|zx_keyboard_|WideOr16~2_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|zx_keyboard_|WideOr16~4_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~7_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~7 .lut_mask = 16'hF022; -defparam \ula_|zx_keyboard_|WideOr16~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~6 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~6_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (((\ula_|zx_keyboard_|WideOr16~7_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|WideOr16~5_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|zx_keyboard_|WideOr16~5_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|WideOr16~7_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~6_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~6 .lut_mask = 16'hF808; -defparam \ula_|zx_keyboard_|WideOr16~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y21_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~46 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][1]~46_combout = (\ula_|zx_keyboard_|keys[7][1]~45_combout & ((\ula_|zx_keyboard_|WideOr16~6_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|WideOr16~6_combout & ((\ula_|zx_keyboard_|keys[7][1]~q ))))) # -// (!\ula_|zx_keyboard_|keys[7][1]~45_combout & (((\ula_|zx_keyboard_|keys[7][1]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[7][1]~45_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[7][1]~q ), - .datad(\ula_|zx_keyboard_|WideOr16~6_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][1]~46_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][1]~46 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[7][1]~46 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y21_N31 -dffeas \ula_|zx_keyboard_|keys[7][1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[7][1]~46_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[7][1]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][1] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[7][1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N20 +// Location: LCCOMB_X31_Y10_N20 cycloneive_lcell_comb \D[1]~31 ( // Equation(s): -// \D[1]~31_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\z80_|address_pins_|abus[15]~22_combout ) # (!\ula_|zx_keyboard_|keys[7][1]~q )))) # (!\z80_|address_pins_|abus[14]~23_combout & (!\ula_|zx_keyboard_|keys[6][1]~q & -// ((\z80_|address_pins_|abus[15]~22_combout ) # (!\ula_|zx_keyboard_|keys[7][1]~q )))) +// \D[1]~31_combout = ((\Equal2~0_combout & (\D[1]~30_combout )) # (!\Equal2~0_combout & ((\D[1]~81_combout )))) # (!\Equal2~1_combout ) - .dataa(\z80_|address_pins_|abus[14]~23_combout ), - .datab(\ula_|zx_keyboard_|keys[6][1]~q ), - .datac(\z80_|address_pins_|abus[15]~22_combout ), - .datad(\ula_|zx_keyboard_|keys[7][1]~q ), + .dataa(\Equal2~1_combout ), + .datab(\Equal2~0_combout ), + .datac(\D[1]~30_combout ), + .datad(\D[1]~81_combout ), .cin(gnd), .combout(\D[1]~31_combout ), .cout()); // synopsys translate_off -defparam \D[1]~31 .lut_mask = 16'hB0BB; +defparam \D[1]~31 .lut_mask = 16'hF7D5; defparam \D[1]~31 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y20_N18 +// Location: LCCOMB_X31_Y10_N2 cycloneive_lcell_comb \D[1]~32 ( // Equation(s): -// \D[1]~32_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[1]~30_combout & (\D[1]~29_combout & \D[1]~31_combout ))) +// \D[1]~32_combout = (\z80_|pin_control_|bus_db_pin_oe~15_combout & (((\z80_|data_pins_|dout [1] & \D[1]~31_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout & (((\D[1]~31_combout )) # (!\Equal2~1_combout ))) - .dataa(\D[1]~30_combout ), - .datab(\z80_|address_pins_|abus[0]~16_combout ), - .datac(\D[1]~29_combout ), + .dataa(\Equal2~1_combout ), + .datab(\z80_|data_pins_|dout [1]), + .datac(\z80_|pin_control_|bus_db_pin_oe~15_combout ), .datad(\D[1]~31_combout ), .cin(gnd), .combout(\D[1]~32_combout ), .cout()); // synopsys translate_off -defparam \D[1]~32 .lut_mask = 16'hECCC; +defparam \D[1]~32 .lut_mask = 16'hCF05; defparam \D[1]~32 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y22_N4 -cycloneive_lcell_comb \D[1]~33 ( -// Equation(s): -// \D[1]~33_combout = ((\Equal2~0_combout & ((\D[1]~32_combout ))) # (!\Equal2~0_combout & (\D[1]~103_combout ))) # (!\Equal2~1_combout ) - - .dataa(\Equal2~0_combout ), - .datab(\Equal2~1_combout ), - .datac(\D[1]~103_combout ), - .datad(\D[1]~32_combout ), - .cin(gnd), - .combout(\D[1]~33_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~33 .lut_mask = 16'hFB73; -defparam \D[1]~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y22_N8 -cycloneive_lcell_comb \D[1]~34 ( -// Equation(s): -// \D[1]~34_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\D[1]~33_combout & \z80_|data_pins_|dout [1])))) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\D[1]~33_combout )) # (!\Equal2~1_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datab(\Equal2~1_combout ), - .datac(\D[1]~33_combout ), - .datad(\z80_|data_pins_|dout [1]), - .cin(gnd), - .combout(\D[1]~34_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~34 .lut_mask = 16'hF151; -defparam \D[1]~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N18 +// Location: LCCOMB_X30_Y13_N14 cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] ( // Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [1] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[1]~11_combout ) # ((\z80_|pin_control_|bus_db_pin_re~combout & \D[1]~34_combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & -// (((\z80_|pin_control_|bus_db_pin_re~combout & \D[1]~34_combout )))) +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [1] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[1]~11_combout ) # ((\D[1]~32_combout & \z80_|pin_control_|bus_db_pin_re~combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & +// (((\D[1]~32_combout & \z80_|pin_control_|bus_db_pin_re~combout )))) .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), .datab(\z80_|bus_control_|db[1]~11_combout ), - .datac(\z80_|pin_control_|bus_db_pin_re~combout ), - .datad(\D[1]~34_combout ), + .datac(\D[1]~32_combout ), + .datad(\z80_|pin_control_|bus_db_pin_re~combout ), .cin(gnd), .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [1]), .cout()); @@ -43910,7 +40644,42 @@ defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] .lut_mask = 16'hF888; defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y13_N19 +// Location: LCCOMB_X28_Y12_N16 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_re~2 ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_re~2_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (((\z80_|execute_|fIORead~3_combout & \z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M1_ff~q ))) # (!\z80_|sequencer_|DFFE_T2_ff~q & +// (\z80_|execute_|fIORead~3_combout & ((\z80_|sequencer_|DFFE_T3_ff~q )))) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(\z80_|execute_|fIORead~3_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_re~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_re~2 .lut_mask = 16'hCE0A; +defparam \z80_|pin_control_|bus_db_pin_re~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N8 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_2 ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_2~combout = (\z80_|execute_|ctl_bus_db_we~7_combout ) # ((\z80_|pin_control_|bus_db_pin_re~2_combout ) # ((\z80_|execute_|fMRead~36_combout & \z80_|sequencer_|DFFE_T2_ff~q ))) + + .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datab(\z80_|execute_|fMRead~36_combout ), + .datac(\z80_|sequencer_|DFFE_T2_ff~q ), + .datad(\z80_|pin_control_|bus_db_pin_re~2_combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_2 .lut_mask = 16'hFFEA; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y13_N15 dffeas \z80_|data_pins_|dout[1] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [1]), @@ -43929,61 +40698,27 @@ defparam \z80_|data_pins_|dout[1] .is_wysiwyg = "true"; defparam \z80_|data_pins_|dout[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N30 -cycloneive_lcell_comb \z80_|bus_control_|db[1]~10 ( -// Equation(s): -// \z80_|bus_control_|db[1]~10_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[1]~26_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) - - .dataa(gnd), - .datab(\z80_|alu_control_|db[1]~26_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|bus_control_|db[0]~4_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[1]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[1]~10 .lut_mask = 16'hCF00; -defparam \z80_|bus_control_|db[1]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N24 +// Location: LCCOMB_X30_Y13_N28 cycloneive_lcell_comb \z80_|bus_control_|db[1]~11 ( // Equation(s): // \z80_|bus_control_|db[1]~11_combout = ((\z80_|bus_control_|db[1]~10_combout & ((\z80_|data_pins_|dout [1]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - .dataa(\z80_|execute_|ctl_bus_db_oe~combout ), - .datab(\z80_|data_pins_|dout [1]), - .datac(\z80_|bus_control_|db[1]~10_combout ), - .datad(\z80_|bus_control_|db[0]~6_combout ), + .dataa(\z80_|bus_control_|db[0]~6_combout ), + .datab(\z80_|bus_control_|db[1]~10_combout ), + .datac(\z80_|data_pins_|dout [1]), + .datad(\z80_|execute_|ctl_bus_db_oe~combout ), .cin(gnd), .combout(\z80_|bus_control_|db[1]~11_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[1]~11 .lut_mask = 16'hD0FF; +defparam \z80_|bus_control_|db[1]~11 .lut_mask = 16'hD5DD; defparam \z80_|bus_control_|db[1]~11 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N14 -cycloneive_lcell_comb \z80_|ir_|opcode[1]~feeder ( -// Equation(s): -// \z80_|ir_|opcode[1]~feeder_combout = \z80_|bus_control_|db[1]~11_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|bus_control_|db[1]~11_combout ), - .cin(gnd), - .combout(\z80_|ir_|opcode[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|ir_|opcode[1]~feeder .lut_mask = 16'hFF00; -defparam \z80_|ir_|opcode[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y12_N15 +// Location: FF_X30_Y13_N29 dffeas \z80_|ir_|opcode[1] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|ir_|opcode[1]~feeder_combout ), + .d(\z80_|bus_control_|db[1]~11_combout ), .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), @@ -43999,8110 +40734,848 @@ defparam \z80_|ir_|opcode[1] .is_wysiwyg = "true"; defparam \z80_|ir_|opcode[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y13_N18 -cycloneive_lcell_comb \z80_|pla_decode_|Equal40~0 ( +// Location: LCCOMB_X27_Y13_N0 +cycloneive_lcell_comb \z80_|pla_decode_|Equal2~0 ( // Equation(s): -// \z80_|pla_decode_|Equal40~0_combout = (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [1])) +// \z80_|pla_decode_|Equal2~0_combout = (!\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1]) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|ir_|opcode [1]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal2~0 .lut_mask = 16'h3030; +defparam \z80_|pla_decode_|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~15 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~15_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal13~0_combout & \z80_|ir_|opcode [3]))) .dataa(\z80_|ir_|opcode [0]), - .datab(gnd), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal40~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal40~0 .lut_mask = 16'h0005; -defparam \z80_|pla_decode_|Equal40~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N24 -cycloneive_lcell_comb \z80_|pla_decode_|Equal21~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal21~1_combout = (\z80_|pla_decode_|Equal21~0_combout & (\z80_|pla_decode_|Equal40~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal21~0_combout ), - .datab(\z80_|pla_decode_|Equal40~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal21~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal21~1 .lut_mask = 16'h0800; -defparam \z80_|pla_decode_|Equal21~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~26 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~26_combout = (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|pla_decode_|Equal21~1_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T4_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(\z80_|sequencer_|DFFE_M3_ff~q ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~26 .lut_mask = 16'hC080; -defparam \z80_|execute_|ctl_alu_op_low~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~28 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~28_combout = (\z80_|execute_|ctl_alu_op_low~26_combout ) # ((\z80_|execute_|ctl_alu_op_low~23_combout ) # ((\z80_|execute_|ctl_alu_op_low~34_combout ) # (\z80_|execute_|ctl_alu_op_low~27_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~26_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~23_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~34_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~28 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_alu_op_low~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~3 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~3_combout = (\z80_|execute_|ctl_alu_op_low~28_combout & (\z80_|pla_decode_|Equal64~0_combout & ((\z80_|pla_decode_|Equal9~0_combout ) # (\z80_|pla_decode_|Equal3~0_combout )))) - - .dataa(\z80_|execute_|ctl_alu_op_low~28_combout ), - .datab(\z80_|pla_decode_|Equal9~0_combout ), - .datac(\z80_|pla_decode_|Equal64~0_combout ), - .datad(\z80_|pla_decode_|Equal3~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~3 .lut_mask = 16'hA080; -defparam \z80_|execute_|ctl_flags_cf_cpl~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~2 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~2_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ) # ((\z80_|execute_|ctl_mRead~36_combout & ((\z80_|execute_|ixy_d~6_combout ) # (\z80_|execute_|ctl_mRead~11_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~36_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|execute_|ctl_mRead~11_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~2 .lut_mask = 16'hFFA8; -defparam \z80_|execute_|ctl_flags_cf_cpl~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N20 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout = (!\z80_|execute_|ctl_mWrite~10_combout & (((!\z80_|pla_decode_|Equal61~2_combout & !\z80_|execute_|ctl_mWrite~16_combout )) # (!\z80_|nM1_int~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal61~2_combout ), - .datab(\z80_|execute_|ctl_mWrite~16_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_mWrite~10_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 .lut_mask = 16'h001F; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N2 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout = (\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_state_alu~5_combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|execute_|ctl_mRead~36_combout )))) # (!\z80_|pla_decode_|Equal56~0_combout & -// (((!\z80_|nM1_int~2_combout )) # (!\z80_|execute_|ctl_mRead~36_combout ))) - - .dataa(\z80_|pla_decode_|Equal56~0_combout ), - .datab(\z80_|execute_|ctl_mRead~36_combout ), - .datac(\z80_|nM1_int~2_combout ), - .datad(\z80_|execute_|ctl_state_alu~5_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 .lut_mask = 16'h153F; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N28 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout = (\z80_|execute_|ctl_alu_core_R~4_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_R~4_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ), - .datac(\z80_|execute_|ctl_reg_sys_hilo[0]~11_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 .lut_mask = 16'h8000; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y11_N16 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~6_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~5_combout & !\z80_|execute_|ctl_alu_sel_op2_neg~16_combout )) - - .dataa(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ), - .datab(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 .lut_mask = 16'h0088; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y11_N22 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout = (!\z80_|execute_|ctl_alu_core_R~1_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout & (\z80_|execute_|ctl_alu_core_S~7_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ))) - - .dataa(\z80_|execute_|ctl_alu_core_R~1_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ), - .datac(\z80_|execute_|ctl_alu_core_S~7_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 .lut_mask = 16'h4000; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N18 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout & (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout & ((!\z80_|execute_|ctl_alu_op_low~27_combout ) # (!\z80_|execute_|ctl_flags_cf_cpl~2_combout )))) - - .dataa(\z80_|execute_|ctl_flags_cf_cpl~2_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ), - .datac(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ), - .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 .lut_mask = 16'h040C; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y12_N30 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~21 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~21_combout = (((!\z80_|pla_decode_|Equal40~1_combout & !\z80_|pla_decode_|Equal39~0_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|pla_decode_|Equal40~1_combout ), - .datad(\z80_|pla_decode_|Equal39~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~21 .lut_mask = 16'h777F; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N26 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout = (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~21_combout & ((\z80_|execute_|ctl_alu_op_low~23_combout ) # (\z80_|execute_|ctl_alu_op_low~27_combout ))) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_alu_op_low~23_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~21_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 .lut_mask = 16'h0F0C; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y15_N4 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout = (\z80_|pla_decode_|Equal21~1_combout & ((\z80_|execute_|ixy_d~6_combout ) # ((\z80_|sequencer_|DFFE_T5_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_T5_ff~q ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|pla_decode_|Equal21~1_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 .lut_mask = 16'hC0E0; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N28 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout & ((\z80_|execute_|ctl_alu_op_low~23_combout ) # ((\z80_|execute_|ctl_alu_op_low~34_combout ) # (\z80_|execute_|ctl_alu_op_low~27_combout )))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ), - .datab(\z80_|execute_|ctl_alu_op_low~23_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~34_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 .lut_mask = 16'hAAA8; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N0 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout = (\z80_|execute_|ctl_flags_nf_we~1_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout & (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout & !\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ))) - - .dataa(\z80_|execute_|ctl_flags_nf_we~1_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 .lut_mask = 16'h0008; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y11_N22 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~22_combout & (\z80_|execute_|ctl_flags_sz_we~4_combout & ((!\z80_|pla_decode_|Equal9~0_combout ) # (!\z80_|pla_decode_|Equal62~2_combout )))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~22_combout ), - .datab(\z80_|pla_decode_|Equal62~2_combout ), - .datac(\z80_|execute_|ctl_flags_sz_we~4_combout ), - .datad(\z80_|pla_decode_|Equal9~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17 .lut_mask = 16'h20A0; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~32 ( -// Equation(s): -// \z80_|execute_|ctl_alu_op_low~32_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|pla_decode_|Equal10~0_combout )) - - .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(gnd), - .datad(\z80_|pla_decode_|Equal10~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_alu_op_low~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_alu_op_low~32 .lut_mask = 16'h8800; -defparam \z80_|execute_|ctl_alu_op_low~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N18 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|pla_decode_|Equal21~0_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal63~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal21~0_combout ), - .datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|pla_decode_|Equal63~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 .lut_mask = 16'hCECC; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N20 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout = (\z80_|execute_|ctl_alu_op_low~32_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~32_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ), - .datac(\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ), - .datad(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 .lut_mask = 16'hFFEF; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y11_N24 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout = ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ) # ((\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & \z80_|execute_|ctl_alu_op_low~20_combout ))) # (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ) - - .dataa(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~17_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~20_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18 .lut_mask = 16'hFFB3; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N0 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~19 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~19_combout = (\z80_|execute_|ctl_state_alu~12_combout & ((\z80_|ir_|opcode [3] & (\z80_|ir_|opcode [4] & \z80_|ir_|opcode [5])) # (!\z80_|ir_|opcode [3] & ((!\z80_|ir_|opcode [5]))))) - - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|execute_|ctl_state_alu~12_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~19 .lut_mask = 16'h8500; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N10 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~0 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[0]~19_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[7]~21_combout )) - - .dataa(\z80_|alu_|db[7]~21_combout ), - .datab(gnd), - .datac(\z80_|alu_|db[0]~19_combout ), - .datad(\z80_|ir_|opcode [3]), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~0 .lut_mask = 16'hF0AA; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N28 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~1 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_control_|out[6]~2_combout )) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .datab(gnd), - .datac(\z80_|alu_control_|out[6]~2_combout ), - .datad(\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~1 .lut_mask = 16'hFA50; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N18 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~2 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout & ((!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout )))) # (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout -// & ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (!\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ))))) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ), - .datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ), - .datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~2 .lut_mask = 16'h11D8; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N30 -cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~3 ( -// Equation(s): -// \z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout = (\z80_|execute_|ctl_flags_cf2_we~3_combout & (\z80_|execute_|ctl_flags_cf2_sel_daa~combout $ ((!\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout )))) # (!\z80_|execute_|ctl_flags_cf2_we~3_combout & -// ((\z80_|alu_flags_|DFFE_inst_latch_cf2~q ) # ((\z80_|execute_|ctl_flags_cf2_sel_daa~combout & \z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout )))) - - .dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), - .datad(\z80_|execute_|ctl_flags_cf2_we~3_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~3 .lut_mask = 16'h99F8; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y9_N31 -dffeas \z80_|alu_flags_|DFFE_inst_latch_cf2 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2 .is_wysiwyg = "true"; -defparam \z80_|alu_flags_|DFFE_inst_latch_cf2 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~10_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal11~0_combout & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_M1_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|pla_decode_|Equal11~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~10 .lut_mask = 16'h0B00; -defparam \z80_|execute_|ctl_flags_use_cf2~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N6 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~11 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~11_combout = (\z80_|execute_|ctl_flags_use_cf2~10_combout ) # ((\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # ((\z80_|pla_decode_|Equal10~0_combout & \z80_|execute_|ixy_d~7_combout ))) - - .dataa(\z80_|pla_decode_|Equal10~0_combout ), - .datab(\z80_|execute_|ctl_flags_use_cf2~10_combout ), - .datac(\z80_|execute_|ixy_d~7_combout ), - .datad(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~11 .lut_mask = 16'hFFEC; -defparam \z80_|execute_|ctl_flags_use_cf2~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~8_combout = (\z80_|execute_|ctl_ir_we~8_combout ) # ((\z80_|pla_decode_|Equal20~0_combout ) # (\z80_|execute_|ctl_ir_we~14_combout )) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(gnd), - .datac(\z80_|pla_decode_|Equal20~0_combout ), - .datad(\z80_|execute_|ctl_ir_we~14_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~8 .lut_mask = 16'hFFFA; -defparam \z80_|execute_|ctl_flags_use_cf2~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~9_combout = (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_flags_use_cf2~8_combout ) # ((\z80_|pla_decode_|Equal9~0_combout & \z80_|pla_decode_|Equal63~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal9~0_combout ), - .datab(\z80_|pla_decode_|Equal63~0_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|execute_|ctl_flags_use_cf2~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~9 .lut_mask = 16'h0F08; -defparam \z80_|execute_|ctl_flags_use_cf2~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y12_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~12 ( -// Equation(s): -// \z80_|execute_|ctl_flags_use_cf2~12_combout = (\z80_|execute_|ctl_flags_use_cf2~11_combout ) # (((\z80_|execute_|ctl_flags_use_cf2~9_combout ) # (\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout )) # (!\z80_|execute_|ctl_flags_use_cf2~13_combout )) - - .dataa(\z80_|execute_|ctl_flags_use_cf2~11_combout ), - .datab(\z80_|execute_|ctl_flags_use_cf2~13_combout ), - .datac(\z80_|execute_|ctl_flags_use_cf2~9_combout ), - .datad(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_use_cf2~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_use_cf2~12 .lut_mask = 16'hFFFB; -defparam \z80_|execute_|ctl_flags_use_cf2~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X36_Y9_N16 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout = (\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & (((\z80_|alu_flags_|DFFE_inst_latch_cf2~q )))) # (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & ((\z80_|execute_|ctl_flags_use_cf2~12_combout & -// ((\z80_|alu_flags_|DFFE_inst_latch_cf2~q ))) # (!\z80_|execute_|ctl_flags_use_cf2~12_combout & (\z80_|alu_flags_|DFFE_inst_latch_cf~q )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_cf~q ), - .datac(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ), - .datad(\z80_|execute_|ctl_flags_use_cf2~12_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 .lut_mask = 16'hF0E4; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N22 -cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~20 ( -// Equation(s): -// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~20_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~19_combout & \z80_|execute_|ctl_alu_op_low~28_combout ))) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~18_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~19_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~28_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~20 .lut_mask = 16'hFEFA; -defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~10 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~10_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ) # ((!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|execute_|ctl_alu_op_low~12_combout ))) - - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(\z80_|sequencer_|DFFE_M2_ff~q ), - .datac(\z80_|execute_|ctl_alu_op_low~12_combout ), - .datad(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~10 .lut_mask = 16'hFF40; -defparam \z80_|execute_|ctl_flags_cf_cpl~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N30 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~8 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~8_combout = (\z80_|execute_|ctl_flags_cf_cpl~10_combout ) # ((\z80_|execute_|ctl_alu_op_low~12_combout & (\z80_|execute_|ctl_alu_op_low~8_combout & \z80_|execute_|ctl_alu_op_low~19_combout ))) - - .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), - .datab(\z80_|execute_|ctl_flags_cf_cpl~10_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~8_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~8 .lut_mask = 16'hECCC; -defparam \z80_|execute_|ctl_flags_cf_cpl~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~5 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~5_combout = ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_alu_op_low~12_combout ) # (\z80_|execute_|ctl_state_alu~7_combout )))) # (!\z80_|execute_|ctl_state_alu~15_combout ) - - .dataa(\z80_|execute_|ctl_alu_op_low~12_combout ), - .datab(\z80_|execute_|ctl_state_alu~15_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|execute_|ctl_state_alu~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~5 .lut_mask = 16'h3F3B; -defparam \z80_|execute_|ctl_flags_cf_cpl~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y12_N24 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~6 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~6_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_flags_cf_cpl~5_combout ) # ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal68~2_combout )))) - - .dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|pla_decode_|Equal68~2_combout ), - .datad(\z80_|execute_|ctl_flags_cf_cpl~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~6 .lut_mask = 16'hAA20; -defparam \z80_|execute_|ctl_flags_cf_cpl~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N16 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~7 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~7_combout = (\z80_|execute_|ctl_flags_cf_cpl~6_combout ) # ((!\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # (\z80_|execute_|ctl_flags_cf2_sel_daa~combout )))) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ), - .datab(\z80_|alu_flags_|DFFE_inst_latch_nf~q ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datad(\z80_|execute_|ctl_flags_cf_cpl~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~7 .lut_mask = 16'hFF32; -defparam \z80_|execute_|ctl_flags_cf_cpl~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N2 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_set~0 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_set~0_combout = (\z80_|execute_|ctl_state_alu~12_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal9~0_combout ))) - - .dataa(\z80_|execute_|ctl_state_alu~12_combout ), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal9~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_set~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_set~0 .lut_mask = 16'h2000; -defparam \z80_|execute_|ctl_flags_cf_set~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~4 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~4_combout = (\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout & ((\z80_|execute_|ctl_alu_op_low~19_combout ) # (!\z80_|execute_|ctl_alu_op_low~33_combout ))) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ), - .datac(\z80_|execute_|ctl_alu_op_low~19_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~33_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~4 .lut_mask = 16'hC0CC; -defparam \z80_|execute_|ctl_flags_cf_cpl~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y11_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~9 ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf_cpl~9_combout = (\z80_|execute_|ctl_flags_cf_cpl~8_combout ) # ((\z80_|execute_|ctl_flags_cf_cpl~7_combout ) # ((\z80_|execute_|ctl_flags_cf_set~0_combout ) # (\z80_|execute_|ctl_flags_cf_cpl~4_combout ))) - - .dataa(\z80_|execute_|ctl_flags_cf_cpl~8_combout ), - .datab(\z80_|execute_|ctl_flags_cf_cpl~7_combout ), - .datac(\z80_|execute_|ctl_flags_cf_set~0_combout ), - .datad(\z80_|execute_|ctl_flags_cf_cpl~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf_cpl~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf_cpl~9 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_flags_cf_cpl~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y11_N4 -cycloneive_lcell_comb \z80_|alu_flags_|flags_cf ( -// Equation(s): -// \z80_|alu_flags_|flags_cf~combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~20_combout $ (((\z80_|execute_|ctl_flags_cf_cpl~3_combout ) # (\z80_|execute_|ctl_flags_cf_cpl~9_combout ))))) - - .dataa(\z80_|execute_|ctl_flags_cf_cpl~3_combout ), - .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~20_combout ), - .datad(\z80_|execute_|ctl_flags_cf_cpl~9_combout ), - .cin(gnd), - .combout(\z80_|alu_flags_|flags_cf~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_flags_|flags_cf .lut_mask = 16'h0C48; -defparam \z80_|alu_flags_|flags_cf .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N2 -cycloneive_lcell_comb \z80_|alu_control_|db[0]~8 ( -// Equation(s): -// \z80_|alu_control_|db[0]~8_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & (((\z80_|bus_control_|db[0]~17_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) - - .dataa(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .datab(\z80_|execute_|ctl_sw_1d~7_combout ), - .datac(\z80_|bus_control_|db[0]~17_combout ), - .datad(\z80_|execute_|ctl_sw_mask543_en~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[0]~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[0]~8 .lut_mask = 16'h22A2; -defparam \z80_|alu_control_|db[0]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N20 -cycloneive_lcell_comb \z80_|sw2_|db_up[0]~0 ( -// Equation(s): -// \z80_|sw2_|db_up[0]~0_combout = (\z80_|alu_|db[0]~19_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_sw_2u~7_combout ), - .datad(\z80_|alu_|db[0]~19_combout ), - .cin(gnd), - .combout(\z80_|sw2_|db_up[0]~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sw2_|db_up[0]~0 .lut_mask = 16'hFF0F; -defparam \z80_|sw2_|db_up[0]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N4 -cycloneive_lcell_comb \z80_|alu_control_|db[0]~9 ( -// Equation(s): -// \z80_|alu_control_|db[0]~9_combout = (\z80_|alu_control_|db[0]~8_combout & (\z80_|sw2_|db_up[0]~0_combout & ((\z80_|reg_file_|gdfx_temp0[0]~22_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) - - .dataa(\z80_|alu_control_|db[0]~8_combout ), - .datab(\z80_|reg_file_|gdfx_temp0[0]~22_combout ), - .datac(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datad(\z80_|sw2_|db_up[0]~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[0]~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[0]~9 .lut_mask = 16'h8A00; -defparam \z80_|alu_control_|db[0]~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N26 -cycloneive_lcell_comb \z80_|alu_control_|db[0]~12 ( -// Equation(s): -// \z80_|alu_control_|db[0]~12_combout = ((\z80_|alu_control_|db[0]~9_combout & ((\z80_|alu_flags_|flags_cf~combout ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|alu_flags_|flags_cf~combout ), - .datab(\z80_|execute_|ctl_flags_oe~2_combout ), - .datac(\z80_|alu_control_|db[0]~9_combout ), - .datad(\z80_|alu_control_|db[6]~11_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[0]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[0]~12 .lut_mask = 16'hB0FF; -defparam \z80_|alu_control_|db[0]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~67 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][0]~67_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [4])) - - .dataa(\ula_|zx_keyboard_|shifted~q ), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][0]~67_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][0]~67 .lut_mask = 16'hFF50; -defparam \ula_|zx_keyboard_|keys[5][0]~67 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~81 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][0]~81_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [3]))) # (!\ula_|ps2_keyboard_|shiftreg [1] & -// (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][0]~81_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][0]~81 .lut_mask = 16'h0420; -defparam \ula_|zx_keyboard_|keys[5][0]~81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~82 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][0]~82_combout = (\ula_|zx_keyboard_|keys[5][0]~81_combout & (\ula_|zx_keyboard_|keys[6][1]~41_combout & (\ula_|ps2_keyboard_|shiftreg [2] $ (\ula_|ps2_keyboard_|shiftreg [4])))) - - .dataa(\ula_|zx_keyboard_|keys[5][0]~81_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|keys[6][1]~41_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][0]~82_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][0]~82 .lut_mask = 16'h2800; -defparam \ula_|zx_keyboard_|keys[5][0]~82 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~83 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][0]~83_combout = (\ula_|zx_keyboard_|keys[5][0]~82_combout & (!\ula_|zx_keyboard_|keys[5][0]~67_combout )) # (!\ula_|zx_keyboard_|keys[5][0]~82_combout & ((\ula_|zx_keyboard_|keys[5][0]~q ))) - - .dataa(\ula_|zx_keyboard_|keys[5][0]~67_combout ), - .datab(\ula_|zx_keyboard_|keys[5][0]~82_combout ), - .datac(\ula_|zx_keyboard_|keys[5][0]~q ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][0]~83_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][0]~83 .lut_mask = 16'h7474; -defparam \ula_|zx_keyboard_|keys[5][0]~83 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y20_N11 -dffeas \ula_|zx_keyboard_|keys[5][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[5][0]~83_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[5][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[5][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~84 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][0]~84_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [5] $ (\ula_|ps2_keyboard_|shiftreg [3])))) # (!\ula_|ps2_keyboard_|shiftreg [1] & -// (!\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [0]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [5]), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][0]~84_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][0]~84 .lut_mask = 16'h0160; -defparam \ula_|zx_keyboard_|keys[4][0]~84 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~85 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][0]~85_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [3])) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|shifted~q ), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][0]~85_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][0]~85 .lut_mask = 16'hBABA; -defparam \ula_|zx_keyboard_|keys[4][0]~85 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~86 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][0]~86_combout = (\ula_|zx_keyboard_|keys[5][1]~37_combout & ((\ula_|zx_keyboard_|keys[4][0]~84_combout & ((!\ula_|zx_keyboard_|keys[4][0]~85_combout ))) # (!\ula_|zx_keyboard_|keys[4][0]~84_combout & -// (\ula_|zx_keyboard_|keys[4][0]~q )))) # (!\ula_|zx_keyboard_|keys[5][1]~37_combout & (((\ula_|zx_keyboard_|keys[4][0]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[5][1]~37_combout ), - .datab(\ula_|zx_keyboard_|keys[4][0]~84_combout ), - .datac(\ula_|zx_keyboard_|keys[4][0]~q ), - .datad(\ula_|zx_keyboard_|keys[4][0]~85_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][0]~86_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][0]~86 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[4][0]~86 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y18_N27 -dffeas \ula_|zx_keyboard_|keys[4][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[4][0]~86_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[4][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[4][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N20 -cycloneive_lcell_comb \D[0]~49 ( -// Equation(s): -// \D[0]~49_combout = (\z80_|address_pins_|abus[13]~20_combout & (((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][0]~q )))) # (!\z80_|address_pins_|abus[13]~20_combout & (!\ula_|zx_keyboard_|keys[5][0]~q & -// ((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][0]~q )))) - - .dataa(\z80_|address_pins_|abus[13]~20_combout ), - .datab(\ula_|zx_keyboard_|keys[5][0]~q ), - .datac(\ula_|zx_keyboard_|keys[4][0]~q ), - .datad(\z80_|address_pins_|abus[12]~21_combout ), - .cin(gnd), - .combout(\D[0]~49_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~49 .lut_mask = 16'hBB0B; -defparam \D[0]~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr4~0 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr4~0_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [5] & ((\ula_|ps2_keyboard_|shiftreg [6])))) # (!\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [5] & -// (\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [6]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr4~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr4~0 .lut_mask = 16'h8810; -defparam \ula_|zx_keyboard_|WideOr4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys~76 ( -// Equation(s): -// \ula_|zx_keyboard_|keys~76_combout = (!\ula_|zx_keyboard_|extended~q & (((\ula_|ps2_keyboard_|shiftreg [3]) # (!\ula_|zx_keyboard_|keys[4][1]~31_combout )) # (!\ula_|zx_keyboard_|WideOr4~0_combout ))) - - .dataa(\ula_|zx_keyboard_|WideOr4~0_combout ), - .datab(\ula_|zx_keyboard_|extended~q ), - .datac(\ula_|zx_keyboard_|keys[4][1]~31_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys~76_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys~76 .lut_mask = 16'h3313; -defparam \ula_|zx_keyboard_|keys~76 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~73 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~73_combout = (\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [6]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][3]~73_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~73 .lut_mask = 16'hF000; -defparam \ula_|zx_keyboard_|keys[4][3]~73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~47 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][4]~47_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [2])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][4]~47_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][4]~47 .lut_mask = 16'h0808; -defparam \ula_|zx_keyboard_|keys[6][4]~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr0~0 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr0~0_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [2])) # (!\ula_|ps2_keyboard_|shiftreg [1] & -// ((\ula_|ps2_keyboard_|shiftreg [2]))))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [0]), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr0~0 .lut_mask = 16'h0310; -defparam \ula_|zx_keyboard_|WideOr0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys~74 ( -// Equation(s): -// \ula_|zx_keyboard_|keys~74_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (((!\ula_|zx_keyboard_|WideOr0~0_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [4] & (((!\ula_|ps2_keyboard_|shiftreg [3])) # (!\ula_|zx_keyboard_|keys[6][4]~47_combout ))) - - .dataa(\ula_|zx_keyboard_|keys[6][4]~47_combout ), - .datab(\ula_|zx_keyboard_|WideOr0~0_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys~74_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys~74 .lut_mask = 16'h353F; -defparam \ula_|zx_keyboard_|keys~74 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~75 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][0]~75_combout = (\ula_|zx_keyboard_|keys[0][0]~15_combout & (((\ula_|zx_keyboard_|keys[4][3]~73_combout & !\ula_|zx_keyboard_|keys~74_combout )) # (!\ula_|zx_keyboard_|extended~q ))) - - .dataa(\ula_|zx_keyboard_|keys[4][3]~73_combout ), - .datab(\ula_|zx_keyboard_|keys~74_combout ), - .datac(\ula_|zx_keyboard_|extended~q ), - .datad(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][0]~75_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][0]~75 .lut_mask = 16'h2F00; -defparam \ula_|zx_keyboard_|keys[0][0]~75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~77 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][0]~77_combout = (\ula_|zx_keyboard_|keys~76_combout & (((\ula_|zx_keyboard_|keys[0][0]~q )))) # (!\ula_|zx_keyboard_|keys~76_combout & ((\ula_|zx_keyboard_|keys[0][0]~75_combout & ((!\ula_|zx_keyboard_|released~q ))) # -// (!\ula_|zx_keyboard_|keys[0][0]~75_combout & (\ula_|zx_keyboard_|keys[0][0]~q )))) - - .dataa(\ula_|zx_keyboard_|keys~76_combout ), - .datab(\ula_|zx_keyboard_|keys[0][0]~75_combout ), - .datac(\ula_|zx_keyboard_|keys[0][0]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][0]~77_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][0]~77 .lut_mask = 16'hB0F4; -defparam \ula_|zx_keyboard_|keys[0][0]~77 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y20_N15 -dffeas \ula_|zx_keyboard_|keys[0][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[0][0]~77_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[0][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[0][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][0]~71 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][0]~71_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[1][4]~25_combout & !\ula_|ps2_keyboard_|shiftreg [5]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [0]), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|zx_keyboard_|keys[1][4]~25_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][0]~71_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][0]~71 .lut_mask = 16'h0040; -defparam \ula_|zx_keyboard_|keys[1][0]~71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][0]~72 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][0]~72_combout = (\ula_|zx_keyboard_|keys[1][0]~71_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[1][0]~71_combout & (\ula_|zx_keyboard_|keys[1][0]~q )) - - .dataa(gnd), - .datab(\ula_|zx_keyboard_|keys[1][0]~71_combout ), - .datac(\ula_|zx_keyboard_|keys[1][0]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][0]~72_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][0]~72 .lut_mask = 16'h30FC; -defparam \ula_|zx_keyboard_|keys[1][0]~72 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y19_N17 -dffeas \ula_|zx_keyboard_|keys[1][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[1][0]~72_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[1][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[1][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N30 -cycloneive_lcell_comb \D[0]~47 ( -// Equation(s): -// \D[0]~47_combout = (\ula_|zx_keyboard_|keys[0][0]~q & (\z80_|address_pins_|abus[8]~18_combout & ((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][0]~q )))) # (!\ula_|zx_keyboard_|keys[0][0]~q & -// (((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][0]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[0][0]~q ), - .datab(\z80_|address_pins_|abus[8]~18_combout ), - .datac(\z80_|address_pins_|abus[9]~17_combout ), - .datad(\ula_|zx_keyboard_|keys[1][0]~q ), - .cin(gnd), - .combout(\D[0]~47_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~47 .lut_mask = 16'hD0DD; -defparam \D[0]~47 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][0]~80 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][0]~80_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (((\ula_|zx_keyboard_|keys[2][0]~q )))) # (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[2][1]~26_combout & (!\ula_|zx_keyboard_|released~q )) # -// (!\ula_|zx_keyboard_|keys[2][1]~26_combout & ((\ula_|zx_keyboard_|keys[2][0]~q ))))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[2][0]~q ), - .datad(\ula_|zx_keyboard_|keys[2][1]~26_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][0]~80_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][0]~80 .lut_mask = 16'hB1F0; -defparam \ula_|zx_keyboard_|keys[2][0]~80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y20_N23 -dffeas \ula_|zx_keyboard_|keys[2][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[2][0]~80_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[2][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[2][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][0]~78 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][0]~78_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [0])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][0]~78_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][0]~78 .lut_mask = 16'h000A; -defparam \ula_|zx_keyboard_|keys[3][0]~78 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][0]~79 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][0]~79_combout = (\ula_|zx_keyboard_|keys[3][0]~78_combout & ((\ula_|zx_keyboard_|keys[3][1]~28_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[3][1]~28_combout & (\ula_|zx_keyboard_|keys[3][0]~q -// )))) # (!\ula_|zx_keyboard_|keys[3][0]~78_combout & (((\ula_|zx_keyboard_|keys[3][0]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[3][0]~78_combout ), - .datab(\ula_|zx_keyboard_|keys[3][1]~28_combout ), - .datac(\ula_|zx_keyboard_|keys[3][0]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][0]~79_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][0]~79 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[3][0]~79 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y20_N5 -dffeas \ula_|zx_keyboard_|keys[3][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[3][0]~79_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[3][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[3][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~1 ( -// Equation(s): -// \ula_|zx_keyboard_|key_row~1_combout = ((\z80_|address_pins_|DFFE_apin_latch [11]) # (!\ula_|zx_keyboard_|keys[3][0]~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\ula_|zx_keyboard_|keys[3][0]~q ), - .datad(\z80_|address_pins_|DFFE_apin_latch [11]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|key_row~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|key_row~1 .lut_mask = 16'hFF3F; -defparam \ula_|zx_keyboard_|key_row~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N4 -cycloneive_lcell_comb \D[0]~48 ( -// Equation(s): -// \D[0]~48_combout = (\D[0]~47_combout & (\ula_|zx_keyboard_|key_row~1_combout & ((\z80_|address_pins_|abus[10]~24_combout ) # (!\ula_|zx_keyboard_|keys[2][0]~q )))) - - .dataa(\D[0]~47_combout ), - .datab(\z80_|address_pins_|abus[10]~24_combout ), - .datac(\ula_|zx_keyboard_|keys[2][0]~q ), - .datad(\ula_|zx_keyboard_|key_row~1_combout ), - .cin(gnd), - .combout(\D[0]~48_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~48 .lut_mask = 16'h8A00; -defparam \D[0]~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~1 ( -// Equation(s): -// \ula_|zx_keyboard_|shifted~1_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [4]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|shifted~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|shifted~1 .lut_mask = 16'h0F00; -defparam \ula_|zx_keyboard_|shifted~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~90 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][0]~90_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][0]~90_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][0]~90 .lut_mask = 16'h0200; -defparam \ula_|zx_keyboard_|keys[6][0]~90 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~91 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][0]~91_combout = (\ula_|zx_keyboard_|shifted~1_combout & (\ula_|zx_keyboard_|keys[7][1]~23_combout & (\ula_|zx_keyboard_|keys[6][0]~90_combout & \ula_|ps2_keyboard_|shiftreg [1]))) - - .dataa(\ula_|zx_keyboard_|shifted~1_combout ), - .datab(\ula_|zx_keyboard_|keys[7][1]~23_combout ), - .datac(\ula_|zx_keyboard_|keys[6][0]~90_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][0]~91_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][0]~91 .lut_mask = 16'h8000; -defparam \ula_|zx_keyboard_|keys[6][0]~91 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~92 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][0]~92_combout = (\ula_|zx_keyboard_|keys[6][0]~91_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[6][0]~91_combout & ((\ula_|zx_keyboard_|keys[6][0]~q ))) - - .dataa(gnd), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[6][0]~q ), - .datad(\ula_|zx_keyboard_|keys[6][0]~91_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][0]~92_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][0]~92 .lut_mask = 16'h33F0; -defparam \ula_|zx_keyboard_|keys[6][0]~92 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y20_N21 -dffeas \ula_|zx_keyboard_|keys[6][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[6][0]~92_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[6][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[6][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y21_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~63 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][4]~63_combout = (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [0]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][4]~63_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][4]~63 .lut_mask = 16'h0F00; -defparam \ula_|zx_keyboard_|keys[5][4]~63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y21_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~3 ( -// Equation(s): -// \ula_|zx_keyboard_|WideOr16~3_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [2]) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|WideOr16~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|WideOr16~3 .lut_mask = 16'h0303; -defparam \ula_|zx_keyboard_|WideOr16~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y21_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~87 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][0]~87_combout = (\ula_|zx_keyboard_|keys[5][4]~63_combout & (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|WideOr16~3_combout ))) - - .dataa(\ula_|zx_keyboard_|keys[5][4]~63_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|WideOr16~3_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][0]~87_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][0]~87 .lut_mask = 16'h0800; -defparam \ula_|zx_keyboard_|keys[7][0]~87 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~132 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][0]~132_combout = (\ula_|zx_keyboard_|keys[3][0]~78_combout & (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [4]))) - - .dataa(\ula_|zx_keyboard_|keys[3][0]~78_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][0]~132_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][0]~132 .lut_mask = 16'h8000; -defparam \ula_|zx_keyboard_|keys[7][0]~132 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y21_N20 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~88 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][0]~88_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|zx_keyboard_|keys[7][1]~23_combout & ((\ula_|zx_keyboard_|keys[7][0]~87_combout ) # (\ula_|zx_keyboard_|keys[7][0]~132_combout )))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [5]), - .datab(\ula_|zx_keyboard_|keys[7][1]~23_combout ), - .datac(\ula_|zx_keyboard_|keys[7][0]~87_combout ), - .datad(\ula_|zx_keyboard_|keys[7][0]~132_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][0]~88_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][0]~88 .lut_mask = 16'h8880; -defparam \ula_|zx_keyboard_|keys[7][0]~88 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~89 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][0]~89_combout = (\ula_|zx_keyboard_|keys[7][0]~88_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[7][0]~88_combout & (\ula_|zx_keyboard_|keys[7][0]~q )) - - .dataa(\ula_|zx_keyboard_|keys[7][0]~88_combout ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[7][0]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][0]~89_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][0]~89 .lut_mask = 16'h50FA; -defparam \ula_|zx_keyboard_|keys[7][0]~89 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X30_Y20_N7 -dffeas \ula_|zx_keyboard_|keys[7][0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[7][0]~89_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[7][0]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][0] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[7][0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N28 -cycloneive_lcell_comb \D[0]~50 ( -// Equation(s): -// \D[0]~50_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\z80_|address_pins_|abus[15]~22_combout ) # (!\ula_|zx_keyboard_|keys[7][0]~q )))) # (!\z80_|address_pins_|abus[14]~23_combout & (!\ula_|zx_keyboard_|keys[6][0]~q & -// ((\z80_|address_pins_|abus[15]~22_combout ) # (!\ula_|zx_keyboard_|keys[7][0]~q )))) - - .dataa(\z80_|address_pins_|abus[14]~23_combout ), - .datab(\ula_|zx_keyboard_|keys[6][0]~q ), - .datac(\z80_|address_pins_|abus[15]~22_combout ), - .datad(\ula_|zx_keyboard_|keys[7][0]~q ), - .cin(gnd), - .combout(\D[0]~50_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~50 .lut_mask = 16'hB0BB; -defparam \D[0]~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y20_N10 -cycloneive_lcell_comb \D[0]~51 ( -// Equation(s): -// \D[0]~51_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[0]~49_combout & (\D[0]~48_combout & \D[0]~50_combout ))) - - .dataa(\D[0]~49_combout ), - .datab(\z80_|address_pins_|abus[0]~16_combout ), - .datac(\D[0]~48_combout ), - .datad(\D[0]~50_combout ), - .cin(gnd), - .combout(\D[0]~51_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~51 .lut_mask = 16'hECCC; -defparam \D[0]~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y16_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a24 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[0]~58_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_first_bit_number = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y14_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a16 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[0]~58_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_first_bit_number = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y13_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a0 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[0]~58_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081; -// synopsys translate_on - -// Location: LCCOMB_X32_Y14_N14 -cycloneive_lcell_comb \D[0]~55 ( -// Equation(s): -// \D[0]~55_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & -// ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout )) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & -// ((\ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ))))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ), - .cin(gnd), - .combout(\D[0]~55_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~55 .lut_mask = 16'hE3E0; -defparam \D[0]~55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y13_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a8 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[0]~58_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N22 -cycloneive_lcell_comb \D[0]~56 ( -// Equation(s): -// \D[0]~56_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[0]~55_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout )) # (!\D[0]~55_combout & -// ((\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ))))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[0]~55_combout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\D[0]~55_combout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ), - .cin(gnd), - .combout(\D[0]~56_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~56 .lut_mask = 16'hBCB0; -defparam \D[0]~56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y28_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a0 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[0]~58_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_bit_number = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF0000000000000000000000003FF03FFC20107FFC3FF00B9C3FF007FC18000FFC3FF03FD42FF43FFC2FFC3FE01FFE7FE81FFE3FDC07FE3FFC07FE2FFC07FE0F0807FE1F18207F0F3030FD8C30383300600000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h000000000000000000000000FFFFFFFFE0408103E004044390120EAA803920C6000000000000000000000000FFFFFFFFE0408103A004005A84723CEA813930C2000000000000000000000000800000009FBF7EFD8004027A8572358A813950EA000000000000000000000000800000009FBF7EFC8005157A85733F0A8139518E0000000000000000000000009FBF7EFC800000008006113A8C73330A813919EA0000000000000000000000009FBF7EFC8000000080060022801333A2813973EA00000000000000000000000080000000DFFFFFFD9FF6022A84730366801913FE000000000000000000000000E0408102FFFFFFFD9FF60ABA84730426901913EE; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h9FF81326887812F28FF0D7C2CC6856E3894C8B62980099E28988BFC2B9EC79829FE81362887842E68FF0C7C2CCE056E2896C89E2888098E28AA8BBC299FC1AC280081372887842E69EE0C7CA8CE046E289E089E289C899E28AA8BEC2993C1AE28008837E882852C69EE0874288E046E2886099E289689FCE8AD8BFC2999C09F680088376880846C69CA88382880042A289D08DE289F098C28AF8BFC289FC88F280088376880857C29CA893C2888043A289508DE288F0D9428BF0AFC289F4888A800883F2880857829C2891C3889047F2898885E2899081428990AF8289FC8BE3800893F6880847C2DC0894E389944F62888899668918914289803582CB8C8AF3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'hCBAC80F38DA845828DF44582840124029375A4A288D108A2FFFFFFFDE0408082CAEC80968DF855828CE4408284012006917194C280510B82DFFFFFFC8000000288EC84A28FFC4586880C648A860124128179900280510F82800000009FBF7F7C8BA080BA8FEC40828808618286012C028179901280510702800000009FBF7F7C8BB081BA8CAC408289E0618286812C1281791002805007029FBF7F7C8000000089B881828CB440828BE07782868322028139909280400F029FBF7F7D8000000089A4C3928FF444828A00260A8792227281199022A0001F03E0408081FFFFFFFF89A0C1928FD440828800260687B720C280199002E0001F03E0408083FFFFFFFF; -// synopsys translate_on - -// Location: M9K_X22_Y30_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a8 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h3C00000000000000000000000000000000000000000000000000000000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005DB824E17CAAE881C1908A79F24B7D1B4857A981A6AF39DFF5A2FEE9141EB33592D8E9B82471FDDA6791810A1C29D415CC1A8FA03444DF0083F83506BA93E8D1A1856A768D73A08418BFB25A40001DD4833DAF33BD311BB45F39667627407EF59ED569C483EB3BE1B10551B1428A6169579293ED063CAA9C6ADB0433CFC15C33AFF04C710408C20AC28B5909A229CD7D1DB4EB9A44CE0EEDBBBD391D3128AAA3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'hDDE6FC8EBE3F9F3C3DFC6E8F07BFD31D50660B1E0B2506A533CE0E340C7C745CAEC4837C2A5FECBB94C1C969FFDDFF79BFFAAFDCA8D748399ABF75558ADD02F56F6DFFF29CB70FFD25A59DFFFED7B3F7E8B4CE6FFF3EF9CEC6BAE57ABFFFCEE647B2AFF5B87AA26AFFDD317DEDCFBDFFE1A0CAD3B58877DD2F647F7DF748E7CF4693FD3C1238FFAFBD7FDF567FA8FEF024F33AFD3AABC6B105EA80272D64895FFF9FFF6E3881C81AFDCF2257FD4F8ED5257D0E9B800726B6564D2B05012F76DF636CDEB4BDFCAEEFC61DFFEFB7E26262DEF2CB9F71565824FEBF3F7BDDEABB593F1BF746FBFFC353E37263FF38A796EF39E3FD7DFEBA7FFEFFBD97ABAF09E909; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'hE629BDF93D7F5B5BAF92FBAB477E9B315DB5A310CFACC7408DF9A544B1E57AF6EFEF92C2FA4D8D4E4AC86C277338FA37BCDD9D47782DB75EFF80781BCD23D0AFCAE30B9FE6AA29FFF6F72DA73DFE4F7ACD39687B9E69C5359E9B991F0246EFFBC5595561AC64787878F5CE14C664CF9EB0CDAFFBABEF1E83358371B9ED96E5069555AFBBD3AEBFCABFBBED7A5C5FE9BD0E6A91C6E7610042695EEB08D8881B1D735AF87DAE59FABBD7DEAF8717F2B72F428F5E37E5D6E13157B99CBD2D73B9C73C563C8B02C8CC39C64DDCEA1BEEB5E7353F93786145598FE634EF1000179B345725EA43CE18F187A1DE4DAABEA97963E3A7A96B8B7CBC095BEB7CE46274D9AF; -defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h4ED4AE2B1650D21EAFE01E7099EFCA3094FD4D705CF6B84AE21583E13385F8650004406BD60A023AB063D4E5966EA41AA997F5A49BFCB0657A9732D28EB8217E65F627A15E1057ADEE7B9E27122A58FB2B98B1EA560390C7E87715861814E04DCB76FAB179E9619BC7E7E9C9FD801CF87DBA1EA496E829D4E62861E1AF436A7585287860729C77B6C68CAEA3033A6E84D67249B594C407B39C68B4C1C97FDEFC6BAD12FDBB525EF4F87F4A23EC13CBC0262D8899A3A290F04F41C1324045B9FCEEC890579E95D5A0A546CCCDD48577558ABE7CA36EF67A70F6A8758BDA052D5B95DE707778B17C2379847A23AE5D4BB01F36F3F44A8162566D9FB15DE7CC83F7; -// synopsys translate_on - -// Location: M9K_X22_Y27_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a8 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(gnd), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[0]~58_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_first_bit_number = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N4 -cycloneive_lcell_comb \D[0]~52 ( -// Equation(s): -// \D[0]~52_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\z80_|address_pins_|abus[14]~23_combout & ((\ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ))) # (!\z80_|address_pins_|abus[14]~23_combout & -// (\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\z80_|address_pins_|abus[14]~23_combout )))) - - .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ), - .datac(\z80_|address_pins_|abus[14]~23_combout ), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ), - .cin(gnd), - .combout(\D[0]~52_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~52 .lut_mask = 16'hF858; -defparam \D[0]~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y20_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a0 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h1EEA3633EFEA856D05BA968C1B3C30CA1788DD95D16B8F914DDDFC3EE5C69945DF7D7BF31C6072BFA7993996AB7DD2F3EE4009844CC9D6CF9E583AEC48A52F2904B57D8E0D755851232838F9B5348838530D7AF95411555D263B8CA86A5D29D7CE4B65409D6F04C5709A56C241C3BCEF07459A416EB4E8F3D73CC714F4333AFE605D53A5C955D5D1412F8361617A54446971FD187442A60FB04457857BECC3120A01FDC7FE2CBF038A61DEE5FCE2D10C8F35FBF80C05ABFF4B6935287B125E8D56F9FDFE7D64C1F4E1F5641845CD17E836B97780400C702523FA8E7C7BBD6F0666591A35ADD26B6B7E33CA56E9AB329EFA7E68F98AE7CE9507755C74C430286A; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h88537A811D4EF6CD9668CCD3E2E7A8041788DCA5F7E08AF52AF5276078304DEB75B74BB9AC3C1A492952F7EEAA0E7CF9FBEDD0FB47EEFDCC3734B816F355C913CD2E1AF14C30545297A91BED3AEAEFF8F696B5F4FC80BC6B1A2559492E9198E4A5875745B625C6CA7A7292332492D139728A689DA1AE78B6B44CE4F4A4EA5A22F331598B364EF27516CC49A4662C5E5C92ED140D96373678F833AE434698237599716B8CBAE2D3D061F2C3D6337AB435B5C2144AB6FA2F8BB51357801066B6589467DA6C480E6D19CEEA8451CEFA88FD70E7925B0302F877F87FA833FBD147E937309C08305A10187707E3D57DDE4931F1D9E97A8F378981ABBF8D7B6B7539C3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h763DD7AA7EED3F4AD4EA7491ADE6F14E6DBADD0F090A8DF34D7BAD35DD2275F0BCCF19EEF299751C919C9C13C6FB9ED711AC4DA7D947CC79E9B6323EF6CE62638CEBCB187AE5D44ECA689C9BD4E5AE544DEA7E90D186B9F335F3323877AAD54196CE81973CB555904419599375501366EC343561BCF83357F8823671393B278C1C387A7970C7F3E688673CF5975EE3E5FF105CFCCFAB725D698FB088B063063C7833830C7B2C7AFB8A8D203C312306DA0E72641FFB93D59B5EC84F44AD55F4B884735325ACC969B2EAE10A1478D866F667DDEF7BBF75E6958B6D02DC6D0F807660A229B98541E6FE734DE2280A9B57FCD5A9BEFEF7CDA5ABEB44FD73D2794D56; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'hD0734B461A36980411EB2A6C1BE76029258777EF227A8F6E84F74C4436098F67BA611013110188547995B108BB2DAE76F423A0D98845F9248BDFA45E10CA403A5E2B1A3E16869E1D37BCE906B82F401CBD467617DB34D9E0C80B5E6E10063EC4BD52921D249E377D95CFAAA309EEDAA57DA85F55DBB7048A69A4C801013948B617F7F5724D40707E6FF30002982023020449B4680C45D1CE6D8EB30A061DB8FEDD6E630C15271E48CA801988654FB501D5393392EE765C1EC95C1E4D86F18A965372B72B484E2F2664B735B69A5AB532B086BA4C62AD6D56EECBDB6984B251454845BD5B243DAED2B2489B313A35C50252AFD3E0B76FEF342335C7F1321D92FF; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N28 -cycloneive_lcell_comb \D[0]~53 ( -// Equation(s): -// \D[0]~53_combout = (\z80_|address_pins_|abus[15]~22_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout $ ((\D[0]~52_combout )))) # (!\z80_|address_pins_|abus[15]~22_combout & (((!\D[0]~52_combout & -// \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ), - .datab(\z80_|address_pins_|abus[15]~22_combout ), - .datac(\D[0]~52_combout ), - .datad(\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ), - .cin(gnd), - .combout(\D[0]~53_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~53 .lut_mask = 16'h4B48; -defparam \D[0]~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N16 -cycloneive_lcell_comb \D[0]~54 ( -// Equation(s): -// \D[0]~54_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[0]~52_combout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[0]~52_combout & -// (\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout & !\D[0]~53_combout )) # (!\D[0]~52_combout & ((\D[0]~53_combout ))))) - - .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\D[0]~52_combout ), - .datad(\D[0]~53_combout ), - .cin(gnd), - .combout(\D[0]~54_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~54 .lut_mask = 16'hC3E0; -defparam \D[0]~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N8 -cycloneive_lcell_comb \D[0]~106 ( -// Equation(s): -// \D[0]~106_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\D[0]~56_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\D[0]~54_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & -// (\D[0]~56_combout )))) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\D[0]~56_combout ), - .datad(\D[0]~54_combout ), - .cin(gnd), - .combout(\D[0]~106_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~106 .lut_mask = 16'hF4B0; -defparam \D[0]~106 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N14 -cycloneive_lcell_comb \D[0]~57 ( -// Equation(s): -// \D[0]~57_combout = ((\Equal2~0_combout & (\D[0]~51_combout )) # (!\Equal2~0_combout & ((\D[0]~106_combout )))) # (!\Equal2~1_combout ) - - .dataa(\Equal2~1_combout ), - .datab(\D[0]~51_combout ), - .datac(\D[0]~106_combout ), - .datad(\Equal2~0_combout ), - .cin(gnd), - .combout(\D[0]~57_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~57 .lut_mask = 16'hDDF5; -defparam \D[0]~57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N0 -cycloneive_lcell_comb \D[0]~58 ( -// Equation(s): -// \D[0]~58_combout = (\D[0]~57_combout & (((\z80_|data_pins_|dout [0]) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) # (!\D[0]~57_combout & (!\Equal2~1_combout & ((!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) - - .dataa(\Equal2~1_combout ), - .datab(\z80_|data_pins_|dout [0]), - .datac(\D[0]~57_combout ), - .datad(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .cin(gnd), - .combout(\D[0]~58_combout ), - .cout()); -// synopsys translate_off -defparam \D[0]~58 .lut_mask = 16'hC0F5; -defparam \D[0]~58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N0 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [0] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[0]~17_combout ) # ((\z80_|pin_control_|bus_db_pin_re~combout & \D[0]~58_combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & -// (((\z80_|pin_control_|bus_db_pin_re~combout & \D[0]~58_combout )))) - - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(\z80_|bus_control_|db[0]~17_combout ), - .datac(\z80_|pin_control_|bus_db_pin_re~combout ), - .datad(\D[0]~58_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [0]), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] .lut_mask = 16'hF888; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y13_N1 -dffeas \z80_|data_pins_|dout[0] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [0]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|data_pins_|dout [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|data_pins_|dout[0] .is_wysiwyg = "true"; -defparam \z80_|data_pins_|dout[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N4 -cycloneive_lcell_comb \z80_|bus_control_|db[0]~16 ( -// Equation(s): -// \z80_|bus_control_|db[0]~16_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [0]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) - - .dataa(gnd), - .datab(\z80_|bus_control_|db[0]~4_combout ), - .datac(\z80_|data_pins_|dout [0]), - .datad(\z80_|execute_|ctl_bus_db_oe~combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[0]~16_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[0]~16 .lut_mask = 16'hC0CC; -defparam \z80_|bus_control_|db[0]~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N28 -cycloneive_lcell_comb \z80_|bus_control_|db[0]~17 ( -// Equation(s): -// \z80_|bus_control_|db[0]~17_combout = ((\z80_|bus_control_|db[0]~16_combout & ((\z80_|alu_control_|db[0]~12_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - - .dataa(\z80_|bus_control_|db[0]~6_combout ), - .datab(\z80_|alu_control_|db[0]~12_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|bus_control_|db[0]~16_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[0]~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[0]~17 .lut_mask = 16'hDF55; -defparam \z80_|bus_control_|db[0]~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y13_N27 -dffeas \z80_|ir_|opcode[0] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\z80_|bus_control_|db[0]~17_combout ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|ir_|opcode [0]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|ir_|opcode[0] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N28 -cycloneive_lcell_comb \z80_|pla_decode_|Equal63~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal63~0_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [5] & (\z80_|execute_|comb~0_combout & \z80_|pla_decode_|Equal6~0_combout ))) - - .dataa(\z80_|ir_|opcode [0]), - .datab(\z80_|ir_|opcode [5]), - .datac(\z80_|execute_|comb~0_combout ), - .datad(\z80_|pla_decode_|Equal6~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal63~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal63~0 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal63~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_daa ( -// Equation(s): -// \z80_|execute_|ctl_flags_cf2_sel_daa~combout = (!\z80_|ir_|opcode [4] & (!\z80_|ir_|opcode [3] & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal63~0_combout ))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [3]), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|pla_decode_|Equal63~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_flags_cf2_sel_daa .lut_mask = 16'h1000; -defparam \z80_|execute_|ctl_flags_cf2_sel_daa .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N20 -cycloneive_lcell_comb \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 ( -// Equation(s): -// \z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout = (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )) # (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ))) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), - .datad(\z80_|pla_decode_|Equal47~0_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 .lut_mask = 16'h070F; -defparam \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N22 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~10 ( -// Equation(s): -// \z80_|alu_control_|db[6]~10_combout = ((\z80_|execute_|ctl_sw_2u~7_combout ) # (\z80_|execute_|ctl_flags_oe~2_combout )) # (!\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ) - - .dataa(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_sw_2u~7_combout ), - .datad(\z80_|execute_|ctl_flags_oe~2_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~10 .lut_mask = 16'hFFF5; -defparam \z80_|alu_control_|db[6]~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N28 -cycloneive_lcell_comb \z80_|alu_control_|db[6]~11 ( -// Equation(s): -// \z80_|alu_control_|db[6]~11_combout = (\z80_|alu_control_|db[6]~10_combout ) # ((\z80_|execute_|ctl_sw_1d~7_combout ) # (\z80_|execute_|ctl_reg_out_lo~8_combout )) - - .dataa(\z80_|alu_control_|db[6]~10_combout ), - .datab(\z80_|execute_|ctl_sw_1d~7_combout ), - .datac(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|alu_control_|db[6]~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[6]~11 .lut_mask = 16'hFEFE; -defparam \z80_|alu_control_|db[6]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N18 -cycloneive_lcell_comb \z80_|alu_control_|db[4]~30 ( -// Equation(s): -// \z80_|alu_control_|db[4]~30_combout = (\z80_|alu_|db[4]~17_combout & (\z80_|execute_|ctl_reg_out_lo~8_combout & (!\z80_|reg_file_|gdfx_temp0[4]~62_combout ))) # (!\z80_|alu_|db[4]~17_combout & ((\z80_|execute_|ctl_sw_2u~7_combout ) # -// ((\z80_|execute_|ctl_reg_out_lo~8_combout & !\z80_|reg_file_|gdfx_temp0[4]~62_combout )))) - - .dataa(\z80_|alu_|db[4]~17_combout ), - .datab(\z80_|execute_|ctl_reg_out_lo~8_combout ), - .datac(\z80_|reg_file_|gdfx_temp0[4]~62_combout ), - .datad(\z80_|execute_|ctl_sw_2u~7_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[4]~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[4]~30 .lut_mask = 16'h5D0C; -defparam \z80_|alu_control_|db[4]~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N24 -cycloneive_lcell_comb \z80_|alu_control_|db[4]~31 ( -// Equation(s): -// \z80_|alu_control_|db[4]~31_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & (!\z80_|alu_control_|db[4]~30_combout & ((\z80_|alu_flags_|flags_hf~combout ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) - - .dataa(\z80_|alu_flags_|flags_hf~combout ), - .datab(\z80_|execute_|ctl_flags_oe~2_combout ), - .datac(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), - .datad(\z80_|alu_control_|db[4]~30_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[4]~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[4]~31 .lut_mask = 16'h00B0; -defparam \z80_|alu_control_|db[4]~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y11_N6 -cycloneive_lcell_comb \z80_|alu_control_|db[4]~32 ( -// Equation(s): -// \z80_|alu_control_|db[4]~32_combout = ((\z80_|alu_control_|db[4]~31_combout & ((\z80_|bus_control_|db[4]~19_combout ) # (!\z80_|execute_|ctl_sw_1d~7_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) - - .dataa(\z80_|bus_control_|db[4]~19_combout ), - .datab(\z80_|alu_control_|db[6]~11_combout ), - .datac(\z80_|execute_|ctl_sw_1d~7_combout ), - .datad(\z80_|alu_control_|db[4]~31_combout ), - .cin(gnd), - .combout(\z80_|alu_control_|db[4]~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|alu_control_|db[4]~32 .lut_mask = 16'hBF33; -defparam \z80_|alu_control_|db[4]~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~119 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][4]~119_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [2]))) # (!\ula_|ps2_keyboard_|shiftreg [0] & -// (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [2]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [0]), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][4]~119_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][4]~119 .lut_mask = 16'h0420; -defparam \ula_|zx_keyboard_|keys[2][4]~119 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~120 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][4]~120_combout = (\ula_|zx_keyboard_|keys[5][1]~36_combout & (\ula_|zx_keyboard_|keys[2][4]~119_combout & (\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [1]))) - - .dataa(\ula_|zx_keyboard_|keys[5][1]~36_combout ), - .datab(\ula_|zx_keyboard_|keys[2][4]~119_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][4]~120_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][4]~120 .lut_mask = 16'h0080; -defparam \ula_|zx_keyboard_|keys[2][4]~120 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~95 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][4]~95_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [6])) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|shifted~q ), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][4]~95_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][4]~95 .lut_mask = 16'hAFAA; -defparam \ula_|zx_keyboard_|keys[2][4]~95 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~121 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][4]~121_combout = (\ula_|zx_keyboard_|keys[2][4]~120_combout & ((!\ula_|zx_keyboard_|keys[2][4]~95_combout ))) # (!\ula_|zx_keyboard_|keys[2][4]~120_combout & (\ula_|zx_keyboard_|keys[2][4]~q )) - - .dataa(\ula_|zx_keyboard_|keys[2][4]~120_combout ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[2][4]~q ), - .datad(\ula_|zx_keyboard_|keys[2][4]~95_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][4]~121_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][4]~121 .lut_mask = 16'h50FA; -defparam \ula_|zx_keyboard_|keys[2][4]~121 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y18_N23 -dffeas \ula_|zx_keyboard_|keys[2][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[2][4]~121_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[2][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[2][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~117 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][4]~117_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|zx_keyboard_|extended~q ))) # (!\ula_|ps2_keyboard_|shiftreg [2] & -// (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|zx_keyboard_|extended~q ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|zx_keyboard_|extended~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][4]~117_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][4]~117 .lut_mask = 16'h4002; -defparam \ula_|zx_keyboard_|keys[3][4]~117 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~136 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][4]~136_combout = (\ula_|zx_keyboard_|keys[3][4]~117_combout & (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [4]))) - - .dataa(\ula_|zx_keyboard_|keys[3][4]~117_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][4]~136_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][4]~136 .lut_mask = 16'h0080; -defparam \ula_|zx_keyboard_|keys[3][4]~136 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y21_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~130 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][4]~130_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (!\ula_|zx_keyboard_|Equal0~1_combout & (!\ula_|ps2_keyboard_|shiftreg [7] & \ula_|ps2_keyboard_|shiftreg [5]))) - - .dataa(\ula_|ps2_keyboard_|scan_code_ready~q ), - .datab(\ula_|zx_keyboard_|Equal0~1_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [7]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][4]~130_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][4]~130 .lut_mask = 16'h0200; -defparam \ula_|zx_keyboard_|keys[3][4]~130 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~118 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][4]~118_combout = (\ula_|zx_keyboard_|keys[3][4]~136_combout & ((\ula_|zx_keyboard_|keys[3][4]~130_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][4]~130_combout & ((\ula_|zx_keyboard_|keys[3][4]~q -// ))))) # (!\ula_|zx_keyboard_|keys[3][4]~136_combout & (((\ula_|zx_keyboard_|keys[3][4]~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[3][4]~136_combout ), - .datac(\ula_|zx_keyboard_|keys[3][4]~q ), - .datad(\ula_|zx_keyboard_|keys[3][4]~130_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][4]~118_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][4]~118 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[3][4]~118 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y18_N9 -dffeas \ula_|zx_keyboard_|keys[3][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[3][4]~118_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[3][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[3][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N18 -cycloneive_lcell_comb \D[4]~78 ( -// Equation(s): -// \D[4]~78_combout = (\z80_|address_pins_|abus[11]~19_combout & ((\z80_|address_pins_|abus[10]~24_combout ) # ((!\ula_|zx_keyboard_|keys[2][4]~q )))) # (!\z80_|address_pins_|abus[11]~19_combout & (!\ula_|zx_keyboard_|keys[3][4]~q & -// ((\z80_|address_pins_|abus[10]~24_combout ) # (!\ula_|zx_keyboard_|keys[2][4]~q )))) - - .dataa(\z80_|address_pins_|abus[11]~19_combout ), - .datab(\z80_|address_pins_|abus[10]~24_combout ), - .datac(\ula_|zx_keyboard_|keys[2][4]~q ), - .datad(\ula_|zx_keyboard_|keys[3][4]~q ), - .cin(gnd), - .combout(\D[4]~78_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~78 .lut_mask = 16'h8ACF; -defparam \D[4]~78 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~126 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][4]~126_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[7][1]~23_combout & (\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [6]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|zx_keyboard_|keys[7][1]~23_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][4]~126_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][4]~126 .lut_mask = 16'h0040; -defparam \ula_|zx_keyboard_|keys[6][4]~126 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~128 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][4]~128_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [1]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][4]~128_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][4]~128 .lut_mask = 16'h0080; -defparam \ula_|zx_keyboard_|keys[5][4]~128 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~129 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][4]~129_combout = (\ula_|zx_keyboard_|keys[6][4]~126_combout & ((\ula_|zx_keyboard_|keys[5][4]~128_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[5][4]~128_combout & -// (\ula_|zx_keyboard_|keys[5][4]~q )))) # (!\ula_|zx_keyboard_|keys[6][4]~126_combout & (((\ula_|zx_keyboard_|keys[5][4]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[6][4]~126_combout ), - .datab(\ula_|zx_keyboard_|keys[5][4]~128_combout ), - .datac(\ula_|zx_keyboard_|keys[5][4]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][4]~129_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][4]~129 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[5][4]~129 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y19_N9 -dffeas \ula_|zx_keyboard_|keys[5][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[5][4]~129_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[5][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[5][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~127 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][4]~127_combout = (\ula_|zx_keyboard_|keys[6][4]~126_combout & ((\ula_|zx_keyboard_|keys[6][4]~20_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[6][4]~20_combout & ((\ula_|zx_keyboard_|keys[6][4]~q -// ))))) # (!\ula_|zx_keyboard_|keys[6][4]~126_combout & (((\ula_|zx_keyboard_|keys[6][4]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[6][4]~126_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[6][4]~q ), - .datad(\ula_|zx_keyboard_|keys[6][4]~20_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][4]~127_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][4]~127 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[6][4]~127 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y20_N5 -dffeas \ula_|zx_keyboard_|keys[6][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[6][4]~127_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[6][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[6][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~2 ( -// Equation(s): -// \ula_|zx_keyboard_|Equal0~2_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [0])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|Equal0~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|Equal0~2 .lut_mask = 16'h0050; -defparam \ula_|zx_keyboard_|Equal0~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~51 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][4]~51_combout = (\ula_|zx_keyboard_|keys[7][1]~23_combout & (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [1] & \ula_|zx_keyboard_|Equal0~2_combout ))) - - .dataa(\ula_|zx_keyboard_|keys[7][1]~23_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|zx_keyboard_|Equal0~2_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][4]~51_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][4]~51 .lut_mask = 16'h2000; -defparam \ula_|zx_keyboard_|keys[7][4]~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~125 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][4]~125_combout = (\ula_|zx_keyboard_|shifted~1_combout & ((\ula_|zx_keyboard_|keys[7][4]~51_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[7][4]~51_combout & ((\ula_|zx_keyboard_|keys[7][4]~q ))))) -// # (!\ula_|zx_keyboard_|shifted~1_combout & (((\ula_|zx_keyboard_|keys[7][4]~q )))) - - .dataa(\ula_|zx_keyboard_|shifted~1_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[7][4]~q ), - .datad(\ula_|zx_keyboard_|keys[7][4]~51_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][4]~125_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][4]~125 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[7][4]~125 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y20_N11 -dffeas \ula_|zx_keyboard_|keys[7][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[7][4]~125_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[7][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[7][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N30 -cycloneive_lcell_comb \D[4]~79 ( -// Equation(s): -// \D[4]~79_combout = (\z80_|address_pins_|abus[15]~22_combout & ((\z80_|address_pins_|abus[14]~23_combout ) # ((!\ula_|zx_keyboard_|keys[6][4]~q )))) # (!\z80_|address_pins_|abus[15]~22_combout & (!\ula_|zx_keyboard_|keys[7][4]~q & -// ((\z80_|address_pins_|abus[14]~23_combout ) # (!\ula_|zx_keyboard_|keys[6][4]~q )))) - - .dataa(\z80_|address_pins_|abus[15]~22_combout ), - .datab(\z80_|address_pins_|abus[14]~23_combout ), - .datac(\ula_|zx_keyboard_|keys[6][4]~q ), - .datad(\ula_|zx_keyboard_|keys[7][4]~q ), - .cin(gnd), - .combout(\D[4]~79_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~79 .lut_mask = 16'h8ACF; -defparam \D[4]~79 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~122 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][4]~122_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|zx_keyboard_|extended~q )) # (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [6] & -// \ula_|zx_keyboard_|extended~q )) - - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(gnd), - .datad(\ula_|zx_keyboard_|extended~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][4]~122_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][4]~122 .lut_mask = 16'h4422; -defparam \ula_|zx_keyboard_|keys[4][4]~122 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~123 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][4]~123_combout = (\ula_|zx_keyboard_|Equal0~2_combout & (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[4][4]~122_combout ))) - - .dataa(\ula_|zx_keyboard_|Equal0~2_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [1]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|keys[4][4]~122_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][4]~123_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][4]~123 .lut_mask = 16'h8000; -defparam \ula_|zx_keyboard_|keys[4][4]~123 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~124 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][4]~124_combout = (\ula_|zx_keyboard_|keys[0][0]~15_combout & ((\ula_|zx_keyboard_|keys[4][4]~123_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[4][4]~123_combout & ((\ula_|zx_keyboard_|keys[4][4]~q -// ))))) # (!\ula_|zx_keyboard_|keys[0][0]~15_combout & (((\ula_|zx_keyboard_|keys[4][4]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[4][4]~q ), - .datad(\ula_|zx_keyboard_|keys[4][4]~123_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][4]~124_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][4]~124 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[4][4]~124 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y19_N25 -dffeas \ula_|zx_keyboard_|keys[4][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[4][4]~124_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[4][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[4][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~3 ( -// Equation(s): -// \ula_|zx_keyboard_|key_row~3_combout = ((\z80_|address_pins_|DFFE_apin_latch [12]) # (!\ula_|zx_keyboard_|keys[4][4]~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [12]), - .datad(\ula_|zx_keyboard_|keys[4][4]~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|key_row~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|key_row~3 .lut_mask = 16'hF3FF; -defparam \ula_|zx_keyboard_|key_row~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N8 -cycloneive_lcell_comb \D[4]~80 ( -// Equation(s): -// \D[4]~80_combout = (\D[4]~79_combout & (\ula_|zx_keyboard_|key_row~3_combout & ((\z80_|address_pins_|abus[13]~20_combout ) # (!\ula_|zx_keyboard_|keys[5][4]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[5][4]~q ), - .datab(\D[4]~79_combout ), - .datac(\z80_|address_pins_|abus[13]~20_combout ), - .datad(\ula_|zx_keyboard_|key_row~3_combout ), - .cin(gnd), - .combout(\D[4]~80_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~80 .lut_mask = 16'hC400; -defparam \D[4]~80 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~111 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][4]~111_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [6])) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|shifted~q ), - .datad(\ula_|ps2_keyboard_|shiftreg [6]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][4]~111_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][4]~111 .lut_mask = 16'hFAAA; -defparam \ula_|zx_keyboard_|keys[0][4]~111 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~97 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][4]~97_combout = (\ula_|zx_keyboard_|keys[5][1]~36_combout & (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [6] $ (\ula_|ps2_keyboard_|shiftreg [5])))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|zx_keyboard_|keys[5][1]~36_combout ), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][4]~97_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][4]~97 .lut_mask = 16'h0060; -defparam \ula_|zx_keyboard_|keys[0][4]~97 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~116 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][4]~116_combout = (\ula_|zx_keyboard_|keys[3][1]~29_combout & ((\ula_|zx_keyboard_|keys[0][4]~97_combout & (!\ula_|zx_keyboard_|keys[0][4]~111_combout )) # (!\ula_|zx_keyboard_|keys[0][4]~97_combout & -// ((\ula_|zx_keyboard_|keys[0][4]~q ))))) # (!\ula_|zx_keyboard_|keys[3][1]~29_combout & (((\ula_|zx_keyboard_|keys[0][4]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[3][1]~29_combout ), - .datab(\ula_|zx_keyboard_|keys[0][4]~111_combout ), - .datac(\ula_|zx_keyboard_|keys[0][4]~q ), - .datad(\ula_|zx_keyboard_|keys[0][4]~97_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][4]~116_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][4]~116 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[0][4]~116 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y18_N11 -dffeas \ula_|zx_keyboard_|keys[0][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[0][4]~116_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[0][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[0][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N6 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][4]~115 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][4]~115_combout = (\ula_|zx_keyboard_|Equal0~2_combout & ((\ula_|zx_keyboard_|keys[1][4]~25_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[1][4]~25_combout & (\ula_|zx_keyboard_|keys[1][4]~q )))) # -// (!\ula_|zx_keyboard_|Equal0~2_combout & (((\ula_|zx_keyboard_|keys[1][4]~q )))) - - .dataa(\ula_|zx_keyboard_|Equal0~2_combout ), - .datab(\ula_|zx_keyboard_|keys[1][4]~25_combout ), - .datac(\ula_|zx_keyboard_|keys[1][4]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][4]~115_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][4]~115 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[1][4]~115 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y19_N7 -dffeas \ula_|zx_keyboard_|keys[1][4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[1][4]~115_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[1][4]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][4] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[1][4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N28 -cycloneive_lcell_comb \D[4]~77 ( -// Equation(s): -// \D[4]~77_combout = (\z80_|address_pins_|abus[9]~17_combout & ((\z80_|address_pins_|abus[8]~18_combout ) # ((!\ula_|zx_keyboard_|keys[0][4]~q )))) # (!\z80_|address_pins_|abus[9]~17_combout & (!\ula_|zx_keyboard_|keys[1][4]~q & -// ((\z80_|address_pins_|abus[8]~18_combout ) # (!\ula_|zx_keyboard_|keys[0][4]~q )))) - - .dataa(\z80_|address_pins_|abus[9]~17_combout ), - .datab(\z80_|address_pins_|abus[8]~18_combout ), - .datac(\ula_|zx_keyboard_|keys[0][4]~q ), - .datad(\ula_|zx_keyboard_|keys[1][4]~q ), - .cin(gnd), - .combout(\D[4]~77_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~77 .lut_mask = 16'h8ACF; -defparam \D[4]~77 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N26 -cycloneive_lcell_comb \D[4]~81 ( -// Equation(s): -// \D[4]~81_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[4]~78_combout & (\D[4]~80_combout & \D[4]~77_combout ))) - - .dataa(\z80_|address_pins_|abus[0]~16_combout ), - .datab(\D[4]~78_combout ), - .datac(\D[4]~80_combout ), - .datad(\D[4]~77_combout ), - .cin(gnd), - .combout(\D[4]~81_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~81 .lut_mask = 16'hEAAA; -defparam \D[4]~81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y1_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a12 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'hA50276000854A0103840403E540424244404783E18807A08A47C54484448544A807E7E10005270182040407E4A1252124208084008404208420A4A42424A125A024428106448524A624A4A24425242522060108010543C00044A105424005E0031ED1E0529E507AE2F6FF1CD51D4C772A648E65F6532C28022061303F06C36CDBD319B55CB8E626C20E46C93C1463A0B1CE594F0ED3B62330C104DECE46CA6CD966B1386612C7B43980349408F36FB64C14342DAE26CE4D8D5E791388729D743B09A27AB81D71A14AB3D24E385B602248476D00249239514B58D3098504ACD119B99E9021B650A69494C22600667473128DA5010D2195982823226DED0ADFCB8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h5861917919344A4685CC0990862A11324792E761B6D41C0FCC0838C1C27211A2453FDC2219C225E421B320085A8FBFD0C42135B16448DFC226E09B3438A740C352979565817114DE46462844A57F7958873FC4B255C8AE549BDD1A87415D5018F88D5002628FFD13203066C850F10649F21319109208387641120B362124803F0678522BA2812C1454A502ED1A59CBD76A034756F5765DF7555F57575F7F57FFFF7FFF7D5712524D4A30723514B2B3064A84B4742D48415281863DDFAA9D9B7E7BB16DDB96B7845371C30B55DB96C8F6EB4B453242FF6A4DF84A76B5AEDC88A68DC6A06905054C8C36E4199E74638E6532965218A965909BA456000451343351; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'hE2975A2686A7AE0288F140141B698E2A82A835F478453A1D722CFCED12859FD735188757AC5A42DEB501FE010586249AC1EA60D08F74CFA5086EC78FC9190C056059E332C311521E6522901852D484B423A98816C9B26A08C92368E9FF05524502288A804612A2A0A102A418CBDFBA554499541660F8124640110101263142892A086B442661015380041594608092D9CB919250100A37DDA3919A1427F660963C251301FB2CA45562245308885131119115C652B2493252340201101942D26000CC60799124A8520C08050122171281808058018C38A645D07931896B39ED259A22242CB58413089465B246231330D806105010035100B08761A08506094160; -defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h1228D91C352915424000000AA0088F63153A8AD81B945C8789F01C86548D12CEAB6AA38578BD55CEC9AA28082C285B8C0201104838AD502AC160C13C70620B818249144AB52CED94200A0202A885100E0D938A30A34512C0CEC98F08A98900F2093E11673256B3169C12284980E92A034141E0782507800F8100009C403C07867000000030082004A17800828F090A0C318CE120012172286317922341A2A12840B6C18040682080125C75401AEC44E8C01A8D40D1412B25A09F7600B0C6FEC65BFE5CE861A20F71E8032916A78F29CC546518461522E4E14998DD54BC0E40B64B710C9DC948F06010DF01D880E2044BE8854062D10DD93F30A62AA7FD227C4C; -// synopsys translate_on - -// Location: M9K_X22_Y22_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a12 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(gnd), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[4]~98_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_first_bit_number = 4; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y3_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a4 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h35861A00A6112A1481AF1A50A6004A05291627227FF08229B87389E08119A28A7888672DC999B7046A61E60810A7434450E3D33E330F321A18E8A120D1EDC8623DA2C64840C2CCE811522B42008095E5A456C98F4B25EAEA410610545024640CF10410AC463BF9349074917E9A74A12830EFA280EBD3131E484A255D0191C6852730A263DBCCAAA88712242B3BE49AA5338990229B391158C726BC7EB4ECC32308980020680249882691A680488292310B4313CE87FFCD5329A64B708CAC8533316412C4900F646A36630261DA093053D98F19D2C5B653165D4A71AA5682B29B89B6054CC727D292805705A93268676A31111371390B240EC3CC85D331813EB1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h1AA1C248D293110CB951445117D9B6AA500F65068B8CC508BD00184F8705B010A0CC46CC9302649242CE08191634113154562B149100204551178DE805D98EC8A2E5A64B241400267194CD524499BC01D31058CD18684A817A5800B65143281C1310B00A49902C0104004C654E0582040001103654011012021912281216B000C653A0510A1B00C36AC88058CAC126E14E198DFB07E81C3F41510BB08F8F851C3B9AF0147BC1F730B4E91D9D11C3A8F1B82DF19988ACC44072FDB17B4D81882E9DD952B29003D7767BA581A68BC41C2B16AD6EB57F1D048CD4E464190D25ADF2C194E3598360AFB031A1690F4625BB628363B4C90A400E3A04DAA70DA0CC4776; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'hC82B30671933680037A65978674DDEC2D30EEEDA78F5F2A1DEE660FFEA11B175DCB42E9277212A58842051A078007109A0D820166B881042600284403143048295D23A0E191EBC2134B833D53D37E42B05018289A10300A188E315CE98640F548A370D60A0AA3E7288A0B0869FA5E703D1AE17C0EC276B2AFB747B550A8B41021620D1A60A901095D12A0973B95E20838001330138951361967847D42901910A3488480610A91A851E84FF08783F81AEA52D2FDC2200BD2FE81C0357FBEC1D875686C6CA41B2224C88D8456C1DBF20D820A6649774CB11B69933246E9739C998470542C2E3C783A4C24767084C52DC209D60E95DBC096D9A0171A12D5AB99BAB; -defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h17A24D2C636ED2478B5AE1C99D40761B1E7AA6A89DDD1BBD8DBD223E70531BCDE90C8E38C8E0478AD8B388F94891C9673A50BC32478E083074657E8E0EA53BEE861F8BC1993560946D92D1C0C7F046A245B5849CB751FF15B97FCD50BC7B8524C13E7C640F3645082248D1CC14296E30DEA3057B35C641762CD00D40DABC27472251A60725008AAA056591C4000BB48C0BC29B8034A03400027B84769B520D9196968460CA3388A03ECB45F2C4B70F1829221000FFFC7FEC346F079F13079798EC2A08157331C6CC0E30884244916A0DE26D4D22454091290404A492016887E2111F830F9851184101370588A06D3BF9AE621A5F4E632A6799C83EFAAE06769D; -// synopsys translate_on - -// Location: M9K_X22_Y25_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a4 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[4]~98_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a4_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_first_bit_number = 4; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFFF0000003E0000003E0000C83F0000D83F0000F03F0000303E0000303E0000003F0010003F0010203F0010F03F0010703F0018303F001C603D800C003CFE26003C7F0F803FFFFFFFFFFFFFFFF; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF00000000000008108000BDF288E9688E000000000000000000000000FFFFFFFF0000000000041D989EA296D29EE969CA000000000000000000000000000000007FFFFFFC8004198A9AA298929EE9498A00000000000000000000000000000000FFFFFFFE800400CA9AA2AADA8AE949CE0000000000000000000000007FFFFFFEC00000028004046A9F22BA5A9EE90FC20000000000000000000000007FFFFFFE8000000280040FEA8002AA7A9EE12742000000000000000000000000000000023FFFFFFC9FE42BA298E2293A80096742000000000000000000000000000000003FFFFFFC9FE4B19298E3181E8009436A; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'h9FE8234A88F836EE9FF8BD4208282BC080DE87C2B84199C2B85E37C2B05B3A829FE8236688F837CE9FF8898208A82A44808A87CAB9C19DC2B80E3AC2927F2AC2800833E288F837C69FE8AB9688882E4283248DC2B9D188C2ABAE2F8291371092800832EA887807C69FE8AB8688080AC283E49D42B914BFC2A3BF1E82910712EA800802EA883807869DE88E8688080AC68BC4BDC2BB1439C2A27F5F82910314E2800886E6880807C69CC89A8681800BC289549CC2AB0C3942A04B7F82953315E2800886EE900805C61C089FC081E415C289D89DC2AB4E3142A1233D8217330090800086EE900805821C08BEC080D407C289C89DC2AADE3142A13B7F82176300F0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h076B0A5083288F028370C182A801468297E5AC1288D308023FFFFFFC00000000072BA9608BA08D028BF4D182AC015682937CA80288D308023FFFFFFC00000002872B892A8FA08F028A14509AAC0166B2B37DA80288D10D02800000027FFFFFFE852BAD128E388D028A004082AC0166C2937DA00288D10F02C00000027FFFFFFE846289368968C90289E0528A8C016CA29379B20280510F02FFFFFFFE0000000085E2A922816089828BE0428286416C829179B00280511F027FFFFFFC0000000087EA8B32872089828800569287436CA28179B20200513F0000000000FFFFFFFF8768A3028610858288004682874364828019900200403E0000000000FFFFFFFF; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N2 -cycloneive_lcell_comb \Selector4~0 ( -// Equation(s): -// \Selector4~0_combout = (\z80_|address_pins_|abus[14]~23_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout )))) # (!\z80_|address_pins_|abus[14]~23_combout -// & (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ))) - - .dataa(\z80_|address_pins_|abus[14]~23_combout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout ), - .cin(gnd), - .combout(\Selector4~0_combout ), - .cout()); -// synopsys translate_off -defparam \Selector4~0 .lut_mask = 16'hBA98; -defparam \Selector4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N26 -cycloneive_lcell_comb \Selector4~1 ( -// Equation(s): -// \Selector4~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Selector4~0_combout & ((\ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ))) # (!\Selector4~0_combout & -// (\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Selector4~0_combout )))) - - .dataa(\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ), - .datad(\Selector4~0_combout ), - .cin(gnd), - .combout(\Selector4~1_combout ), - .cout()); -// synopsys translate_off -defparam \Selector4~1 .lut_mask = 16'hF388; -defparam \Selector4~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y14_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a28 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[4]~98_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a28_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_first_bit_number = 4; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y8_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a12 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[4]~98_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y16_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a20 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[4]~98_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_first_bit_number = 4; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y3_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a4 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[4]~98_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N20 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout )) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ))))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout ), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2 .lut_mask = 16'hE5E0; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N10 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2_combout & -// (\ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout )) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ))))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2_combout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ), - .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2_combout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3 .lut_mask = 16'hAFC0; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N6 -cycloneive_lcell_comb \D[4]~109 ( -// Equation(s): -// \D[4]~109_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\Selector4~1_combout -// )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3_combout ))))) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\Selector4~1_combout ), - .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3_combout ), - .cin(gnd), - .combout(\D[4]~109_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~109 .lut_mask = 16'hFB40; -defparam \D[4]~109 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N18 -cycloneive_lcell_comb \D[4]~97 ( -// Equation(s): -// \D[4]~97_combout = ((\Equal2~0_combout & (\D[4]~81_combout )) # (!\Equal2~0_combout & ((\D[4]~109_combout )))) # (!\Equal2~1_combout ) - - .dataa(\Equal2~0_combout ), - .datab(\D[4]~81_combout ), - .datac(\Equal2~1_combout ), - .datad(\D[4]~109_combout ), - .cin(gnd), - .combout(\D[4]~97_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~97 .lut_mask = 16'hDF8F; -defparam \D[4]~97 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N30 -cycloneive_lcell_comb \D[4]~98 ( -// Equation(s): -// \D[4]~98_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout & (\z80_|data_pins_|dout [4] & ((\D[4]~97_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\D[4]~97_combout ) # (!\Equal2~1_combout )))) - - .dataa(\z80_|data_pins_|dout [4]), - .datab(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datac(\Equal2~1_combout ), - .datad(\D[4]~97_combout ), - .cin(gnd), - .combout(\D[4]~98_combout ), - .cout()); -// synopsys translate_off -defparam \D[4]~98 .lut_mask = 16'hBB03; -defparam \D[4]~98 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N24 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[4] ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [4] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[4]~19_combout ) # ((\D[4]~98_combout & \z80_|pin_control_|bus_db_pin_re~combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & -// (\D[4]~98_combout & (\z80_|pin_control_|bus_db_pin_re~combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(\D[4]~98_combout ), - .datac(\z80_|pin_control_|bus_db_pin_re~combout ), - .datad(\z80_|bus_control_|db[4]~19_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [4]), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[4] .lut_mask = 16'hEAC0; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[4] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y13_N25 -dffeas \z80_|data_pins_|dout[4] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [4]), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|data_pins_|dout [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|data_pins_|dout[4] .is_wysiwyg = "true"; -defparam \z80_|data_pins_|dout[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N20 -cycloneive_lcell_comb \z80_|bus_control_|db[4]~18 ( -// Equation(s): -// \z80_|bus_control_|db[4]~18_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [4]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) - - .dataa(\z80_|data_pins_|dout [4]), - .datab(\z80_|bus_control_|db[0]~4_combout ), - .datac(gnd), - .datad(\z80_|execute_|ctl_bus_db_oe~combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[4]~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[4]~18 .lut_mask = 16'h88CC; -defparam \z80_|bus_control_|db[4]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y10_N18 -cycloneive_lcell_comb \z80_|bus_control_|db[4]~19 ( -// Equation(s): -// \z80_|bus_control_|db[4]~19_combout = ((\z80_|bus_control_|db[4]~18_combout & ((\z80_|alu_control_|db[4]~32_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - - .dataa(\z80_|bus_control_|db[0]~6_combout ), - .datab(\z80_|alu_control_|db[4]~32_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|bus_control_|db[4]~18_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[4]~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[4]~19 .lut_mask = 16'hDF55; -defparam \z80_|bus_control_|db[4]~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X34_Y10_N19 -dffeas \z80_|ir_|opcode[4] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|bus_control_|db[4]~19_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|ir_|opcode [4]), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|ir_|opcode[4] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N6 -cycloneive_lcell_comb \z80_|pla_decode_|Equal21~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal21~0_combout = (!\z80_|ir_|opcode [3] & \z80_|ir_|opcode [4]) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|ir_|opcode [3]), - .datad(\z80_|ir_|opcode [4]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal21~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal21~0 .lut_mask = 16'h0F00; -defparam \z80_|pla_decode_|Equal21~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_mRead~5 ( -// Equation(s): -// \z80_|execute_|ctl_mRead~5_combout = (\z80_|pla_decode_|Equal21~0_combout & (\z80_|pla_decode_|Equal2~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal1~7_combout ))) - - .dataa(\z80_|pla_decode_|Equal21~0_combout ), .datab(\z80_|pla_decode_|Equal2~0_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~15 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_mRead~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~39 ( +// Equation(s): +// \z80_|execute_|ctl_inc_cy~39_combout = (((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|execute_|ctl_mRead~15_combout ) + + .dataa(\z80_|sequencer_|M5~q ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|execute_|ctl_mRead~15_combout ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_inc_cy~39_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_inc_cy~39 .lut_mask = 16'h1FFF; +defparam \z80_|execute_|ctl_inc_cy~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~36 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo[1]~36_combout = (\z80_|execute_|ctl_inc_cy~39_combout & (\z80_|execute_|ctl_inc_cy~38_combout & \z80_|execute_|ctl_inc_cy~82_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_inc_cy~39_combout ), + .datac(\z80_|execute_|ctl_inc_cy~38_combout ), + .datad(\z80_|execute_|ctl_inc_cy~82_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo[1]~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~36 .lut_mask = 16'hC000; +defparam \z80_|execute_|ctl_reg_sys_hilo[1]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~4 ( +// Equation(s): +// \z80_|execute_|ctl_sw_4u~4_combout = (\z80_|execute_|ctl_alu_op_low~22_combout & (\z80_|pla_decode_|Equal55~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal6~0_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal1~7_combout ), + .datad(\z80_|pla_decode_|Equal6~0_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_mRead~5_combout ), + .combout(\z80_|execute_|ctl_sw_4u~4_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mRead~5 .lut_mask = 16'h0800; -defparam \z80_|execute_|ctl_mRead~5 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_sw_4u~4 .lut_mask = 16'h0800; +defparam \z80_|execute_|ctl_sw_4u~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y18_N22 -cycloneive_lcell_comb \z80_|execute_|fIOWrite~2 ( +// Location: LCCOMB_X21_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~16 ( // Equation(s): -// \z80_|execute_|fIOWrite~2_combout = (\z80_|execute_|ctl_iorw~11_combout & ((\z80_|execute_|ctl_mWrite~3_combout ) # ((\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|execute_|fMRead~0_combout )))) +// \z80_|execute_|ctl_reg_sel_wz~16_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & (!\z80_|execute_|ctl_sw_4u~4_combout & ((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|ctl_ir_we~12_combout )))) - .dataa(\z80_|execute_|ctl_mWrite~3_combout ), - .datab(\z80_|execute_|ctl_state_alu~4_combout ), - .datac(\z80_|execute_|ctl_iorw~11_combout ), - .datad(\z80_|execute_|fMRead~0_combout ), + .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ), + .datab(\z80_|execute_|ctl_ir_we~12_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|ctl_sw_4u~4_combout ), .cin(gnd), - .combout(\z80_|execute_|fIOWrite~2_combout ), + .combout(\z80_|execute_|ctl_reg_sel_wz~16_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fIOWrite~2 .lut_mask = 16'hE0F0; -defparam \z80_|execute_|fIOWrite~2 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_reg_sel_wz~16 .lut_mask = 16'h0015; +defparam \z80_|execute_|ctl_reg_sel_wz~16 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y18_N16 -cycloneive_lcell_comb \z80_|execute_|fIOWrite~3 ( +// Location: LCCOMB_X21_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~17 ( // Equation(s): -// \z80_|execute_|fIOWrite~3_combout = ((!\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q ) +// \z80_|execute_|ctl_reg_sel_wz~17_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~36_combout & (\z80_|execute_|fMRead~6_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout & \z80_|execute_|ctl_reg_sel_wz~16_combout ))) - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T4_ff~q ), - .datac(\z80_|sequencer_|DFFE_M3_ff~q ), - .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~36_combout ), + .datab(\z80_|execute_|fMRead~6_combout ), + .datac(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ), + .datad(\z80_|execute_|ctl_reg_sel_wz~16_combout ), .cin(gnd), - .combout(\z80_|execute_|fIOWrite~3_combout ), + .combout(\z80_|execute_|ctl_reg_sel_wz~17_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fIOWrite~3 .lut_mask = 16'h3F0F; -defparam \z80_|execute_|fIOWrite~3 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_reg_sel_wz~17 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sel_wz~17 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y18_N2 -cycloneive_lcell_comb \z80_|execute_|fIOWrite~4 ( +// Location: LCCOMB_X27_Y17_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~5 ( // Equation(s): -// \z80_|execute_|fIOWrite~4_combout = (\z80_|execute_|ctl_mRead~36_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ixy_d~6_combout ) # (!\z80_|execute_|fIOWrite~3_combout )))) +// \z80_|execute_|ctl_sw_4u~5_combout = (\z80_|execute_|ctl_alu_op_low~28_combout ) # (((\z80_|execute_|ctl_alu_shift_oe~14_combout & \z80_|pla_decode_|Equal47~0_combout )) # (!\z80_|execute_|ctl_sw_4u~1_combout )) - .dataa(\z80_|execute_|ctl_mRead~36_combout ), - .datab(\z80_|execute_|ixy_d~5_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|execute_|fIOWrite~3_combout ), + .dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datab(\z80_|pla_decode_|Equal47~0_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~28_combout ), + .datad(\z80_|execute_|ctl_sw_4u~1_combout ), .cin(gnd), - .combout(\z80_|execute_|fIOWrite~4_combout ), + .combout(\z80_|execute_|ctl_sw_4u~5_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fIOWrite~4 .lut_mask = 16'hA8AA; -defparam \z80_|execute_|fIOWrite~4 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_sw_4u~5 .lut_mask = 16'hF8FF; +defparam \z80_|execute_|ctl_sw_4u~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y18_N4 -cycloneive_lcell_comb \z80_|execute_|fIOWrite~5 ( +// Location: LCCOMB_X29_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~6 ( // Equation(s): -// \z80_|execute_|fIOWrite~5_combout = (\z80_|execute_|fIOWrite~2_combout ) # ((\z80_|execute_|fIOWrite~4_combout ) # ((\z80_|execute_|fIOWrite~1_combout & \z80_|execute_|ctl_mRead~5_combout ))) +// \z80_|execute_|ctl_sw_4u~6_combout = (((\z80_|execute_|ctl_sw_4u~5_combout ) # (!\z80_|execute_|ctl_sw_4u~3_combout )) # (!\z80_|execute_|ctl_apin_mux~0_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~17_combout ) - .dataa(\z80_|execute_|fIOWrite~1_combout ), - .datab(\z80_|execute_|ctl_mRead~5_combout ), - .datac(\z80_|execute_|fIOWrite~2_combout ), - .datad(\z80_|execute_|fIOWrite~4_combout ), + .dataa(\z80_|execute_|ctl_reg_sel_wz~17_combout ), + .datab(\z80_|execute_|ctl_apin_mux~0_combout ), + .datac(\z80_|execute_|ctl_sw_4u~3_combout ), + .datad(\z80_|execute_|ctl_sw_4u~5_combout ), .cin(gnd), - .combout(\z80_|execute_|fIOWrite~5_combout ), + .combout(\z80_|execute_|ctl_sw_4u~6_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|fIOWrite~5 .lut_mask = 16'hFFF8; -defparam \z80_|execute_|fIOWrite~5 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_sw_4u~6 .lut_mask = 16'hFF7F; +defparam \z80_|execute_|ctl_sw_4u~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y17_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~11 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~11_combout = (!\z80_|execute_|ctl_mWrite~10_combout & (((!\z80_|execute_|ctl_mRead~10_combout & !\z80_|execute_|ctl_mRead~8_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|execute_|ctl_mWrite~10_combout ), - .datac(\z80_|execute_|ctl_mRead~8_combout ), - .datad(\z80_|execute_|ctl_state_alu~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~11 .lut_mask = 16'h0133; -defparam \z80_|execute_|ctl_mWrite~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~12 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~12_combout = (\z80_|execute_|ctl_mWrite~8_combout & (\z80_|execute_|ctl_mWrite~11_combout & ((!\z80_|execute_|ctl_mWrite~6_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|ctl_mWrite~8_combout ), - .datac(\z80_|execute_|ctl_mWrite~6_combout ), - .datad(\z80_|execute_|ctl_mWrite~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~12 .lut_mask = 16'h4C00; -defparam \z80_|execute_|ctl_mWrite~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y14_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~13 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~13_combout = (\z80_|execute_|ctl_mWrite~12_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~4_combout & (\z80_|execute_|ctl_mWrite~9_combout & \z80_|execute_|ctl_bus_db_oe~7_combout ))) - - .dataa(\z80_|execute_|ctl_mWrite~12_combout ), - .datab(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ), - .datac(\z80_|execute_|ctl_mWrite~9_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~13 .lut_mask = 16'h8000; -defparam \z80_|execute_|ctl_mWrite~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~14 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~14_combout = (\z80_|execute_|ctl_state_alu~4_combout & ((\z80_|execute_|ctl_mRead~7_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & \z80_|execute_|ctl_mWrite~5_combout )))) # (!\z80_|execute_|ctl_state_alu~4_combout & -// (((\z80_|execute_|ctl_eval_cond~0_combout & \z80_|execute_|ctl_mWrite~5_combout )))) - - .dataa(\z80_|execute_|ctl_state_alu~4_combout ), - .datab(\z80_|execute_|ctl_mRead~7_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|ctl_mWrite~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~14 .lut_mask = 16'hF888; -defparam \z80_|execute_|ctl_mWrite~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~15 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~15_combout = ((\z80_|execute_|ctl_mWrite~14_combout ) # ((!\z80_|execute_|ixy_d~17_combout & \z80_|execute_|ixy_d~8_combout ))) # (!\z80_|execute_|ctl_mWrite~13_combout ) - - .dataa(\z80_|execute_|ixy_d~17_combout ), - .datab(\z80_|execute_|ctl_mWrite~13_combout ), - .datac(\z80_|execute_|ctl_mWrite~14_combout ), - .datad(\z80_|execute_|ixy_d~8_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~15 .lut_mask = 16'hF7F3; -defparam \z80_|execute_|ctl_mWrite~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X43_Y17_N29 -dffeas \z80_|memory_ifc_|DFFE_mwr_ff1 ( +// Location: FF_X30_Y12_N27 +dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[3] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|execute_|ctl_mWrite~15_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|DFFE_mwr_ff1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|DFFE_mwr_ff1 .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|DFFE_mwr_ff1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N4 -cycloneive_lcell_comb \z80_|memory_ifc_|wait_mwr~feeder ( -// Equation(s): -// \z80_|memory_ifc_|wait_mwr~feeder_combout = \z80_|memory_ifc_|DFFE_mwr_ff1~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\z80_|memory_ifc_|DFFE_mwr_ff1~q ), - .cin(gnd), - .combout(\z80_|memory_ifc_|wait_mwr~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_mwr~feeder .lut_mask = 16'hFF00; -defparam \z80_|memory_ifc_|wait_mwr~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X43_Y17_N5 -dffeas \z80_|memory_ifc_|wait_mwr ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|memory_ifc_|wait_mwr~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|wait_mwr~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|wait_mwr .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|wait_mwr .power_up = "low"; -// synopsys translate_on - -// Location: FF_X43_Y17_N17 -dffeas \z80_|memory_ifc_|mwr_wr ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), - .asdata(\z80_|memory_ifc_|wait_mwr~q ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|memory_ifc_|mwr_wr~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|memory_ifc_|mwr_wr .is_wysiwyg = "true"; -defparam \z80_|memory_ifc_|mwr_wr .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N16 -cycloneive_lcell_comb \z80_|memory_ifc_|nWR_out~0 ( -// Equation(s): -// \z80_|memory_ifc_|nWR_out~0_combout = (\z80_|memory_ifc_|mwr_wr~q ) # ((\z80_|execute_|fIOWrite~5_combout & \z80_|memory_ifc_|iorq~0_combout )) - - .dataa(\z80_|execute_|fIOWrite~5_combout ), - .datab(\z80_|memory_ifc_|iorq~0_combout ), - .datac(\z80_|memory_ifc_|mwr_wr~q ), - .datad(gnd), - .cin(gnd), - .combout(\z80_|memory_ifc_|nWR_out~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|memory_ifc_|nWR_out~0 .lut_mask = 16'hF8F8; -defparam \z80_|memory_ifc_|nWR_out~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N4 -cycloneive_lcell_comb \D[5]~84 ( -// Equation(s): -// \D[5]~84_combout = (!\z80_|memory_ifc_|nWR_out~0_combout & (\z80_|memory_ifc_|nRD_out~2_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|memory_ifc_|nIORQ_out~0_combout ))) - - .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), - .datab(\z80_|memory_ifc_|nRD_out~2_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\z80_|memory_ifc_|nIORQ_out~0_combout ), - .cin(gnd), - .combout(\D[5]~84_combout ), - .cout()); -// synopsys translate_off -defparam \D[5]~84 .lut_mask = 16'h0040; -defparam \D[5]~84 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y5_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a23 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[7]~102_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_first_bit_number = 7; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y4_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a7 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[7]~102_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081; -// synopsys translate_on - -// Location: M9K_X33_Y7_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a15 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[7]~102_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N14 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]) # -// ((\ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & -// (\ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6 .lut_mask = 16'hBA98; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y4_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a31 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[7]~102_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a31_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_first_bit_number = 7; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N4 -cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7 ( -// Equation(s): -// \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6_combout & -// ((\ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout )))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6_combout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout ), - .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6_combout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ), - .cin(gnd), - .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout ), - .cout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7 .lut_mask = 16'hF858; -defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y24_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a15 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(gnd), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[7]~102_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_first_bit_number = 7; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y30_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a15 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h3C0000000000000000000000000000000000000000000000000000000000000080000000000002000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFB91060128E2D09899B4D10A148392808351AD282E76190E029FDC286449331D89080802222C0D04D1121484041D21084C223B0A12EBE72083D81421B93CA9589A04864A853089602E536320C2A5944831907110C246020089C76EE701A4E23964C6586008731635460418000008202040C300110000FCE7E12403749F8C6AB8F69167210EF8A4B8228710884C5C47A9986E8840C02862C088C36E19CF1D315; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h03020CCE064769B15020A6030880234C64E9BEF8E98A81489083A026140D648906E5AD6C882882990A40D293FED064710CB226CDA0330D7B189B344442EC35E3763C75FA1DB107B865E5B8F7B95E77F222244C6BDC1879C0562EF779BE0009465775469089F04C623E19317B486F653C1C22CA642CD685C10EE47EDD66C8C226C7C57F084106FB3B8B1E47463C0088D11104F23C180222A0AA22A22882A202A00000000288964258156302504F5F660C054DEDCA20CC201A4074192601E376C9596CD8B4B568A4DFEF3DBF8027A3422A56A2C003E514582104BF8D6B5D80BB397FBBEC46E8B3CAEBE0100275A1092081D0C1E5716DF09CFEEC00AD800529E1A8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h873CB568FC3F09080F4400DAC600092017210911A6081DCC4979244124815884AE6302C4BE6BA8C22A084803225A0855ABBBC528B1CA2456A4951A53C1209153CFC3000F43632B49C39723270C604B184D1940F1B2A04459BEB088666843BB38C23A8D170CED981891256A2C1D9B31C0F040202103900E6765976089DB8DE16E0001022EC10015E263787F7E581EF83F062200C626EC4E19021840D9C112400C4B987A78AE1BF80005EF370C0739371E0D3E5CF1E3677332370BB98D1831B30F7D8CDC0131C444798F040DC0116E2C4336B0166109A15D1FCC7EDE31EB23862203C11245EE31E38E6DEF2188BE2068F3C716E10317783020D8EF5C256774BA0E; -defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h1B9CE2DA363196DC20007FF5554FC631286DC716B048384C26510685218DF9E6C629E6050C619658692170C1022C2232C965C92C189020C705873084858910322166D72DC524870C422BBFFD4808A7032B088DE3000B853800736C8E9968C19A4B72C08871D2413188E4829219C38C2025920480D64856902E4D4D60B640C833C14D536A45D144B244C24A290076E58CC2E64E4A2DC4C5939C4C2DDBD1B918B231248625B2C0DD0F07A27A111CB80A48808C7C21C205029100010400228BB3BDFF7DCCEF40196C8381658D8840043B119B86A46247665810E2203000141023C366CB633B3376DC625DA8A0856C484392B779E1BA4088EDB4A6CDB9BD46DCC0B2; -// synopsys translate_on - -// Location: M9K_X22_Y2_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a7 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h7C762E21DB2481CB6BB88C68811C76C63B18ECC1BACDC6110DCC70BC20940800C71478E35468600B01A93082C63DD073AE4181844449C08D8D56B0DCC881251C202139803D3000B2E0209DB9101160989A5916381001B0446631006064DB1B996E436E644CF6C8606F124DA230E9B66E2F46BB466E2CE068661B4B05F02F7D00CB3E518948104042F84F1840401018406877D800A00000F5122597005DA4411000800020249004081008924124080114000000020BFFFFEC638C31207B6C321407D901787004001C459326210CCE00C6AF707B84440C313110B8C4D13B2C6E06C4C088B1A9B24BEB0178C4D6C18230DF72B07A28063647CC4721026D8C711864; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h881B30810845E6D18622EC9B6236A000030986A4F0644601226000A2F220D40310438334E51C28000400B18422CA60FC42C9C03F066366ECBBB010B00B004807CC0E00DAEC3000194A52B80C606262092D84A1102410000001400010002000800200080020000800200008000800400040002004000040002000020002000801000010004002001000200008000AEE708008880C86112251B45B36C0048833B319B4C2CE6660D2C0619246C4B208BC0AD00202001E104FC30911410804201E92102B400E8004C40AD6E4614466308ABC7165AA57060A3A736A188ABB300200A10BB04344008422327B1393C43396A931B8C8C87227A6141C0E2DCC76D830B082; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h101CC0024A6C32005CCB31908842211604D8B326101118B54B188CB4D502F5F02DA65C2472B824F109BC594C2401209C01A0E59830002C73B396C6015B85A163184B56183004204267600220A061A004893E1D609106BDBB553920A011AA5AE581E08228382D54C2989BC59535528176240438C9AA757917F95C7428981A26470D1C3E528444D9B00E561C40973AE1806031C464834F03D34A11233A34B34A1D1A55A50C3384B549B64C381920140D4008004020B119D5834C10064000006001169808000200040100000002F8986E37654DDFF88E20860382DC089D4C239F6E4C3C8D784218667F524CE209881213DC91099C14744901620044C802DA414966; -defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h84724A241226DB4809C9A1100DE6A63984D651A2624A09420496DDC12CC10964B6E370363701B41848117683379C8422106D001BB41FB8248067301E1002C636A276585D5273AC87206840415DA74B4E9D213CAE3234B308E19608AA38250844883838649E1442A0D983F4A9094A5AD4A52D56C5D80CAC58D9645944A230091549F30426B100842A12B25160D6D991E6C8C81AFB4C644004C2140A342020D84C9001624489A10045D16C944B02763FF55405E400BADFE5BFFFFFF00000000011042250089108884888410924041204444209102084241104204108824114455292225124929249248894408541300A6DB00791E5B12FEF24037181F1901B007B; -// synopsys translate_on - -// Location: M9K_X33_Y26_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a7 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[7]~102_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_first_bit_number = 7; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h000000000000000000000000FFFFFFFFC0810207C0001A176020155177486D89000000000000000000000000FFFFFFFF80000003C0000217724019F17748EDC900000000000000000000000000000001BF7EFDF9400406B17A400BF57748AD81000000000000000000000000000000013F7EFDF940041EB1724218157749A7910000000000000000000000003F7EFDF90000000140042AF97B426C157DC9B7590000000000000000000000003F7EFDF90000000140042069600246057DC95351000000000000000000000000408102053FFFFFF95FE4084175C246896009F35100000000000000000000000040810207BFFFFFFF7FE4147177C2004960291759; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h7FE8374958F827C15FF88F91E9A80DC3629A9FC172033EC170FB0E8173F792815FE826E158F805C95FF8AF8169A80DC3629A1EC17B033BC1706B3E8173FFB0C1400826E558F805C15DF8AF9169A82DD163C21BC17B133BC1716B3781723F14C1400826E958D825815DD8AF8168482DC161229BC17A133FC171AB3781723F16E9400826E95818058179582F9160480FC162229FC17ACA39C172FB3F8152CF10A1400826E958180D8179580F05614C0DC162329BC171EB398173537F8152E310D1400826E158180D81F8580FD1612C0F41631293C173BB398D63037F81D22313D1400827E958080F01F8188FCB60A40F41435083C1723B198161834F01D67300E3; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'hD4FB0D2352268F0151E680016803440977EDE98148F31101BFFFFFFF4081010750FB094B52728F0151FEC0016C034C0153EDA90148F31F013FFFFFFB4081010152F3096156DA8901503ED2016C03480173FDA00148F11F01000000013F7EFEF952E3017156DA85015022C2016C034C0153FCA00148F10F01000000013F7EFEF956B3A9115052850543C2C2116C014D2153FDA12148D11F013F7EFEF900000001469F8B3150728D0143C05A016D014C81537DA00148D11E01BF7EFEF900000001528F8F2156628D0140004E016F054481513DA181C8513E0580000007FFFFFFFF528E8B2156E28C0148024E0167676C415139B041C8513E07C0810107FFFFFFFF; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N18 -cycloneive_lcell_comb \Mux0~0 ( -// Equation(s): -// \Mux0~0_combout = (\z80_|address_pins_|abus[14]~23_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout )))) # (!\z80_|address_pins_|abus[14]~23_combout & -// (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ))) - - .dataa(\z80_|address_pins_|abus[14]~23_combout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout ), - .cin(gnd), - .combout(\Mux0~0_combout ), - .cout()); -// synopsys translate_off -defparam \Mux0~0 .lut_mask = 16'hBA98; -defparam \Mux0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N12 -cycloneive_lcell_comb \Mux0~1 ( -// Equation(s): -// \Mux0~1_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\Mux0~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout )) # (!\Mux0~0_combout & -// ((\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ))))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\Mux0~0_combout )))) - - .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ), - .datad(\Mux0~0_combout ), - .cin(gnd), - .combout(\Mux0~1_combout ), - .cout()); -// synopsys translate_off -defparam \Mux0~1 .lut_mask = 16'hBBC0; -defparam \Mux0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N22 -cycloneive_lcell_comb \D[7]~112 ( -// Equation(s): -// \D[7]~112_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\Mux0~1_combout ))) -// # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout )))) - - .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout ), - .datad(\Mux0~1_combout ), - .cin(gnd), - .combout(\D[7]~112_combout ), - .cout()); -// synopsys translate_off -defparam \D[7]~112 .lut_mask = 16'hF4B0; -defparam \D[7]~112 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N30 -cycloneive_lcell_comb \D[7]~94 ( -// Equation(s): -// \D[7]~94_combout = (\D[5]~84_combout & (\D[7]~112_combout & ((\z80_|data_pins_|dout [7]) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) # (!\D[5]~84_combout & ((\z80_|data_pins_|dout [7]) # ((!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) - - .dataa(\D[5]~84_combout ), - .datab(\z80_|data_pins_|dout [7]), - .datac(\D[7]~112_combout ), - .datad(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .cin(gnd), - .combout(\D[7]~94_combout ), - .cout()); -// synopsys translate_off -defparam \D[7]~94 .lut_mask = 16'hC4F5; -defparam \D[7]~94 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y10_N26 -cycloneive_lcell_comb \D[7]~102 ( -// Equation(s): -// \D[7]~102_combout = (\D[7]~94_combout ) # (!\D[0]~107_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\D[7]~94_combout ), - .datad(\D[0]~107_combout ), - .cin(gnd), - .combout(\D[7]~102_combout ), - .cout()); -// synopsys translate_off -defparam \D[7]~102 .lut_mask = 16'hF0FF; -defparam \D[7]~102 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N26 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [7] = (\D[7]~102_combout & ((\z80_|pin_control_|bus_db_pin_re~combout ) # ((\z80_|bus_control_|db[7]~7_combout & \z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\D[7]~102_combout & (\z80_|bus_control_|db[7]~7_combout -// & ((\z80_|execute_|ctl_bus_db_we~7_combout )))) - - .dataa(\D[7]~102_combout ), - .datab(\z80_|bus_control_|db[7]~7_combout ), - .datac(\z80_|pin_control_|bus_db_pin_re~combout ), - .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [7]), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] .lut_mask = 16'hECA0; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y13_N27 -dffeas \z80_|data_pins_|dout[7] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [7]), - .asdata(vcc), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), - .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|data_pins_|dout [7]), + .q(\z80_|reg_file_|b2v_latch_hl_lo|latch [3]), .prn(vcc)); // synopsys translate_off -defparam \z80_|data_pins_|dout[7] .is_wysiwyg = "true"; -defparam \z80_|data_pins_|dout[7] .power_up = "low"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y13_N2 -cycloneive_lcell_comb \z80_|bus_control_|db[7]~5 ( -// Equation(s): -// \z80_|bus_control_|db[7]~5_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[7]~18_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) - - .dataa(gnd), - .datab(\z80_|alu_control_|db[7]~18_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|bus_control_|db[0]~4_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[7]~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[7]~5 .lut_mask = 16'hCF00; -defparam \z80_|bus_control_|db[7]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y13_N8 -cycloneive_lcell_comb \z80_|bus_control_|db[7]~7 ( -// Equation(s): -// \z80_|bus_control_|db[7]~7_combout = ((\z80_|bus_control_|db[7]~5_combout & ((\z80_|data_pins_|dout [7]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - - .dataa(\z80_|data_pins_|dout [7]), - .datab(\z80_|execute_|ctl_bus_db_oe~combout ), - .datac(\z80_|bus_control_|db[0]~6_combout ), - .datad(\z80_|bus_control_|db[7]~5_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[7]~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[7]~7 .lut_mask = 16'hBF0F; -defparam \z80_|bus_control_|db[7]~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y13_N21 -dffeas \z80_|ir_|opcode[7] ( +// Location: FF_X30_Y12_N29 +dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), - .asdata(\z80_|bus_control_|db[7]~7_combout ), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(vcc), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|ir_|opcode [7]), + .q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]), .prn(vcc)); // synopsys translate_off -defparam \z80_|ir_|opcode[7] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[7] .power_up = "low"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y13_N16 -cycloneive_lcell_comb \z80_|pla_decode_|Equal77~0 ( +// Location: LCCOMB_X30_Y12_N28 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~44 ( // Equation(s): -// \z80_|pla_decode_|Equal77~0_combout = (!\z80_|ir_|opcode [7] & (!\z80_|decode_state_|DFFE_instCB~q & (\z80_|ir_|opcode [6] & !\z80_|decode_state_|DFFE_instED~q ))) +// \z80_|reg_file_|gdfx_temp0[3]~44_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [3] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [3] & +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) - .dataa(\z80_|ir_|opcode [7]), - .datab(\z80_|decode_state_|DFFE_instCB~q ), - .datac(\z80_|ir_|opcode [6]), - .datad(\z80_|decode_state_|DFFE_instED~q ), + .dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [3]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ), + .datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ), .cin(gnd), - .combout(\z80_|pla_decode_|Equal77~0_combout ), + .combout(\z80_|reg_file_|gdfx_temp0[3]~44_combout ), .cout()); // synopsys translate_off -defparam \z80_|pla_decode_|Equal77~0 .lut_mask = 16'h0010; -defparam \z80_|pla_decode_|Equal77~0 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|gdfx_temp0[3]~44 .lut_mask = 16'hA2F3; +defparam \z80_|reg_file_|gdfx_temp0[3]~44 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y17_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~5 ( -// Equation(s): -// \z80_|execute_|ctl_mWrite~5_combout = (\z80_|pla_decode_|Equal77~0_combout & (!\z80_|decode_state_|in_halt~q & (!\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal33~1_combout ))) +// Location: FF_X31_Y11_N21 +dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[3] .power_up = "low"; +// synopsys translate_on - .dataa(\z80_|pla_decode_|Equal77~0_combout ), - .datab(\z80_|decode_state_|in_halt~q ), - .datac(\z80_|decode_state_|use_ixiy~combout ), - .datad(\z80_|pla_decode_|Equal33~1_combout ), +// Location: FF_X31_Y11_N11 +dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N20 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~43 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~43_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [3]), + .datad(\z80_|reg_file_|b2v_latch_de_lo|latch [3]), .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~5_combout ), + .combout(\z80_|reg_file_|gdfx_temp0[3]~43_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~5 .lut_mask = 16'h0200; -defparam \z80_|execute_|ctl_mWrite~5 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|gdfx_temp0[3]~43 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp0[3]~43 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout = (\z80_|pla_decode_|Equal13~0_combout & (\z80_|execute_|ctl_ir_we~4_combout & (\z80_|pla_decode_|Equal8~0_combout & !\z80_|ir_|opcode [3]))) +// Location: FF_X32_Y13_N7 +dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3] .power_up = "low"; +// synopsys translate_on - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|pla_decode_|Equal8~0_combout ), - .datad(\z80_|ir_|opcode [3]), +// Location: FF_X32_Y14_N13 +dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y14_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~46 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~46_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [3] & ((\z80_|alu_control_|db[3]~35_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (((\z80_|alu_control_|db[3]~35_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ), + .datab(\z80_|execute_|ctl_reg_in_lo~8_combout ), + .datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [3]), + .datad(\z80_|alu_control_|db[3]~35_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ), + .combout(\z80_|reg_file_|gdfx_temp0[3]~46_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 .lut_mask = 16'h0080; -defparam \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|gdfx_temp0[3]~46 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[3]~46 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y16_N10 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~3 ( +// Location: LCCOMB_X32_Y13_N6 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~47 ( // Equation(s): -// \z80_|execute_|ctl_bus_db_we~3_combout = (\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # (\z80_|execute_|ctl_iorw~11_combout )))) - - .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), - .datab(\z80_|execute_|ctl_mWrite~5_combout ), - .datac(\z80_|execute_|ctl_iorw~11_combout ), - .datad(\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~3 .lut_mask = 16'hFFA8; -defparam \z80_|execute_|ctl_bus_db_we~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~8 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_we~8_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|M5~q & ((\z80_|execute_|ctl_mRead~10_combout ) # (\z80_|pla_decode_|Equal9~1_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|M5~q ), - .datad(\z80_|pla_decode_|Equal9~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~8 .lut_mask = 16'h3020; -defparam \z80_|execute_|ctl_bus_db_we~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N14 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~2 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_we~2_combout = (\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_mRead~10_combout ) # ((\z80_|pla_decode_|Equal13~2_combout ) # (\z80_|execute_|ctl_mWrite~5_combout )))) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|pla_decode_|Equal13~2_combout ), - .datad(\z80_|execute_|ctl_mWrite~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~2 .lut_mask = 16'hCCC8; -defparam \z80_|execute_|ctl_bus_db_we~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~4 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_we~4_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mWrite~4_combout ) # ((\z80_|pla_decode_|Equal21~0_combout & \z80_|pla_decode_|Equal24~0_combout )))) - - .dataa(\z80_|pla_decode_|Equal21~0_combout ), - .datab(\z80_|execute_|ixy_d~7_combout ), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|pla_decode_|Equal24~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~4 .lut_mask = 16'hC8C0; -defparam \z80_|execute_|ctl_bus_db_we~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N28 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~6 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_we~6_combout = (((\z80_|execute_|ctl_bus_db_we~4_combout ) # (!\z80_|execute_|ctl_sw_2u~3_combout )) # (!\z80_|execute_|ctl_bus_db_we~5_combout )) # (!\z80_|execute_|ctl_apin_mux~0_combout ) - - .dataa(\z80_|execute_|ctl_apin_mux~0_combout ), - .datab(\z80_|execute_|ctl_bus_db_we~5_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~4_combout ), - .datad(\z80_|execute_|ctl_sw_2u~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~6 .lut_mask = 16'hF7FF; -defparam \z80_|execute_|ctl_bus_db_we~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y16_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~7 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_we~7_combout = (\z80_|execute_|ctl_bus_db_we~3_combout ) # ((\z80_|execute_|ctl_bus_db_we~8_combout ) # ((\z80_|execute_|ctl_bus_db_we~2_combout ) # (\z80_|execute_|ctl_bus_db_we~6_combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_we~3_combout ), - .datab(\z80_|execute_|ctl_bus_db_we~8_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~2_combout ), - .datad(\z80_|execute_|ctl_bus_db_we~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_we~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_we~7 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_bus_db_we~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][2]~50 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][2]~50_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [4]) +// \z80_|reg_file_|gdfx_temp0[3]~47_combout = (\z80_|reg_file_|gdfx_temp0[3]~46_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))) .dataa(gnd), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ), + .datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [3]), + .datad(\z80_|reg_file_|gdfx_temp0[3]~46_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][2]~50_combout ), + .combout(\z80_|reg_file_|gdfx_temp0[3]~47_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][2]~50 .lut_mask = 16'h000F; -defparam \ula_|zx_keyboard_|keys[0][2]~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][2]~52 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][2]~52_combout = (\ula_|zx_keyboard_|keys[7][4]~51_combout & ((\ula_|zx_keyboard_|keys[0][2]~50_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[0][2]~50_combout & ((\ula_|zx_keyboard_|keys[0][2]~q -// ))))) # (!\ula_|zx_keyboard_|keys[7][4]~51_combout & (((\ula_|zx_keyboard_|keys[0][2]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[7][4]~51_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[0][2]~q ), - .datad(\ula_|zx_keyboard_|keys[0][2]~50_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][2]~52_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][2]~52 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[0][2]~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y20_N17 -dffeas \ula_|zx_keyboard_|keys[0][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[0][2]~52_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[0][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[0][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][3]~48 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][3]~48_combout = (\ula_|zx_keyboard_|keys[7][4]~19_combout & (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|zx_keyboard_|keys[7][4]~19_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][3]~48_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][3]~48 .lut_mask = 16'h0008; -defparam \ula_|zx_keyboard_|keys[3][3]~48 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][2]~49 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][2]~49_combout = (\ula_|zx_keyboard_|keys[3][3]~48_combout & ((\ula_|zx_keyboard_|keys[6][4]~47_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[6][4]~47_combout & (\ula_|zx_keyboard_|keys[1][2]~q -// )))) # (!\ula_|zx_keyboard_|keys[3][3]~48_combout & (((\ula_|zx_keyboard_|keys[1][2]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[3][3]~48_combout ), - .datab(\ula_|zx_keyboard_|keys[6][4]~47_combout ), - .datac(\ula_|zx_keyboard_|keys[1][2]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][2]~49_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][2]~49 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[1][2]~49 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y20_N23 -dffeas \ula_|zx_keyboard_|keys[1][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[1][2]~49_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[1][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[1][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N22 -cycloneive_lcell_comb \D[2]~35 ( -// Equation(s): -// \D[2]~35_combout = (\z80_|address_pins_|abus[8]~18_combout & (((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][2]~q )))) # (!\z80_|address_pins_|abus[8]~18_combout & (!\ula_|zx_keyboard_|keys[0][2]~q & -// ((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][2]~q )))) - - .dataa(\z80_|address_pins_|abus[8]~18_combout ), - .datab(\ula_|zx_keyboard_|keys[0][2]~q ), - .datac(\ula_|zx_keyboard_|keys[1][2]~q ), - .datad(\z80_|address_pins_|abus[9]~17_combout ), - .cin(gnd), - .combout(\D[2]~35_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~35 .lut_mask = 16'hBB0B; -defparam \D[2]~35 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~57 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][2]~57_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [0]) - - .dataa(gnd), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(gnd), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][2]~57_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][2]~57 .lut_mask = 16'h3300; -defparam \ula_|zx_keyboard_|keys[5][2]~57 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~58 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][2]~58_combout = (\ula_|zx_keyboard_|keys[5][2]~57_combout & ((\ula_|zx_keyboard_|keys[5][2]~33_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[5][2]~33_combout & (\ula_|zx_keyboard_|keys[5][2]~q -// )))) # (!\ula_|zx_keyboard_|keys[5][2]~57_combout & (((\ula_|zx_keyboard_|keys[5][2]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[5][2]~57_combout ), - .datab(\ula_|zx_keyboard_|keys[5][2]~33_combout ), - .datac(\ula_|zx_keyboard_|keys[5][2]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][2]~58_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][2]~58 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[5][2]~58 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y18_N15 -dffeas \ula_|zx_keyboard_|keys[5][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[5][2]~58_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[5][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[5][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~59 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][2]~59_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|zx_keyboard_|extended~q ))) # (!\ula_|ps2_keyboard_|shiftreg [1] & -// (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|zx_keyboard_|extended~q ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|zx_keyboard_|extended~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][2]~59_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][2]~59 .lut_mask = 16'h0420; -defparam \ula_|zx_keyboard_|keys[4][2]~59 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~131 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][2]~131_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|keys[4][2]~59_combout & (\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [0]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|zx_keyboard_|keys[4][2]~59_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][2]~131_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][2]~131 .lut_mask = 16'h0080; -defparam \ula_|zx_keyboard_|keys[4][2]~131 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~60 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][2]~60_combout = (\ula_|zx_keyboard_|keys[4][2]~131_combout & ((\ula_|zx_keyboard_|keys[3][4]~130_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][4]~130_combout & ((\ula_|zx_keyboard_|keys[4][2]~q -// ))))) # (!\ula_|zx_keyboard_|keys[4][2]~131_combout & (((\ula_|zx_keyboard_|keys[4][2]~q )))) - - .dataa(\ula_|zx_keyboard_|released~q ), - .datab(\ula_|zx_keyboard_|keys[4][2]~131_combout ), - .datac(\ula_|zx_keyboard_|keys[4][2]~q ), - .datad(\ula_|zx_keyboard_|keys[3][4]~130_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][2]~60_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][2]~60 .lut_mask = 16'h74F0; -defparam \ula_|zx_keyboard_|keys[4][2]~60 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y18_N15 -dffeas \ula_|zx_keyboard_|keys[4][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[4][2]~60_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[4][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[4][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N4 -cycloneive_lcell_comb \D[2]~37 ( -// Equation(s): -// \D[2]~37_combout = (\z80_|address_pins_|abus[13]~20_combout & (((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][2]~q )))) # (!\z80_|address_pins_|abus[13]~20_combout & (!\ula_|zx_keyboard_|keys[5][2]~q & -// ((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][2]~q )))) - - .dataa(\z80_|address_pins_|abus[13]~20_combout ), - .datab(\ula_|zx_keyboard_|keys[5][2]~q ), - .datac(\ula_|zx_keyboard_|keys[4][2]~q ), - .datad(\z80_|address_pins_|abus[12]~21_combout ), - .cin(gnd), - .combout(\D[2]~37_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~37 .lut_mask = 16'hBB0B; -defparam \D[2]~37 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][2]~53 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][2]~53_combout = (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [4]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [4]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][2]~53_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][2]~53 .lut_mask = 16'h00F0; -defparam \ula_|zx_keyboard_|keys[3][2]~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][2]~55 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][2]~55_combout = (\ula_|zx_keyboard_|keys[7][4]~19_combout & (\ula_|zx_keyboard_|keys[3][2]~53_combout & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|zx_keyboard_|Equal0~2_combout ))) - - .dataa(\ula_|zx_keyboard_|keys[7][4]~19_combout ), - .datab(\ula_|zx_keyboard_|keys[3][2]~53_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|zx_keyboard_|Equal0~2_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][2]~55_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][2]~55 .lut_mask = 16'h0800; -defparam \ula_|zx_keyboard_|keys[2][2]~55 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][2]~56 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][2]~56_combout = (\ula_|zx_keyboard_|keys[2][2]~55_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[2][2]~55_combout & ((\ula_|zx_keyboard_|keys[2][2]~q ))) - - .dataa(gnd), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[2][2]~q ), - .datad(\ula_|zx_keyboard_|keys[2][2]~55_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][2]~56_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][2]~56 .lut_mask = 16'h33F0; -defparam \ula_|zx_keyboard_|keys[2][2]~56 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y20_N27 -dffeas \ula_|zx_keyboard_|keys[2][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[2][2]~56_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[2][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[2][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][2]~54 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][2]~54_combout = (\ula_|zx_keyboard_|keys[7][4]~51_combout & ((\ula_|zx_keyboard_|keys[3][2]~53_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][2]~53_combout & ((\ula_|zx_keyboard_|keys[3][2]~q -// ))))) # (!\ula_|zx_keyboard_|keys[7][4]~51_combout & (((\ula_|zx_keyboard_|keys[3][2]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[7][4]~51_combout ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(\ula_|zx_keyboard_|keys[3][2]~q ), - .datad(\ula_|zx_keyboard_|keys[3][2]~53_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][2]~54_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][2]~54 .lut_mask = 16'h72F0; -defparam \ula_|zx_keyboard_|keys[3][2]~54 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X27_Y20_N29 -dffeas \ula_|zx_keyboard_|keys[3][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[3][2]~54_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[3][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[3][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N8 -cycloneive_lcell_comb \D[2]~36 ( -// Equation(s): -// \D[2]~36_combout = (\ula_|zx_keyboard_|keys[2][2]~q & (\z80_|address_pins_|abus[10]~24_combout & ((\z80_|address_pins_|abus[11]~19_combout ) # (!\ula_|zx_keyboard_|keys[3][2]~q )))) # (!\ula_|zx_keyboard_|keys[2][2]~q & -// (((\z80_|address_pins_|abus[11]~19_combout )) # (!\ula_|zx_keyboard_|keys[3][2]~q ))) - - .dataa(\ula_|zx_keyboard_|keys[2][2]~q ), - .datab(\ula_|zx_keyboard_|keys[3][2]~q ), - .datac(\z80_|address_pins_|abus[10]~24_combout ), - .datad(\z80_|address_pins_|abus[11]~19_combout ), - .cin(gnd), - .combout(\D[2]~36_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~36 .lut_mask = 16'hF531; -defparam \D[2]~36 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~68 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][2]~68_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [1]))) # (!\ula_|ps2_keyboard_|shiftreg [4] & -// (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [1]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][2]~68_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][2]~68 .lut_mask = 16'h0180; -defparam \ula_|zx_keyboard_|keys[6][2]~68 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~69 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][2]~69_combout = (\ula_|zx_keyboard_|keys[6][1]~41_combout & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|zx_keyboard_|keys[6][2]~68_combout )) - - .dataa(\ula_|zx_keyboard_|keys[6][1]~41_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(gnd), - .datad(\ula_|zx_keyboard_|keys[6][2]~68_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][2]~69_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][2]~69 .lut_mask = 16'h2200; -defparam \ula_|zx_keyboard_|keys[6][2]~69 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~70 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[6][2]~70_combout = (\ula_|zx_keyboard_|keys[6][2]~69_combout & (!\ula_|zx_keyboard_|keys[5][0]~67_combout )) # (!\ula_|zx_keyboard_|keys[6][2]~69_combout & ((\ula_|zx_keyboard_|keys[6][2]~q ))) - - .dataa(\ula_|zx_keyboard_|keys[5][0]~67_combout ), - .datab(\ula_|zx_keyboard_|keys[6][2]~69_combout ), - .datac(\ula_|zx_keyboard_|keys[6][2]~q ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][2]~70_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][2]~70 .lut_mask = 16'h7474; -defparam \ula_|zx_keyboard_|keys[6][2]~70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y20_N1 -dffeas \ula_|zx_keyboard_|keys[6][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[6][2]~70_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[6][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[6][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y21_N16 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~61 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~61_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [5]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~61_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~61 .lut_mask = 16'h0F00; -defparam \ula_|zx_keyboard_|keys[7][2]~61 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y21_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~62 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~62_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|zx_keyboard_|keys[7][2]~61_combout & (\ula_|ps2_keyboard_|shiftreg [1] & !\ula_|ps2_keyboard_|shiftreg [0]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [4]), - .datab(\ula_|zx_keyboard_|keys[7][2]~61_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [0]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~62_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~62 .lut_mask = 16'h0080; -defparam \ula_|zx_keyboard_|keys[7][2]~62 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y21_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~64 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~64_combout = (\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[7][2]~62_combout ) # ((\ula_|zx_keyboard_|keys[5][4]~63_combout & \ula_|zx_keyboard_|keys[7][2]~32_combout )))) - - .dataa(\ula_|zx_keyboard_|keys[5][4]~63_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|zx_keyboard_|keys[7][2]~62_combout ), - .datad(\ula_|zx_keyboard_|keys[7][2]~32_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~64_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~64 .lut_mask = 16'hC8C0; -defparam \ula_|zx_keyboard_|keys[7][2]~64 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y21_N14 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~65 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~65_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|zx_keyboard_|extended~q & (\ula_|zx_keyboard_|keys[0][0]~15_combout & \ula_|zx_keyboard_|keys[7][2]~64_combout ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|zx_keyboard_|extended~q ), - .datac(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .datad(\ula_|zx_keyboard_|keys[7][2]~64_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~65_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~65 .lut_mask = 16'h1000; -defparam \ula_|zx_keyboard_|keys[7][2]~65 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|Selector13~0 ( -// Equation(s): -// \ula_|zx_keyboard_|Selector13~0_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & !\ula_|ps2_keyboard_|shiftreg [5])) - - .dataa(\ula_|zx_keyboard_|shifted~q ), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(gnd), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|Selector13~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|Selector13~0 .lut_mask = 16'hFF22; -defparam \ula_|zx_keyboard_|Selector13~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y21_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~66 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][2]~66_combout = (\ula_|zx_keyboard_|keys[7][2]~65_combout & ((!\ula_|zx_keyboard_|Selector13~0_combout ))) # (!\ula_|zx_keyboard_|keys[7][2]~65_combout & (\ula_|zx_keyboard_|keys[7][2]~q )) - - .dataa(\ula_|zx_keyboard_|keys[7][2]~65_combout ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[7][2]~q ), - .datad(\ula_|zx_keyboard_|Selector13~0_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][2]~66_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2]~66 .lut_mask = 16'h50FA; -defparam \ula_|zx_keyboard_|keys[7][2]~66 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y21_N13 -dffeas \ula_|zx_keyboard_|keys[7][2] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[7][2]~66_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[7][2]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][2] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[7][2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y21_N0 -cycloneive_lcell_comb \D[2]~38 ( -// Equation(s): -// \D[2]~38_combout = (\z80_|address_pins_|abus[15]~22_combout & (((\z80_|address_pins_|abus[14]~23_combout )) # (!\ula_|zx_keyboard_|keys[6][2]~q ))) # (!\z80_|address_pins_|abus[15]~22_combout & (!\ula_|zx_keyboard_|keys[7][2]~q & -// ((\z80_|address_pins_|abus[14]~23_combout ) # (!\ula_|zx_keyboard_|keys[6][2]~q )))) - - .dataa(\z80_|address_pins_|abus[15]~22_combout ), - .datab(\ula_|zx_keyboard_|keys[6][2]~q ), - .datac(\z80_|address_pins_|abus[14]~23_combout ), - .datad(\ula_|zx_keyboard_|keys[7][2]~q ), - .cin(gnd), - .combout(\D[2]~38_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~38 .lut_mask = 16'hA2F3; -defparam \D[2]~38 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X27_Y20_N14 -cycloneive_lcell_comb \D[2]~39 ( -// Equation(s): -// \D[2]~39_combout = (\D[2]~35_combout & (\D[2]~37_combout & (\D[2]~36_combout & \D[2]~38_combout ))) - - .dataa(\D[2]~35_combout ), - .datab(\D[2]~37_combout ), - .datac(\D[2]~36_combout ), - .datad(\D[2]~38_combout ), - .cin(gnd), - .combout(\D[2]~39_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~39 .lut_mask = 16'h8000; -defparam \D[2]~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N14 -cycloneive_lcell_comb \D[2]~104 ( -// Equation(s): -// \D[2]~104_combout = ((\z80_|address_pins_|DFFE_apin_latch [0]) # (\D[2]~39_combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - - .dataa(gnd), - .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datac(\z80_|address_pins_|DFFE_apin_latch [0]), - .datad(\D[2]~39_combout ), - .cin(gnd), - .combout(\D[2]~104_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~104 .lut_mask = 16'hFFF3; -defparam \D[2]~104 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y8_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a26 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[2]~46_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_first_bit_number = 2; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y12_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a10 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[2]~46_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X33_Y9_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a18 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[2]~46_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_first_bit_number = 2; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y12_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a2 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[2]~46_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N8 -cycloneive_lcell_comb \D[2]~43 ( -// Equation(s): -// \D[2]~43_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout )))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ), - .cin(gnd), - .combout(\D[2]~43_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~43 .lut_mask = 16'hB9A8; -defparam \D[2]~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N6 -cycloneive_lcell_comb \D[2]~44 ( -// Equation(s): -// \D[2]~44_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[2]~43_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout )) # (!\D[2]~43_combout & -// ((\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ))))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\D[2]~43_combout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ), - .datad(\D[2]~43_combout ), - .cin(gnd), - .combout(\D[2]~44_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~44 .lut_mask = 16'hBBC0; -defparam \D[2]~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y17_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a10 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h8102080042447C443C0C3C402004FC1838787840407A00707C02487E444878428008004042460424402040024A3242124220044022404208520A4A24424A125A0A1028440000524A0A4A4A204A5240460800100010540042002064547E0600001FA9BE02B828694B8A82CB8C8158226808198E9EC6B021F07A2098D5E0ECB639D2B1908129B6A2D646516192D87593189D8B2B26CD6E16234C1CC90AD9831EBD89EAD271ECC39A80507716BB49626B743DFFCF99576C3FAC889860E46618ACB79EC30EEDE42EB1E31F3976CA23243179FAA96DCD66D51535351770D410DC8531866136E6184518410368288C446EC63A4FEE425019C244097049C2B2DC8D93C4; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'hA111466C9493A2A7CA2204102414CC798BF0EEC2995A4814580BD07585585ED92E5172E82E845070000A846100500E84EA1803B8B07B99E1DC75BE6419674597B38F54EB9091AE3320201EE395AD63902282A031CE3E87CC902954AA515D5D6B6A855EC94CFEC4E0172C59A7D054F8F9F4356C312C204E40B05E2059407C8DC84683814663FB910969D1D631A952B381B7F635A33FD38D5CF15DF47D057F7FF555B555C2278100000A24804D7D98EB98602733818A12094F281287422CB40002464C92242004E0AE8518E001D124A7628010115D23C30462FC00A014A12133582A191E00538FC8A5004036A959ACB7A463D23E419EA06B744005385455A71250; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h6C60009CA281AEACDC1762945981B869F93D683EAF4AC7EE52412E85B60B91CD03AD0025F0D509F63202D877ECD8BF8005451F7BD346CF9E17B36F1850A7D80A8CF14A288EAE3BFE00FB2DB45080D4A50C58263A3B398DD51AB9CB554ECAA7B2E73D9D6D2C265859DB844C2C1952AD10241100174FE0444E6707D80A098D8585AAAC4802B74190FB007C0C0206186AFC1B3A2A46864F26118ED1D03ACB1062B7315502751655F60070E6B2C50609369611365AD1E3352327320331A51818030C7D8C4C59396600DC0C420495A0D987501490002BAD38012E20620D556A230B1796450B74E95A860FF3E434C65F1308F16F92395816B914F0CE870C1323347A4E; -defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h7FC8531A7A319F3EBFC1383FFCDB0E09BD288288B078B4AD220B6FA934CF6187D972662C0D31E34E63B31CFC6EB4B35A69B67D85489E62EA99899A94F6800FDBA5D31B86A0288D29CE2EAAFF86A6A9F7000082293E6BB54F06E98ECCB199973EDA00FADB1D3A630BA18050635DE7DCB13B9B86E0CE6E08DC46331A352F716E3C441A0CC068A0823F8668A00621B779DE35FEC004050469F34866AEE766743D8C00FDF3B9F8DE7B76E97F8D32F0F39E4CAC68D9BBB68EA3915F6225F932CAAFDAD6E60DC661155EC9E80F8CEE659F19CC554B2C67C33EDCDA63BAD91B7D1842A7177AF49DF118FE47ACE3344964EBCADCFBB543F7729CCB340866D1157B6CCDDB; -// synopsys translate_on - -// Location: M9K_X33_Y28_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a10 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(\z80_|address_pins_|abus[13]~20_combout ), - .ena1(gnd), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[2]~46_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .clk1_core_clock_enable = "ena1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_first_bit_number = 2; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N12 -cycloneive_lcell_comb \D[2]~40 ( -// Equation(s): -// \D[2]~40_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))) # (!\z80_|address_pins_|abus[14]~23_combout -// & (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ))) - - .dataa(\z80_|address_pins_|abus[14]~23_combout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout ), - .cin(gnd), - .combout(\D[2]~40_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~40 .lut_mask = 16'hEA62; -defparam \D[2]~40 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X33_Y31_N0 -cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a2 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(\CLOCK_50~inputclkctrl_outclk ), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[2]~46_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain({\~GND~combout }), - .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], -\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), - .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus )); -// synopsys translate_off -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file = "ula/test_scr.hex"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mixed_port_feed_through_mode = "dont_care"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "bidir_dual_port"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_in_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clear = "none"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_address = 0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_bit_number = 2; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_last_address = 8191; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_depth = 16384; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_width = 8; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_write_enable_clock = "clock1"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF00000000FFFFFFFFFFFFFFFFFFF68003FFF38003FFF9F403FFF8B003D8F87003FFF8F01BEDFC701FEBFEA01FDBFDC00FDBFDC01FC7FDC0FFC7FDE87FC7FCDC8FC7FCF89FC07071FFC0F873F3E0303FE7FFFFFFFFFFFFFFFF; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000000040078400234B1474928D1000000000000000000000000FFFFFFFF204081024004027153423DA5474928DD000000000000000000000000000000003FFFFFFF40041CB14162378547495999000000000000000000000000000000003FFFFFFF4004189141623485474959F90000000000000000000000003FFFFFFE40000001400400815B6223C15FC913DD0000000000000000000000007FFFFFFE40000001400402E9400333715FC973E5000000000000000000000000604081027FFFFFFD5FE60AE95763353540091361000000000000000000000000400000003FFFFFFC5FE60AE95763081D40011361; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h5FE0236948F816F55FE897C10C28028041DC8DE178059BC16900BB4173E47AC15FE8236148E806F55FE891054CA80E8148288DE179E597C169903AC153F13A8140080365486806D55FE891D548080A8148608FE159E493C16BB03FD152BD1AE14008037D482017D15FE881C548A00AC148E08FE159FC9AC16AA02FC15AAF18F1400083F1482007C15EE882C148E00A4148B08FE148F88D4168E436915ABB01E9400092F9480007815C2882C148E00B6149B49F614868FD41436476814AFA42A1400892FD480807C15C0883C149800FE149DC9FE14A60BD41431C3F914AEA01C1400882F1480817C11C0883C041940FE549CC9EE54860BDC143BC7D8108D2C4D0; -defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h0B928870484885014DE84481680162815375AC0148D308813FFFFFFC400000004B9288314DC0970149FC44856C0166815375AC8140D108817FFFFFFD6040808249D0A2094F908581481C40814C016099417DA88140D10B01400000017FFFFFFE48D083394B9085814A085081440166814179900140510F01400000013FFFFFFE4A508335498001814BE0608146016E8941799041405107413FFFFFFF000000004B98812149C005814BE0628146836E814179100140510F013FFFFFFF000000004B98A1114BE801814A00668147832C814119904140401F4120408082FFFFFFFF48D881154EA801854800768147C22CC14019900100003E0000000000FFFFFFFF; -// synopsys translate_on - -// Location: M9K_X33_Y17_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a2 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h77A47C739FF6A22B8B5CDC49E748E9C739BDE6756DB4D22437E74183E12400CBF7D3C6CC8C7841AB49CC538E8A72F2E73C64D3DF3662B19C07D7D299CBEDEF3E7DA5F4A8458A9451315B681ADA9AB0D63218DFB77D3353C32837E954604B9D98144A4566F47B71715BE6CDB8BA64D536762E9224D70F9A5C374B4D1CAB8DF527027170C5DBCC2B6AD72B8E4CCC94DAA139D8BA64E3384337426E7F274CC88A373AB1F9007B8A7F2936D16274F9BF8B6BABD48FCE74047C1E738C5B303E815BA720C76D6362915156A7671331CE657011862E594E46A6D99392E2D640D766869389A4D43867379AB880C1ACE279E451CB3A9063A0B320F65E536B8EEF9CBB9C76; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h9A2921ED6AA0CC8387B267B9E7A182720833CEE061E6450C8E4A72E3C043F21A0AD007E832124E92429C091D167806C10041AF32DDE13A669990457D098CC2FE3AC884B1E69101135CD080022451F20884CCB9CD203C141402A5AD293C3BABA95ADFAF6726384795A7656B753D2369B9EB5595BAA722012DF8DCFBF15BF46D6EB755D1CBF0DCF6FD40BEEC16EAB4A6D16839C98CBE9DBB437C69FB709F8E79993B9DDFE4F823D6E124B75BCE9B29F799F926619184B6C1178389F07349210436293A130C900FBA4EA70D2BA25B343C5B026D8E8766A4E4267CDAEC99E830D2307D94E6ED80D6722F3989B91E31C63B64C363DCE71A861C14382E270FC02868C7; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h386BA04E797A3F8551DAD9D24A8D259A03ECFF5AB81B1C31DFDAE10100544F8CF1A8CCFC0C7A15BD9E7C2557CB00BF2584E16AAD13D7EDB525A85ABF90C0136DD195D748900C29DF7F381280A9738CDC3BF5BBF937D3A4D99CE2BCCD97CEF2C7F00030AFDB7F22E68CBAA4D9BE7633D3B53E90E4B124422A2A4454BACA5A8DC9352CD1DAFC910CC504334DF9E6F1F4F30161A36293CC5CCF1CA13994ED29D34A5699692496359B8E67A7E74D9A0FC504C8465638CF74A0AF9185921A7D2629893091900604017933442359491FBAB63F346F0C5EC8E3A531984B09E605A30A0627271C28420E47B8DEC74738FC3EDF9FBD40EC09FC7B4D3A1475BE433705FB5F; -defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h973FED2E9BEDBA474B70B121A8D60F3B4EE3F1A238FB3B730EDEEE74EC632DB4D7779D7B79D1C75DF87378E98719C1AF38B1B801C71D180CE86370AE9C2BF38CF84DBBB9878C55457324E92D3DAE91D729AC76BBAD4C6EECA74DAB5EE9A175EE34ABEB9DFAA48538A57E3E5C158947081CA41402E8E65478737F73BB629AAE2EE51D405CAF70F622DD4599602D7910DCAC8214B2A42025110593202C8B164C8DF6369572C3BB8AA1984A8D12F776E224ECEEB21F97FCD6C0CF17A044EC2BBF0571A553CCDD8ABA79BD27B7AF735ED2D34F1EF3A81A160C9ECB1B1FAE6EDEEFF99E28CC30C7C2553DED3378D655AD194B2E6C1BCBED700F6713D960F33E4C361A; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N16 -cycloneive_lcell_comb \D[2]~41 ( -// Equation(s): -// \D[2]~41_combout = (\z80_|address_pins_|abus[15]~22_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout $ (\D[2]~40_combout )))) # (!\z80_|address_pins_|abus[15]~22_combout & -// (\rom|altsyncram_component|auto_generated|ram_block1a2~portadataout & ((!\D[2]~40_combout )))) - - .dataa(\z80_|address_pins_|abus[15]~22_combout ), - .datab(\rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ), - .datad(\D[2]~40_combout ), - .cin(gnd), - .combout(\D[2]~41_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~41 .lut_mask = 16'h0AE4; -defparam \D[2]~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X30_Y14_N30 -cycloneive_lcell_comb \D[2]~42 ( -// Equation(s): -// \D[2]~42_combout = (\D[2]~40_combout & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]) # ((\ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout & !\D[2]~41_combout )))) # (!\D[2]~40_combout & -// (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[2]~41_combout )))) - - .dataa(\D[2]~40_combout ), - .datab(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ), - .datad(\D[2]~41_combout ), - .cin(gnd), - .combout(\D[2]~42_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~42 .lut_mask = 16'h99A8; -defparam \D[2]~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N0 -cycloneive_lcell_comb \D[2]~105 ( -// Equation(s): -// \D[2]~105_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (\D[2]~44_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\D[2]~42_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & -// (\D[2]~44_combout )))) - - .dataa(\D[2]~44_combout ), - .datab(\z80_|address_pins_|DFFE_apin_latch [15]), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\D[2]~42_combout ), - .cin(gnd), - .combout(\D[2]~105_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~105 .lut_mask = 16'hBA8A; -defparam \D[2]~105 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N28 -cycloneive_lcell_comb \D[2]~45 ( -// Equation(s): -// \D[2]~45_combout = ((\Equal2~0_combout & (\D[2]~104_combout )) # (!\Equal2~0_combout & ((\D[2]~105_combout )))) # (!\Equal2~1_combout ) - - .dataa(\Equal2~0_combout ), - .datab(\Equal2~1_combout ), - .datac(\D[2]~104_combout ), - .datad(\D[2]~105_combout ), - .cin(gnd), - .combout(\D[2]~45_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~45 .lut_mask = 16'hF7B3; -defparam \D[2]~45 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|gdfx_temp0[3]~47 .lut_mask = 16'hF300; +defparam \z80_|reg_file_|gdfx_temp0[3]~47 .sum_lutc_input = "datac"; // synopsys translate_on // Location: LCCOMB_X31_Y12_N30 -cycloneive_lcell_comb \D[2]~46 ( +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder ( // Equation(s): -// \D[2]~46_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout & (\z80_|data_pins_|dout [2] & ((\D[2]~45_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\D[2]~45_combout ) # (!\Equal2~1_combout )))) +// \z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp0[3]~52_combout - .dataa(\z80_|data_pins_|dout [2]), - .datab(\Equal2~1_combout ), - .datac(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datad(\D[2]~45_combout ), + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), .cin(gnd), - .combout(\D[2]~46_combout ), + .combout(\z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder_combout ), .cout()); // synopsys translate_off -defparam \D[2]~46 .lut_mask = 16'hAF03; -defparam \D[2]~46 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N2 -cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] ( -// Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [2] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[2]~13_combout ) # ((\z80_|pin_control_|bus_db_pin_re~combout & \D[2]~46_combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & -// (\z80_|pin_control_|bus_db_pin_re~combout & (\D[2]~46_combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(\z80_|pin_control_|bus_db_pin_re~combout ), - .datac(\D[2]~46_combout ), - .datad(\z80_|bus_control_|db[2]~13_combout ), - .cin(gnd), - .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [2]), - .cout()); -// synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] .lut_mask = 16'hEAC0; -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y12_N3 -dffeas \z80_|data_pins_|dout[2] ( - .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [2]), +// Location: FF_X31_Y12_N31 +dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|data_pins_|dout [2]), + .q(\z80_|reg_file_|b2v_latch_iy_lo|latch [3]), .prn(vcc)); // synopsys translate_off -defparam \z80_|data_pins_|dout[2] .is_wysiwyg = "true"; -defparam \z80_|data_pins_|dout[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N18 -cycloneive_lcell_comb \z80_|bus_control_|db[2]~12 ( -// Equation(s): -// \z80_|bus_control_|db[2]~12_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[2]~29_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) - - .dataa(gnd), - .datab(\z80_|alu_control_|db[2]~29_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|bus_control_|db[0]~4_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[2]~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[2]~12 .lut_mask = 16'hCF00; -defparam \z80_|bus_control_|db[2]~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N12 -cycloneive_lcell_comb \z80_|bus_control_|db[2]~13 ( -// Equation(s): -// \z80_|bus_control_|db[2]~13_combout = ((\z80_|bus_control_|db[2]~12_combout & ((\z80_|data_pins_|dout [2]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) - - .dataa(\z80_|data_pins_|dout [2]), - .datab(\z80_|bus_control_|db[0]~6_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~combout ), - .datad(\z80_|bus_control_|db[2]~12_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[2]~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[2]~13 .lut_mask = 16'hBF33; -defparam \z80_|bus_control_|db[2]~13 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[3] .power_up = "low"; // synopsys translate_on // Location: FF_X32_Y12_N13 -dffeas \z80_|ir_|opcode[2] ( +dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[3] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|bus_control_|db[2]~13_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), - .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|ir_|opcode [2]), + .q(\z80_|reg_file_|b2v_latch_sp_lo|latch [3]), .prn(vcc)); // synopsys translate_off -defparam \z80_|ir_|opcode[2] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[2] .power_up = "low"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X38_Y16_N8 -cycloneive_lcell_comb \z80_|pla_decode_|Equal3~1 ( +// Location: LCCOMB_X32_Y12_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~49 ( // Equation(s): -// \z80_|pla_decode_|Equal3~1_combout = (\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [1]) +// \z80_|reg_file_|gdfx_temp0[3]~49_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [3]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_iy_lo|latch [3]), + .datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~49_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~49 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp0[3]~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y11_N27 +dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y11_N12 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp0[3]~52_combout .dataa(gnd), .datab(gnd), - .datac(\z80_|ir_|opcode [2]), - .datad(\z80_|ir_|opcode [1]), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal3~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal3~1 .lut_mask = 16'h00F0; -defparam \z80_|pla_decode_|Equal3~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N26 -cycloneive_lcell_comb \z80_|pla_decode_|Equal43~0 ( -// Equation(s): -// \z80_|pla_decode_|Equal43~0_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal32~0_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal1~7_combout ))) - - .dataa(\z80_|pla_decode_|Equal3~1_combout ), - .datab(\z80_|pla_decode_|Equal32~0_combout ), - .datac(\z80_|ir_|opcode [5]), - .datad(\z80_|pla_decode_|Equal1~7_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal43~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal43~0 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal43~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y17_N24 -cycloneive_lcell_comb \z80_|interrupts_|test1~2 ( -// Equation(s): -// \z80_|interrupts_|test1~2_combout = (!\z80_|pla_decode_|Equal43~0_combout & (!\z80_|pla_decode_|Equal3~2_combout & (!\z80_|pla_decode_|Equal79~0_combout & !\z80_|pla_decode_|Equal36~0_combout ))) - - .dataa(\z80_|pla_decode_|Equal43~0_combout ), - .datab(\z80_|pla_decode_|Equal3~2_combout ), - .datac(\z80_|pla_decode_|Equal79~0_combout ), - .datad(\z80_|pla_decode_|Equal36~0_combout ), - .cin(gnd), - .combout(\z80_|interrupts_|test1~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|interrupts_|test1~2 .lut_mask = 16'h0001; -defparam \z80_|interrupts_|test1~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N26 -cycloneive_lcell_comb \z80_|interrupts_|test1~3 ( -// Equation(s): -// \z80_|interrupts_|test1~3_combout = (!\z80_|execute_|setM1~52_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((\z80_|interrupts_|test1~2_combout ) # (!\z80_|sequencer_|DFFE_T4_ff~q )))) - - .dataa(\z80_|execute_|setM1~52_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|interrupts_|test1~2_combout ), - .cin(gnd), - .combout(\z80_|interrupts_|test1~3_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|interrupts_|test1~3 .lut_mask = 16'h5545; -defparam \z80_|interrupts_|test1~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y15_N13 -dffeas \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|interrupts_|test1~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED .is_wysiwyg = "true"; -defparam \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N2 -cycloneive_lcell_comb \z80_|clk_delay_|SYNTHESIZED_WIRE_4 ( -// Equation(s): -// \z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (!\z80_|sequencer_|DFFE_M1_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|interrupts_|DFFE_inst44~q ))) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_T1_ff~q ), - .datad(\z80_|interrupts_|DFFE_inst44~q ), - .cin(gnd), - .combout(\z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_4 .lut_mask = 16'h0100; -defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X43_Y15_N3 -dffeas \z80_|clk_delay_|SYNTHESIZED_WIRE_7 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_7 .is_wysiwyg = "true"; -defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_7 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y15_N20 -cycloneive_lcell_comb \z80_|clk_delay_|hold_clk_iorq ( -// Equation(s): -// \z80_|clk_delay_|hold_clk_iorq~combout = (!\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q & !\z80_|clk_delay_|DFF_inst5~q ) - - .dataa(gnd), - .datab(\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ), .datac(gnd), - .datad(\z80_|clk_delay_|DFF_inst5~q ), + .datad(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), .cin(gnd), - .combout(\z80_|clk_delay_|hold_clk_iorq~combout ), + .combout(\z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder_combout ), .cout()); // synopsys translate_off -defparam \z80_|clk_delay_|hold_clk_iorq .lut_mask = 16'h0033; -defparam \z80_|clk_delay_|hold_clk_iorq .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y17_N13 -dffeas \z80_|sequencer_|DFFE_T1_ff ( +// Location: FF_X32_Y11_N13 +dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[3] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|ena_M~combout ), + .d(\z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder_combout ), .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|sequencer_|DFFE_T1_ff~q ), + .q(\z80_|reg_file_|b2v_latch_af_lo|latch [3]), .prn(vcc)); // synopsys translate_off -defparam \z80_|sequencer_|DFFE_T1_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_T1_ff .power_up = "low"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y17_N4 -cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_13 ( +// Location: LCCOMB_X32_Y11_N26 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~45 ( // Equation(s): -// \z80_|sequencer_|SYNTHESIZED_WIRE_13~combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|execute_|setM1~52_combout & !\z80_|execute_|nextM~14_combout )) +// \z80_|reg_file_|gdfx_temp0[3]~45_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ))) - .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), - .datab(gnd), - .datac(\z80_|execute_|setM1~52_combout ), - .datad(\z80_|execute_|nextM~14_combout ), + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [3]), + .datad(\z80_|reg_file_|b2v_latch_af_lo|latch [3]), .cin(gnd), - .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ), + .combout(\z80_|reg_file_|gdfx_temp0[3]~45_combout ), .cout()); // synopsys translate_off -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_13 .lut_mask = 16'h0050; -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_13 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|gdfx_temp0[3]~45 .lut_mask = 16'hF531; +defparam \z80_|reg_file_|gdfx_temp0[3]~45 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y17_N5 -dffeas \z80_|sequencer_|DFFE_T2_ff ( +// Location: FF_X32_Y13_N17 +dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[3] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|sequencer_|DFFE_T2_ff~q ), + .q(\z80_|reg_file_|b2v_latch_ix_lo|latch [3]), .prn(vcc)); // synopsys translate_off -defparam \z80_|sequencer_|DFFE_T2_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_T2_ff .power_up = "low"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X35_Y13_N10 -cycloneive_lcell_comb \z80_|resets_|x3 ( -// Equation(s): -// \z80_|resets_|x3~combout = (\z80_|resets_|x1~q ) # ((\z80_|sequencer_|DFFE_T2_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )) +// Location: FF_X32_Y14_N15 +dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_lo|latch [3]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[3] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[3] .power_up = "low"; +// synopsys translate_on - .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), - .datab(gnd), - .datac(\z80_|resets_|x1~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), +// Location: LCCOMB_X32_Y14_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~48 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~48_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (\z80_|reg_file_|b2v_latch_ix_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_ix_lo|latch [3]), + .datac(\z80_|reg_file_|b2v_latch_bc_lo|latch [3]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ), .cin(gnd), - .combout(\z80_|resets_|x3~combout ), + .combout(\z80_|reg_file_|gdfx_temp0[3]~48_combout ), .cout()); // synopsys translate_off -defparam \z80_|resets_|x3 .lut_mask = 16'hF0FA; -defparam \z80_|resets_|x3 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|gdfx_temp0[3]~48 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp0[3]~48 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X35_Y13_N11 -dffeas \z80_|resets_|SYNTHESIZED_WIRE_12 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|resets_|x3~combout ), - .asdata(vcc), - .clrn(\z80_|fpga_reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_12 .is_wysiwyg = "true"; -defparam \z80_|resets_|SYNTHESIZED_WIRE_12 .power_up = "low"; -// synopsys translate_on - -// Location: CLKCTRL_G7 -cycloneive_clkctrl \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl ( - .ena(vcc), - .inclk({vcc,vcc,vcc,\z80_|resets_|SYNTHESIZED_WIRE_12~q }), - .clkselect(2'b00), - .devclrn(devclrn), - .devpor(devpor), - .outclk(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk )); -// synopsys translate_off -defparam \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl .clock_type = "global clock"; -defparam \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl .ena_register_mode = "none"; -// synopsys translate_on - -// Location: FF_X32_Y17_N21 -dffeas \z80_|sequencer_|DFFE_M1_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|DFFE_M1_ff~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|DFFE_M1_ff~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_M1_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_M1_ff .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N10 -cycloneive_lcell_comb \z80_|sequencer_|DFFE_M2_ff~0 ( +// Location: LCCOMB_X32_Y11_N4 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~50 ( // Equation(s): -// \z80_|sequencer_|DFFE_M2_ff~0_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|execute_|nextM~14_combout & (!\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|DFFE_M2_ff~q ))))) +// \z80_|reg_file_|gdfx_temp0[3]~50_combout = (\z80_|reg_file_|gdfx_temp0[3]~47_combout & (\z80_|reg_file_|gdfx_temp0[3]~49_combout & (\z80_|reg_file_|gdfx_temp0[3]~45_combout & \z80_|reg_file_|gdfx_temp0[3]~48_combout ))) - .dataa(\z80_|execute_|setM1~52_combout ), - .datab(\z80_|sequencer_|DFFE_M1_ff~q ), - .datac(\z80_|sequencer_|DFFE_M2_ff~q ), - .datad(\z80_|execute_|nextM~14_combout ), + .dataa(\z80_|reg_file_|gdfx_temp0[3]~47_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[3]~49_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[3]~45_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[3]~48_combout ), .cin(gnd), - .combout(\z80_|sequencer_|DFFE_M2_ff~0_combout ), + .combout(\z80_|reg_file_|gdfx_temp0[3]~50_combout ), .cout()); // synopsys translate_off -defparam \z80_|sequencer_|DFFE_M2_ff~0 .lut_mask = 16'h22A0; -defparam \z80_|sequencer_|DFFE_M2_ff~0 .sum_lutc_input = "datac"; +defparam \z80_|reg_file_|gdfx_temp0[3]~50 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp0[3]~50 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y17_N11 -dffeas \z80_|sequencer_|DFFE_M2_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|DFFE_M2_ff~0_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|DFFE_M2_ff~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_M2_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_M2_ff .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~3 ( +// Location: LCCOMB_X31_Y11_N10 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~51 ( // Equation(s): -// \z80_|execute_|ctl_mWrite~3_combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ) +// \z80_|reg_file_|gdfx_temp0[3]~51_combout = (\z80_|reg_file_|gdfx_temp0[3]~44_combout & (\z80_|reg_file_|gdfx_temp0[3]~43_combout & \z80_|reg_file_|gdfx_temp0[3]~50_combout )) + + .dataa(\z80_|reg_file_|gdfx_temp0[3]~44_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[3]~43_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp0[3]~50_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~51 .lut_mask = 16'h8800; +defparam \z80_|reg_file_|gdfx_temp0[3]~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y11_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~52 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp0[3]~52_combout = ((\z80_|reg_file_|gdfx_temp0[3]~51_combout & ((\z80_|reg_file_|db_lo_as[3]~12_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout ) + + .dataa(\z80_|execute_|ctl_sw_4u~6_combout ), + .datab(\z80_|reg_file_|gdfx_temp0[3]~51_combout ), + .datac(\z80_|reg_file_|db_lo_as[3]~12_combout ), + .datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp0[3]~52 .lut_mask = 16'hC4FF; +defparam \z80_|reg_file_|gdfx_temp0[3]~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N20 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_35 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout = (\z80_|execute_|ctl_flags_bus~combout & ((\z80_|alu_control_|db[3]~35_combout ) # ((\z80_|execute_|ctl_flags_alu~15_combout & \z80_|alu_|db_low[3]~25_combout )))) # (!\z80_|execute_|ctl_flags_bus~combout +// & (((\z80_|execute_|ctl_flags_alu~15_combout & \z80_|alu_|db_low[3]~25_combout )))) + + .dataa(\z80_|execute_|ctl_flags_bus~combout ), + .datab(\z80_|alu_control_|db[3]~35_combout ), + .datac(\z80_|execute_|ctl_flags_alu~15_combout ), + .datad(\z80_|alu_|db_low[3]~25_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_35 .lut_mask = 16'hF888; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~15 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~15_combout = (\z80_|execute_|ctl_state_alu~2_combout & ((\z80_|execute_|ctl_ir_we~12_combout ) # ((\z80_|execute_|ctl_alu_op_low~22_combout & \z80_|pla_decode_|Equal56~0_combout )))) # +// (!\z80_|execute_|ctl_state_alu~2_combout & (\z80_|execute_|ctl_alu_op_low~22_combout & (\z80_|pla_decode_|Equal56~0_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~2_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datac(\z80_|pla_decode_|Equal56~0_combout ), + .datad(\z80_|execute_|ctl_ir_we~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_flags_xy_we~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_flags_xy_we~15 .lut_mask = 16'hEAC0; +defparam \z80_|execute_|ctl_flags_xy_we~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y19_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~16 ( +// Equation(s): +// \z80_|execute_|ctl_flags_xy_we~16_combout = (\z80_|execute_|ctl_flags_xy_we~15_combout ) # ((\z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ) # (!\z80_|execute_|ctl_flags_xy_we~12_combout )) .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|execute_|ctl_flags_xy_we~15_combout ), + .datac(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~12_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~3_combout ), + .combout(\z80_|execute_|ctl_flags_xy_we~16_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~3 .lut_mask = 16'hF000; -defparam \z80_|execute_|ctl_mWrite~3 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_flags_xy_we~16 .lut_mask = 16'hFCFF; +defparam \z80_|execute_|ctl_flags_xy_we~16 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X41_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|nextM~11 ( +// Location: LCCOMB_X28_Y18_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~17 ( // Equation(s): -// \z80_|execute_|nextM~11_combout = ((!\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_alu_op_low~12_combout & !\z80_|execute_|ctl_alu_op_low~11_combout ))) # (!\z80_|execute_|ctl_mWrite~3_combout ) +// \z80_|execute_|ctl_flags_xy_we~17_combout = (\z80_|execute_|ctl_flags_xy_we~16_combout ) # (((!\z80_|execute_|ctl_flags_xy_we~19_combout ) # (!\z80_|execute_|ctl_flags_xy_we~9_combout )) # (!\z80_|execute_|ctl_flags_xy_we~11_combout )) - .dataa(\z80_|execute_|ctl_mWrite~3_combout ), - .datab(\z80_|pla_decode_|Equal56~0_combout ), - .datac(\z80_|execute_|ctl_alu_op_low~12_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~11_combout ), + .dataa(\z80_|execute_|ctl_flags_xy_we~16_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~11_combout ), + .datac(\z80_|execute_|ctl_flags_xy_we~9_combout ), + .datad(\z80_|execute_|ctl_flags_xy_we~19_combout ), .cin(gnd), - .combout(\z80_|execute_|nextM~11_combout ), + .combout(\z80_|execute_|ctl_flags_xy_we~17_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|nextM~11 .lut_mask = 16'h5557; -defparam \z80_|execute_|nextM~11 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_flags_xy_we~17 .lut_mask = 16'hBFFF; +defparam \z80_|execute_|ctl_flags_xy_we~17 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X40_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|nextM~8 ( +// Location: LCCOMB_X28_Y18_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~18 ( // Equation(s): -// \z80_|execute_|nextM~8_combout = (\z80_|alu_control_|flags_cond_true~q & (((\z80_|execute_|ixy_d~8_combout & !\z80_|execute_|ctl_flags_bus~5_combout )))) # (!\z80_|alu_control_|flags_cond_true~q & ((\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout -// ) # ((\z80_|execute_|ixy_d~8_combout & !\z80_|execute_|ctl_flags_bus~5_combout )))) +// \z80_|execute_|ctl_flags_xy_we~18_combout = ((\z80_|execute_|ctl_flags_xy_we~17_combout ) # ((!\z80_|execute_|ctl_flags_pf_we~4_combout ) # (!\z80_|execute_|ctl_pf_sel[0]~3_combout ))) # (!\z80_|execute_|ctl_flags_sz_we~7_combout ) - .dataa(\z80_|alu_control_|flags_cond_true~q ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), - .datac(\z80_|execute_|ixy_d~8_combout ), - .datad(\z80_|execute_|ctl_flags_bus~5_combout ), + .dataa(\z80_|execute_|ctl_flags_sz_we~7_combout ), + .datab(\z80_|execute_|ctl_flags_xy_we~17_combout ), + .datac(\z80_|execute_|ctl_pf_sel[0]~3_combout ), + .datad(\z80_|execute_|ctl_flags_pf_we~4_combout ), .cin(gnd), - .combout(\z80_|execute_|nextM~8_combout ), + .combout(\z80_|execute_|ctl_flags_xy_we~18_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|nextM~8 .lut_mask = 16'h44F4; -defparam \z80_|execute_|nextM~8 .sum_lutc_input = "datac"; +defparam \z80_|execute_|ctl_flags_xy_we~18 .lut_mask = 16'hDFFF; +defparam \z80_|execute_|ctl_flags_xy_we~18 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y13_N4 -cycloneive_lcell_comb \z80_|execute_|nextM~9 ( -// Equation(s): -// \z80_|execute_|nextM~9_combout = (\z80_|execute_|ctl_mWrite~2_combout & (\z80_|pla_decode_|Equal55~0_combout & ((\z80_|execute_|ctl_mRead~11_combout ) # (\z80_|execute_|ixy_d~6_combout )))) - - .dataa(\z80_|execute_|ctl_mWrite~2_combout ), - .datab(\z80_|pla_decode_|Equal55~0_combout ), - .datac(\z80_|execute_|ctl_mRead~11_combout ), - .datad(\z80_|execute_|ixy_d~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~9 .lut_mask = 16'h8880; -defparam \z80_|execute_|nextM~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N8 -cycloneive_lcell_comb \z80_|execute_|nextM~10 ( -// Equation(s): -// \z80_|execute_|nextM~10_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ) # ((\z80_|execute_|nextM~9_combout ) # ((\z80_|execute_|ctl_mRead~36_combout & \z80_|execute_|ixy_d~9_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .datab(\z80_|execute_|nextM~9_combout ), - .datac(\z80_|execute_|ctl_mRead~36_combout ), - .datad(\z80_|execute_|ixy_d~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~10 .lut_mask = 16'hFEEE; -defparam \z80_|execute_|nextM~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N6 -cycloneive_lcell_comb \z80_|execute_|nextM~12 ( -// Equation(s): -// \z80_|execute_|nextM~12_combout = ((\z80_|execute_|nextM~8_combout ) # ((\z80_|execute_|nextM~10_combout ) # (\z80_|execute_|ctl_alu_op_low~32_combout ))) # (!\z80_|execute_|nextM~11_combout ) - - .dataa(\z80_|execute_|nextM~11_combout ), - .datab(\z80_|execute_|nextM~8_combout ), - .datac(\z80_|execute_|nextM~10_combout ), - .datad(\z80_|execute_|ctl_alu_op_low~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~12 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|nextM~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N22 -cycloneive_lcell_comb \z80_|execute_|nextM~15 ( -// Equation(s): -// \z80_|execute_|nextM~15_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & ((\z80_|execute_|ctl_mRead~7_combout ) # (!\z80_|execute_|fMRead~10_combout )))) - - .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), - .datab(\z80_|execute_|ctl_mRead~7_combout ), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|execute_|fMRead~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~15_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~15 .lut_mask = 16'h80A0; -defparam \z80_|execute_|nextM~15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N8 -cycloneive_lcell_comb \z80_|execute_|nextM~6 ( -// Equation(s): -// \z80_|execute_|nextM~6_combout = (((\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal49~0_combout )) # (!\z80_|execute_|nextM~3_combout )) # (!\z80_|execute_|ixy_d~17_combout ) - - .dataa(\z80_|execute_|ixy_d~17_combout ), - .datab(\z80_|decode_state_|use_ixiy~combout ), - .datac(\z80_|execute_|nextM~3_combout ), - .datad(\z80_|pla_decode_|Equal49~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~6 .lut_mask = 16'hDF5F; -defparam \z80_|execute_|nextM~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y18_N6 -cycloneive_lcell_comb \z80_|execute_|nextM~7 ( -// Equation(s): -// \z80_|execute_|nextM~7_combout = ((\z80_|execute_|nextM~6_combout & ((\z80_|execute_|ixy_d~8_combout ) # (\z80_|execute_|ctl_state_alu~4_combout )))) # (!\z80_|execute_|nextM~4_combout ) - - .dataa(\z80_|execute_|ixy_d~8_combout ), - .datab(\z80_|execute_|nextM~6_combout ), - .datac(\z80_|execute_|ctl_state_alu~4_combout ), - .datad(\z80_|execute_|nextM~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~7 .lut_mask = 16'hC8FF; -defparam \z80_|execute_|nextM~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N6 -cycloneive_lcell_comb \z80_|execute_|nextM~13 ( -// Equation(s): -// \z80_|execute_|nextM~13_combout = (\z80_|execute_|nextM~12_combout ) # ((\z80_|execute_|nextM~15_combout ) # (\z80_|execute_|nextM~7_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|nextM~12_combout ), - .datac(\z80_|execute_|nextM~15_combout ), - .datad(\z80_|execute_|nextM~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~13 .lut_mask = 16'hFFFC; -defparam \z80_|execute_|nextM~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N12 -cycloneive_lcell_comb \z80_|execute_|setM1~39 ( -// Equation(s): -// \z80_|execute_|setM1~39_combout = (!\z80_|execute_|ctl_mWrite~5_combout & \z80_|execute_|setM1~38_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_mWrite~5_combout ), - .datad(\z80_|execute_|setM1~38_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~39_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~39 .lut_mask = 16'h0F00; -defparam \z80_|execute_|setM1~39 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N6 -cycloneive_lcell_comb \z80_|execute_|nextM~5 ( -// Equation(s): -// \z80_|execute_|nextM~5_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (((!\z80_|execute_|setM1~45_combout ) # (!\z80_|execute_|nextM~2_combout )) # (!\z80_|execute_|setM1~39_combout ))) - - .dataa(\z80_|execute_|setM1~39_combout ), - .datab(\z80_|execute_|ctl_eval_cond~0_combout ), - .datac(\z80_|execute_|nextM~2_combout ), - .datad(\z80_|execute_|setM1~45_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~5 .lut_mask = 16'h4CCC; -defparam \z80_|execute_|nextM~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X43_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|nextM~14 ( -// Equation(s): -// \z80_|execute_|nextM~14_combout = (\z80_|execute_|nextM~13_combout ) # (((\z80_|execute_|nextM~5_combout ) # (!\z80_|execute_|ctl_mRead~30_combout )) # (!\z80_|execute_|ctl_mWrite~13_combout )) - - .dataa(\z80_|execute_|nextM~13_combout ), - .datab(\z80_|execute_|ctl_mWrite~13_combout ), - .datac(\z80_|execute_|ctl_mRead~30_combout ), - .datad(\z80_|execute_|nextM~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|nextM~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|nextM~14 .lut_mask = 16'hFFBF; -defparam \z80_|execute_|nextM~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N14 -cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_15 ( -// Equation(s): -// \z80_|sequencer_|SYNTHESIZED_WIRE_15~combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|execute_|setM1~52_combout & !\z80_|execute_|nextM~14_combout )) - - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T3_ff~q ), - .datac(\z80_|execute_|setM1~52_combout ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_15 .lut_mask = 16'h00C0; -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_15 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y17_N15 -dffeas \z80_|sequencer_|DFFE_T4_ff ( +// Location: FF_X31_Y15_N21 +dffeas \z80_|alu_flags_|flags_xf ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ), + .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ), .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .ena(\z80_|execute_|ctl_flags_xy_we~18_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|sequencer_|DFFE_T4_ff~q ), + .q(\z80_|alu_flags_|flags_xf~q ), .prn(vcc)); // synopsys translate_off -defparam \z80_|sequencer_|DFFE_T4_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_T4_ff .power_up = "low"; +defparam \z80_|alu_flags_|flags_xf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|flags_xf .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y17_N18 -cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_16 ( +// Location: LCCOMB_X31_Y15_N30 +cycloneive_lcell_comb \z80_|alu_control_|db[3]~33 ( // Equation(s): -// \z80_|sequencer_|SYNTHESIZED_WIRE_16~combout = (\z80_|execute_|setM1~52_combout & (\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|execute_|nextM~14_combout )) - - .dataa(\z80_|execute_|setM1~52_combout ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T4_ff~q ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_16 .lut_mask = 16'h00A0; -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y17_N19 -dffeas \z80_|sequencer_|DFFE_T5_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|DFFE_T5_ff~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_T5_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_T5_ff .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N26 -cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_17 ( -// Equation(s): -// \z80_|sequencer_|SYNTHESIZED_WIRE_17~combout = (\z80_|sequencer_|DFFE_T5_ff~q & (\z80_|execute_|setM1~52_combout & !\z80_|execute_|nextM~14_combout )) +// \z80_|alu_control_|db[3]~33_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & ((\z80_|alu_flags_|flags_xf~q ) # (!\z80_|execute_|ctl_flags_oe~2_combout ))) .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T5_ff~q ), - .datac(\z80_|execute_|setM1~52_combout ), - .datad(\z80_|execute_|nextM~14_combout ), + .datab(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .datac(\z80_|execute_|ctl_flags_oe~2_combout ), + .datad(\z80_|alu_flags_|flags_xf~q ), .cin(gnd), - .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_17~combout ), + .combout(\z80_|alu_control_|db[3]~33_combout ), .cout()); // synopsys translate_off -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_17 .lut_mask = 16'h00C0; -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_17 .sum_lutc_input = "datac"; +defparam \z80_|alu_control_|db[3]~33 .lut_mask = 16'hCC0C; +defparam \z80_|alu_control_|db[3]~33 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y17_N27 -dffeas \z80_|sequencer_|T6 ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|SYNTHESIZED_WIRE_17~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|T6~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|T6 .is_wysiwyg = "true"; -defparam \z80_|sequencer_|T6 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N20 -cycloneive_lcell_comb \z80_|execute_|setM1~13 ( +// Location: LCCOMB_X31_Y14_N20 +cycloneive_lcell_comb \z80_|sw1_|db_down[3]~2 ( // Equation(s): -// \z80_|execute_|setM1~13_combout = (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|pla_decode_|Equal33~0_combout & ((!\z80_|pla_decode_|Equal32~0_combout ) # (!\z80_|pla_decode_|Equal21~2_combout )))) # (!\z80_|pla_decode_|Equal13~0_combout & -// (((!\z80_|pla_decode_|Equal32~0_combout )) # (!\z80_|pla_decode_|Equal21~2_combout ))) +// \z80_|sw1_|db_down[3]~2_combout = (\z80_|bus_control_|db[3]~21_combout ) # ((\z80_|execute_|ctl_sw_1d~6_combout & ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|execute_|ctl_66_oe~2_combout )))) - .dataa(\z80_|pla_decode_|Equal13~0_combout ), - .datab(\z80_|pla_decode_|Equal21~2_combout ), - .datac(\z80_|pla_decode_|Equal32~0_combout ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~13_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~13 .lut_mask = 16'h153F; -defparam \z80_|execute_|setM1~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y17_N4 -cycloneive_lcell_comb \z80_|pla_decode_|Equal77~1 ( -// Equation(s): -// \z80_|pla_decode_|Equal77~1_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal21~0_combout & (\z80_|pla_decode_|Equal77~0_combout & \z80_|pla_decode_|Equal33~0_combout ))) - - .dataa(\z80_|ir_|opcode [5]), - .datab(\z80_|pla_decode_|Equal21~0_combout ), - .datac(\z80_|pla_decode_|Equal77~0_combout ), - .datad(\z80_|pla_decode_|Equal33~0_combout ), - .cin(gnd), - .combout(\z80_|pla_decode_|Equal77~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|pla_decode_|Equal77~1 .lut_mask = 16'h8000; -defparam \z80_|pla_decode_|Equal77~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N2 -cycloneive_lcell_comb \z80_|execute_|setM1~12 ( -// Equation(s): -// \z80_|execute_|setM1~12_combout = (!\z80_|pla_decode_|Equal77~1_combout & (!\z80_|execute_|ctl_alu_oe~3_combout & (!\z80_|pla_decode_|Equal1~6_combout & !\z80_|pla_decode_|Equal2~2_combout ))) - - .dataa(\z80_|pla_decode_|Equal77~1_combout ), - .datab(\z80_|execute_|ctl_alu_oe~3_combout ), - .datac(\z80_|pla_decode_|Equal1~6_combout ), - .datad(\z80_|pla_decode_|Equal2~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~12_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~12 .lut_mask = 16'h0001; -defparam \z80_|execute_|setM1~12 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N18 -cycloneive_lcell_comb \z80_|execute_|setM1~14 ( -// Equation(s): -// \z80_|execute_|setM1~14_combout = (\z80_|execute_|setM1~13_combout & (\z80_|interrupts_|test1~2_combout & \z80_|execute_|setM1~12_combout )) - - .dataa(gnd), - .datab(\z80_|execute_|setM1~13_combout ), - .datac(\z80_|interrupts_|test1~2_combout ), - .datad(\z80_|execute_|setM1~12_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~14_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~14 .lut_mask = 16'hC000; -defparam \z80_|execute_|setM1~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y16_N24 -cycloneive_lcell_comb \z80_|execute_|setM1~41 ( -// Equation(s): -// \z80_|execute_|setM1~41_combout = (!\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_mWrite~4_combout & !\z80_|execute_|ctl_ir_we~10_combout )) - - .dataa(\z80_|execute_|ctl_ir_we~9_combout ), - .datab(gnd), - .datac(\z80_|execute_|ctl_mWrite~4_combout ), - .datad(\z80_|execute_|ctl_ir_we~10_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~41_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~41 .lut_mask = 16'h0005; -defparam \z80_|execute_|setM1~41 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N18 -cycloneive_lcell_comb \z80_|execute_|setM1~42 ( -// Equation(s): -// \z80_|execute_|setM1~42_combout = (!\z80_|pla_decode_|Equal38~2_combout & (!\z80_|pla_decode_|Equal37~0_combout & (!\z80_|pla_decode_|Equal47~0_combout & \z80_|sequencer_|DFFE_T4_ff~q ))) - - .dataa(\z80_|pla_decode_|Equal38~2_combout ), - .datab(\z80_|pla_decode_|Equal37~0_combout ), - .datac(\z80_|pla_decode_|Equal47~0_combout ), - .datad(\z80_|sequencer_|DFFE_T4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~42_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~42 .lut_mask = 16'h0100; -defparam \z80_|execute_|setM1~42 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y15_N24 -cycloneive_lcell_comb \z80_|execute_|setM1~43 ( -// Equation(s): -// \z80_|execute_|setM1~43_combout = (!\z80_|pla_decode_|Equal21~1_combout & (\z80_|execute_|setM1~41_combout & (!\z80_|pla_decode_|Equal48~0_combout & \z80_|execute_|setM1~42_combout ))) - - .dataa(\z80_|pla_decode_|Equal21~1_combout ), - .datab(\z80_|execute_|setM1~41_combout ), - .datac(\z80_|pla_decode_|Equal48~0_combout ), - .datad(\z80_|execute_|setM1~42_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~43_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~43 .lut_mask = 16'h0400; -defparam \z80_|execute_|setM1~43 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N26 -cycloneive_lcell_comb \z80_|execute_|setM1~44 ( -// Equation(s): -// \z80_|execute_|setM1~44_combout = (\z80_|execute_|setM1~43_combout & (\z80_|execute_|setM1~40_combout & ((!\z80_|pla_decode_|Equal2~1_combout ) # (!\z80_|pla_decode_|Equal1~4_combout )))) - - .dataa(\z80_|execute_|setM1~43_combout ), - .datab(\z80_|pla_decode_|Equal1~4_combout ), - .datac(\z80_|execute_|setM1~40_combout ), - .datad(\z80_|pla_decode_|Equal2~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~44_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~44 .lut_mask = 16'h20A0; -defparam \z80_|execute_|setM1~44 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N20 -cycloneive_lcell_comb \z80_|execute_|setM1~50 ( -// Equation(s): -// \z80_|execute_|setM1~50_combout = (\z80_|execute_|setM1~46_combout & (\z80_|execute_|setM1~14_combout & (\z80_|execute_|setM1~44_combout & \z80_|execute_|setM1~49_combout ))) - - .dataa(\z80_|execute_|setM1~46_combout ), - .datab(\z80_|execute_|setM1~14_combout ), - .datac(\z80_|execute_|setM1~44_combout ), - .datad(\z80_|execute_|setM1~49_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~50_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~50 .lut_mask = 16'h8000; -defparam \z80_|execute_|setM1~50 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|setM1~51 ( -// Equation(s): -// \z80_|execute_|setM1~51_combout = (\z80_|sequencer_|T6~q & (((\z80_|execute_|setM1~50_combout & \z80_|execute_|setM1~39_combout )) # (!\z80_|execute_|setM1~40_combout ))) # (!\z80_|sequencer_|T6~q & (\z80_|execute_|setM1~50_combout & -// ((\z80_|execute_|setM1~39_combout )))) - - .dataa(\z80_|sequencer_|T6~q ), - .datab(\z80_|execute_|setM1~50_combout ), - .datac(\z80_|execute_|setM1~40_combout ), - .datad(\z80_|execute_|setM1~39_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~51_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~51 .lut_mask = 16'hCE0A; -defparam \z80_|execute_|setM1~51 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N2 -cycloneive_lcell_comb \z80_|execute_|setM1~6 ( -// Equation(s): -// \z80_|execute_|setM1~6_combout = (\z80_|execute_|ctl_al_we~13_combout & (\z80_|sequencer_|M5~q & (\z80_|pla_decode_|Equal9~1_combout ))) # (!\z80_|execute_|ctl_al_we~13_combout & ((\z80_|sequencer_|DFFE_M4_ff~q ) # ((\z80_|sequencer_|M5~q & -// \z80_|pla_decode_|Equal9~1_combout )))) - - .dataa(\z80_|execute_|ctl_al_we~13_combout ), - .datab(\z80_|sequencer_|M5~q ), - .datac(\z80_|pla_decode_|Equal9~1_combout ), - .datad(\z80_|sequencer_|DFFE_M4_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~6 .lut_mask = 16'hD5C0; -defparam \z80_|execute_|setM1~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N12 -cycloneive_lcell_comb \z80_|execute_|setM1~7 ( -// Equation(s): -// \z80_|execute_|setM1~7_combout = ((\z80_|sequencer_|DFFE_T5_ff~q & \z80_|execute_|setM1~6_combout )) # (!\z80_|execute_|ctl_flags_xy_we~16_combout ) - - .dataa(gnd), - .datab(\z80_|execute_|ctl_flags_xy_we~16_combout ), - .datac(\z80_|sequencer_|DFFE_T5_ff~q ), - .datad(\z80_|execute_|setM1~6_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~7_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~7 .lut_mask = 16'hF333; -defparam \z80_|execute_|setM1~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N0 -cycloneive_lcell_comb \z80_|execute_|setM1~8 ( -// Equation(s): -// \z80_|execute_|setM1~8_combout = (\z80_|execute_|ctl_mWrite~4_combout ) # ((\z80_|execute_|ctl_mRead~7_combout ) # ((\z80_|pla_decode_|Equal6~1_combout ) # (!\z80_|execute_|fMWrite~3_combout ))) - - .dataa(\z80_|execute_|ctl_mWrite~4_combout ), - .datab(\z80_|execute_|ctl_mRead~7_combout ), - .datac(\z80_|pla_decode_|Equal6~1_combout ), - .datad(\z80_|execute_|fMWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~8_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~8 .lut_mask = 16'hFEFF; -defparam \z80_|execute_|setM1~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y16_N10 -cycloneive_lcell_comb \z80_|execute_|setM1~9 ( -// Equation(s): -// \z80_|execute_|setM1~9_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ) # ((!\z80_|ir_|opcode [4] & (!\z80_|ir_|opcode [2] & \z80_|execute_|ctl_mWrite~2_combout ))) - - .dataa(\z80_|ir_|opcode [4]), - .datab(\z80_|ir_|opcode [2]), - .datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .datad(\z80_|execute_|ctl_mWrite~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~9_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~9 .lut_mask = 16'hF1F0; -defparam \z80_|execute_|setM1~9 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N10 -cycloneive_lcell_comb \z80_|execute_|setM1~10 ( -// Equation(s): -// \z80_|execute_|setM1~10_combout = ((\z80_|execute_|setM1~8_combout ) # ((\z80_|execute_|ctl_mWrite~16_combout & \z80_|execute_|setM1~9_combout ))) # (!\z80_|execute_|nextM~2_combout ) - - .dataa(\z80_|execute_|ctl_mWrite~16_combout ), - .datab(\z80_|execute_|nextM~2_combout ), - .datac(\z80_|execute_|setM1~8_combout ), - .datad(\z80_|execute_|setM1~9_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~10_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~10 .lut_mask = 16'hFBF3; -defparam \z80_|execute_|setM1~10 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y17_N26 -cycloneive_lcell_comb \z80_|execute_|setM1~11 ( -// Equation(s): -// \z80_|execute_|setM1~11_combout = (\z80_|execute_|setM1~7_combout ) # (((\z80_|execute_|ixy_d~6_combout & \z80_|execute_|setM1~10_combout )) # (!\z80_|reg_control_|reg_sel_pc~3_combout )) - - .dataa(\z80_|execute_|setM1~7_combout ), - .datab(\z80_|execute_|ixy_d~6_combout ), - .datac(\z80_|execute_|setM1~10_combout ), - .datad(\z80_|reg_control_|reg_sel_pc~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~11_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~11 .lut_mask = 16'hEAFF; -defparam \z80_|execute_|setM1~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N14 -cycloneive_lcell_comb \z80_|execute_|setM1~17 ( -// Equation(s): -// \z80_|execute_|setM1~17_combout = ((\z80_|execute_|setM1~11_combout ) # ((!\z80_|execute_|setM1~14_combout & \z80_|execute_|ctl_eval_cond~0_combout ))) # (!\z80_|execute_|setM1~16_combout ) - - .dataa(\z80_|execute_|setM1~16_combout ), - .datab(\z80_|execute_|setM1~14_combout ), - .datac(\z80_|execute_|ctl_eval_cond~0_combout ), - .datad(\z80_|execute_|setM1~11_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~17_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~17 .lut_mask = 16'hFF75; -defparam \z80_|execute_|setM1~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y16_N16 -cycloneive_lcell_comb \z80_|execute_|setM1~31 ( -// Equation(s): -// \z80_|execute_|setM1~31_combout = (\z80_|pla_decode_|Equal35~0_combout & ((\z80_|execute_|ixy_d~6_combout ) # ((\z80_|execute_|ctl_reg_in_hi~2_combout & \z80_|execute_|ctl_mRead~18_combout )))) # (!\z80_|pla_decode_|Equal35~0_combout & -// (\z80_|execute_|ctl_reg_in_hi~2_combout & ((\z80_|execute_|ctl_mRead~18_combout )))) - - .dataa(\z80_|pla_decode_|Equal35~0_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datac(\z80_|execute_|ixy_d~6_combout ), - .datad(\z80_|execute_|ctl_mRead~18_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~31_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~31 .lut_mask = 16'hECA0; -defparam \z80_|execute_|setM1~31 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y18_N2 -cycloneive_lcell_comb \z80_|execute_|setM1~28 ( -// Equation(s): -// \z80_|execute_|setM1~28_combout = ((\z80_|execute_|ctl_mRead~9_combout ) # ((\z80_|execute_|ctl_mRead~15_combout ) # (\z80_|execute_|ctl_mRead~7_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ) - - .dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), - .datab(\z80_|execute_|ctl_mRead~9_combout ), - .datac(\z80_|execute_|ctl_mRead~15_combout ), - .datad(\z80_|execute_|ctl_mRead~7_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~28_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~28 .lut_mask = 16'hFFFD; -defparam \z80_|execute_|setM1~28 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N0 -cycloneive_lcell_comb \z80_|execute_|setM1~30 ( -// Equation(s): -// \z80_|execute_|setM1~30_combout = (((\z80_|execute_|ctl_state_alu~6_combout & \z80_|execute_|setM1~28_combout )) # (!\z80_|execute_|setM1~29_combout )) # (!\z80_|execute_|setM1~54_combout ) - - .dataa(\z80_|execute_|setM1~54_combout ), - .datab(\z80_|execute_|setM1~29_combout ), - .datac(\z80_|execute_|ctl_state_alu~6_combout ), - .datad(\z80_|execute_|setM1~28_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~30_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~30 .lut_mask = 16'hF777; -defparam \z80_|execute_|setM1~30 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N10 -cycloneive_lcell_comb \z80_|execute_|setM1~32 ( -// Equation(s): -// \z80_|execute_|setM1~32_combout = (\z80_|execute_|ctl_mRead~5_combout ) # ((\z80_|execute_|ctl_mRead~4_combout ) # ((\z80_|execute_|setM1~9_combout & \z80_|execute_|ctl_mRead~36_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~5_combout ), - .datab(\z80_|execute_|setM1~9_combout ), - .datac(\z80_|execute_|ctl_mRead~36_combout ), - .datad(\z80_|execute_|ctl_mRead~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~32_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~32 .lut_mask = 16'hFFEA; -defparam \z80_|execute_|setM1~32 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y16_N8 -cycloneive_lcell_comb \z80_|execute_|setM1~33 ( -// Equation(s): -// \z80_|execute_|setM1~33_combout = (\z80_|execute_|setM1~31_combout ) # ((\z80_|execute_|setM1~30_combout ) # ((\z80_|execute_|ixy_d~9_combout & \z80_|execute_|setM1~32_combout ))) - - .dataa(\z80_|execute_|setM1~31_combout ), - .datab(\z80_|execute_|setM1~30_combout ), - .datac(\z80_|execute_|ixy_d~9_combout ), - .datad(\z80_|execute_|setM1~32_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~33_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~33 .lut_mask = 16'hFEEE; -defparam \z80_|execute_|setM1~33 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N10 -cycloneive_lcell_comb \z80_|execute_|setM1~25 ( -// Equation(s): -// \z80_|execute_|setM1~25_combout = ((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & \z80_|pla_decode_|Equal21~1_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ) - - .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .datab(gnd), - .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ), - .datad(\z80_|pla_decode_|Equal21~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~25_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~25 .lut_mask = 16'hAF0F; -defparam \z80_|execute_|setM1~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|setM1~26 ( -// Equation(s): -// \z80_|execute_|setM1~26_combout = ((\z80_|execute_|ctl_mRead~13_combout ) # ((!\z80_|alu_control_|flags_cond_true~q & \z80_|pla_decode_|Equal40~1_combout ))) # (!\z80_|execute_|ctl_bus_inc_oe~29_combout ) - - .dataa(\z80_|execute_|ctl_bus_inc_oe~29_combout ), - .datab(\z80_|alu_control_|flags_cond_true~q ), - .datac(\z80_|execute_|ctl_mRead~13_combout ), - .datad(\z80_|pla_decode_|Equal40~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~26_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~26 .lut_mask = 16'hF7F5; -defparam \z80_|execute_|setM1~26 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y13_N0 -cycloneive_lcell_comb \z80_|execute_|setM1~24 ( -// Equation(s): -// \z80_|execute_|setM1~24_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & (((\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & !\z80_|alu_control_|flags_cond_true~q )) # (!\z80_|execute_|ctl_mRead~12_combout ))) # -// (!\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & (\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & ((!\z80_|alu_control_|flags_cond_true~q )))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), - .datab(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), - .datac(\z80_|execute_|ctl_mRead~12_combout ), - .datad(\z80_|alu_control_|flags_cond_true~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~24_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~24 .lut_mask = 16'h0ACE; -defparam \z80_|execute_|setM1~24 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N18 -cycloneive_lcell_comb \z80_|execute_|setM1~27 ( -// Equation(s): -// \z80_|execute_|setM1~27_combout = (\z80_|execute_|setM1~24_combout ) # ((\z80_|execute_|ctl_state_alu~4_combout & ((\z80_|execute_|setM1~25_combout ) # (\z80_|execute_|setM1~26_combout )))) - - .dataa(\z80_|execute_|setM1~25_combout ), - .datab(\z80_|execute_|setM1~26_combout ), - .datac(\z80_|execute_|setM1~24_combout ), - .datad(\z80_|execute_|ctl_state_alu~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~27_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~27 .lut_mask = 16'hFEF0; -defparam \z80_|execute_|setM1~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N6 -cycloneive_lcell_comb \z80_|execute_|setM1~22 ( -// Equation(s): -// \z80_|execute_|setM1~22_combout = (!\z80_|execute_|ctl_mRead~10_combout & (\z80_|execute_|fMWrite~9_combout & (!\z80_|execute_|ctl_mRead~8_combout & \z80_|execute_|fMWrite~3_combout ))) - - .dataa(\z80_|execute_|ctl_mRead~10_combout ), - .datab(\z80_|execute_|fMWrite~9_combout ), - .datac(\z80_|execute_|ctl_mRead~8_combout ), - .datad(\z80_|execute_|fMWrite~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~22_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~22 .lut_mask = 16'h0400; -defparam \z80_|execute_|setM1~22 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y19_N26 -cycloneive_lcell_comb \z80_|execute_|setM1~21 ( -// Equation(s): -// \z80_|execute_|setM1~21_combout = (\z80_|decode_state_|DFFE_instNonRep~q ) # ((!\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [4] & \z80_|execute_|ctl_mWrite~2_combout ))) - - .dataa(\z80_|ir_|opcode [2]), - .datab(\z80_|ir_|opcode [4]), - .datac(\z80_|decode_state_|DFFE_instNonRep~q ), - .datad(\z80_|execute_|ctl_mWrite~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~21_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~21 .lut_mask = 16'hF1F0; -defparam \z80_|execute_|setM1~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N2 -cycloneive_lcell_comb \z80_|execute_|setM1~53 ( -// Equation(s): -// \z80_|execute_|setM1~53_combout = (\z80_|sequencer_|DFFE_T5_ff~q & ((\z80_|sequencer_|DFFE_M4_ff~q ) # ((\z80_|execute_|setM1~21_combout & \z80_|sequencer_|DFFE_M3_ff~q )))) - - .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), - .datab(\z80_|sequencer_|DFFE_T5_ff~q ), - .datac(\z80_|execute_|setM1~21_combout ), - .datad(\z80_|sequencer_|DFFE_M3_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~53_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~53 .lut_mask = 16'hC888; -defparam \z80_|execute_|setM1~53 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y17_N4 -cycloneive_lcell_comb \z80_|execute_|setM1~23 ( -// Equation(s): -// \z80_|execute_|setM1~23_combout = (\z80_|execute_|setM1~22_combout & (((!\z80_|execute_|ctl_flags_bus~5_combout & \z80_|execute_|setM1~53_combout )))) # (!\z80_|execute_|setM1~22_combout & ((\z80_|execute_|ctl_reg_in_hi~2_combout ) # -// ((!\z80_|execute_|ctl_flags_bus~5_combout & \z80_|execute_|setM1~53_combout )))) - - .dataa(\z80_|execute_|setM1~22_combout ), - .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), - .datac(\z80_|execute_|ctl_flags_bus~5_combout ), - .datad(\z80_|execute_|setM1~53_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~23_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~23 .lut_mask = 16'h4F44; -defparam \z80_|execute_|setM1~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y16_N6 -cycloneive_lcell_comb \z80_|execute_|setM1~18 ( -// Equation(s): -// \z80_|execute_|setM1~18_combout = (\z80_|execute_|ctl_mRead~11_combout & (((\z80_|pla_decode_|Equal37~0_combout & !\z80_|alu_control_|flags_cond_true~q )) # (!\z80_|execute_|ctl_flags_bus~4_combout ))) - - .dataa(\z80_|pla_decode_|Equal37~0_combout ), - .datab(\z80_|execute_|ctl_mRead~11_combout ), - .datac(\z80_|alu_control_|flags_cond_true~q ), - .datad(\z80_|execute_|ctl_flags_bus~4_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~18_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~18 .lut_mask = 16'h08CC; -defparam \z80_|execute_|setM1~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y15_N28 -cycloneive_lcell_comb \z80_|execute_|setM1~19 ( -// Equation(s): -// \z80_|execute_|setM1~19_combout = (\z80_|execute_|setM1~18_combout ) # ((\z80_|execute_|ixy_d~8_combout & (\z80_|pla_decode_|Equal10~0_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ))) - - .dataa(\z80_|execute_|setM1~18_combout ), - .datab(\z80_|execute_|ixy_d~8_combout ), - .datac(\z80_|pla_decode_|Equal10~0_combout ), - .datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~19_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~19 .lut_mask = 16'hEAAA; -defparam \z80_|execute_|setM1~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N0 -cycloneive_lcell_comb \z80_|execute_|setM1~20 ( -// Equation(s): -// \z80_|execute_|setM1~20_combout = ((\z80_|execute_|setM1~19_combout ) # ((\z80_|execute_|ctl_iorw~11_combout & \z80_|execute_|ctl_mWrite~3_combout ))) # (!\z80_|execute_|ctl_flags_sz_we~0_combout ) - - .dataa(\z80_|execute_|ctl_iorw~11_combout ), - .datab(\z80_|execute_|ctl_mWrite~3_combout ), - .datac(\z80_|execute_|ctl_flags_sz_we~0_combout ), - .datad(\z80_|execute_|setM1~19_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~20_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~20 .lut_mask = 16'hFF8F; -defparam \z80_|execute_|setM1~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y17_N16 -cycloneive_lcell_comb \z80_|execute_|setM1~34 ( -// Equation(s): -// \z80_|execute_|setM1~34_combout = (\z80_|execute_|setM1~33_combout ) # ((\z80_|execute_|setM1~27_combout ) # ((\z80_|execute_|setM1~23_combout ) # (\z80_|execute_|setM1~20_combout ))) - - .dataa(\z80_|execute_|setM1~33_combout ), - .datab(\z80_|execute_|setM1~27_combout ), - .datac(\z80_|execute_|setM1~23_combout ), - .datad(\z80_|execute_|setM1~20_combout ), - .cin(gnd), - .combout(\z80_|execute_|setM1~34_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~34 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|setM1~34 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X41_Y17_N24 -cycloneive_lcell_comb \z80_|execute_|setM1~52 ( -// Equation(s): -// \z80_|execute_|setM1~52_combout = (!\z80_|execute_|setM1~17_combout & (!\z80_|execute_|setM1~34_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|execute_|setM1~51_combout )))) - - .dataa(\z80_|execute_|setM1~51_combout ), - .datab(\z80_|execute_|setM1~17_combout ), - .datac(\z80_|execute_|setM1~34_combout ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|setM1~52_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|setM1~52 .lut_mask = 16'h0301; -defparam \z80_|execute_|setM1~52 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N24 -cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_14 ( -// Equation(s): -// \z80_|sequencer_|SYNTHESIZED_WIRE_14~combout = (\z80_|execute_|setM1~52_combout & (\z80_|sequencer_|DFFE_T2_ff~q & !\z80_|execute_|nextM~14_combout )) - - .dataa(\z80_|execute_|setM1~52_combout ), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T2_ff~q ), - .datad(\z80_|execute_|nextM~14_combout ), - .cin(gnd), - .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_14 .lut_mask = 16'h00A0; -defparam \z80_|sequencer_|SYNTHESIZED_WIRE_14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y17_N25 -dffeas \z80_|sequencer_|DFFE_T3_ff ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|sequencer_|DFFE_T3_ff~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|sequencer_|DFFE_T3_ff .is_wysiwyg = "true"; -defparam \z80_|sequencer_|DFFE_T3_ff .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y15_N12 -cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 ( -// Equation(s): -// \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout = (\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|sequencer_|DFFE_T3_ff~q ), - .datad(\z80_|sequencer_|DFFE_M1_ff~q ), - .cin(gnd), - .combout(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 .lut_mask = 16'h00F0; -defparam \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y15_N24 -cycloneive_lcell_comb \z80_|decode_state_|in_halt~0 ( -// Equation(s): -// \z80_|decode_state_|in_halt~0_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|decode_state_|in_halt~q & !\z80_|interrupts_|DFFE_inst44~q )) - - .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), - .datab(gnd), - .datac(\z80_|decode_state_|in_halt~q ), - .datad(\z80_|interrupts_|DFFE_inst44~q ), - .cin(gnd), - .combout(\z80_|decode_state_|in_halt~0_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|in_halt~0 .lut_mask = 16'h0050; -defparam \z80_|decode_state_|in_halt~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y13_N24 -cycloneive_lcell_comb \z80_|decode_state_|in_halt~1 ( -// Equation(s): -// \z80_|decode_state_|in_halt~1_combout = (\z80_|decode_state_|in_halt~0_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (!\z80_|decode_state_|in_halt~q & \z80_|pla_decode_|Equal77~1_combout ))) - - .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), - .datab(\z80_|decode_state_|in_halt~0_combout ), - .datac(\z80_|decode_state_|in_halt~q ), - .datad(\z80_|pla_decode_|Equal77~1_combout ), - .cin(gnd), - .combout(\z80_|decode_state_|in_halt~1_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|decode_state_|in_halt~1 .lut_mask = 16'hCECC; -defparam \z80_|decode_state_|in_halt~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X35_Y13_N25 -dffeas \z80_|decode_state_|in_halt ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|decode_state_|in_halt~1_combout ), - .asdata(vcc), - .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\z80_|decode_state_|in_halt~q ), - .prn(vcc)); -// synopsys translate_off -defparam \z80_|decode_state_|in_halt .is_wysiwyg = "true"; -defparam \z80_|decode_state_|in_halt .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N26 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~2 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~2_combout = (!\z80_|execute_|ctl_bus_zero_oe~0_combout & (!\z80_|execute_|ctl_bus_ff_oe~1_combout & ((\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) # (!\z80_|decode_state_|in_halt~q )))) - - .dataa(\z80_|decode_state_|in_halt~q ), - .datab(\z80_|execute_|ctl_bus_zero_oe~0_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datad(\z80_|execute_|ctl_bus_ff_oe~1_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~2_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~2 .lut_mask = 16'h0031; -defparam \z80_|execute_|ctl_bus_db_oe~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N18 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~5 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~5_combout = (\z80_|execute_|ctl_ir_we~8_combout ) # ((\z80_|execute_|ctl_ir_we~14_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout ) # (\z80_|pla_decode_|Equal41~2_combout ))) - - .dataa(\z80_|execute_|ctl_ir_we~8_combout ), - .datab(\z80_|execute_|ctl_ir_we~14_combout ), - .datac(\z80_|execute_|ctl_ir_we~11_combout ), - .datad(\z80_|pla_decode_|Equal41~2_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~5_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~5 .lut_mask = 16'hFFFE; -defparam \z80_|execute_|ctl_bus_db_oe~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X35_Y12_N4 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~6 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~6_combout = ((\z80_|execute_|ctl_66_oe~2_combout ) # ((\z80_|execute_|ctl_ir_we~4_combout & \z80_|execute_|ctl_bus_db_oe~5_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) - - .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), - .datab(\z80_|execute_|ctl_ir_we~4_combout ), - .datac(\z80_|execute_|ctl_66_oe~2_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~5_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~6 .lut_mask = 16'hFDF5; -defparam \z80_|execute_|ctl_bus_db_oe~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~4 ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~4_combout = (!\z80_|execute_|ctl_bus_db_oe~3_combout ) # (!\z80_|execute_|ctl_bus_db_oe~0_combout ) - - .dataa(gnd), - .datab(gnd), - .datac(\z80_|execute_|ctl_bus_db_oe~0_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~3_combout ), - .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~4_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe~4 .lut_mask = 16'h0FFF; -defparam \z80_|execute_|ctl_bus_db_oe~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y12_N22 -cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe ( -// Equation(s): -// \z80_|execute_|ctl_bus_db_oe~combout = (\z80_|execute_|ctl_bus_db_oe~2_combout & (((\z80_|execute_|ctl_bus_db_oe~6_combout ) # (\z80_|execute_|ctl_bus_db_oe~4_combout )) # (!\z80_|execute_|ctl_sw_1d~6_combout ))) - - .dataa(\z80_|execute_|ctl_bus_db_oe~2_combout ), + .dataa(\z80_|execute_|ctl_66_oe~2_combout ), .datab(\z80_|execute_|ctl_sw_1d~6_combout ), - .datac(\z80_|execute_|ctl_bus_db_oe~6_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~4_combout ), + .datac(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datad(\z80_|bus_control_|db[3]~21_combout ), .cin(gnd), - .combout(\z80_|execute_|ctl_bus_db_oe~combout ), + .combout(\z80_|sw1_|db_down[3]~2_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_bus_db_oe .lut_mask = 16'hAAA2; -defparam \z80_|execute_|ctl_bus_db_oe .sum_lutc_input = "datac"; +defparam \z80_|sw1_|db_down[3]~2 .lut_mask = 16'hFFC4; +defparam \z80_|sw1_|db_down[3]~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N28 -cycloneive_lcell_comb \z80_|bus_control_|db[0]~6 ( +// Location: LCCOMB_X31_Y14_N6 +cycloneive_lcell_comb \z80_|alu_control_|db[3]~34 ( // Equation(s): -// \z80_|bus_control_|db[0]~6_combout = (\z80_|execute_|ctl_bus_db_oe~combout ) # ((\z80_|execute_|ctl_bus_db_we~7_combout ) # (!\z80_|execute_|ctl_bus_db_oe~2_combout )) +// \z80_|alu_control_|db[3]~34_combout = (\z80_|alu_control_|db[3]~33_combout & (\z80_|sw1_|db_down[3]~2_combout & ((\z80_|reg_file_|gdfx_temp0[3]~52_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) - .dataa(\z80_|execute_|ctl_bus_db_oe~combout ), + .dataa(\z80_|reg_file_|gdfx_temp0[3]~52_combout ), + .datab(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .datac(\z80_|alu_control_|db[3]~33_combout ), + .datad(\z80_|sw1_|db_down[3]~2_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[3]~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[3]~34 .lut_mask = 16'hB000; +defparam \z80_|alu_control_|db[3]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N0 +cycloneive_lcell_comb \z80_|alu_control_|db[3]~35 ( +// Equation(s): +// \z80_|alu_control_|db[3]~35_combout = ((\z80_|alu_control_|db[3]~34_combout & ((\z80_|alu_|db[3]~20_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) + + .dataa(\z80_|alu_control_|db[3]~34_combout ), + .datab(\z80_|execute_|ctl_sw_2u~7_combout ), + .datac(\z80_|alu_|db[3]~20_combout ), + .datad(\z80_|alu_control_|db[6]~11_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[3]~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[3]~35 .lut_mask = 16'hA2FF; +defparam \z80_|alu_control_|db[3]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][0]~75 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][0]~75_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [1])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), .datab(gnd), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|execute_|ctl_bus_db_oe~2_combout ), - .cin(gnd), - .combout(\z80_|bus_control_|db[0]~6_combout ), - .cout()); -// synopsys translate_off -defparam \z80_|bus_control_|db[0]~6 .lut_mask = 16'hFAFF; -defparam \z80_|bus_control_|db[0]~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][3]~93 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][3]~93_combout = (\ula_|zx_keyboard_|keys[7][4]~19_combout & (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[6][4]~47_combout ))) - - .dataa(\ula_|zx_keyboard_|keys[7][4]~19_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [5]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|keys[6][4]~47_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][3]~93_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][3]~93 .lut_mask = 16'h0800; -defparam \ula_|zx_keyboard_|keys[1][3]~93 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][3]~94 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[1][3]~94_combout = (\ula_|zx_keyboard_|keys[1][3]~93_combout & ((\ula_|ps2_keyboard_|shiftreg [3] & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[1][3]~q )))) # -// (!\ula_|zx_keyboard_|keys[1][3]~93_combout & (((\ula_|zx_keyboard_|keys[1][3]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[1][3]~93_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|zx_keyboard_|keys[1][3]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[1][3]~94_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][3]~94 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[1][3]~94 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y19_N31 -dffeas \ula_|zx_keyboard_|keys[1][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[1][3]~94_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[1][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[1][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[1][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y18_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][3]~96 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[0][3]~96_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [1]))) # (!\ula_|ps2_keyboard_|shiftreg [3] & -// (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), .datad(\ula_|ps2_keyboard_|shiftreg [1]), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][3]~96_combout ), + .combout(\ula_|zx_keyboard_|keys[3][0]~75_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][3]~96 .lut_mask = 16'h0810; -defparam \ula_|zx_keyboard_|keys[0][3]~96 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[3][0]~75 .lut_mask = 16'h0500; +defparam \ula_|zx_keyboard_|keys[3][0]~75 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y18_N0 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][3]~98 ( +// Location: LCCOMB_X27_Y8_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|Selector5~0 ( // Equation(s): -// \ula_|zx_keyboard_|keys[0][3]~98_combout = (\ula_|zx_keyboard_|keys[0][3]~96_combout & ((\ula_|zx_keyboard_|keys[0][4]~97_combout & ((!\ula_|zx_keyboard_|keys[2][4]~95_combout ))) # (!\ula_|zx_keyboard_|keys[0][4]~97_combout & -// (\ula_|zx_keyboard_|keys[0][3]~q )))) # (!\ula_|zx_keyboard_|keys[0][3]~96_combout & (((\ula_|zx_keyboard_|keys[0][3]~q )))) +// \ula_|zx_keyboard_|Selector5~0_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|keys[3][0]~75_combout & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [6]))) - .dataa(\ula_|zx_keyboard_|keys[0][3]~96_combout ), - .datab(\ula_|zx_keyboard_|keys[0][4]~97_combout ), - .datac(\ula_|zx_keyboard_|keys[0][3]~q ), - .datad(\ula_|zx_keyboard_|keys[2][4]~95_combout ), + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|zx_keyboard_|keys[3][0]~75_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[0][3]~98_combout ), + .combout(\ula_|zx_keyboard_|Selector5~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][3]~98 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[0][3]~98 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|Selector5~0 .lut_mask = 16'h0400; +defparam \ula_|zx_keyboard_|Selector5~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X29_Y18_N1 -dffeas \ula_|zx_keyboard_|keys[0][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[0][3]~98_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[0][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[0][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[0][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N4 -cycloneive_lcell_comb \D[3]~65 ( +// Location: LCCOMB_X26_Y10_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|Selector5~1 ( // Equation(s): -// \D[3]~65_combout = (\z80_|address_pins_|abus[9]~17_combout & ((\z80_|address_pins_|abus[8]~18_combout ) # ((!\ula_|zx_keyboard_|keys[0][3]~q )))) # (!\z80_|address_pins_|abus[9]~17_combout & (!\ula_|zx_keyboard_|keys[1][3]~q & -// ((\z80_|address_pins_|abus[8]~18_combout ) # (!\ula_|zx_keyboard_|keys[0][3]~q )))) - - .dataa(\z80_|address_pins_|abus[9]~17_combout ), - .datab(\z80_|address_pins_|abus[8]~18_combout ), - .datac(\ula_|zx_keyboard_|keys[1][3]~q ), - .datad(\ula_|zx_keyboard_|keys[0][3]~q ), - .cin(gnd), - .combout(\D[3]~65_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~65 .lut_mask = 16'h8CAF; -defparam \D[3]~65 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][3]~99 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][3]~99_combout = (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [2])) +// \ula_|zx_keyboard_|Selector5~1_combout = (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [2]))) .dataa(\ula_|ps2_keyboard_|shiftreg [1]), .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [2]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][3]~99_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][3]~99 .lut_mask = 16'h4040; -defparam \ula_|zx_keyboard_|keys[3][3]~99 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y20_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][3]~100 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[3][3]~100_combout = (\ula_|zx_keyboard_|keys[3][3]~48_combout & ((\ula_|zx_keyboard_|keys[3][3]~99_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[3][3]~99_combout & (\ula_|zx_keyboard_|keys[3][3]~q -// )))) # (!\ula_|zx_keyboard_|keys[3][3]~48_combout & (((\ula_|zx_keyboard_|keys[3][3]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[3][3]~48_combout ), - .datab(\ula_|zx_keyboard_|keys[3][3]~99_combout ), - .datac(\ula_|zx_keyboard_|keys[3][3]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[3][3]~100_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][3]~100 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[3][3]~100 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y20_N9 -dffeas \ula_|zx_keyboard_|keys[3][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[3][3]~100_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[3][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[3][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[3][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~101 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][3]~101_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & !\ula_|ps2_keyboard_|shiftreg [2])) - - .dataa(\ula_|zx_keyboard_|shifted~q ), - .datab(\ula_|zx_keyboard_|released~q ), - .datac(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), .datad(\ula_|ps2_keyboard_|shiftreg [2]), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][3]~101_combout ), + .combout(\ula_|zx_keyboard_|Selector5~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][3]~101 .lut_mask = 16'hCCDD; -defparam \ula_|zx_keyboard_|keys[2][3]~101 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|Selector5~1 .lut_mask = 16'h4000; +defparam \ula_|zx_keyboard_|Selector5~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y18_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~102 ( +// Location: LCCOMB_X27_Y8_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~132 ( // Equation(s): -// \ula_|zx_keyboard_|keys[2][3]~102_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [2]))) # (!\ula_|ps2_keyboard_|shiftreg [3] & -// (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [2]))) +// \ula_|zx_keyboard_|keys[4][3]~132_combout = (\ula_|zx_keyboard_|Selector5~0_combout ) # ((\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|zx_keyboard_|Selector5~1_combout ))) - .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .dataa(\ula_|zx_keyboard_|Selector5~0_combout ), .datab(\ula_|ps2_keyboard_|shiftreg [5]), .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|zx_keyboard_|Selector5~1_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][3]~102_combout ), + .combout(\ula_|zx_keyboard_|keys[4][3]~132_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][3]~102 .lut_mask = 16'h0810; -defparam \ula_|zx_keyboard_|keys[2][3]~102 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[4][3]~132 .lut_mask = 16'hAEAA; +defparam \ula_|zx_keyboard_|keys[4][3]~132 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y18_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~133 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][3]~133_combout = (\ula_|zx_keyboard_|keys[5][1]~36_combout & (\ula_|zx_keyboard_|keys[2][3]~102_combout & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1]))) - - .dataa(\ula_|zx_keyboard_|keys[5][1]~36_combout ), - .datab(\ula_|zx_keyboard_|keys[2][3]~102_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(\ula_|ps2_keyboard_|shiftreg [1]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][3]~133_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][3]~133 .lut_mask = 16'h0080; -defparam \ula_|zx_keyboard_|keys[2][3]~133 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y18_N2 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~103 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[2][3]~103_combout = (\ula_|zx_keyboard_|keys[2][3]~133_combout & (!\ula_|zx_keyboard_|keys[2][3]~101_combout )) # (!\ula_|zx_keyboard_|keys[2][3]~133_combout & ((\ula_|zx_keyboard_|keys[2][3]~q ))) - - .dataa(\ula_|zx_keyboard_|keys[2][3]~101_combout ), - .datab(gnd), - .datac(\ula_|zx_keyboard_|keys[2][3]~q ), - .datad(\ula_|zx_keyboard_|keys[2][3]~133_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[2][3]~103_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][3]~103 .lut_mask = 16'h55F0; -defparam \ula_|zx_keyboard_|keys[2][3]~103 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X28_Y18_N3 -dffeas \ula_|zx_keyboard_|keys[2][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[2][3]~103_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[2][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[2][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[2][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y20_N28 -cycloneive_lcell_comb \D[3]~66 ( -// Equation(s): -// \D[3]~66_combout = (\z80_|address_pins_|abus[11]~19_combout & (((\z80_|address_pins_|abus[10]~24_combout ) # (!\ula_|zx_keyboard_|keys[2][3]~q )))) # (!\z80_|address_pins_|abus[11]~19_combout & (!\ula_|zx_keyboard_|keys[3][3]~q & -// ((\z80_|address_pins_|abus[10]~24_combout ) # (!\ula_|zx_keyboard_|keys[2][3]~q )))) - - .dataa(\z80_|address_pins_|abus[11]~19_combout ), - .datab(\ula_|zx_keyboard_|keys[3][3]~q ), - .datac(\z80_|address_pins_|abus[10]~24_combout ), - .datad(\ula_|zx_keyboard_|keys[2][3]~q ), - .cin(gnd), - .combout(\D[3]~66_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~66 .lut_mask = 16'hB0BB; -defparam \D[3]~66 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N12 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][3]~104 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][3]~104_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [0])) - - .dataa(\ula_|ps2_keyboard_|shiftreg [5]), - .datab(\ula_|ps2_keyboard_|shiftreg [3]), - .datac(\ula_|ps2_keyboard_|shiftreg [0]), - .datad(gnd), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][3]~104_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][3]~104 .lut_mask = 16'h0808; -defparam \ula_|zx_keyboard_|keys[5][3]~104 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y19_N22 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][3]~105 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[5][3]~105_combout = (\ula_|zx_keyboard_|keys[5][3]~104_combout & ((\ula_|zx_keyboard_|keys[1][4]~25_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[1][4]~25_combout & (\ula_|zx_keyboard_|keys[5][3]~q -// )))) # (!\ula_|zx_keyboard_|keys[5][3]~104_combout & (((\ula_|zx_keyboard_|keys[5][3]~q )))) - - .dataa(\ula_|zx_keyboard_|keys[5][3]~104_combout ), - .datab(\ula_|zx_keyboard_|keys[1][4]~25_combout ), - .datac(\ula_|zx_keyboard_|keys[5][3]~q ), - .datad(\ula_|zx_keyboard_|released~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[5][3]~105_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][3]~105 .lut_mask = 16'h70F8; -defparam \ula_|zx_keyboard_|keys[5][3]~105 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X29_Y19_N23 -dffeas \ula_|zx_keyboard_|keys[5][3] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[5][3]~105_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|zx_keyboard_|keys[5][3]~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[5][3] .is_wysiwyg = "true"; -defparam \ula_|zx_keyboard_|keys[5][3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y19_N16 +// Location: LCCOMB_X27_Y8_N10 cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~106 ( // Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~106_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[5][4]~24_combout & (\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|WideOr16~2_combout ))) +// \ula_|zx_keyboard_|keys[4][3]~106_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|WideOr16~2_combout & (\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[5][4]~22_combout ))) .dataa(\ula_|ps2_keyboard_|shiftreg [6]), - .datab(\ula_|zx_keyboard_|keys[5][4]~24_combout ), + .datab(\ula_|zx_keyboard_|WideOr16~2_combout ), .datac(\ula_|ps2_keyboard_|shiftreg [5]), - .datad(\ula_|zx_keyboard_|WideOr16~2_combout ), + .datad(\ula_|zx_keyboard_|keys[5][4]~22_combout ), .cin(gnd), .combout(\ula_|zx_keyboard_|keys[4][3]~106_combout ), .cout()); @@ -52111,110 +41584,59 @@ defparam \ula_|zx_keyboard_|keys[4][3]~106 .lut_mask = 16'h8000; defparam \ula_|zx_keyboard_|keys[4][3]~106 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X27_Y21_N26 -cycloneive_lcell_comb \ula_|zx_keyboard_|Selector5~1 ( -// Equation(s): -// \ula_|zx_keyboard_|Selector5~1_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [3]))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|ps2_keyboard_|shiftreg [0]), - .datac(\ula_|ps2_keyboard_|shiftreg [1]), - .datad(\ula_|ps2_keyboard_|shiftreg [3]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|Selector5~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|Selector5~1 .lut_mask = 16'h0800; -defparam \ula_|zx_keyboard_|Selector5~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y21_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|Selector5~0 ( -// Equation(s): -// \ula_|zx_keyboard_|Selector5~0_combout = (\ula_|zx_keyboard_|keys[3][0]~78_combout & (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [5]))) - - .dataa(\ula_|zx_keyboard_|keys[3][0]~78_combout ), - .datab(\ula_|ps2_keyboard_|shiftreg [2]), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|Selector5~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|Selector5~0 .lut_mask = 16'h0020; -defparam \ula_|zx_keyboard_|Selector5~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y21_N4 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~134 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~134_combout = (\ula_|zx_keyboard_|Selector5~0_combout ) # ((\ula_|zx_keyboard_|Selector5~1_combout & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [5]))) - - .dataa(\ula_|zx_keyboard_|Selector5~1_combout ), - .datab(\ula_|zx_keyboard_|Selector5~0_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [6]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][3]~134_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~134 .lut_mask = 16'hCECC; -defparam \ula_|zx_keyboard_|keys[4][3]~134 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y21_N6 +// Location: LCCOMB_X27_Y8_N26 cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~107 ( // Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~107_combout = (\ula_|zx_keyboard_|extended~q & (\ula_|zx_keyboard_|keys[4][3]~106_combout )) # (!\ula_|zx_keyboard_|extended~q & (((\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[4][3]~134_combout )))) +// \ula_|zx_keyboard_|keys[4][3]~107_combout = (\ula_|zx_keyboard_|extended~q & (((\ula_|zx_keyboard_|keys[4][3]~106_combout )))) # (!\ula_|zx_keyboard_|extended~q & (\ula_|zx_keyboard_|keys[4][3]~132_combout & (\ula_|ps2_keyboard_|shiftreg [4]))) .dataa(\ula_|zx_keyboard_|extended~q ), - .datab(\ula_|zx_keyboard_|keys[4][3]~106_combout ), + .datab(\ula_|zx_keyboard_|keys[4][3]~132_combout ), .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|keys[4][3]~134_combout ), + .datad(\ula_|zx_keyboard_|keys[4][3]~106_combout ), .cin(gnd), .combout(\ula_|zx_keyboard_|keys[4][3]~107_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~107 .lut_mask = 16'hD888; +defparam \ula_|zx_keyboard_|keys[4][3]~107 .lut_mask = 16'hEA40; defparam \ula_|zx_keyboard_|keys[4][3]~107 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y21_N10 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~135 ( +// Location: LCCOMB_X27_Y8_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~133 ( // Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~135_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|shifted~q ))) +// \ula_|zx_keyboard_|keys[4][3]~133_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|shifted~q ))) .dataa(\ula_|zx_keyboard_|extended~q ), .datab(\ula_|zx_keyboard_|released~q ), .datac(\ula_|ps2_keyboard_|shiftreg [5]), .datad(\ula_|zx_keyboard_|shifted~q ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[4][3]~135_combout ), + .combout(\ula_|zx_keyboard_|keys[4][3]~133_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~135 .lut_mask = 16'hCDCC; -defparam \ula_|zx_keyboard_|keys[4][3]~135 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[4][3]~133 .lut_mask = 16'hCDCC; +defparam \ula_|zx_keyboard_|keys[4][3]~133 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y21_N22 +// Location: LCCOMB_X27_Y8_N6 cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~108 ( // Equation(s): -// \ula_|zx_keyboard_|keys[4][3]~108_combout = (\ula_|zx_keyboard_|keys[4][3]~107_combout & ((\ula_|zx_keyboard_|keys[0][0]~15_combout & ((!\ula_|zx_keyboard_|keys[4][3]~135_combout ))) # (!\ula_|zx_keyboard_|keys[0][0]~15_combout & -// (\ula_|zx_keyboard_|keys[4][3]~q )))) # (!\ula_|zx_keyboard_|keys[4][3]~107_combout & (((\ula_|zx_keyboard_|keys[4][3]~q )))) +// \ula_|zx_keyboard_|keys[4][3]~108_combout = (\ula_|zx_keyboard_|keys[4][3]~107_combout & ((\ula_|zx_keyboard_|keys[0][0]~13_combout & (!\ula_|zx_keyboard_|keys[4][3]~133_combout )) # (!\ula_|zx_keyboard_|keys[0][0]~13_combout & +// ((\ula_|zx_keyboard_|keys[4][3]~q ))))) # (!\ula_|zx_keyboard_|keys[4][3]~107_combout & (((\ula_|zx_keyboard_|keys[4][3]~q )))) .dataa(\ula_|zx_keyboard_|keys[4][3]~107_combout ), - .datab(\ula_|zx_keyboard_|keys[0][0]~15_combout ), + .datab(\ula_|zx_keyboard_|keys[4][3]~133_combout ), .datac(\ula_|zx_keyboard_|keys[4][3]~q ), - .datad(\ula_|zx_keyboard_|keys[4][3]~135_combout ), + .datad(\ula_|zx_keyboard_|keys[0][0]~13_combout ), .cin(gnd), .combout(\ula_|zx_keyboard_|keys[4][3]~108_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[4][3]~108 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[4][3]~108 .lut_mask = 16'h72F0; defparam \ula_|zx_keyboard_|keys[4][3]~108 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y21_N23 +// Location: FF_X27_Y8_N7 dffeas \ula_|zx_keyboard_|keys[4][3] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\ula_|zx_keyboard_|keys[4][3]~108_combout ), @@ -52233,79 +41655,555 @@ defparam \ula_|zx_keyboard_|keys[4][3] .is_wysiwyg = "true"; defparam \ula_|zx_keyboard_|keys[4][3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y19_N20 -cycloneive_lcell_comb \D[3]~67 ( +// Location: LCCOMB_X28_Y7_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][3]~104 ( // Equation(s): -// \D[3]~67_combout = (\ula_|zx_keyboard_|keys[5][3]~q & (\z80_|address_pins_|abus[13]~20_combout & ((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][3]~q )))) # (!\ula_|zx_keyboard_|keys[5][3]~q & -// (((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][3]~q )))) +// \ula_|zx_keyboard_|keys[5][3]~104_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [5])) - .dataa(\ula_|zx_keyboard_|keys[5][3]~q ), - .datab(\z80_|address_pins_|abus[13]~20_combout ), - .datac(\ula_|zx_keyboard_|keys[4][3]~q ), - .datad(\z80_|address_pins_|abus[12]~21_combout ), + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), .cin(gnd), - .combout(\D[3]~67_combout ), + .combout(\ula_|zx_keyboard_|keys[5][3]~104_combout ), .cout()); // synopsys translate_off -defparam \D[3]~67 .lut_mask = 16'hDD0D; -defparam \D[3]~67 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[5][3]~104 .lut_mask = 16'h0A00; +defparam \ula_|zx_keyboard_|keys[5][3]~104 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X27_Y21_N4 +// Location: LCCOMB_X28_Y7_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][3]~105 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][3]~105_combout = (\ula_|zx_keyboard_|keys[1][4]~23_combout & ((\ula_|zx_keyboard_|keys[5][3]~104_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[5][3]~104_combout & ((\ula_|zx_keyboard_|keys[5][3]~q +// ))))) # (!\ula_|zx_keyboard_|keys[1][4]~23_combout & (((\ula_|zx_keyboard_|keys[5][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[1][4]~23_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[5][3]~q ), + .datad(\ula_|zx_keyboard_|keys[5][3]~104_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][3]~105_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][3]~105 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[5][3]~105 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y7_N23 +dffeas \ula_|zx_keyboard_|keys[5][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[5][3]~105_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[5][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[5][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N12 +cycloneive_lcell_comb \D[3]~55 ( +// Equation(s): +// \D[3]~55_combout = (\z80_|address_pins_|abus[12]~21_combout & (((\z80_|address_pins_|abus[13]~20_combout ) # (!\ula_|zx_keyboard_|keys[5][3]~q )))) # (!\z80_|address_pins_|abus[12]~21_combout & (!\ula_|zx_keyboard_|keys[4][3]~q & +// ((\z80_|address_pins_|abus[13]~20_combout ) # (!\ula_|zx_keyboard_|keys[5][3]~q )))) + + .dataa(\z80_|address_pins_|abus[12]~21_combout ), + .datab(\ula_|zx_keyboard_|keys[4][3]~q ), + .datac(\ula_|zx_keyboard_|keys[5][3]~q ), + .datad(\z80_|address_pins_|abus[13]~20_combout ), + .cin(gnd), + .combout(\D[3]~55_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~55 .lut_mask = 16'hBB0B; +defparam \D[3]~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~46 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][4]~46_combout = (\ula_|zx_keyboard_|keys[7][1]~21_combout & (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|zx_keyboard_|keys[7][1]~21_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][4]~46_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][4]~46 .lut_mask = 16'h0200; +defparam \ula_|zx_keyboard_|keys[6][4]~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~62 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][4]~62_combout = (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][4]~62_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][4]~62 .lut_mask = 16'h00F0; +defparam \ula_|zx_keyboard_|keys[5][4]~62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][3]~102 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][3]~102_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|zx_keyboard_|keys[6][4]~46_combout & (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|zx_keyboard_|keys[5][4]~62_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|zx_keyboard_|keys[6][4]~46_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|zx_keyboard_|keys[5][4]~62_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][3]~102_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][3]~102 .lut_mask = 16'h4000; +defparam \ula_|zx_keyboard_|keys[3][3]~102 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][3]~103 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][3]~103_combout = (\ula_|zx_keyboard_|keys[3][3]~102_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][3]~102_combout & ((\ula_|zx_keyboard_|keys[3][3]~q ))) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[3][3]~q ), + .datad(\ula_|zx_keyboard_|keys[3][3]~102_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][3]~103_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][3]~103 .lut_mask = 16'h33F0; +defparam \ula_|zx_keyboard_|keys[3][3]~103 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y7_N11 +dffeas \ula_|zx_keyboard_|keys[3][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[3][3]~103_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[3][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[3][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~96 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][4]~96_combout = (\ula_|zx_keyboard_|keys[5][1]~34_combout & (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [5] $ (\ula_|ps2_keyboard_|shiftreg [6])))) + + .dataa(\ula_|zx_keyboard_|keys[5][1]~34_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][4]~96_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][4]~96 .lut_mask = 16'h0208; +defparam \ula_|zx_keyboard_|keys[0][4]~96 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~94 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][4]~94_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [6])) + + .dataa(\ula_|zx_keyboard_|shifted~q ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][4]~94_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][4]~94 .lut_mask = 16'hDDCC; +defparam \ula_|zx_keyboard_|keys[2][4]~94 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][3]~95 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][3]~95_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [6]))) # (!\ula_|ps2_keyboard_|shiftreg [1] & +// (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [6]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][3]~95_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][3]~95 .lut_mask = 16'h0810; +defparam \ula_|zx_keyboard_|keys[0][3]~95 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][3]~97 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][3]~97_combout = (\ula_|zx_keyboard_|keys[0][4]~96_combout & ((\ula_|zx_keyboard_|keys[0][3]~95_combout & (!\ula_|zx_keyboard_|keys[2][4]~94_combout )) # (!\ula_|zx_keyboard_|keys[0][3]~95_combout & +// ((\ula_|zx_keyboard_|keys[0][3]~q ))))) # (!\ula_|zx_keyboard_|keys[0][4]~96_combout & (((\ula_|zx_keyboard_|keys[0][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[0][4]~96_combout ), + .datab(\ula_|zx_keyboard_|keys[2][4]~94_combout ), + .datac(\ula_|zx_keyboard_|keys[0][3]~q ), + .datad(\ula_|zx_keyboard_|keys[0][3]~95_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][3]~97_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][3]~97 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[0][3]~97 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y9_N19 +dffeas \ula_|zx_keyboard_|keys[0][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[0][3]~97_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[0][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[0][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~45 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][4]~45_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [1])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][4]~45_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][4]~45 .lut_mask = 16'h5000; +defparam \ula_|zx_keyboard_|keys[6][4]~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][3]~92 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][3]~92_combout = (\ula_|zx_keyboard_|keys[6][4]~45_combout & (\ula_|zx_keyboard_|keys[7][4]~17_combout & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|zx_keyboard_|keys[6][4]~45_combout ), + .datab(\ula_|zx_keyboard_|keys[7][4]~17_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][3]~92_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][3]~92 .lut_mask = 16'h0800; +defparam \ula_|zx_keyboard_|keys[1][3]~92 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][3]~93 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][3]~93_combout = (\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[1][3]~92_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[1][3]~92_combout & ((\ula_|zx_keyboard_|keys[1][3]~q ))))) # +// (!\ula_|ps2_keyboard_|shiftreg [3] & (((\ula_|zx_keyboard_|keys[1][3]~q )))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[1][3]~q ), + .datad(\ula_|zx_keyboard_|keys[1][3]~92_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][3]~93_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][3]~93 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[1][3]~93 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y7_N15 +dffeas \ula_|zx_keyboard_|keys[1][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[1][3]~93_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[1][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[1][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N0 +cycloneive_lcell_comb \D[3]~53 ( +// Equation(s): +// \D[3]~53_combout = (\ula_|zx_keyboard_|keys[0][3]~q & (\z80_|address_pins_|abus[8]~18_combout & ((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][3]~q )))) # (!\ula_|zx_keyboard_|keys[0][3]~q & +// (((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[0][3]~q ), + .datab(\z80_|address_pins_|abus[8]~18_combout ), + .datac(\ula_|zx_keyboard_|keys[1][3]~q ), + .datad(\z80_|address_pins_|abus[9]~17_combout ), + .cin(gnd), + .combout(\D[3]~53_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~53 .lut_mask = 16'hDD0D; +defparam \D[3]~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~99 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][3]~99_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [6])) # (!\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [2] & +// \ula_|ps2_keyboard_|shiftreg [6])) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][3]~99_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][3]~99 .lut_mask = 16'h03C0; +defparam \ula_|zx_keyboard_|keys[2][3]~99 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~100 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][3]~100_combout = (\ula_|zx_keyboard_|keys[2][3]~99_combout & (\ula_|zx_keyboard_|keys[5][4]~62_combout & (\ula_|ps2_keyboard_|shiftreg [2] $ (!\ula_|ps2_keyboard_|shiftreg [3])))) + + .dataa(\ula_|zx_keyboard_|keys[2][3]~99_combout ), + .datab(\ula_|zx_keyboard_|keys[5][4]~62_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][3]~100_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][3]~100 .lut_mask = 16'h8008; +defparam \ula_|zx_keyboard_|keys[2][3]~100 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~98 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][3]~98_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & !\ula_|ps2_keyboard_|shiftreg [2])) + + .dataa(\ula_|zx_keyboard_|shifted~q ), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][3]~98_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][3]~98 .lut_mask = 16'hFF05; +defparam \ula_|zx_keyboard_|keys[2][3]~98 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~101 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][3]~101_combout = (\ula_|zx_keyboard_|keys[5][1]~34_combout & ((\ula_|zx_keyboard_|keys[2][3]~100_combout & ((!\ula_|zx_keyboard_|keys[2][3]~98_combout ))) # (!\ula_|zx_keyboard_|keys[2][3]~100_combout & +// (\ula_|zx_keyboard_|keys[2][3]~q )))) # (!\ula_|zx_keyboard_|keys[5][1]~34_combout & (((\ula_|zx_keyboard_|keys[2][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][1]~34_combout ), + .datab(\ula_|zx_keyboard_|keys[2][3]~100_combout ), + .datac(\ula_|zx_keyboard_|keys[2][3]~q ), + .datad(\ula_|zx_keyboard_|keys[2][3]~98_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][3]~101_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][3]~101 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[2][3]~101 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y9_N9 +dffeas \ula_|zx_keyboard_|keys[2][3] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[2][3]~101_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[2][3]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][3] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[2][3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y7_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~3 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row~3_combout = ((\z80_|address_pins_|DFFE_apin_latch [10]) # (!\ula_|zx_keyboard_|keys[2][3]~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|address_pins_|DFFE_apin_latch [10]), + .datac(gnd), + .datad(\ula_|zx_keyboard_|keys[2][3]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row~3 .lut_mask = 16'hDDFF; +defparam \ula_|zx_keyboard_|key_row~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N20 +cycloneive_lcell_comb \D[3]~54 ( +// Equation(s): +// \D[3]~54_combout = (\D[3]~53_combout & (\ula_|zx_keyboard_|key_row~3_combout & ((\z80_|address_pins_|abus[11]~19_combout ) # (!\ula_|zx_keyboard_|keys[3][3]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[3][3]~q ), + .datab(\D[3]~53_combout ), + .datac(\z80_|address_pins_|abus[11]~19_combout ), + .datad(\ula_|zx_keyboard_|key_row~3_combout ), + .cin(gnd), + .combout(\D[3]~54_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~54 .lut_mask = 16'hC400; +defparam \D[3]~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~109 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][4]~109_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [6])) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|shifted~q ), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][4]~109_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][4]~109 .lut_mask = 16'hFFC0; +defparam \ula_|zx_keyboard_|keys[0][4]~109 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~60 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][2]~60_combout = (\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [6]) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][2]~60_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2]~60 .lut_mask = 16'h0C0C; +defparam \ula_|zx_keyboard_|keys[7][2]~60 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][3]~110 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][3]~110_combout = (\ula_|zx_keyboard_|WideOr16~2_combout & ((\ula_|zx_keyboard_|keys[7][2]~30_combout ) # ((\ula_|zx_keyboard_|keys[7][2]~60_combout & \ula_|ps2_keyboard_|shiftreg [4])))) + + .dataa(\ula_|zx_keyboard_|keys[7][2]~60_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|zx_keyboard_|WideOr16~2_combout ), + .datad(\ula_|zx_keyboard_|keys[7][2]~30_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][3]~110_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][3]~110 .lut_mask = 16'hF080; +defparam \ula_|zx_keyboard_|keys[7][3]~110 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][3]~111 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][3]~111_combout = (\ula_|zx_keyboard_|keys[0][0]~13_combout & (!\ula_|zx_keyboard_|extended~q & (\ula_|zx_keyboard_|keys[7][3]~110_combout & !\ula_|ps2_keyboard_|shiftreg [2]))) + + .dataa(\ula_|zx_keyboard_|keys[0][0]~13_combout ), + .datab(\ula_|zx_keyboard_|extended~q ), + .datac(\ula_|zx_keyboard_|keys[7][3]~110_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][3]~111_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][3]~111 .lut_mask = 16'h0020; +defparam \ula_|zx_keyboard_|keys[7][3]~111 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N14 cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][3]~112 ( // Equation(s): -// \ula_|zx_keyboard_|keys[7][3]~112_combout = (\ula_|zx_keyboard_|WideOr16~2_combout & ((\ula_|zx_keyboard_|keys[7][2]~32_combout ) # ((\ula_|ps2_keyboard_|shiftreg [4] & \ula_|zx_keyboard_|keys[7][2]~61_combout )))) +// \ula_|zx_keyboard_|keys[7][3]~112_combout = (\ula_|zx_keyboard_|keys[7][3]~111_combout & (!\ula_|zx_keyboard_|keys[0][4]~109_combout )) # (!\ula_|zx_keyboard_|keys[7][3]~111_combout & ((\ula_|zx_keyboard_|keys[7][3]~q ))) - .dataa(\ula_|zx_keyboard_|WideOr16~2_combout ), - .datab(\ula_|zx_keyboard_|keys[7][2]~32_combout ), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|zx_keyboard_|keys[7][2]~61_combout ), + .dataa(\ula_|zx_keyboard_|keys[0][4]~109_combout ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[7][3]~q ), + .datad(\ula_|zx_keyboard_|keys[7][3]~111_combout ), .cin(gnd), .combout(\ula_|zx_keyboard_|keys[7][3]~112_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][3]~112 .lut_mask = 16'hA888; +defparam \ula_|zx_keyboard_|keys[7][3]~112 .lut_mask = 16'h55F0; defparam \ula_|zx_keyboard_|keys[7][3]~112 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X27_Y21_N30 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][3]~113 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][3]~113_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|keys[7][3]~112_combout & (\ula_|zx_keyboard_|keys[0][0]~15_combout & !\ula_|zx_keyboard_|extended~q ))) - - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|zx_keyboard_|keys[7][3]~112_combout ), - .datac(\ula_|zx_keyboard_|keys[0][0]~15_combout ), - .datad(\ula_|zx_keyboard_|extended~q ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][3]~113_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][3]~113 .lut_mask = 16'h0040; -defparam \ula_|zx_keyboard_|keys[7][3]~113 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X25_Y20_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][3]~114 ( -// Equation(s): -// \ula_|zx_keyboard_|keys[7][3]~114_combout = (\ula_|zx_keyboard_|keys[7][3]~113_combout & ((!\ula_|zx_keyboard_|keys[0][4]~111_combout ))) # (!\ula_|zx_keyboard_|keys[7][3]~113_combout & (\ula_|zx_keyboard_|keys[7][3]~q )) - - .dataa(gnd), - .datab(\ula_|zx_keyboard_|keys[7][3]~113_combout ), - .datac(\ula_|zx_keyboard_|keys[7][3]~q ), - .datad(\ula_|zx_keyboard_|keys[0][4]~111_combout ), - .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[7][3]~114_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|zx_keyboard_|keys[7][3]~114 .lut_mask = 16'h30FC; -defparam \ula_|zx_keyboard_|keys[7][3]~114 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X25_Y20_N9 +// Location: FF_X29_Y9_N15 dffeas \ula_|zx_keyboard_|keys[7][3] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[7][3]~114_combout ), + .d(\ula_|zx_keyboard_|keys[7][3]~112_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -52321,79 +42219,96 @@ defparam \ula_|zx_keyboard_|keys[7][3] .is_wysiwyg = "true"; defparam \ula_|zx_keyboard_|keys[7][3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X27_Y21_N8 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~109 ( +// Location: LCCOMB_X28_Y9_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|Selector13~0 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][3]~109_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [5]))) +// \ula_|zx_keyboard_|Selector13~0_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|shifted~q )) - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|ps2_keyboard_|shiftreg [6]), - .datac(\ula_|ps2_keyboard_|shiftreg [4]), - .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), + .datab(\ula_|zx_keyboard_|shifted~q ), + .datac(gnd), + .datad(\ula_|zx_keyboard_|released~q ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][3]~109_combout ), + .combout(\ula_|zx_keyboard_|Selector13~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][3]~109 .lut_mask = 16'h1000; -defparam \ula_|zx_keyboard_|keys[6][3]~109 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|Selector13~0 .lut_mask = 16'hFF44; +defparam \ula_|zx_keyboard_|Selector13~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X27_Y21_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~110 ( +// Location: LCCOMB_X29_Y9_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~113 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][3]~110_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (((\ula_|zx_keyboard_|keys[6][3]~109_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|keys[7][2]~32_combout ))) +// \ula_|zx_keyboard_|keys[6][3]~113_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [2]))) - .dataa(\ula_|ps2_keyboard_|shiftreg [2]), - .datab(\ula_|zx_keyboard_|keys[7][2]~32_combout ), - .datac(\ula_|zx_keyboard_|keys[6][3]~109_combout ), + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|ps2_keyboard_|shiftreg [5]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][3]~113_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][3]~113 .lut_mask = 16'h0040; +defparam \ula_|zx_keyboard_|keys[6][3]~113 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~114 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][3]~114_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|zx_keyboard_|keys[6][3]~113_combout )) # (!\ula_|ps2_keyboard_|shiftreg [0] & (((\ula_|ps2_keyboard_|shiftreg [2] & \ula_|zx_keyboard_|keys[7][2]~30_combout )))) + + .dataa(\ula_|zx_keyboard_|keys[6][3]~113_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|zx_keyboard_|keys[7][2]~30_combout ), .datad(\ula_|ps2_keyboard_|shiftreg [0]), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][3]~110_combout ), + .combout(\ula_|zx_keyboard_|keys[6][3]~114_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][3]~110 .lut_mask = 16'hF088; -defparam \ula_|zx_keyboard_|keys[6][3]~110 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[6][3]~114 .lut_mask = 16'hAAC0; +defparam \ula_|zx_keyboard_|keys[6][3]~114 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y21_N24 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~137 ( +// Location: LCCOMB_X29_Y9_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~135 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][3]~137_combout = (\ula_|zx_keyboard_|extended~q ) # (((!\ula_|zx_keyboard_|keys[0][0]~15_combout ) # (!\ula_|ps2_keyboard_|shiftreg [3])) # (!\ula_|zx_keyboard_|keys[6][3]~110_combout )) +// \ula_|zx_keyboard_|keys[6][3]~135_combout = ((\ula_|zx_keyboard_|extended~q ) # ((!\ula_|zx_keyboard_|keys[6][3]~114_combout ) # (!\ula_|ps2_keyboard_|shiftreg [3]))) # (!\ula_|zx_keyboard_|keys[0][0]~13_combout ) - .dataa(\ula_|zx_keyboard_|extended~q ), - .datab(\ula_|zx_keyboard_|keys[6][3]~110_combout ), + .dataa(\ula_|zx_keyboard_|keys[0][0]~13_combout ), + .datab(\ula_|zx_keyboard_|extended~q ), .datac(\ula_|ps2_keyboard_|shiftreg [3]), - .datad(\ula_|zx_keyboard_|keys[0][0]~15_combout ), + .datad(\ula_|zx_keyboard_|keys[6][3]~114_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][3]~137_combout ), + .combout(\ula_|zx_keyboard_|keys[6][3]~135_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][3]~137 .lut_mask = 16'hBFFF; -defparam \ula_|zx_keyboard_|keys[6][3]~137 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[6][3]~135 .lut_mask = 16'hDFFF; +defparam \ula_|zx_keyboard_|keys[6][3]~135 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X28_Y21_N28 -cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~138 ( +// Location: LCCOMB_X29_Y9_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~136 ( // Equation(s): -// \ula_|zx_keyboard_|keys[6][3]~138_combout = (\ula_|ps2_keyboard_|shiftreg [1] & ((\ula_|zx_keyboard_|keys[6][3]~137_combout & ((\ula_|zx_keyboard_|keys[6][3]~q ))) # (!\ula_|zx_keyboard_|keys[6][3]~137_combout & -// (!\ula_|zx_keyboard_|Selector13~0_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [1] & (((\ula_|zx_keyboard_|keys[6][3]~q )))) +// \ula_|zx_keyboard_|keys[6][3]~136_combout = (\ula_|zx_keyboard_|keys[6][3]~135_combout & (((\ula_|zx_keyboard_|keys[6][3]~q )))) # (!\ula_|zx_keyboard_|keys[6][3]~135_combout & ((\ula_|ps2_keyboard_|shiftreg [1] & +// (!\ula_|zx_keyboard_|Selector13~0_combout )) # (!\ula_|ps2_keyboard_|shiftreg [1] & ((\ula_|zx_keyboard_|keys[6][3]~q ))))) - .dataa(\ula_|ps2_keyboard_|shiftreg [1]), - .datab(\ula_|zx_keyboard_|Selector13~0_combout ), + .dataa(\ula_|zx_keyboard_|Selector13~0_combout ), + .datab(\ula_|zx_keyboard_|keys[6][3]~135_combout ), .datac(\ula_|zx_keyboard_|keys[6][3]~q ), - .datad(\ula_|zx_keyboard_|keys[6][3]~137_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), .cin(gnd), - .combout(\ula_|zx_keyboard_|keys[6][3]~138_combout ), + .combout(\ula_|zx_keyboard_|keys[6][3]~136_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|keys[6][3]~138 .lut_mask = 16'hF072; -defparam \ula_|zx_keyboard_|keys[6][3]~138 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[6][3]~136 .lut_mask = 16'hD1F0; +defparam \ula_|zx_keyboard_|keys[6][3]~136 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y21_N29 +// Location: FF_X29_Y9_N9 dffeas \ula_|zx_keyboard_|keys[6][3] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|zx_keyboard_|keys[6][3]~138_combout ), + .d(\ula_|zx_keyboard_|keys[6][3]~136_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -52409,247 +42324,42 @@ defparam \ula_|zx_keyboard_|keys[6][3] .is_wysiwyg = "true"; defparam \ula_|zx_keyboard_|keys[6][3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N18 -cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~2 ( +// Location: LCCOMB_X29_Y9_N30 +cycloneive_lcell_comb \D[3]~56 ( // Equation(s): -// \ula_|zx_keyboard_|key_row~2_combout = (\z80_|address_pins_|DFFE_apin_latch [14]) # ((!\ula_|zx_keyboard_|keys[6][3]~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) +// \D[3]~56_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\z80_|address_pins_|abus[15]~22_combout )) # (!\ula_|zx_keyboard_|keys[7][3]~q ))) # (!\z80_|address_pins_|abus[14]~23_combout & (!\ula_|zx_keyboard_|keys[6][3]~q & +// ((\z80_|address_pins_|abus[15]~22_combout ) # (!\ula_|zx_keyboard_|keys[7][3]~q )))) - .dataa(gnd), - .datab(\z80_|address_pins_|DFFE_apin_latch [14]), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\ula_|zx_keyboard_|keys[6][3]~q ), + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\ula_|zx_keyboard_|keys[7][3]~q ), + .datac(\ula_|zx_keyboard_|keys[6][3]~q ), + .datad(\z80_|address_pins_|abus[15]~22_combout ), .cin(gnd), - .combout(\ula_|zx_keyboard_|key_row~2_combout ), + .combout(\D[3]~56_combout ), .cout()); // synopsys translate_off -defparam \ula_|zx_keyboard_|key_row~2 .lut_mask = 16'hCFFF; -defparam \ula_|zx_keyboard_|key_row~2 .sum_lutc_input = "datac"; +defparam \D[3]~56 .lut_mask = 16'hAF23; +defparam \D[3]~56 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N8 -cycloneive_lcell_comb \D[3]~68 ( +// Location: LCCOMB_X28_Y7_N30 +cycloneive_lcell_comb \D[3]~57 ( // Equation(s): -// \D[3]~68_combout = (\D[3]~67_combout & (\ula_|zx_keyboard_|key_row~2_combout & ((\z80_|address_pins_|abus[15]~22_combout ) # (!\ula_|zx_keyboard_|keys[7][3]~q )))) +// \D[3]~57_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[3]~55_combout & (\D[3]~54_combout & \D[3]~56_combout ))) - .dataa(\z80_|address_pins_|abus[15]~22_combout ), - .datab(\D[3]~67_combout ), - .datac(\ula_|zx_keyboard_|keys[7][3]~q ), - .datad(\ula_|zx_keyboard_|key_row~2_combout ), + .dataa(\D[3]~55_combout ), + .datab(\D[3]~54_combout ), + .datac(\z80_|address_pins_|abus[0]~16_combout ), + .datad(\D[3]~56_combout ), .cin(gnd), - .combout(\D[3]~68_combout ), + .combout(\D[3]~57_combout ), .cout()); // synopsys translate_off -defparam \D[3]~68 .lut_mask = 16'h8C00; -defparam \D[3]~68 .sum_lutc_input = "datac"; +defparam \D[3]~57 .lut_mask = 16'hF8F0; +defparam \D[3]~57 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N30 -cycloneive_lcell_comb \D[3]~69 ( -// Equation(s): -// \D[3]~69_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[3]~65_combout & (\D[3]~66_combout & \D[3]~68_combout ))) - - .dataa(\D[3]~65_combout ), - .datab(\z80_|address_pins_|abus[0]~16_combout ), - .datac(\D[3]~66_combout ), - .datad(\D[3]~68_combout ), - .cin(gnd), - .combout(\D[3]~69_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~69 .lut_mask = 16'hECCC; -defparam \D[3]~69 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y11_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a19 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[3]~96_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_first_bit_number = 3; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: M9K_X22_Y15_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a3 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[3]~96_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; -// synopsys translate_on - -// Location: M9K_X22_Y18_N0 -cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a11 ( - .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .clk1(gnd), - .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain({\D[3]~96_combout }), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .init_file = "led_patterns.mif"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "single_port"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock0"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 32768; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K"; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; -// synopsys translate_on - -// Location: LCCOMB_X23_Y15_N14 -cycloneive_lcell_comb \D[3]~73 ( -// Equation(s): -// \D[3]~73_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ) # (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # -// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout & ((!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) - - .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ), - .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datac(\ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ), - .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .cin(gnd), - .combout(\D[3]~73_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~73 .lut_mask = 16'hCCE2; -defparam \D[3]~73 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y5_N0 +// Location: M9K_X33_Y14_N0 cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a27 ( .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), .portare(vcc), @@ -52665,7 +42375,7 @@ cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a27 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[3]~96_combout }), + .portadatain({\D[3]~74_combout }), .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , \z80_|address_pins_|abus[0]~16_combout }), @@ -52706,25 +42416,274 @@ defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init1 = 20 defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N16 -cycloneive_lcell_comb \D[3]~74 ( -// Equation(s): -// \D[3]~74_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\D[3]~73_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ))) # (!\D[3]~73_combout & -// (\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout )))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\D[3]~73_combout )))) - - .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ), - .datac(\D[3]~73_combout ), - .datad(\ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ), - .cin(gnd), - .combout(\D[3]~74_combout ), - .cout()); +// Location: M9K_X22_Y14_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a3 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[3]~74_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), + .portbdataout()); // synopsys translate_off -defparam \D[3]~74 .lut_mask = 16'hF858; -defparam \D[3]~74 .sum_lutc_input = "datac"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; // synopsys translate_on -// Location: M9K_X22_Y19_N0 +// Location: M9K_X22_Y13_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a19 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[3]~74_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_first_bit_number = 3; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X23_Y14_N26 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6 .lut_mask = 16'hF4A4; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y16_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a11 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[3]~74_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X23_Y14_N22 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout & +// (\ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout )) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ))))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7 .lut_mask = 16'hDAD0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y20_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a3 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h7BBD7F79FFE0AB8FC33758D1C1145DDD6311CF69FFFDF62EDD236FC6A0358FA2B4B15EB89456517DFF58F68BDADB95B5F764CAE7E7C7E7D70CADB8FFD8F9A72BFBB9EB400590D7F939FF5A70A29817DC2CC29B679B2D7146BD21D47EF06F7D5EAF72F66DC666B0726D66FD941AD9BC6D758D5EC24DFEBA64871D6B86D37DF1DFBFF05FBD6AD8CA62C6CBE43BDBFD99E9EB6DD724D235FBEA9FE7D6767D811C40681A00AF8D864D8BB6D2A0916C8A93250A76B8A977F82E8FDFBE68F8E0F8DF237CA976FE488D1069D687A6F1D68A70F37CAAA367A74CBB75D3A6FFB4B1E8D4B7F7F22D2FE1509BDF80E6DD7B717D7E9C6531C3A86BE9F1D7A6AFD5BFB7A37A60; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h8AB3B7FDEE7B9CC735FCCE93E3AC1AAAA691AD6350E57F1F5773302B6F36F63D130E0574D6BB44B2C0D7A907702A748D0BA50F8FA5437ACD3B343C35039F44D19CD4E55E6CB00410842B02A7FD105706DF9E2A1FA025005632A0CC080400D280CCCA0665222D038CC873351A21B23939A98CC08803282189C8440D40CD40462421A40982C046D22C10146484345CAF7BC828BFE79DFBE3C631CBF660C487EBB759BD7F8DE9E0F27A65DE5245BEB8F7829C36F0D136168F97C2BD77D649A39EB4DDB3A42AC80797FDEF4DE3EEF7ED8C7307E4CE6A6317F7BF25D077BBF03AEA3363B065F7D671322D6BFB2B8759433929CEC27E3FD7741292A4A5AF02703CC4E3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'hFD5CB07B6C729B510A78BEC5F7C7A1E7809F1976D0DD3615C1D27D2DF596BFE7A8BCDC2E6655185CC45008B39EFD1FA6E9F5E816114F93E1E7A2A27C72C7349F3497229CB9044B6E7A7861A04A712AAF29EFBD393727F1F3FC2AA1E6CF571457F0A09C47F23F20FE2AABF5FD3ABE6167E5FD36E1D9735BBD5375C1F79BD0424ECF133BF47B9D3DA46DD6DBF3A8ADCDD3DF1176D2FE23447DFC65E1DD7BF3BE5E1C9DCD8EBB9D36AF570CF25CDD16F645D1DE9F9EE575E3A2B91D5659FC131CE3DCD4560015805B13AC0290001EF8261B7E4EB867C828D9777FFF47B6903008DDD7D77EF5E2C6D7220BE64B3C6E9EF22AFDFCC8005C2FFFFA3AB9AD1ADFC0AFE7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h06ABC52D5DBEF57EEB3311A9D85D253B44E250E1566BED57C6DBEB2ABFD1ADF6FF4DEBFBDEB376DF68D5EEDB5EB4D5AB5B79745D76CD8ADC59CB30C8AA33E1551D2FCA8DCB43C5356BAE638588C302868CE1161CACADFEF7696F8C3AA82EC16F47A8EA413A2DCF09B996582318DBF3C4711871B3BC0404EC45252A485234A663C1FFFB3487617BE24FD79501DE05F1A341B89EC82FD5702497FD866639C0DE08B383E6E7C3B310E1F7FF595C5DF6F0E9A9FFFBE16D3FFBE82C1E0051F1E060D500812F408CC6501331852531B04480021D9220D4903A41404312032840153FE9CC8070206B8245AC240020752EBC2BEF3E74AB288F360C239C4AFAE93F68775A; +// synopsys translate_on + +// Location: M9K_X22_Y32_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a11 ( .portawe(vcc), .portare(vcc), @@ -52732,7 +42691,7 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a11 ( .portbwe(gnd), .portbre(vcc), .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .clk1(gnd), .ena0(\z80_|address_pins_|abus[13]~20_combout ), .ena1(vcc), @@ -52782,9 +42741,9 @@ defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 204 defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h420539B476E305B8200E47DFAAE8D5D1D0724DCC3FD72C4F8DE54622A1DD1BA78CA3CE9F24BEFA9E2BB9D89B423C327C8E050114401A62FDCD2054E166C0005F7941B61372AC884EE60A372057B59CFF30A6020B875C06E7C5FBDF9A91F8F0588ED67F67AA66B0674CD240410F613700B8DFE7F8837F88FF4520002E4BFD7FA2768008002000002624793100811F43BC315A6004052671392B47FEB7F5DC90E62175C7B8FC48FCC916D46F9315DFDECBE43E5F03D7D27F97E09E4700AA694552A1FF3BE5E159FFDDEB2FBECAEB87BBCC5FCF6E23D77E4DD4C9DEBC93C10F636326FAFE3BE30DFAF7B9E7A5FFE44BF314DAA1C1529CDBFFE9D94EB11A9F68D4DF; // synopsys translate_on -// Location: M9K_X22_Y23_N0 +// Location: M9K_X22_Y22_N0 cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a11 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1_combout ), + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), @@ -52798,7 +42757,7 @@ cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a11 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[3]~96_combout }), + .portadatain({\D[3]~74_combout }), .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , \z80_|address_pins_|abus[0]~16_combout }), @@ -52855,103 +42814,9 @@ defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 20 defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N24 -cycloneive_lcell_comb \D[3]~70 ( -// Equation(s): -// \D[3]~70_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\z80_|address_pins_|abus[14]~23_combout & ((\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ))) # (!\z80_|address_pins_|abus[14]~23_combout & -// (\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout )))) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\z80_|address_pins_|abus[14]~23_combout )) - - .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\z80_|address_pins_|abus[14]~23_combout ), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ), - .cin(gnd), - .combout(\D[3]~70_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~70 .lut_mask = 16'hEC64; -defparam \D[3]~70 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y21_N0 -cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a3 ( - .portawe(vcc), - .portare(vcc), - .portaaddrstall(gnd), - .portbwe(gnd), - .portbre(vcc), - .portbaddrstall(gnd), - .clk0(\CLOCK_50~inputclkctrl_outclk ), - .clk1(gnd), - .ena0(!\z80_|address_pins_|abus[13]~20_combout ), - .ena1(vcc), - .ena2(vcc), - .ena3(vcc), - .clr0(gnd), - .clr1(gnd), - .portadatain(1'b0), - .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , -\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , -\z80_|address_pins_|abus[0]~16_combout }), - .portabyteenamasks(1'b1), - .portbdatain(1'b0), - .portbaddr(13'b0000000000000), - .portbbyteenamasks(1'b1), - .devclrn(devclrn), - .devpor(devpor), - .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), - .portbdataout()); -// synopsys translate_off -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file = "./rom/gw03.hex"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "rom"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 16384; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h7BBD7F79FFE0AB8FC33758D1C1145DDD6311CF69FFFDF62EDD236FC6A0358FA2B4B15EB89456517DFF58F68BDADB95B5F764CAE7E7C7E7D70CADB8FFD8F9A72BFBB9EB400590D7F939FF5A70A29817DC2CC29B679B2D7146BD21D47EF06F7D5EAF72F66DC666B0726D66FD941AD9BC6D758D5EC24DFEBA64871D6B86D37DF1DFBFF05FBD6AD8CA62C6CBE43BDBFD99E9EB6DD724D235FBEA9FE7D6767D811C40681A00AF8D864D8BB6D2A0916C8A93250A76B8A977F82E8FDFBE68F8E0F8DF237CA976FE488D1069D687A6F1D68A70F37CAAA367A74CBB75D3A6FFB4B1E8D4B7F7F22D2FE1509BDF80E6DD7B717D7E9C6531C3A86BE9F1D7A6AFD5BFB7A37A60; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h8AB3B7FDEE7B9CC735FCCE93E3AC1AAAA691AD6350E57F1F5773302B6F36F63D130E0574D6BB44B2C0D7A907702A748D0BA50F8FA5437ACD3B343C35039F44D19CD4E55E6CB00410842B02A7FD105706DF9E2A1FA025005632A0CC080400D280CCCA0665222D038CC873351A21B23939A98CC08803282189C8440D40CD40462421A40982C046D22C10146484345CAF7BC828BFE79DFBE3C631CBF660C487EBB759BD7F8DE9E0F27A65DE5245BEB8F7829C36F0D136168F97C2BD77D649A39EB4DDB3A42AC80797FDEF4DE3EEF7ED8C7307E4CE6A6317F7BF25D077BBF03AEA3363B065F7D671322D6BFB2B8759433929CEC27E3FD7741292A4A5AF02703CC4E3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'hFD5CB07B6C729B510A78BEC5F7C7A1E7809F1976D0DD3615C1D27D2DF596BFE7A8BCDC2E6655185CC45008B39EFD1FA6E9F5E816114F93E1E7A2A27C72C7349F3497229CB9044B6E7A7861A04A712AAF29EFBD393727F1F3FC2AA1E6CF571457F0A09C47F23F20FE2AABF5FD3ABE6167E5FD36E1D9735BBD5375C1F79BD0424ECF133BF47B9D3DA46DD6DBF3A8ADCDD3DF1176D2FE23447DFC65E1DD7BF3BE5E1C9DCD8EBB9D36AF570CF25CDD16F645D1DE9F9EE575E3A2B91D5659FC131CE3DCD4560015805B13AC0290001EF8261B7E4EB867C828D9777FFF47B6903008DDD7D77EF5E2C6D7220BE64B3C6E9EF22AFDFCC8005C2FFFFA3AB9AD1ADFC0AFE7; -defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h06ABC52D5DBEF57EEB3311A9D85D253B44E250E1566BED57C6DBEB2ABFD1ADF6FF4DEBFBDEB376DF68D5EEDB5EB4D5AB5B79745D76CD8ADC59CB30C8AA33E1551D2FCA8DCB43C5356BAE638588C302868CE1161CACADFEF7696F8C3AA82EC16F47A8EA413A2DCF09B996582318DBF3C4711871B3BC0404EC45252A485234A663C1FFFB3487617BE24FD79501DE05F1A341B89EC82FD5702497FD866639C0DE08B383E6E7C3B310E1F7FF595C5DF6F0E9A9FFFBE16D3FFBE82C1E0051F1E060D500812F408CC6501331852531B04480021D9220D4903A41404312032840153FE9CC8070206B8245AC240020752EBC2BEF3E74AB288F360C239C4AFAE93F68775A; -// synopsys translate_on - -// Location: LCCOMB_X23_Y15_N22 -cycloneive_lcell_comb \D[3]~71 ( -// Equation(s): -// \D[3]~71_combout = (\z80_|address_pins_|abus[15]~22_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout $ (((\D[3]~70_combout ))))) # (!\z80_|address_pins_|abus[15]~22_combout & -// (((\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout & !\D[3]~70_combout )))) - - .dataa(\z80_|address_pins_|abus[15]~22_combout ), - .datab(\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ), - .datac(\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ), - .datad(\D[3]~70_combout ), - .cin(gnd), - .combout(\D[3]~71_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~71 .lut_mask = 16'h22D8; -defparam \D[3]~71 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: M9K_X22_Y31_N0 +// Location: M9K_X22_Y30_N0 cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a3 ( - .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0_combout ), + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ), .portare(vcc), .portaaddrstall(gnd), .portbwe(gnd), @@ -52965,7 +42830,7 @@ cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a3 ( .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain({\D[3]~96_combout }), + .portadatain({\D[3]~74_combout }), .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , \z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , \z80_|address_pins_|abus[0]~16_combout }), @@ -53021,95 +42886,113 @@ defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 204 defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h022388704B6887014BD84185680166815764AC0148D308813FFFFFFC0000000003228A304BA085014BFC40816C0166915375AC0140D308013FFFFFFC40000000432289294EB08F014A1C40816C016681537DA80140D10E01400000017FFFFFFE406281154FB08D014A0040894C016299437DB00140D10F01400000037FFFFFFE4062A13149A88D814BE0429146016EA14179B001405107017FFFFFFF0000000043E0812549C889814BE0528146016C814179924140511F413FFFFFFE0000000043E881314EE881814A00468147436C814159100100513F0000000000FFFFFFFF4B6883014EA881814800668147C22C814019900100003E0000000000FFFFFFFF; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N20 -cycloneive_lcell_comb \D[3]~72 ( +// Location: LCCOMB_X23_Y14_N24 +cycloneive_lcell_comb \Selector3~1 ( // Equation(s): -// \D[3]~72_combout = (\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & (\D[3]~70_combout )) # (!\ram0|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\D[3]~70_combout & (!\D[3]~71_combout & -// \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout )) # (!\D[3]~70_combout & (\D[3]~71_combout )))) +// \Selector3~1_combout = (\Selector3~0_combout & (((\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout )) # (!\z80_|address_pins_|abus[14]~23_combout ))) # (!\Selector3~0_combout & (\z80_|address_pins_|abus[14]~23_combout & +// ((\ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout )))) - .dataa(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]), - .datab(\D[3]~70_combout ), - .datac(\D[3]~71_combout ), + .dataa(\Selector3~0_combout ), + .datab(\z80_|address_pins_|abus[14]~23_combout ), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ), .datad(\ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ), .cin(gnd), - .combout(\D[3]~72_combout ), + .combout(\Selector3~1_combout ), .cout()); // synopsys translate_off -defparam \D[3]~72 .lut_mask = 16'h9C98; -defparam \D[3]~72 .sum_lutc_input = "datac"; +defparam \Selector3~1 .lut_mask = 16'hE6A2; +defparam \Selector3~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N28 -cycloneive_lcell_comb \D[3]~108 ( +// Location: LCCOMB_X23_Y14_N16 +cycloneive_lcell_comb \Selector3~2 ( // Equation(s): -// \D[3]~108_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (\D[3]~74_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\D[3]~72_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & -// (\D[3]~74_combout )))) +// \Selector3~2_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\Selector3~1_combout )))) # (!\z80_|address_pins_|abus[14]~23_combout & ((\Selector3~1_combout & ((\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ))) # +// (!\Selector3~1_combout & (\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout )))) + + .dataa(\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ), + .datab(\z80_|address_pins_|abus[14]~23_combout ), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ), + .datad(\Selector3~1_combout ), + .cin(gnd), + .combout(\Selector3~2_combout ), + .cout()); +// synopsys translate_off +defparam \Selector3~2 .lut_mask = 16'hFC22; +defparam \Selector3~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y14_N10 +cycloneive_lcell_comb \D[3]~85 ( +// Equation(s): +// \D[3]~85_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\Selector3~2_combout +// ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout )))) .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), - .datab(\D[3]~74_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(\D[3]~72_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout ), + .datad(\Selector3~2_combout ), .cin(gnd), - .combout(\D[3]~108_combout ), + .combout(\D[3]~85_combout ), .cout()); // synopsys translate_off -defparam \D[3]~108 .lut_mask = 16'hDC8C; -defparam \D[3]~108 .sum_lutc_input = "datac"; +defparam \D[3]~85 .lut_mask = 16'hF4B0; +defparam \D[3]~85 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N4 -cycloneive_lcell_comb \D[3]~95 ( +// Location: LCCOMB_X23_Y14_N2 +cycloneive_lcell_comb \D[3]~73 ( // Equation(s): -// \D[3]~95_combout = ((\Equal2~0_combout & (\D[3]~69_combout )) # (!\Equal2~0_combout & ((\D[3]~108_combout )))) # (!\Equal2~1_combout ) +// \D[3]~73_combout = ((\Equal2~0_combout & (\D[3]~57_combout )) # (!\Equal2~0_combout & ((\D[3]~85_combout )))) # (!\Equal2~1_combout ) - .dataa(\D[3]~69_combout ), + .dataa(\D[3]~57_combout ), .datab(\Equal2~1_combout ), .datac(\Equal2~0_combout ), - .datad(\D[3]~108_combout ), + .datad(\D[3]~85_combout ), .cin(gnd), - .combout(\D[3]~95_combout ), + .combout(\D[3]~73_combout ), .cout()); // synopsys translate_off -defparam \D[3]~95 .lut_mask = 16'hBFB3; -defparam \D[3]~95 .sum_lutc_input = "datac"; +defparam \D[3]~73 .lut_mask = 16'hBFB3; +defparam \D[3]~73 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N26 -cycloneive_lcell_comb \D[3]~96 ( +// Location: LCCOMB_X23_Y14_N8 +cycloneive_lcell_comb \D[3]~74 ( // Equation(s): -// \D[3]~96_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\z80_|data_pins_|dout [3] & \D[3]~95_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\D[3]~95_combout )) # (!\Equal2~1_combout ))) +// \D[3]~74_combout = (\z80_|pin_control_|bus_db_pin_oe~15_combout & (\z80_|data_pins_|dout [3] & ((\D[3]~73_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout & (((\D[3]~73_combout ) # (!\Equal2~1_combout )))) - .dataa(\z80_|pin_control_|bus_db_pin_oe~14_combout ), + .dataa(\z80_|data_pins_|dout [3]), .datab(\Equal2~1_combout ), - .datac(\z80_|data_pins_|dout [3]), - .datad(\D[3]~95_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .datad(\D[3]~73_combout ), .cin(gnd), - .combout(\D[3]~96_combout ), + .combout(\D[3]~74_combout ), .cout()); // synopsys translate_off -defparam \D[3]~96 .lut_mask = 16'hF511; -defparam \D[3]~96 .sum_lutc_input = "datac"; +defparam \D[3]~74 .lut_mask = 16'hAF03; +defparam \D[3]~74 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y13_N6 +// Location: LCCOMB_X30_Y13_N16 cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] ( // Equation(s): -// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [3] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[3]~21_combout ) # ((\D[3]~96_combout & \z80_|pin_control_|bus_db_pin_re~combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & -// (\D[3]~96_combout & (\z80_|pin_control_|bus_db_pin_re~combout ))) +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [3] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[3]~21_combout ) # ((\z80_|pin_control_|bus_db_pin_re~combout & \D[3]~74_combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & +// (\z80_|pin_control_|bus_db_pin_re~combout & ((\D[3]~74_combout )))) .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datab(\D[3]~96_combout ), - .datac(\z80_|pin_control_|bus_db_pin_re~combout ), - .datad(\z80_|bus_control_|db[3]~21_combout ), + .datab(\z80_|pin_control_|bus_db_pin_re~combout ), + .datac(\z80_|bus_control_|db[3]~21_combout ), + .datad(\D[3]~74_combout ), .cin(gnd), .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [3]), .cout()); // synopsys translate_off -defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] .lut_mask = 16'hEAC0; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] .lut_mask = 16'hECA0; defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y13_N7 +// Location: FF_X30_Y13_N17 dffeas \z80_|data_pins_|dout[3] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [3]), @@ -53128,44 +43011,903 @@ defparam \z80_|data_pins_|dout[3] .is_wysiwyg = "true"; defparam \z80_|data_pins_|dout[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y12_N4 +// Location: LCCOMB_X29_Y13_N20 cycloneive_lcell_comb \z80_|bus_control_|db[3]~20 ( // Equation(s): // \z80_|bus_control_|db[3]~20_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [3]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) - .dataa(\z80_|execute_|ctl_bus_db_oe~combout ), - .datab(\z80_|data_pins_|dout [3]), - .datac(gnd), - .datad(\z80_|bus_control_|db[0]~4_combout ), + .dataa(gnd), + .datab(\z80_|bus_control_|db[0]~4_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~combout ), + .datad(\z80_|data_pins_|dout [3]), .cin(gnd), .combout(\z80_|bus_control_|db[3]~20_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[3]~20 .lut_mask = 16'hDD00; +defparam \z80_|bus_control_|db[3]~20 .lut_mask = 16'hCC0C; defparam \z80_|bus_control_|db[3]~20 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y10_N0 +// Location: LCCOMB_X30_Y17_N30 cycloneive_lcell_comb \z80_|bus_control_|db[3]~21 ( // Equation(s): // \z80_|bus_control_|db[3]~21_combout = ((\z80_|bus_control_|db[3]~20_combout & ((\z80_|alu_control_|db[3]~35_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) .dataa(\z80_|bus_control_|db[0]~6_combout ), - .datab(\z80_|bus_control_|db[3]~20_combout ), - .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), - .datad(\z80_|alu_control_|db[3]~35_combout ), + .datab(\z80_|alu_control_|db[3]~35_combout ), + .datac(\z80_|bus_control_|db[3]~20_combout ), + .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), .cin(gnd), .combout(\z80_|bus_control_|db[3]~21_combout ), .cout()); // synopsys translate_off -defparam \z80_|bus_control_|db[3]~21 .lut_mask = 16'hDD5D; +defparam \z80_|bus_control_|db[3]~21 .lut_mask = 16'hD5F5; defparam \z80_|bus_control_|db[3]~21 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X34_Y10_N1 -dffeas \z80_|ir_|opcode[3] ( +// Location: LCCOMB_X30_Y17_N12 +cycloneive_lcell_comb \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 ( +// Equation(s): +// \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout = (\z80_|bus_control_|db[4]~19_combout & \z80_|bus_control_|db[3]~21_combout ) + + .dataa(gnd), + .datab(\z80_|bus_control_|db[4]~19_combout ), + .datac(\z80_|bus_control_|db[3]~21_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 .lut_mask = 16'hC0C0; +defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y17_N13 +dffeas \z80_|interrupts_|im2 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\z80_|bus_control_|db[3]~21_combout ), + .d(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_im_we~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|interrupts_|im2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|interrupts_|im2 .is_wysiwyg = "true"; +defparam \z80_|interrupts_|im2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~10 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~10_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|interrupts_|im2~q & \z80_|interrupts_|DFFE_inst44~q )) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|interrupts_|im2~q ), + .datac(\z80_|interrupts_|DFFE_inst44~q ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~10 .lut_mask = 16'h4040; +defparam \z80_|execute_|ctl_mRead~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_sw_mask543_en~0 ( +// Equation(s): +// \z80_|execute_|ctl_sw_mask543_en~0_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (!\z80_|execute_|ctl_mRead~10_combout & (\z80_|pla_decode_|Equal47~0_combout & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|execute_|ctl_mRead~10_combout ), + .datac(\z80_|pla_decode_|Equal47~0_combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_sw_mask543_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_sw_mask543_en~0 .lut_mask = 16'h1000; +defparam \z80_|execute_|ctl_sw_mask543_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N24 +cycloneive_lcell_comb \z80_|alu_control_|db[7]~16 ( +// Equation(s): +// \z80_|alu_control_|db[7]~16_combout = (\z80_|alu_flags_|DFFE_inst_latch_sf~q & (!\z80_|alu_|db[7]~12_combout & ((\z80_|execute_|ctl_sw_2u~7_combout )))) # (!\z80_|alu_flags_|DFFE_inst_latch_sf~q & ((\z80_|execute_|ctl_flags_oe~2_combout ) # +// ((!\z80_|alu_|db[7]~12_combout & \z80_|execute_|ctl_sw_2u~7_combout )))) + + .dataa(\z80_|alu_flags_|DFFE_inst_latch_sf~q ), + .datab(\z80_|alu_|db[7]~12_combout ), + .datac(\z80_|execute_|ctl_flags_oe~2_combout ), + .datad(\z80_|execute_|ctl_sw_2u~7_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[7]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[7]~16 .lut_mask = 16'h7350; +defparam \z80_|alu_control_|db[7]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N6 +cycloneive_lcell_comb \z80_|alu_control_|db[7]~17 ( +// Equation(s): +// \z80_|alu_control_|db[7]~17_combout = (!\z80_|alu_control_|db[7]~16_combout & (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & ((\z80_|reg_file_|gdfx_temp0[7]~91_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp0[7]~91_combout ), + .datab(\z80_|alu_control_|db[7]~16_combout ), + .datac(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[7]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[7]~17 .lut_mask = 16'h2030; +defparam \z80_|alu_control_|db[7]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N12 +cycloneive_lcell_comb \z80_|alu_control_|db[7]~18 ( +// Equation(s): +// \z80_|alu_control_|db[7]~18_combout = (\z80_|alu_control_|db[7]~17_combout & (((!\z80_|execute_|ctl_sw_mask543_en~0_combout & \z80_|bus_control_|db[7]~7_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout ))) + + .dataa(\z80_|execute_|ctl_sw_mask543_en~0_combout ), + .datab(\z80_|bus_control_|db[7]~7_combout ), + .datac(\z80_|execute_|ctl_sw_1d~7_combout ), + .datad(\z80_|alu_control_|db[7]~17_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[7]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[7]~18 .lut_mask = 16'h4F00; +defparam \z80_|alu_control_|db[7]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y14_N26 +cycloneive_lcell_comb \z80_|alu_control_|db[7]~19 ( +// Equation(s): +// \z80_|alu_control_|db[7]~19_combout = (\z80_|alu_control_|db[7]~18_combout ) # (!\z80_|alu_control_|db[6]~11_combout ) + + .dataa(\z80_|alu_control_|db[7]~18_combout ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|alu_control_|db[6]~11_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[7]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[7]~19 .lut_mask = 16'hAAFF; +defparam \z80_|alu_control_|db[7]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N28 +cycloneive_lcell_comb \z80_|bus_control_|db[7]~5 ( +// Equation(s): +// \z80_|bus_control_|db[7]~5_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[7]~19_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datab(\z80_|bus_control_|db[0]~4_combout ), + .datac(gnd), + .datad(\z80_|alu_control_|db[7]~19_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[7]~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[7]~5 .lut_mask = 16'hCC44; +defparam \z80_|bus_control_|db[7]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N2 +cycloneive_lcell_comb \D[5]~67 ( +// Equation(s): +// \D[5]~67_combout = (!\z80_|memory_ifc_|nIORQ_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\z80_|memory_ifc_|nRD_out~2_combout & !\z80_|memory_ifc_|nWR_out~0_combout ))) + + .dataa(\z80_|memory_ifc_|nIORQ_out~0_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|memory_ifc_|nRD_out~2_combout ), + .datad(\z80_|memory_ifc_|nWR_out~0_combout ), + .cin(gnd), + .combout(\D[5]~67_combout ), + .cout()); +// synopsys translate_off +defparam \D[5]~67 .lut_mask = 16'h0040; +defparam \D[5]~67 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y21_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a7 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[7]~80_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081; +// synopsys translate_on + +// Location: M9K_X33_Y20_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a23 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[7]~80_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_first_bit_number = 7; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N10 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout ) # +// (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout & +// ((!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14 .lut_mask = 16'hCCE2; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y18_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a31 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[7]~80_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a31_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_first_bit_number = 7; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y16_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a15 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[7]~80_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N24 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15_combout = (\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ) # +// ((!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14_combout & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & +// \ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14_combout ), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15 .lut_mask = 16'hDA8A; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y29_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a15 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h3C0000000000000000000000000000000000000000000000000000000000000080000000000002000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFB91060128E2D09899B4D10A148392808351AD282E76190E029FDC286449331D89080802222C0D04D1121484041D21084C223B0A12EBE72083D81421B93CA9589A04864A853089602E536320C2A5944831907110C246020089C76EE701A4E23964C6586008731635460418000008202040C300110000FCE7E12403749F8C6AB8F69167210EF8A4B8228710884C5C47A9986E8840C02862C088C36E19CF1D315; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h03020CCE064769B15020A6030880234C64E9BEF8E98A81489083A026140D648906E5AD6C882882990A40D293FED064710CB226CDA0330D7B189B344442EC35E3763C75FA1DB107B865E5B8F7B95E77F222244C6BDC1879C0562EF779BE0009465775469089F04C623E19317B486F653C1C22CA642CD685C10EE47EDD66C8C226C7C57F084106FB3B8B1E47463C0088D11104F23C180222A0AA22A22882A202A00000000288964258156302504F5F660C054DEDCA20CC201A4074192601E376C9596CD8B4B568A4DFEF3DBF8027A3422A56A2C003E514582104BF8D6B5D80BB397FBBEC46E8B3CAEBE0100275A1092081D0C1E5716DF09CFEEC00AD800529E1A8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h873CB568FC3F09080F4400DAC600092017210911A6081DCC4979244124815884AE6302C4BE6BA8C22A084803225A0855ABBBC528B1CA2456A4951A53C1209153CFC3000F43632B49C39723270C604B184D1940F1B2A04459BEB088666843BB38C23A8D170CED981891256A2C1D9B31C0F040202103900E6765976089DB8DE16E0001022EC10015E263787F7E581EF83F062200C626EC4E19021840D9C112400C4B987A78AE1BF80005EF370C0739371E0D3E5CF1E3677332370BB98D1831B30F7D8CDC0131C444798F040DC0116E2C4336B0166109A15D1FCC7EDE31EB23862203C11245EE31E38E6DEF2188BE2068F3C716E10317783020D8EF5C256774BA0E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h1B9CE2DA363196DC20007FF5554FC631286DC716B048384C26510685218DF9E6C629E6050C619658692170C1022C2232C965C92C189020C705873084858910322166D72DC524870C422BBFFD4808A7032B088DE3000B853800736C8E9968C19A4B72C08871D2413188E4829219C38C2025920480D64856902E4D4D60B640C833C14D536A45D144B244C24A290076E58CC2E64E4A2DC4C5939C4C2DDBD1B918B231248625B2C0DD0F07A27A111CB80A48808C7C21C205029100010400228BB3BDFF7DCCEF40196C8381658D8840043B119B86A46247665810E2203000141023C366CB633B3376DC625DA8A0856C484392B779E1BA4088EDB4A6CDB9BD46DCC0B2; +// synopsys translate_on + +// Location: M9K_X33_Y23_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a15 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(gnd), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[7]~80_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_first_bit_number = 7; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y24_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a7 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[7]~80_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_first_bit_number = 7; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h000000000000000000000000FFFFFFFFC0810207C0001A176020155177486D89000000000000000000000000FFFFFFFF80000003C0000217724019F17748EDC900000000000000000000000000000001BF7EFDF9400406B17A400BF57748AD81000000000000000000000000000000013F7EFDF940041EB1724218157749A7910000000000000000000000003F7EFDF90000000140042AF97B426C157DC9B7590000000000000000000000003F7EFDF90000000140042069600246057DC95351000000000000000000000000408102053FFFFFF95FE4084175C246896009F35100000000000000000000000040810207BFFFFFFF7FE4147177C2004960291759; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h7FE8374958F827C15FF88F91E9A80DC3629A9FC172033EC170FB0E8173F792815FE826E158F805C95FF8AF8169A80DC3629A1EC17B033BC1706B3E8173FFB0C1400826E558F805C15DF8AF9169A82DD163C21BC17B133BC1716B3781723F14C1400826E958D825815DD8AF8168482DC161229BC17A133FC171AB3781723F16E9400826E95818058179582F9160480FC162229FC17ACA39C172FB3F8152CF10A1400826E958180D8179580F05614C0DC162329BC171EB398173537F8152E310D1400826E158180D81F8580FD1612C0F41631293C173BB398D63037F81D22313D1400827E958080F01F8188FCB60A40F41435083C1723B198161834F01D67300E3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'hD4FB0D2352268F0151E680016803440977EDE98148F31101BFFFFFFF4081010750FB094B52728F0151FEC0016C034C0153EDA90148F31F013FFFFFFB4081010152F3096156DA8901503ED2016C03480173FDA00148F11F01000000013F7EFEF952E3017156DA85015022C2016C034C0153FCA00148F10F01000000013F7EFEF956B3A9115052850543C2C2116C014D2153FDA12148D11F013F7EFEF900000001469F8B3150728D0143C05A016D014C81537DA00148D11E01BF7EFEF900000001528F8F2156628D0140004E016F054481513DA181C8513E0580000007FFFFFFFF528E8B2156E28C0148024E0167676C415139B041C8513E07C0810107FFFFFFFF; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N14 +cycloneive_lcell_comb \Mux0~0 ( +// Equation(s): +// \Mux0~0_combout = (\z80_|address_pins_|abus[14]~23_combout & ((\Selector3~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout )) # (!\Selector3~0_combout & +// ((\ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout ))))) # (!\z80_|address_pins_|abus[14]~23_combout & (((\Selector3~0_combout )))) + + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout ), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout ), + .datad(\Selector3~0_combout ), + .cin(gnd), + .combout(\Mux0~0_combout ), + .cout()); +// synopsys translate_off +defparam \Mux0~0 .lut_mask = 16'hDDA0; +defparam \Mux0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y32_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a7 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h7C762E21DB2481CB6BB88C68811C76C63B18ECC1BACDC6110DCC70BC20940800C71478E35468600B01A93082C63DD073AE4181844449C08D8D56B0DCC881251C202139803D3000B2E0209DB9101160989A5916381001B0446631006064DB1B996E436E644CF6C8606F124DA230E9B66E2F46BB466E2CE068661B4B05F02F7D00CB3E518948104042F84F1840401018406877D800A00000F5122597005DA4411000800020249004081008924124080114000000020BFFFFEC638C31207B6C321407D901787004001C459326210CCE00C6AF707B84440C313110B8C4D13B2C6E06C4C088B1A9B24BEB0178C4D6C18230DF72B07A28063647CC4721026D8C711864; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h881B30810845E6D18622EC9B6236A000030986A4F0644601226000A2F220D40310438334E51C28000400B18422CA60FC42C9C03F066366ECBBB010B00B004807CC0E00DAEC3000194A52B80C606262092D84A1102410000001400010002000800200080020000800200008000800400040002004000040002000020002000801000010004002001000200008000AEE708008880C86112251B45B36C0048833B319B4C2CE6660D2C0619246C4B208BC0AD00202001E104FC30911410804201E92102B400E8004C40AD6E4614466308ABC7165AA57060A3A736A188ABB300200A10BB04344008422327B1393C43396A931B8C8C87227A6141C0E2DCC76D830B082; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h101CC0024A6C32005CCB31908842211604D8B326101118B54B188CB4D502F5F02DA65C2472B824F109BC594C2401209C01A0E59830002C73B396C6015B85A163184B56183004204267600220A061A004893E1D609106BDBB553920A011AA5AE581E08228382D54C2989BC59535528176240438C9AA757917F95C7428981A26470D1C3E528444D9B00E561C40973AE1806031C464834F03D34A11233A34B34A1D1A55A50C3384B549B64C381920140D4008004020B119D5834C10064000006001169808000200040100000002F8986E37654DDFF88E20860382DC089D4C239F6E4C3C8D784218667F524CE209881213DC91099C14744901620044C802DA414966; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h84724A241226DB4809C9A1100DE6A63984D651A2624A09420496DDC12CC10964B6E370363701B41848117683379C8422106D001BB41FB8248067301E1002C636A276585D5273AC87206840415DA74B4E9D213CAE3234B308E19608AA38250844883838649E1442A0D983F4A9094A5AD4A52D56C5D80CAC58D9645944A230091549F30426B100842A12B25160D6D991E6C8C81AFB4C644004C2140A342020D84C9001624489A10045D16C944B02763FF55405E400BADFE5BFFFFFF00000000011042250089108884888410924041204444209102084241104204108824114455292225124929249248894408541300A6DB00791E5B12FEF24037181F1901B007B; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N16 +cycloneive_lcell_comb \Mux0~1 ( +// Equation(s): +// \Mux0~1_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\Mux0~0_combout )))) # (!\z80_|address_pins_|abus[14]~23_combout & ((\Mux0~0_combout & (\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout )) # (!\Mux0~0_combout & +// ((\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ))))) + + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ), + .datac(\Mux0~0_combout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ), + .cin(gnd), + .combout(\Mux0~1_combout ), + .cout()); +// synopsys translate_off +defparam \Mux0~1 .lut_mask = 16'hE5E0; +defparam \Mux0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N22 +cycloneive_lcell_comb \D[7]~89 ( +// Equation(s): +// \D[7]~89_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [15] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\Mux0~1_combout ))))) # +// (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15_combout )) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15_combout ), + .datac(\z80_|address_pins_|DFFE_apin_latch [15]), + .datad(\Mux0~1_combout ), + .cin(gnd), + .combout(\D[7]~89_combout ), + .cout()); +// synopsys translate_off +defparam \D[7]~89 .lut_mask = 16'hCEC4; +defparam \D[7]~89 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N30 +cycloneive_lcell_comb \D[7]~72 ( +// Equation(s): +// \D[7]~72_combout = (\D[5]~67_combout & (\D[7]~89_combout & ((\z80_|data_pins_|dout [7]) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout )))) # (!\D[5]~67_combout & ((\z80_|data_pins_|dout [7]) # ((!\z80_|pin_control_|bus_db_pin_oe~15_combout )))) + + .dataa(\D[5]~67_combout ), + .datab(\z80_|data_pins_|dout [7]), + .datac(\D[7]~89_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .cin(gnd), + .combout(\D[7]~72_combout ), + .cout()); +// synopsys translate_off +defparam \D[7]~72 .lut_mask = 16'hC4F5; +defparam \D[7]~72 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y11_N12 +cycloneive_lcell_comb \D[0]~84 ( +// Equation(s): +// \D[0]~84_combout = (\z80_|pin_control_|bus_db_pin_oe~15_combout ) # ((\z80_|memory_ifc_|nRD_out~2_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|memory_ifc_|nWR_out~0_combout ))) + + .dataa(\z80_|memory_ifc_|nRD_out~2_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .datad(\z80_|memory_ifc_|nWR_out~0_combout ), + .cin(gnd), + .combout(\D[0]~84_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~84 .lut_mask = 16'hF0F8; +defparam \D[0]~84 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N6 +cycloneive_lcell_comb \D[7]~80 ( +// Equation(s): +// \D[7]~80_combout = (\D[7]~72_combout ) # (!\D[0]~84_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\D[7]~72_combout ), + .datad(\D[0]~84_combout ), + .cin(gnd), + .combout(\D[7]~80_combout ), + .cout()); +// synopsys translate_off +defparam \D[7]~80 .lut_mask = 16'hF0FF; +defparam \D[7]~80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N12 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [7] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[7]~7_combout ) # ((\D[7]~80_combout & \z80_|pin_control_|bus_db_pin_re~combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & +// (((\D[7]~80_combout & \z80_|pin_control_|bus_db_pin_re~combout )))) + + .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datab(\z80_|bus_control_|db[7]~7_combout ), + .datac(\D[7]~80_combout ), + .datad(\z80_|pin_control_|bus_db_pin_re~combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [7]), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] .lut_mask = 16'hF888; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y13_N13 +dffeas \z80_|data_pins_|dout[7] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [7]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|data_pins_|dout [7]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|data_pins_|dout[7] .is_wysiwyg = "true"; +defparam \z80_|data_pins_|dout[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N20 +cycloneive_lcell_comb \z80_|bus_control_|db[7]~7 ( +// Equation(s): +// \z80_|bus_control_|db[7]~7_combout = ((\z80_|bus_control_|db[7]~5_combout & ((\z80_|data_pins_|dout [7]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) + + .dataa(\z80_|bus_control_|db[0]~6_combout ), + .datab(\z80_|bus_control_|db[7]~5_combout ), + .datac(\z80_|data_pins_|dout [7]), + .datad(\z80_|execute_|ctl_bus_db_oe~combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[7]~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[7]~7 .lut_mask = 16'hD5DD; +defparam \z80_|bus_control_|db[7]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y13_N21 +dffeas \z80_|ir_|opcode[7] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|bus_control_|db[7]~7_combout ), .asdata(vcc), .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), .aload(gnd), @@ -53174,65 +43916,9090 @@ dffeas \z80_|ir_|opcode[3] ( .ena(\z80_|execute_|ctl_ir_we~13_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\z80_|ir_|opcode [3]), + .q(\z80_|ir_|opcode [7]), .prn(vcc)); // synopsys translate_off -defparam \z80_|ir_|opcode[3] .is_wysiwyg = "true"; -defparam \z80_|ir_|opcode[3] .power_up = "low"; +defparam \z80_|ir_|opcode[7] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X40_Y15_N8 -cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~4 ( +// Location: LCCOMB_X29_Y13_N30 +cycloneive_lcell_comb \z80_|pla_decode_|Equal6~0 ( // Equation(s): -// \z80_|execute_|ctl_mWrite~4_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal52~0_combout ))) +// \z80_|pla_decode_|Equal6~0_combout = (!\z80_|decode_state_|DFFE_instED~q & (!\z80_|decode_state_|DFFE_instCB~q & (!\z80_|ir_|opcode [7] & !\z80_|ir_|opcode [6]))) - .dataa(\z80_|ir_|opcode [3]), - .datab(\z80_|pla_decode_|Equal3~1_combout ), - .datac(\z80_|ir_|opcode [0]), - .datad(\z80_|pla_decode_|Equal52~0_combout ), + .dataa(\z80_|decode_state_|DFFE_instED~q ), + .datab(\z80_|decode_state_|DFFE_instCB~q ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|ir_|opcode [6]), .cin(gnd), - .combout(\z80_|execute_|ctl_mWrite~4_combout ), + .combout(\z80_|pla_decode_|Equal6~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_mWrite~4 .lut_mask = 16'h4000; -defparam \z80_|execute_|ctl_mWrite~4 .sum_lutc_input = "datac"; +defparam \z80_|pla_decode_|Equal6~0 .lut_mask = 16'h0001; +defparam \z80_|pla_decode_|Equal6~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y17_N20 -cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~2 ( +// Location: LCCOMB_X21_Y16_N4 +cycloneive_lcell_comb \z80_|pla_decode_|Equal12~0 ( // Equation(s): -// \z80_|execute_|ctl_apin_mux~2_combout = ((\z80_|execute_|ctl_mWrite~4_combout & \z80_|execute_|ctl_apin_mux~1_combout )) # (!\z80_|execute_|ctl_inc_dec~6_combout ) +// \z80_|pla_decode_|Equal12~0_combout = (!\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [0]))) - .dataa(\z80_|execute_|ctl_mWrite~4_combout ), - .datab(\z80_|execute_|ctl_apin_mux~1_combout ), - .datac(\z80_|execute_|ctl_inc_dec~6_combout ), + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|pla_decode_|Equal6~0_combout ), + .datac(\z80_|ir_|opcode [1]), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal12~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal12~0 .lut_mask = 16'h0040; +defparam \z80_|pla_decode_|Equal12~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~16 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~16_combout = (\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal12~0_combout & \z80_|ir_|opcode [3]))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|ir_|opcode [4]), + .datac(\z80_|pla_decode_|Equal12~0_combout ), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~16 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_mRead~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|fMRead~24 ( +// Equation(s): +// \z80_|execute_|fMRead~24_combout = (\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_mRead~16_combout ) # ((\z80_|execute_|ctl_mRead~15_combout )))) # (!\z80_|execute_|ctl_ir_we~4_combout & (\z80_|execute_|ctl_alu_oe~0_combout & +// ((\z80_|execute_|ctl_mRead~16_combout ) # (\z80_|execute_|ctl_mRead~15_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~4_combout ), + .datab(\z80_|execute_|ctl_mRead~16_combout ), + .datac(\z80_|execute_|ctl_mRead~15_combout ), + .datad(\z80_|execute_|ctl_alu_oe~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~24 .lut_mask = 16'hFCA8; +defparam \z80_|execute_|fMRead~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N12 +cycloneive_lcell_comb \z80_|execute_|fMRead~25 ( +// Equation(s): +// \z80_|execute_|fMRead~25_combout = ((\z80_|execute_|fMRead~24_combout ) # ((\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|pc_inc_hold~26_combout ))) # (!\z80_|execute_|ctl_bus_db_oe~0_combout ) + + .dataa(\z80_|execute_|ctl_bus_db_oe~0_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|fMRead~24_combout ), + .datad(\z80_|execute_|pc_inc_hold~26_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~25 .lut_mask = 16'hF5FD; +defparam \z80_|execute_|fMRead~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y16_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~21 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~21_combout = (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|decode_state_|in_halt~q & (!\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal77~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|decode_state_|in_halt~q ), + .datac(\z80_|decode_state_|use_ixiy~combout ), + .datad(\z80_|pla_decode_|Equal77~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~21 .lut_mask = 16'h0200; +defparam \z80_|execute_|ctl_mRead~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|fMRead~16 ( +// Equation(s): +// \z80_|execute_|fMRead~16_combout = (\z80_|execute_|ctl_ir_we~11_combout ) # ((\z80_|execute_|ctl_ir_we~12_combout ) # ((\z80_|execute_|ctl_mRead~13_combout ) # (\z80_|execute_|ctl_mRead~21_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~11_combout ), + .datab(\z80_|execute_|ctl_ir_we~12_combout ), + .datac(\z80_|execute_|ctl_mRead~13_combout ), + .datad(\z80_|execute_|ctl_mRead~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~16 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|fMRead~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y17_N28 +cycloneive_lcell_comb \z80_|execute_|fMRead~14 ( +// Equation(s): +// \z80_|execute_|fMRead~14_combout = (\z80_|execute_|ctl_ir_we~14_combout ) # ((\z80_|execute_|ctl_ir_we~8_combout ) # ((!\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal49~0_combout ))) + + .dataa(\z80_|decode_state_|use_ixiy~combout ), + .datab(\z80_|pla_decode_|Equal49~0_combout ), + .datac(\z80_|execute_|ctl_ir_we~14_combout ), + .datad(\z80_|execute_|ctl_ir_we~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~14 .lut_mask = 16'hFFF4; +defparam \z80_|execute_|fMRead~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y14_N2 +cycloneive_lcell_comb \z80_|execute_|fMRead~15 ( +// Equation(s): +// \z80_|execute_|fMRead~15_combout = (!\z80_|execute_|fMWrite~3_combout & ((\z80_|execute_|ctl_ir_we~11_combout ) # ((\z80_|execute_|ctl_mRead~4_combout ) # (\z80_|execute_|fMRead~14_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~11_combout ), + .datab(\z80_|execute_|ctl_mRead~4_combout ), + .datac(\z80_|execute_|fMRead~14_combout ), + .datad(\z80_|execute_|fMWrite~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~15 .lut_mask = 16'h00FE; +defparam \z80_|execute_|fMRead~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|fMRead~12 ( +// Equation(s): +// \z80_|execute_|fMRead~12_combout = (!\z80_|pla_decode_|Equal13~2_combout & (!\z80_|execute_|ctl_mRead~2_combout & (!\z80_|pla_decode_|Equal6~1_combout & \z80_|execute_|ctl_bus_db_oe~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(\z80_|execute_|ctl_mRead~2_combout ), + .datac(\z80_|pla_decode_|Equal6~1_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~12 .lut_mask = 16'h0100; +defparam \z80_|execute_|fMRead~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y14_N18 +cycloneive_lcell_comb \z80_|execute_|fMRead~11 ( +// Equation(s): +// \z80_|execute_|fMRead~11_combout = (((\z80_|execute_|ctl_mRead~11_combout ) # (\z80_|execute_|ctl_mRead~21_combout )) # (!\z80_|execute_|pc_inc_hold~6_combout )) # (!\z80_|execute_|nextM~3_combout ) + + .dataa(\z80_|execute_|nextM~3_combout ), + .datab(\z80_|execute_|pc_inc_hold~6_combout ), + .datac(\z80_|execute_|ctl_mRead~11_combout ), + .datad(\z80_|execute_|ctl_mRead~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~11 .lut_mask = 16'hFFF7; +defparam \z80_|execute_|fMRead~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|fMRead~13 ( +// Equation(s): +// \z80_|execute_|fMRead~13_combout = (\z80_|execute_|ctl_state_alu~2_combout & (((\z80_|execute_|ctl_ir_we~14_combout ) # (\z80_|execute_|fMRead~11_combout )) # (!\z80_|execute_|fMRead~12_combout ))) + + .dataa(\z80_|execute_|fMRead~12_combout ), + .datab(\z80_|execute_|ctl_ir_we~14_combout ), + .datac(\z80_|execute_|ctl_state_alu~2_combout ), + .datad(\z80_|execute_|fMRead~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~13 .lut_mask = 16'hF0D0; +defparam \z80_|execute_|fMRead~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y14_N6 +cycloneive_lcell_comb \z80_|execute_|fMRead~17 ( +// Equation(s): +// \z80_|execute_|fMRead~17_combout = (\z80_|execute_|fMRead~15_combout ) # ((\z80_|execute_|fMRead~13_combout ) # ((\z80_|execute_|fMRead~16_combout & \z80_|execute_|ctl_state_alu~4_combout ))) + + .dataa(\z80_|execute_|fMRead~16_combout ), + .datab(\z80_|execute_|fMRead~15_combout ), + .datac(\z80_|execute_|ctl_state_alu~4_combout ), + .datad(\z80_|execute_|fMRead~13_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~17 .lut_mask = 16'hFFEC; +defparam \z80_|execute_|fMRead~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|fMRead~22 ( +// Equation(s): +// \z80_|execute_|fMRead~22_combout = (\z80_|execute_|fMRead~17_combout ) # (((!\z80_|execute_|fMRead~21_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~40_combout )) # (!\z80_|execute_|ctl_sw_4d~2_combout )) + + .dataa(\z80_|execute_|fMRead~17_combout ), + .datab(\z80_|execute_|ctl_sw_4d~2_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~40_combout ), + .datad(\z80_|execute_|fMRead~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~22 .lut_mask = 16'hBFFF; +defparam \z80_|execute_|fMRead~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N22 +cycloneive_lcell_comb \z80_|execute_|fMRead~27 ( +// Equation(s): +// \z80_|execute_|fMRead~27_combout = ((\z80_|sequencer_|DFFE_M2_ff~q & (!\z80_|execute_|ixy_d~4_combout & \z80_|execute_|ctl_mRead~12_combout ))) # (!\z80_|execute_|fMRead~26_combout ) + + .dataa(\z80_|sequencer_|DFFE_M2_ff~q ), + .datab(\z80_|execute_|fMRead~26_combout ), + .datac(\z80_|execute_|ixy_d~4_combout ), + .datad(\z80_|execute_|ctl_mRead~12_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~27 .lut_mask = 16'h3B33; +defparam \z80_|execute_|fMRead~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N14 +cycloneive_lcell_comb \z80_|execute_|fMRead~37 ( +// Equation(s): +// \z80_|execute_|fMRead~37_combout = (\z80_|sequencer_|DFFE_M4_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|execute_|ctl_mRead~13_combout ) # (\z80_|execute_|ctl_state_alu~6_combout )))) + + .dataa(\z80_|sequencer_|DFFE_M4_ff~q ), + .datab(\z80_|execute_|ctl_mRead~13_combout ), + .datac(\z80_|sequencer_|DFFE_T1_ff~q ), + .datad(\z80_|execute_|ctl_state_alu~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~37_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~37 .lut_mask = 16'h0A08; +defparam \z80_|execute_|fMRead~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|fMRead~31 ( +// Equation(s): +// \z80_|execute_|fMRead~31_combout = (\z80_|pla_decode_|Equal33~3_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ixy_d~6_combout )))) # (!\z80_|pla_decode_|Equal33~3_combout & (\z80_|pla_decode_|Equal6~1_combout & +// ((\z80_|execute_|ixy_d~5_combout ) # (\z80_|execute_|ixy_d~6_combout )))) + + .dataa(\z80_|pla_decode_|Equal33~3_combout ), + .datab(\z80_|execute_|ixy_d~5_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|pla_decode_|Equal6~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~31 .lut_mask = 16'hFCA8; +defparam \z80_|execute_|fMRead~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N14 +cycloneive_lcell_comb \z80_|execute_|fMRead~29 ( +// Equation(s): +// \z80_|execute_|fMRead~29_combout = (\z80_|execute_|ctl_ir_we~5_combout & (\z80_|pla_decode_|Equal33~0_combout & ((\z80_|ir_|opcode [7]) # (\z80_|ir_|opcode [6])))) + + .dataa(\z80_|execute_|ctl_ir_we~5_combout ), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|pla_decode_|Equal33~0_combout ), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|execute_|fMRead~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~29 .lut_mask = 16'hA080; +defparam \z80_|execute_|fMRead~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|fMRead~30 ( +// Equation(s): +// \z80_|execute_|fMRead~30_combout = (\z80_|execute_|ctl_alu_shift_oe~14_combout & ((\z80_|execute_|ctl_ir_we~9_combout ) # ((\z80_|execute_|fMRead~29_combout ) # (\z80_|execute_|ctl_ir_we~10_combout )))) + + .dataa(\z80_|execute_|ctl_ir_we~9_combout ), + .datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ), + .datac(\z80_|execute_|fMRead~29_combout ), + .datad(\z80_|execute_|ctl_ir_we~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~30_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~30 .lut_mask = 16'hCCC8; +defparam \z80_|execute_|fMRead~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|fMRead~28 ( +// Equation(s): +// \z80_|execute_|fMRead~28_combout = ((\z80_|execute_|ixy_d~6_combout & ((\z80_|pla_decode_|Equal41~2_combout ) # (\z80_|pla_decode_|Equal9~1_combout )))) # (!\z80_|execute_|nextM~4_combout ) + + .dataa(\z80_|execute_|ixy_d~6_combout ), + .datab(\z80_|execute_|nextM~4_combout ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~28 .lut_mask = 16'hBBB3; +defparam \z80_|execute_|fMRead~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|fMRead~32 ( +// Equation(s): +// \z80_|execute_|fMRead~32_combout = ((\z80_|execute_|fMRead~31_combout ) # ((\z80_|execute_|fMRead~30_combout ) # (\z80_|execute_|fMRead~28_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ), + .datab(\z80_|execute_|fMRead~31_combout ), + .datac(\z80_|execute_|fMRead~30_combout ), + .datad(\z80_|execute_|fMRead~28_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~32 .lut_mask = 16'hFFFD; +defparam \z80_|execute_|fMRead~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|fMRead~33 ( +// Equation(s): +// \z80_|execute_|fMRead~33_combout = (\z80_|execute_|fMRead~27_combout ) # (((\z80_|execute_|fMRead~37_combout ) # (\z80_|execute_|fMRead~32_combout )) # (!\z80_|execute_|fMRead~6_combout )) + + .dataa(\z80_|execute_|fMRead~27_combout ), + .datab(\z80_|execute_|fMRead~6_combout ), + .datac(\z80_|execute_|fMRead~37_combout ), + .datad(\z80_|execute_|fMRead~32_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~33 .lut_mask = 16'hFFFB; +defparam \z80_|execute_|fMRead~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y14_N24 +cycloneive_lcell_comb \z80_|execute_|fMRead~23 ( +// Equation(s): +// \z80_|execute_|fMRead~23_combout = (\z80_|execute_|ctl_state_alu~3_combout & (((\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|fMRead~5_combout )) # (!\z80_|execute_|fMRead~4_combout ))) + + .dataa(\z80_|execute_|ctl_state_alu~3_combout ), + .datab(\z80_|execute_|fMRead~4_combout ), + .datac(\z80_|execute_|ctl_mRead~34_combout ), + .datad(\z80_|execute_|fMRead~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~23 .lut_mask = 16'hA2AA; +defparam \z80_|execute_|fMRead~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N26 +cycloneive_lcell_comb \z80_|execute_|fMRead~34 ( +// Equation(s): +// \z80_|execute_|fMRead~34_combout = (\z80_|execute_|fMRead~25_combout ) # ((\z80_|execute_|fMRead~22_combout ) # ((\z80_|execute_|fMRead~33_combout ) # (\z80_|execute_|fMRead~23_combout ))) + + .dataa(\z80_|execute_|fMRead~25_combout ), + .datab(\z80_|execute_|fMRead~22_combout ), + .datac(\z80_|execute_|fMRead~33_combout ), + .datad(\z80_|execute_|fMRead~23_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~34 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|fMRead~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y14_N14 +cycloneive_lcell_comb \z80_|execute_|fMRead~35 ( +// Equation(s): +// \z80_|execute_|fMRead~35_combout = ((\z80_|execute_|ctl_ir_we~12_combout ) # ((\z80_|execute_|ctl_mRead~21_combout ) # (!\z80_|execute_|fMRead~7_combout ))) # (!\z80_|execute_|fMWrite~1_combout ) + + .dataa(\z80_|execute_|fMWrite~1_combout ), + .datab(\z80_|execute_|ctl_ir_we~12_combout ), + .datac(\z80_|execute_|fMRead~7_combout ), + .datad(\z80_|execute_|ctl_mRead~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~35 .lut_mask = 16'hFFDF; +defparam \z80_|execute_|fMRead~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~19 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~19_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|pla_decode_|Equal33~3_combout ) # (!\z80_|execute_|ctl_al_we~5_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|sequencer_|DFFE_M3_ff~q ), + .datac(\z80_|pla_decode_|Equal33~3_combout ), + .datad(\z80_|execute_|ctl_al_we~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~19 .lut_mask = 16'h4044; +defparam \z80_|execute_|ctl_reg_sel_pc~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N16 +cycloneive_lcell_comb \z80_|execute_|fMRead~36 ( +// Equation(s): +// \z80_|execute_|fMRead~36_combout = (\z80_|execute_|fMRead~34_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~19_combout ) # ((!\z80_|execute_|fMRead~2_combout & \z80_|execute_|fMRead~35_combout ))) + + .dataa(\z80_|execute_|fMRead~34_combout ), + .datab(\z80_|execute_|fMRead~2_combout ), + .datac(\z80_|execute_|fMRead~35_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|fMRead~36_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|fMRead~36 .lut_mask = 16'hFFBA; +defparam \z80_|execute_|fMRead~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N22 +cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_re ( +// Equation(s): +// \z80_|pin_control_|bus_db_pin_re~combout = (\z80_|pin_control_|bus_db_pin_re~2_combout ) # ((\z80_|sequencer_|DFFE_T2_ff~q & \z80_|execute_|fMRead~36_combout )) + + .dataa(\z80_|sequencer_|DFFE_T2_ff~q ), + .datab(gnd), + .datac(\z80_|execute_|fMRead~36_combout ), + .datad(\z80_|pin_control_|bus_db_pin_re~2_combout ), + .cin(gnd), + .combout(\z80_|pin_control_|bus_db_pin_re~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pin_control_|bus_db_pin_re .lut_mask = 16'hFFA0; +defparam \z80_|pin_control_|bus_db_pin_re .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~118 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][4]~118_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [6]))) # (!\ula_|ps2_keyboard_|shiftreg [2] & +// (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [6]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][4]~118_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][4]~118 .lut_mask = 16'h1008; +defparam \ula_|zx_keyboard_|keys[2][4]~118 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~119 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][4]~119_combout = (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[2][4]~118_combout & \ula_|zx_keyboard_|keys[5][1]~34_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|zx_keyboard_|keys[2][4]~118_combout ), + .datad(\ula_|zx_keyboard_|keys[5][1]~34_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][4]~119_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][4]~119 .lut_mask = 16'h4000; +defparam \ula_|zx_keyboard_|keys[2][4]~119 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~120 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][4]~120_combout = (\ula_|zx_keyboard_|keys[2][4]~119_combout & ((!\ula_|zx_keyboard_|keys[2][4]~94_combout ))) # (!\ula_|zx_keyboard_|keys[2][4]~119_combout & (\ula_|zx_keyboard_|keys[2][4]~q )) + + .dataa(\ula_|zx_keyboard_|keys[2][4]~119_combout ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[2][4]~q ), + .datad(\ula_|zx_keyboard_|keys[2][4]~94_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][4]~120_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][4]~120 .lut_mask = 16'h50FA; +defparam \ula_|zx_keyboard_|keys[2][4]~120 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y9_N1 +dffeas \ula_|zx_keyboard_|keys[2][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[2][4]~120_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[2][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[2][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~129 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][4]~129_combout = (!\ula_|ps2_keyboard_|shiftreg [7] & (\ula_|ps2_keyboard_|scan_code_ready~q & (!\ula_|zx_keyboard_|Equal0~1_combout & \ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [7]), + .datab(\ula_|ps2_keyboard_|scan_code_ready~q ), + .datac(\ula_|zx_keyboard_|Equal0~1_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][4]~129_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][4]~129 .lut_mask = 16'h0400; +defparam \ula_|zx_keyboard_|keys[3][4]~129 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~116 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][4]~116_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [0]))) # (!\ula_|ps2_keyboard_|shiftreg [6] & +// (!\ula_|zx_keyboard_|extended~q & (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [0]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|zx_keyboard_|extended~q ), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][4]~116_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][4]~116 .lut_mask = 16'h0810; +defparam \ula_|zx_keyboard_|keys[3][4]~116 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~134 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][4]~134_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [1] & \ula_|zx_keyboard_|keys[3][4]~116_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [1]), + .datad(\ula_|zx_keyboard_|keys[3][4]~116_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][4]~134_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][4]~134 .lut_mask = 16'h4000; +defparam \ula_|zx_keyboard_|keys[3][4]~134 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~117 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][4]~117_combout = (\ula_|zx_keyboard_|keys[3][4]~129_combout & ((\ula_|zx_keyboard_|keys[3][4]~134_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][4]~134_combout & ((\ula_|zx_keyboard_|keys[3][4]~q +// ))))) # (!\ula_|zx_keyboard_|keys[3][4]~129_combout & (((\ula_|zx_keyboard_|keys[3][4]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[3][4]~129_combout ), + .datac(\ula_|zx_keyboard_|keys[3][4]~q ), + .datad(\ula_|zx_keyboard_|keys[3][4]~134_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][4]~117_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][4]~117 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[3][4]~117 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y8_N19 +dffeas \ula_|zx_keyboard_|keys[3][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[3][4]~117_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[3][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[3][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N6 +cycloneive_lcell_comb \D[4]~60 ( +// Equation(s): +// \D[4]~60_combout = (\z80_|address_pins_|abus[11]~19_combout & ((\z80_|address_pins_|abus[10]~24_combout ) # ((!\ula_|zx_keyboard_|keys[2][4]~q )))) # (!\z80_|address_pins_|abus[11]~19_combout & (!\ula_|zx_keyboard_|keys[3][4]~q & +// ((\z80_|address_pins_|abus[10]~24_combout ) # (!\ula_|zx_keyboard_|keys[2][4]~q )))) + + .dataa(\z80_|address_pins_|abus[11]~19_combout ), + .datab(\z80_|address_pins_|abus[10]~24_combout ), + .datac(\ula_|zx_keyboard_|keys[2][4]~q ), + .datad(\ula_|zx_keyboard_|keys[3][4]~q ), + .cin(gnd), + .combout(\D[4]~60_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~60 .lut_mask = 16'h8ACF; +defparam \D[4]~60 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~2 ( +// Equation(s): +// \ula_|zx_keyboard_|Equal0~2_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [3])) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|Equal0~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|Equal0~2 .lut_mask = 16'h000C; +defparam \ula_|zx_keyboard_|Equal0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][4]~121 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][4]~121_combout = (\ula_|zx_keyboard_|keys[1][4]~23_combout & ((\ula_|zx_keyboard_|Equal0~2_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|Equal0~2_combout & ((\ula_|zx_keyboard_|keys[1][4]~q ))))) # +// (!\ula_|zx_keyboard_|keys[1][4]~23_combout & (((\ula_|zx_keyboard_|keys[1][4]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[1][4]~23_combout ), + .datac(\ula_|zx_keyboard_|keys[1][4]~q ), + .datad(\ula_|zx_keyboard_|Equal0~2_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][4]~121_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][4]~121 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[1][4]~121 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y9_N9 +dffeas \ula_|zx_keyboard_|keys[1][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[1][4]~121_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[1][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[1][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~115 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][4]~115_combout = (\ula_|zx_keyboard_|keys[3][1]~27_combout & ((\ula_|zx_keyboard_|keys[0][4]~96_combout & ((!\ula_|zx_keyboard_|keys[0][4]~109_combout ))) # (!\ula_|zx_keyboard_|keys[0][4]~96_combout & +// (\ula_|zx_keyboard_|keys[0][4]~q )))) # (!\ula_|zx_keyboard_|keys[3][1]~27_combout & (((\ula_|zx_keyboard_|keys[0][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[3][1]~27_combout ), + .datab(\ula_|zx_keyboard_|keys[0][4]~96_combout ), + .datac(\ula_|zx_keyboard_|keys[0][4]~q ), + .datad(\ula_|zx_keyboard_|keys[0][4]~109_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][4]~115_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][4]~115 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[0][4]~115 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y9_N31 +dffeas \ula_|zx_keyboard_|keys[0][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[0][4]~115_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[0][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[0][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~4 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row~4_combout = ((\z80_|address_pins_|DFFE_apin_latch [8]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) # (!\ula_|zx_keyboard_|keys[0][4]~q ) + + .dataa(\ula_|zx_keyboard_|keys[0][4]~q ), + .datab(gnd), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [8]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row~4_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row~4 .lut_mask = 16'hFF5F; +defparam \ula_|zx_keyboard_|key_row~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N22 +cycloneive_lcell_comb \D[4]~61 ( +// Equation(s): +// \D[4]~61_combout = (\D[4]~60_combout & (\ula_|zx_keyboard_|key_row~4_combout & ((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][4]~q )))) + + .dataa(\D[4]~60_combout ), + .datab(\z80_|address_pins_|abus[9]~17_combout ), + .datac(\ula_|zx_keyboard_|keys[1][4]~q ), + .datad(\ula_|zx_keyboard_|key_row~4_combout ), + .cin(gnd), + .combout(\D[4]~61_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~61 .lut_mask = 16'h8A00; +defparam \D[4]~61 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~124 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][4]~124_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|extended~q & !\ula_|ps2_keyboard_|shiftreg [2])) # (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|zx_keyboard_|extended~q & \ula_|ps2_keyboard_|shiftreg +// [2])) + + .dataa(gnd), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|zx_keyboard_|extended~q ), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][4]~124_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][4]~124 .lut_mask = 16'h03C0; +defparam \ula_|zx_keyboard_|keys[4][4]~124 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~125 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][4]~125_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|zx_keyboard_|keys[4][4]~124_combout & (\ula_|zx_keyboard_|Equal0~2_combout & \ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|zx_keyboard_|keys[4][4]~124_combout ), + .datac(\ula_|zx_keyboard_|Equal0~2_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][4]~125_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][4]~125 .lut_mask = 16'h8000; +defparam \ula_|zx_keyboard_|keys[4][4]~125 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~126 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][4]~126_combout = (\ula_|zx_keyboard_|keys[0][0]~13_combout & ((\ula_|zx_keyboard_|keys[4][4]~125_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[4][4]~125_combout & ((\ula_|zx_keyboard_|keys[4][4]~q +// ))))) # (!\ula_|zx_keyboard_|keys[0][0]~13_combout & (((\ula_|zx_keyboard_|keys[4][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[0][0]~13_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[4][4]~q ), + .datad(\ula_|zx_keyboard_|keys[4][4]~125_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][4]~126_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][4]~126 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[4][4]~126 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y8_N7 +dffeas \ula_|zx_keyboard_|keys[4][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[4][4]~126_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[4][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[4][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N16 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~122 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][4]~122_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [2]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][4]~122_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][4]~122 .lut_mask = 16'h2000; +defparam \ula_|zx_keyboard_|keys[5][4]~122 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~123 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][4]~123_combout = (\ula_|zx_keyboard_|keys[6][4]~46_combout & ((\ula_|zx_keyboard_|keys[5][4]~122_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[5][4]~122_combout & (\ula_|zx_keyboard_|keys[5][4]~q +// )))) # (!\ula_|zx_keyboard_|keys[6][4]~46_combout & (((\ula_|zx_keyboard_|keys[5][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[6][4]~46_combout ), + .datab(\ula_|zx_keyboard_|keys[5][4]~122_combout ), + .datac(\ula_|zx_keyboard_|keys[5][4]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][4]~123_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][4]~123 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[5][4]~123 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y8_N1 +dffeas \ula_|zx_keyboard_|keys[5][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[5][4]~123_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[5][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[5][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N8 +cycloneive_lcell_comb \D[4]~62 ( +// Equation(s): +// \D[4]~62_combout = (\ula_|zx_keyboard_|keys[4][4]~q & (\z80_|address_pins_|abus[12]~21_combout & ((\z80_|address_pins_|abus[13]~20_combout ) # (!\ula_|zx_keyboard_|keys[5][4]~q )))) # (!\ula_|zx_keyboard_|keys[4][4]~q & +// ((\z80_|address_pins_|abus[13]~20_combout ) # ((!\ula_|zx_keyboard_|keys[5][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[4][4]~q ), + .datab(\z80_|address_pins_|abus[13]~20_combout ), + .datac(\z80_|address_pins_|abus[12]~21_combout ), + .datad(\ula_|zx_keyboard_|keys[5][4]~q ), + .cin(gnd), + .combout(\D[4]~62_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~62 .lut_mask = 16'hC4F5; +defparam \D[4]~62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~49 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][4]~49_combout = (\ula_|zx_keyboard_|keys[7][1]~21_combout & (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|zx_keyboard_|Equal0~2_combout & !\ula_|ps2_keyboard_|shiftreg [6]))) + + .dataa(\ula_|zx_keyboard_|keys[7][1]~21_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\ula_|zx_keyboard_|Equal0~2_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][4]~49_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][4]~49 .lut_mask = 16'h0080; +defparam \ula_|zx_keyboard_|keys[7][4]~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~3 ( +// Equation(s): +// \ula_|zx_keyboard_|shifted~3_combout = (\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [2]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|shifted~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|shifted~3 .lut_mask = 16'h00F0; +defparam \ula_|zx_keyboard_|shifted~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~127 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][4]~127_combout = (\ula_|zx_keyboard_|keys[7][4]~49_combout & ((\ula_|zx_keyboard_|shifted~3_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|shifted~3_combout & ((\ula_|zx_keyboard_|keys[7][4]~q ))))) # +// (!\ula_|zx_keyboard_|keys[7][4]~49_combout & (((\ula_|zx_keyboard_|keys[7][4]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[7][4]~49_combout ), + .datac(\ula_|zx_keyboard_|keys[7][4]~q ), + .datad(\ula_|zx_keyboard_|shifted~3_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][4]~127_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][4]~127 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[7][4]~127 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y7_N23 +dffeas \ula_|zx_keyboard_|keys[7][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[7][4]~127_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[7][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[7][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~128 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][4]~128_combout = (\ula_|zx_keyboard_|keys[6][4]~46_combout & ((\ula_|zx_keyboard_|keys[6][4]~18_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[6][4]~18_combout & ((\ula_|zx_keyboard_|keys[6][4]~q +// ))))) # (!\ula_|zx_keyboard_|keys[6][4]~46_combout & (((\ula_|zx_keyboard_|keys[6][4]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[6][4]~46_combout ), + .datac(\ula_|zx_keyboard_|keys[6][4]~q ), + .datad(\ula_|zx_keyboard_|keys[6][4]~18_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][4]~128_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][4]~128 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[6][4]~128 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y7_N9 +dffeas \ula_|zx_keyboard_|keys[6][4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[6][4]~128_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[6][4]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][4] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[6][4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N28 +cycloneive_lcell_comb \D[4]~63 ( +// Equation(s): +// \D[4]~63_combout = (\ula_|zx_keyboard_|keys[7][4]~q & (\z80_|address_pins_|abus[15]~22_combout & ((\z80_|address_pins_|abus[14]~23_combout ) # (!\ula_|zx_keyboard_|keys[6][4]~q )))) # (!\ula_|zx_keyboard_|keys[7][4]~q & +// (((\z80_|address_pins_|abus[14]~23_combout ) # (!\ula_|zx_keyboard_|keys[6][4]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[7][4]~q ), + .datab(\z80_|address_pins_|abus[15]~22_combout ), + .datac(\ula_|zx_keyboard_|keys[6][4]~q ), + .datad(\z80_|address_pins_|abus[14]~23_combout ), + .cin(gnd), + .combout(\D[4]~63_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~63 .lut_mask = 16'hDD0D; +defparam \D[4]~63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N6 +cycloneive_lcell_comb \D[4]~64 ( +// Equation(s): +// \D[4]~64_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[4]~61_combout & (\D[4]~62_combout & \D[4]~63_combout ))) + + .dataa(\D[4]~61_combout ), + .datab(\D[4]~62_combout ), + .datac(\z80_|address_pins_|abus[0]~16_combout ), + .datad(\D[4]~63_combout ), + .cin(gnd), + .combout(\D[4]~64_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~64 .lut_mask = 16'hF8F0; +defparam \D[4]~64 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y5_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a28 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[4]~76_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a28_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_first_bit_number = 4; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y6_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a20 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[4]~76_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_first_bit_number = 4; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y11_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a12 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[4]~76_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y9_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a4 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[4]~76_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N4 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ) # +// ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout & +// !\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8 .lut_mask = 16'hAAD8; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N14 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout = (\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ) # +// ((!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout & (((\ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout & +// \ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout ), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9 .lut_mask = 16'hACF0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y3_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a12 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'hA50276000854A0103840403E540424244404783E18807A08A47C54484448544A807E7E10005270182040407E4A1252124208084008404208420A4A42424A125A024428106448524A624A4A24425242522060108010543C00044A105424005E0031ED1E0529E507AE2F6FF1CD51D4C772A648E65F6532C28022061303F06C36CDBD319B55CB8E626C20E46C93C1463A0B1CE594F0ED3B62330C104DECE46CA6CD966B1386612C7B43980349408F36FB64C14342DAE26CE4D8D5E791388729D743B09A27AB81D71A14AB3D24E385B602248476D00249239514B58D3098504ACD119B99E9021B650A69494C22600667473128DA5010D2195982823226DED0ADFCB8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h5861917919344A4685CC0990862A11324792E761B6D41C0FCC0838C1C27211A2453FDC2219C225E421B320085A8FBFD0C42135B16448DFC226E09B3438A740C352979565817114DE46462844A57F7958873FC4B255C8AE549BDD1A87415D5018F88D5002628FFD13203066C850F10649F21319109208387641120B362124803F0678522BA2812C1454A502ED1A59CBD76A034756F5765DF7555F57575F7F57FFFF7FFF7D5712524D4A30723514B2B3064A84B4742D48415281863DDFAA9D9B7E7BB16DDB96B7845371C30B55DB96C8F6EB4B453242FF6A4DF84A76B5AEDC88A68DC6A06905054C8C36E4199E74638E6532965218A965909BA456000451343351; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'hE2975A2686A7AE0288F140141B698E2A82A835F478453A1D722CFCED12859FD735188757AC5A42DEB501FE010586249AC1EA60D08F74CFA5086EC78FC9190C056059E332C311521E6522901852D484B423A98816C9B26A08C92368E9FF05524502288A804612A2A0A102A418CBDFBA554499541660F8124640110101263142892A086B442661015380041594608092D9CB919250100A37DDA3919A1427F660963C251301FB2CA45562245308885131119115C652B2493252340201101942D26000CC60799124A8520C08050122171281808058018C38A645D07931896B39ED259A22242CB58413089465B246231330D806105010035100B08761A08506094160; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h1228D91C352915424000000AA0088F63153A8AD81B945C8789F01C86548D12CEAB6AA38578BD55CEC9AA28082C285B8C0201104838AD502AC160C13C70620B818249144AB52CED94200A0202A885100E0D938A30A34512C0CEC98F08A98900F2093E11673256B3169C12284980E92A034141E0782507800F8100009C403C07867000000030082004A17800828F090A0C318CE120012172286317922341A2A12840B6C18040682080125C75401AEC44E8C01A8D40D1412B25A09F7600B0C6FEC65BFE5CE861A20F71E8032916A78F29CC546518461522E4E14998DD54BC0E40B64B710C9DC948F06010DF01D880E2044BE8854062D10DD93F30A62AA7FD227C4C; +// synopsys translate_on + +// Location: M9K_X33_Y27_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a12 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(gnd), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[4]~76_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_first_bit_number = 4; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y24_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a4 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[4]~76_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a4_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_first_bit_number = 4; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFFF0000003E0000003E0000C83F0000D83F0000F03F0000303E0000303E0000003F0010003F0010203F0010F03F0010703F0018303F001C603D800C003CFE26003C7F0F803FFFFFFFFFFFFFFFF; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF00000000000008108000BDF288E9688E000000000000000000000000FFFFFFFF0000000000041D989EA296D29EE969CA000000000000000000000000000000007FFFFFFC8004198A9AA298929EE9498A00000000000000000000000000000000FFFFFFFE800400CA9AA2AADA8AE949CE0000000000000000000000007FFFFFFEC00000028004046A9F22BA5A9EE90FC20000000000000000000000007FFFFFFE8000000280040FEA8002AA7A9EE12742000000000000000000000000000000023FFFFFFC9FE42BA298E2293A80096742000000000000000000000000000000003FFFFFFC9FE4B19298E3181E8009436A; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'h9FE8234A88F836EE9FF8BD4208282BC080DE87C2B84199C2B85E37C2B05B3A829FE8236688F837CE9FF8898208A82A44808A87CAB9C19DC2B80E3AC2927F2AC2800833E288F837C69FE8AB9688882E4283248DC2B9D188C2ABAE2F8291371092800832EA887807C69FE8AB8688080AC283E49D42B914BFC2A3BF1E82910712EA800802EA883807869DE88E8688080AC68BC4BDC2BB1439C2A27F5F82910314E2800886E6880807C69CC89A8681800BC289549CC2AB0C3942A04B7F82953315E2800886EE900805C61C089FC081E415C289D89DC2AB4E3142A1233D8217330090800086EE900805821C08BEC080D407C289C89DC2AADE3142A13B7F82176300F0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h076B0A5083288F028370C182A801468297E5AC1288D308023FFFFFFC00000000072BA9608BA08D028BF4D182AC015682937CA80288D308023FFFFFFC00000002872B892A8FA08F028A14509AAC0166B2B37DA80288D10D02800000027FFFFFFE852BAD128E388D028A004082AC0166C2937DA00288D10F02C00000027FFFFFFE846289368968C90289E0528A8C016CA29379B20280510F02FFFFFFFE0000000085E2A922816089828BE0428286416C829179B00280511F027FFFFFFC0000000087EA8B32872089828800569287436CA28179B20200513F0000000000FFFFFFFF8768A3028610858288004682874364828019900200403E0000000000FFFFFFFF; +// synopsys translate_on + +// Location: M9K_X33_Y4_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a4 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h35861A00A6112A1481AF1A50A6004A05291627227FF08229B87389E08119A28A7888672DC999B7046A61E60810A7434450E3D33E330F321A18E8A120D1EDC8623DA2C64840C2CCE811522B42008095E5A456C98F4B25EAEA410610545024640CF10410AC463BF9349074917E9A74A12830EFA280EBD3131E484A255D0191C6852730A263DBCCAAA88712242B3BE49AA5338990229B391158C726BC7EB4ECC32308980020680249882691A680488292310B4313CE87FFCD5329A64B708CAC8533316412C4900F646A36630261DA093053D98F19D2C5B653165D4A71AA5682B29B89B6054CC727D292805705A93268676A31111371390B240EC3CC85D331813EB1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h1AA1C248D293110CB951445117D9B6AA500F65068B8CC508BD00184F8705B010A0CC46CC9302649242CE08191634113154562B149100204551178DE805D98EC8A2E5A64B241400267194CD524499BC01D31058CD18684A817A5800B65143281C1310B00A49902C0104004C654E0582040001103654011012021912281216B000C653A0510A1B00C36AC88058CAC126E14E198DFB07E81C3F41510BB08F8F851C3B9AF0147BC1F730B4E91D9D11C3A8F1B82DF19988ACC44072FDB17B4D81882E9DD952B29003D7767BA581A68BC41C2B16AD6EB57F1D048CD4E464190D25ADF2C194E3598360AFB031A1690F4625BB628363B4C90A400E3A04DAA70DA0CC4776; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'hC82B30671933680037A65978674DDEC2D30EEEDA78F5F2A1DEE660FFEA11B175DCB42E9277212A58842051A078007109A0D820166B881042600284403143048295D23A0E191EBC2134B833D53D37E42B05018289A10300A188E315CE98640F548A370D60A0AA3E7288A0B0869FA5E703D1AE17C0EC276B2AFB747B550A8B41021620D1A60A901095D12A0973B95E20838001330138951361967847D42901910A3488480610A91A851E84FF08783F81AEA52D2FDC2200BD2FE81C0357FBEC1D875686C6CA41B2224C88D8456C1DBF20D820A6649774CB11B69933246E9739C998470542C2E3C783A4C24767084C52DC209D60E95DBC096D9A0171A12D5AB99BAB; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h17A24D2C636ED2478B5AE1C99D40761B1E7AA6A89DDD1BBD8DBD223E70531BCDE90C8E38C8E0478AD8B388F94891C9673A50BC32478E083074657E8E0EA53BEE861F8BC1993560946D92D1C0C7F046A245B5849CB751FF15B97FCD50BC7B8524C13E7C640F3645082248D1CC14296E30DEA3057B35C641762CD00D40DABC27472251A60725008AAA056591C4000BB48C0BC29B8034A03400027B84769B520D9196968460CA3388A03ECB45F2C4B70F1829221000FFFC7FEC346F079F13079798EC2A08157331C6CC0E30884244916A0DE26D4D22454091290404A492016887E2111F830F9851184101370588A06D3BF9AE621A5F4E632A6799C83EFAAE06769D; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N24 +cycloneive_lcell_comb \Selector4~0 ( +// Equation(s): +// \Selector4~0_combout = (\z80_|address_pins_|abus[14]~23_combout & ((\Selector3~0_combout ) # ((\ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout )))) # (!\z80_|address_pins_|abus[14]~23_combout & (!\Selector3~0_combout & +// ((\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout )))) + + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\Selector3~0_combout ), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ), + .cin(gnd), + .combout(\Selector4~0_combout ), + .cout()); +// synopsys translate_off +defparam \Selector4~0 .lut_mask = 16'hB9A8; +defparam \Selector4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N14 +cycloneive_lcell_comb \Selector4~1 ( +// Equation(s): +// \Selector4~1_combout = (\Selector3~0_combout & ((\Selector4~0_combout & ((\ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ))) # (!\Selector4~0_combout & (\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout )))) # +// (!\Selector3~0_combout & (((\Selector4~0_combout )))) + + .dataa(\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ), + .datab(\Selector3~0_combout ), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ), + .datad(\Selector4~0_combout ), + .cin(gnd), + .combout(\Selector4~1_combout ), + .cout()); +// synopsys translate_off +defparam \Selector4~1 .lut_mask = 16'hF388; +defparam \Selector4~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N10 +cycloneive_lcell_comb \D[4]~86 ( +// Equation(s): +// \D[4]~86_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [15] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\Selector4~1_combout +// ))))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout )))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\z80_|address_pins_|DFFE_apin_latch [15]), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout ), + .datad(\Selector4~1_combout ), + .cin(gnd), + .combout(\D[4]~86_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~86 .lut_mask = 16'hF2D0; +defparam \D[4]~86 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N16 +cycloneive_lcell_comb \D[4]~75 ( +// Equation(s): +// \D[4]~75_combout = ((\Equal2~0_combout & (\D[4]~64_combout )) # (!\Equal2~0_combout & ((\D[4]~86_combout )))) # (!\Equal2~1_combout ) + + .dataa(\Equal2~1_combout ), + .datab(\D[4]~64_combout ), + .datac(\Equal2~0_combout ), + .datad(\D[4]~86_combout ), + .cin(gnd), + .combout(\D[4]~75_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~75 .lut_mask = 16'hDFD5; +defparam \D[4]~75 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N30 +cycloneive_lcell_comb \D[4]~76 ( +// Equation(s): +// \D[4]~76_combout = (\z80_|pin_control_|bus_db_pin_oe~15_combout & (((\z80_|data_pins_|dout [4] & \D[4]~75_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout & (((\D[4]~75_combout )) # (!\Equal2~1_combout ))) + + .dataa(\Equal2~1_combout ), + .datab(\z80_|data_pins_|dout [4]), + .datac(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .datad(\D[4]~75_combout ), + .cin(gnd), + .combout(\D[4]~76_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~76 .lut_mask = 16'hCF05; +defparam \D[4]~76 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N30 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[4] ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [4] = (\z80_|bus_control_|db[4]~19_combout & ((\z80_|execute_|ctl_bus_db_we~7_combout ) # ((\z80_|pin_control_|bus_db_pin_re~combout & \D[4]~76_combout )))) # (!\z80_|bus_control_|db[4]~19_combout & +// (\z80_|pin_control_|bus_db_pin_re~combout & ((\D[4]~76_combout )))) + + .dataa(\z80_|bus_control_|db[4]~19_combout ), + .datab(\z80_|pin_control_|bus_db_pin_re~combout ), + .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datad(\D[4]~76_combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [4]), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[4] .lut_mask = 16'hECA0; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[4] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y13_N31 +dffeas \z80_|data_pins_|dout[4] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [4]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|data_pins_|dout [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|data_pins_|dout[4] .is_wysiwyg = "true"; +defparam \z80_|data_pins_|dout[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N24 +cycloneive_lcell_comb \z80_|bus_control_|db[4]~18 ( +// Equation(s): +// \z80_|bus_control_|db[4]~18_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [4]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) + + .dataa(\z80_|bus_control_|db[0]~4_combout ), + .datab(\z80_|data_pins_|dout [4]), + .datac(gnd), + .datad(\z80_|execute_|ctl_bus_db_oe~combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[4]~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[4]~18 .lut_mask = 16'h88AA; +defparam \z80_|bus_control_|db[4]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N0 +cycloneive_lcell_comb \z80_|bus_control_|db[4]~19 ( +// Equation(s): +// \z80_|bus_control_|db[4]~19_combout = ((\z80_|bus_control_|db[4]~18_combout & ((\z80_|alu_control_|db[4]~32_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) + + .dataa(\z80_|bus_control_|db[0]~6_combout ), + .datab(\z80_|bus_control_|db[4]~18_combout ), + .datac(\z80_|alu_control_|db[4]~32_combout ), + .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[4]~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[4]~19 .lut_mask = 16'hD5DD; +defparam \z80_|bus_control_|db[4]~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y17_N1 +dffeas \z80_|ir_|opcode[4] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|bus_control_|db[4]~19_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|ir_|opcode [4]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|ir_|opcode[4] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y17_N18 +cycloneive_lcell_comb \z80_|pla_decode_|Equal32~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal32~0_combout = (!\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3]) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [4]), + .datac(gnd), + .datad(\z80_|ir_|opcode [3]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal32~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal32~0 .lut_mask = 16'h3300; +defparam \z80_|pla_decode_|Equal32~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N18 +cycloneive_lcell_comb \z80_|pla_decode_|Equal41~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal41~1_combout = (\z80_|ir_|opcode [7] & (\z80_|ir_|opcode [6] & ((\z80_|decode_state_|DFFE_instIY1~q ) # (\z80_|decode_state_|DFFE_inst4~q )))) + + .dataa(\z80_|decode_state_|DFFE_instIY1~q ), + .datab(\z80_|decode_state_|DFFE_inst4~q ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal41~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal41~1 .lut_mask = 16'hE000; +defparam \z80_|pla_decode_|Equal41~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N12 +cycloneive_lcell_comb \z80_|pla_decode_|Equal41~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal41~2_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal32~0_combout & (\z80_|pla_decode_|Equal41~1_combout & \z80_|pla_decode_|Equal8~0_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal32~0_combout ), + .datac(\z80_|pla_decode_|Equal41~1_combout ), + .datad(\z80_|pla_decode_|Equal8~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal41~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal41~2 .lut_mask = 16'h4000; +defparam \z80_|pla_decode_|Equal41~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal36~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal36~0_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal1~7_combout & \z80_|pla_decode_|Equal32~0_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal2~0_combout ), + .datac(\z80_|pla_decode_|Equal1~7_combout ), + .datad(\z80_|pla_decode_|Equal32~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal36~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal36~0 .lut_mask = 16'h4000; +defparam \z80_|pla_decode_|Equal36~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_cb_set ( +// Equation(s): +// \z80_|execute_|ctl_state_tbl_cb_set~combout = (\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|pla_decode_|Equal41~2_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & +// ((\z80_|pla_decode_|Equal36~0_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & \z80_|pla_decode_|Equal41~2_combout )))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(\z80_|pla_decode_|Equal36~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_tbl_cb_set~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_tbl_cb_set .lut_mask = 16'hD5C0; +defparam \z80_|execute_|ctl_state_tbl_cb_set .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_state_tbl_we~8_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # ((\z80_|sequencer_|DFFE_T3_ff~q & \z80_|pla_decode_|Equal41~2_combout )))) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|pla_decode_|Equal41~2_combout ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_tbl_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_tbl_we~8 .lut_mask = 16'h00EC; +defparam \z80_|execute_|ctl_state_tbl_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y13_N9 +dffeas \z80_|decode_state_|DFFE_instCB ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|execute_|ctl_state_tbl_cb_set~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_state_tbl_we~8_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|decode_state_|DFFE_instCB~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instCB .is_wysiwyg = "true"; +defparam \z80_|decode_state_|DFFE_instCB .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y16_N2 +cycloneive_lcell_comb \z80_|pla_decode_|Equal52~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal52~0_combout = (!\z80_|decode_state_|DFFE_instCB~q & (!\z80_|decode_state_|DFFE_instED~q & (\z80_|ir_|opcode [7] & \z80_|ir_|opcode [6]))) + + .dataa(\z80_|decode_state_|DFFE_instCB~q ), + .datab(\z80_|decode_state_|DFFE_instED~q ), + .datac(\z80_|ir_|opcode [7]), + .datad(\z80_|ir_|opcode [6]), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal52~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal52~0 .lut_mask = 16'h1000; +defparam \z80_|pla_decode_|Equal52~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y16_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal2~1 ( +// Equation(s): +// \z80_|pla_decode_|Equal2~1_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal32~0_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal52~0_combout ), + .datac(\z80_|ir_|opcode [0]), + .datad(\z80_|pla_decode_|Equal32~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal2~1 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_ed_set ( +// Equation(s): +// \z80_|execute_|ctl_state_tbl_ed_set~combout = (\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal2~1_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & !\z80_|ir_|opcode [1]))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|pla_decode_|Equal2~1_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|ir_|opcode [1]), + .cin(gnd), + .combout(\z80_|execute_|ctl_state_tbl_ed_set~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_state_tbl_ed_set .lut_mask = 16'h0008; +defparam \z80_|execute_|ctl_state_tbl_ed_set .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y13_N13 +dffeas \z80_|decode_state_|DFFE_instED ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|execute_|ctl_state_tbl_ed_set~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_state_tbl_we~8_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|decode_state_|DFFE_instED~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|decode_state_|DFFE_instED .is_wysiwyg = "true"; +defparam \z80_|decode_state_|DFFE_instED .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N26 +cycloneive_lcell_comb \z80_|decode_state_|table_xx~0 ( +// Equation(s): +// \z80_|decode_state_|table_xx~0_combout = (\z80_|decode_state_|DFFE_instED~q ) # (\z80_|decode_state_|DFFE_instCB~q ) + + .dataa(\z80_|decode_state_|DFFE_instED~q ), + .datab(gnd), + .datac(gnd), + .datad(\z80_|decode_state_|DFFE_instCB~q ), + .cin(gnd), + .combout(\z80_|decode_state_|table_xx~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|decode_state_|table_xx~0 .lut_mask = 16'hFFAA; +defparam \z80_|decode_state_|table_xx~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N24 +cycloneive_lcell_comb \z80_|pla_decode_|Equal34~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal34~0_combout = (!\z80_|ir_|opcode [0] & (!\z80_|decode_state_|table_xx~0_combout & (\z80_|pla_decode_|Equal3~1_combout & \z80_|pla_decode_|Equal41~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|decode_state_|table_xx~0_combout ), + .datac(\z80_|pla_decode_|Equal3~1_combout ), + .datad(\z80_|pla_decode_|Equal41~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal34~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal34~0 .lut_mask = 16'h1000; +defparam \z80_|pla_decode_|Equal34~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~6 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~6_combout = (\z80_|execute_|ctl_alu_op_low~22_combout & (!\z80_|execute_|ixy_d~16_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|pla_decode_|Equal34~0_combout )))) # (!\z80_|execute_|ctl_alu_op_low~22_combout & +// (((!\z80_|execute_|ixy_d~5_combout )) # (!\z80_|pla_decode_|Equal34~0_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datab(\z80_|pla_decode_|Equal34~0_combout ), + .datac(\z80_|execute_|ixy_d~16_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~6 .lut_mask = 16'h135F; +defparam \z80_|execute_|ctl_reg_sel_pc~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~5 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~5_combout = ((!\z80_|execute_|ctl_mRead~6_combout & (!\z80_|execute_|ctl_mRead~7_combout & !\z80_|execute_|ctl_mRead~15_combout ))) # (!\z80_|execute_|ixy_d~5_combout ) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_mRead~6_combout ), + .datac(\z80_|execute_|ctl_mRead~7_combout ), + .datad(\z80_|execute_|ctl_mRead~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~5 .lut_mask = 16'h5557; +defparam \z80_|execute_|ctl_reg_sel_pc~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~4 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~4_combout = ((!\z80_|execute_|ixy_d~10_combout & ((!\z80_|pla_decode_|Equal24~0_combout ) # (!\z80_|pla_decode_|Equal21~0_combout )))) # (!\z80_|execute_|ctl_alu_op_low~22_combout ) + + .dataa(\z80_|execute_|ixy_d~10_combout ), + .datab(\z80_|pla_decode_|Equal21~0_combout ), + .datac(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datad(\z80_|pla_decode_|Equal24~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~4 .lut_mask = 16'h1F5F; +defparam \z80_|execute_|ctl_reg_sel_pc~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~2 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~2_combout = ((!\z80_|execute_|ctl_mRead~13_combout & ((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout )))) # (!\z80_|execute_|ixy_d~5_combout ) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_mRead~13_combout ), + .datac(\z80_|pla_decode_|Equal12~1_combout ), + .datad(\z80_|pla_decode_|Equal25~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~2 .lut_mask = 16'h7577; +defparam \z80_|execute_|ctl_reg_sel_pc~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~3_combout = (\z80_|execute_|ctl_reg_sel_pc~2_combout & (((!\z80_|pla_decode_|Equal19~0_combout & !\z80_|execute_|ctl_mRead~8_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) + + .dataa(\z80_|pla_decode_|Equal19~0_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~2_combout ), + .datac(\z80_|execute_|ctl_mRead~8_combout ), + .datad(\z80_|execute_|ixy_d~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~3 .lut_mask = 16'h04CC; +defparam \z80_|execute_|ctl_reg_sel_pc~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~7 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~7_combout = (\z80_|execute_|ctl_reg_sel_pc~6_combout & (\z80_|execute_|ctl_reg_sel_pc~5_combout & (\z80_|execute_|ctl_reg_sel_pc~4_combout & \z80_|execute_|ctl_reg_sel_pc~3_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~6_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~5_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~4_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~7 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_reg_sel_pc~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y16_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~8 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~8_combout = (\z80_|pla_decode_|Equal12~1_combout & (((\z80_|pla_decode_|Equal3~0_combout & \z80_|pla_decode_|Equal24~0_combout )))) # (!\z80_|pla_decode_|Equal12~1_combout & ((\z80_|pla_decode_|Equal25~0_combout ) # +// ((\z80_|pla_decode_|Equal3~0_combout & \z80_|pla_decode_|Equal24~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal12~1_combout ), + .datab(\z80_|pla_decode_|Equal25~0_combout ), + .datac(\z80_|pla_decode_|Equal3~0_combout ), + .datad(\z80_|pla_decode_|Equal24~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~8 .lut_mask = 16'hF444; +defparam \z80_|execute_|ctl_reg_sel_pc~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N26 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~9 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~9_combout = (\z80_|execute_|ctl_alu_op_low~22_combout & ((\z80_|execute_|ctl_mRead~15_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~8_combout ) # (\z80_|pla_decode_|Equal34~0_combout )))) + + .dataa(\z80_|execute_|ctl_alu_op_low~22_combout ), + .datab(\z80_|execute_|ctl_mRead~15_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~8_combout ), + .datad(\z80_|pla_decode_|Equal34~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~9 .lut_mask = 16'hAAA8; +defparam \z80_|execute_|ctl_reg_sel_pc~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y16_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~10 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~10_combout = (\z80_|execute_|ctl_reg_sel_pc~7_combout & (!\z80_|execute_|ctl_reg_sel_pc~9_combout & ((!\z80_|pla_decode_|Equal41~2_combout ) # (!\z80_|execute_|ixy_d~5_combout )))) + + .dataa(\z80_|execute_|ixy_d~5_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~7_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~9_combout ), + .datad(\z80_|pla_decode_|Equal41~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~10 .lut_mask = 16'h040C; +defparam \z80_|execute_|ctl_reg_sel_pc~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N14 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~16 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~16_combout = (((\z80_|execute_|ctl_state_alu~3_combout & !\z80_|execute_|fMRead~4_combout )) # (!\z80_|execute_|ctl_apin_mux~0_combout )) # (!\z80_|execute_|ctl_reg_sel_pc~10_combout ) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~10_combout ), + .datab(\z80_|execute_|ctl_apin_mux~0_combout ), + .datac(\z80_|execute_|ctl_state_alu~3_combout ), + .datad(\z80_|execute_|fMRead~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~16 .lut_mask = 16'h77F7; +defparam \z80_|execute_|ctl_reg_sel_pc~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y17_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~17 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~17_combout = (\z80_|nM1_int~2_combout ) # ((\z80_|execute_|ctl_reg_sys_we~0_combout ) # ((!\z80_|execute_|ctl_sw_4u~1_combout ) # (!\z80_|execute_|ctl_inc_dec~12_combout ))) + + .dataa(\z80_|nM1_int~2_combout ), + .datab(\z80_|execute_|ctl_reg_sys_we~0_combout ), + .datac(\z80_|execute_|ctl_inc_dec~12_combout ), + .datad(\z80_|execute_|ctl_sw_4u~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~17 .lut_mask = 16'hEFFF; +defparam \z80_|execute_|ctl_reg_sel_pc~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y11_N0 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~15 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~15_combout = (\z80_|execute_|ctl_reg_sel_pc~19_combout ) # ((!\z80_|execute_|fMRead~2_combout & ((!\z80_|execute_|ctl_reg_sel_pc~14_combout ) # (!\z80_|execute_|setM1~38_combout )))) + + .dataa(\z80_|execute_|setM1~38_combout ), + .datab(\z80_|execute_|fMRead~2_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~14_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~19_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~15 .lut_mask = 16'hFF13; +defparam \z80_|execute_|ctl_reg_sel_pc~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~18 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_pc~18_combout = (\z80_|execute_|ctl_reg_sel_pc~16_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~17_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~15_combout ) # (!\z80_|execute_|ctl_reg_sel_pc~13_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~16_combout ), + .datab(\z80_|execute_|ctl_reg_sel_pc~17_combout ), + .datac(\z80_|execute_|ctl_reg_sel_pc~13_combout ), + .datad(\z80_|execute_|ctl_reg_sel_pc~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_pc~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_pc~18 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|ctl_reg_sel_pc~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X20_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~19 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sel_wz~19_combout = (((!\z80_|pla_decode_|Equal19~0_combout & !\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|sequencer_|M5~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(\z80_|sequencer_|DFFE_T3_ff~q ), + .datab(\z80_|pla_decode_|Equal19~0_combout ), + .datac(\z80_|sequencer_|M5~q ), + .datad(\z80_|pla_decode_|Equal34~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sel_wz~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sel_wz~19 .lut_mask = 16'h5F7F; +defparam \z80_|execute_|ctl_reg_sel_wz~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y14_N20 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~3 ( +// Equation(s): +// \z80_|reg_control_|reg_sel_pc~3_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout & (\z80_|execute_|ctl_reg_sel_wz~19_combout & (\z80_|reg_control_|reg_sel_pc~2_combout & \z80_|execute_|ctl_alu_sel_op2_neg~2_combout ))) + + .dataa(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ), + .datab(\z80_|execute_|ctl_reg_sel_wz~19_combout ), + .datac(\z80_|reg_control_|reg_sel_pc~2_combout ), + .datad(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_pc~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_pc~3 .lut_mask = 16'h4000; +defparam \z80_|reg_control_|reg_sel_pc~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N24 +cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc ( +// Equation(s): +// \z80_|reg_control_|reg_sel_pc~combout = (\z80_|execute_|ctl_reg_sel_pc~18_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & (!\z80_|execute_|ctl_reg_sel_wz~20_combout & \z80_|reg_control_|reg_sel_pc~3_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sel_pc~18_combout ), + .datab(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .datac(\z80_|execute_|ctl_reg_sel_wz~20_combout ), + .datad(\z80_|reg_control_|reg_sel_pc~3_combout ), + .cin(gnd), + .combout(\z80_|reg_control_|reg_sel_pc~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_control_|reg_sel_pc .lut_mask = 16'h0200; +defparam \z80_|reg_control_|reg_sel_pc .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y12_N24 +cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_72 ( +// Equation(s): +// \z80_|reg_file_|SYNTHESIZED_WIRE_72~combout = (\z80_|reg_control_|reg_sel_pc~combout & (!\z80_|reg_control_|reg_sys_we_hi~combout & \z80_|execute_|ctl_reg_sys_hilo[1]~35_combout )) + + .dataa(\z80_|reg_control_|reg_sel_pc~combout ), + .datab(gnd), + .datac(\z80_|reg_control_|reg_sys_we_hi~combout ), + .datad(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_72 .lut_mask = 16'h0A00; +defparam \z80_|reg_file_|SYNTHESIZED_WIRE_72 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N10 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~2 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[0]~2_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ) # ((\z80_|reg_control_|reg_sw_4d_hi~0_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~43_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[0]~2 .lut_mask = 16'hFFFE; +defparam \z80_|reg_file_|db_hi_as[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y14_N23 +dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|db_hi_as[5]~15_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_pc_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y14_N17 +dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|db_hi_as[5]~15_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ir_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N16 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~13 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[5]~13_combout = (\z80_|reg_file_|gdfx_temp1[5]~57_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # (!\z80_|reg_file_|gdfx_temp1[5]~57_combout & +// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) + + .dataa(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[5]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[5]~13 .lut_mask = 16'hB0BB; +defparam \z80_|reg_file_|db_hi_as[5]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N28 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~14 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[5]~14_combout = (\z80_|reg_file_|db_hi_as[5]~13_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ), + .datab(\z80_|reg_file_|b2v_latch_pc_hi|latch [5]), + .datac(gnd), + .datad(\z80_|reg_file_|db_hi_as[5]~13_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[5]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[5]~14 .lut_mask = 16'hDD00; +defparam \z80_|reg_file_|db_hi_as[5]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N22 +cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~15 ( +// Equation(s): +// \z80_|reg_file_|db_hi_as[5]~15_combout = ((\z80_|reg_file_|db_hi_as[5]~14_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[0]~2_combout ), + .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ), + .datac(\z80_|execute_|ctl_bus_inc_oe~43_combout ), + .datad(\z80_|reg_file_|db_hi_as[5]~14_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|db_hi_as[5]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|db_hi_as[5]~15 .lut_mask = 16'hDF55; +defparam \z80_|reg_file_|db_hi_as[5]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y14_N9 +dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X37_Y14_N23 +dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y14_N22 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~50 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~50_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (\z80_|reg_file_|b2v_latch_hl_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_hl2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (((\z80_|reg_file_|b2v_latch_hl2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ), + .datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [5]), + .datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~50_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~50 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[5]~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y16_N13 +dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af2_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y16_N12 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~53 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~53_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout & (\z80_|alu_|db[5]~24_combout & ((\z80_|reg_file_|b2v_latch_af2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) # +// (!\z80_|execute_|ctl_reg_in_hi~12_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) + + .dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ), + .datab(\z80_|alu_|db[5]~24_combout ), + .datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~53_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~53 .lut_mask = 16'hD0DD; +defparam \z80_|reg_file_|gdfx_temp1[5]~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y15_N19 +dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_sp_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X35_Y15_N17 +dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_wz_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N16 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~54 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~54_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (\z80_|reg_file_|b2v_latch_wz_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [5]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ), + .datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [5]), + .datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~54_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~54 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp1[5]~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X34_Y16_N3 +dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_ix_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X34_Y16_N21 +dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_iy_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y16_N2 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~52 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~52_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ), + .datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [5]), + .datad(\z80_|reg_file_|b2v_latch_iy_hi|latch [5]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~52_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~52 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[5]~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y16_N5 +dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X37_Y16_N19 +dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y16_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~51 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~51_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (\z80_|reg_file_|b2v_latch_bc2_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [5]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ), + .datab(\z80_|reg_file_|b2v_latch_bc_hi|latch [5]), + .datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]), + .datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~51_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~51 .lut_mask = 16'hC4F5; +defparam \z80_|reg_file_|gdfx_temp1[5]~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y16_N0 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~55 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~55_combout = (\z80_|reg_file_|gdfx_temp1[5]~53_combout & (\z80_|reg_file_|gdfx_temp1[5]~54_combout & (\z80_|reg_file_|gdfx_temp1[5]~52_combout & \z80_|reg_file_|gdfx_temp1[5]~51_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[5]~53_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[5]~54_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[5]~52_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[5]~51_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~55_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~55 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[5]~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y15_N27 +dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_af_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_af_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y15_N26 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[5]~14 ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_af_hi|db[5]~14_combout = (\z80_|execute_|ctl_reg_gp_we~8_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [5]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout )) + + .dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ), + .datab(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|latch [5]), + .datad(\z80_|reg_control_|reg_sel_af~0_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_af_hi|db[5]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_af_hi|db[5]~14 .lut_mask = 16'hFBFF; +defparam \z80_|reg_file_|b2v_latch_af_hi|db[5]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y15_N15 +dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de2_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N28 +cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_hi|latch[5]~feeder ( +// Equation(s): +// \z80_|reg_file_|b2v_latch_de_hi|latch[5]~feeder_combout = \z80_|reg_file_|gdfx_temp1[5]~57_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|b2v_latch_de_hi|latch[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[5]~feeder .lut_mask = 16'hFF00; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y15_N29 +dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|reg_file_|b2v_latch_de_hi|latch[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|reg_file_|b2v_latch_de_hi|latch [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[5] .is_wysiwyg = "true"; +defparam \z80_|reg_file_|b2v_latch_de_hi|latch[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y15_N14 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~49 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~49_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) # +// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))) + + .dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ), + .datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ), + .datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [5]), + .datad(\z80_|reg_file_|b2v_latch_de_hi|latch [5]), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~49_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~49 .lut_mask = 16'hF351; +defparam \z80_|reg_file_|gdfx_temp1[5]~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y15_N8 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~56 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~56_combout = (\z80_|reg_file_|gdfx_temp1[5]~50_combout & (\z80_|reg_file_|gdfx_temp1[5]~55_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[5]~14_combout & \z80_|reg_file_|gdfx_temp1[5]~49_combout ))) + + .dataa(\z80_|reg_file_|gdfx_temp1[5]~50_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[5]~55_combout ), + .datac(\z80_|reg_file_|b2v_latch_af_hi|db[5]~14_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[5]~49_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~56_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~56 .lut_mask = 16'h8000; +defparam \z80_|reg_file_|gdfx_temp1[5]~56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y15_N18 +cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~57 ( +// Equation(s): +// \z80_|reg_file_|gdfx_temp1[5]~57_combout = ((\z80_|reg_file_|gdfx_temp1[5]~56_combout & ((\z80_|reg_file_|db_hi_as[5]~15_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout ) + + .dataa(\z80_|reg_file_|db_hi_as[5]~15_combout ), + .datab(\z80_|execute_|ctl_sw_4u~6_combout ), + .datac(\z80_|reg_file_|gdfx_temp1[0]~20_combout ), + .datad(\z80_|reg_file_|gdfx_temp1[5]~56_combout ), + .cin(gnd), + .combout(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|reg_file_|gdfx_temp1[5]~57 .lut_mask = 16'hBF0F; +defparam \z80_|reg_file_|gdfx_temp1[5]~57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N14 +cycloneive_lcell_comb \z80_|alu_|db[5]~23 ( +// Equation(s): +// \z80_|alu_|db[5]~23_combout = (\z80_|alu_control_|db[5]~15_combout & ((\z80_|reg_file_|gdfx_temp1[5]~57_combout ) # ((!\z80_|execute_|ctl_reg_out_hi~7_combout )))) # (!\z80_|alu_control_|db[5]~15_combout & (!\z80_|execute_|ctl_sw_2d~13_combout & +// ((\z80_|reg_file_|gdfx_temp1[5]~57_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) + + .dataa(\z80_|alu_control_|db[5]~15_combout ), + .datab(\z80_|reg_file_|gdfx_temp1[5]~57_combout ), + .datac(\z80_|execute_|ctl_reg_out_hi~7_combout ), + .datad(\z80_|execute_|ctl_sw_2d~13_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[5]~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[5]~23 .lut_mask = 16'h8ACF; +defparam \z80_|alu_|db[5]~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y15_N14 +cycloneive_lcell_comb \z80_|alu_|db[5]~24 ( +// Equation(s): +// \z80_|alu_|db[5]~24_combout = ((\z80_|alu_|db[5]~23_combout & ((\z80_|alu_|db_high[1]~19_combout ) # (!\z80_|execute_|ctl_alu_oe~11_combout )))) # (!\z80_|alu_|db[7]~9_combout ) + + .dataa(\z80_|alu_|db[5]~23_combout ), + .datab(\z80_|alu_|db_high[1]~19_combout ), + .datac(\z80_|alu_|db[7]~9_combout ), + .datad(\z80_|execute_|ctl_alu_oe~11_combout ), + .cin(gnd), + .combout(\z80_|alu_|db[5]~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_|db[5]~24 .lut_mask = 16'h8FAF; +defparam \z80_|alu_|db[5]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N26 +cycloneive_lcell_comb \z80_|sw1_|db_down[5]~0 ( +// Equation(s): +// \z80_|sw1_|db_down[5]~0_combout = (\z80_|bus_control_|db[5]~15_combout ) # ((\z80_|execute_|ctl_sw_1d~6_combout & ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|execute_|ctl_66_oe~2_combout )))) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|execute_|ctl_sw_1d~6_combout ), + .datac(\z80_|bus_control_|db[5]~15_combout ), + .datad(\z80_|execute_|ctl_66_oe~2_combout ), + .cin(gnd), + .combout(\z80_|sw1_|db_down[5]~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sw1_|db_down[5]~0 .lut_mask = 16'hF8FC; +defparam \z80_|sw1_|db_down[5]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y15_N22 +cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_36 ( +// Equation(s): +// \z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout = (\z80_|execute_|ctl_flags_bus~combout & ((\z80_|alu_control_|db[5]~15_combout ) # ((\z80_|alu_|db_high[1]~19_combout & \z80_|execute_|ctl_flags_alu~15_combout )))) # (!\z80_|execute_|ctl_flags_bus~combout +// & (\z80_|alu_|db_high[1]~19_combout & (\z80_|execute_|ctl_flags_alu~15_combout ))) + + .dataa(\z80_|execute_|ctl_flags_bus~combout ), + .datab(\z80_|alu_|db_high[1]~19_combout ), + .datac(\z80_|execute_|ctl_flags_alu~15_combout ), + .datad(\z80_|alu_control_|db[5]~15_combout ), + .cin(gnd), + .combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_36 .lut_mask = 16'hEAC0; +defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y15_N23 +dffeas \z80_|alu_flags_|flags_yf ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_flags_xy_we~18_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|alu_flags_|flags_yf~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|alu_flags_|flags_yf .is_wysiwyg = "true"; +defparam \z80_|alu_flags_|flags_yf .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N26 +cycloneive_lcell_comb \z80_|alu_control_|db[5]~13 ( +// Equation(s): +// \z80_|alu_control_|db[5]~13_combout = (\z80_|execute_|ctl_flags_oe~2_combout & (\z80_|alu_flags_|flags_yf~q & ((\z80_|alu_control_|out[6]~2_combout ) # (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout )))) # (!\z80_|execute_|ctl_flags_oe~2_combout & +// ((\z80_|alu_control_|out[6]~2_combout ) # ((\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout )))) + + .dataa(\z80_|execute_|ctl_flags_oe~2_combout ), + .datab(\z80_|alu_control_|out[6]~2_combout ), + .datac(\z80_|alu_flags_|flags_yf~q ), + .datad(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[5]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[5]~13 .lut_mask = 16'hF5C4; +defparam \z80_|alu_control_|db[5]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N8 +cycloneive_lcell_comb \z80_|alu_control_|db[5]~14 ( +// Equation(s): +// \z80_|alu_control_|db[5]~14_combout = (\z80_|sw1_|db_down[5]~0_combout & (\z80_|alu_control_|db[5]~13_combout & ((\z80_|reg_file_|gdfx_temp0[5]~72_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout )))) + + .dataa(\z80_|sw1_|db_down[5]~0_combout ), + .datab(\z80_|alu_control_|db[5]~13_combout ), + .datac(\z80_|reg_file_|gdfx_temp0[5]~72_combout ), + .datad(\z80_|execute_|ctl_reg_out_lo~8_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[5]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[5]~14 .lut_mask = 16'h8088; +defparam \z80_|alu_control_|db[5]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y14_N14 +cycloneive_lcell_comb \z80_|alu_control_|db[5]~15 ( +// Equation(s): +// \z80_|alu_control_|db[5]~15_combout = ((\z80_|alu_control_|db[5]~14_combout & ((\z80_|alu_|db[5]~24_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout )))) # (!\z80_|alu_control_|db[6]~11_combout ) + + .dataa(\z80_|alu_|db[5]~24_combout ), + .datab(\z80_|execute_|ctl_sw_2u~7_combout ), + .datac(\z80_|alu_control_|db[5]~14_combout ), + .datad(\z80_|alu_control_|db[6]~11_combout ), + .cin(gnd), + .combout(\z80_|alu_control_|db[5]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|alu_control_|db[5]~15 .lut_mask = 16'hB0FF; +defparam \z80_|alu_control_|db[5]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y17_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a29 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[5]~77_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_first_bit_number = 5; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y15_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a13 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[5]~77_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_bit_number = 5; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y19_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a21 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[5]~77_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_first_bit_number = 5; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y22_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a5 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[5]~77_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_bit_number = 5; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N28 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ) # +// ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout & +// !\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10 .lut_mask = 16'hCCB8; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N18 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout & +// (\ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout )) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ))))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11 .lut_mask = 16'hAFC0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y31_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a13 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_bit_number = 5; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init3 = 2048'h990442000864A0284030400454782424440404007E404808A4005448387E547C8004420800620824402040024A1242124204044008404208420A4A42424A1242020028008000524A024A4A284252446240001000101042000054265C7E0600007FAF5CA001C181BE0C02418447B1D88BAA85409896BC7C0E5FAC2529CB69A4038E2564731F88FE730045956C357C5ECF7EF8591DF2A8ACFFBFEEF268CD9B51238594AF691A9B8640983B7F76AAB97209EA6257389992FFE684926E0B19FA338B8489D73811171D5C9FF3DCFFFFFF8002000780101F3F4035A0CDED99F79A4775854F179F7D7DBBCF81B2F6421FF684CA6AF85894D29B9D3ACCBA3F27D9DC9911; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init2 = 2048'h5B438D714D4E3DD115E8BD1286EAB5FA1D71BD8F4508BD4BDC8838F9D27B552259BCEFFBB68A6FF529B3B0D92970010BBB6C7D872421210E190E1CCC47A485EAD2F8735647315839EF6F683C64773FC73464D5FE354936D50823A5DAEBEBDBCC6CAFF2622B8D518F63C6030424188FD357718970D25A30CD0731E532DB23002D02C12B12378356DE2C52041CA7A320C51E0D7CA9F5D575775D57FD75DDFDF75FFFDFFFD75F145247F03A0AE7F1E1EB2D5A99D2444108C6A5979B7CC26ABCC241EA4C912568003BB493CE04FF086C188980052BF6ABAAA2FD5D658000011277EB924C10EFAF3CB9B62486512344C61ADE6F15AB67F335A52513FF05AFAEEE8400; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 2048'h0C840083AD485153ACD3C035591630199B8C096CE4DC557D6D55FCCD738573D6E0948817C496E9DE8EA1F88F627B7460106691CC452DB9799E59A5D003733C4EA1BCE33AD2D8BE40A4E5BB7D7BBEC2CEADBBC8B6F87A4A56FBE0B891DE57E4C64EF9AD87727C49CFE7C5DE942B72AC7F6D97DE18920777FDDEE9EB11122A4E18F5569FDE08906765428FB9E6F89FBF0DEAA6064637BCA63FD02E273E5557F0548662C97BC2E8D3FFDB26D23E87BFD97E635A6560CFD93F8EED26E30C70DE8633D6B97C86DF7D9BEDFB99E36B6658F16C6DEFBDD5DF728D6209C852C37FE67CFF32EE4CCCECC64F7E6225FC99EC64C3B6DD7DED0FD7CCEA3BF09A006ECDD1009E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'hA9C9CE3AECF7BE27C000000A8ABA95251B309A60B9DDC19EC3E391458CBB53CA00A85E3C5AAE2C49DDC2F6C7B013DACB319A769818A1081A7389F711D76A09BCBED23D9A99FF9B77183697955D76BF0E0008822742DA45B883C9193DAF09424501859565800698515E10A8189EE9B323E35CE7388D73C6E7A50D0DE6739C73AC538D134115D860ADA57B5B868E54393B1E31E762062577697D57E8464340420E9434CCA34CC9A1CB1FAACC56168071EAC113F5265D5F6A45A098D604A820508C4EA47F9A7E46083716911B0D585CE937B530218E8D2AD3777EE7D3B4BC56C29ADB46809D15D185F8809229B150C29C8081174CA6173B99703DA466629005C604; +// synopsys translate_on + +// Location: M9K_X33_Y1_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a5 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_bit_number = 5; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init3 = 2048'hE10F8B8C100323720BEBBDEBB81DF13FF97B252E2CB4F27BA091FBD0002D1A611E1EDBBC716D44D2912B80041C44558060CFCF15955C0D780DD5E71393920844F25E16C87C5D0308EEC52C011514BBC13AFA1028924D0C7CE738105BD47A10AA5B5C1D9D4193E4339F492B0E1A64E13AE35BE6B67AC8057BDACC155F14E906A017A1841358335450D4B26CD2A21B3D8F2211080B81EC040D7FA0B51CD48008112508062020A02490900092D2040259108806A328F4006D2AA514B42FB006ECCCCB9A360865678449975A8AE72B5C0F7BA800C1B5DC55D7D6FE2EF4EED85D00AB111821321BA426A4FE4956B43595832C271E83E060341AE5F2023FC808177383; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init2 = 2048'h1A2955372D510AC266A5445146E27000020C320FAE1557E37154040A13202DC6F40B840FB9A59B6DBB296562CB6220EFBE99D2776A202044D9101006FD221D305519198C859000004012AFF4FB060307C92BB732203BFDFEFFFFFFDFFF87FCFFFBFFEFF03FFE0FFFBFAFE0FF80787FFF7FFF83F7F87003FFBFFFFBFFFBFF0FFC0FF81FFF7FFBFFDFFFBFFFE1FF0086F3141AAB6005810A0621595A893F9D85983B9254954341968BAC8C141C90938C05B2C9CD267E11650407375FEDD6A2FEB346AAF6CFDC0791AA97B741995A3B3981E06D1A44D3711955197BB9910FCA20744915C84D6C24BAF53929814CA8A4697E8F4201145AE7415DC122A5F010436107; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048'h02E84F969E3C800AC610D276182020227809001A50DDDBA3487BB6AE802BA06509312DA0E620656EAF24D57C08FFB14D289613DC32083803B84DC6415FD5EDC000300A8D128FA20030ACCBAFA237B7024504D36A4BA26081137F059E78991154FE2AC2A884A8CC7FBBB21C851CC92B12E15593C0C020FFEE066558590E882D5B67459F1A8C3240FE4E6A8D028C0C088FCF471D400A19B38211004DD122212288B111114514CB11840E04828849C621392041163C00808C67223422F00110201DD18FCFFFF3FFE7F9FFFFFFF82C0B422D214711E08904524A069491774E663F48F665955B4E2C63DAC0078652D10120900298F7EE380092442AFD400BEC43C003; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'hB5D49EA9D7036A45AA9E870B8E8016720C7C3102AE925262492C84584942D209042216E0216C85B8912250B7157D5955AD406CB685BBF071B47D5193363C1CECAFE59E91BF11498940A0944996D47EE8D7E3A4EAE611AE19A965D01BA86B55E9C52A6A379A382C6C265FB0DA01396D0800C0046405C06F466DD18C4DD7655CD4E7622EC485808C841D64B737041FF68813B149A41531A0A692FB14AE2E5B49D49CDCADCF90E7BD88125BCE706BF6D04AABFC1C001163DC6EFF7FD3230303030000000000000000000008400000000000000000000000000030600000100007E00220000000000000080040004023AD496997B8C0077B886EEF161CF2298A091B; +// synopsys translate_on + +// Location: M9K_X33_Y25_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a13 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(gnd), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[5]~77_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_bit_number = 5; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_first_bit_number = 5; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X33_Y28_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a5 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[5]~77_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a5_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_bit_number = 5; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_first_bit_number = 5; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init3 = 2048'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF80000001C000000160F000FF70C0007F78C00000F05001007870010010000000000800000038000000F000000070000000300000006000000000000040000000F00000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000000001D108000BEDA9FA9698A000000000000000000000000FFFFFFFF408102048004188297E014DA9FA9E9CA00000000000000000000000000000000FFFFFFFC800400CA972208DA9FA9CD8E00000000000000000000000000000000FFFFFFFC8004046A97A289FA9FA9CDC20000000000000000000000007FFFFFFC8000000280040E2A97A2997A9DA9CFC20000000000000000000000007FFFFFFE8000000280042EB28002BE369DA9274200000000000000000000000040810206BFFFFFFE9FE430A29D82AC3E8009E34A000000000000000000000000000000023FFFFFFC9FE4B1829FA2800E8009436A; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048'h9FE8334E88F827C697F88D1600A80A44809E8FC2B86999C2B85B3A82B1D32A869FE8336A88F807CA97F88F96A0A80EC2838E8D42B9E98FC2B86B3B82B0D7B2D2800832E288F827CA97F88B82A0080EC683869542B939B8C2B1AB0F8290B730C2800826EA8878078297F88AD2A0280EC283E694C2B83A3BC2A3AB3E8291A316AA800826EE881807C69DE8ABD6A0280BC282209CD2BA2A3D42A2737F82918314E2800806E6981805C69D48AED6A1E80BCA82709FC2BB223DC2A07B7F8295DF11C2800886E6980805869848AAC6A1E42DC281789DC2BBAA3DC6A02B7582955F00928008A6EE98082D9618088AC8A0F40FC289E89DC2BBCA3DC2A18B7782154F02F0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'h174F0870801C870281E2C982A801460297E5AC0288F318023FFFFFFC0000000297DF094A8094870281D6C082AC01460293FDA89288D31902BFFFFFFE40810106879F8D228C8685028016C082AC014642B3FCA80288D10F02800000027FFFFFFE879F893284DEC9028000408AAC014C02937DA00288D10F02800000027FFFFFFC841FA902804E81068BC04292AC0145E29379B00288D11F02FFFFFFFC0000000084FE89328166C1028BE05282AE4144829179B20288511F02FFFFFFFC0000000084F283328516850A88204602874364829179B08280513E0240810104FFFFFFFF843A8302853685828800560287476C928039B00200413E0000000000FFFFFFFF; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N20 +cycloneive_lcell_comb \Mux2~0 ( +// Equation(s): +// \Mux2~0_combout = (\Selector3~0_combout & (((\ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout )) # (!\z80_|address_pins_|abus[14]~23_combout ))) # (!\Selector3~0_combout & (\z80_|address_pins_|abus[14]~23_combout & +// ((\ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout )))) + + .dataa(\Selector3~0_combout ), + .datab(\z80_|address_pins_|abus[14]~23_combout ), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout ), + .cin(gnd), + .combout(\Mux2~0_combout ), + .cout()); +// synopsys translate_off +defparam \Mux2~0 .lut_mask = 16'hE6A2; +defparam \Mux2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N26 +cycloneive_lcell_comb \Mux2~1 ( +// Equation(s): +// \Mux2~1_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\Mux2~0_combout )))) # (!\z80_|address_pins_|abus[14]~23_combout & ((\Mux2~0_combout & (\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout )) # (!\Mux2~0_combout & +// ((\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ))))) + + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ), + .datad(\Mux2~0_combout ), + .cin(gnd), + .combout(\Mux2~1_combout ), + .cout()); +// synopsys translate_off +defparam \Mux2~1 .lut_mask = 16'hEE50; +defparam \Mux2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N8 +cycloneive_lcell_comb \D[5]~87 ( +// Equation(s): +// \D[5]~87_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [15] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\Mux2~1_combout ))))) # +// (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout )) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datab(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout ), + .datac(\Mux2~1_combout ), + .datad(\z80_|address_pins_|DFFE_apin_latch [15]), + .cin(gnd), + .combout(\D[5]~87_combout ), + .cout()); +// synopsys translate_off +defparam \D[5]~87 .lut_mask = 16'hCCE4; +defparam \D[5]~87 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N4 +cycloneive_lcell_comb \D[5]~68 ( +// Equation(s): +// \D[5]~68_combout = (\D[5]~67_combout & (\D[5]~87_combout & ((\z80_|data_pins_|dout [5]) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout )))) # (!\D[5]~67_combout & ((\z80_|data_pins_|dout [5]) # ((!\z80_|pin_control_|bus_db_pin_oe~15_combout )))) + + .dataa(\D[5]~67_combout ), + .datab(\z80_|data_pins_|dout [5]), + .datac(\D[5]~87_combout ), + .datad(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .cin(gnd), + .combout(\D[5]~68_combout ), + .cout()); +// synopsys translate_off +defparam \D[5]~68 .lut_mask = 16'hC4F5; +defparam \D[5]~68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N12 +cycloneive_lcell_comb \D[5]~77 ( +// Equation(s): +// \D[5]~77_combout = (\D[5]~68_combout ) # (!\D[0]~84_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\D[5]~68_combout ), + .datad(\D[0]~84_combout ), + .cin(gnd), + .combout(\D[5]~77_combout ), + .cout()); +// synopsys translate_off +defparam \D[5]~77 .lut_mask = 16'hF0FF; +defparam \D[5]~77 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N16 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[5] ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [5] = (\D[5]~77_combout & ((\z80_|pin_control_|bus_db_pin_re~combout ) # ((\z80_|execute_|ctl_bus_db_we~7_combout & \z80_|bus_control_|db[5]~15_combout )))) # (!\D[5]~77_combout & +// (((\z80_|execute_|ctl_bus_db_we~7_combout & \z80_|bus_control_|db[5]~15_combout )))) + + .dataa(\D[5]~77_combout ), + .datab(\z80_|pin_control_|bus_db_pin_re~combout ), + .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datad(\z80_|bus_control_|db[5]~15_combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [5]), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[5] .lut_mask = 16'hF888; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[5] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y13_N25 +dffeas \z80_|data_pins_|dout[5] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [5]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|data_pins_|dout [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|data_pins_|dout[5] .is_wysiwyg = "true"; +defparam \z80_|data_pins_|dout[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N10 +cycloneive_lcell_comb \z80_|bus_control_|db[5]~14 ( +// Equation(s): +// \z80_|bus_control_|db[5]~14_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [5]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_bus_db_oe~combout ), + .datac(\z80_|bus_control_|db[0]~4_combout ), + .datad(\z80_|data_pins_|dout [5]), + .cin(gnd), + .combout(\z80_|bus_control_|db[5]~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[5]~14 .lut_mask = 16'hF030; +defparam \z80_|bus_control_|db[5]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y17_N18 +cycloneive_lcell_comb \z80_|bus_control_|db[5]~15 ( +// Equation(s): +// \z80_|bus_control_|db[5]~15_combout = ((\z80_|bus_control_|db[5]~14_combout & ((\z80_|alu_control_|db[5]~15_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) + + .dataa(\z80_|bus_control_|db[0]~6_combout ), + .datab(\z80_|alu_control_|db[5]~15_combout ), + .datac(\z80_|bus_control_|db[5]~14_combout ), + .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[5]~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[5]~15 .lut_mask = 16'hD5F5; +defparam \z80_|bus_control_|db[5]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y16_N17 +dffeas \z80_|ir_|opcode[5] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|bus_control_|db[5]~15_combout ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|ir_|opcode [5]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|ir_|opcode[5] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y17_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~8 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~8_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal9~0_combout ))) + + .dataa(\z80_|ir_|opcode [5]), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|pla_decode_|Equal6~0_combout ), + .datad(\z80_|pla_decode_|Equal9~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~8 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_mRead~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~8 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_we~8_combout = (\z80_|sequencer_|M5~q & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|execute_|ctl_mRead~8_combout ) # (\z80_|pla_decode_|Equal9~1_combout )))) + + .dataa(\z80_|sequencer_|M5~q ), + .datab(\z80_|execute_|ctl_mRead~8_combout ), + .datac(\z80_|pla_decode_|Equal9~1_combout ), + .datad(\z80_|sequencer_|DFFE_T1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_we~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_we~8 .lut_mask = 16'h00A8; +defparam \z80_|execute_|ctl_bus_db_we~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y15_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~4 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_we~4_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mWrite~6_combout ) # ((\z80_|pla_decode_|Equal21~0_combout & \z80_|pla_decode_|Equal24~0_combout )))) + + .dataa(\z80_|pla_decode_|Equal21~0_combout ), + .datab(\z80_|pla_decode_|Equal24~0_combout ), + .datac(\z80_|execute_|ixy_d~7_combout ), + .datad(\z80_|execute_|ctl_mWrite~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_we~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_we~4 .lut_mask = 16'hF080; +defparam \z80_|execute_|ctl_bus_db_we~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y15_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~6 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_we~6_combout = (\z80_|execute_|ctl_bus_db_we~4_combout ) # (((!\z80_|execute_|ctl_apin_mux~0_combout ) # (!\z80_|execute_|ctl_sw_2u~3_combout )) # (!\z80_|execute_|ctl_bus_db_we~5_combout )) + + .dataa(\z80_|execute_|ctl_bus_db_we~4_combout ), + .datab(\z80_|execute_|ctl_bus_db_we~5_combout ), + .datac(\z80_|execute_|ctl_sw_2u~3_combout ), + .datad(\z80_|execute_|ctl_apin_mux~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_we~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_we~6 .lut_mask = 16'hBFFF; +defparam \z80_|execute_|ctl_bus_db_we~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y16_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout = (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal8~0_combout & \z80_|execute_|ctl_ir_we~4_combout ))) + + .dataa(\z80_|pla_decode_|Equal13~0_combout ), + .datab(\z80_|ir_|opcode [3]), + .datac(\z80_|pla_decode_|Equal8~0_combout ), + .datad(\z80_|execute_|ctl_ir_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 .lut_mask = 16'h2000; +defparam \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y16_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~3 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_we~3_combout = (\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_iorw~10_combout ) # (\z80_|execute_|ctl_mWrite~7_combout )))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ), + .datac(\z80_|execute_|ctl_iorw~10_combout ), + .datad(\z80_|execute_|ctl_mWrite~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_we~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_we~3 .lut_mask = 16'hEEEC; +defparam \z80_|execute_|ctl_bus_db_we~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~2 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_we~2_combout = (\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|pla_decode_|Equal13~2_combout ) # ((\z80_|execute_|ctl_mRead~8_combout ) # (\z80_|execute_|ctl_mWrite~7_combout )))) + + .dataa(\z80_|pla_decode_|Equal13~2_combout ), + .datab(\z80_|execute_|ctl_ir_we~4_combout ), + .datac(\z80_|execute_|ctl_mRead~8_combout ), + .datad(\z80_|execute_|ctl_mWrite~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_we~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_we~2 .lut_mask = 16'hCCC8; +defparam \z80_|execute_|ctl_bus_db_we~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y15_N30 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~7 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_we~7_combout = (\z80_|execute_|ctl_bus_db_we~8_combout ) # ((\z80_|execute_|ctl_bus_db_we~6_combout ) # ((\z80_|execute_|ctl_bus_db_we~3_combout ) # (\z80_|execute_|ctl_bus_db_we~2_combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_we~8_combout ), + .datab(\z80_|execute_|ctl_bus_db_we~6_combout ), + .datac(\z80_|execute_|ctl_bus_db_we~3_combout ), + .datad(\z80_|execute_|ctl_bus_db_we~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_we~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_we~7 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_bus_db_we~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~66 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][0]~66_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|zx_keyboard_|shifted~q )) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|shifted~q ), .datad(gnd), .cin(gnd), - .combout(\z80_|execute_|ctl_apin_mux~2_combout ), + .combout(\ula_|zx_keyboard_|keys[5][0]~66_combout ), .cout()); // synopsys translate_off -defparam \z80_|execute_|ctl_apin_mux~2 .lut_mask = 16'h8F8F; -defparam \z80_|execute_|ctl_apin_mux~2 .sum_lutc_input = "datac"; +defparam \ula_|zx_keyboard_|keys[5][0]~66 .lut_mask = 16'hCECE; +defparam \ula_|zx_keyboard_|keys[5][0]~66 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y16_N18 +// Location: LCCOMB_X29_Y8_N30 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~80 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][0]~80_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [0]))) # (!\ula_|ps2_keyboard_|shiftreg [4] & +// (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [0]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][0]~80_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][0]~80 .lut_mask = 16'h1008; +defparam \ula_|zx_keyboard_|keys[5][0]~80 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N0 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~81 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][0]~81_combout = (\ula_|zx_keyboard_|keys[5][0]~80_combout & (\ula_|ps2_keyboard_|shiftreg [2] $ (\ula_|ps2_keyboard_|shiftreg [4]))) + + .dataa(\ula_|zx_keyboard_|keys[5][0]~80_combout ), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][0]~81_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][0]~81 .lut_mask = 16'h0AA0; +defparam \ula_|zx_keyboard_|keys[5][0]~81 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~82 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][0]~82_combout = (\ula_|zx_keyboard_|keys[6][1]~39_combout & ((\ula_|zx_keyboard_|keys[5][0]~81_combout & (!\ula_|zx_keyboard_|keys[5][0]~66_combout )) # (!\ula_|zx_keyboard_|keys[5][0]~81_combout & +// ((\ula_|zx_keyboard_|keys[5][0]~q ))))) # (!\ula_|zx_keyboard_|keys[6][1]~39_combout & (((\ula_|zx_keyboard_|keys[5][0]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][0]~66_combout ), + .datab(\ula_|zx_keyboard_|keys[6][1]~39_combout ), + .datac(\ula_|zx_keyboard_|keys[5][0]~q ), + .datad(\ula_|zx_keyboard_|keys[5][0]~81_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][0]~82_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][0]~82 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[5][0]~82 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y8_N5 +dffeas \ula_|zx_keyboard_|keys[5][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[5][0]~82_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[5][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[5][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~84 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][0]~84_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|zx_keyboard_|shifted~q )) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|zx_keyboard_|shifted~q ), + .datac(gnd), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][0]~84_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][0]~84 .lut_mask = 16'hFF22; +defparam \ula_|zx_keyboard_|keys[4][0]~84 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N8 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~83 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][0]~83_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [5] $ (\ula_|ps2_keyboard_|shiftreg [3])))) # (!\ula_|ps2_keyboard_|shiftreg [1] & +// (!\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [0]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][0]~83_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][0]~83 .lut_mask = 16'h0148; +defparam \ula_|zx_keyboard_|keys[4][0]~83 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~85 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][0]~85_combout = (\ula_|zx_keyboard_|keys[4][0]~83_combout & ((\ula_|zx_keyboard_|keys[5][1]~35_combout & (!\ula_|zx_keyboard_|keys[4][0]~84_combout )) # (!\ula_|zx_keyboard_|keys[5][1]~35_combout & +// ((\ula_|zx_keyboard_|keys[4][0]~q ))))) # (!\ula_|zx_keyboard_|keys[4][0]~83_combout & (((\ula_|zx_keyboard_|keys[4][0]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[4][0]~84_combout ), + .datab(\ula_|zx_keyboard_|keys[4][0]~83_combout ), + .datac(\ula_|zx_keyboard_|keys[4][0]~q ), + .datad(\ula_|zx_keyboard_|keys[5][1]~35_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][0]~85_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][0]~85 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[4][0]~85 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y10_N21 +dffeas \ula_|zx_keyboard_|keys[4][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[4][0]~85_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[4][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[4][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N14 +cycloneive_lcell_comb \D[0]~42 ( +// Equation(s): +// \D[0]~42_combout = (\z80_|address_pins_|abus[12]~21_combout & (((\z80_|address_pins_|abus[13]~20_combout )) # (!\ula_|zx_keyboard_|keys[5][0]~q ))) # (!\z80_|address_pins_|abus[12]~21_combout & (!\ula_|zx_keyboard_|keys[4][0]~q & +// ((\z80_|address_pins_|abus[13]~20_combout ) # (!\ula_|zx_keyboard_|keys[5][0]~q )))) + + .dataa(\z80_|address_pins_|abus[12]~21_combout ), + .datab(\ula_|zx_keyboard_|keys[5][0]~q ), + .datac(\z80_|address_pins_|abus[13]~20_combout ), + .datad(\ula_|zx_keyboard_|keys[4][0]~q ), + .cin(gnd), + .combout(\D[0]~42_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~42 .lut_mask = 16'hA2F3; +defparam \D[0]~42 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][0]~78 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][0]~78_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|zx_keyboard_|keys[1][4]~23_combout & \ula_|ps2_keyboard_|shiftreg [3]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|ps2_keyboard_|shiftreg [5]), + .datac(\ula_|zx_keyboard_|keys[1][4]~23_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][0]~78_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][0]~78 .lut_mask = 16'h1000; +defparam \ula_|zx_keyboard_|keys[1][0]~78 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][0]~79 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][0]~79_combout = (\ula_|zx_keyboard_|keys[1][0]~78_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[1][0]~78_combout & ((\ula_|zx_keyboard_|keys[1][0]~q ))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[1][0]~q ), + .datad(\ula_|zx_keyboard_|keys[1][0]~78_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][0]~79_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][0]~79 .lut_mask = 16'h55F0; +defparam \ula_|zx_keyboard_|keys[1][0]~79 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y9_N27 +dffeas \ula_|zx_keyboard_|keys[1][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[1][0]~79_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[1][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[1][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][0]~76 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][0]~76_combout = (\ula_|zx_keyboard_|keys[3][1]~26_combout & ((\ula_|zx_keyboard_|keys[3][0]~75_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][0]~75_combout & ((\ula_|zx_keyboard_|keys[3][0]~q +// ))))) # (!\ula_|zx_keyboard_|keys[3][1]~26_combout & (((\ula_|zx_keyboard_|keys[3][0]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[3][1]~26_combout ), + .datac(\ula_|zx_keyboard_|keys[3][0]~q ), + .datad(\ula_|zx_keyboard_|keys[3][0]~75_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][0]~76_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][0]~76 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[3][0]~76 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y9_N13 +dffeas \ula_|zx_keyboard_|keys[3][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[3][0]~76_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[3][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[3][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][0]~77 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][0]~77_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (((\ula_|zx_keyboard_|keys[2][0]~q )))) # (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[2][1]~24_combout & (!\ula_|zx_keyboard_|released~q )) # +// (!\ula_|zx_keyboard_|keys[2][1]~24_combout & ((\ula_|zx_keyboard_|keys[2][0]~q ))))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|zx_keyboard_|keys[2][0]~q ), + .datad(\ula_|zx_keyboard_|keys[2][1]~24_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][0]~77_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][0]~77 .lut_mask = 16'hD1F0; +defparam \ula_|zx_keyboard_|keys[2][0]~77 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y9_N11 +dffeas \ula_|zx_keyboard_|keys[2][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[2][0]~77_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[2][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[2][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N28 +cycloneive_lcell_comb \D[0]~40 ( +// Equation(s): +// \D[0]~40_combout = (\ula_|zx_keyboard_|keys[3][0]~q & (\z80_|address_pins_|abus[11]~19_combout & ((\z80_|address_pins_|abus[10]~24_combout ) # (!\ula_|zx_keyboard_|keys[2][0]~q )))) # (!\ula_|zx_keyboard_|keys[3][0]~q & +// ((\z80_|address_pins_|abus[10]~24_combout ) # ((!\ula_|zx_keyboard_|keys[2][0]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[3][0]~q ), + .datab(\z80_|address_pins_|abus[10]~24_combout ), + .datac(\z80_|address_pins_|abus[11]~19_combout ), + .datad(\ula_|zx_keyboard_|keys[2][0]~q ), + .cin(gnd), + .combout(\D[0]~40_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~40 .lut_mask = 16'hC4F5; +defparam \D[0]~40 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y9_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr0~0 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr0~0_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [0])) # (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg +// [2])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr0~0 .lut_mask = 16'h1012; +defparam \ula_|zx_keyboard_|WideOr0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys~71 ( +// Equation(s): +// \ula_|zx_keyboard_|keys~71_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (((!\ula_|zx_keyboard_|WideOr0~0_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [4] & (((!\ula_|ps2_keyboard_|shiftreg [3])) # (!\ula_|zx_keyboard_|keys[6][4]~45_combout ))) + + .dataa(\ula_|zx_keyboard_|keys[6][4]~45_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|zx_keyboard_|WideOr0~0_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys~71_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys~71 .lut_mask = 16'h13DF; +defparam \ula_|zx_keyboard_|keys~71 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y10_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~70 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][3]~70_combout = (\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [6]) + + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), + .datab(gnd), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][3]~70_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][3]~70 .lut_mask = 16'hAA00; +defparam \ula_|zx_keyboard_|keys[4][3]~70 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~72 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][0]~72_combout = (\ula_|zx_keyboard_|keys[0][0]~13_combout & (((!\ula_|zx_keyboard_|keys~71_combout & \ula_|zx_keyboard_|keys[4][3]~70_combout )) # (!\ula_|zx_keyboard_|extended~q ))) + + .dataa(\ula_|zx_keyboard_|extended~q ), + .datab(\ula_|zx_keyboard_|keys~71_combout ), + .datac(\ula_|zx_keyboard_|keys[0][0]~13_combout ), + .datad(\ula_|zx_keyboard_|keys[4][3]~70_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][0]~72_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][0]~72 .lut_mask = 16'h7050; +defparam \ula_|zx_keyboard_|keys[0][0]~72 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr4~0 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr4~0_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (((\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [1])))) # (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [4] & +// (!\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [5]), + .datab(\ula_|ps2_keyboard_|shiftreg [4]), + .datac(\ula_|ps2_keyboard_|shiftreg [6]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr4~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr4~0 .lut_mask = 16'hA004; +defparam \ula_|zx_keyboard_|WideOr4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys~73 ( +// Equation(s): +// \ula_|zx_keyboard_|keys~73_combout = (!\ula_|zx_keyboard_|extended~q & (((\ula_|ps2_keyboard_|shiftreg [3]) # (!\ula_|zx_keyboard_|WideOr4~0_combout )) # (!\ula_|zx_keyboard_|keys[4][1]~29_combout ))) + + .dataa(\ula_|zx_keyboard_|extended~q ), + .datab(\ula_|zx_keyboard_|keys[4][1]~29_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|zx_keyboard_|WideOr4~0_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys~73_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys~73 .lut_mask = 16'h5155; +defparam \ula_|zx_keyboard_|keys~73 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~74 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][0]~74_combout = (\ula_|zx_keyboard_|keys[0][0]~72_combout & ((\ula_|zx_keyboard_|keys~73_combout & (\ula_|zx_keyboard_|keys[0][0]~q )) # (!\ula_|zx_keyboard_|keys~73_combout & ((!\ula_|zx_keyboard_|released~q ))))) # +// (!\ula_|zx_keyboard_|keys[0][0]~72_combout & (((\ula_|zx_keyboard_|keys[0][0]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[0][0]~72_combout ), + .datab(\ula_|zx_keyboard_|keys~73_combout ), + .datac(\ula_|zx_keyboard_|keys[0][0]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][0]~74_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][0]~74 .lut_mask = 16'hD0F2; +defparam \ula_|zx_keyboard_|keys[0][0]~74 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y8_N11 +dffeas \ula_|zx_keyboard_|keys[0][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[0][0]~74_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[0][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[0][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~2 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row~2_combout = ((\z80_|address_pins_|DFFE_apin_latch [8]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) # (!\ula_|zx_keyboard_|keys[0][0]~q ) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|keys[0][0]~q ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\z80_|address_pins_|DFFE_apin_latch [8]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row~2 .lut_mask = 16'hFF3F; +defparam \ula_|zx_keyboard_|key_row~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y9_N16 +cycloneive_lcell_comb \D[0]~41 ( +// Equation(s): +// \D[0]~41_combout = (\D[0]~40_combout & (\ula_|zx_keyboard_|key_row~2_combout & ((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][0]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[1][0]~q ), + .datab(\D[0]~40_combout ), + .datac(\ula_|zx_keyboard_|key_row~2_combout ), + .datad(\z80_|address_pins_|abus[9]~17_combout ), + .cin(gnd), + .combout(\D[0]~41_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~41 .lut_mask = 16'hC040; +defparam \D[0]~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~89 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][0]~89_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [5]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|ps2_keyboard_|shiftreg [6]), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][0]~89_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][0]~89 .lut_mask = 16'h0008; +defparam \ula_|zx_keyboard_|keys[6][0]~89 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~90 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][0]~90_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|zx_keyboard_|keys[6][0]~89_combout & (\ula_|zx_keyboard_|shifted~3_combout & \ula_|zx_keyboard_|keys[7][1]~21_combout ))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [1]), + .datab(\ula_|zx_keyboard_|keys[6][0]~89_combout ), + .datac(\ula_|zx_keyboard_|shifted~3_combout ), + .datad(\ula_|zx_keyboard_|keys[7][1]~21_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][0]~90_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][0]~90 .lut_mask = 16'h8000; +defparam \ula_|zx_keyboard_|keys[6][0]~90 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~91 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][0]~91_combout = (\ula_|zx_keyboard_|keys[6][0]~90_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[6][0]~90_combout & (\ula_|zx_keyboard_|keys[6][0]~q )) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|keys[6][0]~90_combout ), + .datac(\ula_|zx_keyboard_|keys[6][0]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][0]~91_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][0]~91 .lut_mask = 16'h30FC; +defparam \ula_|zx_keyboard_|keys[6][0]~91 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y10_N19 +dffeas \ula_|zx_keyboard_|keys[6][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[6][0]~91_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[6][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[6][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y8_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~131 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][0]~131_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|keys[3][0]~75_combout & (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [6]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [2]), + .datab(\ula_|zx_keyboard_|keys[3][0]~75_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][0]~131_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][0]~131 .lut_mask = 16'h8000; +defparam \ula_|zx_keyboard_|keys[7][0]~131 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N22 +cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~3 ( +// Equation(s): +// \ula_|zx_keyboard_|WideOr16~3_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [6]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [6]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|WideOr16~3_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|WideOr16~3 .lut_mask = 16'h000F; +defparam \ula_|zx_keyboard_|WideOr16~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~86 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][0]~86_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|zx_keyboard_|keys[5][4]~62_combout & (\ula_|zx_keyboard_|WideOr16~3_combout & \ula_|ps2_keyboard_|shiftreg [3]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|zx_keyboard_|keys[5][4]~62_combout ), + .datac(\ula_|zx_keyboard_|WideOr16~3_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [3]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][0]~86_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][0]~86 .lut_mask = 16'h4000; +defparam \ula_|zx_keyboard_|keys[7][0]~86 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y9_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~87 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][0]~87_combout = (\ula_|zx_keyboard_|keys[7][1]~21_combout & (\ula_|ps2_keyboard_|shiftreg [5] & ((\ula_|zx_keyboard_|keys[7][0]~131_combout ) # (\ula_|zx_keyboard_|keys[7][0]~86_combout )))) + + .dataa(\ula_|zx_keyboard_|keys[7][1]~21_combout ), + .datab(\ula_|zx_keyboard_|keys[7][0]~131_combout ), + .datac(\ula_|zx_keyboard_|keys[7][0]~86_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [5]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][0]~87_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][0]~87 .lut_mask = 16'hA800; +defparam \ula_|zx_keyboard_|keys[7][0]~87 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~88 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][0]~88_combout = (\ula_|zx_keyboard_|keys[7][0]~87_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[7][0]~87_combout & (\ula_|zx_keyboard_|keys[7][0]~q )) + + .dataa(\ula_|zx_keyboard_|keys[7][0]~87_combout ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[7][0]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][0]~88_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][0]~88 .lut_mask = 16'h50FA; +defparam \ula_|zx_keyboard_|keys[7][0]~88 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y10_N5 +dffeas \ula_|zx_keyboard_|keys[7][0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[7][0]~88_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[7][0]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][0] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[7][0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N12 +cycloneive_lcell_comb \D[0]~43 ( +// Equation(s): +// \D[0]~43_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\z80_|address_pins_|abus[15]~22_combout ) # (!\ula_|zx_keyboard_|keys[7][0]~q )))) # (!\z80_|address_pins_|abus[14]~23_combout & (!\ula_|zx_keyboard_|keys[6][0]~q & +// ((\z80_|address_pins_|abus[15]~22_combout ) # (!\ula_|zx_keyboard_|keys[7][0]~q )))) + + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\ula_|zx_keyboard_|keys[6][0]~q ), + .datac(\ula_|zx_keyboard_|keys[7][0]~q ), + .datad(\z80_|address_pins_|abus[15]~22_combout ), + .cin(gnd), + .combout(\D[0]~43_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~43 .lut_mask = 16'hBB0B; +defparam \D[0]~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y10_N10 +cycloneive_lcell_comb \D[0]~44 ( +// Equation(s): +// \D[0]~44_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[0]~42_combout & (\D[0]~41_combout & \D[0]~43_combout ))) + + .dataa(\D[0]~42_combout ), + .datab(\D[0]~41_combout ), + .datac(\z80_|address_pins_|abus[0]~16_combout ), + .datad(\D[0]~43_combout ), + .cin(gnd), + .combout(\D[0]~44_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~44 .lut_mask = 16'hF8F0; +defparam \D[0]~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y17_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a24 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[0]~46_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_first_bit_number = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y18_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a16 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[0]~46_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_first_bit_number = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y15_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a8 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[0]~46_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y19_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a0 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[0]~46_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081; +// synopsys translate_on + +// Location: LCCOMB_X23_Y14_N12 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout )) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ))))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4 .lut_mask = 16'hE3E0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y14_N6 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~5 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~5_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4_combout & +// (\ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout )) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout ))))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4_combout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~5 .lut_mask = 16'hAFC0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y13_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a8 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h3C00000000000000000000000000000000000000000000000000000000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005DB824E17CAAE881C1908A79F24B7D1B4857A981A6AF39DFF5A2FEE9141EB33592D8E9B82471FDDA6791810A1C29D415CC1A8FA03444DF0083F83506BA93E8D1A1856A768D73A08418BFB25A40001DD4833DAF33BD311BB45F39667627407EF59ED569C483EB3BE1B10551B1428A6169579293ED063CAA9C6ADB0433CFC15C33AFF04C710408C20AC28B5909A229CD7D1DB4EB9A44CE0EEDBBBD391D3128AAA3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'hDDE6FC8EBE3F9F3C3DFC6E8F07BFD31D50660B1E0B2506A533CE0E340C7C745CAEC4837C2A5FECBB94C1C969FFDDFF79BFFAAFDCA8D748399ABF75558ADD02F56F6DFFF29CB70FFD25A59DFFFED7B3F7E8B4CE6FFF3EF9CEC6BAE57ABFFFCEE647B2AFF5B87AA26AFFDD317DEDCFBDFFE1A0CAD3B58877DD2F647F7DF748E7CF4693FD3C1238FFAFBD7FDF567FA8FEF024F33AFD3AABC6B105EA80272D64895FFF9FFF6E3881C81AFDCF2257FD4F8ED5257D0E9B800726B6564D2B05012F76DF636CDEB4BDFCAEEFC61DFFEFB7E26262DEF2CB9F71565824FEBF3F7BDDEABB593F1BF746FBFFC353E37263FF38A796EF39E3FD7DFEBA7FFEFFBD97ABAF09E909; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'hE629BDF93D7F5B5BAF92FBAB477E9B315DB5A310CFACC7408DF9A544B1E57AF6EFEF92C2FA4D8D4E4AC86C277338FA37BCDD9D47782DB75EFF80781BCD23D0AFCAE30B9FE6AA29FFF6F72DA73DFE4F7ACD39687B9E69C5359E9B991F0246EFFBC5595561AC64787878F5CE14C664CF9EB0CDAFFBABEF1E83358371B9ED96E5069555AFBBD3AEBFCABFBBED7A5C5FE9BD0E6A91C6E7610042695EEB08D8881B1D735AF87DAE59FABBD7DEAF8717F2B72F428F5E37E5D6E13157B99CBD2D73B9C73C563C8B02C8CC39C64DDCEA1BEEB5E7353F93786145598FE634EF1000179B345725EA43CE18F187A1DE4DAABEA97963E3A7A96B8B7CBC095BEB7CE46274D9AF; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h4ED4AE2B1650D21EAFE01E7099EFCA3094FD4D705CF6B84AE21583E13385F8650004406BD60A023AB063D4E5966EA41AA997F5A49BFCB0657A9732D28EB8217E65F627A15E1057ADEE7B9E27122A58FB2B98B1EA560390C7E87715861814E04DCB76FAB179E9619BC7E7E9C9FD801CF87DBA1EA496E829D4E62861E1AF436A7585287860729C77B6C68CAEA3033A6E84D67249B594C407B39C68B4C1C97FDEFC6BAD12FDBB525EF4F87F4A23EC13CBC0262D8899A3A290F04F41C1324045B9FCEEC890579E95D5A0A546CCCDD48577558ABE7CA36EF67A70F6A8758BDA052D5B95DE707778B17C2379847A23AE5D4BB01F36F3F44A8162566D9FB15DE7CC83F7; +// synopsys translate_on + +// Location: M9K_X22_Y28_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a0 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[0]~46_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_bit_number = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF0000000000000000000000003FF03FFC20107FFC3FF00B9C3FF007FC18000FFC3FF03FD42FF43FFC2FFC3FE01FFE7FE81FFE3FDC07FE3FFC07FE2FFC07FE0F0807FE1F18207F0F3030FD8C30383300600000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h000000000000000000000000FFFFFFFFE0408103E004044390120EAA803920C6000000000000000000000000FFFFFFFFE0408103A004005A84723CEA813930C2000000000000000000000000800000009FBF7EFD8004027A8572358A813950EA000000000000000000000000800000009FBF7EFC8005157A85733F0A8139518E0000000000000000000000009FBF7EFC800000008006113A8C73330A813919EA0000000000000000000000009FBF7EFC8000000080060022801333A2813973EA00000000000000000000000080000000DFFFFFFD9FF6022A84730366801913FE000000000000000000000000E0408102FFFFFFFD9FF60ABA84730426901913EE; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h9FF81326887812F28FF0D7C2CC6856E3894C8B62980099E28988BFC2B9EC79829FE81362887842E68FF0C7C2CCE056E2896C89E2888098E28AA8BBC299FC1AC280081372887842E69EE0C7CA8CE046E289E089E289C899E28AA8BEC2993C1AE28008837E882852C69EE0874288E046E2886099E289689FCE8AD8BFC2999C09F680088376880846C69CA88382880042A289D08DE289F098C28AF8BFC289FC88F280088376880857C29CA893C2888043A289508DE288F0D9428BF0AFC289F4888A800883F2880857829C2891C3889047F2898885E2899081428990AF8289FC8BE3800893F6880847C2DC0894E389944F62888899668918914289803582CB8C8AF3; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'hCBAC80F38DA845828DF44582840124029375A4A288D108A2FFFFFFFDE0408082CAEC80968DF855828CE4408284012006917194C280510B82DFFFFFFC8000000288EC84A28FFC4586880C648A860124128179900280510F82800000009FBF7F7C8BA080BA8FEC40828808618286012C028179901280510702800000009FBF7F7C8BB081BA8CAC408289E0618286812C1281791002805007029FBF7F7C8000000089B881828CB440828BE07782868322028139909280400F029FBF7F7D8000000089A4C3928FF444828A00260A8792227281199022A0001F03E0408081FFFFFFFF89A0C1928FD440828800260687B720C280199002E0001F03E0408083FFFFFFFF; +// synopsys translate_on + +// Location: M9K_X22_Y21_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a8 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(gnd), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[0]~46_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_first_bit_number = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X23_Y14_N4 +cycloneive_lcell_comb \Selector2~0 ( +// Equation(s): +// \Selector2~0_combout = (\Selector3~0_combout & (((\ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ) # (!\z80_|address_pins_|abus[14]~23_combout )))) # (!\Selector3~0_combout & +// (\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout & (\z80_|address_pins_|abus[14]~23_combout ))) + + .dataa(\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ), + .datab(\Selector3~0_combout ), + .datac(\z80_|address_pins_|abus[14]~23_combout ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ), + .cin(gnd), + .combout(\Selector2~0_combout ), + .cout()); +// synopsys translate_off +defparam \Selector2~0 .lut_mask = 16'hEC2C; +defparam \Selector2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y31_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a0 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h1EEA3633EFEA856D05BA968C1B3C30CA1788DD95D16B8F914DDDFC3EE5C69945DF7D7BF31C6072BFA7993996AB7DD2F3EE4009844CC9D6CF9E583AEC48A52F2904B57D8E0D755851232838F9B5348838530D7AF95411555D263B8CA86A5D29D7CE4B65409D6F04C5709A56C241C3BCEF07459A416EB4E8F3D73CC714F4333AFE605D53A5C955D5D1412F8361617A54446971FD187442A60FB04457857BECC3120A01FDC7FE2CBF038A61DEE5FCE2D10C8F35FBF80C05ABFF4B6935287B125E8D56F9FDFE7D64C1F4E1F5641845CD17E836B97780400C702523FA8E7C7BBD6F0666591A35ADD26B6B7E33CA56E9AB329EFA7E68F98AE7CE9507755C74C430286A; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h88537A811D4EF6CD9668CCD3E2E7A8041788DCA5F7E08AF52AF5276078304DEB75B74BB9AC3C1A492952F7EEAA0E7CF9FBEDD0FB47EEFDCC3734B816F355C913CD2E1AF14C30545297A91BED3AEAEFF8F696B5F4FC80BC6B1A2559492E9198E4A5875745B625C6CA7A7292332492D139728A689DA1AE78B6B44CE4F4A4EA5A22F331598B364EF27516CC49A4662C5E5C92ED140D96373678F833AE434698237599716B8CBAE2D3D061F2C3D6337AB435B5C2144AB6FA2F8BB51357801066B6589467DA6C480E6D19CEEA8451CEFA88FD70E7925B0302F877F87FA833FBD147E937309C08305A10187707E3D57DDE4931F1D9E97A8F378981ABBF8D7B6B7539C3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h763DD7AA7EED3F4AD4EA7491ADE6F14E6DBADD0F090A8DF34D7BAD35DD2275F0BCCF19EEF299751C919C9C13C6FB9ED711AC4DA7D947CC79E9B6323EF6CE62638CEBCB187AE5D44ECA689C9BD4E5AE544DEA7E90D186B9F335F3323877AAD54196CE81973CB555904419599375501366EC343561BCF83357F8823671393B278C1C387A7970C7F3E688673CF5975EE3E5FF105CFCCFAB725D698FB088B063063C7833830C7B2C7AFB8A8D203C312306DA0E72641FFB93D59B5EC84F44AD55F4B884735325ACC969B2EAE10A1478D866F667DDEF7BBF75E6958B6D02DC6D0F807660A229B98541E6FE734DE2280A9B57FCD5A9BEFEF7CDA5ABEB44FD73D2794D56; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'hD0734B461A36980411EB2A6C1BE76029258777EF227A8F6E84F74C4436098F67BA611013110188547995B108BB2DAE76F423A0D98845F9248BDFA45E10CA403A5E2B1A3E16869E1D37BCE906B82F401CBD467617DB34D9E0C80B5E6E10063EC4BD52921D249E377D95CFAAA309EEDAA57DA85F55DBB7048A69A4C801013948B617F7F5724D40707E6FF30002982023020449B4680C45D1CE6D8EB30A061DB8FEDD6E630C15271E48CA801988654FB501D5393392EE765C1EC95C1E4D86F18A965372B72B484E2F2664B735B69A5AB532B086BA4C62AD6D56EECBDB6984B251454845BD5B243DAED2B2489B313A35C50252AFD3E0B76FEF342335C7F1321D92FF; +// synopsys translate_on + +// Location: LCCOMB_X23_Y14_N28 +cycloneive_lcell_comb \Selector2~1 ( +// Equation(s): +// \Selector2~1_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\Selector2~0_combout )))) # (!\z80_|address_pins_|abus[14]~23_combout & ((\Selector2~0_combout & (\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout )) # +// (!\Selector2~0_combout & ((\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ))))) + + .dataa(\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ), + .datab(\z80_|address_pins_|abus[14]~23_combout ), + .datac(\Selector2~0_combout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ), + .cin(gnd), + .combout(\Selector2~1_combout ), + .cout()); +// synopsys translate_off +defparam \Selector2~1 .lut_mask = 16'hE3E0; +defparam \Selector2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y14_N30 +cycloneive_lcell_comb \D[0]~83 ( +// Equation(s): +// \D[0]~83_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [15] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~5_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\Selector2~1_combout +// ))))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~5_combout )) + + .dataa(\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~5_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [15]), + .datad(\Selector2~1_combout ), + .cin(gnd), + .combout(\D[0]~83_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~83 .lut_mask = 16'hAEA2; +defparam \D[0]~83 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y14_N14 +cycloneive_lcell_comb \D[0]~45 ( +// Equation(s): +// \D[0]~45_combout = ((\Equal2~0_combout & (\D[0]~44_combout )) # (!\Equal2~0_combout & ((\D[0]~83_combout )))) # (!\Equal2~1_combout ) + + .dataa(\Equal2~0_combout ), + .datab(\D[0]~44_combout ), + .datac(\D[0]~83_combout ), + .datad(\Equal2~1_combout ), + .cin(gnd), + .combout(\D[0]~45_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~45 .lut_mask = 16'hD8FF; +defparam \D[0]~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y14_N0 +cycloneive_lcell_comb \D[0]~46 ( +// Equation(s): +// \D[0]~46_combout = (\z80_|pin_control_|bus_db_pin_oe~15_combout & (((\D[0]~45_combout & \z80_|data_pins_|dout [0])))) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout & (((\D[0]~45_combout )) # (!\Equal2~1_combout ))) + + .dataa(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .datab(\Equal2~1_combout ), + .datac(\D[0]~45_combout ), + .datad(\z80_|data_pins_|dout [0]), + .cin(gnd), + .combout(\D[0]~46_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~46 .lut_mask = 16'hF151; +defparam \D[0]~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N26 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [0] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[0]~17_combout ) # ((\D[0]~46_combout & \z80_|pin_control_|bus_db_pin_re~combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & +// (\D[0]~46_combout & ((\z80_|pin_control_|bus_db_pin_re~combout )))) + + .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datab(\D[0]~46_combout ), + .datac(\z80_|bus_control_|db[0]~17_combout ), + .datad(\z80_|pin_control_|bus_db_pin_re~combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [0]), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] .lut_mask = 16'hECA0; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y13_N27 +dffeas \z80_|data_pins_|dout[0] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [0]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|data_pins_|dout [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|data_pins_|dout[0] .is_wysiwyg = "true"; +defparam \z80_|data_pins_|dout[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N10 +cycloneive_lcell_comb \z80_|bus_control_|db[0]~16 ( +// Equation(s): +// \z80_|bus_control_|db[0]~16_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [0]) # (!\z80_|execute_|ctl_bus_db_oe~combout ))) + + .dataa(\z80_|data_pins_|dout [0]), + .datab(\z80_|bus_control_|db[0]~4_combout ), + .datac(\z80_|execute_|ctl_bus_db_oe~combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|bus_control_|db[0]~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[0]~16 .lut_mask = 16'h8C8C; +defparam \z80_|bus_control_|db[0]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N0 +cycloneive_lcell_comb \z80_|bus_control_|db[0]~17 ( +// Equation(s): +// \z80_|bus_control_|db[0]~17_combout = ((\z80_|bus_control_|db[0]~16_combout & ((\z80_|alu_control_|db[0]~12_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) + + .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datab(\z80_|alu_control_|db[0]~12_combout ), + .datac(\z80_|bus_control_|db[0]~6_combout ), + .datad(\z80_|bus_control_|db[0]~16_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[0]~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[0]~17 .lut_mask = 16'hDF0F; +defparam \z80_|bus_control_|db[0]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y13_N1 +dffeas \z80_|ir_|opcode[0] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|bus_control_|db[0]~17_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|ir_|opcode [0]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|ir_|opcode[0] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N6 +cycloneive_lcell_comb \z80_|pla_decode_|Equal3~2 ( +// Equation(s): +// \z80_|pla_decode_|Equal3~2_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal52~0_combout & \z80_|pla_decode_|Equal3~0_combout ))) + + .dataa(\z80_|ir_|opcode [0]), + .datab(\z80_|pla_decode_|Equal3~1_combout ), + .datac(\z80_|pla_decode_|Equal52~0_combout ), + .datad(\z80_|pla_decode_|Equal3~0_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal3~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal3~2 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal3~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N16 +cycloneive_lcell_comb \z80_|pla_decode_|Equal43~0 ( +// Equation(s): +// \z80_|pla_decode_|Equal43~0_combout = (\z80_|pla_decode_|Equal1~7_combout & (\z80_|pla_decode_|Equal32~0_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal3~1_combout ))) + + .dataa(\z80_|pla_decode_|Equal1~7_combout ), + .datab(\z80_|pla_decode_|Equal32~0_combout ), + .datac(\z80_|ir_|opcode [5]), + .datad(\z80_|pla_decode_|Equal3~1_combout ), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal43~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal43~0 .lut_mask = 16'h8000; +defparam \z80_|pla_decode_|Equal43~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y17_N24 +cycloneive_lcell_comb \z80_|interrupts_|test1~2 ( +// Equation(s): +// \z80_|interrupts_|test1~2_combout = (!\z80_|pla_decode_|Equal3~2_combout & (!\z80_|pla_decode_|Equal43~0_combout & (!\z80_|pla_decode_|Equal79~0_combout & !\z80_|pla_decode_|Equal36~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal3~2_combout ), + .datab(\z80_|pla_decode_|Equal43~0_combout ), + .datac(\z80_|pla_decode_|Equal79~0_combout ), + .datad(\z80_|pla_decode_|Equal36~0_combout ), + .cin(gnd), + .combout(\z80_|interrupts_|test1~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|test1~2 .lut_mask = 16'h0001; +defparam \z80_|interrupts_|test1~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N22 +cycloneive_lcell_comb \z80_|interrupts_|test1~3 ( +// Equation(s): +// \z80_|interrupts_|test1~3_combout = (!\z80_|execute_|setM1~54_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (\z80_|interrupts_|test1~2_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q ))) + + .dataa(\z80_|sequencer_|DFFE_T4_ff~q ), + .datab(\z80_|execute_|setM1~54_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|interrupts_|test1~2_combout ), + .cin(gnd), + .combout(\z80_|interrupts_|test1~3_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|interrupts_|test1~3 .lut_mask = 16'h3331; +defparam \z80_|interrupts_|test1~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y13_N1 +dffeas \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|interrupts_|test1~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED .is_wysiwyg = "true"; +defparam \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N6 +cycloneive_lcell_comb \z80_|clk_delay_|SYNTHESIZED_WIRE_4 ( +// Equation(s): +// \z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (!\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|interrupts_|DFFE_inst44~q ))) + + .dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|interrupts_|DFFE_inst44~q ), + .cin(gnd), + .combout(\z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_4 .lut_mask = 16'h0100; +defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y14_N7 +dffeas \z80_|clk_delay_|SYNTHESIZED_WIRE_7 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_7 .is_wysiwyg = "true"; +defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_7 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y12_N12 +cycloneive_lcell_comb \z80_|clk_delay_|hold_clk_iorq ( +// Equation(s): +// \z80_|clk_delay_|hold_clk_iorq~combout = (!\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q & !\z80_|clk_delay_|DFF_inst5~q ) + + .dataa(\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ), + .datab(\z80_|clk_delay_|DFF_inst5~q ), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\z80_|clk_delay_|hold_clk_iorq~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|clk_delay_|hold_clk_iorq .lut_mask = 16'h1111; +defparam \z80_|clk_delay_|hold_clk_iorq .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y13_N31 +dffeas \z80_|sequencer_|DFFE_T4_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_T4_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_T4_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_T4_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_eval_cond~0 ( +// Equation(s): +// \z80_|execute_|ctl_eval_cond~0_combout = (\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_eval_cond~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_eval_cond~0 .lut_mask = 16'h00F0; +defparam \z80_|execute_|ctl_eval_cond~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y17_N22 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~27 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~27_combout = (\z80_|execute_|ctl_mRead~23_combout & (((!\z80_|pla_decode_|Equal38~2_combout & !\z80_|pla_decode_|Equal52~1_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout ))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|pla_decode_|Equal38~2_combout ), + .datac(\z80_|execute_|ctl_mRead~23_combout ), + .datad(\z80_|pla_decode_|Equal52~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~27 .lut_mask = 16'h5070; +defparam \z80_|execute_|ctl_mRead~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y17_N20 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~26 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~26_combout = (\z80_|execute_|ctl_mRead~34_combout ) # ((\z80_|pla_decode_|Equal21~1_combout ) # (\z80_|pla_decode_|Equal37~0_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|pla_decode_|Equal21~1_combout ), + .datad(\z80_|pla_decode_|Equal37~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~26 .lut_mask = 16'hFFFC; +defparam \z80_|execute_|ctl_mRead~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y17_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_mRead~28 ( +// Equation(s): +// \z80_|execute_|ctl_mRead~28_combout = (\z80_|execute_|ctl_mRead~27_combout & (\z80_|execute_|ctl_mRead~22_combout & ((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|execute_|ctl_mRead~26_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~27_combout ), + .datab(\z80_|execute_|ctl_mRead~26_combout ), + .datac(\z80_|execute_|ctl_mRead~22_combout ), + .datad(\z80_|execute_|ctl_mRead~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_mRead~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_mRead~28 .lut_mask = 16'h20A0; +defparam \z80_|execute_|ctl_mRead~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N12 +cycloneive_lcell_comb \z80_|execute_|nextM~6 ( +// Equation(s): +// \z80_|execute_|nextM~6_combout = (((\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal49~0_combout )) # (!\z80_|execute_|nextM~3_combout )) # (!\z80_|execute_|ixy_d~17_combout ) + + .dataa(\z80_|decode_state_|use_ixiy~combout ), + .datab(\z80_|execute_|ixy_d~17_combout ), + .datac(\z80_|execute_|nextM~3_combout ), + .datad(\z80_|pla_decode_|Equal49~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~6 .lut_mask = 16'hBF3F; +defparam \z80_|execute_|nextM~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y15_N10 +cycloneive_lcell_comb \z80_|execute_|nextM~7 ( +// Equation(s): +// \z80_|execute_|nextM~7_combout = ((\z80_|execute_|nextM~6_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # (\z80_|execute_|ixy_d~8_combout )))) # (!\z80_|execute_|nextM~4_combout ) + + .dataa(\z80_|execute_|nextM~6_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|execute_|ixy_d~8_combout ), + .datad(\z80_|execute_|nextM~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~7_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~7 .lut_mask = 16'hA8FF; +defparam \z80_|execute_|nextM~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|nextM~8 ( +// Equation(s): +// \z80_|execute_|nextM~8_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & (((\z80_|execute_|ixy_d~8_combout & !\z80_|execute_|ctl_flags_bus~1_combout )) # (!\z80_|alu_control_|flags_cond_true~q ))) # +// (!\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & (\z80_|execute_|ixy_d~8_combout & ((!\z80_|execute_|ctl_flags_bus~1_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), + .datab(\z80_|execute_|ixy_d~8_combout ), + .datac(\z80_|alu_control_|flags_cond_true~q ), + .datad(\z80_|execute_|ctl_flags_bus~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~8 .lut_mask = 16'h0ACE; +defparam \z80_|execute_|nextM~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N26 +cycloneive_lcell_comb \z80_|execute_|nextM~9 ( +// Equation(s): +// \z80_|execute_|nextM~9_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_mWrite~4_combout & ((\z80_|execute_|ctl_mRead~9_combout ) # (\z80_|execute_|ixy_d~6_combout )))) + + .dataa(\z80_|execute_|ctl_mRead~9_combout ), + .datab(\z80_|pla_decode_|Equal55~0_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ctl_mWrite~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~9 .lut_mask = 16'hC800; +defparam \z80_|execute_|nextM~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y15_N6 +cycloneive_lcell_comb \z80_|execute_|nextM~10 ( +// Equation(s): +// \z80_|execute_|nextM~10_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ) # ((\z80_|execute_|nextM~9_combout ) # ((\z80_|execute_|ctl_mRead~34_combout & \z80_|execute_|ixy_d~9_combout ))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|execute_|nextM~9_combout ), + .datad(\z80_|execute_|ixy_d~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~10 .lut_mask = 16'hFEFA; +defparam \z80_|execute_|nextM~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N20 +cycloneive_lcell_comb \z80_|execute_|nextM~12 ( +// Equation(s): +// \z80_|execute_|nextM~12_combout = (\z80_|execute_|nextM~8_combout ) # ((\z80_|execute_|ctl_alu_op_low~46_combout ) # ((\z80_|execute_|nextM~10_combout ) # (!\z80_|execute_|nextM~11_combout ))) + + .dataa(\z80_|execute_|nextM~8_combout ), + .datab(\z80_|execute_|ctl_alu_op_low~46_combout ), + .datac(\z80_|execute_|nextM~10_combout ), + .datad(\z80_|execute_|nextM~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~12 .lut_mask = 16'hFEFF; +defparam \z80_|execute_|nextM~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N24 +cycloneive_lcell_comb \z80_|execute_|nextM~15 ( +// Equation(s): +// \z80_|execute_|nextM~15_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & ((\z80_|execute_|ctl_mRead~5_combout ) # (!\z80_|execute_|fMRead~12_combout )))) + + .dataa(\z80_|execute_|fMRead~12_combout ), + .datab(\z80_|sequencer_|DFFE_T3_ff~q ), + .datac(\z80_|sequencer_|DFFE_M2_ff~q ), + .datad(\z80_|execute_|ctl_mRead~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~15 .lut_mask = 16'hC040; +defparam \z80_|execute_|nextM~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N26 +cycloneive_lcell_comb \z80_|execute_|nextM~13 ( +// Equation(s): +// \z80_|execute_|nextM~13_combout = (\z80_|execute_|nextM~7_combout ) # ((\z80_|execute_|nextM~12_combout ) # (\z80_|execute_|nextM~15_combout )) + + .dataa(\z80_|execute_|nextM~7_combout ), + .datab(\z80_|execute_|nextM~12_combout ), + .datac(gnd), + .datad(\z80_|execute_|nextM~15_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~13 .lut_mask = 16'hFFEE; +defparam \z80_|execute_|nextM~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N6 +cycloneive_lcell_comb \z80_|execute_|setM1~41 ( +// Equation(s): +// \z80_|execute_|setM1~41_combout = (\z80_|execute_|setM1~40_combout & !\z80_|execute_|ctl_mWrite~7_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|setM1~40_combout ), + .datac(\z80_|execute_|ctl_mWrite~7_combout ), + .datad(gnd), + .cin(gnd), + .combout(\z80_|execute_|setM1~41_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~41 .lut_mask = 16'h0C0C; +defparam \z80_|execute_|setM1~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N8 +cycloneive_lcell_comb \z80_|execute_|nextM~5 ( +// Equation(s): +// \z80_|execute_|nextM~5_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (((!\z80_|execute_|setM1~41_combout ) # (!\z80_|execute_|setM1~47_combout )) # (!\z80_|execute_|nextM~2_combout ))) + + .dataa(\z80_|execute_|ctl_eval_cond~0_combout ), + .datab(\z80_|execute_|nextM~2_combout ), + .datac(\z80_|execute_|setM1~47_combout ), + .datad(\z80_|execute_|setM1~41_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~5 .lut_mask = 16'h2AAA; +defparam \z80_|execute_|nextM~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y11_N0 +cycloneive_lcell_comb \z80_|execute_|nextM~14 ( +// Equation(s): +// \z80_|execute_|nextM~14_combout = (((\z80_|execute_|nextM~13_combout ) # (\z80_|execute_|nextM~5_combout )) # (!\z80_|execute_|ctl_mWrite~14_combout )) # (!\z80_|execute_|ctl_mRead~28_combout ) + + .dataa(\z80_|execute_|ctl_mRead~28_combout ), + .datab(\z80_|execute_|ctl_mWrite~14_combout ), + .datac(\z80_|execute_|nextM~13_combout ), + .datad(\z80_|execute_|nextM~5_combout ), + .cin(gnd), + .combout(\z80_|execute_|nextM~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|nextM~14 .lut_mask = 16'hFFF7; +defparam \z80_|execute_|nextM~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N24 +cycloneive_lcell_comb \z80_|sequencer_|ena_M ( +// Equation(s): +// \z80_|sequencer_|ena_M~combout = (\z80_|execute_|setM1~54_combout & !\z80_|execute_|nextM~14_combout ) + + .dataa(gnd), + .datab(\z80_|execute_|setM1~54_combout ), + .datac(gnd), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|ena_M~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|ena_M .lut_mask = 16'h00CC; +defparam \z80_|sequencer_|ena_M .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y13_N25 +dffeas \z80_|sequencer_|DFFE_T1_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|ena_M~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_T1_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_T1_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_T1_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N20 +cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_13 ( +// Equation(s): +// \z80_|sequencer_|SYNTHESIZED_WIRE_13~combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|execute_|setM1~54_combout & !\z80_|execute_|nextM~14_combout )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T1_ff~q ), + .datac(\z80_|execute_|setM1~54_combout ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_13 .lut_mask = 16'h0030; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y13_N21 +dffeas \z80_|sequencer_|DFFE_T2_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_T2_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_T2_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_T2_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N16 +cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_14 ( +// Equation(s): +// \z80_|sequencer_|SYNTHESIZED_WIRE_14~combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|execute_|setM1~54_combout & !\z80_|execute_|nextM~14_combout )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|execute_|setM1~54_combout ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_14 .lut_mask = 16'h00C0; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y13_N17 +dffeas \z80_|sequencer_|DFFE_T3_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_T3_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_T3_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_T3_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y14_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 ( +// Equation(s): +// \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout = (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 .lut_mask = 16'h0F00; +defparam \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y16_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_66_oe~2 ( +// Equation(s): +// \z80_|execute_|ctl_66_oe~2_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|execute_|comb~0_combout & \z80_|ir_|opcode [0]))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ), + .datab(\z80_|pla_decode_|Equal52~0_combout ), + .datac(\z80_|execute_|comb~0_combout ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_66_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_66_oe~2 .lut_mask = 16'h8000; +defparam \z80_|execute_|ctl_66_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y17_N11 +dffeas \z80_|interrupts_|im1 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_im_we~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|interrupts_|im1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|interrupts_|im1 .is_wysiwyg = "true"; +defparam \z80_|interrupts_|im1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_ff_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_bus_ff_oe~0_combout = (\z80_|interrupts_|DFFE_inst44~q & ((\z80_|interrupts_|im1~q ) # ((\z80_|interrupts_|im2~q & !\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) + + .dataa(\z80_|interrupts_|DFFE_inst44~q ), + .datab(\z80_|interrupts_|im2~q ), + .datac(\z80_|interrupts_|im1~q ), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_ff_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_ff_oe~0 .lut_mask = 16'hA0A8; +defparam \z80_|execute_|ctl_bus_ff_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_ff_oe~1 ( +// Equation(s): +// \z80_|execute_|ctl_bus_ff_oe~1_combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) # (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|execute_|ctl_bus_ff_oe~0_combout & +// ((\z80_|execute_|ctl_66_oe~2_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) + + .dataa(\z80_|execute_|ctl_66_oe~2_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datac(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ), + .datad(\z80_|execute_|ctl_bus_ff_oe~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_ff_oe~1_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_ff_oe~1 .lut_mask = 16'h3B30; +defparam \z80_|execute_|ctl_bus_ff_oe~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_zero_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_bus_zero_oe~0_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_iorw~10_combout ) # (\z80_|execute_|ctl_alu_op_low~27_combout )))) + + .dataa(\z80_|pla_decode_|Equal33~1_combout ), + .datab(\z80_|execute_|ctl_eval_cond~0_combout ), + .datac(\z80_|execute_|ctl_iorw~10_combout ), + .datad(\z80_|execute_|ctl_alu_op_low~27_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_zero_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_zero_oe~0 .lut_mask = 16'h8880; +defparam \z80_|execute_|ctl_bus_zero_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N18 +cycloneive_lcell_comb \z80_|bus_control_|db[0]~4 ( +// Equation(s): +// \z80_|bus_control_|db[0]~4_combout = (\z80_|execute_|ctl_bus_ff_oe~1_combout ) # ((!\z80_|execute_|ctl_bus_zero_oe~0_combout & ((\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) # (!\z80_|decode_state_|in_halt~q )))) + + .dataa(\z80_|execute_|ctl_bus_ff_oe~1_combout ), + .datab(\z80_|execute_|ctl_bus_zero_oe~0_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|decode_state_|in_halt~q ), + .cin(gnd), + .combout(\z80_|bus_control_|db[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[0]~4 .lut_mask = 16'hBABB; +defparam \z80_|bus_control_|db[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N24 +cycloneive_lcell_comb \z80_|bus_control_|db[6]~8 ( +// Equation(s): +// \z80_|bus_control_|db[6]~8_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[6]~22_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) + + .dataa(\z80_|bus_control_|db[0]~4_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datad(\z80_|alu_control_|db[6]~22_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[6]~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[6]~8 .lut_mask = 16'hAA0A; +defparam \z80_|bus_control_|db[6]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y7_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a22 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~79_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_first_bit_number = 6; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y8_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a30 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~79_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_first_bit_number = 6; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y11_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a14 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~79_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y10_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a6 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~79_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N16 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ) # +// ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout & +// !\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12 .lut_mask = 16'hF0AC; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y10_N22 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13_combout = (\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout & (((\ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout & +// ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout ), + .datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13 .lut_mask = 16'hCAF0; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y1_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a6 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h3C766E63DB6481CB39BC8C68831C724633186CC1BAE9D608A5DEF0FF219C28C1EFF4FDE394D0E19B6FD89186C23CF071E6F1CC8F7FC4F1E48756B0DCD8ED6D0C3DA139003D7A86B2F878DD99DAFB70DE1A19F3FB7DB3B8EF2633007664CB19992E43664448EFF06072648DBA32EDB76E26439BCCEF2DFBF664594B04FBAE72A84A3E508B49DC6BEAAB4F3F0CCCF6D8F568F2DA00EB384A7F53249323198000100408002024010408824080002008011482ED5615E40012EE630C3B2CDB2C13A736DB5B7BD2850018CF936621C6863095A73F7BE7442CB13110B9C0BBB96EEF16CE618EEDCFB393738178C476C367909F71307F6803F677575763DB2D8C3118E4; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h881331ED7AC4EFD38DFACDBB236790005719AEA2FAECCF0D126A30A27222D61BBA428334561F4EDB60C6BF8DB6E267BC56CB69BBCE636CCCB3B2B4B103CC46D5CEEC06DAECB0001569589D5F267AFE086C8FED5DE41DFEFF027DFDFF7FFBFBFDFFDFFF6FFFBDFFDFFF57FF7F7FB7FBBDFBDFFDBFF78FFDBFFEDDFFFDFFFEFF6FF7F7FDDFFEDFF6FF7FFEEFFEFEFC4E51EC0888848E1F2044B47B66608D8A3B3919B9466E6D60D27565964244B218B48AD83430D996068EC908D9E112096996041D77401A0C0CCF5DEEE561F7F7E68CBE72E48E570B047C772CBACC33753080E32EB0B348C0B62337739B1BC73192392592C84E37B7AC141CFE65EE76D83C9083; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h1C5CF062CA6F13854A59BDEEEA07E3C6559EBB3618111895CBBACCBCD512B5F07D361CCE72B925658DBE1F7C4707E195C5C665B8118C3C31B196C261DA85A5E11889D25CB816ACC6627802052C61A4099B7B0EC923971DB3B9F9204BDBCCFA457EE296E8986E64C6DC99E59436641567648CB84DEB7D7937F974F038D838274F3D3CF1BE8C84DDB000565880A776E5C0E13166E49F47119A4CA1311CF97B965E7CBBCB2CB384BD0D92ED105D0617856E80441124B31DE58B8C001607FEE668899693E3EFF8FBF1FCEEFBCF7CF9BA6C37640DDF7FFE6187B19ACF089D4C038F6607B78D38001FE67E56CCE399DE36D7DDBD699D5CFC5B6D7A1421CE06FE40DB6E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h0776C62C316FF94B0BC3A0288DE6A62B14D6C1A2DADF9BDF85B2CCB02CE1DB2D96632C3232C3974CDC1172E1779D8C6738251819975DB8146067301E0C0277B6B657485DCD62AC0662C8C005DDE7494C9CA13AAE3234BB0EE1B708A23A2F48AC4C3838641E940620F9CDDCCA14BCC07104C112BCC9032C48E925594CB886A604C9F7627EB100872A52FB5141D65111E6C8DA0ADB6CEC6004461D0E366B20DCCDB607E624499300E4DF6D95CB62F62FB75403E400EFBC3BD34080FC9CDCFCFCFFFFFFFFFFFFFFFFFFFFF7BFFFFFFFFFFFFFFFFFFFFFFFFFFFCF9FFFFFEFFFF81FFDDFFFFFFFFFFFFFF7FFBFFFBFDC0A6DBE6F8BE5BB7FE7A39B3DA3F3BE13B679; +// synopsys translate_on + +// Location: M9K_X22_Y4_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a14 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h4200420000441C443C0C3C00480018FC387C7C000000007E180038300000204880084204004204423E1E3E02247E3C7E3C7E7E7E7E30007E3C7E7E7E3C7E7C3C0400000000000C34023C2E302464003C00000000000000000020460024000000FF991E65536D2D8D9C9B4DB081C83A5A881B0DFDE2D72DF0FA08FCD6F664173D989098D02025E0F6043B4B9080F4923880C3A3B02D269E730C3DCC423386DCB98B4AD0C5C8D6119602E5121008325B7457090E914F4876EC8A18C664210A4C2392C7658400073421047C75FBE7BE73FDFFF05FEE07BF8AEF7F1378B359E8C61F8F692C2218C98A4A8748531986E7C770D984E0000C02060C000C0DF50F68A580; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h0100046606572583002086010800054C0F2DE8371AC0000A9003E024840C7C0806F6612D770080980A40D293FEC069F16CB2164CA033C539F69B37741AEF1CE3662FF5DF9CB107BB23A39EF7B95E7372200448DBDC18F9C0DE0EF379BF49480657781E91788044213E091339886F337D0612CA646CD48FC58EE77EDD7ECEC466C744FD00E1A7F9E9FBFE4777FD50ABD11F0E57FF4808802282200888A20AA88000000008800AC11D556264251ECFA68C056FBCCB040C614A6850222300D2F6FF59F878FCF5689FCFEF34BFD52FA2422A56A3C113409F7813007F8D6B5F80FE9D7FB1E62675F7C2CBE01032DCA16BADC570C1CBF7ECBC4E7E6C54A5D4550BE1A8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'hE33CB578DEBFAFAEDFD530DE8FA1992072F31B116644B18C72F9F44116C79ADF2F3982C7BE09AD4A32196807648A2495ADF98FD2B16CC096A5E25F5BC811C953CEC3000F432029B3FE3F211712944CA54D1940F193204C199C9F49666CC11B38C23B9D130CA49818913D3A2C1FBF71C5B0C774336F903C677D976189D98CA127AAAD6B6AF36195DA637C6EFA3E36E8FE97FA02EC26EB46198AD8DAD8C11260AF499D7BD86619EE5574CD27C80D39F71E653FDCF1B366737233CBB98D1E7B330F7DCCFC5939C4EC79CF0E1CD43BA7AFC716900A21BDB9DD0FCC7ECE1063238407C7E1B221EA10E38F64EF31CEBF3368E1C712BB1B33781134CFE54C2123349A6E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h5F9CB25A3631964C20007FF5754FC631A97D4F93986C30CF24394625658DE9A7C228A2050470925E29A35D8D06242712CD25C9241898204D85A710947C802013E1265727652C8F0C422BA8C28A0FBB893B0881E00403DDD8843B2D8EB929D0D8CB76E03779E019E2C4E4028219C38C202C9384E0D24E569C2E4D4D60B670CE37414D536A41D144B6C4624A2B00366D8CF6734A4A2DC465B308462CCBD1BF9CB863FC93EDB2CA5DC61B01639318985C88F01680E307C42311C0124700B28BF9B4FF7CCCEFE1996DE3ED6D8CFBF1871BD98EE7646242664EB2E338BD009838637124C921BB3332DC66D9C1706B6C48C3129639A3BA4088EDB496EDBBBFC2CC40B6; +// synopsys translate_on + +// Location: M9K_X22_Y23_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a14 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(gnd), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~79_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_first_bit_number = 6; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y26_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a6 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[6]~79_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_first_bit_number = 6; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFFFFFEBFFFFFFFFFFFFFFFFFFFFFFFBFFFFFFFFFFFFFFFFFDFFFFFFFFFFFFFBFFFFFFFFFEFFFFFFFDFFFFFFFFFFFFFEFFFFFFFDF8FFFFFFF9FFFFFFFFFFFFFFFF3FFFFFFE7FFFFFFFFFFFFFFFF; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000380001887600094C977486989000000000000000000000000FFFFFFFFC0810205C00018C36DC09CF97749EDCD00000000000000000000000000000001FFFFFFFDC004000B6D028BF17749ED8100000000000000000000000000000001BF7EFDF9400404A96D8289B57549FFC10000000000000000000000003F7EFDF90000000140041EB16D8298357DC9F7410000000000000000000000007FFFFFFD8000000340043AB160021E757DC9134100000000000000000000000040810207BFFFFFFF5FE430497702760D60099349000000000000000000000000408102073FFFFFFD5FE40E49774240C96009735D; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h5FE8334948F827C15FF88F8169A80ECB609EAD417A698FC178F33E8171F72A915FE836E948F807C95FF88F81E9A80FC7639E1FC17B2BBEC170730F8D70F7B0C1400826E548B807C95FF88F95E8280FCB63C6BCC17B3B3FC171AB3E81708734C1400826ED58F8258159F88B8168280FC161629DC17A3B3F41738B3F8150AF16E9400826ED581805C151D88A8160682FC1422297C17A2A39C162FB378550CF10A1400826ED58182581D1580B8761EC2FC14232B7C179AA39C5627B7781D0CF10D3400826E158182D81F0488A4B61EC0DC143789FC17BBB39C1610B7F81D45F11D34008A7E958080D01F0088A4160B42DD143689FC17B9B398561837F81D41702B1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h50DF086350368F0151C688016801460157EDE81148F310013FFFFFFF40810103D2D70D4B50168F0141D6C8116C01462153EDA90148F31D01BFFFFFFF40810107D2D7296354D68501403EC0016C01482173FDA08148F11F01800000037FFFFFFD4297893154DE81054022D2116C014D6153FCA00148D10F01000000013F7EFEF9429F810150CEC10143E042016C014C09537DA00148D11F01BF7EFEF900000001469F833150168D0543E04A116F014DA15379B181C8511F03FFFFFFFD00000001449AAB2155368D01482046016F416CA15079B001C8513E03C0810105FFFFFFFF403A8B0155C685014800461167476CA15039B08180413E0500000007FFFFFFFF; +// synopsys translate_on + +// Location: LCCOMB_X24_Y10_N16 +cycloneive_lcell_comb \Selector6~0 ( +// Equation(s): +// \Selector6~0_combout = (\z80_|address_pins_|abus[14]~23_combout & ((\Selector3~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout )) # (!\Selector3~0_combout & +// ((\ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ))))) # (!\z80_|address_pins_|abus[14]~23_combout & (\Selector3~0_combout )) + + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\Selector3~0_combout ), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ), + .cin(gnd), + .combout(\Selector6~0_combout ), + .cout()); +// synopsys translate_off +defparam \Selector6~0 .lut_mask = 16'hE6C4; +defparam \Selector6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y10_N18 +cycloneive_lcell_comb \Selector6~1 ( +// Equation(s): +// \Selector6~1_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\Selector6~0_combout )))) # (!\z80_|address_pins_|abus[14]~23_combout & ((\Selector6~0_combout & ((\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ))) # +// (!\Selector6~0_combout & (\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout )))) + + .dataa(\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ), + .datab(\z80_|address_pins_|abus[14]~23_combout ), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .datad(\Selector6~0_combout ), + .cin(gnd), + .combout(\Selector6~1_combout ), + .cout()); +// synopsys translate_off +defparam \Selector6~1 .lut_mask = 16'hFC22; +defparam \Selector6~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y10_N4 +cycloneive_lcell_comb \D[6]~88 ( +// Equation(s): +// \D[6]~88_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\Selector6~1_combout +// ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13_combout )))) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13_combout ), + .datad(\Selector6~1_combout ), + .cin(gnd), + .combout(\D[6]~88_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~88 .lut_mask = 16'hF4B0; +defparam \D[6]~88 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X16_Y34_N8 +cycloneive_io_ibuf \raw_loader_in~input ( + .i(raw_loader_in), + .ibar(gnd), + .o(\raw_loader_in~input_o )); +// synopsys translate_off +defparam \raw_loader_in~input .bus_hold = "false"; +defparam \raw_loader_in~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y10_N24 +cycloneive_lcell_comb \D[6]~69 ( +// Equation(s): +// \D[6]~69_combout = ((\z80_|address_pins_|DFFE_apin_latch [0]) # (\raw_loader_in~input_o )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) + + .dataa(gnd), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\z80_|address_pins_|DFFE_apin_latch [0]), + .datad(\raw_loader_in~input_o ), + .cin(gnd), + .combout(\D[6]~69_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~69 .lut_mask = 16'hFFF3; +defparam \D[6]~69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y10_N0 +cycloneive_lcell_comb \D[6]~78 ( +// Equation(s): +// \D[6]~78_combout = ((\Equal2~0_combout & ((\D[6]~69_combout ))) # (!\Equal2~0_combout & (\D[6]~88_combout ))) # (!\Equal2~1_combout ) + + .dataa(\Equal2~0_combout ), + .datab(\Equal2~1_combout ), + .datac(\D[6]~88_combout ), + .datad(\D[6]~69_combout ), + .cin(gnd), + .combout(\D[6]~78_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~78 .lut_mask = 16'hFB73; +defparam \D[6]~78 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y10_N6 +cycloneive_lcell_comb \D[6]~79 ( +// Equation(s): +// \D[6]~79_combout = (\z80_|pin_control_|bus_db_pin_oe~15_combout & (\z80_|data_pins_|dout [6] & ((\D[6]~78_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout & (((\D[6]~78_combout ) # (!\Equal2~1_combout )))) + + .dataa(\z80_|data_pins_|dout [6]), + .datab(\Equal2~1_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .datad(\D[6]~78_combout ), + .cin(gnd), + .combout(\D[6]~79_combout ), + .cout()); +// synopsys translate_off +defparam \D[6]~79 .lut_mask = 16'hAF03; +defparam \D[6]~79 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N18 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [6] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[6]~9_combout ) # ((\z80_|pin_control_|bus_db_pin_re~combout & \D[6]~79_combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & +// (\z80_|pin_control_|bus_db_pin_re~combout & (\D[6]~79_combout ))) + + .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datab(\z80_|pin_control_|bus_db_pin_re~combout ), + .datac(\D[6]~79_combout ), + .datad(\z80_|bus_control_|db[6]~9_combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [6]), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] .lut_mask = 16'hEAC0; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y13_N19 +dffeas \z80_|data_pins_|dout[6] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [6]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|data_pins_|dout [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|data_pins_|dout[6] .is_wysiwyg = "true"; +defparam \z80_|data_pins_|dout[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N6 +cycloneive_lcell_comb \z80_|bus_control_|db[6]~9 ( +// Equation(s): +// \z80_|bus_control_|db[6]~9_combout = ((\z80_|bus_control_|db[6]~8_combout & ((\z80_|data_pins_|dout [6]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) + + .dataa(\z80_|bus_control_|db[0]~6_combout ), + .datab(\z80_|bus_control_|db[6]~8_combout ), + .datac(\z80_|data_pins_|dout [6]), + .datad(\z80_|execute_|ctl_bus_db_oe~combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[6]~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[6]~9 .lut_mask = 16'hD5DD; +defparam \z80_|bus_control_|db[6]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y13_N7 +dffeas \z80_|ir_|opcode[6] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|bus_control_|db[6]~9_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|ir_|opcode [6]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|ir_|opcode[6] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y17_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~10 ( +// Equation(s): +// \z80_|execute_|ctl_ir_we~10_combout = (!\z80_|ir_|opcode [6] & (\z80_|ir_|opcode [7] & (\z80_|execute_|ctl_ir_we~5_combout & !\z80_|pla_decode_|Equal46~0_combout ))) + + .dataa(\z80_|ir_|opcode [6]), + .datab(\z80_|ir_|opcode [7]), + .datac(\z80_|execute_|ctl_ir_we~5_combout ), + .datad(\z80_|pla_decode_|Equal46~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_ir_we~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_ir_we~10 .lut_mask = 16'h0040; +defparam \z80_|execute_|ctl_ir_we~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N8 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~0 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~0_combout = (\z80_|execute_|ctl_alu_bs_oe~6_combout & (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~7_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~10_combout ), + .datab(\z80_|execute_|ctl_ir_we~7_combout ), + .datac(\z80_|execute_|ctl_alu_bs_oe~6_combout ), + .datad(\z80_|execute_|ctl_ir_we~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~0 .lut_mask = 16'h10F0; +defparam \z80_|execute_|ctl_bus_db_oe~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~4 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~4_combout = (!\z80_|execute_|ctl_bus_db_oe~3_combout ) # (!\z80_|execute_|ctl_bus_db_oe~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\z80_|execute_|ctl_bus_db_oe~0_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~4 .lut_mask = 16'h0FFF; +defparam \z80_|execute_|ctl_bus_db_oe~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~2 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~2_combout = (!\z80_|execute_|ctl_bus_ff_oe~1_combout & (!\z80_|execute_|ctl_bus_zero_oe~0_combout & ((\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) # (!\z80_|decode_state_|in_halt~q )))) + + .dataa(\z80_|execute_|ctl_bus_ff_oe~1_combout ), + .datab(\z80_|execute_|ctl_bus_zero_oe~0_combout ), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datad(\z80_|decode_state_|in_halt~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~2_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~2 .lut_mask = 16'h1011; +defparam \z80_|execute_|ctl_bus_db_oe~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y17_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~5 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~5_combout = (\z80_|execute_|ctl_ir_we~8_combout ) # ((\z80_|pla_decode_|Equal41~2_combout ) # ((\z80_|execute_|ctl_ir_we~14_combout ) # (\z80_|execute_|ctl_ir_we~11_combout ))) + + .dataa(\z80_|execute_|ctl_ir_we~8_combout ), + .datab(\z80_|pla_decode_|Equal41~2_combout ), + .datac(\z80_|execute_|ctl_ir_we~14_combout ), + .datad(\z80_|execute_|ctl_ir_we~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~5_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~5 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|ctl_bus_db_oe~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y17_N4 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~6 ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~6_combout = ((\z80_|execute_|ctl_66_oe~2_combout ) # ((\z80_|execute_|ctl_bus_db_oe~5_combout & \z80_|execute_|ctl_ir_we~4_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ), + .datab(\z80_|execute_|ctl_bus_db_oe~5_combout ), + .datac(\z80_|execute_|ctl_ir_we~4_combout ), + .datad(\z80_|execute_|ctl_66_oe~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe~6 .lut_mask = 16'hFFD5; +defparam \z80_|execute_|ctl_bus_db_oe~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe ( +// Equation(s): +// \z80_|execute_|ctl_bus_db_oe~combout = (\z80_|execute_|ctl_bus_db_oe~2_combout & ((\z80_|execute_|ctl_bus_db_oe~4_combout ) # ((\z80_|execute_|ctl_bus_db_oe~6_combout ) # (!\z80_|execute_|ctl_sw_1d~6_combout )))) + + .dataa(\z80_|execute_|ctl_bus_db_oe~4_combout ), + .datab(\z80_|execute_|ctl_bus_db_oe~2_combout ), + .datac(\z80_|execute_|ctl_sw_1d~6_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|ctl_bus_db_oe~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_bus_db_oe .lut_mask = 16'hCC8C; +defparam \z80_|execute_|ctl_bus_db_oe .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y13_N14 +cycloneive_lcell_comb \z80_|bus_control_|db[0]~6 ( +// Equation(s): +// \z80_|bus_control_|db[0]~6_combout = (\z80_|execute_|ctl_bus_db_oe~combout ) # ((\z80_|execute_|ctl_bus_db_we~7_combout ) # (!\z80_|execute_|ctl_bus_db_oe~2_combout )) + + .dataa(\z80_|execute_|ctl_bus_db_oe~combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datad(\z80_|execute_|ctl_bus_db_oe~2_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[0]~6 .lut_mask = 16'hFAFF; +defparam \z80_|bus_control_|db[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~61 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][2]~61_combout = (\ula_|zx_keyboard_|keys[7][2]~60_combout & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|zx_keyboard_|keys[7][2]~60_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [0]), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][2]~61_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2]~61 .lut_mask = 16'h2000; +defparam \ula_|zx_keyboard_|keys[7][2]~61 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~63 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][2]~63_combout = (\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[7][2]~61_combout ) # ((\ula_|zx_keyboard_|keys[5][4]~62_combout & \ula_|zx_keyboard_|keys[7][2]~30_combout )))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [3]), + .datab(\ula_|zx_keyboard_|keys[7][2]~61_combout ), + .datac(\ula_|zx_keyboard_|keys[5][4]~62_combout ), + .datad(\ula_|zx_keyboard_|keys[7][2]~30_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][2]~63_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2]~63 .lut_mask = 16'hA888; +defparam \ula_|zx_keyboard_|keys[7][2]~63 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~64 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][2]~64_combout = (\ula_|zx_keyboard_|keys[0][0]~13_combout & (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|keys[7][2]~63_combout & !\ula_|zx_keyboard_|extended~q ))) + + .dataa(\ula_|zx_keyboard_|keys[0][0]~13_combout ), + .datab(\ula_|ps2_keyboard_|shiftreg [2]), + .datac(\ula_|zx_keyboard_|keys[7][2]~63_combout ), + .datad(\ula_|zx_keyboard_|extended~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][2]~64_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2]~64 .lut_mask = 16'h0020; +defparam \ula_|zx_keyboard_|keys[7][2]~64 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y9_N4 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~65 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[7][2]~65_combout = (\ula_|zx_keyboard_|keys[7][2]~64_combout & (!\ula_|zx_keyboard_|Selector13~0_combout )) # (!\ula_|zx_keyboard_|keys[7][2]~64_combout & ((\ula_|zx_keyboard_|keys[7][2]~q ))) + + .dataa(\ula_|zx_keyboard_|Selector13~0_combout ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[7][2]~q ), + .datad(\ula_|zx_keyboard_|keys[7][2]~64_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[7][2]~65_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2]~65 .lut_mask = 16'h55F0; +defparam \ula_|zx_keyboard_|keys[7][2]~65 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y9_N5 +dffeas \ula_|zx_keyboard_|keys[7][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[7][2]~65_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[7][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[7][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[7][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N2 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~67 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][2]~67_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [4])) # (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [1] & +// !\ula_|ps2_keyboard_|shiftreg [4])) + + .dataa(\ula_|ps2_keyboard_|shiftreg [0]), + .datab(\ula_|ps2_keyboard_|shiftreg [1]), + .datac(gnd), + .datad(\ula_|ps2_keyboard_|shiftreg [4]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][2]~67_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][2]~67 .lut_mask = 16'h2244; +defparam \ula_|zx_keyboard_|keys[6][2]~67 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~68 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][2]~68_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[6][2]~67_combout & (\ula_|ps2_keyboard_|shiftreg [4] $ (!\ula_|ps2_keyboard_|shiftreg [2])))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|ps2_keyboard_|shiftreg [3]), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|zx_keyboard_|keys[6][2]~67_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][2]~68_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][2]~68 .lut_mask = 16'h2100; +defparam \ula_|zx_keyboard_|keys[6][2]~68 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~69 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[6][2]~69_combout = (\ula_|zx_keyboard_|keys[6][1]~39_combout & ((\ula_|zx_keyboard_|keys[6][2]~68_combout & (!\ula_|zx_keyboard_|keys[5][0]~66_combout )) # (!\ula_|zx_keyboard_|keys[6][2]~68_combout & +// ((\ula_|zx_keyboard_|keys[6][2]~q ))))) # (!\ula_|zx_keyboard_|keys[6][1]~39_combout & (((\ula_|zx_keyboard_|keys[6][2]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][0]~66_combout ), + .datab(\ula_|zx_keyboard_|keys[6][1]~39_combout ), + .datac(\ula_|zx_keyboard_|keys[6][2]~q ), + .datad(\ula_|zx_keyboard_|keys[6][2]~68_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[6][2]~69_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][2]~69 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[6][2]~69 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y8_N11 +dffeas \ula_|zx_keyboard_|keys[6][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[6][2]~69_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[6][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[6][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[6][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N12 +cycloneive_lcell_comb \D[2]~36 ( +// Equation(s): +// \D[2]~36_combout = (\ula_|zx_keyboard_|keys[7][2]~q & (\z80_|address_pins_|abus[15]~22_combout & ((\z80_|address_pins_|abus[14]~23_combout ) # (!\ula_|zx_keyboard_|keys[6][2]~q )))) # (!\ula_|zx_keyboard_|keys[7][2]~q & +// (((\z80_|address_pins_|abus[14]~23_combout )) # (!\ula_|zx_keyboard_|keys[6][2]~q ))) + + .dataa(\ula_|zx_keyboard_|keys[7][2]~q ), + .datab(\ula_|zx_keyboard_|keys[6][2]~q ), + .datac(\z80_|address_pins_|abus[14]~23_combout ), + .datad(\z80_|address_pins_|abus[15]~22_combout ), + .cin(gnd), + .combout(\D[2]~36_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~36 .lut_mask = 16'hF351; +defparam \D[2]~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~58 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][2]~58_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [1]))) # (!\ula_|ps2_keyboard_|shiftreg [6] & +// (!\ula_|zx_keyboard_|extended~q & (\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [6]), + .datab(\ula_|zx_keyboard_|extended~q ), + .datac(\ula_|ps2_keyboard_|shiftreg [3]), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][2]~58_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][2]~58 .lut_mask = 16'h1008; +defparam \ula_|zx_keyboard_|keys[4][2]~58 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~130 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][2]~130_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|zx_keyboard_|keys[4][2]~58_combout & (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [0]))) + + .dataa(\ula_|ps2_keyboard_|shiftreg [4]), + .datab(\ula_|zx_keyboard_|keys[4][2]~58_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [2]), + .datad(\ula_|ps2_keyboard_|shiftreg [0]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][2]~130_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][2]~130 .lut_mask = 16'h0080; +defparam \ula_|zx_keyboard_|keys[4][2]~130 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~59 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[4][2]~59_combout = (\ula_|zx_keyboard_|keys[3][4]~129_combout & ((\ula_|zx_keyboard_|keys[4][2]~130_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[4][2]~130_combout & ((\ula_|zx_keyboard_|keys[4][2]~q +// ))))) # (!\ula_|zx_keyboard_|keys[3][4]~129_combout & (((\ula_|zx_keyboard_|keys[4][2]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[3][4]~129_combout ), + .datac(\ula_|zx_keyboard_|keys[4][2]~q ), + .datad(\ula_|zx_keyboard_|keys[4][2]~130_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[4][2]~59_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][2]~59 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[4][2]~59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y8_N25 +dffeas \ula_|zx_keyboard_|keys[4][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[4][2]~59_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[4][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[4][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[4][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~56 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][2]~56_combout = (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [2]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [0]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][2]~56_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][2]~56 .lut_mask = 16'h00F0; +defparam \ula_|zx_keyboard_|keys[5][2]~56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y10_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~57 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[5][2]~57_combout = (\ula_|zx_keyboard_|keys[5][2]~56_combout & ((\ula_|zx_keyboard_|keys[5][2]~31_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[5][2]~31_combout & ((\ula_|zx_keyboard_|keys[5][2]~q +// ))))) # (!\ula_|zx_keyboard_|keys[5][2]~56_combout & (((\ula_|zx_keyboard_|keys[5][2]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[5][2]~56_combout ), + .datab(\ula_|zx_keyboard_|released~q ), + .datac(\ula_|zx_keyboard_|keys[5][2]~q ), + .datad(\ula_|zx_keyboard_|keys[5][2]~31_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[5][2]~57_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][2]~57 .lut_mask = 16'h72F0; +defparam \ula_|zx_keyboard_|keys[5][2]~57 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y10_N19 +dffeas \ula_|zx_keyboard_|keys[5][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[5][2]~57_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[5][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[5][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[5][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y8_N24 +cycloneive_lcell_comb \D[2]~35 ( +// Equation(s): +// \D[2]~35_combout = (\z80_|address_pins_|abus[13]~20_combout & (((\z80_|address_pins_|abus[12]~21_combout )) # (!\ula_|zx_keyboard_|keys[4][2]~q ))) # (!\z80_|address_pins_|abus[13]~20_combout & (!\ula_|zx_keyboard_|keys[5][2]~q & +// ((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][2]~q )))) + + .dataa(\z80_|address_pins_|abus[13]~20_combout ), + .datab(\ula_|zx_keyboard_|keys[4][2]~q ), + .datac(\z80_|address_pins_|abus[12]~21_combout ), + .datad(\ula_|zx_keyboard_|keys[5][2]~q ), + .cin(gnd), + .combout(\D[2]~35_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~35 .lut_mask = 16'hA2F3; +defparam \D[2]~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N10 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][2]~54 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][2]~54_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [2]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][2]~54_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][2]~54 .lut_mask = 16'h000F; +defparam \ula_|zx_keyboard_|keys[0][2]~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N18 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][2]~55 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[0][2]~55_combout = (\ula_|zx_keyboard_|keys[7][4]~49_combout & ((\ula_|zx_keyboard_|keys[0][2]~54_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[0][2]~54_combout & ((\ula_|zx_keyboard_|keys[0][2]~q +// ))))) # (!\ula_|zx_keyboard_|keys[7][4]~49_combout & (((\ula_|zx_keyboard_|keys[0][2]~q )))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(\ula_|zx_keyboard_|keys[7][4]~49_combout ), + .datac(\ula_|zx_keyboard_|keys[0][2]~q ), + .datad(\ula_|zx_keyboard_|keys[0][2]~54_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[0][2]~55_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][2]~55 .lut_mask = 16'h74F0; +defparam \ula_|zx_keyboard_|keys[0][2]~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y7_N19 +dffeas \ula_|zx_keyboard_|keys[0][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[0][2]~55_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[0][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[0][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[0][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N26 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][2]~50 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][2]~50_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [2]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(\ula_|ps2_keyboard_|shiftreg [2]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][2]~50_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][2]~50 .lut_mask = 16'h0F00; +defparam \ula_|zx_keyboard_|keys[3][2]~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N14 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][2]~51 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[3][2]~51_combout = (\ula_|zx_keyboard_|keys[3][2]~50_combout & ((\ula_|zx_keyboard_|keys[7][4]~49_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[7][4]~49_combout & (\ula_|zx_keyboard_|keys[3][2]~q +// )))) # (!\ula_|zx_keyboard_|keys[3][2]~50_combout & (((\ula_|zx_keyboard_|keys[3][2]~q )))) + + .dataa(\ula_|zx_keyboard_|keys[3][2]~50_combout ), + .datab(\ula_|zx_keyboard_|keys[7][4]~49_combout ), + .datac(\ula_|zx_keyboard_|keys[3][2]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[3][2]~51_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][2]~51 .lut_mask = 16'h70F8; +defparam \ula_|zx_keyboard_|keys[3][2]~51 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y7_N15 +dffeas \ula_|zx_keyboard_|keys[3][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[3][2]~51_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[3][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[3][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[3][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N12 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][2]~52 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][2]~52_combout = (\ula_|zx_keyboard_|Equal0~2_combout & (\ula_|zx_keyboard_|keys[7][4]~17_combout & (\ula_|zx_keyboard_|keys[3][2]~50_combout & !\ula_|ps2_keyboard_|shiftreg [1]))) + + .dataa(\ula_|zx_keyboard_|Equal0~2_combout ), + .datab(\ula_|zx_keyboard_|keys[7][4]~17_combout ), + .datac(\ula_|zx_keyboard_|keys[3][2]~50_combout ), + .datad(\ula_|ps2_keyboard_|shiftreg [1]), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][2]~52_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][2]~52 .lut_mask = 16'h0080; +defparam \ula_|zx_keyboard_|keys[2][2]~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N24 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][2]~53 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[2][2]~53_combout = (\ula_|zx_keyboard_|keys[2][2]~52_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[2][2]~52_combout & ((\ula_|zx_keyboard_|keys[2][2]~q ))) + + .dataa(\ula_|zx_keyboard_|released~q ), + .datab(gnd), + .datac(\ula_|zx_keyboard_|keys[2][2]~q ), + .datad(\ula_|zx_keyboard_|keys[2][2]~52_combout ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[2][2]~53_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][2]~53 .lut_mask = 16'h55F0; +defparam \ula_|zx_keyboard_|keys[2][2]~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y7_N25 +dffeas \ula_|zx_keyboard_|keys[2][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[2][2]~53_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[2][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[2][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[2][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y7_N8 +cycloneive_lcell_comb \D[2]~33 ( +// Equation(s): +// \D[2]~33_combout = (\ula_|zx_keyboard_|keys[3][2]~q & (\z80_|address_pins_|abus[11]~19_combout & ((\z80_|address_pins_|abus[10]~24_combout ) # (!\ula_|zx_keyboard_|keys[2][2]~q )))) # (!\ula_|zx_keyboard_|keys[3][2]~q & +// (((\z80_|address_pins_|abus[10]~24_combout )) # (!\ula_|zx_keyboard_|keys[2][2]~q ))) + + .dataa(\ula_|zx_keyboard_|keys[3][2]~q ), + .datab(\ula_|zx_keyboard_|keys[2][2]~q ), + .datac(\z80_|address_pins_|abus[11]~19_combout ), + .datad(\z80_|address_pins_|abus[10]~24_combout ), + .cin(gnd), + .combout(\D[2]~33_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~33 .lut_mask = 16'hF531; +defparam \D[2]~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N20 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][2]~47 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][2]~47_combout = (\ula_|zx_keyboard_|keys[6][4]~45_combout & (\ula_|zx_keyboard_|keys[6][4]~46_combout & !\ula_|ps2_keyboard_|shiftreg [4])) + + .dataa(\ula_|zx_keyboard_|keys[6][4]~45_combout ), + .datab(\ula_|zx_keyboard_|keys[6][4]~46_combout ), + .datac(\ula_|ps2_keyboard_|shiftreg [4]), + .datad(gnd), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][2]~47_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][2]~47 .lut_mask = 16'h0808; +defparam \ula_|zx_keyboard_|keys[1][2]~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N6 +cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][2]~48 ( +// Equation(s): +// \ula_|zx_keyboard_|keys[1][2]~48_combout = (\ula_|zx_keyboard_|keys[1][2]~47_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[1][2]~47_combout & (\ula_|zx_keyboard_|keys[1][2]~q )) + + .dataa(gnd), + .datab(\ula_|zx_keyboard_|keys[1][2]~47_combout ), + .datac(\ula_|zx_keyboard_|keys[1][2]~q ), + .datad(\ula_|zx_keyboard_|released~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|keys[1][2]~48_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][2]~48 .lut_mask = 16'h30FC; +defparam \ula_|zx_keyboard_|keys[1][2]~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y7_N7 +dffeas \ula_|zx_keyboard_|keys[1][2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|zx_keyboard_|keys[1][2]~48_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|zx_keyboard_|keys[1][2]~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|zx_keyboard_|keys[1][2] .is_wysiwyg = "true"; +defparam \ula_|zx_keyboard_|keys[1][2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N28 +cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~1 ( +// Equation(s): +// \ula_|zx_keyboard_|key_row~1_combout = (\z80_|address_pins_|DFFE_apin_latch [9]) # ((!\ula_|zx_keyboard_|keys[1][2]~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) + + .dataa(gnd), + .datab(\z80_|address_pins_|DFFE_apin_latch [9]), + .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datad(\ula_|zx_keyboard_|keys[1][2]~q ), + .cin(gnd), + .combout(\ula_|zx_keyboard_|key_row~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|zx_keyboard_|key_row~1 .lut_mask = 16'hCFFF; +defparam \ula_|zx_keyboard_|key_row~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y7_N4 +cycloneive_lcell_comb \D[2]~34 ( +// Equation(s): +// \D[2]~34_combout = (\D[2]~33_combout & (\ula_|zx_keyboard_|key_row~1_combout & ((\z80_|address_pins_|abus[8]~18_combout ) # (!\ula_|zx_keyboard_|keys[0][2]~q )))) + + .dataa(\z80_|address_pins_|abus[8]~18_combout ), + .datab(\ula_|zx_keyboard_|keys[0][2]~q ), + .datac(\D[2]~33_combout ), + .datad(\ula_|zx_keyboard_|key_row~1_combout ), + .cin(gnd), + .combout(\D[2]~34_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~34 .lut_mask = 16'hB000; +defparam \D[2]~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y8_N28 +cycloneive_lcell_comb \D[2]~37 ( +// Equation(s): +// \D[2]~37_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[2]~36_combout & (\D[2]~35_combout & \D[2]~34_combout ))) + + .dataa(\D[2]~36_combout ), + .datab(\D[2]~35_combout ), + .datac(\D[2]~34_combout ), + .datad(\z80_|address_pins_|abus[0]~16_combout ), + .cin(gnd), + .combout(\D[2]~37_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~37 .lut_mask = 16'hFF80; +defparam \D[2]~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y6_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a18 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[2]~39_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_first_bit_number = 2; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y9_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a2 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[2]~39_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024; +// synopsys translate_on + +// Location: M9K_X22_Y12_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a10 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[2]~39_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N26 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2 .lut_mask = 16'hDC98; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y5_N0 +cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a26 ( + .portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[2]~39_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .clk0_core_clock_enable = "ena0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .data_interleave_offset_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .data_interleave_width_in_bits = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .init_file = "led_patterns.mif"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .init_file_layout = "port_a"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .operation_mode = "single_port"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_address_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_byte_enable_clock = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_out_clear = "none"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_out_clock = "clock0"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_first_address = 0; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_first_bit_number = 2; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_last_address = 8191; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_logical_ram_depth = 32768; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_logical_ram_width = 8; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_b_address_width = 13; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_b_data_width = 1; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .ram_block_type = "M9K"; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N8 +cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~3 ( +// Equation(s): +// \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~3_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout & +// ((\ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout )))) # +// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout )))) + + .dataa(\ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout ), + .datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout ), + .datad(\ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ), + .cin(gnd), + .combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~3_combout ), + .cout()); +// synopsys translate_off +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~3 .lut_mask = 16'hF838; +defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y3_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a10 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h8102080042447C443C0C3C402004FC1838787840407A00707C02487E444878428008004042460424402040024A3242124220044022404208520A4A24424A125A0A1028440000524A0A4A4A204A5240460800100010540042002064547E0600001FA9BE02B828694B8A82CB8C8158226808198E9EC6B021F07A2098D5E0ECB639D2B1908129B6A2D646516192D87593189D8B2B26CD6E16234C1CC90AD9831EBD89EAD271ECC39A80507716BB49626B743DFFCF99576C3FAC889860E46618ACB79EC30EEDE42EB1E31F3976CA23243179FAA96DCD66D51535351770D410DC8531866136E6184518410368288C446EC63A4FEE425019C244097049C2B2DC8D93C4; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'hA111466C9493A2A7CA2204102414CC798BF0EEC2995A4814580BD07585585ED92E5172E82E845070000A846100500E84EA1803B8B07B99E1DC75BE6419674597B38F54EB9091AE3320201EE395AD63902282A031CE3E87CC902954AA515D5D6B6A855EC94CFEC4E0172C59A7D054F8F9F4356C312C204E40B05E2059407C8DC84683814663FB910969D1D631A952B381B7F635A33FD38D5CF15DF47D057F7FF555B555C2278100000A24804D7D98EB98602733818A12094F281287422CB40002464C92242004E0AE8518E001D124A7628010115D23C30462FC00A014A12133582A191E00538FC8A5004036A959ACB7A463D23E419EA06B744005385455A71250; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h6C60009CA281AEACDC1762945981B869F93D683EAF4AC7EE52412E85B60B91CD03AD0025F0D509F63202D877ECD8BF8005451F7BD346CF9E17B36F1850A7D80A8CF14A288EAE3BFE00FB2DB45080D4A50C58263A3B398DD51AB9CB554ECAA7B2E73D9D6D2C265859DB844C2C1952AD10241100174FE0444E6707D80A098D8585AAAC4802B74190FB007C0C0206186AFC1B3A2A46864F26118ED1D03ACB1062B7315502751655F60070E6B2C50609369611365AD1E3352327320331A51818030C7D8C4C59396600DC0C420495A0D987501490002BAD38012E20620D556A230B1796450B74E95A860FF3E434C65F1308F16F92395816B914F0CE870C1323347A4E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h7FC8531A7A319F3EBFC1383FFCDB0E09BD288288B078B4AD220B6FA934CF6187D972662C0D31E34E63B31CFC6EB4B35A69B67D85489E62EA99899A94F6800FDBA5D31B86A0288D29CE2EAAFF86A6A9F7000082293E6BB54F06E98ECCB199973EDA00FADB1D3A630BA18050635DE7DCB13B9B86E0CE6E08DC46331A352F716E3C441A0CC068A0823F8668A00621B779DE35FEC004050469F34866AEE766743D8C00FDF3B9F8DE7B76E97F8D32F0F39E4CAC68D9BBB68EA3915F6225F932CAAFDAD6E60DC661155EC9E80F8CEE659F19CC554B2C67C33EDCDA63BAD91B7D1842A7177AF49DF118FE47ACE3344964EBCADCFBB543F7729CCB340866D1157B6CCDDB; +// synopsys translate_on + +// Location: M9K_X22_Y29_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a2 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(gnd), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h77A47C739FF6A22B8B5CDC49E748E9C739BDE6756DB4D22437E74183E12400CBF7D3C6CC8C7841AB49CC538E8A72F2E73C64D3DF3662B19C07D7D299CBEDEF3E7DA5F4A8458A9451315B681ADA9AB0D63218DFB77D3353C32837E954604B9D98144A4566F47B71715BE6CDB8BA64D536762E9224D70F9A5C374B4D1CAB8DF527027170C5DBCC2B6AD72B8E4CCC94DAA139D8BA64E3384337426E7F274CC88A373AB1F9007B8A7F2936D16274F9BF8B6BABD48FCE74047C1E738C5B303E815BA720C76D6362915156A7671331CE657011862E594E46A6D99392E2D640D766869389A4D43867379AB880C1ACE279E451CB3A9063A0B320F65E536B8EEF9CBB9C76; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h9A2921ED6AA0CC8387B267B9E7A182720833CEE061E6450C8E4A72E3C043F21A0AD007E832124E92429C091D167806C10041AF32DDE13A669990457D098CC2FE3AC884B1E69101135CD080022451F20884CCB9CD203C141402A5AD293C3BABA95ADFAF6726384795A7656B753D2369B9EB5595BAA722012DF8DCFBF15BF46D6EB755D1CBF0DCF6FD40BEEC16EAB4A6D16839C98CBE9DBB437C69FB709F8E79993B9DDFE4F823D6E124B75BCE9B29F799F926619184B6C1178389F07349210436293A130C900FBA4EA70D2BA25B343C5B026D8E8766A4E4267CDAEC99E830D2307D94E6ED80D6722F3989B91E31C63B64C363DCE71A861C14382E270FC02868C7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h386BA04E797A3F8551DAD9D24A8D259A03ECFF5AB81B1C31DFDAE10100544F8CF1A8CCFC0C7A15BD9E7C2557CB00BF2584E16AAD13D7EDB525A85ABF90C0136DD195D748900C29DF7F381280A9738CDC3BF5BBF937D3A4D99CE2BCCD97CEF2C7F00030AFDB7F22E68CBAA4D9BE7633D3B53E90E4B124422A2A4454BACA5A8DC9352CD1DAFC910CC504334DF9E6F1F4F30161A36293CC5CCF1CA13994ED29D34A5699692496359B8E67A7E74D9A0FC504C8465638CF74A0AF9185921A7D2629893091900604017933442359491FBAB63F346F0C5EC8E3A531984B09E605A30A0627271C28420E47B8DEC74738FC3EDF9FBD40EC09FC7B4D3A1475BE433705FB5F; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h973FED2E9BEDBA474B70B121A8D60F3B4EE3F1A238FB3B730EDEEE74EC632DB4D7779D7B79D1C75DF87378E98719C1AF38B1B801C71D180CE86370AE9C2BF38CF84DBBB9878C55457324E92D3DAE91D729AC76BBAD4C6EECA74DAB5EE9A175EE34ABEB9DFAA48538A57E3E5C158947081CA41402E8E65478737F73BB629AAE2EE51D405CAF70F622DD4599602D7910DCAC8214B2A42025110593202C8B164C8DF6369572C3BB8AA1984A8D12F776E224ECEEB21F97FCD6C0CF17A044EC2BBF0571A553CCDD8ABA79BD27B7AF735ED2D34F1EF3A81A160C9ECB1B1FAE6EDEEFF99E28CC30C7C2553DED3378D655AD194B2E6C1BCBED700F6713D960F33E4C361A; +// synopsys translate_on + +// Location: M9K_X22_Y25_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a10 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(\z80_|address_pins_|abus[13]~20_combout ), + .ena1(gnd), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[2]~39_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .clk1_core_clock_enable = "ena1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_first_bit_number = 2; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; +// synopsys translate_on + +// Location: M9K_X22_Y27_N0 +cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a2 ( + .portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(\CLOCK_50~inputclkctrl_outclk ), + .ena0(!\z80_|address_pins_|abus[13]~20_combout ), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({\D[2]~39_combout }), + .portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout , +\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout , +\z80_|address_pins_|abus[0]~16_combout }), + .portabyteenamasks(1'b1), + .portbdatain({\~GND~combout }), + .portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4], +\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), + .portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file = "ula/test_scr.hex"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mixed_port_feed_through_mode = "dont_care"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "bidir_dual_port"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_in_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clear = "none"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_address = 0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_bit_number = 2; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_last_address = 8191; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_depth = 16384; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_width = 8; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_write_enable_clock = "clock1"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF00000000FFFFFFFFFFFFFFFFFFF68003FFF38003FFF9F403FFF8B003D8F87003FFF8F01BEDFC701FEBFEA01FDBFDC00FDBFDC01FC7FDC0FFC7FDE87FC7FCDC8FC7FCF89FC07071FFC0F873F3E0303FE7FFFFFFFFFFFFFFFF; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000000040078400234B1474928D1000000000000000000000000FFFFFFFF204081024004027153423DA5474928DD000000000000000000000000000000003FFFFFFF40041CB14162378547495999000000000000000000000000000000003FFFFFFF4004189141623485474959F90000000000000000000000003FFFFFFE40000001400400815B6223C15FC913DD0000000000000000000000007FFFFFFE40000001400402E9400333715FC973E5000000000000000000000000604081027FFFFFFD5FE60AE95763353540091361000000000000000000000000400000003FFFFFFC5FE60AE95763081D40011361; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h5FE0236948F816F55FE897C10C28028041DC8DE178059BC16900BB4173E47AC15FE8236148E806F55FE891054CA80E8148288DE179E597C169903AC153F13A8140080365486806D55FE891D548080A8148608FE159E493C16BB03FD152BD1AE14008037D482017D15FE881C548A00AC148E08FE159FC9AC16AA02FC15AAF18F1400083F1482007C15EE882C148E00A4148B08FE148F88D4168E436915ABB01E9400092F9480007815C2882C148E00B6149B49F614868FD41436476814AFA42A1400892FD480807C15C0883C149800FE149DC9FE14A60BD41431C3F914AEA01C1400882F1480817C11C0883C041940FE549CC9EE54860BDC143BC7D8108D2C4D0; +defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h0B928870484885014DE84481680162815375AC0148D308813FFFFFFC400000004B9288314DC0970149FC44856C0166815375AC8140D108817FFFFFFD6040808249D0A2094F908581481C40814C016099417DA88140D10B01400000017FFFFFFE48D083394B9085814A085081440166814179900140510F01400000013FFFFFFE4A508335498001814BE0608146016E8941799041405107413FFFFFFF000000004B98812149C005814BE0628146836E814179100140510F013FFFFFFF000000004B98A1114BE801814A00668147832C814119904140401F4120408082FFFFFFFF48D881154EA801854800768147C22CC14019900100003E0000000000FFFFFFFF; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N24 +cycloneive_lcell_comb \Selector0~0 ( +// Equation(s): +// \Selector0~0_combout = (\Selector3~0_combout & (((\ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout )) # (!\z80_|address_pins_|abus[14]~23_combout ))) # (!\Selector3~0_combout & (\z80_|address_pins_|abus[14]~23_combout & +// ((\ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout )))) + + .dataa(\Selector3~0_combout ), + .datab(\z80_|address_pins_|abus[14]~23_combout ), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout ), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ), + .cin(gnd), + .combout(\Selector0~0_combout ), + .cout()); +// synopsys translate_off +defparam \Selector0~0 .lut_mask = 16'hE6A2; +defparam \Selector0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N18 +cycloneive_lcell_comb \Selector0~1 ( +// Equation(s): +// \Selector0~1_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\Selector0~0_combout )))) # (!\z80_|address_pins_|abus[14]~23_combout & ((\Selector0~0_combout & (\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout )) # +// (!\Selector0~0_combout & ((\rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ))))) + + .dataa(\z80_|address_pins_|abus[14]~23_combout ), + .datab(\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ), + .datad(\Selector0~0_combout ), + .cin(gnd), + .combout(\Selector0~1_combout ), + .cout()); +// synopsys translate_off +defparam \Selector0~1 .lut_mask = 16'hEE50; +defparam \Selector0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N28 +cycloneive_lcell_comb \D[2]~82 ( +// Equation(s): +// \D[2]~82_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~3_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\Selector0~1_combout +// ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~3_combout )))) + + .dataa(\z80_|address_pins_|DFFE_apin_latch [15]), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~3_combout ), + .datad(\Selector0~1_combout ), + .cin(gnd), + .combout(\D[2]~82_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~82 .lut_mask = 16'hF4B0; +defparam \D[2]~82 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N12 +cycloneive_lcell_comb \D[2]~38 ( +// Equation(s): +// \D[2]~38_combout = ((\Equal2~0_combout & (\D[2]~37_combout )) # (!\Equal2~0_combout & ((\D[2]~82_combout )))) # (!\Equal2~1_combout ) + + .dataa(\Equal2~1_combout ), + .datab(\Equal2~0_combout ), + .datac(\D[2]~37_combout ), + .datad(\D[2]~82_combout ), + .cin(gnd), + .combout(\D[2]~38_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~38 .lut_mask = 16'hF7D5; +defparam \D[2]~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y10_N30 +cycloneive_lcell_comb \D[2]~39 ( +// Equation(s): +// \D[2]~39_combout = (\z80_|pin_control_|bus_db_pin_oe~15_combout & (((\z80_|data_pins_|dout [2] & \D[2]~38_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout & (((\D[2]~38_combout )) # (!\Equal2~1_combout ))) + + .dataa(\Equal2~1_combout ), + .datab(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .datac(\z80_|data_pins_|dout [2]), + .datad(\D[2]~38_combout ), + .cin(gnd), + .combout(\D[2]~39_combout ), + .cout()); +// synopsys translate_off +defparam \D[2]~39 .lut_mask = 16'hF311; +defparam \D[2]~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N4 +cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] ( +// Equation(s): +// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [2] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[2]~13_combout ) # ((\D[2]~39_combout & \z80_|pin_control_|bus_db_pin_re~combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout & +// (((\D[2]~39_combout & \z80_|pin_control_|bus_db_pin_re~combout )))) + + .dataa(\z80_|execute_|ctl_bus_db_we~7_combout ), + .datab(\z80_|bus_control_|db[2]~13_combout ), + .datac(\D[2]~39_combout ), + .datad(\z80_|pin_control_|bus_db_pin_re~combout ), + .cin(gnd), + .combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [2]), + .cout()); +// synopsys translate_off +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] .lut_mask = 16'hF888; +defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y13_N5 +dffeas \z80_|data_pins_|dout[2] ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [2]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|data_pins_|dout [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|data_pins_|dout[2] .is_wysiwyg = "true"; +defparam \z80_|data_pins_|dout[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y13_N6 +cycloneive_lcell_comb \z80_|bus_control_|db[2]~12 ( +// Equation(s): +// \z80_|bus_control_|db[2]~12_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[2]~29_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout ))) + + .dataa(\z80_|bus_control_|db[0]~4_combout ), + .datab(gnd), + .datac(\z80_|alu_control_|db[2]~29_combout ), + .datad(\z80_|execute_|ctl_bus_db_we~7_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[2]~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[2]~12 .lut_mask = 16'hA0AA; +defparam \z80_|bus_control_|db[2]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y13_N0 +cycloneive_lcell_comb \z80_|bus_control_|db[2]~13 ( +// Equation(s): +// \z80_|bus_control_|db[2]~13_combout = ((\z80_|bus_control_|db[2]~12_combout & ((\z80_|data_pins_|dout [2]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout ) + + .dataa(\z80_|bus_control_|db[0]~6_combout ), + .datab(\z80_|execute_|ctl_bus_db_oe~combout ), + .datac(\z80_|data_pins_|dout [2]), + .datad(\z80_|bus_control_|db[2]~12_combout ), + .cin(gnd), + .combout(\z80_|bus_control_|db[2]~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|bus_control_|db[2]~13 .lut_mask = 16'hF755; +defparam \z80_|bus_control_|db[2]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y13_N27 +dffeas \z80_|ir_|opcode[2] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|bus_control_|db[2]~13_combout ), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\z80_|execute_|ctl_ir_we~13_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|ir_|opcode [2]), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|ir_|opcode[2] .is_wysiwyg = "true"; +defparam \z80_|ir_|opcode[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N18 +cycloneive_lcell_comb \z80_|pla_decode_|Equal1~4 ( +// Equation(s): +// \z80_|pla_decode_|Equal1~4_combout = (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [1]) + + .dataa(gnd), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|ir_|opcode [1]), + .datad(gnd), + .cin(gnd), + .combout(\z80_|pla_decode_|Equal1~4_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|pla_decode_|Equal1~4 .lut_mask = 16'h0303; +defparam \z80_|pla_decode_|Equal1~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~26 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~26_combout = (\z80_|pla_decode_|Equal1~4_combout & (\z80_|execute_|ctl_mWrite~5_combout & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|ir_|opcode [0]))) + + .dataa(\z80_|pla_decode_|Equal1~4_combout ), + .datab(\z80_|execute_|ctl_mWrite~5_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|ir_|opcode [0]), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~26 .lut_mask = 16'h0080; +defparam \z80_|execute_|ctl_alu_op_low~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y16_N18 +cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~45 ( +// Equation(s): +// \z80_|execute_|ctl_alu_op_low~45_combout = (!\z80_|execute_|ctl_alu_op_low~26_combout & (((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|pla_decode_|Equal13~2_combout )) # (!\z80_|sequencer_|DFFE_M4_ff~q ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~26_combout ), + .datab(\z80_|sequencer_|DFFE_M4_ff~q ), + .datac(\z80_|pla_decode_|Equal13~2_combout ), + .datad(\z80_|sequencer_|DFFE_T3_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|ctl_alu_op_low~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|ctl_alu_op_low~45 .lut_mask = 16'h1555; +defparam \z80_|execute_|ctl_alu_op_low~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y18_N28 +cycloneive_lcell_comb \z80_|execute_|setM1~17 ( +// Equation(s): +// \z80_|execute_|setM1~17_combout = (!\z80_|execute_|ctl_alu_shift_oe~15_combout & (\z80_|execute_|ctl_sw_2u~1_combout & \z80_|execute_|ctl_state_alu~7_combout )) + + .dataa(\z80_|execute_|ctl_alu_shift_oe~15_combout ), + .datab(gnd), + .datac(\z80_|execute_|ctl_sw_2u~1_combout ), + .datad(\z80_|execute_|ctl_state_alu~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~17_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~17 .lut_mask = 16'h5000; +defparam \z80_|execute_|setM1~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y18_N30 +cycloneive_lcell_comb \z80_|execute_|setM1~18 ( +// Equation(s): +// \z80_|execute_|setM1~18_combout = (\z80_|execute_|ctl_alu_op_low~45_combout & (\z80_|execute_|setM1~17_combout & (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & !\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ))) + + .dataa(\z80_|execute_|ctl_alu_op_low~45_combout ), + .datab(\z80_|execute_|setM1~17_combout ), + .datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ), + .datad(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~18_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~18 .lut_mask = 16'h0008; +defparam \z80_|execute_|setM1~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|setM1~11 ( +// Equation(s): +// \z80_|execute_|setM1~11_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ) # ((!\z80_|ir_|opcode [2] & (\z80_|execute_|ctl_mWrite~4_combout & !\z80_|ir_|opcode [4]))) + + .dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datab(\z80_|ir_|opcode [2]), + .datac(\z80_|execute_|ctl_mWrite~4_combout ), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|setM1~11_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~11 .lut_mask = 16'hAABA; +defparam \z80_|execute_|setM1~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N10 +cycloneive_lcell_comb \z80_|execute_|setM1~10 ( +// Equation(s): +// \z80_|execute_|setM1~10_combout = (\z80_|execute_|ctl_mRead~5_combout ) # (((\z80_|execute_|ctl_mWrite~6_combout ) # (\z80_|pla_decode_|Equal6~1_combout )) # (!\z80_|execute_|fMWrite~1_combout )) + + .dataa(\z80_|execute_|ctl_mRead~5_combout ), + .datab(\z80_|execute_|fMWrite~1_combout ), + .datac(\z80_|execute_|ctl_mWrite~6_combout ), + .datad(\z80_|pla_decode_|Equal6~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~10_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~10 .lut_mask = 16'hFFFB; +defparam \z80_|execute_|setM1~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|setM1~12 ( +// Equation(s): +// \z80_|execute_|setM1~12_combout = ((\z80_|execute_|setM1~10_combout ) # ((\z80_|execute_|setM1~11_combout & \z80_|execute_|ctl_mWrite~17_combout ))) # (!\z80_|execute_|nextM~2_combout ) + + .dataa(\z80_|execute_|nextM~2_combout ), + .datab(\z80_|execute_|setM1~11_combout ), + .datac(\z80_|execute_|ctl_mWrite~17_combout ), + .datad(\z80_|execute_|setM1~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~12_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~12 .lut_mask = 16'hFFD5; +defparam \z80_|execute_|setM1~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|setM1~8 ( +// Equation(s): +// \z80_|execute_|setM1~8_combout = (\z80_|execute_|ctl_al_we~13_combout & (\z80_|sequencer_|M5~q & ((\z80_|pla_decode_|Equal9~1_combout )))) # (!\z80_|execute_|ctl_al_we~13_combout & ((\z80_|sequencer_|DFFE_M4_ff~q ) # ((\z80_|sequencer_|M5~q & +// \z80_|pla_decode_|Equal9~1_combout )))) + + .dataa(\z80_|execute_|ctl_al_we~13_combout ), + .datab(\z80_|sequencer_|M5~q ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|pla_decode_|Equal9~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~8_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~8 .lut_mask = 16'hDC50; +defparam \z80_|execute_|setM1~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y12_N2 +cycloneive_lcell_comb \z80_|execute_|setM1~9 ( +// Equation(s): +// \z80_|execute_|setM1~9_combout = ((\z80_|sequencer_|DFFE_T5_ff~q & \z80_|execute_|setM1~8_combout )) # (!\z80_|execute_|ctl_flags_xy_we~19_combout ) + + .dataa(\z80_|execute_|ctl_flags_xy_we~19_combout ), + .datab(\z80_|sequencer_|DFFE_T5_ff~q ), + .datac(gnd), + .datad(\z80_|execute_|setM1~8_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~9_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~9 .lut_mask = 16'hDD55; +defparam \z80_|execute_|setM1~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N18 +cycloneive_lcell_comb \z80_|execute_|setM1~13 ( +// Equation(s): +// \z80_|execute_|setM1~13_combout = ((\z80_|execute_|setM1~9_combout ) # ((\z80_|execute_|setM1~12_combout & \z80_|execute_|ixy_d~6_combout ))) # (!\z80_|reg_control_|reg_sel_pc~3_combout ) + + .dataa(\z80_|reg_control_|reg_sel_pc~3_combout ), + .datab(\z80_|execute_|setM1~12_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|setM1~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~13_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~13 .lut_mask = 16'hFFD5; +defparam \z80_|execute_|setM1~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|setM1~15 ( +// Equation(s): +// \z80_|execute_|setM1~15_combout = (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|pla_decode_|Equal13~0_combout & ((!\z80_|pla_decode_|Equal21~2_combout ) # (!\z80_|pla_decode_|Equal32~0_combout )))) # (!\z80_|pla_decode_|Equal33~0_combout & +// (((!\z80_|pla_decode_|Equal21~2_combout )) # (!\z80_|pla_decode_|Equal32~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal33~0_combout ), + .datab(\z80_|pla_decode_|Equal32~0_combout ), + .datac(\z80_|pla_decode_|Equal13~0_combout ), + .datad(\z80_|pla_decode_|Equal21~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~15_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~15 .lut_mask = 16'h135F; +defparam \z80_|execute_|setM1~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N24 +cycloneive_lcell_comb \z80_|execute_|setM1~14 ( +// Equation(s): +// \z80_|execute_|setM1~14_combout = (!\z80_|execute_|ctl_alu_oe~1_combout & (!\z80_|pla_decode_|Equal77~1_combout & (!\z80_|pla_decode_|Equal1~6_combout & !\z80_|pla_decode_|Equal2~2_combout ))) + + .dataa(\z80_|execute_|ctl_alu_oe~1_combout ), + .datab(\z80_|pla_decode_|Equal77~1_combout ), + .datac(\z80_|pla_decode_|Equal1~6_combout ), + .datad(\z80_|pla_decode_|Equal2~2_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~14_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~14 .lut_mask = 16'h0001; +defparam \z80_|execute_|setM1~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y13_N30 +cycloneive_lcell_comb \z80_|execute_|setM1~16 ( +// Equation(s): +// \z80_|execute_|setM1~16_combout = (\z80_|interrupts_|test1~2_combout & (\z80_|execute_|setM1~15_combout & \z80_|execute_|setM1~14_combout )) + + .dataa(gnd), + .datab(\z80_|interrupts_|test1~2_combout ), + .datac(\z80_|execute_|setM1~15_combout ), + .datad(\z80_|execute_|setM1~14_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~16_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~16 .lut_mask = 16'hC000; +defparam \z80_|execute_|setM1~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N28 +cycloneive_lcell_comb \z80_|execute_|setM1~19 ( +// Equation(s): +// \z80_|execute_|setM1~19_combout = ((\z80_|execute_|setM1~13_combout ) # ((!\z80_|execute_|setM1~16_combout & \z80_|execute_|ctl_eval_cond~0_combout ))) # (!\z80_|execute_|setM1~18_combout ) + + .dataa(\z80_|execute_|setM1~18_combout ), + .datab(\z80_|execute_|setM1~13_combout ), + .datac(\z80_|execute_|setM1~16_combout ), + .datad(\z80_|execute_|ctl_eval_cond~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~19_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~19 .lut_mask = 16'hDFDD; +defparam \z80_|execute_|setM1~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N16 +cycloneive_lcell_comb \z80_|execute_|setM1~23 ( +// Equation(s): +// \z80_|execute_|setM1~23_combout = (\z80_|execute_|fMWrite~1_combout & (!\z80_|execute_|ctl_mRead~8_combout & (!\z80_|execute_|ctl_mRead~6_combout & \z80_|execute_|fMWrite~6_combout ))) + + .dataa(\z80_|execute_|fMWrite~1_combout ), + .datab(\z80_|execute_|ctl_mRead~8_combout ), + .datac(\z80_|execute_|ctl_mRead~6_combout ), + .datad(\z80_|execute_|fMWrite~6_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~23_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~23 .lut_mask = 16'h0200; +defparam \z80_|execute_|setM1~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|setM1~22 ( +// Equation(s): +// \z80_|execute_|setM1~22_combout = (\z80_|decode_state_|DFFE_instNonRep~q ) # ((!\z80_|ir_|opcode [2] & (\z80_|execute_|ctl_mWrite~4_combout & !\z80_|ir_|opcode [4]))) + + .dataa(\z80_|ir_|opcode [2]), + .datab(\z80_|execute_|ctl_mWrite~4_combout ), + .datac(\z80_|decode_state_|DFFE_instNonRep~q ), + .datad(\z80_|ir_|opcode [4]), + .cin(gnd), + .combout(\z80_|execute_|setM1~22_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~22 .lut_mask = 16'hF0F4; +defparam \z80_|execute_|setM1~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|setM1~56 ( +// Equation(s): +// \z80_|execute_|setM1~56_combout = (\z80_|sequencer_|DFFE_T5_ff~q & ((\z80_|sequencer_|DFFE_M4_ff~q ) # ((\z80_|sequencer_|DFFE_M3_ff~q & \z80_|execute_|setM1~22_combout )))) + + .dataa(\z80_|sequencer_|DFFE_M3_ff~q ), + .datab(\z80_|sequencer_|DFFE_T5_ff~q ), + .datac(\z80_|sequencer_|DFFE_M4_ff~q ), + .datad(\z80_|execute_|setM1~22_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~56_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~56 .lut_mask = 16'hC8C0; +defparam \z80_|execute_|setM1~56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N6 +cycloneive_lcell_comb \z80_|execute_|setM1~24 ( +// Equation(s): +// \z80_|execute_|setM1~24_combout = (\z80_|execute_|setM1~23_combout & (!\z80_|execute_|ctl_flags_bus~1_combout & ((\z80_|execute_|setM1~56_combout )))) # (!\z80_|execute_|setM1~23_combout & ((\z80_|execute_|ctl_reg_in_hi~2_combout ) # +// ((!\z80_|execute_|ctl_flags_bus~1_combout & \z80_|execute_|setM1~56_combout )))) + + .dataa(\z80_|execute_|setM1~23_combout ), + .datab(\z80_|execute_|ctl_flags_bus~1_combout ), + .datac(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datad(\z80_|execute_|setM1~56_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~24_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~24 .lut_mask = 16'h7350; +defparam \z80_|execute_|setM1~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y15_N4 +cycloneive_lcell_comb \z80_|execute_|setM1~25 ( +// Equation(s): +// \z80_|execute_|setM1~25_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & (((\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & !\z80_|execute_|ctl_mRead~10_combout )) # (!\z80_|alu_control_|flags_cond_true~q ))) # +// (!\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & (((\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & !\z80_|execute_|ctl_mRead~10_combout )))) + + .dataa(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ), + .datab(\z80_|alu_control_|flags_cond_true~q ), + .datac(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ), + .datad(\z80_|execute_|ctl_mRead~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~25_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~25 .lut_mask = 16'h22F2; +defparam \z80_|execute_|setM1~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y12_N12 +cycloneive_lcell_comb \z80_|execute_|setM1~26 ( +// Equation(s): +// \z80_|execute_|setM1~26_combout = ((\z80_|execute_|ctl_mRead~11_combout ) # ((!\z80_|alu_control_|flags_cond_true~q & \z80_|pla_decode_|Equal40~1_combout ))) # (!\z80_|execute_|ctl_bus_inc_oe~31_combout ) + + .dataa(\z80_|execute_|ctl_bus_inc_oe~31_combout ), + .datab(\z80_|alu_control_|flags_cond_true~q ), + .datac(\z80_|pla_decode_|Equal40~1_combout ), + .datad(\z80_|execute_|ctl_mRead~11_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~26_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~26 .lut_mask = 16'hFF75; +defparam \z80_|execute_|setM1~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N16 +cycloneive_lcell_comb \z80_|execute_|setM1~27 ( +// Equation(s): +// \z80_|execute_|setM1~27_combout = (\z80_|execute_|setM1~26_combout ) # (((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & \z80_|pla_decode_|Equal21~1_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout )) + + .dataa(\z80_|execute_|setM1~26_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ), + .datad(\z80_|pla_decode_|Equal21~1_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~27_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~27 .lut_mask = 16'hEFAF; +defparam \z80_|execute_|setM1~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N10 +cycloneive_lcell_comb \z80_|execute_|setM1~28 ( +// Equation(s): +// \z80_|execute_|setM1~28_combout = (\z80_|execute_|setM1~24_combout ) # ((\z80_|execute_|setM1~25_combout ) # ((\z80_|execute_|ctl_state_alu~2_combout & \z80_|execute_|setM1~27_combout ))) + + .dataa(\z80_|execute_|setM1~24_combout ), + .datab(\z80_|execute_|ctl_state_alu~2_combout ), + .datac(\z80_|execute_|setM1~25_combout ), + .datad(\z80_|execute_|setM1~27_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~28_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~28 .lut_mask = 16'hFEFA; +defparam \z80_|execute_|setM1~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N18 +cycloneive_lcell_comb \z80_|execute_|setM1~55 ( +// Equation(s): +// \z80_|execute_|setM1~55_combout = ((\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|execute_|ctl_iorw~10_combout ))) # (!\z80_|execute_|ctl_flags_sz_we~0_combout ) + + .dataa(\z80_|execute_|ctl_flags_sz_we~0_combout ), + .datab(\z80_|sequencer_|DFFE_M2_ff~q ), + .datac(\z80_|sequencer_|DFFE_T4_ff~q ), + .datad(\z80_|execute_|ctl_iorw~10_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~55_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~55 .lut_mask = 16'hD555; +defparam \z80_|execute_|setM1~55 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N4 +cycloneive_lcell_comb \z80_|execute_|setM1~29 ( +// Equation(s): +// \z80_|execute_|setM1~29_combout = (\z80_|execute_|ctl_mRead~13_combout ) # ((\z80_|execute_|ctl_mRead~5_combout ) # ((\z80_|execute_|ctl_mRead~7_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~13_combout ), + .datab(\z80_|execute_|ctl_mRead~5_combout ), + .datac(\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ), + .datad(\z80_|execute_|ctl_mRead~7_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~29_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~29 .lut_mask = 16'hFFEF; +defparam \z80_|execute_|setM1~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N12 +cycloneive_lcell_comb \z80_|execute_|setM1~31 ( +// Equation(s): +// \z80_|execute_|setM1~31_combout = (((\z80_|execute_|ctl_state_alu~4_combout & \z80_|execute_|setM1~29_combout )) # (!\z80_|execute_|setM1~57_combout )) # (!\z80_|execute_|setM1~30_combout ) + + .dataa(\z80_|execute_|setM1~30_combout ), + .datab(\z80_|execute_|ctl_state_alu~4_combout ), + .datac(\z80_|execute_|setM1~29_combout ), + .datad(\z80_|execute_|setM1~57_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~31_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~31 .lut_mask = 16'hD5FF; +defparam \z80_|execute_|setM1~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N20 +cycloneive_lcell_comb \z80_|execute_|setM1~33 ( +// Equation(s): +// \z80_|execute_|setM1~33_combout = (\z80_|execute_|ctl_mRead~2_combout ) # ((\z80_|execute_|ctl_mRead~3_combout ) # ((\z80_|execute_|ctl_mRead~34_combout & \z80_|execute_|setM1~11_combout ))) + + .dataa(\z80_|execute_|ctl_mRead~2_combout ), + .datab(\z80_|execute_|ctl_mRead~34_combout ), + .datac(\z80_|execute_|setM1~11_combout ), + .datad(\z80_|execute_|ctl_mRead~3_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~33_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~33 .lut_mask = 16'hFFEA; +defparam \z80_|execute_|setM1~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N2 +cycloneive_lcell_comb \z80_|execute_|setM1~32 ( +// Equation(s): +// \z80_|execute_|setM1~32_combout = (\z80_|pla_decode_|Equal35~0_combout & ((\z80_|execute_|ixy_d~6_combout ) # ((\z80_|execute_|ctl_reg_in_hi~2_combout & \z80_|execute_|ctl_mRead~16_combout )))) # (!\z80_|pla_decode_|Equal35~0_combout & +// (\z80_|execute_|ctl_reg_in_hi~2_combout & ((\z80_|execute_|ctl_mRead~16_combout )))) + + .dataa(\z80_|pla_decode_|Equal35~0_combout ), + .datab(\z80_|execute_|ctl_reg_in_hi~2_combout ), + .datac(\z80_|execute_|ixy_d~6_combout ), + .datad(\z80_|execute_|ctl_mRead~16_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~32_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~32 .lut_mask = 16'hECA0; +defparam \z80_|execute_|setM1~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N26 +cycloneive_lcell_comb \z80_|execute_|setM1~34 ( +// Equation(s): +// \z80_|execute_|setM1~34_combout = (\z80_|execute_|setM1~31_combout ) # ((\z80_|execute_|setM1~32_combout ) # ((\z80_|execute_|setM1~33_combout & \z80_|execute_|ixy_d~9_combout ))) + + .dataa(\z80_|execute_|setM1~31_combout ), + .datab(\z80_|execute_|setM1~33_combout ), + .datac(\z80_|execute_|ixy_d~9_combout ), + .datad(\z80_|execute_|setM1~32_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~34_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~34 .lut_mask = 16'hFFEA; +defparam \z80_|execute_|setM1~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N0 +cycloneive_lcell_comb \z80_|execute_|setM1~20 ( +// Equation(s): +// \z80_|execute_|setM1~20_combout = (\z80_|execute_|ctl_mRead~9_combout & (((\z80_|pla_decode_|Equal37~0_combout & !\z80_|alu_control_|flags_cond_true~q )) # (!\z80_|execute_|ctl_flags_bus~0_combout ))) + + .dataa(\z80_|pla_decode_|Equal37~0_combout ), + .datab(\z80_|alu_control_|flags_cond_true~q ), + .datac(\z80_|execute_|ctl_mRead~9_combout ), + .datad(\z80_|execute_|ctl_flags_bus~0_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~20_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~20 .lut_mask = 16'h20F0; +defparam \z80_|execute_|setM1~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N0 +cycloneive_lcell_comb \z80_|execute_|setM1~21 ( +// Equation(s): +// \z80_|execute_|setM1~21_combout = (\z80_|execute_|setM1~20_combout ) # ((\z80_|execute_|ixy_d~8_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & \z80_|pla_decode_|Equal10~0_combout ))) + + .dataa(\z80_|execute_|ixy_d~8_combout ), + .datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ), + .datac(\z80_|pla_decode_|Equal10~0_combout ), + .datad(\z80_|execute_|setM1~20_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~21_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~21 .lut_mask = 16'hFF80; +defparam \z80_|execute_|setM1~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y13_N28 +cycloneive_lcell_comb \z80_|execute_|setM1~35 ( +// Equation(s): +// \z80_|execute_|setM1~35_combout = (\z80_|execute_|setM1~28_combout ) # ((\z80_|execute_|setM1~55_combout ) # ((\z80_|execute_|setM1~34_combout ) # (\z80_|execute_|setM1~21_combout ))) + + .dataa(\z80_|execute_|setM1~28_combout ), + .datab(\z80_|execute_|setM1~55_combout ), + .datac(\z80_|execute_|setM1~34_combout ), + .datad(\z80_|execute_|setM1~21_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~35_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~35 .lut_mask = 16'hFFFE; +defparam \z80_|execute_|setM1~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N0 +cycloneive_lcell_comb \z80_|execute_|setM1~43 ( +// Equation(s): +// \z80_|execute_|setM1~43_combout = (!\z80_|execute_|ctl_mWrite~6_combout & (!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~9_combout )) + + .dataa(gnd), + .datab(\z80_|execute_|ctl_mWrite~6_combout ), + .datac(\z80_|execute_|ctl_ir_we~10_combout ), + .datad(\z80_|execute_|ctl_ir_we~9_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~43_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~43 .lut_mask = 16'h0003; +defparam \z80_|execute_|setM1~43 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y14_N6 +cycloneive_lcell_comb \z80_|execute_|setM1~44 ( +// Equation(s): +// \z80_|execute_|setM1~44_combout = (!\z80_|pla_decode_|Equal47~0_combout & (!\z80_|pla_decode_|Equal37~0_combout & (!\z80_|pla_decode_|Equal38~2_combout & \z80_|sequencer_|DFFE_T4_ff~q ))) + + .dataa(\z80_|pla_decode_|Equal47~0_combout ), + .datab(\z80_|pla_decode_|Equal37~0_combout ), + .datac(\z80_|pla_decode_|Equal38~2_combout ), + .datad(\z80_|sequencer_|DFFE_T4_ff~q ), + .cin(gnd), + .combout(\z80_|execute_|setM1~44_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~44 .lut_mask = 16'h0100; +defparam \z80_|execute_|setM1~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y14_N18 +cycloneive_lcell_comb \z80_|execute_|setM1~45 ( +// Equation(s): +// \z80_|execute_|setM1~45_combout = (!\z80_|pla_decode_|Equal21~1_combout & (\z80_|execute_|setM1~43_combout & (!\z80_|pla_decode_|Equal48~0_combout & \z80_|execute_|setM1~44_combout ))) + + .dataa(\z80_|pla_decode_|Equal21~1_combout ), + .datab(\z80_|execute_|setM1~43_combout ), + .datac(\z80_|pla_decode_|Equal48~0_combout ), + .datad(\z80_|execute_|setM1~44_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~45_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~45 .lut_mask = 16'h0400; +defparam \z80_|execute_|setM1~45 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N20 +cycloneive_lcell_comb \z80_|execute_|setM1~46 ( +// Equation(s): +// \z80_|execute_|setM1~46_combout = (\z80_|execute_|setM1~45_combout & (\z80_|execute_|setM1~42_combout & ((!\z80_|pla_decode_|Equal1~4_combout ) # (!\z80_|pla_decode_|Equal2~1_combout )))) + + .dataa(\z80_|execute_|setM1~45_combout ), + .datab(\z80_|pla_decode_|Equal2~1_combout ), + .datac(\z80_|pla_decode_|Equal1~4_combout ), + .datad(\z80_|execute_|setM1~42_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~46_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~46 .lut_mask = 16'h2A00; +defparam \z80_|execute_|setM1~46 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N6 +cycloneive_lcell_comb \z80_|execute_|setM1~52 ( +// Equation(s): +// \z80_|execute_|setM1~52_combout = (\z80_|execute_|setM1~48_combout & (\z80_|execute_|setM1~46_combout & (\z80_|execute_|setM1~16_combout & \z80_|execute_|setM1~51_combout ))) + + .dataa(\z80_|execute_|setM1~48_combout ), + .datab(\z80_|execute_|setM1~46_combout ), + .datac(\z80_|execute_|setM1~16_combout ), + .datad(\z80_|execute_|setM1~51_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~52_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~52 .lut_mask = 16'h8000; +defparam \z80_|execute_|setM1~52 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N4 +cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_17 ( +// Equation(s): +// \z80_|sequencer_|SYNTHESIZED_WIRE_17~combout = (\z80_|execute_|setM1~54_combout & (\z80_|sequencer_|DFFE_T5_ff~q & !\z80_|execute_|nextM~14_combout )) + + .dataa(\z80_|execute_|setM1~54_combout ), + .datab(gnd), + .datac(\z80_|sequencer_|DFFE_T5_ff~q ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|SYNTHESIZED_WIRE_17~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_17 .lut_mask = 16'h00A0; +defparam \z80_|sequencer_|SYNTHESIZED_WIRE_17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y12_N5 +dffeas \z80_|sequencer_|T6 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|SYNTHESIZED_WIRE_17~combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\z80_|clk_delay_|hold_clk_iorq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|T6~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|T6 .is_wysiwyg = "true"; +defparam \z80_|sequencer_|T6 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y12_N22 +cycloneive_lcell_comb \z80_|execute_|setM1~53 ( +// Equation(s): +// \z80_|execute_|setM1~53_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|execute_|setM1~41_combout ) # ((\z80_|sequencer_|T6~q & !\z80_|execute_|setM1~42_combout )))) # (!\z80_|execute_|setM1~52_combout & (((\z80_|sequencer_|T6~q & +// !\z80_|execute_|setM1~42_combout )))) + + .dataa(\z80_|execute_|setM1~52_combout ), + .datab(\z80_|execute_|setM1~41_combout ), + .datac(\z80_|sequencer_|T6~q ), + .datad(\z80_|execute_|setM1~42_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~53_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~53 .lut_mask = 16'h88F8; +defparam \z80_|execute_|setM1~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y12_N30 +cycloneive_lcell_comb \z80_|execute_|setM1~54 ( +// Equation(s): +// \z80_|execute_|setM1~54_combout = (!\z80_|execute_|setM1~19_combout & (!\z80_|execute_|setM1~35_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|execute_|setM1~53_combout )))) + + .dataa(\z80_|execute_|setM1~19_combout ), + .datab(\z80_|execute_|setM1~35_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|execute_|setM1~53_combout ), + .cin(gnd), + .combout(\z80_|execute_|setM1~54_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|execute_|setM1~54 .lut_mask = 16'h1011; +defparam \z80_|execute_|setM1~54 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y13_N28 +cycloneive_lcell_comb \z80_|sequencer_|DFFE_M1_ff~0 ( +// Equation(s): +// \z80_|sequencer_|DFFE_M1_ff~0_combout = (\z80_|execute_|setM1~54_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # (\z80_|execute_|nextM~14_combout ))) + + .dataa(gnd), + .datab(\z80_|execute_|setM1~54_combout ), + .datac(\z80_|sequencer_|DFFE_M1_ff~q ), + .datad(\z80_|execute_|nextM~14_combout ), + .cin(gnd), + .combout(\z80_|sequencer_|DFFE_M1_ff~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_M1_ff~0 .lut_mask = 16'hCCC0; +defparam \z80_|sequencer_|DFFE_M1_ff~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y13_N29 +dffeas \z80_|sequencer_|DFFE_M1_ff ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|sequencer_|DFFE_M1_ff~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|sequencer_|DFFE_M1_ff~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|sequencer_|DFFE_M1_ff .is_wysiwyg = "true"; +defparam \z80_|sequencer_|DFFE_M1_ff .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X52_Y17_N4 +cycloneive_lcell_comb \z80_|resets_|x1~0 ( +// Equation(s): +// \z80_|resets_|x1~0_combout = !\reset~combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\reset~combout ), + .cin(gnd), + .combout(\z80_|resets_|x1~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|resets_|x1~0 .lut_mask = 16'h00FF; +defparam \z80_|resets_|x1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y16_N16 +cycloneive_lcell_comb \z80_|fpga_reset~feeder ( +// Equation(s): +// \z80_|fpga_reset~feeder_combout = VCC + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\z80_|fpga_reset~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|fpga_reset~feeder .lut_mask = 16'hFFFF; +defparam \z80_|fpga_reset~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X1_Y16_N17 +dffeas \z80_|fpga_reset ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|fpga_reset~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|fpga_reset~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|fpga_reset .is_wysiwyg = "true"; +defparam \z80_|fpga_reset .power_up = "low"; +// synopsys translate_on + +// Location: CLKCTRL_G2 +cycloneive_clkctrl \z80_|fpga_reset~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\z80_|fpga_reset~q }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\z80_|fpga_reset~clkctrl_outclk )); +// synopsys translate_off +defparam \z80_|fpga_reset~clkctrl .clock_type = "global clock"; +defparam \z80_|fpga_reset~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: FF_X52_Y17_N5 +dffeas \z80_|resets_|x1 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|resets_|x1~0_combout ), + .asdata(vcc), + .clrn(\z80_|fpga_reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|resets_|x1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|resets_|x1 .is_wysiwyg = "true"; +defparam \z80_|resets_|x1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X52_Y17_N12 +cycloneive_lcell_comb \z80_|resets_|x3 ( +// Equation(s): +// \z80_|resets_|x3~combout = (\z80_|resets_|x1~q ) # ((!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T2_ff~q )) + + .dataa(gnd), + .datab(\z80_|sequencer_|DFFE_M1_ff~q ), + .datac(\z80_|resets_|x1~q ), + .datad(\z80_|sequencer_|DFFE_T2_ff~q ), + .cin(gnd), + .combout(\z80_|resets_|x3~combout ), + .cout()); +// synopsys translate_off +defparam \z80_|resets_|x3 .lut_mask = 16'hF3F0; +defparam \z80_|resets_|x3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X52_Y17_N13 +dffeas \z80_|resets_|SYNTHESIZED_WIRE_12 ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|resets_|x3~combout ), + .asdata(vcc), + .clrn(\z80_|fpga_reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|resets_|SYNTHESIZED_WIRE_12 .is_wysiwyg = "true"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_12 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N28 +cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_10~0 ( +// Equation(s): +// \z80_|resets_|SYNTHESIZED_WIRE_10~0_combout = !\z80_|resets_|SYNTHESIZED_WIRE_12~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .cin(gnd), + .combout(\z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|resets_|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h00FF; +defparam \z80_|resets_|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y13_N29 +dffeas \z80_|resets_|SYNTHESIZED_WIRE_10 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|resets_|SYNTHESIZED_WIRE_10 .is_wysiwyg = "true"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_10 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N22 +cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_9~feeder ( +// Equation(s): +// \z80_|resets_|SYNTHESIZED_WIRE_9~feeder_combout = \z80_|resets_|SYNTHESIZED_WIRE_10~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), + .cin(gnd), + .combout(\z80_|resets_|SYNTHESIZED_WIRE_9~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|resets_|SYNTHESIZED_WIRE_9~feeder .lut_mask = 16'hFF00; +defparam \z80_|resets_|SYNTHESIZED_WIRE_9~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y13_N23 +dffeas \z80_|resets_|SYNTHESIZED_WIRE_9 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|resets_|SYNTHESIZED_WIRE_9~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|resets_|SYNTHESIZED_WIRE_9 .is_wysiwyg = "true"; +defparam \z80_|resets_|SYNTHESIZED_WIRE_9 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X36_Y13_N19 +dffeas \z80_|resets_|DFFE_intr_ff3 ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(gnd), + .asdata(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|resets_|DFFE_intr_ff3~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|resets_|DFFE_intr_ff3 .is_wysiwyg = "true"; +defparam \z80_|resets_|DFFE_intr_ff3 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N0 +cycloneive_lcell_comb \z80_|resets_|clrpc_int~0 ( +// Equation(s): +// \z80_|resets_|clrpc_int~0_combout = (\z80_|sequencer_|DFFE_M1_ff~q & (((\z80_|resets_|clrpc_int~q )))) # (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|resets_|clrpc_int~q & !\z80_|resets_|x1~q )) # +// (!\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|resets_|clrpc_int~q )))) + + .dataa(\z80_|sequencer_|DFFE_M1_ff~q ), + .datab(\z80_|sequencer_|DFFE_T2_ff~q ), + .datac(\z80_|resets_|clrpc_int~q ), + .datad(\z80_|resets_|x1~q ), + .cin(gnd), + .combout(\z80_|resets_|clrpc_int~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|resets_|clrpc_int~0 .lut_mask = 16'hB0B4; +defparam \z80_|resets_|clrpc_int~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y13_N1 +dffeas \z80_|resets_|clrpc_int ( + .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\z80_|resets_|clrpc_int~0_combout ), + .asdata(vcc), + .clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\z80_|resets_|clrpc_int~q ), + .prn(vcc)); +// synopsys translate_off +defparam \z80_|resets_|clrpc_int .is_wysiwyg = "true"; +defparam \z80_|resets_|clrpc_int .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y13_N18 +cycloneive_lcell_comb \z80_|resets_|clrpc~0 ( +// Equation(s): +// \z80_|resets_|clrpc~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_9~q ) # ((\z80_|resets_|SYNTHESIZED_WIRE_10~q ) # ((\z80_|resets_|DFFE_intr_ff3~q ) # (\z80_|resets_|clrpc_int~q ))) + + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_9~q ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_10~q ), + .datac(\z80_|resets_|DFFE_intr_ff3~q ), + .datad(\z80_|resets_|clrpc_int~q ), + .cin(gnd), + .combout(\z80_|resets_|clrpc~0_combout ), + .cout()); +// synopsys translate_off +defparam \z80_|resets_|clrpc~0 .lut_mask = 16'hFFFE; +defparam \z80_|resets_|clrpc~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N2 +cycloneive_lcell_comb \z80_|address_latch_|abusz[0] ( +// Equation(s): +// \z80_|address_latch_|abusz [0] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[0]~3_combout ) + + .dataa(gnd), + .datab(\z80_|resets_|clrpc~0_combout ), + .datac(gnd), + .datad(\z80_|reg_file_|db_lo_as[0]~3_combout ), + .cin(gnd), + .combout(\z80_|address_latch_|abusz [0]), + .cout()); +// synopsys translate_off +defparam \z80_|address_latch_|abusz[0] .lut_mask = 16'h3300; +defparam \z80_|address_latch_|abusz[0] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y11_N24 cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[0]~0 ( // Equation(s): -// \z80_|address_pins_|DFFE_apin_latch[0]~0_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [0]))) +// \z80_|address_pins_|DFFE_apin_latch[0]~0_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [0])) - .dataa(\z80_|execute_|ctl_apin_mux~2_combout ), - .datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), + .dataa(\z80_|address_latch_|abusz [0]), + .datab(\z80_|execute_|ctl_apin_mux~2_combout ), .datac(gnd), - .datad(\z80_|address_latch_|abusz [0]), + .datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ), .cin(gnd), .combout(\z80_|address_pins_|DFFE_apin_latch[0]~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|address_pins_|DFFE_apin_latch[0]~0 .lut_mask = 16'hDD88; +defparam \z80_|address_pins_|DFFE_apin_latch[0]~0 .lut_mask = 16'hEE22; defparam \z80_|address_pins_|DFFE_apin_latch[0]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y16_N19 +// Location: FF_X34_Y11_N25 dffeas \z80_|address_pins_|DFFE_apin_latch[0] ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|address_pins_|DFFE_apin_latch[0]~0_combout ), @@ -53241,7 +53008,7 @@ dffeas \z80_|address_pins_|DFFE_apin_latch[0] ( .aload(gnd), .sclr(gnd), .sload(\z80_|execute_|ctl_apin_mux2~0_combout ), - .ena(\z80_|pin_control_|bus_ab_pin_we~3_combout ), + .ena(\z80_|pin_control_|bus_ab_pin_we~1_combout ), .devclrn(devclrn), .devpor(devpor), .q(\z80_|address_pins_|DFFE_apin_latch [0]), @@ -53251,228 +53018,228 @@ defparam \z80_|address_pins_|DFFE_apin_latch[0] .is_wysiwyg = "true"; defparam \z80_|address_pins_|DFFE_apin_latch[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y14_N12 -cycloneive_lcell_comb \D[0]~59 ( +// Location: LCCOMB_X23_Y14_N20 +cycloneive_lcell_comb \D[0]~47 ( // Equation(s): -// \D[0]~59_combout = (\Equal2~0_combout & (\D[0]~51_combout )) # (!\Equal2~0_combout & ((\D[0]~106_combout ))) +// \D[0]~47_combout = (\Equal2~0_combout & (\D[0]~44_combout )) # (!\Equal2~0_combout & ((\D[0]~83_combout ))) .dataa(\Equal2~0_combout ), - .datab(\D[0]~51_combout ), - .datac(\D[0]~106_combout ), + .datab(\D[0]~44_combout ), + .datac(\D[0]~83_combout ), .datad(gnd), .cin(gnd), - .combout(\D[0]~59_combout ), + .combout(\D[0]~47_combout ), .cout()); // synopsys translate_off -defparam \D[0]~59 .lut_mask = 16'hD8D8; -defparam \D[0]~59 .sum_lutc_input = "datac"; +defparam \D[0]~47 .lut_mask = 16'hD8D8; +defparam \D[0]~47 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N8 -cycloneive_lcell_comb \D[0]~60 ( +// Location: LCCOMB_X24_Y14_N24 +cycloneive_lcell_comb \D[0]~48 ( // Equation(s): -// \D[0]~60_combout = (\Equal2~1_combout & (\D[0]~59_combout & ((\z80_|data_pins_|dout [0]) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) # (!\Equal2~1_combout & ((\z80_|data_pins_|dout [0]) # ((!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) +// \D[0]~48_combout = (\z80_|data_pins_|dout [0] & (((\D[0]~47_combout ) # (!\Equal2~1_combout )))) # (!\z80_|data_pins_|dout [0] & (!\z80_|pin_control_|bus_db_pin_oe~15_combout & ((\D[0]~47_combout ) # (!\Equal2~1_combout )))) + + .dataa(\z80_|data_pins_|dout [0]), + .datab(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .datac(\Equal2~1_combout ), + .datad(\D[0]~47_combout ), + .cin(gnd), + .combout(\D[0]~48_combout ), + .cout()); +// synopsys translate_off +defparam \D[0]~48 .lut_mask = 16'hBB0B; +defparam \D[0]~48 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N12 +cycloneive_lcell_comb \D[1]~49 ( +// Equation(s): +// \D[1]~49_combout = (\Equal2~0_combout & (\D[1]~30_combout )) # (!\Equal2~0_combout & ((\D[1]~81_combout ))) + + .dataa(\D[1]~30_combout ), + .datab(gnd), + .datac(\Equal2~0_combout ), + .datad(\D[1]~81_combout ), + .cin(gnd), + .combout(\D[1]~49_combout ), + .cout()); +// synopsys translate_off +defparam \D[1]~49 .lut_mask = 16'hAFA0; +defparam \D[1]~49 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N18 +cycloneive_lcell_comb \D[1]~50 ( +// Equation(s): +// \D[1]~50_combout = (\Equal2~1_combout & (\D[1]~49_combout & ((\z80_|data_pins_|dout [1]) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout )))) # (!\Equal2~1_combout & ((\z80_|data_pins_|dout [1]) # ((!\z80_|pin_control_|bus_db_pin_oe~15_combout )))) .dataa(\Equal2~1_combout ), - .datab(\z80_|data_pins_|dout [0]), - .datac(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datad(\D[0]~59_combout ), + .datab(\z80_|data_pins_|dout [1]), + .datac(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .datad(\D[1]~49_combout ), .cin(gnd), - .combout(\D[0]~60_combout ), + .combout(\D[1]~50_combout ), .cout()); // synopsys translate_off -defparam \D[0]~60 .lut_mask = 16'hCF45; -defparam \D[0]~60 .sum_lutc_input = "datac"; +defparam \D[1]~50 .lut_mask = 16'hCF45; +defparam \D[1]~50 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y18_N20 -cycloneive_lcell_comb \D[1]~61 ( +// Location: LCCOMB_X23_Y10_N2 +cycloneive_lcell_comb \D[2]~51 ( // Equation(s): -// \D[1]~61_combout = (\Equal2~0_combout & (\D[1]~32_combout )) # (!\Equal2~0_combout & ((\D[1]~103_combout ))) +// \D[2]~51_combout = (\Equal2~0_combout & (\D[2]~37_combout )) # (!\Equal2~0_combout & ((\D[2]~82_combout ))) - .dataa(\Equal2~0_combout ), + .dataa(\D[2]~37_combout ), .datab(gnd), - .datac(\D[1]~32_combout ), - .datad(\D[1]~103_combout ), + .datac(\Equal2~0_combout ), + .datad(\D[2]~82_combout ), .cin(gnd), - .combout(\D[1]~61_combout ), + .combout(\D[2]~51_combout ), .cout()); // synopsys translate_off -defparam \D[1]~61 .lut_mask = 16'hF5A0; -defparam \D[1]~61 .sum_lutc_input = "datac"; +defparam \D[2]~51 .lut_mask = 16'hAFA0; +defparam \D[2]~51 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y18_N22 -cycloneive_lcell_comb \D[1]~62 ( +// Location: LCCOMB_X24_Y10_N2 +cycloneive_lcell_comb \D[2]~52 ( // Equation(s): -// \D[1]~62_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout & (\z80_|data_pins_|dout [1] & ((\D[1]~61_combout ) # (!\Equal2~1_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout & (((\D[1]~61_combout )) # (!\Equal2~1_combout ))) - - .dataa(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datab(\Equal2~1_combout ), - .datac(\z80_|data_pins_|dout [1]), - .datad(\D[1]~61_combout ), - .cin(gnd), - .combout(\D[1]~62_combout ), - .cout()); -// synopsys translate_off -defparam \D[1]~62 .lut_mask = 16'hF531; -defparam \D[1]~62 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N12 -cycloneive_lcell_comb \D[2]~63 ( -// Equation(s): -// \D[2]~63_combout = (\Equal2~0_combout & (\D[2]~104_combout )) # (!\Equal2~0_combout & ((\D[2]~105_combout ))) - - .dataa(\Equal2~0_combout ), - .datab(gnd), - .datac(\D[2]~104_combout ), - .datad(\D[2]~105_combout ), - .cin(gnd), - .combout(\D[2]~63_combout ), - .cout()); -// synopsys translate_off -defparam \D[2]~63 .lut_mask = 16'hF5A0; -defparam \D[2]~63 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N26 -cycloneive_lcell_comb \D[2]~64 ( -// Equation(s): -// \D[2]~64_combout = (\z80_|data_pins_|dout [2] & (((\D[2]~63_combout )) # (!\Equal2~1_combout ))) # (!\z80_|data_pins_|dout [2] & (!\z80_|pin_control_|bus_db_pin_oe~14_combout & ((\D[2]~63_combout ) # (!\Equal2~1_combout )))) +// \D[2]~52_combout = (\z80_|data_pins_|dout [2] & (((\D[2]~51_combout )) # (!\Equal2~1_combout ))) # (!\z80_|data_pins_|dout [2] & (!\z80_|pin_control_|bus_db_pin_oe~15_combout & ((\D[2]~51_combout ) # (!\Equal2~1_combout )))) .dataa(\z80_|data_pins_|dout [2]), .datab(\Equal2~1_combout ), - .datac(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datad(\D[2]~63_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .datad(\D[2]~51_combout ), .cin(gnd), - .combout(\D[2]~64_combout ), + .combout(\D[2]~52_combout ), .cout()); // synopsys translate_off -defparam \D[2]~64 .lut_mask = 16'hAF23; -defparam \D[2]~64 .sum_lutc_input = "datac"; +defparam \D[2]~52 .lut_mask = 16'hAF23; +defparam \D[2]~52 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y15_N2 -cycloneive_lcell_comb \D[3]~75 ( +// Location: LCCOMB_X23_Y14_N18 +cycloneive_lcell_comb \D[3]~58 ( // Equation(s): -// \D[3]~75_combout = (\Equal2~0_combout & (\D[3]~69_combout )) # (!\Equal2~0_combout & ((\D[3]~108_combout ))) - - .dataa(\D[3]~69_combout ), - .datab(gnd), - .datac(\Equal2~0_combout ), - .datad(\D[3]~108_combout ), - .cin(gnd), - .combout(\D[3]~75_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~75 .lut_mask = 16'hAFA0; -defparam \D[3]~75 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X24_Y15_N20 -cycloneive_lcell_comb \D[3]~76 ( -// Equation(s): -// \D[3]~76_combout = (\z80_|data_pins_|dout [3] & (((\D[3]~75_combout )) # (!\Equal2~1_combout ))) # (!\z80_|data_pins_|dout [3] & (!\z80_|pin_control_|bus_db_pin_oe~14_combout & ((\D[3]~75_combout ) # (!\Equal2~1_combout )))) - - .dataa(\z80_|data_pins_|dout [3]), - .datab(\Equal2~1_combout ), - .datac(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datad(\D[3]~75_combout ), - .cin(gnd), - .combout(\D[3]~76_combout ), - .cout()); -// synopsys translate_off -defparam \D[3]~76 .lut_mask = 16'hAF23; -defparam \D[3]~76 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X29_Y14_N24 -cycloneive_lcell_comb \D[4]~82 ( -// Equation(s): -// \D[4]~82_combout = (\Equal2~0_combout & (\D[4]~81_combout )) # (!\Equal2~0_combout & ((\D[4]~109_combout ))) +// \D[3]~58_combout = (\Equal2~0_combout & (\D[3]~57_combout )) # (!\Equal2~0_combout & ((\D[3]~85_combout ))) .dataa(\Equal2~0_combout ), - .datab(\D[4]~81_combout ), + .datab(\D[3]~57_combout ), .datac(gnd), - .datad(\D[4]~109_combout ), + .datad(\D[3]~85_combout ), .cin(gnd), - .combout(\D[4]~82_combout ), + .combout(\D[3]~58_combout ), .cout()); // synopsys translate_off -defparam \D[4]~82 .lut_mask = 16'hDD88; -defparam \D[4]~82 .sum_lutc_input = "datac"; +defparam \D[3]~58 .lut_mask = 16'hDD88; +defparam \D[3]~58 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N26 -cycloneive_lcell_comb \D[4]~83 ( +// Location: LCCOMB_X24_Y14_N18 +cycloneive_lcell_comb \D[3]~59 ( // Equation(s): -// \D[4]~83_combout = (\Equal2~1_combout & (\D[4]~82_combout & ((\z80_|data_pins_|dout [4]) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) # (!\Equal2~1_combout & ((\z80_|data_pins_|dout [4]) # ((!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) +// \D[3]~59_combout = (\z80_|data_pins_|dout [3] & (((\D[3]~58_combout ) # (!\Equal2~1_combout )))) # (!\z80_|data_pins_|dout [3] & (!\z80_|pin_control_|bus_db_pin_oe~15_combout & ((\D[3]~58_combout ) # (!\Equal2~1_combout )))) + + .dataa(\z80_|data_pins_|dout [3]), + .datab(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .datac(\Equal2~1_combout ), + .datad(\D[3]~58_combout ), + .cin(gnd), + .combout(\D[3]~59_combout ), + .cout()); +// synopsys translate_off +defparam \D[3]~59 .lut_mask = 16'hBB0B; +defparam \D[3]~59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N0 +cycloneive_lcell_comb \D[4]~65 ( +// Equation(s): +// \D[4]~65_combout = (\Equal2~0_combout & (\D[4]~64_combout )) # (!\Equal2~0_combout & ((\D[4]~86_combout ))) + + .dataa(gnd), + .datab(\D[4]~64_combout ), + .datac(\Equal2~0_combout ), + .datad(\D[4]~86_combout ), + .cin(gnd), + .combout(\D[4]~65_combout ), + .cout()); +// synopsys translate_off +defparam \D[4]~65 .lut_mask = 16'hCFC0; +defparam \D[4]~65 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y10_N22 +cycloneive_lcell_comb \D[4]~66 ( +// Equation(s): +// \D[4]~66_combout = (\Equal2~1_combout & (\D[4]~65_combout & ((\z80_|data_pins_|dout [4]) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout )))) # (!\Equal2~1_combout & ((\z80_|data_pins_|dout [4]) # ((!\z80_|pin_control_|bus_db_pin_oe~15_combout )))) .dataa(\Equal2~1_combout ), .datab(\z80_|data_pins_|dout [4]), - .datac(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datad(\D[4]~82_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .datad(\D[4]~65_combout ), .cin(gnd), - .combout(\D[4]~83_combout ), + .combout(\D[4]~66_combout ), .cout()); // synopsys translate_off -defparam \D[4]~83 .lut_mask = 16'hCF45; -defparam \D[4]~83 .sum_lutc_input = "datac"; +defparam \D[4]~66 .lut_mask = 16'hCF45; +defparam \D[4]~66 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N24 -cycloneive_lcell_comb \D[6]~92 ( +// Location: LCCOMB_X24_Y10_N20 +cycloneive_lcell_comb \D[6]~70 ( // Equation(s): -// \D[6]~92_combout = (\Equal2~0_combout & ((\D[6]~86_combout ))) # (!\Equal2~0_combout & (\D[6]~111_combout )) +// \D[6]~70_combout = (\Equal2~0_combout & ((\D[6]~69_combout ))) # (!\Equal2~0_combout & (\D[6]~88_combout )) - .dataa(gnd), - .datab(\Equal2~0_combout ), - .datac(\D[6]~111_combout ), - .datad(\D[6]~86_combout ), + .dataa(\Equal2~0_combout ), + .datab(gnd), + .datac(\D[6]~88_combout ), + .datad(\D[6]~69_combout ), .cin(gnd), - .combout(\D[6]~92_combout ), + .combout(\D[6]~70_combout ), .cout()); // synopsys translate_off -defparam \D[6]~92 .lut_mask = 16'hFC30; -defparam \D[6]~92 .sum_lutc_input = "datac"; +defparam \D[6]~70 .lut_mask = 16'hFA50; +defparam \D[6]~70 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X30_Y14_N10 -cycloneive_lcell_comb \D[6]~93 ( +// Location: LCCOMB_X24_Y10_N10 +cycloneive_lcell_comb \D[6]~71 ( // Equation(s): -// \D[6]~93_combout = (\Equal2~1_combout & (\D[6]~92_combout & ((\z80_|data_pins_|dout [6]) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) # (!\Equal2~1_combout & ((\z80_|data_pins_|dout [6]) # ((!\z80_|pin_control_|bus_db_pin_oe~14_combout )))) +// \D[6]~71_combout = (\z80_|data_pins_|dout [6] & (((\D[6]~70_combout )) # (!\Equal2~1_combout ))) # (!\z80_|data_pins_|dout [6] & (!\z80_|pin_control_|bus_db_pin_oe~15_combout & ((\D[6]~70_combout ) # (!\Equal2~1_combout )))) - .dataa(\Equal2~1_combout ), - .datab(\z80_|data_pins_|dout [6]), - .datac(\z80_|pin_control_|bus_db_pin_oe~14_combout ), - .datad(\D[6]~92_combout ), + .dataa(\z80_|data_pins_|dout [6]), + .datab(\Equal2~1_combout ), + .datac(\z80_|pin_control_|bus_db_pin_oe~15_combout ), + .datad(\D[6]~70_combout ), .cin(gnd), - .combout(\D[6]~93_combout ), + .combout(\D[6]~71_combout ), .cout()); // synopsys translate_off -defparam \D[6]~93 .lut_mask = 16'hCF45; -defparam \D[6]~93 .sum_lutc_input = "datac"; +defparam \D[6]~71 .lut_mask = 16'hAF23; +defparam \D[6]~71 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X43_Y17_N0 +// Location: LCCOMB_X27_Y13_N28 cycloneive_lcell_comb \z80_|nM1_int~3 ( // Equation(s): -// \z80_|nM1_int~3_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # (\z80_|sequencer_|DFFE_M1_ff~q ))) +// \z80_|nM1_int~3_combout = (\z80_|execute_|setM1~54_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # (\z80_|sequencer_|DFFE_M1_ff~q ))) - .dataa(gnd), - .datab(\z80_|sequencer_|DFFE_T1_ff~q ), - .datac(\z80_|sequencer_|DFFE_M1_ff~q ), - .datad(\z80_|execute_|setM1~52_combout ), + .dataa(\z80_|sequencer_|DFFE_T1_ff~q ), + .datab(\z80_|execute_|setM1~54_combout ), + .datac(gnd), + .datad(\z80_|sequencer_|DFFE_M1_ff~q ), .cin(gnd), .combout(\z80_|nM1_int~3_combout ), .cout()); // synopsys translate_off -defparam \z80_|nM1_int~3 .lut_mask = 16'hFC00; +defparam \z80_|nM1_int~3 .lut_mask = 16'hCC88; defparam \z80_|nM1_int~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X43_Y17_N1 +// Location: FF_X27_Y13_N29 dffeas \z80_|memory_ifc_|SYNTHESIZED_WIRE_16 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|nM1_int~3_combout ), @@ -53491,7 +53258,7 @@ defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_16 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_16 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X43_Y17_N30 +// Location: LCCOMB_X27_Y11_N4 cycloneive_lcell_comb \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder ( // Equation(s): // \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder_combout = \z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q @@ -53508,7 +53275,7 @@ defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder .lut_mask = 16'hFF00; defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X43_Y17_N31 +// Location: FF_X27_Y11_N5 dffeas \z80_|memory_ifc_|SYNTHESIZED_WIRE_17 ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder_combout ), @@ -53527,7 +53294,7 @@ defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_17 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_17 .power_up = "low"; // synopsys translate_on -// Location: FF_X43_Y17_N25 +// Location: FF_X27_Y11_N11 dffeas \z80_|memory_ifc_|DFFE_mreq_ff2 ( .clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), @@ -53546,32 +53313,32 @@ defparam \z80_|memory_ifc_|DFFE_mreq_ff2 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|DFFE_mreq_ff2 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X43_Y17_N24 +// Location: LCCOMB_X27_Y11_N10 cycloneive_lcell_comb \z80_|memory_ifc_|nMREQ_out~0 ( // Equation(s): // \z80_|memory_ifc_|nMREQ_out~0_combout = (\z80_|memory_ifc_|wait_mwr~q ) # ((\z80_|memory_ifc_|mwr_wr~q ) # ((\z80_|memory_ifc_|SYNTHESIZED_WIRE_17~q & !\z80_|memory_ifc_|DFFE_mreq_ff2~q ))) - .dataa(\z80_|memory_ifc_|SYNTHESIZED_WIRE_17~q ), - .datab(\z80_|memory_ifc_|wait_mwr~q ), + .dataa(\z80_|memory_ifc_|wait_mwr~q ), + .datab(\z80_|memory_ifc_|SYNTHESIZED_WIRE_17~q ), .datac(\z80_|memory_ifc_|DFFE_mreq_ff2~q ), .datad(\z80_|memory_ifc_|mwr_wr~q ), .cin(gnd), .combout(\z80_|memory_ifc_|nMREQ_out~0_combout ), .cout()); // synopsys translate_off -defparam \z80_|memory_ifc_|nMREQ_out~0 .lut_mask = 16'hFFCE; +defparam \z80_|memory_ifc_|nMREQ_out~0 .lut_mask = 16'hFFAE; defparam \z80_|memory_ifc_|nMREQ_out~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X43_Y17_N2 +// Location: LCCOMB_X27_Y11_N16 cycloneive_lcell_comb \z80_|memory_ifc_|nMREQ_out~1 ( // Equation(s): -// \z80_|memory_ifc_|nMREQ_out~1_combout = (!\z80_|memory_ifc_|wait_mrd~q & (!\z80_|memory_ifc_|nMREQ_out~0_combout & (!\z80_|memory_ifc_|DFFE_mrd_ff3~q & !\z80_|memory_ifc_|nRD_out~0_combout ))) +// \z80_|memory_ifc_|nMREQ_out~1_combout = (!\z80_|memory_ifc_|wait_mrd~q & (!\z80_|memory_ifc_|nRD_out~0_combout & (!\z80_|memory_ifc_|DFFE_mrd_ff3~q & !\z80_|memory_ifc_|nMREQ_out~0_combout ))) .dataa(\z80_|memory_ifc_|wait_mrd~q ), - .datab(\z80_|memory_ifc_|nMREQ_out~0_combout ), + .datab(\z80_|memory_ifc_|nRD_out~0_combout ), .datac(\z80_|memory_ifc_|DFFE_mrd_ff3~q ), - .datad(\z80_|memory_ifc_|nRD_out~0_combout ), + .datad(\z80_|memory_ifc_|nMREQ_out~0_combout ), .cin(gnd), .combout(\z80_|memory_ifc_|nMREQ_out~1_combout ), .cout()); @@ -53593,7 +53360,7 @@ defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl .cl defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N0 +// Location: LCCOMB_X3_Y23_N28 cycloneive_lcell_comb \ula_|i2c_loader_|state.Idle~feeder ( // Equation(s): // \ula_|i2c_loader_|state.Idle~feeder_combout = VCC @@ -53610,7 +53377,7 @@ defparam \ula_|i2c_loader_|state.Idle~feeder .lut_mask = 16'hFFFF; defparam \ula_|i2c_loader_|state.Idle~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X4_Y24_N0 +// Location: LCCOMB_X1_Y24_N22 cycloneive_lcell_comb \ula_|i2c_loader_|divider[0]~15 ( // Equation(s): // \ula_|i2c_loader_|divider[0]~15_combout = !\ula_|i2c_loader_|divider [0] @@ -53627,7 +53394,7 @@ defparam \ula_|i2c_loader_|divider[0]~15 .lut_mask = 16'h0F0F; defparam \ula_|i2c_loader_|divider[0]~15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X4_Y24_N1 +// Location: FF_X1_Y24_N23 dffeas \ula_|i2c_loader_|divider[0] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[0]~15_combout ), @@ -53646,14 +53413,14 @@ defparam \ula_|i2c_loader_|divider[0] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X4_Y24_N10 +// Location: LCCOMB_X1_Y24_N0 cycloneive_lcell_comb \ula_|i2c_loader_|divider[1]~5 ( // Equation(s): -// \ula_|i2c_loader_|divider[1]~5_combout = (\ula_|i2c_loader_|divider [1] & (\ula_|i2c_loader_|divider [0] $ (VCC))) # (!\ula_|i2c_loader_|divider [1] & (\ula_|i2c_loader_|divider [0] & VCC)) -// \ula_|i2c_loader_|divider[1]~6 = CARRY((\ula_|i2c_loader_|divider [1] & \ula_|i2c_loader_|divider [0])) +// \ula_|i2c_loader_|divider[1]~5_combout = (\ula_|i2c_loader_|divider [0] & (\ula_|i2c_loader_|divider [1] $ (VCC))) # (!\ula_|i2c_loader_|divider [0] & (\ula_|i2c_loader_|divider [1] & VCC)) +// \ula_|i2c_loader_|divider[1]~6 = CARRY((\ula_|i2c_loader_|divider [0] & \ula_|i2c_loader_|divider [1])) - .dataa(\ula_|i2c_loader_|divider [1]), - .datab(\ula_|i2c_loader_|divider [0]), + .dataa(\ula_|i2c_loader_|divider [0]), + .datab(\ula_|i2c_loader_|divider [1]), .datac(gnd), .datad(vcc), .cin(gnd), @@ -53664,7 +53431,7 @@ defparam \ula_|i2c_loader_|divider[1]~5 .lut_mask = 16'h6688; defparam \ula_|i2c_loader_|divider[1]~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X4_Y24_N11 +// Location: FF_X1_Y24_N1 dffeas \ula_|i2c_loader_|divider[1] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[1]~5_combout ), @@ -53683,25 +53450,25 @@ defparam \ula_|i2c_loader_|divider[1] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X4_Y24_N12 +// Location: LCCOMB_X1_Y24_N2 cycloneive_lcell_comb \ula_|i2c_loader_|divider[2]~7 ( // Equation(s): // \ula_|i2c_loader_|divider[2]~7_combout = (\ula_|i2c_loader_|divider [2] & (!\ula_|i2c_loader_|divider[1]~6 )) # (!\ula_|i2c_loader_|divider [2] & ((\ula_|i2c_loader_|divider[1]~6 ) # (GND))) // \ula_|i2c_loader_|divider[2]~8 = CARRY((!\ula_|i2c_loader_|divider[1]~6 ) # (!\ula_|i2c_loader_|divider [2])) - .dataa(\ula_|i2c_loader_|divider [2]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|i2c_loader_|divider [2]), .datac(gnd), .datad(vcc), .cin(\ula_|i2c_loader_|divider[1]~6 ), .combout(\ula_|i2c_loader_|divider[2]~7_combout ), .cout(\ula_|i2c_loader_|divider[2]~8 )); // synopsys translate_off -defparam \ula_|i2c_loader_|divider[2]~7 .lut_mask = 16'h5A5F; +defparam \ula_|i2c_loader_|divider[2]~7 .lut_mask = 16'h3C3F; defparam \ula_|i2c_loader_|divider[2]~7 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X4_Y24_N13 +// Location: FF_X1_Y24_N3 dffeas \ula_|i2c_loader_|divider[2] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[2]~7_combout ), @@ -53720,7 +53487,7 @@ defparam \ula_|i2c_loader_|divider[2] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X4_Y24_N14 +// Location: LCCOMB_X1_Y24_N4 cycloneive_lcell_comb \ula_|i2c_loader_|divider[3]~9 ( // Equation(s): // \ula_|i2c_loader_|divider[3]~9_combout = (\ula_|i2c_loader_|divider [3] & (\ula_|i2c_loader_|divider[2]~8 $ (GND))) # (!\ula_|i2c_loader_|divider [3] & (!\ula_|i2c_loader_|divider[2]~8 & VCC)) @@ -53738,7 +53505,7 @@ defparam \ula_|i2c_loader_|divider[3]~9 .lut_mask = 16'hC30C; defparam \ula_|i2c_loader_|divider[3]~9 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X4_Y24_N15 +// Location: FF_X1_Y24_N5 dffeas \ula_|i2c_loader_|divider[3] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[3]~9_combout ), @@ -53757,25 +53524,42 @@ defparam \ula_|i2c_loader_|divider[3] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X4_Y24_N16 +// Location: LCCOMB_X1_Y24_N12 +cycloneive_lcell_comb \ula_|i2c_loader_|WideAnd0~0 ( +// Equation(s): +// \ula_|i2c_loader_|WideAnd0~0_combout = (((!\ula_|i2c_loader_|divider [2]) # (!\ula_|i2c_loader_|divider [3])) # (!\ula_|i2c_loader_|divider [1])) # (!\ula_|i2c_loader_|divider [0]) + + .dataa(\ula_|i2c_loader_|divider [0]), + .datab(\ula_|i2c_loader_|divider [1]), + .datac(\ula_|i2c_loader_|divider [3]), + .datad(\ula_|i2c_loader_|divider [2]), + .cin(gnd), + .combout(\ula_|i2c_loader_|WideAnd0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|WideAnd0~0 .lut_mask = 16'h7FFF; +defparam \ula_|i2c_loader_|WideAnd0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y24_N6 cycloneive_lcell_comb \ula_|i2c_loader_|divider[4]~11 ( // Equation(s): // \ula_|i2c_loader_|divider[4]~11_combout = (\ula_|i2c_loader_|divider [4] & (!\ula_|i2c_loader_|divider[3]~10 )) # (!\ula_|i2c_loader_|divider [4] & ((\ula_|i2c_loader_|divider[3]~10 ) # (GND))) // \ula_|i2c_loader_|divider[4]~12 = CARRY((!\ula_|i2c_loader_|divider[3]~10 ) # (!\ula_|i2c_loader_|divider [4])) - .dataa(gnd), - .datab(\ula_|i2c_loader_|divider [4]), + .dataa(\ula_|i2c_loader_|divider [4]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\ula_|i2c_loader_|divider[3]~10 ), .combout(\ula_|i2c_loader_|divider[4]~11_combout ), .cout(\ula_|i2c_loader_|divider[4]~12 )); // synopsys translate_off -defparam \ula_|i2c_loader_|divider[4]~11 .lut_mask = 16'h3C3F; +defparam \ula_|i2c_loader_|divider[4]~11 .lut_mask = 16'h5A5F; defparam \ula_|i2c_loader_|divider[4]~11 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X4_Y24_N17 +// Location: FF_X1_Y24_N7 dffeas \ula_|i2c_loader_|divider[4] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[4]~11_combout ), @@ -53794,24 +53578,24 @@ defparam \ula_|i2c_loader_|divider[4] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X4_Y24_N18 +// Location: LCCOMB_X1_Y24_N8 cycloneive_lcell_comb \ula_|i2c_loader_|divider[5]~13 ( // Equation(s): -// \ula_|i2c_loader_|divider[5]~13_combout = \ula_|i2c_loader_|divider[4]~12 $ (!\ula_|i2c_loader_|divider [5]) +// \ula_|i2c_loader_|divider[5]~13_combout = \ula_|i2c_loader_|divider [5] $ (!\ula_|i2c_loader_|divider[4]~12 ) .dataa(gnd), - .datab(gnd), + .datab(\ula_|i2c_loader_|divider [5]), .datac(gnd), - .datad(\ula_|i2c_loader_|divider [5]), + .datad(gnd), .cin(\ula_|i2c_loader_|divider[4]~12 ), .combout(\ula_|i2c_loader_|divider[5]~13_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|divider[5]~13 .lut_mask = 16'hF00F; +defparam \ula_|i2c_loader_|divider[5]~13 .lut_mask = 16'hC3C3; defparam \ula_|i2c_loader_|divider[5]~13 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X4_Y24_N19 +// Location: FF_X1_Y24_N9 dffeas \ula_|i2c_loader_|divider[5] ( .clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|divider[5]~13_combout ), @@ -53830,41 +53614,24 @@ defparam \ula_|i2c_loader_|divider[5] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|divider[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X4_Y24_N22 -cycloneive_lcell_comb \ula_|i2c_loader_|WideAnd0~0 ( -// Equation(s): -// \ula_|i2c_loader_|WideAnd0~0_combout = (((!\ula_|i2c_loader_|divider [2]) # (!\ula_|i2c_loader_|divider [3])) # (!\ula_|i2c_loader_|divider [0])) # (!\ula_|i2c_loader_|divider [1]) - - .dataa(\ula_|i2c_loader_|divider [1]), - .datab(\ula_|i2c_loader_|divider [0]), - .datac(\ula_|i2c_loader_|divider [3]), - .datad(\ula_|i2c_loader_|divider [2]), - .cin(gnd), - .combout(\ula_|i2c_loader_|WideAnd0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|WideAnd0~0 .lut_mask = 16'h7FFF; -defparam \ula_|i2c_loader_|WideAnd0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y24_N8 +// Location: LCCOMB_X1_Y24_N30 cycloneive_lcell_comb \ula_|i2c_loader_|WideAnd0 ( // Equation(s): -// \ula_|i2c_loader_|WideAnd0~combout = ((\ula_|i2c_loader_|WideAnd0~0_combout ) # (!\ula_|i2c_loader_|divider [4])) # (!\ula_|i2c_loader_|divider [5]) +// \ula_|i2c_loader_|WideAnd0~combout = (\ula_|i2c_loader_|WideAnd0~0_combout ) # ((!\ula_|i2c_loader_|divider [4]) # (!\ula_|i2c_loader_|divider [5])) - .dataa(gnd), - .datab(\ula_|i2c_loader_|divider [5]), - .datac(\ula_|i2c_loader_|WideAnd0~0_combout ), + .dataa(\ula_|i2c_loader_|WideAnd0~0_combout ), + .datab(gnd), + .datac(\ula_|i2c_loader_|divider [5]), .datad(\ula_|i2c_loader_|divider [4]), .cin(gnd), .combout(\ula_|i2c_loader_|WideAnd0~combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|WideAnd0 .lut_mask = 16'hF3FF; +defparam \ula_|i2c_loader_|WideAnd0 .lut_mask = 16'hAFFF; defparam \ula_|i2c_loader_|WideAnd0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X1_Y23_N1 +// Location: FF_X3_Y23_N29 dffeas \ula_|i2c_loader_|state.Idle ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|state.Idle~feeder_combout ), @@ -53883,7 +53650,7 @@ defparam \ula_|i2c_loader_|state.Idle .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|state.Idle .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N4 +// Location: LCCOMB_X3_Y23_N0 cycloneive_lcell_comb \ula_|i2c_loader_|phase~0 ( // Equation(s): // \ula_|i2c_loader_|phase~0_combout = (!\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|state.Idle~q ) @@ -53900,7 +53667,7 @@ defparam \ula_|i2c_loader_|phase~0 .lut_mask = 16'h0F00; defparam \ula_|i2c_loader_|phase~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X1_Y23_N5 +// Location: FF_X3_Y23_N1 dffeas \ula_|i2c_loader_|phase[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|phase~0_combout ), @@ -53919,7 +53686,7 @@ defparam \ula_|i2c_loader_|phase[0] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|phase[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N14 +// Location: LCCOMB_X3_Y23_N2 cycloneive_lcell_comb \ula_|i2c_loader_|phase~1 ( // Equation(s): // \ula_|i2c_loader_|phase~1_combout = (\ula_|i2c_loader_|state.Idle~q & (\ula_|i2c_loader_|phase [0] $ (\ula_|i2c_loader_|phase [1]))) @@ -53936,7 +53703,7 @@ defparam \ula_|i2c_loader_|phase~1 .lut_mask = 16'h3C00; defparam \ula_|i2c_loader_|phase~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X1_Y23_N15 +// Location: FF_X3_Y23_N3 dffeas \ula_|i2c_loader_|phase[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|phase~1_combout ), @@ -53955,59 +53722,182 @@ defparam \ula_|i2c_loader_|phase[1] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|phase[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y24_N2 +// Location: LCCOMB_X2_Y24_N2 cycloneive_lcell_comb \ula_|i2c_loader_|nbit~5 ( // Equation(s): -// \ula_|i2c_loader_|nbit~5_combout = (!\ula_|i2c_loader_|nbit [0]) # (!\ula_|i2c_loader_|state.Data~q ) +// \ula_|i2c_loader_|nbit~5_combout = (!\ula_|i2c_loader_|state.Data~q ) # (!\ula_|i2c_loader_|nbit [0]) - .dataa(\ula_|i2c_loader_|state.Data~q ), + .dataa(gnd), .datab(gnd), .datac(\ula_|i2c_loader_|nbit [0]), - .datad(gnd), + .datad(\ula_|i2c_loader_|state.Data~q ), .cin(gnd), .combout(\ula_|i2c_loader_|nbit~5_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|nbit~5 .lut_mask = 16'h5F5F; +defparam \ula_|i2c_loader_|nbit~5 .lut_mask = 16'h0FFF; defparam \ula_|i2c_loader_|nbit~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N14 -cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[0]~8 ( +// Location: LCCOMB_X2_Y23_N16 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Idle~0 ( // Equation(s): -// \ula_|i2c_loader_|thisbyte[0]~8_combout = \ula_|i2c_loader_|thisbyte [0] $ (VCC) -// \ula_|i2c_loader_|thisbyte[0]~9 = CARRY(\ula_|i2c_loader_|thisbyte [0]) +// \ula_|i2c_loader_|state.Idle~0_combout = (!\ula_|i2c_loader_|state.Stop~q & (!\ula_|i2c_loader_|state.Ack~q & (!\ula_|i2c_loader_|state.Start~q & !\ula_|i2c_loader_|state.Pause~q ))) - .dataa(gnd), - .datab(\ula_|i2c_loader_|thisbyte [0]), - .datac(gnd), - .datad(vcc), + .dataa(\ula_|i2c_loader_|state.Stop~q ), + .datab(\ula_|i2c_loader_|state.Ack~q ), + .datac(\ula_|i2c_loader_|state.Start~q ), + .datad(\ula_|i2c_loader_|state.Pause~q ), .cin(gnd), - .combout(\ula_|i2c_loader_|thisbyte[0]~8_combout ), - .cout(\ula_|i2c_loader_|thisbyte[0]~9 )); + .combout(\ula_|i2c_loader_|state.Idle~0_combout ), + .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[0]~8 .lut_mask = 16'h33CC; -defparam \ula_|i2c_loader_|thisbyte[0]~8 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|state.Idle~0 .lut_mask = 16'h0001; +defparam \ula_|i2c_loader_|state.Idle~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N8 +// Location: LCCOMB_X1_Y23_N30 cycloneive_lcell_comb \ula_|i2c_loader_|Mux42~0 ( // Equation(s): -// \ula_|i2c_loader_|Mux42~0_combout = (\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|phase [1]) +// \ula_|i2c_loader_|Mux42~0_combout = (\ula_|i2c_loader_|phase [1] & \ula_|i2c_loader_|phase [0]) .dataa(gnd), - .datab(gnd), + .datab(\ula_|i2c_loader_|phase [1]), .datac(\ula_|i2c_loader_|phase [0]), - .datad(\ula_|i2c_loader_|phase [1]), + .datad(gnd), .cin(gnd), .combout(\ula_|i2c_loader_|Mux42~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|Mux42~0 .lut_mask = 16'hF000; +defparam \ula_|i2c_loader_|Mux42~0 .lut_mask = 16'hC0C0; defparam \ula_|i2c_loader_|Mux42~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N28 +// Location: LCCOMB_X2_Y24_N0 +cycloneive_lcell_comb \ula_|i2c_loader_|nbit~6 ( +// Equation(s): +// \ula_|i2c_loader_|nbit~6_combout = (\ula_|i2c_loader_|nbit [1] $ (!\ula_|i2c_loader_|nbit [0])) # (!\ula_|i2c_loader_|state.Data~q ) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|state.Data~q ), + .datac(\ula_|i2c_loader_|nbit [1]), + .datad(\ula_|i2c_loader_|nbit [0]), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbit~6_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit~6 .lut_mask = 16'hF33F; +defparam \ula_|i2c_loader_|nbit~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y24_N1 +dffeas \ula_|i2c_loader_|nbit[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|nbit~6_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2c_loader_|nbit[0]~4_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|nbit [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit[1] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|nbit[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y24_N30 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Done~0 ( +// Equation(s): +// \ula_|i2c_loader_|state.Done~0_combout = (!\ula_|i2c_loader_|nbit [2] & (!\ula_|i2c_loader_|nbit [0] & (\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|nbit [1]))) + + .dataa(\ula_|i2c_loader_|nbit [2]), + .datab(\ula_|i2c_loader_|nbit [0]), + .datac(\ula_|i2c_loader_|state.Data~q ), + .datad(\ula_|i2c_loader_|nbit [1]), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Done~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Done~0 .lut_mask = 16'h0010; +defparam \ula_|i2c_loader_|state.Done~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N18 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Ack~0 ( +// Equation(s): +// \ula_|i2c_loader_|state.Ack~0_combout = ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Done~0_combout ) # (!\ula_|i2c_loader_|state.Idle~0_combout )))) # (!\ula_|i2c_loader_|state.Idle~q ) + + .dataa(\ula_|i2c_loader_|state.Idle~0_combout ), + .datab(\ula_|i2c_loader_|Mux42~0_combout ), + .datac(\ula_|i2c_loader_|state.Done~0_combout ), + .datad(\ula_|i2c_loader_|state.Idle~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Ack~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Ack~0 .lut_mask = 16'hC4FF; +defparam \ula_|i2c_loader_|state.Ack~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N24 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Ack~1 ( +// Equation(s): +// \ula_|i2c_loader_|state.Ack~1_combout = (\ula_|i2c_loader_|WideAnd0~combout & (((\ula_|i2c_loader_|state.Ack~q )))) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|state.Ack~0_combout & (\ula_|i2c_loader_|state.Data~q )) # +// (!\ula_|i2c_loader_|state.Ack~0_combout & ((\ula_|i2c_loader_|state.Ack~q ))))) + + .dataa(\ula_|i2c_loader_|WideAnd0~combout ), + .datab(\ula_|i2c_loader_|state.Data~q ), + .datac(\ula_|i2c_loader_|state.Ack~q ), + .datad(\ula_|i2c_loader_|state.Ack~0_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Ack~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Ack~1 .lut_mask = 16'hE4F0; +defparam \ula_|i2c_loader_|state.Ack~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y23_N25 +dffeas \ula_|i2c_loader_|state.Ack ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|state.Ack~1_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|state.Ack~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Ack .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|state.Ack .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N2 +cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~2 ( +// Equation(s): +// \ula_|i2c_loader_|nbit[0]~2_combout = (\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|phase [0])) # (!\ula_|i2c_loader_|phase [1]))) # (!\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|state.Ack~q )))) + + .dataa(\ula_|i2c_loader_|phase [1]), + .datab(\ula_|i2c_loader_|state.Ack~q ), + .datac(\ula_|i2c_loader_|phase [0]), + .datad(\ula_|i2c_loader_|state.Data~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbit[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbit[0]~2 .lut_mask = 16'h5F33; +defparam \ula_|i2c_loader_|nbit[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N26 cycloneive_lcell_comb \ula_|i2c_loader_|nbyte~4 ( // Equation(s): // \ula_|i2c_loader_|nbyte~4_combout = (\ula_|i2c_loader_|state.Start~q ) # ((\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|nbyte [0] $ (!\ula_|i2c_loader_|nbyte [1])))) @@ -54024,14 +53914,14 @@ defparam \ula_|i2c_loader_|nbyte~4 .lut_mask = 16'hFF84; defparam \ula_|i2c_loader_|nbyte~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N26 +// Location: LCCOMB_X1_Y23_N4 cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[0]~7 ( // Equation(s): -// \ula_|i2c_loader_|thisbyte[0]~7_combout = (\ula_|i2c_loader_|phase [1] & \ula_|i2c_loader_|state.Ack~q ) +// \ula_|i2c_loader_|thisbyte[0]~7_combout = (\ula_|i2c_loader_|state.Ack~q & \ula_|i2c_loader_|phase [1]) .dataa(gnd), - .datab(\ula_|i2c_loader_|phase [1]), - .datac(\ula_|i2c_loader_|state.Ack~q ), + .datab(\ula_|i2c_loader_|state.Ack~q ), + .datac(\ula_|i2c_loader_|phase [1]), .datad(gnd), .cin(gnd), .combout(\ula_|i2c_loader_|thisbyte[0]~7_combout ), @@ -54051,13 +53941,13 @@ defparam \I2C_SDAT~input .bus_hold = "false"; defparam \I2C_SDAT~input .simulate_z_as = "z"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N20 +// Location: LCCOMB_X2_Y23_N20 cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~1 ( // Equation(s): -// \ula_|i2c_loader_|nbyte[0]~1_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|nbyte [0]) # ((\ula_|i2c_loader_|nbyte [1])))) # (!\ula_|i2c_loader_|phase [0] & (((\I2C_SDAT~input_o )))) +// \ula_|i2c_loader_|nbyte[0]~1_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|nbyte [1]) # ((\ula_|i2c_loader_|nbyte [0])))) # (!\ula_|i2c_loader_|phase [0] & (((\I2C_SDAT~input_o )))) - .dataa(\ula_|i2c_loader_|nbyte [0]), - .datab(\ula_|i2c_loader_|nbyte [1]), + .dataa(\ula_|i2c_loader_|nbyte [1]), + .datab(\ula_|i2c_loader_|nbyte [0]), .datac(\ula_|i2c_loader_|phase [0]), .datad(\I2C_SDAT~input_o ), .cin(gnd), @@ -54068,7 +53958,7 @@ defparam \ula_|i2c_loader_|nbyte[0]~1 .lut_mask = 16'hEFE0; defparam \ula_|i2c_loader_|nbyte[0]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N18 +// Location: LCCOMB_X2_Y23_N10 cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~2 ( // Equation(s): // \ula_|i2c_loader_|nbyte[0]~2_combout = (\ula_|i2c_loader_|state.Start~q & (\ula_|i2c_loader_|Mux42~0_combout )) # (!\ula_|i2c_loader_|state.Start~q & (((\ula_|i2c_loader_|thisbyte[0]~7_combout & \ula_|i2c_loader_|nbyte[0]~1_combout )))) @@ -54085,24 +53975,24 @@ defparam \ula_|i2c_loader_|nbyte[0]~2 .lut_mask = 16'hD888; defparam \ula_|i2c_loader_|nbyte[0]~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N24 +// Location: LCCOMB_X2_Y23_N8 cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~3 ( // Equation(s): -// \ula_|i2c_loader_|nbyte[0]~3_combout = (!\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|state.Idle~q & \ula_|i2c_loader_|nbyte[0]~2_combout )) +// \ula_|i2c_loader_|nbyte[0]~3_combout = (\ula_|i2c_loader_|state.Idle~q & (!\ula_|i2c_loader_|WideAnd0~combout & \ula_|i2c_loader_|nbyte[0]~2_combout )) .dataa(gnd), - .datab(\ula_|i2c_loader_|WideAnd0~combout ), - .datac(\ula_|i2c_loader_|state.Idle~q ), + .datab(\ula_|i2c_loader_|state.Idle~q ), + .datac(\ula_|i2c_loader_|WideAnd0~combout ), .datad(\ula_|i2c_loader_|nbyte[0]~2_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|nbyte[0]~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|nbyte[0]~3 .lut_mask = 16'h3000; +defparam \ula_|i2c_loader_|nbyte[0]~3 .lut_mask = 16'h0C00; defparam \ula_|i2c_loader_|nbyte[0]~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X1_Y23_N29 +// Location: FF_X2_Y23_N27 dffeas \ula_|i2c_loader_|nbyte[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|nbyte~4_combout ), @@ -54121,632 +54011,41 @@ defparam \ula_|i2c_loader_|nbyte[1] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|nbyte[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N18 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Stop~0 ( -// Equation(s): -// \ula_|i2c_loader_|state.Stop~0_combout = (!\ula_|i2c_loader_|nbyte [0] & (!\ula_|i2c_loader_|nbyte [1] & \ula_|i2c_loader_|state.Ack~q )) - - .dataa(\ula_|i2c_loader_|nbyte [0]), - .datab(\ula_|i2c_loader_|nbyte [1]), - .datac(\ula_|i2c_loader_|state.Ack~q ), - .datad(gnd), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Stop~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Stop~0 .lut_mask = 16'h1010; -defparam \ula_|i2c_loader_|state.Stop~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y24_N2 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Stop~1 ( -// Equation(s): -// \ula_|i2c_loader_|state.Stop~1_combout = (\ula_|i2c_loader_|WideAnd0~combout & (((\ula_|i2c_loader_|state.Stop~q )))) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Stop~0_combout ))) # -// (!\ula_|i2c_loader_|Mux42~0_combout & (\ula_|i2c_loader_|state.Stop~q )))) - - .dataa(\ula_|i2c_loader_|WideAnd0~combout ), - .datab(\ula_|i2c_loader_|Mux42~0_combout ), - .datac(\ula_|i2c_loader_|state.Stop~q ), - .datad(\ula_|i2c_loader_|state.Stop~0_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Stop~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Stop~1 .lut_mask = 16'hF4B0; -defparam \ula_|i2c_loader_|state.Stop~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X1_Y24_N3 -dffeas \ula_|i2c_loader_|state.Stop ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|state.Stop~1_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|state.Stop~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Stop .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|state.Stop .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y24_N20 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Idle~0 ( -// Equation(s): -// \ula_|i2c_loader_|state.Idle~0_combout = (!\ula_|i2c_loader_|state.Start~q & (!\ula_|i2c_loader_|state.Stop~q & (!\ula_|i2c_loader_|state.Pause~q & !\ula_|i2c_loader_|state.Ack~q ))) - - .dataa(\ula_|i2c_loader_|state.Start~q ), - .datab(\ula_|i2c_loader_|state.Stop~q ), - .datac(\ula_|i2c_loader_|state.Pause~q ), - .datad(\ula_|i2c_loader_|state.Ack~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Idle~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Idle~0 .lut_mask = 16'h0001; -defparam \ula_|i2c_loader_|state.Idle~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y24_N0 -cycloneive_lcell_comb \ula_|i2c_loader_|nbit~0 ( -// Equation(s): -// \ula_|i2c_loader_|nbit~0_combout = (\ula_|i2c_loader_|nbit [2] $ (((!\ula_|i2c_loader_|nbit [0] & !\ula_|i2c_loader_|nbit [1])))) # (!\ula_|i2c_loader_|state.Data~q ) - - .dataa(\ula_|i2c_loader_|state.Data~q ), - .datab(\ula_|i2c_loader_|nbit [0]), - .datac(\ula_|i2c_loader_|nbit [2]), - .datad(\ula_|i2c_loader_|nbit [1]), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbit~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit~0 .lut_mask = 16'hF5D7; -defparam \ula_|i2c_loader_|nbit~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X3_Y24_N1 -dffeas \ula_|i2c_loader_|nbit[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|nbit~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2c_loader_|nbit[0]~4_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|nbit [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit[2] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|nbit[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y24_N6 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Done~0 ( -// Equation(s): -// \ula_|i2c_loader_|state.Done~0_combout = (!\ula_|i2c_loader_|nbit [1] & (!\ula_|i2c_loader_|nbit [2] & (\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|nbit [0]))) - - .dataa(\ula_|i2c_loader_|nbit [1]), - .datab(\ula_|i2c_loader_|nbit [2]), - .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|nbit [0]), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Done~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Done~0 .lut_mask = 16'h0010; -defparam \ula_|i2c_loader_|state.Done~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N12 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Ack~0 ( -// Equation(s): -// \ula_|i2c_loader_|state.Ack~0_combout = ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Done~0_combout ) # (!\ula_|i2c_loader_|state.Idle~0_combout )))) # (!\ula_|i2c_loader_|state.Idle~q ) - - .dataa(\ula_|i2c_loader_|Mux42~0_combout ), - .datab(\ula_|i2c_loader_|state.Idle~0_combout ), - .datac(\ula_|i2c_loader_|state.Idle~q ), - .datad(\ula_|i2c_loader_|state.Done~0_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Ack~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Ack~0 .lut_mask = 16'hAF2F; -defparam \ula_|i2c_loader_|state.Ack~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N30 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Ack~1 ( -// Equation(s): -// \ula_|i2c_loader_|state.Ack~1_combout = (\ula_|i2c_loader_|state.Ack~0_combout & ((\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|state.Ack~q )) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|state.Data~q ))))) # -// (!\ula_|i2c_loader_|state.Ack~0_combout & (((\ula_|i2c_loader_|state.Ack~q )))) - - .dataa(\ula_|i2c_loader_|state.Ack~0_combout ), - .datab(\ula_|i2c_loader_|WideAnd0~combout ), - .datac(\ula_|i2c_loader_|state.Ack~q ), - .datad(\ula_|i2c_loader_|state.Data~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Ack~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Ack~1 .lut_mask = 16'hF2D0; -defparam \ula_|i2c_loader_|state.Ack~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X2_Y24_N31 -dffeas \ula_|i2c_loader_|state.Ack ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|state.Ack~1_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|state.Ack~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Ack .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|state.Ack .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N30 -cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[1]~5 ( -// Equation(s): -// \ula_|i2c_loader_|nbyte[1]~5_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|nbyte [0]) # ((\ula_|i2c_loader_|nbyte [1])))) # (!\ula_|i2c_loader_|phase [0] & (((\I2C_SDAT~input_o )))) - - .dataa(\ula_|i2c_loader_|nbyte [0]), - .datab(\ula_|i2c_loader_|nbyte [1]), - .datac(\ula_|i2c_loader_|phase [0]), - .datad(\I2C_SDAT~input_o ), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbyte[1]~5_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbyte[1]~5 .lut_mask = 16'hEFE0; -defparam \ula_|i2c_loader_|nbyte[1]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N8 -cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[0]~18 ( -// Equation(s): -// \ula_|i2c_loader_|thisbyte[0]~18_combout = (\ula_|i2c_loader_|phase [1] & (\ula_|i2c_loader_|state.Ack~q & (!\ula_|i2c_loader_|WideAnd0~combout & \ula_|i2c_loader_|nbyte[1]~5_combout ))) - - .dataa(\ula_|i2c_loader_|phase [1]), - .datab(\ula_|i2c_loader_|state.Ack~q ), - .datac(\ula_|i2c_loader_|WideAnd0~combout ), - .datad(\ula_|i2c_loader_|nbyte[1]~5_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|thisbyte[0]~18_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[0]~18 .lut_mask = 16'h0800; -defparam \ula_|i2c_loader_|thisbyte[0]~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X2_Y23_N15 -dffeas \ula_|i2c_loader_|thisbyte[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|thisbyte[0]~8_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(!\ula_|i2c_loader_|phase [0]), - .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|thisbyte [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[0] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|thisbyte[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N16 -cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[1]~10 ( -// Equation(s): -// \ula_|i2c_loader_|thisbyte[1]~10_combout = (\ula_|i2c_loader_|thisbyte [1] & (!\ula_|i2c_loader_|thisbyte[0]~9 )) # (!\ula_|i2c_loader_|thisbyte [1] & ((\ula_|i2c_loader_|thisbyte[0]~9 ) # (GND))) -// \ula_|i2c_loader_|thisbyte[1]~11 = CARRY((!\ula_|i2c_loader_|thisbyte[0]~9 ) # (!\ula_|i2c_loader_|thisbyte [1])) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|thisbyte [1]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2c_loader_|thisbyte[0]~9 ), - .combout(\ula_|i2c_loader_|thisbyte[1]~10_combout ), - .cout(\ula_|i2c_loader_|thisbyte[1]~11 )); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[1]~10 .lut_mask = 16'h3C3F; -defparam \ula_|i2c_loader_|thisbyte[1]~10 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X2_Y23_N17 -dffeas \ula_|i2c_loader_|thisbyte[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|thisbyte[1]~10_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(!\ula_|i2c_loader_|phase [0]), - .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|thisbyte [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[1] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|thisbyte[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N18 -cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[2]~12 ( -// Equation(s): -// \ula_|i2c_loader_|thisbyte[2]~12_combout = (\ula_|i2c_loader_|thisbyte [2] & (\ula_|i2c_loader_|thisbyte[1]~11 $ (GND))) # (!\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte[1]~11 & VCC)) -// \ula_|i2c_loader_|thisbyte[2]~13 = CARRY((\ula_|i2c_loader_|thisbyte [2] & !\ula_|i2c_loader_|thisbyte[1]~11 )) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|thisbyte [2]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2c_loader_|thisbyte[1]~11 ), - .combout(\ula_|i2c_loader_|thisbyte[2]~12_combout ), - .cout(\ula_|i2c_loader_|thisbyte[2]~13 )); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[2]~12 .lut_mask = 16'hC30C; -defparam \ula_|i2c_loader_|thisbyte[2]~12 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X2_Y23_N19 -dffeas \ula_|i2c_loader_|thisbyte[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|thisbyte[2]~12_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(!\ula_|i2c_loader_|phase [0]), - .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|thisbyte [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[2] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|thisbyte[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N20 -cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[3]~14 ( -// Equation(s): -// \ula_|i2c_loader_|thisbyte[3]~14_combout = (\ula_|i2c_loader_|thisbyte [3] & (!\ula_|i2c_loader_|thisbyte[2]~13 )) # (!\ula_|i2c_loader_|thisbyte [3] & ((\ula_|i2c_loader_|thisbyte[2]~13 ) # (GND))) -// \ula_|i2c_loader_|thisbyte[3]~15 = CARRY((!\ula_|i2c_loader_|thisbyte[2]~13 ) # (!\ula_|i2c_loader_|thisbyte [3])) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|thisbyte [3]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2c_loader_|thisbyte[2]~13 ), - .combout(\ula_|i2c_loader_|thisbyte[3]~14_combout ), - .cout(\ula_|i2c_loader_|thisbyte[3]~15 )); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[3]~14 .lut_mask = 16'h3C3F; -defparam \ula_|i2c_loader_|thisbyte[3]~14 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X2_Y23_N21 -dffeas \ula_|i2c_loader_|thisbyte[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|thisbyte[3]~14_combout ), - .asdata(\~GND~combout ), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(!\ula_|i2c_loader_|phase [0]), - .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|thisbyte [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[3] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|thisbyte[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N2 -cycloneive_lcell_comb \ula_|i2c_loader_|Equal2~0 ( -// Equation(s): -// \ula_|i2c_loader_|Equal2~0_combout = (\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte [1] & (!\ula_|i2c_loader_|thisbyte [0] & !\ula_|i2c_loader_|thisbyte [3]))) - - .dataa(\ula_|i2c_loader_|thisbyte [2]), - .datab(\ula_|i2c_loader_|thisbyte [1]), - .datac(\ula_|i2c_loader_|thisbyte [0]), - .datad(\ula_|i2c_loader_|thisbyte [3]), - .cin(gnd), - .combout(\ula_|i2c_loader_|Equal2~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|Equal2~0 .lut_mask = 16'h0002; -defparam \ula_|i2c_loader_|Equal2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y24_N26 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~0 ( -// Equation(s): -// \ula_|i2c_loader_|state.Pause~0_combout = (\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|phase [0])) # (!\ula_|i2c_loader_|phase [1]))) # (!\ula_|i2c_loader_|state.Data~q & (((\ula_|i2c_loader_|state.Stop~q )))) - - .dataa(\ula_|i2c_loader_|phase [1]), - .datab(\ula_|i2c_loader_|state.Stop~q ), - .datac(\ula_|i2c_loader_|phase [0]), - .datad(\ula_|i2c_loader_|state.Data~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Pause~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Pause~0 .lut_mask = 16'h5FCC; -defparam \ula_|i2c_loader_|state.Pause~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N22 -cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[4]~16 ( -// Equation(s): -// \ula_|i2c_loader_|thisbyte[4]~16_combout = \ula_|i2c_loader_|thisbyte [4] $ (!\ula_|i2c_loader_|thisbyte[3]~15 ) - - .dataa(\ula_|i2c_loader_|thisbyte [4]), - .datab(gnd), - .datac(gnd), - .datad(gnd), - .cin(\ula_|i2c_loader_|thisbyte[3]~15 ), - .combout(\ula_|i2c_loader_|thisbyte[4]~16_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[4]~16 .lut_mask = 16'hA5A5; -defparam \ula_|i2c_loader_|thisbyte[4]~16 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X2_Y23_N23 -dffeas \ula_|i2c_loader_|thisbyte[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|thisbyte[4]~16_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(!\ula_|i2c_loader_|phase [0]), - .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|thisbyte [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|thisbyte[4] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|thisbyte[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N20 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~1 ( -// Equation(s): -// \ula_|i2c_loader_|state.Pause~1_combout = (\ula_|i2c_loader_|state.Pause~0_combout & ((!\ula_|i2c_loader_|thisbyte [4]) # (!\ula_|i2c_loader_|Equal2~0_combout ))) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|Equal2~0_combout ), - .datac(\ula_|i2c_loader_|state.Pause~0_combout ), - .datad(\ula_|i2c_loader_|thisbyte [4]), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Pause~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Pause~1 .lut_mask = 16'h30F0; -defparam \ula_|i2c_loader_|state.Pause~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y24_N24 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Done~2 ( -// Equation(s): -// \ula_|i2c_loader_|state.Done~2_combout = (\ula_|i2c_loader_|scl_out~0_combout & (((\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|state.Done~1_combout )) # (!\ula_|i2c_loader_|state.Pause~q ))) # (!\ula_|i2c_loader_|scl_out~0_combout & -// (\ula_|i2c_loader_|state.Data~q & ((!\ula_|i2c_loader_|state.Done~1_combout )))) - - .dataa(\ula_|i2c_loader_|scl_out~0_combout ), - .datab(\ula_|i2c_loader_|state.Data~q ), - .datac(\ula_|i2c_loader_|state.Pause~q ), - .datad(\ula_|i2c_loader_|state.Done~1_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Done~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Done~2 .lut_mask = 16'h0ACE; -defparam \ula_|i2c_loader_|state.Done~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y24_N18 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~2 ( -// Equation(s): -// \ula_|i2c_loader_|state.Pause~2_combout = ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Start~q ) # (!\ula_|i2c_loader_|state.Done~2_combout )))) # (!\ula_|i2c_loader_|state.Idle~q ) - - .dataa(\ula_|i2c_loader_|state.Done~2_combout ), - .datab(\ula_|i2c_loader_|Mux42~0_combout ), - .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|state.Idle~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Pause~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Pause~2 .lut_mask = 16'hC4FF; -defparam \ula_|i2c_loader_|state.Pause~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y24_N22 -cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~3 ( -// Equation(s): -// \ula_|i2c_loader_|state.Pause~3_combout = (\ula_|i2c_loader_|WideAnd0~combout & (((\ula_|i2c_loader_|state.Pause~q )))) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|state.Pause~2_combout & (\ula_|i2c_loader_|state.Pause~1_combout )) # -// (!\ula_|i2c_loader_|state.Pause~2_combout & ((\ula_|i2c_loader_|state.Pause~q ))))) - - .dataa(\ula_|i2c_loader_|state.Pause~1_combout ), - .datab(\ula_|i2c_loader_|WideAnd0~combout ), - .datac(\ula_|i2c_loader_|state.Pause~q ), - .datad(\ula_|i2c_loader_|state.Pause~2_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state.Pause~3_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Pause~3 .lut_mask = 16'hE2F0; -defparam \ula_|i2c_loader_|state.Pause~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X1_Y24_N23 -dffeas \ula_|i2c_loader_|state.Pause ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|state.Pause~3_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|state.Pause~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Pause .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|state.Pause .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y24_N30 -cycloneive_lcell_comb \ula_|i2c_loader_|state~25 ( -// Equation(s): -// \ula_|i2c_loader_|state~25_combout = ((\ula_|i2c_loader_|Mux42~0_combout & (\ula_|i2c_loader_|state.Pause~q & !\ula_|i2c_loader_|state.Start~q )) # (!\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Start~q )))) # -// (!\ula_|i2c_loader_|state.Idle~q ) - - .dataa(\ula_|i2c_loader_|state.Pause~q ), - .datab(\ula_|i2c_loader_|Mux42~0_combout ), - .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|state.Idle~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|state~25_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|state~25 .lut_mask = 16'h38FF; -defparam \ula_|i2c_loader_|state~25 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X1_Y24_N31 -dffeas \ula_|i2c_loader_|state.Start ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|state~25_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(!\ula_|i2c_loader_|WideAnd0~combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|state.Start~q ), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|state.Start .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|state.Start .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X1_Y23_N10 -cycloneive_lcell_comb \ula_|i2c_loader_|nbyte~0 ( -// Equation(s): -// \ula_|i2c_loader_|nbyte~0_combout = (\ula_|i2c_loader_|phase [0] & (!\ula_|i2c_loader_|nbyte [0] & !\ula_|i2c_loader_|state.Start~q )) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|phase [0]), - .datac(\ula_|i2c_loader_|nbyte [0]), - .datad(\ula_|i2c_loader_|state.Start~q ), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbyte~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbyte~0 .lut_mask = 16'h000C; -defparam \ula_|i2c_loader_|nbyte~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X1_Y23_N11 -dffeas \ula_|i2c_loader_|nbyte[0] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|nbyte~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|i2c_loader_|nbyte[0]~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2c_loader_|nbyte [0]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbyte[0] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|nbyte[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N22 +// Location: LCCOMB_X2_Y23_N28 cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~1 ( // Equation(s): -// \ula_|i2c_loader_|nbit[0]~1_combout = (!\ula_|i2c_loader_|nbyte [0] & (!\ula_|i2c_loader_|nbyte [1] & !\ula_|i2c_loader_|state.Data~q )) +// \ula_|i2c_loader_|nbit[0]~1_combout = (!\ula_|i2c_loader_|nbyte [1] & (!\ula_|i2c_loader_|nbyte [0] & !\ula_|i2c_loader_|state.Data~q )) - .dataa(\ula_|i2c_loader_|nbyte [0]), - .datab(gnd), - .datac(\ula_|i2c_loader_|nbyte [1]), - .datad(\ula_|i2c_loader_|state.Data~q ), + .dataa(\ula_|i2c_loader_|nbyte [1]), + .datab(\ula_|i2c_loader_|nbyte [0]), + .datac(\ula_|i2c_loader_|state.Data~q ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2c_loader_|nbit[0]~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|nbit[0]~1 .lut_mask = 16'h0005; +defparam \ula_|i2c_loader_|nbit[0]~1 .lut_mask = 16'h0101; defparam \ula_|i2c_loader_|nbit[0]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N0 -cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~2 ( -// Equation(s): -// \ula_|i2c_loader_|nbit[0]~2_combout = (\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|phase [1])) # (!\ula_|i2c_loader_|phase [0]))) # (!\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|state.Ack~q )))) - - .dataa(\ula_|i2c_loader_|phase [0]), - .datab(\ula_|i2c_loader_|state.Data~q ), - .datac(\ula_|i2c_loader_|state.Ack~q ), - .datad(\ula_|i2c_loader_|phase [1]), - .cin(gnd), - .combout(\ula_|i2c_loader_|nbit[0]~2_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|nbit[0]~2 .lut_mask = 16'h47CF; -defparam \ula_|i2c_loader_|nbit[0]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N6 +// Location: LCCOMB_X2_Y23_N30 cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~3 ( // Equation(s): -// \ula_|i2c_loader_|nbit[0]~3_combout = (!\ula_|i2c_loader_|state.Start~q & ((\ula_|i2c_loader_|nbit[0]~1_combout ) # ((\ula_|i2c_loader_|nbit[0]~2_combout ) # (\ula_|i2c_loader_|state.Done~0_combout )))) +// \ula_|i2c_loader_|nbit[0]~3_combout = (!\ula_|i2c_loader_|state.Start~q & ((\ula_|i2c_loader_|nbit[0]~2_combout ) # ((\ula_|i2c_loader_|nbit[0]~1_combout ) # (\ula_|i2c_loader_|state.Done~0_combout )))) - .dataa(\ula_|i2c_loader_|nbit[0]~1_combout ), - .datab(\ula_|i2c_loader_|nbit[0]~2_combout ), - .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|state.Done~0_combout ), + .dataa(\ula_|i2c_loader_|nbit[0]~2_combout ), + .datab(\ula_|i2c_loader_|nbit[0]~1_combout ), + .datac(\ula_|i2c_loader_|state.Done~0_combout ), + .datad(\ula_|i2c_loader_|state.Start~q ), .cin(gnd), .combout(\ula_|i2c_loader_|nbit[0]~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|nbit[0]~3 .lut_mask = 16'h0F0E; +defparam \ula_|i2c_loader_|nbit[0]~3 .lut_mask = 16'h00FE; defparam \ula_|i2c_loader_|nbit[0]~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N4 +// Location: LCCOMB_X2_Y23_N0 cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~4 ( // Equation(s): // \ula_|i2c_loader_|nbit[0]~4_combout = (!\ula_|i2c_loader_|nbit[0]~3_combout & (\ula_|i2c_loader_|Mux42~0_combout & (!\ula_|i2c_loader_|WideAnd0~combout & \ula_|i2c_loader_|state.Idle~q ))) @@ -54763,7 +54062,7 @@ defparam \ula_|i2c_loader_|nbit[0]~4 .lut_mask = 16'h0400; defparam \ula_|i2c_loader_|nbit[0]~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y24_N3 +// Location: FF_X2_Y24_N3 dffeas \ula_|i2c_loader_|nbit[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|nbit~5_combout ), @@ -54782,27 +54081,27 @@ defparam \ula_|i2c_loader_|nbit[0] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|nbit[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y24_N12 -cycloneive_lcell_comb \ula_|i2c_loader_|nbit~6 ( +// Location: LCCOMB_X2_Y24_N12 +cycloneive_lcell_comb \ula_|i2c_loader_|nbit~0 ( // Equation(s): -// \ula_|i2c_loader_|nbit~6_combout = (\ula_|i2c_loader_|nbit [1] $ (!\ula_|i2c_loader_|nbit [0])) # (!\ula_|i2c_loader_|state.Data~q ) +// \ula_|i2c_loader_|nbit~0_combout = (\ula_|i2c_loader_|nbit [2] $ (((!\ula_|i2c_loader_|nbit [0] & !\ula_|i2c_loader_|nbit [1])))) # (!\ula_|i2c_loader_|state.Data~q ) .dataa(\ula_|i2c_loader_|state.Data~q ), - .datab(gnd), - .datac(\ula_|i2c_loader_|nbit [1]), - .datad(\ula_|i2c_loader_|nbit [0]), + .datab(\ula_|i2c_loader_|nbit [0]), + .datac(\ula_|i2c_loader_|nbit [2]), + .datad(\ula_|i2c_loader_|nbit [1]), .cin(gnd), - .combout(\ula_|i2c_loader_|nbit~6_combout ), + .combout(\ula_|i2c_loader_|nbit~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|nbit~6 .lut_mask = 16'hF55F; -defparam \ula_|i2c_loader_|nbit~6 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|nbit~0 .lut_mask = 16'hF5D7; +defparam \ula_|i2c_loader_|nbit~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y24_N13 -dffeas \ula_|i2c_loader_|nbit[1] ( +// Location: FF_X2_Y24_N13 +dffeas \ula_|i2c_loader_|nbit[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|nbit~6_combout ), + .d(\ula_|i2c_loader_|nbit~0_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -54811,22 +54110,22 @@ dffeas \ula_|i2c_loader_|nbit[1] ( .ena(\ula_|i2c_loader_|nbit[0]~4_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\ula_|i2c_loader_|nbit [1]), + .q(\ula_|i2c_loader_|nbit [2]), .prn(vcc)); // synopsys translate_off -defparam \ula_|i2c_loader_|nbit[1] .is_wysiwyg = "true"; -defparam \ula_|i2c_loader_|nbit[1] .power_up = "low"; +defparam \ula_|i2c_loader_|nbit[2] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|nbit[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y24_N16 +// Location: LCCOMB_X2_Y24_N28 cycloneive_lcell_comb \ula_|i2c_loader_|state.Done~1 ( // Equation(s): -// \ula_|i2c_loader_|state.Done~1_combout = (!\ula_|i2c_loader_|nbit [1] & (!\ula_|i2c_loader_|nbit [2] & !\ula_|i2c_loader_|nbit [0])) +// \ula_|i2c_loader_|state.Done~1_combout = (!\ula_|i2c_loader_|nbit [2] & (!\ula_|i2c_loader_|nbit [0] & !\ula_|i2c_loader_|nbit [1])) - .dataa(\ula_|i2c_loader_|nbit [1]), - .datab(\ula_|i2c_loader_|nbit [2]), + .dataa(\ula_|i2c_loader_|nbit [2]), + .datab(\ula_|i2c_loader_|nbit [0]), .datac(gnd), - .datad(\ula_|i2c_loader_|nbit [0]), + .datad(\ula_|i2c_loader_|nbit [1]), .cin(gnd), .combout(\ula_|i2c_loader_|state.Done~1_combout ), .cout()); @@ -54835,75 +54134,75 @@ defparam \ula_|i2c_loader_|state.Done~1 .lut_mask = 16'h0011; defparam \ula_|i2c_loader_|state.Done~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N6 +// Location: LCCOMB_X1_Y23_N18 cycloneive_lcell_comb \ula_|i2c_loader_|state~27 ( // Equation(s): // \ula_|i2c_loader_|state~27_combout = ((!\ula_|i2c_loader_|state.Done~1_combout ) # (!\ula_|i2c_loader_|phase [0])) # (!\ula_|i2c_loader_|phase [1]) .dataa(\ula_|i2c_loader_|phase [1]), - .datab(gnd), - .datac(\ula_|i2c_loader_|phase [0]), - .datad(\ula_|i2c_loader_|state.Done~1_combout ), + .datab(\ula_|i2c_loader_|phase [0]), + .datac(\ula_|i2c_loader_|state.Done~1_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2c_loader_|state~27_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|state~27 .lut_mask = 16'h5FFF; +defparam \ula_|i2c_loader_|state~27 .lut_mask = 16'h7F7F; defparam \ula_|i2c_loader_|state~27 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N28 +// Location: LCCOMB_X2_Y23_N14 cycloneive_lcell_comb \ula_|i2c_loader_|state~24 ( // Equation(s): // \ula_|i2c_loader_|state~24_combout = (\ula_|i2c_loader_|state.Ack~q & ((\ula_|i2c_loader_|nbyte [0]) # (\ula_|i2c_loader_|nbyte [1]))) - .dataa(\ula_|i2c_loader_|nbyte [0]), - .datab(\ula_|i2c_loader_|nbyte [1]), - .datac(\ula_|i2c_loader_|state.Ack~q ), - .datad(gnd), + .dataa(gnd), + .datab(\ula_|i2c_loader_|nbyte [0]), + .datac(\ula_|i2c_loader_|nbyte [1]), + .datad(\ula_|i2c_loader_|state.Ack~q ), .cin(gnd), .combout(\ula_|i2c_loader_|state~24_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|state~24 .lut_mask = 16'hE0E0; +defparam \ula_|i2c_loader_|state~24 .lut_mask = 16'hFC00; defparam \ula_|i2c_loader_|state~24 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N16 +// Location: LCCOMB_X2_Y23_N2 cycloneive_lcell_comb \ula_|i2c_loader_|state~26 ( // Equation(s): -// \ula_|i2c_loader_|state~26_combout = (\ula_|i2c_loader_|phase [1] & (\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|state~24_combout )) +// \ula_|i2c_loader_|state~26_combout = (\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|state~24_combout & \ula_|i2c_loader_|phase [1])) - .dataa(\ula_|i2c_loader_|phase [1]), - .datab(gnd), - .datac(\ula_|i2c_loader_|phase [0]), - .datad(\ula_|i2c_loader_|state~24_combout ), + .dataa(gnd), + .datab(\ula_|i2c_loader_|phase [0]), + .datac(\ula_|i2c_loader_|state~24_combout ), + .datad(\ula_|i2c_loader_|phase [1]), .cin(gnd), .combout(\ula_|i2c_loader_|state~26_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|state~26 .lut_mask = 16'hA000; +defparam \ula_|i2c_loader_|state~26 .lut_mask = 16'hC000; defparam \ula_|i2c_loader_|state~26 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N28 +// Location: LCCOMB_X1_Y23_N0 cycloneive_lcell_comb \ula_|i2c_loader_|state.Data~0 ( // Equation(s): // \ula_|i2c_loader_|state.Data~0_combout = (\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|state~27_combout )) # (!\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|state~26_combout ))) - .dataa(\ula_|i2c_loader_|state~27_combout ), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|i2c_loader_|state~27_combout ), .datac(\ula_|i2c_loader_|state.Data~q ), .datad(\ula_|i2c_loader_|state~26_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|state.Data~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|state.Data~0 .lut_mask = 16'hAFA0; +defparam \ula_|i2c_loader_|state.Data~0 .lut_mask = 16'hCFC0; defparam \ula_|i2c_loader_|state.Data~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X1_Y24_N29 +// Location: FF_X1_Y23_N1 dffeas \ula_|i2c_loader_|state.Data ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|state.Data~0_combout ), @@ -54922,24 +54221,492 @@ defparam \ula_|i2c_loader_|state.Data .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|state.Data .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N12 -cycloneive_lcell_comb \ula_|i2c_loader_|scl_out~0 ( +// Location: LCCOMB_X1_Y23_N16 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Done~2 ( // Equation(s): -// \ula_|i2c_loader_|scl_out~0_combout = (!\ula_|i2c_loader_|state.Data~q & (!\ula_|i2c_loader_|state.Ack~q & !\ula_|i2c_loader_|state.Stop~q )) +// \ula_|i2c_loader_|state.Done~2_combout = (\ula_|i2c_loader_|scl_out~0_combout & (((\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|state.Done~1_combout )) # (!\ula_|i2c_loader_|state.Pause~q ))) # (!\ula_|i2c_loader_|scl_out~0_combout & +// (\ula_|i2c_loader_|state.Data~q & (!\ula_|i2c_loader_|state.Done~1_combout ))) + + .dataa(\ula_|i2c_loader_|scl_out~0_combout ), + .datab(\ula_|i2c_loader_|state.Data~q ), + .datac(\ula_|i2c_loader_|state.Done~1_combout ), + .datad(\ula_|i2c_loader_|state.Pause~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Done~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Done~2 .lut_mask = 16'h0CAE; +defparam \ula_|i2c_loader_|state.Done~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N10 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~1 ( +// Equation(s): +// \ula_|i2c_loader_|state.Pause~1_combout = ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Start~q ) # (!\ula_|i2c_loader_|state.Done~2_combout )))) # (!\ula_|i2c_loader_|state.Idle~q ) + + .dataa(\ula_|i2c_loader_|state.Start~q ), + .datab(\ula_|i2c_loader_|state.Done~2_combout ), + .datac(\ula_|i2c_loader_|Mux42~0_combout ), + .datad(\ula_|i2c_loader_|state.Idle~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Pause~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Pause~1 .lut_mask = 16'hB0FF; +defparam \ula_|i2c_loader_|state.Pause~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X5_Y23_N18 +cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[0]~8 ( +// Equation(s): +// \ula_|i2c_loader_|thisbyte[0]~8_combout = \ula_|i2c_loader_|thisbyte [0] $ (VCC) +// \ula_|i2c_loader_|thisbyte[0]~9 = CARRY(\ula_|i2c_loader_|thisbyte [0]) .dataa(gnd), + .datab(\ula_|i2c_loader_|thisbyte [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\ula_|i2c_loader_|thisbyte[0]~8_combout ), + .cout(\ula_|i2c_loader_|thisbyte[0]~9 )); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[0]~8 .lut_mask = 16'h33CC; +defparam \ula_|i2c_loader_|thisbyte[0]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X5_Y23_N28 +cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[1]~5 ( +// Equation(s): +// \ula_|i2c_loader_|nbyte[1]~5_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|nbyte [0]) # ((\ula_|i2c_loader_|nbyte [1])))) # (!\ula_|i2c_loader_|phase [0] & (((\I2C_SDAT~input_o )))) + + .dataa(\ula_|i2c_loader_|phase [0]), + .datab(\ula_|i2c_loader_|nbyte [0]), + .datac(\ula_|i2c_loader_|nbyte [1]), + .datad(\I2C_SDAT~input_o ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbyte[1]~5_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbyte[1]~5 .lut_mask = 16'hFDA8; +defparam \ula_|i2c_loader_|nbyte[1]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X5_Y23_N16 +cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[0]~18 ( +// Equation(s): +// \ula_|i2c_loader_|thisbyte[0]~18_combout = (\ula_|i2c_loader_|state.Ack~q & (\ula_|i2c_loader_|phase [1] & (!\ula_|i2c_loader_|WideAnd0~combout & \ula_|i2c_loader_|nbyte[1]~5_combout ))) + + .dataa(\ula_|i2c_loader_|state.Ack~q ), + .datab(\ula_|i2c_loader_|phase [1]), + .datac(\ula_|i2c_loader_|WideAnd0~combout ), + .datad(\ula_|i2c_loader_|nbyte[1]~5_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|thisbyte[0]~18_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[0]~18 .lut_mask = 16'h0800; +defparam \ula_|i2c_loader_|thisbyte[0]~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X5_Y23_N19 +dffeas \ula_|i2c_loader_|thisbyte[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|thisbyte[0]~8_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\ula_|i2c_loader_|phase [0]), + .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|thisbyte [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[0] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|thisbyte[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X5_Y23_N20 +cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[1]~10 ( +// Equation(s): +// \ula_|i2c_loader_|thisbyte[1]~10_combout = (\ula_|i2c_loader_|thisbyte [1] & (!\ula_|i2c_loader_|thisbyte[0]~9 )) # (!\ula_|i2c_loader_|thisbyte [1] & ((\ula_|i2c_loader_|thisbyte[0]~9 ) # (GND))) +// \ula_|i2c_loader_|thisbyte[1]~11 = CARRY((!\ula_|i2c_loader_|thisbyte[0]~9 ) # (!\ula_|i2c_loader_|thisbyte [1])) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|thisbyte [1]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2c_loader_|thisbyte[0]~9 ), + .combout(\ula_|i2c_loader_|thisbyte[1]~10_combout ), + .cout(\ula_|i2c_loader_|thisbyte[1]~11 )); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[1]~10 .lut_mask = 16'h3C3F; +defparam \ula_|i2c_loader_|thisbyte[1]~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X5_Y23_N21 +dffeas \ula_|i2c_loader_|thisbyte[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|thisbyte[1]~10_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\ula_|i2c_loader_|phase [0]), + .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|thisbyte [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[1] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|thisbyte[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X5_Y23_N22 +cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[2]~12 ( +// Equation(s): +// \ula_|i2c_loader_|thisbyte[2]~12_combout = (\ula_|i2c_loader_|thisbyte [2] & (\ula_|i2c_loader_|thisbyte[1]~11 $ (GND))) # (!\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte[1]~11 & VCC)) +// \ula_|i2c_loader_|thisbyte[2]~13 = CARRY((\ula_|i2c_loader_|thisbyte [2] & !\ula_|i2c_loader_|thisbyte[1]~11 )) + + .dataa(\ula_|i2c_loader_|thisbyte [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2c_loader_|thisbyte[1]~11 ), + .combout(\ula_|i2c_loader_|thisbyte[2]~12_combout ), + .cout(\ula_|i2c_loader_|thisbyte[2]~13 )); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[2]~12 .lut_mask = 16'hA50A; +defparam \ula_|i2c_loader_|thisbyte[2]~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X5_Y23_N23 +dffeas \ula_|i2c_loader_|thisbyte[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|thisbyte[2]~12_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\ula_|i2c_loader_|phase [0]), + .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|thisbyte [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[2] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|thisbyte[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X5_Y23_N24 +cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[3]~14 ( +// Equation(s): +// \ula_|i2c_loader_|thisbyte[3]~14_combout = (\ula_|i2c_loader_|thisbyte [3] & (!\ula_|i2c_loader_|thisbyte[2]~13 )) # (!\ula_|i2c_loader_|thisbyte [3] & ((\ula_|i2c_loader_|thisbyte[2]~13 ) # (GND))) +// \ula_|i2c_loader_|thisbyte[3]~15 = CARRY((!\ula_|i2c_loader_|thisbyte[2]~13 ) # (!\ula_|i2c_loader_|thisbyte [3])) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|thisbyte [3]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2c_loader_|thisbyte[2]~13 ), + .combout(\ula_|i2c_loader_|thisbyte[3]~14_combout ), + .cout(\ula_|i2c_loader_|thisbyte[3]~15 )); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[3]~14 .lut_mask = 16'h3C3F; +defparam \ula_|i2c_loader_|thisbyte[3]~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X5_Y23_N25 +dffeas \ula_|i2c_loader_|thisbyte[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|thisbyte[3]~14_combout ), + .asdata(\~GND~combout ), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\ula_|i2c_loader_|phase [0]), + .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|thisbyte [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[3] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|thisbyte[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y23_N4 +cycloneive_lcell_comb \ula_|i2c_loader_|Equal2~0 ( +// Equation(s): +// \ula_|i2c_loader_|Equal2~0_combout = (\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte [3] & (!\ula_|i2c_loader_|thisbyte [1] & !\ula_|i2c_loader_|thisbyte [0]))) + + .dataa(\ula_|i2c_loader_|thisbyte [2]), + .datab(\ula_|i2c_loader_|thisbyte [3]), + .datac(\ula_|i2c_loader_|thisbyte [1]), + .datad(\ula_|i2c_loader_|thisbyte [0]), + .cin(gnd), + .combout(\ula_|i2c_loader_|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|Equal2~0 .lut_mask = 16'h0002; +defparam \ula_|i2c_loader_|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X5_Y23_N26 +cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[4]~16 ( +// Equation(s): +// \ula_|i2c_loader_|thisbyte[4]~16_combout = \ula_|i2c_loader_|thisbyte [4] $ (!\ula_|i2c_loader_|thisbyte[3]~15 ) + + .dataa(\ula_|i2c_loader_|thisbyte [4]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\ula_|i2c_loader_|thisbyte[3]~15 ), + .combout(\ula_|i2c_loader_|thisbyte[4]~16_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[4]~16 .lut_mask = 16'hA5A5; +defparam \ula_|i2c_loader_|thisbyte[4]~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X5_Y23_N27 +dffeas \ula_|i2c_loader_|thisbyte[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|thisbyte[4]~16_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\ula_|i2c_loader_|phase [0]), + .ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|thisbyte [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|thisbyte[4] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|thisbyte[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y23_N30 +cycloneive_lcell_comb \ula_|i2c_loader_|Equal2~1 ( +// Equation(s): +// \ula_|i2c_loader_|Equal2~1_combout = (\ula_|i2c_loader_|Equal2~0_combout & \ula_|i2c_loader_|thisbyte [4]) + + .dataa(gnd), + .datab(gnd), + .datac(\ula_|i2c_loader_|Equal2~0_combout ), + .datad(\ula_|i2c_loader_|thisbyte [4]), + .cin(gnd), + .combout(\ula_|i2c_loader_|Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|Equal2~1 .lut_mask = 16'hF000; +defparam \ula_|i2c_loader_|Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N22 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~0 ( +// Equation(s): +// \ula_|i2c_loader_|state.Pause~0_combout = (!\ula_|i2c_loader_|Equal2~1_combout & ((\ula_|i2c_loader_|state.Data~q & ((!\ula_|i2c_loader_|Mux42~0_combout ))) # (!\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|state.Stop~q )))) + + .dataa(\ula_|i2c_loader_|state.Stop~q ), + .datab(\ula_|i2c_loader_|Mux42~0_combout ), + .datac(\ula_|i2c_loader_|state.Data~q ), + .datad(\ula_|i2c_loader_|Equal2~1_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Pause~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Pause~0 .lut_mask = 16'h003A; +defparam \ula_|i2c_loader_|state.Pause~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N24 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~2 ( +// Equation(s): +// \ula_|i2c_loader_|state.Pause~2_combout = (\ula_|i2c_loader_|state.Pause~1_combout & ((\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|state.Pause~q )) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|state.Pause~0_combout ))))) # +// (!\ula_|i2c_loader_|state.Pause~1_combout & (((\ula_|i2c_loader_|state.Pause~q )))) + + .dataa(\ula_|i2c_loader_|state.Pause~1_combout ), + .datab(\ula_|i2c_loader_|WideAnd0~combout ), + .datac(\ula_|i2c_loader_|state.Pause~q ), + .datad(\ula_|i2c_loader_|state.Pause~0_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Pause~2_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Pause~2 .lut_mask = 16'hF2D0; +defparam \ula_|i2c_loader_|state.Pause~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X1_Y23_N25 +dffeas \ula_|i2c_loader_|state.Pause ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|state.Pause~2_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|state.Pause~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Pause .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|state.Pause .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y23_N26 +cycloneive_lcell_comb \ula_|i2c_loader_|state~25 ( +// Equation(s): +// \ula_|i2c_loader_|state~25_combout = ((\ula_|i2c_loader_|Mux42~0_combout & (\ula_|i2c_loader_|state.Pause~q & !\ula_|i2c_loader_|state.Start~q )) # (!\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Start~q )))) # +// (!\ula_|i2c_loader_|state.Idle~q ) + + .dataa(\ula_|i2c_loader_|state.Pause~q ), + .datab(\ula_|i2c_loader_|Mux42~0_combout ), + .datac(\ula_|i2c_loader_|state.Start~q ), + .datad(\ula_|i2c_loader_|state.Idle~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state~25_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state~25 .lut_mask = 16'h38FF; +defparam \ula_|i2c_loader_|state~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X3_Y23_N27 +dffeas \ula_|i2c_loader_|state.Start ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|state~25_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(!\ula_|i2c_loader_|WideAnd0~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|state.Start~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Start .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|state.Start .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N4 +cycloneive_lcell_comb \ula_|i2c_loader_|nbyte~0 ( +// Equation(s): +// \ula_|i2c_loader_|nbyte~0_combout = (\ula_|i2c_loader_|phase [0] & (!\ula_|i2c_loader_|nbyte [0] & !\ula_|i2c_loader_|state.Start~q )) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|phase [0]), + .datac(\ula_|i2c_loader_|nbyte [0]), + .datad(\ula_|i2c_loader_|state.Start~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|nbyte~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbyte~0 .lut_mask = 16'h000C; +defparam \ula_|i2c_loader_|nbyte~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y23_N5 +dffeas \ula_|i2c_loader_|nbyte[0] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|nbyte~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|i2c_loader_|nbyte[0]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|nbyte [0]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|nbyte[0] .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|nbyte[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N12 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Stop~0 ( +// Equation(s): +// \ula_|i2c_loader_|state.Stop~0_combout = (!\ula_|i2c_loader_|nbyte [0] & (!\ula_|i2c_loader_|nbyte [1] & \ula_|i2c_loader_|state.Ack~q )) + + .dataa(gnd), + .datab(\ula_|i2c_loader_|nbyte [0]), + .datac(\ula_|i2c_loader_|nbyte [1]), + .datad(\ula_|i2c_loader_|state.Ack~q ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Stop~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Stop~0 .lut_mask = 16'h0300; +defparam \ula_|i2c_loader_|state.Stop~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y23_N6 +cycloneive_lcell_comb \ula_|i2c_loader_|state.Stop~1 ( +// Equation(s): +// \ula_|i2c_loader_|state.Stop~1_combout = (\ula_|i2c_loader_|WideAnd0~combout & (((\ula_|i2c_loader_|state.Stop~q )))) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|Mux42~0_combout & (\ula_|i2c_loader_|state.Stop~0_combout )) # +// (!\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Stop~q ))))) + + .dataa(\ula_|i2c_loader_|state.Stop~0_combout ), + .datab(\ula_|i2c_loader_|WideAnd0~combout ), + .datac(\ula_|i2c_loader_|state.Stop~q ), + .datad(\ula_|i2c_loader_|Mux42~0_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|state.Stop~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Stop~1 .lut_mask = 16'hE2F0; +defparam \ula_|i2c_loader_|state.Stop~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y23_N7 +dffeas \ula_|i2c_loader_|state.Stop ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2c_loader_|state.Stop~1_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2c_loader_|state.Stop~q ), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2c_loader_|state.Stop .is_wysiwyg = "true"; +defparam \ula_|i2c_loader_|state.Stop .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y23_N22 +cycloneive_lcell_comb \ula_|i2c_loader_|scl_out~0 ( +// Equation(s): +// \ula_|i2c_loader_|scl_out~0_combout = (!\ula_|i2c_loader_|state.Stop~q & (!\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|state.Ack~q )) + + .dataa(\ula_|i2c_loader_|state.Stop~q ), .datab(\ula_|i2c_loader_|state.Data~q ), - .datac(\ula_|i2c_loader_|state.Ack~q ), - .datad(\ula_|i2c_loader_|state.Stop~q ), + .datac(gnd), + .datad(\ula_|i2c_loader_|state.Ack~q ), .cin(gnd), .combout(\ula_|i2c_loader_|scl_out~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|scl_out~0 .lut_mask = 16'h0003; +defparam \ula_|i2c_loader_|scl_out~0 .lut_mask = 16'h0011; defparam \ula_|i2c_loader_|scl_out~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X1_Y23_N13 +// Location: FF_X1_Y23_N7 dffeas \ula_|i2c_loader_|scl_out~_Duplicate_1 ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|scl_out~2_combout ), @@ -54958,7 +54725,7 @@ defparam \ula_|i2c_loader_|scl_out~_Duplicate_1 .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|scl_out~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N16 +// Location: LCCOMB_X1_Y23_N8 cycloneive_lcell_comb \ula_|i2c_loader_|scl_out~1 ( // Equation(s): // \ula_|i2c_loader_|scl_out~1_combout = (\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|state.Start~q $ (((!\ula_|i2c_loader_|scl_out~_Duplicate_1_q ))))) # (!\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|phase [1]) # @@ -54976,20 +54743,20 @@ defparam \ula_|i2c_loader_|scl_out~1 .lut_mask = 16'hBA74; defparam \ula_|i2c_loader_|scl_out~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N12 +// Location: LCCOMB_X1_Y23_N6 cycloneive_lcell_comb \ula_|i2c_loader_|scl_out~2 ( // Equation(s): // \ula_|i2c_loader_|scl_out~2_combout = (\ula_|i2c_loader_|scl_out~1_combout & ((\ula_|i2c_loader_|state.Start~q ))) # (!\ula_|i2c_loader_|scl_out~1_combout & (!\ula_|i2c_loader_|scl_out~0_combout & !\ula_|i2c_loader_|state.Start~q )) .dataa(\ula_|i2c_loader_|scl_out~0_combout ), .datab(\ula_|i2c_loader_|scl_out~1_combout ), - .datac(gnd), - .datad(\ula_|i2c_loader_|state.Start~q ), + .datac(\ula_|i2c_loader_|state.Start~q ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2c_loader_|scl_out~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|scl_out~2 .lut_mask = 16'hCC11; +defparam \ula_|i2c_loader_|scl_out~2 .lut_mask = 16'hC1C1; defparam \ula_|i2c_loader_|scl_out~2 .sum_lutc_input = "datac"; // synopsys translate_on @@ -55012,7 +54779,7 @@ defparam \ula_|i2c_loader_|scl_out .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|scl_out .power_up = "high"; // synopsys translate_on -// Location: FF_X1_Y23_N23 +// Location: FF_X1_Y23_N13 dffeas \ula_|i2c_loader_|sda_out~_Duplicate_1 ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|sda_out~4_combout ), @@ -55031,32 +54798,32 @@ defparam \ula_|i2c_loader_|sda_out~_Duplicate_1 .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|sda_out~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N10 +// Location: LCCOMB_X4_Y23_N10 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~4 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~4_combout = (!\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|state.Start~q ) +// \ula_|i2c_loader_|shiftreg~4_combout = (!\ula_|i2c_loader_|state.Start~q & !\ula_|i2c_loader_|state.Data~q ) - .dataa(gnd), + .dataa(\ula_|i2c_loader_|state.Start~q ), .datab(gnd), .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|state.Start~q ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg~4_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~4 .lut_mask = 16'h000F; +defparam \ula_|i2c_loader_|shiftreg~4 .lut_mask = 16'h0505; defparam \ula_|i2c_loader_|shiftreg~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N0 +// Location: LCCOMB_X4_Y23_N20 cycloneive_lcell_comb \ula_|i2c_loader_|Mux35~0 ( // Equation(s): -// \ula_|i2c_loader_|Mux35~0_combout = (\ula_|i2c_loader_|thisbyte [0] & (\ula_|i2c_loader_|thisbyte [2] & ((!\ula_|i2c_loader_|thisbyte [1]) # (!\ula_|i2c_loader_|thisbyte [3])))) +// \ula_|i2c_loader_|Mux35~0_combout = (\ula_|i2c_loader_|thisbyte [2] & (\ula_|i2c_loader_|thisbyte [0] & ((!\ula_|i2c_loader_|thisbyte [1]) # (!\ula_|i2c_loader_|thisbyte [3])))) - .dataa(\ula_|i2c_loader_|thisbyte [0]), + .dataa(\ula_|i2c_loader_|thisbyte [2]), .datab(\ula_|i2c_loader_|thisbyte [3]), .datac(\ula_|i2c_loader_|thisbyte [1]), - .datad(\ula_|i2c_loader_|thisbyte [2]), + .datad(\ula_|i2c_loader_|thisbyte [0]), .cin(gnd), .combout(\ula_|i2c_loader_|Mux35~0_combout ), .cout()); @@ -55065,135 +54832,186 @@ defparam \ula_|i2c_loader_|Mux35~0 .lut_mask = 16'h2A00; defparam \ula_|i2c_loader_|Mux35~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N30 +// Location: LCCOMB_X5_Y23_N12 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~13 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~13_combout = (!\ula_|i2c_loader_|thisbyte [2] & ((\ula_|i2c_loader_|thisbyte [4] & ((!\ula_|i2c_loader_|thisbyte [0]))) # (!\ula_|i2c_loader_|thisbyte [4] & (!\ula_|i2c_loader_|thisbyte [1] & \ula_|i2c_loader_|thisbyte [0])))) +// \ula_|i2c_loader_|shiftreg~13_combout = (!\ula_|i2c_loader_|thisbyte [2] & \ula_|i2c_loader_|thisbyte [4]) - .dataa(\ula_|i2c_loader_|thisbyte [4]), - .datab(\ula_|i2c_loader_|thisbyte [1]), - .datac(\ula_|i2c_loader_|thisbyte [0]), - .datad(\ula_|i2c_loader_|thisbyte [2]), + .dataa(\ula_|i2c_loader_|thisbyte [2]), + .datab(gnd), + .datac(\ula_|i2c_loader_|thisbyte [4]), + .datad(gnd), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg~13_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~13 .lut_mask = 16'h001A; +defparam \ula_|i2c_loader_|shiftreg~13 .lut_mask = 16'h5050; defparam \ula_|i2c_loader_|shiftreg~13 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N24 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~14 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~14_combout = (\ula_|i2c_loader_|thisbyte [4] & !\ula_|i2c_loader_|thisbyte [2]) - - .dataa(gnd), - .datab(gnd), - .datac(\ula_|i2c_loader_|thisbyte [4]), - .datad(\ula_|i2c_loader_|thisbyte [2]), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~14_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~14 .lut_mask = 16'h00F0; -defparam \ula_|i2c_loader_|shiftreg~14 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y23_N10 +// Location: LCCOMB_X5_Y23_N4 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~15 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~15_combout = (\ula_|i2c_loader_|shiftreg~13_combout ) # ((!\ula_|i2c_loader_|thisbyte [3] & (\ula_|i2c_loader_|thisbyte [0] & !\ula_|i2c_loader_|shiftreg~14_combout ))) +// \ula_|i2c_loader_|shiftreg~15_combout = (\ula_|i2c_loader_|thisbyte [2] & (((!\ula_|i2c_loader_|thisbyte [3])))) # (!\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte [1] & (\ula_|i2c_loader_|thisbyte [4]))) - .dataa(\ula_|i2c_loader_|shiftreg~13_combout ), - .datab(\ula_|i2c_loader_|thisbyte [3]), - .datac(\ula_|i2c_loader_|thisbyte [0]), - .datad(\ula_|i2c_loader_|shiftreg~14_combout ), + .dataa(\ula_|i2c_loader_|thisbyte [2]), + .datab(\ula_|i2c_loader_|thisbyte [1]), + .datac(\ula_|i2c_loader_|thisbyte [4]), + .datad(\ula_|i2c_loader_|thisbyte [3]), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg~15_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~15 .lut_mask = 16'hAABA; +defparam \ula_|i2c_loader_|shiftreg~15 .lut_mask = 16'h10BA; defparam \ula_|i2c_loader_|shiftreg~15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N12 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~24 ( +// Location: LCCOMB_X5_Y23_N10 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~16 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg[0]~24_combout = (!\ula_|i2c_loader_|thisbyte [3] & (!\ula_|i2c_loader_|state.Data~q & \ula_|i2c_loader_|thisbyte [0])) +// \ula_|i2c_loader_|shiftreg~16_combout = (\ula_|i2c_loader_|thisbyte [0] & (((\ula_|i2c_loader_|shiftreg~15_combout )))) # (!\ula_|i2c_loader_|thisbyte [0] & (!\ula_|i2c_loader_|shiftreg~13_combout & (\ula_|i2c_loader_|thisbyte [3]))) + + .dataa(\ula_|i2c_loader_|shiftreg~13_combout ), + .datab(\ula_|i2c_loader_|thisbyte [3]), + .datac(\ula_|i2c_loader_|shiftreg~15_combout ), + .datad(\ula_|i2c_loader_|thisbyte [0]), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~16_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~16 .lut_mask = 16'hF044; +defparam \ula_|i2c_loader_|shiftreg~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y23_N12 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~17 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~17_combout = (\ula_|i2c_loader_|thisbyte [0] & ((\ula_|i2c_loader_|thisbyte [4] & (!\ula_|i2c_loader_|thisbyte [1])) # (!\ula_|i2c_loader_|thisbyte [4] & ((!\ula_|i2c_loader_|thisbyte [3]))))) + + .dataa(\ula_|i2c_loader_|thisbyte [4]), + .datab(\ula_|i2c_loader_|thisbyte [0]), + .datac(\ula_|i2c_loader_|thisbyte [1]), + .datad(\ula_|i2c_loader_|thisbyte [3]), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~17_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~17 .lut_mask = 16'h084C; +defparam \ula_|i2c_loader_|shiftreg~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y23_N22 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~18 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~18_combout = ((\ula_|i2c_loader_|thisbyte [2] & ((!\ula_|i2c_loader_|thisbyte [0]))) # (!\ula_|i2c_loader_|thisbyte [2] & (\ula_|i2c_loader_|shiftreg~17_combout ))) # (!\ula_|i2c_loader_|shiftreg~4_combout ) + + .dataa(\ula_|i2c_loader_|shiftreg~17_combout ), + .datab(\ula_|i2c_loader_|thisbyte [2]), + .datac(\ula_|i2c_loader_|shiftreg~4_combout ), + .datad(\ula_|i2c_loader_|thisbyte [0]), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~18_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~18 .lut_mask = 16'h2FEF; +defparam \ula_|i2c_loader_|shiftreg~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y23_N14 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~20 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~20_combout = (\ula_|i2c_loader_|thisbyte [0] & ((\ula_|i2c_loader_|thisbyte [3] & (\ula_|i2c_loader_|thisbyte [2])) # (!\ula_|i2c_loader_|thisbyte [3] & (!\ula_|i2c_loader_|thisbyte [2] & !\ula_|i2c_loader_|thisbyte [4])))) + + .dataa(\ula_|i2c_loader_|thisbyte [0]), + .datab(\ula_|i2c_loader_|thisbyte [3]), + .datac(\ula_|i2c_loader_|thisbyte [2]), + .datad(\ula_|i2c_loader_|thisbyte [4]), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~20_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~20 .lut_mask = 16'h8082; +defparam \ula_|i2c_loader_|shiftreg~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y23_N24 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~21 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~21_combout = (\ula_|i2c_loader_|shiftreg~4_combout & ((\ula_|i2c_loader_|shiftreg~20_combout ) # ((\ula_|i2c_loader_|thisbyte [1] & !\ula_|i2c_loader_|thisbyte [0])))) + + .dataa(\ula_|i2c_loader_|shiftreg~4_combout ), + .datab(\ula_|i2c_loader_|shiftreg~20_combout ), + .datac(\ula_|i2c_loader_|thisbyte [1]), + .datad(\ula_|i2c_loader_|thisbyte [0]), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~21_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~21 .lut_mask = 16'h88A8; +defparam \ula_|i2c_loader_|shiftreg~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y23_N0 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~23 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg[0]~23_combout = (!\ula_|i2c_loader_|thisbyte [3] & (!\ula_|i2c_loader_|state.Data~q & \ula_|i2c_loader_|thisbyte [0])) .dataa(gnd), .datab(\ula_|i2c_loader_|thisbyte [3]), .datac(\ula_|i2c_loader_|state.Data~q ), .datad(\ula_|i2c_loader_|thisbyte [0]), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg[0]~24_combout ), + .combout(\ula_|i2c_loader_|shiftreg[0]~23_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[0]~24 .lut_mask = 16'h0300; -defparam \ula_|i2c_loader_|shiftreg[0]~24 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg[0]~23 .lut_mask = 16'h0300; +defparam \ula_|i2c_loader_|shiftreg[0]~23 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N14 +// Location: LCCOMB_X3_Y23_N30 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~6 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg[0]~6_combout = (!\ula_|i2c_loader_|phase [1] & (\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|state.Data~q )) +// \ula_|i2c_loader_|shiftreg[0]~6_combout = (\ula_|i2c_loader_|phase [1] & ((\ula_|i2c_loader_|state~24_combout ) # ((\ula_|i2c_loader_|state.Start~q )))) # (!\ula_|i2c_loader_|phase [1] & (((\ula_|i2c_loader_|state.Data~q )))) - .dataa(\ula_|i2c_loader_|phase [1]), - .datab(gnd), - .datac(\ula_|i2c_loader_|phase [0]), - .datad(\ula_|i2c_loader_|state.Data~q ), + .dataa(\ula_|i2c_loader_|state~24_combout ), + .datab(\ula_|i2c_loader_|state.Data~q ), + .datac(\ula_|i2c_loader_|state.Start~q ), + .datad(\ula_|i2c_loader_|phase [1]), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg[0]~6_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[0]~6 .lut_mask = 16'h5000; +defparam \ula_|i2c_loader_|shiftreg[0]~6 .lut_mask = 16'hFACC; defparam \ula_|i2c_loader_|shiftreg[0]~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N0 +// Location: LCCOMB_X3_Y23_N8 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~7 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg[0]~7_combout = (\ula_|i2c_loader_|shiftreg[0]~6_combout ) # ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Start~q ) # (\ula_|i2c_loader_|state~24_combout )))) +// \ula_|i2c_loader_|shiftreg[0]~7_combout = (\ula_|i2c_loader_|shiftreg[0]~6_combout & (\ula_|i2c_loader_|phase [0] & (!\ula_|i2c_loader_|WideAnd0~combout & \ula_|i2c_loader_|state.Idle~q ))) - .dataa(\ula_|i2c_loader_|state.Start~q ), - .datab(\ula_|i2c_loader_|Mux42~0_combout ), - .datac(\ula_|i2c_loader_|shiftreg[0]~6_combout ), - .datad(\ula_|i2c_loader_|state~24_combout ), + .dataa(\ula_|i2c_loader_|shiftreg[0]~6_combout ), + .datab(\ula_|i2c_loader_|phase [0]), + .datac(\ula_|i2c_loader_|WideAnd0~combout ), + .datad(\ula_|i2c_loader_|state.Idle~q ), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg[0]~7_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[0]~7 .lut_mask = 16'hFCF8; +defparam \ula_|i2c_loader_|shiftreg[0]~7 .lut_mask = 16'h0800; defparam \ula_|i2c_loader_|shiftreg[0]~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y24_N10 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~8 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg[0]~8_combout = (\ula_|i2c_loader_|state.Idle~q & (!\ula_|i2c_loader_|WideAnd0~combout & \ula_|i2c_loader_|shiftreg[0]~7_combout )) - - .dataa(gnd), - .datab(\ula_|i2c_loader_|state.Idle~q ), - .datac(\ula_|i2c_loader_|WideAnd0~combout ), - .datad(\ula_|i2c_loader_|shiftreg[0]~7_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg[0]~8_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[0]~8 .lut_mask = 16'h0C00; -defparam \ula_|i2c_loader_|shiftreg[0]~8 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X3_Y23_N13 +// Location: FF_X4_Y23_N1 dffeas \ula_|i2c_loader_|shiftreg[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|shiftreg[0]~24_combout ), + .d(\ula_|i2c_loader_|shiftreg[0]~23_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(\ula_|i2c_loader_|state.Start~q ), .sload(gnd), - .ena(\ula_|i2c_loader_|shiftreg[0]~8_combout ), + .ena(\ula_|i2c_loader_|shiftreg[0]~7_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [0]), @@ -55203,102 +55021,68 @@ defparam \ula_|i2c_loader_|shiftreg[0] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N26 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~21 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~21_combout = (\ula_|i2c_loader_|thisbyte [0] & ((\ula_|i2c_loader_|thisbyte [3] & ((\ula_|i2c_loader_|thisbyte [2]))) # (!\ula_|i2c_loader_|thisbyte [3] & (!\ula_|i2c_loader_|thisbyte [4] & !\ula_|i2c_loader_|thisbyte [2])))) - - .dataa(\ula_|i2c_loader_|thisbyte [4]), - .datab(\ula_|i2c_loader_|thisbyte [3]), - .datac(\ula_|i2c_loader_|thisbyte [0]), - .datad(\ula_|i2c_loader_|thisbyte [2]), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~21_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~21 .lut_mask = 16'hC010; -defparam \ula_|i2c_loader_|shiftreg~21 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y23_N28 +// Location: LCCOMB_X4_Y23_N28 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~22 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~22_combout = (\ula_|i2c_loader_|shiftreg~4_combout & ((\ula_|i2c_loader_|shiftreg~21_combout ) # ((\ula_|i2c_loader_|thisbyte [1] & !\ula_|i2c_loader_|thisbyte [0])))) +// \ula_|i2c_loader_|shiftreg~22_combout = (\ula_|i2c_loader_|shiftreg~21_combout ) # ((\ula_|i2c_loader_|state.Data~q & \ula_|i2c_loader_|shiftreg [0])) - .dataa(\ula_|i2c_loader_|shiftreg~21_combout ), - .datab(\ula_|i2c_loader_|shiftreg~4_combout ), - .datac(\ula_|i2c_loader_|thisbyte [1]), - .datad(\ula_|i2c_loader_|thisbyte [0]), + .dataa(gnd), + .datab(\ula_|i2c_loader_|shiftreg~21_combout ), + .datac(\ula_|i2c_loader_|state.Data~q ), + .datad(\ula_|i2c_loader_|shiftreg [0]), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg~22_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~22 .lut_mask = 16'h88C8; +defparam \ula_|i2c_loader_|shiftreg~22 .lut_mask = 16'hFCCC; defparam \ula_|i2c_loader_|shiftreg~22 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N22 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~23 ( +// Location: LCCOMB_X3_Y23_N10 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[6]~9 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~23_combout = (\ula_|i2c_loader_|shiftreg~22_combout ) # ((\ula_|i2c_loader_|shiftreg [0] & \ula_|i2c_loader_|state.Data~q )) +// \ula_|i2c_loader_|shiftreg[6]~9_combout = (\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|state.Start~q $ (!\ula_|i2c_loader_|phase [1])))) # (!\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|phase [1] & ((\ula_|i2c_loader_|state~24_combout +// ) # (\ula_|i2c_loader_|state.Start~q )))) - .dataa(\ula_|i2c_loader_|shiftreg [0]), - .datab(gnd), - .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|shiftreg~22_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~23_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~23 .lut_mask = 16'hFFA0; -defparam \ula_|i2c_loader_|shiftreg~23 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X2_Y24_N10 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[6]~10 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg[6]~10_combout = (\ula_|i2c_loader_|phase [1] & ((\ula_|i2c_loader_|state.Start~q ) # ((!\ula_|i2c_loader_|state.Data~q & \ula_|i2c_loader_|state~24_combout )))) # (!\ula_|i2c_loader_|phase [1] & (\ula_|i2c_loader_|state.Data~q -// & (!\ula_|i2c_loader_|state.Start~q ))) - - .dataa(\ula_|i2c_loader_|phase [1]), + .dataa(\ula_|i2c_loader_|state~24_combout ), .datab(\ula_|i2c_loader_|state.Data~q ), .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|state~24_combout ), + .datad(\ula_|i2c_loader_|phase [1]), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg[6]~9_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg[6]~9 .lut_mask = 16'hF20C; +defparam \ula_|i2c_loader_|shiftreg[6]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y23_N12 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[6]~10 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg[6]~10_combout = (\ula_|i2c_loader_|shiftreg[6]~9_combout & (\ula_|i2c_loader_|phase [0] & (!\ula_|i2c_loader_|WideAnd0~combout & \ula_|i2c_loader_|state.Idle~q ))) + + .dataa(\ula_|i2c_loader_|shiftreg[6]~9_combout ), + .datab(\ula_|i2c_loader_|phase [0]), + .datac(\ula_|i2c_loader_|WideAnd0~combout ), + .datad(\ula_|i2c_loader_|state.Idle~q ), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg[6]~10_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[6]~10 .lut_mask = 16'hA6A4; +defparam \ula_|i2c_loader_|shiftreg[6]~10 .lut_mask = 16'h0800; defparam \ula_|i2c_loader_|shiftreg[6]~10 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N24 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[6]~11 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg[6]~11_combout = (\ula_|i2c_loader_|phase [0] & (!\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|state.Idle~q & \ula_|i2c_loader_|shiftreg[6]~10_combout ))) - - .dataa(\ula_|i2c_loader_|phase [0]), - .datab(\ula_|i2c_loader_|WideAnd0~combout ), - .datac(\ula_|i2c_loader_|state.Idle~q ), - .datad(\ula_|i2c_loader_|shiftreg[6]~10_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg[6]~11_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg[6]~11 .lut_mask = 16'h2000; -defparam \ula_|i2c_loader_|shiftreg[6]~11 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X3_Y23_N23 +// Location: FF_X4_Y23_N29 dffeas \ula_|i2c_loader_|shiftreg[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|shiftreg~23_combout ), + .d(\ula_|i2c_loader_|shiftreg~22_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2c_loader_|shiftreg[6]~11_combout ), + .ena(\ula_|i2c_loader_|shiftreg[6]~10_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [1]), @@ -55308,67 +55092,33 @@ defparam \ula_|i2c_loader_|shiftreg[1] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N4 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~18 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~18_combout = (\ula_|i2c_loader_|thisbyte [0] & ((\ula_|i2c_loader_|thisbyte [4] & ((!\ula_|i2c_loader_|thisbyte [1]))) # (!\ula_|i2c_loader_|thisbyte [4] & (!\ula_|i2c_loader_|thisbyte [3])))) - - .dataa(\ula_|i2c_loader_|thisbyte [4]), - .datab(\ula_|i2c_loader_|thisbyte [3]), - .datac(\ula_|i2c_loader_|thisbyte [0]), - .datad(\ula_|i2c_loader_|thisbyte [1]), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~18_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~18 .lut_mask = 16'h10B0; -defparam \ula_|i2c_loader_|shiftreg~18 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y23_N24 +// Location: LCCOMB_X4_Y23_N2 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~19 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~19_combout = ((\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte [0])) # (!\ula_|i2c_loader_|thisbyte [2] & ((\ula_|i2c_loader_|shiftreg~18_combout )))) # (!\ula_|i2c_loader_|shiftreg~4_combout ) +// \ula_|i2c_loader_|shiftreg~19_combout = (\ula_|i2c_loader_|shiftreg~18_combout & ((\ula_|i2c_loader_|shiftreg [1]) # (!\ula_|i2c_loader_|state.Data~q ))) - .dataa(\ula_|i2c_loader_|thisbyte [0]), - .datab(\ula_|i2c_loader_|thisbyte [2]), - .datac(\ula_|i2c_loader_|shiftreg~18_combout ), - .datad(\ula_|i2c_loader_|shiftreg~4_combout ), + .dataa(\ula_|i2c_loader_|shiftreg~18_combout ), + .datab(\ula_|i2c_loader_|shiftreg [1]), + .datac(\ula_|i2c_loader_|state.Data~q ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2c_loader_|shiftreg~19_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~19 .lut_mask = 16'h74FF; +defparam \ula_|i2c_loader_|shiftreg~19 .lut_mask = 16'h8A8A; defparam \ula_|i2c_loader_|shiftreg~19 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N2 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~20 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~20_combout = (\ula_|i2c_loader_|shiftreg~19_combout & ((\ula_|i2c_loader_|shiftreg [1]) # (!\ula_|i2c_loader_|state.Data~q ))) - - .dataa(\ula_|i2c_loader_|shiftreg [1]), - .datab(gnd), - .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|shiftreg~19_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~20_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~20 .lut_mask = 16'hAF00; -defparam \ula_|i2c_loader_|shiftreg~20 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X3_Y23_N3 +// Location: FF_X4_Y23_N3 dffeas \ula_|i2c_loader_|shiftreg[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|shiftreg~20_combout ), + .d(\ula_|i2c_loader_|shiftreg~19_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2c_loader_|shiftreg[6]~11_combout ), + .ena(\ula_|i2c_loader_|shiftreg[6]~10_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [2]), @@ -55378,67 +55128,33 @@ defparam \ula_|i2c_loader_|shiftreg[2] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N28 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~16 ( +// Location: LCCOMB_X4_Y23_N8 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~25 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~16_combout = (\ula_|i2c_loader_|thisbyte [2] & (((!\ula_|i2c_loader_|thisbyte [3])))) # (!\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte [1] & (\ula_|i2c_loader_|thisbyte [4]))) - - .dataa(\ula_|i2c_loader_|thisbyte [2]), - .datab(\ula_|i2c_loader_|thisbyte [1]), - .datac(\ula_|i2c_loader_|thisbyte [4]), - .datad(\ula_|i2c_loader_|thisbyte [3]), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~16_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~16 .lut_mask = 16'h10BA; -defparam \ula_|i2c_loader_|shiftreg~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y23_N20 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~17 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~17_combout = (\ula_|i2c_loader_|thisbyte [0] & (((\ula_|i2c_loader_|shiftreg~16_combout )))) # (!\ula_|i2c_loader_|thisbyte [0] & (\ula_|i2c_loader_|thisbyte [3] & ((!\ula_|i2c_loader_|shiftreg~14_combout )))) - - .dataa(\ula_|i2c_loader_|thisbyte [0]), - .datab(\ula_|i2c_loader_|thisbyte [3]), - .datac(\ula_|i2c_loader_|shiftreg~16_combout ), - .datad(\ula_|i2c_loader_|shiftreg~14_combout ), - .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~17_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~17 .lut_mask = 16'hA0E4; -defparam \ula_|i2c_loader_|shiftreg~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X3_Y23_N6 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~26 ( -// Equation(s): -// \ula_|i2c_loader_|shiftreg~26_combout = (\ula_|i2c_loader_|state.Data~q & (((\ula_|i2c_loader_|shiftreg [2])))) # (!\ula_|i2c_loader_|state.Data~q & (!\ula_|i2c_loader_|state.Start~q & ((\ula_|i2c_loader_|shiftreg~17_combout )))) +// \ula_|i2c_loader_|shiftreg~25_combout = (\ula_|i2c_loader_|state.Data~q & (((\ula_|i2c_loader_|shiftreg [2])))) # (!\ula_|i2c_loader_|state.Data~q & (!\ula_|i2c_loader_|state.Start~q & (\ula_|i2c_loader_|shiftreg~16_combout ))) .dataa(\ula_|i2c_loader_|state.Start~q ), - .datab(\ula_|i2c_loader_|shiftreg [2]), - .datac(\ula_|i2c_loader_|state.Data~q ), - .datad(\ula_|i2c_loader_|shiftreg~17_combout ), + .datab(\ula_|i2c_loader_|state.Data~q ), + .datac(\ula_|i2c_loader_|shiftreg~16_combout ), + .datad(\ula_|i2c_loader_|shiftreg [2]), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~26_combout ), + .combout(\ula_|i2c_loader_|shiftreg~25_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~26 .lut_mask = 16'hC5C0; -defparam \ula_|i2c_loader_|shiftreg~26 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg~25 .lut_mask = 16'hDC10; +defparam \ula_|i2c_loader_|shiftreg~25 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y23_N7 +// Location: FF_X4_Y23_N9 dffeas \ula_|i2c_loader_|shiftreg[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|shiftreg~26_combout ), + .d(\ula_|i2c_loader_|shiftreg~25_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2c_loader_|shiftreg[6]~11_combout ), + .ena(\ula_|i2c_loader_|shiftreg[6]~10_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [3]), @@ -55448,33 +55164,67 @@ defparam \ula_|i2c_loader_|shiftreg[3] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N0 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~25 ( +// Location: LCCOMB_X5_Y23_N14 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~12 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~25_combout = (\ula_|i2c_loader_|state.Data~q & (((\ula_|i2c_loader_|shiftreg [3])))) # (!\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|shiftreg~15_combout ) # ((\ula_|i2c_loader_|state.Start~q )))) +// \ula_|i2c_loader_|shiftreg~12_combout = (!\ula_|i2c_loader_|thisbyte [2] & ((\ula_|i2c_loader_|thisbyte [4] & ((!\ula_|i2c_loader_|thisbyte [0]))) # (!\ula_|i2c_loader_|thisbyte [4] & (!\ula_|i2c_loader_|thisbyte [1] & \ula_|i2c_loader_|thisbyte [0])))) - .dataa(\ula_|i2c_loader_|shiftreg~15_combout ), - .datab(\ula_|i2c_loader_|state.Data~q ), - .datac(\ula_|i2c_loader_|state.Start~q ), - .datad(\ula_|i2c_loader_|shiftreg [3]), + .dataa(\ula_|i2c_loader_|thisbyte [2]), + .datab(\ula_|i2c_loader_|thisbyte [1]), + .datac(\ula_|i2c_loader_|thisbyte [4]), + .datad(\ula_|i2c_loader_|thisbyte [0]), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~25_combout ), + .combout(\ula_|i2c_loader_|shiftreg~12_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~25 .lut_mask = 16'hFE32; -defparam \ula_|i2c_loader_|shiftreg~25 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg~12 .lut_mask = 16'h0150; +defparam \ula_|i2c_loader_|shiftreg~12 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X2_Y23_N1 +// Location: LCCOMB_X5_Y23_N6 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~14 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~14_combout = (\ula_|i2c_loader_|shiftreg~12_combout ) # ((!\ula_|i2c_loader_|shiftreg~13_combout & (!\ula_|i2c_loader_|thisbyte [3] & \ula_|i2c_loader_|thisbyte [0]))) + + .dataa(\ula_|i2c_loader_|shiftreg~13_combout ), + .datab(\ula_|i2c_loader_|thisbyte [3]), + .datac(\ula_|i2c_loader_|shiftreg~12_combout ), + .datad(\ula_|i2c_loader_|thisbyte [0]), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~14_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~14 .lut_mask = 16'hF1F0; +defparam \ula_|i2c_loader_|shiftreg~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y23_N6 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~24 ( +// Equation(s): +// \ula_|i2c_loader_|shiftreg~24_combout = (\ula_|i2c_loader_|state.Data~q & (((\ula_|i2c_loader_|shiftreg [3])))) # (!\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|state.Start~q ) # ((\ula_|i2c_loader_|shiftreg~14_combout )))) + + .dataa(\ula_|i2c_loader_|state.Start~q ), + .datab(\ula_|i2c_loader_|shiftreg [3]), + .datac(\ula_|i2c_loader_|state.Data~q ), + .datad(\ula_|i2c_loader_|shiftreg~14_combout ), + .cin(gnd), + .combout(\ula_|i2c_loader_|shiftreg~24_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2c_loader_|shiftreg~24 .lut_mask = 16'hCFCA; +defparam \ula_|i2c_loader_|shiftreg~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X4_Y23_N7 dffeas \ula_|i2c_loader_|shiftreg[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|shiftreg~25_combout ), + .d(\ula_|i2c_loader_|shiftreg~24_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(\ula_|i2c_loader_|shiftreg[6]~11_combout ), + .ena(\ula_|i2c_loader_|shiftreg[6]~10_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [4]), @@ -55484,33 +55234,33 @@ defparam \ula_|i2c_loader_|shiftreg[4] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y24_N4 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~12 ( +// Location: LCCOMB_X3_Y23_N24 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~11 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~12_combout = (\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|shiftreg [4]))) # (!\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|Mux35~0_combout )) +// \ula_|i2c_loader_|shiftreg~11_combout = (\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|shiftreg [4]))) # (!\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|Mux35~0_combout )) .dataa(\ula_|i2c_loader_|Mux35~0_combout ), .datab(\ula_|i2c_loader_|state.Data~q ), .datac(gnd), .datad(\ula_|i2c_loader_|shiftreg [4]), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~12_combout ), + .combout(\ula_|i2c_loader_|shiftreg~11_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~12 .lut_mask = 16'hEE22; -defparam \ula_|i2c_loader_|shiftreg~12 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg~11 .lut_mask = 16'hEE22; +defparam \ula_|i2c_loader_|shiftreg~11 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X2_Y24_N5 +// Location: FF_X3_Y23_N25 dffeas \ula_|i2c_loader_|shiftreg[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|shiftreg~12_combout ), + .d(\ula_|i2c_loader_|shiftreg~11_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(gnd), .sload(\ula_|i2c_loader_|state.Start~q ), - .ena(\ula_|i2c_loader_|shiftreg[6]~11_combout ), + .ena(\ula_|i2c_loader_|shiftreg[6]~10_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [5]), @@ -55520,33 +55270,33 @@ defparam \ula_|i2c_loader_|shiftreg[5] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N18 -cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~9 ( +// Location: LCCOMB_X4_Y23_N18 +cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~8 ( // Equation(s): -// \ula_|i2c_loader_|shiftreg~9_combout = (\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|shiftreg [5])) # (!\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|Mux35~0_combout ))) +// \ula_|i2c_loader_|shiftreg~8_combout = (\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|shiftreg [5])) # (!\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|Mux35~0_combout ))) .dataa(gnd), .datab(\ula_|i2c_loader_|shiftreg [5]), .datac(\ula_|i2c_loader_|state.Data~q ), .datad(\ula_|i2c_loader_|Mux35~0_combout ), .cin(gnd), - .combout(\ula_|i2c_loader_|shiftreg~9_combout ), + .combout(\ula_|i2c_loader_|shiftreg~8_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|shiftreg~9 .lut_mask = 16'hCFC0; -defparam \ula_|i2c_loader_|shiftreg~9 .sum_lutc_input = "datac"; +defparam \ula_|i2c_loader_|shiftreg~8 .lut_mask = 16'hCFC0; +defparam \ula_|i2c_loader_|shiftreg~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y23_N19 +// Location: FF_X4_Y23_N19 dffeas \ula_|i2c_loader_|shiftreg[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2c_loader_|shiftreg~9_combout ), + .d(\ula_|i2c_loader_|shiftreg~8_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), .sclr(\ula_|i2c_loader_|state.Start~q ), .sload(gnd), - .ena(\ula_|i2c_loader_|shiftreg[6]~11_combout ), + .ena(\ula_|i2c_loader_|shiftreg[6]~10_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [6]), @@ -55556,7 +55306,7 @@ defparam \ula_|i2c_loader_|shiftreg[6] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X3_Y23_N4 +// Location: LCCOMB_X4_Y23_N16 cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[7]~5 ( // Equation(s): // \ula_|i2c_loader_|shiftreg[7]~5_combout = (\ula_|i2c_loader_|state.Data~q & \ula_|i2c_loader_|shiftreg [6]) @@ -55573,7 +55323,7 @@ defparam \ula_|i2c_loader_|shiftreg[7]~5 .lut_mask = 16'hF000; defparam \ula_|i2c_loader_|shiftreg[7]~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X3_Y23_N5 +// Location: FF_X4_Y23_N17 dffeas \ula_|i2c_loader_|shiftreg[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2c_loader_|shiftreg[7]~5_combout ), @@ -55582,7 +55332,7 @@ dffeas \ula_|i2c_loader_|shiftreg[7] ( .aload(gnd), .sclr(\ula_|i2c_loader_|state.Start~q ), .sload(gnd), - .ena(\ula_|i2c_loader_|shiftreg[0]~8_combout ), + .ena(\ula_|i2c_loader_|shiftreg[0]~7_combout ), .devclrn(devclrn), .devpor(devpor), .q(\ula_|i2c_loader_|shiftreg [7]), @@ -55592,25 +55342,25 @@ defparam \ula_|i2c_loader_|shiftreg[7] .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|shiftreg[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X2_Y23_N12 +// Location: LCCOMB_X1_Y23_N26 cycloneive_lcell_comb \ula_|i2c_loader_|sda_out~0 ( // Equation(s): -// \ula_|i2c_loader_|sda_out~0_combout = (\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|shiftreg [7]))) # (!\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|state.Ack~q )))) # (!\ula_|i2c_loader_|state.Data~q & +// \ula_|i2c_loader_|sda_out~0_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|shiftreg [7])) # (!\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|state.Ack~q ))))) # (!\ula_|i2c_loader_|phase [0] & // (((\ula_|i2c_loader_|state.Ack~q )))) - .dataa(\ula_|i2c_loader_|state.Data~q ), - .datab(\ula_|i2c_loader_|phase [0]), - .datac(\ula_|i2c_loader_|state.Ack~q ), - .datad(\ula_|i2c_loader_|shiftreg [7]), + .dataa(\ula_|i2c_loader_|shiftreg [7]), + .datab(\ula_|i2c_loader_|state.Ack~q ), + .datac(\ula_|i2c_loader_|phase [0]), + .datad(\ula_|i2c_loader_|state.Data~q ), .cin(gnd), .combout(\ula_|i2c_loader_|sda_out~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|sda_out~0 .lut_mask = 16'hF870; +defparam \ula_|i2c_loader_|sda_out~0 .lut_mask = 16'hACCC; defparam \ula_|i2c_loader_|sda_out~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N6 +// Location: LCCOMB_X1_Y23_N20 cycloneive_lcell_comb \ula_|i2c_loader_|sda_out~1 ( // Equation(s): // \ula_|i2c_loader_|sda_out~1_combout = (\ula_|i2c_loader_|sda_out~0_combout & ((\ula_|i2c_loader_|phase [0]) # ((\ula_|i2c_loader_|shiftreg~4_combout & !\I2C_SDAT~input_o )))) @@ -55627,55 +55377,55 @@ defparam \ula_|i2c_loader_|sda_out~1 .lut_mask = 16'hC0E0; defparam \ula_|i2c_loader_|sda_out~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N8 +// Location: LCCOMB_X1_Y23_N14 cycloneive_lcell_comb \ula_|i2c_loader_|sda_out~2 ( // Equation(s): // \ula_|i2c_loader_|sda_out~2_combout = (!\ula_|i2c_loader_|sda_out~_Duplicate_1_q & ((\ula_|i2c_loader_|phase [0]) # ((\ula_|i2c_loader_|phase [1] & !\ula_|i2c_loader_|sda_out~1_combout )))) .dataa(\ula_|i2c_loader_|sda_out~_Duplicate_1_q ), - .datab(\ula_|i2c_loader_|phase [0]), - .datac(\ula_|i2c_loader_|phase [1]), + .datab(\ula_|i2c_loader_|phase [1]), + .datac(\ula_|i2c_loader_|phase [0]), .datad(\ula_|i2c_loader_|sda_out~1_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|sda_out~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|sda_out~2 .lut_mask = 16'h4454; +defparam \ula_|i2c_loader_|sda_out~2 .lut_mask = 16'h5054; defparam \ula_|i2c_loader_|sda_out~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N2 +// Location: LCCOMB_X1_Y23_N28 cycloneive_lcell_comb \ula_|i2c_loader_|sda_out~3 ( // Equation(s): -// \ula_|i2c_loader_|sda_out~3_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|phase [1] & (\ula_|i2c_loader_|sda_out~_Duplicate_1_q )) # (!\ula_|i2c_loader_|phase [1] & ((!\ula_|i2c_loader_|sda_out~1_combout ))))) # (!\ula_|i2c_loader_|phase -// [0] & ((\ula_|i2c_loader_|sda_out~_Duplicate_1_q ) # ((\ula_|i2c_loader_|phase [1] & \ula_|i2c_loader_|sda_out~1_combout )))) +// \ula_|i2c_loader_|sda_out~3_combout = (\ula_|i2c_loader_|phase [1] & ((\ula_|i2c_loader_|sda_out~_Duplicate_1_q ) # ((!\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|sda_out~1_combout )))) # (!\ula_|i2c_loader_|phase [1] & ((\ula_|i2c_loader_|phase [0] +// & ((!\ula_|i2c_loader_|sda_out~1_combout ))) # (!\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|sda_out~_Duplicate_1_q )))) .dataa(\ula_|i2c_loader_|sda_out~_Duplicate_1_q ), - .datab(\ula_|i2c_loader_|phase [0]), - .datac(\ula_|i2c_loader_|phase [1]), + .datab(\ula_|i2c_loader_|phase [1]), + .datac(\ula_|i2c_loader_|phase [0]), .datad(\ula_|i2c_loader_|sda_out~1_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|sda_out~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|sda_out~3 .lut_mask = 16'hB2AE; +defparam \ula_|i2c_loader_|sda_out~3 .lut_mask = 16'h8EBA; defparam \ula_|i2c_loader_|sda_out~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X1_Y23_N22 +// Location: LCCOMB_X1_Y23_N12 cycloneive_lcell_comb \ula_|i2c_loader_|sda_out~4 ( // Equation(s): // \ula_|i2c_loader_|sda_out~4_combout = (\ula_|i2c_loader_|state.Start~q & (((!\ula_|i2c_loader_|sda_out~2_combout )))) # (!\ula_|i2c_loader_|state.Start~q & (!\ula_|i2c_loader_|scl_out~0_combout & ((\ula_|i2c_loader_|sda_out~3_combout )))) - .dataa(\ula_|i2c_loader_|state.Start~q ), - .datab(\ula_|i2c_loader_|scl_out~0_combout ), + .dataa(\ula_|i2c_loader_|scl_out~0_combout ), + .datab(\ula_|i2c_loader_|state.Start~q ), .datac(\ula_|i2c_loader_|sda_out~2_combout ), .datad(\ula_|i2c_loader_|sda_out~3_combout ), .cin(gnd), .combout(\ula_|i2c_loader_|sda_out~4_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2c_loader_|sda_out~4 .lut_mask = 16'h1B0A; +defparam \ula_|i2c_loader_|sda_out~4 .lut_mask = 16'h1D0C; defparam \ula_|i2c_loader_|sda_out~4 .sum_lutc_input = "datac"; // synopsys translate_on @@ -55698,7 +55448,7 @@ defparam \ula_|i2c_loader_|sda_out .is_wysiwyg = "true"; defparam \ula_|i2c_loader_|sda_out .power_up = "high"; // synopsys translate_on -// Location: LCCOMB_X27_Y23_N16 +// Location: LCCOMB_X25_Y32_N20 cycloneive_lcell_comb \ula_|i2s_intf_|mclk_r~0 ( // Equation(s): // \ula_|i2s_intf_|mclk_r~0_combout = !\ula_|i2s_intf_|mclk_r~_Duplicate_1_q @@ -55715,7 +55465,7 @@ defparam \ula_|i2s_intf_|mclk_r~0 .lut_mask = 16'h0F0F; defparam \ula_|i2s_intf_|mclk_r~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X27_Y23_N17 +// Location: FF_X25_Y32_N21 dffeas \ula_|i2s_intf_|mclk_r~_Duplicate_1 ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|mclk_r~0_combout ), @@ -55753,7 +55503,7 @@ defparam \ula_|i2s_intf_|mclk_r .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|mclk_r .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N6 +// Location: LCCOMB_X24_Y32_N8 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~1 ( // Equation(s): // \ula_|i2s_intf_|Add0~1_cout = CARRY(!\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ) @@ -55770,25 +55520,25 @@ defparam \ula_|i2s_intf_|Add0~1 .lut_mask = 16'h0055; defparam \ula_|i2s_intf_|Add0~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N8 +// Location: LCCOMB_X24_Y32_N10 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~2 ( // Equation(s): // \ula_|i2s_intf_|Add0~2_combout = (\ula_|i2s_intf_|lrdivider [1] & (\ula_|i2s_intf_|Add0~1_cout & VCC)) # (!\ula_|i2s_intf_|lrdivider [1] & (!\ula_|i2s_intf_|Add0~1_cout )) // \ula_|i2s_intf_|Add0~3 = CARRY((!\ula_|i2s_intf_|lrdivider [1] & !\ula_|i2s_intf_|Add0~1_cout )) - .dataa(gnd), - .datab(\ula_|i2s_intf_|lrdivider [1]), + .dataa(\ula_|i2s_intf_|lrdivider [1]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\ula_|i2s_intf_|Add0~1_cout ), .combout(\ula_|i2s_intf_|Add0~2_combout ), .cout(\ula_|i2s_intf_|Add0~3 )); // synopsys translate_off -defparam \ula_|i2s_intf_|Add0~2 .lut_mask = 16'hC303; +defparam \ula_|i2s_intf_|Add0~2 .lut_mask = 16'hA505; defparam \ula_|i2s_intf_|Add0~2 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N28 +// Location: LCCOMB_X23_Y32_N10 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider~2 ( // Equation(s): // \ula_|i2s_intf_|lrdivider~2_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|Add0~2_combout ) @@ -55805,7 +55555,7 @@ defparam \ula_|i2s_intf_|lrdivider~2 .lut_mask = 16'h5050; defparam \ula_|i2s_intf_|lrdivider~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X29_Y23_N29 +// Location: FF_X23_Y32_N11 dffeas \ula_|i2s_intf_|lrdivider[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider~2_combout ), @@ -55824,42 +55574,42 @@ defparam \ula_|i2s_intf_|lrdivider[1] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N10 +// Location: LCCOMB_X24_Y32_N12 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~4 ( // Equation(s): // \ula_|i2s_intf_|Add0~4_combout = (\ula_|i2s_intf_|lrdivider [2] & (\ula_|i2s_intf_|Add0~3 $ (GND))) # (!\ula_|i2s_intf_|lrdivider [2] & ((GND) # (!\ula_|i2s_intf_|Add0~3 ))) // \ula_|i2s_intf_|Add0~5 = CARRY((!\ula_|i2s_intf_|Add0~3 ) # (!\ula_|i2s_intf_|lrdivider [2])) - .dataa(\ula_|i2s_intf_|lrdivider [2]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|i2s_intf_|lrdivider [2]), .datac(gnd), .datad(vcc), .cin(\ula_|i2s_intf_|Add0~3 ), .combout(\ula_|i2s_intf_|Add0~4_combout ), .cout(\ula_|i2s_intf_|Add0~5 )); // synopsys translate_off -defparam \ula_|i2s_intf_|Add0~4 .lut_mask = 16'hA55F; +defparam \ula_|i2s_intf_|Add0~4 .lut_mask = 16'hC33F; defparam \ula_|i2s_intf_|Add0~4 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X30_Y23_N6 +// Location: LCCOMB_X23_Y32_N22 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[2]~8 ( // Equation(s): // \ula_|i2s_intf_|lrdivider[2]~8_combout = !\ula_|i2s_intf_|Add0~4_combout .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|Add0~4_combout ), + .datac(\ula_|i2s_intf_|Add0~4_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|lrdivider[2]~8_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[2]~8 .lut_mask = 16'h00FF; +defparam \ula_|i2s_intf_|lrdivider[2]~8 .lut_mask = 16'h0F0F; defparam \ula_|i2s_intf_|lrdivider[2]~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y23_N7 +// Location: FF_X23_Y32_N23 dffeas \ula_|i2s_intf_|lrdivider[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider[2]~8_combout ), @@ -55878,7 +55628,7 @@ defparam \ula_|i2s_intf_|lrdivider[2] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N12 +// Location: LCCOMB_X24_Y32_N14 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~6 ( // Equation(s): // \ula_|i2s_intf_|Add0~6_combout = (\ula_|i2s_intf_|lrdivider [3] & (!\ula_|i2s_intf_|Add0~5 )) # (!\ula_|i2s_intf_|lrdivider [3] & (\ula_|i2s_intf_|Add0~5 & VCC)) @@ -55896,24 +55646,24 @@ defparam \ula_|i2s_intf_|Add0~6 .lut_mask = 16'h3C0C; defparam \ula_|i2s_intf_|Add0~6 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X28_Y23_N6 +// Location: LCCOMB_X23_Y32_N4 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[3]~7 ( // Equation(s): // \ula_|i2s_intf_|lrdivider[3]~7_combout = !\ula_|i2s_intf_|Add0~6_combout .dataa(gnd), .datab(gnd), - .datac(\ula_|i2s_intf_|Add0~6_combout ), - .datad(gnd), + .datac(gnd), + .datad(\ula_|i2s_intf_|Add0~6_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|lrdivider[3]~7_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[3]~7 .lut_mask = 16'h0F0F; +defparam \ula_|i2s_intf_|lrdivider[3]~7 .lut_mask = 16'h00FF; defparam \ula_|i2s_intf_|lrdivider[3]~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y23_N7 +// Location: FF_X23_Y32_N5 dffeas \ula_|i2s_intf_|lrdivider[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider[3]~7_combout ), @@ -55932,42 +55682,42 @@ defparam \ula_|i2s_intf_|lrdivider[3] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N14 +// Location: LCCOMB_X24_Y32_N16 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~8 ( // Equation(s): // \ula_|i2s_intf_|Add0~8_combout = (\ula_|i2s_intf_|lrdivider [4] & ((GND) # (!\ula_|i2s_intf_|Add0~7 ))) # (!\ula_|i2s_intf_|lrdivider [4] & (\ula_|i2s_intf_|Add0~7 $ (GND))) // \ula_|i2s_intf_|Add0~9 = CARRY((\ula_|i2s_intf_|lrdivider [4]) # (!\ula_|i2s_intf_|Add0~7 )) - .dataa(gnd), - .datab(\ula_|i2s_intf_|lrdivider [4]), + .dataa(\ula_|i2s_intf_|lrdivider [4]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\ula_|i2s_intf_|Add0~7 ), .combout(\ula_|i2s_intf_|Add0~8_combout ), .cout(\ula_|i2s_intf_|Add0~9 )); // synopsys translate_off -defparam \ula_|i2s_intf_|Add0~8 .lut_mask = 16'h3CCF; +defparam \ula_|i2s_intf_|Add0~8 .lut_mask = 16'h5AAF; defparam \ula_|i2s_intf_|Add0~8 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N4 +// Location: LCCOMB_X23_Y32_N16 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider~1 ( // Equation(s): // \ula_|i2s_intf_|lrdivider~1_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|Add0~8_combout ) - .dataa(\ula_|i2s_intf_|Equal0~2_combout ), + .dataa(gnd), .datab(gnd), - .datac(\ula_|i2s_intf_|Add0~8_combout ), - .datad(gnd), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|Add0~8_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|lrdivider~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider~1 .lut_mask = 16'h5050; +defparam \ula_|i2s_intf_|lrdivider~1 .lut_mask = 16'h0F00; defparam \ula_|i2s_intf_|lrdivider~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X29_Y23_N5 +// Location: FF_X23_Y32_N17 dffeas \ula_|i2s_intf_|lrdivider[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider~1_combout ), @@ -55986,25 +55736,25 @@ defparam \ula_|i2s_intf_|lrdivider[4] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N16 +// Location: LCCOMB_X24_Y32_N18 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~10 ( // Equation(s): // \ula_|i2s_intf_|Add0~10_combout = (\ula_|i2s_intf_|lrdivider [5] & (!\ula_|i2s_intf_|Add0~9 )) # (!\ula_|i2s_intf_|lrdivider [5] & (\ula_|i2s_intf_|Add0~9 & VCC)) // \ula_|i2s_intf_|Add0~11 = CARRY((\ula_|i2s_intf_|lrdivider [5] & !\ula_|i2s_intf_|Add0~9 )) - .dataa(gnd), - .datab(\ula_|i2s_intf_|lrdivider [5]), + .dataa(\ula_|i2s_intf_|lrdivider [5]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\ula_|i2s_intf_|Add0~9 ), .combout(\ula_|i2s_intf_|Add0~10_combout ), .cout(\ula_|i2s_intf_|Add0~11 )); // synopsys translate_off -defparam \ula_|i2s_intf_|Add0~10 .lut_mask = 16'h3C0C; +defparam \ula_|i2s_intf_|Add0~10 .lut_mask = 16'h5A0A; defparam \ula_|i2s_intf_|Add0~10 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N2 +// Location: LCCOMB_X23_Y32_N14 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[5]~6 ( // Equation(s): // \ula_|i2s_intf_|lrdivider[5]~6_combout = !\ula_|i2s_intf_|Add0~10_combout @@ -56021,7 +55771,7 @@ defparam \ula_|i2s_intf_|lrdivider[5]~6 .lut_mask = 16'h00FF; defparam \ula_|i2s_intf_|lrdivider[5]~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X29_Y23_N3 +// Location: FF_X23_Y32_N15 dffeas \ula_|i2s_intf_|lrdivider[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider[5]~6_combout ), @@ -56040,24 +55790,24 @@ defparam \ula_|i2s_intf_|lrdivider[5] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N26 +// Location: LCCOMB_X24_Y32_N0 cycloneive_lcell_comb \ula_|i2s_intf_|Equal0~1 ( // Equation(s): -// \ula_|i2s_intf_|Equal0~1_combout = (\ula_|i2s_intf_|lrdivider [2] & (!\ula_|i2s_intf_|lrdivider [4] & (\ula_|i2s_intf_|lrdivider [3] & \ula_|i2s_intf_|lrdivider [5]))) +// \ula_|i2s_intf_|Equal0~1_combout = (!\ula_|i2s_intf_|lrdivider [4] & (\ula_|i2s_intf_|lrdivider [2] & (\ula_|i2s_intf_|lrdivider [3] & \ula_|i2s_intf_|lrdivider [5]))) - .dataa(\ula_|i2s_intf_|lrdivider [2]), - .datab(\ula_|i2s_intf_|lrdivider [4]), + .dataa(\ula_|i2s_intf_|lrdivider [4]), + .datab(\ula_|i2s_intf_|lrdivider [2]), .datac(\ula_|i2s_intf_|lrdivider [3]), .datad(\ula_|i2s_intf_|lrdivider [5]), .cin(gnd), .combout(\ula_|i2s_intf_|Equal0~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|Equal0~1 .lut_mask = 16'h2000; +defparam \ula_|i2s_intf_|Equal0~1 .lut_mask = 16'h4000; defparam \ula_|i2s_intf_|Equal0~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N18 +// Location: LCCOMB_X24_Y32_N20 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~12 ( // Equation(s): // \ula_|i2s_intf_|Add0~12_combout = (\ula_|i2s_intf_|lrdivider [6] & (\ula_|i2s_intf_|Add0~11 $ (GND))) # (!\ula_|i2s_intf_|lrdivider [6] & ((GND) # (!\ula_|i2s_intf_|Add0~11 ))) @@ -56075,24 +55825,24 @@ defparam \ula_|i2s_intf_|Add0~12 .lut_mask = 16'hA55F; defparam \ula_|i2s_intf_|Add0~12 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X28_Y23_N26 +// Location: LCCOMB_X23_Y32_N0 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[6]~5 ( // Equation(s): // \ula_|i2s_intf_|lrdivider[6]~5_combout = !\ula_|i2s_intf_|Add0~12_combout .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|Add0~12_combout ), + .datac(\ula_|i2s_intf_|Add0~12_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|lrdivider[6]~5_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[6]~5 .lut_mask = 16'h00FF; +defparam \ula_|i2s_intf_|lrdivider[6]~5 .lut_mask = 16'h0F0F; defparam \ula_|i2s_intf_|lrdivider[6]~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y23_N27 +// Location: FF_X23_Y32_N1 dffeas \ula_|i2s_intf_|lrdivider[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider[6]~5_combout ), @@ -56111,42 +55861,42 @@ defparam \ula_|i2s_intf_|lrdivider[6] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N20 +// Location: LCCOMB_X24_Y32_N22 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~14 ( // Equation(s): // \ula_|i2s_intf_|Add0~14_combout = (\ula_|i2s_intf_|lrdivider [7] & (!\ula_|i2s_intf_|Add0~13 )) # (!\ula_|i2s_intf_|lrdivider [7] & (\ula_|i2s_intf_|Add0~13 & VCC)) // \ula_|i2s_intf_|Add0~15 = CARRY((\ula_|i2s_intf_|lrdivider [7] & !\ula_|i2s_intf_|Add0~13 )) - .dataa(\ula_|i2s_intf_|lrdivider [7]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|i2s_intf_|lrdivider [7]), .datac(gnd), .datad(vcc), .cin(\ula_|i2s_intf_|Add0~13 ), .combout(\ula_|i2s_intf_|Add0~14_combout ), .cout(\ula_|i2s_intf_|Add0~15 )); // synopsys translate_off -defparam \ula_|i2s_intf_|Add0~14 .lut_mask = 16'h5A0A; +defparam \ula_|i2s_intf_|Add0~14 .lut_mask = 16'h3C0C; defparam \ula_|i2s_intf_|Add0~14 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X30_Y23_N4 +// Location: LCCOMB_X24_Y32_N2 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[7]~4 ( // Equation(s): // \ula_|i2s_intf_|lrdivider[7]~4_combout = !\ula_|i2s_intf_|Add0~14_combout .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|Add0~14_combout ), + .datac(\ula_|i2s_intf_|Add0~14_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|lrdivider[7]~4_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[7]~4 .lut_mask = 16'h00FF; +defparam \ula_|i2s_intf_|lrdivider[7]~4 .lut_mask = 16'h0F0F; defparam \ula_|i2s_intf_|lrdivider[7]~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X30_Y23_N5 +// Location: FF_X24_Y32_N3 dffeas \ula_|i2s_intf_|lrdivider[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider[7]~4_combout ), @@ -56165,25 +55915,25 @@ defparam \ula_|i2s_intf_|lrdivider[7] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N22 +// Location: LCCOMB_X24_Y32_N24 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~16 ( // Equation(s): // \ula_|i2s_intf_|Add0~16_combout = (\ula_|i2s_intf_|lrdivider [8] & ((GND) # (!\ula_|i2s_intf_|Add0~15 ))) # (!\ula_|i2s_intf_|lrdivider [8] & (\ula_|i2s_intf_|Add0~15 $ (GND))) // \ula_|i2s_intf_|Add0~17 = CARRY((\ula_|i2s_intf_|lrdivider [8]) # (!\ula_|i2s_intf_|Add0~15 )) - .dataa(\ula_|i2s_intf_|lrdivider [8]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|i2s_intf_|lrdivider [8]), .datac(gnd), .datad(vcc), .cin(\ula_|i2s_intf_|Add0~15 ), .combout(\ula_|i2s_intf_|Add0~16_combout ), .cout(\ula_|i2s_intf_|Add0~17 )); // synopsys translate_off -defparam \ula_|i2s_intf_|Add0~16 .lut_mask = 16'h5AAF; +defparam \ula_|i2s_intf_|Add0~16 .lut_mask = 16'h3CCF; defparam \ula_|i2s_intf_|Add0~16 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X28_Y23_N16 +// Location: LCCOMB_X24_Y32_N28 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider~0 ( // Equation(s): // \ula_|i2s_intf_|lrdivider~0_combout = (\ula_|i2s_intf_|Add0~16_combout & !\ula_|i2s_intf_|Equal0~2_combout ) @@ -56200,7 +55950,7 @@ defparam \ula_|i2s_intf_|lrdivider~0 .lut_mask = 16'h0C0C; defparam \ula_|i2s_intf_|lrdivider~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y23_N17 +// Location: FF_X24_Y32_N29 dffeas \ula_|i2s_intf_|lrdivider[8] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider~0_combout ), @@ -56219,41 +55969,41 @@ defparam \ula_|i2s_intf_|lrdivider[8] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[8] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N24 +// Location: LCCOMB_X24_Y32_N26 cycloneive_lcell_comb \ula_|i2s_intf_|Add0~18 ( // Equation(s): -// \ula_|i2s_intf_|Add0~18_combout = \ula_|i2s_intf_|Add0~17 $ (\ula_|i2s_intf_|lrdivider [9]) +// \ula_|i2s_intf_|Add0~18_combout = \ula_|i2s_intf_|lrdivider [9] $ (\ula_|i2s_intf_|Add0~17 ) .dataa(gnd), - .datab(gnd), + .datab(\ula_|i2s_intf_|lrdivider [9]), .datac(gnd), - .datad(\ula_|i2s_intf_|lrdivider [9]), + .datad(gnd), .cin(\ula_|i2s_intf_|Add0~17 ), .combout(\ula_|i2s_intf_|Add0~18_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|Add0~18 .lut_mask = 16'h0FF0; +defparam \ula_|i2s_intf_|Add0~18 .lut_mask = 16'h3C3C; defparam \ula_|i2s_intf_|Add0~18 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: LCCOMB_X28_Y23_N24 +// Location: LCCOMB_X24_Y32_N4 cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[9]~3 ( // Equation(s): // \ula_|i2s_intf_|lrdivider[9]~3_combout = !\ula_|i2s_intf_|Add0~18_combout .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|Add0~18_combout ), + .datac(\ula_|i2s_intf_|Add0~18_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|lrdivider[9]~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrdivider[9]~3 .lut_mask = 16'h00FF; +defparam \ula_|i2s_intf_|lrdivider[9]~3 .lut_mask = 16'h0F0F; defparam \ula_|i2s_intf_|lrdivider[9]~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y23_N25 +// Location: FF_X24_Y32_N5 dffeas \ula_|i2s_intf_|lrdivider[9] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|lrdivider[9]~3_combout ), @@ -56272,61 +56022,44 @@ defparam \ula_|i2s_intf_|lrdivider[9] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrdivider[9] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N0 +// Location: LCCOMB_X24_Y32_N6 cycloneive_lcell_comb \ula_|i2s_intf_|Equal0~0 ( // Equation(s): -// \ula_|i2s_intf_|Equal0~0_combout = (!\ula_|i2s_intf_|lrdivider [8] & (\ula_|i2s_intf_|lrdivider [9] & (\ula_|i2s_intf_|lrdivider [6] & \ula_|i2s_intf_|lrdivider [7]))) +// \ula_|i2s_intf_|Equal0~0_combout = (\ula_|i2s_intf_|lrdivider [6] & (!\ula_|i2s_intf_|lrdivider [8] & (\ula_|i2s_intf_|lrdivider [9] & \ula_|i2s_intf_|lrdivider [7]))) - .dataa(\ula_|i2s_intf_|lrdivider [8]), - .datab(\ula_|i2s_intf_|lrdivider [9]), - .datac(\ula_|i2s_intf_|lrdivider [6]), + .dataa(\ula_|i2s_intf_|lrdivider [6]), + .datab(\ula_|i2s_intf_|lrdivider [8]), + .datac(\ula_|i2s_intf_|lrdivider [9]), .datad(\ula_|i2s_intf_|lrdivider [7]), .cin(gnd), .combout(\ula_|i2s_intf_|Equal0~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|Equal0~0 .lut_mask = 16'h4000; +defparam \ula_|i2s_intf_|Equal0~0 .lut_mask = 16'h2000; defparam \ula_|i2s_intf_|Equal0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X29_Y23_N30 +// Location: LCCOMB_X24_Y32_N30 cycloneive_lcell_comb \ula_|i2s_intf_|Equal0~2 ( // Equation(s): -// \ula_|i2s_intf_|Equal0~2_combout = (\ula_|i2s_intf_|Equal0~1_combout & (!\ula_|i2s_intf_|lrdivider [1] & (\ula_|i2s_intf_|mclk_r~_Duplicate_1_q & \ula_|i2s_intf_|Equal0~0_combout ))) +// \ula_|i2s_intf_|Equal0~2_combout = (!\ula_|i2s_intf_|lrdivider [1] & (\ula_|i2s_intf_|Equal0~1_combout & (\ula_|i2s_intf_|mclk_r~_Duplicate_1_q & \ula_|i2s_intf_|Equal0~0_combout ))) - .dataa(\ula_|i2s_intf_|Equal0~1_combout ), - .datab(\ula_|i2s_intf_|lrdivider [1]), + .dataa(\ula_|i2s_intf_|lrdivider [1]), + .datab(\ula_|i2s_intf_|Equal0~1_combout ), .datac(\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ), .datad(\ula_|i2s_intf_|Equal0~0_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|Equal0~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|Equal0~2 .lut_mask = 16'h2000; +defparam \ula_|i2s_intf_|Equal0~2 .lut_mask = 16'h4000; defparam \ula_|i2s_intf_|Equal0~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y22_N24 -cycloneive_lcell_comb \ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder ( -// Equation(s): -// \ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder_combout = \ula_|i2s_intf_|lrclk_r~0_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|lrclk_r~0_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder .lut_mask = 16'hFF00; -defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y22_N25 +// Location: FF_X23_Y31_N5 dffeas \ula_|i2s_intf_|lrclk_r~_Duplicate_2 ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder_combout ), + .d(\ula_|i2s_intf_|lrclk_r~0_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -56342,20 +56075,20 @@ defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_2 .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_2 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y22_N0 +// Location: LCCOMB_X23_Y31_N4 cycloneive_lcell_comb \ula_|i2s_intf_|lrclk_r~0 ( // Equation(s): // \ula_|i2s_intf_|lrclk_r~0_combout = \ula_|i2s_intf_|Equal0~2_combout $ (\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ) .dataa(gnd), .datab(\ula_|i2s_intf_|Equal0~2_combout ), - .datac(gnd), - .datad(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), + .datac(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|lrclk_r~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|lrclk_r~0 .lut_mask = 16'h33CC; +defparam \ula_|i2s_intf_|lrclk_r~0 .lut_mask = 16'h3C3C; defparam \ula_|i2s_intf_|lrclk_r~0 .sum_lutc_input = "datac"; // synopsys translate_on @@ -56397,7 +56130,7 @@ defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_1 .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y22_N0 +// Location: LCCOMB_X25_Y31_N0 cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[0]~5 ( // Equation(s): // \ula_|i2s_intf_|bitcount[0]~5_combout = !\ula_|i2s_intf_|bitcount [0] @@ -56415,10 +56148,27 @@ defparam \ula_|i2s_intf_|bitcount[0]~5 .lut_mask = 16'h3333; defparam \ula_|i2s_intf_|bitcount[0]~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y22_N11 +// Location: LCCOMB_X25_Y31_N26 +cycloneive_lcell_comb \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder ( +// Equation(s): +// \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder_combout = \ula_|i2s_intf_|bclk_r~1_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|i2s_intf_|bclk_r~1_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|bclk_r~_Duplicate_1feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder .lut_mask = 16'hFF00; +defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X25_Y31_N27 dffeas \ula_|i2s_intf_|bclk_r~_Duplicate_1 ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|bclk_r~1_combout ), + .d(\ula_|i2s_intf_|bclk_r~_Duplicate_1feeder_combout ), .asdata(vcc), .clrn(!\reset~clkctrl_outclk ), .aload(gnd), @@ -56434,24 +56184,24 @@ defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1 .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y22_N28 +// Location: LCCOMB_X25_Y31_N22 cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[4]~15 ( // Equation(s): -// \ula_|i2s_intf_|bitcount[4]~15_combout = (\ula_|i2s_intf_|Equal0~2_combout ) # ((\ula_|i2s_intf_|shiftreg[4]~1_combout & !\ula_|i2s_intf_|bclk_r~_Duplicate_1_q )) +// \ula_|i2s_intf_|bitcount[4]~15_combout = (\ula_|i2s_intf_|Equal0~2_combout ) # ((!\ula_|i2s_intf_|bclk_r~_Duplicate_1_q & \ula_|i2s_intf_|shiftreg[4]~1_combout )) - .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg[4]~1_combout ), + .dataa(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .datab(gnd), .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .datad(\ula_|i2s_intf_|shiftreg[4]~1_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|bitcount[4]~15_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[4]~15 .lut_mask = 16'hF0FC; +defparam \ula_|i2s_intf_|bitcount[4]~15 .lut_mask = 16'hF5F0; defparam \ula_|i2s_intf_|bitcount[4]~15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y22_N1 +// Location: FF_X25_Y31_N1 dffeas \ula_|i2s_intf_|bitcount[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|bitcount[0]~5_combout ), @@ -56470,25 +56220,25 @@ defparam \ula_|i2s_intf_|bitcount[0] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|bitcount[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y22_N2 +// Location: LCCOMB_X25_Y31_N2 cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[1]~7 ( // Equation(s): // \ula_|i2s_intf_|bitcount[1]~7_combout = (\ula_|i2s_intf_|bitcount [1] & (\ula_|i2s_intf_|bitcount[0]~6 & VCC)) # (!\ula_|i2s_intf_|bitcount [1] & (!\ula_|i2s_intf_|bitcount[0]~6 )) // \ula_|i2s_intf_|bitcount[1]~8 = CARRY((!\ula_|i2s_intf_|bitcount [1] & !\ula_|i2s_intf_|bitcount[0]~6 )) - .dataa(gnd), - .datab(\ula_|i2s_intf_|bitcount [1]), + .dataa(\ula_|i2s_intf_|bitcount [1]), + .datab(gnd), .datac(gnd), .datad(vcc), .cin(\ula_|i2s_intf_|bitcount[0]~6 ), .combout(\ula_|i2s_intf_|bitcount[1]~7_combout ), .cout(\ula_|i2s_intf_|bitcount[1]~8 )); // synopsys translate_off -defparam \ula_|i2s_intf_|bitcount[1]~7 .lut_mask = 16'hC303; +defparam \ula_|i2s_intf_|bitcount[1]~7 .lut_mask = 16'hA505; defparam \ula_|i2s_intf_|bitcount[1]~7 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y22_N3 +// Location: FF_X25_Y31_N3 dffeas \ula_|i2s_intf_|bitcount[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|bitcount[1]~7_combout ), @@ -56507,7 +56257,7 @@ defparam \ula_|i2s_intf_|bitcount[1] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|bitcount[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y22_N4 +// Location: LCCOMB_X25_Y31_N4 cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[2]~9 ( // Equation(s): // \ula_|i2s_intf_|bitcount[2]~9_combout = (\ula_|i2s_intf_|bitcount [2] & ((GND) # (!\ula_|i2s_intf_|bitcount[1]~8 ))) # (!\ula_|i2s_intf_|bitcount [2] & (\ula_|i2s_intf_|bitcount[1]~8 $ (GND))) @@ -56525,7 +56275,7 @@ defparam \ula_|i2s_intf_|bitcount[2]~9 .lut_mask = 16'h3CCF; defparam \ula_|i2s_intf_|bitcount[2]~9 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y22_N5 +// Location: FF_X25_Y31_N5 dffeas \ula_|i2s_intf_|bitcount[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|bitcount[2]~9_combout ), @@ -56544,7 +56294,7 @@ defparam \ula_|i2s_intf_|bitcount[2] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|bitcount[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y22_N6 +// Location: LCCOMB_X25_Y31_N6 cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[3]~11 ( // Equation(s): // \ula_|i2s_intf_|bitcount[3]~11_combout = (\ula_|i2s_intf_|bitcount [3] & (\ula_|i2s_intf_|bitcount[2]~10 & VCC)) # (!\ula_|i2s_intf_|bitcount [3] & (!\ula_|i2s_intf_|bitcount[2]~10 )) @@ -56562,7 +56312,7 @@ defparam \ula_|i2s_intf_|bitcount[3]~11 .lut_mask = 16'hA505; defparam \ula_|i2s_intf_|bitcount[3]~11 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y22_N7 +// Location: FF_X25_Y31_N7 dffeas \ula_|i2s_intf_|bitcount[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|bitcount[3]~11_combout ), @@ -56581,24 +56331,7 @@ defparam \ula_|i2s_intf_|bitcount[3] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|bitcount[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y22_N24 -cycloneive_lcell_comb \ula_|i2s_intf_|LessThan0~0 ( -// Equation(s): -// \ula_|i2s_intf_|LessThan0~0_combout = (\ula_|i2s_intf_|bitcount [3]) # (((\ula_|i2s_intf_|bitcount [2]) # (\ula_|i2s_intf_|bitcount [1])) # (!\ula_|i2s_intf_|bitcount [0])) - - .dataa(\ula_|i2s_intf_|bitcount [3]), - .datab(\ula_|i2s_intf_|bitcount [0]), - .datac(\ula_|i2s_intf_|bitcount [2]), - .datad(\ula_|i2s_intf_|bitcount [1]), - .cin(gnd), - .combout(\ula_|i2s_intf_|LessThan0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|LessThan0~0 .lut_mask = 16'hFFFB; -defparam \ula_|i2s_intf_|LessThan0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y22_N8 +// Location: LCCOMB_X25_Y31_N8 cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[4]~13 ( // Equation(s): // \ula_|i2s_intf_|bitcount[4]~13_combout = \ula_|i2s_intf_|bitcount [4] $ (\ula_|i2s_intf_|bitcount[3]~12 ) @@ -56615,7 +56348,7 @@ defparam \ula_|i2s_intf_|bitcount[4]~13 .lut_mask = 16'h3C3C; defparam \ula_|i2s_intf_|bitcount[4]~13 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y22_N9 +// Location: FF_X25_Y31_N9 dffeas \ula_|i2s_intf_|bitcount[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|bitcount[4]~13_combout ), @@ -56634,273 +56367,41 @@ defparam \ula_|i2s_intf_|bitcount[4] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|bitcount[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y22_N14 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~7 ( +// Location: LCCOMB_X25_Y31_N20 +cycloneive_lcell_comb \ula_|i2s_intf_|LessThan0~0 ( // Equation(s): -// \ula_|i2s_intf_|Add2~7_cout = CARRY(!\ula_|i2s_intf_|bdivider [0]) +// \ula_|i2s_intf_|LessThan0~0_combout = (\ula_|i2s_intf_|bitcount [1]) # (((\ula_|i2s_intf_|bitcount [2]) # (\ula_|i2s_intf_|bitcount [3])) # (!\ula_|i2s_intf_|bitcount [0])) - .dataa(\ula_|i2s_intf_|bdivider [0]), - .datab(gnd), - .datac(gnd), - .datad(vcc), + .dataa(\ula_|i2s_intf_|bitcount [1]), + .datab(\ula_|i2s_intf_|bitcount [0]), + .datac(\ula_|i2s_intf_|bitcount [2]), + .datad(\ula_|i2s_intf_|bitcount [3]), .cin(gnd), - .combout(), - .cout(\ula_|i2s_intf_|Add2~7_cout )); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~7 .lut_mask = 16'h0055; -defparam \ula_|i2s_intf_|Add2~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y22_N16 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~8 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~8_combout = (\ula_|i2s_intf_|bdivider [1] & (\ula_|i2s_intf_|Add2~7_cout & VCC)) # (!\ula_|i2s_intf_|bdivider [1] & (!\ula_|i2s_intf_|Add2~7_cout )) -// \ula_|i2s_intf_|Add2~9 = CARRY((!\ula_|i2s_intf_|bdivider [1] & !\ula_|i2s_intf_|Add2~7_cout )) - - .dataa(\ula_|i2s_intf_|bdivider [1]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|Add2~7_cout ), - .combout(\ula_|i2s_intf_|Add2~8_combout ), - .cout(\ula_|i2s_intf_|Add2~9 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~8 .lut_mask = 16'hA505; -defparam \ula_|i2s_intf_|Add2~8 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y22_N12 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~20 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~20_combout = (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|Add2~8_combout & ((!\ula_|i2s_intf_|Equal1~0_combout ) # (!\ula_|i2s_intf_|bdivider [0])))) - - .dataa(\ula_|i2s_intf_|bdivider [0]), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), - .datac(\ula_|i2s_intf_|Equal1~0_combout ), - .datad(\ula_|i2s_intf_|Add2~8_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|Add2~20_combout ), + .combout(\ula_|i2s_intf_|LessThan0~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|Add2~20 .lut_mask = 16'h1300; -defparam \ula_|i2s_intf_|Add2~20 .sum_lutc_input = "datac"; +defparam \ula_|i2s_intf_|LessThan0~0 .lut_mask = 16'hFFFB; +defparam \ula_|i2s_intf_|LessThan0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y22_N13 -dffeas \ula_|i2s_intf_|bdivider[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|Add2~20_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bdivider [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bdivider[1] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bdivider[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y22_N18 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~10 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~10_combout = (\ula_|i2s_intf_|bdivider [2] & (\ula_|i2s_intf_|Add2~9 $ (GND))) # (!\ula_|i2s_intf_|bdivider [2] & ((GND) # (!\ula_|i2s_intf_|Add2~9 ))) -// \ula_|i2s_intf_|Add2~11 = CARRY((!\ula_|i2s_intf_|Add2~9 ) # (!\ula_|i2s_intf_|bdivider [2])) - - .dataa(\ula_|i2s_intf_|bdivider [2]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|Add2~9 ), - .combout(\ula_|i2s_intf_|Add2~10_combout ), - .cout(\ula_|i2s_intf_|Add2~11 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~10 .lut_mask = 16'hA55F; -defparam \ula_|i2s_intf_|Add2~10 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y22_N16 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~17 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~17_combout = (!\ula_|i2s_intf_|shiftreg[4]~1_combout & (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~1_combout ) # (!\ula_|i2s_intf_|Add2~10_combout )))) - - .dataa(\ula_|i2s_intf_|Equal1~1_combout ), - .datab(\ula_|i2s_intf_|shiftreg[4]~1_combout ), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|Add2~10_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|Add2~17_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~17 .lut_mask = 16'h0203; -defparam \ula_|i2s_intf_|Add2~17 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y22_N17 -dffeas \ula_|i2s_intf_|bdivider[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|Add2~17_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bdivider [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bdivider[2] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bdivider[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y22_N20 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~12 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~12_combout = (\ula_|i2s_intf_|bdivider [3] & (\ula_|i2s_intf_|Add2~11 & VCC)) # (!\ula_|i2s_intf_|bdivider [3] & (!\ula_|i2s_intf_|Add2~11 )) -// \ula_|i2s_intf_|Add2~13 = CARRY((!\ula_|i2s_intf_|bdivider [3] & !\ula_|i2s_intf_|Add2~11 )) - - .dataa(gnd), - .datab(\ula_|i2s_intf_|bdivider [3]), - .datac(gnd), - .datad(vcc), - .cin(\ula_|i2s_intf_|Add2~11 ), - .combout(\ula_|i2s_intf_|Add2~12_combout ), - .cout(\ula_|i2s_intf_|Add2~13 )); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~12 .lut_mask = 16'hC303; -defparam \ula_|i2s_intf_|Add2~12 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y22_N2 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~19 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~19_combout = (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|Add2~12_combout & ((!\ula_|i2s_intf_|Equal1~0_combout ) # (!\ula_|i2s_intf_|bdivider [0])))) - - .dataa(\ula_|i2s_intf_|bdivider [0]), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), - .datac(\ula_|i2s_intf_|Equal1~0_combout ), - .datad(\ula_|i2s_intf_|Add2~12_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|Add2~19_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~19 .lut_mask = 16'h1300; -defparam \ula_|i2s_intf_|Add2~19 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y22_N3 -dffeas \ula_|i2s_intf_|bdivider[3] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|Add2~19_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bdivider [3]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bdivider[3] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bdivider[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y22_N22 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~14 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~14_combout = \ula_|i2s_intf_|Add2~13 $ (!\ula_|i2s_intf_|bdivider [4]) - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|bdivider [4]), - .cin(\ula_|i2s_intf_|Add2~13 ), - .combout(\ula_|i2s_intf_|Add2~14_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~14 .lut_mask = 16'hF00F; -defparam \ula_|i2s_intf_|Add2~14 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y22_N18 -cycloneive_lcell_comb \ula_|i2s_intf_|Add2~16 ( -// Equation(s): -// \ula_|i2s_intf_|Add2~16_combout = (!\ula_|i2s_intf_|shiftreg[4]~1_combout & (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~1_combout ) # (!\ula_|i2s_intf_|Add2~14_combout )))) - - .dataa(\ula_|i2s_intf_|Equal1~1_combout ), - .datab(\ula_|i2s_intf_|shiftreg[4]~1_combout ), - .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|Add2~14_combout ), - .cin(gnd), - .combout(\ula_|i2s_intf_|Add2~16_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Add2~16 .lut_mask = 16'h0203; -defparam \ula_|i2s_intf_|Add2~16 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X31_Y22_N19 -dffeas \ula_|i2s_intf_|bdivider[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|Add2~16_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|bdivider [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|bdivider[4] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|bdivider[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y22_N26 -cycloneive_lcell_comb \ula_|i2s_intf_|Equal1~0 ( -// Equation(s): -// \ula_|i2s_intf_|Equal1~0_combout = (!\ula_|i2s_intf_|bdivider [1] & (!\ula_|i2s_intf_|bdivider [3] & (\ula_|i2s_intf_|bdivider [2] & \ula_|i2s_intf_|bdivider [4]))) - - .dataa(\ula_|i2s_intf_|bdivider [1]), - .datab(\ula_|i2s_intf_|bdivider [3]), - .datac(\ula_|i2s_intf_|bdivider [2]), - .datad(\ula_|i2s_intf_|bdivider [4]), - .cin(gnd), - .combout(\ula_|i2s_intf_|Equal1~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|Equal1~0 .lut_mask = 16'h1000; -defparam \ula_|i2s_intf_|Equal1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y22_N20 +// Location: LCCOMB_X25_Y31_N10 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[4]~1 ( // Equation(s): // \ula_|i2s_intf_|shiftreg[4]~1_combout = (\ula_|i2s_intf_|bdivider [0] & (\ula_|i2s_intf_|Equal1~0_combout & ((\ula_|i2s_intf_|LessThan0~0_combout ) # (!\ula_|i2s_intf_|bitcount [4])))) .dataa(\ula_|i2s_intf_|bdivider [0]), - .datab(\ula_|i2s_intf_|LessThan0~0_combout ), + .datab(\ula_|i2s_intf_|Equal1~0_combout ), .datac(\ula_|i2s_intf_|bitcount [4]), - .datad(\ula_|i2s_intf_|Equal1~0_combout ), + .datad(\ula_|i2s_intf_|LessThan0~0_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg[4]~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[4]~1 .lut_mask = 16'h8A00; +defparam \ula_|i2s_intf_|shiftreg[4]~1 .lut_mask = 16'h8808; defparam \ula_|i2s_intf_|shiftreg[4]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y22_N12 +// Location: LCCOMB_X24_Y31_N12 cycloneive_lcell_comb \ula_|i2s_intf_|Add2~18 ( // Equation(s): // \ula_|i2s_intf_|Add2~18_combout = (!\ula_|i2s_intf_|Equal0~2_combout & (!\ula_|i2s_intf_|shiftreg[4]~1_combout & ((\ula_|i2s_intf_|Equal1~0_combout ) # (!\ula_|i2s_intf_|bdivider [0])))) @@ -56917,7 +56418,7 @@ defparam \ula_|i2s_intf_|Add2~18 .lut_mask = 16'h1101; defparam \ula_|i2s_intf_|Add2~18 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y22_N13 +// Location: FF_X24_Y31_N13 dffeas \ula_|i2s_intf_|bdivider[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|Add2~18_combout ), @@ -56936,54 +56437,303 @@ defparam \ula_|i2s_intf_|bdivider[0] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|bdivider[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y22_N22 -cycloneive_lcell_comb \ula_|i2s_intf_|Equal1~1 ( +// Location: LCCOMB_X24_Y31_N2 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~7 ( // Equation(s): -// \ula_|i2s_intf_|Equal1~1_combout = (\ula_|i2s_intf_|bdivider [0] & \ula_|i2s_intf_|Equal1~0_combout ) +// \ula_|i2s_intf_|Add2~7_cout = CARRY(!\ula_|i2s_intf_|bdivider [0]) + + .dataa(\ula_|i2s_intf_|bdivider [0]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(), + .cout(\ula_|i2s_intf_|Add2~7_cout )); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~7 .lut_mask = 16'h0055; +defparam \ula_|i2s_intf_|Add2~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y31_N4 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~8 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~8_combout = (\ula_|i2s_intf_|bdivider [1] & (\ula_|i2s_intf_|Add2~7_cout & VCC)) # (!\ula_|i2s_intf_|bdivider [1] & (!\ula_|i2s_intf_|Add2~7_cout )) +// \ula_|i2s_intf_|Add2~9 = CARRY((!\ula_|i2s_intf_|bdivider [1] & !\ula_|i2s_intf_|Add2~7_cout )) + + .dataa(\ula_|i2s_intf_|bdivider [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|Add2~7_cout ), + .combout(\ula_|i2s_intf_|Add2~8_combout ), + .cout(\ula_|i2s_intf_|Add2~9 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~8 .lut_mask = 16'hA505; +defparam \ula_|i2s_intf_|Add2~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y31_N22 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~20 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~20_combout = (\ula_|i2s_intf_|Add2~8_combout & (!\ula_|i2s_intf_|Equal0~2_combout & ((!\ula_|i2s_intf_|Equal1~0_combout ) # (!\ula_|i2s_intf_|bdivider [0])))) + + .dataa(\ula_|i2s_intf_|bdivider [0]), + .datab(\ula_|i2s_intf_|Add2~8_combout ), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|Equal1~0_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|Add2~20_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~20 .lut_mask = 16'h040C; +defparam \ula_|i2s_intf_|Add2~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y31_N23 +dffeas \ula_|i2s_intf_|bdivider[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|Add2~20_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bdivider [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bdivider[1] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bdivider[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y31_N6 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~10 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~10_combout = (\ula_|i2s_intf_|bdivider [2] & (\ula_|i2s_intf_|Add2~9 $ (GND))) # (!\ula_|i2s_intf_|bdivider [2] & ((GND) # (!\ula_|i2s_intf_|Add2~9 ))) +// \ula_|i2s_intf_|Add2~11 = CARRY((!\ula_|i2s_intf_|Add2~9 ) # (!\ula_|i2s_intf_|bdivider [2])) + + .dataa(\ula_|i2s_intf_|bdivider [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|Add2~9 ), + .combout(\ula_|i2s_intf_|Add2~10_combout ), + .cout(\ula_|i2s_intf_|Add2~11 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~10 .lut_mask = 16'hA55F; +defparam \ula_|i2s_intf_|Add2~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y31_N26 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~17 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~17_combout = (!\ula_|i2s_intf_|Equal0~2_combout & (!\ula_|i2s_intf_|shiftreg[4]~1_combout & ((\ula_|i2s_intf_|Equal1~1_combout ) # (!\ula_|i2s_intf_|Add2~10_combout )))) + + .dataa(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(\ula_|i2s_intf_|Equal1~1_combout ), + .datac(\ula_|i2s_intf_|shiftreg[4]~1_combout ), + .datad(\ula_|i2s_intf_|Add2~10_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|Add2~17_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~17 .lut_mask = 16'h0405; +defparam \ula_|i2s_intf_|Add2~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y31_N27 +dffeas \ula_|i2s_intf_|bdivider[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|Add2~17_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bdivider [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bdivider[2] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bdivider[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y31_N8 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~12 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~12_combout = (\ula_|i2s_intf_|bdivider [3] & (\ula_|i2s_intf_|Add2~11 & VCC)) # (!\ula_|i2s_intf_|bdivider [3] & (!\ula_|i2s_intf_|Add2~11 )) +// \ula_|i2s_intf_|Add2~13 = CARRY((!\ula_|i2s_intf_|bdivider [3] & !\ula_|i2s_intf_|Add2~11 )) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|bdivider [3]), + .datac(gnd), + .datad(vcc), + .cin(\ula_|i2s_intf_|Add2~11 ), + .combout(\ula_|i2s_intf_|Add2~12_combout ), + .cout(\ula_|i2s_intf_|Add2~13 )); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~12 .lut_mask = 16'hC303; +defparam \ula_|i2s_intf_|Add2~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y31_N0 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~19 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~19_combout = (\ula_|i2s_intf_|Add2~12_combout & (!\ula_|i2s_intf_|Equal0~2_combout & ((!\ula_|i2s_intf_|Equal1~0_combout ) # (!\ula_|i2s_intf_|bdivider [0])))) + + .dataa(\ula_|i2s_intf_|bdivider [0]), + .datab(\ula_|i2s_intf_|Add2~12_combout ), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|Equal1~0_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|Add2~19_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~19 .lut_mask = 16'h040C; +defparam \ula_|i2s_intf_|Add2~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y31_N1 +dffeas \ula_|i2s_intf_|bdivider[3] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|Add2~19_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bdivider [3]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bdivider[3] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bdivider[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y31_N10 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~14 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~14_combout = \ula_|i2s_intf_|Add2~13 $ (!\ula_|i2s_intf_|bdivider [4]) .dataa(gnd), .datab(gnd), - .datac(\ula_|i2s_intf_|bdivider [0]), - .datad(\ula_|i2s_intf_|Equal1~0_combout ), + .datac(gnd), + .datad(\ula_|i2s_intf_|bdivider [4]), + .cin(\ula_|i2s_intf_|Add2~13 ), + .combout(\ula_|i2s_intf_|Add2~14_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~14 .lut_mask = 16'hF00F; +defparam \ula_|i2s_intf_|Add2~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y31_N28 +cycloneive_lcell_comb \ula_|i2s_intf_|Add2~16 ( +// Equation(s): +// \ula_|i2s_intf_|Add2~16_combout = (!\ula_|i2s_intf_|Equal0~2_combout & (!\ula_|i2s_intf_|shiftreg[4]~1_combout & ((\ula_|i2s_intf_|Equal1~1_combout ) # (!\ula_|i2s_intf_|Add2~14_combout )))) + + .dataa(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(\ula_|i2s_intf_|Equal1~1_combout ), + .datac(\ula_|i2s_intf_|shiftreg[4]~1_combout ), + .datad(\ula_|i2s_intf_|Add2~14_combout ), + .cin(gnd), + .combout(\ula_|i2s_intf_|Add2~16_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Add2~16 .lut_mask = 16'h0405; +defparam \ula_|i2s_intf_|Add2~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y31_N29 +dffeas \ula_|i2s_intf_|bdivider[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|Add2~16_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|bdivider [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|bdivider[4] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|bdivider[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y31_N20 +cycloneive_lcell_comb \ula_|i2s_intf_|Equal1~0 ( +// Equation(s): +// \ula_|i2s_intf_|Equal1~0_combout = (!\ula_|i2s_intf_|bdivider [1] & (\ula_|i2s_intf_|bdivider [4] & (\ula_|i2s_intf_|bdivider [2] & !\ula_|i2s_intf_|bdivider [3]))) + + .dataa(\ula_|i2s_intf_|bdivider [1]), + .datab(\ula_|i2s_intf_|bdivider [4]), + .datac(\ula_|i2s_intf_|bdivider [2]), + .datad(\ula_|i2s_intf_|bdivider [3]), + .cin(gnd), + .combout(\ula_|i2s_intf_|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|Equal1~0 .lut_mask = 16'h0040; +defparam \ula_|i2s_intf_|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y31_N14 +cycloneive_lcell_comb \ula_|i2s_intf_|Equal1~1 ( +// Equation(s): +// \ula_|i2s_intf_|Equal1~1_combout = (\ula_|i2s_intf_|Equal1~0_combout & \ula_|i2s_intf_|bdivider [0]) + + .dataa(gnd), + .datab(\ula_|i2s_intf_|Equal1~0_combout ), + .datac(gnd), + .datad(\ula_|i2s_intf_|bdivider [0]), .cin(gnd), .combout(\ula_|i2s_intf_|Equal1~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|Equal1~1 .lut_mask = 16'hF000; +defparam \ula_|i2s_intf_|Equal1~1 .lut_mask = 16'hCC00; defparam \ula_|i2s_intf_|Equal1~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y22_N14 +// Location: LCCOMB_X25_Y31_N18 cycloneive_lcell_comb \ula_|i2s_intf_|bclk_r~0 ( // Equation(s): // \ula_|i2s_intf_|bclk_r~0_combout = \ula_|i2s_intf_|bclk_r~_Duplicate_1_q $ (((\ula_|i2s_intf_|LessThan0~0_combout ) # (!\ula_|i2s_intf_|bitcount [4]))) - .dataa(gnd), + .dataa(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), .datab(\ula_|i2s_intf_|LessThan0~0_combout ), .datac(\ula_|i2s_intf_|bitcount [4]), - .datad(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|bclk_r~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|bclk_r~0 .lut_mask = 16'h30CF; +defparam \ula_|i2s_intf_|bclk_r~0 .lut_mask = 16'h6565; defparam \ula_|i2s_intf_|bclk_r~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y22_N10 +// Location: LCCOMB_X25_Y31_N24 cycloneive_lcell_comb \ula_|i2s_intf_|bclk_r~1 ( // Equation(s): -// \ula_|i2s_intf_|bclk_r~1_combout = (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~1_combout & (\ula_|i2s_intf_|bclk_r~0_combout )) # (!\ula_|i2s_intf_|Equal1~1_combout & ((\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ))))) +// \ula_|i2s_intf_|bclk_r~1_combout = (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~1_combout & ((\ula_|i2s_intf_|bclk_r~0_combout ))) # (!\ula_|i2s_intf_|Equal1~1_combout & (\ula_|i2s_intf_|bclk_r~_Duplicate_1_q )))) .dataa(\ula_|i2s_intf_|Equal1~1_combout ), - .datab(\ula_|i2s_intf_|bclk_r~0_combout ), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), .datac(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|bclk_r~0_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|bclk_r~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|bclk_r~1 .lut_mask = 16'h00D8; +defparam \ula_|i2s_intf_|bclk_r~1 .lut_mask = 16'h3210; defparam \ula_|i2s_intf_|bclk_r~1 .sum_lutc_input = "datac"; // synopsys translate_on @@ -57006,61 +56756,44 @@ defparam \ula_|i2s_intf_|bclk_r .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|bclk_r .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y19_N24 -cycloneive_lcell_comb \ula_|pcm_outl[13]~feeder ( -// Equation(s): -// \ula_|pcm_outl[13]~feeder_combout = \D[3]~96_combout - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\D[3]~96_combout ), - .cin(gnd), - .combout(\ula_|pcm_outl[13]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|pcm_outl[13]~feeder .lut_mask = 16'hFF00; -defparam \ula_|pcm_outl[13]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y12_N2 +// Location: LCCOMB_X29_Y11_N14 cycloneive_lcell_comb \ula_|always0~2 ( // Equation(s): -// \ula_|always0~2_combout = (\z80_|memory_ifc_|nWR_out~0_combout & (!\z80_|memory_ifc_|nRD_out~2_combout & \z80_|resets_|SYNTHESIZED_WIRE_12~q )) +// \ula_|always0~2_combout = (!\z80_|memory_ifc_|nRD_out~2_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \z80_|memory_ifc_|nWR_out~0_combout )) - .dataa(\z80_|memory_ifc_|nWR_out~0_combout ), - .datab(\z80_|memory_ifc_|nRD_out~2_combout ), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), - .datad(gnd), + .dataa(\z80_|memory_ifc_|nRD_out~2_combout ), + .datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(gnd), + .datad(\z80_|memory_ifc_|nWR_out~0_combout ), .cin(gnd), .combout(\ula_|always0~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|always0~2 .lut_mask = 16'h2020; +defparam \ula_|always0~2 .lut_mask = 16'h4400; defparam \ula_|always0~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y12_N20 +// Location: LCCOMB_X29_Y11_N26 cycloneive_lcell_comb \ula_|always0~3 ( // Equation(s): -// \ula_|always0~3_combout = (!\z80_|address_pins_|DFFE_apin_latch [0] & (\z80_|memory_ifc_|nIORQ_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \ula_|always0~2_combout ))) +// \ula_|always0~3_combout = (\z80_|memory_ifc_|nIORQ_out~0_combout & (!\z80_|address_pins_|DFFE_apin_latch [0] & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \ula_|always0~2_combout ))) - .dataa(\z80_|address_pins_|DFFE_apin_latch [0]), - .datab(\z80_|memory_ifc_|nIORQ_out~0_combout ), + .dataa(\z80_|memory_ifc_|nIORQ_out~0_combout ), + .datab(\z80_|address_pins_|DFFE_apin_latch [0]), .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .datad(\ula_|always0~2_combout ), .cin(gnd), .combout(\ula_|always0~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|always0~3 .lut_mask = 16'h4000; +defparam \ula_|always0~3 .lut_mask = 16'h2000; defparam \ula_|always0~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y19_N25 -dffeas \ula_|pcm_outl[13] ( +// Location: FF_X31_Y10_N31 +dffeas \ula_|pcm_outl[14] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\ula_|pcm_outl[13]~feeder_combout ), + .d(\D[4]~76_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -57069,27 +56802,27 @@ dffeas \ula_|pcm_outl[13] ( .ena(\ula_|always0~3_combout ), .devclrn(devclrn), .devpor(devpor), - .q(\ula_|pcm_outl [13]), + .q(\ula_|pcm_outl [14]), .prn(vcc)); // synopsys translate_off -defparam \ula_|pcm_outl[13] .is_wysiwyg = "true"; -defparam \ula_|pcm_outl[13] .power_up = "low"; +defparam \ula_|pcm_outl[14] .is_wysiwyg = "true"; +defparam \ula_|pcm_outl[14] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y22_N26 +// Location: LCCOMB_X25_Y31_N16 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[0]~19 ( // Equation(s): // \ula_|i2s_intf_|shiftreg[0]~19_combout = (\ula_|i2s_intf_|Equal1~1_combout & (!\ula_|i2s_intf_|bclk_r~_Duplicate_1_q & ((\ula_|i2s_intf_|LessThan0~0_combout ) # (!\ula_|i2s_intf_|bitcount [4])))) .dataa(\ula_|i2s_intf_|Equal1~1_combout ), - .datab(\ula_|i2s_intf_|LessThan0~0_combout ), - .datac(\ula_|i2s_intf_|bitcount [4]), - .datad(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .datab(\ula_|i2s_intf_|bitcount [4]), + .datac(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .datad(\ula_|i2s_intf_|LessThan0~0_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg[0]~19_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[0]~19 .lut_mask = 16'h008A; +defparam \ula_|i2s_intf_|shiftreg[0]~19 .lut_mask = 16'h0A02; defparam \ula_|i2s_intf_|shiftreg[0]~19 .sum_lutc_input = "datac"; // synopsys translate_on @@ -57103,25 +56836,25 @@ defparam \AUD_ADCDAT~input .bus_hold = "false"; defparam \AUD_ADCDAT~input .simulate_z_as = "z"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N20 +// Location: LCCOMB_X24_Y31_N18 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[0]~20 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg[0]~20_combout = (\ula_|i2s_intf_|shiftreg[0]~19_combout & ((\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|shiftreg [0])) # (!\ula_|i2s_intf_|Equal0~2_combout & ((\AUD_ADCDAT~input_o ))))) # -// (!\ula_|i2s_intf_|shiftreg[0]~19_combout & (((\ula_|i2s_intf_|shiftreg [0])))) +// \ula_|i2s_intf_|shiftreg[0]~20_combout = (\ula_|i2s_intf_|Equal0~2_combout & (((\ula_|i2s_intf_|shiftreg [0])))) # (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|shiftreg[0]~19_combout & ((\AUD_ADCDAT~input_o ))) # +// (!\ula_|i2s_intf_|shiftreg[0]~19_combout & (\ula_|i2s_intf_|shiftreg [0])))) - .dataa(\ula_|i2s_intf_|shiftreg[0]~19_combout ), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .dataa(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(\ula_|i2s_intf_|shiftreg[0]~19_combout ), .datac(\ula_|i2s_intf_|shiftreg [0]), .datad(\AUD_ADCDAT~input_o ), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg[0]~20_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[0]~20 .lut_mask = 16'hF2D0; +defparam \ula_|i2s_intf_|shiftreg[0]~20 .lut_mask = 16'hF4B0; defparam \ula_|i2s_intf_|shiftreg[0]~20 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N21 +// Location: FF_X24_Y31_N19 dffeas \ula_|i2s_intf_|shiftreg[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg[0]~20_combout ), @@ -57140,41 +56873,41 @@ defparam \ula_|i2s_intf_|shiftreg[0] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N26 +// Location: LCCOMB_X23_Y31_N26 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~18 ( // Equation(s): // \ula_|i2s_intf_|shiftreg~18_combout = (\ula_|i2s_intf_|shiftreg [0] & !\ula_|i2s_intf_|Equal0~2_combout ) .dataa(gnd), .datab(\ula_|i2s_intf_|shiftreg [0]), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~18_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~18 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~18 .lut_mask = 16'h0C0C; defparam \ula_|i2s_intf_|shiftreg~18 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y22_N30 +// Location: LCCOMB_X25_Y31_N28 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[4]~2 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg[4]~2_combout = (\ula_|i2s_intf_|Equal0~2_combout ) # ((\ula_|i2s_intf_|shiftreg[4]~1_combout & \ula_|i2s_intf_|bclk_r~_Duplicate_1_q )) +// \ula_|i2s_intf_|shiftreg[4]~2_combout = (\ula_|i2s_intf_|Equal0~2_combout ) # ((\ula_|i2s_intf_|bclk_r~_Duplicate_1_q & \ula_|i2s_intf_|shiftreg[4]~1_combout )) - .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg[4]~1_combout ), + .dataa(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .datab(gnd), .datac(\ula_|i2s_intf_|Equal0~2_combout ), - .datad(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ), + .datad(\ula_|i2s_intf_|shiftreg[4]~1_combout ), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg[4]~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg[4]~2 .lut_mask = 16'hFCF0; +defparam \ula_|i2s_intf_|shiftreg[4]~2 .lut_mask = 16'hFAF0; defparam \ula_|i2s_intf_|shiftreg[4]~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N27 +// Location: FF_X23_Y31_N27 dffeas \ula_|i2s_intf_|shiftreg[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~18_combout ), @@ -57193,24 +56926,24 @@ defparam \ula_|i2s_intf_|shiftreg[1] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N24 +// Location: LCCOMB_X23_Y31_N12 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~17 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~17_combout = (\ula_|i2s_intf_|shiftreg [1] & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|shiftreg~17_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [1]) .dataa(gnd), - .datab(gnd), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), .datac(\ula_|i2s_intf_|shiftreg [1]), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~17_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~17 .lut_mask = 16'h00F0; +defparam \ula_|i2s_intf_|shiftreg~17 .lut_mask = 16'h3030; defparam \ula_|i2s_intf_|shiftreg~17 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N25 +// Location: FF_X23_Y31_N13 dffeas \ula_|i2s_intf_|shiftreg[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~17_combout ), @@ -57229,24 +56962,24 @@ defparam \ula_|i2s_intf_|shiftreg[2] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N18 +// Location: LCCOMB_X23_Y31_N22 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~16 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~16_combout = (\ula_|i2s_intf_|shiftreg [2] & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|shiftreg~16_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [2]) .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg [2]), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(gnd), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|shiftreg [2]), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~16_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~16 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~16 .lut_mask = 16'h0F00; defparam \ula_|i2s_intf_|shiftreg~16 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N19 +// Location: FF_X23_Y31_N23 dffeas \ula_|i2s_intf_|shiftreg[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~16_combout ), @@ -57265,24 +56998,24 @@ defparam \ula_|i2s_intf_|shiftreg[3] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N0 +// Location: LCCOMB_X23_Y31_N0 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~15 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~15_combout = (\ula_|i2s_intf_|shiftreg [3] & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|shiftreg~15_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [3]) .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg [3]), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|shiftreg [3]), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~15_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~15 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~15 .lut_mask = 16'h3030; defparam \ula_|i2s_intf_|shiftreg~15 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N1 +// Location: FF_X23_Y31_N1 dffeas \ula_|i2s_intf_|shiftreg[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~15_combout ), @@ -57301,24 +57034,24 @@ defparam \ula_|i2s_intf_|shiftreg[4] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N10 +// Location: LCCOMB_X23_Y31_N14 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~14 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~14_combout = (\ula_|i2s_intf_|shiftreg [4] & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|shiftreg~14_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [4]) .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg [4]), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(gnd), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|shiftreg [4]), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~14_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~14 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~14 .lut_mask = 16'h0F00; defparam \ula_|i2s_intf_|shiftreg~14 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N11 +// Location: FF_X23_Y31_N15 dffeas \ula_|i2s_intf_|shiftreg[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~14_combout ), @@ -57337,24 +57070,24 @@ defparam \ula_|i2s_intf_|shiftreg[5] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N16 +// Location: LCCOMB_X23_Y31_N24 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~13 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~13_combout = (\ula_|i2s_intf_|shiftreg [5] & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|shiftreg~13_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [5]) - .dataa(\ula_|i2s_intf_|shiftreg [5]), - .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .dataa(gnd), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|shiftreg [5]), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~13_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~13 .lut_mask = 16'h00AA; +defparam \ula_|i2s_intf_|shiftreg~13 .lut_mask = 16'h3030; defparam \ula_|i2s_intf_|shiftreg~13 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N17 +// Location: FF_X23_Y31_N25 dffeas \ula_|i2s_intf_|shiftreg[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~13_combout ), @@ -57373,24 +57106,24 @@ defparam \ula_|i2s_intf_|shiftreg[6] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N30 +// Location: LCCOMB_X23_Y31_N30 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~12 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~12_combout = (\ula_|i2s_intf_|shiftreg [6] & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|shiftreg~12_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [6]) .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg [6]), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(gnd), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|shiftreg [6]), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~12_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~12 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~12 .lut_mask = 16'h0F00; defparam \ula_|i2s_intf_|shiftreg~12 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N31 +// Location: FF_X23_Y31_N31 dffeas \ula_|i2s_intf_|shiftreg[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~12_combout ), @@ -57409,24 +57142,24 @@ defparam \ula_|i2s_intf_|shiftreg[7] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N28 +// Location: LCCOMB_X23_Y31_N20 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~11 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~11_combout = (\ula_|i2s_intf_|shiftreg [7] & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|shiftreg~11_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [7]) .dataa(gnd), - .datab(gnd), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), .datac(\ula_|i2s_intf_|shiftreg [7]), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~11_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~11 .lut_mask = 16'h00F0; +defparam \ula_|i2s_intf_|shiftreg~11 .lut_mask = 16'h3030; defparam \ula_|i2s_intf_|shiftreg~11 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N29 +// Location: FF_X23_Y31_N21 dffeas \ula_|i2s_intf_|shiftreg[8] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~11_combout ), @@ -57445,24 +57178,24 @@ defparam \ula_|i2s_intf_|shiftreg[8] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[8] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N22 +// Location: LCCOMB_X23_Y31_N6 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~10 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~10_combout = (\ula_|i2s_intf_|shiftreg [8] & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|shiftreg~10_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [8]) .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg [8]), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(gnd), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|shiftreg [8]), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~10_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~10 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~10 .lut_mask = 16'h0F00; defparam \ula_|i2s_intf_|shiftreg~10 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N23 +// Location: FF_X23_Y31_N7 dffeas \ula_|i2s_intf_|shiftreg[9] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~10_combout ), @@ -57481,24 +57214,24 @@ defparam \ula_|i2s_intf_|shiftreg[9] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[9] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N12 +// Location: LCCOMB_X23_Y31_N16 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~9 ( // Equation(s): // \ula_|i2s_intf_|shiftreg~9_combout = (\ula_|i2s_intf_|shiftreg [9] & !\ula_|i2s_intf_|Equal0~2_combout ) - .dataa(gnd), + .dataa(\ula_|i2s_intf_|shiftreg [9]), .datab(gnd), - .datac(\ula_|i2s_intf_|shiftreg [9]), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~9_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~9 .lut_mask = 16'h00F0; +defparam \ula_|i2s_intf_|shiftreg~9 .lut_mask = 16'h0A0A; defparam \ula_|i2s_intf_|shiftreg~9 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N13 +// Location: FF_X23_Y31_N17 dffeas \ula_|i2s_intf_|shiftreg[10] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~9_combout ), @@ -57517,24 +57250,24 @@ defparam \ula_|i2s_intf_|shiftreg[10] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[10] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N2 +// Location: LCCOMB_X23_Y31_N18 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~8 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~8_combout = (\ula_|i2s_intf_|shiftreg [10] & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|shiftreg~8_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [10]) - .dataa(\ula_|i2s_intf_|shiftreg [10]), + .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(\ula_|i2s_intf_|shiftreg [10]), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~8_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~8 .lut_mask = 16'h00AA; +defparam \ula_|i2s_intf_|shiftreg~8 .lut_mask = 16'h0F00; defparam \ula_|i2s_intf_|shiftreg~8 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N3 +// Location: FF_X23_Y31_N19 dffeas \ula_|i2s_intf_|shiftreg[11] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~8_combout ), @@ -57553,24 +57286,24 @@ defparam \ula_|i2s_intf_|shiftreg[11] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[11] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N8 +// Location: LCCOMB_X23_Y31_N28 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~7 ( // Equation(s): // \ula_|i2s_intf_|shiftreg~7_combout = (\ula_|i2s_intf_|shiftreg [11] & !\ula_|i2s_intf_|Equal0~2_combout ) .dataa(gnd), .datab(\ula_|i2s_intf_|shiftreg [11]), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~7_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~7 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~7 .lut_mask = 16'h0C0C; defparam \ula_|i2s_intf_|shiftreg~7 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N9 +// Location: FF_X23_Y31_N29 dffeas \ula_|i2s_intf_|shiftreg[12] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~7_combout ), @@ -57589,62 +57322,25 @@ defparam \ula_|i2s_intf_|shiftreg[12] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[12] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y22_N30 -cycloneive_lcell_comb \ula_|i2s_intf_|PCM_INR[14]~0 ( -// Equation(s): -// \ula_|i2s_intf_|PCM_INR[14]~0_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & (\ula_|i2s_intf_|shiftreg [14])) # (!\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & ((\ula_|i2s_intf_|PCM_INR [14]))))) # -// (!\ula_|i2s_intf_|Equal0~2_combout & (((\ula_|i2s_intf_|PCM_INR [14])))) - - .dataa(\ula_|i2s_intf_|shiftreg [14]), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), - .datac(\ula_|i2s_intf_|PCM_INR [14]), - .datad(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), - .cin(gnd), - .combout(\ula_|i2s_intf_|PCM_INR[14]~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|i2s_intf_|PCM_INR[14]~0 .lut_mask = 16'hB8F0; -defparam \ula_|i2s_intf_|PCM_INR[14]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y22_N31 -dffeas \ula_|i2s_intf_|PCM_INR[14] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), - .d(\ula_|i2s_intf_|PCM_INR[14]~0_combout ), - .asdata(vcc), - .clrn(!\reset~clkctrl_outclk ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|i2s_intf_|PCM_INR [14]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|i2s_intf_|PCM_INR[14] .is_wysiwyg = "true"; -defparam \ula_|i2s_intf_|PCM_INR[14] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y22_N28 +// Location: LCCOMB_X24_Y31_N30 cycloneive_lcell_comb \ula_|i2s_intf_|PCM_INL[14]~0 ( // Equation(s): -// \ula_|i2s_intf_|PCM_INL[14]~0_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & ((\ula_|i2s_intf_|PCM_INL [14]))) # (!\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & (\ula_|i2s_intf_|shiftreg [14])))) # +// \ula_|i2s_intf_|PCM_INL[14]~0_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & (\ula_|i2s_intf_|PCM_INL [14])) # (!\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & ((\ula_|i2s_intf_|shiftreg [14]))))) # // (!\ula_|i2s_intf_|Equal0~2_combout & (((\ula_|i2s_intf_|PCM_INL [14])))) - .dataa(\ula_|i2s_intf_|shiftreg [14]), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .dataa(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), .datac(\ula_|i2s_intf_|PCM_INL [14]), - .datad(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), + .datad(\ula_|i2s_intf_|shiftreg [14]), .cin(gnd), .combout(\ula_|i2s_intf_|PCM_INL[14]~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|PCM_INL[14]~0 .lut_mask = 16'hF0B8; +defparam \ula_|i2s_intf_|PCM_INL[14]~0 .lut_mask = 16'hF2D0; defparam \ula_|i2s_intf_|PCM_INL[14]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y22_N29 +// Location: FF_X24_Y31_N31 dffeas \ula_|i2s_intf_|PCM_INL[14] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|PCM_INL[14]~0_combout ), @@ -57663,15 +57359,52 @@ defparam \ula_|i2s_intf_|PCM_INL[14] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|PCM_INL[14] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y22_N6 +// Location: LCCOMB_X24_Y31_N16 +cycloneive_lcell_comb \ula_|i2s_intf_|PCM_INR[14]~0 ( +// Equation(s): +// \ula_|i2s_intf_|PCM_INR[14]~0_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & ((\ula_|i2s_intf_|shiftreg [14]))) # (!\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & (\ula_|i2s_intf_|PCM_INR [14])))) # +// (!\ula_|i2s_intf_|Equal0~2_combout & (((\ula_|i2s_intf_|PCM_INR [14])))) + + .dataa(\ula_|i2s_intf_|Equal0~2_combout ), + .datab(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ), + .datac(\ula_|i2s_intf_|PCM_INR [14]), + .datad(\ula_|i2s_intf_|shiftreg [14]), + .cin(gnd), + .combout(\ula_|i2s_intf_|PCM_INR[14]~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|i2s_intf_|PCM_INR[14]~0 .lut_mask = 16'hF870; +defparam \ula_|i2s_intf_|PCM_INR[14]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y31_N17 +dffeas \ula_|i2s_intf_|PCM_INR[14] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .d(\ula_|i2s_intf_|PCM_INR[14]~0_combout ), + .asdata(vcc), + .clrn(!\reset~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|i2s_intf_|PCM_INR [14]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|i2s_intf_|PCM_INR[14] .is_wysiwyg = "true"; +defparam \ula_|i2s_intf_|PCM_INR[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y31_N24 cycloneive_lcell_comb \ula_|pcm_outr~0 ( // Equation(s): -// \ula_|pcm_outr~0_combout = (\ula_|i2s_intf_|PCM_INR [14]) # (\ula_|i2s_intf_|PCM_INL [14]) +// \ula_|pcm_outr~0_combout = (\ula_|i2s_intf_|PCM_INL [14]) # (\ula_|i2s_intf_|PCM_INR [14]) .dataa(gnd), .datab(gnd), - .datac(\ula_|i2s_intf_|PCM_INR [14]), - .datad(\ula_|i2s_intf_|PCM_INL [14]), + .datac(\ula_|i2s_intf_|PCM_INL [14]), + .datad(\ula_|i2s_intf_|PCM_INR [14]), .cin(gnd), .combout(\ula_|pcm_outr~0_combout ), .cout()); @@ -57680,7 +57413,7 @@ defparam \ula_|pcm_outr~0 .lut_mask = 16'hFFF0; defparam \ula_|pcm_outr~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y22_N7 +// Location: FF_X24_Y31_N25 dffeas \ula_|pcm_outl[12] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\ula_|pcm_outr~0_combout ), @@ -57699,24 +57432,24 @@ defparam \ula_|pcm_outl[12] .is_wysiwyg = "true"; defparam \ula_|pcm_outl[12] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N14 +// Location: LCCOMB_X23_Y31_N10 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~6 ( // Equation(s): // \ula_|i2s_intf_|shiftreg~6_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|pcm_outl [12]))) # (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|shiftreg [12])) .dataa(gnd), - .datab(\ula_|i2s_intf_|Equal0~2_combout ), - .datac(\ula_|i2s_intf_|shiftreg [12]), + .datab(\ula_|i2s_intf_|shiftreg [12]), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), .datad(\ula_|pcm_outl [12]), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~6_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~6 .lut_mask = 16'hFC30; +defparam \ula_|i2s_intf_|shiftreg~6 .lut_mask = 16'hFC0C; defparam \ula_|i2s_intf_|shiftreg~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N15 +// Location: FF_X23_Y31_N11 dffeas \ula_|i2s_intf_|shiftreg[13] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~6_combout ), @@ -57735,24 +57468,43 @@ defparam \ula_|i2s_intf_|shiftreg[13] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[13] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X24_Y30_N4 +// Location: FF_X23_Y14_N9 +dffeas \ula_|pcm_outl[13] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\D[3]~74_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|always0~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|pcm_outl [13]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|pcm_outl[13] .is_wysiwyg = "true"; +defparam \ula_|pcm_outl[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y31_N8 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~5 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~5_combout = (\ula_|i2s_intf_|Equal0~2_combout & (\ula_|pcm_outl [13])) # (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|shiftreg [13]))) +// \ula_|i2s_intf_|shiftreg~5_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|pcm_outl [13]))) # (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|shiftreg [13])) - .dataa(gnd), - .datab(\ula_|pcm_outl [13]), - .datac(\ula_|i2s_intf_|shiftreg [13]), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .dataa(\ula_|i2s_intf_|shiftreg [13]), + .datab(\ula_|i2s_intf_|Equal0~2_combout ), + .datac(gnd), + .datad(\ula_|pcm_outl [13]), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~5_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~5 .lut_mask = 16'hCCF0; +defparam \ula_|i2s_intf_|shiftreg~5 .lut_mask = 16'hEE22; defparam \ula_|i2s_intf_|shiftreg~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X24_Y30_N5 +// Location: FF_X23_Y31_N9 dffeas \ula_|i2s_intf_|shiftreg[14] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~5_combout ), @@ -57771,43 +57523,24 @@ defparam \ula_|i2s_intf_|shiftreg[14] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[14] .power_up = "low"; // synopsys translate_on -// Location: FF_X29_Y14_N31 -dffeas \ula_|pcm_outl[14] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(\D[4]~98_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|always0~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|pcm_outl [14]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|pcm_outl[14] .is_wysiwyg = "true"; -defparam \ula_|pcm_outl[14] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X28_Y22_N4 +// Location: LCCOMB_X23_Y31_N2 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~4 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~4_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|pcm_outl [14]))) # (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|shiftreg [14])) +// \ula_|i2s_intf_|shiftreg~4_combout = (\ula_|i2s_intf_|Equal0~2_combout & (\ula_|pcm_outl [14])) # (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|shiftreg [14]))) - .dataa(\ula_|i2s_intf_|shiftreg [14]), - .datab(gnd), - .datac(\ula_|pcm_outl [14]), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .dataa(\ula_|pcm_outl [14]), + .datab(\ula_|i2s_intf_|shiftreg [14]), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~4_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~4 .lut_mask = 16'hF0AA; +defparam \ula_|i2s_intf_|shiftreg~4 .lut_mask = 16'hACAC; defparam \ula_|i2s_intf_|shiftreg~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y22_N5 +// Location: FF_X23_Y31_N3 dffeas \ula_|i2s_intf_|shiftreg[15] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~4_combout ), @@ -57826,24 +57559,24 @@ defparam \ula_|i2s_intf_|shiftreg[15] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[15] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y22_N0 +// Location: LCCOMB_X23_Y32_N12 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~3 ( // Equation(s): -// \ula_|i2s_intf_|shiftreg~3_combout = (\ula_|i2s_intf_|shiftreg [15] & !\ula_|i2s_intf_|Equal0~2_combout ) +// \ula_|i2s_intf_|shiftreg~3_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [15]) - .dataa(gnd), + .dataa(\ula_|i2s_intf_|Equal0~2_combout ), .datab(gnd), .datac(\ula_|i2s_intf_|shiftreg [15]), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~3 .lut_mask = 16'h00F0; +defparam \ula_|i2s_intf_|shiftreg~3 .lut_mask = 16'h5050; defparam \ula_|i2s_intf_|shiftreg~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X28_Y22_N1 +// Location: FF_X23_Y32_N13 dffeas \ula_|i2s_intf_|shiftreg[16] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), .d(\ula_|i2s_intf_|shiftreg~3_combout ), @@ -57862,20 +57595,20 @@ defparam \ula_|i2s_intf_|shiftreg[16] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[16] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X28_Y22_N10 +// Location: LCCOMB_X23_Y32_N2 cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~0 ( // Equation(s): // \ula_|i2s_intf_|shiftreg~0_combout = (\ula_|i2s_intf_|shiftreg [16] & !\ula_|i2s_intf_|Equal0~2_combout ) - .dataa(gnd), - .datab(\ula_|i2s_intf_|shiftreg [16]), - .datac(gnd), - .datad(\ula_|i2s_intf_|Equal0~2_combout ), + .dataa(\ula_|i2s_intf_|shiftreg [16]), + .datab(gnd), + .datac(\ula_|i2s_intf_|Equal0~2_combout ), + .datad(gnd), .cin(gnd), .combout(\ula_|i2s_intf_|shiftreg~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|i2s_intf_|shiftreg~0 .lut_mask = 16'h00CC; +defparam \ula_|i2s_intf_|shiftreg~0 .lut_mask = 16'h0A0A; defparam \ula_|i2s_intf_|shiftreg~0 .sum_lutc_input = "datac"; // synopsys translate_on @@ -57898,32 +57631,85 @@ defparam \ula_|i2s_intf_|shiftreg[17] .is_wysiwyg = "true"; defparam \ula_|i2s_intf_|shiftreg[17] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X38_Y33_N8 -cycloneive_lcell_comb \ula_|video_|LessThan2~0 ( +// Location: LCCOMB_X31_Y10_N24 +cycloneive_lcell_comb \ula_|border[1]~feeder ( // Equation(s): -// \ula_|video_|LessThan2~0_combout = (!\ula_|video_|vga_vc [9] & (!\ula_|video_|vga_vc [8] & (!\ula_|video_|vga_vc [7] & !\ula_|video_|vga_vc [6]))) +// \ula_|border[1]~feeder_combout = \D[1]~32_combout - .dataa(\ula_|video_|vga_vc [9]), - .datab(\ula_|video_|vga_vc [8]), - .datac(\ula_|video_|vga_vc [7]), - .datad(\ula_|video_|vga_vc [6]), + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\D[1]~32_combout ), .cin(gnd), - .combout(\ula_|video_|LessThan2~0_combout ), + .combout(\ula_|border[1]~feeder_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|LessThan2~0 .lut_mask = 16'h0001; -defparam \ula_|video_|LessThan2~0 .sum_lutc_input = "datac"; +defparam \ula_|border[1]~feeder .lut_mask = 16'hFF00; +defparam \ula_|border[1]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y33_N4 +// Location: FF_X31_Y10_N25 +dffeas \ula_|border[1] ( + .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), + .d(\ula_|border[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|always0~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|border [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|border[1] .is_wysiwyg = "true"; +defparam \ula_|border[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X34_Y32_N30 +cycloneive_lcell_comb \ula_|video_|LessThan4~0 ( +// Equation(s): +// \ula_|video_|LessThan4~0_combout = (((!\ula_|video_|vga_hc [4] & !\ula_|video_|vga_hc [5])) # (!\ula_|video_|vga_hc [7])) # (!\ula_|video_|vga_hc [6]) + + .dataa(\ula_|video_|vga_hc [4]), + .datab(\ula_|video_|vga_hc [6]), + .datac(\ula_|video_|vga_hc [7]), + .datad(\ula_|video_|vga_hc [5]), + .cin(gnd), + .combout(\ula_|video_|LessThan4~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|LessThan4~0 .lut_mask = 16'h3F7F; +defparam \ula_|video_|LessThan4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y32_N26 +cycloneive_lcell_comb \ula_|video_|screen_en~0 ( +// Equation(s): +// \ula_|video_|screen_en~0_combout = (!\ula_|video_|vga_vc [9] & (\ula_|video_|vga_hc [9] $ (((\ula_|video_|vga_hc [8]) # (!\ula_|video_|LessThan4~0_combout ))))) + + .dataa(\ula_|video_|vga_hc [9]), + .datab(\ula_|video_|vga_vc [9]), + .datac(\ula_|video_|vga_hc [8]), + .datad(\ula_|video_|LessThan4~0_combout ), + .cin(gnd), + .combout(\ula_|video_|screen_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|screen_en~0 .lut_mask = 16'h1211; +defparam \ula_|video_|screen_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y32_N28 cycloneive_lcell_comb \ula_|video_|LessThan6~0 ( // Equation(s): -// \ula_|video_|LessThan6~0_combout = (!\ula_|video_|vga_vc [2] & (!\ula_|video_|vga_vc [3] & ((!\ula_|video_|vga_vc [0]) # (!\ula_|video_|vga_vc [1])))) +// \ula_|video_|LessThan6~0_combout = (!\ula_|video_|vga_vc [3] & (!\ula_|video_|vga_vc [2] & ((!\ula_|video_|vga_vc [1]) # (!\ula_|video_|vga_vc [0])))) - .dataa(\ula_|video_|vga_vc [2]), - .datab(\ula_|video_|vga_vc [3]), - .datac(\ula_|video_|vga_vc [1]), - .datad(\ula_|video_|vga_vc [0]), + .dataa(\ula_|video_|vga_vc [3]), + .datab(\ula_|video_|vga_vc [2]), + .datac(\ula_|video_|vga_vc [0]), + .datad(\ula_|video_|vga_vc [1]), .cin(gnd), .combout(\ula_|video_|LessThan6~0_combout ), .cout()); @@ -57932,76 +57718,128 @@ defparam \ula_|video_|LessThan6~0 .lut_mask = 16'h0111; defparam \ula_|video_|LessThan6~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y33_N30 +// Location: LCCOMB_X35_Y32_N12 +cycloneive_lcell_comb \ula_|video_|LessThan6~1 ( +// Equation(s): +// \ula_|video_|LessThan6~1_combout = ((!\ula_|video_|vga_vc [5] & ((\ula_|video_|LessThan6~0_combout ) # (!\ula_|video_|vga_vc [4])))) # (!\ula_|video_|vga_vc [6]) + + .dataa(\ula_|video_|vga_vc [4]), + .datab(\ula_|video_|vga_vc [6]), + .datac(\ula_|video_|vga_vc [5]), + .datad(\ula_|video_|LessThan6~0_combout ), + .cin(gnd), + .combout(\ula_|video_|LessThan6~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|LessThan6~1 .lut_mask = 16'h3F37; +defparam \ula_|video_|LessThan6~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y32_N22 +cycloneive_lcell_comb \ula_|video_|screen_en~1 ( +// Equation(s): +// \ula_|video_|screen_en~1_combout = (\ula_|video_|screen_en~0_combout & ((\ula_|video_|vga_vc [7] & ((\ula_|video_|LessThan6~1_combout ) # (!\ula_|video_|vga_vc [8]))) # (!\ula_|video_|vga_vc [7] & ((\ula_|video_|vga_vc [8]) # +// (!\ula_|video_|LessThan6~1_combout ))))) + + .dataa(\ula_|video_|vga_vc [7]), + .datab(\ula_|video_|vga_vc [8]), + .datac(\ula_|video_|screen_en~0_combout ), + .datad(\ula_|video_|LessThan6~1_combout ), + .cin(gnd), + .combout(\ula_|video_|screen_en~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|screen_en~1 .lut_mask = 16'hE070; +defparam \ula_|video_|screen_en~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y32_N14 +cycloneive_lcell_comb \ula_|video_|LessThan2~0 ( +// Equation(s): +// \ula_|video_|LessThan2~0_combout = (!\ula_|video_|vga_vc [9] & (!\ula_|video_|vga_vc [8] & (!\ula_|video_|vga_vc [6] & !\ula_|video_|vga_vc [7]))) + + .dataa(\ula_|video_|vga_vc [9]), + .datab(\ula_|video_|vga_vc [8]), + .datac(\ula_|video_|vga_vc [6]), + .datad(\ula_|video_|vga_vc [7]), + .cin(gnd), + .combout(\ula_|video_|LessThan2~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|LessThan2~0 .lut_mask = 16'h0001; +defparam \ula_|video_|LessThan2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y32_N12 cycloneive_lcell_comb \ula_|video_|LessThan2~1 ( // Equation(s): // \ula_|video_|LessThan2~1_combout = (\ula_|video_|LessThan2~0_combout & (((!\ula_|video_|vga_vc [4] & \ula_|video_|LessThan6~0_combout )) # (!\ula_|video_|vga_vc [5]))) - .dataa(\ula_|video_|vga_vc [5]), - .datab(\ula_|video_|vga_vc [4]), + .dataa(\ula_|video_|vga_vc [4]), + .datab(\ula_|video_|vga_vc [5]), .datac(\ula_|video_|LessThan2~0_combout ), .datad(\ula_|video_|LessThan6~0_combout ), .cin(gnd), .combout(\ula_|video_|LessThan2~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|LessThan2~1 .lut_mask = 16'h7050; +defparam \ula_|video_|LessThan2~1 .lut_mask = 16'h7030; defparam \ula_|video_|LessThan2~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y33_N16 +// Location: LCCOMB_X36_Y32_N4 cycloneive_lcell_comb \ula_|video_|LessThan3~0 ( // Equation(s): -// \ula_|video_|LessThan3~0_combout = ((\ula_|video_|LessThan6~0_combout & (!\ula_|video_|vga_vc [5] & \ula_|video_|Equal2~0_combout ))) # (!\ula_|video_|vga_vc [9]) +// \ula_|video_|LessThan3~0_combout = ((!\ula_|video_|vga_vc [5] & (\ula_|video_|LessThan6~0_combout & \ula_|video_|Equal2~0_combout ))) # (!\ula_|video_|vga_vc [9]) - .dataa(\ula_|video_|vga_vc [9]), + .dataa(\ula_|video_|vga_vc [5]), .datab(\ula_|video_|LessThan6~0_combout ), - .datac(\ula_|video_|vga_vc [5]), + .datac(\ula_|video_|vga_vc [9]), .datad(\ula_|video_|Equal2~0_combout ), .cin(gnd), .combout(\ula_|video_|LessThan3~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|LessThan3~0 .lut_mask = 16'h5D55; +defparam \ula_|video_|LessThan3~0 .lut_mask = 16'h4F0F; defparam \ula_|video_|LessThan3~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y33_N22 +// Location: LCCOMB_X34_Y32_N2 cycloneive_lcell_comb \ula_|video_|LessThan0~0 ( // Equation(s): -// \ula_|video_|LessThan0~0_combout = (!\ula_|video_|vga_hc [4] & (!\ula_|video_|vga_hc [6] & !\ula_|video_|vga_hc [5])) +// \ula_|video_|LessThan0~0_combout = (!\ula_|video_|vga_hc [6] & (!\ula_|video_|vga_hc [4] & !\ula_|video_|vga_hc [5])) - .dataa(\ula_|video_|vga_hc [4]), + .dataa(gnd), .datab(\ula_|video_|vga_hc [6]), - .datac(gnd), + .datac(\ula_|video_|vga_hc [4]), .datad(\ula_|video_|vga_hc [5]), .cin(gnd), .combout(\ula_|video_|LessThan0~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|LessThan0~0 .lut_mask = 16'h0011; +defparam \ula_|video_|LessThan0~0 .lut_mask = 16'h0003; defparam \ula_|video_|LessThan0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X39_Y33_N24 +// Location: LCCOMB_X34_Y32_N0 cycloneive_lcell_comb \ula_|video_|disp_enable~0 ( // Equation(s): -// \ula_|video_|disp_enable~0_combout = (\ula_|video_|vga_hc [8] & (((\ula_|video_|LessThan0~0_combout & !\ula_|video_|vga_hc [7])) # (!\ula_|video_|vga_hc [9]))) # (!\ula_|video_|vga_hc [8] & ((\ula_|video_|vga_hc [9]) # -// ((!\ula_|video_|LessThan0~0_combout & \ula_|video_|vga_hc [7])))) +// \ula_|video_|disp_enable~0_combout = (\ula_|video_|vga_hc [8] & (((!\ula_|video_|vga_hc [7] & \ula_|video_|LessThan0~0_combout )) # (!\ula_|video_|vga_hc [9]))) # (!\ula_|video_|vga_hc [8] & ((\ula_|video_|vga_hc [9]) # ((\ula_|video_|vga_hc [7] & +// !\ula_|video_|LessThan0~0_combout )))) - .dataa(\ula_|video_|LessThan0~0_combout ), + .dataa(\ula_|video_|vga_hc [7]), .datab(\ula_|video_|vga_hc [8]), - .datac(\ula_|video_|vga_hc [7]), - .datad(\ula_|video_|vga_hc [9]), + .datac(\ula_|video_|vga_hc [9]), + .datad(\ula_|video_|LessThan0~0_combout ), .cin(gnd), .combout(\ula_|video_|disp_enable~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|disp_enable~0 .lut_mask = 16'h3BDC; +defparam \ula_|video_|disp_enable~0 .lut_mask = 16'h7C3E; defparam \ula_|video_|disp_enable~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y33_N2 +// Location: LCCOMB_X36_Y32_N6 cycloneive_lcell_comb \ula_|video_|disp_enable~1 ( // Equation(s): // \ula_|video_|disp_enable~1_combout = (!\ula_|video_|LessThan2~1_combout & (\ula_|video_|LessThan3~0_combout & \ula_|video_|disp_enable~0_combout )) @@ -58018,239 +57856,7 @@ defparam \ula_|video_|disp_enable~1 .lut_mask = 16'h4400; defparam \ula_|video_|disp_enable~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y22_N11 -dffeas \ula_|border[1] ( - .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), - .d(gnd), - .asdata(\D[1]~34_combout ), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|always0~3_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|border [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|border[1] .is_wysiwyg = "true"; -defparam \ula_|border[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y33_N8 -cycloneive_lcell_comb \ula_|video_|LessThan6~1 ( -// Equation(s): -// \ula_|video_|LessThan6~1_combout = ((!\ula_|video_|vga_vc [5] & ((\ula_|video_|LessThan6~0_combout ) # (!\ula_|video_|vga_vc [4])))) # (!\ula_|video_|vga_vc [6]) - - .dataa(\ula_|video_|vga_vc [6]), - .datab(\ula_|video_|vga_vc [5]), - .datac(\ula_|video_|vga_vc [4]), - .datad(\ula_|video_|LessThan6~0_combout ), - .cin(gnd), - .combout(\ula_|video_|LessThan6~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|LessThan6~1 .lut_mask = 16'h7757; -defparam \ula_|video_|LessThan6~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N28 -cycloneive_lcell_comb \ula_|video_|LessThan4~0 ( -// Equation(s): -// \ula_|video_|LessThan4~0_combout = (((!\ula_|video_|vga_hc [4] & !\ula_|video_|vga_hc [5])) # (!\ula_|video_|vga_hc [7])) # (!\ula_|video_|vga_hc [6]) - - .dataa(\ula_|video_|vga_hc [4]), - .datab(\ula_|video_|vga_hc [5]), - .datac(\ula_|video_|vga_hc [6]), - .datad(\ula_|video_|vga_hc [7]), - .cin(gnd), - .combout(\ula_|video_|LessThan4~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|LessThan4~0 .lut_mask = 16'h1FFF; -defparam \ula_|video_|LessThan4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y33_N10 -cycloneive_lcell_comb \ula_|video_|screen_en~0 ( -// Equation(s): -// \ula_|video_|screen_en~0_combout = (!\ula_|video_|vga_vc [9] & (\ula_|video_|vga_hc [9] $ (((\ula_|video_|vga_hc [8]) # (!\ula_|video_|LessThan4~0_combout ))))) - - .dataa(\ula_|video_|vga_hc [9]), - .datab(\ula_|video_|vga_vc [9]), - .datac(\ula_|video_|LessThan4~0_combout ), - .datad(\ula_|video_|vga_hc [8]), - .cin(gnd), - .combout(\ula_|video_|screen_en~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|screen_en~0 .lut_mask = 16'h1121; -defparam \ula_|video_|screen_en~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X37_Y33_N22 -cycloneive_lcell_comb \ula_|video_|screen_en~1 ( -// Equation(s): -// \ula_|video_|screen_en~1_combout = (\ula_|video_|screen_en~0_combout & ((\ula_|video_|vga_vc [7] & ((\ula_|video_|LessThan6~1_combout ) # (!\ula_|video_|vga_vc [8]))) # (!\ula_|video_|vga_vc [7] & ((\ula_|video_|vga_vc [8]) # -// (!\ula_|video_|LessThan6~1_combout ))))) - - .dataa(\ula_|video_|vga_vc [7]), - .datab(\ula_|video_|vga_vc [8]), - .datac(\ula_|video_|LessThan6~1_combout ), - .datad(\ula_|video_|screen_en~0_combout ), - .cin(gnd), - .combout(\ula_|video_|screen_en~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|screen_en~1 .lut_mask = 16'hE700; -defparam \ula_|video_|screen_en~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y33_N28 -cycloneive_lcell_comb \ula_|video_|attr_prefetch[1]~feeder ( -// Equation(s): -// \ula_|video_|attr_prefetch[1]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|attr_prefetch[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|attr_prefetch[1]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|attr_prefetch[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N10 -cycloneive_lcell_comb \ula_|video_|Decoder0~1 ( -// Equation(s): -// \ula_|video_|Decoder0~1_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|vga_hc [3] & (\ula_|video_|vga_hc [1] & !\ula_|video_|vga_hc [0]))) - - .dataa(\ula_|video_|vga_hc [2]), - .datab(\ula_|video_|vga_hc [3]), - .datac(\ula_|video_|vga_hc [1]), - .datad(\ula_|video_|vga_hc [0]), - .cin(gnd), - .combout(\ula_|video_|Decoder0~1_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Decoder0~1 .lut_mask = 16'h0080; -defparam \ula_|video_|Decoder0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y33_N29 -dffeas \ula_|video_|attr_prefetch[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|attr_prefetch[1]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|attr_prefetch [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|attr_prefetch[1] .is_wysiwyg = "true"; -defparam \ula_|video_|attr_prefetch[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X34_Y31_N12 -cycloneive_lcell_comb \ula_|video_|Decoder0~0 ( -// Equation(s): -// \ula_|video_|Decoder0~0_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|vga_hc [3] & (\ula_|video_|vga_hc [1] & \ula_|video_|vga_hc [0]))) - - .dataa(\ula_|video_|vga_hc [2]), - .datab(\ula_|video_|vga_hc [3]), - .datac(\ula_|video_|vga_hc [1]), - .datad(\ula_|video_|vga_hc [0]), - .cin(gnd), - .combout(\ula_|video_|Decoder0~0_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|Decoder0~0 .lut_mask = 16'h8000; -defparam \ula_|video_|Decoder0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X37_Y33_N27 -dffeas \ula_|video_|attr[1] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|attr_prefetch [1]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|Decoder0~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|attr [1]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|attr[1] .is_wysiwyg = "true"; -defparam \ula_|video_|attr[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y33_N10 -cycloneive_lcell_comb \ula_|video_|attr_prefetch[4]~feeder ( -// Equation(s): -// \ula_|video_|attr_prefetch[4]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|attr_prefetch[4]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|attr_prefetch[4]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|attr_prefetch[4]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y33_N11 -dffeas \ula_|video_|attr_prefetch[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|attr_prefetch[4]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|attr_prefetch [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|attr_prefetch[4] .is_wysiwyg = "true"; -defparam \ula_|video_|attr_prefetch[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X37_Y33_N13 -dffeas \ula_|video_|attr[4] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|attr_prefetch [4]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|Decoder0~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|attr [4]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|attr[4] .is_wysiwyg = "true"; -defparam \ula_|video_|attr[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y33_N24 +// Location: LCCOMB_X38_Y32_N8 cycloneive_lcell_comb \ula_|video_|attr_prefetch[7]~feeder ( // Equation(s): // \ula_|video_|attr_prefetch[7]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 @@ -58267,7 +57873,24 @@ defparam \ula_|video_|attr_prefetch[7]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|attr_prefetch[7]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N25 +// Location: LCCOMB_X35_Y31_N24 +cycloneive_lcell_comb \ula_|video_|Decoder0~1 ( +// Equation(s): +// \ula_|video_|Decoder0~1_combout = (\ula_|video_|vga_hc [1] & (\ula_|video_|vga_hc [3] & (\ula_|video_|vga_hc [2] & !\ula_|video_|vga_hc [0]))) + + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|vga_hc [3]), + .datac(\ula_|video_|vga_hc [2]), + .datad(\ula_|video_|vga_hc [0]), + .cin(gnd), + .combout(\ula_|video_|Decoder0~1_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Decoder0~1 .lut_mask = 16'h0080; +defparam \ula_|video_|Decoder0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X38_Y32_N9 dffeas \ula_|video_|attr_prefetch[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr_prefetch[7]~feeder_combout ), @@ -58286,7 +57909,24 @@ defparam \ula_|video_|attr_prefetch[7] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[7] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y33_N5 +// Location: LCCOMB_X35_Y31_N2 +cycloneive_lcell_comb \ula_|video_|Decoder0~0 ( +// Equation(s): +// \ula_|video_|Decoder0~0_combout = (\ula_|video_|vga_hc [1] & (\ula_|video_|vga_hc [3] & (\ula_|video_|vga_hc [2] & \ula_|video_|vga_hc [0]))) + + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|vga_hc [3]), + .datac(\ula_|video_|vga_hc [2]), + .datad(\ula_|video_|vga_hc [0]), + .cin(gnd), + .combout(\ula_|video_|Decoder0~0_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|Decoder0~0 .lut_mask = 16'h8000; +defparam \ula_|video_|Decoder0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y32_N23 dffeas \ula_|video_|attr[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -58305,24 +57945,24 @@ defparam \ula_|video_|attr[7] .is_wysiwyg = "true"; defparam \ula_|video_|attr[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y33_N22 +// Location: LCCOMB_X35_Y31_N0 cycloneive_lcell_comb \ula_|video_|frame[0]~12 ( // Equation(s): -// \ula_|video_|frame[0]~12_combout = \ula_|video_|Equal3~1_combout $ (\ula_|video_|frame [0]) +// \ula_|video_|frame[0]~12_combout = \ula_|video_|frame [0] $ (\ula_|video_|Equal3~1_combout ) - .dataa(\ula_|video_|Equal3~1_combout ), + .dataa(gnd), .datab(gnd), .datac(\ula_|video_|frame [0]), - .datad(gnd), + .datad(\ula_|video_|Equal3~1_combout ), .cin(gnd), .combout(\ula_|video_|frame[0]~12_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|frame[0]~12 .lut_mask = 16'h5A5A; +defparam \ula_|video_|frame[0]~12 .lut_mask = 16'h0FF0; defparam \ula_|video_|frame[0]~12 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X34_Y33_N23 +// Location: FF_X35_Y31_N1 dffeas \ula_|video_|frame[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|frame[0]~12_combout ), @@ -58341,7 +57981,7 @@ defparam \ula_|video_|frame[0] .is_wysiwyg = "true"; defparam \ula_|video_|frame[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X35_Y33_N24 +// Location: LCCOMB_X35_Y32_N14 cycloneive_lcell_comb \ula_|video_|frame[1]~4 ( // Equation(s): // \ula_|video_|frame[1]~4_combout = (\ula_|video_|frame [0] & (\ula_|video_|frame [1] $ (VCC))) # (!\ula_|video_|frame [0] & (\ula_|video_|frame [1] & VCC)) @@ -58359,7 +57999,7 @@ defparam \ula_|video_|frame[1]~4 .lut_mask = 16'h6688; defparam \ula_|video_|frame[1]~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X35_Y33_N25 +// Location: FF_X35_Y32_N15 dffeas \ula_|video_|frame[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|frame[1]~4_combout ), @@ -58378,25 +58018,25 @@ defparam \ula_|video_|frame[1] .is_wysiwyg = "true"; defparam \ula_|video_|frame[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X35_Y33_N26 +// Location: LCCOMB_X35_Y32_N16 cycloneive_lcell_comb \ula_|video_|frame[2]~6 ( // Equation(s): // \ula_|video_|frame[2]~6_combout = (\ula_|video_|frame [2] & (!\ula_|video_|frame[1]~5 )) # (!\ula_|video_|frame [2] & ((\ula_|video_|frame[1]~5 ) # (GND))) // \ula_|video_|frame[2]~7 = CARRY((!\ula_|video_|frame[1]~5 ) # (!\ula_|video_|frame [2])) - .dataa(\ula_|video_|frame [2]), - .datab(gnd), + .dataa(gnd), + .datab(\ula_|video_|frame [2]), .datac(gnd), .datad(vcc), .cin(\ula_|video_|frame[1]~5 ), .combout(\ula_|video_|frame[2]~6_combout ), .cout(\ula_|video_|frame[2]~7 )); // synopsys translate_off -defparam \ula_|video_|frame[2]~6 .lut_mask = 16'h5A5F; +defparam \ula_|video_|frame[2]~6 .lut_mask = 16'h3C3F; defparam \ula_|video_|frame[2]~6 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X35_Y33_N27 +// Location: FF_X35_Y32_N17 dffeas \ula_|video_|frame[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|frame[2]~6_combout ), @@ -58415,7 +58055,7 @@ defparam \ula_|video_|frame[2] .is_wysiwyg = "true"; defparam \ula_|video_|frame[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X35_Y33_N28 +// Location: LCCOMB_X35_Y32_N18 cycloneive_lcell_comb \ula_|video_|frame[3]~8 ( // Equation(s): // \ula_|video_|frame[3]~8_combout = (\ula_|video_|frame [3] & (\ula_|video_|frame[2]~7 $ (GND))) # (!\ula_|video_|frame [3] & (!\ula_|video_|frame[2]~7 & VCC)) @@ -58433,7 +58073,7 @@ defparam \ula_|video_|frame[3]~8 .lut_mask = 16'hC30C; defparam \ula_|video_|frame[3]~8 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X35_Y33_N29 +// Location: FF_X35_Y32_N19 dffeas \ula_|video_|frame[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|frame[3]~8_combout ), @@ -58452,27 +58092,44 @@ defparam \ula_|video_|frame[3] .is_wysiwyg = "true"; defparam \ula_|video_|frame[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X35_Y33_N30 +// Location: LCCOMB_X35_Y32_N20 cycloneive_lcell_comb \ula_|video_|frame[4]~10 ( // Equation(s): -// \ula_|video_|frame[4]~10_combout = \ula_|video_|frame [4] $ (\ula_|video_|frame[3]~9 ) +// \ula_|video_|frame[4]~10_combout = \ula_|video_|frame[3]~9 $ (\ula_|video_|frame [4]) - .dataa(\ula_|video_|frame [4]), + .dataa(gnd), .datab(gnd), .datac(gnd), - .datad(gnd), + .datad(\ula_|video_|frame [4]), .cin(\ula_|video_|frame[3]~9 ), .combout(\ula_|video_|frame[4]~10_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|frame[4]~10 .lut_mask = 16'h5A5A; +defparam \ula_|video_|frame[4]~10 .lut_mask = 16'h0FF0; defparam \ula_|video_|frame[4]~10 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X35_Y33_N31 +// Location: LCCOMB_X37_Y32_N0 +cycloneive_lcell_comb \ula_|video_|frame[4]~feeder ( +// Equation(s): +// \ula_|video_|frame[4]~feeder_combout = \ula_|video_|frame[4]~10_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ula_|video_|frame[4]~10_combout ), + .cin(gnd), + .combout(\ula_|video_|frame[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|frame[4]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|frame[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y32_N1 dffeas \ula_|video_|frame[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|frame[4]~10_combout ), + .d(\ula_|video_|frame[4]~feeder_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -58488,7 +58145,7 @@ defparam \ula_|video_|frame[4] .is_wysiwyg = "true"; defparam \ula_|video_|frame[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N4 +// Location: LCCOMB_X37_Y32_N22 cycloneive_lcell_comb \ula_|video_|inverted ( // Equation(s): // \ula_|video_|inverted~combout = (\ula_|video_|attr [7] & \ula_|video_|frame [4]) @@ -58505,41 +58162,41 @@ defparam \ula_|video_|inverted .lut_mask = 16'hF000; defparam \ula_|video_|inverted .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N12 +// Location: LCCOMB_X38_Y32_N4 cycloneive_lcell_comb \ula_|video_|bits_prefetch[6]~feeder ( // Equation(s): // \ula_|video_|bits_prefetch[6]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 ), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 ), + .datad(gnd), .cin(gnd), .combout(\ula_|video_|bits_prefetch[6]~feeder_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|bits_prefetch[6]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|bits_prefetch[6]~feeder .lut_mask = 16'hF0F0; defparam \ula_|video_|bits_prefetch[6]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X34_Y31_N8 +// Location: LCCOMB_X35_Y31_N10 cycloneive_lcell_comb \ula_|video_|Decoder0~2 ( // Equation(s): -// \ula_|video_|Decoder0~2_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [1] & !\ula_|video_|vga_hc [0]))) +// \ula_|video_|Decoder0~2_combout = (!\ula_|video_|vga_hc [1] & (\ula_|video_|vga_hc [3] & (\ula_|video_|vga_hc [2] & !\ula_|video_|vga_hc [0]))) - .dataa(\ula_|video_|vga_hc [2]), + .dataa(\ula_|video_|vga_hc [1]), .datab(\ula_|video_|vga_hc [3]), - .datac(\ula_|video_|vga_hc [1]), + .datac(\ula_|video_|vga_hc [2]), .datad(\ula_|video_|vga_hc [0]), .cin(gnd), .combout(\ula_|video_|Decoder0~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Decoder0~2 .lut_mask = 16'h0008; +defparam \ula_|video_|Decoder0~2 .lut_mask = 16'h0040; defparam \ula_|video_|Decoder0~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N13 +// Location: FF_X38_Y32_N5 dffeas \ula_|video_|bits_prefetch[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits_prefetch[6]~feeder_combout ), @@ -58558,32 +58215,15 @@ defparam \ula_|video_|bits_prefetch[6] .is_wysiwyg = "true"; defparam \ula_|video_|bits_prefetch[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N6 -cycloneive_lcell_comb \ula_|video_|bits[6]~feeder ( -// Equation(s): -// \ula_|video_|bits[6]~feeder_combout = \ula_|video_|bits_prefetch [6] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ula_|video_|bits_prefetch [6]), - .cin(gnd), - .combout(\ula_|video_|bits[6]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|bits[6]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|bits[6]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X36_Y33_N7 +// Location: FF_X37_Y32_N27 dffeas \ula_|video_|bits[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|bits[6]~feeder_combout ), - .asdata(vcc), + .d(gnd), + .asdata(\ula_|video_|bits_prefetch [6]), .clrn(vcc), .aload(gnd), .sclr(gnd), - .sload(gnd), + .sload(vcc), .ena(\ula_|video_|Decoder0~0_combout ), .devclrn(devclrn), .devpor(devpor), @@ -58594,7 +58234,7 @@ defparam \ula_|video_|bits[6] .is_wysiwyg = "true"; defparam \ula_|video_|bits[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N22 +// Location: LCCOMB_X38_Y32_N10 cycloneive_lcell_comb \ula_|video_|bits_prefetch[4]~feeder ( // Equation(s): // \ula_|video_|bits_prefetch[4]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 @@ -58611,7 +58251,7 @@ defparam \ula_|video_|bits_prefetch[4]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits_prefetch[4]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N23 +// Location: FF_X38_Y32_N11 dffeas \ula_|video_|bits_prefetch[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits_prefetch[4]~feeder_combout ), @@ -58630,7 +58270,7 @@ defparam \ula_|video_|bits_prefetch[4] .is_wysiwyg = "true"; defparam \ula_|video_|bits_prefetch[4] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y33_N23 +// Location: FF_X37_Y32_N9 dffeas \ula_|video_|bits[4] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -58649,7 +58289,7 @@ defparam \ula_|video_|bits[4] .is_wysiwyg = "true"; defparam \ula_|video_|bits[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N18 +// Location: LCCOMB_X38_Y32_N26 cycloneive_lcell_comb \ula_|video_|bits_prefetch[5]~feeder ( // Equation(s): // \ula_|video_|bits_prefetch[5]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 @@ -58666,7 +58306,7 @@ defparam \ula_|video_|bits_prefetch[5]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits_prefetch[5]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N19 +// Location: FF_X38_Y32_N27 dffeas \ula_|video_|bits_prefetch[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits_prefetch[5]~feeder_combout ), @@ -58685,7 +58325,7 @@ defparam \ula_|video_|bits_prefetch[5] .is_wysiwyg = "true"; defparam \ula_|video_|bits_prefetch[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N18 +// Location: LCCOMB_X37_Y32_N12 cycloneive_lcell_comb \ula_|video_|bits[5]~feeder ( // Equation(s): // \ula_|video_|bits[5]~feeder_combout = \ula_|video_|bits_prefetch [5] @@ -58702,7 +58342,7 @@ defparam \ula_|video_|bits[5]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits[5]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X36_Y33_N19 +// Location: FF_X37_Y32_N13 dffeas \ula_|video_|bits[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits[5]~feeder_combout ), @@ -58721,7 +58361,7 @@ defparam \ula_|video_|bits[5] .is_wysiwyg = "true"; defparam \ula_|video_|bits[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N0 +// Location: LCCOMB_X38_Y32_N12 cycloneive_lcell_comb \ula_|video_|bits_prefetch[7]~feeder ( // Equation(s): // \ula_|video_|bits_prefetch[7]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 @@ -58738,7 +58378,7 @@ defparam \ula_|video_|bits_prefetch[7]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits_prefetch[7]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N1 +// Location: FF_X38_Y32_N13 dffeas \ula_|video_|bits_prefetch[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits_prefetch[7]~feeder_combout ), @@ -58757,7 +58397,7 @@ defparam \ula_|video_|bits_prefetch[7] .is_wysiwyg = "true"; defparam \ula_|video_|bits_prefetch[7] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y33_N1 +// Location: FF_X37_Y32_N19 dffeas \ula_|video_|bits[7] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -58776,41 +58416,41 @@ defparam \ula_|video_|bits[7] .is_wysiwyg = "true"; defparam \ula_|video_|bits[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N0 +// Location: LCCOMB_X37_Y32_N18 cycloneive_lcell_comb \ula_|video_|Mux0~0 ( // Equation(s): -// \ula_|video_|Mux0~0_combout = (\ula_|video_|vga_hc [1] & (((\ula_|video_|vga_hc [2])))) # (!\ula_|video_|vga_hc [1] & ((\ula_|video_|vga_hc [2] & (\ula_|video_|bits [5])) # (!\ula_|video_|vga_hc [2] & ((\ula_|video_|bits [7]))))) +// \ula_|video_|Mux0~0_combout = (\ula_|video_|vga_hc [2] & ((\ula_|video_|bits [5]) # ((\ula_|video_|vga_hc [1])))) # (!\ula_|video_|vga_hc [2] & (((\ula_|video_|bits [7] & !\ula_|video_|vga_hc [1])))) .dataa(\ula_|video_|bits [5]), - .datab(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|vga_hc [2]), .datac(\ula_|video_|bits [7]), - .datad(\ula_|video_|vga_hc [2]), + .datad(\ula_|video_|vga_hc [1]), .cin(gnd), .combout(\ula_|video_|Mux0~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Mux0~0 .lut_mask = 16'hEE30; +defparam \ula_|video_|Mux0~0 .lut_mask = 16'hCCB8; defparam \ula_|video_|Mux0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N22 +// Location: LCCOMB_X37_Y32_N8 cycloneive_lcell_comb \ula_|video_|Mux0~1 ( // Equation(s): // \ula_|video_|Mux0~1_combout = (\ula_|video_|vga_hc [1] & ((\ula_|video_|Mux0~0_combout & ((\ula_|video_|bits [4]))) # (!\ula_|video_|Mux0~0_combout & (\ula_|video_|bits [6])))) # (!\ula_|video_|vga_hc [1] & (((\ula_|video_|Mux0~0_combout )))) - .dataa(\ula_|video_|bits [6]), - .datab(\ula_|video_|vga_hc [1]), + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|bits [6]), .datac(\ula_|video_|bits [4]), .datad(\ula_|video_|Mux0~0_combout ), .cin(gnd), .combout(\ula_|video_|Mux0~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Mux0~1 .lut_mask = 16'hF388; +defparam \ula_|video_|Mux0~1 .lut_mask = 16'hF588; defparam \ula_|video_|Mux0~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N16 +// Location: LCCOMB_X38_Y32_N16 cycloneive_lcell_comb \ula_|video_|bits_prefetch[2]~feeder ( // Equation(s): // \ula_|video_|bits_prefetch[2]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 @@ -58827,7 +58467,7 @@ defparam \ula_|video_|bits_prefetch[2]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits_prefetch[2]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N17 +// Location: FF_X38_Y32_N17 dffeas \ula_|video_|bits_prefetch[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits_prefetch[2]~feeder_combout ), @@ -58846,7 +58486,7 @@ defparam \ula_|video_|bits_prefetch[2] .is_wysiwyg = "true"; defparam \ula_|video_|bits_prefetch[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N12 +// Location: LCCOMB_X37_Y32_N30 cycloneive_lcell_comb \ula_|video_|bits[2]~feeder ( // Equation(s): // \ula_|video_|bits[2]~feeder_combout = \ula_|video_|bits_prefetch [2] @@ -58863,7 +58503,7 @@ defparam \ula_|video_|bits[2]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits[2]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X36_Y33_N13 +// Location: FF_X37_Y32_N31 dffeas \ula_|video_|bits[2] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits[2]~feeder_combout ), @@ -58882,7 +58522,7 @@ defparam \ula_|video_|bits[2] .is_wysiwyg = "true"; defparam \ula_|video_|bits[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N14 +// Location: LCCOMB_X38_Y32_N6 cycloneive_lcell_comb \ula_|video_|bits_prefetch[0]~feeder ( // Equation(s): // \ula_|video_|bits_prefetch[0]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 @@ -58899,7 +58539,7 @@ defparam \ula_|video_|bits_prefetch[0]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits_prefetch[0]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N15 +// Location: FF_X38_Y32_N7 dffeas \ula_|video_|bits_prefetch[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits_prefetch[0]~feeder_combout ), @@ -58918,7 +58558,7 @@ defparam \ula_|video_|bits_prefetch[0] .is_wysiwyg = "true"; defparam \ula_|video_|bits_prefetch[0] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y33_N3 +// Location: FF_X37_Y32_N25 dffeas \ula_|video_|bits[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -58937,7 +58577,7 @@ defparam \ula_|video_|bits[0] .is_wysiwyg = "true"; defparam \ula_|video_|bits[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N6 +// Location: LCCOMB_X38_Y32_N2 cycloneive_lcell_comb \ula_|video_|bits_prefetch[1]~feeder ( // Equation(s): // \ula_|video_|bits_prefetch[1]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 @@ -58954,7 +58594,7 @@ defparam \ula_|video_|bits_prefetch[1]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits_prefetch[1]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N7 +// Location: FF_X38_Y32_N3 dffeas \ula_|video_|bits_prefetch[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits_prefetch[1]~feeder_combout ), @@ -58973,7 +58613,7 @@ defparam \ula_|video_|bits_prefetch[1] .is_wysiwyg = "true"; defparam \ula_|video_|bits_prefetch[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N26 +// Location: LCCOMB_X37_Y32_N28 cycloneive_lcell_comb \ula_|video_|bits[1]~feeder ( // Equation(s): // \ula_|video_|bits[1]~feeder_combout = \ula_|video_|bits_prefetch [1] @@ -58990,7 +58630,7 @@ defparam \ula_|video_|bits[1]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits[1]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X36_Y33_N27 +// Location: FF_X37_Y32_N29 dffeas \ula_|video_|bits[1] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits[1]~feeder_combout ), @@ -59009,7 +58649,7 @@ defparam \ula_|video_|bits[1] .is_wysiwyg = "true"; defparam \ula_|video_|bits[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N4 +// Location: LCCOMB_X38_Y32_N20 cycloneive_lcell_comb \ula_|video_|bits_prefetch[3]~feeder ( // Equation(s): // \ula_|video_|bits_prefetch[3]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 @@ -59026,7 +58666,7 @@ defparam \ula_|video_|bits_prefetch[3]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|bits_prefetch[3]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N5 +// Location: FF_X38_Y32_N21 dffeas \ula_|video_|bits_prefetch[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|bits_prefetch[3]~feeder_combout ), @@ -59045,7 +58685,7 @@ defparam \ula_|video_|bits_prefetch[3] .is_wysiwyg = "true"; defparam \ula_|video_|bits_prefetch[3] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y33_N25 +// Location: FF_X37_Y32_N7 dffeas \ula_|video_|bits[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -59064,109 +58704,219 @@ defparam \ula_|video_|bits[3] .is_wysiwyg = "true"; defparam \ula_|video_|bits[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N24 +// Location: LCCOMB_X37_Y32_N6 cycloneive_lcell_comb \ula_|video_|Mux0~2 ( // Equation(s): // \ula_|video_|Mux0~2_combout = (\ula_|video_|vga_hc [1] & (((\ula_|video_|vga_hc [2])))) # (!\ula_|video_|vga_hc [1] & ((\ula_|video_|vga_hc [2] & (\ula_|video_|bits [1])) # (!\ula_|video_|vga_hc [2] & ((\ula_|video_|bits [3]))))) - .dataa(\ula_|video_|bits [1]), - .datab(\ula_|video_|vga_hc [1]), + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|bits [1]), .datac(\ula_|video_|bits [3]), .datad(\ula_|video_|vga_hc [2]), .cin(gnd), .combout(\ula_|video_|Mux0~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Mux0~2 .lut_mask = 16'hEE30; +defparam \ula_|video_|Mux0~2 .lut_mask = 16'hEE50; defparam \ula_|video_|Mux0~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N2 +// Location: LCCOMB_X37_Y32_N24 cycloneive_lcell_comb \ula_|video_|Mux0~3 ( // Equation(s): // \ula_|video_|Mux0~3_combout = (\ula_|video_|vga_hc [1] & ((\ula_|video_|Mux0~2_combout & ((\ula_|video_|bits [0]))) # (!\ula_|video_|Mux0~2_combout & (\ula_|video_|bits [2])))) # (!\ula_|video_|vga_hc [1] & (((\ula_|video_|Mux0~2_combout )))) - .dataa(\ula_|video_|bits [2]), - .datab(\ula_|video_|vga_hc [1]), + .dataa(\ula_|video_|vga_hc [1]), + .datab(\ula_|video_|bits [2]), .datac(\ula_|video_|bits [0]), .datad(\ula_|video_|Mux0~2_combout ), .cin(gnd), .combout(\ula_|video_|Mux0~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Mux0~3 .lut_mask = 16'hF388; +defparam \ula_|video_|Mux0~3 .lut_mask = 16'hF588; defparam \ula_|video_|Mux0~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N10 +// Location: LCCOMB_X37_Y32_N20 cycloneive_lcell_comb \ula_|video_|cindex[1]~0 ( // Equation(s): // \ula_|video_|cindex[1]~0_combout = \ula_|video_|inverted~combout $ (((\ula_|video_|vga_hc [3] & ((\ula_|video_|Mux0~3_combout ))) # (!\ula_|video_|vga_hc [3] & (\ula_|video_|Mux0~1_combout )))) - .dataa(\ula_|video_|vga_hc [3]), - .datab(\ula_|video_|inverted~combout ), + .dataa(\ula_|video_|inverted~combout ), + .datab(\ula_|video_|vga_hc [3]), .datac(\ula_|video_|Mux0~1_combout ), .datad(\ula_|video_|Mux0~3_combout ), .cin(gnd), .combout(\ula_|video_|cindex[1]~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|cindex[1]~0 .lut_mask = 16'h369C; +defparam \ula_|video_|cindex[1]~0 .lut_mask = 16'h569A; defparam \ula_|video_|cindex[1]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y33_N12 +// Location: LCCOMB_X38_Y32_N14 +cycloneive_lcell_comb \ula_|video_|attr_prefetch[4]~feeder ( +// Equation(s): +// \ula_|video_|attr_prefetch[4]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ula_|video_|attr_prefetch[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|attr_prefetch[4]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|attr_prefetch[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X38_Y32_N15 +dffeas \ula_|video_|attr_prefetch[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|attr_prefetch[4]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|Decoder0~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|attr_prefetch [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|attr_prefetch[4] .is_wysiwyg = "true"; +defparam \ula_|video_|attr_prefetch[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X36_Y32_N17 +dffeas \ula_|video_|attr[4] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|attr_prefetch [4]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|attr [4]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|attr[4] .is_wysiwyg = "true"; +defparam \ula_|video_|attr[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y32_N28 +cycloneive_lcell_comb \ula_|video_|attr_prefetch[1]~feeder ( +// Equation(s): +// \ula_|video_|attr_prefetch[1]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ula_|video_|attr_prefetch[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|attr_prefetch[1]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|attr_prefetch[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X38_Y32_N29 +dffeas \ula_|video_|attr_prefetch[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|attr_prefetch[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|Decoder0~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|attr_prefetch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|attr_prefetch[1] .is_wysiwyg = "true"; +defparam \ula_|video_|attr_prefetch[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X36_Y32_N7 +dffeas \ula_|video_|attr[1] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|attr_prefetch [1]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|attr [1]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|attr[1] .is_wysiwyg = "true"; +defparam \ula_|video_|attr[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y32_N16 cycloneive_lcell_comb \ula_|video_|cindex[1]~1 ( // Equation(s): -// \ula_|video_|cindex[1]~1_combout = (\ula_|video_|cindex[1]~0_combout & (\ula_|video_|attr [1])) # (!\ula_|video_|cindex[1]~0_combout & ((\ula_|video_|attr [4]))) +// \ula_|video_|cindex[1]~1_combout = (\ula_|video_|cindex[1]~0_combout & ((\ula_|video_|attr [1]))) # (!\ula_|video_|cindex[1]~0_combout & (\ula_|video_|attr [4])) - .dataa(\ula_|video_|attr [1]), + .dataa(\ula_|video_|cindex[1]~0_combout ), .datab(gnd), .datac(\ula_|video_|attr [4]), - .datad(\ula_|video_|cindex[1]~0_combout ), + .datad(\ula_|video_|attr [1]), .cin(gnd), .combout(\ula_|video_|cindex[1]~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|cindex[1]~1 .lut_mask = 16'hAAF0; +defparam \ula_|video_|cindex[1]~1 .lut_mask = 16'hFA50; defparam \ula_|video_|cindex[1]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y33_N24 +// Location: LCCOMB_X36_Y32_N26 cycloneive_lcell_comb \ula_|video_|VGA_R[0]~0 ( // Equation(s): // \ula_|video_|VGA_R[0]~0_combout = (\ula_|video_|disp_enable~1_combout & ((\ula_|video_|screen_en~1_combout & ((\ula_|video_|cindex[1]~1_combout ))) # (!\ula_|video_|screen_en~1_combout & (\ula_|border [1])))) - .dataa(\ula_|video_|disp_enable~1_combout ), - .datab(\ula_|border [1]), - .datac(\ula_|video_|screen_en~1_combout ), + .dataa(\ula_|border [1]), + .datab(\ula_|video_|screen_en~1_combout ), + .datac(\ula_|video_|disp_enable~1_combout ), .datad(\ula_|video_|cindex[1]~1_combout ), .cin(gnd), .combout(\ula_|video_|VGA_R[0]~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|VGA_R[0]~0 .lut_mask = 16'hA808; +defparam \ula_|video_|VGA_R[0]~0 .lut_mask = 16'hE020; defparam \ula_|video_|VGA_R[0]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N26 +// Location: LCCOMB_X38_Y32_N18 cycloneive_lcell_comb \ula_|video_|attr_prefetch[6]~feeder ( // Equation(s): // \ula_|video_|attr_prefetch[6]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 ), + .datac(\ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 ), + .datad(gnd), .cin(gnd), .combout(\ula_|video_|attr_prefetch[6]~feeder_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|attr_prefetch[6]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|attr_prefetch[6]~feeder .lut_mask = 16'hF0F0; defparam \ula_|video_|attr_prefetch[6]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N27 +// Location: FF_X38_Y32_N19 dffeas \ula_|video_|attr_prefetch[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr_prefetch[6]~feeder_combout ), @@ -59185,7 +58935,7 @@ defparam \ula_|video_|attr_prefetch[6] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[6] .power_up = "low"; // synopsys translate_on -// Location: FF_X38_Y33_N1 +// Location: FF_X36_Y32_N9 dffeas \ula_|video_|attr[6] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -59204,7 +58954,7 @@ defparam \ula_|video_|attr[6] .is_wysiwyg = "true"; defparam \ula_|video_|attr[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X38_Y33_N0 +// Location: LCCOMB_X36_Y32_N8 cycloneive_lcell_comb \ula_|video_|VGA_B[1]~0 ( // Equation(s): // \ula_|video_|VGA_B[1]~0_combout = (!\ula_|video_|LessThan2~1_combout & (\ula_|video_|LessThan3~0_combout & (\ula_|video_|attr [6] & \ula_|video_|disp_enable~0_combout ))) @@ -59221,28 +58971,28 @@ defparam \ula_|video_|VGA_B[1]~0 .lut_mask = 16'h4000; defparam \ula_|video_|VGA_B[1]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y33_N2 +// Location: LCCOMB_X36_Y32_N30 cycloneive_lcell_comb \ula_|video_|VGA_R[1]~1 ( // Equation(s): // \ula_|video_|VGA_R[1]~1_combout = (\ula_|video_|screen_en~1_combout & (\ula_|video_|VGA_B[1]~0_combout & \ula_|video_|cindex[1]~1_combout )) .dataa(\ula_|video_|screen_en~1_combout ), - .datab(gnd), - .datac(\ula_|video_|VGA_B[1]~0_combout ), + .datab(\ula_|video_|VGA_B[1]~0_combout ), + .datac(gnd), .datad(\ula_|video_|cindex[1]~1_combout ), .cin(gnd), .combout(\ula_|video_|VGA_R[1]~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|VGA_R[1]~1 .lut_mask = 16'hA000; +defparam \ula_|video_|VGA_R[1]~1 .lut_mask = 16'h8800; defparam \ula_|video_|VGA_R[1]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y12_N17 +// Location: FF_X31_Y10_N27 dffeas \ula_|border[2] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), - .asdata(\D[2]~46_combout ), + .asdata(\D[2]~39_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), @@ -59257,62 +59007,7 @@ defparam \ula_|border[2] .is_wysiwyg = "true"; defparam \ula_|border[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N8 -cycloneive_lcell_comb \ula_|video_|attr_prefetch[2]~feeder ( -// Equation(s): -// \ula_|video_|attr_prefetch[2]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 ), - .cin(gnd), - .combout(\ula_|video_|attr_prefetch[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \ula_|video_|attr_prefetch[2]~feeder .lut_mask = 16'hFF00; -defparam \ula_|video_|attr_prefetch[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y33_N9 -dffeas \ula_|video_|attr_prefetch[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(\ula_|video_|attr_prefetch[2]~feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\ula_|video_|Decoder0~1_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|attr_prefetch [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|attr_prefetch[2] .is_wysiwyg = "true"; -defparam \ula_|video_|attr_prefetch[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X36_Y33_N21 -dffeas \ula_|video_|attr[2] ( - .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), - .d(gnd), - .asdata(\ula_|video_|attr_prefetch [2]), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\ula_|video_|Decoder0~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\ula_|video_|attr [2]), - .prn(vcc)); -// synopsys translate_off -defparam \ula_|video_|attr[2] .is_wysiwyg = "true"; -defparam \ula_|video_|attr[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y33_N30 +// Location: LCCOMB_X38_Y32_N22 cycloneive_lcell_comb \ula_|video_|attr_prefetch[5]~feeder ( // Equation(s): // \ula_|video_|attr_prefetch[5]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 @@ -59329,7 +59024,7 @@ defparam \ula_|video_|attr_prefetch[5]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|attr_prefetch[5]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N31 +// Location: FF_X38_Y32_N23 dffeas \ula_|video_|attr_prefetch[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr_prefetch[5]~feeder_combout ), @@ -59348,7 +59043,7 @@ defparam \ula_|video_|attr_prefetch[5] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[5] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y33_N15 +// Location: FF_X36_Y32_N21 dffeas \ula_|video_|attr[5] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -59367,24 +59062,79 @@ defparam \ula_|video_|attr[5] .is_wysiwyg = "true"; defparam \ula_|video_|attr[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N14 -cycloneive_lcell_comb \ula_|video_|cindex[2]~2 ( +// Location: LCCOMB_X38_Y32_N0 +cycloneive_lcell_comb \ula_|video_|attr_prefetch[2]~feeder ( // Equation(s): -// \ula_|video_|cindex[2]~2_combout = (\ula_|video_|cindex[1]~0_combout & (\ula_|video_|attr [2])) # (!\ula_|video_|cindex[1]~0_combout & ((\ula_|video_|attr [5]))) +// \ula_|video_|attr_prefetch[2]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 .dataa(gnd), - .datab(\ula_|video_|attr [2]), + .datab(gnd), + .datac(gnd), + .datad(\ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 ), + .cin(gnd), + .combout(\ula_|video_|attr_prefetch[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \ula_|video_|attr_prefetch[2]~feeder .lut_mask = 16'hFF00; +defparam \ula_|video_|attr_prefetch[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X38_Y32_N1 +dffeas \ula_|video_|attr_prefetch[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\ula_|video_|attr_prefetch[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\ula_|video_|Decoder0~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|attr_prefetch [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|attr_prefetch[2] .is_wysiwyg = "true"; +defparam \ula_|video_|attr_prefetch[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X36_Y32_N19 +dffeas \ula_|video_|attr[2] ( + .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\ula_|video_|attr_prefetch [2]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\ula_|video_|Decoder0~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\ula_|video_|attr [2]), + .prn(vcc)); +// synopsys translate_off +defparam \ula_|video_|attr[2] .is_wysiwyg = "true"; +defparam \ula_|video_|attr[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y32_N20 +cycloneive_lcell_comb \ula_|video_|cindex[2]~2 ( +// Equation(s): +// \ula_|video_|cindex[2]~2_combout = (\ula_|video_|cindex[1]~0_combout & ((\ula_|video_|attr [2]))) # (!\ula_|video_|cindex[1]~0_combout & (\ula_|video_|attr [5])) + + .dataa(\ula_|video_|cindex[1]~0_combout ), + .datab(gnd), .datac(\ula_|video_|attr [5]), - .datad(\ula_|video_|cindex[1]~0_combout ), + .datad(\ula_|video_|attr [2]), .cin(gnd), .combout(\ula_|video_|cindex[2]~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|cindex[2]~2 .lut_mask = 16'hCCF0; +defparam \ula_|video_|cindex[2]~2 .lut_mask = 16'hFA50; defparam \ula_|video_|cindex[2]~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X38_Y33_N26 +// Location: LCCOMB_X36_Y32_N22 cycloneive_lcell_comb \ula_|video_|VGA_G[0]~0 ( // Equation(s): // \ula_|video_|VGA_G[0]~0_combout = (\ula_|video_|disp_enable~1_combout & ((\ula_|video_|screen_en~1_combout & ((\ula_|video_|cindex[2]~2_combout ))) # (!\ula_|video_|screen_en~1_combout & (\ula_|border [2])))) @@ -59401,15 +59151,15 @@ defparam \ula_|video_|VGA_G[0]~0 .lut_mask = 16'hE020; defparam \ula_|video_|VGA_G[0]~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N20 +// Location: LCCOMB_X36_Y32_N18 cycloneive_lcell_comb \ula_|video_|VGA_G[1]~1 ( // Equation(s): -// \ula_|video_|VGA_G[1]~1_combout = (\ula_|video_|VGA_B[1]~0_combout & (\ula_|video_|cindex[2]~2_combout & \ula_|video_|screen_en~1_combout )) +// \ula_|video_|VGA_G[1]~1_combout = (\ula_|video_|VGA_B[1]~0_combout & (\ula_|video_|screen_en~1_combout & \ula_|video_|cindex[2]~2_combout )) .dataa(\ula_|video_|VGA_B[1]~0_combout ), - .datab(\ula_|video_|cindex[2]~2_combout ), + .datab(\ula_|video_|screen_en~1_combout ), .datac(gnd), - .datad(\ula_|video_|screen_en~1_combout ), + .datad(\ula_|video_|cindex[2]~2_combout ), .cin(gnd), .combout(\ula_|video_|VGA_G[1]~1_combout ), .cout()); @@ -59418,11 +59168,11 @@ defparam \ula_|video_|VGA_G[1]~1 .lut_mask = 16'h8800; defparam \ula_|video_|VGA_G[1]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y22_N1 +// Location: FF_X23_Y14_N19 dffeas \ula_|border[0] ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), - .asdata(\D[0]~58_combout ), + .asdata(\D[0]~46_combout ), .clrn(vcc), .aload(gnd), .sclr(gnd), @@ -59437,7 +59187,7 @@ defparam \ula_|border[0] .is_wysiwyg = "true"; defparam \ula_|border[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N20 +// Location: LCCOMB_X38_Y32_N24 cycloneive_lcell_comb \ula_|video_|attr_prefetch[0]~feeder ( // Equation(s): // \ula_|video_|attr_prefetch[0]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 @@ -59454,7 +59204,7 @@ defparam \ula_|video_|attr_prefetch[0]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|attr_prefetch[0]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N21 +// Location: FF_X38_Y32_N25 dffeas \ula_|video_|attr_prefetch[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr_prefetch[0]~feeder_combout ), @@ -59473,7 +59223,7 @@ defparam \ula_|video_|attr_prefetch[0] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X37_Y33_N28 +// Location: LCCOMB_X37_Y32_N10 cycloneive_lcell_comb \ula_|video_|attr[0]~feeder ( // Equation(s): // \ula_|video_|attr[0]~feeder_combout = \ula_|video_|attr_prefetch [0] @@ -59490,7 +59240,7 @@ defparam \ula_|video_|attr[0]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|attr[0]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X37_Y33_N29 +// Location: FF_X37_Y32_N11 dffeas \ula_|video_|attr[0] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr[0]~feeder_combout ), @@ -59509,7 +59259,7 @@ defparam \ula_|video_|attr[0] .is_wysiwyg = "true"; defparam \ula_|video_|attr[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y33_N2 +// Location: LCCOMB_X38_Y32_N30 cycloneive_lcell_comb \ula_|video_|attr_prefetch[3]~feeder ( // Equation(s): // \ula_|video_|attr_prefetch[3]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 @@ -59526,7 +59276,7 @@ defparam \ula_|video_|attr_prefetch[3]~feeder .lut_mask = 16'hFF00; defparam \ula_|video_|attr_prefetch[3]~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X32_Y33_N3 +// Location: FF_X38_Y32_N31 dffeas \ula_|video_|attr_prefetch[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|attr_prefetch[3]~feeder_combout ), @@ -59545,7 +59295,7 @@ defparam \ula_|video_|attr_prefetch[3] .is_wysiwyg = "true"; defparam \ula_|video_|attr_prefetch[3] .power_up = "low"; // synopsys translate_on -// Location: FF_X36_Y33_N29 +// Location: FF_X37_Y32_N17 dffeas \ula_|video_|attr[3] ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(gnd), @@ -59564,48 +59314,48 @@ defparam \ula_|video_|attr[3] .is_wysiwyg = "true"; defparam \ula_|video_|attr[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X36_Y33_N28 +// Location: LCCOMB_X37_Y32_N16 cycloneive_lcell_comb \ula_|video_|cindex[0]~3 ( // Equation(s): // \ula_|video_|cindex[0]~3_combout = (\ula_|video_|cindex[1]~0_combout & (\ula_|video_|attr [0])) # (!\ula_|video_|cindex[1]~0_combout & ((\ula_|video_|attr [3]))) - .dataa(gnd), - .datab(\ula_|video_|attr [0]), + .dataa(\ula_|video_|attr [0]), + .datab(gnd), .datac(\ula_|video_|attr [3]), .datad(\ula_|video_|cindex[1]~0_combout ), .cin(gnd), .combout(\ula_|video_|cindex[0]~3_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|cindex[0]~3 .lut_mask = 16'hCCF0; +defparam \ula_|video_|cindex[0]~3 .lut_mask = 16'hAAF0; defparam \ula_|video_|cindex[0]~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y33_N30 +// Location: LCCOMB_X37_Y32_N14 cycloneive_lcell_comb \ula_|video_|VGA_B[0]~1 ( // Equation(s): // \ula_|video_|VGA_B[0]~1_combout = (\ula_|video_|disp_enable~1_combout & ((\ula_|video_|screen_en~1_combout & ((\ula_|video_|cindex[0]~3_combout ))) # (!\ula_|video_|screen_en~1_combout & (\ula_|border [0])))) - .dataa(\ula_|video_|disp_enable~1_combout ), + .dataa(\ula_|video_|screen_en~1_combout ), .datab(\ula_|border [0]), - .datac(\ula_|video_|screen_en~1_combout ), + .datac(\ula_|video_|disp_enable~1_combout ), .datad(\ula_|video_|cindex[0]~3_combout ), .cin(gnd), .combout(\ula_|video_|VGA_B[0]~1_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|VGA_B[0]~1 .lut_mask = 16'hA808; +defparam \ula_|video_|VGA_B[0]~1 .lut_mask = 16'hE040; defparam \ula_|video_|VGA_B[0]~1 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y33_N0 +// Location: LCCOMB_X37_Y32_N4 cycloneive_lcell_comb \ula_|video_|VGA_B[1]~2 ( // Equation(s): -// \ula_|video_|VGA_B[1]~2_combout = (\ula_|video_|screen_en~1_combout & (\ula_|video_|VGA_B[1]~0_combout & \ula_|video_|cindex[0]~3_combout )) +// \ula_|video_|VGA_B[1]~2_combout = (\ula_|video_|VGA_B[1]~0_combout & (\ula_|video_|screen_en~1_combout & \ula_|video_|cindex[0]~3_combout )) - .dataa(\ula_|video_|screen_en~1_combout ), + .dataa(\ula_|video_|VGA_B[1]~0_combout ), .datab(gnd), - .datac(\ula_|video_|VGA_B[1]~0_combout ), + .datac(\ula_|video_|screen_en~1_combout ), .datad(\ula_|video_|cindex[0]~3_combout ), .cin(gnd), .combout(\ula_|video_|VGA_B[1]~2_combout ), @@ -59615,24 +59365,24 @@ defparam \ula_|video_|VGA_B[1]~2 .lut_mask = 16'hA000; defparam \ula_|video_|VGA_B[1]~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X37_Y33_N26 +// Location: LCCOMB_X35_Y31_N22 cycloneive_lcell_comb \ula_|video_|Equal0~2 ( // Equation(s): -// \ula_|video_|Equal0~2_combout = (\ula_|video_|vga_hc [6] & (!\ula_|video_|vga_hc [9] & !\ula_|video_|vga_hc [8])) +// \ula_|video_|Equal0~2_combout = (!\ula_|video_|vga_hc [8] & (\ula_|video_|vga_hc [6] & !\ula_|video_|vga_hc [9])) - .dataa(\ula_|video_|vga_hc [6]), - .datab(\ula_|video_|vga_hc [9]), - .datac(gnd), - .datad(\ula_|video_|vga_hc [8]), + .dataa(gnd), + .datab(\ula_|video_|vga_hc [8]), + .datac(\ula_|video_|vga_hc [6]), + .datad(\ula_|video_|vga_hc [9]), .cin(gnd), .combout(\ula_|video_|Equal0~2_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Equal0~2 .lut_mask = 16'h0022; +defparam \ula_|video_|Equal0~2 .lut_mask = 16'h0030; defparam \ula_|video_|Equal0~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X37_Y33_N7 +// Location: FF_X35_Y31_N21 dffeas \ula_|video_|VGA_HS~_Duplicate_1 ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|Selector0~0_combout ), @@ -59651,21 +59401,21 @@ defparam \ula_|video_|VGA_HS~_Duplicate_1 .is_wysiwyg = "true"; defparam \ula_|video_|VGA_HS~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X37_Y33_N6 +// Location: LCCOMB_X35_Y31_N20 cycloneive_lcell_comb \ula_|video_|Selector0~0 ( // Equation(s): -// \ula_|video_|Selector0~0_combout = (\ula_|video_|Equal0~2_combout & ((\ula_|video_|Equal0~1_combout ) # ((\ula_|video_|Equal1~0_combout & \ula_|video_|VGA_HS~_Duplicate_1_q )))) # (!\ula_|video_|Equal0~2_combout & (\ula_|video_|Equal1~0_combout & -// (\ula_|video_|VGA_HS~_Duplicate_1_q ))) +// \ula_|video_|Selector0~0_combout = (\ula_|video_|Equal0~2_combout & ((\ula_|video_|Equal0~1_combout ) # ((\ula_|video_|VGA_HS~_Duplicate_1_q & \ula_|video_|Equal1~0_combout )))) # (!\ula_|video_|Equal0~2_combout & (((\ula_|video_|VGA_HS~_Duplicate_1_q +// & \ula_|video_|Equal1~0_combout )))) .dataa(\ula_|video_|Equal0~2_combout ), - .datab(\ula_|video_|Equal1~0_combout ), + .datab(\ula_|video_|Equal0~1_combout ), .datac(\ula_|video_|VGA_HS~_Duplicate_1_q ), - .datad(\ula_|video_|Equal0~1_combout ), + .datad(\ula_|video_|Equal1~0_combout ), .cin(gnd), .combout(\ula_|video_|Selector0~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Selector0~0 .lut_mask = 16'hEAC0; +defparam \ula_|video_|Selector0~0 .lut_mask = 16'hF888; defparam \ula_|video_|Selector0~0 .sum_lutc_input = "datac"; // synopsys translate_on @@ -59688,7 +59438,7 @@ defparam \ula_|video_|VGA_HS .is_wysiwyg = "true"; defparam \ula_|video_|VGA_HS .power_up = "low"; // synopsys translate_on -// Location: FF_X34_Y33_N25 +// Location: FF_X35_Y32_N5 dffeas \ula_|video_|VGA_VS~_Duplicate_1 ( .clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), .d(\ula_|video_|Selector1~0_combout ), @@ -59707,21 +59457,21 @@ defparam \ula_|video_|VGA_VS~_Duplicate_1 .is_wysiwyg = "true"; defparam \ula_|video_|VGA_VS~_Duplicate_1 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X34_Y33_N24 +// Location: LCCOMB_X35_Y32_N4 cycloneive_lcell_comb \ula_|video_|Selector1~0 ( // Equation(s): -// \ula_|video_|Selector1~0_combout = (\ula_|video_|Equal3~1_combout & (\ula_|video_|Equal2~2_combout & ((\ula_|video_|vga_vc [1])))) # (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|VGA_VS~_Duplicate_1_q ) # ((\ula_|video_|Equal2~2_combout & -// \ula_|video_|vga_vc [1])))) +// \ula_|video_|Selector1~0_combout = (\ula_|video_|Equal2~2_combout & ((\ula_|video_|vga_vc [1]) # ((\ula_|video_|VGA_VS~_Duplicate_1_q & !\ula_|video_|Equal3~1_combout )))) # (!\ula_|video_|Equal2~2_combout & (((\ula_|video_|VGA_VS~_Duplicate_1_q & +// !\ula_|video_|Equal3~1_combout )))) - .dataa(\ula_|video_|Equal3~1_combout ), - .datab(\ula_|video_|Equal2~2_combout ), + .dataa(\ula_|video_|Equal2~2_combout ), + .datab(\ula_|video_|vga_vc [1]), .datac(\ula_|video_|VGA_VS~_Duplicate_1_q ), - .datad(\ula_|video_|vga_vc [1]), + .datad(\ula_|video_|Equal3~1_combout ), .cin(gnd), .combout(\ula_|video_|Selector1~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|video_|Selector1~0 .lut_mask = 16'hDC50; +defparam \ula_|video_|Selector1~0 .lut_mask = 16'h88F8; defparam \ula_|video_|Selector1~0 .sum_lutc_input = "datac"; // synopsys translate_on @@ -59744,7 +59494,7 @@ defparam \ula_|video_|VGA_VS .is_wysiwyg = "true"; defparam \ula_|video_|VGA_VS .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X47_Y17_N4 +// Location: LCCOMB_X27_Y13_N26 cycloneive_lcell_comb \z80_|memory_ifc_|q1~feeder ( // Equation(s): // \z80_|memory_ifc_|q1~feeder_combout = \z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q @@ -59761,7 +59511,7 @@ defparam \z80_|memory_ifc_|q1~feeder .lut_mask = 16'hFF00; defparam \z80_|memory_ifc_|q1~feeder .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X47_Y17_N5 +// Location: FF_X27_Y13_N27 dffeas \z80_|memory_ifc_|q1 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\z80_|memory_ifc_|q1~feeder_combout ), @@ -59780,7 +59530,7 @@ defparam \z80_|memory_ifc_|q1 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|q1 .power_up = "low"; // synopsys translate_on -// Location: FF_X47_Y17_N25 +// Location: FF_X27_Y13_N17 dffeas \z80_|memory_ifc_|q2 ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(gnd), @@ -59799,7 +59549,7 @@ defparam \z80_|memory_ifc_|q2 .is_wysiwyg = "true"; defparam \z80_|memory_ifc_|q2 .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X47_Y17_N24 +// Location: LCCOMB_X27_Y13_N16 cycloneive_lcell_comb \z80_|memory_ifc_|nRFSH_out~0 ( // Equation(s): // \z80_|memory_ifc_|nRFSH_out~0_combout = (!\z80_|memory_ifc_|q2~q & \z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q ) @@ -59816,41 +59566,41 @@ defparam \z80_|memory_ifc_|nRFSH_out~0 .lut_mask = 16'h0F00; defparam \z80_|memory_ifc_|nRFSH_out~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X47_Y17_N26 +// Location: LCCOMB_X27_Y13_N20 cycloneive_lcell_comb \z80_|memory_ifc_|nM1_out ( // Equation(s): // \z80_|memory_ifc_|nM1_out~combout = (\z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ) - .dataa(gnd), + .dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), .datab(gnd), - .datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ), + .datac(gnd), .datad(\z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q ), .cin(gnd), .combout(\z80_|memory_ifc_|nM1_out~combout ), .cout()); // synopsys translate_off -defparam \z80_|memory_ifc_|nM1_out .lut_mask = 16'hFF0F; +defparam \z80_|memory_ifc_|nM1_out .lut_mask = 16'hFF55; defparam \z80_|memory_ifc_|nM1_out .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X23_Y26_N0 +// Location: LCCOMB_X24_Y10_N28 cycloneive_lcell_comb \ula_|beep~0 ( // Equation(s): -// \ula_|beep~0_combout = \D[4]~98_combout $ (\raw_loader_in~input_o $ (\D[3]~96_combout )) +// \ula_|beep~0_combout = \raw_loader_in~input_o $ (\D[3]~74_combout $ (\D[4]~76_combout )) - .dataa(gnd), - .datab(\D[4]~98_combout ), - .datac(\raw_loader_in~input_o ), - .datad(\D[3]~96_combout ), + .dataa(\raw_loader_in~input_o ), + .datab(\D[3]~74_combout ), + .datac(gnd), + .datad(\D[4]~76_combout ), .cin(gnd), .combout(\ula_|beep~0_combout ), .cout()); // synopsys translate_off -defparam \ula_|beep~0 .lut_mask = 16'hC33C; +defparam \ula_|beep~0 .lut_mask = 16'h9966; defparam \ula_|beep~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X23_Y26_N1 +// Location: FF_X24_Y10_N29 dffeas \ula_|beep ( .clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ), .d(\ula_|beep~0_combout ), diff --git a/simulation/modelsim/spectrum_min_1200mv_0c_v_fast.sdo b/simulation/modelsim/spectrum_min_1200mv_0c_v_fast.sdo index ef4ecfb..488c80a 100644 --- a/simulation/modelsim/spectrum_min_1200mv_0c_v_fast.sdo +++ b/simulation/modelsim/spectrum_min_1200mv_0c_v_fast.sdo @@ -29,7 +29,7 @@ (DELAYFILE (SDFVERSION "2.1") (DESIGN "spectrum") - (DATE "04/01/2022 18:55:52") + (DATE "04/02/2022 15:53:45") (VENDOR "Altera") (PROGRAM "Quartus II 32-bit") (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition") @@ -41,8 +41,8 @@ (INSTANCE GPIO_1\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (1174:1174:1174) (1317:1317:1317)) - (PORT oe (934:934:934) (1057:1057:1057)) + (PORT i (1004:1004:1004) (1151:1151:1151)) + (PORT oe (366:366:366) (427:427:427)) (IOPATH i o (1586:1586:1586) (1541:1541:1541)) (IOPATH oe o (1579:1579:1579) (1514:1514:1514)) ) @@ -53,8 +53,8 @@ (INSTANCE GPIO_1\[1\]\~output) (DELAY (ABSOLUTE - (PORT i (1180:1180:1180) (1340:1340:1340)) - (PORT oe (1037:1037:1037) (1174:1174:1174)) + (PORT i (816:816:816) (930:930:930)) + (PORT oe (1443:1443:1443) (1634:1634:1634)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) (IOPATH oe o (1635:1635:1635) (1561:1561:1561)) ) @@ -65,8 +65,8 @@ (INSTANCE GPIO_1\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (1119:1119:1119) (1291:1291:1291)) - (PORT oe (1037:1037:1037) (1174:1174:1174)) + (PORT i (909:909:909) (1030:1030:1030)) + (PORT oe (1443:1443:1443) (1634:1634:1634)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) (IOPATH oe o (1635:1635:1635) (1561:1561:1561)) ) @@ -77,8 +77,8 @@ (INSTANCE GPIO_1\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (1254:1254:1254) (1427:1427:1427)) - (PORT oe (1198:1198:1198) (1376:1376:1376)) + (PORT i (735:735:735) (839:839:839)) + (PORT oe (1329:1329:1329) (1510:1510:1510)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) (IOPATH oe o (1635:1635:1635) (1561:1561:1561)) ) @@ -89,8 +89,8 @@ (INSTANCE GPIO_1\[4\]\~output) (DELAY (ABSOLUTE - (PORT i (1312:1312:1312) (1495:1495:1495)) - (PORT oe (1198:1198:1198) (1376:1376:1376)) + (PORT i (735:735:735) (831:831:831)) + (PORT oe (1329:1329:1329) (1510:1510:1510)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) (IOPATH oe o (1635:1635:1635) (1561:1561:1561)) ) @@ -101,8 +101,8 @@ (INSTANCE GPIO_1\[5\]\~output) (DELAY (ABSOLUTE - (PORT i (1099:1099:1099) (1242:1242:1242)) - (PORT oe (1064:1064:1064) (1222:1222:1222)) + (PORT i (793:793:793) (904:904:904)) + (PORT oe (1214:1214:1214) (1386:1386:1386)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) (IOPATH oe o (1635:1635:1635) (1561:1561:1561)) ) @@ -113,8 +113,8 @@ (INSTANCE GPIO_1\[6\]\~output) (DELAY (ABSOLUTE - (PORT i (918:918:918) (1050:1050:1050)) - (PORT oe (1064:1064:1064) (1222:1222:1222)) + (PORT i (668:668:668) (763:763:763)) + (PORT oe (1214:1214:1214) (1386:1386:1386)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) (IOPATH oe o (1635:1635:1635) (1561:1561:1561)) ) @@ -125,8 +125,8 @@ (INSTANCE GPIO_1\[7\]\~output) (DELAY (ABSOLUTE - (PORT i (1143:1143:1143) (1334:1334:1334)) - (PORT oe (1064:1064:1064) (1222:1222:1222)) + (PORT i (508:508:508) (595:595:595)) + (PORT oe (1214:1214:1214) (1386:1386:1386)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) (IOPATH oe o (1635:1635:1635) (1561:1561:1561)) ) @@ -137,8 +137,8 @@ (INSTANCE GPIO_1\[8\]\~output) (DELAY (ABSOLUTE - (PORT i (543:543:543) (634:634:634)) - (PORT oe (1215:1215:1215) (1393:1393:1393)) + (PORT i (644:644:644) (741:741:741)) + (PORT oe (1078:1078:1078) (1228:1228:1228)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) (IOPATH oe o (1635:1635:1635) (1561:1561:1561)) ) @@ -149,8 +149,8 @@ (INSTANCE GPIO_1\[9\]\~output) (DELAY (ABSOLUTE - (PORT i (970:970:970) (1109:1109:1109)) - (PORT oe (1215:1215:1215) (1393:1393:1393)) + (PORT i (662:662:662) (754:754:754)) + (PORT oe (1078:1078:1078) (1228:1228:1228)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) (IOPATH oe o (1635:1635:1635) (1561:1561:1561)) ) @@ -161,8 +161,8 @@ (INSTANCE GPIO_1\[10\]\~output) (DELAY (ABSOLUTE - (PORT i (1061:1061:1061) (1219:1219:1219)) - (PORT oe (1375:1375:1375) (1593:1593:1593)) + (PORT i (770:770:770) (886:886:886)) + (PORT oe (1308:1308:1308) (1496:1496:1496)) (IOPATH i o (3177:3177:3177) (2883:2883:2883)) (IOPATH oe o (3164:3164:3164) (2848:2848:2848)) ) @@ -173,8 +173,8 @@ (INSTANCE GPIO_1\[11\]\~output) (DELAY (ABSOLUTE - (PORT i (775:775:775) (876:876:876)) - (PORT oe (1215:1215:1215) (1393:1393:1393)) + (PORT i (513:513:513) (602:602:602)) + (PORT oe (1078:1078:1078) (1228:1228:1228)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) (IOPATH oe o (1635:1635:1635) (1561:1561:1561)) ) @@ -185,8 +185,8 @@ (INSTANCE GPIO_1\[12\]\~output) (DELAY (ABSOLUTE - (PORT i (1194:1194:1194) (1336:1336:1336)) - (PORT oe (933:933:933) (1055:1055:1055)) + (PORT i (1099:1099:1099) (1263:1263:1263)) + (PORT oe (1554:1554:1554) (1759:1759:1759)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) (IOPATH oe o (1635:1635:1635) (1561:1561:1561)) ) @@ -197,8 +197,8 @@ (INSTANCE GPIO_1\[13\]\~output) (DELAY (ABSOLUTE - (PORT i (1275:1275:1275) (1459:1459:1459)) - (PORT oe (1375:1375:1375) (1593:1593:1593)) + (PORT i (498:498:498) (586:586:586)) + (PORT oe (1308:1308:1308) (1496:1496:1496)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) (IOPATH oe o (1635:1635:1635) (1561:1561:1561)) ) @@ -209,8 +209,8 @@ (INSTANCE GPIO_1\[14\]\~output) (DELAY (ABSOLUTE - (PORT i (934:934:934) (1057:1057:1057)) - (PORT oe (1212:1212:1212) (1388:1388:1388)) + (PORT i (805:805:805) (932:932:932)) + (PORT oe (1340:1340:1340) (1536:1536:1536)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) (IOPATH oe o (1635:1635:1635) (1561:1561:1561)) ) @@ -221,8 +221,8 @@ (INSTANCE GPIO_1\[15\]\~output) (DELAY (ABSOLUTE - (PORT i (987:987:987) (1146:1146:1146)) - (PORT oe (1050:1050:1050) (1190:1190:1190)) + (PORT i (665:665:665) (779:779:779)) + (PORT oe (1422:1422:1422) (1610:1610:1610)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) (IOPATH oe o (1635:1635:1635) (1561:1561:1561)) ) @@ -233,8 +233,8 @@ (INSTANCE GPIO_1\[16\]\~output) (DELAY (ABSOLUTE - (PORT i (673:673:673) (772:772:772)) - (PORT oe (1396:1396:1396) (1566:1566:1566)) + (PORT i (702:702:702) (804:804:804)) + (PORT oe (1398:1398:1398) (1566:1566:1566)) (IOPATH i o (1666:1666:1666) (1600:1600:1600)) (IOPATH oe o (1659:1659:1659) (1566:1566:1566)) ) @@ -245,8 +245,8 @@ (INSTANCE GPIO_1\[17\]\~output) (DELAY (ABSOLUTE - (PORT i (694:694:694) (791:791:791)) - (PORT oe (1396:1396:1396) (1567:1567:1567)) + (PORT i (641:641:641) (724:724:724)) + (PORT oe (1398:1398:1398) (1566:1566:1566)) (IOPATH i o (1666:1666:1666) (1600:1600:1600)) (IOPATH oe o (1659:1659:1659) (1566:1566:1566)) ) @@ -257,8 +257,8 @@ (INSTANCE GPIO_1\[18\]\~output) (DELAY (ABSOLUTE - (PORT i (620:620:620) (700:700:700)) - (PORT oe (1211:1211:1211) (1355:1355:1355)) + (PORT i (792:792:792) (899:899:899)) + (PORT oe (1213:1213:1213) (1355:1355:1355)) (IOPATH i o (1666:1666:1666) (1600:1600:1600)) (IOPATH oe o (1659:1659:1659) (1566:1566:1566)) ) @@ -269,8 +269,8 @@ (INSTANCE GPIO_1\[19\]\~output) (DELAY (ABSOLUTE - (PORT i (663:663:663) (769:769:769)) - (PORT oe (1396:1396:1396) (1566:1566:1566)) + (PORT i (782:782:782) (877:877:877)) + (PORT oe (1398:1398:1398) (1566:1566:1566)) (IOPATH i o (1666:1666:1666) (1600:1600:1600)) (IOPATH oe o (1659:1659:1659) (1566:1566:1566)) ) @@ -281,8 +281,8 @@ (INSTANCE GPIO_1\[20\]\~output) (DELAY (ABSOLUTE - (PORT i (826:826:826) (944:944:944)) - (PORT oe (1184:1184:1184) (1331:1331:1331)) + (PORT i (675:675:675) (768:768:768)) + (PORT oe (1192:1192:1192) (1328:1328:1328)) (IOPATH i o (1586:1586:1586) (1541:1541:1541)) (IOPATH oe o (1579:1579:1579) (1514:1514:1514)) ) @@ -293,8 +293,8 @@ (INSTANCE GPIO_1\[21\]\~output) (DELAY (ABSOLUTE - (PORT i (736:736:736) (825:825:825)) - (PORT oe (1210:1210:1210) (1354:1354:1354)) + (PORT i (795:795:795) (896:896:896)) + (PORT oe (1212:1212:1212) (1354:1354:1354)) (IOPATH i o (1666:1666:1666) (1600:1600:1600)) (IOPATH oe o (1659:1659:1659) (1566:1566:1566)) ) @@ -305,8 +305,8 @@ (INSTANCE GPIO_1\[22\]\~output) (DELAY (ABSOLUTE - (PORT i (678:678:678) (773:773:773)) - (PORT oe (1148:1148:1148) (1280:1280:1280)) + (PORT i (801:801:801) (913:913:913)) + (PORT oe (1150:1150:1150) (1279:1279:1279)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) (IOPATH oe o (1635:1635:1635) (1561:1561:1561)) ) @@ -317,8 +317,8 @@ (INSTANCE GPIO_1\[23\]\~output) (DELAY (ABSOLUTE - (PORT i (622:622:622) (691:691:691)) - (PORT oe (1364:1364:1364) (1526:1526:1526)) + (PORT i (735:735:735) (848:848:848)) + (PORT oe (1369:1369:1369) (1537:1537:1537)) (IOPATH i o (1666:1666:1666) (1600:1600:1600)) (IOPATH oe o (1659:1659:1659) (1566:1566:1566)) ) @@ -329,8 +329,8 @@ (INSTANCE GPIO_1\[27\]\~output) (DELAY (ABSOLUTE - (PORT i (846:846:846) (761:761:761)) - (PORT oe (926:926:926) (1046:1046:1046)) + (PORT i (1332:1332:1332) (1203:1203:1203)) + (PORT oe (739:739:739) (863:863:863)) (IOPATH i o (1541:1541:1541) (1586:1586:1586)) (IOPATH oe o (1579:1579:1579) (1514:1514:1514)) ) @@ -341,8 +341,8 @@ (INSTANCE GPIO_1\[28\]\~output) (DELAY (ABSOLUTE - (PORT i (1098:1098:1098) (954:954:954)) - (PORT oe (1050:1050:1050) (1190:1190:1190)) + (PORT i (927:927:927) (830:830:830)) + (PORT oe (1422:1422:1422) (1610:1610:1610)) (IOPATH i o (1588:1588:1588) (1643:1643:1643)) (IOPATH oe o (1635:1635:1635) (1561:1561:1561)) ) @@ -353,8 +353,8 @@ (INSTANCE GPIO_1\[29\]\~output) (DELAY (ABSOLUTE - (PORT i (934:934:934) (837:837:837)) - (PORT oe (757:757:757) (859:859:859)) + (PORT i (994:994:994) (906:906:906)) + (PORT oe (556:556:556) (656:656:656)) (IOPATH i o (1600:1600:1600) (1666:1666:1666)) (IOPATH oe o (1659:1659:1659) (1566:1566:1566)) ) @@ -365,8 +365,8 @@ (INSTANCE GPIO_1\[30\]\~output) (DELAY (ABSOLUTE - (PORT i (571:571:571) (628:628:628)) - (PORT oe (731:731:731) (836:836:836)) + (PORT i (959:959:959) (1069:1069:1069)) + (PORT oe (380:380:380) (445:445:445)) (IOPATH i o (1666:1666:1666) (1600:1600:1600)) (IOPATH oe o (1659:1659:1659) (1566:1566:1566)) ) @@ -377,7 +377,7 @@ (INSTANCE LED\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (1022:1022:1022) (889:889:889)) + (PORT i (1031:1031:1031) (895:895:895)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) ) ) @@ -397,7 +397,7 @@ (INSTANCE LED\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (741:741:741) (831:831:831)) + (PORT i (802:802:802) (907:907:907)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) ) ) @@ -452,7 +452,7 @@ (INSTANCE VGA_R\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (638:638:638) (733:733:733)) + (PORT i (752:752:752) (862:862:862)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) ) ) @@ -462,7 +462,7 @@ (INSTANCE VGA_R\[1\]\~output) (DELAY (ABSOLUTE - (PORT i (601:601:601) (687:687:687)) + (PORT i (646:646:646) (736:736:736)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) ) ) @@ -472,7 +472,7 @@ (INSTANCE VGA_R\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (397:397:397) (437:437:437)) + (PORT i (268:268:268) (296:296:296)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) ) ) @@ -482,7 +482,7 @@ (INSTANCE VGA_R\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (527:527:527) (586:586:586)) + (PORT i (558:558:558) (626:626:626)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) ) ) @@ -492,7 +492,7 @@ (INSTANCE VGA_G\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (524:524:524) (579:579:579)) + (PORT i (423:423:423) (471:471:471)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) ) ) @@ -502,7 +502,7 @@ (INSTANCE VGA_G\[1\]\~output) (DELAY (ABSOLUTE - (PORT i (382:382:382) (418:418:418)) + (PORT i (418:418:418) (461:461:461)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) ) ) @@ -512,7 +512,7 @@ (INSTANCE VGA_G\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (444:444:444) (480:480:480)) + (PORT i (552:552:552) (615:615:615)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) ) ) @@ -522,7 +522,7 @@ (INSTANCE VGA_G\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (444:444:444) (480:480:480)) + (PORT i (538:538:538) (601:601:601)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) ) ) @@ -532,7 +532,7 @@ (INSTANCE VGA_B\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (384:384:384) (417:417:417)) + (PORT i (412:412:412) (450:450:450)) (IOPATH i o (3177:3177:3177) (2883:2883:2883)) ) ) @@ -542,7 +542,7 @@ (INSTANCE VGA_B\[1\]\~output) (DELAY (ABSOLUTE - (PORT i (373:373:373) (405:405:405)) + (PORT i (393:393:393) (432:432:432)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) ) ) @@ -552,7 +552,7 @@ (INSTANCE VGA_B\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (511:511:511) (561:561:561)) + (PORT i (534:534:534) (584:584:584)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) ) ) @@ -562,7 +562,7 @@ (INSTANCE VGA_B\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (738:738:738) (808:808:808)) + (PORT i (594:594:594) (667:667:667)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) ) ) @@ -590,7 +590,7 @@ (INSTANCE GPIO_1\[25\]\~output) (DELAY (ABSOLUTE - (PORT i (1282:1282:1282) (1120:1120:1120)) + (PORT i (1387:1387:1387) (1242:1242:1242)) (IOPATH i o (1588:1588:1588) (1643:1643:1643)) ) ) @@ -600,7 +600,7 @@ (INSTANCE GPIO_1\[26\]\~output) (DELAY (ABSOLUTE - (PORT i (792:792:792) (715:715:715)) + (PORT i (1068:1068:1068) (963:963:963)) (IOPATH i o (2841:2841:2841) (3106:3106:3106)) ) ) @@ -610,7 +610,7 @@ (INSTANCE GPIO_1\[31\]\~output) (DELAY (ABSOLUTE - (PORT i (506:506:506) (553:553:553)) + (PORT i (783:783:783) (861:861:861)) (IOPATH i o (1666:1666:1666) (1600:1600:1600)) ) ) @@ -620,7 +620,7 @@ (INSTANCE buzzer_out\~output) (DELAY (ABSOLUTE - (PORT i (749:749:749) (860:860:860)) + (PORT i (1273:1273:1273) (1464:1464:1464)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) ) ) @@ -707,8 +707,8 @@ (INSTANCE ula_\|clocks_\|clk_cpu\~0) (DELAY (ABSOLUTE - (PORT datab (131:131:131) (179:179:179)) - (PORT datad (340:340:340) (316:316:316)) + (PORT datab (130:130:130) (178:178:178)) + (PORT datad (341:341:341) (316:316:316)) (IOPATH datab combout (188:188:188) (193:193:193)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -734,35 +734,33 @@ (INSTANCE ula_\|clocks_\|clk_cpu\~clkctrl) (DELAY (ABSOLUTE - (PORT inclk[0] (388:388:388) (421:421:421)) + (PORT inclk[0] (391:391:391) (423:423:423)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|DFFE_M1_ff\~0) + (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_15) (DELAY (ABSOLUTE - (PORT dataa (610:610:610) (714:714:714)) - (PORT datad (612:612:612) (707:707:707)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|ena_M) - (DELAY - (ABSOLUTE - (PORT datac (596:596:596) (692:692:692)) - (PORT datad (608:608:608) (702:702:702)) + (PORT datab (648:648:648) (768:768:768)) + (PORT datac (328:328:328) (396:396:396)) + (PORT datad (511:511:511) (623:623:623)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_12\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (333:333:333) (370:370:370)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_io_ibuf") (INSTANCE KEY\[1\]\~input) @@ -777,9 +775,9 @@ (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_9) (DELAY (ABSOLUTE - (PORT dataa (203:203:203) (280:280:280)) - (PORT datad (1132:1132:1132) (1310:1310:1310)) - (IOPATH dataa combout (166:166:166) (163:163:163)) + (PORT datac (211:211:211) (270:270:270)) + (PORT datad (1395:1395:1395) (1639:1639:1639)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -789,9 +787,9 @@ (INSTANCE z80_\|interrupts_\|nmi_armed) (DELAY (ABSOLUTE - (PORT clk (830:830:830) (891:891:891)) + (PORT clk (986:986:986) (1060:1060:1060)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (694:694:694) (742:742:742)) + (PORT clrn (391:391:391) (409:409:409)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -805,47 +803,52 @@ (INSTANCE z80_\|interrupts_\|in_nmi_ALTERA_SYNTHESIZED\~feeder) (DELAY (ABSOLUTE - (PORT datad (425:425:425) (491:491:491)) + (PORT datad (185:185:185) (230:230:230)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_eval_cond\~0) + (INSTANCE z80_\|sequencer_\|DFFE_M2_ff\~0) (DELAY (ABSOLUTE - (PORT datac (133:133:133) (175:175:175)) - (PORT datad (136:136:136) (177:177:177)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1371:1371:1371) (1593:1593:1593)) - (PORT datab (1375:1375:1375) (1595:1595:1595)) - (PORT datad (904:904:904) (1067:1067:1067)) + (PORT dataa (226:226:226) (287:287:287)) + (PORT datab (650:650:650) (771:771:771)) + (PORT datad (512:512:512) (623:623:623)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_M2_ff) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (903:903:903) (890:890:890)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|sequencer_\|DFFE_M3_ff\~0) (DELAY (ABSOLUTE - (PORT dataa (606:606:606) (709:709:709)) - (PORT datab (214:214:214) (274:274:274)) - (PORT datad (615:615:615) (711:711:711)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) + (PORT dataa (145:145:145) (196:196:196)) + (PORT datab (655:655:655) (776:776:776)) + (PORT datad (513:513:513) (625:625:625)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -856,9 +859,9 @@ (INSTANCE z80_\|sequencer_\|DFFE_M3_ff) (DELAY (ABSOLUTE - (PORT clk (920:920:920) (927:927:927)) + (PORT clk (902:902:902) (907:907:907)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (927:927:927) (908:908:908)) + (PORT clrn (903:903:903) (890:890:890)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -867,30 +870,16 @@ (HOLD d (posedge clk) (84:84:84)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~1) - (DELAY - (ABSOLUTE - (PORT dataa (743:743:743) (846:846:846)) - (PORT datab (854:854:854) (1004:1004:1004)) - (PORT datac (752:752:752) (882:882:882)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|sequencer_\|DFFE_M4_ff\~0) (DELAY (ABSOLUTE - (PORT dataa (619:619:619) (724:724:724)) - (PORT datab (218:218:218) (276:276:276)) - (PORT datad (605:605:605) (699:699:699)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) + (PORT dataa (158:158:158) (215:215:215)) + (PORT datab (654:654:654) (775:775:775)) + (PORT datad (513:513:513) (625:625:625)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -901,9 +890,9 @@ (INSTANCE z80_\|sequencer_\|DFFE_M4_ff) (DELAY (ABSOLUTE - (PORT clk (920:920:920) (927:927:927)) + (PORT clk (902:902:902) (907:907:907)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (927:927:927) (908:908:908)) + (PORT clrn (903:903:903) (890:890:890)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -914,12 +903,55 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal32\~0) + (INSTANCE z80_\|sequencer_\|M5\~0) (DELAY (ABSOLUTE - (PORT datab (206:206:206) (265:265:265)) - (PORT datad (363:363:363) (441:441:441)) + (PORT dataa (143:143:143) (194:194:194)) + (PORT datab (657:657:657) (778:778:778)) + (PORT datad (513:513:513) (625:625:625)) + (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|M5) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (903:903:903) (890:890:890)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~5) + (DELAY + (ABSOLUTE + (PORT datab (678:678:678) (834:834:834)) + (PORT datac (519:519:519) (614:614:614)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~22) + (DELAY + (ABSOLUTE + (PORT dataa (688:688:688) (804:804:804)) + (PORT datad (957:957:957) (1117:1117:1117)) + (IOPATH dataa combout (166:166:166) (163:163:163)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -929,268 +961,8 @@ (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_11) (DELAY (ABSOLUTE - (PORT datab (1456:1456:1456) (1687:1687:1687)) - (PORT datad (880:880:880) (1039:1039:1039)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|table_xx\~0) - (DELAY - (ABSOLUTE - (PORT dataa (781:781:781) (936:936:936)) - (PORT datad (666:666:666) (794:794:794)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal1\~7) - (DELAY - (ABSOLUTE - (PORT dataa (929:929:929) (1066:1066:1066)) - (PORT datab (519:519:519) (601:601:601)) - (PORT datac (1240:1240:1240) (1447:1447:1447)) - (PORT datad (652:652:652) (756:756:756)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal2\~0) - (DELAY - (ABSOLUTE - (PORT datac (811:811:811) (946:946:946)) - (PORT datad (1277:1277:1277) (1473:1473:1473)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal36\~0) - (DELAY - (ABSOLUTE - (PORT dataa (704:704:704) (826:826:826)) - (PORT datab (932:932:932) (1116:1116:1116)) - (PORT datac (516:516:516) (599:599:599)) - (PORT datad (519:519:519) (609:609:609)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_tbl_cb_set) - (DELAY - (ABSOLUTE - (PORT dataa (975:975:975) (1124:1124:1124)) - (PORT datab (801:801:801) (910:910:910)) - (PORT datac (461:461:461) (539:539:539)) - (PORT datad (425:425:425) (474:474:474)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_tbl_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (676:676:676) (795:795:795)) - (PORT datab (1485:1485:1485) (1716:1716:1716)) - (PORT datac (459:459:459) (536:536:536)) - (PORT datad (543:543:543) (638:638:638)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|DFFE_instCB) - (DELAY - (ABSOLUTE - (PORT clk (914:914:914) (920:920:920)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (920:920:920) (902:902:902)) - (PORT ena (407:407:407) (424:424:424)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal52\~0) - (DELAY - (ABSOLUTE - (PORT dataa (392:392:392) (481:481:481)) - (PORT datab (680:680:680) (814:814:814)) - (PORT datac (543:543:543) (642:642:642)) - (PORT datad (760:760:760) (909:909:909)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal2\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1347:1347:1347) (1572:1572:1572)) - (PORT datab (931:931:931) (1114:1114:1114)) - (PORT datac (515:515:515) (597:597:597)) - (PORT datad (376:376:376) (440:440:440)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_tbl_ed_set) - (DELAY - (ABSOLUTE - (PORT dataa (987:987:987) (1141:1141:1141)) - (PORT datab (447:447:447) (515:515:515)) - (PORT datac (784:784:784) (887:887:887)) - (PORT datad (1145:1145:1145) (1327:1327:1327)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|DFFE_instED) - (DELAY - (ABSOLUTE - (PORT clk (914:914:914) (920:920:920)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (920:920:920) (902:902:902)) - (PORT ena (407:407:407) (424:424:424)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal13\~0) - (DELAY - (ABSOLUTE - (PORT dataa (395:395:395) (485:485:485)) - (PORT datac (535:535:535) (633:633:633)) - (PORT datad (756:756:756) (905:905:905)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal33\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1256:1256:1256) (1471:1471:1471)) - (PORT datac (811:811:811) (946:946:946)) - (PORT datad (1277:1277:1277) (1474:1474:1474)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_im_we) - (DELAY - (ABSOLUTE - (PORT dataa (316:316:316) (366:366:366)) - (PORT datab (591:591:591) (702:702:702)) - (PORT datac (752:752:752) (890:890:890)) - (PORT datad (510:510:510) (595:595:595)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal49\~0) - (DELAY - (ABSOLUTE - (PORT datab (553:553:553) (662:662:662)) - (PORT datac (372:372:372) (439:439:439)) - (PORT datad (715:715:715) (832:832:832)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal33\~1) - (DELAY - (ABSOLUTE - (PORT dataa (793:793:793) (929:929:929)) - (PORT datab (843:843:843) (988:988:988)) - (PORT datac (813:813:813) (946:946:946)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal6\~0) - (DELAY - (ABSOLUTE - (PORT dataa (392:392:392) (481:481:481)) - (PORT datab (680:680:680) (814:814:814)) - (PORT datac (544:544:544) (643:643:643)) - (PORT datad (760:760:760) (910:910:910)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (PORT datac (917:917:917) (1063:1063:1063)) + (PORT datad (1195:1195:1195) (1382:1382:1382)) (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -1198,232 +970,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~14) + (INSTANCE z80_\|execute_\|ctl_ir_we\~4) (DELAY (ABSOLUTE - (PORT dataa (670:670:670) (794:794:794)) - (PORT datab (731:731:731) (859:859:859)) - (PORT datad (401:401:401) (483:483:483)) + (PORT dataa (682:682:682) (820:820:820)) + (PORT datad (619:619:619) (723:723:723)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (158:158:158)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal12\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1529:1529:1529) (1775:1775:1775)) - (PORT datab (476:476:476) (565:565:565)) - (PORT datac (615:615:615) (717:717:717)) - (PORT datad (630:630:630) (728:728:728)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~8) - (DELAY - (ABSOLUTE - (PORT dataa (522:522:522) (627:627:627)) - (PORT datab (882:882:882) (1046:1046:1046)) - (PORT datac (771:771:771) (895:895:895)) - (PORT datad (107:107:107) (132:132:132)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|nM1_int\~2) - (DELAY - (ABSOLUTE - (PORT dataa (616:616:616) (758:758:758)) - (PORT datad (1171:1171:1171) (1359:1359:1359)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~5) - (DELAY - (ABSOLUTE - (PORT dataa (613:613:613) (731:731:731)) - (PORT datab (606:606:606) (688:688:688)) - (PORT datac (170:170:170) (203:203:203)) - (PORT datad (387:387:387) (458:458:458)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal3\~0) - (DELAY - (ABSOLUTE - (PORT datac (814:814:814) (955:955:955)) - (PORT datad (835:835:835) (972:972:972)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~4) - (DELAY - (ABSOLUTE - (PORT dataa (700:700:700) (821:821:821)) - (PORT datab (929:929:929) (1113:1113:1113)) - (PORT datac (957:957:957) (1095:1095:1095)) - (PORT datad (521:521:521) (611:611:611)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~7) - (DELAY - (ABSOLUTE - (PORT datac (1149:1149:1149) (1365:1365:1365)) - (PORT datad (685:685:685) (796:796:796)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1088:1088:1088) (1274:1274:1274)) - (PORT datac (1441:1441:1441) (1671:1671:1671)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~4) - (DELAY - (ABSOLUTE - (PORT dataa (488:488:488) (571:571:571)) - (PORT datab (589:589:589) (696:696:696)) - (PORT datac (481:481:481) (579:579:579)) - (PORT datad (501:501:501) (587:587:587)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal40\~1) - (DELAY - (ABSOLUTE - (PORT dataa (490:490:490) (571:571:571)) - (PORT datab (485:485:485) (562:562:562)) - (PORT datac (500:500:500) (609:609:609)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal39\~0) - (DELAY - (ABSOLUTE - (PORT dataa (490:490:490) (571:571:571)) - (PORT datab (485:485:485) (562:562:562)) - (PORT datac (499:499:499) (609:609:609)) - (PORT datad (652:652:652) (747:747:747)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~1) - (DELAY - (ABSOLUTE - (PORT dataa (472:472:472) (546:546:546)) - (PORT datac (544:544:544) (643:643:643)) - (PORT datad (626:626:626) (718:718:718)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal13\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1255:1255:1255) (1470:1470:1470)) - (PORT datac (811:811:811) (947:947:947)) - (PORT datad (1276:1276:1276) (1472:1472:1472)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal13\~2) - (DELAY - (ABSOLUTE - (PORT dataa (482:482:482) (579:579:579)) - (PORT datab (961:961:961) (1119:1119:1119)) - (PORT datac (623:623:623) (709:709:709)) - (PORT datad (350:350:350) (413:413:413)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal3\~2) - (DELAY - (ABSOLUTE - (PORT dataa (508:508:508) (595:595:595)) - (PORT datab (1337:1337:1337) (1560:1560:1560)) - (PORT datac (959:959:959) (1097:1097:1097)) - (PORT datad (370:370:370) (434:434:434)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -1433,10 +985,10 @@ (INSTANCE z80_\|execute_\|ctl_state_iy_set\~2) (DELAY (ABSOLUTE - (PORT dataa (681:681:681) (814:814:814)) - (PORT datab (1179:1179:1179) (1400:1400:1400)) - (PORT datac (470:470:470) (534:534:534)) - (PORT datad (824:824:824) (972:972:972)) + (PORT dataa (948:948:948) (1097:1097:1097)) + (PORT datab (1220:1220:1220) (1414:1414:1414)) + (PORT datac (382:382:382) (470:470:470)) + (PORT datad (205:205:205) (239:239:239)) (IOPATH dataa combout (166:166:166) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -1446,112 +998,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~8) + (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_16) (DELAY (ABSOLUTE - (PORT datab (780:780:780) (902:902:902)) - (PORT datac (872:872:872) (1009:1009:1009)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~6) - (DELAY - (ABSOLUTE - (PORT datac (897:897:897) (1030:1030:1030)) - (PORT datad (1066:1066:1066) (1247:1247:1247)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~9) - (DELAY - (ABSOLUTE - (PORT datac (572:572:572) (683:683:683)) - (PORT datad (542:542:542) (632:632:632)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~12) - (DELAY - (ABSOLUTE - (PORT dataa (559:559:559) (651:651:651)) - (PORT datab (547:547:547) (647:647:647)) - (PORT datac (486:486:486) (568:568:568)) - (PORT datad (1183:1183:1183) (1350:1350:1350)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~10) - (DELAY - (ABSOLUTE - (PORT dataa (214:214:214) (265:265:265)) - (PORT datab (642:642:642) (740:740:740)) - (PORT datac (352:352:352) (411:411:411)) - (PORT datad (619:619:619) (708:708:708)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal44\~0) - (DELAY - (ABSOLUTE - (PORT dataa (395:395:395) (484:484:484)) - (PORT datab (686:686:686) (821:821:821)) - (PORT datac (535:535:535) (634:634:634)) - (PORT datad (756:756:756) (905:905:905)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~16) - (DELAY - (ABSOLUTE - (PORT dataa (556:556:556) (660:660:660)) - (PORT datab (737:737:737) (838:838:838)) - (PORT datac (528:528:528) (622:622:622)) - (PORT datad (598:598:598) (682:682:682)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~13) - (DELAY - (ABSOLUTE - (PORT datab (461:461:461) (539:539:539)) - (PORT datac (346:346:346) (409:409:409)) - (PORT datad (114:114:114) (136:136:136)) + (PORT datab (651:651:651) (772:772:772)) + (PORT datac (129:129:129) (171:171:171)) + (PORT datad (512:512:512) (624:624:624)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -1559,13 +1011,33 @@ ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal50\~0) + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_T5_ff) (DELAY (ABSOLUTE - (PORT datab (554:554:554) (662:662:662)) - (PORT datac (372:372:372) (439:439:439)) - (PORT datad (648:648:648) (765:765:765)) + (PORT clk (902:902:902) (907:907:907)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (903:903:903) (890:890:890)) + (PORT ena (769:769:769) (833:833:833)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_ixiy_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (458:458:458) (535:535:535)) + (PORT datab (1222:1222:1222) (1416:1416:1416)) + (PORT datac (927:927:927) (1075:1075:1075)) + (PORT datad (527:527:527) (640:640:640)) + (IOPATH dataa combout (165:165:165) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -1573,57 +1045,43 @@ ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal33\~2) + (CELLTYPE "dffeas") + (INSTANCE z80_\|decode_state_\|DFFE_instIY1) (DELAY (ABSOLUTE - (PORT dataa (670:670:670) (794:794:794)) - (PORT datab (731:731:731) (860:860:860)) - (PORT datad (402:402:402) (483:483:483)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) + (PORT clk (909:909:909) (917:917:917)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (904:904:904) (891:891:891)) + (PORT ena (422:422:422) (450:450:450)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|use_ixiy) + (DELAY + (ABSOLUTE + (PORT datab (270:270:270) (337:337:337)) + (PORT datad (239:239:239) (297:297:297)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~17) + (INSTANCE z80_\|execute_\|ixy_d\~4) (DELAY (ABSOLUTE - (PORT dataa (546:546:546) (648:648:648)) - (PORT datab (601:601:601) (680:680:680)) - (PORT datac (526:526:526) (619:619:619)) - (PORT datad (581:581:581) (663:663:663)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~5) - (DELAY - (ABSOLUTE - (PORT datac (894:894:894) (1057:1057:1057)) - (PORT datad (540:540:540) (631:631:631)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~14) - (DELAY - (ABSOLUTE - (PORT dataa (345:345:345) (409:409:409)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (105:105:105) (129:129:129)) - (PORT datad (589:589:589) (682:682:682)) - (IOPATH dataa combout (170:170:170) (163:163:163)) + (PORT datab (548:548:548) (654:654:654)) + (PORT datac (859:859:859) (1029:1029:1029)) + (PORT datad (513:513:513) (604:604:604)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -1635,359 +1093,11 @@ (INSTANCE z80_\|execute_\|ixy_d\~11) (DELAY (ABSOLUTE - (PORT dataa (887:887:887) (1033:1033:1033)) - (PORT datab (781:781:781) (903:903:903)) - (PORT datac (191:191:191) (228:228:228)) - (PORT datad (1020:1020:1020) (1182:1182:1182)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~15) - (DELAY - (ABSOLUTE - (PORT dataa (595:595:595) (674:674:674)) - (PORT datab (124:124:124) (156:156:156)) - (PORT datac (89:89:89) (111:111:111)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_ixiy_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (706:706:706) (832:832:832)) - (PORT datab (845:845:845) (1000:1000:1000)) - (PORT datac (837:837:837) (976:976:976)) - (PORT datad (1172:1172:1172) (1384:1384:1384)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|DFFE_instIY1) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (916:916:916)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (922:922:922) (904:904:904)) - (PORT ena (422:422:422) (450:450:450)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (473:473:473) (571:571:571)) - (PORT datac (350:350:350) (421:421:421)) - (PORT datad (781:781:781) (925:925:925)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~14) - (DELAY - (ABSOLUTE - (PORT dataa (701:701:701) (832:832:832)) - (PORT datab (253:253:253) (308:308:308)) - (PORT datac (938:938:938) (1081:1081:1081)) - (PORT datad (145:145:145) (182:182:182)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~2) - (DELAY - (ABSOLUTE - (PORT dataa (393:393:393) (481:481:481)) - (PORT datab (559:559:559) (663:663:663)) - (PORT datac (375:375:375) (457:457:457)) - (PORT datad (759:759:759) (909:909:909)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~16) - (DELAY - (ABSOLUTE - (PORT dataa (925:925:925) (1090:1090:1090)) - (PORT datab (862:862:862) (993:993:993)) - (PORT datac (979:979:979) (1128:1128:1128)) - (PORT datad (857:857:857) (1004:1004:1004)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~18) - (DELAY - (ABSOLUTE - (PORT dataa (729:729:729) (859:859:859)) - (PORT datab (696:696:696) (819:819:819)) - (PORT datac (580:580:580) (688:688:688)) - (PORT datad (936:936:936) (1067:1067:1067)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~26) - (DELAY - (ABSOLUTE - (PORT datac (375:375:375) (436:436:436)) - (PORT datad (979:979:979) (1143:1143:1143)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~27) - (DELAY - (ABSOLUTE - (PORT dataa (333:333:333) (387:387:387)) - (PORT datac (606:606:606) (703:703:703)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~7) - (DELAY - (ABSOLUTE - (PORT dataa (109:109:109) (141:141:141)) - (PORT datab (132:132:132) (167:167:167)) - (PORT datac (358:358:358) (422:422:422)) - (PORT datad (1181:1181:1181) (1348:1348:1348)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~5) - (DELAY - (ABSOLUTE - (PORT dataa (560:560:560) (651:651:651)) - (PORT datab (682:682:682) (795:795:795)) - (PORT datac (379:379:379) (441:441:441)) - (PORT datad (93:93:93) (112:112:112)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~18) - (DELAY - (ABSOLUTE - (PORT dataa (520:520:520) (625:625:625)) - (PORT datab (880:880:880) (1044:1044:1044)) - (PORT datac (766:766:766) (890:890:890)) - (PORT datad (106:106:106) (130:130:130)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal55\~0) - (DELAY - (ABSOLUTE - (PORT dataa (159:159:159) (217:217:217)) - (PORT datac (500:500:500) (585:585:585)) - (PORT datad (507:507:507) (594:594:594)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|comb\~1) - (DELAY - (ABSOLUTE - (PORT dataa (985:985:985) (1160:1160:1160)) - (PORT datac (638:638:638) (752:752:752)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~15) - (DELAY - (ABSOLUTE - (PORT dataa (334:334:334) (388:388:388)) - (PORT datab (637:637:637) (747:747:747)) - (PORT datac (521:521:521) (627:627:627)) - (PORT datad (95:95:95) (115:115:115)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~17) - (DELAY - (ABSOLUTE - (PORT dataa (344:344:344) (414:414:414)) - (PORT datab (347:347:347) (398:398:398)) - (PORT datac (523:523:523) (630:630:630)) - (PORT datad (494:494:494) (570:570:570)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~5) - (DELAY - (ABSOLUTE - (PORT dataa (499:499:499) (584:584:584)) - (PORT datab (638:638:638) (743:743:743)) - (PORT datac (1023:1023:1023) (1194:1194:1194)) - (PORT datad (484:484:484) (556:556:556)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~9) - (DELAY - (ABSOLUTE - (PORT dataa (945:945:945) (1085:1085:1085)) - (PORT datac (898:898:898) (1044:1044:1044)) - (PORT datad (656:656:656) (761:761:761)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal9\~0) - (DELAY - (ABSOLUTE - (PORT datac (448:448:448) (528:528:528)) - (PORT datad (490:490:490) (584:584:584)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~10) - (DELAY - (ABSOLUTE - (PORT dataa (945:945:945) (1085:1085:1085)) - (PORT datab (915:915:915) (1066:1066:1066)) - (PORT datac (835:835:835) (984:984:984)) - (PORT datad (668:668:668) (776:776:776)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~8) - (DELAY - (ABSOLUTE - (PORT dataa (835:835:835) (968:968:968)) - (PORT datab (691:691:691) (816:816:816)) - (PORT datac (804:804:804) (935:935:935)) - (PORT datad (446:446:446) (503:503:503)) + (PORT dataa (843:843:843) (989:989:989)) + (PORT datab (1541:1541:1541) (1792:1792:1792)) + (PORT datac (739:739:739) (870:870:870)) + (PORT datad (469:469:469) (535:535:535)) (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~20) - (DELAY - (ABSOLUTE - (PORT dataa (477:477:477) (551:551:551)) - (PORT datab (694:694:694) (803:803:803)) - (PORT datac (752:752:752) (855:855:855)) - (PORT datad (715:715:715) (832:832:832)) - (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -1996,12 +1106,76 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal12\~1) + (INSTANCE z80_\|execute_\|ixy_d\~9) (DELAY (ABSOLUTE - (PORT dataa (330:330:330) (384:384:384)) - (PORT datab (534:534:534) (640:640:640)) - (PORT datad (627:627:627) (727:727:727)) + (PORT dataa (947:947:947) (1101:1101:1101)) + (PORT datac (1379:1379:1379) (1620:1620:1620)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~7) + (DELAY + (ABSOLUTE + (PORT datac (1014:1014:1014) (1180:1180:1180)) + (PORT datad (547:547:547) (680:680:680)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~6) + (DELAY + (ABSOLUTE + (PORT dataa (335:335:335) (413:413:413)) + (PORT datac (374:374:374) (461:461:461)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~8) + (DELAY + (ABSOLUTE + (PORT datab (145:145:145) (195:195:195)) + (PORT datad (142:142:142) (187:187:187)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1129:1129:1129) (1292:1292:1292)) + (PORT datab (529:529:529) (619:619:619)) + (PORT datac (956:956:956) (1109:1109:1109)) + (PORT datad (749:749:749) (873:873:873)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal33\~0) + (DELAY + (ABSOLUTE + (PORT dataa (927:927:927) (1079:1079:1079)) + (PORT datab (148:148:148) (198:198:198)) + (PORT datad (199:199:199) (250:250:250)) (IOPATH dataa combout (166:166:166) (159:159:159)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -2010,13 +1184,69 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal9\~1) + (INSTANCE z80_\|pla_decode_\|Equal33\~1) (DELAY (ABSOLUTE - (PORT dataa (863:863:863) (1011:1011:1011)) - (PORT datab (539:539:539) (636:636:636)) - (PORT datac (912:912:912) (1095:1095:1095)) - (PORT datad (688:688:688) (798:798:798)) + (PORT dataa (1163:1163:1163) (1379:1379:1379)) + (PORT datab (664:664:664) (800:800:800)) + (PORT datad (694:694:694) (829:829:829)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal33\~2) + (DELAY + (ABSOLUTE + (PORT dataa (672:672:672) (795:795:795)) + (PORT datab (549:549:549) (648:648:648)) + (PORT datad (900:900:900) (1019:1019:1019)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal21\~0) + (DELAY + (ABSOLUTE + (PORT datab (788:788:788) (935:935:935)) + (PORT datad (792:792:792) (932:932:932)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal77\~0) + (DELAY + (ABSOLUTE + (PORT dataa (572:572:572) (687:687:687)) + (PORT datab (557:557:557) (664:664:664)) + (PORT datac (529:529:529) (638:638:638)) + (PORT datad (537:537:537) (643:643:643)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal77\~1) + (DELAY + (ABSOLUTE + (PORT dataa (375:375:375) (442:442:442)) + (PORT datab (351:351:351) (429:429:429)) + (PORT datac (943:943:943) (1090:1090:1090)) + (PORT datad (314:314:314) (359:359:359)) (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -2026,57 +1256,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal25\~0) + (INSTANCE z80_\|pla_decode_\|Equal1\~7) (DELAY (ABSOLUTE - (PORT dataa (828:828:828) (976:976:976)) - (PORT datab (865:865:865) (1032:1032:1032)) - (PORT datac (748:748:748) (868:868:868)) - (PORT datad (877:877:877) (994:994:994)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~21) - (DELAY - (ABSOLUTE - (PORT dataa (474:474:474) (548:548:548)) - (PORT datab (1013:1013:1013) (1170:1170:1170)) - (PORT datac (462:462:462) (531:531:531)) - (PORT datad (841:841:841) (969:969:969)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~6) - (DELAY - (ABSOLUTE - (PORT dataa (666:666:666) (782:782:782)) - (PORT datac (526:526:526) (615:615:615)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal19\~0) - (DELAY - (ABSOLUTE - (PORT dataa (503:503:503) (588:588:588)) - (PORT datab (532:532:532) (619:619:619)) - (PORT datac (912:912:912) (1095:1095:1095)) - (PORT datad (688:688:688) (798:798:798)) + (PORT dataa (651:651:651) (762:762:762)) + (PORT datab (324:324:324) (394:394:394)) + (PORT datac (291:291:291) (334:334:334)) + (PORT datad (314:314:314) (379:379:379)) (IOPATH dataa combout (158:158:158) (163:163:163)) (IOPATH datab combout (160:160:160) (167:167:167)) (IOPATH datac combout (119:119:119) (125:125:125)) @@ -2086,27 +1272,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal1\~4) + (INSTANCE z80_\|pla_decode_\|Equal79\~0) (DELAY (ABSOLUTE - (PORT datac (963:963:963) (1115:1115:1115)) - (PORT datad (1142:1142:1142) (1323:1323:1323)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal29\~0) - (DELAY - (ABSOLUTE - (PORT dataa (115:115:115) (145:145:145)) - (PORT datab (632:632:632) (729:729:729)) - (PORT datac (877:877:877) (995:995:995)) - (PORT datad (817:817:817) (953:953:953)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT dataa (427:427:427) (528:528:528)) + (PORT datab (1100:1100:1100) (1290:1290:1290)) + (PORT datac (726:726:726) (849:849:849)) + (PORT datad (882:882:882) (1030:1030:1030)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -2114,63 +1288,83 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal24\~1) + (INSTANCE z80_\|interrupts_\|iff1\~0) (DELAY (ABSOLUTE - (PORT dataa (861:861:861) (1009:1009:1009)) - (PORT datab (537:537:537) (633:633:633)) - (PORT datac (915:915:915) (1098:1098:1098)) - (PORT datad (693:693:693) (804:804:804)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (PORT dataa (116:116:116) (152:152:152)) + (PORT datab (766:766:766) (890:890:890)) + (PORT datac (203:203:203) (258:258:258)) + (PORT datad (676:676:676) (803:803:803)) + (IOPATH dataa combout (158:158:158) (173:173:173)) + (IOPATH datab combout (160:160:160) (176:176:176)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal34\~0) + (INSTANCE z80_\|interrupts_\|DFFE_instIFF2\~0) (DELAY (ABSOLUTE - (PORT dataa (1256:1256:1256) (1471:1471:1471)) - (PORT datab (521:521:521) (603:603:603)) - (PORT datac (102:102:102) (123:123:123)) - (PORT datad (232:232:232) (271:271:271)) + (PORT dataa (112:112:112) (148:148:148)) + (PORT datab (766:766:766) (890:890:890)) + (PORT datad (679:679:679) (807:807:807)) + (IOPATH dataa combout (158:158:158) (173:173:173)) + (IOPATH datab combout (160:160:160) (176:176:176)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_12) + (DELAY + (ABSOLUTE + (PORT dataa (1553:1553:1553) (1812:1812:1812)) + (PORT datab (382:382:382) (464:464:464)) + (PORT datad (482:482:482) (570:570:570)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal37\~0) + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_12\~clkctrl) (DELAY (ABSOLUTE - (PORT dataa (243:243:243) (292:292:292)) - (PORT datab (518:518:518) (600:600:600)) - (PORT datac (1240:1240:1240) (1447:1447:1447)) - (PORT datad (622:622:622) (714:714:714)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) + (PORT inclk[0] (608:608:608) (667:667:667)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal35\~0) + (CELLTYPE "dffeas") + (INSTANCE z80_\|interrupts_\|DFFE_instIFF2) (DELAY (ABSOLUTE - (PORT dataa (244:244:244) (294:294:294)) - (PORT datab (520:520:520) (602:602:602)) - (PORT datac (1240:1240:1240) (1447:1447:1447)) - (PORT datad (102:102:102) (120:120:120)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (PORT clk (920:920:920) (928:928:928)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (895:895:895) (899:899:899)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal13\~0) + (DELAY + (ABSOLUTE + (PORT dataa (156:156:156) (212:212:212)) + (PORT datac (211:211:211) (271:271:271)) + (PORT datad (203:203:203) (256:256:256)) + (IOPATH dataa combout (165:165:165) (163:163:163)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -2181,433 +1375,10 @@ (INSTANCE z80_\|pla_decode_\|Equal38\~2) (DELAY (ABSOLUTE - (PORT dataa (924:924:924) (1089:1089:1089)) - (PORT datab (876:876:876) (1032:1032:1032)) - (PORT datac (978:978:978) (1128:1128:1128)) - (PORT datad (815:815:815) (930:930:930)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~2) - (DELAY - (ABSOLUTE - (PORT dataa (607:607:607) (708:708:708)) - (PORT datab (616:616:616) (736:736:736)) - (PORT datac (315:315:315) (370:370:370)) - (PORT datad (487:487:487) (571:571:571)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~3) - (DELAY - (ABSOLUTE - (PORT dataa (468:468:468) (551:551:551)) - (PORT datab (784:784:784) (923:923:923)) - (PORT datac (325:325:325) (381:381:381)) - (PORT datad (316:316:316) (360:360:360)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|comb\~0) - (DELAY - (ABSOLUTE - (PORT datab (1101:1101:1101) (1266:1266:1266)) - (PORT datac (656:656:656) (766:766:766)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal47\~0) - (DELAY - (ABSOLUTE - (PORT dataa (248:248:248) (299:299:299)) - (PORT datab (524:524:524) (606:606:606)) - (PORT datac (1238:1238:1238) (1444:1444:1444)) - (PORT datad (188:188:188) (219:219:219)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~4) - (DELAY - (ABSOLUTE - (PORT dataa (724:724:724) (850:850:850)) - (PORT datab (657:657:657) (761:761:761)) - (PORT datac (90:90:90) (111:111:111)) - (PORT datad (717:717:717) (845:845:845)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~22) - (DELAY - (ABSOLUTE - (PORT dataa (366:366:366) (430:430:430)) - (PORT datab (336:336:336) (396:396:396)) - (PORT datac (95:95:95) (119:119:119)) - (PORT datad (638:638:638) (735:735:735)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~24) - (DELAY - (ABSOLUTE - (PORT dataa (496:496:496) (581:581:581)) - (PORT datab (122:122:122) (157:157:157)) - (PORT datac (335:335:335) (390:390:390)) - (PORT datad (361:361:361) (420:420:420)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla42M3T3_6) - (DELAY - (ABSOLUTE - (PORT dataa (800:800:800) (920:920:920)) - (PORT datab (687:687:687) (811:811:811)) - (PORT datac (373:373:373) (443:443:443)) - (PORT datad (633:633:633) (722:722:722)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~6) - (DELAY - (ABSOLUTE - (PORT dataa (372:372:372) (454:454:454)) - (PORT datab (621:621:621) (717:717:717)) - (PORT datac (1030:1030:1030) (1202:1202:1202)) - (PORT datad (307:307:307) (363:363:363)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal6\~1) - (DELAY - (ABSOLUTE - (PORT dataa (824:824:824) (963:963:963)) - (PORT datab (633:633:633) (730:730:730)) - (PORT datac (670:670:670) (792:792:792)) - (PORT datad (359:359:359) (425:425:425)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~16) - (DELAY - (ABSOLUTE - (PORT dataa (831:831:831) (971:971:971)) - (PORT datab (377:377:377) (452:452:452)) - (PORT datac (666:666:666) (788:788:788)) - (PORT datad (778:778:778) (892:892:892)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|M5\~0) - (DELAY - (ABSOLUTE - (PORT dataa (612:612:612) (716:716:716)) - (PORT datab (144:144:144) (193:193:193)) - (PORT datad (611:611:611) (705:705:705)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|M5) - (DELAY - (ABSOLUTE - (PORT clk (920:920:920) (927:927:927)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (927:927:927) (908:908:908)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~2) - (DELAY - (ABSOLUTE - (PORT datab (908:908:908) (1071:1071:1071)) - (PORT datac (1462:1462:1462) (1689:1689:1689)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~29) - (DELAY - (ABSOLUTE - (PORT dataa (333:333:333) (389:389:389)) - (PORT datab (516:516:516) (605:605:605)) - (PORT datac (563:563:563) (665:665:665)) - (PORT datad (364:364:364) (430:430:430)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~25) - (DELAY - (ABSOLUTE - (PORT dataa (1104:1104:1104) (1300:1300:1300)) - (PORT datab (377:377:377) (453:453:453)) - (PORT datac (376:376:376) (440:440:440)) - (PORT datad (309:309:309) (358:358:358)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1059:1059:1059) (1216:1216:1216)) - (PORT datab (516:516:516) (618:618:618)) - (PORT datac (102:102:102) (124:124:124)) - (PORT datad (97:97:97) (118:118:118)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~7) - (DELAY - (ABSOLUTE - (PORT dataa (702:702:702) (833:833:833)) - (PORT datab (252:252:252) (307:307:307)) - (PORT datac (936:936:936) (1080:1080:1080)) - (PORT datad (146:146:146) (182:182:182)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal52\~1) - (DELAY - (ABSOLUTE - (PORT dataa (780:780:780) (935:935:935)) - (PORT datab (522:522:522) (616:616:616)) - (PORT datac (526:526:526) (613:613:613)) - (PORT datad (668:668:668) (796:796:796)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~14) - (DELAY - (ABSOLUTE - (PORT dataa (552:552:552) (655:655:655)) - (PORT datab (738:738:738) (839:839:839)) - (PORT datac (527:527:527) (621:621:621)) - (PORT datad (596:596:596) (679:679:679)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~8) - (DELAY - (ABSOLUTE - (PORT dataa (333:333:333) (396:396:396)) - (PORT datab (703:703:703) (820:820:820)) - (PORT datac (306:306:306) (350:350:350)) - (PORT datad (911:911:911) (1051:1051:1051)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal24\~0) - (DELAY - (ABSOLUTE - (PORT dataa (393:393:393) (481:481:481)) - (PORT datab (114:114:114) (143:143:143)) - (PORT datac (142:142:142) (190:190:190)) - (PORT datad (494:494:494) (571:571:571)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_pc\~0) - (DELAY - (ABSOLUTE - (PORT dataa (488:488:488) (582:582:582)) - (PORT datab (619:619:619) (740:740:740)) - (PORT datac (607:607:607) (691:691:691)) - (PORT datad (370:370:370) (429:429:429)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_pc\~1) - (DELAY - (ABSOLUTE - (PORT dataa (240:240:240) (291:291:291)) - (PORT datab (1132:1132:1132) (1336:1336:1336)) - (PORT datac (579:579:579) (676:676:676)) - (PORT datad (891:891:891) (1034:1034:1034)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_pc\~2) - (DELAY - (ABSOLUTE - (PORT dataa (505:505:505) (599:599:599)) - (PORT datab (102:102:102) (131:131:131)) - (PORT datac (90:90:90) (112:112:112)) - (PORT datad (487:487:487) (571:571:571)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~17) - (DELAY - (ABSOLUTE - (PORT dataa (334:334:334) (396:396:396)) - (PORT datab (661:661:661) (762:762:762)) - (PORT datac (109:109:109) (134:134:134)) - (PORT datad (338:338:338) (397:397:397)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~6) - (DELAY - (ABSOLUTE - (PORT dataa (212:212:212) (261:261:261)) - (PORT datab (647:647:647) (745:745:745)) - (PORT datac (350:350:350) (409:409:409)) - (PORT datad (620:620:620) (709:709:709)) + (PORT dataa (876:876:876) (1039:1039:1039)) + (PORT datab (813:813:813) (946:946:946)) + (PORT datac (779:779:779) (952:952:952)) + (PORT datad (850:850:850) (993:993:993)) (IOPATH dataa combout (158:158:158) (163:163:163)) (IOPATH datab combout (160:160:160) (167:167:167)) (IOPATH datac combout (119:119:119) (125:125:125)) @@ -2617,5898 +1388,42 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal11\~0) - (DELAY - (ABSOLUTE - (PORT dataa (924:924:924) (1088:1088:1088)) - (PORT datab (861:861:861) (993:993:993)) - (PORT datac (978:978:978) (1128:1128:1128)) - (PORT datad (855:855:855) (1002:1002:1002)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal10\~0) - (DELAY - (ABSOLUTE - (PORT dataa (925:925:925) (1090:1090:1090)) - (PORT datab (862:862:862) (994:994:994)) - (PORT datac (979:979:979) (1129:1129:1129)) - (PORT datad (858:858:858) (1005:1005:1005)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~9) - (DELAY - (ABSOLUTE - (PORT dataa (949:949:949) (1095:1095:1095)) - (PORT datab (826:826:826) (967:967:967)) - (PORT datac (1442:1442:1442) (1672:1672:1672)) - (PORT datad (1066:1066:1066) (1247:1247:1247)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~4) - (DELAY - (ABSOLUTE - (PORT dataa (335:335:335) (397:397:397)) - (PORT datab (702:702:702) (819:819:819)) - (PORT datac (608:608:608) (702:702:702)) - (PORT datad (290:290:290) (330:330:330)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~15) - (DELAY - (ABSOLUTE - (PORT dataa (701:701:701) (833:833:833)) - (PORT datab (252:252:252) (307:307:307)) - (PORT datac (937:937:937) (1081:1081:1081)) - (PORT datad (146:146:146) (182:182:182)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~16) - (DELAY - (ABSOLUTE - (PORT dataa (612:612:612) (729:729:729)) - (PORT datab (639:639:639) (740:740:740)) - (PORT datac (294:294:294) (332:332:332)) - (PORT datad (319:319:319) (370:370:370)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~9) - (DELAY - (ABSOLUTE - (PORT dataa (158:158:158) (205:205:205)) - (PORT datab (253:253:253) (308:308:308)) - (PORT datac (101:101:101) (121:121:121)) - (PORT datad (782:782:782) (926:926:926)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal46\~0) - (DELAY - (ABSOLUTE - (PORT dataa (156:156:156) (213:213:213)) - (PORT datab (517:517:517) (613:613:613)) - (PORT datac (501:501:501) (586:586:586)) - (PORT datad (662:662:662) (789:789:789)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~10) - (DELAY - (ABSOLUTE - (PORT dataa (697:697:697) (829:829:829)) - (PORT datab (475:475:475) (551:551:551)) - (PORT datac (942:942:942) (1086:1086:1086)) - (PORT datad (144:144:144) (178:178:178)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1196:1196:1196) (1388:1388:1388)) - (PORT datab (1137:1137:1137) (1323:1323:1323)) - (PORT datac (552:552:552) (649:649:649)) - (PORT datad (663:663:663) (762:762:762)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~6) - (DELAY - (ABSOLUTE - (PORT dataa (770:770:770) (890:890:890)) - (PORT datab (613:613:613) (728:728:728)) - (PORT datac (402:402:402) (458:458:458)) - (PORT datad (679:679:679) (797:797:797)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (547:547:547) (645:645:645)) - (PORT datac (625:625:625) (720:720:720)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (162:162:162) (210:210:210)) - (PORT datab (252:252:252) (307:307:307)) - (PORT datac (666:666:666) (779:779:779)) - (PORT datad (777:777:777) (921:921:921)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~16) - (DELAY - (ABSOLUTE - (PORT dataa (659:659:659) (794:794:794)) - (PORT datab (1230:1230:1230) (1413:1413:1413)) - (PORT datac (749:749:749) (886:886:886)) - (PORT datad (534:534:534) (628:628:628)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1009:1009:1009) (1176:1176:1176)) - (PORT datab (728:728:728) (854:854:854)) - (PORT datac (751:751:751) (855:855:855)) - (PORT datad (477:477:477) (546:546:546)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~8) - (DELAY - (ABSOLUTE - (PORT dataa (322:322:322) (374:374:374)) - (PORT datac (295:295:295) (337:337:337)) - (PORT datad (703:703:703) (813:813:813)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~18) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (135:135:135)) - (PORT datab (114:114:114) (142:142:142)) - (PORT datac (90:90:90) (112:112:112)) - (PORT datad (104:104:104) (121:121:121)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~19) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (136:136:136)) - (PORT datab (108:108:108) (139:139:139)) - (PORT datac (455:455:455) (527:527:527)) - (PORT datad (472:472:472) (544:544:544)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~16) - (DELAY - (ABSOLUTE - (PORT datac (1152:1152:1152) (1344:1344:1344)) - (PORT datad (536:536:536) (632:632:632)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~36) - (DELAY - (ABSOLUTE - (PORT dataa (922:922:922) (1087:1087:1087)) - (PORT datab (861:861:861) (992:992:992)) - (PORT datac (978:978:978) (1128:1128:1128)) - (PORT datad (854:854:854) (1001:1001:1001)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~9) - (DELAY - (ABSOLUTE - (PORT dataa (375:375:375) (446:446:446)) - (PORT datab (844:844:844) (979:979:979)) - (PORT datac (635:635:635) (741:741:741)) - (PORT datad (782:782:782) (889:889:889)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~44) - (DELAY - (ABSOLUTE - (PORT dataa (1213:1213:1213) (1420:1420:1420)) - (PORT datab (379:379:379) (463:463:463)) - (PORT datac (930:930:930) (1068:1068:1068)) - (PORT datad (110:110:110) (130:130:130)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~11) - (DELAY - (ABSOLUTE - (PORT dataa (705:705:705) (831:831:831)) - (PORT datad (1162:1162:1162) (1373:1373:1373)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~6) - (DELAY - (ABSOLUTE - (PORT dataa (504:504:504) (599:599:599)) - (PORT datab (241:241:241) (281:281:281)) - (PORT datac (213:213:213) (262:262:262)) - (PORT datad (880:880:880) (1017:1017:1017)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~7) - (DELAY - (ABSOLUTE - (PORT dataa (340:340:340) (393:393:393)) - (PORT datab (640:640:640) (745:745:745)) - (PORT datac (805:805:805) (935:935:935)) - (PORT datad (173:173:173) (205:205:205)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~7) - (DELAY - (ABSOLUTE - (PORT datac (845:845:845) (986:986:986)) - (PORT datad (630:630:630) (726:726:726)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~11) - (DELAY - (ABSOLUTE - (PORT dataa (703:703:703) (836:836:836)) - (PORT datab (473:473:473) (549:549:549)) - (PORT datac (934:934:934) (1077:1077:1077)) - (PORT datad (148:148:148) (184:184:184)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~12) - (DELAY - (ABSOLUTE - (PORT dataa (702:702:702) (834:834:834)) - (PORT datab (252:252:252) (307:307:307)) - (PORT datac (936:936:936) (1079:1079:1079)) - (PORT datad (147:147:147) (183:183:183)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~0) - (DELAY - (ABSOLUTE - (PORT dataa (793:793:793) (907:907:907)) - (PORT datab (596:596:596) (688:688:688)) - (PORT datac (582:582:582) (663:663:663)) - (PORT datad (527:527:527) (618:618:618)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla27npla34M1T1_3) - (DELAY - (ABSOLUTE - (PORT dataa (376:376:376) (447:447:447)) - (PORT datab (650:650:650) (762:762:762)) - (PORT datac (811:811:811) (941:941:941)) - (PORT datad (831:831:831) (957:957:957)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~8) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (241:241:241)) - (PORT datab (105:105:105) (134:134:134)) - (PORT datac (344:344:344) (400:400:400)) - (PORT datad (99:99:99) (120:120:120)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~9) - (DELAY - (ABSOLUTE - (PORT dataa (298:298:298) (349:349:349)) - (PORT datab (466:466:466) (534:534:534)) - (PORT datac (467:467:467) (542:542:542)) - (PORT datad (428:428:428) (494:494:494)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~6) - (DELAY - (ABSOLUTE - (PORT dataa (629:629:629) (721:721:721)) - (PORT datab (101:101:101) (130:130:130)) - (PORT datac (101:101:101) (128:128:128)) - (PORT datad (93:93:93) (111:111:111)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~7) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (276:276:276)) - (PORT datab (685:685:685) (797:797:797)) - (PORT datac (360:360:360) (430:430:430)) - (PORT datad (725:725:725) (861:861:861)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~8) - (DELAY - (ABSOLUTE - (PORT datab (1663:1663:1663) (1925:1925:1925)) - (PORT datac (1123:1123:1123) (1307:1307:1307)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla21M2T2_3) - (DELAY - (ABSOLUTE - (PORT dataa (1045:1045:1045) (1187:1187:1187)) - (PORT datab (1192:1192:1192) (1397:1397:1397)) - (PORT datac (618:618:618) (703:703:703)) - (PORT datad (109:109:109) (130:130:130)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_ixy_dT4_2) - (DELAY - (ABSOLUTE - (PORT datac (670:670:670) (795:795:795)) - (PORT datad (335:335:335) (398:398:398)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~39) - (DELAY - (ABSOLUTE - (PORT dataa (657:657:657) (758:758:758)) - (PORT datab (516:516:516) (598:598:598)) - (PORT datac (1136:1136:1136) (1290:1290:1290)) - (PORT datad (826:826:826) (963:963:963)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla26M1T4_3) - (DELAY - (ABSOLUTE - (PORT dataa (583:583:583) (701:701:701)) - (PORT datab (1350:1350:1350) (1567:1567:1567)) - (PORT datad (1175:1175:1175) (1364:1364:1364)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~4) - (DELAY - (ABSOLUTE - (PORT dataa (847:847:847) (974:974:974)) - (PORT datab (563:563:563) (662:662:662)) - (PORT datac (491:491:491) (576:576:576)) - (PORT datad (627:627:627) (719:719:719)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~15) - (DELAY - (ABSOLUTE - (PORT dataa (804:804:804) (914:914:914)) - (PORT datab (633:633:633) (730:730:730)) - (PORT datac (174:174:174) (207:207:207)) - (PORT datad (629:629:629) (717:717:717)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~38) - (DELAY - (ABSOLUTE - (PORT dataa (195:195:195) (235:235:235)) - (PORT datab (588:588:588) (678:678:678)) - (PORT datac (874:874:874) (992:992:992)) - (PORT datad (439:439:439) (505:505:505)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_zero) - (DELAY - (ABSOLUTE - (PORT dataa (632:632:632) (734:734:734)) - (PORT datab (643:643:643) (735:735:735)) - (PORT datac (464:464:464) (527:527:527)) - (PORT datad (440:440:440) (503:503:503)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (650:650:650) (755:755:755)) - (PORT datab (153:153:153) (197:197:197)) - (PORT datac (138:138:138) (178:178:178)) - (PORT datad (136:136:136) (167:167:167)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~14) - (DELAY - (ABSOLUTE - (PORT datac (527:527:527) (616:616:616)) - (PORT datad (1139:1139:1139) (1332:1332:1332)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (472:472:472) (546:546:546)) - (PORT datab (563:563:563) (662:662:662)) - (PORT datac (682:682:682) (798:798:798)) - (PORT datad (626:626:626) (718:718:718)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~1) - (DELAY - (ABSOLUTE - (PORT datab (114:114:114) (142:142:142)) - (PORT datad (102:102:102) (119:119:119)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~5) - (DELAY - (ABSOLUTE - (PORT dataa (655:655:655) (755:755:755)) - (PORT datab (562:562:562) (662:662:662)) - (PORT datac (1135:1135:1135) (1289:1289:1289)) - (PORT datad (827:827:827) (964:964:964)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~30) - (DELAY - (ABSOLUTE - (PORT dataa (741:741:741) (866:866:866)) - (PORT datab (650:650:650) (759:759:759)) - (PORT datac (469:469:469) (538:538:538)) - (PORT datad (755:755:755) (896:896:896)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~29) - (DELAY - (ABSOLUTE - (PORT dataa (516:516:516) (608:608:608)) - (PORT datab (533:533:533) (618:618:618)) - (PORT datac (671:671:671) (792:792:792)) - (PORT datad (361:361:361) (422:422:422)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~31) - (DELAY - (ABSOLUTE - (PORT dataa (768:768:768) (921:921:921)) - (PORT datab (101:101:101) (130:130:130)) - (PORT datac (90:90:90) (111:111:111)) - (PORT datad (201:201:201) (232:232:232)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal69\~0) - (DELAY - (ABSOLUTE - (PORT dataa (480:480:480) (577:577:577)) - (PORT datab (956:956:956) (1113:1113:1113)) - (PORT datac (618:618:618) (701:701:701)) - (PORT datad (356:356:356) (419:419:419)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal1\~5) - (DELAY - (ABSOLUTE - (PORT dataa (660:660:660) (791:791:791)) - (PORT datad (648:648:648) (770:770:770)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~14) - (DELAY - (ABSOLUTE - (PORT dataa (561:561:561) (653:653:653)) - (PORT datab (1135:1135:1135) (1296:1296:1296)) - (PORT datac (623:623:623) (708:708:708)) - (PORT datad (351:351:351) (414:414:414)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~12) - (DELAY - (ABSOLUTE - (PORT dataa (991:991:991) (1166:1166:1166)) - (PORT datab (511:511:511) (594:594:594)) - (PORT datad (117:117:117) (134:134:134)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal56\~0) - (DELAY - (ABSOLUTE - (PORT dataa (345:345:345) (415:415:415)) - (PORT datab (638:638:638) (748:748:748)) - (PORT datac (520:520:520) (626:626:626)) - (PORT datad (500:500:500) (583:583:583)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~11) - (DELAY - (ABSOLUTE - (PORT dataa (837:837:837) (970:970:970)) - (PORT datab (687:687:687) (811:811:811)) - (PORT datac (812:812:812) (944:944:944)) - (PORT datad (441:441:441) (498:498:498)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~2) - (DELAY - (ABSOLUTE - (PORT dataa (447:447:447) (515:515:515)) - (PORT datab (465:465:465) (538:538:538)) - (PORT datad (364:364:364) (427:427:427)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1108:1108:1108) (1300:1300:1300)) - (PORT datab (1182:1182:1182) (1366:1366:1366)) - (PORT datac (284:284:284) (330:330:330)) - (PORT datad (971:971:971) (1107:1107:1107)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~4) - (DELAY - (ABSOLUTE - (PORT dataa (463:463:463) (539:539:539)) - (PORT datab (533:533:533) (615:615:615)) - (PORT datac (93:93:93) (117:117:117)) - (PORT datad (816:816:816) (946:946:946)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~5) - (DELAY - (ABSOLUTE - (PORT datac (627:627:627) (734:734:734)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~3) - (DELAY - (ABSOLUTE - (PORT dataa (673:673:673) (798:798:798)) - (PORT datab (551:551:551) (659:659:659)) - (PORT datac (371:371:371) (438:438:438)) - (PORT datad (713:713:713) (830:830:830)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~15) - (DELAY - (ABSOLUTE - (PORT datab (611:611:611) (734:734:734)) - (PORT datac (830:830:830) (972:972:972)) - (PORT datad (1305:1305:1305) (1526:1526:1526)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~8) - (DELAY - (ABSOLUTE - (PORT dataa (364:364:364) (440:440:440)) - (PORT datab (997:997:997) (1144:1144:1144)) - (PORT datac (553:553:553) (652:652:652)) - (PORT datad (665:665:665) (764:764:764)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~9) - (DELAY - (ABSOLUTE - (PORT dataa (575:575:575) (673:673:673)) - (PORT datab (683:683:683) (789:789:789)) - (PORT datac (613:613:613) (700:700:700)) - (PORT datad (97:97:97) (117:117:117)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~3) - (DELAY - (ABSOLUTE - (PORT dataa (525:525:525) (605:605:605)) - (PORT datab (616:616:616) (732:732:732)) - (PORT datac (561:561:561) (661:661:661)) - (PORT datad (639:639:639) (736:736:736)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~4) - (DELAY - (ABSOLUTE - (PORT dataa (575:575:575) (683:683:683)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (701:701:701) (826:826:826)) - (PORT datad (598:598:598) (707:707:707)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4) - (DELAY - (ABSOLUTE - (PORT datab (842:842:842) (985:985:985)) - (PORT datac (831:831:831) (968:968:968)) - (PORT datad (727:727:727) (823:823:823)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~10) - (DELAY - (ABSOLUTE - (PORT dataa (432:432:432) (499:499:499)) - (PORT datab (457:457:457) (527:527:527)) - (PORT datac (680:680:680) (759:759:759)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~11) - (DELAY - (ABSOLUTE - (PORT dataa (784:784:784) (906:906:906)) - (PORT datab (1159:1159:1159) (1325:1325:1325)) - (PORT datac (457:457:457) (530:530:530)) - (PORT datad (425:425:425) (487:487:487)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal48\~0) - (DELAY - (ABSOLUTE - (PORT dataa (479:479:479) (576:576:576)) - (PORT datab (955:955:955) (1113:1113:1113)) - (PORT datac (618:618:618) (701:701:701)) - (PORT datad (357:357:357) (420:420:420)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf2_we) - (DELAY - (ABSOLUTE - (PORT dataa (517:517:517) (604:604:604)) - (PORT datab (491:491:491) (589:589:589)) - (PORT datac (524:524:524) (617:617:617)) - (PORT datad (714:714:714) (820:820:820)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~41) - (DELAY - (ABSOLUTE - (PORT dataa (701:701:701) (837:837:837)) - (PORT datab (547:547:547) (646:646:646)) - (PORT datac (112:112:112) (138:138:138)) - (PORT datad (688:688:688) (791:791:791)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1010:1010:1010) (1177:1177:1177)) - (PORT datab (733:733:733) (860:860:860)) - (PORT datac (1145:1145:1145) (1334:1334:1334)) - (PORT datad (450:450:450) (514:514:514)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~17) - (DELAY - (ABSOLUTE - (PORT dataa (664:664:664) (771:771:771)) - (PORT datab (562:562:562) (662:662:662)) - (PORT datac (344:344:344) (398:398:398)) - (PORT datad (631:631:631) (724:724:724)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~19) - (DELAY - (ABSOLUTE - (PORT dataa (487:487:487) (573:573:573)) - (PORT datab (600:600:600) (713:713:713)) - (PORT datac (310:310:310) (364:364:364)) - (PORT datad (595:595:595) (683:683:683)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_iorw\~10) - (DELAY - (ABSOLUTE - (PORT dataa (921:921:921) (1086:1086:1086)) - (PORT datab (872:872:872) (1027:1027:1027)) - (PORT datac (978:978:978) (1128:1128:1128)) - (PORT datad (820:820:820) (936:936:936)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~18) - (DELAY - (ABSOLUTE - (PORT dataa (931:931:931) (1064:1064:1064)) - (PORT datab (853:853:853) (1005:1005:1005)) - (PORT datac (524:524:524) (616:616:616)) - (PORT datad (657:657:657) (760:760:760)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~20) - (DELAY - (ABSOLUTE - (PORT dataa (307:307:307) (366:366:366)) - (PORT datab (496:496:496) (581:581:581)) - (PORT datac (528:528:528) (621:621:621)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~13) - (DELAY - (ABSOLUTE - (PORT dataa (919:919:919) (1079:1079:1079)) - (PORT datab (630:630:630) (743:743:743)) - (PORT datac (1001:1001:1001) (1169:1169:1169)) - (PORT datad (529:529:529) (621:621:621)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~9) - (DELAY - (ABSOLUTE - (PORT dataa (680:680:680) (797:797:797)) - (PORT datab (103:103:103) (131:131:131)) - (PORT datac (542:542:542) (622:622:622)) - (PORT datad (515:515:515) (597:597:597)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~3) - (DELAY - (ABSOLUTE - (PORT dataa (754:754:754) (879:879:879)) - (PORT datab (544:544:544) (643:643:643)) - (PORT datac (304:304:304) (357:357:357)) - (PORT datad (349:349:349) (410:410:410)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal20\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1134:1134:1134) (1319:1319:1319)) - (PORT datab (852:852:852) (1008:1008:1008)) - (PORT datac (123:123:123) (151:151:151)) - (PORT datad (617:617:617) (712:712:712)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal68\~2) - (DELAY - (ABSOLUTE - (PORT dataa (921:921:921) (1086:1086:1086)) - (PORT datab (873:873:873) (1028:1028:1028)) - (PORT datac (978:978:978) (1128:1128:1128)) - (PORT datad (819:819:819) (935:935:935)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~14) - (DELAY - (ABSOLUTE - (PORT dataa (516:516:516) (605:605:605)) - (PORT datab (792:792:792) (918:918:918)) - (PORT datac (749:749:749) (887:887:887)) - (PORT datad (855:855:855) (1000:1000:1000)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~13) - (DELAY - (ABSOLUTE - (PORT dataa (368:368:368) (433:433:433)) - (PORT datab (883:883:883) (1009:1009:1009)) - (PORT datac (709:709:709) (807:807:807)) - (PORT datad (820:820:820) (956:956:956)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~15) - (DELAY - (ABSOLUTE - (PORT dataa (870:870:870) (1028:1028:1028)) - (PORT datab (766:766:766) (906:906:906)) - (PORT datac (624:624:624) (718:718:718)) - (PORT datad (436:436:436) (498:498:498)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~11) - (DELAY - (ABSOLUTE - (PORT dataa (373:373:373) (441:441:441)) - (PORT datab (550:550:550) (651:651:651)) - (PORT datac (631:631:631) (756:756:756)) - (PORT datad (90:90:90) (106:106:106)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1268:1268:1268) (1469:1469:1469)) - (PORT datab (459:459:459) (530:530:530)) - (PORT datac (1182:1182:1182) (1375:1375:1375)) - (PORT datad (362:362:362) (424:424:424)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~10) - (DELAY - (ABSOLUTE - (PORT dataa (515:515:515) (602:602:602)) - (PORT datab (548:548:548) (647:647:647)) - (PORT datac (815:815:815) (942:942:942)) - (PORT datad (843:843:843) (988:988:988)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~8) - (DELAY - (ABSOLUTE - (PORT dataa (344:344:344) (407:407:407)) - (PORT datab (232:232:232) (277:277:277)) - (PORT datac (107:107:107) (130:130:130)) - (PORT datad (776:776:776) (892:892:892)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~9) - (DELAY - (ABSOLUTE - (PORT dataa (333:333:333) (390:390:390)) - (PORT datab (544:544:544) (642:642:642)) - (PORT datac (479:479:479) (551:551:551)) - (PORT datad (450:450:450) (513:513:513)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~12) - (DELAY - (ABSOLUTE - (PORT dataa (189:189:189) (225:225:225)) - (PORT datab (169:169:169) (206:206:206)) - (PORT datac (88:88:88) (109:109:109)) - (PORT datad (91:91:91) (108:108:108)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~11) - (DELAY - (ABSOLUTE - (PORT dataa (116:116:116) (147:147:147)) - (PORT datab (119:119:119) (149:149:149)) - (PORT datac (106:106:106) (129:129:129)) - (PORT datad (106:106:106) (124:124:124)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~12) - (DELAY - (ABSOLUTE - (PORT dataa (337:337:337) (395:395:395)) - (PORT datab (810:810:810) (932:932:932)) - (PORT datac (336:336:336) (400:400:400)) - (PORT datad (917:917:917) (1055:1055:1055)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~6) - (DELAY - (ABSOLUTE - (PORT dataa (357:357:357) (427:427:427)) - (PORT datab (549:549:549) (650:650:650)) - (PORT datac (631:631:631) (755:755:755)) - (PORT datad (1285:1285:1285) (1467:1467:1467)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~7) - (DELAY - (ABSOLUTE - (PORT dataa (515:515:515) (604:604:604)) - (PORT datab (103:103:103) (131:131:131)) - (PORT datac (175:175:175) (210:210:210)) - (PORT datad (1286:1286:1286) (1469:1469:1469)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~4) - (DELAY - (ABSOLUTE - (PORT datab (589:589:589) (720:720:720)) - (PORT datac (812:812:812) (935:935:935)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~8) - (DELAY - (ABSOLUTE - (PORT dataa (774:774:774) (900:900:900)) - (PORT datab (535:535:535) (623:623:623)) - (PORT datac (614:614:614) (721:721:721)) - (PORT datad (788:788:788) (903:903:903)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (547:547:547) (635:635:635)) - (PORT datab (798:798:798) (921:921:921)) - (PORT datac (544:544:544) (624:624:624)) - (PORT datad (103:103:103) (121:121:121)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~12) - (DELAY - (ABSOLUTE - (PORT dataa (601:601:601) (687:687:687)) - (PORT datab (653:653:653) (762:762:762)) - (PORT datac (371:371:371) (437:437:437)) - (PORT datad (483:483:483) (565:565:565)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~13) - (DELAY - (ABSOLUTE - (PORT dataa (318:318:318) (371:371:371)) - (PORT datac (294:294:294) (345:345:345)) - (PORT datad (285:285:285) (323:323:323)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~14) - (DELAY - (ABSOLUTE - (PORT dataa (133:133:133) (171:171:171)) - (PORT datab (689:689:689) (799:799:799)) - (PORT datac (642:642:642) (742:742:742)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~15) - (DELAY - (ABSOLUTE - (PORT dataa (487:487:487) (571:571:571)) - (PORT datab (459:459:459) (531:531:531)) - (PORT datac (173:173:173) (208:208:208)) - (PORT datad (103:103:103) (120:120:120)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_66_oe\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1136:1136:1136) (1321:1321:1321)) - (PORT datab (503:503:503) (587:587:587)) - (PORT datac (120:120:120) (149:149:149)) - (PORT datad (788:788:788) (906:906:906)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel_pla11M1T1_11) - (DELAY - (ABSOLUTE - (PORT dataa (1018:1018:1018) (1199:1199:1199)) - (PORT datab (890:890:890) (1045:1045:1045)) - (PORT datad (790:790:790) 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dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero) - (DELAY - (ABSOLUTE - (PORT dataa (635:635:635) (722:722:722)) - (PORT datab (118:118:118) (153:153:153)) - (PORT datac (90:90:90) (112:112:112)) - (PORT datad (459:459:459) (527:527:527)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[2\]) - (DELAY - (ABSOLUTE - (PORT datab (532:532:532) (631:631:631)) - (PORT datac (308:308:308) (355:355:355)) - (PORT datad (372:372:372) (443:443:443)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|ena\~0) - (DELAY - (ABSOLUTE - (PORT datac (509:509:509) (606:606:606)) - (PORT datad (376:376:376) (447:447:447)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_high\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (916:916:916) (901:901:901)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (422:422:422) (450:450:450)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_lq) - (DELAY - (ABSOLUTE - (PORT dataa (560:560:560) (653:653:653)) - (PORT datab (394:394:394) (463:463:463)) - (PORT datac (485:485:485) (568:568:568)) - (PORT datad (984:984:984) (1149:1149:1149)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~10) - (DELAY - (ABSOLUTE - (PORT dataa (849:849:849) (998:998:998)) - (PORT datab (833:833:833) (979:979:979)) - (PORT datac (1038:1038:1038) (1201:1201:1201)) - (PORT datad (215:215:215) (255:255:255)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~11) - (DELAY - (ABSOLUTE - (PORT dataa (665:665:665) (781:781:781)) - (PORT datac (522:522:522) (609:609:609)) - (PORT datad (685:685:685) (795:795:795)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~21) - (DELAY - (ABSOLUTE - (PORT dataa (687:687:687) (790:790:790)) - (PORT datab (795:795:795) (904:904:904)) - (PORT datac (597:597:597) (680:680:680)) - (PORT datad (723:723:723) (824:824:824)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~22) - (DELAY - (ABSOLUTE - (PORT datab (511:511:511) (594:594:594)) - (PORT datac (279:279:279) (321:321:321)) - (PORT datad (89:89:89) (106:106:106)) - (IOPATH datab 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(IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~4) - (DELAY - (ABSOLUTE - (PORT dataa (111:111:111) (145:145:145)) - (PORT datab (128:128:128) (160:160:160)) - (PORT datac (456:456:456) (522:522:522)) - (PORT datad (291:291:291) (331:331:331)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~5) - (DELAY - (ABSOLUTE - (PORT datac (1434:1434:1434) (1701:1701:1701)) - (PORT datad (1109:1109:1109) (1285:1285:1285)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~18) - (DELAY - (ABSOLUTE - (PORT dataa (823:823:823) (951:951:951)) - (PORT datab (458:458:458) (530:530:530)) - (PORT datac (530:530:530) (608:608:608)) - (PORT datad (362:362:362) (424:424:424)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~19) - (DELAY - (ABSOLUTE - (PORT dataa (790:790:790) (902:902:902)) - (PORT datab (730:730:730) (837:837:837)) - (PORT datac (453:453:453) (531:531:531)) - (PORT datad (428:428:428) (489:489:489)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~33) - (DELAY - (ABSOLUTE - (PORT dataa (599:599:599) (690:690:690)) - (PORT datab (1442:1442:1442) (1669:1669:1669)) - (PORT datac (871:871:871) (1031:1031:1031)) - (PORT datad (948:948:948) (1102:1102:1102)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~20) - (DELAY - (ABSOLUTE - (PORT datac (112:112:112) (138:138:138)) - (PORT datad (112:112:112) (132:132:132)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~23) - (DELAY - (ABSOLUTE - (PORT dataa (681:681:681) (799:799:799)) - (PORT datab (727:727:727) (862:862:862)) - (PORT datac (985:985:985) (1124:1124:1124)) - (PORT datad (446:446:446) (511:511:511)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~24) - (DELAY - (ABSOLUTE - (PORT dataa (204:204:204) (242:242:242)) - (PORT datab (204:204:204) (243:243:243)) - (PORT datac (189:189:189) (225:225:225)) - (PORT datad (110:110:110) (134:134:134)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~25) - (DELAY - (ABSOLUTE - (PORT dataa (848:848:848) (975:975:975)) - (PORT datab (729:729:729) (862:862:862)) - (PORT datac (491:491:491) (575:575:575)) - (PORT datad (630:630:630) (722:722:722)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~34) - (DELAY - (ABSOLUTE - (PORT dataa (385:385:385) (454:454:454)) - (PORT datab (1530:1530:1530) (1769:1769:1769)) - (PORT datac (725:725:725) (854:854:854)) - (PORT datad (307:307:307) (354:354:354)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low) - (DELAY - (ABSOLUTE - (PORT dataa (480:480:480) (556:556:556)) - (PORT datab (117:117:117) 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(1023:1023:1023) (1165:1165:1165)) - (PORT datac (627:627:627) (722:722:722)) - (PORT datad (986:986:986) (1115:1115:1115)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~39) - (DELAY - (ABSOLUTE - (PORT dataa (1049:1049:1049) (1198:1198:1198)) - (PORT datab (102:102:102) (129:129:129)) - (PORT datac (657:657:657) (749:749:749)) - (PORT datad (325:325:325) (380:380:380)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~46) - (DELAY - (ABSOLUTE - (PORT dataa (338:338:338) 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(794:794:794) (911:911:911)) - (PORT datab (797:797:797) (920:920:920)) - (PORT datac (330:330:330) (380:380:380)) - (PORT datad (512:512:512) (593:593:593)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~45) - (DELAY - (ABSOLUTE - (PORT dataa (919:919:919) (1079:1079:1079)) - (PORT datab (104:104:104) (133:133:133)) - (PORT datac (1001:1001:1001) (1169:1169:1169)) - (PORT datad (519:519:519) (601:601:601)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~22) - (DELAY - (ABSOLUTE - (PORT dataa (794:794:794) (911:911:911)) - (PORT datab (797:797:797) (921:921:921)) - (PORT datac (617:617:617) (724:724:724)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~23) - (DELAY - (ABSOLUTE - (PORT dataa (1016:1016:1016) (1164:1164:1164)) - (PORT datab (173:173:173) (209:209:209)) - (PORT datac (614:614:614) (721:721:721)) - (PORT datad (657:657:657) (768:768:768)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~24) - (DELAY - (ABSOLUTE - (PORT dataa (792:792:792) (905:905:905)) - (PORT datab (796:796:796) (920:920:920)) - (PORT datac (90:90:90) (112:112:112)) - (PORT datad (526:526:526) (617:617:617)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~25) - (DELAY - (ABSOLUTE - (PORT dataa (105:105:105) (137:137:137)) - (PORT datab (547:547:547) (644:644:644)) - (PORT datac (585:585:585) (667:667:667)) - (PORT datad (656:656:656) (767:767:767)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (188:188:188) (177:177:177)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1100:1100:1100) (1268:1268:1268)) - (PORT datab (1019:1019:1019) (1160:1160:1160)) - (PORT datac (624:624:624) (719:719:719)) - (PORT datad (1134:1134:1134) (1315:1315:1315)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~26) - (DELAY - (ABSOLUTE - (PORT dataa (192:192:192) (232:232:232)) - (PORT datab (1020:1020:1020) (1161:1161:1161)) - (PORT datac (877:877:877) (996:996:996)) - (PORT datad (98:98:98) (121:121:121)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~27) - (DELAY - (ABSOLUTE - (PORT dataa (350:350:350) (409:409:409)) - (PORT datab (570:570:570) (660:660:660)) - (PORT datac (708:708:708) (805:805:805)) - (PORT datad (439:439:439) (498:498:498)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~28) - (DELAY - (ABSOLUTE - (PORT dataa (337:337:337) (405:405:405)) - (PORT datac (580:580:580) (650:650:650)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~10) - (DELAY - (ABSOLUTE - (PORT dataa (547:547:547) (636:636:636)) - (PORT datab (795:795:795) (919:919:919)) - (PORT datac (546:546:546) (626:626:626)) - (PORT datad (661:661:661) (773:773:773)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~11) - (DELAY - (ABSOLUTE - (PORT dataa (197:197:197) (236:236:236)) - (PORT datab (111:111:111) (144:144:144)) - (PORT datac (182:182:182) (221:221:221)) - (PORT datad (178:178:178) (207:207:207)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~32) - (DELAY - (ABSOLUTE - (PORT datab (349:349:349) (409:409:409)) - (PORT datac (485:485:485) (563:563:563)) - (PORT datad (95:95:95) (114:114:114)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~33) - (DELAY - (ABSOLUTE - (PORT dataa (304:304:304) (355:355:355)) - (PORT datab (483:483:483) (559:559:559)) - (PORT datac (102:102:102) (123:123:123)) - (PORT datad (89:89:89) (106:106:106)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~0) - (DELAY - (ABSOLUTE - (PORT dataa (444:444:444) (511:511:511)) - (PORT datab (376:376:376) (447:447:447)) - (PORT datac (530:530:530) (609:609:609)) - (PORT datad (443:443:443) (505:505:505)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~1) - (DELAY - (ABSOLUTE - (PORT datab (460:460:460) (537:537:537)) - (PORT datad (436:436:436) (495:495:495)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~12) - (DELAY - (ABSOLUTE - (PORT datab (113:113:113) (146:146:146)) - (PORT datac (182:182:182) (221:221:221)) - (PORT datad (179:179:179) (208:208:208)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~47) - (DELAY - (ABSOLUTE - (PORT dataa (919:919:919) (1079:1079:1079)) - (PORT datab (1019:1019:1019) (1194:1194:1194)) - (PORT datac (1001:1001:1001) (1169:1169:1169)) - (PORT datad (533:533:533) (609:609:609)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~34) - (DELAY - (ABSOLUTE - (PORT dataa (794:794:794) (911:911:911)) - (PORT datab (796:796:796) (919:919:919)) - (PORT datac (545:545:545) (626:626:626)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~35) - (DELAY - (ABSOLUTE - (PORT dataa (1017:1017:1017) (1164:1164:1164)) - (PORT datab (560:560:560) (645:645:645)) - (PORT datac (161:161:161) (190:190:190)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~36) - (DELAY - (ABSOLUTE - (PORT dataa (360:360:360) (420:420:420)) - (PORT datab (325:325:325) (375:375:375)) - (PORT datac (441:441:441) (508:508:508)) - (PORT datad (171:171:171) (202:202:202)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~43) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (135:135:135)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datac (89:89:89) (110:110:110)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_lo\~9) - (DELAY - (ABSOLUTE - (PORT dataa (720:720:720) (841:841:841)) - (PORT datab (551:551:551) (651:651:651)) - (PORT datac (608:608:608) (730:730:730)) - (PORT datad (550:550:550) (651:651:651)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (794:794:794) (913:913:913)) - (PORT datab (733:733:733) (835:835:835)) - (PORT datac (878:878:878) (998:998:998)) - (PORT datad (718:718:718) (838:838:838)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla57M1T4_4) - (DELAY - (ABSOLUTE - (PORT dataa (661:661:661) (760:760:760)) - (PORT datab (583:583:583) (702:702:702)) - (PORT datad (763:763:763) (910:910:910)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_oe\~1) - (DELAY - (ABSOLUTE - (PORT dataa (374:374:374) (448:448:448)) - (PORT datab (535:535:535) (630:630:630)) - (PORT datac (291:291:291) (336:336:336)) - (PORT datad (119:119:119) (137:137:137)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (410:410:410) (491:491:491)) - (PORT datab (531:531:531) (621:621:621)) - (PORT datac (591:591:591) (686:686:686)) - (PORT datad (497:497:497) (597:597:597)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~9) - (DELAY - (ABSOLUTE - (PORT dataa (689:689:689) (810:810:810)) - (PORT datab (119:119:119) (153:153:153)) - (PORT datac (1335:1335:1335) (1559:1559:1559)) - (PORT datad (88:88:88) (106:106:106)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal8\~0) - (DELAY - (ABSOLUTE - (PORT datab (1162:1162:1162) (1349:1349:1349)) - (PORT datac (963:963:963) (1116:1116:1116)) - (PORT datad (644:644:644) (755:755:755)) - (IOPATH datab combout (166:166:166) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~9) - (DELAY - (ABSOLUTE - (PORT dataa (803:803:803) (934:934:934)) - (PORT datab (791:791:791) (908:908:908)) - (PORT datac (457:457:457) (519:519:519)) - (PORT datad (205:205:205) (245:245:245)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~4) - (DELAY - (ABSOLUTE - (PORT dataa (472:472:472) (546:546:546)) - (PORT datab (639:639:639) (740:740:740)) - (PORT datac (544:544:544) (643:643:643)) - (PORT datad (551:551:551) (647:647:647)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1150:1150:1150) (1360:1360:1360)) - (PORT datab (237:237:237) (277:277:277)) - (PORT datac (560:560:560) (651:651:651)) - (PORT datad (490:490:490) (579:579:579)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal11\~1) - (DELAY - (ABSOLUTE - (PORT datac (908:908:908) (1064:1064:1064)) - (PORT datad (858:858:858) (1006:1006:1006)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla12M3T1_2) - (DELAY - (ABSOLUTE - (PORT dataa (543:543:543) (631:631:631)) - (PORT datab (650:650:650) (745:745:745)) - (PORT datac (1107:1107:1107) (1270:1270:1270)) - (PORT datad (361:361:361) (419:419:419)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~10) - (DELAY - (ABSOLUTE - (PORT dataa (102:102:102) (133:133:133)) - (PORT datab (331:331:331) (396:396:396)) - (PORT datac (990:990:990) (1152:1152:1152)) - (PORT datad (339:339:339) (397:397:397)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~11) - (DELAY - (ABSOLUTE - (PORT dataa (848:848:848) (992:992:992)) - (PORT datab (187:187:187) (227:227:227)) - (PORT datac (1177:1177:1177) (1366:1366:1366)) - (PORT datad (306:306:306) (360:360:360)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla77M1T1_3) - (DELAY - (ABSOLUTE - (PORT dataa (410:410:410) (491:491:491)) - (PORT datab (530:530:530) (620:620:620)) - (PORT datac (591:591:591) (686:686:686)) - (PORT datad (499:499:499) (600:600:600)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel_pla82M1T1_16) - (DELAY - (ABSOLUTE - (PORT dataa (836:836:836) (969:969:969)) - (PORT datab (689:689:689) (813:813:813)) - (PORT datac (812:812:812) (946:946:946)) - (PORT datad (630:630:630) (718:718:718)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1014:1014:1014) (1193:1193:1193)) - (PORT datab (1143:1143:1143) (1332:1332:1332)) - (PORT datac (720:720:720) (823:823:823)) - (PORT datad (1122:1122:1122) (1302:1302:1302)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~7) - (DELAY - (ABSOLUTE - (PORT dataa (622:622:622) (753:753:753)) - (PORT datab (348:348:348) (399:399:399)) - (PORT datac (674:674:674) (787:787:787)) - (PORT datad (322:322:322) (364:364:364)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel\[0\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (617:617:617) (711:711:711)) - (PORT datab (455:455:455) (523:523:523)) - (PORT datad (296:296:296) (342:342:342)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (158:158:158)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~2) - (DELAY - (ABSOLUTE - (PORT datac (989:989:989) (1149:1149:1149)) - (PORT datad (879:879:879) (1038:1038:1038)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~25) - (DELAY - (ABSOLUTE - (PORT dataa (563:563:563) (657:657:657)) - (PORT datab (587:587:587) (695:695:695)) - (PORT datac (594:594:594) (709:709:709)) - (PORT datad (341:341:341) (395:395:395)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (890:890:890) (1056:1056:1056)) - (PORT datab (106:106:106) (135:135:135)) - (PORT datac (595:595:595) (710:710:710)) - (PORT datad (1013:1013:1013) (1180:1180:1180)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~10) - (DELAY - (ABSOLUTE - (PORT dataa (663:663:663) (770:770:770)) - (PORT datab (362:362:362) (426:426:426)) - (PORT datac (716:716:716) (846:846:846)) - (PORT datad (886:886:886) (1036:1036:1036)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~48) - (DELAY - (ABSOLUTE - (PORT dataa (115:115:115) (146:146:146)) - (PORT datab (111:111:111) (142:142:142)) - (PORT datac (714:714:714) (844:844:844)) - (PORT datad (888:888:888) (1038:1038:1038)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (689:689:689) (789:789:789)) - (PORT datab (900:900:900) (1019:1019:1019)) - (PORT datac (423:423:423) (478:478:478)) - (PORT datad (317:317:317) (366:366:366)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (327:327:327) (387:387:387)) - (PORT datab (361:361:361) (425:425:425)) - (PORT datac (382:382:382) (448:448:448)) - (PORT datad (467:467:467) (555:555:555)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~17) - (DELAY - (ABSOLUTE - (PORT dataa (547:547:547) (652:652:652)) - (PORT datab (912:912:912) (1061:1061:1061)) - (PORT datac (886:886:886) (1038:1038:1038)) - (PORT datad (539:539:539) (626:626:626)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~5) - (DELAY - (ABSOLUTE - (PORT dataa (718:718:718) (837:837:837)) - (PORT datab (509:509:509) (594:594:594)) - (PORT datac (543:543:543) (642:642:642)) - (PORT datad (632:632:632) (725:725:725)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~6) - (DELAY - (ABSOLUTE - (PORT dataa (182:182:182) (223:223:223)) - (PORT datab (807:807:807) (925:925:925)) - (PORT datac (598:598:598) (678:678:678)) - (PORT datad (743:743:743) (846:846:846)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~10) - (DELAY - (ABSOLUTE - (PORT dataa (183:183:183) (225:225:225)) - (PORT datab (126:126:126) (154:154:154)) - (PORT datac (581:581:581) (690:690:690)) - (PORT datad (768:768:768) (885:885:885)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla21M2T3_4) - (DELAY - (ABSOLUTE - (PORT dataa (474:474:474) (543:543:543)) - (PORT datab (190:190:190) (228:228:228)) - (PORT datac (365:365:365) (419:419:419)) - (PORT datad (449:449:449) (521:521:521)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~7) - (DELAY - (ABSOLUTE - (PORT dataa (395:395:395) (485:485:485)) - (PORT datab (522:522:522) (616:616:616)) - (PORT datac (534:534:534) (632:632:632)) - (PORT datad (102:102:102) (119:119:119)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~1) - (DELAY - (ABSOLUTE - (PORT dataa (822:822:822) (959:959:959)) - (PORT datab (327:327:327) (388:388:388)) - (PORT datac (677:677:677) (785:785:785)) - (PORT datad (447:447:447) (511:511:511)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (120:120:120) (152:152:152)) - (PORT datab (110:110:110) (141:141:141)) - (PORT datac (309:309:309) (352:352:352)) - (PORT datad (464:464:464) (538:538:538)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~6) - (DELAY - (ABSOLUTE - (PORT dataa (666:666:666) (774:774:774)) - (PORT datab (537:537:537) (628:628:628)) - (PORT datac (608:608:608) (716:716:716)) - (PORT datad (810:810:810) (922:922:922)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~7) - (DELAY - (ABSOLUTE - (PORT dataa (624:624:624) (741:741:741)) - (PORT datab (543:543:543) (635:635:635)) - (PORT datac (158:158:158) (190:190:190)) - (PORT datad (346:346:346) (400:400:400)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~4) - (DELAY - (ABSOLUTE - (PORT dataa (575:575:575) (674:674:674)) - (PORT datab (761:761:761) (862:862:862)) - (PORT datac (650:650:650) (750:750:750)) - (PORT datad (664:664:664) (763:763:763)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~5) - (DELAY - (ABSOLUTE - (PORT dataa (108:108:108) (142:142:142)) - (PORT datab (684:684:684) (790:790:790)) - (PORT datac (553:553:553) (651:651:651)) - (PORT datad (344:344:344) (398:398:398)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla20M1T5_5) - (DELAY - (ABSOLUTE - (PORT dataa (477:477:477) (546:546:546)) - (PORT datab (793:793:793) (910:910:910)) - (PORT datac (931:931:931) (1064:1064:1064)) - (PORT datad (1156:1156:1156) (1339:1339:1339)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (333:333:333) (390:390:390)) - (PORT datab (111:111:111) (142:142:142)) - (PORT datac (802:802:802) (918:918:918)) - (PORT datad (792:792:792) (911:911:911)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1014:1014:1014) (1189:1189:1189)) - (PORT datab (452:452:452) (517:517:517)) - (PORT datac (459:459:459) (521:521:521)) - (PORT datad (1156:1156:1156) (1340:1340:1340)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~1) - (DELAY - (ABSOLUTE - (PORT dataa (439:439:439) (511:511:511)) - (PORT datab (419:419:419) (486:486:486)) - (PORT datac (88:88:88) (110:110:110)) - (PORT datad (91:91:91) (108:108:108)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~2) - (DELAY - (ABSOLUTE - (PORT dataa (178:178:178) (218:218:218)) - (PORT datab (115:115:115) (144:144:144)) - (PORT datac (103:103:103) (125:125:125)) - (PORT datad (287:287:287) (330:330:330)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (530:530:530) (618:618:618)) - (PORT datab (463:463:463) (527:527:527)) - (PORT datac (958:958:958) (1116:1116:1116)) - (PORT datad (640:640:640) (747:747:747)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (729:729:729) (831:831:831)) - (PORT datab (658:658:658) (760:760:760)) - (PORT datac (619:619:619) (706:706:706)) - (PORT datad (370:370:370) (438:438:438)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (650:650:650) (763:763:763)) - (PORT datac (314:314:314) (366:366:366)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (644:644:644) (757:757:757)) - (PORT datab (349:349:349) (411:411:411)) - (PORT datac (103:103:103) (133:133:133)) - (PORT datad (329:329:329) (379:379:379)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~7) - (DELAY - (ABSOLUTE - (PORT dataa (120:120:120) (153:153:153)) - (PORT datac (1178:1178:1178) (1367:1367:1367)) - (PORT datad (827:827:827) (965:965:965)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel_pla66npla53M1T1_15) - (DELAY - (ABSOLUTE - (PORT dataa (215:215:215) (266:266:266)) - (PORT datab (640:640:640) (738:738:738)) - (PORT datac (814:814:814) (949:949:949)) - (PORT datad (618:618:618) (707:707:707)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (623:623:623) (739:739:739)) - (PORT datab (588:588:588) (702:702:702)) - (PORT datac (650:650:650) (750:750:750)) - (PORT datad (663:663:663) (763:763:763)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~8) - (DELAY - (ABSOLUTE - (PORT dataa (476:476:476) (540:540:540)) - (PORT datab (362:362:362) (423:423:423)) - (PORT datac (598:598:598) (686:686:686)) - (PORT datad (410:410:410) (473:473:473)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~8) - (DELAY - (ABSOLUTE - (PORT dataa (602:602:602) (704:704:704)) - (PORT datab (881:881:881) (1027:1027:1027)) - (PORT datac (339:339:339) (403:403:403)) - (PORT datad (97:97:97) (117:117:117)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~4) - (DELAY - (ABSOLUTE - (PORT dataa (404:404:404) (469:469:469)) - (PORT datab (459:459:459) (531:531:531)) - (PORT datac (429:429:429) (487:487:487)) - (PORT datad (362:362:362) (424:424:424)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~9) - (DELAY - (ABSOLUTE - (PORT dataa (577:577:577) (675:675:675)) - (PORT datab (541:541:541) (634:634:634)) - (PORT datac (101:101:101) (122:122:122)) - (PORT datad (810:810:810) (922:922:922)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~10) - (DELAY - (ABSOLUTE - (PORT dataa (729:729:729) (859:859:859)) - (PORT datab (541:541:541) (633:633:633)) - (PORT datac (608:608:608) (717:717:717)) - (PORT datad (875:875:875) (1029:1029:1029)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~43) - (DELAY - (ABSOLUTE - (PORT dataa (729:729:729) (859:859:859)) - (PORT datab (684:684:684) (790:790:790)) - (PORT datac (553:553:553) (651:651:651)) - (PORT datad (875:875:875) (1030:1030:1030)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~26) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (133:133:133)) - (PORT datac (92:92:92) (115:115:115)) - (PORT datad (95:95:95) (115:115:115)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (295:295:295) (341:341:341)) - (PORT datab (127:127:127) (161:161:161)) - (PORT datac (282:282:282) (323:323:323)) - (PORT datad (801:801:801) (933:933:933)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~9) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (134:134:134)) - (PORT datab (735:735:735) (853:853:853)) - (PORT datac (296:296:296) (342:342:342)) - (PORT datad (313:313:313) (366:366:366)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~11) - (DELAY - (ABSOLUTE - (PORT dataa (374:374:374) (448:448:448)) - (PORT datab (608:608:608) (701:701:701)) - (PORT datac (519:519:519) (611:611:611)) - (PORT datad (647:647:647) (744:744:744)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~5) - (DELAY - (ABSOLUTE - (PORT dataa (516:516:516) (609:609:609)) - (PORT datab (533:533:533) (618:618:618)) - (PORT datac (671:671:671) (792:792:792)) - (PORT datad (199:199:199) (230:230:230)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~11) - (DELAY - (ABSOLUTE - (PORT dataa (971:971:971) (1110:1110:1110)) - (PORT datab (896:896:896) (1028:1028:1028)) - (PORT datac (730:730:730) (858:858:858)) - (PORT datad (881:881:881) (1044:1044:1044)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~6) - (DELAY - (ABSOLUTE - (PORT dataa (609:609:609) (704:704:704)) - (PORT datab (597:597:597) (694:694:694)) - (PORT datac (528:528:528) (615:615:615)) - (PORT datad (438:438:438) (504:504:504)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~7) - (DELAY - (ABSOLUTE - (PORT dataa (543:543:543) (639:639:639)) - (PORT datab (374:374:374) (440:440:440)) - (PORT datac (115:115:115) (143:143:143)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~12) - (DELAY - (ABSOLUTE - (PORT dataa (463:463:463) (536:536:536)) - (PORT datab (349:349:349) (410:410:410)) - (PORT datac (485:485:485) (557:557:557)) - (PORT datad (444:444:444) (508:508:508)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~13) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (134:134:134)) - (PORT datab (186:186:186) (226:226:226)) - (PORT datac (556:556:556) (646:646:646)) - (PORT datad (305:305:305) (359:359:359)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~14) - (DELAY - (ABSOLUTE - (PORT dataa (116:116:116) (147:147:147)) - (PORT datac (952:952:952) (1085:1085:1085)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (129:129:129) (165:165:165)) - (PORT datab (654:654:654) (759:759:759)) - (PORT datac (672:672:672) (775:775:775)) - (PORT datad (283:283:283) (329:329:329)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (609:609:609) (705:705:705)) - (PORT datab (132:132:132) (166:166:166)) - (PORT datac (484:484:484) (566:566:566)) - (PORT datad (1090:1090:1090) (1242:1242:1242)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~40) - (DELAY - (ABSOLUTE - (PORT dataa (440:440:440) (509:509:509)) - (PORT datab (459:459:459) (533:533:533)) - (PORT datac (305:305:305) (363:363:363)) - (PORT datad (437:437:437) (496:496:496)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~53) - (DELAY - (ABSOLUTE - (PORT dataa (1198:1198:1198) (1392:1392:1392)) - (PORT datab (994:994:994) (1150:1150:1150)) - (PORT datac (474:474:474) (554:554:554)) - (PORT datad (1331:1331:1331) (1541:1541:1541)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~8) - (DELAY - (ABSOLUTE - (PORT dataa (536:536:536) (632:632:632)) - (PORT datab (1179:1179:1179) (1363:1363:1363)) - (PORT datac (287:287:287) (333:333:333)) - (PORT datad (1092:1092:1092) (1271:1271:1271)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (166:166:166) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~54) - (DELAY - (ABSOLUTE - (PORT dataa (988:988:988) (1156:1156:1156)) - (PORT datab (631:631:631) (745:745:745)) - (PORT datac (542:542:542) (622:622:622)) - (PORT datad (1123:1123:1123) (1309:1309:1309)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~1) - (DELAY - (ABSOLUTE - (PORT dataa (654:654:654) (789:789:789)) - (PORT datab (648:648:648) (756:756:756)) - (PORT datac (320:320:320) (378:378:378)) - (PORT datad (1286:1286:1286) (1469:1469:1469)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~4) - (DELAY - (ABSOLUTE - (PORT dataa (541:541:541) (627:627:627)) - (PORT datab (626:626:626) (720:720:720)) - (PORT datac (181:181:181) (222:222:222)) - (PORT datad (341:341:341) (406:406:406)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~5) - (DELAY - (ABSOLUTE - (PORT dataa (465:465:465) (548:548:548)) - (PORT datac (464:464:464) (528:528:528)) - (PORT datad (279:279:279) (316:316:316)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~6) - (DELAY - (ABSOLUTE - (PORT dataa (129:129:129) (165:165:165)) - (PORT datab (133:133:133) (168:168:168)) - (PORT datac (1121:1121:1121) (1299:1299:1299)) - (PORT datad (107:107:107) (132:132:132)) - (IOPATH dataa combout (165:165:165) (163:163:163)) - (IOPATH datab combout (188:188:188) (193:193:193)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~35) - (DELAY - (ABSOLUTE - (PORT dataa (767:767:767) (919:919:919)) - (PORT datab (731:731:731) (841:841:841)) - (PORT datac (471:471:471) (548:548:548)) - (PORT datad (816:816:816) (944:944:944)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (622:622:622) (753:753:753)) - (PORT datab (386:386:386) (461:461:461)) - (PORT datac (538:538:538) (632:632:632)) - (PORT datad (327:327:327) (376:376:376)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~6) - (DELAY - (ABSOLUTE - (PORT dataa (336:336:336) (390:390:390)) - (PORT datab (545:545:545) (654:654:654)) - (PORT datac (970:970:970) (1135:1135:1135)) - (PORT datad (621:621:621) (720:720:720)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1098:1098:1098) (1260:1260:1260)) - (PORT datab (471:471:471) (556:556:556)) - (PORT datac (765:765:765) (900:900:900)) - (PORT datad (784:784:784) (899:899:899)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~0) - (DELAY - (ABSOLUTE - (PORT dataa (321:321:321) (381:381:381)) - (PORT datab (594:594:594) (706:706:706)) - (PORT datac (109:109:109) (135:135:135)) - (PORT datad (488:488:488) (568:568:568)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~3) - (DELAY - (ABSOLUTE - (PORT dataa (319:319:319) (374:374:374)) - (PORT datab (105:105:105) (135:135:135)) - (PORT datac (482:482:482) (557:557:557)) - (PORT datad (463:463:463) (533:533:533)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~52) - (DELAY - (ABSOLUTE - (PORT dataa (967:967:967) (1114:1114:1114)) - (PORT datab (591:591:591) (723:723:723)) - (PORT datac (676:676:676) (794:794:794)) - (PORT datad (467:467:467) (542:542:542)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (379:379:379) (450:450:450)) - (PORT datab (648:648:648) (760:760:760)) - (PORT datac (824:824:824) (943:943:943)) - (PORT datad (832:832:832) (958:958:958)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~2) - (DELAY - (ABSOLUTE - (PORT dataa (463:463:463) (539:539:539)) - (PORT datab (747:747:747) (852:852:852)) - (PORT datac (415:415:415) (480:480:480)) - (PORT datad (970:970:970) (1105:1105:1105)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|rsel3) - (DELAY - (ABSOLUTE - (PORT dataa (770:770:770) (910:910:910)) - (PORT datab (1305:1305:1305) (1522:1522:1522)) - (PORT datac (615:615:615) (716:716:716)) - (IOPATH dataa combout (188:188:188) (203:203:203)) - (IOPATH datab combout (190:190:190) (205:205:205)) - (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~5) - (DELAY - (ABSOLUTE - (PORT dataa (531:531:531) (624:624:624)) - (PORT datab (567:567:567) (659:659:659)) - (PORT datac (96:96:96) (120:120:120)) - (PORT datad (354:354:354) (414:414:414)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~6) - (DELAY - (ABSOLUTE - (PORT dataa (310:310:310) (369:369:369)) - (PORT datab (369:369:369) (432:432:432)) - (PORT datac (264:264:264) (301:301:301)) - (PORT datad (463:463:463) (533:533:533)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~7) - (DELAY - (ABSOLUTE - (PORT dataa (110:110:110) (144:144:144)) - (PORT datab (486:486:486) (561:561:561)) - (PORT datac (485:485:485) (559:559:559)) - (PORT datad (96:96:96) (116:116:116)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|rsel0) - (DELAY - (ABSOLUTE - (PORT dataa (1255:1255:1255) (1469:1469:1469)) - (PORT datac (812:812:812) (947:947:947)) - (PORT datad (1276:1276:1276) (1472:1472:1472)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_ixy_dT2_2) - (DELAY - (ABSOLUTE - (PORT datab (530:530:530) (627:627:627)) - (PORT datac (861:861:861) (1011:1011:1011)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (380:380:380) (446:446:446)) - (PORT datab (460:460:460) (536:536:536)) - (PORT datac (734:734:734) (872:872:872)) - (PORT datad (483:483:483) (564:564:564)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~6) - (DELAY - (ABSOLUTE - (PORT dataa (835:835:835) (964:964:964)) - (PORT datab (107:107:107) (136:136:136)) - (PORT datac (572:572:572) (655:655:655)) - (PORT datad (573:573:573) (670:670:670)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~7) - (DELAY - (ABSOLUTE - (PORT dataa (124:124:124) (160:160:160)) - (PORT datab (190:190:190) (227:227:227)) - (PORT datac (331:331:331) (387:387:387)) - (PORT datad (106:106:106) (129:129:129)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_iorw\~11) - (DELAY - (ABSOLUTE - (PORT dataa (923:923:923) (1088:1088:1088)) - (PORT datab (874:874:874) (1029:1029:1029)) - (PORT datac (978:978:978) (1128:1128:1128)) - (PORT datad (817:817:817) (933:933:933)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~10) - (DELAY - (ABSOLUTE - (PORT dataa (992:992:992) (1133:1133:1133)) - (PORT datab (370:370:370) (439:439:439)) - (PORT datac (287:287:287) (334:334:334)) - (PORT datad (622:622:622) (722:722:722)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~14) - (DELAY - (ABSOLUTE - (PORT dataa (389:389:389) (463:463:463)) - (PORT datab (555:555:555) (664:664:664)) - (PORT datac (101:101:101) (121:121:121)) - (PORT datad (716:716:716) (833:833:833)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~11) - (DELAY - (ABSOLUTE - (PORT dataa (313:313:313) (368:368:368)) - (PORT datab (477:477:477) (554:554:554)) - (PORT datac (175:175:175) (209:209:209)) - (PORT datad (384:384:384) (454:454:454)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~12) - (DELAY - (ABSOLUTE - (PORT dataa (357:357:357) (422:422:422)) - (PORT datab (530:530:530) (611:611:611)) - (PORT datac (315:315:315) (365:365:365)) - (PORT datad (356:356:356) (417:417:417)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~13) - (DELAY - (ABSOLUTE - (PORT dataa (612:612:612) (705:705:705)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (298:298:298) (348:348:348)) - (PORT datad (94:94:94) (114:114:114)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_66_oe) - (DELAY - (ABSOLUTE - (PORT dataa (205:205:205) (283:283:283)) - (PORT datab (723:723:723) (852:852:852)) - (PORT datac (383:383:383) (464:464:464)) - (PORT datad (731:731:731) (868:868:868)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~34) - (DELAY - (ABSOLUTE - (PORT dataa (886:886:886) (1020:1020:1020)) - (PORT datab (492:492:492) (582:582:582)) - (PORT datac (706:706:706) (818:818:818)) - (PORT datad (917:917:917) (1048:1048:1048)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_apin_mux\~0) - (DELAY - (ABSOLUTE - (PORT dataa (192:192:192) (229:229:229)) - (PORT datab (117:117:117) (146:146:146)) - (PORT datac (366:366:366) (437:437:437)) - (PORT datad (918:918:918) (1050:1050:1050)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~5) - (DELAY - (ABSOLUTE - (PORT dataa (741:741:741) (866:866:866)) - (PORT datab (663:663:663) (763:763:763)) - (PORT datac (634:634:634) (740:740:740)) - (PORT datad (752:752:752) (892:892:892)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~75) - (DELAY - (ABSOLUTE - (PORT dataa (486:486:486) (561:561:561)) - (PORT datab (193:193:193) (235:235:235)) - (PORT datac (360:360:360) (431:431:431)) - (PORT datad (661:661:661) (765:765:765)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~76) - (DELAY - (ABSOLUTE - (PORT dataa (584:584:584) (672:672:672)) - (PORT datab (482:482:482) (567:567:567)) - (PORT datac (579:579:579) (678:678:678)) - (PORT datad (481:481:481) (566:566:566)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (107:107:107) (138:138:138)) - (PORT datab (534:534:534) (641:641:641)) - (PORT datac (469:469:469) (537:537:537)) - (PORT datad (501:501:501) (584:584:584)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~48) - (DELAY - (ABSOLUTE - (PORT dataa (544:544:544) (649:649:649)) - (PORT datab (658:658:658) (766:766:766)) - (PORT datac (883:883:883) (1035:1035:1035)) - (PORT datad (636:636:636) (741:741:741)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~46) - (DELAY - (ABSOLUTE - (PORT dataa (339:339:339) (405:405:405)) - (PORT datab (1177:1177:1177) (1396:1396:1396)) - (PORT datac (470:470:470) (542:542:542)) - (PORT datad (682:682:682) (803:803:803)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~53) - (DELAY - (ABSOLUTE - (PORT dataa (492:492:492) (578:578:578)) - (PORT datab (477:477:477) (561:561:561)) - (PORT datac (603:603:603) (695:695:695)) - (PORT datad (482:482:482) (568:568:568)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~92) - (DELAY - (ABSOLUTE - (PORT dataa (573:573:573) (682:682:682)) - (PORT datab (908:908:908) (1071:1071:1071)) - (PORT datac (341:341:341) (391:391:391)) - (PORT datad (959:959:959) (1118:1118:1118)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal19\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1348:1348:1348) (1572:1572:1572)) - (PORT datab (930:930:930) (1114:1114:1114)) - (PORT datac (515:515:515) (597:597:597)) - (PORT datad (376:376:376) (440:440:440)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~0) - (DELAY - (ABSOLUTE - (PORT dataa (568:568:568) (676:676:676)) - (PORT datad (880:880:880) (1030:1030:1030)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~38) - (DELAY - (ABSOLUTE - (PORT dataa (742:742:742) (866:866:866)) - (PORT datab (360:360:360) (425:425:425)) - (PORT datac (754:754:754) (862:862:862)) - (PORT datad (479:479:479) (556:556:556)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~93) - (DELAY - (ABSOLUTE - (PORT dataa (625:625:625) (720:720:720)) - (PORT datab (973:973:973) (1143:1143:1143)) - (PORT datac (891:891:891) (1050:1050:1050)) - (PORT datad (559:559:559) (657:657:657)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~39) - (DELAY - (ABSOLUTE - (PORT dataa (772:772:772) (924:924:924)) - (PORT datab (455:455:455) (530:530:530)) - (PORT datac (609:609:609) (694:694:694)) - (PORT datad (355:355:355) (422:422:422)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~24) - (DELAY - (ABSOLUTE - (PORT datab (653:653:653) (759:759:759)) - (PORT datac (103:103:103) (124:124:124)) - (PORT datad (97:97:97) (117:117:117)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~1) - (DELAY - (ABSOLUTE - (PORT dataa (115:115:115) (146:146:146)) - (PORT datab (466:466:466) (543:543:543)) - (PORT datac (103:103:103) (131:131:131)) - (PORT datad (372:372:372) (448:448:448)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla9M1T5_2) - (DELAY - (ABSOLUTE - (PORT dataa (541:541:541) (637:637:637)) - (PORT datab (518:518:518) (603:603:603)) - (PORT datac (782:782:782) (906:906:906)) - (PORT datad (285:285:285) (323:323:323)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~44) - (DELAY - (ABSOLUTE - (PORT dataa (317:317:317) (373:373:373)) - (PORT datab (472:472:472) (548:548:548)) - (PORT datac (768:768:768) (902:902:902)) - (PORT datad (837:837:837) (992:992:992)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (510:510:510) (605:605:605)) - (PORT datab (478:478:478) (562:562:562)) - (PORT datac (502:502:502) (594:594:594)) - (PORT datad (861:861:861) (1018:1018:1018)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~0) - (DELAY - (ABSOLUTE - (PORT dataa (626:626:626) (735:735:735)) - (PORT datab (345:345:345) (419:419:419)) - (PORT datac (496:496:496) (578:578:578)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla10M5T4_2) - (DELAY - (ABSOLUTE - (PORT datab (841:841:841) (988:988:988)) - (PORT datac (974:974:974) (1125:1125:1125)) - (PORT datad (587:587:587) (666:666:666)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (378:378:378) (441:441:441)) - (PORT datab (657:657:657) (752:752:752)) - (PORT datac (468:468:468) (540:540:540)) - (PORT datad (660:660:660) (773:773:773)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~2) - (DELAY - (ABSOLUTE - (PORT dataa (504:504:504) (595:595:595)) - (PORT datab (520:520:520) (613:613:613)) - (PORT datac (345:345:345) (409:409:409)) - (PORT datad (629:629:629) (732:732:732)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~3) - (DELAY - (ABSOLUTE - (PORT datab (476:476:476) (555:555:555)) - (PORT datac (93:93:93) (116:116:116)) - (PORT datad (465:465:465) (535:535:535)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~3) - (DELAY - (ABSOLUTE - (PORT dataa (558:558:558) (633:633:633)) - (PORT datab (811:811:811) (939:939:939)) - (PORT datac (711:711:711) (816:816:816)) - (PORT datad (463:463:463) (532:532:532)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~4) - (DELAY - (ABSOLUTE - (PORT dataa (943:943:943) (1083:1083:1083)) - (PORT datab (919:919:919) (1069:1069:1069)) - (PORT datac (837:837:837) (986:986:986)) - (PORT datad (465:465:465) (533:533:533)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla38pla13M4T2_4) - (DELAY - (ABSOLUTE - (PORT dataa (809:809:809) (936:936:936)) - (PORT datab (920:920:920) (1071:1071:1071)) - (PORT datac (925:925:925) (1058:1058:1058)) - (PORT datad (655:655:655) (760:760:760)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~15) - (DELAY - (ABSOLUTE - (PORT dataa (486:486:486) (576:576:576)) - (PORT datab (318:318:318) (370:370:370)) - (PORT datac (836:836:836) (966:966:966)) - (PORT datad (306:306:306) (350:350:350)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (516:516:516) (597:597:597)) - (PORT datab (500:500:500) (584:584:584)) - (PORT datac (481:481:481) (564:564:564)) - (PORT datad (103:103:103) (120:120:120)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~94) - (DELAY - (ABSOLUTE - (PORT dataa (1015:1015:1015) (1177:1177:1177)) - (PORT datab (971:971:971) (1140:1140:1140)) - (PORT datac (892:892:892) (1051:1051:1051)) - (PORT datad (561:561:561) (658:658:658)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~87) - (DELAY - (ABSOLUTE - (PORT dataa (921:921:921) (1090:1090:1090)) - (PORT datac (1406:1406:1406) (1623:1623:1623)) - (PORT datad (835:835:835) (990:990:990)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~42) - (DELAY - (ABSOLUTE - (PORT dataa (639:639:639) (733:733:733)) - (PORT datab (652:652:652) (753:753:753)) - (PORT datac (103:103:103) (124:124:124)) - (PORT datad (469:469:469) (539:539:539)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~34) - (DELAY - (ABSOLUTE - (PORT datab (365:365:365) (434:434:434)) - (PORT datac (201:201:201) (241:241:241)) - (PORT datad (107:107:107) (127:127:127)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~16) - (DELAY - (ABSOLUTE - (PORT dataa (239:239:239) (285:285:285)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (432:432:432) (496:496:496)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~6) - (DELAY - (ABSOLUTE - (PORT dataa (193:193:193) (236:236:236)) - (PORT datab (480:480:480) (553:553:553)) - (PORT datac (336:336:336) (397:397:397)) - (PORT datad (667:667:667) (771:771:771)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal2\~2) - (DELAY - (ABSOLUTE - (PORT dataa (709:709:709) (831:831:831)) - (PORT datab (935:935:935) (1119:1119:1119)) - (PORT datac (518:518:518) (601:601:601)) - (PORT datad (517:517:517) (606:606:606)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal1\~6) - (DELAY - (ABSOLUTE - (PORT dataa (822:822:822) (960:960:960)) - (PORT datab (959:959:959) (1114:1114:1114)) - (PORT datac (446:446:446) (515:515:515)) - (PORT datad (358:358:358) (424:424:424)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|bank_exx\~2) - (DELAY - (ABSOLUTE - (PORT dataa (787:787:787) (943:943:943)) - (PORT datab (491:491:491) (569:569:569)) - (PORT datad (1310:1310:1310) (1532:1532:1532)) - (IOPATH dataa combout (159:159:159) (173:173:173)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_control_\|bank_exx) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (908:908:908)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (914:914:914) (898:898:898)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|bank_hl_de1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (635:635:635) (739:739:739)) - (PORT datab (660:660:660) (759:759:759)) - (PORT datad (671:671:671) (796:796:796)) - (IOPATH dataa combout (192:192:192) (184:184:184)) - (IOPATH datab combout (182:182:182) (193:193:193)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_control_\|bank_hl_de1) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (922:922:922)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (929:929:929) (911:911:911)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (514:514:514) (597:597:597)) - (PORT datab (1135:1135:1135) (1296:1296:1296)) - (PORT datac (427:427:427) (493:493:493)) - (PORT datad (177:177:177) (207:207:207)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (503:503:503) (593:593:593)) - (PORT datab (953:953:953) (1084:1084:1084)) - (PORT datac (698:698:698) (818:818:818)) - (PORT datad (630:630:630) (733:733:733)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (410:410:410) (472:472:472)) - (PORT datab (102:102:102) (131:131:131)) - (PORT datac (698:698:698) (819:819:819)) - (PORT datad (863:863:863) (1020:1020:1020)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~7) - (DELAY - (ABSOLUTE - (PORT dataa (669:669:669) (793:793:793)) - (PORT datab (732:732:732) (861:861:861)) - (PORT datac (629:629:629) (733:733:733)) - (PORT datad (403:403:403) (485:485:485)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (330:330:330) (395:395:395)) - (PORT datab (308:308:308) (356:356:356)) - (PORT datac (494:494:494) (576:576:576)) - (PORT datad (981:981:981) (1128:1128:1128)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (514:514:514) (597:597:597)) - (PORT datab (186:186:186) (222:222:222)) - (PORT datac (645:645:645) (746:746:746)) - (PORT datad (1145:1145:1145) (1339:1339:1339)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (175:175:175) (212:212:212)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (89:89:89) (111:111:111)) - (PORT datad (489:489:489) (568:568:568)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~47) - (DELAY - (ABSOLUTE - (PORT dataa (549:549:549) (652:652:652)) - (PORT datab (518:518:518) (615:615:615)) - (PORT datac (584:584:584) (657:657:657)) - (PORT datad (581:581:581) (648:648:648)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~3) - (DELAY - (ABSOLUTE - (PORT dataa (762:762:762) (897:897:897)) - (PORT datab (498:498:498) (585:585:585)) - (PORT datac (356:356:356) (420:420:420)) - (PORT datad (635:635:635) (739:739:739)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1149:1149:1149) (1325:1325:1325)) - (PORT datac (919:919:919) (1039:1039:1039)) - (PORT datad (967:967:967) (1114:1114:1114)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~2) - (DELAY - (ABSOLUTE - (PORT dataa (565:565:565) (657:657:657)) - (PORT datab (729:729:729) (840:840:840)) - (PORT datac (765:765:765) (881:881:881)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~19) - (DELAY - (ABSOLUTE - (PORT datab (355:355:355) (410:410:410)) - (PORT datac (347:347:347) (408:408:408)) - (PORT datad (506:506:506) (589:589:589)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (355:355:355) (418:418:418)) - (PORT datab (384:384:384) (447:447:447)) - (PORT datac (369:369:369) (448:448:448)) - (PORT datad (440:440:440) (506:506:506)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (458:458:458) (541:541:541)) - (PORT datac (1089:1089:1089) (1248:1248:1248)) - (PORT datad (106:106:106) (130:130:130)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (342:342:342) (408:408:408)) - (PORT datab (484:484:484) (566:566:566)) - (PORT datac (603:603:603) (690:690:690)) - (PORT datad (450:450:450) (521:521:521)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (604:604:604) (734:734:734)) - (PORT datab (567:567:567) (668:668:668)) - (PORT datac (770:770:770) (894:894:894)) - (PORT datad (106:106:106) (131:131:131)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (605:605:605) (736:736:736)) - (PORT datab (1101:1101:1101) (1277:1277:1277)) - (PORT datac (627:627:627) (722:722:722)) - (PORT datad (523:523:523) (615:615:615)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~17) + (INSTANCE z80_\|interrupts_\|iff1\~1) (DELAY (ABSOLUTE (PORT dataa (104:104:104) (135:135:135)) - (PORT datab (104:104:104) (134:134:134)) - (PORT datac (1507:1507:1507) (1752:1752:1752)) - (PORT datad (102:102:102) (119:119:119)) + (PORT datab (560:560:560) (658:658:658)) + (PORT datac (132:132:132) (174:174:174)) + (PORT datad (619:619:619) (697:697:697)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_15) + (DELAY + (ABSOLUTE + (PORT dataa (262:262:262) (342:342:342)) + (PORT datac (147:147:147) (197:197:197)) + (PORT datad (1633:1633:1633) (1896:1896:1896)) (IOPATH dataa combout (165:165:165) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (522:522:522) (627:627:627)) - (PORT datac (614:614:614) (716:716:716)) - (PORT datad (629:629:629) (727:727:727)) - (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~2) - (DELAY - (ABSOLUTE - (PORT dataa (545:545:545) (627:627:627)) - (PORT datab (449:449:449) (517:517:517)) - (PORT datac (1117:1117:1117) (1276:1276:1276)) - (PORT datad (774:774:774) (885:885:885)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~47) - (DELAY - (ABSOLUTE - (PORT dataa (902:902:902) (1057:1057:1057)) - (PORT datab (498:498:498) (586:586:586)) - (PORT datac (510:510:510) (598:598:598)) - (PORT datad (857:857:857) (1010:1010:1010)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~3) - (DELAY - (ABSOLUTE - (PORT dataa (337:337:337) (407:407:407)) - (PORT datab (461:461:461) (537:537:537)) - (PORT datac (338:338:338) (398:398:398)) - (PORT datad (435:435:435) (494:494:494)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~9) - (DELAY - (ABSOLUTE - (PORT dataa (616:616:616) (758:758:758)) - (PORT datac (784:784:784) (900:900:900)) - (PORT datad (1170:1170:1170) (1359:1359:1359)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (506:506:506) (599:599:599)) - (PORT datab (901:901:901) (1063:1063:1063)) - (PORT datac (114:114:114) (141:141:141)) - (PORT datad (334:334:334) (384:384:384)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (761:761:761) (889:889:889)) - (PORT datab (330:330:330) (387:387:387)) - (PORT datac (415:415:415) (481:481:481)) - (PORT datad (318:318:318) (369:369:369)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (932:932:932) (1074:1074:1074)) - (PORT datab (609:609:609) (691:691:691)) - (PORT datac (596:596:596) (705:705:705)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~49) - (DELAY - (ABSOLUTE - (PORT dataa (743:743:743) (891:891:891)) - (PORT datab (106:106:106) (136:136:136)) - (PORT datac (325:325:325) (376:376:376)) - (PORT datad (819:819:819) (947:947:947)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (305:305:305) (357:357:357)) - (PORT datab (344:344:344) (408:408:408)) - (PORT datac (325:325:325) (383:383:383)) - (PORT datad (304:304:304) (348:348:348)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1261:1261:1261) (1461:1461:1461)) - (PORT datab (140:140:140) (187:187:187)) - (PORT datac (637:637:637) (730:730:730)) - (PORT datad (128:128:128) (165:165:165)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (134:134:134)) - (PORT datab (102:102:102) (131:131:131)) - (PORT datac (92:92:92) (116:116:116)) - (PORT datad (480:480:480) (556:556:556)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~28) - (DELAY - (ABSOLUTE - (PORT datab (110:110:110) (140:140:140)) - (PORT datad (361:361:361) (422:422:422)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (116:116:116) (152:152:152)) - (PORT datab (565:565:565) (667:667:667)) - (PORT datac (170:170:170) (204:204:204)) - (PORT datad (387:387:387) (457:457:457)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~2) - (DELAY - (ABSOLUTE - (PORT dataa (658:658:658) (794:794:794)) - (PORT datac (495:495:495) (585:585:585)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~14) - (DELAY - (ABSOLUTE - (PORT datac (369:369:369) (448:448:448)) - (PORT datad (488:488:488) (560:560:560)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~10) - (DELAY - (ABSOLUTE - (PORT dataa (803:803:803) (928:928:928)) - (PORT datab (331:331:331) (393:393:393)) - (PORT datac (90:90:90) (112:112:112)) - (PORT datad (624:624:624) (709:709:709)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~47) - (DELAY - (ABSOLUTE - (PORT dataa (318:318:318) (371:371:371)) - (PORT datab (340:340:340) (397:397:397)) - (PORT datac (479:479:479) (553:553:553)) - (PORT datad (482:482:482) (556:556:556)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~48) - (DELAY - (ABSOLUTE - (PORT dataa (176:176:176) (219:219:219)) - (PORT datab (115:115:115) (143:143:143)) - (PORT datac (335:335:335) (395:395:395)) - (PORT datad (573:573:573) (656:656:656)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1150:1150:1150) (1326:1326:1326)) - (PORT datac (919:919:919) (1039:1039:1039)) - (PORT datad (967:967:967) (1114:1114:1114)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (765:765:765) (907:907:907)) - (PORT datab (604:604:604) (690:690:690)) - (PORT datac (516:516:516) (599:599:599)) - (PORT datad (293:293:293) (334:334:334)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_oe\~1) - (DELAY - (ABSOLUTE - (PORT dataa (122:122:122) (156:156:156)) - (PORT datab (120:120:120) (150:150:150)) - (PORT datac (654:654:654) (762:762:762)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~13) - (DELAY - (ABSOLUTE - (PORT dataa (447:447:447) (515:515:515)) - (PORT datab (712:712:712) (832:832:832)) - (PORT datac (1031:1031:1031) (1187:1187:1187)) - (PORT datad (1174:1174:1174) (1364:1364:1364)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (136:136:136)) - (PORT datab (328:328:328) (385:385:385)) - (PORT datac (305:305:305) (362:362:362)) - (PORT datad (463:463:463) (529:529:529)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~40) - (DELAY - (ABSOLUTE - (PORT dataa (771:771:771) (923:923:923)) - (PORT datab (414:414:414) (500:500:500)) - (PORT datac (475:475:475) (552:552:552)) - (PORT datad (502:502:502) (582:582:582)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~2) - (DELAY - (ABSOLUTE - (PORT dataa (471:471:471) (542:542:542)) - (PORT datab (383:383:383) (458:458:458)) - (PORT datac (538:538:538) (636:636:636)) - (PORT datad (996:996:996) (1148:1148:1148)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~12) - (DELAY - (ABSOLUTE - (PORT dataa (704:704:704) (836:836:836)) - (PORT datab (488:488:488) (567:567:567)) - (PORT datac (342:342:342) (392:392:392)) - (PORT datad (963:963:963) (1107:1107:1107)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~43) - (DELAY - (ABSOLUTE - (PORT dataa (773:773:773) (926:926:926)) - (PORT datab (366:366:366) (431:431:431)) - (PORT datac (477:477:477) (555:555:555)) - (PORT datad (199:199:199) (229:229:229)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~5) - (DELAY - (ABSOLUTE - (PORT dataa (500:500:500) (582:582:582)) - (PORT datab (386:386:386) (461:461:461)) - (PORT datac (547:547:547) (642:642:642)) - (PORT datad (335:335:335) (387:387:387)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (823:823:823) (941:941:941)) - (PORT datab (505:505:505) (589:589:589)) - (PORT datac (100:100:100) (122:122:122)) - (PORT datad (789:789:789) (906:906:906)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~6) - (DELAY - (ABSOLUTE - (PORT dataa (904:904:904) (1060:1060:1060)) - (PORT datab (872:872:872) (999:999:999)) - (PORT datac (560:560:560) (651:651:651)) - (PORT datad (878:878:878) (1014:1014:1014)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~7) - (DELAY - (ABSOLUTE - (PORT dataa (822:822:822) (954:954:954)) - (PORT datab (516:516:516) (618:618:618)) - (PORT datac (467:467:467) (556:556:556)) - (PORT datad (307:307:307) (356:356:356)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~8) - (DELAY - (ABSOLUTE - (PORT dataa (818:818:818) (950:950:950)) - (PORT datab (517:517:517) (619:619:619)) - (PORT datac (90:90:90) (112:112:112)) - (PORT datad (505:505:505) (591:591:591)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (309:309:309) (359:359:359)) - (PORT datab (475:475:475) (554:554:554)) - (PORT datac (449:449:449) (536:536:536)) - (PORT datad (442:442:442) (526:526:526)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~13) - (DELAY - (ABSOLUTE - (PORT dataa (346:346:346) (406:406:406)) - (PORT datab (127:127:127) (160:160:160)) - (PORT datac (739:739:739) (871:871:871)) - (PORT datad (1224:1224:1224) (1419:1419:1419)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1024:1024:1024) (1204:1204:1204)) - (PORT datab (900:900:900) (1065:1065:1065)) - (PORT datac (729:729:729) (864:864:864)) - (PORT datad (1439:1439:1439) (1664:1664:1664)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~11) - (DELAY - (ABSOLUTE - (PORT dataa (712:712:712) (825:825:825)) - (PORT datab (461:461:461) (536:536:536)) - (PORT datac (91:91:91) (113:113:113)) - (PORT datad (313:313:313) (365:365:365)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~9) - (DELAY - (ABSOLUTE - (PORT dataa (822:822:822) (958:958:958)) - (PORT datab (143:143:143) (176:176:176)) - (PORT datac (676:676:676) (784:784:784)) - (PORT datad (447:447:447) (511:511:511)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal62\~2) - (DELAY - (ABSOLUTE - (PORT dataa (486:486:486) (573:573:573)) - (PORT datab (480:480:480) (559:559:559)) - (PORT datac (464:464:464) (541:541:541)) - (PORT datad (488:488:488) (587:587:587)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (465:465:465) (554:554:554)) - (PORT datab (510:510:510) (610:610:610)) - (PORT datac (102:102:102) (128:128:128)) - (PORT datad (653:653:653) (748:748:748)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (798:798:798) (920:920:920)) - (PORT datab (842:842:842) (981:981:981)) - (PORT datac (610:610:610) (703:703:703)) - (PORT datad (212:212:212) (252:252:252)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal64\~0) - (DELAY - (ABSOLUTE - (PORT dataa (483:483:483) (570:570:570)) - (PORT datab (482:482:482) (561:561:561)) - (PORT datac (467:467:467) (545:545:545)) - (PORT datad (490:490:490) (589:589:589)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel\[0\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (398:398:398) (489:489:489)) - (PORT datab (437:437:437) (539:539:539)) - (PORT datad (641:641:641) (743:743:743)) - (IOPATH dataa combout (166:166:166) (159:159:159)) - (IOPATH datab combout (167:167:167) (158:158:158)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (316:316:316) (369:369:369)) - (PORT datab (640:640:640) (739:739:739)) - (PORT datac (472:472:472) (550:550:550)) - (PORT datad (504:504:504) (582:582:582)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~15) - (DELAY - (ABSOLUTE - (PORT dataa (821:821:821) (958:958:958)) - (PORT datab (461:461:461) (536:536:536)) - (PORT datac (714:714:714) (822:822:822)) - (PORT datad (879:879:879) (1038:1038:1038)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla89M1T2_3) - (DELAY - (ABSOLUTE - (PORT dataa (849:849:849) (998:998:998)) - (PORT datab (789:789:789) (902:902:902)) - (PORT datac (816:816:816) (958:958:958)) - (PORT datad (214:214:214) (254:254:254)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (564:564:564) (655:655:655)) - (PORT datac (425:425:425) (486:486:486)) - (PORT datad (548:548:548) (625:625:625)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (102:102:102) (132:132:132)) - (PORT datab (214:214:214) (257:257:257)) - (PORT datac (547:547:547) (625:625:625)) - (PORT datad (96:96:96) (116:116:116)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (175:175:175) (212:212:212)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (320:320:320) (367:367:367)) - (PORT datad (862:862:862) (1021:1021:1021)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (687:687:687) (788:788:788)) - (PORT datab (680:680:680) (797:797:797)) - (PORT datac (492:492:492) (568:568:568)) - (PORT datad (877:877:877) (1018:1018:1018)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (459:459:459) (542:542:542)) - (PORT datab (119:119:119) (152:152:152)) - (PORT datac (654:654:654) (764:764:764)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\~20) - (DELAY - (ABSOLUTE - (PORT dataa (941:941:941) (1081:1081:1081)) - (PORT datab (921:921:921) (1072:1072:1072)) - (PORT datac (838:838:838) (987:987:987)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (523:523:523) (628:628:628)) - (PORT datab (108:108:108) (138:138:138)) - (PORT datac (666:666:666) (777:777:777)) - (PORT datad (496:496:496) (567:567:567)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~35) - (DELAY - (ABSOLUTE - (PORT datab (660:660:660) (761:761:761)) - (PORT datac (678:678:678) (804:804:804)) - (PORT datad (424:424:424) (481:481:481)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_de2\~5) - (DELAY - (ABSOLUTE - (PORT dataa (483:483:483) (580:580:580)) - (PORT datab (502:502:502) (601:601:601)) - (PORT datac (628:628:628) (727:727:727)) - (PORT datad (200:200:200) (241:241:241)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_de2\~6) - (DELAY - (ABSOLUTE - (PORT dataa (695:695:695) (823:823:823)) - (PORT datab (657:657:657) (758:758:758)) - (PORT datac (626:626:626) (725:725:725)) - (PORT datad (423:423:423) (480:480:480)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_hl\~0) - (DELAY - (ABSOLUTE - (PORT dataa (138:138:138) (190:190:190)) - (PORT datab (119:119:119) (153:153:153)) - (PORT datac (178:178:178) (212:212:212)) - (PORT datad (681:681:681) (806:806:806)) - (IOPATH dataa combout (188:188:188) (179:179:179)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|bank_hl_de2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (638:638:638) (742:742:742)) - (PORT datab (658:658:658) (758:758:758)) - (PORT datad (677:677:677) (802:802:802)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (161:161:161) (174:174:174)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_control_\|bank_hl_de2) + (INSTANCE z80_\|interrupts_\|iff1) (DELAY (ABSOLUTE - (PORT clk (915:915:915) (922:922:922)) + (PORT clk (920:920:920) (928:928:928)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (929:929:929) (911:911:911)) + (PORT clrn (648:648:648) (708:708:708)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -8517,4322 +1432,6 @@ (HOLD d (posedge clk) (84:84:84)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_hl2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (188:188:188) (231:231:231)) - (PORT datab (117:117:117) (151:151:151)) - (PORT datac (121:121:121) (164:164:164)) - (PORT datad (668:668:668) (791:791:791)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (166:166:166) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~7) - (DELAY - (ABSOLUTE - (PORT dataa (297:297:297) (339:339:339)) - (PORT datab (567:567:567) (669:669:669)) - (PORT datac (175:175:175) (209:209:209)) - (PORT datad (384:384:384) (454:454:454)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (352:352:352) (423:423:423)) - (PORT datab (975:975:975) (1126:1126:1126)) - (PORT datad (469:469:469) (536:536:536)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla30npla13M4T3_5) - (DELAY - (ABSOLUTE - (PORT dataa (1477:1477:1477) (1704:1704:1704)) - (PORT datab (970:970:970) (1139:1139:1139)) - (PORT datac (568:568:568) (656:656:656)) - (PORT datad (861:861:861) (996:996:996)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (120:120:120) (153:153:153)) - (PORT datab (464:464:464) (548:548:548)) - (PORT datac (841:841:841) (978:978:978)) - (PORT datad (687:687:687) (788:788:788)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~13) - (DELAY - (ABSOLUTE - (PORT dataa (543:543:543) (626:626:626)) - (PORT datab (106:106:106) (137:137:137)) - (PORT datac (527:527:527) (615:615:615)) - (PORT datad (111:111:111) (132:132:132)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla30npla13M5T3_5) - (DELAY - (ABSOLUTE - (PORT dataa (520:520:520) (613:613:613)) - (PORT datab (120:120:120) (154:154:154)) - (PORT datac (770:770:770) (895:895:895)) - (PORT datad (844:844:844) (974:974:974)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (637:637:637) (737:737:737)) - (PORT datab (849:849:849) (985:985:985)) - (PORT datac (329:329:329) (386:386:386)) - (PORT datad (102:102:102) (119:119:119)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (184:184:184) (224:224:224)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (89:89:89) (109:109:109)) - (PORT datad (93:93:93) (112:112:112)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (491:491:491) (573:573:573)) - (PORT datab (355:355:355) (418:418:418)) - (PORT datac (598:598:598) (686:686:686)) - (PORT datad (410:410:410) (473:473:473)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~14) - (DELAY - (ABSOLUTE - (PORT dataa (923:923:923) (1088:1088:1088)) - (PORT datab (861:861:861) (993:993:993)) - (PORT datac (978:978:978) (1128:1128:1128)) - (PORT datad (577:577:577) (656:656:656)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~50) - (DELAY - (ABSOLUTE - (PORT dataa (1164:1164:1164) (1388:1388:1388)) - (PORT datab (845:845:845) (992:992:992)) - (PORT datac (835:835:835) (979:979:979)) - (PORT datad (1090:1090:1090) (1237:1237:1237)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (503:503:503) (596:596:596)) - (PORT datab (481:481:481) (558:558:558)) - (PORT datac (472:472:472) (562:562:562)) - (PORT datad (885:885:885) (1041:1041:1041)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (339:339:339) (399:399:399)) - (PORT datab (369:369:369) (437:437:437)) - (PORT datac (514:514:514) (596:596:596)) - (PORT datad (94:94:94) (113:113:113)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (377:377:377) (447:447:447)) - (PORT datab (678:678:678) (781:781:781)) - (PORT datac (357:357:357) (421:421:421)) - (PORT datad (741:741:741) (871:871:871)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (767:767:767) (892:892:892)) - (PORT datab (350:350:350) (409:409:409)) - (PORT datac (717:717:717) (828:828:828)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla10M5T1_5\~2) - (DELAY - (ABSOLUTE - (PORT dataa (624:624:624) (755:755:755)) - (PORT datab (1014:1014:1014) (1171:1171:1171)) - (PORT datad (550:550:550) (651:651:651)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (158:158:158)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (476:476:476) (561:561:561)) - (PORT datab (376:376:376) (446:446:446)) - (PORT datac (107:107:107) (130:130:130)) - (PORT datad (1233:1233:1233) (1400:1400:1400)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~51) - (DELAY - (ABSOLUTE - (PORT dataa (687:687:687) (805:805:805)) - (PORT datab (841:841:841) (994:994:994)) - (PORT datac (668:668:668) (785:785:785)) - (PORT datad (675:675:675) (774:774:774)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (1061:1061:1061) (1218:1218:1218)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datac (500:500:500) (596:596:596)) - (PORT datad (99:99:99) (120:120:120)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (324:324:324) (375:375:375)) - (PORT datab (114:114:114) (142:142:142)) - (PORT datac (497:497:497) (568:568:568)) - (PORT datad (464:464:464) (555:555:555)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (469:469:469) (560:560:560)) - (PORT datab (107:107:107) (137:137:137)) - (PORT datac (289:289:289) (340:340:340)) - (PORT datad (344:344:344) (402:402:402)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (458:458:458) (540:540:540)) - (PORT datac (112:112:112) (139:139:139)) - (PORT datad (106:106:106) (130:130:130)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (726:726:726) (837:837:837)) - (PORT datab (324:324:324) (381:381:381)) - (PORT datac (455:455:455) (526:526:526)) - (PORT datad (318:318:318) (373:373:373)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (791:791:791) (923:923:923)) - (PORT datab (495:495:495) (579:579:579)) - (PORT datac (643:643:643) (731:731:731)) - (PORT datad (660:660:660) (773:773:773)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla6M1T4_4) - (DELAY - (ABSOLUTE - (PORT dataa (986:986:986) (1138:1138:1138)) - (PORT datab (445:445:445) (512:512:512)) - (PORT datac (1117:1117:1117) (1277:1277:1277)) - (PORT datad (1145:1145:1145) (1327:1327:1327)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~40) - (DELAY - (ABSOLUTE - (PORT dataa (514:514:514) (597:597:597)) - (PORT datab (619:619:619) (713:713:713)) - (PORT datad (103:103:103) (120:120:120)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (278:278:278) (330:330:330)) - (PORT datab (364:364:364) (430:430:430)) - (PORT datac (1103:1103:1103) (1260:1260:1260)) - (PORT datad (281:281:281) (320:320:320)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (133:133:133)) - (PORT datab (498:498:498) (594:594:594)) - (PORT datac (94:94:94) (117:117:117)) - (PORT datad (103:103:103) (121:121:121)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~38) - (DELAY - (ABSOLUTE - (PORT dataa (105:105:105) (137:137:137)) - (PORT datab (465:465:465) (539:539:539)) - (PORT datac (299:299:299) (348:348:348)) - (PORT datad (96:96:96) (116:116:116)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~93) - (DELAY - (ABSOLUTE - (PORT dataa (665:665:665) (774:774:774)) - (PORT datab (555:555:555) (630:630:630)) - (PORT datac (642:642:642) (731:731:731)) - (PORT datad (735:735:735) (845:845:845)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_de\~0) - (DELAY - (ABSOLUTE - (PORT dataa (133:133:133) (185:185:185)) - (PORT datab (117:117:117) (150:150:150)) - (PORT datac (173:173:173) (207:207:207)) - (PORT datad (668:668:668) (792:792:792)) - (IOPATH dataa combout (188:188:188) (184:184:184)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_50) - (DELAY - (ABSOLUTE - (PORT datab (758:758:758) (873:873:873)) - (PORT datac (634:634:634) (722:722:722)) - (PORT datad (325:325:325) (377:377:377)) - (IOPATH datab combout (166:166:166) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_70\~2) - (DELAY - (ABSOLUTE - (PORT datac (504:504:504) (580:580:580)) - (PORT datad (733:733:733) (840:840:840)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_66\~0) - (DELAY - (ABSOLUTE - (PORT dataa (648:648:648) (758:758:758)) - (PORT datab (118:118:118) (152:152:152)) - (PORT datac (631:631:631) (727:727:727)) - (PORT datad (374:374:374) (434:434:434)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_38\~0) - (DELAY - (ABSOLUTE - (PORT dataa (391:391:391) (466:466:466)) - (PORT datab (817:817:817) (959:959:959)) - (PORT datac (634:634:634) (731:731:731)) - (PORT datad (107:107:107) (132:132:132)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_42\~0) - (DELAY - (ABSOLUTE - (PORT dataa (387:387:387) (461:461:461)) - (PORT datab (821:821:821) (964:964:964)) - (PORT datac (628:628:628) (724:724:724)) - (PORT datad (103:103:103) (128:128:128)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~9) - (DELAY - (ABSOLUTE - (PORT dataa (743:743:743) (872:872:872)) - (PORT datab (472:472:472) (548:548:548)) - (PORT datac (1037:1037:1037) (1204:1204:1204)) - (PORT datad (878:878:878) (1011:1011:1011)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~10) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (133:133:133)) - (PORT datab (107:107:107) (137:137:137)) - (PORT datad (467:467:467) (543:543:543)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~19) - (DELAY - (ABSOLUTE - (PORT dataa (547:547:547) (653:653:653)) - (PORT datab (349:349:349) (411:411:411)) - (PORT datac (514:514:514) (595:595:595)) - (PORT datad (833:833:833) (968:968:968)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla37pla28M2T3_4) - (DELAY - (ABSOLUTE - (PORT dataa (619:619:619) (713:713:713)) - (PORT datab (399:399:399) (482:482:482)) - (PORT datac (817:817:817) (959:959:959)) - (PORT datad (835:835:835) (972:972:972)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_lo\~8) - (DELAY - (ABSOLUTE - (PORT dataa (310:310:310) (366:366:366)) - (PORT datab (106:106:106) (137:137:137)) - (PORT datac (337:337:337) (397:397:397)) - (PORT datad (591:591:591) (668:668:668)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (241:241:241)) - (PORT datab (643:643:643) (746:746:746)) - (PORT datac (179:179:179) (217:217:217)) - (PORT datad (593:593:593) (677:677:677)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~4) - (DELAY - (ABSOLUTE - (PORT dataa (691:691:691) (814:814:814)) - (PORT datab (882:882:882) (1040:1040:1040)) - (PORT datac (1221:1221:1221) (1398:1398:1398)) - (PORT datad (597:597:597) (722:722:722)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~5) - (DELAY - (ABSOLUTE - (PORT dataa (521:521:521) (615:615:615)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datac (686:686:686) (808:808:808)) - (PORT datad (103:103:103) (120:120:120)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~6) - (DELAY - (ABSOLUTE - (PORT dataa (331:331:331) (398:398:398)) - (PORT datac (352:352:352) (414:414:414)) - (PORT datad (292:292:292) (332:332:332)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_78\~0) - (DELAY - (ABSOLUTE - (PORT dataa (632:632:632) (736:736:736)) - (PORT datab (113:113:113) (146:146:146)) - (PORT datac (625:625:625) (721:721:721)) - (PORT datad (369:369:369) (429:429:429)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal21\~2) - (DELAY - (ABSOLUTE - (PORT dataa (489:489:489) (571:571:571)) - (PORT datab (486:486:486) (563:563:563)) - (PORT datac (499:499:499) (608:608:608)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|bank_af\~0) - (DELAY - (ABSOLUTE - (PORT dataa (383:383:383) (447:447:447)) - (PORT datab (643:643:643) (742:742:742)) - (PORT datad (509:509:509) (596:596:596)) - (IOPATH dataa combout (159:159:159) (173:173:173)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_control_\|bank_af) - (DELAY - (ABSOLUTE - (PORT clk (907:907:907) (911:911:911)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (918:918:918) (902:902:902)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_af\~0) - (DELAY - (ABSOLUTE - (PORT dataa (633:633:633) (736:736:736)) - (PORT datab (133:133:133) (182:182:182)) - (PORT datac (634:634:634) (730:730:730)) - (PORT datad (376:376:376) (436:436:436)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_34) - (DELAY - (ABSOLUTE - (PORT dataa (364:364:364) (432:432:432)) - (PORT datab (745:745:745) (856:856:856)) - (PORT datad (516:516:516) (594:594:594)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_af2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (632:632:632) (736:736:736)) - (PORT datab (134:134:134) (183:183:183)) - (PORT datac (627:627:627) (723:723:723)) - (PORT datad (371:371:371) (431:431:431)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_30) - (DELAY - (ABSOLUTE - (PORT dataa (971:971:971) (1123:1123:1123)) - (PORT datab (648:648:648) (745:745:745)) - (PORT datad (431:431:431) (486:486:486)) - (IOPATH dataa combout (166:166:166) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~12) - (DELAY - (ABSOLUTE - (PORT dataa (373:373:373) (455:455:455)) - (PORT datab (502:502:502) (588:588:588)) - (PORT datac (1028:1028:1028) (1200:1200:1200)) - (PORT datad (612:612:612) (705:705:705)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~4) - (DELAY - (ABSOLUTE - (PORT dataa (830:830:830) (978:978:978)) - (PORT datac (587:587:587) (665:665:665)) - (PORT datad (166:166:166) (198:198:198)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~6) - (DELAY - (ABSOLUTE - (PORT dataa (784:784:784) (904:904:904)) - (PORT datab (654:654:654) (760:760:760)) - (PORT datac (1151:1151:1151) (1341:1341:1341)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~7) - (DELAY - (ABSOLUTE - (PORT dataa (648:648:648) (747:747:747)) - (PORT datab (1147:1147:1147) (1325:1325:1325)) - (PORT datac (527:527:527) (620:620:620)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~24) - (DELAY - (ABSOLUTE - (PORT dataa (484:484:484) (575:575:575)) - (PORT datab (853:853:853) (990:990:990)) - (PORT datac (714:714:714) (819:819:819)) - (PORT datad (469:469:469) (539:539:539)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~13) - (DELAY - (ABSOLUTE - (PORT datab (119:119:119) (149:149:149)) - (PORT datac (106:106:106) (129:129:129)) - (PORT datad (107:107:107) (125:125:125)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (134:134:134)) - (PORT datab (914:914:914) (1068:1068:1068)) - (PORT datac (108:108:108) (134:134:134)) - (PORT datad (92:92:92) (109:109:109)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~3) - (DELAY - (ABSOLUTE - (PORT dataa (308:308:308) (364:364:364)) - (PORT datab (477:477:477) (553:553:553)) - (PORT datac (753:753:753) (873:873:873)) - (PORT datad (1084:1084:1084) (1240:1240:1240)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (117:117:117) (149:149:149)) - (PORT datab (1128:1128:1128) (1305:1305:1305)) - (PORT datac (431:431:431) (494:494:494)) - (PORT datad (102:102:102) (120:120:120)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~2) - (DELAY - (ABSOLUTE - (PORT dataa (383:383:383) (454:454:454)) - (PORT datab (808:808:808) (935:935:935)) - (PORT datac (188:188:188) (222:222:222)) - (PORT datad (640:640:640) (734:734:734)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~3) - (DELAY - (ABSOLUTE - (PORT dataa (120:120:120) (153:153:153)) - (PORT datab (293:293:293) (340:340:340)) - (PORT datac (435:435:435) (496:496:496)) - (PORT datad (315:315:315) (366:366:366)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~6) - (DELAY - (ABSOLUTE - (PORT dataa (659:659:659) (772:772:772)) - (PORT datab (310:310:310) (361:361:361)) - (PORT datac (359:359:359) (431:431:431)) - (PORT datad (462:462:462) (531:531:531)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~5) - (DELAY - (ABSOLUTE - (PORT dataa (382:382:382) (454:454:454)) - (PORT datab (649:649:649) (751:751:751)) - (PORT datac (659:659:659) (753:753:753)) - (PORT datad (314:314:314) (361:361:361)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~4) - (DELAY - (ABSOLUTE - (PORT dataa (482:482:482) (556:556:556)) - (PORT datab (677:677:677) (783:783:783)) - (PORT datac (489:489:489) (563:563:563)) - (PORT datad (354:354:354) (417:417:417)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~7) - (DELAY - (ABSOLUTE - (PORT dataa (310:310:310) (360:360:360)) - (PORT datab (104:104:104) (133:133:133)) - (PORT datac (90:90:90) (112:112:112)) - (PORT datad (89:89:89) (106:106:106)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~8) - (DELAY - (ABSOLUTE - (PORT dataa (498:498:498) (577:577:577)) - (PORT datab (676:676:676) (782:782:782)) - (PORT datac (191:191:191) (226:226:226)) - (PORT datad (639:639:639) (733:733:733)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~9) - (DELAY - (ABSOLUTE - (PORT dataa (658:658:658) (771:771:771)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (660:660:660) (754:754:754)) - (PORT datad (460:460:460) (530:530:530)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~10) - (DELAY - (ABSOLUTE - (PORT dataa (108:108:108) (141:141:141)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datac (360:360:360) (431:431:431)) - (PORT datad (467:467:467) (543:543:543)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (312:312:312) (370:370:370)) - (PORT datab (366:366:366) (434:434:434)) - (PORT datac (201:201:201) (241:241:241)) - (PORT datad (108:108:108) (128:128:128)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (102:102:102) (133:133:133)) - (PORT datab (322:322:322) (373:373:373)) - (PORT datac (272:272:272) (312:312:312)) - (PORT datad (473:473:473) (544:544:544)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~29) - (DELAY - (ABSOLUTE - (PORT dataa (510:510:510) (595:595:595)) - (PORT datab (880:880:880) (1044:1044:1044)) - (PORT datac (767:767:767) (891:891:891)) - (PORT datad (106:106:106) (129:129:129)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~13) - (DELAY - (ABSOLUTE - (PORT dataa (331:331:331) (385:385:385)) - (PORT datab (535:535:535) (642:642:642)) - (PORT datac (970:970:970) (1136:1136:1136)) - (PORT datad (626:626:626) (726:726:726)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~49) - (DELAY - (ABSOLUTE - (PORT dataa (619:619:619) (712:712:712)) - (PORT datab (832:832:832) (978:978:978)) - (PORT datac (904:904:904) (1039:1039:1039)) - (PORT datad (643:643:643) (748:748:748)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (763:763:763) (875:875:875)) - (PORT datab (693:693:693) (802:802:802)) - (PORT datac (688:688:688) (789:789:789)) - (PORT datad (713:713:713) (830:830:830)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (619:619:619) (717:717:717)) - (PORT datac (326:326:326) (385:385:385)) - (PORT datad (89:89:89) (107:107:107)) - (IOPATH dataa combout (165:165:165) (163:163:163)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~28) - (DELAY - (ABSOLUTE - (PORT dataa (126:126:126) (161:161:161)) - (PORT datab (114:114:114) (142:142:142)) - (PORT datac (623:623:623) (726:726:726)) - (PORT datad (102:102:102) (119:119:119)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~35) - (DELAY - (ABSOLUTE - (PORT datab (1124:1124:1124) (1293:1293:1293)) - (PORT datac (736:736:736) (840:840:840)) - (PORT datad (461:461:461) (530:530:530)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~36) - (DELAY - (ABSOLUTE - (PORT dataa (113:113:113) (147:147:147)) - (PORT datab (490:490:490) (568:568:568)) - (PORT datac (331:331:331) (391:391:391)) - (PORT datad (516:516:516) (598:598:598)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~5) - (DELAY - (ABSOLUTE - (PORT dataa (837:837:837) (973:973:973)) - (PORT datab (646:646:646) (742:742:742)) - (PORT datac (620:620:620) (707:707:707)) - (PORT datad (288:288:288) (330:330:330)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~31) - (DELAY - (ABSOLUTE - (PORT dataa (328:328:328) (392:392:392)) - (PORT datab (123:123:123) (154:154:154)) - (PORT datac (619:619:619) (716:716:716)) - (PORT datad (104:104:104) (121:121:121)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~29) - (DELAY - (ABSOLUTE - (PORT dataa (918:918:918) (1082:1082:1082)) - (PORT datab (563:563:563) (663:663:663)) - (PORT datac (574:574:574) (685:685:685)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~1) - (DELAY - (ABSOLUTE - (PORT dataa (645:645:645) (756:756:756)) - (PORT datab (861:861:861) (1015:1015:1015)) - (PORT datad (106:106:106) (124:124:124)) - (IOPATH dataa combout (166:166:166) (159:159:159)) - (IOPATH datab combout (167:167:167) (158:158:158)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (481:481:481) (562:562:562)) - (PORT datab (304:304:304) (350:350:350)) - (PORT datac (309:309:309) (367:367:367)) - (PORT datad (316:316:316) (362:362:362)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal33\~3) - (DELAY - (ABSOLUTE - (PORT dataa (671:671:671) (795:795:795)) - (PORT datab (730:730:730) (859:859:859)) - (PORT datac (626:626:626) (729:729:729)) - (PORT datad (399:399:399) (481:481:481)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~0) - (DELAY - (ABSOLUTE - (PORT dataa (376:376:376) (448:448:448)) - (PORT datab (713:713:713) (821:821:821)) - (PORT datac (662:662:662) (773:773:773)) - (PORT datad (928:928:928) (1065:1065:1065)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (585:585:585) (692:692:692)) - (PORT datab (490:490:490) (570:570:570)) - (PORT datac (88:88:88) (109:109:109)) - (PORT datad (119:119:119) (137:137:137)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we_lo\~2) - (DELAY - (ABSOLUTE - (PORT dataa (581:581:581) (703:703:703)) - (PORT datac (1206:1206:1206) (1387:1387:1387)) - (PORT datad (371:371:371) (437:437:437)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we_lo\~3) - (DELAY - (ABSOLUTE - (PORT dataa (400:400:400) (473:473:473)) - (PORT datab (615:615:615) (712:712:712)) - (PORT datac (89:89:89) (109:109:109)) - (PORT datad (620:620:620) (713:713:713)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we_lo\~4) - (DELAY - (ABSOLUTE - (PORT dataa (566:566:566) (672:672:672)) - (PORT datab (349:349:349) (415:415:415)) - (PORT datac (559:559:559) (671:671:671)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo) - (DELAY - (ABSOLUTE - (PORT dataa (108:108:108) (141:141:141)) - (PORT datab (104:104:104) (133:133:133)) - (PORT datac (94:94:94) (118:118:118)) - (PORT datad (515:515:515) (599:599:599)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_ir\~0) - (DELAY - (ABSOLUTE - (PORT datab (152:152:152) (203:203:203)) - (PORT datac (130:130:130) (173:173:173)) - (PORT datad (135:135:135) (175:175:175)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_ir\~1) - (DELAY - (ABSOLUTE - (PORT dataa (522:522:522) (612:612:612)) - (PORT datab (114:114:114) (142:142:142)) - (PORT datac (605:605:605) (688:688:688)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~9) - (DELAY - (ABSOLUTE - (PORT dataa (624:624:624) (755:755:755)) - (PORT datab (114:114:114) (142:142:142)) - (PORT datac (368:368:368) (439:439:439)) - (PORT datad (550:550:550) (651:651:651)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (1417:1417:1417) (1651:1651:1651)) - (PORT datab (891:891:891) (1048:1048:1048)) - (PORT datac (102:102:102) (124:124:124)) - (PORT datad (117:117:117) (141:141:141)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (579:579:579) (682:682:682)) - (PORT datab (106:106:106) (136:136:136)) - (PORT datac (481:481:481) (555:555:555)) - (PORT datad (452:452:452) (517:517:517)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_ixy_dT5_7) - (DELAY - (ABSOLUTE - (PORT datab (512:512:512) (597:597:597)) - (PORT datad (334:334:334) (397:397:397)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~4) - (DELAY - (ABSOLUTE - (PORT dataa (346:346:346) (412:412:412)) - (PORT datab (516:516:516) (605:605:605)) - (PORT datac (600:600:600) (684:684:684)) - (PORT datad (105:105:105) (124:124:124)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~4) - (DELAY - (ABSOLUTE - (PORT dataa (491:491:491) (577:577:577)) - (PORT datab (490:490:490) (573:573:573)) - (PORT datac (345:345:345) (403:403:403)) - (PORT datad (480:480:480) (557:557:557)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla56M3T3_6) - (DELAY - (ABSOLUTE - (PORT dataa (1138:1138:1138) (1322:1322:1322)) - (PORT datab (506:506:506) (590:590:590)) - (PORT datac (117:117:117) (145:145:145)) - (PORT datad (619:619:619) (717:717:717)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~5) - (DELAY - (ABSOLUTE - (PORT dataa (513:513:513) (593:593:593)) - (PORT datab (498:498:498) (586:586:586)) - (PORT datac (476:476:476) (560:560:560)) - (PORT datad (326:326:326) (381:381:381)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~6) - (DELAY - (ABSOLUTE - (PORT dataa (492:492:492) (585:585:585)) - (PORT datad (95:95:95) (114:114:114)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~7) - (DELAY - (ABSOLUTE - (PORT dataa (582:582:582) (673:673:673)) - (PORT datab (494:494:494) (579:579:579)) - (PORT datac (340:340:340) (402:402:402)) - (PORT datad (481:481:481) (557:557:557)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1373:1373:1373) (1595:1595:1595)) - (PORT datab (1019:1019:1019) (1196:1196:1196)) - (PORT datac (581:581:581) (652:652:652)) - (PORT datad (902:902:902) (1065:1065:1065)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~11) - (DELAY - (ABSOLUTE - (PORT dataa (446:446:446) (511:511:511)) - (PORT datab (476:476:476) (564:564:564)) - (PORT datac (443:443:443) (521:521:521)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1375:1375:1375) (1597:1597:1597)) - (PORT datab (1373:1373:1373) (1593:1593:1593)) - (PORT datac (780:780:780) (900:900:900)) - (PORT datad (901:901:901) (1063:1063:1063)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~12) - (DELAY - (ABSOLUTE - (PORT dataa (105:105:105) (136:136:136)) - (PORT datab (121:121:121) (151:151:151)) - (PORT datac (109:109:109) (133:133:133)) - (PORT datad (91:91:91) (108:108:108)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~13) - (DELAY - (ABSOLUTE - (PORT dataa (718:718:718) (827:827:827)) - (PORT datab (104:104:104) (133:133:133)) - (PORT datac (436:436:436) (498:498:498)) - (PORT datad (475:475:475) (552:552:552)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (473:473:473) (549:549:549)) - (PORT datab (126:126:126) (158:158:158)) - (PORT datac (347:347:347) (409:409:409)) - (PORT datad (752:752:752) (857:857:857)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~38) - (DELAY - (ABSOLUTE - (PORT dataa (690:690:690) (814:814:814)) - (PORT datab (773:773:773) (932:932:932)) - (PORT datac (486:486:486) (570:570:570)) - (PORT datad (444:444:444) (510:510:510)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1145:1145:1145) (1330:1330:1330)) - (PORT datab (1472:1472:1472) (1749:1749:1749)) - (PORT datac (1647:1647:1647) (1903:1903:1903)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~24) - (DELAY - (ABSOLUTE - (PORT datab (458:458:458) (537:537:537)) - (PORT datac (551:551:551) (649:649:649)) - (PORT datad (778:778:778) (883:883:883)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (114:114:114) (150:150:150)) - (PORT datac (354:354:354) (417:417:417)) - (PORT datad (595:595:595) (705:705:705)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~4) - (DELAY - (ABSOLUTE - (PORT dataa (754:754:754) (904:904:904)) - (PORT datac (642:642:642) (743:743:743)) - (PORT datad (1138:1138:1138) (1332:1332:1332)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (609:609:609) (697:697:697)) - (PORT datab (117:117:117) (147:147:147)) - (PORT datac (321:321:321) (376:376:376)) - (PORT datad (646:646:646) (746:746:746)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~9) - (DELAY - (ABSOLUTE - (PORT dataa (647:647:647) (780:780:780)) - (PORT datac (631:631:631) (719:719:719)) - (PORT datad (529:529:529) (623:623:623)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3) - (DELAY - (ABSOLUTE - (PORT datab (1181:1181:1181) (1364:1364:1364)) - (PORT datac (512:512:512) (606:606:606)) - (PORT datad (1094:1094:1094) (1273:1273:1273)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (656:656:656) (766:766:766)) - (PORT datab (306:306:306) (356:356:356)) - (PORT datac (495:495:495) (571:571:571)) - (PORT datad (625:625:625) (719:719:719)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (619:619:619) (717:717:717)) - (PORT datab (303:303:303) (352:352:352)) - (PORT datac (624:624:624) (716:716:716)) - (PORT datad (468:468:468) (543:543:543)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1011:1011:1011) (1173:1173:1173)) - (PORT datab (882:882:882) (1025:1025:1025)) - (PORT datad (553:553:553) (642:642:642)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (158:158:158)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (502:502:502) (586:586:586)) - (PORT datab (643:643:643) (754:754:754)) - (PORT datac (834:834:834) (971:971:971)) - (PORT datad (609:609:609) (698:698:698)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (378:378:378) (441:441:441)) - (PORT datab (491:491:491) (569:569:569)) - (PORT datac (328:328:328) (388:388:388)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (133:133:133)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datac (857:857:857) (971:971:971)) - (PORT datad (89:89:89) (107:107:107)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (502:502:502) (586:586:586)) - (PORT datab (505:505:505) (595:595:595)) - (PORT datac (97:97:97) (123:123:123)) - (PORT datad (476:476:476) (545:545:545)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (102:102:102) (133:133:133)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (976:976:976) (1116:1116:1116)) - (PORT datad (173:173:173) (202:202:202)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (651:651:651) (750:750:750)) - (PORT datab (436:436:436) (510:510:510)) - (PORT datac (453:453:453) (529:529:529)) - (PORT datad (92:92:92) (111:111:111)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~18) - (DELAY - (ABSOLUTE - (PORT dataa (867:867:867) (1021:1021:1021)) - (PORT datab (977:977:977) (1131:1131:1131)) - (PORT datac (1461:1461:1461) (1688:1688:1688)) - (PORT datad (636:636:636) (733:733:733)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (1480:1480:1480) (1707:1707:1707)) - (PORT datab (909:909:909) (1072:1072:1072)) - (PORT datac (343:343:343) (393:393:393)) - (PORT datad (108:108:108) (128:128:128)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (311:311:311) (362:362:362)) - (PORT datab (354:354:354) (417:417:417)) - (PORT datac (357:357:357) (412:412:412)) - (PORT datad (484:484:484) (555:555:555)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_62) - (DELAY - (ABSOLUTE - (PORT datab (377:377:377) (446:446:446)) - (PORT datac (568:568:568) (654:654:654)) - (PORT datad (503:503:503) (584:584:584)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~38) - (DELAY - (ABSOLUTE - (PORT dataa (186:186:186) (231:231:231)) - (PORT datab (610:610:610) (698:698:698)) - (PORT datac (569:569:569) (645:645:645)) - (PORT datad (455:455:455) (523:523:523)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~39) - (DELAY - (ABSOLUTE - (PORT dataa (966:966:966) (1113:1113:1113)) - (PORT datab (482:482:482) (562:562:562)) - (PORT datac (866:866:866) (1010:1010:1010)) - (PORT datad (630:630:630) (738:738:738)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~30) - (DELAY - (ABSOLUTE - (PORT dataa (621:621:621) (716:716:716)) - (PORT datab (911:911:911) (1046:1046:1046)) - (PORT datac (623:623:623) (725:725:725)) - (PORT datad (114:114:114) (137:137:137)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~45) - (DELAY - (ABSOLUTE - (PORT dataa (364:364:364) (423:423:423)) - (PORT datab (628:628:628) (731:731:731)) - (PORT datac (641:641:641) (735:735:735)) - (PORT datad (539:539:539) (628:628:628)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~1) - (DELAY - (ABSOLUTE - (PORT dataa (159:159:159) (204:204:204)) - (PORT datac (940:940:940) (1084:1084:1084)) - (PORT datad (238:238:238) (284:284:284)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~36) - (DELAY - (ABSOLUTE - (PORT dataa (359:359:359) (422:422:422)) - (PORT datab (636:636:636) (742:742:742)) - (PORT datac (850:850:850) (970:970:970)) - (PORT datad (715:715:715) (832:832:832)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~27) - (DELAY - (ABSOLUTE - (PORT dataa (784:784:784) (914:914:914)) - (PORT datab (496:496:496) (583:583:583)) - (PORT datac (475:475:475) (562:562:562)) - (PORT datad (530:530:530) (618:618:618)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~28) - (DELAY - (ABSOLUTE - (PORT dataa (471:471:471) (546:546:546)) - (PORT datac (568:568:568) (667:667:667)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~37) - (DELAY - (ABSOLUTE - (PORT dataa (593:593:593) (713:713:713)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datac (593:593:593) (674:674:674)) - (PORT datad (93:93:93) (113:113:113)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~40) - (DELAY - (ABSOLUTE - (PORT dataa (177:177:177) (214:214:214)) - (PORT datab (101:101:101) (130:130:130)) - (PORT datac (182:182:182) (222:222:222)) - (PORT datad (467:467:467) (538:538:538)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~35) - (DELAY - (ABSOLUTE - (PORT dataa (755:755:755) (871:871:871)) - (PORT datab (439:439:439) (502:502:502)) - (PORT datac (946:946:946) (1093:1093:1093)) - (PORT datad (508:508:508) (588:588:588)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~77) - (DELAY - (ABSOLUTE - (PORT dataa (604:604:604) (693:693:693)) - (PORT datab (347:347:347) (408:408:408)) - (PORT datac (462:462:462) (532:532:532)) - (PORT datad (481:481:481) (559:559:559)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~32) - (DELAY - (ABSOLUTE - (PORT dataa (120:120:120) (153:153:153)) - (PORT datab (345:345:345) (407:407:407)) - (PORT datac (773:773:773) (892:892:892)) - (PORT datad (627:627:627) (723:723:723)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla91pla21M4T2_3\~2) - (DELAY - (ABSOLUTE - (PORT dataa (920:920:920) (1084:1084:1084)) - (PORT datab (563:563:563) (663:663:663)) - (PORT datac (1072:1072:1072) (1218:1218:1218)) - (PORT datad (906:906:906) (1050:1050:1050)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~33) - (DELAY - (ABSOLUTE - (PORT dataa (115:115:115) (146:146:146)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datac (88:88:88) (109:109:109)) - (PORT datad (364:364:364) (431:431:431)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~34) - (DELAY - (ABSOLUTE - (PORT dataa (117:117:117) (154:154:154)) - (PORT datab (342:342:342) (402:402:402)) - (PORT datac (106:106:106) (128:128:128)) - (PORT datad (657:657:657) (748:748:748)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~41) - (DELAY - (ABSOLUTE - (PORT dataa (102:102:102) (133:133:133)) - (PORT datab (580:580:580) (687:687:687)) - (PORT datac (91:91:91) (113:113:113)) - (PORT datad (331:331:331) (385:385:385)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~10) - (DELAY - (ABSOLUTE - (PORT dataa (509:509:509) (599:599:599)) - (PORT datab (622:622:622) (721:721:721)) - (PORT datac (480:480:480) (563:563:563)) - (PORT datad (634:634:634) (736:736:736)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~11) - (DELAY - (ABSOLUTE - (PORT datab (114:114:114) (141:141:141)) - (PORT datac (335:335:335) (393:393:393)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~3) - (DELAY - (ABSOLUTE - (PORT dataa (111:111:111) (147:147:147)) - (PORT datac (286:286:286) (335:335:335)) - (PORT datad (478:478:478) (567:567:567)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~4) - (DELAY - (ABSOLUTE - (PORT dataa (745:745:745) (873:873:873)) - (PORT datab (362:362:362) (420:420:420)) - (PORT datac (104:104:104) (125:125:125)) - (PORT datad (634:634:634) (743:743:743)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~2) - (DELAY - (ABSOLUTE - (PORT dataa (290:290:290) (338:338:338)) - (PORT datac (450:450:450) (537:537:537)) - (PORT datad (442:442:442) (526:526:526)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~5) - (DELAY - (ABSOLUTE - (PORT dataa (495:495:495) (570:570:570)) - (PORT datab (363:363:363) (428:428:428)) - (PORT datac (196:196:196) (235:235:235)) - (PORT datad (335:335:335) (388:388:388)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~45) - (DELAY - (ABSOLUTE - (PORT dataa (347:347:347) (416:416:416)) - (PORT datab (456:456:456) (527:527:527)) - (PORT datac (482:482:482) (553:553:553)) - (PORT datad (351:351:351) (418:418:418)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~46) - (DELAY - (ABSOLUTE - (PORT datab (438:438:438) (503:503:503)) - (PORT datac (105:105:105) (127:127:127)) - (PORT datad (821:821:821) (939:939:939)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~1) - (DELAY - (ABSOLUTE - (PORT dataa (311:311:311) (357:357:357)) - (PORT datab (496:496:496) (585:585:585)) - (PORT datac (306:306:306) (346:346:346)) - (PORT datad (311:311:311) (363:363:363)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~0) - (DELAY - (ABSOLUTE - (PORT dataa (524:524:524) (599:599:599)) - (PORT datab (904:904:904) (1066:1066:1066)) - (PORT datac (466:466:466) (536:536:536)) - (PORT datad (198:198:198) (231:231:231)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~6) - (DELAY - (ABSOLUTE - (PORT dataa (107:107:107) (139:139:139)) - (PORT datab (177:177:177) (214:214:214)) - (PORT datac (114:114:114) (140:140:140)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~4) - (DELAY - (ABSOLUTE - (PORT dataa (502:502:502) (586:586:586)) - (PORT datac (488:488:488) (572:572:572)) - (PORT datad (442:442:442) (507:507:507)) - (IOPATH dataa combout (165:165:165) (163:163:163)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~16) - (DELAY - (ABSOLUTE - (PORT dataa (344:344:344) (411:411:411)) - (PORT datab (835:835:835) (969:969:969)) - (PORT datac (450:450:450) (512:512:512)) - (PORT datad (458:458:458) (527:527:527)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~14) - (DELAY - (ABSOLUTE - (PORT dataa (245:245:245) (295:295:295)) - (PORT datab (520:520:520) (602:602:602)) - (PORT datac (201:201:201) (234:234:234)) - (PORT datad (1100:1100:1100) (1292:1292:1292)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~20) - (DELAY - (ABSOLUTE - (PORT dataa (1449:1449:1449) (1724:1724:1724)) - (PORT datab (289:289:289) (333:333:333)) - (PORT datac (486:486:486) (560:560:560)) - (PORT datad (633:633:633) (727:727:727)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~15) - (DELAY - (ABSOLUTE - (PORT dataa (348:348:348) (419:419:419)) - (PORT datab (306:306:306) (354:354:354)) - (PORT datac (444:444:444) (524:524:524)) - (PORT datad (108:108:108) (126:126:126)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~17) - (DELAY - (ABSOLUTE - (PORT dataa (308:308:308) (363:363:363)) - (PORT datab (477:477:477) (554:554:554)) - (PORT datac (1115:1115:1115) (1290:1290:1290)) - (PORT datad (318:318:318) (364:364:364)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~18) - (DELAY - (ABSOLUTE - (PORT dataa (626:626:626) (715:715:715)) - (PORT datab (900:900:900) (1058:1058:1058)) - (PORT datac (353:353:353) (417:417:417)) - (PORT datad (336:336:336) (386:386:386)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~19) - (DELAY - (ABSOLUTE - (PORT dataa (481:481:481) (561:561:561)) - (PORT datab (298:298:298) (343:343:343)) - (PORT datac (338:338:338) (390:390:390)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_pc\~3) - (DELAY - (ABSOLUTE - (PORT dataa (346:346:346) (413:413:413)) - (PORT datab (515:515:515) (604:604:604)) - (PORT datac (273:273:273) (312:312:312)) - (PORT datad (477:477:477) (558:558:558)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_pc) - (DELAY - (ABSOLUTE - (PORT dataa (121:121:121) (153:153:153)) - (PORT datab (351:351:351) (414:414:414)) - (PORT datac (452:452:452) (520:520:520)) - (PORT datad (175:175:175) (207:207:207)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_74) - (DELAY - (ABSOLUTE - (PORT datab (803:803:803) (941:941:941)) - (PORT datac (498:498:498) (577:577:577)) - (PORT datad (435:435:435) (504:504:504)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (121:121:121) (154:154:154)) - (PORT datab (714:714:714) (816:816:816)) - (PORT datac (757:757:757) (868:868:868)) - (PORT datad (162:162:162) (189:189:189)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_75) - (DELAY - (ABSOLUTE - (PORT datab (518:518:518) (608:608:608)) - (PORT datac (803:803:803) (934:934:934)) - (PORT datad (358:358:358) (423:423:423)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (529:529:529) (593:593:593)) - (PORT ena (636:636:636) (682:682:682)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (1037:1037:1037) (1192:1192:1192)) - (PORT datab (385:385:385) (456:456:456)) - (PORT datad (662:662:662) (772:772:772)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_63) - (DELAY - (ABSOLUTE - (PORT datab (377:377:377) (447:447:447)) - (PORT datac (570:570:570) (655:655:655)) - (PORT datad (503:503:503) (584:584:584)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (920:920:920) (927:927:927)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (679:679:679) (746:746:746)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~23) - (DELAY - (ABSOLUTE - (PORT datab (404:404:404) (479:479:479)) - (PORT datac (339:339:339) (398:398:398)) - (PORT datad (118:118:118) (155:155:155)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_10\~0) - (DELAY - (ABSOLUTE - (PORT datac (1107:1107:1107) (1285:1285:1285)) - (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_10) - (DELAY - (ABSOLUTE - (PORT clk (932:932:932) (916:916:916)) - (PORT d (37:37:37) (50:50:50)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_9) - (DELAY - (ABSOLUTE - (PORT clk (932:932:932) (916:916:916)) - (PORT asdata (300:300:300) (342:342:342)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|resets_\|DFFE_intr_ff3) - (DELAY - (ABSOLUTE - (PORT clk (932:932:932) (916:916:916)) - (PORT asdata (301:301:301) (343:343:343)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_io_ibuf") - (INSTANCE KEY\[0\]\~input) - (DELAY - (ABSOLUTE - (IOPATH i o (153:153:153) (705:705:705)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE reset) - (DELAY - (ABSOLUTE - (PORT datac (981:981:981) (856:856:856)) - (PORT datad (284:284:284) (306:306:306)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|resets_\|x1\~0) - (DELAY - (ABSOLUTE - (PORT datad (827:827:827) (963:963:963)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|fpga_reset) - (DELAY - (ABSOLUTE - (PORT clk (914:914:914) (919:919:919)) - (PORT d (37:37:37) (50:50:50)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_clkctrl") - (INSTANCE z80_\|fpga_reset\~clkctrl) - (DELAY - (ABSOLUTE - (PORT inclk[0] (391:391:391) (424:424:424)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|resets_\|x1) - (DELAY - (ABSOLUTE - (PORT clk (912:912:912) (899:899:899)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (1092:1092:1092) (1064:1064:1064)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|resets_\|clrpc_int\~0) - (DELAY - (ABSOLUTE - (PORT dataa (341:341:341) (418:418:418)) - (PORT datab (321:321:321) (386:386:386)) - (PORT datad (642:642:642) (749:749:749)) - (IOPATH dataa combout (181:181:181) (193:193:193)) - (IOPATH datab combout (191:191:191) (188:188:188)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|resets_\|clrpc_int) - (DELAY - (ABSOLUTE - (PORT clk (932:932:932) (916:916:916)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (928:928:928) (909:909:909)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|resets_\|clrpc\~0) - (DELAY - (ABSOLUTE - (PORT dataa (134:134:134) (187:187:187)) - (PORT datab (138:138:138) (189:189:189)) - (PORT datad (117:117:117) (154:154:154)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[7\]) - (DELAY - (ABSOLUTE - (PORT datac (362:362:362) (425:425:425)) - (PORT datad (330:330:330) (387:387:387)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_apin_mux\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1449:1449:1449) (1725:1725:1725)) - (PORT datac (486:486:486) (561:561:561)) - (PORT datad (1109:1109:1109) (1285:1285:1285)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (188:188:188) (224:224:224)) - (PORT datab (294:294:294) (338:338:338)) - (PORT datac (468:468:468) (539:539:539)) - (PORT datad (632:632:632) (726:726:726)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~7) - (DELAY - (ABSOLUTE - (PORT dataa (603:603:603) (701:701:701)) - (PORT datab (633:633:633) (735:735:735)) - (PORT datac (425:425:425) (483:483:483)) - (PORT datad (341:341:341) (396:396:396)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (549:549:549) (652:652:652)) - (PORT datab (908:908:908) (1030:1030:1030)) - (PORT datac (91:91:91) (113:113:113)) - (PORT datad (638:638:638) (733:733:733)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~10) - (DELAY - (ABSOLUTE - (PORT dataa (671:671:671) (796:796:796)) - (PORT datab (556:556:556) (665:665:665)) - (PORT datac (373:373:373) (440:440:440)) - (PORT datad (717:717:717) (834:834:834)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~9) - (DELAY - (ABSOLUTE - (PORT dataa (417:417:417) (476:476:476)) - (PORT datab (346:346:346) (408:408:408)) - (PORT datac (473:473:473) (541:541:541)) - (PORT datad (592:592:592) (693:693:693)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~10) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (135:135:135)) - (PORT datab (387:387:387) (450:450:450)) - (PORT datac (106:106:106) (129:129:129)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~11) - (DELAY - (ABSOLUTE - (PORT dataa (106:106:106) (138:138:138)) - (PORT datac (96:96:96) (120:120:120)) - (PORT datad (287:287:287) (329:329:329)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~12) - (DELAY - (ABSOLUTE - (PORT dataa (718:718:718) (827:827:827)) - (PORT datab (440:440:440) (506:506:506)) - (PORT datac (439:439:439) (501:501:501)) - (PORT datad (477:477:477) (554:554:554)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (920:920:920) (904:904:904)) - (PORT ena (1159:1159:1159) (1318:1318:1318)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~6) - (DELAY - (ABSOLUTE - (PORT dataa (209:209:209) (248:248:248)) - (PORT datab (1010:1010:1010) (1167:1167:1167)) - (PORT datac (107:107:107) (131:131:131)) - (PORT datad (358:358:358) (422:422:422)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~0) - (DELAY - (ABSOLUTE - (PORT dataa (665:665:665) (781:781:781)) - (PORT datab (1128:1128:1128) (1312:1312:1312)) - (PORT datac (739:739:739) (880:880:880)) - (PORT datad (1144:1144:1144) (1338:1338:1338)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~8) - (DELAY - (ABSOLUTE - (PORT dataa (195:195:195) (234:234:234)) - (PORT datab (114:114:114) (146:146:146)) - (PORT datac (607:607:607) (700:700:700)) - (PORT datad (666:666:666) (759:759:759)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~9) - (DELAY - (ABSOLUTE - (PORT dataa (115:115:115) (144:144:144)) - (PORT datab (957:957:957) (1115:1115:1115)) - (PORT datac (290:290:290) (329:329:329)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~10) - (DELAY - (ABSOLUTE - (PORT datab (548:548:548) (641:641:641)) - (PORT datac (607:607:607) (700:700:700)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~7) - (DELAY - (ABSOLUTE - (PORT dataa (566:566:566) (659:659:659)) - (PORT datad (620:620:620) (707:707:707)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (920:920:920) (927:927:927)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (679:679:679) (746:746:746)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_54) - (DELAY - (ABSOLUTE - (PORT datab (865:865:865) (1006:1006:1006)) - (PORT datac (667:667:667) (775:775:775)) - (PORT datad (578:578:578) (662:662:662)) - (IOPATH datab combout (166:166:166) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_58) - (DELAY - (ABSOLUTE - (PORT datab (863:863:863) (1004:1004:1004)) - (PORT datac (675:675:675) (784:784:784)) - (PORT datad (548:548:548) (645:645:645)) - (IOPATH datab combout (166:166:166) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_55) - (DELAY - (ABSOLUTE - (PORT datab (862:862:862) (1004:1004:1004)) - (PORT datac (677:677:677) (786:786:786)) - (PORT datad (577:577:577) (661:661:661)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (902:902:902) (908:908:908)) - (PORT asdata (761:761:761) (846:846:846)) - (PORT ena (915:915:915) (1002:1002:1002)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_59) - (DELAY - (ABSOLUTE - (PORT datab (866:866:866) (1008:1008:1008)) - (PORT datac (664:664:664) (771:771:771)) - (PORT datad (552:552:552) (650:650:650)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (902:902:902) (908:908:908)) - (PORT asdata (760:760:760) (845:845:845)) - (PORT ena (756:756:756) (816:816:816)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (482:482:482) (566:566:566)) - (PORT datab (545:545:545) (641:641:641)) - (PORT datad (116:116:116) (152:152:152)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_51) - (DELAY - (ABSOLUTE - (PORT datab (754:754:754) (870:870:870)) - (PORT datac (642:642:642) (731:731:731)) - (PORT datad (320:320:320) (371:371:371)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (377:377:377) (413:413:413)) - (PORT ena (419:419:419) (435:435:435)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_de2\~4) - (DELAY - (ABSOLUTE - (PORT dataa (191:191:191) (234:234:234)) - (PORT datab (117:117:117) (151:151:151)) - (PORT datac (119:119:119) (161:161:161)) - (PORT datad (676:676:676) (801:801:801)) - (IOPATH dataa combout (165:165:165) (163:163:163)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_46) - (DELAY - (ABSOLUTE - (PORT datab (650:650:650) (745:745:745)) - (PORT datac (346:346:346) (410:410:410)) - (PORT datad (739:739:739) (849:849:849)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_47) - (DELAY - (ABSOLUTE - (PORT datab (653:653:653) (749:749:749)) - (PORT datac (346:346:346) (410:410:410)) - (PORT datad (738:738:738) (848:848:848)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (375:375:375) (411:411:411)) - (PORT ena (432:432:432) (460:460:460)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (130:130:130) (181:181:181)) - (PORT datab (141:141:141) (179:179:179)) - (PORT datad (126:126:126) (150:150:150)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_71\~2) - (DELAY - (ABSOLUTE - (PORT datac (503:503:503) (580:580:580)) - (PORT datad (731:731:731) (838:838:838)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_43\~0) - (DELAY - (ABSOLUTE - (PORT dataa (388:388:388) (462:462:462)) - (PORT datab (646:646:646) (750:750:750)) - (PORT datac (104:104:104) (134:134:134)) - (PORT datad (804:804:804) (942:942:942)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (910:910:910)) - (PORT asdata (643:643:643) (714:714:714)) - (PORT ena (660:660:660) (723:723:723)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_39\~0) - (DELAY - (ABSOLUTE - (PORT dataa (386:386:386) (461:461:461)) - (PORT datab (645:645:645) (748:748:748)) - (PORT datac (105:105:105) (135:135:135)) - (PORT datad (805:805:805) (943:943:943)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (910:910:910)) - (PORT asdata (643:643:643) (714:714:714)) - (PORT ena (631:631:631) (680:680:680)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (231:231:231) (294:294:294)) - (PORT datab (130:130:130) (178:178:178)) - (PORT datad (344:344:344) (402:402:402)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_83) - (DELAY - (ABSOLUTE - (PORT dataa (340:340:340) (397:397:397)) - (PORT datab (517:517:517) (608:608:608)) - (PORT datad (358:358:358) (423:423:423)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (910:910:910) (917:917:917)) - (PORT asdata (915:915:915) (1012:1012:1012)) - (PORT ena (812:812:812) (885:885:885)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (342:342:342) (404:404:404)) - (PORT datab (766:766:766) (882:882:882)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_79\~0) - (DELAY - (ABSOLUTE - (PORT dataa (633:633:633) (737:737:737)) - (PORT datab (644:644:644) (748:748:748)) - (PORT datac (105:105:105) (135:135:135)) - (PORT datad (371:371:371) (430:430:430)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (910:910:910) (918:918:918)) - (PORT asdata (661:661:661) (736:736:736)) - (PORT ena (644:644:644) (698:698:698)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~39) - (DELAY - (ABSOLUTE - (PORT dataa (492:492:492) (581:581:581)) - (PORT datab (214:214:214) (269:269:269)) - (PORT datac (508:508:508) (591:591:591)) - (PORT datad (333:333:333) (387:387:387)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (166:166:166) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_iy\~2) - (DELAY - (ABSOLUTE - (PORT dataa (483:483:483) (580:580:580)) - (PORT datab (502:502:502) (600:600:600)) - (PORT datac (627:627:627) (726:726:726)) - (PORT datad (200:200:200) (242:242:242)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_70) - (DELAY - (ABSOLUTE - (PORT datab (527:527:527) (614:614:614)) - (PORT datac (733:733:733) (838:838:838)) - (PORT datad (497:497:497) (573:573:573)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_67\~0) - (DELAY - (ABSOLUTE - (PORT dataa (650:650:650) (761:761:761)) - (PORT datab (648:648:648) (752:752:752)) - (PORT datac (103:103:103) (132:132:132)) - (PORT datad (374:374:374) (434:434:434)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (910:910:910) (917:917:917)) - (PORT asdata (915:915:915) (1012:1012:1012)) - (PORT ena (649:649:649) (703:703:703)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_71) - (DELAY - (ABSOLUTE - (PORT dataa (972:972:972) (1102:1102:1102)) - (PORT datab (510:510:510) (597:597:597)) - (PORT datad (515:515:515) (592:592:592)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (910:910:910) (918:918:918)) - (PORT asdata (662:662:662) (738:738:738)) - (PORT ena (421:421:421) (449:449:449)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~38) - (DELAY - (ABSOLUTE - (PORT dataa (218:218:218) (264:264:264)) - (PORT datab (344:344:344) (406:406:406)) - (PORT datad (187:187:187) (230:230:230)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_31) - (DELAY - (ABSOLUTE - (PORT dataa (970:970:970) (1122:1122:1122)) - (PORT datab (650:650:650) (747:747:747)) - (PORT datad (431:431:431) (486:486:486)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (911:911:911) (918:918:918)) - (PORT asdata (762:762:762) (844:844:844)) - (PORT ena (422:422:422) (454:454:454)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (465:465:465) (528:528:528)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_35) - (DELAY - (ABSOLUTE - (PORT datab (562:562:562) (646:646:646)) - (PORT datac (491:491:491) (581:581:581)) - (PORT datad (481:481:481) (559:559:559)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (911:911:911) (918:918:918)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (669:669:669) (725:725:725)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (218:218:218) (274:274:274)) - (PORT datab (313:313:313) (371:371:371)) - (PORT datad (116:116:116) (153:153:153)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~40) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (135:135:135)) - (PORT datab (104:104:104) (133:133:133)) - (PORT datac (89:89:89) (110:110:110)) - (PORT datad (275:275:275) (313:313:313)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~41) - (DELAY - (ABSOLUTE - (PORT dataa (352:352:352) (415:415:415)) - (PORT datab (102:102:102) (131:131:131)) - (PORT datad (426:426:426) (485:485:485)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~42) - (DELAY - (ABSOLUTE - (PORT dataa (191:191:191) (228:228:228)) - (PORT datab (323:323:323) (376:376:376)) - (PORT datac (748:748:748) (865:865:865)) - (PORT datad (346:346:346) (405:405:405)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (762:762:762) (847:847:847)) - (PORT ena (636:636:636) (682:682:682)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (115:115:115) (147:147:147)) - (PORT datab (675:675:675) (791:791:791)) - (PORT datad (362:362:362) (425:425:425)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~8) - (DELAY - (ABSOLUTE - (PORT datab (368:368:368) (431:431:431)) - (PORT datac (622:622:622) (719:719:719)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (920:920:920) (927:927:927)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (679:679:679) (746:746:746)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (769:769:769) (850:850:850)) - (PORT ena (419:419:419) (435:435:435)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (769:769:769) (849:849:849)) - (PORT ena (432:432:432) (460:460:460)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (130:130:130) (181:181:181)) - (PORT datab (141:141:141) (179:179:179)) - (PORT datad (126:126:126) (151:151:151)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (902:902:902) (907:907:907)) - (PORT asdata (645:645:645) (709:709:709)) - (PORT ena (421:421:421) (441:441:441)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|db\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (650:650:650) (749:749:749)) - (PORT datab (862:862:862) (1003:1003:1003)) - (PORT datad (577:577:577) (660:660:660)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (902:902:902) (908:908:908)) - (PORT asdata (810:810:810) (910:910:910)) - (PORT ena (756:756:756) (816:816:816)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (346:346:346) (415:415:415)) - (PORT datab (610:610:610) (699:699:699)) - (PORT datad (528:528:528) (614:614:614)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (910:910:910) (918:918:918)) - (PORT asdata (648:648:648) (715:715:715)) - (PORT ena (644:644:644) (698:698:698)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (910:910:910) (918:918:918)) - (PORT asdata (649:649:649) (715:715:715)) - (PORT ena (421:421:421) (449:449:449)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (356:356:356) (427:427:427)) - (PORT datab (129:129:129) (176:176:176)) - (PORT datad (191:191:191) (225:225:225)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (910:910:910)) - (PORT asdata (809:809:809) (908:908:908)) - (PORT ena (794:794:794) (880:880:880)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (180:180:180) (214:214:214)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (910:910:910)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (660:660:660) (723:723:723)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (910:910:910)) - (PORT asdata (806:806:806) (905:905:905)) - (PORT ena (736:736:736) (793:793:793)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (224:224:224) (283:283:283)) - (PORT datab (346:346:346) (408:408:408)) - (PORT datad (436:436:436) (508:508:508)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (678:678:678) (794:794:794)) - (PORT datab (493:493:493) (580:580:580)) - (PORT datad (92:92:92) (109:109:109)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (910:910:910)) - (PORT asdata (486:486:486) (535:535:535)) - (PORT ena (631:631:631) (680:680:680)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (223:223:223) (283:283:283)) - (PORT datab (624:624:624) (718:718:718)) - (PORT datad (283:283:283) (328:328:328)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (911:911:911) (918:918:918)) - (PORT asdata (927:927:927) (1045:1045:1045)) - (PORT ena (422:422:422) (454:454:454)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (911:911:911) (918:918:918)) - (PORT asdata (927:927:927) (1045:1045:1045)) - (PORT ena (669:669:669) (725:725:725)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (277:277:277)) - (PORT datab (306:306:306) (363:363:363)) - (PORT datad (117:117:117) (153:153:153)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (329:329:329) (390:390:390)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datac (173:173:173) (208:208:208)) - (PORT datad (317:317:317) (368:368:368)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (656:656:656) (761:761:761)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (621:621:621) (707:707:707)) - (PORT datad (446:446:446) (510:510:510)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (867:867:867) (954:954:954)) - (PORT ena (636:636:636) (682:682:682)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (619:619:619) (715:715:715)) - (PORT datab (381:381:381) (451:451:451)) - (PORT datad (654:654:654) (763:763:763)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~1) - (DELAY - (ABSOLUTE - (PORT datab (131:131:131) (180:180:180)) - (PORT datac (386:386:386) (461:461:461)) - (PORT datad (455:455:455) (520:520:520)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~72) - (DELAY - (ABSOLUTE - (PORT dataa (501:501:501) (593:593:593)) - (PORT datab (516:516:516) (603:603:603)) - (PORT datac (843:843:843) (964:964:964)) - (PORT datad (375:375:375) (446:446:446)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_clkctrl") (INSTANCE ula_\|pll_\|altpll_component\|auto_generated\|wire_pll1_clk\[0\]\~clkctrl) @@ -12842,103 +1441,12 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add0\~14) - (DELAY - (ABSOLUTE - (PORT datab (773:773:773) (898:898:898)) - (IOPATH datab combout (166:166:166) (176:176:176)) - (IOPATH datab cout (227:227:227) (175:175:175)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add0\~16) - (DELAY - (ABSOLUTE - (PORT dataa (143:143:143) (194:194:194)) - (IOPATH dataa combout (186:186:186) (175:175:175)) - (IOPATH dataa cout (226:226:226) (171:171:171)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vga_hc\~2) - (DELAY - (ABSOLUTE - (PORT datac (457:457:457) (527:527:527)) - (PORT datad (91:91:91) (108:108:108)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_hc\[8\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) - (PORT d (37:37:37) (50:50:50)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add0\~18) - (DELAY - (ABSOLUTE - (PORT datad (363:363:363) (425:425:425)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vga_hc\~1) - (DELAY - (ABSOLUTE - (PORT datab (120:120:120) (149:149:149)) - (PORT datad (295:295:295) (343:343:343)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_hc\[9\]) - (DELAY - (ABSOLUTE - (PORT clk (917:917:917) (921:921:921)) - (PORT d (37:37:37) (50:50:50)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|Add0\~0) (DELAY (ABSOLUTE - (PORT datab (571:571:571) (658:658:658)) + (PORT datab (203:203:203) (263:263:263)) (IOPATH datab combout (192:192:192) (181:181:181)) (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -12950,9 +1458,9 @@ (INSTANCE ula_\|video_\|vga_hc\~3) (DELAY (ABSOLUTE - (PORT datac (457:457:457) (535:535:535)) - (PORT datad (505:505:505) (580:580:580)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT datab (177:177:177) (213:213:213)) + (PORT datad (458:458:458) (534:534:534)) + (IOPATH datab combout (167:167:167) (167:167:167)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -12962,13 +1470,13 @@ (INSTANCE ula_\|video_\|vga_hc\[0\]) (DELAY (ABSOLUTE - (PORT clk (918:918:918) (923:923:923)) - (PORT d (37:37:37) (50:50:50)) + (PORT clk (1117:1117:1117) (1146:1146:1146)) + (PORT asdata (927:927:927) (1024:1024:1024)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) ) ) (CELL @@ -12976,7 +1484,7 @@ (INSTANCE ula_\|video_\|Add0\~2) (DELAY (ABSOLUTE - (PORT datab (360:360:360) (430:430:430)) + (PORT datab (674:674:674) (793:793:793)) (IOPATH datab combout (166:166:166) (176:176:176)) (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -12985,28 +1493,18 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vga_hc\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (307:307:307) (358:358:358)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|video_\|vga_hc\[1\]) (DELAY (ABSOLUTE - (PORT clk (918:918:918) (922:922:922)) - (PORT d (37:37:37) (50:50:50)) + (PORT clk (918:918:918) (923:923:923)) + (PORT asdata (440:440:440) (473:473:473)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) ) ) (CELL @@ -13014,7 +1512,7 @@ (INSTANCE ula_\|video_\|Add0\~4) (DELAY (ABSOLUTE - (PORT datab (217:217:217) (275:275:275)) + (PORT datab (759:759:759) (883:883:883)) (IOPATH datab combout (192:192:192) (177:177:177)) (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -13028,8 +1526,8 @@ (INSTANCE ula_\|video_\|vga_hc\[2\]) (DELAY (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) - (PORT asdata (340:340:340) (367:367:367)) + (PORT clk (918:918:918) (923:923:923)) + (PORT asdata (664:664:664) (734:734:734)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -13042,37 +1540,27 @@ (INSTANCE ula_\|video_\|Add0\~6) (DELAY (ABSOLUTE - (PORT datab (366:366:366) (441:441:441)) - (IOPATH datab combout (166:166:166) (176:176:176)) - (IOPATH datab cout (227:227:227) (175:175:175)) + (PORT dataa (334:334:334) (410:410:410)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) (IOPATH cin cout (34:34:34) (34:34:34)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vga_hc\[3\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (295:295:295) (339:339:339)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|video_\|vga_hc\[3\]) (DELAY (ABSOLUTE - (PORT clk (918:918:918) (922:922:922)) - (PORT d (37:37:37) (50:50:50)) + (PORT clk (919:919:919) (923:923:923)) + (PORT asdata (448:448:448) (481:481:481)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) ) ) (CELL @@ -13080,7 +1568,7 @@ (INSTANCE ula_\|video_\|Add0\~8) (DELAY (ABSOLUTE - (PORT dataa (561:561:561) (647:647:647)) + (PORT dataa (704:704:704) (825:825:825)) (IOPATH dataa combout (186:186:186) (175:175:175)) (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -13094,8 +1582,8 @@ (INSTANCE ula_\|video_\|vga_hc\[4\]) (DELAY (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) - (PORT asdata (340:340:340) (367:367:367)) + (PORT clk (919:919:919) (923:923:923)) + (PORT asdata (267:267:267) (287:287:287)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -13103,61 +1591,14 @@ (HOLD asdata (posedge clk) (84:84:84)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Equal0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (680:680:680) (808:808:808)) - (PORT datab (530:530:530) (634:634:634)) - (PORT datac (534:534:534) (639:639:639)) - (PORT datad (156:156:156) (204:204:204)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Equal0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (350:350:350) (423:423:423)) - (PORT datab (774:774:774) (900:900:900)) - (PORT datad (508:508:508) (565:565:565)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Equal1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (236:236:236) (295:295:295)) - (PORT datab (366:366:366) (440:440:440)) - (PORT datac (343:343:343) (414:414:414)) - (PORT datad (299:299:299) (344:344:344)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|Add0\~10) (DELAY (ABSOLUTE - (PORT dataa (346:346:346) (418:418:418)) - (IOPATH dataa combout (165:165:165) (173:173:173)) - (IOPATH dataa cout (226:226:226) (171:171:171)) + (PORT datab (352:352:352) (424:424:424)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) (IOPATH cin cout (34:34:34) (34:34:34)) @@ -13169,9 +1610,9 @@ (INSTANCE ula_\|video_\|vga_hc\~0) (DELAY (ABSOLUTE - (PORT datac (460:460:460) (530:530:530)) - (PORT datad (91:91:91) (108:108:108)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT datab (286:286:286) (332:332:332)) + (PORT datad (457:457:457) (534:534:534)) + (IOPATH datab combout (167:167:167) (167:167:167)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -13181,13 +1622,13 @@ (INSTANCE ula_\|video_\|vga_hc\[5\]) (DELAY (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) - (PORT d (37:37:37) (50:50:50)) + (PORT clk (919:919:919) (923:923:923)) + (PORT asdata (431:431:431) (461:461:461)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) ) ) (CELL @@ -13195,7 +1636,7 @@ (INSTANCE ula_\|video_\|Add0\~12) (DELAY (ABSOLUTE - (PORT dataa (326:326:326) (394:394:394)) + (PORT dataa (219:219:219) (282:282:282)) (IOPATH dataa combout (186:186:186) (175:175:175)) (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -13209,8 +1650,8 @@ (INSTANCE ula_\|video_\|vga_hc\[6\]) (DELAY (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) - (PORT asdata (268:268:268) (288:288:288)) + (PORT clk (919:919:919) (923:923:923)) + (PORT asdata (338:338:338) (369:369:369)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -13218,13 +1659,27 @@ (HOLD asdata (posedge clk) (84:84:84)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add0\~14) + (DELAY + (ABSOLUTE + (PORT datab (216:216:216) (275:275:275)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|video_\|vga_hc\[7\]) (DELAY (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) - (PORT asdata (446:446:446) (483:483:483)) + (PORT clk (919:919:919) (923:923:923)) + (PORT asdata (338:338:338) (363:363:363)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -13234,36 +1689,220 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add1\~0) + (INSTANCE ula_\|video_\|Add0\~16) (DELAY (ABSOLUTE - (PORT datab (393:393:393) (474:474:474)) - (IOPATH datab combout (192:192:192) (181:181:181)) + (PORT datab (225:225:225) (287:287:287)) + (IOPATH datab combout (192:192:192) (177:177:177)) (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add1\~2) - (DELAY - (ABSOLUTE - (PORT dataa (388:388:388) (464:464:464)) - (IOPATH dataa combout (165:165:165) (173:173:173)) - (IOPATH dataa cout (226:226:226) (171:171:171)) - (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) (IOPATH cin cout (34:34:34) (34:34:34)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vga_hc\~2) + (DELAY + (ABSOLUTE + (PORT datab (177:177:177) (216:216:216)) + (PORT datad (466:466:466) (548:548:548)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vga_hc\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (918:918:918) (923:923:923)) + (PORT asdata (840:840:840) (929:929:929)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add0\~18) + (DELAY + (ABSOLUTE + (PORT datad (132:132:132) (169:169:169)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vga_hc\~1) + (DELAY + (ABSOLUTE + (PORT dataa (410:410:410) (476:476:476)) + (PORT datad (455:455:455) (531:531:531)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vga_hc\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (919:919:919) (923:923:923)) + (PORT asdata (336:336:336) (365:365:365)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (401:401:401) (508:508:508)) + (PORT datab (401:401:401) (489:489:489)) + (PORT datac (618:618:618) (727:727:727)) + (PORT datad (373:373:373) (453:453:453)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (700:700:700) (821:821:821)) + (PORT datab (724:724:724) (838:838:838)) + (PORT datac (174:174:174) (210:210:210)) + (PORT datad (477:477:477) (563:563:563)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (570:570:570) (677:677:677)) + (PORT datab (382:382:382) (469:469:469)) + (PORT datac (347:347:347) (420:420:420)) + (PORT datad (280:280:280) (323:323:323)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (510:510:510) (614:614:614)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vga_vc\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (196:196:196) (242:242:242)) + (PORT datab (481:481:481) (567:567:567)) + (PORT datac (176:176:176) (211:211:211)) + (PORT datad (492:492:492) (591:591:591)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vga_vc\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (917:917:917) (922:922:922)) + (PORT asdata (485:485:485) (535:535:535)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add1\~2) + (DELAY + (ABSOLUTE + (PORT datab (484:484:484) (575:575:575)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vga_vc\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (322:322:322) (383:383:383)) + (PORT datab (300:300:300) (349:349:349)) + (PORT datad (688:688:688) (773:773:773)) + (IOPATH dataa combout (188:188:188) (179:179:179)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vga_vc\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (917:917:917) (922:922:922)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|Add1\~4) (DELAY (ABSOLUTE - (PORT dataa (362:362:362) (437:437:437)) + (PORT dataa (381:381:381) (460:460:460)) (IOPATH dataa combout (186:186:186) (175:175:175)) (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -13277,12 +1916,23 @@ (INSTANCE ula_\|video_\|vga_vc\[2\]\~2) (DELAY (ABSOLUTE - (PORT dataa (266:266:266) (332:332:332)) - (PORT datab (313:313:313) (364:364:364)) - (PORT datad (476:476:476) (552:552:552)) - (IOPATH dataa combout (188:188:188) (179:179:179)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) + (PORT dataa (194:194:194) (241:241:241)) + (PORT datab (482:482:482) (567:567:567)) + (PORT datac (634:634:634) (741:741:741)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (170:170:170) (165:165:165)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vga_vc\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (296:296:296) (343:343:343)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -13292,7 +1942,7 @@ (INSTANCE ula_\|video_\|vga_vc\[2\]) (DELAY (ABSOLUTE - (PORT clk (914:914:914) (918:918:918)) + (PORT clk (917:917:917) (922:922:922)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -13306,7 +1956,7 @@ (INSTANCE ula_\|video_\|Add1\~6) (DELAY (ABSOLUTE - (PORT dataa (376:376:376) (456:456:456)) + (PORT dataa (370:370:370) (452:452:452)) (IOPATH dataa combout (165:165:165) (173:173:173)) (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -13320,12 +1970,12 @@ (INSTANCE ula_\|video_\|vga_vc\[3\]\~3) (DELAY (ABSOLUTE - (PORT dataa (322:322:322) (377:377:377)) - (PORT datab (354:354:354) (417:417:417)) - (PORT datac (358:358:358) (437:437:437)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT dataa (371:371:371) (453:453:453)) + (PORT datab (481:481:481) (567:567:567)) + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (181:181:181) (215:215:215)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -13336,8 +1986,8 @@ (INSTANCE ula_\|video_\|vga_vc\[3\]) (DELAY (ABSOLUTE - (PORT clk (914:914:914) (918:918:918)) - (PORT asdata (707:707:707) (780:780:780)) + (PORT clk (917:917:917) (922:922:922)) + (PORT asdata (821:821:821) (912:912:912)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -13350,9 +2000,9 @@ (INSTANCE ula_\|video_\|Add1\~8) (DELAY (ABSOLUTE - (PORT datab (373:373:373) (454:454:454)) - (IOPATH datab combout (192:192:192) (177:177:177)) - (IOPATH datab cout (227:227:227) (175:175:175)) + (PORT dataa (401:401:401) (484:484:484)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) (IOPATH cin cout (34:34:34) (34:34:34)) @@ -13364,10 +2014,10 @@ (INSTANCE ula_\|video_\|vga_vc\[4\]\~5) (DELAY (ABSOLUTE - (PORT dataa (266:266:266) (332:332:332)) - (PORT datab (327:327:327) (381:381:381)) - (PORT datad (474:474:474) (549:549:549)) - (IOPATH dataa combout (188:188:188) (179:179:179)) + (PORT dataa (614:614:614) (712:712:712)) + (PORT datab (433:433:433) (505:505:505)) + (PORT datad (466:466:466) (548:548:548)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -13379,7 +2029,7 @@ (INSTANCE ula_\|video_\|vga_vc\[4\]) (DELAY (ABSOLUTE - (PORT clk (914:914:914) (918:918:918)) + (PORT clk (918:918:918) (923:923:923)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -13393,51 +2043,21 @@ (INSTANCE ula_\|video_\|Add1\~10) (DELAY (ABSOLUTE - (PORT dataa (382:382:382) (469:469:469)) - (IOPATH dataa combout (165:165:165) (173:173:173)) - (IOPATH dataa cout (226:226:226) (171:171:171)) + (PORT datab (381:381:381) (458:458:458)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) (IOPATH cin cout (34:34:34) (34:34:34)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vga_vc\[5\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (322:322:322) (377:377:377)) - (PORT datab (354:354:354) (417:417:417)) - (PORT datac (384:384:384) (465:465:465)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_vc\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (914:914:914) (918:918:918)) - (PORT asdata (467:467:467) (503:503:503)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|Add1\~12) (DELAY (ABSOLUTE - (PORT datab (389:389:389) (469:469:469)) + (PORT datab (630:630:630) (727:727:727)) (IOPATH datab combout (192:192:192) (177:177:177)) (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -13451,10 +2071,10 @@ (INSTANCE ula_\|video_\|vga_vc\[6\]\~4) (DELAY (ABSOLUTE - (PORT dataa (266:266:266) (332:332:332)) - (PORT datab (310:310:310) (365:365:365)) - (PORT datad (477:477:477) (553:553:553)) - (IOPATH dataa combout (188:188:188) (179:179:179)) + (PORT dataa (614:614:614) (712:712:712)) + (PORT datab (431:431:431) (499:499:499)) + (PORT datad (466:466:466) (548:548:548)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -13466,7 +2086,7 @@ (INSTANCE ula_\|video_\|vga_vc\[6\]) (DELAY (ABSOLUTE - (PORT clk (914:914:914) (918:918:918)) + (PORT clk (918:918:918) (923:923:923)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -13480,7 +2100,7 @@ (INSTANCE ula_\|video_\|Add1\~14) (DELAY (ABSOLUTE - (PORT datab (376:376:376) (449:449:449)) + (PORT datab (609:609:609) (704:704:704)) (IOPATH datab combout (166:166:166) (176:176:176)) (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -13494,10 +2114,10 @@ (INSTANCE ula_\|video_\|vga_vc\[7\]\~6) (DELAY (ABSOLUTE - (PORT dataa (266:266:266) (332:332:332)) - (PORT datab (639:639:639) (726:726:726)) - (PORT datad (476:476:476) (551:551:551)) - (IOPATH dataa combout (188:188:188) (179:179:179)) + (PORT dataa (615:615:615) (712:712:712)) + (PORT datab (448:448:448) (521:521:521)) + (PORT datad (467:467:467) (548:548:548)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -13509,7 +2129,7 @@ (INSTANCE ula_\|video_\|vga_vc\[7\]) (DELAY (ABSOLUTE - (PORT clk (914:914:914) (918:918:918)) + (PORT clk (918:918:918) (923:923:923)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -13523,9 +2143,9 @@ (INSTANCE ula_\|video_\|Add1\~16) (DELAY (ABSOLUTE - (PORT datab (399:399:399) (484:484:484)) - (IOPATH datab combout (192:192:192) (177:177:177)) - (IOPATH datab cout (227:227:227) (175:175:175)) + (PORT dataa (560:560:560) (665:665:665)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) (IOPATH cin cout (34:34:34) (34:34:34)) @@ -13537,9 +2157,9 @@ (INSTANCE ula_\|video_\|vga_vc\[8\]\~7) (DELAY (ABSOLUTE - (PORT dataa (266:266:266) (332:332:332)) - (PORT datab (521:521:521) (599:599:599)) - (PORT datad (473:473:473) (548:548:548)) + (PORT dataa (322:322:322) (383:383:383)) + (PORT datab (606:606:606) (695:695:695)) + (PORT datad (689:689:689) (773:773:773)) (IOPATH dataa combout (188:188:188) (179:179:179)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) @@ -13552,7 +2172,7 @@ (INSTANCE ula_\|video_\|vga_vc\[8\]) (DELAY (ABSOLUTE - (PORT clk (914:914:914) (918:918:918)) + (PORT clk (917:917:917) (922:922:922)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -13566,7 +2186,7 @@ (INSTANCE ula_\|video_\|Add1\~18) (DELAY (ABSOLUTE - (PORT datad (351:351:351) (415:415:415)) + (PORT datad (699:699:699) (821:821:821)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) ) @@ -13577,11 +2197,11 @@ (INSTANCE ula_\|video_\|vga_vc\[9\]\~9) (DELAY (ABSOLUTE - (PORT dataa (266:266:266) (332:332:332)) - (PORT datab (537:537:537) (608:608:608)) - (PORT datad (477:477:477) (552:552:552)) - (IOPATH dataa combout (188:188:188) (179:179:179)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT dataa (305:305:305) (363:363:363)) + (PORT datab (331:331:331) (390:390:390)) + (PORT datad (600:600:600) (686:686:686)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (188:188:188) (177:177:177)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -13592,7 +2212,7 @@ (INSTANCE ula_\|video_\|vga_vc\[9\]) (DELAY (ABSOLUTE - (PORT clk (914:914:914) (918:918:918)) + (PORT clk (918:918:918) (923:923:923)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -13601,15 +2221,31 @@ (HOLD d (posedge clk) (84:84:84)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Equal3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (504:504:504) (604:604:604)) + (PORT datab (625:625:625) (727:727:727)) + (PORT datac (508:508:508) (606:606:606)) + (PORT datad (628:628:628) (734:734:734)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|Equal2\~0) (DELAY (ABSOLUTE - (PORT dataa (147:147:147) (200:200:200)) - (PORT datab (146:146:146) (195:195:195)) - (PORT datac (144:144:144) (186:186:186)) - (PORT datad (133:133:133) (172:172:172)) + (PORT dataa (240:240:240) (293:293:293)) + (PORT datab (156:156:156) (206:206:206)) + (PORT datac (213:213:213) (261:261:261)) + (PORT datad (202:202:202) (247:247:247)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (124:124:124)) @@ -13617,31 +2253,15 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Equal3\~0) - (DELAY - (ABSOLUTE - (PORT dataa (650:650:650) (772:772:772)) - (PORT datab (457:457:457) (535:535:535)) - (PORT datac (339:339:339) (397:397:397)) - (PORT datad (370:370:370) (443:443:443)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|Equal3\~1) (DELAY (ABSOLUTE - (PORT dataa (340:340:340) (409:409:409)) - (PORT datab (359:359:359) (427:427:427)) - (PORT datac (300:300:300) (343:343:343)) - (PORT datad (156:156:156) (182:182:182)) + (PORT dataa (678:678:678) (789:789:789)) + (PORT datab (148:148:148) (199:199:199)) + (PORT datac (319:319:319) (372:372:372)) + (PORT datad (179:179:179) (208:208:208)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (167:167:167) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -13651,13 +2271,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vga_vc\[0\]\~0) + (INSTANCE ula_\|video_\|vga_vc\[5\]\~8) (DELAY (ABSOLUTE - (PORT dataa (265:265:265) (331:331:331)) - (PORT datab (295:295:295) (339:339:339)) - (PORT datad (472:472:472) (547:547:547)) - (IOPATH dataa combout (188:188:188) (179:179:179)) + (PORT dataa (615:615:615) (712:712:712)) + (PORT datab (321:321:321) (379:379:379)) + (PORT datad (468:468:468) (550:550:550)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -13666,10 +2286,10 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_vc\[0\]) + (INSTANCE ula_\|video_\|vga_vc\[5\]) (DELAY (ABSOLUTE - (PORT clk (914:914:914) (918:918:918)) + (PORT clk (918:918:918) (923:923:923)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -13680,32 +2300,33 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vga_vc\[1\]\~1) + (INSTANCE ula_\|video_\|Equal2\~1) (DELAY (ABSOLUTE - (PORT dataa (266:266:266) (332:332:332)) - (PORT datab (301:301:301) (348:348:348)) - (PORT datad (474:474:474) (549:549:549)) - (IOPATH dataa combout (188:188:188) (179:179:179)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) + (PORT dataa (384:384:384) (464:464:464)) + (PORT datab (712:712:712) (843:843:843)) + (PORT datac (470:470:470) (556:556:556)) + (PORT datad (491:491:491) (590:590:590)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_vc\[1\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Equal2\~2) (DELAY (ABSOLUTE - (PORT clk (914:914:914) (918:918:918)) - (PORT d (37:37:37) (50:50:50)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (PORT dataa (675:675:675) (786:786:786)) + (PORT datab (315:315:315) (368:368:368)) + (PORT datad (182:182:182) (211:211:211)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) ) (CELL (CELLTYPE "cycloneive_io_ibuf") @@ -13721,10 +2342,10 @@ (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_13\~0) (DELAY (ABSOLUTE - (PORT dataa (784:784:784) (902:902:902)) - (PORT datab (396:396:396) (475:475:475)) - (PORT datac (1149:1149:1149) (995:995:995)) - (PORT datad (359:359:359) (424:424:424)) + (PORT dataa (449:449:449) (527:527:527)) + (PORT datab (559:559:559) (665:665:665)) + (PORT datac (670:670:670) (781:781:781)) + (PORT datad (1199:1199:1199) (1031:1031:1031)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (124:124:124)) @@ -13732,180 +2353,18 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal79\~0) - (DELAY - (ABSOLUTE - (PORT dataa (712:712:712) (834:834:834)) - (PORT datab (535:535:535) (631:631:631)) - (PORT datac (917:917:917) (1101:1101:1101)) - (PORT datad (676:676:676) (800:800:800)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|DFFE_instIFF2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (833:833:833) (979:979:979)) - (PORT datab (187:187:187) (223:223:223)) - (PORT datad (365:365:365) (435:435:435)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_12) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (286:286:286)) - (PORT datab (1139:1139:1139) (1327:1327:1327)) - (PORT datad (152:152:152) (195:195:195)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_clkctrl") - (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_12\~clkctrl) - (DELAY - (ABSOLUTE - (PORT inclk[0] (890:890:890) (988:988:988)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|DFFE_instIFF2) - (DELAY - (ABSOLUTE - (PORT clk (916:916:916) (923:923:923)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (890:890:890) (894:894:894)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|iff1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (387:387:387) (463:463:463)) - (PORT datab (144:144:144) (193:193:193)) - (PORT datac (109:109:109) (134:134:134)) - (PORT datad (808:808:808) (948:948:948)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|iff1\~1) - (DELAY - (ABSOLUTE - (PORT dataa (723:723:723) (832:832:832)) - (PORT datab (142:142:142) (191:191:191)) - (PORT datac (481:481:481) (565:565:565)) - (PORT datad (92:92:92) (109:109:109)) - (IOPATH dataa combout (172:172:172) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_15) - (DELAY - (ABSOLUTE - (PORT datab (781:781:781) (906:906:906)) - (PORT datac (840:840:840) (975:975:975)) - (PORT datad (711:711:711) (827:827:827)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|iff1) - (DELAY - (ABSOLUTE - (PORT clk (916:916:916) (923:923:923)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (739:739:739) (803:803:803)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Equal2\~1) - (DELAY - (ABSOLUTE - (PORT dataa (872:872:872) (1011:1011:1011)) - (PORT datab (456:456:456) (534:534:534)) - (PORT datac (342:342:342) (402:402:402)) - (PORT datad (233:233:233) (287:287:287)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Equal2\~2) - (DELAY - (ABSOLUTE - (PORT datab (103:103:103) (132:132:132)) - (PORT datac (301:301:301) (343:343:343)) - (PORT datad (239:239:239) (295:295:295)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_13) (DELAY (ABSOLUTE - (PORT dataa (636:636:636) (749:749:749)) - (PORT datab (338:338:338) (394:394:394)) - (PORT datac (873:873:873) (1017:1017:1017)) - (PORT datad (456:456:456) (527:527:527)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT dataa (819:819:819) (963:963:963)) + (PORT datab (294:294:294) (344:344:344)) + (PORT datac (324:324:324) (383:383:383)) + (PORT datad (93:93:93) (111:111:111)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -13915,9 +2374,9 @@ (INSTANCE z80_\|interrupts_\|int_armed) (DELAY (ABSOLUTE - (PORT clk (913:913:913) (917:917:917)) + (PORT clk (914:914:914) (918:918:918)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (900:900:900) (904:904:904)) + (PORT clrn (901:901:901) (904:904:904)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -13926,1251 +2385,87 @@ (HOLD d (posedge clk) (84:84:84)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|DFFE_inst44\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (847:847:847) (995:995:995)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|interrupts_\|DFFE_inst44) - (DELAY - (ABSOLUTE - (PORT clk (914:914:914) (922:922:922)) - (PORT asdata (1177:1177:1177) (1361:1361:1361)) - (PORT clrn (928:928:928) (910:910:910)) - (PORT ena (890:890:890) (972:972:972)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~38) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (275:275:275)) - (PORT datac (655:655:655) (768:768:768)) - (PORT datad (147:147:147) (189:189:189)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~91) - (DELAY - (ABSOLUTE - (PORT dataa (942:942:942) (1111:1111:1111)) - (PORT datab (680:680:680) (788:788:788)) - (PORT datac (543:543:543) (644:644:644)) - (PORT datad (466:466:466) (541:541:541)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~45) - (DELAY - (ABSOLUTE - (PORT dataa (584:584:584) (679:679:679)) - (PORT datab (394:394:394) (470:470:470)) - (PORT datac (663:663:663) (783:783:783)) - (PORT datad (349:349:349) (403:403:403)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~44) - (DELAY - (ABSOLUTE - (PORT dataa (584:584:584) (679:679:679)) - (PORT datab (514:514:514) (601:601:601)) - (PORT datac (474:474:474) (540:540:540)) - (PORT datad (588:588:588) (671:671:671)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~46) - (DELAY - (ABSOLUTE - (PORT dataa (172:172:172) (212:212:212)) - (PORT datab (395:395:395) (471:471:471)) - (PORT datac (92:92:92) (114:114:114)) - (PORT datad (592:592:592) (676:676:676)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~37) - (DELAY - (ABSOLUTE - (PORT dataa (643:643:643) (753:753:753)) - (PORT datab (502:502:502) (579:579:579)) - (PORT datac (578:578:578) (652:652:652)) - (PORT datad (106:106:106) (124:124:124)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~50) - (DELAY - (ABSOLUTE - (PORT dataa (442:442:442) (518:518:518)) - (PORT datab (102:102:102) (131:131:131)) - (PORT datac (892:892:892) (1053:1053:1053)) - (PORT datad (1280:1280:1280) (1481:1481:1481)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~33) - (DELAY - (ABSOLUTE - (PORT dataa (121:121:121) (155:155:155)) - (PORT datab (650:650:650) (755:755:755)) - (PORT datac (592:592:592) (674:674:674)) - (PORT datad (314:314:314) (365:365:365)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla38pla13M3T2_4) - (DELAY - (ABSOLUTE - (PORT dataa (943:943:943) (1083:1083:1083)) - (PORT datab (328:328:328) (388:388:388)) - (PORT datac (902:902:902) (1048:1048:1048)) - (PORT datad (656:656:656) (761:761:761)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla40M3T2_4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (396:396:396) (481:481:481)) - (PORT datab (368:368:368) (440:440:440)) - (PORT datac (623:623:623) (726:726:726)) - (PORT datad (114:114:114) (137:137:137)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~31) - (DELAY - (ABSOLUTE - (PORT dataa (609:609:609) (697:697:697)) - (PORT datab (455:455:455) (525:525:525)) - (PORT datac (683:683:683) (777:777:777)) - (PORT datad (442:442:442) (508:508:508)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~32) - (DELAY - (ABSOLUTE - (PORT dataa (610:610:610) (697:697:697)) - (PORT datab (329:329:329) (389:389:389)) - (PORT datac (110:110:110) (135:135:135)) - (PORT datad (915:915:915) (1056:1056:1056)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (167:167:167) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~34) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (133:133:133)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (103:103:103) (132:132:132)) - (PORT datad (93:93:93) (113:113:113)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~51) - (DELAY - (ABSOLUTE - (PORT dataa (645:645:645) (744:744:744)) - (PORT datab (786:786:786) (922:922:922)) - (PORT datac (1403:1403:1403) (1620:1620:1620)) - (PORT datad (839:839:839) (994:994:994)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~30) - (DELAY - (ABSOLUTE - (PORT dataa (382:382:382) (454:454:454)) - (PORT datab (652:652:652) (755:755:755)) - (PORT datac (193:193:193) (227:227:227)) - (PORT datad (461:461:461) (529:529:529)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~52) - (DELAY - (ABSOLUTE - (PORT dataa (846:846:846) (1011:1011:1011)) - (PORT datab (783:783:783) (918:918:918)) - (PORT datac (1408:1408:1408) (1626:1626:1626)) - (PORT datad (595:595:595) (700:700:700)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~35) - (DELAY - (ABSOLUTE - (PORT dataa (192:192:192) (236:236:236)) - (PORT datab (104:104:104) (133:133:133)) - (PORT datac (324:324:324) (385:385:385)) - (PORT datad (94:94:94) (112:112:112)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~36) - (DELAY - (ABSOLUTE - (PORT dataa (606:606:606) (697:697:697)) - (PORT datab (345:345:345) (407:407:407)) - (PORT datac (335:335:335) (384:384:384)) - (PORT datad (773:773:773) (885:885:885)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~44) - (DELAY - (ABSOLUTE - (PORT dataa (1139:1139:1139) (1333:1333:1333)) - (PORT datab (514:514:514) (601:601:601)) - (PORT datac (788:788:788) (904:904:904)) - (PORT datad (352:352:352) (421:421:421)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_use_ixiypla53M2T2_4) - (DELAY - (ABSOLUTE - (PORT dataa (749:749:749) (876:876:876)) - (PORT datab (989:989:989) (1158:1158:1158)) - (PORT datad (354:354:354) (418:418:418)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~45) - (DELAY - (ABSOLUTE - (PORT dataa (114:114:114) (148:148:148)) - (PORT datab (115:115:115) (147:147:147)) - (PORT datac (366:366:366) (431:431:431)) - (PORT datad (302:302:302) (349:349:349)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~43) - (DELAY - (ABSOLUTE - (PORT dataa (791:791:791) (908:908:908)) - (PORT datab (369:369:369) (428:428:428)) - (PORT datac (1100:1100:1100) (1281:1281:1281)) - (PORT datad (710:710:710) (816:816:816)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~71) - (DELAY - (ABSOLUTE - (PORT dataa (109:109:109) (142:142:142)) - (PORT datab (117:117:117) (145:145:145)) - (PORT datac (346:346:346) (410:410:410)) - (PORT datad (101:101:101) (123:123:123)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~73) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (241:241:241)) - (PORT datab (102:102:102) (131:131:131)) - (PORT datac (341:341:341) (395:395:395)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~46) - (DELAY - (ABSOLUTE - (PORT dataa (368:368:368) (433:433:433)) - (PORT datab (393:393:393) (469:469:469)) - (PORT datac (344:344:344) (398:398:398)) - (PORT datad (642:642:642) (741:741:741)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (166:166:166) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~53) - (DELAY - (ABSOLUTE - (PORT dataa (920:920:920) (1083:1083:1083)) - (PORT datab (591:591:591) (704:704:704)) - (PORT datac (328:328:328) (388:388:388)) - (PORT datad (545:545:545) (639:639:639)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~39) - (DELAY - (ABSOLUTE - (PORT dataa (113:113:113) (147:147:147)) - (PORT datab (105:105:105) (134:134:134)) - (PORT datac (334:334:334) (383:383:383)) - (PORT datad (297:297:297) (344:344:344)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~47) - (DELAY - (ABSOLUTE - (PORT dataa (203:203:203) (238:238:238)) - (PORT datab (110:110:110) (143:143:143)) - (PORT datac (346:346:346) (409:409:409)) - (PORT datad (104:104:104) (121:121:121)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~74) - (DELAY - (ABSOLUTE - (PORT dataa (117:117:117) (149:149:149)) - (PORT datab (114:114:114) (142:142:142)) - (PORT datac (472:472:472) (539:539:539)) - (PORT datad (102:102:102) (120:120:120)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~78) - (DELAY - (ABSOLUTE - (PORT datab (108:108:108) (139:139:139)) - (PORT datac (353:353:353) (411:411:411)) - (PORT datad (89:89:89) (106:106:106)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~79) - (DELAY - (ABSOLUTE - (PORT dataa (109:109:109) (143:143:143)) - (PORT datab (174:174:174) (214:214:214)) - (PORT datac (343:343:343) (397:397:397)) - (PORT datad (96:96:96) (117:117:117)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~80) - (DELAY - (ABSOLUTE - (PORT dataa (369:369:369) (435:435:435)) - (PORT datab (517:517:517) (604:604:604)) - (PORT datac (663:663:663) (782:782:782)) - (PORT datad (99:99:99) (121:121:121)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~81) - (DELAY - (ABSOLUTE - (PORT dataa (483:483:483) (566:566:566)) - (PORT datab (377:377:377) (447:447:447)) - (PORT datac (546:546:546) (641:641:641)) - (PORT datad (345:345:345) (406:406:406)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~82) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (133:133:133)) - (PORT datab (383:383:383) (458:458:458)) - (PORT datac (538:538:538) (636:636:636)) - (PORT datad (919:919:919) (1050:1050:1050)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~83) - (DELAY - (ABSOLUTE - (PORT dataa (108:108:108) (142:142:142)) - (PORT datab (173:173:173) (210:210:210)) - (PORT datac (343:343:343) (396:396:396)) - (PORT datad (183:183:183) (213:213:213)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~84) - (DELAY - (ABSOLUTE - (PORT datab (106:106:106) (136:136:136)) - (PORT datac (93:93:93) (117:117:117)) - (PORT datad (93:93:93) (112:112:112)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~42) - (DELAY - (ABSOLUTE - (PORT datab (341:341:341) (404:404:404)) - (PORT datac (176:176:176) (211:211:211)) - (PORT datad (94:94:94) (113:113:113)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~90) - (DELAY - (ABSOLUTE - (PORT dataa (563:563:563) (668:668:668)) - (PORT datab (610:610:610) (722:722:722)) - (PORT datac (648:648:648) (744:744:744)) - (PORT datad (838:838:838) (993:993:993)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~41) - (DELAY - (ABSOLUTE - (PORT dataa (122:122:122) (161:161:161)) - (PORT datab (330:330:330) (390:390:390)) - (PORT datac (110:110:110) (135:135:135)) - (PORT datad (93:93:93) (112:112:112)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~66) - (DELAY - (ABSOLUTE - (PORT dataa (203:203:203) (281:281:281)) - (PORT datab (508:508:508) (586:586:586)) - (PORT datac (652:652:652) (766:766:766)) - (PORT datad (149:149:149) (193:193:193)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~67) - (DELAY - (ABSOLUTE - (PORT dataa (610:610:610) (698:698:698)) - (PORT datab (122:122:122) (152:152:152)) - (PORT datac (106:106:106) (136:136:136)) - (PORT datad (491:491:491) (559:559:559)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~68) - (DELAY - (ABSOLUTE - (PORT dataa (808:808:808) (935:935:935)) - (PORT datab (101:101:101) (129:129:129)) - (PORT datac (88:88:88) (109:109:109)) - (PORT datad (916:916:916) (1058:1058:1058)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~64) - (DELAY - (ABSOLUTE - (PORT dataa (610:610:610) (698:698:698)) - (PORT datab (124:124:124) (156:156:156)) - (PORT datac (106:106:106) (136:136:136)) - (PORT datad (315:315:315) (367:367:367)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~63) - (DELAY - (ABSOLUTE - (PORT dataa (458:458:458) (529:529:529)) - (PORT datab (627:627:627) (716:716:716)) - (PORT datac (177:177:177) (212:212:212)) - (PORT datad (470:470:470) (537:537:537)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~65) - (DELAY - (ABSOLUTE - (PORT dataa (641:641:641) (741:741:741)) - (PORT datab (191:191:191) (229:229:229)) - (PORT datac (157:157:157) (183:183:183)) - (PORT datad (88:88:88) (106:106:106)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~69) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (133:133:133)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datac (166:166:166) (197:197:197)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~49) - (DELAY - (ABSOLUTE - (PORT dataa (360:360:360) (432:432:432)) - (PORT datab (211:211:211) (252:252:252)) - (PORT datac (603:603:603) (696:696:696)) - (PORT datad (467:467:467) (541:541:541)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~50) - (DELAY - (ABSOLUTE - (PORT dataa (362:362:362) (434:434:434)) - (PORT datab (519:519:519) (612:612:612)) - (PORT datac (622:622:622) (717:717:717)) - (PORT datad (972:972:972) (1106:1106:1106)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~51) - (DELAY - (ABSOLUTE - (PORT dataa (189:189:189) (225:225:225)) - (PORT datab (622:622:622) (722:722:722)) - (PORT datac (564:564:564) (638:638:638)) - (PORT datad (665:665:665) (757:757:757)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~52) - (DELAY - (ABSOLUTE - (PORT dataa (364:364:364) (433:433:433)) - (PORT datab (484:484:484) (569:569:569)) - (PORT datac (501:501:501) (593:593:593)) - (PORT datad (161:161:161) (189:189:189)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~36) - (DELAY - (ABSOLUTE - (PORT dataa (514:514:514) (605:605:605)) - (PORT datab (488:488:488) (571:571:571)) - (PORT datac (760:760:760) (876:876:876)) - (PORT datad (474:474:474) (551:551:551)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~37) - (DELAY - (ABSOLUTE - (PORT dataa (779:779:779) (905:905:905)) - (PORT datab (509:509:509) (608:608:608)) - (PORT datac (166:166:166) (201:201:201)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~54) - (DELAY - (ABSOLUTE - (PORT dataa (122:122:122) (159:159:159)) - (PORT datab (105:105:105) (134:134:134)) - (PORT datac (88:88:88) (109:109:109)) - (PORT datad (315:315:315) (360:360:360)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~41) - (DELAY - (ABSOLUTE - (PORT dataa (675:675:675) (777:777:777)) - (PORT datab (652:652:652) (755:755:755)) - (PORT datac (192:192:192) (227:227:227)) - (PORT datad (645:645:645) (746:746:746)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~58) - (DELAY - (ABSOLUTE - (PORT dataa (605:605:605) (700:700:700)) - (PORT datab (652:652:652) (754:754:754)) - (PORT datad (102:102:102) (119:119:119)) - (IOPATH dataa combout (166:166:166) (159:159:159)) - (IOPATH datab combout (167:167:167) (158:158:158)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~55) - (DELAY - (ABSOLUTE - (PORT dataa (513:513:513) (609:609:609)) - (PORT datab (483:483:483) (568:568:568)) - (PORT datac (347:347:347) (408:408:408)) - (PORT datad (864:864:864) (1021:1021:1021)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~56) - (DELAY - (ABSOLUTE - (PORT dataa (241:241:241) (288:288:288)) - (PORT datab (115:115:115) (143:143:143)) - (PORT datac (430:430:430) (494:494:494)) - (PORT datad (102:102:102) (119:119:119)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~89) - (DELAY - (ABSOLUTE - (PORT dataa (749:749:749) (876:876:876)) - (PORT datab (624:624:624) (715:715:715)) - (PORT datac (785:785:785) (899:899:899)) - (PORT datad (466:466:466) (543:543:543)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~57) - (DELAY - (ABSOLUTE - (PORT dataa (109:109:109) (142:142:142)) - (PORT datab (456:456:456) (518:518:518)) - (PORT datac (160:160:160) (188:188:188)) - (PORT datad (89:89:89) (106:106:106)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~59) - (DELAY - (ABSOLUTE - (PORT dataa (485:485:485) (560:560:560)) - (PORT datab (102:102:102) (131:131:131)) - (PORT datac (317:317:317) (362:362:362)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~60) - (DELAY - (ABSOLUTE - (PORT dataa (642:642:642) (741:741:741)) - (PORT datab (114:114:114) (142:142:142)) - (PORT datac (291:291:291) (331:331:331)) - (PORT datad (295:295:295) (341:341:341)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~47) - (DELAY - (ABSOLUTE - (PORT dataa (593:593:593) (693:693:693)) - (PORT datab (110:110:110) (142:142:142)) - (PORT datac (579:579:579) (653:653:653)) - (PORT datad (100:100:100) (122:122:122)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~88) - (DELAY - (ABSOLUTE - (PORT dataa (920:920:920) (1089:1089:1089)) - (PORT datab (473:473:473) (548:548:548)) - (PORT datac (1407:1407:1407) (1624:1624:1624)) - (PORT datad (834:834:834) (989:989:989)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~48) - (DELAY - (ABSOLUTE - (PORT dataa (304:304:304) (356:356:356)) - (PORT datab (298:298:298) (346:346:346)) - (PORT datac (90:90:90) (111:111:111)) - (PORT datad (631:631:631) (718:718:718)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~40) - (DELAY - (ABSOLUTE - (PORT datab (342:342:342) (404:404:404)) - (PORT datac (175:175:175) (210:210:210)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~61) - (DELAY - (ABSOLUTE - (PORT dataa (121:121:121) (154:154:154)) - (PORT datab (112:112:112) (145:145:145)) - (PORT datac (579:579:579) (652:652:652)) - (PORT datad (628:628:628) (724:724:724)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~62) - (DELAY - (ABSOLUTE - (PORT dataa (644:644:644) (744:744:744)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (285:285:285) (332:332:332)) - (PORT datad (212:212:212) (249:249:249)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~70) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (135:135:135)) - (PORT datab (104:104:104) (133:133:133)) - (PORT datac (88:88:88) (109:109:109)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~85) - (DELAY - (ABSOLUTE - (PORT dataa (615:615:615) (710:710:710)) - (PORT datab (608:608:608) (701:701:701)) - (PORT datac (590:590:590) (677:677:677)) - (PORT datad (648:648:648) (752:752:752)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|d0_out) - (DELAY - (ABSOLUTE - (PORT datac (386:386:386) (469:469:469)) - (PORT datad (189:189:189) (220:220:220)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (135:135:135)) - (PORT datab (527:527:527) (619:619:619)) - (PORT datac (375:375:375) (447:447:447)) - (PORT datad (174:174:174) (206:206:206)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[0\]) - (DELAY - (ABSOLUTE - (PORT datac (541:541:541) (617:617:617)) - (PORT datad (498:498:498) (573:573:573)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|Q\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (93:93:93) (113:113:113)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (913:913:913)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (920:920:920) (904:904:904)) - (PORT ena (1125:1125:1125) (1271:1271:1271)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_41) - (DELAY - (ABSOLUTE - (PORT dataa (624:624:624) (725:725:725)) - (PORT datab (549:549:549) (642:642:642)) - (PORT datac (382:382:382) (465:465:465)) - (PORT datad (107:107:107) (126:126:126)) - (IOPATH dataa combout (188:188:188) (203:203:203)) - (IOPATH datab combout (188:188:188) (177:177:177)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (920:920:920) (927:927:927)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (679:679:679) (746:746:746)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[1\]) (DELAY (ABSOLUTE (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (535:535:535) (593:593:593)) - (PORT ena (636:636:636) (682:682:682)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (909:909:909) (896:896:896)) + (PORT ena (492:492:492) (529:529:529)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) + (HOLD d (posedge clk) (84:84:84)) (HOLD ena (posedge clk) (84:84:84)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~4) + (INSTANCE z80_\|decode_state_\|in_halt\~0) (DELAY (ABSOLUTE - (PORT dataa (184:184:184) (228:228:228)) - (PORT datab (381:381:381) (451:451:451)) - (PORT datad (655:655:655) (764:764:764)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (PORT dataa (257:257:257) (335:335:335)) + (PORT datac (152:152:152) (205:205:205)) + (PORT datad (392:392:392) (471:471:471)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|in_halt\~1) + (DELAY + (ABSOLUTE + (PORT dataa (179:179:179) (217:217:217)) + (PORT datab (900:900:900) (1035:1035:1035)) + (PORT datad (344:344:344) (402:402:402)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~5) + (CELLTYPE "dffeas") + (INSTANCE z80_\|decode_state_\|in_halt) (DELAY (ABSOLUTE - (PORT datab (405:405:405) (481:481:481)) - (PORT datac (119:119:119) (160:160:160)) - (PORT datad (339:339:339) (396:396:396)) + (PORT clk (909:909:909) (914:914:914)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (910:910:910) (897:897:897)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal50\~0) + (DELAY + (ABSOLUTE + (PORT datab (172:172:172) (232:232:232)) + (PORT datac (1021:1021:1021) (1156:1156:1156)) + (PORT datad (311:311:311) (357:357:357)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -15179,105 +2474,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|d1_out) + (INSTANCE z80_\|execute_\|ixy_d\~17) (DELAY (ABSOLUTE - (PORT dataa (441:441:441) (521:521:521)) - (PORT datab (207:207:207) (245:245:245)) - (PORT datac (103:103:103) (125:125:125)) - (IOPATH dataa combout (195:195:195) (203:203:203)) - (IOPATH datab combout (188:188:188) (177:177:177)) - (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (105:105:105) (137:137:137)) - (PORT datab (527:527:527) (618:618:618)) - (PORT datac (376:376:376) (448:448:448)) - (PORT datad (174:174:174) (205:205:205)) - (IOPATH dataa combout (170:170:170) (163:163:163)) + (PORT dataa (262:262:262) (335:335:335)) + (PORT datab (263:263:263) (330:330:330)) + (PORT datac (438:438:438) (502:502:502)) + (PORT datad (317:317:317) (362:362:362)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[1\]) + (INSTANCE z80_\|pla_decode_\|Equal44\~0) (DELAY (ABSOLUTE - (PORT datab (204:204:204) (241:241:241)) - (PORT datad (176:176:176) (210:210:210)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (920:920:920) (928:928:928)) - (PORT asdata (279:279:279) (298:298:298)) - (PORT clrn (927:927:927) (909:909:909)) - (PORT ena (1168:1168:1168) (1321:1321:1321)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_40\~4) - (DELAY - (ABSOLUTE - (PORT dataa (570:570:570) (664:664:664)) - (PORT datab (635:635:635) (731:731:731)) - (PORT datac (426:426:426) (498:498:498)) - (PORT datad (187:187:187) (218:218:218)) - (IOPATH dataa combout (181:181:181) (193:193:193)) - (IOPATH datab combout (182:182:182) (193:193:193)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|d0_out) - (DELAY - (ABSOLUTE - (PORT dataa (211:211:211) (253:253:253)) - (PORT datab (114:114:114) (142:142:142)) - (PORT datac (128:128:128) (169:169:169)) - (PORT datad (167:167:167) (198:198:198)) - (IOPATH dataa combout (158:158:158) (173:173:173)) - (IOPATH datab combout (160:160:160) (176:176:176)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (390:390:390) (469:469:469)) - (PORT datab (528:528:528) (619:619:619)) - (PORT datac (344:344:344) (405:405:405)) - (PORT datad (277:277:277) (315:315:315)) + (PORT dataa (570:570:570) (686:686:686)) + (PORT datab (558:558:558) (666:666:666)) + (PORT datac (531:531:531) (640:640:640)) + (PORT datad (535:535:535) (640:640:640)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -15287,35 +2506,145 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[2\]) + (INSTANCE z80_\|execute_\|ixy_d\~16) (DELAY (ABSOLUTE - (PORT dataa (288:288:288) (342:342:342)) - (PORT datad (114:114:114) (137:137:137)) - (IOPATH dataa combout (170:170:170) (163:163:163)) + (PORT dataa (258:258:258) (331:331:331)) + (PORT datab (266:266:266) (333:333:333)) + (PORT datac (661:661:661) (780:780:780)) + (PORT datad (109:109:109) (128:128:128)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|Q\[2\]\~feeder) + (INSTANCE z80_\|pla_decode_\|Equal3\~1) (DELAY (ABSOLUTE - (PORT datad (102:102:102) (119:119:119)) + (PORT datac (478:478:478) (569:569:569)) + (PORT datad (716:716:716) (858:858:858)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~10) + (DELAY + (ABSOLUTE + (PORT dataa (914:914:914) (1046:1046:1046)) + (PORT datab (362:362:362) (423:423:423)) + (PORT datac (491:491:491) (574:574:574)) + (PORT datad (529:529:529) (623:623:623)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~13) + (DELAY + (ABSOLUTE + (PORT dataa (663:663:663) (765:765:765)) + (PORT datab (194:194:194) (241:241:241)) + (PORT datac (895:895:895) (1042:1042:1042)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~14) + (DELAY + (ABSOLUTE + (PORT dataa (624:624:624) (733:733:733)) + (PORT datab (358:358:358) (428:428:428)) + (PORT datac (340:340:340) (403:403:403)) + (PORT datad (89:89:89) (106:106:106)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal49\~0) + (DELAY + (ABSOLUTE + (PORT datab (172:172:172) (232:232:232)) + (PORT datac (943:943:943) (1091:1091:1091)) + (PORT datad (312:312:312) (357:357:357)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~15) + (DELAY + (ABSOLUTE + (PORT dataa (522:522:522) (609:609:609)) + (PORT datab (508:508:508) (586:586:586)) + (PORT datac (88:88:88) (109:109:109)) + (PORT datad (709:709:709) (819:819:819)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_ixy_dT5_7) + (DELAY + (ABSOLUTE + (PORT datab (507:507:507) (584:584:584)) + (PORT datac (812:812:812) (974:974:974)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|SYNTHESIZED_WIRE_0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (396:396:396) (493:493:493)) + (PORT datab (531:531:531) (623:623:623)) + (PORT datac (101:101:101) (122:122:122)) + (PORT datad (208:208:208) (243:243:243)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[2\]) + (INSTANCE z80_\|decode_state_\|DFFE_inst4) (DELAY (ABSOLUTE - (PORT clk (920:920:920) (928:928:928)) + (PORT clk (909:909:909) (917:917:917)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (928:928:928) (909:909:909)) - (PORT ena (1169:1169:1169) (1320:1320:1320)) + (PORT clrn (904:904:904) (891:891:891)) + (PORT ena (422:422:422) (450:450:450)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -15327,15 +2656,1685 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_42) + (INSTANCE z80_\|execute_\|ctl_ir_we\~5) (DELAY (ABSOLUTE - (PORT dataa (200:200:200) (242:242:242)) - (PORT datab (635:635:635) (730:730:730)) - (PORT datac (548:548:548) (641:641:641)) - (PORT datad (207:207:207) (252:252:252)) - (IOPATH dataa combout (181:181:181) (180:180:180)) + (PORT dataa (571:571:571) (686:686:686)) + (PORT datab (271:271:271) (339:339:339)) + (PORT datad (237:237:237) (295:295:295)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~13) + (DELAY + (ABSOLUTE + (PORT dataa (549:549:549) (642:642:642)) + (PORT datab (318:318:318) (367:367:367)) + (PORT datac (1096:1096:1096) (1263:1263:1263)) + (PORT datad (470:470:470) (545:545:545)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (920:920:920) (928:928:928)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (909:909:909) (896:896:896)) + (PORT ena (738:738:738) (795:795:795)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal8\~0) + (DELAY + (ABSOLUTE + (PORT dataa (871:871:871) (1033:1033:1033)) + (PORT datac (769:769:769) (940:940:940)) + (PORT datad (851:851:851) (995:995:995)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~6) + (DELAY + (ABSOLUTE + (PORT datab (717:717:717) (859:859:859)) + (PORT datac (347:347:347) (406:406:406)) + (PORT datad (672:672:672) (777:777:777)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal9\~0) + (DELAY + (ABSOLUTE + (PORT datab (791:791:791) (937:937:937)) + (PORT datad (792:792:792) (932:932:932)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal9\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1456:1456:1456) (1704:1704:1704)) + (PORT datab (544:544:544) (642:642:642)) + (PORT datac (961:961:961) (1125:1125:1125)) + (PORT datad (503:503:503) (593:593:593)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla10M5T1_5\~2) + (DELAY + (ABSOLUTE + (PORT datab (690:690:690) (824:824:824)) + (PORT datac (1006:1006:1006) (1164:1164:1164)) + (PORT datad (564:564:564) (672:672:672)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (748:748:748) (868:868:868)) + (PORT datab (697:697:697) (814:814:814)) + (PORT datac (661:661:661) (762:762:762)) + (PORT datad (356:356:356) (414:414:414)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal13\~1) + (DELAY + (ABSOLUTE + (PORT dataa (878:878:878) (1040:1040:1040)) + (PORT datac (782:782:782) (956:956:956)) + (PORT datad (850:850:850) (993:993:993)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal69\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1161:1161:1161) (1376:1376:1376)) + (PORT datab (686:686:686) (801:801:801)) + (PORT datac (643:643:643) (772:772:772)) + (PORT datad (654:654:654) (747:747:747)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (338:338:338) (401:401:401)) + (PORT datab (866:866:866) (1016:1016:1016)) + (PORT datac (447:447:447) (520:520:520)) + (PORT datad (492:492:492) (591:591:591)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~27) + (DELAY + (ABSOLUTE + (PORT dataa (778:778:778) (926:926:926)) + (PORT datab (120:120:120) (151:151:151)) + (PORT datac (689:689:689) (807:807:807)) + (PORT datad (462:462:462) (531:531:531)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~2) + (DELAY + (ABSOLUTE + (PORT dataa (945:945:945) (1084:1084:1084)) + (PORT datab (558:558:558) (651:651:651)) + (PORT datac (623:623:623) (719:719:719)) + (PORT datad (671:671:671) (766:766:766)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|rsel3) + (DELAY + (ABSOLUTE + (PORT dataa (434:434:434) (537:537:537)) + (PORT datac (755:755:755) (885:885:885)) + (PORT datad (675:675:675) (801:801:801)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~12) + (DELAY + (ABSOLUTE + (PORT dataa (397:397:397) (482:482:482)) + (PORT datab (593:593:593) (718:718:718)) + (PORT datac (701:701:701) (836:836:836)) + (PORT datad (560:560:560) (671:671:671)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3) + (DELAY + (ABSOLUTE + (PORT dataa (548:548:548) (662:662:662)) + (PORT datac (604:604:604) (688:688:688)) + (PORT datad (757:757:757) (885:885:885)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal56\~0) + (DELAY + (ABSOLUTE + (PORT dataa (547:547:547) (663:663:663)) + (PORT datab (841:841:841) (977:977:977)) + (PORT datac (574:574:574) (673:673:673)) + (PORT datad (929:929:929) (1099:1099:1099)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~24) + (DELAY + (ABSOLUTE + (PORT dataa (1163:1163:1163) (1361:1361:1361)) + (PORT datab (1244:1244:1244) (1422:1422:1422)) + (PORT datac (1079:1079:1079) (1240:1240:1240)) + (PORT datad (500:500:500) (593:593:593)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~25) + (DELAY + (ABSOLUTE + (PORT dataa (1233:1233:1233) (1446:1446:1446)) + (PORT datab (548:548:548) (647:647:647)) + (PORT datac (642:642:642) (745:745:745)) + (PORT datad (484:484:484) (580:580:580)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~2) + (DELAY + (ABSOLUTE + (PORT dataa (527:527:527) (635:635:635)) + (PORT datac (306:306:306) (355:355:355)) + (PORT datad (572:572:572) (655:655:655)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~16) + (DELAY + (ABSOLUTE + (PORT dataa (551:551:551) (665:665:665)) + (PORT datab (547:547:547) (638:638:638)) + (PORT datac (734:734:734) (842:842:842)) + (PORT datad (683:683:683) (800:800:800)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~3) + (DELAY + (ABSOLUTE + (PORT dataa (351:351:351) (421:421:421)) + (PORT datab (369:369:369) (445:445:445)) + (PORT datac (101:101:101) (122:122:122)) + (PORT datad (102:102:102) (119:119:119)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal40\~0) + (DELAY + (ABSOLUTE + (PORT dataa (519:519:519) (621:621:621)) + (PORT datac (478:478:478) (570:570:570)) + (PORT datad (717:717:717) (859:859:859)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal40\~1) + (DELAY + (ABSOLUTE + (PORT dataa (124:124:124) (161:161:161)) + (PORT datab (474:474:474) (552:552:552)) + (PORT datad (783:783:783) (932:932:932)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla23pla16M3T1_5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (547:547:547) (663:663:663)) + (PORT datab (606:606:606) (698:698:698)) + (PORT datac (506:506:506) (593:593:593)) + (PORT datad (582:582:582) (692:692:692)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal3\~0) + (DELAY + (ABSOLUTE + (PORT datab (669:669:669) (805:805:805)) + (PORT datad (690:690:690) (823:823:823)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal39\~0) + (DELAY + (ABSOLUTE + (PORT dataa (123:123:123) (160:160:160)) + (PORT datab (474:474:474) (552:552:552)) + (PORT datac (763:763:763) (902:902:902)) + (PORT datad (506:506:506) (575:575:575)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~4) + (DELAY + (ABSOLUTE + (PORT dataa (723:723:723) (843:843:843)) + (PORT datab (352:352:352) (416:416:416)) + (PORT datac (780:780:780) (899:899:899)) + (PORT datad (1117:1117:1117) (1279:1279:1279)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~0) + (DELAY + (ABSOLUTE + (PORT datac (897:897:897) (1050:1050:1050)) + (PORT datad (743:743:743) (883:883:883)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|comb\~0) + (DELAY + (ABSOLUTE + (PORT datac (755:755:755) (881:881:881)) + (PORT datad (657:657:657) (772:772:772)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal41\~0) + (DELAY + (ABSOLUTE + (PORT dataa (577:577:577) (703:703:703)) + (PORT datad (573:573:573) (690:690:690)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal47\~0) + (DELAY + (ABSOLUTE + (PORT dataa (518:518:518) (622:622:622)) + (PORT datab (351:351:351) (410:410:410)) + (PORT datac (335:335:335) (398:398:398)) + (PORT datad (376:376:376) (439:439:439)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~32) + (DELAY + (ABSOLUTE + (PORT dataa (698:698:698) (820:820:820)) + (PORT datab (983:983:983) (1127:1127:1127)) + (PORT datac (113:113:113) (139:139:139)) + (PORT datad (749:749:749) (879:879:879)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal19\~0) + (DELAY + (ABSOLUTE + (PORT dataa (744:744:744) (874:874:874)) + (PORT datab (491:491:491) (561:561:561)) + (PORT datac (405:405:405) (505:505:505)) + (PORT datad (595:595:595) (672:672:672)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~9) + (DELAY + (ABSOLUTE + (PORT dataa (112:112:112) (147:147:147)) + (PORT datab (671:671:671) (778:778:778)) + (PORT datac (893:893:893) (1047:1047:1047)) + (PORT datad (737:737:737) (876:876:876)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~5) + (DELAY + (ABSOLUTE + (PORT dataa (330:330:330) (378:378:378)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (320:320:320) (374:374:374)) + (PORT datad (744:744:744) (838:838:838)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~4) + (DELAY + (ABSOLUTE + (PORT dataa (158:158:158) (216:216:216)) + (PORT datab (632:632:632) (737:737:737)) + (PORT datac (209:209:209) (270:270:270)) + (PORT datad (207:207:207) (260:260:260)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla21M2T2_3) + (DELAY + (ABSOLUTE + (PORT dataa (531:531:531) (629:629:629)) + (PORT datab (939:939:939) (1069:1069:1069)) + (PORT datac (526:526:526) (631:631:631)) + (PORT datad (1468:1468:1468) (1701:1701:1701)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~34) + (DELAY + (ABSOLUTE + (PORT dataa (393:393:393) (483:483:483)) + (PORT datab (947:947:947) (1103:1103:1103)) + (PORT datac (607:607:607) (708:708:708)) + (PORT datad (486:486:486) (569:569:569)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_ixy_dT4_2) + (DELAY + (ABSOLUTE + (PORT datac (935:935:935) (1100:1100:1100)) + (PORT datad (605:605:605) (688:688:688)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (107:107:107) (140:140:140)) + (PORT datab (627:627:627) (753:753:753)) + (PORT datac (547:547:547) (643:643:643)) + (PORT datad (580:580:580) (667:667:667)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~5) + (DELAY + (ABSOLUTE + (PORT datab (246:246:246) (309:309:309)) + (PORT datac (219:219:219) (276:276:276)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~11) + (DELAY + (ABSOLUTE + (PORT dataa (457:457:457) (531:531:531)) + (PORT datab (958:958:958) (1094:1094:1094)) + (PORT datac (469:469:469) (542:542:542)) + (PORT datad (527:527:527) (647:647:647)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal20\~0) + (DELAY + (ABSOLUTE + (PORT dataa (965:965:965) (1145:1145:1145)) + (PORT datab (834:834:834) (970:970:970)) + (PORT datac (730:730:730) (855:855:855)) + (PORT datad (354:354:354) (425:425:425)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal13\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1163:1163:1163) (1379:1379:1379)) + (PORT datab (685:685:685) (800:800:800)) + (PORT datac (645:645:645) (775:775:775)) + (PORT datad (654:654:654) (746:746:746)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~24) + (DELAY + (ABSOLUTE + (PORT datac (1242:1242:1242) (1434:1434:1434)) + (PORT datad (787:787:787) (926:926:926)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (615:615:615) (716:716:716)) + (PORT datab (555:555:555) (647:647:647)) + (PORT datac (774:774:774) (889:889:889)) + (PORT datad (619:619:619) (714:714:714)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal48\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1167:1167:1167) (1383:1383:1383)) + (PORT datab (684:684:684) (799:799:799)) + (PORT datac (650:650:650) (780:780:780)) + (PORT datad (652:652:652) (745:745:745)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal10\~0) + (DELAY + (ABSOLUTE + (PORT dataa (809:809:809) (985:985:985)) + (PORT datab (696:696:696) (809:809:809)) + (PORT datac (861:861:861) (1014:1014:1014)) + (PORT datad (850:850:850) (993:993:993)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal11\~0) + (DELAY + (ABSOLUTE + (PORT dataa (810:810:810) (987:987:987)) + (PORT datab (696:696:696) (809:809:809)) + (PORT datac (861:861:861) (1015:1015:1015)) + (PORT datad (849:849:849) (993:993:993)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal63\~0) + (DELAY + (ABSOLUTE + (PORT dataa (964:964:964) (1144:1144:1144)) + (PORT datab (835:835:835) (970:970:970)) + (PORT datac (730:730:730) (855:855:855)) + (PORT datad (354:354:354) (425:425:425)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf2_we) + (DELAY + (ABSOLUTE + (PORT dataa (644:644:644) (744:744:744)) + (PORT datab (774:774:774) (892:892:892)) + (PORT datac (781:781:781) (926:926:926)) + (PORT datad (497:497:497) (591:591:591)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~41) + (DELAY + (ABSOLUTE + (PORT dataa (1314:1314:1314) (1523:1523:1523)) + (PORT datab (963:963:963) (1101:1101:1101)) + (PORT datac (107:107:107) (132:132:132)) + (PORT datad (757:757:757) (871:871:871)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal68\~3) + (DELAY + (ABSOLUTE + (PORT dataa (497:497:497) (597:597:597)) + (PORT datab (735:735:735) (887:887:887)) + (PORT datac (449:449:449) (524:524:524)) + (PORT datad (496:496:496) (592:592:592)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~7) + (DELAY + (ABSOLUTE + (PORT dataa (129:129:129) (160:160:160)) + (PORT datab (109:109:109) (139:139:139)) + (PORT datac (690:690:690) (809:809:809)) + (PORT datad (627:627:627) (726:726:726)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~8) + (DELAY + (ABSOLUTE + (PORT dataa (587:587:587) (682:682:682)) + (PORT datab (890:890:890) (1032:1032:1032)) + (PORT datac (915:915:915) (1053:1053:1053)) + (PORT datad (482:482:482) (560:560:560)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~9) + (DELAY + (ABSOLUTE + (PORT dataa (321:321:321) (378:378:378)) + (PORT datab (964:964:964) (1118:1118:1118)) + (PORT datac (1065:1065:1065) (1236:1236:1236)) + (PORT datad (505:505:505) (608:608:608)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (573:573:573) (699:699:699)) + (PORT datad (574:574:574) (691:691:691)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (407:407:407) (494:494:494)) + (PORT datab (120:120:120) (150:150:150)) + (PORT datac (708:708:708) (844:844:844)) + (PORT datad (539:539:539) (638:638:638)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~14) + (DELAY + (ABSOLUTE + (PORT dataa (409:409:409) (496:496:496)) + (PORT datab (596:596:596) (721:721:721)) + (PORT datac (709:709:709) (845:845:845)) + (PORT datad (550:550:550) (660:660:660)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~4) + (DELAY + (ABSOLUTE + (PORT dataa (474:474:474) (546:546:546)) + (PORT datab (1080:1080:1080) (1258:1258:1258)) + (PORT datac (947:947:947) (1100:1100:1100)) + (PORT datad (332:332:332) (387:387:387)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~5) + (DELAY + (ABSOLUTE + (PORT dataa (656:656:656) (754:754:754)) + (PORT datab (941:941:941) (1104:1104:1104)) + (PORT datac (278:278:278) (319:319:319)) + (PORT datad (752:752:752) (850:850:850)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~4) + (DELAY + (ABSOLUTE + (PORT dataa (911:911:911) (1043:1043:1043)) + (PORT datab (356:356:356) (416:416:416)) + (PORT datac (501:501:501) (587:587:587)) + (PORT datad (532:532:532) (626:626:626)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~6) + (DELAY + (ABSOLUTE + (PORT dataa (505:505:505) (603:603:603)) + (PORT datab (848:848:848) (979:979:979)) + (PORT datac (915:915:915) (1053:1053:1053)) + (PORT datad (798:798:798) (912:912:912)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~9) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (137:137:137)) + (PORT datab (107:107:107) (138:138:138)) + (PORT datac (89:89:89) (111:111:111)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_iorw\~11) + (DELAY + (ABSOLUTE + (PORT dataa (874:874:874) (1036:1036:1036)) + (PORT datab (813:813:813) (946:946:946)) + (PORT datac (774:774:774) (945:945:945)) + (PORT datad (851:851:851) (994:994:994)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~17) + (DELAY + (ABSOLUTE + (PORT dataa (805:805:805) (981:981:981)) + (PORT datab (696:696:696) (809:809:809)) + (PORT datac (859:859:859) (1012:1012:1012)) + (PORT datad (850:850:850) (993:993:993)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~18) + (DELAY + (ABSOLUTE + (PORT dataa (513:513:513) (599:599:599)) + (PORT datab (1364:1364:1364) (1545:1545:1545)) + (PORT datac (477:477:477) (544:544:544)) + (PORT datad (448:448:448) (521:521:521)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal37\~0) + (DELAY + (ABSOLUTE + (PORT dataa (516:516:516) (620:620:620)) + (PORT datab (355:355:355) (415:415:415)) + (PORT datac (323:323:323) (377:377:377)) + (PORT datad (380:380:380) (444:444:444)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~19) + (DELAY + (ABSOLUTE + (PORT dataa (585:585:585) (681:681:681)) + (PORT datab (663:663:663) (755:755:755)) + (PORT datac (662:662:662) (756:756:756)) + (PORT datad (1038:1038:1038) (1206:1206:1206)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal35\~0) + (DELAY + (ABSOLUTE + (PORT dataa (515:515:515) (618:618:618)) + (PORT datab (358:358:358) (418:418:418)) + (PORT datac (291:291:291) (335:335:335)) + (PORT datad (384:384:384) (447:447:447)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal21\~1) + (DELAY + (ABSOLUTE + (PORT dataa (128:128:128) (167:167:167)) + (PORT datab (479:479:479) (557:557:557)) + (PORT datac (687:687:687) (806:806:806)) + (PORT datad (785:785:785) (934:934:934)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~17) + (DELAY + (ABSOLUTE + (PORT dataa (799:799:799) (926:926:926)) + (PORT datab (602:602:602) (703:703:703)) + (PORT datac (463:463:463) (540:540:540)) + (PORT datad (939:939:939) (1076:1076:1076)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~20) + (DELAY + (ABSOLUTE + (PORT dataa (471:471:471) (543:543:543)) + (PORT datab (480:480:480) (563:563:563)) + (PORT datac (88:88:88) (109:109:109)) + (PORT datad (93:93:93) (111:111:111)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~9) + (DELAY + (ABSOLUTE + (PORT dataa (730:730:730) (867:867:867)) + (PORT datab (116:116:116) (145:145:145)) + (PORT datac (386:386:386) (463:463:463)) + (PORT datad (540:540:540) (639:639:639)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~11) + (DELAY + (ABSOLUTE + (PORT dataa (633:633:633) (727:727:727)) + (PORT datab (864:864:864) (1016:1016:1016)) + (PORT datac (517:517:517) (599:599:599)) + (PORT datad (1405:1405:1405) (1620:1620:1620)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~15) + (DELAY + (ABSOLUTE + (PORT dataa (406:406:406) (493:493:493)) + (PORT datab (595:595:595) (721:721:721)) + (PORT datac (707:707:707) (843:843:843)) + (PORT datad (553:553:553) (663:663:663)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~7) + (DELAY + (ABSOLUTE + (PORT dataa (814:814:814) (943:943:943)) + (PORT datab (608:608:608) (707:707:707)) + (PORT datac (88:88:88) (109:109:109)) + (PORT datad (515:515:515) (600:600:600)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~7) + (DELAY + (ABSOLUTE + (PORT dataa (401:401:401) (486:486:486)) + (PORT datab (594:594:594) (719:719:719)) + (PORT datac (704:704:704) (839:839:839)) + (PORT datad (557:557:557) (668:668:668)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal46\~0) + (DELAY + (ABSOLUTE + (PORT dataa (931:931:931) (1083:1083:1083)) + (PORT datab (143:143:143) (193:193:193)) + (PORT datac (130:130:130) (173:173:173)) + (PORT datad (203:203:203) (255:255:255)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~11) + (DELAY + (ABSOLUTE + (PORT dataa (577:577:577) (704:704:704)) + (PORT datab (592:592:592) (717:717:717)) + (PORT datac (376:376:376) (451:451:451)) + (PORT datad (619:619:619) (715:715:715)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~3) + (DELAY + (ABSOLUTE + (PORT dataa (367:367:367) (436:436:436)) + (PORT datab (813:813:813) (944:944:944)) + (PORT datac (514:514:514) (597:597:597)) + (PORT datad (492:492:492) (569:569:569)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal52\~1) + (DELAY + (ABSOLUTE + (PORT dataa (685:685:685) (806:806:806)) + (PORT datab (557:557:557) (665:665:665)) + (PORT datac (348:348:348) (401:401:401)) + (PORT datad (549:549:549) (659:659:659)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~21) + (DELAY + (ABSOLUTE + (PORT dataa (1340:1340:1340) (1544:1544:1544)) + (PORT datab (699:699:699) (831:831:831)) + (PORT datac (439:439:439) (501:501:501)) + (PORT datad (201:201:201) (235:235:235)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~13) + (DELAY + (ABSOLUTE + (PORT dataa (336:336:336) (394:394:394)) + (PORT datab (683:683:683) (795:795:795)) + (PORT datac (406:406:406) (457:457:457)) + (PORT datad (601:601:601) (684:684:684)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~6) + (DELAY + (ABSOLUTE + (PORT dataa (259:259:259) (332:332:332)) + (PORT datab (265:265:265) (332:332:332)) + (PORT datac (661:661:661) (780:780:780)) + (PORT datad (109:109:109) (128:128:128)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~14) + (DELAY + (ABSOLUTE + (PORT dataa (825:825:825) (974:974:974)) + (PORT datac (533:533:533) (640:640:640)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~14) + (DELAY + (ABSOLUTE + (PORT dataa (116:116:116) (147:147:147)) + (PORT datab (115:115:115) (143:143:143)) + (PORT datac (620:620:620) (719:719:719)) + (PORT datad (876:876:876) (1028:1028:1028)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (907:907:907) (1042:1042:1042)) + (PORT datab (1060:1060:1060) (1220:1220:1220)) + (PORT datac (908:908:908) (1036:1036:1036)) + (PORT datad (285:285:285) (329:329:329)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (452:452:452) (535:535:535)) + (PORT datab (643:643:643) (736:736:736)) + (PORT datac (333:333:333) (391:391:391)) + (PORT datad (103:103:103) (120:120:120)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1179:1179:1179) (1370:1370:1370)) + (PORT datab (354:354:354) (414:414:414)) + (PORT datac (452:452:452) (523:523:523)) + (PORT datad (379:379:379) (443:443:443)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|rsel0) + (DELAY + (ABSOLUTE + (PORT datab (829:829:829) (978:978:978)) + (PORT datac (809:809:809) (939:939:939)) + (PORT datad (501:501:501) (592:592:592)) + (IOPATH datab combout (188:188:188) (181:181:181)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1209:1209:1209) (1405:1405:1405)) + (PORT datac (866:866:866) (1019:1019:1019)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~0) + (DELAY + (ABSOLUTE + (PORT dataa (482:482:482) (556:556:556)) + (PORT datab (486:486:486) (564:564:564)) + (PORT datac (441:441:441) (505:505:505)) + (PORT datad (526:526:526) (646:646:646)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~2) + (DELAY + (ABSOLUTE + (PORT datab (207:207:207) (268:268:268)) + (PORT datad (230:230:230) (288:288:288)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_ixy_dT2_2) + (DELAY + (ABSOLUTE + (PORT dataa (613:613:613) (706:706:706)) + (PORT datad (957:957:957) (1103:1103:1103)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (531:531:531) (626:626:626)) + (PORT datab (117:117:117) (151:151:151)) + (PORT datac (796:796:796) (943:943:943)) + (PORT datad (709:709:709) (820:820:820)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (797:797:797) (924:924:924)) + (PORT datab (957:957:957) (1101:1101:1101)) + (PORT datac (908:908:908) (1033:1033:1033)) + (PORT datad (699:699:699) (813:813:813)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~6) + (DELAY + (ABSOLUTE + (PORT dataa (597:597:597) (689:689:689)) + (PORT datab (1260:1260:1260) (1467:1467:1467)) + (PORT datac (435:435:435) (523:523:523)) + (PORT datad (1092:1092:1092) (1267:1267:1267)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~5) + (DELAY + (ABSOLUTE + (PORT dataa (115:115:115) (146:146:146)) + (PORT datab (114:114:114) (142:142:142)) + (PORT datac (210:210:210) (270:270:270)) + (PORT datad (206:206:206) (260:260:260)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~1) + (DELAY + (ABSOLUTE + (PORT dataa (231:231:231) (288:288:288)) + (PORT datab (1306:1306:1306) (1512:1512:1512)) + (PORT datac (768:768:768) (880:880:880)) + (PORT datad (308:308:308) (360:360:360)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~1) + (DELAY + (ABSOLUTE + (PORT dataa (961:961:961) (1115:1115:1115)) + (PORT datab (172:172:172) (232:232:232)) + (PORT datac (1021:1021:1021) (1155:1155:1155)) + (PORT datad (311:311:311) (356:356:356)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~7) + (DELAY + (ABSOLUTE + (PORT dataa (329:329:329) (386:386:386)) + (PORT datab (1038:1038:1038) (1179:1179:1179)) + (PORT datac (337:337:337) (391:391:391)) + (PORT datad (155:155:155) (205:205:205)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~4) + (DELAY + (ABSOLUTE + (PORT dataa (600:600:600) (697:697:697)) + (PORT datab (114:114:114) (141:141:141)) + (PORT datac (590:590:590) (679:679:679)) + (PORT datad (436:436:436) (506:506:506)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~57) + (DELAY + (ABSOLUTE + (PORT dataa (387:387:387) (455:455:455)) + (PORT datab (643:643:643) (771:771:771)) + (PORT datac (692:692:692) (809:809:809)) + (PORT datad (757:757:757) (878:878:878)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~5) + (DELAY + (ABSOLUTE + (PORT datab (484:484:484) (561:561:561)) + (PORT datac (451:451:451) (513:513:513)) + (PORT datad (613:613:613) (704:704:704)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~7) + (DELAY + (ABSOLUTE + (PORT dataa (527:527:527) (619:619:619)) + (PORT datab (473:473:473) (546:546:546)) + (PORT datac (431:431:431) (492:492:492)) + (PORT datad (101:101:101) (124:124:124)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla91pla21M4T2_3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1173:1173:1173) (1370:1370:1370)) + (PORT datab (668:668:668) (777:777:777)) + (PORT datac (951:951:951) (1082:1082:1082)) + (PORT datad (820:820:820) (951:951:951)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~41) + (DELAY + (ABSOLUTE + (PORT dataa (1172:1172:1172) (1368:1368:1368)) + (PORT datab (970:970:970) (1118:1118:1118)) + (PORT datac (1563:1563:1563) (1793:1793:1793)) + (PORT datad (523:523:523) (596:596:596)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -15346,283 +4345,12 @@ (INSTANCE z80_\|execute_\|ctl_inc_cy\~86) (DELAY (ABSOLUTE - (PORT dataa (115:115:115) (146:146:146)) - (PORT datab (108:108:108) (139:139:139)) - (PORT datac (93:93:93) (116:116:116)) - (PORT datad (94:94:94) (113:113:113)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|SYNTHESIZED_WIRE_0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (249:249:249)) - (PORT datab (605:605:605) (698:698:698)) - (PORT datac (589:589:589) (671:671:671)) - (PORT datad (652:652:652) (757:757:757)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~11) - (DELAY - (ABSOLUTE - (PORT dataa (619:619:619) (720:720:720)) - (PORT datab (545:545:545) (637:637:637)) - (PORT datac (540:540:540) (631:631:631)) - (PORT datad (619:619:619) (706:706:706)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|carry_borrow_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (442:442:442) (522:522:522)) - (PORT datab (758:758:758) (874:874:874)) - (PORT datac (381:381:381) (464:464:464)) - (PORT datad (192:192:192) (224:224:224)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|d1_out) - (DELAY - (ABSOLUTE - (PORT datab (107:107:107) (138:138:138)) - (PORT datac (169:169:169) (201:201:201)) - (PORT datad (132:132:132) (170:170:170)) - (IOPATH datab combout (188:188:188) (181:181:181)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (911:911:911) (918:918:918)) - (PORT asdata (747:747:747) (829:829:829)) - (PORT ena (422:422:422) (454:454:454)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (911:911:911) (918:918:918)) - (PORT asdata (748:748:748) (829:829:829)) - (PORT ena (669:669:669) (725:725:725)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~45) - (DELAY - (ABSOLUTE - (PORT dataa (222:222:222) (279:279:279)) - (PORT datab (311:311:311) (370:370:370)) - (PORT datad (118:118:118) (155:155:155)) + (PORT dataa (879:879:879) (1048:1048:1048)) + (PORT datab (672:672:672) (779:779:779)) + (PORT datac (966:966:966) (1122:1122:1122)) + (PORT datad (742:742:742) (881:881:881)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[3\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (443:443:443) (510:510:510)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (910:910:910)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (736:736:736) (793:793:793)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (910:910:910)) - (PORT asdata (621:621:621) (686:686:686)) - (PORT ena (660:660:660) (723:723:723)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~48) - (DELAY - (ABSOLUTE - (PORT dataa (322:322:322) (387:387:387)) - (PORT datab (444:444:444) (522:522:522)) - (PORT datad (348:348:348) (407:407:407)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (910:910:910) (918:918:918)) - (PORT asdata (644:644:644) (719:719:719)) - (PORT ena (421:421:421) (449:449:449)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (910:910:910) (918:918:918)) - (PORT asdata (644:644:644) (719:719:719)) - (PORT ena (644:644:644) (698:698:698)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~49) - (DELAY - (ABSOLUTE - (PORT dataa (360:360:360) (433:433:433)) - (PORT datab (131:131:131) (179:179:179)) - (PORT datad (195:195:195) (229:229:229)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[3\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (440:440:440) (507:507:507)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (910:910:910)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (794:794:794) (880:880:880)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (910:910:910)) - (PORT asdata (625:625:625) (689:689:689)) - (PORT ena (631:631:631) (680:680:680)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~41) - (DELAY - (ABSOLUTE - (PORT dataa (493:493:493) (580:580:580)) - (PORT datab (322:322:322) (376:376:376)) - (PORT datac (285:285:285) (331:331:331)) - (PORT datad (877:877:877) (1019:1019:1019)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -15630,47 +4358,89 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~42) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~88) (DELAY (ABSOLUTE - (PORT dataa (532:532:532) (626:626:626)) - (PORT datab (313:313:313) (361:361:361)) - (PORT datac (549:549:549) (639:639:639)) - (PORT datad (490:490:490) (559:559:559)) - (IOPATH dataa combout (159:159:159) (163:163:163)) + (PORT dataa (879:879:879) (1048:1048:1048)) + (PORT datab (983:983:983) (1127:1127:1127)) + (PORT datac (903:903:903) (1076:1076:1076)) + (PORT datad (856:856:856) (1003:1003:1003)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~43) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~36) (DELAY (ABSOLUTE - (PORT dataa (115:115:115) (146:146:146)) - (PORT datab (371:371:371) (440:440:440)) - (PORT datac (91:91:91) (112:112:112)) + (PORT dataa (731:731:731) (871:871:871)) + (PORT datab (770:770:770) (907:907:907)) + (PORT datac (653:653:653) (758:758:758)) (PORT datad (89:89:89) (106:106:106)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~44) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~87) (DELAY (ABSOLUTE - (PORT dataa (281:281:281) (326:326:326)) - (PORT datab (322:322:322) (378:378:378)) - (PORT datac (466:466:466) (543:543:543)) - (PORT datad (317:317:317) (372:372:372)) + (PORT dataa (880:880:880) (1050:1050:1050)) + (PORT datab (751:751:751) (900:900:900)) + (PORT datac (494:494:494) (577:577:577)) + (PORT datad (858:858:858) (1005:1005:1005)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~26) + (DELAY + (ABSOLUTE + (PORT dataa (108:108:108) (141:141:141)) + (PORT datab (107:107:107) (138:138:138)) + (PORT datad (103:103:103) (120:120:120)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~9) + (DELAY + (ABSOLUTE + (PORT datab (945:945:945) (1116:1116:1116)) + (PORT datac (807:807:807) (943:943:943)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1579:1579:1579) (1819:1819:1819)) + (PORT datab (532:532:532) (626:626:626)) + (PORT datac (1152:1152:1152) (1348:1348:1348)) + (PORT datad (597:597:597) (685:685:685)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -15678,31 +4448,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~45) + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~42) (DELAY (ABSOLUTE - (PORT dataa (345:345:345) (412:412:412)) - (PORT datab (350:350:350) (409:409:409)) - (PORT datac (661:661:661) (758:758:758)) - (PORT datad (311:311:311) (362:362:362)) + (PORT dataa (103:103:103) (133:133:133)) + (PORT datab (102:102:102) (131:131:131)) + (PORT datac (319:319:319) (368:368:368)) + (PORT datad (94:94:94) (113:113:113)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~46) - (DELAY - (ABSOLUTE - (PORT dataa (108:108:108) (142:142:142)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (327:327:327) (384:384:384)) - (PORT datad (96:96:96) (115:115:115)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -15710,407 +4464,59 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_48) + (INSTANCE z80_\|pla_decode_\|Equal40\~2) (DELAY (ABSOLUTE - (PORT datab (790:790:790) (915:915:915)) - (PORT datac (670:670:670) (778:778:778)) - (PORT datad (466:466:466) (542:542:542)) - (IOPATH datab combout (166:166:166) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_44) - (DELAY - (ABSOLUTE - (PORT datab (791:791:791) (916:916:916)) - (PORT datac (674:674:674) (783:783:783)) - (PORT datad (465:465:465) (533:533:533)) - (IOPATH datab combout (166:166:166) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_45) - (DELAY - (ABSOLUTE - (PORT datab (789:789:789) (914:914:914)) - (PORT datac (665:665:665) (773:773:773)) - (PORT datad (465:465:465) (533:533:533)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (548:548:548) (616:616:616)) - (PORT ena (515:515:515) (556:556:556)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_49) - (DELAY - (ABSOLUTE - (PORT datab (789:789:789) (914:914:914)) - (PORT datac (666:666:666) (774:774:774)) - (PORT datad (468:468:468) (544:544:544)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (551:551:551) (620:620:620)) - (PORT ena (506:506:506) (537:537:537)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~40) - (DELAY - (ABSOLUTE - (PORT dataa (256:256:256) (309:309:309)) - (PORT datab (268:268:268) (320:320:320)) - (PORT datad (118:118:118) (155:155:155)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_52) - (DELAY - (ABSOLUTE - (PORT datab (790:790:790) (915:915:915)) - (PORT datac (669:669:669) (777:777:777)) - (PORT datad (578:578:578) (662:662:662)) - (IOPATH datab combout (166:166:166) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_57) - (DELAY - (ABSOLUTE - (PORT datab (791:791:791) (916:916:916)) - (PORT datac (673:673:673) (782:782:782)) - (PORT datad (549:549:549) (646:646:646)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (623:623:623) (692:692:692)) - (PORT ena (759:759:759) (842:842:842)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_53) - (DELAY - (ABSOLUTE - (PORT datab (791:791:791) (916:916:916)) - (PORT datac (672:672:672) (781:781:781)) - (PORT datad (578:578:578) (661:661:661)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (625:625:625) (694:694:694)) - (PORT ena (753:753:753) (845:845:845)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_56) - (DELAY - (ABSOLUTE - (PORT datab (793:793:793) (918:918:918)) - (PORT datac (678:678:678) (788:788:788)) - (PORT datad (547:547:547) (644:644:644)) - (IOPATH datab combout (166:166:166) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~41) - (DELAY - (ABSOLUTE - (PORT dataa (510:510:510) (624:624:624)) - (PORT datab (130:130:130) (178:178:178)) - (PORT datad (498:498:498) (596:596:596)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_33) - (DELAY - (ABSOLUTE - (PORT datab (669:669:669) (791:791:791)) - (PORT datac (488:488:488) (577:577:577)) - (PORT datad (488:488:488) (567:567:567)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (638:638:638) (715:715:715)) - (PORT ena (408:408:408) (429:429:429)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[3\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (510:510:510) (609:609:609)) - (PORT datab (669:669:669) (792:792:792)) - (PORT datad (480:480:480) (558:558:558)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~11) - (DELAY - (ABSOLUTE - (PORT dataa (624:624:624) (730:730:730)) - (PORT datab (106:106:106) (136:136:136)) - (PORT datac (1031:1031:1031) (1204:1204:1204)) - (PORT datad (110:110:110) (135:135:135)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~12) - (DELAY - (ABSOLUTE - (PORT dataa (466:466:466) (539:539:539)) - (PORT datab (108:108:108) (138:138:138)) - (PORT datac (339:339:339) (401:401:401)) - (PORT datad (482:482:482) (558:558:558)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_29) - (DELAY - (ABSOLUTE - (PORT dataa (816:816:816) (949:949:949)) - (PORT datac (442:442:442) (513:513:513)) - (PORT datad (617:617:617) (712:712:712)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (911:911:911)) - (PORT asdata (537:537:537) (596:596:596)) - (PORT ena (405:405:405) (422:422:422)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_28) - (DELAY - (ABSOLUTE - (PORT dataa (818:818:818) (952:952:952)) - (PORT datac (443:443:443) (515:515:515)) - (PORT datad (619:619:619) (714:714:714)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~44) - (DELAY - (ABSOLUTE - (PORT dataa (591:591:591) (683:683:683)) - (PORT datab (650:650:650) (752:752:752)) - (PORT datad (129:129:129) (157:157:157)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[3\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (370:370:370) (434:434:434)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_69) - (DELAY - (ABSOLUTE - (PORT datab (613:613:613) (713:713:713)) - (PORT datac (756:756:756) (883:883:883)) - (PORT datad (454:454:454) (522:522:522)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (907:907:907) (912:912:912)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (405:405:405) (422:422:422)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_68\~2) - (DELAY - (ABSOLUTE - (PORT dataa (506:506:506) (605:605:605)) - (PORT datab (669:669:669) (791:791:791)) + (PORT dataa (872:872:872) (1034:1034:1034)) + (PORT datab (869:869:869) (1012:1012:1012)) + (PORT datac (772:772:772) (943:943:943)) + (PORT datad (851:851:851) (994:994:994)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_64\~0) + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~14) (DELAY (ABSOLUTE - (PORT dataa (211:211:211) (264:264:264)) - (PORT datab (506:506:506) (605:605:605)) - (PORT datac (635:635:635) (735:735:735)) - (PORT datad (354:354:354) (415:415:415)) + (PORT dataa (337:337:337) (391:391:391)) + (PORT datab (710:710:710) (835:835:835)) + (PORT datac (1412:1412:1412) (1643:1643:1643)) + (PORT datad (670:670:670) (768:768:768)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal55\~0) + (DELAY + (ABSOLUTE + (PORT dataa (871:871:871) (1032:1032:1032)) + (PORT datac (768:768:768) (938:938:938)) + (PORT datad (852:852:852) (995:995:995)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1069:1069:1069) (1259:1259:1259)) + (PORT datab (1029:1029:1029) (1192:1192:1192)) + (PORT datac (373:373:373) (449:449:449)) + (PORT datad (988:988:988) (1159:1159:1159)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (167:167:167) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -16120,11 +4526,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_69\~2) + (INSTANCE z80_\|pla_decode_\|Equal6\~1) (DELAY (ABSOLUTE - (PORT datac (795:795:795) (928:928:928)) - (PORT datad (618:618:618) (713:713:713)) + (PORT dataa (547:547:547) (663:663:663)) + (PORT datab (841:841:841) (977:977:977)) + (PORT datac (574:574:574) (673:673:673)) + (PORT datad (930:930:930) (1100:1100:1100)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -16132,13 +4542,73 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_65\~0) + (INSTANCE z80_\|execute_\|setM1\~36) (DELAY (ABSOLUTE - (PORT dataa (653:653:653) (764:764:764)) - (PORT datab (431:431:431) (504:504:504)) - (PORT datac (626:626:626) (722:722:722)) - (PORT datad (370:370:370) (430:430:430)) + (PORT dataa (1122:1122:1122) (1294:1294:1294)) + (PORT datab (1424:1424:1424) (1662:1662:1662)) + (PORT datac (508:508:508) (582:582:582)) + (PORT datad (673:673:673) (771:771:771)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|comb\~1) + (DELAY + (ABSOLUTE + (PORT datab (629:629:629) (763:763:763)) + (PORT datad (870:870:870) (1009:1009:1009)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~13) + (DELAY + (ABSOLUTE + (PORT dataa (600:600:600) (688:688:688)) + (PORT datab (938:938:938) (1111:1111:1111)) + (PORT datac (1169:1169:1169) (1375:1375:1375)) + (PORT datad (491:491:491) (568:568:568)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (749:749:749) (861:861:861)) + (PORT datab (378:378:378) (450:450:450)) + (PORT datac (526:526:526) (623:623:623)) + (PORT datad (363:363:363) (435:435:435)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal24\~0) + (DELAY + (ABSOLUTE + (PORT dataa (965:965:965) (1146:1146:1146)) + (PORT datab (357:357:357) (419:419:419)) + (PORT datac (1204:1204:1204) (1405:1405:1405)) + (PORT datad (354:354:354) (425:425:425)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -16147,29 +4617,79 @@ ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[3\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~26) (DELAY (ABSOLUTE - (PORT clk (907:907:907) (912:912:912)) - (PORT asdata (810:810:810) (913:913:913)) - (PORT ena (582:582:582) (618:618:618)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (PORT dataa (938:938:938) (1101:1101:1101)) + (PORT datab (1166:1166:1166) (1363:1363:1363)) + (PORT datac (730:730:730) (863:863:863)) + (PORT datad (370:370:370) (436:436:436)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_68) + (INSTANCE z80_\|execute_\|setM1\~37) (DELAY (ABSOLUTE - (PORT datab (613:613:613) (713:713:713)) - (PORT datac (756:756:756) (883:883:883)) - (PORT datad (453:453:453) (522:522:522)) + (PORT dataa (784:784:784) (903:903:903)) + (PORT datab (101:101:101) (130:130:130)) + (PORT datac (334:334:334) (383:383:383)) + (PORT datad (102:102:102) (118:118:118)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~6) + (DELAY + (ABSOLUTE + (PORT dataa (117:117:117) (148:148:148)) + (PORT datab (334:334:334) (386:386:386)) + (PORT datac (438:438:438) (502:502:502)) + (PORT datad (340:340:340) (387:387:387)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\~38) + (DELAY + (ABSOLUTE + (PORT dataa (399:399:399) (476:476:476)) + (PORT datab (1033:1033:1033) (1196:1196:1196)) + (PORT datac (727:727:727) (828:828:828)) + (PORT datad (517:517:517) (604:604:604)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~7) + (DELAY + (ABSOLUTE + (PORT dataa (836:836:836) (969:969:969)) + (PORT datab (118:118:118) (148:148:148)) + (PORT datac (493:493:493) (564:564:564)) + (PORT datad (97:97:97) (117:117:117)) + (IOPATH dataa combout (166:166:166) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -16178,28 +4698,587 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~43) + (INSTANCE z80_\|execute_\|ctl_mRead\~12) (DELAY (ABSOLUTE - (PORT dataa (199:199:199) (257:257:257)) - (PORT datab (483:483:483) (564:564:564)) - (PORT datad (193:193:193) (221:221:221)) + (PORT dataa (671:671:671) (794:794:794)) + (PORT datab (549:549:549) (648:648:648)) + (PORT datad (900:900:900) (1019:1019:1019)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~31) + (DELAY + (ABSOLUTE + (PORT dataa (512:512:512) (601:601:601)) + (PORT datab (708:708:708) (849:849:849)) + (PORT datac (366:366:366) (434:434:434)) + (PORT datad (1154:1154:1154) (1356:1356:1356)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla38pla13M4T2_4) + (DELAY + (ABSOLUTE + (PORT dataa (498:498:498) (589:589:589)) + (PORT datab (509:509:509) (594:594:594)) + (PORT datac (301:301:301) (343:343:343)) + (PORT datad (917:917:917) (1082:1082:1082)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|nM1_int\~2) + (DELAY + (ABSOLUTE + (PORT datac (928:928:928) (1069:1069:1069)) + (PORT datad (1095:1095:1095) (1278:1278:1278)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~0) + (DELAY + (ABSOLUTE + (PORT datab (1004:1004:1004) (1166:1166:1166)) + (PORT datad (699:699:699) (821:821:821)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (549:549:549) (646:646:646)) + (PORT datab (481:481:481) (554:554:554)) + (PORT datac (648:648:648) (741:741:741)) + (PORT datad (364:364:364) (436:436:436)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~6) + (DELAY + (ABSOLUTE + (PORT dataa (330:330:330) (381:381:381)) + (PORT datab (521:521:521) (604:604:604)) + (PORT datac (364:364:364) (428:428:428)) + (PORT datad (109:109:109) (128:128:128)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~12) + (DELAY + (ABSOLUTE + (PORT dataa (542:542:542) (649:649:649)) + (PORT datab (692:692:692) (804:804:804)) + (PORT datac (905:905:905) (1065:1065:1065)) + (PORT datad (726:726:726) (843:843:843)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (917:917:917) (1079:1079:1079)) + (PORT datab (725:725:725) (823:823:823)) + (PORT datac (100:100:100) (126:126:126)) + (PORT datad (784:784:784) (917:917:917)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal25\~0) + (DELAY + (ABSOLUTE + (PORT dataa (797:797:797) (952:952:952)) + (PORT datab (934:934:934) (1106:1106:1106)) + (PORT datac (925:925:925) (1089:1089:1089)) + (PORT datad (485:485:485) (562:562:562)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal12\~1) + (DELAY + (ABSOLUTE + (PORT dataa (547:547:547) (663:663:663)) + (PORT datab (837:837:837) (973:973:973)) + (PORT datac (1203:1203:1203) (1403:1403:1403)) + (PORT datad (936:936:936) (1107:1107:1107)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~38) + (DELAY + (ABSOLUTE + (PORT dataa (782:782:782) (892:892:892)) + (PORT datab (1106:1106:1106) (1290:1290:1290)) + (PORT datac (330:330:330) (389:389:389)) + (PORT datad (107:107:107) (127:127:127)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~82) + (DELAY + (ABSOLUTE + (PORT dataa (713:713:713) (856:856:856)) + (PORT datab (848:848:848) (982:982:982)) + (PORT datad (831:831:831) (975:975:975)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (665:665:665) (784:784:784)) + (PORT datab (328:328:328) (388:388:388)) + (PORT datac (325:325:325) (375:375:375)) + (PORT datad (340:340:340) (392:392:392)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (223:223:223)) + (PORT datab (809:809:809) (944:944:944)) + (PORT datac (103:103:103) (124:124:124)) + (PORT datad (94:94:94) (114:114:114)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~32) + (DELAY + (ABSOLUTE + (PORT dataa (120:120:120) (152:152:152)) + (PORT datab (119:119:119) (148:148:148)) + (PORT datac (926:926:926) (1053:1053:1053)) + (PORT datad (325:325:325) (377:377:377)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~77) + (DELAY + (ABSOLUTE + (PORT dataa (726:726:726) (826:826:826)) + (PORT datab (873:873:873) (1035:1035:1035)) + (PORT datac (465:465:465) (526:526:526)) + (PORT datad (1144:1144:1144) (1289:1289:1289)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal29\~0) + (DELAY + (ABSOLUTE + (PORT dataa (749:749:749) (879:879:879)) + (PORT datab (497:497:497) (568:568:568)) + (PORT datac (412:412:412) (514:514:514)) + (PORT datad (1005:1005:1005) (1164:1164:1164)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~78) + (DELAY + (ABSOLUTE + (PORT dataa (725:725:725) (825:825:825)) + (PORT datab (872:872:872) (1034:1034:1034)) + (PORT datac (88:88:88) (109:109:109)) + (PORT datad (601:601:601) (690:690:690)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~79) + (DELAY + (ABSOLUTE + (PORT dataa (119:119:119) (150:150:150)) + (PORT datab (1255:1255:1255) (1462:1462:1462)) + (PORT datac (476:476:476) (552:552:552)) + (PORT datad (1093:1093:1093) (1268:1268:1268)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~14) + (DELAY + (ABSOLUTE + (PORT dataa (547:547:547) (663:663:663)) + (PORT datab (352:352:352) (414:414:414)) + (PORT datac (650:650:650) (761:761:761)) + (PORT datad (356:356:356) (418:418:418)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~49) + (DELAY + (ABSOLUTE + (PORT dataa (894:894:894) (1038:1038:1038)) + (PORT datab (690:690:690) (805:805:805)) + (PORT datac (592:592:592) (706:706:706)) + (PORT datad (1391:1391:1391) (1624:1624:1624)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (537:537:537) (620:620:620)) + (PORT datab (529:529:529) (623:623:623)) + (PORT datac (1567:1567:1567) (1797:1797:1797)) + (PORT datad (1392:1392:1392) (1625:1625:1625)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~40) + (DELAY + (ABSOLUTE + (PORT dataa (822:822:822) (939:939:939)) + (PORT datab (110:110:110) (142:142:142)) + (PORT datac (98:98:98) (124:124:124)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~5) + (DELAY + (ABSOLUTE + (PORT dataa (670:670:670) (793:793:793)) + (PORT datab (1012:1012:1012) (1146:1146:1146)) + (PORT datac (494:494:494) (578:578:578)) + (PORT datad (530:530:530) (624:624:624)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~44) + (DELAY + (ABSOLUTE + (PORT dataa (352:352:352) (412:412:412)) + (PORT datab (264:264:264) (331:331:331)) + (PORT datac (304:304:304) (345:345:345)) + (PORT datad (246:246:246) (304:304:304)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~36) + (DELAY + (ABSOLUTE + (PORT dataa (655:655:655) (767:767:767)) + (PORT datab (458:458:458) (528:528:528)) + (PORT datac (494:494:494) (577:577:577)) + (PORT datad (519:519:519) (608:608:608)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~35) + (DELAY + (ABSOLUTE + (PORT dataa (694:694:694) (804:804:804)) + (PORT datab (632:632:632) (734:734:734)) + (PORT datad (334:334:334) (387:387:387)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~46) + (DELAY + (ABSOLUTE + (PORT dataa (1006:1006:1006) (1179:1179:1179)) + (PORT datab (102:102:102) (131:131:131)) + (PORT datac (945:945:945) (1093:1093:1093)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~33) + (DELAY + (ABSOLUTE + (PORT dataa (656:656:656) (749:749:749)) + (PORT datab (533:533:533) (613:613:613)) + (PORT datac (788:788:788) (915:915:915)) + (PORT datad (345:345:345) (404:404:404)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~47) + (DELAY + (ABSOLUTE + (PORT dataa (859:859:859) (1005:1005:1005)) + (PORT datab (660:660:660) (766:766:766)) + (PORT datac (645:645:645) (734:734:734)) + (PORT datad (1423:1423:1423) (1648:1648:1648)) (IOPATH dataa combout (166:166:166) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_76\~0) + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla9M1T5_2) (DELAY (ABSOLUTE - (PORT dataa (215:215:215) (268:268:268)) - (PORT datab (779:779:779) (899:899:899)) - (PORT datac (628:628:628) (727:727:727)) - (PORT datad (351:351:351) (412:412:412)) + (PORT dataa (594:594:594) (702:702:702)) + (PORT datab (937:937:937) (1060:1060:1060)) + (PORT datac (478:478:478) (575:575:575)) + (PORT datad (527:527:527) (624:624:624)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~45) + (DELAY + (ABSOLUTE + (PORT dataa (538:538:538) (621:621:621)) + (PORT datab (1015:1015:1015) (1192:1192:1192)) + (PORT datac (913:913:913) (1077:1077:1077)) + (PORT datad (1021:1021:1021) (1184:1184:1184)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~34) + (DELAY + (ABSOLUTE + (PORT dataa (513:513:513) (593:593:593)) + (PORT datab (535:535:535) (628:628:628)) + (PORT datac (926:926:926) (1045:1045:1045)) + (PORT datad (333:333:333) (387:387:387)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla10M5T4_2) + (DELAY + (ABSOLUTE + (PORT dataa (660:660:660) (771:771:771)) + (PORT datac (736:736:736) (872:872:872)) + (PORT datad (996:996:996) (1166:1166:1166)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~6) + (DELAY + (ABSOLUTE + (PORT dataa (547:547:547) (663:663:663)) + (PORT datab (611:611:611) (703:703:703)) + (PORT datac (333:333:333) (390:390:390)) + (PORT datad (932:932:932) (1102:1102:1102)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~50) + (DELAY + (ABSOLUTE + (PORT dataa (624:624:624) (730:730:730)) + (PORT datab (538:538:538) (635:635:635)) + (PORT datac (542:542:542) (652:652:652)) + (PORT datad (742:742:742) (865:865:865)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (194:194:194) (243:243:243)) + (PORT datab (201:201:201) (242:242:242)) + (PORT datac (706:706:706) (844:844:844)) + (PORT datad (102:102:102) (120:120:120)) (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -16209,15 +5288,3019 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_77\~0) + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~48) (DELAY (ABSOLUTE - (PORT dataa (633:633:633) (737:737:737)) - (PORT datab (432:432:432) (506:506:506)) - (PORT datac (632:632:632) (729:729:729)) - (PORT datad (375:375:375) (435:435:435)) + (PORT dataa (178:178:178) (221:221:221)) + (PORT datab (497:497:497) (601:601:601)) + (PORT datac (462:462:462) (545:545:545)) + (PORT datad (525:525:525) (621:621:621)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~49) + (DELAY + (ABSOLUTE + (PORT dataa (559:559:559) (672:672:672)) + (PORT datab (380:380:380) (454:454:454)) + (PORT datac (656:656:656) (777:777:777)) + (PORT datad (835:835:835) (986:986:986)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~7) + (DELAY + (ABSOLUTE + (PORT dataa (499:499:499) (589:589:589)) + (PORT datab (507:507:507) (591:591:591)) + (PORT datad (916:916:916) (1080:1080:1080)) (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~29) + (DELAY + (ABSOLUTE + (PORT dataa (549:549:549) (655:655:655)) + (PORT datab (835:835:835) (957:957:957)) + (PORT datac (555:555:555) (632:632:632)) + (PORT datad (931:931:931) (1071:1071:1071)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~11) + (DELAY + (ABSOLUTE + (PORT dataa (116:116:116) (147:147:147)) + (PORT datab (129:129:129) (157:157:157)) + (PORT datac (1352:1352:1352) (1564:1564:1564)) + (PORT datad (560:560:560) (665:665:665)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~27) + (DELAY + (ABSOLUTE + (PORT dataa (770:770:770) (876:876:876)) + (PORT datab (332:332:332) (392:392:392)) + (PORT datac (521:521:521) (613:613:613)) + (PORT datad (214:214:214) (260:260:260)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~44) + (DELAY + (ABSOLUTE + (PORT dataa (507:507:507) (593:593:593)) + (PORT datab (528:528:528) (616:616:616)) + (PORT datac (1060:1060:1060) (1239:1239:1239)) + (PORT datad (1053:1053:1053) (1234:1234:1234)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~28) + (DELAY + (ABSOLUTE + (PORT dataa (117:117:117) (149:149:149)) + (PORT datab (202:202:202) (238:238:238)) + (PORT datad (454:454:454) (514:514:514)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~30) + (DELAY + (ABSOLUTE + (PORT dataa (495:495:495) (578:578:578)) + (PORT datab (441:441:441) (505:505:505)) + (PORT datad (471:471:471) (544:544:544)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~3) + (DELAY + (ABSOLUTE + (PORT dataa (745:745:745) (875:875:875)) + (PORT datab (1099:1099:1099) (1289:1289:1289)) + (PORT datac (406:406:406) (506:506:506)) + (PORT datad (447:447:447) (516:516:516)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~3) + (DELAY + (ABSOLUTE + (PORT dataa (398:398:398) (483:483:483)) + (PORT datab (593:593:593) (718:718:718)) + (PORT datac (702:702:702) (837:837:837)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~37) + (DELAY + (ABSOLUTE + (PORT dataa (577:577:577) (664:664:664)) + (PORT datab (538:538:538) (632:632:632)) + (PORT datac (684:684:684) (796:796:796)) + (PORT datad (330:330:330) (384:384:384)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~38) + (DELAY + (ABSOLUTE + (PORT dataa (333:333:333) (400:400:400)) + (PORT datab (753:753:753) (896:896:896)) + (PORT datac (489:489:489) (570:570:570)) + (PORT datad (89:89:89) (107:107:107)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~39) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (133:133:133)) + (PORT datab (103:103:103) (131:131:131)) + (PORT datac (91:91:91) (114:114:114)) + (PORT datad (89:89:89) (106:106:106)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~43) + (DELAY + (ABSOLUTE + (PORT dataa (638:638:638) (744:744:744)) + (PORT datab (351:351:351) (407:407:407)) + (PORT datac (645:645:645) (745:745:745)) + (PORT datad (675:675:675) (781:781:781)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~3) + (DELAY + (ABSOLUTE + (PORT dataa (959:959:959) (1113:1113:1113)) + (PORT datab (169:169:169) (227:227:227)) + (PORT datac (1023:1023:1023) (1158:1158:1158)) + (PORT datad (314:314:314) (360:360:360)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~1) + (DELAY + (ABSOLUTE + (PORT dataa (378:378:378) (448:448:448)) + (PORT datab (987:987:987) (1134:1134:1134)) + (PORT datac (370:370:370) (444:444:444)) + (PORT datad (473:473:473) (546:546:546)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~1) + (DELAY + (ABSOLUTE + (PORT datab (631:631:631) (728:728:728)) + (PORT datac (752:752:752) (878:878:878)) + (PORT datad (658:658:658) (773:773:773)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~5) + (DELAY + (ABSOLUTE + (PORT dataa (839:839:839) (969:969:969)) + (PORT datab (582:582:582) (683:683:683)) + (PORT datac (464:464:464) (536:536:536)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~17) + (DELAY + (ABSOLUTE + (PORT dataa (189:189:189) (235:235:235)) + (PORT datab (512:512:512) (598:598:598)) + (PORT datad (341:341:341) (398:398:398)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_iorw\~10) + (DELAY + (ABSOLUTE + (PORT dataa (875:875:875) (1038:1038:1038)) + (PORT datab (813:813:813) (946:946:946)) + (PORT datac (778:778:778) (950:950:950)) + (PORT datad (850:850:850) (994:994:994)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~47) + (DELAY + (ABSOLUTE + (PORT dataa (513:513:513) (599:599:599)) + (PORT datab (519:519:519) (599:599:599)) + (PORT datac (97:97:97) (123:123:123)) + (PORT datad (861:861:861) (965:965:965)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~8) + (DELAY + (ABSOLUTE + (PORT dataa (940:940:940) (1113:1113:1113)) + (PORT datab (935:935:935) (1107:1107:1107)) + (PORT datac (1169:1169:1169) (1376:1376:1376)) + (PORT datad (486:486:486) (563:563:563)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~13) + (DELAY + (ABSOLUTE + (PORT datab (633:633:633) (730:730:730)) + (PORT datac (758:758:758) (884:884:884)) + (PORT datad (657:657:657) (772:772:772)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~48) + (DELAY + (ABSOLUTE + (PORT dataa (355:355:355) (414:414:414)) + (PORT datac (588:588:588) (661:661:661)) + (PORT datad (295:295:295) (334:334:334)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~0) + (DELAY + (ABSOLUTE + (PORT dataa (491:491:491) (571:571:571)) + (PORT datab (819:819:819) (941:941:941)) + (PORT datac (456:456:456) (524:524:524)) + (PORT datad (102:102:102) (120:120:120)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla57M1T4_4) + (DELAY + (ABSOLUTE + (PORT datab (643:643:643) (771:771:771)) + (PORT datac (1370:1370:1370) (1592:1592:1592)) + (PORT datad (757:757:757) (879:879:879)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~9) + (DELAY + (ABSOLUTE + (PORT datac (483:483:483) (580:580:580)) + (PORT datad (524:524:524) (620:620:620)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1425:1425:1425) (1639:1639:1639)) + (PORT datab (954:954:954) (1098:1098:1098)) + (PORT datac (1154:1154:1154) (1324:1324:1324)) + (PORT datad (518:518:518) (599:599:599)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla12M3T1_2) + (DELAY + (ABSOLUTE + (PORT datab (884:884:884) (1024:1024:1024)) + (PORT datac (1008:1008:1008) (1173:1173:1173)) + (PORT datad (548:548:548) (680:680:680)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~9) + (DELAY + (ABSOLUTE + (PORT dataa (641:641:641) (753:753:753)) + (PORT datab (1179:1179:1179) (1348:1348:1348)) + (PORT datac (838:838:838) (985:985:985)) + (PORT datad (464:464:464) (539:539:539)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~2) + (DELAY + (ABSOLUTE + (PORT dataa (762:762:762) (898:898:898)) + (PORT datab (952:952:952) (1096:1096:1096)) + (PORT datac (775:775:775) (894:894:894)) + (PORT datad (701:701:701) (815:815:815)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~10) + (DELAY + (ABSOLUTE + (PORT dataa (495:495:495) (585:585:585)) + (PORT datab (463:463:463) (553:553:553)) + (PORT datac (188:188:188) (221:221:221)) + (PORT datad (347:347:347) (407:407:407)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~10) + (DELAY + (ABSOLUTE + (PORT dataa (520:520:520) (608:608:608)) + (PORT datab (588:588:588) (717:717:717)) + (PORT datac (1001:1001:1001) (1181:1181:1181)) + (PORT datad (610:610:610) (714:714:714)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel_pla11M1T1_11) + (DELAY + (ABSOLUTE + (PORT datab (676:676:676) (800:800:800)) + (PORT datac (667:667:667) (802:802:802)) + (PORT datad (850:850:850) (981:981:981)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~11) + (DELAY + (ABSOLUTE + (PORT dataa (318:318:318) (370:370:370)) + (PORT datab (509:509:509) (585:585:585)) + (PORT datac (813:813:813) (975:975:975)) + (PORT datad (472:472:472) (547:547:547)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~11) + (DELAY + (ABSOLUTE + (PORT dataa (368:368:368) (435:435:435)) + (PORT datab (107:107:107) (137:137:137)) + (PORT datac (493:493:493) (563:563:563)) + (PORT datad (1049:1049:1049) (1221:1221:1221)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~1) + (DELAY + (ABSOLUTE + (PORT datac (102:102:102) (130:130:130)) + (PORT datad (109:109:109) (130:130:130)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~4) + (DELAY + (ABSOLUTE + (PORT datac (703:703:703) (834:834:834)) + (PORT datad (1346:1346:1346) (1562:1562:1562)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~9) + (DELAY + (ABSOLUTE + (PORT dataa (846:846:846) (987:987:987)) + (PORT datab (1077:1077:1077) (1257:1257:1257)) + (PORT datac (717:717:717) (834:834:834)) + (PORT datad (835:835:835) (971:971:971)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~4) + (DELAY + (ABSOLUTE + (PORT dataa (523:523:523) (613:613:613)) + (PORT datab (808:808:808) (923:923:923)) + (PORT datac (673:673:673) (784:784:784)) + (PORT datad (348:348:348) (410:410:410)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~0) + (DELAY + (ABSOLUTE + (PORT dataa (659:659:659) (759:759:759)) + (PORT datab (773:773:773) (898:898:898)) + (PORT datac (908:908:908) (1039:1039:1039)) + (PORT datad (492:492:492) (570:570:570)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (301:301:301) (348:348:348)) + (PORT datab (347:347:347) (414:414:414)) + (PORT datac (349:349:349) (418:418:418)) + (PORT datad (710:710:710) (845:845:845)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~47) + (DELAY + (ABSOLUTE + (PORT dataa (121:121:121) (154:154:154)) + (PORT datab (697:697:697) (810:810:810)) + (PORT datac (846:846:846) (997:997:997)) + (PORT datad (1350:1350:1350) (1573:1573:1573)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~3) + (DELAY + (ABSOLUTE + (PORT dataa (931:931:931) (1067:1067:1067)) + (PORT datab (624:624:624) (751:751:751)) + (PORT datac (548:548:548) (644:644:644)) + (PORT datad (94:94:94) (114:114:114)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~12) + (DELAY + (ABSOLUTE + (PORT dataa (629:629:629) (717:717:717)) + (PORT datab (635:635:635) (735:735:735)) + (PORT datac (207:207:207) (249:249:249)) + (PORT datad (534:534:534) (635:635:635)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~23) + (DELAY + (ABSOLUTE + (PORT dataa (1300:1300:1300) (1496:1496:1496)) + (PORT datab (792:792:792) (939:939:939)) + (PORT datac (357:357:357) (414:414:414)) + (PORT datad (792:792:792) (933:933:933)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1069:1069:1069) (1268:1268:1268)) + (PORT datab (113:113:113) (141:141:141)) + (PORT datac (995:995:995) (1151:1151:1151)) + (PORT datad (368:368:368) (434:434:434)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~13) + (DELAY + (ABSOLUTE + (PORT dataa (308:308:308) (357:357:357)) + (PORT datab (484:484:484) (559:559:559)) + (PORT datac (319:319:319) (373:373:373)) + (PORT datad (537:537:537) (609:609:609)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~4) + (DELAY + (ABSOLUTE + (PORT dataa (725:725:725) (845:845:845)) + (PORT datab (952:952:952) (1095:1095:1095)) + (PORT datac (775:775:775) (893:893:893)) + (PORT datad (1114:1114:1114) (1275:1275:1275)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~1) + (DELAY + (ABSOLUTE + (PORT datac (272:272:272) (310:310:310)) + (PORT datad (327:327:327) (378:378:378)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~29) + (DELAY + (ABSOLUTE + (PORT dataa (619:619:619) (713:713:713)) + (PORT datac (934:934:934) (1099:1099:1099)) + (PORT datad (952:952:952) (1098:1098:1098)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~14) + (DELAY + (ABSOLUTE + (PORT dataa (308:308:308) (366:366:366)) + (PORT datab (102:102:102) (131:131:131)) + (PORT datac (103:103:103) (124:124:124)) + (PORT datad (647:647:647) (750:750:750)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla77M1T1_3) + (DELAY + (ABSOLUTE + (PORT dataa (521:521:521) (608:608:608)) + (PORT datab (589:589:589) (717:717:717)) + (PORT datac (1001:1001:1001) (1182:1182:1182)) + (PORT datad (610:610:610) (714:714:714)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel_pla82M1T1_16) + (DELAY + (ABSOLUTE + (PORT dataa (1232:1232:1232) (1445:1445:1445)) + (PORT datab (700:700:700) (824:824:824)) + (PORT datac (643:643:643) (744:744:744)) + (PORT datad (874:874:874) (995:995:995)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~13) + (DELAY + (ABSOLUTE + (PORT dataa (945:945:945) (1099:1099:1099)) + (PORT datab (518:518:518) (603:603:603)) + (PORT datac (657:657:657) (777:777:777)) + (PORT datad (1101:1101:1101) (1272:1272:1272)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1021:1021:1021) (1193:1193:1193)) + (PORT datab (1373:1373:1373) (1602:1602:1602)) + (PORT datac (538:538:538) (636:636:636)) + (PORT datad (941:941:941) (1064:1064:1064)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT datab (671:671:671) (782:782:782)) + (PORT datac (495:495:495) (570:570:570)) + (PORT datad (94:94:94) (113:113:113)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (223:223:223) (280:280:280)) + (PORT datab (1394:1394:1394) (1623:1623:1623)) + (PORT datac (858:858:858) (999:999:999)) + (PORT datad (105:105:105) (122:122:122)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1125:1125:1125) (1309:1309:1309)) + (PORT datab (861:861:861) (1030:1030:1030)) + (PORT datac (1093:1093:1093) (1264:1264:1264)) + (PORT datad (431:431:431) (493:493:493)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal68\~2) + (DELAY + (ABSOLUTE + (PORT dataa (550:550:550) (669:669:669)) + (PORT datab (557:557:557) (665:665:665)) + (PORT datac (530:530:530) (638:638:638)) + (PORT datad (656:656:656) (777:777:777)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (646:646:646) (747:747:747)) + (PORT datab (908:908:908) (1072:1072:1072)) + (PORT datac (1132:1132:1132) (1331:1331:1331)) + (PORT datad (348:348:348) (410:410:410)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (184:184:184) (222:222:222)) + (PORT datab (173:173:173) (211:211:211)) + (PORT datac (314:314:314) (372:372:372)) + (PORT datad (318:318:318) (369:369:369)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~4) + (DELAY + (ABSOLUTE + (PORT dataa (803:803:803) (949:949:949)) + (PORT datab (741:741:741) (868:868:868)) + (PORT datac (1415:1415:1415) (1646:1646:1646)) + (PORT datad (345:345:345) (401:401:401)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (540:540:540) (628:628:628)) + (PORT datac (102:102:102) (124:124:124)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~20) + (DELAY + (ABSOLUTE + (PORT dataa (1160:1160:1160) (1343:1343:1343)) + (PORT datab (829:829:829) (951:951:951)) + (PORT datac (970:970:970) (1128:1128:1128)) + (PORT datad (940:940:940) (1077:1077:1077)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~9) + (DELAY + (ABSOLUTE + (PORT dataa (316:316:316) (371:371:371)) + (PORT datab (788:788:788) (929:929:929)) + (PORT datac (309:309:309) (353:353:353)) + (PORT datad (313:313:313) (362:362:362)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1024:1024:1024) (1184:1184:1184)) + (PORT datab (926:926:926) (1087:1087:1087)) + (PORT datac (671:671:671) (773:773:773)) + (PORT datad (922:922:922) (1051:1051:1051)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~1) + (DELAY + (ABSOLUTE + (PORT datab (948:948:948) (1091:1091:1091)) + (PORT datac (771:771:771) (888:888:888)) + (PORT datad (702:702:702) (817:817:817)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~10) + (DELAY + (ABSOLUTE + (PORT dataa (747:747:747) (884:884:884)) + (PORT datab (447:447:447) (510:510:510)) + (PORT datac (847:847:847) (1017:1017:1017)) + (PORT datad (600:600:600) (683:683:683)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~2) + (DELAY + (ABSOLUTE + (PORT datab (182:182:182) (218:218:218)) + (PORT datac (1038:1038:1038) (1177:1177:1177)) + (PORT datad (346:346:346) (403:403:403)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1188:1188:1188) (1394:1394:1394)) + (PORT datab (328:328:328) (387:387:387)) + (PORT datac (707:707:707) (846:846:846)) + (PORT datad (210:210:210) (255:255:255)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1196:1196:1196) (1387:1387:1387)) + (PORT datab (1030:1030:1030) (1204:1204:1204)) + (PORT datac (512:512:512) (595:595:595)) + (PORT datad (494:494:494) (568:568:568)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~6) + (DELAY + (ABSOLUTE + (PORT dataa (772:772:772) (877:877:877)) + (PORT datab (115:115:115) (148:148:148)) + (PORT datac (502:502:502) (584:584:584)) + (PORT datad (379:379:379) (446:446:446)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~19) + (DELAY + (ABSOLUTE + (PORT dataa (353:353:353) (414:414:414)) + (PORT datab (978:978:978) (1146:1146:1146)) + (PORT datac (720:720:720) (849:849:849)) + (PORT datad (745:745:745) (865:865:865)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal1\~5) + (DELAY + (ABSOLUTE + (PORT datac (602:602:602) (710:710:710)) + (PORT datad (741:741:741) (863:863:863)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~0) + (DELAY + (ABSOLUTE + (PORT dataa (526:526:526) (616:616:616)) + (PORT datab (954:954:954) (1101:1101:1101)) + (PORT datac (645:645:645) (735:735:735)) + (PORT datad (1027:1027:1027) (1195:1195:1195)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel_pla12M1T1_12\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1006:1006:1006) (1170:1170:1170)) + (PORT datab (1219:1219:1219) (1408:1408:1408)) + (PORT datac (681:681:681) (784:784:784)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~1) + (DELAY + (ABSOLUTE + (PORT dataa (197:197:197) (236:236:236)) + (PORT datab (1219:1219:1219) (1409:1409:1409)) + (PORT datac (93:93:93) (115:115:115)) + (PORT datad (1048:1048:1048) (1242:1242:1242)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~7) + (DELAY + (ABSOLUTE + (PORT dataa (468:468:468) (542:542:542)) + (PORT datab (544:544:544) (670:670:670)) + (PORT datac (399:399:399) (478:478:478)) + (PORT datad (568:568:568) (670:670:670)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~5) + (DELAY + (ABSOLUTE + (PORT dataa (795:795:795) (921:921:921)) + (PORT datab (955:955:955) (1098:1098:1098)) + (PORT datac (956:956:956) (1109:1109:1109)) + (PORT datad (700:700:700) (814:814:814)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~8) + (DELAY + (ABSOLUTE + (PORT dataa (718:718:718) (850:850:850)) + (PORT datab (813:813:813) (956:956:956)) + (PORT datac (951:951:951) (1095:1095:1095)) + (PORT datad (316:316:316) (368:368:368)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~8) + (DELAY + (ABSOLUTE + (PORT dataa (465:465:465) (535:535:535)) + (PORT datab (424:424:424) (483:483:483)) + (PORT datac (284:284:284) (322:322:322)) + (PORT datad (314:314:314) (365:365:365)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~15) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (222:222:222)) + (PORT datab (184:184:184) (220:220:220)) + (PORT datac (164:164:164) (194:194:194)) + (PORT datad (169:169:169) (199:199:199)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~7) + (DELAY + (ABSOLUTE + (PORT dataa (492:492:492) (566:566:566)) + (PORT datab (200:200:200) (242:242:242)) + (PORT datac (363:363:363) (433:433:433)) + (PORT datad (195:195:195) (231:231:231)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~12) + (DELAY + (ABSOLUTE + (PORT dataa (214:214:214) (262:262:262)) + (PORT datab (117:117:117) (146:146:146)) + (PORT datac (825:825:825) (979:979:979)) + (PORT datad (686:686:686) (808:808:808)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~9) + (DELAY + (ABSOLUTE + (PORT dataa (872:872:872) (1039:1039:1039)) + (PORT datab (1152:1152:1152) (1329:1329:1329)) + (PORT datac (1194:1194:1194) (1384:1384:1384)) + (PORT datad (1078:1078:1078) (1245:1245:1245)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~10) + (DELAY + (ABSOLUTE + (PORT dataa (102:102:102) (133:133:133)) + (PORT datab (785:785:785) (909:909:909)) + (PORT datac (599:599:599) (681:681:681)) + (PORT datad (107:107:107) (126:126:126)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~8) + (DELAY + (ABSOLUTE + (PORT dataa (495:495:495) (580:580:580)) + (PORT datab (855:855:855) (987:987:987)) + (PORT datac (480:480:480) (555:555:555)) + (PORT datad (710:710:710) (845:845:845)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal64\~0) + (DELAY + (ABSOLUTE + (PORT dataa (569:569:569) (688:688:688)) + (PORT datab (363:363:363) (430:430:430)) + (PORT datac (166:166:166) (198:198:198)) + (PORT datad (98:98:98) (119:119:119)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (334:334:334) (387:387:387)) + (PORT datab (1220:1220:1220) (1410:1410:1410)) + (PORT datac (994:994:994) (1150:1150:1150)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal62\~2) + (DELAY + (ABSOLUTE + (PORT dataa (567:567:567) (686:686:686)) + (PORT datab (361:361:361) (428:428:428)) + (PORT datac (168:168:168) (201:201:201)) + (PORT datad (98:98:98) (118:118:118)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (845:845:845) (998:998:998)) + (PORT datab (629:629:629) (745:745:745)) + (PORT datac (113:113:113) (141:141:141)) + (PORT datad (708:708:708) (843:843:843)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~46) + (DELAY + (ABSOLUTE + (PORT dataa (944:944:944) (1094:1094:1094)) + (PORT datab (797:797:797) (906:906:906)) + (PORT datac (338:338:338) (398:398:398)) + (PORT datad (1534:1534:1534) (1760:1760:1760)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (659:659:659) (756:756:756)) + (PORT datab (1547:1547:1547) (1783:1783:1783)) + (PORT datac (928:928:928) (1069:1069:1069)) + (PORT datad (1094:1094:1094) (1278:1278:1278)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~7) + (DELAY + (ABSOLUTE + (PORT dataa (370:370:370) (438:438:438)) + (PORT datab (337:337:337) (399:399:399)) + (PORT datac (623:623:623) (724:724:724)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~11) + (DELAY + (ABSOLUTE + (PORT dataa (382:382:382) (447:447:447)) + (PORT datab (184:184:184) (224:224:224)) + (PORT datac (532:532:532) (613:613:613)) + (PORT datad (98:98:98) (118:118:118)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal62\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1169:1169:1169) (1386:1386:1386)) + (PORT datab (670:670:670) (808:808:808)) + (PORT datac (529:529:529) (615:615:615)) + (PORT datad (690:690:690) (823:823:823)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (683:683:683) (782:782:782)) + (PORT datab (335:335:335) (396:396:396)) + (PORT datac (1238:1238:1238) (1417:1417:1417)) + (PORT datad (627:627:627) (710:710:710)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (115:115:115) (146:146:146)) + (PORT datab (509:509:509) (588:588:588)) + (PORT datac (442:442:442) (501:501:501)) + (PORT datad (645:645:645) (749:749:749)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (108:108:108) (141:141:141)) + (PORT datab (102:102:102) (131:131:131)) + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (102:102:102) (120:120:120)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~9) + (DELAY + (ABSOLUTE + (PORT dataa (306:306:306) (360:360:360)) + (PORT datab (114:114:114) (143:143:143)) + (PORT datac (451:451:451) (515:515:515)) + (PORT datad (333:333:333) (392:392:392)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~6) + (DELAY + (ABSOLUTE + (PORT dataa (532:532:532) (622:622:622)) + (PORT datab (948:948:948) (1087:1087:1087)) + (PORT datac (520:520:520) (602:602:602)) + (PORT datad (354:354:354) (413:413:413)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~7) + (DELAY + (ABSOLUTE + (PORT dataa (534:534:534) (625:625:625)) + (PORT datab (514:514:514) (589:589:589)) + (PORT datac (519:519:519) (601:601:601)) + (PORT datad (102:102:102) (120:120:120)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~1) + (DELAY + (ABSOLUTE + (PORT dataa (321:321:321) (374:374:374)) + (PORT datab (709:709:709) (824:824:824)) + (PORT datac (618:618:618) (706:706:706)) + (PORT datad (293:293:293) (325:325:325)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (528:528:528) (606:606:606)) + (PORT datab (706:706:706) (814:814:814)) + (PORT datac (689:689:689) (807:807:807)) + (PORT datad (504:504:504) (582:582:582)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~4) + (DELAY + (ABSOLUTE + (PORT dataa (510:510:510) (597:597:597)) + (PORT datab (370:370:370) (435:435:435)) + (PORT datac (937:937:937) (1076:1076:1076)) + (PORT datad (594:594:594) (684:684:684)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~5) + (DELAY + (ABSOLUTE + (PORT dataa (511:511:511) (598:598:598)) + (PORT datab (608:608:608) (707:707:707)) + (PORT datac (498:498:498) (571:571:571)) + (PORT datad (103:103:103) (120:120:120)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~2) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (482:482:482) (555:555:555)) + (PORT datac (647:647:647) (745:745:745)) + (PORT datad (304:304:304) (347:347:347)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla21M2T3_4) + (DELAY + (ABSOLUTE + (PORT dataa (535:535:535) (634:634:634)) + (PORT datab (942:942:942) (1071:1071:1071)) + (PORT datac (529:529:529) (634:634:634)) + (PORT datad (375:375:375) (438:438:438)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~6) + (DELAY + (ABSOLUTE + (PORT dataa (336:336:336) (393:393:393)) + (PORT datab (974:974:974) (1160:1160:1160)) + (PORT datac (793:793:793) (935:935:935)) + (PORT datad (164:164:164) (192:192:192)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~12) + (DELAY + (ABSOLUTE + (PORT dataa (547:547:547) (641:641:641)) + (PORT datab (383:383:383) (455:455:455)) + (PORT datac (792:792:792) (933:933:933)) + (PORT datad (377:377:377) (450:450:450)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (580:580:580) (658:658:658)) + (PORT datab (718:718:718) (816:816:816)) + (PORT datac (1038:1038:1038) (1176:1176:1176)) + (PORT datad (337:337:337) (391:391:391)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~3) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (222:222:222)) + (PORT datab (447:447:447) (521:521:521)) + (PORT datac (94:94:94) (118:118:118)) + (PORT datad (335:335:335) (384:384:384)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_high) + (DELAY + (ABSOLUTE + (PORT dataa (1258:1258:1258) (1459:1459:1459)) + (PORT datab (1062:1062:1062) (1238:1238:1238)) + (PORT datac (278:278:278) (318:318:318)) + (PORT datad (709:709:709) (831:831:831)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero\~4) + (DELAY + (ABSOLUTE + (PORT dataa (705:705:705) (829:829:829)) + (PORT datab (887:887:887) (1017:1017:1017)) + (PORT datac (643:643:643) (744:744:744)) + (PORT datad (939:939:939) (1091:1091:1091)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~12) + (DELAY + (ABSOLUTE + (PORT dataa (888:888:888) (1005:1005:1005)) + (PORT datab (711:711:711) (837:837:837)) + (PORT datac (1412:1412:1412) (1644:1644:1644)) + (PORT datad (494:494:494) (566:566:566)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal61\~2) + (DELAY + (ABSOLUTE + (PORT dataa (877:877:877) (1039:1039:1039)) + (PORT datab (872:872:872) (1016:1016:1016)) + (PORT datac (780:780:780) (953:953:953)) + (PORT datad (850:850:850) (993:993:993)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~4) + (DELAY + (ABSOLUTE + (PORT dataa (708:708:708) (833:833:833)) + (PORT datab (703:703:703) (827:827:827)) + (PORT datac (607:607:607) (704:704:704)) + (PORT datad (335:335:335) (385:385:385)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~13) + (DELAY + (ABSOLUTE + (PORT dataa (846:846:846) (987:987:987)) + (PORT datab (617:617:617) (701:701:701)) + (PORT datac (569:569:569) (645:645:645)) + (PORT datad (394:394:394) (483:483:483)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~14) + (DELAY + (ABSOLUTE + (PORT dataa (627:627:627) (718:718:718)) + (PORT datab (463:463:463) (535:535:535)) + (PORT datac (462:462:462) (537:537:537)) + (PORT datad (870:870:870) (984:984:984)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~18) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (403:403:403)) + (PORT datab (980:980:980) (1148:1148:1148)) + (PORT datac (724:724:724) (853:853:853)) + (PORT datad (744:744:744) (864:864:864)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~10) + (DELAY + (ABSOLUTE + (PORT dataa (338:338:338) (396:396:396)) + (PORT datab (685:685:685) (797:797:797)) + (PORT datac (405:405:405) (456:456:456)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~2) + (DELAY + (ABSOLUTE + (PORT datab (320:320:320) (365:365:365)) + (PORT datac (332:332:332) (389:389:389)) + (PORT datad (1023:1023:1023) (1171:1171:1171)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1164:1164:1164) (1380:1380:1380)) + (PORT datab (685:685:685) (800:800:800)) + (PORT datad (653:653:653) (746:746:746)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~3) + (DELAY + (ABSOLUTE + (PORT dataa (528:528:528) (615:615:615)) + (PORT datab (711:711:711) (826:826:826)) + (PORT datac (1603:1603:1603) (1841:1841:1841)) + (PORT datad (759:759:759) (873:873:873)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~26) + (DELAY + (ABSOLUTE + (PORT dataa (590:590:590) (682:682:682)) + (PORT datab (721:721:721) (837:837:837)) + (PORT datac (624:624:624) (724:724:724)) + (PORT datad (876:876:876) (1028:1028:1028)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (136:136:136)) + (PORT datab (102:102:102) (131:131:131)) + (PORT datac (109:109:109) (133:133:133)) + (PORT datad (102:102:102) (119:119:119)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_lo\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1260:1260:1260) (1474:1474:1474)) + (PORT datab (412:412:412) (501:501:501)) + (PORT datac (1014:1014:1014) (1179:1179:1179)) + (PORT datad (532:532:532) (653:653:653)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (527:527:527) (617:617:617)) + (PORT datab (468:468:468) (546:546:546)) + (PORT datac (1243:1243:1243) (1435:1435:1435)) + (PORT datad (962:962:962) (1116:1116:1116)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_oe\~1) + (DELAY + (ABSOLUTE + (PORT dataa (538:538:538) (646:646:646)) + (PORT datab (472:472:472) (551:551:551)) + (PORT datac (521:521:521) (608:608:608)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~6) + (DELAY + (ABSOLUTE + (PORT dataa (477:477:477) (553:553:553)) + (PORT datab (913:913:913) (1059:1059:1059)) + (PORT datac (501:501:501) (583:583:583)) + (PORT datad (748:748:748) (848:848:848)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~12) + (DELAY + (ABSOLUTE + (PORT dataa (868:868:868) (1039:1039:1039)) + (PORT datab (517:517:517) (609:609:609)) + (PORT datac (807:807:807) (943:943:943)) + (PORT datad (1051:1051:1051) (1200:1200:1200)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~8) + (DELAY + (ABSOLUTE + (PORT dataa (114:114:114) (151:151:151)) + (PORT datac (561:561:561) (638:638:638)) + (PORT datad (341:341:341) (404:404:404)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~9) + (DELAY + (ABSOLUTE + (PORT dataa (507:507:507) (593:593:593)) + (PORT datab (811:811:811) (942:942:942)) + (PORT datac (512:512:512) (595:595:595)) + (PORT datad (902:902:902) (1037:1037:1037)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe) + (DELAY + (ABSOLUTE + (PORT dataa (109:109:109) (142:142:142)) + (PORT datab (913:913:913) (1060:1060:1060)) + (PORT datac (712:712:712) (824:824:824)) + (PORT datad (96:96:96) (117:117:117)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (357:357:357) (429:429:429)) + (PORT datab (803:803:803) (953:953:953)) + (PORT datac (1244:1244:1244) (1436:1436:1436)) + (PORT datad (755:755:755) (852:852:852)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (132:132:132) (163:163:163)) + (PORT datab (866:866:866) (980:980:980)) + (PORT datac (280:280:280) (321:321:321)) + (PORT datad (117:117:117) (142:142:142)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla83M1T3_2) + (DELAY + (ABSOLUTE + (PORT dataa (525:525:525) (616:616:616)) + (PORT datab (1060:1060:1060) (1220:1220:1220)) + (PORT datac (649:649:649) (740:740:740)) + (PORT datad (939:939:939) (1076:1076:1076)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~15) + (DELAY + (ABSOLUTE + (PORT dataa (914:914:914) (1046:1046:1046)) + (PORT datab (838:838:838) (974:974:974)) + (PORT datac (348:348:348) (402:402:402)) + (PORT datad (529:529:529) (622:622:622)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~38) + (DELAY + (ABSOLUTE + (PORT dataa (547:547:547) (642:642:642)) + (PORT datab (824:824:824) (948:948:948)) + (PORT datac (796:796:796) (944:944:944)) + (PORT datad (495:495:495) (577:577:577)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~28) + (DELAY + (ABSOLUTE + (PORT dataa (525:525:525) (615:615:615)) + (PORT datab (952:952:952) (1100:1100:1100)) + (PORT datac (648:648:648) (739:739:739)) + (PORT datad (1288:1288:1288) (1476:1476:1476)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~6) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (380:380:380) (446:446:446)) + (PORT datac (467:467:467) (546:546:546)) + (PORT datad (112:112:112) (134:134:134)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~37) + (DELAY + (ABSOLUTE + (PORT dataa (1281:1281:1281) (1476:1476:1476)) + (PORT datab (928:928:928) (1071:1071:1071)) + (PORT datac (333:333:333) (393:393:393)) + (PORT datad (500:500:500) (588:588:588)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~39) + (DELAY + (ABSOLUTE + (PORT dataa (646:646:646) (747:747:747)) + (PORT datab (276:276:276) (323:323:323)) + (PORT datac (307:307:307) (352:352:352)) + (PORT datad (875:875:875) (1027:1027:1027)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_daa) + (DELAY + (ABSOLUTE + (PORT dataa (1203:1203:1203) (1403:1403:1403)) + (PORT datab (493:493:493) (576:576:576)) + (PORT datac (1001:1001:1001) (1181:1181:1181)) + (PORT datad (610:610:610) (714:714:714)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~7) + (DELAY + (ABSOLUTE + (PORT dataa (226:226:226) (283:283:283)) + (PORT datab (329:329:329) (388:388:388)) + (PORT datac (950:950:950) (1093:1093:1093)) + (PORT datad (1297:1297:1297) (1494:1494:1494)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~8) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (1307:1307:1307) (1513:1513:1513)) + (PORT datac (487:487:487) (571:571:571)) + (PORT datad (104:104:104) (121:121:121)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~30) + (DELAY + (ABSOLUTE + (PORT dataa (994:994:994) (1164:1164:1164)) + (PORT datab (530:530:530) (620:620:620)) + (PORT datac (956:956:956) (1109:1109:1109)) + (PORT datad (585:585:585) (701:701:701)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~31) + (DELAY + (ABSOLUTE + (PORT datab (325:325:325) (376:376:376)) + (PORT datac (458:458:458) (526:526:526)) + (PORT datad (291:291:291) (329:329:329)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~25) + (DELAY + (ABSOLUTE + (PORT datac (961:961:961) (1102:1102:1102)) + (PORT datad (339:339:339) (407:407:407)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~40) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (427:427:427)) + (PORT datab (783:783:783) (898:898:898)) + (PORT datac (819:819:819) (934:934:934)) + (PORT datad (451:451:451) (525:525:525)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~42) + (DELAY + (ABSOLUTE + (PORT dataa (111:111:111) (144:144:144)) + (PORT datab (335:335:335) (393:393:393)) + (PORT datac (446:446:446) (512:512:512)) + (PORT datad (89:89:89) (106:106:106)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla65npla52M1T4_4) + (DELAY + (ABSOLUTE + (PORT dataa (774:774:774) (904:904:904)) + (PORT datab (840:840:840) (996:996:996)) + (PORT datac (437:437:437) (498:498:498)) + (PORT datad (686:686:686) (809:809:809)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~4) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (436:436:436)) + (PORT datab (388:388:388) (462:462:462)) + (PORT datac (517:517:517) (603:603:603)) + (PORT datad (336:336:336) (391:391:391)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~47) + (DELAY + (ABSOLUTE + (PORT dataa (1297:1297:1297) (1496:1496:1496)) + (PORT datab (497:497:497) (580:580:580)) + (PORT datac (863:863:863) (1015:1015:1015)) + (PORT datad (1078:1078:1078) (1245:1245:1245)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~34) + (DELAY + (ABSOLUTE + (PORT dataa (507:507:507) (592:592:592)) + (PORT datab (391:391:391) (468:468:468)) + (PORT datac (289:289:289) (329:329:329)) + (PORT datad (900:900:900) (1035:1035:1035)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~35) + (DELAY + (ABSOLUTE + (PORT dataa (109:109:109) (143:143:143)) + (PORT datab (171:171:171) (210:210:210)) + (PORT datac (688:688:688) (800:800:800)) + (PORT datad (494:494:494) (568:568:568)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~36) + (DELAY + (ABSOLUTE + (PORT dataa (605:605:605) (695:695:695)) + (PORT datab (465:465:465) (533:533:533)) + (PORT datac (317:317:317) (360:360:360)) + (PORT datad (290:290:290) (331:331:331)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~28) + (DELAY + (ABSOLUTE + (PORT dataa (383:383:383) (454:454:454)) + (PORT datab (514:514:514) (600:600:600)) + (PORT datac (648:648:648) (752:752:752)) + (PORT datad (646:646:646) (752:752:752)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~44) + (DELAY + (ABSOLUTE + (PORT dataa (366:366:366) (434:434:434)) + (PORT datab (918:918:918) (1061:1061:1061)) + (PORT datac (826:826:826) (992:992:992)) + (PORT datad (334:334:334) (389:389:389)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~29) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (135:135:135)) + (PORT datac (478:478:478) (547:547:547)) + (PORT datad (93:93:93) (112:112:112)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~16) + (DELAY + (ABSOLUTE + (PORT datac (851:851:851) (1020:1020:1020)) + (PORT datad (604:604:604) (687:687:687)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~27) + (DELAY + (ABSOLUTE + (PORT dataa (116:116:116) (147:147:147)) + (PORT datab (875:875:875) (989:989:989)) + (PORT datac (102:102:102) (123:123:123)) + (PORT datad (171:171:171) (198:198:198)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~10) + (DELAY + (ABSOLUTE + (PORT dataa (113:113:113) (148:148:148)) + (PORT datab (108:108:108) (139:139:139)) + (PORT datac (562:562:562) (640:640:640)) + (PORT datad (342:342:342) (406:406:406)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~31) + (DELAY + (ABSOLUTE + (PORT dataa (1098:1098:1098) (1280:1280:1280)) + (PORT datab (1263:1263:1263) (1471:1471:1471)) + (PORT datac (209:209:209) (251:251:251)) + (PORT datad (349:349:349) (410:410:410)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~30) + (DELAY + (ABSOLUTE + (PORT dataa (719:719:719) (846:846:846)) + (PORT datab (745:745:745) (872:872:872)) + (PORT datac (494:494:494) (565:565:565)) + (PORT datad (343:343:343) (399:399:399)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~32) + (DELAY + (ABSOLUTE + (PORT dataa (1436:1436:1436) (1668:1668:1668)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (1242:1242:1242) (1449:1449:1449)) + (PORT datad (92:92:92) (109:109:109)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~33) + (DELAY + (ABSOLUTE + (PORT dataa (569:569:569) (650:650:650)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (409:409:409) (460:460:460)) + (PORT datad (429:429:429) (482:482:482)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~21) + (DELAY + (ABSOLUTE + (PORT dataa (538:538:538) (630:630:630)) + (PORT datab (1000:1000:1000) (1147:1147:1147)) + (PORT datac (531:531:531) (620:620:620)) + (PORT datad (828:828:828) (956:956:956)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~45) + (DELAY + (ABSOLUTE + (PORT dataa (1426:1426:1426) (1646:1646:1646)) + (PORT datab (866:866:866) (1018:1018:1018)) + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (509:509:509) (593:593:593)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~22) + (DELAY + (ABSOLUTE + (PORT dataa (175:175:175) (217:217:217)) + (PORT datab (1001:1001:1001) (1148:1148:1148)) + (PORT datac (518:518:518) (599:599:599)) + (PORT datad (534:534:534) (621:621:621)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~23) + (DELAY + (ABSOLUTE + (PORT dataa (537:537:537) (626:626:626)) + (PORT datab (104:104:104) (132:132:132)) + (PORT datac (993:993:993) (1149:1149:1149)) + (PORT datad (799:799:799) (916:916:916)) + (IOPATH dataa combout (186:186:186) (179:179:179)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~24) + (DELAY + (ABSOLUTE + (PORT dataa (635:635:635) (729:729:729)) + (PORT datab (1002:1002:1002) (1149:1149:1149)) + (PORT datac (769:769:769) (878:878:878)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (186:186:186) (179:179:179)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~25) + (DELAY + (ABSOLUTE + (PORT dataa (815:815:815) (944:944:944)) + (PORT datab (956:956:956) (1096:1096:1096)) + (PORT datac (618:618:618) (703:703:703)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~26) + (DELAY + (ABSOLUTE + (PORT dataa (115:115:115) (145:145:145)) + (PORT datab (518:518:518) (609:609:609)) + (PORT datac (430:430:430) (493:493:493)) + (PORT datad (102:102:102) (118:118:118)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~43) + (DELAY + (ABSOLUTE + (PORT dataa (294:294:294) (339:339:339)) + (PORT datab (298:298:298) (344:344:344)) + (PORT datac (89:89:89) (109:109:109)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_low) + (DELAY + (ABSOLUTE + (PORT dataa (546:546:546) (640:640:640)) + (PORT datab (1090:1090:1090) (1244:1244:1244)) + (PORT datac (1251:1251:1251) (1452:1452:1452)) + (PORT datad (792:792:792) (933:933:933)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero\~5) + (DELAY + (ABSOLUTE + (PORT dataa (712:712:712) (838:838:838)) + (PORT datab (497:497:497) (602:602:602)) + (PORT datac (608:608:608) (705:705:705)) + (PORT datad (447:447:447) (533:533:533)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero) + (DELAY + (ABSOLUTE + (PORT dataa (316:316:316) (371:371:371)) + (PORT datab (1031:1031:1031) (1184:1184:1184)) + (PORT datac (930:930:930) (1095:1095:1095)) + (PORT datad (274:274:274) (312:312:312)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~13) + (DELAY + (ABSOLUTE + (PORT dataa (366:366:366) (431:431:431)) + (PORT datab (317:317:317) (367:367:367)) + (PORT datac (1096:1096:1096) (1264:1264:1264)) + (PORT datad (311:311:311) (364:364:364)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~17) + (DELAY + (ABSOLUTE + (PORT dataa (908:908:908) (1043:1043:1043)) + (PORT datab (297:297:297) (350:350:350)) + (PORT datac (1052:1052:1052) (1222:1222:1222)) + (PORT datad (1026:1026:1026) (1193:1193:1193)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~14) + (DELAY + (ABSOLUTE + (PORT dataa (762:762:762) (890:890:890)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (1163:1163:1163) (1357:1357:1357)) + (PORT datad (569:569:569) (660:660:660)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~3) + (DELAY + (ABSOLUTE + (PORT dataa (535:535:535) (624:624:624)) + (PORT datab (960:960:960) (1110:1110:1110)) + (PORT datac (989:989:989) (1144:1144:1144)) + (PORT datad (512:512:512) (597:597:597)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~4) + (DELAY + (ABSOLUTE + (PORT dataa (533:533:533) (624:624:624)) + (PORT datab (554:554:554) (649:649:649)) + (PORT datac (519:519:519) (601:601:601)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4) + (DELAY + (ABSOLUTE + (PORT dataa (1102:1102:1102) (1274:1274:1274)) + (PORT datab (669:669:669) (777:777:777)) + (PORT datad (853:853:853) (1016:1016:1016)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1007:1007:1007) (1171:1171:1171)) + (PORT datab (608:608:608) (707:707:707)) + (PORT datac (497:497:497) (575:575:575)) + (PORT datad (826:826:826) (954:954:954)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~10) + (DELAY + (ABSOLUTE + (PORT dataa (176:176:176) (217:217:217)) + (PORT datab (117:117:117) (145:145:145)) + (PORT datac (96:96:96) (121:121:121)) + (PORT datad (338:338:338) (399:399:399)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~11) + (DELAY + (ABSOLUTE + (PORT dataa (386:386:386) (461:461:461)) + (PORT datab (1010:1010:1010) (1171:1171:1171)) + (PORT datac (330:330:330) (389:389:389)) + (PORT datad (441:441:441) (507:507:507)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~12) + (DELAY + (ABSOLUTE + (PORT dataa (617:617:617) (711:711:711)) + (PORT datab (973:973:973) (1125:1125:1125)) + (PORT datac (933:933:933) (1098:1098:1098)) + (PORT datad (319:319:319) (365:365:365)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~15) + (DELAY + (ABSOLUTE + (PORT dataa (295:295:295) (343:343:343)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (266:266:266) (301:301:301)) + (PORT datad (429:429:429) (482:482:482)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[3\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (516:516:516) (601:601:601)) + (PORT datab (458:458:458) (532:532:532)) + (PORT datac (473:473:473) (540:540:540)) + (PORT datad (336:336:336) (388:388:388)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[3\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (377:377:377) (458:458:458)) + (PORT datab (478:478:478) (556:556:556)) + (PORT datac (484:484:484) (559:559:559)) + (PORT datad (89:89:89) (106:106:106)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|ena) + (DELAY + (ABSOLUTE + (PORT dataa (512:512:512) (597:597:597)) + (PORT datac (497:497:497) (576:576:576)) + (PORT datad (455:455:455) (527:527:527)) + (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -16225,12 +8308,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[3\]) + (INSTANCE z80_\|alu_\|op1_low\[3\]) (DELAY (ABSOLUTE - (PORT clk (915:915:915) (923:923:923)) + (PORT clk (931:931:931) (916:916:916)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (776:776:776) (851:851:851)) + (PORT ena (409:409:409) (429:429:429)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -16241,14 +8324,284 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~31) + (INSTANCE z80_\|alu_\|db_low\[3\]\~15) (DELAY (ABSOLUTE - (PORT dataa (1009:1009:1009) (1180:1180:1180)) - (PORT datab (530:530:530) (614:614:614)) - (PORT datac (805:805:805) (923:923:923)) - (PORT datad (1092:1092:1092) (1244:1244:1244)) + (PORT dataa (353:353:353) (414:414:414)) + (PORT datab (378:378:378) (438:438:438)) + (PORT datac (362:362:362) (443:443:443)) + (PORT datad (224:224:224) (281:281:281)) (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[3\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (147:147:147) (186:186:186)) + (PORT datac (618:618:618) (709:709:709)) + (PORT datad (175:175:175) (208:208:208)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~33) + (DELAY + (ABSOLUTE + (PORT dataa (482:482:482) (556:556:556)) + (PORT datab (956:956:956) (1092:1092:1092)) + (PORT datac (471:471:471) (544:544:544)) + (PORT datad (525:525:525) (645:645:645)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~34) + (DELAY + (ABSOLUTE + (PORT dataa (329:329:329) (391:391:391)) + (PORT datab (630:630:630) (744:744:744)) + (PORT datac (330:330:330) (388:388:388)) + (PORT datad (494:494:494) (570:570:570)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~48) + (DELAY + (ABSOLUTE + (PORT dataa (873:873:873) (1041:1041:1041)) + (PORT datab (882:882:882) (1036:1036:1036)) + (PORT datac (1193:1193:1193) (1383:1383:1383)) + (PORT datad (599:599:599) (687:687:687)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~35) + (DELAY + (ABSOLUTE + (PORT dataa (482:482:482) (558:558:558)) + (PORT datab (889:889:889) (1057:1057:1057)) + (PORT datac (465:465:465) (530:530:530)) + (PORT datad (660:660:660) (753:753:753)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~36) + (DELAY + (ABSOLUTE + (PORT dataa (335:335:335) (395:395:395)) + (PORT datab (454:454:454) (530:530:530)) + (PORT datac (329:329:329) (387:387:387)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~37) + (DELAY + (ABSOLUTE + (PORT dataa (120:120:120) (158:158:158)) + (PORT datab (349:349:349) (410:410:410)) + (PORT datac (316:316:316) (366:366:366)) + (PORT datad (305:305:305) (359:359:359)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla26M1T4_3) + (DELAY + (ABSOLUTE + (PORT dataa (876:876:876) (1044:1044:1044)) + (PORT datab (911:911:911) (1048:1048:1048)) + (PORT datad (1079:1079:1079) (1246:1246:1246)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~38) + (DELAY + (ABSOLUTE + (PORT dataa (574:574:574) (675:675:675)) + (PORT datab (1174:1174:1174) (1344:1344:1344)) + (PORT datac (606:606:606) (716:716:716)) + (PORT datad (627:627:627) (722:722:722)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~39) + (DELAY + (ABSOLUTE + (PORT dataa (789:789:789) (915:915:915)) + (PORT datab (1130:1130:1130) (1297:1297:1297)) + (PORT datac (909:909:909) (1034:1034:1034)) + (PORT datad (702:702:702) (816:816:816)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~40) + (DELAY + (ABSOLUTE + (PORT dataa (209:209:209) (252:252:252)) + (PORT datab (437:437:437) (509:509:509)) + (PORT datac (106:106:106) (130:130:130)) + (PORT datad (476:476:476) (568:568:568)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~41) + (DELAY + (ABSOLUTE + (PORT dataa (1090:1090:1090) (1239:1239:1239)) + (PORT datab (467:467:467) (545:545:545)) + (PORT datac (1383:1383:1383) (1563:1563:1563)) + (PORT datad (503:503:503) (582:582:582)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low) + (DELAY + (ABSOLUTE + (PORT dataa (532:532:532) (633:633:633)) + (PORT datab (124:124:124) (157:157:157)) + (PORT datac (921:921:921) (1069:1069:1069)) + (PORT datad (444:444:444) (509:509:509)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|result_lo\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (913:913:913)) + (PORT asdata (508:508:508) (561:561:561)) + (PORT ena (1078:1078:1078) (1189:1189:1189)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~5) + (DELAY + (ABSOLUTE + (PORT dataa (492:492:492) (584:584:584)) + (PORT datab (128:128:128) (162:162:162)) + (PORT datac (653:653:653) (762:762:762)) + (PORT datad (572:572:572) (694:694:694)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~6) + (DELAY + (ABSOLUTE + (PORT dataa (460:460:460) (547:547:547)) + (PORT datab (336:336:336) (397:397:397)) + (PORT datac (449:449:449) (503:503:503)) + (PORT datad (337:337:337) (396:396:396)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~9) + (DELAY + (ABSOLUTE + (PORT dataa (682:682:682) (781:781:781)) + (PORT datab (363:363:363) (435:435:435)) + (PORT datac (615:615:615) (694:694:694)) + (PORT datad (322:322:322) (373:373:373)) + (IOPATH dataa combout (165:165:165) (159:159:159)) (IOPATH datab combout (166:166:166) (158:158:158)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -16257,13 +8610,187 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~30) + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~12) (DELAY (ABSOLUTE - (PORT dataa (329:329:329) (391:391:391)) - (PORT datab (688:688:688) (797:797:797)) - (PORT datac (1033:1033:1033) (1205:1205:1205)) - (PORT datad (605:605:605) (696:696:696)) + (PORT dataa (739:739:739) (847:847:847)) + (PORT datab (659:659:659) (769:769:769)) + (PORT datac (927:927:927) (1068:1068:1068)) + (PORT datad (1093:1093:1093) (1276:1276:1276)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~10) + (DELAY + (ABSOLUTE + (PORT dataa (106:106:106) (138:138:138)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (611:611:611) (717:717:717)) + (PORT datad (103:103:103) (121:121:121)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~2) + (DELAY + (ABSOLUTE + (PORT dataa (457:457:457) (530:530:530)) + (PORT datab (485:485:485) (563:563:563)) + (PORT datac (401:401:401) (481:481:481)) + (PORT datad (527:527:527) (647:647:647)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel_pla66npla53M1T1_15) + (DELAY + (ABSOLUTE + (PORT dataa (1049:1049:1049) (1195:1195:1195)) + (PORT datab (610:610:610) (702:702:702)) + (PORT datac (827:827:827) (994:994:994)) + (PORT datad (819:819:819) (950:950:950)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (387:387:387) (454:454:454)) + (PORT datab (485:485:485) (563:563:563)) + (PORT datac (694:694:694) (812:812:812)) + (PORT datad (798:798:798) (955:955:955)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~8) + (DELAY + (ABSOLUTE + (PORT dataa (528:528:528) (618:618:618)) + (PORT datab (500:500:500) (579:579:579)) + (PORT datac (493:493:493) (571:571:571)) + (PORT datad (597:597:597) (676:676:676)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1070:1070:1070) (1247:1247:1247)) + (PORT datab (728:728:728) (833:833:833)) + (PORT datac (492:492:492) (563:563:563)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~7) + (DELAY + (ABSOLUTE + (PORT dataa (437:437:437) (511:511:511)) + (PORT datab (302:302:302) (353:353:353)) + (PORT datac (666:666:666) (768:768:768)) + (PORT datad (336:336:336) (392:392:392)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~11) + (DELAY + (ABSOLUTE + (PORT dataa (966:966:966) (1118:1118:1118)) + (PORT datab (212:212:212) (248:248:248)) + (PORT datac (314:314:314) (363:363:363)) + (PORT datad (646:646:646) (734:734:734)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (305:305:305) (358:358:358)) + (PORT datab (631:631:631) (736:736:736)) + (PORT datac (878:878:878) (995:995:995)) + (PORT datad (311:311:311) (357:357:357)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~8) + (DELAY + (ABSOLUTE + (PORT dataa (509:509:509) (596:596:596)) + (PORT datab (614:614:614) (719:719:719)) + (PORT datac (89:89:89) (110:110:110)) + (PORT datad (447:447:447) (514:514:514)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~16) + (DELAY + (ABSOLUTE + (PORT dataa (368:368:368) (436:436:436)) + (PORT datab (114:114:114) (142:142:142)) + (PORT datac (304:304:304) (353:353:353)) + (PORT datad (471:471:471) (547:547:547)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -16271,16 +8798,2125 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~11) + (DELAY + (ABSOLUTE + (PORT dataa (615:615:615) (702:702:702)) + (PORT datab (296:296:296) (342:342:342)) + (PORT datac (812:812:812) (917:917:917)) + (PORT datad (455:455:455) (521:521:521)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~48) + (DELAY + (ABSOLUTE + (PORT dataa (665:665:665) (767:767:767)) + (PORT datab (1050:1050:1050) (1223:1223:1223)) + (PORT datac (287:287:287) (332:332:332)) + (PORT datad (953:953:953) (1103:1103:1103)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~8) + (DELAY + (ABSOLUTE + (PORT dataa (782:782:782) (916:916:916)) + (PORT datab (547:547:547) (637:637:637)) + (PORT datac (603:603:603) (687:687:687)) + (PORT datad (538:538:538) (641:641:641)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~5) + (DELAY + (ABSOLUTE + (PORT dataa (351:351:351) (422:422:422)) + (PORT datab (384:384:384) (458:458:458)) + (PORT datac (343:343:343) (397:397:397)) + (PORT datad (355:355:355) (422:422:422)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1472:1472:1472) (1693:1693:1693)) + (PORT datab (484:484:484) (560:560:560)) + (PORT datac (928:928:928) (1072:1072:1072)) + (PORT datad (644:644:644) (735:735:735)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~0) + (DELAY + (ABSOLUTE + (PORT dataa (540:540:540) (628:628:628)) + (PORT datab (946:946:946) (1095:1095:1095)) + (PORT datac (522:522:522) (617:617:617)) + (PORT datad (688:688:688) (795:795:795)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~3) + (DELAY + (ABSOLUTE + (PORT dataa (578:578:578) (664:664:664)) + (PORT datab (367:367:367) (436:436:436)) + (PORT datac (103:103:103) (125:125:125)) + (PORT datad (94:94:94) (113:113:113)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (736:736:736) (878:878:878)) + (PORT datab (185:185:185) (223:223:223)) + (PORT datac (677:677:677) (784:784:784)) + (PORT datad (738:738:738) (877:877:877)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~33) + (DELAY + (ABSOLUTE + (PORT dataa (619:619:619) (715:715:715)) + (PORT datab (983:983:983) (1127:1127:1127)) + (PORT datac (758:758:758) (877:877:877)) + (PORT datad (750:750:750) (881:881:881)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (880:880:880) (1049:1049:1049)) + (PORT datab (671:671:671) (779:779:779)) + (PORT datac (894:894:894) (1048:1048:1048)) + (PORT datad (94:94:94) (113:113:113)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~6) + (DELAY + (ABSOLUTE + (PORT dataa (527:527:527) (618:618:618)) + (PORT datab (496:496:496) (589:589:589)) + (PORT datac (583:583:583) (663:663:663)) + (PORT datad (100:100:100) (122:122:122)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datab combout (188:188:188) (193:193:193)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~6) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (133:133:133)) + (PORT datab (489:489:489) (560:560:560)) + (PORT datac (737:737:737) (825:825:825)) + (PORT datad (160:160:160) (188:188:188)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~7) + (DELAY + (ABSOLUTE + (PORT dataa (373:373:373) (447:447:447)) + (PORT datab (370:370:370) (439:439:439)) + (PORT datac (89:89:89) (110:110:110)) + (PORT datad (102:102:102) (119:119:119)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~2) + (DELAY + (ABSOLUTE + (PORT dataa (341:341:341) (394:394:394)) + (PORT datab (978:978:978) (1149:1149:1149)) + (PORT datac (530:530:530) (628:628:628)) + (PORT datad (1442:1442:1442) (1679:1679:1679)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~6) + (DELAY + (ABSOLUTE + (PORT dataa (660:660:660) (772:772:772)) + (PORT datab (756:756:756) (892:892:892)) + (PORT datac (867:867:867) (999:999:999)) + (PORT datad (1117:1117:1117) (1305:1305:1305)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~7) + (DELAY + (ABSOLUTE + (PORT dataa (969:969:969) (1145:1145:1145)) + (PORT datab (398:398:398) (481:481:481)) + (PORT datac (300:300:300) (348:348:348)) + (PORT datad (488:488:488) (555:555:555)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla27npla34M1T1_3) + (DELAY + (ABSOLUTE + (PORT dataa (428:428:428) (520:520:520)) + (PORT datab (1019:1019:1019) (1184:1184:1184)) + (PORT datac (1238:1238:1238) (1418:1418:1418)) + (PORT datad (394:394:394) (472:472:472)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~8) + (DELAY + (ABSOLUTE + (PORT dataa (480:480:480) (555:555:555)) + (PORT datab (101:101:101) (129:129:129)) + (PORT datac (586:586:586) (675:675:675)) + (PORT datad (94:94:94) (113:113:113)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~7) + (DELAY + (ABSOLUTE + (PORT dataa (360:360:360) (424:424:424)) + (PORT datab (319:319:319) (368:368:368)) + (PORT datac (821:821:821) (936:936:936)) + (PORT datad (448:448:448) (523:523:523)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~5) + (DELAY + (ABSOLUTE + (PORT dataa (539:539:539) (631:631:631)) + (PORT datab (502:502:502) (598:598:598)) + (PORT datac (497:497:497) (581:581:581)) + (PORT datad (645:645:645) (751:751:751)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~19) + (DELAY + (ABSOLUTE + (PORT dataa (480:480:480) (561:561:561)) + (PORT datab (513:513:513) (608:608:608)) + (PORT datac (517:517:517) (613:613:613)) + (PORT datad (482:482:482) (552:552:552)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~18) + (DELAY + (ABSOLUTE + (PORT dataa (549:549:549) (645:645:645)) + (PORT datab (378:378:378) (450:450:450)) + (PORT datac (602:602:602) (690:690:690)) + (PORT datad (363:363:363) (434:434:434)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~2) + (DELAY + (ABSOLUTE + (PORT dataa (204:204:204) (244:244:244)) + (PORT datab (114:114:114) (141:141:141)) + (PORT datac (115:115:115) (135:135:135)) + (PORT datad (940:940:940) (1068:1068:1068)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal24\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1456:1456:1456) (1703:1703:1703)) + (PORT datab (543:543:543) (641:641:641)) + (PORT datac (960:960:960) (1125:1125:1125)) + (PORT datad (503:503:503) (593:593:593)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~3) + (DELAY + (ABSOLUTE + (PORT dataa (502:502:502) (595:595:595)) + (PORT datab (802:802:802) (918:918:918)) + (PORT datac (90:90:90) (112:112:112)) + (PORT datad (346:346:346) (407:407:407)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~4) + (DELAY + (ABSOLUTE + (PORT dataa (672:672:672) (785:785:785)) + (PORT datab (760:760:760) (897:897:897)) + (PORT datac (727:727:727) (845:845:845)) + (PORT datad (548:548:548) (636:636:636)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~20) + (DELAY + (ABSOLUTE + (PORT dataa (318:318:318) (367:367:367)) + (PORT datab (320:320:320) (377:377:377)) + (PORT datac (548:548:548) (647:647:647)) + (PORT datad (519:519:519) (608:608:608)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~5) + (DELAY + (ABSOLUTE + (PORT dataa (388:388:388) (451:451:451)) + (PORT datab (483:483:483) (562:562:562)) + (PORT datac (322:322:322) (365:365:365)) + (PORT datad (621:621:621) (710:710:710)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~22) + (DELAY + (ABSOLUTE + (PORT dataa (517:517:517) (594:594:594)) + (PORT datab (647:647:647) (745:745:745)) + (PORT datac (446:446:446) (507:507:507)) + (PORT datad (326:326:326) (378:378:378)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla42M3T3_6) + (DELAY + (ABSOLUTE + (PORT dataa (674:674:674) (790:790:790)) + (PORT datab (607:607:607) (699:699:699)) + (PORT datac (337:337:337) (395:395:395)) + (PORT datad (938:938:938) (1109:1109:1109)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~6) + (DELAY + (ABSOLUTE + (PORT dataa (478:478:478) (554:554:554)) + (PORT datab (508:508:508) (583:583:583)) + (PORT datac (1204:1204:1204) (1391:1391:1391)) + (PORT datad (485:485:485) (565:565:565)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1075:1075:1075) (1248:1248:1248)) + (PORT datad (665:665:665) (782:782:782)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~30) + (DELAY + (ABSOLUTE + (PORT dataa (335:335:335) (387:387:387)) + (PORT datab (382:382:382) (451:451:451)) + (PORT datac (605:605:605) (708:708:708)) + (PORT datad (469:469:469) (539:539:539)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~23) + (DELAY + (ABSOLUTE + (PORT dataa (327:327:327) (378:378:378)) + (PORT datab (712:712:712) (827:827:827)) + (PORT datac (604:604:604) (707:707:707)) + (PORT datad (469:469:469) (539:539:539)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (780:780:780) (889:889:889)) + (PORT datab (116:116:116) (144:144:144)) + (PORT datac (326:326:326) (384:384:384)) + (PORT datad (472:472:472) (550:550:550)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1295:1295:1295) (1519:1519:1519)) + (PORT datab (620:620:620) (714:714:714)) + (PORT datac (525:525:525) (622:622:622)) + (PORT datad (360:360:360) (431:431:431)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~10) + (DELAY + (ABSOLUTE + (PORT dataa (465:465:465) (534:534:534)) + (PORT datab (424:424:424) (483:483:483)) + (PORT datad (636:636:636) (727:727:727)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~18) + (DELAY + (ABSOLUTE + (PORT dataa (474:474:474) (544:544:544)) + (PORT datab (678:678:678) (787:787:787)) + (PORT datac (675:675:675) (786:786:786)) + (PORT datad (609:609:609) (694:694:694)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_pc\~0) + (DELAY + (ABSOLUTE + (PORT dataa (640:640:640) (731:731:731)) + (PORT datab (502:502:502) (591:591:591)) + (PORT datac (1048:1048:1048) (1210:1210:1210)) + (PORT datad (369:369:369) (435:435:435)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_pc\~1) + (DELAY + (ABSOLUTE + (PORT dataa (502:502:502) (595:595:595)) + (PORT datab (130:130:130) (164:164:164)) + (PORT datac (116:116:116) (137:137:137)) + (PORT datad (493:493:493) (567:567:567)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_pc\~2) + (DELAY + (ABSOLUTE + (PORT dataa (360:360:360) (424:424:424)) + (PORT datab (128:128:128) (161:161:161)) + (PORT datac (89:89:89) (111:111:111)) + (PORT datad (939:939:939) (1067:1067:1067)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~19) + (DELAY + (ABSOLUTE + (PORT dataa (513:513:513) (593:593:593)) + (PORT datab (361:361:361) (429:429:429)) + (PORT datac (674:674:674) (785:785:785)) + (PORT datad (369:369:369) (437:437:437)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~20) + (DELAY + (ABSOLUTE + (PORT dataa (319:319:319) (373:373:373)) + (PORT datab (116:116:116) (144:144:144)) + (PORT datac (88:88:88) (109:109:109)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~21) + (DELAY + (ABSOLUTE + (PORT dataa (519:519:519) (623:623:623)) + (PORT datab (492:492:492) (591:591:591)) + (PORT datac (105:105:105) (128:128:128)) + (PORT datad (347:347:347) (407:407:407)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~9) + (DELAY + (ABSOLUTE + (PORT dataa (355:355:355) (416:416:416)) + (PORT datab (352:352:352) (411:411:411)) + (PORT datac (664:664:664) (768:768:768)) + (PORT datad (334:334:334) (389:389:389)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~14) + (DELAY + (ABSOLUTE + (PORT dataa (959:959:959) (1113:1113:1113)) + (PORT datab (168:168:168) (226:226:226)) + (PORT datac (464:464:464) (531:531:531)) + (PORT datad (315:315:315) (361:361:361)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_1d\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1169:1169:1169) (1386:1386:1386)) + (PORT datab (671:671:671) (808:808:808)) + (PORT datac (366:366:366) (435:435:435)) + (PORT datad (688:688:688) (821:821:821)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~10) + (DELAY + (ABSOLUTE + (PORT dataa (353:353:353) (428:428:428)) + (PORT datab (614:614:614) (728:728:728)) + (PORT datac (504:504:504) (584:584:584)) + (PORT datad (654:654:654) (756:756:756)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~11) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (137:137:137)) + (PORT datab (665:665:665) (772:772:772)) + (PORT datac (414:414:414) (504:504:504)) + (PORT datad (88:88:88) (106:106:106)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~12) + (DELAY + (ABSOLUTE + (PORT dataa (645:645:645) (748:748:748)) + (PORT datab (520:520:520) (613:613:613)) + (PORT datac (312:312:312) (357:357:357)) + (PORT datad (465:465:465) (543:543:543)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~13) + (DELAY + (ABSOLUTE + (PORT dataa (490:490:490) (567:567:567)) + (PORT datab (105:105:105) (135:135:135)) + (PORT datac (433:433:433) (504:504:504)) + (PORT datad (460:460:460) (528:528:528)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[7\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (329:329:329) (398:398:398)) + (PORT datac (305:305:305) (356:356:356)) + (PORT datad (363:363:363) (441:441:441)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|SYNTHESIZED_WIRE_2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (333:333:333) (408:408:408)) + (PORT datab (611:611:611) (695:695:695)) + (PORT datac (162:162:162) (195:195:195)) + (PORT datad (1137:1137:1137) (1336:1336:1336)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla89M1T2_3) + (DELAY + (ABSOLUTE + (PORT dataa (1016:1016:1016) (1202:1202:1202)) + (PORT datab (539:539:539) (631:631:631)) + (PORT datac (502:502:502) (581:581:581)) + (PORT datad (610:610:610) (714:714:714)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~32) + (DELAY + (ABSOLUTE + (PORT dataa (365:365:365) (432:432:432)) + (PORT datab (525:525:525) (606:606:606)) + (PORT datac (682:682:682) (804:804:804)) + (PORT datad (1167:1167:1167) (1352:1352:1352)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~2) + (DELAY + (ABSOLUTE + (PORT dataa (520:520:520) (611:611:611)) + (PORT datab (908:908:908) (1071:1071:1071)) + (PORT datac (1131:1131:1131) (1330:1330:1330)) + (PORT datad (347:347:347) (409:409:409)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~22) + (DELAY + (ABSOLUTE + (PORT dataa (1100:1100:1100) (1272:1272:1272)) + (PORT datab (532:532:532) (622:622:622)) + (PORT datac (1195:1195:1195) (1385:1385:1385)) + (PORT datad (618:618:618) (721:721:721)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~3) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (426:426:426)) + (PORT datab (105:105:105) (134:134:134)) + (PORT datad (93:93:93) (111:111:111)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~4) + (DELAY + (ABSOLUTE + (PORT dataa (325:325:325) (382:382:382)) + (PORT datab (329:329:329) (390:390:390)) + (PORT datac (458:458:458) (526:526:526)) + (PORT datad (340:340:340) (401:401:401)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~5) + (DELAY + (ABSOLUTE + (PORT dataa (317:317:317) (379:379:379)) + (PORT datab (628:628:628) (713:713:713)) + (PORT datac (115:115:115) (142:142:142)) + (PORT datad (323:323:323) (379:379:379)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~12) + (DELAY + (ABSOLUTE + (PORT dataa (695:695:695) (823:823:823)) + (PORT datab (792:792:792) (933:933:933)) + (PORT datac (352:352:352) (421:421:421)) + (PORT datad (1014:1014:1014) (1172:1172:1172)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~13) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (411:411:411)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (117:117:117) (146:146:146)) + (PORT datad (104:104:104) (121:121:121)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~15) + (DELAY + (ABSOLUTE + (PORT dataa (569:569:569) (688:688:688)) + (PORT datab (122:122:122) (152:152:152)) + (PORT datac (611:611:611) (688:688:688)) + (PORT datad (323:323:323) (384:384:384)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~6) + (DELAY + (ABSOLUTE + (PORT datab (294:294:294) (342:342:342)) + (PORT datac (167:167:167) (200:200:200)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~7) + (DELAY + (ABSOLUTE + (PORT dataa (190:190:190) (228:228:228)) + (PORT datab (108:108:108) (139:139:139)) + (PORT datac (89:89:89) (110:110:110)) + (PORT datad (305:305:305) (355:355:355)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_nop3pla68M1T3_2) + (DELAY + (ABSOLUTE + (PORT dataa (931:931:931) (1070:1070:1070)) + (PORT datab (778:778:778) (896:896:896)) + (PORT datac (1079:1079:1079) (1240:1240:1240)) + (PORT datad (504:504:504) (598:598:598)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1318:1318:1318) (1528:1528:1528)) + (PORT datab (105:105:105) (134:134:134)) + (PORT datac (483:483:483) (567:567:567)) + (PORT datad (750:750:750) (844:844:844)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~17) + (DELAY + (ABSOLUTE + (PORT dataa (520:520:520) (622:622:622)) + (PORT datab (122:122:122) (153:153:153)) + (PORT datac (655:655:655) (757:757:757)) + (PORT datad (464:464:464) (533:533:533)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1054:1054:1054) (1202:1202:1202)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (102:102:102) (123:123:123)) + (PORT datad (624:624:624) (719:719:719)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~2) + (DELAY + (ABSOLUTE + (PORT dataa (467:467:467) (545:545:545)) + (PORT datab (349:349:349) (412:412:412)) + (PORT datac (450:450:450) (519:519:519)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1320:1320:1320) (1530:1530:1530)) + (PORT datab (968:968:968) (1108:1108:1108)) + (PORT datac (483:483:483) (567:567:567)) + (PORT datad (749:749:749) (843:843:843)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~0) + (DELAY + (ABSOLUTE + (PORT dataa (644:644:644) (743:743:743)) + (PORT datab (622:622:622) (738:738:738)) + (PORT datac (1159:1159:1159) (1326:1326:1326)) + (PORT datad (975:975:975) (1125:1125:1125)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal73\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1160:1160:1160) (1376:1376:1376)) + (PORT datab (660:660:660) (795:795:795)) + (PORT datac (536:536:536) (622:622:622)) + (PORT datad (698:698:698) (834:834:834)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal72\~2) + (DELAY + (ABSOLUTE + (PORT dataa (567:567:567) (685:685:685)) + (PORT datab (117:117:117) (148:148:148)) + (PORT datac (612:612:612) (726:726:726)) + (PORT datad (832:832:832) (973:973:973)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~1) + (DELAY + (ABSOLUTE + (PORT dataa (351:351:351) (414:414:414)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (610:610:610) (694:694:694)) + (PORT datad (323:323:323) (377:377:377)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (180:180:180) (219:219:219)) + (PORT datab (294:294:294) (342:342:342)) + (PORT datac (167:167:167) (200:200:200)) + (PORT datad (458:458:458) (540:540:540)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (371:371:371) (450:450:450)) + (PORT datab (872:872:872) (1042:1042:1042)) + (PORT datad (533:533:533) (634:634:634)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (134:134:134)) + (PORT datab (529:529:529) (611:611:611)) + (PORT datac (1257:1257:1257) (1428:1428:1428)) + (PORT datad (476:476:476) (554:554:554)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (306:306:306) (359:359:359)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (847:847:847) (996:996:996)) + (PORT datad (303:303:303) (351:351:351)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~8) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (136:136:136)) + (PORT datab (300:300:300) (347:347:347)) + (PORT datad (92:92:92) (109:109:109)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (913:913:913)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~14) + (DELAY + (ABSOLUTE + (PORT datab (645:645:645) (750:750:750)) + (PORT datad (740:740:740) (869:869:869)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~10) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (137:137:137)) + (PORT datab (199:199:199) (237:237:237)) + (PORT datac (975:975:975) (1130:1130:1130)) + (PORT datad (94:94:94) (114:114:114)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal45\~0) + (DELAY + (ABSOLUTE + (PORT dataa (498:498:498) (588:588:588)) + (PORT datab (633:633:633) (751:751:751)) + (PORT datac (657:657:657) (783:783:783)) + (PORT datad (920:920:920) (1084:1084:1084)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~11) + (DELAY + (ABSOLUTE + (PORT dataa (690:690:690) (802:802:802)) + (PORT datab (465:465:465) (536:536:536)) + (PORT datac (630:630:630) (723:723:723)) + (PORT datad (922:922:922) (1050:1050:1050)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~12) + (DELAY + (ABSOLUTE + (PORT dataa (691:691:691) (796:796:796)) + (PORT datab (534:534:534) (625:625:625)) + (PORT datac (1025:1025:1025) (1183:1183:1183)) + (PORT datad (93:93:93) (111:111:111)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~13) + (DELAY + (ABSOLUTE + (PORT dataa (859:859:859) (1012:1012:1012)) + (PORT datab (702:702:702) (825:825:825)) + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (555:555:555) (651:651:651)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~8) + (DELAY + (ABSOLUTE + (PORT dataa (485:485:485) (568:568:568)) + (PORT datab (308:308:308) (356:356:356)) + (PORT datac (182:182:182) (214:214:214)) + (PORT datad (585:585:585) (690:690:690)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~9) + (DELAY + (ABSOLUTE + (PORT dataa (351:351:351) (414:414:414)) + (PORT datac (337:337:337) (389:389:389)) + (PORT datad (324:324:324) (378:378:378)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~10) + (DELAY + (ABSOLUTE + (PORT dataa (325:325:325) (373:373:373)) + (PORT datab (343:343:343) (403:403:403)) + (PORT datac (176:176:176) (207:207:207)) + (PORT datad (446:446:446) (513:513:513)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S) + (DELAY + (ABSOLUTE + (PORT dataa (470:470:470) (543:543:543)) + (PORT datab (109:109:109) (140:140:140)) + (PORT datac (200:200:200) (242:242:242)) + (PORT datad (325:325:325) (374:374:374)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[3\]) + (DELAY + (ABSOLUTE + (PORT dataa (378:378:378) (459:459:459)) + (PORT datac (488:488:488) (564:564:564)) + (PORT datad (451:451:451) (512:512:512)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|ena\~0) + (DELAY + (ABSOLUTE + (PORT dataa (516:516:516) (600:600:600)) + (PORT datac (486:486:486) (561:561:561)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_high\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (931:931:931) (916:916:916)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (421:421:421) (449:449:449)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op1\[3\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (666:666:666) (790:790:790)) + (PORT datab (372:372:372) (437:437:437)) + (PORT datac (213:213:213) (274:274:274)) + (PORT datad (224:224:224) (282:282:282)) + (IOPATH dataa combout (158:158:158) (173:173:173)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|SYNTHESIZED_WIRE_10\~1) + (DELAY + (ABSOLUTE + (PORT dataa (734:734:734) (863:863:863)) + (PORT datac (101:101:101) (121:121:121)) + (PORT datad (107:107:107) (127:127:127)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_we_lo\~2) + (DELAY + (ABSOLUTE + (PORT datab (522:522:522) (606:606:606)) + (PORT datac (650:650:650) (751:751:751)) + (PORT datad (1442:1442:1442) (1679:1679:1679)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_we_lo\~3) + (DELAY + (ABSOLUTE + (PORT dataa (527:527:527) (605:605:605)) + (PORT datab (182:182:182) (219:219:219)) + (PORT datac (642:642:642) (743:743:743)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~14) + (DELAY + (ABSOLUTE + (PORT dataa (478:478:478) (554:554:554)) + (PORT datab (511:511:511) (586:586:586)) + (PORT datac (471:471:471) (532:532:532)) + (PORT datad (514:514:514) (611:611:611)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_hi\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1039:1039:1039) (1202:1202:1202)) + (PORT datab (508:508:508) (584:584:584)) + (PORT datac (1204:1204:1204) (1392:1392:1392)) + (PORT datad (95:95:95) (114:114:114)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal33\~3) + (DELAY + (ABSOLUTE + (PORT dataa (671:671:671) (794:794:794)) + (PORT datab (1012:1012:1012) (1146:1146:1146)) + (PORT datac (493:493:493) (577:577:577)) + (PORT datad (530:530:530) (623:623:623)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~0) + (DELAY + (ABSOLUTE + (PORT dataa (360:360:360) (425:425:425)) + (PORT datab (325:325:325) (381:381:381)) + (PORT datac (788:788:788) (915:915:915)) + (PORT datad (515:515:515) (590:590:590)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (537:537:537) (620:620:620)) + (PORT datab (107:107:107) (137:137:137)) + (PORT datac (1155:1155:1155) (1351:1351:1351)) + (PORT datad (633:633:633) (723:723:723)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (433:433:433) (503:503:503)) + (PORT datab (353:353:353) (408:408:408)) + (PORT datac (855:855:855) (992:992:992)) + (PORT datad (605:605:605) (686:686:686)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~4) + (DELAY + (ABSOLUTE + (PORT dataa (480:480:480) (566:566:566)) + (PORT datab (613:613:613) (718:718:718)) + (PORT datac (367:367:367) (431:431:431)) + (PORT datad (357:357:357) (421:421:421)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_hi) + (DELAY + (ABSOLUTE + (PORT dataa (484:484:484) (560:560:560)) + (PORT datab (479:479:479) (558:558:558)) + (PORT datad (96:96:96) (117:117:117)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (498:498:498) (591:591:591)) + (PORT datab (690:690:690) (824:824:824)) + (PORT datac (701:701:701) (820:820:820)) + (PORT datad (633:633:633) (738:738:738)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\~17) + (DELAY + (ABSOLUTE + (PORT dataa (653:653:653) (763:763:763)) + (PORT datab (1002:1002:1002) (1176:1176:1176)) + (PORT datac (467:467:467) (536:536:536)) + (PORT datad (677:677:677) (801:801:801)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~11) + (DELAY + (ABSOLUTE + (PORT dataa (776:776:776) (883:883:883)) + (PORT datab (992:992:992) (1134:1134:1134)) + (PORT datac (630:630:630) (732:732:732)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~12) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (205:205:205) (244:244:244)) + (PORT datac (90:90:90) (111:111:111)) + (PORT datad (190:190:190) (223:223:223)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~13) + (DELAY + (ABSOLUTE + (PORT dataa (124:124:124) (159:159:159)) + (PORT datab (954:954:954) (1107:1107:1107)) + (PORT datac (287:287:287) (332:332:332)) + (PORT datad (875:875:875) (1006:1006:1006)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla56M3T3_6) + (DELAY + (ABSOLUTE + (PORT dataa (673:673:673) (789:789:789)) + (PORT datab (357:357:357) (420:420:420)) + (PORT datac (729:729:729) (855:855:855)) + (PORT datad (942:942:942) (1114:1114:1114)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~6) + (DELAY + (ABSOLUTE + (PORT dataa (706:706:706) (829:829:829)) + (PORT datab (678:678:678) (786:786:786)) + (PORT datac (316:316:316) (375:375:375)) + (PORT datad (108:108:108) (127:127:127)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~7) + (DELAY + (ABSOLUTE + (PORT dataa (485:485:485) (556:556:556)) + (PORT datab (119:119:119) (147:147:147)) + (PORT datac (1207:1207:1207) (1394:1394:1394)) + (PORT datad (435:435:435) (497:497:497)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~9) + (DELAY + (ABSOLUTE + (PORT dataa (992:992:992) (1161:1161:1161)) + (PORT datab (847:847:847) (976:976:976)) + (PORT datac (600:600:600) (683:683:683)) + (PORT datad (98:98:98) (119:119:119)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (749:749:749) (883:883:883)) + (PORT datab (340:340:340) (402:402:402)) + (PORT datac (333:333:333) (382:382:382)) + (PORT datad (764:764:764) (878:878:878)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~8) + (DELAY + (ABSOLUTE + (PORT dataa (490:490:490) (575:575:575)) + (PORT datac (586:586:586) (671:671:671)) + (PORT datad (641:641:641) (733:733:733)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (334:334:334) (400:400:400)) + (PORT datab (354:354:354) (412:412:412)) + (PORT datac (340:340:340) (394:394:394)) + (PORT datad (508:508:508) (583:583:583)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (384:384:384) (456:456:456)) + (PORT datab (193:193:193) (240:240:240)) + (PORT datac (647:647:647) (741:741:741)) + (PORT datad (618:618:618) (713:713:713)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~41) + (DELAY + (ABSOLUTE + (PORT dataa (609:609:609) (697:697:697)) + (PORT datab (1002:1002:1002) (1176:1176:1176)) + (PORT datac (621:621:621) (711:711:711)) + (PORT datad (677:677:677) (801:801:801)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~10) + (DELAY + (ABSOLUTE + (PORT dataa (507:507:507) (597:597:597)) + (PORT datac (496:496:496) (568:568:568)) + (PORT datad (498:498:498) (584:584:584)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\~21) + (DELAY + (ABSOLUTE + (PORT dataa (940:940:940) (1113:1113:1113)) + (PORT datab (506:506:506) (591:591:591)) + (PORT datad (915:915:915) (1079:1079:1079)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~3) + (DELAY + (ABSOLUTE + (PORT dataa (156:156:156) (212:212:212)) + (PORT datab (146:146:146) (196:196:196)) + (PORT datad (134:134:134) (173:173:173)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (450:450:450) (507:507:507)) + (PORT datab (631:631:631) (730:730:730)) + (PORT datac (460:460:460) (522:522:522)) + (PORT datad (102:102:102) (119:119:119)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (107:107:107) (139:139:139)) + (PORT datab (340:340:340) (398:398:398)) + (PORT datac (732:732:732) (845:845:845)) + (PORT datad (597:597:597) (698:698:698)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (810:810:810) (938:938:938)) + (PORT datab (533:533:533) (613:613:613)) + (PORT datac (313:313:313) (363:363:363)) + (PORT datad (335:335:335) (391:391:391)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (521:521:521) (610:610:610)) + (PORT datab (951:951:951) (1082:1082:1082)) + (PORT datac (731:731:731) (844:844:844)) + (PORT datad (170:170:170) (201:201:201)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~2) + (DELAY + (ABSOLUTE + (PORT dataa (880:880:880) (1036:1036:1036)) + (PORT datac (524:524:524) (619:619:619)) + (PORT datad (495:495:495) (583:583:583)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (651:651:651) (757:757:757)) + (PORT datab (583:583:583) (673:673:673)) + (PORT datac (507:507:507) (574:574:574)) + (PORT datad (114:114:114) (138:138:138)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (214:214:214) (261:261:261)) + (PORT datab (318:318:318) (373:373:373)) + (PORT datad (644:644:644) (749:749:749)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (493:493:493) (577:577:577)) + (PORT datab (132:132:132) (167:167:167)) + (PORT datad (476:476:476) (546:546:546)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (136:136:136)) + (PORT datab (103:103:103) (131:131:131)) + (PORT datac (89:89:89) (111:111:111)) + (PORT datad (517:517:517) (596:596:596)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (115:115:115) (145:145:145)) + (PORT datab (102:102:102) (129:129:129)) + (PORT datac (880:880:880) (1022:1022:1022)) + (PORT datad (304:304:304) (352:352:352)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (488:488:488) (569:569:569)) + (PORT datab (302:302:302) (345:345:345)) + (PORT datac (459:459:459) (532:532:532)) + (PORT datad (260:260:260) (293:293:293)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1135:1135:1135) (1314:1314:1314)) + (PORT datab (512:512:512) (588:588:588)) + (PORT datac (1207:1207:1207) (1394:1394:1394)) + (PORT datad (107:107:107) (125:125:125)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~32) (DELAY (ABSOLUTE - (PORT dataa (354:354:354) (421:421:421)) - (PORT datab (500:500:500) (585:585:585)) - (PORT datac (474:474:474) (552:552:552)) - (PORT datad (89:89:89) (106:106:106)) - (IOPATH dataa combout (158:158:158) (157:157:157)) + (PORT dataa (477:477:477) (553:553:553)) + (PORT datab (478:478:478) (577:577:577)) + (PORT datac (496:496:496) (568:568:568)) + (PORT datad (484:484:484) (565:565:565)) + (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -16292,12 +10928,118 @@ (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~33) (DELAY (ABSOLUTE - (PORT dataa (108:108:108) (142:142:142)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datac (646:646:646) (737:737:737)) - (PORT datad (109:109:109) (133:133:133)) + (PORT dataa (831:831:831) (978:978:978)) + (PORT datab (123:123:123) (155:155:155)) + (PORT datac (892:892:892) (1019:1019:1019)) + (PORT datad (1288:1288:1288) (1476:1476:1476)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (943:943:943) (1067:1067:1067)) + (PORT datab (350:350:350) (422:422:422)) + (PORT datac (748:748:748) (869:869:869)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (110:110:110) (144:144:144)) + (PORT datab (347:347:347) (407:407:407)) + (PORT datac (92:92:92) (116:116:116)) + (PORT datad (700:700:700) (824:824:824)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_73) + (DELAY + (ABSOLUTE + (PORT dataa (573:573:573) (648:648:648)) + (PORT datac (607:607:607) (696:696:696)) + (PORT datad (510:510:510) (576:576:576)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (909:909:909)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (665:665:665) (730:730:730)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_ir\~0) + (DELAY + (ABSOLUTE + (PORT datab (552:552:552) (658:658:658)) + (PORT datac (530:530:530) (625:625:625)) + (PORT datad (519:519:519) (611:611:611)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_ir\~1) + (DELAY + (ABSOLUTE + (PORT dataa (734:734:734) (868:868:868)) + (PORT datab (785:785:785) (891:891:891)) + (PORT datac (172:172:172) (208:208:208)) + (PORT datad (475:475:475) (568:568:568)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_60) + (DELAY + (ABSOLUTE + (PORT datab (524:524:524) (599:599:599)) + (PORT datac (606:606:606) (695:695:695)) + (PORT datad (432:432:432) (484:484:484)) + (IOPATH datab combout (166:166:166) (167:167:167)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -16305,13 +11047,3088 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_hi\~0) + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_61) (DELAY (ABSOLUTE - (PORT dataa (378:378:378) (461:461:461)) - (PORT datab (107:107:107) (136:136:136)) - (PORT datac (177:177:177) (213:213:213)) - (PORT datad (627:627:627) (725:725:725)) + (PORT datab (524:524:524) (599:599:599)) + (PORT datac (606:606:606) (696:696:696)) + (PORT datad (433:433:433) (484:484:484)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (909:909:909)) + (PORT asdata (279:279:279) (299:299:299)) + (PORT ena (766:766:766) (830:830:830)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_we_lo\~4) + (DELAY + (ABSOLUTE + (PORT datab (639:639:639) (735:735:735)) + (PORT datac (902:902:902) (1050:1050:1050)) + (PORT datad (511:511:511) (604:604:604)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo) + (DELAY + (ABSOLUTE + (PORT dataa (348:348:348) (416:416:416)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (985:985:985) (1128:1128:1128)) + (PORT datad (463:463:463) (532:532:532)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sw_4d_hi\~0) + (DELAY + (ABSOLUTE + (PORT dataa (600:600:600) (678:678:678)) + (PORT datab (524:524:524) (599:599:599)) + (PORT datac (635:635:635) (731:731:731)) + (PORT datad (430:430:430) (482:482:482)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (466:466:466) (539:539:539)) + (PORT datab (363:363:363) (435:435:435)) + (PORT datad (361:361:361) (431:431:431)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~11) + (DELAY + (ABSOLUTE + (PORT datab (365:365:365) (433:433:433)) + (PORT datac (188:188:188) (238:238:238)) + (PORT datad (161:161:161) (185:185:185)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[11\]) + (DELAY + (ABSOLUTE + (PORT dataa (357:357:357) (422:422:422)) + (PORT datac (306:306:306) (354:354:354)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_apin_mux\~1) + (DELAY + (ABSOLUTE + (PORT dataa (567:567:567) (678:678:678)) + (PORT datab (871:871:871) (1042:1042:1042)) + (PORT datac (610:610:610) (707:707:707)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~37) + (DELAY + (ABSOLUTE + (PORT dataa (740:740:740) (868:868:868)) + (PORT datab (759:759:759) (895:895:895)) + (PORT datac (971:971:971) (1103:1103:1103)) + (PORT datad (547:547:547) (635:635:635)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~2) + (DELAY + (ABSOLUTE + (PORT dataa (656:656:656) (766:766:766)) + (PORT datab (567:567:567) (660:660:660)) + (PORT datac (640:640:640) (741:741:741)) + (PORT datad (102:102:102) (119:119:119)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~40) + (DELAY + (ABSOLUTE + (PORT dataa (986:986:986) (1128:1128:1128)) + (PORT datab (760:760:760) (896:896:896)) + (PORT datac (863:863:863) (995:995:995)) + (PORT datad (817:817:817) (939:939:939)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1167:1167:1167) (1357:1357:1357)) + (PORT datab (115:115:115) (143:143:143)) + (PORT datac (639:639:639) (740:740:740)) + (PORT datad (994:994:994) (1164:1164:1164)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~5) + (DELAY + (ABSOLUTE + (PORT dataa (659:659:659) (771:771:771)) + (PORT datab (109:109:109) (140:140:140)) + (PORT datac (88:88:88) (110:110:110)) + (PORT datad (814:814:814) (936:936:936)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (385:385:385) (461:461:461)) + (PORT datab (629:629:629) (723:723:723)) + (PORT datac (868:868:868) (997:997:997)) + (PORT datad (813:813:813) (926:926:926)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla6M1T4_4) + (DELAY + (ABSOLUTE + (PORT dataa (736:736:736) (871:871:871)) + (PORT datab (529:529:529) (621:621:621)) + (PORT datac (911:911:911) (1047:1047:1047)) + (PORT datad (519:519:519) (620:620:620)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~42) + (DELAY + (ABSOLUTE + (PORT dataa (594:594:594) (701:701:701)) + (PORT datac (463:463:463) (545:545:545)) + (PORT datad (918:918:918) (1034:1034:1034)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (115:115:115) (146:146:146)) + (PORT datab (110:110:110) (141:141:141)) + (PORT datac (463:463:463) (536:536:536)) + (PORT datad (725:725:725) (849:849:849)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_1d\~4) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (428:428:428)) + (PORT datab (380:380:380) (453:453:453)) + (PORT datac (520:520:520) (608:608:608)) + (PORT datad (628:628:628) (720:720:720)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~3) + (DELAY + (ABSOLUTE + (PORT datab (506:506:506) (601:601:601)) + (PORT datac (319:319:319) (375:375:375)) + (PORT datad (321:321:321) (373:373:373)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~9) + (DELAY + (ABSOLUTE + (PORT dataa (476:476:476) (564:564:564)) + (PORT datab (702:702:702) (810:810:810)) + (PORT datac (1000:1000:1000) (1147:1147:1147)) + (PORT datad (790:790:790) (901:901:901)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1016:1016:1016) (1172:1172:1172)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (931:931:931) (1061:1061:1061)) + (PORT datad (790:790:790) (900:900:900)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1144:1144:1144) (1316:1316:1316)) + (PORT datab (790:790:790) (907:907:907)) + (PORT datac (355:355:355) (418:418:418)) + (PORT datad (603:603:603) (692:692:692)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~2) + (DELAY + (ABSOLUTE + (PORT dataa (214:214:214) (260:260:260)) + (PORT datab (117:117:117) (145:145:145)) + (PORT datad (447:447:447) (534:534:534)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~11) + (DELAY + (ABSOLUTE + (PORT dataa (185:185:185) (228:228:228)) + (PORT datab (951:951:951) (1081:1081:1081)) + (PORT datac (729:729:729) (841:841:841)) + (PORT datad (95:95:95) (115:115:115)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~12) + (DELAY + (ABSOLUTE + (PORT datac (461:461:461) (534:534:534)) + (PORT datad (452:452:452) (508:508:508)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1014:1014:1014) (1178:1178:1178)) + (PORT datab (128:128:128) (160:160:160)) + (PORT datac (355:355:355) (423:423:423)) + (PORT datad (491:491:491) (565:565:565)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~5) + (DELAY + (ABSOLUTE + (PORT dataa (478:478:478) (557:557:557)) + (PORT datab (325:325:325) (385:385:385)) + (PORT datac (182:182:182) (220:220:220)) + (PORT datad (323:323:323) (377:377:377)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~14) + (DELAY + (ABSOLUTE + (PORT dataa (772:772:772) (907:907:907)) + (PORT datab (633:633:633) (730:730:730)) + (PORT datac (347:347:347) (413:413:413)) + (PORT datad (657:657:657) (772:772:772)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~10) + (DELAY + (ABSOLUTE + (PORT dataa (198:198:198) (238:238:238)) + (PORT datac (578:578:578) (655:655:655)) + (PORT datad (305:305:305) (348:348:348)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1045:1045:1045) (1197:1197:1197)) + (PORT datab (207:207:207) (246:246:246)) + (PORT datac (823:823:823) (940:940:940)) + (PORT datad (188:188:188) (222:222:222)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~7) + (DELAY + (ABSOLUTE + (PORT dataa (645:645:645) (749:749:749)) + (PORT datab (321:321:321) (374:374:374)) + (PORT datac (179:179:179) (217:217:217)) + (PORT datad (118:118:118) (142:142:142)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (472:472:472) (549:549:549)) + (PORT datab (353:353:353) (424:424:424)) + (PORT datac (1005:1005:1005) (1133:1133:1133)) + (PORT datad (332:332:332) (384:384:384)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~9) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (406:406:406)) + (PORT datab (820:820:820) (942:942:942)) + (PORT datac (332:332:332) (390:390:390)) + (PORT datad (92:92:92) (109:109:109)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~11) + (DELAY + (ABSOLUTE + (PORT dataa (320:320:320) (377:377:377)) + (PORT datab (108:108:108) (138:138:138)) + (PORT datac (89:89:89) (110:110:110)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~12) + (DELAY + (ABSOLUTE + (PORT dataa (125:125:125) (160:160:160)) + (PORT datab (956:956:956) (1109:1109:1109)) + (PORT datac (173:173:173) (209:209:209)) + (PORT datad (877:877:877) (1009:1009:1009)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (909:909:909)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (905:905:905) (891:891:891)) + (PORT ena (904:904:904) (977:977:977)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIOWrite\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1208:1208:1208) (1405:1405:1405)) + (PORT datab (1284:1284:1284) (1486:1486:1486)) + (PORT datac (869:869:869) (1022:1022:1022)) + (PORT datad (1127:1127:1127) (1295:1295:1295)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1436:1436:1436) (1668:1668:1668)) + (PORT datab (639:639:639) (737:737:737)) + (PORT datac (346:346:346) (403:403:403)) + (PORT datad (492:492:492) (579:579:579)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (891:891:891) (1036:1036:1036)) + (PORT datab (111:111:111) (143:143:143)) + (PORT datac (103:103:103) (125:125:125)) + (PORT datad (633:633:633) (722:722:722)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~9) + (DELAY + (ABSOLUTE + (PORT dataa (123:123:123) (157:157:157)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (446:446:446) (510:510:510)) + (PORT datad (339:339:339) (408:408:408)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[1\]) + (DELAY + (ABSOLUTE + (PORT dataa (331:331:331) (395:395:395)) + (PORT datac (499:499:499) (585:585:585)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (915:915:915)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (911:911:911) (895:895:895)) + (PORT ena (1070:1070:1070) (1171:1171:1171)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_apin_mux\~0) + (DELAY + (ABSOLUTE + (PORT dataa (113:113:113) (148:148:148)) + (PORT datab (114:114:114) (141:141:141)) + (PORT datac (112:112:112) (139:139:139)) + (PORT datad (652:652:652) (754:754:754)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1045:1045:1045) (1196:1196:1196)) + (PORT datab (1042:1042:1042) (1210:1210:1210)) + (PORT datac (102:102:102) (123:123:123)) + (PORT datad (688:688:688) (785:785:785)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1076:1076:1076) (1258:1258:1258)) + (PORT datac (999:999:999) (1162:1162:1162)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_40\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1019:1019:1019) (1196:1196:1196)) + (PORT datab (207:207:207) (265:265:265)) + (PORT datac (711:711:711) (801:801:801)) + (PORT datad (106:106:106) (132:132:132)) + (IOPATH dataa combout (188:188:188) (179:179:179)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~21) + (DELAY + (ABSOLUTE + (PORT dataa (643:643:643) (739:739:739)) + (PORT datab (847:847:847) (995:995:995)) + (PORT datac (699:699:699) (794:794:794)) + (PORT datad (631:631:631) (726:726:726)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (1074:1074:1074) (1247:1247:1247)) + (PORT datab (683:683:683) (808:808:808)) + (PORT datac (101:101:101) (123:123:123)) + (PORT datad (1120:1120:1120) (1287:1287:1287)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (968:968:968) (1131:1131:1131)) + (PORT datab (122:122:122) (154:154:154)) + (PORT datac (892:892:892) (1018:1018:1018)) + (PORT datad (1023:1023:1023) (1190:1190:1190)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (137:137:137)) + (PORT datab (937:937:937) (1086:1086:1086)) + (PORT datac (461:461:461) (545:545:545)) + (PORT datad (807:807:807) (948:948:948)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (111:111:111) (144:144:144)) + (PORT datab (800:800:800) (912:912:912)) + (PORT datac (90:90:90) (111:111:111)) + (PORT datad (775:775:775) (918:918:918)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_63) + (DELAY + (ABSOLUTE + (PORT datab (503:503:503) (578:578:578)) + (PORT datac (631:631:631) (726:726:726)) + (PORT datad (432:432:432) (483:483:483)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (633:633:633) (693:693:693)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~49) + (DELAY + (ABSOLUTE + (PORT dataa (1091:1091:1091) (1239:1239:1239)) + (PORT datab (706:706:706) (825:825:825)) + (PORT datac (509:509:509) (583:583:583)) + (PORT datad (630:630:630) (729:729:729)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~2) + (DELAY + (ABSOLUTE + (PORT datac (468:468:468) (539:539:539)) + (PORT datad (362:362:362) (429:429:429)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~50) + (DELAY + (ABSOLUTE + (PORT dataa (117:117:117) (148:148:148)) + (PORT datab (714:714:714) (836:836:836)) + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (312:312:312) (360:360:360)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (514:514:514) (599:599:599)) + (PORT datab (990:990:990) (1137:1137:1137)) + (PORT datac (374:374:374) (448:448:448)) + (PORT datad (493:493:493) (574:574:574)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_oe\~1) + (DELAY + (ABSOLUTE + (PORT dataa (121:121:121) (154:154:154)) + (PORT datab (128:128:128) (156:156:156)) + (PORT datac (339:339:339) (401:401:401)) + (PORT datad (687:687:687) (794:794:794)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~13) + (DELAY + (ABSOLUTE + (PORT dataa (481:481:481) (556:556:556)) + (PORT datab (690:690:690) (809:809:809)) + (PORT datac (464:464:464) (539:539:539)) + (PORT datad (683:683:683) (796:796:796)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~12) + (DELAY + (ABSOLUTE + (PORT datab (470:470:470) (544:544:544)) + (PORT datac (296:296:296) (344:344:344)) + (PORT datad (289:289:289) (320:320:320)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1070:1070:1070) (1218:1218:1218)) + (PORT datab (766:766:766) (878:878:878)) + (PORT datac (303:303:303) (357:357:357)) + (PORT datad (835:835:835) (993:993:993)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~13) + (DELAY + (ABSOLUTE + (PORT dataa (752:752:752) (872:872:872)) + (PORT datab (689:689:689) (809:809:809)) + (PORT datac (554:554:554) (636:636:636)) + (PORT datad (480:480:480) (547:547:547)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (808:808:808) (924:924:924)) + (PORT datab (110:110:110) (141:141:141)) + (PORT datac (185:185:185) (220:220:220)) + (PORT datad (107:107:107) (126:126:126)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (621:621:621) (716:716:716)) + (PORT datab (119:119:119) (148:148:148)) + (PORT datac (589:589:589) (674:674:674)) + (PORT datad (643:643:643) (736:736:736)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (630:630:630) (727:727:727)) + (PORT datab (116:116:116) (145:145:145)) + (PORT datac (683:683:683) (801:801:801)) + (PORT datad (339:339:339) (390:390:390)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (574:574:574) (662:662:662)) + (PORT datab (347:347:347) (404:404:404)) + (PORT datac (458:458:458) (523:523:523)) + (PORT datad (96:96:96) (116:116:116)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~10) + (DELAY + (ABSOLUTE + (PORT dataa (123:123:123) (157:157:157)) + (PORT datab (624:624:624) (751:751:751)) + (PORT datac (1048:1048:1048) (1201:1201:1201)) + (PORT datad (813:813:813) (926:926:926)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_1d\~9) + (DELAY + (ABSOLUTE + (PORT datab (1029:1029:1029) (1199:1199:1199)) + (PORT datac (1206:1206:1206) (1396:1396:1396)) + (PORT datad (470:470:470) (548:548:548)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1260:1260:1260) (1463:1463:1463)) + (PORT datab (552:552:552) (681:681:681)) + (PORT datac (102:102:102) (123:123:123)) + (PORT datad (713:713:713) (801:801:801)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (549:549:549) (642:642:642)) + (PORT datab (482:482:482) (577:577:577)) + (PORT datad (185:185:185) (216:216:216)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~7) + (DELAY + (ABSOLUTE + (PORT dataa (212:212:212) (254:254:254)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (287:287:287) (332:332:332)) + (PORT datad (93:93:93) (113:113:113)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (641:641:641) (764:764:764)) + (PORT datab (906:906:906) (1064:1064:1064)) + (PORT datac (318:318:318) (367:367:367)) + (PORT datad (100:100:100) (122:122:122)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (1282:1282:1282) (1485:1485:1485)) + (PORT datab (485:485:485) (563:563:563)) + (PORT datac (1154:1154:1154) (1321:1321:1321)) + (PORT datad (1173:1173:1173) (1337:1337:1337)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~2) + (DELAY + (ABSOLUTE + (PORT dataa (915:915:915) (1061:1061:1061)) + (PORT datab (766:766:766) (891:891:891)) + (PORT datac (1155:1155:1155) (1322:1322:1322)) + (PORT datad (687:687:687) (775:775:775)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~3) + (DELAY + (ABSOLUTE + (PORT dataa (488:488:488) (568:568:568)) + (PORT datab (106:106:106) (136:136:136)) + (PORT datac (89:89:89) (110:110:110)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (531:531:531) (622:622:622)) + (PORT datab (368:368:368) (435:435:435)) + (PORT datac (470:470:470) (541:541:541)) + (PORT datad (487:487:487) (562:562:562)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (353:353:353) (423:423:423)) + (PORT datab (1011:1011:1011) (1146:1146:1146)) + (PORT datac (166:166:166) (195:195:195)) + (PORT datad (338:338:338) (396:396:396)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (297:297:297) (353:353:353)) + (PORT datab (852:852:852) (1015:1015:1015)) + (PORT datac (305:305:305) (359:359:359)) + (PORT datad (737:737:737) (871:871:871)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla30npla13M4T3_5) + (DELAY + (ABSOLUTE + (PORT dataa (723:723:723) (855:855:855)) + (PORT datab (1361:1361:1361) (1586:1586:1586)) + (PORT datac (587:587:587) (672:672:672)) + (PORT datad (641:641:641) (734:734:734)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (521:521:521) (609:609:609)) + (PORT datab (521:521:521) (600:600:600)) + (PORT datac (881:881:881) (1006:1006:1006)) + (PORT datad (617:617:617) (691:691:691)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (646:646:646) (732:732:732)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (832:832:832) (952:952:952)) + (PORT datad (508:508:508) (585:585:585)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (533:533:533) (641:641:641)) + (PORT datab (842:842:842) (982:982:982)) + (PORT datac (691:691:691) (806:806:806)) + (PORT datad (619:619:619) (718:718:718)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (454:454:454) (531:531:531)) + (PORT datab (954:954:954) (1108:1108:1108)) + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (876:876:876) (1007:1007:1007)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (103:103:103) (124:124:124)) + (PORT datad (333:333:333) (388:388:388)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (120:120:120) (153:153:153)) + (PORT datab (538:538:538) (625:625:625)) + (PORT datac (348:348:348) (413:413:413)) + (PORT datad (874:874:874) (1005:1005:1005)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (923:923:923) (1058:1058:1058)) + (PORT datab (651:651:651) (754:754:754)) + (PORT datac (465:465:465) (539:539:539)) + (PORT datad (453:453:453) (520:520:520)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (133:133:133)) + (PORT datab (353:353:353) (420:420:420)) + (PORT datac (301:301:301) (343:343:343)) + (PORT datad (188:188:188) (222:222:222)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (1173:1173:1173) (1341:1341:1341)) + (PORT datab (631:631:631) (740:740:740)) + (PORT datac (1267:1267:1267) (1461:1461:1461)) + (PORT datad (753:753:753) (868:868:868)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (486:486:486) (565:565:565)) + (PORT datab (225:225:225) (265:265:265)) + (PORT datac (492:492:492) (580:580:580)) + (PORT datad (102:102:102) (119:119:119)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (106:106:106) (138:138:138)) + (PORT datab (108:108:108) (138:138:138)) + (PORT datac (318:318:318) (375:375:375)) + (PORT datad (102:102:102) (119:119:119)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (808:808:808) (924:924:924)) + (PORT datab (119:119:119) (148:148:148)) + (PORT datac (372:372:372) (438:438:438)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (526:526:526) (617:617:617)) + (PORT datab (110:110:110) (143:143:143)) + (PORT datad (486:486:486) (561:561:561)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (326:326:326) (380:380:380)) + (PORT datab (590:590:590) (682:682:682)) + (PORT datac (459:459:459) (533:533:533)) + (PORT datad (639:639:639) (732:732:732)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (216:216:216) (258:258:258)) + (PORT datab (210:210:210) (255:255:255)) + (PORT datac (95:95:95) (120:120:120)) + (PORT datad (89:89:89) (106:106:106)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal2\~2) + (DELAY + (ABSOLUTE + (PORT dataa (432:432:432) (535:535:535)) + (PORT datab (1097:1097:1097) (1287:1287:1287)) + (PORT datac (730:730:730) (853:853:853)) + (PORT datad (480:480:480) (540:540:540)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal1\~6) + (DELAY + (ABSOLUTE + (PORT dataa (194:194:194) (243:243:243)) + (PORT datab (722:722:722) (863:863:863)) + (PORT datac (467:467:467) (556:556:556)) + (PORT datad (183:183:183) (218:218:218)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|bank_exx\~2) + (DELAY + (ABSOLUTE + (PORT dataa (477:477:477) (556:556:556)) + (PORT datab (796:796:796) (929:929:929)) + (PORT datad (659:659:659) (778:778:778)) + (IOPATH dataa combout (188:188:188) (203:203:203)) + (IOPATH datab combout (190:190:190) (205:205:205)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_control_\|bank_exx) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (910:910:910) (897:897:897)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|bank_hl_de1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (524:524:524) (607:607:607)) + (PORT datab (344:344:344) (408:408:408)) + (PORT datad (153:153:153) (201:201:201)) + (IOPATH dataa combout (181:181:181) (193:193:193)) + (IOPATH datab combout (191:191:191) (188:188:188)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_control_\|bank_hl_de1) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (910:910:910) (897:897:897)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (335:335:335) (401:401:401)) + (PORT datab (429:429:429) (525:525:525)) + (PORT datac (648:648:648) (753:753:753)) + (PORT datad (900:900:900) (1014:1014:1014)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (502:502:502) (590:590:590)) + (PORT datac (324:324:324) (365:365:365)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (453:453:453) (527:527:527)) + (PORT datab (302:302:302) (350:350:350)) + (PORT datac (465:465:465) (541:541:541)) + (PORT datad (97:97:97) (118:118:118)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (109:109:109) (143:143:143)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (433:433:433) (491:491:491)) + (PORT datad (525:525:525) (612:612:612)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (540:540:540) (628:628:628)) + (PORT datab (704:704:704) (822:822:822)) + (PORT datac (955:955:955) (1103:1103:1103)) + (PORT datad (336:336:336) (385:385:385)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~45) + (DELAY + (ABSOLUTE + (PORT dataa (296:296:296) (352:352:352)) + (PORT datab (324:324:324) (381:381:381)) + (PORT datac (1207:1207:1207) (1396:1396:1396)) + (PORT datad (998:998:998) (1160:1160:1160)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~2) + (DELAY + (ABSOLUTE + (PORT dataa (122:122:122) (156:156:156)) + (PORT datab (937:937:937) (1059:1059:1059)) + (PORT datac (573:573:573) (679:679:679)) + (PORT datad (723:723:723) (847:847:847)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~3) + (DELAY + (ABSOLUTE + (PORT dataa (126:126:126) (161:161:161)) + (PORT datab (640:640:640) (737:737:737)) + (PORT datac (104:104:104) (131:131:131)) + (PORT datad (876:876:876) (1015:1015:1015)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (402:402:402)) + (PORT datab (115:115:115) (144:144:144)) + (PORT datac (105:105:105) (128:128:128)) + (PORT datad (477:477:477) (567:567:567)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (346:346:346) (405:405:405)) + (PORT datab (769:769:769) (912:912:912)) + (PORT datac (630:630:630) (712:712:712)) + (PORT datad (508:508:508) (585:585:585)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (600:600:600) (691:691:691)) + (PORT datab (379:379:379) (452:452:452)) + (PORT datac (349:349:349) (403:403:403)) + (PORT datad (875:875:875) (1006:1006:1006)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (639:639:639) (736:736:736)) + (PORT datab (501:501:501) (581:581:581)) + (PORT datac (452:452:452) (514:514:514)) + (PORT datad (470:470:470) (536:536:536)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~34) + (DELAY + (ABSOLUTE + (PORT datab (173:173:173) (210:210:210)) + (PORT datac (93:93:93) (116:116:116)) + (PORT datad (503:503:503) (597:597:597)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (301:301:301) (350:350:350)) + (PORT datac (408:408:408) (467:467:467)) + (PORT datad (163:163:163) (191:191:191)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (477:477:477) (569:569:569)) + (PORT datab (357:357:357) (422:422:422)) + (PORT datac (516:516:516) (602:602:602)) + (PORT datad (727:727:727) (851:851:851)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (600:600:600) (692:692:692)) + (PORT datab (701:701:701) (829:829:829)) + (PORT datac (520:520:520) (608:608:608)) + (PORT datad (534:534:534) (619:619:619)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (332:332:332) (391:391:391)) + (PORT datab (721:721:721) (824:824:824)) + (PORT datac (520:520:520) (608:608:608)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (476:476:476) (545:545:545)) + (PORT datab (707:707:707) (832:832:832)) + (PORT datac (875:875:875) (993:993:993)) + (PORT datad (368:368:368) (434:434:434)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (1043:1043:1043) (1211:1211:1211)) + (PORT datab (1015:1015:1015) (1192:1192:1192)) + (PORT datac (100:100:100) (126:126:126)) + (PORT datad (637:637:637) (726:726:726)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (574:574:574) (651:651:651)) + (PORT datab (342:342:342) (399:399:399)) + (PORT datac (569:569:569) (640:640:640)) + (PORT datad (632:632:632) (720:720:720)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (189:189:189) (225:225:225)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (93:93:93) (115:115:115)) + (PORT datad (924:924:924) (1070:1070:1070)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (115:115:115) (150:150:150)) + (PORT datab (574:574:574) (658:658:658)) + (PORT datac (480:480:480) (547:547:547)) + (PORT datad (781:781:781) (892:892:892)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (534:534:534) (635:635:635)) + (PORT datab (562:562:562) (645:645:645)) + (PORT datac (918:918:918) (1065:1065:1065)) + (PORT datad (444:444:444) (509:509:509)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (377:377:377) (456:456:456)) + (PORT datab (220:220:220) (276:276:276)) + (PORT datac (341:341:341) (402:402:402)) + (PORT datad (127:127:127) (164:164:164)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (364:364:364) (445:445:445)) + (PORT datab (946:946:946) (1095:1095:1095)) + (PORT datac (186:186:186) (222:222:222)) + (PORT datad (868:868:868) (1006:1006:1006)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (383:383:383) (465:465:465)) + (PORT datab (682:682:682) (818:818:818)) + (PORT datac (397:397:397) (486:486:486)) + (PORT datad (647:647:647) (763:763:763)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (412:412:412) (510:510:510)) + (PORT datab (655:655:655) (745:745:745)) + (PORT datac (665:665:665) (800:800:800)) + (PORT datad (747:747:747) (870:870:870)) + (IOPATH dataa combout (159:159:159) (173:173:173)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (500:500:500) (602:602:602)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (90:90:90) (111:111:111)) + (PORT datad (624:624:624) (711:711:711)) + (IOPATH dataa combout (172:172:172) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (393:393:393) (476:476:476)) + (PORT datab (345:345:345) (401:401:401)) + (PORT datac (436:436:436) (499:499:499)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (299:299:299) (349:349:349)) + (PORT datab (187:187:187) (224:224:224)) + (PORT datac (474:474:474) (538:538:538)) + (PORT datad (90:90:90) (106:106:106)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_de2\~5) + (DELAY + (ABSOLUTE + (PORT dataa (260:260:260) (333:333:333)) + (PORT datab (265:265:265) (332:332:332)) + (PORT datac (445:445:445) (515:515:515)) + (PORT datad (492:492:492) (568:568:568)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_de2\~6) + (DELAY + (ABSOLUTE + (PORT dataa (297:297:297) (346:346:346)) + (PORT datab (174:174:174) (212:212:212)) + (PORT datac (411:411:411) (470:470:470)) + (PORT datad (104:104:104) (121:121:121)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_de\~0) + (DELAY + (ABSOLUTE + (PORT dataa (136:136:136) (189:189:189)) + (PORT datab (163:163:163) (218:218:218)) + (PORT datac (581:581:581) (662:662:662)) + (PORT datad (101:101:101) (123:123:123)) + (IOPATH dataa combout (170:170:170) (165:165:165)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_50) + (DELAY + (ABSOLUTE + (PORT dataa (389:389:389) (473:473:473)) + (PORT datac (448:448:448) (513:513:513)) + (PORT datad (337:337:337) (395:395:395)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|bank_hl_de2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (525:525:525) (608:608:608)) + (PORT datab (341:341:341) (404:404:404)) + (PORT datad (151:151:151) (195:195:195)) + (IOPATH dataa combout (159:159:159) (173:173:173)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_control_\|bank_hl_de2) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (910:910:910) (897:897:897)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_de2\~4) + (DELAY + (ABSOLUTE + (PORT dataa (135:135:135) (186:186:186)) + (PORT datab (163:163:163) (219:219:219)) + (PORT datac (579:579:579) (661:661:661)) + (PORT datad (102:102:102) (125:125:125)) + (IOPATH dataa combout (181:181:181) (175:175:175)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_46) + (DELAY + (ABSOLUTE + (PORT dataa (392:392:392) (477:477:477)) + (PORT datac (449:449:449) (515:515:515)) + (PORT datad (350:350:350) (413:413:413)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_47) + (DELAY + (ABSOLUTE + (PORT dataa (392:392:392) (477:477:477)) + (PORT datac (449:449:449) (516:516:516)) + (PORT datad (350:350:350) (413:413:413)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (919:919:919)) + (PORT asdata (853:853:853) (947:947:947)) + (PORT ena (501:501:501) (535:535:535)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_51) + (DELAY + (ABSOLUTE + (PORT dataa (391:391:391) (475:475:475)) + (PORT datac (449:449:449) (515:515:515)) + (PORT datad (337:337:337) (394:394:394)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (919:919:919)) + (PORT asdata (851:851:851) (946:946:946)) + (PORT ena (502:502:502) (534:534:534)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (217:217:217) (261:261:261)) + (PORT datab (232:232:232) (275:275:275)) + (PORT datad (116:116:116) (153:153:153)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_hl\~0) + (DELAY + (ABSOLUTE + (PORT dataa (134:134:134) (186:186:186)) + (PORT datab (164:164:164) (221:221:221)) + (PORT datac (577:577:577) (658:658:658)) + (PORT datad (104:104:104) (127:127:127)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_59) + (DELAY + (ABSOLUTE + (PORT dataa (495:495:495) (588:588:588)) + (PORT datab (359:359:359) (426:426:426)) + (PORT datad (328:328:328) (382:382:382)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (907:907:907) (911:911:911)) + (PORT asdata (465:465:465) (502:502:502)) + (PORT ena (505:505:505) (542:542:542)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_hl2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (134:134:134) (186:186:186)) + (PORT datab (162:162:162) (218:218:218)) + (PORT datac (582:582:582) (664:664:664)) + (PORT datad (99:99:99) (122:122:122)) + (IOPATH dataa combout (158:158:158) (173:173:173)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_54) + (DELAY + (ABSOLUTE + (PORT dataa (492:492:492) (585:585:585)) + (PORT datab (651:651:651) (754:754:754)) + (PORT datad (352:352:352) (412:412:412)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_55) + (DELAY + (ABSOLUTE + (PORT dataa (494:494:494) (587:587:587)) + (PORT datab (650:650:650) (753:753:753)) + (PORT datad (347:347:347) (407:407:407)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (907:907:907) (911:911:911)) + (PORT asdata (464:464:464) (501:501:501)) + (PORT ena (417:417:417) (434:434:434)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_58) + (DELAY + (ABSOLUTE + (PORT dataa (494:494:494) (587:587:587)) + (PORT datac (342:342:342) (403:403:403)) + (PORT datad (328:328:328) (381:381:381)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (130:130:130) (181:181:181)) + (PORT datab (138:138:138) (174:174:174)) + (PORT datad (122:122:122) (144:144:144)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_70\~2) + (DELAY + (ABSOLUTE + (PORT datab (641:641:641) (745:745:745)) + (PORT datac (517:517:517) (621:621:621)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_38\~0) + (DELAY + (ABSOLUTE + (PORT dataa (546:546:546) (653:653:653)) + (PORT datab (420:420:420) (499:499:499)) + (PORT datac (343:343:343) (405:405:405)) + (PORT datad (514:514:514) (589:589:589)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_71\~2) + (DELAY + (ABSOLUTE + (PORT datab (639:639:639) (743:743:743)) + (PORT datac (512:512:512) (614:614:614)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_43\~0) + (DELAY + (ABSOLUTE + (PORT dataa (552:552:552) (661:661:661)) + (PORT datab (414:414:414) (492:492:492)) + (PORT datac (341:341:341) (399:399:399)) + (PORT datad (512:512:512) (587:587:587)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (672:672:672) (740:740:740)) + (PORT ena (644:644:644) (699:699:699)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_39\~0) + (DELAY + (ABSOLUTE + (PORT dataa (550:550:550) (659:659:659)) + (PORT datab (417:417:417) (496:496:496)) + (PORT datac (342:342:342) (400:400:400)) + (PORT datad (513:513:513) (588:588:588)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (670:670:670) (739:739:739)) + (PORT ena (634:634:634) (686:686:686)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_42\~0) + (DELAY + (ABSOLUTE + (PORT dataa (550:550:550) (657:657:657)) + (PORT datab (414:414:414) (492:492:492)) + (PORT datac (347:347:347) (410:410:410)) + (PORT datad (512:512:512) (587:587:587)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (479:479:479) (562:562:562)) + (PORT datab (131:131:131) (180:180:180)) + (PORT datad (363:363:363) (434:434:434)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~15) + (DELAY + (ABSOLUTE + (PORT dataa (110:110:110) (144:144:144)) + (PORT datab (350:350:350) (410:410:410)) + (PORT datac (557:557:557) (639:639:639)) + (PORT datad (95:95:95) (115:115:115)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~18) + (DELAY + (ABSOLUTE + (PORT dataa (598:598:598) (680:680:680)) + (PORT datab (799:799:799) (911:911:911)) + (PORT datac (179:179:179) (215:215:215)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_83) + (DELAY + (ABSOLUTE + (PORT dataa (544:544:544) (627:627:627)) + (PORT datac (636:636:636) (732:732:732)) + (PORT datad (494:494:494) (560:560:560)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (907:907:907) (912:912:912)) + (PORT asdata (850:850:850) (943:943:943)) + (PORT ena (669:669:669) (725:725:725)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_82) + (DELAY + (ABSOLUTE + (PORT dataa (544:544:544) (627:627:627)) + (PORT datac (632:632:632) (727:727:727)) + (PORT datad (490:490:490) (556:556:556)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~37) + (DELAY + (ABSOLUTE + (PORT datab (333:333:333) (396:396:396)) + (PORT datad (509:509:509) (591:591:591)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_66\~0) + (DELAY + (ABSOLUTE + (PORT dataa (366:366:366) (430:430:430)) + (PORT datab (521:521:521) (613:613:613)) + (PORT datac (506:506:506) (580:580:580)) + (PORT datad (397:397:397) (467:467:467)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_iy\~2) + (DELAY + (ABSOLUTE + (PORT dataa (255:255:255) (328:328:328)) + (PORT datab (268:268:268) (336:336:336)) + (PORT datac (448:448:448) (517:517:517)) + (PORT datad (492:492:492) (569:569:569)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_71) + (DELAY + (ABSOLUTE + (PORT datab (594:594:594) (678:678:678)) + (PORT datac (450:450:450) (518:518:518)) + (PORT datad (629:629:629) (726:726:726)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (907:907:907) (911:911:911)) + (PORT asdata (700:700:700) (775:775:775)) + (PORT ena (405:405:405) (422:422:422)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_67\~0) + (DELAY + (ABSOLUTE + (PORT dataa (356:356:356) (422:422:422)) + (PORT datab (410:410:410) (489:489:489)) + (PORT datac (505:505:505) (580:580:580)) + (PORT datad (506:506:506) (588:588:588)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (907:907:907) (911:911:911)) + (PORT asdata (700:700:700) (775:775:775)) + (PORT ena (677:677:677) (748:748:748)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_70) + (DELAY + (ABSOLUTE + (PORT datab (594:594:594) (678:678:678)) + (PORT datac (450:450:450) (518:518:518)) + (PORT datad (629:629:629) (725:725:725)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (370:370:370) (448:448:448)) + (PORT datab (128:128:128) (176:176:176)) + (PORT datad (125:125:125) (149:149:149)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla37pla28M2T3_4) + (DELAY + (ABSOLUTE + (PORT dataa (691:691:691) (807:807:807)) + (PORT datab (1166:1166:1166) (1363:1363:1363)) + (PORT datac (923:923:923) (1077:1077:1077)) + (PORT datad (371:371:371) (436:436:436)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~9) + (DELAY + (ABSOLUTE + (PORT dataa (601:601:601) (681:681:681)) + (PORT datab (1122:1122:1122) (1291:1291:1291)) + (PORT datac (998:998:998) (1145:1145:1145)) + (PORT datad (300:300:300) (346:346:346)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~10) + (DELAY + (ABSOLUTE + (PORT dataa (587:587:587) (695:695:695)) + (PORT datac (285:285:285) (329:329:329)) + (PORT datad (163:163:163) (190:190:190)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_lo\~8) + (DELAY + (ABSOLUTE + (PORT dataa (585:585:585) (667:667:667)) + (PORT datab (644:644:644) (735:735:735)) + (PORT datac (489:489:489) (575:575:575)) + (PORT datad (96:96:96) (116:116:116)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (102:102:102) (119:119:119)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1222:1222:1222) (1421:1421:1421)) + (PORT datab (566:566:566) (704:704:704)) + (PORT datac (1011:1011:1011) (1177:1177:1177)) + (PORT datad (471:471:471) (548:548:548)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~5) + (DELAY + (ABSOLUTE + (PORT dataa (503:503:503) (593:593:593)) + (PORT datab (196:196:196) (235:235:235)) + (PORT datac (348:348:348) (406:406:406)) + (PORT datad (329:329:329) (375:375:375)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~6) + (DELAY + (ABSOLUTE + (PORT dataa (184:184:184) (220:220:220)) + (PORT datab (491:491:491) (590:590:590)) + (PORT datac (452:452:452) (513:513:513)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_79\~0) + (DELAY + (ABSOLUTE + (PORT dataa (468:468:468) (549:549:549)) + (PORT datab (416:416:416) (495:495:495)) + (PORT datac (342:342:342) (400:400:400)) + (PORT datad (513:513:513) (588:588:588)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (911:911:911)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (768:768:768) (845:845:845)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_1d\~5) + (DELAY + (ABSOLUTE + (PORT dataa (477:477:477) (553:553:553)) + (PORT datab (431:431:431) (527:527:527)) + (PORT datac (650:650:650) (756:756:756)) + (PORT datad (104:104:104) (121:121:121)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_im_we) + (DELAY + (ABSOLUTE + (PORT dataa (1136:1136:1136) (1320:1320:1320)) + (PORT datab (1046:1046:1046) (1219:1219:1219)) + (PORT datac (1050:1050:1050) (1220:1220:1220)) + (PORT datad (940:940:940) (1077:1077:1077)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_1d\~6) + (DELAY + (ABSOLUTE + (PORT dataa (335:335:335) (401:401:401)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (465:465:465) (539:539:539)) + (PORT datad (352:352:352) (403:403:403)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_1d\~7) + (DELAY + (ABSOLUTE + (PORT dataa (468:468:468) (545:545:545)) + (PORT datab (739:739:739) (839:839:839)) + (PORT datac (334:334:334) (402:402:402)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_ds\[2\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (444:444:444) (514:514:514)) + (PORT datab (624:624:624) (715:715:715)) + (PORT datac (348:348:348) (414:414:414)) + (PORT datad (680:680:680) (770:770:770)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[2\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (458:458:458) (534:534:534)) + (PORT datab (194:194:194) (233:233:233)) + (PORT datac (216:216:216) (264:264:264)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~11) + (DELAY + (ABSOLUTE + (PORT dataa (115:115:115) (146:146:146)) + (PORT datab (350:350:350) (410:410:410)) + (PORT datac (491:491:491) (562:562:562)) + (PORT datad (1119:1119:1119) (1287:1287:1287)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~12) + (DELAY + (ABSOLUTE + (PORT dataa (107:107:107) (140:140:140)) + (PORT datab (847:847:847) (976:976:976)) + (PORT datac (461:461:461) (522:522:522)) + (PORT datad (99:99:99) (120:120:120)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (719:719:719) (828:828:828)) + (PORT datab (781:781:781) (899:899:899)) + (PORT datac (908:908:908) (1034:1034:1034)) + (PORT datad (196:196:196) (231:231:231)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (427:427:427)) + (PORT datab (652:652:652) (741:741:741)) + (PORT datac (364:364:364) (436:436:436)) + (PORT datad (616:616:616) (706:706:706)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (597:597:597) (688:688:688)) + (PORT datab (538:538:538) (632:632:632)) + (PORT datac (322:322:322) (378:378:378)) + (PORT datad (528:528:528) (613:613:613)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (134:134:134)) + (PORT datab (373:373:373) (450:450:450)) + (PORT datac (92:92:92) (114:114:114)) + (PORT datad (329:329:329) (366:366:366)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~41) + (DELAY + (ABSOLUTE + (PORT dataa (180:180:180) (224:224:224)) + (PORT datab (587:587:587) (680:680:680)) + (PORT datac (473:473:473) (541:541:541)) + (PORT datad (305:305:305) (354:354:354)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~43) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (136:136:136)) + (PORT datab (366:366:366) (434:434:434)) + (PORT datac (88:88:88) (109:109:109)) + (PORT datad (94:94:94) (113:113:113)) (IOPATH dataa combout (158:158:158) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -16321,13 +14138,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_hi) + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_68\~2) (DELAY (ABSOLUTE - (PORT datab (502:502:502) (587:587:587)) - (PORT datac (301:301:301) (353:353:353)) - (PORT datad (95:95:95) (115:115:115)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (PORT datac (1069:1069:1069) (1244:1244:1244)) + (PORT datad (997:997:997) (1152:1152:1152)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -16335,93 +14150,64 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_81) + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_64\~0) (DELAY (ABSOLUTE - (PORT dataa (464:464:464) (547:547:547)) - (PORT datac (614:614:614) (717:717:717)) - (PORT datad (449:449:449) (516:516:516)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (907:907:907) (912:912:912)) - (PORT asdata (810:810:810) (913:913:913)) - (PORT ena (673:673:673) (745:745:745)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_80) - (DELAY - (ABSOLUTE - (PORT dataa (462:462:462) (545:545:545)) - (PORT datac (610:610:610) (713:713:713)) - (PORT datad (450:450:450) (517:517:517)) + (PORT dataa (654:654:654) (753:753:753)) + (PORT datab (314:314:314) (368:368:368)) + (PORT datac (528:528:528) (610:610:610)) + (PORT datad (345:345:345) (392:392:392)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~45) - (DELAY - (ABSOLUTE - (PORT dataa (591:591:591) (685:685:685)) - (PORT datab (736:736:736) (875:875:875)) - (PORT datad (454:454:454) (523:523:523)) - (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_41\~0) + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_76\~0) (DELAY (ABSOLUTE - (PORT dataa (347:347:347) (415:415:415)) - (PORT datab (700:700:700) (833:833:833)) - (PORT datac (634:634:634) (734:734:734)) - (PORT datad (197:197:197) (238:238:238)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) + (PORT dataa (522:522:522) (604:604:604)) + (PORT datab (410:410:410) (488:488:488)) + (PORT datac (441:441:441) (521:521:521)) + (PORT datad (349:349:349) (407:407:407)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[3\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_68) (DELAY (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (539:539:539) (600:600:600)) - (PORT ena (627:627:627) (675:675:675)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (PORT datab (581:581:581) (653:653:653)) + (PORT datac (1071:1071:1071) (1246:1246:1246)) + (PORT datad (998:998:998) (1154:1154:1154)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_40\~0) + (DELAY + (ABSOLUTE + (PORT dataa (377:377:377) (446:446:446)) + (PORT datab (812:812:812) (921:921:921)) + (PORT datac (464:464:464) (537:537:537)) + (PORT datad (341:341:341) (383:383:383)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) ) ) (CELL @@ -16429,10 +14215,99 @@ (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_36\~0) (DELAY (ABSOLUTE - (PORT dataa (212:212:212) (265:265:265)) - (PORT datab (697:697:697) (830:830:830)) - (PORT datac (633:633:633) (732:732:732)) - (PORT datad (353:353:353) (414:414:414)) + (PORT dataa (548:548:548) (656:656:656)) + (PORT datab (418:418:418) (497:497:497)) + (PORT datac (506:506:506) (581:581:581)) + (PORT datad (350:350:350) (408:408:408)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (365:365:365) (435:435:435)) + (PORT datab (179:179:179) (218:218:218)) + (PORT datac (324:324:324) (374:374:374)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_80) + (DELAY + (ABSOLUTE + (PORT datab (524:524:524) (599:599:599)) + (PORT datac (608:608:608) (697:697:697)) + (PORT datad (525:525:525) (603:603:603)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal21\~2) + (DELAY + (ABSOLUTE + (PORT dataa (125:125:125) (164:164:164)) + (PORT datab (476:476:476) (554:554:554)) + (PORT datad (783:783:783) (933:933:933)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|bank_af\~0) + (DELAY + (ABSOLUTE + (PORT dataa (646:646:646) (750:750:750)) + (PORT datab (792:792:792) (906:906:906)) + (PORT datad (166:166:166) (191:191:191)) + (IOPATH dataa combout (159:159:159) (173:173:173)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_control_\|bank_af) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (903:903:903) (890:890:890)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_af\~0) + (DELAY + (ABSOLUTE + (PORT dataa (465:465:465) (545:545:545)) + (PORT datab (526:526:526) (610:610:610)) + (PORT datac (750:750:750) (910:910:910)) + (PORT datad (390:390:390) (460:460:460)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (166:166:166) (158:158:158)) (IOPATH datac combout (119:119:119) (125:125:125)) @@ -16442,78 +14317,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_37\~0) + (INSTANCE z80_\|reg_control_\|reg_sel_af2\~0) (DELAY (ABSOLUTE - (PORT dataa (349:349:349) (417:417:417)) - (PORT datab (695:695:695) (827:827:827)) - (PORT datac (630:630:630) (729:729:729)) - (PORT datad (200:200:200) (241:241:241)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (538:538:538) (599:599:599)) - (PORT ena (670:670:670) (742:742:742)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_40\~0) - (DELAY - (ABSOLUTE - (PORT dataa (211:211:211) (264:264:264)) - (PORT datab (700:700:700) (832:832:832)) - (PORT datac (635:635:635) (734:734:734)) - (PORT datad (354:354:354) (415:415:415)) + (PORT dataa (468:468:468) (550:550:550)) + (PORT datab (528:528:528) (612:612:612)) + (PORT datac (751:751:751) (912:912:912)) + (PORT datad (396:396:396) (466:466:466)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~42) - (DELAY - (ABSOLUTE - (PORT dataa (217:217:217) (272:272:272)) - (PORT datab (898:898:898) (1047:1047:1047)) - (PORT datad (644:644:644) (749:749:749)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~46) - (DELAY - (ABSOLUTE - (PORT dataa (322:322:322) (386:386:386)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (88:88:88) (109:109:109)) - (PORT datad (415:415:415) (471:471:471)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datab combout (167:167:167) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -16521,15 +14333,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~47) + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_28) (DELAY (ABSOLUTE - (PORT dataa (328:328:328) (393:393:393)) - (PORT datab (172:172:172) (210:210:210)) - (PORT datac (89:89:89) (110:110:110)) - (PORT datad (334:334:334) (392:392:392)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) + (PORT dataa (1090:1090:1090) (1266:1266:1266)) + (PORT datac (333:333:333) (386:386:386)) + (PORT datad (994:994:994) (1148:1148:1148)) + (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -16540,10 +14350,10 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~17) (DELAY (ABSOLUTE - (PORT dataa (504:504:504) (599:599:599)) - (PORT datab (114:114:114) (142:142:142)) - (PORT datac (346:346:346) (396:396:396)) - (PORT datad (416:416:416) (473:473:473)) + (PORT dataa (365:365:365) (431:431:431)) + (PORT datab (304:304:304) (358:358:358)) + (PORT datac (328:328:328) (375:375:375)) + (PORT datad (210:210:210) (258:258:258)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -16553,29 +14363,71 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~18) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~19) (DELAY (ABSOLUTE - (PORT dataa (594:594:594) (699:699:699)) - (PORT datab (459:459:459) (531:531:531)) - (PORT datac (116:116:116) (144:144:144)) + (PORT dataa (192:192:192) (229:229:229)) + (PORT datab (357:357:357) (418:418:418)) + (PORT datac (159:159:159) (187:187:187)) + (PORT datad (90:90:90) (107:107:107)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~19) + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_52) (DELAY (ABSOLUTE - (PORT dataa (350:350:350) (410:410:410)) - (PORT datab (458:458:458) (536:536:536)) - (PORT datac (92:92:92) (114:114:114)) - (PORT datad (470:470:470) (548:548:548)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT dataa (627:627:627) (714:714:714)) + (PORT datac (790:790:790) (899:899:899)) + (PORT datad (446:446:446) (505:505:505)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_44) + (DELAY + (ABSOLUTE + (PORT dataa (1030:1030:1030) (1196:1196:1196)) + (PORT datac (1080:1080:1080) (1257:1257:1257)) + (PORT datad (605:605:605) (693:693:693)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_48) + (DELAY + (ABSOLUTE + (PORT dataa (1031:1031:1031) (1198:1198:1198)) + (PORT datac (1081:1081:1081) (1258:1258:1258)) + (PORT datad (595:595:595) (673:673:673)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_56) + (DELAY + (ABSOLUTE + (PORT dataa (1026:1026:1026) (1192:1192:1192)) + (PORT datac (1076:1076:1076) (1251:1251:1251)) + (PORT datad (590:590:590) (675:675:675)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -16586,10 +14438,10 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~16) (DELAY (ABSOLUTE - (PORT dataa (115:115:115) (145:145:145)) - (PORT datab (114:114:114) (142:142:142)) - (PORT datac (103:103:103) (125:125:125)) - (PORT datad (103:103:103) (120:120:120)) + (PORT dataa (483:483:483) (557:557:557)) + (PORT datab (117:117:117) (146:146:146)) + (PORT datac (104:104:104) (126:126:126)) + (PORT datad (104:104:104) (121:121:121)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -16602,10 +14454,10 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~20) (DELAY (ABSOLUTE - (PORT dataa (839:839:839) (955:955:955)) - (PORT datab (475:475:475) (575:575:575)) - (PORT datac (623:623:623) (711:711:711)) - (PORT datad (91:91:91) (109:109:109)) + (PORT dataa (639:639:639) (753:753:753)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (289:289:289) (336:336:336)) + (PORT datad (617:617:617) (702:702:702)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -16615,368 +14467,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_73) + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_69\~2) (DELAY (ABSOLUTE - (PORT dataa (729:729:729) (872:872:872)) - (PORT datac (613:613:613) (716:716:716)) - (PORT datad (449:449:449) (516:516:516)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (679:679:679) (747:747:747)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (659:659:659) (734:734:734)) - (PORT ena (515:515:515) (556:556:556)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (658:658:658) (734:734:734)) - (PORT ena (506:506:506) (537:537:537)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (256:256:256) (310:310:310)) - (PORT datab (267:267:267) (319:319:319)) - (PORT datad (117:117:117) (153:153:153)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (1077:1077:1077) (1197:1197:1197)) - (PORT ena (408:408:408) (429:429:429)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (510:510:510) (609:609:609)) - (PORT datab (669:669:669) (792:792:792)) - (PORT datad (479:479:479) (557:557:557)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (923:923:923)) - (PORT asdata (286:286:286) (308:308:308)) - (PORT ena (776:776:776) (851:851:851)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (907:907:907) (912:912:912)) - (PORT asdata (937:937:937) (1041:1041:1041)) - (PORT ena (673:673:673) (745:745:745)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (592:592:592) (685:685:685)) - (PORT datab (357:357:357) (432:432:432)) - (PORT datad (459:459:459) (529:529:529)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (911:911:911)) - (PORT asdata (1203:1203:1203) (1346:1346:1346)) - (PORT ena (405:405:405) (422:422:422)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (450:450:450) (528:528:528)) - (PORT datab (650:650:650) (752:752:752)) - (PORT datad (130:130:130) (158:158:158)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (1082:1082:1082) (1206:1206:1206)) - (PORT ena (627:627:627) (675:675:675)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (1084:1084:1084) (1208:1208:1208)) - (PORT ena (670:670:670) (742:742:742)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (204:204:204) (266:266:266)) - (PORT datab (890:890:890) (1038:1038:1038)) - (PORT datad (642:642:642) (746:746:746)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (907:907:907) (912:912:912)) - (PORT asdata (935:935:935) (1038:1038:1038)) - (PORT ena (582:582:582) (618:618:618)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (879:879:879) (1000:1000:1000)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (907:907:907) (912:912:912)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (405:405:405) (422:422:422)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (207:207:207) (248:248:248)) - (PORT datab (482:482:482) (562:562:562)) - (PORT datad (462:462:462) (542:542:542)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (133:133:133)) - (PORT datab (334:334:334) (392:392:392)) - (PORT datac (170:170:170) (203:203:203)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (1313:1313:1313) (1470:1470:1470)) - (PORT ena (753:753:753) (845:845:845)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (1313:1313:1313) (1469:1469:1469)) - (PORT ena (759:759:759) (842:842:842)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (508:508:508) (621:621:621)) - (PORT datab (514:514:514) (622:622:622)) - (PORT datad (116:116:116) (153:153:153)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (344:344:344) (405:405:405)) - (PORT datab (101:101:101) (129:129:129)) - (PORT datac (321:321:321) (375:375:375)) - (PORT datad (160:160:160) (183:183:183)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) + (PORT datac (1066:1066:1066) (1241:1241:1241)) + (PORT datad (994:994:994) (1149:1149:1149)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -16984,132 +14479,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~21) + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_65\~0) (DELAY (ABSOLUTE - (PORT dataa (504:504:504) (602:602:602)) - (PORT datab (284:284:284) (333:333:333)) - (PORT datac (591:591:591) (692:692:692)) - (PORT datad (731:731:731) (840:840:840)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_60) - (DELAY - (ABSOLUTE - (PORT dataa (465:465:465) (542:542:542)) - (PORT datac (609:609:609) (712:712:712)) - (PORT datad (459:459:459) (536:536:536)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_61) - (DELAY - (ABSOLUTE - (PORT dataa (464:464:464) (542:542:542)) - (PORT datac (612:612:612) (714:714:714)) - (PORT datad (460:460:460) (536:536:536)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (923:923:923)) - (PORT asdata (768:768:768) (868:868:868)) - (PORT ena (480:480:480) (509:509:509)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sw_4d_hi\~0) - (DELAY - (ABSOLUTE - (PORT dataa (640:640:640) (739:739:739)) - (PORT datab (446:446:446) (520:520:520)) - (PORT datac (613:613:613) (716:716:716)) - (PORT datad (460:460:460) (536:536:536)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (120:120:120) (153:153:153)) - (PORT datab (213:213:213) (257:257:257)) - (PORT datad (203:203:203) (241:241:241)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_72) - (DELAY - (ABSOLUTE - (PORT dataa (729:729:729) (871:871:871)) - (PORT datac (613:613:613) (715:715:715)) - (PORT datad (449:449:449) (516:516:516)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (130:130:130) (180:180:180)) - (PORT datac (428:428:428) (511:511:511)) - (PORT datad (343:343:343) (399:399:399)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (128:128:128) (164:164:164)) - (PORT datab (122:122:122) (153:153:153)) - (PORT datac (589:589:589) (685:685:685)) - (PORT datad (115:115:115) (137:137:137)) + (PORT dataa (347:347:347) (415:415:415)) + (PORT datab (523:523:523) (616:616:616)) + (PORT datac (506:506:506) (581:581:581)) + (PORT datad (398:398:398) (469:469:469)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -17117,670 +14493,14 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|d1_out) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (288:288:288)) - (PORT datab (150:150:150) (202:202:202)) - (PORT datac (723:723:723) (827:827:827)) - (PORT datad (95:95:95) (116:116:116)) - (IOPATH dataa combout (165:165:165) (173:173:173)) - (IOPATH datab combout (192:192:192) (177:177:177)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (923:923:923)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (434:434:434) (466:466:466)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (504:504:504) (554:554:554)) - (PORT ena (753:753:753) (845:845:845)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (504:504:504) (554:554:554)) - (PORT ena (759:759:759) (842:842:842)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (504:504:504) (616:616:616)) - (PORT datab (516:516:516) (624:624:624)) - (PORT datad (115:115:115) (152:152:152)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (753:753:753) (853:853:853)) - (PORT ena (515:515:515) (556:556:556)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (749:749:749) (850:850:850)) - (PORT ena (506:506:506) (537:537:537)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (255:255:255) (309:309:309)) - (PORT datab (269:269:269) (321:321:321)) - (PORT datad (119:119:119) (156:156:156)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (691:691:691) (767:767:767)) - (PORT ena (670:670:670) (742:742:742)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (691:691:691) (768:768:768)) - (PORT ena (627:627:627) (675:675:675)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (258:258:258)) - (PORT datab (897:897:897) (1046:1046:1046)) - (PORT datad (644:644:644) (749:749:749)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (911:911:911)) - (PORT asdata (682:682:682) (746:746:746)) - (PORT ena (405:405:405) (422:422:422)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (565:565:565) (645:645:645)) - (PORT datab (649:649:649) (751:751:751)) - (PORT datad (127:127:127) (156:156:156)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (463:463:463) (542:542:542)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (907:907:907) (912:912:912)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (622:622:622) (680:680:680)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (907:907:907) (912:912:912)) - (PORT asdata (688:688:688) (764:764:764)) - (PORT ena (405:405:405) (422:422:422)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (132:132:132) (184:184:184)) - (PORT datab (130:130:130) (163:163:163)) - (PORT datad (471:471:471) (549:549:549)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (908:908:908)) - (PORT asdata (356:356:356) (383:383:383)) - (PORT ena (747:747:747) (810:810:810)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (908:908:908)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (778:778:778) (855:855:855)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (563:563:563) (644:644:644)) - (PORT datab (720:720:720) (850:850:850)) - (PORT datad (117:117:117) (153:153:153)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (453:453:453) (524:524:524)) - (PORT datab (568:568:568) (676:676:676)) - (PORT datac (457:457:457) (544:544:544)) - (PORT datad (90:90:90) (106:106:106)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (512:512:512) (563:563:563)) - (PORT ena (408:408:408) (429:429:429)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[0\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (505:505:505) (604:604:604)) - (PORT datab (669:669:669) (791:791:791)) - (PORT datad (488:488:488) (568:568:568)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (249:249:249)) - (PORT datab (466:466:466) (557:557:557)) - (PORT datac (88:88:88) (109:109:109)) - (PORT datad (295:295:295) (341:341:341)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (452:452:452) (524:524:524)) - (PORT datab (476:476:476) (550:550:550)) - (PORT datac (455:455:455) (546:546:546)) - (PORT datad (89:89:89) (107:107:107)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (923:923:923)) - (PORT asdata (451:451:451) (491:491:491)) - (PORT ena (482:482:482) (509:509:509)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (126:126:126) (160:160:160)) - (PORT datab (505:505:505) (574:574:574)) - (PORT datad (112:112:112) (133:133:133)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (127:127:127) (163:163:163)) - (PORT datac (116:116:116) (156:156:156)) - (PORT datad (90:90:90) (106:106:106)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (611:611:611) (709:709:709)) - (PORT datab (442:442:442) (512:512:512)) - (PORT datac (104:104:104) (128:128:128)) - (PORT datad (89:89:89) (106:106:106)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[8\]) - (DELAY - (ABSOLUTE - (PORT dataa (377:377:377) (449:449:449)) - (PORT datac (424:424:424) (492:492:492)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[8\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (920:920:920) (904:904:904)) - (PORT ena (1159:1159:1159) (1318:1318:1318)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|carry_borrow_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (225:225:225) (293:293:293)) - (PORT datab (152:152:152) (204:204:204)) - (PORT datac (720:720:720) (824:824:824)) - (PORT datad (100:100:100) (121:121:121)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|d0_out) - (DELAY - (ABSOLUTE - (PORT datac (136:136:136) (185:185:185)) - (PORT datad (166:166:166) (195:195:195)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (133:133:133)) - (PORT datab (389:389:389) (459:459:459)) - (PORT datac (438:438:438) (508:508:508)) - (PORT datad (303:303:303) (347:347:347)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[9\]) - (DELAY - (ABSOLUTE - (PORT datab (185:185:185) (222:222:222)) - (PORT datac (481:481:481) (555:555:555)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|Q\[9\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (286:286:286) (329:329:329)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[9\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (913:913:913)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (920:920:920) (904:904:904)) - (PORT ena (1125:1125:1125) (1271:1271:1271)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|d1_out) - (DELAY - (ABSOLUTE - (PORT dataa (144:144:144) (201:201:201)) - (PORT datab (154:154:154) (211:211:211)) - (PORT datac (729:729:729) (840:840:840)) - (PORT datad (166:166:166) (195:195:195)) - (IOPATH dataa combout (186:186:186) (175:175:175)) - (IOPATH datab combout (166:166:166) (174:174:174)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (612:612:612) (684:684:684)) - (PORT ena (753:753:753) (845:845:845)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (612:612:612) (684:684:684)) - (PORT ena (759:759:759) (842:842:842)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (505:505:505) (617:617:617)) - (PORT datab (516:516:516) (623:623:623)) - (PORT datad (117:117:117) (153:153:153)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (911:911:911)) - (PORT asdata (1078:1078:1078) (1235:1235:1235)) - (PORT ena (405:405:405) (422:422:422)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (434:434:434) (502:502:502)) - (PORT datab (651:651:651) (753:753:753)) - (PORT datad (130:130:130) (159:159:159)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[2\]) (DELAY (ABSOLUTE - (PORT clk (907:907:907) (912:912:912)) - (PORT asdata (806:806:806) (926:926:926)) - (PORT ena (582:582:582) (618:618:618)) + (PORT clk (905:905:905) (910:910:910)) + (PORT asdata (819:819:819) (919:919:919)) + (PORT ena (649:649:649) (707:707:707)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -17791,10 +14511,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[2\]\~feeder) + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_69) (DELAY (ABSOLUTE - (PORT datad (456:456:456) (544:544:544)) + (PORT datab (580:580:580) (652:652:652)) + (PORT datac (1067:1067:1067) (1242:1242:1242)) + (PORT datad (995:995:995) (1150:1150:1150)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -17804,66 +14528,9 @@ (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[2\]) (DELAY (ABSOLUTE - (PORT clk (907:907:907) (912:912:912)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (405:405:405) (422:422:422)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (207:207:207) (248:248:248)) - (PORT datab (481:481:481) (561:561:561)) - (PORT datad (183:183:183) (228:228:228)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (573:573:573) (673:673:673)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (627:627:627) (675:675:675)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (1123:1123:1123) (1280:1280:1280)) - (PORT ena (670:670:670) (742:742:742)) + (PORT clk (905:905:905) (910:910:910)) + (PORT asdata (823:823:823) (923:923:923)) + (PORT ena (604:604:604) (647:647:647)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -17874,27 +14541,43 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~33) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~34) (DELAY (ABSOLUTE - (PORT dataa (297:297:297) (365:365:365)) - (PORT datab (895:895:895) (1044:1044:1044)) - (PORT datad (643:643:643) (748:748:748)) - (IOPATH dataa combout (166:166:166) (163:163:163)) + (PORT dataa (364:364:364) (434:434:434)) + (PORT datab (144:144:144) (181:181:181)) + (PORT datad (118:118:118) (156:156:156)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_77\~0) + (DELAY + (ABSOLUTE + (PORT dataa (347:347:347) (415:415:415)) + (PORT datab (420:420:420) (499:499:499)) + (PORT datac (448:448:448) (529:529:529)) + (PORT datad (514:514:514) (589:589:589)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[2\]) (DELAY (ABSOLUTE - (PORT clk (915:915:915) (923:923:923)) + (PORT clk (904:904:904) (909:909:909)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (776:776:776) (851:851:851)) + (PORT ena (800:800:800) (878:878:878)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -17903,14 +14586,28 @@ (HOLD ena (posedge clk) (84:84:84)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_81) + (DELAY + (ABSOLUTE + (PORT datab (524:524:524) (599:599:599)) + (PORT datac (609:609:609) (699:699:699)) + (PORT datad (526:526:526) (604:604:604)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[2\]) (DELAY (ABSOLUTE - (PORT clk (907:907:907) (912:912:912)) - (PORT asdata (805:805:805) (926:926:926)) - (PORT ena (673:673:673) (745:745:745)) + (PORT clk (904:904:904) (909:909:909)) + (PORT asdata (901:901:901) (1001:1001:1001)) + (PORT ena (655:655:655) (714:714:714)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -17924,9 +14621,54 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~36) (DELAY (ABSOLUTE - (PORT dataa (592:592:592) (685:685:685)) - (PORT datab (371:371:371) (448:448:448)) - (PORT datad (462:462:462) (533:533:533)) + (PORT dataa (395:395:395) (473:473:473)) + (PORT datab (129:129:129) (176:176:176)) + (PORT datad (377:377:377) (443:443:443)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_29) + (DELAY + (ABSOLUTE + (PORT dataa (1099:1099:1099) (1277:1277:1277)) + (PORT datac (336:336:336) (389:389:389)) + (PORT datad (1001:1001:1001) (1158:1158:1158)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (909:909:909)) + (PORT asdata (633:633:633) (700:700:700)) + (PORT ena (619:619:619) (671:671:671)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (641:641:641) (755:755:755)) + (PORT datab (491:491:491) (564:564:564)) + (PORT datad (212:212:212) (260:260:260)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) @@ -17934,15 +14676,94 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_37\~0) + (DELAY + (ABSOLUTE + (PORT dataa (553:553:553) (662:662:662)) + (PORT datab (412:412:412) (491:491:491)) + (PORT datac (506:506:506) (580:580:580)) + (PORT datad (335:335:335) (392:392:392)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) + (PORT asdata (744:744:744) (844:844:844)) + (PORT ena (648:648:648) (700:700:700)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_41\~0) + (DELAY + (ABSOLUTE + (PORT dataa (553:553:553) (661:661:661)) + (PORT datab (413:413:413) (492:492:492)) + (PORT datac (506:506:506) (580:580:580)) + (PORT datad (335:335:335) (392:392:392)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) + (PORT asdata (742:742:742) (842:842:842)) + (PORT ena (757:757:757) (811:811:811)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (384:384:384) (457:457:457)) + (PORT datab (341:341:341) (400:400:400)) + (PORT datad (118:118:118) (155:155:155)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~37) (DELAY (ABSOLUTE - (PORT dataa (333:333:333) (391:391:391)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (317:317:317) (374:374:374)) - (PORT datad (92:92:92) (110:110:110)) + (PORT dataa (325:325:325) (381:381:381)) + (PORT datab (339:339:339) (398:398:398)) + (PORT datac (337:337:337) (388:388:388)) + (PORT datad (563:563:563) (655:655:655)) (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -17950,35 +14771,73 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_45) + (DELAY + (ABSOLUTE + (PORT dataa (839:839:839) (989:989:989)) + (PORT datab (1227:1227:1227) (1416:1416:1416)) + (PORT datad (759:759:759) (866:866:866)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) + (PORT asdata (506:506:506) (560:560:560)) + (PORT ena (501:501:501) (541:541:541)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (302:302:302) (344:344:344)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_49) + (DELAY + (ABSOLUTE + (PORT dataa (1028:1028:1028) (1194:1194:1194)) + (PORT datac (1078:1078:1078) (1254:1254:1254)) + (PORT datad (594:594:594) (673:673:673)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[2\]) (DELAY (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (1225:1225:1225) (1404:1404:1404)) - (PORT ena (506:506:506) (537:537:537)) + (PORT clk (902:902:902) (907:907:907)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (621:621:621) (666:666:666)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (1227:1227:1227) (1407:1407:1407)) - (PORT ena (515:515:515) (556:556:556)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) + (HOLD d (posedge clk) (84:84:84)) (HOLD ena (posedge clk) (84:84:84)) ) ) @@ -17987,24 +14846,38 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~31) (DELAY (ABSOLUTE - (PORT dataa (257:257:257) (311:311:311)) - (PORT datab (132:132:132) (181:181:181)) - (PORT datad (245:245:245) (290:290:290)) + (PORT dataa (356:356:356) (433:433:433)) + (PORT datab (373:373:373) (436:436:436)) + (PORT datad (118:118:118) (155:155:155)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_33) + (DELAY + (ABSOLUTE + (PORT dataa (835:835:835) (983:983:983)) + (PORT datab (1233:1233:1233) (1422:1422:1422)) + (PORT datad (729:729:729) (820:820:820)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[2\]) (DELAY (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (1237:1237:1237) (1417:1417:1417)) - (PORT ena (408:408:408) (429:429:429)) + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (478:478:478) (519:519:519)) + (PORT ena (406:406:406) (423:423:423)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -18015,12 +14888,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[2\]\~17) + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[2\]\~12) (DELAY (ABSOLUTE - (PORT dataa (506:506:506) (605:605:605)) - (PORT datab (669:669:669) (791:791:791)) - (PORT datad (486:486:486) (565:565:565)) + (PORT dataa (841:841:841) (992:992:992)) + (PORT datab (1224:1224:1224) (1413:1413:1413)) + (PORT datad (733:733:733) (823:823:823)) (IOPATH dataa combout (158:158:158) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (190:190:190) (195:195:195)) @@ -18028,15 +14901,90 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_57) + (DELAY + (ABSOLUTE + (PORT dataa (1029:1029:1029) (1196:1196:1196)) + (PORT datac (1079:1079:1079) (1256:1256:1256)) + (PORT datad (590:590:590) (675:675:675)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) + (PORT asdata (644:644:644) (713:713:713)) + (PORT ena (649:649:649) (705:705:705)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_53) + (DELAY + (ABSOLUTE + (PORT dataa (627:627:627) (714:714:714)) + (PORT datac (790:790:790) (899:899:899)) + (PORT datad (447:447:447) (505:505:505)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) + (PORT asdata (643:643:643) (712:712:712)) + (PORT ena (422:422:422) (449:449:449)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (388:388:388) (465:465:465)) + (PORT datab (130:130:130) (179:179:179)) + (PORT datad (120:120:120) (145:145:145)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~38) (DELAY (ABSOLUTE - (PORT dataa (440:440:440) (531:531:531)) - (PORT datab (297:297:297) (349:349:349)) - (PORT datac (292:292:292) (336:336:336)) - (PORT datad (462:462:462) (537:537:537)) + (PORT dataa (172:172:172) (211:211:211)) + (PORT datab (330:330:330) (386:386:386)) + (PORT datac (172:172:172) (204:204:204)) + (PORT datad (161:161:161) (190:190:190)) (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -18046,190 +14994,27 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~39) + (INSTANCE z80_\|execute_\|ctl_inc_dec\~11) (DELAY (ABSOLUTE - (PORT dataa (488:488:488) (579:579:579)) - (PORT datab (202:202:202) (239:239:239)) - (PORT datac (489:489:489) (580:580:580)) - (PORT datad (730:730:730) (840:840:840)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (923:923:923)) - (PORT asdata (284:284:284) (306:306:306)) - (PORT ena (482:482:482) (509:509:509)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1080:1080:1080) (1264:1264:1264)) - (PORT datab (125:125:125) (156:156:156)) - (PORT datad (113:113:113) (135:135:135)) - (IOPATH dataa combout (166:166:166) (163:163:163)) + (PORT dataa (725:725:725) (823:823:823)) + (PORT datab (1016:1016:1016) (1180:1180:1180)) + (PORT datac (1149:1149:1149) (1328:1328:1328)) + (PORT datad (998:998:998) (1169:1169:1169)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (923:923:923)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (434:434:434) (466:466:466)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (126:126:126) (160:160:160)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datad (185:185:185) (232:232:232)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~9) + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|d0_out) (DELAY (ABSOLUTE - (PORT dataa (615:615:615) (713:713:713)) - (PORT datab (283:283:283) (325:325:325)) - (PORT datac (108:108:108) (132:132:132)) - (PORT datad (89:89:89) (107:107:107)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[10\]) - (DELAY - (ABSOLUTE - (PORT datac (105:105:105) (128:128:128)) - (PORT datad (479:479:479) (549:549:549)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|Q\[10\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (276:276:276) (318:318:318)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[10\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (913:913:913)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (920:920:920) (904:904:904)) - (PORT ena (1125:1125:1125) (1271:1271:1271)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|carry_borrow_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (148:148:148) (206:206:206)) - (PORT datab (149:149:149) (204:204:204)) - (PORT datac (732:732:732) (843:843:843)) - (PORT datad (167:167:167) (196:196:196)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[11\]) - (DELAY - (ABSOLUTE - (PORT datab (328:328:328) (387:387:387)) - (PORT datad (499:499:499) (574:574:574)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[11\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (913:913:913)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (920:920:920) (904:904:904)) - (PORT ena (1125:1125:1125) (1271:1271:1271)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[11\]) - (DELAY - (ABSOLUTE - (PORT dataa (115:115:115) (145:145:145)) - (PORT datac (300:300:300) (361:361:361)) + (PORT dataa (541:541:541) (642:642:642)) + (PORT datac (100:100:100) (127:127:127)) (IOPATH dataa combout (195:195:195) (203:203:203)) (IOPATH datac combout (120:120:120) (125:125:125)) ) @@ -18237,12 +15022,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[3\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[1\]) (DELAY (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) + (PORT clk (904:904:904) (909:909:909)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (679:679:679) (747:747:747)) + (PORT ena (665:665:665) (730:730:730)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -18251,62 +15036,17 @@ (HOLD ena (posedge clk) (84:84:84)) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (923:923:923)) - (PORT asdata (389:389:389) (432:432:432)) - (PORT ena (480:480:480) (509:509:509)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~10) + (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~5) (DELAY (ABSOLUTE - (PORT dataa (115:115:115) (145:145:145)) - (PORT datab (210:210:210) (253:253:253)) - (PORT datad (206:206:206) (244:244:244)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (134:134:134) (186:186:186)) - (PORT datac (465:465:465) (547:547:547)) - (PORT datad (340:340:340) (396:396:396)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (293:293:293) (339:339:339)) - (PORT datab (461:461:461) (536:536:536)) - (PORT datac (372:372:372) (442:442:442)) - (PORT datad (93:93:93) (111:111:111)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (PORT dataa (502:502:502) (596:596:596)) + (PORT datab (849:849:849) (1005:1005:1005)) + (PORT datac (859:859:859) (1000:1000:1000)) + (PORT datad (212:212:212) (257:257:257)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -18314,15 +15054,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~48) + (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~3) (DELAY (ABSOLUTE - (PORT dataa (325:325:325) (389:389:389)) - (PORT datab (469:469:469) (565:565:565)) - (PORT datac (209:209:209) (254:254:254)) - (PORT datad (731:731:731) (840:840:840)) + (PORT dataa (554:554:554) (670:670:670)) + (PORT datab (659:659:659) (778:778:778)) + (PORT datac (949:949:949) (1092:1092:1092)) + (PORT datad (378:378:378) (447:447:447)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -18330,13 +15070,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[3\]\~9) + (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~4) (DELAY (ABSOLUTE - (PORT dataa (484:484:484) (570:570:570)) - (PORT datab (118:118:118) (152:152:152)) - (PORT datac (628:628:628) (734:734:734)) - (PORT datad (329:329:329) (379:379:379)) + (PORT dataa (173:173:173) (210:210:210)) + (PORT datab (119:119:119) (148:148:148)) + (PORT datac (381:381:381) (457:457:457)) + (PORT datad (171:171:171) (202:202:202)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~4) + (DELAY + (ABSOLUTE + (PORT dataa (883:883:883) (1006:1006:1006)) + (PORT datab (931:931:931) (1076:1076:1076)) + (PORT datac (1372:1372:1372) (1570:1570:1570)) + (PORT datad (839:839:839) (966:966:966)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (120:120:120) (124:124:124)) @@ -18346,415 +15102,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_low) + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~5) (DELAY (ABSOLUTE - (PORT dataa (560:560:560) (652:652:652)) - (PORT datab (1201:1201:1201) (1376:1376:1376)) - (PORT datac (377:377:377) (439:439:439)) - (PORT datad (981:981:981) (1147:1147:1147)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[3\]) - (DELAY - (ABSOLUTE - (PORT datab (530:530:530) (628:628:628)) - (PORT datac (626:626:626) (726:726:726)) - (PORT datad (375:375:375) (446:446:446)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_high\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (916:916:916) (901:901:901)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (422:422:422) (450:450:450)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op1\[3\]\~3) - (DELAY - (ABSOLUTE - (PORT datab (347:347:347) (419:419:419)) - (PORT datac (345:345:345) (409:409:409)) - (PORT datad (344:344:344) (397:397:397)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_10\~0) - (DELAY - (ABSOLUTE - (PORT dataa (347:347:347) (419:419:419)) - (PORT datab (344:344:344) (416:416:416)) - (PORT datac (101:101:101) (122:122:122)) - (PORT datad (301:301:301) (348:348:348)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~6) - (DELAY - (ABSOLUTE - (PORT dataa (627:627:627) (719:719:719)) - (PORT datab (730:730:730) (864:864:864)) - (PORT datac (331:331:331) (378:378:378)) - (PORT datad (608:608:608) (689:689:689)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1163:1163:1163) (1387:1387:1387)) - (PORT datab (701:701:701) (819:819:819)) - (PORT datac (545:545:545) (643:643:643)) - (PORT datad (828:828:828) (966:966:966)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~0) - (DELAY - (ABSOLUTE - (PORT dataa (565:565:565) (657:657:657)) - (PORT datab (893:893:893) (1051:1051:1051)) - (PORT datac (617:617:617) (699:699:699)) - (PORT datad (358:358:358) (422:422:422)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1416:1416:1416) (1651:1651:1651)) - (PORT datab (887:887:887) (1038:1038:1038)) - (PORT datac (470:470:470) (547:547:547)) - (PORT datad (101:101:101) (124:124:124)) + (PORT dataa (673:673:673) (782:782:782)) + (PORT datab (856:856:856) (988:988:988)) + (PORT datac (448:448:448) (512:512:512)) + (PORT datad (496:496:496) (574:574:574)) (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~7) - (DELAY - (ABSOLUTE - (PORT dataa (195:195:195) (235:235:235)) - (PORT datab (457:457:457) (533:533:533)) - (PORT datac (446:446:446) (511:511:511)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~8) - (DELAY - (ABSOLUTE - (PORT dataa (331:331:331) (385:385:385)) - (PORT datab (672:672:672) (771:771:771)) - (PORT datac (289:289:289) (323:323:323)) - (PORT datad (323:323:323) (372:372:372)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[1\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (314:314:314) (368:368:368)) - (PORT datab (621:621:621) (741:741:741)) - (PORT datac (290:290:290) (338:338:338)) - (PORT datad (504:504:504) (590:590:590)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[1\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (143:143:143) (190:190:190)) - (PORT datac (88:88:88) (109:109:109)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|ena) - (DELAY - (ABSOLUTE - (PORT dataa (145:145:145) (193:193:193)) - (PORT datac (605:605:605) (725:725:725)) - (PORT datad (499:499:499) (585:585:585)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_high\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (900:900:900)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (420:420:420) (448:448:448)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[1\]) - (DELAY - (ABSOLUTE - (PORT datab (533:533:533) (632:632:632)) - (PORT datac (191:191:191) (233:233:233)) - (PORT datad (371:371:371) (441:441:441)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_high\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (916:916:916) (901:901:901)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (422:422:422) (450:450:450)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[1\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (350:350:350) (422:422:422)) - (PORT datab (627:627:627) (749:749:749)) - (PORT datac (315:315:315) (362:362:362)) - (PORT datad (201:201:201) (247:247:247)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[1\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (146:146:146) (194:194:194)) - (PORT datab (102:102:102) (131:131:131)) - (PORT datac (297:297:297) (342:342:342)) - (PORT datad (498:498:498) (583:583:583)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_low\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (900:900:900)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (420:420:420) (448:448:448)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~6) - (DELAY - (ABSOLUTE - (PORT dataa (798:798:798) (920:920:920)) - (PORT datab (843:843:843) (982:982:982)) - (PORT datac (1035:1035:1035) (1198:1198:1198)) - (PORT datad (212:212:212) (252:252:252)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~20) - (DELAY - (ABSOLUTE - (PORT dataa (800:800:800) (925:925:925)) - (PORT datab (897:897:897) (1061:1061:1061)) - (PORT datac (580:580:580) (670:670:670)) - (PORT datad (732:732:732) (861:861:861)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~12) - (DELAY - (ABSOLUTE - (PORT dataa (477:477:477) (551:551:551)) - (PORT datab (527:527:527) (606:606:606)) - (PORT datac (462:462:462) (539:539:539)) - (PORT datad (351:351:351) (409:409:409)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~18) - (DELAY - (ABSOLUTE - (PORT dataa (253:253:253) (301:301:301)) - (PORT datab (660:660:660) (765:765:765)) - (PORT datac (501:501:501) (611:611:611)) - (PORT datad (786:786:786) (923:923:923)) - (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal61\~2) - (DELAY - (ABSOLUTE - (PORT dataa (997:997:997) (1156:1156:1156)) - (PORT datab (779:779:779) (892:892:892)) - (PORT datac (909:909:909) (1065:1065:1065)) - (PORT datad (859:859:859) (1007:1007:1007)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~16) (DELAY (ABSOLUTE - (PORT datab (1021:1021:1021) (1197:1197:1197)) - (PORT datac (945:945:945) (1094:1094:1094)) - (PORT datad (520:520:520) (608:608:608)) - (IOPATH datab combout (166:166:166) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1015:1015:1015) (1160:1160:1160)) - (PORT datab (102:102:102) (131:131:131)) - (PORT datac (471:471:471) (535:535:535)) - (PORT datad (427:427:427) (493:493:493)) + (PORT dataa (345:345:345) (411:411:411)) + (PORT datab (517:517:517) (599:599:599)) + (PORT datac (1136:1136:1136) (1311:1311:1311)) + (PORT datad (712:712:712) (847:847:847)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -18764,610 +15134,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~21) + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~6) (DELAY (ABSOLUTE - (PORT dataa (752:752:752) (888:888:888)) - (PORT datab (980:980:980) (1147:1147:1147)) - (PORT datac (812:812:812) (935:935:935)) - (PORT datad (102:102:102) (118:118:118)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~15) - (DELAY - (ABSOLUTE - (PORT dataa (849:849:849) (987:987:987)) - (PORT datab (517:517:517) (606:606:606)) - (PORT datac (100:100:100) (121:121:121)) - (PORT datad (108:108:108) (127:127:127)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~12) - (DELAY - (ABSOLUTE - (PORT dataa (114:114:114) (145:145:145)) - (PORT datab (109:109:109) (139:139:139)) - (PORT datac (93:93:93) (116:116:116)) - (PORT datad (97:97:97) (117:117:117)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~22) - (DELAY - (ABSOLUTE - (PORT dataa (971:971:971) (1110:1110:1110)) - (PORT datab (448:448:448) (525:525:525)) - (PORT datac (731:731:731) (858:858:858)) - (PORT datad (1411:1411:1411) (1636:1636:1636)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~20) - (DELAY - (ABSOLUTE - (PORT dataa (314:314:314) (372:372:372)) - (PORT datab (132:132:132) (161:161:161)) - (PORT datac (120:120:120) (143:143:143)) - (PORT datad (490:490:490) (589:589:589)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (559:559:559) (641:641:641)) - (PORT datab (892:892:892) (1024:1024:1024)) - (PORT datac (662:662:662) (770:770:770)) - (PORT datad (960:960:960) (1087:1087:1087)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal71\~2) - (DELAY - (ABSOLUTE - (PORT dataa (466:466:466) (555:555:555)) - (PORT datab (511:511:511) (611:611:611)) - (PORT datac (117:117:117) (139:139:139)) - (PORT datad (487:487:487) (585:585:585)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~8) - (DELAY - (ABSOLUTE - (PORT dataa (110:110:110) (144:144:144)) - (PORT datab (115:115:115) (143:143:143)) - (PORT datac (106:106:106) (130:130:130)) - (PORT datad (96:96:96) (116:116:116)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~31) - (DELAY - (ABSOLUTE - (PORT dataa (663:663:663) (770:770:770)) - (PORT datab (121:121:121) (151:151:151)) - (PORT datac (1168:1168:1168) (1352:1352:1352)) - (PORT datad (796:796:796) (914:914:914)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~4) - (DELAY - (ABSOLUTE - (PORT dataa (366:366:366) (431:431:431)) - (PORT datab (826:826:826) (963:963:963)) - (PORT datac (824:824:824) (944:944:944)) - (PORT datad (340:340:340) (393:393:393)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla25M1T1_3) - (DELAY - (ABSOLUTE - (PORT dataa (447:447:447) (516:516:516)) - (PORT datab (828:828:828) (965:965:965)) - (PORT datac (869:869:869) (992:992:992)) - (PORT datad (821:821:821) (957:957:957)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~5) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (133:133:133)) - (PORT datab (111:111:111) (142:142:142)) - (PORT datac (449:449:449) (518:518:518)) - (PORT datad (103:103:103) (120:120:120)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~6) - (DELAY - (ABSOLUTE - (PORT dataa (117:117:117) (148:148:148)) - (PORT datab (116:116:116) (145:145:145)) - (PORT datac (586:586:586) (666:666:666)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal72\~2) - (DELAY - (ABSOLUTE - (PORT dataa (768:768:768) (908:908:908)) - (PORT datab (1306:1306:1306) (1524:1524:1524)) - (PORT datac (614:614:614) (714:714:714)) - (PORT datad (453:453:453) (513:513:513)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal73\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1116:1116:1116) (1306:1306:1306)) - (PORT datab (619:619:619) (727:727:727)) - (PORT datac (752:752:752) (871:871:871)) - (PORT datad (463:463:463) (523:523:523)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~0) - (DELAY - (ABSOLUTE - (PORT dataa (552:552:552) (647:647:647)) - (PORT datab (549:549:549) (651:651:651)) - (PORT datac (1000:1000:1000) (1140:1140:1140)) - (PORT datad (819:819:819) (951:951:951)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~1) - (DELAY - (ABSOLUTE - (PORT dataa (573:573:573) (657:657:657)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (329:329:329) (388:388:388)) - (PORT datad (318:318:318) (372:372:372)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (838:838:838) (980:980:980)) - (PORT datab (1112:1112:1112) (1276:1276:1276)) - (PORT datac (715:715:715) (835:835:835)) - (PORT datad (526:526:526) (615:615:615)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~3) - (DELAY - (ABSOLUTE - (PORT datab (467:467:467) (539:539:539)) - (PORT datac (445:445:445) (513:513:513)) - (PORT datad (444:444:444) (508:508:508)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1417:1417:1417) (1652:1652:1652)) - (PORT datac (871:871:871) (1016:1016:1016)) - (PORT datad (878:878:878) (1033:1033:1033)) - (IOPATH dataa combout (165:165:165) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (135:135:135) (172:172:172)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datac (644:644:644) (743:743:743)) - (PORT datad (102:102:102) (125:125:125)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (454:454:454) (539:539:539)) - (PORT datab (337:337:337) (399:399:399)) + (PORT dataa (329:329:329) (401:401:401)) + (PORT datab (105:105:105) (134:134:134)) (PORT datac (89:89:89) (110:110:110)) - (PORT datad (470:470:470) (559:559:559)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~15) - (DELAY - (ABSOLUTE - (PORT dataa (509:509:509) (588:588:588)) - (PORT datac (457:457:457) (527:527:527)) - (PORT datad (352:352:352) (408:408:408)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~16) - (DELAY - (ABSOLUTE - (PORT dataa (513:513:513) (593:593:593)) - (PORT datab (187:187:187) (226:226:226)) - (PORT datac (320:320:320) (372:372:372)) - (PORT datad (175:175:175) (203:203:203)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~6) - (DELAY - (ABSOLUTE - (PORT datac (486:486:486) (564:564:564)) - (PORT datad (448:448:448) (512:512:512)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~7) - (DELAY - (ABSOLUTE - (PORT dataa (325:325:325) (384:384:384)) - (PORT datab (609:609:609) (696:696:696)) - (PORT datac (403:403:403) (461:461:461)) - (PORT datad (333:333:333) (388:388:388)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (486:486:486) (565:565:565)) - (PORT datab (108:108:108) (139:139:139)) - (PORT datad (103:103:103) (120:120:120)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel_pla12M1T1_12\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1116:1116:1116) (1286:1286:1286)) - (PORT datab (121:121:121) (151:151:151)) - (PORT datac (978:978:978) (1128:1128:1128)) - (PORT datad (846:846:846) (969:969:969)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~1) - (DELAY - (ABSOLUTE - (PORT dataa (642:642:642) (738:738:738)) - (PORT datab (894:894:894) (1056:1056:1056)) - (PORT datac (1399:1399:1399) (1627:1627:1627)) - (PORT datad (100:100:100) (122:122:122)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~7) - (DELAY - (ABSOLUTE - (PORT dataa (560:560:560) (652:652:652)) - (PORT datab (739:739:739) (866:866:866)) - (PORT datac (485:485:485) (560:560:560)) - (PORT datad (94:94:94) (113:113:113)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~8) - (DELAY - (ABSOLUTE - (PORT dataa (341:341:341) (397:397:397)) - (PORT datab (1270:1270:1270) (1476:1476:1476)) - (PORT datac (1157:1157:1157) (1345:1345:1345)) - (PORT datad (635:635:635) (733:733:733)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~8) - (DELAY - (ABSOLUTE - (PORT dataa (325:325:325) (378:378:378)) - (PORT datab (324:324:324) (384:384:384)) - (PORT datac (292:292:292) (335:335:335)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~16) - (DELAY - (ABSOLUTE - (PORT dataa (563:563:563) (664:664:664)) - (PORT datab (1124:1124:1124) (1307:1307:1307)) - (PORT datac (436:436:436) (501:501:501)) - (PORT datad (1392:1392:1392) (1610:1610:1610)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~12) - (DELAY - (ABSOLUTE - (PORT dataa (853:853:853) (1001:1001:1001)) - (PORT datab (524:524:524) (626:626:626)) - (PORT datac (338:338:338) (398:398:398)) - (PORT datad (302:302:302) (342:342:342)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~13) - (DELAY - (ABSOLUTE - (PORT dataa (494:494:494) (583:583:583)) - (PORT datab (115:115:115) (142:142:142)) - (PORT datac (359:359:359) (422:422:422)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~14) - (DELAY - (ABSOLUTE - (PORT dataa (347:347:347) (409:409:409)) - (PORT datab (644:644:644) (748:748:748)) - (PORT datac (354:354:354) (418:418:418)) - (PORT datad (157:157:157) (184:184:184)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~15) - (DELAY - (ABSOLUTE - (PORT dataa (356:356:356) (416:416:416)) - (PORT datab (464:464:464) (557:557:557)) - (PORT datac (613:613:613) (698:698:698)) - (PORT datad (329:329:329) (376:376:376)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_nop3pla68M1T3_2) - (DELAY - (ABSOLUTE - (PORT dataa (335:335:335) (390:390:390)) - (PORT datab (347:347:347) (398:398:398)) - (PORT datac (523:523:523) (629:629:629)) - (PORT datad (452:452:452) (514:514:514)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~0) - (DELAY - (ABSOLUTE - (PORT dataa (839:839:839) (981:981:981)) - (PORT datab (577:577:577) (656:656:656)) - (PORT datac (716:716:716) (836:836:836)) - (PORT datad (524:524:524) (612:612:612)) - (IOPATH dataa combout (170:170:170) (163:163:163)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH dataa combout (170:170:170) (165:165:165)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -19376,15 +15150,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~19) + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~7) (DELAY (ABSOLUTE - (PORT dataa (806:806:806) (917:917:917)) - (PORT datab (635:635:635) (733:733:733)) - (PORT datac (669:669:669) (792:792:792)) - (PORT datad (632:632:632) (721:721:721)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) + (PORT dataa (345:345:345) (411:411:411)) + (PORT datab (857:857:857) (989:989:989)) + (PORT datac (117:117:117) (145:145:145)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -19392,14 +15166,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~1) + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~10) (DELAY (ABSOLUTE - (PORT dataa (328:328:328) (384:384:384)) - (PORT datab (578:578:578) (678:678:678)) - (PORT datac (408:408:408) (468:468:468)) - (PORT datad (331:331:331) (381:381:381)) - (IOPATH dataa combout (170:170:170) (163:163:163)) + (PORT dataa (1187:1187:1187) (1379:1379:1379)) + (PORT datab (705:705:705) (799:799:799)) + (PORT datac (823:823:823) (949:949:949)) + (PORT datad (462:462:462) (532:532:532)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -19408,92 +15182,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~2) + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~8) (DELAY (ABSOLUTE - (PORT dataa (120:120:120) (152:152:152)) - (PORT datab (581:581:581) (678:678:678)) - (PORT datac (463:463:463) (533:533:533)) - (PORT datad (324:324:324) (374:374:374)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~7) - (DELAY - (ABSOLUTE - (PORT dataa (315:315:315) (373:373:373)) - (PORT datab (117:117:117) (152:152:152)) - (PORT datac (447:447:447) (523:523:523)) - (PORT datad (800:800:800) (932:932:932)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~9) - (DELAY - (ABSOLUTE - (PORT dataa (439:439:439) (533:533:533)) - (PORT datab (452:452:452) (524:524:524)) - (PORT datac (445:445:445) (535:535:535)) - (PORT datad (431:431:431) (511:511:511)) + (PORT dataa (118:118:118) (156:156:156)) + (PORT datab (480:480:480) (557:557:557)) + (PORT datac (89:89:89) (109:109:109)) + (PORT datad (1078:1078:1078) (1255:1255:1255)) (IOPATH dataa combout (158:158:158) (163:163:163)) (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~10) - (DELAY - (ABSOLUTE - (PORT dataa (105:105:105) (136:136:136)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (158:158:158) (173:173:173)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf) - (DELAY - (ABSOLUTE - (PORT clk (896:896:896) (901:901:901)) - (PORT d (37:37:37) (50:50:50)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~7) - (DELAY - (ABSOLUTE - (PORT dataa (688:688:688) (789:789:789)) - (PORT datab (382:382:382) (457:457:457)) - (PORT datac (505:505:505) (595:595:595)) - (PORT datad (585:585:585) (669:669:669)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -19504,10 +15201,10 @@ (INSTANCE z80_\|execute_\|ctl_pf_sel_nop3pla68M3T1_20) (DELAY (ABSOLUTE - (PORT dataa (334:334:334) (389:389:389)) - (PORT datab (347:347:347) (397:397:397)) - (PORT datac (522:522:522) (629:629:629)) - (PORT datad (200:200:200) (232:232:232)) + (PORT dataa (527:527:527) (624:624:624)) + (PORT datab (541:541:541) (634:634:634)) + (PORT datac (1002:1002:1002) (1182:1182:1182)) + (PORT datad (941:941:941) (1064:1064:1064)) (IOPATH dataa combout (158:158:158) (163:163:163)) (IOPATH datab combout (160:160:160) (167:167:167)) (IOPATH datac combout (119:119:119) (125:125:125)) @@ -19517,13 +15214,25 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~10) + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~42) (DELAY (ABSOLUTE - (PORT dataa (546:546:546) (639:639:639)) - (PORT datab (1012:1012:1012) (1158:1158:1158)) - (PORT datac (715:715:715) (835:835:835)) - (PORT datad (582:582:582) (657:657:657)) + (PORT datac (316:316:316) (366:366:366)) + (PORT datad (106:106:106) (132:132:132)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~9) + (DELAY + (ABSOLUTE + (PORT dataa (316:316:316) (375:375:375)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (499:499:499) (571:571:571)) + (PORT datad (112:112:112) (134:134:134)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -19533,13 +15242,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~8) + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~5) (DELAY (ABSOLUTE - (PORT dataa (1121:1121:1121) (1298:1298:1298)) - (PORT datab (1374:1374:1374) (1594:1594:1594)) - (PORT datac (763:763:763) (873:873:873)) - (PORT datad (903:903:903) (1066:1066:1066)) + (PORT dataa (356:356:356) (421:421:421)) + (PORT datab (1066:1066:1066) (1225:1225:1225)) + (PORT datac (653:653:653) (763:763:763)) + (PORT datad (811:811:811) (923:923:923)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1218:1218:1218) (1408:1408:1408)) + (PORT datab (548:548:548) (657:657:657)) + (PORT datac (590:590:590) (676:676:676)) + (PORT datad (624:624:624) (719:719:719)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (124:124:124)) @@ -19549,29 +15274,105 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~9) + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~7) (DELAY (ABSOLUTE - (PORT dataa (836:836:836) (977:977:977)) - (PORT datab (196:196:196) (231:231:231)) - (PORT datac (714:714:714) (833:833:833)) - (PORT datad (489:489:489) (565:565:565)) + (PORT dataa (208:208:208) (249:249:249)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (107:107:107) (131:131:131)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~18) + (DELAY + (ABSOLUTE + (PORT dataa (844:844:844) (985:985:985)) + (PORT datac (721:721:721) (839:839:839)) + (PORT datad (1056:1056:1056) (1232:1232:1232)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~11) + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~1) (DELAY (ABSOLUTE - (PORT dataa (679:679:679) (778:778:778)) - (PORT datab (174:174:174) (213:213:213)) - (PORT datac (584:584:584) (667:667:667)) - (PORT datad (171:171:171) (202:202:202)) + (PORT dataa (648:648:648) (749:749:749)) + (PORT datab (524:524:524) (610:610:610)) + (PORT datac (1133:1133:1133) (1333:1333:1333)) + (PORT datad (345:345:345) (407:407:407)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (337:337:337) (393:393:393)) + (PORT datab (622:622:622) (738:738:738)) + (PORT datac (435:435:435) (492:492:492)) + (PORT datad (501:501:501) (600:600:600)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~3) + (DELAY + (ABSOLUTE + (PORT dataa (302:302:302) (354:354:354)) + (PORT datab (497:497:497) (602:602:602)) + (PORT datac (417:417:417) (471:471:471)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~2) + (DELAY + (ABSOLUTE + (PORT dataa (212:212:212) (255:255:255)) + (PORT datab (621:621:621) (737:737:737)) + (PORT datac (1208:1208:1208) (1390:1390:1390)) + (PORT datad (481:481:481) (569:569:569)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (615:615:615) (715:715:715)) + (PORT datab (746:746:746) (847:847:847)) + (PORT datac (288:288:288) (334:334:334)) + (PORT datad (451:451:451) (517:517:517)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -19581,14 +15382,183 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~14) + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~4) (DELAY (ABSOLUTE - (PORT dataa (184:184:184) (221:221:221)) - (PORT datab (343:343:343) (403:403:403)) - (PORT datac (87:87:87) (109:109:109)) - (PORT datad (335:335:335) (382:382:382)) + (PORT dataa (103:103:103) (133:133:133)) + (PORT datab (101:101:101) (130:130:130)) + (PORT datac (458:458:458) (519:519:519)) + (PORT datad (89:89:89) (107:107:107)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~8) + (DELAY + (ABSOLUTE + (PORT dataa (341:341:341) (400:400:400)) + (PORT datab (115:115:115) (143:143:143)) + (PORT datac (89:89:89) (111:111:111)) + (PORT datad (90:90:90) (107:107:107)) (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (845:845:845) (986:986:986)) + (PORT datab (1076:1076:1076) (1256:1256:1256)) + (PORT datac (723:723:723) (841:841:841)) + (PORT datad (832:832:832) (968:968:968)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~2) + (DELAY + (ABSOLUTE + (PORT datab (327:327:327) (378:378:378)) + (PORT datac (459:459:459) (527:527:527)) + (PORT datad (185:185:185) (214:214:214)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (506:506:506) (585:585:585)) + (PORT datab (739:739:739) (841:841:841)) + (PORT datac (922:922:922) (1073:1073:1073)) + (PORT datad (313:313:313) (359:359:359)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (406:406:406) (423:423:423)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_32) + (DELAY + (ABSOLUTE + (PORT dataa (836:836:836) (985:985:985)) + (PORT datab (1231:1231:1231) (1421:1421:1421)) + (PORT datad (730:730:730) (820:820:820)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (909:909:909)) + (PORT asdata (369:369:369) (411:411:411)) + (PORT ena (655:655:655) (714:714:714)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (909:909:909)) + (PORT asdata (370:370:370) (411:411:411)) + (PORT ena (800:800:800) (878:878:878)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~81) + (DELAY + (ABSOLUTE + (PORT dataa (387:387:387) (464:464:464)) + (PORT datab (129:129:129) (176:176:176)) + (PORT datad (382:382:382) (449:449:449)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[2\]\~8) + (DELAY + (ABSOLUTE + (PORT datab (464:464:464) (545:545:545)) + (PORT datac (436:436:436) (503:503:503)) + (PORT datad (638:638:638) (763:763:763)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[2\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (576:576:576) (666:666:666)) + (PORT datab (386:386:386) (451:451:451)) + (PORT datac (90:90:90) (111:111:111)) + (PORT datad (689:689:689) (776:776:776)) + (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -19597,15 +15567,59 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~18) + (INSTANCE z80_\|alu_\|db_high\[2\]\~11) (DELAY (ABSOLUTE - (PORT dataa (456:456:456) (533:533:533)) - (PORT datab (629:629:629) (726:726:726)) - (PORT datac (466:466:466) (540:540:540)) - (PORT datad (191:191:191) (239:239:239)) + (PORT datab (148:148:148) (187:187:187)) + (PORT datac (137:137:137) (178:178:178)) + (PORT datad (134:134:134) (166:166:166)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[2\]) + (DELAY + (ABSOLUTE + (PORT dataa (517:517:517) (595:595:595)) + (PORT datac (336:336:336) (396:396:396)) + (PORT datad (451:451:451) (512:512:512)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_high\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (931:931:931) (916:916:916)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (421:421:421) (449:449:449)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_lq) + (DELAY + (ABSOLUTE + (PORT dataa (996:996:996) (1166:1166:1166)) + (PORT datab (533:533:533) (624:624:624)) + (PORT datac (957:957:957) (1110:1110:1110)) + (PORT datad (588:588:588) (704:704:704)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -19613,31 +15627,2051 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_high) + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[2\]\~2) (DELAY (ABSOLUTE - (PORT dataa (1417:1417:1417) (1651:1651:1651)) - (PORT datab (116:116:116) (145:145:145)) - (PORT datac (775:775:775) (886:886:886)) - (PORT datad (1053:1053:1053) (1215:1215:1215)) + (PORT datac (315:315:315) (376:376:376)) + (PORT datad (358:358:358) (409:409:409)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1073:1073:1073) (1273:1273:1273)) + (PORT datab (1061:1061:1061) (1242:1242:1242)) + (PORT datac (574:574:574) (652:652:652)) + (PORT datad (176:176:176) (210:210:210)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~6) + (DELAY + (ABSOLUTE + (PORT dataa (335:335:335) (400:400:400)) + (PORT datab (1107:1107:1107) (1292:1292:1292)) + (PORT datac (962:962:962) (1102:1102:1102)) + (PORT datad (616:616:616) (692:692:692)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~7) + (DELAY + (ABSOLUTE + (PORT dataa (180:180:180) (219:219:219)) + (PORT datac (103:103:103) (131:131:131)) + (PORT datad (113:113:113) (135:135:135)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~8) + (DELAY + (ABSOLUTE + (PORT dataa (486:486:486) (562:562:562)) + (PORT datab (114:114:114) (142:142:142)) + (PORT datac (280:280:280) (319:319:319)) + (PORT datad (574:574:574) (675:675:675)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_zero) + (DELAY + (ABSOLUTE + (PORT dataa (452:452:452) (535:535:535)) + (PORT datab (351:351:351) (423:423:423)) + (PORT datac (469:469:469) (548:548:548)) + (PORT datad (303:303:303) (345:345:345)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[2\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (134:134:134)) + (PORT datab (486:486:486) (559:559:559)) + (PORT datac (496:496:496) (577:577:577)) + (PORT datad (470:470:470) (543:543:543)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|ena) + (DELAY + (ABSOLUTE + (PORT dataa (339:339:339) (400:400:400)) + (PORT datab (493:493:493) (574:574:574)) + (PORT datac (499:499:499) (582:582:582)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_high\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (923:923:923) (910:910:910)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (422:422:422) (450:450:450)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[2\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (317:317:317) (390:390:390)) + (PORT datab (375:375:375) (435:435:435)) + (PORT datac (336:336:336) (388:388:388)) + (PORT datad (354:354:354) (429:429:429)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[2\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (337:337:337) (405:405:405)) + (PORT datab (633:633:633) (729:729:729)) + (PORT datac (88:88:88) (110:110:110)) + (PORT datad (165:165:165) (194:194:194)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~1) + (DELAY + (ABSOLUTE + (PORT datab (385:385:385) (449:449:449)) + (PORT datad (354:354:354) (418:418:418)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[2\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (483:483:483) (561:561:561)) + (PORT datab (324:324:324) (383:383:383)) + (PORT datac (175:175:175) (210:210:210)) + (PORT datad (341:341:341) (398:398:398)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (907:907:907) (911:911:911)) + (PORT asdata (489:489:489) (542:542:542)) + (PORT ena (405:405:405) (422:422:422)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (907:907:907) (911:911:911)) + (PORT asdata (490:490:490) (543:543:543)) + (PORT ena (677:677:677) (748:748:748)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~78) + (DELAY + (ABSOLUTE + (PORT dataa (374:374:374) (452:452:452)) + (PORT datab (130:130:130) (178:178:178)) + (PORT datad (124:124:124) (150:150:150)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_78\~0) + (DELAY + (ABSOLUTE + (PORT dataa (464:464:464) (545:545:545)) + (PORT datab (410:410:410) (489:489:489)) + (PORT datac (349:349:349) (413:413:413)) + (PORT datad (511:511:511) (586:586:586)) (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (911:911:911)) + (PORT asdata (281:281:281) (301:301:301)) + (PORT ena (768:768:768) (845:845:845)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~79) + (DELAY + (ABSOLUTE + (PORT dataa (391:391:391) (468:468:468)) + (PORT datab (466:466:466) (537:537:537)) + (PORT datad (722:722:722) (817:817:817)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_34) + (DELAY + (ABSOLUTE + (PORT dataa (538:538:538) (642:642:642)) + (PORT datac (865:865:865) (971:971:971)) + (PORT datad (626:626:626) (722:722:722)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (470:470:470) (544:544:544)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_35) + (DELAY + (ABSOLUTE + (PORT dataa (541:541:541) (646:646:646)) + (PORT datac (867:867:867) (973:973:973)) + (PORT datad (628:628:628) (724:724:724)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (419:419:419) (436:436:436)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_31) + (DELAY + (ABSOLUTE + (PORT dataa (537:537:537) (641:641:641)) + (PORT datab (640:640:640) (744:744:744)) + (PORT datac (433:433:433) (496:496:496)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (652:652:652) (723:723:723)) + (PORT ena (432:432:432) (460:460:460)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_30) + (DELAY + (ABSOLUTE + (PORT dataa (532:532:532) (635:635:635)) + (PORT datab (638:638:638) (741:741:741)) + (PORT datac (433:433:433) (495:495:495)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~75) + (DELAY + (ABSOLUTE + (PORT dataa (122:122:122) (155:155:155)) + (PORT datab (129:129:129) (176:176:176)) + (PORT datad (107:107:107) (125:125:125)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (352:352:352) (408:408:408)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (644:644:644) (699:699:699)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (629:629:629) (698:698:698)) + (PORT ena (634:634:634) (686:686:686)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~76) + (DELAY + (ABSOLUTE + (PORT dataa (472:472:472) (555:555:555)) + (PORT datab (129:129:129) (177:177:177)) + (PORT datad (371:371:371) (442:442:442)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (907:907:907) (912:912:912)) + (PORT asdata (517:517:517) (573:573:573)) + (PORT ena (669:669:669) (725:725:725)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~77) + (DELAY + (ABSOLUTE + (PORT dataa (195:195:195) (232:232:232)) + (PORT datad (505:505:505) (587:587:587)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~80) + (DELAY + (ABSOLUTE + (PORT dataa (289:289:289) (337:337:337)) + (PORT datab (272:272:272) (316:316:316)) + (PORT datac (412:412:412) (469:469:469)) + (PORT datad (439:439:439) (505:505:505)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (907:907:907) (912:912:912)) + (PORT asdata (488:488:488) (538:538:538)) + (PORT ena (501:501:501) (530:530:530)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (907:907:907) (912:912:912)) + (PORT asdata (488:488:488) (537:537:537)) + (PORT ena (518:518:518) (557:557:557)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~74) + (DELAY + (ABSOLUTE + (PORT dataa (197:197:197) (240:240:240)) + (PORT datab (128:128:128) (176:176:176)) + (PORT datad (189:189:189) (222:222:222)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (919:919:919)) + (PORT asdata (625:625:625) (694:694:694)) + (PORT ena (417:417:417) (434:434:434)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (919:919:919)) + (PORT asdata (625:625:625) (694:694:694)) + (PORT ena (435:435:435) (465:465:465)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~73) + (DELAY + (ABSOLUTE + (PORT dataa (130:130:130) (179:179:179)) + (PORT datab (124:124:124) (155:155:155)) + (PORT datad (112:112:112) (133:133:133)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~81) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (135:135:135)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datad (321:321:321) (377:377:377)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (612:612:612) (709:709:709)) + (PORT datab (362:362:362) (429:429:429)) + (PORT datac (349:349:349) (410:410:410)) + (PORT datad (723:723:723) (818:818:818)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (358:358:358) (420:420:420)) + (PORT datab (339:339:339) (401:401:401)) + (PORT datac (369:369:369) (438:438:438)) + (PORT datad (637:637:637) (733:733:733)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (216:216:216) (256:256:256)) + (PORT datab (101:101:101) (129:129:129)) + (PORT datac (340:340:340) (398:398:398)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~92) + (DELAY + (ABSOLUTE + (PORT dataa (492:492:492) (585:585:585)) + (PORT datab (364:364:364) (433:433:433)) + (PORT datac (340:340:340) (400:400:400)) + (PORT datad (325:325:325) (378:378:378)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (217:217:217) (261:261:261)) + (PORT datab (228:228:228) (271:271:271)) + (PORT datac (320:320:320) (374:374:374)) + (PORT datad (310:310:310) (357:357:357)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_74) + (DELAY + (ABSOLUTE + (PORT dataa (575:575:575) (649:649:649)) + (PORT datac (634:634:634) (729:729:729)) + (PORT datad (492:492:492) (558:558:558)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_62) + (DELAY + (ABSOLUTE + (PORT datab (505:505:505) (580:580:580)) + (PORT datac (633:633:633) (728:728:728)) + (PORT datad (431:431:431) (482:482:482)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (237:237:237) (287:287:287)) + (PORT datab (580:580:580) (654:654:654)) + (PORT datac (906:906:906) (1026:1026:1026)) + (PORT datad (318:318:318) (371:371:371)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (633:633:633) (693:693:693)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (907:907:907) (911:911:911)) + (PORT asdata (380:380:380) (419:419:419)) + (PORT ena (405:405:405) (422:422:422)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (911:911:911)) + (PORT asdata (279:279:279) (297:297:297)) + (PORT ena (768:768:768) (845:845:845)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~55) + (DELAY + (ABSOLUTE + (PORT dataa (138:138:138) (175:175:175)) + (PORT datab (353:353:353) (422:422:422)) + (PORT datad (188:188:188) (235:235:235)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (907:907:907) (911:911:911)) + (PORT asdata (382:382:382) (421:421:421)) + (PORT ena (677:677:677) (748:748:748)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~56) + (DELAY + (ABSOLUTE + (PORT datab (103:103:103) (132:132:132)) + (PORT datad (360:360:360) (428:428:428)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (907:907:907) (911:911:911)) + (PORT asdata (477:477:477) (521:521:521)) + (PORT ena (505:505:505) (542:542:542)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (907:907:907) (911:911:911)) + (PORT asdata (476:476:476) (520:520:520)) + (PORT ena (417:417:417) (434:434:434)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~57) + (DELAY + (ABSOLUTE + (PORT dataa (131:131:131) (181:181:181)) + (PORT datab (138:138:138) (173:173:173)) + (PORT datad (122:122:122) (144:144:144)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (547:547:547) (605:605:605)) + (PORT ena (644:644:644) (699:699:699)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (548:548:548) (605:605:605)) + (PORT ena (634:634:634) (686:686:686)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~59) + (DELAY + (ABSOLUTE + (PORT dataa (478:478:478) (561:561:561)) + (PORT datab (129:129:129) (177:177:177)) + (PORT datad (364:364:364) (435:435:435)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (548:548:548) (617:617:617)) + (PORT ena (419:419:419) (436:436:436)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (550:550:550) (619:619:619)) + (PORT ena (432:432:432) (460:460:460)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~58) + (DELAY + (ABSOLUTE + (PORT dataa (123:123:123) (157:157:157)) + (PORT datab (130:130:130) (178:178:178)) + (PORT datad (105:105:105) (124:124:124)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (907:907:907) (912:912:912)) + (PORT asdata (745:745:745) (812:812:812)) + (PORT ena (669:669:669) (725:725:725)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~60) + (DELAY + (ABSOLUTE + (PORT dataa (336:336:336) (395:395:395)) + (PORT datab (173:173:173) (211:211:211)) + (PORT datad (510:510:510) (592:592:592)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (919:919:919)) + (PORT asdata (623:623:623) (683:683:683)) + (PORT ena (501:501:501) (535:535:535)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (919:919:919)) + (PORT asdata (623:623:623) (684:684:684)) + (PORT ena (502:502:502) (534:534:534)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~53) + (DELAY + (ABSOLUTE + (PORT dataa (218:218:218) (262:262:262)) + (PORT datab (226:226:226) (269:269:269)) + (PORT datad (117:117:117) (153:153:153)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~54) + (DELAY + (ABSOLUTE + (PORT dataa (459:459:459) (545:545:545)) + (PORT datac (473:473:473) (541:541:541)) + (PORT datad (453:453:453) (515:515:515)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~61) + (DELAY + (ABSOLUTE + (PORT dataa (336:336:336) (392:392:392)) + (PORT datab (324:324:324) (387:387:387)) + (PORT datac (173:173:173) (209:209:209)) + (PORT datad (174:174:174) (205:205:205)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~62) + (DELAY + (ABSOLUTE + (PORT dataa (335:335:335) (393:393:393)) + (PORT datab (360:360:360) (420:420:420)) + (PORT datac (597:597:597) (688:688:688)) + (PORT datad (332:332:332) (383:383:383)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_75) + (DELAY + (ABSOLUTE + (PORT dataa (574:574:574) (649:649:649)) + (PORT datac (632:632:632) (727:727:727)) + (PORT datad (490:490:490) (556:556:556)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (348:348:348) (376:376:376)) + (PORT ena (621:621:621) (659:659:659)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (495:495:495) (573:573:573)) + (PORT datab (364:364:364) (417:417:417)) + (PORT datad (207:207:207) (252:252:252)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (131:131:131) (182:182:182)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datad (317:317:317) (369:369:369)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_4\|d0_out) + (DELAY + (ABSOLUTE + (PORT datac (525:525:525) (619:619:619)) + (PORT datad (323:323:323) (369:369:369)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (925:925:925) (1053:1053:1053)) + (PORT datab (102:102:102) (131:131:131)) + (PORT datac (300:300:300) (346:346:346)) + (PORT datad (183:183:183) (217:217:217)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[4\]) + (DELAY + (ABSOLUTE + (PORT datab (514:514:514) (593:593:593)) + (PORT datad (521:521:521) (610:610:610)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (904:904:904) (891:891:891)) + (PORT ena (1032:1032:1032) (1123:1123:1123)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_4\|d1_out) + (DELAY + (ABSOLUTE + (PORT dataa (610:610:610) (709:709:709)) + (PORT datab (540:540:540) (641:641:641)) + (PORT datac (513:513:513) (602:602:602)) + (PORT datad (323:323:323) (369:369:369)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH datab combout (166:166:166) (174:174:174)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (901:901:901) (906:906:906)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (505:505:505) (549:549:549)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (907:907:907) (911:911:911)) + (PORT asdata (948:948:948) (1056:1056:1056)) + (PORT ena (505:505:505) (542:542:542)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (907:907:907) (911:911:911)) + (PORT asdata (947:947:947) (1055:1055:1055)) + (PORT ena (417:417:417) (434:434:434)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~64) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (256:256:256)) + (PORT datab (135:135:135) (171:171:171)) + (PORT datad (123:123:123) (146:146:146)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (919:919:919)) + (PORT asdata (641:641:641) (707:707:707)) + (PORT ena (501:501:501) (535:535:535)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (919:919:919)) + (PORT asdata (641:641:641) (707:707:707)) + (PORT ena (502:502:502) (534:534:534)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~63) + (DELAY + (ABSOLUTE + (PORT dataa (218:218:218) (262:262:262)) + (PORT datab (225:225:225) (268:268:268)) + (PORT datad (116:116:116) (153:153:153)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (919:919:919)) + (PORT asdata (959:959:959) (1069:1069:1069)) + (PORT ena (656:656:656) (712:712:712)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (454:454:454) (520:520:520)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (919:919:919)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (637:637:637) (680:680:680)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~65) + (DELAY + (ABSOLUTE + (PORT dataa (383:383:383) (452:452:452)) + (PORT datab (386:386:386) (451:451:451)) + (PORT datad (116:116:116) (153:153:153)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (907:907:907) (911:911:911)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (405:405:405) (422:422:422)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (911:911:911)) + (PORT asdata (930:930:930) (1026:1026:1026)) + (PORT ena (768:768:768) (845:845:845)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~69) + (DELAY + (ABSOLUTE + (PORT dataa (385:385:385) (461:461:461)) + (PORT datab (318:318:318) (385:385:385)) + (PORT datad (193:193:193) (227:227:227)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (907:907:907) (912:912:912)) + (PORT asdata (802:802:802) (897:897:897)) + (PORT ena (655:655:655) (712:712:712)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (1109:1109:1109) (1240:1240:1240)) + (PORT ena (644:644:644) (699:699:699)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~68) + (DELAY + (ABSOLUTE + (PORT dataa (351:351:351) (419:419:419)) + (PORT datab (362:362:362) (440:440:440)) + (PORT datad (370:370:370) (441:441:441)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (907:907:907) (912:912:912)) + (PORT asdata (804:804:804) (899:899:899)) + (PORT ena (669:669:669) (725:725:725)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (1109:1109:1109) (1240:1240:1240)) + (PORT ena (634:634:634) (686:686:686)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~66) + (DELAY + (ABSOLUTE + (PORT dataa (475:475:475) (559:559:559)) + (PORT datab (305:305:305) (357:357:357)) + (PORT datad (288:288:288) (331:331:331)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~67) + (DELAY + (ABSOLUTE + (PORT datab (523:523:523) (615:615:615)) + (PORT datad (319:319:319) (371:371:371)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~70) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (402:402:402)) + (PORT datab (351:351:351) (417:417:417)) + (PORT datac (319:319:319) (367:367:367)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~71) + (DELAY + (ABSOLUTE + (PORT dataa (173:173:173) (213:213:213)) + (PORT datab (336:336:336) (395:395:395)) + (PORT datad (317:317:317) (367:367:367)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~72) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (441:441:441) (509:509:509)) + (PORT datac (337:337:337) (395:395:395)) + (PORT datad (448:448:448) (517:517:517)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (901:901:901) (906:906:906)) + (PORT asdata (467:467:467) (514:514:514)) + (PORT ena (501:501:501) (528:528:528)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[5\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (785:785:785) (904:904:904)) + (PORT datab (578:578:578) (651:651:651)) + (PORT datad (293:293:293) (331:331:331)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[5\]\~17) + (DELAY + (ABSOLUTE + (PORT datab (131:131:131) (180:180:180)) + (PORT datac (172:172:172) (204:204:204)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[5\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (300:300:300) (352:352:352)) + (PORT datab (115:115:115) (142:142:142)) + (PORT datac (90:90:90) (111:111:111)) + (PORT datad (1017:1017:1017) (1138:1138:1138)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[5\]) + (DELAY + (ABSOLUTE + (PORT datab (492:492:492) (571:571:571)) + (PORT datad (522:522:522) (610:610:610)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (904:904:904) (891:891:891)) + (PORT ena (1032:1032:1032) (1123:1123:1123)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~10) + (DELAY + (ABSOLUTE + (PORT datac (706:706:706) (795:795:795)) + (PORT datad (1000:1000:1000) (1171:1171:1171)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_43\~4) + (DELAY + (ABSOLUTE + (PORT dataa (551:551:551) (647:647:647)) + (PORT datab (1017:1017:1017) (1182:1182:1182)) + (PORT datac (110:110:110) (143:143:143)) + (PORT datad (1054:1054:1054) (1231:1231:1231)) + (IOPATH dataa combout (158:158:158) (173:173:173)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_44) + (DELAY + (ABSOLUTE + (PORT dataa (1073:1073:1073) (1253:1253:1253)) + (PORT datab (1015:1015:1015) (1180:1180:1180)) + (PORT datac (114:114:114) (148:148:148)) + (PORT datad (680:680:680) (792:792:792)) + (IOPATH dataa combout (158:158:158) (173:173:173)) + (IOPATH datab combout (160:160:160) (176:176:176)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[6\]) + (DELAY + (ABSOLUTE + (PORT datac (481:481:481) (555:555:555)) + (PORT datad (520:520:520) (609:609:609)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (904:904:904) (891:891:891)) + (PORT ena (1032:1032:1032) (1123:1123:1123)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[6\]) + (DELAY + (ABSOLUTE + (PORT dataa (108:108:108) (142:142:142)) + (PORT datab (108:108:108) (139:139:139)) + (PORT datac (513:513:513) (595:595:595)) + (PORT datad (108:108:108) (128:128:128)) + (IOPATH dataa combout (158:158:158) (173:173:173)) + (IOPATH datab combout (160:160:160) (176:176:176)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (901:901:901) (906:906:906)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (505:505:505) (549:549:549)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (901:901:901) (906:906:906)) + (PORT asdata (347:347:347) (376:376:376)) + (PORT ena (501:501:501) (528:528:528)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (355:355:355) (410:410:410)) + (PORT datab (578:578:578) (651:651:651)) + (PORT datad (293:293:293) (332:332:332)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~20) + (DELAY + (ABSOLUTE + (PORT datab (130:130:130) (177:177:177)) + (PORT datac (173:173:173) (206:206:206)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (301:301:301) (352:352:352)) + (PORT datab (450:450:450) (517:517:517)) + (PORT datac (88:88:88) (109:109:109)) + (PORT datad (1017:1017:1017) (1138:1138:1138)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~82) + (DELAY + (ABSOLUTE + (PORT dataa (612:612:612) (710:710:710)) + (PORT datab (314:314:314) (362:362:362)) + (PORT datac (347:347:347) (402:402:402)) + (PORT datad (337:337:337) (392:392:392)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_ds\[6\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (442:442:442) (511:511:511)) + (PORT datab (619:619:619) (708:708:708)) + (PORT datac (348:348:348) (413:413:413)) + (PORT datad (471:471:471) (545:545:545)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sw1_\|db_down\[6\]\~1) + (DELAY + (ABSOLUTE + (PORT datab (346:346:346) (403:403:403)) + (PORT datac (216:216:216) (263:263:263)) + (PORT datad (443:443:443) (505:505:505)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_66_oe) + (DELAY + (ABSOLUTE + (PORT dataa (1301:1301:1301) (1520:1520:1520)) + (PORT datab (695:695:695) (817:817:817)) + (PORT datac (314:314:314) (380:380:380)) + (PORT datad (900:900:900) (1043:1043:1043)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[1\]) + (DELAY + (ABSOLUTE + (PORT dataa (513:513:513) (598:598:598)) + (PORT datac (495:495:495) (572:572:572)) + (PORT datad (336:336:336) (391:391:391)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_high\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (931:931:931) (916:916:916)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (421:421:421) (449:449:449)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[1\]\~4) + (DELAY + (ABSOLUTE + (PORT datab (365:365:365) (431:431:431)) + (PORT datac (315:315:315) (376:376:376)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[1\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (510:510:510) (598:598:598)) + (PORT datab (103:103:103) (131:131:131)) + (PORT datac (347:347:347) (405:405:405)) + (PORT datad (467:467:467) (540:540:540)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_high\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (923:923:923) (910:910:910)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (422:422:422) (450:450:450)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[1\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (337:337:337) (399:399:399)) + (PORT datab (384:384:384) (462:462:462)) + (PORT datac (603:603:603) (701:701:701)) + (PORT datad (600:600:600) (693:693:693)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[1\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (512:512:512) (601:601:601)) + (PORT datab (489:489:489) (569:569:569)) + (PORT datac (352:352:352) (411:411:411)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_low\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (923:923:923) (910:910:910)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (422:422:422) (450:450:450)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|alu_\|alu_op2\[1\]\~1) (DELAY (ABSOLUTE - (PORT dataa (242:242:242) (303:303:303)) - (PORT datab (240:240:240) (302:302:302)) - (PORT datac (469:469:469) (547:547:547)) - (PORT datad (356:356:356) (422:422:422)) - (IOPATH dataa combout (165:165:165) (173:173:173)) - (IOPATH datab combout (196:196:196) (205:205:205)) + (PORT dataa (311:311:311) (378:378:378)) + (PORT datab (114:114:114) (142:142:142)) + (PORT datac (101:101:101) (122:122:122)) + (PORT datad (294:294:294) (352:352:352)) + (IOPATH dataa combout (188:188:188) (203:203:203)) + (IOPATH datab combout (190:190:190) (205:205:205)) (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -19648,10 +17682,10 @@ (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_10\~1) (DELAY (ABSOLUTE - (PORT dataa (285:285:285) (335:335:335)) - (PORT datab (346:346:346) (413:413:413)) - (PORT datac (335:335:335) (386:386:386)) - (PORT datad (346:346:346) (404:404:404)) + (PORT dataa (494:494:494) (584:584:584)) + (PORT datab (473:473:473) (558:558:558)) + (PORT datac (601:601:601) (699:699:699)) + (PORT datad (95:95:95) (114:114:114)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (124:124:124)) @@ -19661,30 +17695,42 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~9) + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_8\~0) (DELAY (ABSOLUTE - (PORT dataa (443:443:443) (511:511:511)) - (PORT datab (319:319:319) (379:379:379)) - (PORT datac (103:103:103) (125:125:125)) - (PORT datad (97:97:97) (117:117:117)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[0\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (424:424:424) (483:483:483)) - (PORT datab (325:325:325) (379:379:379)) - (PORT datac (607:607:607) (727:727:727)) - (PORT datad (498:498:498) (582:582:582)) + (PORT dataa (497:497:497) (587:587:587)) + (PORT datab (478:478:478) (565:565:565)) + (PORT datac (604:604:604) (702:702:702)) + (PORT datad (94:94:94) (113:113:113)) (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_10\~0) + (DELAY + (ABSOLUTE + (PORT datac (600:600:600) (714:714:714)) + (PORT datad (167:167:167) (196:196:196)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~5) + (DELAY + (ABSOLUTE + (PORT dataa (351:351:351) (413:413:413)) + (PORT datab (525:525:525) (596:596:596)) + (PORT datac (330:330:330) (391:391:391)) + (PORT datad (324:324:324) (378:378:378)) + (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -19693,11 +17739,493 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[0\]\~8) + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~2) (DELAY (ABSOLUTE - (PORT datac (90:90:90) (112:112:112)) - (PORT datad (129:129:129) (163:163:163)) + (PORT dataa (473:473:473) (559:559:559)) + (PORT datab (1175:1175:1175) (1343:1343:1343)) + (PORT datac (836:836:836) (983:983:983)) + (PORT datad (810:810:810) (925:925:925)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R) + (DELAY + (ABSOLUTE + (PORT dataa (304:304:304) (356:356:356)) + (PORT datab (105:105:105) (136:136:136)) + (PORT datac (611:611:611) (695:695:695)) + (PORT datad (757:757:757) (897:897:897)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[0\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (156:156:156) (206:206:206)) + (PORT datab (149:149:149) (191:191:191)) + (PORT datac (613:613:613) (703:703:703)) + (PORT datad (133:133:133) (164:164:164)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[0\]) + (DELAY + (ABSOLUTE + (PORT dataa (513:513:513) (597:597:597)) + (PORT datac (496:496:496) (574:574:574)) + (PORT datad (352:352:352) (418:418:418)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_high\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (931:931:931) (916:916:916)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (421:421:421) (449:449:449)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[0\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (223:223:223) (264:264:264)) + (PORT datab (497:497:497) (594:594:594)) + (PORT datac (185:185:185) (216:216:216)) + (PORT datad (203:203:203) (255:255:255)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[0\]\~22) + (DELAY + (ABSOLUTE + (PORT datab (460:460:460) (531:531:531)) + (PORT datac (448:448:448) (522:522:522)) + (PORT datad (640:640:640) (765:765:765)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[0\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (480:480:480) (557:557:557)) + (PORT datab (704:704:704) (800:800:800)) + (PORT datad (93:93:93) (111:111:111)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[0\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (354:354:354) (420:420:420)) + (PORT datab (384:384:384) (448:448:448)) + (PORT datac (349:349:349) (413:413:413)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (158:158:158) (208:208:208)) + (PORT datab (150:150:150) (192:192:192)) + (PORT datac (612:612:612) (703:703:703)) + (PORT datad (130:130:130) (160:160:160)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|result_lo\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (914:914:914) (919:919:919)) + (PORT asdata (281:281:281) (300:300:300)) + (PORT ena (922:922:922) (1022:1022:1022)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (336:336:336) (403:403:403)) + (PORT datab (370:370:370) (442:442:442)) + (PORT datac (496:496:496) (574:574:574)) + (PORT datad (456:456:456) (529:529:529)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT datac (482:482:482) (557:557:557)) + (PORT datad (92:92:92) (109:109:109)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_low\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (931:931:931) (916:916:916)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (409:409:409) (429:429:429)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (223:223:223) (263:263:263)) + (PORT datab (321:321:321) (390:390:390)) + (PORT datac (184:184:184) (216:216:216)) + (PORT datad (209:209:209) (264:264:264)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (287:287:287) (333:333:333)) + (PORT datab (316:316:316) (368:368:368)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~1) + (DELAY + (ABSOLUTE + (PORT dataa (448:448:448) (524:524:524)) + (PORT datab (146:146:146) (196:196:196)) + (PORT datac (367:367:367) (447:447:447)) + (PORT datad (436:436:436) (506:506:506)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (182:182:182) (193:193:193)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (624:624:624) (728:728:728)) + (PORT datab (446:446:446) (514:514:514)) + (PORT datac (332:332:332) (387:387:387)) + (PORT datad (1041:1041:1041) (1212:1212:1212)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1458:1458:1458) (1682:1682:1682)) + (PORT datab (586:586:586) (674:674:674)) + (PORT datac (189:189:189) (224:224:224)) + (PORT datad (966:966:966) (1113:1113:1113)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (118:118:118) (150:150:150)) + (PORT datab (1092:1092:1092) (1260:1260:1260)) + (PORT datac (497:497:497) (577:577:577)) + (PORT datad (643:643:643) (733:733:733)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (108:108:108) (141:141:141)) + (PORT datab (672:672:672) (783:783:783)) + (PORT datac (116:116:116) (144:144:144)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (108:108:108) (142:142:142)) + (PORT datab (107:107:107) (137:137:137)) + (PORT datac (89:89:89) (111:111:111)) + (PORT datad (316:316:316) (362:362:362)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~0) + (DELAY + (ABSOLUTE + (PORT dataa (436:436:436) (506:506:506)) + (PORT datab (464:464:464) (535:535:535)) + (PORT datac (112:112:112) (138:138:138)) + (PORT datad (336:336:336) (393:393:393)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~1) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (133:133:133)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datad (103:103:103) (120:120:120)) + (IOPATH dataa combout (188:188:188) (184:184:184)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (919:919:919)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (586:586:586) (688:688:688)) + (PORT datab (147:147:147) (197:197:197)) + (PORT datac (469:469:469) (560:560:560)) + (PORT datad (639:639:639) (764:764:764)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~2) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (137:137:137)) + (PORT datab (103:103:103) (131:131:131)) + (PORT datac (571:571:571) (664:664:664)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (446:446:446) (527:527:527)) + (PORT datab (107:107:107) (138:138:138)) + (PORT datad (638:638:638) (763:763:763)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (402:402:402) (476:476:476)) + (PORT datab (610:610:610) (702:702:702)) + (PORT datac (307:307:307) (357:357:357)) + (PORT datad (428:428:428) (494:494:494)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (182:182:182) (177:177:177)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (370:370:370) (443:443:443)) + (PORT datab (106:106:106) (135:135:135)) + (PORT datac (386:386:386) (453:453:453)) + (PORT datad (363:363:363) (434:434:434)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (602:602:602) (701:701:701)) + (PORT datab (503:503:503) (601:601:601)) + (PORT datac (281:281:281) (320:320:320)) + (PORT datad (309:309:309) (372:372:372)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (366:366:366) (433:433:433)) + (PORT datab (491:491:491) (572:572:572)) + (PORT datac (498:498:498) (579:579:579)) + (PORT datad (165:165:165) (192:192:192)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -19705,12 +18233,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_high\[0\]) + (INSTANCE z80_\|alu_\|op2_low\[0\]) (DELAY (ABSOLUTE - (PORT clk (915:915:915) (900:900:900)) + (PORT clk (923:923:923) (910:910:910)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (420:420:420) (448:448:448)) + (PORT ena (422:422:422) (450:450:450)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -19724,76 +18252,182 @@ (INSTANCE z80_\|alu_\|alu_op2\[0\]\~3) (DELAY (ABSOLUTE - (PORT dataa (235:235:235) (302:302:302)) - (PORT datab (358:358:358) (435:435:435)) - (PORT datac (469:469:469) (547:547:547)) - (PORT datad (357:357:357) (423:423:423)) - (IOPATH dataa combout (195:195:195) (203:203:203)) - (IOPATH datab combout (166:166:166) (176:176:176)) + (PORT dataa (210:210:210) (274:274:274)) + (PORT datab (209:209:209) (247:247:247)) + (PORT datac (321:321:321) (371:371:371)) + (PORT datad (205:205:205) (259:259:259)) + (IOPATH dataa combout (188:188:188) (203:203:203)) + (IOPATH datab combout (190:190:190) (205:205:205)) (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~12) - (DELAY - (ABSOLUTE - (PORT dataa (466:466:466) (556:556:556)) - (PORT datab (117:117:117) (151:151:151)) - (PORT datac (451:451:451) (526:526:526)) - (PORT datad (493:493:493) (588:588:588)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~8) - (DELAY - (ABSOLUTE - (PORT dataa (441:441:441) (526:526:526)) - (PORT datab (102:102:102) (131:131:131)) - (PORT datac (986:986:986) (1116:1116:1116)) - (PORT datad (432:432:432) (495:495:495)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_1) (DELAY (ABSOLUTE - (PORT dataa (360:360:360) (423:423:423)) - (PORT datab (977:977:977) (1099:1099:1099)) - (PORT datac (93:93:93) (116:116:116)) - (PORT datad (443:443:443) (508:508:508)) + (PORT dataa (623:623:623) (738:738:738)) + (PORT datac (598:598:598) (681:681:681)) + (PORT datad (95:95:95) (115:115:115)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla26M3T5_8) + (DELAY + (ABSOLUTE + (PORT datab (543:543:543) (661:661:661)) + (PORT datac (453:453:453) (523:523:523)) + (PORT datad (774:774:774) (938:938:938)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1708:1708:1708) (1961:1961:1961)) + (PORT datab (102:102:102) (131:131:131)) + (PORT datac (922:922:922) (1069:1069:1069)) + (PORT datad (444:444:444) (509:509:509)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~16) + (DELAY + (ABSOLUTE + (PORT dataa (774:774:774) (902:902:902)) + (PORT datac (328:328:328) (384:384:384)) + (PORT datad (90:90:90) (106:106:106)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~13) + (DELAY + (ABSOLUTE + (PORT dataa (928:928:928) (1062:1062:1062)) + (PORT datab (1071:1071:1071) (1231:1231:1231)) + (PORT datac (652:652:652) (763:763:763)) + (PORT datad (805:805:805) (917:917:917)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~17) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (133:133:133)) + (PORT datab (340:340:340) (406:406:406)) + (PORT datac (109:109:109) (134:134:134)) + (PORT datad (503:503:503) (583:583:583)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~44) + (DELAY + (ABSOLUTE + (PORT dataa (206:206:206) (245:245:245)) + (PORT datab (125:125:125) (158:158:158)) + (PORT datac (330:330:330) (389:389:389)) + (PORT datad (308:308:308) (362:362:362)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~20) + (DELAY + (ABSOLUTE + (PORT dataa (927:927:927) (1061:1061:1061)) + (PORT datab (628:628:628) (755:755:755)) + (PORT datac (652:652:652) (763:763:763)) + (PORT datad (805:805:805) (917:917:917)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~21) (DELAY (ABSOLUTE - (PORT dataa (1328:1328:1328) (1554:1554:1554)) - (PORT datab (847:847:847) (991:991:991)) - (PORT datac (471:471:471) (546:546:546)) - (PORT datad (574:574:574) (679:679:679)) - (IOPATH dataa combout (159:159:159) (163:163:163)) + (PORT dataa (121:121:121) (154:154:154)) + (PORT datab (627:627:627) (753:753:753)) + (PORT datac (547:547:547) (643:643:643)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~18) + (DELAY + (ABSOLUTE + (PORT dataa (517:517:517) (605:605:605)) + (PORT datab (672:672:672) (782:782:782)) + (PORT datac (1179:1179:1179) (1376:1376:1376)) + (PORT datad (892:892:892) (1007:1007:1007)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~19) + (DELAY + (ABSOLUTE + (PORT dataa (116:116:116) (147:147:147)) + (PORT datab (130:130:130) (165:165:165)) + (PORT datac (89:89:89) (111:111:111)) + (PORT datad (111:111:111) (133:133:133)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -19804,12 +18438,12 @@ (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~22) (DELAY (ABSOLUTE - (PORT dataa (310:310:310) (357:357:357)) - (PORT datab (556:556:556) (654:654:654)) - (PORT datac (365:365:365) (433:433:433)) - (PORT datad (450:450:450) (510:510:510)) + (PORT dataa (118:118:118) (150:150:150)) + (PORT datab (127:127:127) (160:160:160)) + (PORT datac (327:327:327) (382:382:382)) + (PORT datad (332:332:332) (389:389:389)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -19817,13 +18451,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~19) + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~43) (DELAY (ABSOLUTE - (PORT dataa (544:544:544) (627:627:627)) - (PORT datab (227:227:227) (274:274:274)) - (PORT datac (528:528:528) (616:616:616)) - (PORT datad (642:642:642) (749:749:749)) + (PORT dataa (360:360:360) (434:434:434)) + (PORT datab (522:522:522) (614:614:614)) + (PORT datac (891:891:891) (1019:1019:1019)) + (PORT datad (334:334:334) (389:389:389)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~24) + (DELAY + (ABSOLUTE + (PORT dataa (700:700:700) (803:803:803)) + (PORT datab (574:574:574) (676:676:676)) + (PORT datac (1686:1686:1686) (1931:1931:1931)) + (PORT datad (821:821:821) (948:948:948)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -19833,29 +18483,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~27) + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~25) (DELAY (ABSOLUTE - (PORT dataa (124:124:124) (158:158:158)) - (PORT datab (117:117:117) (146:146:146)) - (PORT datac (103:103:103) (125:125:125)) - (PORT datad (109:109:109) (129:129:129)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT dataa (516:516:516) (597:597:597)) + (PORT datab (667:667:667) (780:780:780)) + (PORT datac (501:501:501) (584:584:584)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~29) + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~35) (DELAY (ABSOLUTE - (PORT datab (123:123:123) (158:158:158)) - (PORT datac (102:102:102) (129:129:129)) - (PORT datad (196:196:196) (226:226:226)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT dataa (1209:1209:1209) (1405:1405:1405)) + (PORT datab (1155:1155:1155) (1331:1331:1331)) + (PORT datac (867:867:867) (1020:1020:1020)) + (PORT datad (600:600:600) (688:688:688)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -19866,75 +18518,13 @@ (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~23) (DELAY (ABSOLUTE - (PORT dataa (104:104:104) (136:136:136)) - (PORT datab (343:343:343) (402:402:402)) - (PORT datac (90:90:90) (111:111:111)) - (PORT datad (103:103:103) (120:120:120)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~37) - (DELAY - (ABSOLUTE - (PORT datab (730:730:730) (863:863:863)) - (PORT datac (490:490:490) (574:574:574)) - (PORT datad (634:634:634) (727:727:727)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~38) - (DELAY - (ABSOLUTE - (PORT dataa (714:714:714) (833:833:833)) - (PORT datab (568:568:568) (671:671:671)) - (PORT datac (830:830:830) (949:949:949)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~24) - (DELAY - (ABSOLUTE - (PORT dataa (1153:1153:1153) (1315:1315:1315)) - (PORT datab (528:528:528) (618:618:618)) - (PORT datac (659:659:659) (762:762:762)) - (PORT datad (597:597:597) (687:687:687)) + (PORT dataa (121:121:121) (159:159:159)) + (PORT datab (575:575:575) (677:677:677)) + (PORT datac (306:306:306) (353:353:353)) + (PORT datad (458:458:458) (528:528:528)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~25) - (DELAY - (ABSOLUTE - (PORT dataa (506:506:506) (584:584:584)) - (PORT datab (581:581:581) (661:661:661)) - (PORT datac (499:499:499) (576:576:576)) - (PORT datad (301:301:301) (346:346:346)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -19944,12 +18534,28 @@ (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~26) (DELAY (ABSOLUTE - (PORT dataa (846:846:846) (994:994:994)) - (PORT datab (228:228:228) (276:276:276)) - (PORT datac (520:520:520) (602:602:602)) - (PORT datad (643:643:643) (751:751:751)) - (IOPATH dataa combout (170:170:170) (163:163:163)) + (PORT dataa (794:794:794) (905:905:905)) + (PORT datab (616:616:616) (719:719:719)) + (PORT datac (797:797:797) (944:944:944)) + (PORT datad (494:494:494) (577:577:577)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~34) + (DELAY + (ABSOLUTE + (PORT dataa (1469:1469:1469) (1716:1716:1716)) + (PORT datab (826:826:826) (950:950:950)) + (PORT datac (823:823:823) (954:954:954)) + (PORT datad (512:512:512) (593:593:593)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -19960,13 +18566,13 @@ (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~27) (DELAY (ABSOLUTE - (PORT dataa (848:848:848) (996:996:996)) - (PORT datab (122:122:122) (153:153:153)) - (PORT datac (1117:1117:1117) (1275:1275:1275)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (PORT dataa (424:424:424) (505:505:505)) + (PORT datab (958:958:958) (1095:1095:1095)) + (PORT datac (469:469:469) (542:542:542)) + (PORT datad (1107:1107:1107) (1301:1301:1301)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -19976,74 +18582,10 @@ (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~28) (DELAY (ABSOLUTE - (PORT dataa (103:103:103) (134:134:134)) - (PORT datab (115:115:115) (144:144:144)) - (PORT datac (334:334:334) (392:392:392)) - (PORT datad (102:102:102) (119:119:119)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~30) - (DELAY - (ABSOLUTE - (PORT dataa (110:110:110) (144:144:144)) - (PORT datab (113:113:113) (142:142:142)) - (PORT datac (464:464:464) (541:541:541)) - (PORT datad (291:291:291) (331:331:331)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~34) - (DELAY - (ABSOLUTE - (PORT dataa (823:823:823) (952:952:952)) - (PORT datab (777:777:777) (887:887:887)) - (PORT datac (874:874:874) (993:993:993)) - (PORT datad (576:576:576) (656:656:656)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~32) - (DELAY - (ABSOLUTE - (PORT dataa (403:403:403) (468:468:468)) - (PORT datab (378:378:378) (450:450:450)) - (PORT datac (865:865:865) (979:979:979)) - (PORT datad (810:810:810) (926:926:926)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~43) - (DELAY - (ABSOLUTE - (PORT dataa (753:753:753) (894:894:894)) - (PORT datab (587:587:587) (675:675:675)) - (PORT datac (873:873:873) (991:991:991)) - (PORT datad (1006:1006:1006) (1178:1178:1178)) + (PORT dataa (106:106:106) (138:138:138)) + (PORT datab (547:547:547) (672:672:672)) + (PORT datac (88:88:88) (109:109:109)) + (PORT datad (1108:1108:1108) (1301:1301:1301)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -20053,61 +18595,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~33) + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~29) (DELAY (ABSOLUTE - (PORT dataa (104:104:104) (136:136:136)) - (PORT datab (458:458:458) (529:529:529)) - (PORT datac (869:869:869) (983:983:983)) - (PORT datad (89:89:89) (107:107:107)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~42) - (DELAY - (ABSOLUTE - (PORT dataa (449:449:449) (528:528:528)) - (PORT datab (591:591:591) (680:680:680)) - (PORT datac (1181:1181:1181) (1374:1374:1374)) - (PORT datad (1001:1001:1001) (1172:1172:1172)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~35) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (133:133:133)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datac (543:543:543) (616:616:616)) - (PORT datad (89:89:89) (107:107:107)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~41) - (DELAY - (ABSOLUTE - (PORT dataa (365:365:365) (427:427:427)) - (PORT datab (1124:1124:1124) (1291:1291:1291)) - (PORT datac (822:822:822) (957:957:957)) - (PORT datad (767:767:767) (909:909:909)) + (PORT dataa (547:547:547) (642:642:642)) + (PORT datab (475:475:475) (558:558:558)) + (PORT datac (807:807:807) (923:923:923)) + (PORT datad (939:939:939) (1070:1070:1070)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -20120,10 +18614,10 @@ (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~30) (DELAY (ABSOLUTE - (PORT dataa (838:838:838) (981:981:981)) - (PORT datab (1110:1110:1110) (1274:1274:1274)) - (PORT datac (715:715:715) (835:835:835)) - (PORT datad (487:487:487) (562:562:562)) + (PORT dataa (104:104:104) (136:136:136)) + (PORT datab (102:102:102) (131:131:131)) + (PORT datac (634:634:634) (725:725:725)) + (PORT datad (90:90:90) (106:106:106)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -20131,31 +18625,15 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~10) - (DELAY - (ABSOLUTE - (PORT dataa (997:997:997) (1156:1156:1156)) - (PORT datab (578:578:578) (684:684:684)) - (PORT datac (104:104:104) (127:127:127)) - (PORT datad (847:847:847) (970:970:970)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~31) (DELAY (ABSOLUTE - (PORT dataa (629:629:629) (717:717:717)) - (PORT datab (104:104:104) (133:133:133)) - (PORT datac (90:90:90) (112:112:112)) - (PORT datad (756:756:756) (863:863:863)) + (PORT dataa (329:329:329) (387:387:387)) + (PORT datab (101:101:101) (129:129:129)) + (PORT datac (91:91:91) (114:114:114)) + (PORT datad (324:324:324) (378:378:378)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -20163,49 +18641,15 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~44) - (DELAY - (ABSOLUTE - (PORT dataa (444:444:444) (511:511:511)) - (PORT datab (1029:1029:1029) (1201:1201:1201)) - (PORT datac (731:731:731) (871:871:871)) - (PORT datad (1007:1007:1007) (1179:1179:1179)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~29) - (DELAY - (ABSOLUTE - (PORT dataa (105:105:105) (137:137:137)) - (PORT datab (378:378:378) (449:449:449)) - (PORT datac (465:465:465) (531:531:531)) - (PORT datad (381:381:381) (441:441:441)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~36) (DELAY (ABSOLUTE - (PORT dataa (276:276:276) (319:319:319)) - (PORT datab (102:102:102) (131:131:131)) - (PORT datac (342:342:342) (406:406:406)) - (PORT datad (89:89:89) (107:107:107)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT dataa (761:761:761) (897:897:897)) + (PORT datac (956:956:956) (1109:1109:1109)) + (PORT datad (1116:1116:1116) (1278:1278:1278)) + (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -20213,15 +18657,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~39) + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~37) (DELAY (ABSOLUTE - (PORT dataa (317:317:317) (376:376:376)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datac (325:325:325) (381:381:381)) - (PORT datad (177:177:177) (203:203:203)) + (PORT dataa (798:798:798) (925:925:925)) + (PORT datab (925:925:925) (1052:1052:1052)) + (PORT datac (88:88:88) (109:109:109)) + (PORT datad (698:698:698) (812:812:812)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -20229,328 +18673,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~40) + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~32) (DELAY (ABSOLUTE (PORT dataa (103:103:103) (133:133:133)) - (PORT datab (519:519:519) (594:594:594)) - (PORT datac (102:102:102) (123:123:123)) - (PORT datad (162:162:162) (191:191:191)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (940:940:940) (1084:1084:1084)) - (PORT datab (810:810:810) (933:933:933)) - (PORT datac (337:337:337) (400:400:400)) - (PORT datad (468:468:468) (534:534:534)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~2) - (DELAY - (ABSOLUTE - (PORT dataa (804:804:804) (935:935:935)) - (PORT datab (454:454:454) (519:519:519)) - (PORT datac (456:456:456) (518:518:518)) - (PORT datad (773:773:773) (884:884:884)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R) - (DELAY - (ABSOLUTE - (PORT dataa (448:448:448) (518:518:518)) - (PORT datab (977:977:977) (1099:1099:1099)) - (PORT datac (330:330:330) (389:389:389)) - (PORT datad (442:442:442) (508:508:508)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[3\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (650:650:650) (763:763:763)) - (PORT datab (116:116:116) (150:150:150)) - (PORT datac (495:495:495) (580:580:580)) - (PORT datad (328:328:328) (378:378:378)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[3\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (144:144:144) (189:189:189)) - (PORT datab (523:523:523) (615:615:615)) - (PORT datac (272:272:272) (314:314:314)) - (PORT datad (614:614:614) (701:701:701)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_high\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (900:900:900)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (420:420:420) (448:448:448)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[3\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (315:315:315) (389:389:389)) - (PORT datab (620:620:620) (740:740:740)) - (PORT datac (310:310:310) (357:357:357)) - (PORT datad (205:205:205) (248:248:248)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[3\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (145:145:145) (193:193:193)) - (PORT datab (104:104:104) (133:133:133)) - (PORT datac (290:290:290) (339:339:339)) - (PORT datad (499:499:499) (584:584:584)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_low\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (900:900:900)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (420:420:420) (448:448:448)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op2\[3\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (229:229:229) (295:295:295)) - (PORT datab (226:226:226) (289:289:289)) - (PORT datac (471:471:471) (549:549:549)) - (PORT datad (352:352:352) (418:418:418)) - (IOPATH dataa combout (165:165:165) (173:173:173)) - (IOPATH datab combout (196:196:196) (205:205:205)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|SYNTHESIZED_WIRE_10\~1) - (DELAY - (ABSOLUTE - (PORT dataa (108:108:108) (141:141:141)) - (PORT datab (341:341:341) (395:395:395)) - (PORT datac (181:181:181) (220:220:220)) - (PORT datad (439:439:439) (506:506:506)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|SYNTHESIZED_WIRE_10\~0) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (240:240:240)) - (PORT datab (348:348:348) (420:420:420)) - (PORT datac (346:346:346) (410:410:410)) - (PORT datad (344:344:344) (397:397:397)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|cy_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (213:213:213) (254:254:254)) - (PORT datab (128:128:128) (161:161:161)) - (PORT datac (96:96:96) (120:120:120)) - (PORT datad (94:94:94) (113:113:113)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf\~0) - (DELAY - (ABSOLUTE - (PORT dataa (383:383:383) (453:453:453)) - (PORT datab (646:646:646) (772:772:772)) - (PORT datac (468:468:468) (546:546:546)) - (PORT datad (360:360:360) (420:420:420)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (739:739:739) (860:860:860)) - (PORT datab (1112:1112:1112) (1276:1276:1276)) - (PORT datac (821:821:821) (956:956:956)) - (PORT datad (848:848:848) (984:984:984)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (620:620:620) (723:723:723)) - (PORT datab (334:334:334) (392:392:392)) - (PORT datac (447:447:447) (512:512:512)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf\~1) - (DELAY - (ABSOLUTE - (PORT dataa (111:111:111) (146:146:146)) - (PORT datab (101:101:101) (130:130:130)) - (PORT datad (423:423:423) (484:484:484)) - (IOPATH dataa combout (188:188:188) (179:179:179)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf) - (DELAY - (ABSOLUTE - (PORT clk (900:900:900) (905:905:905)) - (PORT d (37:37:37) (50:50:50)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~11) - (DELAY - (ABSOLUTE - (PORT dataa (631:631:631) (727:727:727)) - (PORT datac (306:306:306) (350:350:350)) - (PORT datad (911:911:911) (1051:1051:1051)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~12) - (DELAY - (ABSOLUTE - (PORT dataa (492:492:492) (567:567:567)) (PORT datab (102:102:102) (130:130:130)) - (PORT datac (1037:1037:1037) (1212:1212:1212)) - (PORT datad (302:302:302) (345:345:345)) + (PORT datac (88:88:88) (110:110:110)) + (PORT datad (447:447:447) (511:511:511)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -20560,32 +18689,16 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~13) + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~33) (DELAY (ABSOLUTE - (PORT dataa (200:200:200) (242:242:242)) - (PORT datab (1171:1171:1171) (1361:1361:1361)) - (PORT datac (739:739:739) (871:871:871)) - (PORT datad (497:497:497) (586:586:586)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|flags_hf) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (260:260:260)) - (PORT datab (314:314:314) (364:364:364)) - (PORT datac (654:654:654) (765:765:765)) - (PORT datad (449:449:449) (520:520:520)) - (IOPATH dataa combout (192:192:192) (184:184:184)) - (IOPATH datab combout (182:182:182) (188:188:188)) - (IOPATH datac combout (120:120:120) (124:124:124)) + (PORT dataa (178:178:178) (218:218:218)) + (PORT datab (530:530:530) (622:622:622)) + (PORT datac (90:90:90) (111:111:111)) + (PORT datad (338:338:338) (393:393:393)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -20595,9 +18708,23 @@ (INSTANCE z80_\|alu_control_\|alu_core_cf_in\~0) (DELAY (ABSOLUTE - (PORT dataa (302:302:302) (353:353:353)) - (PORT datab (319:319:319) (370:370:370)) - (PORT datad (288:288:288) (330:330:330)) + (PORT dataa (342:342:342) (395:395:395)) + (PORT datab (459:459:459) (532:532:532)) + (PORT datac (452:452:452) (520:520:520)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op1\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (603:603:603) (702:702:702)) + (PORT datab (500:500:500) (597:597:597)) + (PORT datad (306:306:306) (368:368:368)) (IOPATH dataa combout (166:166:166) (159:159:159)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -20609,10 +18736,10 @@ (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|result\~0) (DELAY (ABSOLUTE - (PORT dataa (350:350:350) (411:411:411)) - (PORT datab (104:104:104) (133:133:133)) - (PORT datac (428:428:428) (490:490:490)) - (PORT datad (107:107:107) (125:125:125)) + (PORT dataa (103:103:103) (133:133:133)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (572:572:572) (652:652:652)) + (PORT datad (94:94:94) (112:112:112)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -20622,49 +18749,1016 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~23) + (INSTANCE z80_\|alu_\|db_high\[0\]\~25) (DELAY (ABSOLUTE - (PORT dataa (934:934:934) (1091:1091:1091)) - (PORT datab (499:499:499) (574:574:574)) - (PORT datac (486:486:486) (558:558:558)) - (IOPATH dataa combout (188:188:188) (179:179:179)) + (PORT dataa (187:187:187) (223:223:223)) + (PORT datab (196:196:196) (236:236:236)) + (PORT datac (465:465:465) (535:535:535)) + (PORT datad (580:580:580) (659:659:659)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (337:337:337) (398:398:398)) + (PORT datab (360:360:360) (425:425:425)) + (PORT datac (489:489:489) (569:569:569)) + (PORT datad (345:345:345) (406:406:406)) + (IOPATH dataa combout (166:166:166) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[0\]\~7) + (DELAY + (ABSOLUTE + (PORT datab (492:492:492) (573:573:573)) + (PORT datac (91:91:91) (113:113:113)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[12\]) + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_high\[0\]) (DELAY (ABSOLUTE - (PORT datab (217:217:217) (260:260:260)) - (PORT datac (484:484:484) (559:559:559)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) + (PORT clk (923:923:923) (910:910:910)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (422:422:422) (450:450:450)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_10\~0) + (DELAY + (ABSOLUTE + (PORT dataa (213:213:213) (278:278:278)) + (PORT datab (207:207:207) (245:245:245)) + (PORT datad (207:207:207) (262:262:262)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (169:169:169) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|Q\[12\]\~feeder) + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_10\~1) (DELAY (ABSOLUTE - (PORT datad (162:162:162) (189:189:189)) + (PORT dataa (340:340:340) (391:391:391)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (570:570:570) (650:650:650)) + (PORT datad (94:94:94) (113:113:113)) + (IOPATH dataa combout (188:188:188) (179:179:179)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|cy_out\~0) + (DELAY + (ABSOLUTE + (PORT datab (763:763:763) (898:898:898)) + (PORT datac (601:601:601) (714:714:714)) + (PORT datad (94:94:94) (113:113:113)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_1) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (108:108:108) (138:138:138)) + (PORT datac (595:595:595) (679:679:679)) + (PORT datad (99:99:99) (121:121:121)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|result\~0) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (246:246:246)) + (PORT datab (176:176:176) (215:215:215)) + (PORT datac (88:88:88) (109:109:109)) + (PORT datad (100:100:100) (121:121:121)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (157:157:157) (207:207:207)) + (PORT datab (152:152:152) (195:195:195)) + (PORT datac (612:612:612) (703:703:703)) + (PORT datad (132:132:132) (163:163:163)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (132:132:132) (169:169:169)) + (PORT datab (476:476:476) (562:562:562)) + (PORT datac (310:310:310) (346:346:346)) + (PORT datad (299:299:299) (353:353:353)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[1\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (290:290:290) (344:344:344)) + (PORT datac (522:522:522) (624:624:624)) + (PORT datad (181:181:181) (211:211:211)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[1\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (457:457:457) (527:527:527)) + (PORT datab (340:340:340) (396:396:396)) + (PORT datad (607:607:607) (693:693:693)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (346:346:346) (406:406:406)) + (PORT datab (349:349:349) (409:409:409)) + (PORT datac (389:389:389) (456:456:456)) + (PORT datad (330:330:330) (382:382:382)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[1\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (482:482:482) (561:561:561)) + (PORT datab (374:374:374) (438:438:438)) + (PORT datac (176:176:176) (211:211:211)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[1\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (514:514:514) (599:599:599)) + (PORT datab (476:476:476) (553:553:553)) + (PORT datac (353:353:353) (407:407:407)) + (PORT datad (335:335:335) (390:390:390)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[1\]\~5) + (DELAY + (ABSOLUTE + (PORT datac (494:494:494) (571:571:571)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[12\]) + (INSTANCE z80_\|alu_\|op1_low\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (931:931:931) (916:916:916)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (409:409:409) (429:429:429)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|out\[6\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (142:142:142) (193:193:193)) + (PORT datac (128:128:128) (169:169:169)) + (PORT datad (140:140:140) (177:177:177)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|out\[6\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (497:497:497) (600:600:600)) + (PORT datab (485:485:485) (564:564:564)) + (PORT datac (498:498:498) (596:596:596)) + (PORT datad (476:476:476) (556:556:556)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|out\[6\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (137:137:137)) + (PORT datab (112:112:112) (144:144:144)) + (PORT datac (382:382:382) (466:466:466)) + (PORT datad (474:474:474) (564:564:564)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_12) + (DELAY + (ABSOLUTE + (PORT datac (367:367:367) (434:434:434)) + (PORT datad (465:465:465) (535:535:535)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_37\~0) + (DELAY + (ABSOLUTE + (PORT dataa (149:149:149) (202:202:202)) + (PORT datab (1233:1233:1233) (1403:1403:1403)) + (PORT datac (507:507:507) (591:591:591)) + (PORT datad (1262:1262:1262) (1449:1449:1449)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11\~2) + (DELAY + (ABSOLUTE + (PORT dataa (379:379:379) (461:461:461)) + (PORT datab (370:370:370) (442:442:442)) + (PORT datac (335:335:335) (395:395:395)) + (PORT datad (336:336:336) (391:391:391)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11\~0) + (DELAY + (ABSOLUTE + (PORT dataa (373:373:373) (447:447:447)) + (PORT datab (191:191:191) (231:231:231)) + (PORT datac (103:103:103) (125:125:125)) + (PORT datad (96:96:96) (115:115:115)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11\~1) + (DELAY + (ABSOLUTE + (PORT dataa (190:190:190) (232:232:232)) + (PORT datab (484:484:484) (563:563:563)) + (PORT datac (185:185:185) (220:220:220)) + (PORT datad (173:173:173) (205:205:205)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_37\~1) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (134:134:134)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (446:446:446) (519:519:519)) + (PORT datad (171:171:171) (202:202:202)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~7) + (DELAY + (ABSOLUTE + (PORT datac (852:852:852) (1001:1001:1001)) + (PORT datad (301:301:301) (349:349:349)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (659:659:659) (757:757:757)) + (PORT datab (483:483:483) (558:558:558)) + (PORT datac (165:165:165) (199:199:199)) + (PORT datad (331:331:331) (383:383:383)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_39) (DELAY (ABSOLUTE (PORT clk (909:909:909) (914:914:914)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (920:920:920) (905:905:905)) - (PORT ena (1106:1106:1106) (1248:1248:1248)) + (PORT ena (645:645:645) (697:697:697)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~51) + (DELAY + (ABSOLUTE + (PORT dataa (773:773:773) (878:878:878)) + (PORT datab (495:495:495) (578:578:578)) + (PORT datac (463:463:463) (538:538:538)) + (PORT datad (480:480:480) (546:546:546)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_oe\~2) + (DELAY + (ABSOLUTE + (PORT dataa (294:294:294) (348:348:348)) + (PORT datab (480:480:480) (560:560:560)) + (PORT datac (553:553:553) (634:634:634)) + (PORT datad (638:638:638) (731:731:731)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~7) + (DELAY + (ABSOLUTE + (PORT dataa (472:472:472) (548:548:548)) + (PORT datab (731:731:731) (869:869:869)) + (PORT datac (435:435:435) (491:491:491)) + (PORT datad (282:282:282) (322:322:322)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[6\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (473:473:473) (554:554:554)) + (PORT datab (389:389:389) (468:468:468)) + (PORT datac (447:447:447) (513:513:513)) + (PORT datad (281:281:281) (325:325:325)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[6\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (628:628:628) (715:715:715)) + (PORT datab (111:111:111) (143:143:143)) + (PORT datac (99:99:99) (125:125:125)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~8) + (DELAY + (ABSOLUTE + (PORT dataa (441:441:441) (510:510:510)) + (PORT datab (623:623:623) (713:713:713)) + (PORT datac (345:345:345) (410:410:410)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[6\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (468:468:468) (544:544:544)) + (PORT datab (471:471:471) (555:555:555)) + (PORT datac (335:335:335) (404:404:404)) + (PORT datad (589:589:589) (662:662:662)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[6\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (117:117:117) (147:147:147)) + (PORT datab (213:213:213) (252:252:252)) + (PORT datac (192:192:192) (231:231:231)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[6\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (135:135:135)) + (PORT datab (102:102:102) (131:131:131)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (189:189:189) (221:221:221)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[6\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (331:331:331) (402:402:402)) + (PORT datab (499:499:499) (573:573:573)) + (PORT datac (308:308:308) (360:360:360)) + (PORT datad (362:362:362) (426:426:426)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[6\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (389:389:389) (475:475:475)) + (PORT datab (140:140:140) (182:182:182)) + (PORT datac (455:455:455) (521:521:521)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (909:909:909)) + (PORT asdata (760:760:760) (842:842:842)) + (PORT ena (619:619:619) (671:671:671)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~80) + (DELAY + (ABSOLUTE + (PORT dataa (639:639:639) (752:752:752)) + (PORT datab (616:616:616) (718:718:718)) + (PORT datad (204:204:204) (251:251:251)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (905:905:905) (910:910:910)) + (PORT asdata (669:669:669) (749:749:749)) + (PORT ena (649:649:649) (707:707:707)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (905:905:905) (910:910:910)) + (PORT asdata (673:673:673) (754:754:754)) + (PORT ena (604:604:604) (647:647:647)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~79) + (DELAY + (ABSOLUTE + (PORT dataa (366:366:366) (436:436:436)) + (PORT datab (145:145:145) (184:184:184)) + (PORT datad (119:119:119) (156:156:156)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) + (PORT asdata (761:761:761) (843:843:843)) + (PORT ena (648:648:648) (700:700:700)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (582:582:582) (666:666:666)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (757:757:757) (811:811:811)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~78) + (DELAY + (ABSOLUTE + (PORT dataa (384:384:384) (456:456:456)) + (PORT datab (343:343:343) (402:402:402)) + (PORT datad (117:117:117) (153:153:153)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~82) + (DELAY + (ABSOLUTE + (PORT dataa (458:458:458) (527:527:527)) + (PORT datab (294:294:294) (338:338:338)) + (PORT datac (306:306:306) (345:345:345)) + (PORT datad (182:182:182) (212:212:212)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) + (PORT asdata (624:624:624) (693:693:693)) + (PORT ena (422:422:422) (449:449:449)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|db\[6\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (803:803:803) (921:921:921)) + (PORT datab (651:651:651) (745:745:745)) + (PORT datad (449:449:449) (507:507:507)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (465:465:465) (510:510:510)) + (PORT ena (662:662:662) (730:730:730)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) + (PORT asdata (483:483:483) (535:535:535)) + (PORT ena (501:501:501) (541:541:541)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (305:305:305) (349:349:349)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (621:621:621) (666:666:666)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~76) + (DELAY + (ABSOLUTE + (PORT dataa (353:353:353) (429:429:429)) + (PORT datab (371:371:371) (435:435:435)) + (PORT datad (117:117:117) (153:153:153)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~77) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (407:407:407)) + (PORT datab (325:325:325) (386:386:386)) + (PORT datad (172:172:172) (203:203:203)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~83) + (DELAY + (ABSOLUTE + (PORT dataa (130:130:130) (181:181:181)) + (PORT datab (107:107:107) (138:138:138)) + (PORT datac (294:294:294) (339:339:339)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~84) + (DELAY + (ABSOLUTE + (PORT dataa (470:470:470) (538:538:538)) + (PORT datab (101:101:101) (129:129:129)) + (PORT datac (577:577:577) (663:663:663)) + (PORT datad (322:322:322) (376:376:376)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (909:909:909)) + (PORT asdata (349:349:349) (372:372:372)) + (PORT ena (649:649:649) (706:706:706)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (433:433:433)) + (PORT datab (472:472:472) (547:547:547)) + (PORT datad (342:342:342) (400:400:400)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (909:909:909)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (672:672:672) (745:745:745)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (177:177:177) (221:221:221)) + (PORT datab (130:130:130) (178:178:178)) + (PORT datad (557:557:557) (638:638:638)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[13\]) + (DELAY + (ABSOLUTE + (PORT dataa (330:330:330) (391:391:391)) + (PORT datad (584:584:584) (656:656:656)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (904:904:904) (891:891:891)) + (PORT ena (1014:1014:1014) (1102:1102:1102)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -20679,180 +19773,25 @@ (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|d0_out) (DELAY (ABSOLUTE - (PORT dataa (323:323:323) (376:376:376)) - (PORT datab (479:479:479) (565:565:565)) - (PORT datac (132:132:132) (179:179:179)) - (PORT datad (309:309:309) (369:369:369)) + (PORT dataa (225:225:225) (284:284:284)) + (PORT datab (112:112:112) (144:144:144)) + (PORT datac (359:359:359) (430:430:430)) + (PORT datad (214:214:214) (265:265:265)) (IOPATH dataa combout (188:188:188) (203:203:203)) - (IOPATH datab combout (190:190:190) (205:205:205)) + (IOPATH datab combout (190:190:190) (177:177:177)) (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (679:679:679) (747:747:747)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (923:923:923)) - (PORT asdata (694:694:694) (776:776:776)) - (PORT ena (480:480:480) (509:509:509)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (215:215:215) (263:263:263)) - (PORT datab (217:217:217) (260:260:260)) - (PORT datad (102:102:102) (118:118:118)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (360:360:360) (428:428:428)) - (PORT datac (117:117:117) (158:158:158)) - (PORT datad (441:441:441) (509:509:509)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (241:241:241)) - (PORT datab (452:452:452) (526:526:526)) - (PORT datac (369:369:369) (438:438:438)) - (PORT datad (91:91:91) (108:108:108)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (911:911:911)) - (PORT asdata (1107:1107:1107) (1234:1234:1234)) - (PORT ena (405:405:405) (422:422:422)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~62) - (DELAY - (ABSOLUTE - (PORT dataa (210:210:210) (248:248:248)) - (PORT datab (648:648:648) (750:750:750)) - (PORT datad (384:384:384) (437:437:437)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (923:923:923)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (776:776:776) (851:851:851)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (911:911:911)) - (PORT asdata (1105:1105:1105) (1232:1232:1232)) - (PORT ena (663:663:663) (731:731:731)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~63) - (DELAY - (ABSOLUTE - (PORT dataa (381:381:381) (461:461:461)) - (PORT datab (470:470:470) (545:545:545)) - (PORT datad (480:480:480) (550:550:550)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[4\]) (DELAY (ABSOLUTE - (PORT clk (907:907:907) (912:912:912)) - (PORT asdata (775:775:775) (861:861:861)) - (PORT ena (622:622:622) (680:680:680)) + (PORT clk (905:905:905) (910:910:910)) + (PORT asdata (652:652:652) (723:723:723)) + (PORT ena (649:649:649) (707:707:707)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -20866,9 +19805,9 @@ (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[4\]) (DELAY (ABSOLUTE - (PORT clk (907:907:907) (912:912:912)) - (PORT asdata (774:774:774) (861:861:861)) - (PORT ena (405:405:405) (422:422:422)) + (PORT clk (905:905:905) (910:910:910)) + (PORT asdata (651:651:651) (722:722:722)) + (PORT ena (604:604:604) (647:647:647)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -20882,128 +19821,8 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~61) (DELAY (ABSOLUTE - (PORT dataa (488:488:488) (578:578:578)) - (PORT datab (130:130:130) (164:164:164)) - (PORT datad (117:117:117) (152:152:152)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[4\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (764:764:764) (865:865:865)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (627:627:627) (675:675:675)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (933:933:933) (1030:1030:1030)) - (PORT ena (670:670:670) (742:742:742)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~60) - (DELAY - (ABSOLUTE - (PORT dataa (204:204:204) (262:262:262)) - (PORT datab (892:892:892) (1040:1040:1040)) - (PORT datad (642:642:642) (747:747:747)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~64) - (DELAY - (ABSOLUTE - (PORT dataa (105:105:105) (136:136:136)) - (PORT datab (101:101:101) (129:129:129)) - (PORT datac (422:422:422) (489:489:489)) - (PORT datad (328:328:328) (384:384:384)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (1062:1062:1062) (1195:1195:1195)) - (PORT ena (753:753:753) (845:845:845)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (1061:1061:1061) (1195:1195:1195)) - (PORT ena (759:759:759) (842:842:842)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~59) - (DELAY - (ABSOLUTE - (PORT dataa (513:513:513) (629:629:629)) - (PORT datab (511:511:511) (618:618:618)) + (PORT dataa (367:367:367) (437:437:437)) + (PORT datab (147:147:147) (185:185:185)) (PORT datad (115:115:115) (152:152:152)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) @@ -21014,12 +19833,210 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[4\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[4\]) (DELAY (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (1044:1044:1044) (1156:1156:1156)) - (PORT ena (515:515:515) (556:556:556)) + (PORT clk (904:904:904) (909:909:909)) + (PORT asdata (1040:1040:1040) (1175:1175:1175)) + (PORT ena (619:619:619) (671:671:671)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~62) + (DELAY + (ABSOLUTE + (PORT dataa (640:640:640) (754:754:754)) + (PORT datab (491:491:491) (565:565:565)) + (PORT datad (208:208:208) (255:255:255)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) + (PORT asdata (612:612:612) (679:679:679)) + (PORT ena (648:648:648) (700:700:700)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (328:328:328) (385:385:385)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (757:757:757) (811:811:811)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~60) + (DELAY + (ABSOLUTE + (PORT dataa (382:382:382) (454:454:454)) + (PORT datab (348:348:348) (408:408:408)) + (PORT datad (115:115:115) (152:152:152)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (909:909:909)) + (PORT asdata (936:936:936) (1041:1041:1041)) + (PORT ena (655:655:655) (714:714:714)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (909:909:909)) + (PORT asdata (936:936:936) (1041:1041:1041)) + (PORT ena (800:800:800) (878:878:878)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~63) + (DELAY + (ABSOLUTE + (PORT dataa (389:389:389) (465:465:465)) + (PORT datab (129:129:129) (177:177:177)) + (PORT datad (381:381:381) (448:448:448)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~64) + (DELAY + (ABSOLUTE + (PORT dataa (299:299:299) (344:344:344)) + (PORT datab (320:320:320) (377:377:377)) + (PORT datac (324:324:324) (381:381:381)) + (PORT datad (160:160:160) (187:187:187)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (406:406:406) (423:423:423)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) + (PORT asdata (726:726:726) (820:820:820)) + (PORT ena (422:422:422) (449:449:449)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|db\[4\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (805:805:805) (923:923:923)) + (PORT datab (650:650:650) (744:744:744)) + (PORT datad (447:447:447) (505:505:505)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (473:473:473) (523:523:523)) + (PORT ena (662:662:662) (730:730:730)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -21033,9 +20050,25 @@ (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[4\]) (DELAY (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (1043:1043:1043) (1155:1155:1155)) - (PORT ena (506:506:506) (537:537:537)) + (PORT clk (902:902:902) (907:907:907)) + (PORT asdata (350:350:350) (383:383:383)) + (PORT ena (621:621:621) (666:666:666)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) + (PORT asdata (353:353:353) (386:386:386)) + (PORT ena (501:501:501) (541:541:541)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -21049,42 +20082,26 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~58) (DELAY (ABSOLUTE - (PORT dataa (257:257:257) (310:310:310)) - (PORT datab (266:266:266) (318:318:318)) - (PORT datad (117:117:117) (154:154:154)) + (PORT dataa (354:354:354) (430:430:430)) + (PORT datab (131:131:131) (179:179:179)) + (PORT datad (333:333:333) (384:384:384)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (1059:1059:1059) (1190:1190:1190)) - (PORT ena (408:408:408) (429:429:429)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[4\]\~19) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~59) (DELAY (ABSOLUTE - (PORT dataa (507:507:507) (606:606:606)) - (PORT datab (669:669:669) (791:791:791)) - (PORT datad (485:485:485) (564:564:564)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (PORT dataa (342:342:342) (406:406:406)) + (PORT datab (334:334:334) (393:393:393)) + (PORT datad (173:173:173) (205:205:205)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -21095,12 +20112,12 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~65) (DELAY (ABSOLUTE - (PORT dataa (353:353:353) (415:415:415)) - (PORT datab (168:168:168) (205:205:205)) - (PORT datac (310:310:310) (357:357:357)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (108:108:108) (139:139:139)) + (PORT datac (118:118:118) (159:159:159)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -21111,10 +20128,10 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~66) (DELAY (ABSOLUTE - (PORT dataa (508:508:508) (606:606:606)) - (PORT datab (479:479:479) (577:577:577)) - (PORT datac (439:439:439) (509:509:509)) - (PORT datad (730:730:730) (839:839:839)) + (PORT dataa (470:470:470) (539:539:539)) + (PORT datab (483:483:483) (562:562:562)) + (PORT datac (90:90:90) (112:112:112)) + (PORT datad (323:323:323) (377:377:377)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -21123,153 +20140,44 @@ ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[4\]\~16) + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[4\]) (DELAY (ABSOLUTE - (PORT dataa (715:715:715) (846:846:846)) - (PORT datab (537:537:537) (630:630:630)) - (PORT datac (464:464:464) (539:539:539)) - (PORT datad (804:804:804) (906:906:906)) + (PORT clk (904:904:904) (909:909:909)) + (PORT asdata (347:347:347) (375:375:375)) + (PORT ena (649:649:649) (706:706:706)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (433:433:433)) + (PORT datab (675:675:675) (786:786:786)) + (PORT datad (344:344:344) (402:402:402)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[7\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (704:704:704) (830:830:830)) - (PORT datab (666:666:666) (773:773:773)) - (PORT datac (507:507:507) (583:583:583)) - (PORT datad (522:522:522) (608:608:608)) - (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[4\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (108:108:108) (140:140:140)) - (PORT datab (129:129:129) (168:168:168)) - (PORT datac (562:562:562) (636:636:636)) - (PORT datad (527:527:527) (614:614:614)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~3) - (DELAY - (ABSOLUTE - (PORT dataa (718:718:718) (845:845:845)) - (PORT datab (522:522:522) (615:615:615)) - (PORT datac (192:192:192) (229:229:229)) - (PORT datad (665:665:665) (793:793:793)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~5) - (DELAY - (ABSOLUTE - (PORT dataa (648:648:648) (781:781:781)) - (PORT datab (1031:1031:1031) (1199:1199:1199)) - (PORT datac (487:487:487) (576:576:576)) - (PORT datad (858:858:858) (1004:1004:1004)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~4) - (DELAY - (ABSOLUTE - (PORT dataa (519:519:519) (610:610:610)) - (PORT datab (346:346:346) (403:403:403)) - (PORT datac (799:799:799) (940:940:940)) - (PORT datad (320:320:320) (371:371:371)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (135:135:135)) - (PORT datac (504:504:504) (590:590:590)) - (PORT datad (127:127:127) (156:156:156)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (651:651:651) (756:756:756)) - (PORT datab (158:158:158) (203:203:203)) - (PORT datac (141:141:141) (181:181:181)) - (PORT datad (131:131:131) (162:162:162)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[0\]) - (DELAY - (ABSOLUTE - (PORT datab (185:185:185) (226:226:226)) - (PORT datac (513:513:513) (610:610:610)) - (PORT datad (371:371:371) (441:441:441)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_high\[0\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[4\]) (DELAY (ABSOLUTE - (PORT clk (916:916:916) (901:901:901)) + (PORT clk (904:904:904) (909:909:909)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (422:422:422) (450:450:450)) + (PORT ena (672:672:672) (745:745:745)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -21280,31 +20188,75 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~22) + (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~17) (DELAY (ABSOLUTE - (PORT dataa (343:343:343) (407:407:407)) - (PORT datab (656:656:656) (758:758:758)) - (PORT datac (341:341:341) (416:416:416)) - (PORT datad (370:370:370) (437:437:437)) + (PORT dataa (103:103:103) (133:133:133)) + (PORT datab (132:132:132) (181:181:181)) + (PORT datad (559:559:559) (641:641:641)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~25) + (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~18) (DELAY (ABSOLUTE - (PORT dataa (318:318:318) (379:379:379)) - (PORT datab (168:168:168) (204:204:204)) - (PORT datac (632:632:632) (738:738:738)) - (PORT datad (281:281:281) (324:324:324)) + (PORT dataa (344:344:344) (406:406:406)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (306:306:306) (355:355:355)) + (PORT datad (745:745:745) (839:839:839)) (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[12\]) + (DELAY + (ABSOLUTE + (PORT dataa (354:354:354) (418:418:418)) + (PORT datac (312:312:312) (364:364:364)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (904:904:904) (891:891:891)) + (PORT ena (1014:1014:1014) (1102:1102:1102)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|SYNTHESIZED_WIRE_0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (225:225:225) (284:284:284)) + (PORT datab (112:112:112) (144:144:144)) + (PORT datac (360:360:360) (431:431:431)) + (PORT datad (214:214:214) (265:265:265)) + (IOPATH dataa combout (158:158:158) (173:173:173)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -21312,15 +20264,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~26) + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[14\]) (DELAY (ABSOLUTE - (PORT dataa (336:336:336) (396:396:396)) - (PORT datab (546:546:546) (645:645:645)) - (PORT datac (90:90:90) (112:112:112)) - (PORT datad (119:119:119) (149:149:149)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) + (PORT dataa (226:226:226) (286:286:286)) + (PORT datab (461:461:461) (533:533:533)) + (PORT datac (130:130:130) (179:179:179)) + (PORT datad (176:176:176) (210:210:210)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH datab combout (166:166:166) (174:174:174)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (757:757:757) (865:865:865)) + (PORT datab (323:323:323) (374:374:374)) + (PORT datac (89:89:89) (110:110:110)) + (PORT datad (334:334:334) (386:386:386)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -21328,55 +20296,27 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[0\]\~7) + (INSTANCE z80_\|address_latch_\|abusz\[14\]) (DELAY (ABSOLUTE - (PORT dataa (317:317:317) (372:372:372)) - (PORT datab (529:529:529) (627:627:627)) - (PORT datac (478:478:478) (551:551:551)) - (PORT datad (175:175:175) (205:205:205)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT datac (312:312:312) (364:364:364)) + (PORT datad (335:335:335) (385:385:385)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[0\]\~8) - (DELAY - (ABSOLUTE - (PORT datac (91:91:91) (113:113:113)) - (PORT datad (369:369:369) (439:439:439)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|ena) - (DELAY - (ABSOLUTE - (PORT dataa (502:502:502) (585:585:585)) - (PORT datab (394:394:394) (473:473:473)) - (PORT datac (511:511:511) (608:608:608)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_low\[0\]) + (INSTANCE z80_\|address_latch_\|Q\[14\]) (DELAY (ABSOLUTE - (PORT clk (916:916:916) (901:901:901)) + (PORT clk (903:903:903) (908:908:908)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (405:405:405) (422:422:422)) + (PORT clrn (904:904:904) (891:891:891)) + (PORT ena (1014:1014:1014) (1102:1102:1102)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) ) (TIMINGCHECK @@ -21386,55 +20326,27 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op1\[0\]\~1) + (INSTANCE z80_\|address_latch_\|abusz\[15\]) (DELAY (ABSOLUTE - (PORT dataa (349:349:349) (409:409:409)) - (PORT datab (342:342:342) (411:411:411)) - (PORT datac (331:331:331) (386:386:386)) - (IOPATH dataa combout (188:188:188) (184:184:184)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[0\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (329:329:329) (379:379:379)) - (PORT datab (515:515:515) (607:607:607)) - (PORT datac (609:609:609) (729:729:729)) - (PORT datad (307:307:307) (355:355:355)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT dataa (331:331:331) (391:391:391)) + (PORT datad (325:325:325) (379:379:379)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[0\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (144:144:144) (192:192:192)) - (PORT datac (90:90:90) (112:112:112)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_low\[0\]) + (INSTANCE z80_\|address_latch_\|Q\[15\]) (DELAY (ABSOLUTE - (PORT clk (915:915:915) (900:900:900)) + (PORT clk (903:903:903) (908:908:908)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (420:420:420) (448:448:448)) + (PORT clrn (904:904:904) (891:891:891)) + (PORT ena (1014:1014:1014) (1102:1102:1102)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) ) (TIMINGCHECK @@ -21444,13 +20356,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_10\~0) + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[15\]\~0) (DELAY (ABSOLUTE - (PORT dataa (235:235:235) (302:302:302)) - (PORT datac (341:341:341) (416:416:416)) - (PORT datad (355:355:355) (421:421:421)) - (IOPATH dataa combout (170:170:170) (163:163:163)) + (PORT dataa (130:130:130) (172:172:172)) + (PORT datab (120:120:120) (156:156:156)) + (PORT datac (322:322:322) (373:373:373)) + (PORT datad (372:372:372) (446:446:446)) + (IOPATH dataa combout (172:172:172) (163:163:163)) + (IOPATH datab combout (169:169:169) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -21458,190 +20372,28 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_10\~1) + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[15\]\~1) (DELAY (ABSOLUTE - (PORT dataa (300:300:300) (345:345:345)) - (PORT datab (451:451:451) (516:516:516)) - (PORT datac (426:426:426) (488:488:488)) - (PORT datad (106:106:106) (125:125:125)) - (IOPATH dataa combout (188:188:188) (179:179:179)) - (IOPATH datab combout (188:188:188) (177:177:177)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|cy_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (364:364:364) (429:429:429)) - (PORT datab (108:108:108) (138:138:138)) - (PORT datac (109:109:109) (133:133:133)) - (PORT datad (438:438:438) (502:502:502)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op1\[1\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (349:349:349) (409:409:409)) - (PORT datab (345:345:345) (412:412:412)) - (PORT datad (346:346:346) (404:404:404)) - (IOPATH dataa combout (172:172:172) (165:165:165)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_10\~0) - (DELAY - (ABSOLUTE - (PORT dataa (360:360:360) (423:423:423)) - (PORT datab (462:462:462) (533:533:533)) - (PORT datac (96:96:96) (120:120:120)) - (PORT datad (267:267:267) (304:304:304)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (107:107:107) (141:141:141)) - (PORT datab (111:111:111) (144:144:144)) - (PORT datac (108:108:108) (132:132:132)) - (PORT datad (97:97:97) (116:116:116)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op1\[2\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (343:343:343) (414:414:414)) - (PORT datab (358:358:358) (421:421:421)) - (PORT datad (326:326:326) (386:386:386)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (167:167:167) (158:158:158)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_10\~1) - (DELAY - (ABSOLUTE - (PORT dataa (194:194:194) (233:233:233)) - (PORT datab (341:341:341) (396:396:396)) - (PORT datac (95:95:95) (120:120:120)) - (PORT datad (439:439:439) (506:506:506)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|cy_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (196:196:196) (237:237:237)) - (PORT datab (203:203:203) (245:245:245)) - (PORT datac (93:93:93) (117:117:117)) - (PORT datad (186:186:186) (220:220:220)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~5) - (DELAY - (ABSOLUTE - (PORT datac (960:960:960) (1080:1080:1080)) - (PORT datad (442:442:442) (507:507:507)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|SYNTHESIZED_WIRE_1) - (DELAY - (ABSOLUTE - (PORT dataa (192:192:192) (234:234:234)) - (PORT datab (123:123:123) (155:155:155)) - (PORT datac (92:92:92) (116:116:116)) - (PORT datad (94:94:94) (113:113:113)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|result\~0) - (DELAY - (ABSOLUTE - (PORT dataa (108:108:108) (142:142:142)) - (PORT datab (125:125:125) (158:158:158)) - (PORT datac (179:179:179) (218:218:218)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[7\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (614:614:614) (710:710:710)) + (PORT dataa (151:151:151) (209:209:209)) + (PORT datab (460:460:460) (531:531:531)) + (PORT datac (195:195:195) (247:247:247)) + (PORT datad (319:319:319) (372:372:372)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH datab combout (166:166:166) (174:174:174)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[7\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) + (PORT clk (904:904:904) (909:909:909)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (627:627:627) (675:675:675)) + (PORT ena (672:672:672) (745:745:745)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -21650,327 +20402,14 @@ (HOLD ena (posedge clk) (84:84:84)) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (803:803:803) (911:911:911)) - (PORT ena (670:670:670) (742:742:742)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~69) - (DELAY - (ABSOLUTE - (PORT dataa (130:130:130) (181:181:181)) - (PORT datab (893:893:893) (1041:1041:1041)) - (PORT datad (643:643:643) (748:748:748)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (907:907:907) (912:912:912)) - (PORT asdata (920:920:920) (1042:1042:1042)) - (PORT ena (622:622:622) (680:680:680)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (907:907:907) (912:912:912)) - (PORT asdata (918:918:918) (1040:1040:1040)) - (PORT ena (405:405:405) (422:422:422)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~70) - (DELAY - (ABSOLUTE - (PORT dataa (484:484:484) (573:573:573)) - (PORT datab (130:130:130) (163:163:163)) - (PORT datad (119:119:119) (156:156:156)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (923:923:923)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (776:776:776) (851:851:851)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (911:911:911)) - (PORT asdata (798:798:798) (895:895:895)) - (PORT ena (663:663:663) (731:731:731)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~72) - (DELAY - (ABSOLUTE - (PORT dataa (386:386:386) (470:470:470)) - (PORT datab (470:470:470) (545:545:545)) - (PORT datad (480:480:480) (550:550:550)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (911:911:911)) - (PORT asdata (798:798:798) (895:895:895)) - (PORT ena (405:405:405) (422:422:422)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~71) - (DELAY - (ABSOLUTE - (PORT dataa (761:761:761) (870:870:870)) - (PORT datab (650:650:650) (752:752:752)) - (PORT datad (129:129:129) (157:157:157)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~73) - (DELAY - (ABSOLUTE - (PORT dataa (439:439:439) (513:513:513)) - (PORT datab (600:600:600) (712:712:712)) - (PORT datac (91:91:91) (113:113:113)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (803:803:803) (913:913:913)) - (PORT ena (515:515:515) (556:556:556)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (803:803:803) (913:913:913)) - (PORT ena (506:506:506) (537:537:537)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~67) - (DELAY - (ABSOLUTE - (PORT dataa (257:257:257) (311:311:311)) - (PORT datab (266:266:266) (317:317:317)) - (PORT datad (117:117:117) (153:153:153)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (765:765:765) (858:858:858)) - (PORT ena (408:408:408) (429:429:429)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[7\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (508:508:508) (607:607:607)) - (PORT datab (669:669:669) (791:791:791)) - (PORT datad (483:483:483) (561:561:561)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (664:664:664) (748:748:748)) - (PORT ena (753:753:753) (845:845:845)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (663:663:663) (747:747:747)) - (PORT ena (759:759:759) (842:842:842)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~68) - (DELAY - (ABSOLUTE - (PORT dataa (506:506:506) (619:619:619)) - (PORT datab (515:515:515) (623:623:623)) - (PORT datad (117:117:117) (154:154:154)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~74) - (DELAY - (ABSOLUTE - (PORT dataa (194:194:194) (234:234:234)) - (PORT datab (339:339:339) (406:406:406)) - (PORT datac (342:342:342) (405:405:405)) - (PORT datad (462:462:462) (547:547:547)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (915:915:915) (923:923:923)) - (PORT asdata (632:632:632) (700:700:700)) - (PORT ena (480:480:480) (509:509:509)) + (PORT clk (904:904:904) (909:909:909)) + (PORT asdata (458:458:458) (499:499:499)) + (PORT ena (649:649:649) (706:706:706)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -21984,1094 +20423,26 @@ (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~19) (DELAY (ABSOLUTE - (PORT dataa (117:117:117) (148:148:148)) - (PORT datab (210:210:210) (253:253:253)) - (PORT datad (206:206:206) (243:243:243)) - (IOPATH dataa combout (166:166:166) (163:163:163)) + (PORT dataa (362:362:362) (433:433:433)) + (PORT datab (360:360:360) (423:423:423)) + (PORT datad (754:754:754) (857:857:857)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (679:679:679) (747:747:747)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~20) (DELAY (ABSOLUTE - (PORT dataa (451:451:451) (544:544:544)) - (PORT datac (115:115:115) (156:156:156)) - (PORT datad (349:349:349) (406:406:406)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|SYNTHESIZED_WIRE_0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (321:321:321) (374:374:374)) - (PORT datab (486:486:486) (573:573:573)) - (PORT datac (129:129:129) (176:176:176)) - (PORT datad (306:306:306) (366:366:366)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (190:190:190) (181:181:181)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|d1_out) - (DELAY - (ABSOLUTE - (PORT datac (144:144:144) (192:192:192)) - (PORT datad (98:98:98) (120:120:120)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (907:907:907) (912:912:912)) - (PORT asdata (796:796:796) (899:899:899)) - (PORT ena (673:673:673) (745:745:745)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (923:923:923)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (776:776:776) (851:851:851)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~54) - (DELAY - (ABSOLUTE - (PORT dataa (592:592:592) (685:685:685)) - (PORT datab (478:478:478) (553:553:553)) - (PORT datad (361:361:361) (437:437:437)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (911:911:911)) - (PORT asdata (1146:1146:1146) (1300:1300:1300)) - (PORT ena (405:405:405) (422:422:422)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~53) - (DELAY - (ABSOLUTE - (PORT dataa (913:913:913) (1038:1038:1038)) - (PORT datab (647:647:647) (748:748:748)) - (PORT datad (121:121:121) (149:149:149)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[5\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (628:628:628) (736:736:736)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (627:627:627) (675:675:675)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (795:795:795) (894:894:894)) - (PORT ena (670:670:670) (742:742:742)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~51) - (DELAY - (ABSOLUTE - (PORT dataa (198:198:198) (259:259:259)) - (PORT datab (896:896:896) (1045:1045:1045)) - (PORT datad (644:644:644) (749:749:749)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (907:907:907) (912:912:912)) - (PORT asdata (1005:1005:1005) (1137:1137:1137)) - (PORT ena (405:405:405) (422:422:422)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (907:907:907) (912:912:912)) - (PORT asdata (796:796:796) (899:899:899)) - (PORT ena (582:582:582) (618:618:618)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~52) - (DELAY - (ABSOLUTE - (PORT dataa (214:214:214) (270:270:270)) - (PORT datab (477:477:477) (557:557:557)) - (PORT datad (191:191:191) (219:219:219)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~55) - (DELAY - (ABSOLUTE - (PORT dataa (105:105:105) (136:136:136)) - (PORT datab (172:172:172) (209:209:209)) - (PORT datac (421:421:421) (477:477:477)) - (PORT datad (93:93:93) (111:111:111)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (805:805:805) (908:908:908)) - (PORT ena (506:506:506) (537:537:537)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (805:805:805) (908:908:908)) - (PORT ena (515:515:515) (556:556:556)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~49) - (DELAY - (ABSOLUTE - (PORT dataa (255:255:255) (308:308:308)) - (PORT datab (129:129:129) (176:176:176)) - (PORT datad (249:249:249) (295:295:295)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (958:958:958) (1085:1085:1085)) - (PORT ena (759:759:759) (842:842:842)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (959:959:959) (1086:1086:1086)) - (PORT ena (753:753:753) (845:845:845)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~50) - (DELAY - (ABSOLUTE - (PORT dataa (512:512:512) (627:627:627)) - (PORT datab (132:132:132) (180:180:180)) - (PORT datad (497:497:497) (594:594:594)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (979:979:979) (1116:1116:1116)) - (PORT ena (408:408:408) (429:429:429)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[5\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (507:507:507) (606:606:606)) - (PORT datab (669:669:669) (791:791:791)) - (PORT datad (486:486:486) (565:565:565)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~56) - (DELAY - (ABSOLUTE - (PORT dataa (356:356:356) (417:417:417)) - (PORT datab (473:473:473) (555:555:555)) - (PORT datac (323:323:323) (380:380:380)) - (PORT datad (438:438:438) (504:504:504)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~57) - (DELAY - (ABSOLUTE - (PORT dataa (509:509:509) (607:607:607)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (463:463:463) (547:547:547)) - (PORT datad (729:729:729) (839:839:839)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (923:923:923)) - (PORT asdata (641:641:641) (723:723:723)) - (PORT ena (480:480:480) (509:509:509)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (214:214:214) (262:262:262)) - (PORT datab (113:113:113) (141:141:141)) - (PORT datad (204:204:204) (240:240:240)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (679:679:679) (747:747:747)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (360:360:360) (428:428:428)) - (PORT datab (202:202:202) (245:245:245)) - (PORT datac (116:116:116) (156:156:156)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (288:288:288) (336:336:336)) - (PORT datab (459:459:459) (533:533:533)) - (PORT datac (372:372:372) (441:441:441)) - (PORT datad (90:90:90) (107:107:107)) + (PORT dataa (131:131:131) (182:182:182)) + (PORT datab (572:572:572) (663:663:663)) + (PORT datad (90:90:90) (108:108:108)) (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[13\]) - (DELAY - (ABSOLUTE - (PORT datab (204:204:204) (251:251:251)) - (PORT datac (486:486:486) (561:561:561)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|Q\[13\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (172:172:172) (202:202:202)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[13\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (920:920:920) (905:905:905)) - (PORT ena (1106:1106:1106) (1248:1248:1248)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_53\~0) - (DELAY - (ABSOLUTE - (PORT datac (144:144:144) (193:193:193)) - (PORT datad (467:467:467) (548:548:548)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[15\]) - (DELAY - (ABSOLUTE - (PORT datac (183:183:183) (215:215:215)) - (PORT datad (471:471:471) (541:541:541)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[15\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (920:920:920) (905:905:905)) - (PORT ena (1106:1106:1106) (1248:1248:1248)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[14\]) - (DELAY - (ABSOLUTE - (PORT dataa (157:157:157) (212:212:212)) - (PORT datab (113:113:113) (146:146:146)) - (PORT datac (134:134:134) (178:178:178)) - (PORT datad (463:463:463) (544:544:544)) - (IOPATH dataa combout (188:188:188) (203:203:203)) - (IOPATH datab combout (190:190:190) (205:205:205)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (679:679:679) (747:747:747)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (1314:1314:1314) (1518:1518:1518)) - (PORT ena (515:515:515) (556:556:556)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (1314:1314:1314) (1517:1517:1517)) - (PORT ena (506:506:506) (537:537:537)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~76) - (DELAY - (ABSOLUTE - (PORT dataa (255:255:255) (309:309:309)) - (PORT datab (268:268:268) (320:320:320)) - (PORT datad (117:117:117) (154:154:154)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (911:911:911)) - (PORT asdata (1077:1077:1077) (1239:1239:1239)) - (PORT ena (405:405:405) (422:422:422)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~80) - (DELAY - (ABSOLUTE - (PORT dataa (441:441:441) (511:511:511)) - (PORT datab (651:651:651) (753:753:753)) - (PORT datad (130:130:130) (158:158:158)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (907:907:907) (912:912:912)) - (PORT asdata (676:676:676) (761:761:761)) - (PORT ena (405:405:405) (422:422:422)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (907:907:907) (912:912:912)) - (PORT asdata (1217:1217:1217) (1390:1390:1390)) - (PORT ena (582:582:582) (618:618:618)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~79) - (DELAY - (ABSOLUTE - (PORT dataa (203:203:203) (261:261:261)) - (PORT datab (478:478:478) (558:558:558)) - (PORT datad (192:192:192) (220:220:220)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (808:808:808) (912:912:912)) - (PORT ena (670:670:670) (742:742:742)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (808:808:808) (913:913:913)) - (PORT ena (627:627:627) (675:675:675)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~78) - (DELAY - (ABSOLUTE - (PORT dataa (714:714:714) (841:841:841)) - (PORT datab (662:662:662) (774:774:774)) - (PORT datad (116:116:116) (153:153:153)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (923:923:923)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (776:776:776) (851:851:851)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (907:907:907) (912:912:912)) - (PORT asdata (1217:1217:1217) (1391:1391:1391)) - (PORT ena (673:673:673) (745:745:745)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~81) - (DELAY - (ABSOLUTE - (PORT dataa (592:592:592) (685:685:685)) - (PORT datab (372:372:372) (450:450:450)) - (PORT datad (461:461:461) (531:531:531)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~82) - (DELAY - (ABSOLUTE - (PORT dataa (321:321:321) (376:376:376)) - (PORT datab (103:103:103) (131:131:131)) - (PORT datac (317:317:317) (369:369:369)) - (PORT datad (91:91:91) (108:108:108)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (666:666:666) (766:766:766)) - (PORT ena (753:753:753) (845:845:845)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (666:666:666) (766:766:766)) - (PORT ena (759:759:759) (842:842:842)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~77) - (DELAY - (ABSOLUTE - (PORT dataa (511:511:511) (625:625:625)) - (PORT datab (512:512:512) (620:620:620)) - (PORT datad (117:117:117) (153:153:153)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (1196:1196:1196) (1350:1350:1350)) - (PORT ena (408:408:408) (429:429:429)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[6\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (509:509:509) (608:608:608)) - (PORT datab (669:669:669) (792:792:792)) - (PORT datad (482:482:482) (561:561:561)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~83) - (DELAY - (ABSOLUTE - (PORT dataa (334:334:334) (390:390:390)) - (PORT datab (338:338:338) (404:404:404)) - (PORT datac (254:254:254) (292:292:292)) - (PORT datad (90:90:90) (106:106:106)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~84) - (DELAY - (ABSOLUTE - (PORT dataa (505:505:505) (602:602:602)) - (PORT datab (349:349:349) (415:415:415)) - (PORT datac (440:440:440) (529:529:529)) - (PORT datad (731:731:731) (840:840:840)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (923:923:923)) - (PORT asdata (618:618:618) (706:706:706)) - (PORT ena (480:480:480) (509:509:509)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (218:218:218) (266:266:266)) - (PORT datab (114:114:114) (142:142:142)) - (PORT datad (199:199:199) (234:234:234)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (132:132:132) (183:183:183)) - (PORT datab (348:348:348) (415:415:415)) - (PORT datad (347:347:347) (404:404:404)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (190:190:190) (230:230:230)) - (PORT datab (388:388:388) (458:458:458)) - (PORT datac (436:436:436) (506:506:506)) - (PORT datad (91:91:91) (108:108:108)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[14\]) - (DELAY - (ABSOLUTE - (PORT dataa (499:499:499) (583:583:583)) - (PORT datac (191:191:191) (227:227:227)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|Q\[14\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (163:163:163) (188:188:188)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[14\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (920:920:920) (905:905:905)) - (PORT ena (1106:1106:1106) (1248:1248:1248)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_16) - (DELAY - (ABSOLUTE - (PORT dataa (627:627:627) (727:727:727)) - (PORT datab (213:213:213) (269:269:269)) - (PORT datac (602:602:602) (688:688:688)) - (PORT datad (345:345:345) (400:400:400)) - (IOPATH dataa combout (188:188:188) (179:179:179)) - (IOPATH datab combout (188:188:188) (177:177:177)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[15\]) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (134:134:134)) - (PORT datab (112:112:112) (144:144:144)) - (PORT datac (127:127:127) (173:173:173)) - (PORT datad (171:171:171) (203:203:203)) - (IOPATH dataa combout (158:158:158) (173:173:173)) - (IOPATH datab combout (160:160:160) (176:176:176)) - (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -23081,429 +20452,12 @@ (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~21) (DELAY (ABSOLUTE - (PORT dataa (200:200:200) (242:242:242)) - (PORT datab (391:391:391) (461:461:461)) - (PORT datac (443:443:443) (513:513:513)) - (PORT datad (288:288:288) (331:331:331)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~75) - (DELAY - (ABSOLUTE - (PORT dataa (508:508:508) (606:606:606)) - (PORT datab (356:356:356) (422:422:422)) - (PORT datac (452:452:452) (521:521:521)) - (PORT datad (729:729:729) (839:839:839)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[7\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (708:708:708) (836:836:836)) - (PORT datab (543:543:543) (638:638:638)) - (PORT datac (1055:1055:1055) (1229:1229:1229)) - (PORT datad (441:441:441) (512:512:512)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[7\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (107:107:107) (139:139:139)) - (PORT datab (138:138:138) (178:178:178)) - (PORT datac (648:648:648) (749:749:749)) - (PORT datad (521:521:521) (607:607:607)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~1) - (DELAY - (ABSOLUTE - (PORT dataa (505:505:505) (584:584:584)) - (PORT datab (661:661:661) (793:793:793)) - (PORT datac (497:497:497) (566:566:566)) - (PORT datad (768:768:768) (892:892:892)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (176:176:176)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~0) - (DELAY - (ABSOLUTE - (PORT dataa (490:490:490) (569:569:569)) - (PORT datab (353:353:353) (410:410:410)) - (PORT datac (359:359:359) (429:429:429)) - (PORT datad (361:361:361) (420:420:420)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (874:874:874) (1031:1031:1031)) - (PORT datab (803:803:803) (960:960:960)) - (PORT datac (791:791:791) (910:910:910)) - (PORT datad (459:459:459) (527:527:527)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (312:312:312) (371:371:371)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (102:102:102) (123:123:123)) - (PORT datad (596:596:596) (686:686:686)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (648:648:648) (747:747:747)) - (PORT datab (550:550:550) (650:650:650)) - (PORT datac (114:114:114) (141:141:141)) - (PORT datad (1129:1129:1129) (1300:1300:1300)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (112:112:112) (147:147:147)) - (PORT datab (334:334:334) (391:391:391)) - (PORT datac (318:318:318) (373:373:373)) - (PORT datad (335:335:335) (384:384:384)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~2) - (DELAY - (ABSOLUTE - (PORT datab (385:385:385) (461:461:461)) - (PORT datac (738:738:738) (842:842:842)) - (PORT datad (620:620:620) (724:724:724)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (952:952:952) (1100:1100:1100)) - (PORT datab (830:830:830) (971:971:971)) - (PORT datac (1441:1441:1441) (1671:1671:1671)) - (PORT datad (1064:1064:1064) (1245:1245:1245)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1091:1091:1091) (1278:1278:1278)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datac (514:514:514) (598:598:598)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~1) - (DELAY - (ABSOLUTE - (PORT dataa (340:340:340) (409:409:409)) - (PORT datab (344:344:344) (403:403:403)) - (PORT datad (484:484:484) (562:562:562)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (190:190:190) (188:188:188)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf) - (DELAY - (ABSOLUTE - (PORT clk (896:896:896) (902:902:902)) - (PORT d (37:37:37) (50:50:50)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (656:656:656) (786:786:786)) - (PORT datab (135:135:135) (186:186:186)) - (PORT datac (749:749:749) (866:866:866)) - (PORT datad (649:649:649) (771:771:771)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~2) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (136:136:136)) - (PORT datab (101:101:101) (130:130:130)) - (PORT datad (643:643:643) (762:762:762)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~5) - (DELAY - (ABSOLUTE - (PORT datab (115:115:115) (143:143:143)) - (PORT datac (487:487:487) (552:552:552)) - (PORT datad (768:768:768) (891:891:891)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (213:213:213) (254:254:254)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (483:483:483) (561:561:561)) - (IOPATH dataa combout (188:188:188) (184:184:184)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (230:230:230) (295:295:295)) - (PORT datab (647:647:647) (748:748:748)) - (PORT datac (321:321:321) (379:379:379)) - (PORT datad (368:368:368) (435:435:435)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (647:647:647) (752:752:752)) - (PORT datab (152:152:152) (195:195:195)) - (PORT datac (135:135:135) (174:174:174)) - (PORT datad (140:140:140) (171:171:171)) + (PORT dataa (755:755:755) (862:862:862)) + (PORT datab (188:188:188) (225:225:225)) + (PORT datac (305:305:305) (353:353:353)) + (PORT datad (90:90:90) (106:106:106)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (175:175:175) (216:216:216)) - (PORT datab (433:433:433) (505:505:505)) - (PORT datac (258:258:258) (289:289:289)) - (PORT datad (604:604:604) (695:695:695)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (316:316:316) (378:378:378)) - (PORT datab (549:549:549) (648:648:648)) - (PORT datac (311:311:311) (363:363:363)) - (PORT datad (121:121:121) (151:151:151)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[3\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (192:192:192) (230:230:230)) - (PORT datab (493:493:493) (573:573:573)) - (PORT datac (627:627:627) (727:727:727)) - (PORT datad (373:373:373) (444:444:444)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_low\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (916:916:916) (901:901:901)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (405:405:405) (422:422:422)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (367:367:367) (440:440:440)) - (PORT datab (659:659:659) (762:762:762)) - (PORT datac (332:332:332) (403:403:403)) - (PORT datad (370:370:370) (438:438:438)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\~2) - (DELAY - (ABSOLUTE - (PORT datab (154:154:154) (199:199:199)) - (PORT datad (134:134:134) (165:165:165)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (153:153:153) (198:198:198)) - (PORT datab (321:321:321) (379:379:379)) - (PORT datac (630:630:630) (728:728:728)) - (PORT datad (91:91:91) (108:108:108)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -23511,258 +20465,43 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|result_lo\[3\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (901:901:901) (909:909:909)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (676:676:676) (740:740:740)) + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (766:766:766) (842:842:842)) + (PORT ena (406:406:406) (423:423:423)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) (HOLD ena (posedge clk) (84:84:84)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~7) + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[7\]\~15) (DELAY (ABSOLUTE - (PORT dataa (523:523:523) (609:609:609)) - (PORT datac (914:914:914) (1063:1063:1063)) - (PORT datad (777:777:777) (877:877:877)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (606:606:606) (693:693:693)) - (PORT datab (615:615:615) (716:716:716)) - (PORT datac (90:90:90) (111:111:111)) - (PORT datad (131:131:131) (159:159:159)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (270:270:270) (311:311:311)) - (PORT datab (466:466:466) (560:560:560)) - (PORT datac (520:520:520) (618:618:618)) - (PORT datad (316:316:316) (367:367:367)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (648:648:648) (761:761:761)) - (PORT datab (328:328:328) (388:388:388)) - (PORT datac (102:102:102) (129:129:129)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[3\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (353:353:353) (417:417:417)) - (PORT datab (503:503:503) (584:584:584)) - (PORT datac (459:459:459) (534:534:534)) - (PORT datad (647:647:647) (738:738:738)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[3\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (347:347:347) (405:405:405)) - (PORT datab (539:539:539) (632:632:632)) - (PORT datac (635:635:635) (724:724:724)) - (PORT datad (120:120:120) (151:151:151)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~7) - (DELAY - (ABSOLUTE - (PORT dataa (122:122:122) (155:155:155)) - (PORT datab (817:817:817) (945:945:945)) - (PORT datac (620:620:620) (709:709:709)) - (PORT datad (92:92:92) (111:111:111)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~49) - (DELAY - (ABSOLUTE - (PORT dataa (658:658:658) (763:763:763)) - (PORT datab (510:510:510) (590:590:590)) - (PORT datac (275:275:275) (319:319:319)) - (PORT datad (447:447:447) (511:511:511)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_oe\~2) - (DELAY - (ABSOLUTE - (PORT dataa (820:820:820) (957:957:957)) - (PORT datab (114:114:114) (142:142:142)) - (PORT datac (127:127:127) (154:154:154)) - (PORT datad (782:782:782) (893:893:893)) + (PORT dataa (841:841:841) (991:991:991)) + (PORT datab (1225:1225:1225) (1414:1414:1414)) + (PORT datad (732:732:732) (823:823:823)) (IOPATH dataa combout (158:158:158) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_35) - (DELAY - (ABSOLUTE - (PORT dataa (342:342:342) (402:402:402)) - (PORT datab (337:337:337) (394:394:394)) - (PORT datac (351:351:351) (419:419:419)) - (PORT datad (369:369:369) (431:431:431)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~7) - (DELAY - (ABSOLUTE - (PORT datab (334:334:334) (395:395:395)) - (PORT datad (467:467:467) (556:556:556)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla69M2T2_3) - (DELAY - (ABSOLUTE - (PORT dataa (341:341:341) (398:398:398)) - (PORT datab (1272:1272:1272) (1479:1479:1479)) - (PORT datac (1155:1155:1155) (1344:1344:1344)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~13) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (247:247:247)) - (PORT datab (922:922:922) (1054:1054:1054)) - (PORT datac (453:453:453) (515:515:515)) - (PORT datad (94:94:94) (114:114:114)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~14) - (DELAY - (ABSOLUTE - (PORT dataa (462:462:462) (559:559:559)) - (PORT datab (185:185:185) (226:226:226)) - (PORT datac (90:90:90) (112:112:112)) - (PORT datad (97:97:97) (117:117:117)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~15) - (DELAY - (ABSOLUTE - (PORT dataa (517:517:517) (607:607:607)) - (PORT datab (369:369:369) (432:432:432)) - (PORT datac (302:302:302) (347:347:347)) - (PORT datad (332:332:332) (387:387:387)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|flags_xf) + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (900:900:900) (905:905:905)) + (PORT clk (904:904:904) (909:909:909)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (421:421:421) (448:448:448)) + (PORT ena (800:800:800) (878:878:878)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -23772,230 +20511,31 @@ ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[3\]\~33) + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[7\]) (DELAY (ABSOLUTE - (PORT datab (515:515:515) (602:602:602)) - (PORT datac (354:354:354) (422:422:422)) - (PORT datad (355:355:355) (423:423:423)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) + (PORT clk (904:904:904) (909:909:909)) + (PORT asdata (278:278:278) (298:298:298)) + (PORT ena (655:655:655) (714:714:714)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~3) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~72) (DELAY (ABSOLUTE - (PORT dataa (178:178:178) (215:215:215)) - (PORT datab (110:110:110) (142:142:142)) - (PORT datac (92:92:92) (115:115:115)) - (PORT datad (354:354:354) (414:414:414)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla23pla16M3T1_5\~0) - (DELAY - (ABSOLUTE - (PORT dataa (471:471:471) (542:542:542)) - (PORT datab (561:561:561) (649:649:649)) - (PORT datac (813:813:813) (945:945:945)) - (PORT datad (636:636:636) (725:725:725)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~4) - (DELAY - (ABSOLUTE - (PORT dataa (348:348:348) (419:419:419)) - (PORT datab (510:510:510) (596:596:596)) - (PORT datac (831:831:831) (950:950:950)) - (PORT datad (625:625:625) (717:717:717)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~5) - (DELAY - (ABSOLUTE - (PORT dataa (326:326:326) (384:384:384)) - (PORT datab (107:107:107) (137:137:137)) - (PORT datac (479:479:479) (558:558:558)) - (PORT datad (102:102:102) (119:119:119)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~8) - (DELAY - (ABSOLUTE - (PORT datab (926:926:926) (1053:1053:1053)) - (PORT datac (804:804:804) (935:935:935)) - (PORT datad (645:645:645) (743:743:743)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sw1_\|db_down\[3\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (205:205:205) (284:284:284)) - (PORT datab (687:687:687) (799:799:799)) - (PORT datac (631:631:631) (721:721:721)) - (PORT datad (503:503:503) (574:574:574)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[3\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (468:468:468) (552:552:552)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (476:476:476) (549:549:549)) - (PORT datad (342:342:342) (397:397:397)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (166:166:166) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[3\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (331:331:331) (391:391:391)) - (PORT datab (133:133:133) (168:168:168)) - (PORT datac (627:627:627) (722:722:722)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~46) - (DELAY - (ABSOLUTE - (PORT dataa (235:235:235) (299:299:299)) - (PORT datab (630:630:630) (725:725:725)) - (PORT datad (805:805:805) (920:920:920)) + (PORT dataa (388:388:388) (465:465:465)) + (PORT datab (329:329:329) (396:396:396)) + (PORT datad (382:382:382) (448:448:448)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~47) - (DELAY - (ABSOLUTE - (PORT dataa (218:218:218) (274:274:274)) - (PORT datac (89:89:89) (111:111:111)) - (PORT datad (881:881:881) (999:999:999)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~50) - (DELAY - (ABSOLUTE - (PORT datab (182:182:182) (224:224:224)) - (PORT datac (419:419:419) (476:476:476)) - (PORT datad (164:164:164) (193:193:193)) (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (902:902:902) (908:908:908)) - (PORT asdata (527:527:527) (588:588:588)) - (PORT ena (756:756:756) (816:816:816)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (902:902:902) (908:908:908)) - (PORT asdata (527:527:527) (588:588:588)) - (PORT ena (915:915:915) (1002:1002:1002)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~44) - (DELAY - (ABSOLUTE - (PORT dataa (134:134:134) (187:187:187)) - (PORT datab (546:546:546) (643:643:643)) - (PORT datad (470:470:470) (544:544:544)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -24003,28 +20543,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[3\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (451:451:451) (486:486:486)) - (PORT ena (419:419:419) (435:435:435)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (451:451:451) (486:486:486)) - (PORT ena (432:432:432) (460:460:460)) + (PORT clk (904:904:904) (909:909:909)) + (PORT asdata (899:899:899) (988:988:988)) + (PORT ena (619:619:619) (671:671:671)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -24035,309 +20559,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~43) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~71) (DELAY (ABSOLUTE - (PORT dataa (131:131:131) (182:182:182)) - (PORT datab (137:137:137) (176:176:176)) - (PORT datad (121:121:121) (146:146:146)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~51) - (DELAY - (ABSOLUTE - (PORT dataa (451:451:451) (520:520:520)) - (PORT datab (105:105:105) (134:134:134)) - (PORT datac (327:327:327) (382:382:382)) - (PORT datad (335:335:335) (393:393:393)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~52) - (DELAY - (ABSOLUTE - (PORT dataa (464:464:464) (542:542:542)) - (PORT datab (328:328:328) (383:383:383)) - (PORT datac (172:172:172) (202:202:202)) - (PORT datad (603:603:603) (692:692:692)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (515:515:515) (573:573:573)) - (PORT ena (636:636:636) (682:682:682)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (724:724:724) (825:825:825)) - (PORT datab (383:383:383) (454:454:454)) - (PORT datad (659:659:659) (768:768:768)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (920:920:920) (927:927:927)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (679:679:679) (746:746:746)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (336:336:336) (401:401:401)) - (PORT datac (386:386:386) (461:461:461)) - (PORT datad (119:119:119) (157:157:157)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (193:193:193) (230:230:230)) - (PORT datab (526:526:526) (617:617:617)) - (PORT datac (376:376:376) (448:448:448)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[3\]) - (DELAY - (ABSOLUTE - (PORT datab (129:129:129) (162:162:162)) - (PORT datac (283:283:283) (331:331:331)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (920:920:920) (928:928:928)) - (PORT asdata (447:447:447) (488:488:488)) - (PORT clrn (927:927:927) (909:909:909)) - (PORT ena (1168:1168:1168) (1321:1321:1321)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_45\~4) - (DELAY - (ABSOLUTE - (PORT dataa (203:203:203) (245:245:245)) - (PORT datab (634:634:634) (730:730:730)) - (PORT datac (543:543:543) (635:635:635)) - (PORT datad (132:132:132) (170:170:170)) - (IOPATH dataa combout (181:181:181) (180:180:180)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|carry_borrow_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (179:179:179) (223:223:223)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (177:177:177) (209:209:209)) - (PORT datad (165:165:165) (195:195:195)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_4\|d0_out) - (DELAY - (ABSOLUTE - (PORT dataa (143:143:143) (194:194:194)) - (PORT datab (108:108:108) (139:139:139)) - (PORT datac (170:170:170) (202:202:202)) - (PORT datad (103:103:103) (120:120:120)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (659:659:659) (731:731:731)) - (PORT ena (419:419:419) (435:435:435)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (655:655:655) (727:727:727)) - (PORT ena (432:432:432) (460:460:460)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~53) - (DELAY - (ABSOLUTE - (PORT dataa (132:132:132) (183:183:183)) - (PORT datab (137:137:137) (175:175:175)) - (PORT datad (122:122:122) (147:147:147)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~54) - (DELAY - (ABSOLUTE - (PORT dataa (326:326:326) (387:387:387)) - (PORT datab (627:627:627) (721:721:721)) - (PORT datad (336:336:336) (393:393:393)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (911:911:911) (918:918:918)) - (PORT asdata (634:634:634) (705:705:705)) - (PORT ena (422:422:422) (454:454:454)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (911:911:911) (918:918:918)) - (PORT asdata (638:638:638) (710:710:710)) - (PORT ena (669:669:669) (725:725:725)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~58) - (DELAY - (ABSOLUTE - (PORT dataa (218:218:218) (273:273:273)) - (PORT datab (314:314:314) (372:372:372)) - (PORT datad (119:119:119) (157:157:157)) + (PORT dataa (641:641:641) (754:754:754)) + (PORT datab (505:505:505) (583:583:583)) + (PORT datad (210:210:210) (257:257:257)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -24345,28 +20574,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[4\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (906:906:906) (910:910:910)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (794:794:794) (880:880:880)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (910:910:910)) - (PORT asdata (492:492:492) (533:533:533)) - (PORT ena (631:631:631) (680:680:680)) + (PORT clk (905:905:905) (910:910:910)) + (PORT asdata (792:792:792) (875:875:875)) + (PORT ena (649:649:649) (707:707:707)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -24377,12 +20590,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[4\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (906:906:906) (910:910:910)) - (PORT asdata (493:493:493) (533:533:533)) - (PORT ena (660:660:660) (723:723:723)) + (PORT clk (905:905:905) (910:910:910)) + (PORT asdata (792:792:792) (874:874:874)) + (PORT ena (604:604:604) (647:647:647)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -24393,11 +20606,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~59) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~70) (DELAY (ABSOLUTE - (PORT dataa (231:231:231) (294:294:294)) - (PORT datab (359:359:359) (425:425:425)) + (PORT dataa (365:365:365) (434:434:434)) + (PORT datab (144:144:144) (181:181:181)) (PORT datad (117:117:117) (152:152:152)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) @@ -24406,30 +20619,14 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~60) - (DELAY - (ABSOLUTE - (PORT dataa (343:343:343) (403:403:403)) - (PORT datab (493:493:493) (580:580:580)) - (PORT datac (114:114:114) (155:155:155)) - (PORT datad (170:170:170) (201:201:201)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[4\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (902:902:902) (908:908:908)) - (PORT asdata (531:531:531) (590:590:590)) - (PORT ena (915:915:915) (1002:1002:1002)) + (PORT clk (902:902:902) (907:907:907)) + (PORT asdata (673:673:673) (747:747:747)) + (PORT ena (648:648:648) (700:700:700)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -24440,12 +20637,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[4\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (902:902:902) (908:908:908)) - (PORT asdata (534:534:534) (593:593:593)) - (PORT ena (756:756:756) (816:816:816)) + (PORT clk (902:902:902) (907:907:907)) + (PORT asdata (671:671:671) (744:744:744)) + (PORT ena (757:757:757) (811:811:811)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -24456,12 +20653,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~57) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~69) (DELAY (ABSOLUTE - (PORT dataa (487:487:487) (572:572:572)) - (PORT datab (537:537:537) (632:632:632)) - (PORT datad (117:117:117) (154:154:154)) + (PORT dataa (383:383:383) (455:455:455)) + (PORT datab (346:346:346) (405:405:405)) + (PORT datad (118:118:118) (155:155:155)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (190:190:190) (195:195:195)) @@ -24469,91 +20666,15 @@ ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (910:910:910) (918:918:918)) - (PORT asdata (523:523:523) (580:580:580)) - (PORT ena (421:421:421) (449:449:449)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (910:910:910) (918:918:918)) - (PORT asdata (523:523:523) (579:579:579)) - (PORT ena (644:644:644) (698:698:698)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~55) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~73) (DELAY (ABSOLUTE - (PORT dataa (359:359:359) (431:431:431)) - (PORT datab (209:209:209) (253:253:253)) - (PORT datad (116:116:116) (153:153:153)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (910:910:910)) - (PORT asdata (453:453:453) (485:485:485)) - (PORT ena (736:736:736) (793:793:793)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~56) - (DELAY - (ABSOLUTE - (PORT dataa (273:273:273) (317:317:317)) - (PORT datad (433:433:433) (505:505:505)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~61) - (DELAY - (ABSOLUTE - (PORT dataa (174:174:174) (215:215:215)) - (PORT datab (102:102:102) (131:131:131)) - (PORT datac (544:544:544) (619:619:619)) - (PORT datad (90:90:90) (106:106:106)) + (PORT dataa (450:450:450) (523:523:523)) + (PORT datab (321:321:321) (376:376:376)) + (PORT datac (288:288:288) (323:323:323)) + (PORT datad (184:184:184) (214:214:214)) (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -24562,29 +20683,29 @@ ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~62) + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[7\]) (DELAY (ABSOLUTE - (PORT dataa (103:103:103) (133:133:133)) - (PORT datab (463:463:463) (533:533:533)) - (PORT datac (614:614:614) (701:701:701)) - (PORT datad (635:635:635) (735:735:735)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) + (PORT clk (902:902:902) (907:907:907)) + (PORT asdata (480:480:480) (517:517:517)) + (PORT ena (649:649:649) (705:705:705)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[4\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (729:729:729) (807:807:807)) - (PORT ena (636:636:636) (682:682:682)) + (PORT clk (902:902:902) (907:907:907)) + (PORT asdata (482:482:482) (520:520:520)) + (PORT ena (422:422:422) (449:449:449)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -24595,14 +20716,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~13) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~68) (DELAY (ABSOLUTE - (PORT dataa (479:479:479) (546:546:546)) - (PORT datab (681:681:681) (797:797:797)) - (PORT datad (365:365:365) (428:428:428)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (PORT dataa (384:384:384) (460:460:460)) + (PORT datab (130:130:130) (178:178:178)) + (PORT datad (127:127:127) (155:155:155)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -24610,12 +20731,38 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[4\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (920:920:920) (927:927:927)) + (PORT clk (902:902:902) (907:907:907)) + (PORT asdata (759:759:759) (832:832:832)) + (PORT ena (501:501:501) (541:541:541)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (473:473:473) (545:545:545)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (679:679:679) (746:746:746)) + (PORT ena (621:621:621) (666:666:666)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -24626,27 +20773,44 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~14) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~67) (DELAY (ABSOLUTE - (PORT datab (349:349:349) (408:408:408)) - (PORT datac (385:385:385) (459:459:459)) - (PORT datad (117:117:117) (154:154:154)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) + (PORT dataa (348:348:348) (422:422:422)) + (PORT datab (369:369:369) (432:432:432)) + (PORT datad (116:116:116) (152:152:152)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~15) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~74) (DELAY (ABSOLUTE - (PORT dataa (193:193:193) (230:230:230)) - (PORT datab (527:527:527) (619:619:619)) - (PORT datac (375:375:375) (448:448:448)) - (PORT datad (90:90:90) (106:106:106)) + (PORT dataa (293:293:293) (340:340:340)) + (PORT datab (446:446:446) (538:538:538)) + (PORT datac (432:432:432) (503:503:503)) + (PORT datad (189:189:189) (222:222:222)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~75) + (DELAY + (ABSOLUTE + (PORT dataa (447:447:447) (519:519:519)) + (PORT datab (496:496:496) (573:573:573)) + (PORT datac (620:620:620) (720:720:720)) + (PORT datad (296:296:296) (341:341:341)) (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (125:125:125)) @@ -24656,27 +20820,398 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[4\]) + (INSTANCE z80_\|alu_\|db\[7\]\~11) (DELAY (ABSOLUTE - (PORT datab (126:126:126) (159:159:159)) - (PORT datad (272:272:272) (314:314:314)) + (PORT dataa (332:332:332) (404:404:404)) + (PORT datab (476:476:476) (547:547:547)) + (PORT datac (305:305:305) (357:357:357)) + (PORT datad (343:343:343) (392:392:392)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[7\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (390:390:390) (476:476:476)) + (PORT datab (142:142:142) (184:184:184)) + (PORT datac (470:470:470) (543:543:543)) + (PORT datad (94:94:94) (113:113:113)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (481:481:481) (562:562:562)) + (PORT datac (287:287:287) (339:339:339)) + (PORT datad (395:395:395) (488:488:488)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~1) + (DELAY + (ABSOLUTE + (PORT datab (105:105:105) (134:134:134)) + (PORT datac (96:96:96) (122:122:122)) + (PORT datad (608:608:608) (695:695:695)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~2) + (DELAY + (ABSOLUTE + (PORT dataa (468:468:468) (552:552:552)) + (PORT datab (104:104:104) (132:132:132)) + (PORT datac (613:613:613) (691:691:691)) + (PORT datad (606:606:606) (693:693:693)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~3) + (DELAY + (ABSOLUTE + (PORT dataa (628:628:628) (715:715:715)) + (PORT datab (374:374:374) (437:437:437)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH datab combout (196:196:196) (192:192:192)) + (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[4\]) + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2) (DELAY (ABSOLUTE - (PORT clk (920:920:920) (928:928:928)) - (PORT asdata (441:441:441) (473:473:473)) - (PORT clrn (927:927:927) (909:909:909)) - (PORT ena (1168:1168:1168) (1321:1321:1321)) + (PORT clk (909:909:909) (913:913:913)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~8) + (DELAY + (ABSOLUTE + (PORT dataa (502:502:502) (595:595:595)) + (PORT datac (312:312:312) (367:367:367)) + (PORT datad (211:211:211) (256:256:256)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~9) + (DELAY + (ABSOLUTE + (PORT dataa (629:629:629) (726:726:726)) + (PORT datab (552:552:552) (648:648:648)) + (PORT datac (161:161:161) (194:194:194)) + (PORT datad (502:502:502) (592:592:592)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1221:1221:1221) (1420:1420:1420)) + (PORT datab (881:881:881) (1021:1021:1021)) + (PORT datac (1013:1013:1013) (1178:1178:1178)) + (PORT datad (547:547:547) (680:680:680)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~11) + (DELAY + (ABSOLUTE + (PORT dataa (528:528:528) (618:618:618)) + (PORT datab (338:338:338) (395:395:395)) + (PORT datac (1362:1362:1362) (1562:1562:1562)) + (PORT datad (303:303:303) (350:350:350)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~12) + (DELAY + (ABSOLUTE + (PORT dataa (760:760:760) (868:868:868)) + (PORT datab (192:192:192) (233:233:233)) + (PORT datac (587:587:587) (662:662:662)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~9) + (DELAY + (ABSOLUTE + (PORT dataa (323:323:323) (398:398:398)) + (PORT datab (663:663:663) (770:770:770)) + (PORT datac (324:324:324) (381:381:381)) + (PORT datad (380:380:380) (461:461:461)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~46) + (DELAY + (ABSOLUTE + (PORT dataa (844:844:844) (985:985:985)) + (PORT datab (850:850:850) (992:992:992)) + (PORT datad (1056:1056:1056) (1231:1231:1231)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~9) + (DELAY + (ABSOLUTE + (PORT dataa (340:340:340) (402:402:402)) + (PORT datab (114:114:114) (141:141:141)) + (PORT datac (98:98:98) (123:123:123)) + (PORT datad (337:337:337) (398:398:398)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~10) + (DELAY + (ABSOLUTE + (PORT dataa (517:517:517) (605:605:605)) + (PORT datab (468:468:468) (543:543:543)) + (PORT datac (525:525:525) (611:611:611)) + (PORT datad (113:113:113) (134:134:134)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~11) + (DELAY + (ABSOLUTE + (PORT dataa (845:845:845) (977:977:977)) + (PORT datab (107:107:107) (137:137:137)) + (PORT datac (444:444:444) (506:506:506)) + (PORT datad (338:338:338) (395:395:395)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~14) + (DELAY + (ABSOLUTE + (PORT dataa (635:635:635) (737:737:737)) + (PORT datab (366:366:366) (429:429:429)) + (PORT datac (311:311:311) (359:359:359)) + (PORT datad (349:349:349) (404:404:404)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1165:1165:1165) (1382:1382:1382)) + (PORT datab (666:666:666) (803:803:803)) + (PORT datac (531:531:531) (617:617:617)) + (PORT datad (692:692:692) (827:827:827)) + (IOPATH dataa combout (159:159:159) (173:173:173)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~16) + (DELAY + (ABSOLUTE + (PORT dataa (567:567:567) (674:674:674)) + (PORT datab (126:126:126) (158:158:158)) + (PORT datac (161:161:161) (189:189:189)) + (PORT datad (794:794:794) (902:902:902)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~3) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (402:402:402)) + (PORT datab (665:665:665) (772:772:772)) + (PORT datac (455:455:455) (518:518:518)) + (PORT datad (609:609:609) (689:689:689)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|flags_cf) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (426:426:426)) + (PORT datab (500:500:500) (595:595:595)) + (PORT datac (89:89:89) (109:109:109)) + (PORT datad (199:199:199) (236:236:236)) + (IOPATH dataa combout (188:188:188) (203:203:203)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sw2_\|db_up\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT datac (458:458:458) (538:538:538)) + (PORT datad (283:283:283) (327:327:327)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[0\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (458:458:458) (535:535:535)) + (PORT datab (309:309:309) (362:362:362)) + (PORT datac (217:217:217) (264:264:264)) + (PORT datad (319:319:319) (372:372:372)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (633:633:633) (693:693:693)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (348:348:348) (378:378:378)) + (PORT ena (621:621:621) (659:659:659)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) ) (TIMINGCHECK @@ -24686,14 +21221,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_44) + (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~0) (DELAY (ABSOLUTE - (PORT dataa (620:620:620) (721:721:721)) - (PORT datab (546:546:546) (639:639:639)) - (PORT datad (106:106:106) (124:124:124)) - (IOPATH dataa combout (188:188:188) (203:203:203)) - (IOPATH datab combout (188:188:188) (177:177:177)) + (PORT dataa (495:495:495) (573:573:573)) + (PORT datab (677:677:677) (787:787:787)) + (PORT datad (208:208:208) (252:252:252)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -24701,42 +21236,1150 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_4\|d1_out) + (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~1) (DELAY (ABSOLUTE - (PORT dataa (362:362:362) (439:439:439)) - (PORT datab (642:642:642) (741:741:741)) - (PORT datac (338:338:338) (393:393:393)) - (IOPATH dataa combout (195:195:195) (203:203:203)) - (IOPATH datab combout (188:188:188) (177:177:177)) + (PORT dataa (132:132:132) (182:182:182)) + (PORT datac (88:88:88) (109:109:109)) + (PORT datad (314:314:314) (365:365:365)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~70) + (DELAY + (ABSOLUTE + (PORT dataa (556:556:556) (663:663:663)) + (PORT datab (884:884:884) (1008:1008:1008)) + (PORT datac (891:891:891) (1046:1046:1046)) + (PORT datad (1602:1602:1602) (1866:1866:1866)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~28) + (DELAY + (ABSOLUTE + (PORT dataa (946:946:946) (1100:1100:1100)) + (PORT datab (1037:1037:1037) (1201:1201:1201)) + (PORT datac (657:657:657) (778:778:778)) + (PORT datad (553:553:553) (649:649:649)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~15) + (DELAY + (ABSOLUTE + (PORT dataa (935:935:935) (1075:1075:1075)) + (PORT datab (503:503:503) (584:584:584)) + (PORT datac (88:88:88) (109:109:109)) + (PORT datad (378:378:378) (451:451:451)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~27) + (DELAY + (ABSOLUTE + (PORT dataa (943:943:943) (1097:1097:1097)) + (PORT datab (381:381:381) (451:451:451)) + (PORT datac (658:658:658) (778:778:778)) + (PORT datad (550:550:550) (645:645:645)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~10) + (DELAY + (ABSOLUTE + (PORT dataa (543:543:543) (648:648:648)) + (PORT datab (119:119:119) (148:148:148)) + (PORT datac (459:459:459) (535:535:535)) + (PORT datad (108:108:108) (128:128:128)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla38pla13M3T2_4) + (DELAY + (ABSOLUTE + (PORT dataa (539:539:539) (643:643:643)) + (PORT datab (939:939:939) (1111:1111:1111)) + (PORT datac (598:598:598) (687:687:687)) + (PORT datad (475:475:475) (561:561:561)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1619:1619:1619) (1891:1891:1891)) + (PORT datab (1279:1279:1279) (1469:1469:1469)) + (PORT datac (678:678:678) (784:784:784)) + (PORT datad (700:700:700) (823:823:823)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla40M3T2_4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (659:659:659) (753:753:753)) + (PORT datab (678:678:678) (834:834:834)) + (PORT datac (518:518:518) (613:613:613)) + (PORT datad (347:347:347) (406:406:406)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~9) + (DELAY + (ABSOLUTE + (PORT dataa (474:474:474) (547:547:547)) + (PORT datab (121:121:121) (151:151:151)) + (PORT datac (602:602:602) (691:691:691)) + (PORT datad (516:516:516) (603:603:603)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~12) + (DELAY + (ABSOLUTE + (PORT dataa (109:109:109) (143:143:143)) + (PORT datab (107:107:107) (137:137:137)) + (PORT datac (351:351:351) (417:417:417)) + (PORT datad (334:334:334) (392:392:392)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~7) + (DELAY + (ABSOLUTE + (PORT dataa (645:645:645) (757:757:757)) + (PORT datab (500:500:500) (576:576:576)) + (PORT datac (465:465:465) (536:536:536)) + (PORT datad (732:732:732) (860:860:860)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~8) + (DELAY + (ABSOLUTE + (PORT dataa (711:711:711) (854:854:854)) + (PORT datab (842:842:842) (987:987:987)) + (PORT datac (504:504:504) (584:584:584)) + (PORT datad (1617:1617:1617) (1876:1876:1876)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1116:1116:1116) (1299:1299:1299)) + (PORT datab (1399:1399:1399) (1642:1642:1642)) + (PORT datac (369:369:369) (437:437:437)) + (PORT datad (548:548:548) (644:644:644)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~14) + (DELAY + (ABSOLUTE + (PORT dataa (346:346:346) (409:409:409)) + (PORT datab (352:352:352) (415:415:415)) + (PORT datac (98:98:98) (124:124:124)) + (PORT datad (177:177:177) (209:209:209)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_use_ixiypla53M2T2_4) + (DELAY + (ABSOLUTE + (PORT dataa (1116:1116:1116) (1299:1299:1299)) + (PORT datab (652:652:652) (747:747:747)) + (PORT datac (449:449:449) (518:518:518)) + (PORT datad (548:548:548) (644:644:644)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~16) + (DELAY + (ABSOLUTE + (PORT dataa (295:295:295) (342:342:342)) + (PORT datab (200:200:200) (241:241:241)) + (PORT datac (93:93:93) (116:116:116)) + (PORT datad (170:170:170) (201:201:201)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~22) + (DELAY + (ABSOLUTE + (PORT dataa (356:356:356) (415:415:415)) + (PORT datab (721:721:721) (865:865:865)) + (PORT datac (822:822:822) (976:976:976)) + (PORT datad (902:902:902) (1039:1039:1039)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~23) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (246:246:246)) + (PORT datab (655:655:655) (773:773:773)) + (PORT datac (753:753:753) (860:860:860)) + (PORT datad (1259:1259:1259) (1467:1467:1467)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~24) + (DELAY + (ABSOLUTE + (PORT dataa (860:860:860) (1004:1004:1004)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (87:87:87) (109:109:109)) + (PORT datad (1259:1259:1259) (1467:1467:1467)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~41) + (DELAY + (ABSOLUTE + (PORT dataa (544:544:544) (635:635:635)) + (PORT datab (531:531:531) (613:613:613)) + (PORT datac (693:693:693) (816:816:816)) + (PORT datad (365:365:365) (430:430:430)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~21) + (DELAY + (ABSOLUTE + (PORT dataa (463:463:463) (535:535:535)) + (PORT datab (767:767:767) (881:881:881)) + (PORT datac (904:904:904) (1025:1025:1025)) + (PORT datad (443:443:443) (517:517:517)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~25) + (DELAY + (ABSOLUTE + (PORT dataa (355:355:355) (420:420:420)) + (PORT datab (492:492:492) (566:566:566)) + (PORT datac (475:475:475) (551:551:551)) + (PORT datad (94:94:94) (114:114:114)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~69) + (DELAY + (ABSOLUTE + (PORT dataa (552:552:552) (659:659:659)) + (PORT datab (1620:1620:1620) (1891:1891:1891)) + (PORT datac (93:93:93) (117:117:117)) + (PORT datad (773:773:773) (875:875:875)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~17) + (DELAY + (ABSOLUTE + (PORT dataa (255:255:255) (333:333:333)) + (PORT datac (150:150:150) (202:202:202)) + (PORT datad (389:389:389) (468:468:468)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~71) + (DELAY + (ABSOLUTE + (PORT dataa (895:895:895) (1040:1040:1040)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (93:93:93) (116:116:116)) + (PORT datad (648:648:648) (752:752:752)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~44) + (DELAY + (ABSOLUTE + (PORT dataa (114:114:114) (145:145:145)) + (PORT datab (773:773:773) (905:905:905)) + (PORT datac (335:335:335) (391:391:391)) + (PORT datad (652:652:652) (757:757:757)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~42) + (DELAY + (ABSOLUTE + (PORT dataa (356:356:356) (422:422:422)) + (PORT datac (475:475:475) (550:550:550)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~43) + (DELAY + (ABSOLUTE + (PORT dataa (674:674:674) (784:784:784)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (553:553:553) (631:631:631)) + (PORT datad (541:541:541) (634:634:634)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~57) + (DELAY + (ABSOLUTE + (PORT dataa (760:760:760) (873:873:873)) + (PORT datab (636:636:636) (735:735:735)) + (PORT datac (334:334:334) (395:395:395)) + (PORT datad (324:324:324) (381:381:381)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~54) + (DELAY + (ABSOLUTE + (PORT dataa (940:940:940) (1093:1093:1093)) + (PORT datab (1400:1400:1400) (1643:1643:1643)) + (PORT datac (1025:1025:1025) (1183:1183:1183)) + (PORT datad (376:376:376) (449:449:449)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~58) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (200:200:200) (241:241:241)) + (PORT datac (94:94:94) (117:117:117)) + (PORT datad (165:165:165) (194:194:194)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~18) + (DELAY + (ABSOLUTE + (PORT dataa (541:541:541) (646:646:646)) + (PORT datab (119:119:119) (148:148:148)) + (PORT datac (94:94:94) (118:118:118)) + (PORT datad (332:332:332) (390:390:390)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~19) + (DELAY + (ABSOLUTE + (PORT dataa (459:459:459) (525:525:525)) + (PORT datab (193:193:193) (232:232:232)) + (PORT datac (339:339:339) (401:401:401)) + (PORT datad (320:320:320) (372:372:372)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~45) + (DELAY + (ABSOLUTE + (PORT dataa (662:662:662) (774:774:774)) + (PORT datab (562:562:562) (655:655:655)) + (PORT datac (298:298:298) (333:333:333)) + (PORT datad (812:812:812) (934:934:934)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~34) + (DELAY + (ABSOLUTE + (PORT dataa (1620:1620:1620) (1892:1892:1892)) + (PORT datab (706:706:706) (824:824:824)) + (PORT datac (551:551:551) (649:649:649)) + (PORT datad (698:698:698) (821:821:821)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~35) + (DELAY + (ABSOLUTE + (PORT dataa (712:712:712) (846:846:846)) + (PORT datab (107:107:107) (137:137:137)) + (PORT datac (368:368:368) (438:438:438)) + (PORT datad (88:88:88) (106:106:106)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~46) + (DELAY + (ABSOLUTE + (PORT dataa (697:697:697) (809:809:809)) + (PORT datab (703:703:703) (815:815:815)) + (PORT datac (699:699:699) (819:819:819)) + (PORT datad (815:815:815) (938:938:938)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~47) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (412:412:412)) + (PORT datab (704:704:704) (815:815:815)) + (PORT datac (866:866:866) (999:999:999)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~48) + (DELAY + (ABSOLUTE + (PORT dataa (537:537:537) (620:620:620)) + (PORT datab (1405:1405:1405) (1647:1647:1647)) + (PORT datac (327:327:327) (375:375:375)) + (PORT datad (529:529:529) (609:609:609)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~50) + (DELAY + (ABSOLUTE + (PORT dataa (346:346:346) (402:402:402)) + (PORT datab (111:111:111) (142:142:142)) + (PORT datac (507:507:507) (584:584:584)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~51) + (DELAY + (ABSOLUTE + (PORT dataa (114:114:114) (150:150:150)) + (PORT datab (637:637:637) (736:736:736)) + (PORT datac (99:99:99) (125:125:125)) + (PORT datad (511:511:511) (595:595:595)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~85) + (DELAY + (ABSOLUTE + (PORT dataa (711:711:711) (854:854:854)) + (PORT datab (670:670:670) (796:796:796)) + (PORT datac (533:533:533) (635:635:635)) + (PORT datad (362:362:362) (427:427:427)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~63) + (DELAY + (ABSOLUTE + (PORT dataa (260:260:260) (339:339:339)) + (PORT datab (495:495:495) (589:589:589)) + (PORT datac (470:470:470) (539:539:539)) + (PORT datad (386:386:386) (464:464:464)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~64) + (DELAY + (ABSOLUTE + (PORT dataa (115:115:115) (145:145:145)) + (PORT datab (474:474:474) (548:548:548)) + (PORT datac (460:460:460) (536:536:536)) + (PORT datad (332:332:332) (390:390:390)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~65) + (DELAY + (ABSOLUTE + (PORT dataa (119:119:119) (151:151:151)) + (PORT datab (104:104:104) (132:132:132)) + (PORT datac (302:302:302) (345:345:345)) + (PORT datad (103:103:103) (120:120:120)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~59) + (DELAY + (ABSOLUTE + (PORT dataa (498:498:498) (588:588:588)) + (PORT datab (939:939:939) (1112:1112:1112)) + (PORT datac (462:462:462) (538:538:538)) + (PORT datad (492:492:492) (570:570:570)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~60) + (DELAY + (ABSOLUTE + (PORT dataa (102:102:102) (133:133:133)) + (PORT datab (353:353:353) (417:417:417)) + (PORT datac (93:93:93) (116:116:116)) + (PORT datad (455:455:455) (523:523:523)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~61) + (DELAY + (ABSOLUTE + (PORT dataa (711:711:711) (854:854:854)) + (PORT datab (669:669:669) (796:796:796)) + (PORT datac (535:535:535) (637:637:637)) + (PORT datad (621:621:621) (710:710:710)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~62) + (DELAY + (ABSOLUTE + (PORT dataa (346:346:346) (409:409:409)) + (PORT datab (340:340:340) (402:402:402)) + (PORT datac (321:321:321) (379:379:379)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~66) + (DELAY + (ABSOLUTE + (PORT dataa (102:102:102) (133:133:133)) + (PORT datab (175:175:175) (214:214:214)) + (PORT datac (102:102:102) (129:129:129)) + (PORT datad (90:90:90) (106:106:106)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~53) + (DELAY + (ABSOLUTE + (PORT dataa (743:743:743) (882:882:882)) + (PORT datab (108:108:108) (139:139:139)) + (PORT datac (651:651:651) (751:751:751)) + (PORT datad (727:727:727) (834:834:834)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~52) + (DELAY + (ABSOLUTE + (PORT dataa (717:717:717) (834:834:834)) + (PORT datab (757:757:757) (865:865:865)) + (PORT datac (605:605:605) (683:683:683)) + (PORT datad (483:483:483) (558:558:558)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~84) + (DELAY + (ABSOLUTE + (PORT dataa (976:976:976) (1141:1141:1141)) + (PORT datab (101:101:101) (129:129:129)) + (PORT datac (108:108:108) (132:132:132)) + (PORT datad (662:662:662) (772:772:772)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla91pla20M2T2_3) + (DELAY + (ABSOLUTE + (PORT dataa (714:714:714) (857:857:857)) + (PORT datab (838:838:838) (982:982:982)) + (PORT datac (477:477:477) (551:551:551)) + (PORT datad (894:894:894) (1017:1017:1017)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~55) + (DELAY + (ABSOLUTE + (PORT dataa (503:503:503) (593:593:593)) + (PORT datab (114:114:114) (142:142:142)) + (PORT datac (429:429:429) (484:484:484)) + (PORT datad (165:165:165) (194:194:194)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~56) + (DELAY + (ABSOLUTE + (PORT dataa (330:330:330) (387:387:387)) + (PORT datab (348:348:348) (409:409:409)) + (PORT datac (621:621:621) (713:713:713)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~67) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (133:133:133)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (90:90:90) (112:112:112)) + (PORT datad (92:92:92) (109:109:109)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~20) + (DELAY + (ABSOLUTE + (PORT dataa (113:113:113) (149:149:149)) + (PORT datab (200:200:200) (241:241:241)) + (PORT datac (99:99:99) (125:125:125)) + (PORT datad (273:273:273) (314:314:314)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~83) + (DELAY + (ABSOLUTE + (PORT dataa (712:712:712) (831:831:831)) + (PORT datab (850:850:850) (999:999:999)) + (PORT datac (322:322:322) (376:376:376)) + (PORT datad (700:700:700) (830:830:830)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~68) + (DELAY + (ABSOLUTE + (PORT dataa (106:106:106) (138:138:138)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (320:320:320) (380:380:380)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|Q\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (105:105:105) (123:123:123)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[5\]) + (INSTANCE z80_\|address_latch_\|Q\[0\]) (DELAY (ABSOLUTE - (PORT clk (902:902:902) (908:908:908)) - (PORT asdata (458:458:458) (495:495:495)) - (PORT ena (756:756:756) (816:816:816)) + (PORT clk (908:908:908) (915:915:915)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (911:911:911) (895:895:895)) + (PORT ena (1070:1070:1070) (1171:1171:1171)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) + (HOLD d (posedge clk) (84:84:84)) (HOLD ena (posedge clk) (84:84:84)) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[5\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~72) (DELAY (ABSOLUTE - (PORT clk (902:902:902) (908:908:908)) - (PORT asdata (458:458:458) (495:495:495)) - (PORT ena (915:915:915) (1002:1002:1002)) + (PORT dataa (354:354:354) (420:420:420)) + (PORT datab (345:345:345) (401:401:401)) + (PORT datac (476:476:476) (551:551:551)) + (PORT datad (94:94:94) (113:113:113)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~73) + (DELAY + (ABSOLUTE + (PORT dataa (879:879:879) (1048:1048:1048)) + (PORT datab (528:528:528) (623:623:623)) + (PORT datac (110:110:110) (136:136:136)) + (PORT datad (1011:1011:1011) (1182:1182:1182)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~74) + (DELAY + (ABSOLUTE + (PORT dataa (108:108:108) (140:140:140)) + (PORT datab (672:672:672) (780:780:780)) + (PORT datac (756:756:756) (875:875:875)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~75) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (135:135:135)) + (PORT datab (108:108:108) (139:139:139)) + (PORT datac (344:344:344) (405:405:405)) + (PORT datad (651:651:651) (756:756:756)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~76) + (DELAY + (ABSOLUTE + (PORT dataa (116:116:116) (151:151:151)) + (PORT datab (106:106:106) (136:136:136)) + (PORT datac (277:277:277) (311:311:311)) + (PORT datad (183:183:183) (213:213:213)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~80) + (DELAY + (ABSOLUTE + (PORT datab (103:103:103) (131:131:131)) + (PORT datac (640:640:640) (737:737:737)) + (PORT datad (97:97:97) (117:117:117)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~81) + (DELAY + (ABSOLUTE + (PORT dataa (673:673:673) (782:782:782)) + (PORT datab (106:106:106) (137:137:137)) + (PORT datac (89:89:89) (109:109:109)) + (PORT datad (336:336:336) (390:390:390)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|d0_out) + (DELAY + (ABSOLUTE + (PORT dataa (862:862:862) (1008:1008:1008)) + (PORT datab (874:874:874) (980:980:980)) + (PORT datac (136:136:136) (183:183:183)) + (PORT datad (821:821:821) (950:950:950)) + (IOPATH dataa combout (192:192:192) (184:184:184)) + (IOPATH datab combout (191:191:191) (188:188:188)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (925:925:925) (1052:1052:1052)) + (PORT datab (102:102:102) (131:131:131)) + (PORT datac (424:424:424) (484:484:484)) + (PORT datad (183:183:183) (217:217:217)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (919:919:919)) + (PORT asdata (520:520:520) (575:575:575)) + (PORT ena (656:656:656) (712:712:712)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -24747,12 +22390,126 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~64) + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[0\]\~feeder) (DELAY (ABSOLUTE - (PORT dataa (131:131:131) (182:182:182)) - (PORT datab (541:541:541) (636:636:636)) - (PORT datad (470:470:470) (544:544:544)) + (PORT datad (798:798:798) (917:917:917)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (919:919:919)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (637:637:637) (680:680:680)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (389:389:389) (459:459:459)) + (PORT datab (388:388:388) (454:454:454)) + (PORT datad (117:117:117) (154:154:154)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (668:668:668) (742:742:742)) + (PORT ena (634:634:634) (686:686:686)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (478:478:478) (562:562:562)) + (PORT datab (617:617:617) (708:708:708)) + (PORT datad (290:290:290) (334:334:334)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (640:640:640) (739:739:739)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (919:919:919)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (417:417:417) (434:434:434)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (919:919:919)) + (PORT asdata (952:952:952) (1060:1060:1060)) + (PORT ena (435:435:435) (465:465:465)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (203:203:203) (265:265:265)) + (PORT datab (125:125:125) (157:157:157)) + (PORT datad (109:109:109) (129:129:129)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (190:190:190) (195:195:195)) @@ -24762,28 +22519,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[5\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[0\]) (DELAY (ABSOLUTE - (PORT clk (902:902:902) (908:908:908)) - (PORT asdata (359:359:359) (387:387:387)) - (PORT ena (781:781:781) (840:840:840)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (902:902:902) (908:908:908)) - (PORT asdata (359:359:359) (387:387:387)) - (PORT ena (662:662:662) (720:720:720)) + (PORT clk (907:907:907) (911:911:911)) + (PORT asdata (488:488:488) (537:537:537)) + (PORT ena (417:417:417) (434:434:434)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -24794,12 +22535,100 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~63) + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|db\[0\]\~0) (DELAY (ABSOLUTE - (PORT dataa (613:613:613) (704:704:704)) - (PORT datab (129:129:129) (176:176:176)) - (PORT datad (358:358:358) (416:416:416)) + (PORT dataa (492:492:492) (584:584:584)) + (PORT datab (354:354:354) (420:420:420)) + (PORT datad (353:353:353) (413:413:413)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (907:907:907) (911:911:911)) + (PORT asdata (488:488:488) (537:537:537)) + (PORT ena (505:505:505) (542:542:542)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (322:322:322) (383:383:383)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datad (124:124:124) (148:148:148)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (358:358:358) (413:413:413)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (644:644:644) (699:699:699)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (907:907:907) (912:912:912)) + (PORT asdata (833:833:833) (932:932:932)) + (PORT ena (655:655:655) (712:712:712)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (348:348:348) (418:418:418)) + (PORT datab (373:373:373) (453:453:453)) + (PORT datad (345:345:345) (405:405:405)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (167:167:167) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) @@ -24809,87 +22638,11 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[5\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[0\]) (DELAY (ABSOLUTE - (PORT clk (906:906:906) (910:910:910)) - (PORT asdata (764:764:764) (851:851:851)) - (PORT ena (794:794:794) (880:880:880)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (910:910:910)) - (PORT asdata (774:774:774) (864:864:864)) - (PORT ena (631:631:631) (680:680:680)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~66) - (DELAY - (ABSOLUTE - (PORT dataa (224:224:224) (284:284:284)) - (PORT datab (625:625:625) (718:718:718)) - (PORT datad (334:334:334) (382:382:382)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~67) - (DELAY - (ABSOLUTE - (PORT datab (492:492:492) (579:579:579)) - (PORT datad (171:171:171) (203:203:203)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (911:911:911) (918:918:918)) - (PORT asdata (638:638:638) (711:711:711)) - (PORT ena (422:422:422) (454:454:454)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (911:911:911) (918:918:918)) - (PORT asdata (637:637:637) (710:710:710)) + (PORT clk (907:907:907) (912:912:912)) + (PORT asdata (833:833:833) (931:931:931)) (PORT ena (669:669:669) (725:725:725)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -24901,94 +22654,22 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~65) + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[0\]\~feeder) (DELAY (ABSOLUTE - (PORT dataa (217:217:217) (273:273:273)) - (PORT datab (315:315:315) (374:374:374)) - (PORT datad (117:117:117) (154:154:154)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) + (PORT datad (102:102:102) (119:119:119)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[5\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[0\]) (DELAY (ABSOLUTE - (PORT clk (910:910:910) (918:918:918)) - (PORT asdata (789:789:789) (871:871:871)) - (PORT ena (644:644:644) (698:698:698)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[5\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (329:329:329) (377:377:377)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (910:910:910) (918:918:918)) + (PORT clk (906:906:906) (911:911:911)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (421:421:421) (449:449:449)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~69) - (DELAY - (ABSOLUTE - (PORT dataa (355:355:355) (426:426:426)) - (PORT datab (202:202:202) (245:245:245)) - (PORT datad (115:115:115) (152:152:152)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[5\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (461:461:461) (525:525:525)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (910:910:910)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (736:736:736) (793:793:793)) + (PORT ena (768:768:768) (845:845:845)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -24999,12 +22680,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[5\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[0\]) (DELAY (ABSOLUTE - (PORT clk (906:906:906) (910:910:910)) - (PORT asdata (774:774:774) (864:864:864)) - (PORT ena (660:660:660) (723:723:723)) + (PORT clk (907:907:907) (911:911:911)) + (PORT asdata (467:467:467) (511:511:511)) + (PORT ena (405:405:405) (422:422:422)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -25015,12 +22696,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~68) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~15) (DELAY (ABSOLUTE - (PORT dataa (300:300:300) (366:366:366)) - (PORT datab (441:441:441) (518:518:518)) - (PORT datad (347:347:347) (405:405:405)) + (PORT dataa (202:202:202) (263:263:263)) + (PORT datab (351:351:351) (420:420:420)) + (PORT datad (124:124:124) (150:150:150)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (190:190:190) (195:195:195)) @@ -25030,106 +22711,30 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~70) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~16) (DELAY (ABSOLUTE - (PORT dataa (343:343:343) (401:401:401)) - (PORT datab (609:609:609) (697:697:697)) - (PORT datac (172:172:172) (204:204:204)) - (PORT datad (320:320:320) (370:370:370)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~71) - (DELAY - (ABSOLUTE - (PORT dataa (189:189:189) (226:226:226)) - (PORT datac (89:89:89) (110:110:110)) - (PORT datad (93:93:93) (111:111:111)) + (PORT dataa (103:103:103) (133:133:133)) + (PORT datab (522:522:522) (613:613:613)) + (PORT datad (303:303:303) (350:350:350)) (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~72) - (DELAY - (ABSOLUTE - (PORT dataa (354:354:354) (419:419:419)) - (PORT datab (522:522:522) (603:603:603)) - (PORT datac (89:89:89) (111:111:111)) - (PORT datad (878:878:878) (998:998:998)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (650:650:650) (724:724:724)) - (PORT ena (636:636:636) (682:682:682)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[5\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (649:649:649) (740:740:740)) - (PORT datab (681:681:681) (798:798:798)) - (PORT datad (365:365:365) (428:428:428)) - (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (914:914:914) (922:922:922)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (419:419:419) (435:435:435)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[5\]\~17) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~17) (DELAY (ABSOLUTE - (PORT dataa (120:120:120) (153:153:153)) - (PORT datac (333:333:333) (385:385:385)) - (PORT datad (119:119:119) (157:157:157)) - (IOPATH dataa combout (158:158:158) (157:157:157)) + (PORT dataa (350:350:350) (410:410:410)) + (PORT datab (336:336:336) (393:393:393)) + (PORT datac (463:463:463) (529:529:529)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -25137,41 +22742,73 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[5\]\~18) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~22) (DELAY (ABSOLUTE - (PORT dataa (348:348:348) (404:404:404)) - (PORT datab (715:715:715) (816:816:816)) - (PORT datac (101:101:101) (121:121:121)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (159:159:159) (163:163:163)) + (PORT dataa (613:613:613) (710:710:710)) + (PORT datab (362:362:362) (421:421:421)) + (PORT datac (330:330:330) (386:386:386)) + (PORT datad (328:328:328) (383:383:383)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[5\]) + (INSTANCE z80_\|alu_control_\|db\[0\]\~9) (DELAY (ABSOLUTE - (PORT datac (358:358:358) (420:420:420)) - (PORT datad (437:437:437) (498:498:498)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (PORT dataa (177:177:177) (215:215:215)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (481:481:481) (560:560:560)) + (PORT datad (106:106:106) (123:123:123)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[0\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (480:480:480) (561:561:561)) + (PORT datab (476:476:476) (553:553:553)) + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (194:194:194) (226:226:226)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[8\]) + (DELAY + (ABSOLUTE + (PORT datac (478:478:478) (548:548:548)) + (PORT datad (522:522:522) (611:611:611)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[5\]) + (INSTANCE z80_\|address_latch_\|Q\[8\]) (DELAY (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) + (PORT clk (904:904:904) (908:908:908)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (920:920:920) (904:904:904)) - (PORT ena (1159:1159:1159) (1318:1318:1318)) + (PORT clrn (904:904:904) (891:891:891)) + (PORT ena (1032:1032:1032) (1123:1123:1123)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -25181,648 +22818,42 @@ (HOLD ena (posedge clk) (84:84:84)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_43\~4) - (DELAY - (ABSOLUTE - (PORT dataa (493:493:493) (588:588:588)) - (PORT datab (633:633:633) (729:729:729)) - (PORT datac (541:541:541) (633:633:633)) - (PORT datad (190:190:190) (221:221:221)) - (IOPATH dataa combout (181:181:181) (193:193:193)) - (IOPATH datab combout (182:182:182) (188:188:188)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[6\]) - (DELAY - (ABSOLUTE - (PORT dataa (354:354:354) (419:419:419)) - (PORT datab (640:640:640) (739:739:739)) - (PORT datac (422:422:422) (496:496:496)) - (PORT datad (332:332:332) (388:388:388)) - (IOPATH dataa combout (158:158:158) (173:173:173)) - (IOPATH datab combout (160:160:160) (176:176:176)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (920:920:920) (927:927:927)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (679:679:679) (746:746:746)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (902:902:902) (908:908:908)) - (PORT asdata (903:903:903) (1009:1009:1009)) - (PORT ena (915:915:915) (1002:1002:1002)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[6\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (724:724:724) (832:832:832)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (902:902:902) (908:908:908)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (756:756:756) (816:816:816)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~74) - (DELAY - (ABSOLUTE - (PORT dataa (486:486:486) (571:571:571)) - (PORT datab (538:538:538) (634:634:634)) - (PORT datad (118:118:118) (154:154:154)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (902:902:902) (908:908:908)) - (PORT asdata (1013:1013:1013) (1123:1123:1123)) - (PORT ena (781:781:781) (840:840:840)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (902:902:902) (908:908:908)) - (PORT asdata (1011:1011:1011) (1120:1120:1120)) - (PORT ena (662:662:662) (720:720:720)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~73) - (DELAY - (ABSOLUTE - (PORT dataa (611:611:611) (701:701:701)) - (PORT datab (130:130:130) (178:178:178)) - (PORT datad (354:354:354) (412:412:412)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (910:910:910) (917:917:917)) - (PORT asdata (1171:1171:1171) (1302:1302:1302)) - (PORT ena (649:649:649) (703:703:703)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[6\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (571:571:571) (650:650:650)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (910:910:910) (918:918:918)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (421:421:421) (449:449:449)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~78) - (DELAY - (ABSOLUTE - (PORT dataa (220:220:220) (266:266:266)) - (PORT datab (346:346:346) (409:409:409)) - (PORT datad (194:194:194) (242:242:242)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (764:764:764) (834:834:834)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~79) - (DELAY - (ABSOLUTE - (PORT dataa (376:376:376) (456:456:456)) - (PORT datab (525:525:525) (610:610:610)) - (PORT datac (479:479:479) (549:549:549)) - (PORT datad (332:332:332) (386:386:386)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (910:910:910) (917:917:917)) - (PORT asdata (1171:1171:1171) (1301:1301:1301)) - (PORT ena (812:812:812) (885:885:885)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[6\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (703:703:703) (802:802:802)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (910:910:910)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (660:660:660) (723:723:723)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (910:910:910)) - (PORT asdata (875:875:875) (968:968:968)) - (PORT ena (631:631:631) (680:680:680)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~76) - (DELAY - (ABSOLUTE - (PORT dataa (230:230:230) (292:292:292)) - (PORT datab (129:129:129) (176:176:176)) - (PORT datad (345:345:345) (403:403:403)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~77) - (DELAY - (ABSOLUTE - (PORT datab (767:767:767) (883:883:883)) - (PORT datad (302:302:302) (347:347:347)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~80) - (DELAY - (ABSOLUTE - (PORT datab (102:102:102) (131:131:131)) - (PORT datac (89:89:89) (110:110:110)) - (PORT datad (89:89:89) (107:107:107)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (911:911:911) (918:918:918)) - (PORT asdata (724:724:724) (793:793:793)) - (PORT ena (422:422:422) (454:454:454)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT asdata (788:788:788) (871:871:871)) - (PORT ena (433:433:433) (461:461:461)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~75) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (277:277:277)) - (PORT datab (305:305:305) (362:362:362)) - (PORT datad (454:454:454) (533:533:533)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~81) - (DELAY - (ABSOLUTE - (PORT dataa (190:190:190) (227:227:227)) - (PORT datab (103:103:103) (131:131:131)) - (PORT datac (422:422:422) (480:480:480)) - (PORT datad (410:410:410) (465:465:465)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~82) - (DELAY - (ABSOLUTE - (PORT dataa (326:326:326) (386:386:386)) - (PORT datab (367:367:367) (432:432:432)) - (PORT datac (747:747:747) (864:864:864)) - (PORT datad (309:309:309) (352:352:352)) - (IOPATH dataa combout (165:165:165) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (527:527:527) (588:588:588)) - (PORT ena (636:636:636) (682:682:682)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (736:736:736) (841:841:841)) - (PORT datab (676:676:676) (792:792:792)) - (PORT datad (362:362:362) (425:425:425)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~20) - (DELAY - (ABSOLUTE - (PORT datab (369:369:369) (432:432:432)) - (PORT datac (372:372:372) (446:446:446)) - (PORT datad (89:89:89) (107:107:107)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (392:392:392) (472:472:472)) - (PORT datab (352:352:352) (417:417:417)) - (PORT datac (511:511:511) (598:598:598)) - (PORT datad (335:335:335) (391:391:391)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[6\]) - (DELAY - (ABSOLUTE - (PORT datac (359:359:359) (421:421:421)) - (PORT datad (442:442:442) (510:510:510)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (920:920:920) (904:904:904)) - (PORT ena (1159:1159:1159) (1318:1318:1318)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_47\~0) - (DELAY - (ABSOLUTE - (PORT dataa (344:344:344) (407:407:407)) - (PORT datab (346:346:346) (408:408:408)) - (PORT datac (422:422:422) (497:497:497)) - (PORT datad (625:625:625) (721:721:721)) - (IOPATH dataa combout (192:192:192) (184:184:184)) - (IOPATH datab combout (191:191:191) (188:188:188)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_47) - (DELAY - (ABSOLUTE - (PORT dataa (102:102:102) (133:133:133)) - (PORT datab (636:636:636) (735:735:735)) - (PORT datac (341:341:341) (397:397:397)) - (PORT datad (333:333:333) (389:389:389)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|d0_out) (DELAY (ABSOLUTE - (PORT dataa (227:227:227) (295:295:295)) - (PORT datad (101:101:101) (122:122:122)) - (IOPATH dataa combout (186:186:186) (180:180:180)) + (PORT datac (339:339:339) (402:402:402)) + (PORT datad (308:308:308) (366:366:366)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (388:388:388) (467:467:467)) - (PORT datab (529:529:529) (620:620:620)) - (PORT datac (89:89:89) (110:110:110)) - (PORT datad (337:337:337) (390:390:390)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (902:902:902) (908:908:908)) - (PORT asdata (644:644:644) (723:723:723)) - (PORT ena (781:781:781) (840:840:840)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (902:902:902) (908:908:908)) - (PORT asdata (643:643:643) (722:722:722)) - (PORT ena (662:662:662) (720:720:720)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~83) - (DELAY - (ABSOLUTE - (PORT dataa (612:612:612) (702:702:702)) - (PORT datab (130:130:130) (179:179:179)) - (PORT datad (355:355:355) (414:414:414)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (902:902:902) (908:908:908)) - (PORT asdata (761:761:761) (847:847:847)) - (PORT ena (915:915:915) (1002:1002:1002)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (902:902:902) (908:908:908)) - (PORT asdata (762:762:762) (848:848:848)) - (PORT ena (756:756:756) (816:816:816)) + (PORT clk (907:907:907) (912:912:912)) + (PORT asdata (487:487:487) (530:530:530)) + (PORT ena (501:501:501) (530:530:530)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (907:907:907) (912:912:912)) + (PORT asdata (488:488:488) (531:531:531)) + (PORT ena (518:518:518) (557:557:557)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -25836,50 +22867,34 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~84) (DELAY (ABSOLUTE - (PORT dataa (489:489:489) (574:574:574)) - (PORT datab (534:534:534) (629:629:629)) - (PORT datad (117:117:117) (153:153:153)) + (PORT dataa (196:196:196) (239:239:239)) + (PORT datab (130:130:130) (178:178:178)) + (PORT datad (190:190:190) (223:223:223)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (910:910:910) (917:917:917)) - (PORT asdata (1049:1049:1049) (1178:1178:1178)) - (PORT ena (649:649:649) (703:703:703)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[7\]\~feeder) + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[7\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (880:880:880) (1011:1011:1011)) + (PORT datad (625:625:625) (717:717:717)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[7\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (910:910:910) (918:918:918)) + (PORT clk (911:911:911) (919:919:919)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (421:421:421) (449:449:449)) + (PORT ena (417:417:417) (434:434:434)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -25888,29 +22903,14 @@ (HOLD ena (posedge clk) (84:84:84)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~88) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (268:268:268)) - (PORT datab (348:348:348) (411:411:411)) - (PORT datad (193:193:193) (240:240:240)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[7\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (910:910:910) (917:917:917)) - (PORT asdata (1047:1047:1047) (1177:1177:1177)) - (PORT ena (812:812:812) (885:885:885)) + (PORT clk (911:911:911) (919:919:919)) + (PORT asdata (644:644:644) (715:715:715)) + (PORT ena (435:435:435) (465:465:465)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -25919,14 +22919,60 @@ (HOLD ena (posedge clk) (84:84:84)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~83) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (258:258:258)) + (PORT datab (124:124:124) (155:155:155)) + (PORT datad (112:112:112) (133:133:133)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (911:911:911)) + (PORT asdata (280:280:280) (299:299:299)) + (PORT ena (768:768:768) (845:845:845)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~88) + (DELAY + (ABSOLUTE + (PORT dataa (383:383:383) (459:459:459)) + (PORT datab (464:464:464) (535:535:535)) + (PORT datad (724:724:724) (818:818:818)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (906:906:906) (910:910:910)) - (PORT asdata (1058:1058:1058) (1183:1183:1183)) - (PORT ena (660:660:660) (723:723:723)) + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (640:640:640) (708:708:708)) + (PORT ena (644:644:644) (699:699:699)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -25940,9 +22986,9 @@ (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (906:906:906) (910:910:910)) - (PORT asdata (1057:1057:1057) (1183:1183:1183)) - (PORT ena (631:631:631) (680:680:680)) + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (639:639:639) (708:708:708)) + (PORT ena (634:634:634) (686:686:686)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -25956,9 +23002,9 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~86) (DELAY (ABSOLUTE - (PORT dataa (225:225:225) (285:285:285)) + (PORT dataa (474:474:474) (557:557:557)) (PORT datab (129:129:129) (176:176:176)) - (PORT datad (347:347:347) (405:405:405)) + (PORT datad (369:369:369) (440:440:440)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (167:167:167) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) @@ -25966,27 +23012,108 @@ ) ) ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (907:907:907) (911:911:911)) + (PORT asdata (493:493:493) (539:539:539)) + (PORT ena (405:405:405) (422:422:422)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (907:907:907) (911:911:911)) + (PORT asdata (493:493:493) (539:539:539)) + (PORT ena (677:677:677) (748:748:748)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~87) (DELAY (ABSOLUTE - (PORT datab (768:768:768) (884:884:884)) - (PORT datad (312:312:312) (360:360:360)) + (PORT dataa (375:375:375) (453:453:453)) + (PORT datab (129:129:129) (176:176:176)) + (PORT datad (126:126:126) (150:150:150)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) + (PORT asdata (522:522:522) (566:566:566)) + (PORT ena (435:435:435) (462:462:462)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|db\[7\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (646:646:646) (742:742:742)) + (PORT datab (495:495:495) (569:569:569)) + (PORT datad (525:525:525) (604:604:604)) + (IOPATH dataa combout (158:158:158) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~89) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (397:397:397)) + (PORT datab (493:493:493) (566:566:566)) + (PORT datac (312:312:312) (354:354:354)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (911:911:911) (918:918:918)) - (PORT asdata (942:942:942) (1061:1061:1061)) - (PORT ena (422:422:422) (454:454:454)) + (PORT clk (911:911:911) (919:919:919)) + (PORT asdata (652:652:652) (720:720:720)) + (PORT ena (656:656:656) (712:712:712)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -26000,9 +23127,9 @@ (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (911:911:911) (918:918:918)) - (PORT asdata (941:941:941) (1060:1060:1060)) - (PORT ena (669:669:669) (725:725:725)) + (PORT clk (911:911:911) (919:919:919)) + (PORT asdata (647:647:647) (714:714:714)) + (PORT ena (637:637:637) (680:680:680)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -26016,9 +23143,9 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~85) (DELAY (ABSOLUTE - (PORT dataa (218:218:218) (274:274:274)) - (PORT datab (313:313:313) (371:371:371)) - (PORT datad (117:117:117) (153:153:153)) + (PORT dataa (380:380:380) (449:449:449)) + (PORT datab (384:384:384) (449:449:449)) + (PORT datad (119:119:119) (156:156:156)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (190:190:190) (195:195:195)) @@ -26026,47 +23153,15 @@ ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (764:764:764) (834:834:834)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~89) - (DELAY - (ABSOLUTE - (PORT dataa (356:356:356) (437:437:437)) - (PORT datab (525:525:525) (610:610:610)) - (PORT datac (444:444:444) (513:513:513)) - (PORT datad (330:330:330) (383:383:383)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~90) (DELAY (ABSOLUTE - (PORT dataa (103:103:103) (133:133:133)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datac (260:260:260) (292:292:292)) - (PORT datad (92:92:92) (110:110:110)) + (PORT dataa (104:104:104) (136:136:136)) + (PORT datab (345:345:345) (410:410:410)) + (PORT datac (415:415:415) (470:470:470)) + (PORT datad (417:417:417) (479:479:479)) (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -26079,56 +23174,125 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~91) (DELAY (ABSOLUTE - (PORT dataa (105:105:105) (136:136:136)) - (PORT datab (183:183:183) (219:219:219)) - (PORT datad (306:306:306) (353:353:353)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~92) - (DELAY - (ABSOLUTE - (PORT dataa (371:371:371) (437:437:437)) - (PORT datab (358:358:358) (423:423:423)) - (PORT datac (746:746:746) (863:863:863)) - (PORT datad (310:310:310) (353:353:353)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (166:166:166) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_ds\[7\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (830:830:830) (963:963:963)) - (PORT datab (929:929:929) (1057:1057:1057)) - (PORT datac (467:467:467) (549:549:549)) - (PORT datad (646:646:646) (745:745:745)) + (PORT dataa (306:306:306) (355:355:355)) + (PORT datab (361:361:361) (421:421:421)) + (PORT datac (596:596:596) (688:688:688)) + (PORT datad (327:327:327) (378:378:378)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|im2) + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[7\]) (DELAY (ABSOLUTE - (PORT clk (906:906:906) (914:914:914)) + (PORT clk (902:902:902) (907:907:907)) + (PORT asdata (355:355:355) (390:390:390)) + (PORT ena (418:418:418) (434:434:434)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (358:358:358) (413:413:413)) + (PORT datab (115:115:115) (144:144:144)) + (PORT datad (578:578:578) (650:650:650)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (901:901:901) (906:906:906)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (911:911:911) (895:895:895)) - (PORT ena (667:667:667) (732:732:732)) + (PORT ena (505:505:505) (549:549:549)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (173:173:173) (209:209:209)) + (PORT datac (173:173:173) (205:205:205)) + (PORT datad (117:117:117) (154:154:154)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (438:438:438) (504:504:504)) + (PORT datab (102:102:102) (131:131:131)) + (PORT datac (287:287:287) (329:329:329)) + (PORT datad (1017:1017:1017) (1139:1139:1139)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[7\]) + (DELAY + (ABSOLUTE + (PORT dataa (321:321:321) (379:379:379)) + (PORT datac (447:447:447) (519:519:519)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|Q\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (103:103:103) (120:120:120)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (909:909:909)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (905:905:905) (891:891:891)) + (PORT ena (904:904:904) (977:977:977)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -26140,122 +23304,397 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~12) + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|d1_out) (DELAY (ABSOLUTE - (PORT dataa (206:206:206) (284:284:284)) - (PORT datac (681:681:681) (805:805:805)) - (PORT datad (150:150:150) (194:194:194)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_mask543_en\~0) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (286:286:286)) - (PORT datab (382:382:382) (455:455:455)) - (PORT datac (100:100:100) (121:121:121)) - (PORT datad (733:733:733) (870:870:870)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[7\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (473:473:473) (545:545:545)) - (PORT datab (493:493:493) (571:571:571)) - (PORT datac (347:347:347) (410:410:410)) - (PORT datad (343:343:343) (394:394:394)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (PORT dataa (475:475:475) (557:557:557)) + (PORT datab (538:538:538) (632:632:632)) + (PORT datac (358:358:358) (429:429:429)) + (PORT datad (308:308:308) (366:366:366)) + (IOPATH dataa combout (188:188:188) (179:179:179)) + (IOPATH datab combout (196:196:196) (205:205:205)) (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[7\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (449:449:449) (521:521:521)) - (PORT datab (460:460:460) (533:533:533)) - (PORT datac (491:491:491) (567:567:567)) - (PORT datad (352:352:352) (423:423:423)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[7\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (136:136:136)) - (PORT datab (131:131:131) (166:166:166)) - (PORT datac (354:354:354) (422:422:422)) - (PORT datad (328:328:328) (381:381:381)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_34) - (DELAY - (ABSOLUTE - (PORT dataa (378:378:378) (444:444:444)) - (PORT datab (499:499:499) (575:575:575)) - (PORT datac (461:461:461) (530:530:530)) - (PORT datad (107:107:107) (125:125:125)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (739:739:739) (872:872:872)) - (PORT datab (486:486:486) (575:575:575)) - (PORT datac (333:333:333) (392:392:392)) - (PORT datad (102:102:102) (119:119:119)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_sf) + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[0\]) (DELAY (ABSOLUTE - (PORT clk (896:896:896) (901:901:901)) + (PORT clk (904:904:904) (909:909:909)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (435:435:435) (466:466:466)) + (PORT ena (672:672:672) (745:745:745)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (909:909:909)) + (PORT asdata (775:775:775) (858:858:858)) + (PORT ena (649:649:649) (706:706:706)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (433:433:433)) + (PORT datab (359:359:359) (421:421:421)) + (PORT datad (321:321:321) (372:372:372)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT datab (573:573:573) (664:664:664)) + (PORT datac (119:119:119) (160:160:160)) + (PORT datad (93:93:93) (111:111:111)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (352:352:352) (409:409:409)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (306:306:306) (355:355:355)) + (PORT datad (745:745:745) (838:838:838)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) + (PORT asdata (619:619:619) (682:682:682)) + (PORT ena (422:422:422) (449:449:449)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) + (PORT asdata (621:621:621) (683:683:683)) + (PORT ena (649:649:649) (705:705:705)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (384:384:384) (460:460:460)) + (PORT datab (141:141:141) (178:178:178)) + (PORT datad (118:118:118) (155:155:155)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (905:905:905) (910:910:910)) + (PORT asdata (1031:1031:1031) (1163:1163:1163)) + (PORT ena (604:604:604) (647:647:647)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (909:909:909)) + (PORT asdata (1031:1031:1031) (1164:1164:1164)) + (PORT ena (645:645:645) (695:695:695)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (366:366:366) (436:436:436)) + (PORT datab (146:146:146) (184:184:184)) + (PORT datad (200:200:200) (251:251:251)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (909:909:909)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (655:655:655) (714:714:714)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (909:909:909)) + (PORT asdata (456:456:456) (495:495:495)) + (PORT ena (800:800:800) (878:878:878)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (394:394:394) (471:471:471)) + (PORT datab (309:309:309) (377:377:377)) + (PORT datad (378:378:378) (444:444:444)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) + (PORT asdata (923:923:923) (1058:1058:1058)) + (PORT ena (757:757:757) (811:811:811)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) + (PORT asdata (923:923:923) (1057:1057:1057)) + (PORT ena (648:648:648) (700:700:700)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (384:384:384) (456:456:456)) + (PORT datab (342:342:342) (401:401:401)) + (PORT datad (116:116:116) (153:153:153)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (909:909:909)) + (PORT asdata (1034:1034:1034) (1168:1168:1168)) + (PORT ena (619:619:619) (671:671:671)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (642:642:642) (756:756:756)) + (PORT datab (492:492:492) (575:575:575)) + (PORT datad (213:213:213) (260:260:260)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (323:323:323) (382:382:382)) + (PORT datab (192:192:192) (232:232:232)) + (PORT datac (475:475:475) (544:544:544)) + (PORT datad (323:323:323) (378:378:378)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (1010:1010:1010) (1142:1142:1142)) + (PORT ena (406:406:406) (423:423:423)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[0\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (838:838:838) (988:988:988)) + (PORT datab (1228:1228:1228) (1417:1417:1417)) + (PORT datad (731:731:731) (822:822:822)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) + (PORT asdata (996:996:996) (1122:1122:1122)) + (PORT ena (501:501:501) (541:541:541)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (695:695:695) (809:809:809)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (621:621:621) (666:666:666)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -26266,13 +23705,28 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal62\~3) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~22) (DELAY (ABSOLUTE - (PORT dataa (830:830:830) (973:973:973)) - (PORT datab (820:820:820) (963:963:963)) - (PORT datac (607:607:607) (704:704:704)) - (PORT datad (358:358:358) (409:409:409)) + (PORT dataa (350:350:350) (425:425:425)) + (PORT datab (370:370:370) (434:434:434)) + (PORT datad (117:117:117) (154:154:154)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (487:487:487) (575:575:575)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (319:319:319) (374:374:374)) + (PORT datad (323:323:323) (372:372:372)) (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -26282,13 +23736,147 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~5) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~30) (DELAY (ABSOLUTE - (PORT dataa (614:614:614) (712:712:712)) - (PORT datab (401:401:401) (473:473:473)) - (PORT datac (779:779:779) (893:893:893)) - (PORT datad (669:669:669) (779:779:779)) + (PORT dataa (335:335:335) (405:405:405)) + (PORT datab (186:186:186) (222:222:222)) + (PORT datac (621:621:621) (722:722:722)) + (PORT datad (479:479:479) (552:552:552)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[0\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (331:331:331) (401:401:401)) + (PORT datab (358:358:358) (424:424:424)) + (PORT datac (441:441:441) (502:502:502)) + (PORT datad (365:365:365) (445:445:445)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[0\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (461:461:461) (540:540:540)) + (PORT datab (139:139:139) (182:182:182)) + (PORT datac (309:309:309) (361:361:361)) + (PORT datad (92:92:92) (109:109:109)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (476:476:476) (558:558:558)) + (PORT datab (452:452:452) (531:531:531)) + (PORT datad (638:638:638) (762:762:762)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (447:447:447) (530:530:530)) + (PORT datab (703:703:703) (798:798:798)) + (PORT datad (89:89:89) (106:106:106)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (133:133:133) (171:171:171)) + (PORT datab (307:307:307) (376:376:376)) + (PORT datac (311:311:311) (347:347:347)) + (PORT datad (475:475:475) (560:560:560)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (158:158:158) (208:208:208)) + (PORT datab (151:151:151) (193:193:193)) + (PORT datac (611:611:611) (702:702:702)) + (PORT datad (129:129:129) (158:158:158)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|result_lo\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (105:105:105) (122:122:122)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|result_lo\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (914:914:914) (919:919:919)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (922:922:922) (1022:1022:1022)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (137:137:137)) + (PORT datab (422:422:422) (490:490:490)) + (PORT datac (281:281:281) (322:322:322)) + (PORT datad (197:197:197) (248:248:248)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -26298,13 +23886,2112 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~6) + (INSTANCE z80_\|alu_\|db_low\[1\]\~12) (DELAY (ABSOLUTE - (PORT dataa (502:502:502) (599:599:599)) - (PORT datab (647:647:647) (748:748:748)) - (PORT datac (404:404:404) (501:501:501)) - (PORT datad (1079:1079:1079) (1263:1263:1263)) + (PORT dataa (191:191:191) (228:228:228)) + (PORT datab (380:380:380) (455:455:455)) + (PORT datac (383:383:383) (449:449:449)) + (PORT datad (329:329:329) (376:376:376)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[1\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (332:332:332) (403:403:403)) + (PORT datab (323:323:323) (380:380:380)) + (PORT datac (341:341:341) (401:401:401)) + (PORT datad (629:629:629) (717:717:717)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (389:389:389) (474:474:474)) + (PORT datab (138:138:138) (180:180:180)) + (PORT datac (460:460:460) (520:520:520)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (909:909:909)) + (PORT asdata (751:751:751) (841:841:841)) + (PORT ena (619:619:619) (671:671:671)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (640:640:640) (753:753:753)) + (PORT datab (808:808:808) (924:924:924)) + (PORT datad (207:207:207) (254:254:254)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (466:466:466) (540:540:540)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (905:905:905) (910:910:910)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (604:604:604) (647:647:647)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (909:909:909)) + (PORT asdata (752:752:752) (842:842:842)) + (PORT ena (645:645:645) (695:695:695)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (313:313:313) (372:372:372)) + (PORT datab (195:195:195) (251:251:251)) + (PORT datad (179:179:179) (203:203:203)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) + (PORT asdata (767:767:767) (860:860:860)) + (PORT ena (648:648:648) (700:700:700)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) + (PORT asdata (767:767:767) (859:859:859)) + (PORT ena (757:757:757) (811:811:811)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (383:383:383) (455:455:455)) + (PORT datab (347:347:347) (406:406:406)) + (PORT datad (117:117:117) (154:154:154)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (909:909:909)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (800:800:800) (878:878:878)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (909:909:909)) + (PORT asdata (364:364:364) (401:401:401)) + (PORT ena (655:655:655) (714:714:714)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (398:398:398) (476:476:476)) + (PORT datab (128:128:128) (176:176:176)) + (PORT datad (375:375:375) (441:441:441)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (136:136:136)) + (PORT datab (105:105:105) (135:135:135)) + (PORT datac (335:335:335) (392:392:392)) + (PORT datad (280:280:280) (322:322:322)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (468:468:468) (510:510:510)) + (PORT ena (406:406:406) (423:423:423)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (840:840:840) (990:990:990)) + (PORT datab (1226:1226:1226) (1415:1415:1415)) + (PORT datad (732:732:732) (822:822:822)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) + (PORT asdata (811:811:811) (906:906:906)) + (PORT ena (649:649:649) (705:705:705)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) + (PORT asdata (807:807:807) (902:902:902)) + (PORT ena (422:422:422) (449:449:449)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (387:387:387) (464:464:464)) + (PORT datab (131:131:131) (180:180:180)) + (PORT datad (122:122:122) (147:147:147)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) + (PORT asdata (811:811:811) (909:909:909)) + (PORT ena (501:501:501) (541:541:541)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (317:317:317) (366:366:366)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (621:621:621) (666:666:666)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (349:349:349) (423:423:423)) + (PORT datab (370:370:370) (433:433:433)) + (PORT datad (118:118:118) (155:155:155)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (334:334:334) (391:391:391)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (319:319:319) (375:375:375)) + (PORT datad (162:162:162) (191:191:191)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (645:645:645) (746:746:746)) + (PORT datab (190:190:190) (228:228:228)) + (PORT datac (442:442:442) (510:510:510)) + (PORT datad (480:480:480) (553:553:553)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (909:909:909)) + (PORT asdata (439:439:439) (475:475:475)) + (PORT ena (766:766:766) (830:830:830)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (369:369:369) (441:441:441)) + (PORT datab (379:379:379) (454:454:454)) + (PORT datad (346:346:346) (407:407:407)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (131:131:131) (182:182:182)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datad (348:348:348) (410:410:410)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (617:617:617) (714:714:714)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (759:759:759) (856:856:856)) + (PORT datad (119:119:119) (143:143:143)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[9\]) + (DELAY + (ABSOLUTE + (PORT datac (494:494:494) (569:569:569)) + (PORT datad (520:520:520) (608:608:608)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|Q\[9\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (93:93:93) (111:111:111)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (904:904:904) (891:891:891)) + (PORT ena (1032:1032:1032) (1123:1123:1123)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[10\]) + (DELAY + (ABSOLUTE + (PORT dataa (329:329:329) (389:389:389)) + (PORT datad (318:318:318) (370:370:370)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (904:904:904) (891:891:891)) + (PORT ena (1014:1014:1014) (1102:1102:1102)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|d1_out) + (DELAY + (ABSOLUTE + (PORT dataa (114:114:114) (150:150:150)) + (PORT datab (377:377:377) (448:448:448)) + (PORT datac (525:525:525) (616:616:616)) + (PORT datad (220:220:220) (273:273:273)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH datab combout (190:190:190) (205:205:205)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (909:909:909)) + (PORT asdata (345:345:345) (380:380:380)) + (PORT ena (766:766:766) (830:830:830)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (471:471:471) (551:551:551)) + (PORT datab (381:381:381) (456:456:456)) + (PORT datad (350:350:350) (411:411:411)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (909:909:909)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (665:665:665) (730:730:730)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (133:133:133)) + (PORT datab (367:367:367) (435:435:435)) + (PORT datad (118:118:118) (155:155:155)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (335:335:335) (403:403:403)) + (PORT datab (772:772:772) (876:876:876)) + (PORT datac (89:89:89) (111:111:111)) + (PORT datad (117:117:117) (142:142:142)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (644:644:644) (745:745:745)) + (PORT datab (295:295:295) (345:345:345)) + (PORT datac (329:329:329) (389:389:389)) + (PORT datad (479:479:479) (552:552:552)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[2\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (321:321:321) (373:373:373)) + (PORT datab (335:335:335) (393:393:393)) + (PORT datac (276:276:276) (317:317:317)) + (PORT datad (325:325:325) (378:378:378)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[2\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (386:386:386) (471:471:471)) + (PORT datab (293:293:293) (343:343:343)) + (PORT datac (117:117:117) (153:153:153)) + (PORT datad (340:340:340) (395:395:395)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[2\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (347:347:347) (409:409:409)) + (PORT datab (464:464:464) (547:547:547)) + (PORT datac (191:191:191) (231:231:231)) + (PORT datad (455:455:455) (528:528:528)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~2) + (DELAY + (ABSOLUTE + (PORT datab (124:124:124) (156:156:156)) + (PORT datac (425:425:425) (487:487:487)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|flags_hf2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (214:214:214) (251:251:251)) + (PORT datab (105:105:105) (134:134:134)) + (PORT datad (364:364:364) (424:424:424)) + (IOPATH dataa combout (188:188:188) (184:184:184)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|flags_hf2) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (919:919:919)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[2\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (628:628:628) (715:715:715)) + (PORT datab (393:393:393) (479:479:479)) + (PORT datac (470:470:470) (546:546:546)) + (PORT datad (99:99:99) (120:120:120)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[2\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (175:175:175) (214:214:214)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (306:306:306) (357:357:357)) + (PORT datad (111:111:111) (134:134:134)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (444:444:444) (525:525:525)) + (PORT datab (316:316:316) (382:382:382)) + (PORT datac (181:181:181) (217:217:217)) + (PORT datad (334:334:334) (391:391:391)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (919:919:919)) + (PORT asdata (654:654:654) (718:718:718)) + (PORT ena (656:656:656) (712:712:712)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (919:919:919)) + (PORT asdata (649:649:649) (713:713:713)) + (PORT ena (637:637:637) (680:680:680)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (388:388:388) (458:458:458)) + (PORT datab (388:388:388) (453:453:453)) + (PORT datad (118:118:118) (155:155:155)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (195:195:195) (235:235:235)) + (PORT datab (172:172:172) (209:209:209)) + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (340:340:340) (399:399:399)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~41) + (DELAY + (ABSOLUTE + (PORT dataa (270:270:270) (316:316:316)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datad (326:326:326) (381:381:381)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (614:614:614) (712:712:712)) + (PORT datab (323:323:323) (372:372:372)) + (PORT datac (345:345:345) (400:400:400)) + (PORT datad (344:344:344) (399:399:399)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (279:279:279) (299:299:299)) + (PORT ena (621:621:621) (659:659:659)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (495:495:495) (573:573:573)) + (PORT datab (378:378:378) (430:430:430)) + (PORT datad (210:210:210) (255:255:255)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (260:260:260)) + (PORT datac (89:89:89) (109:109:109)) + (PORT datad (315:315:315) (366:366:366)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_41) + (DELAY + (ABSOLUTE + (PORT dataa (1019:1019:1019) (1195:1195:1195)) + (PORT datab (209:209:209) (262:262:262)) + (PORT datac (711:711:711) (801:801:801)) + (PORT datad (107:107:107) (132:132:132)) + (IOPATH dataa combout (188:188:188) (179:179:179)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|SYNTHESIZED_WIRE_0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (863:863:863) (1009:1009:1009)) + (PORT datab (833:833:833) (971:971:971)) + (PORT datac (862:862:862) (961:961:961)) + (PORT datad (173:173:173) (206:206:206)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|d0_out) + (DELAY + (ABSOLUTE + (PORT dataa (526:526:526) (625:625:625)) + (PORT datac (196:196:196) (232:232:232)) + (PORT datad (98:98:98) (121:121:121)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (133:133:133)) + (PORT datab (197:197:197) (242:242:242)) + (PORT datac (908:908:908) (1029:1029:1029)) + (PORT datad (318:318:318) (370:370:370)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[2\]) + (DELAY + (ABSOLUTE + (PORT datac (499:499:499) (586:586:586)) + (PORT datad (332:332:332) (381:381:381)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (915:915:915)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (911:911:911) (895:895:895)) + (PORT ena (1070:1070:1070) (1171:1171:1171)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_42) + (DELAY + (ABSOLUTE + (PORT dataa (1000:1000:1000) (1161:1161:1161)) + (PORT datab (778:778:778) (900:900:900)) + (PORT datac (112:112:112) (143:143:143)) + (PORT datad (1052:1052:1052) (1228:1228:1228)) + (IOPATH dataa combout (158:158:158) (165:165:165)) + (IOPATH datab combout (160:160:160) (176:176:176)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (278:278:278) (298:298:298)) + (PORT ena (621:621:621) (659:659:659)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (496:496:496) (573:573:573)) + (PORT datab (610:610:610) (695:695:695)) + (PORT datad (213:213:213) (258:258:258)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (633:633:633) (693:693:693)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (333:333:333) (396:396:396)) + (PORT datab (101:101:101) (129:129:129)) + (PORT datad (189:189:189) (235:235:235)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|d1_out) + (DELAY + (ABSOLUTE + (PORT dataa (115:115:115) (150:150:150)) + (PORT datab (345:345:345) (413:413:413)) + (PORT datac (190:190:190) (225:225:225)) + (PORT datad (94:94:94) (113:113:113)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (191:191:191) (181:181:181)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (923:923:923) (1051:1051:1051)) + (PORT datab (101:101:101) (129:129:129)) + (PORT datac (324:324:324) (380:380:380)) + (PORT datad (178:178:178) (212:212:212)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[3\]) + (DELAY + (ABSOLUTE + (PORT datab (517:517:517) (605:605:605)) + (PORT datac (284:284:284) (323:323:323)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (915:915:915)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (911:911:911) (895:895:895)) + (PORT ena (1070:1070:1070) (1171:1171:1171)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_45\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1076:1076:1076) (1257:1257:1257)) + (PORT datab (345:345:345) (412:412:412)) + (PORT datac (111:111:111) (142:142:142)) + (PORT datad (988:988:988) (1136:1136:1136)) + (IOPATH dataa combout (158:158:158) (165:165:165)) + (IOPATH datab combout (160:160:160) (176:176:176)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|carry_borrow_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (112:112:112) (147:147:147)) + (PORT datab (107:107:107) (137:137:137)) + (PORT datac (193:193:193) (229:229:229)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_47\~0) + (DELAY + (ABSOLUTE + (PORT dataa (528:528:528) (618:618:618)) + (PORT datab (116:116:116) (151:151:151)) + (PORT datac (112:112:112) (144:144:144)) + (PORT datad (724:724:724) (820:820:820)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (196:196:196) (192:192:192)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_47) + (DELAY + (ABSOLUTE + (PORT dataa (120:120:120) (152:152:152)) + (PORT datab (107:107:107) (138:138:138)) + (PORT datac (96:96:96) (120:120:120)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|carry_borrow_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (478:478:478) (560:560:560)) + (PORT datab (539:539:539) (633:633:633)) + (PORT datac (360:360:360) (431:431:431)) + (PORT datad (307:307:307) (365:365:365)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (176:176:176)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|carry_borrow_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (112:112:112) (146:146:146)) + (PORT datab (379:379:379) (451:451:451)) + (PORT datac (522:522:522) (614:614:614)) + (PORT datad (216:216:216) (269:269:269)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[11\]) + (DELAY + (ABSOLUTE + (PORT datac (133:133:133) (176:176:176)) + (PORT datad (98:98:98) (120:120:120)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (128:128:128) (164:164:164)) + (PORT datab (769:769:769) (872:872:872)) + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (327:327:327) (379:379:379)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) + (PORT asdata (633:633:633) (695:695:695)) + (PORT ena (649:649:649) (705:705:705)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) + (PORT asdata (632:632:632) (694:694:694)) + (PORT ena (422:422:422) (449:449:449)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~41) + (DELAY + (ABSOLUTE + (PORT dataa (384:384:384) (459:459:459)) + (PORT datab (130:130:130) (178:178:178)) + (PORT datad (129:129:129) (157:157:157)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (909:909:909)) + (PORT asdata (359:359:359) (388:388:388)) + (PORT ena (655:655:655) (714:714:714)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (909:909:909)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (800:800:800) (878:878:878)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~45) + (DELAY + (ABSOLUTE + (PORT dataa (396:396:396) (474:474:474)) + (PORT datab (343:343:343) (394:394:394)) + (PORT datad (116:116:116) (153:153:153)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (909:909:909)) + (PORT asdata (530:530:530) (588:588:588)) + (PORT ena (619:619:619) (671:671:671)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~44) + (DELAY + (ABSOLUTE + (PORT dataa (641:641:641) (755:755:755)) + (PORT datab (501:501:501) (577:577:577)) + (PORT datad (211:211:211) (259:259:259)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (905:905:905) (910:910:910)) + (PORT asdata (527:527:527) (586:586:586)) + (PORT ena (649:649:649) (707:707:707)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (905:905:905) (910:910:910)) + (PORT asdata (525:525:525) (585:585:585)) + (PORT ena (604:604:604) (647:647:647)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~43) + (DELAY + (ABSOLUTE + (PORT dataa (366:366:366) (435:435:435)) + (PORT datab (144:144:144) (183:183:183)) + (PORT datad (186:186:186) (231:231:231)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) + (PORT asdata (654:654:654) (724:724:724)) + (PORT ena (757:757:757) (811:811:811)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) + (PORT asdata (654:654:654) (723:723:723)) + (PORT ena (648:648:648) (700:700:700)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (382:382:382) (454:454:454)) + (PORT datab (129:129:129) (176:176:176)) + (PORT datad (328:328:328) (380:380:380)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (330:330:330) (396:396:396)) + (PORT datab (170:170:170) (207:207:207)) + (PORT datac (274:274:274) (310:310:310)) + (PORT datad (164:164:164) (194:194:194)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (316:316:316) (362:362:362)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (621:621:621) (666:666:666)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) + (PORT asdata (496:496:496) (536:536:536)) + (PORT ena (501:501:501) (541:541:541)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (355:355:355) (431:431:431)) + (PORT datab (131:131:131) (179:179:179)) + (PORT datad (333:333:333) (384:384:384)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (603:603:603) (658:658:658)) + (PORT ena (406:406:406) (423:423:423)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[3\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1021:1021:1021) (1184:1184:1184)) + (PORT datab (355:355:355) (411:411:411)) + (PORT datac (1068:1068:1068) (1243:1243:1243)) + (PORT datad (463:463:463) (542:542:542)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (350:350:350) (421:421:421)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (333:333:333) (395:395:395)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~48) + (DELAY + (ABSOLUTE + (PORT dataa (340:340:340) (405:405:405)) + (PORT datab (499:499:499) (578:578:578)) + (PORT datac (622:622:622) (723:723:723)) + (PORT datad (314:314:314) (363:363:363)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[3\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (329:329:329) (399:399:399)) + (PORT datab (339:339:339) (397:397:397)) + (PORT datac (337:337:337) (386:386:386)) + (PORT datad (362:362:362) (440:440:440)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[3\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (313:313:313) (366:366:366)) + (PORT datab (141:141:141) (183:183:183)) + (PORT datac (311:311:311) (363:363:363)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[2\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (588:588:588) (681:681:681)) + (PORT datab (625:625:625) (752:752:752)) + (PORT datad (328:328:328) (385:385:385)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (169:169:169) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[2\]\~22) + (DELAY + (ABSOLUTE + (PORT datab (102:102:102) (131:131:131)) + (PORT datac (354:354:354) (424:424:424)) + (PORT datad (597:597:597) (680:680:680)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|result_lo\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (920:920:920) (927:927:927)) + (PORT asdata (351:351:351) (381:381:381)) + (PORT ena (1084:1084:1084) (1203:1203:1203)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\~3) + (DELAY + (ABSOLUTE + (PORT datab (146:146:146) (186:186:186)) + (PORT datac (139:139:139) (180:180:180)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[2\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (384:384:384) (467:467:467)) + (PORT datab (621:621:621) (720:720:720)) + (PORT datac (314:314:314) (375:375:375)) + (PORT datad (361:361:361) (437:437:437)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (169:169:169) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[2\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (505:505:505) (593:593:593)) + (PORT datab (483:483:483) (563:563:563)) + (PORT datac (89:89:89) (110:110:110)) + (PORT datad (359:359:359) (410:410:410)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_low\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (923:923:923) (910:910:910)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (422:422:422) (450:450:450)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[2\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (353:353:353) (413:413:413)) + (PORT datab (230:230:230) (287:287:287)) + (PORT datac (298:298:298) (357:357:357)) + (PORT datad (359:359:359) (414:414:414)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[2\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (147:147:147) (186:186:186)) + (PORT datac (618:618:618) (709:709:709)) + (PORT datad (165:165:165) (195:195:195)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[2\]\~20) + (DELAY + (ABSOLUTE + (PORT datab (569:569:569) (648:648:648)) + (PORT datad (159:159:159) (186:186:186)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[2\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (133:133:133)) + (PORT datab (384:384:384) (461:461:461)) + (PORT datac (390:390:390) (457:457:457)) + (PORT datad (318:318:318) (370:370:370)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[2\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (516:516:516) (601:601:601)) + (PORT datab (356:356:356) (415:415:415)) + (PORT datac (336:336:336) (396:396:396)) + (PORT datad (460:460:460) (533:533:533)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[2\]\~8) + (DELAY + (ABSOLUTE + (PORT datac (487:487:487) (562:562:562)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_low\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (931:931:931) (916:916:916)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (409:409:409) (429:429:429)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op1\[2\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (414:414:414)) + (PORT datab (653:653:653) (772:772:772)) + (PORT datac (357:357:357) (416:416:416)) + (PORT datad (319:319:319) (385:385:385)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (169:169:169) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_10\~1) + (DELAY + (ABSOLUTE + (PORT dataa (196:196:196) (234:234:234)) + (PORT datac (97:97:97) (123:123:123)) + (PORT datad (587:587:587) (686:686:686)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_10\~0) + (DELAY + (ABSOLUTE + (PORT dataa (115:115:115) (151:151:151)) + (PORT datab (229:229:229) (286:286:286)) + (PORT datac (304:304:304) (368:368:368)) + (PORT datad (769:769:769) (888:888:888)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (244:244:244)) + (PORT datab (763:763:763) (897:897:897)) + (PORT datac (93:93:93) (117:117:117)) + (PORT datad (99:99:99) (120:120:120)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|cy_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (110:110:110) (144:144:144)) + (PORT datab (614:614:614) (724:724:724)) + (PORT datac (94:94:94) (118:118:118)) + (PORT datad (334:334:334) (394:394:394)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|SYNTHESIZED_WIRE_10\~0) + (DELAY + (ABSOLUTE + (PORT dataa (248:248:248) (312:312:312)) + (PORT datab (121:121:121) (151:151:151)) + (PORT datac (213:213:213) (275:275:275)) + (PORT datad (767:767:767) (886:886:886)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|cy_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (108:108:108) (140:140:140)) + (PORT datab (119:119:119) (148:148:148)) + (PORT datac (745:745:745) (869:869:869)) + (PORT datad (95:95:95) (115:115:115)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf\~0) + (DELAY + (ABSOLUTE + (PORT dataa (439:439:439) (510:510:510)) + (PORT datab (464:464:464) (536:536:536)) + (PORT datac (110:110:110) (135:135:135)) + (PORT datad (361:361:361) (421:421:421)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1320:1320:1320) (1531:1531:1531)) + (PORT datab (969:969:969) (1108:1108:1108)) + (PORT datac (483:483:483) (567:567:567)) + (PORT datad (756:756:756) (870:870:870)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (323:323:323) (377:377:377)) + (PORT datab (535:535:535) (624:624:624)) + (PORT datac (101:101:101) (122:122:122)) + (PORT datad (322:322:322) (376:376:376)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf\~1) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (137:137:137)) + (PORT datab (107:107:107) (137:137:137)) + (PORT datad (165:165:165) (194:194:194)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf) + (DELAY + (ABSOLUTE + (PORT clk (915:915:915) (919:919:919)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|flags_hf) + (DELAY + (ABSOLUTE + (PORT dataa (522:522:522) (600:600:600)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (1017:1017:1017) (1179:1179:1179)) + (PORT datad (625:625:625) (717:717:717)) + (IOPATH dataa combout (192:192:192) (184:184:184)) + (IOPATH datab combout (191:191:191) (188:188:188)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[4\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (663:663:663) (770:770:770)) + (PORT datab (381:381:381) (456:456:456)) + (PORT datac (189:189:189) (229:229:229)) + (PORT datad (197:197:197) (231:231:231)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[4\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (315:315:315) (361:361:361)) + (PORT datab (593:593:593) (672:672:672)) + (PORT datac (457:457:457) (527:527:527)) + (PORT datad (90:90:90) (107:107:107)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (120:120:120) (124:124:124)) @@ -26314,13 +26001,400 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~7) + (INSTANCE z80_\|alu_control_\|db\[4\]\~32) (DELAY (ABSOLUTE - (PORT dataa (411:411:411) (492:492:492)) - (PORT datab (803:803:803) (961:961:961)) - (PORT datac (614:614:614) (693:693:693)) - (PORT datad (105:105:105) (130:130:130)) + (PORT dataa (379:379:379) (447:447:447)) + (PORT datab (174:174:174) (213:213:213)) + (PORT datac (214:214:214) (260:260:260)) + (PORT datad (193:193:193) (226:226:226)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[4\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (329:329:329) (398:398:398)) + (PORT datab (489:489:489) (558:558:558)) + (PORT datac (312:312:312) (365:365:365)) + (PORT datad (353:353:353) (417:417:417)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[4\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (388:388:388) (474:474:474)) + (PORT datab (138:138:138) (180:180:180)) + (PORT datac (91:91:91) (112:112:112)) + (PORT datad (320:320:320) (372:372:372)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[3\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (480:480:480) (557:557:557)) + (PORT datab (651:651:651) (784:784:784)) + (PORT datad (452:452:452) (528:528:528)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (169:169:169) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[3\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (192:192:192) (230:230:230)) + (PORT datab (611:611:611) (703:703:703)) + (PORT datac (388:388:388) (455:455:455)) + (PORT datad (573:573:573) (654:654:654)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (169:169:169) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[3\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (482:482:482) (560:560:560)) + (PORT datab (485:485:485) (559:559:559)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[3\]\~25) + (DELAY + (ABSOLUTE + (PORT datab (382:382:382) (458:458:458)) + (PORT datac (387:387:387) (453:453:453)) + (PORT datad (103:103:103) (120:120:120)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[3\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (449:449:449)) + (PORT datab (621:621:621) (721:721:721)) + (PORT datac (362:362:362) (436:436:436)) + (PORT datad (402:402:402) (451:451:451)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[3\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (643:643:643) (738:738:738)) + (PORT datab (484:484:484) (563:563:563)) + (PORT datac (488:488:488) (568:568:568)) + (PORT datad (89:89:89) (107:107:107)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_low\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (923:923:923) (910:910:910)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (422:422:422) (450:450:450)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[3\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (513:513:513) (601:601:601)) + (PORT datab (420:420:420) (476:476:476)) + (PORT datac (630:630:630) (716:716:716)) + (PORT datad (349:349:349) (410:410:410)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[3\]\~1) + (DELAY + (ABSOLUTE + (PORT datab (486:486:486) (566:566:566)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_high\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (923:923:923) (910:910:910)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (422:422:422) (450:450:450)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op2\[3\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (365:365:365) (431:431:431)) + (PORT datab (377:377:377) (460:460:460)) + (PORT datac (470:470:470) (535:535:535)) + (PORT datad (354:354:354) (430:430:430)) + (IOPATH dataa combout (181:181:181) (193:193:193)) + (IOPATH datab combout (191:191:191) (188:188:188)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|SYNTHESIZED_WIRE_1) + (DELAY + (ABSOLUTE + (PORT dataa (109:109:109) (142:142:142)) + (PORT datab (106:106:106) (134:134:134)) + (PORT datac (613:613:613) (701:701:701)) + (PORT datad (106:106:106) (125:125:125)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|result\~0) + (DELAY + (ABSOLUTE + (PORT dataa (189:189:189) (231:231:231)) + (PORT datab (201:201:201) (238:238:238)) + (PORT datac (285:285:285) (323:323:323)) + (PORT datad (173:173:173) (204:204:204)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (131:131:131) (169:169:169)) + (PORT datab (322:322:322) (390:390:390)) + (PORT datac (817:817:817) (957:957:957)) + (PORT datad (120:120:120) (140:140:140)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (573:573:573) (662:662:662)) + (PORT datab (110:110:110) (141:141:141)) + (PORT datad (637:637:637) (762:762:762)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (583:583:583) (672:672:672)) + (PORT datab (609:609:609) (701:701:701)) + (PORT datad (157:157:157) (183:183:183)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (144:144:144) (191:191:191)) + (PORT datab (147:147:147) (186:186:186)) + (PORT datac (619:619:619) (710:710:710)) + (PORT datad (137:137:137) (167:167:167)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (351:351:351) (414:414:414)) + (PORT datab (177:177:177) (217:217:217)) + (PORT datac (359:359:359) (418:418:418)) + (PORT datad (330:330:330) (385:385:385)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (482:482:482) (560:560:560)) + (PORT datab (344:344:344) (405:405:405)) + (PORT datac (179:179:179) (214:214:214)) + (PORT datad (289:289:289) (327:327:327)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_34) + (DELAY + (ABSOLUTE + (PORT dataa (480:480:480) (563:563:563)) + (PORT datab (580:580:580) (661:661:661)) + (PORT datac (275:275:275) (316:316:316)) + (PORT datad (350:350:350) (406:406:406)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_sf) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (645:645:645) (697:697:697)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~5) + (DELAY + (ABSOLUTE + (PORT dataa (124:124:124) (159:159:159)) + (PORT datab (131:131:131) (165:165:165)) + (PORT datac (334:334:334) (390:390:390)) + (PORT datad (470:470:470) (554:554:554)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~7) + (DELAY + (ABSOLUTE + (PORT dataa (960:960:960) (1150:1150:1150)) + (PORT datab (498:498:498) (575:575:575)) + (PORT datac (566:566:566) (628:628:628)) + (PORT datad (522:522:522) (613:613:613)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -26330,14 +26404,78 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~8) + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_nop3pla68M2T2_3) (DELAY (ABSOLUTE - (PORT dataa (346:346:346) (400:400:400)) - (PORT datab (440:440:440) (497:497:497)) - (PORT datac (617:617:617) (699:699:699)) + (PORT dataa (1283:1283:1283) (1476:1476:1476)) + (PORT datab (1258:1258:1258) (1474:1474:1474)) + (PORT datac (1218:1218:1218) (1381:1381:1381)) + (PORT datad (393:393:393) (488:488:488)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~6) + (DELAY + (ABSOLUTE + (PORT dataa (709:709:709) (830:830:830)) + (PORT datab (522:522:522) (609:609:609)) + (PORT datac (1116:1116:1116) (1291:1291:1291)) + (PORT datad (936:936:936) (1120:1120:1120)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~8) + (DELAY + (ABSOLUTE + (PORT dataa (492:492:492) (574:574:574)) + (PORT datab (104:104:104) (132:132:132)) + (PORT datac (88:88:88) (109:109:109)) (PORT datad (90:90:90) (107:107:107)) (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~11) + (DELAY + (ABSOLUTE + (PORT dataa (437:437:437) (496:496:496)) + (PORT datab (582:582:582) (661:661:661)) + (PORT datac (691:691:691) (799:799:799)) + (PORT datad (319:319:319) (369:369:369)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~12) + (DELAY + (ABSOLUTE + (PORT dataa (373:373:373) (445:445:445)) + (PORT datab (369:369:369) (443:443:443)) + (PORT datac (367:367:367) (431:431:431)) + (PORT datad (648:648:648) (748:748:748)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -26346,48 +26484,128 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~9) + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~15) (DELAY (ABSOLUTE - (PORT dataa (354:354:354) (418:418:418)) - (PORT datab (579:579:579) (679:679:679)) - (PORT datac (302:302:302) (347:347:347)) - (PORT datad (502:502:502) (580:580:580)) + (PORT dataa (460:460:460) (534:534:534)) + (PORT datab (413:413:413) (506:506:506)) + (PORT datac (90:90:90) (112:112:112)) + (PORT datad (545:545:545) (614:614:614)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~0) + (INSTANCE z80_\|alu_\|alu_op2\[2\]\~0) (DELAY (ABSOLUTE - (PORT dataa (380:380:380) (450:450:450)) - (PORT datab (315:315:315) (366:366:366)) - (PORT datac (128:128:128) (169:169:169)) - (PORT datad (95:95:95) (114:114:114)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) + (PORT dataa (370:370:370) (437:437:437)) + (PORT datab (488:488:488) (561:561:561)) + (PORT datac (300:300:300) (359:359:359)) + (PORT datad (354:354:354) (429:429:429)) + (IOPATH dataa combout (181:181:181) (184:184:184)) + (IOPATH datab combout (192:192:192) (188:188:188)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_1) + (DELAY + (ABSOLUTE + (PORT dataa (109:109:109) (143:143:143)) + (PORT datab (108:108:108) (139:139:139)) + (PORT datac (614:614:614) (701:701:701)) + (PORT datad (334:334:334) (394:394:394)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|result\~0) + (DELAY + (ABSOLUTE + (PORT dataa (112:112:112) (147:147:147)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (174:174:174) (212:212:212)) + (PORT datad (335:335:335) (395:395:395)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_control_\|DFFE_latch_pf_tmp) + (DELAY + (ABSOLUTE + (PORT clk (921:921:921) (928:928:928)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (1178:1178:1178) (1299:1299:1299)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_parity_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (503:503:503) (585:585:585)) + (PORT datab (203:203:203) (257:257:257)) + (PORT datac (459:459:459) (532:532:532)) + (PORT datad (630:630:630) (742:742:742)) + (IOPATH dataa combout (192:192:192) (184:184:184)) + (IOPATH datab combout (182:182:182) (193:193:193)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_parity_out\~1) + (DELAY + (ABSOLUTE + (PORT dataa (285:285:285) (335:335:335)) + (PORT datab (278:278:278) (329:329:329)) + (PORT datac (89:89:89) (110:110:110)) + (PORT datad (457:457:457) (525:525:525)) + (IOPATH dataa combout (188:188:188) (203:203:203)) + (IOPATH datab combout (190:190:190) (205:205:205)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~4) (DELAY (ABSOLUTE - (PORT dataa (615:615:615) (714:714:714)) - (PORT datab (399:399:399) (471:471:471)) - (PORT datac (509:509:509) (590:590:590)) - (PORT datad (650:650:650) (742:742:742)) - (IOPATH dataa combout (158:158:158) (157:157:157)) + (PORT dataa (497:497:497) (584:584:584)) + (PORT datab (820:820:820) (934:934:934)) + (PORT datac (428:428:428) (528:528:528)) + (PORT datad (670:670:670) (764:764:764)) + (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -26397,12 +26615,12 @@ (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~5) (DELAY (ABSOLUTE - (PORT dataa (805:805:805) (926:926:926)) - (PORT datab (360:360:360) (432:432:432)) - (PORT datac (89:89:89) (110:110:110)) - (PORT datad (791:791:791) (904:904:904)) - (IOPATH dataa combout (186:186:186) (175:175:175)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (PORT dataa (565:565:565) (669:669:669)) + (PORT datab (281:281:281) (329:329:329)) + (PORT datac (289:289:289) (327:327:327)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (196:196:196) (205:205:205)) (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -26413,12 +26631,12 @@ (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~6) (DELAY (ABSOLUTE - (PORT dataa (786:786:786) (906:906:906)) - (PORT datab (399:399:399) (470:470:470)) - (PORT datac (636:636:636) (731:731:731)) - (PORT datad (89:89:89) (107:107:107)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (PORT dataa (948:948:948) (1088:1088:1088)) + (PORT datab (880:880:880) (1018:1018:1018)) + (PORT datac (428:428:428) (528:528:528)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -26426,31 +26644,16 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~0) + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~1) (DELAY (ABSOLUTE - (PORT dataa (219:219:219) (282:282:282)) - (PORT datab (146:146:146) (201:201:201)) - (PORT datac (124:124:124) (170:170:170)) - (PORT datad (313:313:313) (370:370:370)) - (IOPATH dataa combout (158:158:158) (157:157:157)) + (PORT dataa (563:563:563) (667:667:667)) + (PORT datab (685:685:685) (789:789:789)) + (PORT datac (479:479:479) (566:566:566)) + (PORT datad (804:804:804) (912:912:912)) + (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~3) - (DELAY - (ABSOLUTE - (PORT dataa (442:442:442) (522:522:522)) - (PORT datab (403:403:403) (487:487:487)) - (PORT datad (208:208:208) (253:253:253)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -26460,10 +26663,10 @@ (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~2) (DELAY (ABSOLUTE - (PORT dataa (224:224:224) (293:293:293)) - (PORT datab (205:205:205) (263:263:263)) - (PORT datac (345:345:345) (421:421:421)) - (PORT datad (374:374:374) (448:448:448)) + (PORT dataa (536:536:536) (627:627:627)) + (PORT datab (684:684:684) (793:793:793)) + (PORT datac (681:681:681) (797:797:797)) + (PORT datad (308:308:308) (365:365:365)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (124:124:124)) @@ -26476,10 +26679,42 @@ (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~1) (DELAY (ABSOLUTE - (PORT dataa (150:150:150) (208:208:208)) - (PORT datab (315:315:315) (383:383:383)) - (PORT datac (134:134:134) (182:182:182)) - (PORT datad (196:196:196) (239:239:239)) + (PORT dataa (543:543:543) (644:644:644)) + (PORT datab (537:537:537) (631:631:631)) + (PORT datac (133:133:133) (176:176:176)) + (PORT datad (222:222:222) (276:276:276)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~3) + (DELAY + (ABSOLUTE + (PORT dataa (156:156:156) (212:212:212)) + (PORT datab (146:146:146) (196:196:196)) + (PORT datac (132:132:132) (175:175:175)) + (PORT datad (419:419:419) (494:494:494)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~0) + (DELAY + (ABSOLUTE + (PORT dataa (144:144:144) (201:201:201)) + (PORT datab (215:215:215) (274:274:274)) + (PORT datac (132:132:132) (175:175:175)) + (PORT datad (214:214:214) (261:261:261)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (124:124:124)) @@ -26492,10 +26727,10 @@ (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~4) (DELAY (ABSOLUTE - (PORT dataa (302:302:302) (349:349:349)) - (PORT datab (486:486:486) (556:556:556)) - (PORT datac (301:301:301) (340:340:340)) - (PORT datad (158:158:158) (184:184:184)) + (PORT dataa (103:103:103) (135:135:135)) + (PORT datab (106:106:106) (135:135:135)) + (PORT datac (331:331:331) (382:382:382)) + (PORT datad (162:162:162) (190:190:190)) (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -26508,11 +26743,11 @@ (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~5) (DELAY (ABSOLUTE - (PORT dataa (788:788:788) (908:908:908)) - (PORT datab (874:874:874) (1011:1011:1011)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (181:181:181) (175:175:175)) - (IOPATH datab combout (166:166:166) (158:158:158)) + (PORT dataa (487:487:487) (565:565:565)) + (PORT datab (638:638:638) (741:741:741)) + (PORT datad (1236:1236:1236) (1399:1399:1399)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (167:167:167) (156:156:156)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -26525,7 +26760,7 @@ (ABSOLUTE (PORT clk (908:908:908) (913:913:913)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (919:919:919) (904:904:904)) + (PORT clrn (909:909:909) (896:896:896)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -26534,32 +26769,16 @@ (HOLD d (posedge clk) (84:84:84)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~1) - (DELAY - (ABSOLUTE - (PORT dataa (615:615:615) (713:713:713)) - (PORT datab (358:358:358) (430:430:430)) - (PORT datac (510:510:510) (591:591:591)) - (PORT datad (648:648:648) (740:740:740)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~2) (DELAY (ABSOLUTE - (PORT dataa (535:535:535) (630:630:630)) - (PORT datab (146:146:146) (195:195:195)) - (PORT datac (633:633:633) (728:728:728)) - (PORT datad (90:90:90) (106:106:106)) - (IOPATH dataa combout (166:166:166) (163:163:163)) + (PORT dataa (103:103:103) (134:134:134)) + (PORT datab (632:632:632) (745:745:745)) + (PORT datac (212:212:212) (265:265:265)) + (PORT datad (925:925:925) (1059:1059:1059)) + (IOPATH dataa combout (159:159:159) (165:165:165)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -26571,119 +26790,26 @@ (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~3) (DELAY (ABSOLUTE - (PORT dataa (104:104:104) (136:136:136)) - (PORT datab (399:399:399) (470:470:470)) - (PORT datac (771:771:771) (882:882:882)) - (PORT datad (133:133:133) (172:172:172)) - (IOPATH dataa combout (170:170:170) (163:163:163)) + (PORT dataa (103:103:103) (134:134:134)) + (PORT datab (443:443:443) (549:549:549)) + (PORT datac (615:615:615) (726:726:726)) + (PORT datad (867:867:867) (997:997:997)) + (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_control_\|DFFE_latch_pf_tmp) - (DELAY - (ABSOLUTE - (PORT clk (901:901:901) (909:909:909)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (676:676:676) (740:740:740)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_1) - (DELAY - (ABSOLUTE - (PORT dataa (116:116:116) (147:147:147)) - (PORT datab (113:113:113) (145:145:145)) - (PORT datac (94:94:94) (119:119:119)) - (PORT datad (95:95:95) (115:115:115)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|result\~0) - (DELAY - (ABSOLUTE - (PORT dataa (284:284:284) (333:333:333)) - (PORT datab (112:112:112) (144:144:144)) - (PORT datac (92:92:92) (116:116:116)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_parity_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (415:415:415) (479:479:479)) - (PORT datac (170:170:170) (204:204:204)) - (PORT datad (104:104:104) (121:121:121)) - (IOPATH dataa combout (195:195:195) (203:203:203)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_parity_out) - (DELAY - (ABSOLUTE - (PORT dataa (179:179:179) (217:217:217)) - (PORT datab (358:358:358) (421:421:421)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (195:195:195) (193:193:193)) - (IOPATH datab combout (196:196:196) (192:192:192)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~7) (DELAY (ABSOLUTE - (PORT dataa (615:615:615) (714:714:714)) - (PORT datab (650:650:650) (752:752:752)) - (PORT datac (772:772:772) (883:883:883)) - (PORT datad (649:649:649) (742:742:742)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~8) - (DELAY - (ABSOLUTE - (PORT dataa (527:527:527) (616:616:616)) - (PORT datab (401:401:401) (473:473:473)) - (PORT datac (342:342:342) (408:408:408)) - (PORT datad (92:92:92) (109:109:109)) + (PORT dataa (945:945:945) (1085:1085:1085)) + (PORT datab (884:884:884) (1023:1023:1023)) + (PORT datac (1155:1155:1155) (1310:1310:1310)) + (PORT datad (672:672:672) (767:767:767)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -26691,32 +26817,64 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~8) + (DELAY + (ABSOLUTE + (PORT dataa (502:502:502) (591:591:591)) + (PORT datab (101:101:101) (130:130:130)) + (PORT datac (426:426:426) (526:526:526)) + (PORT datad (549:549:549) (640:640:640)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~9) (DELAY (ABSOLUTE - (PORT dataa (105:105:105) (137:137:137)) - (PORT datab (104:104:104) (133:133:133)) - (PORT datac (778:778:778) (888:888:888)) - (PORT datad (89:89:89) (107:107:107)) - (IOPATH dataa combout (170:170:170) (163:163:163)) + (PORT dataa (104:104:104) (136:136:136)) + (PORT datab (102:102:102) (131:131:131)) + (PORT datac (90:90:90) (111:111:111)) + (PORT datad (93:93:93) (111:111:111)) + (IOPATH dataa combout (165:165:165) (159:159:159)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~0) + (DELAY + (ABSOLUTE + (PORT dataa (480:480:480) (559:559:559)) + (PORT datab (144:144:144) (193:193:193)) + (PORT datac (458:458:458) (526:526:526)) + (PORT datad (322:322:322) (373:373:373)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~10) (DELAY (ABSOLUTE - (PORT dataa (107:107:107) (140:140:140)) - (PORT datab (173:173:173) (208:208:208)) - (PORT datac (680:680:680) (776:776:776)) - (PORT datad (364:364:364) (424:424:424)) - (IOPATH dataa combout (166:166:166) (157:157:157)) + (PORT dataa (636:636:636) (736:736:736)) + (PORT datab (476:476:476) (546:546:546)) + (PORT datac (571:571:571) (653:653:653)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -26728,7 +26886,7 @@ (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf) (DELAY (ABSOLUTE - (PORT clk (900:900:900) (905:905:905)) + (PORT clk (909:909:909) (913:913:913)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -26742,134 +26900,26 @@ (INSTANCE z80_\|alu_control_\|sel\[1\]\~0) (DELAY (ABSOLUTE - (PORT dataa (491:491:491) (574:574:574)) - (PORT datab (1125:1125:1125) (1288:1288:1288)) - (PORT datac (502:502:502) (612:612:612)) - (PORT datad (466:466:466) (538:538:538)) + (PORT dataa (677:677:677) (780:780:780)) + (PORT datab (799:799:799) (958:958:958)) + (PORT datac (111:111:111) (142:142:142)) + (PORT datad (464:464:464) (534:534:534)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11\~2) - (DELAY - (ABSOLUTE - (PORT dataa (213:213:213) (257:257:257)) - (PORT datab (642:642:642) (749:749:749)) - (PORT datac (309:309:309) (355:355:355)) - (PORT datad (173:173:173) (203:203:203)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_12) - (DELAY - (ABSOLUTE - (PORT dataa (447:447:447) (518:518:518)) - (PORT datad (176:176:176) (202:202:202)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11\~0) - (DELAY - (ABSOLUTE - (PORT dataa (121:121:121) (160:160:160)) - (PORT datab (117:117:117) (152:152:152)) - (PORT datac (330:330:330) (391:391:391)) - (PORT datad (116:116:116) (146:146:146)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11\~1) - (DELAY - (ABSOLUTE - (PORT dataa (316:316:316) (370:370:370)) - (PORT datab (358:358:358) (422:422:422)) - (PORT datac (302:302:302) (348:348:348)) - (PORT datad (160:160:160) (183:183:183)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_37\~0) - (DELAY - (ABSOLUTE - (PORT dataa (331:331:331) (385:385:385)) - (PORT datab (345:345:345) (395:395:395)) - (PORT datac (131:131:131) (173:173:173)) - (PORT datad (198:198:198) (230:230:230)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_37\~1) - (DELAY - (ABSOLUTE - (PORT dataa (355:355:355) (417:417:417)) - (PORT datab (104:104:104) (133:133:133)) - (PORT datac (334:334:334) (392:392:392)) - (PORT datad (93:93:93) (111:111:111)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_39) - (DELAY - (ABSOLUTE - (PORT clk (902:902:902) (907:907:907)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (661:661:661) (712:712:712)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|alu_control_\|b2v_inst_cond_mux\|out\~0) (DELAY (ABSOLUTE - (PORT dataa (891:891:891) (1048:1048:1048)) - (PORT datab (117:117:117) (146:146:146)) - (PORT datac (95:95:95) (119:119:119)) - (PORT datad (479:479:479) (570:570:570)) + (PORT dataa (149:149:149) (202:202:202)) + (PORT datab (327:327:327) (378:378:378)) + (PORT datac (564:564:564) (635:635:635)) + (PORT datad (563:563:563) (653:653:653)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (166:166:166) (167:167:167)) (IOPATH datac combout (120:120:120) (124:124:124)) @@ -26882,13 +26932,13 @@ (INSTANCE z80_\|alu_control_\|b2v_inst_cond_mux\|out\~1) (DELAY (ABSOLUTE - (PORT dataa (367:367:367) (451:451:451)) - (PORT datab (347:347:347) (416:416:416)) - (PORT datac (94:94:94) (118:118:118)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (PORT dataa (489:489:489) (579:579:579)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (564:564:564) (635:635:635)) + (PORT datad (130:130:130) (167:167:167)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (196:196:196) (205:205:205)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -26898,11 +26948,11 @@ (INSTANCE z80_\|alu_control_\|flags_cond_true\~0) (DELAY (ABSOLUTE - (PORT dataa (1019:1019:1019) (1203:1203:1203)) - (PORT datab (1126:1126:1126) (1289:1289:1289)) + (PORT dataa (547:547:547) (644:644:644)) + (PORT datab (410:410:410) (513:513:513)) (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (159:159:159) (173:173:173)) - (IOPATH datab combout (196:196:196) (192:192:192)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (161:161:161) (176:176:176)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -26913,7 +26963,7 @@ (INSTANCE z80_\|alu_control_\|flags_cond_true) (DELAY (ABSOLUTE - (PORT clk (899:899:899) (904:904:904)) + (PORT clk (909:909:909) (914:914:914)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -26924,75 +26974,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~13) + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~20) (DELAY (ABSOLUTE - (PORT dataa (330:330:330) (392:392:392)) - (PORT datab (985:985:985) (1144:1144:1144)) - (PORT datac (1024:1024:1024) (1196:1196:1196)) - (PORT datad (302:302:302) (349:349:349)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~14) - (DELAY - (ABSOLUTE - (PORT dataa (108:108:108) (142:142:142)) - (PORT datab (121:121:121) (155:155:155)) - (PORT datac (301:301:301) (349:349:349)) - (PORT datad (94:94:94) (113:113:113)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~17) - (DELAY - (ABSOLUTE - (PORT dataa (477:477:477) (550:550:550)) - (PORT datab (117:117:117) (146:146:146)) - (PORT datac (337:337:337) (398:398:398)) - (PORT datad (670:670:670) (775:775:775)) + (PORT dataa (1074:1074:1074) (1246:1246:1246)) + (PORT datab (516:516:516) (641:641:641)) + (PORT datac (463:463:463) (530:530:530)) + (PORT datad (516:516:516) (613:613:613)) (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_82) + (INSTANCE z80_\|execute_\|ctl_sw_4d\~1) (DELAY (ABSOLUTE - (PORT dataa (340:340:340) (398:398:398)) - (PORT datab (517:517:517) (608:608:608)) - (PORT datad (358:358:358) (423:423:423)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (358:358:358) (429:429:429)) - (PORT datab (268:268:268) (309:309:309)) - (PORT datac (384:384:384) (430:430:430)) - (PORT datad (604:604:604) (691:691:691)) + (PORT dataa (491:491:491) (568:568:568)) + (PORT datab (872:872:872) (1015:1015:1015)) + (PORT datac (301:301:301) (349:349:349)) + (PORT datad (176:176:176) (210:210:210)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -27002,31 +27006,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~20) + (INSTANCE z80_\|execute_\|ctl_sw_4d\~6) (DELAY (ABSOLUTE - (PORT dataa (282:282:282) (331:331:331)) - (PORT datab (105:105:105) (134:134:134)) - (PORT datac (316:316:316) (370:370:370)) - (PORT datad (341:341:341) (393:393:393)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (134:134:134)) - (PORT datab (139:139:139) (175:175:175)) - (PORT datac (322:322:322) (372:372:372)) - (PORT datad (128:128:128) (157:157:157)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT datab (102:102:102) (129:129:129)) + (PORT datac (88:88:88) (110:110:110)) + (PORT datad (94:94:94) (112:112:112)) + (IOPATH datab combout (166:166:166) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -27034,28 +27020,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[1\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[1\]) (DELAY (ABSOLUTE - (PORT clk (910:910:910) (918:918:918)) - (PORT asdata (1007:1007:1007) (1124:1124:1124)) - (PORT ena (421:421:421) (449:449:449)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (910:910:910) (917:917:917)) - (PORT asdata (989:989:989) (1095:1095:1095)) - (PORT ena (649:649:649) (703:703:703)) + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (455:455:455) (496:496:496)) + (PORT ena (621:621:621) (659:659:659)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -27066,12 +27036,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~28) + (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~4) (DELAY (ABSOLUTE - (PORT dataa (218:218:218) (265:265:265)) - (PORT datab (198:198:198) (255:255:255)) - (PORT datad (331:331:331) (384:384:384)) + (PORT dataa (495:495:495) (573:573:573)) + (PORT datab (647:647:647) (748:748:748)) + (PORT datad (211:211:211) (256:256:256)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) @@ -27081,76 +27051,58 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[1\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[1\]) (DELAY (ABSOLUTE - (PORT clk (910:910:910) (917:917:917)) - (PORT asdata (988:988:988) (1095:1095:1095)) - (PORT ena (812:812:812) (885:885:885)) + (PORT clk (903:903:903) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (633:633:633) (693:693:693)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (910:910:910)) - (PORT asdata (1163:1163:1163) (1294:1294:1294)) - (PORT ena (631:631:631) (680:680:680)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (907:907:907) (911:911:911)) - (PORT asdata (1168:1168:1168) (1299:1299:1299)) - (PORT ena (432:432:432) (460:460:460)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) + (HOLD d (posedge clk) (84:84:84)) (HOLD ena (posedge clk) (84:84:84)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~26) + (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~5) (DELAY (ABSOLUTE - (PORT dataa (227:227:227) (288:288:288)) - (PORT datab (360:360:360) (427:427:427)) - (PORT datad (338:338:338) (407:407:407)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (116:116:116) (156:156:156)) + (PORT datad (318:318:318) (370:370:370)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~27) + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|d1_out) (DELAY (ABSOLUTE - (PORT datab (768:768:768) (884:884:884)) - (PORT datad (311:311:311) (359:359:359)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) + (PORT dataa (339:339:339) (414:414:414)) + (PORT datac (101:101:101) (122:122:122)) + (IOPATH dataa combout (195:195:195) (203:203:203)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (924:924:924) (1051:1051:1051)) + (PORT datab (102:102:102) (129:129:129)) + (PORT datac (579:579:579) (654:654:654)) + (PORT datad (179:179:179) (214:214:214)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -27160,9 +27112,9 @@ (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[1\]) (DELAY (ABSOLUTE - (PORT clk (910:910:910) (918:918:918)) - (PORT asdata (1006:1006:1006) (1123:1123:1123)) - (PORT ena (644:644:644) (698:698:698)) + (PORT clk (906:906:906) (911:911:911)) + (PORT asdata (685:685:685) (760:760:760)) + (PORT ena (768:768:768) (845:845:845)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -27176,25 +27128,40 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~29) (DELAY (ABSOLUTE - (PORT dataa (336:336:336) (403:403:403)) - (PORT datab (525:525:525) (610:610:610)) - (PORT datac (488:488:488) (565:565:565)) - (PORT datad (333:333:333) (386:386:386)) - (IOPATH dataa combout (166:166:166) (163:163:163)) + (PORT dataa (391:391:391) (467:467:467)) + (PORT datab (741:741:741) (852:852:852)) + (PORT datad (459:459:459) (523:523:523)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[1\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[1\]) (DELAY (ABSOLUTE - (PORT clk (911:911:911) (918:918:918)) - (PORT asdata (875:875:875) (973:973:973)) - (PORT ena (422:422:422) (454:454:454)) + (PORT clk (907:907:907) (911:911:911)) + (PORT asdata (521:521:521) (570:570:570)) + (PORT ena (405:405:405) (422:422:422)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (907:907:907) (911:911:911)) + (PORT asdata (520:520:520) (569:569:569)) + (PORT ena (677:677:677) (748:748:748)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -27205,40 +27172,90 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[1\]\~feeder) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~28) (DELAY (ABSOLUTE - (PORT datad (450:450:450) (519:519:519)) + (PORT dataa (138:138:138) (176:176:176)) + (PORT datab (129:129:129) (177:177:177)) + (PORT datad (357:357:357) (421:421:421)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[1\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[1\]) (DELAY (ABSOLUTE - (PORT clk (911:911:911) (918:918:918)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (669:669:669) (725:725:725)) + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (523:523:523) (569:569:569)) + (PORT ena (644:644:644) (699:699:699)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (525:525:525) (571:571:571)) + (PORT ena (634:634:634) (686:686:686)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) (HOLD ena (posedge clk) (84:84:84)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~25) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~26) (DELAY (ABSOLUTE - (PORT dataa (222:222:222) (278:278:278)) - (PORT datab (305:305:305) (362:362:362)) - (PORT datad (300:300:300) (360:360:360)) + (PORT dataa (475:475:475) (558:558:558)) + (PORT datab (131:131:131) (179:179:179)) + (PORT datad (367:367:367) (438:438:438)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (907:907:907) (912:912:912)) + (PORT asdata (975:975:975) (1092:1092:1092)) + (PORT ena (669:669:669) (725:725:725)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~27) + (DELAY + (ABSOLUTE + (PORT datab (321:321:321) (374:374:374)) + (PORT datad (506:506:506) (588:588:588)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -27249,23 +27266,11 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~30) (DELAY (ABSOLUTE - (PORT dataa (106:106:106) (137:137:137)) - (PORT datab (104:104:104) (133:133:133)) - (PORT datac (88:88:88) (109:109:109)) - (PORT datad (282:282:282) (322:322:322)) + (PORT dataa (300:300:300) (352:352:352)) + (PORT datab (103:103:103) (131:131:131)) + (PORT datad (428:428:428) (487:487:487)) (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (833:833:833) (949:949:949)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -27275,14 +27280,14 @@ (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[1\]) (DELAY (ABSOLUTE - (PORT clk (902:902:902) (908:908:908)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (756:756:756) (816:816:816)) + (PORT clk (907:907:907) (911:911:911)) + (PORT asdata (544:544:544) (606:606:606)) + (PORT ena (505:505:505) (542:542:542)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) (HOLD ena (posedge clk) (84:84:84)) ) ) @@ -27291,9 +27296,9 @@ (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[1\]) (DELAY (ABSOLUTE - (PORT clk (902:902:902) (908:908:908)) - (PORT asdata (1002:1002:1002) (1110:1110:1110)) - (PORT ena (915:915:915) (1002:1002:1002)) + (PORT clk (907:907:907) (911:911:911)) + (PORT asdata (544:544:544) (606:606:606)) + (PORT ena (417:417:417) (434:434:434)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -27308,9 +27313,9 @@ (DELAY (ABSOLUTE (PORT dataa (130:130:130) (180:180:180)) - (PORT datab (536:536:536) (631:631:631)) - (PORT datad (474:474:474) (547:547:547)) - (IOPATH dataa combout (170:170:170) (163:163:163)) + (PORT datab (131:131:131) (166:166:166)) + (PORT datad (125:125:125) (149:149:149)) + (IOPATH dataa combout (166:166:166) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -27319,12 +27324,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[1\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[1\]) (DELAY (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (368:368:368) (408:408:408)) - (PORT ena (419:419:419) (435:435:435)) + (PORT clk (911:911:911) (919:919:919)) + (PORT asdata (296:296:296) (316:316:316)) + (PORT ena (501:501:501) (535:535:535)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -27335,12 +27340,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[1\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[1\]) (DELAY (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT asdata (368:368:368) (408:408:408)) - (PORT ena (432:432:432) (460:460:460)) + (PORT clk (911:911:911) (919:919:919)) + (PORT asdata (297:297:297) (318:318:318)) + (PORT ena (502:502:502) (534:534:534)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -27354,10 +27359,57 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~23) (DELAY (ABSOLUTE - (PORT dataa (130:130:130) (180:180:180)) - (PORT datab (142:142:142) (180:180:180)) - (PORT datad (127:127:127) (152:152:152)) - (IOPATH dataa combout (166:166:166) (163:163:163)) + (PORT dataa (217:217:217) (261:261:261)) + (PORT datab (231:231:231) (274:274:274)) + (PORT datad (118:118:118) (155:155:155)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (919:919:919)) + (PORT asdata (507:507:507) (549:549:549)) + (PORT ena (656:656:656) (712:712:712)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (919:919:919)) + (PORT asdata (507:507:507) (550:550:550)) + (PORT ena (637:637:637) (680:680:680)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (382:382:382) (451:451:451)) + (PORT datab (385:385:385) (450:450:450)) + (PORT datad (117:117:117) (153:153:153)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -27369,11 +27421,13 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~31) (DELAY (ABSOLUTE - (PORT dataa (366:366:366) (434:434:434)) - (PORT datab (346:346:346) (405:405:405)) - (PORT datad (90:90:90) (106:106:106)) + (PORT dataa (323:323:323) (380:380:380)) + (PORT datab (330:330:330) (386:386:386)) + (PORT datac (92:92:92) (114:114:114)) + (PORT datad (171:171:171) (201:201:201)) (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -27383,12 +27437,12 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~32) (DELAY (ABSOLUTE - (PORT dataa (727:727:727) (836:836:836)) - (PORT datab (323:323:323) (375:375:375)) - (PORT datac (356:356:356) (416:416:416)) - (PORT datad (158:158:158) (184:184:184)) + (PORT dataa (465:465:465) (539:539:539)) + (PORT datab (474:474:474) (553:553:553)) + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (106:106:106) (124:124:124)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -27399,11 +27453,11 @@ (INSTANCE z80_\|reg_file_\|db_lo_ds\[1\]\~1) (DELAY (ABSOLUTE - (PORT dataa (828:828:828) (961:961:961)) - (PORT datab (928:928:928) (1056:1056:1056)) - (PORT datac (831:831:831) (943:943:943)) - (PORT datad (647:647:647) (747:747:747)) - (IOPATH dataa combout (170:170:170) (163:163:163)) + (PORT dataa (444:444:444) (514:514:514)) + (PORT datab (627:627:627) (718:718:718)) + (PORT datac (346:346:346) (412:412:412)) + (PORT datad (369:369:369) (427:427:427)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -27415,10 +27469,10 @@ (INSTANCE z80_\|alu_control_\|db\[1\]\~25) (DELAY (ABSOLUTE - (PORT dataa (527:527:527) (608:608:608)) - (PORT datab (489:489:489) (559:559:559)) - (PORT datac (506:506:506) (591:591:591)) - (PORT datad (488:488:488) (556:556:556)) + (PORT dataa (106:106:106) (138:138:138)) + (PORT datab (370:370:370) (436:436:436)) + (PORT datac (217:217:217) (264:264:264)) + (PORT datad (443:443:443) (507:507:507)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (120:120:120) (125:125:125)) @@ -27431,13 +27485,13 @@ (INSTANCE z80_\|alu_control_\|db\[1\]\~24) (DELAY (ABSOLUTE - (PORT dataa (367:367:367) (434:434:434)) - (PORT datab (612:612:612) (709:709:709)) - (PORT datac (491:491:491) (582:582:582)) - (PORT datad (652:652:652) (747:747:747)) + (PORT dataa (473:473:473) (552:552:552)) + (PORT datab (609:609:609) (703:703:703)) + (PORT datac (186:186:186) (225:225:225)) + (PORT datad (783:783:783) (900:900:900)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -27447,1394 +27501,43 @@ (INSTANCE z80_\|alu_control_\|db\[1\]\~26) (DELAY (ABSOLUTE - (PORT dataa (105:105:105) (137:137:137)) - (PORT datab (498:498:498) (583:583:583)) - (PORT datac (342:342:342) (402:402:402)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[1\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (714:714:714) (844:844:844)) - (PORT datab (508:508:508) (596:596:596)) - (PORT datac (805:805:805) (914:914:914)) - (PORT datad (517:517:517) (603:603:603)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[1\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (106:106:106) (138:138:138)) - (PORT datab (545:545:545) (638:638:638)) - (PORT datac (484:484:484) (567:567:567)) - (PORT datad (118:118:118) (149:149:149)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (931:931:931) (1087:1087:1087)) - (PORT datac (492:492:492) (566:566:566)) - (PORT datad (186:186:186) (217:217:217)) - (IOPATH dataa combout (186:186:186) (175:175:175)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~22) - (DELAY - (ABSOLUTE - (PORT datab (104:104:104) (132:132:132)) - (PORT datac (503:503:503) (580:580:580)) - (PORT datad (122:122:122) (149:149:149)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (649:649:649) (754:754:754)) - (PORT datab (152:152:152) (196:196:196)) - (PORT datac (137:137:137) (175:175:175)) - (PORT datad (138:138:138) (168:168:168)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (235:235:235) (302:302:302)) - (PORT datab (650:650:650) (752:752:752)) - (PORT datac (635:635:635) (744:744:744)) - (PORT datad (368:368:368) (436:436:436)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|result_lo\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (901:901:901) (909:909:909)) - (PORT asdata (348:348:348) (380:380:380)) - (PORT ena (676:676:676) (740:740:740)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (334:334:334) (387:387:387)) - (PORT datab (186:186:186) (223:223:223)) - (PORT datad (630:630:630) (723:723:723)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (307:307:307) (358:358:358)) - (PORT datab (116:116:116) (145:145:145)) - (PORT datac (610:610:610) (705:705:705)) - (PORT datad (170:170:170) (200:200:200)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[0\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (707:707:707) (834:834:834)) - (PORT datab (489:489:489) (568:568:568)) - (PORT datac (627:627:627) (702:702:702)) - (PORT datad (525:525:525) (611:611:611)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[0\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (134:134:134)) - (PORT datab (537:537:537) (630:630:630)) - (PORT datac (430:430:430) (491:491:491)) - (PORT datad (122:122:122) (153:153:153)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (531:531:531) (611:611:611)) - (PORT datac (914:914:914) (1063:1063:1063)) - (PORT datad (777:777:777) (876:876:876)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (135:135:135)) - (PORT datac (494:494:494) (569:569:569)) - (PORT datad (129:129:129) (157:157:157)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (651:651:651) (756:756:756)) - (PORT datab (155:155:155) (200:200:200)) - (PORT datac (141:141:141) (181:181:181)) - (PORT datad (132:132:132) (163:163:163)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (357:357:357) (433:433:433)) - (PORT datab (651:651:651) (752:752:752)) - (PORT datac (328:328:328) (390:390:390)) - (PORT datad (368:368:368) (436:436:436)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|result_lo\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (901:901:901) (909:909:909)) - (PORT asdata (579:579:579) (631:631:631)) - (PORT ena (676:676:676) (740:740:740)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (294:294:294) (344:344:344)) - (PORT datab (170:170:170) (207:207:207)) - (PORT datad (629:629:629) (722:722:722)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (363:363:363) (430:430:430)) - (PORT datab (187:187:187) (223:223:223)) - (PORT datac (433:433:433) (492:492:492)) - (PORT datad (90:90:90) (106:106:106)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[1\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (313:313:313) (367:367:367)) - (PORT datab (534:534:534) (632:632:632)) - (PORT datac (190:190:190) (233:233:233)) - (PORT datad (481:481:481) (558:558:558)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[1\]\~6) - (DELAY - (ABSOLUTE - (PORT datac (91:91:91) (113:113:113)) - (PORT datad (376:376:376) (447:447:447)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_low\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (916:916:916) (901:901:901)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (405:405:405) (422:422:422)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|out\[6\]\~0) - (DELAY - (ABSOLUTE - (PORT datab (144:144:144) (192:192:192)) - (PORT datac (128:128:128) (169:169:169)) - (PORT datad (128:128:128) (164:164:164)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~2) - (DELAY - (ABSOLUTE - (PORT datac (464:464:464) (542:542:542)) - (PORT datad (365:365:365) (428:428:428)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|flags_hf2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (368:368:368) (429:429:429)) + (PORT dataa (177:177:177) (216:216:216)) (PORT datab (103:103:103) (132:132:132)) - (PORT datad (330:330:330) (381:381:381)) - (IOPATH dataa combout (166:166:166) (159:159:159)) - (IOPATH datab combout (167:167:167) (158:158:158)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|flags_hf2) - (DELAY - (ABSOLUTE - (PORT clk (900:900:900) (905:905:905)) - (PORT d (37:37:37) (50:50:50)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[2\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (662:662:662) (755:755:755)) - (PORT datab (357:357:357) (420:420:420)) - (PORT datac (641:641:641) (735:735:735)) - (PORT datad (358:358:358) (432:432:432)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_ds\[2\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (665:665:665) (777:777:777)) - (PORT datab (925:925:925) (1052:1052:1052)) - (PORT datac (801:801:801) (932:932:932)) - (PORT datad (471:471:471) (543:543:543)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[2\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (352:352:352) (410:410:410)) - (PORT datab (492:492:492) (569:569:569)) - (PORT datac (349:349:349) (411:411:411)) - (PORT datad (457:457:457) (516:516:516)) + (PORT datac (307:307:307) (358:358:358)) + (PORT datad (114:114:114) (137:137:137)) (IOPATH dataa combout (166:166:166) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[2\]\~27) + (INSTANCE z80_\|bus_control_\|db\[1\]\~10) (DELAY (ABSOLUTE - (PORT dataa (444:444:444) (515:515:515)) - (PORT datab (500:500:500) (573:573:573)) - (PORT datac (215:215:215) (270:270:270)) - (PORT datad (452:452:452) (516:516:516)) + (PORT dataa (299:299:299) (352:352:352)) + (PORT datac (781:781:781) (891:891:891)) + (PORT datad (317:317:317) (367:367:367)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[2\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (363:363:363) (425:425:425)) - (PORT datab (498:498:498) (583:583:583)) - (PORT datac (310:310:310) (358:358:358)) - (PORT datad (163:163:163) (191:191:191)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[2\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (716:716:716) (847:847:847)) - (PORT datab (535:535:535) (629:629:629)) - (PORT datac (498:498:498) (575:575:575)) - (PORT datad (889:889:889) (1031:1031:1031)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[2\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (332:332:332) (389:389:389)) - (PORT datab (546:546:546) (639:639:639)) - (PORT datac (93:93:93) (116:116:116)) - (PORT datad (117:117:117) (147:147:147)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (931:931:931) (1087:1087:1087)) - (PORT datab (497:497:497) (571:571:571)) - (PORT datac (496:496:496) (571:571:571)) - (IOPATH dataa combout (188:188:188) (184:184:184)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (791:791:791) (903:903:903)) - (PORT datab (617:617:617) (717:717:717)) - (PORT datac (88:88:88) (109:109:109)) - (PORT datad (125:125:125) (153:153:153)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[2\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (120:120:120) (158:158:158)) - (PORT datab (133:133:133) (171:171:171)) - (PORT datac (331:331:331) (392:392:392)) - (PORT datad (471:471:471) (545:545:545)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[2\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (285:285:285) (330:330:330)) - (PORT datab (390:390:390) (468:468:468)) - (PORT datac (310:310:310) (356:356:356)) - (PORT datad (481:481:481) (558:558:558)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_low\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (916:916:916) (901:901:901)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (405:405:405) (422:422:422)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[2\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (345:345:345) (415:415:415)) - (PORT datab (626:626:626) (748:748:748)) - (PORT datac (314:314:314) (362:362:362)) - (PORT datad (210:210:210) (258:258:258)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[2\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (144:144:144) (189:189:189)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datac (288:288:288) (335:335:335)) - (PORT datad (502:502:502) (587:587:587)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_low\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (900:900:900)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (420:420:420) (448:448:448)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (247:247:247) (310:310:310)) - (PORT datab (342:342:342) (414:414:414)) - (PORT datac (609:609:609) (701:701:701)) - (PORT datad (367:367:367) (435:435:435)) - (IOPATH dataa combout (165:165:165) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|result_lo\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (901:901:901) (909:909:909)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (676:676:676) (740:740:740)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (174:174:174) (211:211:211)) - (PORT datab (324:324:324) (381:381:381)) - (PORT datac (530:530:530) (629:629:629)) - (PORT datad (317:317:317) (378:378:378)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[2\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (118:118:118) (156:156:156)) - (PORT datab (350:350:350) (411:411:411)) - (PORT datac (497:497:497) (583:583:583)) - (PORT datad (120:120:120) (150:150:150)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[2\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (147:147:147) (195:195:195)) - (PORT datab (306:306:306) (357:357:357)) - (PORT datac (305:305:305) (346:346:346)) - (PORT datad (496:496:496) (581:581:581)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_high\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (900:900:900)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (420:420:420) (448:448:448)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op2\[2\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (245:245:245) (307:307:307)) - (PORT datab (373:373:373) (444:444:444)) - (PORT datac (470:470:470) (548:548:548)) - (PORT datad (223:223:223) (280:280:280)) - (IOPATH dataa combout (188:188:188) (203:203:203)) - (IOPATH datab combout (190:190:190) (205:205:205)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_1) - (DELAY - (ABSOLUTE - (PORT dataa (196:196:196) (237:237:237)) - (PORT datab (203:203:203) (246:246:246)) - (PORT datac (93:93:93) (117:117:117)) - (PORT datad (179:179:179) (209:209:209)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|result\~0) - (DELAY - (ABSOLUTE - (PORT dataa (194:194:194) (233:233:233)) - (PORT datab (102:102:102) (131:131:131)) - (PORT datac (95:95:95) (119:119:119)) - (PORT datad (183:183:183) (219:219:219)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (648:648:648) (752:752:752)) - (PORT datab (152:152:152) (194:194:194)) - (PORT datac (136:136:136) (173:173:173)) - (PORT datad (140:140:140) (170:170:170)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (931:931:931) (1087:1087:1087)) - (PORT datac (486:486:486) (558:558:558)) - (PORT datad (479:479:479) (548:548:548)) - (IOPATH dataa combout (165:165:165) (173:173:173)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~12) - (DELAY - (ABSOLUTE - (PORT datab (102:102:102) (129:129:129)) - (PORT datac (499:499:499) (575:575:575)) - (PORT datad (130:130:130) (158:158:158)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (346:346:346) (419:419:419)) - (PORT datab (649:649:649) (750:750:750)) - (PORT datac (222:222:222) (282:282:282)) - (PORT datad (368:368:368) (436:436:436)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (134:134:134)) - (PORT datab (606:606:606) (705:705:705)) - (PORT datac (320:320:320) (375:375:375)) - (PORT datad (335:335:335) (389:389:389)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (689:689:689) (813:813:813)) - (PORT datab (128:128:128) (167:167:167)) - (PORT datac (521:521:521) (619:619:619)) - (PORT datad (167:167:167) (197:197:197)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[6\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (710:710:710) (839:839:839)) - (PORT datab (536:536:536) (629:629:629)) - (PORT datac (915:915:915) (1056:1056:1056)) - (PORT datad (471:471:471) (544:544:544)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[6\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (342:342:342) (401:401:401)) - (PORT datab (542:542:542) (634:634:634)) - (PORT datac (161:161:161) (194:194:194)) - (PORT datad (123:123:123) (154:154:154)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|out\[6\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (204:204:204) (261:261:261)) - (PORT datab (141:141:141) (189:189:189)) - (PORT datac (128:128:128) (169:169:169)) - (PORT datad (104:104:104) (122:122:122)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|out\[6\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (660:660:660) (752:752:752)) - (PORT datab (344:344:344) (406:406:406)) - (PORT datac (338:338:338) (413:413:413)) - (PORT datad (128:128:128) (170:170:170)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (617:617:617) (716:716:716)) - (PORT datab (499:499:499) (574:574:574)) - (PORT datac (348:348:348) (415:415:415)) - (PORT datad (470:470:470) (539:539:539)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~20) - (DELAY - (ABSOLUTE - (PORT datab (503:503:503) (574:574:574)) - (PORT datac (597:597:597) (687:687:687)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (527:527:527) (617:617:617)) - (PORT datab (520:520:520) (607:607:607)) - (PORT datac (88:88:88) (109:109:109)) - (PORT datad (487:487:487) (555:555:555)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (368:368:368) (430:430:430)) - (PORT datab (104:104:104) (132:132:132)) - (PORT datac (881:881:881) (1001:1001:1001)) - (PORT datad (480:480:480) (538:538:538)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_zero_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (328:328:328) (381:381:381)) - (PORT datab (696:696:696) (795:795:795)) - (PORT datac (627:627:627) (732:732:732)) - (PORT datad (174:174:174) (208:208:208)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\~3) - (DELAY - (ABSOLUTE - (PORT datab (155:155:155) (199:199:199)) - (PORT datad (133:133:133) (164:164:164)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|im1) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (914:914:914)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (911:911:911) (895:895:895)) - (PORT ena (667:667:667) (732:732:732)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_ff_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (666:666:666) (769:769:769)) - (PORT datab (669:669:669) (790:790:790)) - (PORT datac (676:676:676) (800:800:800)) - (PORT datad (147:147:147) (190:190:190)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_ff_oe\~1) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (276:276:276)) - (PORT datab (101:101:101) (130:130:130)) - (PORT datac (631:631:631) (720:720:720)) - (PORT datad (644:644:644) (741:741:741)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[0\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (537:537:537) (643:643:643)) - (PORT datab (644:644:644) (740:740:740)) - (PORT datac (366:366:366) (427:427:427)) - (PORT datad (345:345:345) (403:403:403)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[6\]\~8) - (DELAY - (ABSOLUTE - (PORT datab (471:471:471) (544:544:544)) - (PORT datac (520:520:520) (612:612:612)) - (PORT datad (113:113:113) (136:136:136)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~37) - (DELAY - (ABSOLUTE - (PORT dataa (705:705:705) (831:831:831)) - (PORT datab (1183:1183:1183) (1403:1403:1403)) - (PORT datac (467:467:467) (556:556:556)) - (PORT datad (515:515:515) (607:607:607)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~28) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (133:133:133)) - (PORT datab (694:694:694) (800:800:800)) - (PORT datac (778:778:778) (887:887:887)) - (PORT datad (504:504:504) (590:590:590)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~29) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (134:134:134)) - (PORT datab (130:130:130) (159:159:159)) - (PORT datac (1120:1120:1120) (1313:1313:1313)) - (PORT datad (99:99:99) (120:120:120)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~30) - (DELAY - (ABSOLUTE - (PORT dataa (480:480:480) (563:563:563)) - (PORT datab (119:119:119) (154:154:154)) - (PORT datac (337:337:337) (393:393:393)) - (PORT datad (523:523:523) (610:610:610)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~37) - (DELAY - (ABSOLUTE - (PORT dataa (580:580:580) (677:677:677)) - (PORT datab (604:604:604) (708:708:708)) - (PORT datac (553:553:553) (632:632:632)) - (PORT datad (335:335:335) (389:389:389)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~55) - (DELAY - (ABSOLUTE - (PORT dataa (543:543:543) (646:646:646)) - (PORT datab (608:608:608) (690:690:690)) - (PORT datac (536:536:536) (633:633:633)) - (PORT datad (581:581:581) (648:648:648)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~38) - (DELAY - (ABSOLUTE - (PORT dataa (485:485:485) (562:562:562)) - (PORT datab (106:106:106) (135:135:135)) - (PORT datac (280:280:280) (321:321:321)) - (PORT datad (285:285:285) (327:327:327)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~34) - (DELAY - (ABSOLUTE - (PORT dataa (365:365:365) (427:427:427)) - (PORT datab (500:500:500) (578:578:578)) - (PORT datac (1097:1097:1097) (1249:1249:1249)) - (PORT datad (437:437:437) (502:502:502)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~3) - (DELAY - (ABSOLUTE - (PORT datab (457:457:457) (536:536:536)) - (PORT datac (349:349:349) (411:411:411)) - (PORT datad (108:108:108) (130:130:130)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~31) - (DELAY - (ABSOLUTE - (PORT dataa (122:122:122) (156:156:156)) - (PORT datab (127:127:127) (160:160:160)) - (PORT datac (183:183:183) (220:220:220)) - (PORT datad (582:582:582) (649:649:649)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~32) - (DELAY - (ABSOLUTE - (PORT dataa (403:403:403) (485:485:485)) - (PORT datab (879:879:879) (1005:1005:1005)) - (PORT datac (332:332:332) (392:392:392)) - (PORT datad (288:288:288) (334:334:334)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~33) - (DELAY - (ABSOLUTE - (PORT datab (287:287:287) (334:334:334)) - (PORT datac (729:729:729) (812:812:812)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~35) - (DELAY - (ABSOLUTE - (PORT dataa (576:576:576) (661:661:661)) - (PORT datab (300:300:300) (349:349:349)) - (PORT datac (420:420:420) (472:472:472)) - (PORT datad (417:417:417) (464:464:464)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|DFFE_mrd_ff1) - (DELAY - (ABSOLUTE - (PORT clk (916:916:916) (923:923:923)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (922:922:922) (904:904:904)) - (PORT ena (689:689:689) (767:767:767)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|wait_mrd\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (453:453:453) (528:528:528)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|wait_mrd) - (DELAY - (ABSOLUTE - (PORT clk (923:923:923) (907:907:907)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (925:925:925) (908:908:908)) - (PORT ena (602:602:602) (646:646:646)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|DFFE_mrd_ff3) - (DELAY - (ABSOLUTE - (PORT clk (927:927:927) (912:912:912)) - (PORT asdata (661:661:661) (755:755:755)) - (PORT clrn (922:922:922) (904:904:904)) - (PORT ena (704:704:704) (789:789:789)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|nRD_out\~1) - (DELAY - (ABSOLUTE - (PORT dataa (497:497:497) (601:601:601)) - (PORT datad (116:116:116) (153:153:153)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|nextM\~4) (DELAY (ABSOLUTE - (PORT dataa (125:125:125) (159:159:159)) - (PORT datab (399:399:399) (483:483:483)) - (PORT datac (471:471:471) (548:548:548)) - (PORT datad (606:606:606) (687:687:687)) + (PORT dataa (693:693:693) (810:810:810)) + (PORT datab (362:362:362) (428:428:428)) + (PORT datac (690:690:690) (813:813:813)) + (PORT datad (368:368:368) (434:434:434)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -28844,13 +27547,13 @@ (INSTANCE z80_\|execute_\|ctl_iorw\~12) (DELAY (ABSOLUTE - (PORT dataa (1064:1064:1064) (1229:1229:1229)) - (PORT datab (829:829:829) (953:953:953)) - (PORT datac (830:830:830) (962:962:962)) - (PORT datad (1098:1098:1098) (1256:1256:1256)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) + (PORT dataa (471:471:471) (548:548:548)) + (PORT datab (733:733:733) (885:885:885)) + (PORT datac (481:481:481) (572:572:572)) + (PORT datad (854:854:854) (999:999:999)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -28860,10 +27563,10 @@ (INSTANCE z80_\|execute_\|ctl_iorw\~8) (DELAY (ABSOLUTE - (PORT dataa (619:619:619) (713:713:713)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (105:105:105) (128:128:128)) - (PORT datad (388:388:388) (461:461:461)) + (PORT dataa (695:695:695) (813:813:813)) + (PORT datab (352:352:352) (422:422:422)) + (PORT datac (516:516:516) (592:592:592)) + (PORT datad (365:365:365) (431:431:431)) (IOPATH dataa combout (166:166:166) (157:157:157)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -28876,12 +27579,12 @@ (INSTANCE z80_\|execute_\|ctl_iorw\~9) (DELAY (ABSOLUTE - (PORT dataa (467:467:467) (537:537:537)) - (PORT datab (648:648:648) (746:746:746)) - (PORT datac (457:457:457) (517:517:517)) - (PORT datad (435:435:435) (495:495:495)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT dataa (929:929:929) (1050:1050:1050)) + (PORT datab (638:638:638) (733:733:733)) + (PORT datac (225:225:225) (267:267:267)) + (PORT datad (553:553:553) (620:620:620)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -28892,10 +27595,10 @@ (INSTANCE z80_\|memory_ifc_\|DFFE_iorq_ff1) (DELAY (ABSOLUTE - (PORT clk (916:916:916) (923:923:923)) + (PORT clk (912:912:912) (919:919:919)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (922:922:922) (904:904:904)) - (PORT ena (689:689:689) (767:767:767)) + (PORT clrn (916:916:916) (899:899:899)) + (PORT ena (773:773:773) (846:846:846)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -28905,43 +27608,15 @@ (HOLD ena (posedge clk) (84:84:84)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_15\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (120:120:120) (157:157:157)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_15) (DELAY (ABSOLUTE - (PORT clk (916:916:916) (923:923:923)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (922:922:922) (904:904:904)) - (PORT ena (689:689:689) (767:767:767)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|wait_iorq) - (DELAY - (ABSOLUTE - (PORT clk (927:927:927) (912:912:912)) - (PORT asdata (307:307:307) (347:347:347)) - (PORT clrn (922:922:922) (904:904:904)) - (PORT ena (704:704:704) (789:789:789)) + (PORT clk (912:912:912) (919:919:919)) + (PORT asdata (392:392:392) (443:443:443)) + (PORT clrn (916:916:916) (899:899:899)) + (PORT ena (773:773:773) (846:846:846)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -28951,15 +27626,43 @@ (HOLD ena (posedge clk) (84:84:84)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|wait_iorq\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (122:122:122) (161:161:161)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|wait_iorq) + (DELAY + (ABSOLUTE + (PORT clk (923:923:923) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (916:916:916) (899:899:899)) + (PORT ena (757:757:757) (820:820:820)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|memory_ifc_\|DFFE_iorq_ff4) (DELAY (ABSOLUTE - (PORT clk (927:927:927) (912:912:912)) + (PORT clk (923:923:923) (908:908:908)) (PORT asdata (298:298:298) (339:339:339)) - (PORT clrn (922:922:922) (904:904:904)) - (PORT ena (704:704:704) (789:789:789)) + (PORT clrn (916:916:916) (899:899:899)) + (PORT ena (757:757:757) (820:820:820)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -28975,92 +27678,28 @@ (DELAY (ABSOLUTE (PORT datab (134:134:134) (183:183:183)) - (PORT datad (316:316:316) (377:377:377)) + (PORT datad (122:122:122) (161:161:161)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIORead\~1) - (DELAY - (ABSOLUTE - (PORT dataa (116:116:116) (146:146:146)) - (PORT datab (542:542:542) (637:637:637)) - (PORT datac (192:192:192) (230:230:230)) - (PORT datad (118:118:118) (135:135:135)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIORead\~2) - (DELAY - (ABSOLUTE - (PORT dataa (476:476:476) (554:554:554)) - (PORT datab (112:112:112) (144:144:144)) - (PORT datac (659:659:659) (755:755:755)) - (PORT datad (604:604:604) (693:693:693)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIORead\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1045:1045:1045) (1187:1187:1187)) - (PORT datab (859:859:859) (999:999:999)) - (PORT datac (1202:1202:1202) (1386:1386:1386)) - (PORT datad (113:113:113) (135:135:135)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIORead\~3) - (DELAY - (ABSOLUTE - (PORT dataa (115:115:115) (145:145:145)) - (PORT datab (173:173:173) (211:211:211)) - (PORT datac (305:305:305) (347:347:347)) - (PORT datad (188:188:188) (222:222:222)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|memory_ifc_\|DFFE_m1_ff1) (DELAY (ABSOLUTE - (PORT clk (924:924:924) (910:910:910)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (920:920:920) (902:902:902)) - (PORT ena (983:983:983) (1112:1112:1112)) + (PORT clk (923:923:923) (908:908:908)) + (PORT asdata (484:484:484) (518:518:518)) + (PORT clrn (916:916:916) (899:899:899)) + (PORT ena (757:757:757) (820:820:820)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) (HOLD ena (posedge clk) (84:84:84)) ) ) @@ -29069,7 +27708,7 @@ (INSTANCE z80_\|memory_ifc_\|wait_m_ALTERA_SYNTHESIZED1\~0) (DELAY (ABSOLUTE - (PORT datad (309:309:309) (371:371:371)) + (PORT datad (120:120:120) (158:158:158)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -29079,10 +27718,10 @@ (INSTANCE z80_\|memory_ifc_\|wait_m_ALTERA_SYNTHESIZED1) (DELAY (ABSOLUTE - (PORT clk (927:927:927) (912:912:912)) + (PORT clk (923:923:923) (908:908:908)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (922:922:922) (904:904:904)) - (PORT ena (704:704:704) (789:789:789)) + (PORT clrn (916:916:916) (899:899:899)) + (PORT ena (757:757:757) (820:820:820)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -29097,10 +27736,10 @@ (INSTANCE z80_\|memory_ifc_\|DFFE_m1_ff3) (DELAY (ABSOLUTE - (PORT clk (916:916:916) (923:923:923)) - (PORT asdata (298:298:298) (340:340:340)) - (PORT clrn (922:922:922) (904:904:904)) - (PORT ena (689:689:689) (767:767:767)) + (PORT clk (912:912:912) (919:919:919)) + (PORT asdata (299:299:299) (341:341:341)) + (PORT clrn (916:916:916) (899:899:899)) + (PORT ena (773:773:773) (846:846:846)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -29115,12 +27754,330 @@ (INSTANCE z80_\|memory_ifc_\|nRD_out\~0) (DELAY (ABSOLUTE - (PORT dataa (805:805:805) (940:940:940)) - (PORT datab (134:134:134) (184:184:184)) - (PORT datad (824:824:824) (959:959:959)) + (PORT dataa (135:135:135) (188:188:188)) + (PORT datab (381:381:381) (463:463:463)) + (PORT datad (482:482:482) (570:570:570)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIORead\~0) + (DELAY + (ABSOLUTE + (PORT dataa (712:712:712) (834:834:834)) + (PORT datab (1237:1237:1237) (1407:1407:1407)) + (PORT datac (595:595:595) (687:687:687)) + (PORT datad (1240:1240:1240) (1449:1449:1449)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIORead\~1) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (438:438:438)) + (PORT datab (911:911:911) (1076:1076:1076)) + (PORT datac (928:928:928) (1063:1063:1063)) + (PORT datad (102:102:102) (119:119:119)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIORead\~2) + (DELAY + (ABSOLUTE + (PORT dataa (943:943:943) (1086:1086:1086)) + (PORT datab (119:119:119) (149:149:149)) + (PORT datac (89:89:89) (110:110:110)) + (PORT datad (637:637:637) (725:725:725)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIOWrite\~1) + (DELAY + (ABSOLUTE + (PORT dataa (372:372:372) (452:452:452)) + (PORT datac (547:547:547) (658:658:658)) + (PORT datad (103:103:103) (120:120:120)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIORead\~3) + (DELAY + (ABSOLUTE + (PORT dataa (689:689:689) (804:804:804)) + (PORT datab (354:354:354) (422:422:422)) + (PORT datac (744:744:744) (846:846:846)) + (PORT datad (94:94:94) (113:113:113)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~30) + (DELAY + (ABSOLUTE + (PORT dataa (630:630:630) (722:722:722)) + (PORT datab (749:749:749) (861:861:861)) + (PORT datac (813:813:813) (935:935:935)) + (PORT datad (722:722:722) (822:822:822)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~31) + (DELAY + (ABSOLUTE + (PORT dataa (528:528:528) (609:609:609)) + (PORT datac (319:319:319) (378:378:378)) + (PORT datad (475:475:475) (545:545:545)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~3) + (DELAY + (ABSOLUTE + (PORT dataa (660:660:660) (763:763:763)) + (PORT datab (188:188:188) (235:235:235)) + (PORT datac (901:901:901) (1050:1050:1050)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~29) + (DELAY + (ABSOLUTE + (PORT dataa (123:123:123) (157:157:157)) + (PORT datab (650:650:650) (774:774:774)) + (PORT datac (497:497:497) (583:583:583)) + (PORT datad (708:708:708) (819:819:819)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~58) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (194:194:194)) + (PORT datab (151:151:151) (198:198:198)) + (PORT datac (321:321:321) (366:366:366)) + (PORT datad (440:440:440) (502:502:502)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~38) + (DELAY + (ABSOLUTE + (PORT datac (492:492:492) (563:563:563)) + (PORT datad (96:96:96) (116:116:116)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~4) + (DELAY + (ABSOLUTE + (PORT dataa (639:639:639) (740:740:740)) + (PORT datab (352:352:352) (413:413:413)) + (PORT datad (338:338:338) (390:390:390)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~39) + (DELAY + (ABSOLUTE + (PORT dataa (615:615:615) (716:716:716)) + (PORT datac (458:458:458) (519:519:519)) + (PORT datad (1120:1120:1120) (1286:1286:1286)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~40) + (DELAY + (ABSOLUTE + (PORT dataa (480:480:480) (573:573:573)) + (PORT datab (505:505:505) (583:583:583)) + (PORT datac (89:89:89) (110:110:110)) + (PORT datad (459:459:459) (546:546:546)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~32) + (DELAY + (ABSOLUTE + (PORT dataa (114:114:114) (147:147:147)) + (PORT datab (519:519:519) (599:599:599)) + (PORT datac (180:180:180) (214:214:214)) + (PORT datad (185:185:185) (216:216:216)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~33) + (DELAY + (ABSOLUTE + (PORT dataa (194:194:194) (231:231:231)) + (PORT datab (383:383:383) (452:452:452)) + (PORT datac (735:735:735) (844:844:844)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|DFFE_mrd_ff1) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (907:907:907)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (904:904:904) (890:890:890)) + (PORT ena (783:783:783) (853:853:853)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|wait_mrd\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (505:505:505) (596:596:596)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|wait_mrd) + (DELAY + (ABSOLUTE + (PORT clk (923:923:923) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (916:916:916) (899:899:899)) + (PORT ena (757:757:757) (820:820:820)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|DFFE_mrd_ff3) + (DELAY + (ABSOLUTE + (PORT clk (923:923:923) (908:908:908)) + (PORT asdata (304:304:304) (349:349:349)) + (PORT clrn (916:916:916) (899:899:899)) + (PORT ena (757:757:757) (820:820:820)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|nRD_out\~1) + (DELAY + (ABSOLUTE + (PORT datac (128:128:128) (175:175:175)) + (PORT datad (117:117:117) (153:153:153)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -29130,10 +28087,120 @@ (INSTANCE z80_\|memory_ifc_\|nRD_out\~2) (DELAY (ABSOLUTE - (PORT dataa (174:174:174) (214:214:214)) - (PORT datab (183:183:183) (225:225:225)) - (PORT datac (557:557:557) (634:634:634)) - (PORT datad (94:94:94) (112:112:112)) + (PORT dataa (188:188:188) (227:227:227)) + (PORT datab (182:182:182) (218:218:218)) + (PORT datac (327:327:327) (372:372:372)) + (PORT datad (167:167:167) (196:196:196)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIOWrite\~3) + (DELAY + (ABSOLUTE + (PORT datab (879:879:879) (1050:1050:1050)) + (PORT datac (550:550:550) (661:661:661)) + (PORT datad (362:362:362) (428:428:428)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIOWrite\~4) + (DELAY + (ABSOLUTE + (PORT dataa (567:567:567) (651:651:651)) + (PORT datab (366:366:366) (426:426:426)) + (PORT datac (92:92:92) (115:115:115)) + (PORT datad (573:573:573) (645:645:645)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIOWrite\~2) + (DELAY + (ABSOLUTE + (PORT dataa (711:711:711) (833:833:833)) + (PORT datab (618:618:618) (736:736:736)) + (PORT datac (472:472:472) (546:546:546)) + (PORT datad (878:878:878) (1011:1011:1011)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIOWrite\~5) + (DELAY + (ABSOLUTE + (PORT dataa (556:556:556) (653:653:653)) + (PORT datab (105:105:105) (134:134:134)) + (PORT datac (321:321:321) (375:375:375)) + (PORT datad (94:94:94) (113:113:113)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~15) + (DELAY + (ABSOLUTE + (PORT dataa (838:838:838) (978:978:978)) + (PORT datab (483:483:483) (569:569:569)) + (PORT datac (373:373:373) (442:442:442)) + (PORT datad (179:179:179) (213:213:213)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~12) + (DELAY + (ABSOLUTE + (PORT dataa (401:401:401) (476:476:476)) + (PORT datab (351:351:351) (422:422:422)) + (PORT datac (327:327:327) (373:373:373)) + (PORT datad (180:180:180) (212:212:212)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~13) + (DELAY + (ABSOLUTE + (PORT dataa (671:671:671) (768:768:768)) + (PORT datab (318:318:318) (369:369:369)) + (PORT datac (325:325:325) (383:383:383)) + (PORT datad (538:538:538) (625:625:625)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -29141,58 +28208,169 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~14) + (DELAY + (ABSOLUTE + (PORT dataa (323:323:323) (381:381:381)) + (PORT datab (343:343:343) (405:405:405)) + (PORT datac (89:89:89) (109:109:109)) + (PORT datad (350:350:350) (404:404:404)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~16) + (DELAY + (ABSOLUTE + (PORT dataa (472:472:472) (550:550:550)) + (PORT datab (481:481:481) (575:575:575)) + (PORT datac (563:563:563) (657:657:657)) + (PORT datad (516:516:516) (597:597:597)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|DFFE_mwr_ff1) + (DELAY + (ABSOLUTE + (PORT clk (912:912:912) (919:919:919)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (916:916:916) (899:899:899)) + (PORT ena (773:773:773) (846:846:846)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|wait_mwr\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (119:119:119) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|wait_mwr) + (DELAY + (ABSOLUTE + (PORT clk (923:923:923) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (916:916:916) (899:899:899)) + (PORT ena (757:757:757) (820:820:820)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|mwr_wr) + (DELAY + (ABSOLUTE + (PORT clk (923:923:923) (908:908:908)) + (PORT asdata (298:298:298) (338:338:338)) + (PORT clrn (916:916:916) (899:899:899)) + (PORT ena (757:757:757) (820:820:820)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|nWR_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (349:349:349) (409:409:409)) + (PORT datab (116:116:116) (144:144:144)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE Equal2\~1) (DELAY (ABSOLUTE - (PORT dataa (975:975:975) (1134:1134:1134)) - (PORT datab (898:898:898) (1064:1064:1064)) - (PORT datac (659:659:659) (776:776:776)) - (IOPATH dataa combout (158:158:158) (157:157:157)) + (PORT datab (1548:1548:1548) (1821:1821:1821)) + (PORT datac (286:286:286) (331:331:331)) + (PORT datad (312:312:312) (368:368:368)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1334:1334:1334) (1561:1561:1561)) - (PORT datad (572:572:572) (677:677:677)) - (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~5) + (INSTANCE z80_\|execute_\|fMWrite\~3) (DELAY (ABSOLUTE - (PORT datab (745:745:745) (882:882:882)) - (PORT datac (1646:1646:1646) (1901:1901:1901)) - (PORT datad (1457:1457:1457) (1728:1728:1728)) + (PORT dataa (686:686:686) (802:802:802)) + (PORT datab (827:827:827) (974:974:974)) + (PORT datac (990:990:990) (1161:1161:1161)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~4) + (DELAY + (ABSOLUTE + (PORT dataa (116:116:116) (147:147:147)) + (PORT datab (662:662:662) (765:765:765)) + (PORT datac (649:649:649) (747:747:747)) + (PORT datad (499:499:499) (574:574:574)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~6) + (INSTANCE z80_\|execute_\|fMWrite\~0) (DELAY (ABSOLUTE - (PORT dataa (193:193:193) (230:230:230)) - (PORT datab (470:470:470) (547:547:547)) - (PORT datac (546:546:546) (629:629:629)) - (PORT datad (576:576:576) (646:646:646)) + (PORT dataa (1153:1153:1153) (1345:1345:1345)) + (PORT datac (882:882:882) (1045:1045:1045)) + (PORT datad (837:837:837) (978:978:978)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -29202,59 +28380,13 @@ (INSTANCE z80_\|execute_\|fMWrite\~2) (DELAY (ABSOLUTE - (PORT dataa (516:516:516) (617:617:617)) - (PORT datac (650:650:650) (757:757:757)) - (PORT datad (1146:1146:1146) (1341:1341:1341)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~4) - (DELAY - (ABSOLUTE - (PORT dataa (781:781:781) (907:907:907)) - (PORT datab (509:509:509) (601:601:601)) - (PORT datac (185:185:185) (217:217:217)) - (PORT datad (101:101:101) (118:118:118)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~1) - (DELAY - (ABSOLUTE - (PORT dataa (374:374:374) (446:446:446)) - (PORT datab (450:450:450) (528:528:528)) - (PORT datac (462:462:462) (539:539:539)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~2) - (DELAY - (ABSOLUTE - (PORT dataa (719:719:719) (828:828:828)) - (PORT datab (468:468:468) (534:534:534)) - (PORT datac (714:714:714) (810:810:810)) - (PORT datad (352:352:352) (411:411:411)) + (PORT dataa (687:687:687) (806:806:806)) + (PORT datab (106:106:106) (135:135:135)) + (PORT datac (958:958:958) (1122:1122:1122)) + (PORT datad (722:722:722) (847:847:847)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -29264,12 +28396,28 @@ (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~3) (DELAY (ABSOLUTE - (PORT dataa (102:102:102) (134:134:134)) - (PORT datab (590:590:590) (677:677:677)) - (PORT datac (191:191:191) (226:226:226)) - (PORT datad (1006:1006:1006) (1174:1174:1174)) + (PORT dataa (177:177:177) (215:215:215)) + (PORT datab (519:519:519) (605:605:605)) + (PORT datac (321:321:321) (376:376:376)) + (PORT datad (973:973:973) (1118:1118:1118)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~8) + (DELAY + (ABSOLUTE + (PORT dataa (538:538:538) (642:642:642)) + (PORT datab (691:691:691) (805:805:805)) + (PORT datac (577:577:577) (659:659:659)) + (PORT datad (650:650:650) (740:740:740)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -29280,40 +28428,26 @@ (INSTANCE z80_\|execute_\|fMWrite\~7) (DELAY (ABSOLUTE - (PORT datab (500:500:500) (588:588:588)) - (PORT datac (481:481:481) (557:557:557)) - (PORT datad (407:407:407) (466:466:466)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) + (PORT dataa (512:512:512) (600:600:600)) + (PORT datab (577:577:577) (680:680:680)) + (PORT datac (646:646:646) (748:748:748)) + (PORT datad (615:615:615) (697:697:697)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~4) + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~16) (DELAY (ABSOLUTE - (PORT dataa (866:866:866) (995:995:995)) - (PORT datab (105:105:105) (134:134:134)) - (PORT datac (940:940:940) (1095:1095:1095)) - (PORT datad (482:482:482) (558:558:558)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~7) - (DELAY - (ABSOLUTE - (PORT dataa (787:787:787) (919:919:919)) - (PORT datab (636:636:636) (729:729:729)) - (PORT datac (472:472:472) (558:558:558)) - (PORT datad (407:407:407) (465:465:465)) + (PORT dataa (347:347:347) (414:414:414)) + (PORT datab (631:631:631) (734:734:734)) + (PORT datac (945:945:945) (1093:1093:1093)) + (PORT datad (1140:1140:1140) (1320:1320:1320)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (125:125:125)) @@ -29321,50 +28455,34 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~6) - (DELAY - (ABSOLUTE - (PORT dataa (865:865:865) (994:994:994)) - (PORT datab (632:632:632) (739:739:739)) - (PORT datac (605:605:605) (693:693:693)) - (PORT datad (332:332:332) (389:389:389)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~9) - (DELAY - (ABSOLUTE - (PORT dataa (696:696:696) (827:827:827)) - (PORT datab (475:475:475) (551:551:551)) - (PORT datac (943:943:943) (1088:1088:1088)) - (PORT datad (143:143:143) (178:178:178)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~8) (DELAY (ABSOLUTE - (PORT dataa (631:631:631) (726:726:726)) - (PORT datab (112:112:112) (143:143:143)) - (PORT datac (101:101:101) (123:123:123)) - (PORT datad (343:343:343) (401:401:401)) + (PORT dataa (743:743:743) (873:873:873)) + (PORT datab (349:349:349) (412:412:412)) + (PORT datac (946:946:946) (1103:1103:1103)) + (PORT datad (633:633:633) (740:740:740)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~6) + (DELAY + (ABSOLUTE + (PORT dataa (564:564:564) (688:688:688)) + (PORT datab (596:596:596) (722:722:722)) + (PORT datac (392:392:392) (470:470:470)) + (PORT datad (616:616:616) (711:711:711)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -29374,26 +28492,12 @@ (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~9) (DELAY (ABSOLUTE - (PORT dataa (105:105:105) (137:137:137)) - (PORT datab (118:118:118) (147:147:147)) - (PORT datac (574:574:574) (650:650:650)) + (PORT dataa (349:349:349) (410:410:410)) + (PORT datab (495:495:495) (572:572:572)) + (PORT datac (512:512:512) (589:589:589)) + (PORT datad (96:96:96) (116:116:116)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~8) - (DELAY - (ABSOLUTE - (PORT dataa (590:590:590) (673:673:673)) - (PORT datab (466:466:466) (542:542:542)) - (PORT datac (326:326:326) (377:377:377)) - (PORT datad (657:657:657) (763:763:763)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -29401,16 +28505,16 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~5) + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~7) (DELAY (ABSOLUTE - (PORT dataa (491:491:491) (584:584:584)) - (PORT datab (107:107:107) (137:137:137)) - (PORT datac (314:314:314) (362:362:362)) - (PORT datad (105:105:105) (123:123:123)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (PORT dataa (940:940:940) (1069:1069:1069)) + (PORT datab (343:343:343) (403:403:403)) + (PORT datac (688:688:688) (800:800:800)) + (PORT datad (517:517:517) (605:605:605)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -29420,10 +28524,10 @@ (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~10) (DELAY (ABSOLUTE - (PORT dataa (104:104:104) (135:135:135)) - (PORT datab (104:104:104) (133:133:133)) - (PORT datac (168:168:168) (200:200:200)) - (PORT datad (439:439:439) (509:509:509)) + (PORT dataa (104:104:104) (136:136:136)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (89:89:89) (110:110:110)) + (PORT datad (92:92:92) (110:110:110)) (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -29431,34 +28535,48 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~10) - (DELAY - (ABSOLUTE - (PORT dataa (477:477:477) (549:549:549)) - (PORT datab (578:578:578) (685:685:685)) - (PORT datac (604:604:604) (692:692:692)) - (PORT datad (616:616:616) (702:702:702)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~11) (DELAY (ABSOLUTE - (PORT dataa (107:107:107) (139:139:139)) - (PORT datab (104:104:104) (133:133:133)) - (PORT datac (91:91:91) (113:113:113)) - (PORT datad (96:96:96) (115:115:115)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (PORT dataa (602:602:602) (691:691:691)) + (PORT datab (334:334:334) (393:393:393)) + (PORT datac (786:786:786) (899:899:899)) + (PORT datad (339:339:339) (394:394:394)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~5) + (DELAY + (ABSOLUTE + (PORT dataa (821:821:821) (946:946:946)) + (PORT datab (703:703:703) (815:815:815)) + (PORT datac (509:509:509) (588:588:588)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~6) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (137:137:137)) + (PORT datab (111:111:111) (142:142:142)) + (PORT datac (697:697:697) (816:816:816)) + (PORT datad (1117:1117:1117) (1304:1304:1304)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -29468,13 +28586,45 @@ (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~12) (DELAY (ABSOLUTE - (PORT dataa (302:302:302) (352:352:352)) - (PORT datab (606:606:606) (708:708:708)) - (PORT datac (940:940:940) (1096:1096:1096)) - (PORT datad (93:93:93) (111:111:111)) - (IOPATH dataa combout (166:166:166) (163:163:163)) + (PORT dataa (370:370:370) (439:439:439)) + (PORT datab (354:354:354) (422:422:422)) + (PORT datac (501:501:501) (584:584:584)) + (PORT datad (89:89:89) (107:107:107)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~4) + (DELAY + (ABSOLUTE + (PORT dataa (206:206:206) (243:243:243)) + (PORT datab (812:812:812) (934:934:934)) + (PORT datac (352:352:352) (423:423:423)) + (PORT datad (844:844:844) (978:978:978)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~5) + (DELAY + (ABSOLUTE + (PORT dataa (980:980:980) (1146:1146:1146)) + (PORT datab (664:664:664) (768:768:768)) + (PORT datac (332:332:332) (387:387:387)) + (PORT datad (467:467:467) (532:532:532)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -29484,13 +28634,13 @@ (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~13) (DELAY (ABSOLUTE - (PORT dataa (376:376:376) (440:440:440)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (327:327:327) (385:385:385)) - (PORT datad (103:103:103) (121:121:121)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT dataa (103:103:103) (133:133:133)) + (PORT datab (539:539:539) (630:630:630)) + (PORT datac (673:673:673) (784:784:784)) + (PORT datad (1117:1117:1117) (1305:1305:1305)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -29500,12 +28650,40 @@ (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~14) (DELAY (ABSOLUTE - (PORT dataa (102:102:102) (133:133:133)) - (PORT datab (498:498:498) (581:581:581)) - (PORT datac (597:597:597) (720:720:720)) - (PORT datad (637:637:637) (733:733:733)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (PORT dataa (322:322:322) (379:379:379)) + (PORT datab (518:518:518) (602:602:602)) + (PORT datac (325:325:325) (374:374:374)) + (PORT datad (318:318:318) (361:361:361)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~2) + (DELAY + (ABSOLUTE + (PORT datab (553:553:553) (660:660:660)) + (PORT datad (520:520:520) (613:613:613)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~15) + (DELAY + (ABSOLUTE + (PORT dataa (757:757:757) (864:864:864)) + (PORT datab (177:177:177) (216:216:216)) + (PORT datac (89:89:89) (111:111:111)) + (PORT datad (357:357:357) (423:423:423)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -29516,7 +28694,7 @@ (INSTANCE z80_\|clk_delay_\|DFF_inst5\~feeder) (DELAY (ABSOLUTE - (PORT datad (120:120:120) (159:159:159)) + (PORT datad (734:734:734) (843:843:843)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -29526,9 +28704,9 @@ (INSTANCE z80_\|clk_delay_\|DFF_inst5) (DELAY (ABSOLUTE - (PORT clk (910:910:910) (917:917:917)) + (PORT clk (902:902:902) (909:909:909)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (924:924:924) (906:906:906)) + (PORT clrn (905:905:905) (889:889:889)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -29537,30 +28715,20 @@ (HOLD d (posedge clk) (84:84:84)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|wait_iorqinta\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (124:124:124) (164:164:164)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|memory_ifc_\|wait_iorqinta) (DELAY (ABSOLUTE - (PORT clk (921:921:921) (906:906:906)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (924:924:924) (906:906:906)) + (PORT clk (923:923:923) (907:907:907)) + (PORT asdata (812:812:812) (917:917:917)) + (PORT clrn (915:915:915) (899:899:899)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) ) ) (CELL @@ -29568,9 +28736,9 @@ (INSTANCE z80_\|memory_ifc_\|DFFE_intr_ff3) (DELAY (ABSOLUTE - (PORT clk (910:910:910) (917:917:917)) - (PORT asdata (299:299:299) (342:342:342)) - (PORT clrn (924:924:924) (906:906:906)) + (PORT clk (911:911:911) (919:919:919)) + (PORT asdata (300:300:300) (342:342:342)) + (PORT clrn (915:915:915) (899:899:899)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -29584,11 +28752,11 @@ (INSTANCE z80_\|memory_ifc_\|nIORQ_out\~0) (DELAY (ABSOLUTE - (PORT dataa (136:136:136) (189:189:189)) - (PORT datad (334:334:334) (390:390:390)) + (PORT dataa (293:293:293) (334:334:334)) + (PORT datab (136:136:136) (187:187:187)) (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) @@ -29597,28 +28765,12 @@ (INSTANCE Equal2\~0) (DELAY (ABSOLUTE - (PORT dataa (977:977:977) (1136:1136:1136)) - (PORT datab (898:898:898) (1063:1063:1063)) - (PORT datac (658:658:658) (774:774:774)) - (PORT datad (680:680:680) (795:795:795)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ExtRamWE\~0) - (DELAY - (ABSOLUTE - (PORT dataa (976:976:976) (1134:1134:1134)) - (PORT datab (898:898:898) (1064:1064:1064)) - (PORT datac (659:659:659) (775:775:775)) - (PORT datad (679:679:679) (794:794:794)) + (PORT dataa (130:130:130) (167:167:167)) + (PORT datab (1550:1550:1550) (1823:1823:1823)) + (PORT datac (284:284:284) (328:328:328)) + (PORT datad (311:311:311) (367:367:367)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -29626,12 +28778,26 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[13\]\~13) + (INSTANCE z80_\|execute_\|ctl_apin_mux\~2) (DELAY (ABSOLUTE - (PORT dataa (964:964:964) (1095:1095:1095)) - (PORT datab (451:451:451) (522:522:522)) - (PORT datad (171:171:171) (201:201:201)) + (PORT dataa (476:476:476) (551:551:551)) + (PORT datac (822:822:822) (930:930:930)) + (PORT datad (488:488:488) (576:576:576)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[10\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (797:797:797) (913:913:913)) + (PORT datab (276:276:276) (320:320:320)) + (PORT datad (163:163:163) (192:192:192)) (IOPATH dataa combout (172:172:172) (165:165:165)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -29643,651 +28809,55 @@ (INSTANCE z80_\|execute_\|ctl_apin_mux2\~0) (DELAY (ABSOLUTE - (PORT dataa (514:514:514) (616:616:616)) - (PORT datab (539:539:539) (651:651:651)) - (PORT datac (1077:1077:1077) (1266:1266:1266)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_ab_pin_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (941:941:941) (1117:1117:1117)) - (PORT datab (543:543:543) (633:633:633)) - (PORT datac (535:535:535) (624:624:624)) - (PORT datad (683:683:683) (785:785:785)) + (PORT dataa (1115:1115:1115) (1287:1287:1287)) + (PORT datab (936:936:936) (1093:1093:1093)) + (PORT datac (847:847:847) (1014:1014:1014)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_ab_pin_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (513:513:513) (615:615:615)) - (PORT datab (540:540:540) (651:651:651)) - (PORT datac (1077:1077:1077) (1266:1266:1266)) - (PORT datad (341:341:341) (400:400:400)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[13\]) - (DELAY - (ABSOLUTE - (PORT clk (918:918:918) (905:905:905)) - (PORT d (37:37:37) (50:50:50)) - (PORT asdata (319:319:319) (365:365:365)) - (PORT sload (583:583:583) (639:639:639)) - (PORT ena (599:599:599) (635:635:635)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sload (posedge clk) (84:84:84)) - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[13\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (645:645:645) (755:755:755)) - (PORT datad (1152:1152:1152) (1332:1332:1332)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[14\]\~14) + (INSTANCE z80_\|pin_control_\|bus_ab_pin_we\~0) (DELAY (ABSOLUTE - (PORT dataa (963:963:963) (1094:1094:1094)) - (PORT datab (115:115:115) (142:142:142)) - (PORT datad (164:164:164) (189:189:189)) - (IOPATH dataa combout (172:172:172) (165:165:165)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[14\]) - (DELAY - (ABSOLUTE - (PORT clk (918:918:918) (905:905:905)) - (PORT d (37:37:37) (50:50:50)) - (PORT asdata (313:313:313) (356:356:356)) - (PORT sload (583:583:583) (639:639:639)) - (PORT ena (599:599:599) (635:635:635)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sload (posedge clk) (84:84:84)) - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[14\]\~23) - (DELAY - (ABSOLUTE - (PORT datab (1165:1165:1165) (1354:1354:1354)) - (PORT datad (628:628:628) (735:735:735)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[15\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (966:966:966) (1097:1097:1097)) - (PORT datab (173:173:173) (212:212:212)) - (PORT datad (282:282:282) (323:323:323)) - (IOPATH dataa combout (166:166:166) (159:159:159)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[15\]) - (DELAY - (ABSOLUTE - (PORT clk (918:918:918) (905:905:905)) - (PORT d (37:37:37) (50:50:50)) - (PORT asdata (305:305:305) (349:349:349)) - (PORT sload (583:583:583) (639:639:639)) - (PORT ena (599:599:599) (635:635:635)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sload (posedge clk) (84:84:84)) - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[15\]\~22) - (DELAY - (ABSOLUTE - (PORT datab (915:915:915) (1073:1073:1073)) - (PORT datac (840:840:840) (974:974:974)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode236w\[2\]) - (DELAY - (ABSOLUTE - (PORT dataa (368:368:368) (445:445:445)) - (PORT datab (139:139:139) (177:177:177)) - (PORT datac (191:191:191) (232:232:232)) - (PORT datad (702:702:702) (789:789:789)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|rden_decode\|w_anode284w\[2\]\~0) - (DELAY - (ABSOLUTE - (PORT datab (1159:1159:1159) (1347:1347:1347)) - (PORT datac (617:617:617) (726:726:726)) - (PORT datad (626:626:626) (733:733:733)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[0\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (499:499:499) (592:592:592)) - (PORT datad (1119:1119:1119) (1292:1292:1292)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[1\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (459:459:459) (534:534:534)) - (PORT datab (189:189:189) (226:226:226)) - (PORT datad (173:173:173) (195:195:195)) - (IOPATH dataa combout (172:172:172) (165:165:165)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (931:931:931) (916:916:916)) - (PORT d (37:37:37) (50:50:50)) - (PORT asdata (586:586:586) (648:648:648)) - (PORT sload (640:640:640) (715:715:715)) - (PORT ena (763:763:763) (829:829:829)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sload (posedge clk) (84:84:84)) - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[1\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (1006:1006:1006) (1180:1180:1180)) - (PORT datad (359:359:359) (438:438:438)) + (PORT dataa (543:543:543) (646:646:646)) + (PORT datab (120:120:120) (149:149:149)) + (PORT datad (745:745:745) (839:839:839)) (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[2\]\~2) + (INSTANCE z80_\|pin_control_\|bus_ab_pin_we\~1) (DELAY (ABSOLUTE - (PORT dataa (461:461:461) (536:536:536)) - (PORT datab (316:316:316) (363:363:363)) - (PORT datad (277:277:277) (315:315:315)) - (IOPATH dataa combout (166:166:166) (159:159:159)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (931:931:931) (916:916:916)) - (PORT d (37:37:37) (50:50:50)) - (PORT asdata (518:518:518) (582:582:582)) - (PORT sload (640:640:640) (715:715:715)) - (PORT ena (763:763:763) (829:829:829)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sload (posedge clk) (84:84:84)) - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[2\]\~26) - (DELAY - (ABSOLUTE - (PORT datac (980:980:980) (1153:1153:1153)) - (PORT datad (345:345:345) (415:415:415)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[3\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (465:465:465) (541:541:541)) - (PORT datab (276:276:276) (318:318:318)) - (PORT datad (171:171:171) (203:203:203)) - (IOPATH dataa combout (166:166:166) (159:159:159)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (931:931:931) (916:916:916)) - (PORT d (37:37:37) (50:50:50)) - (PORT asdata (390:390:390) (439:439:439)) - (PORT sload (640:640:640) (715:715:715)) - (PORT ena (763:763:763) (829:829:829)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sload (posedge clk) (84:84:84)) - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[3\]\~27) - (DELAY - (ABSOLUTE - (PORT datac (986:986:986) (1159:1159:1159)) - (PORT datad (193:193:193) (241:241:241)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[4\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (459:459:459) (533:533:533)) - (PORT datab (278:278:278) (323:323:323)) - (PORT datad (172:172:172) (204:204:204)) - (IOPATH dataa combout (166:166:166) (159:159:159)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (931:931:931) (916:916:916)) - (PORT d (37:37:37) (50:50:50)) - (PORT asdata (516:516:516) (572:572:572)) - (PORT sload (640:640:640) (715:715:715)) - (PORT ena (763:763:763) (829:829:829)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sload (posedge clk) (84:84:84)) - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[4\]\~28) - (DELAY - (ABSOLUTE - (PORT datac (989:989:989) (1163:1163:1163)) - (PORT datad (350:350:350) (423:423:423)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[5\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (737:737:737) (848:848:848)) - (PORT datab (173:173:173) (212:212:212)) - (PORT datad (104:104:104) (122:122:122)) - (IOPATH dataa combout (166:166:166) (159:159:159)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (918:918:918) (905:905:905)) - (PORT d (37:37:37) (50:50:50)) - (PORT asdata (522:522:522) (598:598:598)) - (PORT sload (591:591:591) (660:660:660)) - (PORT ena (606:606:606) (650:650:650)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sload (posedge clk) (84:84:84)) - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[5\]\~29) - (DELAY - (ABSOLUTE - (PORT datab (1121:1121:1121) (1302:1302:1302)) - (PORT datac (365:365:365) (442:442:442)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[6\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (135:135:135)) - (PORT datab (115:115:115) (143:143:143)) - (PORT datad (723:723:723) (822:822:822)) + (PORT dataa (573:573:573) (655:655:655)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (859:859:859) (1030:1030:1030)) + (PORT datad (474:474:474) (551:551:551)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (918:918:918) (905:905:905)) - (PORT d (37:37:37) (50:50:50)) - (PORT asdata (601:601:601) (673:673:673)) - (PORT sload (591:591:591) (660:660:660)) - (PORT ena (606:606:606) (650:650:650)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sload (posedge clk) (84:84:84)) - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[6\]\~30) - (DELAY - (ABSOLUTE - (PORT datab (385:385:385) (466:466:466)) - (PORT datac (980:980:980) (1152:1152:1152)) (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[7\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (740:740:740) (852:852:852)) - (PORT datab (105:105:105) (134:134:134)) - (PORT datad (102:102:102) (119:119:119)) - (IOPATH dataa combout (166:166:166) (159:159:159)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (918:918:918) (905:905:905)) - (PORT d (37:37:37) (50:50:50)) - (PORT asdata (866:866:866) (977:977:977)) - (PORT sload (591:591:591) (660:660:660)) - (PORT ena (606:606:606) (650:650:650)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sload (posedge clk) (84:84:84)) - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[7\]\~31) - (DELAY - (ABSOLUTE - (PORT datac (981:981:981) (1154:1154:1154)) - (PORT datad (513:513:513) (600:600:600)) (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[8\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (176:176:176) (217:217:217)) - (PORT datab (737:737:737) (840:840:840)) - (PORT datad (104:104:104) (122:122:122)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (167:167:167) (158:158:158)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[8\]) - (DELAY - (ABSOLUTE - (PORT clk (918:918:918) (905:905:905)) - (PORT d (37:37:37) (50:50:50)) - (PORT asdata (316:316:316) (360:360:360)) - (PORT sload (591:591:591) (660:660:660)) - (PORT ena (606:606:606) (650:650:650)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sload (posedge clk) (84:84:84)) - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[8\]\~18) - (DELAY - (ABSOLUTE - (PORT datab (508:508:508) (604:604:604)) - (PORT datad (1141:1141:1141) (1320:1320:1320)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[9\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (757:757:757) (876:876:876)) - (PORT datab (115:115:115) (142:142:142)) - (PORT datad (284:284:284) (327:327:327)) - (IOPATH dataa combout (172:172:172) (165:165:165)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[9\]) - (DELAY - (ABSOLUTE - (PORT clk (917:917:917) (905:905:905)) - (PORT d (37:37:37) (50:50:50)) - (PORT asdata (314:314:314) (361:361:361)) - (PORT sload (575:575:575) (630:630:630)) - (PORT ena (419:419:419) (435:435:435)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sload (posedge clk) (84:84:84)) - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[9\]\~17) - (DELAY - (ABSOLUTE - (PORT datac (988:988:988) (1162:1162:1162)) - (PORT datad (372:372:372) (453:453:453)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[10\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (115:115:115) (146:146:146)) - (PORT datab (294:294:294) (342:342:342)) - (PORT datad (745:745:745) (852:852:852)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[10\]) (DELAY (ABSOLUTE - (PORT clk (917:917:917) (905:905:905)) + (PORT clk (912:912:912) (899:899:899)) (PORT d (37:37:37) (50:50:50)) - (PORT asdata (307:307:307) (354:354:354)) - (PORT sload (575:575:575) (630:630:630)) - (PORT ena (419:419:419) (435:435:435)) + (PORT asdata (307:307:307) (347:347:347)) + (PORT sload (1093:1093:1093) (1226:1226:1226)) + (PORT ena (1226:1226:1226) (1349:1349:1349)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -30298,5778 +28868,6 @@ (HOLD ena (posedge clk) (84:84:84)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[10\]\~24) - (DELAY - (ABSOLUTE - (PORT datac (495:495:495) (592:592:592)) - (PORT datad (829:829:829) (968:968:968)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[11\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (115:115:115) (145:145:145)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datad (741:741:741) (848:848:848)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[11\]) - (DELAY - (ABSOLUTE - (PORT clk (917:917:917) (905:905:905)) - (PORT d (37:37:37) (50:50:50)) - (PORT asdata (477:477:477) (537:537:537)) - (PORT sload (575:575:575) (630:630:630)) - (PORT ena (419:419:419) (435:435:435)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sload (posedge clk) (84:84:84)) - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[11\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (513:513:513) (606:606:606)) - (PORT datad (831:831:831) (970:970:970)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[12\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (175:175:175) (215:215:215)) - (PORT datab (435:435:435) (497:497:497)) - (PORT datad (841:841:841) (952:952:952)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[12\]) - (DELAY - (ABSOLUTE - (PORT clk (918:918:918) (905:905:905)) - (PORT d (37:37:37) (50:50:50)) - (PORT asdata (307:307:307) (353:353:353)) - (PORT sload (583:583:583) (639:639:639)) - (PORT ena (599:599:599) (635:635:635)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sload (posedge clk) (84:84:84)) - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[12\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1003:1003:1003) (1176:1176:1176)) - (PORT datad (472:472:472) (553:553:553)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (565:565:565) (645:645:645)) - (PORT clk (1094:1094:1094) (1111:1111:1111)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (568:568:568) (645:645:645)) - (PORT d[1] (1218:1218:1218) (1443:1443:1443)) - (PORT d[2] (828:828:828) (946:946:946)) - (PORT d[3] (1657:1657:1657) (1939:1939:1939)) - (PORT d[4] (1525:1525:1525) (1792:1792:1792)) - (PORT d[5] (1840:1840:1840) (2134:2134:2134)) - (PORT d[6] (790:790:790) (920:920:920)) - (PORT d[7] (1703:1703:1703) (1928:1928:1928)) - (PORT d[8] (558:558:558) (640:640:640)) - (PORT d[9] (903:903:903) (1044:1044:1044)) - (PORT d[10] (932:932:932) (1066:1066:1066)) - (PORT d[11] (1275:1275:1275) (1489:1489:1489)) - (PORT d[12] (927:927:927) (1071:1071:1071)) - (PORT clk (1092:1092:1092) (1109:1109:1109)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (528:528:528) (555:555:555)) - (PORT clk (1092:1092:1092) (1109:1109:1109)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1094:1094:1094) (1111:1111:1111)) - (PORT d[0] (804:804:804) (836:836:836)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1095:1095:1095) (1112:1112:1112)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1095:1095:1095) (1112:1112:1112)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1095:1095:1095) (1112:1112:1112)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1095:1095:1095) (1112:1112:1112)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1074:1074:1074) (1090:1090:1090)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (614:614:614) (622:622:622)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (615:615:615) (623:623:623)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (615:615:615) (623:623:623)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (615:615:615) (623:623:623)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1110:1110:1110) (1139:1139:1139)) - (PORT asdata (1127:1127:1127) (1272:1272:1272)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (912:912:912) (917:917:917)) - (PORT asdata (755:755:755) (842:842:842)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode223w\[2\]) - (DELAY - (ABSOLUTE - (PORT dataa (369:369:369) (445:445:445)) - (PORT datab (140:140:140) (179:179:179)) - (PORT datac (192:192:192) (233:233:233)) - (PORT datad (702:702:702) (789:789:789)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode223w\[2\]\~0) - (DELAY - (ABSOLUTE - (PORT datab (1160:1160:1160) (1348:1348:1348)) - (PORT datac (618:618:618) (727:727:727)) - (PORT datad (626:626:626) (733:733:733)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (555:555:555) (632:632:632)) - (PORT clk (1092:1092:1092) (1110:1110:1110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (569:569:569) (646:646:646)) - (PORT d[1] (1219:1219:1219) (1447:1447:1447)) - (PORT d[2] (1946:1946:1946) (2222:2222:2222)) - (PORT d[3] (1649:1649:1649) (1930:1930:1930)) - (PORT d[4] (1489:1489:1489) (1749:1749:1749)) - (PORT d[5] (1847:1847:1847) (2145:2145:2145)) - (PORT d[6] (933:933:933) (1077:1077:1077)) - (PORT d[7] (1691:1691:1691) (1915:1915:1915)) - (PORT d[8] (572:572:572) (660:660:660)) - (PORT d[9] (1843:1843:1843) (2130:2130:2130)) - (PORT d[10] (955:955:955) (1096:1096:1096)) - (PORT d[11] (1109:1109:1109) (1291:1291:1291)) - (PORT d[12] (1075:1075:1075) (1236:1236:1236)) - (PORT clk (1090:1090:1090) (1108:1108:1108)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (523:523:523) (545:545:545)) - (PORT clk (1090:1090:1090) (1108:1108:1108)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1092:1092:1092) (1110:1110:1110)) - (PORT d[0] (928:928:928) (968:968:968)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1093:1093:1093) (1111:1111:1111)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1093:1093:1093) (1111:1111:1111)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1093:1093:1093) (1111:1111:1111)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1093:1093:1093) (1111:1111:1111)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1072:1072:1072) (1089:1089:1089)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (612:612:612) (621:621:621)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (613:613:613) (622:622:622)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (613:613:613) (622:622:622)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (613:613:613) (622:622:622)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (913:913:913) (917:917:917)) - (PORT asdata (801:801:801) (910:910:910)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (913:913:913) (917:917:917)) - (PORT asdata (367:367:367) (416:416:416)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode244w\[2\]) - (DELAY - (ABSOLUTE - (PORT dataa (370:370:370) (447:447:447)) - (PORT datab (144:144:144) (182:182:182)) - (PORT datac (195:195:195) (237:237:237)) - (PORT datad (702:702:702) (789:789:789)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode244w\[2\]\~0) - (DELAY - (ABSOLUTE - (PORT datab (1157:1157:1157) (1345:1345:1345)) - (PORT datac (616:616:616) (725:725:725)) - (PORT datad (625:625:625) (732:732:732)) - (IOPATH datab combout (166:166:166) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (659:659:659) (756:756:756)) - (PORT clk (1087:1087:1087) (1104:1104:1104)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2260:2260:2260) (2618:2618:2618)) - (PORT d[1] (967:967:967) (1145:1145:1145)) - (PORT d[2] (1935:1935:1935) (2216:2216:2216)) - (PORT d[3] (1210:1210:1210) (1410:1410:1410)) - (PORT d[4] (1232:1232:1232) (1428:1428:1428)) - (PORT d[5] (955:955:955) (1125:1125:1125)) - (PORT d[6] (1005:1005:1005) (1163:1163:1163)) - (PORT d[7] (1786:1786:1786) (2020:2020:2020)) - (PORT d[8] (1927:1927:1927) (2239:2239:2239)) - (PORT d[9] (1000:1000:1000) (1155:1155:1155)) - (PORT d[10] (1873:1873:1873) (2157:2157:2157)) - (PORT d[11] (1185:1185:1185) (1369:1369:1369)) - (PORT d[12] (1018:1018:1018) (1175:1175:1175)) - (PORT clk (1085:1085:1085) (1102:1102:1102)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1271:1271:1271) (1396:1396:1396)) - (PORT clk (1085:1085:1085) (1102:1102:1102)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1087:1087:1087) (1104:1104:1104)) - (PORT d[0] (1658:1658:1658) (1820:1820:1820)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1088:1088:1088) (1105:1105:1105)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1088:1088:1088) (1105:1105:1105)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1088:1088:1088) (1105:1105:1105)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1088:1088:1088) (1105:1105:1105)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1067:1067:1067) (1083:1083:1083)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (607:607:607) (615:615:615)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (608:608:608) (616:616:616)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (608:608:608) (616:616:616)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (608:608:608) (616:616:616)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~90) - (DELAY - (ABSOLUTE - (PORT dataa (319:319:319) (368:368:368)) - (PORT datab (518:518:518) (618:618:618)) - (PORT datac (460:460:460) (513:513:513)) - (PORT datad (632:632:632) (741:741:741)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (188:188:188) (177:177:177)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode252w\[2\]) - (DELAY - (ABSOLUTE - (PORT dataa (370:370:370) (447:447:447)) - (PORT datab (143:143:143) (181:181:181)) - (PORT datac (194:194:194) (236:236:236)) - (PORT datad (702:702:702) (789:789:789)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode252w\[2\]\~0) - (DELAY - (ABSOLUTE - (PORT datab (1165:1165:1165) (1354:1354:1354)) - (PORT datac (622:622:622) (731:731:731)) - (PORT datad (628:628:628) (735:735:735)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (679:679:679) (760:760:760)) - (PORT clk (1092:1092:1092) (1110:1110:1110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2377:2377:2377) (2744:2744:2744)) - (PORT d[1] (1350:1350:1350) (1590:1590:1590)) - (PORT d[2] (1850:1850:1850) (2107:2107:2107)) - (PORT d[3] (1476:1476:1476) (1736:1736:1736)) - (PORT d[4] (1493:1493:1493) (1748:1748:1748)) - (PORT d[5] (1642:1642:1642) (1906:1906:1906)) - (PORT d[6] (1107:1107:1107) (1279:1279:1279)) - (PORT d[7] (1510:1510:1510) (1712:1712:1712)) - (PORT d[8] (1945:1945:1945) (2280:2280:2280)) - (PORT d[9] (1660:1660:1660) (1922:1922:1922)) - (PORT d[10] (2963:2963:2963) (3389:3389:3389)) - (PORT d[11] (1075:1075:1075) (1261:1261:1261)) - (PORT d[12] (1256:1256:1256) (1442:1442:1442)) - (PORT clk (1090:1090:1090) (1108:1108:1108)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1116:1116:1116) (1216:1216:1216)) - (PORT clk (1090:1090:1090) (1108:1108:1108)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1092:1092:1092) (1110:1110:1110)) - (PORT d[0] (1226:1226:1226) (1303:1303:1303)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1093:1093:1093) (1111:1111:1111)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1093:1093:1093) (1111:1111:1111)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1093:1093:1093) (1111:1111:1111)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1093:1093:1093) (1111:1111:1111)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1072:1072:1072) (1089:1089:1089)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (612:612:612) (621:621:621)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (613:613:613) (622:622:622)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (613:613:613) (622:622:622)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (613:613:613) (622:622:622)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~91) - (DELAY - (ABSOLUTE - (PORT dataa (456:456:456) (524:524:524)) - (PORT datab (782:782:782) (914:914:914)) - (PORT datac (163:163:163) (191:191:191)) - (PORT datad (617:617:617) (704:704:704)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (190:190:190) (205:205:205)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|decode2\|eq_node\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (368:368:368) (444:444:444)) - (PORT datab (136:136:136) (174:174:174)) - (PORT datac (189:189:189) (231:231:231)) - (PORT datad (702:702:702) (789:789:789)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_clkctrl") - (INSTANCE CLOCK_50\~inputclkctrl) - (DELAY - (ABSOLUTE - (PORT inclk[0] (91:91:91) (78:78:78)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vram_address\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (558:558:558) (639:639:639)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vram_address\~0) - (DELAY - (ABSOLUTE - (PORT dataa (683:683:683) (811:811:811)) - (PORT datab (535:535:535) (640:640:640)) - (PORT datac (530:530:530) (634:634:634)) - (PORT datad (151:151:151) (199:199:199)) - (IOPATH dataa combout (188:188:188) (203:203:203)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (919:919:919) (923:923:923)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (629:629:629) (680:680:680)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (919:919:919) (923:923:923)) - (PORT asdata (643:643:643) (725:725:725)) - (PORT ena (629:629:629) (680:680:680)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vram_address\[2\]\~4) - (DELAY - (ABSOLUTE - (PORT datac (479:479:479) (568:568:568)) - (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (919:919:919) (923:923:923)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (629:629:629) (680:680:680)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add3\~0) - (DELAY - (ABSOLUTE - (PORT datac (475:475:475) (562:562:562)) - (PORT datad (789:789:789) (916:916:916)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (919:919:919) (923:923:923)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (629:629:629) (680:680:680)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add3\~1) - (DELAY - (ABSOLUTE - (PORT dataa (497:497:497) (586:586:586)) - (PORT datac (762:762:762) (879:879:879)) - (PORT datad (789:789:789) (916:916:916)) - (IOPATH dataa combout (166:166:166) (173:173:173)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (919:919:919) (923:923:923)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (629:629:629) (680:680:680)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (384:384:384) (465:465:465)) - (PORT datab (398:398:398) (477:477:477)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH dataa cout (226:226:226) (171:171:171)) - (IOPATH datab combout (190:190:190) (181:181:181)) - (IOPATH datab cout (227:227:227) (175:175:175)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~2) - (DELAY - (ABSOLUTE - (PORT datab (347:347:347) (425:425:425)) - (IOPATH datab combout (167:167:167) (174:174:174)) - (IOPATH datab cout (227:227:227) (175:175:175)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~4) - (DELAY - (ABSOLUTE - (PORT datab (372:372:372) (452:452:452)) - (IOPATH datab combout (188:188:188) (181:181:181)) - (IOPATH datab cout (227:227:227) (175:175:175)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~6) - (DELAY - (ABSOLUTE - (PORT datab (376:376:376) (457:457:457)) - (IOPATH datab combout (166:166:166) (176:176:176)) - (IOPATH datab cout (227:227:227) (175:175:175)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (919:919:919) (923:923:923)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (629:629:629) (680:680:680)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~8) - (DELAY - (ABSOLUTE - (PORT dataa (387:387:387) (470:470:470)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH dataa cout (226:226:226) (171:171:171)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (919:919:919) (923:923:923)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (629:629:629) (680:680:680)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~10) - (DELAY - (ABSOLUTE - (PORT dataa (520:520:520) (618:618:618)) - (IOPATH dataa combout (165:165:165) (173:173:173)) - (IOPATH dataa cout (226:226:226) (171:171:171)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (919:919:919) (923:923:923)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (629:629:629) (680:680:680)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~12) - (DELAY - (ABSOLUTE - (PORT datab (379:379:379) (452:452:452)) - (IOPATH datab combout (188:188:188) (181:181:181)) - (IOPATH datab cout (227:227:227) (175:175:175)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Selector6\~0) - (DELAY - (ABSOLUTE - (PORT datab (331:331:331) (390:390:390)) - (PORT datac (306:306:306) (357:357:357)) - (PORT datad (526:526:526) (625:625:625)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vram_address\[9\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (682:682:682) (811:811:811)) - (PORT datab (533:533:533) (638:638:638)) - (PORT datac (533:533:533) (638:638:638)) - (PORT datad (155:155:155) (204:204:204)) - (IOPATH dataa combout (188:188:188) (203:203:203)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[8\]) - (DELAY - (ABSOLUTE - (PORT clk (918:918:918) (923:923:923)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (421:421:421) (449:449:449)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~14) - (DELAY - (ABSOLUTE - (PORT datad (384:384:384) (462:462:462)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Selector5\~0) - (DELAY - (ABSOLUTE - (PORT dataa (354:354:354) (413:413:413)) - (PORT datac (429:429:429) (491:491:491)) - (PORT datad (526:526:526) (625:625:625)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[9\]) - (DELAY - (ABSOLUTE - (PORT clk (918:918:918) (923:923:923)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (421:421:421) (449:449:449)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vram_address\[10\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (680:680:680) (809:809:809)) - (PORT datab (529:529:529) (634:634:634)) - (PORT datac (538:538:538) (643:643:643)) - (PORT datad (158:158:158) (207:207:207)) - (IOPATH dataa combout (188:188:188) (203:203:203)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vram_address\[10\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (334:334:334) (392:392:392)) - (PORT datab (557:557:557) (667:667:667)) - (PORT datad (89:89:89) (107:107:107)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[10\]) - (DELAY - (ABSOLUTE - (PORT clk (918:918:918) (923:923:923)) - (PORT d (37:37:37) (50:50:50)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Selector3\~0) - (DELAY - (ABSOLUTE - (PORT datab (332:332:332) (391:391:391)) - (PORT datad (526:526:526) (625:625:625)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[11\]) - (DELAY - (ABSOLUTE - (PORT clk (918:918:918) (923:923:923)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (421:421:421) (449:449:449)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Selector2\~0) - (DELAY - (ABSOLUTE - (PORT datac (333:333:333) (392:392:392)) - (PORT datad (525:525:525) (625:625:625)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[12\]) - (DELAY - (ABSOLUTE - (PORT clk (918:918:918) (923:923:923)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (421:421:421) (449:449:449)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (875:875:875) (1007:1007:1007)) - (PORT clk (1099:1099:1099) (1117:1117:1117)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1463:1463:1463) (1667:1667:1667)) - (PORT d[1] (1368:1368:1368) (1613:1613:1613)) - (PORT d[2] (1329:1329:1329) (1557:1557:1557)) - (PORT d[3] (1137:1137:1137) (1317:1317:1317)) - (PORT d[4] (1716:1716:1716) (2014:2014:2014)) - (PORT d[5] (1231:1231:1231) (1458:1458:1458)) - (PORT d[6] (908:908:908) (1038:1038:1038)) - (PORT d[7] (933:933:933) (1073:1073:1073)) - (PORT d[8] (1605:1605:1605) (1884:1884:1884)) - (PORT d[9] (1200:1200:1200) (1368:1368:1368)) - (PORT d[10] (1231:1231:1231) (1400:1400:1400)) - (PORT d[11] (1813:1813:1813) (2074:2074:2074)) - (PORT d[12] (1246:1246:1246) (1439:1439:1439)) - (PORT clk (1097:1097:1097) (1115:1115:1115)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1536:1536:1536) (1684:1684:1684)) - (PORT clk (1097:1097:1097) (1115:1115:1115)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1099:1099:1099) (1117:1117:1117)) - (PORT d[0] (1721:1721:1721) (1605:1605:1605)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1100:1100:1100) (1118:1118:1118)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1100:1100:1100) (1118:1118:1118)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1100:1100:1100) (1118:1118:1118)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1100:1100:1100) (1118:1118:1118)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1054:1054:1054) (1074:1074:1074)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1208:1208:1208) (1358:1358:1358)) - (PORT clk (1059:1059:1059) (1077:1077:1077)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2557:2557:2557) (2902:2902:2902)) - (PORT d[1] (2446:2446:2446) (2755:2755:2755)) - (PORT d[2] (2547:2547:2547) (2893:2893:2893)) - (PORT d[3] (2605:2605:2605) (2960:2960:2960)) - (PORT d[4] (2353:2353:2353) (2651:2651:2651)) - (PORT d[5] (2406:2406:2406) (2710:2710:2710)) - (PORT d[6] (2575:2575:2575) (2938:2938:2938)) - (PORT d[7] (2406:2406:2406) (2709:2709:2709)) - (PORT d[8] (2610:2610:2610) (2940:2940:2940)) - (PORT d[9] (2605:2605:2605) (2984:2984:2984)) - (PORT d[10] (2474:2474:2474) (2781:2781:2781)) - (PORT d[11] (2556:2556:2556) (2881:2881:2881)) - (PORT d[12] (2476:2476:2476) (2788:2788:2788)) - (PORT clk (1056:1056:1056) (1076:1076:1076)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1059:1059:1059) (1077:1077:1077)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1060:1060:1060) (1078:1078:1078)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1060:1060:1060) (1078:1078:1078)) - (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1060:1060:1060) (1078:1078:1078)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1060:1060:1060) (1078:1078:1078)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1055:1055:1055) (1075:1075:1075)) - (IOPATH (posedge clk) q (164:164:164) (166:166:166)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|address_reg_a\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (682:682:682) (804:804:804)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|address_reg_a\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1122:1122:1122) (1154:1154:1154)) - (PORT d (37:37:37) (50:50:50)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (913:913:913) (917:917:917)) - (PORT asdata (927:927:927) (1048:1048:1048)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|decode2\|eq_node\[1\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (369:369:369) (445:445:445)) - (PORT datab (139:139:139) (178:178:178)) - (PORT datac (191:191:191) (233:233:233)) - (PORT datad (702:702:702) (789:789:789)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (857:857:857) (982:982:982)) - (PORT clk (1094:1094:1094) (1111:1111:1111)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1642:1642:1642) (1871:1871:1871)) - (PORT d[1] (1395:1395:1395) (1637:1637:1637)) - (PORT d[2] (688:688:688) (789:789:789)) - (PORT d[3] (1143:1143:1143) (1331:1331:1331)) - (PORT d[4] (1700:1700:1700) (1997:1997:1997)) - (PORT d[5] (1414:1414:1414) (1670:1670:1670)) - (PORT d[6] (879:879:879) (1002:1002:1002)) - (PORT d[7] (737:737:737) (847:847:847)) - (PORT d[8] (979:979:979) (1123:1123:1123)) - (PORT d[9] (882:882:882) (1016:1016:1016)) - (PORT d[10] (1266:1266:1266) (1445:1445:1445)) - (PORT d[11] (1830:1830:1830) (2093:2093:2093)) - (PORT d[12] (1100:1100:1100) (1269:1269:1269)) - (PORT clk (1092:1092:1092) (1109:1109:1109)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1509:1509:1509) (1656:1656:1656)) - (PORT clk (1092:1092:1092) (1109:1109:1109)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1094:1094:1094) (1111:1111:1111)) - (PORT d[0] (1739:1739:1739) (1900:1900:1900)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1095:1095:1095) (1112:1112:1112)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1095:1095:1095) (1112:1112:1112)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1095:1095:1095) (1112:1112:1112)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1095:1095:1095) (1112:1112:1112)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1049:1049:1049) (1068:1068:1068)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1204:1204:1204) (1366:1366:1366)) - (PORT clk (1054:1054:1054) (1071:1071:1071)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2539:2539:2539) (2882:2882:2882)) - (PORT d[1] (2319:2319:2319) (2617:2617:2617)) - (PORT d[2] (2377:2377:2377) (2701:2701:2701)) - (PORT d[3] (2488:2488:2488) (2836:2836:2836)) - (PORT d[4] (2376:2376:2376) (2699:2699:2699)) - (PORT d[5] (2409:2409:2409) (2733:2733:2733)) - (PORT d[6] (2476:2476:2476) (2830:2830:2830)) - (PORT d[7] (2266:2266:2266) (2556:2556:2556)) - (PORT d[8] (2430:2430:2430) (2726:2726:2726)) - (PORT d[9] (2585:2585:2585) (2963:2963:2963)) - (PORT d[10] (2471:2471:2471) (2777:2777:2777)) - (PORT d[11] (2523:2523:2523) (2853:2853:2853)) - (PORT d[12] (2469:2469:2469) (2781:2781:2781)) - (PORT clk (1051:1051:1051) (1070:1070:1070)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1054:1054:1054) (1071:1071:1071)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1055:1055:1055) (1072:1072:1072)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1055:1055:1055) (1072:1072:1072)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1055:1055:1055) (1072:1072:1072)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1055:1055:1055) (1072:1072:1072)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1426:1426:1426) (1615:1615:1615)) - (PORT d[1] (1269:1269:1269) (1482:1482:1482)) - (PORT d[2] (1336:1336:1336) (1564:1564:1564)) - (PORT d[3] (1228:1228:1228) (1448:1448:1448)) - (PORT d[4] (1698:1698:1698) (1990:1990:1990)) - (PORT d[5] (1326:1326:1326) (1565:1565:1565)) - (PORT d[6] (1094:1094:1094) (1247:1247:1247)) - (PORT d[7] (1243:1243:1243) (1418:1418:1418)) - (PORT d[8] (1582:1582:1582) (1856:1856:1856)) - (PORT d[9] (1014:1014:1014) (1157:1157:1157)) - (PORT d[10] (1002:1002:1002) (1126:1126:1126)) - (PORT d[11] (1757:1757:1757) (2009:2009:2009)) - (PORT d[12] (728:728:728) (843:843:843)) - (PORT clk (1106:1106:1106) (1123:1123:1123)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1106:1106:1106) (1123:1123:1123)) - (PORT d[0] (1273:1273:1273) (1427:1427:1427)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1107:1107:1107) (1124:1124:1124)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1088:1088:1088) (1104:1104:1104)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (628:628:628) (636:636:636)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (629:629:629) (637:637:637)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (629:629:629) (637:637:637)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (629:629:629) (637:637:637)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~87) - (DELAY - (ABSOLUTE - (PORT dataa (740:740:740) (855:855:855)) - (PORT datab (148:148:148) (201:201:201)) - (PORT datac (794:794:794) (897:897:897)) - (PORT datad (908:908:908) (1038:1038:1038)) - (IOPATH dataa combout (186:186:186) (175:175:175)) - (IOPATH datab combout (167:167:167) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2075:2075:2075) (2400:2400:2400)) - (PORT d[1] (1515:1515:1515) (1769:1769:1769)) - (PORT d[2] (1420:1420:1420) (1623:1623:1623)) - (PORT d[3] (1217:1217:1217) (1428:1428:1428)) - (PORT d[4] (1287:1287:1287) (1509:1509:1509)) - (PORT d[5] (1213:1213:1213) (1425:1425:1425)) - (PORT d[6] (1122:1122:1122) (1294:1294:1294)) - (PORT d[7] (1157:1157:1157) (1309:1309:1309)) - (PORT d[8] (1735:1735:1735) (2028:2028:2028)) - (PORT d[9] (1494:1494:1494) (1731:1731:1731)) - (PORT d[10] (2747:2747:2747) (3134:3134:3134)) - (PORT d[11] (1194:1194:1194) (1379:1379:1379)) - (PORT d[12] (1423:1423:1423) (1629:1629:1629)) - (PORT clk (1096:1096:1096) (1113:1113:1113)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1096:1096:1096) (1113:1113:1113)) - (PORT d[0] (1992:1992:1992) (1801:1801:1801)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1114:1114:1114)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1078:1078:1078) (1094:1094:1094)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (618:618:618) (626:626:626)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (619:619:619) (627:627:627)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (619:619:619) (627:627:627)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (619:619:619) (627:627:627)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~88) - (DELAY - (ABSOLUTE - (PORT dataa (698:698:698) (786:786:786)) - (PORT datab (637:637:637) (730:730:730)) - (PORT datac (884:884:884) (1011:1011:1011)) - (PORT datad (93:93:93) (113:113:113)) - (IOPATH dataa combout (188:188:188) (184:184:184)) - (IOPATH datab combout (190:190:190) (181:181:181)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~89) - (DELAY - (ABSOLUTE - (PORT dataa (790:790:790) (926:926:926)) - (PORT datab (108:108:108) (139:139:139)) - (PORT datac (326:326:326) (394:394:394)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (190:190:190) (177:177:177)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~111) - (DELAY - (ABSOLUTE - (PORT dataa (349:349:349) (409:409:409)) - (PORT datab (1129:1129:1129) (1312:1312:1312)) - (PORT datac (494:494:494) (589:589:589)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_io_ibuf") - (INSTANCE raw_loader_in\~input) - (DELAY - (ABSOLUTE - (IOPATH i o (153:153:153) (704:704:704)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~86) - (DELAY - (ABSOLUTE - (PORT dataa (496:496:496) (588:588:588)) - (PORT datac (913:913:913) (1067:1067:1067)) - (PORT datad (1114:1114:1114) (1287:1287:1287)) - (IOPATH dataa combout (165:165:165) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~100) - (DELAY - (ABSOLUTE - (PORT dataa (509:509:509) (602:602:602)) - (PORT datab (728:728:728) (836:836:836)) - (PORT datac (95:95:95) (119:119:119)) - (PORT datad (95:95:95) (114:114:114)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (176:176:176)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~101) - (DELAY - (ABSOLUTE - (PORT dataa (504:504:504) (596:596:596)) - (PORT datab (479:479:479) (578:578:578)) - (PORT datac (902:902:902) (1028:1028:1028)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[6\]) - (DELAY - (ABSOLUTE - (PORT dataa (149:149:149) (194:194:194)) - (PORT datab (772:772:772) (880:880:880)) - (PORT datac (525:525:525) (620:620:620)) - (PORT datad (443:443:443) (498:498:498)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_re\~2) - (DELAY - (ABSOLUTE - (PORT dataa (940:940:940) (1115:1115:1115)) - (PORT datab (426:426:426) (518:518:518)) - (PORT datac (519:519:519) (605:605:605)) - (PORT datad (686:686:686) (789:789:789)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_2) - (DELAY - (ABSOLUTE - (PORT dataa (541:541:541) (643:643:643)) - (PORT datab (549:549:549) (639:639:639)) - (PORT datac (520:520:520) (608:608:608)) - (PORT datad (94:94:94) (114:114:114)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (916:916:916) (903:903:903)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (432:432:432) (460:460:460)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[6\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (135:135:135)) - (PORT datab (635:635:635) (752:752:752)) - (PORT datac (121:121:121) (151:151:151)) - (PORT datad (112:112:112) (133:133:133)) - (IOPATH dataa combout (165:165:165) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|ir_\|opcode\[6\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (102:102:102) (119:119:119)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~13) - (DELAY - (ABSOLUTE - (PORT dataa (639:639:639) (754:754:754)) - (PORT datab (501:501:501) (593:593:593)) - (PORT datac (369:369:369) (435:435:435)) - (PORT datad (198:198:198) (225:225:225)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (911:911:911)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (917:917:917) (902:902:902)) - (PORT ena (645:645:645) (697:697:697)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal41\~0) - (DELAY - (ABSOLUTE - (PORT datac (941:941:941) (1085:1085:1085)) - (PORT datad (683:683:683) (800:800:800)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal41\~1) - (DELAY - (ABSOLUTE - (PORT dataa (835:835:835) (970:970:970)) - (PORT datab (1296:1296:1296) (1497:1497:1497)) - (PORT datac (1238:1238:1238) (1445:1445:1445)) - (PORT datad (817:817:817) (953:953:953)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal41\~2) - (DELAY - (ABSOLUTE - (PORT dataa (247:247:247) (297:297:297)) - (PORT datab (895:895:895) (1020:1020:1020)) - (PORT datac (88:88:88) (109:109:109)) - (PORT datad (609:609:609) (701:701:701)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe) - (DELAY - (ABSOLUTE - (PORT dataa (1100:1100:1100) (1268:1268:1268)) - (PORT datab (611:611:611) (701:701:701)) - (PORT datac (1150:1150:1150) (1342:1342:1342)) - (PORT datad (93:93:93) (112:112:112)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (651:651:651) (757:757:757)) - (PORT datab (159:159:159) (204:204:204)) - (PORT datac (143:143:143) (184:184:184)) - (PORT datad (130:130:130) (160:160:160)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (611:611:611) (714:714:714)) - (PORT datab (655:655:655) (757:757:757)) - (PORT datac (221:221:221) (280:280:280)) - (PORT datad (369:369:369) (437:437:437)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (522:522:522) (599:599:599)) - (PORT datac (916:916:916) (1066:1066:1066)) - (PORT datad (490:490:490) (565:565:565)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~18) - (DELAY - (ABSOLUTE - (PORT datab (104:104:104) (132:132:132)) - (PORT datac (489:489:489) (561:561:561)) - (PORT datad (132:132:132) (161:161:161)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (186:186:186) (222:222:222)) - (PORT datab (336:336:336) (392:392:392)) - (PORT datac (630:630:630) (736:736:736)) - (PORT datad (322:322:322) (376:376:376)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (135:135:135)) - (PORT datab (547:547:547) (647:647:647)) - (PORT datac (309:309:309) (360:360:360)) - (PORT datad (120:120:120) (150:150:150)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[5\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (711:711:711) (839:839:839)) - (PORT datab (504:504:504) (587:587:587)) - (PORT datac (1033:1033:1033) (1182:1182:1182)) - (PORT datad (520:520:520) (607:607:607)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[5\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (346:346:346) (406:406:406)) - (PORT datab (139:139:139) (179:179:179)) - (PORT datac (91:91:91) (113:113:113)) - (PORT datad (520:520:520) (605:605:605)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sw1_\|db_down\[5\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (204:204:204) (283:283:283)) - (PORT datab (747:747:747) (871:871:871)) - (PORT datac (632:632:632) (721:721:721)) - (PORT datad (674:674:674) (776:776:776)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_36) - (DELAY - (ABSOLUTE - (PORT dataa (290:290:290) (338:338:338)) - (PORT datab (337:337:337) (396:396:396)) - (PORT datac (353:353:353) (422:422:422)) - (PORT datad (366:366:366) (429:429:429)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|flags_yf) - (DELAY - (ABSOLUTE - (PORT clk (900:900:900) (905:905:905)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (421:421:421) (448:448:448)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[5\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (338:338:338) (409:409:409)) - (PORT datab (502:502:502) (579:579:579)) - (PORT datac (352:352:352) (420:420:420)) - (PORT datad (473:473:473) (542:542:542)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[5\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (533:533:533) (611:611:611)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datac (522:522:522) (600:600:600)) - (PORT datad (482:482:482) (540:540:540)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[5\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (367:367:367) (429:429:429)) - (PORT datab (658:658:658) (756:756:756)) - (PORT datac (594:594:594) (684:684:684)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~107) - (DELAY - (ABSOLUTE - (PORT dataa (980:980:980) (1140:1140:1140)) - (PORT datab (673:673:673) (794:794:794)) - (PORT datac (879:879:879) (1043:1043:1043)) - (PORT datad (607:607:607) (694:694:694)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (659:659:659) (755:755:755)) - (PORT clk (1087:1087:1087) (1104:1104:1104)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2092:2092:2092) (2427:2427:2427)) - (PORT d[1] (1003:1003:1003) (1187:1187:1187)) - (PORT d[2] (1762:1762:1762) (2022:2022:2022)) - (PORT d[3] (1066:1066:1066) (1248:1248:1248)) - (PORT d[4] (1270:1270:1270) (1482:1482:1482)) - (PORT d[5] (1549:1549:1549) (1816:1816:1816)) - (PORT d[6] (1190:1190:1190) (1376:1376:1376)) - (PORT d[7] (1606:1606:1606) (1818:1818:1818)) - (PORT d[8] (1757:1757:1757) (2045:2045:2045)) - (PORT d[9] (1602:1602:1602) (1842:1842:1842)) - (PORT d[10] (2054:2054:2054) (2366:2366:2366)) - (PORT d[11] (1012:1012:1012) (1176:1176:1176)) - (PORT d[12] (1207:1207:1207) (1391:1391:1391)) - (PORT clk (1085:1085:1085) (1102:1102:1102)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1093:1093:1093) (1194:1194:1194)) - (PORT clk (1085:1085:1085) (1102:1102:1102)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1087:1087:1087) (1104:1104:1104)) - (PORT d[0] (1481:1481:1481) (1623:1623:1623)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1088:1088:1088) (1105:1105:1105)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1088:1088:1088) (1105:1105:1105)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1088:1088:1088) (1105:1105:1105)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1088:1088:1088) (1105:1105:1105)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1067:1067:1067) (1083:1083:1083)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (607:607:607) (615:615:615)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (608:608:608) (616:616:616)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (608:608:608) (616:616:616)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (608:608:608) (616:616:616)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (643:643:643) (736:736:736)) - (PORT clk (1084:1084:1084) (1102:1102:1102)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2264:2264:2264) (2626:2626:2626)) - (PORT d[1] (976:976:976) (1155:1155:1155)) - (PORT d[2] (1924:1924:1924) (2200:2200:2200)) - (PORT d[3] (1054:1054:1054) (1231:1231:1231)) - (PORT d[4] (1073:1073:1073) (1242:1242:1242)) - (PORT d[5] (954:954:954) (1119:1119:1119)) - (PORT d[6] (1009:1009:1009) (1167:1167:1167)) - (PORT d[7] (1774:1774:1774) (2007:2007:2007)) - (PORT d[8] (1932:1932:1932) (2243:2243:2243)) - (PORT d[9] (1635:1635:1635) (1882:1882:1882)) - (PORT d[10] (2007:2007:2007) (2303:2303:2303)) - (PORT d[11] (861:861:861) (1003:1003:1003)) - (PORT d[12] (1003:1003:1003) (1150:1150:1150)) - (PORT clk (1082:1082:1082) (1100:1100:1100)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1068:1068:1068) (1159:1159:1159)) - (PORT clk (1082:1082:1082) (1100:1100:1100)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1084:1084:1084) (1102:1102:1102)) - (PORT d[0] (1327:1327:1327) (1422:1422:1422)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1085:1085:1085) (1103:1103:1103)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1085:1085:1085) (1103:1103:1103)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1085:1085:1085) (1103:1103:1103)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1085:1085:1085) (1103:1103:1103)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1064:1064:1064) (1081:1081:1081)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (604:604:604) (613:613:613)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (605:605:605) (614:614:614)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (605:605:605) (614:614:614)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (605:605:605) (614:614:614)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (673:673:673) (772:772:772)) - (PORT clk (1084:1084:1084) (1102:1102:1102)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2093:2093:2093) (2428:2428:2428)) - (PORT d[1] (983:983:983) (1158:1158:1158)) - (PORT d[2] (1742:1742:1742) (1993:1993:1993)) - (PORT d[3] (1189:1189:1189) (1381:1381:1381)) - (PORT d[4] (1286:1286:1286) (1504:1504:1504)) - (PORT d[5] (1557:1557:1557) (1827:1827:1827)) - (PORT d[6] (1042:1042:1042) (1211:1211:1211)) - (PORT d[7] (1613:1613:1613) (1825:1825:1825)) - (PORT d[8] (1938:1938:1938) (2254:2254:2254)) - (PORT d[9] (1639:1639:1639) (1892:1892:1892)) - (PORT d[10] (2034:2034:2034) (2338:2338:2338)) - (PORT d[11] (1022:1022:1022) (1190:1190:1190)) - (PORT d[12] (1170:1170:1170) (1342:1342:1342)) - (PORT clk (1082:1082:1082) (1100:1100:1100)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1059:1059:1059) (1151:1151:1151)) - (PORT clk (1082:1082:1082) (1100:1100:1100)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1084:1084:1084) (1102:1102:1102)) - (PORT d[0] (1375:1375:1375) (1493:1493:1493)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1085:1085:1085) (1103:1103:1103)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1085:1085:1085) (1103:1103:1103)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1085:1085:1085) (1103:1103:1103)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1085:1085:1085) (1103:1103:1103)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1064:1064:1064) (1081:1081:1081)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (604:604:604) (613:613:613)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (605:605:605) (614:614:614)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (605:605:605) (614:614:614)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (605:605:605) (614:614:614)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (782:782:782) (913:913:913)) - (PORT datab (781:781:781) (913:913:913)) - (PORT datac (638:638:638) (717:717:717)) - (PORT datad (631:631:631) (709:709:709)) - (IOPATH dataa combout (188:188:188) (184:184:184)) - (IOPATH datab combout (190:190:190) (188:188:188)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (707:707:707) (817:817:817)) - (PORT clk (1091:1091:1091) (1109:1109:1109)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1636:1636:1636) (1864:1864:1864)) - (PORT d[1] (1552:1552:1552) (1823:1823:1823)) - (PORT d[2] (682:682:682) (782:782:782)) - (PORT d[3] (962:962:962) (1117:1117:1117)) - (PORT d[4] (1687:1687:1687) (1968:1968:1968)) - (PORT d[5] (1407:1407:1407) (1658:1658:1658)) - (PORT d[6] (722:722:722) (827:827:827)) - (PORT d[7] (750:750:750) (869:869:869)) - (PORT d[8] (995:995:995) (1153:1153:1153)) - (PORT d[9] (708:708:708) (820:820:820)) - (PORT d[10] (1411:1411:1411) (1604:1604:1604)) - (PORT d[11] (1846:1846:1846) (2146:2146:2146)) - (PORT d[12] (1264:1264:1264) (1454:1454:1454)) - (PORT clk (1089:1089:1089) (1107:1107:1107)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (854:854:854) (919:919:919)) - (PORT clk (1089:1089:1089) (1107:1107:1107)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1091:1091:1091) (1109:1109:1109)) - (PORT d[0] (1185:1185:1185) (1273:1273:1273)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1092:1092:1092) (1110:1110:1110)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1092:1092:1092) (1110:1110:1110)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1092:1092:1092) (1110:1110:1110)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1092:1092:1092) (1110:1110:1110)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1071:1071:1071) (1088:1088:1088)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (611:611:611) (620:620:620)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (612:612:612) (621:621:621)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (612:612:612) (621:621:621)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (612:612:612) (621:621:621)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (640:640:640) (729:729:729)) - (PORT datab (935:935:935) (1086:1086:1086)) - (PORT datac (89:89:89) (110:110:110)) - (PORT datad (785:785:785) (911:911:911)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (190:190:190) (205:205:205)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (898:898:898) (1053:1053:1053)) - (PORT clk (1091:1091:1091) (1108:1108:1108)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1785:1785:1785) (2045:2045:2045)) - (PORT d[1] (1164:1164:1164) (1373:1373:1373)) - (PORT d[2] (1221:1221:1221) (1417:1417:1417)) - (PORT d[3] (1049:1049:1049) (1230:1230:1230)) - (PORT d[4] (1442:1442:1442) (1668:1668:1668)) - (PORT d[5] (1305:1305:1305) (1532:1532:1532)) - (PORT d[6] (976:976:976) (1119:1119:1119)) - (PORT d[7] (940:940:940) (1092:1092:1092)) - (PORT d[8] (1488:1488:1488) (1732:1732:1732)) - (PORT d[9] (1134:1134:1134) (1301:1301:1301)) - (PORT d[10] (1133:1133:1133) (1307:1307:1307)) - (PORT d[11] (1381:1381:1381) (1598:1598:1598)) - (PORT d[12] (1446:1446:1446) (1655:1655:1655)) - (PORT clk (1089:1089:1089) (1106:1106:1106)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1438:1438:1438) (1584:1584:1584)) - (PORT clk (1089:1089:1089) (1106:1106:1106)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1091:1091:1091) (1108:1108:1108)) - (PORT d[0] (2262:2262:2262) (2502:2502:2502)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1092:1092:1092) (1109:1109:1109)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1092:1092:1092) (1109:1109:1109)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1092:1092:1092) (1109:1109:1109)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1092:1092:1092) (1109:1109:1109)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1046:1046:1046) (1065:1065:1065)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (946:946:946) (1050:1050:1050)) - (PORT clk (1051:1051:1051) (1068:1068:1068)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2446:2446:2446) (2778:2778:2778)) - (PORT d[1] (2362:2362:2362) (2678:2678:2678)) - (PORT d[2] (2423:2423:2423) (2755:2755:2755)) - (PORT d[3] (2615:2615:2615) (2968:2968:2968)) - (PORT d[4] (2392:2392:2392) (2714:2714:2714)) - (PORT d[5] (2550:2550:2550) (2906:2906:2906)) - (PORT d[6] (2637:2637:2637) (3014:3014:3014)) - (PORT d[7] (2422:2422:2422) (2758:2758:2758)) - (PORT d[8] (2414:2414:2414) (2749:2749:2749)) - (PORT d[9] (2559:2559:2559) (2937:2937:2937)) - (PORT d[10] (2575:2575:2575) (2895:2895:2895)) - (PORT d[11] (2424:2424:2424) (2742:2742:2742)) - (PORT d[12] (2554:2554:2554) (2908:2908:2908)) - (PORT clk (1048:1048:1048) (1067:1067:1067)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1051:1051:1051) (1068:1068:1068)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1052:1052:1052) (1069:1069:1069)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1052:1052:1052) (1069:1069:1069)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1052:1052:1052) (1069:1069:1069)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1052:1052:1052) (1069:1069:1069)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1599:1599:1599) (1833:1833:1833)) - (PORT d[1] (989:989:989) (1178:1178:1178)) - (PORT d[2] (1107:1107:1107) (1292:1292:1292)) - (PORT d[3] (1072:1072:1072) (1258:1258:1258)) - (PORT d[4] (1602:1602:1602) (1841:1841:1841)) - (PORT d[5] (1316:1316:1316) (1540:1540:1540)) - (PORT d[6] (1129:1129:1129) (1293:1293:1293)) - (PORT d[7] (1227:1227:1227) (1432:1432:1432)) - (PORT d[8] (1367:1367:1367) (1595:1595:1595)) - (PORT d[9] (1129:1129:1129) (1298:1298:1298)) - (PORT d[10] (959:959:959) (1096:1096:1096)) - (PORT d[11] (1135:1135:1135) (1299:1299:1299)) - (PORT d[12] (1423:1423:1423) (1625:1625:1625)) - (PORT clk (1096:1096:1096) (1113:1113:1113)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1096:1096:1096) (1113:1113:1113)) - (PORT d[0] (1578:1578:1578) (1775:1775:1775)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1114:1114:1114)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1078:1078:1078) (1094:1094:1094)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (618:618:618) (626:626:626)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (619:619:619) (627:627:627)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (619:619:619) (627:627:627)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (619:619:619) (627:627:627)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2216:2216:2216) (2563:2563:2563)) - (PORT d[1] (1659:1659:1659) (1935:1935:1935)) - (PORT d[2] (1569:1569:1569) (1794:1794:1794)) - (PORT d[3] (1294:1294:1294) (1526:1526:1526)) - (PORT d[4] (1452:1452:1452) (1691:1691:1691)) - (PORT d[5] (1461:1461:1461) (1699:1699:1699)) - (PORT d[6] (1104:1104:1104) (1269:1269:1269)) - (PORT d[7] (1321:1321:1321) (1494:1494:1494)) - (PORT d[8] (1792:1792:1792) (2113:2113:2113)) - (PORT d[9] (1529:1529:1529) (1780:1780:1780)) - (PORT d[10] (2637:2637:2637) (3017:3017:3017)) - (PORT d[11] (1109:1109:1109) (1296:1296:1296)) - (PORT d[12] (1409:1409:1409) (1611:1611:1611)) - (PORT clk (1095:1095:1095) (1112:1112:1112)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1095:1095:1095) (1112:1112:1112)) - (PORT d[0] (2281:2281:2281) (2058:2058:2058)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1096:1096:1096) (1113:1113:1113)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1077:1077:1077) (1093:1093:1093)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (617:617:617) (625:625:625)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (618:618:618) (626:626:626)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (618:618:618) (626:626:626)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (618:618:618) (626:626:626)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (839:839:839) (963:963:963)) - (PORT clk (1104:1104:1104) (1120:1120:1120)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1582:1582:1582) (1791:1791:1791)) - (PORT d[1] (1211:1211:1211) (1427:1427:1427)) - (PORT d[2] (1254:1254:1254) (1474:1474:1474)) - (PORT d[3] (1306:1306:1306) (1512:1512:1512)) - (PORT d[4] (1722:1722:1722) (2020:2020:2020)) - (PORT d[5] (1375:1375:1375) (1614:1614:1614)) - (PORT d[6] (917:917:917) (1047:1047:1047)) - (PORT d[7] (907:907:907) (1040:1040:1040)) - (PORT d[8] (1585:1585:1585) (1863:1863:1863)) - (PORT d[9] (1205:1205:1205) (1379:1379:1379)) - (PORT d[10] (1085:1085:1085) (1238:1238:1238)) - (PORT d[11] (1643:1643:1643) (1882:1882:1882)) - (PORT d[12] (905:905:905) (1047:1047:1047)) - (PORT clk (1102:1102:1102) (1118:1118:1118)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1389:1389:1389) (1525:1525:1525)) - (PORT clk (1102:1102:1102) (1118:1118:1118)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1104:1104:1104) (1120:1120:1120)) - (PORT d[0] (1751:1751:1751) (1627:1627:1627)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1105:1105:1105) (1121:1121:1121)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1105:1105:1105) (1121:1121:1121)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1105:1105:1105) (1121:1121:1121)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1105:1105:1105) (1121:1121:1121)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1059:1059:1059) (1077:1077:1077)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1400:1400:1400) (1590:1590:1590)) - (PORT clk (1064:1064:1064) (1080:1080:1080)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2480:2480:2480) (2801:2801:2801)) - (PORT d[1] (2279:2279:2279) (2566:2566:2566)) - (PORT d[2] (2448:2448:2448) (2750:2750:2750)) - (PORT d[3] (2483:2483:2483) (2821:2821:2821)) - (PORT d[4] (2520:2520:2520) (2837:2837:2837)) - (PORT d[5] (2430:2430:2430) (2762:2762:2762)) - (PORT d[6] (2545:2545:2545) (2901:2901:2901)) - (PORT d[7] (2265:2265:2265) (2556:2556:2556)) - (PORT d[8] (2566:2566:2566) (2898:2898:2898)) - (PORT d[9] (2550:2550:2550) (2915:2915:2915)) - (PORT d[10] (2580:2580:2580) (2904:2904:2904)) - (PORT d[11] (2430:2430:2430) (2736:2736:2736)) - (PORT d[12] (2483:2483:2483) (2802:2802:2802)) - (PORT clk (1061:1061:1061) (1079:1079:1079)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1064:1064:1064) (1080:1080:1080)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1065:1065:1065) (1081:1081:1081)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1065:1065:1065) (1081:1081:1081)) - (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1065:1065:1065) (1081:1081:1081)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1065:1065:1065) (1081:1081:1081)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1060:1060:1060) (1078:1078:1078)) - (IOPATH (posedge clk) q (164:164:164) (166:166:166)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Mux2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (802:802:802) (931:931:931)) - (PORT datab (528:528:528) (629:629:629)) - (PORT datac (650:650:650) (748:748:748)) - (PORT datad (918:918:918) (1051:1051:1051)) - (IOPATH dataa combout (188:188:188) (184:184:184)) - (IOPATH datab combout (190:190:190) (188:188:188)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Mux2\~1) - (DELAY - (ABSOLUTE - (PORT dataa (865:865:865) (1000:1000:1000)) - (PORT datab (528:528:528) (629:629:629)) - (PORT datac (963:963:963) (1090:1090:1090)) - (PORT datad (89:89:89) (106:106:106)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (169:169:169) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[5\]\~110) - (DELAY - (ABSOLUTE - (PORT dataa (105:105:105) (136:136:136)) - (PORT datab (666:666:666) (787:787:787)) - (PORT datac (899:899:899) (1036:1036:1036)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[5\]\~85) - (DELAY - (ABSOLUTE - (PORT dataa (745:745:745) (854:854:854)) - (PORT datab (747:747:747) (855:855:855)) - (PORT datac (467:467:467) (550:550:550)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[5\]\~99) - (DELAY - (ABSOLUTE - (PORT dataa (442:442:442) (512:512:512)) - (PORT datad (102:102:102) (119:119:119)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[5\]) - (DELAY - (ABSOLUTE - (PORT dataa (542:542:542) (645:645:645)) - (PORT datab (566:566:566) (642:642:642)) - (PORT datac (132:132:132) (169:169:169)) - (PORT datad (527:527:527) (607:607:607)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (916:916:916) (903:903:903)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (432:432:432) (460:460:460)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[5\]\~14) - (DELAY - (ABSOLUTE - (PORT datab (374:374:374) (442:442:442)) - (PORT datac (127:127:127) (168:168:168)) - (PORT datad (186:186:186) (216:216:216)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[5\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (539:539:539) (623:623:623)) - (PORT datab (519:519:519) (599:599:599)) - (PORT datac (435:435:435) (493:493:493)) - (PORT datad (491:491:491) (558:558:558)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (914:914:914)) - (PORT asdata (317:317:317) (356:356:356)) - (PORT clrn (911:911:911) (895:895:895)) - (PORT ena (780:780:780) (849:849:849)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|SYNTHESIZED_WIRE_0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (681:681:681) (814:814:814)) - (PORT datab (474:474:474) (551:551:551)) - (PORT datac (470:470:470) (534:534:534)) - (PORT datad (1077:1077:1077) (1218:1218:1218)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|DFFE_inst4) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (916:916:916)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (922:922:922) (904:904:904)) - (PORT ena (422:422:422) (450:450:450)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|use_ixiy) - (DELAY - (ABSOLUTE - (PORT dataa (555:555:555) (659:659:659)) - (PORT datac (528:528:528) (621:621:621)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~23) - (DELAY - (ABSOLUTE - (PORT dataa (648:648:648) (752:752:752)) - (PORT datab (554:554:554) (663:663:663)) - (PORT datac (372:372:372) (440:440:440)) - (PORT datad (715:715:715) (832:832:832)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~34) - (DELAY - (ABSOLUTE - (PORT dataa (479:479:479) (563:563:563)) - (PORT datab (353:353:353) (408:408:408)) - (PORT datac (506:506:506) (589:589:589)) - (PORT datad (187:187:187) (217:217:217)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~31) - (DELAY - (ABSOLUTE - (PORT dataa (637:637:637) (745:745:745)) - (PORT datab (877:877:877) (1003:1003:1003)) - (PORT datac (330:330:330) (389:389:389)) - (PORT datad (608:608:608) (690:690:690)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~29) - (DELAY - (ABSOLUTE - (PORT dataa (697:697:697) (828:828:828)) - (PORT datab (254:254:254) (310:310:310)) - (PORT datac (945:945:945) (1090:1090:1090)) - (PORT datad (144:144:144) (179:179:179)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~30) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (258:258:258)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datac (602:602:602) (684:684:684)) - (PORT datad (107:107:107) (126:126:126)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~28) - (DELAY - (ABSOLUTE - (PORT dataa (639:639:639) (747:747:747)) - (PORT datab (301:301:301) (357:357:357)) - (PORT datac (600:600:600) (688:688:688)) - (PORT datad (164:164:164) (193:193:193)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~32) - (DELAY - (ABSOLUTE - (PORT dataa (466:466:466) (542:542:542)) - (PORT datab (103:103:103) (131:131:131)) - (PORT datac (311:311:311) (362:362:362)) - (PORT datad (92:92:92) (111:111:111)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~42) - (DELAY - (ABSOLUTE - (PORT dataa (121:121:121) (153:153:153)) - (PORT datab (342:342:342) (402:402:402)) - (PORT datac (101:101:101) (130:130:130)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~14) - (DELAY - (ABSOLUTE - (PORT dataa (479:479:479) (563:563:563)) - (PORT datab (611:611:611) (699:699:699)) - (PORT datac (785:785:785) (905:905:905)) - (PORT datad (506:506:506) (590:590:590)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~10) - (DELAY - (ABSOLUTE - (PORT dataa (473:473:473) (549:549:549)) - (PORT datab (512:512:512) (603:603:603)) - (PORT datac (547:547:547) (631:631:631)) - (PORT datad (615:615:615) (700:700:700)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~9) - (DELAY - (ABSOLUTE - (PORT dataa (480:480:480) (564:564:564)) - (PORT datab (472:472:472) (554:554:554)) - (PORT datac (616:616:616) (700:700:700)) - (PORT datad (169:169:169) (200:200:200)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~11) - (DELAY - (ABSOLUTE - (PORT dataa (882:882:882) (1032:1032:1032)) - (PORT datab (107:107:107) (136:136:136)) - (PORT datac (1068:1068:1068) (1218:1218:1218)) - (PORT datad (89:89:89) (107:107:107)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~12) - (DELAY - (ABSOLUTE - (PORT dataa (657:657:657) (793:793:793)) - (PORT datab (553:553:553) (655:655:655)) - (PORT datac (934:934:934) (1076:1076:1076)) - (PORT datad (653:653:653) (755:755:755)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~13) - (DELAY - (ABSOLUTE - (PORT dataa (780:780:780) (888:888:888)) - (PORT datab (611:611:611) (699:699:699)) - (PORT datac (570:570:570) (646:646:646)) - (PORT datad (171:171:171) (202:202:202)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~15) - (DELAY - (ABSOLUTE - (PORT dataa (105:105:105) (136:136:136)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (90:90:90) (112:112:112)) - (PORT datad (322:322:322) (366:366:366)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~20) - (DELAY - (ABSOLUTE - (PORT dataa (325:325:325) (374:374:374)) - (PORT datab (578:578:578) (680:680:680)) - (PORT datac (294:294:294) (344:344:344)) - (PORT datad (337:337:337) (390:390:390)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~48) - (DELAY - (ABSOLUTE - (PORT dataa (489:489:489) (583:583:583)) - (PORT datab (644:644:644) (749:749:749)) - (PORT datac (834:834:834) (982:982:982)) - (PORT datad (370:370:370) (429:429:429)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~22) - (DELAY - (ABSOLUTE - (PORT dataa (743:743:743) (842:842:842)) - (PORT datab (463:463:463) (538:538:538)) - (PORT datac (592:592:592) (674:674:674)) - (PORT datad (103:103:103) (119:119:119)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~21) - (DELAY - (ABSOLUTE - (PORT dataa (507:507:507) (600:600:600)) - (PORT datab (525:525:525) (628:628:628)) - (PORT datac (856:856:856) (976:976:976)) - (PORT datad (675:675:675) (763:763:763)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~23) - (DELAY - (ABSOLUTE - (PORT dataa (469:469:469) (543:543:543)) - (PORT datab (102:102:102) (131:131:131)) - (PORT datac (427:427:427) (493:493:493)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~26) - (DELAY - (ABSOLUTE - (PORT dataa (1167:1167:1167) (1359:1359:1359)) - (PORT datab (657:657:657) (756:756:756)) - (PORT datac (636:636:636) (734:734:734)) - (PORT datad (649:649:649) (747:747:747)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~25) - (DELAY - (ABSOLUTE - (PORT dataa (1406:1406:1406) (1620:1620:1620)) - (PORT datab (297:297:297) (343:343:343)) - (PORT datac (101:101:101) (121:121:121)) - (PORT datad (557:557:557) (639:639:639)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~27) - (DELAY - (ABSOLUTE - (PORT dataa (899:899:899) (1026:1026:1026)) - (PORT datab (477:477:477) (571:571:571)) - (PORT datac (582:582:582) (688:688:688)) - (PORT datad (438:438:438) (519:519:519)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~33) - (DELAY - (ABSOLUTE - (PORT dataa (555:555:555) (640:640:640)) - (PORT datab (104:104:104) (133:133:133)) - (PORT datac (470:470:470) (561:561:561)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~35) - (DELAY - (ABSOLUTE - (PORT dataa (463:463:463) (536:536:536)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datac (463:463:463) (549:549:549)) - (PORT datad (102:102:102) (119:119:119)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_re) - (DELAY - (ABSOLUTE - (PORT datab (553:553:553) (643:643:643)) - (PORT datac (523:523:523) (610:610:610)) - (PORT datad (96:96:96) (116:116:116)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (581:581:581) (665:665:665)) - (PORT clk (1098:1098:1098) (1115:1115:1115)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (648:648:648) (731:731:731)) - (PORT d[1] (1411:1411:1411) (1666:1666:1666)) - (PORT d[2] (993:993:993) (1127:1127:1127)) - (PORT d[3] (570:570:570) (662:662:662)) - (PORT d[4] (1533:1533:1533) (1796:1796:1796)) - (PORT d[5] (2036:2036:2036) (2359:2359:2359)) - (PORT d[6] (588:588:588) (683:683:683)) - (PORT d[7] (1881:1881:1881) (2126:2126:2126)) - (PORT d[8] (688:688:688) (792:792:792)) - (PORT d[9] (574:574:574) (672:672:672)) - (PORT d[10] (753:753:753) (864:864:864)) - (PORT d[11] (1435:1435:1435) (1666:1666:1666)) - (PORT d[12] (744:744:744) (861:861:861)) - (PORT clk (1096:1096:1096) (1113:1113:1113)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (508:508:508) (530:530:530)) - (PORT clk (1096:1096:1096) (1113:1113:1113)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1098:1098:1098) (1115:1115:1115)) - (PORT d[0] (920:920:920) (961:961:961)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1099:1099:1099) (1116:1116:1116)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1099:1099:1099) (1116:1116:1116)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1099:1099:1099) (1116:1116:1116)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1099:1099:1099) (1116:1116:1116)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1078:1078:1078) (1094:1094:1094)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (618:618:618) (626:626:626)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (619:619:619) (627:627:627)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (619:619:619) (627:627:627)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (619:619:619) (627:627:627)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (397:397:397) (457:457:457)) - (PORT clk (1097:1097:1097) (1114:1114:1114)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (546:546:546) (622:622:622)) - (PORT d[1] (1745:1745:1745) (2043:2043:2043)) - (PORT d[2] (693:693:693) (795:795:795)) - (PORT d[3] (737:737:737) (857:857:857)) - (PORT d[4] (1511:1511:1511) (1768:1768:1768)) - (PORT d[5] (1749:1749:1749) (2050:2050:2050)) - (PORT d[6] (379:379:379) (434:434:434)) - (PORT d[7] (386:386:386) (446:446:446)) - (PORT d[8] (571:571:571) (657:657:657)) - (PORT d[9] (390:390:390) (452:452:452)) - (PORT d[10] (585:585:585) (673:673:673)) - (PORT d[11] (1495:1495:1495) (1741:1741:1741)) - (PORT d[12] (704:704:704) (811:811:811)) - (PORT clk (1095:1095:1095) (1112:1112:1112)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (536:536:536) (563:563:563)) - (PORT clk (1095:1095:1095) (1112:1112:1112)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1114:1114:1114)) - (PORT d[0] (1141:1141:1141) (1215:1215:1215)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1098:1098:1098) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1098:1098:1098) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1098:1098:1098) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1098:1098:1098) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1077:1077:1077) (1093:1093:1093)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (617:617:617) (625:625:625)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (618:618:618) (626:626:626)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (618:618:618) (626:626:626)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (618:618:618) (626:626:626)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[1\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (366:366:366) (439:439:439)) - (PORT datab (358:358:358) (429:429:429)) - (PORT datac (429:429:429) (482:482:482)) - (PORT datad (479:479:479) (551:551:551)) - (IOPATH dataa combout (188:188:188) (184:184:184)) - (IOPATH datab combout (190:190:190) (188:188:188)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (392:392:392) (449:449:449)) - (PORT clk (1096:1096:1096) (1114:1114:1114)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1810:1810:1810) (2056:2056:2056)) - (PORT d[1] (1721:1721:1721) (2012:2012:2012)) - (PORT d[2] (533:533:533) (613:613:613)) - (PORT d[3] (755:755:755) (880:880:880)) - (PORT d[4] (1533:1533:1533) (1796:1796:1796)) - (PORT d[5] (1573:1573:1573) (1841:1841:1841)) - (PORT d[6] (533:533:533) (609:609:609)) - (PORT d[7] (720:720:720) (823:823:823)) - (PORT d[8] (819:819:819) (944:944:944)) - (PORT d[9] (535:535:535) (619:619:619)) - (PORT d[10] (565:565:565) (652:652:652)) - (PORT d[11] (1679:1679:1679) (1958:1958:1958)) - (PORT d[12] (537:537:537) (624:624:624)) - (PORT clk (1094:1094:1094) (1112:1112:1112)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (691:691:691) (739:739:739)) - (PORT clk (1094:1094:1094) (1112:1112:1112)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1096:1096:1096) (1114:1114:1114)) - (PORT d[0] (1110:1110:1110) (1180:1180:1180)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1076:1076:1076) (1093:1093:1093)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (616:616:616) (625:625:625)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (617:617:617) (626:626:626)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (617:617:617) (626:626:626)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (617:617:617) (626:626:626)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (408:408:408) (473:473:473)) - (PORT clk (1096:1096:1096) (1112:1112:1112)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1820:1820:1820) (2069:2069:2069)) - (PORT d[1] (1574:1574:1574) (1849:1849:1849)) - (PORT d[2] (717:717:717) (831:831:831)) - (PORT d[3] (756:756:756) (884:884:884)) - (PORT d[4] (1541:1541:1541) (1805:1805:1805)) - (PORT d[5] (1574:1574:1574) (1853:1853:1853)) - (PORT d[6] (692:692:692) (791:791:791)) - (PORT d[7] (625:625:625) (715:715:715)) - (PORT d[8] (837:837:837) (967:967:967)) - (PORT d[9] (877:877:877) (1007:1007:1007)) - (PORT d[10] (398:398:398) (459:459:459)) - (PORT d[11] (1680:1680:1680) (1954:1954:1954)) - (PORT d[12] (548:548:548) (636:636:636)) - (PORT clk (1094:1094:1094) (1110:1110:1110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (690:690:690) (738:738:738)) - (PORT clk (1094:1094:1094) (1110:1110:1110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1096:1096:1096) (1112:1112:1112)) - (PORT d[0] (1009:1009:1009) (1075:1075:1075)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1113:1113:1113)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1113:1113:1113)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1113:1113:1113)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1113:1113:1113)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1076:1076:1076) (1091:1091:1091)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (616:616:616) (623:623:623)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (617:617:617) (624:624:624)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (617:617:617) (624:624:624)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (617:617:617) (624:624:624)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[1\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (687:687:687) (803:803:803)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datac (547:547:547) (632:632:632)) - (PORT datad (621:621:621) (701:701:701)) - (IOPATH dataa combout (188:188:188) (179:179:179)) - (IOPATH datab combout (196:196:196) (192:192:192)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (411:411:411) (475:475:475)) - (PORT clk (1089:1089:1089) (1107:1107:1107)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1643:1643:1643) (1872:1872:1872)) - (PORT d[1] (1390:1390:1390) (1638:1638:1638)) - (PORT d[2] (876:876:876) (1010:1010:1010)) - (PORT d[3] (1125:1125:1125) (1310:1310:1310)) - (PORT d[4] (1706:1706:1706) (2004:2004:2004)) - (PORT d[5] (1570:1570:1570) (1848:1848:1848)) - (PORT d[6] (730:730:730) (836:836:836)) - (PORT d[7] (750:750:750) (866:866:866)) - (PORT d[8] (999:999:999) (1150:1150:1150)) - (PORT d[9] (872:872:872) (1005:1005:1005)) - (PORT d[10] (1264:1264:1264) (1440:1440:1440)) - (PORT d[11] (1844:1844:1844) (2112:2112:2112)) - (PORT d[12] (729:729:729) (841:841:841)) - (PORT clk (1087:1087:1087) (1105:1105:1105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1646:1646:1646) (1803:1803:1803)) - (PORT clk (1087:1087:1087) (1105:1105:1105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1089:1089:1089) (1107:1107:1107)) - (PORT d[0] (1744:1744:1744) (1905:1905:1905)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1090:1090:1090) (1108:1108:1108)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1090:1090:1090) (1108:1108:1108)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1090:1090:1090) (1108:1108:1108)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1090:1090:1090) (1108:1108:1108)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1044:1044:1044) (1064:1064:1064)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1177:1177:1177) (1330:1330:1330)) - (PORT clk (1049:1049:1049) (1067:1067:1067)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2414:2414:2414) (2742:2742:2742)) - (PORT d[1] (2309:2309:2309) (2604:2604:2604)) - (PORT d[2] (2377:2377:2377) (2705:2705:2705)) - (PORT d[3] (2410:2410:2410) (2738:2738:2738)) - (PORT d[4] (2388:2388:2388) (2717:2717:2717)) - (PORT d[5] (2415:2415:2415) (2707:2707:2707)) - (PORT d[6] (2588:2588:2588) (2951:2951:2951)) - (PORT d[7] (2446:2446:2446) (2756:2756:2756)) - (PORT d[8] (2454:2454:2454) (2760:2760:2760)) - (PORT d[9] (2548:2548:2548) (2918:2918:2918)) - (PORT d[10] (2469:2469:2469) (2774:2774:2774)) - (PORT d[11] (2511:2511:2511) (2836:2836:2836)) - (PORT d[12] (2491:2491:2491) (2835:2835:2835)) - (PORT clk (1046:1046:1046) (1066:1066:1066)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1049:1049:1049) (1067:1067:1067)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1050:1050:1050) (1068:1068:1068)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1050:1050:1050) (1068:1068:1068)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1050:1050:1050) (1068:1068:1068)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1050:1050:1050) (1068:1068:1068)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1438:1438:1438) (1631:1631:1631)) - (PORT d[1] (1172:1172:1172) (1379:1379:1379)) - (PORT d[2] (1335:1335:1335) (1563:1563:1563)) - (PORT d[3] (1428:1428:1428) (1670:1670:1670)) - (PORT d[4] (1729:1729:1729) (2027:2027:2027)) - (PORT d[5] (1311:1311:1311) (1534:1534:1534)) - (PORT d[6] (1094:1094:1094) (1246:1246:1246)) - (PORT d[7] (1420:1420:1420) (1623:1623:1623)) - (PORT d[8] (1591:1591:1591) (1868:1868:1868)) - (PORT d[9] (1016:1016:1016) (1161:1161:1161)) - (PORT d[10] (873:873:873) (992:992:992)) - (PORT d[11] (1938:1938:1938) (2221:2221:2221)) - (PORT d[12] (889:889:889) (1021:1021:1021)) - (PORT clk (1105:1105:1105) (1122:1122:1122)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1105:1105:1105) (1122:1122:1122)) - (PORT d[0] (1274:1274:1274) (1426:1426:1426)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1106:1106:1106) (1123:1123:1123)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1087:1087:1087) (1103:1103:1103)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (627:627:627) (635:635:635)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (628:628:628) (636:636:636)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (628:628:628) (636:636:636)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (628:628:628) (636:636:636)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (847:847:847) (954:954:954)) - (PORT d[1] (1579:1579:1579) (1848:1848:1848)) - (PORT d[2] (553:553:553) (640:640:640)) - (PORT d[3] (947:947:947) (1108:1108:1108)) - (PORT d[4] (1531:1531:1531) (1791:1791:1791)) - (PORT d[5] (1588:1588:1588) (1867:1867:1867)) - (PORT d[6] (553:553:553) (632:632:632)) - (PORT d[7] (541:541:541) (622:622:622)) - (PORT d[8] (817:817:817) (941:941:941)) - (PORT d[9] (884:884:884) (1019:1019:1019)) - (PORT d[10] (1446:1446:1446) (1649:1649:1649)) - (PORT d[11] (1701:1701:1701) (1982:1982:1982)) - (PORT d[12] (715:715:715) (824:824:824)) - (PORT clk (1093:1093:1093) (1110:1110:1110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1093:1093:1093) (1110:1110:1110)) - (PORT d[0] (546:546:546) (501:501:501)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1094:1094:1094) (1111:1111:1111)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1075:1075:1075) (1091:1091:1091)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (615:615:615) (623:623:623)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (616:616:616) (624:624:624)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (616:616:616) (624:624:624)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (616:616:616) (624:624:624)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (494:494:494) (554:554:554)) - (PORT clk (1093:1093:1093) (1110:1110:1110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1800:1800:1800) (2048:2048:2048)) - (PORT d[1] (1566:1566:1566) (1841:1841:1841)) - (PORT d[2] (873:873:873) (1009:1009:1009)) - (PORT d[3] (961:961:961) (1116:1116:1116)) - (PORT d[4] (1712:1712:1712) (2007:2007:2007)) - (PORT d[5] (1587:1587:1587) (1867:1867:1867)) - (PORT d[6] (553:553:553) (633:633:633)) - (PORT d[7] (863:863:863) (998:998:998)) - (PORT d[8] (1771:1771:1771) (2072:2072:2072)) - (PORT d[9] (557:557:557) (646:646:646)) - (PORT d[10] (1448:1448:1448) (1654:1654:1654)) - (PORT d[11] (1688:1688:1688) (1963:1963:1963)) - (PORT d[12] (1278:1278:1278) (1473:1473:1473)) - (PORT clk (1091:1091:1091) (1108:1108:1108)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1724:1724:1724) (1898:1898:1898)) - (PORT clk (1091:1091:1091) (1108:1108:1108)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1093:1093:1093) (1110:1110:1110)) - (PORT d[0] (1046:1046:1046) (1015:1015:1015)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1094:1094:1094) (1111:1111:1111)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1094:1094:1094) (1111:1111:1111)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1094:1094:1094) (1111:1111:1111)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1094:1094:1094) (1111:1111:1111)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1048:1048:1048) (1067:1067:1067)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1342:1342:1342) (1511:1511:1511)) - (PORT clk (1053:1053:1053) (1070:1070:1070)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2545:2545:2545) (2890:2890:2890)) - (PORT d[1] (2355:2355:2355) (2682:2682:2682)) - (PORT d[2] (2365:2365:2365) (2686:2686:2686)) - (PORT d[3] (2422:2422:2422) (2765:2765:2765)) - (PORT d[4] (2372:2372:2372) (2696:2696:2696)) - (PORT d[5] (2509:2509:2509) (2830:2830:2830)) - (PORT d[6] (2634:2634:2634) (3005:3005:3005)) - (PORT d[7] (2483:2483:2483) (2824:2824:2824)) - (PORT d[8] (2457:2457:2457) (2761:2761:2761)) - (PORT d[9] (2566:2566:2566) (2937:2937:2937)) - (PORT d[10] (2510:2510:2510) (2831:2831:2831)) - (PORT d[11] (2433:2433:2433) (2735:2735:2735)) - (PORT d[12] (2433:2433:2433) (2739:2739:2739)) - (PORT clk (1050:1050:1050) (1069:1069:1069)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1053:1053:1053) (1070:1070:1070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1054:1054:1054) (1071:1071:1071)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1054:1054:1054) (1071:1071:1071)) - (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1054:1054:1054) (1071:1071:1071)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1054:1054:1054) (1071:1071:1071)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1049:1049:1049) (1068:1068:1068)) - (IOPATH (posedge clk) q (164:164:164) (166:166:166)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Selector1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (371:371:371) (440:440:440)) - (PORT datab (638:638:638) (739:739:739)) - (PORT datac (453:453:453) (513:513:513)) - (PORT datad (481:481:481) (546:546:546)) - (IOPATH dataa combout (188:188:188) (184:184:184)) - (IOPATH datab combout (190:190:190) (188:188:188)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Selector1\~1) - (DELAY - (ABSOLUTE - (PORT dataa (653:653:653) (748:748:748)) - (PORT datab (638:638:638) (740:740:740)) - (PORT datac (870:870:870) (992:992:992)) - (PORT datad (89:89:89) (106:106:106)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (169:169:169) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~103) - (DELAY - (ABSOLUTE - (PORT dataa (978:978:978) (1137:1137:1137)) - (PORT datab (787:787:787) (919:919:919)) - (PORT datac (358:358:358) (424:424:424)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (182:182:182) (177:177:177)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_io_ibuf") (INSTANCE PS2_DAT\~input) @@ -36080,24 +28878,45 @@ ) ) (CELL - (CELLTYPE "cycloneive_clkctrl") - (INSTANCE reset\~clkctrl) + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE KEY\[0\]\~input) (DELAY (ABSOLUTE - (PORT inclk[0] (477:477:477) (502:502:502)) + (IOPATH i o (153:153:153) (705:705:705)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\~0) + (INSTANCE reset) (DELAY (ABSOLUTE - (PORT dataa (157:157:157) (218:218:218)) - (PORT datab (159:159:159) (214:214:214)) - (PORT datad (131:131:131) (175:175:175)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (PORT datac (1000:1000:1000) (869:869:869)) + (PORT datad (464:464:464) (514:514:514)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE reset\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (313:313:313) (319:319:319)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\~3) + (DELAY + (ABSOLUTE + (PORT dataa (151:151:151) (209:209:209)) + (PORT datab (156:156:156) (213:213:213)) + (PORT datad (136:136:136) (180:180:180)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (176:176:176)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -36117,7 +28936,7 @@ (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[7\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (1960:1960:1960) (2226:2226:2226)) + (PORT datad (1844:1844:1844) (2068:2068:2068)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -36127,9 +28946,9 @@ (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[7\]) (DELAY (ABSOLUTE - (PORT clk (899:899:899) (904:904:904)) + (PORT clk (896:896:896) (900:900:900)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (901:901:901) (907:907:907)) + (PORT clrn (889:889:889) (892:892:892)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -36143,7 +28962,7 @@ (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[6\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (121:121:121) (161:161:161)) + (PORT datad (122:122:122) (161:161:161)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -36153,9 +28972,9 @@ (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[6\]) (DELAY (ABSOLUTE - (PORT clk (899:899:899) (904:904:904)) + (PORT clk (896:896:896) (900:900:900)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (901:901:901) (907:907:907)) + (PORT clrn (889:889:889) (892:892:892)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -36169,7 +28988,7 @@ (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[5\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (124:124:124) (164:164:164)) + (PORT datad (131:131:131) (168:168:168)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -36179,9 +28998,9 @@ (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[5\]) (DELAY (ABSOLUTE - (PORT clk (899:899:899) (904:904:904)) + (PORT clk (896:896:896) (900:900:900)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (901:901:901) (907:907:907)) + (PORT clrn (889:889:889) (892:892:892)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -36195,7 +29014,7 @@ (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[4\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (129:129:129) (166:166:166)) + (PORT datad (121:121:121) (160:160:160)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -36205,9 +29024,9 @@ (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[4\]) (DELAY (ABSOLUTE - (PORT clk (899:899:899) (904:904:904)) + (PORT clk (896:896:896) (900:900:900)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (901:901:901) (907:907:907)) + (PORT clrn (889:889:889) (892:892:892)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -36216,28 +29035,12 @@ (HOLD d (posedge clk) (84:84:84)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|Equal0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (136:136:136) (188:188:188)) - (PORT datab (135:135:135) (186:186:186)) - (PORT datac (200:200:200) (245:245:245)) - (PORT datad (122:122:122) (161:161:161)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[3\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (123:123:123) (162:162:162)) + (PORT datad (122:122:122) (162:162:162)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -36247,9 +29050,9 @@ (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[3\]) (DELAY (ABSOLUTE - (PORT clk (899:899:899) (904:904:904)) + (PORT clk (896:896:896) (900:900:900)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (901:901:901) (907:907:907)) + (PORT clrn (889:889:889) (892:892:892)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -36263,7 +29066,7 @@ (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[2\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (125:125:125) (164:164:164)) + (PORT datad (124:124:124) (164:164:164)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -36273,9 +29076,9 @@ (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[2\]) (DELAY (ABSOLUTE - (PORT clk (899:899:899) (904:904:904)) + (PORT clk (896:896:896) (900:900:900)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (901:901:901) (907:907:907)) + (PORT clrn (889:889:889) (892:892:892)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -36289,7 +29092,7 @@ (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[1\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (122:122:122) (161:161:161)) + (PORT datad (121:121:121) (160:160:160)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -36299,9 +29102,9 @@ (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[1\]) (DELAY (ABSOLUTE - (PORT clk (899:899:899) (904:904:904)) + (PORT clk (896:896:896) (900:900:900)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (901:901:901) (907:907:907)) + (PORT clrn (889:889:889) (892:892:892)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -36310,18 +29113,34 @@ (HOLD d (posedge clk) (84:84:84)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (137:137:137) (189:189:189)) + (PORT datab (135:135:135) (184:184:184)) + (PORT datac (198:198:198) (247:247:247)) + (PORT datad (123:123:123) (163:163:163)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|ps2_keyboard_\|Equal0\~1) (DELAY (ABSOLUTE - (PORT dataa (104:104:104) (136:136:136)) + (PORT dataa (135:135:135) (187:187:187)) (PORT datab (136:136:136) (186:186:186)) - (PORT datac (122:122:122) (164:164:164)) - (PORT datad (123:123:123) (162:162:162)) - (IOPATH dataa combout (170:170:170) (163:163:163)) + (PORT datac (123:123:123) (167:167:167)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -36331,7 +29150,7 @@ (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[0\]\~0) (DELAY (ABSOLUTE - (PORT datac (123:123:123) (166:166:166)) + (PORT datac (124:124:124) (169:169:169)) (IOPATH datac combout (120:120:120) (125:125:125)) ) ) @@ -36341,9 +29160,9 @@ (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[0\]) (DELAY (ABSOLUTE - (PORT clk (899:899:899) (904:904:904)) + (PORT clk (896:896:896) (900:900:900)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (901:901:901) (907:907:907)) + (PORT clrn (889:889:889) (892:892:892)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -36357,9 +29176,9 @@ (INSTANCE ula_\|ps2_keyboard_\|ps2_clk_in\~0) (DELAY (ABSOLUTE - (PORT datab (108:108:108) (139:139:139)) - (PORT datad (123:123:123) (162:162:162)) - (IOPATH datab combout (166:166:166) (176:176:176)) + (PORT dataa (111:111:111) (146:146:146)) + (PORT datad (124:124:124) (164:164:164)) + (IOPATH dataa combout (165:165:165) (173:173:173)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -36370,9 +29189,9 @@ (INSTANCE ula_\|ps2_keyboard_\|ps2_clk_in) (DELAY (ABSOLUTE - (PORT clk (899:899:899) (904:904:904)) + (PORT clk (896:896:896) (900:900:900)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (901:901:901) (907:907:907)) + (PORT clrn (889:889:889) (892:892:892)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -36386,10 +29205,10 @@ (INSTANCE ula_\|ps2_keyboard_\|clk_edge\~0) (DELAY (ABSOLUTE - (PORT datab (109:109:109) (140:140:140)) - (PORT datac (119:119:119) (161:161:161)) - (PORT datad (121:121:121) (159:159:159)) - (IOPATH datab combout (166:166:166) (167:167:167)) + (PORT dataa (112:112:112) (146:146:146)) + (PORT datac (117:117:117) (157:157:157)) + (PORT datad (125:125:125) (165:165:165)) + (IOPATH dataa combout (165:165:165) (163:163:163)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -36400,9 +29219,9 @@ (INSTANCE ula_\|ps2_keyboard_\|clk_edge) (DELAY (ABSOLUTE - (PORT clk (899:899:899) (904:904:904)) + (PORT clk (896:896:896) (900:900:900)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (901:901:901) (907:907:907)) + (PORT clrn (889:889:889) (892:892:892)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -36413,13 +29232,13 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\[0\]) + (INSTANCE ula_\|ps2_keyboard_\|bit_count\[3\]) (DELAY (ABSOLUTE - (PORT clk (907:907:907) (911:911:911)) + (PORT clk (895:895:895) (900:900:900)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (903:903:903) (908:908:908)) - (PORT ena (1092:1092:1092) (1217:1217:1217)) + (PORT clrn (888:888:888) (892:892:892)) + (PORT ena (1246:1246:1246) (1402:1402:1402)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -36434,9 +29253,9 @@ (INSTANCE ula_\|ps2_keyboard_\|bit_count\~1) (DELAY (ABSOLUTE - (PORT dataa (158:158:158) (218:218:218)) - (PORT datab (160:160:160) (214:214:214)) - (PORT datad (128:128:128) (170:170:170)) + (PORT dataa (147:147:147) (204:204:204)) + (PORT datab (153:153:153) (207:207:207)) + (PORT datad (139:139:139) (183:183:183)) (IOPATH dataa combout (165:165:165) (159:159:159)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (190:190:190) (195:195:195)) @@ -36449,43 +29268,10 @@ (INSTANCE ula_\|ps2_keyboard_\|bit_count\[2\]) (DELAY (ABSOLUTE - (PORT clk (907:907:907) (911:911:911)) + (PORT clk (895:895:895) (900:900:900)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (903:903:903) (908:908:908)) - (PORT ena (1092:1092:1092) (1217:1217:1217)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\~3) - (DELAY - (ABSOLUTE - (PORT dataa (153:153:153) (213:213:213)) - (PORT datab (152:152:152) (207:207:207)) - (PORT datad (132:132:132) (175:175:175)) - (IOPATH dataa combout (158:158:158) (173:173:173)) - (IOPATH datab combout (160:160:160) (176:176:176)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (907:907:907) (911:911:911)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (903:903:903) (908:908:908)) - (PORT ena (1092:1092:1092) (1217:1217:1217)) + (PORT clrn (888:888:888) (892:892:892)) + (PORT ena (1246:1246:1246) (1402:1402:1402)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -36500,10 +29286,10 @@ (INSTANCE ula_\|ps2_keyboard_\|bit_count\~2) (DELAY (ABSOLUTE - (PORT dataa (214:214:214) (269:269:269)) - (PORT datab (153:153:153) (209:209:209)) - (PORT datad (133:133:133) (177:177:177)) - (IOPATH dataa combout (158:158:158) (157:157:157)) + (PORT dataa (149:149:149) (208:208:208)) + (PORT datab (154:154:154) (211:211:211)) + (PORT datad (134:134:134) (178:178:178)) + (IOPATH dataa combout (195:195:195) (203:203:203)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -36515,10 +29301,43 @@ (INSTANCE ula_\|ps2_keyboard_\|bit_count\[1\]) (DELAY (ABSOLUTE - (PORT clk (907:907:907) (911:911:911)) + (PORT clk (895:895:895) (900:900:900)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (903:903:903) (908:908:908)) - (PORT ena (1092:1092:1092) (1217:1217:1217)) + (PORT clrn (888:888:888) (892:892:892)) + (PORT ena (1246:1246:1246) (1402:1402:1402)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\~0) + (DELAY + (ABSOLUTE + (PORT dataa (152:152:152) (211:211:211)) + (PORT datab (149:149:149) (205:205:205)) + (PORT datad (138:138:138) (181:181:181)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (895:895:895) (900:900:900)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (888:888:888) (892:892:892)) + (PORT ena (1246:1246:1246) (1402:1402:1402)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -36533,10 +29352,10 @@ (INSTANCE ula_\|ps2_keyboard_\|always1\~0) (DELAY (ABSOLUTE - (PORT dataa (151:151:151) (210:210:210)) - (PORT datab (156:156:156) (210:210:210)) - (PORT datac (2001:2001:2001) (2280:2280:2280)) - (PORT datad (138:138:138) (182:182:182)) + (PORT dataa (150:150:150) (207:207:207)) + (PORT datab (155:155:155) (212:212:212)) + (PORT datac (2398:2398:2398) (2750:2750:2750)) + (PORT datad (130:130:130) (173:173:173)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (124:124:124)) @@ -36549,11 +29368,11 @@ (INSTANCE ula_\|ps2_keyboard_\|LessThan0\~0) (DELAY (ABSOLUTE - (PORT datab (157:157:157) (212:212:212)) - (PORT datac (139:139:139) (189:189:189)) - (PORT datad (135:135:135) (179:179:179)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT dataa (150:150:150) (207:207:207)) + (PORT datab (153:153:153) (210:210:210)) + (PORT datad (134:134:134) (178:178:178)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (167:167:167) (158:158:158)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -36563,12 +29382,12 @@ (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[0\]\~0) (DELAY (ABSOLUTE - (PORT dataa (106:106:106) (138:138:138)) - (PORT datab (143:143:143) (196:196:196)) - (PORT datac (760:760:760) (876:876:876)) - (PORT datad (96:96:96) (115:115:115)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT dataa (146:146:146) (203:203:203)) + (PORT datab (106:106:106) (135:135:135)) + (PORT datac (915:915:915) (1065:1065:1065)) + (PORT datad (95:95:95) (114:114:114)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -36579,10 +29398,10 @@ (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[8\]) (DELAY (ABSOLUTE - (PORT clk (913:913:913) (917:917:917)) - (PORT asdata (2292:2292:2292) (2579:2579:2579)) - (PORT clrn (909:909:909) (914:914:914)) - (PORT ena (638:638:638) (688:688:688)) + (PORT clk (906:906:906) (911:911:911)) + (PORT asdata (2390:2390:2390) (2706:2706:2706)) + (PORT clrn (892:892:892) (897:897:897)) + (PORT ena (973:973:973) (1072:1072:1072)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -36592,21 +29411,31 @@ (HOLD ena (posedge clk) (84:84:84)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (117:117:117) (154:154:154)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[7\]) (DELAY (ABSOLUTE - (PORT clk (913:913:913) (917:917:917)) - (PORT asdata (294:294:294) (333:333:333)) - (PORT clrn (909:909:909) (914:914:914)) - (PORT ena (638:638:638) (688:688:688)) + (PORT clk (906:906:906) (911:911:911)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (892:892:892) (897:897:897)) + (PORT ena (973:973:973) (1072:1072:1072)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) + (HOLD d (posedge clk) (84:84:84)) (HOLD ena (posedge clk) (84:84:84)) ) ) @@ -36615,10 +29444,10 @@ (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[6\]) (DELAY (ABSOLUTE - (PORT clk (913:913:913) (917:917:917)) - (PORT asdata (320:320:320) (365:365:365)) - (PORT clrn (909:909:909) (914:914:914)) - (PORT ena (638:638:638) (688:688:688)) + (PORT clk (906:906:906) (911:911:911)) + (PORT asdata (336:336:336) (384:384:384)) + (PORT clrn (892:892:892) (897:897:897)) + (PORT ena (973:973:973) (1072:1072:1072)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -36633,10 +29462,10 @@ (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[5\]) (DELAY (ABSOLUTE - (PORT clk (913:913:913) (917:917:917)) - (PORT asdata (310:310:310) (352:352:352)) - (PORT clrn (909:909:909) (914:914:914)) - (PORT ena (638:638:638) (688:688:688)) + (PORT clk (906:906:906) (911:911:911)) + (PORT asdata (554:554:554) (634:634:634)) + (PORT clrn (892:892:892) (897:897:897)) + (PORT ena (973:973:973) (1072:1072:1072)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -36651,10 +29480,10 @@ (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[4\]) (DELAY (ABSOLUTE - (PORT clk (913:913:913) (917:917:917)) - (PORT asdata (499:499:499) (556:556:556)) - (PORT clrn (908:908:908) (914:914:914)) - (PORT ena (632:632:632) (688:688:688)) + (PORT clk (906:906:906) (911:911:911)) + (PORT asdata (431:431:431) (502:502:502)) + (PORT clrn (892:892:892) (897:897:897)) + (PORT ena (973:973:973) (1072:1072:1072)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -36669,10 +29498,10 @@ (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[3\]) (DELAY (ABSOLUTE - (PORT clk (913:913:913) (917:917:917)) - (PORT asdata (506:506:506) (568:568:568)) - (PORT clrn (909:909:909) (914:914:914)) - (PORT ena (638:638:638) (688:688:688)) + (PORT clk (902:902:902) (908:908:908)) + (PORT asdata (846:846:846) (962:962:962)) + (PORT clrn (895:895:895) (899:899:899)) + (PORT ena (1240:1240:1240) (1367:1367:1367)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -36687,10 +29516,10 @@ (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[2\]) (DELAY (ABSOLUTE - (PORT clk (913:913:913) (917:917:917)) - (PORT asdata (499:499:499) (563:563:563)) - (PORT clrn (908:908:908) (914:914:914)) - (PORT ena (632:632:632) (688:688:688)) + (PORT clk (906:906:906) (911:911:911)) + (PORT asdata (810:810:810) (934:934:934)) + (PORT clrn (892:892:892) (897:897:897)) + (PORT ena (1066:1066:1066) (1176:1176:1176)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -36705,10 +29534,10 @@ (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[1\]) (DELAY (ABSOLUTE - (PORT clk (913:913:913) (917:917:917)) - (PORT asdata (402:402:402) (464:464:464)) - (PORT clrn (908:908:908) (914:914:914)) - (PORT ena (632:632:632) (688:688:688)) + (PORT clk (906:906:906) (911:911:911)) + (PORT asdata (319:319:319) (364:364:364)) + (PORT clrn (892:892:892) (897:897:897)) + (PORT ena (1066:1066:1066) (1176:1176:1176)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -36718,93 +29547,43 @@ (HOLD ena (posedge clk) (84:84:84)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (640:640:640) (770:770:770)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[0\]) (DELAY (ABSOLUTE - (PORT clk (913:913:913) (917:917:917)) - (PORT asdata (405:405:405) (477:477:477)) - (PORT clrn (908:908:908) (914:914:914)) - (PORT ena (632:632:632) (688:688:688)) + (PORT clk (898:898:898) (903:903:903)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (891:891:891) (895:895:895)) + (PORT ena (662:662:662) (725:725:725)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) + (HOLD d (posedge clk) (84:84:84)) (HOLD ena (posedge clk) (84:84:84)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Equal0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (532:532:532) (640:640:640)) - (PORT datab (370:370:370) (447:447:447)) - (PORT datac (426:426:426) (527:527:527)) - (PORT datad (425:425:425) (531:531:531)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Equal0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (791:791:791) (953:953:953)) - (PORT datab (514:514:514) (619:619:619)) - (PORT datac (89:89:89) (111:111:111)) - (PORT datad (422:422:422) (528:528:528)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|extended\~0) - (DELAY - (ABSOLUTE - (PORT datab (592:592:592) (716:716:716)) - (PORT datad (423:423:423) (484:484:484)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (342:342:342) (413:413:413)) - (PORT datab (157:157:157) (211:211:211)) - (PORT datad (440:440:440) (513:513:513)) - (IOPATH dataa combout (195:195:195) (193:193:193)) - (IOPATH datab combout (196:196:196) (193:193:193)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~0) (DELAY (ABSOLUTE - (PORT dataa (388:388:388) (492:492:492)) - (PORT datab (357:357:357) (432:432:432)) - (PORT datac (340:340:340) (413:413:413)) - (PORT datad (234:234:234) (292:292:292)) + (PORT dataa (650:650:650) (791:791:791)) + (PORT datab (174:174:174) (234:234:234)) + (PORT datac (534:534:534) (642:642:642)) + (PORT datad (525:525:525) (617:617:617)) (IOPATH dataa combout (195:195:195) (193:193:193)) (IOPATH datab combout (196:196:196) (193:193:193)) (IOPATH datac combout (120:120:120) (125:125:125)) @@ -36812,15 +29591,30 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (252:252:252) (326:326:326)) + (PORT datab (269:269:269) (346:346:346)) + (PORT datad (239:239:239) (286:286:286)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (196:196:196) (193:193:193)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~2) (DELAY (ABSOLUTE - (PORT datab (358:358:358) (433:433:433)) - (PORT datac (174:174:174) (210:210:210)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH datab combout (196:196:196) (205:205:205)) + (PORT dataa (572:572:572) (692:692:692)) + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (442:442:442) (528:528:528)) + (IOPATH dataa combout (195:195:195) (203:203:203)) (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -36831,10 +29625,10 @@ (INSTANCE ula_\|ps2_keyboard_\|scan_code_ready\~0) (DELAY (ABSOLUTE - (PORT dataa (109:109:109) (141:141:141)) - (PORT datab (2011:2011:2011) (2305:2305:2305)) - (PORT datac (760:760:760) (876:876:876)) - (PORT datad (192:192:192) (226:226:226)) + (PORT dataa (2420:2420:2420) (2773:2773:2773)) + (PORT datab (925:925:925) (1082:1082:1082)) + (PORT datac (333:333:333) (391:391:391)) + (PORT datad (94:94:94) (113:113:113)) (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -36847,9 +29641,9 @@ (INSTANCE ula_\|ps2_keyboard_\|scan_code_ready) (DELAY (ABSOLUTE - (PORT clk (907:907:907) (911:911:911)) + (PORT clk (895:895:895) (900:900:900)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (903:903:903) (908:908:908)) + (PORT clrn (888:888:888) (892:892:892)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -36858,15 +29652,91 @@ (HOLD d (posedge clk) (84:84:84)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (230:230:230) (286:286:286)) + (PORT datab (549:549:549) (657:657:657)) + (PORT datac (494:494:494) (595:595:595)) + (PORT datad (374:374:374) (451:451:451)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (384:384:384) (476:476:476)) + (PORT datab (367:367:367) (441:441:441)) + (PORT datac (89:89:89) (110:110:110)) + (PORT datad (1229:1229:1229) (1441:1441:1441)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|released\~0) + (DELAY + (ABSOLUTE + (PORT dataa (158:158:158) (214:214:214)) + (PORT datab (686:686:686) (803:803:803)) + (PORT datad (173:173:173) (204:204:204)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (176:176:176)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|released) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (911:911:911)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (892:892:892) (897:897:897)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|extended\~0) + (DELAY + (ABSOLUTE + (PORT dataa (186:186:186) (227:227:227)) + (PORT datad (512:512:512) (613:613:613)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|zx_keyboard_\|extended) (DELAY (ABSOLUTE - (PORT clk (914:914:914) (918:918:918)) + (PORT clk (906:906:906) (911:911:911)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (910:910:910) (915:915:915)) - (PORT ena (933:933:933) (1038:1038:1038)) + (PORT clrn (892:892:892) (897:897:897)) + (PORT ena (989:989:989) (1104:1104:1104)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -36878,26 +29748,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~15) + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~21) (DELAY (ABSOLUTE - (PORT dataa (363:363:363) (447:447:447)) - (PORT datab (359:359:359) (424:424:424)) - (PORT datac (142:142:142) (190:190:190)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (257:257:257) (316:316:316)) - (PORT datac (759:759:759) (914:914:914)) - (PORT datad (448:448:448) (517:517:517)) + (PORT dataa (266:266:266) (338:338:338)) + (PORT datac (159:159:159) (209:209:209)) + (PORT datad (667:667:667) (778:778:778)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -36906,293 +29762,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~37) + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~22) (DELAY (ABSOLUTE - (PORT dataa (652:652:652) (771:771:771)) - (PORT datac (346:346:346) (412:412:412)) - (PORT datad (492:492:492) (585:585:585)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|shifted\~0) - (DELAY - (ABSOLUTE - (PORT dataa (204:204:204) (246:246:246)) - (PORT datac (322:322:322) (381:381:381)) - (PORT datad (403:403:403) (480:480:480)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|released\~0) - (DELAY - (ABSOLUTE - (PORT dataa (354:354:354) (427:427:427)) - (PORT datab (359:359:359) (423:423:423)) - (PORT datad (730:730:730) (836:836:836)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|released) - (DELAY - (ABSOLUTE - (PORT clk (913:913:913) (917:917:917)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (909:909:909) (914:914:914)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr17\~0) - (DELAY - (ABSOLUTE - (PORT dataa (253:253:253) (328:328:328)) - (PORT datab (352:352:352) (427:427:427)) - (PORT datac (322:322:322) (387:387:387)) - (PORT datad (141:141:141) (183:183:183)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|shifted\~2) - (DELAY - (ABSOLUTE - (PORT dataa (105:105:105) (137:137:137)) - (PORT datac (221:221:221) (285:285:285)) - (PORT datad (347:347:347) (422:422:422)) - (IOPATH dataa combout (165:165:165) (163:163:163)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|shifted\~3) - (DELAY - (ABSOLUTE - (PORT dataa (302:302:302) (352:352:352)) - (PORT datab (227:227:227) (289:289:289)) - (PORT datad (91:91:91) (108:108:108)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|shifted) - (DELAY - (ABSOLUTE - (PORT clk (913:913:913) (917:917:917)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (908:908:908) (914:914:914)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (409:409:409) (504:504:504)) - (PORT datab (538:538:538) (642:642:642)) - (PORT datad (526:526:526) (622:622:622)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~38) - (DELAY - (ABSOLUTE - (PORT datab (419:419:419) (519:519:519)) - (PORT datac (410:410:410) (505:505:505)) - (PORT datad (414:414:414) (506:506:506)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~39) - (DELAY - (ABSOLUTE - (PORT dataa (181:181:181) (225:225:225)) - (PORT datab (106:106:106) (135:135:135)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (911:911:911) (916:916:916)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]\~31) - (DELAY - (ABSOLUTE - (PORT datab (516:516:516) (623:623:623)) - (PORT datad (412:412:412) (504:504:504)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (410:410:410) (492:492:492)) - (PORT datab (157:157:157) (211:211:211)) - (PORT datac (351:351:351) (426:426:426)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~32) - (DELAY - (ABSOLUTE - (PORT datab (348:348:348) (421:421:421)) - (PORT datac (210:210:210) (264:264:264)) - (PORT datad (342:342:342) (420:420:420)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (196:196:196) (240:240:240)) - (PORT datab (117:117:117) (150:150:150)) - (PORT datac (345:345:345) (419:419:419)) - (PORT datad (229:229:229) (286:286:286)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (119:119:119) (151:151:151)) - (PORT datab (343:343:343) (405:405:405)) - (PORT datad (525:525:525) (621:621:621)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH datab combout (190:190:190) (181:181:181)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (911:911:911) (916:916:916)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (630:630:630) (743:743:743)) - (PORT datab (129:129:129) (177:177:177)) - (PORT datac (117:117:117) (158:158:158)) - (PORT datad (289:289:289) (337:337:337)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (528:528:528) (633:633:633)) - (PORT datac (493:493:493) (593:593:593)) + (PORT dataa (357:357:357) (431:431:431)) + (PORT datac (142:142:142) (189:189:189)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datac combout (119:119:119) (124:124:124)) ) @@ -37200,105 +29774,44 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~28) + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]\~23) (DELAY (ABSOLUTE - (PORT dataa (789:789:789) (950:950:950)) - (PORT datab (379:379:379) (444:444:444)) - (PORT datac (518:518:518) (616:616:616)) - (PORT datad (100:100:100) (122:122:122)) + (PORT dataa (485:485:485) (588:588:588)) + (PORT datab (552:552:552) (663:663:663)) + (PORT datac (474:474:474) (564:564:564)) + (PORT datad (864:864:864) (1011:1011:1011)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (412:412:412) (499:499:499)) + (PORT datab (545:545:545) (675:675:675)) + (PORT datad (105:105:105) (123:123:123)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (504:504:504) (603:603:603)) + (PORT datab (342:342:342) (422:422:422)) + (PORT datad (199:199:199) (234:234:234)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~29) - (DELAY - (ABSOLUTE - (PORT datab (536:536:536) (640:640:640)) - (PORT datac (405:405:405) (503:503:503)) - (PORT datad (413:413:413) (506:506:506)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (446:446:446) (547:547:547)) - (PORT datab (349:349:349) (412:412:412)) - (PORT datad (259:259:259) (295:295:295)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (910:910:910) (916:916:916)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (787:787:787) (948:948:948)) - (PORT datab (111:111:111) (143:143:143)) - (PORT datac (364:364:364) (422:422:422)) - (PORT datad (426:426:426) (532:532:532)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (398:398:398) (490:490:490)) - (PORT datab (187:187:187) (226:226:226)) - (PORT datac (396:396:396) (487:487:487)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (872:872:872) (1025:1025:1025)) - (PORT datab (521:521:521) (620:620:620)) - (PORT datad (268:268:268) (306:306:306)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -37309,9 +29822,9 @@ (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]) (DELAY (ABSOLUTE - (PORT clk (914:914:914) (918:918:918)) + (PORT clk (903:903:903) (908:908:908)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (909:909:909) (914:914:914)) + (PORT clrn (895:895:895) (899:899:899)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -37325,23 +29838,374 @@ (INSTANCE ula_\|zx_keyboard_\|key_row\~0) (DELAY (ABSOLUTE - (PORT datab (844:844:844) (993:993:993)) - (PORT datac (497:497:497) (594:594:594)) - (PORT datad (116:116:116) (153:153:153)) + (PORT datab (1344:1344:1344) (1589:1589:1589)) + (PORT datac (1044:1044:1044) (1208:1208:1208)) + (PORT datad (117:117:117) (153:153:153)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (483:483:483) (585:585:585)) + (PORT datab (555:555:555) (666:666:666)) + (PORT datac (474:474:474) (564:564:564)) + (PORT datad (520:520:520) (642:642:642)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (740:740:740) (880:880:880)) + (PORT datab (538:538:538) (643:643:643)) + (PORT datad (212:212:212) (269:269:269)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (325:325:325) (376:376:376)) + (PORT datab (511:511:511) (610:610:610)) + (PORT datad (98:98:98) (119:119:119)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (895:895:895) (899:899:899)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[11\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (796:796:796) (912:912:912)) + (PORT datab (735:735:735) (855:855:855)) + (PORT datad (158:158:158) (183:183:183)) + (IOPATH dataa combout (172:172:172) (165:165:165)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (912:912:912) (899:899:899)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (507:507:507) (569:569:569)) + (PORT sload (1093:1093:1093) (1226:1226:1226)) + (PORT ena (1226:1226:1226) (1349:1349:1349)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[11\]\~19) + (DELAY + (ABSOLUTE + (PORT datac (1164:1164:1164) (1357:1357:1357)) + (PORT datad (684:684:684) (802:802:802)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (259:259:259) (328:328:328)) + (PORT datab (395:395:395) (483:483:483)) + (PORT datac (161:161:161) (212:212:212)) + (PORT datad (667:667:667) (778:778:778)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (663:663:663) (781:781:781)) + (PORT datab (389:389:389) (471:471:471)) + (PORT datac (539:539:539) (641:641:641)) + (PORT datad (1241:1241:1241) (1452:1452:1452)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (841:841:841) (989:989:989)) + (PORT datab (518:518:518) (622:622:622)) + (PORT datac (326:326:326) (385:385:385)) + (PORT datad (178:178:178) (212:212:212)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (418:418:418) (520:520:520)) + (PORT datad (92:92:92) (109:109:109)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (895:895:895) (899:899:899)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[9\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (770:770:770) (877:877:877)) + (PORT datab (481:481:481) (555:555:555)) + (PORT datad (95:95:95) (115:115:115)) + (IOPATH dataa combout (172:172:172) (165:165:165)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (912:912:912) (900:900:900)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (307:307:307) (347:347:347)) + (PORT sload (1116:1116:1116) (1249:1249:1249)) + (PORT ena (1058:1058:1058) (1163:1163:1163)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[9\]\~17) + (DELAY + (ABSOLUTE + (PORT datab (141:141:141) (189:189:189)) + (PORT datac (1344:1344:1344) (1561:1561:1561)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~13) + (DELAY + (ABSOLUTE + (PORT datab (685:685:685) (802:802:802)) + (PORT datac (160:160:160) (211:211:211)) + (PORT datad (172:172:172) (203:203:203)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|shifted\~2) + (DELAY + (ABSOLUTE + (PORT datab (561:561:561) (671:671:671)) + (PORT datac (379:379:379) (457:457:457)) + (PORT datad (323:323:323) (369:369:369)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~14) (DELAY (ABSOLUTE - (PORT datab (227:227:227) (288:288:288)) - (PORT datac (605:605:605) (707:707:707)) - (PORT datad (347:347:347) (421:421:421)) + (PORT dataa (572:572:572) (692:692:692)) + (PORT datab (171:171:171) (231:231:231)) + (PORT datac (530:530:530) (638:638:638)) + (PORT datad (524:524:524) (616:616:616)) + (IOPATH dataa combout (172:172:172) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (571:571:571) (691:691:691)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (532:532:532) (640:640:640)) + (PORT datad (635:635:635) (764:764:764)) + (IOPATH dataa combout (158:158:158) (173:173:173)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr17\~0) + (DELAY + (ABSOLUTE + (PORT dataa (651:651:651) (792:792:792)) + (PORT datab (174:174:174) (234:234:234)) + (PORT datac (531:531:531) (639:639:639)) + (PORT datad (501:501:501) (595:595:595)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|shifted\~5) + (DELAY + (ABSOLUTE + (PORT dataa (573:573:573) (694:694:694)) + (PORT datab (538:538:538) (639:639:639)) + (PORT datac (164:164:164) (193:193:193)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|shifted\~4) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (135:135:135)) + (PORT datab (629:629:629) (735:735:735)) + (PORT datad (468:468:468) (532:532:532)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|shifted) + (DELAY + (ABSOLUTE + (PORT clk (898:898:898) (903:903:903)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (891:891:891) (895:895:895)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~12) + (DELAY + (ABSOLUTE + (PORT datab (632:632:632) (739:739:739)) + (PORT datac (144:144:144) (185:185:185)) + (PORT datad (547:547:547) (662:662:662)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -37353,43 +30217,11 @@ (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~16) (DELAY (ABSOLUTE - (PORT dataa (372:372:372) (451:451:451)) - (PORT datab (217:217:217) (280:280:280)) - (PORT datac (322:322:322) (387:387:387)) - (PORT datad (141:141:141) (183:183:183)) - (IOPATH dataa combout (188:188:188) (179:179:179)) - (IOPATH datab combout (188:188:188) (177:177:177)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (254:254:254) (329:329:329)) - (PORT datab (353:353:353) (428:428:428)) - (PORT datac (259:259:259) (297:297:297)) - (PORT datad (349:349:349) (423:423:423)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (188:188:188) (177:177:177)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (302:302:302) (353:353:353)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (PORT dataa (481:481:481) (557:557:557)) + (PORT datab (105:105:105) (134:134:134)) + (PORT datad (93:93:93) (111:111:111)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datab combout (190:190:190) (181:181:181)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -37400,9 +30232,9 @@ (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]) (DELAY (ABSOLUTE - (PORT clk (913:913:913) (917:917:917)) + (PORT clk (898:898:898) (903:903:903)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (908:908:908) (914:914:914)) + (PORT clrn (891:891:891) (895:895:895)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -37413,14 +30245,208 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~19) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[8\]\~8) (DELAY (ABSOLUTE - (PORT dataa (378:378:378) (457:457:457)) - (PORT datab (668:668:668) (791:791:791)) - (PORT datac (229:229:229) (287:287:287)) - (PORT datad (580:580:580) (661:661:661)) + (PORT dataa (769:769:769) (876:876:876)) + (PORT datab (536:536:536) (620:620:620)) + (PORT datad (89:89:89) (106:106:106)) + (IOPATH dataa combout (172:172:172) (165:165:165)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (912:912:912) (900:900:900)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (387:387:387) (436:436:436)) + (PORT sload (1116:1116:1116) (1249:1249:1249)) + (PORT ena (1058:1058:1058) (1163:1163:1163)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[8\]\~18) + (DELAY + (ABSOLUTE + (PORT datac (1326:1326:1326) (1566:1566:1566)) + (PORT datad (799:799:799) (931:931:931)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (364:364:364) (451:451:451)) + (PORT datab (598:598:598) (692:692:692)) + (PORT datac (452:452:452) (553:553:553)) + (PORT datad (105:105:105) (122:122:122)) (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (106:106:106) (138:138:138)) + (PORT datab (203:203:203) (262:262:262)) + (PORT datac (572:572:572) (653:653:653)) + (PORT datad (89:89:89) (107:107:107)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[12\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (794:794:794) (910:910:910)) + (PORT datab (174:174:174) (214:214:214)) + (PORT datad (281:281:281) (324:324:324)) + (IOPATH dataa combout (172:172:172) (165:165:165)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (912:912:912) (899:899:899)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (310:310:310) (351:351:351)) + (PORT sload (1093:1093:1093) (1226:1226:1226)) + (PORT ena (1226:1226:1226) (1349:1349:1349)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[12\]\~21) + (DELAY + (ABSOLUTE + (PORT datac (1339:1339:1339) (1554:1554:1554)) + (PORT datad (543:543:543) (646:646:646)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|d1_out) + (DELAY + (ABSOLUTE + (PORT datab (196:196:196) (236:236:236)) + (PORT datad (212:212:212) (259:259:259)) + (IOPATH datab combout (192:192:192) (181:181:181)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[13\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (797:797:797) (914:914:914)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datad (102:102:102) (119:119:119)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (912:912:912) (899:899:899)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (508:508:508) (570:570:570)) + (PORT sload (1093:1093:1093) (1226:1226:1226)) + (PORT ena (1226:1226:1226) (1349:1349:1349)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[13\]\~20) + (DELAY + (ABSOLUTE + (PORT datab (1443:1443:1443) (1702:1702:1702)) + (PORT datad (1242:1242:1242) (1458:1458:1458)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (505:505:505) (603:603:603)) + (PORT datac (362:362:362) (437:437:437)) + (PORT datad (547:547:547) (653:653:653)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~34) + (DELAY + (ABSOLUTE + (PORT datab (384:384:384) (466:466:466)) + (PORT datac (378:378:378) (456:456:456)) + (PORT datad (322:322:322) (369:369:369)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -37429,15 +30455,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~20) + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~35) (DELAY (ABSOLUTE - (PORT dataa (407:407:407) (502:502:502)) - (PORT datab (777:777:777) (933:933:933)) - (PORT datac (489:489:489) (592:592:592)) - (PORT datad (461:461:461) (545:545:545)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT dataa (348:348:348) (407:407:407)) + (PORT datac (553:553:553) (664:664:664)) + (PORT datad (384:384:384) (460:460:460)) + (IOPATH dataa combout (166:166:166) (163:163:163)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -37445,28 +30469,28 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]\~21) + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~33) (DELAY (ABSOLUTE - (PORT dataa (119:119:119) (156:156:156)) - (PORT datab (117:117:117) (145:145:145)) - (PORT datac (403:403:403) (499:499:499)) - (PORT datad (864:864:864) (1017:1017:1017)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (PORT dataa (796:796:796) (939:939:939)) + (PORT datab (389:389:389) (465:465:465)) + (PORT datad (498:498:498) (591:591:591)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]\~22) + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~37) (DELAY (ABSOLUTE - (PORT datab (269:269:269) (309:309:309)) - (PORT datad (503:503:503) (596:596:596)) - (IOPATH datab combout (191:191:191) (181:181:181)) + (PORT dataa (105:105:105) (137:137:137)) + (PORT datab (110:110:110) (140:140:140)) + (PORT datad (93:93:93) (111:111:111)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datab combout (190:190:190) (181:181:181)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -37474,12 +30498,85 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]) + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]) (DELAY (ABSOLUTE - (PORT clk (914:914:914) (918:918:918)) + (PORT clk (904:904:904) (909:909:909)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (909:909:909) (914:914:914)) + (PORT clrn (897:897:897) (901:901:901)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]\~29) + (DELAY + (ABSOLUTE + (PORT datac (532:532:532) (634:634:634)) + (PORT datad (351:351:351) (421:421:421)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (564:564:564) (683:683:683)) + (PORT datab (687:687:687) (806:806:806)) + (PORT datac (540:540:540) (649:649:649)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (218:218:218) (280:280:280)) + (PORT datab (352:352:352) (414:414:414)) + (PORT datac (178:178:178) (207:207:207)) + (PORT datad (490:490:490) (575:575:575)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (404:404:404)) + (PORT datab (508:508:508) (610:610:610)) + (PORT datad (165:165:165) (193:193:193)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (909:909:909)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (897:897:897) (901:901:901)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -37493,75 +30590,71 @@ (INSTANCE D\[1\]\~28) (DELAY (ABSOLUTE - (PORT dataa (358:358:358) (434:434:434)) - (PORT datab (636:636:636) (744:744:744)) - (PORT datac (347:347:347) (415:415:415)) - (PORT datad (117:117:117) (153:153:153)) - (IOPATH dataa combout (158:158:158) (157:157:157)) + (PORT dataa (313:313:313) (374:374:374)) + (PORT datab (418:418:418) (476:476:476)) + (PORT datac (116:116:116) (156:156:156)) + (PORT datad (116:116:116) (153:153:153)) + (IOPATH dataa combout (165:165:165) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~29) + (INSTANCE z80_\|address_pins_\|abus\[0\]\~16) (DELAY (ABSOLUTE - (PORT dataa (372:372:372) (450:450:450)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datac (103:103:103) (125:125:125)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) + (PORT datab (505:505:505) (607:607:607)) + (PORT datac (1528:1528:1528) (1796:1796:1796)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~41) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[14\]\~14) (DELAY (ABSOLUTE - (PORT dataa (254:254:254) (313:313:313)) - (PORT datab (666:666:666) (789:789:789)) - (PORT datac (407:407:407) (504:504:504)) - (PORT datad (448:448:448) (518:518:518)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (PORT dataa (793:793:793) (909:909:909)) + (PORT datab (115:115:115) (142:142:142)) + (PORT datad (160:160:160) (185:185:185)) + (IOPATH dataa combout (172:172:172) (165:165:165)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~42) + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[14\]) (DELAY (ABSOLUTE - (PORT dataa (413:413:413) (523:523:523)) - (PORT datab (491:491:491) (586:586:586)) - (PORT datac (597:597:597) (701:701:701)) - (PORT datad (385:385:385) (471:471:471)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (188:188:188) (177:177:177)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) + (PORT clk (912:912:912) (899:899:899)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (309:309:309) (356:356:356)) + (PORT sload (1093:1093:1093) (1226:1226:1226)) + (PORT ena (1226:1226:1226) (1349:1349:1349)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~43) + (INSTANCE z80_\|address_pins_\|abus\[14\]\~23) (DELAY (ABSOLUTE - (PORT dataa (185:185:185) (226:226:226)) - (PORT datac (383:383:383) (467:467:467)) - (PORT datad (92:92:92) (109:109:109)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT datac (1425:1425:1425) (1684:1684:1684)) + (PORT datad (898:898:898) (1064:1064:1064)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -37571,23 +30664,71 @@ (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~40) (DELAY (ABSOLUTE - (PORT dataa (425:425:425) (518:518:518)) - (PORT datab (489:489:489) (584:584:584)) - (PORT datac (360:360:360) (437:437:437)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT dataa (533:533:533) (641:641:641)) + (PORT datab (673:673:673) (789:789:789)) + (PORT datad (729:729:729) (855:855:855)) + (IOPATH dataa combout (172:172:172) (165:165:165)) + (IOPATH datab combout (169:169:169) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~44) + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~41) (DELAY (ABSOLUTE - (PORT dataa (103:103:103) (134:134:134)) - (PORT datad (93:93:93) (111:111:111)) + (PORT dataa (537:537:537) (646:646:646)) + (PORT datab (226:226:226) (293:293:293)) + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (524:524:524) (620:620:620)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (419:419:419) (524:524:524)) + (PORT datab (405:405:405) (496:496:496)) + (PORT datac (294:294:294) (338:338:338)) + (PORT datad (228:228:228) (279:279:279)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (547:547:547) (651:651:651)) + (PORT datac (517:517:517) (617:617:617)) + (PORT datad (492:492:492) (586:586:586)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (136:136:136)) + (PORT datab (345:345:345) (409:409:409)) + (PORT datad (91:91:91) (108:108:108)) (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datab combout (190:190:190) (181:181:181)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -37598,9 +30739,9 @@ (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]) (DELAY (ABSOLUTE - (PORT clk (914:914:914) (918:918:918)) + (PORT clk (903:903:903) (908:908:908)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (909:909:909) (914:914:914)) + (PORT clrn (895:895:895) (899:899:899)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -37611,31 +30752,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~45) + (INSTANCE ula_\|zx_keyboard_\|WideOr16\~4) (DELAY (ABSOLUTE - (PORT dataa (342:342:342) (419:419:419)) - (PORT datab (272:272:272) (339:339:339)) - (PORT datac (209:209:209) (264:264:264)) - (PORT datad (312:312:312) (367:367:367)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr16\~5) - (DELAY - (ABSOLUTE - (PORT dataa (450:450:450) (562:562:562)) - (PORT datab (516:516:516) (621:621:621)) - (PORT datac (428:428:428) (529:529:529)) - (PORT datad (421:421:421) (528:528:528)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (190:190:190) (205:205:205)) + (PORT dataa (653:653:653) (794:794:794)) + (PORT datab (171:171:171) (232:232:232)) + (PORT datac (531:531:531) (639:639:639)) + (PORT datad (524:524:524) (616:616:616)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH datab combout (166:166:166) (158:158:158)) (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -37646,27 +30771,11 @@ (INSTANCE ula_\|zx_keyboard_\|WideOr16\~2) (DELAY (ABSOLUTE - (PORT dataa (445:445:445) (555:555:555)) - (PORT datab (439:439:439) (541:541:541)) - (PORT datad (424:424:424) (530:530:530)) - (IOPATH dataa combout (158:158:158) (157:157:157)) + (PORT datab (170:170:170) (229:229:229)) + (PORT datac (527:527:527) (635:635:635)) + (PORT datad (641:641:641) (771:771:771)) (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr16\~4) - (DELAY - (ABSOLUTE - (PORT dataa (447:447:447) (558:558:558)) - (PORT datab (514:514:514) (619:619:619)) - (PORT datac (424:424:424) (525:525:525)) - (PORT datad (423:423:423) (529:529:529)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -37676,12 +30785,28 @@ (INSTANCE ula_\|zx_keyboard_\|WideOr16\~7) (DELAY (ABSOLUTE - (PORT dataa (123:123:123) (155:155:155)) - (PORT datab (516:516:516) (622:622:622)) - (PORT datac (159:159:159) (192:192:192)) - (PORT datad (779:779:779) (929:929:929)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (PORT dataa (551:551:551) (660:660:660)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (170:170:170) (200:200:200)) + (PORT datad (523:523:523) (615:615:615)) + (IOPATH dataa combout (188:188:188) (184:184:184)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr16\~5) + (DELAY + (ABSOLUTE + (PORT dataa (651:651:651) (792:792:792)) + (PORT datab (173:173:173) (234:234:234)) + (PORT datac (533:533:533) (641:641:641)) + (PORT datad (525:525:525) (617:617:617)) + (IOPATH dataa combout (188:188:188) (179:179:179)) + (IOPATH datab combout (196:196:196) (192:192:192)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -37692,27 +30817,43 @@ (INSTANCE ula_\|zx_keyboard_\|WideOr16\~6) (DELAY (ABSOLUTE - (PORT dataa (792:792:792) (954:954:954)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datac (508:508:508) (604:604:604)) - (PORT datad (264:264:264) (302:302:302)) - (IOPATH dataa combout (170:170:170) (163:163:163)) + (PORT dataa (571:571:571) (691:691:691)) + (PORT datab (105:105:105) (134:134:134)) + (PORT datac (531:531:531) (639:639:639)) + (PORT datad (191:191:191) (224:224:224)) + (IOPATH dataa combout (172:172:172) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~46) + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~43) (DELAY (ABSOLUTE - (PORT dataa (192:192:192) (229:229:229)) - (PORT datab (147:147:147) (198:198:198)) - (PORT datad (328:328:328) (379:379:379)) - (IOPATH dataa combout (165:165:165) (159:159:159)) + (PORT dataa (262:262:262) (332:332:332)) + (PORT datab (175:175:175) (231:231:231)) + (PORT datac (253:253:253) (325:325:325)) + (PORT datad (667:667:667) (778:778:778)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~44) + (DELAY + (ABSOLUTE + (PORT dataa (217:217:217) (259:259:259)) + (PORT datab (332:332:332) (395:395:395)) + (PORT datad (590:590:590) (682:682:682)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datab combout (190:190:190) (181:181:181)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -37721,3113 +30862,92 @@ (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (913:913:913) (917:917:917)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (909:909:909) (914:914:914)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (780:780:780) (899:899:899)) - (PORT datab (211:211:211) (266:266:266)) - (PORT datac (770:770:770) (877:877:877)) - (PORT datad (305:305:305) (361:361:361)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (422:422:422) (485:485:485)) - (PORT datab (1903:1903:1903) (2161:2161:2161)) - (PORT datac (89:89:89) (111:111:111)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (929:929:929) (1064:1064:1064)) - (PORT datab (709:709:709) (818:818:818)) - (PORT datac (348:348:348) (407:407:407)) - (PORT datad (638:638:638) (725:725:725)) - (IOPATH dataa combout (158:158:158) (173:173:173)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (865:865:865) (997:997:997)) - (PORT datab (709:709:709) (819:819:819)) - (PORT datac (89:89:89) (110:110:110)) - (PORT datad (721:721:721) (842:842:842)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[1\]) - (DELAY - (ABSOLUTE - (PORT dataa (541:541:541) (643:643:643)) - (PORT datab (346:346:346) (408:408:408)) - (PORT datac (129:129:129) (165:165:165)) - (PORT datad (944:944:944) (1074:1074:1074)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (916:916:916) (903:903:903)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (432:432:432) (460:460:460)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[1\]\~10) - (DELAY - (ABSOLUTE - (PORT datab (500:500:500) (577:577:577)) - (PORT datac (517:517:517) (610:610:610)) - (PORT datad (119:119:119) (142:142:142)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[1\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (136:136:136) (173:173:173)) - (PORT datab (378:378:378) (461:461:461)) - (PORT datac (88:88:88) (110:110:110)) - (PORT datad (110:110:110) (131:131:131)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|ir_\|opcode\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (103:103:103) (120:120:120)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (911:911:911)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (917:917:917) (902:902:902)) - (PORT ena (645:645:645) (697:697:697)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal40\~0) - (DELAY - (ABSOLUTE - (PORT dataa (157:157:157) (214:214:214)) - (PORT datac (501:501:501) (586:586:586)) - (PORT datad (505:505:505) (592:592:592)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal21\~1) - (DELAY - (ABSOLUTE - (PORT dataa (798:798:798) (947:947:947)) - (PORT datab (481:481:481) (557:557:557)) - (PORT datac (501:501:501) (610:610:610)) - (PORT datad (468:468:468) (544:544:544)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~26) - (DELAY - (ABSOLUTE - (PORT dataa (874:874:874) (1034:1034:1034)) - (PORT datab (1302:1302:1302) (1480:1480:1480)) - (PORT datac (364:364:364) (432:432:432)) - (PORT datad (1513:1513:1513) (1746:1746:1746)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~28) - (DELAY - (ABSOLUTE - (PORT dataa (106:106:106) (138:138:138)) - (PORT datab (122:122:122) (157:157:157)) - (PORT datac (101:101:101) (128:128:128)) - (PORT datad (195:195:195) (226:226:226)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~3) - (DELAY - (ABSOLUTE - (PORT dataa (329:329:329) (383:383:383)) - (PORT datab (230:230:230) (273:273:273)) - (PORT datac (290:290:290) (331:331:331)) - (PORT datad (651:651:651) (746:746:746)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~2) - (DELAY - (ABSOLUTE - (PORT dataa (845:845:845) (994:994:994)) - (PORT datab (229:229:229) (277:277:277)) - (PORT datac (519:519:519) (601:601:601)) - (PORT datad (112:112:112) (133:133:133)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~5) - (DELAY - (ABSOLUTE - (PORT dataa (550:550:550) (643:643:643)) - (PORT datab (627:627:627) (714:714:714)) - (PORT datac (714:714:714) (833:833:833)) - (PORT datad (756:756:756) (864:864:864)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~6) - (DELAY - (ABSOLUTE - (PORT dataa (601:601:601) (683:683:683)) - (PORT datab (552:552:552) (654:654:654)) - (PORT datac (716:716:716) (835:835:835)) - (PORT datad (697:697:697) (795:795:795)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~7) - (DELAY - (ABSOLUTE - (PORT dataa (814:814:814) (919:919:919)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (461:461:461) (519:519:519)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~4) - (DELAY - (ABSOLUTE - (PORT dataa (870:870:870) (1001:1001:1001)) - (PORT datab (450:450:450) (525:525:525)) - (PORT datad (557:557:557) (632:632:632)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~8) - (DELAY - (ABSOLUTE - (PORT dataa (861:861:861) (1003:1003:1003)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (348:348:348) (413:413:413)) - (PORT datad (295:295:295) (338:338:338)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~9) - (DELAY - (ABSOLUTE - (PORT dataa (332:332:332) (399:399:399)) - (PORT datab (288:288:288) (333:333:333)) - (PORT datac (102:102:102) (123:123:123)) - (PORT datad (193:193:193) (226:226:226)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1233:1233:1233) (1408:1408:1408)) - (PORT datab (883:883:883) (1032:1032:1032)) - (PORT datac (492:492:492) (577:577:577)) - (PORT datad (622:622:622) (713:713:713)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~12) - (DELAY - (ABSOLUTE - (PORT datab (120:120:120) (155:155:155)) - (PORT datac (176:176:176) (209:209:209)) - (PORT datad (191:191:191) (224:224:224)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~10) - (DELAY - (ABSOLUTE - (PORT dataa (704:704:704) (829:829:829)) - (PORT datab (511:511:511) (600:600:600)) - (PORT datac (1119:1119:1119) (1312:1312:1312)) - (PORT datad (1169:1169:1169) (1381:1381:1381)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~11) - (DELAY - (ABSOLUTE - (PORT dataa (477:477:477) (553:553:553)) - (PORT datab (120:120:120) (155:155:155)) - (PORT datac (104:104:104) (132:132:132)) - (PORT datad (191:191:191) (223:223:223)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~13) - (DELAY - (ABSOLUTE - (PORT dataa (624:624:624) (721:721:721)) - (PORT datab (104:104:104) (132:132:132)) - (PORT datac (91:91:91) (113:113:113)) - (PORT datad (93:93:93) (111:111:111)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~17) - (DELAY - (ABSOLUTE - (PORT dataa (110:110:110) (144:144:144)) - (PORT datab (117:117:117) (151:151:151)) - (PORT datac (105:105:105) (128:128:128)) - (PORT datad (120:120:120) (138:138:138)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~32) - (DELAY - (ABSOLUTE - (PORT dataa (1087:1087:1087) (1273:1273:1273)) - (PORT datab (1458:1458:1458) (1689:1689:1689)) - (PORT datad (811:811:811) (945:945:945)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~15) - (DELAY - (ABSOLUTE - (PORT dataa (364:364:364) (434:434:434)) - (PORT datab (383:383:383) (458:458:458)) - (PORT datac (593:593:593) (676:676:676)) - (PORT datad (358:358:358) (416:416:416)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~16) - (DELAY - (ABSOLUTE - (PORT dataa (107:107:107) (140:140:140)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (325:325:325) (382:382:382)) - (PORT datad (424:424:424) (480:480:480)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~18) - (DELAY - (ABSOLUTE - (PORT dataa (464:464:464) (539:539:539)) - (PORT datab (171:171:171) (208:208:208)) - (PORT datac (191:191:191) (228:228:228)) - (PORT datad (330:330:330) (383:383:383)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1014:1014:1014) (1196:1196:1196)) - (PORT datab (498:498:498) (595:595:595)) - (PORT datac (499:499:499) (608:608:608)) - (PORT datad (227:227:227) (269:269:269)) - (IOPATH dataa combout (159:159:159) (173:173:173)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (505:505:505) (583:583:583)) - (PORT datac (494:494:494) (563:563:563)) - (PORT datad (768:768:768) (891:891:891)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~1) - (DELAY - (ABSOLUTE - (PORT dataa (215:215:215) (257:257:257)) - (PORT datac (101:101:101) (122:122:122)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (165:165:165) (173:173:173)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~2) - (DELAY - (ABSOLUTE - (PORT dataa (655:655:655) (759:759:759)) - (PORT datab (102:102:102) (131:131:131)) - (PORT datac (310:310:310) (366:366:366)) - (PORT datad (190:190:190) (226:226:226)) - (IOPATH dataa combout (188:188:188) (184:184:184)) - (IOPATH datab combout (169:169:169) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~3) - (DELAY - (ABSOLUTE - (PORT dataa (655:655:655) (759:759:759)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datad (480:480:480) (559:559:559)) - (IOPATH dataa combout (172:172:172) (165:165:165)) - (IOPATH datab combout (169:169:169) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2) - (DELAY - (ABSOLUTE - (PORT clk (896:896:896) (902:902:902)) - (PORT d (37:37:37) (50:50:50)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1338:1338:1338) (1530:1530:1530)) - (PORT datab (891:891:891) (1046:1046:1046)) - (PORT datac (1005:1005:1005) (1176:1176:1176)) - (PORT datad (938:938:938) (1076:1076:1076)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~11) - (DELAY - (ABSOLUTE - (PORT dataa (801:801:801) (942:942:942)) - (PORT datab (102:102:102) (131:131:131)) - (PORT datac (585:585:585) (679:679:679)) - (PORT datad (727:727:727) (829:829:829)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~8) - (DELAY - (ABSOLUTE - (PORT dataa (651:651:651) (786:786:786)) - (PORT datac (490:490:490) (579:579:579)) - (PORT datad (531:531:531) (625:625:625)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~9) - (DELAY - (ABSOLUTE - (PORT dataa (495:495:495) (570:570:570)) - (PORT datab (528:528:528) (618:618:618)) - (PORT datac (310:310:310) (355:355:355)) - (PORT datad (282:282:282) (315:315:315)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~12) - (DELAY - (ABSOLUTE - (PORT dataa (105:105:105) (137:137:137)) - (PORT datab (452:452:452) (520:520:520)) - (PORT datac (88:88:88) (109:109:109)) - (PORT datad (100:100:100) (124:124:124)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~14) - (DELAY - (ABSOLUTE - (PORT dataa (660:660:660) (769:769:769)) - (PORT datab (139:139:139) (191:191:191)) - (PORT datac (116:116:116) (157:157:157)) - (PORT datad (318:318:318) (367:367:367)) - (IOPATH dataa combout (188:188:188) (179:179:179)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~20) - (DELAY - (ABSOLUTE - (PORT dataa (303:303:303) (355:355:355)) - (PORT datab (104:104:104) (133:133:133)) - (PORT datac (326:326:326) (377:377:377)) - (PORT datad (318:318:318) (359:359:359)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~10) - (DELAY - (ABSOLUTE - (PORT dataa (887:887:887) (1057:1057:1057)) - (PORT datab (1441:1441:1441) (1668:1668:1668)) - (PORT datac (584:584:584) (667:667:667)) - (PORT datad (486:486:486) (557:557:557)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~8) - (DELAY - (ABSOLUTE - (PORT dataa (598:598:598) (690:690:690)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datac (662:662:662) (752:752:752)) - (PORT datad (292:292:292) (331:331:331)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~5) - (DELAY - (ABSOLUTE - (PORT dataa (474:474:474) (552:552:552)) - (PORT datab (115:115:115) (144:144:144)) - (PORT datac (128:128:128) (154:154:154)) - (PORT datad (319:319:319) (372:372:372)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~6) - (DELAY - (ABSOLUTE - (PORT dataa (522:522:522) (620:620:620)) - (PORT datab (143:143:143) (176:176:176)) - (PORT datac (778:778:778) (901:901:901)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~7) - (DELAY - (ABSOLUTE - (PORT dataa (506:506:506) (585:585:585)) - (PORT datab (613:613:613) (718:718:718)) - (PORT datac (497:497:497) (574:574:574)) - (PORT datad (550:550:550) (616:616:616)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_set\~0) - (DELAY - (ABSOLUTE - (PORT dataa (250:250:250) (297:297:297)) - (PORT datab (484:484:484) (559:559:559)) - (PORT datac (499:499:499) (608:608:608)) - (PORT datad (218:218:218) (252:252:252)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~4) - (DELAY - (ABSOLUTE - (PORT datab (582:582:582) (662:662:662)) - (PORT datac (110:110:110) (135:135:135)) - (PORT datad (110:110:110) (130:130:130)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~9) - (DELAY - (ABSOLUTE - (PORT dataa (105:105:105) (137:137:137)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (279:279:279) (322:322:322)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|flags_cf) - (DELAY - (ABSOLUTE - (PORT dataa (102:102:102) (133:133:133)) - (PORT datab (309:309:309) (361:361:361)) - (PORT datac (90:90:90) (112:112:112)) - (PORT datad (299:299:299) (346:346:346)) - (IOPATH dataa combout (188:188:188) (203:203:203)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[0\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (380:380:380) (448:448:448)) - (PORT datab (362:362:362) (431:431:431)) - (PORT datac (481:481:481) (550:550:550)) - (PORT datad (477:477:477) (548:548:548)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sw2_\|db_up\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT datac (629:629:629) (724:724:724)) - (PORT datad (336:336:336) (387:387:387)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[0\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (193:193:193) (230:230:230)) - (PORT datab (344:344:344) (402:402:402)) - (PORT datac (476:476:476) (549:549:549)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (165:165:165) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[0\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (371:371:371) (436:436:436)) - (PORT datab (513:513:513) (599:599:599)) - (PORT datac (91:91:91) (113:113:113)) - (PORT datad (113:113:113) (137:137:137)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~67) - (DELAY - (ABSOLUTE - (PORT dataa (374:374:374) (460:460:460)) - (PORT datac (596:596:596) (699:699:699)) - (PORT datad (408:408:408) (499:499:499)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~81) - (DELAY - (ABSOLUTE - (PORT dataa (414:414:414) (524:524:524)) - (PORT datab (394:394:394) (484:484:484)) - (PORT datac (598:598:598) (701:701:701)) - (PORT datad (385:385:385) (471:471:471)) - (IOPATH dataa combout (186:186:186) (175:175:175)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~82) - (DELAY - (ABSOLUTE - (PORT dataa (105:105:105) (137:137:137)) - (PORT datab (493:493:493) (588:588:588)) - (PORT datac (597:597:597) (700:700:700)) - (PORT datad (172:172:172) (200:200:200)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (176:176:176)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~83) - (DELAY - (ABSOLUTE - (PORT dataa (112:112:112) (148:148:148)) - (PORT datab (103:103:103) (132:132:132)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (196:196:196) (192:192:192)) - (IOPATH datac combout (190:190:190) (195:195:195)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (914:914:914) (918:918:918)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (909:909:909) (914:914:914)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~84) - (DELAY - (ABSOLUTE - (PORT dataa (401:401:401) (482:482:482)) - (PORT datab (535:535:535) (638:638:638)) - (PORT datac (408:408:408) (506:506:506)) - (PORT datad (413:413:413) (505:505:505)) - (IOPATH dataa combout (188:188:188) (179:179:179)) - (IOPATH datab combout (188:188:188) (177:177:177)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~85) - (DELAY - (ABSOLUTE - (PORT dataa (445:445:445) (545:545:545)) - (PORT datab (410:410:410) (500:500:500)) - (PORT datac (400:400:400) (487:487:487)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~86) - (DELAY - (ABSOLUTE - (PORT dataa (181:181:181) (224:224:224)) - (PORT datab (103:103:103) (132:132:132)) - (PORT datad (171:171:171) (202:202:202)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH datab combout (190:190:190) (181:181:181)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (911:911:911) (916:916:916)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~49) - (DELAY - (ABSOLUTE - (PORT dataa (629:629:629) (742:742:742)) - (PORT datab (392:392:392) (480:480:480)) - (PORT datac (116:116:116) (156:156:156)) - (PORT datad (290:290:290) (338:338:338)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (504:504:504) (614:614:614)) - (PORT datab (430:430:430) (528:528:528)) - (PORT datac (758:758:758) (914:914:914)) - (PORT datad (644:644:644) (761:761:761)) - (IOPATH dataa combout (159:159:159) (173:173:173)) - (IOPATH datab combout (161:161:161) (176:176:176)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\~76) - (DELAY - (ABSOLUTE - (PORT dataa (177:177:177) (219:219:219)) - (PORT datab (153:153:153) (201:201:201)) - (PORT datac (517:517:517) (597:597:597)) - (PORT datad (839:839:839) (979:979:979)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~73) - (DELAY - (ABSOLUTE - (PORT datac (406:406:406) (503:503:503)) - (PORT datad (647:647:647) (765:765:765)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~47) - (DELAY - (ABSOLUTE - (PORT dataa (410:410:410) (519:519:519)) - (PORT datab (397:397:397) (487:487:487)) - (PORT datac (477:477:477) (565:565:565)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (406:406:406) (499:499:499)) - (PORT datab (846:846:846) (997:997:997)) - (PORT datac (491:491:491) (594:594:594)) - (PORT datad (459:459:459) (543:543:543)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\~74) - (DELAY - (ABSOLUTE - (PORT dataa (308:308:308) (361:361:361)) - (PORT datab (174:174:174) (210:210:210)) - (PORT datac (756:756:756) (911:911:911)) - (PORT datad (864:864:864) (1017:1017:1017)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~75) - (DELAY - (ABSOLUTE - (PORT dataa (105:105:105) (136:136:136)) - (PORT datab (105:105:105) (135:135:135)) - (PORT datac (234:234:234) (293:293:293)) - (PORT datad (448:448:448) (518:518:518)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~77) - (DELAY - (ABSOLUTE - (PORT dataa (287:287:287) (330:330:330)) - (PORT datab (171:171:171) (209:209:209)) - (PORT datad (404:404:404) (493:493:493)) - (IOPATH dataa combout (159:159:159) (173:173:173)) - (IOPATH datab combout (169:169:169) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (914:914:914) (918:918:918)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (909:909:909) (914:914:914)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]\~71) - (DELAY - (ABSOLUTE - (PORT dataa (421:421:421) (513:513:513)) - (PORT datab (404:404:404) (495:495:495)) - (PORT datac (173:173:173) (207:207:207)) - (PORT datad (610:610:610) (712:712:712)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]\~72) - (DELAY - (ABSOLUTE - (PORT datab (103:103:103) (132:132:132)) - (PORT datad (403:403:403) (484:484:484)) - (IOPATH datab combout (191:191:191) (181:181:181)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (910:910:910) (916:916:916)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~47) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (257:257:257)) - (PORT datab (639:639:639) (748:748:748)) - (PORT datac (350:350:350) (419:419:419)) - (PORT datad (337:337:337) (404:404:404)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[0\]\~80) - (DELAY - (ABSOLUTE - (PORT dataa (873:873:873) (1025:1025:1025)) - (PORT datab (520:520:520) (619:619:619)) - (PORT datad (267:267:267) (305:305:305)) - (IOPATH dataa combout (159:159:159) (165:165:165)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (914:914:914) (918:918:918)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (909:909:909) (914:914:914)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]\~78) - (DELAY - (ABSOLUTE - (PORT dataa (255:255:255) (330:330:330)) - (PORT datac (321:321:321) (387:387:387)) - (PORT datad (142:142:142) (184:184:184)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]\~79) - (DELAY - (ABSOLUTE - (PORT dataa (207:207:207) (243:243:243)) - (PORT datab (443:443:443) (515:515:515)) - (PORT datad (401:401:401) (491:491:491)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH datab combout (190:190:190) (181:181:181)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (914:914:914) (918:918:918)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (909:909:909) (914:914:914)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|key_row\~1) - (DELAY - (ABSOLUTE - (PORT datab (845:845:845) (994:994:994)) - (PORT datac (181:181:181) (230:230:230)) - (PORT datad (489:489:489) (577:577:577)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~48) - (DELAY - (ABSOLUTE - (PORT dataa (106:106:106) (138:138:138)) - (PORT datab (117:117:117) (146:146:146)) - (PORT datac (117:117:117) (158:158:158)) - (PORT datad (89:89:89) (107:107:107)) - (IOPATH dataa combout (165:165:165) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|shifted\~1) - (DELAY - (ABSOLUTE - (PORT datac (598:598:598) (727:727:727)) - (PORT datad (577:577:577) (691:691:691)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~90) - (DELAY - (ABSOLUTE - (PORT dataa (788:788:788) (949:949:949)) - (PORT datab (437:437:437) (539:539:539)) - (PORT datac (518:518:518) (616:616:616)) - (PORT datad (420:420:420) (525:525:525)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~91) - (DELAY - (ABSOLUTE - (PORT dataa (110:110:110) (142:142:142)) - (PORT datab (359:359:359) (429:429:429)) - (PORT datac (321:321:321) (376:376:376)) - (PORT datad (487:487:487) (584:584:584)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~92) - (DELAY - (ABSOLUTE - (PORT datab (525:525:525) (630:630:630)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (914:914:914) (918:918:918)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (910:910:910) (915:915:915)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~63) - (DELAY - (ABSOLUTE - (PORT datac (341:341:341) (415:415:415)) - (PORT datad (342:342:342) (406:406:406)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr16\~3) - (DELAY - (ABSOLUTE - (PORT datab (346:346:346) (418:418:418)) - (PORT datac (361:361:361) (461:461:461)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~87) - (DELAY - (ABSOLUTE - (PORT dataa (110:110:110) (144:144:144)) - (PORT datab (249:249:249) (312:312:312)) - (PORT datac (343:343:343) (412:412:412)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~132) - (DELAY - (ABSOLUTE - (PORT dataa (120:120:120) (153:153:153)) - (PORT datab (354:354:354) (429:429:429)) - (PORT datad (348:348:348) (423:423:423)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~88) - (DELAY - (ABSOLUTE - (PORT dataa (455:455:455) (541:541:541)) - (PORT datab (117:117:117) (146:146:146)) - (PORT datac (171:171:171) (205:205:205)) - (PORT datad (280:280:280) (323:323:323)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~89) - (DELAY - (ABSOLUTE - (PORT dataa (430:430:430) (494:494:494)) - (PORT datad (503:503:503) (597:597:597)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (914:914:914) (918:918:918)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (909:909:909) (914:914:914)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~50) - (DELAY - (ABSOLUTE - (PORT dataa (780:780:780) (900:900:900)) - (PORT datab (311:311:311) (377:377:377)) - (PORT datac (770:770:770) (877:877:877)) - (PORT datad (119:119:119) (156:156:156)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~51) - (DELAY - (ABSOLUTE - (PORT dataa (423:423:423) (488:488:488)) - (PORT datab (1905:1905:1905) (2163:2163:2163)) - (PORT datac (89:89:89) (110:110:110)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (489:489:489) (554:554:554)) - (PORT clk (1098:1098:1098) (1115:1115:1115)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (692:692:692) (785:785:785)) - (PORT d[1] (555:555:555) (645:645:645)) - (PORT d[2] (539:539:539) (612:612:612)) - (PORT d[3] (570:570:570) (664:664:664)) - (PORT d[4] (1524:1524:1524) (1787:1787:1787)) - (PORT d[5] (567:567:567) (665:665:665)) - (PORT d[6] (566:566:566) (652:652:652)) - (PORT d[7] (538:538:538) (620:620:620)) - (PORT d[8] (582:582:582) (677:677:677)) - (PORT d[9] (556:556:556) (651:651:651)) - (PORT d[10] (600:600:600) (694:694:694)) - (PORT d[11] (1498:1498:1498) (1745:1745:1745)) - (PORT d[12] (743:743:743) (860:860:860)) - (PORT clk (1096:1096:1096) (1113:1113:1113)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (519:519:519) (547:547:547)) - (PORT clk (1096:1096:1096) (1113:1113:1113)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1098:1098:1098) (1115:1115:1115)) - (PORT d[0] (809:809:809) (845:845:845)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1099:1099:1099) (1116:1116:1116)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1099:1099:1099) (1116:1116:1116)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1099:1099:1099) (1116:1116:1116)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1099:1099:1099) (1116:1116:1116)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1078:1078:1078) (1094:1094:1094)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (618:618:618) (626:626:626)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (619:619:619) (627:627:627)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (619:619:619) (627:627:627)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (619:619:619) (627:627:627)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (528:528:528) (606:606:606)) - (PORT clk (1097:1097:1097) (1114:1114:1114)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (388:388:388) (446:446:446)) - (PORT d[1] (1400:1400:1400) (1651:1651:1651)) - (PORT d[2] (850:850:850) (968:968:968)) - (PORT d[3] (558:558:558) (641:641:641)) - (PORT d[4] (1510:1510:1510) (1771:1771:1771)) - (PORT d[5] (2023:2023:2023) (2340:2340:2340)) - (PORT d[6] (729:729:729) (838:838:838)) - (PORT d[7] (1869:1869:1869) (2113:2113:2113)) - (PORT d[8] (377:377:377) (441:441:441)) - (PORT d[9] (912:912:912) (1053:1053:1053)) - (PORT d[10] (777:777:777) (894:894:894)) - (PORT d[11] (1301:1301:1301) (1515:1515:1515)) - (PORT d[12] (893:893:893) (1028:1028:1028)) - (PORT clk (1095:1095:1095) (1112:1112:1112)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (355:355:355) (356:356:356)) - (PORT clk (1095:1095:1095) (1112:1112:1112)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1114:1114:1114)) - (PORT d[0] (800:800:800) (826:826:826)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1098:1098:1098) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1098:1098:1098) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1098:1098:1098) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1098:1098:1098) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1077:1077:1077) (1093:1093:1093)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (617:617:617) (625:625:625)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (618:618:618) (626:626:626)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (618:618:618) (626:626:626)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (618:618:618) (626:626:626)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (593:593:593) (668:668:668)) - (PORT clk (1097:1097:1097) (1114:1114:1114)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (539:539:539) (619:619:619)) - (PORT d[1] (2026:2026:2026) (2346:2346:2346)) - (PORT d[2] (705:705:705) (808:808:808)) - (PORT d[3] (715:715:715) (826:826:826)) - (PORT d[4] (1504:1504:1504) (1764:1764:1764)) - (PORT d[5] (2029:2029:2029) (2352:2352:2352)) - (PORT d[6] (754:754:754) (872:872:872)) - (PORT d[7] (692:692:692) (792:792:792)) - (PORT d[8] (552:552:552) (638:638:638)) - (PORT d[9] (891:891:891) (1024:1024:1024)) - (PORT d[10] (788:788:788) (909:909:909)) - (PORT d[11] (1310:1310:1310) (1527:1527:1527)) - (PORT d[12] (919:919:919) (1062:1062:1062)) - (PORT clk (1095:1095:1095) (1112:1112:1112)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (518:518:518) (544:544:544)) - (PORT clk (1095:1095:1095) (1112:1112:1112)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1114:1114:1114)) - (PORT d[0] (912:912:912) (949:949:949)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1098:1098:1098) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1098:1098:1098) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1098:1098:1098) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1098:1098:1098) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1077:1077:1077) (1093:1093:1093)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (617:617:617) (625:625:625)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (618:618:618) (626:626:626)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (618:618:618) (626:626:626)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (618:618:618) (626:626:626)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~55) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (246:246:246)) - (PORT datab (355:355:355) (426:426:426)) - (PORT datac (352:352:352) (416:416:416)) - (PORT datad (349:349:349) (402:402:402)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (188:188:188) (177:177:177)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (652:652:652) (746:746:746)) - (PORT clk (1091:1091:1091) (1108:1108:1108)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2062:2062:2062) (2392:2392:2392)) - (PORT d[1] (795:795:795) (938:938:938)) - (PORT d[2] (1144:1144:1144) (1312:1312:1312)) - (PORT d[3] (1386:1386:1386) (1609:1609:1609)) - (PORT d[4] (1274:1274:1274) (1480:1480:1480)) - (PORT d[5] (775:775:775) (917:917:917)) - (PORT d[6] (824:824:824) (954:954:954)) - (PORT d[7] (1952:1952:1952) (2204:2204:2204)) - (PORT d[8] (2104:2104:2104) (2435:2435:2435)) - (PORT d[9] (1815:1815:1815) (2090:2090:2090)) - (PORT d[10] (1826:1826:1826) (2094:2094:2094)) - (PORT d[11] (1007:1007:1007) (1167:1167:1167)) - (PORT d[12] (814:814:814) (935:935:935)) - (PORT clk (1089:1089:1089) (1106:1106:1106)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (890:890:890) (960:960:960)) - (PORT clk (1089:1089:1089) (1106:1106:1106)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1091:1091:1091) (1108:1108:1108)) - (PORT d[0] (1554:1554:1554) (1684:1684:1684)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1092:1092:1092) (1109:1109:1109)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1092:1092:1092) (1109:1109:1109)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1092:1092:1092) (1109:1109:1109)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1092:1092:1092) (1109:1109:1109)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1071:1071:1071) (1087:1087:1087)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (611:611:611) (619:619:619)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (612:612:612) (620:620:620)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (612:612:612) (620:620:620)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (612:612:612) (620:620:620)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~56) - (DELAY - (ABSOLUTE - (PORT dataa (571:571:571) (652:652:652)) - (PORT datab (785:785:785) (918:918:918)) - (PORT datac (276:276:276) (323:323:323)) - (PORT datad (654:654:654) (746:746:746)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (166:166:166) (176:176:176)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (914:914:914) (1070:1070:1070)) - (PORT clk (1096:1096:1096) (1114:1114:1114)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1612:1612:1612) (1843:1843:1843)) - (PORT d[1] (1155:1155:1155) (1367:1367:1367)) - (PORT d[2] (1117:1117:1117) (1292:1292:1292)) - (PORT d[3] (1070:1070:1070) (1255:1255:1255)) - (PORT d[4] (1763:1763:1763) (2023:2023:2023)) - (PORT d[5] (1312:1312:1312) (1534:1534:1534)) - (PORT d[6] (982:982:982) (1126:1126:1126)) - (PORT d[7] (1219:1219:1219) (1414:1414:1414)) - (PORT d[8] (1382:1382:1382) (1622:1622:1622)) - (PORT d[9] (965:965:965) (1112:1112:1112)) - (PORT d[10] (820:820:820) (943:943:943)) - (PORT d[11] (960:960:960) (1098:1098:1098)) - (PORT d[12] (1308:1308:1308) (1499:1499:1499)) - (PORT clk (1094:1094:1094) (1112:1112:1112)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1425:1425:1425) (1591:1591:1591)) - (PORT clk (1094:1094:1094) (1112:1112:1112)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1096:1096:1096) (1114:1114:1114)) - (PORT d[0] (2282:2282:2282) (2098:2098:2098)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1051:1051:1051) (1071:1071:1071)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1117:1117:1117) (1240:1240:1240)) - (PORT clk (1056:1056:1056) (1074:1074:1074)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2452:2452:2452) (2784:2784:2784)) - (PORT d[1] (2314:2314:2314) (2623:2623:2623)) - (PORT d[2] (2389:2389:2389) (2699:2699:2699)) - (PORT d[3] (2550:2550:2550) (2907:2907:2907)) - (PORT d[4] (2364:2364:2364) (2679:2679:2679)) - (PORT d[5] (2568:2568:2568) (2916:2916:2916)) - (PORT d[6] (2462:2462:2462) (2816:2816:2816)) - (PORT d[7] (2364:2364:2364) (2657:2657:2657)) - (PORT d[8] (2551:2551:2551) (2900:2900:2900)) - (PORT d[9] (2545:2545:2545) (2918:2918:2918)) - (PORT d[10] (2631:2631:2631) (2982:2982:2982)) - (PORT d[11] (2413:2413:2413) (2724:2724:2724)) - (PORT d[12] (2561:2561:2561) (2915:2915:2915)) - (PORT clk (1053:1053:1053) (1073:1073:1073)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1056:1056:1056) (1074:1074:1074)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1057:1057:1057) (1075:1075:1075)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1057:1057:1057) (1075:1075:1075)) - (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1057:1057:1057) (1075:1075:1075)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1057:1057:1057) (1075:1075:1075)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1052:1052:1052) (1072:1072:1072)) - (IOPATH (posedge clk) q (164:164:164) (166:166:166)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1588:1588:1588) (1816:1816:1816)) - (PORT d[1] (992:992:992) (1179:1179:1179)) - (PORT d[2] (1103:1103:1103) (1283:1283:1283)) - (PORT d[3] (1062:1062:1062) (1246:1246:1246)) - (PORT d[4] (1617:1617:1617) (1864:1864:1864)) - (PORT d[5] (1317:1317:1317) (1540:1540:1540)) - (PORT d[6] (1154:1154:1154) (1319:1319:1319)) - (PORT d[7] (1225:1225:1225) (1427:1427:1427)) - (PORT d[8] (1375:1375:1375) (1606:1606:1606)) - (PORT d[9] (1130:1130:1130) (1297:1297:1297)) - (PORT d[10] (1111:1111:1111) (1274:1274:1274)) - (PORT d[11] (1134:1134:1134) (1293:1293:1293)) - (PORT d[12] (1458:1458:1458) (1670:1670:1670)) - (PORT clk (1097:1097:1097) (1115:1115:1115)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1115:1115:1115)) - (PORT d[0] (1576:1576:1576) (1776:1776:1776)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1098:1098:1098) (1116:1116:1116)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1079:1079:1079) (1096:1096:1096)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (619:619:619) (628:628:628)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (620:620:620) (629:629:629)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (620:620:620) (629:629:629)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (620:620:620) (629:629:629)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (906:906:906) (1058:1058:1058)) - (PORT clk (1094:1094:1094) (1112:1112:1112)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1607:1607:1607) (1841:1841:1841)) - (PORT d[1] (1178:1178:1178) (1395:1395:1395)) - (PORT d[2] (1073:1073:1073) (1246:1246:1246)) - (PORT d[3] (1061:1061:1061) (1246:1246:1246)) - (PORT d[4] (1778:1778:1778) (2032:2032:2032)) - (PORT d[5] (1152:1152:1152) (1354:1354:1354)) - (PORT d[6] (984:984:984) (1132:1132:1132)) - (PORT d[7] (1029:1029:1029) (1190:1190:1190)) - (PORT d[8] (1394:1394:1394) (1627:1627:1627)) - (PORT d[9] (1130:1130:1130) (1298:1298:1298)) - (PORT d[10] (1118:1118:1118) (1290:1290:1290)) - (PORT d[11] (1424:1424:1424) (1619:1619:1619)) - (PORT d[12] (1271:1271:1271) (1457:1457:1457)) - (PORT clk (1092:1092:1092) (1110:1110:1110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1419:1419:1419) (1556:1556:1556)) - (PORT clk (1092:1092:1092) (1110:1110:1110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1094:1094:1094) (1112:1112:1112)) - (PORT d[0] (2096:2096:2096) (2313:2313:2313)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1095:1095:1095) (1113:1113:1113)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1095:1095:1095) (1113:1113:1113)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1095:1095:1095) (1113:1113:1113)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1095:1095:1095) (1113:1113:1113)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1049:1049:1049) (1069:1069:1069)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1117:1117:1117) (1241:1241:1241)) - (PORT clk (1054:1054:1054) (1072:1072:1072)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2473:2473:2473) (2812:2812:2812)) - (PORT d[1] (2361:2361:2361) (2677:2677:2677)) - (PORT d[2] (2402:2402:2402) (2727:2727:2727)) - (PORT d[3] (2543:2543:2543) (2900:2900:2900)) - (PORT d[4] (2378:2378:2378) (2698:2698:2698)) - (PORT d[5] (2560:2560:2560) (2905:2905:2905)) - (PORT d[6] (2623:2623:2623) (2996:2996:2996)) - (PORT d[7] (2364:2364:2364) (2664:2664:2664)) - (PORT d[8] (2457:2457:2457) (2789:2789:2789)) - (PORT d[9] (2540:2540:2540) (2926:2926:2926)) - (PORT d[10] (2593:2593:2593) (2922:2922:2922)) - (PORT d[11] (2412:2412:2412) (2719:2719:2719)) - (PORT d[12] (2561:2561:2561) (2914:2914:2914)) - (PORT clk (1051:1051:1051) (1071:1071:1071)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1054:1054:1054) (1072:1072:1072)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1055:1055:1055) (1073:1073:1073)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1055:1055:1055) (1073:1073:1073)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1055:1055:1055) (1073:1073:1073)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1055:1055:1055) (1073:1073:1073)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~52) - (DELAY - (ABSOLUTE - (PORT dataa (667:667:667) (789:789:789)) - (PORT datab (803:803:803) (920:920:920)) - (PORT datac (624:624:624) (734:734:734)) - (PORT datad (798:798:798) (908:908:908)) - (IOPATH dataa combout (188:188:188) (203:203:203)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2050:2050:2050) (2378:2378:2378)) - (PORT d[1] (1539:1539:1539) (1803:1803:1803)) - (PORT d[2] (930:930:930) (1089:1089:1089)) - (PORT d[3] (1196:1196:1196) (1398:1398:1398)) - (PORT d[4] (1249:1249:1249) (1444:1444:1444)) - (PORT d[5] (957:957:957) (1133:1133:1133)) - (PORT d[6] (636:636:636) (734:734:734)) - (PORT d[7] (650:650:650) (750:750:750)) - (PORT d[8] (1254:1254:1254) (1478:1478:1478)) - (PORT d[9] (1328:1328:1328) (1519:1519:1519)) - (PORT d[10] (1463:1463:1463) (1678:1678:1678)) - (PORT d[11] (502:502:502) (579:579:579)) - (PORT d[12] (986:986:986) (1140:1140:1140)) - (PORT clk (1088:1088:1088) (1105:1105:1105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1088:1088:1088) (1105:1105:1105)) - (PORT d[0] (2202:2202:2202) (1954:1954:1954)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1089:1089:1089) (1106:1106:1106)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1070:1070:1070) (1086:1086:1086)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (610:610:610) (618:618:618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (611:611:611) (619:619:619)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (611:611:611) (619:619:619)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (611:611:611) (619:619:619)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~53) - (DELAY - (ABSOLUTE - (PORT dataa (668:668:668) (763:763:763)) - (PORT datab (588:588:588) (669:669:669)) - (PORT datac (96:96:96) (121:121:121)) - (PORT datad (788:788:788) (884:884:884)) - (IOPATH dataa combout (188:188:188) (203:203:203)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~54) - (DELAY - (ABSOLUTE - (PORT dataa (836:836:836) (986:986:986)) - (PORT datab (506:506:506) (601:601:601)) - (PORT datac (95:95:95) (119:119:119)) - (PORT datad (91:91:91) (108:108:108)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (188:188:188) (177:177:177)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~106) - (DELAY - (ABSOLUTE - (PORT dataa (378:378:378) (465:465:465)) - (PORT datab (646:646:646) (769:769:769)) - (PORT datac (90:90:90) (112:112:112)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (181:181:181) (175:175:175)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~57) - (DELAY - (ABSOLUTE - (PORT dataa (1112:1112:1112) (1282:1282:1282)) - (PORT datab (639:639:639) (743:743:743)) - (PORT datac (94:94:94) (118:118:118)) - (PORT datad (454:454:454) (532:532:532)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~58) - (DELAY - (ABSOLUTE - (PORT dataa (1114:1114:1114) (1284:1284:1284)) - (PORT datab (341:341:341) (410:410:410)) - (PORT datac (90:90:90) (111:111:111)) - (PORT datad (884:884:884) (1007:1007:1007)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[0\]) - (DELAY - (ABSOLUTE - (PORT dataa (545:545:545) (648:648:648)) - (PORT datab (512:512:512) (593:593:593)) - (PORT datac (135:135:135) (172:172:172)) - (PORT datad (877:877:877) (993:993:993)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (916:916:916) (903:903:903)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (432:432:432) (460:460:460)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[0\]\~16) - (DELAY - (ABSOLUTE - (PORT datab (206:206:206) (246:246:246)) - (PORT datac (211:211:211) (262:262:262)) - (PORT datad (359:359:359) (422:422:422)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[0\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (539:539:539) (622:622:622)) - (PORT datab (735:735:735) (841:841:841)) - (PORT datac (505:505:505) (580:580:580)) - (PORT datad (489:489:489) (557:557:557)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[0\]) (DELAY (ABSOLUTE (PORT clk (904:904:904) (909:909:909)) - (PORT asdata (833:833:833) (925:925:925)) - (PORT clrn (915:915:915) (899:899:899)) - (PORT ena (784:784:784) (855:855:855)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (897:897:897) (901:901:901)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) ) (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[15\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (796:796:796) (913:913:913)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datad (102:102:102) (120:120:120)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (912:912:912) (899:899:899)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (374:374:374) (424:424:424)) + (PORT sload (1093:1093:1093) (1226:1226:1226)) + (PORT ena (1226:1226:1226) (1349:1349:1349)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) (HOLD asdata (posedge clk) (84:84:84)) (HOLD ena (posedge clk) (84:84:84)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal63\~0) + (INSTANCE z80_\|address_pins_\|abus\[15\]\~22) (DELAY (ABSOLUTE - (PORT dataa (1134:1134:1134) (1318:1318:1318)) - (PORT datab (852:852:852) (1008:1008:1008)) - (PORT datac (123:123:123) (152:152:152)) - (PORT datad (617:617:617) (712:712:712)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT datac (1529:1529:1529) (1796:1796:1796)) + (PORT datad (794:794:794) (925:925:925)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_daa) + (INSTANCE D\[1\]\~29) (DELAY (ABSOLUTE - (PORT dataa (849:849:849) (998:998:998)) - (PORT datab (837:837:837) (983:983:983)) - (PORT datac (1033:1033:1033) (1196:1196:1196)) - (PORT datad (211:211:211) (250:250:250)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|SYNTHESIZED_WIRE_2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (204:204:204) (282:282:282)) - (PORT datab (380:380:380) (452:452:452)) - (PORT datac (820:820:820) (948:948:948)) - (PORT datad (730:730:730) (867:867:867)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (376:376:376) (443:443:443)) - (PORT datac (629:629:629) (724:724:724)) - (PORT datad (495:495:495) (576:576:576)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (102:102:102) (133:133:133)) - (PORT datab (366:366:366) (433:433:433)) - (PORT datac (477:477:477) (551:551:551)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[4\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (274:274:274) (322:322:322)) - (PORT datab (495:495:495) (569:569:569)) - (PORT datac (306:306:306) (352:352:352)) - (PORT datad (626:626:626) (722:722:722)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[4\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (350:350:350) (406:406:406)) - (PORT datab (513:513:513) (599:599:599)) - (PORT datac (353:353:353) (420:420:420)) - (PORT datad (90:90:90) (107:107:107)) + (PORT dataa (785:785:785) (958:958:958)) + (PORT datab (473:473:473) (559:559:559)) + (PORT datac (353:353:353) (426:426:426)) + (PORT datad (325:325:325) (377:377:377)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (584:584:584) (689:689:689)) + (PORT datab (184:184:184) (220:220:220)) + (PORT datac (1674:1674:1674) (1965:1965:1965)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -40835,30 +30955,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[4\]\~32) + (INSTANCE ExtRamWE\~0) (DELAY (ABSOLUTE - (PORT dataa (494:494:494) (571:571:571)) - (PORT datab (132:132:132) (167:167:167)) - (PORT datac (344:344:344) (405:405:405)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~119) - (DELAY - (ABSOLUTE - (PORT dataa (423:423:423) (518:518:518)) - (PORT datab (404:404:404) (495:495:495)) - (PORT datac (636:636:636) (744:744:744)) - (PORT datad (495:495:495) (588:588:588)) - (IOPATH dataa combout (186:186:186) (175:175:175)) + (PORT dataa (133:133:133) (171:171:171)) + (PORT datab (1549:1549:1549) (1822:1822:1822)) + (PORT datac (286:286:286) (330:330:330)) + (PORT datad (312:312:312) (368:368:368)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (166:166:166) (158:158:158)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -40867,536 +30971,546 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~120) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode236w\[2\]) (DELAY (ABSOLUTE - (PORT dataa (365:365:365) (432:432:432)) - (PORT datab (175:175:175) (210:210:210)) - (PORT datac (403:403:403) (491:491:491)) - (PORT datad (406:406:406) (506:506:506)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~95) - (DELAY - (ABSOLUTE - (PORT dataa (445:445:445) (545:545:545)) - (PORT datac (395:395:395) (479:479:479)) - (PORT datad (640:640:640) (745:745:745)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~121) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (136:136:136)) - (PORT datad (94:94:94) (114:114:114)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (910:910:910) (916:916:916)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~117) - (DELAY - (ABSOLUTE - (PORT dataa (235:235:235) (305:305:305)) - (PORT datab (349:349:349) (423:423:423)) - (PORT datad (400:400:400) (477:477:477)) - (IOPATH dataa combout (186:186:186) (180:180:180)) + (PORT dataa (641:641:641) (744:744:744)) + (PORT datab (131:131:131) (168:168:168)) + (PORT datac (293:293:293) (344:344:344)) + (PORT datad (881:881:881) (998:998:998)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~136) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|rden_decode\|w_anode284w\[2\]\~0) (DELAY (ABSOLUTE - (PORT dataa (288:288:288) (338:338:338)) - (PORT datab (237:237:237) (296:296:296)) - (PORT datad (346:346:346) (420:420:420)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~130) - (DELAY - (ABSOLUTE - (PORT dataa (366:366:366) (450:450:450)) - (PORT datab (358:358:358) (422:422:422)) - (PORT datad (440:440:440) (514:514:514)) - (IOPATH dataa combout (165:165:165) (159:159:159)) + (PORT datab (920:920:920) (1093:1093:1093)) + (PORT datac (1425:1425:1425) (1684:1684:1684)) + (PORT datad (1242:1242:1242) (1459:1459:1459)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~118) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[1\]\~1) (DELAY (ABSOLUTE - (PORT dataa (448:448:448) (548:548:548)) - (PORT datab (340:340:340) (399:399:399)) - (PORT datad (335:335:335) (383:383:383)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (190:190:190) (195:195:195)) + (PORT dataa (705:705:705) (810:810:810)) + (PORT datab (176:176:176) (213:213:213)) + (PORT datad (103:103:103) (120:120:120)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[1\]) (DELAY (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) + (PORT clk (919:919:919) (904:904:904)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (910:910:910) (916:916:916)) + (PORT asdata (504:504:504) (569:569:569)) + (PORT sload (985:985:985) (1102:1102:1102)) + (PORT ena (911:911:911) (988:988:988)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) ) (TIMINGCHECK (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~78) + (INSTANCE z80_\|address_pins_\|abus\[1\]\~25) (DELAY (ABSOLUTE - (PORT dataa (469:469:469) (542:542:542)) - (PORT datab (466:466:466) (538:538:538)) - (PORT datac (329:329:329) (399:399:399)) - (PORT datad (347:347:347) (419:419:419)) - (IOPATH dataa combout (165:165:165) (163:163:163)) + (PORT datab (310:310:310) (374:374:374)) + (PORT datac (1108:1108:1108) (1291:1291:1291)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~126) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[2\]\~2) (DELAY (ABSOLUTE - (PORT dataa (446:446:446) (557:557:557)) - (PORT datab (380:380:380) (445:445:445)) - (PORT datac (517:517:517) (616:616:616)) - (PORT datad (775:775:775) (924:924:924)) - (IOPATH dataa combout (158:158:158) (157:157:157)) + (PORT dataa (706:706:706) (811:811:811)) + (PORT datab (194:194:194) (235:235:235)) + (PORT datad (160:160:160) (187:187:187)) + (IOPATH dataa combout (172:172:172) (165:165:165)) (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (919:919:919) (904:904:904)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (310:310:310) (351:351:351)) + (PORT sload (985:985:985) (1102:1102:1102)) + (PORT ena (911:911:911) (988:988:988)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[2\]\~26) + (DELAY + (ABSOLUTE + (PORT datac (1107:1107:1107) (1290:1290:1290)) + (PORT datad (129:129:129) (166:166:166)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~128) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[3\]\~3) (DELAY (ABSOLUTE - (PORT dataa (529:529:529) (634:634:634)) - (PORT datab (435:435:435) (537:537:537)) - (PORT datac (493:493:493) (594:594:594)) - (PORT datad (427:427:427) (533:533:533)) + (PORT dataa (384:384:384) (444:444:444)) + (PORT datab (192:192:192) (232:232:232)) + (PORT datad (684:684:684) (784:784:784)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~129) - (DELAY - (ABSOLUTE - (PORT dataa (180:180:180) (220:220:220)) - (PORT datab (103:103:103) (133:133:133)) - (PORT datad (493:493:493) (582:582:582)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH datab combout (190:190:190) (181:181:181)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (910:910:910) (916:916:916)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~127) - (DELAY - (ABSOLUTE - (PORT dataa (321:321:321) (383:383:383)) - (PORT datab (519:519:519) (623:623:623)) - (PORT datad (295:295:295) (337:337:337)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (914:914:914) (918:918:918)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (910:910:910) (915:915:915)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Equal0\~2) - (DELAY - (ABSOLUTE - (PORT dataa (889:889:889) (1047:1047:1047)) - (PORT datac (414:414:414) (511:511:511)) - (PORT datad (387:387:387) (476:476:476)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~51) - (DELAY - (ABSOLUTE - (PORT dataa (374:374:374) (441:441:441)) - (PORT datab (669:669:669) (792:792:792)) - (PORT datac (493:493:493) (597:597:597)) - (PORT datad (172:172:172) (201:201:201)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~125) - (DELAY - (ABSOLUTE - (PORT dataa (110:110:110) (142:142:142)) - (PORT datab (521:521:521) (625:625:625)) - (PORT datad (179:179:179) (219:219:219)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (914:914:914) (918:918:918)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (910:910:910) (915:915:915)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~79) - (DELAY - (ABSOLUTE - (PORT dataa (753:753:753) (856:856:856)) - (PORT datab (674:674:674) (793:793:793)) - (PORT datac (118:118:118) (160:160:160)) - (PORT datad (119:119:119) (156:156:156)) - (IOPATH dataa combout (165:165:165) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~122) - (DELAY - (ABSOLUTE - (PORT dataa (237:237:237) (307:307:307)) - (PORT datab (348:348:348) (422:422:422)) - (PORT datad (401:401:401) (478:478:478)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH datab combout (167:167:167) (158:158:158)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~123) - (DELAY - (ABSOLUTE - (PORT dataa (300:300:300) (351:351:351)) - (PORT datab (402:402:402) (496:496:496)) - (PORT datac (860:860:860) (1023:1023:1023)) - (PORT datad (317:317:317) (366:366:366)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~124) - (DELAY - (ABSOLUTE - (PORT dataa (357:357:357) (422:422:422)) - (PORT datab (416:416:416) (509:509:509)) - (PORT datad (92:92:92) (109:109:109)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (910:910:910) (916:916:916)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|key_row\~3) - (DELAY - (ABSOLUTE - (PORT datab (848:848:848) (999:999:999)) - (PORT datac (477:477:477) (571:571:571)) - (PORT datad (119:119:119) (156:156:156)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~80) - (DELAY - (ABSOLUTE - (PORT dataa (198:198:198) (256:256:256)) - (PORT datab (339:339:339) (392:392:392)) - (PORT datac (744:744:744) (860:860:860)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~111) + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[3\]) (DELAY (ABSOLUTE - (PORT dataa (448:448:448) (548:548:548)) - (PORT datac (389:389:389) (472:472:472)) - (PORT datad (633:633:633) (736:736:736)) + (PORT clk (919:919:919) (904:904:904)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (311:311:311) (352:352:352)) + (PORT sload (985:985:985) (1102:1102:1102)) + (PORT ena (911:911:911) (988:988:988)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[3\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (210:210:210) (271:271:271)) + (PORT datac (1109:1109:1109) (1293:1293:1293)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH datac combout (120:120:120) (125:125:125)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~97) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[4\]\~4) (DELAY (ABSOLUTE - (PORT dataa (653:653:653) (772:772:772)) - (PORT datab (407:407:407) (498:498:498)) - (PORT datac (347:347:347) (413:413:413)) - (PORT datad (491:491:491) (584:584:584)) - (IOPATH dataa combout (188:188:188) (179:179:179)) - (IOPATH datab combout (188:188:188) (177:177:177)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~116) - (DELAY - (ABSOLUTE - (PORT dataa (195:195:195) (235:235:235)) - (PORT datab (116:116:116) (145:145:145)) - (PORT datad (96:96:96) (117:117:117)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) + (PORT dataa (773:773:773) (880:880:880)) + (PORT datab (509:509:509) (594:594:594)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (172:172:172) (165:165:165)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[4\]) (DELAY (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) + (PORT clk (912:912:912) (900:900:900)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (910:910:910) (916:916:916)) + (PORT asdata (372:372:372) (425:425:425)) + (PORT sload (1116:1116:1116) (1249:1249:1249)) + (PORT ena (1058:1058:1058) (1163:1163:1163)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) ) (TIMINGCHECK (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]\~115) + (INSTANCE z80_\|address_pins_\|abus\[4\]\~28) (DELAY (ABSOLUTE - (PORT dataa (300:300:300) (351:351:351)) - (PORT datab (188:188:188) (227:227:227)) - (PORT datad (403:403:403) (484:484:484)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH datab combout (190:190:190) (181:181:181)) - (IOPATH datac combout (190:190:190) (195:195:195)) + (PORT datac (1345:1345:1345) (1562:1562:1562)) + (PORT datad (129:129:129) (166:166:166)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[5\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (773:773:773) (881:881:881)) + (PORT datab (512:512:512) (593:593:593)) + (PORT datad (166:166:166) (194:194:194)) + (IOPATH dataa combout (172:172:172) (165:165:165)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[5\]) (DELAY (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) + (PORT clk (912:912:912) (900:900:900)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (910:910:910) (916:916:916)) + (PORT asdata (306:306:306) (346:346:346)) + (PORT sload (1116:1116:1116) (1249:1249:1249)) + (PORT ena (1058:1058:1058) (1163:1163:1163)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) ) (TIMINGCHECK (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~77) + (INSTANCE z80_\|address_pins_\|abus\[5\]\~29) (DELAY (ABSOLUTE - (PORT dataa (593:593:593) (687:687:687)) - (PORT datab (643:643:643) (753:753:753)) - (PORT datac (342:342:342) (417:417:417)) - (PORT datad (119:119:119) (156:156:156)) - (IOPATH dataa combout (165:165:165) (163:163:163)) + (PORT datac (1339:1339:1339) (1554:1554:1554)) + (PORT datad (129:129:129) (166:166:166)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[6\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (772:772:772) (879:879:879)) + (PORT datab (486:486:486) (560:560:560)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (172:172:172) (165:165:165)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (912:912:912) (900:900:900)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (377:377:377) (420:420:420)) + (PORT sload (1116:1116:1116) (1249:1249:1249)) + (PORT ena (1058:1058:1058) (1163:1163:1163)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[6\]\~30) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (PORT datac (1339:1339:1339) (1555:1555:1555)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[7\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (793:793:793) (909:909:909)) + (PORT datab (297:297:297) (340:340:340)) + (PORT datad (708:708:708) (801:801:801)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (912:912:912) (899:899:899)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (379:379:379) (422:422:422)) + (PORT sload (1093:1093:1093) (1226:1226:1226)) + (PORT ena (1226:1226:1226) (1349:1349:1349)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[7\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (1524:1524:1524) (1781:1781:1781)) + (PORT datad (515:515:515) (610:610:610)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~81) + (INSTANCE z80_\|address_pins_\|abus\[10\]\~24) (DELAY (ABSOLUTE - (PORT dataa (889:889:889) (1015:1015:1015)) - (PORT datab (103:103:103) (131:131:131)) - (PORT datac (91:91:91) (112:112:112)) - (PORT datad (89:89:89) (107:107:107)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (167:167:167) (156:156:156)) + (PORT dataa (1496:1496:1496) (1753:1753:1753)) + (PORT datad (782:782:782) (909:909:909)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (526:526:526) (585:585:585)) + (PORT clk (1096:1096:1096) (1113:1113:1113)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1875:1875:1875) (2192:2192:2192)) + (PORT d[1] (709:709:709) (814:814:814)) + (PORT d[2] (1712:1712:1712) (2000:2000:2000)) + (PORT d[3] (388:388:388) (456:456:456)) + (PORT d[4] (619:619:619) (710:710:710)) + (PORT d[5] (671:671:671) (772:772:772)) + (PORT d[6] (552:552:552) (635:635:635)) + (PORT d[7] (1678:1678:1678) (1960:1960:1960)) + (PORT d[8] (694:694:694) (790:790:790)) + (PORT d[9] (541:541:541) (621:621:621)) + (PORT d[10] (920:920:920) (1066:1066:1066)) + (PORT d[11] (849:849:849) (966:966:966)) + (PORT d[12] (1482:1482:1482) (1680:1680:1680)) + (PORT clk (1094:1094:1094) (1111:1111:1111)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1093:1093:1093) (1181:1181:1181)) + (PORT clk (1094:1094:1094) (1111:1111:1111)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1096:1096:1096) (1113:1113:1113)) + (PORT d[0] (1226:1226:1226) (1307:1307:1307)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1114:1114:1114)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1114:1114:1114)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1114:1114:1114)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1114:1114:1114)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1076:1076:1076) (1092:1092:1092)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (616:616:616) (624:624:624)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (617:617:617) (625:625:625)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (617:617:617) (625:625:625)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (617:617:617) (625:625:625)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode223w\[2\]) + (DELAY + (ABSOLUTE + (PORT dataa (642:642:642) (745:745:745)) + (PORT datab (130:130:130) (167:167:167)) + (PORT datac (294:294:294) (344:344:344)) + (PORT datad (881:881:881) (999:999:999)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode223w\[2\]\~0) + (DELAY + (ABSOLUTE + (PORT datab (922:922:922) (1095:1095:1095)) + (PORT datac (1424:1424:1424) (1683:1683:1683)) + (PORT datad (1242:1242:1242) (1458:1458:1458)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -41404,22 +31518,35 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1903:1903:1903) (2207:2207:2207)) - (PORT d[1] (924:924:924) (1081:1081:1081)) - (PORT d[2] (1394:1394:1394) (1602:1602:1602)) - (PORT d[3] (1060:1060:1060) (1235:1235:1235)) - (PORT d[4] (1100:1100:1100) (1278:1278:1278)) - (PORT d[5] (1202:1202:1202) (1421:1421:1421)) - (PORT d[6] (1313:1313:1313) (1508:1508:1508)) - (PORT d[7] (1246:1246:1246) (1411:1411:1411)) - (PORT d[8] (1678:1678:1678) (1943:1943:1943)) - (PORT d[9] (1275:1275:1275) (1470:1470:1470)) - (PORT d[10] (2344:2344:2344) (2687:2687:2687)) - (PORT d[11] (1008:1008:1008) (1166:1166:1166)) - (PORT d[12] (1364:1364:1364) (1560:1560:1560)) + (PORT d[0] (405:405:405) (458:458:458)) + (PORT clk (1092:1092:1092) (1110:1110:1110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1499:1499:1499) (1709:1709:1709)) + (PORT d[1] (526:526:526) (610:610:610)) + (PORT d[2] (1547:1547:1547) (1817:1817:1817)) + (PORT d[3] (555:555:555) (640:640:640)) + (PORT d[4] (384:384:384) (447:447:447)) + (PORT d[5] (363:363:363) (419:419:419)) + (PORT d[6] (366:366:366) (424:424:424)) + (PORT d[7] (1232:1232:1232) (1440:1440:1440)) + (PORT d[8] (842:842:842) (955:955:955)) + (PORT d[9] (367:367:367) (421:421:421)) + (PORT d[10] (1230:1230:1230) (1414:1414:1414)) + (PORT d[11] (971:971:971) (1109:1109:1109)) + (PORT d[12] (1466:1466:1466) (1665:1665:1665)) (PORT clk (1090:1090:1090) (1108:1108:1108)) ) ) @@ -41429,27 +31556,70 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.we_a_register) (DELAY (ABSOLUTE + (PORT d[0] (785:785:785) (834:834:834)) (PORT clk (1090:1090:1090) (1108:1108:1108)) - (PORT d[0] (1428:1428:1428) (1591:1591:1591)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1110:1110:1110)) + (PORT d[0] (1041:1041:1041) (1096:1096:1096)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1091:1091:1091) (1109:1109:1109)) + (PORT clk (1093:1093:1093) (1111:1111:1111)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1093:1093:1093) (1111:1111:1111)) (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) ) ) ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1093:1093:1093) (1111:1111:1111)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1093:1093:1093) (1111:1111:1111)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) (DELAY (ABSOLUTE (PORT clk (1072:1072:1072) (1089:1089:1089)) @@ -41463,7 +31633,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) (DELAY (ABSOLUTE (PORT clk (612:612:612) (621:621:621)) @@ -41472,7 +31642,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) (DELAY (ABSOLUTE (PORT clk (613:613:613) (622:622:622)) @@ -41481,7 +31651,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) (DELAY (ABSOLUTE (PORT clk (613:613:613) (622:622:622)) @@ -41491,7 +31661,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) (DELAY (ABSOLUTE (PORT clk (613:613:613) (622:622:622)) @@ -41500,12 +31670,80 @@ ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.datain_a_register) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[0\]\~feeder) (DELAY (ABSOLUTE - (PORT d[0] (858:858:858) (978:978:978)) - (PORT clk (1087:1087:1087) (1105:1105:1105)) + (PORT datad (868:868:868) (981:981:981)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (906:906:906)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (906:906:906)) + (PORT asdata (791:791:791) (887:887:887)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode244w\[2\]) + (DELAY + (ABSOLUTE + (PORT dataa (647:647:647) (752:752:752)) + (PORT datab (126:126:126) (162:162:162)) + (PORT datac (298:298:298) (349:349:349)) + (PORT datad (885:885:885) (1003:1003:1003)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode244w\[2\]\~0) + (DELAY + (ABSOLUTE + (PORT datab (1145:1145:1145) (1359:1359:1359)) + (PORT datac (741:741:741) (882:882:882)) + (PORT datad (1705:1705:1705) (1995:1995:1995)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (543:543:543) (618:618:618)) + (PORT clk (1087:1087:1087) (1106:1106:1106)) ) ) (TIMINGCHECK @@ -41514,23 +31752,23 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1958:1958:1958) (2237:2237:2237)) - (PORT d[1] (952:952:952) (1135:1135:1135)) - (PORT d[2] (1019:1019:1019) (1175:1175:1175)) - (PORT d[3] (1176:1176:1176) (1375:1375:1375)) - (PORT d[4] (1274:1274:1274) (1480:1480:1480)) - (PORT d[5] (965:965:965) (1137:1137:1137)) - (PORT d[6] (813:813:813) (936:936:936)) - (PORT d[7] (825:825:825) (950:950:950)) - (PORT d[8] (1671:1671:1671) (1934:1934:1934)) - (PORT d[9] (1320:1320:1320) (1511:1511:1511)) - (PORT d[10] (1313:1313:1313) (1512:1512:1512)) - (PORT d[11] (1209:1209:1209) (1403:1403:1403)) - (PORT d[12] (1130:1130:1130) (1305:1305:1305)) - (PORT clk (1085:1085:1085) (1103:1103:1103)) + (PORT d[0] (1493:1493:1493) (1703:1703:1703)) + (PORT d[1] (551:551:551) (640:640:640)) + (PORT d[2] (1538:1538:1538) (1806:1806:1806)) + (PORT d[3] (553:553:553) (634:634:634)) + (PORT d[4] (413:413:413) (486:486:486)) + (PORT d[5] (652:652:652) (748:748:748)) + (PORT d[6] (557:557:557) (643:643:643)) + (PORT d[7] (1214:1214:1214) (1421:1421:1421)) + (PORT d[8] (672:672:672) (763:763:763)) + (PORT d[9] (699:699:699) (803:803:803)) + (PORT d[10] (619:619:619) (701:701:701)) + (PORT d[11] (830:830:830) (946:946:946)) + (PORT d[12] (1301:1301:1301) (1479:1479:1479)) + (PORT clk (1085:1085:1085) (1104:1104:1104)) ) ) (TIMINGCHECK @@ -41539,11 +31777,11 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.we_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1619:1619:1619) (1787:1787:1787)) - (PORT clk (1085:1085:1085) (1103:1103:1103)) + (PORT d[0] (1248:1248:1248) (1360:1360:1360)) + (PORT clk (1085:1085:1085) (1104:1104:1104)) ) ) (TIMINGCHECK @@ -41552,60 +31790,60 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1087:1087:1087) (1105:1105:1105)) - (PORT d[0] (2447:2447:2447) (2710:2710:2710)) + (PORT clk (1087:1087:1087) (1106:1106:1106)) + (PORT d[0] (1050:1050:1050) (1112:1112:1112)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1088:1088:1088) (1106:1106:1106)) + (PORT clk (1088:1088:1088) (1107:1107:1107)) (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1088:1088:1088) (1106:1106:1106)) + (PORT clk (1088:1088:1088) (1107:1107:1107)) (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1088:1088:1088) (1106:1106:1106)) + (PORT clk (1088:1088:1088) (1107:1107:1107)) (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1088:1088:1088) (1106:1106:1106)) + (PORT clk (1088:1088:1088) (1107:1107:1107)) (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1042:1042:1042) (1062:1062:1062)) + (PORT clk (1067:1067:1067) (1085:1085:1085)) (IOPATH (posedge clk) q (164:164:164) (167:167:167)) ) ) @@ -41616,108 +31854,303 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.datain_b_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.active_core_port_b) (DELAY (ABSOLUTE - (PORT d[0] (941:941:941) (1043:1043:1043)) - (PORT clk (1047:1047:1047) (1065:1065:1065)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2450:2450:2450) (2777:2777:2777)) - (PORT d[1] (2392:2392:2392) (2704:2704:2704)) - (PORT d[2] (2394:2394:2394) (2721:2721:2721)) - (PORT d[3] (2491:2491:2491) (2861:2861:2861)) - (PORT d[4] (2566:2566:2566) (2910:2910:2910)) - (PORT d[5] (2373:2373:2373) (2706:2706:2706)) - (PORT d[6] (2612:2612:2612) (2990:2990:2990)) - (PORT d[7] (2373:2373:2373) (2714:2714:2714)) - (PORT d[8] (2476:2476:2476) (2808:2808:2808)) - (PORT d[9] (2554:2554:2554) (2935:2935:2935)) - (PORT d[10] (2444:2444:2444) (2765:2765:2765)) - (PORT d[11] (2421:2421:2421) (2728:2728:2728)) - (PORT d[12] (2407:2407:2407) (2712:2712:2712)) - (PORT clk (1044:1044:1044) (1064:1064:1064)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1047:1047:1047) (1065:1065:1065)) + (PORT clk (607:607:607) (617:617:617)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1048:1048:1048) (1066:1066:1066)) + (PORT clk (608:608:608) (618:618:618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (608:608:608) (618:618:618)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (608:608:608) (618:618:618)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (907:907:907) (911:911:911)) + (PORT asdata (1130:1130:1130) (1268:1268:1268)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (907:907:907) (911:911:911)) + (PORT asdata (1105:1105:1105) (1255:1255:1255)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[1\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (316:316:316) (365:365:365)) + (PORT datab (627:627:627) (728:728:728)) + (PORT datac (462:462:462) (532:532:532)) + (PORT datad (759:759:759) (867:867:867)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode252w\[2\]) + (DELAY + (ABSOLUTE + (PORT dataa (646:646:646) (750:750:750)) + (PORT datab (127:127:127) (163:163:163)) + (PORT datac (297:297:297) (348:348:348)) + (PORT datad (884:884:884) (1002:1002:1002)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode252w\[2\]\~0) + (DELAY + (ABSOLUTE + (PORT datab (1147:1147:1147) (1361:1361:1361)) + (PORT datac (739:739:739) (880:880:880)) + (PORT datad (1703:1703:1703) (1992:1992:1992)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (563:563:563) (640:640:640)) + (PORT clk (1090:1090:1090) (1108:1108:1108)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1332:1332:1332) (1522:1522:1522)) + (PORT d[1] (555:555:555) (646:646:646)) + (PORT d[2] (1526:1526:1526) (1793:1793:1793)) + (PORT d[3] (1600:1600:1600) (1854:1854:1854)) + (PORT d[4] (413:413:413) (477:477:477)) + (PORT d[5] (678:678:678) (782:782:782)) + (PORT d[6] (550:550:550) (630:630:630)) + (PORT d[7] (1071:1071:1071) (1266:1266:1266)) + (PORT d[8] (675:675:675) (765:765:765)) + (PORT d[9] (546:546:546) (626:626:626)) + (PORT d[10] (368:368:368) (422:422:422)) + (PORT d[11] (839:839:839) (954:954:954)) + (PORT d[12] (1298:1298:1298) (1478:1478:1478)) + (PORT clk (1088:1088:1088) (1106:1106:1106)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (985:985:985) (1066:1066:1066)) + (PORT clk (1088:1088:1088) (1106:1106:1106)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1108:1108:1108)) + (PORT d[0] (1047:1047:1047) (1109:1109:1109)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1109:1109:1109)) (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1048:1048:1048) (1066:1066:1066)) + (PORT clk (1091:1091:1091) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1048:1048:1048) (1066:1066:1066)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + (PORT clk (1091:1091:1091) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1048:1048:1048) (1066:1066:1066)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + (PORT clk (1091:1091:1091) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.dataout_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2356:2356:2356) (2720:2720:2720)) - (PORT d[1] (1675:1675:1675) (1954:1954:1954)) - (PORT d[2] (1571:1571:1571) (1793:1793:1793)) - (PORT d[3] (1306:1306:1306) (1539:1539:1539)) - (PORT d[4] (1463:1463:1463) (1705:1705:1705)) - (PORT d[5] (1474:1474:1474) (1713:1713:1713)) - (PORT d[6] (1093:1093:1093) (1258:1258:1258)) - (PORT d[7] (1344:1344:1344) (1523:1523:1523)) - (PORT d[8] (1807:1807:1807) (2124:2124:2124)) - (PORT d[9] (1492:1492:1492) (1734:1734:1734)) - (PORT d[10] (2804:2804:2804) (3207:3207:3207)) - (PORT d[11] (1095:1095:1095) (1275:1275:1275)) - (PORT d[12] (1289:1289:1289) (1483:1483:1483)) + (PORT clk (1070:1070:1070) (1087:1087:1087)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (610:610:610) (619:619:619)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (611:611:611) (620:620:620)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (611:611:611) (620:620:620)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (611:611:611) (620:620:620)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (606:606:606) (691:691:691)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (880:880:880) (1004:1004:1004)) + (PORT datad (661:661:661) (748:748:748)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (196:196:196) (205:205:205)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1163:1163:1163) (1327:1327:1327)) + (PORT d[1] (946:946:946) (1096:1096:1096)) + (PORT d[2] (1375:1375:1375) (1597:1597:1597)) + (PORT d[3] (1532:1532:1532) (1769:1769:1769)) + (PORT d[4] (589:589:589) (687:687:687)) + (PORT d[5] (863:863:863) (990:990:990)) + (PORT d[6] (1778:1778:1778) (2007:2007:2007)) + (PORT d[7] (1024:1024:1024) (1205:1205:1205)) + (PORT d[8] (884:884:884) (1007:1007:1007)) + (PORT d[9] (1978:1978:1978) (2326:2326:2326)) + (PORT d[10] (696:696:696) (798:798:798)) + (PORT d[11] (821:821:821) (931:931:931)) + (PORT d[12] (1102:1102:1102) (1252:1252:1252)) (PORT clk (1095:1095:1095) (1112:1112:1112)) ) ) @@ -41727,17 +32160,17 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) (DELAY (ABSOLUTE (PORT clk (1095:1095:1095) (1112:1112:1112)) - (PORT d[0] (2275:2275:2275) (2058:2058:2058)) + (PORT d[0] (1499:1499:1499) (1355:1355:1355)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) (DELAY (ABSOLUTE (PORT clk (1096:1096:1096) (1113:1113:1113)) @@ -41747,7 +32180,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) (DELAY (ABSOLUTE (PORT clk (1077:1077:1077) (1093:1093:1093)) @@ -41761,7 +32194,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) (DELAY (ABSOLUTE (PORT clk (617:617:617) (625:625:625)) @@ -41770,7 +32203,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) (DELAY (ABSOLUTE (PORT clk (618:618:618) (626:626:626)) @@ -41779,7 +32212,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) (DELAY (ABSOLUTE (PORT clk (618:618:618) (626:626:626)) @@ -41789,7 +32222,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) (DELAY (ABSOLUTE (PORT clk (618:618:618) (626:626:626)) @@ -41799,283 +32232,22 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.datain_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (876:876:876) (1020:1020:1020)) - (PORT clk (1088:1088:1088) (1106:1106:1106)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1688:1688:1688) (1964:1964:1964)) - (PORT d[1] (1334:1334:1334) (1569:1569:1569)) - (PORT d[2] (1223:1223:1223) (1416:1416:1416)) - (PORT d[3] (1064:1064:1064) (1252:1252:1252)) - (PORT d[4] (1419:1419:1419) (1629:1629:1629)) - (PORT d[5] (1143:1143:1143) (1344:1344:1344)) - (PORT d[6] (986:986:986) (1130:1130:1130)) - (PORT d[7] (1372:1372:1372) (1582:1582:1582)) - (PORT d[8] (1652:1652:1652) (1914:1914:1914)) - (PORT d[9] (1153:1153:1153) (1324:1324:1324)) - (PORT d[10] (1141:1141:1141) (1317:1317:1317)) - (PORT d[11] (1383:1383:1383) (1601:1601:1601)) - (PORT d[12] (1451:1451:1451) (1660:1660:1660)) - (PORT clk (1086:1086:1086) (1104:1104:1104)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1453:1453:1453) (1609:1609:1609)) - (PORT clk (1086:1086:1086) (1104:1104:1104)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1088:1088:1088) (1106:1106:1106)) - (PORT d[0] (2488:2488:2488) (2278:2278:2278)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1089:1089:1089) (1107:1107:1107)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1089:1089:1089) (1107:1107:1107)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1089:1089:1089) (1107:1107:1107)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1089:1089:1089) (1107:1107:1107)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1043:1043:1043) (1063:1063:1063)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1108:1108:1108) (1228:1228:1228)) - (PORT clk (1048:1048:1048) (1066:1066:1066)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2443:2443:2443) (2777:2777:2777)) - (PORT d[1] (2372:2372:2372) (2684:2684:2684)) - (PORT d[2] (2405:2405:2405) (2732:2732:2732)) - (PORT d[3] (2484:2484:2484) (2833:2833:2833)) - (PORT d[4] (2401:2401:2401) (2725:2725:2725)) - (PORT d[5] (2571:2571:2571) (2915:2915:2915)) - (PORT d[6] (2478:2478:2478) (2831:2831:2831)) - (PORT d[7] (2422:2422:2422) (2757:2757:2757)) - (PORT d[8] (2472:2472:2472) (2808:2808:2808)) - (PORT d[9] (2555:2555:2555) (2931:2931:2931)) - (PORT d[10] (2414:2414:2414) (2717:2717:2717)) - (PORT d[11] (2582:2582:2582) (2920:2920:2920)) - (PORT d[12] (2506:2506:2506) (2850:2850:2850)) - (PORT clk (1045:1045:1045) (1065:1065:1065)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1048:1048:1048) (1066:1066:1066)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1049:1049:1049) (1067:1067:1067)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1049:1049:1049) (1067:1067:1067)) - (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1049:1049:1049) (1067:1067:1067)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1049:1049:1049) (1067:1067:1067)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1044:1044:1044) (1064:1064:1064)) - (IOPATH (posedge clk) q (164:164:164) (166:166:166)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Selector4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (646:646:646) (757:757:757)) - (PORT datab (501:501:501) (596:596:596)) - (PORT datac (785:785:785) (890:890:890)) - (PORT datad (804:804:804) (913:913:913)) - (IOPATH dataa combout (188:188:188) (184:184:184)) - (IOPATH datab combout (190:190:190) (188:188:188)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Selector4\~1) - (DELAY - (ABSOLUTE - (PORT dataa (735:735:735) (849:849:849)) - (PORT datab (508:508:508) (603:603:603)) - (PORT datac (801:801:801) (924:924:924)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (190:190:190) (177:177:177)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (496:496:496) (569:569:569)) - (PORT clk (1092:1092:1092) (1109:1109:1109)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1898:1898:1898) (2205:2205:2205)) - (PORT d[1] (1002:1002:1002) (1185:1185:1185)) - (PORT d[2] (1140:1140:1140) (1304:1304:1304)) - (PORT d[3] (1203:1203:1203) (1403:1403:1403)) - (PORT d[4] (1057:1057:1057) (1219:1219:1219)) - (PORT d[5] (774:774:774) (921:921:921)) - (PORT d[6] (820:820:820) (948:948:948)) - (PORT d[7] (1963:1963:1963) (2216:2216:2216)) - (PORT d[8] (1431:1431:1431) (1674:1674:1674)) - (PORT d[9] (2015:2015:2015) (2327:2327:2327)) - (PORT d[10] (1692:1692:1692) (1948:1948:1948)) - (PORT d[11] (827:827:827) (959:959:959)) - (PORT d[12] (830:830:830) (960:960:960)) + (PORT d[0] (1038:1038:1038) (1194:1194:1194)) + (PORT d[1] (1297:1297:1297) (1490:1490:1490)) + (PORT d[2] (1176:1176:1176) (1388:1388:1388)) + (PORT d[3] (1067:1067:1067) (1238:1238:1238)) + (PORT d[4] (1328:1328:1328) (1516:1516:1516)) + (PORT d[5] (960:960:960) (1096:1096:1096)) + (PORT d[6] (980:980:980) (1125:1125:1125)) + (PORT d[7] (861:861:861) (1007:1007:1007)) + (PORT d[8] (1247:1247:1247) (1439:1439:1439)) + (PORT d[9] (1757:1757:1757) (2045:2045:2045)) + (PORT d[10] (926:926:926) (1078:1078:1078)) + (PORT d[11] (1117:1117:1117) (1272:1272:1272)) + (PORT d[12] (1149:1149:1149) (1299:1299:1299)) (PORT clk (1090:1090:1090) (1107:1107:1107)) ) ) @@ -42085,70 +32257,27 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.we_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) (DELAY (ABSOLUTE - (PORT d[0] (1893:1893:1893) (2093:2093:2093)) (PORT clk (1090:1090:1090) (1107:1107:1107)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1092:1092:1092) (1109:1109:1109)) - (PORT d[0] (1046:1046:1046) (1116:1116:1116)) + (PORT d[0] (1447:1447:1447) (1601:1601:1601)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.wpgen_a) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1093:1093:1093) (1110:1110:1110)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1093:1093:1093) (1110:1110:1110)) + (PORT clk (1091:1091:1091) (1108:1108:1108)) (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) ) ) ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1093:1093:1093) (1110:1110:1110)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1093:1093:1093) (1110:1110:1110)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.dataout_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) (DELAY (ABSOLUTE (PORT clk (1072:1072:1072) (1088:1088:1088)) @@ -42162,7 +32291,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.active_core_port_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) (DELAY (ABSOLUTE (PORT clk (612:612:612) (620:620:620)) @@ -42171,7 +32300,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) (DELAY (ABSOLUTE (PORT clk (613:613:613) (621:621:621)) @@ -42180,7 +32309,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.ftpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) (DELAY (ABSOLUTE (PORT clk (613:613:613) (621:621:621)) @@ -42190,7 +32319,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rwpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) (DELAY (ABSOLUTE (PORT clk (613:613:613) (621:621:621)) @@ -42199,12 +32328,577 @@ ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.datain_a_register) + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE CLOCK_50\~inputclkctrl) (DELAY (ABSOLUTE - (PORT d[0] (828:828:828) (944:944:944)) - (PORT clk (1082:1082:1082) (1100:1100:1100)) + (PORT inclk[0] (91:91:91) (78:78:78)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|address_reg_a\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (865:865:865) (977:977:977)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|address_reg_a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (906:906:906)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (906:906:906)) + (PORT asdata (294:294:294) (334:334:334)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (142:142:142) (193:193:193)) + (PORT datab (1444:1444:1444) (1703:1703:1703)) + (PORT datad (900:900:900) (1067:1067:1067)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (190:190:190) (188:188:188)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|decode2\|eq_node\[1\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (646:646:646) (751:751:751)) + (PORT datab (127:127:127) (161:161:161)) + (PORT datac (298:298:298) (348:348:348)) + (PORT datad (885:885:885) (1002:1002:1002)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vram_address\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (500:500:500) (591:591:591)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vram_address\~0) + (DELAY + (ABSOLUTE + (PORT dataa (406:406:406) (515:515:515)) + (PORT datab (407:407:407) (496:496:496)) + (PORT datac (613:613:613) (722:722:722)) + (PORT datad (372:372:372) (452:452:452)) + (IOPATH dataa combout (188:188:188) (203:203:203)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (917:917:917) (922:922:922)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (625:625:625) (673:673:673)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vram_address\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (486:486:486) (568:568:568)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (917:917:917) (922:922:922)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (625:625:625) (673:673:673)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vram_address\[2\]\~4) + (DELAY + (ABSOLUTE + (PORT datac (408:408:408) (500:500:500)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (917:917:917) (922:922:922)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (625:625:625) (673:673:673)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add3\~0) + (DELAY + (ABSOLUTE + (PORT datac (411:411:411) (504:504:504)) + (PORT datad (605:605:605) (699:699:699)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (917:917:917) (922:922:922)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (625:625:625) (673:673:673)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add3\~1) + (DELAY + (ABSOLUTE + (PORT dataa (511:511:511) (614:614:614)) + (PORT datac (407:407:407) (499:499:499)) + (PORT datad (605:605:605) (699:699:699)) + (IOPATH dataa combout (166:166:166) (173:173:173)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (917:917:917) (922:922:922)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (625:625:625) (673:673:673)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (503:503:503) (602:602:602)) + (PORT datab (660:660:660) (778:778:778)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~2) + (DELAY + (ABSOLUTE + (PORT datab (527:527:527) (628:628:628)) + (IOPATH datab combout (167:167:167) (174:174:174)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~4) + (DELAY + (ABSOLUTE + (PORT datab (623:623:623) (725:725:725)) + (IOPATH datab combout (188:188:188) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~6) + (DELAY + (ABSOLUTE + (PORT datab (410:410:410) (496:496:496)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (916:916:916) (921:921:921)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (661:661:661) (730:730:730)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~8) + (DELAY + (ABSOLUTE + (PORT datab (501:501:501) (600:600:600)) + (IOPATH datab combout (188:188:188) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (916:916:916) (921:921:921)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (661:661:661) (730:730:730)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~10) + (DELAY + (ABSOLUTE + (PORT dataa (516:516:516) (600:600:600)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (916:916:916) (921:921:921)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (661:661:661) (730:730:730)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~12) + (DELAY + (ABSOLUTE + (PORT dataa (611:611:611) (704:704:704)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Selector6\~0) + (DELAY + (ABSOLUTE + (PORT datab (512:512:512) (610:610:610)) + (PORT datac (163:163:163) (197:197:197)) + (PORT datad (177:177:177) (210:210:210)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vram_address\[9\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (403:403:403) (511:511:511)) + (PORT datab (404:404:404) (492:492:492)) + (PORT datac (617:617:617) (726:726:726)) + (PORT datad (373:373:373) (453:453:453)) + (IOPATH dataa combout (188:188:188) (203:203:203)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (917:917:917) (922:922:922)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (660:660:660) (729:729:729)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~14) + (DELAY + (ABSOLUTE + (PORT datad (495:495:495) (576:576:576)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Selector5\~0) + (DELAY + (ABSOLUTE + (PORT datab (512:512:512) (610:610:610)) + (PORT datac (174:174:174) (210:210:210)) + (PORT datad (177:177:177) (210:210:210)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (917:917:917) (922:922:922)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (660:660:660) (729:729:729)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vram_address\[10\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (400:400:400) (507:507:507)) + (PORT datab (400:400:400) (489:489:489)) + (PORT datac (621:621:621) (731:731:731)) + (PORT datad (375:375:375) (456:456:456)) + (IOPATH dataa combout (188:188:188) (203:203:203)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vram_address\[10\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (407:407:407) (516:516:516)) + (PORT datab (326:326:326) (381:381:381)) + (PORT datad (93:93:93) (111:111:111)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (917:917:917) (922:922:922)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Selector3\~0) + (DELAY + (ABSOLUTE + (PORT datac (494:494:494) (590:590:590)) + (PORT datad (179:179:179) (212:212:212)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (917:917:917) (922:922:922)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (660:660:660) (729:729:729)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Selector2\~0) + (DELAY + (ABSOLUTE + (PORT datac (494:494:494) (590:590:590)) + (PORT datad (178:178:178) (211:211:211)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (917:917:917) (922:922:922)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (660:660:660) (729:729:729)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (772:772:772) (892:892:892)) + (PORT clk (1097:1097:1097) (1114:1114:1114)) ) ) (TIMINGCHECK @@ -42213,23 +32907,23 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2082:2082:2082) (2419:2419:2419)) - (PORT d[1] (977:977:977) (1152:1152:1152)) - (PORT d[2] (1908:1908:1908) (2182:2182:2182)) - (PORT d[3] (1200:1200:1200) (1400:1400:1400)) - (PORT d[4] (1473:1473:1473) (1710:1710:1710)) - (PORT d[5] (973:973:973) (1145:1145:1145)) - (PORT d[6] (1035:1035:1035) (1202:1202:1202)) - (PORT d[7] (970:970:970) (1112:1112:1112)) - (PORT d[8] (1931:1931:1931) (2242:2242:2242)) - (PORT d[9] (1624:1624:1624) (1868:1868:1868)) - (PORT d[10] (2021:2021:2021) (2323:2323:2323)) - (PORT d[11] (1010:1010:1010) (1172:1172:1172)) - (PORT d[12] (1004:1004:1004) (1151:1151:1151)) - (PORT clk (1080:1080:1080) (1098:1098:1098)) + (PORT d[0] (1595:1595:1595) (1860:1860:1860)) + (PORT d[1] (1745:1745:1745) (2003:2003:2003)) + (PORT d[2] (1104:1104:1104) (1280:1280:1280)) + (PORT d[3] (1545:1545:1545) (1822:1822:1822)) + (PORT d[4] (1689:1689:1689) (1942:1942:1942)) + (PORT d[5] (1970:1970:1970) (2271:2271:2271)) + (PORT d[6] (1266:1266:1266) (1449:1449:1449)) + (PORT d[7] (1101:1101:1101) (1302:1302:1302)) + (PORT d[8] (1557:1557:1557) (1774:1774:1774)) + (PORT d[9] (1756:1756:1756) (2017:2017:2017)) + (PORT d[10] (2064:2064:2064) (2406:2406:2406)) + (PORT d[11] (1692:1692:1692) (1975:1975:1975)) + (PORT d[12] (1181:1181:1181) (1354:1354:1354)) + (PORT clk (1095:1095:1095) (1112:1112:1112)) ) ) (TIMINGCHECK @@ -42238,11 +32932,11 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.we_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1078:1078:1078) (1178:1178:1178)) - (PORT clk (1080:1080:1080) (1098:1098:1098)) + (PORT d[0] (1767:1767:1767) (1944:1944:1944)) + (PORT clk (1095:1095:1095) (1112:1112:1112)) ) ) (TIMINGCHECK @@ -42251,60 +32945,60 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1082:1082:1082) (1100:1100:1100)) - (PORT d[0] (1538:1538:1538) (1677:1677:1677)) + (PORT clk (1097:1097:1097) (1114:1114:1114)) + (PORT d[0] (1899:1899:1899) (2061:2061:2061)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1083:1083:1083) (1101:1101:1101)) + (PORT clk (1098:1098:1098) (1115:1115:1115)) (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1083:1083:1083) (1101:1101:1101)) + (PORT clk (1098:1098:1098) (1115:1115:1115)) (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1083:1083:1083) (1101:1101:1101)) + (PORT clk (1098:1098:1098) (1115:1115:1115)) (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1083:1083:1083) (1101:1101:1101)) + (PORT clk (1098:1098:1098) (1115:1115:1115)) (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1062:1062:1062) (1079:1079:1079)) + (PORT clk (1052:1052:1052) (1071:1071:1071)) (IOPATH (posedge clk) q (164:164:164) (167:167:167)) ) ) @@ -42315,38 +33009,5958 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.datain_b_register) (DELAY (ABSOLUTE - (PORT clk (602:602:602) (611:611:611)) + (PORT d[0] (1564:1564:1564) (1820:1820:1820)) + (PORT clk (1057:1057:1057) (1074:1074:1074)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2286:2286:2286) (2589:2589:2589)) + (PORT d[1] (2310:2310:2310) (2608:2608:2608)) + (PORT d[2] (2269:2269:2269) (2561:2561:2561)) + (PORT d[3] (2308:2308:2308) (2647:2647:2647)) + (PORT d[4] (2333:2333:2333) (2626:2626:2626)) + (PORT d[5] (2461:2461:2461) (2789:2789:2789)) + (PORT d[6] (2359:2359:2359) (2675:2675:2675)) + (PORT d[7] (2320:2320:2320) (2643:2643:2643)) + (PORT d[8] (2349:2349:2349) (2647:2647:2647)) + (PORT d[9] (2386:2386:2386) (2705:2705:2705)) + (PORT d[10] (2265:2265:2265) (2548:2548:2548)) + (PORT d[11] (2407:2407:2407) (2717:2717:2717)) + (PORT d[12] (2235:2235:2235) (2535:2535:2535)) + (PORT clk (1054:1054:1054) (1073:1073:1073)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1057:1057:1057) (1074:1074:1074)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_b) (DELAY (ABSOLUTE - (PORT clk (603:603:603) (612:612:612)) + (PORT clk (1058:1058:1058) (1075:1075:1075)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (603:603:603) (612:612:612)) + (PORT clk (1058:1058:1058) (1075:1075:1075)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1058:1058:1058) (1075:1075:1075)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (603:603:603) (612:612:612)) + (PORT clk (1058:1058:1058) (1075:1075:1075)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|decode2\|eq_node\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (643:643:643) (747:747:747)) + (PORT datab (129:129:129) (166:166:166)) + (PORT datac (295:295:295) (346:346:346)) + (PORT datad (882:882:882) (1000:1000:1000)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (889:889:889) (1010:1010:1010)) + (PORT clk (1105:1105:1105) (1123:1123:1123)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1581:1581:1581) (1843:1843:1843)) + (PORT d[1] (1541:1541:1541) (1776:1776:1776)) + (PORT d[2] (1278:1278:1278) (1477:1477:1477)) + (PORT d[3] (1342:1342:1342) (1579:1579:1579)) + (PORT d[4] (1506:1506:1506) (1734:1734:1734)) + (PORT d[5] (1789:1789:1789) (2069:2069:2069)) + (PORT d[6] (1439:1439:1439) (1641:1641:1641)) + (PORT d[7] (1140:1140:1140) (1347:1347:1347)) + (PORT d[8] (1375:1375:1375) (1564:1564:1564)) + (PORT d[9] (1545:1545:1545) (1783:1783:1783)) + (PORT d[10] (2515:2515:2515) (2924:2924:2924)) + (PORT d[11] (1550:1550:1550) (1813:1813:1813)) + (PORT d[12] (1486:1486:1486) (1699:1699:1699)) + (PORT clk (1103:1103:1103) (1121:1121:1121)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1430:1430:1430) (1560:1560:1560)) + (PORT clk (1103:1103:1103) (1121:1121:1121)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1105:1105:1105) (1123:1123:1123)) + (PORT d[0] (2260:2260:2260) (2100:2100:2100)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1106:1106:1106) (1124:1124:1124)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1106:1106:1106) (1124:1124:1124)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1106:1106:1106) (1124:1124:1124)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1106:1106:1106) (1124:1124:1124)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1060:1060:1060) (1080:1080:1080)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1726:1726:1726) (2000:2000:2000)) + (PORT clk (1065:1065:1065) (1083:1083:1083)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2233:2233:2233) (2517:2517:2517)) + (PORT d[1] (2299:2299:2299) (2593:2593:2593)) + (PORT d[2] (2300:2300:2300) (2594:2594:2594)) + (PORT d[3] (2280:2280:2280) (2604:2604:2604)) + (PORT d[4] (2357:2357:2357) (2664:2664:2664)) + (PORT d[5] (2336:2336:2336) (2645:2645:2645)) + (PORT d[6] (2392:2392:2392) (2689:2689:2689)) + (PORT d[7] (2236:2236:2236) (2545:2545:2545)) + (PORT d[8] (2403:2403:2403) (2719:2719:2719)) + (PORT d[9] (2356:2356:2356) (2663:2663:2663)) + (PORT d[10] (2258:2258:2258) (2540:2540:2540)) + (PORT d[11] (2351:2351:2351) (2631:2631:2631)) + (PORT d[12] (2348:2348:2348) (2657:2657:2657)) + (PORT clk (1062:1062:1062) (1082:1082:1082)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1065:1065:1065) (1083:1083:1083)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1066:1066:1066) (1084:1084:1084)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1066:1066:1066) (1084:1084:1084)) + (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1066:1066:1066) (1084:1084:1084)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1066:1066:1066) (1084:1084:1084)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1061:1061:1061) (1081:1081:1081)) + (IOPATH (posedge clk) q (164:164:164) (166:166:166)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (786:786:786) (959:959:959)) + (PORT datab (472:472:472) (537:537:537)) + (PORT datac (806:806:806) (922:922:922)) + (PORT datad (827:827:827) (942:942:942)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (787:787:787) (960:960:960)) + (PORT datab (636:636:636) (732:732:732)) + (PORT datac (776:776:776) (878:878:878)) + (PORT datad (90:90:90) (106:106:106)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~81) + (DELAY + (ABSOLUTE + (PORT dataa (106:106:106) (138:138:138)) + (PORT datab (669:669:669) (795:795:795)) + (PORT datac (1503:1503:1503) (1764:1764:1764)) + (PORT datad (157:157:157) (183:183:183)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (169:169:169) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (478:478:478) (562:562:562)) + (PORT datab (480:480:480) (559:559:559)) + (PORT datac (172:172:172) (209:209:209)) + (PORT datad (94:94:94) (113:113:113)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (182:182:182) (177:177:177)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[1\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (476:476:476) (559:559:559)) + (PORT datab (516:516:516) (608:608:608)) + (PORT datac (846:846:846) (958:958:958)) + (PORT datad (92:92:92) (109:109:109)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[1\]) + (DELAY + (ABSOLUTE + (PORT dataa (797:797:797) (914:914:914)) + (PORT datab (116:116:116) (144:144:144)) + (PORT datac (600:600:600) (676:676:676)) + (PORT datad (195:195:195) (230:230:230)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_re\~2) + (DELAY + (ABSOLUTE + (PORT dataa (675:675:675) (783:783:783)) + (PORT datab (120:120:120) (149:149:149)) + (PORT datac (529:529:529) (624:624:624)) + (PORT datad (532:532:532) (634:634:634)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_2) + (DELAY + (ABSOLUTE + (PORT dataa (798:798:798) (915:915:915)) + (PORT datab (592:592:592) (674:674:674)) + (PORT datac (601:601:601) (702:702:702)) + (PORT datad (407:407:407) (460:460:460)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (917:917:917) (904:904:904)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (421:421:421) (449:449:449)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[1\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (211:211:211) (256:256:256)) + (PORT datab (105:105:105) (134:134:134)) + (PORT datac (130:130:130) (171:171:171)) + (PORT datad (304:304:304) (354:354:354)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (909:909:909) (896:896:896)) + (PORT ena (912:912:912) (993:993:993)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal2\~0) + (DELAY + (ABSOLUTE + (PORT datab (945:945:945) (1094:1094:1094)) + (PORT datac (351:351:351) (423:423:423)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1232:1232:1232) (1445:1445:1445)) + (PORT datab (545:545:545) (644:644:644)) + (PORT datac (643:643:643) (744:744:744)) + (PORT datad (487:487:487) (582:582:582)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~39) + (DELAY + (ABSOLUTE + (PORT dataa (558:558:558) (670:670:670)) + (PORT datab (673:673:673) (799:799:799)) + (PORT datac (502:502:502) (581:581:581)) + (PORT datad (552:552:552) (648:648:648)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~36) + (DELAY + (ABSOLUTE + (PORT datab (327:327:327) (388:388:388)) + (PORT datac (650:650:650) (760:760:760)) + (PORT datad (340:340:340) (391:391:391)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~4) + (DELAY + (ABSOLUTE + (PORT dataa (474:474:474) (559:559:559)) + (PORT datab (504:504:504) (588:588:588)) + (PORT datac (925:925:925) (1089:1089:1089)) + (PORT datad (914:914:914) (1077:1077:1077)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~16) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (224:224:224)) + (PORT datab (1189:1189:1189) (1374:1374:1374)) + (PORT datac (814:814:814) (936:936:936)) + (PORT datad (154:154:154) (180:180:180)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~17) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (133:133:133)) + (PORT datab (110:110:110) (142:142:142)) + (PORT datac (703:703:703) (798:798:798)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1098:1098:1098) (1280:1280:1280)) + (PORT datab (1264:1264:1264) (1472:1472:1472)) + (PORT datac (486:486:486) (566:566:566)) + (PORT datad (349:349:349) (410:410:410)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~6) + (DELAY + (ABSOLUTE + (PORT dataa (635:635:635) (721:721:721)) + (PORT datab (1152:1152:1152) (1344:1344:1344)) + (PORT datac (469:469:469) (540:540:540)) + (PORT datad (596:596:596) (697:697:697)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (907:907:907) (911:911:911)) + (PORT asdata (1039:1039:1039) (1161:1161:1161)) + (PORT ena (505:505:505) (542:542:542)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (907:907:907) (911:911:911)) + (PORT asdata (1039:1039:1039) (1161:1161:1161)) + (PORT ena (417:417:417) (434:434:434)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~44) + (DELAY + (ABSOLUTE + (PORT dataa (129:129:129) (180:180:180)) + (PORT datab (139:139:139) (175:175:175)) + (PORT datad (122:122:122) (144:144:144)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (919:919:919)) + (PORT asdata (283:283:283) (305:305:305)) + (PORT ena (501:501:501) (535:535:535)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (919:919:919)) + (PORT asdata (283:283:283) (304:304:304)) + (PORT ena (502:502:502) (534:534:534)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~43) + (DELAY + (ABSOLUTE + (PORT dataa (217:217:217) (262:262:262)) + (PORT datab (226:226:226) (269:269:269)) + (PORT datad (117:117:117) (154:154:154)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (907:907:907) (912:912:912)) + (PORT asdata (669:669:669) (738:738:738)) + (PORT ena (669:669:669) (725:725:725)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (880:880:880) (986:986:986)) + (PORT ena (634:634:634) (686:686:686)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (477:477:477) (561:561:561)) + (PORT datab (303:303:303) (355:355:355)) + (PORT datad (544:544:544) (614:614:614)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~47) + (DELAY + (ABSOLUTE + (PORT datab (523:523:523) (614:614:614)) + (PORT datad (337:337:337) (395:395:395)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (846:846:846) (954:954:954)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (907:907:907) (911:911:911)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (405:405:405) (422:422:422)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (911:911:911)) + (PORT asdata (652:652:652) (720:720:720)) + (PORT ena (768:768:768) (845:845:845)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~49) + (DELAY + (ABSOLUTE + (PORT dataa (389:389:389) (465:465:465)) + (PORT datab (196:196:196) (251:251:251)) + (PORT datad (192:192:192) (226:226:226)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (919:919:919)) + (PORT asdata (493:493:493) (533:533:533)) + (PORT ena (656:656:656) (712:712:712)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (177:177:177) (203:203:203)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (919:919:919)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (637:637:637) (680:680:680)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~45) + (DELAY + (ABSOLUTE + (PORT dataa (381:381:381) (449:449:449)) + (PORT datab (385:385:385) (450:450:450)) + (PORT datad (118:118:118) (155:155:155)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (907:907:907) (912:912:912)) + (PORT asdata (669:669:669) (739:739:739)) + (PORT ena (655:655:655) (712:712:712)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (881:881:881) (986:986:986)) + (PORT ena (644:644:644) (699:699:699)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~48) + (DELAY + (ABSOLUTE + (PORT dataa (351:351:351) (419:419:419)) + (PORT datab (387:387:387) (474:474:474)) + (PORT datad (366:366:366) (436:436:436)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~50) + (DELAY + (ABSOLUTE + (PORT dataa (334:334:334) (398:398:398)) + (PORT datab (338:338:338) (396:396:396)) + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (330:330:330) (378:378:378)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (319:319:319) (379:379:379)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datad (174:174:174) (207:207:207)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~52) + (DELAY + (ABSOLUTE + (PORT dataa (466:466:466) (540:540:540)) + (PORT datab (175:175:175) (210:210:210)) + (PORT datac (323:323:323) (367:367:367)) + (PORT datad (106:106:106) (125:125:125)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_35) + (DELAY + (ABSOLUTE + (PORT dataa (483:483:483) (563:563:563)) + (PORT datab (181:181:181) (222:222:222)) + (PORT datac (620:620:620) (712:712:712)) + (PORT datad (337:337:337) (389:389:389)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~15) + (DELAY + (ABSOLUTE + (PORT dataa (678:678:678) (785:785:785)) + (PORT datab (974:974:974) (1160:1160:1160)) + (PORT datac (794:794:794) (936:936:936)) + (PORT datad (456:456:456) (516:516:516)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~16) + (DELAY + (ABSOLUTE + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (95:95:95) (118:118:118)) + (PORT datad (104:104:104) (121:121:121)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~17) + (DELAY + (ABSOLUTE + (PORT dataa (193:193:193) (230:230:230)) + (PORT datab (107:107:107) (137:137:137)) + (PORT datac (102:102:102) (123:123:123)) + (PORT datad (536:536:536) (609:609:609)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~18) + (DELAY + (ABSOLUTE + (PORT dataa (659:659:659) (758:758:758)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (345:345:345) (406:406:406)) + (PORT datad (310:310:310) (359:359:359)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|flags_xf) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (913:913:913)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (765:765:765) (833:833:833)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[3\]\~33) + (DELAY + (ABSOLUTE + (PORT datab (325:325:325) (374:374:374)) + (PORT datac (602:602:602) (686:686:686)) + (PORT datad (118:118:118) (155:155:155)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sw1_\|db_down\[3\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (471:471:471) (549:549:549)) + (PORT datab (743:743:743) (844:844:844)) + (PORT datac (334:334:334) (403:403:403)) + (PORT datad (354:354:354) (413:413:413)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[3\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (710:710:710) (812:812:812)) + (PORT datab (220:220:220) (260:260:260)) + (PORT datac (173:173:173) (206:206:206)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[3\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (136:136:136)) + (PORT datab (202:202:202) (245:245:245)) + (PORT datac (444:444:444) (515:515:515)) + (PORT datad (118:118:118) (141:141:141)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]\~75) + (DELAY + (ABSOLUTE + (PORT dataa (583:583:583) (701:701:701)) + (PORT datac (630:630:630) (755:755:755)) + (PORT datad (338:338:338) (401:401:401)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|Selector5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (359:359:359) (433:433:433)) + (PORT datab (426:426:426) (494:494:494)) + (PORT datac (250:250:250) (322:322:322)) + (PORT datad (237:237:237) (299:299:299)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|Selector5\~1) + (DELAY + (ABSOLUTE + (PORT dataa (652:652:652) (793:793:793)) + (PORT datab (172:172:172) (233:233:233)) + (PORT datac (531:531:531) (639:639:639)) + (PORT datad (524:524:524) (617:617:617)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~132) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (134:134:134)) + (PORT datab (267:267:267) (343:343:343)) + (PORT datad (455:455:455) (537:537:537)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~106) + (DELAY + (ABSOLUTE + (PORT dataa (251:251:251) (325:325:325)) + (PORT datab (629:629:629) (729:729:729)) + (PORT datac (250:250:250) (323:323:323)) + (PORT datad (104:104:104) (121:121:121)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~107) + (DELAY + (ABSOLUTE + (PORT dataa (260:260:260) (330:330:330)) + (PORT datab (105:105:105) (134:134:134)) + (PORT datac (143:143:143) (190:190:190)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (166:166:166) (173:173:173)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~133) + (DELAY + (ABSOLUTE + (PORT dataa (267:267:267) (338:338:338)) + (PORT datab (150:150:150) (202:202:202)) + (PORT datad (518:518:518) (627:627:627)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~108) + (DELAY + (ABSOLUTE + (PORT dataa (106:106:106) (138:138:138)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datad (105:105:105) (123:123:123)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (911:911:911)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (892:892:892) (897:897:897)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]\~104) + (DELAY + (ABSOLUTE + (PORT dataa (529:529:529) (636:636:636)) + (PORT datac (541:541:541) (644:644:644)) + (PORT datad (545:545:545) (649:649:649)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]\~105) + (DELAY + (ABSOLUTE + (PORT dataa (502:502:502) (577:577:577)) + (PORT datab (391:391:391) (480:480:480)) + (PORT datad (93:93:93) (111:111:111)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (895:895:895) (899:899:899)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~55) + (DELAY + (ABSOLUTE + (PORT dataa (592:592:592) (684:684:684)) + (PORT datab (352:352:352) (434:434:434)) + (PORT datac (116:116:116) (157:157:157)) + (PORT datad (561:561:561) (635:635:635)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (479:479:479) (580:580:580)) + (PORT datab (557:557:557) (669:669:669)) + (PORT datac (346:346:346) (419:419:419)) + (PORT datad (524:524:524) (646:646:646)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~62) + (DELAY + (ABSOLUTE + (PORT datac (382:382:382) (467:467:467)) + (PORT datad (863:863:863) (1010:1010:1010)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]\~102) + (DELAY + (ABSOLUTE + (PORT dataa (517:517:517) (619:619:619)) + (PORT datab (115:115:115) (144:144:144)) + (PORT datac (519:519:519) (614:614:614)) + (PORT datad (114:114:114) (137:137:137)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]\~103) + (DELAY + (ABSOLUTE + (PORT datab (389:389:389) (478:478:478)) + (PORT datad (457:457:457) (524:524:524)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (895:895:895) (899:899:899)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~96) + (DELAY + (ABSOLUTE + (PORT dataa (350:350:350) (422:422:422)) + (PORT datab (845:845:845) (987:987:987)) + (PORT datac (522:522:522) (623:623:623)) + (PORT datad (636:636:636) (745:745:745)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (190:190:190) (177:177:177)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~94) + (DELAY + (ABSOLUTE + (PORT dataa (546:546:546) (649:649:649)) + (PORT datab (511:511:511) (611:611:611)) + (PORT datad (634:634:634) (743:743:743)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]\~95) + (DELAY + (ABSOLUTE + (PORT dataa (882:882:882) (1033:1033:1033)) + (PORT datab (374:374:374) (459:459:459)) + (PORT datac (387:387:387) (474:474:474)) + (PORT datad (537:537:537) (642:642:642)) + (IOPATH dataa combout (158:158:158) (173:173:173)) + (IOPATH datab combout (160:160:160) (176:176:176)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]\~97) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (246:246:246)) + (PORT datab (203:203:203) (240:240:240)) + (PORT datad (185:185:185) (216:216:216)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (895:895:895) (899:899:899)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~45) + (DELAY + (ABSOLUTE + (PORT dataa (663:663:663) (781:781:781)) + (PORT datac (540:540:540) (643:643:643)) + (PORT datad (1242:1242:1242) (1453:1453:1453)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]\~92) + (DELAY + (ABSOLUTE + (PORT dataa (124:124:124) (158:158:158)) + (PORT datab (335:335:335) (393:393:393)) + (PORT datac (375:375:375) (451:451:451)) + (PORT datad (542:542:542) (646:646:646)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]\~93) + (DELAY + (ABSOLUTE + (PORT dataa (532:532:532) (640:640:640)) + (PORT datab (389:389:389) (479:479:479)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (895:895:895) (899:899:899)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~53) + (DELAY + (ABSOLUTE + (PORT dataa (369:369:369) (447:447:447)) + (PORT datab (343:343:343) (397:397:397)) + (PORT datac (116:116:116) (157:157:157)) + (PORT datad (580:580:580) (664:664:664)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~99) + (DELAY + (ABSOLUTE + (PORT datab (537:537:537) (665:665:665)) + (PORT datac (515:515:515) (610:610:610)) + (PORT datad (533:533:533) (637:637:637)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~100) + (DELAY + (ABSOLUTE + (PORT dataa (107:107:107) (139:139:139)) + (PORT datab (128:128:128) (161:161:161)) + (PORT datac (520:520:520) (616:616:616)) + (PORT datad (360:360:360) (435:435:435)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~98) + (DELAY + (ABSOLUTE + (PORT dataa (543:543:543) (646:646:646)) + (PORT datac (522:522:522) (624:624:624)) + (PORT datad (495:495:495) (589:589:589)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~101) + (DELAY + (ABSOLUTE + (PORT dataa (350:350:350) (422:422:422)) + (PORT datab (341:341:341) (392:392:392)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (895:895:895) (899:899:899)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1496:1496:1496) (1753:1753:1753)) + (PORT datab (800:800:800) (932:932:932)) + (PORT datad (350:350:350) (420:420:420)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~54) + (DELAY + (ABSOLUTE + (PORT dataa (131:131:131) (181:181:181)) + (PORT datab (105:105:105) (133:133:133)) + (PORT datac (559:559:559) (645:645:645)) + (PORT datad (164:164:164) (193:193:193)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~109) + (DELAY + (ABSOLUTE + (PORT datab (524:524:524) (614:614:614)) + (PORT datac (545:545:545) (654:654:654)) + (PORT datad (618:618:618) (723:723:723)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~60) + (DELAY + (ABSOLUTE + (PORT datab (556:556:556) (672:672:672)) + (PORT datac (545:545:545) (654:654:654)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]\~110) + (DELAY + (ABSOLUTE + (PORT dataa (110:110:110) (142:142:142)) + (PORT datab (688:688:688) (807:807:807)) + (PORT datac (459:459:459) (529:529:529)) + (PORT datad (108:108:108) (127:127:127)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]\~111) + (DELAY + (ABSOLUTE + (PORT dataa (469:469:469) (546:546:546)) + (PORT datab (583:583:583) (689:689:689)) + (PORT datac (162:162:162) (190:190:190)) + (PORT datad (397:397:397) (482:482:482)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]\~112) + (DELAY + (ABSOLUTE + (PORT dataa (118:118:118) (150:150:150)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (895:895:895) (899:899:899)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|Selector13\~0) + (DELAY + (ABSOLUTE + (PORT dataa (841:841:841) (982:982:982)) + (PORT datab (502:502:502) (586:586:586)) + (PORT datad (493:493:493) (587:587:587)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~113) + (DELAY + (ABSOLUTE + (PORT dataa (564:564:564) (682:682:682)) + (PORT datab (687:687:687) (806:806:806)) + (PORT datac (540:540:540) (650:650:650)) + (PORT datad (395:395:395) (480:480:480)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~114) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (136:136:136)) + (PORT datab (413:413:413) (504:504:504)) + (PORT datac (179:179:179) (208:208:208)) + (PORT datad (526:526:526) (621:621:621)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~135) + (DELAY + (ABSOLUTE + (PORT dataa (468:468:468) (545:545:545)) + (PORT datab (581:581:581) (687:687:687)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~136) + (DELAY + (ABSOLUTE + (PORT dataa (181:181:181) (220:220:220)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datad (491:491:491) (576:576:576)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (895:895:895) (899:899:899)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~56) + (DELAY + (ABSOLUTE + (PORT dataa (911:911:911) (1087:1087:1087)) + (PORT datab (131:131:131) (178:178:178)) + (PORT datac (118:118:118) (159:159:159)) + (PORT datad (335:335:335) (393:393:393)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~57) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (136:136:136)) + (PORT datab (102:102:102) (131:131:131)) + (PORT datac (460:460:460) (532:532:532)) + (PORT datad (316:316:316) (365:365:365)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (552:552:552) (619:619:619)) + (PORT clk (1097:1097:1097) (1114:1114:1114)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1848:1848:1848) (2156:2156:2156)) + (PORT d[1] (917:917:917) (1057:1057:1057)) + (PORT d[2] (551:551:551) (644:644:644)) + (PORT d[3] (1921:1921:1921) (2245:2245:2245)) + (PORT d[4] (574:574:574) (658:658:658)) + (PORT d[5] (830:830:830) (948:948:948)) + (PORT d[6] (560:560:560) (644:644:644)) + (PORT d[7] (1658:1658:1658) (1935:1935:1935)) + (PORT d[8] (2089:2089:2089) (2375:2375:2375)) + (PORT d[9] (645:645:645) (740:740:740)) + (PORT d[10] (2634:2634:2634) (3062:3062:3062)) + (PORT d[11] (2244:2244:2244) (2607:2607:2607)) + (PORT d[12] (653:653:653) (753:753:753)) + (PORT clk (1095:1095:1095) (1112:1112:1112)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (819:819:819) (879:879:879)) + (PORT clk (1095:1095:1095) (1112:1112:1112)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1114:1114:1114)) + (PORT d[0] (1333:1333:1333) (1438:1438:1438)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1077:1077:1077) (1093:1093:1093)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (617:617:617) (625:625:625)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (618:618:618) (626:626:626)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (618:618:618) (626:626:626)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (618:618:618) (626:626:626)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (365:365:365) (425:425:425)) + (PORT clk (1092:1092:1092) (1109:1109:1109)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (834:834:834) (968:968:968)) + (PORT d[1] (2810:2810:2810) (3210:3210:3210)) + (PORT d[2] (1715:1715:1715) (1994:1994:1994)) + (PORT d[3] (1052:1052:1052) (1227:1227:1227)) + (PORT d[4] (812:812:812) (939:939:939)) + (PORT d[5] (953:953:953) (1094:1094:1094)) + (PORT d[6] (891:891:891) (1044:1044:1044)) + (PORT d[7] (1229:1229:1229) (1430:1430:1430)) + (PORT d[8] (1666:1666:1666) (1921:1921:1921)) + (PORT d[9] (1620:1620:1620) (1895:1895:1895)) + (PORT d[10] (1526:1526:1526) (1778:1778:1778)) + (PORT d[11] (1298:1298:1298) (1510:1510:1510)) + (PORT d[12] (1719:1719:1719) (1956:1956:1956)) + (PORT clk (1090:1090:1090) (1107:1107:1107)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1286:1286:1286) (1421:1421:1421)) + (PORT clk (1090:1090:1090) (1107:1107:1107)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1109:1109:1109)) + (PORT d[0] (1076:1076:1076) (1144:1144:1144)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1093:1093:1093) (1110:1110:1110)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1093:1093:1093) (1110:1110:1110)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1093:1093:1093) (1110:1110:1110)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1093:1093:1093) (1110:1110:1110)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1072:1072:1072) (1088:1088:1088)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (620:620:620)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (621:621:621)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (621:621:621)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (621:621:621)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (515:515:515) (593:593:593)) + (PORT clk (1091:1091:1091) (1108:1108:1108)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (823:823:823) (956:956:956)) + (PORT d[1] (1076:1076:1076) (1252:1252:1252)) + (PORT d[2] (1110:1110:1110) (1292:1292:1292)) + (PORT d[3] (1032:1032:1032) (1192:1192:1192)) + (PORT d[4] (975:975:975) (1124:1124:1124)) + (PORT d[5] (778:778:778) (892:892:892)) + (PORT d[6] (953:953:953) (1095:1095:1095)) + (PORT d[7] (1045:1045:1045) (1216:1216:1216)) + (PORT d[8] (1647:1647:1647) (1895:1895:1895)) + (PORT d[9] (1794:1794:1794) (2092:2092:2092)) + (PORT d[10] (1027:1027:1027) (1200:1200:1200)) + (PORT d[11] (1281:1281:1281) (1484:1484:1484)) + (PORT d[12] (1552:1552:1552) (1765:1765:1765)) + (PORT clk (1089:1089:1089) (1106:1106:1106)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (964:964:964) (1053:1053:1053)) + (PORT clk (1089:1089:1089) (1106:1106:1106)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1108:1108:1108)) + (PORT d[0] (974:974:974) (1023:1023:1023)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1071:1071:1071) (1087:1087:1087)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (611:611:611) (619:619:619)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (620:620:620)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (620:620:620)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (620:620:620)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[3\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (414:414:414) (503:503:503)) + (PORT datab (349:349:349) (398:398:398)) + (PORT datad (497:497:497) (558:558:558)) + (IOPATH dataa combout (188:188:188) (193:193:193)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (537:537:537) (619:619:619)) + (PORT clk (1092:1092:1092) (1110:1110:1110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (996:996:996) (1159:1159:1159)) + (PORT d[1] (2624:2624:2624) (2994:2994:2994)) + (PORT d[2] (973:973:973) (1159:1159:1159)) + (PORT d[3] (1657:1657:1657) (1927:1927:1927)) + (PORT d[4] (2381:2381:2381) (2735:2735:2735)) + (PORT d[5] (965:965:965) (1115:1115:1115)) + (PORT d[6] (2081:2081:2081) (2394:2394:2394)) + (PORT d[7] (1248:1248:1248) (1449:1449:1449)) + (PORT d[8] (1606:1606:1606) (1854:1854:1854)) + (PORT d[9] (1620:1620:1620) (1894:1894:1894)) + (PORT d[10] (1518:1518:1518) (1769:1769:1769)) + (PORT d[11] (1096:1096:1096) (1279:1279:1279)) + (PORT d[12] (2116:2116:2116) (2411:2411:2411)) + (PORT clk (1090:1090:1090) (1108:1108:1108)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (822:822:822) (890:890:890)) + (PORT clk (1090:1090:1090) (1108:1108:1108)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1110:1110:1110)) + (PORT d[0] (1431:1431:1431) (1574:1574:1574)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1093:1093:1093) (1111:1111:1111)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1093:1093:1093) (1111:1111:1111)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1093:1093:1093) (1111:1111:1111)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1093:1093:1093) (1111:1111:1111)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1072:1072:1072) (1089:1089:1089)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (621:621:621)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (622:622:622)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (622:622:622)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (622:622:622)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[3\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (858:858:858) (1010:1010:1010)) + (PORT datab (579:579:579) (662:662:662)) + (PORT datac (89:89:89) (110:110:110)) + (PORT datad (513:513:513) (583:583:583)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1952:1952:1952) (2282:2282:2282)) + (PORT d[1] (2442:2442:2442) (2791:2791:2791)) + (PORT d[2] (1354:1354:1354) (1583:1583:1583)) + (PORT d[3] (1463:1463:1463) (1704:1704:1704)) + (PORT d[4] (2339:2339:2339) (2682:2682:2682)) + (PORT d[5] (1179:1179:1179) (1368:1368:1368)) + (PORT d[6] (1867:1867:1867) (2148:2148:2148)) + (PORT d[7] (1883:1883:1883) (2173:2173:2173)) + (PORT d[8] (1415:1415:1415) (1637:1637:1637)) + (PORT d[9] (1615:1615:1615) (1891:1891:1891)) + (PORT d[10] (1347:1347:1347) (1585:1585:1585)) + (PORT d[11] (1323:1323:1323) (1541:1541:1541)) + (PORT d[12] (1938:1938:1938) (2209:2209:2209)) + (PORT clk (1088:1088:1088) (1105:1105:1105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1088:1088:1088) (1105:1105:1105)) + (PORT d[0] (2952:2952:2952) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1089:1089:1089) (1106:1106:1106)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1070:1070:1070) (1086:1086:1086)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (610:610:610) (618:618:618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (611:611:611) (619:619:619)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (611:611:611) (619:619:619)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (611:611:611) (619:619:619)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1471:1471:1471) (1700:1700:1700)) + (PORT d[1] (1628:1628:1628) (1869:1869:1869)) + (PORT d[2] (1186:1186:1186) (1376:1376:1376)) + (PORT d[3] (1382:1382:1382) (1604:1604:1604)) + (PORT d[4] (1330:1330:1330) (1537:1537:1537)) + (PORT d[5] (1341:1341:1341) (1573:1573:1573)) + (PORT d[6] (1868:1868:1868) (2140:2140:2140)) + (PORT d[7] (1175:1175:1175) (1362:1362:1362)) + (PORT d[8] (1341:1341:1341) (1546:1546:1546)) + (PORT d[9] (1764:1764:1764) (2046:2046:2046)) + (PORT d[10] (2355:2355:2355) (2734:2734:2734)) + (PORT d[11] (1290:1290:1290) (1490:1490:1490)) + (PORT d[12] (1551:1551:1551) (1763:1763:1763)) + (PORT clk (1099:1099:1099) (1117:1117:1117)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1099:1099:1099) (1117:1117:1117)) + (PORT d[0] (2095:2095:2095) (2322:2322:2322)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1100:1100:1100) (1118:1118:1118)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1081:1081:1081) (1098:1098:1098)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (621:621:621) (630:630:630)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (622:622:622) (631:631:631)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (622:622:622) (631:631:631)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (622:622:622) (631:631:631)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (915:915:915) (1064:1064:1064)) + (PORT clk (1087:1087:1087) (1105:1105:1105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1793:1793:1793) (2104:2104:2104)) + (PORT d[1] (2284:2284:2284) (2608:2608:2608)) + (PORT d[2] (1189:1189:1189) (1396:1396:1396)) + (PORT d[3] (1263:1263:1263) (1474:1474:1474)) + (PORT d[4] (2171:2171:2171) (2496:2496:2496)) + (PORT d[5] (1353:1353:1353) (1565:1565:1565)) + (PORT d[6] (1719:1719:1719) (1985:1985:1985)) + (PORT d[7] (1721:1721:1721) (1990:1990:1990)) + (PORT d[8] (1397:1397:1397) (1612:1612:1612)) + (PORT d[9] (1416:1416:1416) (1668:1668:1668)) + (PORT d[10] (1771:1771:1771) (2064:2064:2064)) + (PORT d[11] (1305:1305:1305) (1518:1518:1518)) + (PORT d[12] (1764:1764:1764) (2010:2010:2010)) + (PORT clk (1085:1085:1085) (1103:1103:1103)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1154:1154:1154) (1262:1262:1262)) + (PORT clk (1085:1085:1085) (1103:1103:1103)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1087:1087:1087) (1105:1105:1105)) + (PORT d[0] (3140:3140:3140) (3457:3457:3457)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1088:1088:1088) (1106:1106:1106)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1088:1088:1088) (1106:1106:1106)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1088:1088:1088) (1106:1106:1106)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1088:1088:1088) (1106:1106:1106)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1042:1042:1042) (1062:1062:1062)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1233:1233:1233) (1449:1449:1449)) + (PORT clk (1047:1047:1047) (1065:1065:1065)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2339:2339:2339) (2678:2678:2678)) + (PORT d[1] (2414:2414:2414) (2752:2752:2752)) + (PORT d[2] (2324:2324:2324) (2645:2645:2645)) + (PORT d[3] (2381:2381:2381) (2734:2734:2734)) + (PORT d[4] (2324:2324:2324) (2654:2654:2654)) + (PORT d[5] (2423:2423:2423) (2770:2770:2770)) + (PORT d[6] (2277:2277:2277) (2566:2566:2566)) + (PORT d[7] (2278:2278:2278) (2602:2602:2602)) + (PORT d[8] (2367:2367:2367) (2674:2674:2674)) + (PORT d[9] (2314:2314:2314) (2637:2637:2637)) + (PORT d[10] (2324:2324:2324) (2642:2642:2642)) + (PORT d[11] (2405:2405:2405) (2727:2727:2727)) + (PORT d[12] (2348:2348:2348) (2649:2649:2649)) + (PORT clk (1044:1044:1044) (1064:1064:1064)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1047:1047:1047) (1065:1065:1065)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1048:1048:1048) (1066:1066:1066)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1048:1048:1048) (1066:1066:1066)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1048:1048:1048) (1066:1066:1066)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1048:1048:1048) (1066:1066:1066)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (939:939:939) (1086:1086:1086)) + (PORT clk (1099:1099:1099) (1117:1117:1117)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1718:1718:1718) (1972:1972:1972)) + (PORT d[1] (1941:1941:1941) (2211:2211:2211)) + (PORT d[2] (1354:1354:1354) (1580:1580:1580)) + (PORT d[3] (1363:1363:1363) (1582:1582:1582)) + (PORT d[4] (1521:1521:1521) (1757:1757:1757)) + (PORT d[5] (1512:1512:1512) (1763:1763:1763)) + (PORT d[6] (2147:2147:2147) (2461:2461:2461)) + (PORT d[7] (1189:1189:1189) (1387:1387:1387)) + (PORT d[8] (1465:1465:1465) (1680:1680:1680)) + (PORT d[9] (1748:1748:1748) (2029:2029:2029)) + (PORT d[10] (2224:2224:2224) (2591:2591:2591)) + (PORT d[11] (1493:1493:1493) (1724:1724:1724)) + (PORT d[12] (1711:1711:1711) (1943:1943:1943)) + (PORT clk (1097:1097:1097) (1115:1115:1115)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1470:1470:1470) (1623:1623:1623)) + (PORT clk (1097:1097:1097) (1115:1115:1115)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1099:1099:1099) (1117:1117:1117)) + (PORT d[0] (3052:3052:3052) (2804:2804:2804)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1100:1100:1100) (1118:1118:1118)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1100:1100:1100) (1118:1118:1118)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1100:1100:1100) (1118:1118:1118)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1100:1100:1100) (1118:1118:1118)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1054:1054:1054) (1074:1074:1074)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (552:552:552) (644:644:644)) + (PORT clk (1059:1059:1059) (1077:1077:1077)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2323:2323:2323) (2632:2632:2632)) + (PORT d[1] (2383:2383:2383) (2706:2706:2706)) + (PORT d[2] (2359:2359:2359) (2670:2670:2670)) + (PORT d[3] (2312:2312:2312) (2642:2642:2642)) + (PORT d[4] (2351:2351:2351) (2669:2669:2669)) + (PORT d[5] (2397:2397:2397) (2741:2741:2741)) + (PORT d[6] (2311:2311:2311) (2618:2618:2618)) + (PORT d[7] (2278:2278:2278) (2601:2601:2601)) + (PORT d[8] (2427:2427:2427) (2760:2760:2760)) + (PORT d[9] (2294:2294:2294) (2610:2610:2610)) + (PORT d[10] (2344:2344:2344) (2682:2682:2682)) + (PORT d[11] (2307:2307:2307) (2602:2602:2602)) + (PORT d[12] (2359:2359:2359) (2674:2674:2674)) + (PORT clk (1056:1056:1056) (1076:1076:1076)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1059:1059:1059) (1077:1077:1077)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1060:1060:1060) (1078:1078:1078)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1060:1060:1060) (1078:1078:1078)) + (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1060:1060:1060) (1078:1078:1078)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1060:1060:1060) (1078:1078:1078)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1055:1055:1055) (1075:1075:1075)) + (IOPATH (posedge clk) q (164:164:164) (166:166:166)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector3\~1) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (406:406:406)) + (PORT datab (973:973:973) (1119:1119:1119)) + (PORT datac (709:709:709) (809:809:809)) + (PORT datad (852:852:852) (980:980:980)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector3\~2) + (DELAY + (ABSOLUTE + (PORT dataa (741:741:741) (855:855:855)) + (PORT datab (971:971:971) (1118:1118:1118)) + (PORT datac (971:971:971) (1105:1105:1105)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~85) + (DELAY + (ABSOLUTE + (PORT dataa (1061:1061:1061) (1273:1273:1273)) + (PORT datab (1740:1740:1740) (2028:2028:2028)) + (PORT datac (90:90:90) (112:112:112)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (181:181:181) (175:175:175)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~73) + (DELAY + (ABSOLUTE + (PORT dataa (1239:1239:1239) (1411:1411:1411)) + (PORT datab (889:889:889) (1013:1013:1013)) + (PORT datac (622:622:622) (731:731:731)) + (PORT datad (94:94:94) (112:112:112)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~74) + (DELAY + (ABSOLUTE + (PORT dataa (1072:1072:1072) (1243:1243:1243)) + (PORT datab (887:887:887) (1011:1011:1011)) + (PORT datac (900:900:900) (1032:1032:1032)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[3\]) + (DELAY + (ABSOLUTE + (PORT dataa (796:796:796) (913:913:913)) + (PORT datab (208:208:208) (252:252:252)) + (PORT datac (455:455:455) (523:523:523)) + (PORT datad (831:831:831) (934:934:934)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (917:917:917) (904:904:904)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (421:421:421) (449:449:449)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[3\]\~20) + (DELAY + (ABSOLUTE + (PORT datab (187:187:187) (228:228:228)) + (PORT datac (174:174:174) (208:208:208)) + (PORT datad (198:198:198) (243:243:243)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[3\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (396:396:396) (471:471:471)) + (PORT datab (376:376:376) (448:448:448)) + (PORT datac (335:335:335) (389:389:389)) + (PORT datad (935:935:935) (1064:1064:1064)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\~2) + (DELAY + (ABSOLUTE + (PORT datab (147:147:147) (187:187:187)) + (PORT datac (138:138:138) (180:180:180)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|interrupts_\|im2) + (DELAY + (ABSOLUTE + (PORT clk (920:920:920) (928:928:928)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (909:909:909) (896:896:896)) + (PORT ena (781:781:781) (861:861:861)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~10) + (DELAY + (ABSOLUTE + (PORT dataa (254:254:254) (331:331:331)) + (PORT datab (485:485:485) (578:578:578)) + (PORT datac (151:151:151) (203:203:203)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_mask543_en\~0) + (DELAY + (ABSOLUTE + (PORT dataa (258:258:258) (336:336:336)) + (PORT datab (115:115:115) (144:144:144)) + (PORT datac (330:330:330) (371:371:371)) + (PORT datad (471:471:471) (550:550:550)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[7\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (770:770:770) (927:927:927)) + (PORT datab (302:302:302) (357:357:357)) + (PORT datac (444:444:444) (509:509:509)) + (PORT datad (282:282:282) (326:326:326)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[7\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (496:496:496) (581:581:581)) + (PORT datab (186:186:186) (223:223:223)) + (PORT datac (292:292:292) (337:337:337)) + (PORT datad (108:108:108) (127:127:127)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[7\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (456:456:456) (531:531:531)) + (PORT datab (356:356:356) (417:417:417)) + (PORT datac (215:215:215) (261:261:261)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[7\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (135:135:135)) + (PORT datad (187:187:187) (219:219:219)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[7\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (777:777:777) (886:886:886)) + (PORT datab (187:187:187) (229:229:229)) + (PORT datad (737:737:737) (837:837:837)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[5\]\~67) + (DELAY + (ABSOLUTE + (PORT dataa (136:136:136) (175:175:175)) + (PORT datab (1545:1545:1545) (1818:1818:1818)) + (PORT datac (290:290:290) (334:334:334)) + (PORT datad (313:313:313) (370:370:370)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (231:231:231) (263:263:263)) + (PORT clk (1095:1095:1095) (1112:1112:1112)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1911:1911:1911) (2219:2219:2219)) + (PORT d[1] (895:895:895) (1028:1028:1028)) + (PORT d[2] (1072:1072:1072) (1231:1231:1231)) + (PORT d[3] (1535:1535:1535) (1805:1805:1805)) + (PORT d[4] (1864:1864:1864) (2139:2139:2139)) + (PORT d[5] (2265:2265:2265) (2598:2598:2598)) + (PORT d[6] (926:926:926) (1067:1067:1067)) + (PORT d[7] (1306:1306:1306) (1533:1533:1533)) + (PORT d[8] (1728:1728:1728) (1966:1966:1966)) + (PORT d[9] (1009:1009:1009) (1162:1162:1162)) + (PORT d[10] (2412:2412:2412) (2801:2801:2801)) + (PORT d[11] (2047:2047:2047) (2379:2379:2379)) + (PORT d[12] (1007:1007:1007) (1154:1154:1154)) + (PORT clk (1093:1093:1093) (1110:1110:1110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1016:1016:1016) (1104:1104:1104)) + (PORT clk (1093:1093:1093) (1110:1110:1110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1095:1095:1095) (1112:1112:1112)) + (PORT d[0] (1506:1506:1506) (1610:1610:1610)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1096:1096:1096) (1113:1113:1113)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1096:1096:1096) (1113:1113:1113)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1096:1096:1096) (1113:1113:1113)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1096:1096:1096) (1113:1113:1113)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1075:1075:1075) (1091:1091:1091)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (615:615:615) (623:623:623)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (616:616:616) (624:624:624)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (616:616:616) (624:624:624)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (616:616:616) (624:624:624)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (388:388:388) (438:438:438)) + (PORT clk (1096:1096:1096) (1112:1112:1112)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2073:2073:2073) (2402:2402:2402)) + (PORT d[1] (909:909:909) (1056:1056:1056)) + (PORT d[2] (910:910:910) (1057:1057:1057)) + (PORT d[3] (1710:1710:1710) (2001:2001:2001)) + (PORT d[4] (2027:2027:2027) (2323:2323:2323)) + (PORT d[5] (2283:2283:2283) (2621:2621:2621)) + (PORT d[6] (922:922:922) (1061:1061:1061)) + (PORT d[7] (1320:1320:1320) (1553:1553:1553)) + (PORT d[8] (1896:1896:1896) (2158:2158:2158)) + (PORT d[9] (1024:1024:1024) (1184:1184:1184)) + (PORT d[10] (2419:2419:2419) (2808:2808:2808)) + (PORT d[11] (2054:2054:2054) (2386:2386:2386)) + (PORT d[12] (990:990:990) (1133:1133:1133)) + (PORT clk (1094:1094:1094) (1110:1110:1110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1036:1036:1036) (1131:1131:1131)) + (PORT clk (1094:1094:1094) (1110:1110:1110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1096:1096:1096) (1112:1112:1112)) + (PORT d[0] (1423:1423:1423) (1541:1541:1541)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1113:1113:1113)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1113:1113:1113)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1113:1113:1113)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1113:1113:1113)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1076:1076:1076) (1091:1091:1091)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (616:616:616) (623:623:623)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (617:617:617) (624:624:624)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (617:617:617) (624:624:624)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (617:617:617) (624:624:624)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (428:428:428) (492:492:492)) + (PORT datab (814:814:814) (952:952:952)) + (PORT datac (465:465:465) (534:534:534)) + (PORT datad (822:822:822) (959:959:959)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (394:394:394) (452:452:452)) + (PORT clk (1097:1097:1097) (1114:1114:1114)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2093:2093:2093) (2425:2425:2425)) + (PORT d[1] (735:735:735) (851:851:851)) + (PORT d[2] (725:725:725) (841:841:841)) + (PORT d[3] (1732:1732:1732) (2021:2021:2021)) + (PORT d[4] (2033:2033:2033) (2327:2327:2327)) + (PORT d[5] (2434:2434:2434) (2790:2790:2790)) + (PORT d[6] (759:759:759) (876:876:876)) + (PORT d[7] (1482:1482:1482) (1736:1736:1736)) + (PORT d[8] (1914:1914:1914) (2176:2176:2176)) + (PORT d[9] (1149:1149:1149) (1323:1323:1323)) + (PORT d[10] (2437:2437:2437) (2838:2838:2838)) + (PORT d[11] (2057:2057:2057) (2394:2394:2394)) + (PORT d[12] (850:850:850) (977:977:977)) + (PORT clk (1095:1095:1095) (1112:1112:1112)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (839:839:839) (899:899:899)) + (PORT clk (1095:1095:1095) (1112:1112:1112)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1114:1114:1114)) + (PORT d[0] (1493:1493:1493) (1620:1620:1620)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1077:1077:1077) (1093:1093:1093)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (617:617:617) (625:625:625)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (618:618:618) (626:626:626)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (618:618:618) (626:626:626)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (618:618:618) (626:626:626)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (573:573:573) (647:647:647)) + (PORT clk (1098:1098:1098) (1115:1115:1115)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1709:1709:1709) (2003:2003:2003)) + (PORT d[1] (713:713:713) (828:828:828)) + (PORT d[2] (721:721:721) (844:844:844)) + (PORT d[3] (1922:1922:1922) (2249:2249:2249)) + (PORT d[4] (2208:2208:2208) (2525:2525:2525)) + (PORT d[5] (826:826:826) (940:940:940)) + (PORT d[6] (746:746:746) (860:860:860)) + (PORT d[7] (1505:1505:1505) (1767:1767:1767)) + (PORT d[8] (1907:1907:1907) (2169:2169:2169)) + (PORT d[9] (844:844:844) (971:971:971)) + (PORT d[10] (2612:2612:2612) (3033:3033:3033)) + (PORT d[11] (2238:2238:2238) (2603:2603:2603)) + (PORT d[12] (837:837:837) (963:963:963)) + (PORT clk (1096:1096:1096) (1113:1113:1113)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (900:900:900) (968:968:968)) + (PORT clk (1096:1096:1096) (1113:1113:1113)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (PORT d[0] (1379:1379:1379) (1478:1478:1478)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1099:1099:1099) (1116:1116:1116)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1099:1099:1099) (1116:1116:1116)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1099:1099:1099) (1116:1116:1116)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1099:1099:1099) (1116:1116:1116)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1078:1078:1078) (1094:1094:1094)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (618:618:618) (626:626:626)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (619:619:619) (627:627:627)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (619:619:619) (627:627:627)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (619:619:619) (627:627:627)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (136:136:136)) + (PORT datab (639:639:639) (742:742:742)) + (PORT datac (1003:1003:1003) (1167:1167:1167)) + (PORT datad (744:744:744) (843:843:843)) + (IOPATH dataa combout (172:172:172) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1426:1426:1426) (1675:1675:1675)) + (PORT d[1] (1555:1555:1555) (1783:1783:1783)) + (PORT d[2] (1289:1289:1289) (1493:1493:1493)) + (PORT d[3] (1332:1332:1332) (1567:1567:1567)) + (PORT d[4] (1503:1503:1503) (1729:1729:1729)) + (PORT d[5] (1647:1647:1647) (1899:1899:1899)) + (PORT d[6] (1551:1551:1551) (1772:1772:1772)) + (PORT d[7] (1133:1133:1133) (1339:1339:1339)) + (PORT d[8] (1369:1369:1369) (1553:1553:1553)) + (PORT d[9] (1668:1668:1668) (1921:1921:1921)) + (PORT d[10] (2513:2513:2513) (2917:2917:2917)) + (PORT d[11] (1666:1666:1666) (1942:1942:1942)) + (PORT d[12] (1363:1363:1363) (1563:1563:1563)) + (PORT clk (1102:1102:1102) (1118:1118:1118)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1102:1102:1102) (1118:1118:1118)) + (PORT d[0] (1574:1574:1574) (1746:1746:1746)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1103:1103:1103) (1119:1119:1119)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1084:1084:1084) (1099:1099:1099)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (624:624:624) (631:631:631)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (625:625:625) (632:632:632)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (625:625:625) (632:632:632)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (625:625:625) (632:632:632)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (589:589:589) (663:663:663)) + (PORT clk (1091:1091:1091) (1109:1109:1109)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1912:1912:1912) (2223:2223:2223)) + (PORT d[1] (1103:1103:1103) (1281:1281:1281)) + (PORT d[2] (1094:1094:1094) (1266:1266:1266)) + (PORT d[3] (1702:1702:1702) (1994:1994:1994)) + (PORT d[4] (1857:1857:1857) (2133:2133:2133)) + (PORT d[5] (2095:2095:2095) (2406:2406:2406)) + (PORT d[6] (1884:1884:1884) (2141:2141:2141)) + (PORT d[7] (1288:1288:1288) (1515:1515:1515)) + (PORT d[8] (1709:1709:1709) (1945:1945:1945)) + (PORT d[9] (1933:1933:1933) (2216:2216:2216)) + (PORT d[10] (2400:2400:2400) (2791:2791:2791)) + (PORT d[11] (1877:1877:1877) (2190:2190:2190)) + (PORT d[12] (1171:1171:1171) (1346:1346:1346)) + (PORT clk (1089:1089:1089) (1107:1107:1107)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1775:1775:1775) (1948:1948:1948)) + (PORT clk (1089:1089:1089) (1107:1107:1107)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1109:1109:1109)) + (PORT d[0] (1717:1717:1717) (1856:1856:1856)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1110:1110:1110)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1110:1110:1110)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1110:1110:1110)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1110:1110:1110)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1046:1046:1046) (1066:1066:1066)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1409:1409:1409) (1644:1644:1644)) + (PORT clk (1051:1051:1051) (1069:1069:1069)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2344:2344:2344) (2647:2647:2647)) + (PORT d[1] (2432:2432:2432) (2753:2753:2753)) + (PORT d[2] (2312:2312:2312) (2614:2614:2614)) + (PORT d[3] (2332:2332:2332) (2657:2657:2657)) + (PORT d[4] (2325:2325:2325) (2649:2649:2649)) + (PORT d[5] (2387:2387:2387) (2732:2732:2732)) + (PORT d[6] (2321:2321:2321) (2622:2622:2622)) + (PORT d[7] (2260:2260:2260) (2571:2571:2571)) + (PORT d[8] (2392:2392:2392) (2702:2702:2702)) + (PORT d[9] (2412:2412:2412) (2726:2726:2726)) + (PORT d[10] (2358:2358:2358) (2681:2681:2681)) + (PORT d[11] (2395:2395:2395) (2715:2715:2715)) + (PORT d[12] (2318:2318:2318) (2623:2623:2623)) + (PORT clk (1048:1048:1048) (1068:1068:1068)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1051:1051:1051) (1069:1069:1069)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1052:1052:1052) (1070:1070:1070)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1052:1052:1052) (1070:1070:1070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1052:1052:1052) (1070:1070:1070)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1052:1052:1052) (1070:1070:1070)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (656:656:656) (743:743:743)) + (PORT clk (1089:1089:1089) (1107:1107:1107)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1889:1889:1889) (2193:2193:2193)) + (PORT d[1] (1714:1714:1714) (1968:1968:1968)) + (PORT d[2] (1097:1097:1097) (1273:1273:1273)) + (PORT d[3] (1354:1354:1354) (1596:1596:1596)) + (PORT d[4] (1850:1850:1850) (2124:2124:2124)) + (PORT d[5] (2094:2094:2094) (2405:2405:2405)) + (PORT d[6] (1353:1353:1353) (1544:1544:1544)) + (PORT d[7] (1251:1251:1251) (1466:1466:1466)) + (PORT d[8] (1502:1502:1502) (1716:1716:1716)) + (PORT d[9] (1281:1281:1281) (1466:1466:1466)) + (PORT d[10] (2237:2237:2237) (2602:2602:2602)) + (PORT d[11] (1863:1863:1863) (2171:2171:2171)) + (PORT d[12] (1172:1172:1172) (1343:1343:1343)) + (PORT clk (1087:1087:1087) (1105:1105:1105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1248:1248:1248) (1355:1355:1355)) + (PORT clk (1087:1087:1087) (1105:1105:1105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1089:1089:1089) (1107:1107:1107)) + (PORT d[0] (1843:1843:1843) (1732:1732:1732)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1108:1108:1108)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1108:1108:1108)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1108:1108:1108)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1108:1108:1108)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1044:1044:1044) (1064:1064:1064)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1543:1543:1543) (1798:1798:1798)) + (PORT clk (1049:1049:1049) (1067:1067:1067)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2324:2324:2324) (2621:2621:2621)) + (PORT d[1] (2316:2316:2316) (2613:2613:2613)) + (PORT d[2] (2387:2387:2387) (2723:2723:2723)) + (PORT d[3] (2302:2302:2302) (2634:2634:2634)) + (PORT d[4] (2323:2323:2323) (2643:2643:2643)) + (PORT d[5] (2429:2429:2429) (2760:2760:2760)) + (PORT d[6] (2349:2349:2349) (2658:2658:2658)) + (PORT d[7] (2327:2327:2327) (2620:2620:2620)) + (PORT d[8] (2394:2394:2394) (2698:2698:2698)) + (PORT d[9] (2422:2422:2422) (2743:2743:2743)) + (PORT d[10] (2352:2352:2352) (2669:2669:2669)) + (PORT d[11] (2402:2402:2402) (2722:2722:2722)) + (PORT d[12] (2290:2290:2290) (2609:2609:2609)) + (PORT clk (1046:1046:1046) (1066:1066:1066)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1049:1049:1049) (1067:1067:1067)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1050:1050:1050) (1068:1068:1068)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1050:1050:1050) (1068:1068:1068)) + (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1050:1050:1050) (1068:1068:1068)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1050:1050:1050) (1068:1068:1068)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1045:1045:1045) (1065:1065:1065)) + (IOPATH (posedge clk) q (164:164:164) (166:166:166)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Mux0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (970:970:970) (1159:1159:1159)) + (PORT datab (370:370:370) (435:435:435)) + (PORT datac (468:468:468) (532:532:532)) + (PORT datad (678:678:678) (787:787:787)) + (IOPATH dataa combout (172:172:172) (165:165:165)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1601:1601:1601) (1869:1869:1869)) + (PORT d[1] (1403:1403:1403) (1607:1607:1607)) + (PORT d[2] (1436:1436:1436) (1652:1652:1652)) + (PORT d[3] (1505:1505:1505) (1760:1760:1760)) + (PORT d[4] (1352:1352:1352) (1555:1555:1555)) + (PORT d[5] (1469:1469:1469) (1699:1699:1699)) + (PORT d[6] (1445:1445:1445) (1648:1648:1648)) + (PORT d[7] (1288:1288:1288) (1511:1511:1511)) + (PORT d[8] (1197:1197:1197) (1364:1364:1364)) + (PORT d[9] (1684:1684:1684) (1938:1938:1938)) + (PORT d[10] (2345:2345:2345) (2729:2729:2729)) + (PORT d[11] (1445:1445:1445) (1648:1648:1648)) + (PORT d[12] (1586:1586:1586) (1801:1801:1801)) + (PORT clk (1105:1105:1105) (1122:1122:1122)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1105:1105:1105) (1122:1122:1122)) + (PORT d[0] (1771:1771:1771) (1597:1597:1597)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1106:1106:1106) (1123:1123:1123)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1087:1087:1087) (1103:1103:1103)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (627:627:627) (635:635:635)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (628:628:628) (636:636:636)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (628:628:628) (636:636:636)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (628:628:628) (636:636:636)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Mux0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (969:969:969) (1158:1158:1158)) + (PORT datab (830:830:830) (941:941:941)) + (PORT datac (89:89:89) (110:110:110)) + (PORT datad (845:845:845) (955:955:955)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[7\]\~89) + (DELAY + (ABSOLUTE + (PORT dataa (1125:1125:1125) (1301:1301:1301)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (937:937:937) (1085:1085:1085)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[7\]\~72) + (DELAY + (ABSOLUTE + (PORT dataa (796:796:796) (914:914:914)) + (PORT datab (868:868:868) (1007:1007:1007)) + (PORT datac (89:89:89) (110:110:110)) + (PORT datad (800:800:800) (900:900:900)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~84) + (DELAY + (ABSOLUTE + (PORT dataa (305:305:305) (356:356:356)) + (PORT datab (1547:1547:1547) (1820:1820:1820)) + (PORT datac (315:315:315) (363:363:363)) + (PORT datad (313:313:313) (369:369:369)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[7\]\~80) + (DELAY + (ABSOLUTE + (PORT datac (104:104:104) (126:126:126)) + (PORT datad (798:798:798) (907:907:907)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[7\]) + (DELAY + (ABSOLUTE + (PORT dataa (797:797:797) (915:915:915)) + (PORT datab (115:115:115) (143:143:143)) + (PORT datac (650:650:650) (746:746:746)) + (PORT datad (195:195:195) (230:230:230)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (917:917:917) (904:904:904)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (421:421:421) (449:449:449)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[7\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (211:211:211) (255:255:255)) + (PORT datab (185:185:185) (221:221:221)) + (PORT datac (313:313:313) (368:368:368)) + (PORT datad (305:305:305) (355:355:355)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (909:909:909) (896:896:896)) + (PORT ena (912:912:912) (993:993:993)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (160:160:160) (218:218:218)) + (PORT datab (148:148:148) (198:198:198)) + (PORT datac (209:209:209) (270:270:270)) + (PORT datad (208:208:208) (262:262:262)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal12\~0) + (DELAY + (ABSOLUTE + (PORT dataa (878:878:878) (1041:1041:1041)) + (PORT datab (873:873:873) (1017:1017:1017)) + (PORT datac (783:783:783) (957:957:957)) + (PORT datad (850:850:850) (993:993:993)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1167:1167:1167) (1384:1384:1384)) + (PORT datab (668:668:668) (805:805:805)) + (PORT datac (364:364:364) (432:432:432)) + (PORT datad (690:690:690) (825:825:825)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~24) + (DELAY + (ABSOLUTE + (PORT dataa (745:745:745) (864:864:864)) + (PORT datab (513:513:513) (595:595:595)) + (PORT datac (465:465:465) (548:548:548)) + (PORT datad (938:938:938) (1059:1059:1059)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~25) + (DELAY + (ABSOLUTE + (PORT dataa (547:547:547) (639:639:639)) + (PORT datab (324:324:324) (380:380:380)) + (PORT datac (328:328:328) (378:378:378)) + (PORT datad (516:516:516) (591:591:591)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~21) + (DELAY + (ABSOLUTE + (PORT dataa (959:959:959) (1113:1113:1113)) + (PORT datab (168:168:168) (226:226:226)) + (PORT datac (339:339:339) (393:393:393)) + (PORT datad (316:316:316) (362:362:362)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1183:1183:1183) (1384:1384:1384)) + (PORT datab (514:514:514) (600:600:600)) + (PORT datac (620:620:620) (706:706:706)) + (PORT datad (587:587:587) (672:672:672)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~14) + (DELAY + (ABSOLUTE + (PORT dataa (649:649:649) (747:747:747)) + (PORT datab (492:492:492) (576:576:576)) + (PORT datac (316:316:316) (372:372:372)) + (PORT datad (216:216:216) (262:262:262)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1183:1183:1183) (1384:1384:1384)) + (PORT datab (986:986:986) (1133:1133:1133)) + (PORT datac (1196:1196:1196) (1361:1361:1361)) + (PORT datad (515:515:515) (589:589:589)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~12) + (DELAY + (ABSOLUTE + (PORT dataa (540:540:540) (632:632:632)) + (PORT datab (398:398:398) (481:481:481)) + (PORT datac (301:301:301) (349:349:349)) + (PORT datad (646:646:646) (752:752:752)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~11) + (DELAY + (ABSOLUTE + (PORT dataa (332:332:332) (381:381:381)) + (PORT datab (357:357:357) (422:422:422)) + (PORT datac (503:503:503) (577:577:577)) + (PORT datad (586:586:586) (671:671:671)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~13) + (DELAY + (ABSOLUTE + (PORT dataa (334:334:334) (392:392:392)) + (PORT datab (386:386:386) (462:462:462)) + (PORT datac (357:357:357) (423:423:423)) + (PORT datad (92:92:92) (109:109:109)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~17) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (134:134:134)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (685:685:685) (786:786:786)) + (PORT datad (89:89:89) (107:107:107)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~22) + (DELAY + (ABSOLUTE + (PORT dataa (338:338:338) (405:405:405)) + (PORT datab (329:329:329) (390:390:390)) + (PORT datac (643:643:643) (744:744:744)) + (PORT datad (334:334:334) (389:389:389)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~27) + (DELAY + (ABSOLUTE + (PORT dataa (1234:1234:1234) (1426:1426:1426)) + (PORT datab (819:819:819) (937:937:937)) + (PORT datac (632:632:632) (731:731:731)) + (PORT datad (502:502:502) (578:578:578)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~37) + (DELAY + (ABSOLUTE + (PORT dataa (826:826:826) (975:975:975)) + (PORT datab (318:318:318) (369:369:369)) + (PORT datac (549:549:549) (660:660:660)) + (PORT datad (502:502:502) (579:579:579)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~31) + (DELAY + (ABSOLUTE + (PORT dataa (631:631:631) (722:722:722)) + (PORT datab (507:507:507) (591:591:591)) + (PORT datac (477:477:477) (540:540:540)) + (PORT datad (722:722:722) (822:822:822)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~29) + (DELAY + (ABSOLUTE + (PORT dataa (404:404:404) (490:490:490)) + (PORT datab (595:595:595) (721:721:721)) + (PORT datac (706:706:706) (842:842:842)) + (PORT datad (556:556:556) (666:666:666)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~30) + (DELAY + (ABSOLUTE + (PORT dataa (618:618:618) (714:714:714)) + (PORT datab (118:118:118) (148:148:148)) + (PORT datac (501:501:501) (580:580:580)) + (PORT datad (520:520:520) (602:602:602)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~28) + (DELAY + (ABSOLUTE + (PORT dataa (494:494:494) (566:566:566)) + (PORT datab (638:638:638) (730:730:730)) + (PORT datac (733:733:733) (838:838:838)) + (PORT datad (529:529:529) (622:622:622)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~32) + (DELAY + (ABSOLUTE + (PORT dataa (108:108:108) (141:141:141)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (89:89:89) (111:111:111)) + (PORT datad (92:92:92) (109:109:109)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~33) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (113:113:113) (145:145:145)) + (PORT datac (89:89:89) (109:109:109)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~23) + (DELAY + (ABSOLUTE + (PORT dataa (798:798:798) (922:922:922)) + (PORT datab (472:472:472) (538:538:538)) + (PORT datac (478:478:478) (545:545:545)) + (PORT datad (342:342:342) (399:399:399)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~34) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (136:136:136)) + (PORT datab (331:331:331) (388:388:388)) + (PORT datac (480:480:480) (548:548:548)) + (PORT datad (343:343:343) (402:402:402)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~35) + (DELAY + (ABSOLUTE + (PORT dataa (188:188:188) (234:234:234)) + (PORT datab (514:514:514) (600:600:600)) + (PORT datac (612:612:612) (692:692:692)) + (PORT datad (586:586:586) (672:672:672)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~19) + (DELAY + (ABSOLUTE + (PORT dataa (877:877:877) (1032:1032:1032)) + (PORT datab (678:678:678) (834:834:834)) + (PORT datac (347:347:347) (403:403:403)) + (PORT datad (317:317:317) (362:362:362)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~36) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (135:135:135)) + (PORT datab (130:130:130) (165:165:165)) + (PORT datac (328:328:328) (385:385:385)) + (PORT datad (95:95:95) (115:115:115)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_re) + (DELAY + (ABSOLUTE + (PORT dataa (619:619:619) (721:721:721)) + (PORT datac (577:577:577) (656:656:656)) + (PORT datad (407:407:407) (460:460:460)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~118) + (DELAY + (ABSOLUTE + (PORT dataa (535:535:535) (643:643:643)) + (PORT datab (842:842:842) (984:984:984)) + (PORT datac (620:620:620) (722:722:722)) + (PORT datad (634:634:634) (743:743:743)) + (IOPATH dataa combout (172:172:172) (163:163:163)) + (IOPATH datab combout (169:169:169) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~119) + (DELAY + (ABSOLUTE + (PORT dataa (740:740:740) (879:879:879)) + (PORT datab (226:226:226) (293:293:293)) + (PORT datac (161:161:161) (187:187:187)) + (PORT datad (337:337:337) (396:396:396)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~120) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (134:134:134)) + (PORT datad (105:105:105) (122:122:122)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (895:895:895) (899:899:899)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~129) + (DELAY + (ABSOLUTE + (PORT dataa (231:231:231) (287:287:287)) + (PORT datab (673:673:673) (785:785:785)) + (PORT datac (172:172:172) (204:204:204)) + (PORT datad (374:374:374) (451:451:451)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~116) + (DELAY + (ABSOLUTE + (PORT dataa (423:423:423) (528:528:528)) + (PORT datab (238:238:238) (299:299:299)) + (PORT datad (561:561:561) (675:675:675)) + (IOPATH dataa combout (158:158:158) (173:173:173)) + (IOPATH datab combout (160:160:160) (176:176:176)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~134) + (DELAY + (ABSOLUTE + (PORT dataa (540:540:540) (647:647:647)) + (PORT datab (651:651:651) (778:778:778)) + (PORT datad (164:164:164) (190:190:190)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~117) + (DELAY + (ABSOLUTE + (PORT dataa (336:336:336) (410:410:410)) + (PORT datab (177:177:177) (216:216:216)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (911:911:911)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (892:892:892) (897:897:897)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~60) + (DELAY + (ABSOLUTE + (PORT dataa (587:587:587) (677:677:677)) + (PORT datab (588:588:588) (708:708:708)) + (PORT datac (199:199:199) (254:254:254)) + (PORT datad (456:456:456) (538:538:538)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|Equal0\~2) + (DELAY + (ABSOLUTE + (PORT datab (536:536:536) (664:664:664)) + (PORT datac (381:381:381) (466:466:466)) + (PORT datad (357:357:357) (430:430:430)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]\~121) + (DELAY + (ABSOLUTE + (PORT dataa (505:505:505) (605:605:605)) + (PORT datab (876:876:876) (1012:1012:1012)) + (PORT datad (198:198:198) (229:229:229)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (895:895:895) (899:899:899)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~115) + (DELAY + (ABSOLUTE + (PORT dataa (111:111:111) (145:145:145)) + (PORT datab (118:118:118) (147:147:147)) + (PORT datad (186:186:186) (216:216:216)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (895:895:895) (899:899:899)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\~4) + (DELAY + (ABSOLUTE + (PORT dataa (223:223:223) (283:283:283)) + (PORT datac (1321:1321:1321) (1560:1560:1560)) + (PORT datad (802:802:802) (934:934:934)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~61) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (136:136:136)) + (PORT datab (595:595:595) (689:689:689)) + (PORT datac (117:117:117) (158:158:158)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~124) + (DELAY + (ABSOLUTE + (PORT datab (386:386:386) (473:473:473)) + (PORT datac (155:155:155) (202:202:202)) + (PORT datad (352:352:352) (422:422:422)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~125) + (DELAY + (ABSOLUTE + (PORT dataa (533:533:533) (639:639:639)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (320:320:320) (364:364:364)) + (PORT datad (1231:1231:1231) (1444:1444:1444)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~126) + (DELAY + (ABSOLUTE + (PORT dataa (316:316:316) (366:366:366)) + (PORT datab (251:251:251) (315:315:315)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (911:911:911)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (892:892:892) (897:897:897)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~122) + (DELAY + (ABSOLUTE + (PORT dataa (534:534:534) (640:640:640)) + (PORT datab (1249:1249:1249) (1468:1468:1468)) + (PORT datac (534:534:534) (636:636:636)) + (PORT datad (350:350:350) (420:420:420)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~123) + (DELAY + (ABSOLUTE + (PORT dataa (491:491:491) (567:567:567)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datad (234:234:234) (292:292:292)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (911:911:911)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (892:892:892) (897:897:897)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~62) + (DELAY + (ABSOLUTE + (PORT dataa (130:130:130) (180:180:180)) + (PORT datab (1150:1150:1150) (1305:1305:1305)) + (PORT datac (468:468:468) (548:548:548)) + (PORT datad (116:116:116) (154:154:154)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~49) + (DELAY + (ABSOLUTE + (PORT dataa (510:510:510) (593:593:593)) + (PORT datab (1259:1259:1259) (1476:1476:1476)) + (PORT datac (462:462:462) (523:523:523)) + (PORT datad (532:532:532) (634:634:634)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|shifted\~3) + (DELAY + (ABSOLUTE + (PORT datac (595:595:595) (721:721:721)) + (PORT datad (663:663:663) (780:780:780)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~127) + (DELAY + (ABSOLUTE + (PORT dataa (419:419:419) (521:521:521)) + (PORT datab (187:187:187) (230:230:230)) + (PORT datad (105:105:105) (123:123:123)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (895:895:895) (899:899:899)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~128) + (DELAY + (ABSOLUTE + (PORT dataa (415:415:415) (516:516:516)) + (PORT datab (482:482:482) (555:555:555)) + (PORT datad (178:178:178) (211:211:211)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (895:895:895) (899:899:899)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~63) + (DELAY + (ABSOLUTE + (PORT dataa (462:462:462) (551:551:551)) + (PORT datab (337:337:337) (399:399:399)) + (PORT datac (699:699:699) (827:827:827)) + (PORT datad (765:765:765) (932:932:932)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~64) + (DELAY + (ABSOLUTE + (PORT dataa (449:449:449) (516:516:516)) + (PORT datab (524:524:524) (599:599:599)) + (PORT datac (1672:1672:1672) (1963:1963:1963)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (543:543:543) (619:619:619)) + (PORT clk (1094:1094:1094) (1111:1111:1111)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1323:1323:1323) (1512:1512:1512)) + (PORT d[1] (732:732:732) (836:836:836)) + (PORT d[2] (1243:1243:1243) (1446:1446:1446)) + (PORT d[3] (1410:1410:1410) (1637:1637:1637)) + (PORT d[4] (568:568:568) (659:659:659)) + (PORT d[5] (686:686:686) (791:791:791)) + (PORT d[6] (1961:1961:1961) (2209:2209:2209)) + (PORT d[7] (1063:1063:1063) (1257:1257:1257)) + (PORT d[8] (696:696:696) (794:794:794)) + (PORT d[9] (2016:2016:2016) (2360:2360:2360)) + (PORT d[10] (554:554:554) (644:644:644)) + (PORT d[11] (852:852:852) (969:969:969)) + (PORT d[12] (1135:1135:1135) (1294:1294:1294)) + (PORT clk (1092:1092:1092) (1109:1109:1109)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (828:828:828) (887:887:887)) + (PORT clk (1092:1092:1092) (1109:1109:1109)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1094:1094:1094) (1111:1111:1111)) + (PORT d[0] (1195:1195:1195) (1264:1264:1264)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1095:1095:1095) (1112:1112:1112)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1095:1095:1095) (1112:1112:1112)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1095:1095:1095) (1112:1112:1112)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1095:1095:1095) (1112:1112:1112)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1074:1074:1074) (1090:1090:1090)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (614:614:614) (622:622:622)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (615:615:615) (623:623:623)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (615:615:615) (623:623:623)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (615:615:615) (623:623:623)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) @@ -42356,7 +38970,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (696:696:696) (802:802:802)) + (PORT d[0] (538:538:538) (617:617:617)) (PORT clk (1092:1092:1092) (1110:1110:1110)) ) ) @@ -42369,19 +38983,19 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1891:1891:1891) (2200:2200:2200)) - (PORT d[1] (764:764:764) (903:903:903)) - (PORT d[2] (1115:1115:1115) (1298:1298:1298)) - (PORT d[3] (861:861:861) (1007:1007:1007)) - (PORT d[4] (1071:1071:1071) (1242:1242:1242)) - (PORT d[5] (927:927:927) (1087:1087:1087)) - (PORT d[6] (665:665:665) (775:775:775)) - (PORT d[7] (836:836:836) (960:960:960)) - (PORT d[8] (1455:1455:1455) (1707:1707:1707)) - (PORT d[9] (2011:2011:2011) (2318:2318:2318)) - (PORT d[10] (1658:1658:1658) (1903:1903:1903)) - (PORT d[11] (696:696:696) (800:800:800)) - (PORT d[12] (623:623:623) (719:719:719)) + (PORT d[0] (1471:1471:1471) (1673:1673:1673)) + (PORT d[1] (720:720:720) (830:830:830)) + (PORT d[2] (1373:1373:1373) (1622:1622:1622)) + (PORT d[3] (1595:1595:1595) (1850:1850:1850)) + (PORT d[4] (415:415:415) (492:492:492)) + (PORT d[5] (685:685:685) (790:790:790)) + (PORT d[6] (1952:1952:1952) (2197:2197:2197)) + (PORT d[7] (1057:1057:1057) (1245:1245:1245)) + (PORT d[8] (682:682:682) (773:773:773)) + (PORT d[9] (2029:2029:2029) (2380:2380:2380)) + (PORT d[10] (544:544:544) (632:632:632)) + (PORT d[11] (847:847:847) (966:966:966)) + (PORT d[12] (1284:1284:1284) (1462:1462:1462)) (PORT clk (1090:1090:1090) (1108:1108:1108)) ) ) @@ -42394,7 +39008,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1641:1641:1641) (1814:1814:1814)) + (PORT d[0] (1104:1104:1104) (1200:1200:1200)) (PORT clk (1090:1090:1090) (1108:1108:1108)) ) ) @@ -42408,7 +39022,7 @@ (DELAY (ABSOLUTE (PORT clk (1092:1092:1092) (1110:1110:1110)) - (PORT d[0] (1828:1828:1828) (2013:2013:2013)) + (PORT d[0] (1053:1053:1053) (1109:1109:1109)) ) ) ) @@ -42506,585 +39120,10 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.datain_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1002:1002:1002) (1135:1135:1135)) - (PORT clk (1091:1091:1091) (1108:1108:1108)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1907:1907:1907) (2218:2218:2218)) - (PORT d[1] (982:982:982) (1157:1157:1157)) - (PORT d[2] (1569:1569:1569) (1801:1801:1801)) - (PORT d[3] (1205:1205:1205) (1398:1398:1398)) - (PORT d[4] (1266:1266:1266) (1475:1475:1475)) - (PORT d[5] (1387:1387:1387) (1637:1637:1637)) - (PORT d[6] (1227:1227:1227) (1424:1424:1424)) - (PORT d[7] (1427:1427:1427) (1617:1617:1617)) - (PORT d[8] (1747:1747:1747) (2037:2037:2037)) - (PORT d[9] (1449:1449:1449) (1675:1675:1675)) - (PORT d[10] (2215:2215:2215) (2545:2545:2545)) - (PORT d[11] (992:992:992) (1149:1149:1149)) - (PORT d[12] (1348:1348:1348) (1543:1543:1543)) - (PORT clk (1089:1089:1089) (1106:1106:1106)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1269:1269:1269) (1391:1391:1391)) - (PORT clk (1089:1089:1089) (1106:1106:1106)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1091:1091:1091) (1108:1108:1108)) - (PORT d[0] (1504:1504:1504) (1616:1616:1616)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1092:1092:1092) (1109:1109:1109)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1092:1092:1092) (1109:1109:1109)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1092:1092:1092) (1109:1109:1109)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1092:1092:1092) (1109:1109:1109)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1071:1071:1071) (1087:1087:1087)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (611:611:611) (619:619:619)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (612:612:612) (620:620:620)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (612:612:612) (620:620:620)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (612:612:612) (620:620:620)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (962:962:962) (1111:1111:1111)) - (PORT datab (660:660:660) (745:745:745)) - (PORT datad (964:964:964) (1091:1091:1091)) - (IOPATH dataa combout (186:186:186) (175:175:175)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (847:847:847) (962:962:962)) - (PORT datab (834:834:834) (948:948:948)) - (PORT datac (1159:1159:1159) (1329:1329:1329)) - (PORT datad (91:91:91) (108:108:108)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~109) - (DELAY - (ABSOLUTE - (PORT dataa (378:378:378) (465:465:465)) - (PORT datab (646:646:646) (769:769:769)) - (PORT datac (91:91:91) (113:113:113)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (158:158:158) (173:173:173)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~97) - (DELAY - (ABSOLUTE - (PORT dataa (478:478:478) (562:562:562)) - (PORT datab (877:877:877) (1025:1025:1025)) - (PORT datac (833:833:833) (962:962:962)) - (PORT datad (95:95:95) (115:115:115)) - (IOPATH dataa combout (172:172:172) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~98) - (DELAY - (ABSOLUTE - (PORT dataa (642:642:642) (768:768:768)) - (PORT datab (898:898:898) (1028:1028:1028)) - (PORT datac (834:834:834) (963:963:963)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[4\]) - (DELAY - (ABSOLUTE - (PORT dataa (539:539:539) (641:641:641)) - (PORT datab (817:817:817) (925:925:925)) - (PORT datac (126:126:126) (162:162:162)) - (PORT datad (642:642:642) (729:729:729)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (916:916:916) (903:903:903)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (432:432:432) (460:460:460)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[4\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (205:205:205) (265:265:265)) - (PORT datab (200:200:200) (240:240:240)) - (PORT datad (356:356:356) (418:418:418)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[4\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (540:540:540) (624:624:624)) - (PORT datab (504:504:504) (580:580:580)) - (PORT datac (503:503:503) (577:577:577)) - (PORT datad (492:492:492) (560:560:560)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (914:914:914)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (911:911:911) (895:895:895)) - (PORT ena (780:780:780) (849:849:849)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal21\~0) - (DELAY - (ABSOLUTE - (PORT datac (814:814:814) (956:956:956)) - (PORT datad (835:835:835) (972:972:972)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~5) - (DELAY - (ABSOLUTE - (PORT dataa (756:756:756) (873:873:873)) - (PORT datab (538:538:538) (635:635:635)) - (PORT datac (913:913:913) (1096:1096:1096)) - (PORT datad (690:690:690) (800:800:800)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~2) - (DELAY - (ABSOLUTE - (PORT dataa (731:731:731) (854:854:854)) - (PORT datab (861:861:861) (1001:1001:1001)) - (PORT datac (440:440:440) (506:506:506)) - (PORT datad (106:106:106) (124:124:124)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~3) - (DELAY - (ABSOLUTE - (PORT datab (853:853:853) (1003:1003:1003)) - (PORT datac (752:752:752) (882:882:882)) - (PORT datad (1442:1442:1442) (1705:1705:1705)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~4) - (DELAY - (ABSOLUTE - (PORT dataa (465:465:465) (551:551:551)) - (PORT datab (488:488:488) (576:576:576)) - (PORT datac (944:944:944) (1100:1100:1100)) - (PORT datad (91:91:91) (108:108:108)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~5) - (DELAY - (ABSOLUTE - (PORT dataa (225:225:225) (265:265:265)) - (PORT datab (667:667:667) (778:778:778)) - (PORT datac (90:90:90) (112:112:112)) - (PORT datad (189:189:189) (221:221:221)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~11) - (DELAY - (ABSOLUTE - (PORT dataa (513:513:513) (594:594:594)) - (PORT datab (340:340:340) (405:405:405)) - (PORT datac (484:484:484) (567:567:567)) - (PORT datad (482:482:482) (551:551:551)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1103:1103:1103) (1266:1266:1266)) - (PORT datab (609:609:609) (706:706:706)) - (PORT datac (460:460:460) (531:531:531)) - (PORT datad (349:349:349) (411:411:411)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~13) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (135:135:135)) - (PORT datab (315:315:315) (367:367:367)) - (PORT datac (278:278:278) (323:323:323)) - (PORT datad (94:94:94) (112:112:112)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~14) - (DELAY - (ABSOLUTE - (PORT dataa (882:882:882) (1032:1032:1032)) - (PORT datab (468:468:468) (544:544:544)) - (PORT datac (835:835:835) (945:945:945)) - (PORT datad (577:577:577) (648:648:648)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~15) - (DELAY - (ABSOLUTE - (PORT dataa (332:332:332) (384:384:384)) - (PORT datab (478:478:478) (556:556:556)) - (PORT datac (459:459:459) (532:532:532)) - (PORT datad (670:670:670) (781:781:781)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|DFFE_mwr_ff1) - (DELAY - (ABSOLUTE - (PORT clk (916:916:916) (923:923:923)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (922:922:922) (904:904:904)) - (PORT ena (689:689:689) (767:767:767)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|wait_mwr\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (120:120:120) (158:158:158)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|wait_mwr) - (DELAY - (ABSOLUTE - (PORT clk (927:927:927) (912:912:912)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (922:922:922) (904:904:904)) - (PORT ena (704:704:704) (789:789:789)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|mwr_wr) - (DELAY - (ABSOLUTE - (PORT clk (927:927:927) (912:912:912)) - (PORT asdata (299:299:299) (341:341:341)) - (PORT clrn (922:922:922) (904:904:904)) - (PORT ena (704:704:704) (789:789:789)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|nWR_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (459:459:459) (532:532:532)) - (PORT datab (182:182:182) (225:225:225)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[5\]\~84) - (DELAY - (ABSOLUTE - (PORT dataa (982:982:982) (1142:1142:1142)) - (PORT datab (897:897:897) (1062:1062:1062)) - (PORT datac (653:653:653) (769:769:769)) - (PORT datad (683:683:683) (799:799:799)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (657:657:657) (743:743:743)) + (PORT d[0] (538:538:538) (612:612:612)) (PORT clk (1094:1094:1094) (1111:1111:1111)) ) ) @@ -43094,22 +39133,22 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.addr_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2376:2376:2376) (2743:2743:2743)) - (PORT d[1] (1673:1673:1673) (1949:1949:1949)) - (PORT d[2] (1859:1859:1859) (2120:2120:2120)) - (PORT d[3] (1457:1457:1457) (1704:1704:1704)) - (PORT d[4] (1308:1308:1308) (1532:1532:1532)) - (PORT d[5] (1495:1495:1495) (1741:1741:1741)) - (PORT d[6] (1079:1079:1079) (1242:1242:1242)) - (PORT d[7] (1355:1355:1355) (1538:1538:1538)) - (PORT d[8] (1818:1818:1818) (2136:2136:2136)) - (PORT d[9] (1647:1647:1647) (1909:1909:1909)) - (PORT d[10] (2810:2810:2810) (3210:3210:3210)) - (PORT d[11] (1259:1259:1259) (1464:1464:1464)) - (PORT d[12] (1279:1279:1279) (1469:1469:1469)) + (PORT d[0] (1500:1500:1500) (1711:1711:1711)) + (PORT d[1] (719:719:719) (827:827:827)) + (PORT d[2] (1703:1703:1703) (1991:1991:1991)) + (PORT d[3] (544:544:544) (627:627:627)) + (PORT d[4] (403:403:403) (478:478:478)) + (PORT d[5] (652:652:652) (748:748:748)) + (PORT d[6] (539:539:539) (622:622:622)) + (PORT d[7] (1245:1245:1245) (1459:1459:1459)) + (PORT d[8] (691:691:691) (789:789:789)) + (PORT d[9] (533:533:533) (608:608:608)) + (PORT d[10] (2793:2793:2793) (3238:3238:3238)) + (PORT d[11] (855:855:855) (978:978:978)) + (PORT d[12] (1478:1478:1478) (1678:1678:1678)) (PORT clk (1092:1092:1092) (1109:1109:1109)) ) ) @@ -43119,10 +39158,10 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.we_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1104:1104:1104) (1196:1196:1196)) + (PORT d[0] (500:500:500) (512:512:512)) (PORT clk (1092:1092:1092) (1109:1109:1109)) ) ) @@ -43132,17 +39171,17 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.active_core_port_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) (DELAY (ABSOLUTE (PORT clk (1094:1094:1094) (1111:1111:1111)) - (PORT d[0] (1283:1283:1283) (1376:1376:1376)) + (PORT d[0] (1185:1185:1185) (1255:1255:1255)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.wpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_a) (DELAY (ABSOLUTE (PORT clk (1095:1095:1095) (1112:1112:1112)) @@ -43152,7 +39191,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) (DELAY (ABSOLUTE (PORT clk (1095:1095:1095) (1112:1112:1112)) @@ -43162,7 +39201,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.ftpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_a) (DELAY (ABSOLUTE (PORT clk (1095:1095:1095) (1112:1112:1112)) @@ -43172,7 +39211,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rwpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_a) (DELAY (ABSOLUTE (PORT clk (1095:1095:1095) (1112:1112:1112)) @@ -43182,7 +39221,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.dataout_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) (DELAY (ABSOLUTE (PORT clk (1074:1074:1074) (1090:1090:1090)) @@ -43196,7 +39235,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.active_core_port_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) (DELAY (ABSOLUTE (PORT clk (614:614:614) (622:622:622)) @@ -43205,7 +39244,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) (DELAY (ABSOLUTE (PORT clk (615:615:615) (623:623:623)) @@ -43214,7 +39253,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.ftpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) (DELAY (ABSOLUTE (PORT clk (615:615:615) (623:623:623)) @@ -43224,7 +39263,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rwpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) (DELAY (ABSOLUTE (PORT clk (615:615:615) (623:623:623)) @@ -43234,163 +39273,10 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.datain_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (667:667:667) (755:755:755)) - (PORT clk (1096:1096:1096) (1113:1113:1113)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2370:2370:2370) (2737:2737:2737)) - (PORT d[1] (1682:1682:1682) (1961:1961:1961)) - (PORT d[2] (1599:1599:1599) (1830:1830:1830)) - (PORT d[3] (1456:1456:1456) (1704:1704:1704)) - (PORT d[4] (1317:1317:1317) (1545:1545:1545)) - (PORT d[5] (1481:1481:1481) (1721:1721:1721)) - (PORT d[6] (1111:1111:1111) (1275:1275:1275)) - (PORT d[7] (1341:1341:1341) (1517:1517:1517)) - (PORT d[8] (1821:1821:1821) (2141:2141:2141)) - (PORT d[9] (1479:1479:1479) (1716:1716:1716)) - (PORT d[10] (2803:2803:2803) (3202:3202:3202)) - (PORT d[11] (1087:1087:1087) (1266:1266:1266)) - (PORT d[12] (1288:1288:1288) (1482:1482:1482)) - (PORT clk (1094:1094:1094) (1111:1111:1111)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1335:1335:1335) (1450:1450:1450)) - (PORT clk (1094:1094:1094) (1111:1111:1111)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1096:1096:1096) (1113:1113:1113)) - (PORT d[0] (1595:1595:1595) (1711:1711:1711)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1114:1114:1114)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1114:1114:1114)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1114:1114:1114)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1114:1114:1114)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1076:1076:1076) (1092:1092:1092)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (616:616:616) (624:624:624)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (617:617:617) (625:625:625)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (617:617:617) (625:625:625)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (617:617:617) (625:625:625)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (490:490:490) (554:554:554)) + (PORT d[0] (402:402:402) (463:463:463)) (PORT clk (1090:1090:1090) (1108:1108:1108)) ) ) @@ -43400,22 +39286,22 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (756:756:756) (870:870:870)) - (PORT d[1] (1184:1184:1184) (1400:1400:1400)) - (PORT d[2] (1753:1753:1753) (2001:2001:2001)) - (PORT d[3] (1487:1487:1487) (1749:1749:1749)) - (PORT d[4] (1499:1499:1499) (1753:1753:1753)) - (PORT d[5] (1655:1655:1655) (1919:1919:1919)) - (PORT d[6] (1127:1127:1127) (1303:1303:1303)) - (PORT d[7] (1522:1522:1522) (1724:1724:1724)) - (PORT d[8] (1982:1982:1982) (2322:2322:2322)) - (PORT d[9] (1666:1666:1666) (1930:1930:1930)) - (PORT d[10] (2976:2976:2976) (3402:3402:3402)) - (PORT d[11] (1099:1099:1099) (1284:1284:1284)) - (PORT d[12] (1108:1108:1108) (1277:1277:1277)) + (PORT d[0] (1494:1494:1494) (1705:1705:1705)) + (PORT d[1] (533:533:533) (615:615:615)) + (PORT d[2] (1546:1546:1546) (1814:1814:1814)) + (PORT d[3] (563:563:563) (647:647:647)) + (PORT d[4] (390:390:390) (460:460:460)) + (PORT d[5] (478:478:478) (551:551:551)) + (PORT d[6] (678:678:678) (776:776:776)) + (PORT d[7] (1239:1239:1239) (1452:1452:1452)) + (PORT d[8] (504:504:504) (576:576:576)) + (PORT d[9] (531:531:531) (611:611:611)) + (PORT d[10] (1231:1231:1231) (1417:1417:1417)) + (PORT d[11] (655:655:655) (748:748:748)) + (PORT d[12] (1315:1315:1315) (1499:1499:1499)) (PORT clk (1088:1088:1088) (1106:1106:1106)) ) ) @@ -43425,10 +39311,10 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.we_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (692:692:692) (734:734:734)) + (PORT d[0] (663:663:663) (701:701:701)) (PORT clk (1088:1088:1088) (1106:1106:1106)) ) ) @@ -43438,17 +39324,17 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) (DELAY (ABSOLUTE (PORT clk (1090:1090:1090) (1108:1108:1108)) - (PORT d[0] (1395:1395:1395) (1506:1506:1506)) + (PORT d[0] (1146:1146:1146) (1206:1206:1206)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_a) (DELAY (ABSOLUTE (PORT clk (1091:1091:1091) (1109:1109:1109)) @@ -43458,7 +39344,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) (DELAY (ABSOLUTE (PORT clk (1091:1091:1091) (1109:1109:1109)) @@ -43468,7 +39354,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_a) (DELAY (ABSOLUTE (PORT clk (1091:1091:1091) (1109:1109:1109)) @@ -43478,7 +39364,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_a) (DELAY (ABSOLUTE (PORT clk (1091:1091:1091) (1109:1109:1109)) @@ -43488,7 +39374,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) (DELAY (ABSOLUTE (PORT clk (1070:1070:1070) (1087:1087:1087)) @@ -43502,7 +39388,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) (DELAY (ABSOLUTE (PORT clk (610:610:610) (619:619:619)) @@ -43511,7 +39397,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) (DELAY (ABSOLUTE (PORT clk (611:611:611) (620:620:620)) @@ -43520,7 +39406,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) (DELAY (ABSOLUTE (PORT clk (611:611:611) (620:620:620)) @@ -43530,7 +39416,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) (DELAY (ABSOLUTE (PORT clk (611:611:611) (620:620:620)) @@ -43540,27 +39426,55 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~6) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~8) (DELAY (ABSOLUTE - (PORT dataa (785:785:785) (912:912:912)) - (PORT datab (518:518:518) (617:617:617)) - (PORT datac (611:611:611) (694:694:694)) - (PORT datad (462:462:462) (525:525:525)) + (PORT dataa (484:484:484) (567:567:567)) + (PORT datab (468:468:468) (537:537:537)) + (PORT datac (447:447:447) (509:509:509)) + (PORT datad (759:759:759) (868:868:868)) (IOPATH dataa combout (188:188:188) (184:184:184)) - (IOPATH datab combout (190:190:190) (188:188:188)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.datain_a_register) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~9) (DELAY (ABSOLUTE - (PORT d[0] (657:657:657) (752:752:752)) - (PORT clk (1090:1090:1090) (1107:1107:1107)) + (PORT dataa (621:621:621) (706:706:706)) + (PORT datab (593:593:593) (675:675:675)) + (PORT datac (90:90:90) (111:111:111)) + (PORT datad (994:994:994) (1151:1151:1151)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1167:1167:1167) (1331:1331:1331)) + (PORT d[1] (924:924:924) (1068:1068:1068)) + (PORT d[2] (1283:1283:1283) (1496:1496:1496)) + (PORT d[3] (1547:1547:1547) (1797:1797:1797)) + (PORT d[4] (586:586:586) (681:681:681)) + (PORT d[5] (857:857:857) (984:984:984)) + (PORT d[6] (1944:1944:1944) (2193:2193:2193)) + (PORT d[7] (1037:1037:1037) (1231:1231:1231)) + (PORT d[8] (876:876:876) (999:999:999)) + (PORT d[9] (2006:2006:2006) (2351:2351:2351)) + (PORT d[10] (550:550:550) (635:635:635)) + (PORT d[11] (530:530:530) (614:614:614)) + (PORT d[12] (1116:1116:1116) (1270:1270:1270)) + (PORT clk (1095:1095:1095) (1112:1112:1112)) ) ) (TIMINGCHECK @@ -43569,98 +39483,30 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.addr_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) (DELAY (ABSOLUTE - (PORT d[0] (1900:1900:1900) (2210:2210:2210)) - (PORT d[1] (990:990:990) (1167:1167:1167)) - (PORT d[2] (1735:1735:1735) (1988:1988:1988)) - (PORT d[3] (1232:1232:1232) (1433:1433:1433)) - (PORT d[4] (1437:1437:1437) (1671:1671:1671)) - (PORT d[5] (1395:1395:1395) (1645:1645:1645)) - (PORT d[6] (1220:1220:1220) (1416:1416:1416)) - (PORT d[7] (1434:1434:1434) (1624:1624:1624)) - (PORT d[8] (1748:1748:1748) (2034:2034:2034)) - (PORT d[9] (1434:1434:1434) (1651:1651:1651)) - (PORT d[10] (2203:2203:2203) (2532:2532:2532)) - (PORT d[11] (965:965:965) (1112:1112:1112)) - (PORT d[12] (1353:1353:1353) (1550:1550:1550)) - (PORT clk (1088:1088:1088) (1105:1105:1105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1241:1241:1241) (1352:1352:1352)) - (PORT clk (1088:1088:1088) (1105:1105:1105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1090:1090:1090) (1107:1107:1107)) - (PORT d[0] (1519:1519:1519) (1646:1646:1646)) + (PORT clk (1095:1095:1095) (1112:1112:1112)) + (PORT d[0] (1325:1325:1325) (1465:1465:1465)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.wpgen_a) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1091:1091:1091) (1108:1108:1108)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1091:1091:1091) (1108:1108:1108)) + (PORT clk (1096:1096:1096) (1113:1113:1113)) (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) ) ) ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1091:1091:1091) (1108:1108:1108)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1091:1091:1091) (1108:1108:1108)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.dataout_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1070:1070:1070) (1086:1086:1086)) + (PORT clk (1077:1077:1077) (1093:1093:1093)) (IOPATH (posedge clk) q (164:164:164) (167:167:167)) ) ) @@ -43671,64 +39517,249 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.active_core_port_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (610:610:610) (618:618:618)) + (PORT clk (617:617:617) (625:625:625)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (611:611:611) (619:619:619)) + (PORT clk (618:618:618) (626:626:626)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.ftpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (611:611:611) (619:619:619)) + (PORT clk (618:618:618) (626:626:626)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rwpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (611:611:611) (619:619:619)) + (PORT clk (618:618:618) (626:626:626)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (782:782:782) (914:914:914)) - (PORT datab (635:635:635) (736:736:736)) - (PORT datac (89:89:89) (110:110:110)) - (PORT datad (807:807:807) (907:907:907)) - (IOPATH dataa combout (188:188:188) (203:203:203)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.datain_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (969:969:969) (1123:1123:1123)) + (PORT d[0] (887:887:887) (1032:1032:1032)) + (PORT clk (1099:1099:1099) (1117:1117:1117)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1511:1511:1511) (1775:1775:1775)) + (PORT d[1] (1388:1388:1388) (1597:1597:1597)) + (PORT d[2] (1282:1282:1282) (1485:1485:1485)) + (PORT d[3] (1521:1521:1521) (1792:1792:1792)) + (PORT d[4] (1678:1678:1678) (1930:1930:1930)) + (PORT d[5] (2067:2067:2067) (2371:2371:2371)) + (PORT d[6] (1715:1715:1715) (1954:1954:1954)) + (PORT d[7] (1119:1119:1119) (1329:1329:1329)) + (PORT d[8] (1531:1531:1531) (1739:1739:1739)) + (PORT d[9] (1499:1499:1499) (1730:1730:1730)) + (PORT d[10] (2209:2209:2209) (2572:2572:2572)) + (PORT d[11] (1844:1844:1844) (2152:2152:2152)) + (PORT d[12] (1379:1379:1379) (1588:1588:1588)) + (PORT clk (1097:1097:1097) (1115:1115:1115)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1610:1610:1610) (1762:1762:1762)) + (PORT clk (1097:1097:1097) (1115:1115:1115)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1099:1099:1099) (1117:1117:1117)) + (PORT d[0] (1918:1918:1918) (2086:2086:2086)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1100:1100:1100) (1118:1118:1118)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1100:1100:1100) (1118:1118:1118)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1100:1100:1100) (1118:1118:1118)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1100:1100:1100) (1118:1118:1118)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1054:1054:1054) (1074:1074:1074)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1564:1564:1564) (1821:1821:1821)) + (PORT clk (1059:1059:1059) (1077:1077:1077)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2275:2275:2275) (2574:2574:2574)) + (PORT d[1] (2289:2289:2289) (2582:2582:2582)) + (PORT d[2] (2270:2270:2270) (2562:2562:2562)) + (PORT d[3] (2323:2323:2323) (2647:2647:2647)) + (PORT d[4] (2405:2405:2405) (2724:2724:2724)) + (PORT d[5] (2463:2463:2463) (2800:2800:2800)) + (PORT d[6] (2349:2349:2349) (2662:2662:2662)) + (PORT d[7] (2269:2269:2269) (2552:2552:2552)) + (PORT d[8] (2351:2351:2351) (2643:2643:2643)) + (PORT d[9] (2368:2368:2368) (2679:2679:2679)) + (PORT d[10] (2254:2254:2254) (2536:2536:2536)) + (PORT d[11] (2333:2333:2333) (2632:2632:2632)) + (PORT d[12] (2297:2297:2297) (2616:2616:2616)) + (PORT clk (1056:1056:1056) (1076:1076:1076)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1059:1059:1059) (1077:1077:1077)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1060:1060:1060) (1078:1078:1078)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1060:1060:1060) (1078:1078:1078)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1060:1060:1060) (1078:1078:1078)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1060:1060:1060) (1078:1078:1078)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (963:963:963) (1135:1135:1135)) (PORT clk (1083:1083:1083) (1102:1102:1102)) ) ) @@ -43738,22 +39769,22 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1865:1865:1865) (2172:2172:2172)) - (PORT d[1] (1358:1358:1358) (1599:1599:1599)) - (PORT d[2] (1247:1247:1247) (1438:1438:1438)) - (PORT d[3] (1075:1075:1075) (1261:1261:1261)) - (PORT d[4] (1421:1421:1421) (1634:1634:1634)) - (PORT d[5] (1142:1142:1142) (1347:1347:1347)) - (PORT d[6] (807:807:807) (930:930:930)) - (PORT d[7] (834:834:834) (959:959:959)) - (PORT d[8] (1664:1664:1664) (1927:1927:1927)) - (PORT d[9] (1154:1154:1154) (1325:1325:1325)) - (PORT d[10] (1129:1129:1129) (1298:1298:1298)) - (PORT d[11] (789:789:789) (907:907:907)) - (PORT d[12] (1148:1148:1148) (1322:1322:1322)) + (PORT d[0] (1785:1785:1785) (2095:2095:2095)) + (PORT d[1] (2264:2264:2264) (2588:2588:2588)) + (PORT d[2] (1194:1194:1194) (1402:1402:1402)) + (PORT d[3] (1230:1230:1230) (1429:1429:1429)) + (PORT d[4] (1998:1998:1998) (2292:2292:2292)) + (PORT d[5] (1305:1305:1305) (1527:1527:1527)) + (PORT d[6] (1858:1858:1858) (2137:2137:2137)) + (PORT d[7] (909:909:909) (1078:1078:1078)) + (PORT d[8] (1238:1238:1238) (1436:1436:1436)) + (PORT d[9] (1428:1428:1428) (1647:1647:1647)) + (PORT d[10] (1628:1628:1628) (1909:1909:1909)) + (PORT d[11] (1121:1121:1121) (1308:1308:1308)) + (PORT d[12] (1746:1746:1746) (1987:1987:1987)) (PORT clk (1081:1081:1081) (1100:1100:1100)) ) ) @@ -43763,10 +39794,10 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.we_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1601:1601:1601) (1763:1763:1763)) + (PORT d[0] (1832:1832:1832) (2024:2024:2024)) (PORT clk (1081:1081:1081) (1100:1100:1100)) ) ) @@ -43776,17 +39807,17 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) (DELAY (ABSOLUTE (PORT clk (1083:1083:1083) (1102:1102:1102)) - (PORT d[0] (2271:2271:2271) (2510:2510:2510)) + (PORT d[0] (3246:3246:3246) (2978:2978:2978)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_a) (DELAY (ABSOLUTE (PORT clk (1084:1084:1084) (1103:1103:1103)) @@ -43796,7 +39827,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) (DELAY (ABSOLUTE (PORT clk (1084:1084:1084) (1103:1103:1103)) @@ -43806,7 +39837,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_a) (DELAY (ABSOLUTE (PORT clk (1084:1084:1084) (1103:1103:1103)) @@ -43816,7 +39847,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_a) (DELAY (ABSOLUTE (PORT clk (1084:1084:1084) (1103:1103:1103)) @@ -43826,7 +39857,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) (DELAY (ABSOLUTE (PORT clk (1038:1038:1038) (1059:1059:1059)) @@ -43840,10 +39871,10 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.datain_b_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.datain_b_register) (DELAY (ABSOLUTE - (PORT d[0] (654:654:654) (722:722:722)) + (PORT d[0] (1395:1395:1395) (1631:1631:1631)) (PORT clk (1043:1043:1043) (1062:1062:1062)) ) ) @@ -43853,22 +39884,22 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.addr_b_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.addr_b_register) (DELAY (ABSOLUTE - (PORT d[0] (2436:2436:2436) (2780:2780:2780)) - (PORT d[1] (2375:2375:2375) (2685:2685:2685)) - (PORT d[2] (2392:2392:2392) (2718:2718:2718)) - (PORT d[3] (2528:2528:2528) (2881:2881:2881)) - (PORT d[4] (2391:2391:2391) (2711:2711:2711)) - (PORT d[5] (2412:2412:2412) (2738:2738:2738)) - (PORT d[6] (2618:2618:2618) (2985:2985:2985)) - (PORT d[7] (2437:2437:2437) (2782:2782:2782)) - (PORT d[8] (2483:2483:2483) (2820:2820:2820)) - (PORT d[9] (2692:2692:2692) (3085:3085:3085)) - (PORT d[10] (2446:2446:2446) (2770:2770:2770)) - (PORT d[11] (2402:2402:2402) (2710:2710:2710)) - (PORT d[12] (2596:2596:2596) (2931:2931:2931)) + (PORT d[0] (2343:2343:2343) (2680:2680:2680)) + (PORT d[1] (2396:2396:2396) (2733:2733:2733)) + (PORT d[2] (2306:2306:2306) (2635:2635:2635)) + (PORT d[3] (2413:2413:2413) (2773:2773:2773)) + (PORT d[4] (2307:2307:2307) (2636:2636:2636)) + (PORT d[5] (2389:2389:2389) (2732:2732:2732)) + (PORT d[6] (2292:2292:2292) (2582:2582:2582)) + (PORT d[7] (2271:2271:2271) (2594:2594:2594)) + (PORT d[8] (2375:2375:2375) (2693:2693:2693)) + (PORT d[9] (2294:2294:2294) (2610:2610:2610)) + (PORT d[10] (2378:2378:2378) (2697:2697:2697)) + (PORT d[11] (2423:2423:2423) (2746:2746:2746)) + (PORT d[12] (2325:2325:2325) (2630:2630:2630)) (PORT clk (1040:1040:1040) (1061:1061:1061)) ) ) @@ -43878,7 +39909,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) (DELAY (ABSOLUTE (PORT clk (1043:1043:1043) (1062:1062:1062)) @@ -43887,7 +39918,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_b) (DELAY (ABSOLUTE (PORT clk (1044:1044:1044) (1063:1063:1063)) @@ -43897,435 +39928,40 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) (DELAY (ABSOLUTE (PORT clk (1044:1044:1044) (1063:1063:1063)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1044:1044:1044) (1063:1063:1063)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1044:1044:1044) (1063:1063:1063)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1451:1451:1451) (1655:1655:1655)) - (PORT d[1] (1198:1198:1198) (1420:1420:1420)) - (PORT d[2] (1305:1305:1305) (1527:1527:1527)) - (PORT d[3] (1317:1317:1317) (1517:1517:1517)) - (PORT d[4] (1725:1725:1725) (2024:2024:2024)) - (PORT d[5] (1210:1210:1210) (1433:1433:1433)) - (PORT d[6] (1075:1075:1075) (1227:1227:1227)) - (PORT d[7] (1440:1440:1440) (1645:1645:1645)) - (PORT d[8] (1584:1584:1584) (1869:1869:1869)) - (PORT d[9] (893:893:893) (1030:1030:1030)) - (PORT d[10] (1067:1067:1067) (1215:1215:1215)) - (PORT d[11] (1632:1632:1632) (1870:1870:1870)) - (PORT d[12] (881:881:881) (1013:1013:1013)) - (PORT clk (1103:1103:1103) (1121:1121:1121)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1103:1103:1103) (1121:1121:1121)) - (PORT d[0] (1263:1263:1263) (1416:1416:1416)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1104:1104:1104) (1122:1122:1122)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1085:1085:1085) (1102:1102:1102)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (625:625:625) (634:634:634)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (626:626:626) (635:635:635)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (626:626:626) (635:635:635)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (626:626:626) (635:635:635)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2011:2011:2011) (2313:2313:2313)) - (PORT d[1] (987:987:987) (1165:1165:1165)) - (PORT d[2] (1558:1558:1558) (1787:1787:1787)) - (PORT d[3] (1194:1194:1194) (1385:1385:1385)) - (PORT d[4] (1098:1098:1098) (1286:1286:1286)) - (PORT d[5] (1372:1372:1372) (1616:1616:1616)) - (PORT d[6] (1346:1346:1346) (1556:1556:1556)) - (PORT d[7] (1416:1416:1416) (1605:1605:1605)) - (PORT d[8] (1556:1556:1556) (1811:1811:1811)) - (PORT d[9] (1412:1412:1412) (1625:1625:1625)) - (PORT d[10] (2235:2235:2235) (2571:2571:2571)) - (PORT d[11] (1016:1016:1016) (1179:1179:1179)) - (PORT d[12] (1382:1382:1382) (1587:1587:1587)) - (PORT clk (1090:1090:1090) (1107:1107:1107)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1090:1090:1090) (1107:1107:1107)) - (PORT d[0] (1590:1590:1590) (1427:1427:1427)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1091:1091:1091) (1108:1108:1108)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1072:1072:1072) (1088:1088:1088)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (612:612:612) (620:620:620)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (613:613:613) (621:621:621)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (613:613:613) (621:621:621)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (613:613:613) (621:621:621)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (936:936:936) (1083:1083:1083)) - (PORT clk (1097:1097:1097) (1114:1114:1114)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1645:1645:1645) (1877:1877:1877)) - (PORT d[1] (1382:1382:1382) (1630:1630:1630)) - (PORT d[2] (1485:1485:1485) (1730:1730:1730)) - (PORT d[3] (1144:1144:1144) (1334:1334:1334)) - (PORT d[4] (1707:1707:1707) (2004:2004:2004)) - (PORT d[5] (1389:1389:1389) (1638:1638:1638)) - (PORT d[6] (1065:1065:1065) (1219:1219:1219)) - (PORT d[7] (939:939:939) (1085:1085:1085)) - (PORT d[8] (1741:1741:1741) (2030:2030:2030)) - (PORT d[9] (699:699:699) (802:802:802)) - (PORT d[10] (1255:1255:1255) (1430:1430:1430)) - (PORT d[11] (2096:2096:2096) (2391:2391:2391)) - (PORT d[12] (1086:1086:1086) (1248:1248:1248)) - (PORT clk (1095:1095:1095) (1112:1112:1112)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1554:1554:1554) (1710:1710:1710)) - (PORT clk (1095:1095:1095) (1112:1112:1112)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1114:1114:1114)) - (PORT d[0] (1889:1889:1889) (1754:1754:1754)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1098:1098:1098) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1098:1098:1098) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1098:1098:1098) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1098:1098:1098) (1115:1115:1115)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1052:1052:1052) (1071:1071:1071)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1217:1217:1217) (1382:1382:1382)) - (PORT clk (1057:1057:1057) (1074:1074:1074)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2540:2540:2540) (2882:2882:2882)) - (PORT d[1] (2318:2318:2318) (2609:2609:2609)) - (PORT d[2] (2339:2339:2339) (2654:2654:2654)) - (PORT d[3] (2599:2599:2599) (2954:2954:2954)) - (PORT d[4] (2392:2392:2392) (2719:2719:2719)) - (PORT d[5] (2428:2428:2428) (2730:2730:2730)) - (PORT d[6] (2583:2583:2583) (2943:2943:2943)) - (PORT d[7] (2268:2268:2268) (2562:2562:2562)) - (PORT d[8] (2620:2620:2620) (2939:2939:2939)) - (PORT d[9] (2601:2601:2601) (2982:2982:2982)) - (PORT d[10] (2462:2462:2462) (2771:2771:2771)) - (PORT d[11] (2504:2504:2504) (2828:2828:2828)) - (PORT d[12] (2488:2488:2488) (2807:2807:2807)) - (PORT clk (1054:1054:1054) (1073:1073:1073)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1057:1057:1057) (1074:1074:1074)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1058:1058:1058) (1075:1075:1075)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1058:1058:1058) (1075:1075:1075)) (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (1058:1058:1058) (1075:1075:1075)) + (PORT clk (1044:1044:1044) (1063:1063:1063)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (1058:1058:1058) (1075:1075:1075)) + (PORT clk (1044:1044:1044) (1063:1063:1063)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_b_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_b_register) (DELAY (ABSOLUTE - (PORT clk (1053:1053:1053) (1072:1072:1072)) + (PORT clk (1039:1039:1039) (1060:1060:1060)) (IOPATH (posedge clk) q (164:164:164) (166:166:166)) ) ) @@ -44334,1029 +39970,24 @@ (HOLD d (posedge clk) (90:90:90)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Mux0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (798:798:798) (926:926:926)) - (PORT datab (532:532:532) (633:633:633)) - (PORT datac (791:791:791) (901:901:901)) - (PORT datad (781:781:781) (900:900:900)) - (IOPATH dataa combout (188:188:188) (184:184:184)) - (IOPATH datab combout (190:190:190) (188:188:188)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Mux0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (841:841:841) (994:994:994)) - (PORT datab (530:530:530) (632:632:632)) - (PORT datac (833:833:833) (959:959:959)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (169:169:169) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[7\]\~112) - (DELAY - (ABSOLUTE - (PORT dataa (826:826:826) (971:971:971)) - (PORT datab (666:666:666) (787:787:787)) - (PORT datac (91:91:91) (113:113:113)) - (PORT datad (91:91:91) (108:108:108)) - (IOPATH dataa combout (181:181:181) (175:175:175)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[7\]\~94) - (DELAY - (ABSOLUTE - (PORT dataa (745:745:745) (854:854:854)) - (PORT datab (484:484:484) (576:576:576)) - (PORT datac (89:89:89) (110:110:110)) - (PORT datad (729:729:729) (831:831:831)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[7\]\~102) - (DELAY - (ABSOLUTE - (PORT datac (100:100:100) (121:121:121)) - (PORT datad (430:430:430) (487:487:487)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[7\]) - (DELAY - (ABSOLUTE - (PORT dataa (532:532:532) (616:616:616)) - (PORT datab (121:121:121) (152:152:152)) - (PORT datac (125:125:125) (161:161:161)) - (PORT datad (480:480:480) (551:551:551)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (916:916:916) (903:903:903)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (432:432:432) (460:460:460)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[7\]\~5) - (DELAY - (ABSOLUTE - (PORT datab (638:638:638) (735:735:735)) - (PORT datac (527:527:527) (622:622:622)) - (PORT datad (193:193:193) (224:224:224)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[7\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (145:145:145) (197:197:197)) - (PORT datab (377:377:377) (445:445:445)) - (PORT datac (457:457:457) (523:523:523)) - (PORT datad (89:89:89) (107:107:107)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (907:907:907) (912:912:912)) - (PORT asdata (285:285:285) (306:306:306)) - (PORT clrn (918:918:918) (903:903:903)) - (PORT ena (800:800:800) (873:873:873)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal77\~0) - (DELAY - (ABSOLUTE - (PORT dataa (394:394:394) (483:483:483)) - (PORT datab (684:684:684) (818:818:818)) - (PORT datac (539:539:539) (638:638:638)) - (PORT datad (758:758:758) (907:907:907)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~5) - (DELAY - (ABSOLUTE - (PORT dataa (389:389:389) (463:463:463)) - (PORT datab (553:553:553) (661:661:661)) - (PORT datac (624:624:624) (727:727:727)) - (PORT datad (648:648:648) (766:766:766)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla31pla33M4T1_3) - (DELAY - (ABSOLUTE - (PORT dataa (398:398:398) (470:470:470)) - (PORT datab (197:197:197) (244:244:244)) - (PORT datac (595:595:595) (689:689:689)) - (PORT datad (962:962:962) (1116:1116:1116)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (542:542:542) (628:628:628)) - (PORT datab (625:625:625) (719:719:719)) - (PORT datac (611:611:611) (714:714:714)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (965:965:965) (1112:1112:1112)) - (PORT datab (590:590:590) (722:722:722)) - (PORT datac (677:677:677) (795:795:795)) - (PORT datad (620:620:620) (714:714:714)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (962:962:962) (1108:1108:1108)) - (PORT datab (197:197:197) (244:244:244)) - (PORT datac (865:865:865) (1010:1010:1010)) - (PORT datad (607:607:607) (695:695:695)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (124:124:124) (158:158:158)) - (PORT datab (585:585:585) (684:684:684)) - (PORT datac (601:601:601) (700:700:700)) - (PORT datad (605:605:605) (686:686:686)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (476:476:476) (551:551:551)) - (PORT datab (821:821:821) (960:960:960)) - (PORT datac (435:435:435) (510:510:510)) - (PORT datad (467:467:467) (542:542:542)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~7) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (134:134:134)) - (PORT datab (102:102:102) (129:129:129)) - (PORT datac (88:88:88) (110:110:110)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]\~50) - (DELAY - (ABSOLUTE - (PORT datac (600:600:600) (730:730:730)) - (PORT datad (576:576:576) (691:691:691)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]\~52) - (DELAY - (ABSOLUTE - (PORT dataa (204:204:204) (250:250:250)) - (PORT datab (524:524:524) (628:628:628)) - (PORT datad (91:91:91) (108:108:108)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (914:914:914) (918:918:918)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (910:910:910) (915:915:915)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]\~48) - (DELAY - (ABSOLUTE - (PORT dataa (120:120:120) (158:158:158)) - (PORT datab (424:424:424) (522:522:522)) - (PORT datac (757:757:757) (913:913:913)) - (PORT datad (864:864:864) (1018:1018:1018)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[2\]\~49) - (DELAY - (ABSOLUTE - (PORT dataa (178:178:178) (219:219:219)) - (PORT datab (116:116:116) (144:144:144)) - (PORT datad (406:406:406) (496:496:496)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH datab combout (190:190:190) (181:181:181)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (914:914:914) (918:918:918)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (909:909:909) (914:914:914)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (1321:1321:1321) (1555:1555:1555)) - (PORT datab (129:129:129) (177:177:177)) - (PORT datac (303:303:303) (362:362:362)) - (PORT datad (707:707:707) (810:810:810)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~57) - (DELAY - (ABSOLUTE - (PORT datab (521:521:521) (629:629:629)) - (PORT datad (414:414:414) (506:506:506)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~58) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (136:136:136)) - (PORT datab (342:342:342) (405:405:405)) - (PORT datad (525:525:525) (620:620:620)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH datab combout (190:190:190) (181:181:181)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (911:911:911) (916:916:916)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~59) - (DELAY - (ABSOLUTE - (PORT dataa (253:253:253) (329:329:329)) - (PORT datab (353:353:353) (428:428:428)) - (PORT datac (321:321:321) (387:387:387)) - (PORT datad (398:398:398) (474:474:474)) - (IOPATH dataa combout (186:186:186) (175:175:175)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~131) - (DELAY - (ABSOLUTE - (PORT dataa (238:238:238) (308:308:308)) - (PORT datab (176:176:176) (216:216:216)) - (PORT datad (141:141:141) (183:183:183)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~60) - (DELAY - (ABSOLUTE - (PORT dataa (447:447:447) (548:548:548)) - (PORT datab (575:575:575) (662:662:662)) - (PORT datad (336:336:336) (383:383:383)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (910:910:910) (916:916:916)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (625:625:625) (737:737:737)) - (PORT datab (129:129:129) (177:177:177)) - (PORT datac (298:298:298) (357:357:357)) - (PORT datad (293:293:293) (342:342:342)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]\~53) - (DELAY - (ABSOLUTE - (PORT datac (601:601:601) (730:730:730)) - (PORT datad (575:575:575) (689:689:689)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]\~55) - (DELAY - (ABSOLUTE - (PORT dataa (122:122:122) (161:161:161)) - (PORT datab (199:199:199) (234:234:234)) - (PORT datac (489:489:489) (592:592:592)) - (PORT datad (169:169:169) (198:198:198)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]\~56) - (DELAY - (ABSOLUTE - (PORT datab (527:527:527) (632:632:632)) - (PORT datad (172:172:172) (203:203:203)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (914:914:914) (918:918:918)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (910:910:910) (915:915:915)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]\~54) - (DELAY - (ABSOLUTE - (PORT dataa (206:206:206) (252:252:252)) - (PORT datab (528:528:528) (632:632:632)) - (PORT datad (103:103:103) (120:120:120)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (914:914:914) (918:918:918)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (910:910:910) (915:915:915)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (132:132:132) (183:183:183)) - (PORT datab (131:131:131) (180:180:180)) - (PORT datac (296:296:296) (342:342:342)) - (PORT datad (291:291:291) (332:332:332)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~68) - (DELAY - (ABSOLUTE - (PORT dataa (523:523:523) (627:627:627)) - (PORT datab (445:445:445) (548:548:548)) - (PORT datac (498:498:498) (598:598:598)) - (PORT datad (422:422:422) (528:528:528)) - (IOPATH dataa combout (170:170:170) (165:165:165)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~69) - (DELAY - (ABSOLUTE - (PORT dataa (186:186:186) (226:226:226)) - (PORT datab (397:397:397) (494:494:494)) - (PORT datad (311:311:311) (362:362:362)) - (IOPATH dataa combout (166:166:166) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~70) - (DELAY - (ABSOLUTE - (PORT dataa (114:114:114) (150:150:150)) - (PORT datab (106:106:106) (135:135:135)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (196:196:196) (192:192:192)) - (IOPATH datac combout (190:190:190) (195:195:195)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (914:914:914) (918:918:918)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (909:909:909) (914:914:914)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~61) - (DELAY - (ABSOLUTE - (PORT datac (134:134:134) (177:177:177)) - (PORT datad (440:440:440) (513:513:513)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~62) - (DELAY - (ABSOLUTE - (PORT dataa (367:367:367) (450:450:450)) - (PORT datab (179:179:179) (219:219:219)) - (PORT datac (346:346:346) (420:420:420)) - (PORT datad (340:340:340) (404:404:404)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~64) - (DELAY - (ABSOLUTE - (PORT dataa (111:111:111) (145:145:145)) - (PORT datab (248:248:248) (310:310:310)) - (PORT datac (188:188:188) (220:220:220)) - (PORT datad (104:104:104) (127:127:127)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~65) - (DELAY - (ABSOLUTE - (PORT dataa (384:384:384) (486:486:486)) - (PORT datab (269:269:269) (336:336:336)) - (PORT datac (300:300:300) (353:353:353)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Selector13\~0) - (DELAY - (ABSOLUTE - (PORT dataa (411:411:411) (507:507:507)) - (PORT datab (428:428:428) (525:525:525)) - (PORT datad (523:523:523) (618:618:618)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~66) - (DELAY - (ABSOLUTE - (PORT dataa (174:174:174) (211:211:211)) - (PORT datad (344:344:344) (402:402:402)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (913:913:913) (917:917:917)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (909:909:909) (914:914:914)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~38) - (DELAY - (ABSOLUTE - (PORT dataa (930:930:930) (1056:1056:1056)) - (PORT datab (322:322:322) (390:390:390)) - (PORT datac (601:601:601) (690:690:690)) - (PORT datad (117:117:117) (153:153:153)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~39) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (135:135:135)) - (PORT datab (339:339:339) (397:397:397)) - (PORT datac (89:89:89) (111:111:111)) - (PORT datad (312:312:312) (363:363:363)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~104) - (DELAY - (ABSOLUTE - (PORT datab (674:674:674) (795:795:795)) - (PORT datac (364:364:364) (433:433:433)) - (PORT datad (776:776:776) (881:881:881)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.datain_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (515:515:515) (582:582:582)) - (PORT clk (1087:1087:1087) (1106:1106:1106)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (756:756:756) (869:869:869)) - (PORT d[1] (1131:1131:1131) (1346:1346:1346)) - (PORT d[2] (1781:1781:1781) (2038:2038:2038)) - (PORT d[3] (1638:1638:1638) (1913:1913:1913)) - (PORT d[4] (1489:1489:1489) (1740:1740:1740)) - (PORT d[5] (1662:1662:1662) (1928:1928:1928)) - (PORT d[6] (1114:1114:1114) (1285:1285:1285)) - (PORT d[7] (1518:1518:1518) (1718:1718:1718)) - (PORT d[8] (1996:1996:1996) (2341:2341:2341)) - (PORT d[9] (919:919:919) (1060:1060:1060)) - (PORT d[10] (2974:2974:2974) (3396:3396:3396)) - (PORT d[11] (1099:1099:1099) (1281:1281:1281)) - (PORT d[12] (1107:1107:1107) (1276:1276:1276)) - (PORT clk (1085:1085:1085) (1104:1104:1104)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (686:686:686) (730:730:730)) - (PORT clk (1085:1085:1085) (1104:1104:1104)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1087:1087:1087) (1106:1106:1106)) - (PORT d[0] (1382:1382:1382) (1484:1484:1484)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1088:1088:1088) (1107:1107:1107)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1088:1088:1088) (1107:1107:1107)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1088:1088:1088) (1107:1107:1107)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1088:1088:1088) (1107:1107:1107)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1067:1067:1067) (1085:1085:1085)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (607:607:607) (617:617:617)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (608:608:608) (618:618:618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (608:608:608) (618:618:618)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (608:608:608) (618:618:618)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (383:383:383) (431:431:431)) - (PORT clk (1096:1096:1096) (1113:1113:1113)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (701:701:701) (805:805:805)) - (PORT d[1] (1229:1229:1229) (1458:1458:1458)) - (PORT d[2] (713:713:713) (805:805:805)) - (PORT d[3] (726:726:726) (840:840:840)) - (PORT d[4] (1534:1534:1534) (1791:1791:1791)) - (PORT d[5] (2015:2015:2015) (2334:2334:2334)) - (PORT d[6] (770:770:770) (891:891:891)) - (PORT d[7] (1699:1699:1699) (1922:1922:1922)) - (PORT d[8] (552:552:552) (633:633:633)) - (PORT d[9] (736:736:736) (855:855:855)) - (PORT d[10] (789:789:789) (910:910:910)) - (PORT d[11] (1418:1418:1418) (1644:1644:1644)) - (PORT d[12] (926:926:926) (1070:1070:1070)) + (PORT d[0] (933:933:933) (1061:1061:1061)) + (PORT d[1] (733:733:733) (837:837:837)) + (PORT d[2] (1369:1369:1369) (1616:1616:1616)) + (PORT d[3] (1563:1563:1563) (1815:1815:1815)) + (PORT d[4] (572:572:572) (666:666:666)) + (PORT d[5] (833:833:833) (953:953:953)) + (PORT d[6] (1944:1944:1944) (2188:2188:2188)) + (PORT d[7] (1047:1047:1047) (1238:1238:1238)) + (PORT d[8] (871:871:871) (995:995:995)) + (PORT d[9] (2019:2019:2019) (2366:2366:2366)) + (PORT d[10] (540:540:540) (621:621:621)) + (PORT d[11] (839:839:839) (949:949:949)) + (PORT d[12] (1124:1124:1124) (1280:1280:1280)) (PORT clk (1094:1094:1094) (1111:1111:1111)) ) ) @@ -45366,70 +39997,27 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.we_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) (DELAY (ABSOLUTE - (PORT d[0] (534:534:534) (564:564:564)) (PORT clk (1094:1094:1094) (1111:1111:1111)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1096:1096:1096) (1113:1113:1113)) - (PORT d[0] (811:811:811) (848:848:848)) + (PORT d[0] (1440:1440:1440) (1311:1311:1311)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_a) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1097:1097:1097) (1114:1114:1114)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1114:1114:1114)) + (PORT clk (1095:1095:1095) (1112:1112:1112)) (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) ) ) ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1114:1114:1114)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1097:1097:1097) (1114:1114:1114)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) (DELAY (ABSOLUTE (PORT clk (1076:1076:1076) (1092:1092:1092)) @@ -45443,7 +40031,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) (DELAY (ABSOLUTE (PORT clk (616:616:616) (624:624:624)) @@ -45452,7 +40040,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) (DELAY (ABSOLUTE (PORT clk (617:617:617) (625:625:625)) @@ -45461,7 +40049,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) (DELAY (ABSOLUTE (PORT clk (617:617:617) (625:625:625)) @@ -45471,7 +40059,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) (DELAY (ABSOLUTE (PORT clk (617:617:617) (625:625:625)) @@ -45480,12 +40068,1222 @@ ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.datain_a_register) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector4\~0) (DELAY (ABSOLUTE - (PORT d[0] (515:515:515) (584:584:584)) - (PORT clk (1090:1090:1090) (1108:1108:1108)) + (PORT dataa (788:788:788) (961:961:961)) + (PORT datab (472:472:472) (537:537:537)) + (PORT datac (827:827:827) (968:968:968)) + (PORT datad (625:625:625) (711:711:711)) + (IOPATH dataa combout (170:170:170) (165:165:165)) + (IOPATH datab combout (169:169:169) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector4\~1) + (DELAY + (ABSOLUTE + (PORT dataa (643:643:643) (746:746:746)) + (PORT datab (575:575:575) (647:647:647)) + (PORT datac (937:937:937) (1070:1070:1070)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (190:190:190) (177:177:177)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~86) + (DELAY + (ABSOLUTE + (PORT dataa (1490:1490:1490) (1751:1751:1751)) + (PORT datab (669:669:669) (796:796:796)) + (PORT datac (89:89:89) (110:110:110)) + (PORT datad (160:160:160) (183:183:183)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (182:182:182) (177:177:177)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~75) + (DELAY + (ABSOLUTE + (PORT dataa (478:478:478) (562:562:562)) + (PORT datab (177:177:177) (213:213:213)) + (PORT datac (464:464:464) (537:537:537)) + (PORT datad (94:94:94) (114:114:114)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~76) + (DELAY + (ABSOLUTE + (PORT dataa (479:479:479) (564:564:564)) + (PORT datab (523:523:523) (620:620:620)) + (PORT datac (855:855:855) (968:968:968)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[4\]) + (DELAY + (ABSOLUTE + (PORT dataa (384:384:384) (454:454:454)) + (PORT datab (206:206:206) (250:250:250)) + (PORT datac (776:776:776) (885:885:885)) + (PORT datad (457:457:457) (522:522:522)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (917:917:917) (904:904:904)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (421:421:421) (449:449:449)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[4\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (293:293:293) (345:345:345)) + (PORT datab (202:202:202) (260:260:260)) + (PORT datad (304:304:304) (354:354:354)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[4\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (394:394:394) (468:468:468)) + (PORT datab (361:361:361) (427:427:427)) + (PORT datac (348:348:348) (402:402:402)) + (PORT datad (937:937:937) (1066:1066:1066)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (920:920:920) (928:928:928)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (909:909:909) (896:896:896)) + (PORT ena (738:738:738) (795:795:795)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal32\~0) + (DELAY + (ABSOLUTE + (PORT datab (667:667:667) (803:803:803)) + (PORT datad (692:692:692) (826:826:826)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal41\~1) + (DELAY + (ABSOLUTE + (PORT dataa (258:258:258) (330:330:330)) + (PORT datab (266:266:266) (334:334:334)) + (PORT datac (527:527:527) (636:636:636)) + (PORT datad (538:538:538) (644:644:644)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal41\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1456:1456:1456) (1704:1704:1704)) + (PORT datab (350:350:350) (409:409:409)) + (PORT datac (448:448:448) (514:514:514)) + (PORT datad (505:505:505) (577:577:577)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal36\~0) + (DELAY + (ABSOLUTE + (PORT dataa (435:435:435) (539:539:539)) + (PORT datab (1095:1095:1095) (1285:1285:1285)) + (PORT datac (732:732:732) (855:855:855)) + (PORT datad (482:482:482) (543:543:543)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_tbl_cb_set) + (DELAY + (ABSOLUTE + (PORT dataa (559:559:559) (651:651:651)) + (PORT datab (486:486:486) (571:571:571)) + (PORT datac (703:703:703) (798:798:798)) + (PORT datad (360:360:360) (419:419:419)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_tbl_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (929:929:929) (1081:1081:1081)) + (PORT datab (376:376:376) (450:450:450)) + (PORT datac (703:703:703) (797:797:797)) + (PORT datad (349:349:349) (412:412:412)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|decode_state_\|DFFE_instCB) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (909:909:909) (896:896:896)) + (PORT ena (406:406:406) (423:423:423)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal52\~0) + (DELAY + (ABSOLUTE + (PORT dataa (571:571:571) (686:686:686)) + (PORT datab (558:558:558) (666:666:666)) + (PORT datac (531:531:531) (640:640:640)) + (PORT datad (535:535:535) (643:643:643)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (395:395:395) (490:490:490)) + (PORT datab (293:293:293) (337:337:337)) + (PORT datac (634:634:634) (744:744:744)) + (PORT datad (1017:1017:1017) (1165:1165:1165)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_tbl_ed_set) + (DELAY + (ABSOLUTE + (PORT dataa (932:932:932) (1084:1084:1084)) + (PORT datab (521:521:521) (608:608:608)) + (PORT datac (536:536:536) (627:627:627)) + (PORT datad (203:203:203) (256:256:256)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|decode_state_\|DFFE_instED) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (909:909:909) (896:896:896)) + (PORT ena (406:406:406) (423:423:423)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|table_xx\~0) + (DELAY + (ABSOLUTE + (PORT dataa (159:159:159) (217:217:217)) + (PORT datad (203:203:203) (248:248:248)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal34\~0) + (DELAY + (ABSOLUTE + (PORT dataa (517:517:517) (621:621:621)) + (PORT datab (352:352:352) (412:412:412)) + (PORT datac (296:296:296) (341:341:341)) + (PORT datad (378:378:378) (441:441:441)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~6) + (DELAY + (ABSOLUTE + (PORT dataa (644:644:644) (756:756:756)) + (PORT datab (949:949:949) (1086:1086:1086)) + (PORT datac (428:428:428) (485:485:485)) + (PORT datad (727:727:727) (854:854:854)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~5) + (DELAY + (ABSOLUTE + (PORT dataa (747:747:747) (887:887:887)) + (PORT datab (377:377:377) (453:453:453)) + (PORT datac (606:606:606) (694:694:694)) + (PORT datad (500:500:500) (586:586:586)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~4) + (DELAY + (ABSOLUTE + (PORT dataa (461:461:461) (545:545:545)) + (PORT datab (703:703:703) (827:827:827)) + (PORT datac (533:533:533) (615:615:615)) + (PORT datad (371:371:371) (437:437:437)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~2) + (DELAY + (ABSOLUTE + (PORT dataa (744:744:744) (883:883:883)) + (PORT datab (378:378:378) (451:451:451)) + (PORT datac (465:465:465) (536:536:536)) + (PORT datad (483:483:483) (553:553:553)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~3) + (DELAY + (ABSOLUTE + (PORT dataa (905:905:905) (1034:1034:1034)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (526:526:526) (622:622:622)) + (PORT datad (730:730:730) (858:858:858)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~7) + (DELAY + (ABSOLUTE + (PORT dataa (102:102:102) (133:133:133)) + (PORT datab (105:105:105) (134:134:134)) + (PORT datac (316:316:316) (364:364:364)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~8) + (DELAY + (ABSOLUTE + (PORT dataa (429:429:429) (500:500:500)) + (PORT datab (817:817:817) (938:938:938)) + (PORT datac (508:508:508) (583:583:583)) + (PORT datad (372:372:372) (438:438:438)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~9) + (DELAY + (ABSOLUTE + (PORT dataa (645:645:645) (757:757:757)) + (PORT datab (512:512:512) (608:608:608)) + (PORT datac (330:330:330) (387:387:387)) + (PORT datad (933:933:933) (1060:1060:1060)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~10) + (DELAY + (ABSOLUTE + (PORT dataa (742:742:742) (880:880:880)) + (PORT datab (106:106:106) (137:137:137)) + (PORT datac (90:90:90) (112:112:112)) + (PORT datad (726:726:726) (833:833:833)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~16) + (DELAY + (ABSOLUTE + (PORT dataa (479:479:479) (557:557:557)) + (PORT datab (705:705:705) (808:808:808)) + (PORT datac (791:791:791) (907:907:907)) + (PORT datad (103:103:103) (120:120:120)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~17) + (DELAY + (ABSOLUTE + (PORT dataa (545:545:545) (658:658:658)) + (PORT datab (779:779:779) (897:897:897)) + (PORT datac (109:109:109) (134:134:134)) + (PORT datad (352:352:352) (413:413:413)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~15) + (DELAY + (ABSOLUTE + (PORT dataa (657:657:657) (759:759:759)) + (PORT datab (133:133:133) (168:168:168)) + (PORT datac (482:482:482) (559:559:559)) + (PORT datad (92:92:92) (111:111:111)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~18) + (DELAY + (ABSOLUTE + (PORT dataa (175:175:175) (212:212:212)) + (PORT datab (640:640:640) (742:742:742)) + (PORT datac (103:103:103) (124:124:124)) + (PORT datad (317:317:317) (369:369:369)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1035:1035:1035) (1212:1212:1212)) + (PORT datab (671:671:671) (778:778:778)) + (PORT datac (908:908:908) (1082:1082:1082)) + (PORT datad (969:969:969) (1105:1105:1105)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_pc\~3) + (DELAY + (ABSOLUTE + (PORT dataa (359:359:359) (416:416:416)) + (PORT datab (794:794:794) (902:902:902)) + (PORT datac (463:463:463) (540:540:540)) + (PORT datad (355:355:355) (419:419:419)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_pc) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (133:133:133)) + (PORT datab (491:491:491) (573:573:573)) + (PORT datac (299:299:299) (344:344:344)) + (PORT datad (461:461:461) (531:531:531)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_72) + (DELAY + (ABSOLUTE + (PORT dataa (573:573:573) (647:647:647)) + (PORT datac (607:607:607) (697:697:697)) + (PORT datad (510:510:510) (576:576:576)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (569:569:569) (658:658:658)) + (PORT datab (381:381:381) (456:456:456)) + (PORT datac (754:754:754) (850:850:850)) + (PORT datad (350:350:350) (411:411:411)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (909:909:909)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (665:665:665) (730:730:730)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (909:909:909)) + (PORT asdata (279:279:279) (298:298:298)) + (PORT ena (766:766:766) (830:830:830)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (415:415:415)) + (PORT datab (380:380:380) (455:455:455)) + (PORT datad (348:348:348) (409:409:409)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (568:568:568) (657:657:657)) + (PORT datab (199:199:199) (255:255:255)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (131:131:131) (167:167:167)) + (PORT datab (348:348:348) (406:406:406)) + (PORT datac (757:757:757) (854:854:854)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) + (PORT asdata (759:759:759) (862:862:862)) + (PORT ena (649:649:649) (705:705:705)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) + (PORT asdata (760:760:760) (864:864:864)) + (PORT ena (422:422:422) (449:449:449)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~50) + (DELAY + (ABSOLUTE + (PORT dataa (385:385:385) (461:461:461)) + (PORT datab (131:131:131) (179:179:179)) + (PORT datad (127:127:127) (155:155:155)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (909:909:909)) + (PORT asdata (626:626:626) (687:687:687)) + (PORT ena (619:619:619) (671:671:671)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~53) + (DELAY + (ABSOLUTE + (PORT dataa (640:640:640) (753:753:753)) + (PORT datab (621:621:621) (711:711:711)) + (PORT datad (207:207:207) (254:254:254)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (909:909:909)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (800:800:800) (878:878:878)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (909:909:909)) + (PORT asdata (489:489:489) (539:539:539)) + (PORT ena (655:655:655) (714:714:714)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~54) + (DELAY + (ABSOLUTE + (PORT dataa (391:391:391) (468:468:468)) + (PORT datab (129:129:129) (177:177:177)) + (PORT datad (380:380:380) (446:446:446)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (905:905:905) (910:910:910)) + (PORT asdata (764:764:764) (849:849:849)) + (PORT ena (649:649:649) (707:707:707)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (905:905:905) (910:910:910)) + (PORT asdata (768:768:768) (853:853:853)) + (PORT ena (604:604:604) (647:647:647)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~52) + (DELAY + (ABSOLUTE + (PORT dataa (364:364:364) (434:434:434)) + (PORT datab (144:144:144) (182:182:182)) + (PORT datad (118:118:118) (155:155:155)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) + (PORT asdata (642:642:642) (705:705:705)) + (PORT ena (757:757:757) (811:811:811)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) + (PORT asdata (644:644:644) (708:708:708)) + (PORT ena (648:648:648) (700:700:700)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (383:383:383) (456:456:456)) + (PORT datab (131:131:131) (179:179:179)) + (PORT datad (324:324:324) (376:376:376)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~55) + (DELAY + (ABSOLUTE + (PORT dataa (191:191:191) (228:228:228)) + (PORT datab (324:324:324) (379:379:379)) + (PORT datac (276:276:276) (320:320:320)) + (PORT datad (172:172:172) (204:204:204)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT asdata (480:480:480) (523:523:523)) + (PORT ena (406:406:406) (423:423:423)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[5\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (840:840:840) (990:990:990)) + (PORT datab (1225:1225:1225) (1414:1414:1414)) + (PORT datad (732:732:732) (823:823:823)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) + (PORT asdata (512:512:512) (568:568:568)) + (PORT ena (501:501:501) (541:541:541)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (313:313:313) (353:353:353)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (621:621:621) (666:666:666)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~49) + (DELAY + (ABSOLUTE + (PORT dataa (351:351:351) (426:426:426)) + (PORT datab (371:371:371) (434:434:434)) + (PORT datad (118:118:118) (155:155:155)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~56) + (DELAY + (ABSOLUTE + (PORT dataa (454:454:454) (542:542:542)) + (PORT datab (532:532:532) (626:626:626)) + (PORT datac (280:280:280) (317:317:317)) + (PORT datad (183:183:183) (213:213:213)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~57) + (DELAY + (ABSOLUTE + (PORT dataa (347:347:347) (405:405:405)) + (PORT datab (497:497:497) (575:575:575)) + (PORT datac (621:621:621) (721:721:721)) + (PORT datad (292:292:292) (336:336:336)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[5\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (337:337:337) (401:401:401)) + (PORT datab (364:364:364) (432:432:432)) + (PORT datac (277:277:277) (317:317:317)) + (PORT datad (296:296:296) (342:342:342)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[5\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (178:178:178) (215:215:215)) + (PORT datab (337:337:337) (395:395:395)) + (PORT datac (119:119:119) (156:156:156)) + (PORT datad (364:364:364) (443:443:443)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sw1_\|db_down\[5\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (349:349:349) (426:426:426)) + (PORT datab (743:743:743) (844:844:844)) + (PORT datac (514:514:514) (594:594:594)) + (PORT datad (457:457:457) (524:524:524)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_36) + (DELAY + (ABSOLUTE + (PORT dataa (483:483:483) (563:563:563)) + (PORT datab (349:349:349) (415:415:415)) + (PORT datac (620:620:620) (712:712:712)) + (PORT datad (323:323:323) (373:373:373)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|flags_yf) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (913:913:913)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (765:765:765) (833:833:833)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[5\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (460:460:460) (536:536:536)) + (PORT datab (117:117:117) (150:150:150)) + (PORT datac (456:456:456) (534:534:534)) + (PORT datad (106:106:106) (124:124:124)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[5\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (107:107:107) (139:139:139)) + (PORT datab (306:306:306) (354:354:354)) + (PORT datac (1028:1028:1028) (1170:1170:1170)) + (PORT datad (200:200:200) (235:235:235)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[5\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (437:437:437) (510:510:510)) + (PORT datab (205:205:205) (248:248:248)) + (PORT datac (90:90:90) (112:112:112)) + (PORT datad (116:116:116) (139:139:139)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (420:420:420) (489:489:489)) + (PORT clk (1097:1097:1097) (1114:1114:1114)) ) ) (TIMINGCHECK @@ -45494,23 +41292,23 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.addr_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (758:758:758) (875:875:875)) - (PORT d[1] (1852:1852:1852) (2153:2153:2153)) - (PORT d[2] (2023:2023:2023) (2302:2302:2302)) - (PORT d[3] (1638:1638:1638) (1914:1914:1914)) - (PORT d[4] (1483:1483:1483) (1743:1743:1743)) - (PORT d[5] (1676:1676:1676) (1948:1948:1948)) - (PORT d[6] (967:967:967) (1121:1121:1121)) - (PORT d[7] (864:864:864) (987:987:987)) - (PORT d[8] (2007:2007:2007) (2356:2356:2356)) - (PORT d[9] (1837:1837:1837) (2124:2124:2124)) - (PORT d[10] (2979:2979:2979) (3401:3401:3401)) - (PORT d[11] (1122:1122:1122) (1311:1311:1311)) - (PORT d[12] (1098:1098:1098) (1263:1263:1263)) - (PORT clk (1088:1088:1088) (1106:1106:1106)) + (PORT d[0] (2094:2094:2094) (2425:2425:2425)) + (PORT d[1] (713:713:713) (821:821:821)) + (PORT d[2] (695:695:695) (795:795:795)) + (PORT d[3] (1891:1891:1891) (2211:2211:2211)) + (PORT d[4] (2043:2043:2043) (2337:2337:2337)) + (PORT d[5] (2447:2447:2447) (2804:2804:2804)) + (PORT d[6] (759:759:759) (875:875:875)) + (PORT d[7] (1489:1489:1489) (1743:1743:1743)) + (PORT d[8] (1915:1915:1915) (2177:2177:2177)) + (PORT d[9] (858:858:858) (990:990:990)) + (PORT d[10] (2605:2605:2605) (3030:3030:3030)) + (PORT d[11] (2235:2235:2235) (2600:2600:2600)) + (PORT d[12] (859:859:859) (989:989:989)) + (PORT clk (1095:1095:1095) (1112:1112:1112)) ) ) (TIMINGCHECK @@ -45519,11 +41317,11 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.we_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (944:944:944) (1020:1020:1020)) - (PORT clk (1088:1088:1088) (1106:1106:1106)) + (PORT d[0] (849:849:849) (914:914:914)) + (PORT clk (1095:1095:1095) (1112:1112:1112)) ) ) (TIMINGCHECK @@ -45532,60 +41330,60 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.active_core_port_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1090:1090:1090) (1108:1108:1108)) - (PORT d[0] (1118:1118:1118) (1193:1193:1193)) + (PORT clk (1097:1097:1097) (1114:1114:1114)) + (PORT d[0] (1504:1504:1504) (1636:1636:1636)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.wpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1091:1091:1091) (1109:1109:1109)) + (PORT clk (1098:1098:1098) (1115:1115:1115)) (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1091:1091:1091) (1109:1109:1109)) + (PORT clk (1098:1098:1098) (1115:1115:1115)) (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.ftpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1091:1091:1091) (1109:1109:1109)) + (PORT clk (1098:1098:1098) (1115:1115:1115)) (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rwpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1091:1091:1091) (1109:1109:1109)) + (PORT clk (1098:1098:1098) (1115:1115:1115)) (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.dataout_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1070:1070:1070) (1087:1087:1087)) + (PORT clk (1077:1077:1077) (1093:1093:1093)) (IOPATH (posedge clk) q (164:164:164) (167:167:167)) ) ) @@ -45596,49 +41394,49 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.active_core_port_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (610:610:610) (619:619:619)) + (PORT clk (617:617:617) (625:625:625)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (611:611:611) (620:620:620)) + (PORT clk (618:618:618) (626:626:626)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.ftpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (611:611:611) (620:620:620)) + (PORT clk (618:618:618) (626:626:626)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rwpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (611:611:611) (620:620:620)) + (PORT clk (618:618:618) (626:626:626)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (619:619:619) (707:707:707)) - (PORT clk (1090:1090:1090) (1107:1107:1107)) + (PORT d[0] (626:626:626) (729:729:729)) + (PORT clk (1098:1098:1098) (1115:1115:1115)) ) ) (TIMINGCHECK @@ -45647,23 +41445,23 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2084:2084:2084) (2418:2418:2418)) - (PORT d[1] (974:974:974) (1149:1149:1149)) - (PORT d[2] (1121:1121:1121) (1283:1283:1283)) - (PORT d[3] (1195:1195:1195) (1397:1397:1397)) - (PORT d[4] (1263:1263:1263) (1466:1466:1466)) - (PORT d[5] (793:793:793) (940:940:940)) - (PORT d[6] (850:850:850) (989:989:989)) - (PORT d[7] (1005:1005:1005) (1152:1152:1152)) - (PORT d[8] (2103:2103:2103) (2435:2435:2435)) - (PORT d[9] (1804:1804:1804) (2075:2075:2075)) - (PORT d[10] (1840:1840:1840) (2114:2114:2114)) - (PORT d[11] (1182:1182:1182) (1363:1363:1363)) - (PORT d[12] (815:815:815) (935:935:935)) - (PORT clk (1088:1088:1088) (1105:1105:1105)) + (PORT d[0] (1697:1697:1697) (1982:1982:1982)) + (PORT d[1] (549:549:549) (633:633:633)) + (PORT d[2] (692:692:692) (803:803:803)) + (PORT d[3] (1920:1920:1920) (2244:2244:2244)) + (PORT d[4] (580:580:580) (680:680:680)) + (PORT d[5] (821:821:821) (935:935:935)) + (PORT d[6] (729:729:729) (841:841:841)) + (PORT d[7] (1493:1493:1493) (1753:1753:1753)) + (PORT d[8] (2065:2065:2065) (2345:2345:2345)) + (PORT d[9] (843:843:843) (971:971:971)) + (PORT d[10] (2613:2613:2613) (3034:3034:3034)) + (PORT d[11] (2239:2239:2239) (2604:2604:2604)) + (PORT d[12] (835:835:835) (965:965:965)) + (PORT clk (1096:1096:1096) (1113:1113:1113)) ) ) (TIMINGCHECK @@ -45672,11 +41470,11 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.we_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (914:914:914) (988:988:988)) - (PORT clk (1088:1088:1088) (1105:1105:1105)) + (PORT d[0] (1005:1005:1005) (1074:1074:1074)) + (PORT clk (1096:1096:1096) (1113:1113:1113)) ) ) (TIMINGCHECK @@ -45685,57 +41483,4742 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1090:1090:1090) (1107:1107:1107)) - (PORT d[0] (1497:1497:1497) (1612:1612:1612)) + (PORT clk (1098:1098:1098) (1115:1115:1115)) + (PORT d[0] (1378:1378:1378) (1477:1477:1477)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1091:1091:1091) (1108:1108:1108)) + (PORT clk (1099:1099:1099) (1116:1116:1116)) (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1091:1091:1091) (1108:1108:1108)) + (PORT clk (1099:1099:1099) (1116:1116:1116)) (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1091:1091:1091) (1108:1108:1108)) + (PORT clk (1099:1099:1099) (1116:1116:1116)) (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1091:1091:1091) (1108:1108:1108)) + (PORT clk (1099:1099:1099) (1116:1116:1116)) (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1078:1078:1078) (1094:1094:1094)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (618:618:618) (626:626:626)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (619:619:619) (627:627:627)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (619:619:619) (627:627:627)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (619:619:619) (627:627:627)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (412:412:412) (479:479:479)) + (PORT clk (1096:1096:1096) (1114:1114:1114)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2096:2096:2096) (2430:2430:2430)) + (PORT d[1] (723:723:723) (839:839:839)) + (PORT d[2] (890:890:890) (1021:1021:1021)) + (PORT d[3] (1731:1731:1731) (2020:2020:2020)) + (PORT d[4] (2029:2029:2029) (2325:2325:2325)) + (PORT d[5] (2284:2284:2284) (2622:2622:2622)) + (PORT d[6] (913:913:913) (1050:1050:1050)) + (PORT d[7] (1311:1311:1311) (1546:1546:1546)) + (PORT d[8] (1908:1908:1908) (2169:2169:2169)) + (PORT d[9] (1015:1015:1015) (1171:1171:1171)) + (PORT d[10] (2432:2432:2432) (2828:2828:2828)) + (PORT d[11] (2054:2054:2054) (2387:2387:2387)) + (PORT d[12] (990:990:990) (1139:1139:1139)) + (PORT clk (1094:1094:1094) (1112:1112:1112)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (852:852:852) (916:916:916)) + (PORT clk (1094:1094:1094) (1112:1112:1112)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1096:1096:1096) (1114:1114:1114)) + (PORT d[0] (1698:1698:1698) (1848:1848:1848)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1076:1076:1076) (1093:1093:1093)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (616:616:616) (625:625:625)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (617:617:617) (626:626:626)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (617:617:617) (626:626:626)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (617:617:617) (626:626:626)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (384:384:384) (439:439:439)) + (PORT clk (1093:1093:1093) (1110:1110:1110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1910:1910:1910) (2218:2218:2218)) + (PORT d[1] (1098:1098:1098) (1275:1275:1275)) + (PORT d[2] (918:918:918) (1065:1065:1065)) + (PORT d[3] (1725:1725:1725) (2022:2022:2022)) + (PORT d[4] (1860:1860:1860) (2134:2134:2134)) + (PORT d[5] (2251:2251:2251) (2582:2582:2582)) + (PORT d[6] (1092:1092:1092) (1253:1253:1253)) + (PORT d[7] (1300:1300:1300) (1527:1527:1527)) + (PORT d[8] (1720:1720:1720) (1956:1956:1956)) + (PORT d[9] (1210:1210:1210) (1404:1404:1404)) + (PORT d[10] (2259:2259:2259) (2633:2633:2633)) + (PORT d[11] (1869:1869:1869) (2178:2178:2178)) + (PORT d[12] (987:987:987) (1130:1130:1130)) + (PORT clk (1091:1091:1091) (1108:1108:1108)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1005:1005:1005) (1090:1090:1090)) + (PORT clk (1091:1091:1091) (1108:1108:1108)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1093:1093:1093) (1110:1110:1110)) + (PORT d[0] (1496:1496:1496) (1599:1599:1599)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1094:1094:1094) (1111:1111:1111)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1094:1094:1094) (1111:1111:1111)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1094:1094:1094) (1111:1111:1111)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1094:1094:1094) (1111:1111:1111)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1073:1073:1073) (1089:1089:1089)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (621:621:621)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (614:614:614) (622:622:622)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (614:614:614) (622:622:622)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (614:614:614) (622:622:622)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (470:470:470) (546:546:546)) + (PORT datab (812:812:812) (950:950:950)) + (PORT datac (449:449:449) (514:514:514)) + (PORT datad (825:825:825) (962:962:962)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (190:190:190) (188:188:188)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (682:682:682) (779:779:779)) + (PORT datab (681:681:681) (779:779:779)) + (PORT datac (1004:1004:1004) (1168:1168:1168)) + (PORT datad (160:160:160) (185:185:185)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1586:1586:1586) (1848:1848:1848)) + (PORT d[1] (1267:1267:1267) (1465:1465:1465)) + (PORT d[2] (1421:1421:1421) (1626:1626:1626)) + (PORT d[3] (1493:1493:1493) (1734:1734:1734)) + (PORT d[4] (1494:1494:1494) (1720:1720:1720)) + (PORT d[5] (1638:1638:1638) (1895:1895:1895)) + (PORT d[6] (1708:1708:1708) (1948:1948:1948)) + (PORT d[7] (1131:1131:1131) (1334:1334:1334)) + (PORT d[8] (1349:1349:1349) (1530:1530:1530)) + (PORT d[9] (1779:1779:1779) (2043:2043:2043)) + (PORT d[10] (2485:2485:2485) (2882:2882:2882)) + (PORT d[11] (1778:1778:1778) (2068:2068:2068)) + (PORT d[12] (1574:1574:1574) (1785:1785:1785)) + (PORT clk (1104:1104:1104) (1122:1122:1122)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1104:1104:1104) (1122:1122:1122)) + (PORT d[0] (1596:1596:1596) (1770:1770:1770)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1105:1105:1105) (1123:1123:1123)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1086:1086:1086) (1103:1103:1103)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (626:626:626) (635:635:635)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (627:627:627) (636:636:636)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (627:627:627) (636:636:636)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (627:627:627) (636:636:636)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1132:1132:1132) (1291:1291:1291)) + (PORT d[1] (901:901:901) (1038:1038:1038)) + (PORT d[2] (1375:1375:1375) (1597:1597:1597)) + (PORT d[3] (1408:1408:1408) (1638:1638:1638)) + (PORT d[4] (704:704:704) (803:803:803)) + (PORT d[5] (864:864:864) (991:991:991)) + (PORT d[6] (1478:1478:1478) (1666:1666:1666)) + (PORT d[7] (1028:1028:1028) (1210:1210:1210)) + (PORT d[8] (898:898:898) (1029:1029:1029)) + (PORT d[9] (1939:1939:1939) (2265:2265:2265)) + (PORT d[10] (697:697:697) (800:800:800)) + (PORT d[11] (667:667:667) (758:758:758)) + (PORT d[12] (920:920:920) (1041:1041:1041)) + (PORT clk (1096:1096:1096) (1113:1113:1113)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1096:1096:1096) (1113:1113:1113)) + (PORT d[0] (1466:1466:1466) (1333:1333:1333)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1114:1114:1114)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1078:1078:1078) (1094:1094:1094)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (618:618:618) (626:626:626)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (619:619:619) (627:627:627)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (619:619:619) (627:627:627)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (619:619:619) (627:627:627)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (631:631:631) (710:710:710)) + (PORT clk (1094:1094:1094) (1111:1111:1111)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1722:1722:1722) (2006:2006:2006)) + (PORT d[1] (1740:1740:1740) (2004:2004:2004)) + (PORT d[2] (1100:1100:1100) (1273:1273:1273)) + (PORT d[3] (1353:1353:1353) (1595:1595:1595)) + (PORT d[4] (1685:1685:1685) (1936:1936:1936)) + (PORT d[5] (1824:1824:1824) (2099:2099:2099)) + (PORT d[6] (1363:1363:1363) (1555:1555:1555)) + (PORT d[7] (1267:1267:1267) (1494:1494:1494)) + (PORT d[8] (1551:1551:1551) (1763:1763:1763)) + (PORT d[9] (1493:1493:1493) (1727:1727:1727)) + (PORT d[10] (2236:2236:2236) (2606:2606:2606)) + (PORT d[11] (1863:1863:1863) (2171:2171:2171)) + (PORT d[12] (1190:1190:1190) (1366:1366:1366)) + (PORT clk (1092:1092:1092) (1109:1109:1109)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1927:1927:1927) (2117:2117:2117)) + (PORT clk (1092:1092:1092) (1109:1109:1109)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1094:1094:1094) (1111:1111:1111)) + (PORT d[0] (1885:1885:1885) (2045:2045:2045)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1095:1095:1095) (1112:1112:1112)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1095:1095:1095) (1112:1112:1112)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1095:1095:1095) (1112:1112:1112)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1095:1095:1095) (1112:1112:1112)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1049:1049:1049) (1068:1068:1068)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1567:1567:1567) (1828:1828:1828)) + (PORT clk (1054:1054:1054) (1071:1071:1071)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2337:2337:2337) (2629:2629:2629)) + (PORT d[1] (2358:2358:2358) (2686:2686:2686)) + (PORT d[2] (2283:2283:2283) (2577:2577:2577)) + (PORT d[3] (2346:2346:2346) (2679:2679:2679)) + (PORT d[4] (2339:2339:2339) (2664:2664:2664)) + (PORT d[5] (2412:2412:2412) (2745:2745:2745)) + (PORT d[6] (2327:2327:2327) (2625:2625:2625)) + (PORT d[7] (2266:2266:2266) (2577:2577:2577)) + (PORT d[8] (2361:2361:2361) (2662:2662:2662)) + (PORT d[9] (2370:2370:2370) (2684:2684:2684)) + (PORT d[10] (2365:2365:2365) (2688:2688:2688)) + (PORT d[11] (2415:2415:2415) (2742:2742:2742)) + (PORT d[12] (2221:2221:2221) (2518:2518:2518)) + (PORT clk (1051:1051:1051) (1070:1070:1070)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1054:1054:1054) (1071:1071:1071)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1055:1055:1055) (1072:1072:1072)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1055:1055:1055) (1072:1072:1072)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1055:1055:1055) (1072:1072:1072)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1055:1055:1055) (1072:1072:1072)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (701:701:701) (795:795:795)) + (PORT clk (1102:1102:1102) (1119:1119:1119)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1642:1642:1642) (1920:1920:1920)) + (PORT d[1] (1550:1550:1550) (1785:1785:1785)) + (PORT d[2] (1441:1441:1441) (1665:1665:1665)) + (PORT d[3] (1340:1340:1340) (1582:1582:1582)) + (PORT d[4] (1669:1669:1669) (1917:1917:1917)) + (PORT d[5] (1660:1660:1660) (1920:1920:1920)) + (PORT d[6] (1714:1714:1714) (1955:1955:1955)) + (PORT d[7] (1109:1109:1109) (1309:1309:1309)) + (PORT d[8] (1370:1370:1370) (1553:1553:1553)) + (PORT d[9] (1375:1375:1375) (1592:1592:1592)) + (PORT d[10] (2203:2203:2203) (2556:2556:2556)) + (PORT d[11] (1858:1858:1858) (2165:2165:2165)) + (PORT d[12] (1484:1484:1484) (1700:1700:1700)) + (PORT clk (1100:1100:1100) (1117:1117:1117)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1414:1414:1414) (1543:1543:1543)) + (PORT clk (1100:1100:1100) (1117:1117:1117)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1102:1102:1102) (1119:1119:1119)) + (PORT d[0] (2057:2057:2057) (1922:1922:1922)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1103:1103:1103) (1120:1120:1120)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1103:1103:1103) (1120:1120:1120)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1103:1103:1103) (1120:1120:1120)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1103:1103:1103) (1120:1120:1120)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1057:1057:1057) (1076:1076:1076)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1732:1732:1732) (2012:2012:2012)) + (PORT clk (1062:1062:1062) (1079:1079:1079)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2235:2235:2235) (2524:2524:2524)) + (PORT d[1] (2425:2425:2425) (2739:2739:2739)) + (PORT d[2] (2318:2318:2318) (2637:2637:2637)) + (PORT d[3] (2418:2418:2418) (2745:2745:2745)) + (PORT d[4] (2351:2351:2351) (2648:2648:2648)) + (PORT d[5] (2599:2599:2599) (2959:2959:2959)) + (PORT d[6] (2332:2332:2332) (2635:2635:2635)) + (PORT d[7] (2338:2338:2338) (2642:2642:2642)) + (PORT d[8] (2367:2367:2367) (2666:2666:2666)) + (PORT d[9] (2394:2394:2394) (2712:2712:2712)) + (PORT d[10] (2230:2230:2230) (2507:2507:2507)) + (PORT d[11] (2387:2387:2387) (2694:2694:2694)) + (PORT d[12] (2358:2358:2358) (2661:2661:2661)) + (PORT clk (1059:1059:1059) (1078:1078:1078)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1062:1062:1062) (1079:1079:1079)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1063:1063:1063) (1080:1080:1080)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1063:1063:1063) (1080:1080:1080)) + (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1063:1063:1063) (1080:1080:1080)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1063:1063:1063) (1080:1080:1080)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1058:1058:1058) (1077:1077:1077)) + (IOPATH (posedge clk) q (164:164:164) (166:166:166)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Mux2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (702:702:702) (816:816:816)) + (PORT datab (1264:1264:1264) (1473:1473:1473)) + (PORT datac (489:489:489) (558:558:558)) + (PORT datad (617:617:617) (696:696:696)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Mux2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (969:969:969) (1158:1158:1158)) + (PORT datab (789:789:789) (892:892:892)) + (PORT datac (773:773:773) (895:895:895)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[5\]\~87) + (DELAY + (ABSOLUTE + (PORT dataa (1126:1126:1126) (1301:1301:1301)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (707:707:707) (836:836:836)) + (IOPATH dataa combout (188:188:188) (179:179:179)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[5\]\~68) + (DELAY + (ABSOLUTE + (PORT dataa (790:790:790) (907:907:907)) + (PORT datab (704:704:704) (819:819:819)) + (PORT datac (89:89:89) (110:110:110)) + (PORT datad (799:799:799) (899:899:899)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[5\]\~77) + (DELAY + (ABSOLUTE + (PORT datac (101:101:101) (122:122:122)) + (PORT datad (798:798:798) (907:907:907)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[5\]) + (DELAY + (ABSOLUTE + (PORT dataa (913:913:913) (1043:1043:1043)) + (PORT datab (193:193:193) (232:232:232)) + (PORT datac (755:755:755) (864:864:864)) + (PORT datad (370:370:370) (433:433:433)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (917:917:917) (904:904:904)) + (PORT asdata (339:339:339) (366:366:366)) + (PORT ena (421:421:421) (449:449:449)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[5\]\~14) + (DELAY + (ABSOLUTE + (PORT datab (325:325:325) (381:381:381)) + (PORT datac (282:282:282) (325:325:325)) + (PORT datad (129:129:129) (167:167:167)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[5\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (395:395:395) (470:470:470)) + (PORT datab (362:362:362) (429:429:429)) + (PORT datac (342:342:342) (401:401:401)) + (PORT datad (936:936:936) (1064:1064:1064)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT asdata (510:510:510) (563:563:563)) + (PORT clrn (910:910:910) (897:897:897)) + (PORT ena (896:896:896) (975:975:975)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1457:1457:1457) (1704:1704:1704)) + (PORT datab (522:522:522) (606:606:606)) + (PORT datac (650:650:650) (752:752:752)) + (PORT datad (502:502:502) (592:592:592)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (733:733:733) (875:875:875)) + (PORT datab (689:689:689) (802:802:802)) + (PORT datac (524:524:524) (618:618:618)) + (PORT datad (736:736:736) (875:875:875)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1007:1007:1007) (1165:1165:1165)) + (PORT datab (659:659:659) (762:762:762)) + (PORT datac (955:955:955) (1103:1103:1103)) + (PORT datad (690:690:690) (798:798:798)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (136:136:136)) + (PORT datab (646:646:646) (746:746:746)) + (PORT datac (100:100:100) (121:121:121)) + (PORT datad (696:696:696) (801:801:801)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla31pla33M4T1_3) + (DELAY + (ABSOLUTE + (PORT dataa (661:661:661) (764:764:764)) + (PORT datab (1166:1166:1166) (1359:1359:1359)) + (PORT datac (105:105:105) (129:129:129)) + (PORT datad (940:940:940) (1085:1085:1085)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (828:828:828) (959:959:959)) + (PORT datab (101:101:101) (130:130:130)) + (PORT datac (102:102:102) (123:123:123)) + (PORT datad (470:470:470) (534:534:534)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (965:965:965) (1109:1109:1109)) + (PORT datab (945:945:945) (1094:1094:1094)) + (PORT datac (674:674:674) (781:781:781)) + (PORT datad (615:615:615) (705:705:705)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~7) + (DELAY + (ABSOLUTE + (PORT dataa (106:106:106) (137:137:137)) + (PORT datab (101:101:101) (129:129:129)) + (PORT datac (180:180:180) (215:215:215)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~66) + (DELAY + (ABSOLUTE + (PORT dataa (161:161:161) (219:219:219)) + (PORT datab (150:150:150) (202:202:202)) + (PORT datac (748:748:748) (868:868:868)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~80) + (DELAY + (ABSOLUTE + (PORT dataa (539:539:539) (646:646:646)) + (PORT datab (357:357:357) (426:426:426)) + (PORT datac (636:636:636) (762:762:762)) + (PORT datad (562:562:562) (675:675:675)) + (IOPATH dataa combout (172:172:172) (163:163:163)) + (IOPATH datab combout (169:169:169) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~81) + (DELAY + (ABSOLUTE + (PORT dataa (108:108:108) (140:140:140)) + (PORT datac (146:146:146) (195:195:195)) + (PORT datad (525:525:525) (620:620:620)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~82) + (DELAY + (ABSOLUTE + (PORT dataa (354:354:354) (415:415:415)) + (PORT datab (120:120:120) (150:150:150)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (911:911:911)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (892:892:892) (897:897:897)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~84) + (DELAY + (ABSOLUTE + (PORT dataa (794:794:794) (936:936:936)) + (PORT datab (387:387:387) (463:463:463)) + (PORT datad (496:496:496) (589:589:589)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~83) + (DELAY + (ABSOLUTE + (PORT dataa (560:560:560) (678:678:678)) + (PORT datab (1017:1017:1017) (1188:1188:1188)) + (PORT datac (772:772:772) (914:914:914)) + (PORT datad (364:364:364) (434:434:434)) + (IOPATH dataa combout (188:188:188) (203:203:203)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~85) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (137:137:137)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datad (97:97:97) (117:117:117)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (909:909:909)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (897:897:897) (901:901:901)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (315:315:315) (376:376:376)) + (PORT datab (364:364:364) (441:441:441)) + (PORT datac (401:401:401) (452:452:452)) + (PORT datad (117:117:117) (154:154:154)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]\~78) + (DELAY + (ABSOLUTE + (PORT dataa (409:409:409) (496:496:496)) + (PORT datab (542:542:542) (671:671:671)) + (PORT datac (180:180:180) (208:208:208)) + (PORT datad (359:359:359) (433:433:433)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]\~79) + (DELAY + (ABSOLUTE + (PORT dataa (503:503:503) (602:602:602)) + (PORT datad (187:187:187) (218:218:218)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (895:895:895) (899:899:899)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]\~76) + (DELAY + (ABSOLUTE + (PORT dataa (505:505:505) (605:605:605)) + (PORT datab (336:336:336) (390:390:390)) + (PORT datad (435:435:435) (499:499:499)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (895:895:895) (899:899:899)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[0\]\~77) + (DELAY + (ABSOLUTE + (PORT dataa (505:505:505) (605:605:605)) + (PORT datab (343:343:343) (423:423:423)) + (PORT datad (197:197:197) (232:232:232)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (895:895:895) (899:899:899)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (131:131:131) (182:182:182)) + (PORT datab (585:585:585) (705:705:705)) + (PORT datac (568:568:568) (648:648:648)) + (PORT datad (118:118:118) (155:155:155)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (742:742:742) (881:881:881)) + (PORT datab (224:224:224) (291:291:291)) + (PORT datac (517:517:517) (617:617:617)) + (PORT datad (521:521:521) (616:616:616)) + (IOPATH dataa combout (192:192:192) (184:184:184)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\~71) + (DELAY + (ABSOLUTE + (PORT dataa (124:124:124) (158:158:158)) + (PORT datab (391:391:391) (473:473:473)) + (PORT datac (512:512:512) (619:619:619)) + (PORT datad (328:328:328) (383:383:383)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (182:182:182) (177:177:177)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~70) + (DELAY + (ABSOLUTE + (PORT dataa (671:671:671) (790:790:790)) + (PORT datad (551:551:551) (659:659:659)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~72) + (DELAY + (ABSOLUTE + (PORT dataa (164:164:164) (219:219:219)) + (PORT datab (350:350:350) (416:416:416)) + (PORT datac (290:290:290) (337:337:337)) + (PORT datad (327:327:327) (382:382:382)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (388:388:388) (477:477:477)) + (PORT datab (221:221:221) (280:280:280)) + (PORT datac (375:375:375) (454:454:454)) + (PORT datad (1230:1230:1230) (1443:1443:1443)) + (IOPATH dataa combout (166:166:166) (173:173:173)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\~73) + (DELAY + (ABSOLUTE + (PORT dataa (168:168:168) (224:224:224)) + (PORT datab (116:116:116) (145:145:145)) + (PORT datac (493:493:493) (595:595:595)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~74) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (137:137:137)) + (PORT datab (103:103:103) (131:131:131)) + (PORT datad (232:232:232) (290:290:290)) + (IOPATH dataa combout (172:172:172) (163:163:163)) + (IOPATH datab combout (161:161:161) (174:174:174)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (911:911:911)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (892:892:892) (897:897:897)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\~2) + (DELAY + (ABSOLUTE + (PORT datab (371:371:371) (453:453:453)) + (PORT datac (1324:1324:1324) (1563:1563:1563)) + (PORT datad (800:800:800) (933:933:933)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~41) + (DELAY + (ABSOLUTE + (PORT dataa (130:130:130) (181:181:181)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (89:89:89) (110:110:110)) + (PORT datad (578:578:578) (665:665:665)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~89) + (DELAY + (ABSOLUTE + (PORT dataa (359:359:359) (441:441:441)) + (PORT datab (554:554:554) (665:665:665)) + (PORT datac (383:383:383) (468:468:468)) + (PORT datad (518:518:518) (640:640:640)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~90) + (DELAY + (ABSOLUTE + (PORT dataa (885:885:885) (1037:1037:1037)) + (PORT datab (103:103:103) (131:131:131)) + (PORT datac (459:459:459) (526:526:526)) + (PORT datad (468:468:468) (561:561:561)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~91) + (DELAY + (ABSOLUTE + (PORT datab (570:570:570) (646:646:646)) + (PORT datad (501:501:501) (592:592:592)) + (IOPATH datab combout (191:191:191) (181:181:181)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (909:909:909)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (897:897:897) (900:900:900)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~131) + (DELAY + (ABSOLUTE + (PORT dataa (357:357:357) (431:431:431)) + (PORT datab (424:424:424) (492:492:492)) + (PORT datad (238:238:238) (301:301:301)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr16\~3) + (DELAY + (ABSOLUTE + (PORT datac (516:516:516) (611:611:611)) + (PORT datad (533:533:533) (638:638:638)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~86) + (DELAY + (ABSOLUTE + (PORT dataa (517:517:517) (618:618:618)) + (PORT datab (126:126:126) (159:159:159)) + (PORT datac (90:90:90) (112:112:112)) + (PORT datad (359:359:359) (433:433:433)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~87) + (DELAY + (ABSOLUTE + (PORT dataa (479:479:479) (581:581:581)) + (PORT datab (466:466:466) (554:554:554)) + (PORT datac (186:186:186) (223:223:223)) + (PORT datad (523:523:523) (646:646:646)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~88) + (DELAY + (ABSOLUTE + (PORT dataa (482:482:482) (558:558:558)) + (PORT datad (502:502:502) (594:594:594)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (909:909:909)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (897:897:897) (900:900:900)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~43) + (DELAY + (ABSOLUTE + (PORT dataa (783:783:783) (955:955:955)) + (PORT datab (129:129:129) (177:177:177)) + (PORT datac (116:116:116) (156:156:156)) + (PORT datad (325:325:325) (377:377:377)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~44) + (DELAY + (ABSOLUTE + (PORT dataa (172:172:172) (211:211:211)) + (PORT datab (440:440:440) (505:505:505)) + (PORT datac (1672:1672:1672) (1963:1963:1963)) + (PORT datad (90:90:90) (106:106:106)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (538:538:538) (616:616:616)) + (PORT clk (1091:1091:1091) (1108:1108:1108)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1002:1002:1002) (1161:1161:1161)) + (PORT d[1] (2580:2580:2580) (2938:2938:2938)) + (PORT d[2] (1537:1537:1537) (1790:1790:1790)) + (PORT d[3] (1653:1653:1653) (1923:1923:1923)) + (PORT d[4] (2387:2387:2387) (2744:2744:2744)) + (PORT d[5] (1143:1143:1143) (1321:1321:1321)) + (PORT d[6] (1081:1081:1081) (1258:1258:1258)) + (PORT d[7] (1242:1242:1242) (1440:1440:1440)) + (PORT d[8] (1587:1587:1587) (1832:1832:1832)) + (PORT d[9] (1629:1629:1629) (1909:1909:1909)) + (PORT d[10] (1499:1499:1499) (1747:1747:1747)) + (PORT d[11] (1509:1509:1509) (1754:1754:1754)) + (PORT d[12] (2116:2116:2116) (2415:2415:2415)) + (PORT clk (1089:1089:1089) (1106:1106:1106)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (982:982:982) (1062:1062:1062)) + (PORT clk (1089:1089:1089) (1106:1106:1106)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1108:1108:1108)) + (PORT d[0] (1253:1253:1253) (1343:1343:1343)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1071:1071:1071) (1087:1087:1087)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (611:611:611) (619:619:619)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (620:620:620)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (620:620:620)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (620:620:620)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (550:550:550) (634:634:634)) + (PORT clk (1091:1091:1091) (1108:1108:1108)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1960:1960:1960) (2290:2290:2290)) + (PORT d[1] (2579:2579:2579) (2937:2937:2937)) + (PORT d[2] (1547:1547:1547) (1804:1804:1804)) + (PORT d[3] (1435:1435:1435) (1663:1663:1663)) + (PORT d[4] (2359:2359:2359) (2710:2710:2710)) + (PORT d[5] (1170:1170:1170) (1357:1357:1357)) + (PORT d[6] (1898:1898:1898) (2187:2187:2187)) + (PORT d[7] (2062:2062:2062) (2382:2382:2382)) + (PORT d[8] (1847:1847:1847) (2126:2126:2126)) + (PORT d[9] (1447:1447:1447) (1698:1698:1698)) + (PORT d[10] (1343:1343:1343) (1574:1574:1574)) + (PORT d[11] (1509:1509:1509) (1753:1753:1753)) + (PORT d[12] (1959:1959:1959) (2238:2238:2238)) + (PORT clk (1089:1089:1089) (1106:1106:1106)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (995:995:995) (1091:1091:1091)) + (PORT clk (1089:1089:1089) (1106:1106:1106)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1108:1108:1108)) + (PORT d[0] (1429:1429:1429) (1564:1564:1564)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1071:1071:1071) (1087:1087:1087)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (611:611:611) (619:619:619)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (620:620:620)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (620:620:620)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (620:620:620)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (387:387:387) (445:445:445)) + (PORT clk (1092:1092:1092) (1110:1110:1110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (824:824:824) (961:961:961)) + (PORT d[1] (1303:1303:1303) (1485:1485:1485)) + (PORT d[2] (1094:1094:1094) (1279:1279:1279)) + (PORT d[3] (903:903:903) (1058:1058:1058)) + (PORT d[4] (2373:2373:2373) (2724:2724:2724)) + (PORT d[5] (941:941:941) (1089:1089:1089)) + (PORT d[6] (1059:1059:1059) (1234:1234:1234)) + (PORT d[7] (1231:1231:1231) (1428:1428:1428)) + (PORT d[8] (1600:1600:1600) (1841:1841:1841)) + (PORT d[9] (1635:1635:1635) (1915:1915:1915)) + (PORT d[10] (1526:1526:1526) (1777:1777:1777)) + (PORT d[11] (1272:1272:1272) (1478:1478:1478)) + (PORT d[12] (2142:2142:2142) (2446:2446:2446)) + (PORT clk (1090:1090:1090) (1108:1108:1108)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (801:801:801) (860:860:860)) + (PORT clk (1090:1090:1090) (1108:1108:1108)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1110:1110:1110)) + (PORT d[0] (1230:1230:1230) (1314:1314:1314)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1093:1093:1093) (1111:1111:1111)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1093:1093:1093) (1111:1111:1111)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1093:1093:1093) (1111:1111:1111)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1093:1093:1093) (1111:1111:1111)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1072:1072:1072) (1089:1089:1089)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (621:621:621)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (622:622:622)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (622:622:622)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (622:622:622)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (577:577:577) (663:663:663)) + (PORT clk (1091:1091:1091) (1108:1108:1108)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1969:1969:1969) (2303:2303:2303)) + (PORT d[1] (2573:2573:2573) (2930:2930:2930)) + (PORT d[2] (1529:1529:1529) (1781:1781:1781)) + (PORT d[3] (1464:1464:1464) (1705:1705:1705)) + (PORT d[4] (2185:2185:2185) (2510:2510:2510)) + (PORT d[5] (1178:1178:1178) (1367:1367:1367)) + (PORT d[6] (1879:1879:1879) (2160:2160:2160)) + (PORT d[7] (1911:1911:1911) (2212:2212:2212)) + (PORT d[8] (1999:1999:1999) (2292:2292:2292)) + (PORT d[9] (1460:1460:1460) (1718:1718:1718)) + (PORT d[10] (1337:1337:1337) (1564:1564:1564)) + (PORT d[11] (1504:1504:1504) (1751:1751:1751)) + (PORT d[12] (1959:1959:1959) (2237:2237:2237)) + (PORT clk (1089:1089:1089) (1106:1106:1106)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1137:1137:1137) (1248:1248:1248)) + (PORT clk (1089:1089:1089) (1106:1106:1106)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1108:1108:1108)) + (PORT d[0] (1410:1410:1410) (1515:1515:1515)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1071:1071:1071) (1087:1087:1087)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (611:611:611) (619:619:619)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (620:620:620)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (620:620:620)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (620:620:620)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (521:521:521) (610:610:610)) + (PORT datab (690:690:690) (809:809:809)) + (PORT datac (845:845:845) (988:988:988)) + (PORT datad (764:764:764) (862:862:862)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (641:641:641) (740:740:740)) + (PORT datab (655:655:655) (753:753:753)) + (PORT datac (965:965:965) (1100:1100:1100)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1708:1708:1708) (1999:1999:1999)) + (PORT d[1] (542:542:542) (631:631:631)) + (PORT d[2] (1718:1718:1718) (2006:2006:2006)) + (PORT d[3] (544:544:544) (629:629:629)) + (PORT d[4] (556:556:556) (635:635:635)) + (PORT d[5] (659:659:659) (754:754:754)) + (PORT d[6] (560:560:560) (644:644:644)) + (PORT d[7] (1664:1664:1664) (1941:1941:1941)) + (PORT d[8] (2082:2082:2082) (2363:2363:2363)) + (PORT d[9] (653:653:653) (748:748:748)) + (PORT d[10] (2789:2789:2789) (3237:3237:3237)) + (PORT d[11] (839:839:839) (953:953:953)) + (PORT d[12] (1473:1473:1473) (1667:1667:1667)) + (PORT clk (1095:1095:1095) (1112:1112:1112)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1095:1095:1095) (1112:1112:1112)) + (PORT d[0] (697:697:697) (752:752:752)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1096:1096:1096) (1113:1113:1113)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1077:1077:1077) (1093:1093:1093)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (617:617:617) (625:625:625)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (618:618:618) (626:626:626)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (618:618:618) (626:626:626)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (618:618:618) (626:626:626)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (867:867:867) (1004:1004:1004)) + (PORT clk (1096:1096:1096) (1114:1114:1114)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1570:1570:1570) (1806:1806:1806)) + (PORT d[1] (1953:1953:1953) (2234:2234:2234)) + (PORT d[2] (1514:1514:1514) (1759:1759:1759)) + (PORT d[3] (1195:1195:1195) (1389:1389:1389)) + (PORT d[4] (1530:1530:1530) (1767:1767:1767)) + (PORT d[5] (1529:1529:1529) (1784:1784:1784)) + (PORT d[6] (1701:1701:1701) (1956:1956:1956)) + (PORT d[7] (1347:1347:1347) (1562:1562:1562)) + (PORT d[8] (1463:1463:1463) (1676:1676:1676)) + (PORT d[9] (1587:1587:1587) (1849:1849:1849)) + (PORT d[10] (1918:1918:1918) (2251:2251:2251)) + (PORT d[11] (1302:1302:1302) (1509:1509:1509)) + (PORT d[12] (1742:1742:1742) (1982:1982:1982)) + (PORT clk (1094:1094:1094) (1112:1112:1112)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1633:1633:1633) (1804:1804:1804)) + (PORT clk (1094:1094:1094) (1112:1112:1112)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1096:1096:1096) (1114:1114:1114)) + (PORT d[0] (3046:3046:3046) (2802:2802:2802)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1115:1115:1115)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1051:1051:1051) (1071:1071:1071)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (567:567:567) (655:655:655)) + (PORT clk (1056:1056:1056) (1074:1074:1074)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2292:2292:2292) (2592:2592:2592)) + (PORT d[1] (2423:2423:2423) (2764:2764:2764)) + (PORT d[2] (2342:2342:2342) (2675:2675:2675)) + (PORT d[3] (2350:2350:2350) (2687:2687:2687)) + (PORT d[4] (2340:2340:2340) (2660:2660:2660)) + (PORT d[5] (2358:2358:2358) (2672:2672:2672)) + (PORT d[6] (2292:2292:2292) (2589:2589:2589)) + (PORT d[7] (2294:2294:2294) (2626:2626:2626)) + (PORT d[8] (2421:2421:2421) (2754:2754:2754)) + (PORT d[9] (2288:2288:2288) (2603:2603:2603)) + (PORT d[10] (2357:2357:2357) (2647:2647:2647)) + (PORT d[11] (2324:2324:2324) (2629:2629:2629)) + (PORT d[12] (2331:2331:2331) (2633:2633:2633)) + (PORT clk (1053:1053:1053) (1073:1073:1073)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1056:1056:1056) (1074:1074:1074)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1057:1057:1057) (1075:1075:1075)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1057:1057:1057) (1075:1075:1075)) + (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1057:1057:1057) (1075:1075:1075)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1057:1057:1057) (1075:1075:1075)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1052:1052:1052) (1072:1072:1072)) + (IOPATH (posedge clk) q (164:164:164) (166:166:166)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (750:750:750) (851:851:851)) + (PORT clk (1089:1089:1089) (1106:1106:1106)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1769:1769:1769) (2074:2074:2074)) + (PORT d[1] (2296:2296:2296) (2624:2624:2624)) + (PORT d[2] (1364:1364:1364) (1598:1598:1598)) + (PORT d[3] (1444:1444:1444) (1679:1679:1679)) + (PORT d[4] (2335:2335:2335) (2680:2680:2680)) + (PORT d[5] (1327:1327:1327) (1533:1533:1533)) + (PORT d[6] (1864:1864:1864) (2141:2141:2141)) + (PORT d[7] (1895:1895:1895) (2190:2190:2190)) + (PORT d[8] (1404:1404:1404) (1624:1624:1624)) + (PORT d[9] (1423:1423:1423) (1668:1668:1668)) + (PORT d[10] (1614:1614:1614) (1887:1887:1887)) + (PORT d[11] (1325:1325:1325) (1546:1546:1546)) + (PORT d[12] (1923:1923:1923) (2192:2192:2192)) + (PORT clk (1087:1087:1087) (1104:1104:1104)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1138:1138:1138) (1240:1240:1240)) + (PORT clk (1087:1087:1087) (1104:1104:1104)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1089:1089:1089) (1106:1106:1106)) + (PORT d[0] (3147:3147:3147) (3464:3464:3464)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1107:1107:1107)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1107:1107:1107)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1107:1107:1107)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1107:1107:1107)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1044:1044:1044) (1063:1063:1063)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1215:1215:1215) (1427:1427:1427)) + (PORT clk (1049:1049:1049) (1066:1066:1066)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2361:2361:2361) (2700:2700:2700)) + (PORT d[1] (2415:2415:2415) (2755:2755:2755)) + (PORT d[2] (2341:2341:2341) (2666:2666:2666)) + (PORT d[3] (2382:2382:2382) (2732:2732:2732)) + (PORT d[4] (2394:2394:2394) (2732:2732:2732)) + (PORT d[5] (2444:2444:2444) (2794:2794:2794)) + (PORT d[6] (2294:2294:2294) (2594:2594:2594)) + (PORT d[7] (2303:2303:2303) (2623:2623:2623)) + (PORT d[8] (2408:2408:2408) (2711:2711:2711)) + (PORT d[9] (2319:2319:2319) (2618:2618:2618)) + (PORT d[10] (2358:2358:2358) (2679:2679:2679)) + (PORT d[11] (2412:2412:2412) (2745:2745:2745)) + (PORT d[12] (2360:2360:2360) (2675:2675:2675)) + (PORT clk (1046:1046:1046) (1065:1065:1065)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1049:1049:1049) (1066:1066:1066)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1050:1050:1050) (1067:1067:1067)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1050:1050:1050) (1067:1067:1067)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1050:1050:1050) (1067:1067:1067)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1050:1050:1050) (1067:1067:1067)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (671:671:671) (775:775:775)) + (PORT datab (372:372:372) (434:434:434)) + (PORT datac (952:952:952) (1092:1092:1092)) + (PORT datad (674:674:674) (764:764:764)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (196:196:196) (205:205:205)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1462:1462:1462) (1686:1686:1686)) + (PORT d[1] (1937:1937:1937) (2207:2207:2207)) + (PORT d[2] (1325:1325:1325) (1534:1534:1534)) + (PORT d[3] (1371:1371:1371) (1590:1590:1590)) + (PORT d[4] (1510:1510:1510) (1744:1744:1744)) + (PORT d[5] (1499:1499:1499) (1750:1750:1750)) + (PORT d[6] (1867:1867:1867) (2139:2139:2139)) + (PORT d[7] (1194:1194:1194) (1396:1396:1396)) + (PORT d[8] (1453:1453:1453) (1670:1670:1670)) + (PORT d[9] (1759:1759:1759) (2041:2041:2041)) + (PORT d[10] (2176:2176:2176) (2540:2540:2540)) + (PORT d[11] (1467:1467:1467) (1690:1690:1690)) + (PORT d[12] (1566:1566:1566) (1784:1784:1784)) + (PORT clk (1099:1099:1099) (1116:1116:1116)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1099:1099:1099) (1116:1116:1116)) + (PORT d[0] (2519:2519:2519) (2266:2266:2266)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1100:1100:1100) (1117:1117:1117)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1081:1081:1081) (1097:1097:1097)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (621:621:621) (629:629:629)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (622:622:622) (630:630:630)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (622:622:622) (630:630:630)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (622:622:622) (630:630:630)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (763:763:763) (885:885:885)) + (PORT datab (974:974:974) (1120:1120:1120)) + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (1002:1002:1002) (1135:1135:1135)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~83) + (DELAY + (ABSOLUTE + (PORT dataa (106:106:106) (138:138:138)) + (PORT datab (1737:1737:1737) (2025:2025:2025)) + (PORT datac (1036:1036:1036) (1245:1245:1245)) + (PORT datad (89:89:89) (106:106:106)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~45) + (DELAY + (ABSOLUTE + (PORT dataa (641:641:641) (751:751:751)) + (PORT datab (583:583:583) (667:667:667)) + (PORT datac (95:95:95) (120:120:120)) + (PORT datad (866:866:866) (985:985:985)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (920:920:920) (1053:1053:1053)) + (PORT datab (889:889:889) (1014:1014:1014)) + (PORT datac (90:90:90) (111:111:111)) + (PORT datad (993:993:993) (1152:1152:1152)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[0\]) + (DELAY + (ABSOLUTE + (PORT dataa (794:794:794) (911:911:911)) + (PORT datab (1488:1488:1488) (1725:1725:1725)) + (PORT datac (174:174:174) (209:209:209)) + (PORT datad (193:193:193) (227:227:227)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (917:917:917) (904:904:904)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (421:421:421) (449:449:449)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[0\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (315:315:315) (384:384:384)) + (PORT datab (188:188:188) (230:230:230)) + (PORT datac (175:175:175) (209:209:209)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[0\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (778:778:778) (888:888:888)) + (PORT datab (345:345:345) (407:407:407)) + (PORT datac (102:102:102) (123:123:123)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (909:909:909) (896:896:896)) + (PORT ena (921:921:921) (1009:1009:1009)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal3\~2) + (DELAY + (ABSOLUTE + (PORT dataa (956:956:956) (1134:1134:1134)) + (PORT datab (611:611:611) (704:704:704)) + (PORT datac (333:333:333) (390:390:390)) + (PORT datad (608:608:608) (688:688:688)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal43\~0) + (DELAY + (ABSOLUTE + (PORT dataa (746:746:746) (876:876:876)) + (PORT datab (492:492:492) (563:563:563)) + (PORT datac (407:407:407) (507:507:507)) + (PORT datad (596:596:596) (673:673:673)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|test1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (446:446:446) (512:512:512)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (98:98:98) (124:124:124)) + (PORT datad (104:104:104) (121:121:121)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|test1\~3) + (DELAY + (ABSOLUTE + (PORT dataa (622:622:622) (745:745:745)) + (PORT datab (603:603:603) (700:700:700)) + (PORT datac (344:344:344) (405:405:405)) + (PORT datad (485:485:485) (564:564:564)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|interrupts_\|in_nmi_ALTERA_SYNTHESIZED) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (909:909:909) (896:896:896)) + (PORT ena (492:492:492) (529:529:529)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|clk_delay_\|SYNTHESIZED_WIRE_4) + (DELAY + (ABSOLUTE + (PORT dataa (333:333:333) (410:410:410)) + (PORT datab (829:829:829) (995:995:995)) + (PORT datac (679:679:679) (796:796:796)) + (PORT datad (466:466:466) (544:544:544)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|clk_delay_\|SYNTHESIZED_WIRE_7) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (913:913:913)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (910:910:910) (896:896:896)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|clk_delay_\|hold_clk_iorq) + (DELAY + (ABSOLUTE + (PORT dataa (601:601:601) (707:707:707)) + (PORT datab (700:700:700) (828:828:828)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_T4_ff) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (903:903:903) (890:890:890)) + (PORT ena (769:769:769) (833:833:833)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_eval_cond\~0) + (DELAY + (ABSOLUTE + (PORT datac (624:624:624) (751:751:751)) + (PORT datad (755:755:755) (876:876:876)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~27) + (DELAY + (ABSOLUTE + (PORT dataa (570:570:570) (667:667:667)) + (PORT datab (639:639:639) (732:732:732)) + (PORT datac (351:351:351) (409:409:409)) + (PORT datad (338:338:338) (389:389:389)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~26) + (DELAY + (ABSOLUTE + (PORT datab (628:628:628) (755:755:755)) + (PORT datac (1054:1054:1054) (1208:1208:1208)) + (PORT datad (1060:1060:1060) (1228:1228:1228)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~28) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (136:136:136)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (101:101:101) (122:122:122)) + (PORT datad (812:812:812) (925:925:925)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~6) + (DELAY + (ABSOLUTE + (PORT dataa (521:521:521) (608:608:608)) + (PORT datab (357:357:357) (423:423:423)) + (PORT datac (108:108:108) (133:133:133)) + (PORT datad (709:709:709) (819:819:819)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~7) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (133:133:133)) + (PORT datab (512:512:512) (601:601:601)) + (PORT datac (632:632:632) (754:754:754)) + (PORT datad (771:771:771) (879:879:879)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~8) + (DELAY + (ABSOLUTE + (PORT dataa (468:468:468) (551:551:551)) + (PORT datab (617:617:617) (728:728:728)) + (PORT datac (492:492:492) (590:590:590)) + (PORT datad (377:377:377) (440:440:440)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~9) + (DELAY + (ABSOLUTE + (PORT dataa (517:517:517) (597:597:597)) + (PORT datab (819:819:819) (944:944:944)) + (PORT datac (620:620:620) (731:731:731)) + (PORT datad (464:464:464) (539:539:539)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~10) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (403:403:403)) + (PORT datab (721:721:721) (825:825:825)) + (PORT datac (317:317:317) (368:368:368)) + (PORT datad (1363:1363:1363) (1541:1541:1541)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~12) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (136:136:136)) + (PORT datab (107:107:107) (137:137:137)) + (PORT datac (288:288:288) (330:330:330)) + (PORT datad (356:356:356) (416:416:416)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~15) + (DELAY + (ABSOLUTE + (PORT dataa (347:347:347) (410:410:410)) + (PORT datab (1076:1076:1076) (1256:1256:1256)) + (PORT datac (827:827:827) (962:962:962)) + (PORT datad (178:178:178) (212:212:212)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~13) + (DELAY + (ABSOLUTE + (PORT dataa (192:192:192) (229:229:229)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~41) + (DELAY + (ABSOLUTE + (PORT datab (114:114:114) (142:142:142)) + (PORT datac (590:590:590) (679:679:679)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~5) + (DELAY + (ABSOLUTE + (PORT dataa (737:737:737) (872:872:872)) + (PORT datab (727:727:727) (869:869:869)) + (PORT datac (448:448:448) (514:514:514)) + (PORT datad (433:433:433) (512:512:512)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~14) + (DELAY + (ABSOLUTE + (PORT dataa (731:731:731) (858:858:858)) + (PORT datab (534:534:534) (622:622:622)) + (PORT datac (465:465:465) (530:530:530)) + (PORT datad (314:314:314) (363:363:363)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|ena_M) + (DELAY + (ABSOLUTE + (PORT datab (650:650:650) (770:770:770)) + (PORT datad (512:512:512) (623:623:623)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_T1_ff) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (903:903:903) (890:890:890)) + (PORT ena (769:769:769) (833:833:833)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_13) + (DELAY + (ABSOLUTE + (PORT datab (146:146:146) (196:196:196)) + (PORT datac (886:886:886) (1031:1031:1031)) + (PORT datad (512:512:512) (624:624:624)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_T2_ff) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (903:903:903) (890:890:890)) + (PORT ena (769:769:769) (833:833:833)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_14) + (DELAY + (ABSOLUTE + (PORT datab (147:147:147) (197:197:197)) + (PORT datac (887:887:887) (1032:1032:1032)) + (PORT datad (512:512:512) (624:624:624)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_T3_ff) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (903:903:903) (890:890:890)) + (PORT ena (769:769:769) (833:833:833)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_1M1T3_3) + (DELAY + (ABSOLUTE + (PORT datac (678:678:678) (794:794:794)) + (PORT datad (901:901:901) (1044:1044:1044)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_66_oe\~2) + (DELAY + (ABSOLUTE + (PORT dataa (783:783:783) (903:903:903)) + (PORT datab (351:351:351) (413:413:413)) + (PORT datac (732:732:732) (858:858:858)) + (PORT datad (933:933:933) (1103:1103:1103)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|interrupts_\|im1) + (DELAY + (ABSOLUTE + (PORT clk (920:920:920) (928:928:928)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (909:909:909) (896:896:896)) + (PORT ena (781:781:781) (861:861:861)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_ff_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (157:157:157) (216:216:216)) + (PORT datab (488:488:488) (582:582:582)) + (PORT datac (463:463:463) (547:547:547)) + (PORT datad (627:627:627) (714:714:714)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_ff_oe\~1) + (DELAY + (ABSOLUTE + (PORT dataa (353:353:353) (415:415:415)) + (PORT datab (648:648:648) (742:742:742)) + (PORT datac (232:232:232) (309:309:309)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_zero_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (851:851:851) (971:971:971)) + (PORT datab (706:706:706) (828:828:828)) + (PORT datac (775:775:775) (909:909:909)) + (PORT datad (485:485:485) (551:551:551)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (109:109:109) (143:143:143)) + (PORT datab (107:107:107) (137:137:137)) + (PORT datac (757:757:757) (868:868:868)) + (PORT datad (387:387:387) (465:465:465)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[6\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (292:292:292) (342:342:342)) + (PORT datac (739:739:739) (831:831:831)) + (PORT datad (319:319:319) (366:366:366)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (527:527:527) (603:603:603)) + (PORT clk (1084:1084:1084) (1102:1102:1102)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (835:835:835) (960:960:960)) + (PORT d[1] (1056:1056:1056) (1219:1219:1219)) + (PORT d[2] (1286:1286:1286) (1493:1493:1493)) + (PORT d[3] (1046:1046:1046) (1215:1215:1215)) + (PORT d[4] (1320:1320:1320) (1510:1510:1510)) + (PORT d[5] (797:797:797) (919:919:919)) + (PORT d[6] (791:791:791) (910:910:910)) + (PORT d[7] (855:855:855) (999:999:999)) + (PORT d[8] (1415:1415:1415) (1640:1640:1640)) + (PORT d[9] (2000:2000:2000) (2329:2329:2329)) + (PORT d[10] (725:725:725) (844:844:844)) + (PORT d[11] (927:927:927) (1060:1060:1060)) + (PORT d[12] (1347:1347:1347) (1526:1526:1526)) + (PORT clk (1082:1082:1082) (1100:1100:1100)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (817:817:817) (891:891:891)) + (PORT clk (1082:1082:1082) (1100:1100:1100)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1084:1084:1084) (1102:1102:1102)) + (PORT d[0] (966:966:966) (1023:1023:1023)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1085:1085:1085) (1103:1103:1103)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1085:1085:1085) (1103:1103:1103)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1085:1085:1085) (1103:1103:1103)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1085:1085:1085) (1103:1103:1103)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1064:1064:1064) (1081:1081:1081)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (604:604:604) (613:613:613)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (605:605:605) (614:614:614)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (605:605:605) (614:614:614)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (605:605:605) (614:614:614)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (562:562:562) (649:649:649)) + (PORT clk (1082:1082:1082) (1100:1100:1100)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (684:684:684) (787:787:787)) + (PORT d[1] (1041:1041:1041) (1210:1210:1210)) + (PORT d[2] (1144:1144:1144) (1352:1352:1352)) + (PORT d[3] (1049:1049:1049) (1216:1216:1216)) + (PORT d[4] (1347:1347:1347) (1545:1545:1545)) + (PORT d[5] (773:773:773) (891:891:891)) + (PORT d[6] (784:784:784) (901:901:901)) + (PORT d[7] (873:873:873) (1022:1022:1022)) + (PORT d[8] (1458:1458:1458) (1680:1680:1680)) + (PORT d[9] (2005:2005:2005) (2336:2336:2336)) + (PORT d[10] (924:924:924) (1069:1069:1069)) + (PORT d[11] (763:763:763) (876:876:876)) + (PORT d[12] (1368:1368:1368) (1554:1554:1554)) + (PORT clk (1080:1080:1080) (1098:1098:1098)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (801:801:801) (864:864:864)) + (PORT clk (1080:1080:1080) (1098:1098:1098)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1082:1082:1082) (1100:1100:1100)) + (PORT d[0] (960:960:960) (1017:1017:1017)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1083:1083:1083) (1101:1101:1101)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1083:1083:1083) (1101:1101:1101)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1083:1083:1083) (1101:1101:1101)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1083:1083:1083) (1101:1101:1101)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1062:1062:1062) (1079:1079:1079)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (602:602:602) (611:611:611)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (603:603:603) (612:612:612)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (603:603:603) (612:612:612)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (603:603:603) (612:612:612)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (513:513:513) (585:585:585)) + (PORT clk (1089:1089:1089) (1106:1106:1106)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (645:645:645) (753:753:753)) + (PORT d[1] (1047:1047:1047) (1215:1215:1215)) + (PORT d[2] (1880:1880:1880) (2176:2176:2176)) + (PORT d[3] (875:875:875) (1024:1024:1024)) + (PORT d[4] (1135:1135:1135) (1296:1296:1296)) + (PORT d[5] (770:770:770) (883:883:883)) + (PORT d[6] (946:946:946) (1089:1089:1089)) + (PORT d[7] (696:696:696) (820:820:820)) + (PORT d[8] (1493:1493:1493) (1724:1724:1724)) + (PORT d[9] (1827:1827:1827) (2135:2135:2135)) + (PORT d[10] (755:755:755) (882:882:882)) + (PORT d[11] (945:945:945) (1082:1082:1082)) + (PORT d[12] (1530:1530:1530) (1736:1736:1736)) + (PORT clk (1087:1087:1087) (1104:1104:1104)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1165:1165:1165) (1276:1276:1276)) + (PORT clk (1087:1087:1087) (1104:1104:1104)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1089:1089:1089) (1106:1106:1106)) + (PORT d[0] (1055:1055:1055) (1119:1119:1119)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1107:1107:1107)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1107:1107:1107)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1107:1107:1107)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1107:1107:1107)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1069:1069:1069) (1085:1085:1085)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (609:609:609) (617:617:617)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (610:610:610) (618:618:618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (610:610:610) (618:618:618)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (610:610:610) (618:618:618)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (384:384:384) (439:439:439)) + (PORT clk (1087:1087:1087) (1104:1104:1104)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (658:658:658) (753:753:753)) + (PORT d[1] (1211:1211:1211) (1405:1405:1405)) + (PORT d[2] (1150:1150:1150) (1352:1352:1352)) + (PORT d[3] (1078:1078:1078) (1253:1253:1253)) + (PORT d[4] (998:998:998) (1150:1150:1150)) + (PORT d[5] (757:757:757) (869:869:869)) + (PORT d[6] (621:621:621) (714:714:714)) + (PORT d[7] (683:683:683) (803:803:803)) + (PORT d[8] (1492:1492:1492) (1723:1723:1723)) + (PORT d[9] (1815:1815:1815) (2116:2116:2116)) + (PORT d[10] (744:744:744) (871:871:871)) + (PORT d[11] (929:929:929) (1062:1062:1062)) + (PORT d[12] (628:628:628) (727:727:727)) + (PORT clk (1085:1085:1085) (1102:1102:1102)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1440:1440:1440) (1595:1595:1595)) + (PORT clk (1085:1085:1085) (1102:1102:1102)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1087:1087:1087) (1104:1104:1104)) + (PORT d[0] (787:787:787) (818:818:818)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1088:1088:1088) (1105:1105:1105)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1088:1088:1088) (1105:1105:1105)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1088:1088:1088) (1105:1105:1105)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1088:1088:1088) (1105:1105:1105)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1067:1067:1067) (1083:1083:1083)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (607:607:607) (615:615:615)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (608:608:608) (616:616:616)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (608:608:608) (616:616:616)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (608:608:608) (616:616:616)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[6\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (498:498:498) (568:568:568)) + (PORT datab (365:365:365) (418:418:418)) + (PORT datac (628:628:628) (732:732:732)) + (PORT datad (748:748:748) (884:884:884)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[6\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (680:680:680) (786:786:786)) + (PORT datab (698:698:698) (800:800:800)) + (PORT datac (160:160:160) (188:188:188)) + (PORT datad (1111:1111:1111) (1288:1288:1288)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1040:1040:1040) (1197:1197:1197)) + (PORT d[1] (1183:1183:1183) (1364:1364:1364)) + (PORT d[2] (1230:1230:1230) (1424:1424:1424)) + (PORT d[3] (1058:1058:1058) (1227:1227:1227)) + (PORT d[4] (1328:1328:1328) (1519:1519:1519)) + (PORT d[5] (960:960:960) (1097:1097:1097)) + (PORT d[6] (1082:1082:1082) (1232:1232:1232)) + (PORT d[7] (824:824:824) (960:960:960)) + (PORT d[8] (1265:1265:1265) (1460:1460:1460)) + (PORT d[9] (1889:1889:1889) (2190:2190:2190)) + (PORT d[10] (930:930:930) (1082:1082:1082)) + (PORT d[11] (1133:1133:1133) (1293:1293:1293)) + (PORT d[12] (985:985:985) (1114:1114:1114)) + (PORT clk (1090:1090:1090) (1108:1108:1108)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1108:1108:1108)) + (PORT d[0] (1637:1637:1637) (1473:1473:1473)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1072:1072:1072) (1089:1089:1089)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (621:621:621)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (622:622:622)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (622:622:622)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (622:622:622)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (851:851:851) (980:980:980)) + (PORT d[1] (1443:1443:1443) (1654:1654:1654)) + (PORT d[2] (1279:1279:1279) (1489:1489:1489)) + (PORT d[3] (1059:1059:1059) (1230:1230:1230)) + (PORT d[4] (1310:1310:1310) (1504:1504:1504)) + (PORT d[5] (954:954:954) (1094:1094:1094)) + (PORT d[6] (972:972:972) (1116:1116:1116)) + (PORT d[7] (844:844:844) (988:988:988)) + (PORT d[8] (1275:1275:1275) (1475:1475:1475)) + (PORT d[9] (2038:2038:2038) (2353:2353:2353)) + (PORT d[10] (780:780:780) (919:919:919)) + (PORT d[11] (939:939:939) (1073:1073:1073)) + (PORT d[12] (1183:1183:1183) (1343:1343:1343)) + (PORT clk (1088:1088:1088) (1105:1105:1105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1088:1088:1088) (1105:1105:1105)) + (PORT d[0] (724:724:724) (789:789:789)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1089:1089:1089) (1106:1106:1106)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) (DELAY (ABSOLUTE (PORT clk (1070:1070:1070) (1086:1086:1086)) @@ -45749,7 +46232,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) (DELAY (ABSOLUTE (PORT clk (610:610:610) (618:618:618)) @@ -45758,7 +46241,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) (DELAY (ABSOLUTE (PORT clk (611:611:611) (619:619:619)) @@ -45767,7 +46250,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) (DELAY (ABSOLUTE (PORT clk (611:611:611) (619:619:619)) @@ -45775,9 +46258,1688 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (611:611:611) (619:619:619)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (718:718:718) (834:834:834)) + (PORT clk (1086:1086:1086) (1104:1104:1104)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1792:1792:1792) (2103:2103:2103)) + (PORT d[1] (2437:2437:2437) (2784:2784:2784)) + (PORT d[2] (1324:1324:1324) (1547:1547:1547)) + (PORT d[3] (1244:1244:1244) (1438:1438:1438)) + (PORT d[4] (1988:1988:1988) (2280:2280:2280)) + (PORT d[5] (1360:1360:1360) (1573:1573:1573)) + (PORT d[6] (2334:2334:2334) (2667:2667:2667)) + (PORT d[7] (1733:1733:1733) (2009:2009:2009)) + (PORT d[8] (1232:1232:1232) (1425:1425:1425)) + (PORT d[9] (1579:1579:1579) (1815:1815:1815)) + (PORT d[10] (1779:1779:1779) (2072:2072:2072)) + (PORT d[11] (1815:1815:1815) (2080:2080:2080)) + (PORT d[12] (1764:1764:1764) (2009:2009:2009)) + (PORT clk (1084:1084:1084) (1102:1102:1102)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1310:1310:1310) (1435:1435:1435)) + (PORT clk (1084:1084:1084) (1102:1102:1102)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1086:1086:1086) (1104:1104:1104)) + (PORT d[0] (3128:3128:3128) (3443:3443:3443)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1087:1087:1087) (1105:1105:1105)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1087:1087:1087) (1105:1105:1105)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1087:1087:1087) (1105:1105:1105)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1087:1087:1087) (1105:1105:1105)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1041:1041:1041) (1061:1061:1061)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1228:1228:1228) (1434:1434:1434)) + (PORT clk (1046:1046:1046) (1064:1064:1064)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2348:2348:2348) (2675:2675:2675)) + (PORT d[1] (2418:2418:2418) (2760:2760:2760)) + (PORT d[2] (2320:2320:2320) (2652:2652:2652)) + (PORT d[3] (2404:2404:2404) (2763:2763:2763)) + (PORT d[4] (2327:2327:2327) (2647:2647:2647)) + (PORT d[5] (2401:2401:2401) (2754:2754:2754)) + (PORT d[6] (2297:2297:2297) (2598:2598:2598)) + (PORT d[7] (2278:2278:2278) (2601:2601:2601)) + (PORT d[8] (2360:2360:2360) (2663:2663:2663)) + (PORT d[9] (2300:2300:2300) (2617:2617:2617)) + (PORT d[10] (2363:2363:2363) (2680:2680:2680)) + (PORT d[11] (2417:2417:2417) (2739:2739:2739)) + (PORT d[12] (2328:2328:2328) (2633:2633:2633)) + (PORT clk (1043:1043:1043) (1063:1063:1063)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1046:1046:1046) (1064:1064:1064)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1047:1047:1047) (1065:1065:1065)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1047:1047:1047) (1065:1065:1065)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1047:1047:1047) (1065:1065:1065)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1047:1047:1047) (1065:1065:1065)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (715:715:715) (831:831:831)) + (PORT clk (1091:1091:1091) (1108:1108:1108)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1587:1587:1587) (1825:1825:1825)) + (PORT d[1] (2097:2097:2097) (2397:2397:2397)) + (PORT d[2] (1522:1522:1522) (1765:1765:1765)) + (PORT d[3] (1093:1093:1093) (1266:1266:1266)) + (PORT d[4] (1976:1976:1976) (2268:2268:2268)) + (PORT d[5] (1523:1523:1523) (1755:1755:1755)) + (PORT d[6] (2319:2319:2319) (2650:2650:2650)) + (PORT d[7] (1538:1538:1538) (1783:1783:1783)) + (PORT d[8] (1650:1650:1650) (1894:1894:1894)) + (PORT d[9] (1587:1587:1587) (1858:1858:1858)) + (PORT d[10] (2203:2203:2203) (2567:2567:2567)) + (PORT d[11] (1656:1656:1656) (1906:1906:1906)) + (PORT d[12] (1570:1570:1570) (1790:1790:1790)) + (PORT clk (1089:1089:1089) (1106:1106:1106)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1641:1641:1641) (1813:1813:1813)) + (PORT clk (1089:1089:1089) (1106:1106:1106)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1108:1108:1108)) + (PORT d[0] (3246:3246:3246) (2979:2979:2979)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1092:1092:1092) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1046:1046:1046) (1065:1065:1065)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (746:746:746) (864:864:864)) + (PORT clk (1051:1051:1051) (1068:1068:1068)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2435:2435:2435) (2777:2777:2777)) + (PORT d[1] (2383:2383:2383) (2715:2715:2715)) + (PORT d[2] (2345:2345:2345) (2683:2683:2683)) + (PORT d[3] (2380:2380:2380) (2747:2747:2747)) + (PORT d[4] (2333:2333:2333) (2653:2653:2653)) + (PORT d[5] (2420:2420:2420) (2762:2762:2762)) + (PORT d[6] (2263:2263:2263) (2557:2557:2557)) + (PORT d[7] (2222:2222:2222) (2551:2551:2551)) + (PORT d[8] (2435:2435:2435) (2770:2770:2770)) + (PORT d[9] (2245:2245:2245) (2568:2568:2568)) + (PORT d[10] (2385:2385:2385) (2705:2705:2705)) + (PORT d[11] (2306:2306:2306) (2600:2600:2600)) + (PORT d[12] (2345:2345:2345) (2653:2653:2653)) + (PORT clk (1048:1048:1048) (1067:1067:1067)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1051:1051:1051) (1068:1068:1068)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1052:1052:1052) (1069:1069:1069)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1052:1052:1052) (1069:1069:1069)) + (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1052:1052:1052) (1069:1069:1069)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1052:1052:1052) (1069:1069:1069)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1047:1047:1047) (1066:1066:1066)) + (IOPATH (posedge clk) q (164:164:164) (166:166:166)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (919:919:919) (1054:1054:1054)) + (PORT datab (592:592:592) (669:669:669)) + (PORT datac (821:821:821) (929:929:929)) + (PORT datad (844:844:844) (967:967:967)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector6\~1) + (DELAY + (ABSOLUTE + (PORT dataa (726:726:726) (840:840:840)) + (PORT datab (202:202:202) (238:238:238)) + (PORT datac (853:853:853) (950:950:950)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~88) + (DELAY + (ABSOLUTE + (PORT dataa (885:885:885) (1074:1074:1074)) + (PORT datab (1724:1724:1724) (2019:2019:2019)) + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (181:181:181) (175:175:175)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE raw_loader_in\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (153:153:153) (704:704:704)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~69) + (DELAY + (ABSOLUTE + (PORT datab (1721:1721:1721) (2017:2017:2017)) + (PORT datac (736:736:736) (861:861:861)) + (PORT datad (896:896:896) (1005:1005:1005)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~78) + (DELAY + (ABSOLUTE + (PORT dataa (613:613:613) (717:717:717)) + (PORT datab (601:601:601) (693:693:693)) + (PORT datac (92:92:92) (115:115:115)) + (PORT datad (97:97:97) (116:116:116)) + (IOPATH dataa combout (158:158:158) (173:173:173)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~79) + (DELAY + (ABSOLUTE + (PORT dataa (748:748:748) (892:892:892)) + (PORT datab (601:601:601) (694:694:694)) + (PORT datac (606:606:606) (697:697:697)) + (PORT datad (89:89:89) (107:107:107)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[6\]) + (DELAY + (ABSOLUTE + (PORT dataa (796:796:796) (913:913:913)) + (PORT datab (208:208:208) (252:252:252)) + (PORT datac (718:718:718) (829:829:829)) + (PORT datad (103:103:103) (120:120:120)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (917:917:917) (904:904:904)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (421:421:421) (449:449:449)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[6\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (211:211:211) (255:255:255)) + (PORT datab (191:191:191) (230:230:230)) + (PORT datac (191:191:191) (243:243:243)) + (PORT datad (306:306:306) (357:357:357)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (909:909:909) (896:896:896)) + (PORT ena (912:912:912) (993:993:993)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~10) + (DELAY + (ABSOLUTE + (PORT dataa (568:568:568) (693:693:693)) + (PORT datab (595:595:595) (720:720:720)) + (PORT datac (387:387:387) (464:464:464)) + (PORT datad (617:617:617) (712:712:712)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (507:507:507) (592:592:592)) + (PORT datab (528:528:528) (616:616:616)) + (PORT datac (100:100:100) (127:127:127)) + (PORT datad (901:901:901) (1037:1037:1037)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~4) + (DELAY + (ABSOLUTE + (PORT datac (807:807:807) (944:944:944)) + (PORT datad (742:742:742) (840:840:840)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~2) + (DELAY + (ABSOLUTE + (PORT dataa (108:108:108) (141:141:141)) + (PORT datab (108:108:108) (139:139:139)) + (PORT datac (759:759:759) (870:870:870)) + (PORT datad (389:389:389) (467:467:467)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~5) + (DELAY + (ABSOLUTE + (PORT dataa (224:224:224) (280:280:280)) + (PORT datab (315:315:315) (364:364:364)) + (PORT datac (310:310:310) (365:365:365)) + (PORT datad (314:314:314) (366:366:366)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~6) + (DELAY + (ABSOLUTE + (PORT dataa (550:550:550) (643:643:643)) + (PORT datab (101:101:101) (129:129:129)) + (PORT datac (1099:1099:1099) (1267:1267:1267)) + (PORT datad (1008:1008:1008) (1144:1144:1144)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (134:134:134)) + (PORT datab (177:177:177) (217:217:217)) + (PORT datac (817:817:817) (915:915:915)) + (PORT datad (469:469:469) (541:541:541)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (189:189:189) (232:232:232)) + (PORT datac (755:755:755) (864:864:864)) + (PORT datad (172:172:172) (202:202:202)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~61) + (DELAY + (ABSOLUTE + (PORT dataa (109:109:109) (142:142:142)) + (PORT datab (543:543:543) (645:645:645)) + (PORT datac (669:669:669) (787:787:787)) + (PORT datad (492:492:492) (578:578:578)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~63) + (DELAY + (ABSOLUTE + (PORT dataa (217:217:217) (279:279:279)) + (PORT datab (105:105:105) (134:134:134)) + (PORT datac (468:468:468) (537:537:537)) + (PORT datad (107:107:107) (125:125:125)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~64) + (DELAY + (ABSOLUTE + (PORT dataa (466:466:466) (544:544:544)) + (PORT datab (412:412:412) (503:503:503)) + (PORT datac (163:163:163) (192:192:192)) + (PORT datad (560:560:560) (660:660:660)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~65) + (DELAY + (ABSOLUTE + (PORT dataa (181:181:181) (220:220:220)) + (PORT datad (93:93:93) (111:111:111)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (908:908:908)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (895:895:895) (899:899:899)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~67) + (DELAY + (ABSOLUTE + (PORT dataa (582:582:582) (700:700:700)) + (PORT datab (358:358:358) (427:427:427)) + (PORT datad (524:524:524) (620:620:620)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (192:192:192) (181:181:181)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~68) + (DELAY + (ABSOLUTE + (PORT dataa (539:539:539) (646:646:646)) + (PORT datab (644:644:644) (770:770:770)) + (PORT datac (145:145:145) (194:194:194)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~69) + (DELAY + (ABSOLUTE + (PORT dataa (355:355:355) (416:416:416)) + (PORT datab (120:120:120) (150:150:150)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (911:911:911)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (892:892:892) (897:897:897)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (350:350:350) (425:425:425)) + (PORT datab (200:200:200) (253:253:253)) + (PORT datac (589:589:589) (667:667:667)) + (PORT datad (341:341:341) (399:399:399)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~58) + (DELAY + (ABSOLUTE + (PORT dataa (423:423:423) (528:528:528)) + (PORT datab (237:237:237) (298:298:298)) + (PORT datac (634:634:634) (760:760:760)) + (PORT datad (338:338:338) (401:401:401)) + (IOPATH dataa combout (172:172:172) (163:163:163)) + (IOPATH datab combout (169:169:169) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~130) + (DELAY + (ABSOLUTE + (PORT dataa (539:539:539) (646:646:646)) + (PORT datab (288:288:288) (332:332:332)) + (PORT datac (143:143:143) (192:192:192)) + (PORT datad (560:560:560) (674:674:674)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~59) + (DELAY + (ABSOLUTE + (PORT dataa (335:335:335) (409:409:409)) + (PORT datab (177:177:177) (215:215:215)) + (PORT datad (259:259:259) (294:294:294)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (906:906:906) (911:911:911)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (892:892:892) (897:897:897)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~56) + (DELAY + (ABSOLUTE + (PORT datac (361:361:361) (436:436:436)) + (PORT datad (381:381:381) (457:457:457)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~57) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (137:137:137)) + (PORT datab (509:509:509) (611:611:611)) + (PORT datad (166:166:166) (194:194:194)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (909:909:909)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (897:897:897) (901:901:901)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (1152:1152:1152) (1306:1306:1306)) + (PORT datab (216:216:216) (274:274:274)) + (PORT datac (472:472:472) (552:552:552)) + (PORT datad (363:363:363) (440:440:440)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]\~54) + (DELAY + (ABSOLUTE + (PORT datac (599:599:599) (725:725:725)) + (PORT datad (663:663:663) (780:780:780)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]\~55) + (DELAY + (ABSOLUTE + (PORT dataa (418:418:418) (520:520:520)) + (PORT datab (188:188:188) (231:231:231)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (895:895:895) (899:899:899)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]\~50) + (DELAY + (ABSOLUTE + (PORT datac (603:603:603) (730:730:730)) + (PORT datad (662:662:662) (778:778:778)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (111:111:111) (145:145:145)) + (PORT datab (189:189:189) (232:232:232)) + (PORT datad (392:392:392) (486:486:486)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (895:895:895) (899:899:899)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]\~52) + (DELAY + (ABSOLUTE + (PORT dataa (492:492:492) (573:573:573)) + (PORT datab (343:343:343) (404:404:404)) + (PORT datac (96:96:96) (121:121:121)) + (PORT datad (1089:1089:1089) (1273:1273:1273)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]\~53) + (DELAY + (ABSOLUTE + (PORT dataa (419:419:419) (522:522:522)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (895:895:895) (899:899:899)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (256:256:256)) + (PORT datab (214:214:214) (269:269:269)) + (PORT datac (559:559:559) (646:646:646)) + (PORT datad (445:445:445) (513:513:513)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[2\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (190:190:190) (231:231:231)) + (PORT datab (484:484:484) (557:557:557)) + (PORT datac (602:602:602) (729:729:729)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[2\]\~48) + (DELAY + (ABSOLUTE + (PORT datab (104:104:104) (133:133:133)) + (PORT datad (390:390:390) (484:484:484)) + (IOPATH datab combout (191:191:191) (181:181:181)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (908:908:908) (913:913:913)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (895:895:895) (899:899:899)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\~1) + (DELAY + (ABSOLUTE + (PORT datab (617:617:617) (720:720:720)) + (PORT datac (1486:1486:1486) (1738:1738:1738)) + (PORT datad (119:119:119) (156:156:156)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (1344:1344:1344) (1575:1575:1575)) + (PORT datab (130:130:130) (178:178:178)) + (PORT datac (173:173:173) (209:209:209)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (136:136:136)) + (PORT datab (184:184:184) (221:221:221)) + (PORT datac (407:407:407) (458:458:458)) + (PORT datad (463:463:463) (536:536:536)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (549:549:549) (625:625:625)) + (PORT clk (1087:1087:1087) (1104:1104:1104)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (871:871:871) (1003:1003:1003)) + (PORT d[1] (1461:1461:1461) (1676:1676:1676)) + (PORT d[2] (1269:1269:1269) (1472:1472:1472)) + (PORT d[3] (1035:1035:1035) (1203:1203:1203)) + (PORT d[4] (1320:1320:1320) (1514:1514:1514)) + (PORT d[5] (781:781:781) (895:895:895)) + (PORT d[6] (792:792:792) (910:910:910)) + (PORT d[7] (854:854:854) (1003:1003:1003)) + (PORT d[8] (1306:1306:1306) (1514:1514:1514)) + (PORT d[9] (1942:1942:1942) (2255:2255:2255)) + (PORT d[10] (752:752:752) (884:884:884)) + (PORT d[11] (930:930:930) (1063:1063:1063)) + (PORT d[12] (1334:1334:1334) (1511:1511:1511)) + (PORT clk (1085:1085:1085) (1102:1102:1102)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (993:993:993) (1092:1092:1092)) + (PORT clk (1085:1085:1085) (1102:1102:1102)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1087:1087:1087) (1104:1104:1104)) + (PORT d[0] (1082:1082:1082) (1148:1148:1148)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1088:1088:1088) (1105:1105:1105)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1088:1088:1088) (1105:1105:1105)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1088:1088:1088) (1105:1105:1105)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1088:1088:1088) (1105:1105:1105)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1067:1067:1067) (1083:1083:1083)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (607:607:607) (615:615:615)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (608:608:608) (616:616:616)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (608:608:608) (616:616:616)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (608:608:608) (616:616:616)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (375:375:375) (432:432:432)) + (PORT clk (1084:1084:1084) (1102:1102:1102)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (688:688:688) (797:797:797)) + (PORT d[1] (1039:1039:1039) (1201:1201:1201)) + (PORT d[2] (1247:1247:1247) (1449:1449:1449)) + (PORT d[3] (1067:1067:1067) (1239:1239:1239)) + (PORT d[4] (1168:1168:1168) (1344:1344:1344)) + (PORT d[5] (586:586:586) (677:677:677)) + (PORT d[6] (770:770:770) (885:885:885)) + (PORT d[7] (864:864:864) (1009:1009:1009)) + (PORT d[8] (1471:1471:1471) (1696:1696:1696)) + (PORT d[9] (1971:1971:1971) (2292:2292:2292)) + (PORT d[10] (753:753:753) (884:884:884)) + (PORT d[11] (931:931:931) (1068:1068:1068)) + (PORT d[12] (1369:1369:1369) (1555:1555:1555)) + (PORT clk (1082:1082:1082) (1100:1100:1100)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1458:1458:1458) (1617:1617:1617)) + (PORT clk (1082:1082:1082) (1100:1100:1100)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1084:1084:1084) (1102:1102:1102)) + (PORT d[0] (942:942:942) (993:993:993)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1085:1085:1085) (1103:1103:1103)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1085:1085:1085) (1103:1103:1103)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1085:1085:1085) (1103:1103:1103)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1085:1085:1085) (1103:1103:1103)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1064:1064:1064) (1081:1081:1081)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (604:604:604) (613:613:613)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (605:605:605) (614:614:614)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (605:605:605) (614:614:614)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (605:605:605) (614:614:614)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (532:532:532) (605:605:605)) + (PORT clk (1090:1090:1090) (1107:1107:1107)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (793:793:793) (919:919:919)) + (PORT d[1] (1064:1064:1064) (1236:1236:1236)) + (PORT d[2] (1098:1098:1098) (1278:1278:1278)) + (PORT d[3] (868:868:868) (1011:1011:1011)) + (PORT d[4] (978:978:978) (1125:1125:1125)) + (PORT d[5] (790:790:790) (910:910:910)) + (PORT d[6] (952:952:952) (1094:1094:1094)) + (PORT d[7] (1054:1054:1054) (1228:1228:1228)) + (PORT d[8] (1774:1774:1774) (2043:2043:2043)) + (PORT d[9] (1830:1830:1830) (2140:2140:2140)) + (PORT d[10] (908:908:908) (1055:1055:1055)) + (PORT d[11] (1282:1282:1282) (1485:1485:1485)) + (PORT d[12] (1551:1551:1551) (1764:1764:1764)) + (PORT clk (1088:1088:1088) (1105:1105:1105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1009:1009:1009) (1105:1105:1105)) + (PORT clk (1088:1088:1088) (1105:1105:1105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1107:1107:1107)) + (PORT d[0] (1214:1214:1214) (1296:1296:1296)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1108:1108:1108)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1108:1108:1108)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1108:1108:1108)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1108:1108:1108)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1070:1070:1070) (1086:1086:1086)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (610:610:610) (618:618:618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (611:611:611) (619:619:619)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (611:611:611) (619:619:619)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) (DELAY (ABSOLUTE (PORT clk (611:611:611) (619:619:619)) @@ -45787,32 +47949,185 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~43) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[2\]\~2) (DELAY (ABSOLUTE - (PORT dataa (531:531:531) (623:623:623)) - (PORT datab (629:629:629) (737:737:737)) - (PORT datac (452:452:452) (516:516:516)) - (PORT datad (577:577:577) (637:637:637)) - (IOPATH dataa combout (170:170:170) (165:165:165)) - (IOPATH datab combout (169:169:169) (167:167:167)) + (PORT dataa (529:529:529) (626:626:626)) + (PORT datab (478:478:478) (564:564:564)) + (PORT datac (478:478:478) (537:537:537)) + (PORT datad (509:509:509) (579:579:579)) + (IOPATH dataa combout (188:188:188) (184:184:184)) + (IOPATH datab combout (190:190:190) (188:188:188)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~44) + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.datain_a_register) (DELAY (ABSOLUTE - (PORT dataa (622:622:622) (711:711:711)) - (PORT datab (899:899:899) (1055:1055:1055)) - (PORT datac (625:625:625) (722:722:722)) - (PORT datad (160:160:160) (186:186:186)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (169:169:169) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT d[0] (550:550:550) (628:628:628)) + (PORT clk (1089:1089:1089) (1106:1106:1106)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (850:850:850) (976:976:976)) + (PORT d[1] (1450:1450:1450) (1661:1661:1661)) + (PORT d[2] (1156:1156:1156) (1364:1364:1364)) + (PORT d[3] (1047:1047:1047) (1217:1217:1217)) + (PORT d[4] (1158:1158:1158) (1332:1332:1332)) + (PORT d[5] (782:782:782) (895:895:895)) + (PORT d[6] (959:959:959) (1101:1101:1101)) + (PORT d[7] (831:831:831) (977:977:977)) + (PORT d[8] (1287:1287:1287) (1487:1487:1487)) + (PORT d[9] (1941:1941:1941) (2254:2254:2254)) + (PORT d[10] (767:767:767) (895:895:895)) + (PORT d[11] (951:951:951) (1092:1092:1092)) + (PORT d[12] (1184:1184:1184) (1344:1344:1344)) + (PORT clk (1087:1087:1087) (1104:1104:1104)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (957:957:957) (1036:1036:1036)) + (PORT clk (1087:1087:1087) (1104:1104:1104)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1089:1089:1089) (1106:1106:1106)) + (PORT d[0] (974:974:974) (1034:1034:1034)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1107:1107:1107)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1107:1107:1107)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1107:1107:1107)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1107:1107:1107)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1069:1069:1069) (1085:1085:1085)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (609:609:609) (617:617:617)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (610:610:610) (618:618:618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (610:610:610) (618:618:618)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (610:610:610) (618:618:618)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[2\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (544:544:544) (626:626:626)) + (PORT datab (762:762:762) (908:908:908)) + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (681:681:681) (776:776:776)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (190:190:190) (205:205:205)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -45822,19 +48137,19 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1711:1711:1711) (1985:1985:1985)) - (PORT d[1] (1692:1692:1692) (1969:1969:1969)) - (PORT d[2] (951:951:951) (1114:1114:1114)) - (PORT d[3] (838:838:838) (978:978:978)) - (PORT d[4] (1077:1077:1077) (1247:1247:1247)) - (PORT d[5] (774:774:774) (919:919:919)) - (PORT d[6] (631:631:631) (730:730:730)) - (PORT d[7] (846:846:846) (976:976:976)) - (PORT d[8] (1434:1434:1434) (1682:1682:1682)) - (PORT d[9] (2200:2200:2200) (2538:2538:2538)) - (PORT d[10] (1484:1484:1484) (1701:1701:1701)) - (PORT d[11] (1006:1006:1006) (1165:1165:1165)) - (PORT d[12] (1141:1141:1141) (1316:1316:1316)) + (PORT d[0] (1022:1022:1022) (1176:1176:1176)) + (PORT d[1] (1327:1327:1327) (1529:1529:1529)) + (PORT d[2] (1139:1139:1139) (1333:1333:1333)) + (PORT d[3] (1066:1066:1066) (1237:1237:1237)) + (PORT d[4] (1312:1312:1312) (1501:1501:1501)) + (PORT d[5] (953:953:953) (1089:1089:1089)) + (PORT d[6] (980:980:980) (1124:1124:1124)) + (PORT d[7] (866:866:866) (1014:1014:1014)) + (PORT d[8] (1253:1253:1253) (1460:1460:1460)) + (PORT d[9] (1937:1937:1937) (2253:2253:2253)) + (PORT d[10] (915:915:915) (1067:1067:1067)) + (PORT d[11] (1115:1115:1115) (1272:1272:1272)) + (PORT d[12] (1162:1162:1162) (1315:1315:1315)) (PORT clk (1089:1089:1089) (1106:1106:1106)) ) ) @@ -45848,7 +48163,7 @@ (DELAY (ABSOLUTE (PORT clk (1089:1089:1089) (1106:1106:1106)) - (PORT d[0] (720:720:720) (792:792:792)) + (PORT d[0] (722:722:722) (785:785:785)) ) ) ) @@ -45914,458 +48229,25 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (908:908:908) (1039:1039:1039)) - (PORT clk (1102:1102:1102) (1119:1119:1119)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1462:1462:1462) (1666:1666:1666)) - (PORT d[1] (1206:1206:1206) (1428:1428:1428)) - (PORT d[2] (1461:1461:1461) (1705:1705:1705)) - (PORT d[3] (1294:1294:1294) (1499:1499:1499)) - (PORT d[4] (1739:1739:1739) (2032:2032:2032)) - (PORT d[5] (1231:1231:1231) (1457:1457:1457)) - (PORT d[6] (916:916:916) (1046:1046:1046)) - (PORT d[7] (1592:1592:1592) (1814:1814:1814)) - (PORT d[8] (1611:1611:1611) (1895:1895:1895)) - (PORT d[9] (1199:1199:1199) (1367:1367:1367)) - (PORT d[10] (1075:1075:1075) (1225:1225:1225)) - (PORT d[11] (2079:2079:2079) (2374:2374:2374)) - (PORT d[12] (1066:1066:1066) (1228:1228:1228)) - (PORT clk (1100:1100:1100) (1117:1117:1117)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1776:1776:1776) (1945:1945:1945)) - (PORT clk (1100:1100:1100) (1117:1117:1117)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1102:1102:1102) (1119:1119:1119)) - (PORT d[0] (1621:1621:1621) (1764:1764:1764)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1103:1103:1103) (1120:1120:1120)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1103:1103:1103) (1120:1120:1120)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1103:1103:1103) (1120:1120:1120)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1103:1103:1103) (1120:1120:1120)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1057:1057:1057) (1076:1076:1076)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1215:1215:1215) (1378:1378:1378)) - (PORT clk (1062:1062:1062) (1079:1079:1079)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2485:2485:2485) (2804:2804:2804)) - (PORT d[1] (2412:2412:2412) (2731:2731:2731)) - (PORT d[2] (2546:2546:2546) (2889:2889:2889)) - (PORT d[3] (2481:2481:2481) (2823:2823:2823)) - (PORT d[4] (2356:2356:2356) (2667:2667:2667)) - (PORT d[5] (2416:2416:2416) (2742:2742:2742)) - (PORT d[6] (2567:2567:2567) (2926:2926:2926)) - (PORT d[7] (2254:2254:2254) (2544:2544:2544)) - (PORT d[8] (2452:2452:2452) (2774:2774:2774)) - (PORT d[9] (2619:2619:2619) (3004:3004:3004)) - (PORT d[10] (2502:2502:2502) (2822:2822:2822)) - (PORT d[11] (2565:2565:2565) (2889:2889:2889)) - (PORT d[12] (2495:2495:2495) (2818:2818:2818)) - (PORT clk (1059:1059:1059) (1078:1078:1078)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1062:1062:1062) (1079:1079:1079)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1063:1063:1063) (1080:1080:1080)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1063:1063:1063) (1080:1080:1080)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1063:1063:1063) (1080:1080:1080)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1063:1063:1063) (1080:1080:1080)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~40) - (DELAY - (ABSOLUTE - (PORT dataa (738:738:738) (852:852:852)) - (PORT datab (151:151:151) (204:204:204)) - (PORT datac (754:754:754) (847:847:847)) - (PORT datad (835:835:835) (953:953:953)) - (IOPATH dataa combout (195:195:195) (193:193:193)) - (IOPATH datab combout (188:188:188) (177:177:177)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (892:892:892) (1016:1016:1016)) - (PORT clk (1106:1106:1106) (1124:1124:1124)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1300:1300:1300) (1471:1471:1471)) - (PORT d[1] (1184:1184:1184) (1402:1402:1402)) - (PORT d[2] (1329:1329:1329) (1558:1558:1558)) - (PORT d[3] (1296:1296:1296) (1525:1525:1525)) - (PORT d[4] (1717:1717:1717) (2015:2015:2015)) - (PORT d[5] (1375:1375:1375) (1630:1630:1630)) - (PORT d[6] (1087:1087:1087) (1239:1239:1239)) - (PORT d[7] (1420:1420:1420) (1618:1618:1618)) - (PORT d[8] (1816:1816:1816) (2139:2139:2139)) - (PORT d[9] (1026:1026:1026) (1177:1177:1177)) - (PORT d[10] (1040:1040:1040) (1180:1180:1180)) - (PORT d[11] (1650:1650:1650) (1901:1901:1901)) - (PORT d[12] (1068:1068:1068) (1234:1234:1234)) - (PORT clk (1104:1104:1104) (1122:1122:1122)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1222:1222:1222) (1331:1331:1331)) - (PORT clk (1104:1104:1104) (1122:1122:1122)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1106:1106:1106) (1124:1124:1124)) - (PORT d[0] (1921:1921:1921) (1784:1784:1784)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1107:1107:1107) (1125:1125:1125)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1107:1107:1107) (1125:1125:1125)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1107:1107:1107) (1125:1125:1125)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1107:1107:1107) (1125:1125:1125)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1061:1061:1061) (1081:1081:1081)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1396:1396:1396) (1583:1583:1583)) - (PORT clk (1066:1066:1066) (1084:1084:1084)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2485:2485:2485) (2802:2802:2802)) - (PORT d[1] (2296:2296:2296) (2585:2585:2585)) - (PORT d[2] (2499:2499:2499) (2826:2826:2826)) - (PORT d[3] (2489:2489:2489) (2856:2856:2856)) - (PORT d[4] (2486:2486:2486) (2819:2819:2819)) - (PORT d[5] (2590:2590:2590) (2938:2938:2938)) - (PORT d[6] (2582:2582:2582) (2952:2952:2952)) - (PORT d[7] (2284:2284:2284) (2579:2579:2579)) - (PORT d[8] (2592:2592:2592) (2930:2930:2930)) - (PORT d[9] (2569:2569:2569) (2938:2938:2938)) - (PORT d[10] (2524:2524:2524) (2834:2834:2834)) - (PORT d[11] (2504:2504:2504) (2829:2829:2829)) - (PORT d[12] (2553:2553:2553) (2895:2895:2895)) - (PORT clk (1063:1063:1063) (1083:1083:1083)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1066:1066:1066) (1084:1084:1084)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1067:1067:1067) (1085:1085:1085)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1067:1067:1067) (1085:1085:1085)) - (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1067:1067:1067) (1085:1085:1085)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1067:1067:1067) (1085:1085:1085)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1062:1062:1062) (1082:1082:1082)) - (IOPATH (posedge clk) q (164:164:164) (166:166:166)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) (CELL (CELLTYPE "cycloneive_ram_register") (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (556:556:556) (637:637:637)) - (PORT d[1] (542:542:542) (629:629:629)) - (PORT d[2] (685:685:685) (787:787:787)) - (PORT d[3] (734:734:734) (855:855:855)) - (PORT d[4] (1524:1524:1524) (1788:1788:1788)) - (PORT d[5] (1750:1750:1750) (2051:2051:2051)) - (PORT d[6] (544:544:544) (626:626:626)) - (PORT d[7] (730:730:730) (835:835:835)) - (PORT d[8] (580:580:580) (669:669:669)) - (PORT d[9] (534:534:534) (619:619:619)) - (PORT d[10] (745:745:745) (856:856:856)) - (PORT d[11] (1492:1492:1492) (1736:1736:1736)) - (PORT d[12] (729:729:729) (842:842:842)) - (PORT clk (1095:1095:1095) (1112:1112:1112)) + (PORT d[0] (1306:1306:1306) (1508:1508:1508)) + (PORT d[1] (1966:1966:1966) (2241:2241:2241)) + (PORT d[2] (1340:1340:1340) (1558:1558:1558)) + (PORT d[3] (1360:1360:1360) (1581:1581:1581)) + (PORT d[4] (1518:1518:1518) (1750:1750:1750)) + (PORT d[5] (1531:1531:1531) (1789:1789:1789)) + (PORT d[6] (1861:1861:1861) (2136:2136:2136)) + (PORT d[7] (1349:1349:1349) (1567:1567:1567)) + (PORT d[8] (1473:1473:1473) (1689:1689:1689)) + (PORT d[9] (1593:1593:1593) (1855:1855:1855)) + (PORT d[10] (2227:2227:2227) (2597:2597:2597)) + (PORT d[11] (1476:1476:1476) (1698:1698:1698)) + (PORT d[12] (1388:1388:1388) (1580:1580:1580)) + (PORT clk (1096:1096:1096) (1113:1113:1113)) ) ) (TIMINGCHECK @@ -46377,8 +48259,8 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1095:1095:1095) (1112:1112:1112)) - (PORT d[0] (356:356:356) (332:332:332)) + (PORT clk (1096:1096:1096) (1113:1113:1113)) + (PORT d[0] (2546:2546:2546) (2288:2288:2288)) ) ) ) @@ -46387,7 +48269,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1096:1096:1096) (1113:1113:1113)) + (PORT clk (1097:1097:1097) (1114:1114:1114)) (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) ) ) @@ -46397,7 +48279,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1077:1077:1077) (1093:1093:1093)) + (PORT clk (1078:1078:1078) (1094:1094:1094)) (IOPATH (posedge clk) q (164:164:164) (167:167:167)) ) ) @@ -46411,7 +48293,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (617:617:617) (625:625:625)) + (PORT clk (618:618:618) (626:626:626)) ) ) ) @@ -46420,7 +48302,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (618:618:618) (626:626:626)) + (PORT clk (619:619:619) (627:627:627)) ) ) ) @@ -46429,7 +48311,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (618:618:618) (626:626:626)) + (PORT clk (619:619:619) (627:627:627)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) @@ -46439,38 +48321,439 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (618:618:618) (626:626:626)) + (PORT clk (619:619:619) (627:627:627)) (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~41) + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.datain_a_register) (DELAY (ABSOLUTE - (PORT dataa (697:697:697) (786:786:786)) - (PORT datab (482:482:482) (556:556:556)) - (PORT datac (468:468:468) (545:545:545)) - (PORT datad (95:95:95) (115:115:115)) - (IOPATH dataa combout (188:188:188) (179:179:179)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) + (PORT d[0] (869:869:869) (1004:1004:1004)) + (PORT clk (1088:1088:1088) (1106:1106:1106)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1593:1593:1593) (1874:1874:1874)) + (PORT d[1] (2109:2109:2109) (2414:2414:2414)) + (PORT d[2] (1327:1327:1327) (1548:1548:1548)) + (PORT d[3] (1090:1090:1090) (1263:1263:1263)) + (PORT d[4] (1980:1980:1980) (2270:2270:2270)) + (PORT d[5] (1561:1561:1561) (1817:1817:1817)) + (PORT d[6] (1697:1697:1697) (1956:1956:1956)) + (PORT d[7] (1536:1536:1536) (1778:1778:1778)) + (PORT d[8] (1225:1225:1225) (1421:1421:1421)) + (PORT d[9] (1663:1663:1663) (1930:1930:1930)) + (PORT d[10] (2078:2078:2078) (2422:2422:2422)) + (PORT d[11] (1296:1296:1296) (1507:1507:1507)) + (PORT d[12] (1733:1733:1733) (1972:1972:1972)) + (PORT clk (1086:1086:1086) (1104:1104:1104)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1320:1320:1320) (1451:1451:1451)) + (PORT clk (1086:1086:1086) (1104:1104:1104)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1088:1088:1088) (1106:1106:1106)) + (PORT d[0] (2965:2965:2965) (3260:3260:3260)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~42) + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_a) (DELAY (ABSOLUTE - (PORT dataa (109:109:109) (142:142:142)) - (PORT datab (155:155:155) (208:208:208)) - (PORT datac (901:901:901) (1024:1024:1024)) - (PORT datad (91:91:91) (108:108:108)) - (IOPATH dataa combout (172:172:172) (165:165:165)) - (IOPATH datab combout (169:169:169) (167:167:167)) + (PORT clk (1089:1089:1089) (1107:1107:1107)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1089:1089:1089) (1107:1107:1107)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1089:1089:1089) (1107:1107:1107)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1089:1089:1089) (1107:1107:1107)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1043:1043:1043) (1063:1063:1063)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (768:768:768) (891:891:891)) + (PORT clk (1048:1048:1048) (1066:1066:1066)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2316:2316:2316) (2651:2651:2651)) + (PORT d[1] (2369:2369:2369) (2712:2712:2712)) + (PORT d[2] (2312:2312:2312) (2640:2640:2640)) + (PORT d[3] (2424:2424:2424) (2787:2787:2787)) + (PORT d[4] (2332:2332:2332) (2654:2654:2654)) + (PORT d[5] (2407:2407:2407) (2756:2756:2756)) + (PORT d[6] (2304:2304:2304) (2600:2600:2600)) + (PORT d[7] (2259:2259:2259) (2582:2582:2582)) + (PORT d[8] (2452:2452:2452) (2783:2783:2783)) + (PORT d[9] (2295:2295:2295) (2616:2616:2616)) + (PORT d[10] (2384:2384:2384) (2704:2704:2704)) + (PORT d[11] (2424:2424:2424) (2746:2746:2746)) + (PORT d[12] (2340:2340:2340) (2671:2671:2671)) + (PORT clk (1045:1045:1045) (1065:1065:1065)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1048:1048:1048) (1066:1066:1066)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1049:1049:1049) (1067:1067:1067)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1049:1049:1049) (1067:1067:1067)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1049:1049:1049) (1067:1067:1067)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1049:1049:1049) (1067:1067:1067)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (939:939:939) (1085:1085:1085)) + (PORT clk (1094:1094:1094) (1112:1112:1112)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1575:1575:1575) (1806:1806:1806)) + (PORT d[1] (2084:2084:2084) (2383:2383:2383)) + (PORT d[2] (1537:1537:1537) (1787:1787:1787)) + (PORT d[3] (1256:1256:1256) (1463:1463:1463)) + (PORT d[4] (1808:1808:1808) (2078:2078:2078)) + (PORT d[5] (1662:1662:1662) (1909:1909:1909)) + (PORT d[6] (2164:2164:2164) (2480:2480:2480)) + (PORT d[7] (1530:1530:1530) (1774:1774:1774)) + (PORT d[8] (1342:1342:1342) (1542:1542:1542)) + (PORT d[9] (1521:1521:1521) (1768:1768:1768)) + (PORT d[10] (2090:2090:2090) (2443:2443:2443)) + (PORT d[11] (1312:1312:1312) (1522:1522:1522)) + (PORT d[12] (1730:1730:1730) (1964:1964:1964)) + (PORT clk (1092:1092:1092) (1110:1110:1110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1640:1640:1640) (1812:1812:1812)) + (PORT clk (1092:1092:1092) (1110:1110:1110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1094:1094:1094) (1112:1112:1112)) + (PORT d[0] (3238:3238:3238) (2972:2972:2972)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1095:1095:1095) (1113:1113:1113)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1095:1095:1095) (1113:1113:1113)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1095:1095:1095) (1113:1113:1113)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1095:1095:1095) (1113:1113:1113)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1049:1049:1049) (1069:1069:1069)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (581:581:581) (680:680:680)) + (PORT clk (1054:1054:1054) (1072:1072:1072)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2326:2326:2326) (2656:2656:2656)) + (PORT d[1] (2416:2416:2416) (2758:2758:2758)) + (PORT d[2] (2352:2352:2352) (2690:2690:2690)) + (PORT d[3] (2437:2437:2437) (2781:2781:2781)) + (PORT d[4] (2358:2358:2358) (2677:2677:2677)) + (PORT d[5] (2354:2354:2354) (2700:2700:2700)) + (PORT d[6] (2269:2269:2269) (2594:2594:2594)) + (PORT d[7] (2271:2271:2271) (2599:2599:2599)) + (PORT d[8] (2442:2442:2442) (2785:2785:2785)) + (PORT d[9] (2277:2277:2277) (2591:2591:2591)) + (PORT d[10] (2349:2349:2349) (2637:2637:2637)) + (PORT d[11] (2319:2319:2319) (2623:2623:2623)) + (PORT d[12] (2349:2349:2349) (2659:2659:2659)) + (PORT clk (1051:1051:1051) (1071:1071:1071)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1054:1054:1054) (1072:1072:1072)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1055:1055:1055) (1073:1073:1073)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1055:1055:1055) (1073:1073:1073)) + (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1055:1055:1055) (1073:1073:1073)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1055:1055:1055) (1073:1073:1073)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1050:1050:1050) (1070:1070:1070)) + (IOPATH (posedge clk) q (164:164:164) (166:166:166)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (328:328:328) (380:380:380)) + (PORT datab (323:323:323) (374:374:374)) + (PORT datac (700:700:700) (803:803:803)) + (PORT datad (855:855:855) (992:992:992)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH datab combout (167:167:167) (158:158:158)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -46478,31 +48761,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~105) + (INSTANCE Selector0\~1) (DELAY (ABSOLUTE - (PORT dataa (103:103:103) (134:134:134)) - (PORT datab (503:503:503) (592:592:592)) - (PORT datac (652:652:652) (768:768:768)) - (PORT datad (311:311:311) (358:358:358)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (169:169:169) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) + (PORT dataa (763:763:763) (866:866:866)) + (PORT datab (677:677:677) (774:774:774)) + (PORT datac (719:719:719) (821:821:821)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~45) + (INSTANCE D\[2\]\~82) (DELAY (ABSOLUTE - (PORT dataa (190:190:190) (237:237:237)) - (PORT datab (125:125:125) (156:156:156)) - (PORT datac (94:94:94) (118:118:118)) - (PORT datad (97:97:97) (117:117:117)) + (PORT dataa (902:902:902) (1095:1095:1095)) + (PORT datab (1445:1445:1445) (1704:1704:1704)) + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (90:90:90) (107:107:107)) (IOPATH dataa combout (181:181:181) (175:175:175)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datab combout (166:166:166) (158:158:158)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -46510,16 +48793,32 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~46) + (INSTANCE D\[2\]\~38) (DELAY (ABSOLUTE - (PORT dataa (220:220:220) (288:288:288)) - (PORT datab (125:125:125) (156:156:156)) - (PORT datac (613:613:613) (702:702:702)) - (PORT datad (89:89:89) (106:106:106)) - (IOPATH dataa combout (166:166:166) (163:163:163)) + (PORT dataa (901:901:901) (1034:1034:1034)) + (PORT datab (605:605:605) (703:703:703)) + (PORT datac (694:694:694) (810:810:810)) + (PORT datad (96:96:96) (116:116:116)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (182:182:182) (177:177:177)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (900:900:900) (1033:1033:1033)) + (PORT datab (847:847:847) (968:968:968)) + (PORT datac (1078:1078:1078) (1240:1240:1240)) + (PORT datad (92:92:92) (109:109:109)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -46529,11 +48828,11 @@ (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[2\]) (DELAY (ABSOLUTE - (PORT dataa (535:535:535) (638:638:638)) - (PORT datab (345:345:345) (406:406:406)) - (PORT datac (317:317:317) (356:356:356)) - (PORT datad (102:102:102) (119:119:119)) - (IOPATH dataa combout (166:166:166) (163:163:163)) + (PORT dataa (799:799:799) (916:916:916)) + (PORT datab (113:113:113) (142:142:142)) + (PORT datac (979:979:979) (1119:1119:1119)) + (PORT datad (196:196:196) (231:231:231)) + (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -46545,9 +48844,9 @@ (INSTANCE z80_\|data_pins_\|dout\[2\]) (DELAY (ABSOLUTE - (PORT clk (915:915:915) (902:902:902)) + (PORT clk (917:917:917) (904:904:904)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (652:652:652) (703:703:703)) + (PORT ena (421:421:421) (449:449:449)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -46561,11 +48860,11 @@ (INSTANCE z80_\|bus_control_\|db\[2\]\~12) (DELAY (ABSOLUTE - (PORT datab (493:493:493) (580:580:580)) - (PORT datac (518:518:518) (611:611:611)) - (PORT datad (117:117:117) (140:140:140)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (PORT dataa (295:295:295) (346:346:346)) + (PORT datac (181:181:181) (217:217:217)) + (PORT datad (748:748:748) (847:847:847)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -46575,13 +48874,13 @@ (INSTANCE z80_\|bus_control_\|db\[2\]\~13) (DELAY (ABSOLUTE - (PORT dataa (227:227:227) (286:286:286)) - (PORT datab (125:125:125) (158:158:158)) - (PORT datac (122:122:122) (151:151:151)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (159:159:159) (163:163:163)) + (PORT dataa (211:211:211) (255:255:255)) + (PORT datab (326:326:326) (382:382:382)) + (PORT datac (128:128:128) (169:169:169)) + (PORT datad (161:161:161) (190:190:190)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -46591,737 +48890,41 @@ (INSTANCE z80_\|ir_\|opcode\[2\]) (DELAY (ABSOLUTE - (PORT clk (906:906:906) (911:911:911)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (917:917:917) (902:902:902)) - (PORT ena (645:645:645) (697:697:697)) + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (371:371:371) (406:406:406)) + (PORT clrn (909:909:909) (896:896:896)) + (PORT ena (921:921:921) (1009:1009:1009)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) (HOLD ena (posedge clk) (84:84:84)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal3\~1) + (INSTANCE z80_\|pla_decode_\|Equal1\~4) (DELAY (ABSOLUTE - (PORT datac (811:811:811) (946:946:946)) - (PORT datad (1279:1279:1279) (1475:1475:1475)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal43\~0) - (DELAY - (ABSOLUTE - (PORT dataa (507:507:507) (594:594:594)) - (PORT datab (535:535:535) (622:622:622)) - (PORT datac (916:916:916) (1100:1100:1100)) - (PORT datad (695:695:695) (806:806:806)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|test1\~2) - (DELAY - (ABSOLUTE - (PORT dataa (102:102:102) (133:133:133)) - (PORT datab (114:114:114) (142:142:142)) - (PORT datac (104:104:104) (128:128:128)) - (PORT datad (103:103:103) (120:120:120)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|test1\~3) - (DELAY - (ABSOLUTE - (PORT dataa (455:455:455) (525:525:525)) - (PORT datab (1139:1139:1139) (1322:1322:1322)) - (PORT datac (717:717:717) (840:840:840)) - (PORT datad (595:595:595) (674:674:674)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|in_nmi_ALTERA_SYNTHESIZED) - (DELAY - (ABSOLUTE - (PORT clk (914:914:914) (922:922:922)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (928:928:928) (910:910:910)) - (PORT ena (890:890:890) (972:972:972)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|clk_delay_\|SYNTHESIZED_WIRE_4) - (DELAY - (ABSOLUTE - (PORT dataa (666:666:666) (786:786:786)) - (PORT datab (1137:1137:1137) (1320:1320:1320)) - (PORT datac (723:723:723) (853:853:853)) - (PORT datad (1052:1052:1052) (1203:1203:1203)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|clk_delay_\|SYNTHESIZED_WIRE_7) - (DELAY - (ABSOLUTE - (PORT clk (910:910:910) (917:917:917)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (924:924:924) (906:906:906)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|clk_delay_\|hold_clk_iorq) - (DELAY - (ABSOLUTE - (PORT datab (136:136:136) (186:186:186)) - (PORT datad (124:124:124) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_T1_ff) - (DELAY - (ABSOLUTE - (PORT clk (920:920:920) (927:927:927)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (927:927:927) (908:908:908)) - (PORT ena (1086:1086:1086) (1232:1232:1232)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_13) - (DELAY - (ABSOLUTE - (PORT dataa (143:143:143) (194:194:194)) - (PORT datac (600:600:600) (695:695:695)) - (PORT datad (605:605:605) (699:699:699)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_T2_ff) - (DELAY - (ABSOLUTE - (PORT clk (920:920:920) (927:927:927)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (927:927:927) (908:908:908)) - (PORT ena (1086:1086:1086) (1232:1232:1232)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|resets_\|x3) - (DELAY - (ABSOLUTE - (PORT dataa (1330:1330:1330) (1557:1557:1557)) - (PORT datac (130:130:130) (172:172:172)) - (PORT datad (763:763:763) (913:913:913)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_12) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (908:908:908)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (1092:1092:1092) (1064:1064:1064)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_clkctrl") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_12\~clkctrl) - (DELAY - (ABSOLUTE - (PORT inclk[0] (903:903:903) (996:996:996)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_M1_ff) - (DELAY - (ABSOLUTE - (PORT clk (920:920:920) (927:927:927)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (927:927:927) (908:908:908)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|DFFE_M2_ff\~0) - (DELAY - (ABSOLUTE - (PORT dataa (615:615:615) (720:720:720)) - (PORT datab (152:152:152) (205:205:205)) - (PORT datad (607:607:607) (702:702:702)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_M2_ff) - (DELAY - (ABSOLUTE - (PORT clk (920:920:920) (927:927:927)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (927:927:927) (908:908:908)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~3) - (DELAY - (ABSOLUTE - (PORT datac (595:595:595) (716:716:716)) - (PORT datad (1126:1126:1126) (1302:1302:1302)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~11) - (DELAY - (ABSOLUTE - (PORT dataa (823:823:823) (951:951:951)) - (PORT datab (464:464:464) (536:536:536)) - (PORT datac (431:431:431) (489:489:489)) - (PORT datad (364:364:364) (427:427:427)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~8) - (DELAY - (ABSOLUTE - (PORT dataa (554:554:554) (656:656:656)) - (PORT datab (359:359:359) (422:422:422)) - (PORT datac (531:531:531) (627:627:627)) - (PORT datad (1266:1266:1266) (1455:1455:1455)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~9) - (DELAY - (ABSOLUTE - (PORT dataa (477:477:477) (547:547:547)) - (PORT datab (452:452:452) (517:517:517)) - (PORT datac (520:520:520) (602:602:602)) - (PORT datad (212:212:212) (253:253:253)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~10) - (DELAY - (ABSOLUTE - (PORT dataa (367:367:367) (435:435:435)) - (PORT datab (171:171:171) (208:208:208)) - (PORT datac (833:833:833) (964:964:964)) - (PORT datad (1187:1187:1187) (1363:1363:1363)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~12) - (DELAY - (ABSOLUTE - (PORT dataa (205:205:205) (243:243:243)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (89:89:89) (110:110:110)) - (PORT datad (95:95:95) (114:114:114)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1106:1106:1106) (1287:1287:1287)) - (PORT datab (467:467:467) (544:544:544)) - (PORT datac (786:786:786) (909:909:909)) - (PORT datad (95:95:95) (114:114:114)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~6) - (DELAY - (ABSOLUTE - (PORT dataa (123:123:123) (157:157:157)) - (PORT datab (125:125:125) (157:157:157)) - (PORT datac (180:180:180) (218:218:218)) - (PORT datad (582:582:582) (648:648:648)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~7) - (DELAY - (ABSOLUTE - (PORT dataa (124:124:124) (158:158:158)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (554:554:554) (656:656:656)) - (PORT datad (428:428:428) (489:489:489)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~13) - (DELAY - (ABSOLUTE - (PORT datab (602:602:602) (697:697:697)) - (PORT datac (90:90:90) (112:112:112)) - (PORT datad (161:161:161) (190:190:190)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~39) - (DELAY - (ABSOLUTE - (PORT datac (411:411:411) (470:470:470)) - (PORT datad (333:333:333) (382:382:382)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~5) - (DELAY - (ABSOLUTE - (PORT dataa (108:108:108) (139:139:139)) - (PORT datab (1136:1136:1136) (1298:1298:1298)) - (PORT datac (345:345:345) (408:408:408)) - (PORT datad (173:173:173) (194:194:194)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~14) - (DELAY - (ABSOLUTE - (PORT dataa (446:446:446) (508:508:508)) - (PORT datab (478:478:478) (557:557:557)) - (PORT datac (564:564:564) (640:640:640)) - (PORT datad (281:281:281) (321:321:321)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_15) - (DELAY - (ABSOLUTE - (PORT datab (147:147:147) (198:198:198)) - (PORT datac (596:596:596) (691:691:691)) - (PORT datad (609:609:609) (703:703:703)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_T4_ff) - (DELAY - (ABSOLUTE - (PORT clk (920:920:920) (927:927:927)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (927:927:927) (908:908:908)) - (PORT ena (1086:1086:1086) (1232:1232:1232)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_16) - (DELAY - (ABSOLUTE - (PORT dataa (611:611:611) (715:715:715)) - (PORT datac (133:133:133) (177:177:177)) - (PORT datad (611:611:611) (706:706:706)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_T5_ff) - (DELAY - (ABSOLUTE - (PORT clk (920:920:920) (927:927:927)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (927:927:927) (908:908:908)) - (PORT ena (1086:1086:1086) (1232:1232:1232)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_17) - (DELAY - (ABSOLUTE - (PORT datab (143:143:143) (191:191:191)) - (PORT datac (589:589:589) (684:684:684)) - (PORT datad (614:614:614) (709:709:709)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|T6) - (DELAY - (ABSOLUTE - (PORT clk (920:920:920) (927:927:927)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (927:927:927) (908:908:908)) - (PORT ena (1086:1086:1086) (1232:1232:1232)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~13) - (DELAY - (ABSOLUTE - (PORT dataa (316:316:316) (367:367:367)) - (PORT datab (483:483:483) (558:558:558)) - (PORT datac (325:325:325) (377:377:377)) - (PORT datad (510:510:510) (594:594:594)) - (IOPATH dataa combout (158:158:158) (157:157:157)) + (PORT datab (947:947:947) (1096:1096:1096)) + (PORT datac (347:347:347) (419:419:419)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal77\~1) + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~26) (DELAY (ABSOLUTE - (PORT dataa (572:572:572) (695:695:695)) - (PORT datab (658:658:658) (767:767:767)) - (PORT datac (372:372:372) (439:439:439)) - (PORT datad (717:717:717) (834:834:834)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~12) - (DELAY - (ABSOLUTE - (PORT dataa (364:364:364) (431:431:431)) - (PORT datab (915:915:915) (1053:1053:1053)) - (PORT datac (469:469:469) (544:544:544)) - (PORT datad (464:464:464) (535:535:535)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~14) - (DELAY - (ABSOLUTE - (PORT datab (102:102:102) (129:129:129)) - (PORT datac (352:352:352) (408:408:408)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~41) - (DELAY - (ABSOLUTE - (PORT dataa (210:210:210) (260:260:260)) - (PORT datac (576:576:576) (672:672:672)) - (PORT datad (108:108:108) (127:127:127)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~42) - (DELAY - (ABSOLUTE - (PORT dataa (510:510:510) (599:599:599)) - (PORT datab (614:614:614) (734:734:734)) - (PORT datac (216:216:216) (266:266:266)) - (PORT datad (1392:1392:1392) (1611:1611:1611)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~43) - (DELAY - (ABSOLUTE - (PORT dataa (1149:1149:1149) (1358:1358:1358)) - (PORT datab (437:437:437) (524:524:524)) - (PORT datac (526:526:526) (610:610:610)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~44) - (DELAY - (ABSOLUTE - (PORT dataa (481:481:481) (557:557:557)) - (PORT datab (184:184:184) (223:223:223)) - (PORT datac (108:108:108) (131:131:131)) - (PORT datad (406:406:406) (458:458:458)) + (PORT dataa (339:339:339) (402:402:402)) + (PORT datab (302:302:302) (358:358:358)) + (PORT datac (447:447:447) (520:520:520)) + (PORT datad (491:491:491) (590:590:590)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~50) - (DELAY - (ABSOLUTE - (PORT dataa (193:193:193) (230:230:230)) - (PORT datab (586:586:586) (660:660:660)) - (PORT datac (89:89:89) (110:110:110)) - (PORT datad (729:729:729) (821:821:821)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~51) - (DELAY - (ABSOLUTE - (PORT dataa (610:610:610) (707:707:707)) - (PORT datab (102:102:102) (131:131:131)) - (PORT datac (105:105:105) (128:128:128)) - (PORT datad (95:95:95) (113:113:113)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~6) - (DELAY - (ABSOLUTE - (PORT dataa (453:453:453) (522:522:522)) - (PORT datab (908:908:908) (1071:1071:1071)) - (PORT datac (339:339:339) (389:389:389)) - (PORT datad (960:960:960) (1120:1120:1120)) - (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -47330,45 +48933,61 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~7) + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~45) (DELAY (ABSOLUTE - (PORT datab (495:495:495) (584:584:584)) - (PORT datac (492:492:492) (563:563:563)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~8) - (DELAY - (ABSOLUTE - (PORT dataa (792:792:792) (928:928:928)) - (PORT datab (471:471:471) (548:548:548)) - (PORT datac (484:484:484) (562:562:562)) - (PORT datad (338:338:338) (387:387:387)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~9) - (DELAY - (ABSOLUTE - (PORT dataa (849:849:849) (998:998:998)) - (PORT datab (1114:1114:1114) (1277:1277:1277)) - (PORT datac (759:759:759) (892:892:892)) - (PORT datad (616:616:616) (699:699:699)) + (PORT dataa (366:366:366) (435:435:435)) + (PORT datab (721:721:721) (864:864:864)) + (PORT datac (517:517:517) (608:608:608)) + (PORT datad (1327:1327:1327) (1519:1519:1519)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~17) + (DELAY + (ABSOLUTE + (PORT dataa (645:645:645) (748:748:748)) + (PORT datac (322:322:322) (373:373:373)) + (PORT datad (368:368:368) (435:435:435)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~18) + (DELAY + (ABSOLUTE + (PORT dataa (365:365:365) (432:432:432)) + (PORT datab (101:101:101) (129:129:129)) + (PORT datac (313:313:313) (358:358:358)) + (PORT datad (426:426:426) (482:482:482)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~11) + (DELAY + (ABSOLUTE + (PORT dataa (517:517:517) (613:613:613)) + (PORT datab (946:946:946) (1095:1095:1095)) + (PORT datac (315:315:315) (371:371:371)) + (PORT datad (869:869:869) (1008:1008:1008)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -47379,11 +48998,11 @@ (INSTANCE z80_\|execute_\|setM1\~10) (DELAY (ABSOLUTE - (PORT dataa (115:115:115) (144:144:144)) - (PORT datab (622:622:622) (714:714:714)) - (PORT datac (266:266:266) (299:299:299)) - (PORT datad (351:351:351) (408:408:408)) - (IOPATH dataa combout (158:158:158) (163:163:163)) + (PORT dataa (363:363:363) (437:437:437)) + (PORT datab (357:357:357) (421:421:421)) + (PORT datac (524:524:524) (604:604:604)) + (PORT datad (938:938:938) (1080:1080:1080)) + (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -47392,15 +49011,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~11) + (INSTANCE z80_\|execute_\|setM1\~12) (DELAY (ABSOLUTE - (PORT dataa (104:104:104) (135:135:135)) - (PORT datab (652:652:652) (767:767:767)) - (PORT datac (562:562:562) (667:667:667)) - (PORT datad (174:174:174) (206:206:206)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (167:167:167) (156:156:156)) + (PORT dataa (712:712:712) (829:829:829)) + (PORT datab (467:467:467) (537:537:537)) + (PORT datac (1192:1192:1192) (1350:1350:1350)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -47408,30 +49027,90 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~17) + (INSTANCE z80_\|execute_\|setM1\~8) (DELAY (ABSOLUTE - (PORT dataa (343:343:343) (405:405:405)) - (PORT datab (585:585:585) (659:659:659)) - (PORT datac (1117:1117:1117) (1277:1277:1277)) - (PORT datad (333:333:333) (385:385:385)) + (PORT dataa (204:204:204) (251:251:251)) + (PORT datab (580:580:580) (695:695:695)) + (PORT datac (701:701:701) (820:820:820)) + (PORT datad (1022:1022:1022) (1183:1183:1183)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~9) + (DELAY + (ABSOLUTE + (PORT dataa (910:910:910) (1042:1042:1042)) + (PORT datab (604:604:604) (725:725:725)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~13) + (DELAY + (ABSOLUTE + (PORT dataa (483:483:483) (559:559:559)) + (PORT datab (102:102:102) (129:129:129)) + (PORT datac (590:590:590) (663:663:663)) + (PORT datad (270:270:270) (310:310:310)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~15) + (DELAY + (ABSOLUTE + (PORT dataa (473:473:473) (545:545:545)) + (PORT datab (786:786:786) (899:899:899)) + (PORT datac (445:445:445) (518:518:518)) + (PORT datad (166:166:166) (190:190:190)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~31) + (INSTANCE z80_\|execute_\|setM1\~14) (DELAY (ABSOLUTE - (PORT dataa (330:330:330) (391:391:391)) - (PORT datab (500:500:500) (587:587:587)) - (PORT datac (1026:1026:1026) (1197:1197:1197)) - (PORT datad (475:475:475) (555:555:555)) - (IOPATH dataa combout (170:170:170) (163:163:163)) + (PORT dataa (597:597:597) (688:688:688)) + (PORT datab (349:349:349) (409:409:409)) + (PORT datac (101:101:101) (122:122:122)) + (PORT datad (466:466:466) (541:541:541)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~16) + (DELAY + (ABSOLUTE + (PORT datab (501:501:501) (587:587:587)) + (PORT datac (293:293:293) (328:328:328)) + (PORT datad (89:89:89) (106:106:106)) (IOPATH datab combout (167:167:167) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -47440,93 +49119,63 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~28) + (INSTANCE z80_\|execute_\|setM1\~19) (DELAY (ABSOLUTE - (PORT dataa (187:187:187) (232:232:232)) - (PORT datab (670:670:670) (786:786:786)) - (PORT datac (786:786:786) (906:906:906)) - (PORT datad (457:457:457) (524:524:524)) + (PORT dataa (636:636:636) (723:723:723)) + (PORT datab (337:337:337) (392:392:392)) + (PORT datac (209:209:209) (253:253:253)) + (PORT datad (728:728:728) (852:852:852)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~30) + (INSTANCE z80_\|execute_\|setM1\~23) (DELAY (ABSOLUTE - (PORT dataa (463:463:463) (545:545:545)) - (PORT datab (503:503:503) (579:579:579)) - (PORT datac (500:500:500) (569:569:569)) - (PORT datad (453:453:453) (528:528:528)) - (IOPATH dataa combout (158:158:158) (157:157:157)) + (PORT dataa (686:686:686) (804:804:804)) + (PORT datab (348:348:348) (411:411:411)) + (PORT datac (169:169:169) (203:203:203)) + (PORT datad (328:328:328) (384:384:384)) + (IOPATH dataa combout (165:165:165) (159:159:159)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~32) + (INSTANCE z80_\|execute_\|setM1\~22) (DELAY (ABSOLUTE - (PORT dataa (507:507:507) (592:592:592)) - (PORT datab (186:186:186) (224:224:224)) - (PORT datac (481:481:481) (558:558:558)) - (PORT datad (610:610:610) (697:697:697)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~33) - (DELAY - (ABSOLUTE - (PORT dataa (313:313:313) (364:364:364)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (496:496:496) (577:577:577)) - (PORT datad (90:90:90) (106:106:106)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~25) - (DELAY - (ABSOLUTE - (PORT dataa (630:630:630) (731:731:731)) - (PORT datac (331:331:331) (393:393:393)) - (PORT datad (900:900:900) (1053:1053:1053)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~26) - (DELAY - (ABSOLUTE - (PORT dataa (487:487:487) (564:564:564)) - (PORT datab (864:864:864) (1009:1009:1009)) - (PORT datac (485:485:485) (555:555:555)) - (PORT datad (638:638:638) (731:731:731)) + (PORT dataa (830:830:830) (974:974:974)) + (PORT datab (347:347:347) (408:408:408)) + (PORT datac (719:719:719) (857:857:857)) + (PORT datad (877:877:877) (1019:1019:1019)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~56) + (DELAY + (ABSOLUTE + (PORT dataa (158:158:158) (215:215:215)) + (PORT datab (145:145:145) (194:194:194)) + (PORT datac (208:208:208) (257:257:257)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -47537,58 +49186,10 @@ (INSTANCE z80_\|execute_\|setM1\~24) (DELAY (ABSOLUTE - (PORT dataa (366:366:366) (433:433:433)) - (PORT datab (359:359:359) (421:421:421)) - (PORT datac (1113:1113:1113) (1238:1238:1238)) - (PORT datad (530:530:530) (626:626:626)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~27) - (DELAY - (ABSOLUTE - (PORT dataa (103:103:103) (134:134:134)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (354:354:354) (420:420:420)) - (PORT datad (380:380:380) (450:450:450)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~22) - (DELAY - (ABSOLUTE - (PORT dataa (515:515:515) (596:596:596)) - (PORT datab (485:485:485) (566:566:566)) - (PORT datac (482:482:482) (565:565:565)) - (PORT datad (329:329:329) (379:379:379)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~21) - (DELAY - (ABSOLUTE - (PORT dataa (996:996:996) (1155:1155:1155)) - (PORT datab (875:875:875) (1044:1044:1044)) - (PORT datac (680:680:680) (794:794:794)) - (PORT datad (846:846:846) (968:968:968)) + (PORT dataa (541:541:541) (628:628:628)) + (PORT datab (380:380:380) (452:452:452)) + (PORT datac (364:364:364) (432:432:432)) + (PORT datad (172:172:172) (203:203:203)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -47598,13 +49199,125 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~53) + (INSTANCE z80_\|execute_\|setM1\~25) (DELAY (ABSOLUTE - (PORT dataa (531:531:531) (620:620:620)) - (PORT datab (519:519:519) (605:605:605)) - (PORT datac (347:347:347) (411:411:411)) - (PORT datad (711:711:711) (805:805:805)) + (PORT dataa (467:467:467) (550:550:550)) + (PORT datab (507:507:507) (607:607:607)) + (PORT datac (312:312:312) (370:370:370)) + (PORT datad (478:478:478) (547:547:547)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~26) + (DELAY + (ABSOLUTE + (PORT dataa (942:942:942) (1078:1078:1078)) + (PORT datab (662:662:662) (785:785:785)) + (PORT datac (465:465:465) (530:530:530)) + (PORT datad (107:107:107) (126:126:126)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~27) + (DELAY + (ABSOLUTE + (PORT dataa (496:496:496) (572:572:572)) + (PORT datab (537:537:537) (635:635:635)) + (PORT datac (473:473:473) (549:549:549)) + (PORT datad (1074:1074:1074) (1231:1231:1231)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~28) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (133:133:133)) + (PORT datab (114:114:114) (142:142:142)) + (PORT datac (313:313:313) (366:366:366)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~55) + (DELAY + (ABSOLUTE + (PORT dataa (643:643:643) (732:732:732)) + (PORT datab (246:246:246) (310:310:310)) + (PORT datac (220:220:220) (277:277:277)) + (PORT datad (904:904:904) (1043:1043:1043)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~29) + (DELAY + (ABSOLUTE + (PORT dataa (389:389:389) (452:452:452)) + (PORT datab (342:342:342) (407:407:407)) + (PORT datac (475:475:475) (552:552:552)) + (PORT datad (338:338:338) (385:385:385)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~31) + (DELAY + (ABSOLUTE + (PORT dataa (117:117:117) (149:149:149)) + (PORT datab (715:715:715) (830:830:830)) + (PORT datac (89:89:89) (110:110:110)) + (PORT datad (309:309:309) (356:356:356)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~33) + (DELAY + (ABSOLUTE + (PORT dataa (638:638:638) (752:752:752)) + (PORT datab (1078:1078:1078) (1222:1222:1222)) + (PORT datac (319:319:319) (375:375:375)) + (PORT datad (632:632:632) (734:734:734)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -47614,47 +49327,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~23) + (INSTANCE z80_\|execute_\|setM1\~32) (DELAY (ABSOLUTE - (PORT dataa (102:102:102) (133:133:133)) - (PORT datab (190:190:190) (228:228:228)) - (PORT datac (866:866:866) (1002:1002:1002)) - (PORT datad (89:89:89) (106:106:106)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~18) - (DELAY - (ABSOLUTE - (PORT dataa (194:194:194) (236:236:236)) - (PORT datab (533:533:533) (619:619:619)) - (PORT datac (844:844:844) (991:991:991)) - (PORT datad (101:101:101) (119:119:119)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~19) - (DELAY - (ABSOLUTE - (PORT dataa (331:331:331) (387:387:387)) - (PORT datab (388:388:388) (463:463:463)) - (PORT datac (364:364:364) (431:431:431)) - (PORT datad (744:744:744) (877:877:877)) + (PORT dataa (449:449:449) (523:523:523)) + (PORT datab (381:381:381) (451:451:451)) + (PORT datac (323:323:323) (366:366:366)) + (PORT datad (622:622:622) (712:712:712)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~34) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (1671:1671:1671) (1899:1899:1899)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -47665,12 +49362,58 @@ (INSTANCE z80_\|execute_\|setM1\~20) (DELAY (ABSOLUTE - (PORT dataa (345:345:345) (414:414:414)) - (PORT datab (645:645:645) (743:743:743)) - (PORT datac (495:495:495) (574:574:574)) - (PORT datad (332:332:332) (388:388:388)) + (PORT dataa (484:484:484) (551:551:551)) + (PORT datab (514:514:514) (614:614:614)) + (PORT datac (110:110:110) (135:135:135)) + (PORT datad (772:772:772) (869:869:869)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~21) + (DELAY + (ABSOLUTE + (PORT dataa (328:328:328) (394:394:394)) + (PORT datab (537:537:537) (635:635:635)) + (PORT datac (655:655:655) (768:768:768)) + (PORT datad (297:297:297) (342:342:342)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~35) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (136:136:136)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (88:88:88) (109:109:109)) + (PORT datad (93:93:93) (111:111:111)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~43) + (DELAY + (ABSOLUTE + (PORT datab (507:507:507) (602:602:602)) + (PORT datac (696:696:696) (813:813:813)) + (PORT datad (364:364:364) (426:426:426)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -47678,16 +49421,48 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~34) + (INSTANCE z80_\|execute_\|setM1\~44) (DELAY (ABSOLUTE - (PORT dataa (334:334:334) (394:394:394)) - (PORT datab (102:102:102) (130:130:130)) - (PORT datac (160:160:160) (190:190:190)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT dataa (599:599:599) (679:679:679)) + (PORT datab (702:702:702) (810:810:810)) + (PORT datac (931:931:931) (1061:1061:1061)) + (PORT datad (619:619:619) (745:745:745)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~45) + (DELAY + (ABSOLUTE + (PORT dataa (1086:1086:1086) (1246:1246:1246)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (1369:1369:1369) (1590:1590:1590)) + (PORT datad (191:191:191) (226:226:226)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~46) + (DELAY + (ABSOLUTE + (PORT dataa (463:463:463) (556:556:556)) + (PORT datab (530:530:530) (623:623:623)) + (PORT datac (339:339:339) (402:402:402)) + (PORT datad (98:98:98) (119:119:119)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -47697,496 +49472,10 @@ (INSTANCE z80_\|execute_\|setM1\~52) (DELAY (ABSOLUTE - (PORT dataa (104:104:104) (135:135:135)) - (PORT datab (103:103:103) (131:131:131)) - (PORT datac (159:159:159) (187:187:187)) - (PORT datad (542:542:542) (636:636:636)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_14) - (DELAY - (ABSOLUTE - (PORT dataa (608:608:608) (712:712:712)) - (PORT datac (135:135:135) (179:179:179)) - (PORT datad (613:613:613) (708:708:708)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_T3_ff) - (DELAY - (ABSOLUTE - (PORT clk (920:920:920) (927:927:927)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (927:927:927) (908:908:908)) - (PORT ena (1086:1086:1086) (1232:1232:1232)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_1M1T3_3) - (DELAY - (ABSOLUTE - (PORT datac (551:551:551) (648:648:648)) - (PORT datad (763:763:763) (910:910:910)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|in_halt\~0) - (DELAY - (ABSOLUTE - (PORT dataa (207:207:207) (285:285:285)) - (PORT datac (652:652:652) (766:766:766)) - (PORT datad (151:151:151) (195:195:195)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|in_halt\~1) - (DELAY - (ABSOLUTE - (PORT dataa (355:355:355) (422:422:422)) - (PORT datab (878:878:878) (991:991:991)) - (PORT datad (347:347:347) (409:409:409)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|in_halt) - (DELAY - (ABSOLUTE - (PORT clk (903:903:903) (908:908:908)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (914:914:914) (898:898:898)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~2) - (DELAY - (ABSOLUTE - (PORT dataa (536:536:536) (641:641:641)) - (PORT datab (645:645:645) (740:740:740)) - (PORT datac (367:367:367) (429:429:429)) - (PORT datad (349:349:349) (407:407:407)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~5) - (DELAY - (ABSOLUTE - (PORT dataa (651:651:651) (785:785:785)) - (PORT datab (550:550:550) (651:651:651)) - (PORT datac (635:635:635) (737:737:737)) - (PORT datad (485:485:485) (566:566:566)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~6) - (DELAY - (ABSOLUTE - (PORT dataa (210:210:210) (249:249:249)) - (PORT datab (382:382:382) (454:454:454)) - (PORT datac (493:493:493) (572:572:572)) - (PORT datad (91:91:91) (108:108:108)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~4) - (DELAY - (ABSOLUTE - (PORT datac (576:576:576) (667:667:667)) - (PORT datad (344:344:344) (397:397:397)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe) - (DELAY - (ABSOLUTE - (PORT dataa (115:115:115) (145:145:145)) - (PORT datab (516:516:516) (610:610:610)) - (PORT datac (335:335:335) (396:396:396)) - (PORT datad (90:90:90) (106:106:106)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[0\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (135:135:135) (173:173:173)) - (PORT datac (517:517:517) (609:609:609)) - (PORT datad (174:174:174) (202:202:202)) - (IOPATH dataa combout (165:165:165) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]\~93) - (DELAY - (ABSOLUTE - (PORT dataa (123:123:123) (161:161:161)) - (PORT datab (432:432:432) (531:531:531)) - (PORT datac (759:759:759) (915:915:915)) - (PORT datad (296:296:296) (336:336:336)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]\~94) - (DELAY - (ABSOLUTE - (PORT dataa (331:331:331) (398:398:398)) - (PORT datab (408:408:408) (499:499:499)) - (PORT datad (402:402:402) (484:484:484)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH datab combout (190:190:190) (181:181:181)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (910:910:910) (916:916:916)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]\~96) - (DELAY - (ABSOLUTE - (PORT dataa (415:415:415) (511:511:511)) - (PORT datab (657:657:657) (772:772:772)) - (PORT datac (407:407:407) (493:493:493)) - (PORT datad (410:410:410) (510:510:510)) - (IOPATH dataa combout (158:158:158) (173:173:173)) - (IOPATH datab combout (160:160:160) (176:176:176)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]\~98) - (DELAY - (ABSOLUTE - (PORT dataa (108:108:108) (140:140:140)) - (PORT datab (110:110:110) (141:141:141)) - (PORT datad (98:98:98) (118:118:118)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH datab combout (190:190:190) (181:181:181)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (910:910:910) (916:916:916)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~65) - (DELAY - (ABSOLUTE - (PORT dataa (593:593:593) (688:688:688)) - (PORT datab (644:644:644) (754:754:754)) - (PORT datac (118:118:118) (160:160:160)) - (PORT datad (189:189:189) (235:235:235)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (166:166:166) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]\~99) - (DELAY - (ABSOLUTE - (PORT dataa (412:412:412) (521:521:521)) - (PORT datab (397:397:397) (488:488:488)) - (PORT datac (478:478:478) (565:565:565)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]\~100) - (DELAY - (ABSOLUTE - (PORT dataa (177:177:177) (217:217:217)) - (PORT datab (104:104:104) (133:133:133)) - (PORT datad (402:402:402) (492:492:492)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH datab combout (190:190:190) (181:181:181)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (914:914:914) (918:918:918)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (909:909:909) (914:914:914)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~101) - (DELAY - (ABSOLUTE - (PORT dataa (410:410:410) (505:505:505)) - (PORT datab (538:538:538) (645:645:645)) - (PORT datad (507:507:507) (606:606:606)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~102) - (DELAY - (ABSOLUTE - (PORT dataa (417:417:417) (513:513:513)) - (PORT datab (406:406:406) (497:497:497)) - (PORT datac (639:639:639) (748:748:748)) - (PORT datad (492:492:492) (585:585:585)) - (IOPATH dataa combout (158:158:158) (173:173:173)) - (IOPATH datab combout (160:160:160) (176:176:176)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~133) - (DELAY - (ABSOLUTE - (PORT dataa (363:363:363) (429:429:429)) - (PORT datab (105:105:105) (134:134:134)) - (PORT datac (409:409:409) (495:495:495)) - (PORT datad (404:404:404) (504:504:504)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~103) - (DELAY - (ABSOLUTE - (PORT dataa (104:104:104) (135:135:135)) - (PORT datad (165:165:165) (195:195:195)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (911:911:911) (916:916:916)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~66) - (DELAY - (ABSOLUTE - (PORT dataa (314:314:314) (364:364:364)) - (PORT datab (217:217:217) (275:275:275)) - (PORT datac (294:294:294) (339:339:339)) - (PORT datad (338:338:338) (406:406:406)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]\~104) - (DELAY - (ABSOLUTE - (PORT dataa (397:397:397) (488:488:488)) - (PORT datab (404:404:404) (494:494:494)) - (PORT datac (399:399:399) (489:489:489)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]\~105) - (DELAY - (ABSOLUTE - (PORT dataa (105:105:105) (137:137:137)) - (PORT datab (191:191:191) (231:231:231)) - (PORT datad (402:402:402) (484:484:484)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH datab combout (190:190:190) (181:181:181)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (910:910:910) (916:916:916)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~106) - (DELAY - (ABSOLUTE - (PORT dataa (791:791:791) (952:952:952)) - (PORT datab (114:114:114) (147:147:147)) - (PORT datac (517:517:517) (615:615:615)) - (PORT datad (108:108:108) (128:128:128)) + (PORT dataa (712:712:712) (826:826:826)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (204:204:204) (247:247:247)) + (PORT datad (338:338:338) (394:394:394)) (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -48196,1676 +49485,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Selector5\~1) + (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_17) (DELAY (ABSOLUTE - (PORT dataa (379:379:379) (479:479:479)) - (PORT datab (355:355:355) (429:429:429)) - (PORT datac (345:345:345) (419:419:419)) - (PORT datad (228:228:228) (285:285:285)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Selector5\~0) - (DELAY - (ABSOLUTE - (PORT dataa (122:122:122) (156:156:156)) - (PORT datab (217:217:217) (280:280:280)) - (PORT datac (333:333:333) (402:402:402)) - (PORT datad (214:214:214) (265:265:265)) + (PORT dataa (588:588:588) (683:683:683)) + (PORT datac (477:477:477) (576:576:576)) + (PORT datad (193:193:193) (229:229:229)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~134) - (DELAY - (ABSOLUTE - (PORT dataa (192:192:192) (229:229:229)) - (PORT datab (193:193:193) (232:232:232)) - (PORT datad (440:440:440) (513:513:513)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~107) - (DELAY - (ABSOLUTE - (PORT dataa (410:410:410) (492:492:492)) - (PORT datab (327:327:327) (387:387:387)) - (PORT datac (328:328:328) (391:391:391)) - (PORT datad (271:271:271) (307:307:307)) - (IOPATH dataa combout (172:172:172) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~135) - (DELAY - (ABSOLUTE - (PORT dataa (409:409:409) (491:491:491)) - (PORT datab (148:148:148) (198:198:198)) - (PORT datad (595:595:595) (692:692:692)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~108) - (DELAY - (ABSOLUTE - (PORT dataa (105:105:105) (137:137:137)) - (PORT datab (190:190:190) (235:235:235)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH datab combout (190:190:190) (181:181:181)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (913:913:913) (917:917:917)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (909:909:909) (914:914:914)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~67) - (DELAY - (ABSOLUTE - (PORT dataa (130:130:130) (179:179:179)) - (PORT datab (663:663:663) (779:779:779)) - (PORT datac (342:342:342) (408:408:408)) - (PORT datad (418:418:418) (478:478:478)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]\~112) - (DELAY - (ABSOLUTE - (PORT dataa (461:461:461) (535:535:535)) - (PORT datab (119:119:119) (153:153:153)) - (PORT datac (342:342:342) (411:411:411)) - (PORT datad (167:167:167) (196:196:196)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]\~113) - (DELAY - (ABSOLUTE - (PORT dataa (378:378:378) (478:478:478)) - (PORT datab (106:106:106) (135:135:135)) - (PORT datac (297:297:297) (351:351:351)) - (PORT datad (251:251:251) (308:308:308)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]\~114) - (DELAY - (ABSOLUTE - (PORT datab (296:296:296) (344:344:344)) - (PORT datad (470:470:470) (539:539:539)) - (IOPATH datab combout (191:191:191) (181:181:181)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (912:912:912)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (903:903:903) (908:908:908)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~109) - (DELAY - (ABSOLUTE - (PORT dataa (386:386:386) (488:488:488)) - (PORT datab (345:345:345) (418:418:418)) - (PORT datac (343:343:343) (411:411:411)) - (PORT datad (424:424:424) (495:495:495)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~110) - (DELAY - (ABSOLUTE - (PORT dataa (382:382:382) (483:483:483)) - (PORT datab (117:117:117) (150:150:150)) - (PORT datac (90:90:90) (112:112:112)) - (PORT datad (341:341:341) (406:406:406)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~137) - (DELAY - (ABSOLUTE - (PORT dataa (405:405:405) (485:485:485)) - (PORT datab (171:171:171) (209:209:209)) - (PORT datad (177:177:177) (212:212:212)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~138) - (DELAY - (ABSOLUTE - (PORT dataa (581:581:581) (714:714:714)) - (PORT datab (361:361:361) (425:425:425)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (195:195:195) (193:193:193)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (913:913:913) (917:917:917)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (909:909:909) (914:914:914)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|key_row\~2) - (DELAY - (ABSOLUTE - (PORT datab (749:749:749) (881:881:881)) - (PORT datac (902:902:902) (1053:1053:1053)) - (PORT datad (669:669:669) (791:791:791)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~68) - (DELAY - (ABSOLUTE - (PORT dataa (121:121:121) (152:152:152)) - (PORT datab (639:639:639) (743:743:743)) - (PORT datac (660:660:660) (773:773:773)) - (PORT datad (91:91:91) (108:108:108)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (166:166:166) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~69) - (DELAY - (ABSOLUTE - (PORT dataa (620:620:620) (721:721:721)) - (PORT datab (1854:1854:1854) (2144:2144:2144)) - (PORT datac (639:639:639) (741:741:741)) - (PORT datad (285:285:285) (326:326:326)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (583:583:583) (669:669:669)) - (PORT clk (1089:1089:1089) (1106:1106:1106)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2271:2271:2271) (2633:2633:2633)) - (PORT d[1] (973:973:973) (1149:1149:1149)) - (PORT d[2] (959:959:959) (1102:1102:1102)) - (PORT d[3] (1046:1046:1046) (1227:1227:1227)) - (PORT d[4] (1245:1245:1245) (1443:1443:1443)) - (PORT d[5] (784:784:784) (927:927:927)) - (PORT d[6] (857:857:857) (998:998:998)) - (PORT d[7] (1954:1954:1954) (2213:2213:2213)) - (PORT d[8] (2109:2109:2109) (2446:2446:2446)) - (PORT d[9] (838:838:838) (972:972:972)) - (PORT d[10] (1853:1853:1853) (2129:2129:2129)) - (PORT d[11] (1194:1194:1194) (1380:1380:1380)) - (PORT d[12] (992:992:992) (1139:1139:1139)) - (PORT clk (1087:1087:1087) (1104:1104:1104)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1463:1463:1463) (1618:1618:1618)) - (PORT clk (1087:1087:1087) (1104:1104:1104)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1089:1089:1089) (1106:1106:1106)) - (PORT d[0] (1670:1670:1670) (1837:1837:1837)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1090:1090:1090) (1107:1107:1107)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1090:1090:1090) (1107:1107:1107)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1090:1090:1090) (1107:1107:1107)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1090:1090:1090) (1107:1107:1107)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1069:1069:1069) (1085:1085:1085)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (609:609:609) (617:617:617)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (610:610:610) (618:618:618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (610:610:610) (618:618:618)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (610:610:610) (618:618:618)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (364:364:364) (418:418:418)) - (PORT clk (1092:1092:1092) (1110:1110:1110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1714:1714:1714) (1988:1988:1988)) - (PORT d[1] (791:791:791) (936:936:936)) - (PORT d[2] (1150:1150:1150) (1318:1318:1318)) - (PORT d[3] (1214:1214:1214) (1418:1418:1418)) - (PORT d[4] (898:898:898) (1045:1045:1045)) - (PORT d[5] (787:787:787) (936:936:936)) - (PORT d[6] (673:673:673) (784:784:784)) - (PORT d[7] (1969:1969:1969) (2223:2223:2223)) - (PORT d[8] (1446:1446:1446) (1694:1694:1694)) - (PORT d[9] (2000:2000:2000) (2303:2303:2303)) - (PORT d[10] (1670:1670:1670) (1918:1918:1918)) - (PORT d[11] (977:977:977) (1132:1132:1132)) - (PORT d[12] (803:803:803) (924:924:924)) - (PORT clk (1090:1090:1090) (1108:1108:1108)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1087:1087:1087) (1186:1186:1186)) - (PORT clk (1090:1090:1090) (1108:1108:1108)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1092:1092:1092) (1110:1110:1110)) - (PORT d[0] (1674:1674:1674) (1813:1813:1813)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1093:1093:1093) (1111:1111:1111)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1093:1093:1093) (1111:1111:1111)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1093:1093:1093) (1111:1111:1111)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1093:1093:1093) (1111:1111:1111)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1072:1072:1072) (1089:1089:1089)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (612:612:612) (621:621:621)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (613:613:613) (622:622:622)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (613:613:613) (622:622:622)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (613:613:613) (622:622:622)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (556:556:556) (636:636:636)) - (PORT clk (1091:1091:1091) (1108:1108:1108)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1698:1698:1698) (1965:1965:1965)) - (PORT d[1] (791:791:791) (935:935:935)) - (PORT d[2] (940:940:940) (1098:1098:1098)) - (PORT d[3] (839:839:839) (978:978:978)) - (PORT d[4] (1094:1094:1094) (1277:1277:1277)) - (PORT d[5] (937:937:937) (1106:1106:1106)) - (PORT d[6] (760:760:760) (866:866:866)) - (PORT d[7] (824:824:824) (946:946:946)) - (PORT d[8] (1251:1251:1251) (1469:1469:1469)) - (PORT d[9] (2197:2197:2197) (2532:2532:2532)) - (PORT d[10] (1497:1497:1497) (1720:1720:1720)) - (PORT d[11] (1017:1017:1017) (1179:1179:1179)) - (PORT d[12] (1136:1136:1136) (1310:1310:1310)) - (PORT clk (1089:1089:1089) (1106:1106:1106)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (919:919:919) (997:997:997)) - (PORT clk (1089:1089:1089) (1106:1106:1106)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1091:1091:1091) (1108:1108:1108)) - (PORT d[0] (1219:1219:1219) (1309:1309:1309)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1092:1092:1092) (1109:1109:1109)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1092:1092:1092) (1109:1109:1109)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1092:1092:1092) (1109:1109:1109)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1092:1092:1092) (1109:1109:1109)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1071:1071:1071) (1087:1087:1087)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (611:611:611) (619:619:619)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (612:612:612) (620:620:620)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (612:612:612) (620:620:620)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (612:612:612) (620:620:620)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~73) - (DELAY - (ABSOLUTE - (PORT dataa (343:343:343) (400:400:400)) - (PORT datab (718:718:718) (841:841:841)) - (PORT datac (507:507:507) (574:574:574)) - (PORT datad (630:630:630) (739:739:739)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (188:188:188) (177:177:177)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (717:717:717) (828:828:828)) - (PORT clk (1089:1089:1089) (1106:1106:1106)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2086:2086:2086) (2416:2416:2416)) - (PORT d[1] (989:989:989) (1166:1166:1166)) - (PORT d[2] (1751:1751:1751) (2006:2006:2006)) - (PORT d[3] (1216:1216:1216) (1416:1416:1416)) - (PORT d[4] (1303:1303:1303) (1522:1522:1522)) - (PORT d[5] (1396:1396:1396) (1646:1646:1646)) - (PORT d[6] (1194:1194:1194) (1381:1381:1381)) - (PORT d[7] (1595:1595:1595) (1805:1805:1805)) - (PORT d[8] (1756:1756:1756) (2044:2044:2044)) - (PORT d[9] (1448:1448:1448) (1671:1671:1671)) - (PORT d[10] (2188:2188:2188) (2512:2512:2512)) - (PORT d[11] (1010:1010:1010) (1170:1170:1170)) - (PORT d[12] (1191:1191:1191) (1366:1366:1366)) - (PORT clk (1087:1087:1087) (1104:1104:1104)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1555:1555:1555) (1720:1720:1720)) - (PORT clk (1087:1087:1087) (1104:1104:1104)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1089:1089:1089) (1106:1106:1106)) - (PORT d[0] (1507:1507:1507) (1632:1632:1632)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1090:1090:1090) (1107:1107:1107)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1090:1090:1090) (1107:1107:1107)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1090:1090:1090) (1107:1107:1107)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1090:1090:1090) (1107:1107:1107)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1069:1069:1069) (1085:1085:1085)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (609:609:609) (617:617:617)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (610:610:610) (618:618:618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (610:610:610) (618:618:618)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (610:610:610) (618:618:618)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~74) - (DELAY - (ABSOLUTE - (PORT dataa (652:652:652) (759:759:759)) - (PORT datab (522:522:522) (603:603:603)) - (PORT datac (89:89:89) (110:110:110)) - (PORT datad (825:825:825) (930:930:930)) - (IOPATH dataa combout (188:188:188) (203:203:203)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2056:2056:2056) (2379:2379:2379)) - (PORT d[1] (1524:1524:1524) (1781:1781:1781)) - (PORT d[2] (942:942:942) (1103:1103:1103)) - (PORT d[3] (1197:1197:1197) (1399:1399:1399)) - (PORT d[4] (1073:1073:1073) (1250:1250:1250)) - (PORT d[5] (783:783:783) (928:928:928)) - (PORT d[6] (636:636:636) (739:739:739)) - (PORT d[7] (818:818:818) (941:941:941)) - (PORT d[8] (1260:1260:1260) (1481:1481:1481)) - (PORT d[9] (2208:2208:2208) (2547:2547:2547)) - (PORT d[10] (1476:1476:1476) (1692:1692:1692)) - (PORT d[11] (1175:1175:1175) (1361:1361:1361)) - (PORT d[12] (1122:1122:1122) (1295:1295:1295)) - (PORT clk (1089:1089:1089) (1106:1106:1106)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1089:1089:1089) (1106:1106:1106)) - (PORT d[0] (1966:1966:1966) (2218:2218:2218)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1090:1090:1090) (1107:1107:1107)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1071:1071:1071) (1087:1087:1087)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (611:611:611) (619:619:619)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (612:612:612) (620:620:620)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (612:612:612) (620:620:620)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (612:612:612) (620:620:620)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (822:822:822) (936:936:936)) - (PORT clk (1086:1086:1086) (1104:1104:1104)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1883:1883:1883) (2185:2185:2185)) - (PORT d[1] (1343:1343:1343) (1577:1577:1577)) - (PORT d[2] (1232:1232:1232) (1425:1425:1425)) - (PORT d[3] (1027:1027:1027) (1201:1201:1201)) - (PORT d[4] (1250:1250:1250) (1450:1450:1450)) - (PORT d[5] (965:965:965) (1138:1138:1138)) - (PORT d[6] (836:836:836) (965:965:965)) - (PORT d[7] (843:843:843) (972:972:972)) - (PORT d[8] (1670:1670:1670) (1933:1933:1933)) - (PORT d[9] (1320:1320:1320) (1516:1516:1516)) - (PORT d[10] (1292:1292:1292) (1485:1485:1485)) - (PORT d[11] (1399:1399:1399) (1626:1626:1626)) - (PORT d[12] (1114:1114:1114) (1279:1279:1279)) - (PORT clk (1084:1084:1084) (1102:1102:1102)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1608:1608:1608) (1771:1771:1771)) - (PORT clk (1084:1084:1084) (1102:1102:1102)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1086:1086:1086) (1104:1104:1104)) - (PORT d[0] (2283:2283:2283) (2527:2527:2527)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1087:1087:1087) (1105:1105:1105)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1087:1087:1087) (1105:1105:1105)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1087:1087:1087) (1105:1105:1105)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1087:1087:1087) (1105:1105:1105)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1041:1041:1041) (1061:1061:1061)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1252:1252:1252) (1392:1392:1392)) - (PORT clk (1046:1046:1046) (1064:1064:1064)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2408:2408:2408) (2741:2741:2741)) - (PORT d[1] (2392:2392:2392) (2698:2698:2698)) - (PORT d[2] (2372:2372:2372) (2705:2705:2705)) - (PORT d[3] (2539:2539:2539) (2894:2894:2894)) - (PORT d[4] (2352:2352:2352) (2674:2674:2674)) - (PORT d[5] (2403:2403:2403) (2727:2727:2727)) - (PORT d[6] (2496:2496:2496) (2860:2860:2860)) - (PORT d[7] (2413:2413:2413) (2753:2753:2753)) - (PORT d[8] (2542:2542:2542) (2856:2856:2856)) - (PORT d[9] (2555:2555:2555) (2936:2936:2936)) - (PORT d[10] (2442:2442:2442) (2755:2755:2755)) - (PORT d[11] (2400:2400:2400) (2708:2708:2708)) - (PORT d[12] (2571:2571:2571) (2895:2895:2895)) - (PORT clk (1043:1043:1043) (1063:1063:1063)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1046:1046:1046) (1064:1064:1064)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1047:1047:1047) (1065:1065:1065)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1047:1047:1047) (1065:1065:1065)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1047:1047:1047) (1065:1065:1065)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1047:1047:1047) (1065:1065:1065)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~70) - (DELAY - (ABSOLUTE - (PORT dataa (472:472:472) (563:563:563)) - (PORT datab (938:938:938) (1094:1094:1094)) - (PORT datac (517:517:517) (591:591:591)) - (PORT datad (685:685:685) (776:776:776)) - (IOPATH dataa combout (188:188:188) (179:179:179)) - (IOPATH datab combout (196:196:196) (192:192:192)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2029:2029:2029) (2354:2354:2354)) - (PORT d[1] (1516:1516:1516) (1773:1773:1773)) - (PORT d[2] (872:872:872) (1012:1012:1012)) - (PORT d[3] (1178:1178:1178) (1374:1374:1374)) - (PORT d[4] (1252:1252:1252) (1447:1447:1447)) - (PORT d[5] (957:957:957) (1129:1129:1129)) - (PORT d[6] (783:783:783) (903:903:903)) - (PORT d[7] (825:825:825) (954:954:954)) - (PORT d[8] (1234:1234:1234) (1452:1452:1452)) - (PORT d[9] (1340:1340:1340) (1538:1538:1538)) - (PORT d[10] (1301:1301:1301) (1494:1494:1494)) - (PORT d[11] (1198:1198:1198) (1388:1388:1388)) - (PORT d[12] (1288:1288:1288) (1479:1479:1479)) - (PORT clk (1087:1087:1087) (1104:1104:1104)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1087:1087:1087) (1104:1104:1104)) - (PORT d[0] (2195:2195:2195) (1948:1948:1948)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1088:1088:1088) (1105:1105:1105)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1069:1069:1069) (1085:1085:1085)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (609:609:609) (617:617:617)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (610:610:610) (618:618:618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (610:610:610) (618:618:618)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (610:610:610) (618:618:618)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~71) - (DELAY - (ABSOLUTE - (PORT dataa (121:121:121) (154:154:154)) - (PORT datab (513:513:513) (583:583:583)) - (PORT datac (627:627:627) (715:715:715)) - (PORT datad (95:95:95) (113:113:113)) - (IOPATH dataa combout (188:188:188) (184:184:184)) - (IOPATH datab combout (190:190:190) (181:181:181)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (860:860:860) (991:991:991)) - (PORT clk (1101:1101:1101) (1118:1118:1118)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1412:1412:1412) (1614:1614:1614)) - (PORT d[1] (1124:1124:1124) (1322:1322:1322)) - (PORT d[2] (1114:1114:1114) (1299:1299:1299)) - (PORT d[3] (1054:1054:1054) (1236:1236:1236)) - (PORT d[4] (1594:1594:1594) (1834:1834:1834)) - (PORT d[5] (1318:1318:1318) (1541:1541:1541)) - (PORT d[6] (1175:1175:1175) (1347:1347:1347)) - (PORT d[7] (1389:1389:1389) (1610:1610:1610)) - (PORT d[8] (1374:1374:1374) (1604:1604:1604)) - (PORT d[9] (1149:1149:1149) (1321:1321:1321)) - (PORT d[10] (975:975:975) (1114:1114:1114)) - (PORT d[11] (1153:1153:1153) (1319:1319:1319)) - (PORT d[12] (1441:1441:1441) (1644:1644:1644)) - (PORT clk (1099:1099:1099) (1116:1116:1116)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1465:1465:1465) (1612:1612:1612)) - (PORT clk (1099:1099:1099) (1116:1116:1116)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1101:1101:1101) (1118:1118:1118)) - (PORT d[0] (2068:2068:2068) (1911:1911:1911)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1102:1102:1102) (1119:1119:1119)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1102:1102:1102) (1119:1119:1119)) - (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1102:1102:1102) (1119:1119:1119)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1102:1102:1102) (1119:1119:1119)) - (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1056:1056:1056) (1075:1075:1075)) - (IOPATH (posedge clk) q (164:164:164) (167:167:167)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1143:1143:1143) (1275:1275:1275)) - (PORT clk (1061:1061:1061) (1078:1078:1078)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2565:2565:2565) (2902:2902:2902)) - (PORT d[1] (2379:2379:2379) (2698:2698:2698)) - (PORT d[2] (2538:2538:2538) (2875:2875:2875)) - (PORT d[3] (2480:2480:2480) (2809:2809:2809)) - (PORT d[4] (2379:2379:2379) (2694:2694:2694)) - (PORT d[5] (2552:2552:2552) (2893:2893:2893)) - (PORT d[6] (2642:2642:2642) (3020:3020:3020)) - (PORT d[7] (2531:2531:2531) (2886:2886:2886)) - (PORT d[8] (2543:2543:2543) (2891:2891:2891)) - (PORT d[9] (2572:2572:2572) (2952:2952:2952)) - (PORT d[10] (2438:2438:2438) (2753:2753:2753)) - (PORT d[11] (2584:2584:2584) (2914:2914:2914)) - (PORT d[12] (2592:2592:2592) (2978:2978:2978)) - (PORT clk (1058:1058:1058) (1077:1077:1077)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (104:104:104)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1061:1061:1061) (1078:1078:1078)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1062:1062:1062) (1079:1079:1079)) - (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1062:1062:1062) (1079:1079:1079)) - (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1062:1062:1062) (1079:1079:1079)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1062:1062:1062) (1079:1079:1079)) - (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1057:1057:1057) (1076:1076:1076)) - (IOPATH (posedge clk) q (164:164:164) (166:166:166)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (25:25:25)) - (HOLD d (posedge clk) (90:90:90)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~72) - (DELAY - (ABSOLUTE - (PORT dataa (472:472:472) (563:563:563)) - (PORT datab (107:107:107) (136:136:136)) - (PORT datac (89:89:89) (109:109:109)) - (PORT datad (831:831:831) (945:945:945)) - (IOPATH dataa combout (188:188:188) (184:184:184)) - (IOPATH datab combout (190:190:190) (188:188:188)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~108) - (DELAY - (ABSOLUTE - (PORT dataa (852:852:852) (995:995:995)) - (PORT datab (103:103:103) (131:131:131)) - (PORT datac (904:904:904) (1055:1055:1055)) - (PORT datad (90:90:90) (107:107:107)) - (IOPATH dataa combout (172:172:172) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~95) - (DELAY - (ABSOLUTE - (PORT dataa (112:112:112) (148:148:148)) - (PORT datab (765:765:765) (879:879:879)) - (PORT datac (730:730:730) (844:844:844)) - (PORT datad (179:179:179) (205:205:205)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~96) - (DELAY - (ABSOLUTE - (PORT dataa (889:889:889) (1024:1024:1024)) - (PORT datab (761:761:761) (876:876:876)) - (PORT datac (610:610:610) (720:720:720)) - (PORT datad (161:161:161) (189:189:189)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[3\]) - (DELAY - (ABSOLUTE - (PORT dataa (544:544:544) (647:647:647)) - (PORT datab (926:926:926) (1052:1052:1052)) - (PORT datac (134:134:134) (171:171:171)) - (PORT datad (486:486:486) (557:557:557)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -49873,59 +49499,13 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[3\]) + (INSTANCE z80_\|sequencer_\|T6) (DELAY (ABSOLUTE - (PORT clk (916:916:916) (903:903:903)) + (PORT clk (907:907:907) (912:912:912)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (432:432:432) (460:460:460)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[3\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (138:138:138) (177:177:177)) - (PORT datab (356:356:356) (436:436:436)) - (PORT datad (112:112:112) (135:135:135)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[3\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (545:545:545) (629:629:629)) - (PORT datab (498:498:498) (571:571:571)) - (PORT datac (499:499:499) (573:573:573)) - (PORT datad (501:501:501) (577:577:577)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (906:906:906) (914:914:914)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (911:911:911) (895:895:895)) - (PORT ena (780:780:780) (849:849:849)) + (PORT clrn (908:908:908) (895:895:895)) + (PORT ena (617:617:617) (666:666:666)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -49937,15 +49517,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~4) + (INSTANCE z80_\|execute_\|setM1\~53) (DELAY (ABSOLUTE - (PORT dataa (829:829:829) (969:969:969)) - (PORT datab (649:649:649) (747:747:747)) - (PORT datac (667:667:667) (790:790:790)) - (PORT datad (778:778:778) (892:892:892)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) + (PORT dataa (104:104:104) (136:136:136)) + (PORT datab (449:449:449) (534:534:534)) + (PORT datac (117:117:117) (158:158:158)) + (PORT datad (98:98:98) (119:119:119)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -49953,15 +49533,245 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_apin_mux\~2) + (INSTANCE z80_\|execute_\|setM1\~54) (DELAY (ABSOLUTE - (PORT dataa (505:505:505) (598:598:598)) - (PORT datab (115:115:115) (144:144:144)) - (PORT datac (488:488:488) (553:553:553)) + (PORT dataa (302:302:302) (354:354:354)) + (PORT datab (459:459:459) (531:531:531)) + (PORT datac (488:488:488) (572:572:572)) + (PORT datad (291:291:291) (336:336:336)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|DFFE_M1_ff\~0) + (DELAY + (ABSOLUTE + (PORT datab (649:649:649) (769:769:769)) + (PORT datad (511:511:511) (623:623:623)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_M1_ff) + (DELAY + (ABSOLUTE + (PORT clk (902:902:902) (907:907:907)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (903:903:903) (890:890:890)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|resets_\|x1\~0) + (DELAY + (ABSOLUTE + (PORT datad (103:103:103) (120:120:120)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|fpga_reset) + (DELAY + (ABSOLUTE + (PORT clk (919:919:919) (927:927:927)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE z80_\|fpga_reset\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (327:327:327) (359:359:359)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|resets_\|x1) + (DELAY + (ABSOLUTE + (PORT clk (930:930:930) (915:915:915)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (921:921:921) (907:907:907)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|resets_\|x3) + (DELAY + (ABSOLUTE + (PORT datab (1169:1169:1169) (1336:1336:1336)) + (PORT datac (129:129:129) (170:170:170)) + (PORT datad (1368:1368:1368) (1532:1532:1532)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_12) + (DELAY + (ABSOLUTE + (PORT clk (919:919:919) (926:926:926)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (921:921:921) (907:907:907)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_10\~0) + (DELAY + (ABSOLUTE + (PORT datad (969:969:969) (1116:1116:1116)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_10) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (898:898:898)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_9\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (122:122:122) (161:161:161)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_9) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (898:898:898)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|resets_\|DFFE_intr_ff3) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (898:898:898)) + (PORT asdata (299:299:299) (340:340:340)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|resets_\|clrpc_int\~0) + (DELAY + (ABSOLUTE + (PORT dataa (638:638:638) (743:743:743)) + (PORT datab (785:785:785) (903:903:903)) + (PORT datad (708:708:708) (840:840:840)) + (IOPATH dataa combout (181:181:181) (193:193:193)) + (IOPATH datab combout (191:191:191) (188:188:188)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|resets_\|clrpc_int) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (898:898:898)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (903:903:903) (890:890:890)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|resets_\|clrpc\~0) + (DELAY + (ABSOLUTE + (PORT dataa (136:136:136) (188:188:188)) + (PORT datab (135:135:135) (184:184:184)) + (PORT datad (119:119:119) (156:156:156)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[0\]) + (DELAY + (ABSOLUTE + (PORT datab (517:517:517) (604:604:604)) + (PORT datad (321:321:321) (370:370:370)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) @@ -49970,11 +49780,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[0\]\~0) (DELAY (ABSOLUTE - (PORT dataa (757:757:757) (876:876:876)) - (PORT datab (339:339:339) (406:406:406)) - (PORT datad (94:94:94) (113:113:113)) - (IOPATH dataa combout (172:172:172) (165:165:165)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT dataa (317:317:317) (365:365:365)) + (PORT datab (693:693:693) (792:792:792)) + (PORT datad (269:269:269) (309:309:309)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (158:158:158)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -49984,11 +49794,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[0\]) (DELAY (ABSOLUTE - (PORT clk (917:917:917) (905:905:905)) + (PORT clk (919:919:919) (904:904:904)) (PORT d (37:37:37) (50:50:50)) - (PORT asdata (306:306:306) (344:344:344)) - (PORT sload (575:575:575) (630:630:630)) - (PORT ena (419:419:419) (435:435:435)) + (PORT asdata (314:314:314) (358:358:358)) + (PORT sload (985:985:985) (1102:1102:1102)) + (PORT ena (911:911:911) (988:988:988)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -50001,12 +49811,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~59) + (INSTANCE D\[0\]\~47) (DELAY (ABSOLUTE - (PORT dataa (476:476:476) (559:559:559)) - (PORT datab (639:639:639) (743:743:743)) - (PORT datac (94:94:94) (117:117:117)) + (PORT dataa (639:639:639) (749:749:749)) + (PORT datab (583:583:583) (666:666:666)) + (PORT datac (93:93:93) (118:118:118)) (IOPATH dataa combout (188:188:188) (184:184:184)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -50015,88 +49825,28 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~60) + (INSTANCE D\[0\]\~48) (DELAY (ABSOLUTE - (PORT dataa (504:504:504) (597:597:597)) - (PORT datab (337:337:337) (405:405:405)) - (PORT datac (901:901:901) (1028:1028:1028)) - (PORT datad (168:168:168) (197:197:197)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~61) - (DELAY - (ABSOLUTE - (PORT dataa (778:778:778) (898:898:898)) - (PORT datac (455:455:455) (518:518:518)) - (PORT datad (103:103:103) (120:120:120)) - (IOPATH dataa combout (186:186:186) (175:175:175)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~62) - (DELAY - (ABSOLUTE - (PORT dataa (781:781:781) (899:899:899)) - (PORT datab (539:539:539) (634:634:634)) - (PORT datac (551:551:551) (659:659:659)) - (PORT datad (90:90:90) (106:106:106)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~63) - (DELAY - (ABSOLUTE - (PORT dataa (191:191:191) (238:238:238)) - (PORT datac (93:93:93) (116:116:116)) - (PORT datad (94:94:94) (114:114:114)) - (IOPATH dataa combout (186:186:186) (175:175:175)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~64) - (DELAY - (ABSOLUTE - (PORT dataa (219:219:219) (286:286:286)) - (PORT datab (125:125:125) (156:156:156)) - (PORT datac (613:613:613) (702:702:702)) - (PORT datad (91:91:91) (109:109:109)) + (PORT dataa (725:725:725) (864:864:864)) + (PORT datab (710:710:710) (807:807:807)) + (PORT datac (738:738:738) (840:840:840)) + (PORT datad (169:169:169) (198:198:198)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~75) + (INSTANCE D\[1\]\~49) (DELAY (ABSOLUTE - (PORT dataa (113:113:113) (148:148:148)) - (PORT datac (730:730:730) (844:844:844)) - (PORT datad (105:105:105) (123:123:123)) + (PORT dataa (196:196:196) (234:234:234)) + (PORT datac (463:463:463) (535:535:535)) + (PORT datad (96:96:96) (116:116:116)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -50105,13 +49855,43 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~76) + (INSTANCE D\[1\]\~50) (DELAY (ABSOLUTE - (PORT dataa (617:617:617) (736:736:736)) - (PORT datab (634:634:634) (729:729:729)) - (PORT datac (838:838:838) (949:949:949)) - (PORT datad (167:167:167) (195:195:195)) + (PORT dataa (478:478:478) (562:562:562)) + (PORT datab (517:517:517) (608:608:608)) + (PORT datac (851:851:851) (964:964:964)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (732:732:732) (863:863:863)) + (PORT datac (587:587:587) (682:682:682)) + (PORT datad (97:97:97) (117:117:117)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~52) + (DELAY + (ABSOLUTE + (PORT dataa (619:619:619) (728:728:728)) + (PORT datab (601:601:601) (693:693:693)) + (PORT datac (607:607:607) (697:697:697)) + (PORT datad (164:164:164) (192:192:192)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (125:125:125)) @@ -50121,12 +49901,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~82) + (INSTANCE D\[3\]\~58) (DELAY (ABSOLUTE - (PORT dataa (479:479:479) (563:563:563)) - (PORT datab (877:877:877) (1024:1024:1024)) - (PORT datad (96:96:96) (115:115:115)) + (PORT dataa (640:640:640) (749:749:749)) + (PORT datab (943:943:943) (1084:1084:1084)) + (PORT datad (94:94:94) (114:114:114)) (IOPATH dataa combout (172:172:172) (165:165:165)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -50135,13 +49915,43 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~83) + (INSTANCE D\[3\]\~59) (DELAY (ABSOLUTE - (PORT dataa (508:508:508) (602:602:602)) - (PORT datab (788:788:788) (926:926:926)) - (PORT datac (898:898:898) (1025:1025:1025)) - (PORT datad (168:168:168) (198:198:198)) + (PORT dataa (622:622:622) (738:738:738)) + (PORT datab (709:709:709) (806:806:806)) + (PORT datac (739:739:739) (840:840:840)) + (PORT datad (159:159:159) (186:186:186)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~65) + (DELAY + (ABSOLUTE + (PORT datab (175:175:175) (211:211:211)) + (PORT datac (461:461:461) (533:533:533)) + (PORT datad (94:94:94) (113:113:113)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~66) + (DELAY + (ABSOLUTE + (PORT dataa (478:478:478) (562:562:562)) + (PORT datab (521:521:521) (617:617:617)) + (PORT datac (852:852:852) (965:965:965)) + (PORT datad (92:92:92) (110:110:110)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (120:120:120) (125:125:125)) @@ -50151,13 +49961,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~92) + (INSTANCE D\[6\]\~70) (DELAY (ABSOLUTE - (PORT datab (728:728:728) (837:837:837)) - (PORT datac (95:95:95) (118:118:118)) - (PORT datad (94:94:94) (113:113:113)) - (IOPATH datab combout (166:166:166) (176:176:176)) + (PORT dataa (616:616:616) (721:721:721)) + (PORT datac (95:95:95) (119:119:119)) + (PORT datad (94:94:94) (112:112:112)) + (IOPATH dataa combout (165:165:165) (173:173:173)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -50165,15 +49975,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~93) + (INSTANCE D\[6\]\~71) (DELAY (ABSOLUTE - (PORT dataa (505:505:505) (597:597:597)) - (PORT datab (479:479:479) (578:578:578)) - (PORT datac (901:901:901) (1028:1028:1028)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT dataa (746:746:746) (890:890:890)) + (PORT datab (602:602:602) (694:694:694)) + (PORT datac (606:606:606) (696:696:696)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -50184,11 +49994,11 @@ (INSTANCE z80_\|nM1_int\~3) (DELAY (ABSOLUTE - (PORT datab (789:789:789) (939:939:939)) - (PORT datac (1301:1301:1301) (1509:1509:1509)) - (PORT datad (288:288:288) (332:332:332)) - (IOPATH datab combout (166:166:166) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT dataa (972:972:972) (1156:1156:1156)) + (PORT datab (602:602:602) (700:700:700)) + (PORT datad (236:236:236) (290:290:290)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -50198,10 +50008,10 @@ (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_16) (DELAY (ABSOLUTE - (PORT clk (916:916:916) (923:923:923)) + (PORT clk (908:908:908) (913:913:913)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (922:922:922) (904:904:904)) - (PORT ena (689:689:689) (767:767:767)) + (PORT clrn (909:909:909) (896:896:896)) + (PORT ena (892:892:892) (980:980:980)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -50216,7 +50026,7 @@ (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_17\~feeder) (DELAY (ABSOLUTE - (PORT datad (133:133:133) (171:171:171)) + (PORT datad (367:367:367) (440:440:440)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -50226,10 +50036,10 @@ (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_17) (DELAY (ABSOLUTE - (PORT clk (927:927:927) (912:912:912)) + (PORT clk (923:923:923) (908:908:908)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (922:922:922) (904:904:904)) - (PORT ena (704:704:704) (789:789:789)) + (PORT clrn (916:916:916) (899:899:899)) + (PORT ena (757:757:757) (820:820:820)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -50244,10 +50054,10 @@ (INSTANCE z80_\|memory_ifc_\|DFFE_mreq_ff2) (DELAY (ABSOLUTE - (PORT clk (927:927:927) (912:912:912)) + (PORT clk (923:923:923) (908:908:908)) (PORT asdata (298:298:298) (340:340:340)) - (PORT clrn (922:922:922) (904:904:904)) - (PORT ena (704:704:704) (789:789:789)) + (PORT clrn (916:916:916) (899:899:899)) + (PORT ena (757:757:757) (820:820:820)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -50262,9 +50072,9 @@ (INSTANCE z80_\|memory_ifc_\|nMREQ_out\~0) (DELAY (ABSOLUTE - (PORT dataa (135:135:135) (188:188:188)) - (PORT datab (137:137:137) (187:187:187)) - (PORT datad (117:117:117) (153:153:153)) + (PORT dataa (136:136:136) (189:189:189)) + (PORT datab (135:135:135) (184:184:184)) + (PORT datad (117:117:117) (154:154:154)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) @@ -50277,9 +50087,9 @@ (INSTANCE z80_\|memory_ifc_\|nMREQ_out\~1) (DELAY (ABSOLUTE - (PORT dataa (498:498:498) (603:603:603)) - (PORT datab (105:105:105) (134:134:134)) - (PORT datad (96:96:96) (115:115:115)) + (PORT dataa (142:142:142) (197:197:197)) + (PORT datab (115:115:115) (143:143:143)) + (PORT datad (90:90:90) (108:108:108)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (190:190:190) (195:195:195)) @@ -50310,9 +50120,9 @@ (INSTANCE ula_\|i2c_loader_\|divider\[0\]) (DELAY (ABSOLUTE - (PORT clk (1140:1140:1140) (1102:1102:1102)) + (PORT clk (1141:1141:1141) (1103:1103:1103)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (906:906:906) (913:913:913)) + (PORT clrn (898:898:898) (902:902:902)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -50326,8 +50136,8 @@ (INSTANCE ula_\|i2c_loader_\|divider\[1\]\~5) (DELAY (ABSOLUTE - (PORT dataa (136:136:136) (188:188:188)) - (PORT datab (135:135:135) (186:186:186)) + (PORT dataa (140:140:140) (193:193:193)) + (PORT datab (134:134:134) (184:184:184)) (IOPATH dataa combout (186:186:186) (180:180:180)) (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datab combout (190:190:190) (181:181:181)) @@ -50341,9 +50151,9 @@ (INSTANCE ula_\|i2c_loader_\|divider\[1\]) (DELAY (ABSOLUTE - (PORT clk (1140:1140:1140) (1102:1102:1102)) + (PORT clk (1141:1141:1141) (1103:1103:1103)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (906:906:906) (913:913:913)) + (PORT clrn (898:898:898) (902:902:902)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -50357,9 +50167,9 @@ (INSTANCE ula_\|i2c_loader_\|divider\[2\]\~7) (DELAY (ABSOLUTE - (PORT dataa (135:135:135) (187:187:187)) - (IOPATH dataa combout (165:165:165) (173:173:173)) - (IOPATH dataa cout (226:226:226) (171:171:171)) + (PORT datab (134:134:134) (183:183:183)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) (IOPATH cin cout (34:34:34) (34:34:34)) @@ -50371,9 +50181,9 @@ (INSTANCE ula_\|i2c_loader_\|divider\[2\]) (DELAY (ABSOLUTE - (PORT clk (1140:1140:1140) (1102:1102:1102)) + (PORT clk (1141:1141:1141) (1103:1103:1103)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (906:906:906) (913:913:913)) + (PORT clrn (898:898:898) (902:902:902)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -50401,66 +50211,9 @@ (INSTANCE ula_\|i2c_loader_\|divider\[3\]) (DELAY (ABSOLUTE - (PORT clk (1140:1140:1140) (1102:1102:1102)) + (PORT clk (1141:1141:1141) (1103:1103:1103)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (906:906:906) (913:913:913)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|divider\[4\]\~11) - (DELAY - (ABSOLUTE - (PORT datab (134:134:134) (184:184:184)) - (IOPATH datab combout (166:166:166) (176:176:176)) - (IOPATH datab cout (227:227:227) (175:175:175)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|divider\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1140:1140:1140) (1102:1102:1102)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (906:906:906) (913:913:913)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|divider\[5\]\~13) - (DELAY - (ABSOLUTE - (PORT datad (122:122:122) (161:161:161)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|divider\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1140:1140:1140) (1102:1102:1102)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (906:906:906) (913:913:913)) + (PORT clrn (898:898:898) (902:902:902)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -50474,10 +50227,10 @@ (INSTANCE ula_\|i2c_loader_\|WideAnd0\~0) (DELAY (ABSOLUTE - (PORT dataa (137:137:137) (190:190:190)) - (PORT datab (137:137:137) (188:188:188)) + (PORT dataa (137:137:137) (191:191:191)) + (PORT datab (136:136:136) (186:186:186)) (PORT datac (121:121:121) (164:164:164)) - (PORT datad (123:123:123) (162:162:162)) + (PORT datad (122:122:122) (162:162:162)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (125:125:125)) @@ -50487,14 +50240,71 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|WideAnd0) + (INSTANCE ula_\|i2c_loader_\|divider\[4\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (135:135:135) (187:187:187)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|divider\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1141:1141:1141) (1103:1103:1103)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (898:898:898) (902:902:902)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|divider\[5\]\~13) (DELAY (ABSOLUTE (PORT datab (135:135:135) (185:185:185)) - (PORT datac (91:91:91) (113:113:113)) - (PORT datad (122:122:122) (161:161:161)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datab combout (188:188:188) (193:193:193)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|divider\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1141:1141:1141) (1103:1103:1103)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (898:898:898) (902:902:902)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|WideAnd0) + (DELAY + (ABSOLUTE + (PORT dataa (106:106:106) (138:138:138)) + (PORT datac (123:123:123) (167:167:167)) + (PORT datad (125:125:125) (165:165:165)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -50506,8 +50316,8 @@ (ABSOLUTE (PORT clk (911:911:911) (916:916:916)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (909:909:909) (915:915:915)) - (PORT ena (810:810:810) (754:754:754)) + (PORT clrn (900:900:900) (904:904:904)) + (PORT ena (838:838:838) (773:773:773)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -50522,7 +50332,7 @@ (INSTANCE ula_\|i2c_loader_\|phase\~0) (DELAY (ABSOLUTE - (PORT datad (132:132:132) (171:171:171)) + (PORT datad (151:151:151) (194:194:194)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -50535,8 +50345,8 @@ (ABSOLUTE (PORT clk (911:911:911) (916:916:916)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (909:909:909) (915:915:915)) - (PORT ena (810:810:810) (754:754:754)) + (PORT clrn (900:900:900) (904:904:904)) + (PORT ena (838:838:838) (773:773:773)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -50551,8 +50361,8 @@ (INSTANCE ula_\|i2c_loader_\|phase\~1) (DELAY (ABSOLUTE - (PORT datab (183:183:183) (249:249:249)) - (PORT datad (135:135:135) (174:174:174)) + (PORT datab (151:151:151) (203:203:203)) + (PORT datad (150:150:150) (194:194:194)) (IOPATH datab combout (166:166:166) (176:176:176)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -50566,8 +50376,8 @@ (ABSOLUTE (PORT clk (911:911:911) (916:916:916)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (909:909:909) (915:915:915)) - (PORT ena (810:810:810) (754:754:754)) + (PORT clrn (900:900:900) (904:904:904)) + (PORT ena (838:838:838) (773:773:773)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -50582,20 +50392,24 @@ (INSTANCE ula_\|i2c_loader_\|nbit\~5) (DELAY (ABSOLUTE - (PORT dataa (338:338:338) (412:412:412)) - (IOPATH dataa combout (158:158:158) (157:157:157)) + (PORT datad (360:360:360) (430:430:430)) (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|thisbyte\[0\]\~8) + (INSTANCE ula_\|i2c_loader_\|state\.Idle\~0) (DELAY (ABSOLUTE - (PORT datab (166:166:166) (225:225:225)) - (IOPATH datab combout (192:192:192) (181:181:181)) - (IOPATH datab cout (227:227:227) (175:175:175)) + (PORT dataa (149:149:149) (204:204:204)) + (PORT datab (151:151:151) (203:203:203)) + (PORT datac (311:311:311) (369:369:369)) + (PORT datad (211:211:211) (259:259:259)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -50605,9 +50419,119 @@ (INSTANCE ula_\|i2c_loader_\|Mux42\~0) (DELAY (ABSOLUTE - (PORT datac (381:381:381) (465:465:465)) - (PORT datad (369:369:369) (445:445:445)) + (PORT datab (338:338:338) (409:409:409)) + (PORT datac (339:339:339) (412:412:412)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbit\~6) + (DELAY + (ABSOLUTE + (PORT datab (378:378:378) (455:455:455)) + (PORT datad (128:128:128) (172:172:172)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|nbit\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (909:909:909) (914:914:914)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (898:898:898) (902:902:902)) + (PORT ena (499:499:499) (536:536:536)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Done\~0) + (DELAY + (ABSOLUTE + (PORT dataa (139:139:139) (193:193:193)) + (PORT datab (149:149:149) (204:204:204)) + (PORT datac (451:451:451) (535:535:535)) + (PORT datad (130:130:130) (172:172:172)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Ack\~0) + (DELAY + (ABSOLUTE + (PORT dataa (175:175:175) (212:212:212)) + (PORT datab (208:208:208) (250:250:250)) + (PORT datac (180:180:180) (216:216:216)) + (PORT datad (215:215:215) (267:267:267)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Ack\~1) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (397:397:397)) + (PORT datab (329:329:329) (395:395:395)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|state\.Ack) + (DELAY + (ABSOLUTE + (PORT clk (1110:1110:1110) (1143:1143:1143)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (900:900:900) (904:904:904)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (339:339:339) (412:412:412)) + (PORT datab (314:314:314) (381:381:381)) + (PORT datac (330:330:330) (402:402:402)) + (PORT datad (139:139:139) (183:183:183)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -50617,9 +50541,9 @@ (INSTANCE ula_\|i2c_loader_\|nbyte\~4) (DELAY (ABSOLUTE - (PORT dataa (157:157:157) (214:214:214)) - (PORT datab (187:187:187) (253:253:253)) - (PORT datad (340:340:340) (406:406:406)) + (PORT dataa (406:406:406) (475:475:475)) + (PORT datab (260:260:260) (325:325:325)) + (PORT datad (235:235:235) (288:288:288)) (IOPATH dataa combout (181:181:181) (193:193:193)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) @@ -50632,8 +50556,8 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[0\]\~7) (DELAY (ABSOLUTE - (PORT datab (158:158:158) (213:213:213)) - (PORT datac (299:299:299) (354:354:354)) + (PORT datab (314:314:314) (381:381:381)) + (PORT datac (314:314:314) (377:377:377)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) ) @@ -50653,10 +50577,10 @@ (INSTANCE ula_\|i2c_loader_\|nbyte\[0\]\~1) (DELAY (ABSOLUTE - (PORT dataa (155:155:155) (212:212:212)) - (PORT datab (148:148:148) (198:198:198)) - (PORT datac (168:168:168) (228:228:228)) - (PORT datad (278:278:278) (297:297:297)) + (PORT dataa (159:159:159) (216:216:216)) + (PORT datab (160:160:160) (215:215:215)) + (PORT datac (240:240:240) (304:304:304)) + (PORT datad (371:371:371) (395:395:395)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (125:125:125)) @@ -50669,10 +50593,10 @@ (INSTANCE ula_\|i2c_loader_\|nbyte\[0\]\~2) (DELAY (ABSOLUTE - (PORT dataa (352:352:352) (429:429:429)) - (PORT datab (341:341:341) (398:398:398)) - (PORT datac (90:90:90) (112:112:112)) - (PORT datad (91:91:91) (108:108:108)) + (PORT dataa (328:328:328) (395:395:395)) + (PORT datab (212:212:212) (254:254:254)) + (PORT datac (157:157:157) (186:186:186)) + (PORT datad (91:91:91) (109:109:109)) (IOPATH dataa combout (172:172:172) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -50685,11 +50609,11 @@ (INSTANCE ula_\|i2c_loader_\|nbyte\[0\]\~3) (DELAY (ABSOLUTE - (PORT datab (445:445:445) (522:522:522)) - (PORT datac (222:222:222) (278:278:278)) - (PORT datad (91:91:91) (108:108:108)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT datab (231:231:231) (294:294:294)) + (PORT datac (330:330:330) (383:383:383)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -50701,7 +50625,7 @@ (ABSOLUTE (PORT clk (911:911:911) (916:916:916)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (909:909:909) (915:915:915)) + (PORT clrn (900:900:900) (904:904:904)) (PORT ena (422:422:422) (449:449:449)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) @@ -50714,63 +50638,66 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Stop\~0) + (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~1) (DELAY (ABSOLUTE - (PORT dataa (369:369:369) (449:449:449)) - (PORT datab (381:381:381) (459:459:459)) - (PORT datac (138:138:138) (185:185:185)) + (PORT dataa (156:156:156) (214:214:214)) + (PORT datab (161:161:161) (216:216:216)) + (PORT datac (314:314:314) (374:374:374)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datac combout (120:120:120) (125:125:125)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Stop\~1) + (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~3) (DELAY (ABSOLUTE - (PORT dataa (310:310:310) (366:366:366)) - (PORT datab (140:140:140) (177:177:177)) - (PORT datad (174:174:174) (205:205:205)) - (IOPATH dataa combout (181:181:181) (175:175:175)) + (PORT dataa (193:193:193) (231:231:231)) + (PORT datab (102:102:102) (131:131:131)) + (PORT datac (183:183:183) (219:219:219)) + (PORT datad (235:235:235) (288:288:288)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (108:108:108) (140:140:140)) + (PORT datab (215:215:215) (258:258:258)) + (PORT datac (330:330:330) (383:383:383)) + (PORT datad (220:220:220) (272:272:272)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|state\.Stop) + (INSTANCE ula_\|i2c_loader_\|nbit\[0\]) (DELAY (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) + (PORT clk (1108:1108:1108) (1143:1143:1143)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (907:907:907) (913:913:913)) + (PORT clrn (898:898:898) (902:902:902)) + (PORT ena (483:483:483) (510:510:510)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) ) (TIMINGCHECK (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Idle\~0) - (DELAY - (ABSOLUTE - (PORT dataa (159:159:159) (218:218:218)) - (PORT datab (142:142:142) (195:195:195)) - (PORT datac (127:127:127) (171:171:171)) - (PORT datad (295:295:295) (350:350:350)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) + (HOLD ena (posedge clk) (84:84:84)) ) ) (CELL @@ -50778,9 +50705,9 @@ (INSTANCE ula_\|i2c_loader_\|nbit\~0) (DELAY (ABSOLUTE - (PORT dataa (339:339:339) (413:413:413)) - (PORT datab (142:142:142) (194:194:194)) - (PORT datad (128:128:128) (170:170:170)) + (PORT dataa (468:468:468) (562:562:562)) + (PORT datab (145:145:145) (200:200:200)) + (PORT datad (126:126:126) (168:168:168)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (182:182:182) (193:193:193)) (IOPATH datac combout (190:190:190) (195:195:195)) @@ -50793,10 +50720,10 @@ (INSTANCE ula_\|i2c_loader_\|nbit\[2\]) (DELAY (ABSOLUTE - (PORT clk (908:908:908) (914:914:914)) + (PORT clk (909:909:909) (914:914:914)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (906:906:906) (913:913:913)) - (PORT ena (612:612:612) (664:664:664)) + (PORT clrn (898:898:898) (902:902:902)) + (PORT ena (499:499:499) (536:536:536)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -50808,15 +50735,122 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Done\~0) + (INSTANCE ula_\|i2c_loader_\|state\.Done\~1) (DELAY (ABSOLUTE - (PORT dataa (141:141:141) (194:194:194)) - (PORT datab (134:134:134) (185:185:185)) - (PORT datac (320:320:320) (383:383:383)) - (PORT datad (129:129:129) (172:172:172)) + (PORT dataa (138:138:138) (192:192:192)) + (PORT datab (149:149:149) (203:203:203)) + (PORT datad (129:129:129) (171:171:171)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\~27) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (417:417:417)) + (PORT datab (354:354:354) (432:432:432)) + (PORT datac (311:311:311) (369:369:369)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\~24) + (DELAY + (ABSOLUTE + (PORT datab (158:158:158) (213:213:213)) + (PORT datac (145:145:145) (194:194:194)) + (PORT datad (139:139:139) (181:181:181)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\~26) + (DELAY + (ABSOLUTE + (PORT datab (253:253:253) (318:318:318)) + (PORT datac (103:103:103) (124:124:124)) + (PORT datad (209:209:209) (258:258:258)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Data\~0) + (DELAY + (ABSOLUTE + (PORT datab (105:105:105) (134:134:134)) + (PORT datad (163:163:163) (192:192:192)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|state\.Data) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (916:916:916)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (288:288:288) (311:311:311)) + (PORT clrn (900:900:900) (904:904:904)) + (PORT sload (639:639:639) (722:722:722)) + (PORT ena (695:695:695) (648:648:648)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Done\~2) + (DELAY + (ABSOLUTE + (PORT dataa (115:115:115) (150:150:150)) + (PORT datab (158:158:158) (213:213:213)) + (PORT datac (311:311:311) (369:369:369)) + (PORT datad (130:130:130) (167:167:167)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Pause\~1) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (414:414:414)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (109:109:109) (135:135:135)) + (PORT datad (296:296:296) (352:352:352)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -50824,63 +50858,28 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Ack\~0) + (INSTANCE ula_\|i2c_loader_\|thisbyte\[0\]\~8) (DELAY (ABSOLUTE - (PORT dataa (189:189:189) (228:228:228)) - (PORT datab (187:187:187) (224:224:224)) - (PORT datac (490:490:490) (579:579:579)) - (PORT datad (167:167:167) (198:198:198)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) + (PORT datab (155:155:155) (208:208:208)) + (IOPATH datab combout (192:192:192) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Ack\~1) - (DELAY - (ABSOLUTE - (PORT dataa (106:106:106) (138:138:138)) - (PORT datab (297:297:297) (354:354:354)) - (PORT datad (232:232:232) (290:290:290)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (182:182:182) (177:177:177)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|state\.Ack) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (907:907:907) (913:913:913)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2c_loader_\|nbyte\[1\]\~5) (DELAY (ABSOLUTE - (PORT dataa (158:158:158) (214:214:214)) - (PORT datab (146:146:146) (196:196:196)) - (PORT datac (170:170:170) (230:230:230)) - (PORT datad (278:278:278) (297:297:297)) - (IOPATH dataa combout (170:170:170) (163:163:163)) + (PORT dataa (360:360:360) (432:432:432)) + (PORT datab (326:326:326) (386:386:386)) + (PORT datac (301:301:301) (353:353:353)) + (PORT datad (384:384:384) (412:412:412)) + (IOPATH dataa combout (170:170:170) (165:165:165)) (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -50890,10 +50889,10 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[0\]\~18) (DELAY (ABSOLUTE - (PORT dataa (218:218:218) (276:276:276)) - (PORT datab (304:304:304) (366:366:366)) - (PORT datac (448:448:448) (524:524:524)) - (PORT datad (159:159:159) (185:185:185)) + (PORT dataa (317:317:317) (379:379:379)) + (PORT datab (324:324:324) (386:386:386)) + (PORT datac (440:440:440) (503:503:503)) + (PORT datad (91:91:91) (109:109:109)) (IOPATH dataa combout (158:158:158) (163:163:163)) (IOPATH datab combout (160:160:160) (167:167:167)) (IOPATH datac combout (119:119:119) (125:125:125)) @@ -50906,12 +50905,12 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[0\]) (DELAY (ABSOLUTE - (PORT clk (911:911:911) (916:916:916)) + (PORT clk (1106:1106:1106) (1130:1130:1130)) (PORT d (37:37:37) (50:50:50)) - (PORT asdata (593:593:593) (659:659:659)) - (PORT clrn (909:909:909) (915:915:915)) - (PORT sload (571:571:571) (535:535:535)) - (PORT ena (408:408:408) (429:429:429)) + (PORT asdata (1058:1058:1058) (1215:1215:1215)) + (PORT clrn (900:900:900) (903:903:903)) + (PORT sload (723:723:723) (666:666:666)) + (PORT ena (421:421:421) (448:448:448)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -50928,7 +50927,7 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[1\]\~10) (DELAY (ABSOLUTE - (PORT datab (161:161:161) (217:217:217)) + (PORT datab (152:152:152) (203:203:203)) (IOPATH datab combout (166:166:166) (176:176:176)) (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -50942,12 +50941,12 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[1\]) (DELAY (ABSOLUTE - (PORT clk (911:911:911) (916:916:916)) + (PORT clk (1106:1106:1106) (1130:1130:1130)) (PORT d (37:37:37) (50:50:50)) - (PORT asdata (594:594:594) (660:660:660)) - (PORT clrn (909:909:909) (915:915:915)) - (PORT sload (571:571:571) (535:535:535)) - (PORT ena (408:408:408) (429:429:429)) + (PORT asdata (1059:1059:1059) (1215:1215:1215)) + (PORT clrn (900:900:900) (903:903:903)) + (PORT sload (723:723:723) (666:666:666)) + (PORT ena (421:421:421) (448:448:448)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -50964,9 +50963,9 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[2\]\~12) (DELAY (ABSOLUTE - (PORT datab (156:156:156) (208:208:208)) - (IOPATH datab combout (192:192:192) (177:177:177)) - (IOPATH datab cout (227:227:227) (175:175:175)) + (PORT dataa (159:159:159) (215:215:215)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) (IOPATH cin cout (34:34:34) (34:34:34)) @@ -50978,11 +50977,11 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[2\]) (DELAY (ABSOLUTE - (PORT clk (911:911:911) (916:916:916)) + (PORT clk (1106:1106:1106) (1130:1130:1130)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (909:909:909) (915:915:915)) - (PORT sload (571:571:571) (535:535:535)) - (PORT ena (408:408:408) (429:429:429)) + (PORT clrn (900:900:900) (903:903:903)) + (PORT sload (723:723:723) (666:666:666)) + (PORT ena (421:421:421) (448:448:448)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -50999,7 +50998,7 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[3\]\~14) (DELAY (ABSOLUTE - (PORT datab (165:165:165) (221:221:221)) + (PORT datab (155:155:155) (209:209:209)) (IOPATH datab combout (166:166:166) (176:176:176)) (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -51013,12 +51012,12 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[3\]) (DELAY (ABSOLUTE - (PORT clk (911:911:911) (916:916:916)) + (PORT clk (1106:1106:1106) (1130:1130:1130)) (PORT d (37:37:37) (50:50:50)) - (PORT asdata (595:595:595) (661:661:661)) - (PORT clrn (909:909:909) (915:915:915)) - (PORT sload (571:571:571) (535:535:535)) - (PORT ena (408:408:408) (429:429:429)) + (PORT asdata (1060:1060:1060) (1216:1216:1216)) + (PORT clrn (900:900:900) (903:903:903)) + (PORT sload (723:723:723) (666:666:666)) + (PORT ena (421:421:421) (448:448:448)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -51035,10 +51034,10 @@ (INSTANCE ula_\|i2c_loader_\|Equal2\~0) (DELAY (ABSOLUTE - (PORT dataa (225:225:225) (289:289:289)) - (PORT datab (163:163:163) (218:218:218)) - (PORT datac (151:151:151) (201:201:201)) - (PORT datad (154:154:154) (202:202:202)) + (PORT dataa (340:340:340) (410:410:410)) + (PORT datab (351:351:351) (419:419:419)) + (PORT datac (216:216:216) (272:272:272)) + (PORT datad (240:240:240) (302:302:302)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (124:124:124)) @@ -51046,28 +51045,12 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Pause\~0) - (DELAY - (ABSOLUTE - (PORT dataa (389:389:389) (476:476:476)) - (PORT datab (143:143:143) (196:196:196)) - (PORT datac (384:384:384) (469:469:469)) - (PORT datad (141:141:141) (185:185:185)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2c_loader_\|thisbyte\[4\]\~16) (DELAY (ABSOLUTE - (PORT dataa (170:170:170) (228:228:228)) + (PORT dataa (156:156:156) (214:214:214)) (IOPATH dataa combout (188:188:188) (193:193:193)) (IOPATH cin combout (187:187:187) (204:204:204)) ) @@ -51078,11 +51061,11 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[4\]) (DELAY (ABSOLUTE - (PORT clk (911:911:911) (916:916:916)) + (PORT clk (1106:1106:1106) (1130:1130:1130)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (909:909:909) (915:915:915)) - (PORT sload (571:571:571) (535:535:535)) - (PORT ena (408:408:408) (429:429:429)) + (PORT clrn (900:900:900) (903:903:903)) + (PORT sload (723:723:723) (666:666:666)) + (PORT ena (421:421:421) (448:448:448)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -51096,13 +51079,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Pause\~1) + (INSTANCE ula_\|i2c_loader_\|Equal2\~1) (DELAY (ABSOLUTE - (PORT datab (329:329:329) (385:385:385)) - (PORT datac (170:170:170) (203:203:203)) - (PORT datad (353:353:353) (421:421:421)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (PORT datac (93:93:93) (115:115:115)) + (PORT datad (218:218:218) (270:270:270)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -51110,16 +51091,16 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Done\~2) + (INSTANCE ula_\|i2c_loader_\|state\.Pause\~0) (DELAY (ABSOLUTE - (PORT dataa (117:117:117) (149:149:149)) - (PORT datab (155:155:155) (209:209:209)) - (PORT datac (127:127:127) (171:171:171)) - (PORT datad (250:250:250) (281:281:281)) + (PORT dataa (150:150:150) (204:204:204)) + (PORT datab (207:207:207) (249:249:249)) + (PORT datac (313:313:313) (373:373:373)) + (PORT datad (275:275:275) (316:316:316)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -51129,27 +51110,11 @@ (INSTANCE ula_\|i2c_loader_\|state\.Pause\~2) (DELAY (ABSOLUTE - (PORT dataa (175:175:175) (212:212:212)) - (PORT datab (142:142:142) (181:181:181)) - (PORT datac (144:144:144) (194:194:194)) - (PORT datad (222:222:222) (275:275:275)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Pause\~3) - (DELAY - (ABSOLUTE - (PORT dataa (176:176:176) (218:218:218)) - (PORT datab (310:310:310) (366:366:366)) - (PORT datad (91:91:91) (107:107:107)) - (IOPATH dataa combout (166:166:166) (159:159:159)) - (IOPATH datab combout (167:167:167) (156:156:156)) + (PORT dataa (105:105:105) (137:137:137)) + (PORT datab (341:341:341) (405:405:405)) + (PORT datad (172:172:172) (203:203:203)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (182:182:182) (177:177:177)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -51160,9 +51125,9 @@ (INSTANCE ula_\|i2c_loader_\|state\.Pause) (DELAY (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) + (PORT clk (911:911:911) (916:916:916)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (907:907:907) (913:913:913)) + (PORT clrn (900:900:900) (904:904:904)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -51176,9 +51141,9 @@ (INSTANCE ula_\|i2c_loader_\|state\~25) (DELAY (ABSOLUTE - (PORT dataa (142:142:142) (196:196:196)) - (PORT datab (144:144:144) (183:183:183)) - (PORT datad (219:219:219) (272:272:272)) + (PORT dataa (311:311:311) (372:372:372)) + (PORT datab (299:299:299) (347:347:347)) + (PORT datad (142:142:142) (185:185:185)) (IOPATH dataa combout (158:158:158) (163:163:163)) (IOPATH datab combout (160:160:160) (176:176:176)) (IOPATH datac combout (190:190:190) (195:195:195)) @@ -51191,10 +51156,10 @@ (INSTANCE ula_\|i2c_loader_\|state\.Start) (DELAY (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) + (PORT clk (911:911:911) (916:916:916)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (907:907:907) (913:913:913)) - (PORT ena (654:654:654) (617:617:617)) + (PORT clrn (900:900:900) (904:904:904)) + (PORT ena (838:838:838) (773:773:773)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -51209,8 +51174,8 @@ (INSTANCE ula_\|i2c_loader_\|nbyte\~0) (DELAY (ABSOLUTE - (PORT datab (181:181:181) (247:247:247)) - (PORT datad (333:333:333) (398:398:398)) + (PORT datab (254:254:254) (318:318:318)) + (PORT datad (239:239:239) (292:292:292)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -51224,7 +51189,7 @@ (ABSOLUTE (PORT clk (911:911:911) (916:916:916)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (909:909:909) (915:915:915)) + (PORT clrn (900:900:900) (904:904:904)) (PORT ena (422:422:422) (449:449:449)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) @@ -51237,138 +51202,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~1) + (INSTANCE ula_\|i2c_loader_\|state\.Stop\~0) (DELAY (ABSOLUTE - (PORT dataa (369:369:369) (449:449:449)) - (PORT datac (366:366:366) (437:437:437)) - (PORT datad (233:233:233) (292:292:292)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (549:549:549) (642:642:642)) - (PORT datab (260:260:260) (324:324:324)) - (PORT datac (142:142:142) (188:188:188)) - (PORT datad (359:359:359) (431:431:431)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (188:188:188) (177:177:177)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (105:105:105) (137:137:137)) - (PORT datab (103:103:103) (131:131:131)) - (PORT datac (314:314:314) (372:372:372)) - (PORT datad (167:167:167) (197:197:197)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (178:178:178) (221:221:221)) - (PORT datab (139:139:139) (177:177:177)) - (PORT datac (292:292:292) (341:341:341)) - (PORT datad (226:226:226) (279:279:279)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|nbit\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1106:1106:1106) (1137:1137:1137)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (906:906:906) (913:913:913)) - (PORT ena (595:595:595) (634:634:634)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\~6) - (DELAY - (ABSOLUTE - (PORT dataa (335:335:335) (408:408:408)) - (PORT datad (131:131:131) (174:174:174)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|nbit\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (914:914:914)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (906:906:906) (913:913:913)) - (PORT ena (612:612:612) (664:664:664)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Done\~1) - (DELAY - (ABSOLUTE - (PORT dataa (140:140:140) (196:196:196)) - (PORT datab (137:137:137) (187:187:187)) - (PORT datad (132:132:132) (175:175:175)) - (IOPATH dataa combout (158:158:158) (157:157:157)) + (PORT datab (158:158:158) (213:213:213)) + (PORT datac (145:145:145) (195:195:195)) + (PORT datad (139:139:139) (182:182:182)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\~27) - (DELAY - (ABSOLUTE - (PORT dataa (382:382:382) (471:471:471)) - (PORT datac (381:381:381) (465:465:465)) - (PORT datad (249:249:249) (280:280:280)) - (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -51376,40 +51216,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\~24) + (INSTANCE ula_\|i2c_loader_\|state\.Stop\~1) (DELAY (ABSOLUTE - (PORT dataa (369:369:369) (450:450:450)) - (PORT datab (382:382:382) (459:459:459)) - (PORT datac (135:135:135) (181:181:181)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\~26) - (DELAY - (ABSOLUTE - (PORT dataa (387:387:387) (475:475:475)) - (PORT datac (384:384:384) (468:468:468)) - (PORT datad (180:180:180) (208:208:208)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Data\~0) - (DELAY - (ABSOLUTE - (PORT dataa (107:107:107) (139:139:139)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (170:170:170) (163:163:163)) + (PORT dataa (105:105:105) (136:136:136)) + (PORT datab (345:345:345) (405:405:405)) + (PORT datad (199:199:199) (230:230:230)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (167:167:167) (156:156:156)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -51417,24 +51231,18 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|state\.Data) + (INSTANCE ula_\|i2c_loader_\|state\.Stop) (DELAY (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) + (PORT clk (1110:1110:1110) (1143:1143:1143)) (PORT d (37:37:37) (50:50:50)) - (PORT asdata (305:305:305) (334:334:334)) - (PORT clrn (907:907:907) (913:913:913)) - (PORT sload (461:461:461) (529:529:529)) - (PORT ena (654:654:654) (617:617:617)) + (PORT clrn (900:900:900) (904:904:904)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) ) (TIMINGCHECK (HOLD d (posedge clk) (84:84:84)) - (HOLD sload (posedge clk) (84:84:84)) - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) ) ) (CELL @@ -51442,11 +51250,11 @@ (INSTANCE ula_\|i2c_loader_\|scl_out\~0) (DELAY (ABSOLUTE - (PORT datab (158:158:158) (212:212:212)) - (PORT datac (311:311:311) (375:375:375)) - (PORT datad (126:126:126) (169:169:169)) + (PORT dataa (217:217:217) (278:278:278)) + (PORT datab (159:159:159) (214:214:214)) + (PORT datad (297:297:297) (354:354:354)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -51458,8 +51266,8 @@ (ABSOLUTE (PORT clk (911:911:911) (916:916:916)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (909:909:909) (915:915:915)) - (PORT ena (810:810:810) (754:754:754)) + (PORT clrn (900:900:900) (904:904:904)) + (PORT ena (695:695:695) (648:648:648)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -51474,10 +51282,10 @@ (INSTANCE ula_\|i2c_loader_\|scl_out\~1) (DELAY (ABSOLUTE - (PORT dataa (351:351:351) (427:427:427)) - (PORT datab (184:184:184) (250:250:250)) - (PORT datac (141:141:141) (190:190:190)) - (PORT datad (117:117:117) (155:155:155)) + (PORT dataa (342:342:342) (414:414:414)) + (PORT datab (349:349:349) (427:427:427)) + (PORT datac (315:315:315) (379:379:379)) + (PORT datad (117:117:117) (154:154:154)) (IOPATH dataa combout (165:165:165) (173:173:173)) (IOPATH datab combout (196:196:196) (192:192:192)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -51490,12 +51298,12 @@ (INSTANCE ula_\|i2c_loader_\|scl_out\~2) (DELAY (ABSOLUTE - (PORT dataa (345:345:345) (403:403:403)) + (PORT dataa (117:117:117) (154:154:154)) (PORT datab (103:103:103) (132:132:132)) - (PORT datad (334:334:334) (399:399:399)) + (PORT datac (327:327:327) (389:389:389)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (176:176:176)) - (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH datab combout (188:188:188) (193:193:193)) + (IOPATH datac combout (120:120:120) (125:125:125)) ) ) ) @@ -51505,9 +51313,9 @@ (DELAY (ABSOLUTE (PORT clk (868:868:868) (887:887:887)) - (PORT d (555:555:555) (509:509:509)) - (PORT aload (1017:1017:1017) (1062:1062:1062)) - (PORT ena (487:487:487) (454:454:454)) + (PORT d (557:557:557) (510:510:510)) + (PORT aload (1008:1008:1008) (1051:1051:1051)) + (PORT ena (365:365:365) (351:351:351)) (IOPATH (posedge clk) q (345:345:345) (339:339:339)) (IOPATH (posedge aload) q (286:286:286) (280:280:280)) ) @@ -51526,8 +51334,8 @@ (ABSOLUTE (PORT clk (911:911:911) (916:916:916)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (909:909:909) (915:915:915)) - (PORT ena (810:810:810) (754:754:754)) + (PORT clrn (900:900:900) (904:904:904)) + (PORT ena (695:695:695) (648:648:648)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -51542,10 +51350,10 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\~4) (DELAY (ABSOLUTE - (PORT datac (473:473:473) (559:559:559)) - (PORT datad (326:326:326) (387:387:387)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) + (PORT dataa (258:258:258) (320:320:320)) + (PORT datac (340:340:340) (411:411:411)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (120:120:120) (125:125:125)) ) ) ) @@ -51554,10 +51362,10 @@ (INSTANCE ula_\|i2c_loader_\|Mux35\~0) (DELAY (ABSOLUTE - (PORT dataa (234:234:234) (295:295:295)) - (PORT datab (239:239:239) (296:296:296)) - (PORT datac (205:205:205) (252:252:252)) - (PORT datad (209:209:209) (257:257:257)) + (PORT dataa (339:339:339) (410:410:410)) + (PORT datab (348:348:348) (415:415:415)) + (PORT datac (215:215:215) (271:271:271)) + (PORT datad (239:239:239) (301:301:301)) (IOPATH dataa combout (166:166:166) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (125:125:125)) @@ -51570,26 +51378,10 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\~13) (DELAY (ABSOLUTE - (PORT dataa (170:170:170) (230:230:230)) - (PORT datab (162:162:162) (218:218:218)) - (PORT datac (153:153:153) (206:206:206)) - (PORT datad (143:143:143) (186:186:186)) - (IOPATH dataa combout (192:192:192) (184:184:184)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~14) - (DELAY - (ABSOLUTE - (PORT datac (153:153:153) (206:206:206)) - (PORT datad (143:143:143) (185:185:185)) + (PORT dataa (160:160:160) (219:219:219)) + (PORT datac (145:145:145) (194:194:194)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) @@ -51598,11 +51390,11 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\~15) (DELAY (ABSOLUTE - (PORT dataa (107:107:107) (139:139:139)) - (PORT datab (167:167:167) (225:225:225)) - (PORT datac (151:151:151) (200:200:200)) - (PORT datad (105:105:105) (122:122:122)) - (IOPATH dataa combout (170:170:170) (163:163:163)) + (PORT dataa (162:162:162) (221:221:221)) + (PORT datab (154:154:154) (207:207:207)) + (PORT datac (146:146:146) (195:195:195)) + (PORT datad (146:146:146) (191:191:191)) + (IOPATH dataa combout (172:172:172) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -51611,12 +51403,92 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~24) + (INSTANCE ula_\|i2c_loader_\|shiftreg\~16) (DELAY (ABSOLUTE - (PORT datab (238:238:238) (295:295:295)) - (PORT datac (474:474:474) (560:560:560)) - (PORT datad (220:220:220) (268:268:268)) + (PORT dataa (110:110:110) (142:142:142)) + (PORT datab (159:159:159) (214:214:214)) + (PORT datac (90:90:90) (112:112:112)) + (PORT datad (143:143:143) (186:186:186)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~17) + (DELAY + (ABSOLUTE + (PORT dataa (317:317:317) (384:384:384)) + (PORT datab (260:260:260) (327:327:327)) + (PORT datac (216:216:216) (272:272:272)) + (PORT datad (330:330:330) (392:392:392)) + (IOPATH dataa combout (158:158:158) (173:173:173)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~18) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (137:137:137)) + (PORT datab (233:233:233) (292:292:292)) + (PORT datac (271:271:271) (311:311:311)) + (PORT datad (239:239:239) (300:300:300)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~20) + (DELAY + (ABSOLUTE + (PORT dataa (330:330:330) (396:396:396)) + (PORT datab (349:349:349) (417:417:417)) + (PORT datac (324:324:324) (386:386:386)) + (PORT datad (220:220:220) (273:273:273)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (182:182:182) (193:193:193)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~21) + (DELAY + (ABSOLUTE + (PORT dataa (285:285:285) (335:335:335)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (214:214:214) (270:270:270)) + (PORT datad (238:238:238) (300:300:300)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~23) + (DELAY + (ABSOLUTE + (PORT datab (352:352:352) (421:421:421)) + (PORT datac (338:338:338) (409:409:409)) + (PORT datad (241:241:241) (303:303:303)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -51628,10 +51500,12 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~6) (DELAY (ABSOLUTE - (PORT dataa (385:385:385) (472:472:472)) - (PORT datac (382:382:382) (467:467:467)) - (PORT datad (144:144:144) (189:189:189)) - (IOPATH dataa combout (158:158:158) (157:157:157)) + (PORT dataa (194:194:194) (232:232:232)) + (PORT datab (334:334:334) (402:402:402)) + (PORT datac (148:148:148) (194:194:194)) + (PORT datad (137:137:137) (176:176:176)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -51642,26 +51516,12 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~7) (DELAY (ABSOLUTE - (PORT dataa (164:164:164) (223:223:223)) - (PORT datab (139:139:139) (177:177:177)) - (PORT datac (90:90:90) (112:112:112)) - (PORT datad (183:183:183) (212:212:212)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~8) - (DELAY - (ABSOLUTE - (PORT datab (239:239:239) (301:301:301)) - (PORT datac (293:293:293) (342:342:342)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH datab combout (166:166:166) (167:167:167)) + (PORT dataa (107:107:107) (139:139:139)) + (PORT datab (152:152:152) (205:205:205)) + (PORT datac (434:434:434) (503:503:503)) + (PORT datad (149:149:149) (193:193:193)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -51674,9 +51534,9 @@ (ABSOLUTE (PORT clk (911:911:911) (916:916:916)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (909:909:909) (915:915:915)) - (PORT sclr (554:554:554) (649:649:649)) - (PORT ena (724:724:724) (781:781:781)) + (PORT clrn (900:900:900) (904:904:904)) + (PORT sclr (463:463:463) (558:558:558)) + (PORT ena (473:473:473) (497:497:497)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -51687,32 +51547,14 @@ (HOLD ena (posedge clk) (84:84:84)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~21) - (DELAY - (ABSOLUTE - (PORT dataa (170:170:170) (229:229:229)) - (PORT datab (164:164:164) (221:221:221)) - (PORT datac (152:152:152) (206:206:206)) - (PORT datad (143:143:143) (185:185:185)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (174:174:174)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2c_loader_\|shiftreg\~22) (DELAY (ABSOLUTE - (PORT dataa (189:189:189) (227:227:227)) - (PORT datab (194:194:194) (230:230:230)) - (PORT datac (204:204:204) (251:251:251)) - (PORT datad (221:221:221) (269:269:269)) - (IOPATH dataa combout (170:170:170) (163:163:163)) + (PORT datab (103:103:103) (131:131:131)) + (PORT datac (347:347:347) (418:418:418)) + (PORT datad (121:121:121) (159:159:159)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -51721,14 +51563,16 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~23) + (INSTANCE ula_\|i2c_loader_\|shiftreg\[6\]\~9) (DELAY (ABSOLUTE - (PORT dataa (132:132:132) (183:183:183)) - (PORT datac (477:477:477) (564:564:564)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT dataa (193:193:193) (230:230:230)) + (PORT datab (328:328:328) (395:395:395)) + (PORT datac (152:152:152) (198:198:198)) + (PORT datad (133:133:133) (173:173:173)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -51738,29 +51582,13 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[6\]\~10) (DELAY (ABSOLUTE - (PORT dataa (383:383:383) (461:461:461)) - (PORT datab (258:258:258) (321:321:321)) - (PORT datac (313:313:313) (371:371:371)) - (PORT datad (105:105:105) (123:123:123)) - (IOPATH dataa combout (188:188:188) (193:193:193)) - (IOPATH datab combout (192:192:192) (177:177:177)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[6\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (548:548:548) (641:641:641)) - (PORT datab (296:296:296) (352:352:352)) - (PORT datac (492:492:492) (580:580:580)) - (PORT datad (92:92:92) (109:109:109)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (153:153:153) (207:207:207)) + (PORT datac (434:434:434) (503:503:503)) + (PORT datad (148:148:148) (192:192:192)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -51772,8 +51600,8 @@ (ABSOLUTE (PORT clk (911:911:911) (916:916:916)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (909:909:909) (915:915:915)) - (PORT ena (629:629:629) (676:676:676)) + (PORT clrn (900:900:900) (904:904:904)) + (PORT ena (514:514:514) (555:555:555)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -51783,49 +51611,17 @@ (HOLD ena (posedge clk) (84:84:84)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~18) - (DELAY - (ABSOLUTE - (PORT dataa (172:172:172) (232:232:232)) - (PORT datab (167:167:167) (225:225:225)) - (PORT datac (151:151:151) (201:201:201)) - (PORT datad (149:149:149) (193:193:193)) - (IOPATH dataa combout (172:172:172) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2c_loader_\|shiftreg\~19) (DELAY (ABSOLUTE - (PORT dataa (235:235:235) (297:297:297)) - (PORT datab (221:221:221) (279:279:279)) - (PORT datac (159:159:159) (189:189:189)) - (PORT datad (104:104:104) (122:122:122)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~20) - (DELAY - (ABSOLUTE - (PORT dataa (133:133:133) (185:185:185)) - (PORT datac (472:472:472) (558:558:558)) - (PORT datad (93:93:93) (111:111:111)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) + (PORT dataa (106:106:106) (138:138:138)) + (PORT datab (134:134:134) (183:183:183)) + (PORT datac (339:339:339) (409:409:409)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) ) ) ) @@ -51836,74 +51632,8 @@ (ABSOLUTE (PORT clk (911:911:911) (916:916:916)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (909:909:909) (915:915:915)) - (PORT ena (629:629:629) (676:676:676)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~16) - (DELAY - (ABSOLUTE - (PORT dataa (223:223:223) (287:287:287)) - (PORT datab (162:162:162) (218:218:218)) - (PORT datac (153:153:153) (207:207:207)) - (PORT datad (151:151:151) (196:196:196)) - (IOPATH dataa combout (172:172:172) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~17) - (DELAY - (ABSOLUTE - (PORT dataa (235:235:235) (297:297:297)) - (PORT datab (237:237:237) (293:293:293)) - (PORT datac (259:259:259) (293:293:293)) - (PORT datad (181:181:181) (209:209:209)) - (IOPATH dataa combout (188:188:188) (179:179:179)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~26) - (DELAY - (ABSOLUTE - (PORT dataa (339:339:339) (413:413:413)) - (PORT datab (130:130:130) (179:179:179)) - (PORT datac (473:473:473) (559:559:559)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (911:911:911) (916:916:916)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (909:909:909) (915:915:915)) - (PORT ena (629:629:629) (676:676:676)) + (PORT clrn (900:900:900) (904:904:904)) + (PORT ena (514:514:514) (555:555:555)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -51918,12 +51648,12 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\~25) (DELAY (ABSOLUTE - (PORT dataa (105:105:105) (136:136:136)) - (PORT datab (359:359:359) (435:435:435)) - (PORT datac (323:323:323) (379:379:379)) - (PORT datad (189:189:189) (236:236:236)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (166:166:166) (158:158:158)) + (PORT dataa (259:259:259) (322:322:322)) + (PORT datab (358:358:358) (434:434:434)) + (PORT datac (164:164:164) (198:198:198)) + (PORT datad (117:117:117) (155:155:155)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (176:176:176)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -51931,13 +51661,13 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[4\]) + (INSTANCE ula_\|i2c_loader_\|shiftreg\[3\]) (DELAY (ABSOLUTE (PORT clk (911:911:911) (916:916:916)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (909:909:909) (915:915:915)) - (PORT ena (728:728:728) (796:796:796)) + (PORT clrn (900:900:900) (904:904:904)) + (PORT ena (514:514:514) (555:555:555)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -51952,9 +51682,75 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\~12) (DELAY (ABSOLUTE - (PORT dataa (286:286:286) (330:330:330)) - (PORT datab (260:260:260) (324:324:324)) - (PORT datad (191:191:191) (237:237:237)) + (PORT dataa (160:160:160) (218:218:218)) + (PORT datab (153:153:153) (205:205:205)) + (PORT datac (144:144:144) (194:194:194)) + (PORT datad (142:142:142) (185:185:185)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~14) + (DELAY + (ABSOLUTE + (PORT dataa (110:110:110) (143:143:143)) + (PORT datab (159:159:159) (215:215:215)) + (PORT datac (90:90:90) (111:111:111)) + (PORT datad (143:143:143) (187:187:187)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~24) + (DELAY + (ABSOLUTE + (PORT dataa (259:259:259) (322:322:322)) + (PORT datab (130:130:130) (178:178:178)) + (PORT datac (340:340:340) (411:411:411)) + (PORT datad (163:163:163) (192:192:192)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|shiftreg\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (911:911:911) (916:916:916)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (900:900:900) (904:904:904)) + (PORT ena (514:514:514) (555:555:555)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~11) + (DELAY + (ABSOLUTE + (PORT dataa (189:189:189) (229:229:229)) + (PORT datab (332:332:332) (400:400:400)) + (PORT datad (191:191:191) (239:239:239)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (167:167:167) (158:158:158)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -51966,11 +51762,11 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[5\]) (DELAY (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) + (PORT clk (911:911:911) (916:916:916)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (907:907:907) (913:913:913)) - (PORT sload (627:627:627) (704:704:704)) - (PORT ena (419:419:419) (435:435:435)) + (PORT clrn (900:900:900) (904:904:904)) + (PORT sload (466:466:466) (531:531:531)) + (PORT ena (418:418:418) (435:435:435)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -51984,12 +51780,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~9) + (INSTANCE ula_\|i2c_loader_\|shiftreg\~8) (DELAY (ABSOLUTE - (PORT datab (342:342:342) (418:418:418)) - (PORT datac (476:476:476) (563:563:563)) - (PORT datad (105:105:105) (123:123:123)) + (PORT datab (213:213:213) (268:268:268)) + (PORT datac (344:344:344) (415:415:415)) + (PORT datad (103:103:103) (120:120:120)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -52003,9 +51799,9 @@ (ABSOLUTE (PORT clk (911:911:911) (916:916:916)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (909:909:909) (915:915:915)) - (PORT sclr (554:554:554) (649:649:649)) - (PORT ena (629:629:629) (676:676:676)) + (PORT clrn (900:900:900) (904:904:904)) + (PORT sclr (463:463:463) (558:558:558)) + (PORT ena (514:514:514) (555:555:555)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -52021,8 +51817,8 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[7\]\~5) (DELAY (ABSOLUTE - (PORT datac (472:472:472) (558:558:558)) - (PORT datad (119:119:119) (156:156:156)) + (PORT datac (343:343:343) (415:415:415)) + (PORT datad (117:117:117) (154:154:154)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -52035,9 +51831,9 @@ (ABSOLUTE (PORT clk (911:911:911) (916:916:916)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (909:909:909) (915:915:915)) - (PORT sclr (554:554:554) (649:649:649)) - (PORT ena (724:724:724) (781:781:781)) + (PORT clrn (900:900:900) (904:904:904)) + (PORT sclr (463:463:463) (558:558:558)) + (PORT ena (473:473:473) (497:497:497)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -52053,13 +51849,13 @@ (INSTANCE ula_\|i2c_loader_\|sda_out\~0) (DELAY (ABSOLUTE - (PORT dataa (364:364:364) (440:440:440)) - (PORT datab (220:220:220) (277:277:277)) - (PORT datac (290:290:290) (344:344:344)) - (PORT datad (198:198:198) (249:249:249)) - (IOPATH dataa combout (158:158:158) (173:173:173)) - (IOPATH datab combout (160:160:160) (176:176:176)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT dataa (304:304:304) (371:371:371)) + (PORT datab (311:311:311) (377:377:377)) + (PORT datac (338:338:338) (411:411:411)) + (PORT datad (146:146:146) (191:191:191)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -52069,10 +51865,10 @@ (INSTANCE ula_\|i2c_loader_\|sda_out\~1) (DELAY (ABSOLUTE - (PORT dataa (279:279:279) (324:324:324)) - (PORT datab (180:180:180) (245:245:245)) - (PORT datac (174:174:174) (211:211:211)) - (PORT datad (279:279:279) (297:297:297)) + (PORT dataa (289:289:289) (338:338:338)) + (PORT datab (354:354:354) (432:432:432)) + (PORT datac (90:90:90) (111:111:111)) + (PORT datad (269:269:269) (285:285:285)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -52085,9 +51881,9 @@ (INSTANCE ula_\|i2c_loader_\|sda_out\~2) (DELAY (ABSOLUTE - (PORT dataa (139:139:139) (193:193:193)) - (PORT datab (181:181:181) (246:246:246)) - (PORT datac (142:142:142) (189:189:189)) + (PORT dataa (136:136:136) (190:190:190)) + (PORT datab (333:333:333) (404:404:404)) + (PORT datac (334:334:334) (406:406:406)) (PORT datad (95:95:95) (114:114:114)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (168:168:168) (167:167:167)) @@ -52101,13 +51897,13 @@ (INSTANCE ula_\|i2c_loader_\|sda_out\~3) (DELAY (ABSOLUTE - (PORT dataa (139:139:139) (194:194:194)) - (PORT datab (178:178:178) (243:243:243)) - (PORT datac (143:143:143) (190:190:190)) + (PORT dataa (138:138:138) (192:192:192)) + (PORT datab (337:337:337) (409:409:409)) + (PORT datac (339:339:339) (412:412:412)) (PORT datad (94:94:94) (113:113:113)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (192:192:192) (177:177:177)) - (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datab combout (166:166:166) (174:174:174)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -52117,12 +51913,12 @@ (INSTANCE ula_\|i2c_loader_\|sda_out\~4) (DELAY (ABSOLUTE - (PORT dataa (353:353:353) (430:430:430)) - (PORT datab (430:430:430) (496:496:496)) - (PORT datac (91:91:91) (113:113:113)) + (PORT dataa (116:116:116) (153:153:153)) + (PORT datab (338:338:338) (405:405:405)) + (PORT datac (89:89:89) (110:110:110)) (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (172:172:172) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (169:169:169) (167:167:167)) (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -52134,9 +51930,9 @@ (DELAY (ABSOLUTE (PORT clk (871:871:871) (889:889:889)) - (PORT d (381:381:381) (356:356:356)) - (PORT aload (1028:1028:1028) (1070:1070:1070)) - (PORT ena (725:725:725) (672:672:672)) + (PORT d (383:383:383) (356:356:356)) + (PORT aload (1019:1019:1019) (1059:1059:1059)) + (PORT ena (458:458:458) (436:436:436)) (IOPATH (posedge clk) q (345:345:345) (339:339:339)) (IOPATH (posedge aload) q (286:286:286) (280:280:280)) ) @@ -52162,9 +51958,9 @@ (INSTANCE ula_\|i2s_intf_\|mclk_r\~_Duplicate_1) (DELAY (ABSOLUTE - (PORT clk (1105:1105:1105) (1134:1134:1134)) + (PORT clk (1125:1125:1125) (1158:1158:1158)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (905:905:905) (911:911:911)) + (PORT clrn (906:906:906) (909:909:909)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -52179,8 +51975,8 @@ (DELAY (ABSOLUTE (PORT clk (891:891:891) (913:913:913)) - (PORT d (1491:1491:1491) (1301:1301:1301)) - (PORT clrn (1029:1029:1029) (1076:1076:1076)) + (PORT d (728:728:728) (661:661:661)) + (PORT clrn (1020:1020:1020) (1065:1065:1065)) (IOPATH (posedge clk) q (329:329:329) (329:329:329)) (IOPATH (negedge clrn) q (395:395:395) (395:395:395)) ) @@ -52195,7 +51991,7 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~1) (DELAY (ABSOLUTE - (PORT dataa (379:379:379) (460:460:460)) + (PORT dataa (213:213:213) (277:277:277)) (IOPATH dataa cout (226:226:226) (171:171:171)) ) ) @@ -52205,9 +52001,9 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~2) (DELAY (ABSOLUTE - (PORT datab (137:137:137) (187:187:187)) - (IOPATH datab combout (167:167:167) (174:174:174)) - (IOPATH datab cout (227:227:227) (175:175:175)) + (PORT dataa (220:220:220) (278:278:278)) + (IOPATH dataa combout (166:166:166) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) (IOPATH cin cout (34:34:34) (34:34:34)) @@ -52219,8 +52015,8 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\~2) (DELAY (ABSOLUTE - (PORT dataa (120:120:120) (154:154:154)) - (PORT datac (92:92:92) (114:114:114)) + (PORT dataa (238:238:238) (289:289:289)) + (PORT datac (162:162:162) (195:195:195)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datac combout (119:119:119) (124:124:124)) ) @@ -52231,9 +52027,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[1\]) (DELAY (ABSOLUTE - (PORT clk (1105:1105:1105) (1134:1134:1134)) + (PORT clk (1131:1131:1131) (1165:1165:1165)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (905:905:905) (911:911:911)) + (PORT clrn (905:905:905) (909:909:909)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -52247,9 +52043,9 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~4) (DELAY (ABSOLUTE - (PORT dataa (207:207:207) (271:271:271)) - (IOPATH dataa combout (166:166:166) (173:173:173)) - (IOPATH dataa cout (226:226:226) (171:171:171)) + (PORT datab (204:204:204) (261:261:261)) + (IOPATH datab combout (167:167:167) (174:174:174)) + (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) (IOPATH cin cout (34:34:34) (34:34:34)) @@ -52261,8 +52057,8 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[2\]\~8) (DELAY (ABSOLUTE - (PORT datad (167:167:167) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) + (PORT datac (175:175:175) (212:212:212)) + (IOPATH datac combout (120:120:120) (125:125:125)) ) ) ) @@ -52271,9 +52067,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[2\]) (DELAY (ABSOLUTE - (PORT clk (1105:1105:1105) (1134:1134:1134)) + (PORT clk (1131:1131:1131) (1165:1165:1165)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (905:905:905) (911:911:911)) + (PORT clrn (905:905:905) (909:909:909)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -52287,7 +52083,7 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~6) (DELAY (ABSOLUTE - (PORT datab (203:203:203) (259:259:259)) + (PORT datab (203:203:203) (260:260:260)) (IOPATH datab combout (191:191:191) (181:181:181)) (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -52301,8 +52097,8 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[3\]\~7) (DELAY (ABSOLUTE - (PORT datac (174:174:174) (211:211:211)) - (IOPATH datac combout (120:120:120) (125:125:125)) + (PORT datad (283:283:283) (326:326:326)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) @@ -52311,9 +52107,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[3\]) (DELAY (ABSOLUTE - (PORT clk (1105:1105:1105) (1134:1134:1134)) + (PORT clk (1131:1131:1131) (1165:1165:1165)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (905:905:905) (911:911:911)) + (PORT clrn (905:905:905) (909:909:909)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -52327,9 +52123,9 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~8) (DELAY (ABSOLUTE - (PORT datab (135:135:135) (186:186:186)) - (IOPATH datab combout (188:188:188) (181:181:181)) - (IOPATH datab cout (227:227:227) (175:175:175)) + (PORT dataa (207:207:207) (265:265:265)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) (IOPATH cin cout (34:34:34) (34:34:34)) @@ -52341,10 +52137,10 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\~1) (DELAY (ABSOLUTE - (PORT dataa (125:125:125) (160:160:160)) - (PORT datac (90:90:90) (111:111:111)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT datac (213:213:213) (262:262:262)) + (PORT datad (162:162:162) (189:189:189)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) @@ -52353,9 +52149,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[4\]) (DELAY (ABSOLUTE - (PORT clk (1105:1105:1105) (1134:1134:1134)) + (PORT clk (1131:1131:1131) (1165:1165:1165)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (905:905:905) (911:911:911)) + (PORT clrn (905:905:905) (909:909:909)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -52369,9 +52165,9 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~10) (DELAY (ABSOLUTE - (PORT datab (136:136:136) (186:186:186)) - (IOPATH datab combout (191:191:191) (181:181:181)) - (IOPATH datab cout (227:227:227) (175:175:175)) + (PORT dataa (206:206:206) (264:264:264)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) (IOPATH cin cout (34:34:34) (34:34:34)) @@ -52383,7 +52179,7 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[5\]\~6) (DELAY (ABSOLUTE - (PORT datad (92:92:92) (109:109:109)) + (PORT datad (172:172:172) (204:204:204)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -52393,9 +52189,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[5\]) (DELAY (ABSOLUTE - (PORT clk (1105:1105:1105) (1134:1134:1134)) + (PORT clk (1131:1131:1131) (1165:1165:1165)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (905:905:905) (911:911:911)) + (PORT clrn (905:905:905) (909:909:909)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -52409,12 +52205,12 @@ (INSTANCE ula_\|i2s_intf_\|Equal0\~1) (DELAY (ABSOLUTE - (PORT dataa (210:210:210) (273:273:273)) - (PORT datab (137:137:137) (187:187:187)) - (PORT datac (191:191:191) (240:240:240)) - (PORT datad (124:124:124) (164:164:164)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (PORT dataa (208:208:208) (266:266:266)) + (PORT datab (205:205:205) (263:263:263)) + (PORT datac (187:187:187) (237:237:237)) + (PORT datad (192:192:192) (237:237:237)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -52425,7 +52221,7 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~12) (DELAY (ABSOLUTE - (PORT dataa (222:222:222) (278:278:278)) + (PORT dataa (220:220:220) (279:279:279)) (IOPATH dataa combout (166:166:166) (173:173:173)) (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -52439,8 +52235,8 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[6\]\~5) (DELAY (ABSOLUTE - (PORT datad (172:172:172) (203:203:203)) - (IOPATH datad combout (68:68:68) (63:63:63)) + (PORT datac (163:163:163) (196:196:196)) + (IOPATH datac combout (120:120:120) (125:125:125)) ) ) ) @@ -52449,9 +52245,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[6\]) (DELAY (ABSOLUTE - (PORT clk (1105:1105:1105) (1134:1134:1134)) + (PORT clk (1131:1131:1131) (1165:1165:1165)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (905:905:905) (911:911:911)) + (PORT clrn (905:905:905) (909:909:909)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -52465,9 +52261,9 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~14) (DELAY (ABSOLUTE - (PORT dataa (227:227:227) (287:287:287)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH dataa cout (226:226:226) (171:171:171)) + (PORT datab (136:136:136) (187:187:187)) + (IOPATH datab combout (191:191:191) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) (IOPATH cin cout (34:34:34) (34:34:34)) @@ -52479,8 +52275,8 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[7\]\~4) (DELAY (ABSOLUTE - (PORT datad (169:169:169) (199:199:199)) - (IOPATH datad combout (68:68:68) (63:63:63)) + (PORT datac (92:92:92) (114:114:114)) + (IOPATH datac combout (120:120:120) (125:125:125)) ) ) ) @@ -52489,9 +52285,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[7\]) (DELAY (ABSOLUTE - (PORT clk (1105:1105:1105) (1134:1134:1134)) + (PORT clk (1125:1125:1125) (1158:1158:1158)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (905:905:905) (911:911:911)) + (PORT clrn (906:906:906) (909:909:909)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -52505,9 +52301,9 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~16) (DELAY (ABSOLUTE - (PORT dataa (207:207:207) (265:265:265)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH dataa cout (226:226:226) (171:171:171)) + (PORT datab (134:134:134) (184:184:184)) + (IOPATH datab combout (188:188:188) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) (IOPATH cin cout (34:34:34) (34:34:34)) @@ -52519,8 +52315,8 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\~0) (DELAY (ABSOLUTE - (PORT datab (190:190:190) (229:229:229)) - (PORT datac (197:197:197) (236:236:236)) + (PORT datab (103:103:103) (131:131:131)) + (PORT datac (101:101:101) (123:123:123)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (120:120:120) (125:125:125)) ) @@ -52531,9 +52327,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[8\]) (DELAY (ABSOLUTE - (PORT clk (1105:1105:1105) (1134:1134:1134)) + (PORT clk (1125:1125:1125) (1158:1158:1158)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (905:905:905) (911:911:911)) + (PORT clrn (906:906:906) (909:909:909)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -52547,8 +52343,8 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~18) (DELAY (ABSOLUTE - (PORT datad (199:199:199) (249:249:249)) - (IOPATH datad combout (68:68:68) (63:63:63)) + (PORT datab (138:138:138) (188:188:188)) + (IOPATH datab combout (196:196:196) (205:205:205)) (IOPATH cin combout (187:187:187) (204:204:204)) ) ) @@ -52558,8 +52354,8 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[9\]\~3) (DELAY (ABSOLUTE - (PORT datad (171:171:171) (202:202:202)) - (IOPATH datad combout (68:68:68) (63:63:63)) + (PORT datac (92:92:92) (114:114:114)) + (IOPATH datac combout (120:120:120) (125:125:125)) ) ) ) @@ -52568,9 +52364,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[9\]) (DELAY (ABSOLUTE - (PORT clk (1105:1105:1105) (1134:1134:1134)) + (PORT clk (1125:1125:1125) (1158:1158:1158)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (905:905:905) (911:911:911)) + (PORT clrn (906:906:906) (909:909:909)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -52584,12 +52380,12 @@ (INSTANCE ula_\|i2s_intf_\|Equal0\~0) (DELAY (ABSOLUTE - (PORT dataa (207:207:207) (266:266:266)) - (PORT datab (220:220:220) (276:276:276)) - (PORT datac (202:202:202) (259:259:259)) - (PORT datad (201:201:201) (254:254:254)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) + (PORT dataa (217:217:217) (275:275:275)) + (PORT datab (137:137:137) (188:188:188)) + (PORT datac (119:119:119) (163:163:163)) + (PORT datad (120:120:120) (160:160:160)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -52600,35 +52396,25 @@ (INSTANCE ula_\|i2s_intf_\|Equal0\~2) (DELAY (ABSOLUTE - (PORT dataa (103:103:103) (134:134:134)) - (PORT datab (132:132:132) (182:182:182)) - (PORT datac (360:360:360) (431:431:431)) - (PORT datad (94:94:94) (112:112:112)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (PORT dataa (222:222:222) (281:281:281)) + (PORT datab (107:107:107) (136:136:136)) + (PORT datac (196:196:196) (251:251:251)) + (PORT datad (93:93:93) (111:111:111)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|lrclk_r\~_Duplicate_2feeder) - (DELAY - (ABSOLUTE - (PORT datad (105:105:105) (123:123:123)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|i2s_intf_\|lrclk_r\~_Duplicate_2) (DELAY (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) + (PORT clk (1124:1124:1124) (1157:1157:1157)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (906:906:906) (912:912:912)) + (PORT clrn (905:905:905) (908:908:908)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -52642,10 +52428,9 @@ (INSTANCE ula_\|i2s_intf_\|lrclk_r\~0) (DELAY (ABSOLUTE - (PORT datab (492:492:492) (573:573:573)) - (PORT datad (128:128:128) (168:168:168)) - (IOPATH datab combout (192:192:192) (181:181:181)) - (IOPATH datad combout (68:68:68) (63:63:63)) + (PORT datab (445:445:445) (533:533:533)) + (IOPATH datab combout (196:196:196) (205:205:205)) + (IOPATH datac combout (190:190:190) (195:195:195)) ) ) ) @@ -52655,8 +52440,8 @@ (DELAY (ABSOLUTE (PORT clk (889:889:889) (911:911:911)) - (PORT d (1273:1273:1273) (1412:1412:1412)) - (PORT clrn (1027:1027:1027) (1074:1074:1074)) + (PORT d (745:745:745) (801:801:801)) + (PORT clrn (1018:1018:1018) (1063:1063:1063)) (IOPATH (posedge clk) q (329:329:329) (329:329:329)) (IOPATH (negedge clrn) q (395:395:395) (395:395:395)) ) @@ -52672,8 +52457,8 @@ (DELAY (ABSOLUTE (PORT clk (891:891:891) (912:912:912)) - (PORT d (1390:1390:1390) (1547:1547:1547)) - (PORT clrn (1029:1029:1029) (1075:1075:1075)) + (PORT d (740:740:740) (796:796:796)) + (PORT clrn (1020:1020:1020) (1064:1064:1064)) (IOPATH (posedge clk) q (329:329:329) (329:329:329)) (IOPATH (negedge clrn) q (395:395:395) (395:395:395)) ) @@ -52694,14 +52479,24 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|bclk_r\~_Duplicate_1feeder) + (DELAY + (ABSOLUTE + (PORT datad (103:103:103) (119:119:119)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|i2s_intf_\|bclk_r\~_Duplicate_1) (DELAY (ABSOLUTE - (PORT clk (909:909:909) (913:913:913)) + (PORT clk (916:916:916) (921:921:921)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (907:907:907) (912:912:912)) + (PORT clrn (905:905:905) (909:909:909)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -52715,10 +52510,10 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[4\]\~15) (DELAY (ABSOLUTE - (PORT datab (124:124:124) (159:159:159)) - (PORT datac (471:471:471) (543:543:543)) - (PORT datad (132:132:132) (176:176:176)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT dataa (153:153:153) (212:212:212)) + (PORT datac (316:316:316) (363:363:363)) + (PORT datad (108:108:108) (128:128:128)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -52729,12 +52524,12 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[0\]) (DELAY (ABSOLUTE - (PORT clk (909:909:909) (913:913:913)) + (PORT clk (916:916:916) (921:921:921)) (PORT d (37:37:37) (50:50:50)) - (PORT asdata (1507:1507:1507) (1683:1683:1683)) - (PORT clrn (907:907:907) (912:912:912)) - (PORT sload (777:777:777) (867:867:867)) - (PORT ena (407:407:407) (424:424:424)) + (PORT asdata (301:301:301) (329:329:329)) + (PORT clrn (905:905:905) (909:909:909)) + (PORT sload (628:628:628) (691:691:691)) + (PORT ena (408:408:408) (428:428:428)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -52751,9 +52546,9 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[1\]\~7) (DELAY (ABSOLUTE - (PORT datab (133:133:133) (183:183:183)) - (IOPATH datab combout (167:167:167) (174:174:174)) - (IOPATH datab cout (227:227:227) (175:175:175)) + (PORT dataa (222:222:222) (281:281:281)) + (IOPATH dataa combout (166:166:166) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) (IOPATH cin cout (34:34:34) (34:34:34)) @@ -52765,12 +52560,12 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[1\]) (DELAY (ABSOLUTE - (PORT clk (909:909:909) (913:913:913)) + (PORT clk (916:916:916) (921:921:921)) (PORT d (37:37:37) (50:50:50)) - (PORT asdata (1507:1507:1507) (1683:1683:1683)) - (PORT clrn (907:907:907) (912:912:912)) - (PORT sload (777:777:777) (867:867:867)) - (PORT ena (407:407:407) (424:424:424)) + (PORT asdata (300:300:300) (328:328:328)) + (PORT clrn (905:905:905) (909:909:909)) + (PORT sload (628:628:628) (691:691:691)) + (PORT ena (408:408:408) (428:428:428)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -52801,12 +52596,12 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[2\]) (DELAY (ABSOLUTE - (PORT clk (909:909:909) (913:913:913)) + (PORT clk (916:916:916) (921:921:921)) (PORT d (37:37:37) (50:50:50)) - (PORT asdata (1506:1506:1506) (1683:1683:1683)) - (PORT clrn (907:907:907) (912:912:912)) - (PORT sload (777:777:777) (867:867:867)) - (PORT ena (407:407:407) (424:424:424)) + (PORT asdata (300:300:300) (328:328:328)) + (PORT clrn (905:905:905) (909:909:909)) + (PORT sload (628:628:628) (691:691:691)) + (PORT ena (408:408:408) (428:428:428)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -52823,7 +52618,7 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[3\]\~11) (DELAY (ABSOLUTE - (PORT dataa (136:136:136) (189:189:189)) + (PORT dataa (135:135:135) (187:187:187)) (IOPATH dataa combout (166:166:166) (173:173:173)) (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -52837,12 +52632,45 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[3\]) (DELAY (ABSOLUTE - (PORT clk (909:909:909) (913:913:913)) + (PORT clk (916:916:916) (921:921:921)) (PORT d (37:37:37) (50:50:50)) - (PORT asdata (1506:1506:1506) (1682:1682:1682)) - (PORT clrn (907:907:907) (912:912:912)) - (PORT sload (777:777:777) (867:867:867)) - (PORT ena (407:407:407) (424:424:424)) + (PORT asdata (299:299:299) (327:327:327)) + (PORT clrn (905:905:905) (909:909:909)) + (PORT sload (628:628:628) (691:691:691)) + (PORT ena (408:408:408) (428:428:428)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|bitcount\[4\]\~13) + (DELAY + (ABSOLUTE + (PORT datab (146:146:146) (199:199:199)) + (IOPATH datab combout (196:196:196) (205:205:205)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|bitcount\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (916:916:916) (921:921:921)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (299:299:299) (327:327:327)) + (PORT clrn (905:905:905) (909:909:909)) + (PORT sload (628:628:628) (691:691:691)) + (PORT ena (408:408:408) (428:428:428)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -52859,10 +52687,10 @@ (INSTANCE ula_\|i2s_intf_\|LessThan0\~0) (DELAY (ABSOLUTE - (PORT dataa (137:137:137) (191:191:191)) - (PORT datab (137:137:137) (188:188:188)) + (PORT dataa (225:225:225) (284:284:284)) + (PORT datab (137:137:137) (187:187:187)) (PORT datac (122:122:122) (166:166:166)) - (PORT datad (124:124:124) (163:163:163)) + (PORT datad (123:123:123) (163:163:163)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -52872,35 +52700,49 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|bitcount\[4\]\~13) + (INSTANCE ula_\|i2s_intf_\|shiftreg\[4\]\~1) (DELAY (ABSOLUTE - (PORT datab (145:145:145) (199:199:199)) - (IOPATH datab combout (196:196:196) (205:205:205)) - (IOPATH cin combout (187:187:187) (204:204:204)) + (PORT dataa (228:228:228) (282:282:282)) + (PORT datab (199:199:199) (235:235:235)) + (PORT datac (130:130:130) (177:177:177)) + (PORT datad (100:100:100) (122:122:122)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add2\~18) + (DELAY + (ABSOLUTE + (PORT dataa (252:252:252) (313:313:313)) + (PORT datab (199:199:199) (242:242:242)) + (PORT datad (117:117:117) (140:140:140)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|bitcount\[4\]) + (INSTANCE ula_\|i2s_intf_\|bdivider\[0\]) (DELAY (ABSOLUTE - (PORT clk (909:909:909) (913:913:913)) + (PORT clk (916:916:916) (921:921:921)) (PORT d (37:37:37) (50:50:50)) - (PORT asdata (1506:1506:1506) (1682:1682:1682)) - (PORT clrn (907:907:907) (912:912:912)) - (PORT sload (777:777:777) (867:867:867)) - (PORT ena (407:407:407) (424:424:424)) + (PORT clrn (905:905:905) (909:909:909)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) ) (TIMINGCHECK (HOLD d (posedge clk) (84:84:84)) - (HOLD sload (posedge clk) (84:84:84)) - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) ) ) (CELL @@ -52908,7 +52750,7 @@ (INSTANCE ula_\|i2s_intf_\|Add2\~7) (DELAY (ABSOLUTE - (PORT dataa (241:241:241) (304:304:304)) + (PORT dataa (158:158:158) (215:215:215)) (IOPATH dataa cout (226:226:226) (171:171:171)) ) ) @@ -52918,7 +52760,7 @@ (INSTANCE ula_\|i2s_intf_\|Add2\~8) (DELAY (ABSOLUTE - (PORT dataa (136:136:136) (190:190:190)) + (PORT dataa (138:138:138) (192:192:192)) (IOPATH dataa combout (166:166:166) (173:173:173)) (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -52932,13 +52774,13 @@ (INSTANCE ula_\|i2s_intf_\|Add2\~20) (DELAY (ABSOLUTE - (PORT dataa (241:241:241) (305:305:305)) - (PORT datab (491:491:491) (572:572:572)) - (PORT datac (109:109:109) (134:134:134)) - (PORT datad (91:91:91) (108:108:108)) + (PORT dataa (159:159:159) (216:216:216)) + (PORT datab (105:105:105) (135:135:135)) + (PORT datac (234:234:234) (294:294:294)) + (PORT datad (115:115:115) (137:137:137)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -52948,9 +52790,9 @@ (INSTANCE ula_\|i2s_intf_\|bdivider\[1\]) (DELAY (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) + (PORT clk (916:916:916) (921:921:921)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (906:906:906) (912:912:912)) + (PORT clrn (905:905:905) (909:909:909)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -52964,7 +52806,7 @@ (INSTANCE ula_\|i2s_intf_\|Add2\~10) (DELAY (ABSOLUTE - (PORT dataa (208:208:208) (267:267:267)) + (PORT dataa (138:138:138) (192:192:192)) (IOPATH dataa combout (166:166:166) (173:173:173)) (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -52978,12 +52820,12 @@ (INSTANCE ula_\|i2s_intf_\|Add2\~17) (DELAY (ABSOLUTE - (PORT dataa (121:121:121) (158:158:158)) - (PORT datab (124:124:124) (160:160:160)) - (PORT datac (472:472:472) (545:545:545)) - (PORT datad (172:172:172) (203:203:203)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (PORT dataa (259:259:259) (322:322:322)) + (PORT datab (122:122:122) (153:153:153)) + (PORT datac (186:186:186) (223:223:223)) + (PORT datad (93:93:93) (111:111:111)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -52994,9 +52836,9 @@ (INSTANCE ula_\|i2s_intf_\|bdivider\[2\]) (DELAY (ABSOLUTE - (PORT clk (909:909:909) (913:913:913)) + (PORT clk (916:916:916) (921:921:921)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (907:907:907) (912:912:912)) + (PORT clrn (905:905:905) (909:909:909)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -53010,7 +52852,7 @@ (INSTANCE ula_\|i2s_intf_\|Add2\~12) (DELAY (ABSOLUTE - (PORT datab (138:138:138) (189:189:189)) + (PORT datab (134:134:134) (185:185:185)) (IOPATH datab combout (167:167:167) (174:174:174)) (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -53024,13 +52866,13 @@ (INSTANCE ula_\|i2s_intf_\|Add2\~19) (DELAY (ABSOLUTE - (PORT dataa (241:241:241) (305:305:305)) - (PORT datab (492:492:492) (574:574:574)) - (PORT datac (110:110:110) (135:135:135)) - (PORT datad (92:92:92) (110:110:110)) + (PORT dataa (159:159:159) (216:216:216)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (224:224:224) (281:281:281)) + (PORT datad (119:119:119) (142:142:142)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -53040,9 +52882,9 @@ (INSTANCE ula_\|i2s_intf_\|bdivider\[3\]) (DELAY (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) + (PORT clk (916:916:916) (921:921:921)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (906:906:906) (912:912:912)) + (PORT clrn (905:905:905) (909:909:909)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -53056,7 +52898,7 @@ (INSTANCE ula_\|i2s_intf_\|Add2\~14) (DELAY (ABSOLUTE - (PORT datad (189:189:189) (236:236:236)) + (PORT datad (124:124:124) (164:164:164)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) ) @@ -53067,12 +52909,12 @@ (INSTANCE ula_\|i2s_intf_\|Add2\~16) (DELAY (ABSOLUTE - (PORT dataa (121:121:121) (158:158:158)) - (PORT datab (124:124:124) (159:159:159)) - (PORT datac (472:472:472) (545:545:545)) - (PORT datad (172:172:172) (203:203:203)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (PORT dataa (260:260:260) (324:324:324)) + (PORT datab (123:123:123) (154:154:154)) + (PORT datac (187:187:187) (223:223:223)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -53083,9 +52925,9 @@ (INSTANCE ula_\|i2s_intf_\|bdivider\[4\]) (DELAY (ABSOLUTE - (PORT clk (909:909:909) (913:913:913)) + (PORT clk (916:916:916) (921:921:921)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (907:907:907) (912:912:912)) + (PORT clrn (905:905:905) (909:909:909)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -53099,72 +52941,25 @@ (INSTANCE ula_\|i2s_intf_\|Equal1\~0) (DELAY (ABSOLUTE - (PORT dataa (137:137:137) (190:190:190)) - (PORT datab (138:138:138) (189:189:189)) - (PORT datac (193:193:193) (243:243:243)) - (PORT datad (189:189:189) (235:235:235)) + (PORT dataa (136:136:136) (187:187:187)) + (PORT datab (134:134:134) (184:184:184)) + (PORT datac (121:121:121) (164:164:164)) + (PORT datad (124:124:124) (163:163:163)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[4\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (143:143:143) (194:194:194)) - (PORT datab (113:113:113) (145:145:145)) - (PORT datac (131:131:131) (180:180:180)) - (PORT datad (193:193:193) (226:226:226)) - (IOPATH dataa combout (165:165:165) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~18) - (DELAY - (ABSOLUTE - (PORT dataa (489:489:489) (573:573:573)) - (PORT datab (124:124:124) (160:160:160)) - (PORT datad (195:195:195) (229:229:229)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|bdivider\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (913:913:913)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (907:907:907) (912:912:912)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2s_intf_\|Equal1\~1) (DELAY (ABSOLUTE - (PORT datac (201:201:201) (253:253:253)) - (PORT datad (193:193:193) (226:226:226)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT datab (129:129:129) (162:162:162)) + (PORT datad (144:144:144) (189:189:189)) + (IOPATH datab combout (167:167:167) (167:167:167)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -53174,12 +52969,12 @@ (INSTANCE ula_\|i2s_intf_\|bclk_r\~0) (DELAY (ABSOLUTE - (PORT datab (114:114:114) (146:146:146)) - (PORT datac (130:130:130) (178:178:178)) - (PORT datad (128:128:128) (172:172:172)) - (IOPATH datab combout (188:188:188) (181:181:181)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) + (PORT dataa (153:153:153) (212:212:212)) + (PORT datab (112:112:112) (143:143:143)) + (PORT datac (131:131:131) (179:179:179)) + (IOPATH dataa combout (188:188:188) (179:179:179)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (120:120:120) (125:125:125)) ) ) ) @@ -53188,12 +52983,13 @@ (INSTANCE ula_\|i2s_intf_\|bclk_r\~1) (DELAY (ABSOLUTE - (PORT dataa (121:121:121) (160:160:160)) - (PORT datab (103:103:103) (131:131:131)) - (PORT datad (466:466:466) (535:535:535)) - (IOPATH dataa combout (188:188:188) (184:184:184)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) + (PORT dataa (194:194:194) (231:231:231)) + (PORT datab (332:332:332) (385:385:385)) + (PORT datac (136:136:136) (186:186:186)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -53204,8 +53000,8 @@ (DELAY (ABSOLUTE (PORT clk (888:888:888) (910:910:910)) - (PORT d (1273:1273:1273) (1428:1428:1428)) - (PORT clrn (1026:1026:1026) (1073:1073:1073)) + (PORT d (843:843:843) (919:919:919)) + (PORT clrn (1017:1017:1017) (1062:1062:1062)) (IOPATH (posedge clk) q (329:329:329) (329:329:329)) (IOPATH (negedge clrn) q (395:395:395) (395:395:395)) ) @@ -53215,27 +53011,17 @@ (HOLD d (posedge clk) (56:56:56)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|pcm_outl\[13\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (471:471:471) (541:541:541)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|always0\~2) (DELAY (ABSOLUTE - (PORT dataa (983:983:983) (1142:1142:1142)) - (PORT datab (897:897:897) (1062:1062:1062)) - (PORT datac (653:653:653) (769:769:769)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT dataa (304:304:304) (355:355:355)) + (PORT datab (1547:1547:1547) (1820:1820:1820)) + (PORT datad (313:313:313) (369:369:369)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) @@ -53244,12 +53030,12 @@ (INSTANCE ula_\|always0\~3) (DELAY (ABSOLUTE - (PORT dataa (379:379:379) (457:457:457)) - (PORT datab (693:693:693) (818:818:818)) - (PORT datac (659:659:659) (775:775:775)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) + (PORT dataa (131:131:131) (169:169:169)) + (PORT datab (507:507:507) (608:608:608)) + (PORT datac (1532:1532:1532) (1800:1800:1800)) + (PORT datad (267:267:267) (305:305:305)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -53257,12 +53043,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|pcm_outl\[13\]) + (INSTANCE ula_\|pcm_outl\[14\]) (DELAY (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) + (PORT clk (904:904:904) (909:909:909)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (1089:1089:1089) (1200:1200:1200)) + (PORT ena (1011:1011:1011) (1119:1119:1119)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -53276,13 +53062,13 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[0\]\~19) (DELAY (ABSOLUTE - (PORT dataa (119:119:119) (156:156:156)) - (PORT datab (112:112:112) (144:144:144)) - (PORT datac (132:132:132) (181:181:181)) - (PORT datad (132:132:132) (175:175:175)) + (PORT dataa (193:193:193) (231:231:231)) + (PORT datab (147:147:147) (202:202:202)) + (PORT datac (138:138:138) (188:188:188)) + (PORT datad (99:99:99) (120:120:120)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -53301,11 +53087,11 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[0\]\~20) (DELAY (ABSOLUTE - (PORT dataa (751:751:751) (865:865:865)) - (PORT datab (734:734:734) (861:861:861)) - (PORT datad (433:433:433) (467:467:467)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (182:182:182) (177:177:177)) + (PORT dataa (256:256:256) (318:318:318)) + (PORT datab (175:175:175) (213:213:213)) + (PORT datad (445:445:445) (482:482:482)) + (IOPATH dataa combout (181:181:181) (175:175:175)) + (IOPATH datab combout (166:166:166) (158:158:158)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -53316,9 +53102,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[0\]) (DELAY (ABSOLUTE - (PORT clk (1102:1102:1102) (1123:1123:1123)) + (PORT clk (916:916:916) (921:921:921)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (913:913:913) (919:919:919)) + (PORT clrn (905:905:905) (909:909:909)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -53332,10 +53118,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~18) (DELAY (ABSOLUTE - (PORT datab (131:131:131) (178:178:178)) - (PORT datad (711:711:711) (829:829:829)) + (PORT datab (217:217:217) (276:276:276)) + (PORT datac (427:427:427) (515:515:515)) (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH datac combout (120:120:120) (125:125:125)) ) ) ) @@ -53344,10 +53130,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[4\]\~2) (DELAY (ABSOLUTE - (PORT datab (123:123:123) (159:159:159)) - (PORT datac (470:470:470) (543:543:543)) - (PORT datad (133:133:133) (176:176:176)) - (IOPATH datab combout (166:166:166) (167:167:167)) + (PORT dataa (151:151:151) (210:210:210)) + (PORT datac (317:317:317) (364:364:364)) + (PORT datad (109:109:109) (129:129:129)) + (IOPATH dataa combout (165:165:165) (163:163:163)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -53358,10 +53144,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[1\]) (DELAY (ABSOLUTE - (PORT clk (1117:1117:1117) (1148:1148:1148)) + (PORT clk (916:916:916) (920:920:920)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (913:913:913) (919:919:919)) - (PORT ena (1166:1166:1166) (1303:1303:1303)) + (PORT clrn (905:905:905) (908:908:908)) + (PORT ena (625:625:625) (678:678:678)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -53376,10 +53162,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~17) (DELAY (ABSOLUTE - (PORT datac (117:117:117) (157:157:157)) - (PORT datad (712:712:712) (830:830:830)) + (PORT datab (447:447:447) (535:535:535)) + (PORT datac (118:118:118) (160:160:160)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) @@ -53388,10 +53174,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[2\]) (DELAY (ABSOLUTE - (PORT clk (1117:1117:1117) (1148:1148:1148)) + (PORT clk (916:916:916) (920:920:920)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (913:913:913) (919:919:919)) - (PORT ena (1166:1166:1166) (1303:1303:1303)) + (PORT clrn (905:905:905) (908:908:908)) + (PORT ena (625:625:625) (678:678:678)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -53406,9 +53192,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~16) (DELAY (ABSOLUTE - (PORT datab (131:131:131) (179:179:179)) - (PORT datad (714:714:714) (833:833:833)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT datac (426:426:426) (514:514:514)) + (PORT datad (118:118:118) (155:155:155)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -53418,10 +53204,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[3\]) (DELAY (ABSOLUTE - (PORT clk (1117:1117:1117) (1148:1148:1148)) + (PORT clk (916:916:916) (920:920:920)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (913:913:913) (919:919:919)) - (PORT ena (1166:1166:1166) (1303:1303:1303)) + (PORT clrn (905:905:905) (908:908:908)) + (PORT ena (625:625:625) (678:678:678)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -53436,10 +53222,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~15) (DELAY (ABSOLUTE - (PORT datab (132:132:132) (181:181:181)) - (PORT datad (723:723:723) (843:843:843)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) + (PORT datab (444:444:444) (533:533:533)) + (PORT datac (119:119:119) (161:161:161)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) ) ) ) @@ -53448,10 +53234,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[4\]) (DELAY (ABSOLUTE - (PORT clk (1117:1117:1117) (1148:1148:1148)) + (PORT clk (916:916:916) (920:920:920)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (913:913:913) (919:919:919)) - (PORT ena (1166:1166:1166) (1303:1303:1303)) + (PORT clrn (905:905:905) (908:908:908)) + (PORT ena (625:625:625) (678:678:678)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -53466,9 +53252,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~14) (DELAY (ABSOLUTE - (PORT datab (131:131:131) (180:180:180)) - (PORT datad (719:719:719) (838:838:838)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT datac (424:424:424) (512:512:512)) + (PORT datad (119:119:119) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -53478,10 +53264,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[5\]) (DELAY (ABSOLUTE - (PORT clk (1117:1117:1117) (1148:1148:1148)) + (PORT clk (916:916:916) (920:920:920)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (913:913:913) (919:919:919)) - (PORT ena (1166:1166:1166) (1303:1303:1303)) + (PORT clrn (905:905:905) (908:908:908)) + (PORT ena (625:625:625) (678:678:678)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -53496,10 +53282,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~13) (DELAY (ABSOLUTE - (PORT dataa (132:132:132) (183:183:183)) - (PORT datad (715:715:715) (834:834:834)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datad combout (68:68:68) (63:63:63)) + (PORT datab (449:449:449) (539:539:539)) + (PORT datac (118:118:118) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) ) ) ) @@ -53508,10 +53294,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[6\]) (DELAY (ABSOLUTE - (PORT clk (1117:1117:1117) (1148:1148:1148)) + (PORT clk (916:916:916) (920:920:920)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (913:913:913) (919:919:919)) - (PORT ena (1166:1166:1166) (1303:1303:1303)) + (PORT clrn (905:905:905) (908:908:908)) + (PORT ena (625:625:625) (678:678:678)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -53526,9 +53312,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~12) (DELAY (ABSOLUTE - (PORT datab (131:131:131) (180:180:180)) - (PORT datad (709:709:709) (827:827:827)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT datac (427:427:427) (516:516:516)) + (PORT datad (117:117:117) (154:154:154)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -53538,10 +53324,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[7\]) (DELAY (ABSOLUTE - (PORT clk (1117:1117:1117) (1148:1148:1148)) + (PORT clk (916:916:916) (920:920:920)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (913:913:913) (919:919:919)) - (PORT ena (1166:1166:1166) (1303:1303:1303)) + (PORT clrn (905:905:905) (908:908:908)) + (PORT ena (625:625:625) (678:678:678)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -53556,10 +53342,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~11) (DELAY (ABSOLUTE - (PORT datac (116:116:116) (157:157:157)) - (PORT datad (710:710:710) (828:828:828)) + (PORT datab (449:449:449) (538:538:538)) + (PORT datac (117:117:117) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) @@ -53568,10 +53354,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[8\]) (DELAY (ABSOLUTE - (PORT clk (1117:1117:1117) (1148:1148:1148)) + (PORT clk (916:916:916) (920:920:920)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (913:913:913) (919:919:919)) - (PORT ena (1166:1166:1166) (1303:1303:1303)) + (PORT clrn (905:905:905) (908:908:908)) + (PORT ena (625:625:625) (678:678:678)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -53586,9 +53372,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~10) (DELAY (ABSOLUTE - (PORT datab (131:131:131) (179:179:179)) - (PORT datad (713:713:713) (831:831:831)) - (IOPATH datab combout (168:168:168) (167:167:167)) + (PORT datac (422:422:422) (510:510:510)) + (PORT datad (119:119:119) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -53598,10 +53384,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[9\]) (DELAY (ABSOLUTE - (PORT clk (1117:1117:1117) (1148:1148:1148)) + (PORT clk (916:916:916) (920:920:920)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (913:913:913) (919:919:919)) - (PORT ena (1166:1166:1166) (1303:1303:1303)) + (PORT clrn (905:905:905) (908:908:908)) + (PORT ena (625:625:625) (678:678:678)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -53616,10 +53402,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~9) (DELAY (ABSOLUTE - (PORT datac (118:118:118) (159:159:159)) - (PORT datad (718:718:718) (837:837:837)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) + (PORT dataa (132:132:132) (184:184:184)) + (PORT datac (425:425:425) (513:513:513)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (120:120:120) (125:125:125)) ) ) ) @@ -53628,10 +53414,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[10\]) (DELAY (ABSOLUTE - (PORT clk (1117:1117:1117) (1148:1148:1148)) + (PORT clk (916:916:916) (920:920:920)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (913:913:913) (919:919:919)) - (PORT ena (1166:1166:1166) (1303:1303:1303)) + (PORT clrn (905:905:905) (908:908:908)) + (PORT ena (625:625:625) (678:678:678)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -53646,9 +53432,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~8) (DELAY (ABSOLUTE - (PORT dataa (132:132:132) (182:182:182)) - (PORT datad (722:722:722) (842:842:842)) - (IOPATH dataa combout (170:170:170) (163:163:163)) + (PORT datac (425:425:425) (513:513:513)) + (PORT datad (117:117:117) (154:154:154)) + (IOPATH datac combout (119:119:119) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -53658,10 +53444,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[11\]) (DELAY (ABSOLUTE - (PORT clk (1117:1117:1117) (1148:1148:1148)) + (PORT clk (916:916:916) (920:920:920)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (913:913:913) (919:919:919)) - (PORT ena (1166:1166:1166) (1303:1303:1303)) + (PORT clrn (905:905:905) (908:908:908)) + (PORT ena (625:625:625) (678:678:678)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -53676,10 +53462,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~7) (DELAY (ABSOLUTE - (PORT datab (130:130:130) (179:179:179)) - (PORT datad (720:720:720) (839:839:839)) + (PORT datab (131:131:131) (179:179:179)) + (PORT datac (427:427:427) (515:515:515)) (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH datac combout (120:120:120) (125:125:125)) ) ) ) @@ -53688,10 +53474,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[12\]) (DELAY (ABSOLUTE - (PORT clk (1117:1117:1117) (1148:1148:1148)) + (PORT clk (916:916:916) (920:920:920)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (913:913:913) (919:919:919)) - (PORT ena (1166:1166:1166) (1303:1303:1303)) + (PORT clrn (905:905:905) (908:908:908)) + (PORT ena (625:625:625) (678:678:678)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -53701,47 +53487,16 @@ (HOLD ena (posedge clk) (84:84:84)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|PCM_INR\[14\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (783:783:783) (903:903:903)) - (PORT datab (487:487:487) (568:568:568)) - (PORT datad (124:124:124) (165:165:165)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|PCM_INR\[14\]) - (DELAY - (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (906:906:906) (912:912:912)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2s_intf_\|PCM_INL\[14\]\~0) (DELAY (ABSOLUTE - (PORT dataa (783:783:783) (903:903:903)) - (PORT datab (487:487:487) (568:568:568)) - (PORT datad (125:125:125) (165:165:165)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (190:190:190) (188:188:188)) + (PORT dataa (261:261:261) (325:325:325)) + (PORT datab (308:308:308) (371:371:371)) + (PORT datad (203:203:203) (248:248:248)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (182:182:182) (177:177:177)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -53752,9 +53507,40 @@ (INSTANCE ula_\|i2s_intf_\|PCM_INL\[14\]) (DELAY (ABSOLUTE - (PORT clk (908:908:908) (913:913:913)) + (PORT clk (916:916:916) (921:921:921)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (906:906:906) (912:912:912)) + (PORT clrn (905:905:905) (909:909:909)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|PCM_INR\[14\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (255:255:255) (317:317:317)) + (PORT datab (306:306:306) (367:367:367)) + (PORT datad (201:201:201) (246:246:246)) + (IOPATH dataa combout (158:158:158) (173:173:173)) + (IOPATH datab combout (160:160:160) (176:176:176)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|PCM_INR\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (916:916:916) (921:921:921)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (905:905:905) (909:909:909)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -53768,8 +53554,8 @@ (INSTANCE ula_\|pcm_outr\~0) (DELAY (ABSOLUTE - (PORT datac (119:119:119) (161:161:161)) - (PORT datad (120:120:120) (158:158:158)) + (PORT datac (116:116:116) (158:158:158)) + (PORT datad (118:118:118) (155:155:155)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -53780,9 +53566,9 @@ (INSTANCE ula_\|pcm_outl\[12\]) (DELAY (ABSOLUTE - (PORT clk (911:911:911) (915:915:915)) + (PORT clk (911:911:911) (916:916:916)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (1148:1148:1148) (1270:1270:1270)) + (PORT ena (1983:1983:1983) (2210:2210:2210)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -53796,11 +53582,11 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~6) (DELAY (ABSOLUTE - (PORT datab (738:738:738) (865:865:865)) - (PORT datac (117:117:117) (158:158:158)) - (PORT datad (720:720:720) (842:842:842)) - (IOPATH datab combout (166:166:166) (176:176:176)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT datab (132:132:132) (182:182:182)) + (PORT datac (423:423:423) (511:511:511)) + (PORT datad (200:200:200) (251:251:251)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -53810,10 +53596,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[13\]) (DELAY (ABSOLUTE - (PORT clk (1117:1117:1117) (1148:1148:1148)) + (PORT clk (916:916:916) (920:920:920)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (913:913:913) (919:919:919)) - (PORT ena (1166:1166:1166) (1303:1303:1303)) + (PORT clrn (905:905:905) (908:908:908)) + (PORT ena (625:625:625) (678:678:678)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -53823,16 +53609,32 @@ (HOLD ena (posedge clk) (84:84:84)) ) ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|pcm_outl\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (903:903:903) (907:907:907)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (1311:1311:1311) (1458:1458:1458)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2s_intf_\|shiftreg\~5) (DELAY (ABSOLUTE - (PORT datab (698:698:698) (823:823:823)) - (PORT datac (117:117:117) (158:158:158)) - (PORT datad (722:722:722) (841:841:841)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT dataa (131:131:131) (182:182:182)) + (PORT datab (446:446:446) (535:535:535)) + (PORT datad (1114:1114:1114) (1275:1275:1275)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (158:158:158)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -53842,10 +53644,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[14\]) (DELAY (ABSOLUTE - (PORT clk (1117:1117:1117) (1148:1148:1148)) + (PORT clk (916:916:916) (920:920:920)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (913:913:913) (919:919:919)) - (PORT ena (1166:1166:1166) (1303:1303:1303)) + (PORT clrn (905:905:905) (908:908:908)) + (PORT ena (625:625:625) (678:678:678)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -53855,33 +53657,17 @@ (HOLD ena (posedge clk) (84:84:84)) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|pcm_outl\[14\]) - (DELAY - (ABSOLUTE - (PORT clk (909:909:909) (913:913:913)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (1213:1213:1213) (1335:1335:1335)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2s_intf_\|shiftreg\~4) (DELAY (ABSOLUTE - (PORT dataa (683:683:683) (796:796:796)) - (PORT datac (555:555:555) (662:662:662)) - (PORT datad (356:356:356) (415:415:415)) + (PORT dataa (1318:1318:1318) (1538:1538:1538)) + (PORT datab (142:142:142) (190:190:190)) + (PORT datac (422:422:422) (509:509:509)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) ) ) ) @@ -53890,10 +53676,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[15\]) (DELAY (ABSOLUTE - (PORT clk (1108:1108:1108) (1141:1141:1141)) + (PORT clk (916:916:916) (920:920:920)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (907:907:907) (913:913:913)) - (PORT ena (599:599:599) (641:641:641)) + (PORT clrn (905:905:905) (908:908:908)) + (PORT ena (625:625:625) (678:678:678)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -53908,10 +53694,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~3) (DELAY (ABSOLUTE - (PORT datac (116:116:116) (157:157:157)) - (PORT datad (357:357:357) (416:416:416)) + (PORT dataa (237:237:237) (288:288:288)) + (PORT datac (319:319:319) (388:388:388)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) @@ -53920,10 +53706,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[16\]) (DELAY (ABSOLUTE - (PORT clk (909:909:909) (914:914:914)) + (PORT clk (1116:1116:1116) (1143:1143:1143)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (907:907:907) (913:913:913)) - (PORT ena (617:617:617) (670:670:670)) + (PORT clrn (905:905:905) (909:909:909)) + (PORT ena (756:756:756) (822:822:822)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -53938,10 +53724,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~0) (DELAY (ABSOLUTE - (PORT datab (131:131:131) (179:179:179)) - (PORT datad (354:354:354) (413:413:413)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) + (PORT dataa (132:132:132) (182:182:182)) + (PORT datac (217:217:217) (268:268:268)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (120:120:120) (125:125:125)) ) ) ) @@ -53951,9 +53737,9 @@ (DELAY (ABSOLUTE (PORT clk (893:893:893) (915:915:915)) - (PORT d (827:827:827) (902:902:902)) - (PORT clrn (1031:1031:1031) (1077:1077:1077)) - (PORT ena (946:946:946) (1053:1053:1053)) + (PORT d (480:480:480) (501:501:501)) + (PORT clrn (1022:1022:1022) (1066:1066:1066)) + (PORT ena (469:469:469) (496:496:496)) (IOPATH (posedge clk) q (329:329:329) (329:329:329)) (IOPATH (negedge clrn) q (395:395:395) (395:395:395)) ) @@ -53967,16 +53753,57 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|LessThan2\~0) + (INSTANCE ula_\|border\[1\]\~feeder) (DELAY (ABSOLUTE - (PORT dataa (159:159:159) (210:210:210)) - (PORT datab (147:147:147) (197:197:197)) - (PORT datac (144:144:144) (185:185:185)) - (PORT datad (133:133:133) (172:172:172)) + (PORT datad (117:117:117) (135:135:135)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|border\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (904:904:904) (909:909:909)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (1011:1011:1011) (1119:1119:1119)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|LessThan4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (235:235:235) (291:291:291)) + (PORT datab (149:149:149) (199:199:199)) + (PORT datac (130:130:130) (174:174:174)) + (PORT datad (130:130:130) (169:169:169)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|screen_en\~0) + (DELAY + (ABSOLUTE + (PORT dataa (232:232:232) (289:289:289)) + (PORT datab (144:144:144) (194:194:194)) + (PORT datad (158:158:158) (185:185:185)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -53986,13 +53813,60 @@ (INSTANCE ula_\|video_\|LessThan6\~0) (DELAY (ABSOLUTE - (PORT dataa (142:142:142) (192:192:192)) + (PORT dataa (140:140:140) (191:191:191)) (PORT datab (140:140:140) (188:188:188)) - (PORT datac (141:141:141) (182:182:182)) - (PORT datad (131:131:131) (168:168:168)) + (PORT datad (130:130:130) (167:167:167)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|LessThan6\~1) + (DELAY + (ABSOLUTE + (PORT dataa (154:154:154) (204:204:204)) + (PORT datab (153:153:153) (201:201:201)) + (PORT datac (129:129:129) (171:171:171)) + (PORT datad (176:176:176) (202:202:202)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|screen_en\~1) + (DELAY + (ABSOLUTE + (PORT dataa (218:218:218) (279:279:279)) + (PORT datab (242:242:242) (297:297:297)) + (PORT datac (89:89:89) (110:110:110)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|LessThan2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (413:413:413)) + (PORT datab (159:159:159) (209:209:209)) + (PORT datac (220:220:220) (272:272:272)) + (PORT datad (203:203:203) (248:248:248)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -54002,10 +53876,10 @@ (INSTANCE ula_\|video_\|LessThan2\~1) (DELAY (ABSOLUTE - (PORT dataa (247:247:247) (310:310:310)) - (PORT datab (146:146:146) (196:196:196)) - (PORT datac (91:91:91) (113:113:113)) - (PORT datad (188:188:188) (214:214:214)) + (PORT dataa (337:337:337) (407:407:407)) + (PORT datab (220:220:220) (280:280:280)) + (PORT datac (89:89:89) (109:109:109)) + (PORT datad (109:109:109) (129:129:129)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -54018,12 +53892,13 @@ (INSTANCE ula_\|video_\|LessThan3\~0) (DELAY (ABSOLUTE - (PORT dataa (159:159:159) (212:212:212)) - (PORT datab (129:129:129) (157:157:157)) + (PORT dataa (330:330:330) (399:399:399)) + (PORT datab (122:122:122) (153:153:153)) + (PORT datac (325:325:325) (392:392:392)) (PORT datad (102:102:102) (119:119:119)) (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -54033,11 +53908,10 @@ (INSTANCE ula_\|video_\|LessThan0\~0) (DELAY (ABSOLUTE - (PORT dataa (147:147:147) (201:201:201)) - (PORT datab (141:141:141) (189:189:189)) - (PORT datad (136:136:136) (176:176:176)) - (IOPATH dataa combout (158:158:158) (157:157:157)) + (PORT datab (144:144:144) (194:194:194)) + (PORT datad (135:135:135) (174:174:174)) (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -54047,11 +53921,11 @@ (INSTANCE ula_\|video_\|disp_enable\~0) (DELAY (ABSOLUTE - (PORT dataa (103:103:103) (133:133:133)) - (PORT datab (215:215:215) (273:273:273)) - (PORT datad (361:361:361) (423:423:423)) - (IOPATH dataa combout (158:158:158) (173:173:173)) - (IOPATH datab combout (191:191:191) (181:181:181)) + (PORT dataa (150:150:150) (203:203:203)) + (PORT datab (228:228:228) (291:291:291)) + (PORT datad (89:89:89) (106:106:106)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datab combout (196:196:196) (192:192:192)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -54062,100 +53936,21 @@ (INSTANCE ula_\|video_\|disp_enable\~1) (DELAY (ABSOLUTE - (PORT dataa (113:113:113) (148:148:148)) - (PORT datab (109:109:109) (140:140:140)) - (PORT datad (179:179:179) (213:213:213)) + (PORT dataa (109:109:109) (141:141:141)) + (PORT datab (107:107:107) (138:138:138)) + (PORT datad (268:268:268) (306:306:306)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (167:167:167) (158:158:158)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|border\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (911:911:911) (915:915:915)) - (PORT asdata (279:279:279) (298:298:298)) - (PORT ena (1148:1148:1148) (1270:1270:1270)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|LessThan6\~1) + (INSTANCE ula_\|video_\|attr_prefetch\[7\]\~feeder) (DELAY (ABSOLUTE - (PORT dataa (245:245:245) (312:312:312)) - (PORT datab (252:252:252) (318:318:318)) - (PORT datac (232:232:232) (290:290:290)) - (PORT datad (220:220:220) (255:255:255)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|LessThan4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (146:146:146) (199:199:199)) - (PORT datab (149:149:149) (200:200:200)) - (PORT datad (128:128:128) (164:164:164)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|screen_en\~0) - (DELAY - (ABSOLUTE - (PORT dataa (236:236:236) (294:294:294)) - (PORT datab (249:249:249) (311:311:311)) - (PORT datac (288:288:288) (330:330:330)) - (PORT datad (348:348:348) (416:416:416)) - (IOPATH dataa combout (188:188:188) (179:179:179)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|screen_en\~1) - (DELAY - (ABSOLUTE - (PORT dataa (365:365:365) (435:435:435)) - (PORT datab (258:258:258) (322:322:322)) - (PORT datac (90:90:90) (112:112:112)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (167:167:167) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|attr_prefetch\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (823:823:823) (939:939:939)) + (PORT datad (765:765:765) (865:865:865)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -54165,10 +53960,10 @@ (INSTANCE ula_\|video_\|Decoder0\~1) (DELAY (ABSOLUTE - (PORT dataa (682:682:682) (811:811:811)) - (PORT datab (533:533:533) (638:638:638)) - (PORT datac (532:532:532) (636:636:636)) - (PORT datad (153:153:153) (202:202:202)) + (PORT dataa (405:405:405) (514:514:514)) + (PORT datab (406:406:406) (495:495:495)) + (PORT datac (614:614:614) (723:723:723)) + (PORT datad (372:372:372) (452:452:452)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -54178,12 +53973,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr_prefetch\[1\]) + (INSTANCE ula_\|video_\|attr_prefetch\[7\]) (DELAY (ABSOLUTE - (PORT clk (1138:1138:1138) (1170:1170:1170)) + (PORT clk (1128:1128:1128) (1160:1160:1160)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (772:772:772) (840:840:840)) + (PORT ena (737:737:737) (794:794:794)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -54197,10 +53992,10 @@ (INSTANCE ula_\|video_\|Decoder0\~0) (DELAY (ABSOLUTE - (PORT dataa (682:682:682) (810:810:810)) - (PORT datab (533:533:533) (638:638:638)) - (PORT datac (532:532:532) (637:637:637)) - (PORT datad (154:154:154) (203:203:203)) + (PORT dataa (399:399:399) (505:505:505)) + (PORT datab (399:399:399) (487:487:487)) + (PORT datac (622:622:622) (732:732:732)) + (PORT datad (376:376:376) (456:456:456)) (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -54208,98 +54003,14 @@ ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (917:917:917) (921:921:921)) - (PORT asdata (974:974:974) (1094:1094:1094)) - (PORT ena (745:745:745) (812:812:812)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|attr_prefetch\[4\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (859:859:859) (961:961:961)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr_prefetch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1138:1138:1138) (1170:1170:1170)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (772:772:772) (840:840:840)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (917:917:917) (921:921:921)) - (PORT asdata (538:538:538) (609:609:609)) - (PORT ena (745:745:745) (812:812:812)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|attr_prefetch\[7\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (684:684:684) (780:780:780)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr_prefetch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1138:1138:1138) (1170:1170:1170)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (772:772:772) (840:840:840)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|video_\|attr\[7\]) (DELAY (ABSOLUTE - (PORT clk (918:918:918) (922:922:922)) - (PORT asdata (535:535:535) (606:606:606)) - (PORT ena (747:747:747) (817:817:817)) + (PORT clk (917:917:917) (921:921:921)) + (PORT asdata (404:404:404) (462:462:462)) + (PORT ena (742:742:742) (808:808:808)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -54313,9 +54024,9 @@ (INSTANCE ula_\|video_\|frame\[0\]\~12) (DELAY (ABSOLUTE - (PORT dataa (326:326:326) (380:380:380)) - (IOPATH dataa combout (195:195:195) (203:203:203)) + (PORT datad (316:316:316) (365:365:365)) (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) @@ -54324,7 +54035,7 @@ (INSTANCE ula_\|video_\|frame\[0\]) (DELAY (ABSOLUTE - (PORT clk (919:919:919) (923:923:923)) + (PORT clk (917:917:917) (922:922:922)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -54338,7 +54049,7 @@ (INSTANCE ula_\|video_\|frame\[1\]\~4) (DELAY (ABSOLUTE - (PORT dataa (319:319:319) (383:383:383)) + (PORT dataa (436:436:436) (520:520:520)) (PORT datab (130:130:130) (178:178:178)) (IOPATH dataa combout (186:186:186) (180:180:180)) (IOPATH dataa cout (226:226:226) (171:171:171)) @@ -54355,7 +54066,7 @@ (ABSOLUTE (PORT clk (918:918:918) (923:923:923)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (642:642:642) (697:697:697)) + (PORT ena (915:915:915) (1000:1000:1000)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -54369,9 +54080,9 @@ (INSTANCE ula_\|video_\|frame\[2\]\~6) (DELAY (ABSOLUTE - (PORT dataa (131:131:131) (182:182:182)) - (IOPATH dataa combout (165:165:165) (173:173:173)) - (IOPATH dataa cout (226:226:226) (171:171:171)) + (PORT datab (130:130:130) (178:178:178)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) (IOPATH cin cout (34:34:34) (34:34:34)) @@ -54385,7 +54096,7 @@ (ABSOLUTE (PORT clk (918:918:918) (923:923:923)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (642:642:642) (697:697:697)) + (PORT ena (915:915:915) (1000:1000:1000)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -54415,7 +54126,7 @@ (ABSOLUTE (PORT clk (918:918:918) (923:923:923)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (642:642:642) (697:697:697)) + (PORT ena (915:915:915) (1000:1000:1000)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -54429,20 +54140,30 @@ (INSTANCE ula_\|video_\|frame\[4\]\~10) (DELAY (ABSOLUTE - (PORT dataa (142:142:142) (193:193:193)) - (IOPATH dataa combout (195:195:195) (203:203:203)) + (PORT datad (369:369:369) (444:444:444)) + (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|frame\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (276:276:276) (317:317:317)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|video_\|frame\[4\]) (DELAY (ABSOLUTE - (PORT clk (918:918:918) (923:923:923)) + (PORT clk (917:917:917) (921:921:921)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (642:642:642) (697:697:697)) + (PORT ena (599:599:599) (637:637:637)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -54456,7 +54177,7 @@ (INSTANCE ula_\|video_\|inverted) (DELAY (ABSOLUTE - (PORT datad (196:196:196) (239:239:239)) + (PORT datad (131:131:131) (168:168:168)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -54467,8 +54188,8 @@ (INSTANCE ula_\|video_\|bits_prefetch\[6\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (646:646:646) (734:734:734)) - (IOPATH datad combout (68:68:68) (63:63:63)) + (PORT datac (828:828:828) (957:957:957)) + (IOPATH datac combout (119:119:119) (124:124:124)) ) ) ) @@ -54477,13 +54198,13 @@ (INSTANCE ula_\|video_\|Decoder0\~2) (DELAY (ABSOLUTE - (PORT dataa (682:682:682) (811:811:811)) - (PORT datab (534:534:534) (639:639:639)) - (PORT datac (531:531:531) (635:635:635)) - (PORT datad (152:152:152) (201:201:201)) - (IOPATH dataa combout (170:170:170) (163:163:163)) + (PORT dataa (401:401:401) (508:508:508)) + (PORT datab (401:401:401) (489:489:489)) + (PORT datac (620:620:620) (729:729:729)) + (PORT datad (375:375:375) (455:455:455)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -54493,9 +54214,9 @@ (INSTANCE ula_\|video_\|bits_prefetch\[6\]) (DELAY (ABSOLUTE - (PORT clk (1123:1123:1123) (1148:1148:1148)) + (PORT clk (1113:1113:1113) (1138:1138:1138)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (773:773:773) (844:844:844)) + (PORT ena (769:769:769) (843:843:843)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -54504,29 +54225,19 @@ (HOLD ena (posedge clk) (84:84:84)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|bits\[6\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (335:335:335) (394:394:394)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|video_\|bits\[6\]) (DELAY (ABSOLUTE - (PORT clk (918:918:918) (922:922:922)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (747:747:747) (817:817:817)) + (PORT clk (917:917:917) (921:921:921)) + (PORT asdata (492:492:492) (552:552:552)) + (PORT ena (742:742:742) (808:808:808)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) (HOLD ena (posedge clk) (84:84:84)) ) ) @@ -54535,7 +54246,7 @@ (INSTANCE ula_\|video_\|bits_prefetch\[4\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (858:858:858) (960:960:960)) + (PORT datad (1006:1006:1006) (1174:1174:1174)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -54545,9 +54256,9 @@ (INSTANCE ula_\|video_\|bits_prefetch\[4\]) (DELAY (ABSOLUTE - (PORT clk (1123:1123:1123) (1148:1148:1148)) + (PORT clk (1113:1113:1113) (1138:1138:1138)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (773:773:773) (844:844:844)) + (PORT ena (769:769:769) (843:843:843)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -54561,9 +54272,9 @@ (INSTANCE ula_\|video_\|bits\[4\]) (DELAY (ABSOLUTE - (PORT clk (918:918:918) (922:922:922)) - (PORT asdata (535:535:535) (601:601:601)) - (PORT ena (747:747:747) (817:817:817)) + (PORT clk (917:917:917) (921:921:921)) + (PORT asdata (390:390:390) (445:445:445)) + (PORT ena (742:742:742) (808:808:808)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -54577,7 +54288,7 @@ (INSTANCE ula_\|video_\|bits_prefetch\[5\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (522:522:522) (600:600:600)) + (PORT datad (460:460:460) (520:520:520)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -54587,9 +54298,9 @@ (INSTANCE ula_\|video_\|bits_prefetch\[5\]) (DELAY (ABSOLUTE - (PORT clk (1123:1123:1123) (1148:1148:1148)) + (PORT clk (1113:1113:1113) (1138:1138:1138)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (773:773:773) (844:844:844)) + (PORT ena (769:769:769) (843:843:843)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -54603,7 +54314,7 @@ (INSTANCE ula_\|video_\|bits\[5\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (356:356:356) (420:420:420)) + (PORT datad (224:224:224) (281:281:281)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -54613,9 +54324,9 @@ (INSTANCE ula_\|video_\|bits\[5\]) (DELAY (ABSOLUTE - (PORT clk (918:918:918) (922:922:922)) + (PORT clk (917:917:917) (921:921:921)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (747:747:747) (817:817:817)) + (PORT ena (742:742:742) (808:808:808)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -54629,7 +54340,7 @@ (INSTANCE ula_\|video_\|bits_prefetch\[7\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (688:688:688) (785:785:785)) + (PORT datad (764:764:764) (865:865:865)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -54639,9 +54350,9 @@ (INSTANCE ula_\|video_\|bits_prefetch\[7\]) (DELAY (ABSOLUTE - (PORT clk (1123:1123:1123) (1148:1148:1148)) + (PORT clk (1113:1113:1113) (1138:1138:1138)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (773:773:773) (844:844:844)) + (PORT ena (769:769:769) (843:843:843)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -54655,9 +54366,9 @@ (INSTANCE ula_\|video_\|bits\[7\]) (DELAY (ABSOLUTE - (PORT clk (918:918:918) (922:922:922)) - (PORT asdata (648:648:648) (729:729:729)) - (PORT ena (747:747:747) (817:817:817)) + (PORT clk (917:917:917) (921:921:921)) + (PORT asdata (403:403:403) (462:462:462)) + (PORT ena (742:742:742) (808:808:808)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -54671,11 +54382,11 @@ (INSTANCE ula_\|video_\|Mux0\~0) (DELAY (ABSOLUTE - (PORT dataa (201:201:201) (262:262:262)) - (PORT datab (158:158:158) (212:212:212)) - (PORT datad (338:338:338) (401:401:401)) - (IOPATH dataa combout (166:166:166) (159:159:159)) - (IOPATH datab combout (167:167:167) (158:158:158)) + (PORT dataa (130:130:130) (181:181:181)) + (PORT datab (321:321:321) (392:392:392)) + (PORT datad (316:316:316) (381:381:381)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (190:190:190) (188:188:188)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -54686,11 +54397,11 @@ (INSTANCE ula_\|video_\|Mux0\~1) (DELAY (ABSOLUTE - (PORT dataa (131:131:131) (182:182:182)) - (PORT datab (155:155:155) (209:209:209)) - (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (190:190:190) (177:177:177)) + (PORT dataa (330:330:330) (404:404:404)) + (PORT datab (224:224:224) (288:288:288)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -54701,7 +54412,7 @@ (INSTANCE ula_\|video_\|bits_prefetch\[2\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (485:485:485) (555:555:555)) + (PORT datad (983:983:983) (1134:1134:1134)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -54711,9 +54422,9 @@ (INSTANCE ula_\|video_\|bits_prefetch\[2\]) (DELAY (ABSOLUTE - (PORT clk (1123:1123:1123) (1148:1148:1148)) + (PORT clk (1113:1113:1113) (1138:1138:1138)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (773:773:773) (844:844:844)) + (PORT ena (769:769:769) (843:843:843)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -54727,7 +54438,7 @@ (INSTANCE ula_\|video_\|bits\[2\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (350:350:350) (413:413:413)) + (PORT datad (312:312:312) (374:374:374)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -54737,9 +54448,9 @@ (INSTANCE ula_\|video_\|bits\[2\]) (DELAY (ABSOLUTE - (PORT clk (918:918:918) (922:922:922)) + (PORT clk (917:917:917) (921:921:921)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (747:747:747) (817:817:817)) + (PORT ena (742:742:742) (808:808:808)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -54753,7 +54464,7 @@ (INSTANCE ula_\|video_\|bits_prefetch\[0\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (800:800:800) (885:885:885)) + (PORT datad (844:844:844) (933:933:933)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -54763,9 +54474,9 @@ (INSTANCE ula_\|video_\|bits_prefetch\[0\]) (DELAY (ABSOLUTE - (PORT clk (1123:1123:1123) (1148:1148:1148)) + (PORT clk (1113:1113:1113) (1138:1138:1138)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (773:773:773) (844:844:844)) + (PORT ena (769:769:769) (843:843:843)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -54779,9 +54490,9 @@ (INSTANCE ula_\|video_\|bits\[0\]) (DELAY (ABSOLUTE - (PORT clk (918:918:918) (922:922:922)) - (PORT asdata (526:526:526) (585:585:585)) - (PORT ena (747:747:747) (817:817:817)) + (PORT clk (917:917:917) (921:921:921)) + (PORT asdata (777:777:777) (879:879:879)) + (PORT ena (742:742:742) (808:808:808)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -54795,7 +54506,7 @@ (INSTANCE ula_\|video_\|bits_prefetch\[1\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (821:821:821) (936:936:936)) + (PORT datad (478:478:478) (544:544:544)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -54805,9 +54516,9 @@ (INSTANCE ula_\|video_\|bits_prefetch\[1\]) (DELAY (ABSOLUTE - (PORT clk (1123:1123:1123) (1148:1148:1148)) + (PORT clk (1113:1113:1113) (1138:1138:1138)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (773:773:773) (844:844:844)) + (PORT ena (769:769:769) (843:843:843)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -54821,7 +54532,7 @@ (INSTANCE ula_\|video_\|bits\[1\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (347:347:347) (411:411:411)) + (PORT datad (218:218:218) (272:272:272)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -54831,9 +54542,9 @@ (INSTANCE ula_\|video_\|bits\[1\]) (DELAY (ABSOLUTE - (PORT clk (918:918:918) (922:922:922)) + (PORT clk (917:917:917) (921:921:921)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (747:747:747) (817:817:817)) + (PORT ena (742:742:742) (808:808:808)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -54847,7 +54558,7 @@ (INSTANCE ula_\|video_\|bits_prefetch\[3\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (687:687:687) (771:771:771)) + (PORT datad (787:787:787) (906:906:906)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -54857,9 +54568,9 @@ (INSTANCE ula_\|video_\|bits_prefetch\[3\]) (DELAY (ABSOLUTE - (PORT clk (1123:1123:1123) (1148:1148:1148)) + (PORT clk (1113:1113:1113) (1138:1138:1138)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (773:773:773) (844:844:844)) + (PORT ena (769:769:769) (843:843:843)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -54873,9 +54584,9 @@ (INSTANCE ula_\|video_\|bits\[3\]) (DELAY (ABSOLUTE - (PORT clk (918:918:918) (922:922:922)) - (PORT asdata (762:762:762) (848:848:848)) - (PORT ena (747:747:747) (817:817:817)) + (PORT clk (917:917:917) (921:921:921)) + (PORT asdata (391:391:391) (446:446:446)) + (PORT ena (742:742:742) (808:808:808)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -54889,9 +54600,9 @@ (INSTANCE ula_\|video_\|Mux0\~2) (DELAY (ABSOLUTE - (PORT dataa (130:130:130) (180:180:180)) - (PORT datab (155:155:155) (209:209:209)) - (PORT datad (335:335:335) (398:398:398)) + (PORT dataa (330:330:330) (404:404:404)) + (PORT datab (131:131:131) (180:180:180)) + (PORT datad (309:309:309) (371:371:371)) (IOPATH dataa combout (166:166:166) (159:159:159)) (IOPATH datab combout (167:167:167) (158:158:158)) (IOPATH datac combout (190:190:190) (195:195:195)) @@ -54904,11 +54615,11 @@ (INSTANCE ula_\|video_\|Mux0\~3) (DELAY (ABSOLUTE - (PORT dataa (130:130:130) (180:180:180)) - (PORT datab (157:157:157) (211:211:211)) + (PORT dataa (327:327:327) (400:400:400)) + (PORT datab (200:200:200) (257:257:257)) (PORT datad (92:92:92) (110:110:110)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (190:190:190) (177:177:177)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -54919,25 +54630,109 @@ (INSTANCE ula_\|video_\|cindex\[1\]\~0) (DELAY (ABSOLUTE - (PORT dataa (210:210:210) (268:268:268)) - (PORT datab (102:102:102) (131:131:131)) + (PORT dataa (103:103:103) (133:133:133)) + (PORT datab (337:337:337) (409:409:409)) (PORT datac (90:90:90) (112:112:112)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (181:181:181) (184:184:184)) - (IOPATH datab combout (192:192:192) (188:188:188)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (192:192:192) (184:184:184)) + (IOPATH datab combout (182:182:182) (188:188:188)) (IOPATH datac combout (120:120:120) (125:125:125)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|attr_prefetch\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1007:1007:1007) (1175:1175:1175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr_prefetch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1128:1128:1128) (1160:1160:1160)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (737:737:737) (794:794:794)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (917:917:917) (922:922:922)) + (PORT asdata (512:512:512) (581:581:581)) + (PORT ena (746:746:746) (816:816:816)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|attr_prefetch\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (480:480:480) (547:547:547)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr_prefetch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1128:1128:1128) (1160:1160:1160)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (737:737:737) (794:794:794)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (917:917:917) (922:922:922)) + (PORT asdata (835:835:835) (955:955:955)) + (PORT ena (746:746:746) (816:816:816)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|cindex\[1\]\~1) (DELAY (ABSOLUTE - (PORT dataa (131:131:131) (183:183:183)) - (PORT datad (179:179:179) (206:206:206)) - (IOPATH dataa combout (166:166:166) (163:163:163)) + (PORT dataa (194:194:194) (236:236:236)) + (PORT datad (118:118:118) (155:155:155)) + (IOPATH dataa combout (165:165:165) (173:173:173)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -54948,13 +54743,13 @@ (INSTANCE ula_\|video_\|VGA_R\[0\]\~0) (DELAY (ABSOLUTE - (PORT dataa (214:214:214) (266:266:266)) - (PORT datab (820:820:820) (958:958:958)) - (PORT datac (128:128:128) (155:155:155)) + (PORT dataa (1513:1513:1513) (1739:1739:1739)) + (PORT datab (190:190:190) (232:232:232)) + (PORT datac (302:302:302) (346:346:346)) (PORT datad (95:95:95) (114:114:114)) (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -54964,8 +54759,8 @@ (INSTANCE ula_\|video_\|attr_prefetch\[6\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (648:648:648) (736:736:736)) - (IOPATH datad combout (68:68:68) (63:63:63)) + (PORT datac (829:829:829) (958:958:958)) + (IOPATH datac combout (119:119:119) (124:124:124)) ) ) ) @@ -54974,9 +54769,9 @@ (INSTANCE ula_\|video_\|attr_prefetch\[6\]) (DELAY (ABSOLUTE - (PORT clk (1138:1138:1138) (1170:1170:1170)) + (PORT clk (1128:1128:1128) (1160:1160:1160)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (772:772:772) (840:840:840)) + (PORT ena (737:737:737) (794:794:794)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -54990,9 +54785,9 @@ (INSTANCE ula_\|video_\|attr\[6\]) (DELAY (ABSOLUTE - (PORT clk (914:914:914) (918:918:918)) - (PORT asdata (655:655:655) (731:731:731)) - (PORT ena (858:858:858) (937:937:937)) + (PORT clk (917:917:917) (922:922:922)) + (PORT asdata (518:518:518) (583:583:583)) + (PORT ena (746:746:746) (816:816:816)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -55006,9 +54801,9 @@ (INSTANCE ula_\|video_\|VGA_B\[1\]\~0) (DELAY (ABSOLUTE - (PORT dataa (114:114:114) (149:149:149)) - (PORT datab (110:110:110) (141:141:141)) - (PORT datad (179:179:179) (214:214:214)) + (PORT dataa (109:109:109) (141:141:141)) + (PORT datab (108:108:108) (138:138:138)) + (PORT datad (269:269:269) (307:307:307)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (167:167:167) (156:156:156)) (IOPATH datac combout (190:190:190) (195:195:195)) @@ -55021,11 +54816,11 @@ (INSTANCE ula_\|video_\|VGA_R\[1\]\~1) (DELAY (ABSOLUTE - (PORT dataa (147:147:147) (185:185:185)) - (PORT datac (207:207:207) (250:250:250)) - (PORT datad (94:94:94) (112:112:112)) - (IOPATH dataa combout (166:166:166) (163:163:163)) - (IOPATH datac combout (119:119:119) (124:124:124)) + (PORT dataa (684:684:684) (776:776:776)) + (PORT datab (117:117:117) (146:146:146)) + (PORT datad (95:95:95) (114:114:114)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -55035,51 +54830,9 @@ (INSTANCE ula_\|border\[2\]) (DELAY (ABSOLUTE - (PORT clk (907:907:907) (911:911:911)) - (PORT asdata (495:495:495) (538:538:538)) - (PORT ena (418:418:418) (434:434:434)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|attr_prefetch\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (486:486:486) (555:555:555)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr_prefetch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1138:1138:1138) (1170:1170:1170)) - (PORT d (37:37:37) (50:50:50)) - (PORT ena (772:772:772) (840:840:840)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (918:918:918) (922:922:922)) - (PORT asdata (641:641:641) (711:711:711)) - (PORT ena (747:747:747) (817:817:817)) + (PORT clk (904:904:904) (909:909:909)) + (PORT asdata (1027:1027:1027) (1129:1129:1129)) + (PORT ena (1011:1011:1011) (1119:1119:1119)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -55093,7 +54846,7 @@ (INSTANCE ula_\|video_\|attr_prefetch\[5\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (521:521:521) (599:599:599)) + (PORT datad (460:460:460) (521:521:521)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -55103,9 +54856,9 @@ (INSTANCE ula_\|video_\|attr_prefetch\[5\]) (DELAY (ABSOLUTE - (PORT clk (1138:1138:1138) (1170:1170:1170)) + (PORT clk (1128:1128:1128) (1160:1160:1160)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (772:772:772) (840:840:840)) + (PORT ena (737:737:737) (794:794:794)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -55119,9 +54872,51 @@ (INSTANCE ula_\|video_\|attr\[5\]) (DELAY (ABSOLUTE - (PORT clk (918:918:918) (922:922:922)) - (PORT asdata (528:528:528) (588:588:588)) - (PORT ena (747:747:747) (817:817:817)) + (PORT clk (917:917:917) (922:922:922)) + (PORT asdata (544:544:544) (622:622:622)) + (PORT ena (746:746:746) (816:816:816)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|attr_prefetch\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (985:985:985) (1135:1135:1135)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr_prefetch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1128:1128:1128) (1160:1160:1160)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (737:737:737) (794:794:794)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (917:917:917) (922:922:922)) + (PORT asdata (745:745:745) (838:838:838)) + (PORT ena (746:746:746) (816:816:816)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -55135,9 +54930,9 @@ (INSTANCE ula_\|video_\|cindex\[2\]\~2) (DELAY (ABSOLUTE - (PORT datab (130:130:130) (177:177:177)) - (PORT datad (106:106:106) (126:126:126)) - (IOPATH datab combout (167:167:167) (167:167:167)) + (PORT dataa (193:193:193) (235:235:235)) + (PORT datad (117:117:117) (153:153:153)) + (IOPATH dataa combout (165:165:165) (173:173:173)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -55148,10 +54943,10 @@ (INSTANCE ula_\|video_\|VGA_G\[0\]\~0) (DELAY (ABSOLUTE - (PORT dataa (1315:1315:1315) (1534:1534:1534)) - (PORT datab (221:221:221) (262:262:262)) - (PORT datac (203:203:203) (246:246:246)) - (PORT datad (294:294:294) (329:329:329)) + (PORT dataa (1521:1521:1521) (1742:1742:1742)) + (PORT datab (191:191:191) (233:233:233)) + (PORT datac (301:301:301) (345:345:345)) + (PORT datad (94:94:94) (112:112:112)) (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (167:167:167) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -55164,9 +54959,9 @@ (INSTANCE ula_\|video_\|VGA_G\[1\]\~1) (DELAY (ABSOLUTE - (PORT dataa (340:340:340) (400:400:400)) - (PORT datab (115:115:115) (144:144:144)) - (PORT datad (195:195:195) (224:224:224)) + (PORT dataa (432:432:432) (497:497:497)) + (PORT datab (191:191:191) (233:233:233)) + (PORT datad (94:94:94) (113:113:113)) (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -55178,9 +54973,9 @@ (INSTANCE ula_\|border\[0\]) (DELAY (ABSOLUTE - (PORT clk (911:911:911) (915:915:915)) - (PORT asdata (823:823:823) (908:908:908)) - (PORT ena (1148:1148:1148) (1270:1270:1270)) + (PORT clk (903:903:903) (907:907:907)) + (PORT asdata (1892:1892:1892) (2175:2175:2175)) + (PORT ena (1311:1311:1311) (1458:1458:1458)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -55194,7 +54989,7 @@ (INSTANCE ula_\|video_\|attr_prefetch\[0\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (799:799:799) (884:884:884)) + (PORT datad (846:846:846) (936:936:936)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -55204,9 +54999,9 @@ (INSTANCE ula_\|video_\|attr_prefetch\[0\]) (DELAY (ABSOLUTE - (PORT clk (1138:1138:1138) (1170:1170:1170)) + (PORT clk (1128:1128:1128) (1160:1160:1160)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (772:772:772) (840:840:840)) + (PORT ena (737:737:737) (794:794:794)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -55220,7 +55015,7 @@ (INSTANCE ula_\|video_\|attr\[0\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (455:455:455) (523:523:523)) + (PORT datad (336:336:336) (403:403:403)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -55232,7 +55027,7 @@ (ABSOLUTE (PORT clk (917:917:917) (921:921:921)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (745:745:745) (812:812:812)) + (PORT ena (742:742:742) (808:808:808)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -55246,7 +55041,7 @@ (INSTANCE ula_\|video_\|attr_prefetch\[3\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (687:687:687) (770:770:770)) + (PORT datad (787:787:787) (906:906:906)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -55256,9 +55051,9 @@ (INSTANCE ula_\|video_\|attr_prefetch\[3\]) (DELAY (ABSOLUTE - (PORT clk (1138:1138:1138) (1170:1170:1170)) + (PORT clk (1128:1128:1128) (1160:1160:1160)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (772:772:772) (840:840:840)) + (PORT ena (737:737:737) (794:794:794)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -55272,9 +55067,9 @@ (INSTANCE ula_\|video_\|attr\[3\]) (DELAY (ABSOLUTE - (PORT clk (918:918:918) (922:922:922)) - (PORT asdata (520:520:520) (583:583:583)) - (PORT ena (747:747:747) (817:817:817)) + (PORT clk (917:917:917) (921:921:921)) + (PORT asdata (406:406:406) (465:465:465)) + (PORT ena (742:742:742) (808:808:808)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) @@ -55288,9 +55083,9 @@ (INSTANCE ula_\|video_\|cindex\[0\]\~3) (DELAY (ABSOLUTE - (PORT datab (200:200:200) (258:258:258)) - (PORT datad (108:108:108) (127:127:127)) - (IOPATH datab combout (167:167:167) (167:167:167)) + (PORT dataa (130:130:130) (181:181:181)) + (PORT datad (102:102:102) (119:119:119)) + (IOPATH dataa combout (166:166:166) (163:163:163)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -55301,13 +55096,13 @@ (INSTANCE ula_\|video_\|VGA_B\[0\]\~1) (DELAY (ABSOLUTE - (PORT dataa (215:215:215) (267:267:267)) - (PORT datab (933:933:933) (1067:1067:1067)) - (PORT datac (128:128:128) (155:155:155)) - (PORT datad (170:170:170) (200:200:200)) - (IOPATH dataa combout (170:170:170) (163:163:163)) + (PORT dataa (307:307:307) (357:357:357)) + (PORT datab (1200:1200:1200) (1434:1434:1434)) + (PORT datac (163:163:163) (190:190:190)) + (PORT datad (93:93:93) (113:113:113)) + (IOPATH dataa combout (166:166:166) (157:157:157)) (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -55317,9 +55112,9 @@ (INSTANCE ula_\|video_\|VGA_B\[1\]\~2) (DELAY (ABSOLUTE - (PORT dataa (148:148:148) (185:185:185)) - (PORT datac (207:207:207) (250:250:250)) - (PORT datad (175:175:175) (206:206:206)) + (PORT dataa (305:305:305) (357:357:357)) + (PORT datac (295:295:295) (336:336:336)) + (PORT datad (95:95:95) (114:114:114)) (IOPATH dataa combout (166:166:166) (163:163:163)) (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -55331,11 +55126,11 @@ (INSTANCE ula_\|video_\|Equal0\~2) (DELAY (ABSOLUTE - (PORT dataa (364:364:364) (435:435:435)) - (PORT datab (154:154:154) (201:201:201)) - (PORT datad (346:346:346) (414:414:414)) - (IOPATH dataa combout (170:170:170) (163:163:163)) + (PORT datab (364:364:364) (443:443:443)) + (PORT datac (610:610:610) (718:718:718)) + (PORT datad (550:550:550) (652:652:652)) (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -55345,7 +55140,7 @@ (INSTANCE ula_\|video_\|VGA_HS\~_Duplicate_1) (DELAY (ABSOLUTE - (PORT clk (917:917:917) (921:921:921)) + (PORT clk (917:917:917) (922:922:922)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -55359,10 +55154,10 @@ (INSTANCE ula_\|video_\|Selector0\~0) (DELAY (ABSOLUTE - (PORT dataa (540:540:540) (616:616:616)) - (PORT datab (120:120:120) (151:151:151)) - (PORT datad (300:300:300) (346:346:346)) - (IOPATH dataa combout (166:166:166) (163:163:163)) + (PORT dataa (104:104:104) (134:134:134)) + (PORT datab (296:296:296) (346:346:346)) + (PORT datad (170:170:170) (201:201:201)) + (IOPATH dataa combout (170:170:170) (163:163:163)) (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) @@ -55375,7 +55170,7 @@ (DELAY (ABSOLUTE (PORT clk (893:893:893) (915:915:915)) - (PORT d (917:917:917) (975:975:975)) + (PORT d (946:946:946) (1008:1008:1008)) (IOPATH (posedge clk) q (329:329:329) (329:329:329)) ) ) @@ -55389,7 +55184,7 @@ (INSTANCE ula_\|video_\|VGA_VS\~_Duplicate_1) (DELAY (ABSOLUTE - (PORT clk (919:919:919) (923:923:923)) + (PORT clk (918:918:918) (923:923:923)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -55403,11 +55198,11 @@ (INSTANCE ula_\|video_\|Selector1\~0) (DELAY (ABSOLUTE - (PORT dataa (325:325:325) (380:380:380)) - (PORT datab (627:627:627) (727:727:727)) - (PORT datad (383:383:383) (452:452:452)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (167:167:167)) + (PORT dataa (582:582:582) (662:662:662)) + (PORT datab (771:771:771) (897:897:897)) + (PORT datad (599:599:599) (686:686:686)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -55419,7 +55214,7 @@ (DELAY (ABSOLUTE (PORT clk (892:892:892) (914:914:914)) - (PORT d (979:979:979) (1050:1050:1050)) + (PORT d (714:714:714) (752:752:752)) (IOPATH (posedge clk) q (329:329:329) (329:329:329)) ) ) @@ -55433,7 +55228,7 @@ (INSTANCE z80_\|memory_ifc_\|q1\~feeder) (DELAY (ABSOLUTE - (PORT datad (323:323:323) (383:383:383)) + (PORT datad (136:136:136) (177:177:177)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -55443,10 +55238,10 @@ (INSTANCE z80_\|memory_ifc_\|q1) (DELAY (ABSOLUTE - (PORT clk (918:918:918) (925:925:925)) + (PORT clk (908:908:908) (913:913:913)) (PORT d (37:37:37) (50:50:50)) - (PORT clrn (924:924:924) (906:906:906)) - (PORT ena (783:783:783) (862:862:862)) + (PORT clrn (909:909:909) (896:896:896)) + (PORT ena (892:892:892) (980:980:980)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -55461,10 +55256,10 @@ (INSTANCE z80_\|memory_ifc_\|q2) (DELAY (ABSOLUTE - (PORT clk (918:918:918) (925:925:925)) - (PORT asdata (296:296:296) (335:335:335)) - (PORT clrn (924:924:924) (906:906:906)) - (PORT ena (783:783:783) (862:862:862)) + (PORT clk (908:908:908) (913:913:913)) + (PORT asdata (294:294:294) (334:334:334)) + (PORT clrn (909:909:909) (896:896:896)) + (PORT ena (892:892:892) (980:980:980)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) ) @@ -55479,7 +55274,7 @@ (INSTANCE z80_\|memory_ifc_\|nRFSH_out\~0) (DELAY (ABSOLUTE - (PORT datad (326:326:326) (386:386:386)) + (PORT datad (137:137:137) (178:178:178)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -55490,9 +55285,9 @@ (INSTANCE z80_\|memory_ifc_\|nM1_out) (DELAY (ABSOLUTE - (PORT datac (730:730:730) (833:833:833)) - (PORT datad (326:326:326) (387:387:387)) - (IOPATH datac combout (120:120:120) (124:124:124)) + (PORT dataa (1409:1409:1409) (1666:1666:1666)) + (PORT datad (137:137:137) (177:177:177)) + (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -55502,11 +55297,11 @@ (INSTANCE ula_\|beep\~0) (DELAY (ABSOLUTE - (PORT datab (972:972:972) (1130:1130:1130)) - (PORT datac (1872:1872:1872) (2097:2097:2097)) - (PORT datad (705:705:705) (818:818:818)) - (IOPATH datab combout (196:196:196) (205:205:205)) - (IOPATH datac combout (120:120:120) (125:125:125)) + (PORT dataa (2220:2220:2220) (2549:2549:2549)) + (PORT datab (625:625:625) (719:719:719)) + (PORT datad (685:685:685) (773:773:773)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (196:196:196) (192:192:192)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) @@ -55516,9 +55311,9 @@ (INSTANCE ula_\|beep) (DELAY (ABSOLUTE - (PORT clk (902:902:902) (907:907:907)) + (PORT clk (898:898:898) (903:903:903)) (PORT d (37:37:37) (50:50:50)) - (PORT ena (1416:1416:1416) (1569:1569:1569)) + (PORT ena (1317:1317:1317) (1452:1452:1452)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) ) diff --git a/simulation/modelsim/spectrum_modelsim.xrf b/simulation/modelsim/spectrum_modelsim.xrf index a3e8bc9..9ee3b08 100644 --- a/simulation/modelsim/spectrum_modelsim.xrf +++ b/simulation/modelsim/spectrum_modelsim.xrf @@ -62,6 +62,7 @@ source_file = 1, /home/benny/work/fpga/spectrum/pll_video.v source_file = 1, /home/benny/work/fpga/spectrum/spectrum.sdc source_file = 1, /home/benny/work/fpga/spectrum/ram_video.qip source_file = 1, /home/benny/work/fpga/spectrum/ram_video.v +source_file = 1, /home/benny/work/fpga/spectrum/output_files/spectrum.cdf source_file = 1, /home/benny/work/fpga/spectrum/db/spectrum.cbx.xml source_file = 1, /home/benny/work/fpga/spectrum/cpu/toplevel/globals.vh source_file = 1, /home/benny/work/fpga/spectrum/cpu/toplevel/coremodules.vh @@ -174,830 +175,93 @@ instance = comp, \SW[2]~input , SW[2]~input, spectrum, 1 instance = comp, \ula_|clocks_|clk_cpu~0 , ula_|clocks_|clk_cpu~0, spectrum, 1 instance = comp, \ula_|clocks_|clk_cpu , ula_|clocks_|clk_cpu, spectrum, 1 instance = comp, \ula_|clocks_|clk_cpu~clkctrl , ula_|clocks_|clk_cpu~clkctrl, spectrum, 1 -instance = comp, \z80_|sequencer_|DFFE_M1_ff~0 , z80_|sequencer_|DFFE_M1_ff~0, spectrum, 1 -instance = comp, \z80_|sequencer_|ena_M , z80_|sequencer_|ena_M, spectrum, 1 +instance = comp, \z80_|sequencer_|SYNTHESIZED_WIRE_15 , z80_|sequencer_|SYNTHESIZED_WIRE_15, spectrum, 1 +instance = comp, \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl , z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl, spectrum, 1 instance = comp, \KEY[1]~input , KEY[1]~input, spectrum, 1 instance = comp, \z80_|interrupts_|nmi_armed~feeder , z80_|interrupts_|nmi_armed~feeder, spectrum, 1 instance = comp, \z80_|interrupts_|SYNTHESIZED_WIRE_9 , z80_|interrupts_|SYNTHESIZED_WIRE_9, spectrum, 1 instance = comp, \z80_|interrupts_|nmi_armed , z80_|interrupts_|nmi_armed, spectrum, 1 instance = comp, \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder , z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder, spectrum, 1 -instance = comp, \z80_|execute_|ctl_eval_cond~0 , z80_|execute_|ctl_eval_cond~0, spectrum, 1 -instance = comp, \z80_|execute_|ixy_d~4 , z80_|execute_|ixy_d~4, spectrum, 1 +instance = comp, \z80_|sequencer_|DFFE_M2_ff~0 , z80_|sequencer_|DFFE_M2_ff~0, spectrum, 1 +instance = comp, \z80_|sequencer_|DFFE_M2_ff , z80_|sequencer_|DFFE_M2_ff, spectrum, 1 instance = comp, \z80_|sequencer_|DFFE_M3_ff~0 , z80_|sequencer_|DFFE_M3_ff~0, spectrum, 1 instance = comp, \z80_|sequencer_|DFFE_M3_ff , z80_|sequencer_|DFFE_M3_ff, spectrum, 1 -instance = comp, \z80_|execute_|fIOWrite~1 , z80_|execute_|fIOWrite~1, spectrum, 1 instance = comp, \z80_|sequencer_|DFFE_M4_ff~0 , z80_|sequencer_|DFFE_M4_ff~0, spectrum, 1 instance = comp, \z80_|sequencer_|DFFE_M4_ff , z80_|sequencer_|DFFE_M4_ff, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal32~0 , z80_|pla_decode_|Equal32~0, spectrum, 1 -instance = comp, \z80_|resets_|SYNTHESIZED_WIRE_11 , z80_|resets_|SYNTHESIZED_WIRE_11, spectrum, 1 -instance = comp, \z80_|decode_state_|table_xx~0 , z80_|decode_state_|table_xx~0, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal1~7 , z80_|pla_decode_|Equal1~7, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal2~0 , z80_|pla_decode_|Equal2~0, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal36~0 , z80_|pla_decode_|Equal36~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_state_tbl_cb_set , z80_|execute_|ctl_state_tbl_cb_set, spectrum, 1 -instance = comp, \z80_|execute_|ctl_state_tbl_we~8 , z80_|execute_|ctl_state_tbl_we~8, spectrum, 1 -instance = comp, \z80_|decode_state_|DFFE_instCB , z80_|decode_state_|DFFE_instCB, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal52~0 , z80_|pla_decode_|Equal52~0, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal2~1 , z80_|pla_decode_|Equal2~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_state_tbl_ed_set , z80_|execute_|ctl_state_tbl_ed_set, spectrum, 1 -instance = comp, \z80_|decode_state_|DFFE_instED , z80_|decode_state_|DFFE_instED, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal13~0 , z80_|pla_decode_|Equal13~0, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal33~0 , z80_|pla_decode_|Equal33~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_im_we , z80_|execute_|ctl_im_we, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal49~0 , z80_|pla_decode_|Equal49~0, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal33~1 , z80_|pla_decode_|Equal33~1, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal6~0 , z80_|pla_decode_|Equal6~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~14 , z80_|execute_|ctl_mRead~14, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal12~0 , z80_|pla_decode_|Equal12~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_1d~8 , z80_|execute_|ctl_sw_1d~8, spectrum, 1 -instance = comp, \z80_|nM1_int~2 , z80_|nM1_int~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_1d~5 , z80_|execute_|ctl_sw_1d~5, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal3~0 , z80_|pla_decode_|Equal3~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~4 , z80_|execute_|ctl_mRead~4, spectrum, 1 -instance = comp, \z80_|execute_|ixy_d~7 , z80_|execute_|ixy_d~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_state_alu~4 , z80_|execute_|ctl_state_alu~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_1d~4 , z80_|execute_|ctl_sw_1d~4, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal40~1 , z80_|pla_decode_|Equal40~1, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal39~0 , z80_|pla_decode_|Equal39~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_db_oe~1 , z80_|execute_|ctl_bus_db_oe~1, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal13~1 , z80_|pla_decode_|Equal13~1, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal13~2 , z80_|pla_decode_|Equal13~2, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal3~2 , z80_|pla_decode_|Equal3~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_state_iy_set~2 , z80_|execute_|ctl_state_iy_set~2, spectrum, 1 -instance = comp, \z80_|execute_|ixy_d~8 , z80_|execute_|ixy_d~8, spectrum, 1 -instance = comp, \z80_|execute_|ixy_d~6 , z80_|execute_|ixy_d~6, spectrum, 1 -instance = comp, \z80_|execute_|ixy_d~9 , z80_|execute_|ixy_d~9, spectrum, 1 -instance = comp, \z80_|execute_|ixy_d~12 , z80_|execute_|ixy_d~12, spectrum, 1 -instance = comp, \z80_|execute_|ixy_d~10 , z80_|execute_|ixy_d~10, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal44~0 , z80_|pla_decode_|Equal44~0, spectrum, 1 -instance = comp, \z80_|execute_|ixy_d~16 , z80_|execute_|ixy_d~16, spectrum, 1 -instance = comp, \z80_|execute_|ixy_d~13 , z80_|execute_|ixy_d~13, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal50~0 , z80_|pla_decode_|Equal50~0, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal33~2 , z80_|pla_decode_|Equal33~2, spectrum, 1 -instance = comp, \z80_|execute_|ixy_d~17 , z80_|execute_|ixy_d~17, spectrum, 1 -instance = comp, \z80_|execute_|ixy_d~5 , z80_|execute_|ixy_d~5, spectrum, 1 -instance = comp, \z80_|execute_|ixy_d~14 , z80_|execute_|ixy_d~14, spectrum, 1 -instance = comp, \z80_|execute_|ixy_d~11 , z80_|execute_|ixy_d~11, spectrum, 1 -instance = comp, \z80_|execute_|ixy_d~15 , z80_|execute_|ixy_d~15, spectrum, 1 -instance = comp, \z80_|execute_|ctl_state_ixiy_we~2 , z80_|execute_|ctl_state_ixiy_we~2, spectrum, 1 -instance = comp, \z80_|decode_state_|DFFE_instIY1 , z80_|decode_state_|DFFE_instIY1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_ir_we~5 , z80_|execute_|ctl_ir_we~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_ir_we~14 , z80_|execute_|ctl_ir_we~14, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mWrite~2 , z80_|execute_|ctl_mWrite~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mWrite~16 , z80_|execute_|ctl_mWrite~16, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_alu~18 , z80_|execute_|ctl_flags_alu~18, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~26 , z80_|execute_|ctl_mRead~26, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~27 , z80_|execute_|ctl_mRead~27, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_db_oe~7 , z80_|execute_|ctl_bus_db_oe~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_2d~5 , z80_|execute_|ctl_sw_2d~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~18 , z80_|execute_|ctl_mRead~18, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal55~0 , z80_|pla_decode_|Equal55~0, spectrum, 1 -instance = comp, \z80_|execute_|comb~1 , z80_|execute_|comb~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~15 , z80_|execute_|ctl_mRead~15, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~17 , z80_|execute_|ctl_mRead~17, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_in_hi~5 , z80_|execute_|ctl_reg_in_hi~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~9 , z80_|execute_|ctl_mRead~9, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal9~0 , z80_|pla_decode_|Equal9~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~10 , z80_|execute_|ctl_mRead~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~8 , z80_|execute_|ctl_mRead~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~20 , z80_|execute_|ctl_mRead~20, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal12~1 , z80_|pla_decode_|Equal12~1, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal9~1 , z80_|pla_decode_|Equal9~1, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal25~0 , z80_|pla_decode_|Equal25~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~21 , z80_|execute_|ctl_mRead~21, spectrum, 1 -instance = comp, \z80_|execute_|ctl_state_alu~6 , z80_|execute_|ctl_state_alu~6, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal19~0 , z80_|pla_decode_|Equal19~0, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal1~4 , z80_|pla_decode_|Equal1~4, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal29~0 , z80_|pla_decode_|Equal29~0, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal24~1 , z80_|pla_decode_|Equal24~1, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal34~0 , z80_|pla_decode_|Equal34~0, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal37~0 , z80_|pla_decode_|Equal37~0, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal35~0 , z80_|pla_decode_|Equal35~0, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal38~2 , z80_|pla_decode_|Equal38~2, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sys_we_lo~2 , z80_|reg_control_|reg_sys_we_lo~2, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sys_we_lo~3 , z80_|reg_control_|reg_sys_we_lo~3, spectrum, 1 -instance = comp, \z80_|execute_|comb~0 , z80_|execute_|comb~0, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal47~0 , z80_|pla_decode_|Equal47~0, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sys_we_lo~4 , z80_|reg_control_|reg_sys_we_lo~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~22 , z80_|execute_|ctl_mRead~22, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~24 , z80_|execute_|ctl_mRead~24, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 , z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_in_hi~6 , z80_|execute_|ctl_reg_in_hi~6, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal6~1 , z80_|pla_decode_|Equal6~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~16 , z80_|execute_|ctl_mRead~16, spectrum, 1 instance = comp, \z80_|sequencer_|M5~0 , z80_|sequencer_|M5~0, spectrum, 1 instance = comp, \z80_|sequencer_|M5 , z80_|sequencer_|M5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_in_hi~2 , z80_|execute_|ctl_reg_in_hi~2, spectrum, 1 -instance = comp, \z80_|execute_|setM1~29 , z80_|execute_|setM1~29, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~25 , z80_|execute_|ctl_mRead~25, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~6 , z80_|execute_|ctl_reg_gp_sel[0]~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_ir_we~7 , z80_|execute_|ctl_ir_we~7, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal52~1 , z80_|pla_decode_|Equal52~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_state_alu~14 , z80_|execute_|ctl_state_alu~14, spectrum, 1 -instance = comp, \z80_|execute_|ctl_state_alu~8 , z80_|execute_|ctl_state_alu~8, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal24~0 , z80_|pla_decode_|Equal24~0, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sel_pc~0 , z80_|reg_control_|reg_sel_pc~0, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sel_pc~1 , z80_|reg_control_|reg_sel_pc~1, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sel_pc~2 , z80_|reg_control_|reg_sel_pc~2, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~17 , z80_|execute_|fMRead~17, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~6 , z80_|execute_|ctl_mRead~6, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal11~0 , z80_|pla_decode_|Equal11~0, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal10~0 , z80_|pla_decode_|Equal10~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op2_sel_bus~9 , z80_|execute_|ctl_alu_op2_sel_bus~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_2d~4 , z80_|execute_|ctl_sw_2d~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_ir_we~15 , z80_|execute_|ctl_ir_we~15, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~16 , z80_|execute_|fMRead~16, spectrum, 1 -instance = comp, \z80_|execute_|ctl_ir_we~9 , z80_|execute_|ctl_ir_we~9, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal46~0 , z80_|pla_decode_|Equal46~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_ir_we~10 , z80_|execute_|ctl_ir_we~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_alu~17 , z80_|execute_|ctl_flags_alu~17, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_alu~6 , z80_|execute_|ctl_flags_alu~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_ir_we~6 , z80_|execute_|ctl_ir_we~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_ir_we~8 , z80_|execute_|ctl_ir_we~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_alu~16 , z80_|execute_|ctl_flags_alu~16, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_in_hi~3 , z80_|execute_|ctl_reg_in_hi~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mWrite~8 , z80_|execute_|ctl_mWrite~8, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~18 , z80_|execute_|fMRead~18, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~19 , z80_|execute_|fMRead~19, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~16 , z80_|execute_|ctl_alu_shift_oe~16, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~36 , z80_|execute_|ctl_mRead~36, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~9 , z80_|execute_|ctl_alu_op_low~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~44 , z80_|execute_|ctl_alu_shift_oe~44, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~11 , z80_|execute_|ctl_mRead~11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_2d~6 , z80_|execute_|ctl_sw_2d~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_2d~7 , z80_|execute_|ctl_sw_2d~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mWrite~7 , z80_|execute_|ctl_mWrite~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_ir_we~11 , z80_|execute_|ctl_ir_we~11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_ir_we~12 , z80_|execute_|ctl_ir_we~12, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_sz_we~0 , z80_|execute_|ctl_flags_sz_we~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 , z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_2d~8 , z80_|execute_|ctl_sw_2d~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_2d~9 , z80_|execute_|ctl_sw_2d~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_1d~6 , z80_|execute_|ctl_sw_1d~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_1d~7 , z80_|execute_|ctl_sw_1d~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~8 , z80_|execute_|ctl_alu_op_low~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 , z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 , z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~39 , z80_|execute_|ctl_reg_gp_hilo[1]~39, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 , z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_out_hi~4 , z80_|execute_|ctl_reg_out_hi~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~15 , z80_|execute_|ctl_alu_shift_oe~15, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~38 , z80_|execute_|ctl_alu_shift_oe~38, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op2_sel_zero , z80_|execute_|ctl_alu_op2_sel_zero, spectrum, 1 -instance = comp, \z80_|alu_|db_low[2]~4 , z80_|alu_|db_low[2]~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~14 , z80_|execute_|ctl_alu_shift_oe~14, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[0]~11 , z80_|execute_|ctl_reg_sys_hilo[0]~11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_4u~1 , z80_|execute_|ctl_sw_4u~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~5 , z80_|execute_|ctl_alu_sel_op2_neg~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~30 , z80_|execute_|ctl_alu_shift_oe~30, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~29 , z80_|execute_|ctl_alu_shift_oe~29, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~31 , z80_|execute_|ctl_alu_shift_oe~31, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal69~0 , z80_|pla_decode_|Equal69~0, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal1~5 , z80_|pla_decode_|Equal1~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~14 , z80_|execute_|ctl_alu_op_low~14, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~12 , z80_|execute_|ctl_alu_op_low~12, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal56~0 , z80_|pla_decode_|Equal56~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~11 , z80_|execute_|ctl_alu_op_low~11, spectrum, 1 -instance = comp, \z80_|execute_|nextM~2 , z80_|execute_|nextM~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~16 , z80_|execute_|ctl_alu_op1_sel_bus~16, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~4 , z80_|execute_|ctl_alu_op1_sel_bus~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~5 , z80_|execute_|ctl_alu_op1_sel_bus~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_oe~3 , z80_|execute_|ctl_alu_oe~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~15 , z80_|execute_|ctl_alu_op_low~15, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~8 , z80_|execute_|ctl_alu_op1_sel_bus~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~9 , z80_|execute_|ctl_alu_op1_sel_bus~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_R~3 , z80_|execute_|ctl_alu_core_R~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_R~4 , z80_|execute_|ctl_alu_core_R~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 , z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~10 , z80_|execute_|ctl_alu_op1_sel_bus~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~11 , z80_|execute_|ctl_alu_op1_sel_bus~11, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal48~0 , z80_|pla_decode_|Equal48~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_hf2_we , z80_|execute_|ctl_flags_hf2_we, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~41 , z80_|execute_|ctl_alu_shift_oe~41, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_xy_we~18 , z80_|execute_|ctl_flags_xy_we~18, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~17 , z80_|execute_|ctl_alu_shift_oe~17, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~19 , z80_|execute_|ctl_alu_shift_oe~19, spectrum, 1 -instance = comp, \z80_|execute_|ctl_iorw~10 , z80_|execute_|ctl_iorw~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~18 , z80_|execute_|ctl_alu_shift_oe~18, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~20 , z80_|execute_|ctl_alu_shift_oe~20, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_bs_oe~13 , z80_|execute_|ctl_alu_bs_oe~13, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_bs_oe~9 , z80_|execute_|ctl_alu_bs_oe~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_db_oe~3 , z80_|execute_|ctl_bus_db_oe~3, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal20~0 , z80_|pla_decode_|Equal20~0, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal68~2 , z80_|pla_decode_|Equal68~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_bus~14 , z80_|execute_|ctl_flags_bus~14, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~13 , z80_|execute_|ctl_alu_op_low~13, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_bus~15 , z80_|execute_|ctl_flags_bus~15, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_bus~11 , z80_|execute_|ctl_flags_bus~11, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_nf~11 , z80_|alu_flags_|DFFE_inst_latch_nf~11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_bus~10 , z80_|execute_|ctl_flags_bus~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_bus~8 , z80_|execute_|ctl_flags_bus~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_bus~9 , z80_|execute_|ctl_flags_bus~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_bus~12 , z80_|execute_|ctl_flags_bus~12, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_xy_we~11 , z80_|execute_|ctl_flags_xy_we~11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_xy_we~12 , z80_|execute_|ctl_flags_xy_we~12, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~6 , z80_|execute_|ctl_alu_op1_sel_bus~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~7 , z80_|execute_|ctl_alu_op1_sel_bus~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_ir_we~4 , z80_|execute_|ctl_ir_we~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_bs_oe~8 , z80_|execute_|ctl_alu_bs_oe~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_db_oe~0 , z80_|execute_|ctl_bus_db_oe~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~12 , z80_|execute_|ctl_alu_op1_sel_bus~12, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~13 , z80_|execute_|ctl_alu_op1_sel_bus~13, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~14 , z80_|execute_|ctl_alu_op1_sel_bus~14, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~15 , z80_|execute_|ctl_alu_op1_sel_bus~15, spectrum, 1 -instance = comp, \z80_|execute_|ctl_66_oe~2 , z80_|execute_|ctl_66_oe~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_pf_sel_pla11M1T1_11 , z80_|execute_|ctl_pf_sel_pla11M1T1_11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op1_sel_zero~5 , z80_|execute_|ctl_alu_op1_sel_zero~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op1_sel_zero~4 , z80_|execute_|ctl_alu_op1_sel_zero~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op1_sel_zero , z80_|execute_|ctl_alu_op1_sel_zero, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op1_latch_mux_high|Q[2] , z80_|alu_|b2v_op1_latch_mux_high|Q[2], spectrum, 1 -instance = comp, \z80_|alu_|b2v_op1_latch_mux_high|ena~0 , z80_|alu_|b2v_op1_latch_mux_high|ena~0, spectrum, 1 -instance = comp, \z80_|alu_|op1_high[2] , z80_|alu_|op1_high[2], spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op2_sel_lq , z80_|execute_|ctl_alu_op2_sel_lq, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~10 , z80_|execute_|ctl_alu_op_low~10, spectrum, 1 -instance = comp, \z80_|execute_|fMWrite~11 , z80_|execute_|fMWrite~11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~21 , z80_|execute_|ctl_alu_op_low~21, spectrum, 1 +instance = comp, \z80_|execute_|ixy_d~5 , z80_|execute_|ixy_d~5, spectrum, 1 instance = comp, \z80_|execute_|ctl_alu_op_low~22 , z80_|execute_|ctl_alu_op_low~22, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~16 , z80_|execute_|ctl_alu_op_low~16, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~17 , z80_|execute_|ctl_alu_op_low~17, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 , z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel~36 , z80_|execute_|ctl_reg_gp_sel~36, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op2_sel_bus~4 , z80_|execute_|ctl_alu_op2_sel_bus~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_state_alu~5 , z80_|execute_|ctl_state_alu~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~18 , z80_|execute_|ctl_alu_op_low~18, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~19 , z80_|execute_|ctl_alu_op_low~19, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~33 , z80_|execute_|ctl_alu_op_low~33, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~20 , z80_|execute_|ctl_alu_op_low~20, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~23 , z80_|execute_|ctl_alu_op_low~23, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~24 , z80_|execute_|ctl_alu_op_low~24, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~25 , z80_|execute_|ctl_alu_op_low~25, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~34 , z80_|execute_|ctl_alu_op_low~34, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low , z80_|execute_|ctl_alu_op_low, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~40 , z80_|execute_|ctl_alu_shift_oe~40, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~37 , z80_|execute_|ctl_alu_shift_oe~37, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~39 , z80_|execute_|ctl_alu_shift_oe~39, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~46 , z80_|execute_|ctl_alu_shift_oe~46, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~42 , z80_|execute_|ctl_alu_shift_oe~42, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~21 , z80_|execute_|ctl_alu_shift_oe~21, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~45 , z80_|execute_|ctl_alu_shift_oe~45, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~22 , z80_|execute_|ctl_alu_shift_oe~22, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~23 , z80_|execute_|ctl_alu_shift_oe~23, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~24 , z80_|execute_|ctl_alu_shift_oe~24, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~25 , z80_|execute_|ctl_alu_shift_oe~25, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_bs_oe~14 , z80_|execute_|ctl_alu_bs_oe~14, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~26 , z80_|execute_|ctl_alu_shift_oe~26, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~27 , z80_|execute_|ctl_alu_shift_oe~27, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~28 , z80_|execute_|ctl_alu_shift_oe~28, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_bs_oe~10 , z80_|execute_|ctl_alu_bs_oe~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_bs_oe~11 , z80_|execute_|ctl_alu_bs_oe~11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~32 , z80_|execute_|ctl_alu_shift_oe~32, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~33 , z80_|execute_|ctl_alu_shift_oe~33, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_use_sp~0 , z80_|execute_|ctl_reg_use_sp~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_use_sp~1 , z80_|execute_|ctl_reg_use_sp~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_bs_oe~12 , z80_|execute_|ctl_alu_bs_oe~12, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~47 , z80_|execute_|ctl_alu_shift_oe~47, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~34 , z80_|execute_|ctl_alu_shift_oe~34, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~35 , z80_|execute_|ctl_alu_shift_oe~35, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~36 , z80_|execute_|ctl_alu_shift_oe~36, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_shift_oe~43 , z80_|execute_|ctl_alu_shift_oe~43, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_in_lo~9 , z80_|execute_|ctl_reg_in_lo~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op1_oe~0 , z80_|execute_|ctl_alu_op1_oe~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 , z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op1_oe~1 , z80_|execute_|ctl_alu_op1_oe~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_xy_we~8 , z80_|execute_|ctl_flags_xy_we~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_xy_we~9 , z80_|execute_|ctl_flags_xy_we~9, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal8~0 , z80_|pla_decode_|Equal8~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_alu~9 , z80_|execute_|ctl_flags_alu~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~4 , z80_|execute_|ctl_alu_sel_op2_neg~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_sz_we~3 , z80_|execute_|ctl_flags_sz_we~3, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal11~1 , z80_|pla_decode_|Equal11~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 , z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_alu~10 , z80_|execute_|ctl_flags_alu~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_alu~11 , z80_|execute_|ctl_flags_alu~11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 , z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_pf_sel_pla82M1T1_16 , z80_|execute_|ctl_pf_sel_pla82M1T1_16, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_use_cf2~13 , z80_|execute_|ctl_flags_use_cf2~13, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf_we~7 , z80_|execute_|ctl_flags_cf_we~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_pf_sel[0]~2 , z80_|execute_|ctl_pf_sel[0]~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_oe~2 , z80_|execute_|ctl_alu_oe~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~25 , z80_|execute_|ctl_bus_inc_oe~25, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_hf_we~5 , z80_|execute_|ctl_flags_hf_we~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_pf_we~10 , z80_|execute_|ctl_flags_pf_we~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~48 , z80_|execute_|ctl_reg_gp_hilo[1]~48, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_pf_we~2 , z80_|execute_|ctl_flags_pf_we~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_pf_we~3 , z80_|execute_|ctl_flags_pf_we~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_xy_we~17 , z80_|execute_|ctl_flags_xy_we~17, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sys_we_lo~5 , z80_|reg_control_|reg_sys_we_lo~5, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sys_we_lo~6 , z80_|reg_control_|reg_sys_we_lo~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_xy_we~10 , z80_|execute_|ctl_flags_xy_we~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 , z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_state_alu~7 , z80_|execute_|ctl_state_alu~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_sz_we~1 , z80_|execute_|ctl_flags_sz_we~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf_we~2 , z80_|execute_|ctl_flags_cf_we~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_S~6 , z80_|execute_|ctl_alu_core_S~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_S~7 , z80_|execute_|ctl_alu_core_S~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_S~4 , z80_|execute_|ctl_alu_core_S~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_S~5 , z80_|execute_|ctl_alu_core_S~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5 , z80_|execute_|ctl_reg_gp_hilo_pla91pla20M1T5_5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_res_oe~0 , z80_|execute_|ctl_alu_res_oe~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_oe~15 , z80_|execute_|ctl_alu_oe~15, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_res_oe~1 , z80_|execute_|ctl_alu_res_oe~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_res_oe~2 , z80_|execute_|ctl_alu_res_oe~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op2_oe~0 , z80_|execute_|ctl_alu_op2_oe~0, spectrum, 1 -instance = comp, \z80_|alu_|db_high[3]~2 , z80_|alu_|db_high[3]~2, spectrum, 1 -instance = comp, \z80_|alu_|db_high[3]~3 , z80_|alu_|db_high[3]~3, spectrum, 1 -instance = comp, \z80_|alu_|db_low[2]~24 , z80_|alu_|db_low[2]~24, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sys_we_lo~7 , z80_|reg_control_|reg_sys_we_lo~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 , z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~19 , z80_|execute_|ctl_reg_gp_hilo[1]~19, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_in_hi~8 , z80_|execute_|ctl_reg_in_hi~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_oe~8 , z80_|execute_|ctl_alu_oe~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_oe~4 , z80_|execute_|ctl_alu_oe~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mWrite~9 , z80_|execute_|ctl_mWrite~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_S~10 , z80_|execute_|ctl_alu_core_S~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~43 , z80_|execute_|ctl_bus_inc_oe~43, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~26 , z80_|execute_|ctl_bus_inc_oe~26, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_db_we~5 , z80_|execute_|ctl_bus_db_we~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_oe~9 , z80_|execute_|ctl_alu_oe~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_oe~11 , z80_|execute_|ctl_alu_oe~11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_oe~5 , z80_|execute_|ctl_alu_oe~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_S~11 , z80_|execute_|ctl_alu_core_S~11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_oe~6 , z80_|execute_|ctl_alu_oe~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_oe~7 , z80_|execute_|ctl_alu_oe~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_oe~12 , z80_|execute_|ctl_alu_oe~12, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_oe~13 , z80_|execute_|ctl_alu_oe~13, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_oe~14 , z80_|execute_|ctl_alu_oe~14, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~24 , z80_|execute_|ctl_reg_gp_sel[0]~24, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~27 , z80_|execute_|ctl_reg_gp_sel[0]~27, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~40 , z80_|execute_|ctl_reg_gp_hilo[1]~40, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~53 , z80_|execute_|ctl_reg_gp_hilo[1]~53, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_out_hi~8 , z80_|execute_|ctl_reg_out_hi~8, spectrum, 1 -instance = comp, \z80_|execute_|setM1~54 , z80_|execute_|setM1~54, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_2u~1 , z80_|execute_|ctl_sw_2u~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_2u~4 , z80_|execute_|ctl_sw_2u~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_2u~5 , z80_|execute_|ctl_sw_2u~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_2u~6 , z80_|execute_|ctl_sw_2u~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~35 , z80_|execute_|ctl_inc_cy~35, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~35 , z80_|execute_|ctl_reg_sys_hilo[1]~35, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mWrite~6 , z80_|execute_|ctl_mWrite~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_2u~2 , z80_|execute_|ctl_sw_2u~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_2u~0 , z80_|execute_|ctl_sw_2u~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_2u~3 , z80_|execute_|ctl_sw_2u~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~52 , z80_|execute_|ctl_reg_gp_hilo[1]~52, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 , z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_out_lo~2 , z80_|execute_|ctl_reg_out_lo~2, spectrum, 1 -instance = comp, \z80_|execute_|rsel3 , z80_|execute_|rsel3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_out_hi~5 , z80_|execute_|ctl_reg_out_hi~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_out_hi~6 , z80_|execute_|ctl_reg_out_hi~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_out_hi~7 , z80_|execute_|ctl_reg_out_hi~7, spectrum, 1 -instance = comp, \z80_|execute_|rsel0 , z80_|execute_|rsel0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 , z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~33 , z80_|execute_|ctl_reg_gp_hilo[0]~33, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_out_lo~6 , z80_|execute_|ctl_reg_out_lo~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_out_lo~7 , z80_|execute_|ctl_reg_out_lo~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_iorw~11 , z80_|execute_|ctl_iorw~11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_2d~10 , z80_|execute_|ctl_sw_2d~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_2d~14 , z80_|execute_|ctl_sw_2d~14, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_2d~11 , z80_|execute_|ctl_sw_2d~11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_2d~12 , z80_|execute_|ctl_sw_2d~12, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_2d~13 , z80_|execute_|ctl_sw_2d~13, spectrum, 1 -instance = comp, \z80_|execute_|ctl_66_oe , z80_|execute_|ctl_66_oe, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~34 , z80_|execute_|ctl_inc_cy~34, spectrum, 1 -instance = comp, \z80_|execute_|ctl_apin_mux~0 , z80_|execute_|ctl_apin_mux~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_4u~5 , z80_|execute_|ctl_sw_4u~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~75 , z80_|execute_|ctl_inc_cy~75, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~76 , z80_|execute_|ctl_inc_cy~76, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal4~0 , z80_|pla_decode_|Equal4~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~48 , z80_|execute_|ctl_bus_inc_oe~48, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~46 , z80_|execute_|ctl_bus_inc_oe~46, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~53 , z80_|execute_|ctl_inc_cy~53, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~92 , z80_|execute_|ctl_inc_cy~92, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal19~1 , z80_|pla_decode_|Equal19~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_4u~0 , z80_|execute_|ctl_sw_4u~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~38 , z80_|execute_|ctl_inc_cy~38, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~93 , z80_|execute_|ctl_inc_cy~93, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~39 , z80_|execute_|ctl_inc_cy~39, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~24 , z80_|execute_|ctl_bus_inc_oe~24, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_we~1 , z80_|execute_|ctl_reg_gp_we~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 , z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~44 , z80_|execute_|ctl_bus_inc_oe~44, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~5 , z80_|execute_|ctl_reg_gp_sel[1]~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_we~0 , z80_|execute_|ctl_reg_gp_we~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 , z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~35 , z80_|execute_|ctl_reg_gp_hilo[1]~35, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_4u~2 , z80_|execute_|ctl_sw_4u~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_4u~3 , z80_|execute_|ctl_sw_4u~3, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~3 , z80_|execute_|fMRead~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_4u~4 , z80_|execute_|ctl_sw_4u~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 , z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_wz~15 , z80_|execute_|ctl_reg_sel_wz~15, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~8 , z80_|execute_|ctl_reg_sys_hilo[1]~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~94 , z80_|execute_|ctl_inc_cy~94, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~87 , z80_|execute_|ctl_inc_cy~87, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~42 , z80_|execute_|ctl_inc_cy~42, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~34 , z80_|execute_|ctl_reg_sys_hilo[1]~34, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_wz~16 , z80_|execute_|ctl_reg_sel_wz~16, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_4u~6 , z80_|execute_|ctl_sw_4u~6, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal2~2 , z80_|pla_decode_|Equal2~2, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal1~6 , z80_|pla_decode_|Equal1~6, spectrum, 1 -instance = comp, \z80_|reg_control_|bank_exx~2 , z80_|reg_control_|bank_exx~2, spectrum, 1 -instance = comp, \z80_|reg_control_|bank_exx , z80_|reg_control_|bank_exx, spectrum, 1 -instance = comp, \z80_|reg_control_|bank_hl_de1~0 , z80_|reg_control_|bank_hl_de1~0, spectrum, 1 -instance = comp, \z80_|reg_control_|bank_hl_de1 , z80_|reg_control_|bank_hl_de1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~10 , z80_|execute_|ctl_reg_gp_sel[1]~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~11 , z80_|execute_|ctl_reg_gp_sel[1]~11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~12 , z80_|execute_|ctl_reg_gp_sel[1]~12, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~7 , z80_|execute_|ctl_mRead~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~9 , z80_|execute_|ctl_reg_gp_sel[1]~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~37 , z80_|execute_|ctl_reg_gp_sel[1]~37, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~13 , z80_|execute_|ctl_reg_gp_sel[1]~13, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~47 , z80_|execute_|ctl_reg_gp_hilo[1]~47, spectrum, 1 -instance = comp, \z80_|execute_|fMWrite~3 , z80_|execute_|fMWrite~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_bus~5 , z80_|execute_|ctl_flags_bus~5, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~2 , z80_|execute_|fMRead~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~19 , z80_|execute_|ctl_mRead~19, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~7 , z80_|execute_|ctl_reg_gp_sel[1]~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~8 , z80_|execute_|ctl_reg_gp_sel[1]~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~14 , z80_|execute_|ctl_reg_gp_sel[1]~14, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~16 , z80_|execute_|ctl_reg_gp_sel[1]~16, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~15 , z80_|execute_|ctl_reg_gp_sel[1]~15, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~17 , z80_|execute_|ctl_reg_gp_sel[1]~17, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~19 , z80_|execute_|ctl_reg_gp_sel[1]~19, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_use_sp~2 , z80_|execute_|ctl_reg_use_sp~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~47 , z80_|execute_|ctl_bus_inc_oe~47, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_use_sp~3 , z80_|execute_|ctl_reg_use_sp~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_1d~9 , z80_|execute_|ctl_sw_1d~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~21 , z80_|execute_|ctl_reg_gp_sel[0]~21, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~20 , z80_|execute_|ctl_reg_gp_hilo[1]~20, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~20 , z80_|execute_|ctl_reg_gp_sel[0]~20, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~49 , z80_|execute_|ctl_reg_gp_hilo[1]~49, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~22 , z80_|execute_|ctl_reg_gp_sel[0]~22, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~18 , z80_|execute_|ctl_reg_gp_sel[1]~18, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~23 , z80_|execute_|ctl_reg_gp_sel[1]~23, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~28 , z80_|execute_|ctl_reg_gp_sel[0]~28, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~23 , z80_|execute_|ctl_reg_gp_hilo[1]~23, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf2_sel_shift~2 , z80_|execute_|ctl_flags_cf2_sel_shift~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_hf_cpl~14 , z80_|execute_|ctl_flags_hf_cpl~14, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_hf_cpl~10 , z80_|execute_|ctl_flags_hf_cpl~10, spectrum, 1 -instance = comp, \z80_|execute_|setM1~47 , z80_|execute_|setM1~47, spectrum, 1 -instance = comp, \z80_|execute_|setM1~48 , z80_|execute_|setM1~48, spectrum, 1 -instance = comp, \z80_|execute_|ctl_al_we~13 , z80_|execute_|ctl_al_we~13, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_oe~0 , z80_|execute_|ctl_flags_oe~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_oe~1 , z80_|execute_|ctl_flags_oe~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_in_hi~13 , z80_|execute_|ctl_reg_in_hi~13, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~29 , z80_|execute_|ctl_reg_gp_sel[0]~29, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~40 , z80_|execute_|ctl_inc_cy~40, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_dec~2 , z80_|execute_|ctl_inc_dec~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_dec~12 , z80_|execute_|ctl_inc_dec~12, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~43 , z80_|execute_|ctl_inc_cy~43, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_dec~5 , z80_|execute_|ctl_inc_dec~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~4 , z80_|execute_|ctl_reg_gp_sel[1]~4, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~6 , z80_|execute_|fMRead~6, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~7 , z80_|execute_|fMRead~7, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~8 , z80_|execute_|fMRead~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~26 , z80_|execute_|ctl_reg_gp_sel[1]~26, spectrum, 1 -instance = comp, \z80_|execute_|ctl_state_alu~13 , z80_|execute_|ctl_state_alu~13, spectrum, 1 -instance = comp, \z80_|execute_|ctl_state_alu~10 , z80_|execute_|ctl_state_alu~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_state_alu~11 , z80_|execute_|ctl_state_alu~11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_state_alu~9 , z80_|execute_|ctl_state_alu~9, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal62~2 , z80_|pla_decode_|Equal62~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_pf_we~4 , z80_|execute_|ctl_flags_pf_we~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~21 , z80_|execute_|ctl_reg_gp_hilo[1]~21, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal64~0 , z80_|pla_decode_|Equal64~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_pf_sel[0]~3 , z80_|execute_|ctl_pf_sel[0]~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~22 , z80_|execute_|ctl_reg_gp_hilo[1]~22, spectrum, 1 -instance = comp, \z80_|execute_|ctl_state_alu~15 , z80_|execute_|ctl_state_alu~15, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 , z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~25 , z80_|execute_|ctl_reg_gp_sel[0]~25, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~30 , z80_|execute_|ctl_reg_gp_sel[0]~30, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~31 , z80_|execute_|ctl_reg_gp_sel[1]~31, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~33 , z80_|execute_|ctl_reg_gp_sel[0]~33, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~34 , z80_|execute_|ctl_reg_gp_sel[0]~34, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo~20 , z80_|execute_|ctl_reg_sys_hilo~20, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~32 , z80_|execute_|ctl_reg_gp_sel[0]~32, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~35 , z80_|execute_|ctl_reg_gp_sel[0]~35, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sel_de2~5 , z80_|reg_control_|reg_sel_de2~5, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sel_de2~6 , z80_|reg_control_|reg_sel_de2~6, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sel_hl~0 , z80_|reg_control_|reg_sel_hl~0, spectrum, 1 -instance = comp, \z80_|reg_control_|bank_hl_de2~0 , z80_|reg_control_|bank_hl_de2~0, spectrum, 1 -instance = comp, \z80_|reg_control_|bank_hl_de2 , z80_|reg_control_|bank_hl_de2, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sel_hl2~0 , z80_|reg_control_|reg_sel_hl2~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_in_hi~7 , z80_|execute_|ctl_reg_in_hi~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_we~4 , z80_|execute_|ctl_reg_gp_we~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 , z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_we~3 , z80_|execute_|ctl_reg_gp_we~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~13 , z80_|execute_|ctl_alu_sel_op2_neg~13, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5 , z80_|execute_|ctl_reg_gp_hilo_pla30npla13M5T3_5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_we~2 , z80_|execute_|ctl_reg_gp_we~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_we~5 , z80_|execute_|ctl_reg_gp_we~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_we~6 , z80_|execute_|ctl_reg_gp_we~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_al_we~14 , z80_|execute_|ctl_al_we~14, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~50 , z80_|execute_|ctl_reg_gp_hilo[0]~50, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~26 , z80_|execute_|ctl_reg_gp_hilo[0]~26, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~27 , z80_|execute_|ctl_reg_gp_hilo[0]~27, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~28 , z80_|execute_|ctl_reg_gp_hilo[0]~28, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~29 , z80_|execute_|ctl_reg_gp_hilo[0]~29, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 , z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~31 , z80_|execute_|ctl_reg_gp_hilo[0]~31, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~51 , z80_|execute_|ctl_reg_gp_hilo[0]~51, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~30 , z80_|execute_|ctl_reg_gp_hilo[0]~30, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~32 , z80_|execute_|ctl_reg_gp_hilo[0]~32, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~34 , z80_|execute_|ctl_reg_gp_hilo[0]~34, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~24 , z80_|execute_|ctl_reg_gp_hilo[1]~24, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~25 , z80_|execute_|ctl_reg_gp_hilo[0]~25, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~36 , z80_|execute_|ctl_reg_gp_hilo[1]~36, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 , z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4, spectrum, 1 -instance = comp, \z80_|execute_|setM1~40 , z80_|execute_|setM1~40, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~18 , z80_|execute_|ctl_reg_gp_hilo[1]~18, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~37 , z80_|execute_|ctl_reg_gp_hilo[1]~37, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~38 , z80_|execute_|ctl_reg_gp_hilo[0]~38, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[0]~93 , z80_|reg_file_|gdfx_temp0[0]~93, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sel_de~0 , z80_|reg_control_|reg_sel_de~0, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_50 , z80_|reg_file_|SYNTHESIZED_WIRE_50, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 , z80_|reg_file_|SYNTHESIZED_WIRE_70~2, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 , z80_|reg_file_|SYNTHESIZED_WIRE_66~0, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 , z80_|reg_file_|SYNTHESIZED_WIRE_38~0, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 , z80_|reg_file_|SYNTHESIZED_WIRE_42~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_in_hi~9 , z80_|execute_|ctl_reg_in_hi~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_in_hi~10 , z80_|execute_|ctl_reg_in_hi~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_wz~19 , z80_|execute_|ctl_reg_sel_wz~19, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 , z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_in_lo~8 , z80_|execute_|ctl_reg_in_lo~8, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[0]~19 , z80_|reg_file_|gdfx_temp0[0]~19, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_use_sp~4 , z80_|execute_|ctl_reg_use_sp~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_use_sp~5 , z80_|execute_|ctl_reg_use_sp~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_use_sp~6 , z80_|execute_|ctl_reg_use_sp~6, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 , z80_|reg_file_|SYNTHESIZED_WIRE_78~0, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal21~2 , z80_|pla_decode_|Equal21~2, spectrum, 1 -instance = comp, \z80_|reg_control_|bank_af~0 , z80_|reg_control_|bank_af~0, spectrum, 1 -instance = comp, \z80_|reg_control_|bank_af , z80_|reg_control_|bank_af, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sel_af~0 , z80_|reg_control_|reg_sel_af~0, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_34 , z80_|reg_file_|SYNTHESIZED_WIRE_34, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sel_af2~0 , z80_|reg_control_|reg_sel_af2~0, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_30 , z80_|reg_file_|SYNTHESIZED_WIRE_30, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_wz~12 , z80_|execute_|ctl_reg_sel_wz~12, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_bus~4 , z80_|execute_|ctl_flags_bus~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_bus~6 , z80_|execute_|ctl_flags_bus~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_bus~7 , z80_|execute_|ctl_flags_bus~7, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~24 , z80_|execute_|fMRead~24, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_bus~13 , z80_|execute_|ctl_flags_bus~13, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_bus , z80_|execute_|ctl_flags_bus, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_dec~3 , z80_|execute_|ctl_inc_dec~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~14 , z80_|execute_|ctl_reg_sys_hilo[1]~14, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_pc~2 , z80_|execute_|ctl_reg_sel_pc~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_pc~3 , z80_|execute_|ctl_reg_sel_pc~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_pc~6 , z80_|execute_|ctl_reg_sel_pc~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_pc~5 , z80_|execute_|ctl_reg_sel_pc~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_pc~4 , z80_|execute_|ctl_reg_sel_pc~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_pc~7 , z80_|execute_|ctl_reg_sel_pc~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_pc~8 , z80_|execute_|ctl_reg_sel_pc~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_pc~9 , z80_|execute_|ctl_reg_sel_pc~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_pc~10 , z80_|execute_|ctl_reg_sel_pc~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~13 , z80_|execute_|ctl_reg_sys_hilo[1]~13, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~15 , z80_|execute_|ctl_reg_sys_hilo[1]~15, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~29 , z80_|execute_|ctl_bus_inc_oe~29, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~13 , z80_|execute_|ctl_mRead~13, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~49 , z80_|execute_|pc_inc_hold~49, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~9 , z80_|execute_|ctl_reg_sys_hilo[1]~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~10 , z80_|execute_|ctl_reg_sys_hilo[1]~10, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~28 , z80_|execute_|pc_inc_hold~28, spectrum, 1 -instance = comp, \z80_|execute_|setM1~35 , z80_|execute_|setM1~35, spectrum, 1 -instance = comp, \z80_|execute_|setM1~36 , z80_|execute_|setM1~36, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~5 , z80_|execute_|fMRead~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~31 , z80_|execute_|ctl_bus_inc_oe~31, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~29 , z80_|execute_|pc_inc_hold~29, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_we~1 , z80_|execute_|ctl_reg_sys_we~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_we~2 , z80_|execute_|ctl_reg_sys_we~2, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal33~3 , z80_|pla_decode_|Equal33~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_we~0 , z80_|execute_|ctl_reg_sys_we~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_we~3 , z80_|execute_|ctl_reg_sys_we~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_we_lo~2 , z80_|execute_|ctl_reg_sys_we_lo~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_we_lo~3 , z80_|execute_|ctl_reg_sys_we_lo~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_we_lo~4 , z80_|execute_|ctl_reg_sys_we_lo~4, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sys_we_lo , z80_|reg_control_|reg_sys_we_lo, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_ir~0 , z80_|execute_|ctl_reg_sel_ir~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_ir~1 , z80_|execute_|ctl_reg_sel_ir~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_out_lo~9 , z80_|execute_|ctl_reg_out_lo~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~36 , z80_|execute_|ctl_reg_sys_hilo[1]~36, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[0]~12 , z80_|execute_|ctl_reg_sys_hilo[0]~12, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 , z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_in_hi~4 , z80_|execute_|ctl_reg_in_hi~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_wz~4 , z80_|execute_|ctl_reg_sel_wz~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 , z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_wz~5 , z80_|execute_|ctl_reg_sel_wz~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_wz~6 , z80_|execute_|ctl_reg_sel_wz~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_wz~7 , z80_|execute_|ctl_reg_sel_wz~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo~16 , z80_|execute_|ctl_reg_sys_hilo~16, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_pc~11 , z80_|execute_|ctl_reg_sel_pc~11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~17 , z80_|execute_|ctl_reg_sys_hilo[1]~17, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_pc~12 , z80_|execute_|ctl_reg_sel_pc~12, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_pc~13 , z80_|execute_|ctl_reg_sel_pc~13, spectrum, 1 -instance = comp, \z80_|execute_|ctl_al_we~4 , z80_|execute_|ctl_al_we~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~38 , z80_|execute_|ctl_reg_sys_hilo[1]~38, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~0 , z80_|execute_|fMRead~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~24 , z80_|execute_|ctl_reg_sys_hilo[1]~24, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~25 , z80_|execute_|ctl_reg_sys_hilo[1]~25, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_dec~4 , z80_|execute_|ctl_inc_dec~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~21 , z80_|execute_|ctl_reg_sys_hilo[1]~21, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_wz~9 , z80_|execute_|ctl_reg_sel_wz~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 , z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~22 , z80_|execute_|ctl_reg_sys_hilo[1]~22, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~23 , z80_|execute_|ctl_reg_sys_hilo[1]~23, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_wz~8 , z80_|execute_|ctl_reg_sel_wz~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~18 , z80_|execute_|ctl_reg_sys_hilo[1]~18, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~19 , z80_|execute_|ctl_reg_sys_hilo[1]~19, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~26 , z80_|execute_|ctl_reg_sys_hilo[1]~26, spectrum, 1 -instance = comp, \z80_|execute_|ctl_al_we~5 , z80_|execute_|ctl_al_we~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~27 , z80_|execute_|ctl_reg_sys_hilo[1]~27, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~28 , z80_|execute_|ctl_reg_sys_hilo[1]~28, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_wz~18 , z80_|execute_|ctl_reg_sel_wz~18, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[0]~37 , z80_|execute_|ctl_reg_sys_hilo[0]~37, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[0]~29 , z80_|execute_|ctl_reg_sys_hilo[0]~29, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_62 , z80_|reg_file_|SYNTHESIZED_WIRE_62, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~38 , z80_|execute_|ctl_bus_inc_oe~38, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~39 , z80_|execute_|ctl_bus_inc_oe~39, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~30 , z80_|execute_|ctl_bus_inc_oe~30, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~45 , z80_|execute_|ctl_bus_inc_oe~45, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~1 , z80_|execute_|fMRead~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~36 , z80_|execute_|ctl_bus_inc_oe~36, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~27 , z80_|execute_|ctl_bus_inc_oe~27, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~28 , z80_|execute_|ctl_bus_inc_oe~28, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~37 , z80_|execute_|ctl_bus_inc_oe~37, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~40 , z80_|execute_|ctl_bus_inc_oe~40, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~35 , z80_|execute_|ctl_bus_inc_oe~35, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~77 , z80_|execute_|ctl_inc_cy~77, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~32 , z80_|execute_|ctl_bus_inc_oe~32, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2 , z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~33 , z80_|execute_|ctl_bus_inc_oe~33, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~34 , z80_|execute_|ctl_bus_inc_oe~34, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~41 , z80_|execute_|ctl_bus_inc_oe~41, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_wz~10 , z80_|execute_|ctl_reg_sel_wz~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_wz~11 , z80_|execute_|ctl_reg_sel_wz~11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_4d~3 , z80_|execute_|ctl_sw_4d~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_4d~4 , z80_|execute_|ctl_sw_4d~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_4d~2 , z80_|execute_|ctl_sw_4d~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_4d~5 , z80_|execute_|ctl_sw_4d~5, spectrum, 1 -instance = comp, \z80_|execute_|setM1~45 , z80_|execute_|setM1~45, spectrum, 1 -instance = comp, \z80_|execute_|setM1~46 , z80_|execute_|setM1~46, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_4d~1 , z80_|execute_|ctl_sw_4d~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_4d~0 , z80_|execute_|ctl_sw_4d~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_4d~6 , z80_|execute_|ctl_sw_4d~6, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~4 , z80_|execute_|fMRead~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_pc~16 , z80_|execute_|ctl_reg_sel_pc~16, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_pc~14 , z80_|execute_|ctl_reg_sel_pc~14, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_pc~20 , z80_|execute_|ctl_reg_sel_pc~20, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_pc~15 , z80_|execute_|ctl_reg_sel_pc~15, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_pc~17 , z80_|execute_|ctl_reg_sel_pc~17, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_pc~18 , z80_|execute_|ctl_reg_sel_pc~18, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_pc~19 , z80_|execute_|ctl_reg_sel_pc~19, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sel_pc~3 , z80_|reg_control_|reg_sel_pc~3, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sel_pc , z80_|reg_control_|reg_sel_pc, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_74 , z80_|reg_file_|SYNTHESIZED_WIRE_74, spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[0]~2 , z80_|reg_file_|db_lo_as[0]~2, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_75 , z80_|reg_file_|SYNTHESIZED_WIRE_75, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_pc_lo|latch[7] , z80_|reg_file_|b2v_latch_pc_lo|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[7]~22 , z80_|reg_file_|db_lo_as[7]~22, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_63 , z80_|reg_file_|SYNTHESIZED_WIRE_63, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ir_lo|latch[7] , z80_|reg_file_|b2v_latch_ir_lo|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[7]~23 , z80_|reg_file_|db_lo_as[7]~23, spectrum, 1 -instance = comp, \z80_|resets_|SYNTHESIZED_WIRE_10~0 , z80_|resets_|SYNTHESIZED_WIRE_10~0, spectrum, 1 -instance = comp, \z80_|resets_|SYNTHESIZED_WIRE_10 , z80_|resets_|SYNTHESIZED_WIRE_10, spectrum, 1 -instance = comp, \z80_|resets_|SYNTHESIZED_WIRE_9 , z80_|resets_|SYNTHESIZED_WIRE_9, spectrum, 1 -instance = comp, \z80_|resets_|DFFE_intr_ff3 , z80_|resets_|DFFE_intr_ff3, spectrum, 1 -instance = comp, \KEY[0]~input , KEY[0]~input, spectrum, 1 -instance = comp, \z80_|resets_|x1~0 , z80_|resets_|x1~0, spectrum, 1 -instance = comp, \z80_|fpga_reset~feeder , z80_|fpga_reset~feeder, spectrum, 1 -instance = comp, \z80_|fpga_reset , z80_|fpga_reset, spectrum, 1 -instance = comp, \z80_|fpga_reset~clkctrl , z80_|fpga_reset~clkctrl, spectrum, 1 -instance = comp, \z80_|resets_|x1 , z80_|resets_|x1, spectrum, 1 -instance = comp, \z80_|resets_|clrpc_int~0 , z80_|resets_|clrpc_int~0, spectrum, 1 -instance = comp, \z80_|resets_|clrpc_int , z80_|resets_|clrpc_int, spectrum, 1 -instance = comp, \z80_|resets_|clrpc~0 , z80_|resets_|clrpc~0, spectrum, 1 -instance = comp, \z80_|address_latch_|abusz[7] , z80_|address_latch_|abusz[7], spectrum, 1 -instance = comp, \z80_|execute_|ctl_apin_mux~1 , z80_|execute_|ctl_apin_mux~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_al_we~6 , z80_|execute_|ctl_al_we~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_al_we~7 , z80_|execute_|ctl_al_we~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_al_we~8 , z80_|execute_|ctl_al_we~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_oe~10 , z80_|execute_|ctl_alu_oe~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_al_we~9 , z80_|execute_|ctl_al_we~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_al_we~10 , z80_|execute_|ctl_al_we~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_al_we~11 , z80_|execute_|ctl_al_we~11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_al_we~12 , z80_|execute_|ctl_al_we~12, spectrum, 1 -instance = comp, \z80_|address_latch_|Q[7] , z80_|address_latch_|Q[7], spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_dec~6 , z80_|execute_|ctl_inc_dec~6, spectrum, 1 -instance = comp, \z80_|execute_|fIOWrite~0 , z80_|execute_|fIOWrite~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_dec~8 , z80_|execute_|ctl_inc_dec~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_dec~9 , z80_|execute_|ctl_inc_dec~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_dec~10 , z80_|execute_|ctl_inc_dec~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_dec~7 , z80_|execute_|ctl_inc_dec~7, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ir_lo|latch[2] , z80_|reg_file_|b2v_latch_ir_lo|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_54 , z80_|reg_file_|SYNTHESIZED_WIRE_54, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_58 , z80_|reg_file_|SYNTHESIZED_WIRE_58, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_55 , z80_|reg_file_|SYNTHESIZED_WIRE_55, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] , z80_|reg_file_|b2v_latch_hl2_lo|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_59 , z80_|reg_file_|SYNTHESIZED_WIRE_59, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl_lo|latch[2] , z80_|reg_file_|b2v_latch_hl_lo|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[2]~34 , z80_|reg_file_|gdfx_temp0[2]~34, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_51 , z80_|reg_file_|SYNTHESIZED_WIRE_51, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de_lo|latch[2] , z80_|reg_file_|b2v_latch_de_lo|latch[2], spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sel_de2~4 , z80_|reg_control_|reg_sel_de2~4, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_46 , z80_|reg_file_|SYNTHESIZED_WIRE_46, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_47 , z80_|reg_file_|SYNTHESIZED_WIRE_47, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de2_lo|latch[2] , z80_|reg_file_|b2v_latch_de2_lo|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[2]~33 , z80_|reg_file_|gdfx_temp0[2]~33, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 , z80_|reg_file_|SYNTHESIZED_WIRE_71~2, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 , z80_|reg_file_|SYNTHESIZED_WIRE_43~0, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc_lo|latch[2] , z80_|reg_file_|b2v_latch_bc_lo|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 , z80_|reg_file_|SYNTHESIZED_WIRE_39~0, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] , z80_|reg_file_|b2v_latch_bc2_lo|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[2]~36 , z80_|reg_file_|gdfx_temp0[2]~36, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_83 , z80_|reg_file_|SYNTHESIZED_WIRE_83, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_wz_lo|latch[2] , z80_|reg_file_|b2v_latch_wz_lo|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[2]~37 , z80_|reg_file_|gdfx_temp0[2]~37, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 , z80_|reg_file_|SYNTHESIZED_WIRE_79~0, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_sp_lo|latch[2] , z80_|reg_file_|b2v_latch_sp_lo|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[2]~39 , z80_|reg_file_|gdfx_temp0[2]~39, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sel_iy~2 , z80_|reg_control_|reg_sel_iy~2, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_70 , z80_|reg_file_|SYNTHESIZED_WIRE_70, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 , z80_|reg_file_|SYNTHESIZED_WIRE_67~0, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ix_lo|latch[2] , z80_|reg_file_|b2v_latch_ix_lo|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_71 , z80_|reg_file_|SYNTHESIZED_WIRE_71, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_iy_lo|latch[2] , z80_|reg_file_|b2v_latch_iy_lo|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[2]~38 , z80_|reg_file_|gdfx_temp0[2]~38, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_31 , z80_|reg_file_|SYNTHESIZED_WIRE_31, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af2_lo|latch[2] , z80_|reg_file_|b2v_latch_af2_lo|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder , z80_|reg_file_|b2v_latch_af_lo|latch[2]~feeder, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_35 , z80_|reg_file_|SYNTHESIZED_WIRE_35, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[2] , z80_|reg_file_|b2v_latch_af_lo|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[2]~35 , z80_|reg_file_|gdfx_temp0[2]~35, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[2]~40 , z80_|reg_file_|gdfx_temp0[2]~40, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[2]~41 , z80_|reg_file_|gdfx_temp0[2]~41, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[2]~42 , z80_|reg_file_|gdfx_temp0[2]~42, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_pc_lo|latch[2] , z80_|reg_file_|b2v_latch_pc_lo|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[2]~7 , z80_|reg_file_|db_lo_as[2]~7, spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[2]~8 , z80_|reg_file_|db_lo_as[2]~8, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ir_lo|latch[0] , z80_|reg_file_|b2v_latch_ir_lo|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de_lo|latch[0] , z80_|reg_file_|b2v_latch_de_lo|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de2_lo|latch[0] , z80_|reg_file_|b2v_latch_de2_lo|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[0]~10 , z80_|reg_file_|gdfx_temp0[0]~10, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] , z80_|reg_file_|b2v_latch_hl2_lo|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0 , z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl_lo|latch[0] , z80_|reg_file_|b2v_latch_hl_lo|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[0]~11 , z80_|reg_file_|gdfx_temp0[0]~11, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_sp_lo|latch[0] , z80_|reg_file_|b2v_latch_sp_lo|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_iy_lo|latch[0] , z80_|reg_file_|b2v_latch_iy_lo|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[0]~15 , z80_|reg_file_|gdfx_temp0[0]~15, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_wz_lo|latch[0] , z80_|reg_file_|b2v_latch_wz_lo|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder , z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc_lo|latch[0] , z80_|reg_file_|b2v_latch_bc_lo|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ix_lo|latch[0] , z80_|reg_file_|b2v_latch_ix_lo|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[0]~14 , z80_|reg_file_|gdfx_temp0[0]~14, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[0]~16 , z80_|reg_file_|gdfx_temp0[0]~16, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] , z80_|reg_file_|b2v_latch_bc2_lo|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[0]~12 , z80_|reg_file_|gdfx_temp0[0]~12, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af2_lo|latch[0] , z80_|reg_file_|b2v_latch_af2_lo|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[0] , z80_|reg_file_|b2v_latch_af_lo|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[0]~13 , z80_|reg_file_|gdfx_temp0[0]~13, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[0]~17 , z80_|reg_file_|gdfx_temp0[0]~17, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[0]~22 , z80_|reg_file_|gdfx_temp0[0]~22, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_pc_lo|latch[0] , z80_|reg_file_|b2v_latch_pc_lo|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[0]~0 , z80_|reg_file_|db_lo_as[0]~0, spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[0]~1 , z80_|reg_file_|db_lo_as[0]~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~72 , z80_|execute_|ctl_inc_cy~72, spectrum, 1 +instance = comp, \z80_|resets_|SYNTHESIZED_WIRE_11 , z80_|resets_|SYNTHESIZED_WIRE_11, spectrum, 1 +instance = comp, \z80_|execute_|ctl_ir_we~4 , z80_|execute_|ctl_ir_we~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_state_iy_set~2 , z80_|execute_|ctl_state_iy_set~2, spectrum, 1 +instance = comp, \z80_|sequencer_|SYNTHESIZED_WIRE_16 , z80_|sequencer_|SYNTHESIZED_WIRE_16, spectrum, 1 +instance = comp, \z80_|sequencer_|DFFE_T5_ff , z80_|sequencer_|DFFE_T5_ff, spectrum, 1 +instance = comp, \z80_|execute_|ctl_state_ixiy_we~2 , z80_|execute_|ctl_state_ixiy_we~2, spectrum, 1 +instance = comp, \z80_|decode_state_|DFFE_instIY1 , z80_|decode_state_|DFFE_instIY1, spectrum, 1 +instance = comp, \z80_|decode_state_|use_ixiy , z80_|decode_state_|use_ixiy, spectrum, 1 +instance = comp, \z80_|execute_|ixy_d~4 , z80_|execute_|ixy_d~4, spectrum, 1 +instance = comp, \z80_|execute_|ixy_d~11 , z80_|execute_|ixy_d~11, spectrum, 1 +instance = comp, \z80_|execute_|ixy_d~9 , z80_|execute_|ixy_d~9, spectrum, 1 +instance = comp, \z80_|execute_|ixy_d~7 , z80_|execute_|ixy_d~7, spectrum, 1 +instance = comp, \z80_|execute_|ixy_d~6 , z80_|execute_|ixy_d~6, spectrum, 1 +instance = comp, \z80_|execute_|ixy_d~8 , z80_|execute_|ixy_d~8, spectrum, 1 +instance = comp, \z80_|execute_|ixy_d~12 , z80_|execute_|ixy_d~12, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal33~0 , z80_|pla_decode_|Equal33~0, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal33~1 , z80_|pla_decode_|Equal33~1, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal33~2 , z80_|pla_decode_|Equal33~2, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal21~0 , z80_|pla_decode_|Equal21~0, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal77~0 , z80_|pla_decode_|Equal77~0, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal77~1 , z80_|pla_decode_|Equal77~1, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal1~7 , z80_|pla_decode_|Equal1~7, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal79~0 , z80_|pla_decode_|Equal79~0, spectrum, 1 +instance = comp, \z80_|interrupts_|iff1~0 , z80_|interrupts_|iff1~0, spectrum, 1 +instance = comp, \z80_|interrupts_|DFFE_instIFF2~0 , z80_|interrupts_|DFFE_instIFF2~0, spectrum, 1 +instance = comp, \z80_|interrupts_|SYNTHESIZED_WIRE_12 , z80_|interrupts_|SYNTHESIZED_WIRE_12, spectrum, 1 +instance = comp, \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl , z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl, spectrum, 1 +instance = comp, \z80_|interrupts_|DFFE_instIFF2 , z80_|interrupts_|DFFE_instIFF2, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal13~0 , z80_|pla_decode_|Equal13~0, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal38~2 , z80_|pla_decode_|Equal38~2, spectrum, 1 +instance = comp, \z80_|interrupts_|iff1~1 , z80_|interrupts_|iff1~1, spectrum, 1 +instance = comp, \z80_|interrupts_|SYNTHESIZED_WIRE_15 , z80_|interrupts_|SYNTHESIZED_WIRE_15, spectrum, 1 +instance = comp, \z80_|interrupts_|iff1 , z80_|interrupts_|iff1, spectrum, 1 instance = comp, \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl , ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl, spectrum, 1 +instance = comp, \ula_|video_|Add0~0 , ula_|video_|Add0~0, spectrum, 1 +instance = comp, \ula_|video_|vga_hc~3 , ula_|video_|vga_hc~3, spectrum, 1 +instance = comp, \ula_|video_|vga_hc[0] , ula_|video_|vga_hc[0], spectrum, 1 +instance = comp, \ula_|video_|Add0~2 , ula_|video_|Add0~2, spectrum, 1 +instance = comp, \ula_|video_|vga_hc[1] , ula_|video_|vga_hc[1], spectrum, 1 +instance = comp, \ula_|video_|Add0~4 , ula_|video_|Add0~4, spectrum, 1 +instance = comp, \ula_|video_|vga_hc[2] , ula_|video_|vga_hc[2], spectrum, 1 +instance = comp, \ula_|video_|Add0~6 , ula_|video_|Add0~6, spectrum, 1 +instance = comp, \ula_|video_|vga_hc[3] , ula_|video_|vga_hc[3], spectrum, 1 +instance = comp, \ula_|video_|Add0~8 , ula_|video_|Add0~8, spectrum, 1 +instance = comp, \ula_|video_|vga_hc[4] , ula_|video_|vga_hc[4], spectrum, 1 +instance = comp, \ula_|video_|Add0~10 , ula_|video_|Add0~10, spectrum, 1 +instance = comp, \ula_|video_|vga_hc~0 , ula_|video_|vga_hc~0, spectrum, 1 +instance = comp, \ula_|video_|vga_hc[5] , ula_|video_|vga_hc[5], spectrum, 1 +instance = comp, \ula_|video_|Add0~12 , ula_|video_|Add0~12, spectrum, 1 +instance = comp, \ula_|video_|vga_hc[6] , ula_|video_|vga_hc[6], spectrum, 1 instance = comp, \ula_|video_|Add0~14 , ula_|video_|Add0~14, spectrum, 1 +instance = comp, \ula_|video_|vga_hc[7] , ula_|video_|vga_hc[7], spectrum, 1 instance = comp, \ula_|video_|Add0~16 , ula_|video_|Add0~16, spectrum, 1 instance = comp, \ula_|video_|vga_hc~2 , ula_|video_|vga_hc~2, spectrum, 1 instance = comp, \ula_|video_|vga_hc[8] , ula_|video_|vga_hc[8], spectrum, 1 instance = comp, \ula_|video_|Add0~18 , ula_|video_|Add0~18, spectrum, 1 instance = comp, \ula_|video_|vga_hc~1 , ula_|video_|vga_hc~1, spectrum, 1 instance = comp, \ula_|video_|vga_hc[9] , ula_|video_|vga_hc[9], spectrum, 1 -instance = comp, \ula_|video_|Add0~0 , ula_|video_|Add0~0, spectrum, 1 -instance = comp, \ula_|video_|vga_hc~3 , ula_|video_|vga_hc~3, spectrum, 1 -instance = comp, \ula_|video_|vga_hc[0] , ula_|video_|vga_hc[0], spectrum, 1 -instance = comp, \ula_|video_|Add0~2 , ula_|video_|Add0~2, spectrum, 1 -instance = comp, \ula_|video_|vga_hc[1]~feeder , ula_|video_|vga_hc[1]~feeder, spectrum, 1 -instance = comp, \ula_|video_|vga_hc[1] , ula_|video_|vga_hc[1], spectrum, 1 -instance = comp, \ula_|video_|Add0~4 , ula_|video_|Add0~4, spectrum, 1 -instance = comp, \ula_|video_|vga_hc[2] , ula_|video_|vga_hc[2], spectrum, 1 -instance = comp, \ula_|video_|Add0~6 , ula_|video_|Add0~6, spectrum, 1 -instance = comp, \ula_|video_|vga_hc[3]~feeder , ula_|video_|vga_hc[3]~feeder, spectrum, 1 -instance = comp, \ula_|video_|vga_hc[3] , ula_|video_|vga_hc[3], spectrum, 1 -instance = comp, \ula_|video_|Add0~8 , ula_|video_|Add0~8, spectrum, 1 -instance = comp, \ula_|video_|vga_hc[4] , ula_|video_|vga_hc[4], spectrum, 1 instance = comp, \ula_|video_|Equal0~0 , ula_|video_|Equal0~0, spectrum, 1 instance = comp, \ula_|video_|Equal0~1 , ula_|video_|Equal0~1, spectrum, 1 instance = comp, \ula_|video_|Equal1~0 , ula_|video_|Equal1~0, spectrum, 1 -instance = comp, \ula_|video_|Add0~10 , ula_|video_|Add0~10, spectrum, 1 -instance = comp, \ula_|video_|vga_hc~0 , ula_|video_|vga_hc~0, spectrum, 1 -instance = comp, \ula_|video_|vga_hc[5] , ula_|video_|vga_hc[5], spectrum, 1 -instance = comp, \ula_|video_|Add0~12 , ula_|video_|Add0~12, spectrum, 1 -instance = comp, \ula_|video_|vga_hc[6] , ula_|video_|vga_hc[6], spectrum, 1 -instance = comp, \ula_|video_|vga_hc[7] , ula_|video_|vga_hc[7], spectrum, 1 instance = comp, \ula_|video_|Add1~0 , ula_|video_|Add1~0, spectrum, 1 +instance = comp, \ula_|video_|vga_vc[0]~0 , ula_|video_|vga_vc[0]~0, spectrum, 1 +instance = comp, \ula_|video_|vga_vc[0] , ula_|video_|vga_vc[0], spectrum, 1 instance = comp, \ula_|video_|Add1~2 , ula_|video_|Add1~2, spectrum, 1 +instance = comp, \ula_|video_|vga_vc[1]~1 , ula_|video_|vga_vc[1]~1, spectrum, 1 +instance = comp, \ula_|video_|vga_vc[1] , ula_|video_|vga_vc[1], spectrum, 1 instance = comp, \ula_|video_|Add1~4 , ula_|video_|Add1~4, spectrum, 1 instance = comp, \ula_|video_|vga_vc[2]~2 , ula_|video_|vga_vc[2]~2, spectrum, 1 +instance = comp, \ula_|video_|vga_vc[2]~feeder , ula_|video_|vga_vc[2]~feeder, spectrum, 1 instance = comp, \ula_|video_|vga_vc[2] , ula_|video_|vga_vc[2], spectrum, 1 instance = comp, \ula_|video_|Add1~6 , ula_|video_|Add1~6, spectrum, 1 instance = comp, \ula_|video_|vga_vc[3]~3 , ula_|video_|vga_vc[3]~3, spectrum, 1 @@ -1006,8 +270,6 @@ instance = comp, \ula_|video_|Add1~8 , ula_|video_|Add1~8, spectrum, 1 instance = comp, \ula_|video_|vga_vc[4]~5 , ula_|video_|vga_vc[4]~5, spectrum, 1 instance = comp, \ula_|video_|vga_vc[4] , ula_|video_|vga_vc[4], spectrum, 1 instance = comp, \ula_|video_|Add1~10 , ula_|video_|Add1~10, spectrum, 1 -instance = comp, \ula_|video_|vga_vc[5]~8 , ula_|video_|vga_vc[5]~8, spectrum, 1 -instance = comp, \ula_|video_|vga_vc[5] , ula_|video_|vga_vc[5], spectrum, 1 instance = comp, \ula_|video_|Add1~12 , ula_|video_|Add1~12, spectrum, 1 instance = comp, \ula_|video_|vga_vc[6]~4 , ula_|video_|vga_vc[6]~4, spectrum, 1 instance = comp, \ula_|video_|vga_vc[6] , ula_|video_|vga_vc[6], spectrum, 1 @@ -1020,449 +282,1539 @@ instance = comp, \ula_|video_|vga_vc[8] , ula_|video_|vga_vc[8], spectrum, 1 instance = comp, \ula_|video_|Add1~18 , ula_|video_|Add1~18, spectrum, 1 instance = comp, \ula_|video_|vga_vc[9]~9 , ula_|video_|vga_vc[9]~9, spectrum, 1 instance = comp, \ula_|video_|vga_vc[9] , ula_|video_|vga_vc[9], spectrum, 1 -instance = comp, \ula_|video_|Equal2~0 , ula_|video_|Equal2~0, spectrum, 1 instance = comp, \ula_|video_|Equal3~0 , ula_|video_|Equal3~0, spectrum, 1 +instance = comp, \ula_|video_|Equal2~0 , ula_|video_|Equal2~0, spectrum, 1 instance = comp, \ula_|video_|Equal3~1 , ula_|video_|Equal3~1, spectrum, 1 -instance = comp, \ula_|video_|vga_vc[0]~0 , ula_|video_|vga_vc[0]~0, spectrum, 1 -instance = comp, \ula_|video_|vga_vc[0] , ula_|video_|vga_vc[0], spectrum, 1 -instance = comp, \ula_|video_|vga_vc[1]~1 , ula_|video_|vga_vc[1]~1, spectrum, 1 -instance = comp, \ula_|video_|vga_vc[1] , ula_|video_|vga_vc[1], spectrum, 1 -instance = comp, \SW[1]~input , SW[1]~input, spectrum, 1 -instance = comp, \z80_|interrupts_|SYNTHESIZED_WIRE_13~0 , z80_|interrupts_|SYNTHESIZED_WIRE_13~0, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal79~0 , z80_|pla_decode_|Equal79~0, spectrum, 1 -instance = comp, \z80_|interrupts_|DFFE_instIFF2~0 , z80_|interrupts_|DFFE_instIFF2~0, spectrum, 1 -instance = comp, \z80_|interrupts_|SYNTHESIZED_WIRE_12 , z80_|interrupts_|SYNTHESIZED_WIRE_12, spectrum, 1 -instance = comp, \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl , z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl, spectrum, 1 -instance = comp, \z80_|interrupts_|DFFE_instIFF2 , z80_|interrupts_|DFFE_instIFF2, spectrum, 1 -instance = comp, \z80_|interrupts_|iff1~0 , z80_|interrupts_|iff1~0, spectrum, 1 -instance = comp, \z80_|interrupts_|iff1~1 , z80_|interrupts_|iff1~1, spectrum, 1 -instance = comp, \z80_|interrupts_|SYNTHESIZED_WIRE_15 , z80_|interrupts_|SYNTHESIZED_WIRE_15, spectrum, 1 -instance = comp, \z80_|interrupts_|iff1 , z80_|interrupts_|iff1, spectrum, 1 +instance = comp, \ula_|video_|vga_vc[5]~8 , ula_|video_|vga_vc[5]~8, spectrum, 1 +instance = comp, \ula_|video_|vga_vc[5] , ula_|video_|vga_vc[5], spectrum, 1 instance = comp, \ula_|video_|Equal2~1 , ula_|video_|Equal2~1, spectrum, 1 instance = comp, \ula_|video_|Equal2~2 , ula_|video_|Equal2~2, spectrum, 1 +instance = comp, \SW[1]~input , SW[1]~input, spectrum, 1 +instance = comp, \z80_|interrupts_|SYNTHESIZED_WIRE_13~0 , z80_|interrupts_|SYNTHESIZED_WIRE_13~0, spectrum, 1 instance = comp, \z80_|interrupts_|SYNTHESIZED_WIRE_13 , z80_|interrupts_|SYNTHESIZED_WIRE_13, spectrum, 1 instance = comp, \z80_|interrupts_|int_armed , z80_|interrupts_|int_armed, spectrum, 1 +instance = comp, \z80_|interrupts_|DFFE_inst44~feeder , z80_|interrupts_|DFFE_inst44~feeder, spectrum, 1 instance = comp, \z80_|interrupts_|DFFE_inst44 , z80_|interrupts_|DFFE_inst44, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~38 , z80_|execute_|pc_inc_hold~38, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~91 , z80_|execute_|ctl_inc_cy~91, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~45 , z80_|execute_|pc_inc_hold~45, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~44 , z80_|execute_|pc_inc_hold~44, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~46 , z80_|execute_|pc_inc_hold~46, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~37 , z80_|execute_|pc_inc_hold~37, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~50 , z80_|execute_|pc_inc_hold~50, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~33 , z80_|execute_|pc_inc_hold~33, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 , z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 , z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~31 , z80_|execute_|pc_inc_hold~31, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~32 , z80_|execute_|pc_inc_hold~32, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~34 , z80_|execute_|pc_inc_hold~34, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~51 , z80_|execute_|pc_inc_hold~51, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~30 , z80_|execute_|pc_inc_hold~30, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~52 , z80_|execute_|pc_inc_hold~52, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~35 , z80_|execute_|pc_inc_hold~35, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~36 , z80_|execute_|pc_inc_hold~36, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~44 , z80_|execute_|ctl_inc_cy~44, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 , z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~45 , z80_|execute_|ctl_inc_cy~45, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~43 , z80_|execute_|pc_inc_hold~43, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~71 , z80_|execute_|ctl_inc_cy~71, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~73 , z80_|execute_|ctl_inc_cy~73, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~46 , z80_|execute_|ctl_inc_cy~46, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~53 , z80_|execute_|pc_inc_hold~53, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~39 , z80_|execute_|pc_inc_hold~39, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~47 , z80_|execute_|pc_inc_hold~47, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~74 , z80_|execute_|ctl_inc_cy~74, spectrum, 1 +instance = comp, \z80_|decode_state_|in_halt~0 , z80_|decode_state_|in_halt~0, spectrum, 1 +instance = comp, \z80_|decode_state_|in_halt~1 , z80_|decode_state_|in_halt~1, spectrum, 1 +instance = comp, \z80_|decode_state_|in_halt , z80_|decode_state_|in_halt, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal50~0 , z80_|pla_decode_|Equal50~0, spectrum, 1 +instance = comp, \z80_|execute_|ixy_d~17 , z80_|execute_|ixy_d~17, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal44~0 , z80_|pla_decode_|Equal44~0, spectrum, 1 +instance = comp, \z80_|execute_|ixy_d~16 , z80_|execute_|ixy_d~16, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal3~1 , z80_|pla_decode_|Equal3~1, spectrum, 1 +instance = comp, \z80_|execute_|ixy_d~10 , z80_|execute_|ixy_d~10, spectrum, 1 +instance = comp, \z80_|execute_|ixy_d~13 , z80_|execute_|ixy_d~13, spectrum, 1 +instance = comp, \z80_|execute_|ixy_d~14 , z80_|execute_|ixy_d~14, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal49~0 , z80_|pla_decode_|Equal49~0, spectrum, 1 +instance = comp, \z80_|execute_|ixy_d~15 , z80_|execute_|ixy_d~15, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 , z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7, spectrum, 1 +instance = comp, \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 , z80_|decode_state_|SYNTHESIZED_WIRE_0~0, spectrum, 1 +instance = comp, \z80_|decode_state_|DFFE_inst4 , z80_|decode_state_|DFFE_inst4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_ir_we~5 , z80_|execute_|ctl_ir_we~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_ir_we~13 , z80_|execute_|ctl_ir_we~13, spectrum, 1 +instance = comp, \z80_|ir_|opcode[3] , z80_|ir_|opcode[3], spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal8~0 , z80_|pla_decode_|Equal8~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~6 , z80_|execute_|ctl_mRead~6, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal9~0 , z80_|pla_decode_|Equal9~0, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal9~1 , z80_|pla_decode_|Equal9~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 , z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~28 , z80_|execute_|ctl_reg_gp_hilo[0]~28, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal13~1 , z80_|pla_decode_|Equal13~1, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal69~0 , z80_|pla_decode_|Equal69~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 , z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~27 , z80_|execute_|ctl_alu_op_low~27, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_out_lo~2 , z80_|execute_|ctl_reg_out_lo~2, spectrum, 1 +instance = comp, \z80_|execute_|rsel3 , z80_|execute_|rsel3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_ir_we~12 , z80_|execute_|ctl_ir_we~12, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 , z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal56~0 , z80_|pla_decode_|Equal56~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~24 , z80_|execute_|ctl_alu_op_low~24, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~25 , z80_|execute_|ctl_alu_op_low~25, spectrum, 1 +instance = comp, \z80_|execute_|nextM~2 , z80_|execute_|nextM~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~16 , z80_|execute_|ctl_alu_op1_sel_bus~16, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_out_lo~3 , z80_|execute_|ctl_reg_out_lo~3, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal40~0 , z80_|pla_decode_|Equal40~0, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal40~1 , z80_|pla_decode_|Equal40~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 , z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal3~0 , z80_|pla_decode_|Equal3~0, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal39~0 , z80_|pla_decode_|Equal39~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_out_lo~4 , z80_|execute_|ctl_reg_out_lo~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_oe~0 , z80_|execute_|ctl_alu_oe~0, spectrum, 1 +instance = comp, \z80_|execute_|comb~0 , z80_|execute_|comb~0, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal41~0 , z80_|pla_decode_|Equal41~0, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal47~0 , z80_|pla_decode_|Equal47~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~32 , z80_|execute_|ctl_inc_cy~32, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal19~0 , z80_|pla_decode_|Equal19~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_out_lo~9 , z80_|execute_|ctl_reg_out_lo~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_out_lo~5 , z80_|execute_|ctl_reg_out_lo~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mWrite~4 , z80_|execute_|ctl_mWrite~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 , z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~34 , z80_|execute_|ctl_mRead~34, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 , z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~36 , z80_|execute_|ctl_reg_gp_hilo[1]~36, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mWrite~5 , z80_|execute_|ctl_mWrite~5, spectrum, 1 +instance = comp, \z80_|execute_|nextM~11 , z80_|execute_|nextM~11, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal20~0 , z80_|pla_decode_|Equal20~0, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal13~2 , z80_|pla_decode_|Equal13~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~24 , z80_|execute_|ctl_mRead~24, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~27 , z80_|execute_|ctl_reg_gp_sel[0]~27, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal48~0 , z80_|pla_decode_|Equal48~0, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal10~0 , z80_|pla_decode_|Equal10~0, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal11~0 , z80_|pla_decode_|Equal11~0, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal63~0 , z80_|pla_decode_|Equal63~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_hf2_we , z80_|execute_|ctl_flags_hf2_we, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~41 , z80_|execute_|ctl_alu_shift_oe~41, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal68~3 , z80_|pla_decode_|Equal68~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_bus~7 , z80_|execute_|ctl_flags_bus~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_bus~8 , z80_|execute_|ctl_flags_bus~8, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_nf~9 , z80_|alu_flags_|DFFE_inst_latch_nf~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_ir_we~6 , z80_|execute_|ctl_ir_we~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_ir_we~8 , z80_|execute_|ctl_ir_we~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_ir_we~14 , z80_|execute_|ctl_ir_we~14, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_bus~4 , z80_|execute_|ctl_flags_bus~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_bus~5 , z80_|execute_|ctl_flags_bus~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~4 , z80_|execute_|ctl_mRead~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_bus~6 , z80_|execute_|ctl_flags_bus~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_bus~9 , z80_|execute_|ctl_flags_bus~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_iorw~11 , z80_|execute_|ctl_iorw~11, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mWrite~17 , z80_|execute_|ctl_mWrite~17, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~18 , z80_|execute_|ctl_alu_shift_oe~18, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal37~0 , z80_|pla_decode_|Equal37~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~19 , z80_|execute_|ctl_alu_shift_oe~19, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal35~0 , z80_|pla_decode_|Equal35~0, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal21~1 , z80_|pla_decode_|Equal21~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~17 , z80_|execute_|ctl_alu_shift_oe~17, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~20 , z80_|execute_|ctl_alu_shift_oe~20, spectrum, 1 +instance = comp, \z80_|execute_|ctl_ir_we~9 , z80_|execute_|ctl_ir_we~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_bs_oe~11 , z80_|execute_|ctl_alu_bs_oe~11, spectrum, 1 +instance = comp, \z80_|execute_|ctl_ir_we~15 , z80_|execute_|ctl_ir_we~15, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_bs_oe~7 , z80_|execute_|ctl_alu_bs_oe~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_ir_we~7 , z80_|execute_|ctl_ir_we~7, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal46~0 , z80_|pla_decode_|Equal46~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_ir_we~11 , z80_|execute_|ctl_ir_we~11, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_db_oe~3 , z80_|execute_|ctl_bus_db_oe~3, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal52~1 , z80_|pla_decode_|Equal52~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_xy_we~21 , z80_|execute_|ctl_flags_xy_we~21, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_xy_we~13 , z80_|execute_|ctl_flags_xy_we~13, spectrum, 1 +instance = comp, \z80_|execute_|ctl_state_alu~6 , z80_|execute_|ctl_state_alu~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~14 , z80_|execute_|ctl_alu_shift_oe~14, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_xy_we~14 , z80_|execute_|ctl_flags_xy_we~14, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~24 , z80_|execute_|ctl_reg_gp_sel[0]~24, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~37 , z80_|execute_|ctl_reg_gp_hilo[1]~37, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel~7 , z80_|execute_|ctl_reg_gp_sel~7, spectrum, 1 +instance = comp, \z80_|execute_|rsel0 , z80_|execute_|rsel0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_state_alu~3 , z80_|execute_|ctl_state_alu~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_use_sp~0 , z80_|execute_|ctl_reg_use_sp~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_state_alu~2 , z80_|execute_|ctl_state_alu~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 , z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~30 , z80_|execute_|ctl_reg_gp_hilo[0]~30, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[0]~12 , z80_|execute_|ctl_reg_sys_hilo[0]~12, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_out_lo~6 , z80_|execute_|ctl_reg_out_lo~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_state_alu~5 , z80_|execute_|ctl_state_alu~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_2u~1 , z80_|execute_|ctl_sw_2u~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_oe~1 , z80_|execute_|ctl_alu_oe~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mWrite~7 , z80_|execute_|ctl_mWrite~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_2u~4 , z80_|execute_|ctl_sw_2u~4, spectrum, 1 +instance = comp, \z80_|execute_|setM1~57 , z80_|execute_|setM1~57, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_2u~5 , z80_|execute_|ctl_sw_2u~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_out_lo~7 , z80_|execute_|ctl_reg_out_lo~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~0 , z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~41 , z80_|execute_|ctl_bus_inc_oe~41, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~86 , z80_|execute_|ctl_inc_cy~86, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~88 , z80_|execute_|ctl_inc_cy~88, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~36 , z80_|execute_|ctl_inc_cy~36, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~87 , z80_|execute_|ctl_inc_cy~87, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~26 , z80_|execute_|ctl_bus_inc_oe~26, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mWrite~9 , z80_|execute_|ctl_mWrite~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_we~1 , z80_|execute_|ctl_reg_sys_we~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~42 , z80_|execute_|ctl_bus_inc_oe~42, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal40~2 , z80_|pla_decode_|Equal40~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_pc~14 , z80_|execute_|ctl_reg_sel_pc~14, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal55~0 , z80_|pla_decode_|Equal55~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~11 , z80_|execute_|ctl_mRead~11, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal6~1 , z80_|pla_decode_|Equal6~1, spectrum, 1 +instance = comp, \z80_|execute_|setM1~36 , z80_|execute_|setM1~36, spectrum, 1 +instance = comp, \z80_|execute_|comb~1 , z80_|execute_|comb~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~13 , z80_|execute_|ctl_mRead~13, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~11 , z80_|execute_|ctl_reg_sys_hilo[1]~11, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal24~0 , z80_|pla_decode_|Equal24~0, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~26 , z80_|execute_|pc_inc_hold~26, spectrum, 1 +instance = comp, \z80_|execute_|setM1~37 , z80_|execute_|setM1~37, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~6 , z80_|execute_|pc_inc_hold~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo~38 , z80_|execute_|ctl_reg_sys_hilo~38, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~7 , z80_|execute_|fMRead~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~12 , z80_|execute_|ctl_mRead~12, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~31 , z80_|execute_|ctl_bus_inc_oe~31, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 , z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4, spectrum, 1 +instance = comp, \z80_|nM1_int~2 , z80_|nM1_int~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_4u~0 , z80_|execute_|ctl_sw_4u~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~10 , z80_|execute_|ctl_reg_sys_hilo[1]~10, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~6 , z80_|execute_|fMRead~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_dec~12 , z80_|execute_|ctl_inc_dec~12, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~15 , z80_|execute_|ctl_reg_sys_hilo[1]~15, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal25~0 , z80_|pla_decode_|Equal25~0, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal12~1 , z80_|pla_decode_|Equal12~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~38 , z80_|execute_|ctl_inc_cy~38, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~82 , z80_|execute_|ctl_inc_cy~82, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~14 , z80_|execute_|ctl_reg_sys_hilo[1]~14, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~16 , z80_|execute_|ctl_reg_sys_hilo[1]~16, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~32 , z80_|execute_|ctl_bus_inc_oe~32, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~77 , z80_|execute_|ctl_inc_cy~77, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal29~0 , z80_|pla_decode_|Equal29~0, spectrum, 1 instance = comp, \z80_|execute_|ctl_inc_cy~78 , z80_|execute_|ctl_inc_cy~78, spectrum, 1 instance = comp, \z80_|execute_|ctl_inc_cy~79 , z80_|execute_|ctl_inc_cy~79, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~80 , z80_|execute_|ctl_inc_cy~80, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~81 , z80_|execute_|ctl_inc_cy~81, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~82 , z80_|execute_|ctl_inc_cy~82, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~83 , z80_|execute_|ctl_inc_cy~83, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~84 , z80_|execute_|ctl_inc_cy~84, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~42 , z80_|execute_|pc_inc_hold~42, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~90 , z80_|execute_|ctl_inc_cy~90, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~41 , z80_|execute_|pc_inc_hold~41, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~66 , z80_|execute_|ctl_inc_cy~66, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~67 , z80_|execute_|ctl_inc_cy~67, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~68 , z80_|execute_|ctl_inc_cy~68, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~64 , z80_|execute_|ctl_inc_cy~64, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~63 , z80_|execute_|ctl_inc_cy~63, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~65 , z80_|execute_|ctl_inc_cy~65, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~69 , z80_|execute_|ctl_inc_cy~69, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~14 , z80_|execute_|ctl_mRead~14, spectrum, 1 instance = comp, \z80_|execute_|ctl_inc_cy~49 , z80_|execute_|ctl_inc_cy~49, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~50 , z80_|execute_|ctl_inc_cy~50, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~51 , z80_|execute_|ctl_inc_cy~51, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~52 , z80_|execute_|ctl_inc_cy~52, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~36 , z80_|execute_|ctl_inc_cy~36, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~37 , z80_|execute_|ctl_inc_cy~37, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~54 , z80_|execute_|ctl_inc_cy~54, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~41 , z80_|execute_|ctl_inc_cy~41, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~58 , z80_|execute_|ctl_inc_cy~58, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~55 , z80_|execute_|ctl_inc_cy~55, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~56 , z80_|execute_|ctl_inc_cy~56, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~89 , z80_|execute_|ctl_inc_cy~89, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~57 , z80_|execute_|ctl_inc_cy~57, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~59 , z80_|execute_|ctl_inc_cy~59, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~60 , z80_|execute_|ctl_inc_cy~60, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~47 , z80_|execute_|ctl_inc_cy~47, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~88 , z80_|execute_|ctl_inc_cy~88, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~48 , z80_|execute_|ctl_inc_cy~48, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~40 , z80_|execute_|pc_inc_hold~40, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~61 , z80_|execute_|ctl_inc_cy~61, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~62 , z80_|execute_|ctl_inc_cy~62, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~70 , z80_|execute_|ctl_inc_cy~70, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~85 , z80_|execute_|ctl_inc_cy~85, spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out, spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[0]~3 , z80_|reg_file_|db_lo_as[0]~3, spectrum, 1 -instance = comp, \z80_|address_latch_|abusz[0] , z80_|address_latch_|abusz[0], spectrum, 1 -instance = comp, \z80_|address_latch_|Q[0]~feeder , z80_|address_latch_|Q[0]~feeder, spectrum, 1 -instance = comp, \z80_|address_latch_|Q[0] , z80_|address_latch_|Q[0], spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 , z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ir_lo|latch[1] , z80_|reg_file_|b2v_latch_ir_lo|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_pc_lo|latch[1] , z80_|reg_file_|b2v_latch_pc_lo|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[1]~4 , z80_|reg_file_|db_lo_as[1]~4, spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[1]~5 , z80_|reg_file_|db_lo_as[1]~5, spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out, spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[1]~6 , z80_|reg_file_|db_lo_as[1]~6, spectrum, 1 -instance = comp, \z80_|address_latch_|abusz[1] , z80_|address_latch_|abusz[1], spectrum, 1 -instance = comp, \z80_|address_latch_|Q[1] , z80_|address_latch_|Q[1], spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4 , z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~4, spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out, spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[2]~9 , z80_|reg_file_|db_lo_as[2]~9, spectrum, 1 -instance = comp, \z80_|address_latch_|abusz[2] , z80_|address_latch_|abusz[2], spectrum, 1 -instance = comp, \z80_|address_latch_|Q[2]~feeder , z80_|address_latch_|Q[2]~feeder, spectrum, 1 -instance = comp, \z80_|address_latch_|Q[2] , z80_|address_latch_|Q[2], spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42 , z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_cy~86 , z80_|execute_|ctl_inc_cy~86, spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0 , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_inc_dec~11 , z80_|execute_|ctl_inc_dec~11, spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0 , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|carry_borrow_out~0, spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af2_lo|latch[3] , z80_|reg_file_|b2v_latch_af2_lo|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[3] , z80_|reg_file_|b2v_latch_af_lo|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[3]~45 , z80_|reg_file_|gdfx_temp0[3]~45, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder , z80_|reg_file_|b2v_latch_ix_lo|latch[3]~feeder, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ix_lo|latch[3] , z80_|reg_file_|b2v_latch_ix_lo|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc_lo|latch[3] , z80_|reg_file_|b2v_latch_bc_lo|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[3]~48 , z80_|reg_file_|gdfx_temp0[3]~48, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_iy_lo|latch[3] , z80_|reg_file_|b2v_latch_iy_lo|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_sp_lo|latch[3] , z80_|reg_file_|b2v_latch_sp_lo|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[3]~49 , z80_|reg_file_|gdfx_temp0[3]~49, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder , z80_|reg_file_|b2v_latch_wz_lo|latch[3]~feeder, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_wz_lo|latch[3] , z80_|reg_file_|b2v_latch_wz_lo|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] , z80_|reg_file_|b2v_latch_bc2_lo|latch[3], spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~41 , z80_|execute_|ctl_reg_gp_hilo[1]~41, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~42 , z80_|execute_|ctl_reg_gp_hilo[1]~42, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~43 , z80_|execute_|ctl_reg_gp_hilo[1]~43, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~5 , z80_|execute_|ctl_reg_gp_sel[1]~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~40 , z80_|execute_|ctl_bus_inc_oe~40, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~5 , z80_|execute_|ctl_mRead~5, spectrum, 1 instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~44 , z80_|execute_|ctl_reg_gp_hilo[1]~44, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~45 , z80_|execute_|ctl_reg_gp_hilo[1]~45, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~46 , z80_|execute_|ctl_reg_gp_hilo[1]~46, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_48 , z80_|reg_file_|SYNTHESIZED_WIRE_48, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_44 , z80_|reg_file_|SYNTHESIZED_WIRE_44, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_45 , z80_|reg_file_|SYNTHESIZED_WIRE_45, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de2_hi|latch[3] , z80_|reg_file_|b2v_latch_de2_hi|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_49 , z80_|reg_file_|SYNTHESIZED_WIRE_49, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de_hi|latch[3] , z80_|reg_file_|b2v_latch_de_hi|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[3]~40 , z80_|reg_file_|gdfx_temp1[3]~40, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_52 , z80_|reg_file_|SYNTHESIZED_WIRE_52, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_57 , z80_|reg_file_|SYNTHESIZED_WIRE_57, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl_hi|latch[3] , z80_|reg_file_|b2v_latch_hl_hi|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_53 , z80_|reg_file_|SYNTHESIZED_WIRE_53, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] , z80_|reg_file_|b2v_latch_hl2_hi|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_56 , z80_|reg_file_|SYNTHESIZED_WIRE_56, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[3]~41 , z80_|reg_file_|gdfx_temp1[3]~41, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_33 , z80_|reg_file_|SYNTHESIZED_WIRE_33, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_hi|latch[3] , z80_|reg_file_|b2v_latch_af_hi|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_hi|db[3]~18 , z80_|reg_file_|b2v_latch_af_hi|db[3]~18, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_in_hi~11 , z80_|execute_|ctl_reg_in_hi~11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_in_hi~12 , z80_|execute_|ctl_reg_in_hi~12, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_29 , z80_|reg_file_|SYNTHESIZED_WIRE_29, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af2_hi|latch[3] , z80_|reg_file_|b2v_latch_af2_hi|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_28 , z80_|reg_file_|SYNTHESIZED_WIRE_28, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[3]~44 , z80_|reg_file_|gdfx_temp1[3]~44, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder , z80_|reg_file_|b2v_latch_iy_hi|latch[3]~feeder, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_69 , z80_|reg_file_|SYNTHESIZED_WIRE_69, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_iy_hi|latch[3] , z80_|reg_file_|b2v_latch_iy_hi|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 , z80_|reg_file_|SYNTHESIZED_WIRE_68~2, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 , z80_|reg_file_|SYNTHESIZED_WIRE_64~0, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 , z80_|reg_file_|SYNTHESIZED_WIRE_69~2, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 , z80_|reg_file_|SYNTHESIZED_WIRE_65~0, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ix_hi|latch[3] , z80_|reg_file_|b2v_latch_ix_hi|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_68 , z80_|reg_file_|SYNTHESIZED_WIRE_68, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[3]~43 , z80_|reg_file_|gdfx_temp1[3]~43, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 , z80_|reg_file_|SYNTHESIZED_WIRE_76~0, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 , z80_|reg_file_|SYNTHESIZED_WIRE_77~0, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_sp_hi|latch[3] , z80_|reg_file_|b2v_latch_sp_hi|latch[3], spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~31 , z80_|execute_|ctl_reg_sys_hilo[1]~31, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~36 , z80_|execute_|ctl_bus_inc_oe~36, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~35 , z80_|execute_|ctl_bus_inc_oe~35, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~46 , z80_|execute_|ctl_bus_inc_oe~46, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~33 , z80_|execute_|ctl_bus_inc_oe~33, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~47 , z80_|execute_|ctl_bus_inc_oe~47, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 , z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~45 , z80_|execute_|ctl_bus_inc_oe~45, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~34 , z80_|execute_|ctl_bus_inc_oe~34, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 , z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mWrite~6 , z80_|execute_|ctl_mWrite~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~50 , z80_|execute_|ctl_bus_inc_oe~50, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal4~0 , z80_|pla_decode_|Equal4~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~48 , z80_|execute_|ctl_bus_inc_oe~48, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~49 , z80_|execute_|ctl_bus_inc_oe~49, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~7 , z80_|execute_|ctl_mRead~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~29 , z80_|execute_|ctl_bus_inc_oe~29, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_S~11 , z80_|execute_|ctl_alu_core_S~11, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~27 , z80_|execute_|ctl_bus_inc_oe~27, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~44 , z80_|execute_|ctl_bus_inc_oe~44, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~28 , z80_|execute_|ctl_bus_inc_oe~28, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~30 , z80_|execute_|ctl_bus_inc_oe~30, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~3 , z80_|execute_|ctl_mRead~3, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~3 , z80_|execute_|fMRead~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~37 , z80_|execute_|ctl_bus_inc_oe~37, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~38 , z80_|execute_|ctl_bus_inc_oe~38, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~39 , z80_|execute_|ctl_bus_inc_oe~39, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_inc_oe~43 , z80_|execute_|ctl_bus_inc_oe~43, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_oe~3 , z80_|execute_|ctl_alu_oe~3, spectrum, 1 +instance = comp, \z80_|execute_|fMWrite~1 , z80_|execute_|fMWrite~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_bus~1 , z80_|execute_|ctl_flags_bus~1, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~5 , z80_|execute_|fMRead~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~17 , z80_|execute_|ctl_mRead~17, spectrum, 1 +instance = comp, \z80_|execute_|ctl_iorw~10 , z80_|execute_|ctl_iorw~10, spectrum, 1 +instance = comp, \z80_|execute_|setM1~47 , z80_|execute_|setM1~47, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mWrite~8 , z80_|execute_|ctl_mWrite~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_al_we~13 , z80_|execute_|ctl_al_we~13, spectrum, 1 +instance = comp, \z80_|execute_|setM1~48 , z80_|execute_|setM1~48, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_4d~0 , z80_|execute_|ctl_sw_4d~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 , z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~9 , z80_|execute_|ctl_mRead~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_sz_we~3 , z80_|execute_|ctl_flags_sz_we~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 , z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_alu~9 , z80_|execute_|ctl_flags_alu~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~2 , z80_|execute_|ctl_alu_sel_op2_neg~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_alu~10 , z80_|execute_|ctl_flags_alu~10, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_xy_we~10 , z80_|execute_|ctl_flags_xy_we~10, spectrum, 1 +instance = comp, \z80_|execute_|ctl_pf_sel_pla11M1T1_11 , z80_|execute_|ctl_pf_sel_pla11M1T1_11, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_xy_we~11 , z80_|execute_|ctl_flags_xy_we~11, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_alu~11 , z80_|execute_|ctl_flags_alu~11, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_use_sp~1 , z80_|execute_|ctl_reg_use_sp~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_state_alu~4 , z80_|execute_|ctl_state_alu~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op2_sel_bus~9 , z80_|execute_|ctl_alu_op2_sel_bus~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_2d~4 , z80_|execute_|ctl_sw_2d~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_sz_we~0 , z80_|execute_|ctl_flags_sz_we~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_sz_we~4 , z80_|execute_|ctl_flags_sz_we~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~47 , z80_|execute_|ctl_alu_op_low~47, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~3 , z80_|execute_|ctl_alu_sel_op2_neg~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_alu~12 , z80_|execute_|ctl_flags_alu~12, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~23 , z80_|execute_|ctl_alu_op_low~23, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_xy_we~19 , z80_|execute_|ctl_flags_xy_we~19, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_alu~13 , z80_|execute_|ctl_flags_alu~13, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_out_hi~4 , z80_|execute_|ctl_reg_out_hi~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_4u~1 , z80_|execute_|ctl_sw_4u~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~29 , z80_|execute_|ctl_alu_op_low~29, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_alu~14 , z80_|execute_|ctl_flags_alu~14, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 , z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_pf_sel_pla82M1T1_16 , z80_|execute_|ctl_pf_sel_pla82M1T1_16, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_use_cf2~13 , z80_|execute_|ctl_flags_use_cf2~13, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf_we~7 , z80_|execute_|ctl_flags_cf_we~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_pf_sel[0]~2 , z80_|execute_|ctl_pf_sel[0]~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_hf_we~5 , z80_|execute_|ctl_flags_hf_we~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_pf_we~10 , z80_|execute_|ctl_flags_pf_we~10, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal68~2 , z80_|pla_decode_|Equal68~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~13 , z80_|execute_|ctl_reg_gp_hilo[1]~13, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_pf_we~2 , z80_|execute_|ctl_flags_pf_we~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_oe~4 , z80_|execute_|ctl_alu_oe~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_xy_we~8 , z80_|execute_|ctl_flags_xy_we~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_xy_we~20 , z80_|execute_|ctl_flags_xy_we~20, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_xy_we~9 , z80_|execute_|ctl_flags_xy_we~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_sz_we~1 , z80_|execute_|ctl_flags_sz_we~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_db_oe~1 , z80_|execute_|ctl_bus_db_oe~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op2_sel_bus~10 , z80_|execute_|ctl_alu_op2_sel_bus~10, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_sz_we~2 , z80_|execute_|ctl_flags_sz_we~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_alu~17 , z80_|execute_|ctl_flags_alu~17, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_alu~18 , z80_|execute_|ctl_flags_alu~18, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_alu~6 , z80_|execute_|ctl_flags_alu~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_alu~19 , z80_|execute_|ctl_flags_alu~19, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal1~5 , z80_|pla_decode_|Equal1~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_R~0 , z80_|execute_|ctl_alu_core_R~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2 , z80_|execute_|ctl_pf_sel_pla12M1T1_12~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_R~1 , z80_|execute_|ctl_alu_core_R~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_alu~7 , z80_|execute_|ctl_flags_alu~7, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sys_we_lo~5 , z80_|reg_control_|reg_sys_we_lo~5, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sys_we_lo~8 , z80_|reg_control_|reg_sys_we_lo~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_alu~8 , z80_|execute_|ctl_flags_alu~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_alu~15 , z80_|execute_|ctl_flags_alu~15, spectrum, 1 +instance = comp, \z80_|execute_|ctl_state_alu~7 , z80_|execute_|ctl_state_alu~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_state_alu~12 , z80_|execute_|ctl_state_alu~12, spectrum, 1 +instance = comp, \z80_|execute_|ctl_state_alu~9 , z80_|execute_|ctl_state_alu~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_state_alu~10 , z80_|execute_|ctl_state_alu~10, spectrum, 1 +instance = comp, \z80_|execute_|ctl_state_alu~8 , z80_|execute_|ctl_state_alu~8, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal64~0 , z80_|pla_decode_|Equal64~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_pf_sel[0]~3 , z80_|execute_|ctl_pf_sel[0]~3, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal62~2 , z80_|pla_decode_|Equal62~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_pf_we~4 , z80_|execute_|ctl_flags_pf_we~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~46 , z80_|execute_|ctl_alu_shift_oe~46, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_pf_we~6 , z80_|execute_|ctl_flags_pf_we~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_pf_we~7 , z80_|execute_|ctl_flags_pf_we~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_state_alu~11 , z80_|execute_|ctl_state_alu~11, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal62~3 , z80_|pla_decode_|Equal62~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_pf_we~5 , z80_|execute_|ctl_flags_pf_we~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_pf_we~3 , z80_|execute_|ctl_flags_pf_we~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_pf_we~8 , z80_|execute_|ctl_flags_pf_we~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_pf_we~9 , z80_|execute_|ctl_flags_pf_we~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_S~6 , z80_|execute_|ctl_alu_core_S~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_S~7 , z80_|execute_|ctl_alu_core_S~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_res_oe~1 , z80_|execute_|ctl_alu_res_oe~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_res_oe~0 , z80_|execute_|ctl_alu_res_oe~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_S~4 , z80_|execute_|ctl_alu_core_S~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_S~5 , z80_|execute_|ctl_alu_core_S~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_res_oe~2 , z80_|execute_|ctl_alu_res_oe~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 , z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sys_we_lo~6 , z80_|reg_control_|reg_sys_we_lo~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_xy_we~12 , z80_|execute_|ctl_flags_xy_we~12, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf_we~2 , z80_|execute_|ctl_flags_cf_we~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_res_oe~3 , z80_|execute_|ctl_alu_res_oe~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_sel_op2_high , z80_|execute_|ctl_alu_sel_op2_high, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op1_sel_zero~4 , z80_|execute_|ctl_alu_op1_sel_zero~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~12 , z80_|execute_|ctl_alu_core_hf~12, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal61~2 , z80_|pla_decode_|Equal61~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~4 , z80_|execute_|ctl_alu_sel_op2_neg~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~13 , z80_|execute_|ctl_alu_sel_op2_neg~13, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~14 , z80_|execute_|ctl_alu_sel_op2_neg~14, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~18 , z80_|execute_|ctl_alu_sel_op2_neg~18, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_bus~10 , z80_|execute_|ctl_flags_bus~10, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_bus~2 , z80_|execute_|ctl_flags_bus~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_bus~0 , z80_|execute_|ctl_flags_bus~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_bus~3 , z80_|execute_|ctl_flags_bus~3, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~26 , z80_|execute_|fMRead~26, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_bus , z80_|execute_|ctl_flags_bus, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_in_lo~9 , z80_|execute_|ctl_reg_in_lo~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op1_oe~0 , z80_|execute_|ctl_alu_op1_oe~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op1_oe~1 , z80_|execute_|ctl_alu_op1_oe~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_bs_oe~6 , z80_|execute_|ctl_alu_bs_oe~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_bs_oe~12 , z80_|execute_|ctl_alu_bs_oe~12, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_bs_oe~8 , z80_|execute_|ctl_alu_bs_oe~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_bs_oe~9 , z80_|execute_|ctl_alu_bs_oe~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_bs_oe , z80_|execute_|ctl_alu_bs_oe, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op2_oe~0 , z80_|execute_|ctl_alu_op2_oe~0, spectrum, 1 +instance = comp, \z80_|alu_|db_high[3]~0 , z80_|alu_|db_high[3]~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla83M1T3_2 , z80_|execute_|ctl_reg_gp_hilo_pla83M1T3_2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~15 , z80_|execute_|ctl_alu_shift_oe~15, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~38 , z80_|execute_|ctl_alu_shift_oe~38, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~28 , z80_|execute_|ctl_alu_op_low~28, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~6 , z80_|execute_|ctl_alu_op1_sel_bus~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~37 , z80_|execute_|ctl_alu_shift_oe~37, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~39 , z80_|execute_|ctl_alu_shift_oe~39, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf2_sel_daa , z80_|execute_|ctl_flags_cf2_sel_daa, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~7 , z80_|execute_|ctl_alu_op1_sel_bus~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~8 , z80_|execute_|ctl_alu_op1_sel_bus~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~30 , z80_|execute_|ctl_alu_op_low~30, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~31 , z80_|execute_|ctl_alu_op_low~31, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~25 , z80_|execute_|ctl_mRead~25, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~40 , z80_|execute_|ctl_alu_shift_oe~40, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~42 , z80_|execute_|ctl_alu_shift_oe~42, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 , z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op2_sel_bus~4 , z80_|execute_|ctl_alu_op2_sel_bus~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~47 , z80_|execute_|ctl_alu_shift_oe~47, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~34 , z80_|execute_|ctl_alu_shift_oe~34, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~35 , z80_|execute_|ctl_alu_shift_oe~35, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~36 , z80_|execute_|ctl_alu_shift_oe~36, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~28 , z80_|execute_|ctl_alu_shift_oe~28, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~44 , z80_|execute_|ctl_alu_shift_oe~44, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~29 , z80_|execute_|ctl_alu_shift_oe~29, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~16 , z80_|execute_|ctl_alu_shift_oe~16, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~27 , z80_|execute_|ctl_alu_shift_oe~27, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_bs_oe~10 , z80_|execute_|ctl_alu_bs_oe~10, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~31 , z80_|execute_|ctl_alu_shift_oe~31, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~30 , z80_|execute_|ctl_alu_shift_oe~30, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~32 , z80_|execute_|ctl_alu_shift_oe~32, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~33 , z80_|execute_|ctl_alu_shift_oe~33, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~21 , z80_|execute_|ctl_alu_shift_oe~21, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~45 , z80_|execute_|ctl_alu_shift_oe~45, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~22 , z80_|execute_|ctl_alu_shift_oe~22, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~23 , z80_|execute_|ctl_alu_shift_oe~23, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~24 , z80_|execute_|ctl_alu_shift_oe~24, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~25 , z80_|execute_|ctl_alu_shift_oe~25, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~26 , z80_|execute_|ctl_alu_shift_oe~26, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_shift_oe~43 , z80_|execute_|ctl_alu_shift_oe~43, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op1_sel_low , z80_|execute_|ctl_alu_op1_sel_low, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op1_sel_zero~5 , z80_|execute_|ctl_alu_op1_sel_zero~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op1_sel_zero , z80_|execute_|ctl_alu_op1_sel_zero, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~13 , z80_|execute_|ctl_alu_op1_sel_bus~13, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~17 , z80_|execute_|ctl_alu_op1_sel_bus~17, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~14 , z80_|execute_|ctl_alu_op1_sel_bus~14, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_R~3 , z80_|execute_|ctl_alu_core_R~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_R~4 , z80_|execute_|ctl_alu_core_R~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 , z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~9 , z80_|execute_|ctl_alu_op1_sel_bus~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~10 , z80_|execute_|ctl_alu_op1_sel_bus~10, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~11 , z80_|execute_|ctl_alu_op1_sel_bus~11, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~12 , z80_|execute_|ctl_alu_op1_sel_bus~12, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op1_sel_bus~15 , z80_|execute_|ctl_alu_op1_sel_bus~15, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9 , z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~6 , z80_|alu_|b2v_op1_latch_mux_low|Q[3]~6, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op1_latch_mux_low|ena , z80_|alu_|b2v_op1_latch_mux_low|ena, spectrum, 1 +instance = comp, \z80_|alu_|op1_low[3] , z80_|alu_|op1_low[3], spectrum, 1 +instance = comp, \z80_|alu_|db_low[3]~15 , z80_|alu_|db_low[3]~15, spectrum, 1 +instance = comp, \z80_|alu_|db_low[3]~16 , z80_|alu_|db_low[3]~16, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~33 , z80_|execute_|ctl_alu_op_low~33, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~34 , z80_|execute_|ctl_alu_op_low~34, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~48 , z80_|execute_|ctl_alu_op_low~48, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~35 , z80_|execute_|ctl_alu_op_low~35, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~36 , z80_|execute_|ctl_alu_op_low~36, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~37 , z80_|execute_|ctl_alu_op_low~37, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 , z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~38 , z80_|execute_|ctl_alu_op_low~38, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~39 , z80_|execute_|ctl_alu_op_low~39, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~40 , z80_|execute_|ctl_alu_op_low~40, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~41 , z80_|execute_|ctl_alu_op_low~41, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low , z80_|execute_|ctl_alu_op_low, spectrum, 1 +instance = comp, \z80_|alu_|result_lo[3] , z80_|alu_|result_lo[3], spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_oe~5 , z80_|execute_|ctl_alu_oe~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_oe~6 , z80_|execute_|ctl_alu_oe~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_oe~9 , z80_|execute_|ctl_alu_oe~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_S~12 , z80_|execute_|ctl_alu_core_S~12, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_oe~10 , z80_|execute_|ctl_alu_oe~10, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_oe~2 , z80_|execute_|ctl_alu_oe~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 , z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~15 , z80_|execute_|ctl_reg_gp_hilo[1]~15, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_in_hi~8 , z80_|execute_|ctl_reg_in_hi~8, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sys_we_lo~7 , z80_|reg_control_|reg_sys_we_lo~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_oe~7 , z80_|execute_|ctl_alu_oe~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mWrite~11 , z80_|execute_|ctl_mWrite~11, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_db_we~5 , z80_|execute_|ctl_bus_db_we~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_oe~8 , z80_|execute_|ctl_alu_oe~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_alu~16 , z80_|execute_|ctl_flags_alu~16, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_oe~11 , z80_|execute_|ctl_alu_oe~11, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~48 , z80_|execute_|ctl_reg_gp_hilo[1]~48, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_out_hi~8 , z80_|execute_|ctl_reg_out_hi~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_out_hi~5 , z80_|execute_|ctl_reg_out_hi~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_2u~2 , z80_|execute_|ctl_sw_2u~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_2u~0 , z80_|execute_|ctl_sw_2u~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_2u~3 , z80_|execute_|ctl_sw_2u~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~47 , z80_|execute_|ctl_reg_gp_hilo[1]~47, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~33 , z80_|execute_|ctl_inc_cy~33, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~37 , z80_|execute_|ctl_reg_sys_hilo[1]~37, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_2u~6 , z80_|execute_|ctl_sw_2u~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_out_hi~6 , z80_|execute_|ctl_reg_out_hi~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_out_hi~7 , z80_|execute_|ctl_reg_out_hi~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~2 , z80_|execute_|ctl_mRead~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_2d~6 , z80_|execute_|ctl_sw_2d~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_2d~7 , z80_|execute_|ctl_sw_2d~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 , z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_2d~8 , z80_|execute_|ctl_sw_2d~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_db_oe~7 , z80_|execute_|ctl_bus_db_oe~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_2d~5 , z80_|execute_|ctl_sw_2d~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~19 , z80_|execute_|ctl_mRead~19, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~18 , z80_|execute_|ctl_mRead~18, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sys_we_lo~2 , z80_|reg_control_|reg_sys_we_lo~2, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal24~1 , z80_|pla_decode_|Equal24~1, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sys_we_lo~3 , z80_|reg_control_|reg_sys_we_lo~3, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sys_we_lo~4 , z80_|reg_control_|reg_sys_we_lo~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~20 , z80_|execute_|ctl_mRead~20, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_in_hi~5 , z80_|execute_|ctl_reg_in_hi~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~22 , z80_|execute_|ctl_mRead~22, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 , z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_in_hi~6 , z80_|execute_|ctl_reg_in_hi~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_in_hi~2 , z80_|execute_|ctl_reg_in_hi~2, spectrum, 1 +instance = comp, \z80_|execute_|setM1~30 , z80_|execute_|setM1~30, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~23 , z80_|execute_|ctl_mRead~23, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~6 , z80_|execute_|ctl_reg_gp_sel[0]~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_in_hi~3 , z80_|execute_|ctl_reg_in_hi~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mWrite~10 , z80_|execute_|ctl_mWrite~10, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~18 , z80_|execute_|fMRead~18, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sel_pc~0 , z80_|reg_control_|reg_sel_pc~0, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sel_pc~1 , z80_|reg_control_|reg_sel_pc~1, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sel_pc~2 , z80_|reg_control_|reg_sel_pc~2, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~19 , z80_|execute_|fMRead~19, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~20 , z80_|execute_|fMRead~20, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~21 , z80_|execute_|fMRead~21, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_2d~9 , z80_|execute_|ctl_sw_2d~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_2d~14 , z80_|execute_|ctl_sw_2d~14, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_1d~8 , z80_|execute_|ctl_sw_1d~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_2d~10 , z80_|execute_|ctl_sw_2d~10, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_2d~11 , z80_|execute_|ctl_sw_2d~11, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_2d~12 , z80_|execute_|ctl_sw_2d~12, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_2d~13 , z80_|execute_|ctl_sw_2d~13, spectrum, 1 +instance = comp, \z80_|alu_|db[7]~9 , z80_|alu_|db[7]~9, spectrum, 1 +instance = comp, \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 , z80_|alu_control_|SYNTHESIZED_WIRE_2~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 , z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~32 , z80_|execute_|ctl_alu_op_low~32, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_nf~2 , z80_|alu_flags_|DFFE_inst_latch_nf~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_xy_we~22 , z80_|execute_|ctl_flags_xy_we~22, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_nf~3 , z80_|alu_flags_|DFFE_inst_latch_nf~3, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_nf~4 , z80_|alu_flags_|DFFE_inst_latch_nf~4, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_nf~5 , z80_|alu_flags_|DFFE_inst_latch_nf~5, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~12, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~13, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~15 , z80_|execute_|ctl_alu_core_hf~15, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_nf~6 , z80_|alu_flags_|DFFE_inst_latch_nf~6, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_nf~7 , z80_|alu_flags_|DFFE_inst_latch_nf~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 , z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 , z80_|alu_flags_|SYNTHESIZED_WIRE_5~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~17 , z80_|execute_|ctl_alu_sel_op2_neg~17, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 , z80_|alu_flags_|SYNTHESIZED_WIRE_5~1, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 , z80_|alu_flags_|SYNTHESIZED_WIRE_5~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_nf_we~3 , z80_|execute_|ctl_flags_nf_we~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_nf_we~0 , z80_|execute_|ctl_flags_nf_we~0, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal73~2 , z80_|pla_decode_|Equal73~2, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal72~2 , z80_|pla_decode_|Equal72~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_nf_we~1 , z80_|execute_|ctl_flags_nf_we~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_nf_we~2 , z80_|execute_|ctl_flags_nf_we~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_sz_we~5 , z80_|execute_|ctl_flags_sz_we~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_sz_we~6 , z80_|execute_|ctl_flags_sz_we~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_nf_we~4 , z80_|execute_|ctl_flags_nf_we~4, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_nf~8 , z80_|alu_flags_|DFFE_inst_latch_nf~8, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_nf , z80_|alu_flags_|DFFE_inst_latch_nf, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_hf_cpl~14 , z80_|execute_|ctl_flags_hf_cpl~14, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_hf_cpl~10 , z80_|execute_|ctl_flags_hf_cpl~10, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal45~0 , z80_|pla_decode_|Equal45~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_hf_cpl~11 , z80_|execute_|ctl_flags_hf_cpl~11, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_hf_cpl~12 , z80_|execute_|ctl_flags_hf_cpl~12, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_hf_cpl~13 , z80_|execute_|ctl_flags_hf_cpl~13, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_S~8 , z80_|execute_|ctl_alu_core_S~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_S~9 , z80_|execute_|ctl_alu_core_S~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_S~10 , z80_|execute_|ctl_alu_core_S~10, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_S , z80_|execute_|ctl_alu_core_S, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op1_latch_mux_high|Q[3] , z80_|alu_|b2v_op1_latch_mux_high|Q[3], spectrum, 1 +instance = comp, \z80_|alu_|b2v_op1_latch_mux_high|ena~0 , z80_|alu_|b2v_op1_latch_mux_high|ena~0, spectrum, 1 +instance = comp, \z80_|alu_|op1_high[3] , z80_|alu_|op1_high[3], spectrum, 1 +instance = comp, \z80_|alu_|alu_op1[3]~2 , z80_|alu_|alu_op1[3]~2, spectrum, 1 +instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 , z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_we_lo~2 , z80_|execute_|ctl_reg_sys_we_lo~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_we_lo~3 , z80_|execute_|ctl_reg_sys_we_lo~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_wz~14 , z80_|execute_|ctl_reg_sel_wz~14, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sys_we_hi~0 , z80_|reg_control_|reg_sys_we_hi~0, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal33~3 , z80_|pla_decode_|Equal33~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_we~0 , z80_|execute_|ctl_reg_sys_we~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_we~2 , z80_|execute_|ctl_reg_sys_we~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_we~3 , z80_|execute_|ctl_reg_sys_we~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_in_hi~4 , z80_|execute_|ctl_reg_in_hi~4, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sys_we_hi , z80_|reg_control_|reg_sys_we_hi, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~18 , z80_|execute_|ctl_reg_sys_hilo[1]~18, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo~17 , z80_|execute_|ctl_reg_sys_hilo~17, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_pc~11 , z80_|execute_|ctl_reg_sel_pc~11, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_pc~12 , z80_|execute_|ctl_reg_sel_pc~12, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_pc~13 , z80_|execute_|ctl_reg_sel_pc~13, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 , z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_wz~6 , z80_|execute_|ctl_reg_sel_wz~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_wz~7 , z80_|execute_|ctl_reg_sel_wz~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_wz~9 , z80_|execute_|ctl_reg_sel_wz~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~25 , z80_|execute_|ctl_reg_sys_hilo[1]~25, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_wz~8 , z80_|execute_|ctl_reg_sel_wz~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_al_we~5 , z80_|execute_|ctl_al_we~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_al_we~4 , z80_|execute_|ctl_al_we~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~41 , z80_|execute_|ctl_reg_sys_hilo[1]~41, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_wz~10 , z80_|execute_|ctl_reg_sel_wz~10, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo~21 , z80_|execute_|ctl_reg_sys_hilo~21, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_dec~3 , z80_|execute_|ctl_inc_dec~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~22 , z80_|execute_|ctl_reg_sys_hilo[1]~22, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~23 , z80_|execute_|ctl_reg_sys_hilo[1]~23, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~24 , z80_|execute_|ctl_reg_sys_hilo[1]~24, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~19 , z80_|execute_|ctl_reg_sys_hilo[1]~19, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~2 , z80_|execute_|fMRead~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~20 , z80_|execute_|ctl_reg_sys_hilo[1]~20, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~26 , z80_|execute_|ctl_reg_sys_hilo[1]~26, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~27 , z80_|execute_|ctl_reg_sys_hilo[1]~27, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~28 , z80_|execute_|ctl_reg_sys_hilo[1]~28, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~29 , z80_|execute_|ctl_reg_sys_hilo[1]~29, spectrum, 1 instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~30 , z80_|execute_|ctl_reg_sys_hilo[1]~30, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_wz~13 , z80_|execute_|ctl_reg_sel_wz~13, spectrum, 1 instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~32 , z80_|execute_|ctl_reg_sys_hilo[1]~32, spectrum, 1 instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~33 , z80_|execute_|ctl_reg_sys_hilo[1]~33, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sys_we_hi~0 , z80_|reg_control_|reg_sys_we_hi~0, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sys_we_hi , z80_|reg_control_|reg_sys_we_hi, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_81 , z80_|reg_file_|SYNTHESIZED_WIRE_81, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_wz_hi|latch[3] , z80_|reg_file_|b2v_latch_wz_hi|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_80 , z80_|reg_file_|SYNTHESIZED_WIRE_80, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[3]~45 , z80_|reg_file_|gdfx_temp1[3]~45, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 , z80_|reg_file_|SYNTHESIZED_WIRE_41~0, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc_hi|latch[3] , z80_|reg_file_|b2v_latch_bc_hi|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 , z80_|reg_file_|SYNTHESIZED_WIRE_36~0, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 , z80_|reg_file_|SYNTHESIZED_WIRE_37~0, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] , z80_|reg_file_|b2v_latch_bc2_hi|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 , z80_|reg_file_|SYNTHESIZED_WIRE_40~0, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[3]~42 , z80_|reg_file_|gdfx_temp1[3]~42, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[3]~46 , z80_|reg_file_|gdfx_temp1[3]~46, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[3]~47 , z80_|reg_file_|gdfx_temp1[3]~47, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[0]~17 , z80_|reg_file_|gdfx_temp1[0]~17, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[0]~18 , z80_|reg_file_|gdfx_temp1[0]~18, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[0]~19 , z80_|reg_file_|gdfx_temp1[0]~19, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[0]~16 , z80_|reg_file_|gdfx_temp1[0]~16, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[0]~20 , z80_|reg_file_|gdfx_temp1[0]~20, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~34 , z80_|execute_|ctl_reg_sys_hilo[1]~34, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~35 , z80_|execute_|ctl_reg_sys_hilo[1]~35, spectrum, 1 instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_73 , z80_|reg_file_|SYNTHESIZED_WIRE_73, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_pc_hi|latch[1] , z80_|reg_file_|b2v_latch_pc_hi|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de2_hi|latch[1] , z80_|reg_file_|b2v_latch_de2_hi|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de_hi|latch[1] , z80_|reg_file_|b2v_latch_de_hi|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[1]~8 , z80_|reg_file_|gdfx_temp1[1]~8, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_hi|latch[1] , z80_|reg_file_|b2v_latch_af_hi|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_hi|db[1]~15 , z80_|reg_file_|b2v_latch_af_hi|db[1]~15, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_sp_hi|latch[1] , z80_|reg_file_|b2v_latch_sp_hi|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_wz_hi|latch[1] , z80_|reg_file_|b2v_latch_wz_hi|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[1]~13 , z80_|reg_file_|gdfx_temp1[1]~13, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af2_hi|latch[1] , z80_|reg_file_|b2v_latch_af2_hi|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[1]~12 , z80_|reg_file_|gdfx_temp1[1]~12, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc_hi|latch[1] , z80_|reg_file_|b2v_latch_bc_hi|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] , z80_|reg_file_|b2v_latch_bc2_hi|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[1]~10 , z80_|reg_file_|gdfx_temp1[1]~10, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ix_hi|latch[1] , z80_|reg_file_|b2v_latch_ix_hi|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder , z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_iy_hi|latch[1] , z80_|reg_file_|b2v_latch_iy_hi|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[1]~11 , z80_|reg_file_|gdfx_temp1[1]~11, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[1]~14 , z80_|reg_file_|gdfx_temp1[1]~14, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] , z80_|reg_file_|b2v_latch_hl2_hi|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl_hi|latch[1] , z80_|reg_file_|b2v_latch_hl_hi|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[1]~9 , z80_|reg_file_|gdfx_temp1[1]~9, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[1]~15 , z80_|reg_file_|gdfx_temp1[1]~15, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[1]~21 , z80_|reg_file_|gdfx_temp1[1]~21, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_pc_hi|latch[3] , z80_|reg_file_|b2v_latch_pc_hi|latch[3], spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_ir~0 , z80_|execute_|ctl_reg_sel_ir~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_ir~1 , z80_|execute_|ctl_reg_sel_ir~1, spectrum, 1 instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_60 , z80_|reg_file_|SYNTHESIZED_WIRE_60, spectrum, 1 instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_61 , z80_|reg_file_|SYNTHESIZED_WIRE_61, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ir_hi|latch[1] , z80_|reg_file_|b2v_latch_ir_hi|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ir_hi|latch[3] , z80_|reg_file_|b2v_latch_ir_hi|latch[3], spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_we_lo~4 , z80_|execute_|ctl_reg_sys_we_lo~4, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sys_we_lo , z80_|reg_control_|reg_sys_we_lo, spectrum, 1 instance = comp, \z80_|reg_control_|reg_sw_4d_hi~0 , z80_|reg_control_|reg_sw_4d_hi~0, spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[1]~0 , z80_|reg_file_|db_hi_as[1]~0, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_72 , z80_|reg_file_|SYNTHESIZED_WIRE_72, spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[1]~1 , z80_|reg_file_|db_hi_as[1]~1, spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[0]~2 , z80_|reg_file_|db_hi_as[0]~2, spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[3]~10 , z80_|reg_file_|db_hi_as[3]~10, spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[3]~11 , z80_|reg_file_|db_hi_as[3]~11, spectrum, 1 +instance = comp, \z80_|address_latch_|abusz[11] , z80_|address_latch_|abusz[11], spectrum, 1 +instance = comp, \z80_|execute_|ctl_apin_mux~1 , z80_|execute_|ctl_apin_mux~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~37 , z80_|execute_|ctl_inc_cy~37, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_dec~2 , z80_|execute_|ctl_inc_dec~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~40 , z80_|execute_|ctl_inc_cy~40, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_dec~4 , z80_|execute_|ctl_inc_dec~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_dec~5 , z80_|execute_|ctl_inc_dec~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~4 , z80_|execute_|ctl_reg_gp_sel[1]~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 , z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4, spectrum, 1 +instance = comp, \z80_|execute_|setM1~42 , z80_|execute_|setM1~42, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~12 , z80_|execute_|ctl_reg_gp_hilo[1]~12, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_1d~4 , z80_|execute_|ctl_sw_1d~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_4d~3 , z80_|execute_|ctl_sw_4d~3, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~9 , z80_|execute_|fMRead~9, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~10 , z80_|execute_|fMRead~10, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~8 , z80_|execute_|fMRead~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_4d~2 , z80_|execute_|ctl_sw_4d~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_wz~11 , z80_|execute_|ctl_reg_sel_wz~11, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_wz~12 , z80_|execute_|ctl_reg_sel_wz~12, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_4d~4 , z80_|execute_|ctl_sw_4d~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_4d~5 , z80_|execute_|ctl_sw_4d~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_al_we~14 , z80_|execute_|ctl_al_we~14, spectrum, 1 +instance = comp, \z80_|execute_|ctl_al_we~10 , z80_|execute_|ctl_al_we~10, spectrum, 1 +instance = comp, \z80_|execute_|ctl_al_we~6 , z80_|execute_|ctl_al_we~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_al_we~7 , z80_|execute_|ctl_al_we~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_al_we~8 , z80_|execute_|ctl_al_we~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_al_we~9 , z80_|execute_|ctl_al_we~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_al_we~11 , z80_|execute_|ctl_al_we~11, spectrum, 1 +instance = comp, \z80_|execute_|ctl_al_we~12 , z80_|execute_|ctl_al_we~12, spectrum, 1 +instance = comp, \z80_|address_latch_|Q[11] , z80_|address_latch_|Q[11], spectrum, 1 +instance = comp, \z80_|execute_|fIOWrite~0 , z80_|execute_|fIOWrite~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_dec~8 , z80_|execute_|ctl_inc_dec~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_we~2 , z80_|execute_|ctl_reg_gp_we~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_dec~9 , z80_|execute_|ctl_inc_dec~9, spectrum, 1 +instance = comp, \z80_|address_latch_|abusz[1] , z80_|address_latch_|abusz[1], spectrum, 1 +instance = comp, \z80_|address_latch_|Q[1] , z80_|address_latch_|Q[1], spectrum, 1 +instance = comp, \z80_|execute_|ctl_apin_mux~0 , z80_|execute_|ctl_apin_mux~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_dec~6 , z80_|execute_|ctl_inc_dec~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_dec~7 , z80_|execute_|ctl_inc_dec~7, spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0 , z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_wz~21 , z80_|execute_|ctl_reg_sel_wz~21, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[0]~40 , z80_|execute_|ctl_reg_sys_hilo[0]~40, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~39 , z80_|execute_|ctl_reg_sys_hilo[1]~39, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[0]~13 , z80_|execute_|ctl_reg_sys_hilo[0]~13, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[0]~31 , z80_|execute_|ctl_reg_sys_hilo[0]~31, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_63 , z80_|reg_file_|SYNTHESIZED_WIRE_63, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ir_lo|latch[2] , z80_|reg_file_|b2v_latch_ir_lo|latch[2], spectrum, 1 +instance = comp, \z80_|execute_|setM1~49 , z80_|execute_|setM1~49, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf2_sel_shift~2 , z80_|execute_|ctl_flags_cf2_sel_shift~2, spectrum, 1 +instance = comp, \z80_|execute_|setM1~50 , z80_|execute_|setM1~50, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_oe~0 , z80_|execute_|ctl_flags_oe~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_oe~1 , z80_|execute_|ctl_flags_oe~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_in_hi~13 , z80_|execute_|ctl_reg_in_hi~13, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~12 , z80_|execute_|ctl_reg_gp_sel[0]~12, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_in_hi~7 , z80_|execute_|ctl_reg_in_hi~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_state_alu~13 , z80_|execute_|ctl_state_alu~13, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_we~6 , z80_|execute_|ctl_reg_gp_we~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_we~5 , z80_|execute_|ctl_reg_gp_we~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~17 , z80_|execute_|ctl_reg_gp_hilo[1]~17, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~18 , z80_|execute_|ctl_reg_gp_hilo[1]~18, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~10 , z80_|execute_|ctl_alu_sel_op2_neg~10, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_1d~9 , z80_|execute_|ctl_sw_1d~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_we~9 , z80_|execute_|ctl_reg_gp_we~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_we~4 , z80_|execute_|ctl_reg_gp_we~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_we~7 , z80_|execute_|ctl_reg_gp_we~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_we~3 , z80_|execute_|ctl_reg_gp_we~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~32 , z80_|execute_|ctl_reg_gp_hilo[1]~32, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_4u~2 , z80_|execute_|ctl_sw_4u~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_4u~3 , z80_|execute_|ctl_sw_4u~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_we~8 , z80_|execute_|ctl_reg_gp_we~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~14 , z80_|execute_|ctl_reg_gp_hilo[1]~14, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~24 , z80_|execute_|ctl_reg_gp_hilo[0]~24, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 , z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~25 , z80_|execute_|ctl_reg_gp_hilo[0]~25, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~26 , z80_|execute_|ctl_reg_gp_hilo[0]~26, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~46 , z80_|execute_|ctl_reg_gp_hilo[0]~46, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~27 , z80_|execute_|ctl_reg_gp_hilo[0]~27, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~29 , z80_|execute_|ctl_reg_gp_hilo[0]~29, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~22 , z80_|execute_|ctl_reg_gp_hilo[0]~22, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~23 , z80_|execute_|ctl_reg_gp_hilo[0]~23, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~31 , z80_|execute_|ctl_reg_gp_hilo[0]~31, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~33 , z80_|execute_|ctl_reg_gp_hilo[1]~33, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~26 , z80_|execute_|ctl_reg_gp_sel[1]~26, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~34 , z80_|execute_|ctl_reg_gp_hilo[1]~34, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~25 , z80_|execute_|ctl_reg_gp_sel[0]~25, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~20 , z80_|execute_|ctl_reg_gp_hilo[1]~20, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~21 , z80_|execute_|ctl_reg_gp_hilo[0]~21, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[0]~35 , z80_|execute_|ctl_reg_gp_hilo[0]~35, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal2~2 , z80_|pla_decode_|Equal2~2, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal1~6 , z80_|pla_decode_|Equal1~6, spectrum, 1 +instance = comp, \z80_|reg_control_|bank_exx~2 , z80_|reg_control_|bank_exx~2, spectrum, 1 +instance = comp, \z80_|reg_control_|bank_exx , z80_|reg_control_|bank_exx, spectrum, 1 +instance = comp, \z80_|reg_control_|bank_hl_de1~0 , z80_|reg_control_|bank_hl_de1~0, spectrum, 1 +instance = comp, \z80_|reg_control_|bank_hl_de1 , z80_|reg_control_|bank_hl_de1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~19 , z80_|execute_|ctl_reg_gp_hilo[1]~19, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~28 , z80_|execute_|ctl_reg_gp_sel[0]~28, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~29 , z80_|execute_|ctl_reg_gp_sel[0]~29, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~30 , z80_|execute_|ctl_reg_gp_sel[0]~30, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~13 , z80_|execute_|ctl_reg_gp_sel[0]~13, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~45 , z80_|execute_|ctl_reg_gp_hilo[1]~45, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_use_sp~2 , z80_|execute_|ctl_reg_use_sp~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_use_sp~3 , z80_|execute_|ctl_reg_use_sp~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~14 , z80_|execute_|ctl_reg_gp_sel[0]~14, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~32 , z80_|execute_|ctl_reg_gp_sel[0]~32, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~33 , z80_|execute_|ctl_reg_gp_sel[0]~33, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~16 , z80_|execute_|ctl_reg_gp_hilo[1]~16, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~34 , z80_|execute_|ctl_reg_gp_sel[0]~34, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[0]~35 , z80_|execute_|ctl_reg_gp_sel[0]~35, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~20 , z80_|execute_|ctl_reg_gp_sel[1]~20, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~21 , z80_|execute_|ctl_reg_gp_sel[1]~21, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~22 , z80_|execute_|ctl_reg_gp_sel[1]~22, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~18 , z80_|execute_|ctl_reg_gp_sel[1]~18, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~37 , z80_|execute_|ctl_reg_gp_sel[1]~37, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~19 , z80_|execute_|ctl_reg_gp_sel[1]~19, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~23 , z80_|execute_|ctl_reg_gp_sel[1]~23, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~16 , z80_|execute_|ctl_reg_gp_sel[1]~16, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~17 , z80_|execute_|ctl_reg_gp_sel[1]~17, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~11 , z80_|execute_|ctl_reg_gp_sel[1]~11, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~36 , z80_|execute_|ctl_reg_gp_sel[1]~36, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~8 , z80_|execute_|ctl_reg_gp_sel[1]~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~9 , z80_|execute_|ctl_reg_gp_sel[1]~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~10 , z80_|execute_|ctl_reg_gp_sel[1]~10, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~15 , z80_|execute_|ctl_reg_gp_sel[1]~15, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel[1]~31 , z80_|execute_|ctl_reg_gp_sel[1]~31, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sel_de2~5 , z80_|reg_control_|reg_sel_de2~5, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sel_de2~6 , z80_|reg_control_|reg_sel_de2~6, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sel_de~0 , z80_|reg_control_|reg_sel_de~0, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_50 , z80_|reg_file_|SYNTHESIZED_WIRE_50, spectrum, 1 +instance = comp, \z80_|reg_control_|bank_hl_de2~0 , z80_|reg_control_|bank_hl_de2~0, spectrum, 1 +instance = comp, \z80_|reg_control_|bank_hl_de2 , z80_|reg_control_|bank_hl_de2, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sel_de2~4 , z80_|reg_control_|reg_sel_de2~4, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_46 , z80_|reg_file_|SYNTHESIZED_WIRE_46, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_47 , z80_|reg_file_|SYNTHESIZED_WIRE_47, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de2_lo|latch[2] , z80_|reg_file_|b2v_latch_de2_lo|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_51 , z80_|reg_file_|SYNTHESIZED_WIRE_51, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de_lo|latch[2] , z80_|reg_file_|b2v_latch_de_lo|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[2]~33 , z80_|reg_file_|gdfx_temp0[2]~33, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sel_hl~0 , z80_|reg_control_|reg_sel_hl~0, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_59 , z80_|reg_file_|SYNTHESIZED_WIRE_59, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl_lo|latch[2] , z80_|reg_file_|b2v_latch_hl_lo|latch[2], spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sel_hl2~0 , z80_|reg_control_|reg_sel_hl2~0, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_54 , z80_|reg_file_|SYNTHESIZED_WIRE_54, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_55 , z80_|reg_file_|SYNTHESIZED_WIRE_55, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] , z80_|reg_file_|b2v_latch_hl2_lo|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_58 , z80_|reg_file_|SYNTHESIZED_WIRE_58, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[2]~34 , z80_|reg_file_|gdfx_temp0[2]~34, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 , z80_|reg_file_|SYNTHESIZED_WIRE_70~2, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 , z80_|reg_file_|SYNTHESIZED_WIRE_38~0, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 , z80_|reg_file_|SYNTHESIZED_WIRE_71~2, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 , z80_|reg_file_|SYNTHESIZED_WIRE_43~0, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc_lo|latch[2] , z80_|reg_file_|b2v_latch_bc_lo|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 , z80_|reg_file_|SYNTHESIZED_WIRE_39~0, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] , z80_|reg_file_|b2v_latch_bc2_lo|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 , z80_|reg_file_|SYNTHESIZED_WIRE_42~0, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[2]~36 , z80_|reg_file_|gdfx_temp0[2]~36, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_wz~15 , z80_|execute_|ctl_reg_sel_wz~15, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_wz~18 , z80_|execute_|ctl_reg_sel_wz~18, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_83 , z80_|reg_file_|SYNTHESIZED_WIRE_83, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_wz_lo|latch[2] , z80_|reg_file_|b2v_latch_wz_lo|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_82 , z80_|reg_file_|SYNTHESIZED_WIRE_82, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[2]~37 , z80_|reg_file_|gdfx_temp0[2]~37, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 , z80_|reg_file_|SYNTHESIZED_WIRE_66~0, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sel_iy~2 , z80_|reg_control_|reg_sel_iy~2, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_71 , z80_|reg_file_|SYNTHESIZED_WIRE_71, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_iy_lo|latch[2] , z80_|reg_file_|b2v_latch_iy_lo|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 , z80_|reg_file_|SYNTHESIZED_WIRE_67~0, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ix_lo|latch[2] , z80_|reg_file_|b2v_latch_ix_lo|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_70 , z80_|reg_file_|SYNTHESIZED_WIRE_70, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[2]~38 , z80_|reg_file_|gdfx_temp0[2]~38, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 , z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_in_hi~9 , z80_|execute_|ctl_reg_in_hi~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_in_hi~10 , z80_|execute_|ctl_reg_in_hi~10, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_in_lo~8 , z80_|execute_|ctl_reg_in_lo~8, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_sp_lo|latch[2]~feeder , z80_|reg_file_|b2v_latch_sp_lo|latch[2]~feeder, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_use_sp~4 , z80_|execute_|ctl_reg_use_sp~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_use_sp~5 , z80_|execute_|ctl_reg_use_sp~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_use_sp~6 , z80_|execute_|ctl_reg_use_sp~6, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 , z80_|reg_file_|SYNTHESIZED_WIRE_79~0, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_sp_lo|latch[2] , z80_|reg_file_|b2v_latch_sp_lo|latch[2], spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_1d~5 , z80_|execute_|ctl_sw_1d~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_im_we , z80_|execute_|ctl_im_we, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_1d~6 , z80_|execute_|ctl_sw_1d~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_1d~7 , z80_|execute_|ctl_sw_1d~7, spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_ds[2]~2 , z80_|reg_file_|db_lo_ds[2]~2, spectrum, 1 +instance = comp, \z80_|alu_control_|db[2]~28 , z80_|alu_control_|db[2]~28, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_in_hi~11 , z80_|execute_|ctl_reg_in_hi~11, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_in_hi~12 , z80_|execute_|ctl_reg_in_hi~12, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~42 , z80_|execute_|ctl_reg_gp_hilo[1]~42, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~39 , z80_|execute_|ctl_reg_gp_hilo[1]~39, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~38 , z80_|execute_|ctl_reg_gp_hilo[1]~38, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~40 , z80_|execute_|ctl_reg_gp_hilo[1]~40, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~41 , z80_|execute_|ctl_reg_gp_hilo[1]~41, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_hilo[1]~43 , z80_|execute_|ctl_reg_gp_hilo[1]~43, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 , z80_|reg_file_|SYNTHESIZED_WIRE_68~2, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 , z80_|reg_file_|SYNTHESIZED_WIRE_64~0, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 , z80_|reg_file_|SYNTHESIZED_WIRE_76~0, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_68 , z80_|reg_file_|SYNTHESIZED_WIRE_68, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 , z80_|reg_file_|SYNTHESIZED_WIRE_40~0, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 , z80_|reg_file_|SYNTHESIZED_WIRE_36~0, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[0]~18 , z80_|reg_file_|gdfx_temp1[0]~18, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_80 , z80_|reg_file_|SYNTHESIZED_WIRE_80, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal21~2 , z80_|pla_decode_|Equal21~2, spectrum, 1 +instance = comp, \z80_|reg_control_|bank_af~0 , z80_|reg_control_|bank_af~0, spectrum, 1 +instance = comp, \z80_|reg_control_|bank_af , z80_|reg_control_|bank_af, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sel_af~0 , z80_|reg_control_|reg_sel_af~0, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sel_af2~0 , z80_|reg_control_|reg_sel_af2~0, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_28 , z80_|reg_file_|SYNTHESIZED_WIRE_28, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[0]~17 , z80_|reg_file_|gdfx_temp1[0]~17, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[0]~19 , z80_|reg_file_|gdfx_temp1[0]~19, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_52 , z80_|reg_file_|SYNTHESIZED_WIRE_52, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_44 , z80_|reg_file_|SYNTHESIZED_WIRE_44, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_48 , z80_|reg_file_|SYNTHESIZED_WIRE_48, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_56 , z80_|reg_file_|SYNTHESIZED_WIRE_56, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[0]~16 , z80_|reg_file_|gdfx_temp1[0]~16, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[0]~20 , z80_|reg_file_|gdfx_temp1[0]~20, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 , z80_|reg_file_|SYNTHESIZED_WIRE_69~2, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 , z80_|reg_file_|SYNTHESIZED_WIRE_65~0, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ix_hi|latch[2] , z80_|reg_file_|b2v_latch_ix_hi|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_69 , z80_|reg_file_|SYNTHESIZED_WIRE_69, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_iy_hi|latch[2] , z80_|reg_file_|b2v_latch_iy_hi|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[2]~34 , z80_|reg_file_|gdfx_temp1[2]~34, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 , z80_|reg_file_|SYNTHESIZED_WIRE_77~0, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_sp_hi|latch[2] , z80_|reg_file_|b2v_latch_sp_hi|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_81 , z80_|reg_file_|SYNTHESIZED_WIRE_81, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_wz_hi|latch[2] , z80_|reg_file_|b2v_latch_wz_hi|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[2]~36 , z80_|reg_file_|gdfx_temp1[2]~36, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_29 , z80_|reg_file_|SYNTHESIZED_WIRE_29, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af2_hi|latch[2] , z80_|reg_file_|b2v_latch_af2_hi|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[2]~35 , z80_|reg_file_|gdfx_temp1[2]~35, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 , z80_|reg_file_|SYNTHESIZED_WIRE_37~0, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] , z80_|reg_file_|b2v_latch_bc2_hi|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 , z80_|reg_file_|SYNTHESIZED_WIRE_41~0, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc_hi|latch[2] , z80_|reg_file_|b2v_latch_bc_hi|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[2]~33 , z80_|reg_file_|gdfx_temp1[2]~33, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[2]~37 , z80_|reg_file_|gdfx_temp1[2]~37, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_45 , z80_|reg_file_|SYNTHESIZED_WIRE_45, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de2_hi|latch[2] , z80_|reg_file_|b2v_latch_de2_hi|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder , z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_49 , z80_|reg_file_|SYNTHESIZED_WIRE_49, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de_hi|latch[2] , z80_|reg_file_|b2v_latch_de_hi|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[2]~31 , z80_|reg_file_|gdfx_temp1[2]~31, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_33 , z80_|reg_file_|SYNTHESIZED_WIRE_33, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_hi|latch[2] , z80_|reg_file_|b2v_latch_af_hi|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_hi|db[2]~12 , z80_|reg_file_|b2v_latch_af_hi|db[2]~12, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_57 , z80_|reg_file_|SYNTHESIZED_WIRE_57, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl_hi|latch[2] , z80_|reg_file_|b2v_latch_hl_hi|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_53 , z80_|reg_file_|SYNTHESIZED_WIRE_53, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] , z80_|reg_file_|b2v_latch_hl2_hi|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[2]~32 , z80_|reg_file_|gdfx_temp1[2]~32, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[2]~38 , z80_|reg_file_|gdfx_temp1[2]~38, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_dec~11 , z80_|execute_|ctl_inc_dec~11, spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_pc_hi|latch[1] , z80_|reg_file_|b2v_latch_pc_hi|latch[1], spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf2_sel_shift~5 , z80_|execute_|ctl_flags_cf2_sel_shift~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf2_sel_shift~3 , z80_|execute_|ctl_flags_cf2_sel_shift~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf2_sel_shift~4 , z80_|execute_|ctl_flags_cf2_sel_shift~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf_cpl~4 , z80_|execute_|ctl_flags_cf_cpl~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf_cpl~5 , z80_|execute_|ctl_flags_cf_cpl~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~16 , z80_|execute_|ctl_alu_sel_op2_neg~16, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf_cpl~6 , z80_|execute_|ctl_flags_cf_cpl~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf_cpl~7 , z80_|execute_|ctl_flags_cf_cpl~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf_cpl~10 , z80_|execute_|ctl_flags_cf_cpl~10, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf_cpl~8 , z80_|execute_|ctl_flags_cf_cpl~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 , z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~42 , z80_|execute_|ctl_alu_op_low~42, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf_cpl~9 , z80_|execute_|ctl_flags_cf_cpl~9, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~5, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~6, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mWrite~18 , z80_|execute_|ctl_mWrite~18, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~1, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~2, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf_cpl~2 , z80_|execute_|ctl_flags_cf_cpl~2, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~0, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~4, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf2_we~4 , z80_|execute_|ctl_flags_cf2_we~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf2_we~2 , z80_|execute_|ctl_flags_cf2_we~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf2_we~3 , z80_|execute_|ctl_flags_cf2_we~3, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_hi|latch[6] , z80_|reg_file_|b2v_latch_af_hi|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_32 , z80_|reg_file_|SYNTHESIZED_WIRE_32, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_wz_hi|latch[6] , z80_|reg_file_|b2v_latch_wz_hi|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_sp_hi|latch[6] , z80_|reg_file_|b2v_latch_sp_hi|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[6]~81 , z80_|reg_file_|gdfx_temp1[6]~81, spectrum, 1 +instance = comp, \z80_|alu_|db_high[2]~8 , z80_|alu_|db_high[2]~8, spectrum, 1 +instance = comp, \z80_|alu_|db_high[2]~9 , z80_|alu_|db_high[2]~9, spectrum, 1 +instance = comp, \z80_|alu_|db_high[2]~11 , z80_|alu_|db_high[2]~11, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op1_latch_mux_high|Q[2] , z80_|alu_|b2v_op1_latch_mux_high|Q[2], spectrum, 1 +instance = comp, \z80_|alu_|op1_high[2] , z80_|alu_|op1_high[2], spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op2_sel_lq , z80_|execute_|ctl_alu_op2_sel_lq, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2 , z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op2_sel_bus~5 , z80_|execute_|ctl_alu_op2_sel_bus~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op2_sel_bus~6 , z80_|execute_|ctl_alu_op2_sel_bus~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op2_sel_bus~7 , z80_|execute_|ctl_alu_op2_sel_bus~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op2_sel_bus~8 , z80_|execute_|ctl_alu_op2_sel_bus~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op2_sel_zero , z80_|execute_|ctl_alu_op2_sel_zero, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 , z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op2_latch_mux_high|ena , z80_|alu_|b2v_op2_latch_mux_high|ena, spectrum, 1 +instance = comp, \z80_|alu_|op2_high[2] , z80_|alu_|op2_high[2], spectrum, 1 +instance = comp, \z80_|alu_|db_high[2]~10 , z80_|alu_|db_high[2]~10, spectrum, 1 +instance = comp, \z80_|alu_|db_high[2]~12 , z80_|alu_|db_high[2]~12, spectrum, 1 +instance = comp, \z80_|alu_|db_high[3]~1 , z80_|alu_|db_high[3]~1, spectrum, 1 +instance = comp, \z80_|alu_|db_high[2]~13 , z80_|alu_|db_high[2]~13, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_iy_lo|latch[6] , z80_|reg_file_|b2v_latch_iy_lo|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ix_lo|latch[6] , z80_|reg_file_|b2v_latch_ix_lo|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[6]~78 , z80_|reg_file_|gdfx_temp0[6]~78, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 , z80_|reg_file_|SYNTHESIZED_WIRE_78~0, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_sp_lo|latch[6] , z80_|reg_file_|b2v_latch_sp_lo|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[6]~79 , z80_|reg_file_|gdfx_temp0[6]~79, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_34 , z80_|reg_file_|SYNTHESIZED_WIRE_34, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder , z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_35 , z80_|reg_file_|SYNTHESIZED_WIRE_35, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[6] , z80_|reg_file_|b2v_latch_af_lo|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_31 , z80_|reg_file_|SYNTHESIZED_WIRE_31, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af2_lo|latch[6] , z80_|reg_file_|b2v_latch_af2_lo|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_30 , z80_|reg_file_|SYNTHESIZED_WIRE_30, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[6]~75 , z80_|reg_file_|gdfx_temp0[6]~75, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder , z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc_lo|latch[6] , z80_|reg_file_|b2v_latch_bc_lo|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] , z80_|reg_file_|b2v_latch_bc2_lo|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[6]~76 , z80_|reg_file_|gdfx_temp0[6]~76, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_wz_lo|latch[6] , z80_|reg_file_|b2v_latch_wz_lo|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[6]~77 , z80_|reg_file_|gdfx_temp0[6]~77, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[6]~80 , z80_|reg_file_|gdfx_temp0[6]~80, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl_lo|latch[6] , z80_|reg_file_|b2v_latch_hl_lo|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] , z80_|reg_file_|b2v_latch_hl2_lo|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[6]~74 , z80_|reg_file_|gdfx_temp0[6]~74, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de_lo|latch[6] , z80_|reg_file_|b2v_latch_de_lo|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de2_lo|latch[6] , z80_|reg_file_|b2v_latch_de2_lo|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[6]~73 , z80_|reg_file_|gdfx_temp0[6]~73, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[6]~81 , z80_|reg_file_|gdfx_temp0[6]~81, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[0]~19 , z80_|reg_file_|gdfx_temp0[0]~19, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[0]~18 , z80_|reg_file_|gdfx_temp0[0]~18, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[0]~20 , z80_|reg_file_|gdfx_temp0[0]~20, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[0]~92 , z80_|reg_file_|gdfx_temp0[0]~92, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[0]~21 , z80_|reg_file_|gdfx_temp0[0]~21, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_74 , z80_|reg_file_|SYNTHESIZED_WIRE_74, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_62 , z80_|reg_file_|SYNTHESIZED_WIRE_62, spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[0]~2 , z80_|reg_file_|db_lo_as[0]~2, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ir_lo|latch[4] , z80_|reg_file_|b2v_latch_ir_lo|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_iy_lo|latch[4] , z80_|reg_file_|b2v_latch_iy_lo|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_sp_lo|latch[4] , z80_|reg_file_|b2v_latch_sp_lo|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[4]~55 , z80_|reg_file_|gdfx_temp0[4]~55, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ix_lo|latch[4] , z80_|reg_file_|b2v_latch_ix_lo|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[4]~56 , z80_|reg_file_|gdfx_temp0[4]~56, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl_lo|latch[4] , z80_|reg_file_|b2v_latch_hl_lo|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] , z80_|reg_file_|b2v_latch_hl2_lo|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[4]~57 , z80_|reg_file_|gdfx_temp0[4]~57, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc_lo|latch[4] , z80_|reg_file_|b2v_latch_bc_lo|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] , z80_|reg_file_|b2v_latch_bc2_lo|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[4]~59 , z80_|reg_file_|gdfx_temp0[4]~59, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[4] , z80_|reg_file_|b2v_latch_af_lo|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af2_lo|latch[4] , z80_|reg_file_|b2v_latch_af2_lo|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[4]~58 , z80_|reg_file_|gdfx_temp0[4]~58, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_wz_lo|latch[4] , z80_|reg_file_|b2v_latch_wz_lo|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[4]~60 , z80_|reg_file_|gdfx_temp0[4]~60, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de2_lo|latch[4] , z80_|reg_file_|b2v_latch_de2_lo|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de_lo|latch[4] , z80_|reg_file_|b2v_latch_de_lo|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[4]~53 , z80_|reg_file_|gdfx_temp0[4]~53, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[4]~54 , z80_|reg_file_|gdfx_temp0[4]~54, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[4]~61 , z80_|reg_file_|gdfx_temp0[4]~61, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[4]~62 , z80_|reg_file_|gdfx_temp0[4]~62, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_75 , z80_|reg_file_|SYNTHESIZED_WIRE_75, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_pc_lo|latch[4] , z80_|reg_file_|b2v_latch_pc_lo|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[4]~13 , z80_|reg_file_|db_lo_as[4]~13, spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[4]~14 , z80_|reg_file_|db_lo_as[4]~14, spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out, spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[4]~15 , z80_|reg_file_|db_lo_as[4]~15, spectrum, 1 +instance = comp, \z80_|address_latch_|abusz[4] , z80_|address_latch_|abusz[4], spectrum, 1 +instance = comp, \z80_|address_latch_|Q[4] , z80_|address_latch_|Q[4], spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ir_lo|latch[5] , z80_|reg_file_|b2v_latch_ir_lo|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl_lo|latch[5] , z80_|reg_file_|b2v_latch_hl_lo|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] , z80_|reg_file_|b2v_latch_hl2_lo|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[5]~64 , z80_|reg_file_|gdfx_temp0[5]~64, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de2_lo|latch[5] , z80_|reg_file_|b2v_latch_de2_lo|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de_lo|latch[5] , z80_|reg_file_|b2v_latch_de_lo|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[5]~63 , z80_|reg_file_|gdfx_temp0[5]~63, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af2_lo|latch[5] , z80_|reg_file_|b2v_latch_af2_lo|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[5]~feeder , z80_|reg_file_|b2v_latch_af_lo|latch[5]~feeder, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[5] , z80_|reg_file_|b2v_latch_af_lo|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[5]~65 , z80_|reg_file_|gdfx_temp0[5]~65, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_iy_lo|latch[5] , z80_|reg_file_|b2v_latch_iy_lo|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_sp_lo|latch[5] , z80_|reg_file_|b2v_latch_sp_lo|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[5]~69 , z80_|reg_file_|gdfx_temp0[5]~69, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ix_lo|latch[5] , z80_|reg_file_|b2v_latch_ix_lo|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc_lo|latch[5] , z80_|reg_file_|b2v_latch_bc_lo|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[5]~68 , z80_|reg_file_|gdfx_temp0[5]~68, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_wz_lo|latch[5] , z80_|reg_file_|b2v_latch_wz_lo|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] , z80_|reg_file_|b2v_latch_bc2_lo|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[5]~66 , z80_|reg_file_|gdfx_temp0[5]~66, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[5]~67 , z80_|reg_file_|gdfx_temp0[5]~67, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[5]~70 , z80_|reg_file_|gdfx_temp0[5]~70, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[5]~71 , z80_|reg_file_|gdfx_temp0[5]~71, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[5]~72 , z80_|reg_file_|gdfx_temp0[5]~72, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_pc_lo|latch[5] , z80_|reg_file_|b2v_latch_pc_lo|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[5]~16 , z80_|reg_file_|db_lo_as[5]~16, spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[5]~17 , z80_|reg_file_|db_lo_as[5]~17, spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[5]~18 , z80_|reg_file_|db_lo_as[5]~18, spectrum, 1 +instance = comp, \z80_|address_latch_|abusz[5] , z80_|address_latch_|abusz[5], spectrum, 1 +instance = comp, \z80_|address_latch_|Q[5] , z80_|address_latch_|Q[5], spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_dec~10 , z80_|execute_|ctl_inc_dec~10, spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4 , z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4, spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 , z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44, spectrum, 1 +instance = comp, \z80_|address_latch_|abusz[6] , z80_|address_latch_|abusz[6], spectrum, 1 +instance = comp, \z80_|address_latch_|Q[6] , z80_|address_latch_|Q[6], spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|address[6] , z80_|address_latch_|b2v_inst_inc_dec|address[6], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ir_lo|latch[6] , z80_|reg_file_|b2v_latch_ir_lo|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_pc_lo|latch[6] , z80_|reg_file_|b2v_latch_pc_lo|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[6]~19 , z80_|reg_file_|db_lo_as[6]~19, spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[6]~20 , z80_|reg_file_|db_lo_as[6]~20, spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[6]~21 , z80_|reg_file_|db_lo_as[6]~21, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[6]~82 , z80_|reg_file_|gdfx_temp0[6]~82, spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_ds[6]~0 , z80_|reg_file_|db_lo_ds[6]~0, spectrum, 1 +instance = comp, \z80_|sw1_|db_down[6]~1 , z80_|sw1_|db_down[6]~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_66_oe , z80_|execute_|ctl_66_oe, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op1_latch_mux_high|Q[1] , z80_|alu_|b2v_op1_latch_mux_high|Q[1], spectrum, 1 +instance = comp, \z80_|alu_|op1_high[1] , z80_|alu_|op1_high[1], spectrum, 1 +instance = comp, \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~4 , z80_|alu_|b2v_op2_latch_mux_high|Q[1]~4, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5 , z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5, spectrum, 1 +instance = comp, \z80_|alu_|op2_high[1] , z80_|alu_|op2_high[1], spectrum, 1 +instance = comp, \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~2 , z80_|alu_|b2v_op2_latch_mux_low|Q[1]~2, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~3 , z80_|alu_|b2v_op2_latch_mux_low|Q[1]~3, spectrum, 1 +instance = comp, \z80_|alu_|op2_low[1] , z80_|alu_|op2_low[1], spectrum, 1 +instance = comp, \z80_|alu_|alu_op2[1]~1 , z80_|alu_|alu_op2[1]~1, spectrum, 1 +instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 , z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1, spectrum, 1 +instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0, spectrum, 1 +instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_R~5 , z80_|execute_|ctl_alu_core_R~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_R~2 , z80_|execute_|ctl_alu_core_R~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_R , z80_|execute_|ctl_alu_core_R, spectrum, 1 +instance = comp, \z80_|alu_|db_high[0]~20 , z80_|alu_|db_high[0]~20, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op1_latch_mux_high|Q[0] , z80_|alu_|b2v_op1_latch_mux_high|Q[0], spectrum, 1 +instance = comp, \z80_|alu_|op1_high[0] , z80_|alu_|op1_high[0], spectrum, 1 +instance = comp, \z80_|alu_|db_high[0]~21 , z80_|alu_|db_high[0]~21, spectrum, 1 +instance = comp, \z80_|alu_|db_high[0]~22 , z80_|alu_|db_high[0]~22, spectrum, 1 +instance = comp, \z80_|alu_|db_high[0]~23 , z80_|alu_|db_high[0]~23, spectrum, 1 +instance = comp, \z80_|alu_|db_high[0]~24 , z80_|alu_|db_high[0]~24, spectrum, 1 +instance = comp, \z80_|alu_|db_low[0]~4 , z80_|alu_|db_low[0]~4, spectrum, 1 +instance = comp, \z80_|alu_|result_lo[0] , z80_|alu_|result_lo[0], spectrum, 1 +instance = comp, \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~2 , z80_|alu_|b2v_op1_latch_mux_low|Q[0]~2, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~3 , z80_|alu_|b2v_op1_latch_mux_low|Q[0]~3, spectrum, 1 +instance = comp, \z80_|alu_|op1_low[0] , z80_|alu_|op1_low[0], spectrum, 1 +instance = comp, \z80_|alu_|db_low[0]~5 , z80_|alu_|db_low[0]~5, spectrum, 1 +instance = comp, \z80_|alu_|db_low[0]~6 , z80_|alu_|db_low[0]~6, spectrum, 1 +instance = comp, \z80_|alu_control_|b2v_inst_shift_mux|out~1 , z80_|alu_control_|b2v_inst_shift_mux|out~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_hf_we~2 , z80_|execute_|ctl_flags_hf_we~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf_we~3 , z80_|execute_|ctl_flags_cf_we~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf_we~4 , z80_|execute_|ctl_flags_cf_we~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf_we~5 , z80_|execute_|ctl_flags_cf_we~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf_we~6 , z80_|execute_|ctl_flags_cf_we~6, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_cf~0 , z80_|alu_flags_|DFFE_inst_latch_cf~0, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_cf~1 , z80_|alu_flags_|DFFE_inst_latch_cf~1, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_cf , z80_|alu_flags_|DFFE_inst_latch_cf, spectrum, 1 +instance = comp, \z80_|alu_control_|b2v_inst_shift_mux|out~0 , z80_|alu_control_|b2v_inst_shift_mux|out~0, spectrum, 1 +instance = comp, \z80_|alu_control_|b2v_inst_shift_mux|out~2 , z80_|alu_control_|b2v_inst_shift_mux|out~2, spectrum, 1 +instance = comp, \z80_|alu_|db_low[0]~2 , z80_|alu_|db_low[0]~2, spectrum, 1 +instance = comp, \z80_|alu_|db_low[0]~3 , z80_|alu_|db_low[0]~3, spectrum, 1 +instance = comp, \z80_|alu_|db_low[0]~24 , z80_|alu_|db_low[0]~24, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~0 , z80_|alu_|b2v_op2_latch_mux_low|Q[0]~0, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~1 , z80_|alu_|b2v_op2_latch_mux_low|Q[0]~1, spectrum, 1 +instance = comp, \z80_|alu_|op2_low[0] , z80_|alu_|op2_low[0], spectrum, 1 +instance = comp, \z80_|alu_|alu_op2[0]~3 , z80_|alu_|alu_op2[0]~3, spectrum, 1 +instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 , z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo_pla26M3T5_8 , z80_|execute_|ctl_reg_sys_hilo_pla26M3T5_8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~14 , z80_|execute_|ctl_alu_core_hf~14, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~16 , z80_|execute_|ctl_alu_core_hf~16, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~13 , z80_|execute_|ctl_alu_core_hf~13, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~17 , z80_|execute_|ctl_alu_core_hf~17, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~44 , z80_|execute_|ctl_alu_op_low~44, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~20 , z80_|execute_|ctl_alu_core_hf~20, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~21 , z80_|execute_|ctl_alu_core_hf~21, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~18 , z80_|execute_|ctl_alu_core_hf~18, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~19 , z80_|execute_|ctl_alu_core_hf~19, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~22 , z80_|execute_|ctl_alu_core_hf~22, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~43 , z80_|execute_|ctl_alu_op_low~43, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~24 , z80_|execute_|ctl_alu_core_hf~24, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~25 , z80_|execute_|ctl_alu_core_hf~25, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~35 , z80_|execute_|ctl_alu_core_hf~35, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~23 , z80_|execute_|ctl_alu_core_hf~23, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~26 , z80_|execute_|ctl_alu_core_hf~26, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~34 , z80_|execute_|ctl_alu_core_hf~34, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~27 , z80_|execute_|ctl_alu_core_hf~27, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~28 , z80_|execute_|ctl_alu_core_hf~28, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~29 , z80_|execute_|ctl_alu_core_hf~29, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~30 , z80_|execute_|ctl_alu_core_hf~30, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~31 , z80_|execute_|ctl_alu_core_hf~31, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~36 , z80_|execute_|ctl_alu_core_hf~36, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~37 , z80_|execute_|ctl_alu_core_hf~37, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~32 , z80_|execute_|ctl_alu_core_hf~32, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_core_hf~33 , z80_|execute_|ctl_alu_core_hf~33, spectrum, 1 +instance = comp, \z80_|alu_control_|alu_core_cf_in~0 , z80_|alu_control_|alu_core_cf_in~0, spectrum, 1 +instance = comp, \z80_|alu_|alu_op1[0]~0 , z80_|alu_|alu_op1[0]~0, spectrum, 1 +instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0, spectrum, 1 +instance = comp, \z80_|alu_|db_high[0]~25 , z80_|alu_|db_high[0]~25, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~6 , z80_|alu_|b2v_op2_latch_mux_high|Q[0]~6, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7 , z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7, spectrum, 1 +instance = comp, \z80_|alu_|op2_high[0] , z80_|alu_|op2_high[0], spectrum, 1 +instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0, spectrum, 1 +instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 , z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1, spectrum, 1 +instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0, spectrum, 1 +instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 , z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1, spectrum, 1 +instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0, spectrum, 1 +instance = comp, \z80_|alu_|db_high[1]~14 , z80_|alu_|db_high[1]~14, spectrum, 1 +instance = comp, \z80_|alu_|db_high[1]~15 , z80_|alu_|db_high[1]~15, spectrum, 1 +instance = comp, \z80_|alu_|db_high[1]~16 , z80_|alu_|db_high[1]~16, spectrum, 1 +instance = comp, \z80_|alu_|db_high[1]~17 , z80_|alu_|db_high[1]~17, spectrum, 1 +instance = comp, \z80_|alu_|db_high[1]~18 , z80_|alu_|db_high[1]~18, spectrum, 1 +instance = comp, \z80_|alu_|db_high[1]~19 , z80_|alu_|db_high[1]~19, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4 , z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 , z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5, spectrum, 1 +instance = comp, \z80_|alu_|op1_low[1] , z80_|alu_|op1_low[1], spectrum, 1 +instance = comp, \z80_|alu_control_|out[6]~0 , z80_|alu_control_|out[6]~0, spectrum, 1 +instance = comp, \z80_|alu_control_|out[6]~1 , z80_|alu_control_|out[6]~1, spectrum, 1 +instance = comp, \z80_|alu_control_|out[6]~2 , z80_|alu_control_|out[6]~2, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_12 , z80_|alu_flags_|SYNTHESIZED_WIRE_12, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 , z80_|alu_flags_|SYNTHESIZED_WIRE_37~0, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2 , z80_|alu_flags_|SYNTHESIZED_WIRE_11~2, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 , z80_|alu_flags_|SYNTHESIZED_WIRE_11~0, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 , z80_|alu_flags_|SYNTHESIZED_WIRE_11~1, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 , z80_|alu_flags_|SYNTHESIZED_WIRE_37~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_sz_we~7 , z80_|execute_|ctl_flags_sz_we~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_sz_we~8 , z80_|execute_|ctl_flags_sz_we~8, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_39 , z80_|alu_flags_|SYNTHESIZED_WIRE_39, spectrum, 1 +instance = comp, \z80_|execute_|setM1~51 , z80_|execute_|setM1~51, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_oe~2 , z80_|execute_|ctl_flags_oe~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_2u~7 , z80_|execute_|ctl_sw_2u~7, spectrum, 1 +instance = comp, \z80_|alu_control_|db[6]~20 , z80_|alu_control_|db[6]~20, spectrum, 1 +instance = comp, \z80_|alu_control_|db[6]~21 , z80_|alu_control_|db[6]~21, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_out_lo~8 , z80_|execute_|ctl_reg_out_lo~8, spectrum, 1 +instance = comp, \z80_|alu_control_|db[6]~10 , z80_|alu_control_|db[6]~10, spectrum, 1 +instance = comp, \z80_|alu_control_|db[6]~11 , z80_|alu_control_|db[6]~11, spectrum, 1 +instance = comp, \z80_|alu_control_|db[6]~22 , z80_|alu_control_|db[6]~22, spectrum, 1 +instance = comp, \z80_|alu_|db[6]~21 , z80_|alu_|db[6]~21, spectrum, 1 +instance = comp, \z80_|alu_|db[6]~22 , z80_|alu_|db[6]~22, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af2_hi|latch[6] , z80_|reg_file_|b2v_latch_af2_hi|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[6]~80 , z80_|reg_file_|gdfx_temp1[6]~80, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ix_hi|latch[6] , z80_|reg_file_|b2v_latch_ix_hi|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_iy_hi|latch[6] , z80_|reg_file_|b2v_latch_iy_hi|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[6]~79 , z80_|reg_file_|gdfx_temp1[6]~79, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] , z80_|reg_file_|b2v_latch_bc2_hi|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc_hi|latch[6]~feeder , z80_|reg_file_|b2v_latch_bc_hi|latch[6]~feeder, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc_hi|latch[6] , z80_|reg_file_|b2v_latch_bc_hi|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[6]~78 , z80_|reg_file_|gdfx_temp1[6]~78, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[6]~82 , z80_|reg_file_|gdfx_temp1[6]~82, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] , z80_|reg_file_|b2v_latch_hl2_hi|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl2_hi|db[6]~5 , z80_|reg_file_|b2v_latch_hl2_hi|db[6]~5, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl_hi|latch[6] , z80_|reg_file_|b2v_latch_hl_hi|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de2_hi|latch[6] , z80_|reg_file_|b2v_latch_de2_hi|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder , z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de_hi|latch[6] , z80_|reg_file_|b2v_latch_de_hi|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[6]~76 , z80_|reg_file_|gdfx_temp1[6]~76, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[6]~77 , z80_|reg_file_|gdfx_temp1[6]~77, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[6]~83 , z80_|reg_file_|gdfx_temp1[6]~83, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[6]~84 , z80_|reg_file_|gdfx_temp1[6]~84, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ir_hi|latch[6] , z80_|reg_file_|b2v_latch_ir_hi|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[6]~22 , z80_|reg_file_|db_hi_as[6]~22, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_pc_hi|latch[6] , z80_|reg_file_|b2v_latch_pc_hi|latch[6], spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[6]~23 , z80_|reg_file_|db_hi_as[6]~23, spectrum, 1 +instance = comp, \z80_|address_latch_|abusz[13] , z80_|address_latch_|abusz[13], spectrum, 1 +instance = comp, \z80_|address_latch_|Q[13] , z80_|address_latch_|Q[13], spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ix_hi|latch[4] , z80_|reg_file_|b2v_latch_ix_hi|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_iy_hi|latch[4] , z80_|reg_file_|b2v_latch_iy_hi|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[4]~61 , z80_|reg_file_|gdfx_temp1[4]~61, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af2_hi|latch[4] , z80_|reg_file_|b2v_latch_af2_hi|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[4]~62 , z80_|reg_file_|gdfx_temp1[4]~62, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] , z80_|reg_file_|b2v_latch_bc2_hi|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder , z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc_hi|latch[4] , z80_|reg_file_|b2v_latch_bc_hi|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[4]~60 , z80_|reg_file_|gdfx_temp1[4]~60, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_wz_hi|latch[4] , z80_|reg_file_|b2v_latch_wz_hi|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_sp_hi|latch[4] , z80_|reg_file_|b2v_latch_sp_hi|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[4]~63 , z80_|reg_file_|gdfx_temp1[4]~63, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[4]~64 , z80_|reg_file_|gdfx_temp1[4]~64, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_hi|latch[4] , z80_|reg_file_|b2v_latch_af_hi|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] , z80_|reg_file_|b2v_latch_hl2_hi|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl2_hi|db[4]~4 , z80_|reg_file_|b2v_latch_hl2_hi|db[4]~4, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl_hi|latch[4] , z80_|reg_file_|b2v_latch_hl_hi|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de_hi|latch[4] , z80_|reg_file_|b2v_latch_de_hi|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de2_hi|latch[4] , z80_|reg_file_|b2v_latch_de2_hi|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[4]~58 , z80_|reg_file_|gdfx_temp1[4]~58, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[4]~59 , z80_|reg_file_|gdfx_temp1[4]~59, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[4]~65 , z80_|reg_file_|gdfx_temp1[4]~65, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[4]~66 , z80_|reg_file_|gdfx_temp1[4]~66, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ir_hi|latch[4] , z80_|reg_file_|b2v_latch_ir_hi|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[4]~16 , z80_|reg_file_|db_hi_as[4]~16, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_pc_hi|latch[4] , z80_|reg_file_|b2v_latch_pc_hi|latch[4], spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[4]~17 , z80_|reg_file_|db_hi_as[4]~17, spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[4]~18 , z80_|reg_file_|db_hi_as[4]~18, spectrum, 1 +instance = comp, \z80_|address_latch_|abusz[12] , z80_|address_latch_|abusz[12], spectrum, 1 +instance = comp, \z80_|address_latch_|Q[12] , z80_|address_latch_|Q[12], spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0, spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|address[14] , z80_|address_latch_|b2v_inst_inc_dec|address[14], spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[6]~24 , z80_|reg_file_|db_hi_as[6]~24, spectrum, 1 +instance = comp, \z80_|address_latch_|abusz[14] , z80_|address_latch_|abusz[14], spectrum, 1 +instance = comp, \z80_|address_latch_|Q[14] , z80_|address_latch_|Q[14], spectrum, 1 +instance = comp, \z80_|address_latch_|abusz[15] , z80_|address_latch_|abusz[15], spectrum, 1 +instance = comp, \z80_|address_latch_|Q[15] , z80_|address_latch_|Q[15], spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|address[15]~0 , z80_|address_latch_|b2v_inst_inc_dec|address[15]~0, spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|address[15]~1 , z80_|address_latch_|b2v_inst_inc_dec|address[15]~1, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_pc_hi|latch[7] , z80_|reg_file_|b2v_latch_pc_hi|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ir_hi|latch[7] , z80_|reg_file_|b2v_latch_ir_hi|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[7]~19 , z80_|reg_file_|db_hi_as[7]~19, spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[7]~20 , z80_|reg_file_|db_hi_as[7]~20, spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[7]~21 , z80_|reg_file_|db_hi_as[7]~21, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_hi|latch[7] , z80_|reg_file_|b2v_latch_af_hi|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_hi|db[7]~15 , z80_|reg_file_|b2v_latch_af_hi|db[7]~15, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_sp_hi|latch[7] , z80_|reg_file_|b2v_latch_sp_hi|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_wz_hi|latch[7] , z80_|reg_file_|b2v_latch_wz_hi|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[7]~72 , z80_|reg_file_|gdfx_temp1[7]~72, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af2_hi|latch[7] , z80_|reg_file_|b2v_latch_af2_hi|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[7]~71 , z80_|reg_file_|gdfx_temp1[7]~71, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ix_hi|latch[7] , z80_|reg_file_|b2v_latch_ix_hi|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_iy_hi|latch[7] , z80_|reg_file_|b2v_latch_iy_hi|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[7]~70 , z80_|reg_file_|gdfx_temp1[7]~70, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] , z80_|reg_file_|b2v_latch_bc2_hi|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc_hi|latch[7] , z80_|reg_file_|b2v_latch_bc_hi|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[7]~69 , z80_|reg_file_|gdfx_temp1[7]~69, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[7]~73 , z80_|reg_file_|gdfx_temp1[7]~73, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl_hi|latch[7] , z80_|reg_file_|b2v_latch_hl_hi|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] , z80_|reg_file_|b2v_latch_hl2_hi|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[7]~68 , z80_|reg_file_|gdfx_temp1[7]~68, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de2_hi|latch[7] , z80_|reg_file_|b2v_latch_de2_hi|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de_hi|latch[7]~feeder , z80_|reg_file_|b2v_latch_de_hi|latch[7]~feeder, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de_hi|latch[7] , z80_|reg_file_|b2v_latch_de_hi|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[7]~67 , z80_|reg_file_|gdfx_temp1[7]~67, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[7]~74 , z80_|reg_file_|gdfx_temp1[7]~74, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[7]~75 , z80_|reg_file_|gdfx_temp1[7]~75, spectrum, 1 +instance = comp, \z80_|alu_|db[7]~11 , z80_|alu_|db[7]~11, spectrum, 1 +instance = comp, \z80_|alu_|db[7]~12 , z80_|alu_|db[7]~12, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_cf2~0 , z80_|alu_flags_|DFFE_inst_latch_cf2~0, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_cf2~1 , z80_|alu_flags_|DFFE_inst_latch_cf2~1, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_cf2~2 , z80_|alu_flags_|DFFE_inst_latch_cf2~2, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_cf2~3 , z80_|alu_flags_|DFFE_inst_latch_cf2~3, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_cf2 , z80_|alu_flags_|DFFE_inst_latch_cf2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_use_cf2~8 , z80_|execute_|ctl_flags_use_cf2~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_use_cf2~9 , z80_|execute_|ctl_flags_use_cf2~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_use_cf2~10 , z80_|execute_|ctl_flags_use_cf2~10, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_use_cf2~11 , z80_|execute_|ctl_flags_use_cf2~11, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_use_cf2~12 , z80_|execute_|ctl_flags_use_cf2~12, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~46 , z80_|execute_|ctl_alu_op_low~46, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~9 , z80_|execute_|ctl_alu_sel_op2_neg~9, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~10, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~11, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~14, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~15, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~16, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_cf_cpl~3 , z80_|execute_|ctl_flags_cf_cpl~3, spectrum, 1 +instance = comp, \z80_|alu_flags_|flags_cf , z80_|alu_flags_|flags_cf, spectrum, 1 +instance = comp, \z80_|sw2_|db_up[0]~0 , z80_|sw2_|db_up[0]~0, spectrum, 1 +instance = comp, \z80_|alu_control_|db[0]~8 , z80_|alu_control_|db[0]~8, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ir_lo|latch[0] , z80_|reg_file_|b2v_latch_ir_lo|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_pc_lo|latch[0] , z80_|reg_file_|b2v_latch_pc_lo|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[0]~0 , z80_|reg_file_|db_lo_as[0]~0, spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[0]~1 , z80_|reg_file_|db_lo_as[0]~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~70 , z80_|execute_|ctl_inc_cy~70, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~28 , z80_|execute_|pc_inc_hold~28, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~15 , z80_|execute_|pc_inc_hold~15, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~27 , z80_|execute_|pc_inc_hold~27, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~10 , z80_|execute_|pc_inc_hold~10, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 , z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~11 , z80_|execute_|pc_inc_hold~11, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 , z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~9 , z80_|execute_|pc_inc_hold~9, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~12 , z80_|execute_|pc_inc_hold~12, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~7 , z80_|execute_|pc_inc_hold~7, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~8 , z80_|execute_|pc_inc_hold~8, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~13 , z80_|execute_|pc_inc_hold~13, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~14 , z80_|execute_|pc_inc_hold~14, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 , z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~16 , z80_|execute_|pc_inc_hold~16, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~22 , z80_|execute_|pc_inc_hold~22, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~23 , z80_|execute_|pc_inc_hold~23, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~24 , z80_|execute_|pc_inc_hold~24, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~41 , z80_|execute_|ctl_inc_cy~41, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~21 , z80_|execute_|pc_inc_hold~21, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~25 , z80_|execute_|pc_inc_hold~25, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~69 , z80_|execute_|ctl_inc_cy~69, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~17 , z80_|execute_|pc_inc_hold~17, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~71 , z80_|execute_|ctl_inc_cy~71, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~44 , z80_|execute_|ctl_inc_cy~44, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~42 , z80_|execute_|ctl_inc_cy~42, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~43 , z80_|execute_|ctl_inc_cy~43, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~57 , z80_|execute_|ctl_inc_cy~57, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~54 , z80_|execute_|ctl_inc_cy~54, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~58 , z80_|execute_|ctl_inc_cy~58, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~18 , z80_|execute_|pc_inc_hold~18, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~19 , z80_|execute_|pc_inc_hold~19, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~45 , z80_|execute_|ctl_inc_cy~45, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~34 , z80_|execute_|ctl_inc_cy~34, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~35 , z80_|execute_|ctl_inc_cy~35, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~46 , z80_|execute_|ctl_inc_cy~46, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~47 , z80_|execute_|ctl_inc_cy~47, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~48 , z80_|execute_|ctl_inc_cy~48, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~50 , z80_|execute_|ctl_inc_cy~50, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~51 , z80_|execute_|ctl_inc_cy~51, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~85 , z80_|execute_|ctl_inc_cy~85, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~63 , z80_|execute_|ctl_inc_cy~63, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~64 , z80_|execute_|ctl_inc_cy~64, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~65 , z80_|execute_|ctl_inc_cy~65, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~59 , z80_|execute_|ctl_inc_cy~59, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~60 , z80_|execute_|ctl_inc_cy~60, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~61 , z80_|execute_|ctl_inc_cy~61, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~62 , z80_|execute_|ctl_inc_cy~62, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~66 , z80_|execute_|ctl_inc_cy~66, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~53 , z80_|execute_|ctl_inc_cy~53, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~52 , z80_|execute_|ctl_inc_cy~52, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~84 , z80_|execute_|ctl_inc_cy~84, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3 , z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~55 , z80_|execute_|ctl_inc_cy~55, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~56 , z80_|execute_|ctl_inc_cy~56, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~67 , z80_|execute_|ctl_inc_cy~67, spectrum, 1 +instance = comp, \z80_|execute_|pc_inc_hold~20 , z80_|execute_|pc_inc_hold~20, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~83 , z80_|execute_|ctl_inc_cy~83, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~68 , z80_|execute_|ctl_inc_cy~68, spectrum, 1 +instance = comp, \z80_|address_latch_|Q[0]~feeder , z80_|address_latch_|Q[0]~feeder, spectrum, 1 +instance = comp, \z80_|address_latch_|Q[0] , z80_|address_latch_|Q[0], spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~72 , z80_|execute_|ctl_inc_cy~72, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~73 , z80_|execute_|ctl_inc_cy~73, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~74 , z80_|execute_|ctl_inc_cy~74, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~75 , z80_|execute_|ctl_inc_cy~75, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~76 , z80_|execute_|ctl_inc_cy~76, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~80 , z80_|execute_|ctl_inc_cy~80, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~81 , z80_|execute_|ctl_inc_cy~81, spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out, spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[0]~3 , z80_|reg_file_|db_lo_as[0]~3, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af2_lo|latch[0] , z80_|reg_file_|b2v_latch_af2_lo|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[0]~feeder , z80_|reg_file_|b2v_latch_af_lo|latch[0]~feeder, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[0] , z80_|reg_file_|b2v_latch_af_lo|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[0]~13 , z80_|reg_file_|gdfx_temp0[0]~13, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] , z80_|reg_file_|b2v_latch_bc2_lo|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[0]~12 , z80_|reg_file_|gdfx_temp0[0]~12, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de_lo|latch[0]~feeder , z80_|reg_file_|b2v_latch_de_lo|latch[0]~feeder, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de_lo|latch[0] , z80_|reg_file_|b2v_latch_de_lo|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de2_lo|latch[0] , z80_|reg_file_|b2v_latch_de2_lo|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[0]~10 , z80_|reg_file_|gdfx_temp0[0]~10, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] , z80_|reg_file_|b2v_latch_hl2_lo|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0 , z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl_lo|latch[0] , z80_|reg_file_|b2v_latch_hl_lo|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[0]~11 , z80_|reg_file_|gdfx_temp0[0]~11, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder , z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc_lo|latch[0] , z80_|reg_file_|b2v_latch_bc_lo|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ix_lo|latch[0] , z80_|reg_file_|b2v_latch_ix_lo|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[0]~14 , z80_|reg_file_|gdfx_temp0[0]~14, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_wz_lo|latch[0] , z80_|reg_file_|b2v_latch_wz_lo|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_sp_lo|latch[0]~feeder , z80_|reg_file_|b2v_latch_sp_lo|latch[0]~feeder, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_sp_lo|latch[0] , z80_|reg_file_|b2v_latch_sp_lo|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_iy_lo|latch[0] , z80_|reg_file_|b2v_latch_iy_lo|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[0]~15 , z80_|reg_file_|gdfx_temp0[0]~15, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[0]~16 , z80_|reg_file_|gdfx_temp0[0]~16, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[0]~17 , z80_|reg_file_|gdfx_temp0[0]~17, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[0]~22 , z80_|reg_file_|gdfx_temp0[0]~22, spectrum, 1 +instance = comp, \z80_|alu_control_|db[0]~9 , z80_|alu_control_|db[0]~9, spectrum, 1 +instance = comp, \z80_|alu_control_|db[0]~12 , z80_|alu_control_|db[0]~12, spectrum, 1 +instance = comp, \z80_|address_latch_|abusz[8] , z80_|address_latch_|abusz[8], spectrum, 1 +instance = comp, \z80_|address_latch_|Q[8] , z80_|address_latch_|Q[8], spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl_lo|latch[7] , z80_|reg_file_|b2v_latch_hl_lo|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] , z80_|reg_file_|b2v_latch_hl2_lo|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[7]~84 , z80_|reg_file_|gdfx_temp0[7]~84, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de_lo|latch[7]~feeder , z80_|reg_file_|b2v_latch_de_lo|latch[7]~feeder, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de_lo|latch[7] , z80_|reg_file_|b2v_latch_de_lo|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de2_lo|latch[7] , z80_|reg_file_|b2v_latch_de2_lo|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[7]~83 , z80_|reg_file_|gdfx_temp0[7]~83, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_sp_lo|latch[7] , z80_|reg_file_|b2v_latch_sp_lo|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[7]~88 , z80_|reg_file_|gdfx_temp0[7]~88, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc_lo|latch[7] , z80_|reg_file_|b2v_latch_bc_lo|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] , z80_|reg_file_|b2v_latch_bc2_lo|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[7]~86 , z80_|reg_file_|gdfx_temp0[7]~86, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_iy_lo|latch[7] , z80_|reg_file_|b2v_latch_iy_lo|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ix_lo|latch[7] , z80_|reg_file_|b2v_latch_ix_lo|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[7]~87 , z80_|reg_file_|gdfx_temp0[7]~87, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_wz_lo|latch[7] , z80_|reg_file_|b2v_latch_wz_lo|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_wz_lo|db[7]~0 , z80_|reg_file_|b2v_latch_wz_lo|db[7]~0, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[7]~89 , z80_|reg_file_|gdfx_temp0[7]~89, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af2_lo|latch[7] , z80_|reg_file_|b2v_latch_af2_lo|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[7] , z80_|reg_file_|b2v_latch_af_lo|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[7]~85 , z80_|reg_file_|gdfx_temp0[7]~85, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[7]~90 , z80_|reg_file_|gdfx_temp0[7]~90, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[7]~91 , z80_|reg_file_|gdfx_temp0[7]~91, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_pc_lo|latch[7] , z80_|reg_file_|b2v_latch_pc_lo|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[7]~22 , z80_|reg_file_|db_lo_as[7]~22, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ir_lo|latch[7] , z80_|reg_file_|b2v_latch_ir_lo|latch[7], spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[7]~23 , z80_|reg_file_|db_lo_as[7]~23, spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[7]~24 , z80_|reg_file_|db_lo_as[7]~24, spectrum, 1 +instance = comp, \z80_|address_latch_|abusz[7] , z80_|address_latch_|abusz[7], spectrum, 1 +instance = comp, \z80_|address_latch_|Q[7]~feeder , z80_|address_latch_|Q[7]~feeder, spectrum, 1 +instance = comp, \z80_|address_latch_|Q[7] , z80_|address_latch_|Q[7], spectrum, 1 instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out, spectrum, 1 instance = comp, \z80_|reg_file_|b2v_latch_pc_hi|latch[0] , z80_|reg_file_|b2v_latch_pc_hi|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] , z80_|reg_file_|b2v_latch_hl2_hi|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl_hi|latch[0] , z80_|reg_file_|b2v_latch_hl_hi|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[0]~23 , z80_|reg_file_|gdfx_temp1[0]~23, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de2_hi|latch[0] , z80_|reg_file_|b2v_latch_de2_hi|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de_hi|latch[0] , z80_|reg_file_|b2v_latch_de_hi|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[0]~22 , z80_|reg_file_|gdfx_temp1[0]~22, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] , z80_|reg_file_|b2v_latch_bc2_hi|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc_hi|latch[0] , z80_|reg_file_|b2v_latch_bc_hi|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[0]~24 , z80_|reg_file_|gdfx_temp1[0]~24, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af2_hi|latch[0] , z80_|reg_file_|b2v_latch_af2_hi|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[0]~26 , z80_|reg_file_|gdfx_temp1[0]~26, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder , z80_|reg_file_|b2v_latch_ix_hi|latch[0]~feeder, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ix_hi|latch[0] , z80_|reg_file_|b2v_latch_ix_hi|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_iy_hi|latch[0] , z80_|reg_file_|b2v_latch_iy_hi|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[0]~25 , z80_|reg_file_|gdfx_temp1[0]~25, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_sp_hi|latch[0] , z80_|reg_file_|b2v_latch_sp_hi|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_wz_hi|latch[0] , z80_|reg_file_|b2v_latch_wz_hi|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[0]~27 , z80_|reg_file_|gdfx_temp1[0]~27, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[0]~28 , z80_|reg_file_|gdfx_temp1[0]~28, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_hi|latch[0] , z80_|reg_file_|b2v_latch_af_hi|latch[0], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_hi|db[0]~16 , z80_|reg_file_|b2v_latch_af_hi|db[0]~16, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[0]~29 , z80_|reg_file_|gdfx_temp1[0]~29, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[0]~30 , z80_|reg_file_|gdfx_temp1[0]~30, spectrum, 1 instance = comp, \z80_|reg_file_|b2v_latch_ir_hi|latch[0] , z80_|reg_file_|b2v_latch_ir_hi|latch[0], spectrum, 1 instance = comp, \z80_|reg_file_|db_hi_as[0]~4 , z80_|reg_file_|db_hi_as[0]~4, spectrum, 1 instance = comp, \z80_|reg_file_|db_hi_as[0]~5 , z80_|reg_file_|db_hi_as[0]~5, spectrum, 1 instance = comp, \z80_|reg_file_|db_hi_as[0]~6 , z80_|reg_file_|db_hi_as[0]~6, spectrum, 1 -instance = comp, \z80_|address_latch_|abusz[8] , z80_|address_latch_|abusz[8], spectrum, 1 -instance = comp, \z80_|address_latch_|Q[8] , z80_|address_latch_|Q[8], spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0, spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] , z80_|reg_file_|b2v_latch_hl2_hi|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl_hi|latch[0] , z80_|reg_file_|b2v_latch_hl_hi|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[0]~23 , z80_|reg_file_|gdfx_temp1[0]~23, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_iy_hi|latch[0] , z80_|reg_file_|b2v_latch_iy_hi|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ix_hi|latch[0] , z80_|reg_file_|b2v_latch_ix_hi|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[0]~25 , z80_|reg_file_|gdfx_temp1[0]~25, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_wz_hi|latch[0] , z80_|reg_file_|b2v_latch_wz_hi|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_sp_hi|latch[0] , z80_|reg_file_|b2v_latch_sp_hi|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[0]~27 , z80_|reg_file_|gdfx_temp1[0]~27, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc_hi|latch[0] , z80_|reg_file_|b2v_latch_bc_hi|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] , z80_|reg_file_|b2v_latch_bc2_hi|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[0]~24 , z80_|reg_file_|gdfx_temp1[0]~24, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af2_hi|latch[0] , z80_|reg_file_|b2v_latch_af2_hi|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[0]~26 , z80_|reg_file_|gdfx_temp1[0]~26, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[0]~28 , z80_|reg_file_|gdfx_temp1[0]~28, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_hi|latch[0] , z80_|reg_file_|b2v_latch_af_hi|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_hi|db[0]~11 , z80_|reg_file_|b2v_latch_af_hi|db[0]~11, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de2_hi|latch[0] , z80_|reg_file_|b2v_latch_de2_hi|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de_hi|latch[0]~feeder , z80_|reg_file_|b2v_latch_de_hi|latch[0]~feeder, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de_hi|latch[0] , z80_|reg_file_|b2v_latch_de_hi|latch[0], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[0]~22 , z80_|reg_file_|gdfx_temp1[0]~22, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[0]~29 , z80_|reg_file_|gdfx_temp1[0]~29, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[0]~30 , z80_|reg_file_|gdfx_temp1[0]~30, spectrum, 1 +instance = comp, \z80_|alu_|db[0]~13 , z80_|alu_|db[0]~13, spectrum, 1 +instance = comp, \z80_|alu_|db[0]~14 , z80_|alu_|db[0]~14, spectrum, 1 +instance = comp, \z80_|alu_|db_low[1]~10 , z80_|alu_|db_low[1]~10, spectrum, 1 +instance = comp, \z80_|alu_|db_low[1]~11 , z80_|alu_|db_low[1]~11, spectrum, 1 +instance = comp, \z80_|alu_|db_low[1]~8 , z80_|alu_|db_low[1]~8, spectrum, 1 +instance = comp, \z80_|alu_|db_low[1]~7 , z80_|alu_|db_low[1]~7, spectrum, 1 +instance = comp, \z80_|alu_|result_lo[1]~feeder , z80_|alu_|result_lo[1]~feeder, spectrum, 1 +instance = comp, \z80_|alu_|result_lo[1] , z80_|alu_|result_lo[1], spectrum, 1 +instance = comp, \z80_|alu_|db_low[1]~9 , z80_|alu_|db_low[1]~9, spectrum, 1 +instance = comp, \z80_|alu_|db_low[1]~12 , z80_|alu_|db_low[1]~12, spectrum, 1 +instance = comp, \z80_|alu_|db[1]~8 , z80_|alu_|db[1]~8, spectrum, 1 +instance = comp, \z80_|alu_|db[1]~10 , z80_|alu_|db[1]~10, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af2_hi|latch[1] , z80_|reg_file_|b2v_latch_af2_hi|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[1]~12 , z80_|reg_file_|gdfx_temp1[1]~12, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder , z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_iy_hi|latch[1] , z80_|reg_file_|b2v_latch_iy_hi|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ix_hi|latch[1] , z80_|reg_file_|b2v_latch_ix_hi|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[1]~11 , z80_|reg_file_|gdfx_temp1[1]~11, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] , z80_|reg_file_|b2v_latch_bc2_hi|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc_hi|latch[1] , z80_|reg_file_|b2v_latch_bc_hi|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[1]~10 , z80_|reg_file_|gdfx_temp1[1]~10, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_sp_hi|latch[1] , z80_|reg_file_|b2v_latch_sp_hi|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_wz_hi|latch[1] , z80_|reg_file_|b2v_latch_wz_hi|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[1]~13 , z80_|reg_file_|gdfx_temp1[1]~13, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[1]~14 , z80_|reg_file_|gdfx_temp1[1]~14, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_hi|latch[1] , z80_|reg_file_|b2v_latch_af_hi|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_hi|db[1]~10 , z80_|reg_file_|b2v_latch_af_hi|db[1]~10, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl_hi|latch[1] , z80_|reg_file_|b2v_latch_hl_hi|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] , z80_|reg_file_|b2v_latch_hl2_hi|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[1]~9 , z80_|reg_file_|gdfx_temp1[1]~9, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de2_hi|latch[1] , z80_|reg_file_|b2v_latch_de2_hi|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de_hi|latch[1]~feeder , z80_|reg_file_|b2v_latch_de_hi|latch[1]~feeder, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de_hi|latch[1] , z80_|reg_file_|b2v_latch_de_hi|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[1]~8 , z80_|reg_file_|gdfx_temp1[1]~8, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[1]~15 , z80_|reg_file_|gdfx_temp1[1]~15, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[1]~21 , z80_|reg_file_|gdfx_temp1[1]~21, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ir_hi|latch[1] , z80_|reg_file_|b2v_latch_ir_hi|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[1]~0 , z80_|reg_file_|db_hi_as[1]~0, spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[1]~1 , z80_|reg_file_|db_hi_as[1]~1, spectrum, 1 instance = comp, \z80_|reg_file_|db_hi_as[1]~3 , z80_|reg_file_|db_hi_as[1]~3, spectrum, 1 instance = comp, \z80_|address_latch_|abusz[9] , z80_|address_latch_|abusz[9], spectrum, 1 instance = comp, \z80_|address_latch_|Q[9]~feeder , z80_|address_latch_|Q[9]~feeder, spectrum, 1 instance = comp, \z80_|address_latch_|Q[9] , z80_|address_latch_|Q[9], spectrum, 1 +instance = comp, \z80_|address_latch_|abusz[10] , z80_|address_latch_|abusz[10], spectrum, 1 +instance = comp, \z80_|address_latch_|Q[10] , z80_|address_latch_|Q[10], spectrum, 1 instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] , z80_|reg_file_|b2v_latch_hl2_hi|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl_hi|latch[2] , z80_|reg_file_|b2v_latch_hl_hi|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[2]~32 , z80_|reg_file_|gdfx_temp1[2]~32, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af2_hi|latch[2] , z80_|reg_file_|b2v_latch_af2_hi|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[2]~35 , z80_|reg_file_|gdfx_temp1[2]~35, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ix_hi|latch[2] , z80_|reg_file_|b2v_latch_ix_hi|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder , z80_|reg_file_|b2v_latch_iy_hi|latch[2]~feeder, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_iy_hi|latch[2] , z80_|reg_file_|b2v_latch_iy_hi|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[2]~34 , z80_|reg_file_|gdfx_temp1[2]~34, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder , z80_|reg_file_|b2v_latch_bc_hi|latch[2]~feeder, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc_hi|latch[2] , z80_|reg_file_|b2v_latch_bc_hi|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] , z80_|reg_file_|b2v_latch_bc2_hi|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[2]~33 , z80_|reg_file_|gdfx_temp1[2]~33, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_sp_hi|latch[2] , z80_|reg_file_|b2v_latch_sp_hi|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_wz_hi|latch[2] , z80_|reg_file_|b2v_latch_wz_hi|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[2]~36 , z80_|reg_file_|gdfx_temp1[2]~36, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[2]~37 , z80_|reg_file_|gdfx_temp1[2]~37, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de_hi|latch[2] , z80_|reg_file_|b2v_latch_de_hi|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de2_hi|latch[2] , z80_|reg_file_|b2v_latch_de2_hi|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[2]~31 , z80_|reg_file_|gdfx_temp1[2]~31, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_hi|latch[2] , z80_|reg_file_|b2v_latch_af_hi|latch[2], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_hi|db[2]~17 , z80_|reg_file_|b2v_latch_af_hi|db[2]~17, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[2]~38 , z80_|reg_file_|gdfx_temp1[2]~38, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[2]~39 , z80_|reg_file_|gdfx_temp1[2]~39, spectrum, 1 instance = comp, \z80_|reg_file_|b2v_latch_ir_hi|latch[2] , z80_|reg_file_|b2v_latch_ir_hi|latch[2], spectrum, 1 instance = comp, \z80_|reg_file_|db_hi_as[2]~7 , z80_|reg_file_|db_hi_as[2]~7, spectrum, 1 instance = comp, \z80_|reg_file_|b2v_latch_pc_hi|latch[2] , z80_|reg_file_|b2v_latch_pc_hi|latch[2], spectrum, 1 instance = comp, \z80_|reg_file_|db_hi_as[2]~8 , z80_|reg_file_|db_hi_as[2]~8, spectrum, 1 instance = comp, \z80_|reg_file_|db_hi_as[2]~9 , z80_|reg_file_|db_hi_as[2]~9, spectrum, 1 -instance = comp, \z80_|address_latch_|abusz[10] , z80_|address_latch_|abusz[10], spectrum, 1 -instance = comp, \z80_|address_latch_|Q[10]~feeder , z80_|address_latch_|Q[10]~feeder, spectrum, 1 -instance = comp, \z80_|address_latch_|Q[10] , z80_|address_latch_|Q[10], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[2]~39 , z80_|reg_file_|gdfx_temp1[2]~39, spectrum, 1 +instance = comp, \z80_|alu_|db[2]~15 , z80_|alu_|db[2]~15, spectrum, 1 +instance = comp, \z80_|alu_|db[2]~16 , z80_|alu_|db[2]~16, spectrum, 1 +instance = comp, \z80_|alu_control_|db[2]~27 , z80_|alu_control_|db[2]~27, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_cf~2 , z80_|alu_flags_|DFFE_inst_latch_cf~2, spectrum, 1 +instance = comp, \z80_|alu_flags_|flags_hf2~0 , z80_|alu_flags_|flags_hf2~0, spectrum, 1 +instance = comp, \z80_|alu_flags_|flags_hf2 , z80_|alu_flags_|flags_hf2, spectrum, 1 +instance = comp, \z80_|alu_control_|db[2]~23 , z80_|alu_control_|db[2]~23, spectrum, 1 +instance = comp, \z80_|alu_control_|db[2]~29 , z80_|alu_control_|db[2]~29, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[2]~39 , z80_|reg_file_|gdfx_temp0[2]~39, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af2_lo|latch[2] , z80_|reg_file_|b2v_latch_af2_lo|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[2] , z80_|reg_file_|b2v_latch_af_lo|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[2]~35 , z80_|reg_file_|gdfx_temp0[2]~35, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[2]~40 , z80_|reg_file_|gdfx_temp0[2]~40, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[2]~41 , z80_|reg_file_|gdfx_temp0[2]~41, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[2]~42 , z80_|reg_file_|gdfx_temp0[2]~42, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_pc_lo|latch[2] , z80_|reg_file_|b2v_latch_pc_lo|latch[2], spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[2]~7 , z80_|reg_file_|db_lo_as[2]~7, spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[2]~8 , z80_|reg_file_|db_lo_as[2]~8, spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 , z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41, spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0 , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0, spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out, spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[2]~9 , z80_|reg_file_|db_lo_as[2]~9, spectrum, 1 +instance = comp, \z80_|address_latch_|abusz[2] , z80_|address_latch_|abusz[2], spectrum, 1 +instance = comp, \z80_|address_latch_|Q[2] , z80_|address_latch_|Q[2], spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42 , z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_pc_lo|latch[3] , z80_|reg_file_|b2v_latch_pc_lo|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[3]~10 , z80_|reg_file_|db_lo_as[3]~10, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ir_lo|latch[3] , z80_|reg_file_|b2v_latch_ir_lo|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[3]~11 , z80_|reg_file_|db_lo_as[3]~11, spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out, spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[3]~12 , z80_|reg_file_|db_lo_as[3]~12, spectrum, 1 +instance = comp, \z80_|address_latch_|abusz[3] , z80_|address_latch_|abusz[3], spectrum, 1 +instance = comp, \z80_|address_latch_|Q[3] , z80_|address_latch_|Q[3], spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4 , z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4, spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0, spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 , z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0, spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 , z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47, spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0, spectrum, 1 instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0, spectrum, 1 -instance = comp, \z80_|address_latch_|abusz[11] , z80_|address_latch_|abusz[11], spectrum, 1 -instance = comp, \z80_|address_latch_|Q[11] , z80_|address_latch_|Q[11], spectrum, 1 instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|address[11] , z80_|address_latch_|b2v_inst_inc_dec|address[11], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_pc_hi|latch[3] , z80_|reg_file_|b2v_latch_pc_hi|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ir_hi|latch[3] , z80_|reg_file_|b2v_latch_ir_hi|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[3]~10 , z80_|reg_file_|db_hi_as[3]~10, spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[3]~11 , z80_|reg_file_|db_hi_as[3]~11, spectrum, 1 instance = comp, \z80_|reg_file_|db_hi_as[3]~12 , z80_|reg_file_|db_hi_as[3]~12, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl_hi|latch[3] , z80_|reg_file_|b2v_latch_hl_hi|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] , z80_|reg_file_|b2v_latch_hl2_hi|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[3]~41 , z80_|reg_file_|gdfx_temp1[3]~41, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_wz_hi|latch[3] , z80_|reg_file_|b2v_latch_wz_hi|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_sp_hi|latch[3] , z80_|reg_file_|b2v_latch_sp_hi|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[3]~45 , z80_|reg_file_|gdfx_temp1[3]~45, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af2_hi|latch[3] , z80_|reg_file_|b2v_latch_af2_hi|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[3]~44 , z80_|reg_file_|gdfx_temp1[3]~44, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ix_hi|latch[3] , z80_|reg_file_|b2v_latch_ix_hi|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_iy_hi|latch[3] , z80_|reg_file_|b2v_latch_iy_hi|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[3]~43 , z80_|reg_file_|gdfx_temp1[3]~43, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc_hi|latch[3] , z80_|reg_file_|b2v_latch_bc_hi|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] , z80_|reg_file_|b2v_latch_bc2_hi|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[3]~42 , z80_|reg_file_|gdfx_temp1[3]~42, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[3]~46 , z80_|reg_file_|gdfx_temp1[3]~46, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de_hi|latch[3]~feeder , z80_|reg_file_|b2v_latch_de_hi|latch[3]~feeder, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de_hi|latch[3] , z80_|reg_file_|b2v_latch_de_hi|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de2_hi|latch[3] , z80_|reg_file_|b2v_latch_de2_hi|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[3]~40 , z80_|reg_file_|gdfx_temp1[3]~40, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_hi|latch[3] , z80_|reg_file_|b2v_latch_af_hi|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_hi|db[3]~13 , z80_|reg_file_|b2v_latch_af_hi|db[3]~13, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[3]~47 , z80_|reg_file_|gdfx_temp1[3]~47, spectrum, 1 instance = comp, \z80_|reg_file_|gdfx_temp1[3]~48 , z80_|reg_file_|gdfx_temp1[3]~48, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9 , z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op1_sel_low , z80_|execute_|ctl_alu_op1_sel_low, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op1_latch_mux_high|Q[3] , z80_|alu_|b2v_op1_latch_mux_high|Q[3], spectrum, 1 -instance = comp, \z80_|alu_|op1_high[3] , z80_|alu_|op1_high[3], spectrum, 1 -instance = comp, \z80_|alu_|alu_op1[3]~3 , z80_|alu_|alu_op1[3]~3, spectrum, 1 +instance = comp, \z80_|alu_|db[3]~19 , z80_|alu_|db[3]~19, spectrum, 1 +instance = comp, \z80_|alu_|db[3]~20 , z80_|alu_|db[3]~20, spectrum, 1 +instance = comp, \z80_|alu_|db_low[2]~21 , z80_|alu_|db_low[2]~21, spectrum, 1 +instance = comp, \z80_|alu_|db_low[2]~22 , z80_|alu_|db_low[2]~22, spectrum, 1 +instance = comp, \z80_|alu_|result_lo[2] , z80_|alu_|result_lo[2], spectrum, 1 +instance = comp, \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 , z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~6 , z80_|alu_|b2v_op2_latch_mux_low|Q[2]~6, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~7 , z80_|alu_|b2v_op2_latch_mux_low|Q[2]~7, spectrum, 1 +instance = comp, \z80_|alu_|op2_low[2] , z80_|alu_|op2_low[2], spectrum, 1 +instance = comp, \z80_|alu_|db_low[2]~18 , z80_|alu_|db_low[2]~18, spectrum, 1 +instance = comp, \z80_|alu_|db_low[2]~19 , z80_|alu_|db_low[2]~19, spectrum, 1 +instance = comp, \z80_|alu_|db_low[2]~20 , z80_|alu_|db_low[2]~20, spectrum, 1 +instance = comp, \z80_|alu_|db_low[2]~23 , z80_|alu_|db_low[2]~23, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~7 , z80_|alu_|b2v_op1_latch_mux_low|Q[2]~7, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~8 , z80_|alu_|b2v_op1_latch_mux_low|Q[2]~8, spectrum, 1 +instance = comp, \z80_|alu_|op1_low[2] , z80_|alu_|op1_low[2], spectrum, 1 +instance = comp, \z80_|alu_|alu_op1[2]~1 , z80_|alu_|alu_op1[2]~1, spectrum, 1 +instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 , z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1, spectrum, 1 instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op2_sel_bus~6 , z80_|execute_|ctl_alu_op2_sel_bus~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op2_sel_bus~10 , z80_|execute_|ctl_alu_op2_sel_bus~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_R~0 , z80_|execute_|ctl_alu_core_R~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op2_sel_bus~5 , z80_|execute_|ctl_alu_op2_sel_bus~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op2_sel_bus~7 , z80_|execute_|ctl_alu_op2_sel_bus~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op2_sel_bus~8 , z80_|execute_|ctl_alu_op2_sel_bus~8, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5 , z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6 , z80_|alu_|b2v_op2_latch_mux_high|Q[1]~6, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op2_latch_mux_high|ena , z80_|alu_|b2v_op2_latch_mux_high|ena, spectrum, 1 -instance = comp, \z80_|alu_|op2_high[1] , z80_|alu_|op2_high[1], spectrum, 1 -instance = comp, \z80_|alu_|b2v_op1_latch_mux_high|Q[1] , z80_|alu_|b2v_op1_latch_mux_high|Q[1], spectrum, 1 -instance = comp, \z80_|alu_|op1_high[1] , z80_|alu_|op1_high[1], spectrum, 1 -instance = comp, \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4 , z80_|alu_|b2v_op2_latch_mux_low|Q[1]~4, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5 , z80_|alu_|b2v_op2_latch_mux_low|Q[1]~5, spectrum, 1 -instance = comp, \z80_|alu_|op2_low[1] , z80_|alu_|op2_low[1], spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~6 , z80_|execute_|ctl_alu_sel_op2_neg~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~20 , z80_|execute_|ctl_alu_sel_op2_neg~20, spectrum, 1 -instance = comp, \z80_|execute_|ctl_state_alu~12 , z80_|execute_|ctl_state_alu~12, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~18 , z80_|execute_|ctl_alu_core_hf~18, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal61~2 , z80_|pla_decode_|Equal61~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~16 , z80_|execute_|ctl_alu_sel_op2_neg~16, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~17 , z80_|execute_|ctl_alu_sel_op2_neg~17, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~21 , z80_|execute_|ctl_alu_sel_op2_neg~21, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~15 , z80_|execute_|ctl_alu_sel_op2_neg~15, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~12 , z80_|execute_|ctl_alu_sel_op2_neg~12, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~22 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~22, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~20 , z80_|execute_|ctl_alu_core_hf~20, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_sz_we~4 , z80_|execute_|ctl_flags_sz_we~4, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal71~2 , z80_|pla_decode_|Equal71~2, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_nf~8 , z80_|alu_flags_|DFFE_inst_latch_nf~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~31 , z80_|execute_|ctl_alu_op_low~31, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_nf~4 , z80_|alu_flags_|DFFE_inst_latch_nf~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3 , z80_|execute_|ctl_reg_gp_hilo_pla25M1T1_3, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_nf~5 , z80_|alu_flags_|DFFE_inst_latch_nf~5, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_nf~6 , z80_|alu_flags_|DFFE_inst_latch_nf~6, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal72~2 , z80_|pla_decode_|Equal72~2, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal73~2 , z80_|pla_decode_|Equal73~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_nf_we~0 , z80_|execute_|ctl_flags_nf_we~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_nf_we~1 , z80_|execute_|ctl_flags_nf_we~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_nf_we~2 , z80_|execute_|ctl_flags_nf_we~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_nf_we~3 , z80_|execute_|ctl_flags_nf_we~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_sz_we~5 , z80_|execute_|ctl_flags_sz_we~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_sz_we~6 , z80_|execute_|ctl_flags_sz_we~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_nf_we~4 , z80_|execute_|ctl_flags_nf_we~4, spectrum, 1 -instance = comp, \z80_|execute_|setM1~15 , z80_|execute_|setM1~15, spectrum, 1 -instance = comp, \z80_|execute_|setM1~16 , z80_|execute_|setM1~16, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_xy_we~6 , z80_|execute_|ctl_flags_xy_we~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_xy_we~7 , z80_|execute_|ctl_flags_xy_we~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_sz_we~2 , z80_|execute_|ctl_flags_sz_we~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_pf_sel_pla12M1T1_12~0 , z80_|execute_|ctl_pf_sel_pla12M1T1_12~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_R~1 , z80_|execute_|ctl_alu_core_R~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_alu~7 , z80_|execute_|ctl_flags_alu~7, spectrum, 1 -instance = comp, \z80_|reg_control_|reg_sys_we_lo~8 , z80_|reg_control_|reg_sys_we_lo~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_alu~8 , z80_|execute_|ctl_flags_alu~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_xy_we~16 , z80_|execute_|ctl_flags_xy_we~16, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_alu~12 , z80_|execute_|ctl_flags_alu~12, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_alu~13 , z80_|execute_|ctl_flags_alu~13, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_alu~14 , z80_|execute_|ctl_flags_alu~14, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_alu~15 , z80_|execute_|ctl_flags_alu~15, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 , z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 , z80_|alu_flags_|SYNTHESIZED_WIRE_5~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~19 , z80_|execute_|ctl_alu_sel_op2_neg~19, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 , z80_|alu_flags_|SYNTHESIZED_WIRE_5~1, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 , z80_|alu_flags_|SYNTHESIZED_WIRE_5~2, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_nf~7 , z80_|alu_flags_|DFFE_inst_latch_nf~7, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_nf~9 , z80_|alu_flags_|DFFE_inst_latch_nf~9, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_nf~10 , z80_|alu_flags_|DFFE_inst_latch_nf~10, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_nf , z80_|alu_flags_|DFFE_inst_latch_nf, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~7 , z80_|execute_|ctl_alu_sel_op2_neg~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 , z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~10 , z80_|execute_|ctl_alu_sel_op2_neg~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~8 , z80_|execute_|ctl_alu_sel_op2_neg~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~9 , z80_|execute_|ctl_alu_sel_op2_neg~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~11 , z80_|execute_|ctl_alu_sel_op2_neg~11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~14 , z80_|execute_|ctl_alu_sel_op2_neg~14, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~18 , z80_|execute_|ctl_alu_sel_op2_neg~18, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_sel_op2_high , z80_|execute_|ctl_alu_sel_op2_high, spectrum, 1 -instance = comp, \z80_|alu_|alu_op2[1]~1 , z80_|alu_|alu_op2[1]~1, spectrum, 1 -instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 , z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_S~9 , z80_|execute_|ctl_alu_core_S~9, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7 , z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8 , z80_|alu_|b2v_op2_latch_mux_high|Q[0]~8, spectrum, 1 -instance = comp, \z80_|alu_|op2_high[0] , z80_|alu_|op2_high[0], spectrum, 1 -instance = comp, \z80_|alu_|alu_op2[0]~3 , z80_|alu_|alu_op2[0]~3, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_nf~12 , z80_|alu_flags_|DFFE_inst_latch_nf~12, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_S~8 , z80_|execute_|ctl_alu_core_S~8, spectrum, 1 -instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 , z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~21 , z80_|execute_|ctl_alu_core_hf~21, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~22 , z80_|execute_|ctl_alu_core_hf~22, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~19 , z80_|execute_|ctl_alu_core_hf~19, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~27 , z80_|execute_|ctl_alu_op_low~27, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~29 , z80_|execute_|ctl_alu_op_low~29, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~23 , z80_|execute_|ctl_alu_core_hf~23, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~37 , z80_|execute_|ctl_alu_core_hf~37, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~38 , z80_|execute_|ctl_alu_core_hf~38, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~24 , z80_|execute_|ctl_alu_core_hf~24, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~25 , z80_|execute_|ctl_alu_core_hf~25, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~26 , z80_|execute_|ctl_alu_core_hf~26, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~27 , z80_|execute_|ctl_alu_core_hf~27, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~28 , z80_|execute_|ctl_alu_core_hf~28, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~30 , z80_|execute_|ctl_alu_op_low~30, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~34 , z80_|execute_|ctl_alu_core_hf~34, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~32 , z80_|execute_|ctl_alu_core_hf~32, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~43 , z80_|execute_|ctl_alu_core_hf~43, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~33 , z80_|execute_|ctl_alu_core_hf~33, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~42 , z80_|execute_|ctl_alu_core_hf~42, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~35 , z80_|execute_|ctl_alu_core_hf~35, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~41 , z80_|execute_|ctl_alu_core_hf~41, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~30 , z80_|execute_|ctl_alu_core_hf~30, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mWrite~10 , z80_|execute_|ctl_mWrite~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~31 , z80_|execute_|ctl_alu_core_hf~31, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~44 , z80_|execute_|ctl_alu_core_hf~44, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~29 , z80_|execute_|ctl_alu_core_hf~29, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~36 , z80_|execute_|ctl_alu_core_hf~36, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~39 , z80_|execute_|ctl_alu_core_hf~39, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_hf~40 , z80_|execute_|ctl_alu_core_hf~40, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_hf_we~2 , z80_|execute_|ctl_flags_hf_we~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_R~2 , z80_|execute_|ctl_alu_core_R~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_R , z80_|execute_|ctl_alu_core_R, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9 , z80_|alu_|b2v_op2_latch_mux_high|Q[3]~9, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2 , z80_|alu_|b2v_op2_latch_mux_high|Q[3]~2, spectrum, 1 -instance = comp, \z80_|alu_|op2_high[3] , z80_|alu_|op2_high[3], spectrum, 1 -instance = comp, \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2 , z80_|alu_|b2v_op2_latch_mux_low|Q[3]~2, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3 , z80_|alu_|b2v_op2_latch_mux_low|Q[3]~3, spectrum, 1 -instance = comp, \z80_|alu_|op2_low[3] , z80_|alu_|op2_low[3], spectrum, 1 -instance = comp, \z80_|alu_|alu_op2[3]~2 , z80_|alu_|alu_op2[3]~2, spectrum, 1 -instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 , z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1, spectrum, 1 +instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0, spectrum, 1 +instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0, spectrum, 1 instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0, spectrum, 1 instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0, spectrum, 1 instance = comp, \z80_|alu_flags_|DFFE_inst_latch_hf~0 , z80_|alu_flags_|DFFE_inst_latch_hf~0, spectrum, 1 @@ -1470,613 +1822,336 @@ instance = comp, \z80_|execute_|ctl_flags_hf_we~3 , z80_|execute_|ctl_flags_hf_w instance = comp, \z80_|execute_|ctl_flags_hf_we~4 , z80_|execute_|ctl_flags_hf_we~4, spectrum, 1 instance = comp, \z80_|alu_flags_|DFFE_inst_latch_hf~1 , z80_|alu_flags_|DFFE_inst_latch_hf~1, spectrum, 1 instance = comp, \z80_|alu_flags_|DFFE_inst_latch_hf , z80_|alu_flags_|DFFE_inst_latch_hf, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_hf_cpl~11 , z80_|execute_|ctl_flags_hf_cpl~11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_hf_cpl~12 , z80_|execute_|ctl_flags_hf_cpl~12, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_hf_cpl~13 , z80_|execute_|ctl_flags_hf_cpl~13, spectrum, 1 instance = comp, \z80_|alu_flags_|flags_hf , z80_|alu_flags_|flags_hf, spectrum, 1 -instance = comp, \z80_|alu_control_|alu_core_cf_in~0 , z80_|alu_control_|alu_core_cf_in~0, spectrum, 1 -instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0, spectrum, 1 -instance = comp, \z80_|alu_|db_high[0]~23 , z80_|alu_|db_high[0]~23, spectrum, 1 -instance = comp, \z80_|address_latch_|abusz[12] , z80_|address_latch_|abusz[12], spectrum, 1 -instance = comp, \z80_|address_latch_|Q[12]~feeder , z80_|address_latch_|Q[12]~feeder, spectrum, 1 -instance = comp, \z80_|address_latch_|Q[12] , z80_|address_latch_|Q[12], spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_pc_hi|latch[4] , z80_|reg_file_|b2v_latch_pc_hi|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ir_hi|latch[4] , z80_|reg_file_|b2v_latch_ir_hi|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[4]~16 , z80_|reg_file_|db_hi_as[4]~16, spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[4]~17 , z80_|reg_file_|db_hi_as[4]~17, spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[4]~18 , z80_|reg_file_|db_hi_as[4]~18, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af2_hi|latch[4] , z80_|reg_file_|b2v_latch_af2_hi|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[4]~62 , z80_|reg_file_|gdfx_temp1[4]~62, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_sp_hi|latch[4] , z80_|reg_file_|b2v_latch_sp_hi|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_wz_hi|latch[4] , z80_|reg_file_|b2v_latch_wz_hi|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[4]~63 , z80_|reg_file_|gdfx_temp1[4]~63, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ix_hi|latch[4] , z80_|reg_file_|b2v_latch_ix_hi|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_iy_hi|latch[4] , z80_|reg_file_|b2v_latch_iy_hi|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[4]~61 , z80_|reg_file_|gdfx_temp1[4]~61, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder , z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc_hi|latch[4] , z80_|reg_file_|b2v_latch_bc_hi|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] , z80_|reg_file_|b2v_latch_bc2_hi|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[4]~60 , z80_|reg_file_|gdfx_temp1[4]~60, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[4]~64 , z80_|reg_file_|gdfx_temp1[4]~64, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] , z80_|reg_file_|b2v_latch_hl2_hi|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl_hi|latch[4] , z80_|reg_file_|b2v_latch_hl_hi|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[4]~59 , z80_|reg_file_|gdfx_temp1[4]~59, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de2_hi|latch[4] , z80_|reg_file_|b2v_latch_de2_hi|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de_hi|latch[4] , z80_|reg_file_|b2v_latch_de_hi|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[4]~58 , z80_|reg_file_|gdfx_temp1[4]~58, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_hi|latch[4] , z80_|reg_file_|b2v_latch_af_hi|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_hi|db[4]~19 , z80_|reg_file_|b2v_latch_af_hi|db[4]~19, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[4]~65 , z80_|reg_file_|gdfx_temp1[4]~65, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[4]~66 , z80_|reg_file_|gdfx_temp1[4]~66, spectrum, 1 -instance = comp, \z80_|alu_|db[4]~16 , z80_|alu_|db[4]~16, spectrum, 1 -instance = comp, \z80_|alu_|db[7]~26 , z80_|alu_|db[7]~26, spectrum, 1 +instance = comp, \z80_|alu_control_|db[4]~30 , z80_|alu_control_|db[4]~30, spectrum, 1 +instance = comp, \z80_|alu_control_|db[4]~31 , z80_|alu_control_|db[4]~31, spectrum, 1 +instance = comp, \z80_|alu_control_|db[4]~32 , z80_|alu_control_|db[4]~32, spectrum, 1 instance = comp, \z80_|alu_|db[4]~17 , z80_|alu_|db[4]~17, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf2_sel_shift~3 , z80_|execute_|ctl_flags_cf2_sel_shift~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf2_sel_shift~5 , z80_|execute_|ctl_flags_cf2_sel_shift~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf2_sel_shift~4 , z80_|execute_|ctl_flags_cf2_sel_shift~4, spectrum, 1 -instance = comp, \z80_|alu_|db_high[0]~24 , z80_|alu_|db_high[0]~24, spectrum, 1 -instance = comp, \z80_|alu_|db_high[0]~21 , z80_|alu_|db_high[0]~21, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op1_latch_mux_high|Q[0] , z80_|alu_|b2v_op1_latch_mux_high|Q[0], spectrum, 1 -instance = comp, \z80_|alu_|op1_high[0] , z80_|alu_|op1_high[0], spectrum, 1 -instance = comp, \z80_|alu_|db_high[0]~22 , z80_|alu_|db_high[0]~22, spectrum, 1 -instance = comp, \z80_|alu_|db_high[0]~25 , z80_|alu_|db_high[0]~25, spectrum, 1 -instance = comp, \z80_|alu_|db_high[0]~26 , z80_|alu_|db_high[0]~26, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7 , z80_|alu_|b2v_op1_latch_mux_low|Q[0]~7, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8 , z80_|alu_|b2v_op1_latch_mux_low|Q[0]~8, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op1_latch_mux_low|ena , z80_|alu_|b2v_op1_latch_mux_low|ena, spectrum, 1 -instance = comp, \z80_|alu_|op1_low[0] , z80_|alu_|op1_low[0], spectrum, 1 -instance = comp, \z80_|alu_|alu_op1[0]~1 , z80_|alu_|alu_op1[0]~1, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6 , z80_|alu_|b2v_op2_latch_mux_low|Q[0]~6, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7 , z80_|alu_|b2v_op2_latch_mux_low|Q[0]~7, spectrum, 1 -instance = comp, \z80_|alu_|op2_low[0] , z80_|alu_|op2_low[0], spectrum, 1 -instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0, spectrum, 1 -instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 , z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1, spectrum, 1 -instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0, spectrum, 1 -instance = comp, \z80_|alu_|alu_op1[1]~0 , z80_|alu_|alu_op1[1]~0, spectrum, 1 -instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0, spectrum, 1 -instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0, spectrum, 1 -instance = comp, \z80_|alu_|alu_op1[2]~2 , z80_|alu_|alu_op1[2]~2, spectrum, 1 -instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 , z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1, spectrum, 1 -instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_core_R~5 , z80_|execute_|ctl_alu_core_R~5, spectrum, 1 +instance = comp, \z80_|alu_|db[4]~18 , z80_|alu_|db[4]~18, spectrum, 1 +instance = comp, \z80_|alu_|db_low[3]~13 , z80_|alu_|db_low[3]~13, spectrum, 1 +instance = comp, \z80_|alu_|db_low[3]~14 , z80_|alu_|db_low[3]~14, spectrum, 1 +instance = comp, \z80_|alu_|db_low[3]~17 , z80_|alu_|db_low[3]~17, spectrum, 1 +instance = comp, \z80_|alu_|db_low[3]~25 , z80_|alu_|db_low[3]~25, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~4 , z80_|alu_|b2v_op2_latch_mux_low|Q[3]~4, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~5 , z80_|alu_|b2v_op2_latch_mux_low|Q[3]~5, spectrum, 1 +instance = comp, \z80_|alu_|op2_low[3] , z80_|alu_|op2_low[3], spectrum, 1 +instance = comp, \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0 , z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0, spectrum, 1 +instance = comp, \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1 , z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1, spectrum, 1 +instance = comp, \z80_|alu_|op2_high[3] , z80_|alu_|op2_high[3], spectrum, 1 +instance = comp, \z80_|alu_|alu_op2[3]~2 , z80_|alu_|alu_op2[3]~2, spectrum, 1 instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1 , z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1, spectrum, 1 instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder , z80_|reg_file_|b2v_latch_bc_hi|latch[7]~feeder, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc_hi|latch[7] , z80_|reg_file_|b2v_latch_bc_hi|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] , z80_|reg_file_|b2v_latch_bc2_hi|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[7]~69 , z80_|reg_file_|gdfx_temp1[7]~69, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ix_hi|latch[7] , z80_|reg_file_|b2v_latch_ix_hi|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_iy_hi|latch[7] , z80_|reg_file_|b2v_latch_iy_hi|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[7]~70 , z80_|reg_file_|gdfx_temp1[7]~70, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_sp_hi|latch[7] , z80_|reg_file_|b2v_latch_sp_hi|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_wz_hi|latch[7] , z80_|reg_file_|b2v_latch_wz_hi|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[7]~72 , z80_|reg_file_|gdfx_temp1[7]~72, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af2_hi|latch[7] , z80_|reg_file_|b2v_latch_af2_hi|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[7]~71 , z80_|reg_file_|gdfx_temp1[7]~71, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[7]~73 , z80_|reg_file_|gdfx_temp1[7]~73, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de2_hi|latch[7] , z80_|reg_file_|b2v_latch_de2_hi|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de_hi|latch[7] , z80_|reg_file_|b2v_latch_de_hi|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[7]~67 , z80_|reg_file_|gdfx_temp1[7]~67, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_hi|latch[7] , z80_|reg_file_|b2v_latch_af_hi|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_hi|db[7]~20 , z80_|reg_file_|b2v_latch_af_hi|db[7]~20, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] , z80_|reg_file_|b2v_latch_hl2_hi|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl_hi|latch[7] , z80_|reg_file_|b2v_latch_hl_hi|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[7]~68 , z80_|reg_file_|gdfx_temp1[7]~68, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[7]~74 , z80_|reg_file_|gdfx_temp1[7]~74, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ir_hi|latch[7] , z80_|reg_file_|b2v_latch_ir_hi|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[7]~19 , z80_|reg_file_|db_hi_as[7]~19, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_pc_hi|latch[7] , z80_|reg_file_|b2v_latch_pc_hi|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[7]~20 , z80_|reg_file_|db_hi_as[7]~20, spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0, spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_wz_hi|latch[5] , z80_|reg_file_|b2v_latch_wz_hi|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_sp_hi|latch[5] , z80_|reg_file_|b2v_latch_sp_hi|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[5]~54 , z80_|reg_file_|gdfx_temp1[5]~54, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af2_hi|latch[5] , z80_|reg_file_|b2v_latch_af2_hi|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[5]~53 , z80_|reg_file_|gdfx_temp1[5]~53, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder , z80_|reg_file_|b2v_latch_bc_hi|latch[5]~feeder, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc_hi|latch[5] , z80_|reg_file_|b2v_latch_bc_hi|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] , z80_|reg_file_|b2v_latch_bc2_hi|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[5]~51 , z80_|reg_file_|gdfx_temp1[5]~51, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_iy_hi|latch[5] , z80_|reg_file_|b2v_latch_iy_hi|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ix_hi|latch[5] , z80_|reg_file_|b2v_latch_ix_hi|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[5]~52 , z80_|reg_file_|gdfx_temp1[5]~52, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[5]~55 , z80_|reg_file_|gdfx_temp1[5]~55, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de_hi|latch[5] , z80_|reg_file_|b2v_latch_de_hi|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de2_hi|latch[5] , z80_|reg_file_|b2v_latch_de2_hi|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[5]~49 , z80_|reg_file_|gdfx_temp1[5]~49, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl_hi|latch[5] , z80_|reg_file_|b2v_latch_hl_hi|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] , z80_|reg_file_|b2v_latch_hl2_hi|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[5]~50 , z80_|reg_file_|gdfx_temp1[5]~50, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_hi|latch[5] , z80_|reg_file_|b2v_latch_af_hi|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_hi|db[5]~14 , z80_|reg_file_|b2v_latch_af_hi|db[5]~14, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[5]~56 , z80_|reg_file_|gdfx_temp1[5]~56, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[5]~57 , z80_|reg_file_|gdfx_temp1[5]~57, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ir_hi|latch[5] , z80_|reg_file_|b2v_latch_ir_hi|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[5]~13 , z80_|reg_file_|db_hi_as[5]~13, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_pc_hi|latch[5] , z80_|reg_file_|b2v_latch_pc_hi|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[5]~14 , z80_|reg_file_|db_hi_as[5]~14, spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[5]~15 , z80_|reg_file_|db_hi_as[5]~15, spectrum, 1 -instance = comp, \z80_|address_latch_|abusz[13] , z80_|address_latch_|abusz[13], spectrum, 1 -instance = comp, \z80_|address_latch_|Q[13]~feeder , z80_|address_latch_|Q[13]~feeder, spectrum, 1 -instance = comp, \z80_|address_latch_|Q[13] , z80_|address_latch_|Q[13], spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0 , z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_53~0, spectrum, 1 -instance = comp, \z80_|address_latch_|abusz[15] , z80_|address_latch_|abusz[15], spectrum, 1 -instance = comp, \z80_|address_latch_|Q[15] , z80_|address_latch_|Q[15], spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|address[14] , z80_|address_latch_|b2v_inst_inc_dec|address[14], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_pc_hi|latch[6] , z80_|reg_file_|b2v_latch_pc_hi|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de2_hi|latch[6] , z80_|reg_file_|b2v_latch_de2_hi|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de_hi|latch[6] , z80_|reg_file_|b2v_latch_de_hi|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[6]~76 , z80_|reg_file_|gdfx_temp1[6]~76, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af2_hi|latch[6] , z80_|reg_file_|b2v_latch_af2_hi|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[6]~80 , z80_|reg_file_|gdfx_temp1[6]~80, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_iy_hi|latch[6] , z80_|reg_file_|b2v_latch_iy_hi|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ix_hi|latch[6] , z80_|reg_file_|b2v_latch_ix_hi|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[6]~79 , z80_|reg_file_|gdfx_temp1[6]~79, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] , z80_|reg_file_|b2v_latch_bc2_hi|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc_hi|latch[6] , z80_|reg_file_|b2v_latch_bc_hi|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[6]~78 , z80_|reg_file_|gdfx_temp1[6]~78, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_sp_hi|latch[6] , z80_|reg_file_|b2v_latch_sp_hi|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_wz_hi|latch[6] , z80_|reg_file_|b2v_latch_wz_hi|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[6]~81 , z80_|reg_file_|gdfx_temp1[6]~81, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[6]~82 , z80_|reg_file_|gdfx_temp1[6]~82, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] , z80_|reg_file_|b2v_latch_hl2_hi|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl_hi|latch[6] , z80_|reg_file_|b2v_latch_hl_hi|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[6]~77 , z80_|reg_file_|gdfx_temp1[6]~77, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_hi|latch[6] , z80_|reg_file_|b2v_latch_af_hi|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_hi|db[6]~21 , z80_|reg_file_|b2v_latch_af_hi|db[6]~21, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[6]~83 , z80_|reg_file_|gdfx_temp1[6]~83, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[6]~84 , z80_|reg_file_|gdfx_temp1[6]~84, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ir_hi|latch[6] , z80_|reg_file_|b2v_latch_ir_hi|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[6]~22 , z80_|reg_file_|db_hi_as[6]~22, spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[6]~23 , z80_|reg_file_|db_hi_as[6]~23, spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[6]~24 , z80_|reg_file_|db_hi_as[6]~24, spectrum, 1 -instance = comp, \z80_|address_latch_|abusz[14] , z80_|address_latch_|abusz[14], spectrum, 1 -instance = comp, \z80_|address_latch_|Q[14]~feeder , z80_|address_latch_|Q[14]~feeder, spectrum, 1 -instance = comp, \z80_|address_latch_|Q[14] , z80_|address_latch_|Q[14], spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16 , z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_16, spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|address[15] , z80_|address_latch_|b2v_inst_inc_dec|address[15], spectrum, 1 -instance = comp, \z80_|reg_file_|db_hi_as[7]~21 , z80_|reg_file_|db_hi_as[7]~21, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp1[7]~75 , z80_|reg_file_|gdfx_temp1[7]~75, spectrum, 1 -instance = comp, \z80_|alu_|db[7]~20 , z80_|alu_|db[7]~20, spectrum, 1 -instance = comp, \z80_|alu_|db[7]~21 , z80_|alu_|db[7]~21, spectrum, 1 -instance = comp, \z80_|alu_control_|b2v_inst_shift_mux|out~1 , z80_|alu_control_|b2v_inst_shift_mux|out~1, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_cf~0 , z80_|alu_flags_|DFFE_inst_latch_cf~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf_we~4 , z80_|execute_|ctl_flags_cf_we~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf_we~5 , z80_|execute_|ctl_flags_cf_we~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf_we~3 , z80_|execute_|ctl_flags_cf_we~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf_we~6 , z80_|execute_|ctl_flags_cf_we~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf2_we~2 , z80_|execute_|ctl_flags_cf2_we~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf2_we~4 , z80_|execute_|ctl_flags_cf2_we~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf2_we~3 , z80_|execute_|ctl_flags_cf2_we~3, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_cf~1 , z80_|alu_flags_|DFFE_inst_latch_cf~1, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_cf , z80_|alu_flags_|DFFE_inst_latch_cf, spectrum, 1 -instance = comp, \z80_|alu_control_|b2v_inst_shift_mux|out~0 , z80_|alu_control_|b2v_inst_shift_mux|out~0, spectrum, 1 -instance = comp, \z80_|alu_control_|b2v_inst_shift_mux|out~2 , z80_|alu_control_|b2v_inst_shift_mux|out~2, spectrum, 1 -instance = comp, \z80_|alu_|db_high[3]~5 , z80_|alu_|db_high[3]~5, spectrum, 1 -instance = comp, \z80_|alu_|db_high[3]~6 , z80_|alu_|db_high[3]~6, spectrum, 1 +instance = comp, \z80_|alu_|db_high[3]~3 , z80_|alu_|db_high[3]~3, spectrum, 1 instance = comp, \z80_|alu_|db_high[3]~4 , z80_|alu_|db_high[3]~4, spectrum, 1 -instance = comp, \z80_|alu_|db_high[3]~27 , z80_|alu_|db_high[3]~27, spectrum, 1 +instance = comp, \z80_|alu_|db_high[3]~5 , z80_|alu_|db_high[3]~5, spectrum, 1 +instance = comp, \z80_|alu_|db_high[3]~2 , z80_|alu_|db_high[3]~2, spectrum, 1 +instance = comp, \z80_|alu_|db_high[3]~6 , z80_|alu_|db_high[3]~6, spectrum, 1 instance = comp, \z80_|alu_|db_high[3]~7 , z80_|alu_|db_high[3]~7, spectrum, 1 -instance = comp, \z80_|alu_|db_high[3]~8 , z80_|alu_|db_high[3]~8, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4 , z80_|alu_|b2v_op1_latch_mux_low|Q[3]~4, spectrum, 1 -instance = comp, \z80_|alu_|op1_low[3] , z80_|alu_|op1_low[3], spectrum, 1 -instance = comp, \z80_|alu_|db_low[3]~9 , z80_|alu_|db_low[3]~9, spectrum, 1 -instance = comp, \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 , z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2, spectrum, 1 -instance = comp, \z80_|alu_|db_low[3]~10 , z80_|alu_|db_low[3]~10, spectrum, 1 -instance = comp, \z80_|alu_|result_lo[3] , z80_|alu_|result_lo[3], spectrum, 1 -instance = comp, \z80_|alu_|db_low[3]~7 , z80_|alu_|db_low[3]~7, spectrum, 1 -instance = comp, \z80_|alu_|db_low[3]~8 , z80_|alu_|db_low[3]~8, spectrum, 1 -instance = comp, \z80_|alu_|db_low[3]~11 , z80_|alu_|db_low[3]~11, spectrum, 1 -instance = comp, \z80_|alu_|db_low[3]~25 , z80_|alu_|db_low[3]~25, spectrum, 1 -instance = comp, \z80_|alu_|db[3]~10 , z80_|alu_|db[3]~10, spectrum, 1 -instance = comp, \z80_|alu_|db[3]~11 , z80_|alu_|db[3]~11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_2u~7 , z80_|execute_|ctl_sw_2u~7, spectrum, 1 -instance = comp, \z80_|execute_|setM1~49 , z80_|execute_|setM1~49, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_oe~2 , z80_|execute_|ctl_flags_oe~2, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_35 , z80_|alu_flags_|SYNTHESIZED_WIRE_35, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_sz_we~7 , z80_|execute_|ctl_flags_sz_we~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3 , z80_|execute_|ctl_reg_sys_hilo_pla69M2T2_3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_xy_we~13 , z80_|execute_|ctl_flags_xy_we~13, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_xy_we~14 , z80_|execute_|ctl_flags_xy_we~14, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_xy_we~15 , z80_|execute_|ctl_flags_xy_we~15, spectrum, 1 -instance = comp, \z80_|alu_flags_|flags_xf , z80_|alu_flags_|flags_xf, spectrum, 1 -instance = comp, \z80_|alu_control_|db[3]~33 , z80_|alu_control_|db[3]~33, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_out_lo~3 , z80_|execute_|ctl_reg_out_lo~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 , z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_out_lo~4 , z80_|execute_|ctl_reg_out_lo~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_out_lo~5 , z80_|execute_|ctl_reg_out_lo~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_out_lo~8 , z80_|execute_|ctl_reg_out_lo~8, spectrum, 1 -instance = comp, \z80_|sw1_|db_down[3]~1 , z80_|sw1_|db_down[3]~1, spectrum, 1 -instance = comp, \z80_|alu_control_|db[3]~34 , z80_|alu_control_|db[3]~34, spectrum, 1 -instance = comp, \z80_|alu_control_|db[3]~35 , z80_|alu_control_|db[3]~35, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[3]~46 , z80_|reg_file_|gdfx_temp0[3]~46, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[3]~47 , z80_|reg_file_|gdfx_temp0[3]~47, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[3]~50 , z80_|reg_file_|gdfx_temp0[3]~50, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl_lo|latch[3] , z80_|reg_file_|b2v_latch_hl_lo|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] , z80_|reg_file_|b2v_latch_hl2_lo|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[3]~44 , z80_|reg_file_|gdfx_temp0[3]~44, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de_lo|latch[3] , z80_|reg_file_|b2v_latch_de_lo|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de2_lo|latch[3] , z80_|reg_file_|b2v_latch_de2_lo|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[3]~43 , z80_|reg_file_|gdfx_temp0[3]~43, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[3]~51 , z80_|reg_file_|gdfx_temp0[3]~51, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[3]~52 , z80_|reg_file_|gdfx_temp0[3]~52, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_pc_lo|latch[3] , z80_|reg_file_|b2v_latch_pc_lo|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[3]~10 , z80_|reg_file_|db_lo_as[3]~10, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ir_lo|latch[3] , z80_|reg_file_|b2v_latch_ir_lo|latch[3], spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[3]~11 , z80_|reg_file_|db_lo_as[3]~11, spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[3]~12 , z80_|reg_file_|db_lo_as[3]~12, spectrum, 1 -instance = comp, \z80_|address_latch_|abusz[3] , z80_|address_latch_|abusz[3], spectrum, 1 -instance = comp, \z80_|address_latch_|Q[3] , z80_|address_latch_|Q[3], spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4 , z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4, spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0, spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de_lo|latch[4] , z80_|reg_file_|b2v_latch_de_lo|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de2_lo|latch[4] , z80_|reg_file_|b2v_latch_de2_lo|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[4]~53 , z80_|reg_file_|gdfx_temp0[4]~53, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[4]~54 , z80_|reg_file_|gdfx_temp0[4]~54, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af2_lo|latch[4] , z80_|reg_file_|b2v_latch_af2_lo|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[4] , z80_|reg_file_|b2v_latch_af_lo|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[4]~58 , z80_|reg_file_|gdfx_temp0[4]~58, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_wz_lo|latch[4] , z80_|reg_file_|b2v_latch_wz_lo|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] , z80_|reg_file_|b2v_latch_bc2_lo|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc_lo|latch[4] , z80_|reg_file_|b2v_latch_bc_lo|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[4]~59 , z80_|reg_file_|gdfx_temp0[4]~59, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[4]~60 , z80_|reg_file_|gdfx_temp0[4]~60, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] , z80_|reg_file_|b2v_latch_hl2_lo|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl_lo|latch[4] , z80_|reg_file_|b2v_latch_hl_lo|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[4]~57 , z80_|reg_file_|gdfx_temp0[4]~57, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_iy_lo|latch[4] , z80_|reg_file_|b2v_latch_iy_lo|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_sp_lo|latch[4] , z80_|reg_file_|b2v_latch_sp_lo|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[4]~55 , z80_|reg_file_|gdfx_temp0[4]~55, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ix_lo|latch[4] , z80_|reg_file_|b2v_latch_ix_lo|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[4]~56 , z80_|reg_file_|gdfx_temp0[4]~56, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[4]~61 , z80_|reg_file_|gdfx_temp0[4]~61, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[4]~62 , z80_|reg_file_|gdfx_temp0[4]~62, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_pc_lo|latch[4] , z80_|reg_file_|b2v_latch_pc_lo|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[4]~13 , z80_|reg_file_|db_lo_as[4]~13, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ir_lo|latch[4] , z80_|reg_file_|b2v_latch_ir_lo|latch[4], spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[4]~14 , z80_|reg_file_|db_lo_as[4]~14, spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[4]~15 , z80_|reg_file_|db_lo_as[4]~15, spectrum, 1 -instance = comp, \z80_|address_latch_|abusz[4] , z80_|address_latch_|abusz[4], spectrum, 1 -instance = comp, \z80_|address_latch_|Q[4] , z80_|address_latch_|Q[4], spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 , z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44, spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl_lo|latch[5] , z80_|reg_file_|b2v_latch_hl_lo|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] , z80_|reg_file_|b2v_latch_hl2_lo|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[5]~64 , z80_|reg_file_|gdfx_temp0[5]~64, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de_lo|latch[5] , z80_|reg_file_|b2v_latch_de_lo|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de2_lo|latch[5] , z80_|reg_file_|b2v_latch_de2_lo|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[5]~63 , z80_|reg_file_|gdfx_temp0[5]~63, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_wz_lo|latch[5] , z80_|reg_file_|b2v_latch_wz_lo|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] , z80_|reg_file_|b2v_latch_bc2_lo|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[5]~66 , z80_|reg_file_|gdfx_temp0[5]~66, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[5]~67 , z80_|reg_file_|gdfx_temp0[5]~67, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af2_lo|latch[5] , z80_|reg_file_|b2v_latch_af2_lo|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[5] , z80_|reg_file_|b2v_latch_af_lo|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[5]~65 , z80_|reg_file_|gdfx_temp0[5]~65, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_sp_lo|latch[5] , z80_|reg_file_|b2v_latch_sp_lo|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder , z80_|reg_file_|b2v_latch_iy_lo|latch[5]~feeder, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_iy_lo|latch[5] , z80_|reg_file_|b2v_latch_iy_lo|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[5]~69 , z80_|reg_file_|gdfx_temp0[5]~69, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder , z80_|reg_file_|b2v_latch_ix_lo|latch[5]~feeder, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ix_lo|latch[5] , z80_|reg_file_|b2v_latch_ix_lo|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc_lo|latch[5] , z80_|reg_file_|b2v_latch_bc_lo|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[5]~68 , z80_|reg_file_|gdfx_temp0[5]~68, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[5]~70 , z80_|reg_file_|gdfx_temp0[5]~70, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[5]~71 , z80_|reg_file_|gdfx_temp0[5]~71, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[5]~72 , z80_|reg_file_|gdfx_temp0[5]~72, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_pc_lo|latch[5] , z80_|reg_file_|b2v_latch_pc_lo|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[5]~16 , z80_|reg_file_|db_lo_as[5]~16, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ir_lo|latch[5] , z80_|reg_file_|b2v_latch_ir_lo|latch[5], spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[5]~17 , z80_|reg_file_|db_lo_as[5]~17, spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[5]~18 , z80_|reg_file_|db_lo_as[5]~18, spectrum, 1 -instance = comp, \z80_|address_latch_|abusz[5] , z80_|address_latch_|abusz[5], spectrum, 1 -instance = comp, \z80_|address_latch_|Q[5] , z80_|address_latch_|Q[5], spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4 , z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4, spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|address[6] , z80_|address_latch_|b2v_inst_inc_dec|address[6], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ir_lo|latch[6] , z80_|reg_file_|b2v_latch_ir_lo|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] , z80_|reg_file_|b2v_latch_hl2_lo|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder , z80_|reg_file_|b2v_latch_hl_lo|latch[6]~feeder, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl_lo|latch[6] , z80_|reg_file_|b2v_latch_hl_lo|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[6]~74 , z80_|reg_file_|gdfx_temp0[6]~74, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de_lo|latch[6] , z80_|reg_file_|b2v_latch_de_lo|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de2_lo|latch[6] , z80_|reg_file_|b2v_latch_de2_lo|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[6]~73 , z80_|reg_file_|gdfx_temp0[6]~73, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ix_lo|latch[6] , z80_|reg_file_|b2v_latch_ix_lo|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder , z80_|reg_file_|b2v_latch_iy_lo|latch[6]~feeder, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_iy_lo|latch[6] , z80_|reg_file_|b2v_latch_iy_lo|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[6]~78 , z80_|reg_file_|gdfx_temp0[6]~78, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_sp_lo|latch[6] , z80_|reg_file_|b2v_latch_sp_lo|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[6]~79 , z80_|reg_file_|gdfx_temp0[6]~79, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_wz_lo|latch[6] , z80_|reg_file_|b2v_latch_wz_lo|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder , z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc_lo|latch[6] , z80_|reg_file_|b2v_latch_bc_lo|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] , z80_|reg_file_|b2v_latch_bc2_lo|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[6]~76 , z80_|reg_file_|gdfx_temp0[6]~76, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[6]~77 , z80_|reg_file_|gdfx_temp0[6]~77, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[6]~80 , z80_|reg_file_|gdfx_temp0[6]~80, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af2_lo|latch[6] , z80_|reg_file_|b2v_latch_af2_lo|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[6] , z80_|reg_file_|b2v_latch_af_lo|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[6]~75 , z80_|reg_file_|gdfx_temp0[6]~75, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[6]~81 , z80_|reg_file_|gdfx_temp0[6]~81, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[6]~82 , z80_|reg_file_|gdfx_temp0[6]~82, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_pc_lo|latch[6] , z80_|reg_file_|b2v_latch_pc_lo|latch[6], spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[6]~19 , z80_|reg_file_|db_lo_as[6]~19, spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[6]~20 , z80_|reg_file_|db_lo_as[6]~20, spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[6]~21 , z80_|reg_file_|db_lo_as[6]~21, spectrum, 1 -instance = comp, \z80_|address_latch_|abusz[6] , z80_|address_latch_|abusz[6], spectrum, 1 -instance = comp, \z80_|address_latch_|Q[6] , z80_|address_latch_|Q[6], spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 , z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0, spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 , z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47, spectrum, 1 -instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out, spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_as[7]~24 , z80_|reg_file_|db_lo_as[7]~24, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de_lo|latch[7] , z80_|reg_file_|b2v_latch_de_lo|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de2_lo|latch[7] , z80_|reg_file_|b2v_latch_de2_lo|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[7]~83 , z80_|reg_file_|gdfx_temp0[7]~83, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] , z80_|reg_file_|b2v_latch_hl2_lo|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl_lo|latch[7] , z80_|reg_file_|b2v_latch_hl_lo|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[7]~84 , z80_|reg_file_|gdfx_temp0[7]~84, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_ix_lo|latch[7] , z80_|reg_file_|b2v_latch_ix_lo|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder , z80_|reg_file_|b2v_latch_iy_lo|latch[7]~feeder, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_iy_lo|latch[7] , z80_|reg_file_|b2v_latch_iy_lo|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[7]~88 , z80_|reg_file_|gdfx_temp0[7]~88, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_wz_lo|latch[7] , z80_|reg_file_|b2v_latch_wz_lo|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc_lo|latch[7] , z80_|reg_file_|b2v_latch_bc_lo|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] , z80_|reg_file_|b2v_latch_bc2_lo|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[7]~86 , z80_|reg_file_|gdfx_temp0[7]~86, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[7]~87 , z80_|reg_file_|gdfx_temp0[7]~87, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af2_lo|latch[7] , z80_|reg_file_|b2v_latch_af2_lo|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[7] , z80_|reg_file_|b2v_latch_af_lo|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[7]~85 , z80_|reg_file_|gdfx_temp0[7]~85, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_sp_lo|latch[7] , z80_|reg_file_|b2v_latch_sp_lo|latch[7], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[7]~89 , z80_|reg_file_|gdfx_temp0[7]~89, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[7]~90 , z80_|reg_file_|gdfx_temp0[7]~90, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[7]~91 , z80_|reg_file_|gdfx_temp0[7]~91, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[7]~92 , z80_|reg_file_|gdfx_temp0[7]~92, spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_ds[7]~0 , z80_|reg_file_|db_lo_ds[7]~0, spectrum, 1 -instance = comp, \z80_|interrupts_|im2 , z80_|interrupts_|im2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~12 , z80_|execute_|ctl_mRead~12, spectrum, 1 -instance = comp, \z80_|execute_|ctl_sw_mask543_en~0 , z80_|execute_|ctl_sw_mask543_en~0, spectrum, 1 -instance = comp, \z80_|alu_control_|db[7]~17 , z80_|alu_control_|db[7]~17, spectrum, 1 -instance = comp, \z80_|alu_control_|db[7]~16 , z80_|alu_control_|db[7]~16, spectrum, 1 -instance = comp, \z80_|alu_control_|db[7]~18 , z80_|alu_control_|db[7]~18, spectrum, 1 instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_34 , z80_|alu_flags_|SYNTHESIZED_WIRE_34, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_sz_we~8 , z80_|execute_|ctl_flags_sz_we~8, spectrum, 1 instance = comp, \z80_|alu_flags_|DFFE_inst_latch_sf , z80_|alu_flags_|DFFE_inst_latch_sf, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal62~3 , z80_|pla_decode_|Equal62~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_pf_we~5 , z80_|execute_|ctl_flags_pf_we~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_pf_we~6 , z80_|execute_|ctl_flags_pf_we~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_pf_we~7 , z80_|execute_|ctl_flags_pf_we~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_pf_we~8 , z80_|execute_|ctl_flags_pf_we~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_pf_we~9 , z80_|execute_|ctl_flags_pf_we~9, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_pf~0 , z80_|alu_flags_|DFFE_inst_latch_pf~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~5 , z80_|execute_|ctl_alu_sel_op2_neg~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~7 , z80_|execute_|ctl_alu_sel_op2_neg~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3 , z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~6 , z80_|execute_|ctl_alu_sel_op2_neg~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~8 , z80_|execute_|ctl_alu_sel_op2_neg~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~11 , z80_|execute_|ctl_alu_sel_op2_neg~11, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~12 , z80_|execute_|ctl_alu_sel_op2_neg~12, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_sel_op2_neg~15 , z80_|execute_|ctl_alu_sel_op2_neg~15, spectrum, 1 +instance = comp, \z80_|alu_|alu_op2[2]~0 , z80_|alu_|alu_op2[2]~0, spectrum, 1 +instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 , z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1, spectrum, 1 +instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0, spectrum, 1 +instance = comp, \z80_|alu_control_|DFFE_latch_pf_tmp , z80_|alu_control_|DFFE_latch_pf_tmp, spectrum, 1 +instance = comp, \z80_|alu_|alu_parity_out~0 , z80_|alu_|alu_parity_out~0, spectrum, 1 +instance = comp, \z80_|alu_|alu_parity_out~1 , z80_|alu_|alu_parity_out~1, spectrum, 1 instance = comp, \z80_|alu_flags_|DFFE_inst_latch_pf~4 , z80_|alu_flags_|DFFE_inst_latch_pf~4, spectrum, 1 instance = comp, \z80_|alu_flags_|DFFE_inst_latch_pf~5 , z80_|alu_flags_|DFFE_inst_latch_pf~5, spectrum, 1 instance = comp, \z80_|alu_flags_|DFFE_inst_latch_pf~6 , z80_|alu_flags_|DFFE_inst_latch_pf~6, spectrum, 1 -instance = comp, \z80_|decode_state_|DFFE_instNonRep~0 , z80_|decode_state_|DFFE_instNonRep~0, spectrum, 1 -instance = comp, \z80_|decode_state_|DFFE_instNonRep~3 , z80_|decode_state_|DFFE_instNonRep~3, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_pf~1 , z80_|alu_flags_|DFFE_inst_latch_pf~1, spectrum, 1 instance = comp, \z80_|decode_state_|DFFE_instNonRep~2 , z80_|decode_state_|DFFE_instNonRep~2, spectrum, 1 instance = comp, \z80_|decode_state_|DFFE_instNonRep~1 , z80_|decode_state_|DFFE_instNonRep~1, spectrum, 1 +instance = comp, \z80_|decode_state_|DFFE_instNonRep~3 , z80_|decode_state_|DFFE_instNonRep~3, spectrum, 1 +instance = comp, \z80_|decode_state_|DFFE_instNonRep~0 , z80_|decode_state_|DFFE_instNonRep~0, spectrum, 1 instance = comp, \z80_|decode_state_|DFFE_instNonRep~4 , z80_|decode_state_|DFFE_instNonRep~4, spectrum, 1 instance = comp, \z80_|decode_state_|DFFE_instNonRep~5 , z80_|decode_state_|DFFE_instNonRep~5, spectrum, 1 instance = comp, \z80_|decode_state_|DFFE_instNonRep , z80_|decode_state_|DFFE_instNonRep, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_pf~1 , z80_|alu_flags_|DFFE_inst_latch_pf~1, spectrum, 1 instance = comp, \z80_|alu_flags_|DFFE_inst_latch_pf~2 , z80_|alu_flags_|DFFE_inst_latch_pf~2, spectrum, 1 instance = comp, \z80_|alu_flags_|DFFE_inst_latch_pf~3 , z80_|alu_flags_|DFFE_inst_latch_pf~3, spectrum, 1 -instance = comp, \z80_|alu_control_|DFFE_latch_pf_tmp , z80_|alu_control_|DFFE_latch_pf_tmp, spectrum, 1 -instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 , z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1, spectrum, 1 -instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0, spectrum, 1 -instance = comp, \z80_|alu_|alu_parity_out~0 , z80_|alu_|alu_parity_out~0, spectrum, 1 -instance = comp, \z80_|alu_|alu_parity_out , z80_|alu_|alu_parity_out, spectrum, 1 instance = comp, \z80_|alu_flags_|DFFE_inst_latch_pf~7 , z80_|alu_flags_|DFFE_inst_latch_pf~7, spectrum, 1 instance = comp, \z80_|alu_flags_|DFFE_inst_latch_pf~8 , z80_|alu_flags_|DFFE_inst_latch_pf~8, spectrum, 1 instance = comp, \z80_|alu_flags_|DFFE_inst_latch_pf~9 , z80_|alu_flags_|DFFE_inst_latch_pf~9, spectrum, 1 +instance = comp, \z80_|alu_flags_|DFFE_inst_latch_pf~0 , z80_|alu_flags_|DFFE_inst_latch_pf~0, spectrum, 1 instance = comp, \z80_|alu_flags_|DFFE_inst_latch_pf~10 , z80_|alu_flags_|DFFE_inst_latch_pf~10, spectrum, 1 instance = comp, \z80_|alu_flags_|DFFE_inst_latch_pf , z80_|alu_flags_|DFFE_inst_latch_pf, spectrum, 1 instance = comp, \z80_|alu_control_|sel[1]~0 , z80_|alu_control_|sel[1]~0, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2 , z80_|alu_flags_|SYNTHESIZED_WIRE_11~2, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_12 , z80_|alu_flags_|SYNTHESIZED_WIRE_12, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 , z80_|alu_flags_|SYNTHESIZED_WIRE_11~0, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 , z80_|alu_flags_|SYNTHESIZED_WIRE_11~1, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 , z80_|alu_flags_|SYNTHESIZED_WIRE_37~0, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 , z80_|alu_flags_|SYNTHESIZED_WIRE_37~1, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_39 , z80_|alu_flags_|SYNTHESIZED_WIRE_39, spectrum, 1 instance = comp, \z80_|alu_control_|b2v_inst_cond_mux|out~0 , z80_|alu_control_|b2v_inst_cond_mux|out~0, spectrum, 1 instance = comp, \z80_|alu_control_|b2v_inst_cond_mux|out~1 , z80_|alu_control_|b2v_inst_cond_mux|out~1, spectrum, 1 instance = comp, \z80_|alu_control_|flags_cond_true~0 , z80_|alu_control_|flags_cond_true~0, spectrum, 1 instance = comp, \z80_|alu_control_|flags_cond_true , z80_|alu_control_|flags_cond_true, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_wz~13 , z80_|execute_|ctl_reg_sel_wz~13, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_wz~14 , z80_|execute_|ctl_reg_sel_wz~14, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_sel_wz~17 , z80_|execute_|ctl_reg_sel_wz~17, spectrum, 1 -instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_82 , z80_|reg_file_|SYNTHESIZED_WIRE_82, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[0]~18 , z80_|reg_file_|gdfx_temp0[0]~18, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[0]~20 , z80_|reg_file_|gdfx_temp0[0]~20, spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[0]~21 , z80_|reg_file_|gdfx_temp0[0]~21, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_wz~20 , z80_|execute_|ctl_reg_sel_wz~20, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_4d~1 , z80_|execute_|ctl_sw_4d~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_4d~6 , z80_|execute_|ctl_sw_4d~6, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_pc_lo|latch[1] , z80_|reg_file_|b2v_latch_pc_lo|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[1]~4 , z80_|reg_file_|db_lo_as[1]~4, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ir_lo|latch[1] , z80_|reg_file_|b2v_latch_ir_lo|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[1]~5 , z80_|reg_file_|db_lo_as[1]~5, spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out, spectrum, 1 +instance = comp, \z80_|reg_file_|db_lo_as[1]~6 , z80_|reg_file_|db_lo_as[1]~6, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_sp_lo|latch[1] , z80_|reg_file_|b2v_latch_sp_lo|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[1]~29 , z80_|reg_file_|gdfx_temp0[1]~29, spectrum, 1 instance = comp, \z80_|reg_file_|b2v_latch_iy_lo|latch[1] , z80_|reg_file_|b2v_latch_iy_lo|latch[1], spectrum, 1 instance = comp, \z80_|reg_file_|b2v_latch_ix_lo|latch[1] , z80_|reg_file_|b2v_latch_ix_lo|latch[1], spectrum, 1 instance = comp, \z80_|reg_file_|gdfx_temp0[1]~28 , z80_|reg_file_|gdfx_temp0[1]~28, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_wz_lo|latch[1] , z80_|reg_file_|b2v_latch_wz_lo|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] , z80_|reg_file_|b2v_latch_bc2_lo|latch[1], spectrum, 1 instance = comp, \z80_|reg_file_|b2v_latch_bc_lo|latch[1] , z80_|reg_file_|b2v_latch_bc_lo|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] , z80_|reg_file_|b2v_latch_bc2_lo|latch[1], spectrum, 1 instance = comp, \z80_|reg_file_|gdfx_temp0[1]~26 , z80_|reg_file_|gdfx_temp0[1]~26, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_wz_lo|latch[1] , z80_|reg_file_|b2v_latch_wz_lo|latch[1], spectrum, 1 instance = comp, \z80_|reg_file_|gdfx_temp0[1]~27 , z80_|reg_file_|gdfx_temp0[1]~27, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_sp_lo|latch[1] , z80_|reg_file_|b2v_latch_sp_lo|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[1]~29 , z80_|reg_file_|gdfx_temp0[1]~29, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af2_lo|latch[1] , z80_|reg_file_|b2v_latch_af2_lo|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder , z80_|reg_file_|b2v_latch_af_lo|latch[1]~feeder, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[1] , z80_|reg_file_|b2v_latch_af_lo|latch[1], spectrum, 1 -instance = comp, \z80_|reg_file_|gdfx_temp0[1]~25 , z80_|reg_file_|gdfx_temp0[1]~25, spectrum, 1 instance = comp, \z80_|reg_file_|gdfx_temp0[1]~30 , z80_|reg_file_|gdfx_temp0[1]~30, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder , z80_|reg_file_|b2v_latch_hl_lo|latch[1]~feeder, spectrum, 1 instance = comp, \z80_|reg_file_|b2v_latch_hl_lo|latch[1] , z80_|reg_file_|b2v_latch_hl_lo|latch[1], spectrum, 1 instance = comp, \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] , z80_|reg_file_|b2v_latch_hl2_lo|latch[1], spectrum, 1 instance = comp, \z80_|reg_file_|gdfx_temp0[1]~24 , z80_|reg_file_|gdfx_temp0[1]~24, spectrum, 1 -instance = comp, \z80_|reg_file_|b2v_latch_de_lo|latch[1] , z80_|reg_file_|b2v_latch_de_lo|latch[1], spectrum, 1 instance = comp, \z80_|reg_file_|b2v_latch_de2_lo|latch[1] , z80_|reg_file_|b2v_latch_de2_lo|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de_lo|latch[1] , z80_|reg_file_|b2v_latch_de_lo|latch[1], spectrum, 1 instance = comp, \z80_|reg_file_|gdfx_temp0[1]~23 , z80_|reg_file_|gdfx_temp0[1]~23, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af2_lo|latch[1] , z80_|reg_file_|b2v_latch_af2_lo|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[1] , z80_|reg_file_|b2v_latch_af_lo|latch[1], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[1]~25 , z80_|reg_file_|gdfx_temp0[1]~25, spectrum, 1 instance = comp, \z80_|reg_file_|gdfx_temp0[1]~31 , z80_|reg_file_|gdfx_temp0[1]~31, spectrum, 1 instance = comp, \z80_|reg_file_|gdfx_temp0[1]~32 , z80_|reg_file_|gdfx_temp0[1]~32, spectrum, 1 instance = comp, \z80_|reg_file_|db_lo_ds[1]~1 , z80_|reg_file_|db_lo_ds[1]~1, spectrum, 1 instance = comp, \z80_|alu_control_|db[1]~25 , z80_|alu_control_|db[1]~25, spectrum, 1 instance = comp, \z80_|alu_control_|db[1]~24 , z80_|alu_control_|db[1]~24, spectrum, 1 instance = comp, \z80_|alu_control_|db[1]~26 , z80_|alu_control_|db[1]~26, spectrum, 1 -instance = comp, \z80_|alu_|db[1]~12 , z80_|alu_|db[1]~12, spectrum, 1 -instance = comp, \z80_|alu_|db[1]~13 , z80_|alu_|db[1]~13, spectrum, 1 -instance = comp, \z80_|alu_|db_low[0]~21 , z80_|alu_|db_low[0]~21, spectrum, 1 -instance = comp, \z80_|alu_|db_low[0]~22 , z80_|alu_|db_low[0]~22, spectrum, 1 -instance = comp, \z80_|alu_|db_low[0]~18 , z80_|alu_|db_low[0]~18, spectrum, 1 -instance = comp, \z80_|alu_|db_low[0]~19 , z80_|alu_|db_low[0]~19, spectrum, 1 -instance = comp, \z80_|alu_|result_lo[0] , z80_|alu_|result_lo[0], spectrum, 1 -instance = comp, \z80_|alu_|db_low[0]~20 , z80_|alu_|db_low[0]~20, spectrum, 1 -instance = comp, \z80_|alu_|db_low[0]~23 , z80_|alu_|db_low[0]~23, spectrum, 1 -instance = comp, \z80_|alu_|db[0]~18 , z80_|alu_|db[0]~18, spectrum, 1 -instance = comp, \z80_|alu_|db[0]~19 , z80_|alu_|db[0]~19, spectrum, 1 -instance = comp, \z80_|alu_|db_low[1]~15 , z80_|alu_|db_low[1]~15, spectrum, 1 -instance = comp, \z80_|alu_|db_low[1]~16 , z80_|alu_|db_low[1]~16, spectrum, 1 -instance = comp, \z80_|alu_|db_low[1]~12 , z80_|alu_|db_low[1]~12, spectrum, 1 -instance = comp, \z80_|alu_|db_low[1]~13 , z80_|alu_|db_low[1]~13, spectrum, 1 -instance = comp, \z80_|alu_|result_lo[1] , z80_|alu_|result_lo[1], spectrum, 1 -instance = comp, \z80_|alu_|db_low[1]~14 , z80_|alu_|db_low[1]~14, spectrum, 1 -instance = comp, \z80_|alu_|db_low[1]~17 , z80_|alu_|db_low[1]~17, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 , z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6 , z80_|alu_|b2v_op1_latch_mux_low|Q[1]~6, spectrum, 1 -instance = comp, \z80_|alu_|op1_low[1] , z80_|alu_|op1_low[1], spectrum, 1 -instance = comp, \z80_|alu_control_|out[6]~0 , z80_|alu_control_|out[6]~0, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_cf~2 , z80_|alu_flags_|DFFE_inst_latch_cf~2, spectrum, 1 -instance = comp, \z80_|alu_flags_|flags_hf2~0 , z80_|alu_flags_|flags_hf2~0, spectrum, 1 -instance = comp, \z80_|alu_flags_|flags_hf2 , z80_|alu_flags_|flags_hf2, spectrum, 1 -instance = comp, \z80_|alu_control_|db[2]~23 , z80_|alu_control_|db[2]~23, spectrum, 1 -instance = comp, \z80_|reg_file_|db_lo_ds[2]~2 , z80_|reg_file_|db_lo_ds[2]~2, spectrum, 1 -instance = comp, \z80_|alu_control_|db[2]~28 , z80_|alu_control_|db[2]~28, spectrum, 1 -instance = comp, \z80_|alu_control_|db[2]~27 , z80_|alu_control_|db[2]~27, spectrum, 1 -instance = comp, \z80_|alu_control_|db[2]~29 , z80_|alu_control_|db[2]~29, spectrum, 1 -instance = comp, \z80_|alu_|db[2]~14 , z80_|alu_|db[2]~14, spectrum, 1 -instance = comp, \z80_|alu_|db[2]~15 , z80_|alu_|db[2]~15, spectrum, 1 -instance = comp, \z80_|alu_|db_low[2]~2 , z80_|alu_|db_low[2]~2, spectrum, 1 -instance = comp, \z80_|alu_|db_low[2]~3 , z80_|alu_|db_low[2]~3, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2 , z80_|alu_|b2v_op1_latch_mux_low|Q[2]~2, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3 , z80_|alu_|b2v_op1_latch_mux_low|Q[2]~3, spectrum, 1 -instance = comp, \z80_|alu_|op1_low[2] , z80_|alu_|op1_low[2], spectrum, 1 -instance = comp, \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0 , z80_|alu_|b2v_op2_latch_mux_low|Q[2]~0, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1 , z80_|alu_|b2v_op2_latch_mux_low|Q[2]~1, spectrum, 1 -instance = comp, \z80_|alu_|op2_low[2] , z80_|alu_|op2_low[2], spectrum, 1 -instance = comp, \z80_|alu_|db_low[2]~5 , z80_|alu_|db_low[2]~5, spectrum, 1 -instance = comp, \z80_|alu_|result_lo[2] , z80_|alu_|result_lo[2], spectrum, 1 -instance = comp, \z80_|alu_|db_low[2]~6 , z80_|alu_|db_low[2]~6, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 , z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3, spectrum, 1 -instance = comp, \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4 , z80_|alu_|b2v_op2_latch_mux_high|Q[2]~4, spectrum, 1 -instance = comp, \z80_|alu_|op2_high[2] , z80_|alu_|op2_high[2], spectrum, 1 -instance = comp, \z80_|alu_|alu_op2[2]~0 , z80_|alu_|alu_op2[2]~0, spectrum, 1 -instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 , z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1, spectrum, 1 -instance = comp, \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 , z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0, spectrum, 1 -instance = comp, \z80_|alu_|db_high[2]~9 , z80_|alu_|db_high[2]~9, spectrum, 1 -instance = comp, \z80_|alu_|db_high[2]~11 , z80_|alu_|db_high[2]~11, spectrum, 1 -instance = comp, \z80_|alu_|db_high[2]~12 , z80_|alu_|db_high[2]~12, spectrum, 1 -instance = comp, \z80_|alu_|db_high[2]~10 , z80_|alu_|db_high[2]~10, spectrum, 1 -instance = comp, \z80_|alu_|db_high[2]~13 , z80_|alu_|db_high[2]~13, spectrum, 1 -instance = comp, \z80_|alu_|db_high[2]~14 , z80_|alu_|db_high[2]~14, spectrum, 1 -instance = comp, \z80_|alu_|db[6]~22 , z80_|alu_|db[6]~22, spectrum, 1 -instance = comp, \z80_|alu_|db[6]~23 , z80_|alu_|db[6]~23, spectrum, 1 -instance = comp, \z80_|alu_control_|out[6]~1 , z80_|alu_control_|out[6]~1, spectrum, 1 -instance = comp, \z80_|alu_control_|out[6]~2 , z80_|alu_control_|out[6]~2, spectrum, 1 -instance = comp, \z80_|alu_control_|db[6]~19 , z80_|alu_control_|db[6]~19, spectrum, 1 -instance = comp, \z80_|alu_control_|db[6]~20 , z80_|alu_control_|db[6]~20, spectrum, 1 -instance = comp, \z80_|alu_control_|db[6]~21 , z80_|alu_control_|db[6]~21, spectrum, 1 -instance = comp, \z80_|alu_control_|db[6]~22 , z80_|alu_control_|db[6]~22, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_zero_oe~0 , z80_|execute_|ctl_bus_zero_oe~0, spectrum, 1 -instance = comp, \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 , z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3, spectrum, 1 -instance = comp, \z80_|interrupts_|im1 , z80_|interrupts_|im1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_ff_oe~0 , z80_|execute_|ctl_bus_ff_oe~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_ff_oe~1 , z80_|execute_|ctl_bus_ff_oe~1, spectrum, 1 -instance = comp, \z80_|bus_control_|db[0]~4 , z80_|bus_control_|db[0]~4, spectrum, 1 -instance = comp, \z80_|bus_control_|db[6]~8 , z80_|bus_control_|db[6]~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~37 , z80_|execute_|ctl_mRead~37, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~28 , z80_|execute_|ctl_mRead~28, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~29 , z80_|execute_|ctl_mRead~29, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~30 , z80_|execute_|ctl_mRead~30, spectrum, 1 -instance = comp, \z80_|execute_|setM1~37 , z80_|execute_|setM1~37, spectrum, 1 -instance = comp, \z80_|execute_|setM1~55 , z80_|execute_|setM1~55, spectrum, 1 -instance = comp, \z80_|execute_|setM1~38 , z80_|execute_|setM1~38, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~34 , z80_|execute_|ctl_mRead~34, spectrum, 1 -instance = comp, \z80_|execute_|nextM~3 , z80_|execute_|nextM~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~31 , z80_|execute_|ctl_mRead~31, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~32 , z80_|execute_|ctl_mRead~32, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~33 , z80_|execute_|ctl_mRead~33, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~35 , z80_|execute_|ctl_mRead~35, spectrum, 1 -instance = comp, \z80_|memory_ifc_|DFFE_mrd_ff1 , z80_|memory_ifc_|DFFE_mrd_ff1, spectrum, 1 -instance = comp, \z80_|memory_ifc_|wait_mrd~feeder , z80_|memory_ifc_|wait_mrd~feeder, spectrum, 1 -instance = comp, \z80_|memory_ifc_|wait_mrd , z80_|memory_ifc_|wait_mrd, spectrum, 1 -instance = comp, \z80_|memory_ifc_|DFFE_mrd_ff3 , z80_|memory_ifc_|DFFE_mrd_ff3, spectrum, 1 -instance = comp, \z80_|memory_ifc_|nRD_out~1 , z80_|memory_ifc_|nRD_out~1, spectrum, 1 +instance = comp, \z80_|bus_control_|db[1]~10 , z80_|bus_control_|db[1]~10, spectrum, 1 instance = comp, \z80_|execute_|nextM~4 , z80_|execute_|nextM~4, spectrum, 1 instance = comp, \z80_|execute_|ctl_iorw~12 , z80_|execute_|ctl_iorw~12, spectrum, 1 instance = comp, \z80_|execute_|ctl_iorw~8 , z80_|execute_|ctl_iorw~8, spectrum, 1 instance = comp, \z80_|execute_|ctl_iorw~9 , z80_|execute_|ctl_iorw~9, spectrum, 1 instance = comp, \z80_|memory_ifc_|DFFE_iorq_ff1 , z80_|memory_ifc_|DFFE_iorq_ff1, spectrum, 1 -instance = comp, \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder , z80_|memory_ifc_|SYNTHESIZED_WIRE_15~feeder, spectrum, 1 instance = comp, \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 , z80_|memory_ifc_|SYNTHESIZED_WIRE_15, spectrum, 1 +instance = comp, \z80_|memory_ifc_|wait_iorq~feeder , z80_|memory_ifc_|wait_iorq~feeder, spectrum, 1 instance = comp, \z80_|memory_ifc_|wait_iorq , z80_|memory_ifc_|wait_iorq, spectrum, 1 instance = comp, \z80_|memory_ifc_|DFFE_iorq_ff4 , z80_|memory_ifc_|DFFE_iorq_ff4, spectrum, 1 instance = comp, \z80_|memory_ifc_|iorq~0 , z80_|memory_ifc_|iorq~0, spectrum, 1 -instance = comp, \z80_|execute_|fIORead~1 , z80_|execute_|fIORead~1, spectrum, 1 -instance = comp, \z80_|execute_|fIORead~2 , z80_|execute_|fIORead~2, spectrum, 1 -instance = comp, \z80_|execute_|fIORead~0 , z80_|execute_|fIORead~0, spectrum, 1 -instance = comp, \z80_|execute_|fIORead~3 , z80_|execute_|fIORead~3, spectrum, 1 instance = comp, \z80_|memory_ifc_|DFFE_m1_ff1 , z80_|memory_ifc_|DFFE_m1_ff1, spectrum, 1 instance = comp, \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0 , z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0, spectrum, 1 instance = comp, \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 , z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1, spectrum, 1 instance = comp, \z80_|memory_ifc_|DFFE_m1_ff3 , z80_|memory_ifc_|DFFE_m1_ff3, spectrum, 1 instance = comp, \z80_|memory_ifc_|nRD_out~0 , z80_|memory_ifc_|nRD_out~0, spectrum, 1 +instance = comp, \z80_|execute_|fIORead~0 , z80_|execute_|fIORead~0, spectrum, 1 +instance = comp, \z80_|execute_|fIORead~1 , z80_|execute_|fIORead~1, spectrum, 1 +instance = comp, \z80_|execute_|fIORead~2 , z80_|execute_|fIORead~2, spectrum, 1 +instance = comp, \z80_|execute_|fIOWrite~1 , z80_|execute_|fIOWrite~1, spectrum, 1 +instance = comp, \z80_|execute_|fIORead~3 , z80_|execute_|fIORead~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~30 , z80_|execute_|ctl_mRead~30, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~31 , z80_|execute_|ctl_mRead~31, spectrum, 1 +instance = comp, \z80_|execute_|nextM~3 , z80_|execute_|nextM~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~29 , z80_|execute_|ctl_mRead~29, spectrum, 1 +instance = comp, \z80_|execute_|setM1~58 , z80_|execute_|setM1~58, spectrum, 1 +instance = comp, \z80_|execute_|setM1~38 , z80_|execute_|setM1~38, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~4 , z80_|execute_|fMRead~4, spectrum, 1 +instance = comp, \z80_|execute_|setM1~39 , z80_|execute_|setM1~39, spectrum, 1 +instance = comp, \z80_|execute_|setM1~40 , z80_|execute_|setM1~40, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~32 , z80_|execute_|ctl_mRead~32, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~33 , z80_|execute_|ctl_mRead~33, spectrum, 1 +instance = comp, \z80_|memory_ifc_|DFFE_mrd_ff1 , z80_|memory_ifc_|DFFE_mrd_ff1, spectrum, 1 +instance = comp, \z80_|memory_ifc_|wait_mrd~feeder , z80_|memory_ifc_|wait_mrd~feeder, spectrum, 1 +instance = comp, \z80_|memory_ifc_|wait_mrd , z80_|memory_ifc_|wait_mrd, spectrum, 1 +instance = comp, \z80_|memory_ifc_|DFFE_mrd_ff3 , z80_|memory_ifc_|DFFE_mrd_ff3, spectrum, 1 +instance = comp, \z80_|memory_ifc_|nRD_out~1 , z80_|memory_ifc_|nRD_out~1, spectrum, 1 instance = comp, \z80_|memory_ifc_|nRD_out~2 , z80_|memory_ifc_|nRD_out~2, spectrum, 1 +instance = comp, \z80_|execute_|fIOWrite~3 , z80_|execute_|fIOWrite~3, spectrum, 1 +instance = comp, \z80_|execute_|fIOWrite~4 , z80_|execute_|fIOWrite~4, spectrum, 1 +instance = comp, \z80_|execute_|fIOWrite~2 , z80_|execute_|fIOWrite~2, spectrum, 1 +instance = comp, \z80_|execute_|fIOWrite~5 , z80_|execute_|fIOWrite~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mWrite~15 , z80_|execute_|ctl_mWrite~15, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mWrite~12 , z80_|execute_|ctl_mWrite~12, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mWrite~13 , z80_|execute_|ctl_mWrite~13, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mWrite~14 , z80_|execute_|ctl_mWrite~14, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mWrite~16 , z80_|execute_|ctl_mWrite~16, spectrum, 1 +instance = comp, \z80_|memory_ifc_|DFFE_mwr_ff1 , z80_|memory_ifc_|DFFE_mwr_ff1, spectrum, 1 +instance = comp, \z80_|memory_ifc_|wait_mwr~feeder , z80_|memory_ifc_|wait_mwr~feeder, spectrum, 1 +instance = comp, \z80_|memory_ifc_|wait_mwr , z80_|memory_ifc_|wait_mwr, spectrum, 1 +instance = comp, \z80_|memory_ifc_|mwr_wr , z80_|memory_ifc_|mwr_wr, spectrum, 1 +instance = comp, \z80_|memory_ifc_|nWR_out~0 , z80_|memory_ifc_|nWR_out~0, spectrum, 1 instance = comp, \Equal2~1 , Equal2~1, spectrum, 1 -instance = comp, \z80_|pin_control_|bus_db_pin_oe~0 , z80_|pin_control_|bus_db_pin_oe~0, spectrum, 1 -instance = comp, \z80_|execute_|fMWrite~5 , z80_|execute_|fMWrite~5, spectrum, 1 -instance = comp, \z80_|execute_|fMWrite~6 , z80_|execute_|fMWrite~6, spectrum, 1 -instance = comp, \z80_|execute_|fMWrite~2 , z80_|execute_|fMWrite~2, spectrum, 1 +instance = comp, \z80_|execute_|fMWrite~3 , z80_|execute_|fMWrite~3, spectrum, 1 instance = comp, \z80_|execute_|fMWrite~4 , z80_|execute_|fMWrite~4, spectrum, 1 -instance = comp, \z80_|pin_control_|bus_db_pin_oe~1 , z80_|pin_control_|bus_db_pin_oe~1, spectrum, 1 -instance = comp, \z80_|pin_control_|bus_db_pin_oe~2 , z80_|pin_control_|bus_db_pin_oe~2, spectrum, 1 +instance = comp, \z80_|execute_|fMWrite~0 , z80_|execute_|fMWrite~0, spectrum, 1 +instance = comp, \z80_|execute_|fMWrite~2 , z80_|execute_|fMWrite~2, spectrum, 1 instance = comp, \z80_|pin_control_|bus_db_pin_oe~3 , z80_|pin_control_|bus_db_pin_oe~3, spectrum, 1 -instance = comp, \z80_|execute_|fMWrite~7 , z80_|execute_|fMWrite~7, spectrum, 1 -instance = comp, \z80_|pin_control_|bus_db_pin_oe~4 , z80_|pin_control_|bus_db_pin_oe~4, spectrum, 1 -instance = comp, \z80_|pin_control_|bus_db_pin_oe~7 , z80_|pin_control_|bus_db_pin_oe~7, spectrum, 1 -instance = comp, \z80_|pin_control_|bus_db_pin_oe~6 , z80_|pin_control_|bus_db_pin_oe~6, spectrum, 1 -instance = comp, \z80_|execute_|fMWrite~9 , z80_|execute_|fMWrite~9, spectrum, 1 -instance = comp, \z80_|pin_control_|bus_db_pin_oe~8 , z80_|pin_control_|bus_db_pin_oe~8, spectrum, 1 -instance = comp, \z80_|pin_control_|bus_db_pin_oe~9 , z80_|pin_control_|bus_db_pin_oe~9, spectrum, 1 instance = comp, \z80_|execute_|fMWrite~8 , z80_|execute_|fMWrite~8, spectrum, 1 -instance = comp, \z80_|pin_control_|bus_db_pin_oe~5 , z80_|pin_control_|bus_db_pin_oe~5, spectrum, 1 +instance = comp, \z80_|execute_|fMWrite~7 , z80_|execute_|fMWrite~7, spectrum, 1 +instance = comp, \z80_|pin_control_|bus_db_pin_oe~16 , z80_|pin_control_|bus_db_pin_oe~16, spectrum, 1 +instance = comp, \z80_|pin_control_|bus_db_pin_oe~8 , z80_|pin_control_|bus_db_pin_oe~8, spectrum, 1 +instance = comp, \z80_|execute_|fMWrite~6 , z80_|execute_|fMWrite~6, spectrum, 1 +instance = comp, \z80_|pin_control_|bus_db_pin_oe~9 , z80_|pin_control_|bus_db_pin_oe~9, spectrum, 1 +instance = comp, \z80_|pin_control_|bus_db_pin_oe~7 , z80_|pin_control_|bus_db_pin_oe~7, spectrum, 1 instance = comp, \z80_|pin_control_|bus_db_pin_oe~10 , z80_|pin_control_|bus_db_pin_oe~10, spectrum, 1 -instance = comp, \z80_|execute_|fMWrite~10 , z80_|execute_|fMWrite~10, spectrum, 1 instance = comp, \z80_|pin_control_|bus_db_pin_oe~11 , z80_|pin_control_|bus_db_pin_oe~11, spectrum, 1 +instance = comp, \z80_|execute_|fMWrite~5 , z80_|execute_|fMWrite~5, spectrum, 1 +instance = comp, \z80_|pin_control_|bus_db_pin_oe~6 , z80_|pin_control_|bus_db_pin_oe~6, spectrum, 1 instance = comp, \z80_|pin_control_|bus_db_pin_oe~12 , z80_|pin_control_|bus_db_pin_oe~12, spectrum, 1 +instance = comp, \z80_|pin_control_|bus_db_pin_oe~4 , z80_|pin_control_|bus_db_pin_oe~4, spectrum, 1 +instance = comp, \z80_|pin_control_|bus_db_pin_oe~5 , z80_|pin_control_|bus_db_pin_oe~5, spectrum, 1 instance = comp, \z80_|pin_control_|bus_db_pin_oe~13 , z80_|pin_control_|bus_db_pin_oe~13, spectrum, 1 instance = comp, \z80_|pin_control_|bus_db_pin_oe~14 , z80_|pin_control_|bus_db_pin_oe~14, spectrum, 1 +instance = comp, \z80_|pin_control_|bus_db_pin_oe~2 , z80_|pin_control_|bus_db_pin_oe~2, spectrum, 1 +instance = comp, \z80_|pin_control_|bus_db_pin_oe~15 , z80_|pin_control_|bus_db_pin_oe~15, spectrum, 1 instance = comp, \z80_|clk_delay_|DFF_inst5~feeder , z80_|clk_delay_|DFF_inst5~feeder, spectrum, 1 instance = comp, \z80_|clk_delay_|DFF_inst5 , z80_|clk_delay_|DFF_inst5, spectrum, 1 -instance = comp, \z80_|memory_ifc_|wait_iorqinta~feeder , z80_|memory_ifc_|wait_iorqinta~feeder, spectrum, 1 instance = comp, \z80_|memory_ifc_|wait_iorqinta , z80_|memory_ifc_|wait_iorqinta, spectrum, 1 instance = comp, \z80_|memory_ifc_|DFFE_intr_ff3 , z80_|memory_ifc_|DFFE_intr_ff3, spectrum, 1 instance = comp, \z80_|memory_ifc_|nIORQ_out~0 , z80_|memory_ifc_|nIORQ_out~0, spectrum, 1 instance = comp, \Equal2~0 , Equal2~0, spectrum, 1 -instance = comp, \ExtRamWE~0 , ExtRamWE~0, spectrum, 1 -instance = comp, \z80_|address_pins_|DFFE_apin_latch[13]~13 , z80_|address_pins_|DFFE_apin_latch[13]~13, spectrum, 1 +instance = comp, \z80_|execute_|ctl_apin_mux~2 , z80_|execute_|ctl_apin_mux~2, spectrum, 1 +instance = comp, \z80_|address_pins_|DFFE_apin_latch[10]~10 , z80_|address_pins_|DFFE_apin_latch[10]~10, spectrum, 1 instance = comp, \z80_|execute_|ctl_apin_mux2~0 , z80_|execute_|ctl_apin_mux2~0, spectrum, 1 -instance = comp, \z80_|pin_control_|bus_ab_pin_we~2 , z80_|pin_control_|bus_ab_pin_we~2, spectrum, 1 -instance = comp, \z80_|pin_control_|bus_ab_pin_we~3 , z80_|pin_control_|bus_ab_pin_we~3, spectrum, 1 +instance = comp, \z80_|pin_control_|bus_ab_pin_we~0 , z80_|pin_control_|bus_ab_pin_we~0, spectrum, 1 +instance = comp, \z80_|pin_control_|bus_ab_pin_we~1 , z80_|pin_control_|bus_ab_pin_we~1, spectrum, 1 +instance = comp, \z80_|address_pins_|DFFE_apin_latch[10] , z80_|address_pins_|DFFE_apin_latch[10], spectrum, 1 +instance = comp, \PS2_DAT~input , PS2_DAT~input, spectrum, 1 +instance = comp, \KEY[0]~input , KEY[0]~input, spectrum, 1 +instance = comp, \reset~clkctrl , reset~clkctrl, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|bit_count~3 , ula_|ps2_keyboard_|bit_count~3, spectrum, 1 +instance = comp, \PS2_CLK~input , PS2_CLK~input, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|clk_filter[7]~feeder , ula_|ps2_keyboard_|clk_filter[7]~feeder, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|clk_filter[7] , ula_|ps2_keyboard_|clk_filter[7], spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|clk_filter[6]~feeder , ula_|ps2_keyboard_|clk_filter[6]~feeder, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|clk_filter[6] , ula_|ps2_keyboard_|clk_filter[6], spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|clk_filter[5]~feeder , ula_|ps2_keyboard_|clk_filter[5]~feeder, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|clk_filter[5] , ula_|ps2_keyboard_|clk_filter[5], spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|clk_filter[4]~feeder , ula_|ps2_keyboard_|clk_filter[4]~feeder, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|clk_filter[4] , ula_|ps2_keyboard_|clk_filter[4], spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|clk_filter[3]~feeder , ula_|ps2_keyboard_|clk_filter[3]~feeder, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|clk_filter[3] , ula_|ps2_keyboard_|clk_filter[3], spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|clk_filter[2]~feeder , ula_|ps2_keyboard_|clk_filter[2]~feeder, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|clk_filter[2] , ula_|ps2_keyboard_|clk_filter[2], spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|clk_filter[1]~feeder , ula_|ps2_keyboard_|clk_filter[1]~feeder, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|clk_filter[1] , ula_|ps2_keyboard_|clk_filter[1], spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|Equal0~0 , ula_|ps2_keyboard_|Equal0~0, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|Equal0~1 , ula_|ps2_keyboard_|Equal0~1, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|clk_filter[0]~0 , ula_|ps2_keyboard_|clk_filter[0]~0, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|clk_filter[0] , ula_|ps2_keyboard_|clk_filter[0], spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|ps2_clk_in~0 , ula_|ps2_keyboard_|ps2_clk_in~0, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|ps2_clk_in , ula_|ps2_keyboard_|ps2_clk_in, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|clk_edge~0 , ula_|ps2_keyboard_|clk_edge~0, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|clk_edge , ula_|ps2_keyboard_|clk_edge, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|bit_count[3] , ula_|ps2_keyboard_|bit_count[3], spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|bit_count~1 , ula_|ps2_keyboard_|bit_count~1, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|bit_count[2] , ula_|ps2_keyboard_|bit_count[2], spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|bit_count~2 , ula_|ps2_keyboard_|bit_count~2, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|bit_count[1] , ula_|ps2_keyboard_|bit_count[1], spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|bit_count~0 , ula_|ps2_keyboard_|bit_count~0, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|bit_count[0] , ula_|ps2_keyboard_|bit_count[0], spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|always1~0 , ula_|ps2_keyboard_|always1~0, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|LessThan0~0 , ula_|ps2_keyboard_|LessThan0~0, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|shiftreg[0]~0 , ula_|ps2_keyboard_|shiftreg[0]~0, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|shiftreg[8] , ula_|ps2_keyboard_|shiftreg[8], spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|shiftreg[7]~feeder , ula_|ps2_keyboard_|shiftreg[7]~feeder, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|shiftreg[7] , ula_|ps2_keyboard_|shiftreg[7], spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|shiftreg[6] , ula_|ps2_keyboard_|shiftreg[6], spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|shiftreg[5] , ula_|ps2_keyboard_|shiftreg[5], spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|shiftreg[4] , ula_|ps2_keyboard_|shiftreg[4], spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|shiftreg[3] , ula_|ps2_keyboard_|shiftreg[3], spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|shiftreg[2] , ula_|ps2_keyboard_|shiftreg[2], spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|shiftreg[1] , ula_|ps2_keyboard_|shiftreg[1], spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|shiftreg[0]~feeder , ula_|ps2_keyboard_|shiftreg[0]~feeder, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|shiftreg[0] , ula_|ps2_keyboard_|shiftreg[0], spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|WideXor0~0 , ula_|ps2_keyboard_|WideXor0~0, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|WideXor0~1 , ula_|ps2_keyboard_|WideXor0~1, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|WideXor0~2 , ula_|ps2_keyboard_|WideXor0~2, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|scan_code_ready~0 , ula_|ps2_keyboard_|scan_code_ready~0, spectrum, 1 +instance = comp, \ula_|ps2_keyboard_|scan_code_ready , ula_|ps2_keyboard_|scan_code_ready, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|Equal0~0 , ula_|zx_keyboard_|Equal0~0, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|Equal0~1 , ula_|zx_keyboard_|Equal0~1, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|released~0 , ula_|zx_keyboard_|released~0, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|released , ula_|zx_keyboard_|released, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|extended~0 , ula_|zx_keyboard_|extended~0, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|extended , ula_|zx_keyboard_|extended, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[7][1]~21 , ula_|zx_keyboard_|keys[7][1]~21, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][4]~22 , ula_|zx_keyboard_|keys[5][4]~22, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[1][4]~23 , ula_|zx_keyboard_|keys[1][4]~23, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[2][1]~24 , ula_|zx_keyboard_|keys[2][1]~24, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[2][1]~25 , ula_|zx_keyboard_|keys[2][1]~25, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[2][1] , ula_|zx_keyboard_|keys[2][1], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|key_row~0 , ula_|zx_keyboard_|key_row~0, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[3][1]~26 , ula_|zx_keyboard_|keys[3][1]~26, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[3][1]~27 , ula_|zx_keyboard_|keys[3][1]~27, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[3][1]~28 , ula_|zx_keyboard_|keys[3][1]~28, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[3][1] , ula_|zx_keyboard_|keys[3][1], spectrum, 1 +instance = comp, \z80_|address_pins_|DFFE_apin_latch[11]~11 , z80_|address_pins_|DFFE_apin_latch[11]~11, spectrum, 1 +instance = comp, \z80_|address_pins_|DFFE_apin_latch[11] , z80_|address_pins_|DFFE_apin_latch[11], spectrum, 1 +instance = comp, \z80_|address_pins_|abus[11]~19 , z80_|address_pins_|abus[11]~19, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[7][4]~17 , ula_|zx_keyboard_|keys[7][4]~17, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][4]~18 , ula_|zx_keyboard_|keys[6][4]~18, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[1][1]~19 , ula_|zx_keyboard_|keys[1][1]~19, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[1][1]~20 , ula_|zx_keyboard_|keys[1][1]~20, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[1][1] , ula_|zx_keyboard_|keys[1][1], spectrum, 1 +instance = comp, \z80_|address_pins_|DFFE_apin_latch[9]~9 , z80_|address_pins_|DFFE_apin_latch[9]~9, spectrum, 1 +instance = comp, \z80_|address_pins_|DFFE_apin_latch[9] , z80_|address_pins_|DFFE_apin_latch[9], spectrum, 1 +instance = comp, \z80_|address_pins_|abus[9]~17 , z80_|address_pins_|abus[9]~17, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[0][0]~13 , ula_|zx_keyboard_|keys[0][0]~13, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|shifted~2 , ula_|zx_keyboard_|shifted~2, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[0][1]~14 , ula_|zx_keyboard_|keys[0][1]~14, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[0][1]~15 , ula_|zx_keyboard_|keys[0][1]~15, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|WideOr17~0 , ula_|zx_keyboard_|WideOr17~0, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|shifted~5 , ula_|zx_keyboard_|shifted~5, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|shifted~4 , ula_|zx_keyboard_|shifted~4, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|shifted , ula_|zx_keyboard_|shifted, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[0][1]~12 , ula_|zx_keyboard_|keys[0][1]~12, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[0][1]~16 , ula_|zx_keyboard_|keys[0][1]~16, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[0][1] , ula_|zx_keyboard_|keys[0][1], spectrum, 1 +instance = comp, \z80_|address_pins_|DFFE_apin_latch[8]~8 , z80_|address_pins_|DFFE_apin_latch[8]~8, spectrum, 1 +instance = comp, \z80_|address_pins_|DFFE_apin_latch[8] , z80_|address_pins_|DFFE_apin_latch[8], spectrum, 1 +instance = comp, \z80_|address_pins_|abus[8]~18 , z80_|address_pins_|abus[8]~18, spectrum, 1 +instance = comp, \D[1]~26 , D[1]~26, spectrum, 1 +instance = comp, \D[1]~27 , D[1]~27, spectrum, 1 +instance = comp, \z80_|address_pins_|DFFE_apin_latch[12]~12 , z80_|address_pins_|DFFE_apin_latch[12]~12, spectrum, 1 +instance = comp, \z80_|address_pins_|DFFE_apin_latch[12] , z80_|address_pins_|DFFE_apin_latch[12], spectrum, 1 +instance = comp, \z80_|address_pins_|abus[12]~21 , z80_|address_pins_|abus[12]~21, spectrum, 1 +instance = comp, \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out , z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out, spectrum, 1 +instance = comp, \z80_|address_pins_|DFFE_apin_latch[13]~13 , z80_|address_pins_|DFFE_apin_latch[13]~13, spectrum, 1 instance = comp, \z80_|address_pins_|DFFE_apin_latch[13] , z80_|address_pins_|DFFE_apin_latch[13], spectrum, 1 instance = comp, \z80_|address_pins_|abus[13]~20 , z80_|address_pins_|abus[13]~20, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][1]~36 , ula_|zx_keyboard_|keys[5][1]~36, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][1]~34 , ula_|zx_keyboard_|keys[5][1]~34, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][1]~35 , ula_|zx_keyboard_|keys[5][1]~35, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][1]~33 , ula_|zx_keyboard_|keys[5][1]~33, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][1]~37 , ula_|zx_keyboard_|keys[5][1]~37, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][1] , ula_|zx_keyboard_|keys[5][1], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[4][1]~29 , ula_|zx_keyboard_|keys[4][1]~29, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[7][2]~30 , ula_|zx_keyboard_|keys[7][2]~30, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][2]~31 , ula_|zx_keyboard_|keys[5][2]~31, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[4][1]~32 , ula_|zx_keyboard_|keys[4][1]~32, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[4][1] , ula_|zx_keyboard_|keys[4][1], spectrum, 1 +instance = comp, \D[1]~28 , D[1]~28, spectrum, 1 +instance = comp, \z80_|address_pins_|abus[0]~16 , z80_|address_pins_|abus[0]~16, spectrum, 1 instance = comp, \z80_|address_pins_|DFFE_apin_latch[14]~14 , z80_|address_pins_|DFFE_apin_latch[14]~14, spectrum, 1 instance = comp, \z80_|address_pins_|DFFE_apin_latch[14] , z80_|address_pins_|DFFE_apin_latch[14], spectrum, 1 instance = comp, \z80_|address_pins_|abus[14]~23 , z80_|address_pins_|abus[14]~23, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][1]~40 , ula_|zx_keyboard_|keys[6][1]~40, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][1]~41 , ula_|zx_keyboard_|keys[6][1]~41, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][1]~39 , ula_|zx_keyboard_|keys[6][1]~39, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][1]~38 , ula_|zx_keyboard_|keys[6][1]~38, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][1]~42 , ula_|zx_keyboard_|keys[6][1]~42, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][1] , ula_|zx_keyboard_|keys[6][1], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|WideOr16~4 , ula_|zx_keyboard_|WideOr16~4, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|WideOr16~2 , ula_|zx_keyboard_|WideOr16~2, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|WideOr16~7 , ula_|zx_keyboard_|WideOr16~7, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|WideOr16~5 , ula_|zx_keyboard_|WideOr16~5, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|WideOr16~6 , ula_|zx_keyboard_|WideOr16~6, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[7][1]~43 , ula_|zx_keyboard_|keys[7][1]~43, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[7][1]~44 , ula_|zx_keyboard_|keys[7][1]~44, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[7][1] , ula_|zx_keyboard_|keys[7][1], spectrum, 1 instance = comp, \z80_|address_pins_|DFFE_apin_latch[15]~15 , z80_|address_pins_|DFFE_apin_latch[15]~15, spectrum, 1 instance = comp, \z80_|address_pins_|DFFE_apin_latch[15] , z80_|address_pins_|DFFE_apin_latch[15], spectrum, 1 instance = comp, \z80_|address_pins_|abus[15]~22 , z80_|address_pins_|abus[15]~22, spectrum, 1 +instance = comp, \D[1]~29 , D[1]~29, spectrum, 1 +instance = comp, \D[1]~30 , D[1]~30, spectrum, 1 +instance = comp, \ExtRamWE~0 , ExtRamWE~0, spectrum, 1 instance = comp, \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] , ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2], spectrum, 1 instance = comp, \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 , ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0, spectrum, 1 -instance = comp, \z80_|address_pins_|abus[0]~16 , z80_|address_pins_|abus[0]~16, spectrum, 1 instance = comp, \z80_|address_pins_|DFFE_apin_latch[1]~1 , z80_|address_pins_|DFFE_apin_latch[1]~1, spectrum, 1 instance = comp, \z80_|address_pins_|DFFE_apin_latch[1] , z80_|address_pins_|DFFE_apin_latch[1], spectrum, 1 instance = comp, \z80_|address_pins_|abus[1]~25 , z80_|address_pins_|abus[1]~25, spectrum, 1 @@ -2098,43 +2173,37 @@ instance = comp, \z80_|address_pins_|abus[6]~30 , z80_|address_pins_|abus[6]~30, instance = comp, \z80_|address_pins_|DFFE_apin_latch[7]~7 , z80_|address_pins_|DFFE_apin_latch[7]~7, spectrum, 1 instance = comp, \z80_|address_pins_|DFFE_apin_latch[7] , z80_|address_pins_|DFFE_apin_latch[7], spectrum, 1 instance = comp, \z80_|address_pins_|abus[7]~31 , z80_|address_pins_|abus[7]~31, spectrum, 1 -instance = comp, \z80_|address_pins_|DFFE_apin_latch[8]~8 , z80_|address_pins_|DFFE_apin_latch[8]~8, spectrum, 1 -instance = comp, \z80_|address_pins_|DFFE_apin_latch[8] , z80_|address_pins_|DFFE_apin_latch[8], spectrum, 1 -instance = comp, \z80_|address_pins_|abus[8]~18 , z80_|address_pins_|abus[8]~18, spectrum, 1 -instance = comp, \z80_|address_pins_|DFFE_apin_latch[9]~9 , z80_|address_pins_|DFFE_apin_latch[9]~9, spectrum, 1 -instance = comp, \z80_|address_pins_|DFFE_apin_latch[9] , z80_|address_pins_|DFFE_apin_latch[9], spectrum, 1 -instance = comp, \z80_|address_pins_|abus[9]~17 , z80_|address_pins_|abus[9]~17, spectrum, 1 -instance = comp, \z80_|address_pins_|DFFE_apin_latch[10]~10 , z80_|address_pins_|DFFE_apin_latch[10]~10, spectrum, 1 -instance = comp, \z80_|address_pins_|DFFE_apin_latch[10] , z80_|address_pins_|DFFE_apin_latch[10], spectrum, 1 instance = comp, \z80_|address_pins_|abus[10]~24 , z80_|address_pins_|abus[10]~24, spectrum, 1 -instance = comp, \z80_|address_pins_|DFFE_apin_latch[11]~11 , z80_|address_pins_|DFFE_apin_latch[11]~11, spectrum, 1 -instance = comp, \z80_|address_pins_|DFFE_apin_latch[11] , z80_|address_pins_|DFFE_apin_latch[11], spectrum, 1 -instance = comp, \z80_|address_pins_|abus[11]~19 , z80_|address_pins_|abus[11]~19, spectrum, 1 -instance = comp, \z80_|address_pins_|DFFE_apin_latch[12]~12 , z80_|address_pins_|DFFE_apin_latch[12]~12, spectrum, 1 -instance = comp, \z80_|address_pins_|DFFE_apin_latch[12] , z80_|address_pins_|DFFE_apin_latch[12], spectrum, 1 -instance = comp, \z80_|address_pins_|abus[12]~21 , z80_|address_pins_|abus[12]~21, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a14 , ram1|altsyncram_component|auto_generated|ram_block1a14, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|address_reg_a[0] , ram1|altsyncram_component|auto_generated|address_reg_a[0], spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] , ram1|altsyncram_component|auto_generated|out_address_reg_a[0], spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a9 , ram1|altsyncram_component|auto_generated|ram_block1a9, spectrum, 1 instance = comp, \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] , ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2], spectrum, 1 instance = comp, \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 , ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a6 , ram1|altsyncram_component|auto_generated|ram_block1a6, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|address_reg_a[1] , ram1|altsyncram_component|auto_generated|address_reg_a[1], spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] , ram1|altsyncram_component|auto_generated|out_address_reg_a[1], spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a1 , ram1|altsyncram_component|auto_generated|ram_block1a1, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder , ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|address_reg_a[0] , ram1|altsyncram_component|auto_generated|address_reg_a[0], spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] , ram1|altsyncram_component|auto_generated|out_address_reg_a[0], spectrum, 1 instance = comp, \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] , ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2], spectrum, 1 instance = comp, \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 , ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a22 , ram1|altsyncram_component|auto_generated|ram_block1a22, spectrum, 1 -instance = comp, \D[6]~90 , D[6]~90, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a17 , ram1|altsyncram_component|auto_generated|ram_block1a17, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|address_reg_a[1] , ram1|altsyncram_component|auto_generated|address_reg_a[1], spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] , ram1|altsyncram_component|auto_generated|out_address_reg_a[1], spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0 , ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0, spectrum, 1 instance = comp, \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] , ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2], spectrum, 1 instance = comp, \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 , ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a30 , ram1|altsyncram_component|auto_generated|ram_block1a30, spectrum, 1 -instance = comp, \D[6]~91 , D[6]~91, spectrum, 1 -instance = comp, \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0 , ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~0, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a25 , ram1|altsyncram_component|auto_generated|ram_block1a25, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1 , ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a1 , rom|altsyncram_component|auto_generated|ram_block1a1, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a9 , rom|altsyncram_component|auto_generated|ram_block1a9, spectrum, 1 instance = comp, \CLOCK_50~inputclkctrl , CLOCK_50~inputclkctrl, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder , ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|address_reg_a[0] , ram0|altsyncram_component|auto_generated|address_reg_a[0], spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] , ram0|altsyncram_component|auto_generated|out_address_reg_a[0], spectrum, 1 +instance = comp, \Selector3~0 , Selector3~0, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0 , ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0, spectrum, 1 instance = comp, \~GND , ~GND, spectrum, 1 instance = comp, \ula_|video_|vram_address[0]~feeder , ula_|video_|vram_address[0]~feeder, spectrum, 1 instance = comp, \ula_|video_|vram_address~0 , ula_|video_|vram_address~0, spectrum, 1 instance = comp, \ula_|video_|vram_address[0] , ula_|video_|vram_address[0], spectrum, 1 +instance = comp, \ula_|video_|vram_address[1]~feeder , ula_|video_|vram_address[1]~feeder, spectrum, 1 instance = comp, \ula_|video_|vram_address[1] , ula_|video_|vram_address[1], spectrum, 1 instance = comp, \ula_|video_|vram_address[2]~4 , ula_|video_|vram_address[2]~4, spectrum, 1 instance = comp, \ula_|video_|vram_address[2] , ula_|video_|vram_address[2], spectrum, 1 @@ -2165,513 +2234,398 @@ instance = comp, \ula_|video_|Selector3~0 , ula_|video_|Selector3~0, spectrum, 1 instance = comp, \ula_|video_|vram_address[11] , ula_|video_|vram_address[11], spectrum, 1 instance = comp, \ula_|video_|Selector2~0 , ula_|video_|Selector2~0, spectrum, 1 instance = comp, \ula_|video_|vram_address[12] , ula_|video_|vram_address[12], spectrum, 1 -instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a6 , ram0|altsyncram_component|auto_generated|ram_block1a6, spectrum, 1 -instance = comp, \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder , ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder, spectrum, 1 -instance = comp, \ram0|altsyncram_component|auto_generated|address_reg_a[0] , ram0|altsyncram_component|auto_generated|address_reg_a[0], spectrum, 1 -instance = comp, \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] , ram0|altsyncram_component|auto_generated|out_address_reg_a[0], spectrum, 1 -instance = comp, \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1 , ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~1, spectrum, 1 -instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a14 , ram0|altsyncram_component|auto_generated|ram_block1a14, spectrum, 1 -instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a14 , rom|altsyncram_component|auto_generated|ram_block1a14, spectrum, 1 -instance = comp, \D[6]~87 , D[6]~87, spectrum, 1 -instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a6 , rom|altsyncram_component|auto_generated|ram_block1a6, spectrum, 1 -instance = comp, \D[6]~88 , D[6]~88, spectrum, 1 -instance = comp, \D[6]~89 , D[6]~89, spectrum, 1 -instance = comp, \D[6]~111 , D[6]~111, spectrum, 1 -instance = comp, \raw_loader_in~input , raw_loader_in~input, spectrum, 1 -instance = comp, \D[6]~86 , D[6]~86, spectrum, 1 -instance = comp, \D[6]~100 , D[6]~100, spectrum, 1 -instance = comp, \D[6]~101 , D[6]~101, spectrum, 1 -instance = comp, \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] , z80_|data_pins_|SYNTHESIZED_WIRE_0[6], spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a9 , ram0|altsyncram_component|auto_generated|ram_block1a9, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1 , ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a1 , ram0|altsyncram_component|auto_generated|ram_block1a1, spectrum, 1 +instance = comp, \Selector1~0 , Selector1~0, spectrum, 1 +instance = comp, \Selector1~1 , Selector1~1, spectrum, 1 +instance = comp, \D[1]~81 , D[1]~81, spectrum, 1 +instance = comp, \D[1]~31 , D[1]~31, spectrum, 1 +instance = comp, \D[1]~32 , D[1]~32, spectrum, 1 +instance = comp, \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] , z80_|data_pins_|SYNTHESIZED_WIRE_0[1], spectrum, 1 instance = comp, \z80_|pin_control_|bus_db_pin_re~2 , z80_|pin_control_|bus_db_pin_re~2, spectrum, 1 instance = comp, \z80_|data_pins_|SYNTHESIZED_WIRE_2 , z80_|data_pins_|SYNTHESIZED_WIRE_2, spectrum, 1 -instance = comp, \z80_|data_pins_|dout[6] , z80_|data_pins_|dout[6], spectrum, 1 -instance = comp, \z80_|bus_control_|db[6]~9 , z80_|bus_control_|db[6]~9, spectrum, 1 -instance = comp, \z80_|ir_|opcode[6]~feeder , z80_|ir_|opcode[6]~feeder, spectrum, 1 -instance = comp, \z80_|execute_|ctl_ir_we~13 , z80_|execute_|ctl_ir_we~13, spectrum, 1 -instance = comp, \z80_|ir_|opcode[6] , z80_|ir_|opcode[6], spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal41~0 , z80_|pla_decode_|Equal41~0, spectrum, 1 +instance = comp, \z80_|data_pins_|dout[1] , z80_|data_pins_|dout[1], spectrum, 1 +instance = comp, \z80_|bus_control_|db[1]~11 , z80_|bus_control_|db[1]~11, spectrum, 1 +instance = comp, \z80_|ir_|opcode[1] , z80_|ir_|opcode[1], spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal2~0 , z80_|pla_decode_|Equal2~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~15 , z80_|execute_|ctl_mRead~15, spectrum, 1 +instance = comp, \z80_|execute_|ctl_inc_cy~39 , z80_|execute_|ctl_inc_cy~39, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sys_hilo[1]~36 , z80_|execute_|ctl_reg_sys_hilo[1]~36, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_4u~4 , z80_|execute_|ctl_sw_4u~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_wz~16 , z80_|execute_|ctl_reg_sel_wz~16, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_wz~17 , z80_|execute_|ctl_reg_sel_wz~17, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_4u~5 , z80_|execute_|ctl_sw_4u~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_4u~6 , z80_|execute_|ctl_sw_4u~6, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl_lo|latch[3] , z80_|reg_file_|b2v_latch_hl_lo|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] , z80_|reg_file_|b2v_latch_hl2_lo|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[3]~44 , z80_|reg_file_|gdfx_temp0[3]~44, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de2_lo|latch[3] , z80_|reg_file_|b2v_latch_de2_lo|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de_lo|latch[3] , z80_|reg_file_|b2v_latch_de_lo|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[3]~43 , z80_|reg_file_|gdfx_temp0[3]~43, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_wz_lo|latch[3] , z80_|reg_file_|b2v_latch_wz_lo|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] , z80_|reg_file_|b2v_latch_bc2_lo|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[3]~46 , z80_|reg_file_|gdfx_temp0[3]~46, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[3]~47 , z80_|reg_file_|gdfx_temp0[3]~47, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder , z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_iy_lo|latch[3] , z80_|reg_file_|b2v_latch_iy_lo|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_sp_lo|latch[3] , z80_|reg_file_|b2v_latch_sp_lo|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[3]~49 , z80_|reg_file_|gdfx_temp0[3]~49, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af2_lo|latch[3] , z80_|reg_file_|b2v_latch_af2_lo|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder , z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_lo|latch[3] , z80_|reg_file_|b2v_latch_af_lo|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[3]~45 , z80_|reg_file_|gdfx_temp0[3]~45, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ix_lo|latch[3] , z80_|reg_file_|b2v_latch_ix_lo|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc_lo|latch[3] , z80_|reg_file_|b2v_latch_bc_lo|latch[3], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[3]~48 , z80_|reg_file_|gdfx_temp0[3]~48, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[3]~50 , z80_|reg_file_|gdfx_temp0[3]~50, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[3]~51 , z80_|reg_file_|gdfx_temp0[3]~51, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp0[3]~52 , z80_|reg_file_|gdfx_temp0[3]~52, spectrum, 1 +instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_35 , z80_|alu_flags_|SYNTHESIZED_WIRE_35, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_xy_we~15 , z80_|execute_|ctl_flags_xy_we~15, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_xy_we~16 , z80_|execute_|ctl_flags_xy_we~16, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_xy_we~17 , z80_|execute_|ctl_flags_xy_we~17, spectrum, 1 +instance = comp, \z80_|execute_|ctl_flags_xy_we~18 , z80_|execute_|ctl_flags_xy_we~18, spectrum, 1 +instance = comp, \z80_|alu_flags_|flags_xf , z80_|alu_flags_|flags_xf, spectrum, 1 +instance = comp, \z80_|alu_control_|db[3]~33 , z80_|alu_control_|db[3]~33, spectrum, 1 +instance = comp, \z80_|sw1_|db_down[3]~2 , z80_|sw1_|db_down[3]~2, spectrum, 1 +instance = comp, \z80_|alu_control_|db[3]~34 , z80_|alu_control_|db[3]~34, spectrum, 1 +instance = comp, \z80_|alu_control_|db[3]~35 , z80_|alu_control_|db[3]~35, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[3][0]~75 , ula_|zx_keyboard_|keys[3][0]~75, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|Selector5~0 , ula_|zx_keyboard_|Selector5~0, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|Selector5~1 , ula_|zx_keyboard_|Selector5~1, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[4][3]~132 , ula_|zx_keyboard_|keys[4][3]~132, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[4][3]~106 , ula_|zx_keyboard_|keys[4][3]~106, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[4][3]~107 , ula_|zx_keyboard_|keys[4][3]~107, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[4][3]~133 , ula_|zx_keyboard_|keys[4][3]~133, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[4][3]~108 , ula_|zx_keyboard_|keys[4][3]~108, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[4][3] , ula_|zx_keyboard_|keys[4][3], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][3]~104 , ula_|zx_keyboard_|keys[5][3]~104, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][3]~105 , ula_|zx_keyboard_|keys[5][3]~105, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][3] , ula_|zx_keyboard_|keys[5][3], spectrum, 1 +instance = comp, \D[3]~55 , D[3]~55, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][4]~46 , ula_|zx_keyboard_|keys[6][4]~46, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][4]~62 , ula_|zx_keyboard_|keys[5][4]~62, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[3][3]~102 , ula_|zx_keyboard_|keys[3][3]~102, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[3][3]~103 , ula_|zx_keyboard_|keys[3][3]~103, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[3][3] , ula_|zx_keyboard_|keys[3][3], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[0][4]~96 , ula_|zx_keyboard_|keys[0][4]~96, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[2][4]~94 , ula_|zx_keyboard_|keys[2][4]~94, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[0][3]~95 , ula_|zx_keyboard_|keys[0][3]~95, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[0][3]~97 , ula_|zx_keyboard_|keys[0][3]~97, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[0][3] , ula_|zx_keyboard_|keys[0][3], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][4]~45 , ula_|zx_keyboard_|keys[6][4]~45, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[1][3]~92 , ula_|zx_keyboard_|keys[1][3]~92, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[1][3]~93 , ula_|zx_keyboard_|keys[1][3]~93, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[1][3] , ula_|zx_keyboard_|keys[1][3], spectrum, 1 +instance = comp, \D[3]~53 , D[3]~53, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[2][3]~99 , ula_|zx_keyboard_|keys[2][3]~99, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[2][3]~100 , ula_|zx_keyboard_|keys[2][3]~100, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[2][3]~98 , ula_|zx_keyboard_|keys[2][3]~98, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[2][3]~101 , ula_|zx_keyboard_|keys[2][3]~101, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[2][3] , ula_|zx_keyboard_|keys[2][3], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|key_row~3 , ula_|zx_keyboard_|key_row~3, spectrum, 1 +instance = comp, \D[3]~54 , D[3]~54, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[0][4]~109 , ula_|zx_keyboard_|keys[0][4]~109, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[7][2]~60 , ula_|zx_keyboard_|keys[7][2]~60, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[7][3]~110 , ula_|zx_keyboard_|keys[7][3]~110, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[7][3]~111 , ula_|zx_keyboard_|keys[7][3]~111, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[7][3]~112 , ula_|zx_keyboard_|keys[7][3]~112, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[7][3] , ula_|zx_keyboard_|keys[7][3], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|Selector13~0 , ula_|zx_keyboard_|Selector13~0, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][3]~113 , ula_|zx_keyboard_|keys[6][3]~113, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][3]~114 , ula_|zx_keyboard_|keys[6][3]~114, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][3]~135 , ula_|zx_keyboard_|keys[6][3]~135, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][3]~136 , ula_|zx_keyboard_|keys[6][3]~136, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][3] , ula_|zx_keyboard_|keys[6][3], spectrum, 1 +instance = comp, \D[3]~56 , D[3]~56, spectrum, 1 +instance = comp, \D[3]~57 , D[3]~57, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a27 , ram1|altsyncram_component|auto_generated|ram_block1a27, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a3 , ram1|altsyncram_component|auto_generated|ram_block1a3, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a19 , ram1|altsyncram_component|auto_generated|ram_block1a19, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6 , ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a11 , ram1|altsyncram_component|auto_generated|ram_block1a11, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7 , ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a3 , rom|altsyncram_component|auto_generated|ram_block1a3, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a11 , rom|altsyncram_component|auto_generated|ram_block1a11, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a11 , ram0|altsyncram_component|auto_generated|ram_block1a11, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a3 , ram0|altsyncram_component|auto_generated|ram_block1a3, spectrum, 1 +instance = comp, \Selector3~1 , Selector3~1, spectrum, 1 +instance = comp, \Selector3~2 , Selector3~2, spectrum, 1 +instance = comp, \D[3]~85 , D[3]~85, spectrum, 1 +instance = comp, \D[3]~73 , D[3]~73, spectrum, 1 +instance = comp, \D[3]~74 , D[3]~74, spectrum, 1 +instance = comp, \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] , z80_|data_pins_|SYNTHESIZED_WIRE_0[3], spectrum, 1 +instance = comp, \z80_|data_pins_|dout[3] , z80_|data_pins_|dout[3], spectrum, 1 +instance = comp, \z80_|bus_control_|db[3]~20 , z80_|bus_control_|db[3]~20, spectrum, 1 +instance = comp, \z80_|bus_control_|db[3]~21 , z80_|bus_control_|db[3]~21, spectrum, 1 +instance = comp, \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 , z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2, spectrum, 1 +instance = comp, \z80_|interrupts_|im2 , z80_|interrupts_|im2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~10 , z80_|execute_|ctl_mRead~10, spectrum, 1 +instance = comp, \z80_|execute_|ctl_sw_mask543_en~0 , z80_|execute_|ctl_sw_mask543_en~0, spectrum, 1 +instance = comp, \z80_|alu_control_|db[7]~16 , z80_|alu_control_|db[7]~16, spectrum, 1 +instance = comp, \z80_|alu_control_|db[7]~17 , z80_|alu_control_|db[7]~17, spectrum, 1 +instance = comp, \z80_|alu_control_|db[7]~18 , z80_|alu_control_|db[7]~18, spectrum, 1 +instance = comp, \z80_|alu_control_|db[7]~19 , z80_|alu_control_|db[7]~19, spectrum, 1 +instance = comp, \z80_|bus_control_|db[7]~5 , z80_|bus_control_|db[7]~5, spectrum, 1 +instance = comp, \D[5]~67 , D[5]~67, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a7 , ram1|altsyncram_component|auto_generated|ram_block1a7, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a23 , ram1|altsyncram_component|auto_generated|ram_block1a23, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14 , ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a31 , ram1|altsyncram_component|auto_generated|ram_block1a31, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a15 , ram1|altsyncram_component|auto_generated|ram_block1a15, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15 , ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a15 , rom|altsyncram_component|auto_generated|ram_block1a15, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a15 , ram0|altsyncram_component|auto_generated|ram_block1a15, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a7 , ram0|altsyncram_component|auto_generated|ram_block1a7, spectrum, 1 +instance = comp, \Mux0~0 , Mux0~0, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a7 , rom|altsyncram_component|auto_generated|ram_block1a7, spectrum, 1 +instance = comp, \Mux0~1 , Mux0~1, spectrum, 1 +instance = comp, \D[7]~89 , D[7]~89, spectrum, 1 +instance = comp, \D[7]~72 , D[7]~72, spectrum, 1 +instance = comp, \D[0]~84 , D[0]~84, spectrum, 1 +instance = comp, \D[7]~80 , D[7]~80, spectrum, 1 +instance = comp, \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] , z80_|data_pins_|SYNTHESIZED_WIRE_0[7], spectrum, 1 +instance = comp, \z80_|data_pins_|dout[7] , z80_|data_pins_|dout[7], spectrum, 1 +instance = comp, \z80_|bus_control_|db[7]~7 , z80_|bus_control_|db[7]~7, spectrum, 1 +instance = comp, \z80_|ir_|opcode[7] , z80_|ir_|opcode[7], spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal6~0 , z80_|pla_decode_|Equal6~0, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal12~0 , z80_|pla_decode_|Equal12~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~16 , z80_|execute_|ctl_mRead~16, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~24 , z80_|execute_|fMRead~24, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~25 , z80_|execute_|fMRead~25, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~21 , z80_|execute_|ctl_mRead~21, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~16 , z80_|execute_|fMRead~16, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~14 , z80_|execute_|fMRead~14, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~15 , z80_|execute_|fMRead~15, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~12 , z80_|execute_|fMRead~12, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~11 , z80_|execute_|fMRead~11, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~13 , z80_|execute_|fMRead~13, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~17 , z80_|execute_|fMRead~17, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~22 , z80_|execute_|fMRead~22, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~27 , z80_|execute_|fMRead~27, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~37 , z80_|execute_|fMRead~37, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~31 , z80_|execute_|fMRead~31, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~29 , z80_|execute_|fMRead~29, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~30 , z80_|execute_|fMRead~30, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~28 , z80_|execute_|fMRead~28, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~32 , z80_|execute_|fMRead~32, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~33 , z80_|execute_|fMRead~33, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~23 , z80_|execute_|fMRead~23, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~34 , z80_|execute_|fMRead~34, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~35 , z80_|execute_|fMRead~35, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_pc~19 , z80_|execute_|ctl_reg_sel_pc~19, spectrum, 1 +instance = comp, \z80_|execute_|fMRead~36 , z80_|execute_|fMRead~36, spectrum, 1 +instance = comp, \z80_|pin_control_|bus_db_pin_re , z80_|pin_control_|bus_db_pin_re, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[2][4]~118 , ula_|zx_keyboard_|keys[2][4]~118, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[2][4]~119 , ula_|zx_keyboard_|keys[2][4]~119, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[2][4]~120 , ula_|zx_keyboard_|keys[2][4]~120, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[2][4] , ula_|zx_keyboard_|keys[2][4], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[3][4]~129 , ula_|zx_keyboard_|keys[3][4]~129, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[3][4]~116 , ula_|zx_keyboard_|keys[3][4]~116, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[3][4]~134 , ula_|zx_keyboard_|keys[3][4]~134, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[3][4]~117 , ula_|zx_keyboard_|keys[3][4]~117, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[3][4] , ula_|zx_keyboard_|keys[3][4], spectrum, 1 +instance = comp, \D[4]~60 , D[4]~60, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|Equal0~2 , ula_|zx_keyboard_|Equal0~2, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[1][4]~121 , ula_|zx_keyboard_|keys[1][4]~121, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[1][4] , ula_|zx_keyboard_|keys[1][4], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[0][4]~115 , ula_|zx_keyboard_|keys[0][4]~115, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[0][4] , ula_|zx_keyboard_|keys[0][4], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|key_row~4 , ula_|zx_keyboard_|key_row~4, spectrum, 1 +instance = comp, \D[4]~61 , D[4]~61, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[4][4]~124 , ula_|zx_keyboard_|keys[4][4]~124, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[4][4]~125 , ula_|zx_keyboard_|keys[4][4]~125, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[4][4]~126 , ula_|zx_keyboard_|keys[4][4]~126, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[4][4] , ula_|zx_keyboard_|keys[4][4], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][4]~122 , ula_|zx_keyboard_|keys[5][4]~122, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][4]~123 , ula_|zx_keyboard_|keys[5][4]~123, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][4] , ula_|zx_keyboard_|keys[5][4], spectrum, 1 +instance = comp, \D[4]~62 , D[4]~62, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[7][4]~49 , ula_|zx_keyboard_|keys[7][4]~49, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|shifted~3 , ula_|zx_keyboard_|shifted~3, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[7][4]~127 , ula_|zx_keyboard_|keys[7][4]~127, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[7][4] , ula_|zx_keyboard_|keys[7][4], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][4]~128 , ula_|zx_keyboard_|keys[6][4]~128, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][4] , ula_|zx_keyboard_|keys[6][4], spectrum, 1 +instance = comp, \D[4]~63 , D[4]~63, spectrum, 1 +instance = comp, \D[4]~64 , D[4]~64, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a28 , ram1|altsyncram_component|auto_generated|ram_block1a28, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a20 , ram1|altsyncram_component|auto_generated|ram_block1a20, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a12 , ram1|altsyncram_component|auto_generated|ram_block1a12, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a4 , ram1|altsyncram_component|auto_generated|ram_block1a4, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8 , ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9 , ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a12 , rom|altsyncram_component|auto_generated|ram_block1a12, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a12 , ram0|altsyncram_component|auto_generated|ram_block1a12, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a4 , ram0|altsyncram_component|auto_generated|ram_block1a4, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a4 , rom|altsyncram_component|auto_generated|ram_block1a4, spectrum, 1 +instance = comp, \Selector4~0 , Selector4~0, spectrum, 1 +instance = comp, \Selector4~1 , Selector4~1, spectrum, 1 +instance = comp, \D[4]~86 , D[4]~86, spectrum, 1 +instance = comp, \D[4]~75 , D[4]~75, spectrum, 1 +instance = comp, \D[4]~76 , D[4]~76, spectrum, 1 +instance = comp, \z80_|data_pins_|SYNTHESIZED_WIRE_0[4] , z80_|data_pins_|SYNTHESIZED_WIRE_0[4], spectrum, 1 +instance = comp, \z80_|data_pins_|dout[4] , z80_|data_pins_|dout[4], spectrum, 1 +instance = comp, \z80_|bus_control_|db[4]~18 , z80_|bus_control_|db[4]~18, spectrum, 1 +instance = comp, \z80_|bus_control_|db[4]~19 , z80_|bus_control_|db[4]~19, spectrum, 1 +instance = comp, \z80_|ir_|opcode[4] , z80_|ir_|opcode[4], spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal32~0 , z80_|pla_decode_|Equal32~0, spectrum, 1 instance = comp, \z80_|pla_decode_|Equal41~1 , z80_|pla_decode_|Equal41~1, spectrum, 1 instance = comp, \z80_|pla_decode_|Equal41~2 , z80_|pla_decode_|Equal41~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_bs_oe , z80_|execute_|ctl_alu_bs_oe, spectrum, 1 -instance = comp, \z80_|alu_|db_high[1]~15 , z80_|alu_|db_high[1]~15, spectrum, 1 -instance = comp, \z80_|alu_|db_high[1]~16 , z80_|alu_|db_high[1]~16, spectrum, 1 -instance = comp, \z80_|alu_|db_high[1]~17 , z80_|alu_|db_high[1]~17, spectrum, 1 -instance = comp, \z80_|alu_|db_high[1]~18 , z80_|alu_|db_high[1]~18, spectrum, 1 -instance = comp, \z80_|alu_|db_high[1]~19 , z80_|alu_|db_high[1]~19, spectrum, 1 -instance = comp, \z80_|alu_|db_high[1]~20 , z80_|alu_|db_high[1]~20, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal36~0 , z80_|pla_decode_|Equal36~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_state_tbl_cb_set , z80_|execute_|ctl_state_tbl_cb_set, spectrum, 1 +instance = comp, \z80_|execute_|ctl_state_tbl_we~8 , z80_|execute_|ctl_state_tbl_we~8, spectrum, 1 +instance = comp, \z80_|decode_state_|DFFE_instCB , z80_|decode_state_|DFFE_instCB, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal52~0 , z80_|pla_decode_|Equal52~0, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal2~1 , z80_|pla_decode_|Equal2~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_state_tbl_ed_set , z80_|execute_|ctl_state_tbl_ed_set, spectrum, 1 +instance = comp, \z80_|decode_state_|DFFE_instED , z80_|decode_state_|DFFE_instED, spectrum, 1 +instance = comp, \z80_|decode_state_|table_xx~0 , z80_|decode_state_|table_xx~0, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal34~0 , z80_|pla_decode_|Equal34~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_pc~6 , z80_|execute_|ctl_reg_sel_pc~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_pc~5 , z80_|execute_|ctl_reg_sel_pc~5, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_pc~4 , z80_|execute_|ctl_reg_sel_pc~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_pc~2 , z80_|execute_|ctl_reg_sel_pc~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_pc~3 , z80_|execute_|ctl_reg_sel_pc~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_pc~7 , z80_|execute_|ctl_reg_sel_pc~7, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_pc~8 , z80_|execute_|ctl_reg_sel_pc~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_pc~9 , z80_|execute_|ctl_reg_sel_pc~9, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_pc~10 , z80_|execute_|ctl_reg_sel_pc~10, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_pc~16 , z80_|execute_|ctl_reg_sel_pc~16, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_pc~17 , z80_|execute_|ctl_reg_sel_pc~17, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_pc~15 , z80_|execute_|ctl_reg_sel_pc~15, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_pc~18 , z80_|execute_|ctl_reg_sel_pc~18, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_sel_wz~19 , z80_|execute_|ctl_reg_sel_wz~19, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sel_pc~3 , z80_|reg_control_|reg_sel_pc~3, spectrum, 1 +instance = comp, \z80_|reg_control_|reg_sel_pc , z80_|reg_control_|reg_sel_pc, spectrum, 1 +instance = comp, \z80_|reg_file_|SYNTHESIZED_WIRE_72 , z80_|reg_file_|SYNTHESIZED_WIRE_72, spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[0]~2 , z80_|reg_file_|db_hi_as[0]~2, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_pc_hi|latch[5] , z80_|reg_file_|b2v_latch_pc_hi|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ir_hi|latch[5] , z80_|reg_file_|b2v_latch_ir_hi|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[5]~13 , z80_|reg_file_|db_hi_as[5]~13, spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[5]~14 , z80_|reg_file_|db_hi_as[5]~14, spectrum, 1 +instance = comp, \z80_|reg_file_|db_hi_as[5]~15 , z80_|reg_file_|db_hi_as[5]~15, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl_hi|latch[5] , z80_|reg_file_|b2v_latch_hl_hi|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] , z80_|reg_file_|b2v_latch_hl2_hi|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[5]~50 , z80_|reg_file_|gdfx_temp1[5]~50, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af2_hi|latch[5] , z80_|reg_file_|b2v_latch_af2_hi|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[5]~53 , z80_|reg_file_|gdfx_temp1[5]~53, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_sp_hi|latch[5] , z80_|reg_file_|b2v_latch_sp_hi|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_wz_hi|latch[5] , z80_|reg_file_|b2v_latch_wz_hi|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[5]~54 , z80_|reg_file_|gdfx_temp1[5]~54, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_ix_hi|latch[5] , z80_|reg_file_|b2v_latch_ix_hi|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_iy_hi|latch[5] , z80_|reg_file_|b2v_latch_iy_hi|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[5]~52 , z80_|reg_file_|gdfx_temp1[5]~52, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc_hi|latch[5] , z80_|reg_file_|b2v_latch_bc_hi|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] , z80_|reg_file_|b2v_latch_bc2_hi|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[5]~51 , z80_|reg_file_|gdfx_temp1[5]~51, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[5]~55 , z80_|reg_file_|gdfx_temp1[5]~55, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_hi|latch[5] , z80_|reg_file_|b2v_latch_af_hi|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_af_hi|db[5]~14 , z80_|reg_file_|b2v_latch_af_hi|db[5]~14, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de2_hi|latch[5] , z80_|reg_file_|b2v_latch_de2_hi|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de_hi|latch[5]~feeder , z80_|reg_file_|b2v_latch_de_hi|latch[5]~feeder, spectrum, 1 +instance = comp, \z80_|reg_file_|b2v_latch_de_hi|latch[5] , z80_|reg_file_|b2v_latch_de_hi|latch[5], spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[5]~49 , z80_|reg_file_|gdfx_temp1[5]~49, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[5]~56 , z80_|reg_file_|gdfx_temp1[5]~56, spectrum, 1 +instance = comp, \z80_|reg_file_|gdfx_temp1[5]~57 , z80_|reg_file_|gdfx_temp1[5]~57, spectrum, 1 +instance = comp, \z80_|alu_|db[5]~23 , z80_|alu_|db[5]~23, spectrum, 1 instance = comp, \z80_|alu_|db[5]~24 , z80_|alu_|db[5]~24, spectrum, 1 -instance = comp, \z80_|alu_|db[5]~25 , z80_|alu_|db[5]~25, spectrum, 1 instance = comp, \z80_|sw1_|db_down[5]~0 , z80_|sw1_|db_down[5]~0, spectrum, 1 instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_36 , z80_|alu_flags_|SYNTHESIZED_WIRE_36, spectrum, 1 instance = comp, \z80_|alu_flags_|flags_yf , z80_|alu_flags_|flags_yf, spectrum, 1 instance = comp, \z80_|alu_control_|db[5]~13 , z80_|alu_control_|db[5]~13, spectrum, 1 instance = comp, \z80_|alu_control_|db[5]~14 , z80_|alu_control_|db[5]~14, spectrum, 1 instance = comp, \z80_|alu_control_|db[5]~15 , z80_|alu_control_|db[5]~15, spectrum, 1 -instance = comp, \D[0]~107 , D[0]~107, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a29 , ram1|altsyncram_component|auto_generated|ram_block1a29, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a13 , ram1|altsyncram_component|auto_generated|ram_block1a13, spectrum, 1 instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a21 , ram1|altsyncram_component|auto_generated|ram_block1a21, spectrum, 1 instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a5 , ram1|altsyncram_component|auto_generated|ram_block1a5, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a13 , ram1|altsyncram_component|auto_generated|ram_block1a13, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4 , ram1|altsyncram_component|auto_generated|mux2|result_node[5]~4, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a29 , ram1|altsyncram_component|auto_generated|ram_block1a29, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5 , ram1|altsyncram_component|auto_generated|mux2|result_node[5]~5, spectrum, 1 -instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a13 , ram0|altsyncram_component|auto_generated|ram_block1a13, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10 , ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11 , ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11, spectrum, 1 instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a13 , rom|altsyncram_component|auto_generated|ram_block1a13, spectrum, 1 instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a5 , rom|altsyncram_component|auto_generated|ram_block1a5, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a13 , ram0|altsyncram_component|auto_generated|ram_block1a13, spectrum, 1 instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a5 , ram0|altsyncram_component|auto_generated|ram_block1a5, spectrum, 1 instance = comp, \Mux2~0 , Mux2~0, spectrum, 1 instance = comp, \Mux2~1 , Mux2~1, spectrum, 1 -instance = comp, \D[5]~110 , D[5]~110, spectrum, 1 -instance = comp, \D[5]~85 , D[5]~85, spectrum, 1 -instance = comp, \D[5]~99 , D[5]~99, spectrum, 1 +instance = comp, \D[5]~87 , D[5]~87, spectrum, 1 +instance = comp, \D[5]~68 , D[5]~68, spectrum, 1 +instance = comp, \D[5]~77 , D[5]~77, spectrum, 1 instance = comp, \z80_|data_pins_|SYNTHESIZED_WIRE_0[5] , z80_|data_pins_|SYNTHESIZED_WIRE_0[5], spectrum, 1 instance = comp, \z80_|data_pins_|dout[5] , z80_|data_pins_|dout[5], spectrum, 1 instance = comp, \z80_|bus_control_|db[5]~14 , z80_|bus_control_|db[5]~14, spectrum, 1 instance = comp, \z80_|bus_control_|db[5]~15 , z80_|bus_control_|db[5]~15, spectrum, 1 instance = comp, \z80_|ir_|opcode[5] , z80_|ir_|opcode[5], spectrum, 1 -instance = comp, \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 , z80_|decode_state_|SYNTHESIZED_WIRE_0~0, spectrum, 1 -instance = comp, \z80_|decode_state_|DFFE_inst4 , z80_|decode_state_|DFFE_inst4, spectrum, 1 -instance = comp, \z80_|decode_state_|use_ixiy , z80_|decode_state_|use_ixiy, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~23 , z80_|execute_|ctl_mRead~23, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~34 , z80_|execute_|fMRead~34, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~31 , z80_|execute_|fMRead~31, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~29 , z80_|execute_|fMRead~29, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~30 , z80_|execute_|fMRead~30, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~28 , z80_|execute_|fMRead~28, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~32 , z80_|execute_|fMRead~32, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_inc_oe~42 , z80_|execute_|ctl_bus_inc_oe~42, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~14 , z80_|execute_|fMRead~14, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~10 , z80_|execute_|fMRead~10, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~9 , z80_|execute_|fMRead~9, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~11 , z80_|execute_|fMRead~11, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~12 , z80_|execute_|fMRead~12, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~13 , z80_|execute_|fMRead~13, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~15 , z80_|execute_|fMRead~15, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~20 , z80_|execute_|fMRead~20, spectrum, 1 -instance = comp, \z80_|execute_|pc_inc_hold~48 , z80_|execute_|pc_inc_hold~48, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~22 , z80_|execute_|fMRead~22, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~21 , z80_|execute_|fMRead~21, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~23 , z80_|execute_|fMRead~23, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~26 , z80_|execute_|fMRead~26, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~25 , z80_|execute_|fMRead~25, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~27 , z80_|execute_|fMRead~27, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~33 , z80_|execute_|fMRead~33, spectrum, 1 -instance = comp, \z80_|execute_|fMRead~35 , z80_|execute_|fMRead~35, spectrum, 1 -instance = comp, \z80_|pin_control_|bus_db_pin_re , z80_|pin_control_|bus_db_pin_re, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a1 , ram1|altsyncram_component|auto_generated|ram_block1a1, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a9 , ram1|altsyncram_component|auto_generated|ram_block1a9, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0 , ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a17 , ram1|altsyncram_component|auto_generated|ram_block1a17, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a25 , ram1|altsyncram_component|auto_generated|ram_block1a25, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1 , ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1, spectrum, 1 -instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a9 , ram0|altsyncram_component|auto_generated|ram_block1a9, spectrum, 1 -instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a9 , rom|altsyncram_component|auto_generated|ram_block1a9, spectrum, 1 -instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a1 , rom|altsyncram_component|auto_generated|ram_block1a1, spectrum, 1 -instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a1 , ram0|altsyncram_component|auto_generated|ram_block1a1, spectrum, 1 -instance = comp, \Selector1~0 , Selector1~0, spectrum, 1 -instance = comp, \Selector1~1 , Selector1~1, spectrum, 1 -instance = comp, \D[1]~103 , D[1]~103, spectrum, 1 -instance = comp, \PS2_DAT~input , PS2_DAT~input, spectrum, 1 -instance = comp, \reset~clkctrl , reset~clkctrl, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|bit_count~0 , ula_|ps2_keyboard_|bit_count~0, spectrum, 1 -instance = comp, \PS2_CLK~input , PS2_CLK~input, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|clk_filter[7]~feeder , ula_|ps2_keyboard_|clk_filter[7]~feeder, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|clk_filter[7] , ula_|ps2_keyboard_|clk_filter[7], spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|clk_filter[6]~feeder , ula_|ps2_keyboard_|clk_filter[6]~feeder, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|clk_filter[6] , ula_|ps2_keyboard_|clk_filter[6], spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|clk_filter[5]~feeder , ula_|ps2_keyboard_|clk_filter[5]~feeder, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|clk_filter[5] , ula_|ps2_keyboard_|clk_filter[5], spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|clk_filter[4]~feeder , ula_|ps2_keyboard_|clk_filter[4]~feeder, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|clk_filter[4] , ula_|ps2_keyboard_|clk_filter[4], spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|Equal0~0 , ula_|ps2_keyboard_|Equal0~0, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|clk_filter[3]~feeder , ula_|ps2_keyboard_|clk_filter[3]~feeder, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|clk_filter[3] , ula_|ps2_keyboard_|clk_filter[3], spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|clk_filter[2]~feeder , ula_|ps2_keyboard_|clk_filter[2]~feeder, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|clk_filter[2] , ula_|ps2_keyboard_|clk_filter[2], spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|clk_filter[1]~feeder , ula_|ps2_keyboard_|clk_filter[1]~feeder, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|clk_filter[1] , ula_|ps2_keyboard_|clk_filter[1], spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|Equal0~1 , ula_|ps2_keyboard_|Equal0~1, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|clk_filter[0]~0 , ula_|ps2_keyboard_|clk_filter[0]~0, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|clk_filter[0] , ula_|ps2_keyboard_|clk_filter[0], spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|ps2_clk_in~0 , ula_|ps2_keyboard_|ps2_clk_in~0, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|ps2_clk_in , ula_|ps2_keyboard_|ps2_clk_in, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|clk_edge~0 , ula_|ps2_keyboard_|clk_edge~0, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|clk_edge , ula_|ps2_keyboard_|clk_edge, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|bit_count[0] , ula_|ps2_keyboard_|bit_count[0], spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|bit_count~1 , ula_|ps2_keyboard_|bit_count~1, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|bit_count[2] , ula_|ps2_keyboard_|bit_count[2], spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|bit_count~3 , ula_|ps2_keyboard_|bit_count~3, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|bit_count[3] , ula_|ps2_keyboard_|bit_count[3], spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|bit_count~2 , ula_|ps2_keyboard_|bit_count~2, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|bit_count[1] , ula_|ps2_keyboard_|bit_count[1], spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|always1~0 , ula_|ps2_keyboard_|always1~0, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|LessThan0~0 , ula_|ps2_keyboard_|LessThan0~0, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|shiftreg[0]~0 , ula_|ps2_keyboard_|shiftreg[0]~0, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|shiftreg[8] , ula_|ps2_keyboard_|shiftreg[8], spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|shiftreg[7] , ula_|ps2_keyboard_|shiftreg[7], spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|shiftreg[6] , ula_|ps2_keyboard_|shiftreg[6], spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|shiftreg[5] , ula_|ps2_keyboard_|shiftreg[5], spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|shiftreg[4] , ula_|ps2_keyboard_|shiftreg[4], spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|shiftreg[3] , ula_|ps2_keyboard_|shiftreg[3], spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|shiftreg[2] , ula_|ps2_keyboard_|shiftreg[2], spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|shiftreg[1] , ula_|ps2_keyboard_|shiftreg[1], spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|shiftreg[0] , ula_|ps2_keyboard_|shiftreg[0], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|Equal0~0 , ula_|zx_keyboard_|Equal0~0, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|Equal0~1 , ula_|zx_keyboard_|Equal0~1, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|extended~0 , ula_|zx_keyboard_|extended~0, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|WideXor0~1 , ula_|ps2_keyboard_|WideXor0~1, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|WideXor0~0 , ula_|ps2_keyboard_|WideXor0~0, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|WideXor0~2 , ula_|ps2_keyboard_|WideXor0~2, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|scan_code_ready~0 , ula_|ps2_keyboard_|scan_code_ready~0, spectrum, 1 -instance = comp, \ula_|ps2_keyboard_|scan_code_ready , ula_|ps2_keyboard_|scan_code_ready, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|extended , ula_|zx_keyboard_|extended, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[0][0]~15 , ula_|zx_keyboard_|keys[0][0]~15, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][1]~36 , ula_|zx_keyboard_|keys[5][1]~36, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][1]~37 , ula_|zx_keyboard_|keys[5][1]~37, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|shifted~0 , ula_|zx_keyboard_|shifted~0, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|released~0 , ula_|zx_keyboard_|released~0, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|released , ula_|zx_keyboard_|released, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|WideOr17~0 , ula_|zx_keyboard_|WideOr17~0, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|shifted~2 , ula_|zx_keyboard_|shifted~2, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|shifted~3 , ula_|zx_keyboard_|shifted~3, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|shifted , ula_|zx_keyboard_|shifted, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][1]~35 , ula_|zx_keyboard_|keys[5][1]~35, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][1]~38 , ula_|zx_keyboard_|keys[5][1]~38, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][1]~39 , ula_|zx_keyboard_|keys[5][1]~39, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][1] , ula_|zx_keyboard_|keys[5][1], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[4][1]~31 , ula_|zx_keyboard_|keys[4][1]~31, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[7][1]~23 , ula_|zx_keyboard_|keys[7][1]~23, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[7][2]~32 , ula_|zx_keyboard_|keys[7][2]~32, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][2]~33 , ula_|zx_keyboard_|keys[5][2]~33, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[4][1]~34 , ula_|zx_keyboard_|keys[4][1]~34, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[4][1] , ula_|zx_keyboard_|keys[4][1], spectrum, 1 -instance = comp, \D[1]~30 , D[1]~30, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][4]~24 , ula_|zx_keyboard_|keys[5][4]~24, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[3][1]~28 , ula_|zx_keyboard_|keys[3][1]~28, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[3][1]~29 , ula_|zx_keyboard_|keys[3][1]~29, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[3][1]~30 , ula_|zx_keyboard_|keys[3][1]~30, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[3][1] , ula_|zx_keyboard_|keys[3][1], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[1][4]~25 , ula_|zx_keyboard_|keys[1][4]~25, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[2][1]~26 , ula_|zx_keyboard_|keys[2][1]~26, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[2][1]~27 , ula_|zx_keyboard_|keys[2][1]~27, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[2][1] , ula_|zx_keyboard_|keys[2][1], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|key_row~0 , ula_|zx_keyboard_|key_row~0, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[0][1]~14 , ula_|zx_keyboard_|keys[0][1]~14, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[0][1]~16 , ula_|zx_keyboard_|keys[0][1]~16, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[0][1]~17 , ula_|zx_keyboard_|keys[0][1]~17, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[0][1]~18 , ula_|zx_keyboard_|keys[0][1]~18, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[0][1] , ula_|zx_keyboard_|keys[0][1], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[7][4]~19 , ula_|zx_keyboard_|keys[7][4]~19, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][4]~20 , ula_|zx_keyboard_|keys[6][4]~20, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[1][1]~21 , ula_|zx_keyboard_|keys[1][1]~21, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[1][1]~22 , ula_|zx_keyboard_|keys[1][1]~22, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[1][1] , ula_|zx_keyboard_|keys[1][1], spectrum, 1 -instance = comp, \D[1]~28 , D[1]~28, spectrum, 1 -instance = comp, \D[1]~29 , D[1]~29, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][1]~41 , ula_|zx_keyboard_|keys[6][1]~41, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][1]~42 , ula_|zx_keyboard_|keys[6][1]~42, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][1]~43 , ula_|zx_keyboard_|keys[6][1]~43, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][1]~40 , ula_|zx_keyboard_|keys[6][1]~40, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][1]~44 , ula_|zx_keyboard_|keys[6][1]~44, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][1] , ula_|zx_keyboard_|keys[6][1], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[7][1]~45 , ula_|zx_keyboard_|keys[7][1]~45, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|WideOr16~5 , ula_|zx_keyboard_|WideOr16~5, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|WideOr16~2 , ula_|zx_keyboard_|WideOr16~2, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|WideOr16~4 , ula_|zx_keyboard_|WideOr16~4, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|WideOr16~7 , ula_|zx_keyboard_|WideOr16~7, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|WideOr16~6 , ula_|zx_keyboard_|WideOr16~6, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[7][1]~46 , ula_|zx_keyboard_|keys[7][1]~46, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[7][1] , ula_|zx_keyboard_|keys[7][1], spectrum, 1 -instance = comp, \D[1]~31 , D[1]~31, spectrum, 1 -instance = comp, \D[1]~32 , D[1]~32, spectrum, 1 -instance = comp, \D[1]~33 , D[1]~33, spectrum, 1 -instance = comp, \D[1]~34 , D[1]~34, spectrum, 1 -instance = comp, \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] , z80_|data_pins_|SYNTHESIZED_WIRE_0[1], spectrum, 1 -instance = comp, \z80_|data_pins_|dout[1] , z80_|data_pins_|dout[1], spectrum, 1 -instance = comp, \z80_|bus_control_|db[1]~10 , z80_|bus_control_|db[1]~10, spectrum, 1 -instance = comp, \z80_|bus_control_|db[1]~11 , z80_|bus_control_|db[1]~11, spectrum, 1 -instance = comp, \z80_|ir_|opcode[1]~feeder , z80_|ir_|opcode[1]~feeder, spectrum, 1 -instance = comp, \z80_|ir_|opcode[1] , z80_|ir_|opcode[1], spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal40~0 , z80_|pla_decode_|Equal40~0, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal21~1 , z80_|pla_decode_|Equal21~1, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~26 , z80_|execute_|ctl_alu_op_low~26, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~28 , z80_|execute_|ctl_alu_op_low~28, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf_cpl~3 , z80_|execute_|ctl_flags_cf_cpl~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf_cpl~2 , z80_|execute_|ctl_flags_cf_cpl~2, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~5, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~6, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~7, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~4, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~8, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~9, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~21 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~21, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~12, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~10, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~11, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~13, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~17 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~17, spectrum, 1 -instance = comp, \z80_|execute_|ctl_alu_op_low~32 , z80_|execute_|ctl_alu_op_low~32, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~15, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~16, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~18 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~18, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~19 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~19, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_cf2~0 , z80_|alu_flags_|DFFE_inst_latch_cf2~0, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_cf2~1 , z80_|alu_flags_|DFFE_inst_latch_cf2~1, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_cf2~2 , z80_|alu_flags_|DFFE_inst_latch_cf2~2, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_cf2~3 , z80_|alu_flags_|DFFE_inst_latch_cf2~3, spectrum, 1 -instance = comp, \z80_|alu_flags_|DFFE_inst_latch_cf2 , z80_|alu_flags_|DFFE_inst_latch_cf2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_use_cf2~10 , z80_|execute_|ctl_flags_use_cf2~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_use_cf2~11 , z80_|execute_|ctl_flags_use_cf2~11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_use_cf2~8 , z80_|execute_|ctl_flags_use_cf2~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_use_cf2~9 , z80_|execute_|ctl_flags_use_cf2~9, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_use_cf2~12 , z80_|execute_|ctl_flags_use_cf2~12, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~14, spectrum, 1 -instance = comp, \z80_|alu_flags_|SYNTHESIZED_WIRE_0~20 , z80_|alu_flags_|SYNTHESIZED_WIRE_0~20, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf_cpl~10 , z80_|execute_|ctl_flags_cf_cpl~10, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf_cpl~8 , z80_|execute_|ctl_flags_cf_cpl~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf_cpl~5 , z80_|execute_|ctl_flags_cf_cpl~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf_cpl~6 , z80_|execute_|ctl_flags_cf_cpl~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf_cpl~7 , z80_|execute_|ctl_flags_cf_cpl~7, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf_set~0 , z80_|execute_|ctl_flags_cf_set~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf_cpl~4 , z80_|execute_|ctl_flags_cf_cpl~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf_cpl~9 , z80_|execute_|ctl_flags_cf_cpl~9, spectrum, 1 -instance = comp, \z80_|alu_flags_|flags_cf , z80_|alu_flags_|flags_cf, spectrum, 1 -instance = comp, \z80_|alu_control_|db[0]~8 , z80_|alu_control_|db[0]~8, spectrum, 1 -instance = comp, \z80_|sw2_|db_up[0]~0 , z80_|sw2_|db_up[0]~0, spectrum, 1 -instance = comp, \z80_|alu_control_|db[0]~9 , z80_|alu_control_|db[0]~9, spectrum, 1 -instance = comp, \z80_|alu_control_|db[0]~12 , z80_|alu_control_|db[0]~12, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][0]~67 , ula_|zx_keyboard_|keys[5][0]~67, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~8 , z80_|execute_|ctl_mRead~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_db_we~8 , z80_|execute_|ctl_bus_db_we~8, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_db_we~4 , z80_|execute_|ctl_bus_db_we~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_db_we~6 , z80_|execute_|ctl_bus_db_we~6, spectrum, 1 +instance = comp, \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 , z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_db_we~3 , z80_|execute_|ctl_bus_db_we~3, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_db_we~2 , z80_|execute_|ctl_bus_db_we~2, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_db_we~7 , z80_|execute_|ctl_bus_db_we~7, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][0]~66 , ula_|zx_keyboard_|keys[5][0]~66, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][0]~80 , ula_|zx_keyboard_|keys[5][0]~80, spectrum, 1 instance = comp, \ula_|zx_keyboard_|keys[5][0]~81 , ula_|zx_keyboard_|keys[5][0]~81, spectrum, 1 instance = comp, \ula_|zx_keyboard_|keys[5][0]~82 , ula_|zx_keyboard_|keys[5][0]~82, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][0]~83 , ula_|zx_keyboard_|keys[5][0]~83, spectrum, 1 instance = comp, \ula_|zx_keyboard_|keys[5][0] , ula_|zx_keyboard_|keys[5][0], spectrum, 1 instance = comp, \ula_|zx_keyboard_|keys[4][0]~84 , ula_|zx_keyboard_|keys[4][0]~84, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[4][0]~83 , ula_|zx_keyboard_|keys[4][0]~83, spectrum, 1 instance = comp, \ula_|zx_keyboard_|keys[4][0]~85 , ula_|zx_keyboard_|keys[4][0]~85, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[4][0]~86 , ula_|zx_keyboard_|keys[4][0]~86, spectrum, 1 instance = comp, \ula_|zx_keyboard_|keys[4][0] , ula_|zx_keyboard_|keys[4][0], spectrum, 1 -instance = comp, \D[0]~49 , D[0]~49, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|WideOr4~0 , ula_|zx_keyboard_|WideOr4~0, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys~76 , ula_|zx_keyboard_|keys~76, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[4][3]~73 , ula_|zx_keyboard_|keys[4][3]~73, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][4]~47 , ula_|zx_keyboard_|keys[6][4]~47, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|WideOr0~0 , ula_|zx_keyboard_|WideOr0~0, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys~74 , ula_|zx_keyboard_|keys~74, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[0][0]~75 , ula_|zx_keyboard_|keys[0][0]~75, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[0][0]~77 , ula_|zx_keyboard_|keys[0][0]~77, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[0][0] , ula_|zx_keyboard_|keys[0][0], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[1][0]~71 , ula_|zx_keyboard_|keys[1][0]~71, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[1][0]~72 , ula_|zx_keyboard_|keys[1][0]~72, spectrum, 1 +instance = comp, \D[0]~42 , D[0]~42, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[1][0]~78 , ula_|zx_keyboard_|keys[1][0]~78, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[1][0]~79 , ula_|zx_keyboard_|keys[1][0]~79, spectrum, 1 instance = comp, \ula_|zx_keyboard_|keys[1][0] , ula_|zx_keyboard_|keys[1][0], spectrum, 1 -instance = comp, \D[0]~47 , D[0]~47, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[2][0]~80 , ula_|zx_keyboard_|keys[2][0]~80, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[2][0] , ula_|zx_keyboard_|keys[2][0], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[3][0]~78 , ula_|zx_keyboard_|keys[3][0]~78, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[3][0]~79 , ula_|zx_keyboard_|keys[3][0]~79, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[3][0]~76 , ula_|zx_keyboard_|keys[3][0]~76, spectrum, 1 instance = comp, \ula_|zx_keyboard_|keys[3][0] , ula_|zx_keyboard_|keys[3][0], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|key_row~1 , ula_|zx_keyboard_|key_row~1, spectrum, 1 -instance = comp, \D[0]~48 , D[0]~48, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|shifted~1 , ula_|zx_keyboard_|shifted~1, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[2][0]~77 , ula_|zx_keyboard_|keys[2][0]~77, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[2][0] , ula_|zx_keyboard_|keys[2][0], spectrum, 1 +instance = comp, \D[0]~40 , D[0]~40, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|WideOr0~0 , ula_|zx_keyboard_|WideOr0~0, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys~71 , ula_|zx_keyboard_|keys~71, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[4][3]~70 , ula_|zx_keyboard_|keys[4][3]~70, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[0][0]~72 , ula_|zx_keyboard_|keys[0][0]~72, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|WideOr4~0 , ula_|zx_keyboard_|WideOr4~0, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys~73 , ula_|zx_keyboard_|keys~73, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[0][0]~74 , ula_|zx_keyboard_|keys[0][0]~74, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[0][0] , ula_|zx_keyboard_|keys[0][0], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|key_row~2 , ula_|zx_keyboard_|key_row~2, spectrum, 1 +instance = comp, \D[0]~41 , D[0]~41, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][0]~89 , ula_|zx_keyboard_|keys[6][0]~89, spectrum, 1 instance = comp, \ula_|zx_keyboard_|keys[6][0]~90 , ula_|zx_keyboard_|keys[6][0]~90, spectrum, 1 instance = comp, \ula_|zx_keyboard_|keys[6][0]~91 , ula_|zx_keyboard_|keys[6][0]~91, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][0]~92 , ula_|zx_keyboard_|keys[6][0]~92, spectrum, 1 instance = comp, \ula_|zx_keyboard_|keys[6][0] , ula_|zx_keyboard_|keys[6][0], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][4]~63 , ula_|zx_keyboard_|keys[5][4]~63, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[7][0]~131 , ula_|zx_keyboard_|keys[7][0]~131, spectrum, 1 instance = comp, \ula_|zx_keyboard_|WideOr16~3 , ula_|zx_keyboard_|WideOr16~3, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[7][0]~86 , ula_|zx_keyboard_|keys[7][0]~86, spectrum, 1 instance = comp, \ula_|zx_keyboard_|keys[7][0]~87 , ula_|zx_keyboard_|keys[7][0]~87, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[7][0]~132 , ula_|zx_keyboard_|keys[7][0]~132, spectrum, 1 instance = comp, \ula_|zx_keyboard_|keys[7][0]~88 , ula_|zx_keyboard_|keys[7][0]~88, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[7][0]~89 , ula_|zx_keyboard_|keys[7][0]~89, spectrum, 1 instance = comp, \ula_|zx_keyboard_|keys[7][0] , ula_|zx_keyboard_|keys[7][0], spectrum, 1 -instance = comp, \D[0]~50 , D[0]~50, spectrum, 1 -instance = comp, \D[0]~51 , D[0]~51, spectrum, 1 +instance = comp, \D[0]~43 , D[0]~43, spectrum, 1 +instance = comp, \D[0]~44 , D[0]~44, spectrum, 1 instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a24 , ram1|altsyncram_component|auto_generated|ram_block1a24, spectrum, 1 instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a16 , ram1|altsyncram_component|auto_generated|ram_block1a16, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a0 , ram1|altsyncram_component|auto_generated|ram_block1a0, spectrum, 1 -instance = comp, \D[0]~55 , D[0]~55, spectrum, 1 instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a8 , ram1|altsyncram_component|auto_generated|ram_block1a8, spectrum, 1 -instance = comp, \D[0]~56 , D[0]~56, spectrum, 1 -instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a0 , ram0|altsyncram_component|auto_generated|ram_block1a0, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a0 , ram1|altsyncram_component|auto_generated|ram_block1a0, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4 , ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~5 , ram1|altsyncram_component|auto_generated|mux2|result_node[0]~5, spectrum, 1 instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a8 , rom|altsyncram_component|auto_generated|ram_block1a8, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a0 , ram0|altsyncram_component|auto_generated|ram_block1a0, spectrum, 1 instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a8 , ram0|altsyncram_component|auto_generated|ram_block1a8, spectrum, 1 -instance = comp, \D[0]~52 , D[0]~52, spectrum, 1 +instance = comp, \Selector2~0 , Selector2~0, spectrum, 1 instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a0 , rom|altsyncram_component|auto_generated|ram_block1a0, spectrum, 1 -instance = comp, \D[0]~53 , D[0]~53, spectrum, 1 -instance = comp, \D[0]~54 , D[0]~54, spectrum, 1 -instance = comp, \D[0]~106 , D[0]~106, spectrum, 1 -instance = comp, \D[0]~57 , D[0]~57, spectrum, 1 -instance = comp, \D[0]~58 , D[0]~58, spectrum, 1 +instance = comp, \Selector2~1 , Selector2~1, spectrum, 1 +instance = comp, \D[0]~83 , D[0]~83, spectrum, 1 +instance = comp, \D[0]~45 , D[0]~45, spectrum, 1 +instance = comp, \D[0]~46 , D[0]~46, spectrum, 1 instance = comp, \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] , z80_|data_pins_|SYNTHESIZED_WIRE_0[0], spectrum, 1 instance = comp, \z80_|data_pins_|dout[0] , z80_|data_pins_|dout[0], spectrum, 1 instance = comp, \z80_|bus_control_|db[0]~16 , z80_|bus_control_|db[0]~16, spectrum, 1 instance = comp, \z80_|bus_control_|db[0]~17 , z80_|bus_control_|db[0]~17, spectrum, 1 instance = comp, \z80_|ir_|opcode[0] , z80_|ir_|opcode[0], spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal63~0 , z80_|pla_decode_|Equal63~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_flags_cf2_sel_daa , z80_|execute_|ctl_flags_cf2_sel_daa, spectrum, 1 -instance = comp, \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 , z80_|alu_control_|SYNTHESIZED_WIRE_2~0, spectrum, 1 -instance = comp, \z80_|alu_control_|db[6]~10 , z80_|alu_control_|db[6]~10, spectrum, 1 -instance = comp, \z80_|alu_control_|db[6]~11 , z80_|alu_control_|db[6]~11, spectrum, 1 -instance = comp, \z80_|alu_control_|db[4]~30 , z80_|alu_control_|db[4]~30, spectrum, 1 -instance = comp, \z80_|alu_control_|db[4]~31 , z80_|alu_control_|db[4]~31, spectrum, 1 -instance = comp, \z80_|alu_control_|db[4]~32 , z80_|alu_control_|db[4]~32, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[2][4]~119 , ula_|zx_keyboard_|keys[2][4]~119, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[2][4]~120 , ula_|zx_keyboard_|keys[2][4]~120, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[2][4]~95 , ula_|zx_keyboard_|keys[2][4]~95, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[2][4]~121 , ula_|zx_keyboard_|keys[2][4]~121, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[2][4] , ula_|zx_keyboard_|keys[2][4], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[3][4]~117 , ula_|zx_keyboard_|keys[3][4]~117, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[3][4]~136 , ula_|zx_keyboard_|keys[3][4]~136, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[3][4]~130 , ula_|zx_keyboard_|keys[3][4]~130, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[3][4]~118 , ula_|zx_keyboard_|keys[3][4]~118, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[3][4] , ula_|zx_keyboard_|keys[3][4], spectrum, 1 -instance = comp, \D[4]~78 , D[4]~78, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][4]~126 , ula_|zx_keyboard_|keys[6][4]~126, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][4]~128 , ula_|zx_keyboard_|keys[5][4]~128, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][4]~129 , ula_|zx_keyboard_|keys[5][4]~129, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][4] , ula_|zx_keyboard_|keys[5][4], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][4]~127 , ula_|zx_keyboard_|keys[6][4]~127, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][4] , ula_|zx_keyboard_|keys[6][4], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|Equal0~2 , ula_|zx_keyboard_|Equal0~2, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[7][4]~51 , ula_|zx_keyboard_|keys[7][4]~51, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[7][4]~125 , ula_|zx_keyboard_|keys[7][4]~125, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[7][4] , ula_|zx_keyboard_|keys[7][4], spectrum, 1 -instance = comp, \D[4]~79 , D[4]~79, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[4][4]~122 , ula_|zx_keyboard_|keys[4][4]~122, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[4][4]~123 , ula_|zx_keyboard_|keys[4][4]~123, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[4][4]~124 , ula_|zx_keyboard_|keys[4][4]~124, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[4][4] , ula_|zx_keyboard_|keys[4][4], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|key_row~3 , ula_|zx_keyboard_|key_row~3, spectrum, 1 -instance = comp, \D[4]~80 , D[4]~80, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[0][4]~111 , ula_|zx_keyboard_|keys[0][4]~111, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[0][4]~97 , ula_|zx_keyboard_|keys[0][4]~97, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[0][4]~116 , ula_|zx_keyboard_|keys[0][4]~116, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[0][4] , ula_|zx_keyboard_|keys[0][4], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[1][4]~115 , ula_|zx_keyboard_|keys[1][4]~115, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[1][4] , ula_|zx_keyboard_|keys[1][4], spectrum, 1 -instance = comp, \D[4]~77 , D[4]~77, spectrum, 1 -instance = comp, \D[4]~81 , D[4]~81, spectrum, 1 -instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a12 , rom|altsyncram_component|auto_generated|ram_block1a12, spectrum, 1 -instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a12 , ram0|altsyncram_component|auto_generated|ram_block1a12, spectrum, 1 -instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a4 , rom|altsyncram_component|auto_generated|ram_block1a4, spectrum, 1 -instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a4 , ram0|altsyncram_component|auto_generated|ram_block1a4, spectrum, 1 -instance = comp, \Selector4~0 , Selector4~0, spectrum, 1 -instance = comp, \Selector4~1 , Selector4~1, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a28 , ram1|altsyncram_component|auto_generated|ram_block1a28, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a12 , ram1|altsyncram_component|auto_generated|ram_block1a12, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a20 , ram1|altsyncram_component|auto_generated|ram_block1a20, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a4 , ram1|altsyncram_component|auto_generated|ram_block1a4, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2 , ram1|altsyncram_component|auto_generated|mux2|result_node[4]~2, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3 , ram1|altsyncram_component|auto_generated|mux2|result_node[4]~3, spectrum, 1 -instance = comp, \D[4]~109 , D[4]~109, spectrum, 1 -instance = comp, \D[4]~97 , D[4]~97, spectrum, 1 -instance = comp, \D[4]~98 , D[4]~98, spectrum, 1 -instance = comp, \z80_|data_pins_|SYNTHESIZED_WIRE_0[4] , z80_|data_pins_|SYNTHESIZED_WIRE_0[4], spectrum, 1 -instance = comp, \z80_|data_pins_|dout[4] , z80_|data_pins_|dout[4], spectrum, 1 -instance = comp, \z80_|bus_control_|db[4]~18 , z80_|bus_control_|db[4]~18, spectrum, 1 -instance = comp, \z80_|bus_control_|db[4]~19 , z80_|bus_control_|db[4]~19, spectrum, 1 -instance = comp, \z80_|ir_|opcode[4] , z80_|ir_|opcode[4], spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal21~0 , z80_|pla_decode_|Equal21~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mRead~5 , z80_|execute_|ctl_mRead~5, spectrum, 1 -instance = comp, \z80_|execute_|fIOWrite~2 , z80_|execute_|fIOWrite~2, spectrum, 1 -instance = comp, \z80_|execute_|fIOWrite~3 , z80_|execute_|fIOWrite~3, spectrum, 1 -instance = comp, \z80_|execute_|fIOWrite~4 , z80_|execute_|fIOWrite~4, spectrum, 1 -instance = comp, \z80_|execute_|fIOWrite~5 , z80_|execute_|fIOWrite~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mWrite~11 , z80_|execute_|ctl_mWrite~11, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mWrite~12 , z80_|execute_|ctl_mWrite~12, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mWrite~13 , z80_|execute_|ctl_mWrite~13, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mWrite~14 , z80_|execute_|ctl_mWrite~14, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mWrite~15 , z80_|execute_|ctl_mWrite~15, spectrum, 1 -instance = comp, \z80_|memory_ifc_|DFFE_mwr_ff1 , z80_|memory_ifc_|DFFE_mwr_ff1, spectrum, 1 -instance = comp, \z80_|memory_ifc_|wait_mwr~feeder , z80_|memory_ifc_|wait_mwr~feeder, spectrum, 1 -instance = comp, \z80_|memory_ifc_|wait_mwr , z80_|memory_ifc_|wait_mwr, spectrum, 1 -instance = comp, \z80_|memory_ifc_|mwr_wr , z80_|memory_ifc_|mwr_wr, spectrum, 1 -instance = comp, \z80_|memory_ifc_|nWR_out~0 , z80_|memory_ifc_|nWR_out~0, spectrum, 1 -instance = comp, \D[5]~84 , D[5]~84, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a23 , ram1|altsyncram_component|auto_generated|ram_block1a23, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a7 , ram1|altsyncram_component|auto_generated|ram_block1a7, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a15 , ram1|altsyncram_component|auto_generated|ram_block1a15, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6 , ram1|altsyncram_component|auto_generated|mux2|result_node[7]~6, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a31 , ram1|altsyncram_component|auto_generated|ram_block1a31, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7 , ram1|altsyncram_component|auto_generated|mux2|result_node[7]~7, spectrum, 1 -instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a15 , ram0|altsyncram_component|auto_generated|ram_block1a15, spectrum, 1 -instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a15 , rom|altsyncram_component|auto_generated|ram_block1a15, spectrum, 1 -instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a7 , rom|altsyncram_component|auto_generated|ram_block1a7, spectrum, 1 -instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a7 , ram0|altsyncram_component|auto_generated|ram_block1a7, spectrum, 1 -instance = comp, \Mux0~0 , Mux0~0, spectrum, 1 -instance = comp, \Mux0~1 , Mux0~1, spectrum, 1 -instance = comp, \D[7]~112 , D[7]~112, spectrum, 1 -instance = comp, \D[7]~94 , D[7]~94, spectrum, 1 -instance = comp, \D[7]~102 , D[7]~102, spectrum, 1 -instance = comp, \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] , z80_|data_pins_|SYNTHESIZED_WIRE_0[7], spectrum, 1 -instance = comp, \z80_|data_pins_|dout[7] , z80_|data_pins_|dout[7], spectrum, 1 -instance = comp, \z80_|bus_control_|db[7]~5 , z80_|bus_control_|db[7]~5, spectrum, 1 -instance = comp, \z80_|bus_control_|db[7]~7 , z80_|bus_control_|db[7]~7, spectrum, 1 -instance = comp, \z80_|ir_|opcode[7] , z80_|ir_|opcode[7], spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal77~0 , z80_|pla_decode_|Equal77~0, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mWrite~5 , z80_|execute_|ctl_mWrite~5, spectrum, 1 -instance = comp, \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 , z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_db_we~3 , z80_|execute_|ctl_bus_db_we~3, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_db_we~8 , z80_|execute_|ctl_bus_db_we~8, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_db_we~2 , z80_|execute_|ctl_bus_db_we~2, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_db_we~4 , z80_|execute_|ctl_bus_db_we~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_db_we~6 , z80_|execute_|ctl_bus_db_we~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_db_we~7 , z80_|execute_|ctl_bus_db_we~7, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[0][2]~50 , ula_|zx_keyboard_|keys[0][2]~50, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[0][2]~52 , ula_|zx_keyboard_|keys[0][2]~52, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[0][2] , ula_|zx_keyboard_|keys[0][2], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[3][3]~48 , ula_|zx_keyboard_|keys[3][3]~48, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[1][2]~49 , ula_|zx_keyboard_|keys[1][2]~49, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[1][2] , ula_|zx_keyboard_|keys[1][2], spectrum, 1 -instance = comp, \D[2]~35 , D[2]~35, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][2]~57 , ula_|zx_keyboard_|keys[5][2]~57, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][2]~58 , ula_|zx_keyboard_|keys[5][2]~58, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][2] , ula_|zx_keyboard_|keys[5][2], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[4][2]~59 , ula_|zx_keyboard_|keys[4][2]~59, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[4][2]~131 , ula_|zx_keyboard_|keys[4][2]~131, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[4][2]~60 , ula_|zx_keyboard_|keys[4][2]~60, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[4][2] , ula_|zx_keyboard_|keys[4][2], spectrum, 1 -instance = comp, \D[2]~37 , D[2]~37, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[3][2]~53 , ula_|zx_keyboard_|keys[3][2]~53, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[2][2]~55 , ula_|zx_keyboard_|keys[2][2]~55, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[2][2]~56 , ula_|zx_keyboard_|keys[2][2]~56, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[2][2] , ula_|zx_keyboard_|keys[2][2], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[3][2]~54 , ula_|zx_keyboard_|keys[3][2]~54, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[3][2] , ula_|zx_keyboard_|keys[3][2], spectrum, 1 -instance = comp, \D[2]~36 , D[2]~36, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][2]~68 , ula_|zx_keyboard_|keys[6][2]~68, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][2]~69 , ula_|zx_keyboard_|keys[6][2]~69, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][2]~70 , ula_|zx_keyboard_|keys[6][2]~70, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][2] , ula_|zx_keyboard_|keys[6][2], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[7][2]~61 , ula_|zx_keyboard_|keys[7][2]~61, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[7][2]~62 , ula_|zx_keyboard_|keys[7][2]~62, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[7][2]~64 , ula_|zx_keyboard_|keys[7][2]~64, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[7][2]~65 , ula_|zx_keyboard_|keys[7][2]~65, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|Selector13~0 , ula_|zx_keyboard_|Selector13~0, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[7][2]~66 , ula_|zx_keyboard_|keys[7][2]~66, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[7][2] , ula_|zx_keyboard_|keys[7][2], spectrum, 1 -instance = comp, \D[2]~38 , D[2]~38, spectrum, 1 -instance = comp, \D[2]~39 , D[2]~39, spectrum, 1 -instance = comp, \D[2]~104 , D[2]~104, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a26 , ram1|altsyncram_component|auto_generated|ram_block1a26, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a10 , ram1|altsyncram_component|auto_generated|ram_block1a10, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a18 , ram1|altsyncram_component|auto_generated|ram_block1a18, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a2 , ram1|altsyncram_component|auto_generated|ram_block1a2, spectrum, 1 -instance = comp, \D[2]~43 , D[2]~43, spectrum, 1 -instance = comp, \D[2]~44 , D[2]~44, spectrum, 1 -instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a10 , rom|altsyncram_component|auto_generated|ram_block1a10, spectrum, 1 -instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a10 , ram0|altsyncram_component|auto_generated|ram_block1a10, spectrum, 1 -instance = comp, \D[2]~40 , D[2]~40, spectrum, 1 -instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a2 , ram0|altsyncram_component|auto_generated|ram_block1a2, spectrum, 1 -instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a2 , rom|altsyncram_component|auto_generated|ram_block1a2, spectrum, 1 -instance = comp, \D[2]~41 , D[2]~41, spectrum, 1 -instance = comp, \D[2]~42 , D[2]~42, spectrum, 1 -instance = comp, \D[2]~105 , D[2]~105, spectrum, 1 -instance = comp, \D[2]~45 , D[2]~45, spectrum, 1 -instance = comp, \D[2]~46 , D[2]~46, spectrum, 1 -instance = comp, \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] , z80_|data_pins_|SYNTHESIZED_WIRE_0[2], spectrum, 1 -instance = comp, \z80_|data_pins_|dout[2] , z80_|data_pins_|dout[2], spectrum, 1 -instance = comp, \z80_|bus_control_|db[2]~12 , z80_|bus_control_|db[2]~12, spectrum, 1 -instance = comp, \z80_|bus_control_|db[2]~13 , z80_|bus_control_|db[2]~13, spectrum, 1 -instance = comp, \z80_|ir_|opcode[2] , z80_|ir_|opcode[2], spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal3~1 , z80_|pla_decode_|Equal3~1, spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal3~2 , z80_|pla_decode_|Equal3~2, spectrum, 1 instance = comp, \z80_|pla_decode_|Equal43~0 , z80_|pla_decode_|Equal43~0, spectrum, 1 instance = comp, \z80_|interrupts_|test1~2 , z80_|interrupts_|test1~2, spectrum, 1 instance = comp, \z80_|interrupts_|test1~3 , z80_|interrupts_|test1~3, spectrum, 1 @@ -2679,158 +2633,192 @@ instance = comp, \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED , z80_|interrupts_| instance = comp, \z80_|clk_delay_|SYNTHESIZED_WIRE_4 , z80_|clk_delay_|SYNTHESIZED_WIRE_4, spectrum, 1 instance = comp, \z80_|clk_delay_|SYNTHESIZED_WIRE_7 , z80_|clk_delay_|SYNTHESIZED_WIRE_7, spectrum, 1 instance = comp, \z80_|clk_delay_|hold_clk_iorq , z80_|clk_delay_|hold_clk_iorq, spectrum, 1 -instance = comp, \z80_|sequencer_|DFFE_T1_ff , z80_|sequencer_|DFFE_T1_ff, spectrum, 1 -instance = comp, \z80_|sequencer_|SYNTHESIZED_WIRE_13 , z80_|sequencer_|SYNTHESIZED_WIRE_13, spectrum, 1 -instance = comp, \z80_|sequencer_|DFFE_T2_ff , z80_|sequencer_|DFFE_T2_ff, spectrum, 1 -instance = comp, \z80_|resets_|x3 , z80_|resets_|x3, spectrum, 1 -instance = comp, \z80_|resets_|SYNTHESIZED_WIRE_12 , z80_|resets_|SYNTHESIZED_WIRE_12, spectrum, 1 -instance = comp, \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl , z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl, spectrum, 1 -instance = comp, \z80_|sequencer_|DFFE_M1_ff , z80_|sequencer_|DFFE_M1_ff, spectrum, 1 -instance = comp, \z80_|sequencer_|DFFE_M2_ff~0 , z80_|sequencer_|DFFE_M2_ff~0, spectrum, 1 -instance = comp, \z80_|sequencer_|DFFE_M2_ff , z80_|sequencer_|DFFE_M2_ff, spectrum, 1 -instance = comp, \z80_|execute_|ctl_mWrite~3 , z80_|execute_|ctl_mWrite~3, spectrum, 1 -instance = comp, \z80_|execute_|nextM~11 , z80_|execute_|nextM~11, spectrum, 1 +instance = comp, \z80_|sequencer_|DFFE_T4_ff , z80_|sequencer_|DFFE_T4_ff, spectrum, 1 +instance = comp, \z80_|execute_|ctl_eval_cond~0 , z80_|execute_|ctl_eval_cond~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~27 , z80_|execute_|ctl_mRead~27, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~26 , z80_|execute_|ctl_mRead~26, spectrum, 1 +instance = comp, \z80_|execute_|ctl_mRead~28 , z80_|execute_|ctl_mRead~28, spectrum, 1 +instance = comp, \z80_|execute_|nextM~6 , z80_|execute_|nextM~6, spectrum, 1 +instance = comp, \z80_|execute_|nextM~7 , z80_|execute_|nextM~7, spectrum, 1 instance = comp, \z80_|execute_|nextM~8 , z80_|execute_|nextM~8, spectrum, 1 instance = comp, \z80_|execute_|nextM~9 , z80_|execute_|nextM~9, spectrum, 1 instance = comp, \z80_|execute_|nextM~10 , z80_|execute_|nextM~10, spectrum, 1 instance = comp, \z80_|execute_|nextM~12 , z80_|execute_|nextM~12, spectrum, 1 instance = comp, \z80_|execute_|nextM~15 , z80_|execute_|nextM~15, spectrum, 1 -instance = comp, \z80_|execute_|nextM~6 , z80_|execute_|nextM~6, spectrum, 1 -instance = comp, \z80_|execute_|nextM~7 , z80_|execute_|nextM~7, spectrum, 1 instance = comp, \z80_|execute_|nextM~13 , z80_|execute_|nextM~13, spectrum, 1 -instance = comp, \z80_|execute_|setM1~39 , z80_|execute_|setM1~39, spectrum, 1 +instance = comp, \z80_|execute_|setM1~41 , z80_|execute_|setM1~41, spectrum, 1 instance = comp, \z80_|execute_|nextM~5 , z80_|execute_|nextM~5, spectrum, 1 instance = comp, \z80_|execute_|nextM~14 , z80_|execute_|nextM~14, spectrum, 1 -instance = comp, \z80_|sequencer_|SYNTHESIZED_WIRE_15 , z80_|sequencer_|SYNTHESIZED_WIRE_15, spectrum, 1 -instance = comp, \z80_|sequencer_|DFFE_T4_ff , z80_|sequencer_|DFFE_T4_ff, spectrum, 1 -instance = comp, \z80_|sequencer_|SYNTHESIZED_WIRE_16 , z80_|sequencer_|SYNTHESIZED_WIRE_16, spectrum, 1 -instance = comp, \z80_|sequencer_|DFFE_T5_ff , z80_|sequencer_|DFFE_T5_ff, spectrum, 1 -instance = comp, \z80_|sequencer_|SYNTHESIZED_WIRE_17 , z80_|sequencer_|SYNTHESIZED_WIRE_17, spectrum, 1 -instance = comp, \z80_|sequencer_|T6 , z80_|sequencer_|T6, spectrum, 1 -instance = comp, \z80_|execute_|setM1~13 , z80_|execute_|setM1~13, spectrum, 1 -instance = comp, \z80_|pla_decode_|Equal77~1 , z80_|pla_decode_|Equal77~1, spectrum, 1 -instance = comp, \z80_|execute_|setM1~12 , z80_|execute_|setM1~12, spectrum, 1 -instance = comp, \z80_|execute_|setM1~14 , z80_|execute_|setM1~14, spectrum, 1 -instance = comp, \z80_|execute_|setM1~41 , z80_|execute_|setM1~41, spectrum, 1 -instance = comp, \z80_|execute_|setM1~42 , z80_|execute_|setM1~42, spectrum, 1 -instance = comp, \z80_|execute_|setM1~43 , z80_|execute_|setM1~43, spectrum, 1 -instance = comp, \z80_|execute_|setM1~44 , z80_|execute_|setM1~44, spectrum, 1 -instance = comp, \z80_|execute_|setM1~50 , z80_|execute_|setM1~50, spectrum, 1 -instance = comp, \z80_|execute_|setM1~51 , z80_|execute_|setM1~51, spectrum, 1 -instance = comp, \z80_|execute_|setM1~6 , z80_|execute_|setM1~6, spectrum, 1 -instance = comp, \z80_|execute_|setM1~7 , z80_|execute_|setM1~7, spectrum, 1 -instance = comp, \z80_|execute_|setM1~8 , z80_|execute_|setM1~8, spectrum, 1 -instance = comp, \z80_|execute_|setM1~9 , z80_|execute_|setM1~9, spectrum, 1 -instance = comp, \z80_|execute_|setM1~10 , z80_|execute_|setM1~10, spectrum, 1 -instance = comp, \z80_|execute_|setM1~11 , z80_|execute_|setM1~11, spectrum, 1 -instance = comp, \z80_|execute_|setM1~17 , z80_|execute_|setM1~17, spectrum, 1 -instance = comp, \z80_|execute_|setM1~31 , z80_|execute_|setM1~31, spectrum, 1 -instance = comp, \z80_|execute_|setM1~28 , z80_|execute_|setM1~28, spectrum, 1 -instance = comp, \z80_|execute_|setM1~30 , z80_|execute_|setM1~30, spectrum, 1 -instance = comp, \z80_|execute_|setM1~32 , z80_|execute_|setM1~32, spectrum, 1 -instance = comp, \z80_|execute_|setM1~33 , z80_|execute_|setM1~33, spectrum, 1 -instance = comp, \z80_|execute_|setM1~25 , z80_|execute_|setM1~25, spectrum, 1 -instance = comp, \z80_|execute_|setM1~26 , z80_|execute_|setM1~26, spectrum, 1 -instance = comp, \z80_|execute_|setM1~24 , z80_|execute_|setM1~24, spectrum, 1 -instance = comp, \z80_|execute_|setM1~27 , z80_|execute_|setM1~27, spectrum, 1 -instance = comp, \z80_|execute_|setM1~22 , z80_|execute_|setM1~22, spectrum, 1 -instance = comp, \z80_|execute_|setM1~21 , z80_|execute_|setM1~21, spectrum, 1 -instance = comp, \z80_|execute_|setM1~53 , z80_|execute_|setM1~53, spectrum, 1 -instance = comp, \z80_|execute_|setM1~23 , z80_|execute_|setM1~23, spectrum, 1 -instance = comp, \z80_|execute_|setM1~18 , z80_|execute_|setM1~18, spectrum, 1 -instance = comp, \z80_|execute_|setM1~19 , z80_|execute_|setM1~19, spectrum, 1 -instance = comp, \z80_|execute_|setM1~20 , z80_|execute_|setM1~20, spectrum, 1 -instance = comp, \z80_|execute_|setM1~34 , z80_|execute_|setM1~34, spectrum, 1 -instance = comp, \z80_|execute_|setM1~52 , z80_|execute_|setM1~52, spectrum, 1 +instance = comp, \z80_|sequencer_|ena_M , z80_|sequencer_|ena_M, spectrum, 1 +instance = comp, \z80_|sequencer_|DFFE_T1_ff , z80_|sequencer_|DFFE_T1_ff, spectrum, 1 +instance = comp, \z80_|sequencer_|SYNTHESIZED_WIRE_13 , z80_|sequencer_|SYNTHESIZED_WIRE_13, spectrum, 1 +instance = comp, \z80_|sequencer_|DFFE_T2_ff , z80_|sequencer_|DFFE_T2_ff, spectrum, 1 instance = comp, \z80_|sequencer_|SYNTHESIZED_WIRE_14 , z80_|sequencer_|SYNTHESIZED_WIRE_14, spectrum, 1 instance = comp, \z80_|sequencer_|DFFE_T3_ff , z80_|sequencer_|DFFE_T3_ff, spectrum, 1 instance = comp, \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 , z80_|execute_|ctl_reg_sys_hilo_1M1T3_3, spectrum, 1 -instance = comp, \z80_|decode_state_|in_halt~0 , z80_|decode_state_|in_halt~0, spectrum, 1 -instance = comp, \z80_|decode_state_|in_halt~1 , z80_|decode_state_|in_halt~1, spectrum, 1 -instance = comp, \z80_|decode_state_|in_halt , z80_|decode_state_|in_halt, spectrum, 1 +instance = comp, \z80_|execute_|ctl_66_oe~2 , z80_|execute_|ctl_66_oe~2, spectrum, 1 +instance = comp, \z80_|interrupts_|im1 , z80_|interrupts_|im1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_ff_oe~0 , z80_|execute_|ctl_bus_ff_oe~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_ff_oe~1 , z80_|execute_|ctl_bus_ff_oe~1, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_zero_oe~0 , z80_|execute_|ctl_bus_zero_oe~0, spectrum, 1 +instance = comp, \z80_|bus_control_|db[0]~4 , z80_|bus_control_|db[0]~4, spectrum, 1 +instance = comp, \z80_|bus_control_|db[6]~8 , z80_|bus_control_|db[6]~8, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a22 , ram1|altsyncram_component|auto_generated|ram_block1a22, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a30 , ram1|altsyncram_component|auto_generated|ram_block1a30, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a14 , ram1|altsyncram_component|auto_generated|ram_block1a14, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a6 , ram1|altsyncram_component|auto_generated|ram_block1a6, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12 , ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13 , ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a6 , rom|altsyncram_component|auto_generated|ram_block1a6, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a14 , rom|altsyncram_component|auto_generated|ram_block1a14, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a14 , ram0|altsyncram_component|auto_generated|ram_block1a14, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a6 , ram0|altsyncram_component|auto_generated|ram_block1a6, spectrum, 1 +instance = comp, \Selector6~0 , Selector6~0, spectrum, 1 +instance = comp, \Selector6~1 , Selector6~1, spectrum, 1 +instance = comp, \D[6]~88 , D[6]~88, spectrum, 1 +instance = comp, \raw_loader_in~input , raw_loader_in~input, spectrum, 1 +instance = comp, \D[6]~69 , D[6]~69, spectrum, 1 +instance = comp, \D[6]~78 , D[6]~78, spectrum, 1 +instance = comp, \D[6]~79 , D[6]~79, spectrum, 1 +instance = comp, \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] , z80_|data_pins_|SYNTHESIZED_WIRE_0[6], spectrum, 1 +instance = comp, \z80_|data_pins_|dout[6] , z80_|data_pins_|dout[6], spectrum, 1 +instance = comp, \z80_|bus_control_|db[6]~9 , z80_|bus_control_|db[6]~9, spectrum, 1 +instance = comp, \z80_|ir_|opcode[6] , z80_|ir_|opcode[6], spectrum, 1 +instance = comp, \z80_|execute_|ctl_ir_we~10 , z80_|execute_|ctl_ir_we~10, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_db_oe~0 , z80_|execute_|ctl_bus_db_oe~0, spectrum, 1 +instance = comp, \z80_|execute_|ctl_bus_db_oe~4 , z80_|execute_|ctl_bus_db_oe~4, spectrum, 1 instance = comp, \z80_|execute_|ctl_bus_db_oe~2 , z80_|execute_|ctl_bus_db_oe~2, spectrum, 1 instance = comp, \z80_|execute_|ctl_bus_db_oe~5 , z80_|execute_|ctl_bus_db_oe~5, spectrum, 1 instance = comp, \z80_|execute_|ctl_bus_db_oe~6 , z80_|execute_|ctl_bus_db_oe~6, spectrum, 1 -instance = comp, \z80_|execute_|ctl_bus_db_oe~4 , z80_|execute_|ctl_bus_db_oe~4, spectrum, 1 instance = comp, \z80_|execute_|ctl_bus_db_oe , z80_|execute_|ctl_bus_db_oe, spectrum, 1 instance = comp, \z80_|bus_control_|db[0]~6 , z80_|bus_control_|db[0]~6, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[1][3]~93 , ula_|zx_keyboard_|keys[1][3]~93, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[1][3]~94 , ula_|zx_keyboard_|keys[1][3]~94, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[1][3] , ula_|zx_keyboard_|keys[1][3], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[0][3]~96 , ula_|zx_keyboard_|keys[0][3]~96, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[0][3]~98 , ula_|zx_keyboard_|keys[0][3]~98, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[0][3] , ula_|zx_keyboard_|keys[0][3], spectrum, 1 -instance = comp, \D[3]~65 , D[3]~65, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[3][3]~99 , ula_|zx_keyboard_|keys[3][3]~99, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[3][3]~100 , ula_|zx_keyboard_|keys[3][3]~100, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[3][3] , ula_|zx_keyboard_|keys[3][3], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[2][3]~101 , ula_|zx_keyboard_|keys[2][3]~101, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[2][3]~102 , ula_|zx_keyboard_|keys[2][3]~102, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[2][3]~133 , ula_|zx_keyboard_|keys[2][3]~133, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[2][3]~103 , ula_|zx_keyboard_|keys[2][3]~103, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[2][3] , ula_|zx_keyboard_|keys[2][3], spectrum, 1 -instance = comp, \D[3]~66 , D[3]~66, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][3]~104 , ula_|zx_keyboard_|keys[5][3]~104, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][3]~105 , ula_|zx_keyboard_|keys[5][3]~105, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[5][3] , ula_|zx_keyboard_|keys[5][3], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[4][3]~106 , ula_|zx_keyboard_|keys[4][3]~106, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|Selector5~1 , ula_|zx_keyboard_|Selector5~1, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|Selector5~0 , ula_|zx_keyboard_|Selector5~0, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[4][3]~134 , ula_|zx_keyboard_|keys[4][3]~134, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[4][3]~107 , ula_|zx_keyboard_|keys[4][3]~107, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[4][3]~135 , ula_|zx_keyboard_|keys[4][3]~135, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[4][3]~108 , ula_|zx_keyboard_|keys[4][3]~108, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[4][3] , ula_|zx_keyboard_|keys[4][3], spectrum, 1 -instance = comp, \D[3]~67 , D[3]~67, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[7][3]~112 , ula_|zx_keyboard_|keys[7][3]~112, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[7][3]~113 , ula_|zx_keyboard_|keys[7][3]~113, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[7][3]~114 , ula_|zx_keyboard_|keys[7][3]~114, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[7][3] , ula_|zx_keyboard_|keys[7][3], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][3]~109 , ula_|zx_keyboard_|keys[6][3]~109, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][3]~110 , ula_|zx_keyboard_|keys[6][3]~110, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][3]~137 , ula_|zx_keyboard_|keys[6][3]~137, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][3]~138 , ula_|zx_keyboard_|keys[6][3]~138, spectrum, 1 -instance = comp, \ula_|zx_keyboard_|keys[6][3] , ula_|zx_keyboard_|keys[6][3], spectrum, 1 -instance = comp, \ula_|zx_keyboard_|key_row~2 , ula_|zx_keyboard_|key_row~2, spectrum, 1 -instance = comp, \D[3]~68 , D[3]~68, spectrum, 1 -instance = comp, \D[3]~69 , D[3]~69, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a19 , ram1|altsyncram_component|auto_generated|ram_block1a19, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a3 , ram1|altsyncram_component|auto_generated|ram_block1a3, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a11 , ram1|altsyncram_component|auto_generated|ram_block1a11, spectrum, 1 -instance = comp, \D[3]~73 , D[3]~73, spectrum, 1 -instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a27 , ram1|altsyncram_component|auto_generated|ram_block1a27, spectrum, 1 -instance = comp, \D[3]~74 , D[3]~74, spectrum, 1 -instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a11 , rom|altsyncram_component|auto_generated|ram_block1a11, spectrum, 1 -instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a11 , ram0|altsyncram_component|auto_generated|ram_block1a11, spectrum, 1 -instance = comp, \D[3]~70 , D[3]~70, spectrum, 1 -instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a3 , rom|altsyncram_component|auto_generated|ram_block1a3, spectrum, 1 -instance = comp, \D[3]~71 , D[3]~71, spectrum, 1 -instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a3 , ram0|altsyncram_component|auto_generated|ram_block1a3, spectrum, 1 -instance = comp, \D[3]~72 , D[3]~72, spectrum, 1 -instance = comp, \D[3]~108 , D[3]~108, spectrum, 1 -instance = comp, \D[3]~95 , D[3]~95, spectrum, 1 -instance = comp, \D[3]~96 , D[3]~96, spectrum, 1 -instance = comp, \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] , z80_|data_pins_|SYNTHESIZED_WIRE_0[3], spectrum, 1 -instance = comp, \z80_|data_pins_|dout[3] , z80_|data_pins_|dout[3], spectrum, 1 -instance = comp, \z80_|bus_control_|db[3]~20 , z80_|bus_control_|db[3]~20, spectrum, 1 -instance = comp, \z80_|bus_control_|db[3]~21 , z80_|bus_control_|db[3]~21, spectrum, 1 -instance = comp, \z80_|ir_|opcode[3] , z80_|ir_|opcode[3], spectrum, 1 -instance = comp, \z80_|execute_|ctl_mWrite~4 , z80_|execute_|ctl_mWrite~4, spectrum, 1 -instance = comp, \z80_|execute_|ctl_apin_mux~2 , z80_|execute_|ctl_apin_mux~2, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[7][2]~61 , ula_|zx_keyboard_|keys[7][2]~61, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[7][2]~63 , ula_|zx_keyboard_|keys[7][2]~63, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[7][2]~64 , ula_|zx_keyboard_|keys[7][2]~64, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[7][2]~65 , ula_|zx_keyboard_|keys[7][2]~65, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[7][2] , ula_|zx_keyboard_|keys[7][2], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][2]~67 , ula_|zx_keyboard_|keys[6][2]~67, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][2]~68 , ula_|zx_keyboard_|keys[6][2]~68, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][2]~69 , ula_|zx_keyboard_|keys[6][2]~69, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[6][2] , ula_|zx_keyboard_|keys[6][2], spectrum, 1 +instance = comp, \D[2]~36 , D[2]~36, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[4][2]~58 , ula_|zx_keyboard_|keys[4][2]~58, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[4][2]~130 , ula_|zx_keyboard_|keys[4][2]~130, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[4][2]~59 , ula_|zx_keyboard_|keys[4][2]~59, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[4][2] , ula_|zx_keyboard_|keys[4][2], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][2]~56 , ula_|zx_keyboard_|keys[5][2]~56, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][2]~57 , ula_|zx_keyboard_|keys[5][2]~57, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[5][2] , ula_|zx_keyboard_|keys[5][2], spectrum, 1 +instance = comp, \D[2]~35 , D[2]~35, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[0][2]~54 , ula_|zx_keyboard_|keys[0][2]~54, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[0][2]~55 , ula_|zx_keyboard_|keys[0][2]~55, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[0][2] , ula_|zx_keyboard_|keys[0][2], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[3][2]~50 , ula_|zx_keyboard_|keys[3][2]~50, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[3][2]~51 , ula_|zx_keyboard_|keys[3][2]~51, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[3][2] , ula_|zx_keyboard_|keys[3][2], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[2][2]~52 , ula_|zx_keyboard_|keys[2][2]~52, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[2][2]~53 , ula_|zx_keyboard_|keys[2][2]~53, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[2][2] , ula_|zx_keyboard_|keys[2][2], spectrum, 1 +instance = comp, \D[2]~33 , D[2]~33, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[1][2]~47 , ula_|zx_keyboard_|keys[1][2]~47, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[1][2]~48 , ula_|zx_keyboard_|keys[1][2]~48, spectrum, 1 +instance = comp, \ula_|zx_keyboard_|keys[1][2] , ula_|zx_keyboard_|keys[1][2], spectrum, 1 +instance = comp, \ula_|zx_keyboard_|key_row~1 , ula_|zx_keyboard_|key_row~1, spectrum, 1 +instance = comp, \D[2]~34 , D[2]~34, spectrum, 1 +instance = comp, \D[2]~37 , D[2]~37, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a18 , ram1|altsyncram_component|auto_generated|ram_block1a18, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a2 , ram1|altsyncram_component|auto_generated|ram_block1a2, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a10 , ram1|altsyncram_component|auto_generated|ram_block1a10, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2 , ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|ram_block1a26 , ram1|altsyncram_component|auto_generated|ram_block1a26, spectrum, 1 +instance = comp, \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~3 , ram1|altsyncram_component|auto_generated|mux2|result_node[2]~3, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a10 , rom|altsyncram_component|auto_generated|ram_block1a10, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a2 , rom|altsyncram_component|auto_generated|ram_block1a2, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a10 , ram0|altsyncram_component|auto_generated|ram_block1a10, spectrum, 1 +instance = comp, \ram0|altsyncram_component|auto_generated|ram_block1a2 , ram0|altsyncram_component|auto_generated|ram_block1a2, spectrum, 1 +instance = comp, \Selector0~0 , Selector0~0, spectrum, 1 +instance = comp, \Selector0~1 , Selector0~1, spectrum, 1 +instance = comp, \D[2]~82 , D[2]~82, spectrum, 1 +instance = comp, \D[2]~38 , D[2]~38, spectrum, 1 +instance = comp, \D[2]~39 , D[2]~39, spectrum, 1 +instance = comp, \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] , z80_|data_pins_|SYNTHESIZED_WIRE_0[2], spectrum, 1 +instance = comp, \z80_|data_pins_|dout[2] , z80_|data_pins_|dout[2], spectrum, 1 +instance = comp, \z80_|bus_control_|db[2]~12 , z80_|bus_control_|db[2]~12, spectrum, 1 +instance = comp, \z80_|bus_control_|db[2]~13 , z80_|bus_control_|db[2]~13, spectrum, 1 +instance = comp, \z80_|ir_|opcode[2] , z80_|ir_|opcode[2], spectrum, 1 +instance = comp, \z80_|pla_decode_|Equal1~4 , z80_|pla_decode_|Equal1~4, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~26 , z80_|execute_|ctl_alu_op_low~26, spectrum, 1 +instance = comp, \z80_|execute_|ctl_alu_op_low~45 , z80_|execute_|ctl_alu_op_low~45, spectrum, 1 +instance = comp, \z80_|execute_|setM1~17 , z80_|execute_|setM1~17, spectrum, 1 +instance = comp, \z80_|execute_|setM1~18 , z80_|execute_|setM1~18, spectrum, 1 +instance = comp, \z80_|execute_|setM1~11 , z80_|execute_|setM1~11, spectrum, 1 +instance = comp, \z80_|execute_|setM1~10 , z80_|execute_|setM1~10, spectrum, 1 +instance = comp, \z80_|execute_|setM1~12 , z80_|execute_|setM1~12, spectrum, 1 +instance = comp, \z80_|execute_|setM1~8 , z80_|execute_|setM1~8, spectrum, 1 +instance = comp, \z80_|execute_|setM1~9 , z80_|execute_|setM1~9, spectrum, 1 +instance = comp, \z80_|execute_|setM1~13 , z80_|execute_|setM1~13, spectrum, 1 +instance = comp, \z80_|execute_|setM1~15 , z80_|execute_|setM1~15, spectrum, 1 +instance = comp, \z80_|execute_|setM1~14 , z80_|execute_|setM1~14, spectrum, 1 +instance = comp, \z80_|execute_|setM1~16 , z80_|execute_|setM1~16, spectrum, 1 +instance = comp, \z80_|execute_|setM1~19 , z80_|execute_|setM1~19, spectrum, 1 +instance = comp, \z80_|execute_|setM1~23 , z80_|execute_|setM1~23, spectrum, 1 +instance = comp, \z80_|execute_|setM1~22 , z80_|execute_|setM1~22, spectrum, 1 +instance = comp, \z80_|execute_|setM1~56 , z80_|execute_|setM1~56, spectrum, 1 +instance = comp, \z80_|execute_|setM1~24 , z80_|execute_|setM1~24, spectrum, 1 +instance = comp, \z80_|execute_|setM1~25 , z80_|execute_|setM1~25, spectrum, 1 +instance = comp, \z80_|execute_|setM1~26 , z80_|execute_|setM1~26, spectrum, 1 +instance = comp, \z80_|execute_|setM1~27 , z80_|execute_|setM1~27, spectrum, 1 +instance = comp, \z80_|execute_|setM1~28 , z80_|execute_|setM1~28, spectrum, 1 +instance = comp, \z80_|execute_|setM1~55 , z80_|execute_|setM1~55, spectrum, 1 +instance = comp, \z80_|execute_|setM1~29 , z80_|execute_|setM1~29, spectrum, 1 +instance = comp, \z80_|execute_|setM1~31 , z80_|execute_|setM1~31, spectrum, 1 +instance = comp, \z80_|execute_|setM1~33 , z80_|execute_|setM1~33, spectrum, 1 +instance = comp, \z80_|execute_|setM1~32 , z80_|execute_|setM1~32, spectrum, 1 +instance = comp, \z80_|execute_|setM1~34 , z80_|execute_|setM1~34, spectrum, 1 +instance = comp, \z80_|execute_|setM1~20 , z80_|execute_|setM1~20, spectrum, 1 +instance = comp, \z80_|execute_|setM1~21 , z80_|execute_|setM1~21, spectrum, 1 +instance = comp, \z80_|execute_|setM1~35 , z80_|execute_|setM1~35, spectrum, 1 +instance = comp, \z80_|execute_|setM1~43 , z80_|execute_|setM1~43, spectrum, 1 +instance = comp, \z80_|execute_|setM1~44 , z80_|execute_|setM1~44, spectrum, 1 +instance = comp, \z80_|execute_|setM1~45 , z80_|execute_|setM1~45, spectrum, 1 +instance = comp, \z80_|execute_|setM1~46 , z80_|execute_|setM1~46, spectrum, 1 +instance = comp, \z80_|execute_|setM1~52 , z80_|execute_|setM1~52, spectrum, 1 +instance = comp, \z80_|sequencer_|SYNTHESIZED_WIRE_17 , z80_|sequencer_|SYNTHESIZED_WIRE_17, spectrum, 1 +instance = comp, \z80_|sequencer_|T6 , z80_|sequencer_|T6, spectrum, 1 +instance = comp, \z80_|execute_|setM1~53 , z80_|execute_|setM1~53, spectrum, 1 +instance = comp, \z80_|execute_|setM1~54 , z80_|execute_|setM1~54, spectrum, 1 +instance = comp, \z80_|sequencer_|DFFE_M1_ff~0 , z80_|sequencer_|DFFE_M1_ff~0, spectrum, 1 +instance = comp, \z80_|sequencer_|DFFE_M1_ff , z80_|sequencer_|DFFE_M1_ff, spectrum, 1 +instance = comp, \z80_|resets_|x1~0 , z80_|resets_|x1~0, spectrum, 1 +instance = comp, \z80_|fpga_reset~feeder , z80_|fpga_reset~feeder, spectrum, 1 +instance = comp, \z80_|fpga_reset , z80_|fpga_reset, spectrum, 1 +instance = comp, \z80_|fpga_reset~clkctrl , z80_|fpga_reset~clkctrl, spectrum, 1 +instance = comp, \z80_|resets_|x1 , z80_|resets_|x1, spectrum, 1 +instance = comp, \z80_|resets_|x3 , z80_|resets_|x3, spectrum, 1 +instance = comp, \z80_|resets_|SYNTHESIZED_WIRE_12 , z80_|resets_|SYNTHESIZED_WIRE_12, spectrum, 1 +instance = comp, \z80_|resets_|SYNTHESIZED_WIRE_10~0 , z80_|resets_|SYNTHESIZED_WIRE_10~0, spectrum, 1 +instance = comp, \z80_|resets_|SYNTHESIZED_WIRE_10 , z80_|resets_|SYNTHESIZED_WIRE_10, spectrum, 1 +instance = comp, \z80_|resets_|SYNTHESIZED_WIRE_9~feeder , z80_|resets_|SYNTHESIZED_WIRE_9~feeder, spectrum, 1 +instance = comp, \z80_|resets_|SYNTHESIZED_WIRE_9 , z80_|resets_|SYNTHESIZED_WIRE_9, spectrum, 1 +instance = comp, \z80_|resets_|DFFE_intr_ff3 , z80_|resets_|DFFE_intr_ff3, spectrum, 1 +instance = comp, \z80_|resets_|clrpc_int~0 , z80_|resets_|clrpc_int~0, spectrum, 1 +instance = comp, \z80_|resets_|clrpc_int , z80_|resets_|clrpc_int, spectrum, 1 +instance = comp, \z80_|resets_|clrpc~0 , z80_|resets_|clrpc~0, spectrum, 1 +instance = comp, \z80_|address_latch_|abusz[0] , z80_|address_latch_|abusz[0], spectrum, 1 instance = comp, \z80_|address_pins_|DFFE_apin_latch[0]~0 , z80_|address_pins_|DFFE_apin_latch[0]~0, spectrum, 1 instance = comp, \z80_|address_pins_|DFFE_apin_latch[0] , z80_|address_pins_|DFFE_apin_latch[0], spectrum, 1 -instance = comp, \D[0]~59 , D[0]~59, spectrum, 1 -instance = comp, \D[0]~60 , D[0]~60, spectrum, 1 -instance = comp, \D[1]~61 , D[1]~61, spectrum, 1 -instance = comp, \D[1]~62 , D[1]~62, spectrum, 1 -instance = comp, \D[2]~63 , D[2]~63, spectrum, 1 -instance = comp, \D[2]~64 , D[2]~64, spectrum, 1 -instance = comp, \D[3]~75 , D[3]~75, spectrum, 1 -instance = comp, \D[3]~76 , D[3]~76, spectrum, 1 -instance = comp, \D[4]~82 , D[4]~82, spectrum, 1 -instance = comp, \D[4]~83 , D[4]~83, spectrum, 1 -instance = comp, \D[6]~92 , D[6]~92, spectrum, 1 -instance = comp, \D[6]~93 , D[6]~93, spectrum, 1 +instance = comp, \D[0]~47 , D[0]~47, spectrum, 1 +instance = comp, \D[0]~48 , D[0]~48, spectrum, 1 +instance = comp, \D[1]~49 , D[1]~49, spectrum, 1 +instance = comp, \D[1]~50 , D[1]~50, spectrum, 1 +instance = comp, \D[2]~51 , D[2]~51, spectrum, 1 +instance = comp, \D[2]~52 , D[2]~52, spectrum, 1 +instance = comp, \D[3]~58 , D[3]~58, spectrum, 1 +instance = comp, \D[3]~59 , D[3]~59, spectrum, 1 +instance = comp, \D[4]~65 , D[4]~65, spectrum, 1 +instance = comp, \D[4]~66 , D[4]~66, spectrum, 1 +instance = comp, \D[6]~70 , D[6]~70, spectrum, 1 +instance = comp, \D[6]~71 , D[6]~71, spectrum, 1 instance = comp, \z80_|nM1_int~3 , z80_|nM1_int~3, spectrum, 1 instance = comp, \z80_|memory_ifc_|SYNTHESIZED_WIRE_16 , z80_|memory_ifc_|SYNTHESIZED_WIRE_16, spectrum, 1 instance = comp, \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder , z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder, spectrum, 1 @@ -2848,11 +2836,11 @@ instance = comp, \ula_|i2c_loader_|divider[2]~7 , ula_|i2c_loader_|divider[2]~7, instance = comp, \ula_|i2c_loader_|divider[2] , ula_|i2c_loader_|divider[2], spectrum, 1 instance = comp, \ula_|i2c_loader_|divider[3]~9 , ula_|i2c_loader_|divider[3]~9, spectrum, 1 instance = comp, \ula_|i2c_loader_|divider[3] , ula_|i2c_loader_|divider[3], spectrum, 1 +instance = comp, \ula_|i2c_loader_|WideAnd0~0 , ula_|i2c_loader_|WideAnd0~0, spectrum, 1 instance = comp, \ula_|i2c_loader_|divider[4]~11 , ula_|i2c_loader_|divider[4]~11, spectrum, 1 instance = comp, \ula_|i2c_loader_|divider[4] , ula_|i2c_loader_|divider[4], spectrum, 1 instance = comp, \ula_|i2c_loader_|divider[5]~13 , ula_|i2c_loader_|divider[5]~13, spectrum, 1 instance = comp, \ula_|i2c_loader_|divider[5] , ula_|i2c_loader_|divider[5], spectrum, 1 -instance = comp, \ula_|i2c_loader_|WideAnd0~0 , ula_|i2c_loader_|WideAnd0~0, spectrum, 1 instance = comp, \ula_|i2c_loader_|WideAnd0 , ula_|i2c_loader_|WideAnd0, spectrum, 1 instance = comp, \ula_|i2c_loader_|state.Idle , ula_|i2c_loader_|state.Idle, spectrum, 1 instance = comp, \ula_|i2c_loader_|phase~0 , ula_|i2c_loader_|phase~0, spectrum, 1 @@ -2860,8 +2848,15 @@ instance = comp, \ula_|i2c_loader_|phase[0] , ula_|i2c_loader_|phase[0], spectru instance = comp, \ula_|i2c_loader_|phase~1 , ula_|i2c_loader_|phase~1, spectrum, 1 instance = comp, \ula_|i2c_loader_|phase[1] , ula_|i2c_loader_|phase[1], spectrum, 1 instance = comp, \ula_|i2c_loader_|nbit~5 , ula_|i2c_loader_|nbit~5, spectrum, 1 -instance = comp, \ula_|i2c_loader_|thisbyte[0]~8 , ula_|i2c_loader_|thisbyte[0]~8, spectrum, 1 +instance = comp, \ula_|i2c_loader_|state.Idle~0 , ula_|i2c_loader_|state.Idle~0, spectrum, 1 instance = comp, \ula_|i2c_loader_|Mux42~0 , ula_|i2c_loader_|Mux42~0, spectrum, 1 +instance = comp, \ula_|i2c_loader_|nbit~6 , ula_|i2c_loader_|nbit~6, spectrum, 1 +instance = comp, \ula_|i2c_loader_|nbit[1] , ula_|i2c_loader_|nbit[1], spectrum, 1 +instance = comp, \ula_|i2c_loader_|state.Done~0 , ula_|i2c_loader_|state.Done~0, spectrum, 1 +instance = comp, \ula_|i2c_loader_|state.Ack~0 , ula_|i2c_loader_|state.Ack~0, spectrum, 1 +instance = comp, \ula_|i2c_loader_|state.Ack~1 , ula_|i2c_loader_|state.Ack~1, spectrum, 1 +instance = comp, \ula_|i2c_loader_|state.Ack , ula_|i2c_loader_|state.Ack, spectrum, 1 +instance = comp, \ula_|i2c_loader_|nbit[0]~2 , ula_|i2c_loader_|nbit[0]~2, spectrum, 1 instance = comp, \ula_|i2c_loader_|nbyte~4 , ula_|i2c_loader_|nbyte~4, spectrum, 1 instance = comp, \ula_|i2c_loader_|thisbyte[0]~7 , ula_|i2c_loader_|thisbyte[0]~7, spectrum, 1 instance = comp, \I2C_SDAT~input , I2C_SDAT~input, spectrum, 1 @@ -2869,16 +2864,21 @@ instance = comp, \ula_|i2c_loader_|nbyte[0]~1 , ula_|i2c_loader_|nbyte[0]~1, spe instance = comp, \ula_|i2c_loader_|nbyte[0]~2 , ula_|i2c_loader_|nbyte[0]~2, spectrum, 1 instance = comp, \ula_|i2c_loader_|nbyte[0]~3 , ula_|i2c_loader_|nbyte[0]~3, spectrum, 1 instance = comp, \ula_|i2c_loader_|nbyte[1] , ula_|i2c_loader_|nbyte[1], spectrum, 1 -instance = comp, \ula_|i2c_loader_|state.Stop~0 , ula_|i2c_loader_|state.Stop~0, spectrum, 1 -instance = comp, \ula_|i2c_loader_|state.Stop~1 , ula_|i2c_loader_|state.Stop~1, spectrum, 1 -instance = comp, \ula_|i2c_loader_|state.Stop , ula_|i2c_loader_|state.Stop, spectrum, 1 -instance = comp, \ula_|i2c_loader_|state.Idle~0 , ula_|i2c_loader_|state.Idle~0, spectrum, 1 +instance = comp, \ula_|i2c_loader_|nbit[0]~1 , ula_|i2c_loader_|nbit[0]~1, spectrum, 1 +instance = comp, \ula_|i2c_loader_|nbit[0]~3 , ula_|i2c_loader_|nbit[0]~3, spectrum, 1 +instance = comp, \ula_|i2c_loader_|nbit[0]~4 , ula_|i2c_loader_|nbit[0]~4, spectrum, 1 +instance = comp, \ula_|i2c_loader_|nbit[0] , ula_|i2c_loader_|nbit[0], spectrum, 1 instance = comp, \ula_|i2c_loader_|nbit~0 , ula_|i2c_loader_|nbit~0, spectrum, 1 instance = comp, \ula_|i2c_loader_|nbit[2] , ula_|i2c_loader_|nbit[2], spectrum, 1 -instance = comp, \ula_|i2c_loader_|state.Done~0 , ula_|i2c_loader_|state.Done~0, spectrum, 1 -instance = comp, \ula_|i2c_loader_|state.Ack~0 , ula_|i2c_loader_|state.Ack~0, spectrum, 1 -instance = comp, \ula_|i2c_loader_|state.Ack~1 , ula_|i2c_loader_|state.Ack~1, spectrum, 1 -instance = comp, \ula_|i2c_loader_|state.Ack , ula_|i2c_loader_|state.Ack, spectrum, 1 +instance = comp, \ula_|i2c_loader_|state.Done~1 , ula_|i2c_loader_|state.Done~1, spectrum, 1 +instance = comp, \ula_|i2c_loader_|state~27 , ula_|i2c_loader_|state~27, spectrum, 1 +instance = comp, \ula_|i2c_loader_|state~24 , ula_|i2c_loader_|state~24, spectrum, 1 +instance = comp, \ula_|i2c_loader_|state~26 , ula_|i2c_loader_|state~26, spectrum, 1 +instance = comp, \ula_|i2c_loader_|state.Data~0 , ula_|i2c_loader_|state.Data~0, spectrum, 1 +instance = comp, \ula_|i2c_loader_|state.Data , ula_|i2c_loader_|state.Data, spectrum, 1 +instance = comp, \ula_|i2c_loader_|state.Done~2 , ula_|i2c_loader_|state.Done~2, spectrum, 1 +instance = comp, \ula_|i2c_loader_|state.Pause~1 , ula_|i2c_loader_|state.Pause~1, spectrum, 1 +instance = comp, \ula_|i2c_loader_|thisbyte[0]~8 , ula_|i2c_loader_|thisbyte[0]~8, spectrum, 1 instance = comp, \ula_|i2c_loader_|nbyte[1]~5 , ula_|i2c_loader_|nbyte[1]~5, spectrum, 1 instance = comp, \ula_|i2c_loader_|thisbyte[0]~18 , ula_|i2c_loader_|thisbyte[0]~18, spectrum, 1 instance = comp, \ula_|i2c_loader_|thisbyte[0] , ula_|i2c_loader_|thisbyte[0], spectrum, 1 @@ -2889,31 +2889,19 @@ instance = comp, \ula_|i2c_loader_|thisbyte[2] , ula_|i2c_loader_|thisbyte[2], s instance = comp, \ula_|i2c_loader_|thisbyte[3]~14 , ula_|i2c_loader_|thisbyte[3]~14, spectrum, 1 instance = comp, \ula_|i2c_loader_|thisbyte[3] , ula_|i2c_loader_|thisbyte[3], spectrum, 1 instance = comp, \ula_|i2c_loader_|Equal2~0 , ula_|i2c_loader_|Equal2~0, spectrum, 1 -instance = comp, \ula_|i2c_loader_|state.Pause~0 , ula_|i2c_loader_|state.Pause~0, spectrum, 1 instance = comp, \ula_|i2c_loader_|thisbyte[4]~16 , ula_|i2c_loader_|thisbyte[4]~16, spectrum, 1 instance = comp, \ula_|i2c_loader_|thisbyte[4] , ula_|i2c_loader_|thisbyte[4], spectrum, 1 -instance = comp, \ula_|i2c_loader_|state.Pause~1 , ula_|i2c_loader_|state.Pause~1, spectrum, 1 -instance = comp, \ula_|i2c_loader_|state.Done~2 , ula_|i2c_loader_|state.Done~2, spectrum, 1 +instance = comp, \ula_|i2c_loader_|Equal2~1 , ula_|i2c_loader_|Equal2~1, spectrum, 1 +instance = comp, \ula_|i2c_loader_|state.Pause~0 , ula_|i2c_loader_|state.Pause~0, spectrum, 1 instance = comp, \ula_|i2c_loader_|state.Pause~2 , ula_|i2c_loader_|state.Pause~2, spectrum, 1 -instance = comp, \ula_|i2c_loader_|state.Pause~3 , ula_|i2c_loader_|state.Pause~3, spectrum, 1 instance = comp, \ula_|i2c_loader_|state.Pause , ula_|i2c_loader_|state.Pause, spectrum, 1 instance = comp, \ula_|i2c_loader_|state~25 , ula_|i2c_loader_|state~25, spectrum, 1 instance = comp, \ula_|i2c_loader_|state.Start , ula_|i2c_loader_|state.Start, spectrum, 1 instance = comp, \ula_|i2c_loader_|nbyte~0 , ula_|i2c_loader_|nbyte~0, spectrum, 1 instance = comp, \ula_|i2c_loader_|nbyte[0] , ula_|i2c_loader_|nbyte[0], spectrum, 1 -instance = comp, \ula_|i2c_loader_|nbit[0]~1 , ula_|i2c_loader_|nbit[0]~1, spectrum, 1 -instance = comp, \ula_|i2c_loader_|nbit[0]~2 , ula_|i2c_loader_|nbit[0]~2, spectrum, 1 -instance = comp, \ula_|i2c_loader_|nbit[0]~3 , ula_|i2c_loader_|nbit[0]~3, spectrum, 1 -instance = comp, \ula_|i2c_loader_|nbit[0]~4 , ula_|i2c_loader_|nbit[0]~4, spectrum, 1 -instance = comp, \ula_|i2c_loader_|nbit[0] , ula_|i2c_loader_|nbit[0], spectrum, 1 -instance = comp, \ula_|i2c_loader_|nbit~6 , ula_|i2c_loader_|nbit~6, spectrum, 1 -instance = comp, \ula_|i2c_loader_|nbit[1] , ula_|i2c_loader_|nbit[1], spectrum, 1 -instance = comp, \ula_|i2c_loader_|state.Done~1 , ula_|i2c_loader_|state.Done~1, spectrum, 1 -instance = comp, \ula_|i2c_loader_|state~27 , ula_|i2c_loader_|state~27, spectrum, 1 -instance = comp, \ula_|i2c_loader_|state~24 , ula_|i2c_loader_|state~24, spectrum, 1 -instance = comp, \ula_|i2c_loader_|state~26 , ula_|i2c_loader_|state~26, spectrum, 1 -instance = comp, \ula_|i2c_loader_|state.Data~0 , ula_|i2c_loader_|state.Data~0, spectrum, 1 -instance = comp, \ula_|i2c_loader_|state.Data , ula_|i2c_loader_|state.Data, spectrum, 1 +instance = comp, \ula_|i2c_loader_|state.Stop~0 , ula_|i2c_loader_|state.Stop~0, spectrum, 1 +instance = comp, \ula_|i2c_loader_|state.Stop~1 , ula_|i2c_loader_|state.Stop~1, spectrum, 1 +instance = comp, \ula_|i2c_loader_|state.Stop , ula_|i2c_loader_|state.Stop, spectrum, 1 instance = comp, \ula_|i2c_loader_|scl_out~0 , ula_|i2c_loader_|scl_out~0, spectrum, 1 instance = comp, \ula_|i2c_loader_|scl_out~_Duplicate_1 , ula_|i2c_loader_|scl_out~_Duplicate_1, spectrum, 1 instance = comp, \ula_|i2c_loader_|scl_out~1 , ula_|i2c_loader_|scl_out~1, spectrum, 1 @@ -2923,32 +2911,31 @@ instance = comp, \ula_|i2c_loader_|sda_out~_Duplicate_1 , ula_|i2c_loader_|sda_o instance = comp, \ula_|i2c_loader_|shiftreg~4 , ula_|i2c_loader_|shiftreg~4, spectrum, 1 instance = comp, \ula_|i2c_loader_|Mux35~0 , ula_|i2c_loader_|Mux35~0, spectrum, 1 instance = comp, \ula_|i2c_loader_|shiftreg~13 , ula_|i2c_loader_|shiftreg~13, spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg~14 , ula_|i2c_loader_|shiftreg~14, spectrum, 1 instance = comp, \ula_|i2c_loader_|shiftreg~15 , ula_|i2c_loader_|shiftreg~15, spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg[0]~24 , ula_|i2c_loader_|shiftreg[0]~24, spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg[0]~6 , ula_|i2c_loader_|shiftreg[0]~6, spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg[0]~7 , ula_|i2c_loader_|shiftreg[0]~7, spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg[0]~8 , ula_|i2c_loader_|shiftreg[0]~8, spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg[0] , ula_|i2c_loader_|shiftreg[0], spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg~21 , ula_|i2c_loader_|shiftreg~21, spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg~22 , ula_|i2c_loader_|shiftreg~22, spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg~23 , ula_|i2c_loader_|shiftreg~23, spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg[6]~10 , ula_|i2c_loader_|shiftreg[6]~10, spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg[6]~11 , ula_|i2c_loader_|shiftreg[6]~11, spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg[1] , ula_|i2c_loader_|shiftreg[1], spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg~18 , ula_|i2c_loader_|shiftreg~18, spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg~19 , ula_|i2c_loader_|shiftreg~19, spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg~20 , ula_|i2c_loader_|shiftreg~20, spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg[2] , ula_|i2c_loader_|shiftreg[2], spectrum, 1 instance = comp, \ula_|i2c_loader_|shiftreg~16 , ula_|i2c_loader_|shiftreg~16, spectrum, 1 instance = comp, \ula_|i2c_loader_|shiftreg~17 , ula_|i2c_loader_|shiftreg~17, spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg~26 , ula_|i2c_loader_|shiftreg~26, spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg[3] , ula_|i2c_loader_|shiftreg[3], spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg~18 , ula_|i2c_loader_|shiftreg~18, spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg~20 , ula_|i2c_loader_|shiftreg~20, spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg~21 , ula_|i2c_loader_|shiftreg~21, spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg[0]~23 , ula_|i2c_loader_|shiftreg[0]~23, spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg[0]~6 , ula_|i2c_loader_|shiftreg[0]~6, spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg[0]~7 , ula_|i2c_loader_|shiftreg[0]~7, spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg[0] , ula_|i2c_loader_|shiftreg[0], spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg~22 , ula_|i2c_loader_|shiftreg~22, spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg[6]~9 , ula_|i2c_loader_|shiftreg[6]~9, spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg[6]~10 , ula_|i2c_loader_|shiftreg[6]~10, spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg[1] , ula_|i2c_loader_|shiftreg[1], spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg~19 , ula_|i2c_loader_|shiftreg~19, spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg[2] , ula_|i2c_loader_|shiftreg[2], spectrum, 1 instance = comp, \ula_|i2c_loader_|shiftreg~25 , ula_|i2c_loader_|shiftreg~25, spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg[4] , ula_|i2c_loader_|shiftreg[4], spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg[3] , ula_|i2c_loader_|shiftreg[3], spectrum, 1 instance = comp, \ula_|i2c_loader_|shiftreg~12 , ula_|i2c_loader_|shiftreg~12, spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg~14 , ula_|i2c_loader_|shiftreg~14, spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg~24 , ula_|i2c_loader_|shiftreg~24, spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg[4] , ula_|i2c_loader_|shiftreg[4], spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg~11 , ula_|i2c_loader_|shiftreg~11, spectrum, 1 instance = comp, \ula_|i2c_loader_|shiftreg[5] , ula_|i2c_loader_|shiftreg[5], spectrum, 1 -instance = comp, \ula_|i2c_loader_|shiftreg~9 , ula_|i2c_loader_|shiftreg~9, spectrum, 1 +instance = comp, \ula_|i2c_loader_|shiftreg~8 , ula_|i2c_loader_|shiftreg~8, spectrum, 1 instance = comp, \ula_|i2c_loader_|shiftreg[6] , ula_|i2c_loader_|shiftreg[6], spectrum, 1 instance = comp, \ula_|i2c_loader_|shiftreg[7]~5 , ula_|i2c_loader_|shiftreg[7]~5, spectrum, 1 instance = comp, \ula_|i2c_loader_|shiftreg[7] , ula_|i2c_loader_|shiftreg[7], spectrum, 1 @@ -2992,12 +2979,12 @@ instance = comp, \ula_|i2s_intf_|lrdivider[9]~3 , ula_|i2s_intf_|lrdivider[9]~3, instance = comp, \ula_|i2s_intf_|lrdivider[9] , ula_|i2s_intf_|lrdivider[9], spectrum, 1 instance = comp, \ula_|i2s_intf_|Equal0~0 , ula_|i2s_intf_|Equal0~0, spectrum, 1 instance = comp, \ula_|i2s_intf_|Equal0~2 , ula_|i2s_intf_|Equal0~2, spectrum, 1 -instance = comp, \ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder , ula_|i2s_intf_|lrclk_r~_Duplicate_2feeder, spectrum, 1 instance = comp, \ula_|i2s_intf_|lrclk_r~_Duplicate_2 , ula_|i2s_intf_|lrclk_r~_Duplicate_2, spectrum, 1 instance = comp, \ula_|i2s_intf_|lrclk_r~0 , ula_|i2s_intf_|lrclk_r~0, spectrum, 1 instance = comp, \ula_|i2s_intf_|lrclk_r , ula_|i2s_intf_|lrclk_r, spectrum, 1 instance = comp, \ula_|i2s_intf_|lrclk_r~_Duplicate_1 , ula_|i2s_intf_|lrclk_r~_Duplicate_1, spectrum, 1 instance = comp, \ula_|i2s_intf_|bitcount[0]~5 , ula_|i2s_intf_|bitcount[0]~5, spectrum, 1 +instance = comp, \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder , ula_|i2s_intf_|bclk_r~_Duplicate_1feeder, spectrum, 1 instance = comp, \ula_|i2s_intf_|bclk_r~_Duplicate_1 , ula_|i2s_intf_|bclk_r~_Duplicate_1, spectrum, 1 instance = comp, \ula_|i2s_intf_|bitcount[4]~15 , ula_|i2s_intf_|bitcount[4]~15, spectrum, 1 instance = comp, \ula_|i2s_intf_|bitcount[0] , ula_|i2s_intf_|bitcount[0], spectrum, 1 @@ -3007,9 +2994,12 @@ instance = comp, \ula_|i2s_intf_|bitcount[2]~9 , ula_|i2s_intf_|bitcount[2]~9, s instance = comp, \ula_|i2s_intf_|bitcount[2] , ula_|i2s_intf_|bitcount[2], spectrum, 1 instance = comp, \ula_|i2s_intf_|bitcount[3]~11 , ula_|i2s_intf_|bitcount[3]~11, spectrum, 1 instance = comp, \ula_|i2s_intf_|bitcount[3] , ula_|i2s_intf_|bitcount[3], spectrum, 1 -instance = comp, \ula_|i2s_intf_|LessThan0~0 , ula_|i2s_intf_|LessThan0~0, spectrum, 1 instance = comp, \ula_|i2s_intf_|bitcount[4]~13 , ula_|i2s_intf_|bitcount[4]~13, spectrum, 1 instance = comp, \ula_|i2s_intf_|bitcount[4] , ula_|i2s_intf_|bitcount[4], spectrum, 1 +instance = comp, \ula_|i2s_intf_|LessThan0~0 , ula_|i2s_intf_|LessThan0~0, spectrum, 1 +instance = comp, \ula_|i2s_intf_|shiftreg[4]~1 , ula_|i2s_intf_|shiftreg[4]~1, spectrum, 1 +instance = comp, \ula_|i2s_intf_|Add2~18 , ula_|i2s_intf_|Add2~18, spectrum, 1 +instance = comp, \ula_|i2s_intf_|bdivider[0] , ula_|i2s_intf_|bdivider[0], spectrum, 1 instance = comp, \ula_|i2s_intf_|Add2~7 , ula_|i2s_intf_|Add2~7, spectrum, 1 instance = comp, \ula_|i2s_intf_|Add2~8 , ula_|i2s_intf_|Add2~8, spectrum, 1 instance = comp, \ula_|i2s_intf_|Add2~20 , ula_|i2s_intf_|Add2~20, spectrum, 1 @@ -3024,17 +3014,13 @@ instance = comp, \ula_|i2s_intf_|Add2~14 , ula_|i2s_intf_|Add2~14, spectrum, 1 instance = comp, \ula_|i2s_intf_|Add2~16 , ula_|i2s_intf_|Add2~16, spectrum, 1 instance = comp, \ula_|i2s_intf_|bdivider[4] , ula_|i2s_intf_|bdivider[4], spectrum, 1 instance = comp, \ula_|i2s_intf_|Equal1~0 , ula_|i2s_intf_|Equal1~0, spectrum, 1 -instance = comp, \ula_|i2s_intf_|shiftreg[4]~1 , ula_|i2s_intf_|shiftreg[4]~1, spectrum, 1 -instance = comp, \ula_|i2s_intf_|Add2~18 , ula_|i2s_intf_|Add2~18, spectrum, 1 -instance = comp, \ula_|i2s_intf_|bdivider[0] , ula_|i2s_intf_|bdivider[0], spectrum, 1 instance = comp, \ula_|i2s_intf_|Equal1~1 , ula_|i2s_intf_|Equal1~1, spectrum, 1 instance = comp, \ula_|i2s_intf_|bclk_r~0 , ula_|i2s_intf_|bclk_r~0, spectrum, 1 instance = comp, \ula_|i2s_intf_|bclk_r~1 , ula_|i2s_intf_|bclk_r~1, spectrum, 1 instance = comp, \ula_|i2s_intf_|bclk_r , ula_|i2s_intf_|bclk_r, spectrum, 1 -instance = comp, \ula_|pcm_outl[13]~feeder , ula_|pcm_outl[13]~feeder, spectrum, 1 instance = comp, \ula_|always0~2 , ula_|always0~2, spectrum, 1 instance = comp, \ula_|always0~3 , ula_|always0~3, spectrum, 1 -instance = comp, \ula_|pcm_outl[13] , ula_|pcm_outl[13], spectrum, 1 +instance = comp, \ula_|pcm_outl[14] , ula_|pcm_outl[14], spectrum, 1 instance = comp, \ula_|i2s_intf_|shiftreg[0]~19 , ula_|i2s_intf_|shiftreg[0]~19, spectrum, 1 instance = comp, \AUD_ADCDAT~input , AUD_ADCDAT~input, spectrum, 1 instance = comp, \ula_|i2s_intf_|shiftreg[0]~20 , ula_|i2s_intf_|shiftreg[0]~20, spectrum, 1 @@ -3064,45 +3050,40 @@ instance = comp, \ula_|i2s_intf_|shiftreg~8 , ula_|i2s_intf_|shiftreg~8, spectru instance = comp, \ula_|i2s_intf_|shiftreg[11] , ula_|i2s_intf_|shiftreg[11], spectrum, 1 instance = comp, \ula_|i2s_intf_|shiftreg~7 , ula_|i2s_intf_|shiftreg~7, spectrum, 1 instance = comp, \ula_|i2s_intf_|shiftreg[12] , ula_|i2s_intf_|shiftreg[12], spectrum, 1 -instance = comp, \ula_|i2s_intf_|PCM_INR[14]~0 , ula_|i2s_intf_|PCM_INR[14]~0, spectrum, 1 -instance = comp, \ula_|i2s_intf_|PCM_INR[14] , ula_|i2s_intf_|PCM_INR[14], spectrum, 1 instance = comp, \ula_|i2s_intf_|PCM_INL[14]~0 , ula_|i2s_intf_|PCM_INL[14]~0, spectrum, 1 instance = comp, \ula_|i2s_intf_|PCM_INL[14] , ula_|i2s_intf_|PCM_INL[14], spectrum, 1 +instance = comp, \ula_|i2s_intf_|PCM_INR[14]~0 , ula_|i2s_intf_|PCM_INR[14]~0, spectrum, 1 +instance = comp, \ula_|i2s_intf_|PCM_INR[14] , ula_|i2s_intf_|PCM_INR[14], spectrum, 1 instance = comp, \ula_|pcm_outr~0 , ula_|pcm_outr~0, spectrum, 1 instance = comp, \ula_|pcm_outl[12] , ula_|pcm_outl[12], spectrum, 1 instance = comp, \ula_|i2s_intf_|shiftreg~6 , ula_|i2s_intf_|shiftreg~6, spectrum, 1 instance = comp, \ula_|i2s_intf_|shiftreg[13] , ula_|i2s_intf_|shiftreg[13], spectrum, 1 +instance = comp, \ula_|pcm_outl[13] , ula_|pcm_outl[13], spectrum, 1 instance = comp, \ula_|i2s_intf_|shiftreg~5 , ula_|i2s_intf_|shiftreg~5, spectrum, 1 instance = comp, \ula_|i2s_intf_|shiftreg[14] , ula_|i2s_intf_|shiftreg[14], spectrum, 1 -instance = comp, \ula_|pcm_outl[14] , ula_|pcm_outl[14], spectrum, 1 instance = comp, \ula_|i2s_intf_|shiftreg~4 , ula_|i2s_intf_|shiftreg~4, spectrum, 1 instance = comp, \ula_|i2s_intf_|shiftreg[15] , ula_|i2s_intf_|shiftreg[15], spectrum, 1 instance = comp, \ula_|i2s_intf_|shiftreg~3 , ula_|i2s_intf_|shiftreg~3, spectrum, 1 instance = comp, \ula_|i2s_intf_|shiftreg[16] , ula_|i2s_intf_|shiftreg[16], spectrum, 1 instance = comp, \ula_|i2s_intf_|shiftreg~0 , ula_|i2s_intf_|shiftreg~0, spectrum, 1 instance = comp, \ula_|i2s_intf_|shiftreg[17] , ula_|i2s_intf_|shiftreg[17], spectrum, 1 -instance = comp, \ula_|video_|LessThan2~0 , ula_|video_|LessThan2~0, spectrum, 1 +instance = comp, \ula_|border[1]~feeder , ula_|border[1]~feeder, spectrum, 1 +instance = comp, \ula_|border[1] , ula_|border[1], spectrum, 1 +instance = comp, \ula_|video_|LessThan4~0 , ula_|video_|LessThan4~0, spectrum, 1 +instance = comp, \ula_|video_|screen_en~0 , ula_|video_|screen_en~0, spectrum, 1 instance = comp, \ula_|video_|LessThan6~0 , ula_|video_|LessThan6~0, spectrum, 1 +instance = comp, \ula_|video_|LessThan6~1 , ula_|video_|LessThan6~1, spectrum, 1 +instance = comp, \ula_|video_|screen_en~1 , ula_|video_|screen_en~1, spectrum, 1 +instance = comp, \ula_|video_|LessThan2~0 , ula_|video_|LessThan2~0, spectrum, 1 instance = comp, \ula_|video_|LessThan2~1 , ula_|video_|LessThan2~1, spectrum, 1 instance = comp, \ula_|video_|LessThan3~0 , ula_|video_|LessThan3~0, spectrum, 1 instance = comp, \ula_|video_|LessThan0~0 , ula_|video_|LessThan0~0, spectrum, 1 instance = comp, \ula_|video_|disp_enable~0 , ula_|video_|disp_enable~0, spectrum, 1 instance = comp, \ula_|video_|disp_enable~1 , ula_|video_|disp_enable~1, spectrum, 1 -instance = comp, \ula_|border[1] , ula_|border[1], spectrum, 1 -instance = comp, \ula_|video_|LessThan6~1 , ula_|video_|LessThan6~1, spectrum, 1 -instance = comp, \ula_|video_|LessThan4~0 , ula_|video_|LessThan4~0, spectrum, 1 -instance = comp, \ula_|video_|screen_en~0 , ula_|video_|screen_en~0, spectrum, 1 -instance = comp, \ula_|video_|screen_en~1 , ula_|video_|screen_en~1, spectrum, 1 -instance = comp, \ula_|video_|attr_prefetch[1]~feeder , ula_|video_|attr_prefetch[1]~feeder, spectrum, 1 -instance = comp, \ula_|video_|Decoder0~1 , ula_|video_|Decoder0~1, spectrum, 1 -instance = comp, \ula_|video_|attr_prefetch[1] , ula_|video_|attr_prefetch[1], spectrum, 1 -instance = comp, \ula_|video_|Decoder0~0 , ula_|video_|Decoder0~0, spectrum, 1 -instance = comp, \ula_|video_|attr[1] , ula_|video_|attr[1], spectrum, 1 -instance = comp, \ula_|video_|attr_prefetch[4]~feeder , ula_|video_|attr_prefetch[4]~feeder, spectrum, 1 -instance = comp, \ula_|video_|attr_prefetch[4] , ula_|video_|attr_prefetch[4], spectrum, 1 -instance = comp, \ula_|video_|attr[4] , ula_|video_|attr[4], spectrum, 1 instance = comp, \ula_|video_|attr_prefetch[7]~feeder , ula_|video_|attr_prefetch[7]~feeder, spectrum, 1 +instance = comp, \ula_|video_|Decoder0~1 , ula_|video_|Decoder0~1, spectrum, 1 instance = comp, \ula_|video_|attr_prefetch[7] , ula_|video_|attr_prefetch[7], spectrum, 1 +instance = comp, \ula_|video_|Decoder0~0 , ula_|video_|Decoder0~0, spectrum, 1 instance = comp, \ula_|video_|attr[7] , ula_|video_|attr[7], spectrum, 1 instance = comp, \ula_|video_|frame[0]~12 , ula_|video_|frame[0]~12, spectrum, 1 instance = comp, \ula_|video_|frame[0] , ula_|video_|frame[0], spectrum, 1 @@ -3113,12 +3094,12 @@ instance = comp, \ula_|video_|frame[2] , ula_|video_|frame[2], spectrum, 1 instance = comp, \ula_|video_|frame[3]~8 , ula_|video_|frame[3]~8, spectrum, 1 instance = comp, \ula_|video_|frame[3] , ula_|video_|frame[3], spectrum, 1 instance = comp, \ula_|video_|frame[4]~10 , ula_|video_|frame[4]~10, spectrum, 1 +instance = comp, \ula_|video_|frame[4]~feeder , ula_|video_|frame[4]~feeder, spectrum, 1 instance = comp, \ula_|video_|frame[4] , ula_|video_|frame[4], spectrum, 1 instance = comp, \ula_|video_|inverted , ula_|video_|inverted, spectrum, 1 instance = comp, \ula_|video_|bits_prefetch[6]~feeder , ula_|video_|bits_prefetch[6]~feeder, spectrum, 1 instance = comp, \ula_|video_|Decoder0~2 , ula_|video_|Decoder0~2, spectrum, 1 instance = comp, \ula_|video_|bits_prefetch[6] , ula_|video_|bits_prefetch[6], spectrum, 1 -instance = comp, \ula_|video_|bits[6]~feeder , ula_|video_|bits[6]~feeder, spectrum, 1 instance = comp, \ula_|video_|bits[6] , ula_|video_|bits[6], spectrum, 1 instance = comp, \ula_|video_|bits_prefetch[4]~feeder , ula_|video_|bits_prefetch[4]~feeder, spectrum, 1 instance = comp, \ula_|video_|bits_prefetch[4] , ula_|video_|bits_prefetch[4], spectrum, 1 @@ -3149,6 +3130,12 @@ instance = comp, \ula_|video_|bits[3] , ula_|video_|bits[3], spectrum, 1 instance = comp, \ula_|video_|Mux0~2 , ula_|video_|Mux0~2, spectrum, 1 instance = comp, \ula_|video_|Mux0~3 , ula_|video_|Mux0~3, spectrum, 1 instance = comp, \ula_|video_|cindex[1]~0 , ula_|video_|cindex[1]~0, spectrum, 1 +instance = comp, \ula_|video_|attr_prefetch[4]~feeder , ula_|video_|attr_prefetch[4]~feeder, spectrum, 1 +instance = comp, \ula_|video_|attr_prefetch[4] , ula_|video_|attr_prefetch[4], spectrum, 1 +instance = comp, \ula_|video_|attr[4] , ula_|video_|attr[4], spectrum, 1 +instance = comp, \ula_|video_|attr_prefetch[1]~feeder , ula_|video_|attr_prefetch[1]~feeder, spectrum, 1 +instance = comp, \ula_|video_|attr_prefetch[1] , ula_|video_|attr_prefetch[1], spectrum, 1 +instance = comp, \ula_|video_|attr[1] , ula_|video_|attr[1], spectrum, 1 instance = comp, \ula_|video_|cindex[1]~1 , ula_|video_|cindex[1]~1, spectrum, 1 instance = comp, \ula_|video_|VGA_R[0]~0 , ula_|video_|VGA_R[0]~0, spectrum, 1 instance = comp, \ula_|video_|attr_prefetch[6]~feeder , ula_|video_|attr_prefetch[6]~feeder, spectrum, 1 @@ -3157,12 +3144,12 @@ instance = comp, \ula_|video_|attr[6] , ula_|video_|attr[6], spectrum, 1 instance = comp, \ula_|video_|VGA_B[1]~0 , ula_|video_|VGA_B[1]~0, spectrum, 1 instance = comp, \ula_|video_|VGA_R[1]~1 , ula_|video_|VGA_R[1]~1, spectrum, 1 instance = comp, \ula_|border[2] , ula_|border[2], spectrum, 1 -instance = comp, \ula_|video_|attr_prefetch[2]~feeder , ula_|video_|attr_prefetch[2]~feeder, spectrum, 1 -instance = comp, \ula_|video_|attr_prefetch[2] , ula_|video_|attr_prefetch[2], spectrum, 1 -instance = comp, \ula_|video_|attr[2] , ula_|video_|attr[2], spectrum, 1 instance = comp, \ula_|video_|attr_prefetch[5]~feeder , ula_|video_|attr_prefetch[5]~feeder, spectrum, 1 instance = comp, \ula_|video_|attr_prefetch[5] , ula_|video_|attr_prefetch[5], spectrum, 1 instance = comp, \ula_|video_|attr[5] , ula_|video_|attr[5], spectrum, 1 +instance = comp, \ula_|video_|attr_prefetch[2]~feeder , ula_|video_|attr_prefetch[2]~feeder, spectrum, 1 +instance = comp, \ula_|video_|attr_prefetch[2] , ula_|video_|attr_prefetch[2], spectrum, 1 +instance = comp, \ula_|video_|attr[2] , ula_|video_|attr[2], spectrum, 1 instance = comp, \ula_|video_|cindex[2]~2 , ula_|video_|cindex[2]~2, spectrum, 1 instance = comp, \ula_|video_|VGA_G[0]~0 , ula_|video_|VGA_G[0]~0, spectrum, 1 instance = comp, \ula_|video_|VGA_G[1]~1 , ula_|video_|VGA_G[1]~1, spectrum, 1 diff --git a/simulation/modelsim/spectrum_v.sdo b/simulation/modelsim/spectrum_v.sdo index 8f29861..299023c 100644 --- a/simulation/modelsim/spectrum_v.sdo +++ b/simulation/modelsim/spectrum_v.sdo @@ -29,7 +29,7 @@ (DELAYFILE (SDFVERSION "2.1") (DESIGN "spectrum") - (DATE "04/01/2022 18:55:53") + (DATE "04/02/2022 15:53:45") (VENDOR "Altera") (PROGRAM "Quartus II 32-bit") (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition") @@ -41,8 +41,8 @@ (INSTANCE GPIO_1\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (2109:2109:2109) (2123:2123:2123)) - (PORT oe (1638:1638:1638) (1708:1708:1708)) + (PORT i (1830:1830:1830) (1899:1899:1899)) + (PORT oe (665:665:665) (729:729:729)) (IOPATH i o (2455:2455:2455) (2378:2378:2378)) (IOPATH oe o (2462:2462:2462) (2342:2342:2342)) ) @@ -53,8 +53,8 @@ (INSTANCE GPIO_1\[1\]\~output) (DELAY (ABSOLUTE - (PORT i (2133:2133:2133) (2174:2174:2174)) - (PORT oe (1897:1897:1897) (1931:1931:1931)) + (PORT i (1501:1501:1501) (1544:1544:1544)) + (PORT oe (2628:2628:2628) (2678:2678:2678)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -65,8 +65,8 @@ (INSTANCE GPIO_1\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (1984:1984:1984) (2083:2083:2083)) - (PORT oe (1897:1897:1897) (1931:1931:1931)) + (PORT i (1614:1614:1614) (1670:1670:1670)) + (PORT oe (2628:2628:2628) (2678:2678:2678)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -77,8 +77,8 @@ (INSTANCE GPIO_1\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (2218:2218:2218) (2284:2284:2284)) - (PORT oe (2147:2147:2147) (2236:2236:2236)) + (PORT i (1332:1332:1332) (1382:1382:1382)) + (PORT oe (2433:2433:2433) (2486:2486:2486)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -89,8 +89,8 @@ (INSTANCE GPIO_1\[4\]\~output) (DELAY (ABSOLUTE - (PORT i (2271:2271:2271) (2432:2432:2432)) - (PORT oe (2147:2147:2147) (2236:2236:2236)) + (PORT i (1331:1331:1331) (1379:1379:1379)) + (PORT oe (2433:2433:2433) (2486:2486:2486)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -101,8 +101,8 @@ (INSTANCE GPIO_1\[5\]\~output) (DELAY (ABSOLUTE - (PORT i (1973:1973:1973) (2011:2011:2011)) - (PORT oe (1910:1910:1910) (2005:2005:2005)) + (PORT i (1438:1438:1438) (1484:1484:1484)) + (PORT oe (2229:2229:2229) (2285:2285:2285)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -113,8 +113,8 @@ (INSTANCE GPIO_1\[6\]\~output) (DELAY (ABSOLUTE - (PORT i (1640:1640:1640) (1716:1716:1716)) - (PORT oe (1910:1910:1910) (2005:2005:2005)) + (PORT i (1192:1192:1192) (1274:1274:1274)) + (PORT oe (2229:2229:2229) (2285:2285:2285)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -125,8 +125,8 @@ (INSTANCE GPIO_1\[7\]\~output) (DELAY (ABSOLUTE - (PORT i (1960:1960:1960) (2148:2148:2148)) - (PORT oe (1910:1910:1910) (2005:2005:2005)) + (PORT i (907:907:907) (989:989:989)) + (PORT oe (2229:2229:2229) (2285:2285:2285)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -137,8 +137,8 @@ (INSTANCE GPIO_1\[8\]\~output) (DELAY (ABSOLUTE - (PORT i (976:976:976) (1064:1064:1064)) - (PORT oe (2161:2161:2161) (2266:2266:2266)) + (PORT i (1163:1163:1163) (1233:1233:1233)) + (PORT oe (1969:1969:1969) (2023:2023:2023)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -149,8 +149,8 @@ (INSTANCE GPIO_1\[9\]\~output) (DELAY (ABSOLUTE - (PORT i (1717:1717:1717) (1803:1803:1803)) - (PORT oe (2161:2161:2161) (2266:2266:2266)) + (PORT i (1181:1181:1181) (1259:1259:1259)) + (PORT oe (1969:1969:1969) (2023:2023:2023)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -161,8 +161,8 @@ (INSTANCE GPIO_1\[10\]\~output) (DELAY (ABSOLUTE - (PORT i (1939:1939:1939) (1996:1996:1996)) - (PORT oe (2404:2404:2404) (2537:2537:2537)) + (PORT i (1369:1369:1369) (1442:1442:1442)) + (PORT oe (2324:2324:2324) (2420:2420:2420)) (IOPATH i o (4557:4557:4557) (4190:4190:4190)) (IOPATH oe o (4578:4578:4578) (4159:4159:4159)) ) @@ -173,8 +173,8 @@ (INSTANCE GPIO_1\[11\]\~output) (DELAY (ABSOLUTE - (PORT i (1417:1417:1417) (1462:1462:1462)) - (PORT oe (2161:2161:2161) (2266:2266:2266)) + (PORT i (915:915:915) (998:998:998)) + (PORT oe (1969:1969:1969) (2023:2023:2023)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -185,8 +185,8 @@ (INSTANCE GPIO_1\[12\]\~output) (DELAY (ABSOLUTE - (PORT i (2181:2181:2181) (2209:2209:2209)) - (PORT oe (1700:1700:1700) (1736:1736:1736)) + (PORT i (1937:1937:1937) (2028:2028:2028)) + (PORT oe (2850:2850:2850) (2883:2883:2883)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -197,8 +197,8 @@ (INSTANCE GPIO_1\[13\]\~output) (DELAY (ABSOLUTE - (PORT i (2231:2231:2231) (2361:2361:2361)) - (PORT oe (2404:2404:2404) (2537:2537:2537)) + (PORT i (904:904:904) (971:971:971)) + (PORT oe (2324:2324:2324) (2420:2420:2420)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -209,8 +209,8 @@ (INSTANCE GPIO_1\[14\]\~output) (DELAY (ABSOLUTE - (PORT i (1625:1625:1625) (1715:1715:1715)) - (PORT oe (2140:2140:2140) (2250:2250:2250)) + (PORT i (1461:1461:1461) (1510:1510:1510)) + (PORT oe (2460:2460:2460) (2506:2506:2506)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -221,8 +221,8 @@ (INSTANCE GPIO_1\[15\]\~output) (DELAY (ABSOLUTE - (PORT i (1724:1724:1724) (1854:1854:1854)) - (PORT oe (1916:1916:1916) (1948:1948:1948)) + (PORT i (1184:1184:1184) (1288:1288:1288)) + (PORT oe (2584:2584:2584) (2639:2639:2639)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -233,8 +233,8 @@ (INSTANCE GPIO_1\[16\]\~output) (DELAY (ABSOLUTE - (PORT i (1202:1202:1202) (1265:1265:1265)) - (PORT oe (2441:2441:2441) (2523:2523:2523)) + (PORT i (1221:1221:1221) (1285:1285:1285)) + (PORT oe (2434:2434:2434) (2522:2522:2522)) (IOPATH i o (2582:2582:2582) (2502:2502:2502)) (IOPATH oe o (2585:2585:2585) (2463:2463:2463)) ) @@ -245,8 +245,8 @@ (INSTANCE GPIO_1\[17\]\~output) (DELAY (ABSOLUTE - (PORT i (1216:1216:1216) (1287:1287:1287)) - (PORT oe (2442:2442:2442) (2524:2524:2524)) + (PORT i (1157:1157:1157) (1182:1182:1182)) + (PORT oe (2435:2435:2435) (2523:2523:2523)) (IOPATH i o (2582:2582:2582) (2502:2502:2502)) (IOPATH oe o (2585:2585:2585) (2463:2463:2463)) ) @@ -257,8 +257,8 @@ (INSTANCE GPIO_1\[18\]\~output) (DELAY (ABSOLUTE - (PORT i (1118:1118:1118) (1163:1163:1163)) - (PORT oe (2137:2137:2137) (2196:2196:2196)) + (PORT i (1420:1420:1420) (1450:1450:1450)) + (PORT oe (2131:2131:2131) (2196:2196:2196)) (IOPATH i o (2582:2582:2582) (2502:2502:2502)) (IOPATH oe o (2585:2585:2585) (2463:2463:2463)) ) @@ -269,8 +269,8 @@ (INSTANCE GPIO_1\[19\]\~output) (DELAY (ABSOLUTE - (PORT i (1161:1161:1161) (1237:1237:1237)) - (PORT oe (2441:2441:2441) (2523:2523:2523)) + (PORT i (1387:1387:1387) (1430:1430:1430)) + (PORT oe (2434:2434:2434) (2522:2522:2522)) (IOPATH i o (2582:2582:2582) (2502:2502:2502)) (IOPATH oe o (2585:2585:2585) (2463:2463:2463)) ) @@ -281,8 +281,8 @@ (INSTANCE GPIO_1\[20\]\~output) (DELAY (ABSOLUTE - (PORT i (1455:1455:1455) (1530:1530:1530)) - (PORT oe (2096:2096:2096) (2158:2158:2158)) + (PORT i (1197:1197:1197) (1228:1228:1228)) + (PORT oe (2099:2099:2099) (2154:2154:2154)) (IOPATH i o (2455:2455:2455) (2378:2378:2378)) (IOPATH oe o (2462:2462:2462) (2342:2342:2342)) ) @@ -293,8 +293,8 @@ (INSTANCE GPIO_1\[21\]\~output) (DELAY (ABSOLUTE - (PORT i (1343:1343:1343) (1352:1352:1352)) - (PORT oe (2136:2136:2136) (2195:2195:2195)) + (PORT i (1419:1419:1419) (1480:1480:1480)) + (PORT oe (2130:2130:2130) (2195:2195:2195)) (IOPATH i o (2582:2582:2582) (2502:2502:2502)) (IOPATH oe o (2585:2585:2585) (2463:2463:2463)) ) @@ -305,8 +305,8 @@ (INSTANCE GPIO_1\[22\]\~output) (DELAY (ABSOLUTE - (PORT i (1213:1213:1213) (1275:1275:1275)) - (PORT oe (2035:2035:2035) (2069:2069:2069)) + (PORT i (1428:1428:1428) (1471:1471:1471)) + (PORT oe (2028:2028:2028) (2068:2068:2068)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -317,8 +317,8 @@ (INSTANCE GPIO_1\[23\]\~output) (DELAY (ABSOLUTE - (PORT i (1131:1131:1131) (1146:1146:1146)) - (PORT oe (2405:2405:2405) (2466:2466:2466)) + (PORT i (1285:1285:1285) (1395:1395:1395)) + (PORT oe (2403:2403:2403) (2480:2480:2480)) (IOPATH i o (2582:2582:2582) (2502:2502:2502)) (IOPATH oe o (2585:2585:2585) (2463:2463:2463)) ) @@ -329,8 +329,8 @@ (INSTANCE GPIO_1\[27\]\~output) (DELAY (ABSOLUTE - (PORT i (1412:1412:1412) (1417:1417:1417)) - (PORT oe (1643:1643:1643) (1693:1693:1693)) + (PORT i (2150:2150:2150) (2203:2203:2203)) + (PORT oe (1277:1277:1277) (1408:1408:1408)) (IOPATH i o (2378:2378:2378) (2455:2455:2455)) (IOPATH oe o (2462:2462:2462) (2342:2342:2342)) ) @@ -341,8 +341,8 @@ (INSTANCE GPIO_1\[28\]\~output) (DELAY (ABSOLUTE - (PORT i (1794:1794:1794) (1688:1688:1688)) - (PORT oe (1916:1916:1916) (1948:1948:1948)) + (PORT i (1506:1506:1506) (1516:1516:1516)) + (PORT oe (2584:2584:2584) (2639:2639:2639)) (IOPATH i o (2445:2445:2445) (2535:2535:2535)) (IOPATH oe o (2558:2558:2558) (2425:2425:2425)) ) @@ -353,8 +353,8 @@ (INSTANCE GPIO_1\[29\]\~output) (DELAY (ABSOLUTE - (PORT i (1533:1533:1533) (1531:1531:1531)) - (PORT oe (1352:1352:1352) (1405:1405:1405)) + (PORT i (1652:1652:1652) (1676:1676:1676)) + (PORT oe (968:968:968) (1077:1077:1077)) (IOPATH i o (2502:2502:2502) (2582:2582:2582)) (IOPATH oe o (2585:2585:2585) (2463:2463:2463)) ) @@ -365,8 +365,8 @@ (INSTANCE GPIO_1\[30\]\~output) (DELAY (ABSOLUTE - (PORT i (1050:1050:1050) (1062:1062:1062)) - (PORT oe (1327:1327:1327) (1369:1369:1369)) + (PORT i (1756:1756:1756) (1738:1738:1738)) + (PORT oe (676:676:676) (749:749:749)) (IOPATH i o (2582:2582:2582) (2502:2502:2502)) (IOPATH oe o (2585:2585:2585) (2463:2463:2463)) ) @@ -377,7 +377,7 @@ (INSTANCE LED\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (1615:1615:1615) (1516:1516:1516)) + (PORT i (1626:1626:1626) (1525:1525:1525)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -397,7 +397,7 @@ (INSTANCE LED\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (1304:1304:1304) (1340:1340:1340)) + (PORT i (1385:1385:1385) (1448:1448:1448)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -452,7 +452,7 @@ (INSTANCE VGA_R\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (1164:1164:1164) (1204:1204:1204)) + (PORT i (1370:1370:1370) (1408:1408:1408)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -462,7 +462,7 @@ (INSTANCE VGA_R\[1\]\~output) (DELAY (ABSOLUTE - (PORT i (1073:1073:1073) (1104:1104:1104)) + (PORT i (1164:1164:1164) (1210:1210:1210)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -472,7 +472,7 @@ (INSTANCE VGA_R\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (774:774:774) (751:751:751)) + (PORT i (512:512:512) (509:509:509)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -482,7 +482,7 @@ (INSTANCE VGA_R\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (986:986:986) (968:968:968)) + (PORT i (1031:1031:1031) (1025:1025:1025)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -492,7 +492,7 @@ (INSTANCE VGA_G\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (972:972:972) (958:958:958)) + (PORT i (789:789:789) (778:778:778)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -502,7 +502,7 @@ (INSTANCE VGA_G\[1\]\~output) (DELAY (ABSOLUTE - (PORT i (721:721:721) (699:699:699)) + (PORT i (777:777:777) (765:765:765)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -512,7 +512,7 @@ (INSTANCE VGA_G\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (843:843:843) (812:812:812)) + (PORT i (1036:1036:1036) (1027:1027:1027)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -522,7 +522,7 @@ (INSTANCE VGA_G\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (843:843:843) (812:812:812)) + (PORT i (1012:1012:1012) (1005:1005:1005)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -532,7 +532,7 @@ (INSTANCE VGA_B\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (717:717:717) (702:702:702)) + (PORT i (779:779:779) (760:760:760)) (IOPATH i o (4557:4557:4557) (4190:4190:4190)) ) ) @@ -542,7 +542,7 @@ (INSTANCE VGA_B\[1\]\~output) (DELAY (ABSOLUTE - (PORT i (692:692:692) (667:667:667)) + (PORT i (725:725:725) (712:712:712)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -552,7 +552,7 @@ (INSTANCE VGA_B\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (952:952:952) (940:940:940)) + (PORT i (984:984:984) (966:966:966)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -562,7 +562,7 @@ (INSTANCE VGA_B\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (1378:1378:1378) (1350:1350:1350)) + (PORT i (1080:1080:1080) (1107:1107:1107)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -590,7 +590,7 @@ (INSTANCE GPIO_1\[25\]\~output) (DELAY (ABSOLUTE - (PORT i (2048:2048:2048) (1957:1957:1957)) + (PORT i (2290:2290:2290) (2263:2263:2263)) (IOPATH i o (2445:2445:2445) (2535:2535:2535)) ) ) @@ -600,7 +600,7 @@ (INSTANCE GPIO_1\[26\]\~output) (DELAY (ABSOLUTE - (PORT i (1307:1307:1307) (1281:1281:1281)) + (PORT i (1745:1745:1745) (1754:1754:1754)) (IOPATH i o (4127:4127:4127) (4477:4477:4477)) ) ) @@ -610,7 +610,7 @@ (INSTANCE GPIO_1\[31\]\~output) (DELAY (ABSOLUTE - (PORT i (927:927:927) (923:923:923)) + (PORT i (1445:1445:1445) (1426:1426:1426)) (IOPATH i o (2582:2582:2582) (2502:2502:2502)) ) ) @@ -620,7 +620,7 @@ (INSTANCE buzzer_out\~output) (DELAY (ABSOLUTE - (PORT i (1348:1348:1348) (1373:1373:1373)) + (PORT i (2280:2280:2280) (2408:2408:2408)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -707,8 +707,8 @@ (INSTANCE ula_\|clocks_\|clk_cpu\~0) (DELAY (ABSOLUTE - (PORT datab (245:245:245) (328:328:328)) - (PORT datad (552:552:552) (573:573:573)) + (PORT datab (243:243:243) (326:326:326)) + (PORT datad (551:551:551) (574:574:574)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -734,35 +734,33 @@ (INSTANCE ula_\|clocks_\|clk_cpu\~clkctrl) (DELAY (ABSOLUTE - (PORT inclk[0] (716:716:716) (747:747:747)) + (PORT inclk[0] (720:720:720) (751:751:751)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|DFFE_M1_ff\~0) + (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_15) (DELAY (ABSOLUTE - (PORT dataa (1122:1122:1122) (1158:1158:1158)) - (PORT datad (1110:1110:1110) (1159:1159:1159)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|ena_M) - (DELAY - (ABSOLUTE - (PORT datac (1094:1094:1094) (1132:1132:1132)) - (PORT datad (1106:1106:1106) (1160:1160:1160)) + (PORT datab (1159:1159:1159) (1227:1227:1227)) + (PORT datac (621:621:621) (692:692:692)) + (PORT datad (895:895:895) (972:972:972)) + (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_12\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (604:604:604) (661:661:661)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_io_ibuf") (INSTANCE KEY\[1\]\~input) @@ -777,9 +775,9 @@ (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_9) (DELAY (ABSOLUTE - (PORT dataa (351:351:351) (490:490:490)) - (PORT datad (1994:1994:1994) (2109:2109:2109)) - (IOPATH dataa combout (304:304:304) (308:308:308)) + (PORT datac (409:409:409) (478:478:478)) + (PORT datad (2505:2505:2505) (2666:2666:2666)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -789,9 +787,9 @@ (INSTANCE z80_\|interrupts_\|nmi_armed) (DELAY (ABSOLUTE - (PORT clk (1476:1476:1476) (1490:1490:1490)) + (PORT clk (1744:1744:1744) (1760:1760:1760)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1325:1325:1325) (1320:1320:1320)) + (PORT clrn (766:766:766) (782:782:782)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -805,47 +803,52 @@ (INSTANCE z80_\|interrupts_\|in_nmi_ALTERA_SYNTHESIZED\~feeder) (DELAY (ABSOLUTE - (PORT datad (790:790:790) (826:826:826)) + (PORT datad (354:354:354) (411:411:411)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_eval_cond\~0) + (INSTANCE z80_\|sequencer_\|DFFE_M2_ff\~0) (DELAY (ABSOLUTE - (PORT datac (243:243:243) (323:323:323)) - (PORT datad (252:252:252) (325:325:325)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (429:429:429) (510:510:510)) + (PORT datab (1159:1159:1159) (1227:1227:1227)) + (PORT datad (893:893:893) (972:972:972)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~4) + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_M2_ff) (DELAY (ABSOLUTE - (PORT dataa (2418:2418:2418) (2567:2567:2567)) - (PORT datab (2411:2411:2411) (2541:2541:2541)) - (PORT datad (1577:1577:1577) (1737:1737:1737)) - (IOPATH dataa combout (301:301:301) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1558:1558:1558) (1539:1539:1539)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|sequencer_\|DFFE_M3_ff\~0) (DELAY (ABSOLUTE - (PORT dataa (1115:1115:1115) (1160:1160:1160)) - (PORT datab (408:408:408) (481:481:481)) - (PORT datad (1111:1111:1111) (1161:1161:1161)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (300:300:300) (311:311:311)) + (PORT dataa (268:268:268) (355:355:355)) + (PORT datab (1162:1162:1162) (1228:1228:1228)) + (PORT datad (896:896:896) (972:972:972)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -856,9 +859,9 @@ (INSTANCE z80_\|sequencer_\|DFFE_M3_ff) (DELAY (ABSOLUTE - (PORT clk (1540:1540:1540) (1556:1556:1556)) + (PORT clk (1514:1514:1514) (1528:1528:1528)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1596:1596:1596) (1571:1571:1571)) + (PORT clrn (1558:1558:1558) (1539:1539:1539)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -867,30 +870,16 @@ (HOLD d (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1355:1355:1355) (1381:1381:1381)) - (PORT datab (1537:1537:1537) (1647:1647:1647)) - (PORT datac (1348:1348:1348) (1441:1441:1441)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|sequencer_\|DFFE_M4_ff\~0) (DELAY (ABSOLUTE - (PORT dataa (1130:1130:1130) (1178:1178:1178)) - (PORT datab (413:413:413) (488:488:488)) - (PORT datad (1104:1104:1104) (1156:1156:1156)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (300:300:300) (311:311:311)) + (PORT dataa (291:291:291) (391:391:391)) + (PORT datab (1158:1158:1158) (1234:1234:1234)) + (PORT datad (894:894:894) (977:977:977)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -901,9 +890,9 @@ (INSTANCE z80_\|sequencer_\|DFFE_M4_ff) (DELAY (ABSOLUTE - (PORT clk (1540:1540:1540) (1556:1556:1556)) + (PORT clk (1514:1514:1514) (1528:1528:1528)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1596:1596:1596) (1571:1571:1571)) + (PORT clrn (1558:1558:1558) (1539:1539:1539)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -914,12 +903,55 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal32\~0) + (INSTANCE z80_\|sequencer_\|M5\~0) (DELAY (ABSOLUTE - (PORT datab (393:393:393) (466:466:466)) - (PORT datad (667:667:667) (742:742:742)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (PORT dataa (267:267:267) (354:354:354)) + (PORT datab (1163:1163:1163) (1235:1235:1235)) + (PORT datad (896:896:896) (975:975:975)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|M5) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1558:1558:1558) (1539:1539:1539)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~5) + (DELAY + (ABSOLUTE + (PORT datab (1182:1182:1182) (1321:1321:1321)) + (PORT datac (960:960:960) (1034:1034:1034)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~22) + (DELAY + (ABSOLUTE + (PORT dataa (1277:1277:1277) (1334:1334:1334)) + (PORT datad (1753:1753:1753) (1821:1821:1821)) + (IOPATH dataa combout (304:304:304) (308:308:308)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -929,48 +961,8 @@ (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_11) (DELAY (ABSOLUTE - (PORT datab (2598:2598:2598) (2742:2742:2742)) - (PORT datad (1607:1607:1607) (1729:1729:1729)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|table_xx\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1365:1365:1365) (1484:1484:1484)) - (PORT datad (1197:1197:1197) (1317:1317:1317)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal1\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1675:1675:1675) (1712:1712:1712)) - (PORT datab (945:945:945) (983:983:983)) - (PORT datac (2134:2134:2134) (2287:2287:2287)) - (PORT datad (1162:1162:1162) (1232:1232:1232)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal2\~0) - (DELAY - (ABSOLUTE - (PORT datac (1459:1459:1459) (1537:1537:1537)) - (PORT datad (2262:2262:2262) (2332:2332:2332)) + (PORT datac (1678:1678:1678) (1762:1762:1762)) + (PORT datad (2068:2068:2068) (2236:2236:2236)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -978,452 +970,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal36\~0) + (INSTANCE z80_\|execute_\|ctl_ir_we\~4) (DELAY (ABSOLUTE - (PORT dataa (1246:1246:1246) (1343:1343:1343)) - (PORT datab (1671:1671:1671) (1786:1786:1786)) - (PORT datac (906:906:906) (959:959:959)) - (PORT datad (943:943:943) (998:998:998)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_tbl_cb_set) - (DELAY - (ABSOLUTE - (PORT dataa (1739:1739:1739) (1786:1786:1786)) - (PORT datab (1426:1426:1426) (1455:1455:1455)) - (PORT datac (846:846:846) (882:882:882)) - (PORT datad (789:789:789) (792:792:792)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_tbl_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1224:1224:1224) (1329:1329:1329)) - (PORT datab (2644:2644:2644) (2764:2764:2764)) - (PORT datac (844:844:844) (879:879:879)) - (PORT datad (972:972:972) (1035:1035:1035)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|DFFE_instCB) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1549:1549:1549)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1588:1588:1588) (1563:1563:1563)) - (PORT ena (790:790:790) (783:783:783)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal52\~0) - (DELAY - (ABSOLUTE - (PORT dataa (711:711:711) (808:808:808)) - (PORT datab (1233:1233:1233) (1347:1347:1347)) - (PORT datac (988:988:988) (1067:1067:1067)) - (PORT datad (1323:1323:1323) (1441:1441:1441)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal2\~1) - (DELAY - (ABSOLUTE - (PORT dataa (2337:2337:2337) (2490:2490:2490)) - (PORT datab (1667:1667:1667) (1786:1786:1786)) - (PORT datac (905:905:905) (957:957:957)) - (PORT datad (672:672:672) (720:720:720)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_tbl_ed_set) - (DELAY - (ABSOLUTE - (PORT dataa (1761:1761:1761) (1838:1838:1838)) - (PORT datab (839:839:839) (854:854:854)) - (PORT datac (1396:1396:1396) (1420:1420:1420)) - (PORT datad (2042:2042:2042) (2106:2106:2106)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|DFFE_instED) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1549:1549:1549)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1588:1588:1588) (1563:1563:1563)) - (PORT ena (790:790:790) (783:783:783)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal13\~0) - (DELAY - (ABSOLUTE - (PORT dataa (714:714:714) (810:810:810)) - (PORT datac (981:981:981) (1058:1058:1058)) - (PORT datad (1323:1323:1323) (1434:1434:1434)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal33\~0) - (DELAY - (ABSOLUTE - (PORT dataa (2169:2169:2169) (2327:2327:2327)) - (PORT datac (1460:1460:1460) (1537:1537:1537)) - (PORT datad (2263:2263:2263) (2329:2329:2329)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_im_we) - (DELAY - (ABSOLUTE - (PORT dataa (610:610:610) (636:636:636)) - (PORT datab (1050:1050:1050) (1169:1169:1169)) - (PORT datac (1337:1337:1337) (1469:1469:1469)) - (PORT datad (915:915:915) (959:959:959)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal49\~0) - (DELAY - (ABSOLUTE - (PORT datab (997:997:997) (1105:1105:1105)) - (PORT datac (656:656:656) (719:719:719)) - (PORT datad (1244:1244:1244) (1328:1328:1328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal33\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1410:1410:1410) (1499:1499:1499)) - (PORT datab (1489:1489:1489) (1614:1614:1614)) - (PORT datac (1433:1433:1433) (1524:1524:1524)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal6\~0) - (DELAY - (ABSOLUTE - (PORT dataa (711:711:711) (809:809:809)) - (PORT datab (1233:1233:1233) (1347:1347:1347)) - (PORT datac (989:989:989) (1067:1067:1067)) - (PORT datad (1323:1323:1323) (1441:1441:1441)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1232:1232:1232) (1301:1301:1301)) - (PORT datab (1273:1273:1273) (1368:1368:1368)) - (PORT datad (711:711:711) (773:773:773)) + (PORT dataa (1200:1200:1200) (1290:1290:1290)) + (PORT datad (1121:1121:1121) (1183:1183:1183)) (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal12\~0) - (DELAY - (ABSOLUTE - (PORT dataa (2639:2639:2639) (2814:2814:2814)) - (PORT datab (899:899:899) (934:934:934)) - (PORT datac (1110:1110:1110) (1167:1167:1167)) - (PORT datad (1150:1150:1150) (1194:1194:1194)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~8) - (DELAY - (ABSOLUTE - (PORT dataa (933:933:933) (1033:1033:1033)) - (PORT datab (1561:1561:1561) (1662:1662:1662)) - (PORT datac (1411:1411:1411) (1476:1476:1476)) - (PORT datad (201:201:201) (238:238:238)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|nM1_int\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1116:1116:1116) (1239:1239:1239)) - (PORT datad (2109:2109:2109) (2254:2254:2254)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1086:1086:1086) (1149:1149:1149)) - (PORT datab (1113:1113:1113) (1123:1123:1123)) - (PORT datac (333:333:333) (359:359:359)) - (PORT datad (689:689:689) (743:743:743)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal3\~0) - (DELAY - (ABSOLUTE - (PORT datac (1439:1439:1439) (1545:1545:1545)) - (PORT datad (1464:1464:1464) (1551:1551:1551)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1247:1247:1247) (1335:1335:1335)) - (PORT datab (1669:1669:1669) (1782:1782:1782)) - (PORT datac (1700:1700:1700) (1785:1785:1785)) - (PORT datad (944:944:944) (1001:1001:1001)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~7) - (DELAY - (ABSOLUTE - (PORT datac (1974:1974:1974) (2154:2154:2154)) - (PORT datad (1235:1235:1235) (1306:1306:1306)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1939:1939:1939) (2060:2060:2060)) - (PORT datac (2560:2560:2560) (2661:2661:2661)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~4) - (DELAY - (ABSOLUTE - (PORT dataa (891:891:891) (937:937:937)) - (PORT datab (1029:1029:1029) (1093:1093:1093)) - (PORT datac (849:849:849) (913:913:913)) - (PORT datad (929:929:929) (973:973:973)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal40\~1) - (DELAY - (ABSOLUTE - (PORT dataa (918:918:918) (941:941:941)) - (PORT datab (898:898:898) (917:917:917)) - (PORT datac (919:919:919) (1011:1011:1011)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal39\~0) - (DELAY - (ABSOLUTE - (PORT dataa (916:916:916) (940:940:940)) - (PORT datab (901:901:901) (913:913:913)) - (PORT datac (920:920:920) (1009:1009:1009)) - (PORT datad (1166:1166:1166) (1216:1216:1216)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~1) - (DELAY - (ABSOLUTE - (PORT dataa (856:856:856) (896:896:896)) - (PORT datac (977:977:977) (1048:1048:1048)) - (PORT datad (1170:1170:1170) (1184:1184:1184)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal13\~1) - (DELAY - (ABSOLUTE - (PORT dataa (2169:2169:2169) (2322:2322:2322)) - (PORT datac (1461:1461:1461) (1534:1534:1534)) - (PORT datad (2261:2261:2261) (2326:2326:2326)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal13\~2) - (DELAY - (ABSOLUTE - (PORT dataa (877:877:877) (972:972:972)) - (PORT datab (1721:1721:1721) (1812:1812:1812)) - (PORT datac (1148:1148:1148) (1153:1153:1153)) - (PORT datad (650:650:650) (690:690:690)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal3\~2) - (DELAY - (ABSOLUTE - (PORT dataa (944:944:944) (975:975:975)) - (PORT datab (2317:2317:2317) (2471:2471:2471)) - (PORT datac (1702:1702:1702) (1788:1788:1788)) - (PORT datad (669:669:669) (716:716:716)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -1433,10 +985,10 @@ (INSTANCE z80_\|execute_\|ctl_state_iy_set\~2) (DELAY (ABSOLUTE - (PORT dataa (1211:1211:1211) (1331:1331:1331)) - (PORT datab (2075:2075:2075) (2256:2256:2256)) - (PORT datac (862:862:862) (881:881:881)) - (PORT datad (1458:1458:1458) (1561:1561:1561)) + (PORT dataa (1727:1727:1727) (1809:1809:1809)) + (PORT datab (2112:2112:2112) (2282:2282:2282)) + (PORT datac (713:713:713) (798:798:798)) + (PORT datad (383:383:383) (415:415:415)) (IOPATH dataa combout (304:304:304) (299:299:299)) (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -1446,220 +998,34 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~8) + (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_16) (DELAY (ABSOLUTE - (PORT datab (1418:1418:1418) (1489:1489:1489)) - (PORT datac (1562:1562:1562) (1631:1631:1631)) + (PORT datab (1159:1159:1159) (1233:1233:1233)) + (PORT datac (237:237:237) (315:315:315)) + (PORT datad (895:895:895) (975:975:975)) (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~6) - (DELAY - (ABSOLUTE - (PORT datac (1595:1595:1595) (1686:1686:1686)) - (PORT datad (1897:1897:1897) (2018:2018:2018)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~9) - (DELAY - (ABSOLUTE - (PORT datac (1033:1033:1033) (1103:1103:1103)) - (PORT datad (985:985:985) (1046:1046:1046)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1003:1003:1003) (1060:1060:1060)) - (PORT datab (989:989:989) (1052:1052:1052)) - (PORT datac (903:903:903) (941:941:941)) - (PORT datad (2055:2055:2055) (2108:2108:2108)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~10) - (DELAY - (ABSOLUTE - (PORT dataa (424:424:424) (461:461:461)) - (PORT datab (1160:1160:1160) (1195:1195:1195)) - (PORT datac (623:623:623) (685:685:685)) - (PORT datad (1108:1108:1108) (1138:1138:1138)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal44\~0) - (DELAY - (ABSOLUTE - (PORT dataa (711:711:711) (810:810:810)) - (PORT datab (1238:1238:1238) (1352:1352:1352)) - (PORT datac (982:982:982) (1059:1059:1059)) - (PORT datad (1323:1323:1323) (1435:1435:1435)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~16) - (DELAY - (ABSOLUTE - (PORT dataa (976:976:976) (1074:1074:1074)) - (PORT datab (1336:1336:1336) (1358:1358:1358)) - (PORT datac (931:931:931) (1016:1016:1016)) - (PORT datad (1108:1108:1108) (1132:1132:1132)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~13) - (DELAY - (ABSOLUTE - (PORT datab (836:836:836) (897:897:897)) - (PORT datac (619:619:619) (671:671:671)) - (PORT datad (213:213:213) (245:245:245)) - (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal50\~0) + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_T5_ff) (DELAY (ABSOLUTE - (PORT datab (998:998:998) (1107:1107:1107)) - (PORT datac (656:656:656) (717:717:717)) - (PORT datad (1193:1193:1193) (1255:1255:1255)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1558:1558:1558) (1539:1539:1539)) + (PORT ena (1441:1441:1441) (1437:1437:1437)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal33\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1233:1233:1233) (1300:1300:1300)) - (PORT datab (1273:1273:1273) (1368:1368:1368)) - (PORT datad (711:711:711) (773:773:773)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~17) - (DELAY - (ABSOLUTE - (PORT dataa (967:967:967) (1063:1063:1063)) - (PORT datab (1112:1112:1112) (1107:1107:1107)) - (PORT datac (928:928:928) (1011:1011:1011)) - (PORT datad (1085:1085:1085) (1082:1082:1082)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~5) - (DELAY - (ABSOLUTE - (PORT datac (1607:1607:1607) (1722:1722:1722)) - (PORT datad (984:984:984) (1047:1047:1047)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~14) - (DELAY - (ABSOLUTE - (PORT dataa (612:612:612) (674:674:674)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (199:199:199) (237:237:237)) - (PORT datad (1103:1103:1103) (1112:1112:1112)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1593:1593:1593) (1671:1671:1671)) - (PORT datab (1420:1420:1420) (1492:1492:1492)) - (PORT datac (372:372:372) (399:399:399)) - (PORT datad (1786:1786:1786) (1904:1904:1904)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ixy_d\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1089:1089:1089) (1107:1107:1107)) - (PORT datab (236:236:236) (282:282:282)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) ) ) (CELL @@ -1667,12 +1033,12 @@ (INSTANCE z80_\|execute_\|ctl_state_ixiy_we\~2) (DELAY (ABSOLUTE - (PORT dataa (1302:1302:1302) (1399:1399:1399)) - (PORT datab (1499:1499:1499) (1604:1604:1604)) - (PORT datac (1460:1460:1460) (1551:1551:1551)) - (PORT datad (2054:2054:2054) (2222:2222:2222)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (PORT dataa (856:856:856) (896:896:896)) + (PORT datab (2112:2112:2112) (2285:2285:2285)) + (PORT datac (1687:1687:1687) (1773:1773:1773)) + (PORT datad (896:896:896) (1011:1011:1011)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -1683,9 +1049,9 @@ (INSTANCE z80_\|decode_state_\|DFFE_instIY1) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1547:1547:1547)) + (PORT clk (1525:1525:1525) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1586:1586:1586) (1563:1563:1563)) + (PORT clrn (1559:1559:1559) (1540:1540:1540)) (PORT ena (820:820:820) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) @@ -1698,89 +1064,25 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~5) + (INSTANCE z80_\|decode_state_\|use_ixiy) (DELAY (ABSOLUTE - (PORT dataa (887:887:887) (960:960:960)) - (PORT datac (643:643:643) (708:708:708)) - (PORT datad (1365:1365:1365) (1481:1481:1481)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT datab (504:504:504) (586:586:586)) + (PORT datad (443:443:443) (528:528:528)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~14) + (INSTANCE z80_\|execute_\|ixy_d\~4) (DELAY (ABSOLUTE - (PORT dataa (1259:1259:1259) (1368:1368:1368)) - (PORT datab (463:463:463) (524:524:524)) - (PORT datac (1699:1699:1699) (1754:1754:1754)) - (PORT datad (267:267:267) (321:321:321)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~2) - (DELAY - (ABSOLUTE - (PORT dataa (709:709:709) (805:805:805)) - (PORT datab (1019:1019:1019) (1101:1101:1101)) - (PORT datac (676:676:676) (769:769:769)) - (PORT datad (1322:1322:1322) (1435:1435:1435)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1624:1624:1624) (1717:1717:1717)) - (PORT datab (1533:1533:1533) (1585:1585:1585)) - (PORT datac (1709:1709:1709) (1830:1830:1830)) - (PORT datad (1494:1494:1494) (1626:1626:1626)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1299:1299:1299) (1388:1388:1388)) - (PORT datab (1243:1243:1243) (1323:1323:1323)) - (PORT datac (1034:1034:1034) (1082:1082:1082)) - (PORT datad (1678:1678:1678) (1738:1738:1738)) - (IOPATH dataa combout (356:356:356) (368:368:368)) + (PORT datab (1017:1017:1017) (1082:1082:1082)) + (PORT datac (1488:1488:1488) (1607:1607:1607)) + (PORT datad (946:946:946) (1006:1006:1006)) (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~26) - (DELAY - (ABSOLUTE - (PORT datac (685:685:685) (734:734:734)) - (PORT datad (1734:1734:1734) (1851:1851:1851)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -1788,191 +1090,39 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~27) + (INSTANCE z80_\|execute_\|ixy_d\~11) (DELAY (ABSOLUTE - (PORT dataa (648:648:648) (666:666:666)) - (PORT datac (1102:1102:1102) (1151:1151:1151)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~7) - (DELAY - (ABSOLUTE - (PORT dataa (206:206:206) (252:252:252)) - (PORT datab (244:244:244) (291:291:291)) - (PORT datac (669:669:669) (688:688:688)) - (PORT datad (2054:2054:2054) (2107:2107:2107)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1002:1002:1002) (1065:1065:1065)) - (PORT datab (1219:1219:1219) (1281:1281:1281)) - (PORT datac (688:688:688) (740:740:740)) - (PORT datad (179:179:179) (206:206:206)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~18) - (DELAY - (ABSOLUTE - (PORT dataa (931:931:931) (1031:1031:1031)) - (PORT datab (1557:1557:1557) (1661:1661:1661)) - (PORT datac (1407:1407:1407) (1474:1474:1474)) - (PORT datad (203:203:203) (238:238:238)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal55\~0) - (DELAY - (ABSOLUTE - (PORT dataa (288:288:288) (386:386:386)) - (PORT datac (902:902:902) (964:964:964)) - (PORT datad (928:928:928) (984:984:984)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|comb\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1762:1762:1762) (1872:1872:1872)) - (PORT datac (1146:1146:1146) (1226:1226:1226)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~15) - (DELAY - (ABSOLUTE - (PORT dataa (622:622:622) (664:664:664)) - (PORT datab (1178:1178:1178) (1215:1215:1215)) - (PORT datac (934:934:934) (1030:1030:1030)) - (PORT datad (181:181:181) (212:212:212)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~17) - (DELAY - (ABSOLUTE - (PORT dataa (668:668:668) (723:723:723)) - (PORT datab (653:653:653) (674:674:674)) - (PORT datac (936:936:936) (1036:1036:1036)) - (PORT datad (898:898:898) (943:943:943)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~5) - (DELAY - (ABSOLUTE - (PORT dataa (941:941:941) (958:958:958)) - (PORT datab (1199:1199:1199) (1222:1222:1222)) - (PORT datac (1813:1813:1813) (1890:1890:1890)) - (PORT datad (871:871:871) (910:910:910)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1687:1687:1687) (1746:1746:1746)) - (PORT datac (1659:1659:1659) (1737:1737:1737)) - (PORT datad (1165:1165:1165) (1209:1209:1209)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal9\~0) - (DELAY - (ABSOLUTE - (PORT datac (826:826:826) (880:880:880)) - (PORT datad (900:900:900) (971:971:971)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1685:1685:1685) (1750:1750:1750)) - (PORT datab (1691:1691:1691) (1776:1776:1776)) - (PORT datac (1479:1479:1479) (1575:1575:1575)) - (PORT datad (1244:1244:1244) (1311:1311:1311)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1465:1465:1465) (1537:1537:1537)) - (PORT datab (1233:1233:1233) (1318:1318:1318)) - (PORT datac (1424:1424:1424) (1514:1514:1514)) - (PORT datad (825:825:825) (838:838:838)) + (PORT dataa (1502:1502:1502) (1609:1609:1609)) + (PORT datab (2670:2670:2670) (2813:2813:2813)) + (PORT datac (1298:1298:1298) (1393:1393:1393)) + (PORT datad (858:858:858) (885:885:885)) (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1714:1714:1714) (1799:1799:1799)) + (PORT datac (2408:2408:2408) (2538:2538:2538)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~7) + (DELAY + (ABSOLUTE + (PORT datac (1804:1804:1804) (1893:1893:1893)) + (PORT datad (956:956:956) (1070:1070:1070)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -1980,28 +1130,52 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~20) + (INSTANCE z80_\|execute_\|ixy_d\~6) (DELAY (ABSOLUTE - (PORT dataa (891:891:891) (914:914:914)) - (PORT datab (1241:1241:1241) (1279:1279:1279)) - (PORT datac (1377:1377:1377) (1384:1384:1384)) - (PORT datad (1263:1263:1263) (1301:1301:1301)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (634:634:634) (716:716:716)) + (PORT datac (685:685:685) (777:777:777)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~8) + (DELAY + (ABSOLUTE + (PORT datab (269:269:269) (353:353:353)) + (PORT datad (258:258:258) (340:340:340)) + (IOPATH datab combout (306:306:306) (311:311:311)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal12\~1) + (INSTANCE z80_\|execute_\|ixy_d\~12) (DELAY (ABSOLUTE - (PORT dataa (619:619:619) (657:657:657)) - (PORT datab (963:963:963) (1059:1059:1059)) - (PORT datad (1154:1154:1154) (1176:1176:1176)) + (PORT dataa (2032:2032:2032) (2090:2090:2090)) + (PORT datab (950:950:950) (1005:1005:1005)) + (PORT datac (1675:1675:1675) (1738:1738:1738)) + (PORT datad (1255:1255:1255) (1334:1334:1334)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal33\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1691:1691:1691) (1740:1740:1740)) + (PORT datab (271:271:271) (356:356:356)) + (PORT datad (380:380:380) (449:449:449)) (IOPATH dataa combout (304:304:304) (299:299:299)) (IOPATH datab combout (336:336:336) (332:332:332)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -2010,75 +1184,55 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal9\~1) + (INSTANCE z80_\|pla_decode_\|Equal33\~1) (DELAY (ABSOLUTE - (PORT dataa (1565:1565:1565) (1659:1659:1659)) - (PORT datab (982:982:982) (1039:1039:1039)) - (PORT datac (1634:1634:1634) (1749:1749:1749)) - (PORT datad (1216:1216:1216) (1293:1293:1293)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (1993:1993:1993) (2188:2188:2188)) + (PORT datab (1212:1212:1212) (1313:1313:1313)) + (PORT datad (1274:1274:1274) (1364:1364:1364)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal25\~0) + (INSTANCE z80_\|pla_decode_\|Equal33\~2) (DELAY (ABSOLUTE - (PORT dataa (1460:1460:1460) (1559:1559:1559)) - (PORT datab (1540:1540:1540) (1676:1676:1676)) - (PORT datac (1379:1379:1379) (1439:1439:1439)) - (PORT datad (1566:1566:1566) (1596:1596:1596)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (1216:1216:1216) (1313:1313:1313)) + (PORT datab (987:987:987) (1068:1068:1068)) + (PORT datad (1628:1628:1628) (1639:1639:1639)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~21) + (INSTANCE z80_\|pla_decode_\|Equal21\~0) (DELAY (ABSOLUTE - (PORT dataa (894:894:894) (913:913:913)) - (PORT datab (1819:1819:1819) (1900:1900:1900)) - (PORT datac (867:867:867) (883:883:883)) - (PORT datad (1475:1475:1475) (1552:1552:1552)) - (IOPATH dataa combout (300:300:300) (307:307:307)) + (PORT datab (1417:1417:1417) (1524:1524:1524)) + (PORT datad (1439:1439:1439) (1527:1527:1527)) (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~6) + (INSTANCE z80_\|pla_decode_\|Equal77\~0) (DELAY (ABSOLUTE - (PORT dataa (1220:1220:1220) (1307:1307:1307)) - (PORT datac (948:948:948) (1024:1024:1024)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal19\~0) - (DELAY - (ABSOLUTE - (PORT dataa (940:940:940) (969:969:969)) - (PORT datab (936:936:936) (992:992:992)) - (PORT datac (1633:1633:1633) (1753:1753:1753)) - (PORT datad (1215:1215:1215) (1294:1294:1294)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) + (PORT dataa (1044:1044:1044) (1137:1137:1137)) + (PORT datab (996:996:996) (1103:1103:1103)) + (PORT datac (929:929:929) (1055:1055:1055)) + (PORT datad (975:975:975) (1059:1059:1059)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -2086,58 +1240,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal1\~4) + (INSTANCE z80_\|pla_decode_\|Equal77\~1) (DELAY (ABSOLUTE - (PORT datac (1720:1720:1720) (1792:1792:1792)) - (PORT datad (2039:2039:2039) (2100:2100:2100)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal29\~0) - (DELAY - (ABSOLUTE - (PORT dataa (220:220:220) (263:263:263)) - (PORT datab (1158:1158:1158) (1201:1201:1201)) - (PORT datac (1618:1618:1618) (1607:1607:1607)) - (PORT datad (1454:1454:1454) (1538:1538:1538)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal24\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1564:1564:1564) (1657:1657:1657)) - (PORT datab (978:978:978) (1038:1038:1038)) - (PORT datac (1634:1634:1634) (1759:1759:1759)) - (PORT datad (1220:1220:1220) (1302:1302:1302)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal34\~0) - (DELAY - (ABSOLUTE - (PORT dataa (2169:2169:2169) (2326:2326:2326)) - (PORT datab (948:948:948) (988:988:988)) - (PORT datac (193:193:193) (227:227:227)) - (PORT datad (416:416:416) (461:461:461)) - (IOPATH dataa combout (301:301:301) (299:299:299)) + (PORT dataa (670:670:670) (727:727:727)) + (PORT datab (658:658:658) (743:743:743)) + (PORT datac (1694:1694:1694) (1759:1759:1759)) + (PORT datad (583:583:583) (602:602:602)) + (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -2146,15 +1256,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal37\~0) + (INSTANCE z80_\|pla_decode_\|Equal1\~7) (DELAY (ABSOLUTE - (PORT dataa (445:445:445) (500:500:500)) - (PORT datab (942:942:942) (982:982:982)) - (PORT datac (2138:2138:2138) (2282:2282:2282)) - (PORT datad (1141:1141:1141) (1176:1176:1176)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) + (PORT dataa (1216:1216:1216) (1292:1292:1292)) + (PORT datab (615:615:615) (683:683:683)) + (PORT datac (570:570:570) (579:579:579)) + (PORT datad (592:592:592) (657:657:657)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -2162,15 +1272,99 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal35\~0) + (INSTANCE z80_\|pla_decode_\|Equal79\~0) (DELAY (ABSOLUTE - (PORT dataa (446:446:446) (504:504:504)) - (PORT datab (946:946:946) (982:982:982)) - (PORT datac (2134:2134:2134) (2284:2284:2284)) - (PORT datad (195:195:195) (221:221:221)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) + (PORT dataa (781:781:781) (882:882:882)) + (PORT datab (1924:1924:1924) (2018:2018:2018)) + (PORT datac (1269:1269:1269) (1341:1341:1341)) + (PORT datad (1618:1618:1618) (1697:1697:1697)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|iff1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (218:218:218) (269:269:269)) + (PORT datab (1398:1398:1398) (1441:1441:1441)) + (PORT datac (393:393:393) (457:457:457)) + (PORT datad (1231:1231:1231) (1327:1327:1327)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|DFFE_instIFF2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (216:216:216) (265:265:265)) + (PORT datab (1399:1399:1399) (1440:1440:1440)) + (PORT datad (1233:1233:1233) (1329:1329:1329)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_12) + (DELAY + (ABSOLUTE + (PORT dataa (2786:2786:2786) (2933:2933:2933)) + (PORT datab (693:693:693) (770:770:770)) + (PORT datad (888:888:888) (957:957:957)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_12\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (1082:1082:1082) (1108:1108:1108)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|interrupts_\|DFFE_instIFF2) + (DELAY + (ABSOLUTE + (PORT clk (1541:1541:1541) (1557:1557:1557)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1556:1556:1556) (1548:1548:1548)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal13\~0) + (DELAY + (ABSOLUTE + (PORT dataa (285:285:285) (382:382:382)) + (PORT datac (398:398:398) (476:476:476)) + (PORT datad (390:390:390) (455:455:455)) + (IOPATH dataa combout (303:303:303) (308:308:308)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -2181,433 +1375,10 @@ (INSTANCE z80_\|pla_decode_\|Equal38\~2) (DELAY (ABSOLUTE - (PORT dataa (1627:1627:1627) (1717:1717:1717)) - (PORT datab (1533:1533:1533) (1663:1663:1663)) - (PORT datac (1709:1709:1709) (1827:1827:1827)) - (PORT datad (1445:1445:1445) (1492:1492:1492)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1114:1114:1114) (1137:1137:1137)) - (PORT datab (1107:1107:1107) (1172:1172:1172)) - (PORT datac (580:580:580) (611:611:611)) - (PORT datad (895:895:895) (945:945:945)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~3) - (DELAY - (ABSOLUTE - (PORT dataa (867:867:867) (927:927:927)) - (PORT datab (1362:1362:1362) (1426:1426:1426)) - (PORT datac (584:584:584) (617:617:617)) - (PORT datad (583:583:583) (602:602:602)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|comb\~0) - (DELAY - (ABSOLUTE - (PORT datab (1940:1940:1940) (2011:2011:2011)) - (PORT datac (1163:1163:1163) (1222:1222:1222)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal47\~0) - (DELAY - (ABSOLUTE - (PORT dataa (450:450:450) (507:507:507)) - (PORT datab (949:949:949) (988:988:988)) - (PORT datac (2135:2135:2135) (2282:2282:2282)) - (PORT datad (364:364:364) (385:385:385)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1290:1290:1290) (1360:1360:1360)) - (PORT datab (1193:1193:1193) (1242:1242:1242)) - (PORT datac (172:172:172) (204:204:204)) - (PORT datad (1264:1264:1264) (1365:1365:1365)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~22) - (DELAY - (ABSOLUTE - (PORT dataa (659:659:659) (717:717:717)) - (PORT datab (639:639:639) (661:661:661)) - (PORT datac (180:180:180) (217:217:217)) - (PORT datad (1158:1158:1158) (1203:1203:1203)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~24) - (DELAY - (ABSOLUTE - (PORT dataa (939:939:939) (959:959:959)) - (PORT datab (231:231:231) (282:282:282)) - (PORT datac (629:629:629) (651:651:651)) - (PORT datad (649:649:649) (681:681:681)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla42M3T3_6) - (DELAY - (ABSOLUTE - (PORT dataa (1447:1447:1447) (1493:1493:1493)) - (PORT datab (1229:1229:1229) (1315:1315:1315)) - (PORT datac (680:680:680) (717:717:717)) - (PORT datad (1141:1141:1141) (1161:1161:1161)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~6) - (DELAY - (ABSOLUTE - (PORT dataa (708:708:708) (759:759:759)) - (PORT datab (1141:1141:1141) (1169:1169:1169)) - (PORT datac (1819:1819:1819) (1896:1896:1896)) - (PORT datad (588:588:588) (613:613:613)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal6\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1461:1461:1461) (1560:1560:1560)) - (PORT datab (1137:1137:1137) (1179:1179:1179)) - (PORT datac (1192:1192:1192) (1287:1287:1287)) - (PORT datad (655:655:655) (686:686:686)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1468:1468:1468) (1566:1566:1566)) - (PORT datab (683:683:683) (725:725:725)) - (PORT datac (1193:1193:1193) (1278:1278:1278)) - (PORT datad (1406:1406:1406) (1445:1445:1445)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|M5\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1125:1125:1125) (1173:1173:1173)) - (PORT datab (267:267:267) (350:350:350)) - (PORT datad (1104:1104:1104) (1160:1160:1160)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|M5) - (DELAY - (ABSOLUTE - (PORT clk (1540:1540:1540) (1556:1556:1556)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1596:1596:1596) (1571:1571:1571)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~2) - (DELAY - (ABSOLUTE - (PORT datab (1589:1589:1589) (1719:1719:1719)) - (PORT datac (2606:2606:2606) (2704:2704:2704)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~29) - (DELAY - (ABSOLUTE - (PORT dataa (629:629:629) (665:665:665)) - (PORT datab (931:931:931) (978:978:978)) - (PORT datac (1004:1004:1004) (1061:1061:1061)) - (PORT datad (662:662:662) (691:691:691)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~25) - (DELAY - (ABSOLUTE - (PORT dataa (1946:1946:1946) (2050:2050:2050)) - (PORT datab (687:687:687) (729:729:729)) - (PORT datac (658:658:658) (709:709:709)) - (PORT datad (585:585:585) (615:615:615)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1904:1904:1904) (1999:1999:1999)) - (PORT datab (898:898:898) (961:961:961)) - (PORT datac (193:193:193) (226:226:226)) - (PORT datad (187:187:187) (219:219:219)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1259:1259:1259) (1371:1371:1371)) - (PORT datab (464:464:464) (522:522:522)) - (PORT datac (1696:1696:1696) (1755:1755:1755)) - (PORT datad (268:268:268) (323:323:323)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal52\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1366:1366:1366) (1481:1481:1481)) - (PORT datab (934:934:934) (992:992:992)) - (PORT datac (958:958:958) (990:990:990)) - (PORT datad (1201:1201:1201) (1318:1318:1318)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~14) - (DELAY - (ABSOLUTE - (PORT dataa (972:972:972) (1071:1071:1071)) - (PORT datab (1335:1335:1335) (1360:1360:1360)) - (PORT datac (927:927:927) (1015:1015:1015)) - (PORT datad (1107:1107:1107) (1130:1130:1130)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~8) - (DELAY - (ABSOLUTE - (PORT dataa (636:636:636) (679:679:679)) - (PORT datab (1262:1262:1262) (1301:1301:1301)) - (PORT datac (566:566:566) (573:573:573)) - (PORT datad (1626:1626:1626) (1701:1701:1701)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal24\~0) - (DELAY - (ABSOLUTE - (PORT dataa (708:708:708) (808:808:808)) - (PORT datab (219:219:219) (258:258:258)) - (PORT datac (255:255:255) (343:343:343)) - (PORT datad (881:881:881) (941:941:941)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_pc\~0) - (DELAY - (ABSOLUTE - (PORT dataa (885:885:885) (933:933:933)) - (PORT datab (1109:1109:1109) (1175:1175:1175)) - (PORT datac (1089:1089:1089) (1121:1121:1121)) - (PORT datad (673:673:673) (713:713:713)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_pc\~1) - (DELAY - (ABSOLUTE - (PORT dataa (449:449:449) (492:492:492)) - (PORT datab (1938:1938:1938) (2051:2051:2051)) - (PORT datac (1035:1035:1035) (1084:1084:1084)) - (PORT datad (1561:1561:1561) (1612:1612:1612)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_pc\~2) - (DELAY - (ABSOLUTE - (PORT dataa (920:920:920) (1000:1000:1000)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (895:895:895) (945:945:945)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~17) - (DELAY - (ABSOLUTE - (PORT dataa (637:637:637) (683:683:683)) - (PORT datab (1196:1196:1196) (1213:1213:1213)) - (PORT datac (208:208:208) (248:248:248)) - (PORT datad (624:624:624) (642:642:642)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~6) - (DELAY - (ABSOLUTE - (PORT dataa (421:421:421) (458:458:458)) - (PORT datab (1170:1170:1170) (1201:1201:1201)) - (PORT datac (620:620:620) (684:684:684)) - (PORT datad (1113:1113:1113) (1142:1142:1142)) + (PORT dataa (1561:1561:1561) (1693:1693:1693)) + (PORT datab (1494:1494:1494) (1548:1548:1548)) + (PORT datac (1378:1378:1378) (1556:1556:1556)) + (PORT datad (1509:1509:1509) (1635:1635:1635)) (IOPATH dataa combout (300:300:300) (308:308:308)) (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -2617,6010 +1388,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal11\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1626:1626:1626) (1717:1717:1717)) - (PORT datab (1533:1533:1533) (1584:1584:1584)) - (PORT datac (1703:1703:1703) (1827:1827:1827)) - (PORT datad (1490:1490:1490) (1625:1625:1625)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal10\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1624:1624:1624) (1719:1719:1719)) - (PORT datab (1534:1534:1534) (1581:1581:1581)) - (PORT datac (1711:1711:1711) (1826:1826:1826)) - (PORT datad (1494:1494:1494) (1620:1620:1620)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1688:1688:1688) (1727:1727:1727)) - (PORT datab (1470:1470:1470) (1564:1564:1564)) - (PORT datac (2563:2563:2563) (2660:2660:2660)) - (PORT datad (1901:1901:1901) (2013:2013:2013)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~4) - (DELAY - (ABSOLUTE - (PORT dataa (637:637:637) (682:682:682)) - (PORT datab (1262:1262:1262) (1302:1302:1302)) - (PORT datac (1116:1116:1116) (1135:1135:1135)) - (PORT datad (553:553:553) (571:571:571)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1260:1260:1260) (1370:1370:1370)) - (PORT datab (464:464:464) (521:521:521)) - (PORT datac (1697:1697:1697) (1755:1755:1755)) - (PORT datad (267:267:267) (323:323:323)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1107:1107:1107) (1153:1153:1153)) - (PORT datab (1145:1145:1145) (1184:1184:1184)) - (PORT datac (548:548:548) (563:563:563)) - (PORT datad (609:609:609) (634:634:634)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~9) - (DELAY - (ABSOLUTE - (PORT dataa (291:291:291) (358:358:358)) - (PORT datab (465:465:465) (519:519:519)) - (PORT datac (191:191:191) (223:223:223)) - (PORT datad (1368:1368:1368) (1479:1479:1479)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal46\~0) - (DELAY - (ABSOLUTE - (PORT dataa (286:286:286) (382:382:382)) - (PORT datab (952:952:952) (1018:1018:1018)) - (PORT datac (903:903:903) (963:963:963)) - (PORT datad (1192:1192:1192) (1312:1312:1312)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1252:1252:1252) (1367:1367:1367)) - (PORT datab (866:866:866) (891:891:891)) - (PORT datac (1704:1704:1704) (1755:1755:1755)) - (PORT datad (263:263:263) (316:316:316)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~17) - (DELAY - (ABSOLUTE - (PORT dataa (2111:2111:2111) (2254:2254:2254)) - (PORT datab (2048:2048:2048) (2161:2161:2161)) - (PORT datac (986:986:986) (1043:1043:1043)) - (PORT datad (1210:1210:1210) (1253:1253:1253)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1380:1380:1380) (1424:1424:1424)) - (PORT datab (1059:1059:1059) (1143:1143:1143)) - (PORT datac (754:754:754) (762:762:762)) - (PORT datad (1235:1235:1235) (1269:1269:1269)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (982:982:982) (1061:1061:1061)) - (PORT datac (1148:1148:1148) (1203:1203:1203)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (296:296:296) (369:369:369)) - (PORT datab (465:465:465) (518:518:518)) - (PORT datac (1197:1197:1197) (1289:1289:1289)) - (PORT datad (1363:1363:1363) (1476:1476:1476)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1126:1126:1126) (1248:1248:1248)) - (PORT datab (2197:2197:2197) (2296:2296:2296)) - (PORT datac (1334:1334:1334) (1445:1445:1445)) - (PORT datad (959:959:959) (1022:1022:1022)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1792:1792:1792) (1883:1883:1883)) - (PORT datab (1288:1288:1288) (1337:1337:1337)) - (PORT datac (1377:1377:1377) (1384:1384:1384)) - (PORT datad (883:883:883) (905:905:905)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~8) - (DELAY - (ABSOLUTE - (PORT dataa (614:614:614) (635:635:635)) - (PORT datac (550:550:550) (559:559:559)) - (PORT datad (1232:1232:1232) (1290:1290:1290)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~18) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (242:242:242)) - (PORT datab (219:219:219) (257:257:257)) - (PORT datac (172:172:172) (204:204:204)) - (PORT datad (196:196:196) (221:221:221)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~19) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (207:207:207) (249:249:249)) - (PORT datac (861:861:861) (876:876:876)) - (PORT datad (848:848:848) (889:889:889)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~16) - (DELAY - (ABSOLUTE - (PORT datac (2061:2061:2061) (2184:2184:2184)) - (PORT datad (959:959:959) (1014:1014:1014)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~36) - (DELAY - (ABSOLUTE - (PORT dataa (1615:1615:1615) (1714:1714:1714)) - (PORT datab (1532:1532:1532) (1580:1580:1580)) - (PORT datac (1706:1706:1706) (1825:1825:1825)) - (PORT datad (1489:1489:1489) (1621:1621:1621)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~9) - (DELAY - (ABSOLUTE - (PORT dataa (682:682:682) (717:717:717)) - (PORT datab (1494:1494:1494) (1553:1553:1553)) - (PORT datac (1138:1138:1138) (1205:1205:1205)) - (PORT datad (1383:1383:1383) (1432:1432:1432)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~44) - (DELAY - (ABSOLUTE - (PORT dataa (2148:2148:2148) (2325:2325:2325)) - (PORT datab (675:675:675) (746:746:746)) - (PORT datac (1715:1715:1715) (1794:1794:1794)) - (PORT datad (205:205:205) (235:235:235)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1299:1299:1299) (1399:1399:1399)) - (PORT datad (2046:2046:2046) (2211:2211:2211)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~6) - (DELAY - (ABSOLUTE - (PORT dataa (919:919:919) (999:999:999)) - (PORT datab (454:454:454) (482:482:482)) - (PORT datac (408:408:408) (448:448:448)) - (PORT datad (1564:1564:1564) (1622:1622:1622)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~7) - (DELAY - (ABSOLUTE - (PORT dataa (629:629:629) (651:651:651)) - (PORT datab (1155:1155:1155) (1200:1200:1200)) - (PORT datac (1451:1451:1451) (1502:1502:1502)) - (PORT datad (337:337:337) (358:358:358)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~7) - (DELAY - (ABSOLUTE - (PORT datac (1520:1520:1520) (1613:1613:1613)) - (PORT datad (1159:1159:1159) (1225:1225:1225)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1261:1261:1261) (1371:1371:1371)) - (PORT datab (865:865:865) (889:889:889)) - (PORT datac (1688:1688:1688) (1749:1749:1749)) - (PORT datad (267:267:267) (323:323:323)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1260:1260:1260) (1371:1371:1371)) - (PORT datab (465:465:465) (519:519:519)) - (PORT datac (1689:1689:1689) (1752:1752:1752)) - (PORT datad (268:268:268) (320:320:320)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1420:1420:1420) (1451:1451:1451)) - (PORT datab (1101:1101:1101) (1122:1122:1122)) - (PORT datac (1072:1072:1072) (1084:1084:1084)) - (PORT datad (939:939:939) (973:973:973)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla27npla34M1T1_3) - (DELAY - (ABSOLUTE - (PORT dataa (683:683:683) (719:719:719)) - (PORT datab (1167:1167:1167) (1240:1240:1240)) - (PORT datac (1455:1455:1455) (1509:1509:1509)) - (PORT datad (1468:1468:1468) (1520:1520:1520)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~8) - (DELAY - (ABSOLUTE - (PORT dataa (391:391:391) (420:420:420)) - (PORT datab (200:200:200) (239:239:239)) - (PORT datac (623:623:623) (666:666:666)) - (PORT datad (189:189:189) (220:220:220)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~9) - (DELAY - (ABSOLUTE - (PORT dataa (566:566:566) (593:593:593)) - (PORT datab (860:860:860) (886:886:886)) - (PORT datac (854:854:854) (889:889:889)) - (PORT datad (805:805:805) (822:822:822)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1150:1150:1150) (1163:1163:1163)) - (PORT datab (196:196:196) (235:235:235)) - (PORT datac (186:186:186) (228:228:228)) - (PORT datad (179:179:179) (206:206:206)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~7) - (DELAY - (ABSOLUTE - (PORT dataa (351:351:351) (483:483:483)) - (PORT datab (1218:1218:1218) (1272:1272:1272)) - (PORT datac (679:679:679) (709:709:709)) - (PORT datad (1295:1295:1295) (1387:1387:1387)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~8) - (DELAY - (ABSOLUTE - (PORT datab (2915:2915:2915) (3094:3094:3094)) - (PORT datac (2028:2028:2028) (2098:2098:2098)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla21M2T2_3) - (DELAY - (ABSOLUTE - (PORT dataa (1889:1889:1889) (1934:1934:1934)) - (PORT datab (2084:2084:2084) (2215:2215:2215)) - (PORT datac (1111:1111:1111) (1144:1144:1144)) - (PORT datad (208:208:208) (238:238:238)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_ixy_dT4_2) - (DELAY - (ABSOLUTE - (PORT datac (1234:1234:1234) (1326:1326:1326)) - (PORT datad (625:625:625) (665:665:665)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~39) - (DELAY - (ABSOLUTE - (PORT dataa (1182:1182:1182) (1232:1232:1232)) - (PORT datab (906:906:906) (961:961:961)) - (PORT datac (2032:2032:2032) (2056:2056:2056)) - (PORT datad (1479:1479:1479) (1541:1541:1541)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla26M1T4_3) - (DELAY - (ABSOLUTE - (PORT dataa (1057:1057:1057) (1151:1151:1151)) - (PORT datab (2381:2381:2381) (2493:2493:2493)) - (PORT datad (2113:2113:2113) (2257:2257:2257)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1487:1487:1487) (1536:1536:1536)) - (PORT datab (1011:1011:1011) (1078:1078:1078)) - (PORT datac (900:900:900) (921:921:921)) - (PORT datad (1172:1172:1172) (1187:1187:1187)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1450:1450:1450) (1479:1479:1479)) - (PORT datab (1137:1137:1137) (1178:1178:1178)) - (PORT datac (337:337:337) (365:365:365)) - (PORT datad (1137:1137:1137) (1159:1159:1159)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~38) - (DELAY - (ABSOLUTE - (PORT dataa (373:373:373) (412:412:412)) - (PORT datab (1088:1088:1088) (1114:1114:1114)) - (PORT datac (1575:1575:1575) (1617:1617:1617)) - (PORT datad (811:811:811) (828:828:828)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_zero) - (DELAY - (ABSOLUTE - (PORT dataa (1142:1142:1142) (1206:1206:1206)) - (PORT datab (1169:1169:1169) (1204:1204:1204)) - (PORT datac (835:835:835) (863:863:863)) - (PORT datad (800:800:800) (827:827:827)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1179:1179:1179) (1212:1212:1212)) - (PORT datab (286:286:286) (351:351:351)) - (PORT datac (253:253:253) (312:312:312)) - (PORT datad (252:252:252) (297:297:297)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~14) - (DELAY - (ABSOLUTE - (PORT datac (948:948:948) (1024:1024:1024)) - (PORT datad (2023:2023:2023) (2146:2146:2146)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (856:856:856) (897:897:897)) - (PORT datab (1012:1012:1012) (1081:1081:1081)) - (PORT datac (1223:1223:1223) (1284:1284:1284)) - (PORT datad (1171:1171:1171) (1183:1183:1183)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~1) - (DELAY - (ABSOLUTE - (PORT datab (219:219:219) (257:257:257)) - (PORT datad (194:194:194) (219:219:219)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1179:1179:1179) (1230:1230:1230)) - (PORT datab (1013:1013:1013) (1082:1082:1082)) - (PORT datac (2030:2030:2030) (2056:2056:2056)) - (PORT datad (1479:1479:1479) (1543:1543:1543)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~30) - (DELAY - (ABSOLUTE - (PORT dataa (1303:1303:1303) (1377:1377:1377)) - (PORT datab (1170:1170:1170) (1231:1231:1231)) - (PORT datac (840:840:840) (887:887:887)) - (PORT datad (1322:1322:1322) (1434:1434:1434)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~29) - (DELAY - (ABSOLUTE - (PORT dataa (918:918:918) (984:984:984)) - (PORT datab (941:941:941) (1009:1009:1009)) - (PORT datac (1210:1210:1210) (1289:1289:1289)) - (PORT datad (658:658:658) (688:688:688)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~31) - (DELAY - (ABSOLUTE - (PORT dataa (1353:1353:1353) (1482:1482:1482)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (382:382:382) (410:410:410)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal69\~0) - (DELAY - (ABSOLUTE - (PORT dataa (873:873:873) (968:968:968)) - (PORT datab (1718:1718:1718) (1808:1808:1808)) - (PORT datac (1144:1144:1144) (1148:1148:1148)) - (PORT datad (653:653:653) (693:693:693)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal1\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1201:1201:1201) (1290:1290:1290)) - (PORT datad (1198:1198:1198) (1259:1259:1259)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1009:1009:1009) (1044:1044:1044)) - (PORT datab (2023:2023:2023) (2060:2060:2060)) - (PORT datac (1148:1148:1148) (1153:1153:1153)) - (PORT datad (650:650:650) (690:690:690)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1758:1758:1758) (1876:1876:1876)) - (PORT datab (915:915:915) (977:977:977)) - (PORT datad (216:216:216) (242:242:242)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal56\~0) - (DELAY - (ABSOLUTE - (PORT dataa (670:670:670) (725:725:725)) - (PORT datab (1178:1178:1178) (1215:1215:1215)) - (PORT datac (934:934:934) (1029:1029:1029)) - (PORT datad (903:903:903) (950:950:950)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1467:1467:1467) (1537:1537:1537)) - (PORT datab (1228:1228:1228) (1312:1312:1312)) - (PORT datac (1432:1432:1432) (1520:1520:1520)) - (PORT datad (820:820:820) (833:833:833)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~2) - (DELAY - (ABSOLUTE - (PORT dataa (822:822:822) (845:845:845)) - (PORT datab (854:854:854) (887:887:887)) - (PORT datad (673:673:673) (693:693:693)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~16) - (DELAY - (ABSOLUTE - (PORT dataa (2011:2011:2011) (2114:2114:2114)) - (PORT datab (2111:2111:2111) (2221:2221:2221)) - (PORT datac (547:547:547) (569:569:569)) - (PORT datad (1739:1739:1739) (1782:1782:1782)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~4) - (DELAY - (ABSOLUTE - (PORT dataa (859:859:859) (882:882:882)) - (PORT datab (952:952:952) (1011:1011:1011)) - (PORT datac (178:178:178) (213:213:213)) - (PORT datad (1472:1472:1472) (1533:1533:1533)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~5) - (DELAY - (ABSOLUTE - (PORT datac (1162:1162:1162) (1174:1174:1174)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1237:1237:1237) (1303:1303:1303)) - (PORT datab (992:992:992) (1101:1101:1101)) - (PORT datac (657:657:657) (716:716:716)) - (PORT datad (1239:1239:1239) (1323:1323:1323)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~15) - (DELAY - (ABSOLUTE - (PORT datab (1082:1082:1082) (1193:1193:1193)) - (PORT datac (1465:1465:1465) (1548:1548:1548)) - (PORT datad (2348:2348:2348) (2497:2497:2497)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~8) - (DELAY - (ABSOLUTE - (PORT dataa (669:669:669) (726:726:726)) - (PORT datab (1800:1800:1800) (1830:1830:1830)) - (PORT datac (988:988:988) (1048:1048:1048)) - (PORT datad (1210:1210:1210) (1257:1257:1257)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1026:1026:1026) (1084:1084:1084)) - (PORT datab (1248:1248:1248) (1292:1292:1292)) - (PORT datac (1097:1097:1097) (1128:1128:1128)) - (PORT datad (183:183:183) (212:212:212)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~3) - (DELAY - (ABSOLUTE - (PORT dataa (942:942:942) (983:983:983)) - (PORT datab (1091:1091:1091) (1163:1163:1163)) - (PORT datac (985:985:985) (1050:1050:1050)) - (PORT datad (1157:1157:1157) (1206:1206:1206)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1013:1013:1013) (1086:1086:1086)) - (PORT datab (197:197:197) (234:234:234)) - (PORT datac (1253:1253:1253) (1320:1320:1320)) - (PORT datad (1054:1054:1054) (1123:1123:1123)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4) - (DELAY - (ABSOLUTE - (PORT datab (1514:1514:1514) (1650:1650:1650)) - (PORT datac (1504:1504:1504) (1617:1617:1617)) - (PORT datad (1306:1306:1306) (1325:1325:1325)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~10) - (DELAY - (ABSOLUTE - (PORT dataa (794:794:794) (831:831:831)) - (PORT datab (860:860:860) (870:870:870)) - (PORT datac (1242:1242:1242) (1262:1262:1262)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1415:1415:1415) (1454:1454:1454)) - (PORT datab (2084:2084:2084) (2114:2114:2114)) - (PORT datac (835:835:835) (859:859:859)) - (PORT datad (788:788:788) (798:798:798)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal48\~0) - (DELAY - (ABSOLUTE - (PORT dataa (873:873:873) (968:968:968)) - (PORT datab (1718:1718:1718) (1807:1807:1807)) - (PORT datac (1144:1144:1144) (1148:1148:1148)) - (PORT datad (654:654:654) (693:693:693)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf2_we) - (DELAY - (ABSOLUTE - (PORT dataa (922:922:922) (998:998:998)) - (PORT datab (900:900:900) (985:985:985)) - (PORT datac (966:966:966) (1015:1015:1015)) - (PORT datad (1295:1295:1295) (1365:1365:1365)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~41) - (DELAY - (ABSOLUTE - (PORT dataa (1246:1246:1246) (1336:1336:1336)) - (PORT datab (1005:1005:1005) (1056:1056:1056)) - (PORT datac (209:209:209) (248:248:248)) - (PORT datad (1195:1195:1195) (1244:1244:1244)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1847:1847:1847) (1960:1960:1960)) - (PORT datab (1294:1294:1294) (1397:1397:1397)) - (PORT datac (2030:2030:2030) (2118:2118:2118)) - (PORT datad (836:836:836) (843:843:843)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1215:1215:1215) (1251:1251:1251)) - (PORT datab (1013:1013:1013) (1076:1076:1076)) - (PORT datac (621:621:621) (659:659:659)) - (PORT datad (1176:1176:1176) (1188:1188:1188)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~19) - (DELAY - (ABSOLUTE - (PORT dataa (886:886:886) (945:945:945)) - (PORT datab (1062:1062:1062) (1128:1128:1128)) - (PORT datac (579:579:579) (602:602:602)) - (PORT datad (1089:1089:1089) (1104:1104:1104)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_iorw\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1618:1618:1618) (1711:1711:1711)) - (PORT datab (1527:1527:1527) (1658:1658:1658)) - (PORT datac (1710:1710:1710) (1825:1825:1825)) - (PORT datad (1448:1448:1448) (1496:1496:1496)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1670:1670:1670) (1753:1753:1753)) - (PORT datab (1528:1528:1528) (1617:1617:1617)) - (PORT datac (966:966:966) (1014:1014:1014)) - (PORT datad (1159:1159:1159) (1218:1218:1218)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~20) - (DELAY - (ABSOLUTE - (PORT dataa (587:587:587) (622:622:622)) - (PORT datab (923:923:923) (944:944:944)) - (PORT datac (969:969:969) (1018:1018:1018)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1638:1638:1638) (1764:1764:1764)) - (PORT datab (1075:1075:1075) (1149:1149:1149)) - (PORT datac (1806:1806:1806) (1948:1948:1948)) - (PORT datad (942:942:942) (974:974:974)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1241:1241:1241) (1294:1294:1294)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (972:972:972) (992:992:992)) - (PORT datad (902:902:902) (955:955:955)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1348:1348:1348) (1398:1398:1398)) - (PORT datab (1002:1002:1002) (1057:1057:1057)) - (PORT datac (575:575:575) (596:596:596)) - (PORT datad (637:637:637) (681:681:681)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal20\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1988:1988:1988) (2128:2128:2128)) - (PORT datab (1534:1534:1534) (1632:1632:1632)) - (PORT datac (227:227:227) (272:272:272)) - (PORT datad (1108:1108:1108) (1149:1149:1149)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal68\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1617:1617:1617) (1711:1711:1711)) - (PORT datab (1528:1528:1528) (1657:1657:1657)) - (PORT datac (1709:1709:1709) (1824:1824:1824)) - (PORT datad (1448:1448:1448) (1496:1496:1496)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~14) - (DELAY - (ABSOLUTE - (PORT dataa (922:922:922) (983:983:983)) - (PORT datab (1427:1427:1427) (1510:1510:1510)) - (PORT datac (1333:1333:1333) (1448:1448:1448)) - (PORT datad (1550:1550:1550) (1659:1659:1659)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~13) - (DELAY - (ABSOLUTE - (PORT dataa (699:699:699) (721:721:721)) - (PORT datab (1637:1637:1637) (1642:1642:1642)) - (PORT datac (1298:1298:1298) (1314:1314:1314)) - (PORT datad (1443:1443:1443) (1563:1563:1563)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1580:1580:1580) (1703:1703:1703)) - (PORT datab (1365:1365:1365) (1479:1479:1479)) - (PORT datac (1152:1152:1152) (1186:1186:1186)) - (PORT datad (832:832:832) (834:834:834)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~11) - (DELAY - (ABSOLUTE - (PORT dataa (672:672:672) (729:729:729)) - (PORT datab (995:995:995) (1057:1057:1057)) - (PORT datac (1074:1074:1074) (1196:1196:1196)) - (PORT datad (173:173:173) (197:197:197)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~11) - (DELAY - (ABSOLUTE - (PORT dataa (2265:2265:2265) (2414:2414:2414)) - (PORT datab (848:848:848) (886:886:886)) - (PORT datac (2113:2113:2113) (2221:2221:2221)) - (PORT datad (669:669:669) (694:694:694)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~10) - (DELAY - (ABSOLUTE - (PORT dataa (920:920:920) (996:996:996)) - (PORT datab (1005:1005:1005) (1060:1060:1060)) - (PORT datac (1413:1413:1413) (1487:1487:1487)) - (PORT datad (1522:1522:1522) (1622:1622:1622)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~8) - (DELAY - (ABSOLUTE - (PORT dataa (647:647:647) (684:684:684)) - (PORT datab (440:440:440) (477:477:477)) - (PORT datac (202:202:202) (238:238:238)) - (PORT datad (1428:1428:1428) (1432:1432:1432)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~9) - (DELAY - (ABSOLUTE - (PORT dataa (630:630:630) (662:662:662)) - (PORT datab (1001:1001:1001) (1053:1053:1053)) - (PORT datac (870:870:870) (914:914:914)) - (PORT datad (809:809:809) (854:854:854)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~12) - (DELAY - (ABSOLUTE - (PORT dataa (371:371:371) (392:392:392)) - (PORT datab (331:331:331) (360:360:360)) - (PORT datac (170:170:170) (202:202:202)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~11) - (DELAY - (ABSOLUTE - (PORT dataa (222:222:222) (266:266:266)) - (PORT datab (228:228:228) (271:271:271)) - (PORT datac (201:201:201) (238:238:238)) - (PORT datad (202:202:202) (231:231:231)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~12) - (DELAY - (ABSOLUTE - (PORT dataa (637:637:637) (657:657:657)) - (PORT datab (1415:1415:1415) (1491:1491:1491)) - (PORT datac (638:638:638) (658:658:658)) - (PORT datad (1624:1624:1624) (1706:1706:1706)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~6) - (DELAY - (ABSOLUTE - (PORT dataa (668:668:668) (702:702:702)) - (PORT datab (995:995:995) (1056:1056:1056)) - (PORT datac (1075:1075:1075) (1194:1194:1194)) - (PORT datad (2306:2306:2306) (2342:2342:2342)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~7) - (DELAY - (ABSOLUTE - (PORT dataa (921:921:921) (980:980:980)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (346:346:346) (371:371:371)) - (PORT datad (2307:2307:2307) (2344:2344:2344)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~4) - (DELAY - (ABSOLUTE - (PORT datab (1060:1060:1060) (1178:1178:1178)) - (PORT datac (1452:1452:1452) (1530:1530:1530)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1391:1391:1391) (1453:1453:1453)) - (PORT datab (942:942:942) (993:993:993)) - (PORT datac (1045:1045:1045) (1115:1115:1115)) - (PORT datad (1421:1421:1421) (1470:1470:1470)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (969:969:969) (1009:1009:1009)) - (PORT datab (1445:1445:1445) (1500:1500:1500)) - (PORT datac (972:972:972) (995:995:995)) - (PORT datad (196:196:196) (222:222:222)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1112:1112:1112) (1123:1123:1123)) - (PORT datab (1196:1196:1196) (1246:1246:1246)) - (PORT datac (663:663:663) (712:712:712)) - (PORT datad (879:879:879) (931:931:931)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~13) - (DELAY - (ABSOLUTE - (PORT dataa (604:604:604) (616:616:616)) - (PORT datac (573:573:573) (593:593:593)) - (PORT datad (531:531:531) (543:543:543)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~14) - (DELAY - (ABSOLUTE - (PORT dataa (248:248:248) (303:303:303)) - (PORT datab (1244:1244:1244) (1269:1269:1269)) - (PORT datac (1174:1174:1174) (1214:1214:1214)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~15) - (DELAY - (ABSOLUTE - (PORT dataa (879:879:879) (925:925:925)) - (PORT datab (852:852:852) (865:865:865)) - (PORT datac (342:342:342) (367:367:367)) - (PORT datad (195:195:195) (221:221:221)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_66_oe\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1987:1987:1987) (2132:2132:2132)) - (PORT datab (903:903:903) (955:955:955)) - (PORT datac (224:224:224) (269:269:269)) - (PORT datad (1402:1402:1402) (1466:1466:1466)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel_pla11M1T1_11) - (DELAY - (ABSOLUTE - (PORT dataa (1798:1798:1798) (1933:1933:1933)) - (PORT datab (1613:1613:1613) (1726:1726:1726)) - (PORT datad (1409:1409:1409) (1475:1475:1475)) - (IOPATH dataa combout (301:301:301) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero\~5) - (DELAY - (ABSOLUTE - (PORT dataa (2050:2050:2050) (2089:2089:2089)) - (PORT datab (946:946:946) (1023:1023:1023)) - (PORT datac (1099:1099:1099) (1158:1158:1158)) - (PORT datad (914:914:914) (1002:1002:1002)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1335:1335:1335) (1354:1354:1354)) - (PORT datab (1166:1166:1166) (1239:1239:1239)) - (PORT datac (1485:1485:1485) (1514:1514:1514)) - (PORT datad (1468:1468:1468) (1520:1520:1520)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero) - (DELAY - (ABSOLUTE - (PORT dataa (1144:1144:1144) (1189:1189:1189)) - (PORT datab (222:222:222) (269:269:269)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (836:836:836) (868:868:868)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[2\]) - (DELAY - (ABSOLUTE - (PORT datab (963:963:963) (1010:1010:1010)) - (PORT datac (601:601:601) (607:607:607)) - (PORT datad (676:676:676) (718:718:718)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|ena\~0) - (DELAY - (ABSOLUTE - (PORT datac (928:928:928) (973:973:973)) - (PORT datad (680:680:680) (720:720:720)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_high\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_lq) - (DELAY - (ABSOLUTE - (PORT dataa (1003:1003:1003) (1064:1064:1064)) - (PORT datab (717:717:717) (774:774:774)) - (PORT datac (903:903:903) (944:944:944)) - (PORT datad (1740:1740:1740) (1858:1858:1858)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1494:1494:1494) (1600:1600:1600)) - (PORT datab (1475:1475:1475) (1582:1582:1582)) - (PORT datac (1847:1847:1847) (1916:1916:1916)) - (PORT datad (402:402:402) (439:439:439)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1219:1219:1219) (1306:1306:1306)) - (PORT datac (943:943:943) (1021:1021:1021)) - (PORT datad (1208:1208:1208) (1293:1293:1293)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~21) - (DELAY - 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(1063:1063:1063)) - (PORT datab (717:717:717) (773:773:773)) - (PORT datac (901:901:901) (942:942:942)) - (PORT datad (1738:1738:1738) (1857:1857:1857)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1357:1357:1357) (1397:1397:1397)) - (PORT datab (917:917:917) (962:962:962)) - (PORT datad (619:619:619) (654:654:654)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla65npla52M1T4_4) - (DELAY - (ABSOLUTE - (PORT dataa (864:864:864) (915:915:915)) - (PORT datab (1463:1463:1463) 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z80_\|execute_\|ctl_alu_shift_oe\~22) - (DELAY - (ABSOLUTE - (PORT dataa (1436:1436:1436) (1449:1449:1449)) - (PORT datab (1436:1436:1436) (1504:1504:1504)) - (PORT datac (1048:1048:1048) (1116:1116:1116)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~23) - (DELAY - (ABSOLUTE - (PORT dataa (1814:1814:1814) (1847:1847:1847)) - (PORT datab (337:337:337) (365:365:365)) - (PORT datac (1045:1045:1045) (1115:1115:1115)) - (PORT datad (1199:1199:1199) (1246:1246:1246)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~24) - (DELAY - (ABSOLUTE - (PORT dataa (1419:1419:1419) (1450:1450:1450)) - (PORT datab (1438:1438:1438) (1497:1497:1497)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (938:938:938) (969:969:969)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~25) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (979:979:979) (1010:1010:1010)) - (PORT datac (1074:1074:1074) (1085:1085:1085)) - (PORT datad (1198:1198:1198) (1245:1245:1245)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (332:332:332)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH 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(IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~27) - (DELAY - (ABSOLUTE - (PORT dataa (632:632:632) (666:666:666)) - (PORT datab (1003:1003:1003) (1051:1051:1051)) - (PORT datac (1298:1298:1298) (1337:1337:1337)) - (PORT datad (805:805:805) (832:832:832)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~28) - (DELAY - (ABSOLUTE - (PORT dataa (638:638:638) (672:672:672)) - (PORT datac (1050:1050:1050) (1065:1065:1065)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~10) - (DELAY - (ABSOLUTE - (PORT dataa (969:969:969) (1008:1008:1008)) - (PORT datab (1439:1439:1439) (1498:1498:1498)) - (PORT datac (975:975:975) (990:990:990)) - (PORT datad (1202:1202:1202) (1250:1250:1250)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~11) - (DELAY - (ABSOLUTE - (PORT dataa (386:386:386) (415:415:415)) - (PORT datab (213:213:213) (258:258:258)) - (PORT datac (354:354:354) (387:387:387)) - (PORT datad (344:344:344) (367:367:367)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac 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(130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~0) - (DELAY - (ABSOLUTE - (PORT dataa (819:819:819) (841:841:841)) - (PORT datab (697:697:697) (728:728:728)) - (PORT datac (916:916:916) (968:968:968)) - (PORT datad (816:816:816) (839:839:839)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~1) - (DELAY - (ABSOLUTE - (PORT datab (869:869:869) (890:890:890)) - (PORT datad (810:810:810) (826:826:826)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~12) - (DELAY - (ABSOLUTE - (PORT datab (215:215:215) (259:259:259)) - (PORT datac (355:355:355) (387:387:387)) - (PORT datad (345:345:345) (368:368:368)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~47) - (DELAY - (ABSOLUTE - (PORT dataa (1639:1639:1639) (1766:1766:1766)) - (PORT datab (1825:1825:1825) (1925:1925:1925)) - (PORT datac (1804:1804:1804) (1951:1951:1951)) - (PORT datad (941:941:941) (965:965:965)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~34) - (DELAY - (ABSOLUTE - (PORT dataa (1437:1437:1437) (1451:1451:1451)) - (PORT datab (1439:1439:1439) (1497:1497:1497)) - (PORT datac (974:974:974) (995:995:995)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~35) - (DELAY - (ABSOLUTE - (PORT dataa (1814:1814:1814) (1850:1850:1850)) - (PORT datab (1003:1003:1003) (1029:1029:1029)) - (PORT datac (315:315:315) (336:336:336)) - (PORT datad (172:172:172) (198:198:198)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~36) - (DELAY - (ABSOLUTE - (PORT dataa (673:673:673) (706:706:706)) - (PORT datab (608:608:608) (621:621:621)) - (PORT datac (813:813:813) (840:840:840)) - (PORT datad (337:337:337) (356:356:356)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~43) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (242:242:242)) - (PORT datab (198:198:198) (238:238:238)) - (PORT datac (170:170:170) (204:204:204)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_lo\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1292:1292:1292) (1357:1357:1357)) - (PORT datab (986:986:986) (1070:1070:1070)) - (PORT datac (1073:1073:1073) (1153:1153:1153)) - (PORT datad (966:966:966) (1077:1077:1077)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1463:1463:1463) (1478:1478:1478)) - (PORT datab (1379:1379:1379) (1398:1398:1398)) - (PORT datac (1618:1618:1618) (1662:1662:1662)) - (PORT datad (1263:1263:1263) (1327:1327:1327)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla57M1T4_4) - (DELAY - (ABSOLUTE - (PORT dataa (1202:1202:1202) (1231:1231:1231)) - (PORT datab (1048:1048:1048) (1149:1149:1149)) - (PORT datad (1348:1348:1348) (1490:1490:1490)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_oe\~1) - (DELAY - (ABSOLUTE - (PORT dataa (681:681:681) (736:736:736)) - (PORT datab (1001:1001:1001) (1033:1033:1033)) - (PORT datac (553:553:553) (568:568:568)) - (PORT datad (222:222:222) (249:249:249)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (737:737:737) (798:798:798)) - (PORT datab (948:948:948) (1025:1025:1025)) - (PORT datac (1099:1099:1099) (1159:1159:1159)) - (PORT datad (909:909:909) (998:998:998)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1225:1225:1225) (1294:1294:1294)) - (PORT datab (224:224:224) (271:271:271)) - (PORT datac (2351:2351:2351) (2449:2449:2449)) - (PORT datad (171:171:171) (196:196:196)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - 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z80_\|execute_\|ctl_alu_sel_op2_neg\~4) - (DELAY - (ABSOLUTE - (PORT dataa (859:859:859) (894:894:894)) - (PORT datab (1197:1197:1197) (1223:1223:1223)) - (PORT datac (981:981:981) (1043:1043:1043)) - (PORT datad (972:972:972) (1036:1036:1036)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (2006:2006:2006) (2147:2147:2147)) - (PORT datab (450:450:450) (480:480:480)) - (PORT datac (1000:1000:1000) (1045:1045:1045)) - (PORT datad (900:900:900) (950:950:950)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal11\~1) - (DELAY - (ABSOLUTE - (PORT datac (1589:1589:1589) (1676:1676:1676)) - (PORT datad (1494:1494:1494) (1621:1621:1621)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla12M3T1_2) - (DELAY - (ABSOLUTE - (PORT dataa (959:959:959) (1016:1016:1016)) - (PORT datab (1194:1194:1194) (1223:1223:1223)) - (PORT datac (1942:1942:1942) (2000:2000:2000)) - (PORT datad (641:641:641) (693:693:693)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~10) - (DELAY - (ABSOLUTE - (PORT dataa (198:198:198) (241:241:241)) - (PORT datab (627:627:627) (662:662:662)) - (PORT datac (1683:1683:1683) (1789:1789:1789)) - (PORT datad (633:633:633) (651:651:651)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1500:1500:1500) (1575:1575:1575)) - (PORT datab (362:362:362) (397:397:397)) - (PORT datac (2091:2091:2091) (2220:2220:2220)) - (PORT datad (590:590:590) (607:607:607)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla77M1T1_3) - (DELAY - (ABSOLUTE - (PORT dataa (736:736:736) (800:800:800)) - (PORT datab (947:947:947) (1025:1025:1025)) - (PORT datac (1098:1098:1098) (1158:1158:1158)) - (PORT datad (911:911:911) (1001:1001:1001)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel_pla82M1T1_16) - (DELAY - (ABSOLUTE - (PORT dataa (1465:1465:1465) (1539:1539:1539)) - (PORT datab (1227:1227:1227) (1318:1318:1318)) - (PORT datac (1459:1459:1459) (1517:1517:1517)) - (PORT datad (1138:1138:1138) (1159:1159:1159)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1840:1840:1840) (1939:1939:1939)) - (PORT datab (2068:2068:2068) (2187:2187:2187)) - (PORT datac (1327:1327:1327) (1336:1336:1336)) - (PORT datad (2013:2013:2013) (2125:2125:2125)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1112:1112:1112) (1215:1215:1215)) - (PORT datab (653:653:653) (674:674:674)) - (PORT datac (1214:1214:1214) (1294:1294:1294)) - (PORT datad (596:596:596) (619:619:619)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel\[0\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1122:1122:1122) (1170:1170:1170)) - (PORT datab (841:841:841) (864:864:864)) - (PORT datad (579:579:579) (590:590:590)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~2) - (DELAY - (ABSOLUTE - (PORT datac (1753:1753:1753) (1873:1873:1873)) - (PORT datad (1571:1571:1571) (1694:1694:1694)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~25) - (DELAY - (ABSOLUTE - (PORT dataa (1025:1025:1025) (1056:1056:1056)) - (PORT datab (1039:1039:1039) (1096:1096:1096)) - (PORT datac (1052:1052:1052) (1117:1117:1117)) - (PORT datad (625:625:625) (651:651:651)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1581:1581:1581) (1726:1726:1726)) - (PORT datab (205:205:205) (247:247:247)) - (PORT datac (1053:1053:1053) (1117:1117:1117)) - (PORT datad (1795:1795:1795) (1930:1930:1930)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1219:1219:1219) (1272:1272:1272)) - (PORT datab (689:689:689) (706:706:706)) - (PORT datac (1267:1267:1267) (1395:1395:1395)) - (PORT datad (1570:1570:1570) (1720:1720:1720)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~48) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (265:265:265)) - (PORT datab (214:214:214) (259:259:259)) - (PORT datac (1265:1265:1265) (1395:1395:1395)) - (PORT datad (1573:1573:1573) (1723:1723:1723)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1230:1230:1230) (1277:1277:1277)) - (PORT datab (1647:1647:1647) (1673:1673:1673)) - (PORT datac (777:777:777) (786:786:786)) - (PORT datad (581:581:581) (600:600:600)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (635:635:635) (652:652:652)) - (PORT datab (656:656:656) (711:711:711)) - (PORT datac (680:680:680) (730:730:730)) - (PORT datad (800:800:800) (871:871:871)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1001:1001:1001) (1087:1087:1087)) - (PORT datab (1683:1683:1683) (1741:1741:1741)) - (PORT datac (1582:1582:1582) (1690:1690:1690)) - (PORT datad (964:964:964) (1004:1004:1004)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1288:1288:1288) (1342:1342:1342)) - (PORT datab (935:935:935) (949:949:949)) - (PORT datac (978:978:978) (1043:1043:1043)) - (PORT datad (1176:1176:1176) (1188:1188:1188)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~6) - (DELAY - (ABSOLUTE - (PORT dataa (355:355:355) (390:390:390)) - (PORT datab (1476:1476:1476) (1506:1506:1506)) - (PORT datac (1080:1080:1080) (1084:1084:1084)) - (PORT datad (1360:1360:1360) (1375:1375:1375)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~10) - (DELAY - (ABSOLUTE - (PORT dataa (357:357:357) (392:392:392)) - (PORT datab (238:238:238) (276:276:276)) - (PORT datac (1044:1044:1044) (1080:1080:1080)) - (PORT datad (1386:1386:1386) (1428:1428:1428)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla21M2T3_4) - (DELAY - (ABSOLUTE - (PORT dataa (869:869:869) (907:907:907)) - (PORT datab (364:364:364) (400:400:400)) - (PORT datac (656:656:656) (701:701:701)) - (PORT datad (837:837:837) (878:878:878)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~7) - (DELAY - (ABSOLUTE - (PORT dataa (714:714:714) (810:810:810)) - (PORT datab (933:933:933) (988:988:988)) - (PORT datac (981:981:981) (1058:1058:1058)) - (PORT datad (194:194:194) (218:218:218)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1441:1441:1441) (1552:1552:1552)) - (PORT datab (614:614:614) (644:644:644)) - (PORT datac (1197:1197:1197) (1258:1258:1258)) - (PORT datad (844:844:844) (855:855:855)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (229:229:229) (275:275:275)) - (PORT datab (208:208:208) (250:250:250)) - (PORT datac (588:588:588) (608:608:608)) - (PORT datad (876:876:876) (896:896:896)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1212:1212:1212) (1250:1250:1250)) - (PORT datab (965:965:965) (1013:1013:1013)) - (PORT datac (1049:1049:1049) (1111:1111:1111)) - (PORT datad (1444:1444:1444) (1477:1477:1477)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1082:1082:1082) (1153:1153:1153)) - (PORT datab (970:970:970) (1019:1019:1019)) - (PORT datac (308:308:308) (334:334:334)) - (PORT datad (628:628:628) (654:654:654)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1024:1024:1024) (1085:1085:1085)) - (PORT datab (1386:1386:1386) (1414:1414:1414)) - (PORT datac (1180:1180:1180) (1211:1211:1211)) - (PORT datad (1209:1209:1209) (1252:1252:1252)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~5) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (255:255:255)) - (PORT datab (1246:1246:1246) (1296:1296:1296)) - (PORT datac (984:984:984) (1048:1048:1048)) - (PORT datad (625:625:625) (654:654:654)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla20M1T5_5) - (DELAY - (ABSOLUTE - (PORT dataa (873:873:873) (910:910:910)) - (PORT datab (1428:1428:1428) (1466:1466:1466)) - (PORT datac (1688:1688:1688) (1726:1726:1726)) - (PORT datad (2057:2057:2057) (2190:2190:2190)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (613:613:613) (642:642:642)) - (PORT datab (208:208:208) (250:250:250)) - (PORT datac (1398:1398:1398) (1422:1422:1422)) - (PORT datad (1424:1424:1424) (1462:1462:1462)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1803:1803:1803) (1945:1945:1945)) - (PORT datab (847:847:847) (858:858:858)) - (PORT datac (838:838:838) (869:869:869)) - (PORT datad (2056:2056:2056) (2191:2191:2191)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~1) - (DELAY - (ABSOLUTE - (PORT dataa (825:825:825) (847:847:847)) - (PORT datab (783:783:783) (809:809:809)) - (PORT datac (170:170:170) (202:202:202)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~2) - (DELAY - (ABSOLUTE - (PORT dataa (350:350:350) (382:382:382)) - (PORT datab (220:220:220) (258:258:258)) - (PORT datac (193:193:193) (227:227:227)) - (PORT datad (539:539:539) (561:561:561)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (952:952:952) (1004:1004:1004)) - (PORT datab (876:876:876) (893:893:893)) - (PORT datac (1689:1689:1689) (1781:1781:1781)) - (PORT datad (1175:1175:1175) (1232:1232:1232)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1346:1346:1346) (1340:1340:1340)) - (PORT datab (1176:1176:1176) (1219:1219:1219)) - (PORT datac (1123:1123:1123) (1137:1137:1137)) - (PORT datad (665:665:665) (719:719:719)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1197:1197:1197) (1247:1247:1247)) - (PORT datac (582:582:582) (614:614:614)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (1190:1190:1190) (1242:1242:1242)) - (PORT datab (650:650:650) (679:679:679)) - (PORT datac (191:191:191) (237:237:237)) - (PORT datad (607:607:607) (635:635:635)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~7) - (DELAY - (ABSOLUTE - (PORT dataa (228:228:228) (274:274:274)) - (PORT datac (2094:2094:2094) (2219:2219:2219)) - (PORT datad (1462:1462:1462) (1527:1527:1527)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel_pla66npla53M1T1_15) - (DELAY - (ABSOLUTE - (PORT dataa (424:424:424) (461:461:461)) - (PORT datab (1161:1161:1161) (1190:1190:1190)) - (PORT datac (1460:1460:1460) (1518:1518:1518)) - (PORT datad (1106:1106:1106) (1136:1136:1136)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1080:1080:1080) (1147:1147:1147)) - (PORT datab (1037:1037:1037) (1105:1105:1105)) - (PORT datac (1180:1180:1180) (1210:1210:1210)) - (PORT datad (1210:1210:1210) (1252:1252:1252)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~8) - (DELAY - (ABSOLUTE - (PORT dataa (898:898:898) (919:919:919)) - (PORT datab (661:661:661) (705:705:705)) - (PORT datac (1104:1104:1104) (1117:1117:1117)) - (PORT datad (766:766:766) (786:786:786)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1112:1112:1112) (1156:1156:1156)) - (PORT datab (1528:1528:1528) (1657:1657:1657)) - (PORT datac (609:609:609) (665:665:665)) - (PORT datad (181:181:181) (210:210:210)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~4) - (DELAY - (ABSOLUTE - (PORT dataa (734:734:734) (762:762:762)) - (PORT datab (849:849:849) (885:885:885)) - (PORT datac (787:787:787) (804:804:804)) - (PORT datad (670:670:670) (694:694:694)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1025:1025:1025) (1084:1084:1084)) - (PORT datab (969:969:969) (1019:1019:1019)) - (PORT datac (192:192:192) (223:223:223)) - (PORT datad (1444:1444:1444) (1475:1475:1475)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1298:1298:1298) (1390:1390:1390)) - (PORT datab (968:968:968) (1017:1017:1017)) - (PORT datac (1050:1050:1050) (1110:1110:1110)) - (PORT datad (1553:1553:1553) (1682:1682:1682)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~43) - (DELAY - (ABSOLUTE - (PORT dataa (1298:1298:1298) (1391:1391:1391)) - (PORT datab (1247:1247:1247) (1291:1291:1291)) - (PORT datac (985:985:985) (1043:1043:1043)) - (PORT datad (1553:1553:1553) (1682:1682:1682)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~26) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datac (179:179:179) (215:215:215)) - (PORT datad (182:182:182) (211:211:211)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (564:564:564) (579:579:579)) - (PORT datab (244:244:244) (288:288:288)) - (PORT datac (543:543:543) (551:551:551)) - (PORT datad (1454:1454:1454) (1511:1511:1511)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~9) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (1400:1400:1400) (1422:1422:1422)) - (PORT datac (572:572:572) (596:596:596)) - (PORT datad (602:602:602) (630:630:630)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~11) - (DELAY - (ABSOLUTE - (PORT dataa (681:681:681) (737:737:737)) - (PORT datab (1115:1115:1115) (1164:1164:1164)) - (PORT datac (969:969:969) (1001:1001:1001)) - (PORT datad (1160:1160:1160) (1223:1223:1223)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~5) - (DELAY - (ABSOLUTE - (PORT dataa (915:915:915) (984:984:984)) - (PORT datab (941:941:941) (1009:1009:1009)) - (PORT datac (1210:1210:1210) (1289:1289:1289)) - (PORT datad (381:381:381) (406:406:406)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1765:1765:1765) (1808:1808:1808)) - (PORT datab (1620:1620:1620) (1658:1658:1658)) - (PORT datac (1305:1305:1305) (1421:1421:1421)) - (PORT datad (1541:1541:1541) (1677:1677:1677)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1103:1103:1103) (1119:1119:1119)) - (PORT datab (1046:1046:1046) (1094:1094:1094)) - (PORT datac (952:952:952) (984:984:984)) - (PORT datad (819:819:819) (844:844:844)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~7) - (DELAY - (ABSOLUTE - (PORT dataa (982:982:982) (1023:1023:1023)) - (PORT datab (700:700:700) (721:721:721)) - (PORT datac (216:216:216) (260:260:260)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~12) - (DELAY - (ABSOLUTE - (PORT dataa (860:860:860) (874:874:874)) - (PORT datab (648:648:648) (669:669:669)) - (PORT datac (877:877:877) (899:899:899)) - (PORT datad (813:813:813) (834:834:834)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~13) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (363:363:363) (397:397:397)) - (PORT datac (964:964:964) (1033:1033:1033)) - (PORT datad (590:590:590) (607:607:607)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~14) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (265:265:265)) - (PORT datac (1711:1711:1711) (1773:1773:1773)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (242:242:242) (296:296:296)) - (PORT datab (1200:1200:1200) (1240:1240:1240)) - (PORT datac (1213:1213:1213) (1232:1232:1232)) - (PORT datad (559:559:559) (571:571:571)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (1102:1102:1102) (1121:1121:1121)) - (PORT datab (246:246:246) (294:294:294)) - (PORT datac (901:901:901) (943:943:943)) - (PORT datad (1975:1975:1975) (2012:2012:2012)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~40) - (DELAY - (ABSOLUTE - (PORT dataa (823:823:823) (840:840:840)) - (PORT datab (850:850:850) (877:877:877)) - (PORT datac (595:595:595) (617:617:617)) - (PORT datad (811:811:811) (824:824:824)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~53) - (DELAY - (ABSOLUTE - (PORT dataa (2154:2154:2154) (2304:2304:2304)) - (PORT datab (1756:1756:1756) (1875:1875:1875)) - (PORT datac (868:868:868) (905:905:905)) - (PORT datad (2343:2343:2343) (2450:2450:2450)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~8) - (DELAY - (ABSOLUTE - (PORT dataa (963:963:963) (1025:1025:1025)) - (PORT datab (2108:2108:2108) (2222:2222:2222)) - (PORT datac (548:548:548) (573:573:573)) - (PORT datad (1982:1982:1982) (2069:2069:2069)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~54) - (DELAY - (ABSOLUTE - (PORT dataa (1779:1779:1779) (1888:1888:1888)) - (PORT datab (1077:1077:1077) (1152:1152:1152)) - (PORT datac (971:971:971) (991:991:991)) - (PORT datad (2049:2049:2049) (2156:2156:2156)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1126:1126:1126) (1244:1244:1244)) - (PORT datab (1192:1192:1192) (1241:1241:1241)) - (PORT datac (610:610:610) (626:626:626)) - (PORT datad (2306:2306:2306) (2345:2345:2345)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~4) - (DELAY - (ABSOLUTE - (PORT dataa (998:998:998) (1033:1033:1033)) - (PORT datab (1150:1150:1150) (1177:1177:1177)) - (PORT datac (346:346:346) (385:385:385)) - (PORT datad (630:630:630) (669:669:669)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~5) - (DELAY - (ABSOLUTE - (PORT dataa (865:865:865) (890:890:890)) - (PORT datac (839:839:839) (858:858:858)) - (PORT datad (520:520:520) (531:531:531)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~6) - (DELAY - (ABSOLUTE - (PORT dataa (238:238:238) (288:288:288)) - (PORT datab (250:250:250) (300:300:300)) - (PORT datac (1960:1960:1960) (2089:2089:2089)) - (PORT datad (202:202:202) (238:238:238)) - (IOPATH dataa combout (303:303:303) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~35) - (DELAY - (ABSOLUTE - (PORT dataa (1352:1352:1352) (1478:1478:1478)) - (PORT datab (1346:1346:1346) (1363:1363:1363)) - (PORT datac (870:870:870) (896:896:896)) - (PORT datad (1449:1449:1449) (1511:1511:1511)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (1104:1104:1104) (1189:1189:1189)) - (PORT datab (685:685:685) (754:754:754)) - (PORT datac (958:958:958) (1039:1039:1039)) - (PORT datad (613:613:613) (629:629:629)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~6) - (DELAY - (ABSOLUTE - (PORT dataa (627:627:627) (664:664:664)) - (PORT datab (973:973:973) (1069:1069:1069)) - (PORT datac (1733:1733:1733) (1832:1832:1832)) - (PORT datad (1149:1149:1149) (1173:1173:1173)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1999:1999:1999) (2036:2036:2036)) - (PORT datab (872:872:872) (899:899:899)) - (PORT datac (1356:1356:1356) (1432:1432:1432)) - (PORT datad (1348:1348:1348) (1396:1396:1396)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~0) - (DELAY - (ABSOLUTE - (PORT dataa (618:618:618) (650:650:650)) - (PORT datab (1061:1061:1061) (1123:1123:1123)) - (PORT datac (208:208:208) (247:247:247)) - (PORT datad (864:864:864) (923:923:923)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~3) - (DELAY - (ABSOLUTE - (PORT dataa (612:612:612) (632:632:632)) - (PORT datab (203:203:203) (245:245:245)) - (PORT datac (877:877:877) (914:914:914)) - (PORT datad (853:853:853) (874:874:874)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~52) - (DELAY - (ABSOLUTE - (PORT dataa (1749:1749:1749) (1769:1769:1769)) - (PORT datab (1064:1064:1064) (1181:1181:1181)) - (PORT datac (1204:1204:1204) (1273:1273:1273)) - (PORT datad (860:860:860) (875:875:875)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (686:686:686) (719:719:719)) - (PORT datab (1166:1166:1166) (1236:1236:1236)) - (PORT datac (1485:1485:1485) (1511:1511:1511)) - (PORT datad (1469:1469:1469) (1516:1516:1516)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~2) - (DELAY - (ABSOLUTE - (PORT dataa (858:858:858) (880:880:880)) - (PORT datab (1385:1385:1385) (1395:1395:1395)) - (PORT datac (777:777:777) (796:796:796)) - (PORT datad (1739:1739:1739) (1779:1779:1779)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|rsel3) - (DELAY - (ABSOLUTE - (PORT dataa (1404:1404:1404) (1480:1480:1480)) - (PORT datab (2358:2358:2358) (2492:2492:2492)) - (PORT datac (1133:1133:1133) (1174:1174:1174)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~5) - (DELAY - (ABSOLUTE - (PORT dataa (966:966:966) (1016:1016:1016)) - (PORT datab (1031:1031:1031) (1053:1053:1053)) - (PORT datac (181:181:181) (219:219:219)) - (PORT datad (652:652:652) (692:692:692)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~6) - (DELAY - (ABSOLUTE - (PORT dataa (590:590:590) (616:616:616)) - (PORT datab (672:672:672) (701:701:701)) - (PORT datac (510:510:510) (522:522:522)) - (PORT datad (840:840:840) (853:853:853)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~7) - (DELAY - (ABSOLUTE - (PORT dataa (207:207:207) (256:256:256)) - (PORT datab (884:884:884) (911:911:911)) - (PORT datac (866:866:866) (930:930:930)) - (PORT datad (180:180:180) (209:209:209)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|rsel0) - (DELAY - (ABSOLUTE - (PORT dataa (2169:2169:2169) (2322:2322:2322)) - (PORT datac (1461:1461:1461) (1534:1534:1534)) - (PORT datad (2260:2260:2260) (2326:2326:2326)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_ixy_dT2_2) - (DELAY - (ABSOLUTE - (PORT datab (924:924:924) (1011:1011:1011)) - (PORT datac (1545:1545:1545) (1672:1672:1672)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (705:705:705) (747:747:747)) - (PORT datab (868:868:868) (890:890:890)) - (PORT datac (1285:1285:1285) (1378:1378:1378)) - (PORT datad (896:896:896) (936:936:936)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1484:1484:1484) (1547:1547:1547)) - (PORT datab (205:205:205) (245:245:245)) - (PORT datac (988:988:988) (1034:1034:1034)) - (PORT datad (1031:1031:1031) (1081:1081:1081)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~7) - (DELAY - (ABSOLUTE - (PORT dataa (236:236:236) (286:286:286)) - (PORT datab (373:373:373) (398:398:398)) - (PORT datac (599:599:599) (641:641:641)) - (PORT datad (200:200:200) (235:235:235)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_iorw\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1623:1623:1623) (1713:1713:1713)) - (PORT datab (1529:1529:1529) (1662:1662:1662)) - (PORT datac (1705:1705:1705) (1826:1826:1826)) - (PORT datad (1447:1447:1447) (1495:1495:1495)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1779:1779:1779) (1826:1826:1826)) - (PORT datab (681:681:681) (732:732:732)) - (PORT datac (551:551:551) (571:571:571)) - (PORT datad (1134:1134:1134) (1177:1177:1177)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~14) - (DELAY - (ABSOLUTE - (PORT dataa (688:688:688) (759:759:759)) - (PORT datab (1001:1001:1001) (1109:1109:1109)) - (PORT datac (192:192:192) (226:226:226)) - (PORT datad (1242:1242:1242) (1328:1328:1328)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~11) - (DELAY - (ABSOLUTE - (PORT dataa (598:598:598) (630:630:630)) - (PORT datab (875:875:875) (920:920:920)) - (PORT datac (338:338:338) (364:364:364)) - (PORT datad (685:685:685) (739:739:739)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~12) - (DELAY - (ABSOLUTE - (PORT dataa (655:655:655) (707:707:707)) - (PORT datab (950:950:950) (1008:1008:1008)) - (PORT datac (590:590:590) (605:605:605)) - (PORT datad (654:654:654) (692:692:692)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2d\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1138:1138:1138) (1171:1171:1171)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (566:566:566) (595:595:595)) - (PORT datad (180:180:180) (208:208:208)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_66_oe) - (DELAY - (ABSOLUTE - (PORT dataa (362:362:362) (494:494:494)) - (PORT datab (1299:1299:1299) (1396:1396:1396)) - (PORT datac (680:680:680) (764:764:764)) - (PORT datad (1300:1300:1300) (1391:1391:1391)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~34) - (DELAY - (ABSOLUTE - (PORT dataa (1581:1581:1581) (1626:1626:1626)) - (PORT datab (906:906:906) (950:950:950)) - (PORT datac (1263:1263:1263) (1320:1320:1320)) - (PORT datad (1666:1666:1666) (1688:1688:1688)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_apin_mux\~0) - (DELAY - (ABSOLUTE - (PORT dataa (370:370:370) (401:401:401)) - (PORT datab (221:221:221) (260:260:260)) - (PORT datac (653:653:653) (714:714:714)) - (PORT datad (1668:1668:1668) (1689:1689:1689)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1304:1304:1304) (1373:1373:1373)) - (PORT datab (1184:1184:1184) (1235:1235:1235)) - (PORT datac (1139:1139:1139) (1197:1197:1197)) - (PORT datad (1323:1323:1323) (1433:1433:1433)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~75) - (DELAY - (ABSOLUTE - (PORT dataa (908:908:908) (940:940:940)) - (PORT datab (380:380:380) (410:410:410)) - (PORT datac (654:654:654) (698:698:698)) - (PORT datad (1204:1204:1204) (1277:1277:1277)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~76) - (DELAY - (ABSOLUTE - (PORT dataa (1111:1111:1111) (1116:1116:1116)) - (PORT datab (917:917:917) (963:963:963)) - (PORT datac (1010:1010:1010) (1060:1060:1060)) - (PORT datad (924:924:924) (954:954:954)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (206:206:206) (251:251:251)) - (PORT datab (964:964:964) (1061:1061:1061)) - (PORT datac (844:844:844) (886:886:886)) - (PORT datad (905:905:905) (950:950:950)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~48) - (DELAY - (ABSOLUTE - (PORT dataa (998:998:998) (1084:1084:1084)) - (PORT datab (1205:1205:1205) (1272:1272:1272)) - (PORT datac (1579:1579:1579) (1687:1687:1687)) - (PORT datad (1138:1138:1138) (1195:1195:1195)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~46) - (DELAY - (ABSOLUTE - (PORT dataa (613:613:613) (653:653:653)) - (PORT datab (2073:2073:2073) (2252:2252:2252)) - (PORT datac (861:861:861) (894:894:894)) - (PORT datad (1257:1257:1257) (1349:1349:1349)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~53) - (DELAY - (ABSOLUTE - (PORT dataa (892:892:892) (961:961:961)) - (PORT datab (916:916:916) (955:955:955)) - (PORT datac (1131:1131:1131) (1156:1156:1156)) - (PORT datad (926:926:926) (955:955:955)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~92) - (DELAY - (ABSOLUTE - (PORT dataa (1028:1028:1028) (1147:1147:1147)) - (PORT datab (1588:1588:1588) (1723:1723:1723)) - (PORT datac (637:637:637) (656:656:656)) - (PORT datad (1691:1691:1691) (1790:1790:1790)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal19\~1) - (DELAY - (ABSOLUTE - (PORT dataa (2337:2337:2337) (2490:2490:2490)) - (PORT datab (1668:1668:1668) (1785:1785:1785)) - (PORT datac (905:905:905) (956:956:956)) - (PORT datad (672:672:672) (720:720:720)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1009:1009:1009) (1130:1130:1130)) - (PORT datad (1542:1542:1542) (1657:1657:1657)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~38) - (DELAY - (ABSOLUTE - (PORT dataa (1306:1306:1306) (1373:1373:1373)) - (PORT datab (656:656:656) (703:703:703)) - (PORT datac (1351:1351:1351) (1409:1409:1409)) - (PORT datad (881:881:881) (908:908:908)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~93) - (DELAY - (ABSOLUTE - (PORT dataa (1127:1127:1127) (1148:1148:1148)) - (PORT datab (1720:1720:1720) (1825:1825:1825)) - (PORT datac (1557:1557:1557) (1685:1685:1685)) - (PORT datad (1001:1001:1001) (1102:1102:1102)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~39) - (DELAY - (ABSOLUTE - (PORT dataa (1356:1356:1356) (1478:1478:1478)) - (PORT datab (827:827:827) (854:854:854)) - (PORT datac (1113:1113:1113) (1149:1149:1149)) - (PORT datad (635:635:635) (687:687:687)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~24) - (DELAY - (ABSOLUTE - (PORT datab (1169:1169:1169) (1230:1230:1230)) - (PORT datac (194:194:194) (227:227:227)) - (PORT datad (183:183:183) (212:212:212)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~1) - (DELAY - (ABSOLUTE - (PORT dataa (222:222:222) (266:266:266)) - (PORT datab (851:851:851) (919:919:919)) - (PORT datac (194:194:194) (241:241:241)) - (PORT datad (673:673:673) (732:732:732)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla9M1T5_2) - (DELAY - (ABSOLUTE - (PORT dataa (968:968:968) (1052:1052:1052)) - (PORT datab (936:936:936) (1006:1006:1006)) - (PORT datac (1407:1407:1407) (1449:1449:1449)) - (PORT datad (537:537:537) (548:548:548)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~44) - (DELAY - (ABSOLUTE - (PORT dataa (592:592:592) (620:620:620)) - (PORT datab (867:867:867) (902:902:902)) - (PORT datac (1366:1366:1366) (1470:1470:1470)) - (PORT datad (1496:1496:1496) (1606:1606:1606)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (951:951:951) (985:985:985)) - (PORT datab (916:916:916) (957:957:957)) - (PORT datac (915:915:915) (950:950:950)) - (PORT datad (1540:1540:1540) (1625:1625:1625)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1174:1174:1174) (1214:1214:1214)) - (PORT datab (649:649:649) (694:694:694)) - (PORT datac (902:902:902) (950:950:950)) - (PORT datad (338:338:338) (355:355:355)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla10M5T4_2) - (DELAY - (ABSOLUTE - (PORT datab (1511:1511:1511) (1618:1618:1618)) - (PORT datac (1726:1726:1726) (1837:1837:1837)) - (PORT datad (1072:1072:1072) (1082:1082:1082)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (675:675:675) (734:734:734)) - (PORT datab (1163:1163:1163) (1210:1210:1210)) - (PORT datac (852:852:852) (881:881:881)) - (PORT datad (1173:1173:1173) (1254:1254:1254)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~2) - (DELAY - (ABSOLUTE - (PORT dataa (966:966:966) (1001:1001:1001)) - (PORT datab (946:946:946) (986:986:986)) - (PORT datac (632:632:632) (678:678:678)) - (PORT datad (1150:1150:1150) (1195:1195:1195)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~3) - (DELAY - (ABSOLUTE - (PORT datab (865:865:865) (918:918:918)) - (PORT datac (179:179:179) (213:213:213)) - (PORT datad (851:851:851) (896:896:896)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1052:1052:1052) (1077:1077:1077)) - (PORT datab (1450:1450:1450) (1521:1521:1521)) - (PORT datac (1291:1291:1291) (1321:1321:1321)) - (PORT datad (856:856:856) (875:875:875)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1685:1685:1685) (1750:1750:1750)) - (PORT datab (1695:1695:1695) (1779:1779:1779)) - (PORT datac (1479:1479:1479) (1576:1576:1576)) - (PORT datad (855:855:855) (874:874:874)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla38pla13M4T2_4) - (DELAY - (ABSOLUTE - (PORT dataa (1444:1444:1444) (1505:1505:1505)) - (PORT datab (1695:1695:1695) (1774:1774:1774)) - (PORT datac (1653:1653:1653) (1704:1704:1704)) - (PORT datad (1165:1165:1165) (1208:1208:1208)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~15) - (DELAY - (ABSOLUTE - (PORT dataa (829:829:829) (902:902:902)) - (PORT datab (612:612:612) (626:626:626)) - (PORT datac (1486:1486:1486) (1525:1525:1525)) - (PORT datad (572:572:572) (587:587:587)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (932:932:932) (953:953:953)) - (PORT datab (920:920:920) (939:939:939)) - (PORT datac (888:888:888) (933:933:933)) - (PORT datad (195:195:195) (221:221:221)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~94) - (DELAY - (ABSOLUTE - (PORT dataa (1805:1805:1805) (1846:1846:1846)) - (PORT datab (1718:1718:1718) (1824:1824:1824)) - (PORT datac (1560:1560:1560) (1684:1684:1684)) - (PORT datad (1003:1003:1003) (1103:1103:1103)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~87) - (DELAY - (ABSOLUTE - (PORT dataa (1617:1617:1617) (1736:1736:1736)) - (PORT datac (2516:2516:2516) (2621:2621:2621)) - (PORT datad (1496:1496:1496) (1610:1610:1610)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~42) - (DELAY - (ABSOLUTE - (PORT dataa (1179:1179:1179) (1204:1204:1204)) - (PORT datab (1153:1153:1153) (1208:1208:1208)) - (PORT datac (193:193:193) (226:226:226)) - (PORT datad (861:861:861) (880:880:880)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~34) - (DELAY - (ABSOLUTE - (PORT datab (684:684:684) (709:709:709)) - (PORT datac (378:378:378) (413:413:413)) - (PORT datad (203:203:203) (232:232:232)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~16) - (DELAY - (ABSOLUTE - (PORT dataa (454:454:454) (494:494:494)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (807:807:807) (827:827:827)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4u\~6) - (DELAY - (ABSOLUTE - (PORT dataa (372:372:372) (413:413:413)) - (PORT datab (907:907:907) (914:914:914)) - (PORT datac (619:619:619) (656:656:656)) - (PORT datad (1190:1190:1190) (1243:1243:1243)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal2\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1250:1250:1250) (1344:1344:1344)) - (PORT datab (1673:1673:1673) (1790:1790:1790)) - (PORT datac (909:909:909) (958:958:958)) - (PORT datad (940:940:940) (995:995:995)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal1\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1458:1458:1458) (1556:1556:1556)) - (PORT datab (1664:1664:1664) (1735:1735:1735)) - (PORT datac (847:847:847) (861:861:861)) - (PORT datad (654:654:654) (683:683:683)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|bank_exx\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1407:1407:1407) (1552:1552:1552)) - (PORT datab (901:901:901) (929:929:929)) - (PORT datad (2354:2354:2354) (2501:2501:2501)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_control_\|bank_exx) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1532:1532:1532)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1575:1575:1575) (1555:1555:1555)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|bank_hl_de1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1165:1165:1165) (1200:1200:1200)) - (PORT datab (1193:1193:1193) (1243:1243:1243)) - (PORT datad (1206:1206:1206) (1288:1288:1288)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_control_\|bank_hl_de1) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1553:1553:1553)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1593:1593:1593) (1569:1569:1569)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (928:928:928) (961:961:961)) - (PORT datab (2051:2051:2051) (2083:2083:2083)) - (PORT datac (805:805:805) (817:817:817)) - (PORT datad (336:336:336) (360:360:360)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (965:965:965) (998:998:998)) - (PORT datab (1733:1733:1733) (1770:1770:1770)) - (PORT datac (1229:1229:1229) (1327:1327:1327)) - (PORT datad (1151:1151:1151) (1194:1194:1194)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (766:766:766) (785:785:785)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (1230:1230:1230) (1329:1329:1329)) - (PORT datad (1542:1542:1542) (1627:1627:1627)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1235:1235:1235) (1298:1298:1298)) - (PORT datab (1276:1276:1276) (1367:1367:1367)) - (PORT datac (1156:1156:1156) (1195:1195:1195)) - (PORT datad (711:711:711) (777:777:777)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (622:622:622) (656:656:656)) - (PORT datab (603:603:603) (615:615:615)) - (PORT datac (902:902:902) (950:950:950)) - (PORT datad (1750:1750:1750) (1806:1806:1806)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (937:937:937) (985:985:985)) - (PORT datab (359:359:359) (388:388:388)) - (PORT datac (1182:1182:1182) (1242:1242:1242)) - (PORT datad (2028:2028:2028) (2153:2153:2153)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (341:341:341) (372:372:372)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (878:878:878) (913:913:913)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~47) - (DELAY - (ABSOLUTE - (PORT dataa (970:970:970) (1069:1069:1069)) - (PORT datab (913:913:913) (1002:1002:1002)) - (PORT datac (1084:1084:1084) (1074:1074:1074)) - (PORT datad (1060:1060:1060) (1062:1062:1062)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1344:1344:1344) (1441:1441:1441)) - (PORT datab (898:898:898) (946:946:946)) - (PORT datac (669:669:669) (692:692:692)) - (PORT datad (1162:1162:1162) (1228:1228:1228)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~5) - (DELAY - (ABSOLUTE - (PORT dataa (2046:2046:2046) (2143:2143:2143)) - (PORT datac (1652:1652:1652) (1690:1690:1690)) - (PORT datad (1726:1726:1726) (1766:1766:1766)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~2) - (DELAY - (ABSOLUTE - (PORT dataa (985:985:985) (1068:1068:1068)) - (PORT datab (1320:1320:1320) (1358:1358:1358)) - (PORT datac (1320:1320:1320) (1375:1375:1375)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~19) - (DELAY - (ABSOLUTE - (PORT datab (667:667:667) (677:677:677)) - (PORT datac (650:650:650) (674:674:674)) - (PORT datad (899:899:899) (937:937:937)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (666:666:666) (691:691:691)) - (PORT datab (711:711:711) (745:745:745)) - (PORT datac (675:675:675) (730:730:730)) - (PORT datad (832:832:832) (843:843:843)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (844:844:844) (889:889:889)) - (PORT datac (1915:1915:1915) (1982:1982:1982)) - (PORT datad (200:200:200) (239:239:239)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (611:611:611) (677:677:677)) - (PORT datab (864:864:864) (932:932:932)) - (PORT datac (1099:1099:1099) (1123:1123:1123)) - (PORT datad (830:830:830) (852:852:852)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1058:1058:1058) (1166:1166:1166)) - (PORT datab (1000:1000:1000) (1115:1115:1115)) - (PORT datac (1411:1411:1411) (1477:1477:1477)) - (PORT datad (203:203:203) (239:239:239)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1061:1061:1061) (1166:1166:1166)) - (PORT datab (1976:1976:1976) (2065:2065:2065)) - (PORT datac (1151:1151:1151) (1205:1205:1205)) - (PORT datad (941:941:941) (1012:1012:1012)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (199:199:199) (239:239:239)) - (PORT datac (2603:2603:2603) (2772:2772:2772)) - (PORT datad (194:194:194) (219:219:219)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (932:932:932) (1032:1032:1032)) - (PORT datac (1109:1109:1109) (1164:1164:1164)) - (PORT datad (1148:1148:1148) (1191:1191:1191)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~2) - (DELAY - (ABSOLUTE - (PORT dataa (988:988:988) (1040:1040:1040)) - (PORT datab (845:845:845) (850:850:850)) - (PORT datac (2021:2021:2021) (2050:2050:2050)) - (PORT datad (1388:1388:1388) (1426:1426:1426)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~47) - (DELAY - (ABSOLUTE - (PORT dataa (1582:1582:1582) (1703:1703:1703)) - (PORT datab (917:917:917) (971:971:971)) - (PORT datac (929:929:929) (1008:1008:1008)) - (PORT datad (1530:1530:1530) (1630:1630:1630)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~3) - (DELAY - (ABSOLUTE - (PORT dataa (642:642:642) (674:674:674)) - (PORT datab (871:871:871) (890:890:890)) - (PORT datac (598:598:598) (661:661:661)) - (PORT datad (809:809:809) (825:825:825)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_1d\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1116:1116:1116) (1239:1239:1239)) - (PORT datac (1383:1383:1383) (1458:1458:1458)) - (PORT datad (2108:2108:2108) (2253:2253:2253)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (896:896:896) (968:968:968)) - (PORT datab (1559:1559:1559) (1655:1655:1655)) - (PORT datac (211:211:211) (252:252:252)) - (PORT datad (618:618:618) (634:634:634)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (1375:1375:1375) (1445:1445:1445)) - (PORT datab (619:619:619) (640:640:640)) - (PORT datac (776:776:776) (799:799:799)) - (PORT datad (597:597:597) (614:614:614)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (1683:1683:1683) (1739:1739:1739)) - (PORT datab (1115:1115:1115) (1125:1125:1125)) - (PORT datac (1054:1054:1054) (1110:1110:1110)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~49) - (DELAY - (ABSOLUTE - (PORT dataa (1324:1324:1324) (1411:1411:1411)) - (PORT datab (205:205:205) (247:247:247)) - (PORT datac (592:592:592) (627:627:627)) - (PORT datad (1466:1466:1466) (1538:1538:1538)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (576:576:576) (604:604:604)) - (PORT datab (614:614:614) (675:675:675)) - (PORT datac (611:611:611) (636:636:636)) - (PORT datad (573:573:573) (586:586:586)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (2248:2248:2248) (2386:2386:2386)) - (PORT datab (260:260:260) (341:341:341)) - (PORT datac (1161:1161:1161) (1218:1218:1218)) - (PORT datad (235:235:235) (303:303:303)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~23) + (INSTANCE z80_\|interrupts_\|iff1\~1) (DELAY (ABSOLUTE (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (179:179:179) (216:216:216)) - (PORT datad (874:874:874) (909:909:909)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~28) - (DELAY - (ABSOLUTE - (PORT datab (208:208:208) (250:250:250)) - (PORT datad (663:663:663) (707:707:707)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (215:215:215) (266:266:266)) - (PORT datab (1027:1027:1027) (1068:1068:1068)) - (PORT datac (332:332:332) (358:358:358)) - (PORT datad (688:688:688) (740:740:740)) + (PORT datab (1002:1002:1002) (1061:1061:1061)) + (PORT datac (241:241:241) (318:318:318)) + (PORT datad (1108:1108:1108) (1117:1117:1117)) (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1125:1125:1125) (1247:1247:1247)) - (PORT datac (887:887:887) (944:944:944)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~14) - (DELAY - (ABSOLUTE - (PORT datac (663:663:663) (747:747:747)) - (PORT datad (890:890:890) (915:915:915)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1435:1435:1435) (1516:1516:1516)) - (PORT datab (619:619:619) (646:646:646)) - (PORT datac (172:172:172) (204:204:204)) - (PORT datad (1126:1126:1126) (1172:1172:1172)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~47) - (DELAY - (ABSOLUTE - (PORT dataa (615:615:615) (640:640:640)) - (PORT datab (648:648:648) (672:672:672)) - (PORT datac (891:891:891) (929:929:929)) - (PORT datad (873:873:873) (908:908:908)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~48) - (DELAY - (ABSOLUTE - (PORT dataa (346:346:346) (385:385:385)) - (PORT datab (220:220:220) (259:259:259)) - (PORT datac (616:616:616) (658:658:658)) - (PORT datad (1046:1046:1046) (1069:1069:1069)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~13) - (DELAY - (ABSOLUTE - (PORT dataa (2048:2048:2048) (2143:2143:2143)) - (PORT datac (1652:1652:1652) (1688:1688:1688)) - (PORT datad (1726:1726:1726) (1766:1766:1766)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1331:1331:1331) (1424:1424:1424)) - (PORT datab (1098:1098:1098) (1141:1141:1141)) - (PORT datac (923:923:923) (945:945:945)) - (PORT datad (569:569:569) (578:578:578)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_oe\~1) - (DELAY - (ABSOLUTE - (PORT dataa (231:231:231) (278:278:278)) - (PORT datab (229:229:229) (272:272:272)) - (PORT datac (1186:1186:1186) (1234:1234:1234)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~13) - (DELAY - (ABSOLUTE - (PORT dataa (816:816:816) (855:855:855)) - (PORT datab (1257:1257:1257) (1326:1326:1326)) - (PORT datac (1798:1798:1798) (1932:1932:1932)) - (PORT datad (2112:2112:2112) (2257:2257:2257)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (632:632:632) (652:652:652)) - (PORT datac (595:595:595) (618:618:618)) - (PORT datad (847:847:847) (860:860:860)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~40) - (DELAY - (ABSOLUTE - (PORT dataa (1357:1357:1357) (1484:1484:1484)) - (PORT datab (742:742:742) (806:806:806)) - (PORT datac (873:873:873) (902:902:902)) - (PORT datad (887:887:887) (943:943:943)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~2) - (DELAY - (ABSOLUTE - (PORT dataa (904:904:904) (916:916:916)) - (PORT datab (683:683:683) (749:749:749)) - (PORT datac (971:971:971) (1032:1032:1032)) - (PORT datad (1783:1783:1783) (1858:1858:1858)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1298:1298:1298) (1401:1401:1401)) - (PORT datab (881:881:881) (925:925:925)) - (PORT datac (637:637:637) (657:657:657)) - (PORT datad (1737:1737:1737) (1788:1788:1788)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~43) - (DELAY - (ABSOLUTE - (PORT dataa (1357:1357:1357) (1486:1486:1486)) - (PORT datab (643:643:643) (709:709:709)) - (PORT datac (874:874:874) (901:901:901)) - (PORT datad (380:380:380) (406:406:406)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~5) - (DELAY - (ABSOLUTE - (PORT dataa (892:892:892) (953:953:953)) - (PORT datab (685:685:685) (750:750:750)) - (PORT datac (967:967:967) (1028:1028:1028)) - (PORT datad (629:629:629) (639:639:639)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1456:1456:1456) (1534:1534:1534)) - (PORT datab (926:926:926) (971:971:971)) - (PORT datac (191:191:191) (224:224:224)) - (PORT datad (1396:1396:1396) (1442:1442:1442)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1587:1587:1587) (1654:1654:1654)) - (PORT datab (1578:1578:1578) (1625:1625:1625)) - (PORT datac (1000:1000:1000) (1045:1045:1045)) - (PORT datad (1562:1562:1562) (1620:1620:1620)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1452:1452:1452) (1526:1526:1526)) - (PORT datab (898:898:898) (959:959:959)) - (PORT datac (823:823:823) (876:876:876)) - (PORT datad (584:584:584) (613:613:613)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1449:1449:1449) (1523:1523:1523)) - (PORT datab (899:899:899) (962:962:962)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (914:914:914) (977:977:977)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (596:596:596) (613:613:613)) - (PORT datab (864:864:864) (919:919:919)) - (PORT datac (792:792:792) (849:849:849)) - (PORT datad (781:781:781) (835:835:835)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~13) - (DELAY - (ABSOLUTE - (PORT dataa (652:652:652) (665:665:665)) - (PORT datab (238:238:238) (284:284:284)) - (PORT datac (1314:1314:1314) (1404:1404:1404)) - (PORT datad (2218:2218:2218) (2338:2338:2338)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1788:1788:1788) (1938:1938:1938)) - (PORT datab (1645:1645:1645) (1766:1766:1766)) - (PORT datac (1304:1304:1304) (1398:1398:1398)) - (PORT datad (2565:2565:2565) (2702:2702:2702)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1255:1255:1255) (1317:1317:1317)) - (PORT datab (870:870:870) (893:893:893)) - (PORT datac (173:173:173) (206:206:206)) - (PORT datad (588:588:588) (606:606:606)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1443:1443:1443) (1548:1548:1548)) - (PORT datab (263:263:263) (309:309:309)) - (PORT datac (1197:1197:1197) (1255:1255:1255)) - (PORT datad (842:842:842) (854:854:854)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal62\~2) - (DELAY - (ABSOLUTE - (PORT dataa (856:856:856) (910:910:910)) - (PORT datab (891:891:891) (912:912:912)) - (PORT datac (859:859:859) (877:877:877)) - (PORT datad (902:902:902) (978:978:978)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (859:859:859) (921:921:921)) - (PORT datab (937:937:937) (1012:1012:1012)) - (PORT datac (195:195:195) (239:239:239)) - (PORT datad (1152:1152:1152) (1199:1199:1199)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1470:1470:1470) (1476:1476:1476)) - (PORT datab (1497:1497:1497) (1569:1569:1569)) - (PORT datac (1102:1102:1102) (1120:1120:1120)) - (PORT datad (400:400:400) (436:436:436)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal64\~0) - (DELAY - (ABSOLUTE - (PORT dataa (854:854:854) (906:906:906)) - (PORT datab (893:893:893) (913:913:913)) - (PORT datac (861:861:861) (879:879:879)) - (PORT datad (904:904:904) (979:979:979)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel\[0\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (710:710:710) (805:805:805)) - (PORT datab (775:775:775) (880:880:880)) - (PORT datad (1178:1178:1178) (1197:1197:1197)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (593:593:593) (619:619:619)) - (PORT datab (1166:1166:1166) (1207:1207:1207)) - (PORT datac (854:854:854) (905:905:905)) - (PORT datad (902:902:902) (956:956:956)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1440:1440:1440) (1550:1550:1550)) - (PORT datab (866:866:866) (895:895:895)) - (PORT datac (1284:1284:1284) (1336:1336:1336)) - (PORT datad (1607:1607:1607) (1729:1729:1729)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla89M1T2_3) - (DELAY - (ABSOLUTE - (PORT dataa (1494:1494:1494) (1601:1601:1601)) - (PORT datab (1439:1439:1439) (1451:1451:1451)) - (PORT datac (1444:1444:1444) (1551:1551:1551)) - (PORT datad (402:402:402) (439:439:439)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (1017:1017:1017) (1057:1057:1057)) - (PORT datac (793:793:793) (802:802:802)) - (PORT datad (1022:1022:1022) (1048:1048:1048)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (397:397:397) (440:440:440)) - (PORT datac (980:980:980) (992:992:992)) - (PORT datad (182:182:182) (211:211:211)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (343:343:343) (373:373:373)) - (PORT datab (198:198:198) (235:235:235)) - (PORT datac (586:586:586) (613:613:613)) - (PORT datad (1522:1522:1522) (1622:1622:1622)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (1222:1222:1222) (1272:1272:1272)) - (PORT datab (1222:1222:1222) (1263:1263:1263)) - (PORT datac (892:892:892) (922:922:922)) - (PORT datad (1507:1507:1507) (1624:1624:1624)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (844:844:844) (886:886:886)) - (PORT datab (227:227:227) (274:274:274)) - (PORT datac (1160:1160:1160) (1222:1222:1222)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\~20) - (DELAY - (ABSOLUTE - (PORT dataa (1685:1685:1685) (1744:1744:1744)) - (PORT datab (1695:1695:1695) (1779:1779:1779)) - (PORT datac (1482:1482:1482) (1577:1577:1577)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (934:934:934) (1034:1034:1034)) - (PORT datab (206:206:206) (246:246:246)) - (PORT datac (1192:1192:1192) (1254:1254:1254)) - (PORT datad (882:882:882) (917:917:917)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~35) - (DELAY - (ABSOLUTE - (PORT datab (1193:1193:1193) (1230:1230:1230)) - (PORT datac (1251:1251:1251) (1308:1308:1308)) - (PORT datad (780:780:780) (799:799:799)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_de2\~5) - (DELAY - (ABSOLUTE - (PORT dataa (896:896:896) (976:976:976)) - (PORT datab (940:940:940) (1022:1022:1022)) - (PORT datac (1140:1140:1140) (1178:1178:1178)) - (PORT datad (375:375:375) (417:417:417)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_de2\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1284:1284:1284) (1345:1345:1345)) - (PORT datab (1189:1189:1189) (1228:1228:1228)) - (PORT datac (1135:1135:1135) (1177:1177:1177)) - (PORT datad (780:780:780) (799:799:799)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_hl\~0) - (DELAY - (ABSOLUTE - (PORT dataa (252:252:252) (343:343:343)) - (PORT datab (224:224:224) (272:272:272)) - (PORT datac (342:342:342) (371:371:371)) - (PORT datad (1219:1219:1219) (1301:1301:1301)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|bank_hl_de2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1167:1167:1167) (1203:1203:1203)) - (PORT datab (1191:1191:1191) (1242:1242:1242)) - (PORT datad (1220:1220:1220) (1299:1299:1299)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_control_\|bank_hl_de2) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1553:1553:1553)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1593:1593:1593) (1569:1569:1569)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_hl2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (368:368:368) (405:405:405)) - (PORT datab (224:224:224) (269:269:269)) - (PORT datac (222:222:222) (302:302:302)) - (PORT datad (1202:1202:1202) (1285:1285:1285)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~7) - (DELAY - (ABSOLUTE - (PORT dataa (568:568:568) (586:586:586)) - (PORT datab (1028:1028:1028) (1073:1073:1073)) - (PORT datac (338:338:338) (364:364:364)) - (PORT datad (686:686:686) (739:739:739)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (647:647:647) (687:687:687)) - (PORT datab (1720:1720:1720) (1802:1802:1802)) - (PORT datad (879:879:879) (876:876:876)) - (IOPATH dataa combout (301:301:301) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla30npla13M4T3_5) - (DELAY - (ABSOLUTE - (PORT dataa (2640:2640:2640) (2740:2740:2740)) - (PORT datab (1718:1718:1718) (1823:1823:1823)) - (PORT datac (1017:1017:1017) (1049:1049:1049)) - (PORT datad (1534:1534:1534) (1564:1564:1564)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (229:229:229) (277:277:277)) - (PORT datab (894:894:894) (923:923:923)) - (PORT datac (1486:1486:1486) (1564:1564:1564)) - (PORT datad (1217:1217:1217) (1256:1256:1256)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~13) - (DELAY - (ABSOLUTE - (PORT dataa (985:985:985) (1038:1038:1038)) - (PORT datab (204:204:204) (246:246:246)) - (PORT datac (946:946:946) (1014:1014:1014)) - (PORT datad (209:209:209) (240:240:240)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla30npla13M5T3_5) - (DELAY - (ABSOLUTE - (PORT dataa (941:941:941) (1011:1011:1011)) - (PORT datab (229:229:229) (278:278:278)) - (PORT datac (1408:1408:1408) (1479:1479:1479)) - (PORT datad (1499:1499:1499) (1550:1550:1550)) - (IOPATH dataa combout (304:304:304) (307:307:307)) (IOPATH datab combout (336:336:336) (325:325:325)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -8629,2584 +1404,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~2) + (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_15) (DELAY (ABSOLUTE - (PORT dataa (1150:1150:1150) (1181:1181:1181)) - (PORT datab (1549:1549:1549) (1573:1573:1573)) - (PORT datac (592:592:592) (626:626:626)) - (PORT datad (194:194:194) (219:219:219)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (357:357:357) (391:391:391)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (170:170:170) (202:202:202)) - (PORT datad (178:178:178) (207:207:207)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (910:910:910) (934:934:934)) - (PORT datab (654:654:654) (689:689:689)) - (PORT datac (1104:1104:1104) (1117:1117:1117)) - (PORT datad (766:766:766) (786:786:786)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1624:1624:1624) (1711:1711:1711)) - (PORT datab (1531:1531:1531) (1582:1582:1582)) - (PORT datac (1704:1704:1704) (1824:1824:1824)) - (PORT datad (1073:1073:1073) (1075:1075:1075)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~50) - (DELAY - (ABSOLUTE - (PORT dataa (2002:2002:2002) (2195:2195:2195)) - (PORT datab (1455:1455:1455) (1549:1549:1549)) - (PORT datac (1508:1508:1508) (1592:1592:1592)) - (PORT datad (1918:1918:1918) (1978:1978:1978)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (892:892:892) (965:965:965)) - (PORT datab (871:871:871) (909:909:909)) - (PORT datac (803:803:803) (870:870:870)) - (PORT datad (1526:1526:1526) (1620:1620:1620)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (621:621:621) (664:664:664)) - (PORT datab (678:678:678) (735:735:735)) - (PORT datac (919:919:919) (966:966:966)) - (PORT datad (181:181:181) (210:210:210)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (699:699:699) (728:728:728)) - (PORT datab (1191:1191:1191) (1244:1244:1244)) - (PORT datac (669:669:669) (694:694:694)) - (PORT datad (1304:1304:1304) (1397:1397:1397)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (1369:1369:1369) (1431:1431:1431)) - (PORT datab (643:643:643) (680:680:680)) - (PORT datac (1322:1322:1322) (1362:1362:1362)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla10M5T1_5\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1105:1105:1105) (1190:1190:1190)) - (PORT datab (1820:1820:1820) (1897:1897:1897)) - (PORT datad (966:966:966) (1074:1074:1074)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (904:904:904) (932:932:932)) - (PORT datab (680:680:680) (741:741:741)) - (PORT datac (202:202:202) (239:239:239)) - (PORT datad (2206:2206:2206) (2251:2251:2251)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~51) - (DELAY - (ABSOLUTE - (PORT dataa (1252:1252:1252) (1348:1348:1348)) - (PORT datab (1492:1492:1492) (1598:1598:1598)) - (PORT datac (1226:1226:1226) (1277:1277:1277)) - (PORT datad (1231:1231:1231) (1263:1263:1263)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (1906:1906:1906) (2000:2000:2000)) - (PORT datab (198:198:198) (238:238:238)) - (PORT datac (869:869:869) (926:926:926)) - (PORT datad (188:188:188) (220:220:220)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (621:621:621) (635:635:635)) - (PORT datab (219:219:219) (258:258:258)) - (PORT datac (898:898:898) (931:931:931)) - (PORT datad (816:816:816) (860:860:860)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (810:810:810) (881:881:881)) - (PORT datab (206:206:206) (246:246:246)) - (PORT datac (561:561:561) (575:575:575)) - (PORT datad (613:613:613) (668:668:668)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (844:844:844) (889:889:889)) - (PORT datac (208:208:208) (251:251:251)) - (PORT datad (202:202:202) (238:238:238)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (1311:1311:1311) (1368:1368:1368)) - (PORT datab (614:614:614) (640:640:640)) - (PORT datac (842:842:842) (872:872:872)) - (PORT datad (607:607:607) (635:635:635)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (1417:1417:1417) (1464:1464:1464)) - (PORT datab (910:910:910) (954:954:954)) - (PORT datac (1136:1136:1136) (1177:1177:1177)) - (PORT datad (1173:1173:1173) (1255:1255:1255)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla6M1T4_4) - (DELAY - (ABSOLUTE - (PORT dataa (1757:1757:1757) (1831:1831:1831)) - (PORT datab (836:836:836) (849:849:849)) - (PORT datac (2018:2018:2018) (2050:2050:2050)) - (PORT datad (2040:2040:2040) (2102:2102:2102)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~40) - (DELAY - (ABSOLUTE - (PORT dataa (927:927:927) (961:961:961)) - (PORT datab (1098:1098:1098) (1150:1150:1150)) - (PORT datad (194:194:194) (220:220:220)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (535:535:535) (566:566:566)) - (PORT datab (662:662:662) (694:694:694)) - (PORT datac (2000:2000:2000) (2031:2031:2031)) - (PORT datad (538:538:538) (549:549:549)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (242:242:242)) - (PORT datab (852:852:852) (924:924:924)) - (PORT datac (179:179:179) (214:214:214)) - (PORT datad (195:195:195) (221:221:221)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~38) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (244:244:244)) - (PORT datab (855:855:855) (863:863:863)) - (PORT datac (568:568:568) (591:591:591)) - (PORT datad (181:181:181) (209:209:209)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~93) - (DELAY - (ABSOLUTE - (PORT dataa (1191:1191:1191) (1227:1227:1227)) - (PORT datab (1050:1050:1050) (1057:1057:1057)) - (PORT datac (1185:1185:1185) (1207:1207:1207)) - (PORT datad (1343:1343:1343) (1388:1388:1388)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_de\~0) - (DELAY - (ABSOLUTE - (PORT dataa (249:249:249) (338:338:338)) - (PORT datab (223:223:223) (268:268:268)) - (PORT datac (337:337:337) (367:367:367)) - (PORT datad (1203:1203:1203) (1285:1285:1285)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_50) - (DELAY - (ABSOLUTE - (PORT datab (1384:1384:1384) (1432:1432:1432)) - (PORT datac (1179:1179:1179) (1200:1200:1200)) - (PORT datad (594:594:594) (610:610:610)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_70\~2) - (DELAY - (ABSOLUTE - (PORT datac (900:900:900) (943:943:943)) - (PORT datad (1328:1328:1328) (1383:1383:1383)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_66\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1165:1165:1165) (1261:1261:1261)) - (PORT datab (223:223:223) (270:270:270)) - (PORT datac (1141:1141:1141) (1178:1178:1178)) - (PORT datad (671:671:671) (721:721:721)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_38\~0) - (DELAY - (ABSOLUTE - (PORT dataa (704:704:704) (769:769:769)) - (PORT datab (1469:1469:1469) (1552:1552:1552)) - (PORT datac (1145:1145:1145) (1180:1180:1180)) - (PORT datad (199:199:199) (235:235:235)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_42\~0) - (DELAY - (ABSOLUTE - (PORT dataa (697:697:697) (766:766:766)) - (PORT datab (1471:1471:1471) (1557:1557:1557)) - (PORT datac (1138:1138:1138) (1176:1176:1176)) - (PORT datad (196:196:196) (232:232:232)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1346:1346:1346) (1411:1411:1411)) - (PORT datab (869:869:869) (903:903:903)) - (PORT datac (1807:1807:1807) (1896:1896:1896)) - (PORT datad (1570:1570:1570) (1608:1608:1608)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~10) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (205:205:205) (247:247:247)) - (PORT datad (868:868:868) (885:885:885)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~19) - (DELAY - (ABSOLUTE - (PORT dataa (981:981:981) (1092:1092:1092)) - (PORT datab (657:657:657) (681:681:681)) - (PORT datac (908:908:908) (975:975:975)) - (PORT datad (1438:1438:1438) (1536:1536:1536)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla37pla28M2T3_4) - (DELAY - (ABSOLUTE - (PORT dataa (1101:1101:1101) (1154:1154:1154)) - (PORT datab (701:701:701) (782:782:782)) - (PORT datac (1444:1444:1444) (1551:1551:1551)) - (PORT datad (1465:1465:1465) (1554:1554:1554)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_lo\~8) - (DELAY - (ABSOLUTE - (PORT dataa (601:601:601) (634:634:634)) - (PORT datab (206:206:206) (247:247:247)) - (PORT datac (622:622:622) (651:651:651)) - (PORT datad (1082:1082:1082) (1107:1107:1107)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (390:390:390) (419:419:419)) - (PORT datab (1179:1179:1179) (1229:1229:1229)) - (PORT datac (351:351:351) (380:380:380)) - (PORT datad (1087:1087:1087) (1108:1108:1108)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1246:1246:1246) (1335:1335:1335)) - (PORT datab (1577:1577:1577) (1714:1714:1714)) - (PORT datac (2188:2188:2188) (2312:2312:2312)) - (PORT datad (1069:1069:1069) (1164:1164:1164)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~5) - (DELAY - (ABSOLUTE - (PORT dataa (942:942:942) (1012:1012:1012)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (1253:1253:1253) (1293:1293:1293)) - (PORT datad (195:195:195) (220:220:220)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~6) - (DELAY - (ABSOLUTE - (PORT dataa (630:630:630) (660:660:660)) - (PORT datac (659:659:659) (688:688:688)) - (PORT datad (550:550:550) (559:559:559)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_78\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1144:1144:1144) (1180:1180:1180)) - (PORT datab (218:218:218) (265:265:265)) - (PORT datac (1135:1135:1135) (1168:1168:1168)) - (PORT datad (665:665:665) (712:712:712)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal21\~2) - (DELAY - (ABSOLUTE - (PORT dataa (916:916:916) (938:938:938)) - (PORT datab (900:900:900) (913:913:913)) - (PORT datac (920:920:920) (1008:1008:1008)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|bank_af\~0) - (DELAY - (ABSOLUTE - (PORT dataa (700:700:700) (751:751:751)) - (PORT datab (1166:1166:1166) (1198:1198:1198)) - (PORT datad (948:948:948) (968:968:968)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_control_\|bank_af) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1535:1535:1535)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1558:1558:1558)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_af\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1142:1142:1142) (1184:1184:1184)) - (PORT datab (248:248:248) (332:332:332)) - (PORT datac (1144:1144:1144) (1179:1179:1179)) - (PORT datad (672:672:672) (720:720:720)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_34) - (DELAY - (ABSOLUTE - (PORT dataa (682:682:682) (703:703:703)) - (PORT datab (1351:1351:1351) (1386:1386:1386)) - (PORT datad (908:908:908) (958:958:958)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_af2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1142:1142:1142) (1183:1183:1183)) - (PORT datab (250:250:250) (335:335:335)) - (PORT datac (1137:1137:1137) (1173:1173:1173)) - (PORT datad (664:664:664) (718:718:718)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_30) - (DELAY - (ABSOLUTE - (PORT dataa (1721:1721:1721) (1780:1780:1780)) - (PORT datab (1170:1170:1170) (1223:1223:1223)) - (PORT datad (792:792:792) (797:797:797)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~12) - (DELAY - (ABSOLUTE - (PORT dataa (709:709:709) (761:761:761)) - (PORT datab (914:914:914) (975:975:975)) - (PORT datac (1817:1817:1817) (1896:1896:1896)) - (PORT datad (1153:1153:1153) (1178:1178:1178)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1482:1482:1482) (1581:1581:1581)) - (PORT datac (1016:1016:1016) (1055:1055:1055)) - (PORT datad (321:321:321) (344:344:344)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1428:1428:1428) (1487:1487:1487)) - (PORT datab (1168:1168:1168) (1215:1215:1215)) - (PORT datac (2035:2035:2035) (2124:2124:2124)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1158:1158:1158) (1200:1200:1200)) - (PORT datab (2031:2031:2031) (2127:2127:2127)) - (PORT datac (969:969:969) (1020:1020:1020)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~24) - (DELAY - (ABSOLUTE - (PORT dataa (826:826:826) (902:902:902)) - (PORT datab (1517:1517:1517) (1560:1560:1560)) - (PORT datac (1294:1294:1294) (1324:1324:1324)) - (PORT datad (862:862:862) (880:880:880)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus\~13) - (DELAY - (ABSOLUTE - (PORT datab (229:229:229) (272:272:272)) - (PORT datac (202:202:202) (239:239:239)) - (PORT datad (202:202:202) (231:231:231)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_bus) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (1544:1544:1544) (1653:1653:1653)) - (PORT datac (208:208:208) (246:246:246)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~3) - (DELAY - (ABSOLUTE - (PORT dataa (587:587:587) (620:620:620)) - (PORT datab (876:876:876) (893:893:893)) - (PORT datac (1384:1384:1384) (1444:1444:1444)) - (PORT datad (1947:1947:1947) (1977:1977:1977)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (223:223:223) (266:266:266)) - (PORT datab (2017:2017:2017) (2075:2075:2075)) - (PORT datac (804:804:804) (827:827:827)) - (PORT datad (194:194:194) (220:220:220)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~2) - (DELAY - (ABSOLUTE - (PORT dataa (694:694:694) (740:740:740)) - (PORT datab (1445:1445:1445) (1514:1514:1514)) - (PORT datac (360:360:360) (389:389:389)) - (PORT datad (1121:1121:1121) (1177:1177:1177)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~3) - (DELAY - (ABSOLUTE - (PORT dataa (229:229:229) (277:277:277)) - (PORT datab (558:558:558) (578:578:578)) - (PORT datac (804:804:804) (818:818:818)) - (PORT datad (595:595:595) (633:633:633)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1170:1170:1170) (1229:1229:1229)) - (PORT datab (599:599:599) (614:614:614)) - (PORT datac (654:654:654) (698:698:698)) - (PORT datad (866:866:866) (893:893:893)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~5) - (DELAY - (ABSOLUTE - (PORT dataa (692:692:692) (737:737:737)) - (PORT datab (1195:1195:1195) (1210:1210:1210)) - (PORT datac (1157:1157:1157) (1193:1193:1193)) - (PORT datad (590:590:590) (602:602:602)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~4) - (DELAY - (ABSOLUTE - (PORT dataa (901:901:901) (936:936:936)) - (PORT datab (1199:1199:1199) (1253:1253:1253)) - (PORT datac (889:889:889) (931:931:931)) - (PORT datad (630:630:630) (687:687:687)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~7) - (DELAY - (ABSOLUTE - (PORT dataa (591:591:591) (601:601:601)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (172:172:172) (206:206:206)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~8) - (DELAY - (ABSOLUTE - (PORT dataa (921:921:921) (951:951:951)) - (PORT datab (1199:1199:1199) (1252:1252:1252)) - (PORT datac (361:361:361) (394:394:394)) - (PORT datad (1118:1118:1118) (1176:1176:1176)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1169:1169:1169) (1230:1230:1230)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (1158:1158:1158) (1196:1196:1196)) - (PORT datad (863:863:863) (892:892:892)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~10) - (DELAY - (ABSOLUTE - (PORT dataa (206:206:206) (252:252:252)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (652:652:652) (697:697:697)) - (PORT datad (845:845:845) (894:894:894)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (615:615:615) (637:637:637)) - (PORT datab (686:686:686) (707:707:707)) - (PORT datac (378:378:378) (410:410:410)) - (PORT datad (202:202:202) (230:230:230)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (607:607:607) (625:625:625)) - (PORT datac (530:530:530) (542:542:542)) - (PORT datad (838:838:838) (876:876:876)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~29) - (DELAY - (ABSOLUTE - (PORT dataa (929:929:929) (962:962:962)) - (PORT datab (1558:1558:1558) (1661:1661:1661)) - (PORT datac (1407:1407:1407) (1474:1474:1474)) - (PORT datad (200:200:200) (235:235:235)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~13) - (DELAY - (ABSOLUTE - (PORT dataa (619:619:619) (660:660:660)) - (PORT datab (965:965:965) (1060:1060:1060)) - (PORT datac (1732:1732:1732) (1835:1835:1835)) - (PORT datad (1150:1150:1150) (1179:1179:1179)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~49) - (DELAY - (ABSOLUTE - (PORT dataa (1102:1102:1102) (1150:1150:1150)) - (PORT datab (1473:1473:1473) (1583:1583:1583)) - (PORT datac (1614:1614:1614) (1681:1681:1681)) - (PORT datad (1173:1173:1173) (1219:1219:1219)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1405:1405:1405) (1418:1418:1418)) - (PORT datab (1241:1241:1241) (1276:1276:1276)) - (PORT datac (1251:1251:1251) (1275:1275:1275)) - (PORT datad (1260:1260:1260) (1298:1298:1298)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1121:1121:1121) (1151:1151:1151)) - (PORT datac (613:613:613) (636:636:636)) - (PORT datad (172:172:172) (197:197:197)) + (PORT dataa (514:514:514) (593:593:593)) + (PORT datac (268:268:268) (358:358:358)) + (PORT datad (2933:2933:2933) (3111:3111:3111)) (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~28) - (DELAY - (ABSOLUTE - (PORT dataa (236:236:236) (284:284:284)) - (PORT datab (219:219:219) (256:256:256)) - (PORT datac (1148:1148:1148) (1190:1190:1190)) - (PORT datad (194:194:194) (218:218:218)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~35) - (DELAY - (ABSOLUTE - (PORT datab (2004:2004:2004) (2134:2134:2134)) - (PORT datac (1351:1351:1351) (1365:1365:1365)) - (PORT datad (859:859:859) (872:872:872)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~36) - (DELAY - (ABSOLUTE - (PORT dataa (216:216:216) (267:267:267)) - (PORT datab (910:910:910) (941:941:941)) - (PORT datac (621:621:621) (645:645:645)) - (PORT datad (924:924:924) (962:962:962)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1513:1513:1513) (1596:1596:1596)) - (PORT datab (1166:1166:1166) (1202:1202:1202)) - (PORT datac (1104:1104:1104) (1142:1142:1142)) - (PORT datad (548:548:548) (560:560:560)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~31) - (DELAY - (ABSOLUTE - (PORT dataa (614:614:614) (650:650:650)) - (PORT datab (234:234:234) (278:278:278)) - (PORT datac (1132:1132:1132) (1164:1164:1164)) - (PORT datad (196:196:196) (222:222:222)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~29) - (DELAY - (ABSOLUTE - (PORT dataa (1646:1646:1646) (1763:1763:1763)) - (PORT datab (1008:1008:1008) (1101:1101:1101)) - (PORT datac (1033:1033:1033) (1107:1107:1107)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1164:1164:1164) (1208:1208:1208)) - (PORT datab (1537:1537:1537) (1621:1621:1621)) - (PORT datad (201:201:201) (229:229:229)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (888:888:888) (923:923:923)) - (PORT datab (570:570:570) (590:590:590)) - (PORT datac (603:603:603) (628:628:628)) - (PORT datad (595:595:595) (619:619:619)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal33\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1229:1229:1229) (1305:1305:1305)) - (PORT datab (1275:1275:1275) (1372:1372:1372)) - (PORT datac (1155:1155:1155) (1192:1192:1192)) - (PORT datad (709:709:709) (772:772:772)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~0) - (DELAY - (ABSOLUTE - (PORT dataa (690:690:690) (719:719:719)) - (PORT datab (1344:1344:1344) (1367:1367:1367)) - (PORT datac (1222:1222:1222) (1269:1269:1269)) - (PORT datad (1654:1654:1654) (1748:1748:1748)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1005:1005:1005) (1089:1089:1089)) - (PORT datab (887:887:887) (923:923:923)) - (PORT datac (170:170:170) (202:202:202)) - (PORT datad (221:221:221) (249:249:249)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we_lo\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1035:1035:1035) (1133:1133:1133)) - (PORT datac (2185:2185:2185) (2272:2272:2272)) - (PORT datad (654:654:654) (711:711:711)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we_lo\~3) - (DELAY - (ABSOLUTE - (PORT dataa (718:718:718) (782:782:782)) - (PORT datab (1135:1135:1135) (1159:1159:1159)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (1153:1153:1153) (1186:1186:1186)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_we_lo\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1016:1016:1016) (1112:1112:1112)) - (PORT datab (668:668:668) (685:685:685)) - (PORT datac (1012:1012:1012) (1113:1113:1113)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (255:255:255)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (180:180:180) (217:217:217)) - (PORT datad (933:933:933) (975:975:975)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_ir\~0) - (DELAY - (ABSOLUTE - (PORT datab (278:278:278) (366:366:366)) - (PORT datac (241:241:241) (319:319:319)) - (PORT datad (246:246:246) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_ir\~1) - (DELAY - (ABSOLUTE - (PORT dataa (941:941:941) (971:971:971)) - (PORT datab (218:218:218) (257:257:257)) - (PORT datac (1095:1095:1095) (1116:1116:1116)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1104:1104:1104) (1192:1192:1192)) - (PORT datab (219:219:219) (258:258:258)) - (PORT datac (650:650:650) (716:716:716)) - (PORT datad (966:966:966) (1077:1077:1077)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (2563:2563:2563) (2705:2705:2705)) - (PORT datab (1595:1595:1595) (1711:1711:1711)) - (PORT datac (194:194:194) (227:227:227)) - (PORT datad (218:218:218) (258:258:258)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1067:1067:1067) (1148:1148:1148)) - (PORT datab (204:204:204) (245:245:245)) - (PORT datac (880:880:880) (911:911:911)) - (PORT datad (824:824:824) (834:834:834)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_ixy_dT5_7) - (DELAY - (ABSOLUTE - (PORT datab (931:931:931) (1002:1002:1002)) - (PORT datad (625:625:625) (662:662:662)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~4) - (DELAY - (ABSOLUTE - (PORT dataa (627:627:627) (663:663:663)) - (PORT datab (924:924:924) (986:986:986)) - (PORT datac (1079:1079:1079) (1113:1113:1113)) - (PORT datad (201:201:201) (229:229:229)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~4) - (DELAY - (ABSOLUTE - (PORT dataa (882:882:882) (951:951:951)) - (PORT datab (902:902:902) (933:933:933)) - (PORT datac (628:628:628) (672:672:672)) - (PORT datad (883:883:883) (909:909:909)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla56M3T3_6) - (DELAY - (ABSOLUTE - (PORT dataa (1992:1992:1992) (2133:2133:2133)) - (PORT datab (907:907:907) (958:958:958)) - (PORT datac (224:224:224) (265:265:265)) - (PORT datad (1139:1139:1139) (1178:1178:1178)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~5) - (DELAY - (ABSOLUTE - (PORT dataa (930:930:930) (951:951:951)) - (PORT datab (917:917:917) (970:970:970)) - (PORT datac (879:879:879) (911:911:911)) - (PORT datad (593:593:593) (627:627:627)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~6) - (DELAY - (ABSOLUTE - (PORT dataa (901:901:901) (926:926:926)) - (PORT datad (181:181:181) (209:209:209)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1074:1074:1074) (1121:1121:1121)) - (PORT datab (894:894:894) (950:950:950)) - (PORT datac (601:601:601) (665:665:665)) - (PORT datad (855:855:855) (908:908:908)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\~16) - (DELAY - (ABSOLUTE - (PORT dataa (2419:2419:2419) (2569:2569:2569)) - (PORT datab (1823:1823:1823) (1925:1925:1925)) - (PORT datac (1074:1074:1074) (1067:1067:1067)) - (PORT datad (1576:1576:1576) (1735:1735:1735)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~11) - (DELAY - (ABSOLUTE - (PORT dataa (827:827:827) (849:849:849)) - (PORT datab (912:912:912) (944:944:944)) - (PORT datac (835:835:835) (868:868:868)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (2421:2421:2421) (2571:2571:2571)) - (PORT datab (2408:2408:2408) (2540:2540:2540)) - (PORT datac (1413:1413:1413) (1473:1473:1473)) - (PORT datad (1573:1573:1573) (1734:1734:1734)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~12) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (229:229:229) (272:272:272)) - (PORT datac (202:202:202) (241:241:241)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1252:1252:1252) (1310:1310:1310)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (832:832:832) (831:831:831)) - (PORT datad (872:872:872) (917:917:917)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (882:882:882) (898:898:898)) - (PORT datab (237:237:237) (281:281:281)) - (PORT datac (619:619:619) (671:671:671)) - (PORT datad (1350:1350:1350) (1391:1391:1391)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~38) - (DELAY - (ABSOLUTE - (PORT dataa (1228:1228:1228) (1318:1318:1318)) - (PORT datab (1384:1384:1384) (1497:1497:1497)) - (PORT datac (857:857:857) (917:917:917)) - (PORT datad (831:831:831) (860:860:860)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~0) - (DELAY - (ABSOLUTE - (PORT dataa (2065:2065:2065) (2136:2136:2136)) - (PORT datab (2504:2504:2504) (2706:2706:2706)) - (PORT datac (2886:2886:2886) (3058:3058:3058)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~24) - (DELAY - (ABSOLUTE - (PORT datab (845:845:845) (894:894:894)) - (PORT datac (990:990:990) (1030:1030:1030)) - (PORT datad (1379:1379:1379) (1425:1425:1425)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (217:217:217) (268:268:268)) - (PORT datac (663:663:663) (700:700:700)) - (PORT datad (1031:1031:1031) (1094:1094:1094)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1328:1328:1328) (1447:1447:1447)) - (PORT datac (1179:1179:1179) (1239:1239:1239)) - (PORT datad (2024:2024:2024) (2146:2146:2146)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1112:1112:1112) (1166:1166:1166)) - (PORT datab (226:226:226) (266:266:266)) - (PORT datac (604:604:604) (622:622:622)) - (PORT datad (1151:1151:1151) (1191:1191:1191)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1111:1111:1111) (1230:1230:1230)) - (PORT datac (1131:1131:1131) (1168:1168:1168)) - (PORT datad (957:957:957) (1017:1017:1017)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3) - (DELAY - (ABSOLUTE - (PORT datab (2109:2109:2109) (2224:2224:2224)) - (PORT datac (925:925:925) (983:983:983)) - (PORT datad (1982:1982:1982) (2072:2072:2072)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (1189:1189:1189) (1250:1250:1250)) - (PORT datab (599:599:599) (617:617:617)) - (PORT datac (871:871:871) (913:913:913)) - (PORT datad (1143:1143:1143) (1193:1193:1193)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (1120:1120:1120) (1154:1154:1154)) - (PORT datab (595:595:595) (609:609:609)) - (PORT datac (1115:1115:1115) (1174:1174:1174)) - (PORT datad (878:878:878) (910:910:910)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1801:1801:1801) (1843:1843:1843)) - (PORT datab (1573:1573:1573) (1608:1608:1608)) - (PORT datad (985:985:985) (1020:1020:1020)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (925:925:925) (957:957:957)) - (PORT datab (1162:1162:1162) (1232:1232:1232)) - (PORT datac (1480:1480:1480) (1554:1554:1554)) - (PORT datad (1102:1102:1102) (1119:1119:1119)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (702:702:702) (740:740:740)) - (PORT datab (913:913:913) (942:942:942)) - (PORT datac (618:618:618) (642:642:642)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (241:241:241)) - (PORT datab (198:198:198) (236:236:236)) - (PORT datac (1512:1512:1512) (1540:1540:1540)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (926:926:926) (959:959:959)) - (PORT datab (887:887:887) (953:953:953)) - (PORT datac (185:185:185) (226:226:226)) - (PORT datad (885:885:885) (902:902:902)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (198:198:198) (241:241:241)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (1725:1725:1725) (1783:1783:1783)) - (PORT datad (330:330:330) (351:351:351)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (1198:1198:1198) (1240:1240:1240)) - (PORT datab (835:835:835) (861:861:861)) - (PORT datac (841:841:841) (865:865:865)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1551:1551:1551) (1610:1610:1610)) - (PORT datab (1763:1763:1763) (1826:1826:1826)) - (PORT datac (2606:2606:2606) (2704:2704:2704)) - (PORT datad (1157:1157:1157) (1177:1177:1177)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (2641:2641:2641) (2744:2744:2744)) - (PORT datab (1587:1587:1587) (1722:1722:1722)) - (PORT datac (639:639:639) (659:659:659)) - (PORT datad (202:202:202) (233:233:233)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (615:615:615) (638:638:638)) - (PORT datab (653:653:653) (683:683:683)) - (PORT datac (637:637:637) (684:684:684)) - (PORT datad (847:847:847) (906:906:906)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_62) - (DELAY - (ABSOLUTE - (PORT datab (707:707:707) (739:739:739)) - (PORT datac (1055:1055:1055) (1068:1068:1068)) - (PORT datad (921:921:921) (956:956:956)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~38) - (DELAY - (ABSOLUTE - (PORT dataa (356:356:356) (401:401:401)) - (PORT datab (1114:1114:1114) (1146:1146:1146)) - (PORT datac (1038:1038:1038) (1080:1080:1080)) - (PORT datad (853:853:853) (854:854:854)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~39) - (DELAY - (ABSOLUTE - (PORT dataa (1748:1748:1748) (1768:1768:1768)) - (PORT datab (881:881:881) (907:907:907)) - (PORT datac (1501:1501:1501) (1630:1630:1630)) - (PORT datad (1129:1129:1129) (1199:1199:1199)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~30) - (DELAY - (ABSOLUTE - (PORT dataa (1137:1137:1137) (1170:1170:1170)) - (PORT datab (1651:1651:1651) (1721:1721:1721)) - (PORT datac (1148:1148:1148) (1186:1186:1186)) - (PORT datad (212:212:212) (247:247:247)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~45) - (DELAY - (ABSOLUTE - (PORT dataa (671:671:671) (702:702:702)) - (PORT datab (1148:1148:1148) (1207:1207:1207)) - (PORT datac (1182:1182:1182) (1237:1237:1237)) - (PORT datad (969:969:969) (1043:1043:1043)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~1) - (DELAY - (ABSOLUTE - (PORT dataa (294:294:294) (365:365:365)) - (PORT datac (1702:1702:1702) (1757:1757:1757)) - (PORT datad (437:437:437) (482:482:482)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~36) - (DELAY - (ABSOLUTE - (PORT dataa (661:661:661) (685:685:685)) - (PORT datab (1154:1154:1154) (1208:1208:1208)) - (PORT datac (1484:1484:1484) (1544:1544:1544)) - (PORT datad (1270:1270:1270) (1331:1331:1331)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~27) - (DELAY - (ABSOLUTE - (PORT dataa (1443:1443:1443) (1501:1501:1501)) - (PORT datab (912:912:912) (961:961:961)) - (PORT datac (896:896:896) (925:925:925)) - (PORT datad (962:962:962) (988:988:988)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~28) - (DELAY - (ABSOLUTE - (PORT dataa (874:874:874) (897:897:897)) - (PORT datac (992:992:992) (1045:1045:1045)) - (PORT datad (172:172:172) (198:198:198)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~37) - (DELAY - (ABSOLUTE - (PORT dataa (1066:1066:1066) (1139:1139:1139)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (1089:1089:1089) (1116:1116:1116)) - (PORT datad (180:180:180) (208:208:208)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~40) - (DELAY - (ABSOLUTE - (PORT dataa (347:347:347) (374:374:374)) - (PORT datab (196:196:196) (234:234:234)) - (PORT datac (345:345:345) (385:385:385)) - (PORT datad (858:858:858) (866:866:866)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~35) - (DELAY - (ABSOLUTE - (PORT dataa (1408:1408:1408) (1444:1444:1444)) - (PORT datab (814:814:814) (844:844:844)) - (PORT datac (1711:1711:1711) (1730:1730:1730)) - (PORT datad (911:911:911) (949:949:949)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~77) - (DELAY - (ABSOLUTE - (PORT dataa (1097:1097:1097) (1124:1124:1124)) - (PORT datab (662:662:662) (693:693:693)) - (PORT datac (868:868:868) (892:892:892)) - (PORT datad (871:871:871) (914:914:914)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~32) - (DELAY - (ABSOLUTE - (PORT dataa (228:228:228) (275:275:275)) - (PORT datab (642:642:642) (663:663:663)) - (PORT datac (1367:1367:1367) (1431:1431:1431)) - (PORT datad (1132:1132:1132) (1158:1158:1158)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla91pla21M4T2_3\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1647:1647:1647) (1764:1764:1764)) - (PORT datab (1009:1009:1009) (1098:1098:1098)) - (PORT datac (1939:1939:1939) (1965:1965:1965)) - (PORT datad (1664:1664:1664) (1726:1726:1726)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~33) - (DELAY - (ABSOLUTE - (PORT dataa (220:220:220) (264:264:264)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (170:170:170) (203:203:203)) - (PORT datad (646:646:646) (703:703:703)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~34) - (DELAY - (ABSOLUTE - (PORT dataa (223:223:223) (275:275:275)) - (PORT datab (645:645:645) (669:669:669)) - (PORT datac (199:199:199) (236:236:236)) - (PORT datad (1191:1191:1191) (1215:1215:1215)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~41) - (DELAY - (ABSOLUTE - (PORT dataa (198:198:198) (241:241:241)) - (PORT datab (1028:1028:1028) (1084:1084:1084)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (593:593:593) (617:617:617)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~10) - (DELAY - (ABSOLUTE - (PORT dataa (896:896:896) (960:960:960)) - (PORT datab (1128:1128:1128) (1156:1156:1156)) - (PORT datac (886:886:886) (918:918:918)) - (PORT datad (1142:1142:1142) (1198:1198:1198)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~11) - (DELAY - (ABSOLUTE - (PORT datab (218:218:218) (256:256:256)) - (PORT datac (593:593:593) (653:653:653)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~3) - (DELAY - (ABSOLUTE - (PORT dataa (214:214:214) (264:264:264)) - (PORT datac (557:557:557) (571:571:571)) - (PORT datad (812:812:812) (882:882:882)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1301:1301:1301) (1363:1363:1363)) - (PORT datab (670:670:670) (695:695:695)) - (PORT datac (195:195:195) (228:228:228)) - (PORT datad (1179:1179:1179) (1216:1216:1216)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~2) - (DELAY - (ABSOLUTE - (PORT dataa (565:565:565) (585:585:585)) - (PORT datac (793:793:793) (849:849:849)) - (PORT datad (781:781:781) (835:835:835)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~5) - (DELAY - (ABSOLUTE - (PORT dataa (914:914:914) (932:932:932)) - (PORT datab (670:670:670) (713:713:713)) - (PORT datac (371:371:371) (406:406:406)) - (PORT datad (595:595:595) (643:643:643)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~45) - (DELAY - (ABSOLUTE - (PORT dataa (627:627:627) (677:677:677)) - (PORT datab (867:867:867) (880:880:880)) - (PORT datac (866:866:866) (892:892:892)) - (PORT datad (646:646:646) (680:680:680)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~46) - (DELAY - (ABSOLUTE - (PORT datab (821:821:821) (842:842:842)) - (PORT datac (201:201:201) (237:237:237)) - (PORT datad (1425:1425:1425) (1509:1509:1509)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~1) - (DELAY - (ABSOLUTE - (PORT dataa (599:599:599) (610:610:610)) - (PORT datab (926:926:926) (956:956:956)) - (PORT datac (586:586:586) (596:596:596)) - (PORT datad (582:582:582) (613:613:613)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~0) - (DELAY - (ABSOLUTE - (PORT dataa (970:970:970) (1011:1011:1011)) - (PORT datab (1561:1561:1561) (1659:1659:1659)) - (PORT datac (842:842:842) (876:876:876)) - (PORT datad (371:371:371) (400:400:400)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_4d\~6) - (DELAY - (ABSOLUTE - (PORT dataa (207:207:207) (251:251:251)) - (PORT datab (340:340:340) (371:371:371)) - (PORT datac (211:211:211) (252:252:252)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~4) - (DELAY - (ABSOLUTE - (PORT dataa (926:926:926) (963:963:963)) - (PORT datac (857:857:857) (921:921:921)) - (PORT datad (828:828:828) (859:859:859)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~16) - (DELAY - (ABSOLUTE - (PORT dataa (646:646:646) (681:681:681)) - (PORT datab (1486:1486:1486) (1550:1550:1550)) - (PORT datac (820:820:820) (856:856:856)) - (PORT datad (815:815:815) (871:871:871)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~14) - (DELAY - (ABSOLUTE - (PORT dataa (446:446:446) (504:504:504)) - (PORT datab (946:946:946) (986:986:986)) - (PORT datac (374:374:374) (405:405:405)) - (PORT datad (1915:1915:1915) (2040:2040:2040)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~20) - (DELAY - (ABSOLUTE - (PORT dataa (2472:2472:2472) (2661:2661:2661)) - (PORT datab (554:554:554) (575:575:575)) - (PORT datac (892:892:892) (956:956:956)) - (PORT datad (1125:1125:1125) (1142:1142:1142)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~15) - (DELAY - (ABSOLUTE - (PORT dataa (644:644:644) (677:677:677)) - (PORT datab (581:581:581) (596:596:596)) - (PORT datac (785:785:785) (834:834:834)) - (PORT datad (202:202:202) (230:230:230)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~17) - (DELAY - (ABSOLUTE - (PORT dataa (587:587:587) (619:619:619)) - (PORT datab (876:876:876) (893:893:893)) - (PORT datac (1988:1988:1988) (2046:2046:2046)) - (PORT datad (596:596:596) (620:620:620)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1153:1153:1153) (1167:1167:1167)) - (PORT datab (1567:1567:1567) (1688:1688:1688)) - (PORT datac (635:635:635) (692:692:692)) - (PORT datad (604:604:604) (642:642:642)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~19) - (DELAY - (ABSOLUTE - (PORT dataa (887:887:887) (914:914:914)) - (PORT datab (562:562:562) (571:571:571)) - (PORT datac (611:611:611) (649:649:649)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_pc\~3) - (DELAY - (ABSOLUTE - (PORT dataa (628:628:628) (663:663:663)) - (PORT datab (925:925:925) (986:986:986)) - (PORT datac (532:532:532) (538:538:538)) - (PORT datad (873:873:873) (880:880:880)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_pc) - (DELAY - (ABSOLUTE - (PORT dataa (230:230:230) (276:276:276)) - (PORT datab (643:643:643) (675:675:675)) - (PORT datac (842:842:842) (864:864:864)) - (PORT datad (344:344:344) (366:366:366)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_74) - (DELAY - (ABSOLUTE - (PORT datab (1438:1438:1438) (1508:1508:1508)) - (PORT datac (915:915:915) (945:945:945)) - (PORT datad (819:819:819) (835:835:835)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (229:229:229) (275:275:275)) - (PORT datab (1330:1330:1330) (1334:1334:1334)) - (PORT datac (1375:1375:1375) (1393:1393:1393)) - (PORT datad (312:312:312) (330:330:330)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_75) - (DELAY - (ABSOLUTE - (PORT datab (949:949:949) (999:999:999)) - (PORT datac (1439:1439:1439) (1498:1498:1498)) - (PORT datad (671:671:671) (702:702:702)) - (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -11214,193 +1418,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (974:974:974) (1028:1028:1028)) - (PORT ena (1201:1201:1201) (1184:1184:1184)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (1880:1880:1880) (1905:1905:1905)) - (PORT datab (702:702:702) (730:730:730)) - (PORT datad (1198:1198:1198) (1238:1238:1238)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_63) - (DELAY - (ABSOLUTE - (PORT datab (709:709:709) (737:737:737)) - (PORT datac (1057:1057:1057) (1070:1070:1070)) - (PORT datad (923:923:923) (954:954:954)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[7\]) + (INSTANCE z80_\|interrupts_\|iff1) (DELAY (ABSOLUTE (PORT clk (1541:1541:1541) (1557:1557:1557)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1283:1283:1283) (1286:1286:1286)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~23) - (DELAY - (ABSOLUTE - (PORT datab (738:738:738) (772:772:772)) - (PORT datac (609:609:609) (659:659:659)) - (PORT datad (217:217:217) (286:286:286)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_10\~0) - (DELAY - (ABSOLUTE - (PORT datac (1990:1990:1990) (2095:2095:2095)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_10) - (DELAY - (ABSOLUTE - (PORT clk (1548:1548:1548) (1550:1550:1550)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_9) - (DELAY - (ABSOLUTE - (PORT clk (1548:1548:1548) (1550:1550:1550)) - (PORT asdata (567:567:567) (646:646:646)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|resets_\|DFFE_intr_ff3) - (DELAY - (ABSOLUTE - (PORT clk (1548:1548:1548) (1550:1550:1550)) - (PORT asdata (569:569:569) (648:648:648)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_io_ibuf") - (INSTANCE KEY\[0\]\~input) - (DELAY - (ABSOLUTE - (IOPATH i o (481:481:481) (733:733:733)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE reset) - (DELAY - (ABSOLUTE - (PORT datac (1566:1566:1566) (1527:1527:1527)) - (PORT datad (531:531:531) (524:524:524)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|resets_\|x1\~0) - (DELAY - (ABSOLUTE - (PORT datad (1474:1474:1474) (1549:1549:1549)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|fpga_reset) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1542:1542:1542)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_clkctrl") - (INSTANCE z80_\|fpga_reset\~clkctrl) - (DELAY - (ABSOLUTE - (PORT inclk[0] (727:727:727) (752:752:752)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|resets_\|x1) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1527:1527:1527)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1883:1883:1883) (1869:1869:1869)) + (PORT clrn (1224:1224:1224) (1261:1261:1261)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -11409,1430 +1432,6 @@ (HOLD d (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|resets_\|clrpc_int\~0) - (DELAY - (ABSOLUTE - (PORT dataa (649:649:649) (728:728:728)) - (PORT datab (605:605:605) (665:665:665)) - (PORT datad (1168:1168:1168) (1217:1217:1217)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|resets_\|clrpc_int) - (DELAY - (ABSOLUTE - (PORT clk (1548:1548:1548) (1550:1550:1550)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1597:1597:1597) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|resets_\|clrpc\~0) - (DELAY - (ABSOLUTE - (PORT dataa (251:251:251) (340:340:340)) - (PORT datab (253:253:253) (339:339:339)) - (PORT datad (217:217:217) (285:285:285)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[7\]) - (DELAY - (ABSOLUTE - (PORT datac (657:657:657) (695:695:695)) - (PORT datad (609:609:609) (638:638:638)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_apin_mux\~1) - (DELAY - (ABSOLUTE - (PORT dataa (2470:2470:2470) (2664:2664:2664)) - (PORT datac (891:891:891) (959:959:959)) - (PORT datad (1997:1997:1997) (2087:2087:2087)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (364:364:364) (394:394:394)) - (PORT datab (558:558:558) (580:580:580)) - (PORT datac (844:844:844) (879:879:879)) - (PORT datad (1124:1124:1124) (1141:1141:1141)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1113:1113:1113) (1149:1149:1149)) - (PORT datab (1162:1162:1162) (1184:1184:1184)) - (PORT datac (794:794:794) (810:810:810)) - (PORT datad (642:642:642) (654:654:654)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (985:985:985) (1053:1053:1053)) - (PORT datab (1645:1645:1645) (1657:1657:1657)) - (PORT datac (173:173:173) (207:207:207)) - (PORT datad (1141:1141:1141) (1167:1167:1167)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_oe\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1232:1232:1232) (1303:1303:1303)) - (PORT datab (1001:1001:1001) (1111:1111:1111)) - (PORT datac (655:655:655) (722:722:722)) - (PORT datad (1242:1242:1242) (1330:1330:1330)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~9) - (DELAY - (ABSOLUTE - (PORT dataa (789:789:789) (798:798:798)) - (PORT datab (653:653:653) (676:676:676)) - (PORT datac (834:834:834) (870:870:870)) - (PORT datad (1032:1032:1032) (1091:1091:1091)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~10) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (714:714:714) (749:749:749)) - (PORT datac (201:201:201) (236:236:236)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~11) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (246:246:246)) - (PORT datac (180:180:180) (218:218:218)) - (PORT datad (538:538:538) (562:562:562)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_al_we\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1254:1254:1254) (1307:1307:1307)) - (PORT datab (845:845:845) (854:854:854)) - (PORT datac (835:835:835) (832:832:832)) - (PORT datad (874:874:874) (917:917:917)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1560:1560:1560)) - (PORT ena (2152:2152:2152) (2220:2220:2220)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~6) - (DELAY - (ABSOLUTE - (PORT dataa (407:407:407) (434:434:434)) - (PORT datab (1814:1814:1814) (1895:1895:1895)) - (PORT datac (201:201:201) (236:236:236)) - (PORT datad (644:644:644) (699:699:699)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1218:1218:1218) (1307:1307:1307)) - (PORT datab (2009:2009:2009) (2129:2129:2129)) - (PORT datac (1296:1296:1296) (1407:1407:1407)) - (PORT datad (2028:2028:2028) (2149:2149:2149)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~8) - (DELAY - (ABSOLUTE - (PORT dataa (384:384:384) (412:412:412)) - (PORT datab (213:213:213) (258:258:258)) - (PORT datac (1100:1100:1100) (1149:1149:1149)) - (PORT datad (1205:1205:1205) (1229:1229:1229)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~9) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (265:265:265)) - (PORT datab (1709:1709:1709) (1797:1797:1797)) - (PORT datac (549:549:549) (562:562:562)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~10) - (DELAY - (ABSOLUTE - (PORT datab (988:988:988) (1021:1021:1021)) - (PORT datac (1126:1126:1126) (1145:1145:1145)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1002:1002:1002) (1072:1072:1072)) - (PORT datad (1126:1126:1126) (1143:1143:1143)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1541:1541:1541) (1557:1557:1557)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1283:1283:1283) (1286:1286:1286)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_54) - (DELAY - (ABSOLUTE - (PORT datab (1546:1546:1546) (1602:1602:1602)) - (PORT datac (1206:1206:1206) (1268:1268:1268)) - (PORT datad (1073:1073:1073) (1099:1099:1099)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_58) - (DELAY - (ABSOLUTE - (PORT datab (1543:1543:1543) (1602:1602:1602)) - (PORT datac (1215:1215:1215) (1279:1279:1279)) - (PORT datad (985:985:985) (1033:1033:1033)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_55) - (DELAY - (ABSOLUTE - (PORT datab (1542:1542:1542) (1602:1602:1602)) - (PORT datac (1217:1217:1217) (1279:1279:1279)) - (PORT datad (1074:1074:1074) (1100:1100:1100)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1531:1531:1531)) - (PORT asdata (1413:1413:1413) (1448:1448:1448)) - (PORT ena (1734:1734:1734) (1719:1719:1719)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_59) - (DELAY - (ABSOLUTE - (PORT datab (1547:1547:1547) (1607:1607:1607)) - (PORT datac (1199:1199:1199) (1261:1261:1261)) - (PORT datad (990:990:990) (1037:1037:1037)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1531:1531:1531)) - (PORT asdata (1413:1413:1413) (1447:1447:1447)) - (PORT ena (1413:1413:1413) (1385:1385:1385)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (870:870:870) (916:916:916)) - (PORT datab (971:971:971) (1024:1024:1024)) - (PORT datad (215:215:215) (283:283:283)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_51) - (DELAY - (ABSOLUTE - (PORT datab (1381:1381:1381) (1428:1428:1428)) - (PORT datac (1185:1185:1185) (1207:1207:1207)) - (PORT datad (589:589:589) (605:605:605)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (726:726:726) (753:753:753)) - (PORT ena (811:811:811) (804:804:804)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_de2\~4) - (DELAY - (ABSOLUTE - (PORT dataa (372:372:372) (407:407:407)) - (PORT datab (224:224:224) (272:272:272)) - (PORT datac (222:222:222) (301:301:301)) - (PORT datad (1218:1218:1218) (1299:1299:1299)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_46) - (DELAY - (ABSOLUTE - (PORT datab (1209:1209:1209) (1234:1234:1234)) - (PORT datac (637:637:637) (665:665:665)) - (PORT datad (1346:1346:1346) (1393:1393:1393)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_47) - (DELAY - (ABSOLUTE - (PORT datab (1212:1212:1212) (1239:1239:1239)) - (PORT datac (637:637:637) (665:665:665)) - (PORT datad (1342:1342:1342) (1391:1391:1391)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (725:725:725) (752:752:752)) - (PORT ena (841:841:841) (846:846:846)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (244:244:244) (331:331:331)) - (PORT datab (261:261:261) (314:314:314)) - (PORT datad (232:232:232) (270:270:270)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_71\~2) - (DELAY - (ABSOLUTE - (PORT datac (898:898:898) (941:941:941)) - (PORT datad (1326:1326:1326) (1381:1381:1381)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_43\~0) - (DELAY - (ABSOLUTE - (PORT dataa (699:699:699) (770:770:770)) - (PORT datab (1175:1175:1175) (1215:1215:1215)) - (PORT datac (195:195:195) (238:238:238)) - (PORT datad (1436:1436:1436) (1519:1519:1519)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1520:1520:1520) (1534:1534:1534)) - (PORT asdata (1192:1192:1192) (1227:1227:1227)) - (PORT ena (1263:1263:1263) (1264:1264:1264)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_39\~0) - (DELAY - (ABSOLUTE - (PORT dataa (695:695:695) (765:765:765)) - (PORT datab (1172:1172:1172) (1214:1214:1214)) - (PORT datac (195:195:195) (237:237:237)) - (PORT datad (1438:1438:1438) (1518:1518:1518)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1520:1520:1520) (1534:1534:1534)) - (PORT asdata (1193:1193:1193) (1225:1225:1225)) - (PORT ena (1207:1207:1207) (1190:1190:1190)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (467:467:467) (505:505:505)) - (PORT datab (241:241:241) (323:323:323)) - (PORT datad (640:640:640) (663:663:663)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_83) - (DELAY - (ABSOLUTE - (PORT dataa (628:628:628) (658:658:658)) - (PORT datab (950:950:950) (994:994:994)) - (PORT datad (672:672:672) (698:698:698)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1544:1544:1544)) - (PORT asdata (1673:1673:1673) (1678:1678:1678)) - (PORT ena (1499:1499:1499) (1507:1507:1507)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (656:656:656) (674:674:674)) - (PORT datab (1409:1409:1409) (1424:1424:1424)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_79\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1144:1144:1144) (1180:1180:1180)) - (PORT datab (1171:1171:1171) (1213:1213:1213)) - (PORT datac (195:195:195) (238:238:238)) - (PORT datad (664:664:664) (715:715:715)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1545:1545:1545)) - (PORT asdata (1225:1225:1225) (1263:1263:1263)) - (PORT ena (1220:1220:1220) (1214:1214:1214)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~39) - (DELAY - (ABSOLUTE - (PORT dataa (911:911:911) (962:962:962)) - (PORT datab (414:414:414) (473:473:473)) - (PORT datac (913:913:913) (963:963:963)) - (PORT datad (609:609:609) (629:629:629)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sel_iy\~2) - (DELAY - (ABSOLUTE - (PORT dataa (896:896:896) (973:973:973)) - (PORT datab (938:938:938) (1019:1019:1019)) - (PORT datac (1135:1135:1135) (1179:1179:1179)) - (PORT datad (378:378:378) (412:412:412)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_70) - (DELAY - (ABSOLUTE - (PORT datab (929:929:929) (993:993:993)) - (PORT datac (1324:1324:1324) (1357:1357:1357)) - (PORT datad (891:891:891) (947:947:947)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_67\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1168:1168:1168) (1265:1265:1265)) - (PORT datab (1178:1178:1178) (1216:1216:1216)) - (PORT datac (195:195:195) (239:239:239)) - (PORT datad (671:671:671) (719:719:719)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1544:1544:1544)) - (PORT asdata (1674:1674:1674) (1676:1676:1676)) - (PORT ena (1231:1231:1231) (1217:1217:1217)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_71) - (DELAY - (ABSOLUTE - (PORT dataa (1791:1791:1791) (1805:1805:1805)) - (PORT datab (916:916:916) (986:986:986)) - (PORT datad (905:905:905) (958:958:958)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1545:1545:1545)) - (PORT asdata (1226:1226:1226) (1265:1265:1265)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~38) - (DELAY - (ABSOLUTE - (PORT dataa (433:433:433) (465:465:465)) - (PORT datab (634:634:634) (665:665:665)) - (PORT datad (357:357:357) (410:410:410)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_31) - (DELAY - (ABSOLUTE - (PORT dataa (1721:1721:1721) (1780:1780:1780)) - (PORT datab (1171:1171:1171) (1225:1225:1225)) - (PORT datad (792:792:792) (797:797:797)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1545:1545:1545)) - (PORT asdata (1407:1407:1407) (1434:1434:1434)) - (PORT ena (821:821:821) (834:834:834)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (841:841:841) (868:868:868)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_35) - (DELAY - (ABSOLUTE - (PORT datab (1032:1032:1032) (1065:1065:1065)) - (PORT datac (905:905:905) (951:951:951)) - (PORT datad (876:876:876) (937:937:937)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1266:1266:1266) (1269:1269:1269)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (407:407:407) (468:468:468)) - (PORT datab (590:590:590) (630:630:630)) - (PORT datad (216:216:216) (284:284:284)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~40) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (200:200:200) (239:239:239)) - (PORT datac (170:170:170) (203:203:203)) - (PORT datad (530:530:530) (540:540:540)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~41) - (DELAY - (ABSOLUTE - (PORT dataa (658:658:658) (699:699:699)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datad (780:780:780) (810:810:810)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~42) - (DELAY - (ABSOLUTE - (PORT dataa (373:373:373) (397:397:397)) - (PORT datab (625:625:625) (654:654:654)) - (PORT datac (1393:1393:1393) (1416:1416:1416)) - (PORT datad (618:618:618) (673:673:673)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (1402:1402:1402) (1441:1441:1441)) - (PORT ena (1201:1201:1201) (1184:1184:1184)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (220:220:220) (264:264:264)) - (PORT datab (1232:1232:1232) (1270:1270:1270)) - (PORT datad (658:658:658) (688:688:688)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~8) - (DELAY - (ABSOLUTE - (PORT datab (671:671:671) (703:703:703)) - (PORT datac (1147:1147:1147) (1188:1188:1188)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1541:1541:1541) (1557:1557:1557)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1283:1283:1283) (1286:1286:1286)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (1460:1460:1460) (1492:1492:1492)) - (PORT ena (811:811:811) (804:804:804)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (1460:1460:1460) (1491:1491:1491)) - (PORT ena (841:841:841) (846:846:846)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (244:244:244) (331:331:331)) - (PORT datab (262:262:262) (315:315:315)) - (PORT datad (233:233:233) (271:271:271)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1514:1514:1514) (1528:1528:1528)) - (PORT asdata (1185:1185:1185) (1213:1213:1213)) - (PORT ena (816:816:816) (813:813:813)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|db\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1182:1182:1182) (1227:1227:1227)) - (PORT datab (1541:1541:1541) (1602:1602:1602)) - (PORT datad (1074:1074:1074) (1100:1100:1100)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1531:1531:1531)) - (PORT asdata (1483:1483:1483) (1519:1519:1519)) - (PORT ena (1413:1413:1413) (1385:1385:1385)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (639:639:639) (688:688:688)) - (PORT datab (1088:1088:1088) (1097:1097:1097)) - (PORT datad (940:940:940) (980:980:980)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1545:1545:1545)) - (PORT asdata (1236:1236:1236) (1247:1247:1247)) - (PORT ena (1220:1220:1220) (1214:1214:1214)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1545:1545:1545)) - (PORT asdata (1237:1237:1237) (1246:1246:1246)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (641:641:641) (696:696:696)) - (PORT datab (241:241:241) (323:323:323)) - (PORT datad (367:367:367) (395:395:395)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1534:1534:1534)) - (PORT asdata (1461:1461:1461) (1534:1534:1534)) - (PORT ena (1505:1505:1505) (1518:1518:1518)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (347:347:347) (372:372:372)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1520:1520:1520) (1534:1534:1534)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1263:1263:1263) (1264:1264:1264)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1534:1534:1534)) - (PORT asdata (1458:1458:1458) (1530:1530:1530)) - (PORT ena (1407:1407:1407) (1382:1382:1382)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (430:430:430) (499:499:499)) - (PORT datab (652:652:652) (676:676:676)) - (PORT datad (827:827:827) (837:837:837)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1212:1212:1212) (1256:1256:1256)) - (PORT datab (919:919:919) (944:944:944)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1520:1520:1520) (1534:1534:1534)) - (PORT asdata (939:939:939) (964:964:964)) - (PORT ena (1207:1207:1207) (1190:1190:1190)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (455:455:455) (491:491:491)) - (PORT datab (1133:1133:1133) (1178:1178:1178)) - (PORT datad (539:539:539) (559:559:559)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1545:1545:1545)) - (PORT asdata (1719:1719:1719) (1765:1765:1765)) - (PORT ena (821:821:821) (834:834:834)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1545:1545:1545)) - (PORT asdata (1719:1719:1719) (1768:1768:1768)) - (PORT ena (1266:1266:1266) (1269:1269:1269)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (412:412:412) (470:470:470)) - (PORT datab (585:585:585) (623:623:623)) - (PORT datad (216:216:216) (283:283:283)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (607:607:607) (635:635:635)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (344:344:344) (368:368:368)) - (PORT datad (597:597:597) (607:607:607)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (1201:1201:1201) (1235:1235:1235)) - (PORT datab (197:197:197) (237:237:237)) - (PORT datac (1104:1104:1104) (1151:1151:1151)) - (PORT datad (820:820:820) (839:839:839)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (1589:1589:1589) (1608:1608:1608)) - (PORT ena (1201:1201:1201) (1184:1184:1184)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1178:1178:1178) (1198:1198:1198)) - (PORT datab (697:697:697) (724:724:724)) - (PORT datad (1194:1194:1194) (1230:1230:1230)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~1) - (DELAY - (ABSOLUTE - (PORT datab (243:243:243) (325:325:325)) - (PORT datac (706:706:706) (737:737:737)) - (PORT datad (842:842:842) (876:876:876)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~72) - (DELAY - (ABSOLUTE - (PORT dataa (938:938:938) (985:985:985)) - (PORT datab (912:912:912) (985:985:985)) - (PORT datac (1500:1500:1500) (1547:1547:1547)) - (PORT datad (662:662:662) (730:730:730)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_clkctrl") (INSTANCE ula_\|pll_\|altpll_component\|auto_generated\|wire_pll1_clk\[0\]\~clkctrl) @@ -12842,103 +1441,12 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add0\~14) - (DELAY - (ABSOLUTE - (PORT datab (1393:1393:1393) (1462:1462:1462)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datab cout (446:446:446) (318:318:318)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add0\~16) - (DELAY - (ABSOLUTE - (PORT dataa (265:265:265) (352:352:352)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH dataa cout (436:436:436) (315:315:315)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vga_hc\~2) - (DELAY - (ABSOLUTE - (PORT datac (830:830:830) (872:872:872)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_hc\[8\]) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add0\~18) - (DELAY - (ABSOLUTE - (PORT datad (660:660:660) (722:722:722)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vga_hc\~1) - (DELAY - (ABSOLUTE - (PORT datab (230:230:230) (272:272:272)) - (PORT datad (560:560:560) (588:588:588)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_hc\[9\]) - (DELAY - (ABSOLUTE - (PORT clk (1536:1536:1536) (1548:1548:1548)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|Add0\~0) (DELAY (ABSOLUTE - (PORT datab (1071:1071:1071) (1110:1110:1110)) + (PORT datab (387:387:387) (463:463:463)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -12950,9 +1458,9 @@ (INSTANCE ula_\|video_\|vga_hc\~3) (DELAY (ABSOLUTE - (PORT datac (830:830:830) (865:865:865)) - (PORT datad (903:903:903) (941:941:941)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT datab (348:348:348) (373:373:373)) + (PORT datad (862:862:862) (885:885:885)) + (IOPATH datab combout (306:306:306) (311:311:311)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -12962,13 +1470,13 @@ (INSTANCE ula_\|video_\|vga_hc\[0\]) (DELAY (ABSOLUTE - (PORT clk (1538:1538:1538) (1550:1550:1550)) - (PORT d (74:74:74) (91:91:91)) + (PORT clk (1904:1904:1904) (1926:1926:1926)) + (PORT asdata (1713:1713:1713) (1720:1720:1720)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) ) ) (CELL @@ -12976,7 +1484,7 @@ (INSTANCE ula_\|video_\|Add0\~2) (DELAY (ABSOLUTE - (PORT datab (672:672:672) (727:727:727)) + (PORT datab (1218:1218:1218) (1298:1298:1298)) (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -12985,28 +1493,18 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vga_hc\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (590:590:590) (612:612:612)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|video_\|vga_hc\[1\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1549:1549:1549)) - (PORT d (74:74:74) (91:91:91)) + (PORT clk (1538:1538:1538) (1550:1550:1550)) + (PORT asdata (851:851:851) (856:856:856)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) ) ) (CELL @@ -13014,7 +1512,7 @@ (INSTANCE ula_\|video_\|Add0\~4) (DELAY (ABSOLUTE - (PORT datab (410:410:410) (485:485:485)) + (PORT datab (1426:1426:1426) (1470:1470:1470)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -13028,8 +1526,8 @@ (INSTANCE ula_\|video_\|vga_hc\[2\]) (DELAY (ABSOLUTE - (PORT clk (1533:1533:1533) (1545:1545:1545)) - (PORT asdata (663:663:663) (679:679:679)) + (PORT clk (1538:1538:1538) (1550:1550:1550)) + (PORT asdata (1240:1240:1240) (1252:1252:1252)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -13042,37 +1540,27 @@ (INSTANCE ula_\|video_\|Add0\~6) (DELAY (ABSOLUTE - (PORT datab (693:693:693) (745:745:745)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (654:654:654) (716:716:716)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vga_hc\[3\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (558:558:558) (581:581:581)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|video_\|vga_hc\[3\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1549:1549:1549)) - (PORT d (74:74:74) (91:91:91)) + (PORT clk (1538:1538:1538) (1551:1551:1551)) + (PORT asdata (872:872:872) (875:875:875)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) ) ) (CELL @@ -13080,7 +1568,7 @@ (INSTANCE ula_\|video_\|Add0\~8) (DELAY (ABSOLUTE - (PORT dataa (1094:1094:1094) (1127:1127:1127)) + (PORT dataa (1285:1285:1285) (1353:1353:1353)) (IOPATH dataa combout (354:354:354) (367:367:367)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -13094,8 +1582,8 @@ (INSTANCE ula_\|video_\|vga_hc\[4\]) (DELAY (ABSOLUTE - (PORT clk (1533:1533:1533) (1545:1545:1545)) - (PORT asdata (662:662:662) (678:678:678)) + (PORT clk (1538:1538:1538) (1551:1551:1551)) + (PORT asdata (515:515:515) (545:545:545)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -13103,61 +1591,14 @@ (HOLD asdata (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Equal0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1251:1251:1251) (1340:1340:1340)) - (PORT datab (983:983:983) (1062:1062:1062)) - (PORT datac (978:978:978) (1050:1050:1050)) - (PORT datad (282:282:282) (366:366:366)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Equal0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (687:687:687) (737:737:737)) - (PORT datab (1394:1394:1394) (1464:1464:1464)) - (PORT datad (941:941:941) (937:937:937)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Equal1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (447:447:447) (523:523:523)) - (PORT datab (684:684:684) (758:758:758)) - (PORT datac (646:646:646) (716:716:716)) - (PORT datad (570:570:570) (576:576:576)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|Add0\~10) (DELAY (ABSOLUTE - (PORT dataa (684:684:684) (734:734:734)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (693:693:693) (752:752:752)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -13169,9 +1610,9 @@ (INSTANCE ula_\|video_\|vga_hc\~0) (DELAY (ABSOLUTE - (PORT datac (833:833:833) (875:875:875)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT datab (559:559:559) (576:576:576)) + (PORT datad (862:862:862) (885:885:885)) + (IOPATH datab combout (306:306:306) (311:311:311)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -13181,13 +1622,13 @@ (INSTANCE ula_\|video_\|vga_hc\[5\]) (DELAY (ABSOLUTE - (PORT clk (1533:1533:1533) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) + (PORT clk (1538:1538:1538) (1551:1551:1551)) + (PORT asdata (834:834:834) (842:842:842)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) ) ) (CELL @@ -13195,7 +1636,7 @@ (INSTANCE ula_\|video_\|Add0\~12) (DELAY (ABSOLUTE - (PORT dataa (629:629:629) (686:686:686)) + (PORT dataa (415:415:415) (498:498:498)) (IOPATH dataa combout (354:354:354) (367:367:367)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -13209,8 +1650,8 @@ (INSTANCE ula_\|video_\|vga_hc\[6\]) (DELAY (ABSOLUTE - (PORT clk (1533:1533:1533) (1545:1545:1545)) - (PORT asdata (516:516:516) (547:547:547)) + (PORT clk (1538:1538:1538) (1551:1551:1551)) + (PORT asdata (656:656:656) (679:679:679)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -13218,13 +1659,27 @@ (HOLD asdata (posedge clk) (157:157:157)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add0\~14) + (DELAY + (ABSOLUTE + (PORT datab (412:412:412) (488:488:488)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|video_\|vga_hc\[7\]) (DELAY (ABSOLUTE - (PORT clk (1533:1533:1533) (1545:1545:1545)) - (PORT asdata (869:869:869) (872:872:872)) + (PORT clk (1538:1538:1538) (1551:1551:1551)) + (PORT asdata (658:658:658) (673:673:673)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -13234,36 +1689,220 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add1\~0) + (INSTANCE ula_\|video_\|Add0\~16) (DELAY (ABSOLUTE - (PORT datab (720:720:720) (795:795:795)) + (PORT datab (433:433:433) (508:508:508)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add1\~2) - (DELAY - (ABSOLUTE - (PORT dataa (707:707:707) (782:782:782)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH dataa cout (436:436:436) (315:315:315)) - (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vga_hc\~2) + (DELAY + (ABSOLUTE + (PORT datab (343:343:343) (375:375:375)) + (PORT datad (891:891:891) (915:915:915)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vga_hc\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1538:1538:1538) (1550:1550:1550)) + (PORT asdata (1614:1614:1614) (1607:1607:1607)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add0\~18) + (DELAY + (ABSOLUTE + (PORT datad (240:240:240) (309:309:309)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vga_hc\~1) + (DELAY + (ABSOLUTE + (PORT dataa (808:808:808) (822:822:822)) + (PORT datad (861:861:861) (880:880:880)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vga_hc\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1538:1538:1538) (1551:1551:1551)) + (PORT asdata (655:655:655) (676:676:676)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (768:768:768) (851:851:851)) + (PORT datab (749:749:749) (820:820:820)) + (PORT datac (1156:1156:1156) (1220:1220:1220)) + (PORT datad (681:681:681) (752:752:752)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1276:1276:1276) (1368:1368:1368)) + (PORT datab (1370:1370:1370) (1423:1423:1423)) + (PORT datac (344:344:344) (367:367:367)) + (PORT datad (899:899:899) (950:950:950)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1019:1019:1019) (1112:1112:1112)) + (PORT datab (706:706:706) (782:782:782)) + (PORT datac (644:644:644) (704:704:704)) + (PORT datad (540:540:540) (562:562:562)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (977:977:977) (1037:1037:1037)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vga_vc\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (371:371:371) (416:416:416)) + (PORT datab (913:913:913) (938:938:938)) + (PORT datac (345:345:345) (367:367:367)) + (PORT datad (939:939:939) (996:996:996)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vga_vc\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1536:1536:1536) (1549:1549:1549)) + (PORT asdata (922:922:922) (937:937:937)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add1\~2) + (DELAY + (ABSOLUTE + (PORT datab (908:908:908) (966:966:966)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vga_vc\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (595:595:595) (634:634:634)) + (PORT datab (569:569:569) (587:587:587)) + (PORT datad (1285:1285:1285) (1292:1292:1292)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vga_vc\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1536:1536:1536) (1549:1549:1549)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|Add1\~4) (DELAY (ABSOLUTE - (PORT dataa (679:679:679) (747:747:747)) + (PORT dataa (717:717:717) (778:778:778)) (IOPATH dataa combout (354:354:354) (367:367:367)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -13277,12 +1916,23 @@ (INSTANCE ula_\|video_\|vga_vc\[2\]\~2) (DELAY (ABSOLUTE - (PORT dataa (517:517:517) (564:564:564)) - (PORT datab (595:595:595) (609:609:609)) - (PORT datad (899:899:899) (922:922:922)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (353:353:353) (369:369:369)) + (PORT dataa (370:370:370) (412:412:412)) + (PORT datab (913:913:913) (939:939:939)) + (PORT datac (1176:1176:1176) (1221:1221:1221)) + (PORT datad (175:175:175) (200:200:200)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vga_vc\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (562:562:562) (574:574:574)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -13292,7 +1942,7 @@ (INSTANCE ula_\|video_\|vga_vc\[2\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1536:1536:1536) (1549:1549:1549)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -13306,7 +1956,7 @@ (INSTANCE ula_\|video_\|Add1\~6) (DELAY (ABSOLUTE - (PORT dataa (712:712:712) (782:782:782)) + (PORT dataa (682:682:682) (759:759:759)) (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -13320,13 +1970,13 @@ (INSTANCE ula_\|video_\|vga_vc\[3\]\~3) (DELAY (ABSOLUTE - (PORT dataa (616:616:616) (648:648:648)) - (PORT datab (645:645:645) (692:692:692)) - (PORT datac (679:679:679) (747:747:747)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (685:685:685) (760:760:760)) + (PORT datab (913:913:913) (938:938:938)) + (PORT datac (173:173:173) (206:206:206)) + (PORT datad (342:342:342) (369:369:369)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -13336,8 +1986,8 @@ (INSTANCE ula_\|video_\|vga_vc\[3\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT asdata (1361:1361:1361) (1352:1352:1352)) + (PORT clk (1536:1536:1536) (1549:1549:1549)) + (PORT asdata (1509:1509:1509) (1524:1524:1524)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -13350,9 +2000,9 @@ (INSTANCE ula_\|video_\|Add1\~8) (DELAY (ABSOLUTE - (PORT datab (680:680:680) (762:762:762)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (752:752:752) (814:814:814)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -13364,9 +2014,9 @@ (INSTANCE ula_\|video_\|vga_vc\[4\]\~5) (DELAY (ABSOLUTE - (PORT dataa (516:516:516) (565:565:565)) - (PORT datab (625:625:625) (643:643:643)) - (PORT datad (899:899:899) (921:921:921)) + (PORT dataa (1138:1138:1138) (1176:1176:1176)) + (PORT datab (824:824:824) (840:840:840)) + (PORT datad (890:890:890) (916:916:916)) (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -13379,7 +2029,7 @@ (INSTANCE ula_\|video_\|vga_vc\[4\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1538:1538:1538) (1550:1550:1550)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -13393,51 +2043,21 @@ (INSTANCE ula_\|video_\|Add1\~10) (DELAY (ABSOLUTE - (PORT dataa (690:690:690) (785:785:785)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (711:711:711) (771:771:771)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vga_vc\[5\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (616:616:616) (645:645:645)) - (PORT datab (645:645:645) (689:689:689)) - (PORT datac (698:698:698) (778:778:778)) - (PORT datad (175:175:175) (199:199:199)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_vc\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT asdata (884:884:884) (883:883:883)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|Add1\~12) (DELAY (ABSOLUTE - (PORT datab (720:720:720) (789:789:789)) + (PORT datab (1187:1187:1187) (1234:1234:1234)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -13451,9 +2071,9 @@ (INSTANCE ula_\|video_\|vga_vc\[6\]\~4) (DELAY (ABSOLUTE - (PORT dataa (519:519:519) (562:562:562)) - (PORT datab (588:588:588) (607:607:607)) - (PORT datad (902:902:902) (917:917:917)) + (PORT dataa (1139:1139:1139) (1176:1176:1176)) + (PORT datab (827:827:827) (836:836:836)) + (PORT datad (892:892:892) (916:916:916)) (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -13466,7 +2086,7 @@ (INSTANCE ula_\|video_\|vga_vc\[6\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1538:1538:1538) (1550:1550:1550)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -13480,7 +2100,7 @@ (INSTANCE ula_\|video_\|Add1\~14) (DELAY (ABSOLUTE - (PORT datab (691:691:691) (762:762:762)) + (PORT datab (1131:1131:1131) (1181:1181:1181)) (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -13494,9 +2114,9 @@ (INSTANCE ula_\|video_\|vga_vc\[7\]\~6) (DELAY (ABSOLUTE - (PORT dataa (517:517:517) (566:566:566)) - (PORT datab (1177:1177:1177) (1178:1178:1178)) - (PORT datad (900:900:900) (920:920:920)) + (PORT dataa (1137:1137:1137) (1176:1176:1176)) + (PORT datab (861:861:861) (876:876:876)) + (PORT datad (890:890:890) (917:917:917)) (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -13509,7 +2129,7 @@ (INSTANCE ula_\|video_\|vga_vc\[7\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1538:1538:1538) (1550:1550:1550)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -13523,9 +2143,9 @@ (INSTANCE ula_\|video_\|Add1\~16) (DELAY (ABSOLUTE - (PORT datab (743:743:743) (817:817:817)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (990:990:990) (1090:1090:1090)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -13537,9 +2157,9 @@ (INSTANCE ula_\|video_\|vga_vc\[8\]\~7) (DELAY (ABSOLUTE - (PORT dataa (517:517:517) (558:558:558)) - (PORT datab (998:998:998) (1000:1000:1000)) - (PORT datad (899:899:899) (916:916:916)) + (PORT dataa (597:597:597) (632:632:632)) + (PORT datab (1128:1128:1128) (1140:1140:1140)) + (PORT datad (1288:1288:1288) (1290:1290:1290)) (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -13552,7 +2172,7 @@ (INSTANCE ula_\|video_\|vga_vc\[8\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1536:1536:1536) (1549:1549:1549)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -13566,7 +2186,7 @@ (INSTANCE ula_\|video_\|Add1\~18) (DELAY (ABSOLUTE - (PORT datad (650:650:650) (707:707:707)) + (PORT datad (1249:1249:1249) (1331:1331:1331)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) ) @@ -13577,11 +2197,11 @@ (INSTANCE ula_\|video_\|vga_vc\[9\]\~9) (DELAY (ABSOLUTE - (PORT dataa (518:518:518) (565:565:565)) - (PORT datab (1005:1005:1005) (1007:1007:1007)) - (PORT datad (899:899:899) (922:922:922)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) + (PORT dataa (575:575:575) (606:606:606)) + (PORT datab (623:623:623) (647:647:647)) + (PORT datad (1108:1108:1108) (1134:1134:1134)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -13592,7 +2212,7 @@ (INSTANCE ula_\|video_\|vga_vc\[9\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1538:1538:1538) (1550:1550:1550)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -13603,31 +2223,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Equal2\~0) + (INSTANCE ula_\|video_\|Equal3\~0) (DELAY (ABSOLUTE - (PORT dataa (272:272:272) (361:361:361)) - (PORT datab (270:270:270) (356:356:356)) - (PORT datac (263:263:263) (343:343:343)) - (PORT datad (244:244:244) (317:317:317)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (934:934:934) (998:998:998)) + (PORT datab (1174:1174:1174) (1232:1232:1232)) + (PORT datac (948:948:948) (1009:1009:1009)) + (PORT datad (1182:1182:1182) (1234:1234:1234)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Equal3\~0) + (INSTANCE ula_\|video_\|Equal2\~0) (DELAY (ABSOLUTE - (PORT dataa (1173:1173:1173) (1262:1262:1262)) - (PORT datab (846:846:846) (922:922:922)) - (PORT datac (628:628:628) (679:679:679)) - (PORT datad (673:673:673) (746:746:746)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) + (PORT dataa (459:459:459) (520:520:520)) + (PORT datab (288:288:288) (373:373:373)) + (PORT datac (404:404:404) (466:466:466)) + (PORT datad (384:384:384) (442:442:442)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -13638,10 +2258,10 @@ (INSTANCE ula_\|video_\|Equal3\~1) (DELAY (ABSOLUTE - (PORT dataa (635:635:635) (701:701:701)) - (PORT datab (664:664:664) (725:725:725)) - (PORT datac (564:564:564) (582:582:582)) - (PORT datad (306:306:306) (321:321:321)) + (PORT dataa (1235:1235:1235) (1301:1301:1301)) + (PORT datab (273:273:273) (358:358:358)) + (PORT datac (593:593:593) (612:612:612)) + (PORT datad (347:347:347) (370:370:370)) (IOPATH dataa combout (324:324:324) (328:328:328)) (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -13651,12 +2271,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vga_vc\[0\]\~0) + (INSTANCE ula_\|video_\|vga_vc\[5\]\~8) (DELAY (ABSOLUTE - (PORT dataa (518:518:518) (561:561:561)) - (PORT datab (553:553:553) (567:567:567)) - (PORT datad (900:900:900) (915:915:915)) + (PORT dataa (1137:1137:1137) (1180:1180:1180)) + (PORT datab (624:624:624) (639:639:639)) + (PORT datad (893:893:893) (919:919:919)) (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -13666,10 +2286,10 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_vc\[0\]) + (INSTANCE ula_\|video_\|vga_vc\[5\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1538:1538:1538) (1550:1550:1550)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -13680,32 +2300,33 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vga_vc\[1\]\~1) + (INSTANCE ula_\|video_\|Equal2\~1) (DELAY (ABSOLUTE - (PORT dataa (516:516:516) (560:560:560)) - (PORT datab (566:566:566) (575:575:575)) - (PORT datad (899:899:899) (916:916:916)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (353:353:353) (369:369:369)) + (PORT dataa (721:721:721) (782:782:782)) + (PORT datab (1274:1274:1274) (1364:1364:1364)) + (PORT datac (872:872:872) (944:944:944)) + (PORT datad (938:938:938) (994:994:994)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vga_vc\[1\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Equal2\~2) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (PORT dataa (1234:1234:1234) (1298:1298:1298)) + (PORT datab (602:602:602) (618:618:618)) + (PORT datad (350:350:350) (372:372:372)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) ) (CELL (CELLTYPE "cycloneive_io_ibuf") @@ -13721,10 +2342,10 @@ (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_13\~0) (DELAY (ABSOLUTE - (PORT dataa (1420:1420:1420) (1497:1497:1497)) - (PORT datab (716:716:716) (801:801:801)) - (PORT datac (1844:1844:1844) (1733:1733:1733)) - (PORT datad (677:677:677) (732:732:732)) + (PORT dataa (849:849:849) (904:904:904)) + (PORT datab (995:995:995) (1083:1083:1083)) + (PORT datac (1205:1205:1205) (1269:1269:1269)) + (PORT datad (1895:1895:1895) (1774:1774:1774)) (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -13732,180 +2353,18 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal79\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1251:1251:1251) (1348:1348:1348)) - (PORT datab (976:976:976) (1034:1034:1034)) - (PORT datac (1637:1637:1637) (1758:1758:1758)) - (PORT datad (1191:1191:1191) (1306:1306:1306)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|DFFE_instIFF2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1500:1500:1500) (1602:1602:1602)) - (PORT datab (361:361:361) (391:391:391)) - (PORT datad (665:665:665) (720:720:720)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_12) - (DELAY - (ABSOLUTE - (PORT dataa (357:357:357) (495:495:495)) - (PORT datab (2014:2014:2014) (2140:2140:2140)) - (PORT datad (275:275:275) (358:358:358)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_clkctrl") - (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_12\~clkctrl) - (DELAY - (ABSOLUTE - (PORT inclk[0] (1586:1586:1586) (1625:1625:1625)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|DFFE_instIFF2) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1553:1553:1553)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1552:1552:1552) (1543:1543:1543)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|iff1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (706:706:706) (765:765:765)) - (PORT datab (266:266:266) (349:349:349)) - (PORT datac (204:204:204) (241:241:241)) - (PORT datad (1456:1456:1456) (1550:1550:1550)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|iff1\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1287:1287:1287) (1330:1330:1330)) - (PORT datab (266:266:266) (349:349:349)) - (PORT datac (888:888:888) (913:913:913)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_15) - (DELAY - (ABSOLUTE - (PORT datab (1431:1431:1431) (1492:1492:1492)) - (PORT datac (1518:1518:1518) (1551:1551:1551)) - (PORT datad (1267:1267:1267) (1335:1335:1335)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|iff1) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1553:1553:1553)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1403:1403:1403) (1412:1412:1412)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Equal2\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1600:1600:1600) (1657:1657:1657)) - (PORT datab (843:843:843) (917:917:917)) - (PORT datac (633:633:633) (688:688:688)) - (PORT datad (427:427:427) (498:498:498)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Equal2\~2) - (DELAY - (ABSOLUTE - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (565:565:565) (583:583:583)) - (PORT datad (436:436:436) (516:516:516)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|interrupts_\|SYNTHESIZED_WIRE_13) (DELAY (ABSOLUTE - (PORT dataa (1175:1175:1175) (1240:1240:1240)) - (PORT datab (630:630:630) (645:645:645)) - (PORT datac (1541:1541:1541) (1636:1636:1636)) - (PORT datad (848:848:848) (861:861:861)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (1473:1473:1473) (1566:1566:1566)) + (PORT datab (566:566:566) (587:587:587)) + (PORT datac (622:622:622) (668:668:668)) + (PORT datad (176:176:176) (202:202:202)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -13915,9 +2374,9 @@ (INSTANCE z80_\|interrupts_\|int_armed) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1542:1542:1542)) + (PORT clk (1532:1532:1532) (1543:1543:1543)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1562:1562:1562) (1552:1552:1552)) + (PORT clrn (1563:1563:1563) (1553:1553:1553)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -13926,49 +2385,43 @@ (HOLD d (posedge clk) (157:157:157)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|DFFE_inst44\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1497:1497:1497) (1623:1623:1623)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|interrupts_\|DFFE_inst44) (DELAY (ABSOLUTE - (PORT clk (1533:1533:1533) (1552:1552:1552)) - (PORT asdata (2158:2158:2158) (2284:2284:2284)) - (PORT clrn (1592:1592:1592) (1568:1568:1568)) - (PORT ena (1669:1669:1669) (1678:1678:1678)) + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1566:1566:1566) (1548:1548:1548)) + (PORT ena (959:959:959) (957:957:957)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) + (HOLD d (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~38) + (INSTANCE z80_\|decode_state_\|in_halt\~0) (DELAY (ABSOLUTE - (PORT dataa (355:355:355) (487:487:487)) - (PORT datac (1180:1180:1180) (1261:1261:1261)) - (PORT datad (269:269:269) (350:350:350)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~91) - (DELAY - (ABSOLUTE - (PORT dataa (1671:1671:1671) (1790:1790:1790)) - (PORT datab (1251:1251:1251) (1347:1347:1347)) - (PORT datac (971:971:971) (1065:1065:1065)) - (PORT datad (862:862:862) (887:887:887)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (336:336:336) (325:325:325)) + (PORT dataa (506:506:506) (585:585:585)) + (PORT datac (267:267:267) (357:357:357)) + (PORT datad (703:703:703) (788:788:788)) + (IOPATH dataa combout (325:325:325) (320:320:320)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -13976,15 +2429,44 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~45) + (INSTANCE z80_\|decode_state_\|in_halt\~1) (DELAY (ABSOLUTE - (PORT dataa (1089:1089:1089) (1139:1139:1139)) - (PORT datab (699:699:699) (765:765:765)) - (PORT datac (1191:1191:1191) (1271:1271:1271)) - (PORT datad (626:626:626) (668:668:668)) + (PORT dataa (349:349:349) (379:379:379)) + (PORT datab (1642:1642:1642) (1678:1678:1678)) + (PORT datad (616:616:616) (664:664:664)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|decode_state_\|in_halt) + (DELAY + (ABSOLUTE + (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1567:1567:1567) (1549:1549:1549)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal50\~0) + (DELAY + (ABSOLUTE + (PORT datab (312:312:312) (409:409:409)) + (PORT datac (1832:1832:1832) (1861:1861:1861)) + (PORT datad (578:578:578) (597:597:597)) + (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -13992,15 +2474,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~44) + (INSTANCE z80_\|execute_\|ixy_d\~17) (DELAY (ABSOLUTE - (PORT dataa (1090:1090:1090) (1140:1140:1140)) - (PORT datab (909:909:909) (981:981:981)) - (PORT datac (856:856:856) (898:898:898)) - (PORT datad (1096:1096:1096) (1107:1107:1107)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (PORT dataa (482:482:482) (579:579:579)) + (PORT datab (495:495:495) (577:577:577)) + (PORT datac (828:828:828) (841:841:841)) + (PORT datad (595:595:595) (614:614:614)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -14008,191 +2490,227 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~46) + (INSTANCE z80_\|pla_decode_\|Equal44\~0) (DELAY (ABSOLUTE - (PORT dataa (338:338:338) (372:372:372)) - (PORT datab (702:702:702) (770:770:770)) - (PORT datac (173:173:173) (207:207:207)) - (PORT datad (1101:1101:1101) (1112:1112:1112)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (1042:1042:1042) (1133:1133:1133)) + (PORT datab (997:997:997) (1104:1104:1104)) + (PORT datac (932:932:932) (1055:1055:1055)) + (PORT datad (973:973:973) (1057:1057:1057)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~37) + (INSTANCE z80_\|execute_\|ixy_d\~16) (DELAY (ABSOLUTE - (PORT dataa (1161:1161:1161) (1207:1207:1207)) - (PORT datab (884:884:884) (933:933:933)) - (PORT datac (1058:1058:1058) (1098:1098:1098)) - (PORT datad (202:202:202) (231:231:231)) - (IOPATH dataa combout (304:304:304) (308:308:308)) + (PORT dataa (478:478:478) (576:576:576)) + (PORT datab (499:499:499) (580:580:580)) + (PORT datac (1219:1219:1219) (1275:1275:1275)) + (PORT datad (204:204:204) (233:233:233)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal3\~1) + (DELAY + (ABSOLUTE + (PORT datac (887:887:887) (952:952:952)) + (PORT datad (1303:1303:1303) (1431:1431:1431)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1657:1657:1657) (1683:1683:1683)) + (PORT datab (654:654:654) (688:688:688)) + (PORT datac (918:918:918) (963:963:963)) + (PORT datad (949:949:949) (1026:1026:1026)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1195:1195:1195) (1265:1265:1265)) + (PORT datab (371:371:371) (414:414:414)) + (PORT datac (1556:1556:1556) (1662:1662:1662)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1066:1066:1066) (1147:1147:1147)) + (PORT datab (654:654:654) (705:705:705)) + (PORT datac (646:646:646) (663:663:663)) + (PORT datad (171:171:171) (196:196:196)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal49\~0) + (DELAY + (ABSOLUTE + (PORT datab (312:312:312) (412:412:412)) + (PORT datac (1693:1693:1693) (1762:1762:1762)) + (PORT datad (579:579:579) (601:601:601)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ixy_d\~15) + (DELAY + (ABSOLUTE + (PORT dataa (965:965:965) (1008:1008:1008)) + (PORT datab (925:925:925) (962:962:962)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (1259:1259:1259) (1310:1310:1310)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_ixy_dT5_7) + (DELAY + (ABSOLUTE + (PORT datab (905:905:905) (938:938:938)) + (PORT datac (1425:1425:1425) (1546:1546:1546)) (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~50) + (INSTANCE z80_\|decode_state_\|SYNTHESIZED_WIRE_0\~0) (DELAY (ABSOLUTE - (PORT dataa (830:830:830) (863:863:863)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (1604:1604:1604) (1719:1719:1719)) - (PORT datad (2285:2285:2285) (2389:2389:2389)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (743:743:743) (836:836:836)) + (PORT datab (973:973:973) (1036:1036:1036)) + (PORT datac (192:192:192) (225:225:225)) + (PORT datad (387:387:387) (419:419:419)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~33) + (CELLTYPE "dffeas") + (INSTANCE z80_\|decode_state_\|DFFE_inst4) (DELAY (ABSOLUTE - (PORT dataa (229:229:229) (276:276:276)) - (PORT datab (1151:1151:1151) (1219:1219:1219)) - (PORT datac (1080:1080:1080) (1126:1126:1126)) - (PORT datad (596:596:596) (629:629:629)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT clk (1525:1525:1525) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1559:1559:1559) (1540:1540:1540)) + (PORT ena (820:820:820) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla38pla13M3T2_4) + (INSTANCE z80_\|execute_\|ctl_ir_we\~5) (DELAY (ABSOLUTE - (PORT dataa (1685:1685:1685) (1750:1750:1750)) - (PORT datab (623:623:623) (672:672:672)) - (PORT datac (1663:1663:1663) (1743:1743:1743)) - (PORT datad (1164:1164:1164) (1212:1212:1212)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla40M3T2_4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (729:729:729) (825:825:825)) - (PORT datab (672:672:672) (761:761:761)) - (PORT datac (1148:1148:1148) (1186:1186:1186)) - (PORT datad (212:212:212) (247:247:247)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~31) - (DELAY - (ABSOLUTE - (PORT dataa (1112:1112:1112) (1165:1165:1165)) - (PORT datab (850:850:850) (866:866:866)) - (PORT datac (1208:1208:1208) (1236:1236:1236)) - (PORT datad (822:822:822) (834:834:834)) + (PORT dataa (1042:1042:1042) (1134:1134:1134)) + (PORT datab (504:504:504) (589:589:589)) + (PORT datad (441:441:441) (521:521:521)) (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~32) + (INSTANCE z80_\|execute_\|ctl_ir_we\~13) (DELAY (ABSOLUTE - (PORT dataa (1110:1110:1110) (1168:1168:1168)) - (PORT datab (622:622:622) (673:673:673)) - (PORT datac (209:209:209) (250:250:250)) - (PORT datad (1641:1641:1641) (1711:1711:1711)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~34) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (193:193:193) (238:238:238)) - (PORT datad (180:180:180) (209:209:209)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~51) - (DELAY - (ABSOLUTE - (PORT dataa (1149:1149:1149) (1191:1191:1191)) - (PORT datab (1399:1399:1399) (1505:1505:1505)) - (PORT datac (2514:2514:2514) (2618:2618:2618)) - (PORT datad (1497:1497:1497) (1611:1611:1611)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~30) - (DELAY - (ABSOLUTE - (PORT dataa (691:691:691) (738:738:738)) - (PORT datab (1144:1144:1144) (1210:1210:1210)) - (PORT datac (365:365:365) (393:393:393)) - (PORT datad (865:865:865) (890:890:890)) - (IOPATH dataa combout (337:337:337) (338:338:338)) + (PORT dataa (975:975:975) (1047:1047:1047)) + (PORT datab (611:611:611) (629:629:629)) + (PORT datac (1954:1954:1954) (2059:2059:2059)) + (PORT datad (877:877:877) (926:926:926)) + (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~52) + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[3\]) (DELAY (ABSOLUTE - (PORT dataa (1521:1521:1521) (1648:1648:1648)) - (PORT datab (1395:1395:1395) (1501:1501:1501)) - (PORT datac (2518:2518:2518) (2621:2621:2621)) - (PORT datad (1054:1054:1054) (1086:1086:1086)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) + (PORT clk (1541:1541:1541) (1557:1557:1557)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1567:1567:1567) (1549:1549:1549)) + (PORT ena (1404:1404:1404) (1375:1375:1375)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal8\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1558:1558:1558) (1685:1685:1685)) + (PORT datac (1365:1365:1365) (1540:1540:1540)) + (PORT datad (1513:1513:1513) (1632:1632:1632)) + (IOPATH dataa combout (324:324:324) (328:328:328)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -14200,13 +2718,239 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~35) + (INSTANCE z80_\|execute_\|ctl_mRead\~6) (DELAY (ABSOLUTE - (PORT dataa (370:370:370) (406:406:406)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (619:619:619) (652:652:652)) - (PORT datad (179:179:179) (207:207:207)) + (PORT datab (1318:1318:1318) (1402:1402:1402)) + (PORT datac (638:638:638) (670:670:670)) + (PORT datad (1196:1196:1196) (1265:1265:1265)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal9\~0) + (DELAY + (ABSOLUTE + (PORT datab (1416:1416:1416) (1527:1527:1527)) + (PORT datad (1440:1440:1440) (1528:1528:1528)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal9\~1) + (DELAY + (ABSOLUTE + (PORT dataa (2523:2523:2523) (2690:2690:2690)) + (PORT datab (968:968:968) (1051:1051:1051)) + (PORT datac (1680:1680:1680) (1751:1751:1751)) + (PORT datad (908:908:908) (962:962:962)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla10M5T1_5\~2) + (DELAY + (ABSOLUTE + (PORT datab (1286:1286:1286) (1375:1375:1375)) + (PORT datac (1790:1790:1790) (1858:1858:1858)) + (PORT datad (1011:1011:1011) (1104:1104:1104)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (1360:1360:1360) (1407:1407:1407)) + (PORT datab (1259:1259:1259) (1302:1302:1302)) + (PORT datac (1205:1205:1205) (1234:1234:1234)) + (PORT datad (636:636:636) (687:687:687)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal13\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1565:1565:1565) (1693:1693:1693)) + (PORT datac (1381:1381:1381) (1558:1558:1558)) + (PORT datad (1511:1511:1511) (1631:1631:1631)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal69\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1992:1992:1992) (2184:2184:2184)) + (PORT datab (1223:1223:1223) (1309:1309:1309)) + (PORT datac (1175:1175:1175) (1266:1266:1266)) + (PORT datad (1186:1186:1186) (1205:1205:1205)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (624:624:624) (680:680:680)) + (PORT datab (1525:1525:1525) (1622:1622:1622)) + (PORT datac (851:851:851) (896:896:896)) + (PORT datad (934:934:934) (1019:1019:1019)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~27) + (DELAY + (ABSOLUTE + (PORT dataa (1345:1345:1345) (1475:1475:1475)) + (PORT datab (229:229:229) (272:272:272)) + (PORT datac (1217:1217:1217) (1269:1269:1269)) + (PORT datad (856:856:856) (901:901:901)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1707:1707:1707) (1758:1758:1758)) + (PORT datab (992:992:992) (1035:1035:1035)) + (PORT datac (1141:1141:1141) (1167:1167:1167)) + (PORT datad (1219:1219:1219) (1214:1214:1214)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|rsel3) + (DELAY + (ABSOLUTE + (PORT dataa (790:790:790) (894:894:894)) + (PORT datac (1368:1368:1368) (1448:1448:1448)) + (PORT datad (1229:1229:1229) (1324:1324:1324)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~12) + (DELAY + (ABSOLUTE + (PORT dataa (719:719:719) (795:795:795)) + (PORT datab (1042:1042:1042) (1181:1181:1181)) + (PORT datac (1282:1282:1282) (1348:1348:1348)) + (PORT datad (996:996:996) (1098:1098:1098)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3) + (DELAY + (ABSOLUTE + (PORT dataa (979:979:979) (1067:1067:1067)) + (PORT datac (1110:1110:1110) (1150:1150:1150)) + (PORT datad (1381:1381:1381) (1455:1455:1455)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal56\~0) + (DELAY + (ABSOLUTE + (PORT dataa (987:987:987) (1092:1092:1092)) + (PORT datab (1518:1518:1518) (1582:1582:1582)) + (PORT datac (1014:1014:1014) (1073:1073:1073)) + (PORT datad (1663:1663:1663) (1795:1795:1795)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~24) + (DELAY + (ABSOLUTE + (PORT dataa (2080:2080:2080) (2164:2164:2164)) + (PORT datab (2213:2213:2213) (2326:2326:2326)) + (PORT datac (1928:1928:1928) (1994:1994:1994)) + (PORT datad (915:915:915) (988:988:988)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~25) + (DELAY + (ABSOLUTE + (PORT dataa (2188:2188:2188) (2323:2323:2323)) + (PORT datab (971:971:971) (1055:1055:1055)) + (PORT datac (1166:1166:1166) (1223:1223:1223)) + (PORT datad (896:896:896) (971:971:971)) (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datab combout (342:342:342) (318:318:318)) (IOPATH datac combout (243:243:243) (241:241:241)) @@ -14216,15 +2960,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~36) + (INSTANCE z80_\|execute_\|nextM\~2) (DELAY (ABSOLUTE - (PORT dataa (1104:1104:1104) (1123:1123:1123)) - (PORT datab (643:643:643) (662:662:662)) - (PORT datac (625:625:625) (646:646:646)) - (PORT datad (1379:1379:1379) (1419:1419:1419)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) + (PORT dataa (895:895:895) (980:980:980)) + (PORT datac (569:569:569) (601:601:601)) + (PORT datad (1058:1058:1058) (1065:1065:1065)) + (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -14232,75 +2974,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~44) + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~16) (DELAY (ABSOLUTE - (PORT dataa (2071:2071:2071) (2185:2185:2185)) - (PORT datab (910:910:910) (981:981:981)) - (PORT datac (1397:1397:1397) (1483:1483:1483)) - (PORT datad (646:646:646) (677:677:677)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_use_ixiypla53M2T2_4) - (DELAY - (ABSOLUTE - (PORT dataa (1333:1333:1333) (1437:1437:1437)) - (PORT datab (1764:1764:1764) (1881:1881:1881)) - (PORT datad (630:630:630) (685:685:685)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~45) - (DELAY - (ABSOLUTE - (PORT dataa (216:216:216) (266:266:266)) - (PORT datab (216:216:216) (261:261:261)) - (PORT datac (670:670:670) (716:716:716)) - (PORT datad (570:570:570) (590:590:590)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~43) - (DELAY - (ABSOLUTE - (PORT dataa (1409:1409:1409) (1454:1454:1454)) - (PORT datab (666:666:666) (697:697:697)) - (PORT datac (1989:1989:1989) (2085:2085:2085)) - (PORT datad (1246:1246:1246) (1294:1294:1294)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~71) - (DELAY - (ABSOLUTE - (PORT dataa (207:207:207) (253:253:253)) - (PORT datab (221:221:221) (260:260:260)) - (PORT datac (635:635:635) (682:682:682)) - (PORT datad (190:190:190) (223:223:223)) + (PORT dataa (981:981:981) (1069:1069:1069)) + (PORT datab (975:975:975) (1040:1040:1040)) + (PORT datac (1312:1312:1312) (1366:1366:1366)) + (PORT datad (1233:1233:1233) (1288:1288:1288)) (IOPATH dataa combout (341:341:341) (319:319:319)) (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (241:241:241)) @@ -14310,15 +2990,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~73) + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~3) (DELAY (ABSOLUTE - (PORT dataa (390:390:390) (421:421:421)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (637:637:637) (672:672:672)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (300:300:300) (308:308:308)) + (PORT dataa (628:628:628) (678:678:678)) + (PORT datab (676:676:676) (719:719:719)) + (PORT datac (193:193:193) (226:226:226)) + (PORT datad (194:194:194) (220:220:220)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal40\~0) + (DELAY + (ABSOLUTE + (PORT dataa (976:976:976) (1070:1070:1070)) + (PORT datac (887:887:887) (952:952:952)) + (PORT datad (1303:1303:1303) (1432:1432:1432)) + (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -14326,30 +3020,28 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~46) + (INSTANCE z80_\|pla_decode_\|Equal40\~1) (DELAY (ABSOLUTE - (PORT dataa (673:673:673) (722:722:722)) - (PORT datab (699:699:699) (766:766:766)) - (PORT datac (639:639:639) (671:671:671)) - (PORT datad (1153:1153:1153) (1224:1224:1224)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (232:232:232) (292:292:292)) + (PORT datab (880:880:880) (938:938:938)) + (PORT datad (1360:1360:1360) (1485:1485:1485)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~53) + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla23pla16M3T1_5\~0) (DELAY (ABSOLUTE - (PORT dataa (1647:1647:1647) (1764:1764:1764)) - (PORT datab (1067:1067:1067) (1136:1136:1136)) - (PORT datac (612:612:612) (631:631:631)) - (PORT datad (973:973:973) (1058:1058:1058)) - (IOPATH dataa combout (304:304:304) (299:299:299)) + (PORT dataa (988:988:988) (1091:1091:1091)) + (PORT datab (1082:1082:1082) (1154:1154:1154)) + (PORT datac (940:940:940) (974:974:974)) + (PORT datad (1027:1027:1027) (1094:1094:1094)) + (IOPATH dataa combout (324:324:324) (328:328:328)) (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -14358,13 +3050,1147 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~39) + (INSTANCE z80_\|pla_decode_\|Equal3\~0) (DELAY (ABSOLUTE - (PORT dataa (215:215:215) (264:264:264)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (623:623:623) (647:647:647)) - (PORT datad (565:565:565) (585:585:585)) + (PORT datab (1218:1218:1218) (1320:1320:1320)) + (PORT datad (1266:1266:1266) (1357:1357:1357)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal39\~0) + (DELAY + (ABSOLUTE + (PORT dataa (233:233:233) (292:292:292)) + (PORT datab (879:879:879) (938:938:938)) + (PORT datac (1315:1315:1315) (1437:1437:1437)) + (PORT datad (887:887:887) (944:944:944)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1290:1290:1290) (1340:1340:1340)) + (PORT datab (644:644:644) (674:674:674)) + (PORT datac (1384:1384:1384) (1432:1432:1432)) + (PORT datad (1996:1996:1996) (2055:2055:2055)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~0) + (DELAY + (ABSOLUTE + (PORT datac (1581:1581:1581) (1680:1680:1680)) + (PORT datad (1300:1300:1300) (1409:1409:1409)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|comb\~0) + (DELAY + (ABSOLUTE + (PORT datac (1400:1400:1400) (1460:1460:1460)) + (PORT datad (1209:1209:1209) (1274:1274:1274)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal41\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1026:1026:1026) (1143:1143:1143)) + (PORT datad (1005:1005:1005) (1141:1141:1141)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal47\~0) + (DELAY + (ABSOLUTE + (PORT dataa (980:980:980) (1067:1067:1067)) + (PORT datab (661:661:661) (687:687:687)) + (PORT datac (636:636:636) (654:654:654)) + (PORT datad (681:681:681) (729:729:729)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~32) + (DELAY + (ABSOLUTE + (PORT dataa (1247:1247:1247) (1322:1322:1322)) + (PORT datab (1732:1732:1732) (1828:1828:1828)) + (PORT datac (211:211:211) (251:251:251)) + (PORT datad (1343:1343:1343) (1419:1419:1419)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal19\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1302:1302:1302) (1383:1383:1383)) + (PORT datab (889:889:889) (925:925:925)) + (PORT datac (740:740:740) (846:846:846)) + (PORT datad (1071:1071:1071) (1093:1093:1093)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~9) + (DELAY + (ABSOLUTE + (PORT dataa (214:214:214) (264:264:264)) + (PORT datab (1205:1205:1205) (1281:1281:1281)) + (PORT datac (1579:1579:1579) (1678:1678:1678)) + (PORT datad (1295:1295:1295) (1406:1406:1406)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~5) + (DELAY + (ABSOLUTE + (PORT dataa (616:616:616) (629:629:629)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (575:575:575) (600:600:600)) + (PORT datad (1345:1345:1345) (1384:1384:1384)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~4) + (DELAY + (ABSOLUTE + (PORT dataa (287:287:287) (385:385:385)) + (PORT datab (1160:1160:1160) (1219:1219:1219)) + (PORT datac (396:396:396) (476:476:476)) + (PORT datad (394:394:394) (459:459:459)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla21M2T2_3) + (DELAY + (ABSOLUTE + (PORT dataa (968:968:968) (1036:1036:1036)) + (PORT datab (1665:1665:1665) (1730:1730:1730)) + (PORT datac (938:938:938) (1051:1051:1051)) + (PORT datad (2586:2586:2586) (2762:2762:2762)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~34) + (DELAY + (ABSOLUTE + (PORT dataa (698:698:698) (807:807:807)) + (PORT datab (1716:1716:1716) (1780:1780:1780)) + (PORT datac (1114:1114:1114) (1189:1189:1189)) + (PORT datad (913:913:913) (932:932:932)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_ixy_dT4_2) + (DELAY + (ABSOLUTE + (PORT datac (1594:1594:1594) (1728:1728:1728)) + (PORT datad (1081:1081:1081) (1116:1116:1116)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (206:206:206) (253:253:253)) + (PORT datab (1127:1127:1127) (1206:1206:1206)) + (PORT datac (973:973:973) (1037:1037:1037)) + (PORT datad (1067:1067:1067) (1096:1096:1096)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~5) + (DELAY + (ABSOLUTE + (PORT datab (468:468:468) (546:546:546)) + (PORT datac (417:417:417) (491:491:491)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~11) + (DELAY + (ABSOLUTE + (PORT dataa (847:847:847) (873:873:873)) + (PORT datab (1711:1711:1711) (1758:1758:1758)) + (PORT datac (862:862:862) (891:891:891)) + (PORT datad (901:901:901) (992:992:992)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal20\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1719:1719:1719) (1854:1854:1854)) + (PORT datab (1514:1514:1514) (1573:1573:1573)) + (PORT datac (1305:1305:1305) (1369:1369:1369)) + (PORT datad (659:659:659) (733:733:733)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal13\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1991:1991:1991) (2189:2189:2189)) + (PORT datab (1221:1221:1221) (1309:1309:1309)) + (PORT datac (1178:1178:1178) (1270:1270:1270)) + (PORT datad (1183:1183:1183) (1205:1205:1205)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~24) + (DELAY + (ABSOLUTE + (PORT datac (2181:2181:2181) (2263:2263:2263)) + (PORT datad (1433:1433:1433) (1514:1514:1514)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (1103:1103:1103) (1150:1150:1150)) + (PORT datab (987:987:987) (1033:1033:1033)) + (PORT datac (1354:1354:1354) (1406:1406:1406)) + (PORT datad (1141:1141:1141) (1141:1141:1141)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal48\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2004:2004:2004) (2196:2196:2196)) + (PORT datab (1220:1220:1220) (1307:1307:1307)) + (PORT datac (1184:1184:1184) (1277:1277:1277)) + (PORT datad (1182:1182:1182) (1203:1203:1203)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal10\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1428:1428:1428) (1603:1603:1603)) + (PORT datab (1228:1228:1228) (1299:1299:1299)) + (PORT datac (1530:1530:1530) (1649:1649:1649)) + (PORT datad (1513:1513:1513) (1634:1634:1634)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal11\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1429:1429:1429) (1604:1604:1604)) + (PORT datab (1228:1228:1228) (1299:1299:1299)) + (PORT datac (1531:1531:1531) (1649:1649:1649)) + (PORT datad (1514:1514:1514) (1635:1635:1635)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal63\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1718:1718:1718) (1854:1854:1854)) + (PORT datab (1514:1514:1514) (1575:1575:1575)) + (PORT datac (1305:1305:1305) (1372:1372:1372)) + (PORT datad (659:659:659) (732:732:732)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf2_we) + (DELAY + (ABSOLUTE + (PORT dataa (1148:1148:1148) (1200:1200:1200)) + (PORT datab (1406:1406:1406) (1447:1447:1447)) + (PORT datac (1417:1417:1417) (1511:1511:1511)) + (PORT datad (914:914:914) (985:985:985)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~41) + (DELAY + (ABSOLUTE + (PORT dataa (2364:2364:2364) (2424:2424:2424)) + (PORT datab (1731:1731:1731) (1782:1782:1782)) + (PORT datac (202:202:202) (239:239:239)) + (PORT datad (1368:1368:1368) (1411:1411:1411)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal68\~3) + (DELAY + (ABSOLUTE + (PORT dataa (922:922:922) (994:994:994)) + (PORT datab (1333:1333:1333) (1472:1472:1472)) + (PORT datac (855:855:855) (907:907:907)) + (PORT datad (934:934:934) (1023:1023:1023)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~7) + (DELAY + (ABSOLUTE + (PORT dataa (242:242:242) (286:286:286)) + (PORT datab (207:207:207) (249:249:249)) + (PORT datac (1220:1220:1220) (1271:1271:1271)) + (PORT datad (1076:1076:1076) (1155:1155:1155)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1088:1088:1088) (1110:1110:1110)) + (PORT datab (1585:1585:1585) (1610:1610:1610)) + (PORT datac (1644:1644:1644) (1686:1686:1686)) + (PORT datad (859:859:859) (911:911:911)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~9) + (DELAY + (ABSOLUTE + (PORT dataa (599:599:599) (640:640:640)) + (PORT datab (1733:1733:1733) (1817:1817:1817)) + (PORT datac (1890:1890:1890) (2010:2010:2010)) + (PORT datad (856:856:856) (936:936:936)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1022:1022:1022) (1142:1142:1142)) + (PORT datad (1002:1002:1002) (1146:1146:1146)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (732:732:732) (806:806:806)) + (PORT datab (227:227:227) (268:268:268)) + (PORT datac (1291:1291:1291) (1355:1355:1355)) + (PORT datad (968:968:968) (1051:1051:1051)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~14) + (DELAY + (ABSOLUTE + (PORT dataa (734:734:734) (808:808:808)) + (PORT datab (1047:1047:1047) (1185:1185:1185)) + (PORT datac (1291:1291:1291) (1356:1356:1356)) + (PORT datad (988:988:988) (1089:1089:1089)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~4) + (DELAY + (ABSOLUTE + (PORT dataa (884:884:884) (916:916:916)) + (PORT datab (1918:1918:1918) (2042:2042:2042)) + (PORT datac (1702:1702:1702) (1782:1782:1782)) + (PORT datad (615:615:615) (631:631:631)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1204:1204:1204) (1260:1260:1260)) + (PORT datab (1666:1666:1666) (1743:1743:1743)) + (PORT datac (537:537:537) (553:553:553)) + (PORT datad (1398:1398:1398) (1411:1411:1411)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1655:1655:1655) (1681:1681:1681)) + (PORT datab (649:649:649) (682:682:682)) + (PORT datac (926:926:926) (974:974:974)) + (PORT datad (953:953:953) (1032:1032:1032)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~6) + (DELAY + (ABSOLUTE + (PORT dataa (864:864:864) (938:938:938)) + (PORT datab (1544:1544:1544) (1580:1580:1580)) + (PORT datac (1644:1644:1644) (1686:1686:1686)) + (PORT datad (1435:1435:1435) (1485:1485:1485)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~9) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (244:244:244)) + (PORT datab (207:207:207) (250:250:250)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_iorw\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1561:1561:1561) (1691:1691:1691)) + (PORT datab (1494:1494:1494) (1547:1547:1547)) + (PORT datac (1374:1374:1374) (1549:1549:1549)) + (PORT datad (1513:1513:1513) (1638:1638:1638)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1425:1425:1425) (1601:1601:1601)) + (PORT datab (1225:1225:1225) (1300:1300:1300)) + (PORT datac (1528:1528:1528) (1646:1646:1646)) + (PORT datad (1510:1510:1510) (1633:1633:1633)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~18) + (DELAY + (ABSOLUTE + (PORT dataa (947:947:947) (987:987:987)) + (PORT datab (2520:2520:2520) (2505:2505:2505)) + (PORT datac (863:863:863) (889:889:889)) + (PORT datad (834:834:834) (862:862:862)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal37\~0) + (DELAY + (ABSOLUTE + (PORT dataa (975:975:975) (1066:1066:1066)) + (PORT datab (666:666:666) (692:692:692)) + (PORT datac (593:593:593) (641:641:641)) + (PORT datad (682:682:682) (732:732:732)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1052:1052:1052) (1095:1095:1095)) + (PORT datab (1183:1183:1183) (1218:1218:1218)) + (PORT datac (1171:1171:1171) (1202:1202:1202)) + (PORT datad (1795:1795:1795) (1839:1839:1839)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal35\~0) + (DELAY + (ABSOLUTE + (PORT dataa (979:979:979) (1061:1061:1061)) + (PORT datab (667:667:667) (694:694:694)) + (PORT datac (547:547:547) (568:568:568)) + (PORT datad (684:684:684) (735:735:735)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal21\~1) + (DELAY + (ABSOLUTE + (PORT dataa (234:234:234) (294:294:294)) + (PORT datab (886:886:886) (943:943:943)) + (PORT datac (1217:1217:1217) (1268:1268:1268)) + (PORT datad (1362:1362:1362) (1487:1487:1487)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1419:1419:1419) (1478:1478:1478)) + (PORT datab (1049:1049:1049) (1106:1106:1106)) + (PORT datac (830:830:830) (890:890:890)) + (PORT datad (1676:1676:1676) (1758:1758:1758)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~20) + (DELAY + (ABSOLUTE + (PORT dataa (845:845:845) (888:888:888)) + (PORT datab (858:858:858) (925:925:925)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1327:1327:1327) (1395:1395:1395)) + (PORT datab (220:220:220) (260:260:260)) + (PORT datac (694:694:694) (759:759:759)) + (PORT datad (969:969:969) (1053:1053:1053)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1123:1123:1123) (1170:1170:1170)) + (PORT datab (1532:1532:1532) (1666:1666:1666)) + (PORT datac (957:957:957) (985:985:985)) + (PORT datad (2545:2545:2545) (2613:2613:2613)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~15) + (DELAY + (ABSOLUTE + (PORT dataa (732:732:732) (806:806:806)) + (PORT datab (1045:1045:1045) (1186:1186:1186)) + (PORT datac (1290:1290:1290) (1355:1355:1355)) + (PORT datad (990:990:990) (1092:1092:1092)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1454:1454:1454) (1506:1506:1506)) + (PORT datab (1139:1139:1139) (1168:1168:1168)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (942:942:942) (1007:1007:1007)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~7) + (DELAY + (ABSOLUTE + (PORT dataa (728:728:728) (801:801:801)) + (PORT datab (1042:1042:1042) (1188:1188:1188)) + (PORT datac (1288:1288:1288) (1353:1353:1353)) + (PORT datad (994:994:994) (1099:1099:1099)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal46\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1695:1695:1695) (1742:1742:1742)) + (PORT datab (267:267:267) (352:352:352)) + (PORT datac (240:240:240) (319:319:319)) + (PORT datad (385:385:385) (451:451:451)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1026:1026:1026) (1144:1144:1144)) + (PORT datab (1044:1044:1044) (1182:1182:1182)) + (PORT datac (683:683:683) (746:746:746)) + (PORT datad (1151:1151:1151) (1174:1174:1174)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~3) + (DELAY + (ABSOLUTE + (PORT dataa (696:696:696) (720:720:720)) + (PORT datab (1474:1474:1474) (1515:1515:1515)) + (PORT datac (937:937:937) (976:976:976)) + (PORT datad (906:906:906) (931:931:931)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal52\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1259:1259:1259) (1313:1313:1313)) + (PORT datab (995:995:995) (1101:1101:1101)) + (PORT datac (640:640:640) (656:656:656)) + (PORT datad (1000:1000:1000) (1088:1088:1088)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~21) + (DELAY + (ABSOLUTE + (PORT dataa (2391:2391:2391) (2514:2514:2514)) + (PORT datab (1262:1262:1262) (1375:1375:1375)) + (PORT datac (815:815:815) (835:835:835)) + (PORT datad (379:379:379) (412:412:412)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~13) + (DELAY + (ABSOLUTE + (PORT dataa (611:611:611) (649:649:649)) + (PORT datab (1249:1249:1249) (1289:1289:1289)) + (PORT datac (754:754:754) (766:766:766)) + (PORT datad (1095:1095:1095) (1107:1107:1107)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~6) + (DELAY + (ABSOLUTE + (PORT dataa (479:479:479) (577:577:577)) + (PORT datab (493:493:493) (585:585:585)) + (PORT datac (1217:1217:1217) (1272:1272:1272)) + (PORT datad (204:204:204) (233:233:233)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1527:1527:1527) (1589:1589:1589)) + (PORT datac (1001:1001:1001) (1069:1069:1069)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~14) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (264:264:264)) + (PORT datab (219:219:219) (257:257:257)) + (PORT datac (1134:1134:1134) (1152:1152:1152)) + (PORT datad (1561:1561:1561) (1676:1676:1676)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (1607:1607:1607) (1657:1657:1657)) + (PORT datab (1918:1918:1918) (1952:1952:1952)) + (PORT datac (1659:1659:1659) (1687:1687:1687)) + (PORT datad (544:544:544) (566:566:566)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (793:793:793) (847:847:847)) + (PORT datab (1152:1152:1152) (1192:1192:1192)) + (PORT datac (617:617:617) (641:641:641)) + (PORT datad (195:195:195) (221:221:221)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\~7) + (DELAY + (ABSOLUTE + (PORT dataa (2063:2063:2063) (2160:2160:2160)) + (PORT datab (663:663:663) (691:691:691)) + (PORT datac (866:866:866) (894:894:894)) + (PORT datad (682:682:682) (732:732:732)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|rsel0) + (DELAY + (ABSOLUTE + (PORT datab (1518:1518:1518) (1572:1572:1572)) + (PORT datac (1447:1447:1447) (1523:1523:1523)) + (PORT datad (913:913:913) (997:997:997)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~3) + (DELAY + (ABSOLUTE + (PORT dataa (2132:2132:2132) (2250:2250:2250)) + (PORT datac (1556:1556:1556) (1656:1656:1656)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~0) + (DELAY + (ABSOLUTE + (PORT dataa (902:902:902) (936:936:936)) + (PORT datab (893:893:893) (930:930:930)) + (PORT datac (816:816:816) (838:838:838)) + (PORT datad (899:899:899) (995:995:995)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~2) + (DELAY + (ABSOLUTE + (PORT datab (394:394:394) (472:472:472)) + (PORT datad (435:435:435) (508:508:508)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_ixy_dT2_2) + (DELAY + (ABSOLUTE + (PORT dataa (1103:1103:1103) (1153:1153:1153)) + (PORT datad (1747:1747:1747) (1803:1803:1803)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (972:972:972) (1011:1011:1011)) + (PORT datab (224:224:224) (272:272:272)) + (PORT datac (1378:1378:1378) (1466:1466:1466)) + (PORT datad (1261:1261:1261) (1305:1305:1305)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1417:1417:1417) (1473:1473:1473)) + (PORT datab (1714:1714:1714) (1790:1790:1790)) + (PORT datac (1605:1605:1605) (1674:1674:1674)) + (PORT datad (1247:1247:1247) (1293:1293:1293)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1127:1127:1127) (1134:1134:1134)) + (PORT datab (2242:2242:2242) (2356:2356:2356)) + (PORT datac (777:777:777) (839:839:839)) + (PORT datad (1950:1950:1950) (2093:2093:2093)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~5) + (DELAY + (ABSOLUTE + (PORT dataa (220:220:220) (264:264:264)) + (PORT datab (219:219:219) (258:258:258)) + (PORT datac (396:396:396) (479:479:479)) + (PORT datad (391:391:391) (460:460:460)) (IOPATH dataa combout (337:337:337) (338:338:338)) (IOPATH datab combout (337:337:337) (348:348:348)) (IOPATH datac combout (243:243:243) (241:241:241)) @@ -14374,15 +4200,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~47) + (INSTANCE z80_\|execute_\|ctl_sw_2u\~1) (DELAY (ABSOLUTE - (PORT dataa (399:399:399) (422:422:422)) - (PORT datab (212:212:212) (257:257:257)) - (PORT datac (620:620:620) (677:677:677)) - (PORT datad (196:196:196) (222:222:222)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) + (PORT dataa (430:430:430) (492:492:492)) + (PORT datab (2354:2354:2354) (2430:2430:2430)) + (PORT datac (1369:1369:1369) (1431:1431:1431)) + (PORT datad (598:598:598) (624:624:624)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -14390,13 +4216,463 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~74) + (INSTANCE z80_\|execute_\|ctl_alu_oe\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1729:1729:1729) (1799:1799:1799)) + (PORT datab (311:311:311) (410:410:410)) + (PORT datac (1831:1831:1831) (1860:1860:1860)) + (PORT datad (579:579:579) (596:596:596)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~7) + (DELAY + (ABSOLUTE + (PORT dataa (612:612:612) (647:647:647)) + (PORT datab (1863:1863:1863) (1897:1897:1897)) + (PORT datac (626:626:626) (642:642:642)) + (PORT datad (282:282:282) (366:366:366)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1108:1108:1108) (1170:1170:1170)) + (PORT datab (219:219:219) (256:256:256)) + (PORT datac (1087:1087:1087) (1107:1107:1107)) + (PORT datad (813:813:813) (842:842:842)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~57) + (DELAY + (ABSOLUTE + (PORT dataa (694:694:694) (753:753:753)) + (PORT datab (1124:1124:1124) (1226:1226:1226)) + (PORT datac (1262:1262:1262) (1293:1293:1293)) + (PORT datad (1389:1389:1389) (1445:1445:1445)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~5) + (DELAY + (ABSOLUTE + (PORT datab (866:866:866) (883:883:883)) + (PORT datac (820:820:820) (827:827:827)) + (PORT datad (1115:1115:1115) (1127:1127:1127)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~7) + (DELAY + (ABSOLUTE + (PORT dataa (965:965:965) (990:990:990)) + (PORT datab (883:883:883) (884:884:884)) + (PORT datac (791:791:791) (801:801:801)) + (PORT datad (190:190:190) (223:223:223)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla91pla21M4T2_3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2102:2102:2102) (2259:2259:2259)) + (PORT datab (1188:1188:1188) (1253:1253:1253)) + (PORT datac (1671:1671:1671) (1722:1722:1722)) + (PORT datad (1477:1477:1477) (1575:1575:1575)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~41) + (DELAY + (ABSOLUTE + (PORT dataa (2103:2103:2103) (2258:2258:2258)) + (PORT datab (1738:1738:1738) (1808:1808:1808)) + (PORT datac (2806:2806:2806) (2841:2841:2841)) + (PORT datad (919:919:919) (955:955:955)) + (IOPATH dataa combout (301:301:301) (307:307:307)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~86) + (DELAY + (ABSOLUTE + (PORT dataa (1571:1571:1571) (1698:1698:1698)) + (PORT datab (1204:1204:1204) (1284:1284:1284)) + (PORT datac (1739:1739:1739) (1846:1846:1846)) + (PORT datad (1296:1296:1296) (1412:1412:1412)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~88) + (DELAY + (ABSOLUTE + (PORT dataa (1572:1572:1572) (1693:1693:1693)) + (PORT datab (1731:1731:1731) (1827:1827:1827)) + (PORT datac (1616:1616:1616) (1726:1726:1726)) + (PORT datad (1535:1535:1535) (1631:1631:1631)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~36) + (DELAY + (ABSOLUTE + (PORT dataa (1309:1309:1309) (1363:1363:1363)) + (PORT datab (1381:1381:1381) (1462:1462:1462)) + (PORT datac (1162:1162:1162) (1215:1215:1215)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~87) + (DELAY + (ABSOLUTE + (PORT dataa (1573:1573:1573) (1694:1694:1694)) + (PORT datab (1320:1320:1320) (1444:1444:1444)) + (PORT datac (909:909:909) (943:943:943)) + (PORT datad (1538:1538:1538) (1632:1632:1632)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~26) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (255:255:255)) + (PORT datab (205:205:205) (247:247:247)) + (PORT datad (195:195:195) (220:220:220)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~9) + (DELAY + (ABSOLUTE + (PORT datab (1620:1620:1620) (1755:1755:1755)) + (PORT datac (1436:1436:1436) (1520:1520:1520)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~1) + (DELAY + (ABSOLUTE + (PORT dataa (2838:2838:2838) (2882:2882:2882)) + (PORT datab (957:957:957) (1006:1006:1006)) + (PORT datac (2067:2067:2067) (2222:2222:2222)) + (PORT datad (1102:1102:1102) (1126:1126:1126)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~42) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (583:583:583) (627:627:627)) + (PORT datad (181:181:181) (210:210:210)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal40\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1557:1557:1557) (1685:1685:1685)) + (PORT datab (1555:1555:1555) (1618:1618:1618)) + (PORT datac (1365:1365:1365) (1547:1547:1547)) + (PORT datad (1515:1515:1515) (1636:1636:1636)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~14) + (DELAY + (ABSOLUTE + (PORT dataa (649:649:649) (676:676:676)) + (PORT datab (1264:1264:1264) (1332:1332:1332)) + (PORT datac (2461:2461:2461) (2594:2594:2594)) + (PORT datad (1176:1176:1176) (1221:1221:1221)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal55\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1557:1557:1557) (1685:1685:1685)) + (PORT datac (1365:1365:1365) (1540:1540:1540)) + (PORT datad (1514:1514:1514) (1632:1632:1632)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1865:1865:1865) (1994:1994:1994)) + (PORT datab (1827:1827:1827) (1884:1884:1884)) + (PORT datac (681:681:681) (738:738:738)) + (PORT datad (1773:1773:1773) (1876:1876:1876)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal6\~1) + (DELAY + (ABSOLUTE + (PORT dataa (986:986:986) (1092:1092:1092)) + (PORT datab (1518:1518:1518) (1576:1576:1576)) + (PORT datac (1013:1013:1013) (1071:1071:1071)) + (PORT datad (1664:1664:1664) (1796:1796:1796)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~36) + (DELAY + (ABSOLUTE + (PORT dataa (1996:1996:1996) (2058:2058:2058)) + (PORT datab (2490:2490:2490) (2625:2625:2625)) + (PORT datac (918:918:918) (963:963:963)) + (PORT datad (1180:1180:1180) (1225:1225:1225)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|comb\~1) + (DELAY + (ABSOLUTE + (PORT datab (1098:1098:1098) (1228:1228:1228)) + (PORT datad (1614:1614:1614) (1668:1668:1668)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1119:1119:1119) (1149:1149:1149)) + (PORT datab (1657:1657:1657) (1753:1753:1753)) + (PORT datac (2114:2114:2114) (2210:2210:2210)) + (PORT datad (884:884:884) (939:939:939)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1389:1389:1389) (1413:1413:1413)) + (PORT datab (688:688:688) (747:747:747)) + (PORT datac (955:955:955) (1004:1004:1004)) + (PORT datad (656:656:656) (710:710:710)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal24\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1719:1719:1719) (1855:1855:1855)) + (PORT datab (668:668:668) (696:696:696)) + (PORT datac (2138:2138:2138) (2209:2209:2209)) + (PORT datad (659:659:659) (733:733:733)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~26) + (DELAY + (ABSOLUTE + (PORT dataa (1701:1701:1701) (1788:1788:1788)) + (PORT datab (2094:2094:2094) (2218:2218:2218)) + (PORT datac (1305:1305:1305) (1362:1362:1362)) + (PORT datad (667:667:667) (713:713:713)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~37) + (DELAY + (ABSOLUTE + (PORT dataa (1433:1433:1433) (1498:1498:1498)) + (PORT datab (196:196:196) (235:235:235)) + (PORT datac (614:614:614) (647:647:647)) + (PORT datad (194:194:194) (218:218:218)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~6) (DELAY (ABSOLUTE (PORT dataa (222:222:222) (266:266:266)) - (PORT datab (219:219:219) (258:258:258)) - (PORT datac (881:881:881) (895:895:895)) - (PORT datad (195:195:195) (221:221:221)) + (PORT datab (631:631:631) (652:652:652)) + (PORT datac (828:828:828) (841:841:841)) + (PORT datad (630:630:630) (657:657:657)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\~38) + (DELAY + (ABSOLUTE + (PORT dataa (721:721:721) (782:782:782)) + (PORT datab (1830:1830:1830) (1887:1887:1887)) + (PORT datac (1347:1347:1347) (1345:1345:1345)) + (PORT datad (943:943:943) (965:965:965)) (IOPATH dataa combout (324:324:324) (328:328:328)) (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -14404,16 +4680,310 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1452:1452:1452) (1556:1556:1556)) + (PORT datab (226:226:226) (266:266:266)) + (PORT datac (883:883:883) (918:918:918)) + (PORT datad (182:182:182) (212:212:212)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1216:1216:1216) (1308:1308:1308)) + (PORT datab (987:987:987) (1068:1068:1068)) + (PORT datad (1628:1628:1628) (1638:1638:1638)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~31) + (DELAY + (ABSOLUTE + (PORT dataa (913:913:913) (975:975:975)) + (PORT datab (1308:1308:1308) (1391:1391:1391)) + (PORT datac (680:680:680) (711:711:711)) + (PORT datad (1971:1971:1971) (2146:2146:2146)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla38pla13M4T2_4) + (DELAY + (ABSOLUTE + (PORT dataa (943:943:943) (967:967:967)) + (PORT datab (922:922:922) (975:975:975)) + (PORT datac (568:568:568) (579:579:579)) + (PORT datad (1619:1619:1619) (1707:1707:1707)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|nM1_int\~2) + (DELAY + (ABSOLUTE + (PORT datac (1641:1641:1641) (1746:1746:1746)) + (PORT datad (1900:1900:1900) (2003:2003:2003)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~0) + (DELAY + (ABSOLUTE + (PORT datab (1789:1789:1789) (1892:1892:1892)) + (PORT datad (1246:1246:1246) (1310:1310:1310)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (994:994:994) (1039:1039:1039)) + (PORT datab (867:867:867) (909:909:909)) + (PORT datac (1176:1176:1176) (1197:1197:1197)) + (PORT datad (659:659:659) (707:707:707)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~6) + (DELAY + (ABSOLUTE + (PORT dataa (641:641:641) (664:664:664)) + (PORT datab (934:934:934) (998:998:998)) + (PORT datac (678:678:678) (726:726:726)) + (PORT datad (202:202:202) (232:232:232)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~12) + (DELAY + (ABSOLUTE + (PORT dataa (955:955:955) (1060:1060:1060)) + (PORT datab (1248:1248:1248) (1295:1295:1295)) + (PORT datac (1533:1533:1533) (1659:1659:1659)) + (PORT datad (1298:1298:1298) (1350:1350:1350)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1583:1583:1583) (1713:1713:1713)) + (PORT datab (1362:1362:1362) (1389:1389:1389)) + (PORT datac (188:188:188) (229:229:229)) + (PORT datad (1348:1348:1348) (1437:1437:1437)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal25\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1441:1441:1441) (1529:1529:1529)) + (PORT datab (1660:1660:1660) (1746:1746:1746)) + (PORT datac (1595:1595:1595) (1726:1726:1726)) + (PORT datad (881:881:881) (930:930:930)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal12\~1) + (DELAY + (ABSOLUTE + (PORT dataa (984:984:984) (1094:1094:1094)) + (PORT datab (1515:1515:1515) (1578:1578:1578)) + (PORT datac (2137:2137:2137) (2207:2207:2207)) + (PORT datad (1670:1670:1670) (1805:1805:1805)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~38) + (DELAY + (ABSOLUTE + (PORT dataa (1435:1435:1435) (1450:1450:1450)) + (PORT datab (1976:1976:1976) (2129:2129:2129)) + (PORT datac (608:608:608) (643:643:643)) + (PORT datad (202:202:202) (233:233:233)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~82) + (DELAY + (ABSOLUTE + (PORT dataa (1290:1290:1290) (1410:1410:1410)) + (PORT datab (1526:1526:1526) (1587:1587:1587)) + (PORT datad (1494:1494:1494) (1581:1581:1581)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1199:1199:1199) (1261:1261:1261)) + (PORT datab (611:611:611) (639:639:639)) + (PORT datac (582:582:582) (623:623:623)) + (PORT datad (624:624:624) (638:638:638)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (354:354:354) (389:389:389)) + (PORT datab (1498:1498:1498) (1530:1530:1530)) + (PORT datac (194:194:194) (226:226:226)) + (PORT datad (179:179:179) (209:209:209)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~32) + (DELAY + (ABSOLUTE + (PORT dataa (229:229:229) (276:276:276)) + (PORT datab (228:228:228) (270:270:270)) + (PORT datac (1668:1668:1668) (1696:1696:1696)) + (PORT datad (607:607:607) (625:625:625)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~77) + (DELAY + (ABSOLUTE + (PORT dataa (1296:1296:1296) (1355:1355:1355)) + (PORT datab (1560:1560:1560) (1682:1682:1682)) + (PORT datac (862:862:862) (878:878:878)) + (PORT datad (2069:2069:2069) (2098:2098:2098)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal29\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1307:1307:1307) (1384:1384:1384)) + (PORT datab (896:896:896) (927:927:927)) + (PORT datac (752:752:752) (852:852:852)) + (PORT datad (1765:1765:1765) (1838:1838:1838)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_inc_cy\~78) (DELAY (ABSOLUTE - (PORT datab (206:206:206) (248:248:248)) - (PORT datac (636:636:636) (661:661:661)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (1295:1295:1295) (1357:1357:1357)) + (PORT datab (1558:1558:1558) (1684:1684:1684)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (1091:1091:1091) (1143:1143:1143)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -14423,184 +4993,12 @@ (INSTANCE z80_\|execute_\|ctl_inc_cy\~79) (DELAY (ABSOLUTE - (PORT dataa (209:209:209) (257:257:257)) - (PORT datab (341:341:341) (376:376:376)) - (PORT datac (639:639:639) (674:674:674)) - (PORT datad (182:182:182) (213:213:213)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~80) - (DELAY - (ABSOLUTE - (PORT dataa (676:676:676) (725:725:725)) - (PORT datab (911:911:911) (985:985:985)) - (PORT datac (1190:1190:1190) (1272:1272:1272)) - (PORT datad (188:188:188) (220:220:220)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~81) - (DELAY - (ABSOLUTE - (PORT dataa (868:868:868) (915:915:915)) - (PORT datab (682:682:682) (741:741:741)) - (PORT datac (965:965:965) (1027:1027:1027)) - (PORT datad (621:621:621) (668:668:668)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~82) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (241:241:241)) - (PORT datab (684:684:684) (749:749:749)) - (PORT datac (972:972:972) (1033:1033:1033)) - (PORT datad (1668:1668:1668) (1690:1690:1690)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~83) - (DELAY - (ABSOLUTE - (PORT dataa (207:207:207) (255:255:255)) - (PORT datab (340:340:340) (370:370:370)) - (PORT datac (638:638:638) (672:672:672)) - (PORT datad (357:357:357) (377:377:377)) + (PORT dataa (229:229:229) (275:275:275)) + (PORT datab (2237:2237:2237) (2351:2351:2351)) + (PORT datac (798:798:798) (857:857:857)) + (PORT datad (1951:1951:1951) (2095:2095:2095)) (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~84) - (DELAY - (ABSOLUTE - (PORT datab (205:205:205) (245:245:245)) - (PORT datac (179:179:179) (215:215:215)) - (PORT datad (180:180:180) (207:207:207)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~42) - (DELAY - (ABSOLUTE - (PORT datab (652:652:652) (687:687:687)) - (PORT datac (339:339:339) (370:370:370)) - (PORT datad (180:180:180) (209:209:209)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~90) - (DELAY - (ABSOLUTE - (PORT dataa (1017:1017:1017) (1099:1099:1099)) - (PORT datab (1086:1086:1086) (1123:1123:1123)) - (PORT datac (1171:1171:1171) (1232:1232:1232)) - (PORT datad (1497:1497:1497) (1611:1611:1611)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~41) - (DELAY - (ABSOLUTE - (PORT dataa (227:227:227) (279:279:279)) - (PORT datab (627:627:627) (674:674:674)) - (PORT datac (208:208:208) (246:246:246)) - (PORT datad (180:180:180) (207:207:207)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~66) - (DELAY - (ABSOLUTE - (PORT dataa (355:355:355) (494:494:494)) - (PORT datab (902:902:902) (935:935:935)) - (PORT datac (1178:1178:1178) (1261:1261:1261)) - (PORT datad (273:273:273) (355:355:355)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~67) - (DELAY - (ABSOLUTE - (PORT dataa (1111:1111:1111) (1166:1166:1166)) - (PORT datab (227:227:227) (270:270:270)) - (PORT datac (194:194:194) (242:242:242)) - (PORT datad (872:872:872) (923:923:923)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~68) - (DELAY - (ABSOLUTE - (PORT dataa (1443:1443:1443) (1505:1505:1505)) - (PORT datab (196:196:196) (234:234:234)) - (PORT datac (170:170:170) (202:202:202)) - (PORT datad (1642:1642:1642) (1712:1712:1712)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -14608,64 +5006,16 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~64) + (INSTANCE z80_\|execute_\|ctl_mRead\~14) (DELAY (ABSOLUTE - (PORT dataa (1110:1110:1110) (1166:1166:1166)) - (PORT datab (235:235:235) (278:278:278)) - (PORT datac (195:195:195) (241:241:241)) - (PORT datad (596:596:596) (630:630:630)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~63) - (DELAY - (ABSOLUTE - (PORT dataa (883:883:883) (888:888:888)) - (PORT datab (1133:1133:1133) (1145:1145:1145)) - (PORT datac (343:343:343) (372:372:372)) - (PORT datad (854:854:854) (886:886:886)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~65) - (DELAY - (ABSOLUTE - (PORT dataa (1157:1157:1157) (1221:1221:1221)) - (PORT datab (375:375:375) (398:398:398)) - (PORT datac (308:308:308) (325:325:325)) - (PORT datad (171:171:171) (196:196:196)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~69) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (330:330:330) (348:348:348)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (986:986:986) (1097:1097:1097)) + (PORT datab (665:665:665) (693:693:693)) + (PORT datac (1163:1163:1163) (1260:1260:1260)) + (PORT datad (634:634:634) (689:689:689)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -14675,44 +5025,12 @@ (INSTANCE z80_\|execute_\|ctl_inc_cy\~49) (DELAY (ABSOLUTE - (PORT dataa (663:663:663) (715:715:715)) - (PORT datab (410:410:410) (440:440:440)) - (PORT datac (1131:1131:1131) (1156:1156:1156)) - (PORT datad (854:854:854) (887:887:887)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~50) - (DELAY - (ABSOLUTE - (PORT dataa (663:663:663) (719:719:719)) - (PORT datab (946:946:946) (985:985:985)) - (PORT datac (1123:1123:1123) (1165:1165:1165)) - (PORT datad (1721:1721:1721) (1778:1778:1778)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~51) - (DELAY - (ABSOLUTE - (PORT dataa (372:372:372) (395:395:395)) - (PORT datab (1129:1129:1129) (1184:1184:1184)) - (PORT datac (1040:1040:1040) (1054:1054:1054)) - (PORT datad (1204:1204:1204) (1229:1229:1229)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (306:306:306) (308:308:308)) + (PORT dataa (1591:1591:1591) (1643:1643:1643)) + (PORT datab (1268:1268:1268) (1301:1301:1301)) + (PORT datac (1030:1030:1030) (1104:1104:1104)) + (PORT datad (2454:2454:2454) (2625:2625:2625)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -14720,29 +5038,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~52) + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~5) (DELAY (ABSOLUTE - (PORT dataa (657:657:657) (717:717:717)) - (PORT datab (921:921:921) (959:959:959)) - (PORT datac (913:913:913) (949:949:949)) - (PORT datad (313:313:313) (331:331:331)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~36) - (DELAY - (ABSOLUTE - (PORT dataa (902:902:902) (981:981:981)) - (PORT datab (893:893:893) (932:932:932)) - (PORT datac (1434:1434:1434) (1470:1470:1470)) - (PORT datad (843:843:843) (890:890:890)) + (PORT dataa (948:948:948) (995:995:995)) + (PORT datab (955:955:955) (1002:1002:1002)) + (PORT datac (2810:2810:2810) (2843:2843:2843)) + (PORT datad (2455:2455:2455) (2623:2623:2623)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (310:310:310)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -14752,910 +5054,30 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~37) + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~40) (DELAY (ABSOLUTE - (PORT dataa (1466:1466:1466) (1512:1512:1512)) - (PORT datab (915:915:915) (968:968:968)) - (PORT datac (321:321:321) (356:356:356)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~54) - (DELAY - (ABSOLUTE - (PORT dataa (227:227:227) (280:280:280)) - (PORT datab (200:200:200) (239:239:239)) - (PORT datac (170:170:170) (202:202:202)) - (PORT datad (588:588:588) (601:601:601)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~41) - (DELAY - (ABSOLUTE - (PORT dataa (1188:1188:1188) (1234:1234:1234)) - (PORT datab (1144:1144:1144) (1214:1214:1214)) - (PORT datac (364:364:364) (396:396:396)) - (PORT datad (1141:1141:1141) (1188:1188:1188)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~58) - (DELAY - (ABSOLUTE - (PORT dataa (1122:1122:1122) (1132:1132:1132)) - (PORT datab (1153:1153:1153) (1193:1193:1193)) - (PORT datad (195:195:195) (220:220:220)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~55) - (DELAY - (ABSOLUTE - (PORT dataa (956:956:956) (987:987:987)) - (PORT datab (921:921:921) (959:959:959)) - (PORT datac (635:635:635) (676:676:676)) - (PORT datad (1543:1543:1543) (1626:1626:1626)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~56) - (DELAY - (ABSOLUTE - (PORT dataa (457:457:457) (498:498:498)) - (PORT datab (219:219:219) (258:258:258)) - (PORT datac (805:805:805) (826:826:826)) - (PORT datad (195:195:195) (220:220:220)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~89) - (DELAY - (ABSOLUTE - (PORT dataa (1333:1333:1333) (1437:1437:1437)) - (PORT datab (1163:1163:1163) (1169:1169:1169)) - (PORT datac (1430:1430:1430) (1469:1469:1469)) - (PORT datad (844:844:844) (894:894:894)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~57) - (DELAY - (ABSOLUTE - (PORT dataa (207:207:207) (254:254:254)) - (PORT datab (828:828:828) (830:830:830)) - (PORT datac (314:314:314) (333:333:333)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~59) - (DELAY - (ABSOLUTE - (PORT dataa (907:907:907) (937:937:937)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (590:590:590) (602:602:602)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~60) - (DELAY - (ABSOLUTE - (PORT dataa (1157:1157:1157) (1220:1220:1220)) - (PORT datab (218:218:218) (256:256:256)) - (PORT datac (563:563:563) (566:566:566)) - (PORT datad (559:559:559) (582:582:582)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~47) - (DELAY - (ABSOLUTE - (PORT dataa (1096:1096:1096) (1139:1139:1139)) - (PORT datab (213:213:213) (256:256:256)) - (PORT datac (1061:1061:1061) (1099:1099:1099)) - (PORT datad (189:189:189) (222:222:222)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~88) - (DELAY - (ABSOLUTE - (PORT dataa (1618:1618:1618) (1736:1736:1736)) - (PORT datab (867:867:867) (905:905:905)) - (PORT datac (2517:2517:2517) (2622:2622:2622)) - (PORT datad (1493:1493:1493) (1607:1607:1607)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~48) - (DELAY - (ABSOLUTE - (PORT dataa (592:592:592) (611:611:611)) - (PORT datab (580:580:580) (593:593:593)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (1133:1133:1133) (1184:1184:1184)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~40) - (DELAY - (ABSOLUTE - (PORT datab (652:652:652) (686:686:686)) - (PORT datac (338:338:338) (369:369:369)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~61) - (DELAY - (ABSOLUTE - (PORT dataa (230:230:230) (277:277:277)) - (PORT datab (214:214:214) (259:259:259)) - (PORT datac (1058:1058:1058) (1099:1099:1099)) - (PORT datad (1134:1134:1134) (1161:1161:1161)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~62) - (DELAY - (ABSOLUTE - (PORT dataa (1157:1157:1157) (1225:1225:1225)) - (PORT datab (197:197:197) (237:237:237)) - (PORT datac (551:551:551) (564:564:564)) - (PORT datad (399:399:399) (430:430:430)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~70) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (169:169:169) (201:201:201)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~85) - (DELAY - (ABSOLUTE - (PORT dataa (1122:1122:1122) (1138:1138:1138)) - (PORT datab (1105:1105:1105) (1122:1122:1122)) - (PORT datac (1065:1065:1065) (1088:1088:1088)) - (PORT datad (1172:1172:1172) (1217:1217:1217)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|d0_out) - (DELAY - (ABSOLUTE - (PORT datac (700:700:700) (784:784:784)) - (PORT datad (365:365:365) (386:386:386)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (958:958:958) (1001:1001:1001)) - (PORT datac (681:681:681) (720:720:720)) - (PORT datad (339:339:339) (361:361:361)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[0\]) - (DELAY - (ABSOLUTE - (PORT datac (1006:1006:1006) (1012:1012:1012)) - (PORT datad (924:924:924) (943:943:943)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|Q\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (179:179:179) (207:207:207)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1560:1560:1560)) - (PORT ena (2096:2096:2096) (2133:2133:2133)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_41) - (DELAY - (ABSOLUTE - (PORT dataa (1158:1158:1158) (1184:1184:1184)) - (PORT datab (989:989:989) (1022:1022:1022)) - (PORT datac (696:696:696) (778:778:778)) - (PORT datad (201:201:201) (229:229:229)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1541:1541:1541) (1557:1557:1557)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1283:1283:1283) (1286:1286:1286)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (985:985:985) (1033:1033:1033)) - (PORT ena (1201:1201:1201) (1184:1184:1184)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (356:356:356) (396:396:396)) - (PORT datab (697:697:697) (726:726:726)) - (PORT datad (1194:1194:1194) (1231:1231:1231)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~5) - (DELAY - (ABSOLUTE - (PORT datab (740:740:740) (774:774:774)) - (PORT datac (217:217:217) (294:294:294)) - (PORT datad (608:608:608) (657:657:657)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|d1_out) - (DELAY - (ABSOLUTE - (PORT dataa (845:845:845) (905:905:905)) - (PORT datab (402:402:402) (425:425:425)) - (PORT datac (194:194:194) (227:227:227)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (244:244:244)) - (PORT datab (959:959:959) (1000:1000:1000)) - (PORT datac (683:683:683) (721:721:721)) - (PORT datad (341:341:341) (359:359:359)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[1\]) - (DELAY - (ABSOLUTE - (PORT datab (396:396:396) (421:421:421)) - (PORT datad (345:345:345) (371:371:371)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1541:1541:1541) (1557:1557:1557)) - (PORT asdata (537:537:537) (568:568:568)) - (PORT clrn (1597:1597:1597) (1572:1572:1572)) - (PORT ena (2143:2143:2143) (2210:2210:2210)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_40\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1005:1005:1005) (1069:1069:1069)) - (PORT datab (1154:1154:1154) (1178:1178:1178)) - (PORT datac (812:812:812) (866:866:866)) - (PORT datad (359:359:359) (383:383:383)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|d0_out) - (DELAY - (ABSOLUTE - (PORT dataa (416:416:416) (443:443:443)) - (PORT datab (219:219:219) (258:258:258)) - (PORT datac (236:236:236) (311:311:311)) - (PORT datad (327:327:327) (348:348:348)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (716:716:716) (758:758:758)) - (PORT datab (962:962:962) (1001:1001:1001)) - (PORT datac (617:617:617) (670:670:670)) - (PORT datad (532:532:532) (544:544:544)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[2\]) - (DELAY - (ABSOLUTE - (PORT dataa (553:553:553) (579:579:579)) - (PORT datad (214:214:214) (247:247:247)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|Q\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (195:195:195) (220:220:220)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1541:1541:1541) (1557:1557:1557)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1597:1597:1597) (1572:1572:1572)) - (PORT ena (2146:2146:2146) (2210:2210:2210)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_42) - (DELAY - (ABSOLUTE - (PORT dataa (386:386:386) (424:424:424)) - (PORT datab (1154:1154:1154) (1182:1182:1182)) - (PORT datac (966:966:966) (1033:1033:1033)) - (PORT datad (394:394:394) (449:449:449)) + (PORT dataa (1470:1470:1470) (1524:1524:1524)) + (PORT datab (214:214:214) (258:258:258)) + (PORT datac (187:187:187) (227:227:227)) (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_cy\~86) - (DELAY - (ABSOLUTE - (PORT dataa (220:220:220) (263:263:263)) - (PORT datab (205:205:205) (247:247:247)) - (PORT datac (178:178:178) (213:213:213)) - (PORT datad (179:179:179) (208:208:208)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|SYNTHESIZED_WIRE_0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (412:412:412) (441:441:441)) - (PORT datab (1103:1103:1103) (1121:1121:1121)) - (PORT datac (1068:1068:1068) (1079:1079:1079)) - (PORT datad (1177:1177:1177) (1222:1222:1222)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_inc_dec\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1155:1155:1155) (1182:1182:1182)) - (PORT datab (983:983:983) (1021:1021:1021)) - (PORT datac (960:960:960) (1025:1025:1025)) - (PORT datad (1127:1127:1127) (1138:1138:1138)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|carry_borrow_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (846:846:846) (907:907:907)) - (PORT datab (1376:1376:1376) (1400:1400:1400)) - (PORT datac (695:695:695) (778:778:778)) - (PORT datad (369:369:369) (389:389:389)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|d1_out) - (DELAY - (ABSOLUTE - (PORT datab (205:205:205) (247:247:247)) - (PORT datac (331:331:331) (357:357:357)) - (PORT datad (244:244:244) (316:316:316)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1545:1545:1545)) - (PORT asdata (1394:1394:1394) (1425:1425:1425)) - (PORT ena (821:821:821) (834:834:834)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1545:1545:1545)) - (PORT asdata (1396:1396:1396) (1427:1427:1427)) - (PORT ena (1266:1266:1266) (1269:1269:1269)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~45) - (DELAY - (ABSOLUTE - (PORT dataa (413:413:413) (478:478:478)) - (PORT datab (593:593:593) (633:633:633)) - (PORT datad (219:219:219) (288:288:288)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[3\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (815:815:815) (857:857:857)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1534:1534:1534)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1407:1407:1407) (1382:1382:1382)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1520:1520:1520) (1534:1534:1534)) - (PORT asdata (1165:1165:1165) (1197:1197:1197)) - (PORT ena (1263:1263:1263) (1264:1264:1264)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~48) - (DELAY - (ABSOLUTE - (PORT dataa (617:617:617) (678:678:678)) - (PORT datab (842:842:842) (870:870:870)) - (PORT datad (643:643:643) (672:672:672)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1545:1545:1545)) - (PORT asdata (1201:1201:1201) (1243:1243:1243)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1545:1545:1545)) - (PORT asdata (1200:1200:1200) (1247:1247:1247)) - (PORT ena (1220:1220:1220) (1214:1214:1214)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~49) - (DELAY - (ABSOLUTE - (PORT dataa (645:645:645) (705:705:705)) - (PORT datab (245:245:245) (328:328:328)) - (PORT datad (369:369:369) (400:400:400)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[3\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (812:812:812) (855:855:855)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1534:1534:1534)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1505:1505:1505) (1518:1518:1518)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1520:1520:1520) (1534:1534:1534)) - (PORT asdata (1168:1168:1168) (1200:1200:1200)) - (PORT ena (1207:1207:1207) (1190:1190:1190)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~41) - (DELAY - (ABSOLUTE - (PORT dataa (934:934:934) (963:963:963)) - (PORT datab (606:606:606) (617:617:617)) - (PORT datac (548:548:548) (570:570:570)) - (PORT datad (1519:1519:1519) (1633:1633:1633)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~42) - (DELAY - (ABSOLUTE - (PORT dataa (968:968:968) (1020:1020:1020)) - (PORT datab (580:580:580) (595:595:595)) - (PORT datac (1000:1000:1000) (1021:1021:1021)) - (PORT datad (861:861:861) (896:896:896)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datab combout (331:331:331) (342:342:342)) (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~43) + (INSTANCE z80_\|execute_\|ctl_mRead\~5) (DELAY (ABSOLUTE - (PORT dataa (221:221:221) (264:264:264)) - (PORT datab (681:681:681) (737:737:737)) - (PORT datac (172:172:172) (206:206:206)) - (PORT datad (171:171:171) (196:196:196)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (1216:1216:1216) (1312:1312:1312)) + (PORT datab (1851:1851:1851) (1863:1863:1863)) + (PORT datac (921:921:921) (968:968:968)) + (PORT datad (950:950:950) (1030:1030:1030)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -15665,26 +5087,10 @@ (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~44) (DELAY (ABSOLUTE - (PORT dataa (542:542:542) (562:562:562)) - (PORT datab (612:612:612) (638:638:638)) - (PORT datac (854:854:854) (888:888:888)) - (PORT datad (607:607:607) (635:635:635)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~45) - (DELAY - (ABSOLUTE - (PORT dataa (624:624:624) (687:687:687)) - (PORT datab (643:643:643) (681:681:681)) - (PORT datac (1161:1161:1161) (1210:1210:1210)) - (PORT datad (581:581:581) (616:616:616)) + (PORT dataa (656:656:656) (699:699:699)) + (PORT datab (494:494:494) (576:576:576)) + (PORT datac (567:567:567) (592:592:592)) + (PORT datad (452:452:452) (532:532:532)) (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -15694,29 +5100,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~46) + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~36) (DELAY (ABSOLUTE - (PORT dataa (207:207:207) (255:255:255)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (603:603:603) (634:634:634)) - (PORT datad (181:181:181) (210:210:210)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_48) - (DELAY - (ABSOLUTE - (PORT datab (1437:1437:1437) (1505:1505:1505)) - (PORT datac (1211:1211:1211) (1273:1273:1273)) - (PORT datad (849:849:849) (886:886:886)) - (IOPATH datab combout (304:304:304) (311:311:311)) + (PORT dataa (1199:1199:1199) (1255:1255:1255)) + (PORT datab (861:861:861) (876:876:876)) + (PORT datac (897:897:897) (928:928:928)) + (PORT datad (945:945:945) (998:998:998)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -15724,102 +5116,45 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_44) + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~35) (DELAY (ABSOLUTE - (PORT datab (1435:1435:1435) (1506:1506:1506)) - (PORT datac (1214:1214:1214) (1277:1277:1277)) - (PORT datad (841:841:841) (870:870:870)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (1212:1212:1212) (1298:1298:1298)) + (PORT datab (1168:1168:1168) (1213:1213:1213)) + (PORT datad (618:618:618) (642:642:642)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_45) + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~46) (DELAY (ABSOLUTE - (PORT datab (1431:1431:1431) (1499:1499:1499)) - (PORT datac (1202:1202:1202) (1265:1265:1265)) - (PORT datad (842:842:842) (868:868:868)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1537:1537:1537)) - (PORT asdata (1009:1009:1009) (1065:1065:1065)) - (PORT ena (990:990:990) (994:994:994)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_49) - (DELAY - (ABSOLUTE - (PORT datab (1431:1431:1431) (1500:1500:1500)) - (PORT datac (1204:1204:1204) (1267:1267:1267)) - (PORT datad (851:851:851) (887:887:887)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1537:1537:1537)) - (PORT asdata (1012:1012:1012) (1067:1067:1067)) - (PORT ena (973:973:973) (964:964:964)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~40) - (DELAY - (ABSOLUTE - (PORT dataa (461:461:461) (523:523:523)) - (PORT datab (490:490:490) (541:541:541)) - (PORT datad (217:217:217) (285:285:285)) + (PORT dataa (1793:1793:1793) (1881:1881:1881)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (1680:1680:1680) (1774:1774:1774)) + (PORT datad (173:173:173) (199:199:199)) (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_52) + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~33) (DELAY (ABSOLUTE - (PORT datab (1436:1436:1436) (1501:1501:1501)) - (PORT datac (1209:1209:1209) (1271:1271:1271)) - (PORT datad (1072:1072:1072) (1103:1103:1103)) - (IOPATH datab combout (304:304:304) (311:311:311)) + (PORT dataa (1197:1197:1197) (1236:1236:1236)) + (PORT datab (950:950:950) (991:991:991)) + (PORT datac (1433:1433:1433) (1477:1477:1477)) + (PORT datad (636:636:636) (679:679:679)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -15827,73 +5162,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_57) + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~47) (DELAY (ABSOLUTE - (PORT datab (1436:1436:1436) (1506:1506:1506)) - (PORT datac (1213:1213:1213) (1276:1276:1276)) - (PORT datad (987:987:987) (1036:1036:1036)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (1181:1181:1181) (1200:1200:1200)) - (PORT ena (1400:1400:1400) (1413:1413:1413)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_53) - (DELAY - (ABSOLUTE - (PORT datab (1437:1437:1437) (1502:1502:1502)) - (PORT datac (1212:1212:1212) (1275:1275:1275)) - (PORT datad (1074:1074:1074) (1101:1101:1101)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (1183:1183:1183) (1203:1203:1203)) - (PORT ena (1388:1388:1388) (1427:1427:1427)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_56) - (DELAY - (ABSOLUTE - (PORT datab (1438:1438:1438) (1503:1503:1503)) - (PORT datac (1218:1218:1218) (1279:1279:1279)) - (PORT datad (985:985:985) (1032:1032:1032)) - (IOPATH datab combout (304:304:304) (311:311:311)) + (PORT dataa (1552:1552:1552) (1656:1656:1656)) + (PORT datab (1179:1179:1179) (1236:1236:1236)) + (PORT datac (1130:1130:1130) (1165:1165:1165)) + (PORT datad (2516:2516:2516) (2622:2622:2622)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -15901,135 +5178,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~41) + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla9M1T5_2) (DELAY (ABSOLUTE - (PORT dataa (929:929:929) (988:988:988)) - (PORT datab (242:242:242) (325:325:325)) - (PORT datad (882:882:882) (948:948:948)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_33) - (DELAY - (ABSOLUTE - (PORT datab (1221:1221:1221) (1292:1292:1292)) - (PORT datac (894:894:894) (941:941:941)) - (PORT datad (886:886:886) (945:945:945)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (1204:1204:1204) (1243:1243:1243)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[3\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (936:936:936) (997:997:997)) - (PORT datab (1221:1221:1221) (1285:1285:1285)) - (PORT datad (879:879:879) (935:935:935)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1180:1180:1180) (1217:1217:1217)) - (PORT datab (204:204:204) (246:246:246)) - (PORT datac (1821:1821:1821) (1898:1898:1898)) - (PORT datad (203:203:203) (239:239:239)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~12) - (DELAY - (ABSOLUTE - (PORT dataa (883:883:883) (899:899:899)) - (PORT datab (206:206:206) (247:247:247)) - (PORT datac (601:601:601) (662:662:662)) - (PORT datad (870:870:870) (912:912:912)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_29) - (DELAY - (ABSOLUTE - (PORT dataa (1473:1473:1473) (1527:1527:1527)) - (PORT datac (833:833:833) (838:838:838)) - (PORT datad (1122:1122:1122) (1157:1157:1157)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1534:1534:1534)) - (PORT asdata (981:981:981) (1026:1026:1026)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_28) - (DELAY - (ABSOLUTE - (PORT dataa (1475:1475:1475) (1527:1527:1527)) - (PORT datac (835:835:835) (838:838:838)) - (PORT datad (1125:1125:1125) (1158:1158:1158)) - (IOPATH dataa combout (341:341:341) (347:347:347)) + (PORT dataa (1075:1075:1075) (1128:1128:1128)) + (PORT datab (1701:1701:1701) (1724:1724:1724)) + (PORT datac (838:838:838) (929:929:929)) + (PORT datad (964:964:964) (1036:1036:1036)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -16037,80 +5194,59 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~44) + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~45) (DELAY (ABSOLUTE - (PORT dataa (1083:1083:1083) (1099:1099:1099)) - (PORT datab (1166:1166:1166) (1217:1217:1217)) - (PORT datad (239:239:239) (279:279:279)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) + (PORT dataa (948:948:948) (1000:1000:1000)) + (PORT datab (1783:1783:1783) (1888:1888:1888)) + (PORT datac (1549:1549:1549) (1647:1647:1647)) + (PORT datad (1812:1812:1812) (1928:1928:1928)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[3\]\~feeder) + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~34) (DELAY (ABSOLUTE - (PORT datad (656:656:656) (709:709:709)) + (PORT dataa (952:952:952) (965:965:965)) + (PORT datab (980:980:980) (1032:1032:1032)) + (PORT datac (1654:1654:1654) (1682:1682:1682)) + (PORT datad (616:616:616) (638:638:638)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_69) + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla10M5T4_2) (DELAY (ABSOLUTE - (PORT datab (1122:1122:1122) (1149:1149:1149)) - (PORT datac (1397:1397:1397) (1448:1448:1448)) - (PORT datad (822:822:822) (857:857:857)) - (IOPATH datab combout (306:306:306) (308:308:308)) + (PORT dataa (1213:1213:1213) (1267:1267:1267)) + (PORT datac (1299:1299:1299) (1398:1398:1398)) + (PORT datad (1818:1818:1818) (1895:1895:1895)) + (IOPATH dataa combout (304:304:304) (307:307:307)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_68\~2) + (INSTANCE z80_\|execute_\|ctl_mWrite\~6) (DELAY (ABSOLUTE - (PORT dataa (929:929:929) (987:987:987)) - (PORT datab (1220:1220:1220) (1288:1288:1288)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_64\~0) - (DELAY - (ABSOLUTE - (PORT dataa (403:403:403) (454:454:454)) - (PORT datab (944:944:944) (1025:1025:1025)) - (PORT datac (1146:1146:1146) (1186:1186:1186)) - (PORT datad (666:666:666) (686:686:686)) + (PORT dataa (986:986:986) (1093:1093:1093)) + (PORT datab (1089:1089:1089) (1155:1155:1155)) + (PORT datac (630:630:630) (653:653:653)) + (PORT datad (1665:1665:1665) (1798:1798:1798)) (IOPATH dataa combout (324:324:324) (328:328:328)) (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -16120,11 +5256,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_69\~2) + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~50) (DELAY (ABSOLUTE - (PORT datac (1438:1438:1438) (1484:1484:1484)) - (PORT datad (1123:1123:1123) (1155:1155:1155)) + (PORT dataa (1148:1148:1148) (1201:1201:1201)) + (PORT datab (987:987:987) (1049:1049:1049)) + (PORT datac (990:990:990) (1074:1074:1074)) + (PORT datad (1286:1286:1286) (1359:1359:1359)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (370:370:370) (422:422:422)) + (PORT datab (392:392:392) (422:422:422)) + (PORT datac (1279:1279:1279) (1371:1371:1371)) + (PORT datad (194:194:194) (220:220:220)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -16132,44 +5288,500 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_65\~0) + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~48) (DELAY (ABSOLUTE - (PORT dataa (1170:1170:1170) (1265:1265:1265)) - (PORT datab (813:813:813) (832:832:832)) - (PORT datac (1134:1134:1134) (1171:1171:1171)) - (PORT datad (664:664:664) (713:713:713)) + (PORT dataa (347:347:347) (386:386:386)) + (PORT datab (870:870:870) (966:966:966)) + (PORT datac (814:814:814) (864:864:864)) + (PORT datad (963:963:963) (1033:1033:1033)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~49) + (DELAY + (ABSOLUTE + (PORT dataa (1009:1009:1009) (1108:1108:1108)) + (PORT datab (685:685:685) (743:743:743)) + (PORT datac (1211:1211:1211) (1287:1287:1287)) + (PORT datad (1529:1529:1529) (1619:1619:1619)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~7) + (DELAY + (ABSOLUTE + (PORT dataa (941:941:941) (968:968:968)) + (PORT datab (922:922:922) (974:974:974)) + (PORT datad (1618:1618:1618) (1707:1707:1707)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~29) + (DELAY + (ABSOLUTE + (PORT dataa (998:998:998) (1048:1048:1048)) + (PORT datab (1493:1493:1493) (1551:1551:1551)) + (PORT datac (1064:1064:1064) (1089:1089:1089)) + (PORT datad (1628:1628:1628) (1750:1750:1750)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~11) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (266:266:266)) + (PORT datab (241:241:241) (280:280:280)) + (PORT datac (2369:2369:2369) (2479:2479:2479)) + (PORT datad (992:992:992) (1075:1075:1075)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~27) + (DELAY + (ABSOLUTE + (PORT dataa (1386:1386:1386) (1429:1429:1429)) + (PORT datab (630:630:630) (663:663:663)) + (PORT datac (952:952:952) (1007:1007:1007)) + (PORT datad (400:400:400) (448:448:448)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~44) + (DELAY + (ABSOLUTE + (PORT dataa (933:933:933) (1006:1006:1006)) + (PORT datab (962:962:962) (1010:1010:1010)) + (PORT datac (1861:1861:1861) (1977:1977:1977)) + (PORT datad (1869:1869:1869) (1988:1988:1988)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~28) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (266:266:266)) + (PORT datab (393:393:393) (414:414:414)) + (PORT datad (830:830:830) (852:852:852)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~30) + (DELAY + (ABSOLUTE + (PORT dataa (889:889:889) (944:944:944)) + (PORT datab (832:832:832) (859:859:859)) + (PORT datad (860:860:860) (891:891:891)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1303:1303:1303) (1385:1385:1385)) + (PORT datab (1924:1924:1924) (2018:2018:2018)) + (PORT datac (745:745:745) (851:851:851)) + (PORT datad (823:823:823) (840:840:840)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~3) + (DELAY + (ABSOLUTE + (PORT dataa (719:719:719) (796:796:796)) + (PORT datab (1041:1041:1041) (1183:1183:1183)) + (PORT datac (1281:1281:1281) (1349:1349:1349)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~37) + (DELAY + (ABSOLUTE + (PORT dataa (1069:1069:1069) (1106:1106:1106)) + (PORT datab (982:982:982) (1037:1037:1037)) + (PORT datac (1244:1244:1244) (1292:1292:1292)) + (PORT datad (613:613:613) (631:631:631)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~38) + (DELAY + (ABSOLUTE + (PORT dataa (619:619:619) (663:663:663)) + (PORT datab (1324:1324:1324) (1447:1447:1447)) + (PORT datac (896:896:896) (928:928:928)) + (PORT datad (172:172:172) (197:197:197)) (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~39) + (DELAY + (ABSOLUTE + (PORT dataa (198:198:198) (240:240:240)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (171:171:171) (205:205:205)) + (PORT datad (172:172:172) (196:196:196)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[3\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~43) (DELAY (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (1504:1504:1504) (1545:1545:1545)) - (PORT ena (1131:1131:1131) (1098:1098:1098)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (PORT dataa (1134:1134:1134) (1214:1214:1214)) + (PORT datab (651:651:651) (689:689:689)) + (PORT datac (1164:1164:1164) (1221:1221:1221)) + (PORT datad (1212:1212:1212) (1252:1252:1252)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_68) + (INSTANCE z80_\|execute_\|ctl_alu_oe\~3) (DELAY (ABSOLUTE - (PORT datab (1121:1121:1121) (1148:1148:1148)) - (PORT datac (1398:1398:1398) (1447:1447:1447)) - (PORT datad (821:821:821) (856:856:856)) + (PORT dataa (1726:1726:1726) (1802:1802:1802)) + (PORT datab (310:310:310) (407:407:407)) + (PORT datac (1834:1834:1834) (1865:1865:1865)) + (PORT datad (583:583:583) (603:603:603)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~1) + (DELAY + (ABSOLUTE + (PORT dataa (688:688:688) (743:743:743)) + (PORT datab (1760:1760:1760) (1801:1801:1801)) + (PORT datac (675:675:675) (732:732:732)) + (PORT datad (862:862:862) (917:917:917)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~1) + (DELAY + (ABSOLUTE + (PORT datab (1184:1184:1184) (1221:1221:1221)) + (PORT datac (1397:1397:1397) (1458:1458:1458)) + (PORT datad (1210:1210:1210) (1274:1274:1274)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1521:1521:1521) (1593:1593:1593)) + (PORT datab (1032:1032:1032) (1091:1091:1091)) + (PORT datac (856:856:856) (896:896:896)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~17) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (407:407:407)) + (PORT datab (942:942:942) (977:977:977)) + (PORT datad (615:615:615) (659:659:659)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_iorw\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1562:1562:1562) (1693:1693:1693)) + (PORT datab (1495:1495:1495) (1547:1547:1547)) + (PORT datac (1378:1378:1378) (1554:1554:1554)) + (PORT datad (1508:1508:1508) (1640:1640:1640)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~47) + (DELAY + (ABSOLUTE + (PORT dataa (946:946:946) (987:987:987)) + (PORT datab (937:937:937) (964:964:964)) + (PORT datac (185:185:185) (226:226:226)) + (PORT datad (1578:1578:1578) (1559:1559:1559)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1625:1625:1625) (1763:1763:1763)) + (PORT datab (1659:1659:1659) (1746:1746:1746)) + (PORT datac (2115:2115:2115) (2208:2208:2208)) + (PORT datad (879:879:879) (933:933:933)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~13) + (DELAY + (ABSOLUTE + (PORT datab (1186:1186:1186) (1222:1222:1222)) + (PORT datac (1402:1402:1402) (1461:1461:1461)) + (PORT datad (1209:1209:1209) (1271:1271:1271)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~48) + (DELAY + (ABSOLUTE + (PORT dataa (657:657:657) (679:679:679)) + (PORT datac (1092:1092:1092) (1098:1098:1098)) + (PORT datad (563:563:563) (579:579:579)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~0) + (DELAY + (ABSOLUTE + (PORT dataa (909:909:909) (954:954:954)) + (PORT datab (1482:1482:1482) (1542:1542:1542)) + (PORT datac (823:823:823) (872:872:872)) + (PORT datad (195:195:195) (221:221:221)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla57M1T4_4) + (DELAY + (ABSOLUTE + (PORT datab (1124:1124:1124) (1227:1227:1227)) + (PORT datac (2388:2388:2388) (2467:2467:2467)) + (PORT datad (1389:1389:1389) (1445:1445:1445)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~9) + (DELAY + (ABSOLUTE + (PORT datac (841:841:841) (934:934:934)) + (PORT datad (964:964:964) (1033:1033:1033)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (2570:2570:2570) (2599:2599:2599)) + (PORT datab (1711:1711:1711) (1793:1793:1793)) + (PORT datac (2040:2040:2040) (2106:2106:2106)) + (PORT datad (926:926:926) (970:970:970)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla12M3T1_2) + (DELAY + (ABSOLUTE + (PORT datab (1585:1585:1585) (1644:1644:1644)) + (PORT datac (1798:1798:1798) (1888:1888:1888)) + (PORT datad (955:955:955) (1073:1073:1073)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1138:1138:1138) (1211:1211:1211)) + (PORT datab (2100:2100:2100) (2152:2152:2152)) + (PORT datac (1427:1427:1427) (1516:1516:1516)) + (PORT datad (873:873:873) (902:902:902)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1279:1279:1279) (1378:1378:1378)) + (PORT datab (1710:1710:1710) (1793:1793:1793)) + (PORT datac (1379:1379:1379) (1430:1430:1430)) + (PORT datad (1246:1246:1246) (1297:1297:1297)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~10) + (DELAY + (ABSOLUTE + (PORT dataa (839:839:839) (913:913:913)) + (PORT datab (821:821:821) (872:872:872)) + (PORT datac (356:356:356) (384:384:384)) + (PORT datad (619:619:619) (676:676:676)) + (IOPATH dataa combout (304:304:304) (299:299:299)) (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -16178,28 +5790,519 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~43) + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~10) (DELAY (ABSOLUTE - (PORT dataa (379:379:379) (453:453:453)) - (PORT datab (887:887:887) (923:923:923)) - (PORT datad (364:364:364) (388:388:388)) - (IOPATH dataa combout (304:304:304) (307:307:307)) + (PORT dataa (927:927:927) (998:998:998)) + (PORT datab (1062:1062:1062) (1143:1143:1143)) + (PORT datac (1799:1799:1799) (1899:1899:1899)) + (PORT datad (1114:1114:1114) (1175:1175:1175)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel_pla11M1T1_11) + (DELAY + (ABSOLUTE + (PORT datab (1233:1233:1233) (1310:1310:1310)) + (PORT datac (1159:1159:1159) (1255:1255:1255)) + (PORT datad (1515:1515:1515) (1578:1578:1578)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~11) + (DELAY + (ABSOLUTE + (PORT dataa (598:598:598) (612:612:612)) + (PORT datab (904:904:904) (941:941:941)) + (PORT datac (1425:1425:1425) (1549:1549:1549)) + (PORT datad (854:854:854) (911:911:911)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~11) + (DELAY + (ABSOLUTE + (PORT dataa (662:662:662) (716:716:716)) + (PORT datab (206:206:206) (248:248:248)) + (PORT datac (875:875:875) (908:908:908)) + (PORT datad (1885:1885:1885) (1993:1993:1993)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~1) + (DELAY + (ABSOLUTE + (PORT datac (195:195:195) (235:235:235)) + (PORT datad (209:209:209) (240:240:240)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~4) + (DELAY + (ABSOLUTE + (PORT datac (1272:1272:1272) (1358:1358:1358)) + (PORT datad (2394:2394:2394) (2515:2515:2515)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1498:1498:1498) (1593:1593:1593)) + (PORT datab (1938:1938:1938) (2058:2058:2058)) + (PORT datac (1282:1282:1282) (1342:1342:1342)) + (PORT datad (1494:1494:1494) (1555:1555:1555)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~4) + (DELAY + (ABSOLUTE + (PORT dataa (945:945:945) (1005:1005:1005)) + (PORT datab (1462:1462:1462) (1478:1478:1478)) + (PORT datac (1216:1216:1216) (1256:1256:1256)) + (PORT datad (632:632:632) (677:677:677)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1186:1186:1186) (1211:1211:1211)) + (PORT datab (1426:1426:1426) (1452:1452:1452)) + (PORT datac (1645:1645:1645) (1692:1692:1692)) + (PORT datad (906:906:906) (931:931:931)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (572:572:572) (597:597:597)) + (PORT datab (638:638:638) (678:678:678)) + (PORT datac (635:635:635) (693:693:693)) + (PORT datad (1270:1270:1270) (1340:1340:1340)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~47) + (DELAY + (ABSOLUTE + (PORT dataa (231:231:231) (277:277:277)) + (PORT datab (1228:1228:1228) (1303:1303:1303)) + (PORT datac (1537:1537:1537) (1646:1646:1646)) + (PORT datad (2345:2345:2345) (2485:2485:2485)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1650:1650:1650) (1734:1734:1734)) + (PORT datab (1126:1126:1126) (1204:1204:1204)) + (PORT datac (976:976:976) (1038:1038:1038)) + (PORT datad (180:180:180) (209:209:209)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1131:1131:1131) (1178:1178:1178)) + (PORT datab (1156:1156:1156) (1201:1201:1201)) + (PORT datac (389:389:389) (422:422:422)) + (PORT datad (947:947:947) (1020:1020:1020)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~23) + (DELAY + (ABSOLUTE + (PORT dataa (2319:2319:2319) (2382:2382:2382)) + (PORT datab (1419:1419:1419) (1524:1524:1524)) + (PORT datac (630:630:630) (677:677:677)) + (PORT datad (1440:1440:1440) (1526:1526:1526)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1842:1842:1842) (1975:1975:1975)) + (PORT datab (218:218:218) (256:256:256)) + (PORT datac (1759:1759:1759) (1877:1877:1877)) + (PORT datad (647:647:647) (706:706:706)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~13) + (DELAY + (ABSOLUTE + (PORT dataa (573:573:573) (604:604:604)) + (PORT datab (887:887:887) (918:918:918)) + (PORT datac (600:600:600) (617:617:617)) + (PORT datad (1021:1021:1021) (1018:1018:1018)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1289:1289:1289) (1346:1346:1346)) + (PORT datab (1711:1711:1711) (1793:1793:1793)) + (PORT datac (1378:1378:1378) (1430:1430:1430)) + (PORT datad (1993:1993:1993) (2056:2056:2056)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~1) + (DELAY + (ABSOLUTE + (PORT datac (523:523:523) (541:541:541)) + (PORT datad (598:598:598) (630:630:630)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~29) + (DELAY + (ABSOLUTE + (PORT dataa (1109:1109:1109) (1160:1160:1160)) + (PORT datac (1594:1594:1594) (1729:1729:1729)) + (PORT datad (1744:1744:1744) (1800:1800:1800)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~14) + (DELAY + (ABSOLUTE + (PORT dataa (576:576:576) (616:616:616)) + (PORT datab (198:198:198) (236:236:236)) + (PORT datac (194:194:194) (226:226:226)) + (PORT datad (1196:1196:1196) (1210:1210:1210)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla77M1T1_3) + (DELAY + (ABSOLUTE + (PORT dataa (927:927:927) (996:996:996)) + (PORT datab (1063:1063:1063) (1142:1142:1142)) + (PORT datac (1800:1800:1800) (1897:1897:1897)) + (PORT datad (1115:1115:1115) (1171:1171:1171)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel_pla82M1T1_16) + (DELAY + (ABSOLUTE + (PORT dataa (2188:2188:2188) (2320:2320:2320)) + (PORT datab (1249:1249:1249) (1337:1337:1337)) + (PORT datac (1169:1169:1169) (1222:1222:1222)) + (PORT datad (1585:1585:1585) (1612:1612:1612)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1710:1710:1710) (1802:1802:1802)) + (PORT datab (954:954:954) (997:997:997)) + (PORT datac (1214:1214:1214) (1292:1292:1292)) + (PORT datad (1992:1992:1992) (2067:2067:2067)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1806:1806:1806) (1900:1900:1900)) + (PORT datab (2414:2414:2414) (2552:2552:2552)) + (PORT datac (969:969:969) (1019:1019:1019)) + (PORT datad (1654:1654:1654) (1727:1727:1727)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT datab (1225:1225:1225) (1272:1272:1272)) + (PORT datac (865:865:865) (921:921:921)) + (PORT datad (179:179:179) (208:208:208)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (422:422:422) (483:483:483)) + (PORT datab (2457:2457:2457) (2574:2574:2574)) + (PORT datac (1535:1535:1535) (1632:1632:1632)) + (PORT datad (196:196:196) (222:222:222)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1958:1958:1958) (2047:2047:2047)) + (PORT datab (1490:1490:1490) (1615:1615:1615)) + (PORT datac (1941:1941:1941) (2054:2054:2054)) + (PORT datad (813:813:813) (814:814:814)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal68\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1002:1002:1002) (1101:1101:1101)) + (PORT datab (995:995:995) (1100:1100:1100)) + (PORT datac (930:930:930) (1052:1052:1052)) + (PORT datad (1208:1208:1208) (1317:1317:1317)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1164:1164:1164) (1212:1212:1212)) + (PORT datab (1589:1589:1589) (1690:1690:1690)) + (PORT datac (1934:1934:1934) (2077:2077:2077)) + (PORT datad (636:636:636) (681:681:681)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (355:355:355) (389:389:389)) + (PORT datab (337:337:337) (370:370:370)) + (PORT datac (604:604:604) (621:621:621)) + (PORT datad (586:586:586) (609:609:609)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1421:1421:1421) (1480:1480:1480)) + (PORT datab (1325:1325:1325) (1389:1389:1389)) + (PORT datac (2509:2509:2509) (2600:2600:2600)) + (PORT datad (626:626:626) (665:665:665)) + (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_76\~0) + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~8) (DELAY (ABSOLUTE - (PORT dataa (408:408:408) (464:464:464)) - (PORT datab (1404:1404:1404) (1437:1437:1437)) - (PORT datac (1139:1139:1139) (1179:1179:1179)) - (PORT datad (663:663:663) (683:683:683)) + (PORT dataa (957:957:957) (1012:1012:1012)) + (PORT datac (193:193:193) (227:227:227)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~20) + (DELAY + (ABSOLUTE + (PORT dataa (2048:2048:2048) (2151:2151:2151)) + (PORT datab (1475:1475:1475) (1514:1514:1514)) + (PORT datac (1735:1735:1735) (1813:1813:1813)) + (PORT datad (1685:1685:1685) (1760:1760:1760)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~9) + (DELAY + (ABSOLUTE + (PORT dataa (584:584:584) (611:611:611)) + (PORT datab (1341:1341:1341) (1437:1437:1437)) + (PORT datac (581:581:581) (583:583:583)) + (PORT datad (584:584:584) (598:598:598)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -16209,13 +6312,481 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_77\~0) + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~1) (DELAY (ABSOLUTE - (PORT dataa (1146:1146:1146) (1180:1180:1180)) - (PORT datab (815:815:815) (833:833:833)) - (PORT datac (1143:1143:1143) (1180:1180:1180)) - (PORT datad (671:671:671) (721:721:721)) + (PORT dataa (1788:1788:1788) (1886:1886:1886)) + (PORT datab (1610:1610:1610) (1712:1712:1712)) + (PORT datac (1206:1206:1206) (1258:1258:1258)) + (PORT datad (1676:1676:1676) (1684:1684:1684)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~1) + (DELAY + (ABSOLUTE + (PORT datab (1710:1710:1710) (1787:1787:1787)) + (PORT datac (1374:1374:1374) (1426:1426:1426)) + (PORT datad (1249:1249:1249) (1299:1299:1299)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1312:1312:1312) (1412:1412:1412)) + (PORT datab (841:841:841) (849:849:849)) + (PORT datac (1462:1462:1462) (1589:1589:1589)) + (PORT datad (1074:1074:1074) (1110:1110:1110)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~2) + (DELAY + (ABSOLUTE + (PORT datab (352:352:352) (380:380:380)) + (PORT datac (1868:1868:1868) (1874:1874:1874)) + (PORT datad (656:656:656) (671:671:671)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~17) + (DELAY + (ABSOLUTE + (PORT dataa (2131:2131:2131) (2239:2239:2239)) + (PORT datab (626:626:626) (661:661:661)) + (PORT datac (1313:1313:1313) (1389:1389:1389)) + (PORT datad (391:391:391) (440:440:440)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~18) + (DELAY + (ABSOLUTE + (PORT dataa (2118:2118:2118) (2232:2232:2232)) + (PORT datab (1816:1816:1816) (1930:1930:1930)) + (PORT datac (935:935:935) (973:973:973)) + (PORT datad (908:908:908) (959:959:959)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1429:1429:1429) (1453:1453:1453)) + (PORT datab (216:216:216) (261:261:261)) + (PORT datac (935:935:935) (967:967:967)) + (PORT datad (662:662:662) (727:727:727)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~19) + (DELAY + (ABSOLUTE + (PORT dataa (654:654:654) (677:677:677)) + (PORT datab (1803:1803:1803) (1884:1884:1884)) + (PORT datac (1284:1284:1284) (1375:1375:1375)) + (PORT datad (1323:1323:1323) (1363:1363:1363)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal1\~5) + (DELAY + (ABSOLUTE + (PORT datac (1067:1067:1067) (1146:1146:1146)) + (PORT datad (1372:1372:1372) (1427:1427:1427)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~0) + (DELAY + (ABSOLUTE + (PORT dataa (944:944:944) (1004:1004:1004)) + (PORT datab (1712:1712:1712) (1802:1802:1802)) + (PORT datac (1159:1159:1159) (1189:1189:1189)) + (PORT datad (1813:1813:1813) (1951:1951:1951)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel_pla12M1T1_12\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1787:1787:1787) (1912:1912:1912)) + (PORT datab (2129:2129:2129) (2228:2228:2228)) + (PORT datac (1194:1194:1194) (1252:1252:1252)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~1) + (DELAY + (ABSOLUTE + (PORT dataa (384:384:384) (411:411:411)) + (PORT datab (2129:2129:2129) (2226:2226:2226)) + (PORT datac (178:178:178) (213:213:213)) + (PORT datad (1802:1802:1802) (1929:1929:1929)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~7) + (DELAY + (ABSOLUTE + (PORT dataa (881:881:881) (907:907:907)) + (PORT datab (937:937:937) (1032:1032:1032)) + (PORT datac (704:704:704) (776:776:776)) + (PORT datad (1013:1013:1013) (1073:1073:1073)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1416:1416:1416) (1474:1474:1474)) + (PORT datab (1710:1710:1710) (1796:1796:1796)) + (PORT datac (1673:1673:1673) (1742:1742:1742)) + (PORT datad (1246:1246:1246) (1299:1299:1299)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1258:1258:1258) (1353:1353:1353)) + (PORT datab (1405:1405:1405) (1490:1490:1490)) + (PORT datac (1724:1724:1724) (1804:1804:1804)) + (PORT datad (595:595:595) (607:607:607)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~8) + (DELAY + (ABSOLUTE + (PORT dataa (848:848:848) (858:858:858)) + (PORT datab (801:801:801) (803:803:803)) + (PORT datac (533:533:533) (540:540:540)) + (PORT datad (588:588:588) (604:604:604)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~15) + (DELAY + (ABSOLUTE + (PORT dataa (355:355:355) (387:387:387)) + (PORT datab (355:355:355) (381:381:381)) + (PORT datac (321:321:321) (343:343:343)) + (PORT datad (332:332:332) (348:348:348)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~7) + (DELAY + (ABSOLUTE + (PORT dataa (900:900:900) (956:956:956)) + (PORT datab (390:390:390) (420:420:420)) + (PORT datac (672:672:672) (718:718:718)) + (PORT datad (374:374:374) (405:405:405)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~12) + (DELAY + (ABSOLUTE + (PORT dataa (406:406:406) (451:451:451)) + (PORT datab (221:221:221) (260:260:260)) + (PORT datac (1536:1536:1536) (1624:1624:1624)) + (PORT datad (1236:1236:1236) (1338:1338:1338)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1611:1611:1611) (1705:1705:1705)) + (PORT datab (2059:2059:2059) (2157:2157:2157)) + (PORT datac (2103:2103:2103) (2208:2208:2208)) + (PORT datad (1923:1923:1923) (2008:2008:2008)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~10) + (DELAY + (ABSOLUTE + (PORT dataa (198:198:198) (240:240:240)) + (PORT datab (1408:1408:1408) (1465:1465:1465)) + (PORT datac (1122:1122:1122) (1126:1126:1126)) + (PORT datad (201:201:201) (230:230:230)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~8) + (DELAY + (ABSOLUTE + (PORT dataa (916:916:916) (954:954:954)) + (PORT datab (1496:1496:1496) (1586:1586:1586)) + (PORT datac (891:891:891) (908:908:908)) + (PORT datad (1270:1270:1270) (1340:1340:1340)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal64\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1002:1002:1002) (1138:1138:1138)) + (PORT datab (654:654:654) (715:715:715)) + (PORT datac (322:322:322) (348:348:348)) + (PORT datad (188:188:188) (219:219:219)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (632:632:632) (656:656:656)) + (PORT datab (2132:2132:2132) (2229:2229:2229)) + (PORT datac (1759:1759:1759) (1877:1877:1877)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal62\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1002:1002:1002) (1134:1134:1134)) + (PORT datab (651:651:651) (712:712:712)) + (PORT datac (325:325:325) (349:349:349)) + (PORT datad (187:187:187) (217:217:217)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1524:1524:1524) (1624:1624:1624)) + (PORT datab (1149:1149:1149) (1229:1229:1229)) + (PORT datac (216:216:216) (256:256:256)) + (PORT datad (1269:1269:1269) (1336:1336:1336)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~46) + (DELAY + (ABSOLUTE + (PORT dataa (1675:1675:1675) (1783:1783:1783)) + (PORT datab (1430:1430:1430) (1468:1468:1468)) + (PORT datac (645:645:645) (660:660:660)) + (PORT datad (2755:2755:2755) (2813:2813:2813)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1185:1185:1185) (1222:1222:1222)) + (PORT datab (2780:2780:2780) (2854:2854:2854)) + (PORT datac (1643:1643:1643) (1747:1747:1747)) + (PORT datad (1901:1901:1901) (2004:2004:2004)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~7) + (DELAY + (ABSOLUTE + (PORT dataa (659:659:659) (717:717:717)) + (PORT datab (658:658:658) (685:685:685)) + (PORT datac (1140:1140:1140) (1183:1183:1183)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~11) + (DELAY + (ABSOLUTE + (PORT dataa (680:680:680) (735:735:735)) + (PORT datab (355:355:355) (385:385:385)) + (PORT datac (923:923:923) (989:989:989)) + (PORT datad (187:187:187) (217:217:217)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal62\~3) + (DELAY + (ABSOLUTE + (PORT dataa (2003:2003:2003) (2196:2196:2196)) + (PORT datab (1221:1221:1221) (1319:1319:1319)) + (PORT datac (963:963:963) (986:986:986)) + (PORT datad (1268:1268:1268) (1352:1352:1352)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -16223,14 +6794,1526 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1229:1229:1229) (1254:1254:1254)) + (PORT datab (656:656:656) (680:680:680)) + (PORT datac (2218:2218:2218) (2248:2248:2248)) + (PORT datad (1113:1113:1113) (1134:1134:1134)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (263:263:263)) + (PORT datab (912:912:912) (948:948:948)) + (PORT datac (801:801:801) (807:807:807)) + (PORT datad (1160:1160:1160) (1209:1209:1209)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (255:255:255)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (194:194:194) (220:220:220)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~9) + (DELAY + (ABSOLUTE + (PORT dataa (579:579:579) (616:616:616)) + (PORT datab (219:219:219) (257:257:257)) + (PORT datac (827:827:827) (828:828:828)) + (PORT datad (635:635:635) (645:645:645)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~6) + (DELAY + (ABSOLUTE + (PORT dataa (978:978:978) (1045:1045:1045)) + (PORT datab (1725:1725:1725) (1763:1763:1763)) + (PORT datac (961:961:961) (991:991:991)) + (PORT datad (658:658:658) (694:694:694)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~7) + (DELAY + (ABSOLUTE + (PORT dataa (981:981:981) (1052:1052:1052)) + (PORT datab (926:926:926) (972:972:972)) + (PORT datac (959:959:959) (990:990:990)) + (PORT datad (194:194:194) (220:220:220)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~1) + (DELAY + (ABSOLUTE + (PORT dataa (609:609:609) (642:642:642)) + (PORT datab (1259:1259:1259) (1318:1318:1318)) + (PORT datac (1105:1105:1105) (1155:1155:1155)) + (PORT datad (542:542:542) (549:549:549)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (958:958:958) (992:992:992)) + (PORT datab (1245:1245:1245) (1321:1321:1321)) + (PORT datac (1223:1223:1223) (1310:1310:1310)) + (PORT datad (915:915:915) (952:952:952)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~4) + (DELAY + (ABSOLUTE + (PORT dataa (935:935:935) (980:980:980)) + (PORT datab (692:692:692) (730:730:730)) + (PORT datac (1698:1698:1698) (1738:1738:1738)) + (PORT datad (1113:1113:1113) (1131:1131:1131)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~5) + (DELAY + (ABSOLUTE + (PORT dataa (936:936:936) (984:984:984)) + (PORT datab (1137:1137:1137) (1172:1172:1172)) + (PORT datac (895:895:895) (939:939:939)) + (PORT datad (195:195:195) (220:220:220)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~2) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (877:877:877) (911:911:911)) + (PORT datac (1173:1173:1173) (1210:1210:1210)) + (PORT datad (568:568:568) (585:585:585)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla91pla21M2T3_4) + (DELAY + (ABSOLUTE + (PORT dataa (971:971:971) (1039:1039:1039)) + (PORT datab (1668:1668:1668) (1733:1733:1733)) + (PORT datac (940:940:940) (1053:1053:1053)) + (PORT datad (651:651:651) (709:709:709)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~6) + (DELAY + (ABSOLUTE + (PORT dataa (635:635:635) (652:652:652)) + (PORT datab (1696:1696:1696) (1875:1875:1875)) + (PORT datac (1371:1371:1371) (1456:1456:1456)) + (PORT datad (316:316:316) (337:337:337)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~12) + (DELAY + (ABSOLUTE + (PORT dataa (997:997:997) (1039:1039:1039)) + (PORT datab (681:681:681) (743:743:743)) + (PORT datac (1370:1370:1370) (1453:1453:1453)) + (PORT datad (688:688:688) (735:735:735)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1081:1081:1081) (1099:1099:1099)) + (PORT datab (1323:1323:1323) (1327:1327:1327)) + (PORT datac (1868:1868:1868) (1871:1871:1871)) + (PORT datad (640:640:640) (651:651:651)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_res_oe\~3) + (DELAY + (ABSOLUTE + (PORT dataa (354:354:354) (390:390:390)) + (PORT datab (825:825:825) (851:851:851)) + (PORT datac (178:178:178) (217:217:217)) + (PORT datad (600:600:600) (623:623:623)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_high) + (DELAY + (ABSOLUTE + (PORT dataa (2212:2212:2212) (2301:2301:2301)) + (PORT datab (1863:1863:1863) (1975:1975:1975)) + (PORT datac (536:536:536) (552:552:552)) + (PORT datad (1238:1238:1238) (1329:1329:1329)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1281:1281:1281) (1347:1347:1347)) + (PORT datab (1610:1610:1610) (1648:1648:1648)) + (PORT datac (1169:1169:1169) (1222:1222:1222)) + (PORT datad (1696:1696:1696) (1799:1799:1799)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1632:1632:1632) (1662:1662:1662)) + (PORT datab (1265:1265:1265) (1333:1333:1333)) + (PORT datac (2462:2462:2462) (2596:2596:2596)) + (PORT datad (911:911:911) (938:938:938)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal61\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1561:1561:1561) (1694:1694:1694)) + (PORT datab (1558:1558:1558) (1623:1623:1623)) + (PORT datac (1379:1379:1379) (1557:1557:1557)) + (PORT datad (1509:1509:1509) (1636:1636:1636)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1285:1285:1285) (1353:1353:1353)) + (PORT datab (1252:1252:1252) (1341:1341:1341)) + (PORT datac (1128:1128:1128) (1177:1177:1177)) + (PORT datad (615:615:615) (659:659:659)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1494:1494:1494) (1588:1588:1588)) + (PORT datab (1151:1151:1151) (1164:1164:1164)) + (PORT datac (1070:1070:1070) (1069:1069:1069)) + (PORT datad (716:716:716) (790:790:790)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1149:1149:1149) (1182:1182:1182)) + (PORT datab (860:860:860) (889:889:889)) + (PORT datac (845:845:845) (891:891:891)) + (PORT datad (1613:1613:1613) (1637:1637:1637)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~18) + (DELAY + (ABSOLUTE + (PORT dataa (649:649:649) (671:671:671)) + (PORT datab (1804:1804:1804) (1888:1888:1888)) + (PORT datac (1288:1288:1288) (1380:1380:1380)) + (PORT datad (1322:1322:1322) (1363:1363:1363)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~10) + (DELAY + (ABSOLUTE + (PORT dataa (613:613:613) (649:649:649)) + (PORT datab (1251:1251:1251) (1289:1289:1289)) + (PORT datac (752:752:752) (764:764:764)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~2) + (DELAY + (ABSOLUTE + (PORT datab (610:610:610) (615:615:615)) + (PORT datac (633:633:633) (653:653:653)) + (PORT datad (1864:1864:1864) (1909:1909:1909)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1996:1996:1996) (2194:2194:2194)) + (PORT datab (1221:1221:1221) (1306:1306:1306)) + (PORT datad (1183:1183:1183) (1203:1203:1203)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus\~3) + (DELAY + (ABSOLUTE + (PORT dataa (944:944:944) (995:995:995)) + (PORT datab (1244:1244:1244) (1296:1296:1296)) + (PORT datac (2743:2743:2743) (2858:2858:2858)) + (PORT datad (1374:1374:1374) (1415:1415:1415)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~26) + (DELAY + (ABSOLUTE + (PORT dataa (1074:1074:1074) (1116:1116:1116)) + (PORT datab (1273:1273:1273) (1302:1302:1302)) + (PORT datac (1138:1138:1138) (1158:1158:1158)) + (PORT datad (1560:1560:1560) (1679:1679:1679)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_bus) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (244:244:244)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (202:202:202) (239:239:239)) + (PORT datad (195:195:195) (220:220:220)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_lo\~9) + (DELAY + (ABSOLUTE + (PORT dataa (2193:2193:2193) (2363:2363:2363)) + (PORT datab (745:745:745) (820:820:820)) + (PORT datac (1804:1804:1804) (1892:1892:1892)) + (PORT datad (932:932:932) (1032:1032:1032)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (949:949:949) (978:978:978)) + (PORT datab (850:850:850) (909:909:909)) + (PORT datac (2180:2180:2180) (2265:2265:2265)) + (PORT datad (1711:1711:1711) (1846:1846:1846)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_oe\~1) + (DELAY + (ABSOLUTE + (PORT dataa (983:983:983) (1040:1040:1040)) + (PORT datab (873:873:873) (899:899:899)) + (PORT datac (918:918:918) (968:968:968)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~6) + (DELAY + (ABSOLUTE + (PORT dataa (892:892:892) (913:913:913)) + (PORT datab (1670:1670:1670) (1749:1749:1749)) + (PORT datac (934:934:934) (965:965:965)) + (PORT datad (1389:1389:1389) (1404:1404:1404)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1499:1499:1499) (1628:1628:1628)) + (PORT datab (937:937:937) (996:996:996)) + (PORT datac (1435:1435:1435) (1520:1520:1520)) + (PORT datad (1888:1888:1888) (1916:1916:1916)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~8) + (DELAY + (ABSOLUTE + (PORT dataa (218:218:218) (269:269:269)) + (PORT datac (1056:1056:1056) (1073:1073:1073)) + (PORT datad (653:653:653) (670:670:670)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~9) + (DELAY + (ABSOLUTE + (PORT dataa (937:937:937) (1004:1004:1004)) + (PORT datab (1474:1474:1474) (1513:1513:1513)) + (PORT datac (936:936:936) (975:975:975)) + (PORT datad (1646:1646:1646) (1715:1715:1715)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (257:257:257)) + (PORT datab (1671:1671:1671) (1753:1753:1753)) + (PORT datac (1246:1246:1246) (1319:1319:1319)) + (PORT datad (182:182:182) (212:212:212)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (635:635:635) (710:710:710)) + (PORT datab (1462:1462:1462) (1554:1554:1554)) + (PORT datac (2183:2183:2183) (2263:2263:2263)) + (PORT datad (1316:1316:1316) (1373:1373:1373)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (249:249:249) (295:295:295)) + (PORT datab (1590:1590:1590) (1583:1583:1583)) + (PORT datac (539:539:539) (554:554:554)) + (PORT datad (218:218:218) (258:258:258)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla83M1T3_2) + (DELAY + (ABSOLUTE + (PORT dataa (945:945:945) (1002:1002:1002)) + (PORT datab (1919:1919:1919) (1951:1951:1951)) + (PORT datac (1162:1162:1162) (1193:1193:1193)) + (PORT datad (1687:1687:1687) (1760:1760:1760)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1657:1657:1657) (1684:1684:1684)) + (PORT datab (1509:1509:1509) (1566:1566:1566)) + (PORT datac (626:626:626) (656:656:656)) + (PORT datad (948:948:948) (1027:1027:1027)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~38) + (DELAY + (ABSOLUTE + (PORT dataa (988:988:988) (1050:1050:1050)) + (PORT datab (1482:1482:1482) (1510:1510:1510)) + (PORT datac (1379:1379:1379) (1463:1463:1463)) + (PORT datad (907:907:907) (951:951:951)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~28) + (DELAY + (ABSOLUTE + (PORT dataa (945:945:945) (1002:1002:1002)) + (PORT datab (1713:1713:1713) (1799:1799:1799)) + (PORT datac (1162:1162:1162) (1193:1193:1193)) + (PORT datad (2291:2291:2291) (2362:2362:2362)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~6) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (700:700:700) (742:742:742)) + (PORT datac (821:821:821) (867:867:867)) + (PORT datad (211:211:211) (243:243:243)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~37) + (DELAY + (ABSOLUTE + (PORT dataa (2304:2304:2304) (2381:2381:2381)) + (PORT datab (1670:1670:1670) (1716:1716:1716)) + (PORT datac (604:604:604) (650:650:650)) + (PORT datad (898:898:898) (960:960:960)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~39) + (DELAY + (ABSOLUTE + (PORT dataa (1177:1177:1177) (1195:1195:1195)) + (PORT datab (531:531:531) (554:554:554)) + (PORT datac (570:570:570) (577:577:577)) + (PORT datad (1560:1560:1560) (1675:1675:1675)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_daa) + (DELAY + (ABSOLUTE + (PORT dataa (2150:2150:2150) (2247:2247:2247)) + (PORT datab (882:882:882) (944:944:944)) + (PORT datac (1798:1798:1798) (1902:1902:1902)) + (PORT datad (1114:1114:1114) (1173:1173:1173)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~7) + (DELAY + (ABSOLUTE + (PORT dataa (424:424:424) (486:486:486)) + (PORT datab (627:627:627) (663:663:663)) + (PORT datac (1709:1709:1709) (1751:1751:1751)) + (PORT datad (2329:2329:2329) (2397:2397:2397)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~8) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (2354:2354:2354) (2430:2430:2430)) + (PORT datac (882:882:882) (943:943:943)) + (PORT datad (196:196:196) (222:222:222)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~30) + (DELAY + (ABSOLUTE + (PORT dataa (1727:1727:1727) (1814:1814:1814)) + (PORT datab (952:952:952) (1007:1007:1007)) + (PORT datac (1672:1672:1672) (1742:1742:1742)) + (PORT datad (1045:1045:1045) (1128:1128:1128)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~31) + (DELAY + (ABSOLUTE + (PORT datab (629:629:629) (646:646:646)) + (PORT datac (852:852:852) (860:860:860)) + (PORT datad (549:549:549) (555:555:555)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~25) + (DELAY + (ABSOLUTE + (PORT datac (1712:1712:1712) (1753:1753:1753)) + (PORT datad (632:632:632) (691:691:691)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~40) + (DELAY + (ABSOLUTE + (PORT dataa (667:667:667) (712:712:712)) + (PORT datab (1437:1437:1437) (1441:1441:1441)) + (PORT datac (1443:1443:1443) (1489:1489:1489)) + (PORT datad (838:838:838) (875:875:875)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~42) + (DELAY + (ABSOLUTE + (PORT dataa (209:209:209) (257:257:257)) + (PORT datab (633:633:633) (653:653:653)) + (PORT datac (801:801:801) (833:833:833)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla65npla52M1T4_4) + (DELAY + (ABSOLUTE + (PORT dataa (1441:1441:1441) (1487:1487:1487)) + (PORT datab (1568:1568:1568) (1657:1657:1657)) + (PORT datac (813:813:813) (833:833:833)) + (PORT datad (1236:1236:1236) (1341:1341:1341)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~4) + (DELAY + (ABSOLUTE + (PORT dataa (660:660:660) (720:720:720)) + (PORT datab (709:709:709) (763:763:763)) + (PORT datac (918:918:918) (970:970:970)) + (PORT datad (615:615:615) (633:633:633)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~47) + (DELAY + (ABSOLUTE + (PORT dataa (2318:2318:2318) (2418:2418:2418)) + (PORT datab (927:927:927) (955:955:955)) + (PORT datac (1554:1554:1554) (1653:1653:1653)) + (PORT datad (1922:1922:1922) (2011:2011:2011)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~34) + (DELAY + (ABSOLUTE + (PORT dataa (935:935:935) (1007:1007:1007)) + (PORT datab (687:687:687) (763:763:763)) + (PORT datac (559:559:559) (571:571:571)) + (PORT datad (1644:1644:1644) (1710:1710:1710)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~35) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (257:257:257)) + (PORT datab (336:336:336) (369:369:369)) + (PORT datac (1234:1234:1234) (1291:1291:1291)) + (PORT datad (907:907:907) (963:963:963)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~36) + (DELAY + (ABSOLUTE + (PORT dataa (1090:1090:1090) (1119:1119:1119)) + (PORT datab (856:856:856) (861:861:861)) + (PORT datac (579:579:579) (597:597:597)) + (PORT datad (545:545:545) (551:551:551)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~28) + (DELAY + (ABSOLUTE + (PORT dataa (707:707:707) (756:756:756)) + (PORT datab (958:958:958) (1003:1003:1003)) + (PORT datac (1167:1167:1167) (1223:1223:1223)) + (PORT datad (1125:1125:1125) (1182:1182:1182)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~44) + (DELAY + (ABSOLUTE + (PORT dataa (667:667:667) (723:723:723)) + (PORT datab (1687:1687:1687) (1768:1768:1768)) + (PORT datac (1403:1403:1403) (1556:1556:1556)) + (PORT datad (615:615:615) (639:639:639)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~29) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datac (858:858:858) (882:882:882)) + (PORT datad (180:180:180) (209:209:209)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~16) + (DELAY + (ABSOLUTE + (PORT datac (1464:1464:1464) (1592:1592:1592)) + (PORT datad (1080:1080:1080) (1115:1115:1115)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~27) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (265:265:265)) + (PORT datab (1591:1591:1591) (1599:1599:1599)) + (PORT datac (193:193:193) (226:226:226)) + (PORT datad (332:332:332) (350:350:350)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_bs_oe\~10) + (DELAY + (ABSOLUTE + (PORT dataa (216:216:216) (267:267:267)) + (PORT datab (207:207:207) (249:249:249)) + (PORT datac (1058:1058:1058) (1075:1075:1075)) + (PORT datad (654:654:654) (671:671:671)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~31) + (DELAY + (ABSOLUTE + (PORT dataa (1966:1966:1966) (2113:2113:2113)) + (PORT datab (2242:2242:2242) (2358:2358:2358)) + (PORT datac (389:389:389) (423:423:423)) + (PORT datad (647:647:647) (684:684:684)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~30) + (DELAY + (ABSOLUTE + (PORT dataa (1262:1262:1262) (1336:1336:1336)) + (PORT datab (1328:1328:1328) (1392:1392:1392)) + (PORT datac (871:871:871) (913:913:913)) + (PORT datad (625:625:625) (662:662:662)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~32) + (DELAY + (ABSOLUTE + (PORT dataa (2546:2546:2546) (2637:2637:2637)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (2208:2208:2208) (2324:2324:2324)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~33) + (DELAY + (ABSOLUTE + (PORT dataa (1028:1028:1028) (1062:1062:1062)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (761:761:761) (761:761:761)) + (PORT datad (798:798:798) (800:800:800)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~21) + (DELAY + (ABSOLUTE + (PORT dataa (984:984:984) (1054:1054:1054)) + (PORT datab (1816:1816:1816) (1894:1894:1894)) + (PORT datac (945:945:945) (997:997:997)) + (PORT datad (1463:1463:1463) (1516:1516:1516)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~45) + (DELAY + (ABSOLUTE + (PORT dataa (2585:2585:2585) (2658:2658:2658)) + (PORT datab (1534:1534:1534) (1667:1667:1667)) + (PORT datac (171:171:171) (205:205:205)) + (PORT datad (937:937:937) (1001:1001:1001)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~22) + (DELAY + (ABSOLUTE + (PORT dataa (341:341:341) (379:379:379)) + (PORT datab (1818:1818:1818) (1898:1898:1898)) + (PORT datac (957:957:957) (990:990:990)) + (PORT datad (951:951:951) (1002:1002:1002)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~23) + (DELAY + (ABSOLUTE + (PORT dataa (993:993:993) (1031:1031:1031)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (1779:1779:1779) (1862:1862:1862)) + (PORT datad (1426:1426:1426) (1463:1463:1463)) + (IOPATH dataa combout (341:341:341) (328:328:328)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~24) + (DELAY + (ABSOLUTE + (PORT dataa (1125:1125:1125) (1172:1172:1172)) + (PORT datab (1820:1820:1820) (1897:1897:1897)) + (PORT datac (1404:1404:1404) (1423:1423:1423)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (341:341:341) (328:328:328)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~25) + (DELAY + (ABSOLUTE + (PORT dataa (1454:1454:1454) (1506:1506:1506)) + (PORT datab (1731:1731:1731) (1771:1771:1771)) + (PORT datac (1092:1092:1092) (1132:1132:1132)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~26) + (DELAY + (ABSOLUTE + (PORT dataa (220:220:220) (262:262:262)) + (PORT datab (939:939:939) (993:993:993)) + (PORT datac (810:810:810) (823:823:823)) + (PORT datad (194:194:194) (218:218:218)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_shift_oe\~43) + (DELAY + (ABSOLUTE + (PORT dataa (567:567:567) (584:584:584)) + (PORT datab (586:586:586) (594:594:594)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_low) + (DELAY + (ABSOLUTE + (PORT dataa (997:997:997) (1038:1038:1038)) + (PORT datab (1942:1942:1942) (1998:1998:1998)) + (PORT datac (2183:2183:2183) (2258:2258:2258)) + (PORT datad (1441:1441:1441) (1528:1528:1528)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1288:1288:1288) (1355:1355:1355)) + (PORT datab (923:923:923) (1007:1007:1007)) + (PORT datac (1130:1130:1130) (1176:1176:1176)) + (PORT datad (829:829:829) (892:892:892)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_zero) + (DELAY + (ABSOLUTE + (PORT dataa (610:610:610) (630:630:630)) + (PORT datab (1839:1839:1839) (1888:1888:1888)) + (PORT datac (1621:1621:1621) (1720:1720:1720)) + (PORT datad (523:523:523) (534:534:534)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~13) + (DELAY + (ABSOLUTE + (PORT dataa (660:660:660) (716:716:716)) + (PORT datab (610:610:610) (628:628:628)) + (PORT datac (1954:1954:1954) (2059:2059:2059)) + (PORT datad (602:602:602) (628:628:628)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1609:1609:1609) (1660:1660:1660)) + (PORT datab (568:568:568) (602:602:602)) + (PORT datac (1888:1888:1888) (1990:1990:1990)) + (PORT datad (1814:1814:1814) (1949:1949:1949)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1335:1335:1335) (1393:1393:1393)) + (PORT datab (198:198:198) (236:236:236)) + (PORT datac (2026:2026:2026) (2181:2181:2181)) + (PORT datad (1017:1017:1017) (1044:1044:1044)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~3) + (DELAY + (ABSOLUTE + (PORT dataa (991:991:991) (1029:1029:1029)) + (PORT datab (1738:1738:1738) (1788:1788:1788)) + (PORT datac (1776:1776:1776) (1858:1858:1858)) + (PORT datad (938:938:938) (1001:1001:1001)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~4) + (DELAY + (ABSOLUTE + (PORT dataa (980:980:980) (1048:1048:1048)) + (PORT datab (990:990:990) (1042:1042:1042)) + (PORT datac (959:959:959) (988:988:988)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4) + (DELAY + (ABSOLUTE + (PORT dataa (1964:1964:1964) (2059:2059:2059)) + (PORT datab (1220:1220:1220) (1270:1270:1270)) + (PORT datad (1572:1572:1572) (1663:1663:1663)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1808:1808:1808) (1896:1896:1896)) + (PORT datab (1137:1137:1137) (1167:1167:1167)) + (PORT datac (906:906:906) (944:944:944)) + (PORT datad (1460:1460:1460) (1513:1513:1513)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~10) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (380:380:380)) + (PORT datab (221:221:221) (260:260:260)) + (PORT datac (186:186:186) (224:224:224)) + (PORT datad (644:644:644) (661:661:661)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~11) + (DELAY + (ABSOLUTE + (PORT dataa (689:689:689) (756:756:756)) + (PORT datab (1818:1818:1818) (1889:1889:1889)) + (PORT datac (623:623:623) (637:637:637)) + (PORT datad (816:816:816) (822:822:822)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1106:1106:1106) (1160:1160:1160)) + (PORT datab (1783:1783:1783) (1844:1844:1844)) + (PORT datac (1595:1595:1595) (1729:1729:1729)) + (PORT datad (579:579:579) (594:594:594)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_bus\~15) + (DELAY + (ABSOLUTE + (PORT dataa (561:561:561) (583:583:583)) + (PORT datab (199:199:199) (239:239:239)) + (PORT datac (511:511:511) (521:521:521)) + (PORT datad (798:798:798) (800:800:800)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[3\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (950:950:950) (979:979:979)) + (PORT datab (854:854:854) (879:879:879)) + (PORT datac (876:876:876) (880:880:880)) + (PORT datad (624:624:624) (643:643:643)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[3\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (713:713:713) (757:757:757)) + (PORT datab (888:888:888) (902:902:902)) + (PORT datac (887:887:887) (909:909:909)) + (PORT datad (172:172:172) (196:196:196)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|ena) + (DELAY + (ABSOLUTE + (PORT dataa (948:948:948) (978:978:978)) + (PORT datac (897:897:897) (919:919:919)) + (PORT datad (848:848:848) (860:860:860)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[3\]) + (INSTANCE z80_\|alu_\|op1_low\[3\]) (DELAY (ABSOLUTE - (PORT clk (1535:1535:1535) (1554:1554:1554)) + (PORT clk (1547:1547:1547) (1549:1549:1549)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1461:1461:1461) (1468:1468:1468)) + (PORT ena (794:794:794) (792:792:792)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -16241,32 +8324,2585 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~31) + (INSTANCE z80_\|alu_\|db_low\[3\]\~15) (DELAY (ABSOLUTE - (PORT dataa (1782:1782:1782) (1906:1906:1906)) - (PORT datab (973:973:973) (1022:1022:1022)) - (PORT datac (1471:1471:1471) (1489:1489:1489)) - (PORT datad (1978:1978:1978) (2013:2013:2013)) + (PORT dataa (654:654:654) (683:683:683)) + (PORT datab (706:706:706) (724:724:724)) + (PORT datac (670:670:670) (744:744:744)) + (PORT datad (429:429:429) (500:500:500)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[3\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (275:275:275) (330:330:330)) + (PORT datac (1117:1117:1117) (1123:1123:1123)) + (PORT datad (344:344:344) (366:366:366)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~33) + (DELAY + (ABSOLUTE + (PORT dataa (903:903:903) (937:937:937)) + (PORT datab (1708:1708:1708) (1760:1760:1760)) + (PORT datac (862:862:862) (894:894:894)) + (PORT datad (899:899:899) (996:996:996)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~34) + (DELAY + (ABSOLUTE + (PORT dataa (607:607:607) (641:641:641)) + (PORT datab (1113:1113:1113) (1182:1182:1182)) + (PORT datac (609:609:609) (635:635:635)) + (PORT datad (900:900:900) (929:929:929)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~48) + (DELAY + (ABSOLUTE + (PORT dataa (1612:1612:1612) (1708:1708:1708)) + (PORT datab (1588:1588:1588) (1686:1686:1686)) + (PORT datac (2100:2100:2100) (2212:2212:2212)) + (PORT datad (1125:1125:1125) (1128:1128:1128)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~35) + (DELAY + (ABSOLUTE + (PORT dataa (866:866:866) (923:923:923)) + (PORT datab (1589:1589:1589) (1736:1736:1736)) + (PORT datac (826:826:826) (871:871:871)) + (PORT datad (1185:1185:1185) (1202:1202:1202)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~36) + (DELAY + (ABSOLUTE + (PORT dataa (624:624:624) (656:656:656)) + (PORT datab (841:841:841) (859:859:859)) + (PORT datac (622:622:622) (633:633:633)) + (PORT datad (173:173:173) (197:197:197)) (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~37) + (DELAY + (ABSOLUTE + (PORT dataa (223:223:223) (278:278:278)) + (PORT datab (646:646:646) (670:670:670)) + (PORT datac (586:586:586) (604:604:604)) + (PORT datad (590:590:590) (608:608:608)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla26M1T4_3) + (DELAY + (ABSOLUTE + (PORT dataa (1614:1614:1614) (1710:1710:1710)) + (PORT datab (1669:1669:1669) (1707:1707:1707)) + (PORT datad (1923:1923:1923) (2012:2012:2012)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~38) + (DELAY + (ABSOLUTE + (PORT dataa (1018:1018:1018) (1094:1094:1094)) + (PORT datab (2048:2048:2048) (2131:2131:2131)) + (PORT datac (1072:1072:1072) (1128:1128:1128)) + (PORT datad (1108:1108:1108) (1172:1172:1172)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~39) + (DELAY + (ABSOLUTE + (PORT dataa (1409:1409:1409) (1467:1467:1467)) + (PORT datab (2028:2028:2028) (2091:2091:2091)) + (PORT datac (1605:1605:1605) (1677:1677:1677)) + (PORT datad (1248:1248:1248) (1299:1299:1299)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~40) + (DELAY + (ABSOLUTE + (PORT dataa (417:417:417) (442:442:442)) + (PORT datab (813:813:813) (847:847:847)) + (PORT datac (201:201:201) (237:237:237)) + (PORT datad (839:839:839) (889:889:889)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~41) + (DELAY + (ABSOLUTE + (PORT dataa (1902:1902:1902) (1975:1975:1975)) + (PORT datab (854:854:854) (902:902:902)) + (PORT datac (2419:2419:2419) (2508:2508:2508)) + (PORT datad (891:891:891) (939:939:939)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low) + (DELAY + (ABSOLUTE + (PORT dataa (987:987:987) (1065:1065:1065)) + (PORT datab (236:236:236) (281:281:281)) + (PORT datac (1684:1684:1684) (1767:1767:1767)) + (PORT datad (826:826:826) (855:855:855)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|result_lo\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT asdata (946:946:946) (976:976:976)) + (PORT ena (1975:1975:1975) (1964:1964:1964)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~5) + (DELAY + (ABSOLUTE + (PORT dataa (876:876:876) (951:951:951)) + (PORT datab (244:244:244) (288:288:288)) + (PORT datac (1192:1192:1192) (1241:1241:1241)) + (PORT datad (1027:1027:1027) (1107:1107:1107)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~6) + (DELAY + (ABSOLUTE + (PORT dataa (862:862:862) (914:914:914)) + (PORT datab (654:654:654) (683:683:683)) + (PORT datac (808:808:808) (801:801:801)) + (PORT datad (623:623:623) (663:663:663)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1228:1228:1228) (1256:1256:1256)) + (PORT datab (642:642:642) (714:714:714)) + (PORT datac (1093:1093:1093) (1122:1122:1122)) + (PORT datad (629:629:629) (643:643:643)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1340:1340:1340) (1376:1376:1376)) + (PORT datab (1193:1193:1193) (1245:1245:1245)) + (PORT datac (1641:1641:1641) (1744:1744:1744)) + (PORT datad (1899:1899:1899) (2002:2002:2002)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~10) + (DELAY + (ABSOLUTE + (PORT dataa (205:205:205) (251:251:251)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (1045:1045:1045) (1117:1117:1117)) + (PORT datad (194:194:194) (220:220:220)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~2) + (DELAY + (ABSOLUTE + (PORT dataa (847:847:847) (874:874:874)) + (PORT datab (892:892:892) (926:926:926)) + (PORT datac (707:707:707) (777:777:777)) + (PORT datad (901:901:901) (992:992:992)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel_pla66npla53M1T1_15) + (DELAY + (ABSOLUTE + (PORT dataa (1898:1898:1898) (1930:1930:1930)) + (PORT datab (1085:1085:1085) (1159:1159:1159)) + (PORT datac (1435:1435:1435) (1548:1548:1548)) + (PORT datad (1477:1477:1477) (1541:1541:1541)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (693:693:693) (754:754:754)) + (PORT datab (893:893:893) (934:934:934)) + (PORT datac (1262:1262:1262) (1296:1296:1296)) + (PORT datad (1388:1388:1388) (1477:1477:1477)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~8) + (DELAY + (ABSOLUTE + (PORT dataa (984:984:984) (1012:1012:1012)) + (PORT datab (923:923:923) (944:944:944)) + (PORT datac (888:888:888) (916:916:916)) + (PORT datad (1082:1082:1082) (1090:1090:1090)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1924:1924:1924) (2037:2037:2037)) + (PORT datab (1344:1344:1344) (1350:1350:1350)) + (PORT datac (875:875:875) (906:906:906)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~7) + (DELAY + (ABSOLUTE + (PORT dataa (816:816:816) (850:850:850)) + (PORT datab (590:590:590) (599:599:599)) + (PORT datac (1182:1182:1182) (1215:1215:1215)) + (PORT datad (594:594:594) (645:645:645)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1740:1740:1740) (1786:1786:1786)) + (PORT datab (413:413:413) (437:437:437)) + (PORT datac (591:591:591) (622:622:622)) + (PORT datad (1148:1148:1148) (1183:1183:1183)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (566:566:566) (604:604:604)) + (PORT datab (1165:1165:1165) (1178:1178:1178)) + (PORT datac (1574:1574:1574) (1621:1621:1621)) + (PORT datad (582:582:582) (583:583:583)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~8) + (DELAY + (ABSOLUTE + (PORT dataa (941:941:941) (972:972:972)) + (PORT datab (1052:1052:1052) (1122:1122:1122)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (824:824:824) (862:862:862)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_alu\~16) + (DELAY + (ABSOLUTE + (PORT dataa (661:661:661) (718:718:718)) + (PORT datab (219:219:219) (258:258:258)) + (PORT datac (568:568:568) (582:582:582)) + (PORT datad (853:853:853) (910:910:910)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_oe\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1101:1101:1101) (1146:1146:1146)) + (PORT datab (572:572:572) (587:587:587)) + (PORT datac (1520:1520:1520) (1523:1523:1523)) + (PORT datad (836:836:836) (851:851:851)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~48) + (DELAY + (ABSOLUTE + (PORT dataa (1193:1193:1193) (1258:1258:1258)) + (PORT datab (1853:1853:1853) (1991:1991:1991)) + (PORT datac (565:565:565) (572:572:572)) + (PORT datad (1722:1722:1722) (1801:1801:1801)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1424:1424:1424) (1504:1504:1504)) + (PORT datab (976:976:976) (1040:1040:1040)) + (PORT datac (1110:1110:1110) (1148:1148:1148)) + (PORT datad (954:954:954) (1028:1028:1028)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~5) + (DELAY + (ABSOLUTE + (PORT dataa (630:630:630) (676:676:676)) + (PORT datab (692:692:692) (757:757:757)) + (PORT datac (638:638:638) (671:671:671)) + (PORT datad (649:649:649) (681:681:681)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~2) + (DELAY + (ABSOLUTE + (PORT dataa (2623:2623:2623) (2703:2703:2703)) + (PORT datab (912:912:912) (940:940:940)) + (PORT datac (1619:1619:1619) (1751:1751:1751)) + (PORT datad (1171:1171:1171) (1196:1196:1196)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~0) + (DELAY + (ABSOLUTE + (PORT dataa (951:951:951) (1017:1017:1017)) + (PORT datab (1649:1649:1649) (1785:1785:1785)) + (PORT datac (934:934:934) (1010:1010:1010)) + (PORT datad (1238:1238:1238) (1290:1290:1290)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1056:1056:1056) (1070:1070:1070)) + (PORT datab (665:665:665) (703:703:703)) + (PORT datac (194:194:194) (228:228:228)) + (PORT datad (181:181:181) (208:208:208)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (1322:1322:1322) (1436:1436:1436)) + (PORT datab (359:359:359) (391:391:391)) + (PORT datac (1243:1243:1243) (1275:1275:1275)) + (PORT datad (1324:1324:1324) (1428:1428:1428)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~33) + (DELAY + (ABSOLUTE + (PORT dataa (1134:1134:1134) (1183:1183:1183)) + (PORT datab (1731:1731:1731) (1830:1830:1830)) + (PORT datac (1336:1336:1336) (1440:1440:1440)) + (PORT datad (1344:1344:1344) (1422:1422:1422)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (1571:1571:1571) (1698:1698:1698)) + (PORT datab (1203:1203:1203) (1284:1284:1284)) + (PORT datac (1579:1579:1579) (1681:1681:1681)) + (PORT datad (181:181:181) (210:210:210)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~6) + (DELAY + (ABSOLUTE + (PORT dataa (964:964:964) (989:989:989)) + (PORT datab (909:909:909) (981:981:981)) + (PORT datac (1063:1063:1063) (1077:1077:1077)) + (PORT datad (189:189:189) (222:222:222)) + (IOPATH dataa combout (303:303:303) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~6) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (907:907:907) (935:935:935)) + (PORT datac (1323:1323:1323) (1342:1342:1342)) + (PORT datad (312:312:312) (332:332:332)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_hi\~7) + (DELAY + (ABSOLUTE + (PORT dataa (681:681:681) (738:738:738)) + (PORT datab (663:663:663) (725:725:725)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (195:195:195) (221:221:221)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~2) + (DELAY + (ABSOLUTE + (PORT dataa (628:628:628) (670:670:670)) + (PORT datab (1712:1712:1712) (1788:1788:1788)) + (PORT datac (937:937:937) (1023:1023:1023)) + (PORT datad (2493:2493:2493) (2650:2650:2650)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1217:1217:1217) (1262:1262:1262)) + (PORT datab (1353:1353:1353) (1438:1438:1438)) + (PORT datac (1518:1518:1518) (1594:1594:1594)) + (PORT datad (1975:1975:1975) (2069:2069:2069)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1683:1683:1683) (1795:1795:1795)) + (PORT datab (736:736:736) (782:782:782)) + (PORT datac (564:564:564) (587:587:587)) + (PORT datad (874:874:874) (900:900:900)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla27npla34M1T1_3) + (DELAY + (ABSOLUTE + (PORT dataa (751:751:751) (826:826:826)) + (PORT datab (1797:1797:1797) (1874:1874:1874)) + (PORT datac (2203:2203:2203) (2280:2280:2280)) + (PORT datad (694:694:694) (787:787:787)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~8) + (DELAY + (ABSOLUTE + (PORT dataa (876:876:876) (910:910:910)) + (PORT datab (196:196:196) (235:235:235)) + (PORT datac (1090:1090:1090) (1140:1140:1140)) + (PORT datad (179:179:179) (207:207:207)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~7) + (DELAY + (ABSOLUTE + (PORT dataa (665:665:665) (710:710:710)) + (PORT datab (602:602:602) (620:620:620)) + (PORT datac (1445:1445:1445) (1492:1492:1492)) + (PORT datad (836:836:836) (873:873:873)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~5) + (DELAY + (ABSOLUTE + (PORT dataa (988:988:988) (1050:1050:1050)) + (PORT datab (907:907:907) (974:974:974)) + (PORT datac (927:927:927) (971:971:971)) + (PORT datad (1125:1125:1125) (1181:1181:1181)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~19) + (DELAY + (ABSOLUTE + (PORT dataa (877:877:877) (918:918:918)) + (PORT datab (934:934:934) (991:991:991)) + (PORT datac (936:936:936) (999:999:999)) + (PORT datad (898:898:898) (915:915:915)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~18) + (DELAY + (ABSOLUTE + (PORT dataa (994:994:994) (1044:1044:1044)) + (PORT datab (688:688:688) (747:747:747)) + (PORT datac (1103:1103:1103) (1124:1124:1124)) + (PORT datad (656:656:656) (710:710:710)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~2) + (DELAY + (ABSOLUTE + (PORT dataa (396:396:396) (426:426:426)) + (PORT datab (218:218:218) (256:256:256)) + (PORT datac (213:213:213) (246:246:246)) + (PORT datad (1704:1704:1704) (1718:1718:1718)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal24\~1) + (DELAY + (ABSOLUTE + (PORT dataa (2523:2523:2523) (2690:2690:2690)) + (PORT datab (967:967:967) (1050:1050:1050)) + (PORT datac (1680:1680:1680) (1751:1751:1751)) + (PORT datad (908:908:908) (966:966:966)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~3) + (DELAY + (ABSOLUTE + (PORT dataa (901:901:901) (976:976:976)) + (PORT datab (1429:1429:1429) (1485:1485:1485)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (626:626:626) (675:675:675)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1188:1188:1188) (1243:1243:1243)) + (PORT datab (1357:1357:1357) (1444:1444:1444)) + (PORT datac (1250:1250:1250) (1340:1340:1340)) + (PORT datad (979:979:979) (1021:1021:1021)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~20) + (DELAY + (ABSOLUTE + (PORT dataa (618:618:618) (633:633:633)) + (PORT datab (597:597:597) (620:620:620)) + (PORT datac (974:974:974) (1034:1034:1034)) + (PORT datad (940:940:940) (987:987:987)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~5) + (DELAY + (ABSOLUTE + (PORT dataa (726:726:726) (763:763:763)) + (PORT datab (864:864:864) (922:922:922)) + (PORT datac (605:605:605) (625:625:625)) + (PORT datad (1117:1117:1117) (1166:1166:1166)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~22) + (DELAY + (ABSOLUTE + (PORT dataa (945:945:945) (999:999:999)) + (PORT datab (1189:1189:1189) (1233:1233:1233)) + (PORT datac (835:835:835) (854:854:854)) + (PORT datad (584:584:584) (629:629:629)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla42M3T3_6) + (DELAY + (ABSOLUTE + (PORT dataa (1179:1179:1179) (1244:1244:1244)) + (PORT datab (1085:1085:1085) (1155:1155:1155)) + (PORT datac (634:634:634) (659:659:659)) + (PORT datad (1671:1671:1671) (1806:1806:1806)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~6) + (DELAY + (ABSOLUTE + (PORT dataa (869:869:869) (901:901:901)) + (PORT datab (943:943:943) (965:965:965)) + (PORT datac (2100:2100:2100) (2201:2201:2201)) + (PORT datad (875:875:875) (929:929:929)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1922:1922:1922) (2033:2033:2033)) + (PORT datad (1201:1201:1201) (1281:1281:1281)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~30) + (DELAY + (ABSOLUTE + (PORT dataa (636:636:636) (660:660:660)) + (PORT datab (719:719:719) (753:753:753)) + (PORT datac (1032:1032:1032) (1114:1114:1114)) + (PORT datad (840:840:840) (883:883:883)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~23) + (DELAY + (ABSOLUTE + (PORT dataa (636:636:636) (654:654:654)) + (PORT datab (1280:1280:1280) (1351:1351:1351)) + (PORT datac (1031:1031:1031) (1113:1113:1113)) + (PORT datad (840:840:840) (882:882:882)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1381:1381:1381) (1435:1435:1435)) + (PORT datab (219:219:219) (258:258:258)) + (PORT datac (589:589:589) (623:623:623)) + (PORT datad (868:868:868) (903:903:903)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~3) + (DELAY + (ABSOLUTE + (PORT dataa (2277:2277:2277) (2380:2380:2380)) + (PORT datab (1135:1135:1135) (1157:1157:1157)) + (PORT datac (955:955:955) (999:999:999)) + (PORT datad (654:654:654) (706:706:706)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~10) + (DELAY + (ABSOLUTE + (PORT dataa (848:848:848) (859:859:859)) + (PORT datab (800:800:800) (804:804:804)) + (PORT datad (1152:1152:1152) (1151:1151:1151)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~18) + (DELAY + (ABSOLUTE + (PORT dataa (881:881:881) (914:914:914)) + (PORT datab (1241:1241:1241) (1283:1283:1283)) + (PORT datac (1219:1219:1219) (1260:1260:1260)) + (PORT datad (1131:1131:1131) (1133:1133:1133)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_pc\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1171:1171:1171) (1204:1204:1204)) + (PORT datab (883:883:883) (956:956:956)) + (PORT datac (1863:1863:1863) (1953:1953:1953)) + (PORT datad (667:667:667) (715:715:715)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_pc\~1) + (DELAY + (ABSOLUTE + (PORT dataa (900:900:900) (975:975:975)) + (PORT datab (243:243:243) (289:289:289)) + (PORT datac (214:214:214) (247:247:247)) + (PORT datad (931:931:931) (953:953:953)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_pc\~2) + (DELAY + (ABSOLUTE + (PORT dataa (668:668:668) (708:708:708)) + (PORT datab (244:244:244) (292:292:292)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (1703:1703:1703) (1718:1718:1718)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~19) + (DELAY + (ABSOLUTE + (PORT dataa (922:922:922) (965:965:965)) + (PORT datab (686:686:686) (707:707:707)) + (PORT datac (1217:1217:1217) (1260:1260:1260)) + (PORT datad (672:672:672) (725:725:725)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~20) + (DELAY + (ABSOLUTE + (PORT dataa (606:606:606) (633:633:633)) + (PORT datab (220:220:220) (258:258:258)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~21) + (DELAY + (ABSOLUTE + (PORT dataa (914:914:914) (973:973:973)) + (PORT datab (843:843:843) (926:926:926)) + (PORT datac (201:201:201) (237:237:237)) + (PORT datad (630:630:630) (676:676:676)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~9) + (DELAY + (ABSOLUTE + (PORT dataa (644:644:644) (695:695:695)) + (PORT datab (641:641:641) (683:683:683)) + (PORT datac (1183:1183:1183) (1242:1242:1242)) + (PORT datad (610:610:610) (646:646:646)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1726:1726:1726) (1799:1799:1799)) + (PORT datab (309:309:309) (407:407:407)) + (PORT datac (847:847:847) (860:860:860)) + (PORT datad (585:585:585) (601:601:601)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_1d\~8) + (DELAY + (ABSOLUTE + (PORT dataa (2003:2003:2003) (2195:2195:2195)) + (PORT datab (1221:1221:1221) (1318:1318:1318)) + (PORT datac (680:680:680) (711:711:711)) + (PORT datad (1269:1269:1269) (1352:1352:1352)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~10) + (DELAY + (ABSOLUTE + (PORT dataa (654:654:654) (703:703:703)) + (PORT datab (1127:1127:1127) (1205:1205:1205)) + (PORT datac (905:905:905) (942:942:942)) + (PORT datad (1157:1157:1157) (1213:1213:1213)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~11) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (1223:1223:1223) (1239:1239:1239)) + (PORT datac (713:713:713) (793:793:793)) + (PORT datad (171:171:171) (196:196:196)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1188:1188:1188) (1235:1235:1235)) + (PORT datab (962:962:962) (1003:1003:1003)) + (PORT datac (601:601:601) (615:615:615)) + (PORT datad (855:855:855) (895:895:895)) + (IOPATH dataa combout (303:303:303) (299:299:299)) (IOPATH datab combout (304:304:304) (308:308:308)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2d\~13) + (DELAY + (ABSOLUTE + (PORT dataa (894:894:894) (932:932:932)) + (PORT datab (200:200:200) (240:240:240)) + (PORT datac (822:822:822) (843:843:843)) + (PORT datad (834:834:834) (852:852:852)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[7\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (644:644:644) (670:670:670)) + (PORT datac (587:587:587) (602:602:602)) + (PORT datad (699:699:699) (727:727:727)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|SYNTHESIZED_WIRE_2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (631:631:631) (702:702:702)) + (PORT datab (1106:1106:1106) (1116:1116:1116)) + (PORT datac (315:315:315) (342:342:342)) + (PORT datad (1985:1985:1985) (2137:2137:2137)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla89M1T2_3) + (DELAY + (ABSOLUTE + (PORT dataa (1830:1830:1830) (1937:1937:1937)) + (PORT datab (937:937:937) (1014:1014:1014)) + (PORT datac (891:891:891) (955:955:955)) + (PORT datad (1116:1116:1116) (1171:1171:1171)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~32) + (DELAY + (ABSOLUTE + (PORT dataa (674:674:674) (722:722:722)) + (PORT datab (950:950:950) (998:998:998)) + (PORT datac (1223:1223:1223) (1290:1290:1290)) + (PORT datad (2080:2080:2080) (2164:2164:2164)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~2) + (DELAY + (ABSOLUTE + (PORT dataa (921:921:921) (987:987:987)) + (PORT datab (1589:1589:1589) (1689:1689:1689)) + (PORT datac (1933:1933:1933) (2076:2076:2076)) + (PORT datad (637:637:637) (680:680:680)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~22) + (DELAY + (ABSOLUTE + (PORT dataa (1966:1966:1966) (2055:2055:2055)) + (PORT datab (960:960:960) (1020:1020:1020)) + (PORT datac (2103:2103:2103) (2213:2213:2213)) + (PORT datad (1127:1127:1127) (1179:1179:1179)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~3) + (DELAY + (ABSOLUTE + (PORT dataa (659:659:659) (707:707:707)) + (PORT datab (200:200:200) (239:239:239)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~4) + (DELAY + (ABSOLUTE + (PORT dataa (606:606:606) (634:634:634)) + (PORT datab (634:634:634) (651:651:651)) + (PORT datac (852:852:852) (861:861:861)) + (PORT datad (619:619:619) (671:671:671)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~5) + (DELAY + (ABSOLUTE + (PORT dataa (602:602:602) (639:639:639)) + (PORT datab (1150:1150:1150) (1196:1196:1196)) + (PORT datac (217:217:217) (261:261:261)) + (PORT datad (617:617:617) (626:626:626)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1256:1256:1256) (1357:1357:1357)) + (PORT datab (1414:1414:1414) (1475:1475:1475)) + (PORT datac (637:637:637) (694:694:694)) + (PORT datad (1773:1773:1773) (1906:1906:1906)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~13) + (DELAY + (ABSOLUTE + (PORT dataa (654:654:654) (684:684:684)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (218:218:218) (262:262:262)) + (PORT datad (196:196:196) (221:221:221)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1005:1005:1005) (1135:1135:1135)) + (PORT datab (227:227:227) (270:270:270)) + (PORT datac (1120:1120:1120) (1159:1159:1159)) + (PORT datad (611:611:611) (638:638:638)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~6) + (DELAY + (ABSOLUTE + (PORT datab (569:569:569) (591:591:591)) + (PORT datac (322:322:322) (351:351:351)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~7) + (DELAY + (ABSOLUTE + (PORT dataa (375:375:375) (400:400:400)) + (PORT datab (208:208:208) (251:251:251)) + (PORT datac (171:171:171) (205:205:205)) + (PORT datad (574:574:574) (601:601:601)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_nop3pla68M1T3_2) + (DELAY + (ABSOLUTE + (PORT dataa (1692:1692:1692) (1735:1735:1735)) + (PORT datab (1411:1411:1411) (1454:1454:1454)) + (PORT datac (1930:1930:1930) (1994:1994:1994)) + (PORT datad (919:919:919) (992:992:992)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2368:2368:2368) (2429:2429:2429)) + (PORT datab (200:200:200) (239:239:239)) + (PORT datac (894:894:894) (932:932:932)) + (PORT datad (1352:1352:1352) (1390:1390:1390)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~17) + (DELAY + (ABSOLUTE + (PORT dataa (977:977:977) (1073:1073:1073)) + (PORT datab (230:230:230) (271:271:271)) + (PORT datac (1199:1199:1199) (1225:1225:1225)) + (PORT datad (858:858:858) (898:898:898)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1938:1938:1938) (1958:1958:1958)) + (PORT datab (198:198:198) (238:238:238)) + (PORT datac (194:194:194) (227:227:227)) + (PORT datad (1135:1135:1135) (1178:1178:1178)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~2) + (DELAY + (ABSOLUTE + (PORT dataa (840:840:840) (888:888:888)) + (PORT datab (655:655:655) (683:683:683)) + (PORT datac (833:833:833) (838:838:838)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (2369:2369:2369) (2430:2430:2430)) + (PORT datab (1735:1735:1735) (1787:1787:1787)) + (PORT datac (895:895:895) (929:929:929)) + (PORT datad (1351:1351:1351) (1387:1387:1387)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1169:1169:1169) (1230:1230:1230)) + (PORT datab (1101:1101:1101) (1165:1165:1165)) + (PORT datac (2016:2016:2016) (2103:2103:2103)) + (PORT datad (1737:1737:1737) (1808:1808:1808)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal73\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1993:1993:1993) (2185:2185:2185)) + (PORT datab (1209:1209:1209) (1305:1305:1305)) + (PORT datac (967:967:967) (992:992:992)) + (PORT datad (1278:1278:1278) (1365:1365:1365)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal72\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1002:1002:1002) (1133:1133:1133)) + (PORT datab (226:226:226) (266:266:266)) + (PORT datac (1116:1116:1116) (1197:1197:1197)) + (PORT datad (1497:1497:1497) (1581:1581:1581)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~1) + (DELAY + (ABSOLUTE + (PORT dataa (654:654:654) (678:678:678)) + (PORT datab (197:197:197) (237:237:237)) + (PORT datac (1112:1112:1112) (1136:1136:1136)) + (PORT datad (602:602:602) (621:621:621)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (351:351:351) (382:382:382)) + (PORT datab (570:570:570) (590:590:590)) + (PORT datac (321:321:321) (350:350:350)) + (PORT datad (801:801:801) (849:849:849)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (679:679:679) (764:764:764)) + (PORT datab (1518:1518:1518) (1635:1635:1635)) + (PORT datad (982:982:982) (1050:1050:1050)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (928:928:928) (999:999:999)) + (PORT datac (2233:2233:2233) (2307:2307:2307)) + (PORT datad (877:877:877) (925:925:925)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (578:578:578) (612:612:612)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (1452:1452:1452) (1529:1529:1529)) + (PORT datad (577:577:577) (602:602:602)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~8) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (565:565:565) (594:594:594)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~14) + (DELAY + (ABSOLUTE + (PORT datab (1111:1111:1111) (1193:1193:1193)) + (PORT datad (1341:1341:1341) (1439:1439:1439)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~10) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (380:380:380) (414:414:414)) + (PORT datac (1736:1736:1736) (1805:1805:1805)) + (PORT datad (180:180:180) (209:209:209)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal45\~0) + (DELAY + (ABSOLUTE + (PORT dataa (943:943:943) (965:965:965)) + (PORT datab (1161:1161:1161) (1240:1240:1240)) + (PORT datac (1214:1214:1214) (1321:1321:1321)) + (PORT datad (1622:1622:1622) (1713:1713:1713)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1238:1238:1238) (1300:1300:1300)) + (PORT datab (882:882:882) (904:904:904)) + (PORT datac (1153:1153:1153) (1191:1191:1191)) + (PORT datad (1675:1675:1675) (1682:1682:1682)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1253:1253:1253) (1274:1274:1274)) + (PORT datab (960:960:960) (1020:1020:1020)) + (PORT datac (1803:1803:1803) (1899:1899:1899)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1563:1563:1563) (1648:1648:1648)) + (PORT datab (1247:1247:1247) (1330:1330:1330)) + (PORT datac (173:173:173) (206:206:206)) + (PORT datad (990:990:990) (1070:1070:1070)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~8) + (DELAY + (ABSOLUTE + (PORT dataa (886:886:886) (931:931:931)) + (PORT datab (598:598:598) (607:607:607)) + (PORT datac (354:354:354) (377:377:377)) + (PORT datad (1043:1043:1043) (1093:1093:1093)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~9) + (DELAY + (ABSOLUTE + (PORT dataa (654:654:654) (674:674:674)) + (PORT datac (620:620:620) (647:647:647)) + (PORT datad (602:602:602) (621:621:621)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S\~10) + (DELAY + (ABSOLUTE + (PORT dataa (609:609:609) (630:630:630)) + (PORT datab (652:652:652) (663:663:663)) + (PORT datac (337:337:337) (364:364:364)) + (PORT datad (821:821:821) (826:826:826)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_S) + (DELAY + (ABSOLUTE + (PORT dataa (871:871:871) (889:889:889)) + (PORT datab (206:206:206) (248:248:248)) + (PORT datac (381:381:381) (416:416:416)) + (PORT datad (610:610:610) (620:620:620)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[3\]) + (DELAY + (ABSOLUTE + (PORT dataa (714:714:714) (762:762:762)) + (PORT datac (890:890:890) (917:917:917)) + (PORT datad (832:832:832) (845:845:845)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|ena\~0) + (DELAY + (ABSOLUTE + (PORT dataa (949:949:949) (979:979:979)) + (PORT datac (889:889:889) (914:914:914)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_high\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1547:1547:1547) (1549:1549:1549)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op1\[3\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1171:1171:1171) (1243:1243:1243)) + (PORT datab (687:687:687) (716:716:716)) + (PORT datac (407:407:407) (483:483:483)) + (PORT datad (430:430:430) (502:502:502)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|SYNTHESIZED_WIRE_10\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1286:1286:1286) (1369:1369:1369)) + (PORT datac (193:193:193) (226:226:226)) + (PORT datad (203:203:203) (232:232:232)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_we_lo\~2) + (DELAY + (ABSOLUTE + (PORT datab (951:951:951) (991:991:991)) + (PORT datac (1196:1196:1196) (1230:1230:1230)) + (PORT datad (2493:2493:2493) (2650:2650:2650)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_we_lo\~3) + (DELAY + (ABSOLUTE + (PORT dataa (956:956:956) (991:991:991)) + (PORT datab (355:355:355) (385:385:385)) + (PORT datac (1167:1167:1167) (1226:1226:1226)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~14) + (DELAY + (ABSOLUTE + (PORT dataa (869:869:869) (900:900:900)) + (PORT datab (946:946:946) (967:967:967)) + (PORT datac (876:876:876) (883:883:883)) + (PORT datad (925:925:925) (1020:1020:1020)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_hi\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1873:1873:1873) (1898:1898:1898)) + (PORT datab (944:944:944) (963:963:963)) + (PORT datac (2100:2100:2100) (2199:2199:2199)) + (PORT datad (181:181:181) (208:208:208)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal33\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1216:1216:1216) (1312:1312:1312)) + (PORT datab (1851:1851:1851) (1863:1863:1863)) + (PORT datac (921:921:921) (968:968:968)) + (PORT datad (950:950:950) (1030:1030:1030)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~0) + (DELAY + (ABSOLUTE + (PORT dataa (655:655:655) (704:704:704)) + (PORT datab (640:640:640) (661:661:661)) + (PORT datac (1432:1432:1432) (1481:1481:1481)) + (PORT datad (913:913:913) (957:957:957)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (948:948:948) (995:995:995)) + (PORT datab (205:205:205) (245:245:245)) + (PORT datac (2069:2069:2069) (2220:2220:2220)) + (PORT datad (1163:1163:1163) (1227:1227:1227)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (814:814:814) (843:843:843)) + (PORT datab (651:651:651) (693:693:693)) + (PORT datac (1541:1541:1541) (1564:1564:1564)) + (PORT datad (1078:1078:1078) (1112:1112:1112)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~4) + (DELAY + (ABSOLUTE + (PORT dataa (883:883:883) (921:921:921)) + (PORT datab (1052:1052:1052) (1120:1120:1120)) + (PORT datac (652:652:652) (708:708:708)) + (PORT datad (639:639:639) (696:696:696)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sys_we_hi) + (DELAY + (ABSOLUTE + (PORT dataa (898:898:898) (916:916:916)) + (PORT datab (885:885:885) (897:897:897)) + (PORT datad (185:185:185) (217:217:217)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (917:917:917) (986:986:986)) + (PORT datab (1287:1287:1287) (1375:1375:1375)) + (PORT datac (1229:1229:1229) (1337:1337:1337)) + (PORT datad (1191:1191:1191) (1247:1247:1247)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1231:1231:1231) (1292:1292:1292)) + (PORT datab (1815:1815:1815) (1890:1890:1890)) + (PORT datac (853:853:853) (898:898:898)) + (PORT datad (1260:1260:1260) (1341:1341:1341)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1364:1364:1364) (1422:1422:1422)) + (PORT datab (1769:1769:1769) (1787:1787:1787)) + (PORT datac (1143:1143:1143) (1192:1192:1192)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~12) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (394:394:394) (428:428:428)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (361:361:361) (392:392:392)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~13) + (DELAY + (ABSOLUTE + (PORT dataa (229:229:229) (278:278:278)) + (PORT datab (1732:1732:1732) (1770:1770:1770)) + (PORT datac (568:568:568) (573:573:573)) + (PORT datad (1511:1511:1511) (1602:1602:1602)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla56M3T3_6) + (DELAY + (ABSOLUTE + (PORT dataa (1180:1180:1180) (1242:1242:1242)) + (PORT datab (669:669:669) (696:696:696)) + (PORT datac (1304:1304:1304) (1370:1370:1370)) + (PORT datad (1674:1674:1674) (1808:1808:1808)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1273:1273:1273) (1322:1322:1322)) + (PORT datab (1235:1235:1235) (1269:1269:1269)) + (PORT datac (591:591:591) (626:626:626)) + (PORT datad (203:203:203) (231:231:231)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~7) + (DELAY + (ABSOLUTE + (PORT dataa (905:905:905) (919:919:919)) + (PORT datab (227:227:227) (267:267:267)) + (PORT datac (2102:2102:2102) (2199:2199:2199)) + (PORT datad (802:802:802) (830:830:830)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1767:1767:1767) (1883:1883:1883)) + (PORT datab (1504:1504:1504) (1590:1590:1590)) + (PORT datac (1111:1111:1111) (1116:1116:1116)) + (PORT datad (187:187:187) (218:218:218)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (1341:1341:1341) (1400:1400:1400)) + (PORT datab (633:633:633) (676:676:676)) + (PORT datac (613:613:613) (649:649:649)) + (PORT datad (1395:1395:1395) (1455:1455:1455)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~8) + (DELAY + (ABSOLUTE + (PORT dataa (899:899:899) (959:959:959)) + (PORT datac (1093:1093:1093) (1116:1116:1116)) + (PORT datad (1195:1195:1195) (1215:1215:1215)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (608:608:608) (670:670:670)) + (PORT datab (665:665:665) (684:684:684)) + (PORT datac (607:607:607) (657:657:657)) + (PORT datad (926:926:926) (953:953:953)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (683:683:683) (741:741:741)) + (PORT datab (371:371:371) (411:411:411)) + (PORT datac (1161:1161:1161) (1224:1224:1224)) + (PORT datad (1144:1144:1144) (1209:1209:1209)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~41) + (DELAY + (ABSOLUTE + (PORT dataa (1153:1153:1153) (1173:1173:1173)) + (PORT datab (1815:1815:1815) (1890:1890:1890)) + (PORT datac (1133:1133:1133) (1169:1169:1169)) + (PORT datad (1259:1259:1259) (1341:1341:1341)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~10) + (DELAY + (ABSOLUTE + (PORT dataa (942:942:942) (998:998:998)) + (PORT datac (881:881:881) (928:928:928)) + (PORT datad (913:913:913) (970:970:970)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\~21) + (DELAY + (ABSOLUTE + (PORT dataa (1624:1624:1624) (1764:1764:1764)) + (PORT datab (917:917:917) (973:973:973)) + (PORT datad (1620:1620:1620) (1708:1708:1708)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~3) + (DELAY + (ABSOLUTE + (PORT dataa (286:286:286) (384:384:384)) + (PORT datab (270:270:270) (355:355:355)) + (PORT datad (245:245:245) (317:317:317)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (832:832:832) (859:859:859)) + (PORT datab (1173:1173:1173) (1194:1194:1194)) + (PORT datac (853:853:853) (852:852:852)) + (PORT datad (195:195:195) (220:220:220)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (251:251:251)) + (PORT datab (654:654:654) (674:674:674)) + (PORT datac (1329:1329:1329) (1368:1368:1368)) + (PORT datad (1055:1055:1055) (1101:1101:1101)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (1471:1471:1471) (1518:1518:1518)) + (PORT datab (951:951:951) (992:992:992)) + (PORT datac (613:613:613) (630:630:630)) + (PORT datad (617:617:617) (654:654:654)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (955:955:955) (1003:1003:1003)) + (PORT datab (1697:1697:1697) (1738:1738:1738)) + (PORT datac (1328:1328:1328) (1367:1367:1367)) + (PORT datad (328:328:328) (353:353:353)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1557:1557:1557) (1655:1655:1655)) + (PORT datac (963:963:963) (1037:1037:1037)) + (PORT datad (906:906:906) (970:970:970)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (1204:1204:1204) (1246:1246:1246)) + (PORT datab (1074:1074:1074) (1106:1106:1106)) + (PORT datac (915:915:915) (939:939:939)) + (PORT datad (216:216:216) (252:252:252)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (406:406:406) (452:452:452)) + (PORT datab (597:597:597) (624:624:624)) + (PORT datad (1125:1125:1125) (1177:1177:1177)) + (IOPATH dataa combout (301:301:301) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (886:886:886) (941:941:941)) + (PORT datab (243:243:243) (290:290:290)) + (PORT datad (847:847:847) (880:880:880)) + (IOPATH dataa combout (301:301:301) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (921:921:921) (958:958:958)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (220:220:220) (263:263:263)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (1539:1539:1539) (1627:1627:1627)) + (PORT datad (570:570:570) (583:583:583)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~30) (DELAY (ABSOLUTE - (PORT dataa (631:631:631) (660:660:660)) - (PORT datab (1249:1249:1249) (1275:1275:1275)) - (PORT datac (1822:1822:1822) (1900:1900:1900)) - (PORT datad (1106:1106:1106) (1134:1134:1134)) - (IOPATH dataa combout (327:327:327) (347:347:347)) + (PORT dataa (895:895:895) (943:943:943)) + (PORT datab (580:580:580) (595:595:595)) + (PORT datac (841:841:841) (867:867:867)) + (PORT datad (497:497:497) (505:505:505)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~13) + (DELAY + (ABSOLUTE + (PORT dataa (2017:2017:2017) (2107:2107:2107)) + (PORT datab (947:947:947) (968:968:968)) + (PORT datac (2102:2102:2102) (2203:2203:2203)) + (PORT datad (202:202:202) (230:230:230)) + (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -16276,11 +10912,11 @@ (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~32) (DELAY (ABSOLUTE - (PORT dataa (640:640:640) (687:687:687)) - (PORT datab (905:905:905) (971:971:971)) - (PORT datac (861:861:861) (888:888:888)) - (PORT datad (171:171:171) (196:196:196)) - (IOPATH dataa combout (371:371:371) (376:376:376)) + (PORT dataa (870:870:870) (898:898:898)) + (PORT datab (815:815:815) (899:899:899)) + (PORT datac (917:917:917) (934:934:934)) + (PORT datad (876:876:876) (927:927:927)) + (IOPATH dataa combout (327:327:327) (347:347:347)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -16292,28 +10928,12 @@ (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~33) (DELAY (ABSOLUTE - (PORT dataa (208:208:208) (256:256:256)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (1153:1153:1153) (1178:1178:1178)) - (PORT datad (204:204:204) (241:241:241)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_hi\~0) - (DELAY - (ABSOLUTE - (PORT dataa (713:713:713) (766:766:766)) - (PORT datab (205:205:205) (245:245:245)) - (PORT datac (346:346:346) (370:370:370)) - (PORT datad (1145:1145:1145) (1176:1176:1176)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (1510:1510:1510) (1595:1595:1595)) + (PORT datab (234:234:234) (278:278:278)) + (PORT datac (1578:1578:1578) (1617:1617:1617)) + (PORT datad (2293:2293:2293) (2360:2360:2360)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -16321,12 +10941,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_hi) + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~34) (DELAY (ABSOLUTE - (PORT datab (922:922:922) (944:944:944)) - (PORT datac (595:595:595) (615:615:615)) - (PORT datad (181:181:181) (212:212:212)) + (PORT dataa (1667:1667:1667) (1727:1727:1727)) + (PORT datab (658:658:658) (688:688:688)) + (PORT datac (1225:1225:1225) (1319:1319:1319)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -16335,12 +10957,28 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_81) + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~35) (DELAY (ABSOLUTE - (PORT dataa (877:877:877) (900:900:900)) - (PORT datac (1144:1144:1144) (1163:1163:1163)) - (PORT datad (832:832:832) (861:861:861)) + (PORT dataa (208:208:208) (255:255:255)) + (PORT datab (651:651:651) (673:673:673)) + (PORT datac (177:177:177) (215:215:215)) + (PORT datad (1154:1154:1154) (1258:1258:1258)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_73) + (DELAY + (ABSOLUTE + (PORT dataa (1040:1040:1040) (1067:1067:1067)) + (PORT datac (1098:1098:1098) (1139:1139:1139)) + (PORT datad (899:899:899) (934:934:934)) (IOPATH dataa combout (304:304:304) (307:307:307)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -16349,12 +10987,86 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[3\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[3\]) (DELAY (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (1506:1506:1506) (1545:1545:1545)) - (PORT ena (1261:1261:1261) (1299:1299:1299)) + (PORT clk (1520:1520:1520) (1533:1533:1533)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1256:1256:1256) (1263:1263:1263)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_ir\~0) + (DELAY + (ABSOLUTE + (PORT datab (1019:1019:1019) (1083:1083:1083)) + (PORT datac (962:962:962) (1040:1040:1040)) + (PORT datad (950:950:950) (1010:1010:1010)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_ir\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1305:1305:1305) (1390:1390:1390)) + (PORT datab (1378:1378:1378) (1422:1422:1422)) + (PORT datac (343:343:343) (366:366:366)) + (PORT datad (812:812:812) (886:886:886)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_60) + (DELAY + (ABSOLUTE + (PORT datab (927:927:927) (977:977:977)) + (PORT datac (1099:1099:1099) (1140:1140:1140)) + (PORT datad (798:798:798) (805:805:805)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_61) + (DELAY + (ABSOLUTE + (PORT datab (926:926:926) (973:973:973)) + (PORT datac (1100:1100:1100) (1142:1142:1142)) + (PORT datad (798:798:798) (804:804:804)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1533:1533:1533)) + (PORT asdata (537:537:537) (567:567:567)) + (PORT ena (1448:1448:1448) (1437:1437:1437)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -16365,28 +11077,60 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_80) + (INSTANCE z80_\|execute_\|ctl_reg_sys_we_lo\~4) (DELAY (ABSOLUTE - (PORT dataa (874:874:874) (899:899:899)) - (PORT datac (1138:1138:1138) (1159:1159:1159)) - (PORT datad (835:835:835) (861:861:861)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT datab (1167:1167:1167) (1178:1178:1178)) + (PORT datac (1620:1620:1620) (1701:1701:1701)) + (PORT datad (922:922:922) (986:986:986)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~45) + (INSTANCE z80_\|reg_control_\|reg_sys_we_lo) (DELAY (ABSOLUTE - (PORT dataa (1100:1100:1100) (1149:1149:1149)) - (PORT datab (1280:1280:1280) (1386:1386:1386)) - (PORT datad (842:842:842) (869:869:869)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT dataa (621:621:621) (685:685:685)) + (PORT datab (199:199:199) (239:239:239)) + (PORT datac (1721:1721:1721) (1776:1776:1776)) + (PORT datad (855:855:855) (858:858:858)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sw_4d_hi\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1106:1106:1106) (1116:1116:1116)) + (PORT datab (930:930:930) (973:973:973)) + (PORT datac (1150:1150:1150) (1188:1188:1188)) + (PORT datad (798:798:798) (803:803:803)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (888:888:888) (915:915:915)) + (PORT datab (675:675:675) (708:708:708)) + (PORT datad (674:674:674) (703:703:703)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -16394,47 +11138,71 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_41\~0) + (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~11) (DELAY (ABSOLUTE - (PORT dataa (638:638:638) (693:693:693)) - (PORT datab (1259:1259:1259) (1346:1346:1346)) - (PORT datac (1146:1146:1146) (1187:1187:1187)) - (PORT datad (374:374:374) (412:412:412)) + (PORT datab (687:687:687) (708:708:708)) + (PORT datac (358:358:358) (423:423:423)) + (PORT datad (317:317:317) (329:329:329)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[11\]) + (DELAY + (ABSOLUTE + (PORT dataa (679:679:679) (697:697:697)) + (PORT datac (582:582:582) (602:602:602)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_apin_mux\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1030:1030:1030) (1119:1119:1119)) + (PORT datab (1518:1518:1518) (1635:1635:1635)) + (PORT datac (1117:1117:1117) (1167:1167:1167)) (IOPATH dataa combout (354:354:354) (349:349:349)) (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~37) + (DELAY + (ABSOLUTE + (PORT dataa (1277:1277:1277) (1377:1377:1377)) + (PORT datab (1354:1354:1354) (1443:1443:1443)) + (PORT datac (1715:1715:1715) (1795:1795:1795)) + (PORT datad (975:975:975) (1020:1020:1020)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (990:990:990) (1035:1035:1035)) - (PORT ena (1193:1193:1193) (1176:1176:1176)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_36\~0) + (INSTANCE z80_\|execute_\|ctl_inc_dec\~2) (DELAY (ABSOLUTE - (PORT dataa (404:404:404) (462:462:462)) - (PORT datab (1258:1258:1258) (1341:1341:1341)) - (PORT datac (1142:1142:1142) (1186:1186:1186)) - (PORT datad (664:664:664) (686:686:686)) + (PORT dataa (1213:1213:1213) (1259:1259:1259)) + (PORT datab (1016:1016:1016) (1060:1060:1060)) + (PORT datac (1158:1158:1158) (1222:1222:1222)) + (PORT datad (194:194:194) (219:219:219)) (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datab combout (336:336:336) (332:332:332)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -16442,13 +11210,77 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_37\~0) + (INSTANCE z80_\|execute_\|ctl_inc_cy\~40) (DELAY (ABSOLUTE - (PORT dataa (639:639:639) (696:696:696)) - (PORT datab (1255:1255:1255) (1339:1339:1339)) - (PORT datac (1141:1141:1141) (1184:1184:1184)) - (PORT datad (375:375:375) (413:413:413)) + (PORT dataa (1746:1746:1746) (1830:1830:1830)) + (PORT datab (1356:1356:1356) (1439:1439:1439)) + (PORT datac (1514:1514:1514) (1589:1589:1589)) + (PORT datad (1458:1458:1458) (1519:1519:1519)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~4) + (DELAY + (ABSOLUTE + (PORT dataa (2047:2047:2047) (2159:2159:2159)) + (PORT datab (219:219:219) (258:258:258)) + (PORT datac (1157:1157:1157) (1221:1221:1221)) + (PORT datad (1817:1817:1817) (1893:1893:1893)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1213:1213:1213) (1263:1263:1263)) + (PORT datab (207:207:207) (250:250:250)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (1456:1456:1456) (1521:1521:1521)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (675:675:675) (747:747:747)) + (PORT datab (1133:1133:1133) (1173:1173:1173)) + (PORT datac (1505:1505:1505) (1624:1624:1624)) + (PORT datad (1434:1434:1434) (1501:1501:1501)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla6M1T4_4) + (DELAY + (ABSOLUTE + (PORT dataa (1306:1306:1306) (1391:1391:1391)) + (PORT datab (966:966:966) (1005:1005:1005)) + (PORT datac (1643:1643:1643) (1693:1693:1693)) + (PORT datad (970:970:970) (1027:1027:1027)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -16457,30 +11289,742 @@ ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[3\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~42) (DELAY (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (989:989:989) (1035:1035:1035)) - (PORT ena (1283:1283:1283) (1283:1283:1283)) + (PORT dataa (1075:1075:1075) (1128:1128:1128)) + (PORT datac (814:814:814) (867:867:867)) + (PORT datad (1664:1664:1664) (1683:1683:1683)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (264:264:264)) + (PORT datab (213:213:213) (257:257:257)) + (PORT datac (783:783:783) (838:838:838)) + (PORT datad (1281:1281:1281) (1350:1350:1350)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_1d\~4) + (DELAY + (ABSOLUTE + (PORT dataa (674:674:674) (713:713:713)) + (PORT datab (689:689:689) (753:753:753)) + (PORT datac (922:922:922) (973:973:973)) + (PORT datad (1125:1125:1125) (1154:1154:1154)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~3) + (DELAY + (ABSOLUTE + (PORT datab (868:868:868) (939:939:939)) + (PORT datac (584:584:584) (610:610:610)) + (PORT datad (603:603:603) (622:622:622)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~9) + (DELAY + (ABSOLUTE + (PORT dataa (834:834:834) (885:885:885)) + (PORT datab (1220:1220:1220) (1298:1298:1298)) + (PORT datac (1748:1748:1748) (1824:1824:1824)) + (PORT datad (1447:1447:1447) (1467:1467:1467)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1781:1781:1781) (1865:1865:1865)) + (PORT datab (196:196:196) (235:235:235)) + (PORT datac (1671:1671:1671) (1712:1712:1712)) + (PORT datad (1446:1446:1446) (1465:1465:1465)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~8) + (DELAY + (ABSOLUTE + (PORT dataa (2024:2024:2024) (2123:2123:2123)) + (PORT datab (1444:1444:1444) (1474:1474:1474)) + (PORT datac (668:668:668) (691:691:691)) + (PORT datad (1093:1093:1093) (1141:1141:1141)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~2) + (DELAY + (ABSOLUTE + (PORT dataa (401:401:401) (449:449:449)) + (PORT datab (221:221:221) (260:260:260)) + (PORT datad (783:783:783) (837:837:837)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~11) + (DELAY + (ABSOLUTE + (PORT dataa (356:356:356) (399:399:399)) + (PORT datab (1697:1697:1697) (1741:1741:1741)) + (PORT datac (1324:1324:1324) (1368:1368:1368)) + (PORT datad (181:181:181) (212:212:212)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~12) + (DELAY + (ABSOLUTE + (PORT datac (841:841:841) (870:870:870)) + (PORT datad (840:840:840) (834:834:834)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1790:1790:1790) (1875:1875:1875)) + (PORT datab (242:242:242) (289:289:289)) + (PORT datac (662:662:662) (700:700:700)) + (PORT datad (929:929:929) (952:952:952)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4d\~5) + (DELAY + (ABSOLUTE + (PORT dataa (881:881:881) (908:908:908)) + (PORT datab (603:603:603) (635:635:635)) + (PORT datac (355:355:355) (384:384:384)) + (PORT datad (614:614:614) (628:628:628)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1430:1430:1430) (1499:1499:1499)) + (PORT datab (1185:1185:1185) (1226:1226:1226)) + (PORT datac (624:624:624) (688:688:688)) + (PORT datad (1209:1209:1209) (1274:1274:1274)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~10) + (DELAY + (ABSOLUTE + (PORT dataa (385:385:385) (415:415:415)) + (PORT datac (1063:1063:1063) (1070:1070:1070)) + (PORT datad (595:595:595) (604:604:604)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1874:1874:1874) (1932:1932:1932)) + (PORT datab (395:395:395) (431:431:431)) + (PORT datac (1474:1474:1474) (1511:1511:1511)) + (PORT datad (362:362:362) (392:392:392)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1179:1179:1179) (1222:1222:1222)) + (PORT datab (601:601:601) (615:615:615)) + (PORT datac (356:356:356) (383:383:383)) + (PORT datad (218:218:218) (254:254:254)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (854:854:854) (911:911:911)) + (PORT datab (640:640:640) (701:701:701)) + (PORT datac (1847:1847:1847) (1863:1863:1863)) + (PORT datad (603:603:603) (644:644:644)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~9) + (DELAY + (ABSOLUTE + (PORT dataa (658:658:658) (675:675:675)) + (PORT datab (1485:1485:1485) (1542:1542:1542)) + (PORT datac (618:618:618) (638:638:638)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~11) + (DELAY + (ABSOLUTE + (PORT dataa (608:608:608) (637:637:637)) + (PORT datab (206:206:206) (246:246:246)) + (PORT datac (171:171:171) (203:203:203)) + (PORT datad (172:172:172) (198:198:198)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_al_we\~12) + (DELAY + (ABSOLUTE + (PORT dataa (233:233:233) (282:282:282)) + (PORT datab (1735:1735:1735) (1773:1773:1773)) + (PORT datac (343:343:343) (367:367:367)) + (PORT datad (1513:1513:1513) (1604:1604:1604)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1562:1562:1562) (1544:1544:1544)) + (PORT ena (1676:1676:1676) (1678:1678:1678)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) + (HOLD d (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_40\~0) + (INSTANCE z80_\|execute_\|fIOWrite\~0) (DELAY (ABSOLUTE - (PORT dataa (402:402:402) (457:457:457)) - (PORT datab (1258:1258:1258) (1344:1344:1344)) - (PORT datac (1146:1146:1146) (1187:1187:1187)) - (PORT datad (666:666:666) (682:682:682)) + (PORT dataa (2133:2133:2133) (2247:2247:2247)) + (PORT datab (2287:2287:2287) (2396:2396:2396)) + (PORT datac (1558:1558:1558) (1657:1657:1657)) + (PORT datad (2000:2000:2000) (2096:2096:2096)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~8) + (DELAY + (ABSOLUTE + (PORT dataa (2546:2546:2546) (2638:2638:2638)) + (PORT datab (1188:1188:1188) (1214:1214:1214)) + (PORT datac (634:634:634) (665:665:665)) + (PORT datad (833:833:833) (902:902:902)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1588:1588:1588) (1640:1640:1640)) + (PORT datab (213:213:213) (257:257:257)) + (PORT datac (193:193:193) (227:227:227)) + (PORT datad (1163:1163:1163) (1227:1227:1227)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~9) + (DELAY + (ABSOLUTE + (PORT dataa (230:230:230) (277:277:277)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (832:832:832) (840:840:840)) + (PORT datad (632:632:632) (692:692:692)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[1\]) + (DELAY + (ABSOLUTE + (PORT dataa (617:617:617) (651:651:651)) + (PORT datac (927:927:927) (948:948:948)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1526:1526:1526) (1546:1546:1546)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1573:1573:1573) (1552:1552:1552)) + (PORT ena (1991:1991:1991) (1983:1983:1983)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_apin_mux\~0) + (DELAY + (ABSOLUTE + (PORT dataa (214:214:214) (265:265:265)) + (PORT datab (219:219:219) (257:257:257)) + (PORT datac (209:209:209) (248:248:248)) + (PORT datad (1166:1166:1166) (1243:1243:1243)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1875:1875:1875) (1932:1932:1932)) + (PORT datab (1847:1847:1847) (1929:1929:1929)) + (PORT datac (194:194:194) (227:227:227)) + (PORT datad (1220:1220:1220) (1273:1273:1273)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1899:1899:1899) (2034:2034:2034)) + (PORT datac (1755:1755:1755) (1880:1880:1880)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_40\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1836:1836:1836) (1914:1914:1914)) + (PORT datab (393:393:393) (464:464:464)) + (PORT datac (1281:1281:1281) (1295:1295:1295)) + (PORT datad (197:197:197) (232:232:232)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~21) + (DELAY + (ABSOLUTE + (PORT dataa (1141:1141:1141) (1193:1193:1193)) + (PORT datab (1533:1533:1533) (1612:1612:1612)) + (PORT datac (1293:1293:1293) (1315:1315:1315)) + (PORT datad (1125:1125:1125) (1163:1163:1163)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (1921:1921:1921) (2032:2032:2032)) + (PORT datab (1238:1238:1238) (1320:1320:1320)) + (PORT datac (193:193:193) (226:226:226)) + (PORT datad (1989:1989:1989) (2064:2064:2064)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (1752:1752:1752) (1846:1846:1846)) + (PORT datab (234:234:234) (277:277:277)) + (PORT datac (1577:1577:1577) (1617:1617:1617)) + (PORT datad (1811:1811:1811) (1943:1943:1943)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (1627:1627:1627) (1722:1722:1722)) + (PORT datac (815:815:815) (866:866:866)) + (PORT datad (1467:1467:1467) (1547:1547:1547)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[0\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (209:209:209) (257:257:257)) + (PORT datab (1453:1453:1453) (1476:1476:1476)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (1294:1294:1294) (1384:1384:1384)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_63) + (DELAY + (ABSOLUTE + (PORT datab (902:902:902) (946:946:946)) + (PORT datac (1148:1148:1148) (1185:1185:1185)) + (PORT datad (799:799:799) (805:805:805)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1231:1231:1231) (1237:1237:1237)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~49) + (DELAY + (ABSOLUTE + (PORT dataa (1939:1939:1939) (1993:1993:1993)) + (PORT datab (1250:1250:1250) (1300:1300:1300)) + (PORT datac (919:919:919) (936:936:936)) + (PORT datad (1080:1080:1080) (1156:1156:1156)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~2) + (DELAY + (ABSOLUTE + (PORT datac (848:848:848) (880:880:880)) + (PORT datad (647:647:647) (704:704:704)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~50) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (266:266:266)) + (PORT datab (1271:1271:1271) (1337:1337:1337)) + (PORT datac (172:172:172) (206:206:206)) + (PORT datad (580:580:580) (596:596:596)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (945:945:945) (986:986:986)) + (PORT datab (1764:1764:1764) (1805:1805:1805)) + (PORT datac (678:678:678) (736:736:736)) + (PORT datad (904:904:904) (937:937:937)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_oe\~1) + (DELAY + (ABSOLUTE + (PORT dataa (229:229:229) (277:277:277)) + (PORT datab (240:240:240) (279:279:279)) + (PORT datac (637:637:637) (654:654:654)) + (PORT datad (1224:1224:1224) (1274:1274:1274)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~13) + (DELAY + (ABSOLUTE + (PORT dataa (891:891:891) (908:908:908)) + (PORT datab (1229:1229:1229) (1316:1316:1316)) + (PORT datac (838:838:838) (873:873:873)) + (PORT datad (1223:1223:1223) (1295:1295:1295)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~12) + (DELAY + (ABSOLUTE + (PORT datab (859:859:859) (880:880:880)) + (PORT datac (576:576:576) (592:592:592)) + (PORT datad (556:556:556) (557:557:557)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1934:1934:1934) (1998:1998:1998)) + (PORT datab (1408:1408:1408) (1411:1411:1411)) + (PORT datac (577:577:577) (613:613:613)) + (PORT datad (1428:1428:1428) (1538:1538:1538)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_alu\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1367:1367:1367) (1430:1430:1430)) + (PORT datab (1228:1228:1228) (1316:1316:1316)) + (PORT datac (983:983:983) (1020:1020:1020)) + (PORT datad (885:885:885) (896:896:896)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1483:1483:1483) (1502:1502:1502)) + (PORT datab (208:208:208) (250:250:250)) + (PORT datac (344:344:344) (376:376:376)) + (PORT datad (203:203:203) (231:231:231)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (310:310:310)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -16490,12 +12034,1382 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~42) + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~5) (DELAY (ABSOLUTE - (PORT dataa (423:423:423) (485:485:485)) - (PORT datab (1600:1600:1600) (1653:1653:1653)) - (PORT datad (1181:1181:1181) (1221:1221:1221)) + (PORT dataa (1132:1132:1132) (1165:1165:1165)) + (PORT datab (227:227:227) (266:266:266)) + (PORT datac (1096:1096:1096) (1117:1117:1117)) + (PORT datad (1197:1197:1197) (1216:1216:1216)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1169:1169:1169) (1218:1218:1218)) + (PORT datab (220:220:220) (259:259:259)) + (PORT datac (1220:1220:1220) (1304:1304:1304)) + (PORT datad (618:618:618) (661:661:661)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1047:1047:1047) (1090:1090:1090)) + (PORT datab (651:651:651) (671:671:671)) + (PORT datac (831:831:831) (835:835:835)) + (PORT datad (182:182:182) (212:212:212)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~10) + (DELAY + (ABSOLUTE + (PORT dataa (231:231:231) (279:279:279)) + (PORT datab (1126:1126:1126) (1204:1204:1204)) + (PORT datac (1875:1875:1875) (1956:1956:1956)) + (PORT datad (1434:1434:1434) (1505:1505:1505)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_1d\~9) + (DELAY + (ABSOLUTE + (PORT datab (1832:1832:1832) (1926:1926:1926)) + (PORT datac (2081:2081:2081) (2255:2255:2255)) + (PORT datad (866:866:866) (901:901:901)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~9) + (DELAY + (ABSOLUTE + (PORT dataa (2210:2210:2210) (2368:2368:2368)) + (PORT datab (971:971:971) (1073:1073:1073)) + (PORT datac (193:193:193) (226:226:226)) + (PORT datad (1305:1305:1305) (1307:1307:1307)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (974:974:974) (1058:1058:1058)) + (PORT datab (845:845:845) (896:896:896)) + (PORT datad (345:345:345) (371:371:371)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~7) + (DELAY + (ABSOLUTE + (PORT dataa (392:392:392) (436:436:436)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (558:558:558) (564:564:564)) + (PORT datad (180:180:180) (209:209:209)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1101:1101:1101) (1193:1193:1193)) + (PORT datab (1600:1600:1600) (1725:1725:1725)) + (PORT datac (583:583:583) (625:625:625)) + (PORT datad (190:190:190) (222:222:222)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (2313:2313:2313) (2362:2362:2362)) + (PORT datab (873:873:873) (920:920:920)) + (PORT datac (1997:1997:1997) (2080:2080:2080)) + (PORT datad (2019:2019:2019) (2099:2099:2099)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1584:1584:1584) (1660:1660:1660)) + (PORT datab (1349:1349:1349) (1417:1417:1417)) + (PORT datac (1996:1996:1996) (2081:2081:2081)) + (PORT datad (1237:1237:1237) (1277:1277:1277)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~3) + (DELAY + (ABSOLUTE + (PORT dataa (899:899:899) (943:943:943)) + (PORT datab (206:206:206) (248:248:248)) + (PORT datac (171:171:171) (205:205:205)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (988:988:988) (1017:1017:1017)) + (PORT datab (688:688:688) (721:721:721)) + (PORT datac (849:849:849) (866:866:866)) + (PORT datad (891:891:891) (908:908:908)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (627:627:627) (692:692:692)) + (PORT datab (1851:1851:1851) (1861:1861:1861)) + (PORT datac (324:324:324) (346:346:346)) + (PORT datad (616:616:616) (643:643:643)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (570:570:570) (606:606:606)) + (PORT datab (1463:1463:1463) (1579:1579:1579)) + (PORT datac (578:578:578) (615:615:615)) + (PORT datad (1326:1326:1326) (1365:1365:1365)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla30npla13M4T3_5) + (DELAY + (ABSOLUTE + (PORT dataa (1308:1308:1308) (1396:1396:1396)) + (PORT datab (2420:2420:2420) (2553:2553:2553)) + (PORT datac (1094:1094:1094) (1118:1118:1118)) + (PORT datad (1195:1195:1195) (1217:1217:1217)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (948:948:948) (992:992:992)) + (PORT datab (957:957:957) (994:994:994)) + (PORT datac (1610:1610:1610) (1647:1647:1647)) + (PORT datad (1133:1133:1133) (1157:1157:1157)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (1188:1188:1188) (1197:1197:1197)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (1467:1467:1467) (1527:1527:1527)) + (PORT datad (927:927:927) (965:965:965)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (958:958:958) (1050:1050:1050)) + (PORT datab (1498:1498:1498) (1564:1564:1564)) + (PORT datac (1217:1217:1217) (1285:1285:1285)) + (PORT datad (1171:1171:1171) (1216:1216:1216)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (862:862:862) (897:897:897)) + (PORT datab (1733:1733:1733) (1770:1770:1770)) + (PORT datac (173:173:173) (206:206:206)) + (PORT datad (1512:1512:1512) (1602:1602:1602)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (242:242:242)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (194:194:194) (226:226:226)) + (PORT datad (610:610:610) (650:650:650)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (229:229:229) (276:276:276)) + (PORT datab (963:963:963) (1008:1008:1008)) + (PORT datac (624:624:624) (685:685:685)) + (PORT datad (1510:1510:1510) (1601:1601:1601)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (1678:1678:1678) (1717:1717:1717)) + (PORT datab (1179:1179:1179) (1219:1219:1219)) + (PORT datac (838:838:838) (872:872:872)) + (PORT datad (819:819:819) (842:842:842)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (241:241:241)) + (PORT datab (637:637:637) (694:694:694)) + (PORT datac (569:569:569) (590:590:590)) + (PORT datad (352:352:352) (382:382:382)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (2032:2032:2032) (2117:2117:2117)) + (PORT datab (1122:1122:1122) (1190:1190:1190)) + (PORT datac (2283:2283:2283) (2323:2323:2323)) + (PORT datad (1325:1325:1325) (1378:1378:1378)) + (IOPATH dataa combout (301:301:301) (307:307:307)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (897:897:897) (941:941:941)) + (PORT datab (425:425:425) (457:457:457)) + (PORT datac (839:839:839) (906:906:906)) + (PORT datad (194:194:194) (220:220:220)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (246:246:246)) + (PORT datab (207:207:207) (249:249:249)) + (PORT datac (585:585:585) (610:610:610)) + (PORT datad (194:194:194) (219:219:219)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (1483:1483:1483) (1501:1501:1501)) + (PORT datab (227:227:227) (266:266:266)) + (PORT datac (671:671:671) (719:719:719)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (964:964:964) (989:989:989)) + (PORT datab (212:212:212) (257:257:257)) + (PORT datad (888:888:888) (910:910:910)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (632:632:632) (645:645:645)) + (PORT datab (1105:1105:1105) (1105:1105:1105)) + (PORT datac (853:853:853) (869:869:869)) + (PORT datad (1157:1157:1157) (1187:1187:1187)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[0\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (412:412:412) (444:444:444)) + (PORT datab (391:391:391) (432:432:432)) + (PORT datac (178:178:178) (216:216:216)) + (PORT datad (171:171:171) (196:196:196)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal2\~2) + (DELAY + (ABSOLUTE + (PORT dataa (789:789:789) (894:894:894)) + (PORT datab (1922:1922:1922) (2016:2016:2016)) + (PORT datac (1273:1273:1273) (1346:1346:1346)) + (PORT datad (865:865:865) (888:888:888)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal1\~6) + (DELAY + (ABSOLUTE + (PORT dataa (370:370:370) (421:421:421)) + (PORT datab (1311:1311:1311) (1402:1402:1402)) + (PORT datac (829:829:829) (882:882:882)) + (PORT datad (357:357:357) (382:382:382)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|bank_exx\~2) + (DELAY + (ABSOLUTE + (PORT dataa (883:883:883) (915:915:915)) + (PORT datab (1481:1481:1481) (1573:1573:1573)) + (PORT datad (1200:1200:1200) (1275:1275:1275)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_control_\|bank_exx) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1567:1567:1567) (1549:1549:1549)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|bank_hl_de1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (948:948:948) (984:984:984)) + (PORT datab (619:619:619) (652:652:652)) + (PORT datad (276:276:276) (359:359:359)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_control_\|bank_hl_de1) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1567:1567:1567) (1549:1549:1549)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (627:627:627) (662:662:662)) + (PORT datab (741:741:741) (823:823:823)) + (PORT datac (1191:1191:1191) (1206:1206:1206)) + (PORT datad (1607:1607:1607) (1626:1626:1626)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (932:932:932) (967:967:967)) + (PORT datac (596:596:596) (622:622:622)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (852:852:852) (872:872:872)) + (PORT datab (588:588:588) (598:598:598)) + (PORT datac (871:871:871) (881:881:881)) + (PORT datad (183:183:183) (213:213:213)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (209:209:209) (256:256:256)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (820:820:820) (826:826:826)) + (PORT datad (931:931:931) (1009:1009:1009)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (951:951:951) (1014:1014:1014)) + (PORT datab (1267:1267:1267) (1328:1328:1328)) + (PORT datac (1708:1708:1708) (1771:1771:1771)) + (PORT datad (623:623:623) (637:637:637)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~45) + (DELAY + (ABSOLUTE + (PORT dataa (569:569:569) (606:606:606)) + (PORT datab (612:612:612) (649:649:649)) + (PORT datac (2087:2087:2087) (2253:2253:2253)) + (PORT datad (1784:1784:1784) (1865:1865:1865)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~2) + (DELAY + (ABSOLUTE + (PORT dataa (229:229:229) (275:275:275)) + (PORT datab (1702:1702:1702) (1722:1722:1722)) + (PORT datac (1037:1037:1037) (1088:1088:1088)) + (PORT datad (1279:1279:1279) (1348:1348:1348)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~3) + (DELAY + (ABSOLUTE + (PORT dataa (238:238:238) (287:287:287)) + (PORT datab (1179:1179:1179) (1189:1189:1189)) + (PORT datac (196:196:196) (239:239:239)) + (PORT datad (1523:1523:1523) (1592:1592:1592)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (633:633:633) (679:679:679)) + (PORT datab (220:220:220) (258:258:258)) + (PORT datac (200:200:200) (235:235:235)) + (PORT datad (804:804:804) (872:872:872)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (641:641:641) (676:676:676)) + (PORT datab (1421:1421:1421) (1501:1501:1501)) + (PORT datac (1162:1162:1162) (1195:1195:1195)) + (PORT datad (927:927:927) (965:965:965)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (1065:1065:1065) (1131:1131:1131)) + (PORT datab (688:688:688) (752:752:752)) + (PORT datac (643:643:643) (676:676:676)) + (PORT datad (1563:1563:1563) (1600:1600:1600)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1160:1160:1160) (1177:1177:1177)) + (PORT datab (923:923:923) (945:945:945)) + (PORT datac (820:820:820) (828:828:828)) + (PORT datad (837:837:837) (844:844:844)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~34) + (DELAY + (ABSOLUTE + (PORT datab (337:337:337) (367:367:367)) + (PORT datac (179:179:179) (216:216:216)) + (PORT datad (919:919:919) (988:988:988)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[0\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (579:579:579) (597:597:597)) + (PORT datac (763:763:763) (765:765:765)) + (PORT datad (318:318:318) (336:336:336)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (845:845:845) (901:901:901)) + (PORT datab (666:666:666) (696:696:696)) + (PORT datac (939:939:939) (971:971:971)) + (PORT datad (1281:1281:1281) (1352:1352:1352)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (1065:1065:1065) (1134:1134:1134)) + (PORT datab (1262:1262:1262) (1330:1330:1330)) + (PORT datac (922:922:922) (973:973:973)) + (PORT datad (942:942:942) (1006:1006:1006)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (608:608:608) (652:652:652)) + (PORT datab (1334:1334:1334) (1345:1345:1345)) + (PORT datac (922:922:922) (975:975:975)) + (PORT datad (172:172:172) (198:198:198)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (906:906:906) (934:934:934)) + (PORT datab (1264:1264:1264) (1330:1330:1330)) + (PORT datac (1581:1581:1581) (1628:1628:1628)) + (PORT datad (665:665:665) (713:713:713)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (1852:1852:1852) (1972:1972:1972)) + (PORT datab (1783:1783:1783) (1887:1887:1887)) + (PORT datac (186:186:186) (226:226:226)) + (PORT datad (1166:1166:1166) (1230:1230:1230)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1073:1073:1073) (1074:1074:1074)) + (PORT datab (626:626:626) (653:653:653)) + (PORT datac (1027:1027:1027) (1044:1044:1044)) + (PORT datad (1119:1119:1119) (1146:1146:1146)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (371:371:371) (392:392:392)) + (PORT datab (198:198:198) (236:236:236)) + (PORT datac (178:178:178) (213:213:213)) + (PORT datad (1663:1663:1663) (1726:1726:1726)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (215:215:215) (265:265:265)) + (PORT datab (1080:1080:1080) (1127:1127:1127)) + (PORT datac (867:867:867) (890:890:890)) + (PORT datad (1433:1433:1433) (1461:1461:1461)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (989:989:989) (1067:1067:1067)) + (PORT datab (1063:1063:1063) (1078:1078:1078)) + (PORT datac (1678:1678:1678) (1763:1763:1763)) + (PORT datad (828:828:828) (852:852:852)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (710:710:710) (785:785:785)) + (PORT datab (420:420:420) (490:490:490)) + (PORT datac (628:628:628) (694:694:694)) + (PORT datad (235:235:235) (303:303:303)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (681:681:681) (756:756:756)) + (PORT datab (1699:1699:1699) (1761:1761:1761)) + (PORT datac (347:347:347) (381:381:381)) + (PORT datad (1611:1611:1611) (1667:1667:1667)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (699:699:699) (774:774:774)) + (PORT datab (1189:1189:1189) (1284:1284:1284)) + (PORT datac (712:712:712) (808:808:808)) + (PORT datad (1178:1178:1178) (1275:1275:1275)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (741:741:741) (843:843:843)) + (PORT datab (1182:1182:1182) (1192:1192:1192)) + (PORT datac (1157:1157:1157) (1253:1253:1253)) + (PORT datad (1371:1371:1371) (1436:1436:1436)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (918:918:918) (998:998:998)) + (PORT datab (198:198:198) (238:238:238)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (1145:1145:1145) (1175:1175:1175)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (740:740:740) (806:806:806)) + (PORT datab (638:638:638) (650:650:650)) + (PORT datac (806:806:806) (818:818:818)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel\[1\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (577:577:577) (597:597:597)) + (PORT datab (369:369:369) (392:392:392)) + (PORT datac (859:859:859) (861:861:861)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_de2\~5) + (DELAY + (ABSOLUTE + (PORT dataa (480:480:480) (578:578:578)) + (PORT datab (494:494:494) (583:583:583)) + (PORT datac (840:840:840) (864:864:864)) + (PORT datad (915:915:915) (945:945:945)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_de2\~6) + (DELAY + (ABSOLUTE + (PORT dataa (577:577:577) (593:593:593)) + (PORT datab (341:341:341) (370:370:370)) + (PORT datac (766:766:766) (769:769:769)) + (PORT datad (196:196:196) (221:221:221)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_de\~0) + (DELAY + (ABSOLUTE + (PORT dataa (250:250:250) (340:340:340)) + (PORT datab (299:299:299) (394:394:394)) + (PORT datac (1077:1077:1077) (1071:1071:1071)) + (PORT datad (192:192:192) (226:226:226)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_50) + (DELAY + (ABSOLUTE + (PORT dataa (721:721:721) (783:783:783)) + (PORT datac (808:808:808) (854:854:854)) + (PORT datad (615:615:615) (659:659:659)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|bank_hl_de2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (950:950:950) (985:985:985)) + (PORT datab (614:614:614) (650:650:650)) + (PORT datad (276:276:276) (359:359:359)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_control_\|bank_hl_de2) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1567:1567:1567) (1549:1549:1549)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_de2\~4) + (DELAY + (ABSOLUTE + (PORT dataa (250:250:250) (341:341:341)) + (PORT datab (302:302:302) (397:397:397)) + (PORT datac (1073:1073:1073) (1071:1071:1071)) + (PORT datad (194:194:194) (229:229:229)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_46) + (DELAY + (ABSOLUTE + (PORT dataa (724:724:724) (786:786:786)) + (PORT datac (810:810:810) (853:853:853)) + (PORT datad (645:645:645) (684:684:684)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_47) + (DELAY + (ABSOLUTE + (PORT dataa (724:724:724) (783:783:783)) + (PORT datac (810:810:810) (854:854:854)) + (PORT datad (645:645:645) (685:685:685)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1549:1549:1549)) + (PORT asdata (1547:1547:1547) (1577:1577:1577)) + (PORT ena (974:974:974) (969:969:969)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_51) + (DELAY + (ABSOLUTE + (PORT dataa (724:724:724) (787:787:787)) + (PORT datac (810:810:810) (855:855:855)) + (PORT datad (614:614:614) (660:660:660)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1549:1549:1549)) + (PORT asdata (1547:1547:1547) (1574:1574:1574)) + (PORT ena (975:975:975) (970:970:970)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (408:408:408) (451:451:451)) + (PORT datab (440:440:440) (472:472:472)) + (PORT datad (215:215:215) (284:284:284)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_hl\~0) + (DELAY + (ABSOLUTE + (PORT dataa (249:249:249) (339:339:339)) + (PORT datab (300:300:300) (394:394:394)) + (PORT datac (1073:1073:1073) (1068:1068:1068)) + (PORT datad (194:194:194) (228:228:228)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_59) + (DELAY + (ABSOLUTE + (PORT dataa (928:928:928) (980:980:980)) + (PORT datab (648:648:648) (704:704:704)) + (PORT datad (595:595:595) (638:638:638)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT asdata (882:882:882) (892:892:892)) + (PORT ena (981:981:981) (980:980:980)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_hl2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (250:250:250) (339:339:339)) + (PORT datab (302:302:302) (394:394:394)) + (PORT datac (1077:1077:1077) (1074:1074:1074)) + (PORT datad (193:193:193) (226:226:226)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_54) + (DELAY + (ABSOLUTE + (PORT dataa (927:927:927) (974:974:974)) + (PORT datab (1199:1199:1199) (1242:1242:1242)) + (PORT datad (642:642:642) (684:684:684)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_55) + (DELAY + (ABSOLUTE + (PORT dataa (926:926:926) (980:980:980)) + (PORT datab (1196:1196:1196) (1244:1244:1244)) + (PORT datad (639:639:639) (683:683:683)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT asdata (881:881:881) (892:892:892)) + (PORT ena (811:811:811) (804:804:804)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_58) + (DELAY + (ABSOLUTE + (PORT dataa (925:925:925) (980:980:980)) + (PORT datac (617:617:617) (671:671:671)) + (PORT datad (595:595:595) (637:637:637)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (242:242:242) (329:329:329)) + (PORT datab (253:253:253) (303:303:303)) + (PORT datad (228:228:228) (265:265:265)) (IOPATH dataa combout (304:304:304) (307:307:307)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -16505,75 +13419,957 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~46) + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_70\~2) (DELAY (ABSOLUTE - (PORT dataa (603:603:603) (634:634:634)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (170:170:170) (203:203:203)) - (PORT datad (787:787:787) (785:785:785)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT datab (1169:1169:1169) (1216:1216:1216)) + (PORT datac (968:968:968) (1025:1025:1025)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~47) + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_38\~0) (DELAY (ABSOLUTE - (PORT dataa (623:623:623) (653:653:653)) - (PORT datab (336:336:336) (368:368:368)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (626:626:626) (642:642:642)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (921:921:921) (988:988:988)) - (PORT datab (218:218:218) (257:257:257)) - (PORT datac (618:618:618) (661:661:661)) - (PORT datad (787:787:787) (791:791:791)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT dataa (1015:1015:1015) (1091:1091:1091)) + (PORT datab (772:772:772) (829:829:829)) + (PORT datac (627:627:627) (674:674:674)) + (PORT datad (945:945:945) (977:977:977)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_71\~2) + (DELAY + (ABSOLUTE + (PORT datab (1168:1168:1168) (1211:1211:1211)) + (PORT datac (961:961:961) (1019:1019:1019)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_43\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1022:1022:1022) (1103:1103:1103)) + (PORT datab (763:763:763) (823:823:823)) + (PORT datac (608:608:608) (659:659:659)) + (PORT datad (940:940:940) (975:975:975)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT asdata (1267:1267:1267) (1311:1311:1311)) + (PORT ena (1220:1220:1220) (1212:1212:1212)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_39\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1022:1022:1022) (1102:1102:1102)) + (PORT datab (768:768:768) (831:831:831)) + (PORT datac (608:608:608) (661:661:661)) + (PORT datad (938:938:938) (975:975:975)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT asdata (1266:1266:1266) (1308:1308:1308)) + (PORT ena (1200:1200:1200) (1188:1188:1188)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_42\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1019:1019:1019) (1100:1100:1100)) + (PORT datab (764:764:764) (828:828:828)) + (PORT datac (631:631:631) (679:679:679)) + (PORT datad (939:939:939) (973:973:973)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (865:865:865) (934:934:934)) + (PORT datab (242:242:242) (325:325:325)) + (PORT datad (657:657:657) (720:720:720)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~15) + (DELAY + (ABSOLUTE + (PORT dataa (210:210:210) (256:256:256)) + (PORT datab (655:655:655) (678:678:678)) + (PORT datac (1025:1025:1025) (1067:1067:1067)) + (PORT datad (181:181:181) (210:210:210)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1118:1118:1118) (1130:1130:1130)) + (PORT datab (1452:1452:1452) (1476:1476:1476)) + (PORT datac (350:350:350) (377:377:377)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_83) + (DELAY + (ABSOLUTE + (PORT dataa (981:981:981) (1022:1022:1022)) + (PORT datac (1151:1151:1151) (1189:1189:1189)) + (PORT datad (876:876:876) (909:909:909)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1535:1535:1535)) + (PORT asdata (1552:1552:1552) (1574:1574:1574)) + (PORT ena (1274:1274:1274) (1265:1265:1265)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_82) + (DELAY + (ABSOLUTE + (PORT dataa (980:980:980) (1021:1021:1021)) + (PORT datac (1147:1147:1147) (1188:1188:1188)) + (PORT datad (872:872:872) (910:910:910)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~37) + (DELAY + (ABSOLUTE + (PORT datab (629:629:629) (651:651:651)) + (PORT datad (929:929:929) (952:952:952)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_66\~0) + (DELAY + (ABSOLUTE + (PORT dataa (666:666:666) (715:715:715)) + (PORT datab (961:961:961) (1016:1016:1016)) + (PORT datac (925:925:925) (952:952:952)) + (PORT datad (729:729:729) (785:785:785)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_iy\~2) + (DELAY + (ABSOLUTE + (PORT dataa (476:476:476) (576:576:576)) + (PORT datab (504:504:504) (584:584:584)) + (PORT datac (843:843:843) (866:866:866)) + (PORT datad (916:916:916) (947:947:947)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_71) + (DELAY + (ABSOLUTE + (PORT datab (1080:1080:1080) (1098:1098:1098)) + (PORT datac (821:821:821) (861:861:861)) + (PORT datad (1158:1158:1158) (1197:1197:1197)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT asdata (1278:1278:1278) (1319:1319:1319)) + (PORT ena (790:790:790) (782:782:782)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_67\~0) + (DELAY + (ABSOLUTE + (PORT dataa (640:640:640) (696:696:696)) + (PORT datab (752:752:752) (818:818:818)) + (PORT datac (927:927:927) (953:953:953)) + (PORT datad (933:933:933) (979:979:979)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT asdata (1277:1277:1277) (1319:1319:1319)) + (PORT ena (1288:1288:1288) (1306:1306:1306)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_70) + (DELAY + (ABSOLUTE + (PORT datab (1080:1080:1080) (1097:1097:1097)) + (PORT datac (821:821:821) (860:860:860)) + (PORT datad (1158:1158:1158) (1197:1197:1197)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (663:663:663) (742:742:742)) + (PORT datab (240:240:240) (322:322:322)) + (PORT datad (231:231:231) (269:269:269)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla37pla28M2T3_4) + (DELAY + (ABSOLUTE + (PORT dataa (1235:1235:1235) (1299:1299:1299)) + (PORT datab (2094:2094:2094) (2218:2218:2218)) + (PORT datac (1670:1670:1670) (1752:1752:1752)) + (PORT datad (666:666:666) (714:714:714)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1108:1108:1108) (1132:1132:1132)) + (PORT datab (1982:1982:1982) (2008:2008:2008)) + (PORT datac (1747:1747:1747) (1823:1823:1823)) + (PORT datad (568:568:568) (585:585:585)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1036:1036:1036) (1106:1106:1106)) + (PORT datac (560:560:560) (564:564:564)) + (PORT datad (316:316:316) (335:335:335)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_lo\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1071:1071:1071) (1086:1086:1086)) + (PORT datab (1166:1166:1166) (1189:1189:1189)) + (PORT datac (904:904:904) (933:933:933)) + (PORT datad (180:180:180) (210:210:210)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (194:194:194) (219:219:219)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~4) + (DELAY + (ABSOLUTE + (PORT dataa (2119:2119:2119) (2290:2290:2290)) + (PORT datab (993:993:993) (1113:1113:1113)) + (PORT datac (1800:1800:1800) (1891:1891:1891)) + (PORT datad (868:868:868) (902:902:902)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~5) + (DELAY + (ABSOLUTE + (PORT dataa (934:934:934) (978:978:978)) + (PORT datab (383:383:383) (410:410:410)) + (PORT datac (619:619:619) (675:675:675)) + (PORT datad (632:632:632) (646:646:646)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_use_sp\~6) + (DELAY + (ABSOLUTE + (PORT dataa (366:366:366) (386:386:386)) + (PORT datab (829:829:829) (911:911:911)) + (PORT datac (833:833:833) (856:856:856)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_79\~0) + (DELAY + (ABSOLUTE + (PORT dataa (894:894:894) (914:914:914)) + (PORT datab (768:768:768) (829:829:829)) + (PORT datac (608:608:608) (661:661:661)) + (PORT datad (938:938:938) (974:974:974)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1438:1438:1438) (1476:1476:1476)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_1d\~5) + (DELAY + (ABSOLUTE + (PORT dataa (877:877:877) (897:897:897)) + (PORT datab (741:741:741) (827:827:827)) + (PORT datac (1193:1193:1193) (1210:1210:1210)) + (PORT datad (196:196:196) (221:221:221)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_im_we) + (DELAY + (ABSOLUTE + (PORT dataa (2036:2036:2036) (2132:2132:2132)) + (PORT datab (1850:1850:1850) (1987:1987:1987)) + (PORT datac (1886:1886:1886) (1987:1987:1987)) + (PORT datad (1685:1685:1685) (1763:1763:1763)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_1d\~6) + (DELAY + (ABSOLUTE + (PORT dataa (626:626:626) (665:665:665)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (854:854:854) (889:889:889)) + (PORT datad (631:631:631) (666:666:666)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_1d\~7) + (DELAY + (ABSOLUTE + (PORT dataa (863:863:863) (899:899:899)) + (PORT datab (1394:1394:1394) (1389:1389:1389)) + (PORT datac (633:633:633) (693:693:693)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_ds\[2\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (827:827:827) (862:862:862)) + (PORT datab (1124:1124:1124) (1164:1164:1164)) + (PORT datac (655:655:655) (684:684:684)) + (PORT datad (1218:1218:1218) (1229:1229:1229)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[2\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (865:865:865) (888:888:888)) + (PORT datab (373:373:373) (407:407:407)) + (PORT datac (408:408:408) (450:450:450)) + (PORT datad (176:176:176) (201:201:201)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~11) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (263:263:263)) + (PORT datab (655:655:655) (675:675:675)) + (PORT datac (912:912:912) (927:927:927)) + (PORT datad (1988:1988:1988) (2062:2062:2062)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_in_hi\~12) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (254:254:254)) + (PORT datab (1505:1505:1505) (1589:1589:1589)) + (PORT datac (825:825:825) (846:846:846)) + (PORT datad (188:188:188) (219:219:219)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (1288:1288:1288) (1315:1315:1315)) + (PORT datab (1444:1444:1444) (1478:1478:1478)) + (PORT datac (1648:1648:1648) (1683:1683:1683)) + (PORT datad (364:364:364) (397:397:397)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (671:671:671) (717:717:717)) + (PORT datab (1159:1159:1159) (1190:1190:1190)) + (PORT datac (657:657:657) (723:723:723)) + (PORT datad (1115:1115:1115) (1128:1128:1128)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (1062:1062:1062) (1130:1130:1130)) + (PORT datab (952:952:952) (1010:1010:1010)) + (PORT datac (607:607:607) (626:626:626)) + (PORT datad (940:940:940) (1002:1002:1002)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (242:242:242)) + (PORT datab (679:679:679) (723:723:723)) + (PORT datac (174:174:174) (207:207:207)) + (PORT datad (602:602:602) (611:611:611)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~41) + (DELAY + (ABSOLUTE + (PORT dataa (350:350:350) (391:391:391)) + (PORT datab (1103:1103:1103) (1102:1102:1102)) + (PORT datac (874:874:874) (899:899:899)) + (PORT datad (592:592:592) (600:600:600)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo\[1\]\~43) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (656:656:656) (713:713:713)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (180:180:180) (207:207:207)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_68\~2) + (DELAY + (ABSOLUTE + (PORT datac (1873:1873:1873) (1943:1943:1943)) + (PORT datad (1780:1780:1780) (1858:1858:1858)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_64\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1195:1195:1195) (1243:1243:1243)) + (PORT datab (598:598:598) (625:625:625)) + (PORT datac (949:949:949) (998:998:998)) + (PORT datad (643:643:643) (669:669:669)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_76\~0) + (DELAY + (ABSOLUTE + (PORT dataa (961:961:961) (994:994:994)) + (PORT datab (750:750:750) (818:818:818)) + (PORT datac (852:852:852) (869:869:869)) + (PORT datad (650:650:650) (672:672:672)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_68) + (DELAY + (ABSOLUTE + (PORT datab (1052:1052:1052) (1073:1073:1073)) + (PORT datac (1876:1876:1876) (1945:1945:1945)) + (PORT datad (1783:1783:1783) (1860:1860:1860)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_40\~0) + (DELAY + (ABSOLUTE + (PORT dataa (688:688:688) (765:765:765)) + (PORT datab (1487:1487:1487) (1504:1504:1504)) + (PORT datac (880:880:880) (892:892:892)) + (PORT datad (618:618:618) (651:651:651)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_36\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1018:1018:1018) (1095:1095:1095)) + (PORT datab (770:770:770) (831:831:831)) + (PORT datac (925:925:925) (952:952:952)) + (PORT datad (651:651:651) (672:672:672)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~18) (DELAY (ABSOLUTE - (PORT dataa (1064:1064:1064) (1103:1103:1103)) - (PORT datab (836:836:836) (868:868:868)) - (PORT datac (218:218:218) (261:261:261)) + (PORT dataa (692:692:692) (732:732:732)) + (PORT datab (348:348:348) (382:382:382)) + (PORT datac (600:600:600) (629:629:629)) (IOPATH dataa combout (354:354:354) (349:349:349)) (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (243:243:243) (242:242:242)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_80) + (DELAY + (ABSOLUTE + (PORT datab (929:929:929) (971:971:971)) + (PORT datac (1103:1103:1103) (1141:1141:1141)) + (PORT datad (942:942:942) (978:978:978)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal21\~2) + (DELAY + (ABSOLUTE + (PORT dataa (232:232:232) (291:291:291)) + (PORT datab (883:883:883) (939:939:939)) + (PORT datad (1361:1361:1361) (1485:1485:1485)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|bank_af\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1181:1181:1181) (1223:1223:1223)) + (PORT datab (1462:1462:1462) (1481:1481:1481)) + (PORT datad (324:324:324) (335:335:335)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_control_\|bank_af) + (DELAY + (ABSOLUTE + (PORT clk (1513:1513:1513) (1527:1527:1527)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1557:1557:1557) (1538:1538:1538)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_af\~0) + (DELAY + (ABSOLUTE + (PORT dataa (889:889:889) (912:912:912)) + (PORT datab (968:968:968) (1010:1010:1010)) + (PORT datac (1317:1317:1317) (1480:1480:1480)) + (PORT datad (714:714:714) (774:774:774)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_af2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (891:891:891) (917:917:917)) + (PORT datab (967:967:967) (1015:1015:1015)) + (PORT datac (1318:1318:1318) (1484:1484:1484)) + (PORT datad (727:727:727) (784:784:784)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_28) + (DELAY + (ABSOLUTE + (PORT dataa (1908:1908:1908) (1979:1979:1979)) + (PORT datac (617:617:617) (658:658:658)) + (PORT datad (1772:1772:1772) (1850:1850:1850)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (673:673:673) (722:722:722)) + (PORT datab (585:585:585) (616:616:616)) + (PORT datac (604:604:604) (633:633:633)) + (PORT datad (399:399:399) (442:442:442)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~19) (DELAY (ABSOLUTE - (PORT dataa (649:649:649) (671:671:671)) - (PORT datab (834:834:834) (892:892:892)) - (PORT datac (174:174:174) (207:207:207)) - (PORT datad (874:874:874) (899:899:899)) + (PORT dataa (370:370:370) (402:402:402)) + (PORT datab (673:673:673) (707:707:707)) + (PORT datac (312:312:312) (333:333:333)) + (PORT datad (173:173:173) (199:199:199)) (IOPATH dataa combout (354:354:354) (349:349:349)) (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (243:243:243) (241:241:241)) @@ -16581,14 +14377,70 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_52) + (DELAY + (ABSOLUTE + (PORT dataa (1127:1127:1127) (1157:1157:1157)) + (PORT datac (1399:1399:1399) (1453:1453:1453)) + (PORT datad (822:822:822) (847:847:847)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_44) + (DELAY + (ABSOLUTE + (PORT dataa (1835:1835:1835) (1917:1917:1917)) + (PORT datac (1882:1882:1882) (1953:1953:1953)) + (PORT datad (1121:1121:1121) (1148:1148:1148)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_48) + (DELAY + (ABSOLUTE + (PORT dataa (1836:1836:1836) (1917:1917:1917)) + (PORT datac (1883:1883:1883) (1953:1953:1953)) + (PORT datad (1107:1107:1107) (1112:1112:1112)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_56) + (DELAY + (ABSOLUTE + (PORT dataa (1832:1832:1832) (1915:1915:1915)) + (PORT datac (1879:1879:1879) (1950:1950:1950)) + (PORT datad (1091:1091:1091) (1097:1097:1097)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~16) (DELAY (ABSOLUTE - (PORT dataa (221:221:221) (265:265:265)) - (PORT datab (220:220:220) (259:259:259)) - (PORT datac (194:194:194) (228:228:228)) + (PORT dataa (897:897:897) (939:939:939)) + (PORT datab (222:222:222) (261:261:261)) + (PORT datac (195:195:195) (229:229:229)) (PORT datad (196:196:196) (222:222:222)) (IOPATH dataa combout (354:354:354) (349:349:349)) (IOPATH datab combout (355:355:355) (349:349:349)) @@ -16602,10 +14454,10 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~20) (DELAY (ABSOLUTE - (PORT dataa (1547:1547:1547) (1564:1564:1564)) - (PORT datab (851:851:851) (910:910:910)) - (PORT datac (1130:1130:1130) (1151:1151:1151)) - (PORT datad (173:173:173) (198:198:198)) + (PORT dataa (1197:1197:1197) (1216:1216:1216)) + (PORT datab (198:198:198) (236:236:236)) + (PORT datac (565:565:565) (582:582:582)) + (PORT datad (1141:1141:1141) (1165:1165:1165)) (IOPATH dataa combout (354:354:354) (349:349:349)) (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (243:243:243) (241:241:241)) @@ -16615,368 +14467,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_73) + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_69\~2) (DELAY (ABSOLUTE - (PORT dataa (1308:1308:1308) (1399:1399:1399)) - (PORT datac (1141:1141:1141) (1164:1164:1164)) - (PORT datad (832:832:832) (866:866:866)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1308:1308:1308) (1303:1303:1303)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1537:1537:1537)) - (PORT asdata (1187:1187:1187) (1229:1229:1229)) - (PORT ena (990:990:990) (994:994:994)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1537:1537:1537)) - (PORT asdata (1186:1186:1186) (1227:1227:1227)) - (PORT ena (973:973:973) (964:964:964)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (460:460:460) (523:523:523)) - (PORT datab (492:492:492) (541:541:541)) - (PORT datad (216:216:216) (285:285:285)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (1950:1950:1950) (1996:1996:1996)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (937:937:937) (991:991:991)) - (PORT datab (1222:1222:1222) (1291:1291:1291)) - (PORT datad (879:879:879) (935:935:935)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1535:1535:1535) (1554:1554:1554)) - (PORT asdata (545:545:545) (579:579:579)) - (PORT ena (1461:1461:1461) (1468:1468:1468)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (1716:1716:1716) (1767:1767:1767)) - (PORT ena (1261:1261:1261) (1299:1299:1299)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1098:1098:1098) (1151:1151:1151)) - (PORT datab (648:648:648) (728:728:728)) - (PORT datad (845:845:845) (876:876:876)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1534:1534:1534)) - (PORT asdata (2219:2219:2219) (2260:2260:2260)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (851:851:851) (881:881:881)) - (PORT datab (1166:1166:1166) (1218:1218:1218)) - (PORT datad (240:240:240) (280:280:280)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (1976:1976:1976) (2020:2020:2020)) - (PORT ena (1193:1193:1193) (1176:1176:1176)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (1977:1977:1977) (2023:2023:2023)) - (PORT ena (1283:1283:1283) (1283:1283:1283)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (387:387:387) (466:466:466)) - (PORT datab (1593:1593:1593) (1643:1643:1643)) - (PORT datad (1180:1180:1180) (1216:1216:1216)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (1715:1715:1715) (1766:1766:1766)) - (PORT ena (1131:1131:1131) (1098:1098:1098)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1611:1611:1611) (1650:1650:1650)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (391:391:391) (433:433:433)) - (PORT datab (886:886:886) (923:923:923)) - (PORT datad (859:859:859) (925:925:925)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (241:241:241)) - (PORT datab (632:632:632) (649:649:649)) - (PORT datac (338:338:338) (358:358:358)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (2372:2372:2372) (2423:2423:2423)) - (PORT ena (1388:1388:1388) (1427:1427:1427)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (2371:2371:2371) (2423:2423:2423)) - (PORT ena (1400:1400:1400) (1413:1413:1413)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (926:926:926) (986:986:986)) - (PORT datab (911:911:911) (986:986:986)) - (PORT datad (216:216:216) (285:285:285)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (651:651:651) (672:672:672)) - (PORT datab (196:196:196) (235:235:235)) - (PORT datac (596:596:596) (613:613:613)) - (PORT datad (313:313:313) (323:323:323)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) + (PORT datac (1867:1867:1867) (1939:1939:1939)) + (PORT datad (1774:1774:1774) (1853:1853:1853)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -16984,803 +14479,28 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~21) + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_65\~0) (DELAY (ABSOLUTE - (PORT dataa (879:879:879) (944:944:944)) - (PORT datab (543:543:543) (563:563:563)) - (PORT datac (1049:1049:1049) (1102:1102:1102)) - (PORT datad (1297:1297:1297) (1338:1338:1338)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_60) - (DELAY - (ABSOLUTE - (PORT dataa (860:860:860) (911:911:911)) - (PORT datac (1138:1138:1138) (1159:1159:1159)) - (PORT datad (844:844:844) (869:869:869)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_61) - (DELAY - (ABSOLUTE - (PORT dataa (860:860:860) (909:909:909)) - (PORT datac (1140:1140:1140) (1164:1164:1164)) - (PORT datad (844:844:844) (871:871:871)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1535:1535:1535) (1554:1554:1554)) - (PORT asdata (1391:1391:1391) (1443:1443:1443)) - (PORT ena (935:935:935) (924:924:924)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sw_4d_hi\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1171:1171:1171) (1195:1195:1195)) - (PORT datab (835:835:835) (855:855:855)) - (PORT datac (1143:1143:1143) (1163:1163:1163)) - (PORT datad (844:844:844) (868:868:868)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (230:230:230) (276:276:276)) - (PORT datab (409:409:409) (450:450:450)) - (PORT datad (382:382:382) (419:419:419)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_72) - (DELAY - (ABSOLUTE - (PORT dataa (1308:1308:1308) (1398:1398:1398)) - (PORT datac (1141:1141:1141) (1165:1165:1165)) - (PORT datad (832:832:832) (866:866:866)) - (IOPATH dataa combout (341:341:341) (347:347:347)) + (PORT dataa (655:655:655) (687:687:687)) + (PORT datab (964:964:964) (1019:1019:1019)) + (PORT datac (926:926:926) (953:953:953)) + (PORT datad (730:730:730) (786:786:786)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (244:244:244) (331:331:331)) - (PORT datac (762:762:762) (815:815:815)) - (PORT datad (642:642:642) (666:666:666)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (239:239:239) (292:292:292)) - (PORT datab (235:235:235) (277:277:277)) - (PORT datac (1097:1097:1097) (1113:1113:1113)) - (PORT datad (212:212:212) (246:246:246)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|d1_out) - (DELAY - (ABSOLUTE - (PORT dataa (418:418:418) (508:508:508)) - (PORT datab (279:279:279) (364:364:364)) - (PORT datac (1332:1332:1332) (1337:1337:1337)) - (PORT datad (184:184:184) (216:216:216)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1554:1554:1554)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (842:842:842) (856:856:856)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (951:951:951) (975:975:975)) - (PORT ena (1388:1388:1388) (1427:1427:1427)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (951:951:951) (974:974:974)) - (PORT ena (1400:1400:1400) (1413:1413:1413)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (918:918:918) (978:978:978)) - (PORT datab (914:914:914) (989:989:989)) - (PORT datad (214:214:214) (283:283:283)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1537:1537:1537)) - (PORT asdata (1393:1393:1393) (1432:1432:1432)) - (PORT ena (990:990:990) (994:994:994)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1537:1537:1537)) - (PORT asdata (1390:1390:1390) (1429:1429:1429)) - (PORT ena (973:973:973) (964:964:964)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (462:462:462) (517:517:517)) - (PORT datab (496:496:496) (537:537:537)) - (PORT datad (217:217:217) (286:286:286)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (1278:1278:1278) (1308:1308:1308)) - (PORT ena (1283:1283:1283) (1283:1283:1283)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (1278:1278:1278) (1306:1306:1306)) - (PORT ena (1193:1193:1193) (1176:1176:1176)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (388:388:388) (458:458:458)) - (PORT datab (1599:1599:1599) (1646:1646:1646)) - (PORT datad (1181:1181:1181) (1215:1215:1215)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1534:1534:1534)) - (PORT asdata (1228:1228:1228) (1277:1277:1277)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (1058:1058:1058) (1070:1070:1070)) - (PORT datab (1167:1167:1167) (1216:1216:1216)) - (PORT datad (237:237:237) (277:277:277)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (810:810:810) (862:862:862)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1214:1214:1214) (1210:1210:1210)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (1259:1259:1259) (1290:1290:1290)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (244:244:244) (331:331:331)) - (PORT datab (243:243:243) (289:289:289)) - (PORT datad (875:875:875) (901:901:901)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT asdata (689:689:689) (709:709:709)) - (PORT ena (1404:1404:1404) (1382:1382:1382)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1474:1474:1474) (1488:1488:1488)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (1058:1058:1058) (1072:1072:1072)) - (PORT datab (1270:1270:1270) (1360:1360:1360)) - (PORT datad (216:216:216) (285:285:285)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (838:838:838) (872:872:872)) - (PORT datab (1030:1030:1030) (1072:1072:1072)) - (PORT datac (803:803:803) (856:856:856)) - (PORT datad (173:173:173) (197:197:197)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (969:969:969) (986:986:986)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[0\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (931:931:931) (986:986:986)) - (PORT datab (1221:1221:1221) (1292:1292:1292)) - (PORT datad (887:887:887) (945:945:945)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (380:380:380) (429:429:429)) - (PORT datab (829:829:829) (880:880:880)) - (PORT datac (170:170:170) (202:202:202)) - (PORT datad (558:558:558) (582:582:582)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (834:834:834) (864:864:864)) - (PORT datab (867:867:867) (903:903:903)) - (PORT datac (808:808:808) (862:862:862)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1554:1554:1554)) - (PORT asdata (881:881:881) (888:888:888)) - (PORT ena (940:940:940) (926:926:926)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (238:238:238) (288:288:288)) - (PORT datab (905:905:905) (941:941:941)) - (PORT datad (211:211:211) (245:245:245)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (237:237:237) (288:288:288)) - (PORT datac (214:214:214) (290:290:290)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1135:1135:1135) (1153:1153:1153)) - (PORT datab (827:827:827) (837:837:837)) - (PORT datac (199:199:199) (234:234:234)) - (PORT datad (171:171:171) (196:196:196)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[8\]) - (DELAY - (ABSOLUTE - (PORT dataa (688:688:688) (733:733:733)) - (PORT datac (799:799:799) (817:817:817)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[8\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1560:1560:1560)) - (PORT ena (2152:2152:2152) (2220:2220:2220)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|carry_borrow_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (422:422:422) (513:513:513)) - (PORT datab (280:280:280) (369:369:369)) - (PORT datac (1329:1329:1329) (1334:1334:1334)) - (PORT datad (189:189:189) (221:221:221)) - (IOPATH dataa combout (301:301:301) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|d0_out) - (DELAY - (ABSOLUTE - (PORT datac (248:248:248) (337:337:337)) - (PORT datad (324:324:324) (346:346:346)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (712:712:712) (756:756:756)) - (PORT datac (810:810:810) (842:842:842)) - (PORT datad (578:578:578) (586:586:586)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[9\]) - (DELAY - (ABSOLUTE - (PORT datab (355:355:355) (385:385:385)) - (PORT datac (880:880:880) (911:911:911)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|Q\[9\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (554:554:554) (561:561:561)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[9\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1560:1560:1560)) - (PORT ena (2096:2096:2096) (2133:2133:2133)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|d1_out) - (DELAY - (ABSOLUTE - (PORT dataa (268:268:268) (364:364:364)) - (PORT datab (279:279:279) (374:374:374)) - (PORT datac (1335:1335:1335) (1349:1349:1349)) - (PORT datad (325:325:325) (343:343:343)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (1106:1106:1106) (1145:1145:1145)) - (PORT ena (1388:1388:1388) (1427:1427:1427)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (1107:1107:1107) (1146:1146:1146)) - (PORT ena (1400:1400:1400) (1413:1413:1413)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (921:921:921) (980:980:980)) - (PORT datab (914:914:914) (982:982:982)) - (PORT datad (216:216:216) (283:283:283)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1534:1534:1534)) - (PORT asdata (1947:1947:1947) (2004:2004:2004)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (812:812:812) (827:827:827)) - (PORT datab (1168:1168:1168) (1216:1216:1216)) - (PORT datad (240:240:240) (281:281:281)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[2\]) (DELAY (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (1439:1439:1439) (1508:1508:1508)) - (PORT ena (1131:1131:1131) (1098:1098:1098)) + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT asdata (1533:1533:1533) (1561:1561:1561)) + (PORT ena (1229:1229:1229) (1240:1240:1240)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -17791,10 +14511,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[2\]\~feeder) + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_69) (DELAY (ABSOLUTE - (PORT datad (778:778:778) (850:850:850)) + (PORT datab (1052:1052:1052) (1072:1072:1072)) + (PORT datac (1869:1869:1869) (1942:1942:1942)) + (PORT datad (1777:1777:1777) (1856:1856:1856)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -17804,66 +14528,9 @@ (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[2\]) (DELAY (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (391:391:391) (433:433:433)) - (PORT datab (886:886:886) (923:923:923)) - (PORT datad (350:350:350) (406:406:406)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1005:1005:1005) (1055:1055:1055)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1193:1193:1193) (1176:1176:1176)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (1994:1994:1994) (2075:2075:2075)) - (PORT ena (1283:1283:1283) (1283:1283:1283)) + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT asdata (1536:1536:1536) (1566:1566:1566)) + (PORT ena (1168:1168:1168) (1147:1147:1147)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -17874,27 +14541,43 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~33) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~34) (DELAY (ABSOLUTE - (PORT dataa (568:568:568) (641:641:641)) - (PORT datab (1599:1599:1599) (1649:1649:1649)) - (PORT datad (1179:1179:1179) (1219:1219:1219)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (693:693:693) (725:725:725)) + (PORT datab (268:268:268) (323:323:323)) + (PORT datad (217:217:217) (285:285:285)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_77\~0) + (DELAY + (ABSOLUTE + (PORT dataa (655:655:655) (688:688:688)) + (PORT datab (773:773:773) (830:830:830)) + (PORT datac (856:856:856) (878:878:878)) + (PORT datad (945:945:945) (977:977:977)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[2\]) (DELAY (ABSOLUTE - (PORT clk (1535:1535:1535) (1554:1554:1554)) + (PORT clk (1520:1520:1520) (1533:1533:1533)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1461:1461:1461) (1468:1468:1468)) + (PORT ena (1503:1503:1503) (1497:1497:1497)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -17903,14 +14586,28 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_81) + (DELAY + (ABSOLUTE + (PORT datab (930:930:930) (973:973:973)) + (PORT datac (1105:1105:1105) (1142:1142:1142)) + (PORT datad (943:943:943) (979:979:979)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[2\]) (DELAY (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (1439:1439:1439) (1506:1506:1506)) - (PORT ena (1261:1261:1261) (1299:1299:1299)) + (PORT clk (1520:1520:1520) (1533:1533:1533)) + (PORT asdata (1702:1702:1702) (1705:1705:1705)) + (PORT ena (1227:1227:1227) (1249:1249:1249)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -17924,9 +14621,54 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~36) (DELAY (ABSOLUTE - (PORT dataa (1100:1100:1100) (1147:1147:1147)) - (PORT datab (678:678:678) (753:753:753)) - (PORT datad (849:849:849) (878:878:878)) + (PORT dataa (707:707:707) (780:780:780)) + (PORT datab (242:242:242) (322:322:322)) + (PORT datad (694:694:694) (744:744:744)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_29) + (DELAY + (ABSOLUTE + (PORT dataa (1921:1921:1921) (1993:1993:1993)) + (PORT datac (619:619:619) (662:662:662)) + (PORT datad (1786:1786:1786) (1864:1864:1864)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1533:1533:1533)) + (PORT asdata (1200:1200:1200) (1213:1213:1213)) + (PORT ena (1201:1201:1201) (1198:1198:1198)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (1201:1201:1201) (1222:1222:1222)) + (PORT datab (908:908:908) (935:935:935)) + (PORT datad (400:400:400) (437:437:437)) (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -17934,15 +14676,94 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_37\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1024:1024:1024) (1103:1103:1103)) + (PORT datab (758:758:758) (823:823:823)) + (PORT datac (925:925:925) (953:953:953)) + (PORT datad (628:628:628) (646:646:646)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (1353:1353:1353) (1408:1408:1408)) + (PORT ena (1225:1225:1225) (1236:1236:1236)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_41\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1023:1023:1023) (1104:1104:1104)) + (PORT datab (761:761:761) (825:825:825)) + (PORT datac (925:925:925) (955:955:955)) + (PORT datad (626:626:626) (647:647:647)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (1351:1351:1351) (1406:1406:1406)) + (PORT ena (1440:1440:1440) (1419:1419:1419)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (702:702:702) (764:764:764)) + (PORT datab (658:658:658) (677:677:677)) + (PORT datad (217:217:217) (286:286:286)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~37) (DELAY (ABSOLUTE - (PORT dataa (631:631:631) (653:653:653)) - (PORT datab (198:198:198) (236:236:236)) - (PORT datac (599:599:599) (617:617:617)) - (PORT datad (175:175:175) (201:201:201)) + (PORT dataa (602:602:602) (622:622:622)) + (PORT datab (642:642:642) (658:658:658)) + (PORT datac (618:618:618) (634:634:634)) + (PORT datad (998:998:998) (1038:1038:1038)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -17950,35 +14771,73 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_45) + (DELAY + (ABSOLUTE + (PORT dataa (1532:1532:1532) (1588:1588:1588)) + (PORT datab (2174:2174:2174) (2213:2213:2213)) + (PORT datad (1400:1400:1400) (1412:1412:1412)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (968:968:968) (992:992:992)) + (PORT ena (981:981:981) (980:980:980)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (563:563:563) (585:585:585)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_49) + (DELAY + (ABSOLUTE + (PORT dataa (1834:1834:1834) (1916:1916:1916)) + (PORT datac (1881:1881:1881) (1952:1952:1952)) + (PORT datad (1107:1107:1107) (1109:1109:1109)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[2\]) (DELAY (ABSOLUTE - (PORT clk (1523:1523:1523) (1537:1537:1537)) - (PORT asdata (2176:2176:2176) (2269:2269:2269)) - (PORT ena (973:973:973) (964:964:964)) + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1190:1190:1190) (1164:1164:1164)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1537:1537:1537)) - (PORT asdata (2177:2177:2177) (2273:2273:2273)) - (PORT ena (990:990:990) (994:994:994)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) + (HOLD d (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) ) ) @@ -17987,24 +14846,38 @@ (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~31) (DELAY (ABSOLUTE - (PORT dataa (461:461:461) (524:524:524)) - (PORT datab (243:243:243) (326:326:326)) - (PORT datad (454:454:454) (497:497:497)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT dataa (700:700:700) (735:735:735)) + (PORT datab (699:699:699) (719:719:719)) + (PORT datad (217:217:217) (286:286:286)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_33) + (DELAY + (ABSOLUTE + (PORT dataa (1526:1526:1526) (1579:1579:1579)) + (PORT datab (2177:2177:2177) (2222:2222:2222)) + (PORT datad (1364:1364:1364) (1385:1385:1385)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[2\]) (DELAY (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (2201:2201:2201) (2285:2285:2285)) - (PORT ena (794:794:794) (792:792:792)) + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (912:912:912) (926:926:926)) + (PORT ena (790:790:790) (782:782:782)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -18015,12 +14888,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[2\]\~17) + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[2\]\~12) (DELAY (ABSOLUTE - (PORT dataa (928:928:928) (990:990:990)) - (PORT datab (1220:1220:1220) (1290:1290:1290)) - (PORT datad (884:884:884) (941:941:941)) + (PORT dataa (1538:1538:1538) (1587:1587:1587)) + (PORT datab (2171:2171:2171) (2210:2210:2210)) + (PORT datad (1367:1367:1367) (1389:1389:1389)) (IOPATH dataa combout (300:300:300) (308:308:308)) (IOPATH datab combout (300:300:300) (310:310:310)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -18028,15 +14901,90 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_57) + (DELAY + (ABSOLUTE + (PORT dataa (1835:1835:1835) (1917:1917:1917)) + (PORT datac (1882:1882:1882) (1952:1952:1952)) + (PORT datad (1091:1091:1091) (1095:1095:1095)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1530:1530:1530)) + (PORT asdata (1220:1220:1220) (1225:1225:1225)) + (PORT ena (1240:1240:1240) (1223:1223:1223)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_53) + (DELAY + (ABSOLUTE + (PORT dataa (1127:1127:1127) (1157:1157:1157)) + (PORT datac (1398:1398:1398) (1452:1452:1452)) + (PORT datad (822:822:822) (846:846:846)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1530:1530:1530)) + (PORT asdata (1220:1220:1220) (1222:1222:1222)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (730:730:730) (755:755:755)) + (PORT datab (242:242:242) (323:323:323)) + (PORT datad (227:227:227) (265:265:265)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~38) (DELAY (ABSOLUTE - (PORT dataa (773:773:773) (837:837:837)) - (PORT datab (560:560:560) (597:597:597)) - (PORT datac (558:558:558) (555:555:555)) - (PORT datad (850:850:850) (877:877:877)) + (PORT dataa (335:335:335) (368:368:368)) + (PORT datab (622:622:622) (648:648:648)) + (PORT datac (339:339:339) (359:359:359)) + (PORT datad (316:316:316) (336:336:336)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -18046,92 +14994,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~39) + (INSTANCE z80_\|execute_\|ctl_inc_dec\~11) (DELAY (ABSOLUTE - (PORT dataa (837:837:837) (909:909:909)) - (PORT datab (396:396:396) (421:421:421)) - (PORT datac (848:848:848) (907:907:907)) - (PORT datad (1297:1297:1297) (1337:1337:1337)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1554:1554:1554)) - (PORT asdata (545:545:545) (579:579:579)) - (PORT ena (940:940:940) (926:926:926)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1897:1897:1897) (1987:1987:1987)) - (PORT datab (235:235:235) (281:281:281)) - (PORT datad (211:211:211) (246:246:246)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1554:1554:1554)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (842:842:842) (856:856:856)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (237:237:237) (287:287:287)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datad (354:354:354) (413:413:413)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1139:1139:1139) (1156:1156:1156)) - (PORT datab (545:545:545) (561:561:561)) - (PORT datac (201:201:201) (238:238:238)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) + (PORT dataa (1309:1309:1309) (1333:1333:1333)) + (PORT datab (1787:1787:1787) (1911:1911:1911)) + (PORT datac (2047:2047:2047) (2168:2168:2168)) + (PORT datad (1796:1796:1796) (1868:1868:1868)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -18139,97 +15010,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[10\]) + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|d0_out) (DELAY (ABSOLUTE - (PORT datac (200:200:200) (235:235:235)) - (PORT datad (869:869:869) (899:899:899)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|Q\[10\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (531:531:531) (546:546:546)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[10\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1560:1560:1560)) - (PORT ena (2096:2096:2096) (2133:2133:2133)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|carry_borrow_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (270:270:270) (368:368:368)) - (PORT datab (276:276:276) (370:370:370)) - (PORT datac (1338:1338:1338) (1352:1352:1352)) - (PORT datad (324:324:324) (345:345:345)) - (IOPATH dataa combout (301:301:301) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[11\]) - (DELAY - (ABSOLUTE - (PORT datab (602:602:602) (632:632:632)) - (PORT datad (924:924:924) (945:945:945)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[11\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1560:1560:1560)) - (PORT ena (2096:2096:2096) (2133:2133:2133)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[11\]) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (265:265:265)) - (PORT datac (568:568:568) (632:632:632)) + (PORT dataa (965:965:965) (1060:1060:1060)) + (PORT datac (186:186:186) (228:228:228)) (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datac combout (243:243:243) (242:242:242)) ) @@ -18237,12 +15022,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[3\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[1\]) (DELAY (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) + (PORT clk (1520:1520:1520) (1533:1533:1533)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1308:1308:1308) (1303:1303:1303)) + (PORT ena (1256:1256:1256) (1263:1263:1263)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -18252,13 +15037,481 @@ ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[3\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~5) (DELAY (ABSOLUTE - (PORT clk (1535:1535:1535) (1554:1554:1554)) - (PORT asdata (738:738:738) (772:772:772)) - (PORT ena (935:935:935) (924:924:924)) + (PORT dataa (911:911:911) (984:984:984)) + (PORT datab (1562:1562:1562) (1669:1669:1669)) + (PORT datac (1535:1535:1535) (1633:1633:1633)) + (PORT datad (396:396:396) (445:445:445)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1001:1001:1001) (1101:1101:1101)) + (PORT datab (1208:1208:1208) (1269:1269:1269)) + (PORT datac (1708:1708:1708) (1749:1749:1749)) + (PORT datad (674:674:674) (737:737:737)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~4) + (DELAY + (ABSOLUTE + (PORT dataa (339:339:339) (368:368:368)) + (PORT datab (228:228:228) (270:270:270)) + (PORT datac (690:690:690) (753:753:753)) + (PORT datad (334:334:334) (356:356:356)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1572:1572:1572) (1633:1633:1633)) + (PORT datab (1675:1675:1675) (1753:1753:1753)) + (PORT datac (2438:2438:2438) (2563:2563:2563)) + (PORT datad (1464:1464:1464) (1552:1552:1552)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1187:1187:1187) (1256:1256:1256)) + (PORT datab (1497:1497:1497) (1588:1588:1588)) + (PORT datac (825:825:825) (837:837:837)) + (PORT datad (911:911:911) (933:933:933)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~16) + (DELAY + (ABSOLUTE + (PORT dataa (651:651:651) (689:689:689)) + (PORT datab (923:923:923) (984:984:984)) + (PORT datac (2027:2027:2027) (2074:2074:2074)) + (PORT datad (1269:1269:1269) (1341:1341:1341)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~6) + (DELAY + (ABSOLUTE + (PORT dataa (636:636:636) (702:702:702)) + (PORT datab (199:199:199) (239:239:239)) + (PORT datac (171:171:171) (203:203:203)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~7) + (DELAY + (ABSOLUTE + (PORT dataa (652:652:652) (685:685:685)) + (PORT datab (1497:1497:1497) (1586:1586:1586)) + (PORT datac (215:215:215) (258:258:258)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~10) + (DELAY + (ABSOLUTE + (PORT dataa (2089:2089:2089) (2206:2206:2206)) + (PORT datab (1341:1341:1341) (1346:1346:1346)) + (PORT datac (1430:1430:1430) (1538:1538:1538)) + (PORT datad (844:844:844) (882:882:882)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~8) + (DELAY + (ABSOLUTE + (PORT dataa (223:223:223) (278:278:278)) + (PORT datab (881:881:881) (923:923:923)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (1876:1876:1876) (2029:2029:2029)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_pf_sel_nop3pla68M3T1_20) + (DELAY + (ABSOLUTE + (PORT dataa (936:936:936) (999:999:999)) + (PORT datab (976:976:976) (1037:1037:1037)) + (PORT datac (1800:1800:1800) (1897:1897:1897)) + (PORT datad (1656:1656:1656) (1724:1724:1724)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~42) + (DELAY + (ABSOLUTE + (PORT datac (586:586:586) (602:602:602)) + (PORT datad (196:196:196) (236:236:236)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~9) + (DELAY + (ABSOLUTE + (PORT dataa (592:592:592) (622:622:622)) + (PORT datab (197:197:197) (237:237:237)) + (PORT datac (901:901:901) (936:936:936)) + (PORT datad (211:211:211) (243:243:243)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~5) + (DELAY + (ABSOLUTE + (PORT dataa (647:647:647) (699:699:699)) + (PORT datab (1906:1906:1906) (1991:1991:1991)) + (PORT datac (1135:1135:1135) (1200:1200:1200)) + (PORT datad (1429:1429:1429) (1503:1503:1503)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~6) + (DELAY + (ABSOLUTE + (PORT dataa (2152:2152:2152) (2228:2228:2228)) + (PORT datab (969:969:969) (1086:1086:1086)) + (PORT datac (1061:1061:1061) (1115:1115:1115)) + (PORT datad (1104:1104:1104) (1170:1170:1170)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~7) + (DELAY + (ABSOLUTE + (PORT dataa (413:413:413) (439:439:439)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (201:201:201) (237:237:237)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1496:1496:1496) (1590:1590:1590)) + (PORT datac (1286:1286:1286) (1347:1347:1347)) + (PORT datad (1899:1899:1899) (2019:2019:2019)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1187:1187:1187) (1240:1240:1240)) + (PORT datab (930:930:930) (999:999:999)) + (PORT datac (1936:1936:1936) (2079:2079:2079)) + (PORT datad (607:607:607) (665:665:665)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (623:623:623) (662:662:662)) + (PORT datab (1100:1100:1100) (1165:1165:1165)) + (PORT datac (813:813:813) (826:826:826)) + (PORT datad (846:846:846) (923:923:923)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~3) + (DELAY + (ABSOLUTE + (PORT dataa (572:572:572) (612:612:612)) + (PORT datab (887:887:887) (950:950:950)) + (PORT datac (784:784:784) (791:791:791)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~2) + (DELAY + (ABSOLUTE + (PORT dataa (418:418:418) (444:444:444)) + (PORT datab (1102:1102:1102) (1162:1162:1162)) + (PORT datac (2128:2128:2128) (2195:2195:2195)) + (PORT datad (814:814:814) (882:882:882)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1125:1125:1125) (1164:1164:1164)) + (PORT datab (1363:1363:1363) (1391:1391:1391)) + (PORT datac (555:555:555) (574:574:574)) + (PORT datad (831:831:831) (848:848:848)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~4) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (241:241:241)) + (PORT datab (196:196:196) (235:235:235)) + (PORT datac (836:836:836) (862:862:862)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~8) + (DELAY + (ABSOLUTE + (PORT dataa (633:633:633) (669:669:669)) + (PORT datab (220:220:220) (259:259:259)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (172:172:172) (198:198:198)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1496:1496:1496) (1590:1590:1590)) + (PORT datab (1937:1937:1937) (2057:2057:2057)) + (PORT datac (1288:1288:1288) (1349:1349:1349)) + (PORT datad (1492:1492:1492) (1552:1552:1552)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~2) + (DELAY + (ABSOLUTE + (PORT datab (630:630:630) (651:651:651)) + (PORT datac (853:853:853) (863:863:863)) + (PORT datad (359:359:359) (379:379:379)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (915:915:915) (927:927:927)) + (PORT datab (1335:1335:1335) (1355:1355:1355)) + (PORT datac (1623:1623:1623) (1740:1740:1740)) + (PORT datad (588:588:588) (591:591:591)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (790:790:790) (782:782:782)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_32) + (DELAY + (ABSOLUTE + (PORT dataa (1526:1526:1526) (1579:1579:1579)) + (PORT datab (2177:2177:2177) (2220:2220:2220)) + (PORT datad (1363:1363:1363) (1385:1385:1385)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1533:1533:1533)) + (PORT asdata (713:713:713) (749:749:749)) + (PORT ena (1227:1227:1227) (1249:1249:1249)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1533:1533:1533)) + (PORT asdata (714:714:714) (748:748:748)) + (PORT ena (1503:1503:1503) (1497:1497:1497)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -18269,14 +15522,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~10) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~81) (DELAY (ABSOLUTE - (PORT dataa (221:221:221) (264:264:264)) - (PORT datab (407:407:407) (446:446:446)) - (PORT datad (388:388:388) (422:422:422)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (702:702:702) (773:773:773)) + (PORT datab (240:240:240) (322:322:322)) + (PORT datad (698:698:698) (750:750:750)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -18284,43 +15537,27 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~11) + (INSTANCE z80_\|alu_\|db_high\[2\]\~8) (DELAY (ABSOLUTE - (PORT dataa (247:247:247) (335:335:335)) - (PORT datac (823:823:823) (870:870:870)) - (PORT datad (639:639:639) (664:664:664)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT datab (872:872:872) (903:903:903)) + (PORT datac (789:789:789) (812:812:812)) + (PORT datad (1182:1182:1182) (1266:1266:1266)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~12) + (INSTANCE z80_\|alu_\|db_high\[2\]\~9) (DELAY (ABSOLUTE - (PORT dataa (565:565:565) (577:577:577)) - (PORT datab (846:846:846) (883:883:883)) - (PORT datac (679:679:679) (728:728:728)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~48) - (DELAY - (ABSOLUTE - (PORT dataa (612:612:612) (644:644:644)) - (PORT datab (820:820:820) (880:880:880)) - (PORT datac (393:393:393) (430:430:430)) - (PORT datad (1301:1301:1301) (1333:1333:1333)) + (PORT dataa (1091:1091:1091) (1112:1112:1112)) + (PORT datab (700:700:700) (753:753:753)) + (PORT datac (173:173:173) (207:207:207)) + (PORT datad (1274:1274:1274) (1296:1296:1296)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -18330,15 +15567,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[3\]\~9) + (INSTANCE z80_\|alu_\|db_high\[2\]\~11) (DELAY (ABSOLUTE - (PORT dataa (872:872:872) (916:916:916)) - (PORT datab (223:223:223) (272:272:272)) - (PORT datac (1159:1159:1159) (1203:1203:1203)) - (PORT datad (607:607:607) (634:634:634)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (331:331:331) (342:342:342)) + (PORT datab (274:274:274) (331:331:331)) + (PORT datac (244:244:244) (308:308:308)) + (PORT datad (250:250:250) (298:298:298)) + (IOPATH datab combout (304:304:304) (311:311:311)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -18346,40 +15581,24 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op1_sel_low) + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[2\]) (DELAY (ABSOLUTE - (PORT dataa (1004:1004:1004) (1068:1068:1068)) - (PORT datab (2092:2092:2092) (2152:2152:2152)) - (PORT datac (686:686:686) (739:739:739)) - (PORT datad (1737:1737:1737) (1857:1857:1857)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[3\]) - (DELAY - (ABSOLUTE - (PORT datab (964:964:964) (1009:1009:1009)) - (PORT datac (1166:1166:1166) (1163:1163:1163)) - (PORT datad (680:680:680) (717:717:717)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (934:934:934) (963:963:963)) + (PORT datac (620:620:620) (650:650:650)) + (PORT datad (831:831:831) (844:844:844)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_high\[3\]) + (INSTANCE z80_\|alu_\|op1_high\[2\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1531:1531:1531)) + (PORT clk (1547:1547:1547) (1549:1549:1549)) (PORT d (74:74:74) (91:91:91)) (PORT ena (819:819:819) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) @@ -18392,61 +15611,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op1\[3\]\~3) + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_lq) (DELAY (ABSOLUTE - (PORT datab (652:652:652) (711:711:711)) - (PORT datac (647:647:647) (707:707:707)) - (PORT datad (634:634:634) (661:661:661)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_10\~0) - (DELAY - (ABSOLUTE - (PORT dataa (638:638:638) (713:713:713)) - (PORT datab (641:641:641) (708:708:708)) - (PORT datac (193:193:193) (226:226:226)) - (PORT datad (575:575:575) (599:599:599)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1127:1127:1127) (1169:1169:1169)) - (PORT datab (1268:1268:1268) (1379:1379:1379)) - (PORT datac (613:613:613) (634:634:634)) - (PORT datad (1131:1131:1131) (1134:1134:1134)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~10) - (DELAY - (ABSOLUTE - (PORT dataa (2003:2003:2003) (2192:2192:2192)) - (PORT datab (1271:1271:1271) (1346:1346:1346)) - (PORT datac (994:994:994) (1035:1035:1035)) - (PORT datad (1461:1461:1461) (1531:1531:1531)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) + (PORT dataa (1728:1728:1728) (1817:1817:1817)) + (PORT datab (954:954:954) (1011:1011:1011)) + (PORT datac (1674:1674:1674) (1744:1744:1744)) + (PORT datad (1047:1047:1047) (1131:1131:1131)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -18454,15 +15627,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~0) + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[2\]\~2) (DELAY (ABSOLUTE - (PORT dataa (1013:1013:1013) (1048:1048:1048)) - (PORT datab (1598:1598:1598) (1713:1713:1713)) - (PORT datac (1145:1145:1145) (1147:1147:1147)) - (PORT datad (654:654:654) (698:698:698)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) + (PORT datac (612:612:612) (626:626:626)) + (PORT datad (650:650:650) (658:658:658)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -18473,10 +15642,10 @@ (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~5) (DELAY (ABSOLUTE - (PORT dataa (2564:2564:2564) (2702:2702:2702)) - (PORT datab (1558:1558:1558) (1680:1680:1680)) - (PORT datac (866:866:866) (908:908:908)) - (PORT datad (191:191:191) (224:224:224)) + (PORT dataa (1847:1847:1847) (1981:1981:1981)) + (PORT datab (1906:1906:1906) (2025:2025:2025)) + (PORT datac (1061:1061:1061) (1069:1069:1069)) + (PORT datad (345:345:345) (369:369:369)) (IOPATH dataa combout (303:303:303) (299:299:299)) (IOPATH datab combout (304:304:304) (308:308:308)) (IOPATH datac combout (243:243:243) (242:242:242)) @@ -18484,18 +15653,32 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~6) + (DELAY + (ABSOLUTE + (PORT dataa (610:610:610) (653:653:653)) + (PORT datab (1978:1978:1978) (2129:2129:2129)) + (PORT datac (1712:1712:1712) (1753:1753:1753)) + (PORT datad (1105:1105:1105) (1133:1133:1133)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~7) (DELAY (ABSOLUTE - (PORT dataa (385:385:385) (411:411:411)) - (PORT datab (804:804:804) (851:851:851)) - (PORT datac (829:829:829) (862:862:862)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (349:349:349) (384:384:384)) + (PORT datac (196:196:196) (241:241:241)) + (PORT datad (211:211:211) (245:245:245)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -18505,12 +15688,12 @@ (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_bus\~8) (DELAY (ABSOLUTE - (PORT dataa (647:647:647) (668:668:668)) - (PORT datab (1164:1164:1164) (1226:1226:1226)) - (PORT datac (562:562:562) (562:562:562)) - (PORT datad (595:595:595) (626:626:626)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) + (PORT dataa (866:866:866) (890:890:890)) + (PORT datab (219:219:219) (258:258:258)) + (PORT datac (531:531:531) (544:544:544)) + (PORT datad (1010:1010:1010) (1067:1067:1067)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -18518,29 +15701,33 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[1\]\~5) + (INSTANCE z80_\|execute_\|ctl_alu_op2_sel_zero) (DELAY (ABSOLUTE - (PORT dataa (588:588:588) (616:616:616)) - (PORT datab (1125:1125:1125) (1173:1173:1173)) - (PORT datac (561:561:561) (579:579:579)) - (PORT datad (905:905:905) (952:952:952)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (794:794:794) (844:844:844)) + (PORT datab (658:658:658) (689:689:689)) + (PORT datac (823:823:823) (867:867:867)) + (PORT datad (564:564:564) (578:578:578)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[1\]\~6) + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[2\]\~3) (DELAY (ABSOLUTE - (PORT dataa (258:258:258) (332:332:332)) - (PORT datac (170:170:170) (202:202:202)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (899:899:899) (923:923:923)) + (PORT datac (928:928:928) (953:953:953)) + (PORT datad (866:866:866) (900:900:900)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -18549,10 +15736,1862 @@ (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|ena) (DELAY (ABSOLUTE - (PORT dataa (263:263:263) (339:339:339)) - (PORT datac (1090:1090:1090) (1144:1144:1144)) - (PORT datad (902:902:902) (951:951:951)) + (PORT dataa (652:652:652) (673:673:673)) + (PORT datab (912:912:912) (940:940:940)) + (PORT datac (936:936:936) (955:955:955)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_high\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1535:1535:1535) (1540:1540:1540)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[2\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (604:604:604) (673:673:673)) + (PORT datab (703:703:703) (722:722:722)) + (PORT datac (623:623:623) (644:644:644)) + (PORT datad (657:657:657) (722:722:722)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[2\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (619:619:619) (669:669:669)) + (PORT datab (1147:1147:1147) (1159:1159:1159)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (321:321:321) (342:342:342)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~1) + (DELAY + (ABSOLUTE + (PORT datab (696:696:696) (745:745:745)) + (PORT datad (646:646:646) (669:669:669)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[2\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (874:874:874) (936:936:936)) + (PORT datab (602:602:602) (632:632:632)) + (PORT datac (342:342:342) (366:366:366)) + (PORT datad (623:623:623) (654:654:654)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT asdata (936:936:936) (967:967:967)) + (PORT ena (790:790:790) (782:782:782)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT asdata (938:938:938) (970:970:970)) + (PORT ena (1288:1288:1288) (1306:1306:1306)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~78) + (DELAY + (ABSOLUTE + (PORT dataa (663:663:663) (748:748:748)) + (PORT datab (241:241:241) (323:323:323)) + (PORT datad (232:232:232) (273:273:273)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_78\~0) + (DELAY + (ABSOLUTE + (PORT dataa (890:890:890) (908:908:908)) + (PORT datab (753:753:753) (817:817:817)) + (PORT datac (632:632:632) (680:680:680)) + (PORT datad (940:940:940) (969:969:969)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT asdata (537:537:537) (568:568:568)) + (PORT ena (1438:1438:1438) (1476:1476:1476)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~79) + (DELAY + (ABSOLUTE + (PORT dataa (701:701:701) (767:767:767)) + (PORT datab (860:860:860) (879:879:879)) + (PORT datad (1349:1349:1349) (1339:1339:1339)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_34) + (DELAY + (ABSOLUTE + (PORT dataa (1003:1003:1003) (1065:1065:1065)) + (PORT datac (1584:1584:1584) (1603:1603:1603)) + (PORT datad (1140:1140:1140) (1176:1176:1176)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (877:877:877) (903:903:903)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_35) + (DELAY + (ABSOLUTE + (PORT dataa (1009:1009:1009) (1067:1067:1067)) + (PORT datac (1587:1587:1587) (1605:1605:1605)) + (PORT datad (1143:1143:1143) (1178:1178:1178)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (812:812:812) (804:804:804)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_31) + (DELAY + (ABSOLUTE + (PORT dataa (1005:1005:1005) (1065:1065:1065)) + (PORT datab (1168:1168:1168) (1214:1214:1214)) + (PORT datac (794:794:794) (826:826:826)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT asdata (1225:1225:1225) (1251:1251:1251)) + (PORT ena (841:841:841) (846:846:846)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_30) + (DELAY + (ABSOLUTE + (PORT dataa (1000:1000:1000) (1056:1056:1056)) + (PORT datab (1168:1168:1168) (1209:1209:1209)) + (PORT datac (795:795:795) (824:824:824)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~75) + (DELAY + (ABSOLUTE + (PORT dataa (230:230:230) (279:279:279)) + (PORT datab (242:242:242) (324:324:324)) + (PORT datad (202:202:202) (231:231:231)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (632:632:632) (663:663:663)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1220:1220:1220) (1212:1212:1212)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT asdata (1168:1168:1168) (1193:1193:1193)) + (PORT ena (1200:1200:1200) (1188:1188:1188)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~76) + (DELAY + (ABSOLUTE + (PORT dataa (855:855:855) (927:927:927)) + (PORT datab (241:241:241) (323:323:323)) + (PORT datad (662:662:662) (728:728:728)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1535:1535:1535)) + (PORT asdata (964:964:964) (1000:1000:1000)) + (PORT ena (1274:1274:1274) (1265:1265:1265)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~77) + (DELAY + (ABSOLUTE + (PORT dataa (383:383:383) (407:407:407)) + (PORT datad (923:923:923) (952:952:952)) (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~80) + (DELAY + (ABSOLUTE + (PORT dataa (557:557:557) (571:571:571)) + (PORT datab (523:523:523) (537:537:537)) + (PORT datac (774:774:774) (767:767:767)) + (PORT datad (829:829:829) (841:841:841)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1535:1535:1535)) + (PORT asdata (925:925:925) (956:956:956)) + (PORT ena (975:975:975) (963:963:963)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1535:1535:1535)) + (PORT asdata (925:925:925) (955:955:955)) + (PORT ena (1008:1008:1008) (1010:1010:1010)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~74) + (DELAY + (ABSOLUTE + (PORT dataa (376:376:376) (418:418:418)) + (PORT datab (239:239:239) (321:321:321)) + (PORT datad (368:368:368) (391:391:391)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1550:1550:1550)) + (PORT asdata (1170:1170:1170) (1200:1200:1200)) + (PORT ena (811:811:811) (804:804:804)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1550:1550:1550)) + (PORT asdata (1170:1170:1170) (1200:1200:1200)) + (PORT ena (842:842:842) (856:856:856)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~73) + (DELAY + (ABSOLUTE + (PORT dataa (243:243:243) (330:330:330)) + (PORT datab (237:237:237) (282:282:282)) + (PORT datad (211:211:211) (243:243:243)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~81) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (242:242:242)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datad (609:609:609) (620:620:620)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1132:1132:1132) (1169:1169:1169)) + (PORT datab (656:656:656) (710:710:710)) + (PORT datac (625:625:625) (675:675:675)) + (PORT datad (1350:1350:1350) (1340:1340:1340)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (681:681:681) (698:698:698)) + (PORT datab (640:640:640) (663:663:663)) + (PORT datac (665:665:665) (728:728:728)) + (PORT datad (1170:1170:1170) (1177:1177:1177)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (413:413:413) (443:443:443)) + (PORT datab (196:196:196) (235:235:235)) + (PORT datac (606:606:606) (655:655:655)) + (PORT datad (173:173:173) (197:197:197)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~92) + (DELAY + (ABSOLUTE + (PORT dataa (925:925:925) (979:979:979)) + (PORT datab (664:664:664) (723:723:723)) + (PORT datac (614:614:614) (668:668:668)) + (PORT datad (592:592:592) (635:635:635)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (406:406:406) (454:454:454)) + (PORT datab (439:439:439) (469:469:469)) + (PORT datac (601:601:601) (622:622:622)) + (PORT datad (582:582:582) (592:592:592)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_74) + (DELAY + (ABSOLUTE + (PORT dataa (1043:1043:1043) (1067:1067:1067)) + (PORT datac (1149:1149:1149) (1189:1189:1189)) + (PORT datad (874:874:874) (911:911:911)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_62) + (DELAY + (ABSOLUTE + (PORT datab (901:901:901) (951:951:951)) + (PORT datac (1148:1148:1148) (1189:1189:1189)) + (PORT datad (798:798:798) (802:802:802)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (448:448:448) (491:491:491)) + (PORT datab (1064:1064:1064) (1078:1078:1078)) + (PORT datac (1615:1615:1615) (1630:1630:1630)) + (PORT datad (615:615:615) (638:638:638)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1231:1231:1231) (1237:1237:1237)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT asdata (732:732:732) (765:765:765)) + (PORT ena (790:790:790) (782:782:782)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT asdata (536:536:536) (566:566:566)) + (PORT ena (1438:1438:1438) (1476:1476:1476)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~55) + (DELAY + (ABSOLUTE + (PORT dataa (258:258:258) (314:314:314)) + (PORT datab (632:632:632) (696:696:696)) + (PORT datad (362:362:362) (421:421:421)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT asdata (735:735:735) (766:766:766)) + (PORT ena (1288:1288:1288) (1306:1306:1306)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~56) + (DELAY + (ABSOLUTE + (PORT datab (198:198:198) (236:236:236)) + (PORT datad (639:639:639) (700:700:700)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT asdata (912:912:912) (932:932:932)) + (PORT ena (981:981:981) (980:980:980)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT asdata (911:911:911) (930:930:930)) + (PORT ena (811:811:811) (804:804:804)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~57) + (DELAY + (ABSOLUTE + (PORT dataa (244:244:244) (330:330:330)) + (PORT datab (253:253:253) (303:303:303)) + (PORT datad (229:229:229) (266:266:266)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT asdata (1017:1017:1017) (1036:1036:1036)) + (PORT ena (1220:1220:1220) (1212:1212:1212)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT asdata (1017:1017:1017) (1039:1039:1039)) + (PORT ena (1200:1200:1200) (1188:1188:1188)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~59) + (DELAY + (ABSOLUTE + (PORT dataa (863:863:863) (935:935:935)) + (PORT datab (241:241:241) (324:324:324)) + (PORT datad (658:658:658) (724:724:724)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT asdata (1040:1040:1040) (1065:1065:1065)) + (PORT ena (812:812:812) (804:804:804)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT asdata (1041:1041:1041) (1066:1066:1066)) + (PORT ena (841:841:841) (846:846:846)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~58) + (DELAY + (ABSOLUTE + (PORT dataa (231:231:231) (280:280:280)) + (PORT datab (241:241:241) (323:323:323)) + (PORT datad (201:201:201) (228:228:228)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1535:1535:1535)) + (PORT asdata (1414:1414:1414) (1418:1418:1418)) + (PORT ena (1274:1274:1274) (1265:1265:1265)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~60) + (DELAY + (ABSOLUTE + (PORT dataa (636:636:636) (656:656:656)) + (PORT datab (336:336:336) (365:365:365)) + (PORT datad (930:930:930) (955:955:955)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1549:1549:1549)) + (PORT asdata (1181:1181:1181) (1187:1187:1187)) + (PORT ena (974:974:974) (969:969:969)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1549:1549:1549)) + (PORT asdata (1182:1182:1182) (1188:1188:1188)) + (PORT ena (975:975:975) (970:970:970)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~53) + (DELAY + (ABSOLUTE + (PORT dataa (409:409:409) (451:451:451)) + (PORT datab (434:434:434) (466:466:466)) + (PORT datad (216:216:216) (284:284:284)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~54) + (DELAY + (ABSOLUTE + (PORT dataa (865:865:865) (894:894:894)) + (PORT datac (905:905:905) (908:908:908)) + (PORT datad (845:845:845) (879:879:879)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~61) + (DELAY + (ABSOLUTE + (PORT dataa (635:635:635) (651:651:651)) + (PORT datab (615:615:615) (639:639:639)) + (PORT datac (345:345:345) (369:369:369)) + (PORT datad (341:341:341) (361:361:361)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~62) + (DELAY + (ABSOLUTE + (PORT dataa (633:633:633) (650:650:650)) + (PORT datab (664:664:664) (693:693:693)) + (PORT datac (1100:1100:1100) (1130:1130:1130)) + (PORT datad (624:624:624) (647:647:647)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_75) + (DELAY + (ABSOLUTE + (PORT dataa (1041:1041:1041) (1071:1071:1071)) + (PORT datac (1149:1149:1149) (1187:1187:1187)) + (PORT datad (874:874:874) (906:906:906)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (672:672:672) (693:693:693)) + (PORT ena (1200:1200:1200) (1181:1181:1181)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (893:893:893) (938:938:938)) + (PORT datab (677:677:677) (714:714:714)) + (PORT datad (402:402:402) (437:437:437)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (245:245:245) (332:332:332)) + (PORT datab (198:198:198) (238:238:238)) + (PORT datad (613:613:613) (638:638:638)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_4\|d0_out) + (DELAY + (ABSOLUTE + (PORT datac (931:931:931) (1001:1001:1001)) + (PORT datad (599:599:599) (611:611:611)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1647:1647:1647) (1678:1678:1678)) + (PORT datab (198:198:198) (238:238:238)) + (PORT datac (576:576:576) (590:590:590)) + (PORT datad (351:351:351) (383:383:383)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[4\]) + (DELAY + (ABSOLUTE + (PORT datab (942:942:942) (968:968:968)) + (PORT datad (940:940:940) (982:982:982)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1560:1560:1560) (1542:1542:1542)) + (PORT ena (1949:1949:1949) (1917:1917:1917)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_4\|d1_out) + (DELAY + (ABSOLUTE + (PORT dataa (1126:1126:1126) (1148:1148:1148)) + (PORT datab (960:960:960) (1034:1034:1034)) + (PORT datac (913:913:913) (1000:1000:1000)) + (PORT datad (599:599:599) (612:612:612)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (985:985:985) (993:993:993)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT asdata (1770:1770:1770) (1777:1777:1777)) + (PORT ena (981:981:981) (980:980:980)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT asdata (1769:1769:1769) (1776:1776:1776)) + (PORT ena (811:811:811) (804:804:804)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~64) + (DELAY + (ABSOLUTE + (PORT dataa (385:385:385) (457:457:457)) + (PORT datab (253:253:253) (304:304:304)) + (PORT datad (230:230:230) (269:269:269)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1549:1549:1549)) + (PORT asdata (1221:1221:1221) (1232:1232:1232)) + (PORT ena (974:974:974) (969:969:969)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1549:1549:1549)) + (PORT asdata (1221:1221:1221) (1232:1232:1232)) + (PORT ena (975:975:975) (970:970:970)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~63) + (DELAY + (ABSOLUTE + (PORT dataa (406:406:406) (455:455:455)) + (PORT datab (435:435:435) (464:464:464)) + (PORT datad (215:215:215) (283:283:283)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1549:1549:1549)) + (PORT asdata (1759:1759:1759) (1781:1781:1781)) + (PORT ena (1240:1240:1240) (1231:1231:1231)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (849:849:849) (862:862:862)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1549:1549:1549)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1207:1207:1207) (1180:1180:1180)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~65) + (DELAY + (ABSOLUTE + (PORT dataa (698:698:698) (740:740:740)) + (PORT datab (706:706:706) (731:731:731)) + (PORT datad (217:217:217) (285:285:285)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (790:790:790) (782:782:782)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT asdata (1725:1725:1725) (1719:1719:1719)) + (PORT ena (1438:1438:1438) (1476:1476:1476)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~69) + (DELAY + (ABSOLUTE + (PORT dataa (697:697:697) (765:765:765)) + (PORT datab (617:617:617) (679:679:679)) + (PORT datad (374:374:374) (394:394:394)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1535:1535:1535)) + (PORT asdata (1502:1502:1502) (1512:1512:1512)) + (PORT ena (1243:1243:1243) (1246:1246:1246)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT asdata (2035:2035:2035) (2028:2028:2028)) + (PORT ena (1220:1220:1220) (1212:1212:1212)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~68) + (DELAY + (ABSOLUTE + (PORT dataa (636:636:636) (696:696:696)) + (PORT datab (681:681:681) (741:741:741)) + (PORT datad (662:662:662) (728:728:728)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1535:1535:1535)) + (PORT asdata (1504:1504:1504) (1515:1515:1515)) + (PORT ena (1274:1274:1274) (1265:1265:1265)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT asdata (2034:2034:2034) (2029:2029:2029)) + (PORT ena (1200:1200:1200) (1188:1188:1188)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~66) + (DELAY + (ABSOLUTE + (PORT dataa (862:862:862) (933:933:933)) + (PORT datab (587:587:587) (614:614:614)) + (PORT datad (555:555:555) (569:569:569)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~67) + (DELAY + (ABSOLUTE + (PORT datab (958:958:958) (995:995:995)) + (PORT datad (601:601:601) (616:616:616)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~70) + (DELAY + (ABSOLUTE + (PORT dataa (641:641:641) (660:660:660)) + (PORT datab (671:671:671) (687:687:687)) + (PORT datac (602:602:602) (610:610:610)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~71) + (DELAY + (ABSOLUTE + (PORT dataa (337:337:337) (369:369:369)) + (PORT datab (635:635:635) (653:653:653)) + (PORT datad (595:595:595) (608:608:608)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~72) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (826:826:826) (846:846:846)) + (PORT datac (631:631:631) (652:652:652)) + (PORT datad (832:832:832) (865:865:865)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (913:913:913) (926:926:926)) + (PORT ena (971:971:971) (959:959:959)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[5\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1444:1444:1444) (1471:1471:1471)) + (PORT datab (1050:1050:1050) (1065:1065:1065)) + (PORT datad (561:561:561) (573:573:573)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[5\]\~17) + (DELAY + (ABSOLUTE + (PORT datab (243:243:243) (325:325:325)) + (PORT datac (334:334:334) (359:359:359)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[5\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (579:579:579) (605:605:605)) + (PORT datab (219:219:219) (258:258:258)) + (PORT datac (171:171:171) (205:205:205)) + (PORT datad (1832:1832:1832) (1823:1823:1823)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[5\]) + (DELAY + (ABSOLUTE + (PORT datab (896:896:896) (918:918:918)) + (PORT datad (941:941:941) (978:978:978)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1560:1560:1560) (1542:1542:1542)) + (PORT ena (1949:1949:1949) (1917:1917:1917)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_dec\~10) + (DELAY + (ABSOLUTE + (PORT datac (1275:1275:1275) (1291:1291:1291)) + (PORT datad (1798:1798:1798) (1868:1868:1868)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_43\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1011:1011:1011) (1080:1080:1080)) + (PORT datab (1788:1788:1788) (1913:1913:1913)) + (PORT datac (211:211:211) (256:256:256)) + (PORT datad (1858:1858:1858) (1988:1988:1988)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_44) + (DELAY + (ABSOLUTE + (PORT dataa (1893:1893:1893) (2029:2029:2029)) + (PORT datab (1787:1787:1787) (1908:1908:1908)) + (PORT datac (208:208:208) (257:257:257)) + (PORT datad (1226:1226:1226) (1279:1279:1279)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[6\]) + (DELAY + (ABSOLUTE + (PORT datac (872:872:872) (895:895:895)) + (PORT datad (939:939:939) (981:981:981)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1560:1560:1560) (1542:1542:1542)) + (PORT ena (1949:1949:1949) (1917:1917:1917)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[6\]) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (255:255:255)) + (PORT datab (208:208:208) (250:250:250)) + (PORT datac (942:942:942) (988:988:988)) + (PORT datad (204:204:204) (234:234:234)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (985:985:985) (993:993:993)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT asdata (672:672:672) (694:694:694)) + (PORT ena (971:971:971) (959:959:959)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (643:643:643) (697:697:697)) + (PORT datab (1050:1050:1050) (1068:1068:1068)) + (PORT datad (561:561:561) (576:576:576)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~20) + (DELAY + (ABSOLUTE + (PORT datab (242:242:242) (324:324:324)) + (PORT datac (336:336:336) (359:359:359)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (579:579:579) (604:604:604)) + (PORT datab (860:860:860) (862:862:862)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (1832:1832:1832) (1822:1822:1822)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~82) + (DELAY + (ABSOLUTE + (PORT dataa (1133:1133:1133) (1169:1169:1169)) + (PORT datab (605:605:605) (614:614:614)) + (PORT datac (635:635:635) (662:662:662)) + (PORT datad (634:634:634) (651:651:651)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_ds\[6\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (821:821:821) (854:854:854)) + (PORT datab (1116:1116:1116) (1154:1154:1154)) + (PORT datac (650:650:650) (678:678:678)) + (PORT datad (863:863:863) (906:906:906)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sw1_\|db_down\[6\]\~1) + (DELAY + (ABSOLUTE + (PORT datab (654:654:654) (671:671:671)) + (PORT datac (404:404:404) (449:449:449)) + (PORT datad (833:833:833) (842:842:842)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_66_oe) + (DELAY + (ABSOLUTE + (PORT dataa (2284:2284:2284) (2429:2429:2429)) + (PORT datab (1247:1247:1247) (1332:1332:1332)) + (PORT datac (597:597:597) (660:660:660)) + (PORT datad (1623:1623:1623) (1693:1693:1693)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[1\]) + (DELAY + (ABSOLUTE + (PORT dataa (947:947:947) (979:979:979)) + (PORT datac (895:895:895) (917:917:917)) + (PORT datad (616:616:616) (641:641:641)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_high\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1547:1547:1547) (1549:1549:1549)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[1\]\~4) + (DELAY + (ABSOLUTE + (PORT datab (656:656:656) (697:697:697)) + (PORT datac (612:612:612) (626:626:626)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[1\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (965:965:965) (988:988:988)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (629:629:629) (647:647:647)) + (PORT datad (866:866:866) (896:896:896)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -18563,7 +17602,7 @@ (INSTANCE z80_\|alu_\|op2_high\[1\]) (DELAY (ABSOLUTE - (PORT clk (1529:1529:1529) (1531:1531:1531)) + (PORT clk (1535:1535:1535) (1540:1540:1540)) (PORT d (74:74:74) (91:91:91)) (PORT ena (819:819:819) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) @@ -18576,72 +17615,42 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[1\]) + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[1\]\~2) (DELAY (ABSOLUTE - (PORT datab (968:968:968) (1010:1010:1010)) - (PORT datac (370:370:370) (404:404:404)) - (PORT datad (675:675:675) (715:715:715)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_high\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[1\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (676:676:676) (733:733:733)) - (PORT datab (1128:1128:1128) (1182:1182:1182)) - (PORT datac (588:588:588) (620:620:620)) - (PORT datad (380:380:380) (439:439:439)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[1\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (264:264:264) (340:340:340)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (556:556:556) (578:578:578)) - (PORT datad (900:900:900) (949:949:949)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) + (PORT dataa (650:650:650) (672:672:672)) + (PORT datab (717:717:717) (776:776:776)) + (PORT datac (1098:1098:1098) (1129:1129:1129)) + (PORT datad (1110:1110:1110) (1144:1144:1144)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[1\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (965:965:965) (991:991:991)) + (PORT datab (908:908:908) (935:935:935)) + (PORT datac (629:629:629) (666:666:666)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|alu_\|op2_low\[1\]) (DELAY (ABSOLUTE - (PORT clk (1529:1529:1529) (1531:1531:1531)) + (PORT clk (1535:1535:1535) (1540:1540:1540)) (PORT d (74:74:74) (91:91:91)) (PORT ena (819:819:819) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) @@ -18652,991 +17661,16 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1468:1468:1468) (1479:1479:1479)) - (PORT datab (1497:1497:1497) (1572:1572:1572)) - (PORT datac (1847:1847:1847) (1915:1915:1915)) - (PORT datad (402:402:402) (438:438:438)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~20) - (DELAY - (ABSOLUTE - (PORT dataa (1433:1433:1433) (1518:1518:1518)) - (PORT datab (1643:1643:1643) (1769:1769:1769)) - (PORT datac (1052:1052:1052) (1102:1102:1102)) - (PORT datad (1294:1294:1294) (1385:1385:1385)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_state_alu\~12) - (DELAY - (ABSOLUTE - (PORT dataa (885:885:885) (898:898:898)) - (PORT datab (943:943:943) (983:983:983)) - (PORT datac (858:858:858) (877:877:877)) - (PORT datad (654:654:654) (664:664:664)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~18) - (DELAY - (ABSOLUTE - (PORT dataa (480:480:480) (518:518:518)) - (PORT datab (1187:1187:1187) (1249:1249:1249)) - (PORT datac (925:925:925) (1011:1011:1011)) - (PORT datad (1383:1383:1383) (1482:1482:1482)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal61\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1746:1746:1746) (1869:1869:1869)) - (PORT datab (1375:1375:1375) (1426:1426:1426)) - (PORT datac (1591:1591:1591) (1672:1672:1672)) - (PORT datad (1495:1495:1495) (1627:1627:1627)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~16) - (DELAY - (ABSOLUTE - (PORT datab (1828:1828:1828) (1926:1926:1926)) - (PORT datac (1699:1699:1699) (1792:1792:1792)) - (PORT datad (926:926:926) (994:994:994)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~17) - (DELAY - (ABSOLUTE - (PORT dataa (1872:1872:1872) (1889:1889:1889)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (880:880:880) (886:886:886)) - (PORT datad (803:803:803) (814:814:814)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1342:1342:1342) (1440:1440:1440)) - (PORT datab (1765:1765:1765) (1873:1873:1873)) - (PORT datac (1447:1447:1447) (1536:1536:1536)) - (PORT datad (195:195:195) (220:220:220)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1520:1520:1520) (1609:1609:1609)) - (PORT datab (925:925:925) (988:988:988)) - (PORT datac (193:193:193) (226:226:226)) - (PORT datad (203:203:203) (232:232:232)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~12) - (DELAY - (ABSOLUTE - (PORT dataa (219:219:219) (262:262:262)) - (PORT datab (207:207:207) (249:249:249)) - (PORT datac (177:177:177) (214:214:214)) - (PORT datad (182:182:182) (212:212:212)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~22) - (DELAY - (ABSOLUTE - (PORT dataa (1766:1766:1766) (1808:1808:1808)) - (PORT datab (836:836:836) (862:862:862)) - (PORT datac (1306:1306:1306) (1421:1421:1421)) - (PORT datad (2555:2555:2555) (2677:2677:2677)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~20) - (DELAY - (ABSOLUTE - (PORT dataa (582:582:582) (614:614:614)) - (PORT datab (246:246:246) (286:286:286)) - (PORT datac (221:221:221) (257:257:257)) - (PORT datad (904:904:904) (976:976:976)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1051:1051:1051) (1075:1075:1075)) - (PORT datab (1615:1615:1615) (1655:1655:1655)) - (PORT datac (1187:1187:1187) (1227:1227:1227)) - (PORT datad (1742:1742:1742) (1769:1769:1769)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal71\~2) - (DELAY - (ABSOLUTE - (PORT dataa (861:861:861) (921:921:921)) - (PORT datab (941:941:941) (1014:1014:1014)) - (PORT datac (219:219:219) (254:254:254)) - (PORT datad (903:903:903) (974:974:974)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~8) - (DELAY - (ABSOLUTE - (PORT dataa (209:209:209) (258:258:258)) - (PORT datab (220:220:220) (259:259:259)) - (PORT datac (201:201:201) (238:238:238)) - (PORT datad (182:182:182) (211:211:211)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~31) - (DELAY - (ABSOLUTE - (PORT dataa (1219:1219:1219) (1272:1272:1272)) - (PORT datab (227:227:227) (268:268:268)) - (PORT datac (2061:2061:2061) (2171:2171:2171)) - (PORT datad (1409:1409:1409) (1503:1503:1503)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~4) - (DELAY - (ABSOLUTE - (PORT dataa (697:697:697) (718:718:718)) - (PORT datab (1484:1484:1484) (1542:1542:1542)) - (PORT datac (1486:1486:1486) (1511:1511:1511)) - (PORT datad (640:640:640) (654:654:654)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_pla25M1T1_3) - (DELAY - (ABSOLUTE - (PORT dataa (837:837:837) (857:857:857)) - (PORT datab (1485:1485:1485) (1542:1542:1542)) - (PORT datac (1608:1608:1608) (1613:1613:1613)) - (PORT datad (1444:1444:1444) (1563:1563:1563)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~5) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (213:213:213) (257:257:257)) - (PORT datac (838:838:838) (870:870:870)) - (PORT datad (195:195:195) (220:220:220)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~6) - (DELAY - (ABSOLUTE - (PORT dataa (222:222:222) (266:266:266)) - (PORT datab (221:221:221) (260:260:260)) - (PORT datac (1070:1070:1070) (1092:1092:1092)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal72\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1402:1402:1402) (1477:1477:1477)) - (PORT datab (2359:2359:2359) (2492:2492:2492)) - (PORT datac (1132:1132:1132) (1171:1171:1171)) - (PORT datad (855:855:855) (857:857:857)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal73\~2) - (DELAY - (ABSOLUTE - (PORT dataa (2002:2002:2002) (2149:2149:2149)) - (PORT datab (1120:1120:1120) (1189:1189:1189)) - (PORT datac (1350:1350:1350) (1403:1403:1403)) - (PORT datad (855:855:855) (872:872:872)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~0) - (DELAY - (ABSOLUTE - (PORT dataa (975:975:975) (1049:1049:1049)) - (PORT datab (960:960:960) (1047:1047:1047)) - (PORT datac (1782:1782:1782) (1803:1803:1803)) - (PORT datad (1450:1450:1450) (1533:1533:1533)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1044:1044:1044) (1059:1059:1059)) - (PORT datab (197:197:197) (237:237:237)) - (PORT datac (616:616:616) (640:640:640)) - (PORT datad (601:601:601) (613:613:613)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1518:1518:1518) (1586:1586:1586)) - (PORT datab (1962:1962:1962) (1991:1991:1991)) - (PORT datac (1263:1263:1263) (1313:1313:1313)) - (PORT datad (933:933:933) (1002:1002:1002)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~3) - (DELAY - (ABSOLUTE - (PORT datab (864:864:864) (893:893:893)) - (PORT datac (819:819:819) (853:853:853)) - (PORT datad (811:811:811) (845:845:845)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (2565:2565:2565) (2704:2704:2704)) - (PORT datac (1529:1529:1529) (1648:1648:1648)) - (PORT datad (1533:1533:1533) (1667:1667:1667)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (248:248:248) (304:304:304)) - (PORT datab (199:199:199) (237:237:237)) - (PORT datac (1176:1176:1176) (1212:1212:1212)) - (PORT datad (191:191:191) (224:224:224)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_nf_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (808:808:808) (859:859:859)) - (PORT datab (618:618:618) (647:647:647)) - (PORT datac (171:171:171) (205:205:205)) - (PORT datad (802:802:802) (881:881:881)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~15) - (DELAY - (ABSOLUTE - (PORT dataa (915:915:915) (957:957:957)) - (PORT datac (824:824:824) (856:856:856)) - (PORT datad (647:647:647) (680:680:680)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~16) - (DELAY - (ABSOLUTE - (PORT dataa (912:912:912) (960:960:960)) - (PORT datab (362:362:362) (394:394:394)) - (PORT datac (591:591:591) (619:619:619)) - (PORT datad (338:338:338) (357:357:357)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~6) - (DELAY - (ABSOLUTE - (PORT datac (891:891:891) (933:933:933)) - (PORT datad (831:831:831) (843:843:843)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~7) - (DELAY - (ABSOLUTE - (PORT dataa (634:634:634) (649:649:649)) - (PORT datab (1105:1105:1105) (1114:1114:1114)) - (PORT datac (753:753:753) (781:781:781)) - (PORT datad (613:613:613) (631:631:631)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (917:917:917) (942:942:942)) - (PORT datab (207:207:207) (249:249:249)) - (PORT datad (195:195:195) (221:221:221)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel_pla12M1T1_12\~0) - (DELAY - (ABSOLUTE - (PORT dataa (2002:2002:2002) (2062:2062:2062)) - (PORT datab (228:228:228) (270:270:270)) - (PORT datac (1707:1707:1707) (1823:1823:1823)) - (PORT datad (1505:1505:1505) (1539:1539:1539)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1137:1137:1137) (1211:1211:1211)) - (PORT datab (1568:1568:1568) (1705:1705:1705)) - (PORT datac (2532:2532:2532) (2663:2663:2663)) - (PORT datad (189:189:189) (222:222:222)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1005:1005:1005) (1063:1063:1063)) - (PORT datab (1299:1299:1299) (1349:1349:1349)) - (PORT datac (890:890:890) (914:914:914)) - (PORT datad (180:180:180) (209:209:209)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_control_\|reg_sys_we_lo\~8) - (DELAY - (ABSOLUTE - (PORT dataa (640:640:640) (665:665:665)) - (PORT datab (2303:2303:2303) (2383:2383:2383)) - (PORT datac (2057:2057:2057) (2199:2199:2199)) - (PORT datad (1163:1163:1163) (1186:1186:1186)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~8) - (DELAY - (ABSOLUTE - (PORT dataa (618:618:618) (640:640:640)) - (PORT datab (608:608:608) (638:638:638)) - (PORT datac (549:549:549) (557:557:557)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1025:1025:1025) (1068:1068:1068)) - (PORT datab (2030:2030:2030) (2166:2166:2166)) - (PORT datac (821:821:821) (831:831:831)) - (PORT datad (2503:2503:2503) (2629:2629:2629)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1546:1546:1546) (1624:1624:1624)) - (PORT datab (938:938:938) (1017:1017:1017)) - (PORT datac (601:601:601) (662:662:662)) - (PORT datad (580:580:580) (585:585:585)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~13) - (DELAY - (ABSOLUTE - (PORT dataa (845:845:845) (920:920:920)) - (PORT datab (220:220:220) (258:258:258)) - (PORT datac (666:666:666) (685:685:685)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~14) - (DELAY - (ABSOLUTE - (PORT dataa (658:658:658) (680:680:680)) - (PORT datab (1172:1172:1172) (1198:1198:1198)) - (PORT datac (636:636:636) (693:693:693)) - (PORT datad (307:307:307) (324:324:324)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_alu\~15) - (DELAY - (ABSOLUTE - (PORT dataa (651:651:651) (694:694:694)) - (PORT datab (806:806:806) (876:876:876)) - (PORT datac (1101:1101:1101) (1130:1130:1130)) - (PORT datad (589:589:589) (627:627:627)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_hilo_nop3pla68M1T3_2) - (DELAY - (ABSOLUTE - (PORT dataa (625:625:625) (667:667:667)) - (PORT datab (654:654:654) (679:679:679)) - (PORT datac (936:936:936) (1033:1033:1033)) - (PORT datad (830:830:830) (861:861:861)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1518:1518:1518) (1588:1588:1588)) - (PORT datab (1051:1051:1051) (1075:1075:1075)) - (PORT datac (1263:1263:1263) (1316:1316:1316)) - (PORT datad (930:930:930) (999:999:999)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1452:1452:1452) (1482:1482:1482)) - (PORT datab (1142:1142:1142) (1181:1181:1181)) - (PORT datac (1196:1196:1196) (1287:1287:1287)) - (PORT datad (1139:1139:1139) (1160:1160:1160)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~1) - (DELAY - (ABSOLUTE - (PORT dataa (631:631:631) (646:646:646)) - (PORT datab (1014:1014:1014) (1076:1076:1076)) - (PORT datac (798:798:798) (807:807:807)) - (PORT datad (619:619:619) (632:632:632)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_5\~2) - (DELAY - (ABSOLUTE - (PORT dataa (230:230:230) (276:276:276)) - (PORT datab (1030:1030:1030) (1067:1067:1067)) - (PORT datac (871:871:871) (866:866:866)) - (PORT datad (599:599:599) (614:614:614)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~7) - (DELAY - (ABSOLUTE - (PORT dataa (583:583:583) (619:619:619)) - (PORT datab (225:225:225) (273:273:273)) - (PORT datac (824:824:824) (846:846:846)) - (PORT datad (1377:1377:1377) (1491:1491:1491)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~9) - (DELAY - (ABSOLUTE - (PORT dataa (780:780:780) (837:837:837)) - (PORT datab (827:827:827) (864:864:864)) - (PORT datac (762:762:762) (835:835:835)) - (PORT datad (767:767:767) (810:810:810)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~10) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf) - (DELAY - (ABSOLUTE - (PORT clk (1511:1511:1511) (1525:1525:1525)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1230:1230:1230) (1277:1277:1277)) - (PORT datab (699:699:699) (755:755:755)) - (PORT datac (917:917:917) (964:964:964)) - (PORT datad (1070:1070:1070) (1101:1101:1101)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_pf_sel_nop3pla68M3T1_20) - (DELAY - (ABSOLUTE - (PORT dataa (625:625:625) (667:667:667)) - (PORT datab (653:653:653) (673:673:673)) - (PORT datac (935:935:935) (1036:1036:1036)) - (PORT datad (387:387:387) (408:408:408)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~10) - (DELAY - (ABSOLUTE - (PORT dataa (971:971:971) (1042:1042:1042)) - (PORT datab (1807:1807:1807) (1835:1835:1835)) - (PORT datac (1262:1262:1262) (1315:1315:1315)) - (PORT datad (1069:1069:1069) (1081:1081:1081)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~8) - (DELAY - (ABSOLUTE - (PORT dataa (2018:2018:2018) (2105:2105:2105)) - (PORT datab (2408:2408:2408) (2537:2537:2537)) - (PORT datac (1381:1381:1381) (1441:1441:1441)) - (PORT datad (1576:1576:1576) (1733:1733:1733)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1517:1517:1517) (1579:1579:1579)) - (PORT datab (385:385:385) (404:404:404)) - (PORT datac (1263:1263:1263) (1308:1308:1308)) - (PORT datad (871:871:871) (923:923:923)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1215:1215:1215) (1269:1269:1269)) - (PORT datab (340:340:340) (375:375:375)) - (PORT datac (1057:1057:1057) (1084:1084:1084)) - (PORT datad (337:337:337) (358:358:358)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~14) - (DELAY - (ABSOLUTE - (PORT dataa (354:354:354) (385:385:385)) - (PORT datab (643:643:643) (665:665:665)) - (PORT datac (169:169:169) (201:201:201)) - (PORT datad (616:616:616) (624:624:624)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~18) - (DELAY - (ABSOLUTE - (PORT dataa (837:837:837) (887:887:887)) - (PORT datab (1118:1118:1118) (1197:1197:1197)) - (PORT datac (848:848:848) (898:898:898)) - (PORT datad (364:364:364) (426:426:426)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_high) - (DELAY - (ABSOLUTE - (PORT dataa (2563:2563:2563) (2705:2705:2705)) - (PORT datab (221:221:221) (260:260:260)) - (PORT datac (1385:1385:1385) (1391:1391:1391)) - (PORT datad (1888:1888:1888) (1980:1980:1980)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|alu_\|alu_op2\[1\]\~1) (DELAY (ABSOLUTE - (PORT dataa (455:455:455) (529:529:529)) - (PORT datab (452:452:452) (522:522:522)) - (PORT datac (877:877:877) (897:897:897)) - (PORT datad (660:660:660) (680:680:680)) - (IOPATH dataa combout (324:324:324) (328:328:328)) + (PORT dataa (592:592:592) (661:661:661)) + (PORT datab (219:219:219) (258:258:258)) + (PORT datac (193:193:193) (226:226:226)) + (PORT datad (549:549:549) (604:604:604)) + (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -19648,12 +17682,28 @@ (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_10\~1) (DELAY (ABSOLUTE - (PORT dataa (546:546:546) (573:573:573)) - (PORT datab (633:633:633) (685:685:685)) - (PORT datac (619:619:619) (639:639:639)) - (PORT datad (630:630:630) (672:672:672)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (337:337:337) (348:348:348)) + (PORT dataa (928:928:928) (972:972:972)) + (PORT datab (872:872:872) (933:933:933)) + (PORT datac (1114:1114:1114) (1134:1134:1134)) + (PORT datad (181:181:181) (209:209:209)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_8\~0) + (DELAY + (ABSOLUTE + (PORT dataa (929:929:929) (977:977:977)) + (PORT datab (877:877:877) (939:939:939)) + (PORT datac (1116:1116:1116) (1138:1138:1138)) + (PORT datad (180:180:180) (207:207:207)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (304:304:304) (311:311:311)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -19661,15 +17711,75 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~9) + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_10\~0) (DELAY (ABSOLUTE - (PORT dataa (815:815:815) (850:850:850)) - (PORT datab (621:621:621) (640:640:640)) - (PORT datac (194:194:194) (228:228:228)) - (PORT datad (182:182:182) (212:212:212)) + (PORT datac (1062:1062:1062) (1104:1104:1104)) + (PORT datad (323:323:323) (344:344:344)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~5) + (DELAY + (ABSOLUTE + (PORT dataa (650:650:650) (685:685:685)) + (PORT datab (974:974:974) (983:983:983)) + (PORT datac (617:617:617) (635:635:635)) + (PORT datad (602:602:602) (621:621:621)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R\~2) + (DELAY + (ABSOLUTE + (PORT dataa (896:896:896) (938:938:938)) + (PORT datab (2096:2096:2096) (2147:2147:2147)) + (PORT datac (1426:1426:1426) (1512:1512:1512)) + (PORT datad (1434:1434:1434) (1483:1483:1483)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_R) + (DELAY + (ABSOLUTE + (PORT dataa (574:574:574) (613:613:613)) + (PORT datab (204:204:204) (244:244:244)) + (PORT datac (1113:1113:1113) (1136:1136:1136)) + (PORT datad (1277:1277:1277) (1367:1367:1367)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[0\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (281:281:281) (354:354:354)) + (PORT datab (277:277:277) (334:334:334)) + (PORT datac (1112:1112:1112) (1121:1121:1121)) + (PORT datad (248:248:248) (292:292:292)) (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab combout (342:342:342) (318:318:318)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -19677,14 +17787,227 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[0\]\~7) + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[0\]) (DELAY (ABSOLUTE - (PORT dataa (811:811:811) (823:823:823)) - (PORT datab (610:610:610) (633:633:633)) - (PORT datac (1092:1092:1092) (1142:1142:1142)) - (PORT datad (895:895:895) (948:948:948)) - (IOPATH dataa combout (304:304:304) (308:308:308)) + (PORT dataa (947:947:947) (977:977:977)) + (PORT datac (896:896:896) (918:918:918)) + (PORT datad (653:653:653) (691:691:691)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_high\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1547:1547:1547) (1549:1549:1549)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[0\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (430:430:430) (459:459:459)) + (PORT datab (951:951:951) (997:997:997)) + (PORT datac (352:352:352) (377:377:377)) + (PORT datad (383:383:383) (450:450:450)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[0\]\~22) + (DELAY + (ABSOLUTE + (PORT datab (857:857:857) (876:876:876)) + (PORT datac (842:842:842) (868:868:868)) + (PORT datad (1187:1187:1187) (1271:1271:1271)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[0\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (911:911:911) (923:923:923)) + (PORT datab (1301:1301:1301) (1338:1338:1338)) + (PORT datad (177:177:177) (203:203:203)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[0\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (665:665:665) (697:697:697)) + (PORT datab (694:694:694) (745:745:745)) + (PORT datac (648:648:648) (667:667:667)) + (PORT datad (175:175:175) (200:200:200)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (280:280:280) (356:356:356)) + (PORT datab (276:276:276) (335:335:335)) + (PORT datac (1112:1112:1112) (1121:1121:1121)) + (PORT datad (243:243:243) (286:286:286)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|result_lo\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT asdata (538:538:538) (569:569:569)) + (PORT ena (1716:1716:1716) (1724:1724:1724)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (613:613:613) (662:662:662)) + (PORT datab (690:690:690) (734:734:734)) + (PORT datac (914:914:914) (939:939:939)) + (PORT datad (848:848:848) (864:864:864)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT datac (885:885:885) (905:905:905)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_low\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1547:1547:1547) (1549:1549:1549)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (794:794:794) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (430:430:430) (457:457:457)) + (PORT datab (613:613:613) (677:677:677)) + (PORT datac (352:352:352) (375:375:375)) + (PORT datad (400:400:400) (463:463:463)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (550:550:550) (573:573:573)) + (PORT datab (593:593:593) (608:608:608)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~1) + (DELAY + (ABSOLUTE + (PORT dataa (816:816:816) (845:845:845)) + (PORT datab (271:271:271) (354:354:354)) + (PORT datac (667:667:667) (748:748:748)) + (PORT datad (824:824:824) (845:845:845)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1142:1142:1142) (1189:1189:1189)) + (PORT datab (845:845:845) (850:850:850)) + (PORT datac (609:609:609) (641:641:641)) + (PORT datad (1844:1844:1844) (1963:1963:1963)) + (IOPATH dataa combout (324:324:324) (328:328:328)) (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -19693,11 +18016,216 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[0\]\~8) + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~3) (DELAY (ABSOLUTE - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (232:232:232) (287:287:287)) + (PORT dataa (2483:2483:2483) (2607:2607:2607)) + (PORT datab (1066:1066:1066) (1107:1107:1107)) + (PORT datac (372:372:372) (395:395:395)) + (PORT datad (1729:1729:1729) (1766:1766:1766)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (223:223:223) (268:268:268)) + (PORT datab (1935:1935:1935) (1992:1992:1992)) + (PORT datac (889:889:889) (926:926:926)) + (PORT datad (1141:1141:1141) (1182:1182:1182)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~5) + (DELAY + (ABSOLUTE + (PORT dataa (209:209:209) (255:255:255)) + (PORT datab (1226:1226:1226) (1278:1278:1278)) + (PORT datac (218:218:218) (263:263:263)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (254:254:254)) + (PORT datab (206:206:206) (247:247:247)) + (PORT datac (172:172:172) (204:204:204)) + (PORT datad (593:593:593) (595:595:595)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~0) + (DELAY + (ABSOLUTE + (PORT dataa (812:812:812) (841:841:841)) + (PORT datab (872:872:872) (895:895:895)) + (PORT datac (209:209:209) (250:250:250)) + (PORT datad (598:598:598) (653:653:653)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~1) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (244:244:244)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datad (196:196:196) (222:222:222)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1086:1086:1086) (1145:1145:1145)) + (PORT datab (270:270:270) (354:354:354)) + (PORT datac (858:858:858) (939:939:939)) + (PORT datad (1180:1180:1180) (1263:1263:1263)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~2) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (1056:1056:1056) (1107:1107:1107)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (847:847:847) (876:876:876)) + (PORT datab (206:206:206) (248:248:248)) + (PORT datad (1179:1179:1179) (1266:1266:1266)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (725:725:725) (788:788:788)) + (PORT datab (1120:1120:1120) (1167:1167:1167)) + (PORT datac (602:602:602) (610:610:610)) + (PORT datad (808:808:808) (828:828:828)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (336:336:336) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[0\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (694:694:694) (718:718:718)) + (PORT datab (205:205:205) (247:247:247)) + (PORT datac (693:693:693) (747:747:747)) + (PORT datad (665:665:665) (701:701:701)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1097:1097:1097) (1131:1131:1131)) + (PORT datab (956:956:956) (1006:1006:1006)) + (PORT datac (541:541:541) (541:541:541)) + (PORT datad (583:583:583) (644:644:644)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (666:666:666) (698:698:698)) + (PORT datab (911:911:911) (937:937:937)) + (PORT datac (934:934:934) (954:954:954)) + (PORT datad (325:325:325) (339:339:339)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -19705,10 +18233,10 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_high\[0\]) + (INSTANCE z80_\|alu_\|op2_low\[0\]) (DELAY (ABSOLUTE - (PORT clk (1529:1529:1529) (1531:1531:1531)) + (PORT clk (1535:1535:1535) (1540:1540:1540)) (PORT d (74:74:74) (91:91:91)) (PORT ena (819:819:819) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) @@ -19724,60 +18252,26 @@ (INSTANCE z80_\|alu_\|alu_op2\[0\]\~3) (DELAY (ABSOLUTE - (PORT dataa (432:432:432) (521:521:521)) - (PORT datab (682:682:682) (739:739:739)) - (PORT datac (877:877:877) (897:897:897)) - (PORT datad (660:660:660) (685:685:685)) + (PORT dataa (405:405:405) (486:486:486)) + (PORT datab (405:405:405) (430:430:430)) + (PORT datac (618:618:618) (634:634:634)) + (PORT datad (395:395:395) (460:460:460)) (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_nf\~12) - (DELAY - (ABSOLUTE - (PORT dataa (862:862:862) (922:922:922)) - (PORT datab (224:224:224) (269:269:269)) - (PORT datac (826:826:826) (848:848:848)) - (PORT datad (904:904:904) (974:974:974)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_S\~8) - (DELAY - (ABSOLUTE - (PORT dataa (786:786:786) (842:842:842)) - (PORT datab (197:197:197) (237:237:237)) - (PORT datac (1821:1821:1821) (1815:1815:1815)) - (PORT datad (790:790:790) (826:826:826)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_1) (DELAY (ABSOLUTE - (PORT dataa (684:684:684) (706:706:706)) - (PORT datab (1772:1772:1772) (1798:1798:1798)) - (PORT datac (179:179:179) (214:214:214)) - (PORT datad (823:823:823) (837:837:837)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (332:332:332)) + (PORT dataa (1101:1101:1101) (1146:1146:1146)) + (PORT datac (1094:1094:1094) (1114:1114:1114)) + (PORT datad (181:181:181) (210:210:210)) + (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -19785,31 +18279,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~21) + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla26M3T5_8) (DELAY (ABSOLUTE - (PORT dataa (2390:2390:2390) (2544:2544:2544)) - (PORT datab (1497:1497:1497) (1581:1581:1581)) - (PORT datac (874:874:874) (897:897:897)) - (PORT datad (1014:1014:1014) (1128:1128:1128)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~22) - (DELAY - (ABSOLUTE - (PORT dataa (578:578:578) (605:605:605)) - (PORT datab (974:974:974) (1056:1056:1056)) - (PORT datac (672:672:672) (715:715:715)) - (PORT datad (819:819:819) (820:820:820)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (300:300:300) (308:308:308)) + (PORT datab (930:930:930) (1046:1046:1046)) + (PORT datac (826:826:826) (869:869:869)) + (PORT datad (1304:1304:1304) (1448:1448:1448)) + (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -19817,45 +18293,45 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~19) + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~14) (DELAY (ABSOLUTE - (PORT dataa (987:987:987) (1039:1039:1039)) - (PORT datab (434:434:434) (474:474:474)) - (PORT datac (947:947:947) (1015:1015:1015)) - (PORT datad (1175:1175:1175) (1235:1235:1235)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~27) - (DELAY - (ABSOLUTE - (PORT dataa (238:238:238) (285:285:285)) - (PORT datab (222:222:222) (261:261:261)) - (PORT datac (194:194:194) (228:228:228)) - (PORT datad (208:208:208) (238:238:238)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~29) - (DELAY - (ABSOLUTE - (PORT datab (229:229:229) (278:278:278)) - (PORT datac (193:193:193) (235:235:235)) - (PORT datad (374:374:374) (396:396:396)) + (PORT dataa (3085:3085:3085) (3152:3152:3152)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (1680:1680:1680) (1768:1768:1768)) + (PORT datad (826:826:826) (854:854:854)) + (IOPATH dataa combout (303:303:303) (299:299:299)) (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1331:1331:1331) (1419:1419:1419)) + (PORT datac (588:588:588) (638:638:638)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1646:1646:1646) (1724:1724:1724)) + (PORT datab (1909:1909:1909) (1995:1995:1995)) + (PORT datac (1136:1136:1136) (1198:1198:1198)) + (PORT datad (1428:1428:1428) (1497:1497:1497)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -19863,13 +18339,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~23) + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~17) (DELAY (ABSOLUTE - (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (639:639:639) (661:661:661)) - (PORT datac (172:172:172) (204:204:204)) - (PORT datad (195:195:195) (220:220:220)) + (PORT dataa (198:198:198) (240:240:240)) + (PORT datab (631:631:631) (669:669:669)) + (PORT datac (206:206:206) (246:246:246)) + (PORT datad (892:892:892) (940:940:940)) (IOPATH dataa combout (354:354:354) (349:349:349)) (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -19879,13 +18355,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~37) + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~44) (DELAY (ABSOLUTE - (PORT datab (1269:1269:1269) (1380:1380:1380)) - (PORT datac (901:901:901) (917:917:917)) - (PORT datad (1177:1177:1177) (1191:1191:1191)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT dataa (405:405:405) (433:433:433)) + (PORT datab (237:237:237) (282:282:282)) + (PORT datac (611:611:611) (637:637:637)) + (PORT datad (591:591:591) (612:612:612)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~20) + (DELAY + (ABSOLUTE + (PORT dataa (1646:1646:1646) (1723:1723:1723)) + (PORT datab (1128:1128:1128) (1211:1211:1211)) + (PORT datac (1136:1136:1136) (1198:1198:1198)) + (PORT datad (1429:1429:1429) (1497:1497:1497)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -19893,15 +18387,79 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~38) + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~21) (DELAY (ABSOLUTE - (PORT dataa (1285:1285:1285) (1340:1340:1340)) - (PORT datab (1007:1007:1007) (1075:1075:1075)) - (PORT datac (1456:1456:1456) (1496:1496:1496)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (304:304:304) (308:308:308)) + (PORT dataa (228:228:228) (276:276:276)) + (PORT datab (1127:1127:1127) (1211:1211:1211)) + (PORT datac (973:973:973) (1038:1038:1038)) + (PORT datad (172:172:172) (198:198:198)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~18) + (DELAY + (ABSOLUTE + (PORT dataa (924:924:924) (993:993:993)) + (PORT datab (1226:1226:1226) (1276:1276:1276)) + (PORT datac (2112:2112:2112) (2204:2204:2204)) + (PORT datad (1660:1660:1660) (1676:1676:1676)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~19) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (265:265:265)) + (PORT datab (245:245:245) (293:293:293)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (210:210:210) (243:243:243)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~22) + (DELAY + (ABSOLUTE + (PORT dataa (223:223:223) (267:267:267)) + (PORT datab (238:238:238) (283:283:283)) + (PORT datac (591:591:591) (637:637:637)) + (PORT datad (623:623:623) (638:638:638)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~43) + (DELAY + (ABSOLUTE + (PORT dataa (660:660:660) (718:718:718)) + (PORT datab (963:963:963) (1006:1006:1006)) + (PORT datac (1606:1606:1606) (1643:1643:1643)) + (PORT datad (613:613:613) (630:630:630)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -19912,13 +18470,13 @@ (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~24) (DELAY (ABSOLUTE - (PORT dataa (2050:2050:2050) (2087:2087:2087)) - (PORT datab (943:943:943) (1022:1022:1022)) - (PORT datac (1211:1211:1211) (1239:1239:1239)) - (PORT datad (1083:1083:1083) (1126:1126:1126)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (1252:1252:1252) (1300:1300:1300)) + (PORT datab (1028:1028:1028) (1085:1085:1085)) + (PORT datac (3027:3027:3027) (3057:3057:3057)) + (PORT datad (1455:1455:1455) (1504:1504:1504)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -19928,156 +18486,12 @@ (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~25) (DELAY (ABSOLUTE - (PORT dataa (923:923:923) (949:949:949)) - (PORT datab (1060:1060:1060) (1085:1085:1085)) - (PORT datac (892:892:892) (934:934:934)) - (PORT datad (568:568:568) (571:571:571)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~26) - (DELAY - (ABSOLUTE - (PORT dataa (1490:1490:1490) (1592:1592:1592)) - (PORT datab (438:438:438) (472:472:472)) - (PORT datac (945:945:945) (997:997:997)) - (PORT datad (1178:1178:1178) (1233:1233:1233)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~27) - (DELAY - (ABSOLUTE - (PORT dataa (1493:1493:1493) (1597:1597:1597)) - (PORT datab (234:234:234) (278:278:278)) - (PORT datac (2021:2021:2021) (2050:2050:2050)) + (PORT dataa (941:941:941) (975:975:975)) + (PORT datab (1204:1204:1204) (1270:1270:1270)) + (PORT datac (896:896:896) (940:940:940)) (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~28) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (220:220:220) (259:259:259)) - (PORT datac (609:609:609) (638:638:638)) - (PORT datad (194:194:194) (220:220:220)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~30) - (DELAY - (ABSOLUTE - (PORT dataa (209:209:209) (258:258:258)) - (PORT datab (218:218:218) (256:256:256)) - (PORT datac (817:817:817) (862:862:862)) - (PORT datad (554:554:554) (572:572:572)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~34) - (DELAY - (ABSOLUTE - (PORT dataa (1462:1462:1462) (1525:1525:1525)) - (PORT datab (1404:1404:1404) (1424:1424:1424)) - (PORT datac (1574:1574:1574) (1618:1618:1618)) - (PORT datad (1065:1065:1065) (1079:1079:1079)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~32) - (DELAY - (ABSOLUTE - (PORT dataa (734:734:734) (759:759:759)) - (PORT datab (699:699:699) (730:730:730)) - (PORT datac (1599:1599:1599) (1604:1604:1604)) - (PORT datad (1436:1436:1436) (1479:1479:1479)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~43) - (DELAY - (ABSOLUTE - (PORT dataa (1343:1343:1343) (1425:1425:1425)) - (PORT datab (1086:1086:1086) (1110:1110:1110)) - (PORT datac (1574:1574:1574) (1614:1614:1614)) - (PORT datad (1794:1794:1794) (1911:1911:1911)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~33) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (843:843:843) (880:880:880)) - (PORT datac (1602:1602:1602) (1608:1608:1608)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~42) - (DELAY - (ABSOLUTE - (PORT dataa (837:837:837) (867:867:867)) - (PORT datab (1092:1092:1092) (1116:1116:1116)) - (PORT datac (2113:2113:2113) (2219:2219:2219)) - (PORT datad (1789:1789:1789) (1904:1904:1904)) (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -20088,90 +18502,10 @@ (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~35) (DELAY (ABSOLUTE - (PORT dataa (199:199:199) (242:242:242)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (1016:1016:1016) (1027:1027:1027)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~41) - (DELAY - (ABSOLUTE - (PORT dataa (675:675:675) (702:702:702)) - (PORT datab (2051:2051:2051) (2134:2134:2134)) - (PORT datac (1486:1486:1486) (1540:1540:1540)) - (PORT datad (1327:1327:1327) (1454:1454:1454)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~30) - (DELAY - (ABSOLUTE - (PORT dataa (1519:1519:1519) (1580:1580:1580)) - (PORT datab (1960:1960:1960) (1986:1986:1986)) - (PORT datac (1263:1263:1263) (1313:1313:1313)) - (PORT datad (869:869:869) (922:922:922)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1748:1748:1748) (1872:1872:1872)) - (PORT datab (1028:1028:1028) (1083:1083:1083)) - (PORT datac (199:199:199) (235:235:235)) - (PORT datad (1506:1506:1506) (1541:1541:1541)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~31) - (DELAY - (ABSOLUTE - (PORT dataa (1165:1165:1165) (1194:1194:1194)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (1359:1359:1359) (1382:1382:1382)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~44) - (DELAY - (ABSOLUTE - (PORT dataa (819:819:819) (841:841:841)) - (PORT datab (1818:1818:1818) (1968:1968:1968)) - (PORT datac (1306:1306:1306) (1386:1386:1386)) - (PORT datad (1794:1794:1794) (1911:1911:1911)) + (PORT dataa (2133:2133:2133) (2251:2251:2251)) + (PORT datab (2062:2062:2062) (2161:2161:2161)) + (PORT datac (1557:1557:1557) (1656:1656:1656)) + (PORT datad (1125:1125:1125) (1129:1129:1129)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -20179,18 +18513,130 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~23) + (DELAY + (ABSOLUTE + (PORT dataa (224:224:224) (279:279:279)) + (PORT datab (1030:1030:1030) (1085:1085:1085)) + (PORT datac (575:575:575) (587:587:587)) + (PORT datad (847:847:847) (867:867:867)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~26) + (DELAY + (ABSOLUTE + (PORT dataa (1451:1451:1451) (1458:1458:1458)) + (PORT datab (1101:1101:1101) (1148:1148:1148)) + (PORT datac (1380:1380:1380) (1467:1467:1467)) + (PORT datad (908:908:908) (950:950:950)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~34) + (DELAY + (ABSOLUTE + (PORT dataa (2559:2559:2559) (2697:2697:2697)) + (PORT datab (1483:1483:1483) (1515:1515:1515)) + (PORT datac (1449:1449:1449) (1537:1537:1537)) + (PORT datad (913:913:913) (966:966:966)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~27) + (DELAY + (ABSOLUTE + (PORT dataa (745:745:745) (816:816:816)) + (PORT datab (1711:1711:1711) (1759:1759:1759)) + (PORT datac (862:862:862) (891:891:891)) + (PORT datad (1925:1925:1925) (2095:2095:2095)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~28) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (246:246:246)) + (PORT datab (939:939:939) (1037:1037:1037)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (1925:1925:1925) (2098:2098:2098)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~29) + (DELAY + (ABSOLUTE + (PORT dataa (988:988:988) (1052:1052:1052)) + (PORT datab (893:893:893) (923:923:923)) + (PORT datac (1450:1450:1450) (1477:1477:1477)) + (PORT datad (1671:1671:1671) (1723:1723:1723)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~30) (DELAY (ABSOLUTE (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (699:699:699) (733:733:733)) - (PORT datac (862:862:862) (901:901:901)) - (PORT datad (693:693:693) (717:717:717)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (1120:1120:1120) (1150:1150:1150)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~31) + (DELAY + (ABSOLUTE + (PORT dataa (610:610:610) (634:634:634)) + (PORT datab (196:196:196) (234:234:234)) + (PORT datac (171:171:171) (205:205:205)) + (PORT datad (607:607:607) (619:619:619)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -20200,28 +18646,10 @@ (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~36) (DELAY (ABSOLUTE - (PORT dataa (532:532:532) (551:551:551)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (641:641:641) (659:659:659)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~39) - (DELAY - (ABSOLUTE - (PORT dataa (593:593:593) (620:620:620)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (603:603:603) (622:622:622)) - (PORT datad (345:345:345) (359:359:359)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) + (PORT dataa (1280:1280:1280) (1375:1375:1375)) + (PORT datac (1673:1673:1673) (1738:1738:1738)) + (PORT datad (1996:1996:1996) (2055:2055:2055)) + (IOPATH dataa combout (354:354:354) (367:367:367)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -20229,47 +18657,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~40) + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~37) (DELAY (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (917:917:917) (956:956:956)) - (PORT datac (193:193:193) (226:226:226)) - (PORT datad (317:317:317) (337:337:337)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1666:1666:1666) (1754:1754:1754)) - (PORT datab (1416:1416:1416) (1493:1493:1493)) - (PORT datac (639:639:639) (659:659:659)) - (PORT datad (847:847:847) (875:875:875)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1450:1450:1450) (1506:1506:1506)) - (PORT datab (849:849:849) (859:859:859)) - (PORT datac (836:836:836) (864:864:864)) - (PORT datad (1389:1389:1389) (1423:1423:1423)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) + (PORT dataa (1418:1418:1418) (1478:1478:1478)) + (PORT datab (1638:1638:1638) (1708:1708:1708)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (1247:1247:1247) (1293:1293:1293)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -20277,314 +18673,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R) + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~32) (DELAY (ABSOLUTE - (PORT dataa (831:831:831) (869:869:869)) - (PORT datab (1772:1772:1772) (1798:1798:1798)) - (PORT datac (618:618:618) (638:638:638)) - (PORT datad (822:822:822) (837:837:837)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[3\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1198:1198:1198) (1248:1248:1248)) - (PORT datab (223:223:223) (268:268:268)) - (PORT datac (914:914:914) (947:947:947)) - (PORT datad (607:607:607) (631:631:631)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[3\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (263:263:263) (334:334:334)) - (PORT datab (944:944:944) (991:991:991)) - (PORT datac (535:535:535) (545:545:545)) - (PORT datad (1139:1139:1139) (1125:1125:1125)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_high\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[3\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (596:596:596) (673:673:673)) - (PORT datab (1125:1125:1125) (1173:1173:1173)) - (PORT datac (583:583:583) (615:615:615)) - (PORT datad (389:389:389) (443:443:443)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[3\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (263:263:263) (340:340:340)) - (PORT datab (199:199:199) (239:239:239)) - (PORT datac (559:559:559) (583:583:583)) - (PORT datad (901:901:901) (948:948:948)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_low\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op2\[3\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (423:423:423) (511:511:511)) - (PORT datab (419:419:419) (499:499:499)) - (PORT datac (878:878:878) (901:901:901)) - (PORT datad (657:657:657) (678:678:678)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|SYNTHESIZED_WIRE_10\~1) - (DELAY - (ABSOLUTE - (PORT dataa (207:207:207) (253:253:253)) - (PORT datab (638:638:638) (659:659:659)) - (PORT datac (355:355:355) (378:378:378)) - (PORT datad (830:830:830) (837:837:837)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|SYNTHESIZED_WIRE_10\~0) - (DELAY - (ABSOLUTE - (PORT dataa (390:390:390) (419:419:419)) - (PORT datab (653:653:653) (711:711:711)) - (PORT datac (647:647:647) (707:707:707)) - (PORT datad (635:635:635) (659:659:659)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|cy_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (413:413:413) (443:443:443)) - (PORT datab (239:239:239) (284:284:284)) - (PORT datac (181:181:181) (218:218:218)) - (PORT datad (180:180:180) (208:208:208)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf\~0) - (DELAY - (ABSOLUTE - (PORT dataa (709:709:709) (742:742:742)) - (PORT datab (1178:1178:1178) (1274:1274:1274)) - (PORT datac (855:855:855) (865:865:865)) - (PORT datad (674:674:674) (693:693:693)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1304:1304:1304) (1358:1358:1358)) - (PORT datab (1962:1962:1962) (1990:1990:1990)) - (PORT datac (1486:1486:1486) (1545:1545:1545)) - (PORT datad (1495:1495:1495) (1557:1557:1557)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1144:1144:1144) (1179:1179:1179)) - (PORT datab (609:609:609) (638:638:638)) - (PORT datac (820:820:820) (842:842:842)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf\~1) - (DELAY - (ABSOLUTE - (PORT dataa (209:209:209) (257:257:257)) + (PORT dataa (199:199:199) (242:242:242)) (PORT datab (196:196:196) (235:235:235)) - (PORT datad (798:798:798) (805:805:805)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (815:815:815) (832:832:832)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_core_hf\~33) + (DELAY + (ABSOLUTE + (PORT dataa (349:349:349) (384:384:384)) + (PORT datab (972:972:972) (1035:1035:1035)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (603:603:603) (650:650:650)) (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf) - (DELAY - (ABSOLUTE - (PORT clk (1514:1514:1514) (1528:1528:1528)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1152:1152:1152) (1175:1175:1175)) - (PORT datac (567:567:567) (576:576:576)) - (PORT datad (1627:1627:1627) (1703:1703:1703)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~12) - (DELAY - (ABSOLUTE - (PORT dataa (919:919:919) (927:927:927)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (1829:1829:1829) (1911:1911:1911)) - (PORT datad (562:562:562) (570:570:570)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_hf_cpl\~13) - (DELAY - (ABSOLUTE - (PORT dataa (378:378:378) (415:415:415)) - (PORT datab (2086:2086:2086) (2229:2229:2229)) - (PORT datac (1314:1314:1314) (1402:1402:1402)) - (PORT datad (902:902:902) (968:968:968)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|flags_hf) - (DELAY - (ABSOLUTE - (PORT dataa (385:385:385) (462:462:462)) - (PORT datab (612:612:612) (633:633:633)) - (PORT datac (1175:1175:1175) (1235:1235:1235)) - (PORT datad (822:822:822) (844:844:844)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (337:337:337) (348:348:348)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -20595,9 +18708,23 @@ (INSTANCE z80_\|alu_control_\|alu_core_cf_in\~0) (DELAY (ABSOLUTE - (PORT dataa (572:572:572) (597:597:597)) - (PORT datab (615:615:615) (638:638:638)) - (PORT datad (567:567:567) (574:574:574)) + (PORT dataa (637:637:637) (672:672:672)) + (PORT datab (848:848:848) (872:872:872)) + (PORT datac (845:845:845) (855:855:855)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op1\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1096:1096:1096) (1133:1133:1133)) + (PORT datab (951:951:951) (1001:1001:1001)) + (PORT datad (578:578:578) (641:641:641)) (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -20609,10 +18736,10 @@ (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|result\~0) (DELAY (ABSOLUTE - (PORT dataa (660:660:660) (685:685:685)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (807:807:807) (808:808:808)) - (PORT datad (203:203:203) (232:232:232)) + (PORT dataa (199:199:199) (241:241:241)) + (PORT datab (196:196:196) (235:235:235)) + (PORT datac (1034:1034:1034) (1067:1067:1067)) + (PORT datad (180:180:180) (207:207:207)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (243:243:243) (242:242:242)) @@ -20620,735 +18747,17 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (1698:1698:1698) (1789:1789:1789)) - (PORT datab (919:919:919) (952:952:952)) - (PORT datac (888:888:888) (909:909:909)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[12\]) - (DELAY - (ABSOLUTE - (PORT datab (403:403:403) (448:448:448)) - (PORT datac (885:885:885) (915:915:915)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|Q\[12\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (314:314:314) (333:333:333)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[12\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1581:1581:1581) (1561:1561:1561)) - (PORT ena (2058:2058:2058) (2109:2109:2109)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|d0_out) - (DELAY - (ABSOLUTE - (PORT dataa (625:625:625) (638:638:638)) - (PORT datab (903:903:903) (926:926:926)) - (PORT datac (240:240:240) (327:327:327)) - (PORT datad (577:577:577) (639:639:639)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1308:1308:1308) (1303:1303:1303)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1535:1535:1535) (1554:1554:1554)) - (PORT asdata (1270:1270:1270) (1318:1318:1318)) - (PORT ena (935:935:935) (924:924:924)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (410:410:410) (460:460:460)) - (PORT datab (412:412:412) (448:448:448)) - (PORT datad (194:194:194) (218:218:218)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (674:674:674) (717:717:717)) - (PORT datac (216:216:216) (293:293:293)) - (PORT datad (775:775:775) (807:807:807)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (391:391:391) (418:418:418)) - (PORT datab (838:838:838) (875:875:875)) - (PORT datac (679:679:679) (721:721:721)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1534:1534:1534)) - (PORT asdata (2041:2041:2041) (2053:2053:2053)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~62) - (DELAY - (ABSOLUTE - (PORT dataa (409:409:409) (437:437:437)) - (PORT datab (1165:1165:1165) (1216:1216:1216)) - (PORT datad (739:739:739) (751:751:751)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1535:1535:1535) (1554:1554:1554)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1461:1461:1461) (1468:1468:1468)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1534:1534:1534)) - (PORT asdata (2041:2041:2041) (2050:2050:2050)) - (PORT ena (1236:1236:1236) (1273:1273:1273)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~63) - (DELAY - (ABSOLUTE - (PORT dataa (692:692:692) (780:780:780)) - (PORT datab (884:884:884) (909:909:909)) - (PORT datad (866:866:866) (902:902:902)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (1376:1376:1376) (1427:1427:1427)) - (PORT ena (1214:1214:1214) (1210:1210:1210)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (1376:1376:1376) (1429:1429:1429)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~61) - (DELAY - (ABSOLUTE - (PORT dataa (905:905:905) (945:945:945)) - (PORT datab (244:244:244) (290:290:290)) - (PORT datad (216:216:216) (284:284:284)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[4\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1394:1394:1394) (1418:1418:1418)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1193:1193:1193) (1176:1176:1176)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (1721:1721:1721) (1742:1742:1742)) - (PORT ena (1283:1283:1283) (1283:1283:1283)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~60) - (DELAY - (ABSOLUTE - (PORT dataa (392:392:392) (467:467:467)) - (PORT datab (1593:1593:1593) (1645:1645:1645)) - (PORT datad (1180:1180:1180) (1215:1215:1215)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~64) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (809:809:809) (810:810:810)) - (PORT datad (610:610:610) (622:622:622)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (1872:1872:1872) (1943:1943:1943)) - (PORT ena (1388:1388:1388) (1427:1427:1427)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (1872:1872:1872) (1942:1942:1942)) - (PORT ena (1400:1400:1400) (1413:1413:1413)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~59) - (DELAY - (ABSOLUTE - (PORT dataa (932:932:932) (991:991:991)) - (PORT datab (912:912:912) (981:981:981)) - (PORT datad (215:215:215) (283:283:283)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1537:1537:1537)) - (PORT asdata (1938:1938:1938) (1952:1952:1952)) - (PORT ena (990:990:990) (994:994:994)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1537:1537:1537)) - (PORT asdata (1936:1936:1936) (1952:1952:1952)) - (PORT ena (973:973:973) (964:964:964)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~58) - (DELAY - (ABSOLUTE - (PORT dataa (466:466:466) (519:519:519)) - (PORT datab (492:492:492) (537:537:537)) - (PORT datad (217:217:217) (284:284:284)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (1867:1867:1867) (1935:1935:1935)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[4\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (930:930:930) (988:988:988)) - (PORT datab (1221:1221:1221) (1295:1295:1295)) - (PORT datad (887:887:887) (943:943:943)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~65) - (DELAY - (ABSOLUTE - (PORT dataa (644:644:644) (697:697:697)) - (PORT datab (331:331:331) (360:360:360)) - (PORT datac (577:577:577) (594:594:594)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~66) - (DELAY - (ABSOLUTE - (PORT dataa (883:883:883) (947:947:947)) - (PORT datab (844:844:844) (916:916:916)) - (PORT datac (840:840:840) (851:851:851)) - (PORT datad (1298:1298:1298) (1335:1335:1335)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[4\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1304:1304:1304) (1356:1356:1356)) - (PORT datab (968:968:968) (1024:1024:1024)) - (PORT datac (891:891:891) (908:908:908)) - (PORT datad (1445:1445:1445) (1454:1454:1454)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[7\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (1289:1289:1289) (1337:1337:1337)) - (PORT datab (1225:1225:1225) (1251:1251:1251)) - (PORT datac (904:904:904) (947:947:947)) - (PORT datad (928:928:928) (986:986:986)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[4\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (206:206:206) (251:251:251)) - (PORT datab (249:249:249) (305:305:305)) - (PORT datac (1067:1067:1067) (1064:1064:1064)) - (PORT datad (949:949:949) (996:996:996)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1286:1286:1286) (1354:1354:1354)) - (PORT datab (933:933:933) (990:990:990)) - (PORT datac (372:372:372) (402:402:402)) - (PORT datad (1200:1200:1200) (1314:1314:1314)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1111:1111:1111) (1230:1230:1230)) - (PORT datab (1831:1831:1831) (1921:1921:1921)) - (PORT datac (881:881:881) (935:935:935)) - (PORT datad (1554:1554:1554) (1661:1661:1661)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_shift\~4) - (DELAY - (ABSOLUTE - (PORT dataa (923:923:923) (987:987:987)) - (PORT datab (637:637:637) (672:672:672)) - (PORT datac (1395:1395:1395) (1470:1470:1470)) - (PORT datad (580:580:580) (617:617:617)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (204:204:204) (249:249:249)) - (PORT datac (935:935:935) (965:965:965)) - (PORT datad (241:241:241) (282:282:282)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1179:1179:1179) (1212:1212:1212)) - (PORT datab (290:290:290) (355:355:355)) - (PORT datac (254:254:254) (314:314:314)) - (PORT datad (246:246:246) (292:292:292)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_high\|Q\[0\]) - (DELAY - (ABSOLUTE - (PORT datab (359:359:359) (395:395:395)) - (PORT datac (927:927:927) (982:982:982)) - (PORT datad (676:676:676) (714:714:714)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_high\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (636:636:636) (695:695:695)) - (PORT datab (1175:1175:1175) (1218:1218:1218)) - (PORT datac (649:649:649) (707:707:707)) - (PORT datad (660:660:660) (719:719:719)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|alu_\|db_high\[0\]\~25) (DELAY (ABSOLUTE - (PORT dataa (598:598:598) (629:629:629)) - (PORT datab (329:329:329) (356:356:356)) - (PORT datac (1163:1163:1163) (1203:1203:1203)) - (PORT datad (530:530:530) (548:548:548)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[0\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (645:645:645) (679:679:679)) - (PORT datab (998:998:998) (1032:1032:1032)) - (PORT datac (172:172:172) (204:204:204)) - (PORT datad (220:220:220) (263:263:263)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[0\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (594:594:594) (621:621:621)) - (PORT datab (963:963:963) (1009:1009:1009)) - (PORT datac (864:864:864) (907:907:907)) - (PORT datad (337:337:337) (357:357:357)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[0\]\~8) - (DELAY - (ABSOLUTE - (PORT datac (173:173:173) (206:206:206)) - (PORT datad (674:674:674) (713:713:713)) + (PORT dataa (370:370:370) (393:393:393)) + (PORT datab (376:376:376) (407:407:407)) + (PORT datac (840:840:840) (893:893:893)) + (PORT datad (1078:1078:1078) (1078:1078:1078)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -21356,59 +18765,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|ena) + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[0\]\~6) (DELAY (ABSOLUTE - (PORT dataa (903:903:903) (963:963:963)) - (PORT datab (719:719:719) (762:762:762)) - (PORT datac (929:929:929) (980:980:980)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_low\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op1\[0\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (647:647:647) (678:678:678)) - (PORT datab (640:640:640) (697:697:697)) - (PORT datac (608:608:608) (646:646:646)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[0\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (620:620:620) (648:648:648)) - (PORT datab (935:935:935) (984:984:984)) - (PORT datac (1093:1093:1093) (1149:1149:1149)) - (PORT datad (575:575:575) (595:595:595)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (306:306:306) (311:311:311)) + (PORT dataa (651:651:651) (667:667:667)) + (PORT datab (655:655:655) (679:679:679)) + (PORT datac (919:919:919) (940:940:940)) + (PORT datad (625:625:625) (655:655:655)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -21416,22 +18781,22 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[0\]\~7) + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[0\]\~7) (DELAY (ABSOLUTE - (PORT dataa (263:263:263) (339:339:339)) - (PORT datac (171:171:171) (204:204:204)) - (IOPATH dataa combout (356:356:356) (368:368:368)) + (PORT datab (911:911:911) (939:939:939)) + (PORT datac (173:173:173) (206:206:206)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (242:242:242)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_low\[0\]) + (INSTANCE z80_\|alu_\|op2_high\[0\]) (DELAY (ABSOLUTE - (PORT clk (1529:1529:1529) (1531:1531:1531)) + (PORT clk (1535:1535:1535) (1540:1540:1540)) (PORT d (74:74:74) (91:91:91)) (PORT ena (819:819:819) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) @@ -21447,11 +18812,11 @@ (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_10\~0) (DELAY (ABSOLUTE - (PORT dataa (431:431:431) (524:524:524)) - (PORT datac (650:650:650) (711:711:711)) - (PORT datad (658:658:658) (684:684:684)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (408:408:408) (491:491:491)) + (PORT datab (402:402:402) (430:430:430)) + (PORT datad (398:398:398) (464:464:464)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -21461,10 +18826,10 @@ (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|SYNTHESIZED_WIRE_10\~1) (DELAY (ABSOLUTE - (PORT dataa (592:592:592) (600:600:600)) - (PORT datab (826:826:826) (830:830:830)) - (PORT datac (805:805:805) (806:806:806)) - (PORT datad (202:202:202) (231:231:231)) + (PORT dataa (653:653:653) (673:673:673)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (1033:1033:1033) (1067:1067:1067)) + (PORT datad (180:180:180) (209:209:209)) (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (242:242:242)) @@ -21477,5139 +18842,27 @@ (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_0\|cy_out\~0) (DELAY (ABSOLUTE - (PORT dataa (688:688:688) (712:712:712)) - (PORT datab (207:207:207) (248:248:248)) - (PORT datac (203:203:203) (240:240:240)) - (PORT datad (818:818:818) (831:831:831)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op1\[1\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (649:649:649) (676:676:676)) - (PORT datab (632:632:632) (684:684:684)) - (PORT datad (630:630:630) (672:672:672)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_10\~0) - (DELAY - (ABSOLUTE - (PORT dataa (683:683:683) (704:704:704)) - (PORT datab (860:860:860) (876:876:876)) - (PORT datac (181:181:181) (218:218:218)) - (PORT datad (515:515:515) (526:526:526)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (206:206:206) (252:252:252)) - (PORT datab (213:213:213) (257:257:257)) - (PORT datac (201:201:201) (238:238:238)) - (PORT datad (182:182:182) (212:212:212)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_op1\[2\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (632:632:632) (690:690:690)) - (PORT datab (662:662:662) (696:696:696)) - (PORT datad (604:604:604) (655:655:655)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_10\~1) - (DELAY - (ABSOLUTE - (PORT dataa (369:369:369) (405:405:405)) - (PORT datab (638:638:638) (659:659:659)) - (PORT datac (180:180:180) (216:216:216)) - (PORT datad (830:830:830) (837:837:837)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|cy_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (387:387:387) (410:410:410)) - (PORT datab (394:394:394) (423:423:423)) - (PORT datac (177:177:177) (214:214:214)) - (PORT datad (368:368:368) (390:390:390)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_core_R\~5) - (DELAY - (ABSOLUTE - (PORT datac (1740:1740:1740) (1766:1766:1766)) - (PORT datad (822:822:822) (836:836:836)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|SYNTHESIZED_WIRE_1) - (DELAY - (ABSOLUTE - (PORT dataa (371:371:371) (410:410:410)) - (PORT datab (234:234:234) (279:279:279)) - (PORT datac (177:177:177) (213:213:213)) - (PORT datad (179:179:179) (207:207:207)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|result\~0) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (255:255:255)) - (PORT datab (236:236:236) (281:281:281)) - (PORT datac (354:354:354) (379:379:379)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[7\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1068:1068:1068) (1102:1102:1102)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1193:1193:1193) (1176:1176:1176)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (1435:1435:1435) (1482:1482:1482)) - (PORT ena (1283:1283:1283) (1283:1283:1283)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~69) - (DELAY - (ABSOLUTE - (PORT dataa (244:244:244) (331:331:331)) - (PORT datab (1596:1596:1596) (1648:1648:1648)) - (PORT datad (1179:1179:1179) (1221:1221:1221)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (1647:1647:1647) (1718:1718:1718)) - (PORT ena (1214:1214:1214) (1210:1210:1210)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (1644:1644:1644) (1714:1714:1714)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~70) - (DELAY - (ABSOLUTE - (PORT dataa (902:902:902) (942:942:942)) - (PORT datab (245:245:245) (290:290:290)) - (PORT datad (218:218:218) (287:287:287)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1535:1535:1535) (1554:1554:1554)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1461:1461:1461) (1468:1468:1468)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1534:1534:1534)) - (PORT asdata (1405:1405:1405) (1471:1471:1471)) - (PORT ena (1236:1236:1236) (1273:1273:1273)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~72) - (DELAY - (ABSOLUTE - (PORT dataa (712:712:712) (798:798:798)) - (PORT datab (884:884:884) (909:909:909)) - (PORT datad (866:866:866) (902:902:902)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1534:1534:1534)) - (PORT asdata (1404:1404:1404) (1472:1472:1472)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~71) - (DELAY - (ABSOLUTE - (PORT dataa (1391:1391:1391) (1418:1418:1418)) - (PORT datab (1167:1167:1167) (1217:1217:1217)) - (PORT datad (238:238:238) (279:279:279)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~73) - (DELAY - (ABSOLUTE - (PORT dataa (820:820:820) (843:843:843)) - (PORT datab (1070:1070:1070) (1130:1130:1130)) - (PORT datac (171:171:171) (205:205:205)) - (PORT datad (172:172:172) (198:198:198)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1537:1537:1537)) - (PORT asdata (1442:1442:1442) (1490:1490:1490)) - (PORT ena (990:990:990) (994:994:994)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1537:1537:1537)) - (PORT asdata (1439:1439:1439) (1490:1490:1490)) - (PORT ena (973:973:973) (964:964:964)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~67) - (DELAY - (ABSOLUTE - (PORT dataa (466:466:466) (523:523:523)) - (PORT datab (492:492:492) (536:536:536)) - (PORT datad (216:216:216) (284:284:284)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (1377:1377:1377) (1423:1423:1423)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[7\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (938:938:938) (994:994:994)) - (PORT datab (1222:1222:1222) (1294:1294:1294)) - (PORT datad (881:881:881) (941:941:941)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (1195:1195:1195) (1249:1249:1249)) - (PORT ena (1388:1388:1388) (1427:1427:1427)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (1195:1195:1195) (1248:1248:1248)) - (PORT ena (1400:1400:1400) (1413:1413:1413)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~68) - (DELAY - (ABSOLUTE - (PORT dataa (924:924:924) (985:985:985)) - (PORT datab (910:910:910) (988:988:988)) - (PORT datad (217:217:217) (286:286:286)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~74) - (DELAY - (ABSOLUTE - (PORT dataa (384:384:384) (410:410:410)) - (PORT datab (634:634:634) (661:661:661)) - (PORT datac (637:637:637) (673:673:673)) - (PORT datad (789:789:789) (853:853:853)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1535:1535:1535) (1554:1554:1554)) - (PORT asdata (1138:1138:1138) (1178:1178:1178)) - (PORT ena (935:935:935) (924:924:924)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (222:222:222) (266:266:266)) - (PORT datab (407:407:407) (446:446:446)) - (PORT datad (387:387:387) (422:422:422)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1308:1308:1308) (1303:1303:1303)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (794:794:794) (860:860:860)) - (PORT datac (214:214:214) (289:289:289)) - (PORT datad (646:646:646) (672:672:672)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|SYNTHESIZED_WIRE_0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (623:623:623) (634:634:634)) - (PORT datab (906:906:906) (933:933:933)) - (PORT datac (239:239:239) (322:322:322)) - (PORT datad (576:576:576) (636:636:636)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|d1_out) - (DELAY - (ABSOLUTE - (PORT datac (258:258:258) (345:345:345)) - (PORT datad (187:187:187) (220:220:220)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (1405:1405:1405) (1477:1477:1477)) - (PORT ena (1261:1261:1261) (1299:1299:1299)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1535:1535:1535) (1554:1554:1554)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1461:1461:1461) (1468:1468:1468)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~54) - (DELAY - (ABSOLUTE - (PORT dataa (1099:1099:1099) (1151:1151:1151)) - (PORT datab (881:881:881) (915:915:915)) - (PORT datad (665:665:665) (744:744:744)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1534:1534:1534)) - (PORT asdata (2052:2052:2052) (2111:2111:2111)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~53) - (DELAY - (ABSOLUTE - (PORT dataa (1647:1647:1647) (1654:1654:1654)) - (PORT datab (1164:1164:1164) (1211:1211:1211)) - (PORT datad (231:231:231) (271:271:271)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[5\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1101:1101:1101) (1166:1166:1166)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1193:1193:1193) (1176:1176:1176)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (1418:1418:1418) (1481:1481:1481)) - (PORT ena (1283:1283:1283) (1283:1283:1283)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~51) - (DELAY - (ABSOLUTE - (PORT dataa (380:380:380) (459:459:459)) - (PORT datab (1594:1594:1594) (1651:1651:1651)) - (PORT datad (1178:1178:1178) (1221:1221:1221)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (1799:1799:1799) (1855:1855:1855)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (1406:1406:1406) (1476:1476:1476)) - (PORT ena (1131:1131:1131) (1098:1098:1098)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~52) - (DELAY - (ABSOLUTE - (PORT dataa (416:416:416) (478:478:478)) - (PORT datab (881:881:881) (916:916:916)) - (PORT datad (364:364:364) (384:384:384)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~55) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (338:338:338) (368:368:368)) - (PORT datac (804:804:804) (808:808:808)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1537:1537:1537)) - (PORT asdata (1448:1448:1448) (1498:1498:1498)) - (PORT ena (973:973:973) (964:964:964)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1537:1537:1537)) - (PORT asdata (1448:1448:1448) (1501:1501:1501)) - (PORT ena (990:990:990) (994:994:994)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~49) - (DELAY - (ABSOLUTE - (PORT dataa (462:462:462) (518:518:518)) - (PORT datab (240:240:240) (322:322:322)) - (PORT datad (458:458:458) (504:504:504)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (1721:1721:1721) (1779:1779:1779)) - (PORT ena (1400:1400:1400) (1413:1413:1413)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (1723:1723:1723) (1782:1782:1782)) - (PORT ena (1388:1388:1388) (1427:1427:1427)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~50) - (DELAY - (ABSOLUTE - (PORT dataa (931:931:931) (989:989:989)) - (PORT datab (243:243:243) (326:326:326)) - (PORT datad (883:883:883) (941:941:941)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (1771:1771:1771) (1829:1829:1829)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[5\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (928:928:928) (989:989:989)) - (PORT datab (1220:1220:1220) (1296:1296:1296)) - (PORT datad (884:884:884) (944:944:944)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~56) - (DELAY - (ABSOLUTE - (PORT dataa (655:655:655) (699:699:699)) - (PORT datab (825:825:825) (869:869:869)) - (PORT datac (606:606:606) (632:632:632)) - (PORT datad (842:842:842) (848:848:848)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~57) - (DELAY - (ABSOLUTE - (PORT dataa (884:884:884) (946:946:946)) - (PORT datab (197:197:197) (234:234:234)) - (PORT datac (817:817:817) (863:863:863)) - (PORT datad (1298:1298:1298) (1332:1332:1332)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1535:1535:1535) (1554:1554:1554)) - (PORT asdata (1159:1159:1159) (1205:1205:1205)) - (PORT ena (935:935:935) (924:924:924)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (410:410:410) (459:459:459)) - (PORT datab (218:218:218) (256:256:256)) - (PORT datad (386:386:386) (413:413:413)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1308:1308:1308) (1303:1303:1303)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (673:673:673) (716:716:716)) - (PORT datab (379:379:379) (421:421:421)) - (PORT datac (215:215:215) (292:292:292)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (567:567:567) (582:582:582)) - (PORT datab (844:844:844) (883:883:883)) - (PORT datac (682:682:682) (722:722:722)) - (PORT datad (173:173:173) (197:197:197)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[13\]) - (DELAY - (ABSOLUTE - (PORT datab (383:383:383) (425:425:425)) - (PORT datac (886:886:886) (918:918:918)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|Q\[13\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (335:335:335) (352:352:352)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[13\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1581:1581:1581) (1561:1561:1561)) - (PORT ena (2058:2058:2058) (2109:2109:2109)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_53\~0) - (DELAY - (ABSOLUTE - (PORT datac (258:258:258) (345:345:345)) - (PORT datad (869:869:869) (891:891:891)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[15\]) - (DELAY - (ABSOLUTE - (PORT datac (356:356:356) (377:377:377)) - (PORT datad (867:867:867) (889:889:889)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[15\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1581:1581:1581) (1561:1561:1561)) - (PORT ena (2058:2058:2058) (2109:2109:2109)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[14\]) - (DELAY - (ABSOLUTE - (PORT dataa (290:290:290) (385:385:385)) - (PORT datab (215:215:215) (260:260:260)) - (PORT datac (245:245:245) (326:326:326)) - (PORT datad (866:866:866) (891:891:891)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1308:1308:1308) (1303:1303:1303)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1537:1537:1537)) - (PORT asdata (2284:2284:2284) (2422:2422:2422)) - (PORT ena (990:990:990) (994:994:994)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1537:1537:1537)) - (PORT asdata (2284:2284:2284) (2422:2422:2422)) - (PORT ena (973:973:973) (964:964:964)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~76) - (DELAY - (ABSOLUTE - (PORT dataa (461:461:461) (524:524:524)) - (PORT datab (491:491:491) (541:541:541)) - (PORT datad (217:217:217) (286:286:286)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1534:1534:1534)) - (PORT asdata (1879:1879:1879) (1975:1975:1975)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~80) - (DELAY - (ABSOLUTE - (PORT dataa (818:818:818) (835:835:835)) - (PORT datab (1168:1168:1168) (1216:1216:1216)) - (PORT datad (239:239:239) (281:281:281)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (1192:1192:1192) (1258:1258:1258)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (2131:2131:2131) (2211:2211:2211)) - (PORT ena (1131:1131:1131) (1098:1098:1098)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~79) - (DELAY - (ABSOLUTE - (PORT dataa (390:390:390) (460:460:460)) - (PORT datab (883:883:883) (917:917:917)) - (PORT datad (364:364:364) (384:384:384)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (1453:1453:1453) (1497:1497:1497)) - (PORT ena (1283:1283:1283) (1283:1283:1283)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (1453:1453:1453) (1497:1497:1497)) - (PORT ena (1193:1193:1193) (1176:1176:1176)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~78) - (DELAY - (ABSOLUTE - (PORT dataa (1297:1297:1297) (1353:1353:1353)) - (PORT datab (1218:1218:1218) (1255:1255:1255)) - (PORT datad (214:214:214) (282:282:282)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1535:1535:1535) (1554:1554:1554)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1461:1461:1461) (1468:1468:1468)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (2133:2133:2133) (2211:2211:2211)) - (PORT ena (1261:1261:1261) (1299:1299:1299)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~81) - (DELAY - (ABSOLUTE - (PORT dataa (1100:1100:1100) (1146:1146:1146)) - (PORT datab (681:681:681) (756:756:756)) - (PORT datad (848:848:848) (874:874:874)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~82) - (DELAY - (ABSOLUTE - (PORT dataa (605:605:605) (624:624:624)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (595:595:595) (612:612:612)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (1205:1205:1205) (1270:1270:1270)) - (PORT ena (1388:1388:1388) (1427:1427:1427)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT asdata (1205:1205:1205) (1270:1270:1270)) - (PORT ena (1400:1400:1400) (1413:1413:1413)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~77) - (DELAY - (ABSOLUTE - (PORT dataa (930:930:930) (985:985:985)) - (PORT datab (912:912:912) (982:982:982)) - (PORT datad (216:216:216) (284:284:284)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (2162:2162:2162) (2212:2212:2212)) - (PORT ena (794:794:794) (792:792:792)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[6\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (939:939:939) (997:997:997)) - (PORT datab (1220:1220:1220) (1296:1296:1296)) - (PORT datad (879:879:879) (940:940:940)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~83) - (DELAY - (ABSOLUTE - (PORT dataa (634:634:634) (650:650:650)) - (PORT datab (632:632:632) (657:657:657)) - (PORT datac (489:489:489) (507:507:507)) - (PORT datad (173:173:173) (197:197:197)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~84) - (DELAY - (ABSOLUTE - (PORT dataa (879:879:879) (944:944:944)) - (PORT datab (672:672:672) (688:688:688)) - (PORT datac (786:786:786) (839:839:839)) - (PORT datad (1301:1301:1301) (1333:1333:1333)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1535:1535:1535) (1554:1554:1554)) - (PORT asdata (1132:1132:1132) (1183:1183:1183)) - (PORT ena (935:935:935) (924:924:924)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (410:410:410) (466:466:466)) - (PORT datab (218:218:218) (258:258:258)) - (PORT datad (382:382:382) (412:412:412)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (245:245:245) (332:332:332)) - (PORT datab (670:670:670) (688:688:688)) - (PORT datad (645:645:645) (672:672:672)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (366:366:366) (401:401:401)) - (PORT datab (712:712:712) (754:754:754)) - (PORT datac (808:808:808) (840:840:840)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[14\]) - (DELAY - (ABSOLUTE - (PORT dataa (916:916:916) (955:955:955)) - (PORT datac (361:361:361) (395:395:395)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|Q\[14\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (320:320:320) (331:331:331)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[14\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1538:1538:1538)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1581:1581:1581) (1561:1561:1561)) - (PORT ena (2058:2058:2058) (2109:2109:2109)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_16) - (DELAY - (ABSOLUTE - (PORT dataa (1141:1141:1141) (1169:1169:1169)) - (PORT datab (404:404:404) (477:477:477)) - (PORT datac (1110:1110:1110) (1117:1117:1117)) - (PORT datad (632:632:632) (663:663:663)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[15\]) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (214:214:214) (258:258:258)) - (PORT datac (232:232:232) (316:316:316)) - (PORT datad (339:339:339) (360:360:360)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (379:379:379) (417:417:417)) - (PORT datab (712:712:712) (760:760:760)) - (PORT datac (814:814:814) (847:847:847)) - (PORT datad (550:550:550) (569:569:569)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~75) - (DELAY - (ABSOLUTE - (PORT dataa (880:880:880) (950:950:950)) - (PORT datab (664:664:664) (704:704:704)) - (PORT datac (792:792:792) (834:834:834)) - (PORT datad (1297:1297:1297) (1337:1337:1337)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[7\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (1297:1297:1297) (1347:1347:1347)) - (PORT datab (973:973:973) (1026:1026:1026)) - (PORT datac (1877:1877:1877) (1946:1946:1946)) - (PORT datad (831:831:831) (844:844:844)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[7\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (204:204:204) (249:249:249)) - (PORT datab (256:256:256) (314:314:314)) - (PORT datac (1193:1193:1193) (1204:1204:1204)) - (PORT datad (945:945:945) (989:989:989)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~1) - (DELAY - (ABSOLUTE - (PORT dataa (933:933:933) (970:970:970)) - (PORT datab (1223:1223:1223) (1296:1296:1296)) - (PORT datac (905:905:905) (924:924:924)) - (PORT datad (1385:1385:1385) (1451:1451:1451)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~0) - (DELAY - (ABSOLUTE - (PORT dataa (893:893:893) (902:902:902)) - (PORT datab (661:661:661) (697:697:697)) - (PORT datac (670:670:670) (697:697:697)) - (PORT datad (675:675:675) (694:694:694)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1512:1512:1512) (1612:1612:1612)) - (PORT datab (1393:1393:1393) (1508:1508:1508)) - (PORT datac (1411:1411:1411) (1459:1459:1459)) - (PORT datad (835:835:835) (870:870:870)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (608:608:608) (635:635:635)) - (PORT datab (198:198:198) (238:238:238)) - (PORT datac (194:194:194) (228:228:228)) - (PORT datad (1083:1083:1083) (1127:1127:1127)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1159:1159:1159) (1199:1199:1199)) - (PORT datab (1007:1007:1007) (1063:1063:1063)) - (PORT datac (212:212:212) (252:252:252)) - (PORT datad (1995:1995:1995) (2085:2085:2085)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (211:211:211) (260:260:260)) - (PORT datab (634:634:634) (650:650:650)) - (PORT datac (599:599:599) (616:616:616)) - (PORT datad (610:610:610) (626:626:626)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~2) - (DELAY - (ABSOLUTE - (PORT datab (701:701:701) (761:761:761)) - (PORT datac (1331:1331:1331) (1352:1352:1352)) - (PORT datad (1148:1148:1148) (1179:1179:1179)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1693:1693:1693) (1732:1732:1732)) - (PORT datab (1474:1474:1474) (1569:1569:1569)) - (PORT datac (2562:2562:2562) (2664:2664:2664)) - (PORT datad (1898:1898:1898) (2017:2017:2017)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1942:1942:1942) (2062:2062:2062)) - (PORT datab (198:198:198) (236:236:236)) - (PORT datac (918:918:918) (965:965:965)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~1) - (DELAY - (ABSOLUTE - (PORT dataa (634:634:634) (664:664:664)) - (PORT datab (640:640:640) (658:658:658)) - (PORT datad (880:880:880) (936:936:936)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf) - (DELAY - (ABSOLUTE - (PORT clk (1511:1511:1511) (1525:1525:1525)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1199:1199:1199) (1286:1286:1286)) - (PORT datab (255:255:255) (340:340:340)) - (PORT datac (1353:1353:1353) (1415:1415:1415)) - (PORT datad (1199:1199:1199) (1262:1262:1262)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|b2v_inst_shift_mux\|out\~2) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (196:196:196) (235:235:235)) - (PORT datad (1171:1171:1171) (1244:1244:1244)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~5) - (DELAY - (ABSOLUTE - (PORT datab (219:219:219) (259:259:259)) - (PORT datac (882:882:882) (919:919:919)) - (PORT datad (1382:1382:1382) (1453:1453:1453)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (416:416:416) (442:442:442)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (896:896:896) (932:932:932)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (423:423:423) (511:511:511)) - (PORT datab (1166:1166:1166) (1210:1210:1210)) - (PORT datac (593:593:593) (646:646:646)) - (PORT datad (662:662:662) (719:719:719)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (1177:1177:1177) (1208:1208:1208)) - (PORT datab (281:281:281) (344:344:344)) - (PORT datac (245:245:245) (304:304:304)) - (PORT datad (256:256:256) (301:301:301)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (342:342:342) (378:378:378)) - (PORT datab (802:802:802) (831:831:831)) - (PORT datac (498:498:498) (504:504:504)) - (PORT datad (1104:1104:1104) (1147:1147:1147)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[3\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (600:600:600) (639:639:639)) - (PORT datab (999:999:999) (1033:1033:1033)) - (PORT datac (589:589:589) (604:604:604)) - (PORT datad (221:221:221) (264:264:264)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[3\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (378:378:378) (404:404:404)) - (PORT datab (893:893:893) (942:942:942)) - (PORT datac (1167:1167:1167) (1166:1166:1166)) - (PORT datad (680:680:680) (715:715:715)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_low\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (790:790:790) (782:782:782)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (695:695:695) (756:756:756)) - (PORT datab (1177:1177:1177) (1222:1222:1222)) - (PORT datac (613:613:613) (678:678:678)) - (PORT datad (666:666:666) (725:725:725)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\~2) - (DELAY - (ABSOLUTE - (PORT datab (288:288:288) (350:350:350)) - (PORT datad (251:251:251) (296:296:296)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (285:285:285) (347:347:347)) - (PORT datab (620:620:620) (638:638:638)) - (PORT datac (1141:1141:1141) (1167:1167:1167)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|result_lo\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1535:1535:1535)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1283:1283:1283) (1287:1287:1287)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (968:968:968) (996:996:996)) - (PORT datac (1660:1660:1660) (1742:1742:1742)) - (PORT datad (1418:1418:1418) (1445:1445:1445)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1138:1138:1138) (1168:1168:1168)) - (PORT datab (1129:1129:1129) (1182:1182:1182)) - (PORT datac (171:171:171) (205:205:205)) - (PORT datad (241:241:241) (282:282:282)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (522:522:522) (538:538:538)) - (PORT datab (879:879:879) (956:956:956)) - (PORT datac (959:959:959) (990:990:990)) - (PORT datad (594:594:594) (608:608:608)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[3\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (1196:1196:1196) (1243:1243:1243)) - (PORT datab (609:609:609) (645:645:645)) - (PORT datac (193:193:193) (235:235:235)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[3\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (669:669:669) (695:695:695)) - (PORT datab (912:912:912) (959:959:959)) - (PORT datac (854:854:854) (883:883:883)) - (PORT datad (1144:1144:1144) (1179:1179:1179)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[3\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (638:638:638) (678:678:678)) - (PORT datab (961:961:961) (1023:1023:1023)) - (PORT datac (1152:1152:1152) (1178:1178:1178)) - (PORT datad (225:225:225) (270:270:270)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_2u\~7) - (DELAY - (ABSOLUTE - (PORT dataa (230:230:230) (279:279:279)) - (PORT datab (1448:1448:1448) (1517:1517:1517)) - (PORT datac (1115:1115:1115) (1163:1163:1163)) - (PORT datad (178:178:178) (206:206:206)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~49) - (DELAY - (ABSOLUTE - (PORT dataa (1187:1187:1187) (1261:1261:1261)) - (PORT datab (930:930:930) (959:959:959)) - (PORT datac (533:533:533) (553:553:553)) - (PORT datad (844:844:844) (856:856:856)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_oe\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1441:1441:1441) (1548:1548:1548)) - (PORT datab (218:218:218) (257:257:257)) - (PORT datac (235:235:235) (277:277:277)) - (PORT datad (1401:1401:1401) (1453:1453:1453)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_35) - (DELAY - (ABSOLUTE - (PORT dataa (645:645:645) (663:663:663)) - (PORT datab (615:615:615) (664:664:664)) - (PORT datac (664:664:664) (693:693:693)) - (PORT datad (680:680:680) (701:701:701)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~7) - (DELAY - (ABSOLUTE - (PORT datab (614:614:614) (644:644:644)) - (PORT datad (801:801:801) (877:877:877)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla69M2T2_3) - (DELAY - (ABSOLUTE - (PORT dataa (640:640:640) (665:665:665)) - (PORT datab (2306:2306:2306) (2385:2385:2385)) - (PORT datac (2054:2054:2054) (2198:2198:2198)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~13) - (DELAY - (ABSOLUTE - (PORT dataa (377:377:377) (426:426:426)) - (PORT datab (1624:1624:1624) (1701:1701:1701)) - (PORT datac (829:829:829) (848:848:848)) - (PORT datad (180:180:180) (209:209:209)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~14) - (DELAY - (ABSOLUTE - (PORT dataa (816:816:816) (877:877:877)) - (PORT datab (360:360:360) (396:396:396)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (182:182:182) (211:211:211)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~15) - (DELAY - (ABSOLUTE - (PORT dataa (930:930:930) (1002:1002:1002)) - (PORT datab (692:692:692) (710:710:710)) - (PORT datac (563:563:563) (586:586:586)) - (PORT datad (616:616:616) (630:630:630)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|flags_xf) - (DELAY - (ABSOLUTE - (PORT clk (1514:1514:1514) (1528:1528:1528)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[3\]\~33) - (DELAY - (ABSOLUTE - (PORT datab (957:957:957) (981:981:981)) - (PORT datac (645:645:645) (694:694:694)) - (PORT datad (656:656:656) (712:712:712)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~3) - (DELAY - (ABSOLUTE - (PORT dataa (348:348:348) (378:378:378)) - (PORT datab (209:209:209) (251:251:251)) - (PORT datac (177:177:177) (213:213:213)) - (PORT datad (652:652:652) (692:692:692)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla23pla16M3T1_5\~0) - (DELAY - (ABSOLUTE - (PORT dataa (887:887:887) (904:904:904)) - (PORT datab (994:994:994) (1026:1026:1026)) - (PORT datac (1433:1433:1433) (1520:1520:1520)) - (PORT datad (1142:1142:1142) (1160:1160:1160)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~4) - (DELAY - (ABSOLUTE - (PORT dataa (644:644:644) (697:697:697)) - (PORT datab (936:936:936) (950:950:950)) - (PORT datac (1455:1455:1455) (1497:1497:1497)) - (PORT datad (1163:1163:1163) (1183:1183:1183)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~5) - (DELAY - (ABSOLUTE - (PORT dataa (631:631:631) (638:638:638)) - (PORT datab (207:207:207) (248:248:248)) - (PORT datac (881:881:881) (909:909:909)) - (PORT datad (194:194:194) (219:219:219)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~8) - (DELAY - (ABSOLUTE - (PORT datab (1639:1639:1639) (1704:1704:1704)) - (PORT datac (1440:1440:1440) (1481:1481:1481)) - (PORT datad (1160:1160:1160) (1199:1199:1199)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sw1_\|db_down\[3\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (362:362:362) (500:500:500)) - (PORT datab (1223:1223:1223) (1282:1282:1282)) - (PORT datac (1145:1145:1145) (1179:1179:1179)) - (PORT datad (899:899:899) (938:938:938)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[3\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (868:868:868) (917:917:917)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (870:870:870) (900:900:900)) - (PORT datad (616:616:616) (665:665:665)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[3\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (622:622:622) (647:647:647)) - (PORT datab (247:247:247) (295:295:295)) - (PORT datac (1154:1154:1154) (1184:1184:1184)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~46) - (DELAY - (ABSOLUTE - (PORT dataa (474:474:474) (512:512:512)) - (PORT datab (1141:1141:1141) (1188:1188:1188)) - (PORT datad (1463:1463:1463) (1479:1479:1479)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~47) - (DELAY - (ABSOLUTE - (PORT dataa (421:421:421) (486:486:486)) - (PORT datac (173:173:173) (206:206:206)) - (PORT datad (1618:1618:1618) (1617:1617:1617)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~50) - (DELAY - (ABSOLUTE - (PORT datab (353:353:353) (390:390:390)) - (PORT datac (784:784:784) (794:794:794)) - (PORT datad (320:320:320) (341:341:341)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1531:1531:1531)) - (PORT asdata (970:970:970) (1022:1022:1022)) - (PORT ena (1413:1413:1413) (1385:1385:1385)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1531:1531:1531)) - (PORT asdata (970:970:970) (1022:1022:1022)) - (PORT ena (1734:1734:1734) (1719:1719:1719)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~44) - (DELAY - (ABSOLUTE - (PORT dataa (247:247:247) (336:336:336)) - (PORT datab (975:975:975) (1029:1029:1029)) - (PORT datad (845:845:845) (875:875:875)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (868:868:868) (877:877:877)) - (PORT ena (811:811:811) (804:804:804)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (869:869:869) (877:877:877)) - (PORT ena (841:841:841) (846:846:846)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~43) - (DELAY - (ABSOLUTE - (PORT dataa (246:246:246) (333:333:333)) - (PORT datab (260:260:260) (314:314:314)) - (PORT datad (229:229:229) (267:267:267)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~51) - (DELAY - (ABSOLUTE - (PORT dataa (858:858:858) (870:870:870)) - (PORT datab (202:202:202) (242:242:242)) - (PORT datac (607:607:607) (626:626:626)) - (PORT datad (625:625:625) (639:639:639)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~52) - (DELAY - (ABSOLUTE - (PORT dataa (858:858:858) (895:895:895)) - (PORT datab (609:609:609) (627:627:627)) - (PORT datac (332:332:332) (359:359:359)) - (PORT datad (1115:1115:1115) (1138:1138:1138)) - (IOPATH dataa combout (300:300:300) (307:307:307)) + (PORT datab (1375:1375:1375) (1436:1436:1436)) + (PORT datac (1062:1062:1062) (1107:1107:1107)) + (PORT datad (181:181:181) (210:210:210)) (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (957:957:957) (1002:1002:1002)) - (PORT ena (1201:1201:1201) (1184:1184:1184)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1331:1331:1331) (1374:1374:1374)) - (PORT datab (697:697:697) (731:731:731)) - (PORT datad (1194:1194:1194) (1238:1238:1238)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1541:1541:1541) (1557:1557:1557)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1283:1283:1283) (1286:1286:1286)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (609:609:609) (669:669:669)) - (PORT datac (704:704:704) (742:742:742)) - (PORT datad (220:220:220) (290:290:290)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (379:379:379) (401:401:401)) - (PORT datab (960:960:960) (999:999:999)) - (PORT datac (683:683:683) (718:718:718)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[3\]) - (DELAY - (ABSOLUTE - (PORT datab (240:240:240) (286:286:286)) - (PORT datac (548:548:548) (560:560:560)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1541:1541:1541) (1557:1557:1557)) - (PORT asdata (870:870:870) (882:882:882)) - (PORT clrn (1597:1597:1597) (1572:1572:1572)) - (PORT ena (2143:2143:2143) (2210:2210:2210)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_45\~4) - (DELAY - (ABSOLUTE - (PORT dataa (387:387:387) (429:429:429)) - (PORT datab (1153:1153:1153) (1183:1183:1183)) - (PORT datac (963:963:963) (1032:1032:1032)) - (PORT datad (244:244:244) (316:316:316)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|carry_borrow_out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (350:350:350) (392:392:392)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (340:340:340) (367:367:367)) - (PORT datad (324:324:324) (346:346:346)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_4\|d0_out) - (DELAY - (ABSOLUTE - (PORT dataa (265:265:265) (352:352:352)) - (PORT datab (206:206:206) (248:248:248)) - (PORT datac (332:332:332) (358:358:358)) - (PORT datad (196:196:196) (221:221:221)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (1239:1239:1239) (1260:1260:1260)) - (PORT ena (811:811:811) (804:804:804)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (1236:1236:1236) (1256:1256:1256)) - (PORT ena (841:841:841) (846:846:846)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~53) - (DELAY - (ABSOLUTE - (PORT dataa (244:244:244) (331:331:331)) - (PORT datab (258:258:258) (310:310:310)) - (PORT datad (228:228:228) (266:266:266)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~54) - (DELAY - (ABSOLUTE - (PORT dataa (635:635:635) (663:663:663)) - (PORT datab (1133:1133:1133) (1182:1182:1182)) - (PORT datad (630:630:630) (644:644:644)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1545:1545:1545)) - (PORT asdata (1202:1202:1202) (1222:1222:1222)) - (PORT ena (821:821:821) (834:834:834)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1545:1545:1545)) - (PORT asdata (1206:1206:1206) (1227:1227:1227)) - (PORT ena (1266:1266:1266) (1269:1269:1269)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~58) - (DELAY - (ABSOLUTE - (PORT dataa (408:408:408) (466:466:466)) - (PORT datab (591:591:591) (631:631:631)) - (PORT datad (218:218:218) (288:288:288)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1534:1534:1534)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1505:1505:1505) (1518:1518:1518)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1520:1520:1520) (1534:1534:1534)) - (PORT asdata (958:958:958) (967:967:967)) - (PORT ena (1207:1207:1207) (1190:1190:1190)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1520:1520:1520) (1534:1534:1534)) - (PORT asdata (960:960:960) (969:969:969)) - (PORT ena (1263:1263:1263) (1264:1264:1264)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~59) - (DELAY - (ABSOLUTE - (PORT dataa (467:467:467) (505:505:505)) - (PORT datab (668:668:668) (703:703:703)) - (PORT datad (216:216:216) (284:284:284)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~60) - (DELAY - (ABSOLUTE - (PORT dataa (646:646:646) (665:665:665)) - (PORT datab (920:920:920) (943:943:943)) - (PORT datac (213:213:213) (288:288:288)) - (PORT datad (335:335:335) (356:356:356)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1531:1531:1531)) - (PORT asdata (993:993:993) (1020:1020:1020)) - (PORT ena (1734:1734:1734) (1719:1719:1719)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1531:1531:1531)) - (PORT asdata (995:995:995) (1022:1022:1022)) - (PORT ena (1413:1413:1413) (1385:1385:1385)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~57) - (DELAY - (ABSOLUTE - (PORT dataa (875:875:875) (922:922:922)) - (PORT datab (965:965:965) (1021:1021:1021)) - (PORT datad (217:217:217) (286:286:286)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1545:1545:1545)) - (PORT asdata (984:984:984) (1006:1006:1006)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1545:1545:1545)) - (PORT asdata (982:982:982) (1003:1003:1003)) - (PORT ena (1220:1220:1220) (1214:1214:1214)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~55) - (DELAY - (ABSOLUTE - (PORT dataa (645:645:645) (700:700:700)) - (PORT datab (396:396:396) (436:436:436)) - (PORT datad (215:215:215) (283:283:283)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1534:1534:1534)) - (PORT asdata (875:875:875) (882:882:882)) - (PORT ena (1407:1407:1407) (1382:1382:1382)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~56) - (DELAY - (ABSOLUTE - (PORT dataa (527:527:527) (547:547:547)) - (PORT datad (825:825:825) (835:835:835)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~61) - (DELAY - (ABSOLUTE - (PORT dataa (340:340:340) (377:377:377)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (1018:1018:1018) (1019:1019:1019)) - (PORT datad (173:173:173) (197:197:197)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[4\]\~62) - (DELAY - (ABSOLUTE - (PORT dataa (198:198:198) (241:241:241)) - (PORT datab (856:856:856) (875:875:875)) - (PORT datac (1094:1094:1094) (1126:1126:1126)) - (PORT datad (1162:1162:1162) (1190:1190:1190)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (1359:1359:1359) (1370:1370:1370)) - (PORT ena (1201:1201:1201) (1184:1184:1184)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (889:889:889) (911:911:911)) - (PORT datab (1236:1236:1236) (1275:1275:1275)) - (PORT datad (664:664:664) (688:688:688)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1541:1541:1541) (1557:1557:1557)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1283:1283:1283) (1286:1286:1286)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~14) - (DELAY - (ABSOLUTE - (PORT datab (624:624:624) (675:675:675)) - (PORT datac (704:704:704) (739:739:739)) - (PORT datad (216:216:216) (285:285:285)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[4\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (379:379:379) (401:401:401)) - (PORT datab (959:959:959) (1001:1001:1001)) - (PORT datac (682:682:682) (721:721:721)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[4\]) - (DELAY - (ABSOLUTE - (PORT datab (238:238:238) (283:283:283)) - (PORT datad (529:529:529) (540:540:540)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1541:1541:1541) (1557:1557:1557)) - (PORT asdata (852:852:852) (858:858:858)) - (PORT clrn (1597:1597:1597) (1572:1572:1572)) - (PORT ena (2143:2143:2143) (2210:2210:2210)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_44) - (DELAY - (ABSOLUTE - (PORT dataa (1155:1155:1155) (1182:1182:1182)) - (PORT datab (985:985:985) (1022:1022:1022)) - (PORT datad (201:201:201) (229:229:229)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_4\|d1_out) - (DELAY - (ABSOLUTE - (PORT dataa (710:710:710) (770:770:770)) - (PORT datab (1162:1162:1162) (1199:1199:1199)) - (PORT datac (626:626:626) (647:647:647)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1531:1531:1531)) - (PORT asdata (879:879:879) (891:891:891)) - (PORT ena (1413:1413:1413) (1385:1385:1385)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1531:1531:1531)) - (PORT asdata (878:878:878) (893:893:893)) - (PORT ena (1734:1734:1734) (1719:1719:1719)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~64) - (DELAY - (ABSOLUTE - (PORT dataa (244:244:244) (331:331:331)) - (PORT datab (966:966:966) (1022:1022:1022)) - (PORT datad (843:843:843) (873:873:873)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1517:1517:1517) (1531:1531:1531)) - (PORT asdata (692:692:692) (715:715:715)) - (PORT ena (1477:1477:1477) (1472:1472:1472)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1517:1517:1517) (1531:1531:1531)) - (PORT asdata (692:692:692) (713:713:713)) - (PORT ena (1247:1247:1247) (1263:1263:1263)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~63) - (DELAY - (ABSOLUTE - (PORT dataa (1095:1095:1095) (1134:1134:1134)) - (PORT datab (241:241:241) (323:323:323)) - (PORT datad (658:658:658) (679:679:679)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1534:1534:1534)) - (PORT asdata (1437:1437:1437) (1460:1460:1460)) - (PORT ena (1505:1505:1505) (1518:1518:1518)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1520:1520:1520) (1534:1534:1534)) - (PORT asdata (1457:1457:1457) (1472:1472:1472)) - (PORT ena (1207:1207:1207) (1190:1190:1190)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~66) - (DELAY - (ABSOLUTE - (PORT dataa (458:458:458) (494:494:494)) - (PORT datab (1132:1132:1132) (1177:1177:1177)) - (PORT datad (626:626:626) (636:636:636)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~67) - (DELAY - (ABSOLUTE - (PORT datab (918:918:918) (940:940:940)) - (PORT datad (338:338:338) (359:359:359)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1545:1545:1545)) - (PORT asdata (1214:1214:1214) (1217:1217:1217)) - (PORT ena (821:821:821) (834:834:834)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1545:1545:1545)) - (PORT asdata (1214:1214:1214) (1215:1215:1215)) - (PORT ena (1266:1266:1266) (1269:1269:1269)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~65) - (DELAY - (ABSOLUTE - (PORT dataa (409:409:409) (467:467:467)) - (PORT datab (592:592:592) (632:632:632)) - (PORT datad (216:216:216) (284:284:284)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1545:1545:1545)) - (PORT asdata (1471:1471:1471) (1477:1477:1477)) - (PORT ena (1220:1220:1220) (1214:1214:1214)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[5\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (607:607:607) (622:622:622)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~69) - (DELAY - (ABSOLUTE - (PORT dataa (641:641:641) (693:693:693)) - (PORT datab (390:390:390) (429:429:429)) - (PORT datad (215:215:215) (283:283:283)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[5\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (853:853:853) (859:859:859)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1534:1534:1534)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1407:1407:1407) (1382:1382:1382)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1520:1520:1520) (1534:1534:1534)) - (PORT asdata (1457:1457:1457) (1474:1474:1474)) - (PORT ena (1263:1263:1263) (1264:1264:1264)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~68) - (DELAY - (ABSOLUTE - (PORT dataa (574:574:574) (638:638:638)) - (PORT datab (836:836:836) (860:860:860)) - (PORT datad (645:645:645) (669:669:669)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~70) - (DELAY - (ABSOLUTE - (PORT dataa (638:638:638) (656:656:656)) - (PORT datab (1118:1118:1118) (1148:1148:1148)) - (PORT datac (339:339:339) (359:359:359)) - (PORT datad (587:587:587) (601:601:601)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~71) - (DELAY - (ABSOLUTE - (PORT dataa (372:372:372) (394:394:394)) - (PORT datac (170:170:170) (203:203:203)) - (PORT datad (175:175:175) (202:202:202)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[5\]\~72) - (DELAY - (ABSOLUTE - (PORT dataa (639:639:639) (699:699:699)) - (PORT datab (929:929:929) (992:992:992)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (1608:1608:1608) (1611:1611:1611)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (1227:1227:1227) (1243:1243:1243)) - (PORT ena (1201:1201:1201) (1184:1184:1184)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[5\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1190:1190:1190) (1197:1197:1197)) - (PORT datab (1236:1236:1236) (1275:1275:1275)) - (PORT datad (664:664:664) (688:688:688)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1534:1534:1534) (1553:1553:1553)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (811:811:811) (804:804:804)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[5\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (229:229:229) (275:275:275)) - (PORT datac (613:613:613) (632:632:632)) - (PORT datad (219:219:219) (288:288:288)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[5\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (655:655:655) (670:670:670)) - (PORT datab (1331:1331:1331) (1335:1335:1335)) - (PORT datac (192:192:192) (224:224:224)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[5\]) - (DELAY - (ABSOLUTE - (PORT datac (653:653:653) (693:693:693)) - (PORT datad (834:834:834) (843:843:843)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1560:1560:1560)) - (PORT ena (2152:2152:2152) (2220:2220:2220)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_43\~4) - (DELAY - (ABSOLUTE - (PORT dataa (920:920:920) (994:994:994)) - (PORT datab (1154:1154:1154) (1178:1178:1178)) - (PORT datac (960:960:960) (1026:1026:1026)) - (PORT datad (362:362:362) (387:387:387)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[6\]) - (DELAY - (ABSOLUTE - (PORT dataa (657:657:657) (687:687:687)) - (PORT datab (1161:1161:1161) (1198:1198:1198)) - (PORT datac (811:811:811) (865:865:865)) - (PORT datad (615:615:615) (643:643:643)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1541:1541:1541) (1557:1557:1557)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1283:1283:1283) (1286:1286:1286)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1531:1531:1531)) - (PORT asdata (1676:1676:1676) (1684:1684:1684)) - (PORT ena (1734:1734:1734) (1719:1719:1719)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[6\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1342:1342:1342) (1345:1345:1345)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1413:1413:1413) (1385:1385:1385)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~74) - (DELAY - (ABSOLUTE - (PORT dataa (870:870:870) (918:918:918)) - (PORT datab (966:966:966) (1020:1020:1020)) - (PORT datad (217:217:217) (285:285:285)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1517:1517:1517) (1531:1531:1531)) - (PORT asdata (1896:1896:1896) (1881:1881:1881)) - (PORT ena (1477:1477:1477) (1472:1472:1472)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1517:1517:1517) (1531:1531:1531)) - (PORT asdata (1893:1893:1893) (1878:1878:1878)) - (PORT ena (1247:1247:1247) (1263:1263:1263)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~73) - (DELAY - (ABSOLUTE - (PORT dataa (1092:1092:1092) (1133:1133:1133)) - (PORT datab (241:241:241) (323:323:323)) - (PORT datad (654:654:654) (676:676:676)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1544:1544:1544)) - (PORT asdata (2168:2168:2168) (2154:2154:2154)) - (PORT ena (1231:1231:1231) (1217:1217:1217)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[6\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1053:1053:1053) (1073:1073:1073)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~78) - (DELAY - (ABSOLUTE - (PORT dataa (435:435:435) (470:470:470)) - (PORT datab (637:637:637) (669:669:669)) - (PORT datad (374:374:374) (432:432:432)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1463:1463:1463) (1454:1454:1454)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~79) - (DELAY - (ABSOLUTE - (PORT dataa (689:689:689) (771:771:771)) - (PORT datab (945:945:945) (995:995:995)) - (PORT datac (878:878:878) (894:894:894)) - (PORT datad (606:606:606) (625:625:625)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1544:1544:1544)) - (PORT asdata (2168:2168:2168) (2153:2153:2153)) - (PORT ena (1499:1499:1499) (1507:1507:1507)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[6\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1302:1302:1302) (1310:1310:1310)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1520:1520:1520) (1534:1534:1534)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1263:1263:1263) (1264:1264:1264)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1520:1520:1520) (1534:1534:1534)) - (PORT asdata (1608:1608:1608) (1628:1628:1628)) - (PORT ena (1207:1207:1207) (1190:1190:1190)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~76) - (DELAY - (ABSOLUTE - (PORT dataa (466:466:466) (503:503:503)) - (PORT datab (242:242:242) (324:324:324)) - (PORT datad (640:640:640) (666:666:666)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~77) - (DELAY - (ABSOLUTE - (PORT datab (1410:1410:1410) (1425:1425:1425)) - (PORT datad (563:563:563) (574:574:574)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~80) - (DELAY - (ABSOLUTE - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1545:1545:1545)) - (PORT asdata (1342:1342:1342) (1366:1366:1366)) - (PORT ena (821:821:821) (834:834:834)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT asdata (1430:1430:1430) (1466:1466:1466)) - (PORT ena (841:841:841) (846:846:846)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~75) - (DELAY - (ABSOLUTE - (PORT dataa (412:412:412) (471:471:471)) - (PORT datab (584:584:584) (622:622:622)) - (PORT datad (835:835:835) (900:900:900)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~81) - (DELAY - (ABSOLUTE - (PORT dataa (374:374:374) (399:399:399)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (794:794:794) (791:791:791)) - (PORT datad (776:776:776) (774:774:774)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[6\]\~82) - (DELAY - (ABSOLUTE - (PORT dataa (592:592:592) (625:625:625)) - (PORT datab (658:658:658) (716:716:716)) - (PORT datac (1393:1393:1393) (1416:1416:1416)) - (PORT datad (599:599:599) (618:618:618)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT asdata (967:967:967) (1025:1025:1025)) - (PORT ena (1201:1201:1201) (1184:1184:1184)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1322:1322:1322) (1350:1350:1350)) - (PORT datab (1232:1232:1232) (1270:1270:1270)) - (PORT datad (660:660:660) (687:687:687)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~20) - (DELAY - (ABSOLUTE - (PORT datab (673:673:673) (705:705:705)) - (PORT datac (668:668:668) (749:749:749)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[6\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (714:714:714) (760:760:760)) - (PORT datab (648:648:648) (689:689:689)) - (PORT datac (926:926:926) (965:965:965)) - (PORT datad (593:593:593) (644:644:644)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|abusz\[6\]) - (DELAY - (ABSOLUTE - (PORT datac (652:652:652) (694:694:694)) - (PORT datad (819:819:819) (838:838:838)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_latch_\|Q\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1560:1560:1560)) - (PORT ena (2152:2152:2152) (2220:2220:2220)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_47\~0) - (DELAY - (ABSOLUTE - (PORT dataa (628:628:628) (670:670:670)) - (PORT datab (632:632:632) (673:673:673)) - (PORT datac (811:811:811) (863:863:863)) - (PORT datad (1165:1165:1165) (1193:1193:1193)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_47) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (242:242:242)) - (PORT datab (1158:1158:1158) (1194:1194:1194)) - (PORT datac (628:628:628) (651:651:651)) - (PORT datad (616:616:616) (644:644:644)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|d0_out) - (DELAY - (ABSOLUTE - (PORT dataa (423:423:423) (515:515:515)) - (PORT datad (190:190:190) (222:222:222)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (708:708:708) (752:752:752)) - (PORT datab (962:962:962) (1002:1002:1002)) - (PORT datac (171:171:171) (203:203:203)) - (PORT datad (619:619:619) (645:645:645)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1517:1517:1517) (1531:1531:1531)) - (PORT asdata (1212:1212:1212) (1251:1251:1251)) - (PORT ena (1477:1477:1477) (1472:1472:1472)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1517:1517:1517) (1531:1531:1531)) - (PORT asdata (1211:1211:1211) (1254:1254:1254)) - (PORT ena (1247:1247:1247) (1263:1263:1263)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~83) - (DELAY - (ABSOLUTE - (PORT dataa (1092:1092:1092) (1137:1137:1137)) - (PORT datab (243:243:243) (325:325:325)) - (PORT datad (656:656:656) (679:679:679)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1531:1531:1531)) - (PORT asdata (1408:1408:1408) (1437:1437:1437)) - (PORT ena (1734:1734:1734) (1719:1719:1719)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1531:1531:1531)) - (PORT asdata (1410:1410:1410) (1439:1439:1439)) - (PORT ena (1413:1413:1413) (1385:1385:1385)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~84) - (DELAY - (ABSOLUTE - (PORT dataa (876:876:876) (924:924:924)) - (PORT datab (963:963:963) (1013:1013:1013)) - (PORT datad (216:216:216) (284:284:284)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1544:1544:1544)) - (PORT asdata (1934:1934:1934) (1968:1968:1968)) - (PORT ena (1231:1231:1231) (1217:1217:1217)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[7\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1624:1624:1624) (1645:1645:1645)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~88) - (DELAY - (ABSOLUTE - (PORT dataa (435:435:435) (469:469:469)) - (PORT datab (636:636:636) (669:669:669)) - (PORT datad (370:370:370) (429:429:429)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1544:1544:1544)) - (PORT asdata (1932:1932:1932) (1967:1967:1967)) - (PORT ena (1499:1499:1499) (1507:1507:1507)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1520:1520:1520) (1534:1534:1534)) - (PORT asdata (1954:1954:1954) (1989:1989:1989)) - (PORT ena (1263:1263:1263) (1264:1264:1264)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1520:1520:1520) (1534:1534:1534)) - (PORT asdata (1954:1954:1954) (1989:1989:1989)) - (PORT ena (1207:1207:1207) (1190:1190:1190)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~86) - (DELAY - (ABSOLUTE - (PORT dataa (459:459:459) (495:495:495)) - (PORT datab (241:241:241) (322:322:322)) - (PORT datad (640:640:640) (664:664:664)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~87) - (DELAY - (ABSOLUTE - (PORT datab (1411:1411:1411) (1427:1427:1427)) - (PORT datad (587:587:587) (598:598:598)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1545:1545:1545)) - (PORT asdata (1731:1731:1731) (1772:1772:1772)) - (PORT ena (821:821:821) (834:834:834)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1545:1545:1545)) - (PORT asdata (1730:1730:1730) (1774:1774:1774)) - (PORT ena (1266:1266:1266) (1269:1269:1269)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~85) - (DELAY - (ABSOLUTE - (PORT dataa (407:407:407) (467:467:467)) - (PORT datab (591:591:591) (631:631:631)) - (PORT datad (216:216:216) (283:283:283)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1463:1463:1463) (1454:1454:1454)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~89) - (DELAY - (ABSOLUTE - (PORT dataa (646:646:646) (738:738:738)) - (PORT datab (944:944:944) (996:996:996)) - (PORT datac (844:844:844) (845:845:845)) - (PORT datad (606:606:606) (623:623:623)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~90) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (242:242:242)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (496:496:496) (503:503:503)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~91) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (364:364:364) (385:385:385)) - (PORT datad (573:573:573) (586:586:586)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~92) - (DELAY - (ABSOLUTE - (PORT dataa (667:667:667) (723:723:723)) - (PORT datab (660:660:660) (704:704:704)) - (PORT datac (1391:1391:1391) (1414:1414:1414)) - (PORT datad (597:597:597) (618:618:618)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_ds\[7\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1484:1484:1484) (1528:1528:1528)) - (PORT datab (1645:1645:1645) (1711:1711:1711)) - (PORT datac (872:872:872) (914:914:914)) - (PORT datad (1163:1163:1163) (1203:1203:1203)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|im2) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1541:1541:1541)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1571:1571:1571) (1550:1550:1550)) - (PORT ena (1258:1258:1258) (1280:1280:1280)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~12) - (DELAY - (ABSOLUTE - (PORT dataa (354:354:354) (492:492:492)) - (PORT datac (1227:1227:1227) (1295:1295:1295)) - (PORT datad (274:274:274) (356:356:356)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_sw_mask543_en\~0) - (DELAY - (ABSOLUTE - (PORT dataa (356:356:356) (494:494:494)) - (PORT datab (716:716:716) (747:747:747)) - (PORT datac (192:192:192) (224:224:224)) - (PORT datad (1301:1301:1301) (1395:1395:1395)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[7\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (881:881:881) (903:903:903)) - (PORT datab (928:928:928) (957:957:957)) - (PORT datac (631:631:631) (687:687:687)) - (PORT datad (632:632:632) (647:647:647)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[7\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (841:841:841) (861:861:861)) - (PORT datab (852:852:852) (879:879:879)) - (PORT datac (900:900:900) (940:940:940)) - (PORT datad (639:639:639) (700:700:700)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[7\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (204:204:204) (249:249:249)) - (PORT datab (244:244:244) (291:291:291)) - (PORT datac (645:645:645) (698:698:698)) - (PORT datad (617:617:617) (628:628:628)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_34) - (DELAY - (ABSOLUTE - (PORT dataa (693:693:693) (738:738:738)) - (PORT datab (889:889:889) (932:932:932)) - (PORT datac (869:869:869) (862:862:862)) - (PORT datad (202:202:202) (231:231:231)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1252:1252:1252) (1344:1344:1344)) - (PORT datab (857:857:857) (911:911:911)) - (PORT datac (614:614:614) (652:652:652)) - (PORT datad (195:195:195) (220:220:220)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_sf) - (DELAY - (ABSOLUTE - (PORT clk (1511:1511:1511) (1525:1525:1525)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (843:843:843) (856:856:856)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal62\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1466:1466:1466) (1594:1594:1594)) - (PORT datab (1469:1469:1469) (1553:1553:1553)) - (PORT datac (1102:1102:1102) (1148:1148:1148)) - (PORT datad (647:647:647) (684:684:684)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1119:1119:1119) (1156:1156:1156)) - (PORT datab (747:747:747) (772:772:772)) - (PORT datac (1394:1394:1394) (1464:1464:1464)) - (PORT datad (1189:1189:1189) (1225:1225:1225)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (929:929:929) (1006:1006:1006)) - (PORT datab (1150:1150:1150) (1220:1220:1220)) - (PORT datac (733:733:733) (829:829:829)) - (PORT datad (1883:1883:1883) (2044:2044:2044)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~7) - (DELAY - (ABSOLUTE - (PORT dataa (737:737:737) (802:802:802)) - (PORT datab (1392:1392:1392) (1509:1509:1509)) - (PORT datac (1112:1112:1112) (1157:1157:1157)) - (PORT datad (198:198:198) (235:235:235)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (653:653:653) (668:668:668)) - (PORT datab (819:819:819) (840:840:840)) - (PORT datac (1123:1123:1123) (1137:1137:1137)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_pf_we\~9) - (DELAY - (ABSOLUTE - (PORT dataa (674:674:674) (696:696:696)) - (PORT datab (1031:1031:1031) (1083:1083:1083)) - (PORT datac (562:562:562) (584:584:584)) - (PORT datad (901:901:901) (957:957:957)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~0) - (DELAY - (ABSOLUTE - (PORT dataa (704:704:704) (741:741:741)) - (PORT datab (618:618:618) (633:633:633)) - (PORT datac (237:237:237) (315:315:315)) - (PORT datad (181:181:181) (212:212:212)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1120:1120:1120) (1156:1156:1156)) - (PORT datab (746:746:746) (770:770:770)) - (PORT datac (899:899:899) (956:956:956)) - (PORT datad (1169:1169:1169) (1206:1206:1206)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1433:1433:1433) (1488:1488:1488)) - (PORT datab (677:677:677) (711:711:711)) - (PORT datac (171:171:171) (203:203:203)) - (PORT datad (1402:1402:1402) (1440:1440:1440)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1422:1422:1422) (1463:1463:1463)) - (PORT datab (746:746:746) (770:770:770)) - (PORT datac (1125:1125:1125) (1193:1193:1193)) - (PORT datad (171:171:171) (196:196:196)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~0) - (DELAY - (ABSOLUTE - (PORT dataa (415:415:415) (496:496:496)) - (PORT datab (268:268:268) (357:357:357)) - (PORT datac (230:230:230) (313:313:313)) - (PORT datad (609:609:609) (655:655:655)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~3) - (DELAY - (ABSOLUTE - (PORT dataa (845:845:845) (908:908:908)) - (PORT datab (730:730:730) (816:816:816)) - (PORT datad (395:395:395) (453:453:453)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~2) - (DELAY - (ABSOLUTE - (PORT dataa (422:422:422) (513:513:513)) - (PORT datab (390:390:390) (465:465:465)) - (PORT datac (675:675:675) (735:735:735)) - (PORT datad (679:679:679) (752:752:752)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~1) - (DELAY - (ABSOLUTE - (PORT dataa (269:269:269) (367:367:367)) - (PORT datab (598:598:598) (665:665:665)) - (PORT datac (245:245:245) (334:334:334)) - (PORT datad (371:371:371) (425:425:425)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~4) - (DELAY - (ABSOLUTE - (PORT dataa (587:587:587) (599:599:599)) - (PORT datab (914:914:914) (923:923:923)) - (PORT datac (565:565:565) (580:580:580)) - (PORT datad (307:307:307) (323:323:323)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1424:1424:1424) (1466:1466:1466)) - (PORT datab (1535:1535:1535) (1597:1597:1597)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|DFFE_instNonRep) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1580:1580:1580) (1559:1559:1559)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1118:1118:1118) (1158:1158:1158)) - (PORT datab (675:675:675) (710:710:710)) - (PORT datac (900:900:900) (960:960:960)) - (PORT datad (1167:1167:1167) (1206:1206:1206)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~2) - (DELAY - (ABSOLUTE - (PORT dataa (979:979:979) (1040:1040:1040)) - (PORT datab (271:271:271) (356:356:356)) - (PORT datac (1122:1122:1122) (1190:1190:1190)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~3) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (746:746:746) (769:769:769)) - (PORT datac (1390:1390:1390) (1425:1425:1425)) - (PORT datad (245:245:245) (316:316:316)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_control_\|DFFE_latch_pf_tmp) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1535:1535:1535)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1283:1283:1283) (1287:1287:1287)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|SYNTHESIZED_WIRE_1) (DELAY (ABSOLUTE - (PORT dataa (221:221:221) (264:264:264)) - (PORT datab (214:214:214) (259:259:259)) - (PORT datac (179:179:179) (216:216:216)) - (PORT datad (181:181:181) (210:210:210)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (398:398:398) (425:425:425)) + (PORT datab (206:206:206) (246:246:246)) + (PORT datac (1090:1090:1090) (1110:1110:1110)) + (PORT datad (188:188:188) (218:218:218)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -26619,12 +18872,12 @@ (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_1\|result\~0) (DELAY (ABSOLUTE - (PORT dataa (545:545:545) (570:570:570)) - (PORT datab (213:213:213) (257:257:257)) - (PORT datac (177:177:177) (214:214:214)) - (PORT datad (173:173:173) (197:197:197)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT dataa (399:399:399) (426:426:426)) + (PORT datab (345:345:345) (377:377:377)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (189:189:189) (221:221:221)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -26632,43 +18885,30 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_parity_out\~0) + (INSTANCE z80_\|alu_\|db_high\[1\]\~14) (DELAY (ABSOLUTE - (PORT dataa (813:813:813) (826:826:826)) - (PORT datac (328:328:328) (358:358:358)) - (PORT datad (196:196:196) (221:221:221)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (280:280:280) (355:355:355)) + (PORT datab (281:281:281) (340:340:340)) + (PORT datac (1112:1112:1112) (1120:1120:1120)) + (PORT datad (247:247:247) (291:291:291)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|alu_parity_out) + (INSTANCE z80_\|alu_\|db_high\[1\]\~15) (DELAY (ABSOLUTE - (PORT dataa (350:350:350) (381:381:381)) - (PORT datab (662:662:662) (697:697:697)) - (PORT datad (172:172:172) (198:198:198)) + (PORT dataa (246:246:246) (301:301:301)) + (PORT datab (876:876:876) (938:938:938)) + (PORT datac (603:603:603) (612:612:612)) + (PORT datad (566:566:566) (620:620:620)) (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1118:1118:1118) (1161:1161:1161)) - (PORT datab (1154:1154:1154) (1224:1224:1224)) - (PORT datac (1392:1392:1392) (1427:1427:1427)) - (PORT datad (1169:1169:1169) (1209:1209:1209)) - (IOPATH dataa combout (341:341:341) (319:319:319)) (IOPATH datab combout (342:342:342) (318:318:318)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -26677,1089 +18917,88 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~8) + (INSTANCE z80_\|alu_\|db_high\[1\]\~16) (DELAY (ABSOLUTE - (PORT dataa (933:933:933) (998:998:998)) - (PORT datab (748:748:748) (772:772:772)) - (PORT datac (646:646:646) (675:675:675)) - (PORT datad (174:174:174) (200:200:200)) + (PORT dataa (563:563:563) (593:593:593)) + (PORT datac (954:954:954) (1041:1041:1041)) + (PORT datad (347:347:347) (371:371:371)) (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~9) + (INSTANCE z80_\|alu_\|db_high\[1\]\~17) (DELAY (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (198:198:198) (238:238:238)) - (PORT datac (1374:1374:1374) (1429:1429:1429)) + (PORT dataa (838:838:838) (862:862:862)) + (PORT datab (639:639:639) (654:654:654)) + (PORT datad (1108:1108:1108) (1130:1130:1130)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (640:640:640) (666:666:666)) + (PORT datab (640:640:640) (663:663:663)) + (PORT datac (696:696:696) (745:745:745)) + (PORT datad (595:595:595) (635:635:635)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[1\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (870:870:870) (932:932:932)) + (PORT datab (678:678:678) (709:709:709)) + (PORT datac (342:342:342) (367:367:367)) (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~10) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (254:254:254)) - (PORT datab (341:341:341) (367:367:367)) - (PORT datac (1214:1214:1214) (1255:1255:1255)) - (PORT datad (677:677:677) (698:698:698)) (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf) - (DELAY - (ABSOLUTE - (PORT clk (1514:1514:1514) (1528:1528:1528)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|sel\[1\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (922:922:922) (946:946:946)) - (PORT datab (2012:2012:2012) (2066:2066:2066)) - (PORT datac (919:919:919) (1015:1015:1015)) - (PORT datad (863:863:863) (877:877:877)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11\~2) - (DELAY - (ABSOLUTE - (PORT dataa (409:409:409) (447:447:447)) - (PORT datab (1195:1195:1195) (1198:1198:1198)) - (PORT datac (601:601:601) (607:607:607)) - (PORT datad (334:334:334) (359:359:359)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_12) - (DELAY - (ABSOLUTE - (PORT dataa (825:825:825) (855:855:855)) - (PORT datad (337:337:337) (354:354:354)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11\~0) - (DELAY - (ABSOLUTE - (PORT dataa (224:224:224) (278:278:278)) - (PORT datab (223:223:223) (271:271:271)) - (PORT datac (616:616:616) (645:645:645)) - (PORT datad (216:216:216) (258:258:258)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11\~1) - (DELAY - (ABSOLUTE - (PORT dataa (592:592:592) (621:621:621)) - (PORT datab (686:686:686) (701:701:701)) - (PORT datac (562:562:562) (583:583:583)) - (PORT datad (312:312:312) (322:322:322)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_37\~0) - (DELAY - (ABSOLUTE - (PORT dataa (622:622:622) (661:661:661)) - (PORT datab (654:654:654) (674:674:674)) - (PORT datac (240:240:240) (317:317:317)) - (PORT datad (385:385:385) (407:407:407)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_37\~1) - (DELAY - (ABSOLUTE - (PORT dataa (646:646:646) (692:692:692)) - (PORT datab (199:199:199) (239:239:239)) - (PORT datac (610:610:610) (651:651:651)) - (PORT datad (176:176:176) (202:202:202)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_39) - (DELAY - (ABSOLUTE - (PORT clk (1517:1517:1517) (1530:1530:1530)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1244:1244:1244) (1250:1250:1250)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|b2v_inst_cond_mux\|out\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1638:1638:1638) (1703:1703:1703)) - (PORT datab (222:222:222) (261:261:261)) - (PORT datac (181:181:181) (218:218:218)) - (PORT datad (884:884:884) (949:949:949)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|b2v_inst_cond_mux\|out\~1) - (DELAY - (ABSOLUTE - (PORT dataa (669:669:669) (747:747:747)) - (PORT datab (659:659:659) (717:717:717)) - (PORT datac (181:181:181) (218:218:218)) - (PORT datad (172:172:172) (198:198:198)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|flags_cond_true\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1816:1816:1816) (1911:1911:1911)) - (PORT datab (2014:2014:2014) (2068:2068:2068)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_control_\|flags_cond_true) - (DELAY - (ABSOLUTE - (PORT clk (1514:1514:1514) (1527:1527:1527)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~13) - (DELAY - (ABSOLUTE - (PORT dataa (629:629:629) (663:663:663)) - (PORT datab (1772:1772:1772) (1863:1863:1863)) - (PORT datac (1815:1815:1815) (1893:1893:1893)) - (PORT datad (552:552:552) (570:570:570)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~14) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (256:256:256)) - (PORT datab (230:230:230) (280:280:280)) - (PORT datac (563:563:563) (592:592:592)) - (PORT datad (181:181:181) (211:211:211)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~17) - (DELAY - (ABSOLUTE - (PORT dataa (888:888:888) (905:905:905)) - (PORT datab (221:221:221) (261:261:261)) - (PORT datac (623:623:623) (650:650:650)) - (PORT datad (1193:1193:1193) (1247:1247:1247)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_82) - (DELAY - (ABSOLUTE - (PORT dataa (629:629:629) (658:658:658)) - (PORT datab (949:949:949) (994:994:994)) - (PORT datad (671:671:671) (699:699:699)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (640:640:640) (694:694:694)) - (PORT datab (517:517:517) (537:537:537)) - (PORT datac (742:742:742) (744:744:744)) - (PORT datad (1107:1107:1107) (1107:1107:1107)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (545:545:545) (573:573:573)) - (PORT datab (199:199:199) (239:239:239)) - (PORT datac (580:580:580) (606:606:606)) - (PORT datad (621:621:621) (643:643:643)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (198:198:198) (242:242:242)) - (PORT datab (259:259:259) (310:310:310)) - (PORT datac (607:607:607) (617:617:617)) - (PORT datad (236:236:236) (276:276:276)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1545:1545:1545)) - (PORT asdata (1881:1881:1881) (1885:1885:1885)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1544:1544:1544)) - (PORT asdata (1836:1836:1836) (1841:1841:1841)) - (PORT ena (1231:1231:1231) (1217:1217:1217)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (434:434:434) (465:465:465)) - (PORT datab (378:378:378) (448:448:448)) - (PORT datad (608:608:608) (629:629:629)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1544:1544:1544)) - (PORT asdata (1836:1836:1836) (1841:1841:1841)) - (PORT ena (1499:1499:1499) (1507:1507:1507)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1520:1520:1520) (1534:1534:1534)) - (PORT asdata (2122:2122:2122) (2138:2138:2138)) - (PORT ena (1207:1207:1207) (1190:1190:1190)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1535:1535:1535)) - (PORT asdata (2124:2124:2124) (2160:2160:2160)) - (PORT ena (841:841:841) (846:846:846)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (462:462:462) (498:498:498)) - (PORT datab (667:667:667) (706:706:706)) - (PORT datad (632:632:632) (685:685:685)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~27) - (DELAY - (ABSOLUTE - (PORT datab (1411:1411:1411) (1423:1423:1423)) - (PORT datad (585:585:585) (594:594:594)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1545:1545:1545)) - (PORT asdata (1880:1880:1880) (1884:1884:1884)) - (PORT ena (1220:1220:1220) (1214:1214:1214)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (657:657:657) (709:709:709)) - (PORT datab (945:945:945) (994:994:994)) - (PORT datac (888:888:888) (910:910:910)) - (PORT datad (609:609:609) (625:625:625)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1545:1545:1545)) - (PORT asdata (1630:1630:1630) (1644:1644:1644)) - (PORT ena (821:821:821) (834:834:834)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (823:823:823) (864:864:864)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1266:1266:1266) (1269:1269:1269)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (412:412:412) (473:473:473)) - (PORT datab (583:583:583) (621:621:621)) - (PORT datad (584:584:584) (628:628:628)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (246:246:246)) - (PORT datab (200:200:200) (239:239:239)) - (PORT datac (170:170:170) (202:202:202)) - (PORT datad (551:551:551) (556:556:556)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1532:1532:1532) (1549:1549:1549)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1413:1413:1413) (1385:1385:1385)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1531:1531:1531)) - (PORT asdata (1857:1857:1857) (1863:1863:1863)) - (PORT ena (1734:1734:1734) (1719:1719:1719)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (242:242:242) (328:328:328)) - (PORT datab (962:962:962) (1016:1016:1016)) - (PORT datad (847:847:847) (873:873:873)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (712:712:712) (740:740:740)) - (PORT ena (811:811:811) (804:804:804)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1523:1523:1523) (1536:1536:1536)) - (PORT asdata (712:712:712) (740:740:740)) - (PORT ena (841:841:841) (846:846:846)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (243:243:243) (329:329:329)) - (PORT datab (263:263:263) (316:316:316)) - (PORT datad (234:234:234) (273:273:273)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (684:684:684) (726:726:726)) - (PORT datab (635:635:635) (674:674:674)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (1349:1349:1349) (1373:1373:1373)) - (PORT datab (623:623:623) (653:653:653)) - (PORT datac (643:643:643) (694:694:694)) - (PORT datad (308:308:308) (323:323:323)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_ds\[1\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1481:1481:1481) (1531:1531:1531)) - (PORT datab (1644:1644:1644) (1715:1715:1715)) - (PORT datac (1522:1522:1522) (1538:1538:1538)) - (PORT datad (1165:1165:1165) (1205:1205:1205)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[1\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (978:978:978) (996:996:996)) - (PORT datab (878:878:878) (913:913:913)) - (PORT datac (923:923:923) (978:978:978)) - (PORT datad (879:879:879) (914:914:914)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[1\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (696:696:696) (721:721:721)) - (PORT datab (1150:1150:1150) (1186:1186:1186)) - (PORT datac (887:887:887) (975:975:975)) - (PORT datad (1184:1184:1184) (1219:1219:1219)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[1\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (203:203:203) (248:248:248)) - (PORT datab (943:943:943) (996:996:996)) - (PORT datac (648:648:648) (674:674:674)) - (PORT datad (172:172:172) (198:198:198)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[1\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1303:1303:1303) (1352:1352:1352)) - (PORT datab (933:933:933) (975:975:975)) - (PORT datac (1446:1446:1446) (1491:1491:1491)) - (PORT datad (926:926:926) (983:983:983)) - (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[1\]\~13) + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[1\]\~4) (DELAY (ABSOLUTE - (PORT dataa (204:204:204) (248:248:248)) - (PORT datab (986:986:986) (1033:1033:1033)) - (PORT datac (900:900:900) (933:933:933)) - (PORT datad (222:222:222) (267:267:267)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1695:1695:1695) (1783:1783:1783)) - (PORT datac (897:897:897) (925:925:925)) - (PORT datad (364:364:364) (385:385:385)) + (PORT dataa (948:948:948) (982:982:982)) + (PORT datab (886:886:886) (904:904:904)) + (PORT datac (647:647:647) (670:670:670)) + (PORT datad (613:613:613) (642:642:642)) (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~22) - (DELAY - (ABSOLUTE - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (926:926:926) (952:952:952)) - (PORT datad (237:237:237) (274:274:274)) (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1179:1179:1179) (1212:1212:1212)) - (PORT datab (286:286:286) (347:347:347)) - (PORT datac (254:254:254) (311:311:311)) - (PORT datad (254:254:254) (300:300:300)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (432:432:432) (525:525:525)) - (PORT datab (1170:1170:1170) (1217:1217:1217)) - (PORT datac (1156:1156:1156) (1212:1212:1212)) - (PORT datad (661:661:661) (724:724:724)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|result_lo\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1535:1535:1535)) - (PORT asdata (672:672:672) (698:698:698)) - (PORT ena (1283:1283:1283) (1287:1287:1287)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (632:632:632) (638:638:638)) - (PORT datab (368:368:368) (389:389:389)) - (PORT datad (1139:1139:1139) (1146:1146:1146)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[0\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (587:587:587) (597:597:597)) - (PORT datab (220:220:220) (258:258:258)) - (PORT datac (1124:1124:1124) (1146:1146:1146)) - (PORT datad (335:335:335) (355:355:355)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[0\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (1292:1292:1292) (1345:1345:1345)) - (PORT datab (915:915:915) (937:937:937)) - (PORT datac (1123:1123:1123) (1144:1144:1144)) - (PORT datad (945:945:945) (995:995:995)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[0\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (964:964:964) (1020:1020:1020)) - (PORT datac (806:806:806) (813:813:813)) - (PORT datad (227:227:227) (273:273:273)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (970:970:970) (999:999:999)) - (PORT datac (1663:1663:1663) (1739:1739:1739)) - (PORT datad (1415:1415:1415) (1442:1442:1442)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (243:243:243)) - (PORT datac (902:902:902) (931:931:931)) - (PORT datad (239:239:239) (281:281:281)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1179:1179:1179) (1211:1211:1211)) - (PORT datab (286:286:286) (349:349:349)) - (PORT datac (255:255:255) (313:313:313)) - (PORT datad (248:248:248) (293:293:293)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (671:671:671) (728:728:728)) - (PORT datab (1171:1171:1171) (1217:1217:1217)) - (PORT datac (615:615:615) (673:673:673)) - (PORT datad (661:661:661) (723:723:723)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|result_lo\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1535:1535:1535)) - (PORT asdata (1127:1127:1127) (1132:1132:1132)) - (PORT ena (1283:1283:1283) (1287:1287:1287)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (549:549:549) (578:578:578)) - (PORT datab (331:331:331) (362:362:362)) - (PORT datad (1138:1138:1138) (1145:1145:1145)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[1\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (683:683:683) (703:703:703)) - (PORT datab (359:359:359) (389:389:389)) - (PORT datac (797:797:797) (800:800:800)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[1\]\~5) (DELAY (ABSOLUTE - (PORT dataa (588:588:588) (619:619:619)) - (PORT datab (968:968:968) (1015:1015:1015)) - (PORT datac (371:371:371) (403:403:403)) - (PORT datad (863:863:863) (917:917:917)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[1\]\~6) - (DELAY - (ABSOLUTE - (PORT datac (173:173:173) (207:207:207)) - (PORT datad (681:681:681) (721:721:721)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT datac (895:895:895) (917:917:917)) + (PORT datad (173:173:173) (197:197:197)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -27769,9 +19008,9 @@ (INSTANCE z80_\|alu_\|op1_low\[1\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1531:1531:1531)) + (PORT clk (1547:1547:1547) (1549:1549:1549)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (790:790:790) (782:782:782)) + (PORT ena (794:794:794) (792:792:792)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -27785,10 +19024,5562 @@ (INSTANCE z80_\|alu_control_\|out\[6\]\~0) (DELAY (ABSOLUTE - (PORT datab (264:264:264) (346:346:346)) + (PORT dataa (264:264:264) (350:350:350)) (PORT datac (235:235:235) (311:311:311)) - (PORT datad (235:235:235) (303:303:303)) + (PORT datad (257:257:257) (326:326:326)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|out\[6\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (903:903:903) (994:994:994)) + (PORT datab (883:883:883) (922:922:922)) + (PORT datac (898:898:898) (995:995:995)) + (PORT datad (849:849:849) (924:924:924)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|out\[6\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (212:212:212) (257:257:257)) + (PORT datac (674:674:674) (774:774:774)) + (PORT datad (860:860:860) (934:934:934)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_12) + (DELAY + (ABSOLUTE + (PORT datac (675:675:675) (703:703:703)) + (PORT datad (855:855:855) (888:888:888)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_37\~0) + (DELAY + (ABSOLUTE + (PORT dataa (274:274:274) (365:365:365)) + (PORT datab (2171:2171:2171) (2260:2260:2260)) + (PORT datac (924:924:924) (952:952:952)) + (PORT datad (2241:2241:2241) (2306:2306:2306)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11\~2) + (DELAY + (ABSOLUTE + (PORT dataa (715:715:715) (761:761:761)) + (PORT datab (690:690:690) (730:730:730)) + (PORT datac (620:620:620) (647:647:647)) + (PORT datad (614:614:614) (644:644:644)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11\~0) + (DELAY + (ABSOLUTE + (PORT dataa (697:697:697) (718:718:718)) + (PORT datab (371:371:371) (402:402:402)) + (PORT datac (193:193:193) (227:227:227)) + (PORT datad (180:180:180) (209:209:209)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_11\~1) + (DELAY + (ABSOLUTE + (PORT dataa (367:367:367) (405:405:405)) + (PORT datab (898:898:898) (920:920:920)) + (PORT datac (363:363:363) (385:385:385)) + (PORT datad (341:341:341) (360:360:360)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_37\~1) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (242:242:242)) + (PORT datab (198:198:198) (238:238:238)) + (PORT datac (833:833:833) (847:847:847)) + (PORT datad (337:337:337) (358:358:358)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~7) + (DELAY + (ABSOLUTE + (PORT datac (1455:1455:1455) (1533:1533:1533)) + (PORT datad (575:575:575) (600:600:600)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_sz_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1186:1186:1186) (1211:1211:1211)) + (PORT datab (887:887:887) (918:918:918)) + (PORT datac (319:319:319) (353:353:353)) + (PORT datad (609:609:609) (640:640:640)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_39) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1218:1218:1218) (1200:1200:1200)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~51) + (DELAY + (ABSOLUTE + (PORT dataa (1441:1441:1441) (1461:1461:1461)) + (PORT datab (868:868:868) (922:922:922)) + (PORT datac (857:857:857) (873:873:873)) + (PORT datad (884:884:884) (896:896:896)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_oe\~2) + (DELAY + (ABSOLUTE + (PORT dataa (584:584:584) (599:599:599)) + (PORT datab (866:866:866) (904:904:904)) + (PORT datac (982:982:982) (1018:1018:1018)) + (PORT datad (1154:1154:1154) (1183:1183:1183)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_2u\~7) + (DELAY + (ABSOLUTE + (PORT dataa (878:878:878) (924:924:924)) + (PORT datab (1320:1320:1320) (1374:1374:1374)) + (PORT datac (822:822:822) (818:818:818)) + (PORT datad (553:553:553) (557:557:557)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[6\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (898:898:898) (922:922:922)) + (PORT datab (708:708:708) (776:776:776)) + (PORT datac (834:834:834) (845:845:845)) + (PORT datad (544:544:544) (559:559:559)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[6\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (1136:1136:1136) (1152:1152:1152)) + (PORT datab (214:214:214) (259:259:259)) + (PORT datac (187:187:187) (227:227:227)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_out_lo\~8) + (DELAY + (ABSOLUTE + (PORT dataa (822:822:822) (850:850:850)) + (PORT datab (1119:1119:1119) (1158:1158:1158)) + (PORT datac (650:650:650) (674:674:674)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[6\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (864:864:864) (895:895:895)) + (PORT datab (883:883:883) (901:901:901)) + (PORT datac (635:635:635) (694:694:694)) + (PORT datad (1043:1043:1043) (1071:1071:1071)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[6\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (266:266:266)) + (PORT datab (412:412:412) (439:439:439)) + (PORT datac (364:364:364) (397:397:397)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[6\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (197:197:197) (237:237:237)) + (PORT datac (335:335:335) (357:357:357)) + (PORT datad (364:364:364) (391:391:391)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[6\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (650:650:650) (679:679:679)) + (PORT datab (935:935:935) (951:951:951)) + (PORT datac (592:592:592) (608:608:608)) + (PORT datad (681:681:681) (707:707:707)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[6\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (747:747:747) (776:776:776)) + (PORT datab (257:257:257) (318:318:318)) + (PORT datac (856:856:856) (874:874:874)) + (PORT datad (176:176:176) (201:201:201)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1533:1533:1533)) + (PORT asdata (1436:1436:1436) (1451:1451:1451)) + (PORT ena (1201:1201:1201) (1198:1198:1198)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~80) + (DELAY + (ABSOLUTE + (PORT dataa (1197:1197:1197) (1218:1218:1218)) + (PORT datab (1143:1143:1143) (1170:1170:1170)) + (PORT datad (394:394:394) (433:433:433)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT asdata (1261:1261:1261) (1297:1297:1297)) + (PORT ena (1229:1229:1229) (1240:1240:1240)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT asdata (1266:1266:1266) (1301:1301:1301)) + (PORT ena (1168:1168:1168) (1147:1147:1147)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~79) + (DELAY + (ABSOLUTE + (PORT dataa (694:694:694) (730:730:730)) + (PORT datab (269:269:269) (324:324:324)) + (PORT datad (218:218:218) (287:287:287)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (1436:1436:1436) (1448:1448:1448)) + (PORT ena (1225:1225:1225) (1236:1236:1236)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1089:1089:1089) (1102:1102:1102)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1440:1440:1440) (1419:1419:1419)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~78) + (DELAY + (ABSOLUTE + (PORT dataa (701:701:701) (760:760:760)) + (PORT datab (657:657:657) (680:680:680)) + (PORT datad (216:216:216) (284:284:284)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~82) + (DELAY + (ABSOLUTE + (PORT dataa (846:846:846) (871:871:871)) + (PORT datab (552:552:552) (566:566:566)) + (PORT datac (573:573:573) (568:568:568)) + (PORT datad (340:340:340) (366:366:366)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1530:1530:1530)) + (PORT asdata (1184:1184:1184) (1204:1204:1204)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|db\[6\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1425:1425:1425) (1489:1489:1489)) + (PORT datab (1191:1191:1191) (1211:1211:1211)) + (PORT datad (825:825:825) (851:851:851)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (889:889:889) (925:925:925)) + (PORT ena (1277:1277:1277) (1271:1271:1271)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (936:936:936) (959:959:959)) + (PORT ena (981:981:981) (980:980:980)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (583:583:583) (602:602:602)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1190:1190:1190) (1164:1164:1164)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~76) + (DELAY + (ABSOLUTE + (PORT dataa (697:697:697) (733:733:733)) + (PORT datab (696:696:696) (722:722:722)) + (PORT datad (216:216:216) (285:285:285)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~77) + (DELAY + (ABSOLUTE + (PORT dataa (637:637:637) (673:673:673)) + (PORT datab (612:612:612) (640:640:640)) + (PORT datad (337:337:337) (356:356:356)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~83) + (DELAY + (ABSOLUTE + (PORT dataa (244:244:244) (331:331:331)) + (PORT datab (207:207:207) (249:249:249)) + (PORT datac (564:564:564) (575:575:575)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[6\]\~84) + (DELAY + (ABSOLUTE + (PORT dataa (864:864:864) (911:911:911)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (1098:1098:1098) (1107:1107:1107)) + (PORT datad (605:605:605) (620:620:620)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1532:1532:1532)) + (PORT asdata (676:676:676) (691:691:691)) + (PORT ena (1224:1224:1224) (1225:1225:1225)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (683:683:683) (713:713:713)) + (PORT datab (894:894:894) (926:926:926)) + (PORT datad (630:630:630) (653:653:653)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1279:1279:1279) (1290:1290:1290)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (384:384:384)) + (PORT datab (243:243:243) (324:324:324)) + (PORT datad (1051:1051:1051) (1065:1065:1065)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[13\]) + (DELAY + (ABSOLUTE + (PORT dataa (628:628:628) (669:669:669)) + (PORT datad (1092:1092:1092) (1096:1096:1096)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1561:1561:1561) (1543:1543:1543)) + (PORT ena (1886:1886:1886) (1891:1891:1891)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|d0_out) + (DELAY + (ABSOLUTE + (PORT dataa (425:425:425) (505:505:505)) + (PORT datab (214:214:214) (259:259:259)) + (PORT datac (655:655:655) (700:700:700)) + (PORT datad (409:409:409) (474:474:474)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT asdata (1215:1215:1215) (1236:1236:1236)) + (PORT ena (1229:1229:1229) (1240:1240:1240)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT asdata (1215:1215:1215) (1239:1239:1239)) + (PORT ena (1168:1168:1168) (1147:1147:1147)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~61) + (DELAY + (ABSOLUTE + (PORT dataa (694:694:694) (729:729:729)) + (PORT datab (271:271:271) (330:330:330)) + (PORT datad (215:215:215) (283:283:283)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1533:1533:1533)) + (PORT asdata (1878:1878:1878) (1923:1923:1923)) + (PORT ena (1201:1201:1201) (1198:1198:1198)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~62) + (DELAY + (ABSOLUTE + (PORT dataa (1203:1203:1203) (1222:1222:1222)) + (PORT datab (894:894:894) (936:936:936)) + (PORT datad (397:397:397) (440:440:440)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (1161:1161:1161) (1187:1187:1187)) + (PORT ena (1225:1225:1225) (1236:1236:1236)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (619:619:619) (636:636:636)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1440:1440:1440) (1419:1419:1419)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~60) + (DELAY + (ABSOLUTE + (PORT dataa (701:701:701) (759:759:759)) + (PORT datab (660:660:660) (686:686:686)) + (PORT datad (214:214:214) (282:282:282)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1533:1533:1533)) + (PORT asdata (1712:1712:1712) (1726:1726:1726)) + (PORT ena (1227:1227:1227) (1249:1249:1249)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1533:1533:1533)) + (PORT asdata (1711:1711:1711) (1726:1726:1726)) + (PORT ena (1503:1503:1503) (1497:1497:1497)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~63) + (DELAY + (ABSOLUTE + (PORT dataa (701:701:701) (776:776:776)) + (PORT datab (241:241:241) (322:322:322)) + (PORT datad (698:698:698) (745:745:745)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~64) + (DELAY + (ABSOLUTE + (PORT dataa (578:578:578) (599:599:599)) + (PORT datab (597:597:597) (621:621:621)) + (PORT datac (611:611:611) (632:632:632)) + (PORT datad (311:311:311) (330:330:330)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (790:790:790) (782:782:782)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1530:1530:1530)) + (PORT asdata (1340:1340:1340) (1368:1368:1368)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|db\[4\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1429:1429:1429) (1490:1490:1490)) + (PORT datab (1191:1191:1191) (1208:1208:1208)) + (PORT datad (822:822:822) (848:848:848)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (926:926:926) (946:946:946)) + (PORT ena (1277:1277:1277) (1271:1271:1271)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (675:675:675) (703:703:703)) + (PORT ena (1190:1190:1190) (1164:1164:1164)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (678:678:678) (706:706:706)) + (PORT ena (981:981:981) (980:980:980)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~58) + (DELAY + (ABSOLUTE + (PORT dataa (698:698:698) (730:730:730)) + (PORT datab (242:242:242) (324:324:324)) + (PORT datad (622:622:622) (632:632:632)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~59) + (DELAY + (ABSOLUTE + (PORT dataa (637:637:637) (673:673:673)) + (PORT datab (638:638:638) (657:657:657)) + (PORT datad (339:339:339) (359:359:359)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~65) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (207:207:207) (248:248:248)) + (PORT datac (216:216:216) (292:292:292)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[4\]\~66) + (DELAY + (ABSOLUTE + (PORT dataa (864:864:864) (908:908:908)) + (PORT datab (925:925:925) (935:935:935)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (608:608:608) (619:619:619)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1532:1532:1532)) + (PORT asdata (671:671:671) (693:693:693)) + (PORT ena (1224:1224:1224) (1225:1225:1225)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (682:682:682) (711:711:711)) + (PORT datab (1220:1220:1220) (1264:1264:1264)) + (PORT datad (630:630:630) (653:653:653)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1279:1279:1279) (1290:1290:1290)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (198:198:198) (241:241:241)) + (PORT datab (244:244:244) (327:327:327)) + (PORT datad (1054:1054:1054) (1068:1068:1068)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[4\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (654:654:654) (675:675:675)) + (PORT datab (199:199:199) (239:239:239)) + (PORT datac (582:582:582) (610:610:610)) + (PORT datad (1332:1332:1332) (1347:1347:1347)) + (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[12\]) + (DELAY + (ABSOLUTE + (PORT dataa (673:673:673) (695:695:695)) + (PORT datac (594:594:594) (625:625:625)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1561:1561:1561) (1543:1543:1543)) + (PORT ena (1886:1886:1886) (1891:1891:1891)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|SYNTHESIZED_WIRE_0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (425:425:425) (505:505:505)) + (PORT datab (214:214:214) (260:260:260)) + (PORT datac (655:655:655) (700:700:700)) + (PORT datad (408:408:408) (474:474:474)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[14\]) + (DELAY + (ABSOLUTE + (PORT dataa (433:433:433) (506:506:506)) + (PORT datab (860:860:860) (882:882:882)) + (PORT datac (236:236:236) (325:325:325)) + (PORT datad (344:344:344) (368:368:368)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[6\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (1357:1357:1357) (1390:1390:1390)) + (PORT datab (611:611:611) (644:644:644)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (627:627:627) (643:643:643)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[14\]) + (DELAY + (ABSOLUTE + (PORT datac (596:596:596) (626:626:626)) + (PORT datad (622:622:622) (640:640:640)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1561:1561:1561) (1543:1543:1543)) + (PORT ena (1886:1886:1886) (1891:1891:1891)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[15\]) + (DELAY + (ABSOLUTE + (PORT dataa (630:630:630) (666:666:666)) + (PORT datad (611:611:611) (624:624:624)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1561:1561:1561) (1543:1543:1543)) + (PORT ena (1886:1886:1886) (1891:1891:1891)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[15\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (244:244:244) (302:302:302)) + (PORT datab (224:224:224) (273:273:273)) + (PORT datac (586:586:586) (607:607:607)) + (PORT datad (683:683:683) (737:737:737)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[15\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (272:272:272) (369:369:369)) + (PORT datab (859:859:859) (881:881:881)) + (PORT datac (375:375:375) (442:442:442)) + (PORT datad (597:597:597) (606:606:606)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1279:1279:1279) (1290:1290:1290)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1532:1532:1532)) + (PORT asdata (893:893:893) (906:906:906)) + (PORT ena (1224:1224:1224) (1225:1225:1225)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (684:684:684) (713:713:713)) + (PORT datab (667:667:667) (692:692:692)) + (PORT datad (1402:1402:1402) (1416:1416:1416)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (244:244:244) (332:332:332)) + (PORT datab (1076:1076:1076) (1105:1105:1105)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[7\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (1356:1356:1356) (1388:1388:1388)) + (PORT datab (362:362:362) (392:392:392)) + (PORT datac (579:579:579) (609:609:609)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (1446:1446:1446) (1450:1450:1450)) + (PORT ena (790:790:790) (782:782:782)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[7\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1537:1537:1537) (1586:1586:1586)) + (PORT datab (2171:2171:2171) (2210:2210:2210)) + (PORT datad (1367:1367:1367) (1389:1389:1389)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1533:1533:1533)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1503:1503:1503) (1497:1497:1497)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1533:1533:1533)) + (PORT asdata (535:535:535) (566:566:566)) + (PORT ena (1227:1227:1227) (1249:1249:1249)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~72) + (DELAY + (ABSOLUTE + (PORT dataa (701:701:701) (775:775:775)) + (PORT datab (645:645:645) (696:696:696)) + (PORT datad (698:698:698) (745:745:745)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1533:1533:1533)) + (PORT asdata (1651:1651:1651) (1665:1665:1665)) + (PORT ena (1201:1201:1201) (1198:1198:1198)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~71) + (DELAY + (ABSOLUTE + (PORT dataa (1203:1203:1203) (1222:1222:1222)) + (PORT datab (938:938:938) (968:968:968)) + (PORT datad (394:394:394) (437:437:437)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT asdata (1465:1465:1465) (1482:1482:1482)) + (PORT ena (1229:1229:1229) (1240:1240:1240)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT asdata (1465:1465:1465) (1481:1481:1481)) + (PORT ena (1168:1168:1168) (1147:1147:1147)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~70) + (DELAY + (ABSOLUTE + (PORT dataa (691:691:691) (730:730:730)) + (PORT datab (270:270:270) (329:329:329)) + (PORT datad (217:217:217) (285:285:285)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (1240:1240:1240) (1271:1271:1271)) + (PORT ena (1225:1225:1225) (1236:1236:1236)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (1237:1237:1237) (1268:1268:1268)) + (PORT ena (1440:1440:1440) (1419:1419:1419)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~69) + (DELAY + (ABSOLUTE + (PORT dataa (700:700:700) (762:762:762)) + (PORT datab (657:657:657) (681:681:681)) + (PORT datad (217:217:217) (285:285:285)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~73) + (DELAY + (ABSOLUTE + (PORT dataa (839:839:839) (851:851:851)) + (PORT datab (618:618:618) (634:634:634)) + (PORT datac (534:534:534) (537:537:537)) + (PORT datad (343:343:343) (365:365:365)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1530:1530:1530)) + (PORT asdata (917:917:917) (929:929:929)) + (PORT ena (1240:1240:1240) (1223:1223:1223)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1530:1530:1530)) + (PORT asdata (919:919:919) (932:932:932)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~68) + (DELAY + (ABSOLUTE + (PORT dataa (724:724:724) (754:754:754)) + (PORT datab (241:241:241) (323:323:323)) + (PORT datad (234:234:234) (272:272:272)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (1431:1431:1431) (1431:1431:1431)) + (PORT ena (981:981:981) (980:980:980)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (878:878:878) (903:903:903)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1190:1190:1190) (1164:1164:1164)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~67) + (DELAY + (ABSOLUTE + (PORT dataa (691:691:691) (724:724:724)) + (PORT datab (698:698:698) (718:718:718)) + (PORT datad (214:214:214) (283:283:283)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~74) + (DELAY + (ABSOLUTE + (PORT dataa (555:555:555) (577:577:577)) + (PORT datab (793:793:793) (854:854:854)) + (PORT datac (765:765:765) (799:799:799)) + (PORT datad (361:361:361) (384:384:384)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[7\]\~75) + (DELAY + (ABSOLUTE + (PORT dataa (846:846:846) (873:873:873)) + (PORT datab (921:921:921) (954:954:954)) + (PORT datac (1144:1144:1144) (1167:1167:1167)) + (PORT datad (557:557:557) (573:573:573)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[7\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (653:653:653) (677:677:677)) + (PORT datab (911:911:911) (921:921:921)) + (PORT datac (591:591:591) (605:605:605)) + (PORT datad (636:636:636) (650:650:650)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[7\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (747:747:747) (781:781:781)) + (PORT datab (259:259:259) (317:317:317)) + (PORT datac (896:896:896) (906:906:906)) + (PORT datad (178:178:178) (204:204:204)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (910:910:910) (932:932:932)) + (PORT datac (545:545:545) (573:573:573)) + (PORT datad (702:702:702) (798:798:798)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~1) + (DELAY + (ABSOLUTE + (PORT datab (200:200:200) (239:239:239)) + (PORT datac (186:186:186) (224:224:224)) + (PORT datad (1129:1129:1129) (1137:1137:1137)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~2) + (DELAY + (ABSOLUTE + (PORT dataa (867:867:867) (903:903:903)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (1106:1106:1106) (1114:1114:1114)) + (PORT datad (1128:1128:1128) (1135:1135:1135)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1136:1136:1136) (1150:1150:1150)) + (PORT datab (671:671:671) (726:726:726)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~8) + (DELAY + (ABSOLUTE + (PORT dataa (911:911:911) (984:984:984)) + (PORT datac (596:596:596) (629:629:629)) + (PORT datad (393:393:393) (441:441:441)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1166:1166:1166) (1214:1214:1214)) + (PORT datab (987:987:987) (1055:1055:1055)) + (PORT datac (315:315:315) (342:342:342)) + (PORT datad (907:907:907) (962:962:962)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~10) + (DELAY + (ABSOLUTE + (PORT dataa (2112:2112:2112) (2291:2291:2291)) + (PORT datab (1583:1583:1583) (1640:1640:1640)) + (PORT datac (1803:1803:1803) (1891:1891:1891)) + (PORT datad (956:956:956) (1070:1070:1070)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~11) + (DELAY + (ABSOLUTE + (PORT dataa (983:983:983) (1011:1011:1011)) + (PORT datab (622:622:622) (650:650:650)) + (PORT datac (2485:2485:2485) (2499:2499:2499)) + (PORT datad (580:580:580) (583:583:583)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1408:1408:1408) (1423:1423:1423)) + (PORT datab (379:379:379) (410:410:410)) + (PORT datac (1069:1069:1069) (1083:1083:1083)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~9) + (DELAY + (ABSOLUTE + (PORT dataa (617:617:617) (692:692:692)) + (PORT datab (1200:1200:1200) (1228:1228:1228)) + (PORT datac (610:610:610) (632:632:632)) + (PORT datad (672:672:672) (769:769:769)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~46) + (DELAY + (ABSOLUTE + (PORT dataa (1496:1496:1496) (1591:1591:1591)) + (PORT datab (1529:1529:1529) (1592:1592:1592)) + (PORT datad (1898:1898:1898) (2020:2020:2020)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~9) + (DELAY + (ABSOLUTE + (PORT dataa (631:631:631) (671:671:671)) + (PORT datab (220:220:220) (259:259:259)) + (PORT datac (186:186:186) (227:227:227)) + (PORT datad (642:642:642) (660:660:660)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~10) + (DELAY + (ABSOLUTE + (PORT dataa (924:924:924) (992:992:992)) + (PORT datab (862:862:862) (887:887:887)) + (PORT datac (909:909:909) (984:984:984)) + (PORT datad (211:211:211) (245:245:245)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1509:1509:1509) (1602:1602:1602)) + (PORT datab (207:207:207) (249:249:249)) + (PORT datac (803:803:803) (840:840:840)) + (PORT datad (607:607:607) (653:653:653)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1143:1143:1143) (1189:1189:1189)) + (PORT datab (660:660:660) (710:710:710)) + (PORT datac (579:579:579) (598:598:598)) + (PORT datad (625:625:625) (673:673:673)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~15) + (DELAY + (ABSOLUTE + (PORT dataa (2002:2002:2002) (2194:2194:2194)) + (PORT datab (1218:1218:1218) (1314:1314:1314)) + (PORT datac (965:965:965) (989:989:989)) + (PORT datad (1275:1275:1275) (1361:1361:1361)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1024:1024:1024) (1073:1073:1073)) + (PORT datab (236:236:236) (280:280:280)) + (PORT datac (314:314:314) (333:333:333)) + (PORT datad (1437:1437:1437) (1476:1476:1476)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~3) + (DELAY + (ABSOLUTE + (PORT dataa (627:627:627) (673:673:673)) + (PORT datab (1184:1184:1184) (1240:1240:1240)) + (PORT datac (817:817:817) (851:851:851)) + (PORT datad (1106:1106:1106) (1136:1136:1136)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|flags_cf) + (DELAY + (ABSOLUTE + (PORT dataa (652:652:652) (707:707:707)) + (PORT datab (854:854:854) (925:925:925)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (375:375:375) (406:406:406)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sw2_\|db_up\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT datac (874:874:874) (895:895:895)) + (PORT datad (546:546:546) (563:563:563)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[0\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (865:865:865) (891:891:891)) + (PORT datab (600:600:600) (623:623:623)) + (PORT datac (408:408:408) (452:452:452)) + (PORT datad (604:604:604) (618:618:618)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1231:1231:1231) (1237:1237:1237)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (675:675:675) (697:697:697)) + (PORT ena (1200:1200:1200) (1181:1181:1181)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (893:893:893) (937:937:937)) + (PORT datab (1242:1242:1242) (1275:1275:1275)) + (PORT datad (402:402:402) (438:438:438)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (245:245:245) (332:332:332)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (613:613:613) (631:631:631)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~70) + (DELAY + (ABSOLUTE + (PORT dataa (1002:1002:1002) (1055:1055:1055)) + (PORT datab (1627:1627:1627) (1636:1636:1636)) + (PORT datac (1549:1549:1549) (1655:1655:1655)) + (PORT datad (2773:2773:2773) (2972:2972:2972)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~28) + (DELAY + (ABSOLUTE + (PORT dataa (1714:1714:1714) (1799:1799:1799)) + (PORT datab (1830:1830:1830) (1927:1927:1927)) + (PORT datac (1212:1212:1212) (1288:1288:1288)) + (PORT datad (990:990:990) (1065:1065:1065)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1702:1702:1702) (1727:1727:1727)) + (PORT datab (904:904:904) (954:954:954)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (680:680:680) (736:736:736)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~27) + (DELAY + (ABSOLUTE + (PORT dataa (1711:1711:1711) (1798:1798:1798)) + (PORT datab (690:690:690) (747:747:747)) + (PORT datac (1216:1216:1216) (1291:1291:1291)) + (PORT datad (987:987:987) (1065:1065:1065)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~10) + (DELAY + (ABSOLUTE + (PORT dataa (982:982:982) (1056:1056:1056)) + (PORT datab (227:227:227) (268:268:268)) + (PORT datac (852:852:852) (906:906:906)) + (PORT datad (203:203:203) (233:233:233)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla38pla13M3T2_4) + (DELAY + (ABSOLUTE + (PORT dataa (979:979:979) (1051:1051:1051)) + (PORT datab (1662:1662:1662) (1751:1751:1751)) + (PORT datac (1100:1100:1100) (1120:1120:1120)) + (PORT datad (900:900:900) (918:918:918)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~11) + (DELAY + (ABSOLUTE + (PORT dataa (2808:2808:2808) (3011:3011:3011)) + (PORT datab (2312:2312:2312) (2341:2341:2341)) + (PORT datac (1243:1243:1243) (1275:1275:1275)) + (PORT datad (1270:1270:1270) (1307:1307:1307)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_pla40M3T2_4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1202:1202:1202) (1238:1238:1238)) + (PORT datab (1183:1183:1183) (1320:1320:1320)) + (PORT datac (960:960:960) (1033:1033:1033)) + (PORT datad (639:639:639) (680:680:680)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~9) + (DELAY + (ABSOLUTE + (PORT dataa (869:869:869) (883:883:883)) + (PORT datab (227:227:227) (269:269:269)) + (PORT datac (1087:1087:1087) (1134:1134:1134)) + (PORT datad (943:943:943) (963:963:963)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~12) + (DELAY + (ABSOLUTE + (PORT dataa (209:209:209) (255:255:255)) + (PORT datab (206:206:206) (248:248:248)) + (PORT datac (654:654:654) (676:676:676)) + (PORT datad (622:622:622) (650:650:650)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1177:1177:1177) (1211:1211:1211)) + (PORT datab (934:934:934) (953:953:953)) + (PORT datac (847:847:847) (878:878:878)) + (PORT datad (1296:1296:1296) (1363:1363:1363)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1301:1301:1301) (1408:1408:1408)) + (PORT datab (1510:1510:1510) (1602:1602:1602)) + (PORT datac (886:886:886) (946:946:946)) + (PORT datad (2838:2838:2838) (2937:2937:2937)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~13) + (DELAY + (ABSOLUTE + (PORT dataa (2022:2022:2022) (2107:2107:2107)) + (PORT datab (2444:2444:2444) (2572:2572:2572)) + (PORT datac (660:660:660) (715:715:715)) + (PORT datad (983:983:983) (1064:1064:1064)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~14) + (DELAY + (ABSOLUTE + (PORT dataa (661:661:661) (683:683:683)) + (PORT datab (652:652:652) (679:679:679)) + (PORT datac (187:187:187) (227:227:227)) + (PORT datad (347:347:347) (370:370:370)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_use_ixiypla53M2T2_4) + (DELAY + (ABSOLUTE + (PORT dataa (2023:2023:2023) (2107:2107:2107)) + (PORT datab (1189:1189:1189) (1228:1228:1228)) + (PORT datac (851:851:851) (873:873:873)) + (PORT datad (984:984:984) (1063:1063:1063)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~16) + (DELAY + (ABSOLUTE + (PORT dataa (568:568:568) (592:592:592)) + (PORT datab (392:392:392) (422:422:422)) + (PORT datac (179:179:179) (215:215:215)) + (PORT datad (337:337:337) (357:357:357)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~22) + (DELAY + (ABSOLUTE + (PORT dataa (655:655:655) (682:682:682)) + (PORT datab (1346:1346:1346) (1448:1448:1448)) + (PORT datac (1534:1534:1534) (1623:1623:1623)) + (PORT datad (1652:1652:1652) (1728:1728:1728)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~23) + (DELAY + (ABSOLUTE + (PORT dataa (401:401:401) (429:429:429)) + (PORT datab (1152:1152:1152) (1216:1216:1216)) + (PORT datac (1367:1367:1367) (1418:1418:1418)) + (PORT datad (2160:2160:2160) (2356:2356:2356)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~24) + (DELAY + (ABSOLUTE + (PORT dataa (1522:1522:1522) (1603:1603:1603)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (169:169:169) (202:202:202)) + (PORT datad (2160:2160:2160) (2356:2356:2356)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~41) + (DELAY + (ABSOLUTE + (PORT dataa (976:976:976) (1029:1029:1029)) + (PORT datab (955:955:955) (1004:1004:1004)) + (PORT datac (1229:1229:1229) (1299:1299:1299)) + (PORT datad (658:658:658) (706:706:706)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~21) + (DELAY + (ABSOLUTE + (PORT dataa (842:842:842) (869:869:869)) + (PORT datab (1383:1383:1383) (1429:1429:1429)) + (PORT datac (1609:1609:1609) (1641:1641:1641)) + (PORT datad (830:830:830) (858:858:858)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~25) + (DELAY + (ABSOLUTE + (PORT dataa (670:670:670) (695:695:695)) + (PORT datab (908:908:908) (921:921:921)) + (PORT datac (876:876:876) (893:893:893)) + (PORT datad (180:180:180) (208:208:208)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~69) + (DELAY + (ABSOLUTE + (PORT dataa (1000:1000:1000) (1053:1053:1053)) + (PORT datab (2808:2808:2808) (3013:3013:3013)) + (PORT datac (179:179:179) (216:216:216)) + (PORT datad (1382:1382:1382) (1437:1437:1437)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~17) + (DELAY + (ABSOLUTE + (PORT dataa (504:504:504) (583:583:583)) + (PORT datac (265:265:265) (354:354:354)) + (PORT datad (700:700:700) (785:785:785)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~71) + (DELAY + (ABSOLUTE + (PORT dataa (1655:1655:1655) (1694:1694:1694)) + (PORT datab (198:198:198) (238:238:238)) + (PORT datac (178:178:178) (213:213:213)) + (PORT datad (1175:1175:1175) (1237:1237:1237)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~44) + (DELAY + (ABSOLUTE + (PORT dataa (220:220:220) (262:262:262)) + (PORT datab (1337:1337:1337) (1422:1422:1422)) + (PORT datac (636:636:636) (654:654:654)) + (PORT datad (1177:1177:1177) (1244:1244:1244)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~42) + (DELAY + (ABSOLUTE + (PORT dataa (670:670:670) (699:699:699)) + (PORT datac (876:876:876) (893:893:893)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~43) + (DELAY + (ABSOLUTE + (PORT dataa (1218:1218:1218) (1286:1286:1286)) + (PORT datab (199:199:199) (239:239:239)) + (PORT datac (1061:1061:1061) (1086:1086:1086)) + (PORT datad (974:974:974) (1012:1012:1012)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~57) + (DELAY + (ABSOLUTE + (PORT dataa (1383:1383:1383) (1420:1420:1420)) + (PORT datab (1160:1160:1160) (1211:1211:1211)) + (PORT datac (620:620:620) (647:647:647)) + (PORT datad (620:620:620) (637:637:637)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~54) + (DELAY + (ABSOLUTE + (PORT dataa (1708:1708:1708) (1796:1796:1796)) + (PORT datab (2444:2444:2444) (2575:2575:2575)) + (PORT datac (1803:1803:1803) (1899:1899:1899)) + (PORT datad (680:680:680) (733:733:733)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~58) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (392:392:392) (420:420:420)) + (PORT datac (179:179:179) (216:216:216)) + (PORT datad (322:322:322) (343:343:343)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~18) + (DELAY + (ABSOLUTE + (PORT dataa (981:981:981) (1054:1054:1054)) + (PORT datab (228:228:228) (269:269:269)) + (PORT datac (179:179:179) (217:217:217)) + (PORT datad (622:622:622) (647:647:647)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~19) + (DELAY + (ABSOLUTE + (PORT dataa (870:870:870) (881:881:881)) + (PORT datab (379:379:379) (406:406:406)) + (PORT datac (623:623:623) (650:650:650)) + (PORT datad (588:588:588) (611:611:611)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~45) + (DELAY + (ABSOLUTE + (PORT dataa (1218:1218:1218) (1267:1267:1267)) + (PORT datab (1012:1012:1012) (1054:1054:1054)) + (PORT datac (572:572:572) (575:575:575)) + (PORT datad (1453:1453:1453) (1517:1517:1517)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~34) + (DELAY + (ABSOLUTE + (PORT dataa (2809:2809:2809) (3013:3013:3013)) + (PORT datab (1267:1267:1267) (1332:1332:1332)) + (PORT datac (977:977:977) (1038:1038:1038)) + (PORT datad (1269:1269:1269) (1304:1304:1304)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~35) + (DELAY + (ABSOLUTE + (PORT dataa (1296:1296:1296) (1347:1347:1347)) + (PORT datab (206:206:206) (247:247:247)) + (PORT datac (682:682:682) (723:723:723)) + (PORT datad (171:171:171) (196:196:196)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~46) + (DELAY + (ABSOLUTE + (PORT dataa (1286:1286:1286) (1347:1347:1347)) + (PORT datab (1241:1241:1241) (1309:1309:1309)) + (PORT datac (1253:1253:1253) (1318:1318:1318)) + (PORT datad (1457:1457:1457) (1522:1522:1522)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~47) + (DELAY + (ABSOLUTE + (PORT dataa (622:622:622) (686:686:686)) + (PORT datab (1241:1241:1241) (1308:1308:1308)) + (PORT datac (1517:1517:1517) (1594:1594:1594)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~48) + (DELAY + (ABSOLUTE + (PORT dataa (947:947:947) (998:998:998)) + (PORT datab (2479:2479:2479) (2662:2662:2662)) + (PORT datac (606:606:606) (642:642:642)) + (PORT datad (919:919:919) (994:994:994)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~50) + (DELAY + (ABSOLUTE + (PORT dataa (659:659:659) (678:678:678)) + (PORT datab (213:213:213) (256:256:256)) + (PORT datac (911:911:911) (964:964:964)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~51) + (DELAY + (ABSOLUTE + (PORT dataa (215:215:215) (267:267:267)) + (PORT datab (1161:1161:1161) (1213:1213:1213)) + (PORT datac (188:188:188) (228:228:228)) + (PORT datad (924:924:924) (975:975:975)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~85) + (DELAY + (ABSOLUTE + (PORT dataa (1302:1302:1302) (1408:1408:1408)) + (PORT datab (1249:1249:1249) (1314:1314:1314)) + (PORT datac (945:945:945) (1046:1046:1046)) + (PORT datad (642:642:642) (700:700:700)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~63) + (DELAY + (ABSOLUTE + (PORT dataa (510:510:510) (589:589:589)) + (PORT datab (937:937:937) (989:989:989)) + (PORT datac (848:848:848) (887:887:887)) + (PORT datad (695:695:695) (784:784:784)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~64) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (265:265:265)) + (PORT datab (875:875:875) (912:912:912)) + (PORT datac (854:854:854) (907:907:907)) + (PORT datad (622:622:622) (646:646:646)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~65) + (DELAY + (ABSOLUTE + (PORT dataa (228:228:228) (273:273:273)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (571:571:571) (580:580:580)) + (PORT datad (195:195:195) (221:221:221)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~59) + (DELAY + (ABSOLUTE + (PORT dataa (943:943:943) (964:964:964)) + (PORT datab (1662:1662:1662) (1751:1751:1751)) + (PORT datac (856:856:856) (906:906:906)) + (PORT datad (886:886:886) (935:935:935)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~60) + (DELAY + (ABSOLUTE + (PORT dataa (198:198:198) (241:241:241)) + (PORT datab (661:661:661) (686:686:686)) + (PORT datac (177:177:177) (213:213:213)) + (PORT datad (835:835:835) (883:883:883)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~61) + (DELAY + (ABSOLUTE + (PORT dataa (1302:1302:1302) (1407:1407:1407)) + (PORT datab (1250:1250:1250) (1315:1315:1315)) + (PORT datac (946:946:946) (1048:1048:1048)) + (PORT datad (1134:1134:1134) (1164:1164:1164)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~62) + (DELAY + (ABSOLUTE + (PORT dataa (661:661:661) (684:684:684)) + (PORT datab (645:645:645) (669:669:669)) + (PORT datac (608:608:608) (628:628:628)) + (PORT datad (172:172:172) (198:198:198)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~66) + (DELAY + (ABSOLUTE + (PORT dataa (198:198:198) (240:240:240)) + (PORT datab (341:341:341) (371:371:371)) + (PORT datac (185:185:185) (229:229:229)) + (PORT datad (172:172:172) (196:196:196)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~53) + (DELAY + (ABSOLUTE + (PORT dataa (1321:1321:1321) (1411:1411:1411)) + (PORT datab (206:206:206) (248:248:248)) + (PORT datac (1179:1179:1179) (1210:1210:1210)) + (PORT datad (1349:1349:1349) (1366:1366:1366)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~52) + (DELAY + (ABSOLUTE + (PORT dataa (1260:1260:1260) (1311:1311:1311)) + (PORT datab (1397:1397:1397) (1421:1421:1421)) + (PORT datac (1108:1108:1108) (1135:1135:1135)) + (PORT datad (872:872:872) (913:913:913)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~84) + (DELAY + (ABSOLUTE + (PORT dataa (1794:1794:1794) (1865:1865:1865)) + (PORT datab (196:196:196) (235:235:235)) + (PORT datac (200:200:200) (238:238:238)) + (PORT datad (1232:1232:1232) (1283:1283:1283)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla91pla20M2T2_3) + (DELAY + (ABSOLUTE + (PORT dataa (1304:1304:1304) (1411:1411:1411)) + (PORT datab (1506:1506:1506) (1599:1599:1599)) + (PORT datac (913:913:913) (932:932:932)) + (PORT datad (1600:1600:1600) (1628:1628:1628)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~55) + (DELAY + (ABSOLUTE + (PORT dataa (910:910:910) (945:945:945)) + (PORT datab (218:218:218) (257:257:257)) + (PORT datac (788:788:788) (808:808:808)) + (PORT datad (322:322:322) (344:344:344)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~56) + (DELAY + (ABSOLUTE + (PORT dataa (611:611:611) (633:633:633)) + (PORT datab (647:647:647) (671:671:671)) + (PORT datac (1133:1133:1133) (1178:1178:1178)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~67) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (241:241:241)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (172:172:172) (204:204:204)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|pc_inc_hold\~20) + (DELAY + (ABSOLUTE + (PORT dataa (216:216:216) (267:267:267)) + (PORT datab (392:392:392) (424:424:424)) + (PORT datac (188:188:188) (229:229:229)) + (PORT datad (527:527:527) (547:547:547)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~83) + (DELAY + (ABSOLUTE + (PORT dataa (1271:1271:1271) (1341:1341:1341)) + (PORT datab (1531:1531:1531) (1623:1623:1623)) + (PORT datac (609:609:609) (627:627:627)) + (PORT datad (1261:1261:1261) (1368:1368:1368)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~68) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (197:197:197) (237:237:237)) + (PORT datac (608:608:608) (627:627:627)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|Q\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (197:197:197) (223:223:223)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1526:1526:1526) (1546:1546:1546)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1573:1573:1573) (1552:1552:1552)) + (PORT ena (1991:1991:1991) (1983:1983:1983)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~72) + (DELAY + (ABSOLUTE + (PORT dataa (667:667:667) (698:698:698)) + (PORT datab (640:640:640) (664:664:664)) + (PORT datac (877:877:877) (896:896:896)) + (PORT datad (181:181:181) (210:210:210)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~73) + (DELAY + (ABSOLUTE + (PORT dataa (1572:1572:1572) (1699:1699:1699)) + (PORT datab (957:957:957) (1009:1009:1009)) + (PORT datac (208:208:208) (247:247:247)) + (PORT datad (1802:1802:1802) (1903:1903:1903)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~74) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (253:253:253)) + (PORT datab (1207:1207:1207) (1284:1284:1284)) + (PORT datac (1334:1334:1334) (1437:1437:1437)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~75) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (242:242:242)) + (PORT datab (207:207:207) (247:247:247)) + (PORT datac (615:615:615) (669:669:669)) + (PORT datad (1180:1180:1180) (1239:1239:1239)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~76) + (DELAY + (ABSOLUTE + (PORT dataa (215:215:215) (267:267:267)) + (PORT datab (205:205:205) (245:245:245)) + (PORT datac (526:526:526) (541:541:541)) + (PORT datad (358:358:358) (378:378:378)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~80) + (DELAY + (ABSOLUTE + (PORT datab (198:198:198) (238:238:238)) + (PORT datac (1152:1152:1152) (1187:1187:1187)) + (PORT datad (182:182:182) (212:212:212)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~81) + (DELAY + (ABSOLUTE + (PORT dataa (1218:1218:1218) (1287:1287:1287)) + (PORT datab (206:206:206) (248:248:248)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (609:609:609) (651:651:651)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|d0_out) + (DELAY + (ABSOLUTE + (PORT dataa (1501:1501:1501) (1627:1627:1627)) + (PORT datab (1554:1554:1554) (1576:1576:1576)) + (PORT datac (249:249:249) (334:334:334)) + (PORT datad (1466:1466:1466) (1550:1550:1550)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1647:1647:1647) (1677:1677:1677)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (804:804:804) (814:814:814)) + (PORT datad (351:351:351) (383:383:383)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1549:1549:1549)) + (PORT asdata (990:990:990) (1006:1006:1006)) + (PORT ena (1240:1240:1240) (1231:1231:1231)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1470:1470:1470) (1475:1475:1475)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1549:1549:1549)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1207:1207:1207) (1180:1180:1180)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (702:702:702) (744:744:744)) + (PORT datab (710:710:710) (732:732:732)) + (PORT datad (217:217:217) (285:285:285)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT asdata (1255:1255:1255) (1279:1279:1279)) + (PORT ena (1200:1200:1200) (1188:1188:1188)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (865:865:865) (934:934:934)) + (PORT datab (1146:1146:1146) (1157:1157:1157)) + (PORT datad (557:557:557) (569:569:569)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1169:1169:1169) (1184:1184:1184)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1550:1550:1550)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (811:811:811) (804:804:804)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1550:1550:1550)) + (PORT asdata (1786:1786:1786) (1780:1780:1780)) + (PORT ena (842:842:842) (856:856:856)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (387:387:387) (466:466:466)) + (PORT datab (237:237:237) (282:282:282)) + (PORT datad (208:208:208) (237:237:237)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT asdata (941:941:941) (960:960:960)) + (PORT ena (811:811:811) (804:804:804)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|db\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (927:927:927) (974:974:974)) + (PORT datab (643:643:643) (698:698:698)) + (PORT datad (643:643:643) (686:686:686)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT asdata (941:941:941) (957:957:957)) + (PORT ena (981:981:981) (980:980:980)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (603:603:603) (631:631:631)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datad (229:229:229) (266:266:266)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (645:645:645) (674:674:674)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1220:1220:1220) (1212:1212:1212)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1535:1535:1535)) + (PORT asdata (1552:1552:1552) (1574:1574:1574)) + (PORT ena (1243:1243:1243) (1246:1246:1246)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (622:622:622) (694:694:694)) + (PORT datab (690:690:690) (760:760:760)) + (PORT datad (619:619:619) (672:672:672)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1535:1535:1535)) + (PORT asdata (1552:1552:1552) (1574:1574:1574)) + (PORT ena (1274:1274:1274) (1265:1265:1265)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (195:195:195) (221:221:221)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1438:1438:1438) (1476:1476:1476)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT asdata (898:898:898) (922:922:922)) + (PORT ena (790:790:790) (782:782:782)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (386:386:386) (467:467:467)) + (PORT datab (631:631:631) (697:697:697)) + (PORT datad (231:231:231) (271:271:271)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (954:954:954) (995:995:995)) + (PORT datad (565:565:565) (578:578:578)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (650:650:650) (671:671:671)) + (PORT datab (636:636:636) (653:653:653)) + (PORT datac (869:869:869) (872:872:872)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[0\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (1133:1133:1133) (1172:1172:1172)) + (PORT datab (663:663:663) (694:694:694)) + (PORT datac (616:616:616) (644:644:644)) + (PORT datad (624:624:624) (637:637:637)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[0\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (348:348:348) (376:376:376)) + (PORT datab (202:202:202) (241:241:241)) + (PORT datac (899:899:899) (921:921:921)) + (PORT datad (201:201:201) (229:229:229)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[0\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (869:869:869) (904:904:904)) + (PORT datab (898:898:898) (903:903:903)) + (PORT datac (172:172:172) (206:206:206)) + (PORT datad (368:368:368) (394:394:394)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[8\]) + (DELAY + (ABSOLUTE + (PORT datac (856:856:856) (889:889:889)) + (PORT datad (941:941:941) (982:982:982)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1560:1560:1560) (1542:1542:1542)) + (PORT ena (1949:1949:1949) (1917:1917:1917)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|d0_out) + (DELAY + (ABSOLUTE + (PORT datac (638:638:638) (656:656:656)) + (PORT datad (584:584:584) (644:644:644)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1535:1535:1535)) + (PORT asdata (924:924:924) (951:951:951)) + (PORT ena (975:975:975) (963:963:963)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1535:1535:1535)) + (PORT asdata (925:925:925) (952:952:952)) + (PORT ena (1008:1008:1008) (1010:1010:1010)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~84) + (DELAY + (ABSOLUTE + (PORT dataa (374:374:374) (417:417:417)) + (PORT datab (242:242:242) (325:325:325)) + (PORT datad (368:368:368) (394:394:394)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1140:1140:1140) (1149:1149:1149)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1550:1550:1550)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (811:811:811) (804:804:804)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1550:1550:1550)) + (PORT asdata (1217:1217:1217) (1236:1236:1236)) + (PORT ena (842:842:842) (856:856:856)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~83) + (DELAY + (ABSOLUTE + (PORT dataa (388:388:388) (458:458:458)) + (PORT datab (235:235:235) (279:279:279)) + (PORT datad (209:209:209) (240:240:240)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT asdata (537:537:537) (568:568:568)) + (PORT ena (1438:1438:1438) (1476:1476:1476)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~88) + (DELAY + (ABSOLUTE + (PORT dataa (697:697:697) (764:764:764)) + (PORT datab (867:867:867) (894:894:894)) + (PORT datad (1351:1351:1351) (1343:1343:1343)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT asdata (1191:1191:1191) (1218:1218:1218)) + (PORT ena (1220:1220:1220) (1212:1212:1212)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT asdata (1191:1191:1191) (1218:1218:1218)) + (PORT ena (1200:1200:1200) (1188:1188:1188)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~86) + (DELAY + (ABSOLUTE + (PORT dataa (858:858:858) (928:928:928)) + (PORT datab (241:241:241) (322:322:322)) + (PORT datad (662:662:662) (722:722:722)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT asdata (947:947:947) (965:965:965)) + (PORT ena (790:790:790) (782:782:782)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT asdata (947:947:947) (966:966:966)) + (PORT ena (1288:1288:1288) (1306:1306:1306)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~87) + (DELAY + (ABSOLUTE + (PORT dataa (667:667:667) (749:749:749)) + (PORT datab (240:240:240) (322:322:322)) + (PORT datad (231:231:231) (272:272:272)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT asdata (970:970:970) (1006:1006:1006)) + (PORT ena (841:841:841) (847:847:847)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|db\[7\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1175:1175:1175) (1215:1215:1215)) + (PORT datab (888:888:888) (933:933:933)) + (PORT datad (943:943:943) (978:978:978)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~89) + (DELAY + (ABSOLUTE + (PORT dataa (640:640:640) (675:675:675)) + (PORT datab (896:896:896) (922:922:922)) + (PORT datac (575:575:575) (602:602:602)) + (PORT datad (172:172:172) (198:198:198)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1549:1549:1549)) + (PORT asdata (1242:1242:1242) (1258:1258:1258)) + (PORT ena (1240:1240:1240) (1231:1231:1231)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1549:1549:1549)) + (PORT asdata (1239:1239:1239) (1254:1254:1254)) + (PORT ena (1207:1207:1207) (1180:1180:1180)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~85) + (DELAY + (ABSOLUTE + (PORT dataa (695:695:695) (736:736:736)) + (PORT datab (706:706:706) (728:728:728)) + (PORT datad (218:218:218) (287:287:287)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~90) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (661:661:661) (676:676:676)) + (PORT datac (765:765:765) (775:775:775)) + (PORT datad (783:783:783) (784:784:784)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[7\]\~91) + (DELAY + (ABSOLUTE + (PORT dataa (586:586:586) (603:603:603)) + (PORT datab (663:663:663) (696:696:696)) + (PORT datac (1100:1100:1100) (1134:1134:1134)) + (PORT datad (609:609:609) (628:628:628)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1531:1531:1531)) + (PORT asdata (692:692:692) (718:718:718)) + (PORT ena (811:811:811) (804:804:804)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (655:655:655) (704:704:704)) + (PORT datab (219:219:219) (259:259:259)) + (PORT datad (1066:1066:1066) (1071:1071:1071)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (985:985:985) (993:993:993)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (338:338:338) (368:368:368)) + (PORT datac (335:335:335) (361:361:361)) + (PORT datad (217:217:217) (286:286:286)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[7\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (820:820:820) (838:838:838)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (549:549:549) (570:570:570)) + (PORT datad (1831:1831:1831) (1825:1825:1825)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[7\]) + (DELAY + (ABSOLUTE + (PORT dataa (614:614:614) (638:638:638)) + (PORT datac (858:858:858) (881:881:881)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|Q\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (195:195:195) (220:220:220)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1562:1562:1562) (1544:1544:1544)) + (PORT ena (1676:1676:1676) (1678:1678:1678)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|d1_out) + (DELAY + (ABSOLUTE + (PORT dataa (910:910:910) (931:931:931)) + (PORT datab (965:965:965) (1050:1050:1050)) + (PORT datac (655:655:655) (698:698:698)) + (PORT datad (584:584:584) (648:648:648)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1279:1279:1279) (1290:1290:1290)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1532:1532:1532)) + (PORT asdata (1459:1459:1459) (1478:1478:1478)) + (PORT ena (1224:1224:1224) (1225:1225:1225)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (684:684:684) (708:708:708)) + (PORT datab (665:665:665) (687:687:687)) + (PORT datad (600:600:600) (617:617:617)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT datab (1080:1080:1080) (1107:1107:1107)) + (PORT datac (217:217:217) (294:294:294)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (664:664:664) (679:679:679)) + (PORT datab (199:199:199) (239:239:239)) + (PORT datac (582:582:582) (610:610:610)) + (PORT datad (1332:1332:1332) (1347:1347:1347)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1530:1530:1530)) + (PORT asdata (1174:1174:1174) (1179:1179:1179)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1530:1530:1530)) + (PORT asdata (1174:1174:1174) (1181:1181:1181)) + (PORT ena (1240:1240:1240) (1223:1223:1223)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (726:726:726) (751:751:751)) + (PORT datab (260:260:260) (312:312:312)) + (PORT datad (217:217:217) (286:286:286)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT asdata (1871:1871:1871) (1898:1898:1898)) + (PORT ena (1168:1168:1168) (1147:1147:1147)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1533:1533:1533)) + (PORT asdata (1876:1876:1876) (1902:1902:1902)) + (PORT ena (1230:1230:1230) (1209:1209:1209)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (694:694:694) (728:728:728)) + (PORT datab (270:270:270) (330:330:330)) + (PORT datad (386:386:386) (445:445:445)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1533:1533:1533)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1227:1227:1227) (1249:1249:1249)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1533:1533:1533)) + (PORT asdata (890:890:890) (899:899:899)) + (PORT ena (1503:1503:1503) (1497:1497:1497)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (705:705:705) (782:782:782)) + (PORT datab (588:588:588) (663:663:663)) + (PORT datad (695:695:695) (748:748:748)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (1676:1676:1676) (1719:1719:1719)) + (PORT ena (1440:1440:1440) (1419:1419:1419)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (1676:1676:1676) (1719:1719:1719)) + (PORT ena (1225:1225:1225) (1236:1236:1236)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (702:702:702) (763:763:763)) + (PORT datab (657:657:657) (676:676:676)) + (PORT datad (215:215:215) (283:283:283)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1533:1533:1533)) + (PORT asdata (1878:1878:1878) (1906:1906:1906)) + (PORT ena (1201:1201:1201) (1198:1198:1198)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (1202:1202:1202) (1220:1220:1220)) + (PORT datab (905:905:905) (941:941:941)) + (PORT datad (400:400:400) (443:443:443)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (604:604:604) (631:631:631)) + (PORT datab (380:380:380) (406:406:406)) + (PORT datac (872:872:872) (889:889:889)) + (PORT datad (617:617:617) (626:626:626)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (1841:1841:1841) (1879:1879:1879)) + (PORT ena (790:790:790) (782:782:782)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[0\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1530:1530:1530) (1588:1588:1588)) + (PORT datab (2174:2174:2174) (2219:2219:2219)) + (PORT datad (1365:1365:1365) (1389:1389:1389)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (1822:1822:1822) (1851:1851:1851)) + (PORT ena (981:981:981) (980:980:980)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1248:1248:1248) (1278:1278:1278)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1190:1190:1190) (1164:1164:1164)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (693:693:693) (730:730:730)) + (PORT datab (696:696:696) (723:723:723)) + (PORT datad (217:217:217) (286:286:286)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (898:898:898) (935:935:935)) + (PORT datab (200:200:200) (239:239:239)) + (PORT datac (621:621:621) (634:634:634)) + (PORT datad (596:596:596) (619:619:619)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[0\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (636:636:636) (671:671:671)) + (PORT datab (367:367:367) (389:389:389)) + (PORT datac (1143:1143:1143) (1172:1172:1172)) + (PORT datad (882:882:882) (921:921:921)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[0\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (649:649:649) (677:677:677)) + (PORT datab (680:680:680) (699:699:699)) + (PORT datac (843:843:843) (848:848:848)) + (PORT datad (706:706:706) (734:734:734)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[0\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (858:858:858) (890:890:890)) + (PORT datab (258:258:258) (317:317:317)) + (PORT datac (590:590:590) (603:603:603)) + (PORT datad (176:176:176) (201:201:201)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (903:903:903) (932:932:932)) + (PORT datab (849:849:849) (885:885:885)) + (PORT datad (1178:1178:1178) (1265:1265:1265)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (851:851:851) (882:882:882)) + (PORT datab (1295:1295:1295) (1332:1332:1332)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (245:245:245) (299:299:299)) + (PORT datab (575:575:575) (641:641:641)) + (PORT datac (603:603:603) (610:610:610)) + (PORT datad (891:891:891) (928:928:928)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (283:283:283) (354:354:354)) + (PORT datab (279:279:279) (337:337:337)) + (PORT datac (1112:1112:1112) (1118:1118:1118)) + (PORT datad (241:241:241) (285:285:285)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|result_lo\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (195:195:195) (222:222:222)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|result_lo\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1716:1716:1716) (1724:1724:1724)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (794:794:794) (816:816:816)) + (PORT datac (540:540:540) (554:554:554)) + (PORT datad (383:383:383) (442:442:442)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[1\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (374:374:374) (398:398:398)) + (PORT datab (700:700:700) (735:735:735)) + (PORT datac (692:692:692) (742:742:742)) + (PORT datad (591:591:591) (606:606:606)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[1\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (652:652:652) (676:676:676)) + (PORT datab (624:624:624) (641:641:641)) + (PORT datac (640:640:640) (667:667:667)) + (PORT datad (1143:1143:1143) (1178:1178:1178)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (745:745:745) (781:781:781)) + (PORT datab (257:257:257) (316:316:316)) + (PORT datac (878:878:878) (881:881:881)) + (PORT datad (177:177:177) (203:203:203)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1533:1533:1533)) + (PORT asdata (1431:1431:1431) (1460:1460:1460)) + (PORT ena (1201:1201:1201) (1198:1198:1198)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1200:1200:1200) (1221:1221:1221)) + (PORT datab (1449:1449:1449) (1507:1507:1507)) + (PORT datad (396:396:396) (441:441:441)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (887:887:887) (910:910:910)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1168:1168:1168) (1147:1147:1147)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1533:1533:1533)) + (PORT asdata (1434:1434:1434) (1461:1461:1461)) + (PORT ena (1230:1230:1230) (1209:1209:1209)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (607:607:607) (637:637:637)) + (PORT datab (374:374:374) (443:443:443)) + (PORT datad (344:344:344) (358:358:358)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (1462:1462:1462) (1488:1488:1488)) + (PORT ena (1225:1225:1225) (1236:1236:1236)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (1463:1463:1463) (1487:1487:1487)) + (PORT ena (1440:1440:1440) (1419:1419:1419)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (699:699:699) (766:766:766)) + (PORT datab (656:656:656) (686:686:686)) + (PORT datad (217:217:217) (286:286:286)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1533:1533:1533)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1503:1503:1503) (1497:1497:1497)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1533:1533:1533)) + (PORT asdata (707:707:707) (735:735:735)) + (PORT ena (1227:1227:1227) (1249:1249:1249)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (709:709:709) (784:784:784)) + (PORT datab (240:240:240) (322:322:322)) + (PORT datad (695:695:695) (743:743:743)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (200:200:200) (240:240:240)) + (PORT datac (627:627:627) (653:653:653)) + (PORT datad (556:556:556) (561:561:561)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (902:902:902) (919:919:919)) + (PORT ena (790:790:790) (782:782:782)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1534:1534:1534) (1587:1587:1587)) + (PORT datab (2170:2170:2170) (2215:2215:2215)) + (PORT datad (1366:1366:1366) (1387:1387:1387)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1530:1530:1530)) + (PORT asdata (1477:1477:1477) (1520:1520:1520)) + (PORT ena (1240:1240:1240) (1223:1223:1223)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1530:1530:1530)) + (PORT asdata (1474:1474:1474) (1517:1517:1517)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (728:728:728) (759:759:759)) + (PORT datab (243:243:243) (325:325:325)) + (PORT datad (229:229:229) (268:268:268)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (1490:1490:1490) (1530:1530:1530)) + (PORT ena (981:981:981) (980:980:980)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (610:610:610) (627:627:627)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1190:1190:1190) (1164:1164:1164)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (692:692:692) (725:725:725)) + (PORT datab (697:697:697) (718:718:718)) + (PORT datad (217:217:217) (285:285:285)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (631:631:631) (650:650:650)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (604:604:604) (625:625:625)) + (PORT datad (318:318:318) (338:338:338)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[1\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (1187:1187:1187) (1214:1214:1214)) + (PORT datab (375:375:375) (399:399:399)) + (PORT datac (833:833:833) (850:850:850)) + (PORT datad (885:885:885) (921:921:921)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1533:1533:1533)) + (PORT asdata (849:849:849) (864:864:864)) + (PORT ena (1448:1448:1448) (1437:1437:1437)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (702:702:702) (730:730:730)) + (PORT datab (711:711:711) (739:739:739)) + (PORT datad (647:647:647) (666:666:666)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (244:244:244) (331:331:331)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datad (650:650:650) (672:672:672)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[1\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1116:1116:1116) (1170:1170:1170)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (1368:1368:1368) (1378:1378:1378)) + (PORT datad (219:219:219) (258:258:258)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[9\]) + (DELAY + (ABSOLUTE + (PORT datac (894:894:894) (933:933:933)) + (PORT datad (939:939:939) (978:978:978)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|Q\[9\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (179:179:179) (207:207:207)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1560:1560:1560) (1542:1542:1542)) + (PORT ena (1949:1949:1949) (1917:1917:1917)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[10\]) + (DELAY + (ABSOLUTE + (PORT dataa (627:627:627) (667:667:667)) + (PORT datad (595:595:595) (612:612:612)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1561:1561:1561) (1543:1543:1543)) + (PORT ena (1886:1886:1886) (1891:1891:1891)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|d1_out) + (DELAY + (ABSOLUTE + (PORT dataa (217:217:217) (268:268:268)) + (PORT datab (688:688:688) (731:731:731)) + (PORT datac (934:934:934) (1023:1023:1023)) + (PORT datad (416:416:416) (486:486:486)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1533:1533:1533)) + (PORT asdata (666:666:666) (699:699:699)) + (PORT ena (1448:1448:1448) (1437:1437:1437)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (895:895:895) (920:920:920)) + (PORT datab (711:711:711) (744:744:744)) + (PORT datad (649:649:649) (671:671:671)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1533:1533:1533)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1256:1256:1256) (1263:1263:1263)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (241:241:241)) + (PORT datab (688:688:688) (709:709:709)) + (PORT datad (218:218:218) (285:285:285)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[2\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (636:636:636) (672:672:672)) + (PORT datab (1397:1397:1397) (1412:1412:1412)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (219:219:219) (258:258:258)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[2\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (1181:1181:1181) (1211:1211:1211)) + (PORT datab (569:569:569) (592:592:592)) + (PORT datac (620:620:620) (643:643:643)) + (PORT datad (883:883:883) (918:918:918)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[2\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (621:621:621) (633:633:633)) + (PORT datab (624:624:624) (650:650:650)) + (PORT datac (530:530:530) (543:543:543)) + (PORT datad (608:608:608) (624:624:624)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[2\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (742:742:742) (772:772:772)) + (PORT datab (576:576:576) (599:599:599)) + (PORT datac (219:219:219) (271:271:271)) + (PORT datad (640:640:640) (654:654:654)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[2\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (653:653:653) (681:681:681)) + (PORT datab (867:867:867) (913:913:913)) + (PORT datac (364:364:364) (393:393:393)) + (PORT datad (854:854:854) (860:860:860)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (332:332:332)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -27799,10 +24590,10 @@ (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf\~2) (DELAY (ABSOLUTE - (PORT datac (852:852:852) (861:861:861)) - (PORT datad (679:679:679) (700:700:700)) + (PORT datab (236:236:236) (279:279:279)) + (PORT datac (785:785:785) (807:807:807)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -27811,11 +24602,11 @@ (INSTANCE z80_\|alu_flags_\|flags_hf2\~0) (DELAY (ABSOLUTE - (PORT dataa (690:690:690) (732:732:732)) - (PORT datab (199:199:199) (237:237:237)) - (PORT datad (621:621:621) (632:632:632)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) + (PORT dataa (411:411:411) (437:437:437)) + (PORT datab (200:200:200) (239:239:239)) + (PORT datad (648:648:648) (705:705:705)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -27826,7 +24617,7 @@ (INSTANCE z80_\|alu_flags_\|flags_hf2) (DELAY (ABSOLUTE - (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -27840,106 +24631,105 @@ (INSTANCE z80_\|alu_control_\|db\[2\]\~23) (DELAY (ABSOLUTE - (PORT dataa (1183:1183:1183) (1231:1231:1231)) - (PORT datab (681:681:681) (697:697:697)) - (PORT datac (1123:1123:1123) (1203:1203:1203)) - (PORT datad (667:667:667) (721:721:721)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|reg_file_\|db_lo_ds\[2\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1196:1196:1196) (1252:1252:1252)) - (PORT datab (1640:1640:1640) (1708:1708:1708)) - (PORT datac (1440:1440:1440) (1482:1482:1482)) - (PORT datad (844:844:844) (890:890:890)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) + (PORT dataa (1137:1137:1137) (1150:1150:1150)) + (PORT datab (714:714:714) (805:805:805)) + (PORT datac (852:852:852) (893:893:893)) + (PORT datad (189:189:189) (220:220:220)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[2\]\~28) - (DELAY - (ABSOLUTE - (PORT dataa (666:666:666) (686:686:686)) - (PORT datab (928:928:928) (956:956:956)) - (PORT datac (630:630:630) (688:688:688)) - (PORT datad (848:848:848) (847:847:847)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[2\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (837:837:837) (856:856:856)) - (PORT datab (904:904:904) (946:946:946)) - (PORT datac (412:412:412) (479:479:479)) - (PORT datad (832:832:832) (862:862:862)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|alu_control_\|db\[2\]\~29) (DELAY (ABSOLUTE - (PORT dataa (682:682:682) (712:712:712)) - (PORT datab (943:943:943) (996:996:996)) - (PORT datac (576:576:576) (598:598:598)) - (PORT datad (316:316:316) (337:337:337)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (339:339:339) (373:373:373)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (599:599:599) (609:609:609)) + (PORT datad (215:215:215) (247:247:247)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[2\]\~14) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~39) (DELAY (ABSOLUTE - (PORT dataa (1305:1305:1305) (1357:1357:1357)) - (PORT datab (967:967:967) (1024:1024:1024)) - (PORT datac (922:922:922) (952:952:952)) - (PORT datad (1557:1557:1557) (1610:1610:1610)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) + (PORT dataa (832:832:832) (860:860:860)) + (PORT datab (609:609:609) (659:659:659)) + (PORT datac (352:352:352) (379:379:379)) + (PORT datad (597:597:597) (646:646:646)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[2\]\~15) + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[2\]) (DELAY (ABSOLUTE - (PORT dataa (620:620:620) (642:642:642)) - (PORT datab (987:987:987) (1034:1034:1034)) - (PORT datac (175:175:175) (210:210:210)) - (PORT datad (221:221:221) (266:266:266)) + (PORT clk (1529:1529:1529) (1549:1549:1549)) + (PORT asdata (1245:1245:1245) (1255:1255:1255)) + (PORT ena (1240:1240:1240) (1231:1231:1231)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1549:1549:1549)) + (PORT asdata (1242:1242:1242) (1251:1251:1251)) + (PORT ena (1207:1207:1207) (1180:1180:1180)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (702:702:702) (744:744:744)) + (PORT datab (710:710:710) (732:732:732)) + (PORT datad (217:217:217) (286:286:286)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (385:385:385) (413:413:413)) + (PORT datab (338:338:338) (368:368:368)) + (PORT datac (173:173:173) (206:206:206)) + (PORT datad (637:637:637) (652:652:652)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -27949,60 +24739,181 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~2) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~41) (DELAY (ABSOLUTE - (PORT dataa (1693:1693:1693) (1778:1778:1778)) - (PORT datab (916:916:916) (942:942:942)) - (PORT datac (904:904:904) (929:929:929)) - (IOPATH dataa combout (339:339:339) (367:367:367)) + (PORT dataa (522:522:522) (545:545:545)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datad (622:622:622) (631:631:631)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[2\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (1132:1132:1132) (1176:1176:1176)) + (PORT datab (618:618:618) (633:633:633)) + (PORT datac (634:634:634) (662:662:662)) + (PORT datad (650:650:650) (677:677:677)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (537:537:537) (567:567:567)) + (PORT ena (1200:1200:1200) (1181:1181:1181)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (893:893:893) (941:941:941)) + (PORT datab (691:691:691) (715:715:715)) + (PORT datad (404:404:404) (441:441:441)) + (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (381:381:381) (459:459:459)) + (PORT datac (171:171:171) (202:202:202)) + (PORT datad (613:613:613) (632:632:632)) + (IOPATH dataa combout (304:304:304) (307:307:307)) (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~3) + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_41) (DELAY (ABSOLUTE - (PORT dataa (1446:1446:1446) (1487:1487:1487)) - (PORT datab (1129:1129:1129) (1183:1183:1183)) - (PORT datac (170:170:170) (203:203:203)) - (PORT datad (234:234:234) (275:275:275)) + (PORT dataa (1836:1836:1836) (1914:1914:1914)) + (PORT datab (397:397:397) (461:461:461)) + (PORT datac (1281:1281:1281) (1295:1295:1295)) + (PORT datad (197:197:197) (232:232:232)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|SYNTHESIZED_WIRE_0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1502:1502:1502) (1628:1628:1628)) + (PORT datab (1490:1490:1490) (1584:1584:1584)) + (PORT datac (1527:1527:1527) (1545:1545:1545)) + (PORT datad (341:341:341) (362:362:362)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|d0_out) + (DELAY + (ABSOLUTE + (PORT dataa (955:955:955) (1038:1038:1038)) + (PORT datac (373:373:373) (399:399:399)) + (PORT datad (188:188:188) (221:221:221)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[2\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (241:241:241)) + (PORT datab (381:381:381) (418:418:418)) + (PORT datac (1615:1615:1615) (1633:1633:1633)) + (PORT datad (597:597:597) (613:613:613)) (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[2\]\~2) + (INSTANCE z80_\|address_latch_\|abusz\[2\]) (DELAY (ABSOLUTE - (PORT dataa (221:221:221) (274:274:274)) - (PORT datab (246:246:246) (301:301:301)) - (PORT datac (617:617:617) (647:647:647)) - (PORT datad (845:845:845) (875:875:875)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT datac (928:928:928) (948:948:948)) + (PORT datad (620:620:620) (633:633:633)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[2\]\~3) + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[2\]) (DELAY (ABSOLUTE - (PORT dataa (549:549:549) (580:580:580)) - (PORT datab (714:714:714) (753:753:753)) - (PORT datac (601:601:601) (608:608:608)) - (PORT datad (865:865:865) (915:915:915)) - (IOPATH dataa combout (354:354:354) (349:349:349)) + (PORT clk (1526:1526:1526) (1546:1546:1546)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1573:1573:1573) (1552:1552:1552)) + (PORT ena (1991:1991:1991) (1983:1983:1983)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_42) + (DELAY + (ABSOLUTE + (PORT dataa (1767:1767:1767) (1880:1880:1880)) + (PORT datab (1425:1425:1425) (1484:1484:1484)) + (PORT datac (211:211:211) (261:261:261)) + (PORT datad (1854:1854:1854) (1987:1987:1987)) + (IOPATH dataa combout (300:300:300) (308:308:308)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -28011,12 +24922,43 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op1_low\[2\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[3\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1531:1531:1531)) + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (535:535:535) (566:566:566)) + (PORT ena (1200:1200:1200) (1181:1181:1181)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (893:893:893) (937:937:937)) + (PORT datab (1125:1125:1125) (1146:1146:1146)) + (PORT datad (407:407:407) (440:440:440)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (790:790:790) (782:782:782)) + (PORT ena (1231:1231:1231) (1237:1237:1237)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -28027,13 +24969,169 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[2\]\~0) + (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~11) (DELAY (ABSOLUTE - (PORT dataa (654:654:654) (718:718:718)) - (PORT datab (1128:1128:1128) (1175:1175:1175)) - (PORT datac (587:587:587) (617:617:617)) - (PORT datad (401:401:401) (459:459:459)) + (PORT dataa (644:644:644) (683:683:683)) + (PORT datab (196:196:196) (235:235:235)) + (PORT datad (360:360:360) (421:421:421)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|d1_out) + (DELAY + (ABSOLUTE + (PORT dataa (217:217:217) (268:268:268)) + (PORT datab (654:654:654) (726:726:726)) + (PORT datac (368:368:368) (392:392:392)) + (PORT datad (181:181:181) (208:208:208)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[3\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1649:1649:1649) (1672:1672:1672)) + (PORT datab (196:196:196) (235:235:235)) + (PORT datac (607:607:607) (628:628:628)) + (PORT datad (350:350:350) (377:377:377)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[3\]) + (DELAY + (ABSOLUTE + (PORT datab (961:961:961) (983:983:983)) + (PORT datac (560:560:560) (566:566:566)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_latch_\|Q\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1526:1526:1526) (1546:1546:1546)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1573:1573:1573) (1552:1552:1552)) + (PORT ena (1991:1991:1991) (1983:1983:1983)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_45\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1898:1898:1898) (2033:2033:2033)) + (PORT datab (655:655:655) (722:722:722)) + (PORT datac (208:208:208) (256:256:256)) + (PORT datad (1741:1741:1741) (1836:1836:1836)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_2\|carry_borrow_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (216:216:216) (267:267:267)) + (PORT datab (207:207:207) (248:248:248)) + (PORT datac (370:370:370) (397:397:397)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_47\~0) + (DELAY + (ABSOLUTE + (PORT dataa (972:972:972) (1024:1024:1024)) + (PORT datab (220:220:220) (269:269:269)) + (PORT datac (210:210:210) (259:259:259)) + (PORT datad (1322:1322:1322) (1328:1328:1328)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|SYNTHESIZED_WIRE_47) + (DELAY + (ABSOLUTE + (PORT dataa (229:229:229) (276:276:276)) + (PORT datab (207:207:207) (249:249:249)) + (PORT datac (179:179:179) (217:217:217)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_7\|carry_borrow_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (913:913:913) (932:932:932)) + (PORT datab (967:967:967) (1049:1049:1049)) + (PORT datac (659:659:659) (695:695:695)) + (PORT datad (584:584:584) (643:643:643)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_9\|carry_borrow_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (215:215:215) (264:264:264)) + (PORT datab (689:689:689) (734:734:734)) + (PORT datac (934:934:934) (1018:1018:1018)) + (PORT datad (414:414:414) (480:480:480)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -28043,31 +25141,106 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[2\]\~1) + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|address\[11\]) (DELAY (ABSOLUTE - (PORT dataa (261:261:261) (336:336:336)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (559:559:559) (578:578:578)) - (PORT datad (903:903:903) (954:954:954)) + (PORT datac (244:244:244) (324:324:324)) + (PORT datad (188:188:188) (219:219:219)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[3\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (242:242:242) (294:294:294)) + (PORT datab (1394:1394:1394) (1406:1406:1406)) + (PORT datac (171:171:171) (205:205:205)) + (PORT datad (614:614:614) (628:628:628)) (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_low\[2\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[3\]) (DELAY (ABSOLUTE - (PORT clk (1529:1529:1529) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) + (PORT clk (1517:1517:1517) (1530:1530:1530)) + (PORT asdata (1196:1196:1196) (1206:1206:1206)) + (PORT ena (1240:1240:1240) (1223:1223:1223)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1530:1530:1530)) + (PORT asdata (1194:1194:1194) (1204:1204:1204)) (PORT ena (819:819:819) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~41) + (DELAY + (ABSOLUTE + (PORT dataa (725:725:725) (752:752:752)) + (PORT datab (241:241:241) (323:323:323)) + (PORT datad (235:235:235) (274:274:274)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1533:1533:1533)) + (PORT asdata (692:692:692) (716:716:716)) + (PORT ena (1227:1227:1227) (1249:1249:1249)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1533:1533:1533)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1503:1503:1503) (1497:1497:1497)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) (TIMINGCHECK (HOLD d (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) @@ -28075,63 +25248,380 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~5) + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~45) (DELAY (ABSOLUTE - (PORT dataa (460:460:460) (538:538:538)) - (PORT datab (638:638:638) (705:705:705)) - (PORT datac (1102:1102:1102) (1133:1133:1133)) - (PORT datad (662:662:662) (719:719:719)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) + (PORT dataa (708:708:708) (782:782:782)) + (PORT datab (630:630:630) (667:667:667)) + (PORT datad (215:215:215) (283:283:283)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1533:1533:1533)) + (PORT asdata (995:995:995) (1025:1025:1025)) + (PORT ena (1201:1201:1201) (1198:1198:1198)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~44) + (DELAY + (ABSOLUTE + (PORT dataa (1201:1201:1201) (1222:1222:1222)) + (PORT datab (926:926:926) (942:942:942)) + (PORT datad (400:400:400) (437:437:437)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT asdata (995:995:995) (1024:1024:1024)) + (PORT ena (1229:1229:1229) (1240:1240:1240)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT asdata (994:994:994) (1022:1022:1022)) + (PORT ena (1168:1168:1168) (1147:1147:1147)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~43) + (DELAY + (ABSOLUTE + (PORT dataa (691:691:691) (729:729:729)) + (PORT datab (270:270:270) (330:330:330)) + (PORT datad (357:357:357) (414:414:414)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (1244:1244:1244) (1251:1251:1251)) + (PORT ena (1440:1440:1440) (1419:1419:1419)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (1243:1243:1243) (1251:1251:1251)) + (PORT ena (1225:1225:1225) (1236:1236:1236)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (701:701:701) (757:757:757)) + (PORT datab (241:241:241) (322:322:322)) + (PORT datad (621:621:621) (642:642:642)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (627:627:627) (657:657:657)) + (PORT datab (332:332:332) (362:362:362)) + (PORT datac (536:536:536) (536:536:536)) + (PORT datad (320:320:320) (342:342:342)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (609:609:609) (622:622:622)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1190:1190:1190) (1164:1164:1164)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (954:954:954) (960:960:960)) + (PORT ena (981:981:981) (980:980:980)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (699:699:699) (734:734:734)) + (PORT datab (243:243:243) (325:325:325)) + (PORT datad (620:620:620) (634:634:634)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (1162:1162:1162) (1178:1178:1178)) + (PORT ena (790:790:790) (782:782:782)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[3\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1823:1823:1823) (1903:1903:1903)) + (PORT datab (657:657:657) (696:696:696)) + (PORT datac (1871:1871:1871) (1941:1941:1941)) + (PORT datad (876:876:876) (916:916:916)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (649:649:649) (682:682:682)) + (PORT datab (198:198:198) (235:235:235)) + (PORT datac (638:638:638) (653:653:653)) + (PORT datad (174:174:174) (198:198:198)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[3\]\~48) + (DELAY + (ABSOLUTE + (PORT dataa (642:642:642) (673:673:673)) + (PORT datab (922:922:922) (955:955:955)) + (PORT datac (1143:1143:1143) (1168:1168:1168)) + (PORT datad (591:591:591) (602:602:602)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[3\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (645:645:645) (670:670:670)) + (PORT datab (627:627:627) (653:653:653)) + (PORT datac (621:621:621) (641:641:641)) + (PORT datad (699:699:699) (726:726:726)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[3\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (604:604:604) (628:628:628)) + (PORT datab (258:258:258) (316:316:316)) + (PORT datac (591:591:591) (608:608:608)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[2\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (1098:1098:1098) (1120:1120:1120)) + (PORT datab (1155:1155:1155) (1240:1240:1240)) + (PORT datad (621:621:621) (637:637:637)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[2\]\~22) + (DELAY + (ABSOLUTE + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (669:669:669) (702:702:702)) + (PORT datad (1093:1093:1093) (1130:1130:1130)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|alu_\|result_lo\[2\]) (DELAY (ABSOLUTE - (PORT clk (1518:1518:1518) (1535:1535:1535)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1283:1283:1283) (1287:1287:1287)) + (PORT clk (1541:1541:1541) (1557:1557:1557)) + (PORT asdata (678:678:678) (699:699:699)) + (PORT ena (2016:2016:2016) (1997:1997:1997)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_low\[2\]\~6) + (INSTANCE z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\~3) (DELAY (ABSOLUTE - (PORT dataa (339:339:339) (368:368:368)) - (PORT datab (597:597:597) (636:636:636)) - (PORT datac (965:965:965) (999:999:999)) - (PORT datad (590:590:590) (645:645:645)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT datab (273:273:273) (330:330:330)) + (PORT datac (248:248:248) (311:311:311)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[2\]\~3) + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[2\]\~6) (DELAY (ABSOLUTE - (PORT dataa (222:222:222) (276:276:276)) - (PORT datab (653:653:653) (675:675:675)) - (PORT datac (916:916:916) (949:949:949)) - (PORT datad (220:220:220) (264:264:264)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) + (PORT dataa (707:707:707) (780:780:780)) + (PORT datab (1133:1133:1133) (1158:1158:1158)) + (PORT datac (611:611:611) (627:627:627)) + (PORT datad (673:673:673) (728:728:728)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -28139,26 +25629,26 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[2\]\~4) + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[2\]\~7) (DELAY (ABSOLUTE - (PORT dataa (263:263:263) (337:337:337)) - (PORT datab (596:596:596) (614:614:614)) - (PORT datac (585:585:585) (589:589:589)) - (PORT datad (896:896:896) (944:944:944)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (954:954:954) (983:983:983)) + (PORT datab (899:899:899) (929:929:929)) + (PORT datac (171:171:171) (203:203:203)) + (PORT datad (651:651:651) (660:660:660)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_\|op2_high\[2\]) + (INSTANCE z80_\|alu_\|op2_low\[2\]) (DELAY (ABSOLUTE - (PORT clk (1529:1529:1529) (1531:1531:1531)) + (PORT clk (1535:1535:1535) (1540:1540:1540)) (PORT d (74:74:74) (91:91:91)) (PORT ena (819:819:819) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) @@ -28169,17 +25659,856 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[2\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (653:653:653) (683:683:683)) + (PORT datab (435:435:435) (506:506:506)) + (PORT datac (575:575:575) (624:624:624)) + (PORT datad (670:670:670) (685:685:685)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[2\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (275:275:275) (331:331:331)) + (PORT datac (1117:1117:1117) (1123:1123:1123)) + (PORT datad (322:322:322) (343:343:343)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[2\]\~20) + (DELAY + (ABSOLUTE + (PORT datab (1083:1083:1083) (1100:1100:1100)) + (PORT datad (309:309:309) (325:325:325)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[2\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (242:242:242)) + (PORT datab (703:703:703) (741:741:741)) + (PORT datac (696:696:696) (750:750:750)) + (PORT datad (593:593:593) (611:611:611)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[2\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (950:950:950) (984:984:984)) + (PORT datab (659:659:659) (688:688:688)) + (PORT datac (622:622:622) (649:649:649)) + (PORT datad (851:851:851) (867:867:867)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op1_latch_mux_low\|Q\[2\]\~8) + (DELAY + (ABSOLUTE + (PORT datac (889:889:889) (916:916:916)) + (PORT datad (172:172:172) (198:198:198)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op1_low\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1547:1547:1547) (1549:1549:1549)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (794:794:794) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op1\[2\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (651:651:651) (707:707:707)) + (PORT datab (1141:1141:1141) (1208:1208:1208)) + (PORT datac (645:645:645) (676:676:676)) + (PORT datad (608:608:608) (660:660:660)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_10\~1) + (DELAY + (ABSOLUTE + (PORT dataa (382:382:382) (410:410:410)) + (PORT datac (185:185:185) (226:226:226)) + (PORT datad (997:997:997) (1055:1055:1055)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_10\~0) + (DELAY + (ABSOLUTE + (PORT dataa (215:215:215) (265:265:265)) + (PORT datab (434:434:434) (504:504:504)) + (PORT datac (575:575:575) (636:636:636)) + (PORT datad (1404:1404:1404) (1413:1413:1413)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (398:398:398) (425:425:425)) + (PORT datab (1375:1375:1375) (1435:1435:1435)) + (PORT datac (180:180:180) (217:217:217)) + (PORT datad (189:189:189) (221:221:221)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|cy_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (255:255:255)) + (PORT datab (1049:1049:1049) (1119:1119:1119)) + (PORT datac (179:179:179) (216:216:216)) + (PORT datad (633:633:633) (651:651:651)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|SYNTHESIZED_WIRE_10\~0) + (DELAY + (ABSOLUTE + (PORT dataa (473:473:473) (551:551:551)) + (PORT datab (228:228:228) (270:270:270)) + (PORT datac (408:408:408) (484:484:484)) + (PORT datad (1402:1402:1402) (1415:1415:1415)) + (IOPATH dataa combout (301:301:301) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|cy_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (256:256:256)) + (PORT datab (228:228:228) (269:269:269)) + (PORT datac (1310:1310:1310) (1377:1377:1377)) + (PORT datad (182:182:182) (211:211:211)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf\~0) + (DELAY + (ABSOLUTE + (PORT dataa (815:815:815) (841:841:841)) + (PORT datab (873:873:873) (893:893:893)) + (PORT datac (207:207:207) (247:247:247)) + (PORT datad (645:645:645) (702:702:702)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (2369:2369:2369) (2430:2430:2430)) + (PORT datab (1735:1735:1735) (1787:1787:1787)) + (PORT datac (895:895:895) (929:929:929)) + (PORT datad (1370:1370:1370) (1410:1410:1410)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_hf_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (611:611:611) (622:622:622)) + (PORT datab (954:954:954) (1018:1018:1018)) + (PORT datac (192:192:192) (225:225:225)) + (PORT datad (603:603:603) (625:625:625)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf\~1) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (206:206:206) (247:247:247)) + (PORT datad (327:327:327) (344:344:344)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_hf) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|flags_hf) + (DELAY + (ABSOLUTE + (PORT dataa (923:923:923) (975:975:975)) + (PORT datab (198:198:198) (238:238:238)) + (PORT datac (1881:1881:1881) (1931:1931:1931)) + (PORT datad (1149:1149:1149) (1161:1161:1161)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[4\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (1196:1196:1196) (1252:1252:1252)) + (PORT datab (698:698:698) (741:741:741)) + (PORT datac (359:359:359) (392:392:392)) + (PORT datad (378:378:378) (403:403:403)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[4\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (604:604:604) (626:626:626)) + (PORT datab (1093:1093:1093) (1119:1119:1119)) + (PORT datac (853:853:853) (862:862:862)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[4\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (694:694:694) (749:749:749)) + (PORT datab (341:341:341) (374:374:374)) + (PORT datac (405:405:405) (444:444:444)) + (PORT datad (368:368:368) (394:394:394)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[4\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (647:647:647) (673:673:673)) + (PORT datab (917:917:917) (929:929:929)) + (PORT datac (595:595:595) (614:614:614)) + (PORT datad (663:663:663) (684:684:684)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[4\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (746:746:746) (777:777:777)) + (PORT datab (256:256:256) (317:317:317)) + (PORT datac (174:174:174) (208:208:208)) + (PORT datad (599:599:599) (615:615:615)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[3\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (911:911:911) (923:923:923)) + (PORT datab (1205:1205:1205) (1303:1303:1303)) + (PORT datad (858:858:858) (880:880:880)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[3\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (377:377:377) (403:403:403)) + (PORT datab (1119:1119:1119) (1166:1166:1166)) + (PORT datac (692:692:692) (749:749:749)) + (PORT datad (1069:1069:1069) (1074:1074:1074)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[3\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (871:871:871) (932:932:932)) + (PORT datab (907:907:907) (925:925:925)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_low\[3\]\~25) + (DELAY + (ABSOLUTE + (PORT datab (702:702:702) (739:739:739)) + (PORT datac (693:693:693) (746:746:746)) + (PORT datad (195:195:195) (220:220:220)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[3\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (678:678:678) (751:751:751)) + (PORT datab (1133:1133:1133) (1158:1158:1158)) + (PORT datac (673:673:673) (734:734:734)) + (PORT datad (774:774:774) (776:776:776)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_low\|Q\[3\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1193:1193:1193) (1211:1211:1211)) + (PORT datab (901:901:901) (928:928:928)) + (PORT datac (919:919:919) (941:941:941)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_low\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1535:1535:1535) (1540:1540:1540)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[3\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (964:964:964) (991:991:991)) + (PORT datab (811:811:811) (818:818:818)) + (PORT datac (1164:1164:1164) (1176:1176:1176)) + (PORT datad (627:627:627) (661:661:661)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_op2_latch_mux_high\|Q\[3\]\~1) + (DELAY + (ABSOLUTE + (PORT datab (905:905:905) (934:934:934)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_\|op2_high\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1535:1535:1535) (1540:1540:1540)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|alu_op2\[3\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (701:701:701) (723:723:723)) + (PORT datab (701:701:701) (774:774:774)) + (PORT datac (885:885:885) (890:890:890)) + (PORT datad (663:663:663) (720:720:720)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|SYNTHESIZED_WIRE_1) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (254:254:254)) + (PORT datab (205:205:205) (245:245:245)) + (PORT datac (1129:1129:1129) (1129:1129:1129)) + (PORT datad (202:202:202) (230:230:230)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_3\|result\~0) + (DELAY + (ABSOLUTE + (PORT dataa (367:367:367) (405:405:405)) + (PORT datab (394:394:394) (419:419:419)) + (PORT datac (551:551:551) (560:560:560)) + (PORT datad (339:339:339) (361:361:361)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (245:245:245) (300:300:300)) + (PORT datab (618:618:618) (675:675:675)) + (PORT datac (1466:1466:1466) (1547:1547:1547)) + (PORT datad (223:223:223) (253:253:253)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1084:1084:1084) (1105:1105:1105)) + (PORT datab (211:211:211) (255:255:255)) + (PORT datad (1179:1179:1179) (1265:1265:1265)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1087:1087:1087) (1092:1092:1092)) + (PORT datab (1119:1119:1119) (1162:1162:1162)) + (PORT datad (307:307:307) (322:322:322)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (266:266:266) (338:338:338)) + (PORT datab (276:276:276) (332:332:332)) + (PORT datac (1117:1117:1117) (1128:1128:1128)) + (PORT datad (250:250:250) (294:294:294)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (643:643:643) (671:671:671)) + (PORT datab (344:344:344) (376:376:376)) + (PORT datac (640:640:640) (694:694:694)) + (PORT datad (609:609:609) (635:635:635)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db_high\[3\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (871:871:871) (932:932:932)) + (PORT datab (630:630:630) (668:668:668)) + (PORT datac (346:346:346) (371:371:371)) + (PORT datad (556:556:556) (562:562:562)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_34) + (DELAY + (ABSOLUTE + (PORT dataa (885:885:885) (932:932:932)) + (PORT datab (1083:1083:1083) (1097:1097:1097)) + (PORT datac (521:521:521) (536:536:536)) + (PORT datad (632:632:632) (660:660:660)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_sf) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1218:1218:1218) (1200:1200:1200)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~5) + (DELAY + (ABSOLUTE + (PORT dataa (238:238:238) (287:287:287)) + (PORT datab (247:247:247) (295:295:295)) + (PORT datac (621:621:621) (646:646:646)) + (PORT datad (879:879:879) (944:944:944)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1712:1712:1712) (1781:1781:1781)) + (PORT datab (894:894:894) (917:917:917)) + (PORT datac (1041:1041:1041) (1058:1058:1058)) + (PORT datad (939:939:939) (999:999:999)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_nop3pla68M2T2_3) + (DELAY + (ABSOLUTE + (PORT dataa (2280:2280:2280) (2349:2349:2349)) + (PORT datab (2206:2206:2206) (2381:2381:2381)) + (PORT datac (2140:2140:2140) (2225:2225:2225)) + (PORT datad (725:725:725) (814:814:814)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1277:1277:1277) (1318:1318:1318)) + (PORT datab (953:953:953) (983:983:983)) + (PORT datac (2034:2034:2034) (2052:2052:2052)) + (PORT datad (1669:1669:1669) (1733:1733:1733)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~8) + (DELAY + (ABSOLUTE + (PORT dataa (880:880:880) (926:926:926)) + (PORT datab (198:198:198) (238:238:238)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~11) + (DELAY + (ABSOLUTE + (PORT dataa (825:825:825) (825:825:825)) + (PORT datab (1077:1077:1077) (1071:1071:1071)) + (PORT datac (1238:1238:1238) (1269:1269:1269)) + (PORT datad (580:580:580) (592:592:592)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~12) + (DELAY + (ABSOLUTE + (PORT dataa (668:668:668) (729:729:729)) + (PORT datab (664:664:664) (729:729:729)) + (PORT datac (653:653:653) (709:709:709)) + (PORT datad (1168:1168:1168) (1191:1191:1191)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_sel_op2_neg\~15) + (DELAY + (ABSOLUTE + (PORT dataa (838:838:838) (864:864:864)) + (PORT datab (742:742:742) (832:832:832)) + (PORT datac (172:172:172) (206:206:206)) + (PORT datad (1009:1009:1009) (1024:1024:1024)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|alu_\|alu_op2\[2\]\~0) (DELAY (ABSOLUTE - (PORT dataa (461:461:461) (534:534:534)) - (PORT datab (695:695:695) (720:720:720)) - (PORT datac (877:877:877) (900:900:900)) - (PORT datad (417:417:417) (490:490:490)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT dataa (705:705:705) (729:729:729)) + (PORT datab (917:917:917) (927:927:927)) + (PORT datac (577:577:577) (626:626:626)) + (PORT datad (657:657:657) (722:722:722)) + (IOPATH dataa combout (337:337:337) (347:347:347)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -28190,12 +26519,12 @@ (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|SYNTHESIZED_WIRE_1) (DELAY (ABSOLUTE - (PORT dataa (388:388:388) (411:411:411)) - (PORT datab (395:395:395) (424:424:424)) - (PORT datac (177:177:177) (214:214:214)) - (PORT datad (345:345:345) (368:368:368)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) + (PORT dataa (207:207:207) (255:255:255)) + (PORT datab (207:207:207) (250:250:250)) + (PORT datac (1131:1131:1131) (1130:1130:1130)) + (PORT datad (632:632:632) (653:653:653)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -28206,10 +26535,10 @@ (INSTANCE z80_\|alu_\|b2v_core\|b2v_alu_slice_bit_2\|result\~0) (DELAY (ABSOLUTE - (PORT dataa (368:368:368) (407:407:407)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (180:180:180) (217:217:217)) - (PORT datad (354:354:354) (383:383:383)) + (PORT dataa (214:214:214) (264:264:264)) + (PORT datab (197:197:197) (234:234:234)) + (PORT datac (346:346:346) (370:370:370)) + (PORT datad (634:634:634) (650:650:650)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (243:243:243) (242:242:242)) @@ -28218,30 +26547,32 @@ ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~9) + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_control_\|DFFE_latch_pf_tmp) (DELAY (ABSOLUTE - (PORT dataa (1176:1176:1176) (1207:1207:1207)) - (PORT datab (281:281:281) (344:344:344)) - (PORT datac (244:244:244) (303:303:303)) - (PORT datad (255:255:255) (301:301:301)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT clk (1542:1542:1542) (1558:1558:1558)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (2192:2192:2192) (2164:2164:2164)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~11) + (INSTANCE z80_\|alu_\|alu_parity_out\~0) (DELAY (ABSOLUTE - (PORT dataa (1695:1695:1695) (1779:1779:1779)) - (PORT datac (887:887:887) (904:904:904)) - (PORT datad (883:883:883) (900:900:900)) - (IOPATH dataa combout (356:356:356) (368:368:368)) + (PORT dataa (938:938:938) (957:957:957)) + (PORT datab (390:390:390) (456:456:456)) + (PORT datac (865:865:865) (875:875:875)) + (PORT datad (1093:1093:1093) (1147:1147:1147)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -28249,76 +26580,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~12) + (INSTANCE z80_\|alu_\|alu_parity_out\~1) (DELAY (ABSOLUTE - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (911:911:911) (960:960:960)) - (PORT datad (237:237:237) (277:277:277)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (638:638:638) (711:711:711)) - (PORT datab (1166:1166:1166) (1213:1213:1213)) - (PORT datac (421:421:421) (493:493:493)) - (PORT datad (662:662:662) (719:719:719)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datab (1116:1116:1116) (1164:1164:1164)) - (PORT datac (603:603:603) (622:622:622)) - (PORT datad (629:629:629) (654:654:654)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[2\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1253:1253:1253) (1347:1347:1347)) - (PORT datab (239:239:239) (295:295:295)) - (PORT datac (959:959:959) (993:993:993)) - (PORT datad (329:329:329) (348:348:348)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[6\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (1295:1295:1295) (1347:1347:1347)) - (PORT datab (963:963:963) (1021:1021:1021)) - (PORT datac (1621:1621:1621) (1653:1653:1653)) - (PORT datad (867:867:867) (886:886:886)) - (IOPATH dataa combout (350:350:350) (366:366:366)) + (PORT dataa (540:540:540) (566:566:566)) + (PORT datab (530:530:530) (556:556:556)) + (PORT datac (171:171:171) (205:205:205)) + (PORT datad (864:864:864) (870:870:870)) + (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -28327,13 +26596,141 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[6\]\~23) + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~4) (DELAY (ABSOLUTE - (PORT dataa (644:644:644) (667:667:667)) - (PORT datab (983:983:983) (1034:1034:1034)) - (PORT datac (313:313:313) (343:343:343)) - (PORT datad (228:228:228) (273:273:273)) + (PORT dataa (937:937:937) (954:954:954)) + (PORT datab (1448:1448:1448) (1493:1493:1493)) + (PORT datac (747:747:747) (825:825:825)) + (PORT datad (1218:1218:1218) (1214:1214:1214)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~5) + (DELAY + (ABSOLUTE + (PORT dataa (998:998:998) (1078:1078:1078)) + (PORT datab (537:537:537) (564:564:564)) + (PORT datac (556:556:556) (566:566:566)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1711:1711:1711) (1763:1763:1763)) + (PORT datab (1530:1530:1530) (1589:1589:1589)) + (PORT datac (746:746:746) (827:827:827)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~1) + (DELAY + (ABSOLUTE + (PORT dataa (996:996:996) (1074:1074:1074)) + (PORT datab (1245:1245:1245) (1252:1252:1252)) + (PORT datac (903:903:903) (917:917:917)) + (PORT datad (1415:1415:1415) (1455:1455:1455)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~2) + (DELAY + (ABSOLUTE + (PORT dataa (969:969:969) (1032:1032:1032)) + (PORT datab (1232:1232:1232) (1293:1293:1293)) + (PORT datac (1228:1228:1228) (1282:1282:1282)) + (PORT datad (586:586:586) (644:644:644)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~1) + (DELAY + (ABSOLUTE + (PORT dataa (970:970:970) (1065:1065:1065)) + (PORT datab (965:965:965) (1048:1048:1048)) + (PORT datac (244:244:244) (323:323:323)) + (PORT datad (420:420:420) (487:487:487)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~3) + (DELAY + (ABSOLUTE + (PORT dataa (281:281:281) (374:374:374)) + (PORT datab (270:270:270) (354:354:354)) + (PORT datac (243:243:243) (321:321:321)) + (PORT datad (805:805:805) (861:861:861)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~0) + (DELAY + (ABSOLUTE + (PORT dataa (269:269:269) (363:363:363)) + (PORT datab (408:408:408) (479:479:479)) + (PORT datac (244:244:244) (322:322:322)) + (PORT datad (403:403:403) (466:466:466)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~4) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (201:201:201) (241:241:241)) + (PORT datac (615:615:615) (627:627:627)) + (PORT datad (315:315:315) (336:336:336)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -28343,155 +26740,46 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|out\[6\]\~1) + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep\~5) (DELAY (ABSOLUTE - (PORT dataa (390:390:390) (465:465:465)) - (PORT datab (263:263:263) (345:345:345)) - (PORT datac (236:236:236) (312:312:312)) - (PORT datad (196:196:196) (222:222:222)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|out\[6\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1182:1182:1182) (1227:1227:1227)) - (PORT datab (658:658:658) (671:671:671)) - (PORT datac (632:632:632) (691:691:691)) - (PORT datad (234:234:234) (310:310:310)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1155:1155:1155) (1213:1213:1213)) - (PORT datab (894:894:894) (942:942:942)) - (PORT datac (660:660:660) (687:687:687)) - (PORT datad (883:883:883) (901:901:901)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~20) - (DELAY - (ABSOLUTE - (PORT datab (924:924:924) (933:933:933)) - (PORT datac (1121:1121:1121) (1153:1153:1153)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (970:970:970) (1018:1018:1018)) - (PORT datab (950:950:950) (1001:1001:1001)) - (PORT datac (170:170:170) (202:202:202)) - (PORT datad (876:876:876) (911:911:911)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~22) - (DELAY - (ABSOLUTE - (PORT dataa (689:689:689) (714:714:714)) - (PORT datab (198:198:198) (236:236:236)) - (PORT datac (1597:1597:1597) (1627:1627:1627)) - (PORT datad (861:861:861) (875:875:875)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_zero_oe\~0) - (DELAY - (ABSOLUTE - (PORT dataa (640:640:640) (655:655:655)) - (PORT datab (1245:1245:1245) (1272:1272:1272)) - (PORT datac (1147:1147:1147) (1195:1195:1195)) - (PORT datad (336:336:336) (365:365:365)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\~3) - (DELAY - (ABSOLUTE - (PORT datab (287:287:287) (348:348:348)) - (PORT datad (249:249:249) (295:295:295)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (PORT dataa (884:884:884) (911:911:911)) + (PORT datab (1164:1164:1164) (1198:1198:1198)) + (PORT datad (2161:2161:2161) (2216:2216:2216)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|im1) + (INSTANCE z80_\|decode_state_\|DFFE_instNonRep) (DELAY (ABSOLUTE - (PORT clk (1525:1525:1525) (1541:1541:1541)) + (PORT clk (1523:1523:1523) (1536:1536:1536)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1571:1571:1571) (1550:1550:1550)) - (PORT ena (1258:1258:1258) (1280:1280:1280)) + (PORT clrn (1566:1566:1566) (1548:1548:1548)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) ) (TIMINGCHECK (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_ff_oe\~0) + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~2) (DELAY (ABSOLUTE - (PORT dataa (1215:1215:1215) (1260:1260:1260)) - (PORT datab (1208:1208:1208) (1291:1291:1291)) - (PORT datac (1222:1222:1222) (1290:1290:1290)) - (PORT datad (272:272:272) (349:349:349)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (304:304:304) (311:311:311)) + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (1161:1161:1161) (1229:1229:1229)) + (PORT datac (408:408:408) (474:474:474)) + (PORT datad (1668:1668:1668) (1715:1715:1715)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -28499,31 +26787,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_ff_oe\~1) + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~3) (DELAY (ABSOLUTE - (PORT dataa (353:353:353) (485:485:485)) - (PORT datab (196:196:196) (235:235:235)) - (PORT datac (1143:1143:1143) (1174:1174:1174)) - (PORT datad (1174:1174:1174) (1212:1212:1212)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (775:775:775) (860:860:860)) + (PORT datac (1129:1129:1129) (1197:1197:1197)) + (PORT datad (1504:1504:1504) (1551:1551:1551)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[0\]\~4) + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~7) (DELAY (ABSOLUTE - (PORT dataa (993:993:993) (1051:1051:1051)) - (PORT datab (1152:1152:1152) (1212:1212:1212)) - (PORT datac (671:671:671) (716:716:716)) - (PORT datad (621:621:621) (670:670:670)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT dataa (1708:1708:1708) (1759:1759:1759)) + (PORT datab (1533:1533:1533) (1591:1591:1591)) + (PORT datac (2080:2080:2080) (2120:2120:2120)) + (PORT datad (1220:1220:1220) (1219:1219:1219)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -28531,59 +26819,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[6\]\~8) + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~8) (DELAY (ABSOLUTE - (PORT datab (864:864:864) (885:885:885)) - (PORT datac (946:946:946) (986:986:986)) - (PORT datad (214:214:214) (249:249:249)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~37) - (DELAY - (ABSOLUTE - (PORT dataa (1300:1300:1300) (1399:1399:1399)) - (PORT datab (2075:2075:2075) (2259:2259:2259)) - (PORT datac (822:822:822) (879:879:879)) - (PORT datad (913:913:913) (964:964:964)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~28) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (1269:1269:1269) (1304:1304:1304)) - (PORT datac (1404:1404:1404) (1456:1456:1456)) - (PORT datad (913:913:913) (977:977:977)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~29) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (242:242:242)) - (PORT datab (241:241:241) (281:281:281)) - (PORT datac (1941:1941:1941) (2072:2072:2072)) - (PORT datad (187:187:187) (218:218:218)) + (PORT dataa (941:941:941) (961:961:961)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (746:746:746) (824:824:824)) + (PORT datad (969:969:969) (1032:1032:1032)) (IOPATH dataa combout (304:304:304) (308:308:308)) (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -28593,13 +26835,45 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~30) + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~9) (DELAY (ABSOLUTE - (PORT dataa (875:875:875) (914:914:914)) - (PORT datab (230:230:230) (277:277:277)) - (PORT datac (631:631:631) (653:653:653)) - (PORT datad (955:955:955) (999:999:999)) + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (175:175:175) (202:202:202)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~0) + (DELAY + (ABSOLUTE + (PORT dataa (861:861:861) (924:924:924)) + (PORT datab (266:266:266) (349:349:349)) + (PORT datac (826:826:826) (871:871:871)) + (PORT datad (603:603:603) (618:618:618)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1167:1167:1167) (1185:1185:1185)) + (PORT datab (859:859:859) (905:905:905)) + (PORT datac (1075:1075:1075) (1090:1090:1090)) + (PORT datad (174:174:174) (200:200:200)) (IOPATH dataa combout (327:327:327) (347:347:347)) (IOPATH datab combout (331:331:331) (342:342:342)) (IOPATH datac combout (243:243:243) (241:241:241)) @@ -28608,48 +26882,46 @@ ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~37) + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_pf) (DELAY (ABSOLUTE - (PORT dataa (1051:1051:1051) (1095:1095:1095)) - (PORT datab (1067:1067:1067) (1105:1105:1105)) - (PORT datac (1033:1033:1033) (1064:1064:1064)) - (PORT datad (634:634:634) (644:644:644)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~55) + (INSTANCE z80_\|alu_control_\|sel\[1\]\~0) (DELAY (ABSOLUTE - (PORT dataa (960:960:960) (1056:1056:1056)) - (PORT datab (1130:1130:1130) (1132:1132:1132)) - (PORT datac (939:939:939) (1031:1031:1031)) - (PORT datad (1060:1060:1060) (1062:1062:1062)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~38) - (DELAY - (ABSOLUTE - (PORT dataa (888:888:888) (940:940:940)) - (PORT datab (200:200:200) (240:240:240)) - (PORT datac (539:539:539) (555:555:555)) - (PORT datad (545:545:545) (556:556:556)) + (PORT dataa (1236:1236:1236) (1265:1265:1265)) + (PORT datab (1389:1389:1389) (1522:1522:1522)) + (PORT datac (201:201:201) (251:251:251)) + (PORT datad (858:858:858) (898:898:898)) (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|b2v_inst_cond_mux\|out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (274:274:274) (366:366:366)) + (PORT datab (610:610:610) (623:623:623)) + (PORT datac (1009:1009:1009) (1040:1040:1040)) + (PORT datad (1045:1045:1045) (1094:1094:1094)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (304:304:304) (311:311:311)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -28657,15 +26929,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~34) + (INSTANCE z80_\|alu_control_\|b2v_inst_cond_mux\|out\~1) (DELAY (ABSOLUTE - (PORT dataa (682:682:682) (715:715:715)) - (PORT datab (898:898:898) (929:929:929)) - (PORT datac (1980:1980:1980) (2019:2019:2019)) - (PORT datad (830:830:830) (842:842:842)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) + (PORT dataa (905:905:905) (961:961:961)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (1008:1008:1008) (1039:1039:1039)) + (PORT datad (239:239:239) (309:309:309)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -28673,137 +26945,88 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~3) + (INSTANCE z80_\|alu_control_\|flags_cond_true\~0) (DELAY (ABSOLUTE - (PORT datab (833:833:833) (894:894:894)) - (PORT datac (622:622:622) (675:675:675)) - (PORT datad (207:207:207) (239:239:239)) + (PORT dataa (983:983:983) (1049:1049:1049)) + (PORT datab (762:762:762) (857:857:857)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~31) + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_control_\|flags_cond_true) (DELAY (ABSOLUTE - (PORT dataa (231:231:231) (279:279:279)) - (PORT datab (238:238:238) (284:284:284)) - (PORT datac (356:356:356) (385:385:385)) - (PORT datad (1060:1060:1060) (1062:1062:1062)) - (IOPATH dataa combout (354:354:354) (367:367:367)) + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~20) + (DELAY + (ABSOLUTE + (PORT dataa (1921:1921:1921) (2028:2028:2028)) + (PORT datab (896:896:896) (1016:1016:1016)) + (PORT datac (838:838:838) (860:860:860)) + (PORT datad (927:927:927) (1020:1020:1020)) + (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~32) + (INSTANCE z80_\|execute_\|ctl_sw_4d\~1) (DELAY (ABSOLUTE - (PORT dataa (719:719:719) (787:787:787)) - (PORT datab (1609:1609:1609) (1627:1627:1627)) - (PORT datac (617:617:617) (649:649:649)) - (PORT datad (544:544:544) (562:562:562)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (914:914:914) (954:954:954)) + (PORT datab (1571:1571:1571) (1598:1598:1598)) + (PORT datac (589:589:589) (609:609:609)) + (PORT datad (345:345:345) (368:368:368)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~33) + (INSTANCE z80_\|execute_\|ctl_sw_4d\~6) (DELAY (ABSOLUTE - (PORT datab (553:553:553) (575:575:575)) - (PORT datac (1318:1318:1318) (1317:1317:1317)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~35) - (DELAY - (ABSOLUTE - (PORT dataa (1048:1048:1048) (1070:1070:1070)) - (PORT datab (577:577:577) (591:591:591)) - (PORT datac (783:783:783) (785:785:785)) - (PORT datad (770:770:770) (770:770:770)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (180:180:180) (208:208:208)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|DFFE_mrd_ff1) + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_lo\|latch\[1\]) (DELAY (ABSOLUTE - (PORT clk (1535:1535:1535) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1591:1591:1591) (1566:1566:1566)) - (PORT ena (1291:1291:1291) (1310:1310:1310)) + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (893:893:893) (901:901:901)) + (PORT ena (1200:1200:1200) (1181:1181:1181)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|wait_mrd\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (815:815:815) (866:866:866)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|wait_mrd) - (DELAY - (ABSOLUTE - (PORT clk (1540:1540:1540) (1538:1538:1538)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1588:1588:1588) (1565:1565:1565)) - (PORT ena (1172:1172:1172) (1151:1151:1151)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|DFFE_mrd_ff3) - (DELAY - (ABSOLUTE - (PORT clk (1542:1542:1542) (1544:1544:1544)) - (PORT asdata (1226:1226:1226) (1290:1290:1290)) - (PORT clrn (1591:1591:1591) (1566:1566:1566)) - (PORT ena (1321:1321:1321) (1347:1347:1347)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) ) (TIMINGCHECK @@ -28813,12 +27036,492 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|nRD_out\~1) + (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~4) (DELAY (ABSOLUTE - (PORT dataa (909:909:909) (983:983:983)) - (PORT datad (215:215:215) (284:284:284)) + (PORT dataa (892:892:892) (941:941:941)) + (PORT datab (1199:1199:1199) (1216:1216:1216)) + (PORT datad (403:403:403) (442:442:442)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1231:1231:1231) (1237:1237:1237)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~5) + (DELAY + (ABSOLUTE + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (215:215:215) (292:292:292)) + (PORT datad (613:613:613) (638:638:638)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_0\|d1_out) + (DELAY + (ABSOLUTE + (PORT dataa (665:665:665) (729:729:729)) + (PORT datac (192:192:192) (226:226:226)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_as\[1\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1648:1648:1648) (1674:1674:1674)) + (PORT datab (198:198:198) (236:236:236)) + (PORT datac (1059:1059:1059) (1066:1066:1066)) + (PORT datad (349:349:349) (378:378:378)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT asdata (1302:1302:1302) (1309:1309:1309)) + (PORT ena (1438:1438:1438) (1476:1476:1476)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (701:701:701) (767:767:767)) + (PORT datab (1396:1396:1396) (1392:1392:1392)) + (PORT datad (849:849:849) (862:862:862)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT asdata (979:979:979) (998:998:998)) + (PORT ena (790:790:790) (782:782:782)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT asdata (980:980:980) (995:995:995)) + (PORT ena (1288:1288:1288) (1306:1306:1306)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (257:257:257) (313:313:313)) + (PORT datab (240:240:240) (321:321:321)) + (PORT datad (634:634:634) (698:698:698)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT asdata (970:970:970) (1000:1000:1000)) + (PORT ena (1220:1220:1220) (1212:1212:1212)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT asdata (972:972:972) (1003:1003:1003)) + (PORT ena (1200:1200:1200) (1188:1188:1188)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (861:861:861) (934:934:934)) + (PORT datab (243:243:243) (325:325:325)) + (PORT datad (661:661:661) (726:726:726)) (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1535:1535:1535)) + (PORT asdata (1831:1831:1831) (1846:1846:1846)) + (PORT ena (1274:1274:1274) (1265:1265:1265)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~27) + (DELAY + (ABSOLUTE + (PORT datab (604:604:604) (620:620:620)) + (PORT datad (923:923:923) (952:952:952)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (590:590:590) (603:603:603)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datad (808:808:808) (811:811:811)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT asdata (1017:1017:1017) (1050:1050:1050)) + (PORT ena (981:981:981) (980:980:980)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT asdata (1017:1017:1017) (1051:1051:1051)) + (PORT ena (811:811:811) (804:804:804)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (243:243:243) (329:329:329)) + (PORT datab (252:252:252) (300:300:300)) + (PORT datad (233:233:233) (270:270:270)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1549:1549:1549)) + (PORT asdata (563:563:563) (596:596:596)) + (PORT ena (974:974:974) (969:969:969)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1549:1549:1549)) + (PORT asdata (566:566:566) (599:599:599)) + (PORT ena (975:975:975) (970:970:970)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (407:407:407) (451:451:451)) + (PORT datab (440:440:440) (467:467:467)) + (PORT datad (216:216:216) (285:285:285)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1549:1549:1549)) + (PORT asdata (969:969:969) (979:979:979)) + (PORT ena (1240:1240:1240) (1231:1231:1231)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1529:1529:1529) (1549:1549:1549)) + (PORT asdata (969:969:969) (979:979:979)) + (PORT ena (1207:1207:1207) (1180:1180:1180)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (695:695:695) (738:738:738)) + (PORT datab (706:706:706) (729:729:729)) + (PORT datad (216:216:216) (284:284:284)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (609:609:609) (629:629:629)) + (PORT datab (625:625:625) (639:639:639)) + (PORT datac (173:173:173) (207:207:207)) + (PORT datad (334:334:334) (356:356:356)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[1\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (864:864:864) (905:905:905)) + (PORT datab (867:867:867) (896:896:896)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (202:202:202) (229:229:229)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_lo_ds\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (828:828:828) (858:858:858)) + (PORT datab (1125:1125:1125) (1165:1165:1165)) + (PORT datac (655:655:655) (680:680:680)) + (PORT datad (656:656:656) (708:708:708)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[1\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (204:204:204) (249:249:249)) + (PORT datab (706:706:706) (725:725:725)) + (PORT datac (407:407:407) (452:452:452)) + (PORT datad (834:834:834) (844:844:844)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[1\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (885:885:885) (898:898:898)) + (PORT datab (1129:1129:1129) (1147:1147:1147)) + (PORT datac (359:359:359) (390:390:390)) + (PORT datad (1401:1401:1401) (1460:1460:1460)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[1\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (348:348:348) (380:380:380)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (600:600:600) (611:611:611)) + (PORT datad (216:216:216) (251:251:251)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (571:571:571) (599:599:599)) + (PORT datac (1398:1398:1398) (1439:1439:1439)) + (PORT datad (597:597:597) (611:611:611)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -28828,12 +27531,12 @@ (INSTANCE z80_\|execute_\|nextM\~4) (DELAY (ABSOLUTE - (PORT dataa (233:233:233) (281:281:281)) - (PORT datab (702:702:702) (781:781:781)) - (PORT datac (856:856:856) (898:898:898)) - (PORT datad (1074:1074:1074) (1111:1111:1111)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT dataa (1236:1236:1236) (1302:1302:1302)) + (PORT datab (677:677:677) (701:701:701)) + (PORT datac (1229:1229:1229) (1298:1298:1298)) + (PORT datad (664:664:664) (715:715:715)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -28844,12 +27547,12 @@ (INSTANCE z80_\|execute_\|ctl_iorw\~12) (DELAY (ABSOLUTE - (PORT dataa (1890:1890:1890) (1960:1960:1960)) - (PORT datab (1472:1472:1472) (1522:1522:1522)) - (PORT datac (1489:1489:1489) (1536:1536:1536)) - (PORT datad (1919:1919:1919) (1985:1985:1985)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT dataa (894:894:894) (948:948:948)) + (PORT datab (1333:1333:1333) (1473:1473:1473)) + (PORT datac (890:890:890) (957:957:957)) + (PORT datad (1498:1498:1498) (1591:1591:1591)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -28860,10 +27563,10 @@ (INSTANCE z80_\|execute_\|ctl_iorw\~8) (DELAY (ABSOLUTE - (PORT dataa (1104:1104:1104) (1152:1152:1152)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (201:201:201) (236:236:236)) - (PORT datad (679:679:679) (747:747:747)) + (PORT dataa (1241:1241:1241) (1304:1304:1304)) + (PORT datab (645:645:645) (695:695:695)) + (PORT datac (926:926:926) (972:972:972)) + (PORT datad (658:658:658) (708:708:708)) (IOPATH dataa combout (304:304:304) (299:299:299)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -28876,12 +27579,12 @@ (INSTANCE z80_\|execute_\|ctl_iorw\~9) (DELAY (ABSOLUTE - (PORT dataa (876:876:876) (891:891:891)) - (PORT datab (1170:1170:1170) (1227:1227:1227)) - (PORT datac (822:822:822) (840:840:840)) - (PORT datad (805:805:805) (814:814:814)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (331:331:331) (342:342:342)) + (PORT dataa (1705:1705:1705) (1717:1717:1717)) + (PORT datab (1161:1161:1161) (1188:1188:1188)) + (PORT datac (418:418:418) (456:456:456)) + (PORT datad (1002:1002:1002) (1015:1015:1015)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -28892,10 +27595,10 @@ (INSTANCE z80_\|memory_ifc_\|DFFE_iorq_ff1) (DELAY (ABSOLUTE - (PORT clk (1535:1535:1535) (1551:1551:1551)) + (PORT clk (1531:1531:1531) (1550:1550:1550)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1591:1591:1591) (1566:1566:1566)) - (PORT ena (1291:1291:1291) (1310:1310:1310)) + (PORT clrn (1578:1578:1578) (1557:1557:1557)) + (PORT ena (1463:1463:1463) (1456:1456:1456)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -28905,43 +27608,15 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_15\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (220:220:220) (290:290:290)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_15) (DELAY (ABSOLUTE - (PORT clk (1535:1535:1535) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1591:1591:1591) (1566:1566:1566)) - (PORT ena (1291:1291:1291) (1310:1310:1310)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|wait_iorq) - (DELAY - (ABSOLUTE - (PORT clk (1542:1542:1542) (1544:1544:1544)) - (PORT asdata (581:581:581) (655:655:655)) - (PORT clrn (1591:1591:1591) (1566:1566:1566)) - (PORT ena (1321:1321:1321) (1347:1347:1347)) + (PORT clk (1531:1531:1531) (1550:1550:1550)) + (PORT asdata (742:742:742) (811:811:811)) + (PORT clrn (1578:1578:1578) (1557:1557:1557)) + (PORT ena (1463:1463:1463) (1456:1456:1456)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -28951,15 +27626,43 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|wait_iorq\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (226:226:226) (298:298:298)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|wait_iorq) + (DELAY + (ABSOLUTE + (PORT clk (1541:1541:1541) (1540:1540:1540)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1578:1578:1578) (1557:1557:1557)) + (PORT ena (1434:1434:1434) (1415:1415:1415)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|memory_ifc_\|DFFE_iorq_ff4) (DELAY (ABSOLUTE - (PORT clk (1542:1542:1542) (1544:1544:1544)) - (PORT asdata (567:567:567) (645:645:645)) - (PORT clrn (1591:1591:1591) (1566:1566:1566)) - (PORT ena (1321:1321:1321) (1347:1347:1347)) + (PORT clk (1541:1541:1541) (1540:1540:1540)) + (PORT asdata (567:567:567) (643:643:643)) + (PORT clrn (1578:1578:1578) (1557:1557:1557)) + (PORT ena (1434:1434:1434) (1415:1415:1415)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -28974,93 +27677,29 @@ (INSTANCE z80_\|memory_ifc_\|iorq\~0) (DELAY (ABSOLUTE - (PORT datab (250:250:250) (335:335:335)) - (PORT datad (613:613:613) (663:663:663)) + (PORT datab (250:250:250) (333:333:333)) + (PORT datad (224:224:224) (295:295:295)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIORead\~1) - (DELAY - (ABSOLUTE - (PORT dataa (222:222:222) (265:265:265)) - (PORT datab (941:941:941) (1024:1024:1024)) - (PORT datac (374:374:374) (401:401:401)) - (PORT datad (217:217:217) (243:243:243)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIORead\~2) - (DELAY - (ABSOLUTE - (PORT dataa (888:888:888) (913:913:913)) - (PORT datab (215:215:215) (260:260:260)) - (PORT datac (1187:1187:1187) (1208:1208:1208)) - (PORT datad (1091:1091:1091) (1137:1137:1137)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIORead\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1889:1889:1889) (1932:1932:1932)) - (PORT datab (1525:1525:1525) (1597:1597:1597)) - (PORT datac (2202:2202:2202) (2248:2248:2248)) - (PORT datad (210:210:210) (242:242:242)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIORead\~3) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (263:263:263)) - (PORT datab (336:336:336) (366:366:366)) - (PORT datac (586:586:586) (589:589:589)) - (PORT datad (351:351:351) (382:382:382)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|memory_ifc_\|DFFE_m1_ff1) (DELAY (ABSOLUTE - (PORT clk (1540:1540:1540) (1541:1541:1541)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1588:1588:1588) (1563:1563:1563)) - (PORT ena (1810:1810:1810) (1851:1851:1851)) + (PORT clk (1541:1541:1541) (1540:1540:1540)) + (PORT asdata (909:909:909) (908:908:908)) + (PORT clrn (1578:1578:1578) (1557:1557:1557)) + (PORT ena (1434:1434:1434) (1415:1415:1415)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) ) ) @@ -29069,7 +27708,7 @@ (INSTANCE z80_\|memory_ifc_\|wait_m_ALTERA_SYNTHESIZED1\~0) (DELAY (ABSOLUTE - (PORT datad (586:586:586) (642:642:642)) + (PORT datad (220:220:220) (290:290:290)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -29079,10 +27718,10 @@ (INSTANCE z80_\|memory_ifc_\|wait_m_ALTERA_SYNTHESIZED1) (DELAY (ABSOLUTE - (PORT clk (1542:1542:1542) (1544:1544:1544)) + (PORT clk (1541:1541:1541) (1540:1540:1540)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1591:1591:1591) (1566:1566:1566)) - (PORT ena (1321:1321:1321) (1347:1347:1347)) + (PORT clrn (1578:1578:1578) (1557:1557:1557)) + (PORT ena (1434:1434:1434) (1415:1415:1415)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -29097,10 +27736,10 @@ (INSTANCE z80_\|memory_ifc_\|DFFE_m1_ff3) (DELAY (ABSOLUTE - (PORT clk (1535:1535:1535) (1551:1551:1551)) - (PORT asdata (568:568:568) (646:646:646)) - (PORT clrn (1591:1591:1591) (1566:1566:1566)) - (PORT ena (1291:1291:1291) (1310:1310:1310)) + (PORT clk (1531:1531:1531) (1550:1550:1550)) + (PORT asdata (566:566:566) (646:646:646)) + (PORT clrn (1578:1578:1578) (1557:1557:1557)) + (PORT ena (1463:1463:1463) (1456:1456:1456)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -29115,11 +27754,11 @@ (INSTANCE z80_\|memory_ifc_\|nRD_out\~0) (DELAY (ABSOLUTE - (PORT dataa (1456:1456:1456) (1520:1520:1520)) - (PORT datab (251:251:251) (336:336:336)) - (PORT datad (1485:1485:1485) (1574:1574:1574)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) + (PORT dataa (251:251:251) (341:341:341)) + (PORT datab (691:691:691) (771:771:771)) + (PORT datad (888:888:888) (958:958:958)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -29127,99 +27766,151 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|nRD_out\~2) + (INSTANCE z80_\|execute_\|fIORead\~0) (DELAY (ABSOLUTE - (PORT dataa (340:340:340) (376:376:376)) - (PORT datab (352:352:352) (391:391:391)) - (PORT datac (1027:1027:1027) (1030:1030:1030)) - (PORT datad (180:180:180) (209:209:209)) - (IOPATH dataa combout (371:371:371) (376:376:376)) + (PORT dataa (1279:1279:1279) (1321:1321:1321)) + (PORT datab (2174:2174:2174) (2263:2263:2263)) + (PORT datac (1118:1118:1118) (1130:1130:1130)) + (PORT datad (2170:2170:2170) (2342:2342:2342)) + (IOPATH dataa combout (327:327:327) (347:347:347)) (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Equal2\~1) + (INSTANCE z80_\|execute_\|fIORead\~1) (DELAY (ABSOLUTE - (PORT dataa (1747:1747:1747) (1852:1852:1852)) - (PORT datab (1597:1597:1597) (1730:1730:1730)) - (PORT datac (1200:1200:1200) (1265:1265:1265)) - (IOPATH dataa combout (356:356:356) (368:368:368)) + (PORT dataa (666:666:666) (725:725:725)) + (PORT datab (1591:1591:1591) (1692:1692:1692)) + (PORT datac (1661:1661:1661) (1724:1724:1724)) + (PORT datad (195:195:195) (219:219:219)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIORead\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1692:1692:1692) (1763:1763:1763)) + (PORT datab (228:228:228) (268:268:268)) + (PORT datac (171:171:171) (203:203:203)) + (PORT datad (1162:1162:1162) (1199:1199:1199)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIOWrite\~1) + (DELAY + (ABSOLUTE + (PORT dataa (682:682:682) (765:765:765)) + (PORT datac (994:994:994) (1080:1080:1080)) + (PORT datad (194:194:194) (220:220:220)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIORead\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1209:1209:1209) (1261:1261:1261)) + (PORT datab (650:650:650) (700:700:700)) + (PORT datac (1322:1322:1322) (1379:1379:1379)) + (PORT datad (181:181:181) (210:210:210)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~30) + (DELAY + (ABSOLUTE + (PORT dataa (1161:1161:1161) (1178:1178:1178)) + (PORT datab (1372:1372:1372) (1394:1394:1394)) + (PORT datac (1442:1442:1442) (1487:1487:1487)) + (PORT datad (1300:1300:1300) (1339:1339:1339)) + (IOPATH dataa combout (341:341:341) (319:319:319)) (IOPATH datab combout (342:342:342) (318:318:318)) (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~0) + (INSTANCE z80_\|execute_\|ctl_mRead\~31) (DELAY (ABSOLUTE - (PORT dataa (2395:2395:2395) (2551:2551:2551)) - (PORT datad (1014:1014:1014) (1128:1128:1128)) + (PORT dataa (947:947:947) (994:994:994)) + (PORT datac (592:592:592) (623:623:623)) + (PORT datad (858:858:858) (892:892:892)) (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~5) + (INSTANCE z80_\|execute_\|nextM\~3) (DELAY (ABSOLUTE - (PORT datab (1342:1342:1342) (1445:1445:1445)) - (PORT datac (2885:2885:2885) (3060:3060:3060)) - (PORT datad (2470:2470:2470) (2672:2672:2672)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (1192:1192:1192) (1262:1262:1262)) + (PORT datab (366:366:366) (408:408:408)) + (PORT datac (1561:1561:1561) (1669:1669:1669)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~6) + (INSTANCE z80_\|execute_\|ctl_mRead\~29) (DELAY (ABSOLUTE - (PORT dataa (378:378:378) (401:401:401)) - (PORT datab (883:883:883) (892:892:892)) - (PORT datac (957:957:957) (1029:1029:1029)) - (PORT datad (1073:1073:1073) (1058:1058:1058)) + (PORT dataa (231:231:231) (277:277:277)) + (PORT datab (1152:1152:1152) (1217:1217:1217)) + (PORT datac (922:922:922) (972:972:972)) + (PORT datad (1258:1258:1258) (1312:1312:1312)) (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~2) + (INSTANCE z80_\|execute_\|setM1\~58) (DELAY (ABSOLUTE - (PORT dataa (931:931:931) (1027:1027:1027)) - (PORT datac (1189:1189:1189) (1270:1270:1270)) - (PORT datad (2029:2029:2029) (2154:2154:2154)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1470:1470:1470) (1514:1514:1514)) - (PORT datab (897:897:897) (976:976:976)) - (PORT datac (362:362:362) (383:383:383)) - (PORT datad (193:193:193) (218:218:218)) + (PORT dataa (264:264:264) (351:351:351)) + (PORT datab (279:279:279) (360:360:360)) + (PORT datac (590:590:590) (620:620:620)) + (PORT datad (819:819:819) (832:832:832)) (IOPATH dataa combout (341:341:341) (319:319:319)) (IOPATH datab combout (342:342:342) (318:318:318)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -29229,14 +27920,272 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~1) + (INSTANCE z80_\|execute_\|setM1\~38) (DELAY (ABSOLUTE - (PORT dataa (678:678:678) (736:736:736)) - (PORT datab (837:837:837) (873:873:873)) - (PORT datac (876:876:876) (891:891:891)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (354:354:354) (349:349:349)) + (PORT datac (882:882:882) (918:918:918)) + (PORT datad (181:181:181) (209:209:209)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1166:1166:1166) (1211:1211:1211)) + (PORT datab (634:634:634) (687:687:687)) + (PORT datad (632:632:632) (649:649:649)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~39) + (DELAY + (ABSOLUTE + (PORT dataa (1118:1118:1118) (1184:1184:1184)) + (PORT datac (847:847:847) (847:847:847)) + (PORT datad (1982:1982:1982) (2076:2076:2076)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~40) + (DELAY + (ABSOLUTE + (PORT dataa (847:847:847) (900:900:900)) + (PORT datab (912:912:912) (955:955:955)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (799:799:799) (849:849:849)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~32) + (DELAY + (ABSOLUTE + (PORT dataa (217:217:217) (269:269:269)) + (PORT datab (938:938:938) (966:966:966)) + (PORT datac (344:344:344) (377:377:377)) + (PORT datad (361:361:361) (382:382:382)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~33) + (DELAY + (ABSOLUTE + (PORT dataa (382:382:382) (406:406:406)) + (PORT datab (706:706:706) (753:753:753)) + (PORT datac (1380:1380:1380) (1388:1388:1388)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|DFFE_mrd_ff1) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1558:1558:1558) (1539:1539:1539)) + (PORT ena (1458:1458:1458) (1464:1464:1464)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|wait_mrd\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (922:922:922) (980:980:980)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|wait_mrd) + (DELAY + (ABSOLUTE + (PORT clk (1541:1541:1541) (1540:1540:1540)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1578:1578:1578) (1557:1557:1557)) + (PORT ena (1434:1434:1434) (1415:1415:1415)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|DFFE_mrd_ff3) + (DELAY + (ABSOLUTE + (PORT clk (1541:1541:1541) (1540:1540:1540)) + (PORT asdata (575:575:575) (657:657:657)) + (PORT clrn (1578:1578:1578) (1557:1557:1557)) + (PORT ena (1434:1434:1434) (1415:1415:1415)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|nRD_out\~1) + (DELAY + (ABSOLUTE + (PORT datac (232:232:232) (316:316:316)) + (PORT datad (217:217:217) (286:286:286)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|nRD_out\~2) + (DELAY + (ABSOLUTE + (PORT dataa (359:359:359) (396:396:396)) + (PORT datab (352:352:352) (382:382:382)) + (PORT datac (617:617:617) (624:624:624)) + (PORT datad (328:328:328) (345:345:345)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIOWrite\~3) + (DELAY + (ABSOLUTE + (PORT datab (1524:1524:1524) (1641:1641:1641)) + (PORT datac (995:995:995) (1081:1081:1081)) + (PORT datad (655:655:655) (722:722:722)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIOWrite\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1038:1038:1038) (1076:1076:1076)) + (PORT datab (663:663:663) (710:710:710)) + (PORT datac (174:174:174) (208:208:208)) + (PORT datad (1064:1064:1064) (1054:1054:1054)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIOWrite\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1282:1282:1282) (1318:1318:1318)) + (PORT datab (1147:1147:1147) (1226:1226:1226)) + (PORT datac (850:850:850) (883:883:883)) + (PORT datad (1534:1534:1534) (1603:1603:1603)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fIOWrite\~5) + (DELAY + (ABSOLUTE + (PORT dataa (998:998:998) (1057:1057:1057)) + (PORT datab (200:200:200) (239:239:239)) + (PORT datac (581:581:581) (624:624:624)) + (PORT datad (180:180:180) (208:208:208)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1510:1510:1510) (1571:1571:1571)) + (PORT datab (900:900:900) (924:924:924)) + (PORT datac (669:669:669) (712:712:712)) + (PORT datad (342:342:342) (372:372:372)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~12) + (DELAY + (ABSOLUTE + (PORT dataa (718:718:718) (781:781:781)) + (PORT datab (628:628:628) (691:691:691)) + (PORT datac (598:598:598) (632:632:632)) + (PORT datad (348:348:348) (371:371:371)) + (IOPATH dataa combout (337:337:337) (338:338:338)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -29245,32 +28194,231 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~2) + (INSTANCE z80_\|execute_\|ctl_mWrite\~13) (DELAY (ABSOLUTE - (PORT dataa (1253:1253:1253) (1311:1311:1311)) - (PORT datab (870:870:870) (881:881:881)) - (PORT datac (1299:1299:1299) (1298:1298:1298)) - (PORT datad (625:625:625) (681:681:681)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (325:325:325)) + (PORT dataa (1200:1200:1200) (1223:1223:1223)) + (PORT datab (595:595:595) (608:608:608)) + (PORT datac (613:613:613) (635:635:635)) + (PORT datad (953:953:953) (996:996:996)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~14) + (DELAY + (ABSOLUTE + (PORT dataa (609:609:609) (626:626:626)) + (PORT datab (641:641:641) (671:671:671)) + (PORT datac (171:171:171) (205:205:205)) + (PORT datad (630:630:630) (667:667:667)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mWrite\~16) + (DELAY + (ABSOLUTE + (PORT dataa (862:862:862) (907:907:907)) + (PORT datab (850:850:850) (904:904:904)) + (PORT datac (1001:1001:1001) (1039:1039:1039)) + (PORT datad (915:915:915) (962:962:962)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (304:304:304) (308:308:308)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|DFFE_mwr_ff1) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1550:1550:1550)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1578:1578:1578) (1557:1557:1557)) + (PORT ena (1463:1463:1463) (1456:1456:1456)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|wait_mwr\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (219:219:219) (288:288:288)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|wait_mwr) + (DELAY + (ABSOLUTE + (PORT clk (1541:1541:1541) (1540:1540:1540)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1578:1578:1578) (1557:1557:1557)) + (PORT ena (1434:1434:1434) (1415:1415:1415)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|memory_ifc_\|mwr_wr) + (DELAY + (ABSOLUTE + (PORT clk (1541:1541:1541) (1540:1540:1540)) + (PORT asdata (567:567:567) (646:646:646)) + (PORT clrn (1578:1578:1578) (1557:1557:1557)) + (PORT ena (1434:1434:1434) (1415:1415:1415)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|memory_ifc_\|nWR_out\~0) + (DELAY + (ABSOLUTE + (PORT dataa (656:656:656) (680:680:680)) + (PORT datab (221:221:221) (260:260:260)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal2\~1) + (DELAY + (ABSOLUTE + (PORT datab (2798:2798:2798) (2990:2990:2990)) + (PORT datac (551:551:551) (572:572:572)) + (PORT datad (605:605:605) (624:624:624)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1274:1274:1274) (1333:1333:1333)) + (PORT datab (1518:1518:1518) (1582:1582:1582)) + (PORT datac (1806:1806:1806) (1891:1891:1891)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~4) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (265:265:265)) + (PORT datab (1176:1176:1176) (1239:1239:1239)) + (PORT datac (1171:1171:1171) (1216:1216:1216)) + (PORT datad (885:885:885) (932:932:932)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2087:2087:2087) (2180:2180:2180)) + (PORT datac (1567:1567:1567) (1702:1702:1702)) + (PORT datad (1512:1512:1512) (1607:1607:1607)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1232:1232:1232) (1278:1278:1278)) + (PORT datab (204:204:204) (246:246:246)) + (PORT datac (1687:1687:1687) (1766:1766:1766)) + (PORT datad (1285:1285:1285) (1324:1324:1324)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~3) (DELAY (ABSOLUTE - (PORT dataa (198:198:198) (242:242:242)) - (PORT datab (1100:1100:1100) (1104:1104:1104)) - (PORT datac (369:369:369) (395:395:395)) - (PORT datad (1798:1798:1798) (1887:1887:1887)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (345:345:345) (375:375:375)) + (PORT datab (901:901:901) (982:982:982)) + (PORT datac (606:606:606) (625:625:625)) + (PORT datad (1750:1750:1750) (1772:1772:1772)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~8) + (DELAY + (ABSOLUTE + (PORT dataa (964:964:964) (1050:1050:1050)) + (PORT datab (1272:1272:1272) (1308:1308:1308)) + (PORT datac (1058:1058:1058) (1063:1063:1063)) + (PORT datad (1189:1189:1189) (1207:1207:1207)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -29280,74 +28428,28 @@ (INSTANCE z80_\|execute_\|fMWrite\~7) (DELAY (ABSOLUTE - (PORT datab (916:916:916) (964:964:964)) - (PORT datac (850:850:850) (896:896:896)) - (PORT datad (781:781:781) (791:791:791)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (913:913:913) (975:975:975)) + (PORT datab (1052:1052:1052) (1084:1084:1084)) + (PORT datac (1145:1145:1145) (1210:1210:1210)) + (PORT datad (1125:1125:1125) (1136:1136:1136)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~4) + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~16) (DELAY (ABSOLUTE - (PORT dataa (1515:1515:1515) (1583:1583:1583)) - (PORT datab (200:200:200) (239:239:239)) - (PORT datac (1714:1714:1714) (1760:1760:1760)) - (PORT datad (881:881:881) (920:920:920)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1447:1447:1447) (1506:1506:1506)) - (PORT datab (1169:1169:1169) (1174:1174:1174)) - (PORT datac (894:894:894) (923:923:923)) - (PORT datad (781:781:781) (794:794:794)) + (PORT dataa (615:615:615) (682:682:682)) + (PORT datab (1168:1168:1168) (1211:1211:1211)) + (PORT datac (1681:1681:1681) (1773:1773:1773)) + (PORT datad (2059:2059:2059) (2140:2140:2140)) (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1513:1513:1513) (1581:1581:1581)) - (PORT datab (1150:1150:1150) (1204:1204:1204)) - (PORT datac (1094:1094:1094) (1111:1111:1111)) - (PORT datad (616:616:616) (634:634:634)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1253:1253:1253) (1361:1361:1361)) - (PORT datab (869:869:869) (894:894:894)) - (PORT datac (1706:1706:1706) (1761:1761:1761)) - (PORT datad (263:263:263) (315:315:315)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -29358,13 +28460,29 @@ (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~8) (DELAY (ABSOLUTE - (PORT dataa (1146:1146:1146) (1188:1188:1188)) - (PORT datab (214:214:214) (258:258:258)) - (PORT datac (192:192:192) (225:225:225)) - (PORT datad (621:621:621) (651:651:651)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (1324:1324:1324) (1371:1371:1371)) + (PORT datab (646:646:646) (678:678:678)) + (PORT datac (1703:1703:1703) (1791:1791:1791)) + (PORT datad (1158:1158:1158) (1211:1211:1211)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMWrite\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1015:1015:1015) (1130:1130:1130)) + (PORT datab (1047:1047:1047) (1185:1185:1185)) + (PORT datac (699:699:699) (763:763:763)) + (PORT datad (1149:1149:1149) (1171:1171:1171)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -29374,26 +28492,12 @@ (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~9) (DELAY (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (222:222:222) (261:261:261)) - (PORT datac (1051:1051:1051) (1068:1068:1068)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1101:1101:1101) (1104:1104:1104)) - (PORT datab (879:879:879) (888:888:888)) - (PORT datac (609:609:609) (624:624:624)) - (PORT datad (1198:1198:1198) (1221:1221:1221)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) + (PORT dataa (656:656:656) (682:682:682)) + (PORT datab (926:926:926) (943:943:943)) + (PORT datac (919:919:919) (950:950:950)) + (PORT datad (181:181:181) (210:210:210)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -29401,15 +28505,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~5) + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~7) (DELAY (ABSOLUTE - (PORT dataa (901:901:901) (927:927:927)) - (PORT datab (206:206:206) (246:246:246)) - (PORT datac (583:583:583) (601:601:601)) - (PORT datad (197:197:197) (223:223:223)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) + (PORT dataa (1685:1685:1685) (1721:1721:1721)) + (PORT datab (644:644:644) (666:666:666)) + (PORT datac (1247:1247:1247) (1297:1297:1297)) + (PORT datad (944:944:944) (994:994:994)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -29421,9 +28525,9 @@ (DELAY (ABSOLUTE (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (199:199:199) (239:239:239)) - (PORT datac (332:332:332) (351:351:351)) - (PORT datad (813:813:813) (840:840:840)) + (PORT datab (198:198:198) (238:238:238)) + (PORT datac (171:171:171) (205:205:205)) + (PORT datad (174:174:174) (200:200:200)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -29433,31 +28537,45 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMWrite\~10) + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~11) (DELAY (ABSOLUTE - (PORT dataa (881:881:881) (906:906:906)) - (PORT datab (1043:1043:1043) (1098:1098:1098)) - (PORT datac (1093:1093:1093) (1111:1111:1111)) - (PORT datad (1130:1130:1130) (1132:1132:1132)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (1135:1135:1135) (1136:1136:1136)) + (PORT datab (613:613:613) (639:639:639)) + (PORT datac (1433:1433:1433) (1447:1447:1447)) + (PORT datad (607:607:607) (657:657:657)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~11) + (INSTANCE z80_\|execute_\|fMWrite\~5) (DELAY (ABSOLUTE - (PORT dataa (202:202:202) (247:247:247)) - (PORT datab (199:199:199) (239:239:239)) - (PORT datac (173:173:173) (206:206:206)) - (PORT datad (181:181:181) (210:210:210)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) + (PORT dataa (1525:1525:1525) (1584:1584:1584)) + (PORT datab (1242:1242:1242) (1306:1306:1306)) + (PORT datac (901:901:901) (949:949:949)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~6) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (209:209:209) (252:252:252)) + (PORT datac (1251:1251:1251) (1315:1315:1315)) + (PORT datad (1976:1976:1976) (2069:2069:2069)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -29468,29 +28586,61 @@ (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~12) (DELAY (ABSOLUTE - (PORT dataa (572:572:572) (605:605:605)) - (PORT datab (1113:1113:1113) (1136:1136:1136)) - (PORT datac (1714:1714:1714) (1760:1760:1760)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (333:333:333) (332:332:332)) + (PORT dataa (676:676:676) (728:728:728)) + (PORT datab (638:638:638) (697:697:697)) + (PORT datac (907:907:907) (942:942:942)) + (PORT datad (171:171:171) (196:196:196)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~4) + (DELAY + (ABSOLUTE + (PORT dataa (403:403:403) (428:428:428)) + (PORT datab (1485:1485:1485) (1511:1511:1511)) + (PORT datac (652:652:652) (695:695:695)) + (PORT datad (1507:1507:1507) (1573:1573:1573)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1795:1795:1795) (1871:1871:1871)) + (PORT datab (1177:1177:1177) (1242:1242:1242)) + (PORT datac (607:607:607) (643:643:643)) + (PORT datad (854:854:854) (884:884:884)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~13) (DELAY (ABSOLUTE - (PORT dataa (675:675:675) (726:726:726)) - (PORT datab (198:198:198) (236:236:236)) - (PORT datac (612:612:612) (639:639:639)) - (PORT datad (196:196:196) (220:220:220)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (198:198:198) (241:241:241)) + (PORT datab (972:972:972) (1020:1020:1020)) + (PORT datac (1248:1248:1248) (1305:1305:1305)) + (PORT datad (1976:1976:1976) (2070:2070:2070)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -29500,23 +28650,51 @@ (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~14) (DELAY (ABSOLUTE - (PORT dataa (198:198:198) (241:241:241)) - (PORT datab (930:930:930) (979:979:979)) - (PORT datac (1054:1054:1054) (1167:1167:1167)) - (PORT datad (1137:1137:1137) (1183:1183:1183)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (598:598:598) (646:646:646)) + (PORT datab (938:938:938) (995:995:995)) + (PORT datac (592:592:592) (636:636:636)) + (PORT datad (594:594:594) (607:607:607)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~2) + (DELAY + (ABSOLUTE + (PORT datab (1021:1021:1021) (1085:1085:1085)) + (PORT datad (951:951:951) (1011:1011:1011)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_oe\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1357:1357:1357) (1373:1373:1373)) + (PORT datab (344:344:344) (377:377:377)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (652:652:652) (719:719:719)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE z80_\|clk_delay_\|DFF_inst5\~feeder) (DELAY (ABSOLUTE - (PORT datad (225:225:225) (296:296:296)) + (PORT datad (1320:1320:1320) (1382:1382:1382)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -29526,9 +28704,9 @@ (INSTANCE z80_\|clk_delay_\|DFF_inst5) (DELAY (ABSOLUTE - (PORT clk (1528:1528:1528) (1547:1547:1547)) + (PORT clk (1520:1520:1520) (1539:1539:1539)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1587:1587:1587) (1563:1563:1563)) + (PORT clrn (1566:1566:1566) (1545:1545:1545)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -29537,30 +28715,20 @@ (HOLD d (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|wait_iorqinta\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (228:228:228) (301:301:301)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|memory_ifc_\|wait_iorqinta) (DELAY (ABSOLUTE - (PORT clk (1538:1538:1538) (1537:1537:1537)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1587:1587:1587) (1563:1563:1563)) + (PORT clk (1541:1541:1541) (1539:1539:1539)) + (PORT asdata (1496:1496:1496) (1564:1564:1564)) + (PORT clrn (1577:1577:1577) (1556:1556:1556)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) ) ) (CELL @@ -29568,9 +28736,9 @@ (INSTANCE z80_\|memory_ifc_\|DFFE_intr_ff3) (DELAY (ABSOLUTE - (PORT clk (1528:1528:1528) (1547:1547:1547)) - (PORT asdata (568:568:568) (647:647:647)) - (PORT clrn (1587:1587:1587) (1563:1563:1563)) + (PORT clk (1530:1530:1530) (1550:1550:1550)) + (PORT asdata (567:567:567) (644:644:644)) + (PORT clrn (1577:1577:1577) (1556:1556:1556)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -29584,11 +28752,11 @@ (INSTANCE z80_\|memory_ifc_\|nIORQ_out\~0) (DELAY (ABSOLUTE - (PORT dataa (253:253:253) (342:342:342)) - (PORT datad (605:605:605) (631:631:631)) - (IOPATH dataa combout (354:354:354) (367:367:367)) + (PORT dataa (562:562:562) (579:579:579)) + (PORT datab (250:250:250) (334:334:334)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -29597,28 +28765,12 @@ (INSTANCE Equal2\~0) (DELAY (ABSOLUTE - (PORT dataa (1750:1750:1750) (1853:1853:1853)) - (PORT datab (1593:1593:1593) (1734:1734:1734)) - (PORT datac (1199:1199:1199) (1264:1264:1264)) - (PORT datad (1222:1222:1222) (1307:1307:1307)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ExtRamWE\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1747:1747:1747) (1852:1852:1852)) - (PORT datab (1597:1597:1597) (1730:1730:1730)) - (PORT datac (1200:1200:1200) (1265:1265:1265)) - (PORT datad (1220:1220:1220) (1307:1307:1307)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT dataa (245:245:245) (300:300:300)) + (PORT datab (2799:2799:2799) (2989:2989:2989)) + (PORT datac (549:549:549) (569:569:569)) + (PORT datad (605:605:605) (620:620:620)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -29626,12 +28778,26 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[13\]\~13) + (INSTANCE z80_\|execute_\|ctl_apin_mux\~2) (DELAY (ABSOLUTE - (PORT dataa (1796:1796:1796) (1810:1810:1810)) - (PORT datab (849:849:849) (873:873:873)) - (PORT datad (335:335:335) (353:353:353)) + (PORT dataa (873:873:873) (893:893:893)) + (PORT datac (1481:1481:1481) (1512:1512:1512)) + (PORT datad (852:852:852) (904:904:904)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[10\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1433:1433:1433) (1480:1480:1480)) + (PORT datab (535:535:535) (553:553:553)) + (PORT datad (317:317:317) (337:337:337)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -29643,651 +28809,55 @@ (INSTANCE z80_\|execute_\|ctl_apin_mux2\~0) (DELAY (ABSOLUTE - (PORT dataa (949:949:949) (1028:1028:1028)) - (PORT datab (994:994:994) (1080:1080:1080)) - (PORT datac (1875:1875:1875) (2047:2047:2047)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) + (PORT dataa (1979:1979:1979) (2093:2093:2093)) + (PORT datab (1651:1651:1651) (1771:1771:1771)) + (PORT datac (1461:1461:1461) (1587:1587:1587)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (342:342:342) (318:318:318)) (IOPATH datac combout (241:241:241) (241:241:241)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_ab_pin_we\~2) + (INSTANCE z80_\|pin_control_\|bus_ab_pin_we\~0) (DELAY (ABSOLUTE - (PORT dataa (1686:1686:1686) (1827:1827:1827)) - (PORT datab (974:974:974) (1024:1024:1024)) - (PORT datac (941:941:941) (1003:1003:1003)) - (PORT datad (1201:1201:1201) (1259:1259:1259)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_ab_pin_we\~3) - (DELAY - (ABSOLUTE - (PORT dataa (948:948:948) (1027:1027:1027)) - (PORT datab (994:994:994) (1080:1080:1080)) - (PORT datac (1875:1875:1875) (2047:2047:2047)) - (PORT datad (622:622:622) (660:660:660)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[13\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1534:1534:1534)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (603:603:603) (689:689:689)) - (PORT sload (1125:1125:1125) (1169:1169:1169)) - (PORT ena (1155:1155:1155) (1129:1129:1129)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[13\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (1195:1195:1195) (1254:1254:1254)) - (PORT datad (2019:2019:2019) (2140:2140:2140)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[14\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1794:1794:1794) (1807:1807:1807)) - (PORT datab (219:219:219) (257:257:257)) - (PORT datad (320:320:320) (334:334:334)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[14\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1534:1534:1534)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (590:590:590) (668:668:668)) - (PORT sload (1125:1125:1125) (1169:1169:1169)) - (PORT ena (1155:1155:1155) (1129:1129:1129)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[14\]\~23) - (DELAY - (ABSOLUTE - (PORT datab (2045:2045:2045) (2178:2178:2178)) - (PORT datad (1147:1147:1147) (1202:1202:1202)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[15\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1796:1796:1796) (1810:1810:1810)) - (PORT datab (337:337:337) (371:371:371)) - (PORT datad (554:554:554) (561:561:561)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[15\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1534:1534:1534)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (577:577:577) (658:658:658)) - (PORT sload (1125:1125:1125) (1169:1169:1169)) - (PORT ena (1155:1155:1155) (1129:1129:1129)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[15\]\~22) - (DELAY - (ABSOLUTE - (PORT datab (1641:1641:1641) (1729:1729:1729)) - (PORT datac (1584:1584:1584) (1634:1634:1634)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode236w\[2\]) - (DELAY - (ABSOLUTE - (PORT dataa (697:697:697) (725:725:725)) - (PORT datab (261:261:261) (314:314:314)) - (PORT datac (366:366:366) (404:404:404)) - (PORT datad (1304:1304:1304) (1296:1296:1296)) - (IOPATH dataa combout (300:300:300) (308:308:308)) + (PORT dataa (991:991:991) (1078:1078:1078)) + (PORT datab (228:228:228) (269:269:269)) + (PORT datad (1333:1333:1333) (1330:1330:1330)) + (IOPATH dataa combout (301:301:301) (307:307:307)) (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|rden_decode\|w_anode284w\[2\]\~0) + (INSTANCE z80_\|pin_control_\|bus_ab_pin_we\~1) (DELAY (ABSOLUTE - (PORT datab (2037:2037:2037) (2174:2174:2174)) - (PORT datac (1153:1153:1153) (1208:1208:1208)) - (PORT datad (1144:1144:1144) (1203:1203:1203)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[0\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (911:911:911) (971:971:971)) - (PORT datad (1987:1987:1987) (2083:2083:2083)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[1\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (854:854:854) (879:879:879)) - (PORT datab (373:373:373) (396:396:396)) - (PORT datad (334:334:334) (343:343:343)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1548:1548:1548) (1550:1550:1550)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (1128:1128:1128) (1174:1174:1174)) - (PORT sload (1213:1213:1213) (1283:1283:1283)) - (PORT ena (1456:1456:1456) (1440:1440:1440)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[1\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (1793:1793:1793) (1909:1909:1909)) - (PORT datad (678:678:678) (733:733:733)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[2\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (855:855:855) (880:880:880)) - (PORT datab (604:604:604) (620:620:620)) - (PORT datad (532:532:532) (544:544:544)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1548:1548:1548) (1550:1550:1550)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (992:992:992) (1045:1045:1045)) - (PORT sload (1213:1213:1213) (1283:1283:1283)) - (PORT ena (1456:1456:1456) (1440:1440:1440)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[2\]\~26) - (DELAY - (ABSOLUTE - (PORT datac (1749:1749:1749) (1862:1862:1862)) - (PORT datad (642:642:642) (699:699:699)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[3\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (858:858:858) (887:887:887)) - (PORT datab (535:535:535) (551:551:551)) - (PORT datad (339:339:339) (355:355:355)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1548:1548:1548) (1550:1550:1550)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (751:751:751) (807:807:807)) - (PORT sload (1213:1213:1213) (1283:1283:1283)) - (PORT ena (1456:1456:1456) (1440:1440:1440)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[3\]\~27) - (DELAY - (ABSOLUTE - (PORT datac (1754:1754:1754) (1872:1872:1872)) - (PORT datad (367:367:367) (429:429:429)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[4\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (853:853:853) (880:880:880)) - (PORT datab (534:534:534) (559:559:559)) - (PORT datad (339:339:339) (357:357:357)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1548:1548:1548) (1550:1550:1550)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (979:979:979) (1031:1031:1031)) - (PORT sload (1213:1213:1213) (1283:1283:1283)) - (PORT ena (1456:1456:1456) (1440:1440:1440)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[4\]\~28) - (DELAY - (ABSOLUTE - (PORT datac (1758:1758:1758) (1874:1874:1874)) - (PORT datad (652:652:652) (710:710:710)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[5\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1351:1351:1351) (1385:1385:1385)) - (PORT datab (337:337:337) (371:371:371)) - (PORT datad (196:196:196) (222:222:222)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1533:1533:1533)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (1019:1019:1019) (1078:1078:1078)) - (PORT sload (1150:1150:1150) (1218:1218:1218)) - (PORT ena (1176:1176:1176) (1166:1166:1166)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[5\]\~29) - (DELAY - (ABSOLUTE - (PORT datab (2021:2021:2021) (2124:2124:2124)) - (PORT datac (676:676:676) (743:743:743)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[6\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (221:221:221) (260:260:260)) - (PORT datad (1323:1323:1323) (1343:1343:1343)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1533:1533:1533)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (1156:1156:1156) (1209:1209:1209)) - (PORT sload (1150:1150:1150) (1218:1218:1218)) - (PORT ena (1176:1176:1176) (1166:1166:1166)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[6\]\~30) - (DELAY - (ABSOLUTE - (PORT datab (696:696:696) (759:759:759)) - (PORT datac (1750:1750:1750) (1863:1863:1863)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[7\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1354:1354:1354) (1387:1387:1387)) - (PORT datab (199:199:199) (239:239:239)) - (PORT datad (194:194:194) (219:219:219)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1533:1533:1533)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (1639:1639:1639) (1657:1657:1657)) - (PORT sload (1150:1150:1150) (1218:1218:1218)) - (PORT ena (1176:1176:1176) (1166:1166:1166)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[7\]\~31) - (DELAY - (ABSOLUTE - (PORT datac (1748:1748:1748) (1867:1867:1867)) - (PORT datad (927:927:927) (1010:1010:1010)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[8\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (342:342:342) (380:380:380)) - (PORT datab (1361:1361:1361) (1369:1369:1369)) - (PORT datad (196:196:196) (222:222:222)) + (PORT dataa (1078:1078:1078) (1090:1090:1090)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (1490:1490:1490) (1609:1609:1609)) + (PORT datad (873:873:873) (922:922:922)) (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[8\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1533:1533:1533)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (597:597:597) (678:678:678)) - (PORT sload (1150:1150:1150) (1218:1218:1218)) - (PORT ena (1176:1176:1176) (1166:1166:1166)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[8\]\~18) - (DELAY - (ABSOLUTE - (PORT datab (948:948:948) (1009:1009:1009)) - (PORT datad (2008:2008:2008) (2130:2130:2130)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[9\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1391:1391:1391) (1422:1422:1422)) - (PORT datab (220:220:220) (259:259:259)) - (PORT datad (552:552:552) (561:561:561)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[9\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1533:1533:1533)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (591:591:591) (677:677:677)) - (PORT sload (1117:1117:1117) (1168:1168:1168)) - (PORT ena (811:811:811) (804:804:804)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[9\]\~17) - (DELAY - (ABSOLUTE - (PORT datac (1757:1757:1757) (1868:1868:1868)) - (PORT datad (678:678:678) (737:737:737)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[10\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (264:264:264)) - (PORT datab (567:567:567) (585:585:585)) - (PORT datad (1365:1365:1365) (1379:1379:1379)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[10\]) (DELAY (ABSOLUTE - (PORT clk (1528:1528:1528) (1533:1533:1533)) + (PORT clk (1523:1523:1523) (1527:1527:1527)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (580:580:580) (668:668:668)) - (PORT sload (1117:1117:1117) (1168:1168:1168)) - (PORT ena (811:811:811) (804:804:804)) + (PORT asdata (581:581:581) (655:655:655)) + (PORT sload (2032:2032:2032) (2084:2084:2084)) + (PORT ena (2298:2298:2298) (2265:2265:2265)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -30298,5778 +28868,6 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[10\]\~24) - (DELAY - (ABSOLUTE - (PORT datac (910:910:910) (972:972:972)) - (PORT datad (1442:1442:1442) (1565:1565:1565)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[11\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (264:264:264)) - (PORT datab (197:197:197) (234:234:234)) - (PORT datad (1362:1362:1362) (1374:1374:1374)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[11\]) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1533:1533:1533)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (913:913:913) (972:972:972)) - (PORT sload (1117:1117:1117) (1168:1168:1168)) - (PORT ena (811:811:811) (804:804:804)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[11\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (942:942:942) (1010:1010:1010)) - (PORT datad (1442:1442:1442) (1566:1566:1566)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[12\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (340:340:340) (375:375:375)) - (PORT datab (816:816:816) (834:834:834)) - (PORT datad (1561:1561:1561) (1571:1571:1571)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[12\]) - (DELAY - (ABSOLUTE - (PORT clk (1529:1529:1529) (1534:1534:1534)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (583:583:583) (667:667:667)) - (PORT sload (1125:1125:1125) (1169:1169:1169)) - (PORT ena (1155:1155:1155) (1129:1129:1129)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|address_pins_\|abus\[12\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1791:1791:1791) (1903:1903:1903)) - (PORT datad (854:854:854) (913:913:913)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1010:1010:1010) (1062:1062:1062)) - (PORT clk (1856:1856:1856) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1009:1009:1009) (1047:1047:1047)) - (PORT d[1] (2076:2076:2076) (2305:2305:2305)) - (PORT d[2] (1463:1463:1463) (1514:1514:1514)) - (PORT d[3] (2867:2867:2867) (3072:3072:3072)) - (PORT d[4] (2625:2625:2625) (2841:2841:2841)) - (PORT d[5] (3152:3152:3152) (3353:3353:3353)) - (PORT d[6] (1368:1368:1368) (1453:1453:1453)) - (PORT d[7] (2906:2906:2906) (3079:3079:3079)) - (PORT d[8] (997:997:997) (1014:1014:1014)) - (PORT d[9] (1597:1597:1597) (1654:1654:1654)) - (PORT d[10] (1607:1607:1607) (1695:1695:1695)) - (PORT d[11] (2235:2235:2235) (2380:2380:2380)) - (PORT d[12] (1610:1610:1610) (1712:1712:1712)) - (PORT clk (1853:1853:1853) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (958:958:958) (934:934:934)) - (PORT clk (1853:1853:1853) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1883:1883:1883)) - (PORT d[0] (1472:1472:1472) (1458:1458:1458)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1816:1816:1816) (1842:1842:1842)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1001:1001:1001) (1005:1005:1005)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1002:1002:1002) (1006:1006:1006)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1002:1002:1002) (1006:1006:1006)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1002:1002:1002) (1006:1006:1006)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1896:1896:1896) (1918:1918:1918)) - (PORT asdata (2035:2035:2035) (2085:2085:2085)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1543:1543:1543)) - (PORT asdata (1451:1451:1451) (1488:1488:1488)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode223w\[2\]) - (DELAY - (ABSOLUTE - (PORT dataa (697:697:697) (725:725:725)) - (PORT datab (262:262:262) (316:316:316)) - (PORT datac (367:367:367) (405:405:405)) - (PORT datad (1303:1303:1303) (1300:1300:1300)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode223w\[2\]\~0) - (DELAY - (ABSOLUTE - (PORT datab (2042:2042:2042) (2178:2178:2178)) - (PORT datac (1154:1154:1154) (1211:1211:1211)) - (PORT datad (1145:1145:1145) (1206:1206:1206)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (991:991:991) (1045:1045:1045)) - (PORT clk (1854:1854:1854) (1881:1881:1881)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1010:1010:1010) (1048:1048:1048)) - (PORT d[1] (2092:2092:2092) (2316:2316:2316)) - (PORT d[2] (3345:3345:3345) (3458:3458:3458)) - (PORT d[3] (2859:2859:2859) (3062:3062:3062)) - (PORT d[4] (2566:2566:2566) (2775:2775:2775)) - (PORT d[5] (3169:3169:3169) (3393:3393:3393)) - (PORT d[6] (1618:1618:1618) (1695:1695:1695)) - (PORT d[7] (2898:2898:2898) (3057:3057:3057)) - (PORT d[8] (1024:1024:1024) (1046:1046:1046)) - (PORT d[9] (3241:3241:3241) (3372:3372:3372)) - (PORT d[10] (1642:1642:1642) (1735:1735:1735)) - (PORT d[11] (1916:1916:1916) (2070:2070:2070)) - (PORT d[12] (1870:1870:1870) (1971:1971:1971)) - (PORT clk (1851:1851:1851) (1877:1877:1877)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (950:950:950) (925:925:925)) - (PORT clk (1851:1851:1851) (1877:1877:1877)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1854:1854:1854) (1881:1881:1881)) - (PORT d[0] (1713:1713:1713) (1683:1683:1683)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1855:1855:1855) (1882:1882:1882)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1855:1855:1855) (1882:1882:1882)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1855:1855:1855) (1882:1882:1882)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1855:1855:1855) (1882:1882:1882)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1814:1814:1814) (1840:1840:1840)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (999:999:999) (1003:1003:1003)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1000:1000:1000) (1004:1004:1004)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1000:1000:1000) (1004:1004:1004)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1000:1000:1000) (1004:1004:1004)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) - (PORT asdata (1470:1470:1470) (1518:1518:1518)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) - (PORT asdata (706:706:706) (770:770:770)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode244w\[2\]) - (DELAY - (ABSOLUTE - (PORT dataa (700:700:700) (726:726:726)) - (PORT datab (266:266:266) (319:319:319)) - (PORT datac (371:371:371) (404:404:404)) - (PORT datad (1304:1304:1304) (1295:1295:1295)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode244w\[2\]\~0) - (DELAY - (ABSOLUTE - (PORT datab (2038:2038:2038) (2171:2171:2171)) - (PORT datac (1153:1153:1153) (1206:1206:1206)) - (PORT datad (1143:1143:1143) (1202:1202:1202)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1184:1184:1184) (1228:1228:1228)) - (PORT clk (1845:1845:1845) (1873:1873:1873)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3973:3973:3973) (4187:4187:4187)) - (PORT d[1] (1695:1695:1695) (1858:1858:1858)) - (PORT d[2] (3329:3329:3329) (3462:3462:3462)) - (PORT d[3] (2153:2153:2153) (2276:2276:2276)) - (PORT d[4] (2142:2142:2142) (2252:2252:2252)) - (PORT d[5] (1659:1659:1659) (1777:1777:1777)) - (PORT d[6] (1754:1754:1754) (1804:1804:1804)) - (PORT d[7] (3063:3063:3063) (3210:3210:3210)) - (PORT d[8] (3317:3317:3317) (3546:3546:3546)) - (PORT d[9] (1753:1753:1753) (1814:1814:1814)) - (PORT d[10] (3216:3216:3216) (3426:3426:3426)) - (PORT d[11] (2090:2090:2090) (2212:2212:2212)) - (PORT d[12] (1771:1771:1771) (1834:1834:1834)) - (PORT clk (1842:1842:1842) (1869:1869:1869)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2235:2235:2235) (2268:2268:2268)) - (PORT clk (1842:1842:1842) (1869:1869:1869)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1845:1845:1845) (1873:1873:1873)) - (PORT d[0] (2962:2962:2962) (3024:3024:3024)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1846:1846:1846) (1874:1874:1874)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1846:1846:1846) (1874:1874:1874)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1846:1846:1846) (1874:1874:1874)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1846:1846:1846) (1874:1874:1874)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1805:1805:1805) (1832:1832:1832)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (990:990:990) (995:995:995)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (991:991:991) (996:996:996)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (991:991:991) (996:996:996)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (991:991:991) (996:996:996)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~90) - (DELAY - (ABSOLUTE - (PORT dataa (602:602:602) (616:616:616)) - (PORT datab (976:976:976) (1039:1039:1039)) - (PORT datac (828:828:828) (832:832:832)) - (PORT datad (1142:1142:1142) (1222:1222:1222)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode252w\[2\]) - (DELAY - (ABSOLUTE - (PORT dataa (700:700:700) (731:731:731)) - (PORT datab (265:265:265) (319:319:319)) - (PORT datac (371:371:371) (408:408:408)) - (PORT datad (1303:1303:1303) (1299:1299:1299)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode252w\[2\]\~0) - (DELAY - (ABSOLUTE - (PORT datab (2046:2046:2046) (2179:2179:2179)) - (PORT datac (1157:1157:1157) (1209:1209:1209)) - (PORT datad (1148:1148:1148) (1203:1203:1203)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1196:1196:1196) (1209:1209:1209)) - (PORT clk (1854:1854:1854) (1881:1881:1881)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4200:4200:4200) (4456:4456:4456)) - (PORT d[1] (2340:2340:2340) (2537:2537:2537)) - (PORT d[2] (3231:3231:3231) (3326:3326:3326)) - (PORT d[3] (2575:2575:2575) (2761:2761:2761)) - (PORT d[4] (2559:2559:2559) (2766:2766:2766)) - (PORT d[5] (2828:2828:2828) (3008:3008:3008)) - (PORT d[6] (1911:1911:1911) (2053:2053:2053)) - (PORT d[7] (2601:2601:2601) (2739:2739:2739)) - (PORT d[8] (3332:3332:3332) (3618:3618:3618)) - (PORT d[9] (2924:2924:2924) (3075:3075:3075)) - (PORT d[10] (5088:5088:5088) (5359:5359:5359)) - (PORT d[11] (1899:1899:1899) (2034:2034:2034)) - (PORT d[12] (2169:2169:2169) (2292:2292:2292)) - (PORT clk (1851:1851:1851) (1877:1877:1877)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2009:2009:2009) (1965:1965:1965)) - (PORT clk (1851:1851:1851) (1877:1877:1877)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1854:1854:1854) (1881:1881:1881)) - (PORT d[0] (2224:2224:2224) (2198:2198:2198)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1855:1855:1855) (1882:1882:1882)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1855:1855:1855) (1882:1882:1882)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1855:1855:1855) (1882:1882:1882)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1855:1855:1855) (1882:1882:1882)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1814:1814:1814) (1840:1840:1840)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (999:999:999) (1003:1003:1003)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1000:1000:1000) (1004:1004:1004)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1000:1000:1000) (1004:1004:1004)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1000:1000:1000) (1004:1004:1004)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~91) - (DELAY - (ABSOLUTE - (PORT dataa (837:837:837) (859:859:859)) - (PORT datab (1432:1432:1432) (1519:1519:1519)) - (PORT datac (318:318:318) (339:339:339)) - (PORT datad (1100:1100:1100) (1101:1101:1101)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|decode2\|eq_node\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (698:698:698) (723:723:723)) - (PORT datab (257:257:257) (310:310:310)) - (PORT datac (364:364:364) (402:402:402)) - (PORT datad (1304:1304:1304) (1295:1295:1295)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_clkctrl") - (INSTANCE CLOCK_50\~inputclkctrl) - (DELAY - (ABSOLUTE - (PORT inclk[0] (154:154:154) (138:138:138)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vram_address\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1044:1044:1044) (1098:1098:1098)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vram_address\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1253:1253:1253) (1340:1340:1340)) - (PORT datab (987:987:987) (1065:1065:1065)) - (PORT datac (971:971:971) (1042:1042:1042)) - (PORT datad (277:277:277) (361:361:361)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1539:1539:1539) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1216:1216:1216) (1194:1194:1194)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1539:1539:1539) (1551:1551:1551)) - (PORT asdata (1205:1205:1205) (1280:1280:1280)) - (PORT ena (1216:1216:1216) (1194:1194:1194)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vram_address\[2\]\~4) - (DELAY - (ABSOLUTE - (PORT datac (896:896:896) (972:972:972)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1539:1539:1539) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1216:1216:1216) (1194:1194:1194)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add3\~0) - (DELAY - (ABSOLUTE - (PORT datac (891:891:891) (968:968:968)) - (PORT datad (1442:1442:1442) (1493:1493:1493)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1539:1539:1539) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1216:1216:1216) (1194:1194:1194)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add3\~1) - (DELAY - (ABSOLUTE - (PORT dataa (929:929:929) (1008:1008:1008)) - (PORT datac (1383:1383:1383) (1458:1458:1458)) - (PORT datad (1442:1442:1442) (1493:1493:1493)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1539:1539:1539) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1216:1216:1216) (1194:1194:1194)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (697:697:697) (779:779:779)) - (PORT datab (721:721:721) (803:803:803)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH dataa cout (436:436:436) (315:315:315)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datab cout (446:446:446) (318:318:318)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~2) - (DELAY - (ABSOLUTE - (PORT datab (644:644:644) (722:722:722)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datab cout (446:446:446) (318:318:318)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~4) - (DELAY - (ABSOLUTE - (PORT datab (706:706:706) (772:772:772)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datab cout (446:446:446) (318:318:318)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~6) - (DELAY - (ABSOLUTE - (PORT datab (682:682:682) (766:766:766)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datab cout (446:446:446) (318:318:318)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1539:1539:1539) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1216:1216:1216) (1194:1194:1194)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~8) - (DELAY - (ABSOLUTE - (PORT dataa (700:700:700) (788:788:788)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH dataa cout (436:436:436) (315:315:315)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1539:1539:1539) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1216:1216:1216) (1194:1194:1194)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~10) - (DELAY - (ABSOLUTE - (PORT dataa (980:980:980) (1052:1052:1052)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH dataa cout (436:436:436) (315:315:315)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1539:1539:1539) (1551:1551:1551)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1216:1216:1216) (1194:1194:1194)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~12) - (DELAY - (ABSOLUTE - (PORT datab (694:694:694) (766:766:766)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datab cout (446:446:446) (318:318:318)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Selector6\~0) - (DELAY - (ABSOLUTE - (PORT datab (610:610:610) (638:638:638)) - (PORT datac (561:561:561) (582:582:582)) - (PORT datad (957:957:957) (1029:1029:1029)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vram_address\[9\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1254:1254:1254) (1344:1344:1344)) - (PORT datab (987:987:987) (1066:1066:1066)) - (PORT datac (976:976:976) (1049:1049:1049)) - (PORT datad (282:282:282) (366:366:366)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[8\]) - (DELAY - (ABSOLUTE - (PORT clk (1538:1538:1538) (1550:1550:1550)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (820:820:820) (826:826:826)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Add4\~14) - (DELAY - (ABSOLUTE - (PORT datad (708:708:708) (780:780:780)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Selector5\~0) - (DELAY - (ABSOLUTE - (PORT dataa (655:655:655) (677:677:677)) - (PORT datac (792:792:792) (807:807:807)) - (PORT datad (957:957:957) (1033:1033:1033)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[9\]) - (DELAY - (ABSOLUTE - (PORT clk (1538:1538:1538) (1550:1550:1550)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (820:820:820) (826:826:826)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vram_address\[10\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1251:1251:1251) (1338:1338:1338)) - (PORT datab (981:981:981) (1058:1058:1058)) - (PORT datac (980:980:980) (1051:1051:1051)) - (PORT datad (285:285:285) (369:369:369)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|vram_address\[10\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (612:612:612) (644:644:644)) - (PORT datab (1014:1014:1014) (1089:1089:1089)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[10\]) - (DELAY - (ABSOLUTE - (PORT clk (1538:1538:1538) (1550:1550:1550)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Selector3\~0) - (DELAY - (ABSOLUTE - (PORT datab (613:613:613) (639:639:639)) - (PORT datad (958:958:958) (1031:1031:1031)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[11\]) - (DELAY - (ABSOLUTE - (PORT clk (1538:1538:1538) (1550:1550:1550)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (820:820:820) (826:826:826)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|Selector2\~0) - (DELAY - (ABSOLUTE - (PORT datac (618:618:618) (638:638:638)) - (PORT datad (957:957:957) (1029:1029:1029)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|vram_address\[12\]) - (DELAY - (ABSOLUTE - (PORT clk (1538:1538:1538) (1550:1550:1550)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (820:820:820) (826:826:826)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1548:1548:1548) (1620:1620:1620)) - (PORT clk (1864:1864:1864) (1891:1891:1891)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2599:2599:2599) (2697:2697:2697)) - (PORT d[1] (2358:2358:2358) (2589:2589:2589)) - (PORT d[2] (2326:2326:2326) (2476:2476:2476)) - (PORT d[3] (1990:1990:1990) (2063:2063:2063)) - (PORT d[4] (2926:2926:2926) (3182:3182:3182)) - (PORT d[5] (2089:2089:2089) (2294:2294:2294)) - (PORT d[6] (1566:1566:1566) (1667:1667:1667)) - (PORT d[7] (1626:1626:1626) (1711:1711:1711)) - (PORT d[8] (2773:2773:2773) (3020:3020:3020)) - (PORT d[9] (2077:2077:2077) (2186:2186:2186)) - (PORT d[10] (2124:2124:2124) (2247:2247:2247)) - (PORT d[11] (3187:3187:3187) (3328:3328:3328)) - (PORT d[12] (2201:2201:2201) (2298:2298:2298)) - (PORT clk (1861:1861:1861) (1887:1887:1887)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2768:2768:2768) (2740:2740:2740)) - (PORT clk (1861:1861:1861) (1887:1887:1887)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1864:1864:1864) (1891:1891:1891)) - (PORT d[0] (2876:2876:2876) (2827:2827:2827)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1865:1865:1865) (1892:1892:1892)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1865:1865:1865) (1892:1892:1892)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1865:1865:1865) (1892:1892:1892)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1865:1865:1865) (1892:1892:1892)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1819:1819:1819) (1816:1816:1816)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2147:2147:2147) (2193:2193:2193)) - (PORT clk (1829:1829:1829) (1822:1822:1822)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4636:4636:4636) (4688:4688:4688)) - (PORT d[1] (4395:4395:4395) (4383:4383:4383)) - (PORT d[2] (4558:4558:4558) (4624:4624:4624)) - (PORT d[3] (4721:4721:4721) (4720:4720:4720)) - (PORT d[4] (4265:4265:4265) (4262:4262:4262)) - (PORT d[5] (4417:4417:4417) (4355:4355:4355)) - (PORT d[6] (4638:4638:4638) (4708:4708:4708)) - (PORT d[7] (4394:4394:4394) (4343:4343:4343)) - (PORT d[8] (4731:4731:4731) (4705:4705:4705)) - (PORT d[9] (4601:4601:4601) (4791:4791:4791)) - (PORT d[10] (4436:4436:4436) (4445:4445:4445)) - (PORT d[11] (4654:4654:4654) (4682:4682:4682)) - (PORT d[12] (4454:4454:4454) (4466:4466:4466)) - (PORT clk (1825:1825:1825) (1818:1818:1818)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1829:1829:1829) (1822:1822:1822)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1830:1830:1830) (1823:1823:1823)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1830:1830:1830) (1823:1823:1823)) - (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1830:1830:1830) (1823:1823:1823)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1830:1830:1830) (1823:1823:1823)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1821:1821:1821) (1818:1818:1818)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|address_reg_a\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1203:1203:1203) (1298:1298:1298)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|address_reg_a\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1923:1923:1923) (1947:1947:1947)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) - (PORT asdata (1724:1724:1724) (1774:1774:1774)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|decode2\|eq_node\[1\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (697:697:697) (726:726:726)) - (PORT datab (262:262:262) (315:315:315)) - (PORT datac (366:366:366) (405:405:405)) - (PORT datad (1303:1303:1303) (1300:1300:1300)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1513:1513:1513) (1593:1593:1593)) - (PORT clk (1857:1857:1857) (1885:1885:1885)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2905:2905:2905) (3002:3002:3002)) - (PORT d[1] (2381:2381:2381) (2621:2621:2621)) - (PORT d[2] (1221:1221:1221) (1275:1275:1275)) - (PORT d[3] (2017:2017:2017) (2080:2080:2080)) - (PORT d[4] (2910:2910:2910) (3179:3179:3179)) - (PORT d[5] (2405:2405:2405) (2631:2631:2631)) - (PORT d[6] (1533:1533:1533) (1608:1608:1608)) - (PORT d[7] (1282:1282:1282) (1365:1365:1365)) - (PORT d[8] (1697:1697:1697) (1794:1794:1794)) - (PORT d[9] (1564:1564:1564) (1639:1639:1639)) - (PORT d[10] (2164:2164:2164) (2311:2311:2311)) - (PORT d[11] (3205:3205:3205) (3345:3345:3345)) - (PORT d[12] (1922:1922:1922) (2027:2027:2027)) - (PORT clk (1854:1854:1854) (1881:1881:1881)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2709:2709:2709) (2650:2650:2650)) - (PORT clk (1854:1854:1854) (1881:1881:1881)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1885:1885:1885)) - (PORT d[0] (3090:3090:3090) (3120:3120:3120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1886:1886:1886)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1886:1886:1886)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1886:1886:1886)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1886:1886:1886)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1812:1812:1812) (1810:1810:1810)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2167:2167:2167) (2208:2208:2208)) - (PORT clk (1822:1822:1822) (1816:1816:1816)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4624:4624:4624) (4660:4660:4660)) - (PORT d[1] (4162:4162:4162) (4152:4152:4152)) - (PORT d[2] (4263:4263:4263) (4325:4325:4325)) - (PORT d[3] (4486:4486:4486) (4524:4524:4524)) - (PORT d[4] (4333:4333:4333) (4346:4346:4346)) - (PORT d[5] (4356:4356:4356) (4399:4399:4399)) - (PORT d[6] (4459:4459:4459) (4542:4542:4542)) - (PORT d[7] (4161:4161:4161) (4129:4129:4129)) - (PORT d[8] (4409:4409:4409) (4389:4389:4389)) - (PORT d[9] (4581:4581:4581) (4772:4772:4772)) - (PORT d[10] (4418:4418:4418) (4409:4409:4409)) - (PORT d[11] (4535:4535:4535) (4594:4594:4594)) - (PORT d[12] (4450:4450:4450) (4459:4459:4459)) - (PORT clk (1818:1818:1818) (1812:1812:1812)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1822:1822:1822) (1816:1816:1816)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1823:1823:1823) (1817:1817:1817)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1823:1823:1823) (1817:1817:1817)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1823:1823:1823) (1817:1817:1817)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1823:1823:1823) (1817:1817:1817)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2533:2533:2533) (2623:2623:2623)) - (PORT d[1] (2220:2220:2220) (2418:2418:2418)) - (PORT d[2] (2325:2325:2325) (2498:2498:2498)) - (PORT d[3] (2178:2178:2178) (2338:2338:2338)) - (PORT d[4] (2896:2896:2896) (3148:3148:3148)) - (PORT d[5] (2277:2277:2277) (2465:2465:2465)) - (PORT d[6] (1866:1866:1866) (1991:1991:1991)) - (PORT d[7] (2226:2226:2226) (2303:2303:2303)) - (PORT d[8] (2742:2742:2742) (2980:2980:2980)) - (PORT d[9] (1744:1744:1744) (1855:1855:1855)) - (PORT d[10] (1754:1754:1754) (1834:1834:1834)) - (PORT d[11] (3116:3116:3116) (3240:3240:3240)) - (PORT d[12] (1285:1285:1285) (1359:1359:1359)) - (PORT clk (1869:1869:1869) (1894:1894:1894)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1869:1869:1869) (1894:1894:1894)) - (PORT d[0] (2187:2187:2187) (2254:2254:2254)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1870:1870:1870) (1895:1895:1895)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1832:1832:1832) (1857:1857:1857)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1017:1017:1017) (1020:1020:1020)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1018:1018:1018) (1021:1021:1021)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1018:1018:1018) (1021:1021:1021)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1018:1018:1018) (1021:1021:1021)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~87) - (DELAY - (ABSOLUTE - (PORT dataa (1348:1348:1348) (1400:1400:1400)) - (PORT datab (276:276:276) (364:364:364)) - (PORT datac (1381:1381:1381) (1421:1421:1421)) - (PORT datad (1657:1657:1657) (1684:1684:1684)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3643:3643:3643) (3885:3885:3885)) - (PORT d[1] (2602:2602:2602) (2837:2837:2837)) - (PORT d[2] (2449:2449:2449) (2542:2542:2542)) - (PORT d[3] (2141:2141:2141) (2296:2296:2296)) - (PORT d[4] (2227:2227:2227) (2405:2405:2405)) - (PORT d[5] (2065:2065:2065) (2249:2249:2249)) - (PORT d[6] (1926:1926:1926) (2066:2066:2066)) - (PORT d[7] (1993:1993:1993) (2107:2107:2107)) - (PORT d[8] (2992:2992:2992) (3233:3233:3233)) - (PORT d[9] (2617:2617:2617) (2763:2763:2763)) - (PORT d[10] (4742:4742:4742) (4968:4968:4968)) - (PORT d[11] (2083:2083:2083) (2222:2222:2222)) - (PORT d[12] (2446:2446:2446) (2592:2592:2592)) - (PORT clk (1857:1857:1857) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1883:1883:1883)) - (PORT d[0] (3176:3176:3176) (3088:3088:3088)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1820:1820:1820) (1846:1846:1846)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~88) - (DELAY - (ABSOLUTE - (PORT dataa (1285:1285:1285) (1292:1292:1292)) - (PORT datab (1157:1157:1157) (1165:1165:1165)) - (PORT datac (1614:1614:1614) (1636:1636:1636)) - (PORT datad (180:180:180) (209:209:209)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~89) - (DELAY - (ABSOLUTE - (PORT dataa (1434:1434:1434) (1498:1498:1498)) - (PORT datab (207:207:207) (249:249:249)) - (PORT datac (624:624:624) (685:685:685)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~111) - (DELAY - (ABSOLUTE - (PORT dataa (642:642:642) (683:683:683)) - (PORT datab (2010:2010:2010) (2117:2117:2117)) - (PORT datac (918:918:918) (1000:1000:1000)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_io_ibuf") - (INSTANCE raw_loader_in\~input) - (DELAY - (ABSOLUTE - (IOPATH i o (479:479:479) (732:732:732)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~86) - (DELAY - (ABSOLUTE - (PORT dataa (909:909:909) (967:967:967)) - (PORT datac (1544:1544:1544) (1682:1682:1682)) - (PORT datad (1984:1984:1984) (2079:2079:2079)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~100) - (DELAY - (ABSOLUTE - (PORT dataa (952:952:952) (1002:1002:1002)) - (PORT datab (1379:1379:1379) (1383:1383:1383)) - (PORT datac (181:181:181) (218:218:218)) - (PORT datad (181:181:181) (208:208:208)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~101) - (DELAY - (ABSOLUTE - (PORT dataa (947:947:947) (995:995:995)) - (PORT datab (894:894:894) (965:965:965)) - (PORT datac (1645:1645:1645) (1669:1669:1669)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[6\]) - (DELAY - (ABSOLUTE - (PORT dataa (275:275:275) (336:336:336)) - (PORT datab (1389:1389:1389) (1429:1429:1429)) - (PORT datac (938:938:938) (1004:1004:1004)) - (PORT datad (830:830:830) (833:833:833)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_re\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1684:1684:1684) (1826:1826:1826)) - (PORT datab (754:754:754) (857:857:857)) - (PORT datac (961:961:961) (1023:1023:1023)) - (PORT datad (1204:1204:1204) (1263:1263:1263)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_2) - (DELAY - (ABSOLUTE - (PORT dataa (971:971:971) (1041:1041:1041)) - (PORT datab (973:973:973) (1033:1033:1033)) - (PORT datac (961:961:961) (1024:1024:1024)) - (PORT datad (181:181:181) (209:209:209)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1526:1526:1526) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (841:841:841) (846:846:846)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[6\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (1178:1178:1178) (1226:1226:1226)) - (PORT datac (224:224:224) (273:273:273)) - (PORT datad (210:210:210) (243:243:243)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|ir_\|opcode\[6\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (195:195:195) (219:219:219)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_ir_we\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1107:1107:1107) (1191:1191:1191)) - (PORT datab (909:909:909) (972:972:972)) - (PORT datac (661:661:661) (712:712:712)) - (PORT datad (375:375:375) (392:392:392)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1534:1534:1534)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1557:1557:1557)) - (PORT ena (1231:1231:1231) (1217:1217:1217)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal41\~0) - (DELAY - (ABSOLUTE - (PORT datac (1703:1703:1703) (1754:1754:1754)) - (PORT datad (1223:1223:1223) (1322:1322:1322)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal41\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1499:1499:1499) (1573:1573:1573)) - (PORT datab (2298:2298:2298) (2366:2366:2366)) - (PORT datac (2132:2132:2132) (2282:2282:2282)) - (PORT datad (1454:1454:1454) (1538:1538:1538)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal41\~2) - (DELAY - (ABSOLUTE - (PORT dataa (450:450:450) (502:502:502)) - (PORT datab (1649:1649:1649) (1644:1644:1644)) - (PORT datac (170:170:170) (202:202:202)) - (PORT datad (1095:1095:1095) (1127:1127:1127)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_bs_oe) - (DELAY - (ABSOLUTE - (PORT dataa (1962:1962:1962) (2070:2070:2070)) - (PORT datab (1125:1125:1125) (1133:1133:1133)) - (PORT datac (2059:2059:2059) (2181:2181:2181)) - (PORT datad (179:179:179) (207:207:207)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (1180:1180:1180) (1214:1214:1214)) - (PORT datab (292:292:292) (354:354:354)) - (PORT datac (259:259:259) (316:316:316)) - (PORT datad (245:245:245) (290:290:290)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~16) - (DELAY - (ABSOLUTE - (PORT dataa (1130:1130:1130) (1202:1202:1202)) - (PORT datab (1172:1172:1172) (1221:1221:1221)) - (PORT datac (419:419:419) (491:491:491)) - (PORT datad (660:660:660) (723:723:723)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (952:952:952) (1002:1002:1002)) - (PORT datac (1667:1667:1667) (1748:1748:1748)) - (PORT datad (900:900:900) (923:923:923)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~18) - (DELAY - (ABSOLUTE - (PORT datab (201:201:201) (240:240:240)) - (PORT datac (891:891:891) (913:913:913)) - (PORT datad (244:244:244) (286:286:286)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (369:369:369) (390:390:390)) - (PORT datab (631:631:631) (659:659:659)) - (PORT datac (1160:1160:1160) (1204:1204:1204)) - (PORT datad (606:606:606) (623:623:623)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db_high\[1\]\~20) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (999:999:999) (1032:1032:1032)) - (PORT datac (582:582:582) (614:614:614)) - (PORT datad (221:221:221) (263:263:263)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[5\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (1300:1300:1300) (1351:1351:1351)) - (PORT datab (940:940:940) (958:958:958)) - (PORT datac (1822:1822:1822) (1884:1884:1884)) - (PORT datad (931:931:931) (981:981:981)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_\|db\[5\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (647:647:647) (673:673:673)) - (PORT datab (255:255:255) (313:313:313)) - (PORT datac (175:175:175) (209:209:209)) - (PORT datad (945:945:945) (988:988:988)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sw1_\|db_down\[5\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (361:361:361) (501:501:501)) - (PORT datab (1351:1351:1351) (1413:1413:1413)) - (PORT datac (1147:1147:1147) (1181:1181:1181)) - (PORT datad (1196:1196:1196) (1243:1243:1243)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_36) - (DELAY - (ABSOLUTE - (PORT dataa (556:556:556) (578:578:578)) - (PORT datab (623:623:623) (651:651:651)) - (PORT datac (663:663:663) (695:695:695)) - (PORT datad (679:679:679) (697:697:697)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|flags_yf) - (DELAY - (ABSOLUTE - (PORT clk (1514:1514:1514) (1528:1528:1528)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (819:819:819) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[5\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (644:644:644) (702:702:702)) - (PORT datab (900:900:900) (949:949:949)) - (PORT datac (666:666:666) (693:693:693)) - (PORT datad (888:888:888) (905:905:905)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[5\]\~14) - (DELAY - (ABSOLUTE - (PORT dataa (969:969:969) (987:987:987)) - (PORT datab (200:200:200) (240:240:240)) - (PORT datac (948:948:948) (982:982:982)) - (PORT datad (864:864:864) (880:880:880)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[5\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (685:685:685) (717:717:717)) - (PORT datab (1197:1197:1197) (1212:1212:1212)) - (PORT datac (1119:1119:1119) (1150:1150:1150)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~107) - (DELAY - (ABSOLUTE - (PORT dataa (1749:1749:1749) (1858:1858:1858)) - (PORT datab (1231:1231:1231) (1298:1298:1298)) - (PORT datac (1559:1559:1559) (1700:1700:1700)) - (PORT datad (1126:1126:1126) (1171:1171:1171)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1190:1190:1190) (1230:1230:1230)) - (PORT clk (1845:1845:1845) (1873:1873:1873)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3686:3686:3686) (3900:3900:3900)) - (PORT d[1] (1735:1735:1735) (1904:1904:1904)) - (PORT d[2] (3045:3045:3045) (3164:3164:3164)) - (PORT d[3] (1901:1901:1901) (2003:2003:2003)) - (PORT d[4] (2206:2206:2206) (2342:2342:2342)) - (PORT d[5] (2677:2677:2677) (2865:2865:2865)) - (PORT d[6] (2060:2060:2060) (2133:2133:2133)) - (PORT d[7] (2769:2769:2769) (2894:2894:2894)) - (PORT d[8] (3033:3033:3033) (3241:3241:3241)) - (PORT d[9] (2831:2831:2831) (2926:2926:2926)) - (PORT d[10] (3516:3516:3516) (3751:3751:3751)) - (PORT d[11] (1807:1807:1807) (1907:1907:1907)) - (PORT d[12] (2081:2081:2081) (2168:2168:2168)) - (PORT clk (1842:1842:1842) (1869:1869:1869)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1939:1939:1939) (1956:1956:1956)) - (PORT clk (1842:1842:1842) (1869:1869:1869)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1845:1845:1845) (1873:1873:1873)) - (PORT d[0] (2676:2676:2676) (2715:2715:2715)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1846:1846:1846) (1874:1874:1874)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1846:1846:1846) (1874:1874:1874)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1846:1846:1846) (1874:1874:1874)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1846:1846:1846) (1874:1874:1874)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1805:1805:1805) (1832:1832:1832)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (990:990:990) (995:995:995)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (991:991:991) (996:996:996)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (991:991:991) (996:996:996)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (991:991:991) (996:996:996)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1180:1180:1180) (1209:1209:1209)) - (PORT clk (1843:1843:1843) (1871:1871:1871)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3984:3984:3984) (4216:4216:4216)) - (PORT d[1] (1704:1704:1704) (1855:1855:1855)) - (PORT d[2] (3307:3307:3307) (3443:3443:3443)) - (PORT d[3] (1880:1880:1880) (1997:1997:1997)) - (PORT d[4] (1863:1863:1863) (1963:1963:1963)) - (PORT d[5] (1643:1643:1643) (1769:1769:1769)) - (PORT d[6] (1761:1761:1761) (1817:1817:1817)) - (PORT d[7] (3056:3056:3056) (3189:3189:3189)) - (PORT d[8] (3324:3324:3324) (3551:3551:3551)) - (PORT d[9] (2869:2869:2869) (2985:2985:2985)) - (PORT d[10] (3454:3454:3454) (3652:3652:3652)) - (PORT d[11] (1540:1540:1540) (1618:1618:1618)) - (PORT d[12] (1726:1726:1726) (1787:1787:1787)) - (PORT clk (1840:1840:1840) (1867:1867:1867)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1932:1932:1932) (1890:1890:1890)) - (PORT clk (1840:1840:1840) (1867:1867:1867)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1843:1843:1843) (1871:1871:1871)) - (PORT d[0] (2406:2406:2406) (2386:2386:2386)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1872:1872:1872)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1872:1872:1872)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1872:1872:1872)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1872:1872:1872)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1803:1803:1803) (1830:1830:1830)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (988:988:988) (993:993:993)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (989:989:989) (994:994:994)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (989:989:989) (994:994:994)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (989:989:989) (994:994:994)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1218:1218:1218) (1268:1268:1268)) - (PORT clk (1843:1843:1843) (1871:1871:1871)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3686:3686:3686) (3901:3901:3901)) - (PORT d[1] (1692:1692:1692) (1858:1858:1858)) - (PORT d[2] (2977:2977:2977) (3118:3118:3118)) - (PORT d[3] (2124:2124:2124) (2230:2230:2230)) - (PORT d[4] (2237:2237:2237) (2352:2352:2352)) - (PORT d[5] (2684:2684:2684) (2875:2875:2875)) - (PORT d[6] (1801:1801:1801) (1880:1880:1880)) - (PORT d[7] (2772:2772:2772) (2901:2901:2901)) - (PORT d[8] (3346:3346:3346) (3575:3575:3575)) - (PORT d[9] (2889:2889:2889) (3004:3004:3004)) - (PORT d[10] (3484:3484:3484) (3709:3709:3709)) - (PORT d[11] (1816:1816:1816) (1924:1924:1924)) - (PORT d[12] (2023:2023:2023) (2090:2090:2090)) - (PORT clk (1840:1840:1840) (1867:1867:1867)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1889:1889:1889) (1883:1883:1883)) - (PORT clk (1840:1840:1840) (1867:1867:1867)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1843:1843:1843) (1871:1871:1871)) - (PORT d[0] (2482:2482:2482) (2488:2488:2488)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1872:1872:1872)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1872:1872:1872)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1872:1872:1872)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1872:1872:1872)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1803:1803:1803) (1830:1830:1830)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (988:988:988) (993:993:993)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (989:989:989) (994:994:994)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (989:989:989) (994:994:994)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (989:989:989) (994:994:994)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1446:1446:1446) (1499:1499:1499)) - (PORT datab (1431:1431:1431) (1517:1517:1517)) - (PORT datac (1141:1141:1141) (1132:1132:1132)) - (PORT datad (1111:1111:1111) (1136:1136:1136)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1272:1272:1272) (1326:1326:1326)) - (PORT clk (1855:1855:1855) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2887:2887:2887) (3004:3004:3004)) - (PORT d[1] (2662:2662:2662) (2916:2916:2916)) - (PORT d[2] (1218:1218:1218) (1257:1257:1257)) - (PORT d[3] (1701:1701:1701) (1750:1750:1750)) - (PORT d[4] (2885:2885:2885) (3119:3119:3119)) - (PORT d[5] (2382:2382:2382) (2607:2607:2607)) - (PORT d[6] (1263:1263:1263) (1339:1339:1339)) - (PORT d[7] (1323:1323:1323) (1404:1404:1404)) - (PORT d[8] (1739:1739:1739) (1814:1814:1814)) - (PORT d[9] (1262:1262:1262) (1335:1335:1335)) - (PORT d[10] (2409:2409:2409) (2560:2560:2560)) - (PORT d[11] (3166:3166:3166) (3381:3381:3381)) - (PORT d[12] (2205:2205:2205) (2307:2307:2307)) - (PORT clk (1852:1852:1852) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1501:1501:1501) (1496:1496:1496)) - (PORT clk (1852:1852:1852) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1855:1855:1855) (1883:1883:1883)) - (PORT d[0] (2128:2128:2128) (2120:2120:2120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1815:1815:1815) (1842:1842:1842)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1000:1000:1000) (1005:1005:1005)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1001:1001:1001) (1006:1006:1006)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1001:1001:1001) (1006:1006:1006)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1001:1001:1001) (1006:1006:1006)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1130:1130:1130) (1175:1175:1175)) - (PORT datab (1704:1704:1704) (1781:1781:1781)) - (PORT datac (171:171:171) (203:203:203)) - (PORT datad (1426:1426:1426) (1482:1482:1482)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1607:1607:1607) (1720:1720:1720)) - (PORT clk (1852:1852:1852) (1880:1880:1880)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3186:3186:3186) (3300:3300:3300)) - (PORT d[1] (2007:2007:2007) (2188:2188:2188)) - (PORT d[2] (2193:2193:2193) (2290:2290:2290)) - (PORT d[3] (1861:1861:1861) (1989:1989:1989)) - (PORT d[4] (2485:2485:2485) (2606:2606:2606)) - (PORT d[5] (2236:2236:2236) (2402:2402:2402)) - (PORT d[6] (1711:1711:1711) (1755:1755:1755)) - (PORT d[7] (1687:1687:1687) (1776:1776:1776)) - (PORT d[8] (2608:2608:2608) (2791:2791:2791)) - (PORT d[9] (1955:1955:1955) (2077:2077:2077)) - (PORT d[10] (2011:2011:2011) (2111:2111:2111)) - (PORT d[11] (2425:2425:2425) (2555:2555:2555)) - (PORT d[12] (2552:2552:2552) (2625:2625:2625)) - (PORT clk (1849:1849:1849) (1876:1876:1876)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2563:2563:2563) (2536:2536:2536)) - (PORT clk (1849:1849:1849) (1876:1876:1876)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1880:1880:1880)) - (PORT d[0] (3968:3968:3968) (4054:4054:4054)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1881:1881:1881)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1881:1881:1881)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1881:1881:1881)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1881:1881:1881)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1807:1807:1807) (1805:1805:1805)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1738:1738:1738) (1727:1727:1727)) - (PORT clk (1817:1817:1817) (1811:1811:1811)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4391:4391:4391) (4458:4458:4458)) - (PORT d[1] (4215:4215:4215) (4261:4261:4261)) - (PORT d[2] (4322:4322:4322) (4388:4388:4388)) - (PORT d[3] (4683:4683:4683) (4718:4718:4718)) - (PORT d[4] (4355:4355:4355) (4366:4366:4366)) - (PORT d[5] (4618:4618:4618) (4672:4672:4672)) - (PORT d[6] (4745:4745:4745) (4781:4781:4781)) - (PORT d[7] (4330:4330:4330) (4399:4399:4399)) - (PORT d[8] (4420:4420:4420) (4455:4455:4455)) - (PORT d[9] (4477:4477:4477) (4721:4721:4721)) - (PORT d[10] (4604:4604:4604) (4600:4600:4600)) - (PORT d[11] (4406:4406:4406) (4437:4437:4437)) - (PORT d[12] (4503:4503:4503) (4638:4638:4638)) - (PORT clk (1813:1813:1813) (1807:1807:1807)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1817:1817:1817) (1811:1811:1811)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1818:1818:1818) (1812:1812:1812)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1818:1818:1818) (1812:1812:1812)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1818:1818:1818) (1812:1812:1812)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1818:1818:1818) (1812:1812:1812)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2857:2857:2857) (2972:2972:2972)) - (PORT d[1] (1730:1730:1730) (1897:1897:1897)) - (PORT d[2] (1950:1950:1950) (2070:2070:2070)) - (PORT d[3] (1897:1897:1897) (2023:2023:2023)) - (PORT d[4] (2739:2739:2739) (2895:2895:2895)) - (PORT d[5] (2232:2232:2232) (2412:2412:2412)) - (PORT d[6] (1964:1964:1964) (2031:2031:2031)) - (PORT d[7] (2136:2136:2136) (2268:2268:2268)) - (PORT d[8] (2383:2383:2383) (2561:2561:2561)) - (PORT d[9] (1973:1973:1973) (2079:2079:2079)) - (PORT d[10] (1681:1681:1681) (1740:1740:1740)) - (PORT d[11] (2036:2036:2036) (2101:2101:2101)) - (PORT d[12] (2509:2509:2509) (2578:2578:2578)) - (PORT clk (1857:1857:1857) (1882:1882:1882)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1882:1882:1882)) - (PORT d[0] (2716:2716:2716) (2794:2794:2794)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1883:1883:1883)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1820:1820:1820) (1845:1845:1845)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1008:1008:1008)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1009:1009:1009)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1009:1009:1009)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1009:1009:1009)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3922:3922:3922) (4160:4160:4160)) - (PORT d[1] (2875:2875:2875) (3108:3108:3108)) - (PORT d[2] (2719:2719:2719) (2815:2815:2815)) - (PORT d[3] (2274:2274:2274) (2436:2436:2436)) - (PORT d[4] (2511:2511:2511) (2691:2691:2691)) - (PORT d[5] (2520:2520:2520) (2696:2696:2696)) - (PORT d[6] (1898:1898:1898) (2018:2018:2018)) - (PORT d[7] (2284:2284:2284) (2398:2398:2398)) - (PORT d[8] (3090:3090:3090) (3363:3363:3363)) - (PORT d[9] (2691:2691:2691) (2835:2835:2835)) - (PORT d[10] (4531:4531:4531) (4774:4774:4774)) - (PORT d[11] (1925:1925:1925) (2083:2083:2083)) - (PORT d[12] (2422:2422:2422) (2553:2553:2553)) - (PORT clk (1857:1857:1857) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1883:1883:1883)) - (PORT d[0] (3644:3644:3644) (3567:3567:3567)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1820:1820:1820) (1846:1846:1846)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1502:1502:1502) (1566:1566:1566)) - (PORT clk (1869:1869:1869) (1895:1895:1895)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2818:2818:2818) (2896:2896:2896)) - (PORT d[1] (2077:2077:2077) (2294:2294:2294)) - (PORT d[2] (2223:2223:2223) (2370:2370:2370)) - (PORT d[3] (2274:2274:2274) (2375:2375:2375)) - (PORT d[4] (2928:2928:2928) (3204:3204:3204)) - (PORT d[5] (2379:2379:2379) (2550:2550:2550)) - (PORT d[6] (1572:1572:1572) (1678:1678:1678)) - (PORT d[7] (1564:1564:1564) (1666:1666:1666)) - (PORT d[8] (2761:2761:2761) (2991:2991:2991)) - (PORT d[9] (2092:2092:2092) (2225:2225:2225)) - (PORT d[10] (1872:1872:1872) (1997:1997:1997)) - (PORT d[11] (2890:2890:2890) (3011:3011:3011)) - (PORT d[12] (1605:1605:1605) (1686:1686:1686)) - (PORT clk (1866:1866:1866) (1891:1891:1891)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2511:2511:2511) (2509:2509:2509)) - (PORT clk (1866:1866:1866) (1891:1891:1891)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1869:1869:1869) (1895:1895:1895)) - (PORT d[0] (2908:2908:2908) (2850:2850:2850)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1870:1870:1870) (1896:1896:1896)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1870:1870:1870) (1896:1896:1896)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1870:1870:1870) (1896:1896:1896)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1870:1870:1870) (1896:1896:1896)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1824:1824:1824) (1820:1820:1820)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2487:2487:2487) (2567:2567:2567)) - (PORT clk (1834:1834:1834) (1826:1826:1826)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4515:4515:4515) (4502:4502:4502)) - (PORT d[1] (4098:4098:4098) (4096:4096:4096)) - (PORT d[2] (4387:4387:4387) (4416:4416:4416)) - (PORT d[3] (4466:4466:4466) (4494:4494:4494)) - (PORT d[4] (4550:4550:4550) (4547:4547:4547)) - (PORT d[5] (4395:4395:4395) (4433:4433:4433)) - (PORT d[6] (4601:4601:4601) (4650:4650:4650)) - (PORT d[7] (4160:4160:4160) (4143:4143:4143)) - (PORT d[8] (4661:4661:4661) (4689:4689:4689)) - (PORT d[9] (4502:4502:4502) (4695:4695:4695)) - (PORT d[10] (4622:4622:4622) (4632:4632:4632)) - (PORT d[11] (4398:4398:4398) (4428:4428:4428)) - (PORT d[12] (4464:4464:4464) (4487:4487:4487)) - (PORT clk (1830:1830:1830) (1822:1822:1822)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1834:1834:1834) (1826:1826:1826)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1835:1835:1835) (1827:1827:1827)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1835:1835:1835) (1827:1827:1827)) - (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1835:1835:1835) (1827:1827:1827)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1835:1835:1835) (1827:1827:1827)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1822:1822:1822)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Mux2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1428:1428:1428) (1500:1500:1500)) - (PORT datab (969:969:969) (1047:1047:1047)) - (PORT datac (1170:1170:1170) (1197:1197:1197)) - (PORT datad (1685:1685:1685) (1714:1714:1714)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Mux2\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1516:1516:1516) (1602:1602:1602)) - (PORT datab (970:970:970) (1048:1048:1048)) - (PORT datac (1706:1706:1706) (1767:1767:1767)) - (PORT datad (171:171:171) (196:196:196)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[5\]\~110) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (246:246:246)) - (PORT datab (1206:1206:1206) (1299:1299:1299)) - (PORT datac (1658:1658:1658) (1693:1693:1693)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[5\]\~85) - (DELAY - (ABSOLUTE - (PORT dataa (1382:1382:1382) (1395:1395:1395)) - (PORT datab (1382:1382:1382) (1409:1409:1409)) - (PORT datac (842:842:842) (919:919:919)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[5\]\~99) - (DELAY - (ABSOLUTE - (PORT dataa (809:809:809) (832:832:832)) - (PORT datad (194:194:194) (219:219:219)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[5\]) - (DELAY - (ABSOLUTE - (PORT dataa (972:972:972) (1043:1043:1043)) - (PORT datab (1039:1039:1039) (1071:1071:1071)) - (PORT datac (240:240:240) (293:293:293)) - (PORT datad (948:948:948) (984:984:984)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1526:1526:1526) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (841:841:841) (846:846:846)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[5\]\~14) - (DELAY - (ABSOLUTE - (PORT datab (707:707:707) (729:729:729)) - (PORT datac (235:235:235) (309:309:309)) - (PORT datad (359:359:359) (384:384:384)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[5\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (980:980:980) (1004:1004:1004)) - (PORT datab (917:917:917) (967:967:967)) - (PORT datac (825:825:825) (825:825:825)) - (PORT datad (891:891:891) (919:919:919)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1541:1541:1541)) - (PORT asdata (598:598:598) (653:653:653)) - (PORT clrn (1571:1571:1571) (1550:1550:1550)) - (PORT ena (1479:1479:1479) (1488:1488:1488)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|SYNTHESIZED_WIRE_0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1209:1209:1209) (1333:1333:1333)) - (PORT datab (857:857:857) (877:877:877)) - (PORT datac (862:862:862) (884:884:884)) - (PORT datad (1897:1897:1897) (1952:1952:1952)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|DFFE_inst4) - (DELAY - (ABSOLUTE - (PORT clk (1527:1527:1527) (1547:1547:1547)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1586:1586:1586) (1563:1563:1563)) - (PORT ena (820:820:820) (825:825:825)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|use_ixiy) - (DELAY - (ABSOLUTE - (PORT dataa (974:974:974) (1072:1072:1072)) - (PORT datac (930:930:930) (1012:1012:1012)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~23) - (DELAY - (ABSOLUTE - (PORT dataa (1192:1192:1192) (1230:1230:1230)) - (PORT datab (998:998:998) (1107:1107:1107)) - (PORT datac (657:657:657) (721:721:721)) - (PORT datad (1243:1243:1243) (1329:1329:1329)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~34) - (DELAY - (ABSOLUTE - (PORT dataa (888:888:888) (915:915:915)) - (PORT datab (667:667:667) (679:679:679)) - (PORT datac (904:904:904) (934:934:934)) - (PORT datad (360:360:360) (382:382:382)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~31) - (DELAY - (ABSOLUTE - (PORT dataa (1168:1168:1168) (1211:1211:1211)) - (PORT datab (1607:1607:1607) (1625:1625:1625)) - (PORT datac (614:614:614) (646:646:646)) - (PORT datad (1081:1081:1081) (1126:1126:1126)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~29) - (DELAY - (ABSOLUTE - (PORT dataa (1255:1255:1255) (1363:1363:1363)) - (PORT datab (469:469:469) (523:523:523)) - (PORT datac (1707:1707:1707) (1763:1763:1763)) - (PORT datad (264:264:264) (317:317:317)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~30) - (DELAY - (ABSOLUTE - (PORT dataa (390:390:390) (441:441:441)) - (PORT datab (198:198:198) (238:238:238)) - (PORT datac (1072:1072:1072) (1108:1108:1108)) - (PORT datad (202:202:202) (231:231:231)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~28) - (DELAY - (ABSOLUTE - (PORT dataa (1172:1172:1172) (1212:1212:1212)) - (PORT datab (568:568:568) (599:599:599)) - (PORT datac (1103:1103:1103) (1115:1115:1115)) - (PORT datad (317:317:317) (336:336:336)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~32) - (DELAY - (ABSOLUTE - (PORT dataa (851:851:851) (898:898:898)) - (PORT datab (198:198:198) (236:236:236)) - (PORT datac (590:590:590) (597:597:597)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_inc_oe\~42) - (DELAY - (ABSOLUTE - (PORT dataa (230:230:230) (275:275:275)) - (PORT datab (645:645:645) (670:670:670)) - (PORT datac (194:194:194) (238:238:238)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~14) - (DELAY - (ABSOLUTE - (PORT dataa (887:887:887) (914:914:914)) - (PORT datab (1115:1115:1115) (1147:1147:1147)) - (PORT datac (1402:1402:1402) (1464:1464:1464)) - (PORT datad (899:899:899) (942:942:942)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~10) - (DELAY - (ABSOLUTE - (PORT dataa (885:885:885) (895:895:895)) - (PORT datab (939:939:939) (994:994:994)) - (PORT datac (959:959:959) (1031:1031:1031)) - (PORT datad (1113:1113:1113) (1143:1143:1143)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~9) - (DELAY - (ABSOLUTE - (PORT dataa (889:889:889) (916:916:916)) - (PORT datab (876:876:876) (896:896:896)) - (PORT datac (1106:1106:1106) (1134:1134:1134)) - (PORT datad (326:326:326) (350:350:350)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1572:1572:1572) (1664:1664:1664)) - (PORT datab (205:205:205) (245:245:245)) - (PORT datac (1885:1885:1885) (1936:1936:1936)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~12) - (DELAY - (ABSOLUTE - (PORT dataa (1126:1126:1126) (1249:1249:1249)) - (PORT datab (997:997:997) (1061:1061:1061)) - (PORT datac (1628:1628:1628) (1678:1678:1678)) - (PORT datad (1161:1161:1161) (1198:1198:1198)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1424:1424:1424) (1425:1425:1425)) - (PORT datab (1116:1116:1116) (1146:1146:1146)) - (PORT datac (1040:1040:1040) (1082:1082:1082)) - (PORT datad (337:337:337) (357:357:357)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~15) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (172:172:172) (206:206:206)) - (PORT datad (594:594:594) (614:614:614)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~20) - (DELAY - (ABSOLUTE - (PORT dataa (631:631:631) (644:644:644)) - (PORT datab (1041:1041:1041) (1082:1082:1082)) - (PORT datac (571:571:571) (588:588:588)) - (PORT datad (598:598:598) (647:647:647)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|pc_inc_hold\~48) - (DELAY - (ABSOLUTE - (PORT dataa (886:886:886) (933:933:933)) - (PORT datab (1205:1205:1205) (1227:1227:1227)) - (PORT datac (1512:1512:1512) (1585:1585:1585)) - (PORT datad (674:674:674) (712:712:712)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~22) - (DELAY - (ABSOLUTE - (PORT dataa (1353:1353:1353) (1383:1383:1383)) - (PORT datab (852:852:852) (880:880:880)) - (PORT datac (1075:1075:1075) (1109:1109:1109)) - (PORT datad (195:195:195) (220:220:220)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~21) - (DELAY - (ABSOLUTE - (PORT dataa (870:870:870) (942:942:942)) - (PORT datab (941:941:941) (1018:1018:1018)) - (PORT datac (1551:1551:1551) (1591:1591:1591)) - (PORT datad (1215:1215:1215) (1217:1217:1217)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~23) - (DELAY - (ABSOLUTE - (PORT dataa (867:867:867) (909:909:909)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (806:806:806) (819:819:819)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~26) - (DELAY - (ABSOLUTE - (PORT dataa (2068:2068:2068) (2159:2159:2159)) - (PORT datab (1202:1202:1202) (1215:1215:1215)) - (PORT datac (1137:1137:1137) (1179:1179:1179)) - (PORT datad (1150:1150:1150) (1187:1187:1187)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~25) - (DELAY - (ABSOLUTE - (PORT dataa (2504:2504:2504) (2616:2616:2616)) - (PORT datab (576:576:576) (586:586:586)) - (PORT datac (193:193:193) (227:227:227)) - (PORT datad (981:981:981) (1012:1012:1012)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~27) - (DELAY - (ABSOLUTE - (PORT dataa (1663:1663:1663) (1697:1697:1697)) - (PORT datab (833:833:833) (893:893:893)) - (PORT datac (1036:1036:1036) (1091:1091:1091)) - (PORT datad (770:770:770) (816:816:816)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~33) - (DELAY - (ABSOLUTE - (PORT dataa (1031:1031:1031) (1043:1043:1043)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (819:819:819) (869:869:869)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fMRead\~35) - (DELAY - (ABSOLUTE - (PORT dataa (865:865:865) (888:888:888)) - (PORT datab (198:198:198) (236:236:236)) - (PORT datac (821:821:821) (872:872:872)) - (PORT datad (195:195:195) (219:219:219)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pin_control_\|bus_db_pin_re) - (DELAY - (ABSOLUTE - (PORT datab (974:974:974) (1035:1035:1035)) - (PORT datac (964:964:964) (1026:1026:1026)) - (PORT datad (182:182:182) (211:211:211)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1008:1008:1008) (1080:1080:1080)) - (PORT clk (1860:1860:1860) (1887:1887:1887)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1191:1191:1191) (1224:1224:1224)) - (PORT d[1] (2415:2415:2415) (2649:2649:2649)) - (PORT d[2] (1758:1758:1758) (1803:1803:1803)) - (PORT d[3] (1013:1013:1013) (1063:1063:1063)) - (PORT d[4] (2608:2608:2608) (2826:2826:2826)) - (PORT d[5] (3496:3496:3496) (3699:3699:3699)) - (PORT d[6] (1026:1026:1026) (1099:1099:1099)) - (PORT d[7] (3197:3197:3197) (3375:3375:3375)) - (PORT d[8] (1246:1246:1246) (1270:1270:1270)) - (PORT d[9] (1026:1026:1026) (1088:1088:1088)) - (PORT d[10] (1315:1315:1315) (1388:1388:1388)) - (PORT d[11] (2503:2503:2503) (2659:2659:2659)) - (PORT d[12] (1307:1307:1307) (1387:1387:1387)) - (PORT clk (1857:1857:1857) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (944:944:944) (900:900:900)) - (PORT clk (1857:1857:1857) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (PORT d[0] (1721:1721:1721) (1677:1677:1677)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1820:1820:1820) (1846:1846:1846)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (708:708:708) (754:754:754)) - (PORT clk (1860:1860:1860) (1888:1888:1888)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (966:966:966) (1010:1010:1010)) - (PORT d[1] (2966:2966:2966) (3237:3237:3237)) - (PORT d[2] (1238:1238:1238) (1256:1256:1256)) - (PORT d[3] (1302:1302:1302) (1383:1383:1383)) - (PORT d[4] (2581:2581:2581) (2796:2796:2796)) - (PORT d[5] (2980:2980:2980) (3208:3208:3208)) - (PORT d[6] (692:692:692) (727:727:727)) - (PORT d[7] (705:705:705) (744:744:744)) - (PORT d[8] (1011:1011:1011) (1032:1032:1032)) - (PORT d[9] (717:717:717) (757:757:757)) - (PORT d[10] (1036:1036:1036) (1102:1102:1102)) - (PORT d[11] (2544:2544:2544) (2757:2757:2757)) - (PORT d[12] (1267:1267:1267) (1319:1319:1319)) - (PORT clk (1857:1857:1857) (1884:1884:1884)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (967:967:967) (945:945:945)) - (PORT clk (1857:1857:1857) (1884:1884:1884)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1888:1888:1888)) - (PORT d[0] (2089:2089:2089) (2073:2073:2073)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1889:1889:1889)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1889:1889:1889)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1889:1889:1889)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1889:1889:1889)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1820:1820:1820) (1847:1847:1847)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1010:1010:1010)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1011:1011:1011)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1011:1011:1011)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1011:1011:1011)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[1\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (682:682:682) (752:752:752)) - (PORT datab (688:688:688) (754:754:754)) - (PORT datac (786:786:786) (795:795:795)) - (PORT datad (864:864:864) (896:896:896)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (700:700:700) (744:744:744)) - (PORT clk (1860:1860:1860) (1887:1887:1887)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3167:3167:3167) (3303:3303:3303)) - (PORT d[1] (2937:2937:2937) (3208:3208:3208)) - (PORT d[2] (967:967:967) (987:987:987)) - (PORT d[3] (1341:1341:1341) (1401:1401:1401)) - (PORT d[4] (2612:2612:2612) (2843:2843:2843)) - (PORT d[5] (2651:2651:2651) (2894:2894:2894)) - (PORT d[6] (960:960:960) (1001:1001:1001)) - (PORT d[7] (1270:1270:1270) (1343:1343:1343)) - (PORT d[8] (1442:1442:1442) (1513:1513:1513)) - (PORT d[9] (971:971:971) (1019:1019:1019)) - (PORT d[10] (1031:1031:1031) (1057:1057:1057)) - (PORT d[11] (2872:2872:2872) (3095:3095:3095)) - (PORT d[12] (969:969:969) (1020:1020:1020)) - (PORT clk (1857:1857:1857) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1245:1245:1245) (1221:1221:1221)) - (PORT clk (1857:1857:1857) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (PORT d[0] (2049:2049:2049) (2003:2003:2003)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1820:1820:1820) (1846:1846:1846)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (743:743:743) (772:772:772)) - (PORT clk (1859:1859:1859) (1886:1886:1886)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3188:3188:3188) (3327:3327:3327)) - (PORT d[1] (2678:2678:2678) (2951:2951:2951)) - (PORT d[2] (1298:1298:1298) (1309:1309:1309)) - (PORT d[3] (1348:1348:1348) (1402:1402:1402)) - (PORT d[4] (2616:2616:2616) (2850:2850:2850)) - (PORT d[5] (2675:2675:2675) (2903:2903:2903)) - (PORT d[6] (1230:1230:1230) (1289:1289:1289)) - (PORT d[7] (1132:1132:1132) (1148:1148:1148)) - (PORT d[8] (1470:1470:1470) (1552:1552:1552)) - (PORT d[9] (1550:1550:1550) (1617:1617:1617)) - (PORT d[10] (724:724:724) (767:767:767)) - (PORT d[11] (2854:2854:2854) (3086:3086:3086)) - (PORT d[12] (971:971:971) (1034:1034:1034)) - (PORT clk (1856:1856:1856) (1882:1882:1882)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1229:1229:1229) (1208:1208:1208)) - (PORT clk (1856:1856:1856) (1882:1882:1882)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1859:1859:1859) (1886:1886:1886)) - (PORT d[0] (1822:1822:1822) (1811:1811:1811)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1819:1819:1819) (1845:1845:1845)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1004:1004:1004) (1008:1008:1008)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[1\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1242:1242:1242) (1299:1299:1299)) - (PORT datab (198:198:198) (238:238:238)) - (PORT datac (968:968:968) (1003:1003:1003)) - (PORT datad (1089:1089:1089) (1119:1119:1119)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (746:746:746) (776:776:776)) - (PORT clk (1853:1853:1853) (1881:1881:1881)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2906:2906:2906) (3003:3003:3003)) - (PORT d[1] (2374:2374:2374) (2624:2624:2624)) - (PORT d[2] (1590:1590:1590) (1604:1604:1604)) - (PORT d[3] (1983:1983:1983) (2059:2059:2059)) - (PORT d[4] (2920:2920:2920) (3176:3176:3176)) - (PORT d[5] (2692:2692:2692) (2903:2903:2903)) - (PORT d[6] (1267:1267:1267) (1350:1350:1350)) - (PORT d[7] (1307:1307:1307) (1395:1395:1395)) - (PORT d[8] (1742:1742:1742) (1842:1842:1842)) - (PORT d[9] (1557:1557:1557) (1621:1621:1621)) - (PORT d[10] (2161:2161:2161) (2306:2306:2306)) - (PORT d[11] (3233:3233:3233) (3375:3375:3375)) - (PORT d[12] (1281:1281:1281) (1357:1357:1357)) - (PORT clk (1850:1850:1850) (1877:1877:1877)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2941:2941:2941) (2895:2895:2895)) - (PORT clk (1850:1850:1850) (1877:1877:1877)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1881:1881:1881)) - (PORT d[0] (3092:3092:3092) (3136:3136:3136)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1854:1854:1854) (1882:1882:1882)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1854:1854:1854) (1882:1882:1882)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1854:1854:1854) (1882:1882:1882)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1854:1854:1854) (1882:1882:1882)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1808:1808:1808) (1806:1806:1806)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2118:2118:2118) (2165:2165:2165)) - (PORT clk (1818:1818:1818) (1812:1812:1812)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4374:4374:4374) (4418:4418:4418)) - (PORT d[1] (4140:4140:4140) (4128:4128:4128)) - (PORT d[2] (4277:4277:4277) (4327:4327:4327)) - (PORT d[3] (4389:4389:4389) (4374:4374:4374)) - (PORT d[4] (4369:4369:4369) (4385:4385:4385)) - (PORT d[5] (4402:4402:4402) (4357:4357:4357)) - (PORT d[6] (4635:4635:4635) (4717:4717:4717)) - (PORT d[7] (4444:4444:4444) (4393:4393:4393)) - (PORT d[8] (4445:4445:4445) (4433:4433:4433)) - (PORT d[9] (4508:4508:4508) (4699:4699:4699)) - (PORT d[10] (4409:4409:4409) (4440:4440:4440)) - (PORT d[11] (4509:4509:4509) (4563:4563:4563)) - (PORT d[12] (4429:4429:4429) (4547:4547:4547)) - (PORT clk (1814:1814:1814) (1808:1808:1808)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1818:1818:1818) (1812:1812:1812)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1819:1819:1819) (1813:1813:1813)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1819:1819:1819) (1813:1813:1813)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1819:1819:1819) (1813:1813:1813)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1819:1819:1819) (1813:1813:1813)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2570:2570:2570) (2648:2648:2648)) - (PORT d[1] (2033:2033:2033) (2232:2232:2232)) - (PORT d[2] (2324:2324:2324) (2498:2498:2498)) - (PORT d[3] (2521:2521:2521) (2687:2687:2687)) - (PORT d[4] (2940:2940:2940) (3191:3191:3191)) - (PORT d[5] (2266:2266:2266) (2447:2447:2447)) - (PORT d[6] (1866:1866:1866) (1990:1990:1990)) - (PORT d[7] (2543:2543:2543) (2628:2628:2628)) - (PORT d[8] (2767:2767:2767) (2988:2988:2988)) - (PORT d[9] (1759:1759:1759) (1863:1863:1863)) - (PORT d[10] (1515:1515:1515) (1609:1609:1609)) - (PORT d[11] (3453:3453:3453) (3586:3586:3586)) - (PORT d[12] (1542:1542:1542) (1649:1649:1649)) - (PORT clk (1868:1868:1868) (1894:1894:1894)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1868:1868:1868) (1894:1894:1894)) - (PORT d[0] (2191:2191:2191) (2247:2247:2247)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1869:1869:1869) (1895:1895:1895)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1831:1831:1831) (1857:1857:1857)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1016:1016:1016) (1020:1020:1020)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1017:1017:1017) (1021:1021:1021)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1017:1017:1017) (1021:1021:1021)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1017:1017:1017) (1021:1021:1021)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1511:1511:1511) (1554:1554:1554)) - (PORT d[1] (2684:2684:2684) (2948:2948:2948)) - (PORT d[2] (989:989:989) (1036:1036:1036)) - (PORT d[3] (1684:1684:1684) (1752:1752:1752)) - (PORT d[4] (2594:2594:2594) (2826:2826:2826)) - (PORT d[5] (2711:2711:2711) (2920:2920:2920)) - (PORT d[6] (973:973:973) (1031:1031:1031)) - (PORT d[7] (964:964:964) (1018:1018:1018)) - (PORT d[8] (1426:1426:1426) (1505:1505:1505)) - (PORT d[9] (1567:1567:1567) (1660:1660:1660)) - (PORT d[10] (2478:2478:2478) (2623:2623:2623)) - (PORT d[11] (2885:2885:2885) (3126:3126:3126)) - (PORT d[12] (1271:1271:1271) (1324:1324:1324)) - (PORT clk (1855:1855:1855) (1882:1882:1882)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1855:1855:1855) (1882:1882:1882)) - (PORT d[0] (872:872:872) (859:859:859)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1883:1883:1883)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1818:1818:1818) (1845:1845:1845)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1003:1003:1003) (1008:1008:1008)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1004:1004:1004) (1009:1009:1009)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1004:1004:1004) (1009:1009:1009)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1004:1004:1004) (1009:1009:1009)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (926:926:926) (931:931:931)) - (PORT clk (1857:1857:1857) (1884:1884:1884)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3174:3174:3174) (3295:3295:3295)) - (PORT d[1] (2670:2670:2670) (2938:2938:2938)) - (PORT d[2] (1591:1591:1591) (1604:1604:1604)) - (PORT d[3] (1700:1700:1700) (1749:1749:1749)) - (PORT d[4] (2908:2908:2908) (3176:3176:3176)) - (PORT d[5] (2711:2711:2711) (2920:2920:2920)) - (PORT d[6] (974:974:974) (1032:1032:1032)) - (PORT d[7] (1544:1544:1544) (1607:1607:1607)) - (PORT d[8] (3051:3051:3051) (3314:3314:3314)) - (PORT d[9] (996:996:996) (1062:1062:1062)) - (PORT d[10] (2482:2482:2482) (2620:2620:2620)) - (PORT d[11] (2859:2859:2859) (3096:3096:3096)) - (PORT d[12] (2233:2233:2233) (2338:2338:2338)) - (PORT clk (1854:1854:1854) (1880:1880:1880)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3083:3083:3083) (3081:3081:3081)) - (PORT clk (1854:1854:1854) (1880:1880:1880)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1884:1884:1884)) - (PORT d[0] (1803:1803:1803) (1787:1787:1787)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1885:1885:1885)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1885:1885:1885)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1885:1885:1885)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1885:1885:1885)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1812:1812:1812) (1809:1809:1809)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2405:2405:2405) (2433:2433:2433)) - (PORT clk (1822:1822:1822) (1815:1815:1815)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4622:4622:4622) (4649:4649:4649)) - (PORT d[1] (4242:4242:4242) (4320:4320:4320)) - (PORT d[2] (4251:4251:4251) (4295:4295:4295)) - (PORT d[3] (4399:4399:4399) (4422:4422:4422)) - (PORT d[4] (4340:4340:4340) (4354:4354:4354)) - (PORT d[5] (4534:4534:4534) (4546:4546:4546)) - (PORT d[6] (4731:4731:4731) (4801:4801:4801)) - (PORT d[7] (4488:4488:4488) (4531:4531:4531)) - (PORT d[8] (4436:4436:4436) (4436:4436:4436)) - (PORT d[9] (4525:4525:4525) (4711:4711:4711)) - (PORT d[10] (4473:4473:4473) (4495:4495:4495)) - (PORT d[11] (4414:4414:4414) (4386:4386:4386)) - (PORT d[12] (4391:4391:4391) (4381:4381:4381)) - (PORT clk (1818:1818:1818) (1811:1811:1811)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1822:1822:1822) (1815:1815:1815)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1823:1823:1823) (1816:1816:1816)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1823:1823:1823) (1816:1816:1816)) - (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1823:1823:1823) (1816:1816:1816)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1823:1823:1823) (1816:1816:1816)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1814:1814:1814) (1811:1811:1811)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Selector1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (668:668:668) (731:731:731)) - (PORT datab (1192:1192:1192) (1240:1240:1240)) - (PORT datac (825:825:825) (833:833:833)) - (PORT datad (890:890:890) (911:911:911)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Selector1\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1189:1189:1189) (1198:1198:1198)) - (PORT datab (1192:1192:1192) (1240:1240:1240)) - (PORT datac (1509:1509:1509) (1586:1586:1586)) - (PORT datad (171:171:171) (196:196:196)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~103) - (DELAY - (ABSOLUTE - (PORT dataa (1738:1738:1738) (1846:1846:1846)) - (PORT datab (1412:1412:1412) (1506:1506:1506)) - (PORT datac (648:648:648) (701:701:701)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (336:336:336) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_io_ibuf") (INSTANCE PS2_DAT\~input) @@ -36080,24 +28878,45 @@ ) ) (CELL - (CELLTYPE "cycloneive_clkctrl") - (INSTANCE reset\~clkctrl) + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE KEY\[0\]\~input) (DELAY (ABSOLUTE - (PORT inclk[0] (842:842:842) (859:859:859)) + (IOPATH i o (481:481:481) (733:733:733)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\~0) + (INSTANCE reset) (DELAY (ABSOLUTE - (PORT dataa (282:282:282) (386:386:386)) - (PORT datab (291:291:291) (382:382:382)) - (PORT datad (245:245:245) (325:325:325)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT datac (1601:1601:1601) (1525:1525:1525)) + (PORT datad (820:820:820) (846:846:846)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE reset\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (573:573:573) (569:569:569)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\~3) + (DELAY + (ABSOLUTE + (PORT dataa (273:273:273) (374:374:374)) + (PORT datab (282:282:282) (378:378:378)) + (PORT datad (249:249:249) (330:330:330)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -36117,7 +28936,7 @@ (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[7\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (3358:3358:3358) (3700:3700:3700)) + (PORT datad (3184:3184:3184) (3436:3436:3436)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -36127,9 +28946,9 @@ (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[7\]) (DELAY (ABSOLUTE - (PORT clk (1512:1512:1512) (1525:1525:1525)) + (PORT clk (1509:1509:1509) (1522:1522:1522)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1566:1566:1566) (1561:1561:1561)) + (PORT clrn (1550:1550:1550) (1543:1543:1543)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -36143,7 +28962,7 @@ (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[6\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (225:225:225) (297:297:297)) + (PORT datad (226:226:226) (300:300:300)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -36153,9 +28972,9 @@ (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[6\]) (DELAY (ABSOLUTE - (PORT clk (1512:1512:1512) (1525:1525:1525)) + (PORT clk (1509:1509:1509) (1522:1522:1522)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1566:1566:1566) (1561:1561:1561)) + (PORT clrn (1550:1550:1550) (1543:1543:1543)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -36169,7 +28988,7 @@ (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[5\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (227:227:227) (302:302:302)) + (PORT datad (240:240:240) (310:310:310)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -36179,9 +28998,9 @@ (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[5\]) (DELAY (ABSOLUTE - (PORT clk (1512:1512:1512) (1525:1525:1525)) + (PORT clk (1509:1509:1509) (1522:1522:1522)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1566:1566:1566) (1561:1561:1561)) + (PORT clrn (1550:1550:1550) (1543:1543:1543)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -36195,7 +29014,7 @@ (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[4\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (239:239:239) (309:309:309)) + (PORT datad (224:224:224) (296:296:296)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -36205,9 +29024,9 @@ (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[4\]) (DELAY (ABSOLUTE - (PORT clk (1512:1512:1512) (1525:1525:1525)) + (PORT clk (1509:1509:1509) (1522:1522:1522)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1566:1566:1566) (1561:1561:1561)) + (PORT clrn (1550:1550:1550) (1543:1543:1543)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -36216,28 +29035,12 @@ (HOLD d (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|Equal0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (252:252:252) (342:342:342)) - (PORT datab (250:250:250) (335:335:335)) - (PORT datac (380:380:380) (441:441:441)) - (PORT datad (225:225:225) (298:298:298)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[3\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (227:227:227) (299:299:299)) + (PORT datad (226:226:226) (300:300:300)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -36247,9 +29050,9 @@ (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[3\]) (DELAY (ABSOLUTE - (PORT clk (1512:1512:1512) (1525:1525:1525)) + (PORT clk (1509:1509:1509) (1522:1522:1522)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1566:1566:1566) (1561:1561:1561)) + (PORT clrn (1550:1550:1550) (1543:1543:1543)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -36263,7 +29066,7 @@ (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[2\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (228:228:228) (301:301:301)) + (PORT datad (226:226:226) (299:299:299)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -36273,9 +29076,9 @@ (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[2\]) (DELAY (ABSOLUTE - (PORT clk (1512:1512:1512) (1525:1525:1525)) + (PORT clk (1509:1509:1509) (1522:1522:1522)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1566:1566:1566) (1561:1561:1561)) + (PORT clrn (1550:1550:1550) (1543:1543:1543)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -36289,7 +29092,7 @@ (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[1\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (226:226:226) (298:298:298)) + (PORT datad (225:225:225) (297:297:297)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -36299,9 +29102,9 @@ (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[1\]) (DELAY (ABSOLUTE - (PORT clk (1512:1512:1512) (1525:1525:1525)) + (PORT clk (1509:1509:1509) (1522:1522:1522)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1566:1566:1566) (1561:1561:1561)) + (PORT clrn (1550:1550:1550) (1543:1543:1543)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -36310,17 +29113,33 @@ (HOLD d (posedge clk) (157:157:157)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (253:253:253) (343:343:343)) + (PORT datab (251:251:251) (336:336:336)) + (PORT datac (376:376:376) (441:441:441)) + (PORT datad (226:226:226) (298:298:298)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|ps2_keyboard_\|Equal0\~1) (DELAY (ABSOLUTE - (PORT dataa (202:202:202) (246:246:246)) - (PORT datab (252:252:252) (337:337:337)) - (PORT datac (225:225:225) (305:305:305)) - (PORT datad (227:227:227) (299:299:299)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (253:253:253) (343:343:343)) + (PORT datab (253:253:253) (338:338:338)) + (PORT datac (226:226:226) (307:307:307)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -36331,7 +29150,7 @@ (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[0\]\~0) (DELAY (ABSOLUTE - (PORT datac (226:226:226) (307:307:307)) + (PORT datac (227:227:227) (309:309:309)) (IOPATH datac combout (241:241:241) (241:241:241)) ) ) @@ -36341,9 +29160,9 @@ (INSTANCE ula_\|ps2_keyboard_\|clk_filter\[0\]) (DELAY (ABSOLUTE - (PORT clk (1512:1512:1512) (1525:1525:1525)) + (PORT clk (1509:1509:1509) (1522:1522:1522)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1566:1566:1566) (1561:1561:1561)) + (PORT clrn (1550:1550:1550) (1543:1543:1543)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -36357,9 +29176,9 @@ (INSTANCE ula_\|ps2_keyboard_\|ps2_clk_in\~0) (DELAY (ABSOLUTE - (PORT datab (208:208:208) (249:249:249)) + (PORT dataa (211:211:211) (258:258:258)) (PORT datad (227:227:227) (299:299:299)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -36370,9 +29189,9 @@ (INSTANCE ula_\|ps2_keyboard_\|ps2_clk_in) (DELAY (ABSOLUTE - (PORT clk (1512:1512:1512) (1525:1525:1525)) + (PORT clk (1509:1509:1509) (1522:1522:1522)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1566:1566:1566) (1561:1561:1561)) + (PORT clrn (1550:1550:1550) (1543:1543:1543)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -36386,10 +29205,10 @@ (INSTANCE ula_\|ps2_keyboard_\|clk_edge\~0) (DELAY (ABSOLUTE - (PORT datab (208:208:208) (250:250:250)) - (PORT datac (218:218:218) (295:295:295)) - (PORT datad (224:224:224) (296:296:296)) - (IOPATH datab combout (304:304:304) (311:311:311)) + (PORT dataa (212:212:212) (261:261:261)) + (PORT datac (217:217:217) (293:293:293)) + (PORT datad (228:228:228) (301:301:301)) + (IOPATH dataa combout (303:303:303) (308:308:308)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -36400,9 +29219,9 @@ (INSTANCE ula_\|ps2_keyboard_\|clk_edge) (DELAY (ABSOLUTE - (PORT clk (1512:1512:1512) (1525:1525:1525)) + (PORT clk (1509:1509:1509) (1522:1522:1522)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1566:1566:1566) (1561:1561:1561)) + (PORT clrn (1550:1550:1550) (1543:1543:1543)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -36413,13 +29232,13 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\[0\]) + (INSTANCE ula_\|ps2_keyboard_\|bit_count\[3\]) (DELAY (ABSOLUTE - (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT clk (1507:1507:1507) (1521:1521:1521)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1567:1567:1567) (1562:1562:1562)) - (PORT ena (2016:2016:2016) (2055:2055:2055)) + (PORT clrn (1547:1547:1547) (1540:1540:1540)) + (PORT ena (2271:2271:2271) (2360:2360:2360)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -36434,9 +29253,9 @@ (INSTANCE ula_\|ps2_keyboard_\|bit_count\~1) (DELAY (ABSOLUTE - (PORT dataa (282:282:282) (387:387:387)) - (PORT datab (292:292:292) (383:383:383)) - (PORT datad (240:240:240) (317:317:317)) + (PORT dataa (271:271:271) (369:369:369)) + (PORT datab (278:278:278) (372:372:372)) + (PORT datad (250:250:250) (334:334:334)) (IOPATH dataa combout (303:303:303) (299:299:299)) (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -36449,43 +29268,10 @@ (INSTANCE ula_\|ps2_keyboard_\|bit_count\[2\]) (DELAY (ABSOLUTE - (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT clk (1507:1507:1507) (1521:1521:1521)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1567:1567:1567) (1562:1562:1562)) - (PORT ena (2016:2016:2016) (2055:2055:2055)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\~3) - (DELAY - (ABSOLUTE - (PORT dataa (279:279:279) (382:382:382)) - (PORT datab (278:278:278) (373:373:373)) - (PORT datad (242:242:242) (321:321:321)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|ps2_keyboard_\|bit_count\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1535:1535:1535)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1567:1567:1567) (1562:1562:1562)) - (PORT ena (2016:2016:2016) (2055:2055:2055)) + (PORT clrn (1547:1547:1547) (1540:1540:1540)) + (PORT ena (2271:2271:2271) (2360:2360:2360)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -36500,9 +29286,9 @@ (INSTANCE ula_\|ps2_keyboard_\|bit_count\~2) (DELAY (ABSOLUTE - (PORT dataa (410:410:410) (480:480:480)) - (PORT datab (279:279:279) (374:374:374)) - (PORT datad (243:243:243) (322:322:322)) + (PORT dataa (272:272:272) (374:374:374)) + (PORT datab (281:281:281) (377:377:377)) + (PORT datad (247:247:247) (327:327:327)) (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datab combout (336:336:336) (325:325:325)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -36515,10 +29301,43 @@ (INSTANCE ula_\|ps2_keyboard_\|bit_count\[1\]) (DELAY (ABSOLUTE - (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT clk (1507:1507:1507) (1521:1521:1521)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1567:1567:1567) (1562:1562:1562)) - (PORT ena (2016:2016:2016) (2055:2055:2055)) + (PORT clrn (1547:1547:1547) (1540:1540:1540)) + (PORT ena (2271:2271:2271) (2360:2360:2360)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\~0) + (DELAY + (ABSOLUTE + (PORT dataa (277:277:277) (377:377:377)) + (PORT datab (276:276:276) (371:371:371)) + (PORT datad (251:251:251) (330:330:330)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|ps2_keyboard_\|bit_count\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1507:1507:1507) (1521:1521:1521)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1547:1547:1547) (1540:1540:1540)) + (PORT ena (2271:2271:2271) (2360:2360:2360)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -36533,10 +29352,10 @@ (INSTANCE ula_\|ps2_keyboard_\|always1\~0) (DELAY (ABSOLUTE - (PORT dataa (275:275:275) (377:377:377)) - (PORT datab (288:288:288) (377:377:377)) - (PORT datac (3414:3414:3414) (3775:3775:3775)) - (PORT datad (251:251:251) (331:331:331)) + (PORT dataa (276:276:276) (373:373:373)) + (PORT datab (279:279:279) (374:374:374)) + (PORT datac (4093:4093:4093) (4524:4524:4524)) + (PORT datad (243:243:243) (322:322:322)) (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -36549,11 +29368,11 @@ (INSTANCE ula_\|ps2_keyboard_\|LessThan0\~0) (DELAY (ABSOLUTE - (PORT datab (289:289:289) (380:380:380)) - (PORT datac (247:247:247) (341:341:341)) - (PORT datad (248:248:248) (328:328:328)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (276:276:276) (378:378:378)) + (PORT datab (278:278:278) (373:373:373)) + (PORT datad (246:246:246) (325:325:325)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -36563,12 +29382,12 @@ (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[0\]\~0) (DELAY (ABSOLUTE - (PORT dataa (202:202:202) (246:246:246)) - (PORT datab (264:264:264) (354:354:354)) - (PORT datac (1368:1368:1368) (1427:1427:1427)) + (PORT dataa (269:269:269) (366:366:366)) + (PORT datab (201:201:201) (241:241:241)) + (PORT datac (1623:1623:1623) (1741:1741:1741)) (PORT datad (182:182:182) (211:211:211)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -36579,10 +29398,10 @@ (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[8\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1544:1544:1544)) - (PORT asdata (3957:3957:3957) (4311:4311:4311)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (PORT ena (1226:1226:1226) (1215:1215:1215)) + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT asdata (4114:4114:4114) (4514:4514:4514)) + (PORT clrn (1555:1555:1555) (1548:1548:1548)) + (PORT ena (1802:1802:1802) (1801:1801:1801)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -36592,21 +29411,31 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (219:219:219) (288:288:288)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[7\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1544:1544:1544)) - (PORT asdata (560:560:560) (634:634:634)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (PORT ena (1226:1226:1226) (1215:1215:1215)) + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1555:1555:1555) (1548:1548:1548)) + (PORT ena (1802:1802:1802) (1801:1801:1801)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) + (HOLD d (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) ) ) @@ -36615,10 +29444,10 @@ (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[6\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1544:1544:1544)) - (PORT asdata (602:602:602) (685:685:685)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (PORT ena (1226:1226:1226) (1215:1215:1215)) + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT asdata (629:629:629) (715:715:715)) + (PORT clrn (1555:1555:1555) (1548:1548:1548)) + (PORT ena (1802:1802:1802) (1801:1801:1801)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -36633,10 +29462,10 @@ (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[5\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1544:1544:1544)) - (PORT asdata (588:588:588) (665:665:665)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (PORT ena (1226:1226:1226) (1215:1215:1215)) + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT asdata (1040:1040:1040) (1106:1106:1106)) + (PORT clrn (1555:1555:1555) (1548:1548:1548)) + (PORT ena (1802:1802:1802) (1801:1801:1801)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -36651,10 +29480,10 @@ (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[4\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1543:1543:1543)) - (PORT asdata (958:958:958) (1010:1010:1010)) - (PORT clrn (1576:1576:1576) (1571:1571:1571)) - (PORT ena (1200:1200:1200) (1196:1196:1196)) + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT asdata (809:809:809) (898:898:898)) + (PORT clrn (1555:1555:1555) (1548:1548:1548)) + (PORT ena (1802:1802:1802) (1801:1801:1801)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -36669,10 +29498,10 @@ (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[3\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1544:1544:1544)) - (PORT asdata (960:960:960) (1018:1018:1018)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (PORT ena (1226:1226:1226) (1215:1215:1215)) + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (1541:1541:1541) (1621:1621:1621)) + (PORT clrn (1557:1557:1557) (1549:1549:1549)) + (PORT ena (2289:2289:2289) (2267:2267:2267)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -36687,10 +29516,10 @@ (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[2\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1543:1543:1543)) - (PORT asdata (951:951:951) (1014:1014:1014)) - (PORT clrn (1576:1576:1576) (1571:1571:1571)) - (PORT ena (1200:1200:1200) (1196:1196:1196)) + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT asdata (1528:1528:1528) (1600:1600:1600)) + (PORT clrn (1555:1555:1555) (1547:1547:1547)) + (PORT ena (1975:1975:1975) (1972:1972:1972)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -36705,10 +29534,10 @@ (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[1\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1543:1543:1543)) - (PORT asdata (761:761:761) (840:840:840)) - (PORT clrn (1576:1576:1576) (1571:1571:1571)) - (PORT ena (1200:1200:1200) (1196:1196:1196)) + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT asdata (604:604:604) (688:688:688)) + (PORT clrn (1555:1555:1555) (1547:1547:1547)) + (PORT ena (1975:1975:1975) (1972:1972:1972)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -36718,93 +29547,43 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1133:1133:1133) (1224:1224:1224)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|ps2_keyboard_\|shiftreg\[0\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1543:1543:1543)) - (PORT asdata (791:791:791) (867:867:867)) - (PORT clrn (1576:1576:1576) (1571:1571:1571)) - (PORT ena (1200:1200:1200) (1196:1196:1196)) + (PORT clk (1510:1510:1510) (1524:1524:1524)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1550:1550:1550) (1543:1543:1543)) + (PORT ena (1270:1270:1270) (1278:1278:1278)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) ) (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) + (HOLD d (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Equal0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (990:990:990) (1075:1075:1075)) - (PORT datab (675:675:675) (742:742:742)) - (PORT datac (757:757:757) (876:876:876)) - (PORT datad (781:781:781) (888:888:888)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Equal0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1415:1415:1415) (1549:1549:1549)) - (PORT datab (937:937:937) (1037:1037:1037)) - (PORT datac (171:171:171) (205:205:205)) - (PORT datad (763:763:763) (875:875:875)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|extended\~0) - (DELAY - (ABSOLUTE - (PORT datab (1062:1062:1062) (1155:1155:1155)) - (PORT datad (785:785:785) (795:795:795)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (664:664:664) (722:722:722)) - (PORT datab (288:288:288) (378:378:378)) - (PORT datad (833:833:833) (880:880:880)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~0) (DELAY (ABSOLUTE - (PORT dataa (741:741:741) (827:827:827)) - (PORT datab (669:669:669) (749:749:749)) - (PORT datac (655:655:655) (721:721:721)) - (PORT datad (438:438:438) (511:511:511)) + (PORT dataa (1156:1156:1156) (1261:1261:1261)) + (PORT datab (313:313:313) (413:413:413)) + (PORT datac (960:960:960) (1045:1045:1045)) + (PORT datad (949:949:949) (1017:1017:1017)) (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (243:243:243) (242:242:242)) @@ -36812,15 +29591,30 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (465:465:465) (561:561:561)) + (PORT datab (495:495:495) (591:591:591)) + (PORT datad (442:442:442) (500:500:500)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|ps2_keyboard_\|WideXor0\~2) (DELAY (ABSOLUTE - (PORT datab (668:668:668) (736:736:736)) - (PORT datac (345:345:345) (369:369:369)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT dataa (1049:1049:1049) (1137:1137:1137)) + (PORT datac (173:173:173) (206:206:206)) + (PORT datad (777:777:777) (823:823:823)) + (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -36831,10 +29625,10 @@ (INSTANCE ula_\|ps2_keyboard_\|scan_code_ready\~0) (DELAY (ABSOLUTE - (PORT dataa (210:210:210) (255:255:255)) - (PORT datab (3434:3434:3434) (3812:3812:3812)) - (PORT datac (1368:1368:1368) (1428:1428:1428)) - (PORT datad (358:358:358) (390:390:390)) + (PORT dataa (4129:4129:4129) (4562:4562:4562)) + (PORT datab (1649:1649:1649) (1770:1770:1770)) + (PORT datac (623:623:623) (642:642:642)) + (PORT datad (181:181:181) (209:209:209)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -36847,9 +29641,9 @@ (INSTANCE ula_\|ps2_keyboard_\|scan_code_ready) (DELAY (ABSOLUTE - (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT clk (1507:1507:1507) (1521:1521:1521)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1567:1567:1567) (1562:1562:1562)) + (PORT clrn (1547:1547:1547) (1540:1540:1540)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -36858,15 +29652,91 @@ (HOLD d (posedge clk) (157:157:157)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (434:434:434) (504:504:504)) + (PORT datab (983:983:983) (1066:1066:1066)) + (PORT datac (931:931:931) (996:996:996)) + (PORT datad (678:678:678) (759:759:759)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (694:694:694) (783:783:783)) + (PORT datab (693:693:693) (752:752:752)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (2178:2178:2178) (2280:2280:2280)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|released\~0) + (DELAY + (ABSOLUTE + (PORT dataa (291:291:291) (387:387:387)) + (PORT datab (1232:1232:1232) (1299:1299:1299)) + (PORT datad (333:333:333) (358:358:358)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|released) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1555:1555:1555) (1548:1548:1548)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|extended\~0) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (397:397:397)) + (PORT datad (956:956:956) (1027:1027:1027)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|zx_keyboard_\|extended) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1545:1545:1545)) + (PORT clk (1521:1521:1521) (1534:1534:1534)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (PORT ena (1764:1764:1764) (1796:1796:1796)) + (PORT clrn (1555:1555:1555) (1548:1548:1548)) + (PORT ena (1826:1826:1826) (1852:1852:1852)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -36878,26 +29748,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~15) + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~21) (DELAY (ABSOLUTE - (PORT dataa (678:678:678) (758:758:758)) - (PORT datab (664:664:664) (692:692:692)) - (PORT datac (260:260:260) (346:346:346)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (486:486:486) (553:553:553)) - (PORT datac (1367:1367:1367) (1453:1453:1453)) - (PORT datad (841:841:841) (864:864:864)) + (PORT dataa (515:515:515) (590:590:590)) + (PORT datac (288:288:288) (373:373:373)) + (PORT datad (1195:1195:1195) (1259:1259:1259)) (IOPATH dataa combout (325:325:325) (320:320:320)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -36906,293 +29762,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~37) + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~22) (DELAY (ABSOLUTE - (PORT dataa (1164:1164:1164) (1265:1265:1265)) - (PORT datac (641:641:641) (670:670:670)) - (PORT datad (910:910:910) (977:977:977)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|shifted\~0) - (DELAY - (ABSOLUTE - (PORT dataa (396:396:396) (426:426:426)) - (PORT datac (615:615:615) (667:667:667)) - (PORT datad (726:726:726) (803:803:803)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|released\~0) - (DELAY - (ABSOLUTE - (PORT dataa (669:669:669) (736:736:736)) - (PORT datab (663:663:663) (694:694:694)) - (PORT datad (1337:1337:1337) (1379:1379:1379)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|released) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr17\~0) - (DELAY - (ABSOLUTE - (PORT dataa (488:488:488) (568:568:568)) - (PORT datab (663:663:663) (740:740:740)) - (PORT datac (606:606:606) (673:673:673)) - (PORT datad (259:259:259) (336:336:336)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|shifted\~2) - (DELAY - (ABSOLUTE - (PORT dataa (203:203:203) (247:247:247)) - (PORT datac (416:416:416) (498:498:498)) - (PORT datad (651:651:651) (725:725:725)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|shifted\~3) - (DELAY - (ABSOLUTE - (PORT dataa (601:601:601) (616:616:616)) - (PORT datab (428:428:428) (507:507:507)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|shifted) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1543:1543:1543)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1576:1576:1576) (1571:1571:1571)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (744:744:744) (848:848:848)) - (PORT datab (984:984:984) (1072:1072:1072)) - (PORT datad (962:962:962) (1042:1042:1042)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~38) - (DELAY - (ABSOLUTE - (PORT datab (751:751:751) (858:858:858)) - (PORT datac (739:739:739) (840:840:840)) - (PORT datad (729:729:729) (835:835:835)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~39) - (DELAY - (ABSOLUTE - (PORT dataa (351:351:351) (394:394:394)) - (PORT datab (201:201:201) (241:241:241)) - (PORT datad (175:175:175) (202:202:202)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1573:1573:1573)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]\~31) - (DELAY - (ABSOLUTE - (PORT datab (963:963:963) (1041:1041:1041)) - (PORT datad (729:729:729) (834:834:834)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (740:740:740) (827:827:827)) - (PORT datab (290:290:290) (378:378:378)) - (PORT datac (649:649:649) (725:725:725)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~32) - (DELAY - (ABSOLUTE - (PORT datab (655:655:655) (729:729:729)) - (PORT datac (395:395:395) (471:471:471)) - (PORT datad (657:657:657) (716:716:716)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (376:376:376) (418:418:418)) - (PORT datab (223:223:223) (270:270:270)) - (PORT datac (658:658:658) (723:723:723)) - (PORT datad (433:433:433) (507:507:507)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (225:225:225) (269:269:269)) - (PORT datab (622:622:622) (671:671:671)) - (PORT datad (962:962:962) (1038:1038:1038)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1573:1573:1573)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (1160:1160:1160) (1230:1230:1230)) - (PORT datab (241:241:241) (321:321:321)) - (PORT datac (215:215:215) (291:291:291)) - (PORT datad (548:548:548) (570:570:570)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~24) - (DELAY - (ABSOLUTE - (PORT dataa (969:969:969) (1044:1044:1044)) - (PORT datac (902:902:902) (995:995:995)) + (PORT dataa (667:667:667) (737:737:737)) + (PORT datac (259:259:259) (350:350:350)) (IOPATH dataa combout (341:341:341) (347:347:347)) (IOPATH datac combout (243:243:243) (242:242:242)) ) @@ -37200,29 +29774,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~28) + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]\~23) (DELAY (ABSOLUTE - (PORT dataa (1413:1413:1413) (1549:1549:1549)) - (PORT datab (696:696:696) (729:729:729)) - (PORT datac (959:959:959) (1041:1041:1041)) - (PORT datad (190:190:190) (224:224:224)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~29) - (DELAY - (ABSOLUTE - (PORT datab (981:981:981) (1070:1070:1070)) - (PORT datac (721:721:721) (830:830:830)) - (PORT datad (729:729:729) (838:838:838)) - (IOPATH datab combout (342:342:342) (342:342:342)) + (PORT dataa (847:847:847) (935:935:935)) + (PORT datab (1008:1008:1008) (1092:1092:1092)) + (PORT datac (830:830:830) (887:887:887)) + (PORT datad (1542:1542:1542) (1630:1630:1630)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -37230,12 +29790,26 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~30) + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]\~24) (DELAY (ABSOLUTE - (PORT dataa (792:792:792) (908:908:908)) - (PORT datab (667:667:667) (685:685:685)) - (PORT datad (496:496:496) (512:512:512)) + (PORT dataa (756:756:756) (830:830:830)) + (PORT datab (951:951:951) (1077:1077:1077)) + (PORT datad (198:198:198) (224:224:224)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (936:936:936) (1023:1023:1023)) + (PORT datab (642:642:642) (729:729:729)) + (PORT datad (375:375:375) (402:402:402)) (IOPATH dataa combout (325:325:325) (328:328:328)) (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -37243,75 +29817,14 @@ ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1573:1573:1573)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]\~25) - (DELAY - (ABSOLUTE - (PORT dataa (1414:1414:1414) (1542:1542:1542)) - (PORT datab (213:213:213) (258:258:258)) - (PORT datac (667:667:667) (692:692:692)) - (PORT datad (766:766:766) (872:872:872)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]\~26) - (DELAY - (ABSOLUTE - (PORT dataa (716:716:716) (818:818:818)) - (PORT datab (363:363:363) (394:394:394)) - (PORT datac (717:717:717) (819:819:819)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]\~27) - (DELAY - (ABSOLUTE - (PORT dataa (1555:1555:1555) (1666:1666:1666)) - (PORT datab (982:982:982) (1037:1037:1037)) - (PORT datad (518:518:518) (530:530:530)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[1\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT clk (1518:1518:1518) (1532:1532:1532)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) + (PORT clrn (1558:1558:1558) (1550:1550:1550)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -37325,23 +29838,374 @@ (INSTANCE ula_\|zx_keyboard_\|key_row\~0) (DELAY (ABSOLUTE - (PORT datab (1469:1469:1469) (1606:1606:1606)) - (PORT datac (912:912:912) (975:975:975)) - (PORT datad (217:217:217) (285:285:285)) + (PORT datab (2434:2434:2434) (2613:2613:2613)) + (PORT datac (1881:1881:1881) (1943:1943:1943)) + (PORT datad (216:216:216) (284:284:284)) (IOPATH datab combout (336:336:336) (325:325:325)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (846:846:846) (935:935:935)) + (PORT datab (1010:1010:1010) (1096:1096:1096)) + (PORT datac (829:829:829) (887:887:887)) + (PORT datad (908:908:908) (1031:1031:1031)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (1316:1316:1316) (1413:1413:1413)) + (PORT datab (971:971:971) (1049:1049:1049)) + (PORT datad (399:399:399) (475:475:475)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (612:612:612) (635:635:635)) + (PORT datab (949:949:949) (1020:1020:1020)) + (PORT datad (184:184:184) (215:215:215)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1558:1558:1558) (1549:1549:1549)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[11\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1433:1433:1433) (1482:1482:1482)) + (PORT datab (1398:1398:1398) (1451:1451:1451)) + (PORT datad (306:306:306) (323:323:323)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1527:1527:1527)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (980:980:980) (1030:1030:1030)) + (PORT sload (2032:2032:2032) (2084:2084:2084)) + (PORT ena (2298:2298:2298) (2265:2265:2265)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[11\]\~19) + (DELAY + (ABSOLUTE + (PORT datac (2119:2119:2119) (2214:2214:2214)) + (PORT datad (1199:1199:1199) (1296:1296:1296)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (506:506:506) (582:582:582)) + (PORT datab (727:727:727) (802:802:802)) + (PORT datac (290:290:290) (379:379:379)) + (PORT datad (1195:1195:1195) (1258:1258:1258)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1196:1196:1196) (1273:1273:1273)) + (PORT datab (719:719:719) (787:787:787)) + (PORT datac (961:961:961) (1035:1035:1035)) + (PORT datad (2206:2206:2206) (2296:2296:2296)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1482:1482:1482) (1607:1607:1607)) + (PORT datab (965:965:965) (1044:1044:1044)) + (PORT datac (614:614:614) (634:634:634)) + (PORT datad (347:347:347) (370:370:370)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (783:783:783) (866:866:866)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1558:1558:1558) (1550:1550:1550)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[9\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1396:1396:1396) (1442:1442:1442)) + (PORT datab (868:868:868) (901:901:901)) + (PORT datad (180:180:180) (209:209:209)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1527:1527:1527)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (580:580:580) (654:654:654)) + (PORT sload (2041:2041:2041) (2133:2133:2133)) + (PORT ena (2004:2004:2004) (1967:1967:1967)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[9\]\~17) + (DELAY + (ABSOLUTE + (PORT datab (261:261:261) (344:344:344)) + (PORT datac (2391:2391:2391) (2523:2523:2523)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~13) + (DELAY + (ABSOLUTE + (PORT datab (1232:1232:1232) (1296:1296:1296)) + (PORT datac (289:289:289) (378:378:378)) + (PORT datad (332:332:332) (357:357:357)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|shifted\~2) + (DELAY + (ABSOLUTE + (PORT datab (1028:1028:1028) (1107:1107:1107)) + (PORT datac (700:700:700) (766:766:766)) + (PORT datad (597:597:597) (613:613:613)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~14) (DELAY (ABSOLUTE - (PORT datab (425:425:425) (503:503:503)) - (PORT datac (1117:1117:1117) (1170:1170:1170)) - (PORT datad (651:651:651) (723:723:723)) + (PORT dataa (1047:1047:1047) (1139:1139:1139)) + (PORT datab (313:313:313) (414:414:414)) + (PORT datac (957:957:957) (1046:1046:1046)) + (PORT datad (946:946:946) (1019:1019:1019)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1049:1049:1049) (1136:1136:1136)) + (PORT datab (200:200:200) (240:240:240)) + (PORT datac (961:961:961) (1043:1043:1043)) + (PORT datad (1125:1125:1125) (1214:1214:1214)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr17\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1157:1157:1157) (1263:1263:1263)) + (PORT datab (314:314:314) (413:413:413)) + (PORT datac (957:957:957) (1039:1039:1039)) + (PORT datad (913:913:913) (983:983:983)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|shifted\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1050:1050:1050) (1142:1142:1142)) + (PORT datab (975:975:975) (1058:1058:1058)) + (PORT datac (321:321:321) (340:340:340)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|shifted\~4) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (1163:1163:1163) (1216:1216:1216)) + (PORT datad (851:851:851) (879:879:879)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|shifted) + (DELAY + (ABSOLUTE + (PORT clk (1510:1510:1510) (1524:1524:1524)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1550:1550:1550) (1543:1543:1543)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~12) + (DELAY + (ABSOLUTE + (PORT datab (1165:1165:1165) (1220:1220:1220)) + (PORT datac (260:260:260) (338:338:338)) + (PORT datad (1006:1006:1006) (1089:1089:1089)) (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -37353,43 +30217,11 @@ (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~16) (DELAY (ABSOLUTE - (PORT dataa (693:693:693) (776:776:776)) - (PORT datab (412:412:412) (493:493:493)) - (PORT datac (606:606:606) (674:674:674)) - (PORT datad (261:261:261) (340:340:340)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (490:490:490) (569:569:569)) - (PORT datab (664:664:664) (741:741:741)) - (PORT datac (497:497:497) (515:515:515)) - (PORT datad (655:655:655) (724:724:724)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]\~18) - (DELAY - (ABSOLUTE - (PORT dataa (600:600:600) (615:615:615)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datad (175:175:175) (200:200:200)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (336:336:336) (332:332:332)) + (PORT dataa (877:877:877) (922:922:922)) + (PORT datab (201:201:201) (241:241:241)) + (PORT datad (176:176:176) (202:202:202)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -37400,9 +30232,9 @@ (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[1\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1543:1543:1543)) + (PORT clk (1510:1510:1510) (1524:1524:1524)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1576:1576:1576) (1571:1571:1571)) + (PORT clrn (1550:1550:1550) (1543:1543:1543)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -37413,15 +30245,45 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~19) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[8\]\~8) (DELAY (ABSOLUTE - (PORT dataa (707:707:707) (768:768:768)) - (PORT datab (1230:1230:1230) (1291:1291:1291)) - (PORT datac (443:443:443) (506:506:506)) - (PORT datad (1066:1066:1066) (1109:1109:1109)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) + (PORT dataa (1396:1396:1396) (1442:1442:1442)) + (PORT datab (975:975:975) (1010:1010:1010)) + (PORT datad (171:171:171) (196:196:196)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1527:1527:1527)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (748:748:748) (806:806:806)) + (PORT sload (2041:2041:2041) (2133:2133:2133)) + (PORT ena (2004:2004:2004) (1967:1967:1967)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[8\]\~18) + (DELAY + (ABSOLUTE + (PORT datac (2403:2403:2403) (2576:2576:2576)) + (PORT datad (1457:1457:1457) (1514:1514:1514)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -37429,31 +30291,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~20) + (INSTANCE D\[1\]\~26) (DELAY (ABSOLUTE - (PORT dataa (752:752:752) (844:844:844)) - (PORT datab (1400:1400:1400) (1489:1489:1489)) - (PORT datac (917:917:917) (988:988:988)) - (PORT datad (854:854:854) (921:921:921)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (225:225:225) (279:279:279)) - (PORT datab (222:222:222) (261:261:261)) - (PORT datac (739:739:739) (839:839:839)) - (PORT datad (1547:1547:1547) (1637:1637:1637)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) + (PORT dataa (676:676:676) (744:744:744)) + (PORT datab (1126:1126:1126) (1130:1130:1130)) + (PORT datac (801:801:801) (888:888:888)) + (PORT datad (197:197:197) (223:223:223)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -37461,12 +30307,190 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]\~22) + (INSTANCE D\[1\]\~27) (DELAY (ABSOLUTE - (PORT datab (523:523:523) (533:533:533)) - (PORT datad (944:944:944) (998:998:998)) + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (388:388:388) (462:462:462)) + (PORT datac (1053:1053:1053) (1052:1052:1052)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[12\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1430:1430:1430) (1480:1480:1480)) + (PORT datab (338:338:338) (373:373:373)) + (PORT datad (561:561:561) (569:569:569)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1527:1527:1527)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (588:588:588) (665:665:665)) + (PORT sload (2032:2032:2032) (2084:2084:2084)) + (PORT ena (2298:2298:2298) (2265:2265:2265)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[12\]\~21) + (DELAY + (ABSOLUTE + (PORT datac (2385:2385:2385) (2515:2515:2515)) + (PORT datad (991:991:991) (1047:1047:1047)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|b2v_inst_inc_dec\|b2v_dual_adder_10\|d1_out) + (DELAY + (ABSOLUTE + (PORT datab (383:383:383) (410:410:410)) + (PORT datad (403:403:403) (462:462:462)) (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[13\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1434:1434:1434) (1480:1480:1480)) + (PORT datab (197:197:197) (234:234:234)) + (PORT datad (194:194:194) (219:219:219)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1527:1527:1527)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (970:970:970) (1036:1036:1036)) + (PORT sload (2032:2032:2032) (2084:2084:2084)) + (PORT ena (2298:2298:2298) (2265:2265:2265)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[13\]\~20) + (DELAY + (ABSOLUTE + (PORT datab (2598:2598:2598) (2762:2762:2762)) + (PORT datad (2258:2258:2258) (2378:2378:2378)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (956:956:956) (1021:1021:1021)) + (PORT datac (666:666:666) (730:730:730)) + (PORT datad (987:987:987) (1074:1074:1074)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~34) + (DELAY + (ABSOLUTE + (PORT datab (714:714:714) (780:780:780)) + (PORT datac (700:700:700) (763:763:763)) + (PORT datad (598:598:598) (610:610:610)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (641:641:641) (679:679:679)) + (PORT datac (993:993:993) (1069:1069:1069)) + (PORT datad (693:693:693) (763:763:763)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (1487:1487:1487) (1546:1546:1546)) + (PORT datab (723:723:723) (778:778:778)) + (PORT datad (918:918:918) (979:979:979)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (245:245:245)) + (PORT datab (207:207:207) (249:249:249)) + (PORT datad (176:176:176) (202:202:202)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -37474,12 +30498,85 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[1\]) + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[1\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT clk (1519:1519:1519) (1533:1533:1533)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) + (PORT clrn (1559:1559:1559) (1552:1552:1552)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]\~29) + (DELAY + (ABSOLUTE + (PORT datac (952:952:952) (1033:1033:1033)) + (PORT datad (659:659:659) (715:715:715)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (1019:1019:1019) (1100:1100:1100)) + (PORT datab (1231:1231:1231) (1315:1315:1315)) + (PORT datac (986:986:986) (1079:1079:1079)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (413:413:413) (493:493:493)) + (PORT datab (652:652:652) (695:695:695)) + (PORT datac (346:346:346) (367:367:367)) + (PORT datad (936:936:936) (976:976:976)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (626:626:626) (654:654:654)) + (PORT datab (942:942:942) (1015:1015:1015)) + (PORT datad (322:322:322) (342:342:342)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1533:1533:1533)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1559:1559:1559) (1552:1552:1552)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -37493,44 +30590,12 @@ (INSTANCE D\[1\]\~28) (DELAY (ABSOLUTE - (PORT dataa (670:670:670) (729:729:729)) - (PORT datab (1120:1120:1120) (1195:1195:1195)) - (PORT datac (633:633:633) (694:694:694)) - (PORT datad (216:216:216) (284:284:284)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~29) - (DELAY - (ABSOLUTE - (PORT dataa (687:687:687) (745:745:745)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (195:195:195) (228:228:228)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~41) - (DELAY - (ABSOLUTE - (PORT dataa (484:484:484) (550:550:550)) - (PORT datab (1228:1228:1228) (1291:1291:1291)) - (PORT datac (741:741:741) (842:842:842)) - (PORT datad (842:842:842) (867:867:867)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) + (PORT dataa (605:605:605) (633:633:633)) + (PORT datab (778:778:778) (783:783:783)) + (PORT datac (214:214:214) (289:289:289)) + (PORT datad (215:215:215) (283:283:283)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -37538,30 +30603,58 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~42) + (INSTANCE z80_\|address_pins_\|abus\[0\]\~16) (DELAY (ABSOLUTE - (PORT dataa (783:783:783) (875:875:875)) - (PORT datab (913:913:913) (986:986:986)) - (PORT datac (1115:1115:1115) (1162:1162:1162)) - (PORT datad (710:710:710) (791:791:791)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (325:325:325)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT datab (956:956:956) (1016:1016:1016)) + (PORT datac (2761:2761:2761) (2948:2948:2948)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~43) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[14\]\~14) (DELAY (ABSOLUTE - (PORT dataa (358:358:358) (395:395:395)) - (PORT datac (700:700:700) (784:784:784)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (1429:1429:1429) (1479:1479:1479)) + (PORT datab (219:219:219) (258:258:258)) + (PORT datad (313:313:313) (329:329:329)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1527:1527:1527)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (582:582:582) (670:670:670)) + (PORT sload (2032:2032:2032) (2084:2084:2084)) + (PORT ena (2298:2298:2298) (2265:2265:2265)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[14\]\~23) + (DELAY + (ABSOLUTE + (PORT datac (2563:2563:2563) (2734:2734:2734)) + (PORT datad (1593:1593:1593) (1728:1728:1728)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -37571,23 +30664,71 @@ (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~40) (DELAY (ABSOLUTE - (PORT dataa (776:776:776) (868:868:868)) - (PORT datab (912:912:912) (984:984:984)) - (PORT datac (659:659:659) (735:735:735)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (997:997:997) (1075:1075:1075)) + (PORT datab (1225:1225:1225) (1305:1305:1305)) + (PORT datad (1291:1291:1291) (1368:1368:1368)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~44) + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~41) (DELAY (ABSOLUTE - (PORT dataa (199:199:199) (243:243:243)) - (PORT datad (176:176:176) (202:202:202)) - (IOPATH dataa combout (354:354:354) (367:367:367)) + (PORT dataa (997:997:997) (1082:1082:1082)) + (PORT datab (426:426:426) (515:515:515)) + (PORT datac (174:174:174) (207:207:207)) + (PORT datad (944:944:944) (1011:1011:1011)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (784:784:784) (862:862:862)) + (PORT datab (747:747:747) (839:839:839)) + (PORT datac (563:563:563) (583:583:583)) + (PORT datad (427:427:427) (491:491:491)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (1010:1010:1010) (1060:1060:1060)) + (PORT datac (964:964:964) (1035:1035:1035)) + (PORT datad (911:911:911) (979:979:979)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (245:245:245)) + (PORT datab (652:652:652) (675:675:675)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -37598,9 +30739,9 @@ (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[1\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT clk (1518:1518:1518) (1532:1532:1532)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1572:1572:1572)) + (PORT clrn (1558:1558:1558) (1549:1549:1549)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -37611,13 +30752,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~45) + (INSTANCE ula_\|zx_keyboard_\|WideOr16\~4) (DELAY (ABSOLUTE - (PORT dataa (632:632:632) (710:710:710)) - (PORT datab (496:496:496) (580:580:580)) - (PORT datac (396:396:396) (470:470:470)) - (PORT datad (601:601:601) (643:643:643)) + (PORT dataa (1160:1160:1160) (1266:1266:1266)) + (PORT datab (314:314:314) (415:415:415)) + (PORT datac (959:959:959) (1046:1046:1046)) + (PORT datad (944:944:944) (1020:1020:1020)) (IOPATH dataa combout (354:354:354) (349:349:349)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -37625,48 +30766,16 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr16\~5) - (DELAY - (ABSOLUTE - (PORT dataa (825:825:825) (937:937:937)) - (PORT datab (941:941:941) (1038:1038:1038)) - (PORT datac (758:758:758) (878:878:878)) - (PORT datad (764:764:764) (871:871:871)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|zx_keyboard_\|WideOr16\~2) (DELAY (ABSOLUTE - (PORT dataa (820:820:820) (932:932:932)) - (PORT datab (788:788:788) (904:904:904)) - (PORT datad (763:763:763) (876:876:876)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr16\~4) - (DELAY - (ABSOLUTE - (PORT dataa (824:824:824) (935:935:935)) - (PORT datab (938:938:938) (1037:1037:1037)) - (PORT datac (757:757:757) (875:875:875)) - (PORT datad (764:764:764) (875:875:875)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT datab (310:310:310) (407:407:407)) + (PORT datac (953:953:953) (1042:1042:1042)) + (PORT datad (1132:1132:1132) (1222:1222:1222)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -37676,13 +30785,29 @@ (INSTANCE ula_\|zx_keyboard_\|WideOr16\~7) (DELAY (ABSOLUTE - (PORT dataa (232:232:232) (279:279:279)) - (PORT datab (941:941:941) (1039:1039:1039)) - (PORT datac (311:311:311) (337:337:337)) - (PORT datad (1387:1387:1387) (1504:1504:1504)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (995:995:995) (1078:1078:1078)) + (PORT datab (200:200:200) (239:239:239)) + (PORT datac (328:328:328) (353:353:353)) + (PORT datad (946:946:946) (1017:1017:1017)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr16\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1158:1158:1158) (1264:1264:1264)) + (PORT datab (315:315:315) (413:413:413)) + (PORT datac (960:960:960) (1044:1044:1044)) + (PORT datad (945:945:945) (1017:1017:1017)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -37692,10 +30817,10 @@ (INSTANCE ula_\|zx_keyboard_\|WideOr16\~6) (DELAY (ABSOLUTE - (PORT dataa (1416:1416:1416) (1544:1544:1544)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (932:932:932) (1003:1003:1003)) - (PORT datad (517:517:517) (528:528:528)) + (PORT dataa (1047:1047:1047) (1139:1139:1139)) + (PORT datab (200:200:200) (240:240:240)) + (PORT datac (957:957:957) (1042:1042:1042)) + (PORT datad (355:355:355) (386:386:386)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -37705,14 +30830,30 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~46) + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~43) (DELAY (ABSOLUTE - (PORT dataa (376:376:376) (398:398:398)) - (PORT datab (274:274:274) (359:359:359)) - (PORT datad (604:604:604) (617:617:617)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (336:336:336) (332:332:332)) + (PORT dataa (512:512:512) (589:589:589)) + (PORT datab (319:319:319) (414:414:414)) + (PORT datac (465:465:465) (559:559:559)) + (PORT datad (1192:1192:1192) (1259:1259:1259)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]\~44) + (DELAY + (ABSOLUTE + (PORT dataa (411:411:411) (441:441:441)) + (PORT datab (609:609:609) (638:638:638)) + (PORT datad (1081:1081:1081) (1131:1131:1131)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -37723,9 +30864,9 @@ (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[1\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1544:1544:1544)) + (PORT clk (1519:1519:1519) (1533:1533:1533)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) + (PORT clrn (1560:1560:1560) (1552:1552:1552)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -37736,602 +30877,45 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~31) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[15\]\~15) (DELAY (ABSOLUTE - (PORT dataa (1387:1387:1387) (1447:1447:1447)) - (PORT datab (411:411:411) (471:471:471)) - (PORT datac (1375:1375:1375) (1408:1408:1408)) - (PORT datad (583:583:583) (631:631:631)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (784:784:784) (804:804:804)) - (PORT datab (3348:3348:3348) (3488:3488:3488)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (1705:1705:1705) (1713:1713:1713)) - (PORT datab (1225:1225:1225) (1301:1301:1301)) - (PORT datac (636:636:636) (675:675:675)) - (PORT datad (1144:1144:1144) (1160:1160:1160)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~34) - (DELAY - (ABSOLUTE - (PORT dataa (1504:1504:1504) (1628:1628:1628)) - (PORT datab (1226:1226:1226) (1302:1302:1302)) - (PORT datac (171:171:171) (203:203:203)) - (PORT datad (1240:1240:1240) (1368:1368:1368)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[1\]) - (DELAY - (ABSOLUTE - (PORT dataa (970:970:970) (1042:1042:1042)) - (PORT datab (636:636:636) (676:676:676)) - (PORT datac (240:240:240) (293:293:293)) - (PORT datad (1667:1667:1667) (1728:1728:1728)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1526:1526:1526) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (841:841:841) (846:846:846)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[1\]\~10) - (DELAY - (ABSOLUTE - (PORT datab (912:912:912) (931:931:931)) - (PORT datac (945:945:945) (986:986:986)) - (PORT datad (219:219:219) (254:254:254)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[1\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (253:253:253) (310:310:310)) - (PORT datab (705:705:705) (769:769:769)) - (PORT datac (170:170:170) (203:203:203)) - (PORT datad (208:208:208) (240:240:240)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|ir_\|opcode\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (195:195:195) (220:220:220)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1521:1521:1521) (1534:1534:1534)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1557:1557:1557)) - (PORT ena (1231:1231:1231) (1217:1217:1217)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal40\~0) - (DELAY - (ABSOLUTE - (PORT dataa (284:284:284) (380:380:380)) - (PORT datac (903:903:903) (966:966:966)) - (PORT datad (928:928:928) (982:982:982)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal21\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1410:1410:1410) (1521:1521:1521)) - (PORT datab (897:897:897) (911:911:911)) - (PORT datac (924:924:924) (1011:1011:1011)) - (PORT datad (876:876:876) (894:894:894)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~26) - (DELAY - (ABSOLUTE - (PORT dataa (1572:1572:1572) (1710:1710:1710)) - (PORT datab (2337:2337:2337) (2410:2410:2410)) - (PORT datac (671:671:671) (718:718:718)) - (PORT datad (2748:2748:2748) (2873:2873:2873)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~28) - (DELAY - (ABSOLUTE - (PORT dataa (207:207:207) (253:253:253)) - (PORT datab (232:232:232) (283:283:283)) - (PORT datac (195:195:195) (238:238:238)) - (PORT datad (371:371:371) (399:399:399)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~3) - (DELAY - (ABSOLUTE - (PORT dataa (626:626:626) (658:658:658)) - (PORT datab (427:427:427) (471:471:471)) - (PORT datac (543:543:543) (559:559:559)) - (PORT datad (1164:1164:1164) (1218:1218:1218)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1490:1490:1490) (1592:1592:1592)) - (PORT datab (438:438:438) (474:474:474)) - (PORT datac (943:943:943) (994:994:994)) - (PORT datad (211:211:211) (243:243:243)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~5) - (DELAY - (ABSOLUTE - (PORT dataa (974:974:974) (1047:1047:1047)) - (PORT datab (1110:1110:1110) (1179:1179:1179)) - (PORT datac (1261:1261:1261) (1313:1313:1313)) - (PORT datad (1359:1359:1359) (1384:1384:1384)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~6) - (DELAY - (ABSOLUTE - (PORT dataa (1101:1101:1101) (1122:1122:1122)) - (PORT datab (961:961:961) (1050:1050:1050)) - (PORT datac (1264:1264:1264) (1310:1310:1310)) - (PORT datad (1206:1206:1206) (1270:1270:1270)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1505:1505:1505) (1526:1526:1526)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (868:868:868) (865:865:865)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~4) - (DELAY - (ABSOLUTE - (PORT dataa (1606:1606:1606) (1627:1627:1627)) - (PORT datab (831:831:831) (859:859:859)) - (PORT datad (1029:1029:1029) (1028:1028:1028)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1568:1568:1568) (1597:1597:1597)) + (PORT dataa (1432:1432:1432) (1481:1481:1481)) (PORT datab (197:197:197) (236:236:236)) - (PORT datac (643:643:643) (684:684:684)) - (PORT datad (555:555:555) (558:558:558)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~9) - (DELAY - (ABSOLUTE - (PORT dataa (622:622:622) (650:650:650)) - (PORT datab (552:552:552) (565:565:565)) - (PORT datac (194:194:194) (227:227:227)) - (PORT datad (372:372:372) (397:397:397)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~21) - (DELAY - (ABSOLUTE - (PORT dataa (2257:2257:2257) (2337:2337:2337)) - (PORT datab (1549:1549:1549) (1673:1673:1673)) - (PORT datac (902:902:902) (922:922:922)) - (PORT datad (1165:1165:1165) (1178:1178:1178)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~12) - (DELAY - (ABSOLUTE - (PORT datab (230:230:230) (277:277:277)) - (PORT datac (343:343:343) (365:365:365)) - (PORT datad (369:369:369) (394:394:394)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1298:1298:1298) (1395:1395:1395)) - (PORT datab (927:927:927) (974:974:974)) - (PORT datac (1940:1940:1940) (2070:2070:2070)) - (PORT datad (2052:2052:2052) (2214:2214:2214)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~11) - (DELAY - (ABSOLUTE - (PORT dataa (855:855:855) (906:906:906)) - (PORT datab (230:230:230) (277:277:277)) - (PORT datac (196:196:196) (240:240:240)) - (PORT datad (370:370:370) (394:394:394)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~13) - (DELAY - (ABSOLUTE - (PORT dataa (1155:1155:1155) (1167:1167:1167)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (173:173:173) (206:206:206)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~17) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (255:255:255)) - (PORT datab (222:222:222) (268:268:268)) - (PORT datac (200:200:200) (236:236:236)) - (PORT datad (223:223:223) (250:250:250)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_alu_op_low\~32) - (DELAY - (ABSOLUTE - (PORT dataa (1938:1938:1938) (2062:2062:2062)) - (PORT datab (2594:2594:2594) (2695:2695:2695)) - (PORT datad (1436:1436:1436) (1528:1528:1528)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~15) - (DELAY - (ABSOLUTE - (PORT dataa (666:666:666) (720:720:720)) - (PORT datab (699:699:699) (758:758:758)) - (PORT datac (1095:1095:1095) (1090:1090:1090)) - (PORT datad (644:644:644) (692:692:692)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~16) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (254:254:254)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (611:611:611) (632:632:632)) - (PORT datad (777:777:777) (789:789:789)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~18) - (DELAY - (ABSOLUTE - (PORT dataa (845:845:845) (890:890:890)) - (PORT datab (332:332:332) (362:362:362)) - (PORT datac (372:372:372) (397:397:397)) - (PORT datad (604:604:604) (626:626:626)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~19) - (DELAY - (ABSOLUTE - (PORT dataa (1811:1811:1811) (1903:1903:1903)) - (PORT datab (921:921:921) (989:989:989)) - (PORT datac (923:923:923) (1008:1008:1008)) - (PORT datad (436:436:436) (468:468:468)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (929:929:929) (966:966:966)) - (PORT datac (902:902:902) (921:921:921)) - (PORT datad (1383:1383:1383) (1455:1455:1455)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~1) - (DELAY - (ABSOLUTE - (PORT dataa (418:418:418) (444:444:444)) - (PORT datac (192:192:192) (225:225:225)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1154:1154:1154) (1242:1242:1242)) - (PORT datab (196:196:196) (236:236:236)) - (PORT datac (593:593:593) (604:604:604)) - (PORT datad (376:376:376) (396:396:396)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1155:1155:1155) (1240:1240:1240)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datad (877:877:877) (932:932:932)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) + (PORT datad (194:194:194) (220:220:220)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|alu_flags_\|DFFE_inst_latch_cf2) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[15\]) (DELAY (ABSOLUTE - (PORT clk (1511:1511:1511) (1525:1525:1525)) + (PORT clk (1523:1523:1523) (1527:1527:1527)) (PORT d (74:74:74) (91:91:91)) + (PORT asdata (720:720:720) (784:784:784)) + (PORT sload (2032:2032:2032) (2084:2084:2084)) + (PORT ena (2298:2298:2298) (2265:2265:2265)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~10) + (INSTANCE z80_\|address_pins_\|abus\[15\]\~22) (DELAY (ABSOLUTE - (PORT dataa (2446:2446:2446) (2535:2535:2535)) - (PORT datab (1615:1615:1615) (1728:1728:1728)) - (PORT datac (1769:1769:1769) (1897:1897:1897)) - (PORT datad (1666:1666:1666) (1684:1684:1684)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (310:310:310)) + (PORT datac (2760:2760:2760) (2950:2950:2950)) + (PORT datad (1406:1406:1406) (1489:1489:1489)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -38339,77 +30923,31 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~11) + (INSTANCE D\[1\]\~29) (DELAY (ABSOLUTE - (PORT dataa (1432:1432:1432) (1515:1515:1515)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (1052:1052:1052) (1100:1100:1100)) - (PORT datad (1335:1335:1335) (1356:1356:1356)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1121:1121:1121) (1241:1241:1241)) - (PORT datac (884:884:884) (939:939:939)) - (PORT datad (957:957:957) (1022:1022:1022)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~9) - (DELAY - (ABSOLUTE - (PORT dataa (903:903:903) (935:935:935)) - (PORT datab (944:944:944) (1021:1021:1021)) - (PORT datac (588:588:588) (603:603:603)) - (PORT datad (537:537:537) (536:536:536)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_use_cf2\~12) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (838:838:838) (860:860:860)) - (PORT datac (169:169:169) (202:202:202)) - (PORT datad (195:195:195) (228:228:228)) + (PORT dataa (1387:1387:1387) (1514:1514:1514)) + (PORT datab (887:887:887) (932:932:932)) + (PORT datac (647:647:647) (708:708:708)) + (PORT datad (602:602:602) (621:621:621)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~14) + (INSTANCE D\[1\]\~30) (DELAY (ABSOLUTE - (PORT dataa (1156:1156:1156) (1255:1255:1255)) - (PORT datab (257:257:257) (345:345:345)) - (PORT datac (214:214:214) (290:290:290)) - (PORT datad (580:580:580) (615:615:615)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) + (PORT dataa (1020:1020:1020) (1076:1076:1076)) + (PORT datab (365:365:365) (385:385:385)) + (PORT datac (2860:2860:2860) (3133:3133:3133)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -38417,63 +30955,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_0\~20) + (INSTANCE ExtRamWE\~0) (DELAY (ABSOLUTE - (PORT dataa (572:572:572) (607:607:607)) - (PORT datab (199:199:199) (239:239:239)) - (PORT datac (590:590:590) (613:613:613)) - (PORT datad (600:600:600) (615:615:615)) - (IOPATH dataa combout (354:354:354) (367:367:367)) + (PORT dataa (247:247:247) (305:305:305)) + (PORT datab (2796:2796:2796) (2991:2991:2991)) + (PORT datac (551:551:551) (572:572:572)) + (PORT datad (604:604:604) (624:624:624)) + (IOPATH dataa combout (325:325:325) (320:320:320)) (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~10) - (DELAY - (ABSOLUTE - (PORT dataa (1561:1561:1561) (1706:1706:1706)) - (PORT datab (2568:2568:2568) (2670:2670:2670)) - (PORT datac (1057:1057:1057) (1083:1083:1083)) - (PORT datad (862:862:862) (898:898:898)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1089:1089:1089) (1120:1120:1120)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (1186:1186:1186) (1228:1228:1228)) - (PORT datad (564:564:564) (579:579:579)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~5) - (DELAY - (ABSOLUTE - (PORT dataa (911:911:911) (920:920:920)) - (PORT datab (219:219:219) (258:258:258)) - (PORT datac (237:237:237) (278:278:278)) - (PORT datad (594:594:594) (611:611:611)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -38481,4348 +30971,121 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~6) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode236w\[2\]) (DELAY (ABSOLUTE - (PORT dataa (948:948:948) (1036:1036:1036)) - (PORT datab (263:263:263) (310:310:310)) - (PORT datac (1393:1393:1393) (1475:1475:1475)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~7) - (DELAY - (ABSOLUTE - (PORT dataa (923:923:923) (950:950:950)) - (PORT datab (1129:1129:1129) (1199:1199:1199)) - (PORT datac (889:889:889) (932:932:932)) - (PORT datad (1015:1015:1015) (1011:1011:1011)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_set\~0) - (DELAY - (ABSOLUTE - (PORT dataa (477:477:477) (514:514:514)) - (PORT datab (896:896:896) (914:914:914)) - (PORT datac (922:922:922) (1007:1007:1007)) - (PORT datad (405:405:405) (434:434:434)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~4) - (DELAY - (ABSOLUTE - (PORT datab (1062:1062:1062) (1088:1088:1088)) - (PORT datac (208:208:208) (250:250:250)) - (PORT datad (209:209:209) (241:241:241)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf_cpl\~9) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (524:524:524) (539:539:539)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_flags_\|flags_cf) - (DELAY - (ABSOLUTE - (PORT dataa (198:198:198) (240:240:240)) - (PORT datab (594:594:594) (613:613:613)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (567:567:567) (592:592:592)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[0\]\~8) - (DELAY - (ABSOLUTE - (PORT dataa (694:694:694) (746:746:746)) - (PORT datab (661:661:661) (721:721:721)) - (PORT datac (883:883:883) (903:903:903)) - (PORT datad (893:893:893) (916:916:916)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sw2_\|db_up\[0\]\~0) - (DELAY - (ABSOLUTE - (PORT datac (1154:1154:1154) (1188:1188:1188)) - (PORT datad (629:629:629) (643:643:643)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[0\]\~9) - (DELAY - (ABSOLUTE - (PORT dataa (384:384:384) (408:408:408)) - (PORT datab (644:644:644) (678:678:678)) - (PORT datac (871:871:871) (896:896:896)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[0\]\~12) - (DELAY - (ABSOLUTE - (PORT dataa (701:701:701) (721:721:721)) - (PORT datab (956:956:956) (981:981:981)) - (PORT datac (172:172:172) (206:206:206)) - (PORT datad (217:217:217) (250:250:250)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~67) - (DELAY - (ABSOLUTE - (PORT dataa (688:688:688) (772:772:772)) - (PORT datac (1115:1115:1115) (1160:1160:1160)) - (PORT datad (739:739:739) (827:827:827)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~81) - (DELAY - (ABSOLUTE - (PORT dataa (785:785:785) (871:871:871)) - (PORT datab (725:725:725) (810:810:810)) - (PORT datac (1118:1118:1118) (1161:1161:1161)) - (PORT datad (711:711:711) (788:788:788)) - (IOPATH dataa combout (341:341:341) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~82) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (246:246:246)) - (PORT datab (915:915:915) (989:989:989)) - (PORT datac (1116:1116:1116) (1162:1162:1162)) - (PORT datad (329:329:329) (349:349:349)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~83) - (DELAY - (ABSOLUTE - (PORT dataa (212:212:212) (261:261:261)) - (PORT datab (199:199:199) (239:239:239)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~84) - (DELAY - (ABSOLUTE - (PORT dataa (727:727:727) (814:814:814)) - (PORT datab (981:981:981) (1068:1068:1068)) - (PORT datac (722:722:722) (831:831:831)) - (PORT datad (729:729:729) (835:835:835)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~85) - (DELAY - (ABSOLUTE - (PORT dataa (792:792:792) (903:903:903)) - (PORT datab (736:736:736) (834:834:834)) - (PORT datac (710:710:710) (811:811:811)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~86) - (DELAY - (ABSOLUTE - (PORT dataa (351:351:351) (390:390:390)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datad (338:338:338) (357:357:357)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1573:1573:1573)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~49) - (DELAY - (ABSOLUTE - (PORT dataa (1159:1159:1159) (1230:1230:1230)) - (PORT datab (724:724:724) (793:793:793)) - (PORT datac (214:214:214) (291:291:291)) - (PORT datad (550:550:550) (572:572:572)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (949:949:949) (1028:1028:1028)) - (PORT datab (779:779:779) (879:879:879)) - (PORT datac (1365:1365:1365) (1458:1458:1458)) - (PORT datad (1189:1189:1189) (1251:1251:1251)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\~76) - (DELAY - (ABSOLUTE - (PORT dataa (345:345:345) (382:382:382)) - (PORT datab (281:281:281) (364:364:364)) - (PORT datac (928:928:928) (975:975:975)) - (PORT datad (1494:1494:1494) (1585:1585:1585)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~73) - (DELAY - (ABSOLUTE - (PORT datac (740:740:740) (842:842:842)) - (PORT datad (1190:1190:1190) (1255:1255:1255)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~47) - (DELAY - (ABSOLUTE - (PORT dataa (782:782:782) (872:872:872)) - (PORT datab (728:728:728) (815:815:815)) - (PORT datac (884:884:884) (953:953:953)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (751:751:751) (844:844:844)) - (PORT datab (1502:1502:1502) (1605:1605:1605)) - (PORT datac (916:916:916) (991:991:991)) - (PORT datad (852:852:852) (919:919:919)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\~74) - (DELAY - (ABSOLUTE - (PORT dataa (588:588:588) (610:610:610)) - (PORT datab (344:344:344) (369:369:369)) - (PORT datac (1366:1366:1366) (1452:1452:1452)) - (PORT datad (1547:1547:1547) (1637:1637:1637)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~75) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (245:245:245)) - (PORT datab (201:201:201) (241:241:241)) - (PORT datac (448:448:448) (513:513:513)) - (PORT datad (841:841:841) (864:864:864)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~77) - (DELAY - (ABSOLUTE - (PORT dataa (556:556:556) (571:571:571)) - (PORT datab (335:335:335) (364:364:364)) - (PORT datad (736:736:736) (824:824:824)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]\~71) - (DELAY - (ABSOLUTE - (PORT dataa (758:758:758) (862:862:862)) - (PORT datab (729:729:729) (828:828:828)) - (PORT datac (335:335:335) (363:363:363)) - (PORT datad (1132:1132:1132) (1201:1201:1201)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]\~72) - (DELAY - (ABSOLUTE - (PORT datab (199:199:199) (239:239:239)) - (PORT datad (718:718:718) (814:814:814)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~47) - (DELAY - (ABSOLUTE - (PORT dataa (384:384:384) (455:455:455)) - (PORT datab (1124:1124:1124) (1199:1199:1199)) - (PORT datac (636:636:636) (698:698:698)) - (PORT datad (629:629:629) (680:680:680)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[0\]\~80) - (DELAY - (ABSOLUTE - (PORT dataa (1557:1557:1557) (1665:1665:1665)) - (PORT datab (981:981:981) (1035:1035:1035)) - (PORT datad (515:515:515) (529:529:529)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]\~78) - (DELAY - (ABSOLUTE - (PORT dataa (489:489:489) (569:569:569)) - (PORT datac (607:607:607) (672:672:672)) - (PORT datad (260:260:260) (335:335:335)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]\~79) - (DELAY - (ABSOLUTE - (PORT dataa (404:404:404) (428:428:428)) - (PORT datab (848:848:848) (850:850:850)) - (PORT datad (734:734:734) (821:821:821)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|key_row\~1) - (DELAY - (ABSOLUTE - (PORT datab (1472:1472:1472) (1607:1607:1607)) - (PORT datac (347:347:347) (411:411:411)) - (PORT datad (901:901:901) (962:962:962)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~48) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (220:220:220) (260:260:260)) - (PORT datac (215:215:215) (291:291:291)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|shifted\~1) - (DELAY - (ABSOLUTE - (PORT datac (1076:1076:1076) (1171:1171:1171)) - (PORT datad (1031:1031:1031) (1115:1115:1115)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~90) - (DELAY - (ABSOLUTE - (PORT dataa (1413:1413:1413) (1543:1543:1543)) - (PORT datab (788:788:788) (903:903:903)) - (PORT datac (960:960:960) (1037:1037:1037)) - (PORT datad (777:777:777) (882:882:882)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~91) - (DELAY - (ABSOLUTE - (PORT dataa (209:209:209) (256:256:256)) - (PORT datab (675:675:675) (704:704:704)) - (PORT datac (604:604:604) (622:622:622)) - (PORT datad (901:901:901) (976:976:976)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~92) - (DELAY - (ABSOLUTE - (PORT datab (968:968:968) (1057:1057:1057)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~63) - (DELAY - (ABSOLUTE - (PORT datac (654:654:654) (724:724:724)) - (PORT datad (637:637:637) (707:707:707)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|WideOr16\~3) - (DELAY - (ABSOLUTE - (PORT datab (654:654:654) (726:726:726)) - (PORT datac (693:693:693) (782:782:782)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~87) - (DELAY - (ABSOLUTE - (PORT dataa (210:210:210) (258:258:258)) - (PORT datab (473:473:473) (549:549:549)) - (PORT datac (637:637:637) (704:704:704)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~132) - (DELAY - (ABSOLUTE - (PORT dataa (230:230:230) (277:277:277)) - (PORT datab (665:665:665) (741:741:741)) - (PORT datad (650:650:650) (727:727:727)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~88) - (DELAY - (ABSOLUTE - (PORT dataa (861:861:861) (926:926:926)) - (PORT datab (223:223:223) (262:262:262)) - (PORT datac (337:337:337) (360:360:360)) - (PORT datad (543:543:543) (562:562:562)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~89) - (DELAY - (ABSOLUTE - (PORT dataa (815:815:815) (820:820:820)) - (PORT datad (946:946:946) (995:995:995)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~50) - (DELAY - (ABSOLUTE - (PORT dataa (1387:1387:1387) (1444:1444:1444)) - (PORT datab (598:598:598) (652:652:652)) - (PORT datac (1375:1375:1375) (1406:1406:1406)) - (PORT datad (218:218:218) (287:287:287)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~51) - (DELAY - (ABSOLUTE - (PORT dataa (784:784:784) (804:804:804)) - (PORT datab (3349:3349:3349) (3490:3490:3490)) - (PORT datac (171:171:171) (205:205:205)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (891:891:891) (902:902:902)) - (PORT clk (1860:1860:1860) (1887:1887:1887)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1236:1236:1236) (1280:1280:1280)) - (PORT d[1] (983:983:983) (1045:1045:1045)) - (PORT d[2] (962:962:962) (977:977:977)) - (PORT d[3] (1021:1021:1021) (1074:1074:1074)) - (PORT d[4] (2601:2601:2601) (2818:2818:2818)) - (PORT d[5] (1028:1028:1028) (1063:1063:1063)) - (PORT d[6] (994:994:994) (1056:1056:1056)) - (PORT d[7] (954:954:954) (1016:1016:1016)) - (PORT d[8] (1046:1046:1046) (1093:1093:1093)) - (PORT d[9] (998:998:998) (1055:1055:1055)) - (PORT d[10] (1047:1047:1047) (1121:1121:1121)) - (PORT d[11] (2576:2576:2576) (2762:2762:2762)) - (PORT d[12] (1307:1307:1307) (1386:1386:1386)) - (PORT clk (1857:1857:1857) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (951:951:951) (911:911:911)) - (PORT clk (1857:1857:1857) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (PORT d[0] (1484:1484:1484) (1455:1455:1455)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1820:1820:1820) (1846:1846:1846)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (980:980:980) (991:991:991)) - (PORT clk (1860:1860:1860) (1887:1887:1887)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (706:706:706) (727:727:727)) - (PORT d[1] (2392:2392:2392) (2624:2624:2624)) - (PORT d[2] (1503:1503:1503) (1540:1540:1540)) - (PORT d[3] (981:981:981) (1040:1040:1040)) - (PORT d[4] (2591:2591:2591) (2807:2807:2807)) - (PORT d[5] (3468:3468:3468) (3668:3668:3668)) - (PORT d[6] (1271:1271:1271) (1334:1334:1334)) - (PORT d[7] (3191:3191:3191) (3366:3366:3366)) - (PORT d[8] (691:691:691) (713:713:713)) - (PORT d[9] (1603:1603:1603) (1661:1661:1661)) - (PORT d[10] (1346:1346:1346) (1434:1434:1434)) - (PORT d[11] (2230:2230:2230) (2413:2413:2413)) - (PORT d[12] (1570:1570:1570) (1649:1649:1649)) - (PORT clk (1857:1857:1857) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (671:671:671) (627:627:627)) - (PORT clk (1857:1857:1857) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (PORT d[0] (1485:1485:1485) (1441:1441:1441)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1888:1888:1888)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1820:1820:1820) (1846:1846:1846)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1010:1010:1010)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1101:1101:1101) (1111:1111:1111)) - (PORT clk (1859:1859:1859) (1886:1886:1886)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (986:986:986) (1014:1014:1014)) - (PORT d[1] (3450:3450:3450) (3742:3742:3742)) - (PORT d[2] (1249:1249:1249) (1290:1290:1290)) - (PORT d[3] (1284:1284:1284) (1331:1331:1331)) - (PORT d[4] (2575:2575:2575) (2806:2806:2806)) - (PORT d[5] (3485:3485:3485) (3709:3709:3709)) - (PORT d[6] (1317:1317:1317) (1415:1415:1415)) - (PORT d[7] (1218:1218:1218) (1279:1279:1279)) - (PORT d[8] (1003:1003:1003) (1027:1027:1027)) - (PORT d[9] (1567:1567:1567) (1623:1623:1623)) - (PORT d[10] (1356:1356:1356) (1454:1454:1454)) - (PORT d[11] (2251:2251:2251) (2436:2436:2436)) - (PORT d[12] (1606:1606:1606) (1702:1702:1702)) - (PORT clk (1856:1856:1856) (1882:1882:1882)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (963:963:963) (919:919:919)) - (PORT clk (1856:1856:1856) (1882:1882:1882)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1859:1859:1859) (1886:1886:1886)) - (PORT d[0] (1702:1702:1702) (1655:1655:1655)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1887:1887:1887)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1819:1819:1819) (1845:1845:1845)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1004:1004:1004) (1008:1008:1008)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~55) - (DELAY - (ABSOLUTE - (PORT dataa (374:374:374) (409:409:409)) - (PORT datab (686:686:686) (752:752:752)) - (PORT datac (651:651:651) (716:716:716)) - (PORT datad (645:645:645) (655:655:655)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (325:325:325)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1183:1183:1183) (1208:1208:1208)) - (PORT clk (1850:1850:1850) (1878:1878:1878)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3642:3642:3642) (3824:3824:3824)) - (PORT d[1] (1366:1366:1366) (1493:1493:1493)) - (PORT d[2] (2003:2003:2003) (2099:2099:2099)) - (PORT d[3] (2459:2459:2459) (2585:2585:2585)) - (PORT d[4] (2200:2200:2200) (2332:2332:2332)) - (PORT d[5] (1345:1345:1345) (1450:1450:1450)) - (PORT d[6] (1456:1456:1456) (1487:1487:1487)) - (PORT d[7] (3346:3346:3346) (3494:3494:3494)) - (PORT d[8] (3607:3607:3607) (3856:3856:3856)) - (PORT d[9] (3167:3167:3167) (3306:3306:3306)) - (PORT d[10] (3154:3154:3154) (3327:3327:3327)) - (PORT d[11] (1793:1793:1793) (1891:1891:1891)) - (PORT d[12] (1416:1416:1416) (1454:1454:1454)) - (PORT clk (1847:1847:1847) (1874:1874:1874)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1620:1620:1620) (1580:1580:1580)) - (PORT clk (1847:1847:1847) (1874:1874:1874)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1878:1878:1878)) - (PORT d[0] (2766:2766:2766) (2809:2809:2809)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1879:1879:1879)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1879:1879:1879)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1879:1879:1879)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1879:1879:1879)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1810:1810:1810) (1837:1837:1837)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (995:995:995) (1000:1000:1000)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~56) - (DELAY - (ABSOLUTE - (PORT dataa (1047:1047:1047) (1075:1075:1075)) - (PORT datab (1410:1410:1410) (1504:1504:1504)) - (PORT datac (532:532:532) (545:545:545)) - (PORT datad (1173:1173:1173) (1173:1173:1173)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1641:1641:1641) (1729:1729:1729)) - (PORT clk (1857:1857:1857) (1885:1885:1885)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2872:2872:2872) (2966:2966:2966)) - (PORT d[1] (2017:2017:2017) (2182:2182:2182)) - (PORT d[2] (1954:1954:1954) (2061:2061:2061)) - (PORT d[3] (1897:1897:1897) (2022:2022:2022)) - (PORT d[4] (3021:3021:3021) (3172:3172:3172)) - (PORT d[5] (2229:2229:2229) (2391:2391:2391)) - (PORT d[6] (1711:1711:1711) (1774:1774:1774)) - (PORT d[7] (2133:2133:2133) (2250:2250:2250)) - (PORT d[8] (2427:2427:2427) (2610:2610:2610)) - (PORT d[9] (1679:1679:1679) (1785:1785:1785)) - (PORT d[10] (1442:1442:1442) (1508:1508:1508)) - (PORT d[11] (1723:1723:1723) (1780:1780:1780)) - (PORT d[12] (2286:2286:2286) (2347:2347:2347)) - (PORT clk (1854:1854:1854) (1881:1881:1881)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2567:2567:2567) (2620:2620:2620)) - (PORT clk (1854:1854:1854) (1881:1881:1881)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1885:1885:1885)) - (PORT d[0] (3733:3733:3733) (3648:3648:3648)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1886:1886:1886)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1886:1886:1886)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1886:1886:1886)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1886:1886:1886)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1812:1812:1812) (1810:1810:1810)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2034:2034:2034) (2028:2028:2028)) - (PORT clk (1822:1822:1822) (1816:1816:1816)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4393:4393:4393) (4461:4461:4461)) - (PORT d[1] (4131:4131:4131) (4181:4181:4181)) - (PORT d[2] (4247:4247:4247) (4323:4323:4323)) - (PORT d[3] (4546:4546:4546) (4614:4614:4614)) - (PORT d[4] (4322:4322:4322) (4309:4309:4309)) - (PORT d[5] (4617:4617:4617) (4651:4651:4651)) - (PORT d[6] (4408:4408:4408) (4485:4485:4485)) - (PORT d[7] (4302:4302:4302) (4274:4274:4274)) - (PORT d[8] (4572:4572:4572) (4637:4637:4637)) - (PORT d[9] (4446:4446:4446) (4691:4691:4691)) - (PORT d[10] (4705:4705:4705) (4743:4743:4743)) - (PORT d[11] (4358:4358:4358) (4390:4390:4390)) - (PORT d[12] (4507:4507:4507) (4645:4645:4645)) - (PORT clk (1818:1818:1818) (1812:1812:1812)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1822:1822:1822) (1816:1816:1816)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1823:1823:1823) (1817:1817:1817)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1823:1823:1823) (1817:1817:1817)) - (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1823:1823:1823) (1817:1817:1817)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1823:1823:1823) (1817:1817:1817)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1814:1814:1814) (1812:1812:1812)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2840:2840:2840) (2949:2949:2949)) - (PORT d[1] (1732:1732:1732) (1897:1897:1897)) - (PORT d[2] (1932:1932:1932) (2053:2053:2053)) - (PORT d[3] (1899:1899:1899) (2019:2019:2019)) - (PORT d[4] (2772:2772:2772) (2916:2916:2916)) - (PORT d[5] (2232:2232:2232) (2415:2415:2415)) - (PORT d[6] (2007:2007:2007) (2069:2069:2069)) - (PORT d[7] (2130:2130:2130) (2260:2260:2260)) - (PORT d[8] (2390:2390:2390) (2571:2571:2571)) - (PORT d[9] (1959:1959:1959) (2082:2082:2082)) - (PORT d[10] (1985:1985:1985) (2067:2067:2067)) - (PORT d[11] (2017:2017:2017) (2091:2091:2091)) - (PORT d[12] (2566:2566:2566) (2656:2656:2656)) - (PORT clk (1859:1859:1859) (1884:1884:1884)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1859:1859:1859) (1884:1884:1884)) - (PORT d[0] (2730:2730:2730) (2796:2796:2796)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1885:1885:1885)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1822:1822:1822) (1847:1847:1847)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1007:1007:1007) (1010:1010:1010)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1008:1008:1008) (1011:1011:1011)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1008:1008:1008) (1011:1011:1011)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1008:1008:1008) (1011:1011:1011)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1622:1622:1622) (1706:1706:1706)) - (PORT clk (1855:1855:1855) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2870:2870:2870) (2964:2964:2964)) - (PORT d[1] (2048:2048:2048) (2231:2231:2231)) - (PORT d[2] (1893:1893:1893) (1990:1990:1990)) - (PORT d[3] (1883:1883:1883) (2014:2014:2014)) - (PORT d[4] (3037:3037:3037) (3174:3174:3174)) - (PORT d[5] (1957:1957:1957) (2122:2122:2122)) - (PORT d[6] (1728:1728:1728) (1783:1783:1783)) - (PORT d[7] (1821:1821:1821) (1856:1856:1856)) - (PORT d[8] (2421:2421:2421) (2612:2612:2612)) - (PORT d[9] (1968:1968:1968) (2080:2080:2080)) - (PORT d[10] (2002:2002:2002) (2089:2089:2089)) - (PORT d[11] (2528:2528:2528) (2597:2597:2597)) - (PORT d[12] (2240:2240:2240) (2309:2309:2309)) - (PORT clk (1852:1852:1852) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2519:2519:2519) (2503:2503:2503)) - (PORT clk (1852:1852:1852) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1855:1855:1855) (1883:1883:1883)) - (PORT d[0] (3674:3674:3674) (3756:3756:3756)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1810:1810:1810) (1808:1808:1808)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2034:2034:2034) (2023:2023:2023)) - (PORT clk (1820:1820:1820) (1814:1814:1814)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4437:4437:4437) (4508:4508:4508)) - (PORT d[1] (4211:4211:4211) (4251:4251:4251)) - (PORT d[2] (4278:4278:4278) (4341:4341:4341)) - (PORT d[3] (4543:4543:4543) (4609:4609:4609)) - (PORT d[4] (4346:4346:4346) (4342:4342:4342)) - (PORT d[5] (4610:4610:4610) (4641:4641:4641)) - (PORT d[6] (4708:4708:4708) (4757:4757:4757)) - (PORT d[7] (4312:4312:4312) (4268:4268:4268)) - (PORT d[8] (4489:4489:4489) (4504:4504:4504)) - (PORT d[9] (4453:4453:4453) (4722:4722:4722)) - (PORT d[10] (4622:4622:4622) (4654:4654:4654)) - (PORT d[11] (4366:4366:4366) (4392:4392:4392)) - (PORT d[12] (4506:4506:4506) (4645:4645:4645)) - (PORT clk (1816:1816:1816) (1810:1810:1810)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1820:1820:1820) (1814:1814:1814)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1821:1821:1821) (1815:1815:1815)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1821:1821:1821) (1815:1815:1815)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1821:1821:1821) (1815:1815:1815)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1821:1821:1821) (1815:1815:1815)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~52) - (DELAY - (ABSOLUTE - (PORT dataa (1206:1206:1206) (1287:1287:1287)) - (PORT datab (1437:1437:1437) (1489:1489:1489)) - (PORT datac (1126:1126:1126) (1177:1177:1177)) - (PORT datad (1429:1429:1429) (1485:1485:1485)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3633:3633:3633) (3814:3814:3814)) - (PORT d[1] (2642:2642:2642) (2867:2867:2867)) - (PORT d[2] (1648:1648:1648) (1726:1726:1726)) - (PORT d[3] (2160:2160:2160) (2263:2263:2263)) - (PORT d[4] (2162:2162:2162) (2254:2254:2254)) - (PORT d[5] (1662:1662:1662) (1786:1786:1786)) - (PORT d[6] (1132:1132:1132) (1171:1171:1171)) - (PORT d[7] (1160:1160:1160) (1190:1190:1190)) - (PORT d[8] (2171:2171:2171) (2353:2353:2353)) - (PORT d[9] (2266:2266:2266) (2413:2413:2413)) - (PORT d[10] (2562:2562:2562) (2693:2693:2693)) - (PORT d[11] (915:915:915) (961:961:961)) - (PORT d[12] (1750:1750:1750) (1775:1775:1775)) - (PORT clk (1847:1847:1847) (1874:1874:1874)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1847:1847:1847) (1874:1874:1874)) - (PORT d[0] (3453:3453:3453) (3330:3330:3330)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1875:1875:1875)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1810:1810:1810) (1837:1837:1837)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (995:995:995) (1000:1000:1000)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~53) - (DELAY - (ABSOLUTE - (PORT dataa (1208:1208:1208) (1217:1217:1217)) - (PORT datab (1079:1079:1079) (1088:1088:1088)) - (PORT datac (181:181:181) (219:219:219)) - (PORT datad (1384:1384:1384) (1408:1408:1408)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~54) - (DELAY - (ABSOLUTE - (PORT dataa (1502:1502:1502) (1614:1614:1614)) - (PORT datab (951:951:951) (1007:1007:1007)) - (PORT datac (180:180:180) (216:216:216)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (325:325:325)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~106) - (DELAY - (ABSOLUTE - (PORT dataa (678:678:678) (778:778:778)) - (PORT datab (1164:1164:1164) (1255:1255:1255)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (174:174:174) (198:198:198)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~57) - (DELAY - (ABSOLUTE - (PORT dataa (1972:1972:1972) (2064:2064:2064)) - (PORT datab (1148:1148:1148) (1200:1200:1200)) - (PORT datac (180:180:180) (216:216:216)) - (PORT datad (843:843:843) (868:868:868)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~58) - (DELAY - (ABSOLUTE - (PORT dataa (1975:1975:1975) (2066:2066:2066)) - (PORT datab (647:647:647) (708:708:708)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (1634:1634:1634) (1673:1673:1673)) - (IOPATH dataa combout (371:371:371) (376:376:376)) + (PORT dataa (1195:1195:1195) (1214:1214:1214)) + (PORT datab (243:243:243) (298:298:298)) + (PORT datac (570:570:570) (596:596:596)) + (PORT datad (1615:1615:1615) (1654:1654:1654)) + (IOPATH dataa combout (324:324:324) (328:328:328)) (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[0\]) - (DELAY - (ABSOLUTE - (PORT dataa (977:977:977) (1044:1044:1044)) - (PORT datab (918:918:918) (964:964:964)) - (PORT datac (244:244:244) (297:297:297)) - (PORT datad (1588:1588:1588) (1606:1606:1606)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[0\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|rden_decode\|w_anode284w\[2\]\~0) (DELAY (ABSOLUTE - (PORT clk (1526:1526:1526) (1531:1531:1531)) + (PORT datab (1632:1632:1632) (1772:1772:1772)) + (PORT datac (2564:2564:2564) (2736:2736:2736)) + (PORT datad (2259:2259:2259) (2383:2383:2383)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1257:1257:1257) (1294:1294:1294)) + (PORT datab (341:341:341) (369:369:369)) + (PORT datad (195:195:195) (220:220:220)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1537:1537:1537) (1535:1535:1535)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (841:841:841) (846:846:846)) + (PORT asdata (982:982:982) (1034:1034:1034)) + (PORT sload (1782:1782:1782) (1900:1900:1900)) + (PORT ena (1716:1716:1716) (1679:1679:1679)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[0\]\~16) - (DELAY - (ABSOLUTE - (PORT datab (393:393:393) (423:423:423)) - (PORT datac (407:407:407) (468:468:468)) - (PORT datad (674:674:674) (692:692:692)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[0\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (981:981:981) (1004:1004:1004)) - (PORT datab (1377:1377:1377) (1376:1376:1376)) - (PORT datac (889:889:889) (939:939:939)) - (PORT datad (892:892:892) (894:894:894)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1519:1519:1519) (1532:1532:1532)) - (PORT asdata (1523:1523:1523) (1555:1555:1555)) - (PORT clrn (1576:1576:1576) (1555:1555:1555)) - (PORT ena (1506:1506:1506) (1484:1484:1484)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK + (HOLD sload (posedge clk) (157:157:157)) (HOLD asdata (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal63\~0) + (INSTANCE z80_\|address_pins_\|abus\[1\]\~25) (DELAY (ABSOLUTE - (PORT dataa (1988:1988:1988) (2128:2128:2128)) - (PORT datab (1534:1534:1534) (1633:1633:1633)) - (PORT datac (227:227:227) (272:272:272)) - (PORT datad (1108:1108:1108) (1149:1149:1149)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_flags_cf2_sel_daa) - (DELAY - (ABSOLUTE - (PORT dataa (1494:1494:1494) (1599:1599:1599)) - (PORT datab (1480:1480:1480) (1588:1588:1588)) - (PORT datac (1844:1844:1844) (1910:1910:1910)) - (PORT datad (400:400:400) (434:434:434)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|SYNTHESIZED_WIRE_2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (357:357:357) (496:496:496)) - (PORT datab (712:712:712) (746:746:746)) - (PORT datac (1434:1434:1434) (1535:1535:1535)) - (PORT datad (1300:1300:1300) (1393:1393:1393)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~10) - (DELAY - (ABSOLUTE - (PORT dataa (684:684:684) (734:734:734)) - (PORT datac (1154:1154:1154) (1186:1186:1186)) - (PORT datad (918:918:918) (942:942:942)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[6\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (198:198:198) (241:241:241)) - (PORT datab (661:661:661) (720:720:720)) - (PORT datac (871:871:871) (900:900:900)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[4\]\~30) - (DELAY - (ABSOLUTE - (PORT dataa (530:530:530) (558:558:558)) - (PORT datab (903:903:903) (932:932:932)) - (PORT datac (591:591:591) (604:604:604)) - (PORT datad (1156:1156:1156) (1185:1185:1185)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[4\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (655:655:655) (673:673:673)) - (PORT datab (955:955:955) (981:981:981)) - (PORT datac (646:646:646) (694:694:694)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|alu_control_\|db\[4\]\~32) - (DELAY - (ABSOLUTE - (PORT dataa (897:897:897) (931:931:931)) - (PORT datab (243:243:243) (291:291:291)) - (PORT datac (626:626:626) (680:680:680)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~119) - (DELAY - (ABSOLUTE - (PORT dataa (757:757:757) (859:859:859)) - (PORT datab (722:722:722) (821:821:821)) - (PORT datac (1142:1142:1142) (1227:1227:1227)) - (PORT datad (912:912:912) (978:978:978)) - (IOPATH dataa combout (341:341:341) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~120) - (DELAY - (ABSOLUTE - (PORT dataa (678:678:678) (707:707:707)) - (PORT datab (345:345:345) (371:371:371)) - (PORT datac (711:711:711) (812:812:812)) - (PORT datad (733:733:733) (834:834:834)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~95) - (DELAY - (ABSOLUTE - (PORT dataa (792:792:792) (904:904:904)) - (PORT datac (708:708:708) (801:801:801)) - (PORT datad (1136:1136:1136) (1221:1221:1221)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~121) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (243:243:243)) - (PORT datad (180:180:180) (209:209:209)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1573:1573:1573)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~117) - (DELAY - (ABSOLUTE - (PORT dataa (444:444:444) (535:535:535)) - (PORT datab (659:659:659) (735:735:735)) - (PORT datad (723:723:723) (804:804:804)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~136) - (DELAY - (ABSOLUTE - (PORT dataa (563:563:563) (585:585:585)) - (PORT datab (451:451:451) (519:519:519)) - (PORT datad (651:651:651) (723:723:723)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~130) - (DELAY - (ABSOLUTE - (PORT dataa (680:680:680) (763:763:763)) - (PORT datab (663:663:663) (692:692:692)) - (PORT datad (833:833:833) (881:881:881)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~118) - (DELAY - (ABSOLUTE - (PORT dataa (794:794:794) (905:905:905)) - (PORT datab (628:628:628) (650:650:650)) - (PORT datad (616:616:616) (634:634:634)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1573:1573:1573)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~78) - (DELAY - (ABSOLUTE - (PORT dataa (894:894:894) (906:906:906)) - (PORT datab (874:874:874) (902:902:902)) - (PORT datac (610:610:610) (671:671:671)) - (PORT datad (657:657:657) (708:708:708)) - (IOPATH dataa combout (303:303:303) (308:308:308)) + (PORT datab (598:598:598) (658:658:658)) + (PORT datac (2048:2048:2048) (2144:2144:2144)) (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~126) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[2\]\~2) (DELAY (ABSOLUTE - (PORT dataa (822:822:822) (934:934:934)) - (PORT datab (697:697:697) (727:727:727)) - (PORT datac (960:960:960) (1039:1039:1039)) - (PORT datad (1384:1384:1384) (1501:1501:1501)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~128) - (DELAY - (ABSOLUTE - (PORT dataa (970:970:970) (1046:1046:1046)) - (PORT datab (788:788:788) (902:902:902)) - (PORT datac (903:903:903) (997:997:997)) - (PORT datad (767:767:767) (878:878:878)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~129) - (DELAY - (ABSOLUTE - (PORT dataa (352:352:352) (385:385:385)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datad (904:904:904) (977:977:977)) + (PORT dataa (1257:1257:1257) (1298:1298:1298)) + (PORT datab (384:384:384) (413:413:413)) + (PORT datad (311:311:311) (330:330:330)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[2\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1537:1537:1537) (1535:1535:1535)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1573:1573:1573)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~127) - (DELAY - (ABSOLUTE - (PORT dataa (601:601:601) (636:636:636)) - (PORT datab (964:964:964) (1050:1050:1050)) - (PORT datad (568:568:568) (584:584:584)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Equal0\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1590:1590:1590) (1687:1687:1687)) - (PORT datac (744:744:744) (848:848:848)) - (PORT datad (713:713:713) (799:799:799)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~51) - (DELAY - (ABSOLUTE - (PORT dataa (707:707:707) (730:730:730)) - (PORT datab (1231:1231:1231) (1291:1291:1291)) - (PORT datac (920:920:920) (989:989:989)) - (PORT datad (331:331:331) (350:350:350)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~125) - (DELAY - (ABSOLUTE - (PORT dataa (210:210:210) (260:260:260)) - (PORT datab (965:965:965) (1053:1053:1053)) - (PORT datad (361:361:361) (388:388:388)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~79) - (DELAY - (ABSOLUTE - (PORT dataa (1349:1349:1349) (1392:1392:1392)) - (PORT datab (1223:1223:1223) (1278:1278:1278)) - (PORT datac (216:216:216) (293:293:293)) - (PORT datad (217:217:217) (286:286:286)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~122) - (DELAY - (ABSOLUTE - (PORT dataa (447:447:447) (536:536:536)) - (PORT datab (659:659:659) (734:734:734)) - (PORT datad (725:725:725) (804:804:804)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~123) - (DELAY - (ABSOLUTE - (PORT dataa (585:585:585) (608:608:608)) - (PORT datab (728:728:728) (826:826:826)) - (PORT datac (1546:1546:1546) (1656:1656:1656)) - (PORT datad (580:580:580) (596:596:596)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~124) - (DELAY - (ABSOLUTE - (PORT dataa (656:656:656) (689:689:689)) - (PORT datab (745:745:745) (852:852:852)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|key_row\~3) - (DELAY - (ABSOLUTE - (PORT datab (1510:1510:1510) (1603:1603:1603)) - (PORT datac (869:869:869) (961:961:961)) - (PORT datad (218:218:218) (287:287:287)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~80) - (DELAY - (ABSOLUTE - (PORT dataa (377:377:377) (453:453:453)) - (PORT datab (632:632:632) (659:659:659)) - (PORT datac (1349:1349:1349) (1408:1408:1408)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~111) - (DELAY - (ABSOLUTE - (PORT dataa (793:793:793) (903:903:903)) - (PORT datac (702:702:702) (794:794:794)) - (PORT datad (1130:1130:1130) (1214:1214:1214)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~97) - (DELAY - (ABSOLUTE - (PORT dataa (1164:1164:1164) (1266:1266:1266)) - (PORT datab (724:724:724) (824:824:824)) - (PORT datac (642:642:642) (670:670:670)) - (PORT datad (909:909:909) (977:977:977)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~116) - (DELAY - (ABSOLUTE - (PORT dataa (383:383:383) (411:411:411)) - (PORT datab (222:222:222) (261:261:261)) - (PORT datad (183:183:183) (213:213:213)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1573:1573:1573)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]\~115) - (DELAY - (ABSOLUTE - (PORT dataa (585:585:585) (605:605:605)) - (PORT datab (363:363:363) (394:394:394)) - (PORT datad (717:717:717) (811:811:811)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~77) - (DELAY - (ABSOLUTE - (PORT dataa (1136:1136:1136) (1168:1168:1168)) - (PORT datab (1142:1142:1142) (1214:1214:1214)) - (PORT datac (639:639:639) (698:698:698)) - (PORT datad (218:218:218) (287:287:287)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~81) - (DELAY - (ABSOLUTE - (PORT dataa (1616:1616:1616) (1662:1662:1662)) - (PORT datab (198:198:198) (236:236:236)) - (PORT datac (173:173:173) (206:206:206)) - (PORT datad (171:171:171) (196:196:196)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3349:3349:3349) (3565:3565:3565)) - (PORT d[1] (1605:1605:1605) (1743:1743:1743)) - (PORT d[2] (2398:2398:2398) (2522:2522:2522)) - (PORT d[3] (1878:1878:1878) (1993:1993:1993)) - (PORT d[4] (1904:1904:1904) (2011:2011:2011)) - (PORT d[5] (2072:2072:2072) (2262:2262:2262)) - (PORT d[6] (2267:2267:2267) (2352:2352:2352)) - (PORT d[7] (2156:2156:2156) (2268:2268:2268)) - (PORT d[8] (2927:2927:2927) (3117:3117:3117)) - (PORT d[9] (2257:2257:2257) (2323:2323:2323)) - (PORT d[10] (4015:4015:4015) (4256:4256:4256)) - (PORT d[11] (1788:1788:1788) (1883:1883:1883)) - (PORT d[12] (2324:2324:2324) (2423:2423:2423)) - (PORT clk (1848:1848:1848) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1875:1875:1875)) - (PORT d[0] (2435:2435:2435) (2530:2530:2530)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1849:1849:1849) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1811:1811:1811) (1838:1838:1838)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1496:1496:1496) (1570:1570:1570)) - (PORT clk (1848:1848:1848) (1876:1876:1876)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3471:3471:3471) (3598:3598:3598)) - (PORT d[1] (1681:1681:1681) (1841:1841:1841)) - (PORT d[2] (1803:1803:1803) (1868:1868:1868)) - (PORT d[3] (2137:2137:2137) (2245:2245:2245)) - (PORT d[4] (2206:2206:2206) (2306:2306:2306)) - (PORT d[5] (1648:1648:1648) (1787:1787:1787)) - (PORT d[6] (1447:1447:1447) (1468:1468:1468)) - (PORT d[7] (1455:1455:1455) (1504:1504:1504)) - (PORT d[8] (2907:2907:2907) (3106:3106:3106)) - (PORT d[9] (2261:2261:2261) (2404:2404:2404)) - (PORT d[10] (2303:2303:2303) (2432:2432:2432)) - (PORT d[11] (2139:2139:2139) (2251:2251:2251)) - (PORT d[12] (2022:2022:2022) (2077:2077:2077)) - (PORT clk (1845:1845:1845) (1872:1872:1872)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2862:2862:2862) (2854:2854:2854)) - (PORT clk (1845:1845:1845) (1872:1872:1872)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1876:1876:1876)) - (PORT d[0] (4272:4272:4272) (4376:4376:4376)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1849:1849:1849) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1849:1849:1849) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1849:1849:1849) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1849:1849:1849) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1803:1803:1803) (1801:1801:1801)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1739:1739:1739) (1715:1715:1715)) - (PORT clk (1813:1813:1813) (1807:1807:1807)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4403:4403:4403) (4442:4442:4442)) - (PORT d[1] (4232:4232:4232) (4305:4305:4305)) - (PORT d[2] (4291:4291:4291) (4336:4336:4336)) - (PORT d[3] (4528:4528:4528) (4564:4564:4564)) - (PORT d[4] (4637:4637:4637) (4664:4664:4664)) - (PORT d[5] (4315:4315:4315) (4358:4358:4358)) - (PORT d[6] (4706:4706:4706) (4798:4798:4798)) - (PORT d[7] (4277:4277:4277) (4349:4349:4349)) - (PORT d[8] (4511:4511:4511) (4526:4526:4526)) - (PORT d[9] (4469:4469:4469) (4738:4738:4738)) - (PORT d[10] (4368:4368:4368) (4407:4407:4407)) - (PORT d[11] (4392:4392:4392) (4374:4374:4374)) - (PORT d[12] (4337:4337:4337) (4342:4342:4342)) - (PORT clk (1809:1809:1809) (1803:1803:1803)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1813:1813:1813) (1807:1807:1807)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1814:1814:1814) (1808:1808:1808)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1814:1814:1814) (1808:1808:1808)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1814:1814:1814) (1808:1808:1808)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1814:1814:1814) (1808:1808:1808)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4186:4186:4186) (4425:4425:4425)) - (PORT d[1] (2884:2884:2884) (3131:3131:3131)) - (PORT d[2] (2708:2708:2708) (2819:2819:2819)) - (PORT d[3] (2283:2283:2283) (2458:2458:2458)) - (PORT d[4] (2517:2517:2517) (2710:2710:2710)) - (PORT d[5] (2529:2529:2529) (2722:2722:2722)) - (PORT d[6] (1890:1890:1890) (2008:2008:2008)) - (PORT d[7] (2314:2314:2314) (2443:2443:2443)) - (PORT d[8] (3115:3115:3115) (3376:3376:3376)) - (PORT d[9] (2627:2627:2627) (2762:2762:2762)) - (PORT d[10] (4822:4822:4822) (5078:5078:5078)) - (PORT d[11] (1897:1897:1897) (2050:2050:2050)) - (PORT d[12] (2209:2209:2209) (2354:2354:2354)) - (PORT clk (1856:1856:1856) (1882:1882:1882)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1882:1882:1882)) - (PORT d[0] (3638:3638:3638) (3555:3555:3555)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1883:1883:1883)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1819:1819:1819) (1845:1845:1845)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1004:1004:1004) (1008:1008:1008)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1009:1009:1009)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1555:1555:1555) (1647:1647:1647)) - (PORT clk (1849:1849:1849) (1877:1877:1877)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3013:3013:3013) (3193:3193:3193)) - (PORT d[1] (2314:2314:2314) (2501:2501:2501)) - (PORT d[2] (2182:2182:2182) (2293:2293:2293)) - (PORT d[3] (1900:1900:1900) (2029:2029:2029)) - (PORT d[4] (2430:2430:2430) (2538:2538:2538)) - (PORT d[5] (1950:1950:1950) (2108:2108:2108)) - (PORT d[6] (1747:1747:1747) (1762:1762:1762)) - (PORT d[7] (2376:2376:2376) (2506:2506:2506)) - (PORT d[8] (2895:2895:2895) (3077:3077:3077)) - (PORT d[9] (1983:1983:1983) (2113:2113:2113)) - (PORT d[10] (2017:2017:2017) (2125:2125:2125)) - (PORT d[11] (2437:2437:2437) (2546:2546:2546)) - (PORT d[12] (2561:2561:2561) (2626:2626:2626)) - (PORT clk (1846:1846:1846) (1873:1873:1873)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2577:2577:2577) (2632:2632:2632)) - (PORT clk (1846:1846:1846) (1873:1873:1873)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1849:1849:1849) (1877:1877:1877)) - (PORT d[0] (4055:4055:4055) (3952:3952:3952)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1878:1878:1878)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1878:1878:1878)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1878:1878:1878)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1878:1878:1878)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1804:1804:1804) (1802:1802:1802)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2048:2048:2048) (2021:2021:2021)) - (PORT clk (1814:1814:1814) (1808:1808:1808)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4402:4402:4402) (4453:4453:4453)) - (PORT d[1] (4222:4222:4222) (4285:4285:4285)) - (PORT d[2] (4296:4296:4296) (4356:4356:4356)) - (PORT d[3] (4467:4467:4467) (4510:4510:4510)) - (PORT d[4] (4361:4361:4361) (4378:4378:4378)) - (PORT d[5] (4645:4645:4645) (4676:4676:4676)) - (PORT d[6] (4445:4445:4445) (4533:4533:4533)) - (PORT d[7] (4329:4329:4329) (4398:4398:4398)) - (PORT d[8] (4517:4517:4517) (4536:4536:4536)) - (PORT d[9] (4456:4456:4456) (4702:4702:4702)) - (PORT d[10] (4317:4317:4317) (4323:4323:4323)) - (PORT d[11] (4684:4684:4684) (4714:4714:4714)) - (PORT d[12] (4438:4438:4438) (4553:4553:4553)) - (PORT clk (1810:1810:1810) (1804:1804:1804)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1814:1814:1814) (1808:1808:1808)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1815:1815:1815) (1809:1809:1809)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1815:1815:1815) (1809:1809:1809)) - (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1815:1815:1815) (1809:1809:1809)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1815:1815:1815) (1809:1809:1809)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1806:1806:1806) (1804:1804:1804)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Selector4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1163:1163:1163) (1219:1219:1219)) - (PORT datab (947:947:947) (1002:1002:1002)) - (PORT datac (1385:1385:1385) (1418:1418:1418)) - (PORT datad (1436:1436:1436) (1475:1475:1475)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Selector4\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1314:1314:1314) (1369:1369:1369)) - (PORT datab (951:951:951) (1008:1008:1008)) - (PORT datac (1440:1440:1440) (1502:1502:1502)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (901:901:901) (939:939:939)) - (PORT clk (1851:1851:1851) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3349:3349:3349) (3527:3527:3527)) - (PORT d[1] (1734:1734:1734) (1904:1904:1904)) - (PORT d[2] (1993:1993:1993) (2068:2068:2068)) - (PORT d[3] (2163:2163:2163) (2257:2257:2257)) - (PORT d[4] (1834:1834:1834) (1918:1918:1918)) - (PORT d[5] (1363:1363:1363) (1460:1460:1460)) - (PORT d[6] (1449:1449:1449) (1474:1474:1474)) - (PORT d[7] (3354:3354:3354) (3503:3503:3503)) - (PORT d[8] (2447:2447:2447) (2653:2653:2653)) - (PORT d[9] (3517:3517:3517) (3682:3682:3682)) - (PORT d[10] (2917:2917:2917) (3102:3102:3102)) - (PORT d[11] (1485:1485:1485) (1553:1553:1553)) - (PORT d[12] (1460:1460:1460) (1502:1502:1502)) - (PORT clk (1848:1848:1848) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3345:3345:3345) (3355:3355:3355)) - (PORT clk (1848:1848:1848) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1879:1879:1879)) - (PORT d[0] (1944:1944:1944) (1906:1906:1906)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1811:1811:1811) (1838:1838:1838)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1470:1470:1470) (1515:1515:1515)) - (PORT clk (1841:1841:1841) (1869:1869:1869)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3671:3671:3671) (3886:3886:3886)) - (PORT d[1] (1690:1690:1690) (1854:1854:1854)) - (PORT d[2] (3275:3275:3275) (3430:3430:3430)) - (PORT d[3] (2158:2158:2158) (2262:2262:2262)) - (PORT d[4] (2542:2542:2542) (2676:2676:2676)) - (PORT d[5] (1672:1672:1672) (1804:1804:1804)) - (PORT d[6] (1797:1797:1797) (1871:1871:1871)) - (PORT d[7] (1692:1692:1692) (1762:1762:1762)) - (PORT d[8] (3323:3323:3323) (3550:3550:3550)) - (PORT d[9] (2846:2846:2846) (2959:2959:2959)) - (PORT d[10] (3476:3476:3476) (3688:3688:3688)) - (PORT d[11] (1790:1790:1790) (1894:1894:1894)) - (PORT d[12] (1727:1727:1727) (1788:1788:1788)) - (PORT clk (1838:1838:1838) (1865:1865:1865)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1941:1941:1941) (1913:1913:1913)) - (PORT clk (1838:1838:1838) (1865:1865:1865)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1841:1841:1841) (1869:1869:1869)) - (PORT d[0] (2779:2779:2779) (2775:2775:2775)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1842:1842:1842) (1870:1870:1870)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1842:1842:1842) (1870:1870:1870)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1842:1842:1842) (1870:1870:1870)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1842:1842:1842) (1870:1870:1870)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1801:1801:1801) (1828:1828:1828)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (986:986:986) (991:991:991)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (987:987:987) (992:992:992)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (987:987:987) (992:992:992)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (987:987:987) (992:992:992)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1247:1247:1247) (1305:1305:1305)) - (PORT clk (1851:1851:1851) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3351:3351:3351) (3542:3542:3542)) - (PORT d[1] (1331:1331:1331) (1442:1442:1442)) - (PORT d[2] (1949:1949:1949) (2052:2052:2052)) - (PORT d[3] (1549:1549:1549) (1617:1617:1617)) - (PORT d[4] (1868:1868:1868) (1957:1957:1957)) - (PORT d[5] (1641:1641:1641) (1721:1721:1721)) - (PORT d[6] (1178:1178:1178) (1228:1228:1228)) - (PORT d[7] (1451:1451:1451) (1507:1507:1507)) - (PORT d[8] (2507:2507:2507) (2697:2697:2697)) - (PORT d[9] (3505:3505:3505) (3649:3649:3649)) - (PORT d[10] (2878:2878:2878) (3044:3044:3044)) - (PORT d[11] (1237:1237:1237) (1307:1307:1307)) - (PORT d[12] (1108:1108:1108) (1125:1125:1125)) - (PORT clk (1848:1848:1848) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2872:2872:2872) (2909:2909:2909)) - (PORT clk (1848:1848:1848) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1879:1879:1879)) - (PORT d[0] (3248:3248:3248) (3325:3325:3325)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1811:1811:1811) (1838:1838:1838)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1750:1750:1750) (1835:1835:1835)) - (PORT clk (1850:1850:1850) (1878:1878:1878)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3365:3365:3365) (3581:3581:3581)) - (PORT d[1] (1702:1702:1702) (1864:1864:1864)) - (PORT d[2] (2694:2694:2694) (2816:2816:2816)) - (PORT d[3] (2143:2143:2143) (2257:2257:2257)) - (PORT d[4] (2191:2191:2191) (2314:2314:2314)) - (PORT d[5] (2392:2392:2392) (2607:2607:2607)) - (PORT d[6] (2106:2106:2106) (2209:2209:2209)) - (PORT d[7] (2467:2467:2467) (2597:2597:2597)) - (PORT d[8] (3036:3036:3036) (3248:3248:3248)) - (PORT d[9] (2577:2577:2577) (2669:2669:2669)) - (PORT d[10] (3785:3785:3785) (4034:4034:4034)) - (PORT d[11] (1778:1778:1778) (1856:1856:1856)) - (PORT d[12] (2315:2315:2315) (2396:2396:2396)) - (PORT clk (1847:1847:1847) (1874:1874:1874)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2267:2267:2267) (2265:2265:2265)) - (PORT clk (1847:1847:1847) (1874:1874:1874)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1878:1878:1878)) - (PORT d[0] (2685:2685:2685) (2695:2695:2695)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1879:1879:1879)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1879:1879:1879)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1879:1879:1879)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1851:1851:1851) (1879:1879:1879)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1810:1810:1810) (1837:1837:1837)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (995:995:995) (1000:1000:1000)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1829:1829:1829) (1854:1854:1854)) - (PORT datab (1177:1177:1177) (1181:1181:1181)) - (PORT datad (1696:1696:1696) (1748:1748:1748)) - (IOPATH dataa combout (341:341:341) (320:320:320)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (1465:1465:1465) (1535:1535:1535)) - (PORT datab (1484:1484:1484) (1501:1501:1501)) - (PORT datac (2124:2124:2124) (2189:2189:2189)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~109) - (DELAY - (ABSOLUTE - (PORT dataa (680:680:680) (777:777:777)) - (PORT datab (1164:1164:1164) (1255:1255:1255)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (173:173:173) (197:197:197)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~97) - (DELAY - (ABSOLUTE - (PORT dataa (887:887:887) (916:916:916)) - (PORT datab (1551:1551:1551) (1605:1605:1605)) - (PORT datac (1462:1462:1462) (1538:1538:1538)) - (PORT datad (182:182:182) (211:211:211)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~98) - (DELAY - (ABSOLUTE - (PORT dataa (1168:1168:1168) (1244:1244:1244)) - (PORT datab (1665:1665:1665) (1708:1708:1708)) - (PORT datac (1463:1463:1463) (1538:1538:1538)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[4\]) - (DELAY - (ABSOLUTE - (PORT dataa (970:970:970) (1037:1037:1037)) - (PORT datab (1506:1506:1506) (1524:1524:1524)) - (PORT datac (236:236:236) (289:289:289)) - (PORT datad (1153:1153:1153) (1165:1165:1165)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1526:1526:1526) (1531:1531:1531)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (841:841:841) (846:846:846)) + (PORT asdata (588:588:588) (666:666:666)) + (PORT sload (1782:1782:1782) (1900:1900:1900)) + (PORT ena (1716:1716:1716) (1679:1679:1679)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[4\]\~18) + (INSTANCE z80_\|address_pins_\|abus\[2\]\~26) (DELAY (ABSOLUTE - (PORT dataa (395:395:395) (471:471:471)) - (PORT datab (388:388:388) (422:422:422)) - (PORT datad (671:671:671) (693:693:693)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[4\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (981:981:981) (1007:1007:1007)) - (PORT datab (922:922:922) (965:965:965)) - (PORT datac (888:888:888) (938:938:938)) - (PORT datad (898:898:898) (913:913:913)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1525:1525:1525) (1541:1541:1541)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1571:1571:1571) (1550:1550:1550)) - (PORT ena (1479:1479:1479) (1488:1488:1488)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal21\~0) - (DELAY - (ABSOLUTE - (PORT datac (1440:1440:1440) (1546:1546:1546)) - (PORT datad (1464:1464:1464) (1552:1552:1552)) + (PORT datac (2048:2048:2048) (2143:2143:2143)) + (PORT datad (238:238:238) (306:306:306)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -42830,109 +31093,91 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mRead\~5) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[3\]\~3) (DELAY (ABSOLUTE - (PORT dataa (1381:1381:1381) (1434:1434:1434)) - (PORT datab (981:981:981) (1038:1038:1038)) - (PORT datac (1636:1636:1636) (1757:1757:1757)) - (PORT datad (1217:1217:1217) (1298:1298:1298)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1286:1286:1286) (1367:1367:1367)) - (PORT datab (1528:1528:1528) (1599:1599:1599)) - (PORT datac (821:821:821) (830:830:830)) - (PORT datad (201:201:201) (229:229:229)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~3) - (DELAY - (ABSOLUTE - (PORT datab (1536:1536:1536) (1647:1647:1647)) - (PORT datac (1349:1349:1349) (1441:1441:1441)) - (PORT datad (2442:2442:2442) (2633:2633:2633)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~4) - (DELAY - (ABSOLUTE - (PORT dataa (863:863:863) (915:915:915)) - (PORT datab (925:925:925) (953:953:953)) - (PORT datac (1717:1717:1717) (1764:1764:1764)) - (PORT datad (174:174:174) (199:199:199)) + (PORT dataa (753:753:753) (767:767:767)) + (PORT datab (379:379:379) (407:407:407)) + (PORT datad (1216:1216:1216) (1251:1251:1251)) (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|fIOWrite\~5) - (DELAY - (ABSOLUTE - (PORT dataa (426:426:426) (455:455:455)) - (PORT datab (1184:1184:1184) (1238:1238:1238)) - (PORT datac (171:171:171) (205:205:205)) - (PORT datad (360:360:360) (383:383:383)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~11) - (DELAY - (ABSOLUTE - (PORT dataa (931:931:931) (953:953:953)) - (PORT datab (618:618:618) (660:660:660)) - (PORT datac (888:888:888) (936:936:936)) - (PORT datad (892:892:892) (905:905:905)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~12) - (DELAY - (ABSOLUTE - (PORT dataa (2004:2004:2004) (2054:2054:2054)) - (PORT datab (1141:1141:1141) (1140:1140:1140)) - (PORT datac (850:850:850) (856:856:856)) - (PORT datad (641:641:641) (681:681:681)) - (IOPATH dataa combout (324:324:324) (328:328:328)) (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1537:1537:1537) (1535:1535:1535)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (588:588:588) (666:666:666)) + (PORT sload (1782:1782:1782) (1900:1900:1900)) + (PORT ena (1716:1716:1716) (1679:1679:1679)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[3\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (401:401:401) (476:476:476)) + (PORT datac (2051:2051:2051) (2145:2145:2145)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[4\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1400:1400:1400) (1446:1446:1446)) + (PORT datab (928:928:928) (953:953:953)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1527:1527:1527)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (712:712:712) (784:784:784)) + (PORT sload (2041:2041:2041) (2133:2133:2133)) + (PORT ena (2004:2004:2004) (1967:1967:1967)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[4\]\~28) + (DELAY + (ABSOLUTE + (PORT datac (2392:2392:2392) (2522:2522:2522)) + (PORT datad (237:237:237) (305:305:305)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -42940,304 +31185,160 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~13) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[5\]\~5) (DELAY (ABSOLUTE - (PORT dataa (201:201:201) (243:243:243)) - (PORT datab (596:596:596) (607:607:607)) - (PORT datac (532:532:532) (546:546:546)) - (PORT datad (180:180:180) (208:208:208)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~14) - (DELAY - (ABSOLUTE - (PORT dataa (1573:1573:1573) (1667:1667:1667)) - (PORT datab (881:881:881) (895:895:895)) - (PORT datac (1465:1465:1465) (1505:1505:1505)) - (PORT datad (1073:1073:1073) (1063:1063:1063)) + (PORT dataa (1400:1400:1400) (1447:1447:1447)) + (PORT datab (944:944:944) (959:959:959)) + (PORT datad (319:319:319) (341:341:341)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~15) - (DELAY - (ABSOLUTE - (PORT dataa (637:637:637) (652:652:652)) - (PORT datab (877:877:877) (906:906:906)) - (PORT datac (864:864:864) (874:874:874)) - (PORT datad (1193:1193:1193) (1249:1249:1249)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|DFFE_mwr_ff1) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[5\]) (DELAY (ABSOLUTE - (PORT clk (1535:1535:1535) (1551:1551:1551)) + (PORT clk (1523:1523:1523) (1527:1527:1527)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1591:1591:1591) (1566:1566:1566)) - (PORT ena (1291:1291:1291) (1310:1310:1310)) + (PORT asdata (581:581:581) (655:655:655)) + (PORT sload (2041:2041:2041) (2133:2133:2133)) + (PORT ena (2004:2004:2004) (1967:1967:1967)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) ) (TIMINGCHECK (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|wait_mwr\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (219:219:219) (289:289:289)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|wait_mwr) - (DELAY - (ABSOLUTE - (PORT clk (1542:1542:1542) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1591:1591:1591) (1566:1566:1566)) - (PORT ena (1321:1321:1321) (1347:1347:1347)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|memory_ifc_\|mwr_wr) - (DELAY - (ABSOLUTE - (PORT clk (1542:1542:1542) (1544:1544:1544)) - (PORT asdata (567:567:567) (645:645:645)) - (PORT clrn (1591:1591:1591) (1566:1566:1566)) - (PORT ena (1321:1321:1321) (1347:1347:1347)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK + (HOLD sload (posedge clk) (157:157:157)) (HOLD asdata (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|memory_ifc_\|nWR_out\~0) + (INSTANCE z80_\|address_pins_\|abus\[5\]\~29) (DELAY (ABSOLUTE - (PORT dataa (870:870:870) (890:890:890)) - (PORT datab (351:351:351) (390:390:390)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) + (PORT datac (2387:2387:2387) (2516:2516:2516)) + (PORT datad (237:237:237) (305:305:305)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[5\]\~84) + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[6\]\~6) (DELAY (ABSOLUTE - (PORT dataa (1754:1754:1754) (1854:1854:1854)) - (PORT datab (1594:1594:1594) (1729:1729:1729)) - (PORT datac (1191:1191:1191) (1256:1256:1256)) - (PORT datad (1224:1224:1224) (1308:1308:1308)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (1398:1398:1398) (1445:1445:1445)) + (PORT datab (897:897:897) (908:908:908)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1527:1527:1527)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (724:724:724) (783:783:783)) + (PORT sload (2041:2041:2041) (2133:2133:2133)) + (PORT ena (2004:2004:2004) (1967:1967:1967)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[6\]\~30) + (DELAY + (ABSOLUTE + (PORT datab (263:263:263) (345:345:345)) + (PORT datac (2385:2385:2385) (2515:2515:2515)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[7\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1428:1428:1428) (1479:1479:1479)) + (PORT datab (574:574:574) (589:589:589)) + (PORT datad (1317:1317:1317) (1317:1317:1317)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1527:1527:1527)) + (PORT d (74:74:74) (91:91:91)) + (PORT asdata (727:727:727) (784:784:784)) + (PORT sload (2032:2032:2032) (2084:2084:2084)) + (PORT ena (2298:2298:2298) (2265:2265:2265)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[7\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (2753:2753:2753) (2927:2927:2927)) + (PORT datad (919:919:919) (994:994:994)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_pins_\|abus\[10\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (2700:2700:2700) (2865:2865:2865)) + (PORT datad (1399:1399:1399) (1477:1477:1477)) + (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.datain_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1170:1170:1170) (1220:1220:1220)) - (PORT clk (1856:1856:1856) (1883:1883:1883)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4199:4199:4199) (4456:4456:4456)) - (PORT d[1] (2869:2869:2869) (3121:3121:3121)) - (PORT d[2] (3253:3253:3253) (3349:3349:3349)) - (PORT d[3] (2536:2536:2536) (2717:2717:2717)) - (PORT d[4] (2232:2232:2232) (2420:2420:2420)) - (PORT d[5] (2568:2568:2568) (2749:2749:2749)) - (PORT d[6] (1862:1862:1862) (1979:1979:1979)) - (PORT d[7] (2324:2324:2324) (2461:2461:2461)) - (PORT d[8] (3106:3106:3106) (3383:3383:3383)) - (PORT d[9] (2915:2915:2915) (3048:3048:3048)) - (PORT d[10] (4807:4807:4807) (5077:5077:5077)) - (PORT d[11] (2186:2186:2186) (2342:2342:2342)) - (PORT d[12] (2200:2200:2200) (2338:2338:2338)) - (PORT clk (1853:1853:1853) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1968:1968:1968) (1944:1944:1944)) - (PORT clk (1853:1853:1853) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1856:1856:1856) (1883:1883:1883)) - (PORT d[0] (2326:2326:2326) (2304:2304:2304)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1884:1884:1884)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1816:1816:1816) (1842:1842:1842)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1001:1001:1001) (1005:1005:1005)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1002:1002:1002) (1006:1006:1006)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1002:1002:1002) (1006:1006:1006)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1002:1002:1002) (1006:1006:1006)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1193:1193:1193) (1222:1222:1222)) + (PORT d[0] (949:949:949) (947:947:947)) (PORT clk (1858:1858:1858) (1884:1884:1884)) ) ) @@ -43247,22 +31348,22 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (4194:4194:4194) (4449:4449:4449)) - (PORT d[1] (2891:2891:2891) (3144:3144:3144)) - (PORT d[2] (2764:2764:2764) (2858:2858:2858)) - (PORT d[3] (2536:2536:2536) (2713:2713:2713)) - (PORT d[4] (2253:2253:2253) (2443:2443:2443)) - (PORT d[5] (2541:2541:2541) (2717:2717:2717)) - (PORT d[6] (1898:1898:1898) (2008:2008:2008)) - (PORT d[7] (2297:2297:2297) (2428:2428:2428)) - (PORT d[8] (3124:3124:3124) (3401:3401:3401)) - (PORT d[9] (2609:2609:2609) (2741:2741:2741)) - (PORT d[10] (4803:4803:4803) (5068:5068:5068)) - (PORT d[11] (1891:1891:1891) (2036:2036:2036)) - (PORT d[12] (2208:2208:2208) (2353:2353:2353)) + (PORT d[0] (3244:3244:3244) (3484:3484:3484)) + (PORT d[1] (1230:1230:1230) (1303:1303:1303)) + (PORT d[2] (2930:2930:2930) (3162:3162:3162)) + (PORT d[3] (711:711:711) (746:746:746)) + (PORT d[4] (1129:1129:1129) (1133:1133:1133)) + (PORT d[5] (1229:1229:1229) (1266:1266:1266)) + (PORT d[6] (986:986:986) (1025:1025:1025)) + (PORT d[7] (2881:2881:2881) (3130:3130:3130)) + (PORT d[8] (1254:1254:1254) (1284:1284:1284)) + (PORT d[9] (965:965:965) (989:989:989)) + (PORT d[10] (1597:1597:1597) (1663:1663:1663)) + (PORT d[11] (1508:1508:1508) (1552:1552:1552)) + (PORT d[12] (2584:2584:2584) (2670:2670:2670)) (PORT clk (1855:1855:1855) (1880:1880:1880)) ) ) @@ -43272,10 +31373,10 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.we_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2383:2383:2383) (2365:2365:2365)) + (PORT d[0] (1973:1973:1973) (1902:1902:1902)) (PORT clk (1855:1855:1855) (1880:1880:1880)) ) ) @@ -43285,17 +31386,17 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) (DELAY (ABSOLUTE (PORT clk (1858:1858:1858) (1884:1884:1884)) - (PORT d[0] (2857:2857:2857) (2839:2839:2839)) + (PORT d[0] (2244:2244:2244) (2181:2181:2181)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_a) (DELAY (ABSOLUTE (PORT clk (1859:1859:1859) (1885:1885:1885)) @@ -43305,7 +31406,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) (DELAY (ABSOLUTE (PORT clk (1859:1859:1859) (1885:1885:1885)) @@ -43315,7 +31416,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_a) (DELAY (ABSOLUTE (PORT clk (1859:1859:1859) (1885:1885:1885)) @@ -43325,7 +31426,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_a) (DELAY (ABSOLUTE (PORT clk (1859:1859:1859) (1885:1885:1885)) @@ -43335,7 +31436,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) (DELAY (ABSOLUTE (PORT clk (1818:1818:1818) (1843:1843:1843)) @@ -43349,7 +31450,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) (DELAY (ABSOLUTE (PORT clk (1003:1003:1003) (1006:1006:1006)) @@ -43358,7 +31459,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) (DELAY (ABSOLUTE (PORT clk (1004:1004:1004) (1007:1007:1007)) @@ -43367,7 +31468,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) (DELAY (ABSOLUTE (PORT clk (1004:1004:1004) (1007:1007:1007)) @@ -43377,7 +31478,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) (DELAY (ABSOLUTE (PORT clk (1004:1004:1004) (1007:1007:1007)) @@ -43385,982 +31486,17 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (880:880:880) (918:918:918)) - (PORT clk (1852:1852:1852) (1879:1879:1879)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1334:1334:1334) (1380:1380:1380)) - (PORT d[1] (2044:2044:2044) (2248:2248:2248)) - (PORT d[2] (3016:3016:3016) (3126:3126:3126)) - (PORT d[3] (2584:2584:2584) (2783:2783:2783)) - (PORT d[4] (2569:2569:2569) (2761:2761:2761)) - (PORT d[5] (2836:2836:2836) (3029:3029:3029)) - (PORT d[6] (1949:1949:1949) (2075:2075:2075)) - (PORT d[7] (2609:2609:2609) (2760:2760:2760)) - (PORT d[8] (3388:3388:3388) (3680:3680:3680)) - (PORT d[9] (2935:2935:2935) (3067:3067:3067)) - (PORT d[10] (5109:5109:5109) (5374:5374:5374)) - (PORT d[11] (1927:1927:1927) (2066:2066:2066)) - (PORT d[12] (1910:1910:1910) (2033:2033:2033)) - (PORT clk (1849:1849:1849) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1228:1228:1228) (1223:1223:1223)) - (PORT clk (1849:1849:1849) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1852:1852:1852) (1879:1879:1879)) - (PORT d[0] (2528:2528:2528) (2496:2496:2496)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1853:1853:1853) (1880:1880:1880)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1812:1812:1812) (1838:1838:1838)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1001:1001:1001)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~6) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode223w\[2\]) (DELAY (ABSOLUTE - (PORT dataa (1430:1430:1430) (1510:1510:1510)) - (PORT datab (977:977:977) (1037:1037:1037)) - (PORT datac (1084:1084:1084) (1106:1106:1106)) - (PORT datad (833:833:833) (863:863:863)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1183:1183:1183) (1216:1216:1216)) - (PORT clk (1849:1849:1849) (1876:1876:1876)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3355:3355:3355) (3572:3572:3572)) - (PORT d[1] (1697:1697:1697) (1865:1865:1865)) - (PORT d[2] (2991:2991:2991) (3133:3133:3133)) - (PORT d[3] (2197:2197:2197) (2290:2290:2290)) - (PORT d[4] (2502:2502:2502) (2653:2653:2653)) - (PORT d[5] (2405:2405:2405) (2601:2601:2601)) - (PORT d[6] (2102:2102:2102) (2200:2200:2200)) - (PORT d[7] (2478:2478:2478) (2588:2588:2588)) - (PORT d[8] (3018:3018:3018) (3244:3244:3244)) - (PORT d[9] (2534:2534:2534) (2624:2624:2624)) - (PORT d[10] (3776:3776:3776) (4011:4011:4011)) - (PORT d[11] (1726:1726:1726) (1804:1804:1804)) - (PORT d[12] (2323:2323:2323) (2409:2409:2409)) - (PORT clk (1846:1846:1846) (1872:1872:1872)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2206:2206:2206) (2199:2199:2199)) - (PORT clk (1846:1846:1846) (1872:1872:1872)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1849:1849:1849) (1876:1876:1876)) - (PORT d[0] (2749:2749:2749) (2715:2715:2715)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1809:1809:1809) (1835:1835:1835)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (994:994:994) (998:998:998)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (995:995:995) (999:999:999)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (995:995:995) (999:999:999)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (995:995:995) (999:999:999)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (1449:1449:1449) (1499:1499:1499)) - (PORT datab (1154:1154:1154) (1180:1180:1180)) - (PORT datac (171:171:171) (203:203:203)) - (PORT datad (1425:1425:1425) (1425:1425:1425)) + (PORT dataa (1196:1196:1196) (1217:1217:1217)) + (PORT datab (239:239:239) (292:292:292)) + (PORT datac (568:568:568) (595:595:595)) + (PORT datad (1614:1614:1614) (1653:1653:1653)) (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1785:1785:1785) (1834:1834:1834)) - (PORT clk (1844:1844:1844) (1873:1873:1873)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3330:3330:3330) (3510:3510:3510)) - (PORT d[1] (2345:2345:2345) (2548:2548:2548)) - (PORT d[2] (2224:2224:2224) (2307:2307:2307)) - (PORT d[3] (1895:1895:1895) (2026:2026:2026)) - (PORT d[4] (2445:2445:2445) (2553:2553:2553)) - (PORT d[5] (1968:1968:1968) (2118:2118:2118)) - (PORT d[6] (1422:1422:1422) (1463:1463:1463)) - (PORT d[7] (1469:1469:1469) (1501:1501:1501)) - (PORT d[8] (2903:2903:2903) (3100:3100:3100)) - (PORT d[9] (1984:1984:1984) (2114:2114:2114)) - (PORT d[10] (1991:1991:1991) (2095:2095:2095)) - (PORT d[11] (1441:1441:1441) (1479:1479:1479)) - (PORT d[12] (2020:2020:2020) (2065:2065:2065)) - (PORT clk (1841:1841:1841) (1869:1869:1869)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2835:2835:2835) (2823:2823:2823)) - (PORT clk (1841:1841:1841) (1869:1869:1869)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1873:1873:1873)) - (PORT d[0] (3960:3960:3960) (4062:4062:4062)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1845:1845:1845) (1874:1874:1874)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1845:1845:1845) (1874:1874:1874)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1845:1845:1845) (1874:1874:1874)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1845:1845:1845) (1874:1874:1874)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1799:1799:1799) (1798:1798:1798)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1198:1198:1198) (1181:1181:1181)) - (PORT clk (1809:1809:1809) (1804:1804:1804)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4418:4418:4418) (4468:4468:4468)) - (PORT d[1] (4222:4222:4222) (4280:4280:4280)) - (PORT d[2] (4287:4287:4287) (4334:4334:4334)) - (PORT d[3] (4530:4530:4530) (4580:4580:4580)) - (PORT d[4] (4340:4340:4340) (4354:4354:4354)) - (PORT d[5] (4359:4359:4359) (4381:4381:4381)) - (PORT d[6] (4659:4659:4659) (4748:4748:4748)) - (PORT d[7] (4373:4373:4373) (4445:4445:4445)) - (PORT d[8] (4529:4529:4529) (4546:4546:4546)) - (PORT d[9] (4710:4710:4710) (4968:4968:4968)) - (PORT d[10] (4380:4380:4380) (4418:4418:4418)) - (PORT d[11] (4364:4364:4364) (4385:4385:4385)) - (PORT d[12] (4681:4681:4681) (4658:4658:4658)) - (PORT clk (1805:1805:1805) (1800:1800:1800)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1809:1809:1809) (1804:1804:1804)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1810:1810:1810) (1805:1805:1805)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1810:1810:1810) (1805:1805:1805)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1810:1810:1810) (1805:1805:1805)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1810:1810:1810) (1805:1805:1805)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2604:2604:2604) (2682:2682:2682)) - (PORT d[1] (2063:2063:2063) (2283:2283:2283)) - (PORT d[2] (2289:2289:2289) (2441:2441:2441)) - (PORT d[3] (2285:2285:2285) (2377:2377:2377)) - (PORT d[4] (2950:2950:2950) (3220:3220:3220)) - (PORT d[5] (2075:2075:2075) (2260:2260:2260)) - (PORT d[6] (1854:1854:1854) (1963:1963:1963)) - (PORT d[7] (2555:2555:2555) (2658:2658:2658)) - (PORT d[8] (2752:2752:2752) (3006:3006:3006)) - (PORT d[9] (1553:1553:1553) (1673:1673:1673)) - (PORT d[10] (1845:1845:1845) (1962:1962:1962)) - (PORT d[11] (2882:2882:2882) (3002:3002:3002)) - (PORT d[12] (1537:1537:1537) (1640:1640:1640)) - (PORT clk (1867:1867:1867) (1892:1892:1892)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1867:1867:1867) (1892:1892:1892)) - (PORT d[0] (2184:2184:2184) (2245:2245:2245)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1868:1868:1868) (1893:1893:1893)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1830:1830:1830) (1855:1855:1855)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1015:1015:1015) (1018:1018:1018)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1016:1016:1016) (1019:1019:1019)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1016:1016:1016) (1019:1019:1019)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1016:1016:1016) (1019:1019:1019)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3543:3543:3543) (3733:3733:3733)) - (PORT d[1] (1715:1715:1715) (1880:1880:1880)) - (PORT d[2] (2685:2685:2685) (2807:2807:2807)) - (PORT d[3] (2133:2133:2133) (2228:2228:2228)) - (PORT d[4] (1902:1902:1902) (2026:2026:2026)) - (PORT d[5] (2379:2379:2379) (2573:2573:2573)) - (PORT d[6] (2329:2329:2329) (2418:2418:2418)) - (PORT d[7] (2458:2458:2458) (2570:2570:2570)) - (PORT d[8] (2691:2691:2691) (2888:2888:2888)) - (PORT d[9] (2519:2519:2519) (2590:2590:2590)) - (PORT d[10] (3815:3815:3815) (4071:4071:4071)) - (PORT d[11] (1813:1813:1813) (1894:1894:1894)) - (PORT d[12] (2372:2372:2372) (2459:2459:2459)) - (PORT clk (1848:1848:1848) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1875:1875:1875)) - (PORT d[0] (2529:2529:2529) (2434:2434:2434)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1849:1849:1849) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1811:1811:1811) (1838:1838:1838)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (996:996:996) (1001:1001:1001)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1649:1649:1649) (1736:1736:1736)) - (PORT clk (1860:1860:1860) (1888:1888:1888)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2915:2915:2915) (3030:3030:3030)) - (PORT d[1] (2366:2366:2366) (2611:2611:2611)) - (PORT d[2] (2597:2597:2597) (2777:2777:2777)) - (PORT d[3] (2017:2017:2017) (2075:2075:2075)) - (PORT d[4] (2919:2919:2919) (3173:3173:3173)) - (PORT d[5] (2370:2370:2370) (2578:2578:2578)) - (PORT d[6] (1866:1866:1866) (1962:1962:1962)) - (PORT d[7] (1642:1642:1642) (1751:1751:1751)) - (PORT d[8] (3027:3027:3027) (3282:3282:3282)) - (PORT d[9] (1219:1219:1219) (1304:1304:1304)) - (PORT d[10] (2155:2155:2155) (2296:2296:2296)) - (PORT d[11] (3694:3694:3694) (3833:3833:3833)) - (PORT d[12] (1894:1894:1894) (1995:1995:1995)) - (PORT clk (1857:1857:1857) (1884:1884:1884)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2802:2802:2802) (2787:2787:2787)) - (PORT clk (1857:1857:1857) (1884:1884:1884)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1860:1860:1860) (1888:1888:1888)) - (PORT d[0] (3138:3138:3138) (3102:3102:3102)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1889:1889:1889)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1889:1889:1889)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1889:1889:1889)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1861:1861:1861) (1889:1889:1889)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1815:1815:1815) (1813:1813:1813)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2176:2176:2176) (2231:2231:2231)) - (PORT clk (1825:1825:1825) (1819:1819:1819)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4610:4610:4610) (4658:4658:4658)) - (PORT d[1] (4157:4157:4157) (4160:4160:4160)) - (PORT d[2] (4196:4196:4196) (4284:4284:4284)) - (PORT d[3] (4718:4718:4718) (4716:4716:4716)) - (PORT d[4] (4356:4356:4356) (4386:4386:4386)) - (PORT d[5] (4428:4428:4428) (4381:4381:4381)) - (PORT d[6] (4640:4640:4640) (4703:4703:4703)) - (PORT d[7] (4181:4181:4181) (4140:4140:4140)) - (PORT d[8] (4708:4708:4708) (4720:4720:4720)) - (PORT d[9] (4594:4594:4594) (4806:4806:4806)) - (PORT d[10] (4407:4407:4407) (4422:4422:4422)) - (PORT d[11] (4504:4504:4504) (4555:4555:4555)) - (PORT d[12] (4480:4480:4480) (4497:4497:4497)) - (PORT clk (1821:1821:1821) (1815:1815:1815)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1825:1825:1825) (1819:1819:1819)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1820:1820:1820)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1820:1820:1820)) - (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1820:1820:1820)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1826:1826:1826) (1820:1820:1820)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_b_register) - (DELAY - (ABSOLUTE - (PORT clk (1817:1817:1817) (1815:1815:1815)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Mux0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1424:1424:1424) (1496:1496:1496)) - (PORT datab (973:973:973) (1052:1052:1052)) - (PORT datac (1431:1431:1431) (1467:1467:1467)) - (PORT datad (1389:1389:1389) (1443:1443:1443)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Mux0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1500:1500:1500) (1615:1615:1615)) - (PORT datab (972:972:972) (1051:1051:1051)) - (PORT datac (1456:1456:1456) (1510:1510:1510)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datab combout (342:342:342) (318:318:318)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -44368,169 +31504,218 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[7\]\~112) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode223w\[2\]\~0) (DELAY (ABSOLUTE - (PORT dataa (1480:1480:1480) (1579:1579:1579)) - (PORT datab (1206:1206:1206) (1296:1296:1296)) - (PORT datac (173:173:173) (206:206:206)) - (PORT datad (174:174:174) (198:198:198)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT datab (1635:1635:1635) (1774:1774:1774)) + (PORT datac (2565:2565:2565) (2731:2731:2731)) + (PORT datad (2259:2259:2259) (2379:2379:2379)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[7\]\~94) + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register) (DELAY (ABSOLUTE - (PORT dataa (1382:1382:1382) (1396:1396:1396)) - (PORT datab (885:885:885) (963:963:963)) - (PORT datac (171:171:171) (203:203:203)) - (PORT datad (1346:1346:1346) (1371:1371:1371)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT d[0] (745:745:745) (777:777:777)) + (PORT clk (1854:1854:1854) (1881:1881:1881)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2601:2601:2601) (2724:2724:2724)) + (PORT d[1] (957:957:957) (991:991:991)) + (PORT d[2] (2647:2647:2647) (2880:2880:2880)) + (PORT d[3] (990:990:990) (1038:1038:1038)) + (PORT d[4] (704:704:704) (741:741:741)) + (PORT d[5] (668:668:668) (685:685:685)) + (PORT d[6] (666:666:666) (687:687:687)) + (PORT d[7] (2154:2154:2154) (2329:2329:2329)) + (PORT d[8] (1515:1515:1515) (1558:1558:1558)) + (PORT d[9] (665:665:665) (685:685:685)) + (PORT d[10] (2168:2168:2168) (2235:2235:2235)) + (PORT d[11] (1753:1753:1753) (1779:1779:1779)) + (PORT d[12] (2577:2577:2577) (2648:2648:2648)) + (PORT clk (1851:1851:1851) (1877:1877:1877)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1431:1431:1431) (1378:1378:1378)) + (PORT clk (1851:1851:1851) (1877:1877:1877)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1881:1881:1881)) + (PORT d[0] (1918:1918:1918) (1876:1876:1876)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1855:1855:1855) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1855:1855:1855) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1855:1855:1855) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1855:1855:1855) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1814:1814:1814) (1840:1840:1840)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (999:999:999) (1003:1003:1003)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1000:1000:1000) (1004:1004:1004)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1000:1000:1000) (1004:1004:1004)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1000:1000:1000) (1004:1004:1004)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[7\]\~102) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[0\]\~feeder) (DELAY (ABSOLUTE - (PORT datac (191:191:191) (224:224:224)) - (PORT datad (781:781:781) (792:792:792)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[7\]) - (DELAY - (ABSOLUTE - (PORT dataa (968:968:968) (1025:1025:1025)) - (PORT datab (229:229:229) (272:272:272)) - (PORT datac (239:239:239) (287:287:287)) - (PORT datad (858:858:858) (899:899:899)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT datad (1551:1551:1551) (1591:1591:1591)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[7\]) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[0\]) (DELAY (ABSOLUTE - (PORT clk (1526:1526:1526) (1531:1531:1531)) + (PORT clk (1516:1516:1516) (1529:1529:1529)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (841:841:841) (846:846:846)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[7\]\~5) - (DELAY - (ABSOLUTE - (PORT datab (1164:1164:1164) (1192:1192:1192)) - (PORT datac (942:942:942) (1003:1003:1003)) - (PORT datad (367:367:367) (390:390:390)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[7\]\~7) - (DELAY - (ABSOLUTE - (PORT dataa (267:267:267) (355:355:355)) - (PORT datab (711:711:711) (731:731:731)) - (PORT datac (879:879:879) (883:883:883)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[7\]) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]) (DELAY (ABSOLUTE - (PORT clk (1522:1522:1522) (1535:1535:1535)) - (PORT asdata (546:546:546) (581:581:581)) - (PORT clrn (1579:1579:1579) (1558:1558:1558)) - (PORT ena (1501:1501:1501) (1488:1488:1488)) + (PORT clk (1516:1516:1516) (1529:1529:1529)) + (PORT asdata (1468:1468:1468) (1527:1527:1527)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) ) (TIMINGCHECK (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal77\~0) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode244w\[2\]) (DELAY (ABSOLUTE - (PORT dataa (711:711:711) (814:814:814)) - (PORT datab (1235:1235:1235) (1355:1355:1355)) - (PORT datac (985:985:985) (1064:1064:1064)) - (PORT datad (1322:1322:1322) (1437:1437:1437)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~5) - (DELAY - (ABSOLUTE - (PORT dataa (690:690:690) (756:756:756)) - (PORT datab (994:994:994) (1104:1104:1104)) - (PORT datac (1148:1148:1148) (1191:1191:1191)) - (PORT datad (1194:1194:1194) (1254:1254:1254)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla31pla33M4T1_3) - (DELAY - (ABSOLUTE - (PORT dataa (717:717:717) (780:780:780)) - (PORT datab (376:376:376) (417:417:417)) - (PORT datac (1100:1100:1100) (1123:1123:1123)) - (PORT datad (1740:1740:1740) (1811:1811:1811)) + (PORT dataa (1201:1201:1201) (1224:1224:1224)) + (PORT datab (238:238:238) (291:291:291)) + (PORT datac (574:574:574) (597:597:597)) + (PORT datad (1616:1616:1616) (1655:1655:1655)) (IOPATH dataa combout (327:327:327) (347:347:347)) (IOPATH datab combout (331:331:331) (342:342:342)) (IOPATH datac combout (243:243:243) (241:241:241)) @@ -44540,645 +31725,24 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~3) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode244w\[2\]\~0) (DELAY (ABSOLUTE - (PORT dataa (999:999:999) (1037:1037:1037)) - (PORT datab (1148:1148:1148) (1181:1181:1181)) - (PORT datac (1118:1118:1118) (1156:1156:1156)) - (PORT datad (172:172:172) (198:198:198)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1747:1747:1747) (1768:1768:1768)) - (PORT datab (1063:1063:1063) (1181:1181:1181)) - (PORT datac (1205:1205:1205) (1277:1277:1277)) - (PORT datad (1152:1152:1152) (1188:1188:1188)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~2) - (DELAY - (ABSOLUTE - (PORT dataa (1745:1745:1745) (1764:1764:1764)) - (PORT datab (372:372:372) (420:420:420)) - (PORT datac (1499:1499:1499) (1632:1632:1632)) - (PORT datad (1111:1111:1111) (1140:1140:1140)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~4) - (DELAY - (ABSOLUTE - (PORT dataa (232:232:232) (279:279:279)) - (PORT datab (1037:1037:1037) (1088:1088:1088)) - (PORT datac (1095:1095:1095) (1134:1134:1134)) - (PORT datad (1073:1073:1073) (1110:1110:1110)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~6) - (DELAY - (ABSOLUTE - (PORT dataa (880:880:880) (904:904:904)) - (PORT datab (1509:1509:1509) (1569:1569:1569)) - (PORT datac (829:829:829) (848:848:848)) - (PORT datad (860:860:860) (875:875:875)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_we\~7) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (171:171:171) (205:205:205)) - (PORT datad (172:172:172) (198:198:198)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]\~50) - (DELAY - (ABSOLUTE - (PORT datac (1078:1078:1078) (1174:1174:1174)) - (PORT datad (1031:1031:1031) (1116:1116:1116)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]\~52) - (DELAY - (ABSOLUTE - (PORT dataa (403:403:403) (436:436:436)) - (PORT datab (968:968:968) (1056:1056:1056)) - (PORT datad (175:175:175) (200:200:200)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]\~48) - (DELAY - (ABSOLUTE - (PORT dataa (224:224:224) (280:280:280)) - (PORT datab (775:775:775) (874:874:874)) - (PORT datac (1366:1366:1366) (1453:1453:1453)) - (PORT datad (1546:1546:1546) (1637:1637:1637)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[2\]\~49) - (DELAY - (ABSOLUTE - (PORT dataa (345:345:345) (379:379:379)) - (PORT datab (222:222:222) (260:260:260)) - (PORT datad (739:739:739) (824:824:824)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (2308:2308:2308) (2488:2488:2488)) - (PORT datab (241:241:241) (322:322:322)) - (PORT datac (574:574:574) (621:621:621)) - (PORT datad (1325:1325:1325) (1345:1345:1345)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~57) - (DELAY - (ABSOLUTE - (PORT datab (965:965:965) (1048:1048:1048)) - (PORT datad (728:728:728) (839:839:839)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~58) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (246:246:246)) - (PORT datab (622:622:622) (672:672:672)) - (PORT datad (961:961:961) (1040:1040:1040)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1573:1573:1573)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~59) - (DELAY - (ABSOLUTE - (PORT dataa (489:489:489) (568:568:568)) - (PORT datab (664:664:664) (740:740:740)) - (PORT datac (606:606:606) (671:671:671)) - (PORT datad (721:721:721) (799:799:799)) - (IOPATH dataa combout (341:341:341) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~131) - (DELAY - (ABSOLUTE - (PORT dataa (447:447:447) (538:538:538)) - (PORT datab (342:342:342) (377:377:377)) - (PORT datad (260:260:260) (338:338:338)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~60) - (DELAY - (ABSOLUTE - (PORT dataa (792:792:792) (908:908:908)) - (PORT datab (1091:1091:1091) (1095:1095:1095)) - (PORT datad (617:617:617) (636:636:636)) - (IOPATH dataa combout (325:325:325) (328:328:328)) + (PORT datab (2065:2065:2065) (2202:2202:2202)) + (PORT datac (1304:1304:1304) (1449:1449:1449)) + (PORT datad (3045:3045:3045) (3237:3237:3237)) (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1573:1573:1573)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (1155:1155:1155) (1224:1224:1224)) - (PORT datab (240:240:240) (321:321:321)) - (PORT datac (568:568:568) (626:626:626)) - (PORT datad (553:553:553) (572:572:572)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]\~53) - (DELAY - (ABSOLUTE - (PORT datac (1077:1077:1077) (1170:1170:1170)) - (PORT datad (1031:1031:1031) (1112:1112:1112)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]\~55) - (DELAY - (ABSOLUTE - (PORT dataa (227:227:227) (285:285:285)) - (PORT datab (390:390:390) (410:410:410)) - (PORT datac (918:918:918) (988:988:988)) - (PORT datad (328:328:328) (348:348:348)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]\~56) - (DELAY - (ABSOLUTE - (PORT datab (969:969:969) (1059:1059:1059)) - (PORT datad (338:338:338) (357:357:357)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]\~54) - (DELAY - (ABSOLUTE - (PORT dataa (406:406:406) (439:439:439)) - (PORT datab (969:969:969) (1059:1059:1059)) - (PORT datad (195:195:195) (220:220:220)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~36) - (DELAY - (ABSOLUTE - (PORT dataa (244:244:244) (330:330:330)) - (PORT datab (242:242:242) (324:324:324)) - (PORT datac (559:559:559) (587:587:587)) - (PORT datad (556:556:556) (572:572:572)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~68) - (DELAY - (ABSOLUTE - (PORT dataa (963:963:963) (1040:1040:1040)) - (PORT datab (793:793:793) (911:911:911)) - (PORT datac (907:907:907) (1000:1000:1000)) - (PORT datad (764:764:764) (871:871:871)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~69) - (DELAY - (ABSOLUTE - (PORT dataa (358:358:358) (395:395:395)) - (PORT datab (737:737:737) (825:825:825)) - (PORT datad (589:589:589) (600:600:600)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (336:336:336) (332:332:332)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~70) - (DELAY - (ABSOLUTE - (PORT dataa (213:213:213) (262:262:262)) - (PORT datab (201:201:201) (241:241:241)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (353:353:353) (369:369:369)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~61) - (DELAY - (ABSOLUTE - (PORT datac (244:244:244) (324:324:324)) - (PORT datad (831:831:831) (879:879:879)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~62) - (DELAY - (ABSOLUTE - (PORT dataa (699:699:699) (764:764:764)) - (PORT datab (349:349:349) (382:382:382)) - (PORT datac (658:658:658) (727:727:727)) - (PORT datad (638:638:638) (705:705:705)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~64) - (DELAY - (ABSOLUTE - (PORT dataa (210:210:210) (257:257:257)) - (PORT datab (471:471:471) (546:546:546)) - (PORT datac (352:352:352) (381:381:381)) - (PORT datad (197:197:197) (232:232:232)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~65) - (DELAY - (ABSOLUTE - (PORT dataa (734:734:734) (824:824:824)) - (PORT datab (493:493:493) (577:577:577)) - (PORT datac (572:572:572) (608:608:608)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Selector13\~0) - (DELAY - (ABSOLUTE - (PORT dataa (747:747:747) (849:849:849)) - (PORT datab (773:773:773) (872:872:872)) - (PORT datad (959:959:959) (1036:1036:1036)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~66) - (DELAY - (ABSOLUTE - (PORT dataa (340:340:340) (370:370:370)) - (PORT datad (635:635:635) (675:675:675)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1530:1530:1530) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~38) - (DELAY - (ABSOLUTE - (PORT dataa (1664:1664:1664) (1689:1689:1689)) - (PORT datab (618:618:618) (678:678:678)) - (PORT datac (1058:1058:1058) (1128:1128:1128)) - (PORT datad (216:216:216) (284:284:284)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~39) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (634:634:634) (655:655:655)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (589:589:589) (603:603:603)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~104) - (DELAY - (ABSOLUTE - (PORT datab (1233:1233:1233) (1299:1299:1299)) - (PORT datac (655:655:655) (738:738:738)) - (PORT datad (1395:1395:1395) (1412:1412:1412)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.datain_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (947:947:947) (974:974:974)) + (PORT d[0] (985:985:985) (999:999:999)) (PORT clk (1850:1850:1850) (1877:1877:1877)) ) ) @@ -45188,22 +31752,22 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.addr_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1333:1333:1333) (1379:1379:1379)) - (PORT d[1] (1965:1965:1965) (2168:2168:2168)) - (PORT d[2] (3064:3064:3064) (3182:3182:3182)) - (PORT d[3] (2837:2837:2837) (3038:3038:3038)) - (PORT d[4] (2548:2548:2548) (2738:2738:2738)) - (PORT d[5] (2841:2841:2841) (3039:3039:3039)) - (PORT d[6] (1923:1923:1923) (2045:2045:2045)) - (PORT d[7] (2590:2590:2590) (2742:2742:2742)) - (PORT d[8] (3415:3415:3415) (3712:3712:3712)) - (PORT d[9] (1607:1607:1607) (1686:1686:1686)) - (PORT d[10] (5088:5088:5088) (5355:5355:5355)) - (PORT d[11] (1909:1909:1909) (2057:2057:2057)) - (PORT d[12] (1909:1909:1909) (2032:2032:2032)) + (PORT d[0] (2598:2598:2598) (2701:2701:2701)) + (PORT d[1] (974:974:974) (1037:1037:1037)) + (PORT d[2] (2642:2642:2642) (2868:2868:2868)) + (PORT d[3] (973:973:973) (1022:1022:1022)) + (PORT d[4] (745:745:745) (794:794:794)) + (PORT d[5] (1202:1202:1202) (1239:1239:1239)) + (PORT d[6] (1002:1002:1002) (1045:1045:1045)) + (PORT d[7] (2142:2142:2142) (2302:2302:2302)) + (PORT d[8] (1221:1221:1221) (1255:1255:1255)) + (PORT d[9] (1256:1256:1256) (1275:1275:1275)) + (PORT d[10] (1133:1133:1133) (1153:1153:1153)) + (PORT d[11] (1494:1494:1494) (1524:1524:1524)) + (PORT d[12] (2288:2288:2288) (2355:2355:2355)) (PORT clk (1847:1847:1847) (1873:1873:1873)) ) ) @@ -45213,10 +31777,10 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.we_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1221:1221:1221) (1217:1217:1217)) + (PORT d[0] (2238:2238:2238) (2178:2178:2178)) (PORT clk (1847:1847:1847) (1873:1873:1873)) ) ) @@ -45226,17 +31790,17 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.active_core_port_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.active_core_port_a) (DELAY (ABSOLUTE (PORT clk (1850:1850:1850) (1877:1877:1877)) - (PORT d[0] (2517:2517:2517) (2474:2474:2474)) + (PORT d[0] (1924:1924:1924) (1902:1902:1902)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.wpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.wpgen_a) (DELAY (ABSOLUTE (PORT clk (1851:1851:1851) (1878:1878:1878)) @@ -45246,7 +31810,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rpgen_a) (DELAY (ABSOLUTE (PORT clk (1851:1851:1851) (1878:1878:1878)) @@ -45256,7 +31820,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.ftpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.ftpgen_a) (DELAY (ABSOLUTE (PORT clk (1851:1851:1851) (1878:1878:1878)) @@ -45266,7 +31830,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rwpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rwpgen_a) (DELAY (ABSOLUTE (PORT clk (1851:1851:1851) (1878:1878:1878)) @@ -45276,7 +31840,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.dataout_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.dataout_a_register) (DELAY (ABSOLUTE (PORT clk (1810:1810:1810) (1836:1836:1836)) @@ -45290,7 +31854,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.active_core_port_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.active_core_port_b) (DELAY (ABSOLUTE (PORT clk (995:995:995) (999:999:999)) @@ -45299,7 +31863,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rpgen_b) (DELAY (ABSOLUTE (PORT clk (996:996:996) (1000:1000:1000)) @@ -45308,7 +31872,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.ftpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.ftpgen_b) (DELAY (ABSOLUTE (PORT clk (996:996:996) (1000:1000:1000)) @@ -45318,7 +31882,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rwpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a17.rwpgen_b) (DELAY (ABSOLUTE (PORT clk (996:996:996) (1000:1000:1000)) @@ -45327,164 +31891,85 @@ ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.datain_a_register) + (CELLTYPE "dffeas") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|address_reg_a\[1\]) (DELAY (ABSOLUTE - (PORT d[0] (704:704:704) (727:727:727)) - (PORT clk (1858:1858:1858) (1884:1884:1884)) + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT asdata (2072:2072:2072) (2099:2099:2099)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) + (HOLD asdata (posedge clk) (157:157:157)) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) + (CELLTYPE "dffeas") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|out_address_reg_a\[1\]) (DELAY (ABSOLUTE - (PORT d[0] (1274:1274:1274) (1301:1301:1301)) - (PORT d[1] (2099:2099:2099) (2330:2330:2330)) - (PORT d[2] (1248:1248:1248) (1286:1286:1286)) - (PORT d[3] (1307:1307:1307) (1357:1357:1357)) - (PORT d[4] (2610:2610:2610) (2833:2833:2833)) - (PORT d[5] (3471:3471:3471) (3676:3676:3676)) - (PORT d[6] (1323:1323:1323) (1420:1420:1420)) - (PORT d[7] (2887:2887:2887) (3061:3061:3061)) - (PORT d[8] (985:985:985) (1023:1023:1023)) - (PORT d[9] (1296:1296:1296) (1359:1359:1359)) - (PORT d[10] (1357:1357:1357) (1455:1455:1455)) - (PORT d[11] (2476:2476:2476) (2609:2609:2609)) - (PORT d[12] (1610:1610:1610) (1711:1711:1711)) - (PORT clk (1855:1855:1855) (1880:1880:1880)) + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT asdata (2010:2010:2010) (2103:2103:2103)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) + (HOLD asdata (posedge clk) (157:157:157)) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.we_a_register) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[1\]\~0) (DELAY (ABSOLUTE - (PORT d[0] (979:979:979) (953:953:953)) - (PORT clk (1855:1855:1855) (1880:1880:1880)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1884:1884:1884)) - (PORT d[0] (1492:1492:1492) (1460:1460:1460)) + (PORT dataa (600:600:600) (611:611:611)) + (PORT datab (1169:1169:1169) (1231:1231:1231)) + (PORT datac (851:851:851) (858:858:858)) + (PORT datad (1375:1375:1375) (1438:1438:1438)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_a) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode252w\[2\]) (DELAY (ABSOLUTE - (PORT clk (1859:1859:1859) (1885:1885:1885)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + (PORT dataa (1201:1201:1201) (1224:1224:1224)) + (PORT datab (242:242:242) (296:296:296)) + (PORT datac (574:574:574) (599:599:599)) + (PORT datad (1614:1614:1614) (1659:1659:1659)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|decode3\|w_anode252w\[2\]\~0) (DELAY (ABSOLUTE - (PORT clk (1859:1859:1859) (1885:1885:1885)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1859:1859:1859) (1885:1885:1885)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1859:1859:1859) (1885:1885:1885)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + (PORT datab (2067:2067:2067) (2204:2204:2204)) + (PORT datac (1304:1304:1304) (1447:1447:1447)) + (PORT datad (3040:3040:3040) (3233:3233:3233)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.datain_a_register) (DELAY (ABSOLUTE - (PORT clk (1818:1818:1818) (1843:1843:1843)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1003:1003:1003) (1006:1006:1006)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1004:1004:1004) (1007:1007:1007)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1004:1004:1004) (1007:1007:1007)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1004:1004:1004) (1007:1007:1007)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (947:947:947) (973:973:973)) + (PORT d[0] (1016:1016:1016) (1054:1054:1054)) (PORT clk (1852:1852:1852) (1879:1879:1879)) ) ) @@ -45494,22 +31979,22 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.addr_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1343:1343:1343) (1413:1413:1413)) - (PORT d[1] (3163:3163:3163) (3436:3436:3436)) - (PORT d[2] (3532:3532:3532) (3625:3625:3625)) - (PORT d[3] (2837:2837:2837) (3043:3043:3043)) - (PORT d[4] (2558:2558:2558) (2781:2781:2781)) - (PORT d[5] (2869:2869:2869) (3072:3072:3072)) - (PORT d[6] (1676:1676:1676) (1759:1759:1759)) - (PORT d[7] (1505:1505:1505) (1586:1586:1586)) - (PORT d[8] (3442:3442:3442) (3720:3720:3720)) - (PORT d[9] (3231:3231:3231) (3382:3382:3382)) - (PORT d[10] (5089:5089:5089) (5374:5374:5374)) - (PORT d[11] (1942:1942:1942) (2100:2100:2100)) - (PORT d[12] (1901:1901:1901) (2017:2017:2017)) + (PORT d[0] (2322:2322:2322) (2426:2426:2426)) + (PORT d[1] (984:984:984) (1039:1039:1039)) + (PORT d[2] (2633:2633:2633) (2847:2847:2847)) + (PORT d[3] (2802:2802:2802) (2969:2969:2969)) + (PORT d[4] (733:733:733) (772:772:772)) + (PORT d[5] (1238:1238:1238) (1298:1298:1298)) + (PORT d[6] (985:985:985) (1001:1001:1001)) + (PORT d[7] (1894:1894:1894) (2056:2056:2056)) + (PORT d[8] (1208:1208:1208) (1253:1253:1253)) + (PORT d[9] (971:971:971) (1010:1010:1010)) + (PORT d[10] (666:666:666) (702:702:702)) + (PORT d[11] (1500:1500:1500) (1540:1540:1540)) + (PORT d[12] (2302:2302:2302) (2344:2344:2344)) (PORT clk (1849:1849:1849) (1875:1875:1875)) ) ) @@ -45519,10 +32004,10 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.we_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1717:1717:1717) (1648:1648:1648)) + (PORT d[0] (1755:1755:1755) (1733:1733:1733)) (PORT clk (1849:1849:1849) (1875:1875:1875)) ) ) @@ -45532,17 +32017,17 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.active_core_port_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.active_core_port_a) (DELAY (ABSOLUTE (PORT clk (1852:1852:1852) (1879:1879:1879)) - (PORT d[0] (2052:2052:2052) (2017:2017:2017)) + (PORT d[0] (1916:1916:1916) (1893:1893:1893)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.wpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.wpgen_a) (DELAY (ABSOLUTE (PORT clk (1853:1853:1853) (1880:1880:1880)) @@ -45552,7 +32037,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rpgen_a) (DELAY (ABSOLUTE (PORT clk (1853:1853:1853) (1880:1880:1880)) @@ -45562,7 +32047,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.ftpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.ftpgen_a) (DELAY (ABSOLUTE (PORT clk (1853:1853:1853) (1880:1880:1880)) @@ -45572,7 +32057,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rwpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rwpgen_a) (DELAY (ABSOLUTE (PORT clk (1853:1853:1853) (1880:1880:1880)) @@ -45582,7 +32067,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.dataout_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.dataout_a_register) (DELAY (ABSOLUTE (PORT clk (1812:1812:1812) (1838:1838:1838)) @@ -45596,7 +32081,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.active_core_port_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.active_core_port_b) (DELAY (ABSOLUTE (PORT clk (997:997:997) (1001:1001:1001)) @@ -45605,7 +32090,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rpgen_b) (DELAY (ABSOLUTE (PORT clk (998:998:998) (1002:1002:1002)) @@ -45614,7 +32099,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.ftpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.ftpgen_b) (DELAY (ABSOLUTE (PORT clk (998:998:998) (1002:1002:1002)) @@ -45624,7 +32109,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rwpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a25.rwpgen_b) (DELAY (ABSOLUTE (PORT clk (998:998:998) (1002:1002:1002)) @@ -45633,12 +32118,40 @@ ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[1\]\~1) (DELAY (ABSOLUTE - (PORT d[0] (1152:1152:1152) (1168:1168:1168)) - (PORT clk (1849:1849:1849) (1876:1876:1876)) + (PORT dataa (1142:1142:1142) (1139:1139:1139)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (1584:1584:1584) (1649:1649:1649)) + (PORT datad (1176:1176:1176) (1205:1205:1205)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2019:2019:2019) (2126:2126:2126)) + (PORT d[1] (1666:1666:1666) (1726:1726:1726)) + (PORT d[2] (2398:2398:2398) (2532:2532:2532)) + (PORT d[3] (2708:2708:2708) (2856:2856:2856)) + (PORT d[4] (1028:1028:1028) (1106:1106:1106)) + (PORT d[5] (1544:1544:1544) (1604:1604:1604)) + (PORT d[6] (3201:3201:3201) (3239:3239:3239)) + (PORT d[7] (1837:1837:1837) (1963:1963:1963)) + (PORT d[8] (1554:1554:1554) (1611:1611:1611)) + (PORT d[9] (3400:3400:3400) (3677:3677:3677)) + (PORT d[10] (1240:1240:1240) (1281:1281:1281)) + (PORT d[11] (1473:1473:1473) (1515:1515:1515)) + (PORT d[12] (1982:1982:1982) (2007:2007:2007)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) ) ) (TIMINGCHECK @@ -45647,98 +32160,30 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) (DELAY (ABSOLUTE - (PORT d[0] (3672:3672:3672) (3852:3852:3852)) - (PORT d[1] (1686:1686:1686) (1851:1851:1851)) - (PORT d[2] (1971:1971:1971) (2046:2046:2046)) - (PORT d[3] (2163:2163:2163) (2263:2263:2263)) - (PORT d[4] (2177:2177:2177) (2306:2306:2306)) - (PORT d[5] (1373:1373:1373) (1485:1485:1485)) - (PORT d[6] (1492:1492:1492) (1541:1541:1541)) - (PORT d[7] (1731:1731:1731) (1802:1802:1802)) - (PORT d[8] (3606:3606:3606) (3855:3855:3855)) - (PORT d[9] (3144:3144:3144) (3281:3281:3281)) - (PORT d[10] (3176:3176:3176) (3363:3363:3363)) - (PORT d[11] (2072:2072:2072) (2195:2195:2195)) - (PORT d[12] (1417:1417:1417) (1455:1455:1455)) - (PORT clk (1846:1846:1846) (1872:1872:1872)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1662:1662:1662) (1645:1645:1645)) - (PORT clk (1846:1846:1846) (1872:1872:1872)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1849:1849:1849) (1876:1876:1876)) - (PORT d[0] (2686:2686:2686) (2681:2681:2681)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) + (PORT d[0] (2414:2414:2414) (2383:2383:2383)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1850:1850:1850) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1877:1877:1877)) + (PORT clk (1858:1858:1858) (1884:1884:1884)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1850:1850:1850) (1877:1877:1877)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1809:1809:1809) (1835:1835:1835)) + (PORT clk (1820:1820:1820) (1846:1846:1846)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -45749,395 +32194,711 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (994:994:994) (998:998:998)) + (PORT clk (1005:1005:1005) (1009:1009:1009)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (995:995:995) (999:999:999)) + (PORT clk (1006:1006:1006) (1010:1010:1010)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (995:995:995) (999:999:999)) + (PORT clk (1006:1006:1006) (1010:1010:1010)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (995:995:995) (999:999:999)) + (PORT clk (1006:1006:1006) (1010:1010:1010)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1803:1803:1803) (1910:1910:1910)) + (PORT d[1] (2308:2308:2308) (2393:2393:2393)) + (PORT d[2] (2037:2037:2037) (2203:2203:2203)) + (PORT d[3] (1874:1874:1874) (1990:1990:1990)) + (PORT d[4] (2328:2328:2328) (2369:2369:2369)) + (PORT d[5] (1694:1694:1694) (1782:1782:1782)) + (PORT d[6] (1733:1733:1733) (1817:1817:1817)) + (PORT d[7] (1535:1535:1535) (1647:1647:1647)) + (PORT d[8] (2183:2183:2183) (2307:2307:2307)) + (PORT d[9] (3031:3031:3031) (3242:3242:3242)) + (PORT d[10] (1585:1585:1585) (1671:1671:1671)) + (PORT d[11] (1956:1956:1956) (2023:2023:2023)) + (PORT d[12] (2060:2060:2060) (2089:2089:2089)) + (PORT clk (1848:1848:1848) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1875:1875:1875)) + (PORT d[0] (2543:2543:2543) (2570:2570:2570)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1811:1811:1811) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE CLOCK_50\~inputclkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (154:154:154) (138:138:138)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~43) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|address_reg_a\[0\]\~feeder) (DELAY (ABSOLUTE - (PORT dataa (980:980:980) (1035:1035:1035)) - (PORT datab (1190:1190:1190) (1238:1238:1238)) - (PORT datac (820:820:820) (836:836:836)) - (PORT datad (1047:1047:1047) (1047:1047:1047)) - (IOPATH dataa combout (341:341:341) (367:367:367)) + (PORT datad (1548:1548:1548) (1588:1588:1588)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|address_reg_a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1529:1529:1529)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1516:1516:1516) (1529:1529:1529)) + (PORT asdata (560:560:560) (634:634:634)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (264:264:264) (350:350:350)) + (PORT datab (2598:2598:2598) (2766:2766:2766)) + (PORT datad (1596:1596:1596) (1730:1730:1730)) + (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~44) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|decode2\|eq_node\[1\]\~0) (DELAY (ABSOLUTE - (PORT dataa (1175:1175:1175) (1168:1168:1168)) - (PORT datab (1602:1602:1602) (1692:1692:1692)) - (PORT datac (1163:1163:1163) (1158:1158:1158)) - (PORT datad (312:312:312) (328:328:328)) + (PORT dataa (1201:1201:1201) (1220:1220:1220)) + (PORT datab (238:238:238) (292:292:292)) + (PORT datac (574:574:574) (597:597:597)) + (PORT datad (1616:1616:1616) (1655:1655:1655)) (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vram_address\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (927:927:927) (1008:1008:1008)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vram_address\~0) + (DELAY + (ABSOLUTE + (PORT dataa (774:774:774) (855:855:855)) + (PORT datab (754:754:754) (825:825:825)) + (PORT datac (1156:1156:1156) (1215:1215:1215)) + (PORT datad (683:683:683) (750:750:750)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[0\]) (DELAY (ABSOLUTE - (PORT d[0] (3036:3036:3036) (3209:3209:3209)) - (PORT d[1] (2901:2901:2901) (3127:3127:3127)) - (PORT d[2] (1663:1663:1663) (1761:1761:1761)) - (PORT d[3] (1512:1512:1512) (1583:1583:1583)) - (PORT d[4] (1858:1858:1858) (1967:1967:1967)) - (PORT d[5] (1341:1341:1341) (1451:1451:1451)) - (PORT d[6] (1141:1141:1141) (1162:1162:1162)) - (PORT d[7] (1474:1474:1474) (1532:1532:1532)) - (PORT d[8] (2472:2472:2472) (2678:2678:2678)) - (PORT d[9] (3827:3827:3827) (3998:3998:3998)) - (PORT d[10] (2576:2576:2576) (2725:2725:2725)) - (PORT d[11] (1801:1801:1801) (1882:1882:1882)) - (PORT d[12] (2041:2041:2041) (2064:2064:2064)) - (PORT clk (1849:1849:1849) (1875:1875:1875)) + (PORT clk (1538:1538:1538) (1549:1549:1549)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1195:1195:1195) (1177:1177:1177)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vram_address\[1\]\~feeder) (DELAY (ABSOLUTE - (PORT clk (1849:1849:1849) (1875:1875:1875)) - (PORT d[0] (1267:1267:1267) (1274:1274:1274)) + (PORT datad (908:908:908) (960:960:960)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[1\]) (DELAY (ABSOLUTE - (PORT clk (1850:1850:1850) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1812:1812:1812) (1838:1838:1838)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + (PORT clk (1538:1538:1538) (1549:1549:1549)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1195:1195:1195) (1177:1177:1177)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vram_address\[2\]\~4) (DELAY (ABSOLUTE - (PORT clk (997:997:997) (1001:1001:1001)) + (PORT datac (742:742:742) (821:821:821)) + (IOPATH datac combout (241:241:241) (241:241:241)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[2\]) (DELAY (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1634:1634:1634) (1680:1680:1680)) - (PORT clk (1866:1866:1866) (1893:1893:1893)) + (PORT clk (1538:1538:1538) (1549:1549:1549)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1195:1195:1195) (1177:1177:1177)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add3\~0) (DELAY (ABSOLUTE - (PORT d[0] (2598:2598:2598) (2696:2696:2696)) - (PORT d[1] (2070:2070:2070) (2298:2298:2298)) - (PORT d[2] (2574:2574:2574) (2730:2730:2730)) - (PORT d[3] (2266:2266:2266) (2351:2351:2351)) - (PORT d[4] (2949:2949:2949) (3214:3214:3214)) - (PORT d[5] (2088:2088:2088) (2293:2293:2293)) - (PORT d[6] (1571:1571:1571) (1677:1677:1677)) - (PORT d[7] (2825:2825:2825) (2918:2918:2918)) - (PORT d[8] (2797:2797:2797) (3045:3045:3045)) - (PORT d[9] (2076:2076:2076) (2185:2185:2185)) - (PORT d[10] (1851:1851:1851) (1973:1973:1973)) - (PORT d[11] (3686:3686:3686) (3803:3803:3803)) - (PORT d[12] (1884:1884:1884) (1967:1967:1967)) - (PORT clk (1863:1863:1863) (1889:1889:1889)) + (PORT datac (743:743:743) (822:822:822)) + (PORT datad (1123:1123:1123) (1176:1176:1176)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1538:1538:1538) (1549:1549:1549)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1195:1195:1195) (1177:1177:1177)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.we_a_register) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add3\~1) (DELAY (ABSOLUTE - (PORT d[0] (3175:3175:3175) (3145:3145:3145)) - (PORT clk (1863:1863:1863) (1889:1889:1889)) + (PORT dataa (959:959:959) (1026:1026:1026)) + (PORT datac (742:742:742) (820:820:820)) + (PORT datad (1122:1122:1122) (1177:1177:1177)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1538:1538:1538) (1549:1549:1549)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1195:1195:1195) (1177:1177:1177)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~0) (DELAY (ABSOLUTE - (PORT clk (1866:1866:1866) (1893:1893:1893)) - (PORT d[0] (2870:2870:2870) (2913:2913:2913)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1867:1867:1867) (1894:1894:1894)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1867:1867:1867) (1894:1894:1894)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1867:1867:1867) (1894:1894:1894)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1867:1867:1867) (1894:1894:1894)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1821:1821:1821) (1818:1818:1818)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2160:2160:2160) (2219:2219:2219)) - (PORT clk (1831:1831:1831) (1824:1824:1824)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4537:4537:4537) (4504:4504:4504)) - (PORT d[1] (4325:4325:4325) (4356:4356:4356)) - (PORT d[2] (4543:4543:4543) (4609:4609:4609)) - (PORT d[3] (4478:4478:4478) (4499:4499:4499)) - (PORT d[4] (4324:4324:4324) (4305:4305:4305)) - (PORT d[5] (4367:4367:4367) (4410:4410:4410)) - (PORT d[6] (4631:4631:4631) (4697:4697:4697)) - (PORT d[7] (4151:4151:4151) (4116:4116:4116)) - (PORT d[8] (4445:4445:4445) (4476:4476:4476)) - (PORT d[9] (4629:4629:4629) (4823:4823:4823)) - (PORT d[10] (4475:4475:4475) (4482:4482:4482)) - (PORT d[11] (4668:4668:4668) (4671:4671:4671)) - (PORT d[12] (4491:4491:4491) (4515:4515:4515)) - (PORT clk (1827:1827:1827) (1820:1820:1820)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1831:1831:1831) (1824:1824:1824)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1832:1832:1832) (1825:1825:1825)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1832:1832:1832) (1825:1825:1825)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1832:1832:1832) (1825:1825:1825)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1832:1832:1832) (1825:1825:1825)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + (PORT dataa (932:932:932) (998:998:998)) + (PORT datab (1249:1249:1249) (1307:1307:1307)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~40) + (INSTANCE ula_\|video_\|Add4\~2) (DELAY (ABSOLUTE - (PORT dataa (1345:1345:1345) (1398:1398:1398)) - (PORT datab (279:279:279) (367:367:367)) - (PORT datac (1350:1350:1350) (1376:1376:1376)) - (PORT datad (1465:1465:1465) (1526:1526:1526)) - (IOPATH dataa combout (356:356:356) (368:368:368)) + (PORT datab (982:982:982) (1044:1044:1044)) (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~4) + (DELAY + (ABSOLUTE + (PORT datab (1173:1173:1173) (1231:1231:1231)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~6) + (DELAY + (ABSOLUTE + (PORT datab (762:762:762) (823:823:823)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1537:1537:1537) (1549:1549:1549)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1273:1273:1273) (1275:1275:1275)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~8) + (DELAY + (ABSOLUTE + (PORT datab (949:949:949) (1027:1027:1027)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1537:1537:1537) (1549:1549:1549)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1273:1273:1273) (1275:1275:1275)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~10) + (DELAY + (ABSOLUTE + (PORT dataa (960:960:960) (1019:1019:1019)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1537:1537:1537) (1549:1549:1549)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1273:1273:1273) (1275:1275:1275)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1136:1136:1136) (1207:1207:1207)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Selector6\~0) + (DELAY + (ABSOLUTE + (PORT datab (947:947:947) (1025:1025:1025)) + (PORT datac (317:317:317) (346:346:346)) + (PORT datad (346:346:346) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vram_address\[9\]\~1) (DELAY (ABSOLUTE - (PORT d[0] (1584:1584:1584) (1645:1645:1645)) - (PORT clk (1870:1870:1870) (1897:1897:1897)) + (PORT dataa (772:772:772) (854:854:854)) + (PORT datab (753:753:753) (824:824:824)) + (PORT datac (1159:1159:1159) (1218:1218:1218)) + (PORT datad (684:684:684) (753:753:753)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1538:1538:1538) (1549:1549:1549)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1273:1273:1273) (1272:1272:1272)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Add4\~14) + (DELAY + (ABSOLUTE + (PORT datad (902:902:902) (975:975:975)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Selector5\~0) + (DELAY + (ABSOLUTE + (PORT datab (944:944:944) (1027:1027:1027)) + (PORT datac (344:344:344) (370:370:370)) + (PORT datad (346:346:346) (370:370:370)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1538:1538:1538) (1549:1549:1549)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1273:1273:1273) (1272:1272:1272)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vram_address\[10\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (765:765:765) (847:847:847)) + (PORT datab (750:750:750) (819:819:819)) + (PORT datac (1163:1163:1163) (1219:1219:1219)) + (PORT datad (688:688:688) (752:752:752)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|vram_address\[10\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (776:776:776) (857:857:857)) + (PORT datab (615:615:615) (632:632:632)) + (PORT datad (176:176:176) (202:202:202)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1537:1537:1537) (1549:1549:1549)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Selector3\~0) + (DELAY + (ABSOLUTE + (PORT datac (911:911:911) (989:989:989)) + (PORT datad (350:350:350) (370:370:370)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1538:1538:1538) (1549:1549:1549)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1273:1273:1273) (1272:1272:1272)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|Selector2\~0) + (DELAY + (ABSOLUTE + (PORT datac (911:911:911) (990:990:990)) + (PORT datad (347:347:347) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|vram_address\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1538:1538:1538) (1549:1549:1549)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1273:1273:1273) (1272:1272:1272)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1380:1380:1380) (1460:1460:1460)) + (PORT clk (1860:1860:1860) (1888:1888:1888)) ) ) (TIMINGCHECK @@ -46146,23 +32907,23 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2320:2320:2320) (2387:2387:2387)) - (PORT d[1] (2054:2054:2054) (2261:2261:2261)) - (PORT d[2] (2320:2320:2320) (2490:2490:2490)) - (PORT d[3] (2275:2275:2275) (2437:2437:2437)) - (PORT d[4] (2932:2932:2932) (3188:3188:3188)) - (PORT d[5] (2382:2382:2382) (2576:2576:2576)) - (PORT d[6] (1862:1862:1862) (1984:1984:1984)) - (PORT d[7] (2524:2524:2524) (2619:2619:2619)) - (PORT d[8] (3132:3132:3132) (3396:3396:3396)) - (PORT d[9] (1782:1782:1782) (1897:1897:1897)) - (PORT d[10] (1810:1810:1810) (1908:1908:1908)) - (PORT d[11] (2927:2927:2927) (3048:3048:3048)) - (PORT d[12] (1876:1876:1876) (1989:1989:1989)) - (PORT clk (1867:1867:1867) (1893:1893:1893)) + (PORT d[0] (2750:2750:2750) (2962:2962:2962)) + (PORT d[1] (3054:3054:3054) (3174:3174:3174)) + (PORT d[2] (1898:1898:1898) (2003:2003:2003)) + (PORT d[3] (2672:2672:2672) (2885:2885:2885)) + (PORT d[4] (2971:2971:2971) (3095:3095:3095)) + (PORT d[5] (3481:3481:3481) (3602:3602:3602)) + (PORT d[6] (2165:2165:2165) (2264:2264:2264)) + (PORT d[7] (1936:1936:1936) (2113:2113:2113)) + (PORT d[8] (2731:2731:2731) (2831:2831:2831)) + (PORT d[9] (3077:3077:3077) (3162:3162:3162)) + (PORT d[10] (3386:3386:3386) (3609:3609:3609)) + (PORT d[11] (2969:2969:2969) (3152:3152:3152)) + (PORT d[12] (2048:2048:2048) (2158:2158:2158)) + (PORT clk (1857:1857:1857) (1884:1884:1884)) ) ) (TIMINGCHECK @@ -46171,11 +32932,11 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.we_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2203:2203:2203) (2195:2195:2195)) - (PORT clk (1867:1867:1867) (1893:1893:1893)) + (PORT d[0] (3102:3102:3102) (3112:3112:3112)) + (PORT clk (1857:1857:1857) (1884:1884:1884)) ) ) (TIMINGCHECK @@ -46184,60 +32945,60 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1870:1870:1870) (1897:1897:1897)) - (PORT d[0] (3171:3171:3171) (3110:3110:3110)) + (PORT clk (1860:1860:1860) (1888:1888:1888)) + (PORT d[0] (3359:3359:3359) (3390:3390:3390)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1871:1871:1871) (1898:1898:1898)) + (PORT clk (1861:1861:1861) (1889:1889:1889)) (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1871:1871:1871) (1898:1898:1898)) + (PORT clk (1861:1861:1861) (1889:1889:1889)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1871:1871:1871) (1898:1898:1898)) + (PORT clk (1861:1861:1861) (1889:1889:1889)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1871:1871:1871) (1898:1898:1898)) + (PORT clk (1861:1861:1861) (1889:1889:1889)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1825:1825:1825) (1822:1822:1822)) + (PORT clk (1815:1815:1815) (1813:1813:1813)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -46248,11 +33009,11 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_b_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.datain_b_register) (DELAY (ABSOLUTE - (PORT d[0] (2476:2476:2476) (2528:2528:2528)) - (PORT clk (1835:1835:1835) (1828:1828:1828)) + (PORT d[0] (2696:2696:2696) (2893:2893:2893)) + (PORT clk (1825:1825:1825) (1819:1819:1819)) ) ) (TIMINGCHECK @@ -46261,23 +33022,23 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_b_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.addr_b_register) (DELAY (ABSOLUTE - (PORT d[0] (4504:4504:4504) (4508:4508:4508)) - (PORT d[1] (4109:4109:4109) (4118:4118:4118)) - (PORT d[2] (4505:4505:4505) (4547:4547:4547)) - (PORT d[3] (4566:4566:4566) (4624:4624:4624)) - (PORT d[4] (4563:4563:4563) (4541:4541:4541)) - (PORT d[5] (4668:4668:4668) (4705:4705:4705)) - (PORT d[6] (4650:4650:4650) (4703:4703:4703)) - (PORT d[7] (4197:4197:4197) (4161:4161:4161)) - (PORT d[8] (4693:4693:4693) (4743:4743:4743)) - (PORT d[9] (4535:4535:4535) (4748:4748:4748)) - (PORT d[10] (4537:4537:4537) (4522:4522:4522)) - (PORT d[11] (4499:4499:4499) (4551:4551:4551)) - (PORT d[12] (4595:4595:4595) (4623:4623:4623)) - (PORT clk (1831:1831:1831) (1824:1824:1824)) + (PORT d[0] (4089:4089:4089) (4122:4122:4122)) + (PORT d[1] (4121:4121:4121) (4097:4097:4097)) + (PORT d[2] (4114:4114:4114) (4135:4135:4135)) + (PORT d[3] (4139:4139:4139) (4213:4213:4213)) + (PORT d[4] (4181:4181:4181) (4258:4258:4258)) + (PORT d[5] (4447:4447:4447) (4531:4531:4531)) + (PORT d[6] (4238:4238:4238) (4316:4316:4316)) + (PORT d[7] (4193:4193:4193) (4288:4288:4288)) + (PORT d[8] (4190:4190:4190) (4234:4234:4234)) + (PORT d[9] (4277:4277:4277) (4323:4323:4323)) + (PORT d[10] (4109:4109:4109) (4115:4115:4115)) + (PORT d[11] (4356:4356:4356) (4399:4399:4399)) + (PORT d[12] (4034:4034:4034) (4089:4089:4089)) + (PORT clk (1821:1821:1821) (1815:1815:1815)) ) ) (TIMINGCHECK @@ -46286,59 +33047,276 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (1835:1835:1835) (1828:1828:1828)) + (PORT clk (1825:1825:1825) (1819:1819:1819)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.wpgen_b) (DELAY (ABSOLUTE - (PORT clk (1836:1836:1836) (1829:1829:1829)) + (PORT clk (1826:1826:1826) (1820:1820:1820)) (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1836:1836:1836) (1829:1829:1829)) + (PORT clk (1826:1826:1826) (1820:1820:1820)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1826:1826:1826) (1820:1820:1820)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1826:1826:1826) (1820:1820:1820)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|decode2\|eq_node\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1197:1197:1197) (1221:1221:1221)) + (PORT datab (242:242:242) (297:297:297)) + (PORT datac (571:571:571) (599:599:599)) + (PORT datad (1614:1614:1614) (1658:1658:1658)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1598:1598:1598) (1668:1668:1668)) + (PORT clk (1870:1870:1870) (1896:1896:1896)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2743:2743:2743) (2934:2934:2934)) + (PORT d[1] (2708:2708:2708) (2829:2829:2829)) + (PORT d[2] (2186:2186:2186) (2311:2311:2311)) + (PORT d[3] (2324:2324:2324) (2514:2514:2514)) + (PORT d[4] (2669:2669:2669) (2771:2771:2771)) + (PORT d[5] (3184:3184:3184) (3303:3303:3303)) + (PORT d[6] (2450:2450:2450) (2566:2566:2566)) + (PORT d[7] (1984:1984:1984) (2179:2179:2179)) + (PORT d[8] (2430:2430:2430) (2505:2505:2505)) + (PORT d[9] (2673:2673:2673) (2782:2782:2782)) + (PORT d[10] (4100:4100:4100) (4359:4359:4359)) + (PORT d[11] (2717:2717:2717) (2910:2910:2910)) + (PORT d[12] (2586:2586:2586) (2706:2706:2706)) + (PORT clk (1867:1867:1867) (1892:1892:1892)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2496:2496:2496) (2533:2533:2533)) + (PORT clk (1867:1867:1867) (1892:1892:1892)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1870:1870:1870) (1896:1896:1896)) + (PORT d[0] (3724:3724:3724) (3665:3665:3665)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1871:1871:1871) (1897:1897:1897)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1871:1871:1871) (1897:1897:1897)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1871:1871:1871) (1897:1897:1897)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1871:1871:1871) (1897:1897:1897)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1825:1825:1825) (1821:1821:1821)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2962:2962:2962) (3172:3172:3172)) + (PORT clk (1835:1835:1835) (1827:1827:1827)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4063:4063:4063) (4054:4054:4054)) + (PORT d[1] (4098:4098:4098) (4072:4072:4072)) + (PORT d[2] (4134:4134:4134) (4164:4164:4164)) + (PORT d[3] (4116:4116:4116) (4184:4184:4184)) + (PORT d[4] (4210:4210:4210) (4304:4304:4304)) + (PORT d[5] (4215:4215:4215) (4252:4252:4252)) + (PORT d[6] (4326:4326:4326) (4369:4369:4369)) + (PORT d[7] (4037:4037:4037) (4096:4096:4096)) + (PORT d[8] (4327:4327:4327) (4350:4350:4350)) + (PORT d[9] (4214:4214:4214) (4279:4279:4279)) + (PORT d[10] (4097:4097:4097) (4102:4102:4102)) + (PORT d[11] (4290:4290:4290) (4257:4257:4257)) + (PORT d[12] (4221:4221:4221) (4283:4283:4283)) + (PORT clk (1831:1831:1831) (1823:1823:1823)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1835:1835:1835) (1827:1827:1827)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1836:1836:1836) (1828:1828:1828)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1836:1836:1836) (1828:1828:1828)) (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (1836:1836:1836) (1829:1829:1829)) + (PORT clk (1836:1836:1836) (1828:1828:1828)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (1836:1836:1836) (1829:1829:1829)) + (PORT clk (1836:1836:1836) (1828:1828:1828)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_b_register) + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_b_register) (DELAY (ABSOLUTE - (PORT clk (1827:1827:1827) (1824:1824:1824)) + (PORT clk (1827:1827:1827) (1823:1823:1823)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -46347,144 +33325,47 @@ (HOLD d (posedge clk) (159:159:159)) ) ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (987:987:987) (1035:1035:1035)) - (PORT d[1] (989:989:989) (1045:1045:1045)) - (PORT d[2] (1232:1232:1232) (1248:1248:1248)) - (PORT d[3] (1325:1325:1325) (1386:1386:1386)) - (PORT d[4] (2598:2598:2598) (2808:2808:2808)) - (PORT d[5] (2981:2981:2981) (3208:3208:3208)) - (PORT d[6] (983:983:983) (1027:1027:1027)) - (PORT d[7] (1279:1279:1279) (1356:1356:1356)) - (PORT d[8] (1032:1032:1032) (1055:1055:1055)) - (PORT d[9] (975:975:975) (1020:1020:1020)) - (PORT d[10] (1319:1319:1319) (1384:1384:1384)) - (PORT d[11] (2558:2558:2558) (2742:2742:2742)) - (PORT d[12] (1296:1296:1296) (1368:1368:1368)) - (PORT clk (1857:1857:1857) (1884:1884:1884)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1857:1857:1857) (1884:1884:1884)) - (PORT d[0] (574:574:574) (581:581:581)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1858:1858:1858) (1885:1885:1885)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1820:1820:1820) (1847:1847:1847)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1005:1005:1005) (1010:1010:1010)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1011:1011:1011)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1011:1011:1011)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1006:1006:1006) (1011:1011:1011)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~41) + (INSTANCE Selector1\~0) (DELAY (ABSOLUTE - (PORT dataa (1284:1284:1284) (1294:1294:1294)) - (PORT datab (865:865:865) (914:914:914)) - (PORT datac (861:861:861) (866:866:866)) - (PORT datad (181:181:181) (211:211:211)) + (PORT dataa (1388:1388:1388) (1516:1516:1516)) + (PORT datab (866:866:866) (882:882:882)) + (PORT datac (1443:1443:1443) (1490:1490:1490)) + (PORT datad (1435:1435:1435) (1479:1479:1479)) (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~42) + (INSTANCE Selector1\~1) (DELAY (ABSOLUTE - (PORT dataa (209:209:209) (255:255:255)) - (PORT datab (282:282:282) (370:370:370)) - (PORT datac (1627:1627:1627) (1645:1645:1645)) + (PORT dataa (1389:1389:1389) (1516:1516:1516)) + (PORT datab (1129:1129:1129) (1178:1178:1178)) + (PORT datac (1393:1393:1393) (1412:1412:1412)) (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (341:341:341) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~105) + (INSTANCE D\[1\]\~81) (DELAY (ABSOLUTE - (PORT dataa (199:199:199) (242:242:242)) - (PORT datab (928:928:928) (981:981:981)) - (PORT datac (1193:1193:1193) (1255:1255:1255)) - (PORT datad (572:572:572) (583:583:583)) + (PORT dataa (202:202:202) (246:246:246)) + (PORT datab (1199:1199:1199) (1296:1296:1296)) + (PORT datac (2728:2728:2728) (2883:2883:2883)) + (PORT datad (305:305:305) (322:322:322)) (IOPATH dataa combout (354:354:354) (367:367:367)) (IOPATH datab combout (331:331:331) (342:342:342)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -46494,15 +33375,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~45) + (INSTANCE D\[1\]\~31) (DELAY (ABSOLUTE - (PORT dataa (365:365:365) (410:410:410)) - (PORT datab (234:234:234) (278:278:278)) - (PORT datac (180:180:180) (217:217:217)) - (PORT datad (183:183:183) (212:212:212)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (916:916:916) (932:932:932)) + (PORT datab (917:917:917) (934:934:934)) + (PORT datac (345:345:345) (368:368:368)) + (PORT datad (180:180:180) (209:209:209)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (336:336:336) (342:342:342)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -46510,15 +33391,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~46) + (INSTANCE D\[1\]\~32) (DELAY (ABSOLUTE - (PORT dataa (415:415:415) (501:501:501)) - (PORT datab (234:234:234) (278:278:278)) - (PORT datac (1139:1139:1139) (1183:1183:1183)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (914:914:914) (925:925:925)) + (PORT datab (957:957:957) (1021:1021:1021)) + (PORT datac (1532:1532:1532) (1586:1586:1586)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -46526,28 +33407,60 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[2\]) + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[1\]) (DELAY (ABSOLUTE - (PORT dataa (978:978:978) (1031:1031:1031)) - (PORT datab (648:648:648) (673:673:673)) - (PORT datac (597:597:597) (612:612:612)) - (PORT datad (194:194:194) (219:219:219)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (1428:1428:1428) (1481:1481:1481)) + (PORT datab (219:219:219) (258:258:258)) + (PORT datac (1147:1147:1147) (1143:1143:1143)) + (PORT datad (375:375:375) (401:401:401)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_re\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1218:1218:1218) (1274:1274:1274)) + (PORT datab (229:229:229) (271:271:271)) + (PORT datac (962:962:962) (1042:1042:1042)) + (PORT datad (982:982:982) (1049:1049:1049)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_2) + (DELAY + (ABSOLUTE + (PORT dataa (1430:1430:1430) (1481:1481:1481)) + (PORT datab (1084:1084:1084) (1098:1098:1098)) + (PORT datac (1130:1130:1130) (1197:1197:1197)) + (PORT datad (763:763:763) (761:761:761)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|data_pins_\|dout\[2\]) + (INSTANCE z80_\|data_pins_\|dout\[1\]) (DELAY (ABSOLUTE - (PORT clk (1525:1525:1525) (1530:1530:1530)) + (PORT clk (1527:1527:1527) (1531:1531:1531)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1245:1245:1245) (1226:1226:1226)) + (PORT ena (819:819:819) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -46558,13 +33471,77 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[2\]\~12) + (INSTANCE z80_\|bus_control_\|db\[1\]\~11) (DELAY (ABSOLUTE - (PORT datab (920:920:920) (962:962:962)) - (PORT datac (944:944:944) (990:990:990)) - (PORT datad (218:218:218) (253:253:253)) - (IOPATH datab combout (306:306:306) (308:308:308)) + (PORT dataa (397:397:397) (444:444:444)) + (PORT datab (200:200:200) (239:239:239)) + (PORT datac (238:238:238) (315:315:315)) + (PORT datad (579:579:579) (606:606:606)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1566:1566:1566) (1548:1548:1548)) + (PORT ena (1684:1684:1684) (1669:1669:1669)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal2\~0) + (DELAY + (ABSOLUTE + (PORT datab (1698:1698:1698) (1757:1757:1757)) + (PORT datac (654:654:654) (719:719:719)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~15) + (DELAY + (ABSOLUTE + (PORT dataa (2188:2188:2188) (2324:2324:2324)) + (PORT datab (969:969:969) (1053:1053:1053)) + (PORT datac (1168:1168:1168) (1226:1226:1226)) + (PORT datad (896:896:896) (972:972:972)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_inc_cy\~39) + (DELAY + (ABSOLUTE + (PORT dataa (1007:1007:1007) (1110:1110:1110)) + (PORT datab (1244:1244:1244) (1325:1325:1325)) + (PORT datac (883:883:883) (943:943:943)) + (PORT datad (986:986:986) (1067:1067:1067)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -46572,15 +33549,93 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[2\]\~13) + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo\[1\]\~36) (DELAY (ABSOLUTE - (PORT dataa (439:439:439) (507:507:507)) - (PORT datab (236:236:236) (280:280:280)) - (PORT datac (225:225:225) (274:274:274)) - (PORT datad (173:173:173) (199:199:199)) + (PORT datab (610:610:610) (642:642:642)) + (PORT datac (1168:1168:1168) (1225:1225:1225)) + (PORT datad (623:623:623) (639:639:639)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~4) + (DELAY + (ABSOLUTE + (PORT dataa (883:883:883) (944:944:944)) + (PORT datab (920:920:920) (970:970:970)) + (PORT datac (1596:1596:1596) (1726:1726:1726)) + (PORT datad (1620:1620:1620) (1707:1707:1707)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~16) + (DELAY + (ABSOLUTE + (PORT dataa (354:354:354) (391:391:391)) + (PORT datab (2085:2085:2085) (2190:2190:2190)) + (PORT datac (1444:1444:1444) (1488:1488:1488)) + (PORT datad (303:303:303) (318:318:318)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~17) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (242:242:242)) + (PORT datab (214:214:214) (256:256:256)) + (PORT datac (1325:1325:1325) (1351:1351:1351)) + (PORT datad (175:175:175) (201:201:201)) (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1966:1966:1966) (2113:2113:2113)) + (PORT datab (2242:2242:2242) (2358:2358:2358)) + (PORT datac (848:848:848) (890:890:890)) + (PORT datad (647:647:647) (684:684:684)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_4u\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1133:1133:1133) (1155:1155:1155)) + (PORT datab (2068:2068:2068) (2184:2184:2184)) + (PORT datac (847:847:847) (869:869:869)) + (PORT datad (1033:1033:1033) (1085:1085:1085)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -46588,259 +33643,210 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[2\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT asdata (1864:1864:1864) (1894:1894:1894)) + (PORT ena (981:981:981) (980:980:980)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT asdata (1862:1862:1862) (1894:1894:1894)) + (PORT ena (811:811:811) (804:804:804)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~44) + (DELAY + (ABSOLUTE + (PORT dataa (242:242:242) (328:328:328)) + (PORT datab (256:256:256) (308:308:308)) + (PORT datad (231:231:231) (265:265:265)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1549:1549:1549)) + (PORT asdata (545:545:545) (579:579:579)) + (PORT ena (974:974:974) (969:969:969)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1549:1549:1549)) + (PORT asdata (545:545:545) (579:579:579)) + (PORT ena (975:975:975) (970:970:970)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~43) + (DELAY + (ABSOLUTE + (PORT dataa (405:405:405) (456:456:456)) + (PORT datab (436:436:436) (470:470:470)) + (PORT datad (217:217:217) (286:286:286)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1535:1535:1535)) + (PORT asdata (1249:1249:1249) (1268:1268:1268)) + (PORT ena (1274:1274:1274) (1265:1265:1265)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT asdata (1613:1613:1613) (1650:1650:1650)) + (PORT ena (1200:1200:1200) (1188:1188:1188)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (864:864:864) (935:935:935)) + (PORT datab (580:580:580) (607:607:607)) + (PORT datad (1013:1013:1013) (1025:1025:1025)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~47) + (DELAY + (ABSOLUTE + (PORT datab (955:955:955) (991:991:991)) + (PORT datad (637:637:637) (649:649:649)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1489:1489:1489) (1505:1505:1505)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_lo\|latch\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1535:1535:1535)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (790:790:790) (782:782:782)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_lo\|latch\[3\]) (DELAY (ABSOLUTE (PORT clk (1521:1521:1521) (1534:1534:1534)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1557:1557:1557)) - (PORT ena (1231:1231:1231) (1217:1217:1217)) + (PORT asdata (1241:1241:1241) (1250:1250:1250)) + (PORT ena (1438:1438:1438) (1476:1476:1476)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal3\~1) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~49) (DELAY (ABSOLUTE - (PORT datac (1460:1460:1460) (1533:1533:1533)) - (PORT datad (2264:2264:2264) (2327:2327:2327)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal43\~0) - (DELAY - (ABSOLUTE - (PORT dataa (944:944:944) (975:975:975)) - (PORT datab (940:940:940) (997:997:997)) - (PORT datac (1637:1637:1637) (1758:1758:1758)) - (PORT datad (1220:1220:1220) (1303:1303:1303)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|test1\~2) - (DELAY - (ABSOLUTE - (PORT dataa (198:198:198) (241:241:241)) - (PORT datab (218:218:218) (256:256:256)) - (PORT datac (198:198:198) (235:235:235)) - (PORT datad (195:195:195) (220:220:220)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|interrupts_\|test1\~3) - (DELAY - (ABSOLUTE - (PORT dataa (845:845:845) (859:859:859)) - (PORT datab (2054:2054:2054) (2187:2187:2187)) - (PORT datac (1260:1260:1260) (1358:1358:1358)) - (PORT datad (1087:1087:1087) (1084:1084:1084)) + (PORT dataa (697:697:697) (771:771:771)) + (PORT datab (376:376:376) (443:443:443)) + (PORT datad (370:370:370) (395:395:395)) (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|interrupts_\|in_nmi_ALTERA_SYNTHESIZED) - (DELAY - (ABSOLUTE - (PORT clk (1533:1533:1533) (1552:1552:1552)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1592:1592:1592) (1568:1568:1568)) - (PORT ena (1669:1669:1669) (1678:1678:1678)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|clk_delay_\|SYNTHESIZED_WIRE_4) - (DELAY - (ABSOLUTE - (PORT dataa (1217:1217:1217) (1308:1308:1308)) - (PORT datab (2052:2052:2052) (2184:2184:2184)) - (PORT datac (1270:1270:1270) (1384:1384:1384)) - (PORT datad (1880:1880:1880) (1934:1934:1934)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|clk_delay_\|SYNTHESIZED_WIRE_7) - (DELAY - (ABSOLUTE - (PORT clk (1528:1528:1528) (1547:1547:1547)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1587:1587:1587) (1563:1563:1563)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|clk_delay_\|hold_clk_iorq) - (DELAY - (ABSOLUTE - (PORT datab (252:252:252) (337:337:337)) - (PORT datad (226:226:226) (299:299:299)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_T1_ff) - (DELAY - (ABSOLUTE - (PORT clk (1540:1540:1540) (1556:1556:1556)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1596:1596:1596) (1571:1571:1571)) - (PORT ena (1939:1939:1939) (2030:2030:2030)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_13) - (DELAY - (ABSOLUTE - (PORT dataa (267:267:267) (353:353:353)) - (PORT datac (1094:1094:1094) (1135:1135:1135)) - (PORT datad (1105:1105:1105) (1151:1151:1151)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_T2_ff) - (DELAY - (ABSOLUTE - (PORT clk (1540:1540:1540) (1556:1556:1556)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1596:1596:1596) (1571:1571:1571)) - (PORT ena (1939:1939:1939) (2030:2030:2030)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|resets_\|x3) - (DELAY - (ABSOLUTE - (PORT dataa (2393:2393:2393) (2551:2551:2551)) - (PORT datac (239:239:239) (317:317:317)) - (PORT datad (1364:1364:1364) (1506:1506:1506)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_12) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1532:1532:1532)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1883:1883:1883) (1869:1869:1869)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_clkctrl") - (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_12\~clkctrl) - (DELAY - (ABSOLUTE - (PORT inclk[0] (1583:1583:1583) (1637:1637:1637)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_M1_ff) - (DELAY - (ABSOLUTE - (PORT clk (1540:1540:1540) (1556:1556:1556)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1596:1596:1596) (1571:1571:1571)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|DFFE_M2_ff\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1130:1130:1130) (1176:1176:1176)) - (PORT datab (283:283:283) (372:372:372)) - (PORT datad (1106:1106:1106) (1160:1160:1160)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -46848,1071 +33854,56 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_M2_ff) + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_lo\|latch\[3\]) (DELAY (ABSOLUTE - (PORT clk (1540:1540:1540) (1556:1556:1556)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1596:1596:1596) (1571:1571:1571)) + (PORT clk (1529:1529:1529) (1549:1549:1549)) + (PORT asdata (955:955:955) (966:966:966)) + (PORT ena (1240:1240:1240) (1231:1231:1231)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~3) - (DELAY - (ABSOLUTE - (PORT datac (1051:1051:1051) (1164:1164:1164)) - (PORT datad (2030:2030:2030) (2123:2123:2123)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1463:1463:1463) (1520:1520:1520)) - (PORT datab (853:853:853) (881:881:881)) - (PORT datac (791:791:791) (801:801:801)) - (PORT datad (672:672:672) (691:691:691)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~8) - (DELAY - (ABSOLUTE - (PORT dataa (996:996:996) (1076:1076:1076)) - (PORT datab (661:661:661) (685:685:685)) - (PORT datac (956:956:956) (1008:1008:1008)) - (PORT datad (2243:2243:2243) (2327:2327:2327)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~9) - (DELAY - (ABSOLUTE - (PORT dataa (873:873:873) (910:910:910)) - (PORT datab (847:847:847) (857:857:857)) - (PORT datac (945:945:945) (997:997:997)) - (PORT datad (402:402:402) (435:435:435)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~10) - (DELAY - (ABSOLUTE - (PORT dataa (675:675:675) (725:725:725)) - (PORT datab (334:334:334) (363:363:363)) - (PORT datac (1475:1475:1475) (1542:1542:1542)) - (PORT datad (2078:2078:2078) (2128:2128:2128)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~12) - (DELAY - (ABSOLUTE - (PORT dataa (402:402:402) (429:429:429)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (171:171:171) (203:203:203)) - (PORT datad (180:180:180) (209:209:209)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~15) - (DELAY - (ABSOLUTE - (PORT dataa (2002:2002:2002) (2100:2100:2100)) - (PORT datab (880:880:880) (891:891:891)) - (PORT datac (1448:1448:1448) (1504:1504:1504)) - (PORT datad (181:181:181) (209:209:209)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~6) - (DELAY - (ABSOLUTE - (PORT dataa (231:231:231) (277:277:277)) - (PORT datab (236:236:236) (281:281:281)) - (PORT datac (354:354:354) (382:382:382)) - (PORT datad (1061:1061:1061) (1062:1062:1062)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~7) - (DELAY - (ABSOLUTE - (PORT dataa (231:231:231) (279:279:279)) - (PORT datab (198:198:198) (236:236:236)) - (PORT datac (989:989:989) (1043:1043:1043)) - (PORT datad (780:780:780) (803:803:803)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~13) - (DELAY - (ABSOLUTE - (PORT datab (1104:1104:1104) (1138:1138:1138)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (316:316:316) (336:336:336)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~39) - (DELAY - (ABSOLUTE - (PORT datac (766:766:766) (771:771:771)) - (PORT datad (608:608:608) (623:623:623)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~5) - (DELAY - (ABSOLUTE - (PORT dataa (207:207:207) (252:252:252)) - (PORT datab (2053:2053:2053) (2084:2084:2084)) - (PORT datac (618:618:618) (675:675:675)) - (PORT datad (334:334:334) (341:341:341)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|nextM\~14) - (DELAY - (ABSOLUTE - (PORT dataa (834:834:834) (843:843:843)) - (PORT datab (877:877:877) (909:909:909)) - (PORT datac (1022:1022:1022) (1035:1035:1035)) - (PORT datad (538:538:538) (551:551:551)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_15) - (DELAY - (ABSOLUTE - (PORT datab (273:273:273) (358:358:358)) - (PORT datac (1093:1093:1093) (1130:1130:1130)) - (PORT datad (1107:1107:1107) (1155:1155:1155)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_T4_ff) - (DELAY - (ABSOLUTE - (PORT clk (1540:1540:1540) (1556:1556:1556)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1596:1596:1596) (1571:1571:1571)) - (PORT ena (1939:1939:1939) (2030:2030:2030)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_16) + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[3\]\~feeder) (DELAY (ABSOLUTE - (PORT dataa (1123:1123:1123) (1157:1157:1157)) - (PORT datac (246:246:246) (327:327:327)) - (PORT datad (1110:1110:1110) (1159:1159:1159)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_T5_ff) - (DELAY - (ABSOLUTE - (PORT clk (1540:1540:1540) (1556:1556:1556)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1596:1596:1596) (1571:1571:1571)) - (PORT ena (1939:1939:1939) (2030:2030:2030)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_17) - (DELAY - (ABSOLUTE - (PORT datab (265:265:265) (348:348:348)) - (PORT datac (1077:1077:1077) (1114:1114:1114)) - (PORT datad (1111:1111:1111) (1161:1161:1161)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|T6) - (DELAY - (ABSOLUTE - (PORT clk (1540:1540:1540) (1556:1556:1556)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1596:1596:1596) (1571:1571:1571)) - (PORT ena (1939:1939:1939) (2030:2030:2030)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~13) - (DELAY - (ABSOLUTE - (PORT dataa (611:611:611) (637:637:637)) - (PORT datab (872:872:872) (895:895:895)) - (PORT datac (589:589:589) (612:612:612)) - (PORT datad (914:914:914) (960:960:960)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|pla_decode_\|Equal77\~1) - (DELAY - (ABSOLUTE - (PORT dataa (1005:1005:1005) (1115:1115:1115)) - (PORT datab (1187:1187:1187) (1258:1258:1258)) - (PORT datac (655:655:655) (715:715:715)) - (PORT datad (1245:1245:1245) (1328:1328:1328)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~12) - (DELAY - (ABSOLUTE - (PORT dataa (673:673:673) (719:719:719)) - (PORT datab (1671:1671:1671) (1704:1704:1704)) - (PORT datac (864:864:864) (890:890:890)) - (PORT datad (857:857:857) (896:896:896)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~14) - (DELAY - (ABSOLUTE - (PORT datab (197:197:197) (237:237:237)) - (PORT datac (631:631:631) (681:681:681)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~41) - (DELAY - (ABSOLUTE - (PORT dataa (390:390:390) (442:442:442)) - (PORT datac (1069:1069:1069) (1104:1104:1104)) - (PORT datad (202:202:202) (230:230:230)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~42) - (DELAY - (ABSOLUTE - (PORT dataa (937:937:937) (992:992:992)) - (PORT datab (1106:1106:1106) (1172:1172:1172)) - (PORT datac (411:411:411) (452:452:452)) - (PORT datad (2503:2503:2503) (2629:2629:2629)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~43) - (DELAY - (ABSOLUTE - (PORT dataa (2006:2006:2006) (2147:2147:2147)) - (PORT datab (771:771:771) (831:831:831)) - (PORT datac (960:960:960) (989:989:989)) - (PORT datad (172:172:172) (197:197:197)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~44) - (DELAY - (ABSOLUTE - (PORT dataa (898:898:898) (941:941:941)) - (PORT datab (355:355:355) (391:391:391)) - (PORT datac (202:202:202) (239:239:239)) - (PORT datad (759:759:759) (760:760:760)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~50) - (DELAY - (ABSOLUTE - (PORT dataa (377:377:377) (403:403:403)) - (PORT datab (1048:1048:1048) (1080:1080:1080)) - (PORT datac (170:170:170) (204:204:204)) - (PORT datad (1303:1303:1303) (1325:1325:1325)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~51) - (DELAY - (ABSOLUTE - (PORT dataa (1126:1126:1126) (1188:1188:1188)) - (PORT datab (198:198:198) (238:238:238)) - (PORT datac (200:200:200) (237:237:237)) - (PORT datad (181:181:181) (212:212:212)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~6) - (DELAY - (ABSOLUTE - (PORT dataa (851:851:851) (871:871:871)) - (PORT datab (1589:1589:1589) (1720:1720:1720)) - (PORT datac (636:636:636) (653:653:653)) - (PORT datad (1694:1694:1694) (1790:1790:1790)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~7) - (DELAY - (ABSOLUTE - (PORT datab (867:867:867) (913:913:913)) - (PORT datac (893:893:893) (946:946:946)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~8) - (DELAY - (ABSOLUTE - (PORT dataa (1439:1439:1439) (1482:1482:1482)) - (PORT datab (885:885:885) (895:895:895)) - (PORT datac (878:878:878) (926:926:926)) - (PORT datad (632:632:632) (642:642:642)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~9) - (DELAY - (ABSOLUTE - (PORT dataa (1493:1493:1493) (1600:1600:1600)) - (PORT datab (1951:1951:1951) (2023:2023:2023)) - (PORT datac (1350:1350:1350) (1424:1424:1424)) - (PORT datad (1111:1111:1111) (1134:1134:1134)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~10) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (265:265:265)) - (PORT datab (1125:1125:1125) (1164:1164:1164)) - (PORT datac (514:514:514) (525:525:525)) - (PORT datad (639:639:639) (676:676:676)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~11) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (1215:1215:1215) (1255:1255:1255)) - (PORT datac (1013:1013:1013) (1058:1058:1058)) - (PORT datad (342:342:342) (364:364:364)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~17) - (DELAY - (ABSOLUTE - (PORT dataa (621:621:621) (655:655:655)) - (PORT datab (1046:1046:1046) (1078:1078:1078)) - (PORT datac (2017:2017:2017) (2052:2052:2052)) - (PORT datad (621:621:621) (635:635:635)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~31) - (DELAY - (ABSOLUTE - (PORT dataa (629:629:629) (662:662:662)) - (PORT datab (914:914:914) (975:975:975)) - (PORT datac (1817:1817:1817) (1894:1894:1894)) - (PORT datad (898:898:898) (912:912:912)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~28) - (DELAY - (ABSOLUTE - (PORT dataa (358:358:358) (403:403:403)) - (PORT datab (1223:1223:1223) (1259:1259:1259)) - (PORT datac (1402:1402:1402) (1465:1465:1465)) - (PORT datad (856:856:856) (854:854:854)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~30) - (DELAY - (ABSOLUTE - (PORT dataa (863:863:863) (886:886:886)) - (PORT datab (916:916:916) (944:944:944)) - (PORT datac (906:906:906) (930:930:930)) - (PORT datad (843:843:843) (882:882:882)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~32) - (DELAY - (ABSOLUTE - (PORT dataa (921:921:921) (960:960:960)) - (PORT datab (360:360:360) (395:395:395)) - (PORT datac (859:859:859) (902:902:902)) - (PORT datad (1107:1107:1107) (1120:1120:1120)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~33) - (DELAY - (ABSOLUTE - (PORT dataa (593:593:593) (602:602:602)) - (PORT datab (196:196:196) (235:235:235)) - (PORT datac (896:896:896) (935:935:935)) - (PORT datad (173:173:173) (197:197:197)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~25) - (DELAY - (ABSOLUTE - (PORT dataa (1130:1130:1130) (1215:1215:1215)) - (PORT datac (627:627:627) (650:650:650)) - (PORT datad (1592:1592:1592) (1700:1700:1700)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~26) - (DELAY - (ABSOLUTE - (PORT dataa (862:862:862) (906:906:906)) - (PORT datab (1566:1566:1566) (1611:1611:1611)) - (PORT datac (868:868:868) (891:891:891)) - (PORT datad (1122:1122:1122) (1151:1151:1151)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~24) - (DELAY - (ABSOLUTE - (PORT dataa (673:673:673) (723:723:723)) - (PORT datab (660:660:660) (684:684:684)) - (PORT datac (2018:2018:2018) (1985:1985:1985)) - (PORT datad (954:954:954) (1028:1028:1028)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~27) - (DELAY - (ABSOLUTE - (PORT dataa (200:200:200) (244:244:244)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (643:643:643) (693:693:693)) - (PORT datad (661:661:661) (727:727:727)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~22) - (DELAY - (ABSOLUTE - (PORT dataa (932:932:932) (949:949:949)) - (PORT datab (904:904:904) (924:924:924)) - (PORT datac (888:888:888) (932:932:932)) - (PORT datad (623:623:623) (628:628:628)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~21) - (DELAY - (ABSOLUTE - (PORT dataa (1744:1744:1744) (1869:1869:1869)) - (PORT datab (1550:1550:1550) (1688:1688:1688)) - (PORT datac (1209:1209:1209) (1285:1285:1285)) - (PORT datad (1505:1505:1505) (1539:1539:1539)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (310:310:310)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~53) - (DELAY - (ABSOLUTE - (PORT dataa (965:965:965) (1045:1045:1045)) - (PORT datab (936:936:936) (1009:1009:1009)) - (PORT datac (649:649:649) (669:669:669)) - (PORT datad (1286:1286:1286) (1339:1339:1339)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~23) - (DELAY - (ABSOLUTE - (PORT dataa (198:198:198) (240:240:240)) - (PORT datab (363:363:363) (396:396:396)) - (PORT datac (1524:1524:1524) (1571:1571:1571)) - (PORT datad (171:171:171) (196:196:196)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~18) - (DELAY - (ABSOLUTE - (PORT dataa (372:372:372) (412:412:412)) - (PORT datab (990:990:990) (1020:1020:1020)) - (PORT datac (1523:1523:1523) (1602:1602:1602)) - (PORT datad (193:193:193) (219:219:219)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~19) - (DELAY - (ABSOLUTE - (PORT dataa (627:627:627) (644:644:644)) - (PORT datab (693:693:693) (758:758:758)) - (PORT datac (646:646:646) (704:704:704)) - (PORT datad (1320:1320:1320) (1419:1419:1419)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~20) - (DELAY - (ABSOLUTE - (PORT dataa (625:625:625) (675:675:675)) - (PORT datab (1180:1180:1180) (1218:1218:1218)) - (PORT datac (868:868:868) (922:922:922)) - (PORT datad (604:604:604) (625:625:625)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~34) - (DELAY - (ABSOLUTE - (PORT dataa (612:612:612) (649:649:649)) - (PORT datab (197:197:197) (236:236:236)) - (PORT datac (309:309:309) (334:334:334)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|setM1\~52) - (DELAY - (ABSOLUTE - (PORT dataa (199:199:199) (242:242:242)) - (PORT datab (197:197:197) (235:235:235)) - (PORT datac (312:312:312) (330:330:330)) - (PORT datad (970:970:970) (1032:1032:1032)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_14) - (DELAY - (ABSOLUTE - (PORT dataa (1112:1112:1112) (1167:1167:1167)) - (PORT datac (245:245:245) (326:326:326)) - (PORT datad (1111:1111:1111) (1159:1159:1159)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|sequencer_\|DFFE_T3_ff) - (DELAY - (ABSOLUTE - (PORT clk (1540:1540:1540) (1556:1556:1556)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1596:1596:1596) (1571:1571:1571)) - (PORT ena (1939:1939:1939) (2030:2030:2030)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_1M1T3_3) - (DELAY - (ABSOLUTE - (PORT datac (984:984:984) (1073:1073:1073)) - (PORT datad (1348:1348:1348) (1490:1490:1490)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|in_halt\~0) - (DELAY - (ABSOLUTE - (PORT dataa (361:361:361) (497:497:497)) - (PORT datac (1177:1177:1177) (1261:1261:1261)) - (PORT datad (272:272:272) (353:353:353)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|decode_state_\|in_halt\~1) - (DELAY - (ABSOLUTE - (PORT dataa (641:641:641) (697:697:697)) - (PORT datab (1593:1593:1593) (1628:1628:1628)) - (PORT datad (638:638:638) (679:679:679)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|decode_state_\|in_halt) - (DELAY - (ABSOLUTE - (PORT clk (1518:1518:1518) (1532:1532:1532)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1575:1575:1575) (1555:1555:1555)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~2) - (DELAY - (ABSOLUTE - (PORT dataa (991:991:991) (1049:1049:1049)) - (PORT datab (1153:1153:1153) (1214:1214:1214)) - (PORT datac (671:671:671) (718:718:718)) - (PORT datad (624:624:624) (674:674:674)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~5) - (DELAY - (ABSOLUTE - (PORT dataa (1120:1120:1120) (1227:1227:1227)) - (PORT datab (994:994:994) (1058:1058:1058)) - (PORT datac (1165:1165:1165) (1211:1211:1211)) - (PORT datad (879:879:879) (933:933:933)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~6) - (DELAY - (ABSOLUTE - (PORT dataa (401:401:401) (432:432:432)) - (PORT datab (689:689:689) (742:742:742)) - (PORT datac (882:882:882) (943:943:943)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~4) - (DELAY - (ABSOLUTE - (PORT datac (1080:1080:1080) (1100:1100:1100)) - (PORT datad (647:647:647) (663:663:663)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_bus_db_oe) - (DELAY - (ABSOLUTE - (PORT dataa (220:220:220) (263:263:263)) - (PORT datab (954:954:954) (979:979:979)) - (PORT datac (638:638:638) (653:653:653)) - (PORT datad (173:173:173) (197:197:197)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|bus_control_\|db\[0\]\~6) - (DELAY - (ABSOLUTE - (PORT dataa (254:254:254) (309:309:309)) - (PORT datac (944:944:944) (985:985:985)) (PORT datad (335:335:335) (356:356:356)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]\~93) + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_lo\|latch\[3\]) (DELAY (ABSOLUTE - (PORT dataa (227:227:227) (285:285:285)) - (PORT datab (780:780:780) (881:881:881)) - (PORT datac (1368:1368:1368) (1458:1458:1458)) - (PORT datad (562:562:562) (568:568:568)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT clk (1529:1529:1529) (1549:1549:1549)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1207:1207:1207) (1180:1180:1180)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]\~94) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~45) (DELAY (ABSOLUTE - (PORT dataa (628:628:628) (659:659:659)) - (PORT datab (733:733:733) (831:831:831)) - (PORT datad (718:718:718) (812:812:812)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT dataa (695:695:695) (736:736:736)) + (PORT datab (706:706:706) (728:728:728)) + (PORT datad (217:217:217) (286:286:286)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -47920,273 +33911,60 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_lo\|latch\[3\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) + (PORT clk (1522:1522:1522) (1535:1535:1535)) + (PORT asdata (1249:1249:1249) (1271:1271:1271)) + (PORT ena (1243:1243:1243) (1246:1246:1246)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]\~96) - (DELAY - (ABSOLUTE - (PORT dataa (741:741:741) (849:849:849)) - (PORT datab (1176:1176:1176) (1266:1266:1266)) - (PORT datac (727:727:727) (821:821:821)) - (PORT datad (735:735:735) (837:837:837)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]\~98) - (DELAY - (ABSOLUTE - (PORT dataa (204:204:204) (249:249:249)) - (PORT datab (208:208:208) (251:251:251)) - (PORT datad (184:184:184) (213:213:213)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]) + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_lo\|latch\[3\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1573:1573:1573)) + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT asdata (1613:1613:1613) (1651:1651:1651)) + (PORT ena (1220:1220:1220) (1212:1212:1212)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~65) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~48) (DELAY (ABSOLUTE - (PORT dataa (1136:1136:1136) (1168:1168:1168)) - (PORT datab (1145:1145:1145) (1215:1215:1215)) - (PORT datac (215:215:215) (292:292:292)) - (PORT datad (361:361:361) (417:417:417)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]\~99) - (DELAY - (ABSOLUTE - (PORT dataa (783:783:783) (873:873:873)) - (PORT datab (729:729:729) (817:817:817)) - (PORT datac (885:885:885) (954:954:954)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]\~100) - (DELAY - (ABSOLUTE - (PORT dataa (342:342:342) (378:378:378)) - (PORT datab (200:200:200) (239:239:239)) - (PORT datad (735:735:735) (822:822:822)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~101) - (DELAY - (ABSOLUTE - (PORT dataa (745:745:745) (850:850:850)) - (PORT datab (987:987:987) (1082:1082:1082)) - (PORT datad (938:938:938) (1011:1011:1011)) + (PORT dataa (635:635:635) (695:695:695)) + (PORT datab (727:727:727) (792:792:792)) + (PORT datad (659:659:659) (725:725:725)) (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~102) - (DELAY - (ABSOLUTE - (PORT dataa (743:743:743) (852:852:852)) - (PORT datab (723:723:723) (826:826:826)) - (PORT datac (1146:1146:1146) (1231:1231:1231)) - (PORT datad (910:910:910) (977:977:977)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~133) - (DELAY - (ABSOLUTE - (PORT dataa (676:676:676) (704:704:704)) - (PORT datab (200:200:200) (240:240:240)) - (PORT datac (728:728:728) (824:824:824)) - (PORT datad (731:731:731) (831:831:831)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (331:331:331) (342:342:342)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~103) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datad (322:322:322) (345:345:345)) - (IOPATH dataa combout (325:325:325) (328:328:328)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1573:1573:1573)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~66) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~50) (DELAY (ABSOLUTE - (PORT dataa (601:601:601) (622:622:622)) - (PORT datab (422:422:422) (485:485:485)) - (PORT datac (556:556:556) (585:585:585)) - (PORT datad (616:616:616) (671:671:671)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]\~104) - (DELAY - (ABSOLUTE - (PORT dataa (714:714:714) (816:816:816)) - (PORT datab (729:729:729) (827:827:827)) - (PORT datac (720:720:720) (822:822:822)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]\~105) - (DELAY - (ABSOLUTE - (PORT dataa (202:202:202) (245:245:245)) - (PORT datab (367:367:367) (395:395:395)) - (PORT datad (718:718:718) (814:814:814)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~106) - (DELAY - (ABSOLUTE - (PORT dataa (1414:1414:1414) (1548:1548:1548)) - (PORT datab (216:216:216) (261:261:261)) - (PORT datac (959:959:959) (1039:1039:1039)) - (PORT datad (204:204:204) (234:234:234)) + (PORT dataa (608:608:608) (647:647:647)) + (PORT datab (638:638:638) (656:656:656)) + (PORT datac (171:171:171) (205:205:205)) + (PORT datad (610:610:610) (628:628:628)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -48196,15 +33974,199 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|Selector5\~1) + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~51) (DELAY (ABSOLUTE - (PORT dataa (732:732:732) (817:817:817)) - (PORT datab (665:665:665) (745:745:745)) - (PORT datac (658:658:658) (727:727:727)) - (PORT datad (433:433:433) (505:505:505)) + (PORT dataa (595:595:595) (627:627:627)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datad (343:343:343) (367:367:367)) (IOPATH dataa combout (300:300:300) (308:308:308)) (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp0\[3\]\~52) + (DELAY + (ABSOLUTE + (PORT dataa (863:863:863) (906:906:906)) + (PORT datab (343:343:343) (371:371:371)) + (PORT datac (599:599:599) (609:609:609)) + (PORT datad (202:202:202) (231:231:231)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_35) + (DELAY + (ABSOLUTE + (PORT dataa (864:864:864) (928:928:928)) + (PORT datab (351:351:351) (388:388:388)) + (PORT datac (1136:1136:1136) (1149:1149:1149)) + (PORT datad (627:627:627) (645:645:645)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1193:1193:1193) (1268:1268:1268)) + (PORT datab (1695:1695:1695) (1875:1875:1875)) + (PORT datac (1375:1375:1375) (1453:1453:1453)) + (PORT datad (819:819:819) (821:821:821)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~16) + (DELAY + (ABSOLUTE + (PORT datab (198:198:198) (236:236:236)) + (PORT datac (180:180:180) (217:217:217)) + (PORT datad (196:196:196) (222:222:222)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~17) + (DELAY + (ABSOLUTE + (PORT dataa (381:381:381) (405:405:405)) + (PORT datab (207:207:207) (249:249:249)) + (PORT datac (192:192:192) (226:226:226)) + (PORT datad (1021:1021:1021) (1018:1018:1018)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_flags_xy_we\~18) + (DELAY + (ABSOLUTE + (PORT dataa (1190:1190:1190) (1212:1212:1212)) + (PORT datab (199:199:199) (239:239:239)) + (PORT datac (637:637:637) (676:676:676)) + (PORT datad (591:591:591) (596:596:596)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|flags_xf) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1440:1440:1440) (1432:1432:1432)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[3\]\~33) + (DELAY + (ABSOLUTE + (PORT datab (633:633:633) (647:647:647)) + (PORT datac (1099:1099:1099) (1100:1100:1100)) + (PORT datad (218:218:218) (287:287:287)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sw1_\|db_down\[3\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (868:868:868) (907:907:907)) + (PORT datab (1400:1400:1400) (1399:1399:1399)) + (PORT datac (637:637:637) (697:697:697)) + (PORT datad (635:635:635) (684:684:684)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[3\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (1273:1273:1273) (1305:1305:1305)) + (PORT datab (422:422:422) (447:447:447)) + (PORT datac (343:343:343) (364:364:364)) + (PORT datad (176:176:176) (201:201:201)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[3\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (203:203:203) (247:247:247)) + (PORT datab (390:390:390) (425:425:425)) + (PORT datac (843:843:843) (851:851:851)) + (PORT datad (219:219:219) (253:253:253)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]\~75) + (DELAY + (ABSOLUTE + (PORT dataa (1058:1058:1058) (1138:1138:1138)) + (PORT datac (1183:1183:1183) (1257:1257:1257)) + (PORT datad (647:647:647) (705:705:705)) + (IOPATH dataa combout (325:325:325) (320:320:320)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -48215,56 +34177,88 @@ (INSTANCE ula_\|zx_keyboard_\|Selector5\~0) (DELAY (ABSOLUTE - (PORT dataa (230:230:230) (279:279:279)) - (PORT datab (412:412:412) (492:492:492)) - (PORT datac (628:628:628) (701:701:701)) - (PORT datad (406:406:406) (471:471:471)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (669:669:669) (737:737:737)) + (PORT datab (828:828:828) (850:850:850)) + (PORT datac (461:461:461) (552:552:552)) + (PORT datad (437:437:437) (520:520:520)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~134) + (INSTANCE ula_\|zx_keyboard_\|Selector5\~1) (DELAY (ABSOLUTE - (PORT dataa (377:377:377) (399:399:399)) - (PORT datab (380:380:380) (403:403:403)) - (PORT datad (833:833:833) (879:879:879)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (PORT dataa (1160:1160:1160) (1266:1266:1266)) + (PORT datab (314:314:314) (415:415:415)) + (PORT datac (956:956:956) (1048:1048:1048)) + (PORT datad (944:944:944) (1022:1022:1022)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~132) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (492:492:492) (589:589:589)) + (PORT datad (796:796:796) (841:841:841)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (304:304:304) (308:308:308)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~106) + (DELAY + (ABSOLUTE + (PORT dataa (466:466:466) (564:564:564)) + (PORT datab (1156:1156:1156) (1181:1181:1181)) + (PORT datac (461:461:461) (553:553:553)) + (PORT datad (197:197:197) (223:223:223)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~107) (DELAY (ABSOLUTE - (PORT dataa (740:740:740) (824:824:824)) - (PORT datab (602:602:602) (630:630:630)) - (PORT datac (616:616:616) (675:675:675)) - (PORT datad (531:531:531) (537:537:537)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (508:508:508) (583:583:583)) + (PORT datab (200:200:200) (240:240:240)) + (PORT datac (260:260:260) (347:347:347)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~135) + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~133) (DELAY (ABSOLUTE - (PORT dataa (737:737:737) (827:827:827)) - (PORT datab (274:274:274) (360:360:360)) - (PORT datad (1094:1094:1094) (1148:1148:1148)) + (PORT dataa (516:516:516) (591:591:591)) + (PORT datab (273:273:273) (359:359:359)) + (PORT datad (910:910:910) (996:996:996)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -48277,11 +34271,11 @@ (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~108) (DELAY (ABSOLUTE - (PORT dataa (202:202:202) (245:245:245)) - (PORT datab (365:365:365) (407:407:407)) - (PORT datad (175:175:175) (200:200:200)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datad (197:197:197) (222:222:222)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -48292,9 +34286,9 @@ (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1544:1544:1544)) + (PORT clk (1521:1521:1521) (1535:1535:1535)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) + (PORT clrn (1555:1555:1555) (1548:1548:1548)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -48305,13 +34299,285 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~67) + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]\~104) (DELAY (ABSOLUTE - (PORT dataa (243:243:243) (330:330:330)) - (PORT datab (1198:1198:1198) (1264:1264:1264)) - (PORT datac (618:618:618) (676:676:676)) - (PORT datad (777:777:777) (790:790:790)) + (PORT dataa (987:987:987) (1069:1069:1069)) + (PORT datac (965:965:965) (1038:1038:1038)) + (PORT datad (993:993:993) (1070:1070:1070)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]\~105) + (DELAY + (ABSOLUTE + (PORT dataa (923:923:923) (940:940:940)) + (PORT datab (727:727:727) (802:802:802)) + (PORT datad (176:176:176) (201:201:201)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1558:1558:1558) (1549:1549:1549)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~55) + (DELAY + (ABSOLUTE + (PORT dataa (1111:1111:1111) (1125:1125:1125)) + (PORT datab (660:660:660) (727:727:727)) + (PORT datac (215:215:215) (292:292:292)) + (PORT datad (1016:1016:1016) (1042:1042:1042)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (842:842:842) (929:929:929)) + (PORT datab (1013:1013:1013) (1093:1093:1093)) + (PORT datac (636:636:636) (713:713:713)) + (PORT datad (911:911:911) (1029:1029:1029)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~62) + (DELAY + (ABSOLUTE + (PORT datac (709:709:709) (781:781:781)) + (PORT datad (1541:1541:1541) (1630:1630:1630)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]\~102) + (DELAY + (ABSOLUTE + (PORT dataa (937:937:937) (1030:1030:1030)) + (PORT datab (221:221:221) (260:260:260)) + (PORT datac (952:952:952) (1027:1027:1027)) + (PORT datad (214:214:214) (247:247:247)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]\~103) + (DELAY + (ABSOLUTE + (PORT datab (725:725:725) (803:803:803)) + (PORT datad (841:841:841) (842:842:842)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1558:1558:1558) (1549:1549:1549)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~96) + (DELAY + (ABSOLUTE + (PORT dataa (651:651:651) (684:684:684)) + (PORT datab (1519:1519:1519) (1598:1598:1598)) + (PORT datac (966:966:966) (1036:1036:1036)) + (PORT datad (1155:1155:1155) (1230:1230:1230)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~94) + (DELAY + (ABSOLUTE + (PORT dataa (1009:1009:1009) (1062:1062:1062)) + (PORT datab (950:950:950) (1023:1023:1023)) + (PORT datad (1154:1154:1154) (1231:1231:1231)) + (IOPATH dataa combout (301:301:301) (307:307:307)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]\~95) + (DELAY + (ABSOLUTE + (PORT dataa (1580:1580:1580) (1672:1672:1672)) + (PORT datab (683:683:683) (775:775:775)) + (PORT datac (716:716:716) (784:784:784)) + (PORT datad (974:974:974) (1053:1053:1053)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]\~97) + (DELAY + (ABSOLUTE + (PORT dataa (406:406:406) (433:433:433)) + (PORT datab (397:397:397) (421:421:421)) + (PORT datad (345:345:345) (370:370:370)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1558:1558:1558) (1550:1550:1550)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~45) + (DELAY + (ABSOLUTE + (PORT dataa (1196:1196:1196) (1271:1271:1271)) + (PORT datac (964:964:964) (1033:1033:1033)) + (PORT datad (2207:2207:2207) (2293:2293:2293)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]\~92) + (DELAY + (ABSOLUTE + (PORT dataa (232:232:232) (280:280:280)) + (PORT datab (634:634:634) (648:648:648)) + (PORT datac (690:690:690) (755:755:755)) + (PORT datad (991:991:991) (1066:1066:1066)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]\~93) + (DELAY + (ABSOLUTE + (PORT dataa (990:990:990) (1073:1073:1073)) + (PORT datab (726:726:726) (803:803:803)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1558:1558:1558) (1549:1549:1549)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~53) + (DELAY + (ABSOLUTE + (PORT dataa (682:682:682) (741:741:741)) + (PORT datab (631:631:631) (650:650:650)) + (PORT datac (215:215:215) (290:290:290)) + (PORT datad (1076:1076:1076) (1076:1076:1076)) (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -48321,13 +34587,27 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]\~112) + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~99) (DELAY (ABSOLUTE - (PORT dataa (853:853:853) (877:877:877)) - (PORT datab (222:222:222) (269:269:269)) - (PORT datac (638:638:638) (702:702:702)) - (PORT datad (324:324:324) (344:344:344)) + (PORT datab (944:944:944) (1067:1067:1067)) + (PORT datac (952:952:952) (1022:1022:1022)) + (PORT datad (969:969:969) (1052:1052:1052)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~100) + (DELAY + (ABSOLUTE + (PORT dataa (203:203:203) (248:248:248)) + (PORT datab (240:240:240) (285:285:285)) + (PORT datac (956:956:956) (1028:1028:1028)) + (PORT datad (659:659:659) (739:739:739)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -48337,15 +34617,88 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]\~113) + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~98) (DELAY (ABSOLUTE - (PORT dataa (734:734:734) (817:817:817)) - (PORT datab (201:201:201) (241:241:241)) - (PORT datac (569:569:569) (605:605:605)) - (PORT datad (464:464:464) (535:535:535)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (342:342:342) (318:318:318)) + (PORT dataa (1005:1005:1005) (1057:1057:1057)) + (PORT datac (967:967:967) (1042:1042:1042)) + (PORT datad (915:915:915) (983:983:983)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]\~101) + (DELAY + (ABSOLUTE + (PORT dataa (652:652:652) (685:685:685)) + (PORT datab (635:635:635) (652:652:652)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1558:1558:1558) (1549:1549:1549)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\~3) + (DELAY + (ABSOLUTE + (PORT dataa (2700:2700:2700) (2865:2865:2865)) + (PORT datab (1435:1435:1435) (1516:1516:1516)) + (PORT datad (641:641:641) (695:695:695)) + (IOPATH dataa combout (301:301:301) (307:307:307)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~54) + (DELAY + (ABSOLUTE + (PORT dataa (244:244:244) (331:331:331)) + (PORT datab (200:200:200) (239:239:239)) + (PORT datac (1051:1051:1051) (1057:1057:1057)) + (PORT datad (320:320:320) (341:341:341)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~109) + (DELAY + (ABSOLUTE + (PORT datab (952:952:952) (1012:1012:1012)) + (PORT datac (986:986:986) (1057:1057:1057)) + (PORT datad (1124:1124:1124) (1177:1177:1177)) + (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -48353,12 +34706,56 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]\~114) + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~60) (DELAY (ABSOLUTE - (PORT datab (562:562:562) (582:582:582)) - (PORT datad (867:867:867) (872:872:872)) + (PORT datab (1016:1016:1016) (1109:1109:1109)) + (PORT datac (985:985:985) (1055:1055:1055)) (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]\~110) + (DELAY + (ABSOLUTE + (PORT dataa (210:210:210) (259:259:259)) + (PORT datab (1231:1231:1231) (1316:1316:1316)) + (PORT datac (838:838:838) (853:853:853)) + (PORT datad (204:204:204) (233:233:233)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]\~111) + (DELAY + (ABSOLUTE + (PORT dataa (874:874:874) (905:905:905)) + (PORT datab (1046:1046:1046) (1134:1134:1134)) + (PORT datac (317:317:317) (335:335:335)) + (PORT datad (738:738:738) (802:802:802)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]\~112) + (DELAY + (ABSOLUTE + (PORT dataa (224:224:224) (268:268:268)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (325:325:325) (328:328:328)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -48369,9 +34766,9 @@ (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[3\]) (DELAY (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT clk (1518:1518:1518) (1531:1531:1531)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1568:1568:1568) (1563:1563:1563)) + (PORT clrn (1557:1557:1557) (1549:1549:1549)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -48382,46 +34779,60 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~109) + (INSTANCE ula_\|zx_keyboard_\|Selector13\~0) (DELAY (ABSOLUTE - (PORT dataa (740:740:740) (820:820:820)) - (PORT datab (654:654:654) (726:726:726)) - (PORT datac (638:638:638) (703:703:703)) - (PORT datad (802:802:802) (842:842:842)) + (PORT dataa (1514:1514:1514) (1594:1594:1594)) + (PORT datab (919:919:919) (975:975:975)) + (PORT datad (914:914:914) (982:982:982)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~113) + (DELAY + (ABSOLUTE + (PORT dataa (1018:1018:1018) (1098:1098:1098)) + (PORT datab (1231:1231:1231) (1315:1315:1315)) + (PORT datac (986:986:986) (1079:1079:1079)) + (PORT datad (735:735:735) (800:800:800)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~114) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (246:246:246)) + (PORT datab (773:773:773) (840:840:840)) + (PORT datac (346:346:346) (369:369:369)) + (PORT datad (954:954:954) (1014:1014:1014)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~135) + (DELAY + (ABSOLUTE + (PORT dataa (871:871:871) (904:904:904)) + (PORT datab (1043:1043:1043) (1133:1133:1133)) + (PORT datad (174:174:174) (200:200:200)) (IOPATH dataa combout (301:301:301) (299:299:299)) (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~110) - (DELAY - (ABSOLUTE - (PORT dataa (736:736:736) (822:822:822)) - (PORT datab (225:225:225) (273:273:273)) - (PORT datac (173:173:173) (207:207:207)) - (PORT datad (638:638:638) (709:709:709)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~137) - (DELAY - (ABSOLUTE - (PORT dataa (734:734:734) (821:821:821)) - (PORT datab (334:334:334) (362:362:362)) - (PORT datad (340:340:340) (370:370:370)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -48429,14 +34840,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~138) + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]\~136) (DELAY (ABSOLUTE - (PORT dataa (1042:1042:1042) (1147:1147:1147)) - (PORT datab (671:671:671) (712:712:712)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (351:351:351) (382:382:382)) + (PORT datab (199:199:199) (237:237:237)) + (PORT datad (936:936:936) (977:977:977)) + (IOPATH dataa combout (301:301:301) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -48447,9 +34858,9 @@ (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[3\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1544:1544:1544)) + (PORT clk (1518:1518:1518) (1531:1531:1531)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) + (PORT clrn (1557:1557:1557) (1549:1549:1549)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -48460,13 +34871,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|zx_keyboard_\|key_row\~2) + (INSTANCE D\[3\]\~56) (DELAY (ABSOLUTE - (PORT datab (1402:1402:1402) (1455:1455:1455)) - (PORT datac (1615:1615:1615) (1701:1701:1701)) - (PORT datad (1189:1189:1189) (1294:1294:1294)) - (IOPATH datab combout (306:306:306) (308:308:308)) + (PORT dataa (1612:1612:1612) (1712:1712:1712)) + (PORT datab (242:242:242) (324:324:324)) + (PORT datac (216:216:216) (293:293:293)) + (PORT datad (622:622:622) (639:639:639)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -48474,43 +34887,27 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~68) + (INSTANCE D\[3\]\~57) (DELAY (ABSOLUTE - (PORT dataa (230:230:230) (277:277:277)) - (PORT datab (1199:1199:1199) (1232:1232:1232)) - (PORT datac (1173:1173:1173) (1255:1255:1255)) - (PORT datad (174:174:174) (198:198:198)) - (IOPATH dataa combout (300:300:300) (307:307:307)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~69) - (DELAY - (ABSOLUTE - (PORT dataa (1123:1123:1123) (1183:1183:1183)) - (PORT datab (3290:3290:3290) (3477:3477:3477)) - (PORT datac (1148:1148:1148) (1200:1200:1200)) - (PORT datad (561:561:561) (572:572:572)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (198:198:198) (236:236:236)) + (PORT datac (839:839:839) (887:887:887)) + (PORT datad (581:581:581) (597:597:597)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.datain_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1048:1048:1048) (1087:1087:1087)) - (PORT clk (1847:1847:1847) (1875:1875:1875)) + (PORT d[0] (1024:1024:1024) (1024:1024:1024)) + (PORT clk (1860:1860:1860) (1887:1887:1887)) ) ) (TIMINGCHECK @@ -48519,23 +34916,23 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.addr_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (3996:3996:3996) (4212:4212:4212)) - (PORT d[1] (1700:1700:1700) (1852:1852:1852)) - (PORT d[2] (1685:1685:1685) (1760:1760:1760)) - (PORT d[3] (1880:1880:1880) (1986:1986:1986)) - (PORT d[4] (2151:2151:2151) (2275:2275:2275)) - (PORT d[5] (1351:1351:1351) (1462:1462:1462)) - (PORT d[6] (1496:1496:1496) (1550:1550:1550)) - (PORT d[7] (3357:3357:3357) (3515:3515:3515)) - (PORT d[8] (3629:3629:3629) (3880:3880:3880)) - (PORT d[9] (1469:1469:1469) (1530:1530:1530)) - (PORT d[10] (3184:3184:3184) (3384:3384:3384)) - (PORT d[11] (2096:2096:2096) (2225:2225:2225)) - (PORT d[12] (1735:1735:1735) (1780:1780:1780)) - (PORT clk (1844:1844:1844) (1871:1871:1871)) + (PORT d[0] (3190:3190:3190) (3440:3440:3440)) + (PORT d[1] (1579:1579:1579) (1682:1682:1682)) + (PORT d[2] (985:985:985) (1036:1036:1036)) + (PORT d[3] (3294:3294:3294) (3529:3529:3529)) + (PORT d[4] (1012:1012:1012) (1054:1054:1054)) + (PORT d[5] (1476:1476:1476) (1548:1548:1548)) + (PORT d[6] (999:999:999) (1021:1021:1021)) + (PORT d[7] (2842:2842:2842) (3107:3107:3107)) + (PORT d[8] (3605:3605:3605) (3755:3755:3755)) + (PORT d[9] (1157:1157:1157) (1203:1203:1203)) + (PORT d[10] (4314:4314:4314) (4615:4615:4615)) + (PORT d[11] (3873:3873:3873) (4130:4130:4130)) + (PORT d[12] (1171:1171:1171) (1229:1229:1229)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) ) ) (TIMINGCHECK @@ -48544,11 +34941,11 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.we_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2569:2569:2569) (2625:2625:2625)) - (PORT clk (1844:1844:1844) (1871:1871:1871)) + (PORT d[0] (1490:1490:1490) (1463:1463:1463)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) ) ) (TIMINGCHECK @@ -48557,60 +34954,60 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.active_core_port_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1847:1847:1847) (1875:1875:1875)) - (PORT d[0] (2985:2985:2985) (3047:3047:3047)) + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (PORT d[0] (2399:2399:2399) (2365:2365:2365)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.wpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1848:1848:1848) (1876:1876:1876)) + (PORT clk (1861:1861:1861) (1888:1888:1888)) (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1848:1848:1848) (1876:1876:1876)) + (PORT clk (1861:1861:1861) (1888:1888:1888)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.ftpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1848:1848:1848) (1876:1876:1876)) + (PORT clk (1861:1861:1861) (1888:1888:1888)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rwpgen_a) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1848:1848:1848) (1876:1876:1876)) + (PORT clk (1861:1861:1861) (1888:1888:1888)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.dataout_a_register) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1807:1807:1807) (1834:1834:1834)) + (PORT clk (1820:1820:1820) (1846:1846:1846)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -48621,38 +35018,38 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.active_core_port_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (992:992:992) (997:997:997)) + (PORT clk (1005:1005:1005) (1009:1009:1009)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (993:993:993) (998:998:998)) + (PORT clk (1006:1006:1006) (1010:1010:1010)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.ftpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (993:993:993) (998:998:998)) + (PORT clk (1006:1006:1006) (1010:1010:1010)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rwpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (993:993:993) (998:998:998)) + (PORT clk (1006:1006:1006) (1010:1010:1010)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) @@ -48662,7 +35059,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (672:672:672) (698:698:698)) + (PORT d[0] (673:673:673) (710:710:710)) (PORT clk (1851:1851:1851) (1879:1879:1879)) ) ) @@ -48675,19 +35072,19 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (3032:3032:3032) (3215:3215:3215)) - (PORT d[1] (1378:1378:1378) (1491:1491:1491)) - (PORT d[2] (2016:2016:2016) (2093:2093:2093)) - (PORT d[3] (2186:2186:2186) (2283:2283:2283)) - (PORT d[4] (1556:1556:1556) (1641:1641:1641)) - (PORT d[5] (1392:1392:1392) (1479:1479:1479)) - (PORT d[6] (1191:1191:1191) (1221:1221:1221)) - (PORT d[7] (3356:3356:3356) (3523:3523:3523)) - (PORT d[8] (2486:2486:2486) (2673:2673:2673)) - (PORT d[9] (3482:3482:3482) (3624:3624:3624)) - (PORT d[10] (2885:2885:2885) (3060:3060:3060)) - (PORT d[11] (1777:1777:1777) (1854:1854:1854)) - (PORT d[12] (1425:1425:1425) (1448:1448:1448)) + (PORT d[0] (1483:1483:1483) (1549:1549:1549)) + (PORT d[1] (4915:4915:4915) (5068:5068:5068)) + (PORT d[2] (2938:2938:2938) (3151:3151:3151)) + (PORT d[3] (1865:1865:1865) (1973:1973:1973)) + (PORT d[4] (1455:1455:1455) (1521:1521:1521)) + (PORT d[5] (1706:1706:1706) (1782:1782:1782)) + (PORT d[6] (1587:1587:1587) (1637:1637:1637)) + (PORT d[7] (2163:2163:2163) (2307:2307:2307)) + (PORT d[8] (2866:2866:2866) (3048:3048:3048)) + (PORT d[9] (2802:2802:2802) (3009:3009:3009)) + (PORT d[10] (2515:2515:2515) (2695:2695:2695)) + (PORT d[11] (2310:2310:2310) (2437:2437:2437)) + (PORT d[12] (3002:3002:3002) (3102:3102:3102)) (PORT clk (1848:1848:1848) (1875:1875:1875)) ) ) @@ -48700,7 +35097,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a3.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1966:1966:1966) (1924:1924:1924)) + (PORT d[0] (2297:2297:2297) (2314:2314:2314)) (PORT clk (1848:1848:1848) (1875:1875:1875)) ) ) @@ -48714,7 +35111,7 @@ (DELAY (ABSOLUTE (PORT clk (1851:1851:1851) (1879:1879:1879)) - (PORT d[0] (2989:2989:2989) (2983:2983:2983)) + (PORT d[0] (1975:1975:1975) (1961:1961:1961)) ) ) ) @@ -48810,13 +35207,181 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (937:937:937) (967:967:967)) + (PORT clk (1850:1850:1850) (1878:1878:1878)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1499:1499:1499) (1536:1536:1536)) + (PORT d[1] (1885:1885:1885) (1998:1998:1998)) + (PORT d[2] (1901:1901:1901) (2033:2033:2033)) + (PORT d[3] (1833:1833:1833) (1903:1903:1903)) + (PORT d[4] (1733:1733:1733) (1793:1793:1793)) + (PORT d[5] (1393:1393:1393) (1463:1463:1463)) + (PORT d[6] (1726:1726:1726) (1772:1772:1772)) + (PORT d[7] (1830:1830:1830) (1968:1968:1968)) + (PORT d[8] (2835:2835:2835) (3009:3009:3009)) + (PORT d[9] (3113:3113:3113) (3322:3322:3322)) + (PORT d[10] (1759:1759:1759) (1852:1852:1852)) + (PORT d[11] (2264:2264:2264) (2387:2387:2387)) + (PORT d[12] (2709:2709:2709) (2808:2808:2808)) + (PORT clk (1847:1847:1847) (1874:1874:1874)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1756:1756:1756) (1705:1705:1705)) + (PORT clk (1847:1847:1847) (1874:1874:1874)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1878:1878:1878)) + (PORT d[0] (1769:1769:1769) (1741:1741:1741)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1810:1810:1810) (1837:1837:1837)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (1000:1000:1000)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a19.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[3\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (742:742:742) (848:848:848)) + (PORT datab (639:639:639) (650:650:650)) + (PORT datad (894:894:894) (895:895:895)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_ram_register") (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (988:988:988) (1034:1034:1034)) - (PORT clk (1852:1852:1852) (1879:1879:1879)) + (PORT d[0] (963:963:963) (997:997:997)) + (PORT clk (1851:1851:1851) (1879:1879:1879)) ) ) (TIMINGCHECK @@ -48828,20 +35393,20 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (3012:3012:3012) (3174:3174:3174)) - (PORT d[1] (1364:1364:1364) (1477:1477:1477)) - (PORT d[2] (1640:1640:1640) (1735:1735:1735)) - (PORT d[3] (1512:1512:1512) (1577:1577:1577)) - (PORT d[4] (1911:1911:1911) (1988:1988:1988)) - (PORT d[5] (1627:1627:1627) (1743:1743:1743)) - (PORT d[6] (1358:1358:1358) (1370:1370:1370)) - (PORT d[7] (1444:1444:1444) (1493:1493:1493)) - (PORT d[8] (2152:2152:2152) (2337:2337:2337)) - (PORT d[9] (3818:3818:3818) (3964:3964:3964)) - (PORT d[10] (2602:2602:2602) (2756:2756:2756)) - (PORT d[11] (1824:1824:1824) (1907:1907:1907)) - (PORT d[12] (2034:2034:2034) (2077:2077:2077)) - (PORT clk (1849:1849:1849) (1875:1875:1875)) + (PORT d[0] (1776:1776:1776) (1835:1835:1835)) + (PORT d[1] (4575:4575:4575) (4749:4749:4749)) + (PORT d[2] (1693:1693:1693) (1828:1828:1828)) + (PORT d[3] (2896:2896:2896) (3023:3023:3023)) + (PORT d[4] (4166:4166:4166) (4317:4317:4317)) + (PORT d[5] (1736:1736:1736) (1799:1799:1799)) + (PORT d[6] (3621:3621:3621) (3744:3744:3744)) + (PORT d[7] (2168:2168:2168) (2330:2330:2330)) + (PORT d[8] (2799:2799:2799) (2963:2963:2963)) + (PORT d[9] (2778:2778:2778) (2982:2982:2982)) + (PORT d[10] (2510:2510:2510) (2687:2687:2687)) + (PORT d[11] (1966:1966:1966) (2071:2071:2071)) + (PORT d[12] (3629:3629:3629) (3803:3803:3803)) + (PORT clk (1848:1848:1848) (1875:1875:1875)) ) ) (TIMINGCHECK @@ -48853,8 +35418,8 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1660:1660:1660) (1642:1642:1642)) - (PORT clk (1849:1849:1849) (1875:1875:1875)) + (PORT d[0] (1496:1496:1496) (1451:1451:1451)) + (PORT clk (1848:1848:1848) (1875:1875:1875)) ) ) (TIMINGCHECK @@ -48866,8 +35431,8 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1852:1852:1852) (1879:1879:1879)) - (PORT d[0] (2201:2201:2201) (2225:2225:2225)) + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (PORT d[0] (2606:2606:2606) (2654:2654:2654)) ) ) ) @@ -48876,7 +35441,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_a) (DELAY (ABSOLUTE - (PORT clk (1853:1853:1853) (1880:1880:1880)) + (PORT clk (1852:1852:1852) (1880:1880:1880)) (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) ) ) @@ -48886,7 +35451,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1853:1853:1853) (1880:1880:1880)) + (PORT clk (1852:1852:1852) (1880:1880:1880)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) @@ -48896,7 +35461,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_a) (DELAY (ABSOLUTE - (PORT clk (1853:1853:1853) (1880:1880:1880)) + (PORT clk (1852:1852:1852) (1880:1880:1880)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) @@ -48906,7 +35471,7 @@ (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_a) (DELAY (ABSOLUTE - (PORT clk (1853:1853:1853) (1880:1880:1880)) + (PORT clk (1852:1852:1852) (1880:1880:1880)) (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) ) ) @@ -48914,288 +35479,6 @@ (CELL (CELLTYPE "cycloneive_ram_register") (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1812:1812:1812) (1838:1838:1838)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (997:997:997) (1001:1001:1001)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (998:998:998) (1002:1002:1002)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~73) - (DELAY - (ABSOLUTE - (PORT dataa (627:627:627) (653:653:653)) - (PORT datab (1345:1345:1345) (1422:1422:1422)) - (PORT datac (885:885:885) (921:921:921)) - (PORT datad (1162:1162:1162) (1219:1219:1219)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1287:1287:1287) (1355:1355:1355)) - (PORT clk (1847:1847:1847) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3658:3658:3658) (3886:3886:3886)) - (PORT d[1] (1696:1696:1696) (1864:1864:1864)) - (PORT d[2] (3022:3022:3022) (3145:3145:3145)) - (PORT d[3] (2178:2178:2178) (2273:2273:2273)) - (PORT d[4] (2261:2261:2261) (2381:2381:2381)) - (PORT d[5] (2406:2406:2406) (2602:2602:2602)) - (PORT d[6] (2067:2067:2067) (2147:2147:2147)) - (PORT d[7] (2761:2761:2761) (2873:2873:2873)) - (PORT d[8] (3032:3032:3032) (3240:3240:3240)) - (PORT d[9] (2561:2561:2561) (2657:2657:2657)) - (PORT d[10] (3754:3754:3754) (3977:3977:3977)) - (PORT d[11] (1812:1812:1812) (1889:1889:1889)) - (PORT d[12] (2036:2036:2036) (2121:2121:2121)) - (PORT clk (1844:1844:1844) (1871:1871:1871)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2791:2791:2791) (2784:2784:2784)) - (PORT clk (1844:1844:1844) (1871:1871:1871)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1847:1847:1847) (1875:1875:1875)) - (PORT d[0] (2736:2736:2736) (2702:2702:2702)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1807:1807:1807) (1834:1834:1834)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (992:992:992) (997:997:997)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (993:993:993) (998:998:998)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (993:993:993) (998:998:998)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a27.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (993:993:993) (998:998:998)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~74) - (DELAY - (ABSOLUTE - (PORT dataa (1203:1203:1203) (1271:1271:1271)) - (PORT datab (935:935:935) (963:963:963)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (1431:1431:1431) (1479:1479:1479)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3642:3642:3642) (3806:3806:3806)) - (PORT d[1] (2601:2601:2601) (2824:2824:2824)) - (PORT d[2] (1657:1657:1657) (1747:1747:1747)) - (PORT d[3] (2161:2161:2161) (2264:2264:2264)) - (PORT d[4] (1866:1866:1866) (1940:1940:1940)) - (PORT d[5] (1348:1348:1348) (1465:1465:1465)) - (PORT d[6] (1148:1148:1148) (1176:1176:1176)) - (PORT d[7] (1458:1458:1458) (1492:1492:1492)) - (PORT d[8] (2173:2173:2173) (2360:2360:2360)) - (PORT d[9] (3841:3841:3841) (3989:3989:3989)) - (PORT d[10] (2571:2571:2571) (2714:2714:2714)) - (PORT d[11] (2100:2100:2100) (2188:2188:2188)) - (PORT d[12] (2024:2024:2024) (2056:2056:2056)) - (PORT clk (1848:1848:1848) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1848:1848:1848) (1875:1875:1875)) - (PORT d[0] (3353:3353:3353) (3478:3478:3478)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1849:1849:1849) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) (DELAY (ABSOLUTE (PORT clk (1811:1811:1811) (1838:1838:1838)) @@ -49209,7 +35492,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_register") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) (DELAY (ABSOLUTE (PORT clk (996:996:996) (1001:1001:1001)) @@ -49218,7 +35501,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) (DELAY (ABSOLUTE (PORT clk (997:997:997) (1002:1002:1002)) @@ -49227,7 +35510,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) (DELAY (ABSOLUTE (PORT clk (997:997:997) (1002:1002:1002)) @@ -49237,7 +35520,7 @@ ) (CELL (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) (DELAY (ABSOLUTE (PORT clk (997:997:997) (1002:1002:1002)) @@ -49245,218 +35528,17 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.datain_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (1472:1472:1472) (1543:1543:1543)) - (PORT clk (1846:1846:1846) (1875:1875:1875)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (3349:3349:3349) (3537:3537:3537)) - (PORT d[1] (2304:2304:2304) (2505:2505:2505)) - (PORT d[2] (2195:2195:2195) (2287:2287:2287)) - (PORT d[3] (1835:1835:1835) (1941:1941:1941)) - (PORT d[4] (2157:2157:2157) (2255:2255:2255)) - (PORT d[5] (1649:1649:1649) (1788:1788:1788)) - (PORT d[6] (1483:1483:1483) (1506:1506:1506)) - (PORT d[7] (1491:1491:1491) (1524:1524:1524)) - (PORT d[8] (2907:2907:2907) (3105:3105:3105)) - (PORT d[9] (2279:2279:2279) (2414:2414:2414)) - (PORT d[10] (2285:2285:2285) (2382:2382:2382)) - (PORT d[11] (2475:2475:2475) (2611:2611:2611)) - (PORT d[12] (1976:1976:1976) (2027:2027:2027)) - (PORT clk (1843:1843:1843) (1871:1871:1871)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.we_a_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2840:2840:2840) (2830:2830:2830)) - (PORT clk (1843:1843:1843) (1871:1871:1871)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) - (DELAY - (ABSOLUTE - (PORT clk (1846:1846:1846) (1875:1875:1875)) - (PORT d[0] (3982:3982:3982) (4087:4087:4087)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1847:1847:1847) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1847:1847:1847) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1847:1847:1847) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_a) - (DELAY - (ABSOLUTE - (PORT clk (1847:1847:1847) (1876:1876:1876)) - (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) - (DELAY - (ABSOLUTE - (PORT clk (1801:1801:1801) (1800:1800:1800)) - (IOPATH (posedge clk) q (301:301:301) (301:301:301)) - ) - ) - (TIMINGCHECK - (SETUP d (posedge clk) (51:51:51)) - (HOLD d (posedge clk) (159:159:159)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.datain_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (2301:2301:2301) (2290:2290:2290)) - (PORT clk (1811:1811:1811) (1806:1806:1806)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.addr_b_register) - (DELAY - (ABSOLUTE - (PORT d[0] (4340:4340:4340) (4420:4420:4420)) - (PORT d[1] (4239:4239:4239) (4282:4282:4282)) - (PORT d[2] (4257:4257:4257) (4315:4315:4315)) - (PORT d[3] (4538:4538:4538) (4588:4588:4588)) - (PORT d[4] (4287:4287:4287) (4306:4306:4306)) - (PORT d[5] (4351:4351:4351) (4371:4371:4371)) - (PORT d[6] (4481:4481:4481) (4572:4572:4572)) - (PORT d[7] (4342:4342:4342) (4398:4398:4398)) - (PORT d[8] (4597:4597:4597) (4592:4592:4592)) - (PORT d[9] (4469:4469:4469) (4739:4739:4739)) - (PORT d[10] (4352:4352:4352) (4394:4394:4394)) - (PORT d[11] (4350:4350:4350) (4370:4370:4370)) - (PORT d[12] (4626:4626:4626) (4608:4608:4608)) - (PORT clk (1807:1807:1807) (1802:1802:1802)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (187:187:187)) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_register") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) - (DELAY - (ABSOLUTE - (PORT clk (1811:1811:1811) (1806:1806:1806)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1812:1812:1812) (1807:1807:1807)) - (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1812:1812:1812) (1807:1807:1807)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1812:1812:1812) (1807:1807:1807)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_ram_pulse_generator") - (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) - (DELAY - (ABSOLUTE - (PORT clk (1812:1812:1812) (1807:1807:1807)) - (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~70) + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[3\]\~7) (DELAY (ABSOLUTE - (PORT dataa (886:886:886) (944:944:944)) - (PORT datab (1682:1682:1682) (1751:1751:1751)) - (PORT datac (910:910:910) (950:950:950)) - (PORT datad (1193:1193:1193) (1243:1243:1243)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT dataa (1555:1555:1555) (1629:1629:1629)) + (PORT datab (1068:1068:1068) (1073:1073:1073)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (920:920:920) (938:938:938)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -49467,20 +35549,20 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (3603:3603:3603) (3780:3780:3780)) - (PORT d[1] (2612:2612:2612) (2820:2820:2820)) - (PORT d[2] (1542:1542:1542) (1613:1613:1613)) - (PORT d[3] (2126:2126:2126) (2248:2248:2248)) - (PORT d[4] (2158:2158:2158) (2252:2252:2252)) - (PORT d[5] (1643:1643:1643) (1776:1776:1776)) - (PORT d[6] (1395:1395:1395) (1417:1417:1417)) - (PORT d[7] (1473:1473:1473) (1509:1509:1509)) - (PORT d[8] (2157:2157:2157) (2322:2322:2322)) - (PORT d[9] (2292:2292:2292) (2444:2444:2444)) - (PORT d[10] (2276:2276:2276) (2402:2402:2402)) - (PORT d[11] (2115:2115:2115) (2225:2225:2225)) - (PORT d[12] (2288:2288:2288) (2338:2338:2338)) - (PORT clk (1846:1846:1846) (1873:1873:1873)) + (PORT d[0] (3390:3390:3390) (3666:3666:3666)) + (PORT d[1] (4281:4281:4281) (4436:4436:4436)) + (PORT d[2] (2345:2345:2345) (2515:2515:2515)) + (PORT d[3] (2564:2564:2564) (2692:2692:2692)) + (PORT d[4] (4103:4103:4103) (4254:4254:4254)) + (PORT d[5] (2082:2082:2082) (2178:2178:2178)) + (PORT d[6] (3273:3273:3273) (3383:3383:3383)) + (PORT d[7] (3289:3289:3289) (3476:3476:3476)) + (PORT d[8] (2493:2493:2493) (2604:2604:2604)) + (PORT d[9] (2780:2780:2780) (2975:2975:2975)) + (PORT d[10] (2224:2224:2224) (2398:2398:2398)) + (PORT d[11] (2350:2350:2350) (2448:2448:2448)) + (PORT d[12] (3337:3337:3337) (3492:3492:3492)) + (PORT clk (1847:1847:1847) (1874:1874:1874)) ) ) (TIMINGCHECK @@ -49492,8 +35574,8 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1846:1846:1846) (1873:1873:1873)) - (PORT d[0] (3448:3448:3448) (3327:3327:3327)) + (PORT clk (1847:1847:1847) (1874:1874:1874)) + (PORT d[0] (4670:4670:4670) (4544:4544:4544)) ) ) ) @@ -49502,7 +35584,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1847:1847:1847) (1874:1874:1874)) + (PORT clk (1848:1848:1848) (1875:1875:1875)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) @@ -49512,7 +35594,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1809:1809:1809) (1836:1836:1836)) + (PORT clk (1810:1810:1810) (1837:1837:1837)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -49526,7 +35608,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (994:994:994) (999:999:999)) + (PORT clk (995:995:995) (1000:1000:1000)) ) ) ) @@ -49535,7 +35617,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (995:995:995) (1000:1000:1000)) + (PORT clk (996:996:996) (1001:1001:1001)) ) ) ) @@ -49544,7 +35626,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (995:995:995) (1000:1000:1000)) + (PORT clk (996:996:996) (1001:1001:1001)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) @@ -49554,24 +35636,306 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (995:995:995) (1000:1000:1000)) + (PORT clk (996:996:996) (1001:1001:1001)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~71) + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) (DELAY (ABSOLUTE - (PORT dataa (230:230:230) (276:276:276)) - (PORT datab (906:906:906) (941:941:941)) - (PORT datac (1129:1129:1129) (1177:1177:1177)) - (PORT datad (181:181:181) (209:209:209)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT d[0] (2571:2571:2571) (2717:2717:2717)) + (PORT d[1] (2866:2866:2866) (2983:2983:2983)) + (PORT d[2] (2017:2017:2017) (2175:2175:2175)) + (PORT d[3] (2450:2450:2450) (2565:2565:2565)) + (PORT d[4] (2353:2353:2353) (2464:2464:2464)) + (PORT d[5] (2400:2400:2400) (2521:2521:2521)) + (PORT d[6] (3248:3248:3248) (3366:3366:3366)) + (PORT d[7] (2069:2069:2069) (2197:2197:2197)) + (PORT d[8] (2413:2413:2413) (2506:2506:2506)) + (PORT d[9] (3015:3015:3015) (3237:3237:3237)) + (PORT d[10] (3895:3895:3895) (4155:4155:4155)) + (PORT d[11] (2298:2298:2298) (2420:2420:2420)) + (PORT d[12] (2690:2690:2690) (2811:2811:2811)) + (PORT clk (1859:1859:1859) (1885:1885:1885)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1885:1885:1885)) + (PORT d[0] (3635:3635:3635) (3699:3699:3699)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1886:1886:1886)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1822:1822:1822) (1848:1848:1848)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1007:1007:1007) (1011:1011:1011)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1008:1008:1008) (1012:1012:1012)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1008:1008:1008) (1012:1012:1012)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1008:1008:1008) (1012:1012:1012)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1618:1618:1618) (1721:1721:1721)) + (PORT clk (1848:1848:1848) (1876:1876:1876)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3132:3132:3132) (3373:3373:3373)) + (PORT d[1] (3979:3979:3979) (4148:4148:4148)) + (PORT d[2] (2052:2052:2052) (2220:2220:2220)) + (PORT d[3] (2223:2223:2223) (2345:2345:2345)) + (PORT d[4] (3835:3835:3835) (3970:3970:3970)) + (PORT d[5] (2376:2376:2376) (2490:2490:2490)) + (PORT d[6] (3017:3017:3017) (3129:3129:3129)) + (PORT d[7] (3020:3020:3020) (3170:3170:3170)) + (PORT d[8] (2470:2470:2470) (2585:2585:2585)) + (PORT d[9] (2475:2475:2475) (2647:2647:2647)) + (PORT d[10] (2936:2936:2936) (3120:3120:3120)) + (PORT d[11] (2315:2315:2315) (2426:2426:2426)) + (PORT d[12] (3050:3050:3050) (3185:3185:3185)) + (PORT clk (1845:1845:1845) (1872:1872:1872)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2050:2050:2050) (2036:2036:2036)) + (PORT clk (1845:1845:1845) (1872:1872:1872)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1876:1876:1876)) + (PORT d[0] (5470:5470:5470) (5591:5591:5591)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1803:1803:1803) (1801:1801:1801)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2106:2106:2106) (2320:2320:2320)) + (PORT clk (1813:1813:1813) (1807:1807:1807)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4170:4170:4170) (4263:4263:4263)) + (PORT d[1] (4283:4283:4283) (4356:4356:4356)) + (PORT d[2] (4122:4122:4122) (4213:4213:4213)) + (PORT d[3] (4257:4257:4257) (4365:4365:4365)) + (PORT d[4] (4105:4105:4105) (4265:4265:4265)) + (PORT d[5] (4360:4360:4360) (4467:4467:4467)) + (PORT d[6] (4086:4086:4086) (4153:4153:4153)) + (PORT d[7] (4082:4082:4082) (4201:4201:4201)) + (PORT d[8] (4244:4244:4244) (4296:4296:4296)) + (PORT d[9] (4129:4129:4129) (4241:4241:4241)) + (PORT d[10] (4179:4179:4179) (4236:4236:4236)) + (PORT d[11] (4332:4332:4332) (4408:4408:4408)) + (PORT d[12] (4199:4199:4199) (4244:4244:4244)) + (PORT clk (1809:1809:1809) (1803:1803:1803)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1813:1813:1813) (1807:1807:1807)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1814:1814:1814) (1808:1808:1808)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1814:1814:1814) (1808:1808:1808)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1814:1814:1814) (1808:1808:1808)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1814:1814:1814) (1808:1808:1808)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) @@ -49580,7 +35944,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1549:1549:1549) (1631:1631:1631)) + (PORT d[0] (1626:1626:1626) (1746:1746:1746)) (PORT clk (1862:1862:1862) (1888:1888:1888)) ) ) @@ -49593,19 +35957,19 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2520:2520:2520) (2617:2617:2617)) - (PORT d[1] (1962:1962:1962) (2122:2122:2122)) - (PORT d[2] (1955:1955:1955) (2077:2077:2077)) - (PORT d[3] (1876:1876:1876) (2000:2000:2000)) - (PORT d[4] (2723:2723:2723) (2864:2864:2864)) - (PORT d[5] (2232:2232:2232) (2416:2416:2416)) - (PORT d[6] (2043:2043:2043) (2115:2115:2115)) - (PORT d[7] (2404:2404:2404) (2531:2531:2531)) - (PORT d[8] (2398:2398:2398) (2577:2577:2577)) - (PORT d[9] (1996:1996:1996) (2101:2101:2101)) - (PORT d[10] (1691:1691:1691) (1769:1769:1769)) - (PORT d[11] (2047:2047:2047) (2128:2128:2128)) - (PORT d[12] (2520:2520:2520) (2605:2605:2605)) + (PORT d[0] (3032:3032:3032) (3145:3145:3145)) + (PORT d[1] (3400:3400:3400) (3508:3508:3508)) + (PORT d[2] (2324:2324:2324) (2504:2504:2504)) + (PORT d[3] (2415:2415:2415) (2549:2549:2549)) + (PORT d[4] (2681:2681:2681) (2805:2805:2805)) + (PORT d[5] (2687:2687:2687) (2824:2824:2824)) + (PORT d[6] (3773:3773:3773) (3895:3895:3895)) + (PORT d[7] (2122:2122:2122) (2230:2230:2230)) + (PORT d[8] (2623:2623:2623) (2737:2737:2737)) + (PORT d[9] (3006:3006:3006) (3209:3209:3209)) + (PORT d[10] (3661:3661:3661) (3927:3927:3927)) + (PORT d[11] (2644:2644:2644) (2790:2790:2790)) + (PORT d[12] (2960:2960:2960) (3114:3114:3114)) (PORT clk (1859:1859:1859) (1884:1884:1884)) ) ) @@ -49618,7 +35982,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.we_a_register) (DELAY (ABSOLUTE - (PORT d[0] (2655:2655:2655) (2640:2640:2640)) + (PORT d[0] (2559:2559:2559) (2640:2640:2640)) (PORT clk (1859:1859:1859) (1884:1884:1884)) ) ) @@ -49632,7 +35996,7 @@ (DELAY (ABSOLUTE (PORT clk (1862:1862:1862) (1888:1888:1888)) - (PORT d[0] (3407:3407:3407) (3339:3339:3339)) + (PORT d[0] (4980:4980:4980) (4896:4896:4896)) ) ) ) @@ -49695,7 +36059,7 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.datain_b_register) (DELAY (ABSOLUTE - (PORT d[0] (2066:2066:2066) (2077:2077:2077)) + (PORT d[0] (1009:1009:1009) (1040:1040:1040)) (PORT clk (1827:1827:1827) (1819:1819:1819)) ) ) @@ -49708,19 +36072,19 @@ (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a3.addr_b_register) (DELAY (ABSOLUTE - (PORT d[0] (4618:4618:4618) (4692:4692:4692)) - (PORT d[1] (4233:4233:4233) (4271:4271:4271)) - (PORT d[2] (4532:4532:4532) (4592:4592:4592)) - (PORT d[3] (4449:4449:4449) (4489:4489:4489)) - (PORT d[4] (4330:4330:4330) (4336:4336:4336)) - (PORT d[5] (4590:4590:4590) (4607:4607:4607)) - (PORT d[6] (4724:4724:4724) (4801:4801:4801)) - (PORT d[7] (4565:4565:4565) (4613:4613:4613)) - (PORT d[8] (4569:4569:4569) (4629:4629:4629)) - (PORT d[9] (4484:4484:4484) (4751:4751:4751)) - (PORT d[10] (4377:4377:4377) (4395:4395:4395)) - (PORT d[11] (4636:4636:4636) (4682:4682:4682)) - (PORT d[12] (4604:4604:4604) (4754:4754:4754)) + (PORT d[0] (4206:4206:4206) (4219:4219:4219)) + (PORT d[1] (4225:4225:4225) (4248:4248:4248)) + (PORT d[2] (4205:4205:4205) (4256:4256:4256)) + (PORT d[3] (4155:4155:4155) (4223:4223:4223)) + (PORT d[4] (4145:4145:4145) (4273:4273:4273)) + (PORT d[5] (4334:4334:4334) (4436:4436:4436)) + (PORT d[6] (4172:4172:4172) (4239:4239:4239)) + (PORT d[7] (4081:4081:4081) (4200:4200:4200)) + (PORT d[8] (4275:4275:4275) (4413:4413:4413)) + (PORT d[9] (4093:4093:4093) (4197:4197:4197)) + (PORT d[10] (4212:4212:4212) (4265:4265:4265)) + (PORT d[11] (4197:4197:4197) (4204:4204:4204)) + (PORT d[12] (4233:4233:4233) (4300:4300:4300)) (PORT clk (1823:1823:1823) (1815:1815:1815)) ) ) @@ -49793,15 +36157,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~72) + (INSTANCE Selector3\~1) (DELAY (ABSOLUTE - (PORT dataa (887:887:887) (946:946:946)) - (PORT datab (206:206:206) (248:248:248)) - (PORT datac (171:171:171) (205:205:205)) - (PORT datad (1482:1482:1482) (1521:1521:1521)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT dataa (626:626:626) (676:676:676)) + (PORT datab (1763:1763:1763) (1794:1794:1794)) + (PORT datac (1241:1241:1241) (1286:1286:1286)) + (PORT datad (1522:1522:1522) (1589:1589:1589)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -49809,15 +36173,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~108) + (INSTANCE Selector3\~2) (DELAY (ABSOLUTE - (PORT dataa (1613:1613:1613) (1669:1669:1669)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (1616:1616:1616) (1701:1701:1701)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (PORT dataa (1323:1323:1323) (1337:1337:1337)) + (PORT datab (1761:1761:1761) (1795:1795:1795)) + (PORT datac (1720:1720:1720) (1775:1775:1775)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -49825,13 +36189,29 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~95) + (INSTANCE D\[3\]\~85) (DELAY (ABSOLUTE - (PORT dataa (209:209:209) (257:257:257)) - (PORT datab (1399:1399:1399) (1458:1458:1458)) - (PORT datac (1325:1325:1325) (1390:1390:1390)) - (PORT datad (341:341:341) (359:359:359)) + (PORT dataa (1884:1884:1884) (2060:2060:2060)) + (PORT datab (3102:3102:3102) (3317:3317:3317)) + (PORT datac (173:173:173) (206:206:206)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[3\]\~73) + (DELAY + (ABSOLUTE + (PORT dataa (2216:2216:2216) (2293:2293:2293)) + (PORT datab (1657:1657:1657) (1691:1691:1691)) + (PORT datac (1127:1127:1127) (1190:1190:1190)) + (PORT datad (180:180:180) (207:207:207)) (IOPATH dataa combout (327:327:327) (347:347:347)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (243:243:243) (241:241:241)) @@ -49841,16 +36221,16 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~96) + (INSTANCE D\[3\]\~74) (DELAY (ABSOLUTE - (PORT dataa (1628:1628:1628) (1657:1657:1657)) - (PORT datab (1397:1397:1397) (1455:1455:1455)) - (PORT datac (1102:1102:1102) (1179:1179:1179)) - (PORT datad (313:313:313) (331:331:331)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (1969:1969:1969) (2019:2019:2019)) + (PORT datab (1656:1656:1656) (1689:1689:1689)) + (PORT datac (1631:1631:1631) (1668:1668:1668)) + (PORT datad (172:172:172) (198:198:198)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -49860,12 +36240,12 @@ (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[3\]) (DELAY (ABSOLUTE - (PORT dataa (975:975:975) (1040:1040:1040)) - (PORT datab (1658:1658:1658) (1724:1724:1724)) - (PORT datac (239:239:239) (291:291:291)) - (PORT datad (875:875:875) (896:896:896)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) + (PORT dataa (1427:1427:1427) (1480:1480:1480)) + (PORT datab (401:401:401) (439:439:439)) + (PORT datac (825:825:825) (872:872:872)) + (PORT datad (1491:1491:1491) (1510:1510:1510)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (306:306:306) (311:311:311)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -49876,9 +36256,9 @@ (INSTANCE z80_\|data_pins_\|dout\[3\]) (DELAY (ABSOLUTE - (PORT clk (1526:1526:1526) (1531:1531:1531)) + (PORT clk (1527:1527:1527) (1531:1531:1531)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (841:841:841) (846:846:846)) + (PORT ena (819:819:819) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -49892,11 +36272,11 @@ (INSTANCE z80_\|bus_control_\|db\[3\]\~20) (DELAY (ABSOLUTE - (PORT dataa (252:252:252) (310:310:310)) - (PORT datab (660:660:660) (727:727:727)) - (PORT datad (213:213:213) (248:248:248)) - (IOPATH dataa combout (301:301:301) (307:307:307)) - (IOPATH datab combout (300:300:300) (311:311:311)) + (PORT datab (360:360:360) (398:398:398)) + (PORT datac (336:336:336) (367:367:367)) + (PORT datad (376:376:376) (438:438:438)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -49906,26 +36286,38 @@ (INSTANCE z80_\|bus_control_\|db\[3\]\~21) (DELAY (ABSOLUTE - (PORT dataa (984:984:984) (1009:1009:1009)) - (PORT datab (906:906:906) (952:952:952)) - (PORT datac (884:884:884) (932:932:932)) - (PORT datad (924:924:924) (947:947:947)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (723:723:723) (780:780:780)) + (PORT datab (692:692:692) (741:741:741)) + (PORT datac (595:595:595) (638:638:638)) + (PORT datad (1670:1670:1670) (1692:1692:1692)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE z80_\|ir_\|opcode\[3\]) + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|b2v_input_bit_select\|bs_out_high_ALTERA_SYNTHESIZED\~2) (DELAY (ABSOLUTE - (PORT clk (1525:1525:1525) (1541:1541:1541)) + (PORT datab (274:274:274) (330:330:330)) + (PORT datac (247:247:247) (310:310:310)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|interrupts_\|im2) + (DELAY + (ABSOLUTE + (PORT clk (1541:1541:1541) (1557:1557:1557)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1571:1571:1571) (1550:1550:1550)) - (PORT ena (1479:1479:1479) (1488:1488:1488)) + (PORT clrn (1567:1567:1567) (1549:1549:1549)) + (PORT ena (1482:1482:1482) (1498:1498:1498)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -49937,13 +36329,2008 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_mWrite\~4) + (INSTANCE z80_\|execute_\|ctl_mRead\~10) (DELAY (ABSOLUTE - (PORT dataa (1465:1465:1465) (1561:1561:1561)) - (PORT datab (1173:1173:1173) (1201:1201:1201)) - (PORT datac (1193:1193:1193) (1280:1280:1280)) - (PORT datad (1406:1406:1406) (1444:1444:1444)) + (PORT dataa (501:501:501) (579:579:579)) + (PORT datab (879:879:879) (976:976:976)) + (PORT datac (269:269:269) (359:359:359)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_sw_mask543_en\~0) + (DELAY + (ABSOLUTE + (PORT dataa (508:508:508) (587:587:587)) + (PORT datab (220:220:220) (259:259:259)) + (PORT datac (616:616:616) (616:616:616)) + (PORT datad (893:893:893) (913:913:913)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[7\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1352:1352:1352) (1488:1488:1488)) + (PORT datab (576:576:576) (605:605:605)) + (PORT datac (832:832:832) (842:842:842)) + (PORT datad (545:545:545) (557:557:557)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[7\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (922:922:922) (952:952:952)) + (PORT datab (368:368:368) (387:387:387)) + (PORT datac (565:565:565) (583:583:583)) + (PORT datad (202:202:202) (230:230:230)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[7\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (861:861:861) (886:886:886)) + (PORT datab (673:673:673) (695:695:695)) + (PORT datac (404:404:404) (447:447:447)) + (PORT datad (172:172:172) (198:198:198)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[7\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datad (362:362:362) (387:387:387)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[7\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1415:1415:1415) (1446:1446:1446)) + (PORT datab (362:362:362) (395:395:395)) + (PORT datad (1352:1352:1352) (1361:1361:1361)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[5\]\~67) + (DELAY + (ABSOLUTE + (PORT dataa (249:249:249) (305:305:305)) + (PORT datab (2795:2795:2795) (2985:2985:2985)) + (PORT datac (554:554:554) (576:576:576)) + (PORT datad (606:606:606) (625:625:625)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (433:433:433) (451:451:451)) + (PORT clk (1858:1858:1858) (1886:1886:1886)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3321:3321:3321) (3530:3530:3530)) + (PORT d[1] (1554:1554:1554) (1635:1635:1635)) + (PORT d[2] (1866:1866:1866) (1937:1937:1937)) + (PORT d[3] (2650:2650:2650) (2849:2849:2849)) + (PORT d[4] (3248:3248:3248) (3394:3394:3394)) + (PORT d[5] (3980:3980:3980) (4138:4138:4138)) + (PORT d[6] (1598:1598:1598) (1673:1673:1673)) + (PORT d[7] (2269:2269:2269) (2463:2463:2463)) + (PORT d[8] (3003:3003:3003) (3126:3126:3126)) + (PORT d[9] (1757:1757:1757) (1842:1842:1842)) + (PORT d[10] (3962:3962:3962) (4221:4221:4221)) + (PORT d[11] (3574:3574:3574) (3779:3779:3779)) + (PORT d[12] (1770:1770:1770) (1850:1850:1850)) + (PORT clk (1855:1855:1855) (1882:1882:1882)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1797:1797:1797) (1804:1804:1804)) + (PORT clk (1855:1855:1855) (1882:1882:1882)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1886:1886:1886)) + (PORT d[0] (2686:2686:2686) (2697:2697:2697)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1818:1818:1818) (1845:1845:1845)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1003:1003:1003) (1008:1008:1008)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1009:1009:1009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1009:1009:1009)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1009:1009:1009)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (713:713:713) (729:729:729)) + (PORT clk (1859:1859:1859) (1886:1886:1886)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3609:3609:3609) (3820:3820:3820)) + (PORT d[1] (1588:1588:1588) (1675:1675:1675)) + (PORT d[2] (1578:1578:1578) (1673:1673:1673)) + (PORT d[3] (2934:2934:2934) (3140:3140:3140)) + (PORT d[4] (3540:3540:3540) (3690:3690:3690)) + (PORT d[5] (4008:4008:4008) (4175:4175:4175)) + (PORT d[6] (1596:1596:1596) (1649:1649:1649)) + (PORT d[7] (2297:2297:2297) (2486:2486:2486)) + (PORT d[8] (3303:3303:3303) (3429:3429:3429)) + (PORT d[9] (1788:1788:1788) (1877:1877:1877)) + (PORT d[10] (3965:3965:3965) (4227:4227:4227)) + (PORT d[11] (3579:3579:3579) (3787:3787:3787)) + (PORT d[12] (1737:1737:1737) (1834:1834:1834)) + (PORT clk (1856:1856:1856) (1882:1882:1882)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1852:1852:1852) (1826:1826:1826)) + (PORT clk (1856:1856:1856) (1882:1882:1882)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1886:1886:1886)) + (PORT d[0] (2578:2578:2578) (2564:2564:2564)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1819:1819:1819) (1845:1845:1845)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1008:1008:1008)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a23.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (825:825:825) (840:840:840)) + (PORT datab (1443:1443:1443) (1548:1548:1548)) + (PORT datac (883:883:883) (887:887:887)) + (PORT datad (1488:1488:1488) (1577:1577:1577)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (705:705:705) (752:752:752)) + (PORT clk (1860:1860:1860) (1888:1888:1888)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3622:3622:3622) (3851:3851:3851)) + (PORT d[1] (1282:1282:1282) (1357:1357:1357)) + (PORT d[2] (1268:1268:1268) (1348:1348:1348)) + (PORT d[3] (2986:2986:2986) (3181:3181:3181)) + (PORT d[4] (3528:3528:3528) (3691:3691:3691)) + (PORT d[5] (4274:4274:4274) (4437:4437:4437)) + (PORT d[6] (1319:1319:1319) (1375:1375:1375)) + (PORT d[7] (2558:2558:2558) (2800:2800:2800)) + (PORT d[8] (3323:3323:3323) (3446:3446:3446)) + (PORT d[9] (2053:2053:2053) (2112:2112:2112)) + (PORT d[10] (3999:3999:3999) (4273:4273:4273)) + (PORT d[11] (3568:3568:3568) (3801:3801:3801)) + (PORT d[12] (1499:1499:1499) (1556:1556:1556)) + (PORT clk (1857:1857:1857) (1884:1884:1884)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1490:1490:1490) (1482:1482:1482)) + (PORT clk (1857:1857:1857) (1884:1884:1884)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1888:1888:1888)) + (PORT d[0] (2685:2685:2685) (2637:2637:2637)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1847:1847:1847)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1010:1010:1010)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1011:1011:1011)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1011:1011:1011)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a31.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1011:1011:1011)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1015:1015:1015) (1051:1051:1051)) + (PORT clk (1860:1860:1860) (1887:1887:1887)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2938:2938:2938) (3189:3189:3189)) + (PORT d[1] (1276:1276:1276) (1338:1338:1338)) + (PORT d[2] (1269:1269:1269) (1331:1331:1331)) + (PORT d[3] (3309:3309:3309) (3542:3542:3542)) + (PORT d[4] (3813:3813:3813) (4002:4002:4002)) + (PORT d[5] (1464:1464:1464) (1519:1519:1519)) + (PORT d[6] (1310:1310:1310) (1355:1355:1355)) + (PORT d[7] (2597:2597:2597) (2822:2822:2822)) + (PORT d[8] (3293:3293:3293) (3442:3442:3442)) + (PORT d[9] (1490:1490:1490) (1549:1549:1549)) + (PORT d[10] (4282:4282:4282) (4575:4575:4575)) + (PORT d[11] (3879:3879:3879) (4130:4130:4130)) + (PORT d[12] (1483:1483:1483) (1560:1560:1560)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1641:1641:1641) (1578:1578:1578)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (PORT d[0] (2502:2502:2502) (2457:2457:2457)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1846:1846:1846)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (1178:1178:1178) (1188:1188:1188)) + (PORT datac (1803:1803:1803) (1899:1899:1899)) + (PORT datad (1338:1338:1338) (1353:1353:1353)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2467:2467:2467) (2663:2663:2663)) + (PORT d[1] (2723:2723:2723) (2844:2844:2844)) + (PORT d[2] (2220:2220:2220) (2326:2326:2326)) + (PORT d[3] (2315:2315:2315) (2492:2492:2492)) + (PORT d[4] (2651:2651:2651) (2757:2757:2757)) + (PORT d[5] (2910:2910:2910) (3032:3032:3032)) + (PORT d[6] (2689:2689:2689) (2779:2779:2779)) + (PORT d[7] (1980:1980:1980) (2172:2172:2172)) + (PORT d[8] (2407:2407:2407) (2482:2482:2482)) + (PORT d[9] (2926:2926:2926) (3008:3008:3008)) + (PORT d[10] (4086:4086:4086) (4372:4372:4372)) + (PORT d[11] (2934:2934:2934) (3119:3119:3119)) + (PORT d[12] (2364:2364:2364) (2475:2475:2475)) + (PORT clk (1866:1866:1866) (1891:1891:1891)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1866:1866:1866) (1891:1891:1891)) + (PORT d[0] (2730:2730:2730) (2773:2773:2773)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1867:1867:1867) (1892:1892:1892)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1829:1829:1829) (1854:1854:1854)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1014:1014:1014) (1017:1017:1017)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1015:1015:1015) (1018:1018:1018)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1015:1015:1015) (1018:1018:1018)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1015:1015:1015) (1018:1018:1018)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1078:1078:1078) (1075:1075:1075)) + (PORT clk (1855:1855:1855) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3337:3337:3337) (3543:3543:3543)) + (PORT d[1] (1935:1935:1935) (2020:2020:2020)) + (PORT d[2] (1898:1898:1898) (1995:1995:1995)) + (PORT d[3] (2945:2945:2945) (3137:3137:3137)) + (PORT d[4] (3259:3259:3259) (3390:3390:3390)) + (PORT d[5] (3698:3698:3698) (3841:3841:3841)) + (PORT d[6] (3247:3247:3247) (3354:3354:3354)) + (PORT d[7] (2249:2249:2249) (2446:2446:2446)) + (PORT d[8] (2991:2991:2991) (3096:3096:3096)) + (PORT d[9] (3392:3392:3392) (3490:3490:3490)) + (PORT d[10] (3958:3958:3958) (4200:4200:4200)) + (PORT d[11] (3288:3288:3288) (3477:3477:3477)) + (PORT d[12] (2051:2051:2051) (2165:2165:2165)) + (PORT clk (1852:1852:1852) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3101:3101:3101) (3111:3111:3111)) + (PORT clk (1852:1852:1852) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1855:1855:1855) (1883:1883:1883)) + (PORT d[0] (3055:3055:3055) (3068:3068:3068)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1810:1810:1810) (1808:1808:1808)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2419:2419:2419) (2599:2599:2599)) + (PORT clk (1820:1820:1820) (1814:1814:1814)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4231:4231:4231) (4215:4215:4215)) + (PORT d[1] (4359:4359:4359) (4372:4372:4372)) + (PORT d[2] (4164:4164:4164) (4188:4188:4188)) + (PORT d[3] (4164:4164:4164) (4242:4242:4242)) + (PORT d[4] (4113:4113:4113) (4265:4265:4265)) + (PORT d[5] (4316:4316:4316) (4445:4445:4445)) + (PORT d[6] (4184:4184:4184) (4238:4238:4238)) + (PORT d[7] (4036:4036:4036) (4137:4137:4137)) + (PORT d[8] (4295:4295:4295) (4299:4299:4299)) + (PORT d[9] (4296:4296:4296) (4400:4400:4400)) + (PORT d[10] (4241:4241:4241) (4307:4307:4307)) + (PORT d[11] (4319:4319:4319) (4408:4408:4408)) + (PORT d[12] (4212:4212:4212) (4259:4259:4259)) + (PORT clk (1816:1816:1816) (1810:1810:1810)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1814:1814:1814)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1821:1821:1821) (1815:1815:1815)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1821:1821:1821) (1815:1815:1815)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1821:1821:1821) (1815:1815:1815)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1821:1821:1821) (1815:1815:1815)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1207:1207:1207) (1211:1211:1211)) + (PORT clk (1853:1853:1853) (1881:1881:1881)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3306:3306:3306) (3496:3496:3496)) + (PORT d[1] (2990:2990:2990) (3143:3143:3143)) + (PORT d[2] (1892:1892:1892) (1990:1990:1990)) + (PORT d[3] (2334:2334:2334) (2532:2532:2532)) + (PORT d[4] (3249:3249:3249) (3381:3381:3381)) + (PORT d[5] (3697:3697:3697) (3840:3840:3840)) + (PORT d[6] (2351:2351:2351) (2442:2442:2442)) + (PORT d[7] (2185:2185:2185) (2360:2360:2360)) + (PORT d[8] (2691:2691:2691) (2784:2784:2784)) + (PORT d[9] (2245:2245:2245) (2325:2325:2325)) + (PORT d[10] (3672:3672:3672) (3909:3909:3909)) + (PORT d[11] (3268:3268:3268) (3478:3478:3478)) + (PORT d[12] (2033:2033:2033) (2161:2161:2161)) + (PORT clk (1850:1850:1850) (1877:1877:1877)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2199:2199:2199) (2195:2195:2195)) + (PORT clk (1850:1850:1850) (1877:1877:1877)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1881:1881:1881)) + (PORT d[0] (3072:3072:3072) (3054:3054:3054)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1808:1808:1808) (1806:1806:1806)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2682:2682:2682) (2860:2860:2860)) + (PORT clk (1818:1818:1818) (1812:1812:1812)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4199:4199:4199) (4194:4194:4194)) + (PORT d[1] (4123:4123:4123) (4119:4119:4119)) + (PORT d[2] (4282:4282:4282) (4380:4380:4380)) + (PORT d[3] (4157:4157:4157) (4224:4224:4224)) + (PORT d[4] (4097:4097:4097) (4250:4250:4250)) + (PORT d[5] (4374:4374:4374) (4426:4426:4426)) + (PORT d[6] (4243:4243:4243) (4281:4281:4281)) + (PORT d[7] (4157:4157:4157) (4210:4210:4210)) + (PORT d[8] (4307:4307:4307) (4339:4339:4339)) + (PORT d[9] (4320:4320:4320) (4416:4416:4416)) + (PORT d[10] (4225:4225:4225) (4267:4267:4267)) + (PORT d[11] (4323:4323:4323) (4416:4416:4416)) + (PORT d[12] (4104:4104:4104) (4195:4195:4195)) + (PORT clk (1814:1814:1814) (1808:1808:1808)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1818:1818:1818) (1812:1812:1812)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1819:1819:1819) (1813:1813:1813)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1819:1819:1819) (1813:1813:1813)) + (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1819:1819:1819) (1813:1813:1813)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1819:1819:1819) (1813:1813:1813)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1810:1810:1810) (1808:1808:1808)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Mux0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1699:1699:1699) (1838:1838:1838)) + (PORT datab (676:676:676) (697:697:697)) + (PORT datac (861:861:861) (889:889:889)) + (PORT datad (1226:1226:1226) (1281:1281:1281)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2758:2758:2758) (2973:2973:2973)) + (PORT d[1] (2459:2459:2459) (2561:2561:2561)) + (PORT d[2] (2454:2454:2454) (2579:2579:2579)) + (PORT d[3] (2605:2605:2605) (2806:2806:2806)) + (PORT d[4] (2391:2391:2391) (2486:2486:2486)) + (PORT d[5] (2623:2623:2623) (2726:2726:2726)) + (PORT d[6] (2453:2453:2453) (2587:2587:2587)) + (PORT d[7] (2233:2233:2233) (2438:2438:2438)) + (PORT d[8] (2128:2128:2128) (2186:2186:2186)) + (PORT d[9] (2932:2932:2932) (3041:3041:3041)) + (PORT d[10] (3805:3805:3805) (4084:4084:4084)) + (PORT d[11] (2563:2563:2563) (2666:2666:2666)) + (PORT d[12] (2766:2766:2766) (2874:2874:2874)) + (PORT clk (1868:1868:1868) (1894:1894:1894)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1868:1868:1868) (1894:1894:1894)) + (PORT d[0] (2808:2808:2808) (2746:2746:2746)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1869:1869:1869) (1895:1895:1895)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1831:1831:1831) (1857:1857:1857)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1016:1016:1016) (1020:1020:1020)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1017:1017:1017) (1021:1021:1021)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1017:1017:1017) (1021:1021:1021)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1017:1017:1017) (1021:1021:1021)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Mux0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1699:1699:1699) (1838:1838:1838)) + (PORT datab (1460:1460:1460) (1484:1484:1484)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (1468:1468:1468) (1528:1528:1528)) + (IOPATH dataa combout (341:341:341) (320:320:320)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[7\]\~89) + (DELAY + (ABSOLUTE + (PORT dataa (2046:2046:2046) (2109:2109:2109)) + (PORT datab (198:198:198) (236:236:236)) + (PORT datac (1678:1678:1678) (1752:1752:1752)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[7\]\~72) + (DELAY + (ABSOLUTE + (PORT dataa (1415:1415:1415) (1492:1492:1492)) + (PORT datab (1626:1626:1626) (1692:1692:1692)) + (PORT datac (171:171:171) (203:203:203)) + (PORT datad (1421:1421:1421) (1438:1438:1438)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~84) + (DELAY + (ABSOLUTE + (PORT dataa (586:586:586) (613:613:613)) + (PORT datab (2797:2797:2797) (2988:2988:2988)) + (PORT datac (586:586:586) (600:600:600)) + (PORT datad (604:604:604) (625:625:625)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[7\]\~80) + (DELAY + (ABSOLUTE + (PORT datac (194:194:194) (227:227:227)) + (PORT datad (1411:1411:1411) (1455:1455:1455)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[7\]) + (DELAY + (ABSOLUTE + (PORT dataa (1429:1429:1429) (1486:1486:1486)) + (PORT datab (220:220:220) (259:259:259)) + (PORT datac (1143:1143:1143) (1216:1216:1216)) + (PORT datad (375:375:375) (401:401:401)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1527:1527:1527) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[7\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (397:397:397) (444:444:444)) + (PORT datab (367:367:367) (389:389:389)) + (PORT datac (604:604:604) (641:641:641)) + (PORT datad (579:579:579) (609:609:609)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1566:1566:1566) (1548:1548:1548)) + (PORT ena (1684:1684:1684) (1669:1669:1669)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (289:289:289) (386:386:386)) + (PORT datab (271:271:271) (355:355:355)) + (PORT datac (397:397:397) (476:476:476)) + (PORT datad (395:395:395) (461:461:461)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal12\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1565:1565:1565) (1693:1693:1693)) + (PORT datab (1560:1560:1560) (1620:1620:1620)) + (PORT datac (1382:1382:1382) (1558:1558:1558)) + (PORT datad (1512:1512:1512) (1630:1630:1630)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~16) + (DELAY + (ABSOLUTE + (PORT dataa (2000:2000:2000) (2198:2198:2198)) + (PORT datab (1217:1217:1217) (1319:1319:1319)) + (PORT datac (679:679:679) (710:710:710)) + (PORT datad (1265:1265:1265) (1358:1358:1358)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~24) + (DELAY + (ABSOLUTE + (PORT dataa (1357:1357:1357) (1405:1405:1405)) + (PORT datab (911:911:911) (960:960:960)) + (PORT datac (859:859:859) (917:917:917)) + (PORT datad (1673:1673:1673) (1702:1702:1702)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~25) + (DELAY + (ABSOLUTE + (PORT dataa (950:950:950) (1026:1026:1026)) + (PORT datab (639:639:639) (660:660:660)) + (PORT datac (603:603:603) (629:629:629)) + (PORT datad (913:913:913) (956:956:956)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~21) + (DELAY + (ABSOLUTE + (PORT dataa (1727:1727:1727) (1799:1799:1799)) + (PORT datab (308:308:308) (404:404:404)) + (PORT datac (627:627:627) (644:644:644)) + (PORT datad (586:586:586) (603:603:603)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~16) + (DELAY + (ABSOLUTE + (PORT dataa (2061:2061:2061) (2163:2163:2163)) + (PORT datab (945:945:945) (981:981:981)) + (PORT datac (1147:1147:1147) (1157:1157:1157)) + (PORT datad (1082:1082:1082) (1111:1111:1111)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1175:1175:1175) (1200:1200:1200)) + (PORT datab (904:904:904) (947:947:947)) + (PORT datac (600:600:600) (633:633:633)) + (PORT datad (402:402:402) (447:447:447)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~15) + (DELAY + (ABSOLUTE + (PORT dataa (2062:2062:2062) (2162:2162:2162)) + (PORT datab (1760:1760:1760) (1802:1802:1802)) + (PORT datac (2157:2157:2157) (2242:2242:2242)) + (PORT datad (937:937:937) (972:972:972)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~12) + (DELAY + (ABSOLUTE + (PORT dataa (990:990:990) (1048:1048:1048)) + (PORT datab (736:736:736) (781:781:781)) + (PORT datac (566:566:566) (589:589:589)) + (PORT datad (1128:1128:1128) (1178:1178:1178)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~11) + (DELAY + (ABSOLUTE + (PORT dataa (649:649:649) (662:662:662)) + (PORT datab (655:655:655) (707:707:707)) + (PORT datac (909:909:909) (932:932:932)) + (PORT datad (1081:1081:1081) (1110:1110:1110)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~13) + (DELAY + (ABSOLUTE + (PORT dataa (610:610:610) (638:638:638)) + (PORT datab (707:707:707) (763:763:763)) + (PORT datac (660:660:660) (697:697:697)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~17) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (242:242:242)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (1234:1234:1234) (1277:1277:1277)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~22) + (DELAY + (ABSOLUTE + (PORT dataa (631:631:631) (660:660:660)) + (PORT datab (608:608:608) (638:638:638)) + (PORT datac (1163:1163:1163) (1218:1218:1218)) + (PORT datad (608:608:608) (647:647:647)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~27) + (DELAY + (ABSOLUTE + (PORT dataa (2262:2262:2262) (2324:2324:2324)) + (PORT datab (1432:1432:1432) (1501:1501:1501)) + (PORT datac (1161:1161:1161) (1183:1183:1183)) + (PORT datad (905:905:905) (948:948:948)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~37) + (DELAY + (ABSOLUTE + (PORT dataa (1527:1527:1527) (1594:1594:1594)) + (PORT datab (608:608:608) (643:643:643)) + (PORT datac (985:985:985) (1077:1077:1077)) + (PORT datad (897:897:897) (960:960:960)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~31) + (DELAY + (ABSOLUTE + (PORT dataa (1161:1161:1161) (1178:1178:1178)) + (PORT datab (922:922:922) (943:943:943)) + (PORT datac (887:887:887) (906:906:906)) + (PORT datad (1299:1299:1299) (1340:1340:1340)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~29) + (DELAY + (ABSOLUTE + (PORT dataa (730:730:730) (805:805:805)) + (PORT datab (1044:1044:1044) (1191:1191:1191)) + (PORT datac (1289:1289:1289) (1355:1355:1355)) + (PORT datad (994:994:994) (1098:1098:1098)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~30) + (DELAY + (ABSOLUTE + (PORT dataa (1098:1098:1098) (1168:1168:1168)) + (PORT datab (227:227:227) (267:267:267)) + (PORT datac (890:890:890) (940:940:940)) + (PORT datad (933:933:933) (975:975:975)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~28) + (DELAY + (ABSOLUTE + (PORT dataa (921:921:921) (946:946:946)) + (PORT datab (1148:1148:1148) (1174:1174:1174)) + (PORT datac (1343:1343:1343) (1359:1359:1359)) + (PORT datad (944:944:944) (997:997:997)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~32) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (255:255:255)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~33) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (244:244:244)) + (PORT datab (215:215:215) (260:260:260)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~23) + (DELAY + (ABSOLUTE + (PORT dataa (1463:1463:1463) (1508:1508:1508)) + (PORT datab (876:876:876) (881:881:881)) + (PORT datac (864:864:864) (889:889:889)) + (PORT datad (616:616:616) (659:659:659)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~34) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (628:628:628) (646:646:646)) + (PORT datac (868:868:868) (883:883:883)) + (PORT datad (636:636:636) (669:669:669)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~35) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (409:409:409)) + (PORT datab (945:945:945) (981:981:981)) + (PORT datac (1115:1115:1115) (1121:1121:1121)) + (PORT datad (1081:1081:1081) (1111:1111:1111)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1553:1553:1553) (1651:1651:1651)) + (PORT datab (1183:1183:1183) (1320:1320:1320)) + (PORT datac (627:627:627) (668:668:668)) + (PORT datad (588:588:588) (600:600:600)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|fMRead\~36) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (245:245:245) (293:293:293)) + (PORT datac (604:604:604) (646:646:646)) + (PORT datad (181:181:181) (210:210:210)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pin_control_\|bus_db_pin_re) + (DELAY + (ABSOLUTE + (PORT dataa (1162:1162:1162) (1235:1235:1235)) + (PORT datac (1054:1054:1054) (1067:1067:1067)) + (PORT datad (764:764:764) (762:762:762)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~118) + (DELAY + (ABSOLUTE + (PORT dataa (996:996:996) (1079:1079:1079)) + (PORT datab (1516:1516:1516) (1598:1598:1598)) + (PORT datac (1146:1146:1146) (1191:1191:1191)) + (PORT datad (1154:1154:1154) (1231:1231:1231)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~119) + (DELAY + (ABSOLUTE + (PORT dataa (1315:1315:1315) (1409:1409:1409)) + (PORT datab (426:426:426) (511:511:511)) + (PORT datac (314:314:314) (332:332:332)) + (PORT datad (624:624:624) (642:642:642)) (IOPATH dataa combout (324:324:324) (328:328:328)) (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -49953,15 +38340,11438 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE z80_\|execute_\|ctl_apin_mux\~2) + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]\~120) (DELAY (ABSOLUTE - (PORT dataa (894:894:894) (970:970:970)) - (PORT datab (221:221:221) (261:261:261)) - (PORT datac (896:896:896) (900:900:900)) + (PORT dataa (199:199:199) (243:243:243)) + (PORT datad (197:197:197) (223:223:223)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1558:1558:1558) (1549:1549:1549)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~129) + (DELAY + (ABSOLUTE + (PORT dataa (434:434:434) (508:508:508)) + (PORT datab (1214:1214:1214) (1261:1261:1261)) + (PORT datac (334:334:334) (361:361:361)) + (PORT datad (677:677:677) (764:764:764)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~116) + (DELAY + (ABSOLUTE + (PORT dataa (788:788:788) (864:864:864)) + (PORT datab (449:449:449) (527:527:527)) + (PORT datad (1018:1018:1018) (1089:1089:1089)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~134) + (DELAY + (ABSOLUTE + (PORT dataa (990:990:990) (1075:1075:1075)) + (PORT datab (1219:1219:1219) (1293:1293:1293)) + (PORT datad (316:316:316) (335:335:335)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]\~117) + (DELAY + (ABSOLUTE + (PORT dataa (635:635:635) (712:712:712)) + (PORT datab (344:344:344) (377:377:377)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1555:1555:1555) (1547:1547:1547)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~60) + (DELAY + (ABSOLUTE + (PORT dataa (1083:1083:1083) (1090:1090:1090)) + (PORT datab (1039:1039:1039) (1115:1115:1115)) + (PORT datac (389:389:389) (452:452:452)) + (PORT datad (848:848:848) (908:908:908)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|Equal0\~2) + (DELAY + (ABSOLUTE + (PORT datab (943:943:943) (1067:1067:1067)) + (PORT datac (709:709:709) (781:781:781)) + (PORT datad (655:655:655) (736:736:736)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]\~121) + (DELAY + (ABSOLUTE + (PORT dataa (935:935:935) (1021:1021:1021)) + (PORT datab (1537:1537:1537) (1611:1611:1611)) + (PORT datad (367:367:367) (393:393:393)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1558:1558:1558) (1550:1550:1550)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]\~115) + (DELAY + (ABSOLUTE + (PORT dataa (211:211:211) (258:258:258)) + (PORT datab (222:222:222) (262:262:262)) + (PORT datad (361:361:361) (382:382:382)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1558:1558:1558) (1549:1549:1549)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\~4) + (DELAY + (ABSOLUTE + (PORT dataa (430:430:430) (499:499:499)) + (PORT datac (2398:2398:2398) (2573:2573:2573)) + (PORT datad (1459:1459:1459) (1518:1518:1518)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~61) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (244:244:244)) + (PORT datab (1122:1122:1122) (1127:1127:1127)) + (PORT datac (215:215:215) (291:291:291)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~124) + (DELAY + (ABSOLUTE + (PORT datab (704:704:704) (778:778:778)) + (PORT datac (275:275:275) (362:362:362)) + (PORT datad (660:660:660) (718:718:718)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~125) + (DELAY + (ABSOLUTE + (PORT dataa (996:996:996) (1073:1073:1073)) + (PORT datab (200:200:200) (239:239:239)) + (PORT datac (602:602:602) (612:612:612)) + (PORT datad (2182:2182:2182) (2284:2284:2284)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]\~126) + (DELAY + (ABSOLUTE + (PORT dataa (606:606:606) (634:634:634)) + (PORT datab (474:474:474) (548:548:548)) + (PORT datad (174:174:174) (198:198:198)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1555:1555:1555) (1548:1548:1548)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~122) + (DELAY + (ABSOLUTE + (PORT dataa (996:996:996) (1072:1072:1072)) + (PORT datab (2218:2218:2218) (2323:2323:2323)) + (PORT datac (952:952:952) (1036:1036:1036)) + (PORT datad (657:657:657) (717:717:717)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]\~123) + (DELAY + (ABSOLUTE + (PORT dataa (923:923:923) (933:933:933)) + (PORT datab (200:200:200) (239:239:239)) + (PORT datad (437:437:437) (511:511:511)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1555:1555:1555) (1548:1548:1548)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~62) + (DELAY + (ABSOLUTE + (PORT dataa (243:243:243) (328:328:328)) + (PORT datab (2091:2091:2091) (2125:2125:2125)) + (PORT datac (864:864:864) (897:897:897)) + (PORT datad (216:216:216) (284:284:284)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~49) + (DELAY + (ABSOLUTE + (PORT dataa (944:944:944) (972:972:972)) + (PORT datab (2243:2243:2243) (2333:2333:2333)) + (PORT datac (835:835:835) (848:848:848)) + (PORT datad (972:972:972) (1027:1027:1027)) (IOPATH dataa combout (327:327:327) (347:347:347)) (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|shifted\~3) + (DELAY + (ABSOLUTE + (PORT datac (1088:1088:1088) (1177:1177:1177)) + (PORT datad (1209:1209:1209) (1270:1270:1270)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]\~127) + (DELAY + (ABSOLUTE + (PORT dataa (784:784:784) (865:865:865)) + (PORT datab (363:363:363) (401:401:401)) + (PORT datad (198:198:198) (224:224:224)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1558:1558:1558) (1550:1550:1550)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]\~128) + (DELAY + (ABSOLUTE + (PORT dataa (777:777:777) (865:865:865)) + (PORT datab (884:884:884) (903:903:903)) + (PORT datad (345:345:345) (368:368:368)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1558:1558:1558) (1550:1550:1550)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~63) + (DELAY + (ABSOLUTE + (PORT dataa (841:841:841) (925:925:925)) + (PORT datab (628:628:628) (655:655:655)) + (PORT datac (1228:1228:1228) (1317:1317:1317)) + (PORT datad (1348:1348:1348) (1469:1469:1469)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~64) + (DELAY + (ABSOLUTE + (PORT dataa (855:855:855) (857:857:857)) + (PORT datab (980:980:980) (994:994:994)) + (PORT datac (2856:2856:2856) (3130:3130:3130)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1003:1003:1003) (1023:1023:1023)) + (PORT clk (1856:1856:1856) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2316:2316:2316) (2413:2413:2413)) + (PORT d[1] (1270:1270:1270) (1336:1336:1336)) + (PORT d[2] (2153:2153:2153) (2308:2308:2308)) + (PORT d[3] (2467:2467:2467) (2629:2629:2629)) + (PORT d[4] (998:998:998) (1054:1054:1054)) + (PORT d[5] (1250:1250:1250) (1291:1291:1291)) + (PORT d[6] (3512:3512:3512) (3548:3548:3548)) + (PORT d[7] (1888:1888:1888) (2045:2045:2045)) + (PORT d[8] (1240:1240:1240) (1295:1295:1295)) + (PORT d[9] (3442:3442:3442) (3722:3722:3722)) + (PORT d[10] (992:992:992) (1040:1040:1040)) + (PORT d[11] (1520:1520:1520) (1555:1555:1555)) + (PORT d[12] (2020:2020:2020) (2068:2068:2068)) + (PORT clk (1853:1853:1853) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1476:1476:1476) (1465:1465:1465)) + (PORT clk (1853:1853:1853) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1883:1883:1883)) + (PORT d[0] (2158:2158:2158) (2124:2124:2124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1816:1816:1816) (1842:1842:1842)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1001:1001:1001) (1005:1005:1005)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1002:1002:1002) (1006:1006:1006)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1002:1002:1002) (1006:1006:1006)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a28.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1002:1002:1002) (1006:1006:1006)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (991:991:991) (1004:1004:1004)) + (PORT clk (1854:1854:1854) (1881:1881:1881)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2556:2556:2556) (2659:2659:2659)) + (PORT d[1] (1257:1257:1257) (1329:1329:1329)) + (PORT d[2] (2368:2368:2368) (2579:2579:2579)) + (PORT d[3] (2792:2792:2792) (2975:2975:2975)) + (PORT d[4] (742:742:742) (799:799:799)) + (PORT d[5] (1249:1249:1249) (1290:1290:1290)) + (PORT d[6] (3491:3491:3491) (3525:3525:3525)) + (PORT d[7] (1866:1866:1866) (2023:2023:2023)) + (PORT d[8] (1212:1212:1212) (1262:1262:1262)) + (PORT d[9] (3469:3469:3469) (3754:3754:3754)) + (PORT d[10] (990:990:990) (1024:1024:1024)) + (PORT d[11] (1507:1507:1507) (1551:1551:1551)) + (PORT d[12] (2277:2277:2277) (2330:2330:2330)) + (PORT clk (1851:1851:1851) (1877:1877:1877)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1984:1984:1984) (1937:1937:1937)) + (PORT clk (1851:1851:1851) (1877:1877:1877)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1881:1881:1881)) + (PORT d[0] (1916:1916:1916) (1885:1885:1885)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1855:1855:1855) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1855:1855:1855) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1855:1855:1855) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1855:1855:1855) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1814:1814:1814) (1840:1840:1840)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (999:999:999) (1003:1003:1003)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1000:1000:1000) (1004:1004:1004)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1000:1000:1000) (1004:1004:1004)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a20.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1000:1000:1000) (1004:1004:1004)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (979:979:979) (1006:1006:1006)) + (PORT clk (1856:1856:1856) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2603:2603:2603) (2726:2726:2726)) + (PORT d[1] (1252:1252:1252) (1326:1326:1326)) + (PORT d[2] (2923:2923:2923) (3153:3153:3153)) + (PORT d[3] (982:982:982) (1016:1016:1016)) + (PORT d[4] (740:740:740) (778:778:778)) + (PORT d[5] (1191:1191:1191) (1244:1244:1244)) + (PORT d[6] (977:977:977) (999:999:999)) + (PORT d[7] (2181:2181:2181) (2361:2361:2361)) + (PORT d[8] (1248:1248:1248) (1302:1302:1302)) + (PORT d[9] (964:964:964) (979:979:979)) + (PORT d[10] (4573:4573:4573) (4886:4886:4886)) + (PORT d[11] (1531:1531:1531) (1576:1576:1576)) + (PORT d[12] (2585:2585:2585) (2670:2670:2670)) + (PORT clk (1853:1853:1853) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (925:925:925) (881:881:881)) + (PORT clk (1853:1853:1853) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1883:1883:1883)) + (PORT d[0] (2184:2184:2184) (2115:2115:2115)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1816:1816:1816) (1842:1842:1842)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1001:1001:1001) (1005:1005:1005)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1002:1002:1002) (1006:1006:1006)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1002:1002:1002) (1006:1006:1006)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1002:1002:1002) (1006:1006:1006)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (747:747:747) (776:776:776)) + (PORT clk (1852:1852:1852) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2600:2600:2600) (2704:2704:2704)) + (PORT d[1] (949:949:949) (995:995:995)) + (PORT d[2] (2647:2647:2647) (2879:2879:2879)) + (PORT d[3] (995:995:995) (1046:1046:1046)) + (PORT d[4] (714:714:714) (746:746:746)) + (PORT d[5] (889:889:889) (921:921:921)) + (PORT d[6] (1226:1226:1226) (1240:1240:1240)) + (PORT d[7] (2177:2177:2177) (2355:2355:2355)) + (PORT d[8] (927:927:927) (954:954:954)) + (PORT d[9] (962:962:962) (980:980:980)) + (PORT d[10] (2172:2172:2172) (2231:2231:2231)) + (PORT d[11] (1185:1185:1185) (1207:1207:1207)) + (PORT d[12] (2316:2316:2316) (2387:2387:2387)) + (PORT clk (1849:1849:1849) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1209:1209:1209) (1166:1166:1166)) + (PORT clk (1849:1849:1849) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1879:1879:1879)) + (PORT d[0] (2107:2107:2107) (2058:2058:2058)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (886:886:886) (945:945:945)) + (PORT datab (874:874:874) (868:868:868)) + (PORT datac (827:827:827) (831:831:831)) + (PORT datad (1376:1376:1376) (1438:1438:1438)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1116:1116:1116) (1150:1150:1150)) + (PORT datab (1109:1109:1109) (1114:1114:1114)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (1746:1746:1746) (1849:1849:1849)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2042:2042:2042) (2133:2133:2133)) + (PORT d[1] (1633:1633:1633) (1690:1690:1690)) + (PORT d[2] (2214:2214:2214) (2383:2383:2383)) + (PORT d[3] (2758:2758:2758) (2918:2918:2918)) + (PORT d[4] (1023:1023:1023) (1094:1094:1094)) + (PORT d[5] (1542:1542:1542) (1600:1600:1600)) + (PORT d[6] (3496:3496:3496) (3536:3536:3536)) + (PORT d[7] (1846:1846:1846) (2009:2009:2009)) + (PORT d[8] (1536:1536:1536) (1608:1608:1608)) + (PORT d[9] (3451:3451:3451) (3717:3717:3717)) + (PORT d[10] (976:976:976) (1035:1035:1035)) + (PORT d[11] (947:947:947) (1004:1004:1004)) + (PORT d[12] (1991:1991:1991) (2028:2028:2028)) + (PORT clk (1856:1856:1856) (1882:1882:1882)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1882:1882:1882)) + (PORT d[0] (2339:2339:2339) (2361:2361:2361)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1883:1883:1883)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1819:1819:1819) (1845:1845:1845)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1008:1008:1008)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1591:1591:1591) (1680:1680:1680)) + (PORT clk (1864:1864:1864) (1891:1891:1891)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2597:2597:2597) (2802:2802:2802)) + (PORT d[1] (2423:2423:2423) (2558:2558:2558)) + (PORT d[2] (2208:2208:2208) (2331:2331:2331)) + (PORT d[3] (2640:2640:2640) (2832:2832:2832)) + (PORT d[4] (2962:2962:2962) (3072:3072:3072)) + (PORT d[5] (3679:3679:3679) (3784:3784:3784)) + (PORT d[6] (2961:2961:2961) (3093:3093:3093)) + (PORT d[7] (1977:1977:1977) (2149:2149:2149)) + (PORT d[8] (2696:2696:2696) (2777:2777:2777)) + (PORT d[9] (2624:2624:2624) (2711:2711:2711)) + (PORT d[10] (3643:3643:3643) (3873:3873:3873)) + (PORT d[11] (3247:3247:3247) (3429:3429:3429)) + (PORT d[12] (2402:2402:2402) (2538:2538:2538)) + (PORT clk (1861:1861:1861) (1887:1887:1887)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2803:2803:2803) (2827:2827:2827)) + (PORT clk (1861:1861:1861) (1887:1887:1887)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1864:1864:1864) (1891:1891:1891)) + (PORT d[0] (3387:3387:3387) (3427:3427:3427)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1865:1865:1865) (1892:1892:1892)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1865:1865:1865) (1892:1892:1892)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1865:1865:1865) (1892:1892:1892)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1865:1865:1865) (1892:1892:1892)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1819:1819:1819) (1816:1816:1816)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2697:2697:2697) (2894:2894:2894)) + (PORT clk (1829:1829:1829) (1822:1822:1822)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4069:4069:4069) (4099:4099:4099)) + (PORT d[1] (4103:4103:4103) (4067:4067:4067)) + (PORT d[2] (4123:4123:4123) (4136:4136:4136)) + (PORT d[3] (4170:4170:4170) (4223:4223:4223)) + (PORT d[4] (4256:4256:4256) (4384:4384:4384)) + (PORT d[5] (4464:4464:4464) (4551:4551:4551)) + (PORT d[6] (4216:4216:4216) (4293:4293:4293)) + (PORT d[7] (4073:4073:4073) (4122:4122:4122)) + (PORT d[8] (4185:4185:4185) (4250:4250:4250)) + (PORT d[9] (4229:4229:4229) (4289:4289:4289)) + (PORT d[10] (4100:4100:4100) (4099:4099:4099)) + (PORT d[11] (4276:4276:4276) (4280:4280:4280)) + (PORT d[12] (4103:4103:4103) (4196:4196:4196)) + (PORT clk (1825:1825:1825) (1818:1818:1818)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1829:1829:1829) (1822:1822:1822)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1830:1830:1830) (1823:1823:1823)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1830:1830:1830) (1823:1823:1823)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1830:1830:1830) (1823:1823:1823)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1830:1830:1830) (1823:1823:1823)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1702:1702:1702) (1829:1829:1829)) + (PORT clk (1844:1844:1844) (1873:1873:1873)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3120:3120:3120) (3377:3377:3377)) + (PORT d[1] (3988:3988:3988) (4117:4117:4117)) + (PORT d[2] (2054:2054:2054) (2224:2224:2224)) + (PORT d[3] (2171:2171:2171) (2286:2286:2286)) + (PORT d[4] (3529:3529:3529) (3657:3657:3657)) + (PORT d[5] (2341:2341:2341) (2458:2458:2458)) + (PORT d[6] (3271:3271:3271) (3376:3376:3376)) + (PORT d[7] (1637:1637:1637) (1757:1757:1757)) + (PORT d[8] (2198:2198:2198) (2315:2315:2315)) + (PORT d[9] (2510:2510:2510) (2590:2590:2590)) + (PORT d[10] (2660:2660:2660) (2871:2871:2871)) + (PORT d[11] (2001:2001:2001) (2095:2095:2095)) + (PORT d[12] (3015:3015:3015) (3165:3165:3165)) + (PORT clk (1841:1841:1841) (1869:1869:1869)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3168:3168:3168) (3259:3259:3259)) + (PORT clk (1841:1841:1841) (1869:1869:1869)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1873:1873:1873)) + (PORT d[0] (5281:5281:5281) (5171:5171:5171)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1874:1874:1874)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1874:1874:1874)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1874:1874:1874)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1874:1874:1874)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1799:1799:1799) (1798:1798:1798)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2386:2386:2386) (2603:2603:2603)) + (PORT clk (1809:1809:1809) (1804:1804:1804)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4219:4219:4219) (4281:4281:4281)) + (PORT d[1] (4270:4270:4270) (4325:4325:4325)) + (PORT d[2] (4095:4095:4095) (4204:4204:4204)) + (PORT d[3] (4293:4293:4293) (4421:4421:4421)) + (PORT d[4] (4107:4107:4107) (4220:4220:4220)) + (PORT d[5] (4318:4318:4318) (4418:4418:4418)) + (PORT d[6] (4128:4128:4128) (4196:4196:4196)) + (PORT d[7] (4078:4078:4078) (4195:4195:4195)) + (PORT d[8] (4287:4287:4287) (4309:4309:4309)) + (PORT d[9] (4099:4099:4099) (4204:4204:4204)) + (PORT d[10] (4255:4255:4255) (4320:4320:4320)) + (PORT d[11] (4343:4343:4343) (4435:4435:4435)) + (PORT d[12] (4182:4182:4182) (4226:4226:4226)) + (PORT clk (1805:1805:1805) (1800:1800:1800)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1809:1809:1809) (1804:1804:1804)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1810:1810:1810) (1805:1805:1805)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1810:1810:1810) (1805:1805:1805)) + (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1810:1810:1810) (1805:1805:1805)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1810:1810:1810) (1805:1805:1805)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1801:1801:1801) (1800:1800:1800)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1639:1639:1639) (1708:1708:1708)) + (PORT d[1] (1271:1271:1271) (1337:1337:1337)) + (PORT d[2] (2348:2348:2348) (2577:2577:2577)) + (PORT d[3] (2790:2790:2790) (2929:2929:2929)) + (PORT d[4] (1002:1002:1002) (1075:1075:1075)) + (PORT d[5] (1507:1507:1507) (1546:1546:1546)) + (PORT d[6] (3478:3478:3478) (3531:3531:3531)) + (PORT d[7] (1876:1876:1876) (2017:2017:2017)) + (PORT d[8] (1552:1552:1552) (1629:1629:1629)) + (PORT d[9] (3460:3460:3460) (3738:3738:3738)) + (PORT d[10] (951:951:951) (1011:1011:1011)) + (PORT d[11] (1492:1492:1492) (1533:1533:1533)) + (PORT d[12] (1997:1997:1997) (2043:2043:2043)) + (PORT clk (1855:1855:1855) (1880:1880:1880)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1855:1855:1855) (1880:1880:1880)) + (PORT d[0] (2338:2338:2338) (2320:2320:2320)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1881:1881:1881)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1818:1818:1818) (1843:1843:1843)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1003:1003:1003) (1006:1006:1006)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1007:1007:1007)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1007:1007:1007)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1007:1007:1007)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1389:1389:1389) (1516:1516:1516)) + (PORT datab (868:868:868) (879:879:879)) + (PORT datac (1474:1474:1474) (1580:1580:1580)) + (PORT datad (1108:1108:1108) (1131:1131:1131)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector4\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1166:1166:1166) (1179:1179:1179)) + (PORT datab (1070:1070:1070) (1089:1089:1089)) + (PORT datac (1676:1676:1676) (1711:1711:1711)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~86) + (DELAY + (ABSOLUTE + (PORT dataa (2693:2693:2693) (2866:2866:2866)) + (PORT datab (1198:1198:1198) (1298:1298:1298)) + (PORT datac (172:172:172) (206:206:206)) + (PORT datad (312:312:312) (324:324:324)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (336:336:336) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~75) + (DELAY + (ABSOLUTE + (PORT dataa (915:915:915) (931:931:931)) + (PORT datab (346:346:346) (372:372:372)) + (PORT datac (886:886:886) (900:900:900)) + (PORT datad (180:180:180) (210:210:210)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~76) + (DELAY + (ABSOLUTE + (PORT dataa (918:918:918) (930:930:930)) + (PORT datab (964:964:964) (1032:1032:1032)) + (PORT datac (1537:1537:1537) (1594:1594:1594)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[4\]) + (DELAY + (ABSOLUTE + (PORT dataa (699:699:699) (756:756:756)) + (PORT datab (398:398:398) (436:436:436)) + (PORT datac (1392:1392:1392) (1434:1434:1434)) + (PORT datad (840:840:840) (886:886:886)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1527:1527:1527) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[4\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (564:564:564) (592:592:592)) + (PORT datab (385:385:385) (461:461:461)) + (PORT datad (579:579:579) (605:605:605)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[4\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (722:722:722) (776:776:776)) + (PORT datab (650:650:650) (703:703:703)) + (PORT datac (619:619:619) (666:666:666)) + (PORT datad (1672:1672:1672) (1695:1695:1695)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1541:1541:1541) (1557:1557:1557)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1567:1567:1567) (1549:1549:1549)) + (PORT ena (1404:1404:1404) (1375:1375:1375)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal32\~0) + (DELAY + (ABSOLUTE + (PORT datab (1215:1215:1215) (1315:1315:1315)) + (PORT datad (1274:1274:1274) (1353:1353:1353)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal41\~1) + (DELAY + (ABSOLUTE + (PORT dataa (481:481:481) (578:578:578)) + (PORT datab (500:500:500) (579:579:579)) + (PORT datac (926:926:926) (1051:1051:1051)) + (PORT datad (976:976:976) (1060:1060:1060)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal41\~2) + (DELAY + (ABSOLUTE + (PORT dataa (2522:2522:2522) (2693:2693:2693)) + (PORT datab (641:641:641) (697:697:697)) + (PORT datac (832:832:832) (846:846:846)) + (PORT datad (915:915:915) (945:945:945)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal36\~0) + (DELAY + (ABSOLUTE + (PORT dataa (792:792:792) (893:893:893)) + (PORT datab (1920:1920:1920) (2012:2012:2012)) + (PORT datac (1274:1274:1274) (1343:1343:1343)) + (PORT datad (869:869:869) (888:888:888)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_tbl_cb_set) + (DELAY + (ABSOLUTE + (PORT dataa (993:993:993) (1045:1045:1045)) + (PORT datab (918:918:918) (947:947:947)) + (PORT datac (1266:1266:1266) (1289:1289:1289)) + (PORT datad (640:640:640) (690:690:690)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_tbl_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1661:1661:1661) (1739:1739:1739)) + (PORT datab (699:699:699) (752:752:752)) + (PORT datac (1265:1265:1265) (1288:1288:1288)) + (PORT datad (631:631:631) (685:685:685)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|decode_state_\|DFFE_instCB) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1566:1566:1566) (1548:1548:1548)) + (PORT ena (790:790:790) (783:783:783)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal52\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1042:1042:1042) (1134:1134:1134)) + (PORT datab (997:997:997) (1103:1103:1103)) + (PORT datac (932:932:932) (1054:1054:1054)) + (PORT datad (973:973:973) (1056:1056:1056)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (739:739:739) (833:833:833)) + (PORT datab (562:562:562) (576:576:576)) + (PORT datac (1143:1143:1143) (1241:1241:1241)) + (PORT datad (1800:1800:1800) (1868:1868:1868)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_state_tbl_ed_set) + (DELAY + (ABSOLUTE + (PORT dataa (1695:1695:1695) (1747:1747:1747)) + (PORT datab (927:927:927) (961:961:961)) + (PORT datac (953:953:953) (1006:1006:1006)) + (PORT datad (386:386:386) (457:457:457)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|decode_state_\|DFFE_instED) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1566:1566:1566) (1548:1548:1548)) + (PORT ena (790:790:790) (783:783:783)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|decode_state_\|table_xx\~0) + (DELAY + (ABSOLUTE + (PORT dataa (289:289:289) (385:385:385)) + (PORT datad (383:383:383) (443:443:443)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal34\~0) + (DELAY + (ABSOLUTE + (PORT dataa (979:979:979) (1062:1062:1062)) + (PORT datab (661:661:661) (688:688:688)) + (PORT datac (566:566:566) (598:598:598)) + (PORT datad (681:681:681) (729:729:729)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1175:1175:1175) (1210:1210:1210)) + (PORT datab (1702:1702:1702) (1772:1772:1772)) + (PORT datac (799:799:799) (820:820:820)) + (PORT datad (1291:1291:1291) (1362:1362:1362)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1325:1325:1325) (1414:1414:1414)) + (PORT datab (691:691:691) (743:743:743)) + (PORT datac (1107:1107:1107) (1128:1128:1128)) + (PORT datad (908:908:908) (955:955:955)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~4) + (DELAY + (ABSOLUTE + (PORT dataa (876:876:876) (916:916:916)) + (PORT datab (1259:1259:1259) (1324:1324:1324)) + (PORT datac (950:950:950) (994:994:994)) + (PORT datad (668:668:668) (713:713:713)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1319:1319:1319) (1408:1408:1408)) + (PORT datab (688:688:688) (747:747:747)) + (PORT datac (846:846:846) (880:880:880)) + (PORT datad (900:900:900) (917:917:917)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1630:1630:1630) (1685:1685:1685)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (955:955:955) (1002:1002:1002)) + (PORT datad (1291:1291:1291) (1368:1368:1368)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~7) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (242:242:242)) + (PORT datab (200:200:200) (240:240:240)) + (PORT datac (600:600:600) (608:608:608)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~8) + (DELAY + (ABSOLUTE + (PORT dataa (817:817:817) (853:853:853)) + (PORT datab (1522:1522:1522) (1531:1531:1531)) + (PORT datac (920:920:920) (963:963:963)) + (PORT datad (669:669:669) (714:714:714)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1178:1178:1178) (1214:1214:1214)) + (PORT datab (933:933:933) (990:990:990)) + (PORT datac (624:624:624) (641:641:641)) + (PORT datad (1672:1672:1672) (1732:1732:1732)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1320:1320:1320) (1407:1407:1407)) + (PORT datab (204:204:204) (246:246:246)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (1348:1348:1348) (1364:1364:1364)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~16) + (DELAY + (ABSOLUTE + (PORT dataa (862:862:862) (922:922:922)) + (PORT datab (1255:1255:1255) (1310:1310:1310)) + (PORT datac (1428:1428:1428) (1489:1489:1489)) + (PORT datad (195:195:195) (220:220:220)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~17) + (DELAY + (ABSOLUTE + (PORT dataa (973:973:973) (1059:1059:1059)) + (PORT datab (1386:1386:1386) (1448:1448:1448)) + (PORT datac (203:203:203) (242:242:242)) + (PORT datad (652:652:652) (687:687:687)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1158:1158:1158) (1234:1234:1234)) + (PORT datab (247:247:247) (295:295:295)) + (PORT datac (874:874:874) (913:913:913)) + (PORT datad (179:179:179) (206:206:206)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_pc\~18) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (371:371:371)) + (PORT datab (1142:1142:1142) (1187:1187:1187)) + (PORT datac (194:194:194) (226:226:226)) + (PORT datad (599:599:599) (612:612:612)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sel_wz\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1844:1844:1844) (1951:1951:1951)) + (PORT datab (1206:1206:1206) (1281:1281:1281)) + (PORT datac (1620:1620:1620) (1731:1731:1731)) + (PORT datad (1706:1706:1706) (1792:1792:1792)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_pc\~3) + (DELAY + (ABSOLUTE + (PORT dataa (664:664:664) (682:682:682)) + (PORT datab (1450:1450:1450) (1461:1461:1461)) + (PORT datac (849:849:849) (882:882:882)) + (PORT datad (637:637:637) (694:694:694)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_control_\|reg_sel_pc) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (241:241:241)) + (PORT datab (890:890:890) (940:940:940)) + (PORT datac (572:572:572) (593:593:593)) + (PORT datad (841:841:841) (863:863:863)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|SYNTHESIZED_WIRE_72) + (DELAY + (ABSOLUTE + (PORT dataa (1040:1040:1040) (1066:1066:1066)) + (PORT datac (1102:1102:1102) (1139:1139:1139)) + (PORT datad (899:899:899) (932:932:932)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1078:1078:1078) (1103:1103:1103)) + (PORT datab (711:711:711) (744:744:744)) + (PORT datac (1364:1364:1364) (1375:1375:1375)) + (PORT datad (648:648:648) (671:671:671)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_pc_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1533:1533:1533)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1256:1256:1256) (1263:1263:1263)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ir_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1533:1533:1533)) + (PORT asdata (537:537:537) (567:567:567)) + (PORT ena (1448:1448:1448) (1437:1437:1437)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (651:651:651) (685:685:685)) + (PORT datab (711:711:711) (743:743:743)) + (PORT datad (649:649:649) (669:669:669)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1079:1079:1079) (1101:1101:1101)) + (PORT datab (379:379:379) (452:452:452)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (301:301:301) (307:307:307)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|db_hi_as\[5\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (244:244:244) (296:296:296)) + (PORT datab (658:658:658) (679:679:679)) + (PORT datac (1367:1367:1367) (1374:1374:1374)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1530:1530:1530)) + (PORT asdata (1388:1388:1388) (1436:1436:1436)) + (PORT ena (1240:1240:1240) (1223:1223:1223)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_hl2_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1517:1517:1517) (1530:1530:1530)) + (PORT asdata (1390:1390:1390) (1437:1437:1437)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~50) + (DELAY + (ABSOLUTE + (PORT dataa (723:723:723) (755:755:755)) + (PORT datab (242:242:242) (323:323:323)) + (PORT datad (233:233:233) (272:272:272)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af2_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1533:1533:1533)) + (PORT asdata (1188:1188:1188) (1204:1204:1204)) + (PORT ena (1201:1201:1201) (1198:1198:1198)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~53) + (DELAY + (ABSOLUTE + (PORT dataa (1201:1201:1201) (1220:1220:1220)) + (PORT datab (1150:1150:1150) (1180:1180:1180)) + (PORT datad (396:396:396) (440:440:440)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_sp_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1533:1533:1533)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1503:1503:1503) (1497:1497:1497)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_wz_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1533:1533:1533)) + (PORT asdata (935:935:935) (960:960:960)) + (PORT ena (1227:1227:1227) (1249:1249:1249)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~54) + (DELAY + (ABSOLUTE + (PORT dataa (705:705:705) (779:779:779)) + (PORT datab (242:242:242) (324:324:324)) + (PORT datad (696:696:696) (747:747:747)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_ix_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT asdata (1458:1458:1458) (1482:1482:1482)) + (PORT ena (1229:1229:1229) (1240:1240:1240)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_iy_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT asdata (1461:1461:1461) (1487:1487:1487)) + (PORT ena (1168:1168:1168) (1147:1147:1147)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~52) + (DELAY + (ABSOLUTE + (PORT dataa (693:693:693) (728:728:728)) + (PORT datab (269:269:269) (323:323:323)) + (PORT datad (217:217:217) (286:286:286)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (1214:1214:1214) (1221:1221:1221)) + (PORT ena (1440:1440:1440) (1419:1419:1419)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_bc2_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (1216:1216:1216) (1225:1225:1225)) + (PORT ena (1225:1225:1225) (1236:1236:1236)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (699:699:699) (763:763:763)) + (PORT datab (243:243:243) (325:325:325)) + (PORT datad (618:618:618) (641:641:641)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~55) + (DELAY + (ABSOLUTE + (PORT dataa (377:377:377) (399:399:399)) + (PORT datab (605:605:605) (629:629:629)) + (PORT datac (540:540:540) (552:552:552)) + (PORT datad (339:339:339) (358:358:358)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (932:932:932) (939:939:939)) + (PORT ena (790:790:790) (782:782:782)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_af_hi\|db\[5\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1536:1536:1536) (1586:1586:1586)) + (PORT datab (2170:2170:2170) (2209:2209:2209)) + (PORT datad (1366:1366:1366) (1388:1388:1388)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de2_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT asdata (985:985:985) (1002:1002:1002)) + (PORT ena (981:981:981) (980:980:980)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (589:589:589) (597:597:597)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|reg_file_\|b2v_latch_de_hi\|latch\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1190:1190:1190) (1164:1164:1164)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~49) + (DELAY + (ABSOLUTE + (PORT dataa (695:695:695) (731:731:731)) + (PORT datab (697:697:697) (721:721:721)) + (PORT datad (217:217:217) (285:285:285)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~56) + (DELAY + (ABSOLUTE + (PORT dataa (814:814:814) (868:868:868)) + (PORT datab (975:975:975) (1017:1017:1017)) + (PORT datac (528:528:528) (538:538:538)) + (PORT datad (342:342:342) (365:365:365)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|reg_file_\|gdfx_temp1\[5\]\~57) + (DELAY + (ABSOLUTE + (PORT dataa (657:657:657) (678:678:678)) + (PORT datab (920:920:920) (958:958:958)) + (PORT datac (1143:1143:1143) (1171:1171:1171)) + (PORT datad (553:553:553) (570:570:570)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[5\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (628:628:628) (667:667:667)) + (PORT datab (689:689:689) (718:718:718)) + (PORT datac (529:529:529) (546:546:546)) + (PORT datad (577:577:577) (584:584:584)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_\|db\[5\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (347:347:347) (379:379:379)) + (PORT datab (634:634:634) (653:653:653)) + (PORT datac (224:224:224) (279:279:279)) + (PORT datad (703:703:703) (733:733:733)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sw1_\|db_down\[5\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (669:669:669) (734:734:734)) + (PORT datab (1402:1402:1402) (1399:1399:1399)) + (PORT datac (954:954:954) (970:970:970)) + (PORT datad (840:840:840) (860:860:860)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_flags_\|SYNTHESIZED_WIRE_36) + (DELAY + (ABSOLUTE + (PORT dataa (864:864:864) (926:926:926)) + (PORT datab (665:665:665) (685:685:685)) + (PORT datac (1135:1135:1135) (1146:1146:1146)) + (PORT datad (599:599:599) (617:617:617)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|alu_flags_\|flags_yf) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1440:1440:1440) (1432:1432:1432)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[5\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (867:867:867) (885:885:885)) + (PORT datab (221:221:221) (267:267:267)) + (PORT datac (847:847:847) (882:882:882)) + (PORT datad (200:200:200) (226:226:226)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[5\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (205:205:205) (249:249:249)) + (PORT datab (601:601:601) (610:610:610)) + (PORT datac (1879:1879:1879) (1868:1868:1868)) + (PORT datad (383:383:383) (406:406:406)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|alu_control_\|db\[5\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (829:829:829) (849:849:849)) + (PORT datab (393:393:393) (429:429:429)) + (PORT datac (174:174:174) (208:208:208)) + (PORT datad (216:216:216) (251:251:251)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (749:749:749) (798:798:798)) + (PORT clk (1860:1860:1860) (1888:1888:1888)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3623:3623:3623) (3852:3852:3852)) + (PORT d[1] (1238:1238:1238) (1321:1321:1321)) + (PORT d[2] (1219:1219:1219) (1249:1249:1249)) + (PORT d[3] (3278:3278:3278) (3487:3487:3487)) + (PORT d[4] (3539:3539:3539) (3704:3704:3704)) + (PORT d[5] (4281:4281:4281) (4445:4445:4445)) + (PORT d[6] (1319:1319:1319) (1374:1374:1374)) + (PORT d[7] (2567:2567:2567) (2787:2787:2787)) + (PORT d[8] (3323:3323:3323) (3447:3447:3447)) + (PORT d[9] (1517:1517:1517) (1578:1578:1578)) + (PORT d[10] (4299:4299:4299) (4577:4577:4577)) + (PORT d[11] (3876:3876:3876) (4125:4125:4125)) + (PORT d[12] (1520:1520:1520) (1580:1580:1580)) + (PORT clk (1857:1857:1857) (1884:1884:1884)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1512:1512:1512) (1505:1505:1505)) + (PORT clk (1857:1857:1857) (1884:1884:1884)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1888:1888:1888)) + (PORT d[0] (2707:2707:2707) (2660:2660:2660)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1889:1889:1889)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1847:1847:1847)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1010:1010:1010)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1011:1011:1011)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1011:1011:1011)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a29.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1011:1011:1011)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1106:1106:1106) (1158:1158:1158)) + (PORT clk (1860:1860:1860) (1887:1887:1887)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2907:2907:2907) (3158:3158:3158)) + (PORT d[1] (980:980:980) (1020:1020:1020)) + (PORT d[2] (1229:1229:1229) (1296:1296:1296)) + (PORT d[3] (3293:3293:3293) (3527:3527:3527)) + (PORT d[4] (1036:1036:1036) (1093:1093:1093)) + (PORT d[5] (1454:1454:1454) (1511:1511:1511)) + (PORT d[6] (1303:1303:1303) (1332:1332:1332)) + (PORT d[7] (2564:2564:2564) (2814:2814:2814)) + (PORT d[8] (3570:3570:3570) (3717:3717:3717)) + (PORT d[9] (1493:1493:1493) (1571:1571:1571)) + (PORT d[10] (4286:4286:4286) (4579:4579:4579)) + (PORT d[11] (3883:3883:3883) (4119:4119:4119)) + (PORT d[12] (1501:1501:1501) (1562:1562:1562)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1837:1837:1837) (1761:1761:1761)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (PORT d[0] (2502:2502:2502) (2456:2456:2456)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1846:1846:1846)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (743:743:743) (785:785:785)) + (PORT clk (1860:1860:1860) (1887:1887:1887)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3640:3640:3640) (3867:3867:3867)) + (PORT d[1] (1263:1263:1263) (1344:1344:1344)) + (PORT d[2] (1555:1555:1555) (1618:1618:1618)) + (PORT d[3] (2985:2985:2985) (3180:3180:3180)) + (PORT d[4] (3522:3522:3522) (3690:3690:3690)) + (PORT d[5] (4009:4009:4009) (4176:4176:4176)) + (PORT d[6] (1585:1585:1585) (1639:1639:1639)) + (PORT d[7] (2268:2268:2268) (2493:2493:2493)) + (PORT d[8] (3312:3312:3312) (3456:3456:3456)) + (PORT d[9] (1780:1780:1780) (1860:1860:1860)) + (PORT d[10] (3993:3993:3993) (4259:4259:4259)) + (PORT d[11] (3579:3579:3579) (3788:3788:3788)) + (PORT d[12] (1755:1755:1755) (1839:1839:1839)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1528:1528:1528) (1500:1500:1500)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1887:1887:1887)) + (PORT d[0] (3101:3101:3101) (3070:3070:3070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1888:1888:1888)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1846:1846:1846)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a21.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (708:708:708) (730:730:730)) + (PORT clk (1857:1857:1857) (1884:1884:1884)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3320:3320:3320) (3529:3529:3529)) + (PORT d[1] (1925:1925:1925) (2035:2035:2035)) + (PORT d[2] (1583:1583:1583) (1671:1671:1671)) + (PORT d[3] (2976:2976:2976) (3185:3185:3185)) + (PORT d[4] (3240:3240:3240) (3388:3388:3388)) + (PORT d[5] (3971:3971:3971) (4117:4117:4117)) + (PORT d[6] (1878:1878:1878) (1973:1973:1973)) + (PORT d[7] (2258:2258:2258) (2473:2473:2473)) + (PORT d[8] (3006:3006:3006) (3103:3103:3103)) + (PORT d[9] (2107:2107:2107) (2217:2217:2217)) + (PORT d[10] (3706:3706:3706) (3953:3953:3953)) + (PORT d[11] (3262:3262:3262) (3467:3467:3467)) + (PORT d[12] (1721:1721:1721) (1829:1829:1829)) + (PORT clk (1854:1854:1854) (1880:1880:1880)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1774:1774:1774) (1779:1779:1779)) + (PORT clk (1854:1854:1854) (1880:1880:1880)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1884:1884:1884)) + (PORT d[0] (2663:2663:2663) (2678:2678:2678)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1817:1817:1817) (1843:1843:1843)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1002:1002:1002) (1006:1006:1006)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1003:1003:1003) (1007:1007:1007)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1003:1003:1003) (1007:1007:1007)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1003:1003:1003) (1007:1007:1007)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (873:873:873) (896:896:896)) + (PORT datab (1443:1443:1443) (1545:1545:1545)) + (PORT datac (837:837:837) (843:843:843)) + (PORT datad (1491:1491:1491) (1579:1579:1579)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1224:1224:1224) (1254:1254:1254)) + (PORT datab (1250:1250:1250) (1252:1252:1252)) + (PORT datac (1806:1806:1806) (1901:1901:1901)) + (PORT datad (312:312:312) (328:328:328)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2736:2736:2736) (2927:2927:2927)) + (PORT d[1] (2212:2212:2212) (2337:2337:2337)) + (PORT d[2] (2433:2433:2433) (2537:2537:2537)) + (PORT d[3] (2574:2574:2574) (2745:2745:2745)) + (PORT d[4] (2659:2659:2659) (2748:2748:2748)) + (PORT d[5] (2923:2923:2923) (3031:3031:3031)) + (PORT d[6] (2947:2947:2947) (3063:3063:3063)) + (PORT d[7] (1963:1963:1963) (2155:2155:2155)) + (PORT d[8] (2395:2395:2395) (2452:2452:2452)) + (PORT d[9] (3128:3128:3128) (3211:3211:3211)) + (PORT d[10] (4046:4046:4046) (4316:4316:4316)) + (PORT d[11] (3089:3089:3089) (3284:3284:3284)) + (PORT d[12] (2737:2737:2737) (2894:2894:2894)) + (PORT clk (1867:1867:1867) (1893:1893:1893)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1867:1867:1867) (1893:1893:1893)) + (PORT d[0] (2745:2745:2745) (2807:2807:2807)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1868:1868:1868) (1894:1894:1894)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1830:1830:1830) (1856:1856:1856)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1015:1015:1015) (1019:1019:1019)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1016:1016:1016) (1020:1020:1020)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1016:1016:1016) (1020:1020:1020)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1016:1016:1016) (1020:1020:1020)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1979:1979:1979) (2050:2050:2050)) + (PORT d[1] (1590:1590:1590) (1643:1643:1643)) + (PORT d[2] (2393:2393:2393) (2525:2525:2525)) + (PORT d[3] (2491:2491:2491) (2649:2649:2649)) + (PORT d[4] (1238:1238:1238) (1305:1305:1305)) + (PORT d[5] (1545:1545:1545) (1605:1605:1605)) + (PORT d[6] (2631:2631:2631) (2688:2688:2688)) + (PORT d[7] (1839:1839:1839) (1978:1978:1978)) + (PORT d[8] (1582:1582:1582) (1642:1642:1642)) + (PORT d[9] (3336:3336:3336) (3585:3585:3585)) + (PORT d[10] (1236:1236:1236) (1276:1276:1276)) + (PORT d[11] (1201:1201:1201) (1245:1245:1245)) + (PORT d[12] (1657:1657:1657) (1673:1673:1673)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1883:1883:1883)) + (PORT d[0] (2372:2372:2372) (2336:2336:2336)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1846:1846:1846)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1159:1159:1159) (1159:1159:1159)) + (PORT clk (1857:1857:1857) (1885:1885:1885)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3013:3013:3013) (3204:3204:3204)) + (PORT d[1] (3047:3047:3047) (3183:3183:3183)) + (PORT d[2] (1908:1908:1908) (1988:1988:1988)) + (PORT d[3] (2333:2333:2333) (2531:2531:2531)) + (PORT d[4] (2951:2951:2951) (3077:3077:3077)) + (PORT d[5] (3204:3204:3204) (3342:3342:3342)) + (PORT d[6] (2360:2360:2360) (2459:2459:2459)) + (PORT d[7] (2245:2245:2245) (2426:2426:2426)) + (PORT d[8] (2709:2709:2709) (2808:2808:2808)) + (PORT d[9] (2628:2628:2628) (2722:2722:2722)) + (PORT d[10] (3690:3690:3690) (3918:3918:3918)) + (PORT d[11] (3268:3268:3268) (3477:3477:3477)) + (PORT d[12] (2070:2070:2070) (2181:2181:2181)) + (PORT clk (1854:1854:1854) (1881:1881:1881)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3372:3372:3372) (3395:3395:3395)) + (PORT clk (1854:1854:1854) (1881:1881:1881)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1885:1885:1885)) + (PORT d[0] (3350:3350:3350) (3368:3368:3368)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1886:1886:1886)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1886:1886:1886)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1886:1886:1886)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1886:1886:1886)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1810:1810:1810)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2713:2713:2713) (2908:2908:2908)) + (PORT clk (1822:1822:1822) (1816:1816:1816)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4225:4225:4225) (4211:4211:4211)) + (PORT d[1] (4225:4225:4225) (4280:4280:4280)) + (PORT d[2] (4120:4120:4120) (4160:4160:4160)) + (PORT d[3] (4205:4205:4205) (4285:4285:4285)) + (PORT d[4] (4152:4152:4152) (4284:4284:4284)) + (PORT d[5] (4348:4348:4348) (4392:4392:4392)) + (PORT d[6] (4200:4200:4200) (4260:4260:4260)) + (PORT d[7] (4039:4039:4039) (4157:4157:4157)) + (PORT d[8] (4218:4218:4218) (4264:4264:4264)) + (PORT d[9] (4253:4253:4253) (4354:4354:4354)) + (PORT d[10] (4253:4253:4253) (4298:4298:4298)) + (PORT d[11] (4351:4351:4351) (4448:4448:4448)) + (PORT d[12] (4022:4022:4022) (4075:4075:4075)) + (PORT clk (1818:1818:1818) (1812:1812:1812)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1822:1822:1822) (1816:1816:1816)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1823:1823:1823) (1817:1817:1817)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1823:1823:1823) (1817:1817:1817)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1823:1823:1823) (1817:1817:1817)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1823:1823:1823) (1817:1817:1817)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1246:1246:1246) (1307:1307:1307)) + (PORT clk (1866:1866:1866) (1893:1893:1893)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2843:2843:2843) (3053:3053:3053)) + (PORT d[1] (2717:2717:2717) (2847:2847:2847)) + (PORT d[2] (2495:2495:2495) (2606:2606:2606)) + (PORT d[3] (2312:2312:2312) (2504:2504:2504)) + (PORT d[4] (2948:2948:2948) (3057:3057:3057)) + (PORT d[5] (2937:2937:2937) (3064:3064:3064)) + (PORT d[6] (2974:2974:2974) (3090:3090:3090)) + (PORT d[7] (1949:1949:1949) (2124:2124:2124)) + (PORT d[8] (2408:2408:2408) (2483:2483:2483)) + (PORT d[9] (2376:2376:2376) (2489:2489:2489)) + (PORT d[10] (3631:3631:3631) (3871:3871:3871)) + (PORT d[11] (3258:3258:3258) (3445:3445:3445)) + (PORT d[12] (2606:2606:2606) (2706:2706:2706)) + (PORT clk (1863:1863:1863) (1889:1889:1889)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2477:2477:2477) (2512:2512:2512)) + (PORT clk (1863:1863:1863) (1889:1889:1889)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1866:1866:1866) (1893:1893:1893)) + (PORT d[0] (3408:3408:3408) (3363:3363:3363)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1867:1867:1867) (1894:1894:1894)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1867:1867:1867) (1894:1894:1894)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1867:1867:1867) (1894:1894:1894)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1867:1867:1867) (1894:1894:1894)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1821:1821:1821) (1818:1818:1818)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2996:2996:2996) (3194:3194:3194)) + (PORT clk (1831:1831:1831) (1824:1824:1824)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4076:4076:4076) (4059:4059:4059)) + (PORT d[1] (4345:4345:4345) (4349:4349:4349)) + (PORT d[2] (4182:4182:4182) (4239:4239:4239)) + (PORT d[3] (4358:4358:4358) (4385:4385:4385)) + (PORT d[4] (4208:4208:4208) (4286:4286:4286)) + (PORT d[5] (4678:4678:4678) (4720:4720:4720)) + (PORT d[6] (4167:4167:4167) (4246:4246:4246)) + (PORT d[7] (4191:4191:4191) (4279:4279:4279)) + (PORT d[8] (4219:4219:4219) (4290:4290:4290)) + (PORT d[9] (4270:4270:4270) (4340:4340:4340)) + (PORT d[10] (4050:4050:4050) (4047:4047:4047)) + (PORT d[11] (4323:4323:4323) (4360:4360:4360)) + (PORT d[12] (4220:4220:4220) (4284:4284:4284)) + (PORT clk (1827:1827:1827) (1820:1820:1820)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1831:1831:1831) (1824:1824:1824)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1832:1832:1832) (1825:1825:1825)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1832:1832:1832) (1825:1825:1825)) + (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1832:1832:1832) (1825:1825:1825)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1832:1832:1832) (1825:1825:1825)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1823:1823:1823) (1820:1820:1820)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Mux2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1266:1266:1266) (1329:1329:1329)) + (PORT datab (2194:2194:2194) (2333:2333:2333)) + (PORT datac (906:906:906) (919:919:919)) + (PORT datad (1091:1091:1091) (1135:1135:1135)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Mux2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1698:1698:1698) (1835:1835:1835)) + (PORT datab (1402:1402:1402) (1435:1435:1435)) + (PORT datac (1386:1386:1386) (1465:1465:1465)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[5\]\~87) + (DELAY + (ABSOLUTE + (PORT dataa (2046:2046:2046) (2109:2109:2109)) + (PORT datab (199:199:199) (237:237:237)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (1259:1259:1259) (1359:1359:1359)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[5\]\~68) + (DELAY + (ABSOLUTE + (PORT dataa (1411:1411:1411) (1486:1486:1486)) + (PORT datab (1257:1257:1257) (1350:1350:1350)) + (PORT datac (170:170:170) (202:202:202)) + (PORT datad (1420:1420:1420) (1435:1435:1435)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[5\]\~77) + (DELAY + (ABSOLUTE + (PORT datac (192:192:192) (226:226:226)) + (PORT datad (1410:1410:1410) (1459:1459:1459)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[5\]) + (DELAY + (ABSOLUTE + (PORT dataa (1673:1673:1673) (1675:1675:1675)) + (PORT datab (380:380:380) (406:406:406)) + (PORT datac (1376:1376:1376) (1410:1410:1410)) + (PORT datad (675:675:675) (717:717:717)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1527:1527:1527) (1531:1531:1531)) + (PORT asdata (659:659:659) (676:676:676)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[5\]\~14) + (DELAY + (ABSOLUTE + (PORT datab (615:615:615) (648:648:648)) + (PORT datac (537:537:537) (559:559:559)) + (PORT datad (238:238:238) (306:306:306)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[5\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (722:722:722) (779:779:779)) + (PORT datab (654:654:654) (712:712:712)) + (PORT datac (612:612:612) (664:664:664)) + (PORT datad (1669:1669:1669) (1694:1694:1694)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT asdata (948:948:948) (981:981:981)) + (PORT clrn (1567:1567:1567) (1549:1549:1549)) + (PORT ena (1667:1667:1667) (1658:1658:1658)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~8) + (DELAY + (ABSOLUTE + (PORT dataa (2526:2526:2526) (2690:2690:2690)) + (PORT datab (952:952:952) (990:990:990)) + (PORT datac (1195:1195:1195) (1230:1230:1230)) + (PORT datad (907:907:907) (962:962:962)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1319:1319:1319) (1432:1432:1432)) + (PORT datab (1270:1270:1270) (1304:1304:1304)) + (PORT datac (936:936:936) (1009:1009:1009)) + (PORT datad (1321:1321:1321) (1424:1424:1424)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1782:1782:1782) (1824:1824:1824)) + (PORT datab (1204:1204:1204) (1229:1229:1229)) + (PORT datac (1706:1706:1706) (1772:1772:1772)) + (PORT datad (1238:1238:1238) (1293:1293:1293)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~6) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (1155:1155:1155) (1222:1222:1222)) + (PORT datac (191:191:191) (224:224:224)) + (PORT datad (1232:1232:1232) (1289:1289:1289)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_gp_sel_pla31pla33M4T1_3) + (DELAY + (ABSOLUTE + (PORT dataa (1181:1181:1181) (1249:1249:1249)) + (PORT datab (2049:2049:2049) (2175:2175:2175)) + (PORT datac (199:199:199) (236:236:236)) + (PORT datad (1656:1656:1656) (1764:1764:1764)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1516:1516:1516) (1555:1555:1555)) + (PORT datab (196:196:196) (235:235:235)) + (PORT datac (193:193:193) (227:227:227)) + (PORT datad (861:861:861) (876:876:876)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1765:1765:1765) (1812:1812:1812)) + (PORT datab (1649:1649:1649) (1786:1786:1786)) + (PORT datac (1241:1241:1241) (1272:1272:1272)) + (PORT datad (1117:1117:1117) (1148:1148:1148)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_we\~7) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (196:196:196) (234:234:234)) + (PORT datac (349:349:349) (373:373:373)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~66) + (DELAY + (ABSOLUTE + (PORT dataa (292:292:292) (389:389:389)) + (PORT datab (275:275:275) (361:361:361)) + (PORT datac (1338:1338:1338) (1403:1403:1403)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~80) + (DELAY + (ABSOLUTE + (PORT dataa (991:991:991) (1073:1073:1073)) + (PORT datab (686:686:686) (745:745:745)) + (PORT datac (1185:1185:1185) (1260:1260:1260)) + (PORT datad (1018:1018:1018) (1093:1093:1093)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~81) + (DELAY + (ABSOLUTE + (PORT dataa (204:204:204) (249:249:249)) + (PORT datac (264:264:264) (352:352:352)) + (PORT datad (962:962:962) (1026:1026:1026)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]\~82) + (DELAY + (ABSOLUTE + (PORT dataa (669:669:669) (704:704:704)) + (PORT datab (228:228:228) (269:269:269)) + (PORT datad (172:172:172) (198:198:198)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1555:1555:1555) (1547:1547:1547)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~84) + (DELAY + (ABSOLUTE + (PORT dataa (1483:1483:1483) (1544:1544:1544)) + (PORT datab (720:720:720) (777:777:777)) + (PORT datad (915:915:915) (979:979:979)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~83) + (DELAY + (ABSOLUTE + (PORT dataa (1014:1014:1014) (1115:1115:1115)) + (PORT datab (1848:1848:1848) (1906:1906:1906)) + (PORT datac (1448:1448:1448) (1501:1501:1501)) + (PORT datad (672:672:672) (725:725:725)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]\~85) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (247:247:247)) + (PORT datab (200:200:200) (240:240:240)) + (PORT datad (183:183:183) (213:213:213)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1533:1533:1533)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1559:1559:1559) (1552:1552:1552)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (606:606:606) (635:635:635)) + (PORT datab (671:671:671) (733:733:733)) + (PORT datac (748:748:748) (748:748:748)) + (PORT datad (217:217:217) (285:285:285)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]\~78) + (DELAY + (ABSOLUTE + (PORT dataa (755:755:755) (828:828:828)) + (PORT datab (950:950:950) (1074:1074:1074)) + (PORT datac (346:346:346) (368:368:368)) + (PORT datad (655:655:655) (738:738:738)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]\~79) + (DELAY + (ABSOLUTE + (PORT dataa (935:935:935) (1020:1020:1020)) + (PORT datad (348:348:348) (372:372:372)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1558:1558:1558) (1550:1550:1550)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]\~76) + (DELAY + (ABSOLUTE + (PORT dataa (935:935:935) (1023:1023:1023)) + (PORT datab (641:641:641) (657:657:657)) + (PORT datad (809:809:809) (821:821:821)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1558:1558:1558) (1550:1550:1550)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[0\]\~77) + (DELAY + (ABSOLUTE + (PORT dataa (935:935:935) (1025:1025:1025)) + (PORT datab (643:643:643) (729:729:729)) + (PORT datad (373:373:373) (399:399:399)) + (IOPATH dataa combout (301:301:301) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1558:1558:1558) (1550:1550:1550)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (244:244:244) (331:331:331)) + (PORT datab (1037:1037:1037) (1114:1114:1114)) + (PORT datac (1050:1050:1050) (1049:1049:1049)) + (PORT datad (217:217:217) (286:286:286)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1318:1318:1318) (1412:1412:1412)) + (PORT datab (424:424:424) (511:511:511)) + (PORT datac (962:962:962) (1039:1039:1039)) + (PORT datad (943:943:943) (1007:1007:1007)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\~71) + (DELAY + (ABSOLUTE + (PORT dataa (233:233:233) (282:282:282)) + (PORT datab (719:719:719) (787:787:787)) + (PORT datac (952:952:952) (1033:1033:1033)) + (PORT datad (609:609:609) (621:621:621)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (336:336:336) (342:342:342)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[3\]\~70) + (DELAY + (ABSOLUTE + (PORT dataa (1210:1210:1210) (1301:1301:1301)) + (PORT datad (990:990:990) (1066:1066:1066)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~72) + (DELAY + (ABSOLUTE + (PORT dataa (301:301:301) (394:394:394)) + (PORT datab (668:668:668) (685:685:685)) + (PORT datac (563:563:563) (590:590:590)) + (PORT datad (608:608:608) (620:620:620)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (705:705:705) (807:807:807)) + (PORT datab (415:415:415) (494:494:494)) + (PORT datac (678:678:678) (748:748:748)) + (PORT datad (2180:2180:2180) (2284:2284:2284)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\~73) + (DELAY + (ABSOLUTE + (PORT dataa (303:303:303) (398:398:398)) + (PORT datab (222:222:222) (261:261:261)) + (PORT datac (931:931:931) (998:998:998)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]\~74) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (246:246:246)) + (PORT datab (199:199:199) (239:239:239)) + (PORT datad (433:433:433) (509:509:509)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1534:1534:1534)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1555:1555:1555) (1548:1548:1548)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\~2) + (DELAY + (ABSOLUTE + (PORT datab (707:707:707) (761:761:761)) + (PORT datac (2400:2400:2400) (2577:2577:2577)) + (PORT datad (1458:1458:1458) (1517:1517:1517)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~41) + (DELAY + (ABSOLUTE + (PORT dataa (243:243:243) (330:330:330)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (1087:1087:1087) (1090:1090:1090)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~89) + (DELAY + (ABSOLUTE + (PORT dataa (663:663:663) (751:751:751)) + (PORT datab (1009:1009:1009) (1098:1098:1098)) + (PORT datac (711:711:711) (784:784:784)) + (PORT datad (906:906:906) (1032:1032:1032)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~90) + (DELAY + (ABSOLUTE + (PORT dataa (1583:1583:1583) (1677:1677:1677)) + (PORT datab (199:199:199) (239:239:239)) + (PORT datac (850:850:850) (868:868:868)) + (PORT datad (818:818:818) (889:889:889)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]\~91) + (DELAY + (ABSOLUTE + (PORT datab (1037:1037:1037) (1058:1058:1058)) + (PORT datad (924:924:924) (982:982:982)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1533:1533:1533)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1559:1559:1559) (1551:1551:1551)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~131) + (DELAY + (ABSOLUTE + (PORT dataa (666:666:666) (735:735:735)) + (PORT datab (827:827:827) (847:847:847)) + (PORT datad (439:439:439) (517:517:517)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|WideOr16\~3) + (DELAY + (ABSOLUTE + (PORT datac (952:952:952) (1022:1022:1022)) + (PORT datad (969:969:969) (1052:1052:1052)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~86) + (DELAY + (ABSOLUTE + (PORT dataa (936:936:936) (1029:1029:1029)) + (PORT datab (239:239:239) (284:284:284)) + (PORT datac (173:173:173) (207:207:207)) + (PORT datad (654:654:654) (737:737:737)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~87) + (DELAY + (ABSOLUTE + (PORT dataa (843:843:843) (929:929:929)) + (PORT datab (825:825:825) (879:879:879)) + (PORT datac (347:347:347) (381:381:381)) + (PORT datad (911:911:911) (1030:1030:1030)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]\~88) + (DELAY + (ABSOLUTE + (PORT dataa (893:893:893) (911:911:911)) + (PORT datad (925:925:925) (982:982:982)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1533:1533:1533)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1559:1559:1559) (1551:1551:1551)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~43) + (DELAY + (ABSOLUTE + (PORT dataa (1384:1384:1384) (1510:1510:1510)) + (PORT datab (242:242:242) (324:324:324)) + (PORT datac (214:214:214) (290:290:290)) + (PORT datad (601:601:601) (621:621:621)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~44) + (DELAY + (ABSOLUTE + (PORT dataa (333:333:333) (369:369:369)) + (PORT datab (826:826:826) (844:844:844)) + (PORT datac (2857:2857:2857) (3133:3133:3133)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (964:964:964) (1010:1010:1010)) + (PORT clk (1852:1852:1852) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1763:1763:1763) (1827:1827:1827)) + (PORT d[1] (4509:4509:4509) (4694:4694:4694)) + (PORT d[2] (2644:2644:2644) (2832:2832:2832)) + (PORT d[3] (2892:2892:2892) (3019:3019:3019)) + (PORT d[4] (4184:4184:4184) (4338:4338:4338)) + (PORT d[5] (2041:2041:2041) (2118:2118:2118)) + (PORT d[6] (1910:1910:1910) (1958:1958:1958)) + (PORT d[7] (2150:2150:2150) (2311:2311:2311)) + (PORT d[8] (2790:2790:2790) (2934:2934:2934)) + (PORT d[9] (2801:2801:2801) (3009:3009:3009)) + (PORT d[10] (2500:2500:2500) (2657:2657:2657)) + (PORT d[11] (2674:2674:2674) (2772:2772:2772)) + (PORT d[12] (3653:3653:3653) (3814:3814:3814)) + (PORT clk (1849:1849:1849) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1741:1741:1741) (1730:1730:1730)) + (PORT clk (1849:1849:1849) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1879:1879:1879)) + (PORT d[0] (2286:2286:2286) (2237:2237:2237)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a24.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (988:988:988) (1037:1037:1037)) + (PORT clk (1852:1852:1852) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3402:3402:3402) (3662:3662:3662)) + (PORT d[1] (4509:4509:4509) (4693:4693:4693)) + (PORT d[2] (2666:2666:2666) (2856:2856:2856)) + (PORT d[3] (2504:2504:2504) (2645:2645:2645)) + (PORT d[4] (4145:4145:4145) (4301:4301:4301)) + (PORT d[5] (2075:2075:2075) (2166:2166:2166)) + (PORT d[6] (3311:3311:3311) (3443:3443:3443)) + (PORT d[7] (3625:3625:3625) (3776:3776:3776)) + (PORT d[8] (3159:3159:3159) (3368:3368:3368)) + (PORT d[9] (2487:2487:2487) (2679:2679:2679)) + (PORT d[10] (2231:2231:2231) (2388:2388:2388)) + (PORT d[11] (2673:2673:2673) (2771:2771:2771)) + (PORT d[12] (3369:3369:3369) (3533:3533:3533)) + (PORT clk (1849:1849:1849) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1803:1803:1803) (1749:1749:1749)) + (PORT clk (1849:1849:1849) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1879:1879:1879)) + (PORT d[0] (2590:2590:2590) (2602:2602:2602)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a16.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (709:709:709) (734:734:734)) + (PORT clk (1851:1851:1851) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1467:1467:1467) (1536:1536:1536)) + (PORT d[1] (2275:2275:2275) (2353:2353:2353)) + (PORT d[2] (1890:1890:1890) (2010:2010:2010)) + (PORT d[3] (1588:1588:1588) (1687:1687:1687)) + (PORT d[4] (4135:4135:4135) (4312:4312:4312)) + (PORT d[5] (1695:1695:1695) (1762:1762:1762)) + (PORT d[6] (1890:1890:1890) (1938:1938:1938)) + (PORT d[7] (2144:2144:2144) (2301:2301:2301)) + (PORT d[8] (2776:2776:2776) (2940:2940:2940)) + (PORT d[9] (2811:2811:2811) (3005:3005:3005)) + (PORT d[10] (2514:2514:2514) (2694:2694:2694)) + (PORT d[11] (2275:2275:2275) (2383:2383:2383)) + (PORT d[12] (3669:3669:3669) (3854:3854:3854)) + (PORT clk (1848:1848:1848) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1458:1458:1458) (1401:1401:1401)) + (PORT clk (1848:1848:1848) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (PORT d[0] (2246:2246:2246) (2210:2210:2210)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1811:1811:1811) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1029:1029:1029) (1058:1058:1058)) + (PORT clk (1851:1851:1851) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3424:3424:3424) (3686:3686:3686)) + (PORT d[1] (4505:4505:4505) (4687:4687:4687)) + (PORT d[2] (2639:2639:2639) (2822:2822:2822)) + (PORT d[3] (2565:2565:2565) (2693:2693:2693)) + (PORT d[4] (3831:3831:3831) (3986:3986:3986)) + (PORT d[5] (2081:2081:2081) (2177:2177:2177)) + (PORT d[6] (3281:3281:3281) (3405:3405:3405)) + (PORT d[7] (3357:3357:3357) (3510:3510:3510)) + (PORT d[8] (3424:3424:3424) (3624:3624:3624)) + (PORT d[9] (2513:2513:2513) (2710:2710:2710)) + (PORT d[10] (2210:2210:2210) (2369:2369:2369)) + (PORT d[11] (2667:2667:2667) (2785:2785:2785)) + (PORT d[12] (3368:3368:3368) (3532:3532:3532)) + (PORT clk (1848:1848:1848) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2007:2007:2007) (2007:2007:2007)) + (PORT clk (1848:1848:1848) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1879:1879:1879)) + (PORT d[0] (2533:2533:2533) (2546:2546:2546)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1811:1811:1811) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (952:952:952) (987:987:987)) + (PORT datab (1269:1269:1269) (1337:1337:1337)) + (PORT datac (1528:1528:1528) (1593:1593:1593)) + (PORT datad (1358:1358:1358) (1381:1381:1381)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (325:325:325)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1159:1159:1159) (1196:1196:1196)) + (PORT datab (1184:1184:1184) (1203:1203:1203)) + (PORT datac (1816:1816:1816) (1835:1835:1835)) + (PORT datad (173:173:173) (197:197:197)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2932:2932:2932) (3182:3182:3182)) + (PORT d[1] (978:978:978) (1027:1027:1027)) + (PORT d[2] (2932:2932:2932) (3179:3179:3179)) + (PORT d[3] (989:989:989) (1021:1021:1021)) + (PORT d[4] (979:979:979) (1010:1010:1010)) + (PORT d[5] (1202:1202:1202) (1237:1237:1237)) + (PORT d[6] (998:998:998) (1020:1020:1020)) + (PORT d[7] (2853:2853:2853) (3100:3100:3100)) + (PORT d[8] (3580:3580:3580) (3745:3745:3745)) + (PORT d[9] (1168:1168:1168) (1216:1216:1216)) + (PORT d[10] (4587:4587:4587) (4885:4885:4885)) + (PORT d[11] (1487:1487:1487) (1529:1529:1529)) + (PORT d[12] (2563:2563:2563) (2646:2646:2646)) + (PORT clk (1856:1856:1856) (1882:1882:1882)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1882:1882:1882)) + (PORT d[0] (1247:1247:1247) (1229:1229:1229)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1883:1883:1883)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1819:1819:1819) (1845:1845:1845)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1008:1008:1008)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1566:1566:1566) (1637:1637:1637)) + (PORT clk (1857:1857:1857) (1885:1885:1885)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2776:2776:2776) (2894:2894:2894)) + (PORT d[1] (3418:3418:3418) (3548:3548:3548)) + (PORT d[2] (2596:2596:2596) (2777:2777:2777)) + (PORT d[3] (2111:2111:2111) (2240:2240:2240)) + (PORT d[4] (2684:2684:2684) (2812:2812:2812)) + (PORT d[5] (2721:2721:2721) (2841:2841:2841)) + (PORT d[6] (2973:2973:2973) (3076:3076:3076)) + (PORT d[7] (2385:2385:2385) (2526:2526:2526)) + (PORT d[8] (2615:2615:2615) (2708:2708:2708)) + (PORT d[9] (2730:2730:2730) (2932:2932:2932)) + (PORT d[10] (3110:3110:3110) (3367:3367:3367)) + (PORT d[11] (2295:2295:2295) (2406:2406:2406)) + (PORT d[12] (2998:2998:2998) (3173:3173:3173)) + (PORT clk (1854:1854:1854) (1881:1881:1881)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2828:2828:2828) (2920:2920:2920)) + (PORT clk (1854:1854:1854) (1881:1881:1881)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1885:1885:1885)) + (PORT d[0] (4970:4970:4970) (4881:4881:4881)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1886:1886:1886)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1886:1886:1886)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1886:1886:1886)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1886:1886:1886)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1810:1810:1810)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1001:1001:1001) (1042:1042:1042)) + (PORT clk (1822:1822:1822) (1816:1816:1816)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4142:4142:4142) (4153:4153:4153)) + (PORT d[1] (4301:4301:4301) (4373:4373:4373)) + (PORT d[2] (4153:4153:4153) (4257:4257:4257)) + (PORT d[3] (4216:4216:4216) (4298:4298:4298)) + (PORT d[4] (4121:4121:4121) (4247:4247:4247)) + (PORT d[5] (4316:4316:4316) (4337:4337:4337)) + (PORT d[6] (4117:4117:4117) (4156:4156:4156)) + (PORT d[7] (4126:4126:4126) (4250:4250:4250)) + (PORT d[8] (4272:4272:4272) (4391:4391:4391)) + (PORT d[9] (4091:4091:4091) (4177:4177:4177)) + (PORT d[10] (4258:4258:4258) (4258:4258:4258)) + (PORT d[11] (4239:4239:4239) (4250:4250:4250)) + (PORT d[12] (4162:4162:4162) (4229:4229:4229)) + (PORT clk (1818:1818:1818) (1812:1812:1812)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1822:1822:1822) (1816:1816:1816)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1823:1823:1823) (1817:1817:1817)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1823:1823:1823) (1817:1817:1817)) + (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1823:1823:1823) (1817:1817:1817)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1823:1823:1823) (1817:1817:1817)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1814:1814:1814) (1812:1812:1812)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1323:1323:1323) (1362:1362:1362)) + (PORT clk (1849:1849:1849) (1877:1877:1877)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3073:3073:3073) (3330:3330:3330)) + (PORT d[1] (4002:4002:4002) (4175:4175:4175)) + (PORT d[2] (2366:2366:2366) (2533:2533:2533)) + (PORT d[3] (2529:2529:2529) (2671:2671:2671)) + (PORT d[4] (4109:4109:4109) (4267:4267:4267)) + (PORT d[5] (2341:2341:2341) (2437:2437:2437)) + (PORT d[6] (3267:3267:3267) (3370:3370:3370)) + (PORT d[7] (3313:3313:3313) (3506:3506:3506)) + (PORT d[8] (2482:2482:2482) (2602:2602:2602)) + (PORT d[9] (2471:2471:2471) (2641:2641:2641)) + (PORT d[10] (2662:2662:2662) (2853:2853:2853)) + (PORT d[11] (2354:2354:2354) (2453:2453:2453)) + (PORT d[12] (3328:3328:3328) (3468:3468:3468)) + (PORT clk (1846:1846:1846) (1873:1873:1873)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2014:2014:2014) (1999:1999:1999)) + (PORT clk (1846:1846:1846) (1873:1873:1873)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1877:1877:1877)) + (PORT d[0] (5474:5474:5474) (5597:5597:5597)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1878:1878:1878)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1878:1878:1878)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1878:1878:1878)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1878:1878:1878)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1804:1804:1804) (1802:1802:1802)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2078:2078:2078) (2283:2283:2283)) + (PORT clk (1814:1814:1814) (1808:1808:1808)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4231:4231:4231) (4308:4308:4308)) + (PORT d[1] (4283:4283:4283) (4355:4355:4355)) + (PORT d[2] (4152:4152:4152) (4236:4236:4236)) + (PORT d[3] (4261:4261:4261) (4359:4359:4359)) + (PORT d[4] (4181:4181:4181) (4391:4391:4391)) + (PORT d[5] (4386:4386:4386) (4502:4502:4502)) + (PORT d[6] (4109:4109:4109) (4199:4199:4199)) + (PORT d[7] (4092:4092:4092) (4207:4207:4207)) + (PORT d[8] (4340:4340:4340) (4366:4366:4366)) + (PORT d[9] (4147:4147:4147) (4246:4246:4246)) + (PORT d[10] (4225:4225:4225) (4278:4278:4278)) + (PORT d[11] (4357:4357:4357) (4437:4437:4437)) + (PORT d[12] (4225:4225:4225) (4293:4293:4293)) + (PORT clk (1810:1810:1810) (1804:1804:1804)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1814:1814:1814) (1808:1808:1808)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1815:1815:1815) (1809:1809:1809)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1815:1815:1815) (1809:1809:1809)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1815:1815:1815) (1809:1809:1809)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1815:1815:1815) (1809:1809:1809)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1194:1194:1194) (1267:1267:1267)) + (PORT datab (678:678:678) (723:723:723)) + (PORT datac (1729:1729:1729) (1757:1757:1757)) + (PORT datad (1180:1180:1180) (1211:1211:1211)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2556:2556:2556) (2680:2680:2680)) + (PORT d[1] (3408:3408:3408) (3502:3502:3502)) + (PORT d[2] (2280:2280:2280) (2429:2429:2429)) + (PORT d[3] (2427:2427:2427) (2540:2540:2540)) + (PORT d[4] (2671:2671:2671) (2782:2782:2782)) + (PORT d[5] (2678:2678:2678) (2797:2797:2797)) + (PORT d[6] (3247:3247:3247) (3365:3365:3365)) + (PORT d[7] (2124:2124:2124) (2236:2236:2236)) + (PORT d[8] (2618:2618:2618) (2716:2716:2716)) + (PORT d[9] (3014:3014:3014) (3218:3218:3218)) + (PORT d[10] (3514:3514:3514) (3791:3791:3791)) + (PORT d[11] (2608:2608:2608) (2736:2736:2736)) + (PORT d[12] (2711:2711:2711) (2865:2865:2865)) + (PORT clk (1859:1859:1859) (1884:1884:1884)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1884:1884:1884)) + (PORT d[0] (4003:4003:4003) (3938:3938:3938)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1822:1822:1822) (1847:1847:1847)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1007:1007:1007) (1010:1010:1010)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1008:1008:1008) (1011:1011:1011)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1008:1008:1008) (1011:1011:1011)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1008:1008:1008) (1011:1011:1011)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1411:1411:1411) (1433:1433:1433)) + (PORT datab (1763:1763:1763) (1798:1798:1798)) + (PORT datac (173:173:173) (207:207:207)) + (PORT datad (1747:1747:1747) (1800:1800:1800)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (325:325:325)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~83) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (246:246:246)) + (PORT datab (3099:3099:3099) (3313:3313:3313)) + (PORT datac (1845:1845:1845) (2016:2016:2016)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~45) + (DELAY + (ABSOLUTE + (PORT dataa (1165:1165:1165) (1228:1228:1228)) + (PORT datab (1042:1042:1042) (1085:1085:1085)) + (PORT datac (179:179:179) (216:216:216)) + (PORT datad (1618:1618:1618) (1648:1648:1648)) + (IOPATH dataa combout (301:301:301) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[0\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (1666:1666:1666) (1706:1706:1706)) + (PORT datab (1658:1658:1658) (1692:1692:1692)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (1753:1753:1753) (1834:1834:1834)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[0\]) + (DELAY + (ABSOLUTE + (PORT dataa (1426:1426:1426) (1476:1476:1476)) + (PORT datab (2669:2669:2669) (2808:2808:2808)) + (PORT datac (339:339:339) (362:362:362)) + (PORT datad (371:371:371) (396:396:396)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1527:1527:1527) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[0\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (601:601:601) (664:664:664)) + (PORT datab (361:361:361) (398:398:398)) + (PORT datac (337:337:337) (369:369:369)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[0\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1418:1418:1418) (1451:1451:1451)) + (PORT datab (650:650:650) (674:674:674)) + (PORT datac (193:193:193) (226:226:226)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1566:1566:1566) (1548:1548:1548)) + (PORT ena (1698:1698:1698) (1714:1714:1714)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal3\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1711:1711:1711) (1845:1845:1845)) + (PORT datab (1089:1089:1089) (1155:1155:1155)) + (PORT datac (630:630:630) (652:652:652)) + (PORT datad (1105:1105:1105) (1133:1133:1133)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal43\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1304:1304:1304) (1384:1384:1384)) + (PORT datab (893:893:893) (927:927:927)) + (PORT datac (748:748:748) (850:850:850)) + (PORT datad (1074:1074:1074) (1094:1094:1094)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|test1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (826:826:826) (849:849:849)) + (PORT datab (197:197:197) (234:234:234)) + (PORT datac (184:184:184) (226:226:226)) + (PORT datad (195:195:195) (220:220:220)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|interrupts_\|test1\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1107:1107:1107) (1206:1206:1206)) + (PORT datab (1070:1070:1070) (1116:1116:1116)) + (PORT datac (631:631:631) (696:696:696)) + (PORT datad (904:904:904) (922:922:922)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|interrupts_\|in_nmi_ALTERA_SYNTHESIZED) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1566:1566:1566) (1548:1548:1548)) + (PORT ena (959:959:959) (957:957:957)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|clk_delay_\|SYNTHESIZED_WIRE_4) + (DELAY + (ABSOLUTE + (PORT dataa (634:634:634) (704:704:704)) + (PORT datab (1457:1457:1457) (1571:1571:1571)) + (PORT datac (1217:1217:1217) (1298:1298:1298)) + (PORT datad (856:856:856) (904:904:904)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|clk_delay_\|SYNTHESIZED_WIRE_7) + (DELAY + (ABSOLUTE + (PORT clk (1524:1524:1524) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1567:1567:1567) (1548:1548:1548)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|clk_delay_\|hold_clk_iorq) + (DELAY + (ABSOLUTE + (PORT dataa (1127:1127:1127) (1169:1169:1169)) + (PORT datab (1278:1278:1278) (1345:1345:1345)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_T4_ff) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1558:1558:1558) (1539:1539:1539)) + (PORT ena (1441:1441:1441) (1437:1437:1437)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_eval_cond\~0) + (DELAY + (ABSOLUTE + (PORT datac (1091:1091:1091) (1195:1195:1195)) + (PORT datad (1389:1389:1389) (1444:1444:1444)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~27) + (DELAY + (ABSOLUTE + (PORT dataa (1012:1012:1012) (1076:1076:1076)) + (PORT datab (1181:1181:1181) (1206:1206:1206)) + (PORT datac (627:627:627) (672:672:672)) + (PORT datad (623:623:623) (643:643:643)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~26) + (DELAY + (ABSOLUTE + (PORT datab (1127:1127:1127) (1212:1212:1212)) + (PORT datac (1880:1880:1880) (1963:1963:1963)) + (PORT datad (1816:1816:1816) (1920:1920:1920)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_mRead\~28) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (244:244:244)) + (PORT datab (199:199:199) (237:237:237)) + (PORT datac (193:193:193) (225:225:225)) + (PORT datad (1435:1435:1435) (1502:1502:1502)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~6) + (DELAY + (ABSOLUTE + (PORT dataa (961:961:961) (1014:1014:1014)) + (PORT datab (678:678:678) (699:699:699)) + (PORT datac (202:202:202) (241:241:241)) + (PORT datad (1258:1258:1258) (1313:1313:1313)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~7) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (245:245:245)) + (PORT datab (924:924:924) (983:983:983)) + (PORT datac (1118:1118:1118) (1186:1186:1186)) + (PORT datad (1371:1371:1371) (1416:1416:1416)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~8) + (DELAY + (ABSOLUTE + (PORT dataa (871:871:871) (908:908:908)) + (PORT datab (1079:1079:1079) (1141:1141:1141)) + (PORT datac (914:914:914) (982:982:982)) + (PORT datad (671:671:671) (720:720:720)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~9) + (DELAY + (ABSOLUTE + (PORT dataa (918:918:918) (984:984:984)) + (PORT datab (1455:1455:1455) (1518:1518:1518)) + (PORT datac (1102:1102:1102) (1173:1173:1173)) + (PORT datad (874:874:874) (902:902:902)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~10) + (DELAY + (ABSOLUTE + (PORT dataa (646:646:646) (665:665:665)) + (PORT datab (1335:1335:1335) (1344:1344:1344)) + (PORT datac (589:589:589) (607:607:607)) + (PORT datad (2396:2396:2396) (2468:2468:2468)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~12) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (246:246:246)) + (PORT datab (207:207:207) (250:250:250)) + (PORT datac (542:542:542) (559:559:559)) + (PORT datad (648:648:648) (691:691:691)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~15) + (DELAY + (ABSOLUTE + (PORT dataa (661:661:661) (680:680:680)) + (PORT datab (1937:1937:1937) (2057:2057:2057)) + (PORT datac (1464:1464:1464) (1549:1549:1549)) + (PORT datad (341:341:341) (369:369:369)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~13) + (DELAY + (ABSOLUTE + (PORT dataa (375:375:375) (399:399:399)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~41) + (DELAY + (ABSOLUTE + (PORT datab (218:218:218) (256:256:256)) + (PORT datac (1086:1086:1086) (1106:1106:1106)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1308:1308:1308) (1393:1393:1393)) + (PORT datab (1212:1212:1212) (1329:1329:1329)) + (PORT datac (808:808:808) (824:824:824)) + (PORT datad (765:765:765) (807:807:807)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|nextM\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1233:1233:1233) (1321:1321:1321)) + (PORT datab (953:953:953) (1004:1004:1004)) + (PORT datac (834:834:834) (857:857:857)) + (PORT datad (588:588:588) (600:600:600)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|ena_M) + (DELAY + (ABSOLUTE + (PORT datab (1159:1159:1159) (1227:1227:1227)) + (PORT datad (894:894:894) (970:970:970)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_T1_ff) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1558:1558:1558) (1539:1539:1539)) + (PORT ena (1441:1441:1441) (1437:1437:1437)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_13) + (DELAY + (ABSOLUTE + (PORT datab (273:273:273) (358:358:358)) + (PORT datac (1558:1558:1558) (1647:1647:1647)) + (PORT datad (895:895:895) (976:976:976)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_T2_ff) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1558:1558:1558) (1539:1539:1539)) + (PORT ena (1441:1441:1441) (1437:1437:1437)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_14) + (DELAY + (ABSOLUTE + (PORT datab (274:274:274) (360:360:360)) + (PORT datac (1559:1559:1559) (1647:1647:1647)) + (PORT datad (896:896:896) (976:976:976)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_T3_ff) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1558:1558:1558) (1539:1539:1539)) + (PORT ena (1441:1441:1441) (1437:1437:1437)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_reg_sys_hilo_1M1T3_3) + (DELAY + (ABSOLUTE + (PORT datac (1216:1216:1216) (1297:1297:1297)) + (PORT datad (1623:1623:1623) (1694:1694:1694)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_66_oe\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1427:1427:1427) (1437:1437:1437)) + (PORT datab (664:664:664) (695:695:695)) + (PORT datac (1306:1306:1306) (1375:1375:1375)) + (PORT datad (1666:1666:1666) (1801:1801:1801)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|interrupts_\|im1) + (DELAY + (ABSOLUTE + (PORT clk (1541:1541:1541) (1557:1557:1557)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1567:1567:1567) (1549:1549:1549)) + (PORT ena (1482:1482:1482) (1498:1498:1498)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_ff_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (295:295:295) (389:389:389)) + (PORT datab (882:882:882) (979:979:979)) + (PORT datac (826:826:826) (910:910:910)) + (PORT datad (1121:1121:1121) (1163:1163:1163)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_ff_oe\~1) + (DELAY + (ABSOLUTE + (PORT dataa (648:648:648) (695:695:695)) + (PORT datab (1160:1160:1160) (1205:1205:1205)) + (PORT datac (463:463:463) (541:541:541)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_zero_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1557:1557:1557) (1574:1574:1574)) + (PORT datab (1249:1249:1249) (1315:1315:1315)) + (PORT datac (1415:1415:1415) (1497:1497:1497)) + (PORT datad (905:905:905) (896:896:896)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (256:256:256)) + (PORT datab (205:205:205) (248:248:248)) + (PORT datac (1372:1372:1372) (1416:1416:1416)) + (PORT datad (698:698:698) (786:786:786)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[6\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (558:558:558) (586:586:586)) + (PORT datac (1329:1329:1329) (1349:1349:1349)) + (PORT datad (593:593:593) (603:603:603)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (945:945:945) (970:970:970)) + (PORT clk (1843:1843:1843) (1871:1871:1871)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1480:1480:1480) (1540:1540:1540)) + (PORT d[1] (1855:1855:1855) (1932:1932:1932)) + (PORT d[2] (2198:2198:2198) (2365:2365:2365)) + (PORT d[3] (1860:1860:1860) (1959:1959:1959)) + (PORT d[4] (2303:2303:2303) (2359:2359:2359)) + (PORT d[5] (1442:1442:1442) (1514:1514:1514)) + (PORT d[6] (1422:1422:1422) (1484:1484:1484)) + (PORT d[7] (1524:1524:1524) (1633:1633:1633)) + (PORT d[8] (2464:2464:2464) (2618:2618:2618)) + (PORT d[9] (3448:3448:3448) (3679:3679:3679)) + (PORT d[10] (1283:1283:1283) (1336:1336:1336)) + (PORT d[11] (1663:1663:1663) (1697:1697:1697)) + (PORT d[12] (2373:2373:2373) (2438:2438:2438)) + (PORT clk (1840:1840:1840) (1867:1867:1867)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1496:1496:1496) (1448:1448:1448)) + (PORT clk (1840:1840:1840) (1867:1867:1867)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1871:1871:1871)) + (PORT d[0] (1761:1761:1761) (1748:1748:1748)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1872:1872:1872)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1872:1872:1872)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1872:1872:1872)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1872:1872:1872)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1803:1803:1803) (1830:1830:1830)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (988:988:988) (993:993:993)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (989:989:989) (994:994:994)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (989:989:989) (994:994:994)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a22.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (989:989:989) (994:994:994)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1028:1028:1028) (1050:1050:1050)) + (PORT clk (1841:1841:1841) (1869:1869:1869)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1207:1207:1207) (1267:1267:1267)) + (PORT d[1] (1839:1839:1839) (1930:1930:1930)) + (PORT d[2] (1987:1987:1987) (2149:2149:2149)) + (PORT d[3] (1847:1847:1847) (1958:1958:1958)) + (PORT d[4] (2349:2349:2349) (2423:2423:2423)) + (PORT d[5] (1411:1411:1411) (1468:1468:1468)) + (PORT d[6] (1418:1418:1418) (1478:1478:1478)) + (PORT d[7] (1552:1552:1552) (1669:1669:1669)) + (PORT d[8] (2535:2535:2535) (2674:2674:2674)) + (PORT d[9] (3468:3468:3468) (3682:3682:3682)) + (PORT d[10] (1582:1582:1582) (1673:1673:1673)) + (PORT d[11] (1374:1374:1374) (1405:1405:1405)) + (PORT d[12] (2405:2405:2405) (2480:2480:2480)) + (PORT clk (1838:1838:1838) (1865:1865:1865)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1442:1442:1442) (1439:1439:1439)) + (PORT clk (1838:1838:1838) (1865:1865:1865)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1869:1869:1869)) + (PORT d[0] (1771:1771:1771) (1732:1732:1732)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1870:1870:1870)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1870:1870:1870)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1870:1870:1870)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1870:1870:1870)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1801:1801:1801) (1828:1828:1828)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (986:986:986) (991:991:991)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (987:987:987) (992:992:992)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (987:987:987) (992:992:992)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a30.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (987:987:987) (992:992:992)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (936:936:936) (957:957:957)) + (PORT clk (1847:1847:1847) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1190:1190:1190) (1232:1232:1232)) + (PORT d[1] (1836:1836:1836) (1942:1942:1942)) + (PORT d[2] (3210:3210:3210) (3443:3443:3443)) + (PORT d[3] (1559:1559:1559) (1636:1636:1636)) + (PORT d[4] (1981:1981:1981) (2055:2055:2055)) + (PORT d[5] (1388:1388:1388) (1453:1453:1453)) + (PORT d[6] (1715:1715:1715) (1779:1779:1779)) + (PORT d[7] (1251:1251:1251) (1325:1325:1325)) + (PORT d[8] (2576:2576:2576) (2738:2738:2738)) + (PORT d[9] (3161:3161:3161) (3375:3375:3375)) + (PORT d[10] (1305:1305:1305) (1378:1378:1378)) + (PORT d[11] (1689:1689:1689) (1717:1717:1717)) + (PORT d[12] (2675:2675:2675) (2763:2763:2763)) + (PORT clk (1844:1844:1844) (1871:1871:1871)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2082:2082:2082) (2053:2053:2053)) + (PORT clk (1844:1844:1844) (1871:1871:1871)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1847:1847:1847) (1875:1875:1875)) + (PORT d[0] (1957:1957:1957) (1912:1912:1912)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1807:1807:1807) (1834:1834:1834)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (992:992:992) (997:997:997)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (993:993:993) (998:998:998)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (993:993:993) (998:998:998)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (993:993:993) (998:998:998)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (702:702:702) (726:726:726)) + (PORT clk (1845:1845:1845) (1873:1873:1873)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1179:1179:1179) (1220:1220:1220)) + (PORT d[1] (2152:2152:2152) (2255:2255:2255)) + (PORT d[2] (2004:2004:2004) (2150:2150:2150)) + (PORT d[3] (1895:1895:1895) (2014:2014:2014)) + (PORT d[4] (1748:1748:1748) (1828:1828:1828)) + (PORT d[5] (1380:1380:1380) (1431:1431:1431)) + (PORT d[6] (1141:1141:1141) (1173:1173:1173)) + (PORT d[7] (1238:1238:1238) (1309:1309:1309)) + (PORT d[8] (2575:2575:2575) (2737:2737:2737)) + (PORT d[9] (3135:3135:3135) (3345:3345:3345)) + (PORT d[10] (1292:1292:1292) (1363:1363:1363)) + (PORT d[11] (1657:1657:1657) (1703:1703:1703)) + (PORT d[12] (1147:1147:1147) (1187:1187:1187)) + (PORT clk (1842:1842:1842) (1869:1869:1869)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2557:2557:2557) (2590:2590:2590)) + (PORT clk (1842:1842:1842) (1869:1869:1869)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1873:1873:1873)) + (PORT d[0] (1461:1461:1461) (1431:1431:1431)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1874:1874:1874)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1874:1874:1874)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1874:1874:1874)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1874:1874:1874)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1805:1805:1805) (1832:1832:1832)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (990:990:990) (995:995:995)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (991:991:991) (996:996:996)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (991:991:991) (996:996:996)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (991:991:991) (996:996:996)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[6\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (909:909:909) (934:934:934)) + (PORT datab (674:674:674) (688:688:688)) + (PORT datac (1144:1144:1144) (1212:1212:1212)) + (PORT datad (1290:1290:1290) (1419:1419:1419)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[6\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1218:1218:1218) (1246:1246:1246)) + (PORT datab (1255:1255:1255) (1282:1282:1282)) + (PORT datac (313:313:313) (332:332:332)) + (PORT datad (1956:1956:1956) (2083:2083:2083)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1807:1807:1807) (1893:1893:1893)) + (PORT d[1] (2094:2094:2094) (2205:2205:2205)) + (PORT d[2] (2125:2125:2125) (2264:2264:2264)) + (PORT d[3] (1876:1876:1876) (1969:1969:1969)) + (PORT d[4] (2315:2315:2315) (2392:2392:2392)) + (PORT d[5] (1694:1694:1694) (1783:1783:1783)) + (PORT d[6] (1925:1925:1925) (1996:1996:1996)) + (PORT d[7] (1486:1486:1486) (1574:1574:1574)) + (PORT d[8] (2216:2216:2216) (2334:2334:2334)) + (PORT d[9] (3286:3286:3286) (3488:3488:3488)) + (PORT d[10] (1591:1591:1591) (1690:1690:1690)) + (PORT d[11] (1981:1981:1981) (2051:2051:2051)) + (PORT d[12] (1772:1772:1772) (1798:1798:1798)) + (PORT clk (1848:1848:1848) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1875:1875:1875)) + (PORT d[0] (2644:2644:2644) (2591:2591:2591)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1811:1811:1811) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1489:1489:1489) (1574:1574:1574)) + (PORT d[1] (2573:2573:2573) (2667:2667:2667)) + (PORT d[2] (2212:2212:2212) (2353:2353:2353)) + (PORT d[3] (1869:1869:1869) (1982:1982:1982)) + (PORT d[4] (2315:2315:2315) (2365:2365:2365)) + (PORT d[5] (1709:1709:1709) (1786:1786:1786)) + (PORT d[6] (1728:1728:1728) (1808:1808:1808)) + (PORT d[7] (1522:1522:1522) (1615:1615:1615)) + (PORT d[8] (2225:2225:2225) (2361:2361:2361)) + (PORT d[9] (3531:3531:3531) (3742:3742:3742)) + (PORT d[10] (1351:1351:1351) (1439:1439:1439)) + (PORT d[11] (1655:1655:1655) (1706:1706:1706)) + (PORT d[12] (2100:2100:2100) (2152:2152:2152)) + (PORT clk (1846:1846:1846) (1872:1872:1872)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1872:1872:1872)) + (PORT d[0] (1291:1291:1291) (1265:1265:1265)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1847:1847:1847) (1873:1873:1873)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1809:1809:1809) (1835:1835:1835)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (994:994:994) (998:998:998)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (999:999:999)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (999:999:999)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (999:999:999)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1321:1321:1321) (1383:1383:1383)) + (PORT clk (1846:1846:1846) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (3132:3132:3132) (3372:3372:3372)) + (PORT d[1] (4267:4267:4267) (4444:4444:4444)) + (PORT d[2] (2301:2301:2301) (2470:2470:2470)) + (PORT d[3] (2187:2187:2187) (2289:2289:2289)) + (PORT d[4] (3508:3508:3508) (3634:3634:3634)) + (PORT d[5] (2380:2380:2380) (2498:2498:2498)) + (PORT d[6] (4072:4072:4072) (4206:4206:4206)) + (PORT d[7] (3046:3046:3046) (3200:3200:3200)) + (PORT d[8] (2176:2176:2176) (2293:2293:2293)) + (PORT d[9] (2772:2772:2772) (2847:2847:2847)) + (PORT d[10] (2937:2937:2937) (3127:3127:3127)) + (PORT d[11] (3179:3179:3179) (3339:3339:3339)) + (PORT d[12] (3050:3050:3050) (3184:3184:3184)) + (PORT clk (1843:1843:1843) (1871:1871:1871)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2312:2312:2312) (2312:2312:2312)) + (PORT clk (1843:1843:1843) (1871:1871:1871)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1875:1875:1875)) + (PORT d[0] (5462:5462:5462) (5569:5569:5569)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1847:1847:1847) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1847:1847:1847) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1847:1847:1847) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1847:1847:1847) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1801:1801:1801) (1800:1800:1800)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2093:2093:2093) (2293:2293:2293)) + (PORT clk (1811:1811:1811) (1806:1806:1806)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4214:4214:4214) (4279:4279:4279)) + (PORT d[1] (4301:4301:4301) (4372:4372:4372)) + (PORT d[2] (4125:4125:4125) (4227:4227:4227)) + (PORT d[3] (4288:4288:4288) (4412:4412:4412)) + (PORT d[4] (4100:4100:4100) (4252:4252:4252)) + (PORT d[5] (4335:4335:4335) (4468:4468:4468)) + (PORT d[6] (4130:4130:4130) (4197:4197:4197)) + (PORT d[7] (4081:4081:4081) (4200:4200:4200)) + (PORT d[8] (4230:4230:4230) (4286:4286:4286)) + (PORT d[9] (4102:4102:4102) (4208:4208:4208)) + (PORT d[10] (4243:4243:4243) (4291:4291:4291)) + (PORT d[11] (4340:4340:4340) (4429:4429:4429)) + (PORT d[12] (4159:4159:4159) (4233:4233:4233)) + (PORT clk (1807:1807:1807) (1802:1802:1802)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1811:1811:1811) (1806:1806:1806)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1807:1807:1807)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1807:1807:1807)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1807:1807:1807)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1807:1807:1807)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1313:1313:1313) (1378:1378:1378)) + (PORT clk (1852:1852:1852) (1880:1880:1880)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2797:2797:2797) (2917:2917:2917)) + (PORT d[1] (3674:3674:3674) (3821:3821:3821)) + (PORT d[2] (2586:2586:2586) (2781:2781:2781)) + (PORT d[3] (1912:1912:1912) (2028:2028:2028)) + (PORT d[4] (3515:3515:3515) (3623:3623:3623)) + (PORT d[5] (2661:2661:2661) (2772:2772:2772)) + (PORT d[6] (4062:4062:4062) (4173:4173:4173)) + (PORT d[7] (2712:2712:2712) (2860:2860:2860)) + (PORT d[8] (2947:2947:2947) (3041:3041:3041)) + (PORT d[9] (2758:2758:2758) (2945:2945:2945)) + (PORT d[10] (3655:3655:3655) (3891:3891:3891)) + (PORT d[11] (2910:2910:2910) (3054:3054:3054)) + (PORT d[12] (2719:2719:2719) (2843:2843:2843)) + (PORT clk (1849:1849:1849) (1876:1876:1876)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2834:2834:2834) (2931:2931:2931)) + (PORT clk (1849:1849:1849) (1876:1876:1876)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1880:1880:1880)) + (PORT d[0] (5279:5279:5279) (5172:5172:5172)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1881:1881:1881)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1881:1881:1881)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1881:1881:1881)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1881:1881:1881)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1807:1807:1807) (1805:1805:1805)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1326:1326:1326) (1367:1367:1367)) + (PORT clk (1817:1817:1817) (1811:1811:1811)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4380:4380:4380) (4430:4430:4430)) + (PORT d[1] (4245:4245:4245) (4297:4297:4297)) + (PORT d[2] (4163:4163:4163) (4287:4287:4287)) + (PORT d[3] (4271:4271:4271) (4359:4359:4359)) + (PORT d[4] (4118:4118:4118) (4243:4243:4243)) + (PORT d[5] (4331:4331:4331) (4458:4458:4458)) + (PORT d[6] (4092:4092:4092) (4140:4140:4140)) + (PORT d[7] (4012:4012:4012) (4135:4135:4135)) + (PORT d[8] (4274:4274:4274) (4402:4402:4402)) + (PORT d[9] (4040:4040:4040) (4147:4147:4147)) + (PORT d[10] (4259:4259:4259) (4327:4327:4327)) + (PORT d[11] (4179:4179:4179) (4202:4202:4202)) + (PORT d[12] (4212:4212:4212) (4286:4286:4286)) + (PORT clk (1813:1813:1813) (1807:1807:1807)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1817:1817:1817) (1811:1811:1811)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1818:1818:1818) (1812:1812:1812)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1818:1818:1818) (1812:1812:1812)) + (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1818:1818:1818) (1812:1812:1812)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1818:1818:1818) (1812:1812:1812)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1809:1809:1809) (1807:1807:1807)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1626:1626:1626) (1682:1682:1682)) + (PORT datab (1084:1084:1084) (1109:1109:1109)) + (PORT datac (1464:1464:1464) (1492:1492:1492)) + (PORT datad (1498:1498:1498) (1563:1563:1563)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector6\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1293:1293:1293) (1371:1371:1371)) + (PORT datab (393:393:393) (418:418:418)) + (PORT datac (1538:1538:1538) (1525:1525:1525)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~88) + (DELAY + (ABSOLUTE + (PORT dataa (1598:1598:1598) (1753:1753:1753)) + (PORT datab (3082:3082:3082) (3273:3273:3273)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE raw_loader_in\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (479:479:479) (732:732:732)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~69) + (DELAY + (ABSOLUTE + (PORT datab (3078:3078:3078) (3271:3271:3271)) + (PORT datac (1351:1351:1351) (1416:1416:1416)) + (PORT datad (1578:1578:1578) (1622:1622:1622)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~78) + (DELAY + (ABSOLUTE + (PORT dataa (1148:1148:1148) (1172:1172:1172)) + (PORT datab (1123:1123:1123) (1163:1163:1163)) + (PORT datac (178:178:178) (214:214:214)) + (PORT datad (182:182:182) (211:211:211)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[6\]\~79) + (DELAY + (ABSOLUTE + (PORT dataa (1330:1330:1330) (1422:1422:1422)) + (PORT datab (1122:1122:1122) (1164:1164:1164)) + (PORT datac (1105:1105:1105) (1155:1155:1155)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[6\]) + (DELAY + (ABSOLUTE + (PORT dataa (1426:1426:1426) (1479:1479:1479)) + (PORT datab (400:400:400) (440:440:440)) + (PORT datac (1276:1276:1276) (1302:1302:1302)) + (PORT datad (195:195:195) (221:221:221)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1527:1527:1527) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[6\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (398:398:398) (440:440:440)) + (PORT datab (377:377:377) (400:400:400)) + (PORT datac (363:363:363) (430:430:430)) + (PORT datad (579:579:579) (606:606:606)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1566:1566:1566) (1548:1548:1548)) + (PORT ena (1684:1684:1684) (1669:1669:1669)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_ir_we\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1019:1019:1019) (1143:1143:1143)) + (PORT datab (1044:1044:1044) (1189:1189:1189)) + (PORT datac (694:694:694) (760:760:760)) + (PORT datad (1149:1149:1149) (1174:1174:1174)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~0) + (DELAY + (ABSOLUTE + (PORT dataa (935:935:935) (1005:1005:1005)) + (PORT datab (964:964:964) (1009:1009:1009)) + (PORT datac (186:186:186) (228:228:228)) + (PORT datad (1645:1645:1645) (1710:1710:1710)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~4) + (DELAY + (ABSOLUTE + (PORT datac (1432:1432:1432) (1541:1541:1541)) + (PORT datad (1343:1343:1343) (1341:1341:1341)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~2) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (255:255:255)) + (PORT datab (207:207:207) (249:249:249)) + (PORT datac (1372:1372:1372) (1418:1418:1418)) + (PORT datad (700:700:700) (789:789:789)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~5) + (DELAY + (ABSOLUTE + (PORT dataa (421:421:421) (482:482:482)) + (PORT datab (609:609:609) (624:624:624)) + (PORT datac (594:594:594) (626:626:626)) + (PORT datad (603:603:603) (630:630:630)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe\~6) + (DELAY + (ABSOLUTE + (PORT dataa (976:976:976) (1045:1045:1045)) + (PORT datab (196:196:196) (234:234:234)) + (PORT datac (1955:1955:1955) (2058:2058:2058)) + (PORT datad (1784:1784:1784) (1837:1837:1837)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_bus_db_oe) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (342:342:342) (377:377:377)) + (PORT datac (1519:1519:1519) (1510:1510:1510)) + (PORT datad (850:850:850) (879:879:879)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (367:367:367) (406:406:406)) + (PORT datac (1375:1375:1375) (1409:1409:1409)) + (PORT datad (334:334:334) (355:355:355)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~61) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (256:256:256)) + (PORT datab (988:988:988) (1051:1051:1051)) + (PORT datac (1200:1200:1200) (1278:1278:1278)) + (PORT datad (937:937:937) (977:977:977)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~63) + (DELAY + (ABSOLUTE + (PORT dataa (410:410:410) (489:489:489)) + (PORT datab (199:199:199) (239:239:239)) + (PORT datac (859:859:859) (882:882:882)) + (PORT datad (202:202:202) (230:230:230)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~64) + (DELAY + (ABSOLUTE + (PORT dataa (871:871:871) (901:901:901)) + (PORT datab (773:773:773) (837:837:837)) + (PORT datac (320:320:320) (339:339:339)) + (PORT datad (1004:1004:1004) (1090:1090:1090)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]\~65) + (DELAY + (ABSOLUTE + (PORT dataa (351:351:351) (381:381:381)) + (PORT datad (174:174:174) (201:201:201)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[7\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1557:1557:1557) (1549:1549:1549)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~67) + (DELAY + (ABSOLUTE + (PORT dataa (1059:1059:1059) (1136:1136:1136)) + (PORT datab (687:687:687) (747:747:747)) + (PORT datad (962:962:962) (1025:1025:1025)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~68) + (DELAY + (ABSOLUTE + (PORT dataa (990:990:990) (1072:1072:1072)) + (PORT datab (1214:1214:1214) (1285:1285:1285)) + (PORT datac (261:261:261) (347:347:347)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]\~69) + (DELAY + (ABSOLUTE + (PORT dataa (670:670:670) (705:705:705)) + (PORT datab (230:230:230) (273:273:273)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[6\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1555:1555:1555) (1547:1547:1547)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (653:653:653) (715:715:715)) + (PORT datab (385:385:385) (451:451:451)) + (PORT datac (1078:1078:1078) (1083:1083:1083)) + (PORT datad (624:624:624) (661:661:661)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~58) + (DELAY + (ABSOLUTE + (PORT dataa (787:787:787) (866:866:866)) + (PORT datab (448:448:448) (525:525:525)) + (PORT datac (1184:1184:1184) (1259:1259:1259)) + (PORT datad (648:648:648) (704:704:704)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~130) + (DELAY + (ABSOLUTE + (PORT dataa (991:991:991) (1074:1074:1074)) + (PORT datab (559:559:559) (576:576:576)) + (PORT datac (261:261:261) (348:348:348)) + (PORT datad (1017:1017:1017) (1092:1092:1092)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]\~59) + (DELAY + (ABSOLUTE + (PORT dataa (634:634:634) (710:710:710)) + (PORT datab (344:344:344) (373:373:373)) + (PORT datad (499:499:499) (510:510:510)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[4\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1520:1520:1520) (1534:1534:1534)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1555:1555:1555) (1547:1547:1547)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~56) + (DELAY + (ABSOLUTE + (PORT datac (666:666:666) (727:727:727)) + (PORT datad (689:689:689) (759:759:759)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]\~57) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (246:246:246)) + (PORT datab (943:943:943) (1018:1018:1018)) + (PORT datad (325:325:325) (344:344:344)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[5\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1519:1519:1519) (1533:1533:1533)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1559:1559:1559) (1552:1552:1552)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (2099:2099:2099) (2130:2130:2130)) + (PORT datab (419:419:419) (486:486:486)) + (PORT datac (867:867:867) (901:901:901)) + (PORT datad (675:675:675) (729:729:729)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]\~54) + (DELAY + (ABSOLUTE + (PORT datac (1091:1091:1091) (1182:1182:1182)) + (PORT datad (1208:1208:1208) (1271:1271:1271)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]\~55) + (DELAY + (ABSOLUTE + (PORT dataa (783:783:783) (871:871:871)) + (PORT datab (366:366:366) (403:403:403)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[0\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1558:1558:1558) (1550:1550:1550)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]\~50) + (DELAY + (ABSOLUTE + (PORT datac (1093:1093:1093) (1185:1185:1185)) + (PORT datad (1208:1208:1208) (1267:1267:1267)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (210:210:210) (257:257:257)) + (PORT datab (366:366:366) (403:403:403)) + (PORT datad (737:737:737) (821:821:821)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[3\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1558:1558:1558) (1550:1550:1550)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]\~52) + (DELAY + (ABSOLUTE + (PORT dataa (902:902:902) (935:935:935)) + (PORT datab (645:645:645) (669:669:669)) + (PORT datac (182:182:182) (220:220:220)) + (PORT datad (1923:1923:1923) (2012:2012:2012)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]\~53) + (DELAY + (ABSOLUTE + (PORT dataa (785:785:785) (866:866:866)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[2\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1558:1558:1558) (1550:1550:1550)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (383:383:383) (453:453:453)) + (PORT datab (415:415:415) (474:474:474)) + (PORT datac (1051:1051:1051) (1055:1055:1055)) + (PORT datad (843:843:843) (857:857:857)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[2\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (367:367:367) (405:405:405)) + (PORT datab (886:886:886) (906:906:906)) + (PORT datac (1093:1093:1093) (1184:1184:1184)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[2\]\~48) + (DELAY + (ABSOLUTE + (PORT datab (199:199:199) (238:238:238)) + (PORT datad (732:732:732) (816:816:816)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|zx_keyboard_\|keys\[1\]\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1537:1537:1537)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1558:1558:1558) (1550:1550:1550)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|zx_keyboard_\|key_row\~1) + (DELAY + (ABSOLUTE + (PORT datab (1126:1126:1126) (1194:1194:1194)) + (PORT datac (2686:2686:2686) (2847:2847:2847)) + (PORT datad (218:218:218) (287:287:287)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (2330:2330:2330) (2493:2493:2493)) + (PORT datab (241:241:241) (323:323:323)) + (PORT datac (343:343:343) (366:366:366)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (365:365:365) (387:387:387)) + (PORT datac (759:759:759) (766:766:766)) + (PORT datad (859:859:859) (894:894:894)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (978:978:978) (1013:1013:1013)) + (PORT clk (1845:1845:1845) (1873:1873:1873)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1539:1539:1539) (1622:1622:1622)) + (PORT d[1] (2607:2607:2607) (2688:2688:2688)) + (PORT d[2] (2171:2171:2171) (2319:2319:2319)) + (PORT d[3] (1846:1846:1846) (1952:1952:1952)) + (PORT d[4] (2317:2317:2317) (2374:2374:2374)) + (PORT d[5] (1398:1398:1398) (1468:1468:1468)) + (PORT d[6] (1423:1423:1423) (1485:1485:1485)) + (PORT d[7] (1543:1543:1543) (1643:1643:1643)) + (PORT d[8] (2272:2272:2272) (2402:2402:2402)) + (PORT d[9] (3351:3351:3351) (3559:3559:3559)) + (PORT d[10] (1322:1322:1322) (1383:1383:1383)) + (PORT d[11] (1649:1649:1649) (1694:1694:1694)) + (PORT d[12] (2365:2365:2365) (2417:2417:2417)) + (PORT clk (1842:1842:1842) (1869:1869:1869)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1809:1809:1809) (1763:1763:1763)) + (PORT clk (1842:1842:1842) (1869:1869:1869)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1873:1873:1873)) + (PORT d[0] (1979:1979:1979) (1957:1957:1957)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1874:1874:1874)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1874:1874:1874)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1874:1874:1874)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1874:1874:1874)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1805:1805:1805) (1832:1832:1832)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (990:990:990) (995:995:995)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (991:991:991) (996:996:996)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (991:991:991) (996:996:996)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a18.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (991:991:991) (996:996:996)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (695:695:695) (718:718:718)) + (PORT clk (1843:1843:1843) (1871:1871:1871)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1232:1232:1232) (1287:1287:1287)) + (PORT d[1] (1839:1839:1839) (1928:1928:1928)) + (PORT d[2] (2152:2152:2152) (2302:2302:2302)) + (PORT d[3] (1872:1872:1872) (1989:1989:1989)) + (PORT d[4] (2048:2048:2048) (2133:2133:2133)) + (PORT d[5] (1091:1091:1091) (1114:1114:1114)) + (PORT d[6] (1409:1409:1409) (1454:1454:1454)) + (PORT d[7] (1530:1530:1530) (1645:1645:1645)) + (PORT d[8] (2543:2543:2543) (2695:2695:2695)) + (PORT d[9] (3411:3411:3411) (3618:3618:3618)) + (PORT d[10] (1316:1316:1316) (1396:1396:1396)) + (PORT d[11] (1672:1672:1672) (1707:1707:1707)) + (PORT d[12] (2406:2406:2406) (2481:2481:2481)) + (PORT clk (1840:1840:1840) (1867:1867:1867)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2592:2592:2592) (2628:2628:2628)) + (PORT clk (1840:1840:1840) (1867:1867:1867)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1871:1871:1871)) + (PORT d[0] (1732:1732:1732) (1708:1708:1708)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1872:1872:1872)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1872:1872:1872)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1872:1872:1872)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1872:1872:1872)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1803:1803:1803) (1830:1830:1830)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (988:988:988) (993:993:993)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (989:989:989) (994:994:994)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (989:989:989) (994:994:994)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (989:989:989) (994:994:994)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (962:962:962) (972:972:972)) + (PORT clk (1849:1849:1849) (1876:1876:1876)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1430:1430:1430) (1475:1475:1475)) + (PORT d[1] (1863:1863:1863) (1974:1974:1974)) + (PORT d[2] (1874:1874:1874) (2006:2006:2006)) + (PORT d[3] (1548:1548:1548) (1613:1613:1613)) + (PORT d[4] (1720:1720:1720) (1791:1791:1791)) + (PORT d[5] (1419:1419:1419) (1494:1494:1494)) + (PORT d[6] (1725:1725:1725) (1771:1771:1771)) + (PORT d[7] (1852:1852:1852) (1991:1991:1991)) + (PORT d[8] (3082:3082:3082) (3241:3241:3241)) + (PORT d[9] (3171:3171:3171) (3406:3406:3406)) + (PORT d[10] (1563:1563:1563) (1656:1656:1656)) + (PORT d[11] (2265:2265:2265) (2388:2388:2388)) + (PORT d[12] (2708:2708:2708) (2807:2807:2807)) + (PORT clk (1846:1846:1846) (1872:1872:1872)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1810:1810:1810) (1782:1782:1782)) + (PORT clk (1846:1846:1846) (1872:1872:1872)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1876:1876:1876)) + (PORT d[0] (2235:2235:2235) (2184:2184:2184)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1877:1877:1877)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1809:1809:1809) (1835:1835:1835)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (994:994:994) (998:998:998)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (999:999:999)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (999:999:999)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (999:999:999)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[2\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (980:980:980) (1052:1052:1052)) + (PORT datab (910:910:910) (970:970:970)) + (PORT datac (864:864:864) (861:861:861)) + (PORT datad (915:915:915) (931:931:931)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (979:979:979) (1014:1014:1014)) + (PORT clk (1847:1847:1847) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1495:1495:1495) (1550:1550:1550)) + (PORT d[1] (2584:2584:2584) (2663:2663:2663)) + (PORT d[2] (2005:2005:2005) (2167:2167:2167)) + (PORT d[3] (1860:1860:1860) (1959:1959:1959)) + (PORT d[4] (2033:2033:2033) (2096:2096:2096)) + (PORT d[5] (1398:1398:1398) (1469:1469:1469)) + (PORT d[6] (1719:1719:1719) (1785:1785:1785)) + (PORT d[7] (1509:1509:1509) (1601:1601:1601)) + (PORT d[8] (2234:2234:2234) (2387:2387:2387)) + (PORT d[9] (3351:3351:3351) (3558:3558:3558)) + (PORT d[10] (1332:1332:1332) (1407:1407:1407)) + (PORT d[11] (1681:1681:1681) (1737:1737:1737)) + (PORT d[12] (2101:2101:2101) (2153:2153:2153)) + (PORT clk (1844:1844:1844) (1871:1871:1871)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1701:1701:1701) (1711:1711:1711)) + (PORT clk (1844:1844:1844) (1871:1871:1871)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1847:1847:1847) (1875:1875:1875)) + (PORT d[0] (1789:1789:1789) (1743:1743:1743)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1807:1807:1807) (1834:1834:1834)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (992:992:992) (997:997:997)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (993:993:993) (998:998:998)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (993:993:993) (998:998:998)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|ram_block1a26.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (993:993:993) (998:998:998)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ram1\|altsyncram_component\|auto_generated\|mux2\|result_node\[2\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (991:991:991) (1002:1002:1002)) + (PORT datab (1317:1317:1317) (1455:1455:1455)) + (PORT datac (173:173:173) (206:206:206)) + (PORT datad (1201:1201:1201) (1246:1246:1246)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1788:1788:1788) (1877:1877:1877)) + (PORT d[1] (2361:2361:2361) (2459:2459:2459)) + (PORT d[2] (1956:1956:1956) (2114:2114:2114)) + (PORT d[3] (1873:1873:1873) (1989:1989:1989)) + (PORT d[4] (2307:2307:2307) (2357:2357:2357)) + (PORT d[5] (1690:1690:1690) (1776:1776:1776)) + (PORT d[6] (1732:1732:1732) (1816:1816:1816)) + (PORT d[7] (1555:1555:1555) (1649:1649:1649)) + (PORT d[8] (2191:2191:2191) (2347:2347:2347)) + (PORT d[9] (3356:3356:3356) (3572:3572:3572)) + (PORT d[10] (1583:1583:1583) (1661:1661:1661)) + (PORT d[11] (1970:1970:1970) (2025:2025:2025)) + (PORT d[12] (2068:2068:2068) (2110:2110:2110)) + (PORT clk (1847:1847:1847) (1874:1874:1874)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1847:1847:1847) (1874:1874:1874)) + (PORT d[0] (1275:1275:1275) (1274:1274:1274)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1875:1875:1875)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1810:1810:1810) (1837:1837:1837)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (1000:1000:1000)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2278:2278:2278) (2409:2409:2409)) + (PORT d[1] (3439:3439:3439) (3559:3559:3559)) + (PORT d[2] (2283:2283:2283) (2459:2459:2459)) + (PORT d[3] (2427:2427:2427) (2545:2545:2545)) + (PORT d[4] (2662:2662:2662) (2786:2786:2786)) + (PORT d[5] (2725:2725:2725) (2847:2847:2847)) + (PORT d[6] (3253:3253:3253) (3377:3377:3377)) + (PORT d[7] (2389:2389:2389) (2532:2532:2532)) + (PORT d[8] (2637:2637:2637) (2732:2732:2732)) + (PORT d[9] (2733:2733:2733) (2939:2939:2939)) + (PORT d[10] (3679:3679:3679) (3942:3942:3942)) + (PORT d[11] (2598:2598:2598) (2740:2740:2740)) + (PORT d[12] (2405:2405:2405) (2534:2534:2534)) + (PORT clk (1857:1857:1857) (1882:1882:1882)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1882:1882:1882)) + (PORT d[0] (4039:4039:4039) (3953:3953:3953)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1883:1883:1883)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1845:1845:1845)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1008:1008:1008)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1009:1009:1009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1009:1009:1009)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1009:1009:1009)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1546:1546:1546) (1629:1629:1629)) + (PORT clk (1849:1849:1849) (1877:1877:1877)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2782:2782:2782) (3017:3017:3017)) + (PORT d[1] (3696:3696:3696) (3846:3846:3846)) + (PORT d[2] (2300:2300:2300) (2462:2462:2462)) + (PORT d[3] (1908:1908:1908) (2025:2025:2025)) + (PORT d[4] (3502:3502:3502) (3621:3621:3621)) + (PORT d[5] (2770:2770:2770) (2893:2893:2893)) + (PORT d[6] (2979:2979:2979) (3093:3093:3093)) + (PORT d[7] (2708:2708:2708) (2854:2854:2854)) + (PORT d[8] (2190:2190:2190) (2293:2293:2293)) + (PORT d[9] (2908:2908:2908) (3077:3077:3077)) + (PORT d[10] (3379:3379:3379) (3620:3620:3620)) + (PORT d[11] (2309:2309:2309) (2408:2408:2408)) + (PORT d[12] (3006:3006:3006) (3139:3139:3139)) + (PORT clk (1846:1846:1846) (1873:1873:1873)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2327:2327:2327) (2335:2335:2335)) + (PORT clk (1846:1846:1846) (1873:1873:1873)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1877:1877:1877)) + (PORT d[0] (5176:5176:5176) (5277:5277:5277)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1878:1878:1878)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1878:1878:1878)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1878:1878:1878)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1878:1878:1878)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1804:1804:1804) (1802:1802:1802)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1357:1357:1357) (1402:1402:1402)) + (PORT clk (1814:1814:1814) (1808:1808:1808)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4184:4184:4184) (4244:4244:4244)) + (PORT d[1] (4245:4245:4245) (4296:4296:4296)) + (PORT d[2] (4109:4109:4109) (4210:4210:4210)) + (PORT d[3] (4316:4316:4316) (4447:4447:4447)) + (PORT d[4] (4132:4132:4132) (4244:4244:4244)) + (PORT d[5] (4358:4358:4358) (4486:4486:4486)) + (PORT d[6] (4149:4149:4149) (4218:4218:4218)) + (PORT d[7] (4070:4070:4070) (4173:4173:4173)) + (PORT d[8] (4401:4401:4401) (4450:4450:4450)) + (PORT d[9] (4118:4118:4118) (4213:4213:4213)) + (PORT d[10] (4259:4259:4259) (4326:4326:4326)) + (PORT d[11] (4343:4343:4343) (4436:4436:4436)) + (PORT d[12] (4162:4162:4162) (4268:4268:4268)) + (PORT clk (1810:1810:1810) (1804:1804:1804)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1814:1814:1814) (1808:1808:1808)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1815:1815:1815) (1809:1809:1809)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1815:1815:1815) (1809:1809:1809)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1815:1815:1815) (1809:1809:1809)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1815:1815:1815) (1809:1809:1809)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1635:1635:1635) (1736:1736:1736)) + (PORT clk (1855:1855:1855) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2769:2769:2769) (2892:2892:2892)) + (PORT d[1] (3675:3675:3675) (3804:3804:3804)) + (PORT d[2] (2626:2626:2626) (2825:2825:2825)) + (PORT d[3] (2214:2214:2214) (2326:2326:2326)) + (PORT d[4] (3219:3219:3219) (3326:3326:3326)) + (PORT d[5] (2898:2898:2898) (3031:3031:3031)) + (PORT d[6] (3790:3790:3790) (3911:3911:3911)) + (PORT d[7] (2700:2700:2700) (2864:2864:2864)) + (PORT d[8] (2395:2395:2395) (2480:2480:2480)) + (PORT d[9] (2642:2642:2642) (2770:2770:2770)) + (PORT d[10] (3427:3427:3427) (3672:3672:3672)) + (PORT d[11] (2316:2316:2316) (2429:2429:2429)) + (PORT d[12] (2971:2971:2971) (3142:3142:3142)) + (PORT clk (1852:1852:1852) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2833:2833:2833) (2930:2930:2930)) + (PORT clk (1852:1852:1852) (1879:1879:1879)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1855:1855:1855) (1883:1883:1883)) + (PORT d[0] (5273:5273:5273) (5168:5168:5168)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1810:1810:1810) (1808:1808:1808)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.datain_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1035:1035:1035) (1083:1083:1083)) + (PORT clk (1820:1820:1820) (1814:1814:1814)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (4177:4177:4177) (4235:4235:4235)) + (PORT d[1] (4298:4298:4298) (4370:4370:4370)) + (PORT d[2] (4174:4174:4174) (4275:4275:4275)) + (PORT d[3] (4395:4395:4395) (4446:4446:4446)) + (PORT d[4] (4147:4147:4147) (4276:4276:4276)) + (PORT d[5] (4270:4270:4270) (4393:4393:4393)) + (PORT d[6] (4089:4089:4089) (4191:4191:4191)) + (PORT d[7] (4096:4096:4096) (4203:4203:4203)) + (PORT d[8] (4302:4302:4302) (4418:4418:4418)) + (PORT d[9] (4083:4083:4083) (4168:4168:4168)) + (PORT d[10] (4255:4255:4255) (4227:4227:4227)) + (PORT d[11] (4248:4248:4248) (4254:4254:4254)) + (PORT d[12] (4214:4214:4214) (4278:4278:4278)) + (PORT clk (1816:1816:1816) (1810:1810:1810)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1814:1814:1814)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1821:1821:1821) (1815:1815:1815)) + (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1821:1821:1821) (1815:1815:1815)) + (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1821:1821:1821) (1815:1815:1815)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1821:1821:1821) (1815:1815:1815)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE ram0\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1810:1810:1810)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (639:639:639) (659:659:659)) + (PORT datab (636:636:636) (654:654:654)) + (PORT datac (1229:1229:1229) (1282:1282:1282)) + (PORT datad (1527:1527:1527) (1587:1587:1587)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Selector0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1393:1393:1393) (1396:1396:1396)) + (PORT datab (1198:1198:1198) (1234:1234:1234)) + (PORT datac (1242:1242:1242) (1318:1318:1318)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~82) + (DELAY + (ABSOLUTE + (PORT dataa (1631:1631:1631) (1779:1779:1779)) + (PORT datab (2600:2600:2600) (2767:2767:2767)) + (PORT datac (173:173:173) (207:207:207)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (1636:1636:1636) (1703:1703:1703)) + (PORT datab (1121:1121:1121) (1146:1146:1146)) + (PORT datac (1231:1231:1231) (1274:1274:1274)) + (PORT datad (182:182:182) (211:211:211)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (336:336:336) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (1637:1637:1637) (1700:1700:1700)) + (PORT datab (1583:1583:1583) (1625:1625:1625)) + (PORT datac (1954:1954:1954) (1991:1991:1991)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|data_pins_\|SYNTHESIZED_WIRE_0\[2\]) + (DELAY + (ABSOLUTE + (PORT dataa (1431:1431:1431) (1482:1482:1482)) + (PORT datab (217:217:217) (256:256:256)) + (PORT datac (1755:1755:1755) (1789:1789:1789)) + (PORT datad (376:376:376) (397:397:397)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|data_pins_\|dout\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1527:1527:1527) (1531:1531:1531)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (819:819:819) (825:825:825)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[2\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (563:563:563) (589:589:589)) + (PORT datac (352:352:352) (379:379:379)) + (PORT datad (1350:1350:1350) (1374:1374:1374)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|bus_control_\|db\[2\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (398:398:398) (441:441:441)) + (PORT datab (621:621:621) (651:651:651)) + (PORT datac (236:236:236) (312:312:312)) + (PORT datad (316:316:316) (336:336:336)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|ir_\|opcode\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1523:1523:1523) (1536:1536:1536)) + (PORT asdata (717:717:717) (742:742:742)) + (PORT clrn (1566:1566:1566) (1548:1548:1548)) + (PORT ena (1698:1698:1698) (1714:1714:1714)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|pla_decode_\|Equal1\~4) + (DELAY + (ABSOLUTE + (PORT datab (1700:1700:1700) (1759:1759:1759)) + (PORT datac (651:651:651) (715:715:715)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~26) + (DELAY + (ABSOLUTE + (PORT dataa (626:626:626) (679:679:679)) + (PORT datab (581:581:581) (612:612:612)) + (PORT datac (853:853:853) (895:895:895)) + (PORT datad (936:936:936) (1013:1013:1013)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|ctl_alu_op_low\~45) + (DELAY + (ABSOLUTE + (PORT dataa (667:667:667) (723:723:723)) + (PORT datab (1346:1346:1346) (1450:1450:1450)) + (PORT datac (950:950:950) (1009:1009:1009)) + (PORT datad (2364:2364:2364) (2472:2472:2472)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~17) + (DELAY + (ABSOLUTE + (PORT dataa (1189:1189:1189) (1236:1236:1236)) + (PORT datac (609:609:609) (620:620:620)) + (PORT datad (672:672:672) (721:721:721)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~18) + (DELAY + (ABSOLUTE + (PORT dataa (660:660:660) (720:720:720)) + (PORT datab (196:196:196) (234:234:234)) + (PORT datac (602:602:602) (615:615:615)) + (PORT datad (795:795:795) (812:812:812)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~11) + (DELAY + (ABSOLUTE + (PORT dataa (944:944:944) (1031:1031:1031)) + (PORT datab (1698:1698:1698) (1757:1757:1757)) + (PORT datac (612:612:612) (633:633:633)) + (PORT datad (1614:1614:1614) (1665:1665:1665)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~10) + (DELAY + (ABSOLUTE + (PORT dataa (654:654:654) (726:726:726)) + (PORT datab (655:655:655) (690:690:690)) + (PORT datac (935:935:935) (977:977:977)) + (PORT datad (1702:1702:1702) (1730:1730:1730)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1253:1253:1253) (1327:1327:1327)) + (PORT datab (863:863:863) (881:881:881)) + (PORT datac (2210:2210:2210) (2204:2204:2204)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~8) + (DELAY + (ABSOLUTE + (PORT dataa (391:391:391) (436:436:436)) + (PORT datab (1048:1048:1048) (1142:1142:1142)) + (PORT datac (1229:1229:1229) (1337:1337:1337)) + (PORT datad (1809:1809:1809) (1886:1886:1886)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1642:1642:1642) (1711:1711:1711)) + (PORT datab (1060:1060:1060) (1165:1165:1165)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~13) + (DELAY + (ABSOLUTE + (PORT dataa (881:881:881) (911:911:911)) + (PORT datab (197:197:197) (236:236:236)) + (PORT datac (1094:1094:1094) (1103:1103:1103)) + (PORT datad (527:527:527) (539:539:539)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~15) + (DELAY + (ABSOLUTE + (PORT dataa (900:900:900) (931:931:931)) + (PORT datab (1455:1455:1455) (1475:1475:1475)) + (PORT datac (852:852:852) (892:892:892)) + (PORT datad (323:323:323) (336:336:336)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1112:1112:1112) (1123:1123:1123)) + (PORT datab (642:642:642) (684:684:684)) + (PORT datac (193:193:193) (225:225:225)) + (PORT datad (851:851:851) (887:887:887)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~16) + (DELAY + (ABSOLUTE + (PORT datab (939:939:939) (960:960:960)) + (PORT datac (544:544:544) (543:543:543)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1124:1124:1124) (1167:1167:1167)) + (PORT datab (639:639:639) (659:659:659)) + (PORT datac (393:393:393) (428:428:428)) + (PORT datad (1282:1282:1282) (1352:1352:1352)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~23) + (DELAY + (ABSOLUTE + (PORT dataa (1232:1232:1232) (1279:1279:1279)) + (PORT datab (645:645:645) (677:677:677)) + (PORT datac (323:323:323) (355:355:355)) + (PORT datad (615:615:615) (636:636:636)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~22) + (DELAY + (ABSOLUTE + (PORT dataa (1502:1502:1502) (1573:1573:1573)) + (PORT datab (659:659:659) (686:686:686)) + (PORT datac (1295:1295:1295) (1359:1359:1359)) + (PORT datad (1603:1603:1603) (1668:1668:1668)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~56) + (DELAY + (ABSOLUTE + (PORT dataa (288:288:288) (386:386:386)) + (PORT datab (269:269:269) (352:352:352)) + (PORT datac (394:394:394) (461:461:461)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~24) + (DELAY + (ABSOLUTE + (PORT dataa (986:986:986) (1028:1028:1028)) + (PORT datab (716:716:716) (749:749:749)) + (PORT datac (686:686:686) (718:718:718)) + (PORT datad (339:339:339) (357:357:357)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~25) + (DELAY + (ABSOLUTE + (PORT dataa (870:870:870) (906:906:906)) + (PORT datab (945:945:945) (1011:1011:1011)) + (PORT datac (586:586:586) (615:615:615)) + (PORT datad (861:861:861) (893:893:893)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~26) + (DELAY + (ABSOLUTE + (PORT dataa (1699:1699:1699) (1734:1734:1734)) + (PORT datab (1175:1175:1175) (1288:1288:1288)) + (PORT datac (850:850:850) (860:860:860)) + (PORT datad (203:203:203) (232:232:232)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~27) + (DELAY + (ABSOLUTE + (PORT dataa (918:918:918) (952:952:952)) + (PORT datab (965:965:965) (1064:1064:1064)) + (PORT datac (882:882:882) (917:917:917)) + (PORT datad (1924:1924:1924) (1970:1970:1970)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~28) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (243:243:243)) + (PORT datab (219:219:219) (259:259:259)) + (PORT datac (574:574:574) (597:597:597)) + (PORT datad (173:173:173) (199:199:199)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~55) + (DELAY + (ABSOLUTE + (PORT dataa (1153:1153:1153) (1187:1187:1187)) + (PORT datab (469:469:469) (549:549:549)) + (PORT datac (420:420:420) (492:492:492)) + (PORT datad (1653:1653:1653) (1722:1722:1722)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~29) + (DELAY + (ABSOLUTE + (PORT dataa (726:726:726) (762:762:762)) + (PORT datab (626:626:626) (660:660:660)) + (PORT datac (884:884:884) (917:917:917)) + (PORT datad (622:622:622) (653:653:653)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~31) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (266:266:266)) + (PORT datab (1282:1282:1282) (1355:1355:1355)) + (PORT datac (170:170:170) (204:204:204)) + (PORT datad (578:578:578) (591:591:591)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~33) + (DELAY + (ABSOLUTE + (PORT dataa (1171:1171:1171) (1229:1229:1229)) + (PORT datab (1916:1916:1916) (1950:1950:1950)) + (PORT datac (608:608:608) (630:630:630)) + (PORT datad (1176:1176:1176) (1214:1214:1214)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~32) + (DELAY + (ABSOLUTE + (PORT dataa (837:837:837) (859:859:859)) + (PORT datab (719:719:719) (751:751:751)) + (PORT datac (608:608:608) (626:626:626)) + (PORT datad (1118:1118:1118) (1168:1168:1168)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~34) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (2938:2938:2938) (3016:3016:3016)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~20) + (DELAY + (ABSOLUTE + (PORT dataa (882:882:882) (902:902:902)) + (PORT datab (953:953:953) (1032:1032:1032)) + (PORT datac (203:203:203) (242:242:242)) + (PORT datad (1353:1353:1353) (1385:1385:1385)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~21) + (DELAY + (ABSOLUTE + (PORT dataa (607:607:607) (657:657:657)) + (PORT datab (966:966:966) (1062:1062:1062)) + (PORT datac (1191:1191:1191) (1245:1245:1245)) + (PORT datad (558:558:558) (574:574:574)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~35) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (197:197:197) (235:235:235)) + (PORT datac (169:169:169) (202:202:202)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~43) + (DELAY + (ABSOLUTE + (PORT datab (889:889:889) (942:942:942)) + (PORT datac (1266:1266:1266) (1297:1297:1297)) + (PORT datad (653:653:653) (705:705:705)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~44) + (DELAY + (ABSOLUTE + (PORT dataa (1105:1105:1105) (1131:1131:1131)) + (PORT datab (1221:1221:1221) (1298:1298:1298)) + (PORT datac (1671:1671:1671) (1710:1710:1710)) + (PORT datad (1088:1088:1088) (1188:1188:1188)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~45) + (DELAY + (ABSOLUTE + (PORT dataa (1917:1917:1917) (2023:2023:2023)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (2387:2387:2387) (2467:2467:2467)) + (PORT datad (357:357:357) (390:390:390)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~46) + (DELAY + (ABSOLUTE + (PORT dataa (828:828:828) (878:878:878)) + (PORT datab (967:967:967) (1007:1007:1007)) + (PORT datac (634:634:634) (663:663:663)) + (PORT datad (189:189:189) (222:222:222)) + (IOPATH dataa combout (304:304:304) (308:308:308)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~52) + (DELAY + (ABSOLUTE + (PORT dataa (1292:1292:1292) (1331:1331:1331)) + (PORT datab (198:198:198) (236:236:236)) + (PORT datac (389:389:389) (424:424:424)) + (PORT datad (616:616:616) (656:656:656)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|SYNTHESIZED_WIRE_17) + (DELAY + (ABSOLUTE + (PORT dataa (1049:1049:1049) (1100:1100:1100)) + (PORT datac (840:840:840) (932:932:932)) + (PORT datad (361:361:361) (394:394:394)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|T6) + (DELAY + (ABSOLUTE + (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1565:1565:1565) (1547:1547:1547)) + (PORT ena (1195:1195:1195) (1189:1189:1189)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~53) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (243:243:243)) + (PORT datab (799:799:799) (844:844:844)) + (PORT datac (215:215:215) (290:290:290)) + (PORT datad (188:188:188) (218:218:218)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|execute_\|setM1\~54) + (DELAY + (ABSOLUTE + (PORT dataa (570:570:570) (598:598:598)) + (PORT datab (867:867:867) (889:889:889)) + (PORT datac (907:907:907) (970:970:970)) + (PORT datad (551:551:551) (571:571:571)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|sequencer_\|DFFE_M1_ff\~0) + (DELAY + (ABSOLUTE + (PORT datab (1159:1159:1159) (1227:1227:1227)) + (PORT datad (895:895:895) (972:972:972)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|sequencer_\|DFFE_M1_ff) + (DELAY + (ABSOLUTE + (PORT clk (1514:1514:1514) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1558:1558:1558) (1539:1539:1539)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|resets_\|x1\~0) + (DELAY + (ABSOLUTE + (PORT datad (196:196:196) (221:221:221)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|fpga_reset) + (DELAY + (ABSOLUTE + (PORT clk (1541:1541:1541) (1560:1560:1560)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE z80_\|fpga_reset\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (596:596:596) (645:645:645)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|resets_\|x1) + (DELAY + (ABSOLUTE + (PORT clk (1546:1546:1546) (1547:1547:1547)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1584:1584:1584) (1563:1563:1563)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|resets_\|x3) + (DELAY + (ABSOLUTE + (PORT datab (2088:2088:2088) (2192:2192:2192)) + (PORT datac (238:238:238) (315:315:315)) + (PORT datad (2475:2475:2475) (2528:2528:2528)) + (IOPATH datab combout (336:336:336) (325:325:325)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_12) + (DELAY + (ABSOLUTE + (PORT clk (1538:1538:1538) (1555:1555:1555)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1584:1584:1584) (1563:1563:1563)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_10\~0) + (DELAY + (ABSOLUTE + (PORT datad (1770:1770:1770) (1814:1814:1814)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_10) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1526:1526:1526)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_9\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (225:225:225) (298:298:298)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|resets_\|SYNTHESIZED_WIRE_9) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1526:1526:1526)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|resets_\|DFFE_intr_ff3) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1526:1526:1526)) + (PORT asdata (567:567:567) (646:646:646)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|resets_\|clrpc_int\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1154:1154:1154) (1241:1241:1241)) + (PORT datab (1446:1446:1446) (1529:1529:1529)) + (PORT datad (1248:1248:1248) (1375:1375:1375)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE z80_\|resets_\|clrpc_int) + (DELAY + (ABSOLUTE + (PORT clk (1521:1521:1521) (1526:1526:1526)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1560:1560:1560) (1542:1542:1542)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|resets_\|clrpc\~0) + (DELAY + (ABSOLUTE + (PORT dataa (253:253:253) (343:343:343)) + (PORT datab (249:249:249) (335:335:335)) + (PORT datad (218:218:218) (287:287:287)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE z80_\|address_latch_\|abusz\[0\]) + (DELAY + (ABSOLUTE + (PORT datab (961:961:961) (981:981:981)) + (PORT datad (595:595:595) (611:611:611)) + (IOPATH datab combout (336:336:336) (332:332:332)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -49970,11 +49780,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[0\]\~0) (DELAY (ABSOLUTE - (PORT dataa (1391:1391:1391) (1424:1424:1424)) - (PORT datab (630:630:630) (671:671:671)) - (PORT datad (180:180:180) (209:209:209)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT dataa (622:622:622) (639:639:639)) + (PORT datab (1234:1234:1234) (1264:1264:1264)) + (PORT datad (524:524:524) (538:538:538)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -49984,11 +49794,11 @@ (INSTANCE z80_\|address_pins_\|DFFE_apin_latch\[0\]) (DELAY (ABSOLUTE - (PORT clk (1528:1528:1528) (1533:1533:1533)) + (PORT clk (1537:1537:1537) (1535:1535:1535)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (580:580:580) (654:654:654)) - (PORT sload (1117:1117:1117) (1168:1168:1168)) - (PORT ena (811:811:811) (804:804:804)) + (PORT asdata (593:593:593) (675:675:675)) + (PORT sload (1782:1782:1782) (1900:1900:1900)) + (PORT ena (1716:1716:1716) (1679:1679:1679)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -50001,11 +49811,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~59) + (INSTANCE D\[0\]\~47) (DELAY (ABSOLUTE - (PORT dataa (884:884:884) (914:914:914)) - (PORT datab (1147:1147:1147) (1200:1200:1200)) + (PORT dataa (1162:1162:1162) (1228:1228:1228)) + (PORT datab (1041:1041:1041) (1085:1085:1085)) (PORT datac (179:179:179) (216:216:216)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) @@ -50015,15 +49825,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[0\]\~60) + (INSTANCE D\[0\]\~48) (DELAY (ABSOLUTE - (PORT dataa (948:948:948) (996:996:996)) - (PORT datab (642:642:642) (701:701:701)) - (PORT datac (1642:1642:1642) (1669:1669:1669)) - (PORT datad (329:329:329) (345:345:345)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (342:342:342) (318:318:318)) + (PORT dataa (1311:1311:1311) (1393:1393:1393)) + (PORT datab (1298:1298:1298) (1344:1344:1344)) + (PORT datac (1371:1371:1371) (1393:1393:1393)) + (PORT datad (331:331:331) (348:348:348)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -50031,72 +49841,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~61) + (INSTANCE D\[1\]\~49) (DELAY (ABSOLUTE - (PORT dataa (1445:1445:1445) (1468:1468:1468)) - (PORT datac (831:831:831) (845:845:845)) - (PORT datad (196:196:196) (222:222:222)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[1\]\~62) - (DELAY - (ABSOLUTE - (PORT dataa (1402:1402:1402) (1476:1476:1476)) - (PORT datab (940:940:940) (1026:1026:1026)) - (PORT datac (962:962:962) (1081:1081:1081)) - (PORT datad (173:173:173) (198:198:198)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~63) - (DELAY - (ABSOLUTE - (PORT dataa (365:365:365) (413:413:413)) - (PORT datac (179:179:179) (216:216:216)) - (PORT datad (180:180:180) (209:209:209)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[2\]\~64) - (DELAY - (ABSOLUTE - (PORT dataa (414:414:414) (500:500:500)) - (PORT datab (233:233:233) (277:277:277)) - (PORT datac (1139:1139:1139) (1183:1183:1183)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~75) - (DELAY - (ABSOLUTE - (PORT dataa (211:211:211) (260:260:260)) - (PORT datac (1325:1325:1325) (1392:1392:1392)) - (PORT datad (197:197:197) (223:223:223)) + (PORT dataa (382:382:382) (409:409:409)) + (PORT datac (885:885:885) (898:898:898)) + (PORT datad (182:182:182) (211:211:211)) (IOPATH dataa combout (341:341:341) (347:347:347)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -50105,13 +49855,43 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[3\]\~76) + (INSTANCE D\[1\]\~50) (DELAY (ABSOLUTE - (PORT dataa (1121:1121:1121) (1209:1209:1209)) - (PORT datab (1140:1140:1140) (1196:1196:1196)) - (PORT datac (1527:1527:1527) (1561:1561:1561)) - (PORT datad (328:328:328) (343:343:343)) + (PORT dataa (915:915:915) (931:931:931)) + (PORT datab (956:956:956) (1023:1023:1023)) + (PORT datac (1536:1536:1536) (1592:1592:1592)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (1313:1313:1313) (1364:1364:1364)) + (PORT datac (1087:1087:1087) (1112:1112:1112)) + (PORT datad (183:183:183) (212:212:212)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[2\]\~52) + (DELAY + (ABSOLUTE + (PORT dataa (1130:1130:1130) (1185:1185:1185)) + (PORT datab (1122:1122:1122) (1162:1162:1162)) + (PORT datac (1107:1107:1107) (1159:1159:1159)) + (PORT datad (324:324:324) (339:339:339)) (IOPATH dataa combout (341:341:341) (319:319:319)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -50121,12 +49901,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~82) + (INSTANCE D\[3\]\~58) (DELAY (ABSOLUTE - (PORT dataa (887:887:887) (917:917:917)) - (PORT datab (1549:1549:1549) (1602:1602:1602)) - (PORT datad (181:181:181) (209:209:209)) + (PORT dataa (1162:1162:1162) (1228:1228:1228)) + (PORT datab (1714:1714:1714) (1779:1779:1779)) + (PORT datad (181:181:181) (210:210:210)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -50135,13 +49915,43 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[4\]\~83) + (INSTANCE D\[3\]\~59) (DELAY (ABSOLUTE - (PORT dataa (952:952:952) (1002:1002:1002)) - (PORT datab (1444:1444:1444) (1508:1508:1508)) - (PORT datac (1641:1641:1641) (1667:1667:1667)) - (PORT datad (330:330:330) (348:348:348)) + (PORT dataa (1149:1149:1149) (1221:1221:1221)) + (PORT datab (1298:1298:1298) (1344:1344:1344)) + (PORT datac (1372:1372:1372) (1395:1395:1395)) + (PORT datad (308:308:308) (327:327:327)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~65) + (DELAY + (ABSOLUTE + (PORT datab (345:345:345) (370:370:370)) + (PORT datac (885:885:885) (896:896:896)) + (PORT datad (180:180:180) (207:207:207)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE D\[4\]\~66) + (DELAY + (ABSOLUTE + (PORT dataa (918:918:918) (929:929:929)) + (PORT datab (963:963:963) (1031:1031:1031)) + (PORT datac (1536:1536:1536) (1593:1593:1593)) + (PORT datad (175:175:175) (201:201:201)) (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (342:342:342) (318:318:318)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -50151,13 +49961,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~92) + (INSTANCE D\[6\]\~70) (DELAY (ABSOLUTE - (PORT datab (1379:1379:1379) (1383:1383:1383)) - (PORT datac (179:179:179) (215:215:215)) - (PORT datad (180:180:180) (207:207:207)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT dataa (1152:1152:1152) (1177:1177:1177)) + (PORT datac (181:181:181) (217:217:217)) + (PORT datad (180:180:180) (209:209:209)) + (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -50165,15 +49975,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE D\[6\]\~93) + (INSTANCE D\[6\]\~71) (DELAY (ABSOLUTE - (PORT dataa (948:948:948) (1000:1000:1000)) - (PORT datab (894:894:894) (967:967:967)) - (PORT datac (1642:1642:1642) (1672:1672:1672)) + (PORT dataa (1326:1326:1326) (1423:1423:1423)) + (PORT datab (1123:1123:1123) (1164:1164:1164)) + (PORT datac (1104:1104:1104) (1158:1158:1158)) (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -50184,11 +49994,11 @@ (INSTANCE z80_\|nM1_int\~3) (DELAY (ABSOLUTE - (PORT datab (1365:1365:1365) (1505:1505:1505)) - (PORT datac (2335:2335:2335) (2467:2467:2467)) - (PORT datad (554:554:554) (564:564:564)) - (IOPATH datab combout (304:304:304) (311:311:311)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (1731:1731:1731) (1846:1846:1846)) + (PORT datab (1069:1069:1069) (1116:1116:1116)) + (PORT datad (438:438:438) (506:506:506)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -50198,10 +50008,10 @@ (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_16) (DELAY (ABSOLUTE - (PORT clk (1535:1535:1535) (1551:1551:1551)) + (PORT clk (1523:1523:1523) (1537:1537:1537)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1591:1591:1591) (1566:1566:1566)) - (PORT ena (1291:1291:1291) (1310:1310:1310)) + (PORT clrn (1567:1567:1567) (1548:1548:1548)) + (PORT ena (1722:1722:1722) (1695:1695:1695)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50216,7 +50026,7 @@ (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_17\~feeder) (DELAY (ABSOLUTE - (PORT datad (242:242:242) (312:312:312)) + (PORT datad (678:678:678) (728:728:728)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -50226,10 +50036,10 @@ (INSTANCE z80_\|memory_ifc_\|SYNTHESIZED_WIRE_17) (DELAY (ABSOLUTE - (PORT clk (1542:1542:1542) (1544:1544:1544)) + (PORT clk (1541:1541:1541) (1540:1540:1540)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1591:1591:1591) (1566:1566:1566)) - (PORT ena (1321:1321:1321) (1347:1347:1347)) + (PORT clrn (1578:1578:1578) (1557:1557:1557)) + (PORT ena (1434:1434:1434) (1415:1415:1415)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50244,10 +50054,10 @@ (INSTANCE z80_\|memory_ifc_\|DFFE_mreq_ff2) (DELAY (ABSOLUTE - (PORT clk (1542:1542:1542) (1544:1544:1544)) - (PORT asdata (565:565:565) (644:644:644)) - (PORT clrn (1591:1591:1591) (1566:1566:1566)) - (PORT ena (1321:1321:1321) (1347:1347:1347)) + (PORT clk (1541:1541:1541) (1540:1540:1540)) + (PORT asdata (567:567:567) (645:645:645)) + (PORT clrn (1578:1578:1578) (1557:1557:1557)) + (PORT ena (1434:1434:1434) (1415:1415:1415)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50262,9 +50072,9 @@ (INSTANCE z80_\|memory_ifc_\|nMREQ_out\~0) (DELAY (ABSOLUTE - (PORT dataa (251:251:251) (340:340:340)) - (PORT datab (251:251:251) (335:335:335)) - (PORT datad (216:216:216) (283:283:283)) + (PORT dataa (253:253:253) (343:343:343)) + (PORT datab (250:250:250) (336:336:336)) + (PORT datad (217:217:217) (286:286:286)) (IOPATH dataa combout (354:354:354) (349:349:349)) (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -50277,9 +50087,9 @@ (INSTANCE z80_\|memory_ifc_\|nMREQ_out\~1) (DELAY (ABSOLUTE - (PORT dataa (912:912:912) (985:985:985)) - (PORT datab (200:200:200) (240:240:240)) - (PORT datad (182:182:182) (211:211:211)) + (PORT dataa (261:261:261) (353:353:353)) + (PORT datab (220:220:220) (260:260:260)) + (PORT datad (174:174:174) (199:199:199)) (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -50310,9 +50120,9 @@ (INSTANCE ula_\|i2c_loader_\|divider\[0\]) (DELAY (ABSOLUTE - (PORT clk (1910:1910:1910) (1908:1908:1908)) + (PORT clk (1911:1911:1911) (1909:1909:1909)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) + (PORT clrn (1565:1565:1565) (1557:1557:1557)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50326,8 +50136,8 @@ (INSTANCE ula_\|i2c_loader_\|divider\[1\]\~5) (DELAY (ABSOLUTE - (PORT dataa (253:253:253) (345:345:345)) - (PORT datab (251:251:251) (337:337:337)) + (PORT dataa (255:255:255) (347:347:347)) + (PORT datab (249:249:249) (334:334:334)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datab combout (344:344:344) (369:369:369)) @@ -50341,9 +50151,9 @@ (INSTANCE ula_\|i2c_loader_\|divider\[1\]) (DELAY (ABSOLUTE - (PORT clk (1910:1910:1910) (1908:1908:1908)) + (PORT clk (1911:1911:1911) (1909:1909:1909)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) + (PORT clrn (1565:1565:1565) (1557:1557:1557)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50357,9 +50167,9 @@ (INSTANCE ula_\|i2c_loader_\|divider\[2\]\~7) (DELAY (ABSOLUTE - (PORT dataa (253:253:253) (343:343:343)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (249:249:249) (333:333:333)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -50371,9 +50181,9 @@ (INSTANCE ula_\|i2c_loader_\|divider\[2\]) (DELAY (ABSOLUTE - (PORT clk (1910:1910:1910) (1908:1908:1908)) + (PORT clk (1911:1911:1911) (1909:1909:1909)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) + (PORT clrn (1565:1565:1565) (1557:1557:1557)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50387,7 +50197,7 @@ (INSTANCE ula_\|i2c_loader_\|divider\[3\]\~9) (DELAY (ABSOLUTE - (PORT datab (252:252:252) (338:338:338)) + (PORT datab (250:250:250) (335:335:335)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -50401,66 +50211,9 @@ (INSTANCE ula_\|i2c_loader_\|divider\[3\]) (DELAY (ABSOLUTE - (PORT clk (1910:1910:1910) (1908:1908:1908)) + (PORT clk (1911:1911:1911) (1909:1909:1909)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|divider\[4\]\~11) - (DELAY - (ABSOLUTE - (PORT datab (251:251:251) (337:337:337)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datab cout (446:446:446) (318:318:318)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|divider\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1910:1910:1910) (1908:1908:1908)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|divider\[5\]\~13) - (DELAY - (ABSOLUTE - (PORT datad (226:226:226) (299:299:299)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|divider\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1910:1910:1910) (1908:1908:1908)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1571:1571:1571)) + (PORT clrn (1565:1565:1565) (1557:1557:1557)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50474,9 +50227,9 @@ (INSTANCE ula_\|i2c_loader_\|WideAnd0\~0) (DELAY (ABSOLUTE - (PORT dataa (253:253:253) (343:343:343)) - (PORT datab (253:253:253) (339:339:339)) - (PORT datac (223:223:223) (302:302:302)) + (PORT dataa (254:254:254) (346:346:346)) + (PORT datab (251:251:251) (336:336:336)) + (PORT datac (223:223:223) (304:304:304)) (PORT datad (225:225:225) (297:297:297)) (IOPATH dataa combout (324:324:324) (328:328:328)) (IOPATH datab combout (333:333:333) (332:332:332)) @@ -50485,16 +50238,73 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|divider\[4\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (251:251:251) (341:341:341)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|divider\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1911:1911:1911) (1909:1909:1909)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1565:1565:1565) (1557:1557:1557)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|divider\[5\]\~13) + (DELAY + (ABSOLUTE + (PORT datab (252:252:252) (338:338:338)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH cin combout (455:455:455) (437:437:437)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|divider\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1911:1911:1911) (1909:1909:1909)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1565:1565:1565) (1557:1557:1557)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2c_loader_\|WideAnd0) (DELAY (ABSOLUTE - (PORT datab (250:250:250) (334:334:334)) - (PORT datac (173:173:173) (206:206:206)) - (PORT datad (225:225:225) (296:296:296)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (202:202:202) (247:247:247)) + (PORT datac (225:225:225) (306:306:306)) + (PORT datad (227:227:227) (301:301:301)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -50504,10 +50314,10 @@ (INSTANCE ula_\|i2c_loader_\|state\.Idle) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1547:1547:1547)) + (PORT clk (1532:1532:1532) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1575:1575:1575)) - (PORT ena (1428:1428:1428) (1403:1403:1403)) + (PORT clrn (1566:1566:1566) (1559:1559:1559)) + (PORT ena (1477:1477:1477) (1441:1441:1441)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50522,7 +50332,7 @@ (INSTANCE ula_\|i2c_loader_\|phase\~0) (DELAY (ABSOLUTE - (PORT datad (245:245:245) (317:317:317)) + (PORT datad (271:271:271) (351:351:351)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -50533,10 +50343,10 @@ (INSTANCE ula_\|i2c_loader_\|phase\[0\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1547:1547:1547)) + (PORT clk (1532:1532:1532) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1575:1575:1575)) - (PORT ena (1428:1428:1428) (1403:1403:1403)) + (PORT clrn (1566:1566:1566) (1559:1559:1559)) + (PORT ena (1477:1477:1477) (1441:1441:1441)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50551,8 +50361,8 @@ (INSTANCE ula_\|i2c_loader_\|phase\~1) (DELAY (ABSOLUTE - (PORT datab (333:333:333) (440:440:440)) - (PORT datad (247:247:247) (319:319:319)) + (PORT datab (280:280:280) (369:369:369)) + (PORT datad (271:271:271) (351:351:351)) (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -50564,10 +50374,10 @@ (INSTANCE ula_\|i2c_loader_\|phase\[1\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1547:1547:1547)) + (PORT clk (1532:1532:1532) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1575:1575:1575)) - (PORT ena (1428:1428:1428) (1403:1403:1403)) + (PORT clrn (1566:1566:1566) (1559:1559:1559)) + (PORT ena (1477:1477:1477) (1441:1441:1441)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50582,20 +50392,24 @@ (INSTANCE ula_\|i2c_loader_\|nbit\~5) (DELAY (ABSOLUTE - (PORT dataa (636:636:636) (709:709:709)) - (IOPATH dataa combout (356:356:356) (368:368:368)) + (PORT datad (666:666:666) (722:722:722)) (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|thisbyte\[0\]\~8) + (INSTANCE ula_\|i2c_loader_\|state\.Idle\~0) (DELAY (ABSOLUTE - (PORT datab (307:307:307) (404:404:404)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (274:274:274) (365:365:365)) + (PORT datab (279:279:279) (367:367:367)) + (PORT datac (587:587:587) (646:646:646)) + (PORT datad (403:403:403) (461:461:461)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -50605,21 +50419,131 @@ (INSTANCE ula_\|i2c_loader_\|Mux42\~0) (DELAY (ABSOLUTE - (PORT datac (700:700:700) (774:774:774)) - (PORT datad (677:677:677) (746:746:746)) + (PORT datab (632:632:632) (708:708:708)) + (PORT datac (647:647:647) (712:712:712)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbit\~6) + (DELAY + (ABSOLUTE + (PORT datab (703:703:703) (762:762:762)) + (PORT datad (241:241:241) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|nbit\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1530:1530:1530) (1544:1544:1544)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1564:1564:1564) (1557:1557:1557)) + (PORT ena (972:972:972) (970:970:970)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Done\~0) + (DELAY + (ABSOLUTE + (PORT dataa (254:254:254) (345:345:345)) + (PORT datab (271:271:271) (362:362:362)) + (PORT datac (838:838:838) (903:903:903)) + (PORT datad (235:235:235) (311:311:311)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Ack\~0) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (373:373:373)) + (PORT datab (400:400:400) (435:435:435)) + (PORT datac (352:352:352) (376:376:376)) + (PORT datad (407:407:407) (476:476:476)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Ack\~1) + (DELAY + (ABSOLUTE + (PORT dataa (642:642:642) (658:658:658)) + (PORT datab (624:624:624) (689:689:689)) + (PORT datad (174:174:174) (198:198:198)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|state\.Ack) + (DELAY + (ABSOLUTE + (PORT clk (1902:1902:1902) (1931:1931:1931)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1566:1566:1566) (1559:1559:1559)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (659:659:659) (724:724:724)) + (PORT datab (596:596:596) (661:661:661)) + (PORT datac (639:639:639) (701:701:701)) + (PORT datad (257:257:257) (336:336:336)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2c_loader_\|nbyte\~4) (DELAY (ABSOLUTE - (PORT dataa (286:286:286) (381:381:381)) - (PORT datab (336:336:336) (443:443:443)) - (PORT datad (634:634:634) (704:704:704)) + (PORT dataa (783:783:783) (830:830:830)) + (PORT datab (489:489:489) (568:568:568)) + (PORT datad (445:445:445) (512:512:512)) (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (355:355:355) (349:349:349)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -50632,8 +50556,8 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[0\]\~7) (DELAY (ABSOLUTE - (PORT datab (290:290:290) (381:381:381)) - (PORT datac (578:578:578) (623:623:623)) + (PORT datab (597:597:597) (658:658:658)) + (PORT datac (596:596:596) (666:666:666)) (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (243:243:243) (242:242:242)) ) @@ -50653,10 +50577,10 @@ (INSTANCE ula_\|i2c_loader_\|nbyte\[0\]\~1) (DELAY (ABSOLUTE - (PORT dataa (284:284:284) (379:379:379)) - (PORT datab (272:272:272) (359:359:359)) - (PORT datac (301:301:301) (403:403:403)) - (PORT datad (516:516:516) (513:513:513)) + (PORT dataa (291:291:291) (389:389:389)) + (PORT datab (291:291:291) (384:384:384)) + (PORT datac (453:453:453) (533:533:533)) + (PORT datad (690:690:690) (674:674:674)) (IOPATH dataa combout (341:341:341) (319:319:319)) (IOPATH datab combout (342:342:342) (318:318:318)) (IOPATH datac combout (243:243:243) (241:241:241)) @@ -50669,10 +50593,10 @@ (INSTANCE ula_\|i2c_loader_\|nbyte\[0\]\~2) (DELAY (ABSOLUTE - (PORT dataa (662:662:662) (747:747:747)) - (PORT datab (653:653:653) (670:670:670)) - (PORT datac (172:172:172) (206:206:206)) - (PORT datad (174:174:174) (200:200:200)) + (PORT dataa (618:618:618) (686:686:686)) + (PORT datab (399:399:399) (439:439:439)) + (PORT datac (305:305:305) (329:329:329)) + (PORT datad (175:175:175) (202:202:202)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -50685,11 +50609,11 @@ (INSTANCE ula_\|i2c_loader_\|nbyte\[0\]\~3) (DELAY (ABSOLUTE - (PORT datab (835:835:835) (857:857:857)) - (PORT datac (423:423:423) (492:492:492)) - (PORT datad (174:174:174) (198:198:198)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT datab (437:437:437) (516:516:516)) + (PORT datac (619:619:619) (636:636:636)) + (PORT datad (174:174:174) (199:199:199)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -50699,9 +50623,9 @@ (INSTANCE ula_\|i2c_loader_\|nbyte\[1\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1547:1547:1547)) + (PORT clk (1532:1532:1532) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1575:1575:1575)) + (PORT clrn (1566:1566:1566) (1559:1559:1559)) (PORT ena (820:820:820) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) @@ -50714,63 +50638,66 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Stop\~0) + (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~1) (DELAY (ABSOLUTE - (PORT dataa (677:677:677) (755:755:755)) - (PORT datab (713:713:713) (770:770:770)) - (PORT datac (253:253:253) (337:337:337)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (289:289:289) (384:384:384)) + (PORT datab (291:291:291) (384:384:384)) + (PORT datac (593:593:593) (653:653:653)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Stop\~1) + (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~3) (DELAY (ABSOLUTE - (PORT dataa (596:596:596) (620:620:620)) - (PORT datab (263:263:263) (314:314:314)) - (PORT datad (341:341:341) (360:360:360)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (353:353:353) (369:369:369)) + (PORT dataa (378:378:378) (400:400:400)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (352:352:352) (377:377:377)) + (PORT datad (443:443:443) (511:511:511)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (204:204:204) (249:249:249)) + (PORT datab (404:404:404) (441:441:441)) + (PORT datac (622:622:622) (637:637:637)) + (PORT datad (411:411:411) (481:481:481)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|state\.Stop) + (INSTANCE ula_\|i2c_loader_\|nbit\[0\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT clk (1902:1902:1902) (1930:1930:1930)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) + (PORT clrn (1564:1564:1564) (1557:1557:1557)) + (PORT ena (943:943:943) (928:928:928)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) ) (TIMINGCHECK (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Idle\~0) - (DELAY - (ABSOLUTE - (PORT dataa (291:291:291) (389:389:389)) - (PORT datab (261:261:261) (350:350:350)) - (PORT datac (232:232:232) (318:318:318)) - (PORT datad (567:567:567) (616:616:616)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) + (HOLD ena (posedge clk) (157:157:157)) ) ) (CELL @@ -50778,9 +50705,9 @@ (INSTANCE ula_\|i2c_loader_\|nbit\~0) (DELAY (ABSOLUTE - (PORT dataa (637:637:637) (710:710:710)) - (PORT datab (267:267:267) (356:356:356)) - (PORT datad (234:234:234) (311:311:311)) + (PORT dataa (870:870:870) (945:945:945)) + (PORT datab (269:269:269) (361:361:361)) + (PORT datad (232:232:232) (308:308:308)) (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -50795,8 +50722,8 @@ (ABSOLUTE (PORT clk (1530:1530:1530) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1572:1572:1572)) - (PORT ena (1191:1191:1191) (1184:1184:1184)) + (PORT clrn (1564:1564:1564) (1557:1557:1557)) + (PORT ena (972:972:972) (970:970:970)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50808,46 +50735,68 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Done\~0) + (INSTANCE ula_\|i2c_loader_\|state\.Done\~1) (DELAY (ABSOLUTE - (PORT dataa (259:259:259) (351:351:351)) - (PORT datab (249:249:249) (335:335:335)) - (PORT datac (602:602:602) (665:665:665)) - (PORT datad (238:238:238) (316:316:316)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (254:254:254) (343:343:343)) + (PORT datab (270:270:270) (362:362:362)) + (PORT datad (235:235:235) (311:311:311)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Ack\~0) + (INSTANCE ula_\|i2c_loader_\|state\~27) (DELAY (ABSOLUTE - (PORT dataa (361:361:361) (399:399:399)) - (PORT datab (370:370:370) (392:392:392)) - (PORT datac (920:920:920) (977:977:977)) - (PORT datad (327:327:327) (351:351:351)) - (IOPATH dataa combout (341:341:341) (319:319:319)) + (PORT dataa (663:663:663) (729:729:729)) + (PORT datab (677:677:677) (747:747:747)) + (PORT datac (599:599:599) (616:616:616)) + (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (241:241:241) (241:241:241)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\~24) + (DELAY + (ABSOLUTE + (PORT datab (289:289:289) (381:381:381)) + (PORT datac (259:259:259) (350:350:350)) + (PORT datad (253:253:253) (329:329:329)) + (IOPATH datab combout (304:304:304) (311:311:311)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Ack\~1) + (INSTANCE ula_\|i2c_loader_\|state\~26) (DELAY (ABSOLUTE - (PORT dataa (203:203:203) (247:247:247)) - (PORT datab (562:562:562) (591:591:591)) - (PORT datad (443:443:443) (515:515:515)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (336:336:336) (342:342:342)) + (PORT datab (483:483:483) (561:561:561)) + (PORT datac (195:195:195) (228:228:228)) + (PORT datad (395:395:395) (460:460:460)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Data\~0) + (DELAY + (ABSOLUTE + (PORT datab (201:201:201) (241:241:241)) + (PORT datad (319:319:319) (339:339:339)) + (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -50855,18 +50804,68 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|state\.Ack) + (INSTANCE ula_\|i2c_loader_\|state\.Data) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1544:1544:1544)) + (PORT clk (1532:1532:1532) (1547:1547:1547)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1572:1572:1572)) + (PORT asdata (549:549:549) (584:584:584)) + (PORT clrn (1566:1566:1566) (1560:1560:1560)) + (PORT sload (1221:1221:1221) (1323:1323:1323)) + (PORT ena (1246:1246:1246) (1213:1213:1213)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) ) (TIMINGCHECK (HOLD d (posedge clk) (157:157:157)) + (HOLD sload (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Done\~2) + (DELAY + (ABSOLUTE + (PORT dataa (218:218:218) (271:271:271)) + (PORT datab (289:289:289) (380:380:380)) + (PORT datac (599:599:599) (615:615:615)) + (PORT datad (238:238:238) (307:307:307)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|state\.Pause\~1) + (DELAY + (ABSOLUTE + (PORT dataa (637:637:637) (713:713:713)) + (PORT datab (200:200:200) (240:240:240)) + (PORT datac (204:204:204) (242:242:242)) + (PORT datad (568:568:568) (620:620:620)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|thisbyte\[0\]\~8) + (DELAY + (ABSOLUTE + (PORT datab (287:287:287) (377:377:377)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) ) ) (CELL @@ -50874,13 +50873,13 @@ (INSTANCE ula_\|i2c_loader_\|nbyte\[1\]\~5) (DELAY (ABSOLUTE - (PORT dataa (285:285:285) (380:380:380)) - (PORT datab (272:272:272) (356:356:356)) - (PORT datac (302:302:302) (404:404:404)) - (PORT datad (517:517:517) (510:510:510)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (687:687:687) (747:747:747)) + (PORT datab (612:612:612) (670:670:670)) + (PORT datac (567:567:567) (618:618:618)) + (PORT datad (713:713:713) (698:698:698)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -50890,10 +50889,10 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[0\]\~18) (DELAY (ABSOLUTE - (PORT dataa (416:416:416) (489:489:489)) - (PORT datab (587:587:587) (640:640:640)) - (PORT datac (850:850:850) (859:859:859)) - (PORT datad (309:309:309) (325:325:325)) + (PORT dataa (601:601:601) (660:660:660)) + (PORT datab (610:610:610) (670:670:670)) + (PORT datac (831:831:831) (829:829:829)) + (PORT datad (175:175:175) (201:201:201)) (IOPATH dataa combout (300:300:300) (308:308:308)) (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -50906,12 +50905,12 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[0\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1546:1546:1546)) + (PORT clk (1898:1898:1898) (1914:1914:1914)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (1124:1124:1124) (1148:1148:1148)) - (PORT clrn (1579:1579:1579) (1574:1574:1574)) - (PORT sload (1067:1067:1067) (1036:1036:1036)) - (PORT ena (794:794:794) (792:792:792)) + (PORT asdata (1879:1879:1879) (2003:2003:2003)) + (PORT clrn (1565:1565:1565) (1559:1559:1559)) + (PORT sload (1322:1322:1322) (1292:1292:1292)) + (PORT ena (820:820:820) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50928,7 +50927,7 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[1\]\~10) (DELAY (ABSOLUTE - (PORT datab (297:297:297) (392:392:392)) + (PORT datab (281:281:281) (370:370:370)) (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -50942,12 +50941,12 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[1\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1546:1546:1546)) + (PORT clk (1898:1898:1898) (1914:1914:1914)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (1125:1125:1125) (1149:1149:1149)) - (PORT clrn (1579:1579:1579) (1574:1574:1574)) - (PORT sload (1067:1067:1067) (1036:1036:1036)) - (PORT ena (794:794:794) (792:792:792)) + (PORT asdata (1879:1879:1879) (2004:2004:2004)) + (PORT clrn (1565:1565:1565) (1559:1559:1559)) + (PORT sload (1322:1322:1322) (1292:1292:1292)) + (PORT ena (820:820:820) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50964,9 +50963,9 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[2\]\~12) (DELAY (ABSOLUTE - (PORT datab (288:288:288) (380:380:380)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (289:289:289) (389:389:389)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -50978,11 +50977,11 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[2\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1546:1546:1546)) + (PORT clk (1898:1898:1898) (1914:1914:1914)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1574:1574:1574)) - (PORT sload (1067:1067:1067) (1036:1036:1036)) - (PORT ena (794:794:794) (792:792:792)) + (PORT clrn (1565:1565:1565) (1559:1559:1559)) + (PORT sload (1322:1322:1322) (1292:1292:1292)) + (PORT ena (820:820:820) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -50999,7 +50998,7 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[3\]\~14) (DELAY (ABSOLUTE - (PORT datab (306:306:306) (403:403:403)) + (PORT datab (286:286:286) (378:378:378)) (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -51013,12 +51012,12 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[3\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1546:1546:1546)) + (PORT clk (1898:1898:1898) (1914:1914:1914)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (1125:1125:1125) (1150:1150:1150)) - (PORT clrn (1579:1579:1579) (1574:1574:1574)) - (PORT sload (1067:1067:1067) (1036:1036:1036)) - (PORT ena (794:794:794) (792:792:792)) + (PORT asdata (1880:1880:1880) (2004:2004:2004)) + (PORT clrn (1565:1565:1565) (1559:1559:1559)) + (PORT sload (1322:1322:1322) (1292:1292:1292)) + (PORT ena (820:820:820) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -51035,10 +51034,10 @@ (INSTANCE ula_\|i2c_loader_\|Equal2\~0) (DELAY (ABSOLUTE - (PORT dataa (426:426:426) (508:508:508)) - (PORT datab (298:298:298) (392:392:392)) - (PORT datac (277:277:277) (365:365:365)) - (PORT datad (279:279:279) (363:363:363)) + (PORT dataa (647:647:647) (713:713:713)) + (PORT datab (659:659:659) (718:718:718)) + (PORT datac (408:408:408) (480:480:480)) + (PORT datad (449:449:449) (524:524:524)) (IOPATH dataa combout (354:354:354) (349:349:349)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -51046,28 +51045,12 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Pause\~0) - (DELAY - (ABSOLUTE - (PORT dataa (710:710:710) (798:798:798)) - (PORT datab (261:261:261) (350:350:350)) - (PORT datac (704:704:704) (778:778:778)) - (PORT datad (260:260:260) (337:337:337)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2c_loader_\|thisbyte\[4\]\~16) (DELAY (ABSOLUTE - (PORT dataa (308:308:308) (413:413:413)) + (PORT dataa (292:292:292) (385:385:385)) (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH cin combout (455:455:455) (437:437:437)) ) @@ -51078,11 +51061,11 @@ (INSTANCE ula_\|i2c_loader_\|thisbyte\[4\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1546:1546:1546)) + (PORT clk (1898:1898:1898) (1914:1914:1914)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1574:1574:1574)) - (PORT sload (1067:1067:1067) (1036:1036:1036)) - (PORT ena (794:794:794) (792:792:792)) + (PORT clrn (1565:1565:1565) (1559:1559:1559)) + (PORT sload (1322:1322:1322) (1292:1292:1292)) + (PORT ena (820:820:820) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -51096,30 +51079,28 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Pause\~1) + (INSTANCE ula_\|i2c_loader_\|Equal2\~1) (DELAY (ABSOLUTE - (PORT datab (622:622:622) (640:640:640)) - (PORT datac (335:335:335) (357:357:357)) - (PORT datad (658:658:658) (710:710:710)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT datac (174:174:174) (208:208:208)) + (PORT datad (415:415:415) (482:482:482)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Done\~2) + (INSTANCE ula_\|i2c_loader_\|state\.Pause\~0) (DELAY (ABSOLUTE - (PORT dataa (223:223:223) (267:267:267)) - (PORT datab (286:286:286) (376:376:376)) - (PORT datac (231:231:231) (314:314:314)) - (PORT datad (487:487:487) (489:489:489)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (275:275:275) (366:366:366)) + (PORT datab (396:396:396) (434:434:434)) + (PORT datac (594:594:594) (654:654:654)) + (PORT datad (536:536:536) (550:550:550)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -51129,27 +51110,11 @@ (INSTANCE ula_\|i2c_loader_\|state\.Pause\~2) (DELAY (ABSOLUTE - (PORT dataa (345:345:345) (374:374:374)) - (PORT datab (266:266:266) (320:320:320)) - (PORT datac (261:261:261) (352:352:352)) - (PORT datad (421:421:421) (491:491:491)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (306:306:306) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Pause\~3) - (DELAY - (ABSOLUTE - (PORT dataa (343:343:343) (380:380:380)) - (PORT datab (590:590:590) (613:613:613)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) + (PORT dataa (202:202:202) (245:245:245)) + (PORT datab (644:644:644) (668:668:668)) + (PORT datad (337:337:337) (357:357:357)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (336:336:336) (342:342:342)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -51160,9 +51125,9 @@ (INSTANCE ula_\|i2c_loader_\|state\.Pause) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT clk (1532:1532:1532) (1547:1547:1547)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) + (PORT clrn (1566:1566:1566) (1560:1560:1560)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -51176,9 +51141,9 @@ (INSTANCE ula_\|i2c_loader_\|state\~25) (DELAY (ABSOLUTE - (PORT dataa (264:264:264) (356:356:356)) - (PORT datab (267:267:267) (321:321:321)) - (PORT datad (419:419:419) (488:488:488)) + (PORT dataa (593:593:593) (651:651:651)) + (PORT datab (580:580:580) (597:597:597)) + (PORT datad (262:262:262) (341:341:341)) (IOPATH dataa combout (300:300:300) (308:308:308)) (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -51191,10 +51156,10 @@ (INSTANCE ula_\|i2c_loader_\|state\.Start) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT clk (1532:1532:1532) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (PORT ena (1192:1192:1192) (1154:1154:1154)) + (PORT clrn (1566:1566:1566) (1559:1559:1559)) + (PORT ena (1477:1477:1477) (1441:1441:1441)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -51209,8 +51174,8 @@ (INSTANCE ula_\|i2c_loader_\|nbyte\~0) (DELAY (ABSOLUTE - (PORT datab (330:330:330) (437:437:437)) - (PORT datad (630:630:630) (700:700:700)) + (PORT datab (485:485:485) (562:562:562)) + (PORT datad (449:449:449) (514:514:514)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -51222,9 +51187,9 @@ (INSTANCE ula_\|i2c_loader_\|nbyte\[0\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1547:1547:1547)) + (PORT clk (1532:1532:1532) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1575:1575:1575)) + (PORT clrn (1566:1566:1566) (1559:1559:1559)) (PORT ena (820:820:820) (825:825:825)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) @@ -51237,13 +51202,13 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~1) + (INSTANCE ula_\|i2c_loader_\|state\.Stop\~0) (DELAY (ABSOLUTE - (PORT dataa (678:678:678) (749:749:749)) - (PORT datac (684:684:684) (733:733:733)) - (PORT datad (441:441:441) (514:514:514)) - (IOPATH dataa combout (371:371:371) (376:376:376)) + (PORT datab (290:290:290) (382:382:382)) + (PORT datac (262:262:262) (352:352:352)) + (PORT datad (255:255:255) (331:331:331)) + (IOPATH datab combout (336:336:336) (325:325:325)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -51251,78 +51216,14 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~2) + (INSTANCE ula_\|i2c_loader_\|state\.Stop\~1) (DELAY (ABSOLUTE - (PORT dataa (1033:1033:1033) (1086:1086:1086)) - (PORT datab (486:486:486) (561:561:561)) - (PORT datac (255:255:255) (338:338:338)) - (PORT datad (669:669:669) (726:726:726)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (198:198:198) (237:237:237)) - (PORT datac (590:590:590) (648:648:648)) - (PORT datad (326:326:326) (348:348:348)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\[0\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (348:348:348) (387:387:387)) - (PORT datab (262:262:262) (314:314:314)) - (PORT datac (556:556:556) (578:578:578)) - (PORT datad (424:424:424) (491:491:491)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|nbit\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1900:1900:1900) (1919:1919:1919)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1572:1572:1572)) - (PORT ena (1160:1160:1160) (1135:1135:1135)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|nbit\~6) - (DELAY - (ABSOLUTE - (PORT dataa (634:634:634) (707:707:707)) - (PORT datad (241:241:241) (319:319:319)) - (IOPATH dataa combout (356:356:356) (368:368:368)) + (PORT dataa (202:202:202) (245:245:245)) + (PORT datab (649:649:649) (669:669:669)) + (PORT datad (376:376:376) (396:396:396)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (336:336:336) (325:325:325)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -51330,111 +51231,18 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|nbit\[1\]) + (INSTANCE ula_\|i2c_loader_\|state\.Stop) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1544:1544:1544)) + (PORT clk (1902:1902:1902) (1931:1931:1931)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1572:1572:1572)) - (PORT ena (1191:1191:1191) (1184:1184:1184)) + (PORT clrn (1566:1566:1566) (1559:1559:1559)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) ) (TIMINGCHECK (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Done\~1) - (DELAY - (ABSOLUTE - (PORT dataa (260:260:260) (355:355:355)) - (PORT datab (252:252:252) (338:338:338)) - (PORT datad (241:241:241) (319:319:319)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\~27) - (DELAY - (ABSOLUTE - (PORT dataa (707:707:707) (793:793:793)) - (PORT datac (701:701:701) (775:775:775)) - (PORT datad (486:486:486) (488:488:488)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\~24) - (DELAY - (ABSOLUTE - (PORT dataa (677:677:677) (753:753:753)) - (PORT datab (714:714:714) (770:770:770)) - (PORT datac (251:251:251) (332:332:332)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (342:342:342) (318:318:318)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\~26) - (DELAY - (ABSOLUTE - (PORT dataa (710:710:710) (798:798:798)) - (PORT datac (702:702:702) (777:777:777)) - (PORT datad (347:347:347) (368:368:368)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|state\.Data\~0) - (DELAY - (ABSOLUTE - (PORT dataa (203:203:203) (248:248:248)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|state\.Data) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (PORT asdata (578:578:578) (625:625:625)) - (PORT clrn (1578:1578:1578) (1572:1572:1572)) - (PORT sload (875:875:875) (1003:1003:1003)) - (PORT ena (1192:1192:1192) (1154:1154:1154)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD sload (posedge clk) (157:157:157)) - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) ) ) (CELL @@ -51442,11 +51250,11 @@ (INSTANCE ula_\|i2c_loader_\|scl_out\~0) (DELAY (ABSOLUTE - (PORT datab (288:288:288) (379:379:379)) - (PORT datac (607:607:607) (657:657:657)) - (PORT datad (233:233:233) (310:310:310)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (413:413:413) (490:490:490)) + (PORT datab (290:290:290) (381:381:381)) + (PORT datad (565:565:565) (619:619:619)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -51458,8 +51266,8 @@ (ABSOLUTE (PORT clk (1532:1532:1532) (1547:1547:1547)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1575:1575:1575)) - (PORT ena (1428:1428:1428) (1403:1403:1403)) + (PORT clrn (1566:1566:1566) (1560:1560:1560)) + (PORT ena (1246:1246:1246) (1213:1213:1213)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -51474,10 +51282,10 @@ (INSTANCE ula_\|i2c_loader_\|scl_out\~1) (DELAY (ABSOLUTE - (PORT dataa (661:661:661) (746:746:746)) - (PORT datab (330:330:330) (435:435:435)) - (PORT datac (260:260:260) (348:348:348)) - (PORT datad (218:218:218) (287:287:287)) + (PORT dataa (640:640:640) (713:713:713)) + (PORT datab (673:673:673) (740:740:740)) + (PORT datac (597:597:597) (666:666:666)) + (PORT datad (217:217:217) (285:285:285)) (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (242:242:242)) @@ -51490,12 +51298,12 @@ (INSTANCE ula_\|i2c_loader_\|scl_out\~2) (DELAY (ABSOLUTE - (PORT dataa (650:650:650) (670:670:670)) - (PORT datab (200:200:200) (240:240:240)) - (PORT datad (630:630:630) (699:699:699)) + (PORT dataa (218:218:218) (270:270:270)) + (PORT datab (199:199:199) (237:237:237)) + (PORT datac (609:609:609) (674:674:674)) (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH datac combout (243:243:243) (242:242:242)) ) ) ) @@ -51505,9 +51313,9 @@ (DELAY (ABSOLUTE (PORT clk (1473:1473:1473) (1495:1495:1495)) - (PORT d (958:958:958) (1002:1002:1002)) - (PORT aload (1710:1710:1710) (1775:1775:1775)) - (PORT ena (885:885:885) (884:884:884)) + (PORT d (960:960:960) (1004:1004:1004)) + (PORT aload (1697:1697:1697) (1760:1760:1760)) + (PORT ena (697:697:697) (696:696:696)) (IOPATH (posedge clk) q (617:617:617) (612:612:612)) (IOPATH (posedge aload) q (513:513:513) (508:508:508)) ) @@ -51526,8 +51334,8 @@ (ABSOLUTE (PORT clk (1532:1532:1532) (1547:1547:1547)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1575:1575:1575)) - (PORT ena (1428:1428:1428) (1403:1403:1403)) + (PORT clrn (1566:1566:1566) (1560:1560:1560)) + (PORT ena (1246:1246:1246) (1213:1213:1213)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -51542,10 +51350,10 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\~4) (DELAY (ABSOLUTE - (PORT datac (887:887:887) (940:940:940)) - (PORT datad (610:610:610) (673:673:673)) + (PORT dataa (496:496:496) (561:561:561)) + (PORT datac (640:640:640) (708:708:708)) + (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -51554,10 +51362,10 @@ (INSTANCE ula_\|i2c_loader_\|Mux35\~0) (DELAY (ABSOLUTE - (PORT dataa (442:442:442) (520:520:520)) - (PORT datab (457:457:457) (520:520:520)) - (PORT datac (391:391:391) (449:449:449)) - (PORT datad (395:395:395) (456:456:456)) + (PORT dataa (646:646:646) (716:716:716)) + (PORT datab (654:654:654) (720:720:720)) + (PORT datac (405:405:405) (482:482:482)) + (PORT datad (446:446:446) (528:528:528)) (IOPATH dataa combout (304:304:304) (308:308:308)) (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -51570,26 +51378,10 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\~13) (DELAY (ABSOLUTE - (PORT dataa (306:306:306) (409:409:409)) - (PORT datab (298:298:298) (389:389:389)) - (PORT datac (278:278:278) (370:370:370)) - (PORT datad (262:262:262) (338:338:338)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~14) - (DELAY - (ABSOLUTE - (PORT datac (274:274:274) (369:369:369)) - (PORT datad (260:260:260) (337:337:337)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT dataa (291:291:291) (392:392:392)) + (PORT datac (262:262:262) (350:350:350)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) ) ) ) @@ -51598,12 +51390,92 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\~15) (DELAY (ABSOLUTE - (PORT dataa (203:203:203) (248:248:248)) - (PORT datab (307:307:307) (404:404:404)) - (PORT datac (278:278:278) (370:370:370)) - (PORT datad (198:198:198) (224:224:224)) + (PORT dataa (289:289:289) (389:389:389)) + (PORT datab (280:280:280) (368:368:368)) + (PORT datac (259:259:259) (348:348:348)) + (PORT datad (262:262:262) (342:342:342)) (IOPATH dataa combout (354:354:354) (367:367:367)) (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~16) + (DELAY + (ABSOLUTE + (PORT dataa (210:210:210) (260:260:260)) + (PORT datab (291:291:291) (383:383:383)) + (PORT datac (173:173:173) (207:207:207)) + (PORT datad (262:262:262) (342:342:342)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (355:355:355) (349:349:349)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~17) + (DELAY + (ABSOLUTE + (PORT dataa (601:601:601) (671:671:671)) + (PORT datab (483:483:483) (567:567:567)) + (PORT datac (405:405:405) (482:482:482)) + (PORT datad (617:617:617) (682:682:682)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~18) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (245:245:245)) + (PORT datab (447:447:447) (517:517:517)) + (PORT datac (520:520:520) (535:535:535)) + (PORT datad (446:446:446) (524:524:524)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (342:342:342) (332:332:332)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~20) + (DELAY + (ABSOLUTE + (PORT dataa (631:631:631) (694:694:694)) + (PORT datab (654:654:654) (720:720:720)) + (PORT datac (616:616:616) (676:676:676)) + (PORT datad (418:418:418) (485:485:485)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~21) + (DELAY + (ABSOLUTE + (PORT dataa (550:550:550) (573:573:573)) + (PORT datab (200:200:200) (238:238:238)) + (PORT datac (405:405:405) (480:480:480)) + (PORT datad (446:446:446) (524:524:524)) + (IOPATH dataa combout (341:341:341) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -51611,12 +51483,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~24) + (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~23) (DELAY (ABSOLUTE - (PORT datab (456:456:456) (520:520:520)) - (PORT datac (890:890:890) (943:943:943)) - (PORT datad (414:414:414) (478:478:478)) + (PORT datab (661:661:661) (726:726:726)) + (PORT datac (638:638:638) (705:705:705)) + (PORT datad (451:451:451) (531:531:531)) (IOPATH datab combout (336:336:336) (325:325:325)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -51628,10 +51500,12 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~6) (DELAY (ABSOLUTE - (PORT dataa (707:707:707) (795:795:795)) - (PORT datac (702:702:702) (777:777:777)) - (PORT datad (261:261:261) (341:341:341)) - (IOPATH dataa combout (324:324:324) (328:328:328)) + (PORT dataa (372:372:372) (404:404:404)) + (PORT datab (629:629:629) (692:692:692)) + (PORT datac (272:272:272) (355:355:355)) + (PORT datad (248:248:248) (320:320:320)) + (IOPATH dataa combout (303:303:303) (308:308:308)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -51642,26 +51516,12 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~7) (DELAY (ABSOLUTE - (PORT dataa (294:294:294) (393:393:393)) - (PORT datab (263:263:263) (313:313:313)) - (PORT datac (173:173:173) (205:205:205)) - (PORT datad (350:350:350) (370:370:370)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[0\]\~8) - (DELAY - (ABSOLUTE - (PORT datab (447:447:447) (530:530:530)) - (PORT datac (557:557:557) (581:581:581)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH datab combout (304:304:304) (311:311:311)) + (PORT dataa (203:203:203) (247:247:247)) + (PORT datab (281:281:281) (370:370:370)) + (PORT datac (817:817:817) (831:831:831)) + (PORT datad (269:269:269) (349:349:349)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -51674,9 +51534,9 @@ (ABSOLUTE (PORT clk (1532:1532:1532) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1574:1574:1574)) - (PORT sclr (1104:1104:1104) (1198:1198:1198)) - (PORT ena (1397:1397:1397) (1366:1366:1366)) + (PORT clrn (1566:1566:1566) (1559:1559:1559)) + (PORT sclr (948:948:948) (1050:1050:1050)) + (PORT ena (922:922:922) (904:904:904)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -51687,48 +51547,32 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~21) - (DELAY - (ABSOLUTE - (PORT dataa (305:305:305) (408:408:408)) - (PORT datab (305:305:305) (398:398:398)) - (PORT datac (278:278:278) (369:369:369)) - (PORT datad (262:262:262) (338:338:338)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2c_loader_\|shiftreg\~22) (DELAY (ABSOLUTE - (PORT dataa (374:374:374) (397:397:397)) - (PORT datab (373:373:373) (401:401:401)) - (PORT datac (390:390:390) (448:448:448)) - (PORT datad (413:413:413) (480:480:480)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (646:646:646) (716:716:716)) + (PORT datad (221:221:221) (291:291:291)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~23) + (INSTANCE ula_\|i2c_loader_\|shiftreg\[6\]\~9) (DELAY (ABSOLUTE - (PORT dataa (247:247:247) (334:334:334)) - (PORT datac (893:893:893) (946:946:946)) - (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (371:371:371) (403:403:403)) + (PORT datab (625:625:625) (687:687:687)) + (PORT datac (274:274:274) (360:360:360)) + (PORT datad (245:245:245) (317:317:317)) + (IOPATH dataa combout (303:303:303) (299:299:299)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -51738,29 +51582,13 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[6\]\~10) (DELAY (ABSOLUTE - (PORT dataa (712:712:712) (775:775:775)) - (PORT datab (482:482:482) (560:560:560)) - (PORT datac (588:588:588) (650:650:650)) - (PORT datad (197:197:197) (223:223:223)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[6\]\~11) - (DELAY - (ABSOLUTE - (PORT dataa (1032:1032:1032) (1083:1083:1083)) - (PORT datab (561:561:561) (587:587:587)) - (PORT datac (921:921:921) (976:976:976)) - (PORT datad (174:174:174) (200:200:200)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (201:201:201) (246:246:246)) + (PORT datab (282:282:282) (370:370:370)) + (PORT datac (817:817:817) (834:834:834)) + (PORT datad (269:269:269) (349:349:349)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -51772,8 +51600,8 @@ (ABSOLUTE (PORT clk (1532:1532:1532) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1574:1574:1574)) - (PORT ena (1207:1207:1207) (1188:1188:1188)) + (PORT clrn (1566:1566:1566) (1559:1559:1559)) + (PORT ena (1000:1000:1000) (1005:1005:1005)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -51783,49 +51611,17 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~18) - (DELAY - (ABSOLUTE - (PORT dataa (305:305:305) (410:410:410)) - (PORT datab (303:303:303) (399:399:399)) - (PORT datac (274:274:274) (364:364:364)) - (PORT datad (268:268:268) (349:349:349)) - (IOPATH dataa combout (327:327:327) (347:347:347)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2c_loader_\|shiftreg\~19) (DELAY (ABSOLUTE - (PORT dataa (445:445:445) (522:522:522)) - (PORT datab (419:419:419) (491:491:491)) - (PORT datac (308:308:308) (330:330:330)) - (PORT datad (197:197:197) (222:222:222)) - (IOPATH dataa combout (325:325:325) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~20) - (DELAY - (ABSOLUTE - (PORT dataa (248:248:248) (337:337:337)) - (PORT datac (886:886:886) (938:938:938)) - (PORT datad (176:176:176) (202:202:202)) - (IOPATH dataa combout (304:304:304) (307:307:307)) + (PORT dataa (203:203:203) (247:247:247)) + (PORT datab (247:247:247) (331:331:331)) + (PORT datac (639:639:639) (707:707:707)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (331:331:331) (342:342:342)) (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -51836,74 +51632,8 @@ (ABSOLUTE (PORT clk (1532:1532:1532) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1574:1574:1574)) - (PORT ena (1207:1207:1207) (1188:1188:1188)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~16) - (DELAY - (ABSOLUTE - (PORT dataa (424:424:424) (505:505:505)) - (PORT datab (298:298:298) (389:389:389)) - (PORT datac (273:273:273) (368:368:368)) - (PORT datad (278:278:278) (358:358:358)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~17) - (DELAY - (ABSOLUTE - (PORT dataa (441:441:441) (526:526:526)) - (PORT datab (454:454:454) (519:519:519)) - (PORT datac (501:501:501) (509:509:509)) - (PORT datad (352:352:352) (369:369:369)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~26) - (DELAY - (ABSOLUTE - (PORT dataa (639:639:639) (715:715:715)) - (PORT datab (244:244:244) (327:327:327)) - (PORT datac (888:888:888) (940:940:940)) - (PORT datad (175:175:175) (200:200:200)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (243:243:243) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1546:1546:1546)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1574:1574:1574)) - (PORT ena (1207:1207:1207) (1188:1188:1188)) + (PORT clrn (1566:1566:1566) (1559:1559:1559)) + (PORT ena (1000:1000:1000) (1005:1005:1005)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -51918,12 +51648,12 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\~25) (DELAY (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (679:679:679) (734:734:734)) - (PORT datac (620:620:620) (667:667:667)) - (PORT datad (364:364:364) (423:423:423)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (499:499:499) (565:565:565)) + (PORT datab (674:674:674) (746:746:746)) + (PORT datac (319:319:319) (348:348:348)) + (PORT datad (218:218:218) (287:287:287)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -51931,13 +51661,13 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|i2c_loader_\|shiftreg\[4\]) + (INSTANCE ula_\|i2c_loader_\|shiftreg\[3\]) (DELAY (ABSOLUTE (PORT clk (1532:1532:1532) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1574:1574:1574)) - (PORT ena (1410:1410:1410) (1399:1399:1399)) + (PORT clrn (1566:1566:1566) (1559:1559:1559)) + (PORT ena (1000:1000:1000) (1005:1005:1005)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -51952,9 +51682,75 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\~12) (DELAY (ABSOLUTE - (PORT dataa (544:544:544) (558:558:558)) - (PORT datab (488:488:488) (559:559:559)) - (PORT datad (364:364:364) (420:420:420)) + (PORT dataa (290:290:290) (391:391:391)) + (PORT datab (281:281:281) (370:370:370)) + (PORT datac (260:260:260) (349:349:349)) + (PORT datad (261:261:261) (340:340:340)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~14) + (DELAY + (ABSOLUTE + (PORT dataa (210:210:210) (257:257:257)) + (PORT datab (289:289:289) (380:380:380)) + (PORT datac (173:173:173) (205:205:205)) + (PORT datad (260:260:260) (338:338:338)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~24) + (DELAY + (ABSOLUTE + (PORT dataa (499:499:499) (565:565:565)) + (PORT datab (244:244:244) (327:327:327)) + (PORT datac (640:640:640) (708:708:708)) + (PORT datad (318:318:318) (338:338:338)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2c_loader_\|shiftreg\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1546:1546:1546)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1566:1566:1566) (1559:1559:1559)) + (PORT ena (1000:1000:1000) (1005:1005:1005)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2c_loader_\|shiftreg\~11) + (DELAY + (ABSOLUTE + (PORT dataa (364:364:364) (400:400:400)) + (PORT datab (630:630:630) (693:693:693)) + (PORT datad (366:366:366) (424:424:424)) (IOPATH dataa combout (354:354:354) (349:349:349)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -51966,10 +51762,10 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[5\]) (DELAY (ABSOLUTE - (PORT clk (1530:1530:1530) (1544:1544:1544)) + (PORT clk (1532:1532:1532) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1577:1577:1577) (1572:1572:1572)) - (PORT sload (1203:1203:1203) (1299:1299:1299)) + (PORT clrn (1566:1566:1566) (1559:1559:1559)) + (PORT sload (887:887:887) (1009:1009:1009)) (PORT ena (812:812:812) (805:805:805)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) @@ -51984,12 +51780,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2c_loader_\|shiftreg\~9) + (INSTANCE ula_\|i2c_loader_\|shiftreg\~8) (DELAY (ABSOLUTE - (PORT datab (642:642:642) (706:706:706)) - (PORT datac (893:893:893) (946:946:946)) - (PORT datad (198:198:198) (224:224:224)) + (PORT datab (416:416:416) (476:476:476)) + (PORT datac (646:646:646) (715:715:715)) + (PORT datad (196:196:196) (222:222:222)) (IOPATH datab combout (342:342:342) (342:342:342)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -52003,9 +51799,9 @@ (ABSOLUTE (PORT clk (1532:1532:1532) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1574:1574:1574)) - (PORT sclr (1104:1104:1104) (1198:1198:1198)) - (PORT ena (1207:1207:1207) (1188:1188:1188)) + (PORT clrn (1566:1566:1566) (1559:1559:1559)) + (PORT sclr (948:948:948) (1050:1050:1050)) + (PORT ena (1000:1000:1000) (1005:1005:1005)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52021,8 +51817,8 @@ (INSTANCE ula_\|i2c_loader_\|shiftreg\[7\]\~5) (DELAY (ABSOLUTE - (PORT datac (887:887:887) (939:939:939)) - (PORT datad (218:218:218) (287:287:287)) + (PORT datac (646:646:646) (714:714:714)) + (PORT datad (219:219:219) (288:288:288)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -52035,9 +51831,9 @@ (ABSOLUTE (PORT clk (1532:1532:1532) (1546:1546:1546)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1574:1574:1574)) - (PORT sclr (1104:1104:1104) (1198:1198:1198)) - (PORT ena (1397:1397:1397) (1366:1366:1366)) + (PORT clrn (1566:1566:1566) (1559:1559:1559)) + (PORT sclr (948:948:948) (1050:1050:1050)) + (PORT ena (922:922:922) (904:904:904)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52053,13 +51849,13 @@ (INSTANCE ula_\|i2c_loader_\|sda_out\~0) (DELAY (ABSOLUTE - (PORT dataa (683:683:683) (742:742:742)) - (PORT datab (416:416:416) (490:490:490)) - (PORT datac (558:558:558) (607:607:607)) - (PORT datad (384:384:384) (444:444:444)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (580:580:580) (642:642:642)) + (PORT datab (591:591:591) (655:655:655)) + (PORT datac (645:645:645) (710:710:710)) + (PORT datad (264:264:264) (344:344:344)) + (IOPATH dataa combout (304:304:304) (307:307:307)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -52069,10 +51865,10 @@ (INSTANCE ula_\|i2c_loader_\|sda_out\~1) (DELAY (ABSOLUTE - (PORT dataa (537:537:537) (561:561:561)) - (PORT datab (327:327:327) (433:433:433)) - (PORT datac (345:345:345) (368:368:368)) - (PORT datad (517:517:517) (510:510:510)) + (PORT dataa (553:553:553) (579:579:579)) + (PORT datab (677:677:677) (747:747:747)) + (PORT datac (172:172:172) (206:206:206)) + (PORT datad (498:498:498) (491:491:491)) (IOPATH dataa combout (341:341:341) (319:319:319)) (IOPATH datab combout (342:342:342) (318:318:318)) (IOPATH datac combout (243:243:243) (242:242:242)) @@ -52085,13 +51881,13 @@ (INSTANCE ula_\|i2c_loader_\|sda_out\~2) (DELAY (ABSOLUTE - (PORT dataa (254:254:254) (345:345:345)) - (PORT datab (329:329:329) (434:434:434)) - (PORT datac (260:260:260) (345:345:345)) - (PORT datad (181:181:181) (208:208:208)) + (PORT dataa (253:253:253) (346:346:346)) + (PORT datab (628:628:628) (705:705:705)) + (PORT datac (643:643:643) (707:707:707)) + (PORT datad (181:181:181) (210:210:210)) (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -52101,13 +51897,13 @@ (INSTANCE ula_\|i2c_loader_\|sda_out\~3) (DELAY (ABSOLUTE - (PORT dataa (255:255:255) (348:348:348)) - (PORT datab (324:324:324) (431:431:431)) - (PORT datac (261:261:261) (346:346:346)) - (PORT datad (180:180:180) (208:208:208)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (355:355:355) (349:349:349)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (255:255:255) (347:347:347)) + (PORT datab (632:632:632) (709:709:709)) + (PORT datac (647:647:647) (712:712:712)) + (PORT datad (181:181:181) (208:208:208)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -52117,12 +51913,12 @@ (INSTANCE ula_\|i2c_loader_\|sda_out\~4) (DELAY (ABSOLUTE - (PORT dataa (663:663:663) (743:743:743)) - (PORT datab (802:802:802) (828:828:828)) - (PORT datac (173:173:173) (206:206:206)) + (PORT dataa (220:220:220) (273:273:273)) + (PORT datab (640:640:640) (701:701:701)) + (PORT datac (172:172:172) (206:206:206)) (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (300:300:300) (310:310:310)) + (IOPATH dataa combout (301:301:301) (307:307:307)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -52134,9 +51930,9 @@ (DELAY (ABSOLUTE (PORT clk (1475:1475:1475) (1497:1497:1497)) - (PORT d (691:691:691) (730:730:730)) - (PORT aload (1726:1726:1726) (1792:1792:1792)) - (PORT ena (1272:1272:1272) (1294:1294:1294)) + (PORT d (694:694:694) (732:732:732)) + (PORT aload (1713:1713:1713) (1777:1777:1777)) + (PORT ena (857:857:857) (866:866:866)) (IOPATH (posedge clk) q (617:617:617) (612:612:612)) (IOPATH (posedge aload) q (513:513:513) (508:508:508)) ) @@ -52162,9 +51958,9 @@ (INSTANCE ula_\|i2s_intf_\|mclk_r\~_Duplicate_1) (DELAY (ABSOLUTE - (PORT clk (1892:1892:1892) (1916:1916:1916)) + (PORT clk (1925:1925:1925) (1950:1950:1950)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1573:1573:1573) (1569:1569:1569)) + (PORT clrn (1567:1567:1567) (1559:1559:1559)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52179,8 +51975,8 @@ (DELAY (ABSOLUTE (PORT clk (1506:1506:1506) (1528:1528:1528)) - (PORT d (2379:2379:2379) (2282:2282:2282)) - (PORT clrn (1763:1763:1763) (1815:1815:1815)) + (PORT d (1249:1249:1249) (1276:1276:1276)) + (PORT clrn (1750:1750:1750) (1800:1800:1800)) (IOPATH (posedge clk) q (586:586:586) (589:589:589)) (IOPATH (negedge clrn) q (712:712:712) (715:715:715)) ) @@ -52195,7 +51991,7 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~1) (DELAY (ABSOLUTE - (PORT dataa (697:697:697) (777:777:777)) + (PORT dataa (403:403:403) (487:487:487)) (IOPATH dataa cout (436:436:436) (315:315:315)) ) ) @@ -52205,9 +52001,9 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~2) (DELAY (ABSOLUTE - (PORT datab (251:251:251) (336:336:336)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (427:427:427) (494:494:494)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -52219,8 +52015,8 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\~2) (DELAY (ABSOLUTE - (PORT dataa (230:230:230) (277:277:277)) - (PORT datac (174:174:174) (208:208:208)) + (PORT dataa (451:451:451) (498:498:498)) + (PORT datac (316:316:316) (346:346:346)) (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datac combout (243:243:243) (242:242:242)) ) @@ -52231,9 +52027,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[1\]) (DELAY (ABSOLUTE - (PORT clk (1892:1892:1892) (1916:1916:1916)) + (PORT clk (1935:1935:1935) (1961:1961:1961)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1573:1573:1573) (1569:1569:1569)) + (PORT clrn (1567:1567:1567) (1559:1559:1559)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52247,9 +52043,9 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~4) (DELAY (ABSOLUTE - (PORT dataa (398:398:398) (479:479:479)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (390:390:390) (459:459:459)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -52261,8 +52057,8 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[2\]\~8) (DELAY (ABSOLUTE - (PORT datad (328:328:328) (343:343:343)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT datac (347:347:347) (370:370:370)) + (IOPATH datac combout (241:241:241) (241:241:241)) ) ) ) @@ -52271,9 +52067,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[2\]) (DELAY (ABSOLUTE - (PORT clk (1892:1892:1892) (1915:1915:1915)) + (PORT clk (1935:1935:1935) (1961:1961:1961)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1573:1573:1573) (1568:1568:1568)) + (PORT clrn (1567:1567:1567) (1559:1559:1559)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52287,7 +52083,7 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~6) (DELAY (ABSOLUTE - (PORT datab (391:391:391) (458:458:458)) + (PORT datab (388:388:388) (459:459:459)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -52301,8 +52097,8 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[3\]\~7) (DELAY (ABSOLUTE - (PORT datac (345:345:345) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT datad (561:561:561) (568:568:568)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -52311,9 +52107,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[3\]) (DELAY (ABSOLUTE - (PORT clk (1892:1892:1892) (1916:1916:1916)) + (PORT clk (1935:1935:1935) (1961:1961:1961)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1573:1573:1573) (1569:1569:1569)) + (PORT clrn (1567:1567:1567) (1559:1559:1559)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52327,9 +52123,9 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~8) (DELAY (ABSOLUTE - (PORT datab (251:251:251) (337:337:337)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (395:395:395) (469:469:469)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -52341,10 +52137,10 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\~1) (DELAY (ABSOLUTE - (PORT dataa (231:231:231) (281:281:281)) - (PORT datac (172:172:172) (204:204:204)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT datac (413:413:413) (454:454:454)) + (PORT datad (314:314:314) (335:335:335)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -52353,9 +52149,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[4\]) (DELAY (ABSOLUTE - (PORT clk (1892:1892:1892) (1916:1916:1916)) + (PORT clk (1935:1935:1935) (1961:1961:1961)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1573:1573:1573) (1569:1569:1569)) + (PORT clrn (1567:1567:1567) (1559:1559:1559)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52369,9 +52165,9 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~10) (DELAY (ABSOLUTE - (PORT datab (251:251:251) (337:337:337)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (393:393:393) (467:467:467)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -52383,7 +52179,7 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[5\]\~6) (DELAY (ABSOLUTE - (PORT datad (175:175:175) (201:201:201)) + (PORT datad (339:339:339) (359:359:359)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -52393,9 +52189,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[5\]) (DELAY (ABSOLUTE - (PORT clk (1892:1892:1892) (1916:1916:1916)) + (PORT clk (1935:1935:1935) (1961:1961:1961)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1573:1573:1573) (1569:1569:1569)) + (PORT clrn (1567:1567:1567) (1559:1559:1559)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52409,12 +52205,12 @@ (INSTANCE ula_\|i2s_intf_\|Equal0\~1) (DELAY (ABSOLUTE - (PORT dataa (400:400:400) (481:481:481)) - (PORT datab (252:252:252) (338:338:338)) - (PORT datac (365:365:365) (427:427:427)) - (PORT datad (227:227:227) (300:300:300)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) + (PORT dataa (398:398:398) (469:469:469)) + (PORT datab (391:391:391) (460:460:460)) + (PORT datac (358:358:358) (423:423:423)) + (PORT datad (367:367:367) (422:422:422)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -52425,7 +52221,7 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~12) (DELAY (ABSOLUTE - (PORT dataa (427:427:427) (491:491:491)) + (PORT dataa (429:429:429) (493:493:493)) (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -52439,8 +52235,8 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[6\]\~5) (DELAY (ABSOLUTE - (PORT datad (338:338:338) (357:357:357)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT datac (317:317:317) (343:343:343)) + (IOPATH datac combout (241:241:241) (241:241:241)) ) ) ) @@ -52449,9 +52245,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[6\]) (DELAY (ABSOLUTE - (PORT clk (1892:1892:1892) (1916:1916:1916)) + (PORT clk (1935:1935:1935) (1961:1961:1961)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1573:1573:1573) (1569:1569:1569)) + (PORT clrn (1567:1567:1567) (1559:1559:1559)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52465,9 +52261,9 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~14) (DELAY (ABSOLUTE - (PORT dataa (438:438:438) (507:507:507)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (251:251:251) (336:336:336)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -52479,8 +52275,8 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[7\]\~4) (DELAY (ABSOLUTE - (PORT datad (333:333:333) (348:348:348)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT datac (174:174:174) (208:208:208)) + (IOPATH datac combout (241:241:241) (241:241:241)) ) ) ) @@ -52489,9 +52285,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[7\]) (DELAY (ABSOLUTE - (PORT clk (1892:1892:1892) (1915:1915:1915)) + (PORT clk (1925:1925:1925) (1950:1950:1950)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1573:1573:1573) (1568:1568:1568)) + (PORT clrn (1567:1567:1567) (1559:1559:1559)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52505,9 +52301,9 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~16) (DELAY (ABSOLUTE - (PORT dataa (396:396:396) (467:467:467)) - (IOPATH dataa combout (341:341:341) (347:347:347)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (250:250:250) (335:335:335)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -52519,8 +52315,8 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\~0) (DELAY (ABSOLUTE - (PORT datab (376:376:376) (401:401:401)) - (PORT datac (380:380:380) (411:411:411)) + (PORT datab (198:198:198) (237:237:237)) + (PORT datac (193:193:193) (226:226:226)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (241:241:241) (241:241:241)) ) @@ -52531,9 +52327,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[8\]) (DELAY (ABSOLUTE - (PORT clk (1892:1892:1892) (1916:1916:1916)) + (PORT clk (1925:1925:1925) (1950:1950:1950)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1573:1573:1573) (1569:1569:1569)) + (PORT clrn (1567:1567:1567) (1559:1559:1559)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52547,8 +52343,8 @@ (INSTANCE ula_\|i2s_intf_\|Add0\~18) (DELAY (ABSOLUTE - (PORT datad (383:383:383) (442:442:442)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT datab (254:254:254) (340:340:340)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH cin combout (455:455:455) (437:437:437)) ) ) @@ -52558,8 +52354,8 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[9\]\~3) (DELAY (ABSOLUTE - (PORT datad (337:337:337) (357:357:357)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT datac (173:173:173) (207:207:207)) + (IOPATH datac combout (241:241:241) (241:241:241)) ) ) ) @@ -52568,9 +52364,9 @@ (INSTANCE ula_\|i2s_intf_\|lrdivider\[9\]) (DELAY (ABSOLUTE - (PORT clk (1892:1892:1892) (1916:1916:1916)) + (PORT clk (1925:1925:1925) (1950:1950:1950)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1573:1573:1573) (1569:1569:1569)) + (PORT clrn (1567:1567:1567) (1559:1559:1559)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52584,12 +52380,12 @@ (INSTANCE ula_\|i2s_intf_\|Equal0\~0) (DELAY (ABSOLUTE - (PORT dataa (397:397:397) (468:468:468)) - (PORT datab (423:423:423) (484:484:484)) - (PORT datac (392:392:392) (453:453:453)) - (PORT datad (393:393:393) (454:454:454)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) + (PORT dataa (426:426:426) (489:489:489)) + (PORT datab (251:251:251) (336:336:336)) + (PORT datac (221:221:221) (301:301:301)) + (PORT datad (223:223:223) (295:295:295)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -52600,35 +52396,25 @@ (INSTANCE ula_\|i2s_intf_\|Equal0\~2) (DELAY (ABSOLUTE - (PORT dataa (200:200:200) (243:243:243)) - (PORT datab (249:249:249) (333:333:333)) - (PORT datac (664:664:664) (736:736:736)) + (PORT dataa (429:429:429) (495:495:495)) + (PORT datab (202:202:202) (242:242:242)) + (PORT datac (373:373:373) (448:448:448)) (PORT datad (176:176:176) (202:202:202)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|lrclk_r\~_Duplicate_2feeder) - (DELAY - (ABSOLUTE - (PORT datad (198:198:198) (224:224:224)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|i2s_intf_\|lrclk_r\~_Duplicate_2) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1540:1540:1540)) + (PORT clk (1924:1924:1924) (1949:1949:1949)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1574:1574:1574) (1568:1568:1568)) + (PORT clrn (1566:1566:1566) (1558:1558:1558)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52642,10 +52428,9 @@ (INSTANCE ula_\|i2s_intf_\|lrclk_r\~0) (DELAY (ABSOLUTE - (PORT datab (905:905:905) (938:938:938)) - (PORT datad (233:233:233) (308:308:308)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT datab (795:795:795) (857:857:857)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) ) ) ) @@ -52655,8 +52440,8 @@ (DELAY (ABSOLUTE (PORT clk (1505:1505:1505) (1526:1526:1526)) - (PORT d (2289:2289:2289) (2450:2450:2450)) - (PORT clrn (1761:1761:1761) (1813:1813:1813)) + (PORT d (1358:1358:1358) (1407:1407:1407)) + (PORT clrn (1748:1748:1748) (1798:1798:1798)) (IOPATH (posedge clk) q (586:586:586) (589:589:589)) (IOPATH (negedge clrn) q (712:712:712) (715:715:715)) ) @@ -52672,8 +52457,8 @@ (DELAY (ABSOLUTE (PORT clk (1505:1505:1505) (1527:1527:1527)) - (PORT d (2528:2528:2528) (2663:2663:2663)) - (PORT clrn (1762:1762:1762) (1814:1814:1814)) + (PORT d (1356:1356:1356) (1407:1407:1407)) + (PORT clrn (1749:1749:1749) (1799:1799:1799)) (IOPATH (posedge clk) q (586:586:586) (589:589:589)) (IOPATH (negedge clrn) q (712:712:712) (715:715:715)) ) @@ -52688,20 +52473,30 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[0\]\~5) (DELAY (ABSOLUTE - (PORT datab (248:248:248) (334:334:334)) + (PORT datab (249:249:249) (334:334:334)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datab cout (446:446:446) (318:318:318)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|bclk_r\~_Duplicate_1feeder) + (DELAY + (ABSOLUTE + (PORT datad (195:195:195) (220:220:220)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|i2s_intf_\|bclk_r\~_Duplicate_1) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1541:1541:1541)) + (PORT clk (1533:1533:1533) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1574:1574:1574) (1569:1569:1569)) + (PORT clrn (1567:1567:1567) (1558:1558:1558)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52715,10 +52510,10 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[4\]\~15) (DELAY (ABSOLUTE - (PORT datab (235:235:235) (283:283:283)) - (PORT datac (873:873:873) (896:896:896)) - (PORT datad (241:241:241) (319:319:319)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (PORT dataa (279:279:279) (379:379:379)) + (PORT datac (601:601:601) (623:623:623)) + (PORT datad (204:204:204) (232:232:232)) + (IOPATH dataa combout (325:325:325) (320:320:320)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -52729,12 +52524,12 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[0\]) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1541:1541:1541)) + (PORT clk (1533:1533:1533) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (2714:2714:2714) (2746:2746:2746)) - (PORT clrn (1574:1574:1574) (1569:1569:1569)) - (PORT sload (1479:1479:1479) (1529:1529:1529)) - (PORT ena (790:790:790) (783:783:783)) + (PORT asdata (571:571:571) (613:613:613)) + (PORT clrn (1567:1567:1567) (1558:1558:1558)) + (PORT sload (1210:1210:1210) (1266:1266:1266)) + (PORT ena (794:794:794) (792:792:792)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52751,9 +52546,9 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[1\]\~7) (DELAY (ABSOLUTE - (PORT datab (248:248:248) (333:333:333)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (436:436:436) (500:500:500)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -52765,12 +52560,12 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[1\]) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1541:1541:1541)) + (PORT clk (1533:1533:1533) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (2713:2713:2713) (2746:2746:2746)) - (PORT clrn (1574:1574:1574) (1569:1569:1569)) - (PORT sload (1479:1479:1479) (1529:1529:1529)) - (PORT ena (790:790:790) (783:783:783)) + (PORT asdata (570:570:570) (613:613:613)) + (PORT clrn (1567:1567:1567) (1558:1558:1558)) + (PORT sload (1210:1210:1210) (1266:1266:1266)) + (PORT ena (794:794:794) (792:792:792)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52801,12 +52596,12 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[2\]) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1541:1541:1541)) + (PORT clk (1533:1533:1533) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (2711:2711:2711) (2744:2744:2744)) - (PORT clrn (1574:1574:1574) (1569:1569:1569)) - (PORT sload (1479:1479:1479) (1529:1529:1529)) - (PORT ena (790:790:790) (783:783:783)) + (PORT asdata (569:569:569) (609:609:609)) + (PORT clrn (1567:1567:1567) (1558:1558:1558)) + (PORT sload (1210:1210:1210) (1266:1266:1266)) + (PORT ena (794:794:794) (792:792:792)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52823,7 +52618,7 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[3\]\~11) (DELAY (ABSOLUTE - (PORT dataa (252:252:252) (343:343:343)) + (PORT dataa (252:252:252) (341:341:341)) (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -52837,12 +52632,12 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[3\]) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1541:1541:1541)) + (PORT clk (1533:1533:1533) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (2711:2711:2711) (2744:2744:2744)) - (PORT clrn (1574:1574:1574) (1569:1569:1569)) - (PORT sload (1479:1479:1479) (1529:1529:1529)) - (PORT ena (790:790:790) (783:783:783)) + (PORT asdata (570:570:570) (610:610:610)) + (PORT clrn (1567:1567:1567) (1558:1558:1558)) + (PORT sload (1210:1210:1210) (1266:1266:1266)) + (PORT ena (794:794:794) (792:792:792)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52854,22 +52649,6 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|LessThan0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (252:252:252) (343:343:343)) - (PORT datab (252:252:252) (338:338:338)) - (PORT datac (223:223:223) (303:303:303)) - (PORT datad (227:227:227) (299:299:299)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2s_intf_\|bitcount\[4\]\~13) @@ -52886,12 +52665,12 @@ (INSTANCE ula_\|i2s_intf_\|bitcount\[4\]) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1541:1541:1541)) + (PORT clk (1533:1533:1533) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) - (PORT asdata (2710:2710:2710) (2743:2743:2743)) - (PORT clrn (1574:1574:1574) (1569:1569:1569)) - (PORT sload (1479:1479:1479) (1529:1529:1529)) - (PORT ena (790:790:790) (783:783:783)) + (PORT asdata (570:570:570) (610:610:610)) + (PORT clrn (1567:1567:1567) (1558:1558:1558)) + (PORT sload (1210:1210:1210) (1266:1266:1266)) + (PORT ena (794:794:794) (792:792:792)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52903,12 +52682,75 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|LessThan0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (439:439:439) (503:503:503)) + (PORT datab (252:252:252) (338:338:338)) + (PORT datac (225:225:225) (305:305:305)) + (PORT datad (226:226:226) (300:300:300)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|shiftreg\[4\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (437:437:437) (501:501:501)) + (PORT datab (390:390:390) (411:411:411)) + (PORT datac (240:240:240) (328:328:328)) + (PORT datad (190:190:190) (223:223:223)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|Add2\~18) + (DELAY + (ABSOLUTE + (PORT dataa (492:492:492) (538:538:538)) + (PORT datab (382:382:382) (421:421:421)) + (PORT datad (220:220:220) (257:257:257)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|bdivider\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1566:1566:1566) (1558:1558:1558)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2s_intf_\|Add2\~7) (DELAY (ABSOLUTE - (PORT dataa (467:467:467) (538:538:538)) + (PORT dataa (287:287:287) (384:384:384)) (IOPATH dataa cout (436:436:436) (315:315:315)) ) ) @@ -52918,7 +52760,7 @@ (INSTANCE ula_\|i2s_intf_\|Add2\~8) (DELAY (ABSOLUTE - (PORT dataa (253:253:253) (344:344:344)) + (PORT dataa (252:252:252) (343:343:343)) (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -52932,12 +52774,12 @@ (INSTANCE ula_\|i2s_intf_\|Add2\~20) (DELAY (ABSOLUTE - (PORT dataa (470:470:470) (540:540:540)) - (PORT datab (903:903:903) (940:940:940)) - (PORT datac (205:205:205) (243:243:243)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) + (PORT dataa (291:291:291) (387:387:387)) + (PORT datab (201:201:201) (240:240:240)) + (PORT datac (456:456:456) (504:504:504)) + (PORT datad (217:217:217) (253:253:253)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -52948,9 +52790,9 @@ (INSTANCE ula_\|i2s_intf_\|bdivider\[1\]) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1540:1540:1540)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1574:1574:1574) (1568:1568:1568)) + (PORT clrn (1566:1566:1566) (1558:1558:1558)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -52964,7 +52806,7 @@ (INSTANCE ula_\|i2s_intf_\|Add2\~10) (DELAY (ABSOLUTE - (PORT dataa (399:399:399) (472:472:472)) + (PORT dataa (253:253:253) (343:343:343)) (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -52978,12 +52820,12 @@ (INSTANCE ula_\|i2s_intf_\|Add2\~17) (DELAY (ABSOLUTE - (PORT dataa (227:227:227) (284:284:284)) - (PORT datab (234:234:234) (285:285:285)) - (PORT datac (875:875:875) (898:898:898)) - (PORT datad (338:338:338) (359:359:359)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (499:499:499) (546:546:546)) + (PORT datab (232:232:232) (275:275:275)) + (PORT datac (355:355:355) (391:391:391)) + (PORT datad (176:176:176) (202:202:202)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (304:304:304) (308:308:308)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -52994,9 +52836,9 @@ (INSTANCE ula_\|i2s_intf_\|bdivider\[2\]) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1541:1541:1541)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1574:1574:1574) (1569:1569:1569)) + (PORT clrn (1566:1566:1566) (1558:1558:1558)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53010,7 +52852,7 @@ (INSTANCE ula_\|i2s_intf_\|Add2\~12) (DELAY (ABSOLUTE - (PORT datab (253:253:253) (339:339:339)) + (PORT datab (249:249:249) (334:334:334)) (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -53024,12 +52866,12 @@ (INSTANCE ula_\|i2s_intf_\|Add2\~19) (DELAY (ABSOLUTE - (PORT dataa (471:471:471) (539:539:539)) - (PORT datab (906:906:906) (939:939:939)) - (PORT datac (206:206:206) (243:243:243)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (336:336:336) (325:325:325)) + (PORT dataa (290:290:290) (387:387:387)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (441:441:441) (486:486:486)) + (PORT datad (221:221:221) (257:257:257)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -53040,9 +52882,9 @@ (INSTANCE ula_\|i2s_intf_\|bdivider\[3\]) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1540:1540:1540)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1574:1574:1574) (1568:1568:1568)) + (PORT clrn (1566:1566:1566) (1558:1558:1558)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53056,7 +52898,7 @@ (INSTANCE ula_\|i2s_intf_\|Add2\~14) (DELAY (ABSOLUTE - (PORT datad (362:362:362) (417:417:417)) + (PORT datad (228:228:228) (301:301:301)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) ) @@ -53067,12 +52909,12 @@ (INSTANCE ula_\|i2s_intf_\|Add2\~16) (DELAY (ABSOLUTE - (PORT dataa (227:227:227) (285:285:285)) - (PORT datab (235:235:235) (288:288:288)) - (PORT datac (875:875:875) (900:900:900)) - (PORT datad (339:339:339) (359:359:359)) - (IOPATH dataa combout (303:303:303) (299:299:299)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT dataa (500:500:500) (547:547:547)) + (PORT datab (232:232:232) (275:275:275)) + (PORT datac (355:355:355) (391:391:391)) + (PORT datad (175:175:175) (202:202:202)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (304:304:304) (308:308:308)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -53083,9 +52925,9 @@ (INSTANCE ula_\|i2s_intf_\|bdivider\[4\]) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1541:1541:1541)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1574:1574:1574) (1569:1569:1569)) + (PORT clrn (1566:1566:1566) (1558:1558:1558)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53099,72 +52941,25 @@ (INSTANCE ula_\|i2s_intf_\|Equal1\~0) (DELAY (ABSOLUTE - (PORT dataa (253:253:253) (345:345:345)) - (PORT datab (253:253:253) (339:339:339)) - (PORT datac (368:368:368) (430:430:430)) - (PORT datad (361:361:361) (415:415:415)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (252:252:252) (343:343:343)) + (PORT datab (249:249:249) (335:335:335)) + (PORT datac (223:223:223) (304:304:304)) + (PORT datad (226:226:226) (299:299:299)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|shiftreg\[4\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (266:266:266) (353:353:353)) - (PORT datab (217:217:217) (263:263:263)) - (PORT datac (241:241:241) (328:328:328)) - (PORT datad (373:373:373) (399:399:399)) - (IOPATH dataa combout (303:303:303) (308:308:308)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|Add2\~18) - (DELAY - (ABSOLUTE - (PORT dataa (908:908:908) (938:938:938)) - (PORT datab (235:235:235) (286:286:286)) - (PORT datad (375:375:375) (401:401:401)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|bdivider\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1527:1527:1527) (1541:1541:1541)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1574:1574:1574) (1569:1569:1569)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2s_intf_\|Equal1\~1) (DELAY (ABSOLUTE - (PORT datac (382:382:382) (450:450:450)) - (PORT datad (371:371:371) (396:396:396)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT datab (244:244:244) (291:291:291)) + (PORT datad (261:261:261) (342:342:342)) + (IOPATH datab combout (306:306:306) (311:311:311)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53174,12 +52969,12 @@ (INSTANCE ula_\|i2s_intf_\|bclk_r\~0) (DELAY (ABSOLUTE - (PORT datab (216:216:216) (262:262:262)) - (PORT datac (239:239:239) (326:326:326)) - (PORT datad (238:238:238) (316:316:316)) - (IOPATH datab combout (342:342:342) (342:342:342)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT dataa (275:275:275) (376:376:376)) + (PORT datab (215:215:215) (259:259:259)) + (PORT datac (240:240:240) (328:328:328)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) ) ) ) @@ -53188,12 +52983,13 @@ (INSTANCE ula_\|i2s_intf_\|bclk_r\~1) (DELAY (ABSOLUTE - (PORT dataa (226:226:226) (283:283:283)) - (PORT datab (199:199:199) (239:239:239)) - (PORT datad (869:869:869) (882:882:882)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (353:353:353) (369:369:369)) + (PORT dataa (373:373:373) (401:401:401)) + (PORT datab (631:631:631) (655:655:655)) + (PORT datac (245:245:245) (335:335:335)) + (PORT datad (173:173:173) (198:198:198)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53204,8 +53000,8 @@ (DELAY (ABSOLUTE (PORT clk (1504:1504:1504) (1526:1526:1526)) - (PORT d (2278:2278:2278) (2430:2430:2430)) - (PORT clrn (1761:1761:1761) (1813:1813:1813)) + (PORT d (1540:1540:1540) (1616:1616:1616)) + (PORT clrn (1748:1748:1748) (1798:1798:1798)) (IOPATH (posedge clk) q (586:586:586) (589:589:589)) (IOPATH (negedge clrn) q (712:712:712) (715:715:715)) ) @@ -53215,27 +53011,17 @@ (HOLD d (posedge clk) (97:97:97)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|pcm_outl\[13\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (861:861:861) (917:917:917)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|always0\~2) (DELAY (ABSOLUTE - (PORT dataa (1754:1754:1754) (1860:1860:1860)) - (PORT datab (1594:1594:1594) (1730:1730:1730)) - (PORT datac (1193:1193:1193) (1255:1255:1255)) - (IOPATH dataa combout (341:341:341) (319:319:319)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (586:586:586) (615:615:615)) + (PORT datab (2799:2799:2799) (2989:2989:2989)) + (PORT datad (605:605:605) (624:624:624)) + (IOPATH dataa combout (325:325:325) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -53244,12 +53030,12 @@ (INSTANCE ula_\|always0\~3) (DELAY (ABSOLUTE - (PORT dataa (686:686:686) (777:777:777)) - (PORT datab (1248:1248:1248) (1347:1347:1347)) - (PORT datac (1200:1200:1200) (1266:1266:1266)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (306:306:306) (308:308:308)) + (PORT dataa (246:246:246) (300:300:300)) + (PORT datab (958:958:958) (1019:1019:1019)) + (PORT datac (2765:2765:2765) (2956:2956:2956)) + (PORT datad (520:520:520) (530:530:530)) + (IOPATH dataa combout (304:304:304) (299:299:299)) + (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -53257,12 +53043,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|pcm_outl\[13\]) + (INSTANCE ula_\|pcm_outl\[14\]) (DELAY (ABSOLUTE - (PORT clk (1522:1522:1522) (1536:1536:1536)) + (PORT clk (1518:1518:1518) (1532:1532:1532)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (2002:2002:2002) (1998:1998:1998)) + (PORT ena (1943:1943:1943) (1924:1924:1924)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -53276,12 +53062,12 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[0\]\~19) (DELAY (ABSOLUTE - (PORT dataa (225:225:225) (279:279:279)) - (PORT datab (216:216:216) (259:259:259)) - (PORT datac (241:241:241) (328:328:328)) - (PORT datad (239:239:239) (317:317:317)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datab combout (331:331:331) (342:342:342)) + (PORT dataa (371:371:371) (403:403:403)) + (PORT datab (269:269:269) (361:361:361)) + (PORT datac (247:247:247) (339:339:339)) + (PORT datad (190:190:190) (222:222:222)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -53301,11 +53087,11 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[0\]\~20) (DELAY (ABSOLUTE - (PORT dataa (1354:1354:1354) (1417:1417:1417)) - (PORT datab (1297:1297:1297) (1385:1385:1385)) - (PORT datad (764:764:764) (757:757:757)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (336:336:336) (342:342:342)) + (PORT dataa (496:496:496) (543:543:543)) + (PORT datab (340:340:340) (373:373:373)) + (PORT datad (795:795:795) (785:785:785)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (337:337:337) (348:348:348)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -53316,9 +53102,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[0\]) (DELAY (ABSOLUTE - (PORT clk (1877:1877:1877) (1887:1887:1887)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1572:1572:1572)) + (PORT clrn (1566:1566:1566) (1558:1558:1558)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53332,10 +53118,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~18) (DELAY (ABSOLUTE - (PORT datab (244:244:244) (327:327:327)) - (PORT datad (1250:1250:1250) (1334:1334:1334)) + (PORT datab (423:423:423) (489:489:489)) + (PORT datac (764:764:764) (828:828:828)) (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH datac combout (241:241:241) (241:241:241)) ) ) ) @@ -53344,10 +53130,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[4\]\~2) (DELAY (ABSOLUTE - (PORT datab (234:234:234) (283:283:283)) - (PORT datac (872:872:872) (895:895:895)) - (PORT datad (240:240:240) (318:318:318)) - (IOPATH datab combout (304:304:304) (311:311:311)) + (PORT dataa (274:274:274) (375:375:375)) + (PORT datac (601:601:601) (625:625:625)) + (PORT datad (204:204:204) (234:234:234)) + (IOPATH dataa combout (303:303:303) (308:308:308)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -53358,10 +53144,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[1\]) (DELAY (ABSOLUTE - (PORT clk (1907:1907:1907) (1929:1929:1929)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1572:1572:1572)) - (PORT ena (2122:2122:2122) (2190:2190:2190)) + (PORT clrn (1566:1566:1566) (1558:1558:1558)) + (PORT ena (1212:1212:1212) (1209:1209:1209)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53376,10 +53162,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~17) (DELAY (ABSOLUTE - (PORT datac (216:216:216) (293:293:293)) - (PORT datad (1250:1250:1250) (1341:1341:1341)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT datab (792:792:792) (867:867:867)) + (PORT datac (219:219:219) (296:296:296)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) ) ) ) @@ -53388,10 +53174,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[2\]) (DELAY (ABSOLUTE - (PORT clk (1907:1907:1907) (1929:1929:1929)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1572:1572:1572)) - (PORT ena (2122:2122:2122) (2190:2190:2190)) + (PORT clrn (1566:1566:1566) (1558:1558:1558)) + (PORT ena (1212:1212:1212) (1209:1209:1209)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53406,9 +53192,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~16) (DELAY (ABSOLUTE - (PORT datab (245:245:245) (328:328:328)) - (PORT datad (1259:1259:1259) (1340:1340:1340)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (PORT datac (758:758:758) (830:830:830)) + (PORT datad (219:219:219) (287:287:287)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53418,10 +53204,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[3\]) (DELAY (ABSOLUTE - (PORT clk (1907:1907:1907) (1929:1929:1929)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1572:1572:1572)) - (PORT ena (2122:2122:2122) (2190:2190:2190)) + (PORT clrn (1566:1566:1566) (1558:1558:1558)) + (PORT ena (1212:1212:1212) (1209:1209:1209)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53436,10 +53222,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~15) (DELAY (ABSOLUTE - (PORT datab (246:246:246) (330:330:330)) - (PORT datad (1269:1269:1269) (1352:1352:1352)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT datab (797:797:797) (863:863:863)) + (PORT datac (219:219:219) (296:296:296)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) ) ) ) @@ -53448,10 +53234,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[4\]) (DELAY (ABSOLUTE - (PORT clk (1907:1907:1907) (1929:1929:1929)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1572:1572:1572)) - (PORT ena (2122:2122:2122) (2190:2190:2190)) + (PORT clrn (1566:1566:1566) (1558:1558:1558)) + (PORT ena (1212:1212:1212) (1209:1209:1209)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53466,9 +53252,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~14) (DELAY (ABSOLUTE - (PORT datab (245:245:245) (328:328:328)) - (PORT datad (1270:1270:1270) (1351:1351:1351)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (PORT datac (751:751:751) (831:831:831)) + (PORT datad (219:219:219) (288:288:288)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53478,10 +53264,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[5\]) (DELAY (ABSOLUTE - (PORT clk (1907:1907:1907) (1929:1929:1929)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1572:1572:1572)) - (PORT ena (2122:2122:2122) (2190:2190:2190)) + (PORT clrn (1566:1566:1566) (1558:1558:1558)) + (PORT ena (1212:1212:1212) (1209:1209:1209)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53496,10 +53282,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~13) (DELAY (ABSOLUTE - (PORT dataa (247:247:247) (335:335:335)) - (PORT datad (1261:1261:1261) (1348:1348:1348)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT datab (799:799:799) (870:870:870)) + (PORT datac (217:217:217) (294:294:294)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) ) ) ) @@ -53508,10 +53294,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[6\]) (DELAY (ABSOLUTE - (PORT clk (1907:1907:1907) (1929:1929:1929)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1572:1572:1572)) - (PORT ena (2122:2122:2122) (2190:2190:2190)) + (PORT clrn (1566:1566:1566) (1558:1558:1558)) + (PORT ena (1212:1212:1212) (1209:1209:1209)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53526,9 +53312,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~12) (DELAY (ABSOLUTE - (PORT datab (245:245:245) (328:328:328)) - (PORT datad (1246:1246:1246) (1335:1335:1335)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (PORT datac (766:766:766) (829:829:829)) + (PORT datad (218:218:218) (286:286:286)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53538,10 +53324,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[7\]) (DELAY (ABSOLUTE - (PORT clk (1907:1907:1907) (1929:1929:1929)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1572:1572:1572)) - (PORT ena (2122:2122:2122) (2190:2190:2190)) + (PORT clrn (1566:1566:1566) (1558:1558:1558)) + (PORT ena (1212:1212:1212) (1209:1209:1209)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53556,10 +53342,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~11) (DELAY (ABSOLUTE - (PORT datac (216:216:216) (292:292:292)) - (PORT datad (1248:1248:1248) (1334:1334:1334)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT datab (802:802:802) (872:872:872)) + (PORT datac (217:217:217) (294:294:294)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) ) ) ) @@ -53568,10 +53354,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[8\]) (DELAY (ABSOLUTE - (PORT clk (1907:1907:1907) (1929:1929:1929)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1572:1572:1572)) - (PORT ena (2122:2122:2122) (2190:2190:2190)) + (PORT clrn (1566:1566:1566) (1558:1558:1558)) + (PORT ena (1212:1212:1212) (1209:1209:1209)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53586,9 +53372,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~10) (DELAY (ABSOLUTE - (PORT datab (244:244:244) (327:327:327)) - (PORT datad (1249:1249:1249) (1344:1344:1344)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (PORT datac (754:754:754) (823:823:823)) + (PORT datad (219:219:219) (288:288:288)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53598,10 +53384,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[9\]) (DELAY (ABSOLUTE - (PORT clk (1907:1907:1907) (1929:1929:1929)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1572:1572:1572)) - (PORT ena (2122:2122:2122) (2190:2190:2190)) + (PORT clrn (1566:1566:1566) (1558:1558:1558)) + (PORT ena (1212:1212:1212) (1209:1209:1209)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53616,10 +53402,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~9) (DELAY (ABSOLUTE - (PORT datac (218:218:218) (296:296:296)) - (PORT datad (1269:1269:1269) (1350:1350:1350)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT dataa (247:247:247) (335:335:335)) + (PORT datac (759:759:759) (831:831:831)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (241:241:241)) ) ) ) @@ -53628,10 +53414,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[10\]) (DELAY (ABSOLUTE - (PORT clk (1907:1907:1907) (1929:1929:1929)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1572:1572:1572)) - (PORT ena (2122:2122:2122) (2190:2190:2190)) + (PORT clrn (1566:1566:1566) (1558:1558:1558)) + (PORT ena (1212:1212:1212) (1209:1209:1209)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53646,9 +53432,9 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~8) (DELAY (ABSOLUTE - (PORT dataa (246:246:246) (334:334:334)) - (PORT datad (1268:1268:1268) (1351:1351:1351)) - (IOPATH dataa combout (354:354:354) (367:367:367)) + (PORT datac (760:760:760) (831:831:831)) + (PORT datad (219:219:219) (288:288:288)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53658,10 +53444,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[11\]) (DELAY (ABSOLUTE - (PORT clk (1907:1907:1907) (1929:1929:1929)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1572:1572:1572)) - (PORT ena (2122:2122:2122) (2190:2190:2190)) + (PORT clrn (1566:1566:1566) (1558:1558:1558)) + (PORT ena (1212:1212:1212) (1209:1209:1209)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53676,10 +53462,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~7) (DELAY (ABSOLUTE - (PORT datab (244:244:244) (327:327:327)) - (PORT datad (1265:1265:1265) (1355:1355:1355)) + (PORT datab (245:245:245) (327:327:327)) + (PORT datac (765:765:765) (828:828:828)) (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH datac combout (241:241:241) (241:241:241)) ) ) ) @@ -53688,10 +53474,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[12\]) (DELAY (ABSOLUTE - (PORT clk (1907:1907:1907) (1929:1929:1929)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1572:1572:1572)) - (PORT ena (2122:2122:2122) (2190:2190:2190)) + (PORT clrn (1566:1566:1566) (1558:1558:1558)) + (PORT ena (1212:1212:1212) (1209:1209:1209)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53701,47 +53487,16 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|i2s_intf_\|PCM_INR\[14\]\~0) - (DELAY - (ABSOLUTE - (PORT dataa (1406:1406:1406) (1457:1457:1457)) - (PORT datab (896:896:896) (935:935:935)) - (PORT datad (232:232:232) (306:306:306)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|i2s_intf_\|PCM_INR\[14\]) - (DELAY - (ABSOLUTE - (PORT clk (1527:1527:1527) (1540:1540:1540)) - (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1574:1574:1574) (1568:1568:1568)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2s_intf_\|PCM_INL\[14\]\~0) (DELAY (ABSOLUTE - (PORT dataa (1405:1405:1405) (1456:1456:1456)) - (PORT datab (896:896:896) (934:934:934)) - (PORT datad (232:232:232) (306:306:306)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT dataa (501:501:501) (547:547:547)) + (PORT datab (587:587:587) (643:643:643)) + (PORT datad (384:384:384) (441:441:441)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (336:336:336) (342:342:342)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -53752,9 +53507,40 @@ (INSTANCE ula_\|i2s_intf_\|PCM_INL\[14\]) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1540:1540:1540)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1574:1574:1574) (1568:1568:1568)) + (PORT clrn (1566:1566:1566) (1558:1558:1558)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|i2s_intf_\|PCM_INR\[14\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (495:495:495) (542:542:542)) + (PORT datab (585:585:585) (641:641:641)) + (PORT datad (382:382:382) (439:439:439)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|i2s_intf_\|PCM_INR\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT clrn (1566:1566:1566) (1558:1558:1558)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53768,8 +53554,8 @@ (INSTANCE ula_\|pcm_outr\~0) (DELAY (ABSOLUTE - (PORT datac (218:218:218) (296:296:296)) - (PORT datad (219:219:219) (289:289:289)) + (PORT datac (216:216:216) (293:293:293)) + (PORT datad (218:218:218) (286:286:286)) (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -53780,9 +53566,9 @@ (INSTANCE ula_\|pcm_outl\[12\]) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1540:1540:1540)) + (PORT clk (1526:1526:1526) (1538:1538:1538)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (2116:2116:2116) (2146:2146:2146)) + (PORT ena (3548:3548:3548) (3625:3625:3625)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -53796,11 +53582,11 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~6) (DELAY (ABSOLUTE - (PORT datab (1303:1303:1303) (1391:1391:1391)) - (PORT datac (218:218:218) (295:295:295)) - (PORT datad (1337:1337:1337) (1421:1421:1421)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT datab (246:246:246) (330:330:330)) + (PORT datac (749:749:749) (828:828:828)) + (PORT datad (385:385:385) (449:449:449)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53810,10 +53596,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[13\]) (DELAY (ABSOLUTE - (PORT clk (1907:1907:1907) (1929:1929:1929)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1572:1572:1572)) - (PORT ena (2122:2122:2122) (2190:2190:2190)) + (PORT clrn (1566:1566:1566) (1558:1558:1558)) + (PORT ena (1212:1212:1212) (1209:1209:1209)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53823,16 +53609,32 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|pcm_outl\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1515:1515:1515) (1528:1528:1528)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (2394:2394:2394) (2437:2437:2437)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2s_intf_\|shiftreg\~5) (DELAY (ABSOLUTE - (PORT datab (1222:1222:1222) (1334:1334:1334)) - (PORT datac (217:217:217) (292:292:292)) - (PORT datad (1267:1267:1267) (1356:1356:1356)) - (IOPATH datab combout (306:306:306) (311:311:311)) - (IOPATH datac combout (243:243:243) (241:241:241)) + (PORT dataa (247:247:247) (333:333:333)) + (PORT datab (794:794:794) (864:864:864)) + (PORT datad (1954:1954:1954) (2063:2063:2063)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53842,10 +53644,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[14\]) (DELAY (ABSOLUTE - (PORT clk (1907:1907:1907) (1929:1929:1929)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1579:1579:1579) (1572:1572:1572)) - (PORT ena (2122:2122:2122) (2190:2190:2190)) + (PORT clrn (1566:1566:1566) (1558:1558:1558)) + (PORT ena (1212:1212:1212) (1209:1209:1209)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53855,33 +53657,17 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|pcm_outl\[14\]) - (DELAY - (ABSOLUTE - (PORT clk (1524:1524:1524) (1537:1537:1537)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (2262:2262:2262) (2235:2235:2235)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|i2s_intf_\|shiftreg\~4) (DELAY (ABSOLUTE - (PORT dataa (1212:1212:1212) (1296:1296:1296)) - (PORT datac (981:981:981) (1087:1087:1087)) - (PORT datad (656:656:656) (680:680:680)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT dataa (2341:2341:2341) (2498:2498:2498)) + (PORT datab (265:265:265) (347:347:347)) + (PORT datac (756:756:756) (824:824:824)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (243:243:243) (242:242:242)) ) ) ) @@ -53890,10 +53676,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[15\]) (DELAY (ABSOLUTE - (PORT clk (1895:1895:1895) (1927:1927:1927)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1575:1575:1575) (1569:1569:1569)) - (PORT ena (1154:1154:1154) (1136:1136:1136)) + (PORT clrn (1566:1566:1566) (1558:1558:1558)) + (PORT ena (1212:1212:1212) (1209:1209:1209)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53908,10 +53694,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~3) (DELAY (ABSOLUTE - (PORT datac (216:216:216) (293:293:293)) - (PORT datad (656:656:656) (683:683:683)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT dataa (451:451:451) (498:498:498)) + (PORT datac (603:603:603) (664:664:664)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datac combout (243:243:243) (242:242:242)) ) ) ) @@ -53920,10 +53706,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\[16\]) (DELAY (ABSOLUTE - (PORT clk (1528:1528:1528) (1541:1541:1541)) + (PORT clk (1905:1905:1905) (1924:1924:1924)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1575:1575:1575) (1569:1569:1569)) - (PORT ena (1190:1190:1190) (1184:1184:1184)) + (PORT clrn (1567:1567:1567) (1559:1559:1559)) + (PORT ena (1441:1441:1441) (1438:1438:1438)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -53938,10 +53724,10 @@ (INSTANCE ula_\|i2s_intf_\|shiftreg\~0) (DELAY (ABSOLUTE - (PORT datab (243:243:243) (325:325:325)) - (PORT datad (652:652:652) (681:681:681)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT dataa (245:245:245) (332:332:332)) + (PORT datac (416:416:416) (458:458:458)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (241:241:241)) ) ) ) @@ -53951,9 +53737,9 @@ (DELAY (ABSOLUTE (PORT clk (1508:1508:1508) (1530:1530:1530)) - (PORT d (1487:1487:1487) (1588:1588:1588)) - (PORT clrn (1765:1765:1765) (1817:1817:1817)) - (PORT ena (1717:1717:1717) (1806:1806:1806)) + (PORT d (899:899:899) (948:948:948)) + (PORT clrn (1752:1752:1752) (1802:1802:1802)) + (PORT ena (887:887:887) (888:888:888)) (IOPATH (posedge clk) q (586:586:586) (589:589:589)) (IOPATH (negedge clrn) q (712:712:712) (715:715:715)) ) @@ -53967,16 +53753,57 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|LessThan2\~0) + (INSTANCE ula_\|border\[1\]\~feeder) (DELAY (ABSOLUTE - (PORT dataa (291:291:291) (381:381:381)) - (PORT datab (270:270:270) (353:353:353)) - (PORT datac (262:262:262) (341:341:341)) - (PORT datad (244:244:244) (316:316:316)) + (PORT datad (217:217:217) (243:243:243)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|border\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1943:1943:1943) (1924:1924:1924)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|LessThan4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (449:449:449) (514:514:514)) + (PORT datab (272:272:272) (357:357:357)) + (PORT datac (242:242:242) (321:321:321)) + (PORT datad (243:243:243) (313:313:313)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|screen_en\~0) + (DELAY + (ABSOLUTE + (PORT dataa (444:444:444) (511:511:511)) + (PORT datab (269:269:269) (352:352:352)) + (PORT datad (309:309:309) (327:327:327)) (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -53986,10 +53813,57 @@ (INSTANCE ula_\|video_\|LessThan6\~0) (DELAY (ABSOLUTE - (PORT dataa (263:263:263) (348:348:348)) - (PORT datab (260:260:260) (342:342:342)) - (PORT datac (255:255:255) (332:332:332)) - (PORT datad (237:237:237) (307:307:307)) + (PORT dataa (262:262:262) (348:348:348)) + (PORT datab (261:261:261) (342:342:342)) + (PORT datad (238:238:238) (307:307:307)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|LessThan6\~1) + (DELAY + (ABSOLUTE + (PORT dataa (283:283:283) (370:370:370)) + (PORT datab (281:281:281) (364:364:364)) + (PORT datac (236:236:236) (313:313:313)) + (PORT datad (338:338:338) (357:357:357)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|screen_en\~1) + (DELAY + (ABSOLUTE + (PORT dataa (413:413:413) (492:492:492)) + (PORT datab (463:463:463) (525:525:525)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (174:174:174) (198:198:198)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|LessThan2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (655:655:655) (724:724:724)) + (PORT datab (290:290:290) (376:376:376)) + (PORT datac (424:424:424) (483:483:483)) + (PORT datad (385:385:385) (444:444:444)) (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -54002,12 +53876,12 @@ (INSTANCE ula_\|video_\|LessThan2\~1) (DELAY (ABSOLUTE - (PORT dataa (457:457:457) (540:540:540)) - (PORT datab (270:270:270) (354:354:354)) - (PORT datac (173:173:173) (207:207:207)) - (PORT datad (356:356:356) (374:374:374)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (333:333:333) (332:332:332)) + (PORT dataa (641:641:641) (708:708:708)) + (PORT datab (415:415:415) (493:493:493)) + (PORT datac (172:172:172) (205:205:205)) + (PORT datad (205:205:205) (235:235:235)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -54018,12 +53892,13 @@ (INSTANCE ula_\|video_\|LessThan3\~0) (DELAY (ABSOLUTE - (PORT dataa (291:291:291) (383:383:383)) - (PORT datab (241:241:241) (280:280:280)) - (PORT datad (195:195:195) (221:221:221)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (353:353:353) (369:369:369)) + (PORT dataa (624:624:624) (700:700:700)) + (PORT datab (228:228:228) (271:271:271)) + (PORT datac (620:620:620) (685:685:685)) + (PORT datad (194:194:194) (219:219:219)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (306:306:306) (308:308:308)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54033,11 +53908,10 @@ (INSTANCE ula_\|video_\|LessThan0\~0) (DELAY (ABSOLUTE - (PORT dataa (271:271:271) (361:361:361)) - (PORT datab (261:261:261) (343:343:343)) - (PORT datad (247:247:247) (320:320:320)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) + (PORT datab (269:269:269) (352:352:352)) + (PORT datad (246:246:246) (318:318:318)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54047,11 +53921,11 @@ (INSTANCE ula_\|video_\|disp_enable\~0) (DELAY (ABSOLUTE - (PORT dataa (199:199:199) (242:242:242)) - (PORT datab (410:410:410) (484:484:484)) - (PORT datad (659:659:659) (717:717:717)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (PORT dataa (274:274:274) (364:364:364)) + (PORT datab (437:437:437) (511:511:511)) + (PORT datad (172:172:172) (197:197:197)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -54062,100 +53936,21 @@ (INSTANCE ula_\|video_\|disp_enable\~1) (DELAY (ABSOLUTE - (PORT dataa (211:211:211) (260:260:260)) - (PORT datab (207:207:207) (248:248:248)) - (PORT datad (348:348:348) (371:371:371)) + (PORT dataa (208:208:208) (254:254:254)) + (PORT datab (206:206:206) (247:247:247)) + (PORT datad (516:516:516) (530:530:530)) (IOPATH dataa combout (325:325:325) (328:328:328)) (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|border\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1527:1527:1527) (1540:1540:1540)) - (PORT asdata (537:537:537) (568:568:568)) - (PORT ena (2116:2116:2116) (2146:2146:2146)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|LessThan6\~1) + (INSTANCE ula_\|video_\|attr_prefetch\[7\]\~feeder) (DELAY (ABSOLUTE - (PORT dataa (453:453:453) (541:541:541)) - (PORT datab (461:461:461) (551:551:551)) - (PORT datac (424:424:424) (504:504:504)) - (PORT datad (416:416:416) (444:444:444)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH datab combout (381:381:381) (380:380:380)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|LessThan4\~0) - (DELAY - (ABSOLUTE - (PORT dataa (271:271:271) (361:361:361)) - (PORT datab (273:273:273) (358:358:358)) - (PORT datad (236:236:236) (304:304:304)) - (IOPATH dataa combout (301:301:301) (299:299:299)) - (IOPATH datab combout (300:300:300) (308:308:308)) - (IOPATH datac combout (353:353:353) (369:369:369)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|screen_en\~0) - (DELAY - (ABSOLUTE - (PORT dataa (446:446:446) (522:522:522)) - (PORT datab (461:461:461) (542:542:542)) - (PORT datac (543:543:543) (561:561:561)) - (PORT datad (646:646:646) (718:718:718)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|screen_en\~1) - (DELAY - (ABSOLUTE - (PORT dataa (683:683:683) (744:744:744)) - (PORT datab (483:483:483) (561:561:561)) - (PORT datac (172:172:172) (205:205:205)) - (PORT datad (174:174:174) (199:199:199)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (336:336:336) (325:325:325)) - (IOPATH datac combout (241:241:241) (242:242:242)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|attr_prefetch\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1472:1472:1472) (1505:1505:1505)) + (PORT datad (1377:1377:1377) (1378:1378:1378)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54165,10 +53960,10 @@ (INSTANCE ula_\|video_\|Decoder0\~1) (DELAY (ABSOLUTE - (PORT dataa (1252:1252:1252) (1343:1343:1343)) - (PORT datab (984:984:984) (1066:1066:1066)) - (PORT datac (973:973:973) (1043:1043:1043)) - (PORT datad (280:280:280) (364:364:364)) + (PORT dataa (773:773:773) (856:856:856)) + (PORT datab (754:754:754) (825:825:825)) + (PORT datac (1155:1155:1155) (1215:1215:1215)) + (PORT datad (683:683:683) (750:750:750)) (IOPATH dataa combout (327:327:327) (347:347:347)) (IOPATH datab combout (331:331:331) (342:342:342)) (IOPATH datac combout (243:243:243) (241:241:241)) @@ -54178,12 +53973,12 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr_prefetch\[1\]) + (INSTANCE ula_\|video_\|attr_prefetch\[7\]) (DELAY (ABSOLUTE - (PORT clk (1944:1944:1944) (1969:1969:1969)) + (PORT clk (1933:1933:1933) (1959:1959:1959)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1465:1465:1465) (1443:1443:1443)) + (PORT ena (1402:1402:1402) (1376:1376:1376)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54197,10 +53992,10 @@ (INSTANCE ula_\|video_\|Decoder0\~0) (DELAY (ABSOLUTE - (PORT dataa (1252:1252:1252) (1342:1342:1342)) - (PORT datab (985:985:985) (1065:1065:1065)) - (PORT datac (974:974:974) (1042:1042:1042)) - (PORT datad (280:280:280) (364:364:364)) + (PORT dataa (764:764:764) (844:844:844)) + (PORT datab (749:749:749) (818:818:818)) + (PORT datac (1162:1162:1162) (1223:1223:1223)) + (PORT datad (687:687:687) (756:756:756)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -54208,98 +54003,14 @@ ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1536:1536:1536) (1548:1548:1548)) - (PORT asdata (1788:1788:1788) (1847:1847:1847)) - (PORT ena (1421:1421:1421) (1414:1414:1414)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|attr_prefetch\[4\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1546:1546:1546) (1544:1544:1544)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr_prefetch\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1944:1944:1944) (1969:1969:1969)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1465:1465:1465) (1443:1443:1443)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1536:1536:1536) (1548:1548:1548)) - (PORT asdata (1012:1012:1012) (1085:1085:1085)) - (PORT ena (1421:1421:1421) (1414:1414:1414)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|attr_prefetch\[7\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (1196:1196:1196) (1239:1239:1239)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr_prefetch\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1944:1944:1944) (1969:1969:1969)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1465:1465:1465) (1443:1443:1443)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|video_\|attr\[7\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1549:1549:1549)) - (PORT asdata (1010:1010:1010) (1078:1078:1078)) - (PORT ena (1428:1428:1428) (1418:1418:1418)) + (PORT clk (1536:1536:1536) (1548:1548:1548)) + (PORT asdata (769:769:769) (839:839:839)) + (PORT ena (1446:1446:1446) (1427:1427:1427)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54313,9 +54024,9 @@ (INSTANCE ula_\|video_\|frame\[0\]\~12) (DELAY (ABSOLUTE - (PORT dataa (620:620:620) (643:643:643)) - (IOPATH dataa combout (356:356:356) (368:368:368)) + (PORT datad (587:587:587) (602:602:602)) (IOPATH datac combout (353:353:353) (369:369:369)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -54324,7 +54035,7 @@ (INSTANCE ula_\|video_\|frame\[0\]) (DELAY (ABSOLUTE - (PORT clk (1539:1539:1539) (1551:1551:1551)) + (PORT clk (1537:1537:1537) (1549:1549:1549)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -54338,7 +54049,7 @@ (INSTANCE ula_\|video_\|frame\[1\]\~4) (DELAY (ABSOLUTE - (PORT dataa (613:613:613) (667:667:667)) + (PORT dataa (841:841:841) (891:891:891)) (PORT datab (243:243:243) (325:325:325)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH dataa cout (436:436:436) (315:315:315)) @@ -54353,9 +54064,9 @@ (INSTANCE ula_\|video_\|frame\[1\]) (DELAY (ABSOLUTE - (PORT clk (1538:1538:1538) (1551:1551:1551)) + (PORT clk (1538:1538:1538) (1550:1550:1550)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1236:1236:1236) (1237:1237:1237)) + (PORT ena (1722:1722:1722) (1716:1716:1716)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54369,9 +54080,9 @@ (INSTANCE ula_\|video_\|frame\[2\]\~6) (DELAY (ABSOLUTE - (PORT dataa (244:244:244) (331:331:331)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (243:243:243) (325:325:325)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -54383,9 +54094,9 @@ (INSTANCE ula_\|video_\|frame\[2\]) (DELAY (ABSOLUTE - (PORT clk (1538:1538:1538) (1551:1551:1551)) + (PORT clk (1538:1538:1538) (1550:1550:1550)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1236:1236:1236) (1237:1237:1237)) + (PORT ena (1722:1722:1722) (1716:1716:1716)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54399,7 +54110,7 @@ (INSTANCE ula_\|video_\|frame\[3\]\~8) (DELAY (ABSOLUTE - (PORT datab (242:242:242) (324:324:324)) + (PORT datab (243:243:243) (325:325:325)) (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -54413,9 +54124,9 @@ (INSTANCE ula_\|video_\|frame\[3\]) (DELAY (ABSOLUTE - (PORT clk (1538:1538:1538) (1551:1551:1551)) + (PORT clk (1538:1538:1538) (1550:1550:1550)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1236:1236:1236) (1237:1237:1237)) + (PORT ena (1722:1722:1722) (1716:1716:1716)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54429,20 +54140,30 @@ (INSTANCE ula_\|video_\|frame\[4\]\~10) (DELAY (ABSOLUTE - (PORT dataa (266:266:266) (353:353:353)) - (IOPATH dataa combout (356:356:356) (368:368:368)) + (PORT datad (688:688:688) (754:754:754)) + (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|frame\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (533:533:533) (544:544:544)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|video_\|frame\[4\]) (DELAY (ABSOLUTE - (PORT clk (1538:1538:1538) (1551:1551:1551)) + (PORT clk (1536:1536:1536) (1548:1548:1548)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1236:1236:1236) (1237:1237:1237)) + (PORT ena (1155:1155:1155) (1132:1132:1132)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54456,7 +54177,7 @@ (INSTANCE ula_\|video_\|inverted) (DELAY (ABSOLUTE - (PORT datad (372:372:372) (423:423:423)) + (PORT datad (239:239:239) (308:308:308)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -54467,8 +54188,8 @@ (INSTANCE ula_\|video_\|bits_prefetch\[6\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (1154:1154:1154) (1160:1160:1160)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT datac (1456:1456:1456) (1512:1512:1512)) + (IOPATH datac combout (243:243:243) (242:242:242)) ) ) ) @@ -54477,13 +54198,13 @@ (INSTANCE ula_\|video_\|Decoder0\~2) (DELAY (ABSOLUTE - (PORT dataa (1252:1252:1252) (1340:1340:1340)) - (PORT datab (986:986:986) (1064:1064:1064)) - (PORT datac (973:973:973) (1044:1044:1044)) - (PORT datad (279:279:279) (363:363:363)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (766:766:766) (847:847:847)) + (PORT datab (750:750:750) (821:821:821)) + (PORT datac (1157:1157:1157) (1222:1222:1222)) + (PORT datad (683:683:683) (754:754:754)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54493,9 +54214,9 @@ (INSTANCE ula_\|video_\|bits_prefetch\[6\]) (DELAY (ABSOLUTE - (PORT clk (1915:1915:1915) (1933:1933:1933)) + (PORT clk (1904:1904:1904) (1922:1922:1922)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1455:1455:1455) (1444:1444:1444)) + (PORT ena (1467:1467:1467) (1441:1441:1441)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54504,29 +54225,19 @@ (HOLD ena (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|bits\[6\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (609:609:609) (678:678:678)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE ula_\|video_\|bits\[6\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1549:1549:1549)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1428:1428:1428) (1418:1418:1418)) + (PORT clk (1536:1536:1536) (1548:1548:1548)) + (PORT asdata (929:929:929) (984:984:984)) + (PORT ena (1446:1446:1446) (1427:1427:1427)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) + (HOLD asdata (posedge clk) (157:157:157)) (HOLD ena (posedge clk) (157:157:157)) ) ) @@ -54535,7 +54246,7 @@ (INSTANCE ula_\|video_\|bits_prefetch\[4\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (1545:1545:1545) (1541:1541:1541)) + (PORT datad (1765:1765:1765) (1863:1863:1863)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54545,9 +54256,9 @@ (INSTANCE ula_\|video_\|bits_prefetch\[4\]) (DELAY (ABSOLUTE - (PORT clk (1915:1915:1915) (1933:1933:1933)) + (PORT clk (1904:1904:1904) (1922:1922:1922)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1455:1455:1455) (1444:1444:1444)) + (PORT ena (1467:1467:1467) (1441:1441:1441)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54561,9 +54272,9 @@ (INSTANCE ula_\|video_\|bits\[4\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1549:1549:1549)) - (PORT asdata (997:997:997) (1070:1070:1070)) - (PORT ena (1428:1428:1428) (1418:1418:1418)) + (PORT clk (1536:1536:1536) (1548:1548:1548)) + (PORT asdata (738:738:738) (812:812:812)) + (PORT ena (1446:1446:1446) (1427:1427:1427)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54577,7 +54288,7 @@ (INSTANCE ula_\|video_\|bits_prefetch\[5\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (937:937:937) (955:955:955)) + (PORT datad (826:826:826) (849:849:849)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54587,9 +54298,9 @@ (INSTANCE ula_\|video_\|bits_prefetch\[5\]) (DELAY (ABSOLUTE - (PORT clk (1915:1915:1915) (1933:1933:1933)) + (PORT clk (1904:1904:1904) (1922:1922:1922)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1455:1455:1455) (1444:1444:1444)) + (PORT ena (1467:1467:1467) (1441:1441:1441)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54603,7 +54314,7 @@ (INSTANCE ula_\|video_\|bits\[5\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (651:651:651) (725:725:725)) + (PORT datad (420:420:420) (492:492:492)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54613,9 +54324,9 @@ (INSTANCE ula_\|video_\|bits\[5\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1549:1549:1549)) + (PORT clk (1536:1536:1536) (1548:1548:1548)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1428:1428:1428) (1418:1418:1418)) + (PORT ena (1446:1446:1446) (1427:1427:1427)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54629,7 +54340,7 @@ (INSTANCE ula_\|video_\|bits_prefetch\[7\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (1201:1201:1201) (1243:1243:1243)) + (PORT datad (1377:1377:1377) (1381:1381:1381)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54639,9 +54350,9 @@ (INSTANCE ula_\|video_\|bits_prefetch\[7\]) (DELAY (ABSOLUTE - (PORT clk (1915:1915:1915) (1933:1933:1933)) + (PORT clk (1904:1904:1904) (1922:1922:1922)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1455:1455:1455) (1444:1444:1444)) + (PORT ena (1467:1467:1467) (1441:1441:1441)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54655,9 +54366,9 @@ (INSTANCE ula_\|video_\|bits\[7\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1549:1549:1549)) - (PORT asdata (1216:1216:1216) (1295:1295:1295)) - (PORT ena (1428:1428:1428) (1418:1418:1418)) + (PORT clk (1536:1536:1536) (1548:1548:1548)) + (PORT asdata (768:768:768) (840:840:840)) + (PORT ena (1446:1446:1446) (1427:1427:1427)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54671,11 +54382,11 @@ (INSTANCE ula_\|video_\|Mux0\~0) (DELAY (ABSOLUTE - (PORT dataa (385:385:385) (460:460:460)) - (PORT datab (288:288:288) (377:377:377)) - (PORT datad (636:636:636) (698:698:698)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT dataa (244:244:244) (330:330:330)) + (PORT datab (620:620:620) (682:682:682)) + (PORT datad (607:607:607) (663:663:663)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -54686,9 +54397,9 @@ (INSTANCE ula_\|video_\|Mux0\~1) (DELAY (ABSOLUTE - (PORT dataa (244:244:244) (330:330:330)) - (PORT datab (287:287:287) (374:374:374)) - (PORT datad (175:175:175) (201:201:201)) + (PORT dataa (629:629:629) (697:697:697)) + (PORT datab (418:418:418) (498:498:498)) + (PORT datad (174:174:174) (198:198:198)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -54701,7 +54412,7 @@ (INSTANCE ula_\|video_\|bits_prefetch\[2\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (883:883:883) (890:890:890)) + (PORT datad (1741:1741:1741) (1810:1810:1810)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54711,9 +54422,9 @@ (INSTANCE ula_\|video_\|bits_prefetch\[2\]) (DELAY (ABSOLUTE - (PORT clk (1915:1915:1915) (1933:1933:1933)) + (PORT clk (1904:1904:1904) (1922:1922:1922)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1455:1455:1455) (1444:1444:1444)) + (PORT ena (1467:1467:1467) (1441:1441:1441)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54727,7 +54438,7 @@ (INSTANCE ula_\|video_\|bits\[2\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (640:640:640) (711:711:711)) + (PORT datad (581:581:581) (639:639:639)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54737,9 +54448,9 @@ (INSTANCE ula_\|video_\|bits\[2\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1549:1549:1549)) + (PORT clk (1536:1536:1536) (1548:1548:1548)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1428:1428:1428) (1418:1418:1418)) + (PORT ena (1446:1446:1446) (1427:1427:1427)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54753,7 +54464,7 @@ (INSTANCE ula_\|video_\|bits_prefetch\[0\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (1463:1463:1463) (1429:1429:1429)) + (PORT datad (1510:1510:1510) (1493:1493:1493)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54763,9 +54474,9 @@ (INSTANCE ula_\|video_\|bits_prefetch\[0\]) (DELAY (ABSOLUTE - (PORT clk (1915:1915:1915) (1933:1933:1933)) + (PORT clk (1904:1904:1904) (1922:1922:1922)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1455:1455:1455) (1444:1444:1444)) + (PORT ena (1467:1467:1467) (1441:1441:1441)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54779,9 +54490,9 @@ (INSTANCE ula_\|video_\|bits\[0\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1549:1549:1549)) - (PORT asdata (978:978:978) (1047:1047:1047)) - (PORT ena (1428:1428:1428) (1418:1418:1418)) + (PORT clk (1536:1536:1536) (1548:1548:1548)) + (PORT asdata (1454:1454:1454) (1504:1504:1504)) + (PORT ena (1446:1446:1446) (1427:1427:1427)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54795,7 +54506,7 @@ (INSTANCE ula_\|video_\|bits_prefetch\[1\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (1470:1470:1470) (1502:1502:1502)) + (PORT datad (870:870:870) (874:874:874)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54805,9 +54516,9 @@ (INSTANCE ula_\|video_\|bits_prefetch\[1\]) (DELAY (ABSOLUTE - (PORT clk (1915:1915:1915) (1933:1933:1933)) + (PORT clk (1904:1904:1904) (1922:1922:1922)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1455:1455:1455) (1444:1444:1444)) + (PORT ena (1467:1467:1467) (1441:1441:1441)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54821,7 +54532,7 @@ (INSTANCE ula_\|video_\|bits\[1\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (642:642:642) (704:704:704)) + (PORT datad (402:402:402) (473:473:473)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54831,9 +54542,9 @@ (INSTANCE ula_\|video_\|bits\[1\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1549:1549:1549)) + (PORT clk (1536:1536:1536) (1548:1548:1548)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1428:1428:1428) (1418:1418:1418)) + (PORT ena (1446:1446:1446) (1427:1427:1427)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54847,7 +54558,7 @@ (INSTANCE ula_\|video_\|bits_prefetch\[3\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (1276:1276:1276) (1241:1241:1241)) + (PORT datad (1411:1411:1411) (1456:1456:1456)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54857,9 +54568,9 @@ (INSTANCE ula_\|video_\|bits_prefetch\[3\]) (DELAY (ABSOLUTE - (PORT clk (1915:1915:1915) (1933:1933:1933)) + (PORT clk (1904:1904:1904) (1922:1922:1922)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1455:1455:1455) (1444:1444:1444)) + (PORT ena (1467:1467:1467) (1441:1441:1441)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54873,9 +54584,9 @@ (INSTANCE ula_\|video_\|bits\[3\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1549:1549:1549)) - (PORT asdata (1448:1448:1448) (1474:1474:1474)) - (PORT ena (1428:1428:1428) (1418:1418:1418)) + (PORT clk (1536:1536:1536) (1548:1548:1548)) + (PORT asdata (738:738:738) (813:813:813)) + (PORT ena (1446:1446:1446) (1427:1427:1427)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54889,11 +54600,11 @@ (INSTANCE ula_\|video_\|Mux0\~2) (DELAY (ABSOLUTE - (PORT dataa (242:242:242) (328:328:328)) - (PORT datab (286:286:286) (373:373:373)) - (PORT datad (633:633:633) (694:694:694)) - (IOPATH dataa combout (304:304:304) (299:299:299)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT dataa (629:629:629) (697:697:697)) + (PORT datab (242:242:242) (325:325:325)) + (PORT datad (594:594:594) (647:647:647)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -54904,9 +54615,9 @@ (INSTANCE ula_\|video_\|Mux0\~3) (DELAY (ABSOLUTE - (PORT dataa (243:243:243) (329:329:329)) - (PORT datab (287:287:287) (377:377:377)) - (PORT datad (175:175:175) (201:201:201)) + (PORT dataa (625:625:625) (695:695:695)) + (PORT datab (382:382:382) (456:456:456)) + (PORT datad (174:174:174) (199:199:199)) (IOPATH dataa combout (339:339:339) (367:367:367)) (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -54919,25 +54630,109 @@ (INSTANCE ula_\|video_\|cindex\[1\]\~0) (DELAY (ABSOLUTE - (PORT dataa (401:401:401) (477:477:477)) - (PORT datab (198:198:198) (237:237:237)) + (PORT dataa (200:200:200) (244:244:244)) + (PORT datab (641:641:641) (704:704:704)) (PORT datac (173:173:173) (206:206:206)) (PORT datad (173:173:173) (199:199:199)) - (IOPATH dataa combout (337:337:337) (347:347:347)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datab combout (337:337:337) (348:348:348)) (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|attr_prefetch\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1766:1766:1766) (1863:1863:1863)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr_prefetch\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1933:1933:1933) (1959:1959:1959)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1402:1402:1402) (1376:1376:1376)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1536:1536:1536) (1549:1549:1549)) + (PORT asdata (979:979:979) (1037:1037:1037)) + (PORT ena (1455:1455:1455) (1436:1436:1436)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|attr_prefetch\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (871:871:871) (877:877:877)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr_prefetch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1933:1933:1933) (1959:1959:1959)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1402:1402:1402) (1376:1376:1376)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1536:1536:1536) (1549:1549:1549)) + (PORT asdata (1530:1530:1530) (1600:1600:1600)) + (PORT ena (1455:1455:1455) (1436:1436:1436)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE ula_\|video_\|cindex\[1\]\~1) (DELAY (ABSOLUTE - (PORT dataa (245:245:245) (332:332:332)) - (PORT datad (347:347:347) (363:363:363)) - (IOPATH dataa combout (304:304:304) (308:308:308)) + (PORT dataa (372:372:372) (412:412:412)) + (PORT datad (217:217:217) (285:285:285)) + (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -54948,13 +54743,13 @@ (INSTANCE ula_\|video_\|VGA_R\[0\]\~0) (DELAY (ABSOLUTE - (PORT dataa (398:398:398) (453:453:453)) - (PORT datab (1490:1490:1490) (1585:1585:1585)) - (PORT datac (235:235:235) (278:278:278)) - (PORT datad (180:180:180) (208:208:208)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (2638:2638:2638) (2746:2746:2746)) + (PORT datab (365:365:365) (401:401:401)) + (PORT datac (591:591:591) (601:601:601)) + (PORT datad (181:181:181) (209:209:209)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -54964,8 +54759,8 @@ (INSTANCE ula_\|video_\|attr_prefetch\[6\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (1157:1157:1157) (1161:1161:1161)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT datac (1456:1456:1456) (1515:1515:1515)) + (IOPATH datac combout (243:243:243) (242:242:242)) ) ) ) @@ -54974,9 +54769,9 @@ (INSTANCE ula_\|video_\|attr_prefetch\[6\]) (DELAY (ABSOLUTE - (PORT clk (1944:1944:1944) (1969:1969:1969)) + (PORT clk (1933:1933:1933) (1959:1959:1959)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1465:1465:1465) (1443:1443:1443)) + (PORT ena (1402:1402:1402) (1376:1376:1376)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -54990,9 +54785,9 @@ (INSTANCE ula_\|video_\|attr\[6\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) - (PORT asdata (1216:1216:1216) (1269:1269:1269)) - (PORT ena (1638:1638:1638) (1616:1616:1616)) + (PORT clk (1536:1536:1536) (1549:1549:1549)) + (PORT asdata (967:967:967) (1031:1031:1031)) + (PORT ena (1455:1455:1455) (1436:1436:1436)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -55006,9 +54801,9 @@ (INSTANCE ula_\|video_\|VGA_B\[1\]\~0) (DELAY (ABSOLUTE - (PORT dataa (212:212:212) (261:261:261)) - (PORT datab (208:208:208) (249:249:249)) - (PORT datad (348:348:348) (371:371:371)) + (PORT dataa (208:208:208) (255:255:255)) + (PORT datab (207:207:207) (248:248:248)) + (PORT datad (516:516:516) (531:531:531)) (IOPATH dataa combout (324:324:324) (328:328:328)) (IOPATH datab combout (306:306:306) (308:308:308)) (IOPATH datac combout (353:353:353) (369:369:369)) @@ -55021,11 +54816,11 @@ (INSTANCE ula_\|video_\|VGA_R\[1\]\~1) (DELAY (ABSOLUTE - (PORT dataa (269:269:269) (322:322:322)) - (PORT datac (391:391:391) (430:430:430)) - (PORT datad (180:180:180) (208:208:208)) - (IOPATH dataa combout (304:304:304) (307:307:307)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (1284:1284:1284) (1303:1303:1303)) + (PORT datab (222:222:222) (262:262:262)) + (PORT datad (181:181:181) (209:209:209)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -55035,51 +54830,9 @@ (INSTANCE ula_\|border\[2\]) (DELAY (ABSOLUTE - (PORT clk (1521:1521:1521) (1535:1535:1535)) - (PORT asdata (956:956:956) (977:977:977)) - (PORT ena (812:812:812) (804:804:804)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE ula_\|video_\|attr_prefetch\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (884:884:884) (889:889:889)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr_prefetch\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1944:1944:1944) (1969:1969:1969)) - (PORT d (74:74:74) (91:91:91)) - (PORT ena (1465:1465:1465) (1443:1443:1443)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - (HOLD ena (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE ula_\|video_\|attr\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1537:1537:1537) (1549:1549:1549)) - (PORT asdata (1208:1208:1208) (1265:1265:1265)) - (PORT ena (1428:1428:1428) (1418:1418:1418)) + (PORT clk (1518:1518:1518) (1532:1532:1532)) + (PORT asdata (1885:1885:1885) (1886:1886:1886)) + (PORT ena (1943:1943:1943) (1924:1924:1924)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -55093,7 +54846,7 @@ (INSTANCE ula_\|video_\|attr_prefetch\[5\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (935:935:935) (952:952:952)) + (PORT datad (826:826:826) (849:849:849)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -55103,9 +54856,9 @@ (INSTANCE ula_\|video_\|attr_prefetch\[5\]) (DELAY (ABSOLUTE - (PORT clk (1944:1944:1944) (1969:1969:1969)) + (PORT clk (1933:1933:1933) (1959:1959:1959)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1465:1465:1465) (1443:1443:1443)) + (PORT ena (1402:1402:1402) (1376:1376:1376)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -55119,9 +54872,51 @@ (INSTANCE ula_\|video_\|attr\[5\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1549:1549:1549)) - (PORT asdata (993:993:993) (1051:1051:1051)) - (PORT ena (1428:1428:1428) (1418:1418:1418)) + (PORT clk (1536:1536:1536) (1549:1549:1549)) + (PORT asdata (1027:1027:1027) (1097:1097:1097)) + (PORT ena (1455:1455:1455) (1436:1436:1436)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE ula_\|video_\|attr_prefetch\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1744:1744:1744) (1810:1810:1810)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr_prefetch\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1933:1933:1933) (1959:1959:1959)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (1402:1402:1402) (1376:1376:1376)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE ula_\|video_\|attr\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1536:1536:1536) (1549:1549:1549)) + (PORT asdata (1392:1392:1392) (1436:1436:1436)) + (PORT ena (1455:1455:1455) (1436:1436:1436)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -55135,9 +54930,9 @@ (INSTANCE ula_\|video_\|cindex\[2\]\~2) (DELAY (ABSOLUTE - (PORT datab (242:242:242) (324:324:324)) - (PORT datad (203:203:203) (232:232:232)) - (IOPATH datab combout (306:306:306) (311:311:311)) + (PORT dataa (371:371:371) (413:413:413)) + (PORT datad (217:217:217) (286:286:286)) + (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -55148,10 +54943,10 @@ (INSTANCE ula_\|video_\|VGA_G\[0\]\~0) (DELAY (ABSOLUTE - (PORT dataa (2313:2313:2313) (2480:2480:2480)) - (PORT datab (411:411:411) (449:449:449)) - (PORT datac (384:384:384) (420:420:420)) - (PORT datad (547:547:547) (557:557:557)) + (PORT dataa (2643:2643:2643) (2790:2790:2790)) + (PORT datab (366:366:366) (401:401:401)) + (PORT datac (591:591:591) (600:600:600)) + (PORT datad (180:180:180) (208:208:208)) (IOPATH dataa combout (341:341:341) (319:319:319)) (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datac combout (243:243:243) (242:242:242)) @@ -55164,9 +54959,9 @@ (INSTANCE ula_\|video_\|VGA_G\[1\]\~1) (DELAY (ABSOLUTE - (PORT dataa (636:636:636) (662:662:662)) - (PORT datab (221:221:221) (261:261:261)) - (PORT datad (378:378:378) (398:398:398)) + (PORT dataa (841:841:841) (856:856:856)) + (PORT datab (367:367:367) (405:405:405)) + (PORT datad (181:181:181) (210:210:210)) (IOPATH dataa combout (300:300:300) (308:308:308)) (IOPATH datab combout (300:300:300) (311:311:311)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -55178,9 +54973,9 @@ (INSTANCE ula_\|border\[0\]) (DELAY (ABSOLUTE - (PORT clk (1527:1527:1527) (1540:1540:1540)) - (PORT asdata (1466:1466:1466) (1519:1519:1519)) - (PORT ena (2116:2116:2116) (2146:2146:2146)) + (PORT clk (1515:1515:1515) (1528:1528:1528)) + (PORT asdata (3345:3345:3345) (3552:3552:3552)) + (PORT ena (2394:2394:2394) (2437:2437:2437)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -55194,7 +54989,7 @@ (INSTANCE ula_\|video_\|attr_prefetch\[0\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (1462:1462:1462) (1430:1430:1430)) + (PORT datad (1513:1513:1513) (1495:1495:1495)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -55204,9 +54999,9 @@ (INSTANCE ula_\|video_\|attr_prefetch\[0\]) (DELAY (ABSOLUTE - (PORT clk (1944:1944:1944) (1969:1969:1969)) + (PORT clk (1933:1933:1933) (1959:1959:1959)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1465:1465:1465) (1443:1443:1443)) + (PORT ena (1402:1402:1402) (1376:1376:1376)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -55220,7 +55015,7 @@ (INSTANCE ula_\|video_\|attr\[0\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (839:839:839) (888:888:888)) + (PORT datad (624:624:624) (687:687:687)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -55232,7 +55027,7 @@ (ABSOLUTE (PORT clk (1536:1536:1536) (1548:1548:1548)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1421:1421:1421) (1414:1414:1414)) + (PORT ena (1446:1446:1446) (1427:1427:1427)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -55246,7 +55041,7 @@ (INSTANCE ula_\|video_\|attr_prefetch\[3\]\~feeder) (DELAY (ABSOLUTE - (PORT datad (1276:1276:1276) (1242:1242:1242)) + (PORT datad (1412:1412:1412) (1456:1456:1456)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -55256,9 +55051,9 @@ (INSTANCE ula_\|video_\|attr_prefetch\[3\]) (DELAY (ABSOLUTE - (PORT clk (1944:1944:1944) (1969:1969:1969)) + (PORT clk (1933:1933:1933) (1959:1959:1959)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (1465:1465:1465) (1443:1443:1443)) + (PORT ena (1402:1402:1402) (1376:1376:1376)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -55272,9 +55067,9 @@ (INSTANCE ula_\|video_\|attr\[3\]) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1549:1549:1549)) - (PORT asdata (965:965:965) (1040:1040:1040)) - (PORT ena (1428:1428:1428) (1418:1418:1418)) + (PORT clk (1536:1536:1536) (1548:1548:1548)) + (PORT asdata (772:772:772) (846:846:846)) + (PORT ena (1446:1446:1446) (1427:1427:1427)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) @@ -55288,9 +55083,9 @@ (INSTANCE ula_\|video_\|cindex\[0\]\~3) (DELAY (ABSOLUTE - (PORT datab (384:384:384) (459:459:459)) - (PORT datad (204:204:204) (232:232:232)) - (IOPATH datab combout (306:306:306) (311:311:311)) + (PORT dataa (244:244:244) (330:330:330)) + (PORT datad (195:195:195) (221:221:221)) + (IOPATH dataa combout (304:304:304) (308:308:308)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -55301,13 +55096,13 @@ (INSTANCE ula_\|video_\|VGA_B\[0\]\~1) (DELAY (ABSOLUTE - (PORT dataa (399:399:399) (453:453:453)) - (PORT datab (1662:1662:1662) (1745:1745:1745)) - (PORT datac (233:233:233) (279:279:279)) - (PORT datad (334:334:334) (354:354:354)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH datab combout (344:344:344) (369:369:369)) - (IOPATH datac combout (241:241:241) (242:242:242)) + (PORT dataa (588:588:588) (614:614:614)) + (PORT datab (2087:2087:2087) (2265:2265:2265)) + (PORT datac (317:317:317) (337:337:337)) + (PORT datad (181:181:181) (209:209:209)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH datab combout (342:342:342) (318:318:318)) + (IOPATH datac combout (243:243:243) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -55317,9 +55112,9 @@ (INSTANCE ula_\|video_\|VGA_B\[1\]\~2) (DELAY (ABSOLUTE - (PORT dataa (269:269:269) (323:323:323)) - (PORT datac (391:391:391) (429:429:429)) - (PORT datad (340:340:340) (359:359:359)) + (PORT dataa (586:586:586) (617:617:617)) + (PORT datac (561:561:561) (576:576:576)) + (PORT datad (180:180:180) (208:208:208)) (IOPATH dataa combout (304:304:304) (307:307:307)) (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) @@ -55331,11 +55126,11 @@ (INSTANCE ula_\|video_\|Equal0\~2) (DELAY (ABSOLUTE - (PORT dataa (681:681:681) (753:753:753)) - (PORT datab (282:282:282) (364:364:364)) - (PORT datad (645:645:645) (715:715:715)) - (IOPATH dataa combout (354:354:354) (349:349:349)) - (IOPATH datab combout (381:381:381) (380:380:380)) + (PORT datab (674:674:674) (739:739:739)) + (PORT datac (1157:1157:1157) (1216:1216:1216)) + (PORT datad (980:980:980) (1067:1067:1067)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -55345,7 +55140,7 @@ (INSTANCE ula_\|video_\|VGA_HS\~_Duplicate_1) (DELAY (ABSOLUTE - (PORT clk (1536:1536:1536) (1548:1548:1548)) + (PORT clk (1537:1537:1537) (1549:1549:1549)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -55359,11 +55154,11 @@ (INSTANCE ula_\|video_\|Selector0\~0) (DELAY (ABSOLUTE - (PORT dataa (1030:1030:1030) (1035:1035:1035)) - (PORT datab (228:228:228) (270:270:270)) - (PORT datad (571:571:571) (575:575:575)) - (IOPATH dataa combout (304:304:304) (308:308:308)) - (IOPATH datab combout (342:342:342) (342:342:342)) + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (575:575:575) (602:602:602)) + (PORT datad (326:326:326) (352:352:352)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -55375,7 +55170,7 @@ (DELAY (ABSOLUTE (PORT clk (1509:1509:1509) (1531:1531:1531)) - (PORT d (1715:1715:1715) (1721:1721:1721)) + (PORT d (1732:1732:1732) (1749:1749:1749)) (IOPATH (posedge clk) q (586:586:586) (589:589:589)) ) ) @@ -55389,7 +55184,7 @@ (INSTANCE ula_\|video_\|VGA_VS\~_Duplicate_1) (DELAY (ABSOLUTE - (PORT clk (1539:1539:1539) (1551:1551:1551)) + (PORT clk (1538:1538:1538) (1550:1550:1550)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -55403,11 +55198,11 @@ (INSTANCE ula_\|video_\|Selector1\~0) (DELAY (ABSOLUTE - (PORT dataa (620:620:620) (642:642:642)) - (PORT datab (1174:1174:1174) (1179:1179:1179)) - (PORT datad (691:691:691) (762:762:762)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH datab combout (304:304:304) (311:311:311)) + (PORT dataa (1099:1099:1099) (1106:1106:1106)) + (PORT datab (1453:1453:1453) (1488:1488:1488)) + (PORT datad (1108:1108:1108) (1129:1129:1129)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -55419,7 +55214,7 @@ (DELAY (ABSOLUTE (PORT clk (1507:1507:1507) (1529:1529:1529)) - (PORT d (1805:1805:1805) (1839:1839:1839)) + (PORT d (1320:1320:1320) (1349:1349:1349)) (IOPATH (posedge clk) q (586:586:586) (589:589:589)) ) ) @@ -55433,7 +55228,7 @@ (INSTANCE z80_\|memory_ifc_\|q1\~feeder) (DELAY (ABSOLUTE - (PORT datad (620:620:620) (667:667:667)) + (PORT datad (252:252:252) (325:325:325)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -55443,10 +55238,10 @@ (INSTANCE z80_\|memory_ifc_\|q1) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1553:1553:1553)) + (PORT clk (1523:1523:1523) (1537:1537:1537)) (PORT d (74:74:74) (91:91:91)) - (PORT clrn (1592:1592:1592) (1568:1568:1568)) - (PORT ena (1483:1483:1483) (1473:1473:1473)) + (PORT clrn (1567:1567:1567) (1548:1548:1548)) + (PORT ena (1722:1722:1722) (1695:1695:1695)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -55461,10 +55256,10 @@ (INSTANCE z80_\|memory_ifc_\|q2) (DELAY (ABSOLUTE - (PORT clk (1537:1537:1537) (1553:1553:1553)) + (PORT clk (1523:1523:1523) (1537:1537:1537)) (PORT asdata (560:560:560) (634:634:634)) - (PORT clrn (1592:1592:1592) (1568:1568:1568)) - (PORT ena (1483:1483:1483) (1473:1473:1473)) + (PORT clrn (1567:1567:1567) (1548:1548:1548)) + (PORT ena (1722:1722:1722) (1695:1695:1695)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) (IOPATH (negedge clrn) q (194:194:194) (194:194:194)) ) @@ -55479,7 +55274,7 @@ (INSTANCE z80_\|memory_ifc_\|nRFSH_out\~0) (DELAY (ABSOLUTE - (PORT datad (621:621:621) (666:666:666)) + (PORT datad (252:252:252) (326:326:326)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -55490,9 +55285,9 @@ (INSTANCE z80_\|memory_ifc_\|nM1_out) (DELAY (ABSOLUTE - (PORT datac (1282:1282:1282) (1346:1346:1346)) - (PORT datad (621:621:621) (669:669:669)) - (IOPATH datac combout (241:241:241) (241:241:241)) + (PORT dataa (2533:2533:2533) (2712:2712:2712)) + (PORT datad (251:251:251) (327:327:327)) + (IOPATH dataa combout (371:371:371) (376:376:376)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -55502,11 +55297,11 @@ (INSTANCE ula_\|beep\~0) (DELAY (ABSOLUTE - (PORT datab (1714:1714:1714) (1839:1839:1839)) - (PORT datac (3217:3217:3217) (3502:3502:3502)) - (PORT datad (1247:1247:1247) (1342:1342:1342)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datac combout (243:243:243) (242:242:242)) + (PORT dataa (3786:3786:3786) (4218:4218:4218)) + (PORT datab (1147:1147:1147) (1179:1179:1179)) + (PORT datad (1264:1264:1264) (1278:1278:1278)) + (IOPATH dataa combout (371:371:371) (376:376:376)) + (IOPATH datab combout (381:381:381) (380:380:380)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -55516,9 +55311,9 @@ (INSTANCE ula_\|beep) (DELAY (ABSOLUTE - (PORT clk (1515:1515:1515) (1529:1529:1529)) + (PORT clk (1510:1510:1510) (1524:1524:1524)) (PORT d (74:74:74) (91:91:91)) - (PORT ena (2564:2564:2564) (2572:2572:2572)) + (PORT ena (2464:2464:2464) (2441:2441:2441)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) ) diff --git a/spectrum.qsf b/spectrum.qsf index 09136a5..3edb3c4 100644 --- a/spectrum.qsf +++ b/spectrum.qsf @@ -462,4 +462,5 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to buzzer_out set_location_assignment PIN_B6 -to raw_loader_in set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to raw_loader_in set_global_assignment -name QIP_FILE ram_video.qip +set_global_assignment -name CDF_FILE output_files/spectrum.cdf set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/spectrum.sv b/spectrum.sv index 2ed0853..2438f1c 100644 --- a/spectrum.sv +++ b/spectrum.sv @@ -109,7 +109,6 @@ begin 3'b001: begin // Normally data supplied by the ULA D[7:0] = ula_data; - /* // Kempston joystick at the IO address 0x1F; active bits are high: // FIRE UP DOWN LEFT RIGHT @@ -129,7 +128,7 @@ end // ---------------------------------------------------- wire[7:0] rom_data; rom0 rom( - .clock(CLOCK_50), + .clock(clk_vram), .address(A), .q(rom_data) );